From deb378c818cfd7019884047f4f673d4d2136449b Mon Sep 17 00:00:00 2001 From: BaiRiDreamer <12110415@mail.sustech.edu.cn> Date: Wed, 8 Oct 2025 09:40:05 +0000 Subject: [PATCH] feat: add initial sk2decompile framework Implementation details to be completed --- sk2decompile/LLaMA-Factory/.dockerignore | 15 + sk2decompile/LLaMA-Factory/.env.local | 42 + sk2decompile/LLaMA-Factory/.gitattributes | 2 + .../LLaMA-Factory/.github/CODE_OF_CONDUCT.md | 128 + .../LLaMA-Factory/.github/CONTRIBUTING.md | 67 + .../.github/ISSUE_TEMPLATE/1-bug-report.yml | 61 + .../ISSUE_TEMPLATE/2-feature-request.yml | 41 + .../.github/ISSUE_TEMPLATE/config.yml | 8 + .../.github/PULL_REQUEST_TEMPLATE.md | 8 + .../LLaMA-Factory/.github/SECURITY.md | 7 + .../.github/workflows/docker.yml | 108 + .../.github/workflows/label_issue.yml | 32 + .../.github/workflows/publish.yml | 36 + .../LLaMA-Factory/.github/workflows/tests.yml | 107 + sk2decompile/LLaMA-Factory/.gitignore | 179 + .../LLaMA-Factory/.pre-commit-config.yaml | 28 + sk2decompile/LLaMA-Factory/README.md | 1 + .../data/norm2code-examples.jsonl | 20 + .../data/pseudo2norm-examples.jsonl | 20 + .../SK2DECOMPILE/train/norm2code-example.yaml | 39 + .../train/pseudo2norm-example.yaml | 39 + sk2decompile/Preprocess/format.py | 99 + sk2decompile/Preprocess/inf_type.py | 144 + .../Preprocess/normalize_src_basedonpseudo.py | 212 + sk2decompile/Preprocess/standard_c.txt | 1 + sk2decompile/README.md | 195 + .../data/humaneval_normsrcpseudo.json | 9641 +++ .../evaluation/data/mbpp_normsrcpseudo.json | 51138 ++++++++++++++++ sk2decompile/evaluation/evaluate_exe.py | 70 + sk2decompile/evaluation/evaluate_r2i.py | 83 + sk2decompile/evaluation/gpt_judge.py | 209 + sk2decompile/evaluation/inf_type.py | 170 + .../evaluation/metrics/cal_execute_rate.py | 102 + sk2decompile/evaluation/stack.yaml | 66 + sk2decompile/evaluation/template.txt | 74 + sk2decompile/verl/.gemini/config.yaml | 10 + sk2decompile/verl/.github/CODEOWNERS | 18 + .../verl/.github/PULL_REQUEST_TEMPLATE.md | 40 + sk2decompile/verl/.github/dependabot.yml | 9 + sk2decompile/verl/.github/workflows/README.md | 68 + .../verl/.github/workflows/check-pr-title.yml | 58 + .../workflows/checkpoint_converter.yml | 136 + .../verl/.github/workflows/cpu_unit_tests.yml | 83 + .../.github/workflows/disabled/e2e_prime.yml | 66 + sk2decompile/verl/.github/workflows/doc.yml | 100 + .../verl/.github/workflows/e2e_ascend.yml | 142 + .../verl/.github/workflows/e2e_dapo.yml | 112 + .../.github/workflows/e2e_eval_aime24.yml | 146 + .../.github/workflows/e2e_genrm_remote.yml | 105 + .../.github/workflows/e2e_ppo_trainer.yml | 424 + .../e2e_ppo_trainer_megatron_sglang.yml | 365 + .../e2e_ppo_trainer_megatron_vllm.yml | 367 + .../verl/.github/workflows/e2e_sft.yml | 148 + .../verl/.github/workflows/e2e_spin.yml | 89 + .../verl/.github/workflows/e2e_sppo.yml | 87 + .../verl/.github/workflows/gpu_unit_tests.yml | 100 + sk2decompile/verl/.github/workflows/model.yml | 144 + .../.github/workflows/pre-commit-full.yml | 30 + .../verl/.github/workflows/pre-commit.yml | 33 + .../verl/.github/workflows/sanity.yml | 97 + .../verl/.github/workflows/scorecard.yml | 66 + .../verl/.github/workflows/secrets_scan.yml | 22 + sk2decompile/verl/.github/workflows/sgl.yml | 142 + .../.github/workflows/type-coverage-check.yml | 29 + sk2decompile/verl/.github/workflows/vllm.yml | 124 + sk2decompile/verl/.gitignore | 126 + sk2decompile/verl/.pre-commit-config.yaml | 8 + sk2decompile/verl/.readthedocs.yaml | 19 + sk2decompile/verl/README.md | 1 + .../data/sk2decompile-rl-examples.jsonl | 100 + 70 files changed, 66806 insertions(+) create mode 100644 sk2decompile/LLaMA-Factory/.dockerignore create mode 100644 sk2decompile/LLaMA-Factory/.env.local create mode 100644 sk2decompile/LLaMA-Factory/.gitattributes create mode 100644 sk2decompile/LLaMA-Factory/.github/CODE_OF_CONDUCT.md create mode 100644 sk2decompile/LLaMA-Factory/.github/CONTRIBUTING.md create mode 100644 sk2decompile/LLaMA-Factory/.github/ISSUE_TEMPLATE/1-bug-report.yml create mode 100644 sk2decompile/LLaMA-Factory/.github/ISSUE_TEMPLATE/2-feature-request.yml create mode 100644 sk2decompile/LLaMA-Factory/.github/ISSUE_TEMPLATE/config.yml create mode 100644 sk2decompile/LLaMA-Factory/.github/PULL_REQUEST_TEMPLATE.md create mode 100644 sk2decompile/LLaMA-Factory/.github/SECURITY.md create mode 100644 sk2decompile/LLaMA-Factory/.github/workflows/docker.yml create mode 100644 sk2decompile/LLaMA-Factory/.github/workflows/label_issue.yml create mode 100644 sk2decompile/LLaMA-Factory/.github/workflows/publish.yml create mode 100644 sk2decompile/LLaMA-Factory/.github/workflows/tests.yml create mode 100644 sk2decompile/LLaMA-Factory/.gitignore create mode 100644 sk2decompile/LLaMA-Factory/.pre-commit-config.yaml create mode 100644 sk2decompile/LLaMA-Factory/README.md create mode 100644 sk2decompile/LLaMA-Factory/SK2DECOMPILE/data/norm2code-examples.jsonl create mode 100644 sk2decompile/LLaMA-Factory/SK2DECOMPILE/data/pseudo2norm-examples.jsonl create mode 100644 sk2decompile/LLaMA-Factory/SK2DECOMPILE/train/norm2code-example.yaml create mode 100644 sk2decompile/LLaMA-Factory/SK2DECOMPILE/train/pseudo2norm-example.yaml create mode 100644 sk2decompile/Preprocess/format.py create mode 100644 sk2decompile/Preprocess/inf_type.py create mode 100644 sk2decompile/Preprocess/normalize_src_basedonpseudo.py create mode 100644 sk2decompile/Preprocess/standard_c.txt create mode 100644 sk2decompile/README.md create mode 100644 sk2decompile/evaluation/data/humaneval_normsrcpseudo.json create mode 100644 sk2decompile/evaluation/data/mbpp_normsrcpseudo.json create mode 100644 sk2decompile/evaluation/evaluate_exe.py create mode 100644 sk2decompile/evaluation/evaluate_r2i.py create mode 100644 sk2decompile/evaluation/gpt_judge.py create mode 100644 sk2decompile/evaluation/inf_type.py create mode 100644 sk2decompile/evaluation/metrics/cal_execute_rate.py create mode 100644 sk2decompile/evaluation/stack.yaml create mode 100644 sk2decompile/evaluation/template.txt create mode 100644 sk2decompile/verl/.gemini/config.yaml create mode 100644 sk2decompile/verl/.github/CODEOWNERS create mode 100644 sk2decompile/verl/.github/PULL_REQUEST_TEMPLATE.md create mode 100644 sk2decompile/verl/.github/dependabot.yml create mode 100644 sk2decompile/verl/.github/workflows/README.md create mode 100644 sk2decompile/verl/.github/workflows/check-pr-title.yml create mode 100644 sk2decompile/verl/.github/workflows/checkpoint_converter.yml create mode 100644 sk2decompile/verl/.github/workflows/cpu_unit_tests.yml create mode 100644 sk2decompile/verl/.github/workflows/disabled/e2e_prime.yml create mode 100644 sk2decompile/verl/.github/workflows/doc.yml create mode 100644 sk2decompile/verl/.github/workflows/e2e_ascend.yml create mode 100644 sk2decompile/verl/.github/workflows/e2e_dapo.yml create mode 100644 sk2decompile/verl/.github/workflows/e2e_eval_aime24.yml create mode 100644 sk2decompile/verl/.github/workflows/e2e_genrm_remote.yml create mode 100644 sk2decompile/verl/.github/workflows/e2e_ppo_trainer.yml create mode 100644 sk2decompile/verl/.github/workflows/e2e_ppo_trainer_megatron_sglang.yml create mode 100644 sk2decompile/verl/.github/workflows/e2e_ppo_trainer_megatron_vllm.yml create mode 100644 sk2decompile/verl/.github/workflows/e2e_sft.yml create mode 100644 sk2decompile/verl/.github/workflows/e2e_spin.yml create mode 100644 sk2decompile/verl/.github/workflows/e2e_sppo.yml create mode 100644 sk2decompile/verl/.github/workflows/gpu_unit_tests.yml create mode 100644 sk2decompile/verl/.github/workflows/model.yml create mode 100644 sk2decompile/verl/.github/workflows/pre-commit-full.yml create mode 100644 sk2decompile/verl/.github/workflows/pre-commit.yml create mode 100644 sk2decompile/verl/.github/workflows/sanity.yml create mode 100644 sk2decompile/verl/.github/workflows/scorecard.yml create mode 100644 sk2decompile/verl/.github/workflows/secrets_scan.yml create mode 100644 sk2decompile/verl/.github/workflows/sgl.yml create mode 100644 sk2decompile/verl/.github/workflows/type-coverage-check.yml create mode 100644 sk2decompile/verl/.github/workflows/vllm.yml create mode 100644 sk2decompile/verl/.gitignore create mode 100644 sk2decompile/verl/.pre-commit-config.yaml create mode 100644 sk2decompile/verl/.readthedocs.yaml create mode 100644 sk2decompile/verl/README.md create mode 100644 sk2decompile/verl/SK2DECOMPILE/data/sk2decompile-rl-examples.jsonl diff --git a/sk2decompile/LLaMA-Factory/.dockerignore b/sk2decompile/LLaMA-Factory/.dockerignore new file mode 100644 index 0000000..a07ec86 --- /dev/null +++ b/sk2decompile/LLaMA-Factory/.dockerignore @@ -0,0 +1,15 @@ +.vscode +.git +.github +.venv +cache +docker +saves +hf_cache +ms_cache +om_cache +shared_data +output +.dockerignore +.gitattributes +.gitignore diff --git a/sk2decompile/LLaMA-Factory/.env.local b/sk2decompile/LLaMA-Factory/.env.local new file mode 100644 index 0000000..88ac8a4 --- /dev/null +++ b/sk2decompile/LLaMA-Factory/.env.local @@ -0,0 +1,42 @@ +# Note: actually we do not support .env, just for reference +# api +API_HOST= +API_PORT= +API_KEY= +API_MODEL_NAME= +API_VERBOSE= +FASTAPI_ROOT_PATH= +MAX_CONCURRENT= +# general +DISABLE_VERSION_CHECK= +FORCE_CHECK_IMPORTS= +ALLOW_EXTRA_ARGS= +LLAMAFACTORY_VERBOSITY= +USE_MODELSCOPE_HUB= +USE_OPENMIND_HUB= +USE_RAY= +RECORD_VRAM= +OPTIM_TORCH= +NPU_JIT_COMPILE= +# torchrun +FORCE_TORCHRUN= +MASTER_ADDR= +MASTER_PORT= +NNODES= +NODE_RANK= +NPROC_PER_NODE= +# wandb +WANDB_DISABLED= +WANDB_PROJECT= +WANDB_API_KEY= +# gradio ui +GRADIO_SHARE= +GRADIO_SERVER_NAME= +GRADIO_SERVER_PORT= +GRADIO_ROOT_PATH= +GRADIO_IPV6= +# setup +ENABLE_SHORT_CONSOLE= +# reserved (do not use) +LLAMABOARD_ENABLED= +LLAMABOARD_WORKDIR= diff --git a/sk2decompile/LLaMA-Factory/.gitattributes b/sk2decompile/LLaMA-Factory/.gitattributes new file mode 100644 index 0000000..dfe0770 --- /dev/null +++ b/sk2decompile/LLaMA-Factory/.gitattributes @@ -0,0 +1,2 @@ +# Auto detect text files and perform LF normalization +* text=auto diff --git a/sk2decompile/LLaMA-Factory/.github/CODE_OF_CONDUCT.md b/sk2decompile/LLaMA-Factory/.github/CODE_OF_CONDUCT.md new file mode 100644 index 0000000..c2035ce --- /dev/null +++ b/sk2decompile/LLaMA-Factory/.github/CODE_OF_CONDUCT.md @@ -0,0 +1,128 @@ +# Contributor Covenant Code of Conduct + +## Our Pledge + +We as members, contributors, and leaders pledge to make participation in our +community a harassment-free experience for everyone, regardless of age, body +size, visible or invisible disability, ethnicity, sex characteristics, gender +identity and expression, level of experience, education, socio-economic status, +nationality, personal appearance, race, religion, or sexual identity +and orientation. + +We pledge to act and interact in ways that contribute to an open, welcoming, +diverse, inclusive, and healthy community. + +## Our Standards + +Examples of behavior that contributes to a positive environment for our +community include: + +* Demonstrating empathy and kindness toward other people +* Being respectful of differing opinions, viewpoints, and experiences +* Giving and gracefully accepting constructive feedback +* Accepting responsibility and apologizing to those affected by our mistakes, + and learning from the experience +* Focusing on what is best not just for us as individuals, but for the + overall community + +Examples of unacceptable behavior include: + +* The use of sexualized language or imagery, and sexual attention or + advances of any kind +* Trolling, insulting or derogatory comments, and personal or political attacks +* Public or private harassment +* Publishing others' private information, such as a physical or email + address, without their explicit permission +* Other conduct which could reasonably be considered inappropriate in a + professional setting + +## Enforcement Responsibilities + +Community leaders are responsible for clarifying and enforcing our standards of +acceptable behavior and will take appropriate and fair corrective action in +response to any behavior that they deem inappropriate, threatening, offensive, +or harmful. + +Community leaders have the right and responsibility to remove, edit, or reject +comments, commits, code, wiki edits, issues, and other contributions that are +not aligned to this Code of Conduct, and will communicate reasons for moderation +decisions when appropriate. + +## Scope + +This Code of Conduct applies within all community spaces, and also applies when +an individual is officially representing the community in public spaces. +Examples of representing our community include using an official e-mail address, +posting via an official social media account, or acting as an appointed +representative at an online or offline event. + +## Enforcement + +Instances of abusive, harassing, or otherwise unacceptable behavior may be +reported to the community leaders responsible for enforcement at +`hoshihiyouga AT gmail DOT com`. +All complaints will be reviewed and investigated promptly and fairly. + +All community leaders are obligated to respect the privacy and security of the +reporter of any incident. + +## Enforcement Guidelines + +Community leaders will follow these Community Impact Guidelines in determining +the consequences for any action they deem in violation of this Code of Conduct: + +### 1. Correction + +**Community Impact**: Use of inappropriate language or other behavior deemed +unprofessional or unwelcome in the community. + +**Consequence**: A private, written warning from community leaders, providing +clarity around the nature of the violation and an explanation of why the +behavior was inappropriate. A public apology may be requested. + +### 2. Warning + +**Community Impact**: A violation through a single incident or series +of actions. + +**Consequence**: A warning with consequences for continued behavior. No +interaction with the people involved, including unsolicited interaction with +those enforcing the Code of Conduct, for a specified period of time. This +includes avoiding interactions in community spaces as well as external channels +like social media. Violating these terms may lead to a temporary or +permanent ban. + +### 3. Temporary Ban + +**Community Impact**: A serious violation of community standards, including +sustained inappropriate behavior. + +**Consequence**: A temporary ban from any sort of interaction or public +communication with the community for a specified period of time. No public or +private interaction with the people involved, including unsolicited interaction +with those enforcing the Code of Conduct, is allowed during this period. +Violating these terms may lead to a permanent ban. + +### 4. Permanent Ban + +**Community Impact**: Demonstrating a pattern of violation of community +standards, including sustained inappropriate behavior, harassment of an +individual, or aggression toward or disparagement of classes of individuals. + +**Consequence**: A permanent ban from any sort of public interaction within +the community. + +## Attribution + +This Code of Conduct is adapted from the [Contributor Covenant][homepage], +version 2.0, available at +https://www.contributor-covenant.org/version/2/0/code_of_conduct.html. + +Community Impact Guidelines were inspired by [Mozilla's code of conduct +enforcement ladder](https://github.com/mozilla/diversity). + +[homepage]: https://www.contributor-covenant.org + +For answers to common questions about this code of conduct, see the FAQ at +https://www.contributor-covenant.org/faq. Translations are available at +https://www.contributor-covenant.org/translations. diff --git a/sk2decompile/LLaMA-Factory/.github/CONTRIBUTING.md b/sk2decompile/LLaMA-Factory/.github/CONTRIBUTING.md new file mode 100644 index 0000000..507d666 --- /dev/null +++ b/sk2decompile/LLaMA-Factory/.github/CONTRIBUTING.md @@ -0,0 +1,67 @@ +# Contributing to LLaMA Factory + +Everyone is welcome to contribute, and we value everybody's contribution. Code contributions are not the only way to help the community. Answering questions, helping others, and improving the documentation are also immensely valuable. + +It also helps us if you spread the word! Reference the library in blog posts about the awesome projects it made possible, shout out on Twitter every time it has helped you, or simply ⭐️ the repository to say thank you. + +However you choose to contribute, please be mindful and respect our [code of conduct](CODE_OF_CONDUCT.md). + +**This guide was heavily inspired by [transformers guide to contributing](https://github.com/huggingface/transformers/blob/main/CONTRIBUTING.md).** + +## Ways to contribute + +There are several ways you can contribute to LLaMA Factory: + +* Fix outstanding issues with the existing code. +* Submit issues related to bugs or desired new features. +* Contribute to the examples or to the documentation. + +### Style guide + +LLaMA Factory follows the [Google Python Style Guide](https://google.github.io/styleguide/pyguide.html), check it for details. + +### Create a Pull Request + +1. Fork the [repository](https://github.com/hiyouga/LLaMA-Factory) by clicking on the [Fork](https://github.com/hiyouga/LLaMA-Factory/fork) button on the repository's page. This creates a copy of the code under your GitHub user account. + +2. Clone your fork to your local disk, and add the base repository as a remote: + +```bash +git clone git@github.com:[username]/LLaMA-Factory.git +cd LLaMA-Factory +git remote add upstream https://github.com/hiyouga/LLaMA-Factory.git +``` + +3. Create a new branch to hold your development changes: + +```bash +git checkout -b dev_your_branch +``` + +4. Set up a development environment by running the following command in a virtual environment: + +```bash +pip install -e ".[dev]" +``` + +If LLaMA Factory was already installed in the virtual environment, remove it with `pip uninstall llamafactory` before reinstalling it in editable mode with the -e flag. + +5. Check code before commit: + +```bash +make commit +make style && make quality +make test +``` + +6. Submit changes: + +```bash +git add . +git commit -m "commit message" +git fetch upstream +git rebase upstream/main +git push -u origin dev_your_branch +``` + +7. Create a merge request from your branch `dev_your_branch` at [origin repo](https://github.com/hiyouga/LLaMA-Factory). diff --git a/sk2decompile/LLaMA-Factory/.github/ISSUE_TEMPLATE/1-bug-report.yml b/sk2decompile/LLaMA-Factory/.github/ISSUE_TEMPLATE/1-bug-report.yml new file mode 100644 index 0000000..a08596f --- /dev/null +++ b/sk2decompile/LLaMA-Factory/.github/ISSUE_TEMPLATE/1-bug-report.yml @@ -0,0 +1,61 @@ +name: "\U0001F41B Bug / help" +description: Create a report to help us improve the LLaMA Factory +labels: ["bug", "pending"] +body: + - type: markdown + attributes: + value: | + Issues included in **[FAQs](https://github.com/hiyouga/LLaMA-Factory/issues/4614)** or those with **insufficient** information may be closed without a response. + 已经包含在 **[常见问题](https://github.com/hiyouga/LLaMA-Factory/issues/4614)** 内或提供信息**不完整**的 issues 可能不会被回复。 + + - type: markdown + attributes: + value: | + Please do not create issues that are not related to framework bugs under this category, use **[Discussions](https://github.com/hiyouga/LLaMA-Factory/discussions/categories/q-a)** instead. + 请勿在此分类下创建和框架 bug 无关的 issues，训练问题求助请使用 **[讨论区](https://github.com/hiyouga/LLaMA-Factory/discussions/categories/q-a)**。 + + - type: checkboxes + id: reminder + attributes: + label: Reminder + description: | + Please ensure you have read the above rules carefully and searched the existing issues (including FAQs). + 请确保您已经认真阅读了上述规则并且搜索过现有的 issues（包括常见问题）。 + + options: + - label: I have read the above rules and searched the existing issues. + required: true + + - type: textarea + id: system-info + validations: + required: true + attributes: + label: System Info + description: | + Please share your system info with us. You can run the command **llamafactory-cli env** and copy-paste its output below. + 请提供您的系统信息。您可以在命令行运行 **llamafactory-cli env** 并将其输出复制到该文本框中。 + + placeholder: llamafactory version, platform, python version, ... + + - type: textarea + id: reproduction + validations: + required: true + attributes: + label: Reproduction + description: | + Please provide entry arguments, error messages and stack traces that reproduces the problem. + 请提供入口参数，错误日志以及异常堆栈以便于我们复现问题。 + + value: | + ```text + Put your message here. + ``` + + - type: textarea + id: others + validations: + required: false + attributes: + label: Others diff --git a/sk2decompile/LLaMA-Factory/.github/ISSUE_TEMPLATE/2-feature-request.yml b/sk2decompile/LLaMA-Factory/.github/ISSUE_TEMPLATE/2-feature-request.yml new file mode 100644 index 0000000..5d72271 --- /dev/null +++ b/sk2decompile/LLaMA-Factory/.github/ISSUE_TEMPLATE/2-feature-request.yml @@ -0,0 +1,41 @@ +name: "\U0001F680 Feature request" +description: Submit a request for a new feature +labels: ["enhancement", "pending"] +body: + - type: markdown + attributes: + value: | + Please do not create issues that are not related to new features under this category. + 请勿在此分类下创建和新特性无关的 issues。 + + - type: checkboxes + id: reminder + attributes: + label: Reminder + description: | + Please ensure you have read the above rules carefully and searched the existing issues. + 请确保您已经认真阅读了上述规则并且搜索过现有的 issues。 + + options: + - label: I have read the above rules and searched the existing issues. + required: true + + - type: textarea + id: description + validations: + required: true + attributes: + label: Description + description: | + A clear and concise description of the feature proposal. + 请详细描述您希望加入的新功能特性。 + + - type: textarea + id: contribution + validations: + required: false + attributes: + label: Pull Request + description: | + Have you already created the relevant PR and submitted the code? + 您是否已经创建了相关 PR 并提交了代码？ diff --git a/sk2decompile/LLaMA-Factory/.github/ISSUE_TEMPLATE/config.yml b/sk2decompile/LLaMA-Factory/.github/ISSUE_TEMPLATE/config.yml new file mode 100644 index 0000000..1a77196 --- /dev/null +++ b/sk2decompile/LLaMA-Factory/.github/ISSUE_TEMPLATE/config.yml @@ -0,0 +1,8 @@ +blank_issues_enabled: false +contact_links: + - name: 📚 FAQs | 常见问题 + url: https://github.com/hiyouga/LLaMA-Factory/issues/4614 + about: Reading in advance is recommended | 建议提前阅读 + - name: Discussions | 讨论区 + url: https://github.com/hiyouga/LLaMA-Factory/discussions + about: Please ask fine-tuning questions here | 请在这里讨论训练问题 diff --git a/sk2decompile/LLaMA-Factory/.github/PULL_REQUEST_TEMPLATE.md b/sk2decompile/LLaMA-Factory/.github/PULL_REQUEST_TEMPLATE.md new file mode 100644 index 0000000..d23d6be --- /dev/null +++ b/sk2decompile/LLaMA-Factory/.github/PULL_REQUEST_TEMPLATE.md @@ -0,0 +1,8 @@ +# What does this PR do? + +Fixes # (issue) + +## Before submitting + +- [ ] Did you read the [contributor guideline](https://github.com/hiyouga/LLaMA-Factory/blob/main/.github/CONTRIBUTING.md)? +- [ ] Did you write any new necessary tests? diff --git a/sk2decompile/LLaMA-Factory/.github/SECURITY.md b/sk2decompile/LLaMA-Factory/.github/SECURITY.md new file mode 100644 index 0000000..d34728e --- /dev/null +++ b/sk2decompile/LLaMA-Factory/.github/SECURITY.md @@ -0,0 +1,7 @@ +# Reporting Security Issues + +To report a security issue, please use the GitHub Security Advisory ["Report a Vulnerability"](https://github.com/hiyouga/LLaMA-Factory/security/advisories/new) tab. + +We will send a response indicating the next steps in handling your report. After the initial reply to your report, the security team will keep you informed of the progress towards a fix and full announcement, and may ask for additional information or guidance. + +Report security bugs in third-party modules to the person or team maintaining the module. diff --git a/sk2decompile/LLaMA-Factory/.github/workflows/docker.yml b/sk2decompile/LLaMA-Factory/.github/workflows/docker.yml new file mode 100644 index 0000000..f5e099f --- /dev/null +++ b/sk2decompile/LLaMA-Factory/.github/workflows/docker.yml @@ -0,0 +1,108 @@ +name: docker + +on: + workflow_dispatch: + push: + branches: + - "main" + paths: + - "**/*.py" + - "requirements.txt" + - "docker/**" + - ".github/workflows/*.yml" + pull_request: + branches: + - "main" + paths: + - "**/*.py" + - "requirements.txt" + - "docker/**" + - ".github/workflows/*.yml" + +jobs: + build: + strategy: + fail-fast: false + matrix: + device: + - "cuda" + - "npu" + + runs-on: ubuntu-latest + + concurrency: + group: ${{ github.workflow }}-${{ github.ref }}-${{ matrix.device }} + cancel-in-progress: ${{ github.ref != 'refs/heads/main' }} + + environment: + name: docker + url: https://hub.docker.com/r/hiyouga/llamafactory + + steps: + - name: Free up disk space + uses: jlumbroso/free-disk-space@54081f138730dfa15788a46383842cd2f914a1be # v1.3.1 + with: + tool-cache: true + docker-images: false + + - name: Checkout + uses: actions/checkout@v4 + + - name: Set up Python + uses: actions/setup-python@v5 + with: + python-version: "3.9" + + - name: Get llamafactory version + id: version + run: | + echo "tag=$(python setup.py --version | sed 's/\.dev0//')" >> "$GITHUB_OUTPUT" + + - name: Set up Docker Buildx + uses: docker/setup-buildx-action@v3 + + - name: Login to Docker Hub + if: ${{ github.event_name != 'pull_request' }} + uses: docker/login-action@v3 + with: + username: ${{ vars.DOCKERHUB_USERNAME }} + password: ${{ secrets.DOCKERHUB_TOKEN }} + + - name: Login to Quay + if: ${{ github.event_name != 'pull_request' && matrix.device == 'npu' }} + uses: docker/login-action@v3 + with: + registry: quay.io + username: ${{ vars.QUAY_ASCEND_USERNAME }} + password: ${{ secrets.QUAY_ASCEND_TOKEN }} + + - name: Build and push Docker image (CUDA) + if: ${{ matrix.device == 'cuda' }} + uses: docker/build-push-action@v6 + with: + context: . + file: ./docker/docker-cuda/Dockerfile + build-args: | + EXTRAS=metrics,deepspeed,liger-kernel + push: ${{ github.event_name != 'pull_request' }} + tags: | + docker.io/hiyouga/llamafactory:latest + docker.io/hiyouga/llamafactory:${{ steps.version.outputs.tag }} + cache-from: type=gha + cache-to: type=gha,mode=max + + - name: Build and push Docker image (NPU) + if: ${{ matrix.device == 'npu' }} + uses: docker/build-push-action@v6 + with: + context: . + platforms: linux/amd64,linux/arm64 + file: ./docker/docker-npu/Dockerfile + push: ${{ github.event_name != 'pull_request' }} + tags: | + docker.io/hiyouga/llamafactory:latest-npu-a2 + docker.io/hiyouga/llamafactory:${{ steps.version.outputs.tag }}-npu-a2 + quay.io/ascend/llamafactory:latest-npu-a2 + quay.io/ascend/llamafactory:${{ steps.version.outputs.tag }}-npu-a2 + cache-from: type=gha + cache-to: type=gha,mode=max diff --git a/sk2decompile/LLaMA-Factory/.github/workflows/label_issue.yml b/sk2decompile/LLaMA-Factory/.github/workflows/label_issue.yml new file mode 100644 index 0000000..3d0424c --- /dev/null +++ b/sk2decompile/LLaMA-Factory/.github/workflows/label_issue.yml @@ -0,0 +1,32 @@ +name: label_issue + +on: + issues: + types: + - opened + +jobs: + label_issue: + runs-on: ubuntu-latest + + permissions: + issues: write + + steps: + - env: + GH_TOKEN: ${{ secrets.GITHUB_TOKEN }} + ISSUE_URL: ${{ github.event.issue.html_url }} + ISSUE_TITLE: ${{ github.event.issue.title }} + run: | + LABEL="" + NPU_KEYWORDS=(npu huawei ascend 华为 昇腾 910) + ISSUE_TITLE_LOWER=$(echo $ISSUE_TITLE | tr '[:upper:]' '[:lower:]') + for KEYWORD in ${NPU_KEYWORDS[@]}; do + if [[ $ISSUE_TITLE_LOWER == *$KEYWORD* ]] && [[ $ISSUE_TITLE_LOWER != *input* ]]; then + LABEL="npu" + break + fi + done + if [ -n "$LABEL" ]; then + gh issue edit $ISSUE_URL --add-label $LABEL + fi diff --git a/sk2decompile/LLaMA-Factory/.github/workflows/publish.yml b/sk2decompile/LLaMA-Factory/.github/workflows/publish.yml new file mode 100644 index 0000000..c3f729a --- /dev/null +++ b/sk2decompile/LLaMA-Factory/.github/workflows/publish.yml @@ -0,0 +1,36 @@ +name: publish + +on: + workflow_dispatch: + release: + types: + - published + +jobs: + publish: + name: Upload release to PyPI + + runs-on: ubuntu-latest + + environment: + name: release + url: https://pypi.org/p/llamafactory + + permissions: + id-token: write + + steps: + - name: Checkout + uses: actions/checkout@v4 + + - name: Set up Python + uses: actions/setup-python@v5 + with: + python-version: "3.9" + + - name: Build package + run: | + make build + + - name: Publish package + uses: pypa/gh-action-pypi-publish@release/v1 diff --git a/sk2decompile/LLaMA-Factory/.github/workflows/tests.yml b/sk2decompile/LLaMA-Factory/.github/workflows/tests.yml new file mode 100644 index 0000000..e7cddda --- /dev/null +++ b/sk2decompile/LLaMA-Factory/.github/workflows/tests.yml @@ -0,0 +1,107 @@ +name: tests + +on: + workflow_dispatch: + push: + branches: + - "main" + paths: + - "**/*.py" + - "requirements.txt" + - ".github/workflows/*.yml" + pull_request: + branches: + - "main" + paths: + - "**/*.py" + - "requirements.txt" + - ".github/workflows/*.yml" + +jobs: + tests: + strategy: + fail-fast: false + matrix: + python: + - "3.9" + - "3.10" + - "3.11" + - "3.12" + os: + - "ubuntu-latest" + - "windows-latest" + - "macos-13" + transformers: + - null + include: # test backward compatibility + - python: "3.9" + os: "ubuntu-latest" + transformers: "4.49.0" + - python: "3.9" + os: "ubuntu-latest" + transformers: "4.51.0" + - python: "3.9" + os: "ubuntu-latest" + transformers: "4.53.0" + + runs-on: ${{ matrix.os }} + + concurrency: + group: ${{ github.workflow }}-${{ github.ref }}-${{ matrix.os }}-${{ matrix.python }}-${{ matrix.transformers }} + cancel-in-progress: ${{ github.ref != 'refs/heads/main' }} + + env: + HF_TOKEN: ${{ secrets.HF_TOKEN }} + OS_NAME: ${{ matrix.os }} + + steps: + - name: Checkout + uses: actions/checkout@v4 + + - name: Set up Python + uses: actions/setup-python@v5 + with: + python-version: ${{ matrix.python }} + cache: "pip" + cache-dependency-path: "**/requirements*.txt" + + - name: Install dependencies + run: | + python -m pip install --upgrade pip + python -m pip install ".[torch,dev]" + + - name: Install transformers + if: ${{ matrix.transformers }} + run: | + python -m pip install "transformers==${{ matrix.transformers }}" + + - name: Install transformers to avoid mac os ci errors + if: ${{ matrix.os == 'macos-13' }} + run: | + python -m pip install "transformers<=4.51.3" + + - name: Cache files + id: hf-hub-cache + uses: actions/cache@v4 + with: + path: ${{ runner.temp }}/huggingface + key: huggingface-${{ matrix.os }}-${{ matrix.python }}-${{ matrix.transformers }}-${{ hashFiles('tests/version.txt') }} + + - name: Check quality + run: | + make style && make quality + + - name: Check license + run: | + make license + + - name: Check build + run: | + make build + + - name: Test with pytest + run: | + make test + env: + HF_HOME: ${{ runner.temp }}/huggingface + HF_HUB_OFFLINE: "${{ steps.hf-hub-cache.outputs.cache-hit == 'true' && '1' || '0' }}" diff --git a/sk2decompile/LLaMA-Factory/.gitignore b/sk2decompile/LLaMA-Factory/.gitignore new file mode 100644 index 0000000..0a3a47b --- /dev/null +++ b/sk2decompile/LLaMA-Factory/.gitignore @@ -0,0 +1,179 @@ +# Byte-compiled / optimized / DLL files +__pycache__/ +*.py[cod] +*$py.class + +# C extensions +*.so + +# Distribution / packaging +.Python +build/ +develop-eggs/ +dist/ +downloads/ +eggs/ +.eggs/ +lib/ +lib64/ +parts/ +sdist/ +var/ +wheels/ +share/python-wheels/ +*.egg-info/ +.installed.cfg +*.egg +MANIFEST + +# PyInstaller +# Usually these files are written by a python script from a template +# before PyInstaller builds the exe, so as to inject date/other infos into it. +*.manifest +*.spec + +# Installer logs +pip-log.txt +pip-delete-this-directory.txt + +# Unit test / coverage reports +htmlcov/ +.tox/ +.nox/ +.coverage +.coverage.* +.cache +nosetests.xml +coverage.xml +*.cover +*.py,cover +.hypothesis/ +.pytest_cache/ +cover/ + +# Translations +*.mo +*.pot + +# Django stuff: +*.log +local_settings.py +db.sqlite3 +db.sqlite3-journal + +# Flask stuff: +instance/ +.webassets-cache + +# Scrapy stuff: +.scrapy + +# Sphinx documentation +docs/_build/ + +# PyBuilder +.pybuilder/ +target/ + +# Jupyter Notebook +.ipynb_checkpoints + +# IPython +profile_default/ +ipython_config.py + +# pyenv +# For a library or package, you might want to ignore these files since the code is +# intended to run in multiple environments; otherwise, check them in: +# .python-version + +# pipenv +# According to pypa/pipenv#598, it is recommended to include Pipfile.lock in version control. +# However, in case of collaboration, if having platform-specific dependencies or dependencies +# having no cross-platform support, pipenv may install dependencies that don't work, or not +# install all needed dependencies. +#Pipfile.lock + +# poetry +# Similar to Pipfile.lock, it is generally recommended to include poetry.lock in version control. +# This is especially recommended for binary packages to ensure reproducibility, and is more +# commonly ignored for libraries. +# https://python-poetry.org/docs/basic-usage/#commit-your-poetrylock-file-to-version-control +#poetry.lock + +# pdm +# Similar to Pipfile.lock, it is generally recommended to include pdm.lock in version control. +#pdm.lock +# pdm stores project-wide configurations in .pdm.toml, but it is recommended to not include it +# in version control. +# https://pdm.fming.dev/#use-with-ide +.pdm.toml + +# PEP 582; used by e.g. github.com/David-OConnor/pyflow and github.com/pdm-project/pdm +__pypackages__/ + +# Celery stuff +celerybeat-schedule +celerybeat.pid + +# SageMath parsed files +*.sage.py + +# Environments +.env +.venv +env/ +venv/ +ENV/ +env.bak/ +venv.bak/ + +# Spyder project settings +.spyderproject +.spyproject + +# Rope project settings +.ropeproject + +# mkdocs documentation +/site + +# mypy +.mypy_cache/ +.dmypy.json +dmypy.json + +# Pyre type checker +.pyre/ + +# pytype static type analyzer +.pytype/ + +# Cython debug symbols +cython_debug/ + +# PyCharm +# JetBrains specific template is maintained in a separate JetBrains.gitignore that can +# be found at https://github.com/github/gitignore/blob/main/Global/JetBrains.gitignore +# and can be added to the global gitignore or merged into this file. For a more nuclear +# option (not recommended) you can uncomment the following to ignore the entire idea folder. +.idea/ + +# vscode +.vscode/ + +# uv +uv.lock + +# custom .gitignore +hf_cache/ +ms_cache/ +om_cache/ +cache/ +config/ +saves/ +output/ +wandb/ +swanlog/ +generated_predictions.jsonl +predictions_score.json diff --git a/sk2decompile/LLaMA-Factory/.pre-commit-config.yaml b/sk2decompile/LLaMA-Factory/.pre-commit-config.yaml new file mode 100644 index 0000000..cbe361e --- /dev/null +++ b/sk2decompile/LLaMA-Factory/.pre-commit-config.yaml @@ -0,0 +1,28 @@ +repos: +- repo: https://github.com/pre-commit/pre-commit-hooks + rev: v5.0.0 + hooks: + - id: check-ast + - id: check-added-large-files + args: ['--maxkb=25000'] + - id: check-merge-conflict + - id: check-yaml + - id: debug-statements + - id: end-of-file-fixer + - id: trailing-whitespace + args: [--markdown-linebreak-ext=md] + - id: no-commit-to-branch + args: ['--branch', 'main'] + +- repo: https://github.com/asottile/pyupgrade + rev: v3.17.0 + hooks: + - id: pyupgrade + args: [--py38-plus] + +- repo: https://github.com/astral-sh/ruff-pre-commit + rev: v0.6.9 + hooks: + - id: ruff + args: [--fix] + - id: ruff-format diff --git a/sk2decompile/LLaMA-Factory/README.md b/sk2decompile/LLaMA-Factory/README.md new file mode 100644 index 0000000..3775d44 --- /dev/null +++ b/sk2decompile/LLaMA-Factory/README.md @@ -0,0 +1 @@ +Waitting to do \ No newline at end of file diff --git a/sk2decompile/LLaMA-Factory/SK2DECOMPILE/data/norm2code-examples.jsonl b/sk2decompile/LLaMA-Factory/SK2DECOMPILE/data/norm2code-examples.jsonl new file mode 100644 index 0000000..a5cc5f4 --- /dev/null +++ b/sk2decompile/LLaMA-Factory/SK2DECOMPILE/data/norm2code-examples.jsonl @@ -0,0 +1,20 @@ +{"instruction": "", "input": "# This is the normalized code:\nstatic bool func1(struct type1 *var1, struct type2 *var2, const char *var3) {\n if (var2->field1->field2 & var4) {\n if (func2(\"RTSP/\", var3, 5)) return TRUE;\n return FALSE;\n }\n return func3(var1, var3);\n}\n# What is the source code?\n", "output": "static bool checkprotoprefix(struct SessionHandle *data,\n struct connectdata *conn, const char *s) {\n#ifndef CURL_DISABLE_RTSP\n if (conn->handler->protocol & CURLPROTO_RTSP) return checkrtspprefix(data, s);\n#else\n (void)conn;\n#endif\n return checkhttpprefix(data, s);\n}", "system": ""} +{"instruction": "", "input": "# This is the normalized code:\nstatic type1 func1(type2 *var1, type3 *var2) {\n type4 *var3;\n int var4;\n var4 = _dbus_string_get_length(var2);\n if (!_dbus_string_append_byte(var2, 'a')) goto oom;\n if (!_dbus_string_append(var2, \"{i\")) goto oom;\n var3 = _dbus_list_get_first(&var1->field1);\n if (var3->field2->field3) {\n if (!var3->field2->field3(var3, var2)) goto oom;\n } else {\n if (!_dbus_string_append_byte(var2, var3->field2->field4)) goto oom;\n }\n if (!_dbus_string_append_byte(var2, '}')) goto oom;\n return TRUE;\noom:\n _dbus_string_set_length(var2, var4);\n return FALSE;\n}\n# What is the source code?\n", "output": "static dbus_bool_t dict_build_signature(TestTypeNode *node, DBusString *str) {\n TestTypeNodeContainer *container = (TestTypeNodeContainer *)node;\n int orig_len;\n orig_len = _dbus_string_get_length(str);\n if (!_dbus_string_append_byte(str, DBUS_TYPE_ARRAY)) goto oom;\n if (!_dbus_string_append(\n str, DBUS_DICT_ENTRY_BEGIN_CHAR_AS_STRING DBUS_TYPE_INT32_AS_STRING))\n goto oom;\n if (!node_build_signature(_dbus_list_get_first(&container->children), str))\n goto oom;\n if (!_dbus_string_append_byte(str, DBUS_DICT_ENTRY_END_CHAR)) goto oom;\n return TRUE;\noom:\n _dbus_string_set_length(str, orig_len);\n return FALSE;\n}", "system": ""} +{"instruction": "", "input": "# This is the normalized code:\nint compiler_addglobal(type1 *var1, type2 *var2, type3 *var3) {\n int var4 = compiler_findglobal(var1, var3, NULL);\n if (var4 == -1) {\n var4 = program_addglobal(var1->field1, var3);\n type3 *var5 = program_internsymbol(var1->field1, var3);\n if (dictionary_insert(&var1->field2, var5, func1(var4))) {\n debugannotation_setglobal(&var1->field1->field3, var4, var3);\n }\n }\n return var4;\n}\n# What is the source code?\n", "output": "globalindx compiler_addglobal(compiler *c, syntaxtreenode *node, value symbol) {\n globalindx indx = compiler_findglobal(c, symbol, false);\n if (indx == GLOBAL_UNALLOCATED) {\n indx = program_addglobal(c->out, symbol);\n value key = program_internsymbol(c->out, symbol);\n if (dictionary_insert(&c->globals, key, MORPHO_INTEGER(indx))) {\n debugannotation_setglobal(&c->out->annotations, indx, symbol);\n }\n }\n return indx;\n}", "system": ""} +{"instruction": "", "input": "# This is the normalized code:\nstatic int func1(int var1, int var2, int var3) {\n int var4 = 0;\n int var5;\n unsigned char *var6 = var7;\n unsigned char *var8 = var9;\n for (var5 = 0; var5 < var1 * var2; var5++) {\n if (var6[var5] != var8[var5]) {\n if (var6[var5] > var8[var5]) {\n if (var6[var5] - var3 < var8[var5]) {\n var6[var5] = var8[var5];\n } else {\n var6[var5] -= var3;\n }\n } else {\n if (var6[var5] + var3 > var8[var5]) {\n var6[var5] = var8[var5];\n } else {\n var6[var5] += var3;\n }\n }\n var4 = 1;\n }\n }\n return !var4;\n}\n# What is the source code?\n", "output": "int wipe_doColorXForm(int width, int height, int ticks) {\n boolean changed;\n pixel_t* w;\n pixel_t* e;\n int newval;\n changed = false;\n w = wipe_scr;\n e = wipe_scr_end;\n while (w != wipe_scr + width * height) {\n if (*w != *e) {\n if (*w > *e) {\n newval = *w - ticks;\n if (newval < *e)\n *w = *e;\n else\n *w = newval;\n changed = true;\n } else if (*w < *e) {\n newval = *w + ticks;\n if (newval > *e)\n *w = *e;\n else\n *w = newval;\n changed = true;\n }\n }\n w++;\n e++;\n }\n return !changed;\n}", "system": ""} +{"instruction": "", "input": "# This is the normalized code:\nsize_t func1(const unsigned char *var1, const unsigned char *var2, size_t var3) {\n size_t var4, var5;\n var4 = (((size_t)var2) + 15) & ~15;\n var5 = var4 - (size_t)var2;\n if (var5 < var3) {\n for (size_t var6 = 0; var6 < var5; var6++) {\n unsigned char var7 = var2[var6];\n if (var7 < 128 && (var1[var7 >> 3] & (1 << (var7 & 7)))) return var6;\n }\n } else {\n var5 = var3;\n }\n size_t var8 = var3 - var5;\n if (var8 >= 16) {\n for (size_t var6 = 0; var6 < var8 / 16; var6++) {\n unsigned char var9[16];\n for (size_t var10 = 0; var10 < 16; var10++) {\n unsigned char var7 = var2[var6 * 16 + var10];\n var9[var10] = var7 < 128 ? var1[var7 >> 3] & (1 << (var7 & 7)) : 0;\n }\n for (size_t var10 = 0; var10 < 16; var10++) {\n if (var9[var10] == 0) continue;\n unsigned char var7 = var2[var6 * 16 + var10];\n if (var7 < 128) return var6 * 16 + var10;\n }\n }\n var5 = var8 & ~15;\n }\n for (size_t var6 = var5; var6 < var3; var6++) {\n unsigned char var7 = var2[var6];\n if (var7 < 128 && (var1[var7 >> 3] & (1 << (var7 & 7)))) return var6;\n }\n return var3;\n}\n# What is the source code?\n", "output": "size_t find_FildeshMascii(const FildeshMascii* mascii, const char* s,\n size_t n) {\n size_t i;\n const FildeshMascii* t =\n (const FildeshMascii*)(((uintptr_t)s + 15) & ~(uintptr_t)15);\n const size_t t_offset =\n ((uintptr_t)t - (uintptr_t)s >= n ? n : (uintptr_t)t - (uintptr_t)s);\n const size_t t_count = ((n - t_offset) / 16);\n for (i = 0; i < t_offset; ++i) {\n if (get_FildeshMascii(mascii, (unsigned char)s[i])) {\n return i;\n }\n }\n for (i = 0; i < t_count; ++i) {\n unsigned idx = get16_FildeshMascii(*mascii, t[i]);\n if (idx < 16) {\n return t_offset + 16 * i + (size_t)idx;\n }\n }\n for (i = t_offset + 16 * t_count; i < n; ++i) {\n if (get_FildeshMascii(mascii, (unsigned char)s[i])) {\n return i;\n }\n }\n return n;\n}", "system": ""} +{"instruction": "", "input": "# This is the normalized code:\nstatic const char* func1(unsigned short var1) {\n switch (var1 & 0x0110) {\n case 0x0000:\n return \"Request\";\n case 0x0100:\n return \"Success Response\";\n case 0x0110:\n return \"Error Response\";\n case 0x0010:\n return \"Indication\";\n default:\n return \"???\";\n }\n}\n# What is the source code?\n", "output": "const char *stun_class_name(uint16_t type) {\n if (STUN_IS_REQUEST(type))\n return \"Request\";\n else if (STUN_IS_SUCCESS_RESPONSE(type))\n return \"Success Response\";\n else if (STUN_IS_ERROR_RESPONSE(type))\n return \"Error Response\";\n else if (STUN_IS_INDICATION(type))\n return \"Indication\";\n else\n return \"???\";\n}", "system": ""} +{"instruction": "", "input": "# This is the normalized code:\nvoid func_timer_use(type1 *var1, type1 *var2, type1 *var3) {\n if (!var1 || !var3) {\n return;\n }\n var1->field1 = var3;\n if (var1->field2) {\n var1->field2 = 0;\n return;\n }\n if (var1->field3) {\n var1->field2 = var4.field4 + var1->field3;\n return;\n }\n func1(var1);\n}\n# What is the source code?\n", "output": "void func_timer_use(edict_t *self, edict_t *other, edict_t *activator) {\n if (!self || !activator) {\n return;\n }\n self->activator = activator;\n if (self->nextthink) {\n self->nextthink = 0;\n return;\n }\n if (self->delay)\n self->nextthink = level.time + self->delay;\n else\n func_timer_think(self);\n}", "system": ""} +{"instruction": "", "input": "# This is the normalized code:\nstatic int func1(const char *var1, const char *var2, const char **var3) {\n int var4 = 0;\n size_t var5;\n int var6;\n log_debug(\"Check %s/%s against %s(%d)\", var1, var2, *var3, func2(*var3));\n var5 = func2(*var3);\n if (var5) {\n if (var5 == 1 && **var3 == '*') {\n (*var3)++;\n var4 = 1;\n } else {\n var6 = func3(var1, *var3, var5);\n *var3 += var5;\n if (var6) var4 = 1;\n }\n }\n if (**var3 == '/') {\n (*var3)++;\n var5 = func2(*var3);\n if (var5) {\n if (var5 == 1 && **var3 == '*')\n var6 = 1;\n else\n var6 = func3(var2, *var3, var5);\n } else\n var6 = 0;\n *var3 += var5;\n var4 &= var6;\n }\n log_debug(\"%satch!\", var4 ? \"M\" : \"No m\");\n return var4;\n}\n# What is the source code?\n", "output": "int _runCommand(const char *origCommand, const abl_info *info,\n int(execFun)(char *const arg[])) {\n int err = 0;\n int bufSize = 0;\n int argNum = 0;\n char **result = NULL;\n char **substResult = NULL;\n char *command = NULL;\n if (!origCommand || !*origCommand) return 0;\n command = strdup(origCommand);\n if (!command) return 1;\n argNum = splitCommand(command, NULL);\n if (argNum == 0) goto cleanup;\n if (argNum < 0) {\n err = 1;\n goto cleanup;\n }\n result = malloc((argNum + 1) * sizeof(char *));\n substResult = malloc((argNum + 1) * sizeof(char *));\n memset(result, 0, (argNum + 1) * sizeof(char *));\n memset(substResult, 0, (argNum + 1) * sizeof(char *));\n argNum = splitCommand(command, result);\n int partIndex = 0;\n while (result[partIndex]) {\n bufSize = prepare_string(result[partIndex], info, NULL);\n if (bufSize <= 0) {\n log_warning(\"failed to substitute %s.\", result[partIndex]);\n err = 1;\n goto cleanup;\n }\n if (bufSize > COMMAND_SIZE) {\n log_warning(\"command length error.\");\n goto cleanup;\n }\n substResult[partIndex] = malloc(bufSize * sizeof(char));\n if (substResult[partIndex] == NULL) {\n err = 1;\n goto cleanup;\n }\n bufSize = prepare_string(result[partIndex], info, substResult[partIndex]);\n ++partIndex;\n }\n err = execFun(substResult);\ncleanup:\n if (result) {\n free(result);\n }\n if (substResult) {\n partIndex = 0;\n while (substResult[partIndex]) {\n free(substResult[partIndex]);\n ++partIndex;\n }\n free(substResult);\n }\n if (command) free(command);\n return err;\n}", "system": ""} +{"instruction": "", "input": "# This is the normalized code:\ntype1 eb_open_narrow_font_file(type2 *var1, int var2) {\n type3 *var3;\n char var4[var5];\n int var6;\n int var7;\n func1((\"in: eb_open_narrow_font(book=%d, font_code=%d)\", (int)var1->field1,\n var2));\n var3 = var1->field2 + var2;\n if (var3->field3 == -1) goto failed;\n if (zio_file(var3->field4) >= 0) goto succeeded;\n var6 = -1;\n if (var1->field5 == var8) {\n if (var3->field6) {\n if (zio_mode(var3->field4) != -1) var6 = var9;\n } else {\n var6 = zio_mode(var3->field7);\n }\n eb_compose_path_name2(var1->field8, var3->field9, var3->field10, var4);\n } else {\n if (var3->field6) {\n if (zio_mode(var3->field4) != -1) var6 = var9;\n eb_compose_path_name3(var1->field8, var3->field9, var3->field10,\n var3->field11, var4);\n } else {\n eb_canonicalize_file_name(var3->field11);\n if (eb_find_file_name3(var1->field8, var3->field9, var3->field10,\n var3->field11, var3->field11) != var10)\n goto failed;\n eb_compose_path_name3(var1->field8, var3->field9, var3->field10,\n var3->field11, var4);\n eb_path_name_zio_code(var4, var11, &var6);\n }\n }\n if (var6 != -1) {\n var7 = zio_open(var3->field4, var4, var6);\n if (var7 < 0) goto failed;\n }\nsucceeded:\n func1((\"out: eb_open_narrow_font_file(file=%d) = %s\", zio_file(var3->field4),\n eb_error_string(var10)));\n return var10;\nfailed:\n func1((\"out: eb_open_narrow_font_file() = %s\", eb_error_string(var12)));\n return var12;\n}\n# What is the source code?\n", "output": "EB_Error_Code eb_open_narrow_font_file(EB_Book *book, EB_Font_Code font_code) {\n EB_Error_Code error_code;\n EB_Subbook *subbook;\n EB_Font *narrow_font;\n char font_path_name[EB_MAX_PATH_LENGTH + 1];\n Zio_Code zio_code;\n LOG((\"in: eb_open_narrow_font(book=%d, font_code=%d)\", (int)book->code,\n (int)font_code));\n subbook = book->subbook_current;\n narrow_font = subbook->narrow_fonts + font_code;\n if (narrow_font->font_code == EB_FONT_INVALID) {\n error_code = EB_ERR_FAIL_OPEN_FONT;\n goto failed;\n }\n if (0 <= zio_file(&narrow_font->zio)) goto succeeded;\n zio_code = ZIO_INVALID;\n if (book->disc_code == EB_DISC_EB) {\n if (narrow_font->initialized) {\n if (zio_mode(&narrow_font->zio) != ZIO_INVALID) zio_code = ZIO_REOPEN;\n } else {\n zio_code = zio_mode(&subbook->text_zio);\n }\n eb_compose_path_name2(book->path, subbook->directory_name,\n subbook->text_file_name, font_path_name);\n } else {\n if (narrow_font->initialized) {\n if (zio_mode(&narrow_font->zio) != ZIO_INVALID) zio_code = ZIO_REOPEN;\n eb_compose_path_name3(book->path, subbook->directory_name,\n subbook->gaiji_directory_name,\n narrow_font->file_name, font_path_name);\n } else {\n eb_canonicalize_file_name(narrow_font->file_name);\n if (eb_find_file_name3(book->path, subbook->directory_name,\n subbook->gaiji_directory_name,\n narrow_font->file_name,\n narrow_font->file_name) != EB_SUCCESS) {\n error_code = EB_ERR_FAIL_OPEN_FONT;\n goto failed;\n }\n eb_compose_path_name3(book->path, subbook->directory_name,\n subbook->gaiji_directory_name,\n narrow_font->file_name, font_path_name);\n eb_path_name_zio_code(font_path_name, ZIO_PLAIN, &zio_code);\n }\n }\n if (zio_code != ZIO_INVALID &&\n zio_open(&narrow_font->zio, font_path_name, zio_code) < 0) {\n error_code = EB_ERR_FAIL_OPEN_FONT;\n goto failed;\n }\nsucceeded:\n LOG((\"out: eb_open_narrow_font_file(file=%d) = %s\",\n zio_file(&narrow_font->zio), eb_error_string(EB_SUCCESS)));\n return EB_SUCCESS;\nfailed:\n LOG((\"out: eb_open_narrow_font_file() = %s\", eb_error_string(error_code)));\n return error_code;\n}", "system": ""} +{"instruction": "", "input": "# This is the normalized code:\nstatic int func1(type1* var1) {\n int var2, var3;\n type2* var4;\n assert(!func2(var1));\n var2 = *var1->field1;\n assert(!func3(var1, var2));\n func4(4, var2, \"popped\");\n var4 = func5(var1, var2);\n assert(!var4->field2);\n var4->field2 = -1;\n var3 = func6(var1);\n if (var3) {\n var4 = func5(var1, var3);\n assert(var4->field2 == var3);\n var4->field2 = 0;\n *var1->field1 = var3;\n func7(var1, var3);\n } else\n assert(var2 == var3);\n return var2;\n}\n# What is the source code?\n", "output": "static int lglpopesched(LGL* lgl) {\n Stk* s = &lgl->esched;\n int res, last, cnt, *p;\n EVar* ev;\n assert(!lglmtstk(s));\n res = *s->start;\n assert(!lglifrozen(lgl, res));\n LOGESCHED(4, res, \"popped\");\n ev = lglevar(lgl, res);\n assert(!ev->pos);\n ev->pos = -1;\n last = lglpopstk(s);\n cnt = lglcntstk(s);\n if (!cnt) {\n assert(last == res);\n return res;\n }\n p = lglepos(lgl, last);\n assert(*p == cnt);\n *p = 0;\n *s->start = last;\n lgledown(lgl, last);\n return res;\n}", "system": ""} +{"instruction": "", "input": "# This is the normalized code:\nssize_t func1(const type1 *var1, char *var2, size_t var3) {\n size_t var4;\n ssize_t var5 = -1;\n type2 assert(type3 != NULL);\n if (NULL == var1->field1)\n func2(var6, var7, var8, \"no filename available for that reference\");\n var4 = strlen(var1->field1);\n assert(var4 <= var9);\n if (var2) {\n var4 = func3(var4, var3 - 1);\n func4(var2, var1->field1, var4);\n var2[var4] = '\\0';\n }\n var5 = (ssize_t)var4 + 1;\nvar10:\n var11(type4)\n}\n# What is the source code?\n", "output": "ssize_t H5R__get_file_name(const H5R_ref_priv_t *ref, char *buf, size_t size) {\n size_t copy_len;\n ssize_t ret_value = -1;\n FUNC_ENTER_PACKAGE\n assert(ref != NULL);\n if (!ref->info.obj.filename)\n HGOTO_ERROR(H5E_REFERENCE, H5E_ARGS, (-1),\n \"no filename available for that reference\");\n copy_len = strlen(ref->info.obj.filename);\n assert(copy_len <= H5R_MAX_STRING_LEN);\n if (buf) {\n copy_len = MIN(copy_len, size - 1);\n H5MM_memcpy(buf, ref->info.obj.filename, copy_len);\n buf[copy_len] = '\\0';\n }\n ret_value = (ssize_t)(copy_len + 1);\ndone:\n FUNC_LEAVE_NOAPI(ret_value)\n}", "system": ""} +{"instruction": "", "input": "# This is the normalized code:\nstatic void func1(type1 *var1, type2 *var2) {\n static int var3 = 0;\n static char *var4[10];\n int var5 = var1->field1 == var1->field2;\n if (!var3) {\n var4[0] = func2(\"_Undo\");\n var4[2] = func2(\"Cu_t\");\n var4[4] = func2(\"_Copy\");\n var4[5] = func2(\"_Paste\");\n var4[7] = func2(\"_Save in UTF8\");\n var4[8] = func2(\"Save in _UCS2\");\n var4[9] = func2(\"_Import\");\n var3 = true;\n }\n var4[1] = var1->field3 == NULL ? \"F\" : \"\";\n var4[3] = var5 ? \"T\" : \"\";\n var4[5] = var5 ? \"T\" : \"\";\n var4[6] = func3(var1->field4, true, \"text/plain;charset=ISO-10646-UCS-2\") ||\n func3(var1->field4, true, \"UTF8_STRING\") ||\n func3(var1->field4, true, \"STRING\")\n ? \"\"\n : \"T\";\n var6 = var1;\n func4(var1->field4, var2, var4);\n}\n# What is the source code?\n", "output": "static void GTFPopupMenu(GTextField *gt, GEvent *event) {\n int no_sel = gt->sel_start == gt->sel_end;\n if (first) {\n gtf_popuplist[0].ti.text = (unichar_t *)_(\"_Undo\");\n gtf_popuplist[2].ti.text = (unichar_t *)_(\"Cu_t\");\n gtf_popuplist[3].ti.text = (unichar_t *)_(\"_Copy\");\n gtf_popuplist[4].ti.text = (unichar_t *)_(\"_Paste\");\n gtf_popuplist[6].ti.text = (unichar_t *)_(\"_Save in UTF8\");\n gtf_popuplist[7].ti.text = (unichar_t *)_(\"Save in _UCS2\");\n gtf_popuplist[8].ti.text = (unichar_t *)_(\"_Import\");\n first = false;\n }\n gtf_popuplist[0].ti.disabled = gt->oldtext == NULL;\n gtf_popuplist[2].ti.disabled = no_sel;\n gtf_popuplist[3].ti.disabled = no_sel;\n gtf_popuplist[4].ti.disabled =\n !GDrawSelectionHasType(gt->g.base, sn_clipboard,\n \"text/plain;charset=ISO-10646-UCS-2\") &&\n !GDrawSelectionHasType(gt->g.base, sn_clipboard, \"UTF8_STRING\") &&\n !GDrawSelectionHasType(gt->g.base, sn_clipboard, \"STRING\");\n popup_kludge = gt;\n GMenuCreatePopupMenu(gt->g.base, event, gtf_popuplist);\n}", "system": ""} +{"instruction": "", "input": "# This is the normalized code:\nstatic void func1(type1 *var1) {\n type2 *var2;\n int var3;\n func2(var1->field1, var2, var3) func3(var2);\n func4(&var1->field1);\n func5(var1->field2);\n func5(var1);\n}\n# What is the source code?\n", "output": "static inline void Abc_SclCellFree(SC_Cell* p) {\n SC_Pin* pTemp;\n int i;\n SC_CellForEachPin(p, pTemp, i) Abc_SclPinFree(pTemp);\n Vec_PtrErase(&p->vPins);\n ABC_FREE(p->pName);\n ABC_FREE(p);\n}", "system": ""} +{"instruction": "", "input": "# This is the normalized code:\nstatic int func1(const struct type1 *var1, const struct type2 *var2) {\n const struct type3 *var3 = func2(var1, var4 var5, var1);\n if (!func3(var3->field1, var2->field2) || var2->field3 != var3->field4)\n return 0;\n func4(\" using listen skt from vhost %s\\n\", var3->field1->field5);\n return 1;\n}\n# What is the source code?\n", "output": "static int check_extant(struct lws_dll2 *d, void *user) {\n struct lws *wsi = lws_container_of(d, struct lws, listen_list);\n struct vh_sock_args *a = (struct vh_sock_args *)user;\n if (!lws_vhost_compare_listen(wsi->a.vhost, a->vhost)) return 0;\n if (wsi->af != a->af) return 0;\n lwsl_notice(\" using listen skt from vhost %s\\n\", wsi->a.vhost->name);\n return 1;\n}", "system": ""} +{"instruction": "", "input": "# This is the normalized code:\nstatic void func1(struct type1 *var1, void *var2) {\n struct type2 *var3, *var4;\n var3 = bufferevent_socket_new(var5, (intptr_t)var2, var6);\n if (var7 && var8) {\n type3 *var9 = SSL_new(var7);\n var4 = bufferevent_openssl_socket_new(var5, -1, var9, var10, var6);\n } else {\n var4 = bufferevent_socket_new(var5, -1, var6);\n }\n if (bufferevent_socket_connect(var4, (struct type4 *)&var11, var12) < 0) {\n perror(\"bufferevent_socket_connect\");\n bufferevent_free(var4);\n bufferevent_free(var3);\n return;\n }\n if (var7 && !var8) {\n type3 *var9 = SSL_new(var7);\n struct type2 *var13 =\n bufferevent_openssl_filter_new(var5, var4, var9, var10, var6);\n if (!var13) {\n perror(\"Bufferevent_openssl_new\");\n bufferevent_free(var4);\n bufferevent_free(var3);\n return;\n }\n var4 = var13;\n }\n bufferevent_setcb(var3, var14, NULL, var15, var4);\n bufferevent_setcb(var4, var14, NULL, var15, var3);\n bufferevent_enable(var3, var16);\n bufferevent_enable(var4, var16);\n}\n# What is the source code?\n", "output": "static void accept_cb(struct evconnlistener *listener, evutil_socket_t fd,\n struct sockaddr *a, int slen, void *p) {\n struct bufferevent *b_out, *b_in;\n b_in = bufferevent_socket_new(\n base, fd, BEV_OPT_CLOSE_ON_FREE | BEV_OPT_DEFER_CALLBACKS);\n if (!ssl_ctx || use_wrapper)\n b_out = bufferevent_socket_new(\n base, -1, BEV_OPT_CLOSE_ON_FREE | BEV_OPT_DEFER_CALLBACKS);\n else {\n SSL *ssl = SSL_new(ssl_ctx);\n b_out = bufferevent_openssl_socket_new(\n base, -1, ssl, BUFFEREVENT_SSL_CONNECTING,\n BEV_OPT_CLOSE_ON_FREE | BEV_OPT_DEFER_CALLBACKS);\n }\n assert(b_in && b_out);\n if (bufferevent_socket_connect(b_out, (struct sockaddr *)&connect_to_addr,\n connect_to_addrlen) < 0) {\n perror(\"bufferevent_socket_connect\");\n bufferevent_free(b_out);\n bufferevent_free(b_in);\n return;\n }\n if (ssl_ctx && use_wrapper) {\n struct bufferevent *b_ssl;\n SSL *ssl = SSL_new(ssl_ctx);\n b_ssl = bufferevent_openssl_filter_new(\n base, b_out, ssl, BUFFEREVENT_SSL_CONNECTING,\n BEV_OPT_CLOSE_ON_FREE | BEV_OPT_DEFER_CALLBACKS);\n if (!b_ssl) {\n perror(\"Bufferevent_openssl_new\");\n bufferevent_free(b_out);\n bufferevent_free(b_in);\n return;\n }\n b_out = b_ssl;\n }\n bufferevent_setcb(b_in, readcb, NULL, eventcb, b_out);\n bufferevent_setcb(b_out, readcb, NULL, eventcb, b_in);\n bufferevent_enable(b_in, EV_READ | EV_WRITE);\n bufferevent_enable(b_out, EV_READ | EV_WRITE);\n}", "system": ""} +{"instruction": "", "input": "# This is the normalized code:\nint fluid_synth_get_cc(type1 *var1, int var2, int var3, int *var4) {\n int var5 = var6;\n func1(var3 >= 0 && var3 <= 127, var5);\n func2(var4);\n func3(var5);\n}\n# What is the source code?\n", "output": "int fluid_synth_get_cc(fluid_synth_t *synth, int chan, int num, int *pval) {\n fluid_return_val_if_fail(num >= 0 && num < 128, FLUID_FAILED);\n fluid_return_val_if_fail(pval != NULL, FLUID_FAILED);\n FLUID_API_ENTRY_CHAN(FLUID_FAILED);\n FLUID_API_RETURN_IF_CHAN_DISABLED(FLUID_FAILED);\n *pval = fluid_channel_get_cc(synth->channel[chan], num);\n FLUID_API_RETURN(FLUID_OK);\n}", "system": ""} +{"instruction": "", "input": "# This is the normalized code:\nvoid func1() {\n type1 *var1 = NULL;\n func2(&var1, 5);\n assert(func3(var1) == 1);\n func2(&var1, 8);\n func2(&var1, 12);\n assert(func3(var1) == 3);\n func4(var1);\n}\n# What is the source code?\n", "output": "void test_push_front() {\n node_t *head = NULL;\n push_front(&head, 5);\n assert(size(head) == 1);\n push_front(&head, 8);\n push_front(&head, 12);\n assert(size(head) == 3);\n destroy_list(head);\n}", "system": ""} +{"instruction": "", "input": "# This is the normalized code:\nvoid test_astronode_request_perf_counters_r(void) {\n uint8_t var1[14] = {0};\n uint8_t var2[14] = {0};\n var3 = var4;\n int var5 = astronode_request_perf_counters_r(var2);\n func1(1, var6.field1);\n func1(0, var5);\n func1(0xE7, var2[0]);\n func1(0xF1, var2[1]);\n func1(0xF2, var2[2]);\n func1(0xF3, var2[3]);\n func1(0xF4, var2[4]);\n func1(0xF5, var2[5]);\n func1(0xF6, var2[6]);\n func1(0xF7, var2[7]);\n func1(0xF8, var2[8]);\n func1(0xF9, var2[9]);\n func1(0xFA, var2[10]);\n func1(0xFB, var2[11]);\n func1(0xFC, var2[12]);\n func1(0xFD, var2[13]);\n}\n# What is the source code?\n", "output": "void test_astronode_request_perf_counters_r(void) {\n perf_counters_r_response_t ans = {0};\n astronode_transport_send_receive_fake.custom_fake =\n astronode_transport_send_receive_custom_fake_perf_counters_r;\n as_return_status_t ret_status = astronode_request_perf_counters_r(&ans);\n TEST_ASSERT_EQUAL(1, astronode_transport_send_receive_fake.call_count);\n TEST_ASSERT_EQUAL(RS_ASSET_SUCCESS, ret_status);\n TEST_ASSERT_EQUAL(ASTRONODE_OP_CODE_PER_RA, ans.data.opcode);\n TEST_ASSERT_EQUAL(0xF1, ans.data.sat_search_phase);\n TEST_ASSERT_EQUAL(0xF2, ans.data.sat_search_try);\n TEST_ASSERT_EQUAL(0xF3, ans.data.sat_demod_phase);\n TEST_ASSERT_EQUAL(0xF4, ans.data.sat_demod_try);\n TEST_ASSERT_EQUAL(0xF5, ans.data.valid_sat_demod);\n TEST_ASSERT_EQUAL(0xF6, ans.data.ack_demod_try);\n TEST_ASSERT_EQUAL(0xF7, ans.data.valid_ack_demod);\n TEST_ASSERT_EQUAL(0xF8, ans.data.msg_queued);\n TEST_ASSERT_EQUAL(0xF9, ans.data.msg_dequeued);\n TEST_ASSERT_EQUAL(0xFA, ans.data.msg_ack);\n TEST_ASSERT_EQUAL(0xFB, ans.data.fragment_tx);\n TEST_ASSERT_EQUAL(0xFC, ans.data.fragment_ack);\n TEST_ASSERT_EQUAL(0xFD, ans.data.unicast_demod_try);\n TEST_ASSERT_EQUAL(0xFE, ans.data.valid_unicast_demod);\n}", "system": ""} +{"instruction": "", "input": "# This is the normalized code:\nint Str_ManVectorAffinity(type1* var1, type2* var2, type2* var3, type3* var4,\n int var5) {\n int var6, var7, var8, var9, var10, var11, var12[64];\n var10 = func1(var2);\n assert(var10 > 2);\n if (var10 > 64) {\n memset(var4, 0, 64 * sizeof(var13));\n return 0;\n }\n Gia_ManIncrementTravId(var1);\n func2(var2, var6, var7) {\n func3(var1, var6);\n func4(var1, var6, var7);\n var4[var7] = 1ULL << (var7);\n var12[var7] = 0;\n }\n for (var9 = 1; var9 < 8; var9++) {\n func2(var2, var6, var7) {\n func5(var1, var6, var8, var11) {\n if (func6(var1, var8)) continue;\n if (var5 == func1(var2)) continue;\n func3(var1, var8);\n var4[func1(var2)] = 0;\n var12[func1(var2)] = var9;\n func4(var1, var8, func1(var2));\n var4[func4(var1, var8, var7)] |= var4[var7];\n }\n if (func7(var1, var6)) var4[func4(var1, var6, var7)] |= var4[var7];\n }\n }\n var11 = 0;\n func2(var2, var6, var7) {\n assert(var4[var7]);\n if (var4[var7] == (1ULL << (var10 - 1))) continue;\n var4[var11] = var4[var7];\n var12[var11] = var12[var7];\n if (++var11 == 64) break;\n }\n for (var7 = var11; var7 < 64; var7++) var4[var7] = 0;\n func8(var4, 64);\n if (func1(var2) > var10) func9(var2, var10);\n return var11;\n}\n# What is the source code?\n", "output": "int Str_ManVectorAffinity(Gia_Man_t* p, Vec_Int_t* vSuper, Vec_Int_t* vDelay,\n word Matrix[256], int nLimit) {\n int fVerbose = 0;\n int Levels[256];\n int nSize = Vec_IntSize(vSuper);\n int Prev = nSize, nLevels = 1;\n int i, k, iLit, iFanin, nSizeNew;\n word Mask;\n assert(nSize > 2);\n if (nSize > 64) {\n for (i = 0; i < 64; i++) Matrix[i] = 0;\n return 0;\n }\n Gia_ManIncrementTravId(p);\n Vec_IntForEachEntry(vSuper, iLit, i) {\n Gia_ObjSetTravIdCurrentId(p, Abc_Lit2Var(iLit));\n Str_ManSetNum(p, Abc_Lit2Var(iLit), i);\n Matrix[i] = ((word)1) << (63 - i);\n Levels[i] = 0;\n }\n Vec_IntForEachEntry(vSuper, iLit, i) {\n Gia_Obj_t* pObj = Gia_ManObj(p, Abc_Lit2Var(iLit));\n if (Gia_ObjIsAnd(pObj)) {\n for (k = 0; k < 2; k++) {\n iFanin = k ? Gia_ObjFaninId1p(p, pObj) : Gia_ObjFaninId0p(p, pObj);\n if (!Gia_ObjIsTravIdCurrentId(p, iFanin)) {\n if (Vec_IntSize(vSuper) == nLimit) break;\n Gia_ObjSetTravIdCurrentId(p, iFanin);\n Matrix[Vec_IntSize(vSuper)] = 0;\n Levels[Vec_IntSize(vSuper)] = nLevels;\n Str_ManSetNum(p, iFanin, Vec_IntSize(vSuper));\n Vec_IntPush(vSuper, Abc_Var2Lit(iFanin, 0));\n }\n Matrix[Str_ManNum(p, iFanin)] |= Matrix[i];\n }\n }\n if (Gia_ObjIsMux(p, pObj)) {\n iFanin = Gia_ObjFaninId2p(p, pObj);\n if (!Gia_ObjIsTravIdCurrentId(p, iFanin)) {\n if (Vec_IntSize(vSuper) == nLimit) break;\n Gia_ObjSetTravIdCurrentId(p, iFanin);\n Matrix[Vec_IntSize(vSuper)] = 0;\n Levels[Vec_IntSize(vSuper)] = nLevels;\n Str_ManSetNum(p, iFanin, Vec_IntSize(vSuper));\n Vec_IntPush(vSuper, Abc_Var2Lit(iFanin, 0));\n }\n Matrix[Str_ManNum(p, iFanin)] |= Matrix[i];\n }\n if (Prev == i) Prev = Vec_IntSize(vSuper), nLevels++;\n if (nLevels == 8) break;\n }\n Mask = (~(word)0) << (64 - nSize);\n for (k = i = 0; i < Vec_IntSize(vSuper); i++) {\n assert(Matrix[i]);\n if ((Matrix[i] & (Matrix[i] - 1)) == 0) continue;\n if (Matrix[i] == Mask) continue;\n Matrix[k] = Matrix[i];\n Levels[k] = Levels[i];\n k++;\n if (k == 64) break;\n }\n for (i = k; i < 64; i++) Matrix[i] = 0;\n nSizeNew = k;\n if (nSizeNew == 0) {\n Vec_IntShrink(vSuper, nSize);\n return 0;\n }\n transpose64(Matrix);\n if (fVerbose && nSize > 10) {\n printf(\n \"Gate inputs = %d. Collected fanins = %d. All = %d. Good = %d. \"\n \"Levels = %d\\n\",\n nSize, Vec_IntSize(vSuper) - nSize, Vec_IntSize(vSuper), nSizeNew,\n nLevels);\n printf(\" \");\n for (i = 0; i < nSizeNew; i++) printf(\"%d\", Levels[i]);\n printf(\"\\n\");\n for (i = 0; i < nSize; i++) {\n printf(\"%6d : \", Abc_Lit2Var(Vec_IntEntry(vSuper, i)));\n printf(\"%3d \", Vec_IntEntry(vDelay, i) >> 4);\n printf(\"%3d \", Vec_IntEntry(vDelay, i) & 15);\n }\n i = 0;\n }\n Vec_IntShrink(vSuper, nSize);\n return nSizeNew;\n}", "system": ""} +{"instruction": "", "input": "# This is the normalized code:\ntype1 xmlAddPrevSibling(type1 var1, type1 var2) {\n if ((var1 == NULL) || (var1->field1 == var3)) {\n return (NULL);\n }\n if ((var2 == NULL) || (var2->field1 == var3)) {\n return (NULL);\n }\n if (var1 == var2) {\n return (NULL);\n }\n xmlUnlinkNode(var2);\n if (var2->field1 == var4) {\n return (func1(var1->field2, var1, var2));\n }\n if (var2->field1 == var5) {\n if (var1->field1 == var5) {\n type2 *var6;\n var6 = xmlStrcat(func2(var2->field3), var1->field3);\n xmlNodeSetContent(var1, var6);\n xmlFree(var6);\n xmlFreeNode(var2);\n return (var1);\n }\n if ((var1->field2 != NULL) && (var1->field2->field1 == var5) &&\n (var1->field4 == var1->field2->field4)) {\n xmlNodeAddContent(var1->field2, var2->field3);\n xmlFreeNode(var2);\n return (var1->field2);\n }\n }\n if (var2->field5 != var1->field5) {\n xmlSetTreeDoc(var2, var1->field5);\n }\n var2->field6 = var1->field6;\n var2->field7 = var1;\n var2->field2 = var1->field2;\n var1->field2 = var2;\n if (var2->field2 != NULL) {\n var2->field2->field7 = var2;\n }\n if ((var2->field6 != NULL) && (var2->field6->field8 == var1)) {\n var2->field6->field8 = var2;\n }\n return (var2);\n}\n# What is the source code?\n", "output": "xmlNodePtr xmlAddPrevSibling(xmlNodePtr cur, xmlNodePtr elem) {\n if ((cur == NULL) || (cur->type == XML_NAMESPACE_DECL)) {\n#ifdef DEBUG_TREE\n xmlGenericError(xmlGenericErrorContext,\n \"xmlAddPrevSibling : cur == NULL\\n\");\n#endif\n return (NULL);\n }\n if ((elem == NULL) || (elem->type == XML_NAMESPACE_DECL)) {\n#ifdef DEBUG_TREE\n xmlGenericError(xmlGenericErrorContext,\n \"xmlAddPrevSibling : elem == NULL\\n\");\n#endif\n return (NULL);\n }\n if (cur == elem) {\n#ifdef DEBUG_TREE\n xmlGenericError(xmlGenericErrorContext,\n \"xmlAddPrevSibling : cur == elem\\n\");\n#endif\n return (NULL);\n }\n xmlUnlinkNode(elem);\n if (elem->type == XML_TEXT_NODE) {\n if (cur->type == XML_TEXT_NODE) {\n xmlChar *tmp;\n tmp = xmlStrdup(elem->content);\n tmp = xmlStrcat(tmp, cur->content);\n xmlNodeSetContent(cur, tmp);\n xmlFree(tmp);\n xmlFreeNode(elem);\n return (cur);\n }\n if ((cur->prev != NULL) && (cur->prev->type == XML_TEXT_NODE) &&\n (cur->name == cur->prev->name)) {\n xmlNodeAddContent(cur->prev, elem->content);\n xmlFreeNode(elem);\n return (cur->prev);\n }\n } else if (elem->type == XML_ATTRIBUTE_NODE) {\n return xmlAddPropSibling(cur->prev, cur, elem);\n }\n if (elem->doc != cur->doc) {\n xmlSetTreeDoc(elem, cur->doc);\n }\n elem->parent = cur->parent;\n elem->next = cur;\n elem->prev = cur->prev;\n cur->prev = elem;\n if (elem->prev != NULL) elem->prev->next = elem;\n if ((elem->parent != NULL) && (elem->parent->children == cur)) {\n elem->parent->children = elem;\n }\n return (elem);\n}", "system": ""} diff --git a/sk2decompile/LLaMA-Factory/SK2DECOMPILE/data/pseudo2norm-examples.jsonl b/sk2decompile/LLaMA-Factory/SK2DECOMPILE/data/pseudo2norm-examples.jsonl new file mode 100644 index 0000000..479b2f1 --- /dev/null +++ b/sk2decompile/LLaMA-Factory/SK2DECOMPILE/data/pseudo2norm-examples.jsonl @@ -0,0 +1,20 @@ +{"instruction": "", "input": "# This is the pseudo code:\nlong long sub_4E05(long long a1) {\n long long v1;\n long long v2;\n long long v3;\n long long result;\n v1 = sub_47A6(0LL, 0LL, 8LL * *(int *)(a1 + 20));\n v2 = v1;\n v3 = *(int *)(a1 + 20);\n if (v3 > 0) memset(v1, 0LL, 8 * v3);\n result = sub_47A6(0LL, 0LL, 40LL);\n *(uint32_t *)result = 2;\n *(uint8_t *)(result + 4) = 0;\n *(uint64_t *)(result + 8) =\n *(long long *)((char *)&qword_40650 + (uint64_t)&unk_A0E0);\n *(long long *)((char *)&qword_40650 + (uint64_t)&unk_A0E0) = result;\n *(uint64_t *)(result + 16) = a1;\n *(uint64_t *)(result + 24) = v2;\n *(uint32_t *)(result + 32) = *(uint32_t *)(a1 + 20);\n return result;\n}\n# What is the source code?\n", "output": "type1* func1(type2* var1) {\n type3** var2 = func2(var3*, var1->field1);\n for (int var4 = 0; var4 < var1->field1; var4++) {\n var2[var4] = NULL;\n }\n type1* var5 = func3(var6, var7);\n var5->field2 = var1;\n var5->field3 = var2;\n var5->field1 = var1->field1;\n return var5;\n}", "system": ""} +{"instruction": "", "input": "# This is the pseudo code:\nlong long sub_5306(long long a1) {\n long long v1;\n long long v2;\n long long v3;\n long long result;\n v1 = sub_1C2C(0LL, 0LL, 8LL * *(int *)(a1 + 20));\n v2 = v1;\n v3 = *(int *)(a1 + 20);\n if (v3 > 0) memset(v1, 0LL, 8 * v3);\n result = sub_1C2C(0LL, 0LL, 40LL);\n *(uint32_t *)result = 2;\n *(uint8_t *)(result + 4) = 0;\n *(uint64_t *)(result + 8) =\n *(long long *)((char *)&qword_20650 + (uint64_t)&unk_A4A8);\n *(long long *)((char *)&qword_20650 + (uint64_t)&unk_A4A8) = result;\n *(uint64_t *)(result + 16) = a1;\n *(uint64_t *)(result + 24) = v2;\n *(uint32_t *)(result + 32) = *(uint32_t *)(a1 + 20);\n return result;\n}\n# What is the source code?\n", "output": "type1* func1(type2* var1) {\n type3** var2 = func2(var3*, var1->field1);\n for (int var4 = 0; var4 < var1->field1; var4++) {\n var2[var4] = NULL;\n }\n type1* var5 = func3(var6, var7);\n var5->field2 = var1;\n var5->field3 = var2;\n var5->field1 = var1->field1;\n return var5;\n}", "system": ""} +{"instruction": "", "input": "# This is the pseudo code:\nlong long defineNativeEnum(long long a1) {\n long long v1;\n long long v2;\n long long v3;\n long long v4;\n v1 = (unsigned int)strlen(a1);\n v2 = copyString(a1, v1);\n push(v2 | 18445618173802708992LL);\n v3 = newEnum(v2);\n *(uint32_t *)(v3 + 56) = 0;\n push(v3 | 18445618173802708992LL);\n v4 = *(uint64_t *)&vm[240] + 80LL;\n tableSet(v4, *(uint64_t *)&vm[71952] & 1125899906842623LL,\n *(uint64_t *)((char *)&loc_11918 + (uint64_t)vm));\n pop(v4);\n pop(v4);\n return v3;\n}\n# What is the source code?\n", "output": "type1* defineNativeEnum(const char* var1) {\n type2* var2 = copyString(var1, (int)strlen(var1));\n push(func1(var2));\n type1* var3 = newEnum(var2);\n var3->field1 = 0;\n push(func1(var3));\n tableSet(&var4.field2->field3, func2(var4.field4[0]), var4.field4[1]);\n pop();\n pop();\n return var3;\n}", "system": ""} +{"instruction": "", "input": "# This is the pseudo code:\nlong long sub_14A80(long long a1, long long a2) {\n long long v2;\n long long v3;\n long long v4;\n long long v5;\n long long i;\n long long v7;\n v2 = 0LL;\n v3 = sub_3440(a1, 0LL, 0LL, 8 * (unsigned int)*(unsigned short *)(a2 + 22));\n if (v3) {\n v4 = v3;\n v5 = *(unsigned short *)(a2 + 22);\n for (i = 0LL; v5 != i; ++i) *(uint64_t *)(v4 + 8 * i) = 0LL;\n v7 = sub_145C0(a1, 40LL, 21);\n if (v7) {\n v2 = v7;\n *(uint64_t *)(v7 + 16) = a2;\n *(uint64_t *)(v7 + 24) = v4;\n *(uint32_t *)(v7 + 32) = *(unsigned short *)(a2 + 22);\n } else {\n v2 = 0LL;\n sub_3440(a1, v4, 8 * (unsigned int)*(unsigned short *)(a2 + 22), 0LL);\n }\n }\n return v2;\n}\n# What is the source code?\n", "output": "type1 *func1(type2 *var1, type3 *var2) {\n type4 **var3 = func2(var1, var4 *, var2->field1);\n if (func3(var3 == NULL)) return NULL;\n for (int var5 = 0; var5 < var2->field1; var5++) var3[var5] = NULL;\n type1 *var6 = func4(var1, var7, var8);\n if (func3(var6 == NULL)) {\n func5(var1, var4 *, var3, var2->field1);\n return NULL;\n }\n var6->field2 = var2;\n var6->field3 = var3;\n var6->field1 = var2->field1;\n return var6;\n}", "system": ""} +{"instruction": "", "input": "# This is the pseudo code:\nlong long sub_662AF(long long a1, long long a2, long long a3, long long a4,\n long long a5, long long a6, __m128 a7, __m128 a8, __m128 a9,\n __m128 a10, __m128 a11, __m128 a12, __m128 a13, __m128 a14,\n char a15) {\n int v15;\n long long v16;\n long long v17;\n double v18;\n double v19;\n long long v20;\n long long result;\n uint64_t v22[4];\n char v23;\n long long v24;\n long long v25;\n long long v26;\n __m128 v27;\n __m128 v28;\n __m128 v29;\n __m128 v30;\n __m128 v31;\n __m128 v32;\n __m128 v33;\n __m128 v34;\n uint8_t v35[296];\n v27 = a7;\n v28 = a8;\n v29 = a9;\n v30 = a10;\n v31 = a11;\n v32 = a12;\n v33 = a13;\n v34 = a14;\n v24 = a4;\n v25 = a5;\n v26 = a6;\n v22[2] = &v23;\n v22[1] = &a15;\n v22[0] = 206158430232LL;\n v15 = ((long long (*)(uint8_t *, long long, long long, uint64_t *, long long,\n long long))vsnprintf)(v35, 255LL, a3, v22, a5, a6);\n v16 = sub_86413(a1, (long long)v35, v15);\n v17 = sub_660BF(a1);\n v20 = sub_7B7F1(a1, a2, a7, a8, a9, a10, v18, v19, a13, a14);\n result = sub_7FD38(a1, v16, v20);\n *(uint64_t *)(result + 48) = v17;\n return result;\n}\n# What is the source code?\n", "output": "type1* func1(type2* var1, const char* var2, const char* var3, ...) {\n char var4[var5];\n type3 var6;\n func2(var6, var3);\n int var7 = vsnprintf(var4, var5, var3, var6);\n func3(var6);\n type4* var8 = func4(var1, var4, var7);\n type5* var9 = func5(var1);\n type6* var10 = func6(var1, var2);\n type1* var11 = func7(var1, var8, var10);\n var11->field1 = var9;\n return var11;\n}", "system": ""} +{"instruction": "", "input": "# This is the pseudo code:\nlong long sub_5F7EA(long long a1, long long a2, long long a3, long long a4,\n long long a5, long long a6, __m128 a7, __m128 a8, __m128 a9,\n __m128 a10, __m128 a11, __m128 a12, __m128 a13, __m128 a14,\n char a15) {\n unsigned int v15;\n long long v16;\n long long v17;\n long long v18;\n uint64_t v20[4];\n char v21;\n long long v22;\n long long v23;\n long long v24;\n __m128 v25;\n __m128 v26;\n __m128 v27;\n __m128 v28;\n __m128 v29;\n __m128 v30;\n __m128 v31;\n __m128 v32;\n uint8_t v33[296];\n v25 = a7;\n v26 = a8;\n v27 = a9;\n v28 = a10;\n v29 = a11;\n v30 = a12;\n v31 = a13;\n v32 = a14;\n v22 = a4;\n v23 = a5;\n v24 = a6;\n v20[2] = &v21;\n v20[1] = &a15;\n v20[0] = 206158430232LL;\n v15 = ((long long (*)(uint8_t *, long long, long long, uint64_t *, long long,\n long long))vsnprintf)(v33, 255LL, a3, v20, a5, a6);\n v16 = sub_7D680(a1, v33, v15);\n v17 = sub_5F528(a1);\n v18 = sub_776AD(a1, v16, a2);\n *(uint64_t *)(v18 + 48) = v17;\n sub_8676D(a1, v18 | 18445618173802708992LL);\n if (!sub_5F25B(a1, 0)) exit(70LL);\n return v18;\n}\n# What is the source code?\n", "output": "type1* func1(type2* var1, type3* var2, const char* var3, ...) {\n char var4[var5];\n type4 var6;\n func2(var6, var3);\n int var7 = vsnprintf(var4, var5, var3, var6);\n func3(var6);\n type5* var8 = func4(var1, var4, var7);\n type6* var9 = func5(var1);\n type1* var10 = func6(var1, var8, var2);\n var10->field1 = var9;\n func7(var1, func8(var10));\n if (!func9(var1, false))\n exit(70);\n else\n return var10;\n}", "system": ""} +{"instruction": "", "input": "# This is the pseudo code:\nlong long new_bound_method(int a1, long long a2, long long a3) {\n long long result;\n result = reallocate(0LL, 0LL, 40LL);\n *(uint32_t *)result = 0;\n *(uint8_t *)(result + 4) = 0;\n *(uint64_t *)(result + 8) =\n *(long long *)((char *)&qword_40650 + (uint64_t)vm);\n *(long long *)((char *)&qword_40650 + (uint64_t)vm) = result;\n *(uint32_t *)(result + 16) = a1;\n *(uint64_t *)(result + 24) = a2;\n *(uint64_t *)(result + 32) = a3;\n return result;\n}\n# What is the source code?\n", "output": "type1 *new_bound_method(type2 var1, type3 *var2) {\n type1 *var3 = func1(var4, var5);\n var3->field1 = var1;\n var3->field2 = var2;\n return var3;\n}", "system": ""} +{"instruction": "", "input": "# This is the pseudo code:\nlong long mochiThreadCurrent(long long a1) {\n long long result;\n bool v2;\n long long v3;\n long long v4;\n long long v5;\n result = thrd_current(a1);\n v2 = *(uint32_t *)(a1 + 152) > 0;\n if (*(int *)(a1 + 152) > 0) {\n v3 = result;\n v4 = 0LL;\n while (1) {\n result = *(uint64_t *)(*(uint64_t *)(a1 + 144) + 8 * v4);\n if (result) {\n result = thrd_equal(v3, *(uint64_t *)(result + 32));\n if ((uint32_t)result) break;\n }\n ++v4;\n v5 = *(int *)(a1 + 152);\n v2 = v4 < v5;\n if (v4 >= v5) goto LABEL_9;\n }\n result = *(uint64_t *)(*(uint64_t *)(a1 + 144) + 8 * v4);\n }\nLABEL_9:\n if (!v2) sub_5826();\n return result;\n}\n# What is the source code?\n", "output": "type1* mochiThreadCurrent(type2* var1) {\n type3 var2 = thrd_current();\n for (int var3 = 0; var3 < var1->field1.field2; var3++) {\n if (var1->field1.field3[var3] != NULL &&\n thrd_equal(var2, var1->field1.field3[var3]->field4)) {\n return var1->field1.field3[var3];\n }\n }\n func1(\n \"Current thread is not a MochiVM thread, but tried to be accessed as \"\n \"one.\");\n return NULL;\n}", "system": ""} +{"instruction": "", "input": "# This is the pseudo code:\nlong long newCallFrame(long long a1, int a2, long long a3, long long a4) {\n long long result;\n result = mochiReallocate(a4, 0LL, 0LL, 40LL);\n *(uint32_t *)result = 6;\n *(uint8_t *)(result + 4) = 0;\n *(uint64_t *)(result + 8) = *(uint64_t *)(a4 + 248);\n *(uint64_t *)(a4 + 248) = result;\n *(uint64_t *)(result + 16) = a1;\n *(uint32_t *)(result + 24) = a2;\n *(uint64_t *)(result + 32) = a3;\n return result;\n}\n# What is the source code?\n", "output": "type1* newCallFrame(type2* var1, int var2, uint8_t* var3, type3* var4) {\n type1* var5 = func1(var4, var6);\n func2(var4, (type4*)var5, var7);\n var5->field1.field2 = var1;\n var5->field1.field3 = var2;\n var5->field4 = var3;\n return var5;\n}", "system": ""} +{"instruction": "", "input": "# This is the pseudo code:\nlong long sub_6FD4B(long long a1, int a2, long long a3) {\n unsigned int v5;\n long long v6;\n long long v7;\n long long v8;\n long long v9;\n long long v10;\n char v11;\n v5 = (a2 - 1) & sub_79144(a3);\n v7 = 0LL;\n do {\n v8 = a1 + 56LL * v5;\n v9 = *(uint64_t *)(v8 + 40);\n if (v9 == 9222246136947933191LL) {\n v10 = v7;\n if (!v7) v10 = a1 + 56LL * v5;\n if (*(uint64_t *)(v8 + 48) == 9222246136947933185LL) {\n v11 = 0;\n v6 = v10;\n continue;\n }\n v7 = v10;\n } else if (v9 == a3) {\n v11 = 0;\n v6 = a1 + 56LL * v5;\n continue;\n }\n v5 = (a2 - 1) & (v5 + 1);\n v11 = 1;\n } while (v11);\n return v6;\n}\n# What is the source code?\n", "output": "type1* func1(type1* var1, int var2, type2 var3) {\n uint32_t var4 = func2(var3);\n uint32_t var5 = var4 & (var2 - 1);\n type1* var6 = NULL;\n for (;;) {\n type1* var7 = &var1[var5];\n if (func3(var7->field1)) {\n if (func4(var7->field2)) {\n return var6 != NULL ? var6 : var7;\n } else {\n if (var6 == NULL) var6 = var7;\n }\n } else if (var7->field1 == var3) {\n return var7;\n }\n var5 = (var5 + 1) & (var2 - 1);\n }\n}", "system": ""} +{"instruction": "", "input": "# This is the pseudo code:\nlong long sub_14700(long long *a1, long long a2, char a3) {\n long long v4;\n long long v5;\n long long v6;\n int v7;\n int v8;\n int v9;\n long long v10;\n long long v11;\n long long v12;\n long long v13;\n long long v15;\n unsigned int v16;\n unsigned int v17;\n v4 = a1[2];\n v5 = a2;\n if (!*(uint32_t *)(a2 + 24)) {\n v6 = *a1;\n if (!(unsigned char)sub_148C0(a1, &v15, 16LL)) return 0LL;\n v7 = sub_14980(v6 + 40);\n sub_14900((uint32_t)a1, (unsigned int)&v15, (unsigned int)\"Class_%lu\", v7,\n v8, v9);\n v10 = sub_149C0(a1, v15, v16, v17);\n if (!v10) return 0LL;\n v5 = v10;\n v11 = *(uint64_t *)(v4 + 64);\n *(uint8_t *)v11 = 15;\n *(uint64_t *)(v11 + 8) = v5;\n *(uint64_t *)(v4 + 64) += 16LL;\n }\n v12 = sub_145C0(a1, 272LL, 20LL);\n if (!v12) return 0LL;\n v13 = v12;\n *(long double *)(v12 + 96) = 0LL;\n *(long double *)(v12 + 80) = 0LL;\n *(long double *)(v12 + 64) = 0LL;\n *(long double *)(v12 + 48) = 0LL;\n *(uint64_t *)(v12 + 112) = 0LL;\n *(long double *)(v12 + 32) = 0LL;\n *(uint64_t *)(v12 + 24) = v5;\n if (!*(uint32_t *)(a2 + 24)) *(uint64_t *)(v4 + 64) -= 16LL;\n *(uint8_t *)(v12 + 120) = 1;\n *(long double *)(v12 + 128) = 0LL;\n *(uint64_t *)(v12 + 144) = 0LL;\n *(uint8_t *)(v12 + 152) = 1;\n *(uint64_t *)(v12 + 160) = 0LL;\n sub_17540(v12 + 168);\n sub_169C0(v13 + 192);\n sub_169C0(v13 + 216);\n sub_178C0(v13 + 240);\n *(uint64_t *)(v13 + 256) = 0LL;\n *(unsigned short *)(v13 + 264) = 0;\n *(uint8_t *)(v13 + 266) = a3;\n return v13;\n}\n# What is the source code?\n", "output": "type1 *func1(type2 *var1, type3 *var2, bool var3) {\n type4 *var4 = var1->field1;\n type5 *var5 = var1->field2;\n type3 *var6 = var2;\n if (var2->field3.field4 == 0) {\n type6 var7;\n bool var8 = func2(var1, &var7, 16);\n if (func3(!var8)) return NULL;\n func4(var1, &var7, \"Class_%lu\", func5(&var4->field5) & 0xFFFFFFFF);\n var6 = func6(var1, var7.field6, var7.field4, var7.field7);\n if (func3(var6 == NULL)) return NULL;\n func7(var5, func8(var6));\n }\n type1 *var9 = func9(var1, var10, var11);\n if (func3(var9 == NULL)) return NULL;\n memset(&var9->field8, 0, sizeof(var12));\n var9->field9 = var6;\n if (var2->field3.field4 == 0) func10(var5);\n var9->field10 = var13;\n var9->field11 = NULL;\n var9->field12 = NULL;\n var9->field13 = var13;\n func11(&var9->field14);\n func12(&var9->field15);\n func12(&var9->field16);\n func13(&var9->field17);\n var9->field18 = NULL;\n var9->field19 = 0;\n var9->field20 = var3;\n return var9;\n}", "system": ""} +{"instruction": "", "input": "# This is the pseudo code:\nlong long sub_6648F(long long a1, long long a2, long long a3, long long a4,\n long long a5, long long a6, __m128 a7, __m128 a8, __m128 a9,\n __m128 a10, __m128 a11, __m128 a12, __m128 a13, __m128 a14,\n char a15) {\n long long v16;\n unsigned int v17;\n long long v18;\n long long v19;\n long long v20;\n uint64_t v22[4];\n char v23;\n long long v24;\n long long v25;\n long long v26;\n __m128 v27;\n __m128 v28;\n __m128 v29;\n __m128 v30;\n __m128 v31;\n __m128 v32;\n __m128 v33;\n __m128 v34;\n uint8_t v35[296];\n v27 = a7;\n v28 = a8;\n v29 = a9;\n v30 = a10;\n v31 = a11;\n v32 = a12;\n v33 = a13;\n v34 = a14;\n v24 = a4;\n v25 = a5;\n v26 = a6;\n v16 = sub_7B7F1(a1, a2);\n v22[2] = &v23;\n v22[1] = &a15;\n v22[0] = 206158430232LL;\n v17 = ((long long (*)(uint8_t *, long long, long long, uint64_t *))vsnprintf)(\n v35, 255LL, a3, v22);\n v18 = sub_86413(a1, v35, v17);\n v19 = sub_660BF(a1);\n v20 = sub_7FD38(a1, v18, v16);\n *(uint64_t *)(v20 + 48) = v19;\n sub_8FF25(a1, v20 | 18445618173802708992LL);\n if (!(unsigned char)sub_65E49(a1, 0)) exit(70LL);\n return v20;\n}\n# What is the source code?\n", "output": "type1* func1(type2* var1, const char* var2, const char* var3, ...) {\n type3* var4 = func2(var1, var2);\n char var5[var6];\n type4 var7;\n func3(var7, var3);\n int var8 = vsnprintf(var5, var6, var3, var7);\n func4(var7);\n type5* var9 = func5(var1, var5, var8);\n type6* var10 = func6(var1);\n type1* var11 = func7(var1, var9, var4);\n var11->field1 = var10;\n func8(var1, func9(var11));\n if (!func10(var1, false))\n exit(70);\n else\n return var11;\n}", "system": ""} +{"instruction": "", "input": "# This is the pseudo code:\nlong long newClass(long long a1, int a2, char a3) {\n long long v4;\n long long v5;\n v4 = *(uint64_t *)&vm[16];\n v5 = reallocate(0LL, 0LL, 176LL);\n *(uint32_t *)v5 = 5;\n *(uint64_t *)(v5 + 8) = v4;\n *(uint8_t *)(v5 + 16) = 0;\n *(uint64_t *)(v5 + 40) = *(long long *)((char *)&qword_919A8 + (uint64_t)vm);\n initTable(v5 + 24);\n *(long long *)((char *)&qword_919A8 + (uint64_t)vm) = v5;\n *(uint32_t *)(v5 + 56) = a2;\n *(uint64_t *)(v5 + 48) = a1;\n *(uint64_t *)(v5 + 64) = *(uint64_t *)&vm[240];\n *(uint64_t *)(v5 + 72) = 0LL;\n *(uint8_t *)(v5 + 168) = 0;\n *(uint8_t *)(v5 + 169) = a3;\n *(unsigned short *)(v5 + 80) = 0;\n initValueArray(v5 + 152);\n initTable(v5 + 88);\n initTable(v5 + 104);\n initTable(v5 + 120);\n initTable(v5 + 136);\n return v5;\n}\n# What is the source code?\n", "output": "type1* newClass(type2* var1, type3 var2, bool var3) {\n type1* var4 = func1(var5, var6, var7.field1);\n var4->field2 = var2;\n var4->field3 = var1;\n var4->field4 = var7.field5;\n var4->field6 = NULL;\n var4->field7 = false;\n var4->field8 = var3;\n var4->field9 = 0;\n initValueArray(&var4->field10);\n initTable(&var4->field11);\n initTable(&var4->field12);\n initTable(&var4->field13);\n initTable(&var4->field14);\n return var4;\n}", "system": ""} +{"instruction": "", "input": "# This is the pseudo code:\nlong long sub_D4660(uint64_t *a1, long long a2) {\n long long v3;\n long long v4;\n v4 = sub_E87A0(a1, a2);\n sub_FAB50(a1, v4 | 18445618173802708992LL);\n v3 = sub_9D8B0(a1, v4);\n *(uint8_t *)(v3 + 112) = 1;\n sub_FAB50(a1, v3 | 18445618173802708992LL);\n sub_ECC40((long long)a1, (long long)(a1 + 18611), *(uint64_t *)(v3 + 64),\n v3 | 18445618173802708992LL);\n sub_ECC40((long long)a1, a1[28] + 72LL, a1[2206] & 1125899906842623LL,\n a1[2207]);\n sub_FAB90(a1);\n sub_FAB90(a1);\n sub_31430(a1[18606], 3LL, v4, *(uint64_t *)(v3 + 64), 0LL);\n return v3;\n}\n# What is the source code?\n", "output": "type1* func1(type2* var1, const char* var2) {\n type3* var3 = func2(var1, var2);\n func3(var1, func4(var3));\n type1* var4 = func5(var1, var3);\n var4->field1 = true;\n func3(var1, func4(var4));\n func6(var1, &var1->field2, var4->field3, func4(var4));\n func6(var1, &var1->field4->field5, func7(var1->field6[0]), var1->field6[1]);\n func8(var1);\n func8(var1);\n func9(var1->field7, var5, var3, var4->field3, NULL);\n return var4;\n}", "system": ""} +{"instruction": "", "input": "# This is the pseudo code:\nlong long mochiNewDouble(long long a1, double a2) {\n long long result;\n result = mochiReallocate(a1, 0LL, 0LL, 24LL);\n *(uint32_t *)result = 2;\n *(uint8_t *)(result + 4) = 0;\n *(uint64_t *)(result + 8) = *(uint64_t *)(a1 + 248);\n *(uint64_t *)(a1 + 248) = result;\n *(double *)(result + 16) = a2;\n return result;\n}\n# What is the source code?\n", "output": "type1* mochiNewDouble(type2* var1, double var2) {\n type1* var3 = func1(var1, var4);\n func2(var1, (type3*)var3, var5);\n var3->field1 = var2;\n return var3;\n}", "system": ""} +{"instruction": "", "input": "# This is the pseudo code:\nuint32_t *silo_GetObjEnt(int a1, int a2, int a3) {\n long long *v3;\n long long v4;\n long long v5;\n long long v6;\n uint32_t *result;\n v3 = (long long *)objTable[a1];\n v4 = *((int *)v3 + 3);\n if (v4 <= 0) return 0LL;\n v5 = *v3;\n v6 = 0LL;\n while (1) {\n result = *(uint32_t **)(v5 + 8 * v6);\n if (result[1] == a2 && *result == a3) break;\n if (v4 == ++v6) return 0LL;\n }\n return result;\n}\n# What is the source code?\n", "output": "type1* silo_GetObjEnt(int var1, int var2, int var3) {\n int var4;\n for (var4 = 0; var4 < var5[var1]->field1; var4++) {\n if (var5[var1]->field2[var4]->field3 == var2 &&\n var5[var1]->field2[var4]->field4 == var3) {\n return (var5[var1]->field2[var4]);\n }\n }\n return (NULL);\n}", "system": ""} +{"instruction": "", "input": "# This is the pseudo code:\nlong long getNativeClass(long long a1, long long a2, __m128 a3, __m128 a4,\n __m128 a5, __m128 a6, double a7, double a8, __m128 a9,\n __m128 a10) {\n long long v10;\n long long v11;\n long long v12;\n long long v13;\n __m128 v14;\n __m128 v15;\n char v17;\n long long v18;\n long long NativeNamespace;\n long long v20;\n long long v21;\n v21 = a1;\n v20 = a2;\n NativeNamespace = getNativeNamespace(a1);\n v10 = newString(a2);\n tableGet(NativeNamespace + 80, v10, &v18);\n if ((sub_228A0(v18, 5LL) & 1) == 0) {\n runtimeError((long long)\"Class %s.%s is undefined.\", v21, v20, v11, v12,\n v13, a3, a4, a5, a6, v14, v15, a9, a10, v17);\n exit(70LL);\n }\n return v18 & 1125899906842623LL;\n}\n# What is the source code?\n", "output": "type1* getNativeClass(const char* var1, const char* var2) {\n type2* var3 = getNativeNamespace(var1);\n type3 var4;\n tableGet(&var3->field1, newString(var2), &var4);\n if (!func1(var4)) {\n runtimeError(\"Class %s.%s is undefined.\", var1, var2);\n exit(70);\n }\n return func2(var4);\n}", "system": ""} +{"instruction": "", "input": "# This is the pseudo code:\nlong long newBoundMethod(long long a1, unsigned long long a2) {\n long long v2;\n bool v3;\n long long v4;\n v2 = *(uint64_t *)&vm[200];\n v3 = 0;\n v4 = reallocate(0LL, 0LL, 72LL);\n *(uint32_t *)v4 = 3;\n *(uint64_t *)(v4 + 8) = v2;\n *(uint8_t *)(v4 + 16) = 0;\n *(uint64_t *)(v4 + 40) = *(long long *)((char *)&qword_919A8 + (uint64_t)vm);\n initTable(v4 + 24);\n *(long long *)((char *)&qword_919A8 + (uint64_t)vm) = v4;\n *(uint64_t *)(v4 + 48) = a1;\n *(uint64_t *)(v4 + 56) = a2;\n if ((unsigned int)(a2 >> 50) >= 16383)\n v3 = *(uint32_t *)(a2 & 1125899906842623LL) == 20;\n *(uint8_t *)(v4 + 64) = v3;\n return v4;\n}\n# What is the source code?\n", "output": "type1* newBoundMethod(type2 var1, type2 var2) {\n type1* var3 = func1(var4, var5, var6.field1);\n var3->field2 = var1;\n var3->field3 = var2;\n var3->field4 = func2(var2);\n return var3;\n}", "system": ""} +{"instruction": "", "input": "# This is the pseudo code:\nlong long mochiNewContinuation(long long a1, long long a2, char a3, int a4,\n int a5) {\n long long v7;\n long long v8;\n int v9;\n long long v10;\n long long v11;\n long long result;\n v7 = 16LL * a4;\n v8 = mochiReallocate(a1, 0LL, 0LL, v7);\n memset(v8, 0LL, v7);\n v9 = a5;\n v10 = 8LL * a5;\n v11 = mochiReallocate(a1, 0LL, 0LL, v10);\n memset(v11, 0LL, v10);\n result = mochiReallocate(a1, 0LL, 0LL, 64LL);\n *(uint32_t *)result = 9;\n *(uint8_t *)(result + 4) = 0;\n *(uint64_t *)(result + 8) = *(uint64_t *)(a1 + 248);\n *(uint64_t *)(a1 + 248) = result;\n *(uint64_t *)(result + 16) = a2;\n *(uint8_t *)(result + 24) = a3;\n *(uint64_t *)(result + 32) = v8;\n *(uint64_t *)(result + 48) = v11;\n *(uint32_t *)(result + 40) = a4;\n *(uint32_t *)(result + 56) = v9;\n return result;\n}\n# What is the source code?\n", "output": "type1* mochiNewContinuation(type2* var1, uint8_t* var2, uint8_t var3, int var4,\n int var5) {\n type3* var6 = func1(var1, var7, var4);\n memset(var6, 0, sizeof(var7) * var4);\n type4** var8 = func1(var1, var9*, var5);\n memset(var8, 0, sizeof(type4*) * var5);\n type1* var10 = func2(var1, var11);\n func3(var1, (type5*)var10, var12);\n var10->field1 = var2;\n var10->field2 = var3;\n var10->field3 = var6;\n var10->field4 = var8;\n var10->field5 = var4;\n var10->field6 = var5;\n return var10;\n}", "system": ""} +{"instruction": "", "input": "# This is the pseudo code:\nlong long throwException(long long a1, long long a2, long long a3, long long a4,\n long long a5, long long a6, __m128 a7, __m128 a8,\n __m128 a9, __m128 a10, __m128 a11, __m128 a12,\n __m128 a13, __m128 a14, char a15) {\n char v16;\n long long v17;\n long long v18;\n long long v19;\n long long v20;\n __m128 v21;\n __m128 v22;\n __m128 v23;\n __m128 v24;\n __m128 v25;\n __m128 v26;\n __m128 v27;\n __m128 v28;\n long long v29;\n long long StackTrace;\n long long v31;\n int v32;\n uint32_t v33[2];\n char *v34;\n char *v35;\n uint8_t v36[256];\n long long v37;\n long long v38;\n v21 = a7;\n v22 = a8;\n v23 = a9;\n v24 = a10;\n v25 = a11;\n v26 = a12;\n v27 = a13;\n v28 = a14;\n v20 = a6;\n v19 = a5;\n v18 = a4;\n v17 = a3;\n v38 = a1;\n v37 = a2;\n v35 = &v16;\n v34 = &a15;\n v33[1] = 48;\n v33[0] = 16;\n v32 = vsnprintf(v36, 255LL, a2, v33);\n v31 = copyString((long long)v36, v32);\n StackTrace = getStackTrace();\n v29 = newException(v31, v38);\n *(uint64_t *)(v29 + 56) = StackTrace;\n push(v29 | 18445618173802708992LL);\n if ((propagateException() & 1) == 0) exit(70LL);\n return v29;\n}\n# What is the source code?\n", "output": "type1* throwException(type2* var1, const char* var2, ...) {\n char var3[var4];\n type3 var5;\n func1(var5, var2);\n int var6 = vsnprintf(var3, var4, var2, var5);\n func2(var5);\n type4* var7 = copyString(var3, var6);\n type5* var8 = getStackTrace();\n type1* var9 = newException(var7, var1);\n var9->field1 = var8;\n push(func3(var9));\n if (!propagateException())\n exit(70);\n else\n return var9;\n}", "system": ""} diff --git a/sk2decompile/LLaMA-Factory/SK2DECOMPILE/train/norm2code-example.yaml b/sk2decompile/LLaMA-Factory/SK2DECOMPILE/train/norm2code-example.yaml new file mode 100644 index 0000000..809ef70 --- /dev/null +++ b/sk2decompile/LLaMA-Factory/SK2DECOMPILE/train/norm2code-example.yaml @@ -0,0 +1,39 @@ +### model +model_name_or_path: SK2DECOMPILE/saves/pseudo2norm-example +trust_remote_code: true + +### method +stage: sft +do_train: true +finetuning_type: full +deepspeed: examples/deepspeed/ds_z2_config.json # choices: [ds_z0_config.json, ds_z2_config.json, ds_z3_config.json] + +### dataset +dataset: norm2code-examples +template: sk2decompile +cutoff_len: 2048 +max_samples: 100 +overwrite_cache: true +preprocessing_num_workers: 16 +dataloader_num_workers: 4 + +### output +output_dir: SK2DECOMPILE/saves/norm2code-example +logging_steps: 10 +save_steps: 500 +plot_loss: true +overwrite_output_dir: true +save_only_model: false +report_to: none # choices: [none, wandb, tensorboard, swanlab, mlflow] + +### train +per_device_train_batch_size: 8 +gradient_accumulation_steps: 8 +learning_rate: 3.0e-6 +num_train_epochs: 2.0 +lr_scheduler_type: cosine_with_min_lr +lr_scheduler_kwargs: {"min_lr": 3.0e-7} +warmup_ratio: 0.02 +bf16: true +ddp_timeout: 180000000 +resume_from_checkpoint: null \ No newline at end of file diff --git a/sk2decompile/LLaMA-Factory/SK2DECOMPILE/train/pseudo2norm-example.yaml b/sk2decompile/LLaMA-Factory/SK2DECOMPILE/train/pseudo2norm-example.yaml new file mode 100644 index 0000000..174fb81 --- /dev/null +++ b/sk2decompile/LLaMA-Factory/SK2DECOMPILE/train/pseudo2norm-example.yaml @@ -0,0 +1,39 @@ +### model +model_name_or_path: LLM4Binary/llm4decompile-6.7b-v2 +trust_remote_code: true + +### method +stage: sft +do_train: true +finetuning_type: full +deepspeed: examples/deepspeed/ds_z2_config.json # choices: [ds_z0_config.json, ds_z2_config.json, ds_z3_config.json] + +### dataset +dataset: pseudo2norm-examples +template: sk2decompile +cutoff_len: 2048 +max_samples: 100 +overwrite_cache: true +preprocessing_num_workers: 16 +dataloader_num_workers: 4 + +### output +output_dir: SK2DECOMPILE/saves/pseudo2norm-example +logging_steps: 10 +save_steps: 500 +plot_loss: true +overwrite_output_dir: true +save_only_model: false +report_to: none # choices: [none, wandb, tensorboard, swanlab, mlflow] + +### train +per_device_train_batch_size: 8 +gradient_accumulation_steps: 8 +learning_rate: 3.0e-6 +num_train_epochs: 2.0 +lr_scheduler_type: cosine_with_min_lr +lr_scheduler_kwargs: {"min_lr": 3.0e-7} +warmup_ratio: 0.02 +bf16: true +ddp_timeout: 180000000 +resume_from_checkpoint: null \ No newline at end of file diff --git a/sk2decompile/Preprocess/format.py b/sk2decompile/Preprocess/format.py new file mode 100644 index 0000000..ed06ca7 --- /dev/null +++ b/sk2decompile/Preprocess/format.py @@ -0,0 +1,99 @@ +import re +import os +from tqdm import tqdm +import json +from multiprocessing import Pool, cpu_count +import argparse + +def good_func(func): + func = '{'.join(func.split('{')[1:]) + func_sp = func.split('\n') + total = 0 + for line in func_sp: + if len(line.strip())>=3: + total+=1 + if total>3 and total<300: + return True + return False + +def strip_empty(code): + return "\n".join(line for line in code.splitlines() if line.strip()) +def comment_remover(text): + def replacer(match): + s = match.group(0) + if s.startswith('/'): + return " " # note: a space and not an empty string + else: + return s + pattern = re.compile( + r'//.*?$|/\*.*?\*/|\'(?:\\.|[^\\\'])*\'|"(?:\\.|[^\\"])*"', + re.DOTALL | re.MULTILINE + ) + return re.sub(pattern, replacer, text) + +import subprocess + +def format_with_clang(func: str, style: str = "Google") -> str: + # Build the command + if not func: + return None + cmd = ["clang-format", f"--style={style}"] + try: + proc = subprocess.run( + cmd, + input=func, + text=True, + capture_output=True, + check=True, + timeout=0.5 + ) + return proc.stdout + except: + # print("clang-format failed") + return None + + +def process_record(record): + src = record.get("code_norm", "") + no_comments = comment_remover(src) + formatted = format_with_clang(no_comments) + if formatted is None: + return {} + cleaned = strip_empty(formatted) + record["code_format"] = cleaned + if not good_func(cleaned): + return {} + return record + +if __name__ == "__main__": + parser = argparse.ArgumentParser( + description="Parallel clang-format + strip for JSONL data" + ) + parser.add_argument("--input_json", type=str, default="train_norm.json") + parser.add_argument("--output_json", type=str, default="train_format.json") + parser.add_argument( + "-j", "--jobs", type=int, default=cpu_count()) + args = parser.parse_args() + + # 1) Load data + with open(args.input_json, "r", encoding="utf-8") as fp: + data = json.load(fp) + + # 2) Process in parallel with a progress bar + with Pool(processes=args.jobs) as pool: + results = list(tqdm(pool.imap(process_record, data), + total=len(data), + desc="Processing format")) + + results = [record for record in results if record]###############only keep good functions that have 3 lines + # 3) Write out + with open(args.output_json, "w", encoding="utf-8") as fp: + json.dump(results, fp, indent=4) + + import random + data_sample = random.sample(results, 2) + for record in data_sample: + print('________________format ori___________________') + print(record['code']) + print('________________format format___________________') + print(record['code_format']) diff --git a/sk2decompile/Preprocess/inf_type.py b/sk2decompile/Preprocess/inf_type.py new file mode 100644 index 0000000..a31373f --- /dev/null +++ b/sk2decompile/Preprocess/inf_type.py @@ -0,0 +1,144 @@ +import os +import sys +import json +import tempfile +import subprocess +from functools import partial +from tqdm import tqdm +import argparse +def process_one(sample_src, generator, solver): + """ + Write sample_src to temp file (sample.c), + run generator -> sample.cstr, + run solver -> sample.h, + read header, return header text. + Any temp files are cleaned up automatically. + """ + with tempfile.TemporaryDirectory() as tmpdir: + sample_path = os.path.join(tmpdir, "sample.c") + output_path = os.path.join(tmpdir, "sample.cstr") + header_path = os.path.join(tmpdir, "sample.h") + + # 1) dump the C鈥恠ource + with open(sample_path, "w", encoding="utf-8") as f: + f.write(sample_src) + + try: + # 2) run the generator + subprocess.run( + [generator, sample_path, "-o", output_path], + check=True, + stdout=subprocess.PIPE, + stderr=subprocess.PIPE, + timeout=1, + ) + # 3) run the solver + subprocess.run( + ["stack", "exec", solver, "--", "-i", output_path, "-o", header_path], + check=True, + stdout=subprocess.PIPE, + stderr=subprocess.PIPE, + timeout=1, + ) + + # 4) read back the .h + with open(header_path, "r", encoding="utf-8") as f: + return f.read() + + # except subprocess.CalledProcessError as e: + # sys.stderr.write( + # f"[ERROR] sample failed:\n" + # f" cmd: {e.cmd!r}\n" + # f" returncode: {e.returncode}\n" + # f" stdout: {e.stdout.decode(errors='ignore')}\n" + # f" stderr: {e.stderr.decode(errors='ignore')}\n" + # ) + except Exception as e: + return None + + +def main(): + p = argparse.ArgumentParser(description="Batch鈥恜rocess C samples into headers.") + p.add_argument("--input_json", default="train_norm.json", help="Path to JSON file with a list of {{'code': 鈥} entries") + p.add_argument("--output_name", default="train_type", help="Where to write the augmented JSON") + p.add_argument("--generator", default="/psychec/psychecgen", help="Path to your generator executable") + p.add_argument("--solver", default="/psychec/psychecsolver-exe", help="Name of your solver (for `stack exec 鈥)") + p.add_argument("--split", type=int, default=5, help="split the data to split parts") + p.add_argument("--idx", type=int, default=0, help="index of the split") + args = p.parse_args() + + # load + with open(args.input_json, "r", encoding="utf-8") as f: + samples = json.load(f) + + if args.split != 0: + SPLIT = int(len(samples) / args.split) + if args.idx == args.split - 1: + samples = samples[SPLIT * args.idx:] + else: + samples = samples[SPLIT * args.idx:SPLIT * (args.idx + 1)] + + # pull out all the code鈥恠trings + codes = [s["code_format"] for s in samples]############# code norm is the final expectation + + # prepare a partial that only needs the code + worker = partial(process_one, generator=args.generator, solver=args.solver) + + memo = {} + results = [] + count_non = 0 + for code in tqdm(codes): + if code not in memo: + header = worker(code) + if header == None: + count_non += 1 + memo[code] = header + results.append(memo[code]) + if len(results) % 5000 == 0: + print(f"len code:{len(codes)}, fail:{count_non}") + + for sample, header in zip(samples, results): + sample["header"] = header + + # dump out + with open(args.output_name+'_'+str(args.idx)+'.json', "w", encoding="utf-8") as f: + json.dump(samples, f, indent=2) + print(f"len code:{len(codes)}, fail:{count_non}") + +def folder(): + p = argparse.ArgumentParser(description="Batch鈥恜rocess C samples into headers.") + p.add_argument("--input_folder", default="/workspace/llm4binary/type/evaluation/result/exebench-8800_github1000") + # p.add_argument("--output_name", default="train_type", help="Where to write the augmented JSON") + p.add_argument("--generator", default="../psychec/psychecgen", help="Path to your generator executable") + p.add_argument("--solver", default="../psychec/psychecsolver-exe", help="Name of your solver (for `stack exec 鈥)") + # p.add_argument("--split", type=int, default=5, help="split the data to split parts") + # p.add_argument("--idx", type=int, default=0, help="index of the split") + args = p.parse_args() + worker = partial(process_one, generator=args.generator, solver=args.solver) + good = 0 + bad = 1 + for root, dirs, files in tqdm(os.walk(args.input_folder)): + for filename in files: + if filename.endswith(".c"): + file_path = os.path.join(root, filename) + with open(file_path, 'r') as f: + code = f.read() + header = worker(code) + with open(file_path.split('.c')[0] + ".h", 'w') as f: + if header: + good += 1 + f.write(header) + else: + bad += 1 + print(f'good:{good},bad:{bad}') + f.write("") + + +if __name__ == "__main__": + # folder() + main() + + + +# ../psychec/psychecgen ./output/ori/3.c -o ./output/cstr/3.cstr +# stack exec ../psychec/psychecsolver-exe -- -i ./output/cstr/3.cstr -o ./output/header/3.h diff --git a/sk2decompile/Preprocess/normalize_src_basedonpseudo.py b/sk2decompile/Preprocess/normalize_src_basedonpseudo.py new file mode 100644 index 0000000..795d66e --- /dev/null +++ b/sk2decompile/Preprocess/normalize_src_basedonpseudo.py @@ -0,0 +1,212 @@ +import re +import json +import argparse +from multiprocessing import Pool, cpu_count +from tqdm import tqdm # ✅ 添加进度条模块 +import random + +import subprocess + +def good_func(func): + func = '{'.join(func.split('{')[1:]) + func_sp = func.split('\n') + total = 0 + for line in func_sp: + if len(line.strip())>=3: + total+=1 + if total>3 and total<300: + return True + return False +def strip_empty(code): + return "\n".join(line for line in code.splitlines() if line.strip()) +def format_with_clang(func: str, style: str = "Google") -> str: + # Build the command + if not func: + return None + cmd = ["clang-format", f"--style={style}"] + try: + proc = subprocess.run( + cmd, + input=func, + text=True, + capture_output=True, + check=True, + timeout=0.5 + ) + return proc.stdout + except Exception as e: + # print(f"clang-format failed:{e}") + # print(func) + # print('-------------------------') + return None + + +# ---------------------------- +# 1. 十六进制转十进制 +# ---------------------------- +def hex_to_dec(text): + pattern = re.compile(r'\b(0x[0-9a-fA-F]+)([uUlL]{1,3})?\b') + def convert(match): + hex_part = match.group(1) + suffix = match.group(2) or "" + dec_value = str(int(hex_part, 16)) + return dec_value + suffix + return pattern.sub(convert, text) + + +# ---------------------------- +# 2. 删除特定关键字 +# ---------------------------- +def remove_keywords(text): + patterns = [ + r'\b__fastcall\b', + r'\b__cdecl\b', + r'\b__ptr32\b', + r'\b__noreturn\s+noreturn\b' + ] + combined_pattern = re.compile('|'.join(patterns)) + return combined_pattern.sub('', text) + + +# ---------------------------- +# 3. 替换 typedef 类型为原始类型 +# ---------------------------- +typedef_map = { + "cpu_set_t": "int", + "nl_item": "int", + "__time_t": "int", + "__mode_t": "unsigned short", + "__off64_t": "long long", + "__blksize_t": "long", + "__ino_t": "unsigned long", + "__blkcnt_t": "unsigned long long", + "__syscall_slong_t": "long", + "__ssize_t": "long int", + "wchar_t": "unsigned short int", + "wctype_t": "unsigned short int", + "__int64": "long long", + "__int32": "int", + "__int16": "short", + "__int8": "char", + "_QWORD": "uint64_t", + "_OWORD": "long double", + "_DWORD": "uint32_t", + "size_t": "unsigned int", + "_BYTE": "uint8_t", + "_TBYTE": "uint16_t", + "_BOOL8": "uint8_t", + "gcc_va_list": "va_list", + "_WORD": "unsigned short", + "_BOOL4": "int", + "__va_list_tag": "va_list", + "_IO_FILE": "FILE", + "DIR": "int", + "__fsword_t": "long", + "__kernel_ulong_t": "int", + "cc_t": "int", + "speed_t": "int", + "fd_set": "int", + "__suseconds_t": "int", + "_UNKNOWN": "void", + "__sighandler_t": "void (*)(int)", + "__compar_fn_t": "int (*)(const void *, const void *)", +} + +def replace_typedefs(text): + for alias, original in typedef_map.items(): + pattern = re.compile(rf'\b{re.escape(alias)}\b') + text = pattern.sub(original, text) + return text + + +# ---------------------------- +# 4. 删除注释 +# ---------------------------- +def remove_comments(text): + text = re.sub(r'/\*.*?\*/', '', text, flags=re.DOTALL) + text = re.sub(r'//.*?$', '', text, flags=re.MULTILINE) + return text + + +# ---------------------------- +# 5. 单条伪代码处理 +# ---------------------------- +def process_code(code_str): + code_str = remove_comments(code_str) + code_str = hex_to_dec(code_str) + code_str = remove_keywords(code_str) + code_str = replace_typedefs(code_str) + return code_str + + +# 包装 process_code，使其接受一个 dict 并处理字段 +def process_entry(entry, key_name='pseudo'): + # result = {} + + # # 原始字段保留 + # result['ida_pseudo'] = entry.get('ida_pseudo', '') + # result['ida_strip_pseudo'] = entry.get('ida_strip_pseudo', '') + + # # 分别处理两个字段 + # result['ida_pseudo_result'] = process_code(result['ida_pseudo']) + # result['ida_strip_pseudo_result'] = process_code(result['ida_strip_pseudo']) + + result = process_code(entry.get(key_name, '')) + if not result.strip(): + return '' + formatted = format_with_clang(result) + if formatted is None: + return None + cleaned = strip_empty(formatted) + + return cleaned + +# 主函数 +def normalize_code_list_parallel(input_json, output_json, key_name='pseudo', num_workers=None, remove=1): + with open(input_json, 'r', encoding='utf-8') as f: + data = json.load(f) + + if not isinstance(data, list): + raise ValueError("输入 JSON 应为对象数组") + + num_workers = num_workers or cpu_count() + print(f"[+] 开始处理 {len(data)} 条记录，使用 {num_workers} 个进程") + + from functools import partial + process_entry_key = partial(process_entry, key_name=key_name) + + with Pool(processes=num_workers) as pool: + result = list(tqdm(pool.imap(process_entry_key, data), total=len(data), desc="Processing")) + + data_good = [] + for record, norm in zip(data, result): + if norm: + if not good_func(norm): + continue + record[f"{key_name}_norm"] = norm + data_good.append(record) + elif norm is None: + if not remove: + record[f"{key_name}_norm"] = record[f"{key_name}"] + data_good.append(record) + + with open(output_json, 'w', encoding='utf-8') as f: + json.dump(data_good, f, indent=2, ensure_ascii=False) + + print(f"[✓] 完成处理：{input_json}:{len(data)} → {output_json}:{len(data_good)}") + + + +# ---------------------------- +# 7. 命令行入口 +# ---------------------------- +if __name__ == '__main__': + parser = argparse.ArgumentParser(description="并行处理 IDA 伪代码字符串列表") + parser.add_argument('--input_json', default="exebench_format_top1p.json", help='输入 JSON 文件路径（每项为字符串）') + parser.add_argument('--output_json', default="exebench_format_pseudo_top1p.json", help='输出 JSON 文件路径') + parser.add_argument('--key_name', default="pseudo", help='输出 JSON 文件路径') + parser.add_argument('--workers', type=int, default=32, help='进程数默认使用8核心') + parser.add_argument('--remove', type=int, default=1, help='remove fail cases') + args = parser.parse_args() + + normalize_code_list_parallel(args.input_json, args.output_json, args.key_name, args.workers, args.remove) \ No newline at end of file diff --git a/sk2decompile/Preprocess/standard_c.txt b/sk2decompile/Preprocess/standard_c.txt new file mode 100644 index 0000000..0631515 --- /dev/null +++ b/sk2decompile/Preprocess/standard_c.txt @@ -0,0 +1 @@ +printf, scanf, fprintf, fscanf, sprintf, snprintf, sscanf, fopen, fclose, fread, fwrite, fgetc, fputc, fgets, fputs, fseek, ftell, rewind, remove, rename, tmpfile, tmpnam, clearerr, feof, ferror, perror, malloc, calloc, realloc, free, atoi, atol, atof, strtol, strtoul, strtod, rand, srand, exit, abort, atexit, system, getenv, abs, labs, div, ldiv, qsort, bsearch, strcpy, strncpy, strcat, strncat, strcmp, strncmp, strlen, strchr, strrchr, strstr, strtok, memset, memcpy, memmove, memcmp, memchr, strerror, sin, cos, tan, asin, acos, atan, atan2, sinh, cosh, tanh, exp, log, log10, pow, sqrt, cbrt, hypot, ceil, floor, round, fabs, fmod, ldexp, frexp, modf, erf, erfc, time, clock, difftime, mktime, asctime, ctime, gmtime, localtime, strftime, isalnum, isalpha, iscntrl, isdigit, isgraph, islower, isprint, ispunct, isspace, isupper, isxdigit, isblank, tolower, toupper,printf, fprintf, sprintf, snprintf, vprintf, vfprintf, vsprintf, vsnprintf, scanf, fscanf, sscanf, getchar, putchar, fgets, fputs, fgetc, fputc, fopen, fclose, fread, fwrite, fflush, rewind, fseek, ftell, perror, malloc, calloc, realloc, free, exit, atexit, system, getenv, atoi, atol, atoll, atof, strtol, strtoul, strtod, rand, srand, bsearch, qsort, abs, labs, llabs, strcpy, strncpy, strcat, strncat, strcmp, strncmp, strlen, strchr, strrchr, strstr, strtok, memset, memcpy, memmove, memcmp, isalpha, isdigit, isalnum, isspace, toupper, tolower, sin, cos, tan, asin, acos, atan, atan2, sinh, cosh, tanh, exp, log, log10, pow, sqrt, ceil, floor, fabs, fmod, time, clock, difftime, mktime, localtime, assert, strerror, setlocale, signal, raise, feof, ferror diff --git a/sk2decompile/README.md b/sk2decompile/README.md new file mode 100644 index 0000000..b48dcdb --- /dev/null +++ b/sk2decompile/README.md @@ -0,0 +1,195 @@ +# SK²Decompile + +**SK²Decompile: LLM-based Two-Phase Binary Decompilation from Skeleton to Skin** + +

+ 🚀 Quick Start + | 🤖 Training Pipeline + | 📊 Evaluation + | 📝 Citation +

+ +## Overview + +SK²Decompile is a novel two-phase framework for binary decompilation using Large Language Models (LLMs). Our approach decomposes the complex decompilation task into two manageable phases: + +- **Phase 1 Structure Recovery (Skeleton)**: Transform binary/pseudo-code into obfuscated intermediate representations 🤗 [HF Link](https://huggingface.co/LLM4Binary/sk2decompile-struct-6.7b) +- **Phase 2 Identifier Naming (Skin)**: Generate human-readable source code with meaningful identifiers 🤗 [HF Link](https://huggingface.co/LLM4Binary/sk2decompile-ident-6.7) + +This repository contains the complete implementation of our paper, including data preprocessing tools, training scripts, and evaluation benchmarks. + +## 🏗️ Architecture + +Our two-phase approach is inspired by the skeleton-to-skin metaphor: + +``` +Binary/Pseudo-code → [Phase 1: Skeleton] → Normalized IR → [Phase 2: Skin] → Source Code + ↓ ↓ + (Structure Extraction) (Identifier Recovery) +``` + +## 📁 Repository Structure + +``` +SK2Decompile/ +├── Preprocess/ # Data preprocessing and normalization tools +├── LLaMA-Factory/ # Supervised Fine-Tuning (SFT) implementation +├── verl/ # Reinforcement Learning (RL) with compiler-based rewards +├── evaluation/ # Comprehensive evaluation suite +└── README.md # This file +``` + +## 🚀 Quick Start + +### Prerequisites + +- Python 3.8+ +- CUDA 11.0+ +- PyTorch 2.0+ +- 40GB+ GPU memory (recommended) +- [Psychec](https://github.com/ltcmelo/psychec.git) (for data preprocessing) + +### Installation + +```bash +git clone https://github.com/yourusername/SK2Decompile.git +cd SK2Decompile +``` + +## 🤖 Training Pipeline + +### Phase 0: Data Preprocessing + +Transform raw pseudo-code into normalized representations suitable for training: + +```bash +cd Preprocess + +# Requirements +pip install tree-sitter==0.24.0 tree-sitter-c==0.23.4 tqdm + +# Step 1: Normalize pseudo-code according to R2I standard +python3 normalize_pseudo.py --input_json exebench_c.json --output_json exebench_pseudonorm.json --key_name pseudo + +# Step 2: Obfuscate source code to generate IR +python3 normalize_src_basedonpseudo.py --input_json exebench_pseudonorm.json --output_json exebench_norm_top0.json --top 0 --pseudo pseudo_norm + +# Step 3: Format codes with clang-format +python3 format.py --input exebench_norm_top0.json --output exebench_format_top0.json + +# Step 4: Infer types for obfuscated IR (used for compiler-based rewards) +python3 inf_type.py --input_json train_format_top0.json --output_name train_format_top0_type \ + --generator ../psychec/psychecgen --solver ../psychec/psychecsolver-exe --split 2 --idx 0 +``` + +### Phase 1: Supervised Fine-Tuning (SFT) + +Our two-phase SFT approach trains specialized models for each transformation: + +#### Setup LLaMA-Factory +```bash +cd ../LLaMA-Factory +# Follow installation instructions in LLaMA-Factory/README.md +``` + +#### Train Models +```bash +# Train Skeleton Model (pseudo2norm) +llamafactory-cli train LLaMA-Factory/SK2DECOMPILE/train/pseudo2norm-example.yaml + +# Train Skin Model (norm2code) +llamafactory-cli train LLaMA-Factory/SK2DECOMPILE/train/norm2code-example.yaml +``` + +**Sample Training Data:** +- Pseudo2Norm: `LLaMA-Factory/SK2DECOMPILE/data/pseudo2norm-examples.jsonl` +- Norm2Code: `LLaMA-Factory/SK2DECOMPILE/data/norm2code-examples.jsonl` + +### Phase 2: Reinforcement Learning (RL) + +Fine-tune models using compiler-based rewards for improved correctness: + +#### Setup VERL +```bash +cd ../verl +# Follow installation instructions in verl/README.md +``` + +#### Run RL Training +```bash +bash verl/SK2DECOMPILE/train/sk2decompile-rl.sh +``` + +**RL Training Data:** `verl/SK2DECOMPILE/data/sk2decompile-rl-examples.parquet` + +### Phase 3: Evaluation + +Comprehensive evaluation on standard benchmarks: + +```bash +cd ../evaluation +# evaluate exe_rate +python evaluate_exe.py --json_file your_json_file_path + --dcompilers decompiler1,decompiler2,...,decompilerN +# evaluate r2i +python evaluate_r2i.py --json_file your_json_file_path + --dcompilers decompiler1,decompiler2,...,decompilerN + --output_path your_output_path +# evaluate gpt-judge +python gpt_judge.py --json_file your_json_file_path + --decompilers decompiler1,decompiler2,...,decompilerN + --opt OPT + --api_key your_openai_api_key +``` + +## 📊 Results + +Our approach achieves state-of-the-art performance: + +| Metric | Dataset | Improvement | +|--------|---------|-------------| +| **Re-executability** | HumanEval | **+21.6%** over GPT-5-mini | +| **R2I Score** | GitHub2025 | **+29.4%** over Idioms | + +## 🔬 Key Innovations + +1. **Two-Phase Decomposition**: Separating structure recovery from identifier prediction +2. **Compiler-Based RL**: Using compiler feedback as reward signal +3. **Generic Placeholders**: Language-agnostic intermediate representation +4. **Independent Optimization**: Separate RL objectives for each phase + +## 📄 Citation + +If you use SK²Decompile in your research, please cite our paper: + +```bibtex +@article{sk2decompile2024, + title={SK²Decompile: From Skeleton to Skin - A Two-Phase Approach for Binary Decompilation}, + author={Your Name and Collaborators}, + journal={arXiv preprint arXiv:XXXX.XXXXX}, + year={2024} +} +``` + +## 🤝 Contributing + +We welcome contributions! Areas of interest: +- Support for additional architectures (ARM, RISC-V) +- Integration with more decompilation tools +- Improved intermediate representations +- Multi-language support + +## 📄 License + +This project is licensed under the MIT License. See LICENSE file for details. + +## 🙏 Acknowledgments + +We thank the developers of: +- [LLaMA-Factory](https://github.com/hiyouga/LLaMA-Factory) for the SFT framework +- [VERL](https://github.com/volcengine/verl) for the RL implementation +- [Psychec](https://github.com/ltcmelo/psychec.git) for C type inference + +--- + +For detailed documentation on each component, please refer to the individual README files in each directory. diff --git a/sk2decompile/evaluation/data/humaneval_normsrcpseudo.json b/sk2decompile/evaluation/data/humaneval_normsrcpseudo.json new file mode 100644 index 0000000..cc1cef5 --- /dev/null +++ b/sk2decompile/evaluation/data/humaneval_normsrcpseudo.json @@ -0,0 +1,9641 @@ +[ + { + "index": "HumanEval-C-0", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int func0(float numbers[], int size, float threshold) {\n int i, j;\n for (i = 0; i < size; i++)\n for (j = i + 1; j < size; j++)\n if (fabs(numbers[i] - numbers[j]) < threshold) return 1;\n return 0;\n}", + "test": "#include \n#include \n\nint main(){\n float a[] = {1.0, 2.0, 3.9, 4.0, 5.0, 2.2};\n assert(func0(a, 6, 0.3) == 1);\n assert(func0(a, 6, 0.05) == 0);\n\n float b[] = {1.0, 2.0, 5.9, 4.0, 5.0};\n assert(func0(b, 5, 0.95) == 1);\n assert(func0(b, 5, 0.8) == 0);\n \n float c[] = {1.0, 2.0, 3.0, 4.0, 5.0};\n assert(func0(c, 5, 2.0) == 1);\n\n float d[] = {1.1, 2.2, 3.1, 4.1, 5.1};\n assert(func0(d, 5, 1.0) == 1);\n assert(func0(d, 5, 0.5) == 0);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmovss [rbp+var_20], xmm0\nmov [rbp+var_8], 0\njmp short loc_11F1\nloc_1186:\nmov eax, [rbp+var_8]\nadd eax, 1\nmov [rbp+var_4], eax\njmp short loc_11E5\nloc_1191:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm1, dword ptr [rax]\nsubss xmm0, xmm1\nmovss xmm1, cs:dword_20D0\nandps xmm1, xmm0\nmovss xmm0, [rbp+var_20]\ncomiss xmm0, xmm1\njbe short loc_11E1\nmov eax, 1\njmp short loc_11FE\nloc_11E1:\nadd [rbp+var_4], 1\nloc_11E5:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1191\nadd [rbp+var_8], 1\nloc_11F1:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_1186\nmov eax, 0\nloc_11FE:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, float a3)\n{\n int i; // [rsp+18h] [rbp-8h]\n int j; // [rsp+1Ch] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( a3 > fabs(*(float *)(4LL * i + a1) - *(float *)(4LL * j + a1)) )\n return 1LL;\n }\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmovss [rbp+var_20], xmm0\nmov [rbp+var_8], 0\njmp short loc_11F1\nloc_1186:\nmov eax, [rbp+var_8]\nadd eax, 1\nmov [rbp+var_4], eax\njmp short loc_11E5\nloc_1191:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm1, dword ptr [rax]\nsubss xmm0, xmm1\nmovss xmm1, cs:dword_20D0\nandps xmm1, xmm0\nmovss xmm0, [rbp+var_20]\ncomiss xmm0, xmm1\njbe short loc_11E1\nmov eax, 1\njmp short loc_11FE\nloc_11E1:\nadd [rbp+var_4], 1\nloc_11E5:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1191\nadd [rbp+var_8], 1\nloc_11F1:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_1186\nmov eax, 0\nloc_11FE:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, float a3)\n{\n int i; // [rsp+18h] [rbp-8h]\n int j; // [rsp+1Ch] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( a3 > fabs(*(float *)(4LL * i + a1) - *(float *)(4LL * j + a1)) )\n return 1LL;\n }\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, float a3) {\n int i;\n int j;\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if (a3 > fabs(*(float *)(4LL * i + a1) - *(float *)(4LL * j + a1)))\n return 1LL;\n }\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, float a3) {\n int i;\n int j;\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if (a3 > fabs(*(float *)(4LL * i + a1) - *(float *)(4LL * j + a1)))\n return 1LL;\n }\n }\n return 0LL;\n}" + }, + { + "index": "HumanEval-C-0", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int func0(float numbers[], int size, float threshold) {\n int i, j;\n for (i = 0; i < size; i++)\n for (j = i + 1; j < size; j++)\n if (fabs(numbers[i] - numbers[j]) < threshold) return 1;\n return 0;\n}", + "test": "#include \n#include \n\nint main(){\n float a[] = {1.0, 2.0, 3.9, 4.0, 5.0, 2.2};\n assert(func0(a, 6, 0.3) == 1);\n assert(func0(a, 6, 0.05) == 0);\n\n float b[] = {1.0, 2.0, 5.9, 4.0, 5.0};\n assert(func0(b, 5, 0.95) == 1);\n assert(func0(b, 5, 0.8) == 0);\n \n float c[] = {1.0, 2.0, 3.0, 4.0, 5.0};\n assert(func0(c, 5, 2.0) == 1);\n\n float d[] = {1.1, 2.2, 3.1, 4.1, 5.1};\n assert(func0(d, 5, 1.0) == 1);\n assert(func0(d, 5, 0.5) == 0);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11BD\nmov ecx, esi\nmovsxd r8, esi\nmov edx, 1\nmovss xmm3, cs:dword_20E0\nloc_1183:\ncmp rdx, rcx\njz short loc_11C3\nmovss xmm2, dword ptr [rdi+rdx*4-4]\nmov rax, rdx\nloc_1191:\nmovaps xmm1, xmm2\nsubss xmm1, dword ptr [rdi+rax*4]\nandps xmm1, xmm3\ncomiss xmm0, xmm1\nja short loc_11C9\nadd rax, 1\ncmp esi, eax\njg short loc_1191\nlea rax, [rdx+1]\ncmp rdx, r8\njz short loc_11B7\nmov rdx, rax\njmp short loc_1183\nloc_11B7:\nmov eax, 0\nretn\nloc_11BD:\nmov eax, 0\nretn\nloc_11C3:\nmov eax, 0\nretn\nloc_11C9:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, float a3)\n{\n __int64 v3; // rdx\n __int64 v4; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v3 = 1LL;\n while ( 2 )\n {\n if ( v3 == a2 )\n return 0LL;\n v4 = v3;\n do\n {\n if ( a3 > fabs(*(float *)(a1 + 4 * v3 - 4) - *(float *)(a1 + 4 * v4)) )\n return 1LL;\n ++v4;\n }\n while ( a2 > (int)v4 );\n if ( v3 != a2 )\n {\n ++v3;\n continue;\n }\n break;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11BD\nmov ecx, esi\nmovsxd r8, esi\nmov edx, 1\nmovss xmm3, cs:dword_20E0\nloc_1183:\ncmp rdx, rcx\njz short loc_11C3\nmovss xmm2, dword ptr [rdi+rdx*4-4]\nmov rax, rdx\nloc_1191:\nmovaps xmm1, xmm2\nsubss xmm1, dword ptr [rdi+rax*4]\nandps xmm1, xmm3\ncomiss xmm0, xmm1\nja short loc_11C9\nadd rax, 1\ncmp esi, eax\njg short loc_1191\nlea rax, [rdx+1]\ncmp rdx, r8\njz short loc_11B7\nmov rdx, rax\njmp short loc_1183\nloc_11B7:\nmov eax, 0\nretn\nloc_11BD:\nmov eax, 0\nretn\nloc_11C3:\nmov eax, 0\nretn\nloc_11C9:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, float a3)\n{\n __int64 v3; // rdx\n __int64 v4; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v3 = 1LL;\n while ( 2 )\n {\n if ( v3 == a2 )\n return 0LL;\n v4 = v3;\n do\n {\n if ( a3 > fabs(*(float *)(a1 + 4 * v3 - 4) - *(float *)(a1 + 4 * v4)) )\n return 1LL;\n ++v4;\n }\n while ( a2 > (int)v4 );\n if ( v3 != a2 )\n {\n ++v3;\n continue;\n }\n break;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, float a3) {\n long long v3;\n long long v4;\n if (a2 <= 0) return 0LL;\n v3 = 1LL;\n while (2) {\n if (v3 == a2) return 0LL;\n v4 = v3;\n do {\n if (a3 > fabs(*(float *)(a1 + 4 * v3 - 4) - *(float *)(a1 + 4 * v4)))\n return 1LL;\n ++v4;\n } while (a2 > (int)v4);\n if (v3 != a2) {\n ++v3;\n continue;\n }\n break;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, float a3) {\n long long v3;\n long long v4;\n if (a2 <= 0) return 0LL;\n v3 = 1LL;\n while (2) {\n if (v3 == a2) return 0LL;\n v4 = v3;\n do {\n if (a3 > fabs(*(float *)(a1 + 4 * v3 - 4) - *(float *)(a1 + 4 * v4)))\n return 1LL;\n ++v4;\n } while (a2 > (int)v4);\n if (v3 != a2) {\n ++v3;\n continue;\n }\n break;\n }\n return 0LL;\n}" + }, + { + "index": "HumanEval-C-0", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int func0(float numbers[], int size, float threshold) {\n int i, j;\n for (i = 0; i < size; i++)\n for (j = i + 1; j < size; j++)\n if (fabs(numbers[i] - numbers[j]) < threshold) return 1;\n return 0;\n}", + "test": "#include \n#include \n\nint main(){\n float a[] = {1.0, 2.0, 3.9, 4.0, 5.0, 2.2};\n assert(func0(a, 6, 0.3) == 1);\n assert(func0(a, 6, 0.05) == 0);\n\n float b[] = {1.0, 2.0, 5.9, 4.0, 5.0};\n assert(func0(b, 5, 0.95) == 1);\n assert(func0(b, 5, 0.8) == 0);\n \n float c[] = {1.0, 2.0, 3.0, 4.0, 5.0};\n assert(func0(c, 5, 2.0) == 1);\n\n float d[] = {1.1, 2.2, 3.1, 4.1, 5.1};\n assert(func0(d, 5, 1.0) == 1);\n assert(func0(d, 5, 0.5) == 0);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_13F9\nmov ecx, esi\nmov edx, 1\nmovss xmm3, cs:dword_20E0\ncmp rdx, rcx\njz short loc_13F9\nloc_13BC:\nmovss xmm2, dword ptr [rdi+rdx*4-4]\nmov rax, rdx\njmp short loc_13D8\nloc_13D0:\nadd rax, 1\ncmp esi, eax\njle short loc_13F0\nloc_13D8:\nmovaps xmm1, xmm2\nsubss xmm1, dword ptr [rdi+rax*4]\nandps xmm1, xmm3\ncomiss xmm0, xmm1\njbe short loc_13D0\nmov eax, 1\nretn\nloc_13F0:\nadd rdx, 1\ncmp rdx, rcx\njnz short loc_13BC\nloc_13F9:\nxor eax, eax\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, float a3)\n{\n __int64 i; // rdx\n __int64 v4; // rax\n\n if ( a2 > 0 )\n {\n for ( i = 1LL; i != a2; ++i )\n {\n v4 = i;\n do\n {\n if ( a3 > fabs(*(float *)(a1 + 4 * i - 4) - *(float *)(a1 + 4 * v4)) )\n return 1LL;\n ++v4;\n }\n while ( a2 > (int)v4 );\n }\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_13A0:\nendbr64\ntest esi, esi\njle short loc_13F9\nmov ecx, esi\nmov edx, 1\nmovss xmm3, cs:dword_20E0\ncmp rdx, rcx\njz short loc_13F9\nloc_13BC:\nmovss xmm2, dword ptr [rdi+rdx*4-4]\nmov rax, rdx\njmp short loc_13D8\nloc_13D0:\nadd rax, 1\ncmp esi, eax\njle short loc_13F0\nloc_13D8:\nmovaps xmm1, xmm2\nsubss xmm1, dword ptr [rdi+rax*4]\nandps xmm1, xmm3\ncomiss xmm0, xmm1\njbe short loc_13D0\nmov eax, 1\nretn\nloc_13F0:\nadd rdx, 1\ncmp rdx, rcx\njnz short loc_13BC\nloc_13F9:\nxor eax, eax\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_13A0(__int64 a1, int a2, float a3)\n{\n __int64 i; // rdx\n __int64 v4; // rax\n\n if ( a2 > 0 )\n {\n for ( i = 1LL; i != a2; ++i )\n {\n v4 = i;\n do\n {\n if ( a3 > fabs(*(float *)(a1 + 4 * i - 4) - *(float *)(a1 + 4 * v4)) )\n return 1LL;\n ++v4;\n }\n while ( a2 > (int)v4 );\n }\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_13A0(long long a1, int a2, float a3) {\n long long i;\n long long v4;\n if (a2 > 0) {\n for (i = 1LL; i != a2; ++i) {\n v4 = i;\n do {\n if (a3 > fabs(*(float *)(a1 + 4 * i - 4) - *(float *)(a1 + 4 * v4)))\n return 1LL;\n ++v4;\n } while (a2 > (int)v4);\n }\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, float a3) {\n long long i;\n long long v4;\n if (a2 > 0) {\n for (i = 1LL; i != a2; ++i) {\n v4 = i;\n do {\n if (a3 > fabs(*(float *)(a1 + 4 * i - 4) - *(float *)(a1 + 4 * v4)))\n return 1LL;\n ++v4;\n } while (a2 > (int)v4);\n }\n }\n return 0LL;\n}" + }, + { + "index": "HumanEval-C-1", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char** func0(const char* paren_string, int* group_count) {\n int length = strlen(paren_string);\n int level = 0;\n int capacity = 10;\n char** groups = malloc(capacity * sizeof(char*));\n char* buffer = malloc(length + 1);\n int buffer_index = 0;\n *group_count = 0;\n for (int i = 0; i < length; ++i) {\n char chr = paren_string[i];\n if (chr == '(') {\n level++;\n buffer[buffer_index++] = chr;\n } else if (chr == ')') {\n level--;\n buffer[buffer_index++] = chr;\n if (level == 0) {\n buffer[buffer_index] = '\\0';\n groups[*group_count] = strdup(buffer);\n (*group_count)++;\n if (*group_count >= capacity) {\n capacity *= 2;\n groups = realloc(groups, capacity * sizeof(char*));\n }\n buffer_index = 0;\n }\n }\n }\n free(buffer);\n return groups;\n}", + "test": "#include \n#include \n#include \n#include \n\nint issame(char** a, int a_size, const char* b[], int b_size) {\n if (a_size != b_size) {\n return 0;\n }\n for (int i = 0; i < a_size; i++) {\n if (strcmp(a[i], b[i]) != 0) {\n return 0;\n }\n }\n return 1;\n}\n\nvoid free_groups(char** groups, int size) {\n for (int i = 0; i < size; i++) {\n free(groups[i]);\n }\n free(groups);\n}\n\nint main() {\n int group_count;\n char** result;\n\n result = func0(\"(()()) ((())) () ((())()())\", &group_count);\n const char* expected1[] = {\"(()())\", \"((()))\", \"()\", \"((())()())\"};\n assert(issame(result, group_count, expected1, 4));\n free_groups(result, group_count);\n\n result = func0(\"() (()) ((())) (((())))\", &group_count);\n const char* expected2[] = {\"()\", \"(())\", \"((()))\", \"(((())))\"};\n assert(issame(result, group_count, expected2, 4));\n free_groups(result, group_count);\n\n result = func0(\"(()(())((())))\", &group_count);\n const char* expected3[] = {\"(()(())((())))\"};\n assert(issame(result, group_count, expected3, 1));\n free_groups(result, group_count);\n\n result = func0(\"( ) (( )) (( )( ))\", &group_count);\n const char* expected4[] = {\"()\", \"(())\", \"(()())\"};\n assert(issame(result, group_count, expected4, 3));\n free_groups(result, group_count);\n\n printf(\"All tests passed.\\n\");\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 48h\nmov [rbp+s], rdi\nmov [rbp+var_50], rsi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_24], eax\nmov [rbp+var_34], 0\nmov [rbp+var_30], 0Ah\nmov eax, [rbp+var_30]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov eax, [rbp+var_24]\nadd eax, 1\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_2C], 0\nmov rax, [rbp+var_50]\nmov dword ptr [rax], 0\nmov [rbp+var_28], 0\njmp loc_13A8\nloc_12C1:\nmov eax, [rbp+var_28]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_35], al\ncmp [rbp+var_35], 28h ; '('\njnz short loc_12FC\nadd [rbp+var_34], 1\nmov eax, [rbp+var_2C]\nlea edx, [rax+1]\nmov [rbp+var_2C], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmovzx eax, [rbp+var_35]\nmov [rdx], al\njmp loc_13A4\nloc_12FC:\ncmp [rbp+var_35], 29h ; ')'\njnz loc_13A4\nsub [rbp+var_34], 1\nmov eax, [rbp+var_2C]\nlea edx, [rax+1]\nmov [rbp+var_2C], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmovzx eax, [rbp+var_35]\nmov [rdx], al\ncmp [rbp+var_34], 0\njnz short loc_13A4\nmov eax, [rbp+var_2C]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+var_50]\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nlea rbx, [rdx+rax]\nmov rax, [rbp+var_18]\nmov rdi, rax; s\ncall _strdup\nmov [rbx], rax\nmov rax, [rbp+var_50]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_50]\nmov [rax], edx\nmov rax, [rbp+var_50]\nmov eax, [rax]\ncmp [rbp+var_30], eax\njg short loc_139D\nshl [rbp+var_30], 1\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nmov rsi, rdx; size\nmov rdi, rax; ptr\ncall _realloc\nmov [rbp+ptr], rax\nloc_139D:\nmov [rbp+var_2C], 0\nloc_13A4:\nadd [rbp+var_28], 1\nloc_13A8:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_24]\njl loc_12C1\nmov rax, [rbp+var_18]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+ptr]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(const char *a1, int *a2)\n{\n int v2; // eax\n int v3; // eax\n char **v4; // rbx\n char v6; // [rsp+1Bh] [rbp-35h]\n int v7; // [rsp+1Ch] [rbp-34h]\n int v8; // [rsp+20h] [rbp-30h]\n int v9; // [rsp+24h] [rbp-2Ch]\n int i; // [rsp+28h] [rbp-28h]\n int v11; // [rsp+2Ch] [rbp-24h]\n char *ptr; // [rsp+30h] [rbp-20h]\n char *v13; // [rsp+38h] [rbp-18h]\n\n v11 = strlen(a1);\n v7 = 0;\n v8 = 10;\n ptr = (char *)malloc(0x50uLL);\n v13 = (char *)malloc(v11 + 1);\n v9 = 0;\n *a2 = 0;\n for ( i = 0; i < v11; ++i )\n {\n v6 = a1[i];\n if ( v6 == 40 )\n {\n ++v7;\n v2 = v9++;\n v13[v2] = 40;\n }\n else if ( v6 == 41 )\n {\n --v7;\n v3 = v9++;\n v13[v3] = 41;\n if ( !v7 )\n {\n v13[v9] = 0;\n v4 = (char **)&ptr[8 * *a2];\n *v4 = strdup(v13);\n if ( v8 <= ++*a2 )\n {\n v8 *= 2;\n ptr = (char *)realloc(ptr, 8LL * v8);\n }\n v9 = 0;\n }\n }\n }\n free(v13);\n return ptr;\n}", + "ida_strip_asm": "sub_1249:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 48h\nmov [rbp+s], rdi\nmov [rbp+var_50], rsi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_24], eax\nmov [rbp+var_34], 0\nmov [rbp+var_30], 0Ah\nmov eax, [rbp+var_30]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov eax, [rbp+var_24]\nadd eax, 1\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_2C], 0\nmov rax, [rbp+var_50]\nmov dword ptr [rax], 0\nmov [rbp+var_28], 0\njmp loc_13A8\nloc_12C1:\nmov eax, [rbp+var_28]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_35], al\ncmp [rbp+var_35], 28h ; '('\njnz short loc_12FC\nadd [rbp+var_34], 1\nmov eax, [rbp+var_2C]\nlea edx, [rax+1]\nmov [rbp+var_2C], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmovzx eax, [rbp+var_35]\nmov [rdx], al\njmp loc_13A4\nloc_12FC:\ncmp [rbp+var_35], 29h ; ')'\njnz loc_13A4\nsub [rbp+var_34], 1\nmov eax, [rbp+var_2C]\nlea edx, [rax+1]\nmov [rbp+var_2C], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmovzx eax, [rbp+var_35]\nmov [rdx], al\ncmp [rbp+var_34], 0\njnz short loc_13A4\nmov eax, [rbp+var_2C]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+var_50]\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nlea rbx, [rdx+rax]\nmov rax, [rbp+var_18]\nmov rdi, rax; s\ncall _strdup\nmov [rbx], rax\nmov rax, [rbp+var_50]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_50]\nmov [rax], edx\nmov rax, [rbp+var_50]\nmov eax, [rax]\ncmp [rbp+var_30], eax\njg short loc_139D\nshl [rbp+var_30], 1\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nmov rsi, rdx; size\nmov rdi, rax; ptr\ncall _realloc\nmov [rbp+ptr], rax\nloc_139D:\nmov [rbp+var_2C], 0\nloc_13A4:\nadd [rbp+var_28], 1\nloc_13A8:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_24]\njl loc_12C1\nmov rax, [rbp+var_18]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+ptr]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1249(const char *a1, int *a2)\n{\n int v2; // eax\n int v3; // eax\n char **v4; // rbx\n char v6; // [rsp+1Bh] [rbp-35h]\n int v7; // [rsp+1Ch] [rbp-34h]\n int v8; // [rsp+20h] [rbp-30h]\n int v9; // [rsp+24h] [rbp-2Ch]\n int i; // [rsp+28h] [rbp-28h]\n int v11; // [rsp+2Ch] [rbp-24h]\n char *ptr; // [rsp+30h] [rbp-20h]\n char *v13; // [rsp+38h] [rbp-18h]\n\n v11 = strlen(a1);\n v7 = 0;\n v8 = 10;\n ptr = (char *)malloc(0x50uLL);\n v13 = (char *)malloc(v11 + 1);\n v9 = 0;\n *a2 = 0;\n for ( i = 0; i < v11; ++i )\n {\n v6 = a1[i];\n if ( v6 == 40 )\n {\n ++v7;\n v2 = v9++;\n v13[v2] = 40;\n }\n else if ( v6 == 41 )\n {\n --v7;\n v3 = v9++;\n v13[v3] = 41;\n if ( !v7 )\n {\n v13[v9] = 0;\n v4 = (char **)&ptr[8 * *a2];\n *v4 = strdup(v13);\n if ( v8 <= ++*a2 )\n {\n v8 *= 2;\n ptr = (char *)realloc(ptr, 8LL * v8);\n }\n v9 = 0;\n }\n }\n }\n free(v13);\n return ptr;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1249(const char *a1, int *a2) {\n int v2;\n int v3;\n char **v4;\n char v6;\n int v7;\n int v8;\n int v9;\n int i;\n int v11;\n char *ptr;\n char *v13;\n v11 = strlen(a1);\n v7 = 0;\n v8 = 10;\n ptr = (char *)malloc(80uLL);\n v13 = (char *)malloc(v11 + 1);\n v9 = 0;\n *a2 = 0;\n for (i = 0; i < v11; ++i) {\n v6 = a1[i];\n if (v6 == 40) {\n ++v7;\n v2 = v9++;\n v13[v2] = 40;\n } else if (v6 == 41) {\n --v7;\n v3 = v9++;\n v13[v3] = 41;\n if (!v7) {\n v13[v9] = 0;\n v4 = (char **)&ptr[8 * *a2];\n *v4 = strdup(v13);\n if (v8 <= ++*a2) {\n v8 *= 2;\n ptr = (char *)realloc(ptr, 8LL * v8);\n }\n v9 = 0;\n }\n }\n }\n free(v13);\n return ptr;\n}", + "ida_pseudo_norm": "char *func0(const char *a1, int *a2) {\n int v2;\n int v3;\n char **v4;\n char v6;\n int v7;\n int v8;\n int v9;\n int i;\n int v11;\n char *ptr;\n char *v13;\n v11 = strlen(a1);\n v7 = 0;\n v8 = 10;\n ptr = (char *)malloc(80uLL);\n v13 = (char *)malloc(v11 + 1);\n v9 = 0;\n *a2 = 0;\n for (i = 0; i < v11; ++i) {\n v6 = a1[i];\n if (v6 == 40) {\n ++v7;\n v2 = v9++;\n v13[v2] = 40;\n } else if (v6 == 41) {\n --v7;\n v3 = v9++;\n v13[v3] = 41;\n if (!v7) {\n v13[v9] = 0;\n v4 = (char **)&ptr[8 * *a2];\n *v4 = strdup(v13);\n if (v8 <= ++*a2) {\n v8 *= 2;\n ptr = (char *)realloc(ptr, 8LL * v8);\n }\n v9 = 0;\n }\n }\n }\n free(v13);\n return ptr;\n}" + }, + { + "index": "HumanEval-C-1", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char** func0(const char* paren_string, int* group_count) {\n int length = strlen(paren_string);\n int level = 0;\n int capacity = 10;\n char** groups = malloc(capacity * sizeof(char*));\n char* buffer = malloc(length + 1);\n int buffer_index = 0;\n *group_count = 0;\n for (int i = 0; i < length; ++i) {\n char chr = paren_string[i];\n if (chr == '(') {\n level++;\n buffer[buffer_index++] = chr;\n } else if (chr == ')') {\n level--;\n buffer[buffer_index++] = chr;\n if (level == 0) {\n buffer[buffer_index] = '\\0';\n groups[*group_count] = strdup(buffer);\n (*group_count)++;\n if (*group_count >= capacity) {\n capacity *= 2;\n groups = realloc(groups, capacity * sizeof(char*));\n }\n buffer_index = 0;\n }\n }\n }\n free(buffer);\n return groups;\n}", + "test": "#include \n#include \n#include \n#include \n\nint issame(char** a, int a_size, const char* b[], int b_size) {\n if (a_size != b_size) {\n return 0;\n }\n for (int i = 0; i < a_size; i++) {\n if (strcmp(a[i], b[i]) != 0) {\n return 0;\n }\n }\n return 1;\n}\n\nvoid free_groups(char** groups, int size) {\n for (int i = 0; i < size; i++) {\n free(groups[i]);\n }\n free(groups);\n}\n\nint main() {\n int group_count;\n char** result;\n\n result = func0(\"(()()) ((())) () ((())()())\", &group_count);\n const char* expected1[] = {\"(()())\", \"((()))\", \"()\", \"((())()())\"};\n assert(issame(result, group_count, expected1, 4));\n free_groups(result, group_count);\n\n result = func0(\"() (()) ((())) (((())))\", &group_count);\n const char* expected2[] = {\"()\", \"(())\", \"((()))\", \"(((())))\"};\n assert(issame(result, group_count, expected2, 4));\n free_groups(result, group_count);\n\n result = func0(\"(()(())((())))\", &group_count);\n const char* expected3[] = {\"(()(())((())))\"};\n assert(issame(result, group_count, expected3, 1));\n free_groups(result, group_count);\n\n result = func0(\"( ) (( )) (( )( ))\", &group_count);\n const char* expected4[] = {\"()\", \"(())\", \"(()())\"};\n assert(issame(result, group_count, expected4, 3));\n free_groups(result, group_count);\n\n printf(\"All tests passed.\\n\");\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov r13, rdi\nmov r14, rsi\ncall _strlen\nmov rbp, rax\nmov edi, 50h ; 'P'; size\ncall _malloc\nmov r15, rax\nlea edi, [rbp+1]\nmovsxd rdi, edi; size\ncall _malloc\nmov r12, rax\nmov dword ptr [r14], 0\ntest ebp, ebp\njle loc_133A\nmov rbx, r13\nlea eax, [rbp-1]\nlea r13, [r13+rax+1]\nmov edx, 0\nmov [rsp+48h+var_44], 0Ah\nmov ebp, 0\njmp short loc_12C9\nloc_12B2:\nadd ebp, 1\nmovsxd rax, edx\nmov byte ptr [r12+rax], 28h ; '('\nlea edx, [rdx+1]\nloc_12C0:\nadd rbx, 1\ncmp rbx, r13\njz short loc_133A\nloc_12C9:\nmovzx eax, byte ptr [rbx]\ncmp al, 28h ; '('\njz short loc_12B2\ncmp al, 29h ; ')'\njnz short loc_12C0\nlea eax, [rdx+1]\nmovsxd rdx, edx\nmov byte ptr [r12+rdx], 29h ; ')'\nmov edx, eax\nsub ebp, 1\njnz short loc_12C0\ncdqe\nmov byte ptr [r12+rax], 0\nmovsxd rax, dword ptr [r14]\nlea rax, [r15+rax*8]\nmov [rsp+48h+var_40], rax\nmov rdi, r12; s\ncall _strdup\nmov rcx, [rsp+48h+var_40]\nmov [rcx], rax\nmov eax, [r14]\nadd eax, 1\nmov [r14], eax\nmov edx, ebp\nmov ecx, [rsp+48h+var_44]\ncmp eax, ecx\njl short loc_12C0\nshl [rsp+48h+var_44], 1\nmov eax, [rsp+48h+var_44]\nmovsxd rsi, eax\nshl rsi, 3; size\nmov rdi, r15; ptr\ncall _realloc\nmov r15, rax\nmov edx, ebp\njmp short loc_12C0\nloc_133A:\nmov rdi, r12; ptr\ncall _free\nmov rax, r15\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "char *__fastcall func0(const char *a1, int *a2)\n{\n int v2; // ebp\n char *v3; // r15\n char *v4; // r12\n const char *v5; // rbx\n __int64 v6; // r13\n int v7; // edx\n int v8; // ebp\n int v9; // eax\n int v10; // eax\n int v12; // [rsp+4h] [rbp-44h]\n char **v13; // [rsp+8h] [rbp-40h]\n\n v2 = strlen(a1);\n v3 = (char *)malloc(0x50uLL);\n v4 = (char *)malloc(v2 + 1);\n *a2 = 0;\n if ( v2 > 0 )\n {\n v5 = a1;\n v6 = (__int64)&a1[v2 - 1 + 1];\n v7 = 0;\n v12 = 10;\n v8 = 0;\n do\n {\n if ( *v5 == 40 )\n {\n ++v8;\n v4[v7++] = 40;\n }\n else if ( *v5 == 41 )\n {\n v9 = v7 + 1;\n v4[v7++] = 41;\n if ( !--v8 )\n {\n v4[v9] = 0;\n v13 = (char **)&v3[8 * *a2];\n *v13 = strdup(v4);\n v10 = *a2 + 1;\n *a2 = v10;\n v7 = 0;\n if ( v10 >= v12 )\n {\n v12 *= 2;\n v3 = (char *)realloc(v3, 8LL * v12);\n v7 = 0;\n }\n }\n }\n ++v5;\n }\n while ( v5 != (const char *)v6 );\n }\n free(v4);\n return v3;\n}", + "ida_strip_asm": "sub_1249:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov r13, rdi\nmov r14, rsi\ncall _strlen\nmov rbp, rax\nmov edi, 50h ; 'P'; size\ncall _malloc\nmov r15, rax\nlea edi, [rbp+1]\nmovsxd rdi, edi; size\ncall _malloc\nmov r12, rax\nmov dword ptr [r14], 0\ntest ebp, ebp\njle loc_133A\nmov rbx, r13\nlea eax, [rbp-1]\nlea r13, [r13+rax+1]\nmov edx, 0\nmov [rsp+48h+var_44], 0Ah\nmov ebp, 0\njmp short loc_12C9\nloc_12B2:\nadd ebp, 1\nmovsxd rax, edx\nmov byte ptr [r12+rax], 28h ; '('\nlea edx, [rdx+1]\nloc_12C0:\nadd rbx, 1\ncmp rbx, r13\njz short loc_133A\nloc_12C9:\nmovzx eax, byte ptr [rbx]\ncmp al, 28h ; '('\njz short loc_12B2\ncmp al, 29h ; ')'\njnz short loc_12C0\nlea eax, [rdx+1]\nmovsxd rdx, edx\nmov byte ptr [r12+rdx], 29h ; ')'\nmov edx, eax\nsub ebp, 1\njnz short loc_12C0\ncdqe\nmov byte ptr [r12+rax], 0\nmovsxd rax, dword ptr [r14]\nlea rax, [r15+rax*8]\nmov [rsp+48h+var_40], rax\nmov rdi, r12; s\ncall _strdup\nmov rcx, [rsp+48h+var_40]\nmov [rcx], rax\nmov eax, [r14]\nadd eax, 1\nmov [r14], eax\nmov edx, ebp\nmov ecx, [rsp+48h+var_44]\ncmp eax, ecx\njl short loc_12C0\nshl [rsp+48h+var_44], 1\nmov eax, [rsp+48h+var_44]\nmovsxd rsi, eax\nshl rsi, 3; size\nmov rdi, r15; ptr\ncall _realloc\nmov r15, rax\nmov edx, ebp\njmp short loc_12C0\nloc_133A:\nmov rdi, r12; ptr\ncall _free\nmov rax, r15\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1249(const char *a1, int *a2)\n{\n int v2; // ebp\n char *v3; // r15\n char *v4; // r12\n const char *v5; // rbx\n __int64 v6; // r13\n int v7; // edx\n int v8; // ebp\n int v9; // eax\n int v10; // eax\n int v12; // [rsp+4h] [rbp-44h]\n char **v13; // [rsp+8h] [rbp-40h]\n\n v2 = strlen(a1);\n v3 = (char *)malloc(0x50uLL);\n v4 = (char *)malloc(v2 + 1);\n *a2 = 0;\n if ( v2 > 0 )\n {\n v5 = a1;\n v6 = (__int64)&a1[v2 - 1 + 1];\n v7 = 0;\n v12 = 10;\n v8 = 0;\n do\n {\n if ( *v5 == 40 )\n {\n ++v8;\n v4[v7++] = 40;\n }\n else if ( *v5 == 41 )\n {\n v9 = v7 + 1;\n v4[v7++] = 41;\n if ( !--v8 )\n {\n v4[v9] = 0;\n v13 = (char **)&v3[8 * *a2];\n *v13 = strdup(v4);\n v10 = *a2 + 1;\n *a2 = v10;\n v7 = 0;\n if ( v10 >= v12 )\n {\n v12 *= 2;\n v3 = (char *)realloc(v3, 8LL * v12);\n v7 = 0;\n }\n }\n }\n ++v5;\n }\n while ( v5 != (const char *)v6 );\n }\n free(v4);\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1249(const char *a1, int *a2) {\n int v2;\n char *v3;\n char *v4;\n const char *v5;\n long long v6;\n int v7;\n int v8;\n int v9;\n int v10;\n int v12;\n char **v13;\n v2 = strlen(a1);\n v3 = (char *)malloc(80uLL);\n v4 = (char *)malloc(v2 + 1);\n *a2 = 0;\n if (v2 > 0) {\n v5 = a1;\n v6 = (long long)&a1[v2 - 1 + 1];\n v7 = 0;\n v12 = 10;\n v8 = 0;\n do {\n if (*v5 == 40) {\n ++v8;\n v4[v7++] = 40;\n } else if (*v5 == 41) {\n v9 = v7 + 1;\n v4[v7++] = 41;\n if (!--v8) {\n v4[v9] = 0;\n v13 = (char **)&v3[8 * *a2];\n *v13 = strdup(v4);\n v10 = *a2 + 1;\n *a2 = v10;\n v7 = 0;\n if (v10 >= v12) {\n v12 *= 2;\n v3 = (char *)realloc(v3, 8LL * v12);\n v7 = 0;\n }\n }\n }\n ++v5;\n } while (v5 != (const char *)v6);\n }\n free(v4);\n return v3;\n}", + "ida_pseudo_norm": "char *func0(const char *a1, int *a2) {\n int v2;\n char *v3;\n char *v4;\n const char *v5;\n long long v6;\n int v7;\n int v8;\n int v9;\n int v10;\n int v12;\n char **v13;\n v2 = strlen(a1);\n v3 = (char *)malloc(80uLL);\n v4 = (char *)malloc(v2 + 1);\n *a2 = 0;\n if (v2 > 0) {\n v5 = a1;\n v6 = (long long)&a1[v2 - 1 + 1];\n v7 = 0;\n v12 = 10;\n v8 = 0;\n do {\n if (*v5 == 40) {\n ++v8;\n v4[v7++] = 40;\n } else if (*v5 == 41) {\n v9 = v7 + 1;\n v4[v7++] = 41;\n if (!--v8) {\n v4[v9] = 0;\n v13 = (char **)&v3[8 * *a2];\n *v13 = strdup(v4);\n v10 = *a2 + 1;\n *a2 = v10;\n v7 = 0;\n if (v10 >= v12) {\n v12 *= 2;\n v3 = (char *)realloc(v3, 8LL * v12);\n v7 = 0;\n }\n }\n }\n ++v5;\n } while (v5 != (const char *)v6);\n }\n free(v4);\n return v3;\n}" + }, + { + "index": "HumanEval-C-1", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char** func0(const char* paren_string, int* group_count) {\n int length = strlen(paren_string);\n int level = 0;\n int capacity = 10;\n char** groups = malloc(capacity * sizeof(char*));\n char* buffer = malloc(length + 1);\n int buffer_index = 0;\n *group_count = 0;\n for (int i = 0; i < length; ++i) {\n char chr = paren_string[i];\n if (chr == '(') {\n level++;\n buffer[buffer_index++] = chr;\n } else if (chr == ')') {\n level--;\n buffer[buffer_index++] = chr;\n if (level == 0) {\n buffer[buffer_index] = '\\0';\n groups[*group_count] = strdup(buffer);\n (*group_count)++;\n if (*group_count >= capacity) {\n capacity *= 2;\n groups = realloc(groups, capacity * sizeof(char*));\n }\n buffer_index = 0;\n }\n }\n }\n free(buffer);\n return groups;\n}", + "test": "#include \n#include \n#include \n#include \n\nint issame(char** a, int a_size, const char* b[], int b_size) {\n if (a_size != b_size) {\n return 0;\n }\n for (int i = 0; i < a_size; i++) {\n if (strcmp(a[i], b[i]) != 0) {\n return 0;\n }\n }\n return 1;\n}\n\nvoid free_groups(char** groups, int size) {\n for (int i = 0; i < size; i++) {\n free(groups[i]);\n }\n free(groups);\n}\n\nint main() {\n int group_count;\n char** result;\n\n result = func0(\"(()()) ((())) () ((())()())\", &group_count);\n const char* expected1[] = {\"(()())\", \"((()))\", \"()\", \"((())()())\"};\n assert(issame(result, group_count, expected1, 4));\n free_groups(result, group_count);\n\n result = func0(\"() (()) ((())) (((())))\", &group_count);\n const char* expected2[] = {\"()\", \"(())\", \"((()))\", \"(((())))\"};\n assert(issame(result, group_count, expected2, 4));\n free_groups(result, group_count);\n\n result = func0(\"(()(())((())))\", &group_count);\n const char* expected3[] = {\"(()(())((())))\"};\n assert(issame(result, group_count, expected3, 1));\n free_groups(result, group_count);\n\n result = func0(\"( ) (( )) (( )( ))\", &group_count);\n const char* expected4[] = {\"()\", \"(())\", \"(()())\"};\n assert(issame(result, group_count, expected4, 3));\n free_groups(result, group_count);\n\n printf(\"All tests passed.\\n\");\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14, rsi\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 18h\ncall _strlen\nmov edi, 50h ; 'P'; size\nmov rbp, rax\ncall _malloc\nlea edi, [rbp+1]\nmovsxd rdi, edi; size\nmov [rsp+48h+ptr], rax\ncall _malloc\nmov dword ptr [r14], 0\nmov r15, rax\ntest ebp, ebp\njle short loc_15DC\nlea eax, [rbp-1]\nmov ecx, 0Ah\nxor ebp, ebp\nxor r12d, r12d\nlea r13, [rbx+rax+1]\njmp short loc_15BD\nloc_15B0:\ncmp al, 29h ; ')'\njz short loc_1600\nloc_15B4:\nadd rbx, 1\ncmp rbx, r13\njz short loc_15DC\nloc_15BD:\nmovzx eax, byte ptr [rbx]\ncmp al, 28h ; '('\njnz short loc_15B0\nmovsxd rax, ebp\nadd rbx, 1\nadd r12d, 1\nadd ebp, 1\nmov byte ptr [r15+rax], 28h ; '('\ncmp rbx, r13\njnz short loc_15BD\nloc_15DC:\nmov rdi, r15; ptr\ncall _free\nmov rax, [rsp+48h+ptr]\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1600:\nmovsxd rax, ebp\nadd ebp, 1\nmov byte ptr [r15+rax], 29h ; ')'\nsub r12d, 1\njnz short loc_15B4\nmovsxd rbp, ebp\nmovsxd rax, dword ptr [r14]\nmov rdx, [rsp+48h+ptr]\nmov rdi, r15; s\nmov byte ptr [r15+rbp], 0\nmov [rsp+48h+var_3C], ecx\nlea rbp, [rdx+rax*8]\ncall _strdup\nmov ecx, [rsp+48h+var_3C]\nmov [rbp+0], rax\nmov eax, [r14]\nxor ebp, ebp\nadd eax, 1\nmov [r14], eax\ncmp eax, ecx\njl loc_15B4\nadd ecx, ecx\nmov rdi, [rsp+48h+ptr]; ptr\nmovsxd rsi, ecx\nmov [rsp+48h+var_3C], ecx\nshl rsi, 3; size\ncall _realloc\nmov ecx, [rsp+48h+var_3C]\nmov [rsp+48h+ptr], rax\njmp loc_15B4", + "ida_pseudo": "char *__fastcall func0(const char *a1, int *a2)\n{\n const char *v2; // rbx\n int v3; // ebp\n char *v4; // rax\n char *v5; // r15\n __int64 v6; // rax\n int v7; // ecx\n int v8; // ebp\n int v9; // r12d\n __int64 v10; // r13\n __int64 v11; // rax\n __int64 v13; // rax\n __int64 v14; // rax\n char **v15; // rbp\n char *v16; // rax\n char *v17; // rax\n char *ptr; // [rsp+0h] [rbp-48h]\n int v19; // [rsp+Ch] [rbp-3Ch]\n\n v2 = a1;\n v3 = strlen(a1);\n ptr = (char *)malloc(0x50uLL);\n v4 = (char *)malloc(v3 + 1);\n *a2 = 0;\n v5 = v4;\n if ( v3 > 0 )\n {\n v6 = (unsigned int)(v3 - 1);\n v7 = 10;\n v8 = 0;\n v9 = 0;\n v10 = (__int64)&a1[v6 + 1];\n do\n {\n while ( *v2 == 40 )\n {\n v11 = v8;\n ++v2;\n ++v9;\n ++v8;\n v5[v11] = 40;\n if ( v2 == (const char *)v10 )\n goto LABEL_7;\n }\n if ( *v2 == 41 )\n {\n v13 = v8++;\n v5[v13] = 41;\n if ( !--v9 )\n {\n v14 = *a2;\n v5[v8] = 0;\n v19 = v7;\n v15 = (char **)&ptr[8 * v14];\n v16 = strdup(v5);\n v7 = v19;\n *v15 = v16;\n v8 = 0;\n LODWORD(v16) = *a2 + 1;\n *a2 = (int)v16;\n if ( (int)v16 >= v19 )\n {\n v17 = (char *)realloc(ptr, 16LL * v19);\n v7 = 2 * v19;\n ptr = v17;\n }\n }\n }\n ++v2;\n }\n while ( v2 != (const char *)v10 );\n }\nLABEL_7:\n free(v5);\n return ptr;\n}", + "ida_strip_asm": "sub_1550:\nendbr64\npush r15\npush r14\nmov r14, rsi\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 18h\ncall _strlen\nmov edi, 50h ; 'P'; size\nmov rbp, rax\ncall _malloc\nlea edi, [rbp+1]\nmovsxd rdi, edi; size\nmov [rsp+48h+ptr], rax\ncall _malloc\nmov dword ptr [r14], 0\nmov r15, rax\ntest ebp, ebp\njle short loc_15DC\nlea eax, [rbp-1]\nmov ecx, 0Ah\nxor ebp, ebp\nxor r12d, r12d\nlea r13, [rbx+rax+1]\njmp short loc_15BD\nloc_15B0:\ncmp al, 29h ; ')'\njz short loc_1600\nloc_15B4:\nadd rbx, 1\ncmp rbx, r13\njz short loc_15DC\nloc_15BD:\nmovzx eax, byte ptr [rbx]\ncmp al, 28h ; '('\njnz short loc_15B0\nmovsxd rax, ebp\nadd rbx, 1\nadd r12d, 1\nadd ebp, 1\nmov byte ptr [r15+rax], 28h ; '('\ncmp rbx, r13\njnz short loc_15BD\nloc_15DC:\nmov rdi, r15; ptr\ncall _free\nmov rax, [rsp+48h+ptr]\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1600:\nmovsxd rax, ebp\nadd ebp, 1\nmov byte ptr [r15+rax], 29h ; ')'\nsub r12d, 1\njnz short loc_15B4\nmovsxd rbp, ebp\nmovsxd rax, dword ptr [r14]\nmov rdx, [rsp+48h+ptr]\nmov rdi, r15; s\nmov byte ptr [r15+rbp], 0\nmov [rsp+48h+var_3C], ecx\nlea rbp, [rdx+rax*8]\ncall _strdup\nmov ecx, [rsp+48h+var_3C]\nmov [rbp+0], rax\nmov eax, [r14]\nxor ebp, ebp\nadd eax, 1\nmov [r14], eax\ncmp eax, ecx\njl loc_15B4\nadd ecx, ecx\nmov rdi, [rsp+48h+ptr]; ptr\nmovsxd rsi, ecx\nmov [rsp+48h+var_3C], ecx\nshl rsi, 3; size\ncall _realloc\nmov ecx, [rsp+48h+var_3C]\nmov [rsp+48h+ptr], rax\njmp loc_15B4", + "ida_strip_pseudo": "char *__fastcall sub_1550(const char *a1, int *a2)\n{\n const char *v2; // rbx\n int v3; // ebp\n char *v4; // rax\n char *v5; // r15\n __int64 v6; // rax\n int v7; // ecx\n int v8; // ebp\n int v9; // r12d\n __int64 v10; // r13\n __int64 v11; // rax\n __int64 v13; // rax\n __int64 v14; // rax\n char **v15; // rbp\n char *v16; // rax\n char *v17; // rax\n char *ptr; // [rsp+0h] [rbp-48h]\n int v19; // [rsp+Ch] [rbp-3Ch]\n\n v2 = a1;\n v3 = strlen(a1);\n ptr = (char *)malloc(0x50uLL);\n v4 = (char *)malloc(v3 + 1);\n *a2 = 0;\n v5 = v4;\n if ( v3 > 0 )\n {\n v6 = (unsigned int)(v3 - 1);\n v7 = 10;\n v8 = 0;\n v9 = 0;\n v10 = (__int64)&a1[v6 + 1];\n do\n {\n while ( *v2 == 40 )\n {\n v11 = v8;\n ++v2;\n ++v9;\n ++v8;\n v5[v11] = 40;\n if ( v2 == (const char *)v10 )\n goto LABEL_7;\n }\n if ( *v2 == 41 )\n {\n v13 = v8++;\n v5[v13] = 41;\n if ( !--v9 )\n {\n v14 = *a2;\n v5[v8] = 0;\n v19 = v7;\n v15 = (char **)&ptr[8 * v14];\n v16 = strdup(v5);\n v7 = v19;\n *v15 = v16;\n v8 = 0;\n LODWORD(v16) = *a2 + 1;\n *a2 = (int)v16;\n if ( (int)v16 >= v19 )\n {\n v17 = (char *)realloc(ptr, 16LL * v19);\n v7 = 2 * v19;\n ptr = v17;\n }\n }\n }\n ++v2;\n }\n while ( v2 != (const char *)v10 );\n }\nLABEL_7:\n free(v5);\n return ptr;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1550(const char *a1, int *a2) {\n const char *v2;\n int v3;\n char *v4;\n char *v5;\n long long v6;\n int v7;\n int v8;\n int v9;\n long long v10;\n long long v11;\n long long v13;\n long long v14;\n char **v15;\n char *v16;\n char *v17;\n char *ptr;\n int v19;\n v2 = a1;\n v3 = strlen(a1);\n ptr = (char *)malloc(80uLL);\n v4 = (char *)malloc(v3 + 1);\n *a2 = 0;\n v5 = v4;\n if (v3 > 0) {\n v6 = (unsigned int)(v3 - 1);\n v7 = 10;\n v8 = 0;\n v9 = 0;\n v10 = (long long)&a1[v6 + 1];\n do {\n while (*v2 == 40) {\n v11 = v8;\n ++v2;\n ++v9;\n ++v8;\n v5[v11] = 40;\n if (v2 == (const char *)v10) goto LABEL_7;\n }\n if (*v2 == 41) {\n v13 = v8++;\n v5[v13] = 41;\n if (!--v9) {\n v14 = *a2;\n v5[v8] = 0;\n v19 = v7;\n v15 = (char **)&ptr[8 * v14];\n v16 = strdup(v5);\n v7 = v19;\n *v15 = v16;\n v8 = 0;\n LODWORD(v16) = *a2 + 1;\n *a2 = (int)v16;\n if ((int)v16 >= v19) {\n v17 = (char *)realloc(ptr, 16LL * v19);\n v7 = 2 * v19;\n ptr = v17;\n }\n }\n }\n ++v2;\n } while (v2 != (const char *)v10);\n }\nLABEL_7:\n free(v5);\n return ptr;\n}", + "ida_pseudo_norm": "char *func0(const char *a1, int *a2) {\n const char *v2;\n int v3;\n char *v4;\n char *v5;\n long long v6;\n int v7;\n int v8;\n int v9;\n long long v10;\n long long v11;\n long long v13;\n long long v14;\n char **v15;\n char *v16;\n char *v17;\n char *ptr;\n int v19;\n v2 = a1;\n v3 = strlen(a1);\n ptr = (char *)malloc(80uLL);\n v4 = (char *)malloc(v3 + 1);\n *a2 = 0;\n v5 = v4;\n if (v3 > 0) {\n v6 = (unsigned int)(v3 - 1);\n v7 = 10;\n v8 = 0;\n v9 = 0;\n v10 = (long long)&a1[v6 + 1];\n do {\n while (*v2 == 40) {\n v11 = v8;\n ++v2;\n ++v9;\n ++v8;\n v5[v11] = 40;\n if (v2 == (const char *)v10) goto LABEL_7;\n }\n if (*v2 == 41) {\n v13 = v8++;\n v5[v13] = 41;\n if (!--v9) {\n v14 = *a2;\n v5[v8] = 0;\n v19 = v7;\n v15 = (char **)&ptr[8 * v14];\n v16 = strdup(v5);\n v7 = v19;\n *v15 = v16;\n v8 = 0;\n LODWORD(v16) = *a2 + 1;\n *a2 = (int)v16;\n if ((int)v16 >= v19) {\n v17 = (char *)realloc(ptr, 16LL * v19);\n v7 = 2 * v19;\n ptr = v17;\n }\n }\n }\n ++v2;\n } while (v2 != (const char *)v10);\n }\nLABEL_7:\n free(v5);\n return ptr;\n}" + }, + { + "index": "HumanEval-C-1", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char** func0(const char* paren_string, int* group_count) {\n int length = strlen(paren_string);\n int level = 0;\n int capacity = 10;\n char** groups = malloc(capacity * sizeof(char*));\n char* buffer = malloc(length + 1);\n int buffer_index = 0;\n *group_count = 0;\n for (int i = 0; i < length; ++i) {\n char chr = paren_string[i];\n if (chr == '(') {\n level++;\n buffer[buffer_index++] = chr;\n } else if (chr == ')') {\n level--;\n buffer[buffer_index++] = chr;\n if (level == 0) {\n buffer[buffer_index] = '\\0';\n groups[*group_count] = strdup(buffer);\n (*group_count)++;\n if (*group_count >= capacity) {\n capacity *= 2;\n groups = realloc(groups, capacity * sizeof(char*));\n }\n buffer_index = 0;\n }\n }\n }\n free(buffer);\n return groups;\n}", + "test": "#include \n#include \n#include \n#include \n\nint issame(char** a, int a_size, const char* b[], int b_size) {\n if (a_size != b_size) {\n return 0;\n }\n for (int i = 0; i < a_size; i++) {\n if (strcmp(a[i], b[i]) != 0) {\n return 0;\n }\n }\n return 1;\n}\n\nvoid free_groups(char** groups, int size) {\n for (int i = 0; i < size; i++) {\n free(groups[i]);\n }\n free(groups);\n}\n\nint main() {\n int group_count;\n char** result;\n\n result = func0(\"(()()) ((())) () ((())()())\", &group_count);\n const char* expected1[] = {\"(()())\", \"((()))\", \"()\", \"((())()())\"};\n assert(issame(result, group_count, expected1, 4));\n free_groups(result, group_count);\n\n result = func0(\"() (()) ((())) (((())))\", &group_count);\n const char* expected2[] = {\"()\", \"(())\", \"((()))\", \"(((())))\"};\n assert(issame(result, group_count, expected2, 4));\n free_groups(result, group_count);\n\n result = func0(\"(()(())((())))\", &group_count);\n const char* expected3[] = {\"(()(())((())))\"};\n assert(issame(result, group_count, expected3, 1));\n free_groups(result, group_count);\n\n result = func0(\"( ) (( )) (( )( ))\", &group_count);\n const char* expected4[] = {\"()\", \"(())\", \"(()())\"};\n assert(issame(result, group_count, expected4, 3));\n free_groups(result, group_count);\n\n printf(\"All tests passed.\\n\");\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14, rsi\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 18h\ncall _strlen\nmov edi, 50h ; 'P'; size\nmov rbp, rax\ncall _malloc\nlea edi, [rbp+1]\nmovsxd rdi, edi; size\nmov [rsp+48h+ptr], rax\ncall _malloc\nmov dword ptr [r14], 0\nmov r15, rax\ntest ebp, ebp\njle short loc_15DC\nlea eax, [rbp-1]\nmov ecx, 0Ah\nxor ebp, ebp\nxor r12d, r12d\nlea r13, [rbx+rax+1]\njmp short loc_15BD\nloc_15B0:\ncmp al, 29h ; ')'\njz short loc_1600\nloc_15B4:\nadd rbx, 1\ncmp rbx, r13\njz short loc_15DC\nloc_15BD:\nmovzx eax, byte ptr [rbx]\ncmp al, 28h ; '('\njnz short loc_15B0\nmovsxd rax, ebp\nadd rbx, 1\nadd r12d, 1\nadd ebp, 1\nmov byte ptr [r15+rax], 28h ; '('\ncmp rbx, r13\njnz short loc_15BD\nloc_15DC:\nmov rdi, r15; ptr\ncall _free\nmov rax, [rsp+48h+ptr]\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1600:\nmovsxd rax, ebp\nadd ebp, 1\nmov byte ptr [r15+rax], 29h ; ')'\nsub r12d, 1\njnz short loc_15B4\nmovsxd rbp, ebp\nmovsxd rax, dword ptr [r14]\nmov rdx, [rsp+48h+ptr]\nmov rdi, r15; s\nmov byte ptr [r15+rbp], 0\nmov [rsp+48h+var_3C], ecx\nlea rbp, [rdx+rax*8]\ncall _strdup\nmov ecx, [rsp+48h+var_3C]\nmov [rbp+0], rax\nmov eax, [r14]\nxor ebp, ebp\nadd eax, 1\nmov [r14], eax\ncmp eax, ecx\njl loc_15B4\nadd ecx, ecx\nmov rdi, [rsp+48h+ptr]; ptr\nmovsxd rsi, ecx\nmov [rsp+48h+var_3C], ecx\nshl rsi, 3; size\ncall _realloc\nmov ecx, [rsp+48h+var_3C]\nmov [rsp+48h+ptr], rax\njmp loc_15B4", + "ida_pseudo": "char *__fastcall func0(const char *a1, int *a2)\n{\n const char *v2; // rbx\n int v3; // ebp\n char *v4; // rax\n char *v5; // r15\n __int64 v6; // rax\n int v7; // ecx\n int v8; // ebp\n int v9; // r12d\n __int64 v10; // r13\n __int64 v11; // rax\n __int64 v13; // rax\n __int64 v14; // rax\n char **v15; // rbp\n char *v16; // rax\n char *v17; // rax\n char *ptr; // [rsp+0h] [rbp-48h]\n int v19; // [rsp+Ch] [rbp-3Ch]\n\n v2 = a1;\n v3 = strlen(a1);\n ptr = (char *)malloc(0x50uLL);\n v4 = (char *)malloc(v3 + 1);\n *a2 = 0;\n v5 = v4;\n if ( v3 > 0 )\n {\n v6 = (unsigned int)(v3 - 1);\n v7 = 10;\n v8 = 0;\n v9 = 0;\n v10 = (__int64)&a1[v6 + 1];\n do\n {\n while ( *v2 == 40 )\n {\n v11 = v8;\n ++v2;\n ++v9;\n ++v8;\n v5[v11] = 40;\n if ( v2 == (const char *)v10 )\n goto LABEL_7;\n }\n if ( *v2 == 41 )\n {\n v13 = v8++;\n v5[v13] = 41;\n if ( !--v9 )\n {\n v14 = *a2;\n v5[v8] = 0;\n v19 = v7;\n v15 = (char **)&ptr[8 * v14];\n v16 = strdup(v5);\n v7 = v19;\n *v15 = v16;\n v8 = 0;\n LODWORD(v16) = *a2 + 1;\n *a2 = (int)v16;\n if ( (int)v16 >= v19 )\n {\n v17 = (char *)realloc(ptr, 16LL * v19);\n v7 = 2 * v19;\n ptr = v17;\n }\n }\n }\n ++v2;\n }\n while ( v2 != (const char *)v10 );\n }\nLABEL_7:\n free(v5);\n return ptr;\n}", + "ida_strip_asm": "sub_1550:\nendbr64\npush r15\npush r14\nmov r14, rsi\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 18h\ncall _strlen\nmov edi, 50h ; 'P'; size\nmov rbp, rax\ncall _malloc\nlea edi, [rbp+1]\nmovsxd rdi, edi; size\nmov [rsp+48h+ptr], rax\ncall _malloc\nmov dword ptr [r14], 0\nmov r15, rax\ntest ebp, ebp\njle short loc_15DC\nlea eax, [rbp-1]\nmov ecx, 0Ah\nxor ebp, ebp\nxor r12d, r12d\nlea r13, [rbx+rax+1]\njmp short loc_15BD\nloc_15B0:\ncmp al, 29h ; ')'\njz short loc_1600\nloc_15B4:\nadd rbx, 1\ncmp rbx, r13\njz short loc_15DC\nloc_15BD:\nmovzx eax, byte ptr [rbx]\ncmp al, 28h ; '('\njnz short loc_15B0\nmovsxd rax, ebp\nadd rbx, 1\nadd r12d, 1\nadd ebp, 1\nmov byte ptr [r15+rax], 28h ; '('\ncmp rbx, r13\njnz short loc_15BD\nloc_15DC:\nmov rdi, r15; ptr\ncall _free\nmov rax, [rsp+48h+ptr]\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1600:\nmovsxd rax, ebp\nadd ebp, 1\nmov byte ptr [r15+rax], 29h ; ')'\nsub r12d, 1\njnz short loc_15B4\nmovsxd rbp, ebp\nmovsxd rax, dword ptr [r14]\nmov rdx, [rsp+48h+ptr]\nmov rdi, r15; s\nmov byte ptr [r15+rbp], 0\nmov [rsp+48h+var_3C], ecx\nlea rbp, [rdx+rax*8]\ncall _strdup\nmov ecx, [rsp+48h+var_3C]\nmov [rbp+0], rax\nmov eax, [r14]\nxor ebp, ebp\nadd eax, 1\nmov [r14], eax\ncmp eax, ecx\njl loc_15B4\nadd ecx, ecx\nmov rdi, [rsp+48h+ptr]; ptr\nmovsxd rsi, ecx\nmov [rsp+48h+var_3C], ecx\nshl rsi, 3; size\ncall _realloc\nmov ecx, [rsp+48h+var_3C]\nmov [rsp+48h+ptr], rax\njmp loc_15B4", + "ida_strip_pseudo": "char *__fastcall sub_1550(const char *a1, int *a2)\n{\n const char *v2; // rbx\n int v3; // ebp\n char *v4; // rax\n char *v5; // r15\n __int64 v6; // rax\n int v7; // ecx\n int v8; // ebp\n int v9; // r12d\n __int64 v10; // r13\n __int64 v11; // rax\n __int64 v13; // rax\n __int64 v14; // rax\n char **v15; // rbp\n char *v16; // rax\n char *v17; // rax\n char *ptr; // [rsp+0h] [rbp-48h]\n int v19; // [rsp+Ch] [rbp-3Ch]\n\n v2 = a1;\n v3 = strlen(a1);\n ptr = (char *)malloc(0x50uLL);\n v4 = (char *)malloc(v3 + 1);\n *a2 = 0;\n v5 = v4;\n if ( v3 > 0 )\n {\n v6 = (unsigned int)(v3 - 1);\n v7 = 10;\n v8 = 0;\n v9 = 0;\n v10 = (__int64)&a1[v6 + 1];\n do\n {\n while ( *v2 == 40 )\n {\n v11 = v8;\n ++v2;\n ++v9;\n ++v8;\n v5[v11] = 40;\n if ( v2 == (const char *)v10 )\n goto LABEL_7;\n }\n if ( *v2 == 41 )\n {\n v13 = v8++;\n v5[v13] = 41;\n if ( !--v9 )\n {\n v14 = *a2;\n v5[v8] = 0;\n v19 = v7;\n v15 = (char **)&ptr[8 * v14];\n v16 = strdup(v5);\n v7 = v19;\n *v15 = v16;\n v8 = 0;\n LODWORD(v16) = *a2 + 1;\n *a2 = (int)v16;\n if ( (int)v16 >= v19 )\n {\n v17 = (char *)realloc(ptr, 16LL * v19);\n v7 = 2 * v19;\n ptr = v17;\n }\n }\n }\n ++v2;\n }\n while ( v2 != (const char *)v10 );\n }\nLABEL_7:\n free(v5);\n return ptr;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1550(const char *a1, int *a2) {\n const char *v2;\n int v3;\n char *v4;\n char *v5;\n long long v6;\n int v7;\n int v8;\n int v9;\n long long v10;\n long long v11;\n long long v13;\n long long v14;\n char **v15;\n char *v16;\n char *v17;\n char *ptr;\n int v19;\n v2 = a1;\n v3 = strlen(a1);\n ptr = (char *)malloc(80uLL);\n v4 = (char *)malloc(v3 + 1);\n *a2 = 0;\n v5 = v4;\n if (v3 > 0) {\n v6 = (unsigned int)(v3 - 1);\n v7 = 10;\n v8 = 0;\n v9 = 0;\n v10 = (long long)&a1[v6 + 1];\n do {\n while (*v2 == 40) {\n v11 = v8;\n ++v2;\n ++v9;\n ++v8;\n v5[v11] = 40;\n if (v2 == (const char *)v10) goto LABEL_7;\n }\n if (*v2 == 41) {\n v13 = v8++;\n v5[v13] = 41;\n if (!--v9) {\n v14 = *a2;\n v5[v8] = 0;\n v19 = v7;\n v15 = (char **)&ptr[8 * v14];\n v16 = strdup(v5);\n v7 = v19;\n *v15 = v16;\n v8 = 0;\n LODWORD(v16) = *a2 + 1;\n *a2 = (int)v16;\n if ((int)v16 >= v19) {\n v17 = (char *)realloc(ptr, 16LL * v19);\n v7 = 2 * v19;\n ptr = v17;\n }\n }\n }\n ++v2;\n } while (v2 != (const char *)v10);\n }\nLABEL_7:\n free(v5);\n return ptr;\n}", + "ida_pseudo_norm": "char *func0(const char *a1, int *a2) {\n const char *v2;\n int v3;\n char *v4;\n char *v5;\n long long v6;\n int v7;\n int v8;\n int v9;\n long long v10;\n long long v11;\n long long v13;\n long long v14;\n char **v15;\n char *v16;\n char *v17;\n char *ptr;\n int v19;\n v2 = a1;\n v3 = strlen(a1);\n ptr = (char *)malloc(80uLL);\n v4 = (char *)malloc(v3 + 1);\n *a2 = 0;\n v5 = v4;\n if (v3 > 0) {\n v6 = (unsigned int)(v3 - 1);\n v7 = 10;\n v8 = 0;\n v9 = 0;\n v10 = (long long)&a1[v6 + 1];\n do {\n while (*v2 == 40) {\n v11 = v8;\n ++v2;\n ++v9;\n ++v8;\n v5[v11] = 40;\n if (v2 == (const char *)v10) goto LABEL_7;\n }\n if (*v2 == 41) {\n v13 = v8++;\n v5[v13] = 41;\n if (!--v9) {\n v14 = *a2;\n v5[v8] = 0;\n v19 = v7;\n v15 = (char **)&ptr[8 * v14];\n v16 = strdup(v5);\n v7 = v19;\n *v15 = v16;\n v8 = 0;\n LODWORD(v16) = *a2 + 1;\n *a2 = (int)v16;\n if ((int)v16 >= v19) {\n v17 = (char *)realloc(ptr, 16LL * v19);\n v7 = 2 * v19;\n ptr = v17;\n }\n }\n }\n ++v2;\n } while (v2 != (const char *)v10);\n }\nLABEL_7:\n free(v5);\n return ptr;\n}" + }, + { + "index": "HumanEval-C-2", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "float func0(float number) { return number - (int)number; }", + "test": "#include \n#include \n#include \n\nint main() {\n assert(func0(3.5f) == 0.5f);\n assert(fabs(func0(1.33f) - 0.33f) < 1e-4);\n assert(fabs(func0(123.456f) - 0.456f) < 1e-4);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmovss [rbp+var_4], xmm0\nmovss xmm0, [rbp+var_4]\ncvttss2si eax, xmm0\npxor xmm1, xmm1\ncvtsi2ss xmm1, eax\nmovss xmm0, [rbp+var_4]\nsubss xmm0, xmm1\npop rbp\nretn", + "ida_pseudo": "float __fastcall func0(float a1)\n{\n return a1 - (float)(int)a1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmovss [rbp+var_4], xmm0\nmovss xmm0, [rbp+var_4]\ncvttss2si eax, xmm0\npxor xmm1, xmm1\ncvtsi2ss xmm1, eax\nmovss xmm0, [rbp+var_4]\nsubss xmm0, xmm1\npop rbp\nretn", + "ida_strip_pseudo": "float __fastcall sub_1149(float a1)\n{\n return a1 - (float)(int)a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "float sub_1149(float a1) { return a1 - (float)(int)a1; }", + "ida_pseudo_norm": "float func0(float a1) { return a1 - (float)(int)a1; }" + }, + { + "index": "HumanEval-C-3", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int operations[], int size) {\n int num = 0;\n for (int i = 0; i < size; i++) {\n num += operations[i];\n if (num < 0) return 1;\n }\n return 0;\n}", + "test": "#include \n\nint main() {\n int case1[] = {};\n assert(func0(case1, 0) == 0);\n\n int case2[] = {1, 2, -3, 1, 2, -3};\n assert(func0(case2, 6) == 0);\n\n int case3[] = {1, 2, -4, 5, 6};\n assert(func0(case3, 5) == 1);\n\n int case4[] = {1, -1, 2, -2, 5, -5, 4, -4};\n assert(func0(case4, 8) == 0);\n\n int case5[] = {1, -1, 2, -2, 5, -5, 4, -5};\n assert(func0(case5, 8) == 1);\n\n int case6[] = {1, -2, 2, -2, 5, -5, 4, -4};\n assert(func0(case6, 8) == 1);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11B2\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\ncmp [rbp+var_8], 0\njns short loc_11AE\nmov eax, 1\njmp short loc_11BF\nloc_11AE:\nadd [rbp+var_4], 1\nloc_11B2:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, 0\nloc_11BF:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v3 += *(_DWORD *)(4LL * i + a1);\n if ( v3 < 0 )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11B2\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\ncmp [rbp+var_8], 0\njns short loc_11AE\nmov eax, 1\njmp short loc_11BF\nloc_11AE:\nadd [rbp+var_4], 1\nloc_11B2:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, 0\nloc_11BF:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v3 += *(_DWORD *)(4LL * i + a1);\n if ( v3 < 0 )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n v3 += *(uint32_t *)(4LL * i + a1);\n if (v3 < 0) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n v3 += *(uint32_t *)(4LL * i + a1);\n if (v3 < 0) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": "HumanEval-C-3", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int operations[], int size) {\n int num = 0;\n for (int i = 0; i < size; i++) {\n num += operations[i];\n if (num < 0) return 1;\n }\n return 0;\n}", + "test": "#include \n\nint main() {\n int case1[] = {};\n assert(func0(case1, 0) == 0);\n\n int case2[] = {1, 2, -3, 1, 2, -3};\n assert(func0(case2, 6) == 0);\n\n int case3[] = {1, 2, -4, 5, 6};\n assert(func0(case3, 5) == 1);\n\n int case4[] = {1, -1, 2, -2, 5, -5, 4, -4};\n assert(func0(case4, 8) == 0);\n\n int case5[] = {1, -1, 2, -2, 5, -5, 4, -5};\n assert(func0(case5, 8) == 1);\n\n int case6[] = {1, -2, 2, -2, 5, -5, 4, -4};\n assert(func0(case6, 8) == 1);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11A1\nmov edx, [rdi]\ntest edx, edx\njs short loc_11A7\nadd rdi, 4\nlea eax, [rsi-1]\nlea rcx, [rdi+rax*4]\nloc_1182:\ncmp rdi, rcx\njz short loc_119B\nmov eax, edx\nadd eax, [rdi]\nmov edx, eax\nadd rdi, 4\ntest eax, eax\njns short loc_1182\nmov eax, 1\nretn\nloc_119B:\nmov eax, 0\nretn\nloc_11A1:\nmov eax, 0\nretn\nloc_11A7:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int v2; // edx\n _DWORD *v3; // rdi\n _DWORD *v4; // rcx\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = *a1;\n if ( *a1 < 0 )\n return 1LL;\n v3 = a1 + 1;\n v4 = &v3[a2 - 1];\n while ( v3 != v4 )\n {\n v2 += *v3++;\n if ( v2 < 0 )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11A1\nmov edx, [rdi]\ntest edx, edx\njs short loc_11A7\nadd rdi, 4\nlea eax, [rsi-1]\nlea rcx, [rdi+rax*4]\nloc_1182:\ncmp rdi, rcx\njz short loc_119B\nmov eax, edx\nadd eax, [rdi]\nmov edx, eax\nadd rdi, 4\ntest eax, eax\njns short loc_1182\nmov eax, 1\nretn\nloc_119B:\nmov eax, 0\nretn\nloc_11A1:\nmov eax, 0\nretn\nloc_11A7:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int *a1, int a2)\n{\n int v2; // edx\n _DWORD *v3; // rdi\n _DWORD *v4; // rcx\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = *a1;\n if ( *a1 < 0 )\n return 1LL;\n v3 = a1 + 1;\n v4 = &v3[a2 - 1];\n while ( v3 != v4 )\n {\n v2 += *v3++;\n if ( v2 < 0 )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int *a1, int a2) {\n int v2;\n uint32_t *v3;\n uint32_t *v4;\n if (a2 <= 0) return 0LL;\n v2 = *a1;\n if (*a1 < 0) return 1LL;\n v3 = a1 + 1;\n v4 = &v3[a2 - 1];\n while (v3 != v4) {\n v2 += *v3++;\n if (v2 < 0) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int v2;\n uint32_t *v3;\n uint32_t *v4;\n if (a2 <= 0) return 0LL;\n v2 = *a1;\n if (*a1 < 0) return 1LL;\n v3 = a1 + 1;\n v4 = &v3[a2 - 1];\n while (v3 != v4) {\n v2 += *v3++;\n if (v2 < 0) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": "HumanEval-C-4", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "float func0(float numbers[], int size) {\n float sum = 0;\n float avg, msum, mavg;\n int i = 0;\n for (i = 0; i < size; i++) sum += numbers[i];\n avg = sum / size;\n msum = 0;\n for (i = 0; i < size; i++) msum += fabs(numbers[i] - avg);\n return msum / size;\n}", + "test": "#include \n#include \n\nint main() {\n float case1[] = {1.0, 2.0, 3.0};\n assert(fabs(func0(case1, 3) - 2.0/3.0) < 1e-4);\n\n float case2[] = {1.0, 2.0, 3.0, 4.0};\n assert(fabs(func0(case2, 4) - 1.0) < 1e-4);\n\n float case3[] = {1.0, 2.0, 3.0, 4.0, 5.0};\n assert(fabs(func0(case3, 5) - 6.0/5.0) < 1e-4);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\npxor xmm0, xmm0\nmovss [rbp+var_10], xmm0\nmov [rbp+var_8], 0\nmov [rbp+var_8], 0\njmp short loc_11BB\nloc_1191:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\nmovss xmm1, [rbp+var_10]\naddss xmm0, xmm1\nmovss [rbp+var_10], xmm0\nadd [rbp+var_8], 1\nloc_11BB:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_1191\npxor xmm1, xmm1\ncvtsi2ss xmm1, [rbp+var_1C]\nmovss xmm0, [rbp+var_10]\ndivss xmm0, xmm1\nmovss [rbp+var_4], xmm0\npxor xmm0, xmm0\nmovss [rbp+var_C], xmm0\nmov [rbp+var_8], 0\njmp short loc_1226\nloc_11EC:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\nsubss xmm0, [rbp+var_4]\nmovss xmm1, cs:dword_20B0\nandps xmm0, xmm1\nmovss xmm1, [rbp+var_C]\naddss xmm0, xmm1\nmovss [rbp+var_C], xmm0\nadd [rbp+var_8], 1\nloc_1226:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_11EC\npxor xmm1, xmm1\ncvtsi2ss xmm1, [rbp+var_1C]\nmovss xmm0, [rbp+var_C]\ndivss xmm0, xmm1\npop rbp\nretn", + "ida_pseudo": "float __fastcall func0(__int64 a1, int a2)\n{\n float v3; // [rsp+Ch] [rbp-10h]\n float v4; // [rsp+10h] [rbp-Ch]\n int i; // [rsp+14h] [rbp-8h]\n int j; // [rsp+14h] [rbp-8h]\n\n v3 = 0.0;\n for ( i = 0; i < a2; ++i )\n v3 = *(float *)(4LL * i + a1) + v3;\n v4 = 0.0;\n for ( j = 0; j < a2; ++j )\n v4 = fabs(*(float *)(4LL * j + a1) - (float)(v3 / (float)a2)) + v4;\n return v4 / (float)a2;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\npxor xmm0, xmm0\nmovss [rbp+var_10], xmm0\nmov [rbp+var_8], 0\nmov [rbp+var_8], 0\njmp short loc_11BB\nloc_1191:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\nmovss xmm1, [rbp+var_10]\naddss xmm0, xmm1\nmovss [rbp+var_10], xmm0\nadd [rbp+var_8], 1\nloc_11BB:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_1191\npxor xmm1, xmm1\ncvtsi2ss xmm1, [rbp+var_1C]\nmovss xmm0, [rbp+var_10]\ndivss xmm0, xmm1\nmovss [rbp+var_4], xmm0\npxor xmm0, xmm0\nmovss [rbp+var_C], xmm0\nmov [rbp+var_8], 0\njmp short loc_1226\nloc_11EC:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\nsubss xmm0, [rbp+var_4]\nmovss xmm1, cs:dword_20B0\nandps xmm0, xmm1\nmovss xmm1, [rbp+var_C]\naddss xmm0, xmm1\nmovss [rbp+var_C], xmm0\nadd [rbp+var_8], 1\nloc_1226:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_11EC\npxor xmm1, xmm1\ncvtsi2ss xmm1, [rbp+var_1C]\nmovss xmm0, [rbp+var_C]\ndivss xmm0, xmm1\npop rbp\nretn", + "ida_strip_pseudo": "float __fastcall sub_1169(__int64 a1, int a2)\n{\n float v3; // [rsp+Ch] [rbp-10h]\n float v4; // [rsp+10h] [rbp-Ch]\n int i; // [rsp+14h] [rbp-8h]\n int j; // [rsp+14h] [rbp-8h]\n\n v3 = 0.0;\n for ( i = 0; i < a2; ++i )\n v3 = *(float *)(4LL * i + a1) + v3;\n v4 = 0.0;\n for ( j = 0; j < a2; ++j )\n v4 = fabs(*(float *)(4LL * j + a1) - (float)(v3 / (float)a2)) + v4;\n return v4 / (float)a2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "float sub_1169(long long a1, int a2) {\n float v3;\n float v4;\n int i;\n int j;\n v3 = 0.0;\n for (i = 0; i < a2; ++i) v3 = *(float *)(4LL * i + a1) + v3;\n v4 = 0.0;\n for (j = 0; j < a2; ++j)\n v4 = fabs(*(float *)(4LL * j + a1) - (float)(v3 / (float)a2)) + v4;\n return v4 / (float)a2;\n}", + "ida_pseudo_norm": "float func0(long long a1, int a2) {\n float v3;\n float v4;\n int i;\n int j;\n v3 = 0.0;\n for (i = 0; i < a2; ++i) v3 = *(float *)(4LL * i + a1) + v3;\n v4 = 0.0;\n for (j = 0; j < a2; ++j)\n v4 = fabs(*(float *)(4LL * j + a1) - (float)(v3 / (float)a2)) + v4;\n return v4 / (float)a2;\n}" + }, + { + "index": "HumanEval-C-4", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "float func0(float numbers[], int size) {\n float sum = 0;\n float avg, msum, mavg;\n int i = 0;\n for (i = 0; i < size; i++) sum += numbers[i];\n avg = sum / size;\n msum = 0;\n for (i = 0; i < size; i++) msum += fabs(numbers[i] - avg);\n return msum / size;\n}", + "test": "#include \n#include \n\nint main() {\n float case1[] = {1.0, 2.0, 3.0};\n assert(fabs(func0(case1, 3) - 2.0/3.0) < 1e-4);\n\n float case2[] = {1.0, 2.0, 3.0, 4.0};\n assert(fabs(func0(case2, 4) - 1.0) < 1e-4);\n\n float case3[] = {1.0, 2.0, 3.0, 4.0, 5.0};\n assert(fabs(func0(case3, 5) - 6.0/5.0) < 1e-4);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11C4\nmov rax, rdi\nmovsxd rdx, esi\nlea rdx, [rdi+rdx*4]\npxor xmm0, xmm0\nloc_117F:\naddss xmm0, dword ptr [rdi]\nadd rdi, 4\ncmp rdi, rdx\njnz short loc_117F\npxor xmm4, xmm4\ncvtsi2ss xmm4, esi\ndivss xmm0, xmm4\npxor xmm2, xmm2\nmovss xmm3, cs:dword_20B0\nloc_11A4:\nmovss xmm1, dword ptr [rax]\nsubss xmm1, xmm0\nandps xmm1, xmm3\naddss xmm2, xmm1\nadd rax, 4\ncmp rax, rdx\njnz short loc_11A4\nloc_11BC:\ndivss xmm2, xmm4\nmovaps xmm0, xmm2\nretn\nloc_11C4:\npxor xmm4, xmm4\ncvtsi2ss xmm4, esi\npxor xmm2, xmm2\njmp short loc_11BC", + "ida_pseudo": "__int128 __usercall func0@(float *a1@, int a2@)\n{\n float *v2; // rax\n float *v3; // rdx\n float v4; // xmm0_4\n float v5; // xmm4_4\n float v6; // xmm0_4\n __int128 v7; // xmm2\n\n if ( a2 <= 0 )\n {\n v5 = (float)a2;\n v7 = 0LL;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0.0;\n do\n v4 = v4 + *a1++;\n while ( a1 != v3 );\n v5 = (float)a2;\n v6 = v4 / (float)a2;\n v7 = 0LL;\n do\n *(float *)&v7 = *(float *)&v7 + fabs(*v2++ - v6);\n while ( v2 != v3 );\n }\n *(float *)&v7 = *(float *)&v7 / v5;\n return v7;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11C4\nmov rax, rdi\nmovsxd rdx, esi\nlea rdx, [rdi+rdx*4]\npxor xmm0, xmm0\nloc_117F:\naddss xmm0, dword ptr [rdi]\nadd rdi, 4\ncmp rdi, rdx\njnz short loc_117F\npxor xmm4, xmm4\ncvtsi2ss xmm4, esi\ndivss xmm0, xmm4\npxor xmm2, xmm2\nmovss xmm3, cs:dword_20B0\nloc_11A4:\nmovss xmm1, dword ptr [rax]\nsubss xmm1, xmm0\nandps xmm1, xmm3\naddss xmm2, xmm1\nadd rax, 4\ncmp rax, rdx\njnz short loc_11A4\nloc_11BC:\ndivss xmm2, xmm4\nmovaps xmm0, xmm2\nretn\nloc_11C4:\npxor xmm4, xmm4\ncvtsi2ss xmm4, esi\npxor xmm2, xmm2\njmp short loc_11BC", + "ida_strip_pseudo": "__int128 __usercall sub_1169@(float *a1@, int a2@)\n{\n float *v2; // rax\n float *v3; // rdx\n float v4; // xmm0_4\n float v5; // xmm4_4\n float v6; // xmm0_4\n __int128 v7; // xmm2\n\n if ( a2 <= 0 )\n {\n v5 = (float)a2;\n v7 = 0LL;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0.0;\n do\n v4 = v4 + *a1++;\n while ( a1 != v3 );\n v5 = (float)a2;\n v6 = v4 / (float)a2;\n v7 = 0LL;\n do\n *(float *)&v7 = *(float *)&v7 + fabs(*v2++ - v6);\n while ( v2 != v3 );\n }\n *(float *)&v7 = *(float *)&v7 / v5;\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__int128 __usercall sub_1169 @(float *a1 @, int a2 @) {\n float *v2;\n float *v3;\n float v4;\n float v5;\n float v6;\n __int128 v7;\n if (a2 <= 0) {\n v5 = (float)a2;\n v7 = 0LL;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0.0;\n do\n v4 = v4 + *a1++;\n while (a1 != v3);\n v5 = (float)a2;\n v6 = v4 / (float)a2;\n v7 = 0LL;\n do\n *(float *)&v7 = *(float *)&v7 + fabs(*v2++ - v6);\n while (v2 != v3);\n }\n *(float *)&v7 = *(float *)&v7 / v5;\n return v7;\n}", + "ida_pseudo_norm": "__int128 __usercall func0 @(float *a1 @, int a2 @) {\n float *v2;\n float *v3;\n float v4;\n float v5;\n float v6;\n __int128 v7;\n if (a2 <= 0) {\n v5 = (float)a2;\n v7 = 0LL;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0.0;\n do\n v4 = v4 + *a1++;\n while (a1 != v3);\n v5 = (float)a2;\n v6 = v4 / (float)a2;\n v7 = 0LL;\n do\n *(float *)&v7 = *(float *)&v7 + fabs(*v2++ - v6);\n while (v2 != v3);\n }\n *(float *)&v7 = *(float *)&v7 / v5;\n return v7;\n}" + }, + { + "index": "HumanEval-C-4", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "float func0(float numbers[], int size) {\n float sum = 0;\n float avg, msum, mavg;\n int i = 0;\n for (i = 0; i < size; i++) sum += numbers[i];\n avg = sum / size;\n msum = 0;\n for (i = 0; i < size; i++) msum += fabs(numbers[i] - avg);\n return msum / size;\n}", + "test": "#include \n#include \n\nint main() {\n float case1[] = {1.0, 2.0, 3.0};\n assert(fabs(func0(case1, 3) - 2.0/3.0) < 1e-4);\n\n float case2[] = {1.0, 2.0, 3.0, 4.0};\n assert(fabs(func0(case2, 4) - 1.0) < 1e-4);\n\n float case3[] = {1.0, 2.0, 3.0, 4.0, 5.0};\n assert(fabs(func0(case3, 5) - 6.0/5.0) < 1e-4);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npxor xmm4, xmm4\ncvtsi2ss xmm4, esi\ntest esi, esi\njle short loc_1330\nmovsxd rsi, esi\nmov rax, rdi\npxor xmm0, xmm0\nlea rdx, [rdi+rsi*4]\nand esi, 1\njz short loc_12E0\nlea rax, [rdi+4]\naddss xmm0, dword ptr [rdi]\ncmp rdx, rax\njz short loc_12F2\nloc_12E0:\naddss xmm0, dword ptr [rax]\nadd rax, 8\naddss xmm0, dword ptr [rax-4]\ncmp rdx, rax\njnz short loc_12E0\nloc_12F2:\ndivss xmm0, xmm4\npxor xmm2, xmm2\nmovss xmm3, cs:dword_20B0\nnop word ptr [rax+rax+00h]\nloc_1308:\nmovss xmm1, dword ptr [rdi]\nadd rdi, 4\nsubss xmm1, xmm0\nandps xmm1, xmm3\naddss xmm2, xmm1\ncmp rdx, rdi\njnz short loc_1308\ndivss xmm2, xmm4\nmovaps xmm0, xmm2\nretn\nloc_1330:\npxor xmm2, xmm2\ndivss xmm2, xmm4\nmovaps xmm0, xmm2\nretn", + "ida_pseudo": "__int128 __usercall func0@(float *a1@, int a2@)\n{\n float v2; // xmm4_4\n float *v3; // rax\n float v4; // xmm0_4\n float *v5; // rdx\n float v6; // xmm0_4\n float v7; // xmm0_4\n __int128 v8; // xmm2\n float v9; // xmm1_4\n __int128 v11; // xmm2\n\n v2 = (float)a2;\n if ( a2 <= 0 )\n {\n v11 = 0LL;\n *(float *)&v11 = 0.0 / v2;\n return v11;\n }\n else\n {\n v3 = a1;\n v4 = 0.0;\n v5 = &a1[a2];\n if ( (a2 & 1) == 0 || (v3 = a1 + 1, v4 = *a1 + 0.0, v5 != a1 + 1) )\n {\n do\n {\n v6 = v4 + *v3;\n v3 += 2;\n v4 = v6 + *(v3 - 1);\n }\n while ( v5 != v3 );\n }\n v7 = v4 / v2;\n v8 = 0LL;\n do\n {\n v9 = *a1++;\n *(float *)&v8 = *(float *)&v8 + fabs(v9 - v7);\n }\n while ( v5 != a1 );\n *(float *)&v8 = *(float *)&v8 / v2;\n return v8;\n }\n}", + "ida_strip_asm": "sub_12B0:\nendbr64\npxor xmm4, xmm4\ncvtsi2ss xmm4, esi\ntest esi, esi\njle short loc_1330\nmovsxd rsi, esi\nmov rax, rdi\npxor xmm0, xmm0\nlea rdx, [rdi+rsi*4]\nand esi, 1\njz short loc_12E0\nlea rax, [rdi+4]\naddss xmm0, dword ptr [rdi]\ncmp rdx, rax\njz short loc_12F2\nloc_12E0:\naddss xmm0, dword ptr [rax]\nadd rax, 8\naddss xmm0, dword ptr [rax-4]\ncmp rdx, rax\njnz short loc_12E0\nloc_12F2:\ndivss xmm0, xmm4\npxor xmm2, xmm2\nmovss xmm3, cs:dword_20B0\nnop word ptr [rax+rax+00h]\nloc_1308:\nmovss xmm1, dword ptr [rdi]\nadd rdi, 4\nsubss xmm1, xmm0\nandps xmm1, xmm3\naddss xmm2, xmm1\ncmp rdx, rdi\njnz short loc_1308\ndivss xmm2, xmm4\nmovaps xmm0, xmm2\nretn\nloc_1330:\npxor xmm2, xmm2\ndivss xmm2, xmm4\nmovaps xmm0, xmm2\nretn", + "ida_strip_pseudo": "__int128 __usercall sub_12B0@(float *a1@, int a2@)\n{\n float v2; // xmm4_4\n float *v3; // rax\n float v4; // xmm0_4\n float *v5; // rdx\n float v6; // xmm0_4\n float v7; // xmm0_4\n __int128 v8; // xmm2\n float v9; // xmm1_4\n __int128 v11; // xmm2\n\n v2 = (float)a2;\n if ( a2 <= 0 )\n {\n v11 = 0LL;\n *(float *)&v11 = 0.0 / v2;\n return v11;\n }\n else\n {\n v3 = a1;\n v4 = 0.0;\n v5 = &a1[a2];\n if ( (a2 & 1) == 0 || (v3 = a1 + 1, v4 = *a1 + 0.0, v5 != a1 + 1) )\n {\n do\n {\n v6 = v4 + *v3;\n v3 += 2;\n v4 = v6 + *(v3 - 1);\n }\n while ( v5 != v3 );\n }\n v7 = v4 / v2;\n v8 = 0LL;\n do\n {\n v9 = *a1++;\n *(float *)&v8 = *(float *)&v8 + fabs(v9 - v7);\n }\n while ( v5 != a1 );\n *(float *)&v8 = *(float *)&v8 / v2;\n return v8;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__int128 __usercall sub_12B0 @(float *a1 @, int a2 @) {\n float v2;\n float *v3;\n float v4;\n float *v5;\n float v6;\n float v7;\n __int128 v8;\n float v9;\n __int128 v11;\n v2 = (float)a2;\n if (a2 <= 0) {\n v11 = 0LL;\n *(float *)&v11 = 0.0 / v2;\n return v11;\n } else {\n v3 = a1;\n v4 = 0.0;\n v5 = &a1[a2];\n if ((a2 & 1) == 0 || (v3 = a1 + 1, v4 = *a1 + 0.0, v5 != a1 + 1)) {\n do {\n v6 = v4 + *v3;\n v3 += 2;\n v4 = v6 + *(v3 - 1);\n } while (v5 != v3);\n }\n v7 = v4 / v2;\n v8 = 0LL;\n do {\n v9 = *a1++;\n *(float *)&v8 = *(float *)&v8 + fabs(v9 - v7);\n } while (v5 != a1);\n *(float *)&v8 = *(float *)&v8 / v2;\n return v8;\n }\n}", + "ida_pseudo_norm": "__int128 __usercall func0 @(float *a1 @, int a2 @) {\n float v2;\n float *v3;\n float v4;\n float *v5;\n float v6;\n float v7;\n __int128 v8;\n float v9;\n __int128 v11;\n v2 = (float)a2;\n if (a2 <= 0) {\n v11 = 0LL;\n *(float *)&v11 = 0.0 / v2;\n return v11;\n } else {\n v3 = a1;\n v4 = 0.0;\n v5 = &a1[a2];\n if ((a2 & 1) == 0 || (v3 = a1 + 1, v4 = *a1 + 0.0, v5 != a1 + 1)) {\n do {\n v6 = v4 + *v3;\n v3 += 2;\n v4 = v6 + *(v3 - 1);\n } while (v5 != v3);\n }\n v7 = v4 / v2;\n v8 = 0LL;\n do {\n v9 = *a1++;\n *(float *)&v8 = *(float *)&v8 + fabs(v9 - v7);\n } while (v5 != a1);\n *(float *)&v8 = *(float *)&v8 / v2;\n return v8;\n }\n}" + }, + { + "index": "HumanEval-C-5", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int *func0(const int numbers[], int size, int delimiter, int *out_size) {\n *out_size = size > 0 ? (size * 2) - 1 : 0;\n int *out = (int *)malloc(*out_size * sizeof(int));\n if (size > 0) out[0] = numbers[0];\n for (int i = 1, j = 1; i < size; ++i) {\n out[j++] = delimiter;\n out[j++] = numbers[i];\n }\n return out;\n}", + "test": "#include \n#include \n\nint issame(const int a[], const int b[], int size_a, int size_b) {\n if (size_a != size_b) return 0;\n for (int i = 0; i < size_a; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int out_size;\n\n // Test with an empty array\n int *result_empty = func0((const int[]){}, 0, 7, &out_size);\n assert(issame(result_empty, (const int[]){}, out_size, 0));\n free(result_empty);\n\n // Test with an array with elements\n int result_expected1[] = {5, 8, 6, 8, 3, 8, 2};\n int *result1 = func0((const int[]){5, 6, 3, 2}, 4, 8, &out_size);\n assert(issame(result1, result_expected1, out_size, 7));\n free(result1);\n\n // Test with an array with delimiters equal to elements\n int result_expected2[] = {2, 2, 2, 2, 2};\n int *result2 = func0((const int[]){2, 2, 2}, 3, 2, &out_size);\n assert(issame(result2, result_expected2, out_size, 5));\n free(result2);\n \n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_28], rcx\ncmp [rbp+var_1C], 0\njle short loc_11D3\nmov eax, [rbp+var_1C]\nadd eax, eax\nlea edx, [rax-1]\njmp short loc_11D8\nloc_11D3:\nmov edx, 0\nloc_11D8:\nmov rax, [rbp+var_28]\nmov [rax], edx\nmov rax, [rbp+var_28]\nmov eax, [rax]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\ncmp [rbp+var_1C], 0\njle short loc_1208\nmov rax, [rbp+var_18]\nmov edx, [rax]\nmov rax, [rbp+var_8]\nmov [rax], edx\nloc_1208:\nmov [rbp+var_10], 1\nmov [rbp+var_C], 1\njmp short loc_126E\nloc_1218:\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_20]\nmov [rdx], eax\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nadd [rbp+var_10], 1\nloc_126E:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_1C]\njl short loc_1218\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(_DWORD *a1, int a2, int a3, int *a4)\n{\n int v4; // edx\n int v5; // eax\n int v8; // [rsp+20h] [rbp-10h]\n int v9; // [rsp+24h] [rbp-Ch]\n _DWORD *v10; // [rsp+28h] [rbp-8h]\n\n if ( a2 <= 0 )\n v4 = 0;\n else\n v4 = 2 * a2 - 1;\n *a4 = v4;\n v10 = malloc(4LL * *a4);\n if ( a2 > 0 )\n *v10 = *a1;\n v8 = 1;\n v9 = 1;\n while ( v8 < a2 )\n {\n v10[v9] = a3;\n v5 = v9 + 1;\n v9 += 2;\n v10[v5] = a1[v8++];\n }\n return v10;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_28], rcx\ncmp [rbp+var_1C], 0\njle short loc_11D3\nmov eax, [rbp+var_1C]\nadd eax, eax\nlea edx, [rax-1]\njmp short loc_11D8\nloc_11D3:\nmov edx, 0\nloc_11D8:\nmov rax, [rbp+var_28]\nmov [rax], edx\nmov rax, [rbp+var_28]\nmov eax, [rax]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\ncmp [rbp+var_1C], 0\njle short loc_1208\nmov rax, [rbp+var_18]\nmov edx, [rax]\nmov rax, [rbp+var_8]\nmov [rax], edx\nloc_1208:\nmov [rbp+var_10], 1\nmov [rbp+var_C], 1\njmp short loc_126E\nloc_1218:\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_20]\nmov [rdx], eax\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nadd [rbp+var_10], 1\nloc_126E:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_1C]\njl short loc_1218\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(_DWORD *a1, int a2, int a3, int *a4)\n{\n int v4; // edx\n int v5; // eax\n int v8; // [rsp+20h] [rbp-10h]\n int v9; // [rsp+24h] [rbp-Ch]\n _DWORD *v10; // [rsp+28h] [rbp-8h]\n\n if ( a2 <= 0 )\n v4 = 0;\n else\n v4 = 2 * a2 - 1;\n *a4 = v4;\n v10 = malloc(4LL * *a4);\n if ( a2 > 0 )\n *v10 = *a1;\n v8 = 1;\n v9 = 1;\n while ( v8 < a2 )\n {\n v10[v9] = a3;\n v5 = v9 + 1;\n v9 += 2;\n v10[v5] = a1[v8++];\n }\n return v10;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(uint32_t *a1, int a2, int a3, int *a4) {\n int v4;\n int v5;\n int v8;\n int v9;\n uint32_t *v10;\n if (a2 <= 0)\n v4 = 0;\n else\n v4 = 2 * a2 - 1;\n *a4 = v4;\n v10 = malloc(4LL * *a4);\n if (a2 > 0) *v10 = *a1;\n v8 = 1;\n v9 = 1;\n while (v8 < a2) {\n v10[v9] = a3;\n v5 = v9 + 1;\n v9 += 2;\n v10[v5] = a1[v8++];\n }\n return v10;\n}", + "ida_pseudo_norm": "uint32_t *func0(uint32_t *a1, int a2, int a3, int *a4) {\n int v4;\n int v5;\n int v8;\n int v9;\n uint32_t *v10;\n if (a2 <= 0)\n v4 = 0;\n else\n v4 = 2 * a2 - 1;\n *a4 = v4;\n v10 = malloc(4LL * *a4);\n if (a2 > 0) *v10 = *a1;\n v8 = 1;\n v9 = 1;\n while (v8 < a2) {\n v10[v9] = a3;\n v5 = v9 + 1;\n v9 += 2;\n v10[v5] = a1[v8++];\n }\n return v10;\n}" + }, + { + "index": "HumanEval-C-5", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int *func0(const int numbers[], int size, int delimiter, int *out_size) {\n *out_size = size > 0 ? (size * 2) - 1 : 0;\n int *out = (int *)malloc(*out_size * sizeof(int));\n if (size > 0) out[0] = numbers[0];\n for (int i = 1, j = 1; i < size; ++i) {\n out[j++] = delimiter;\n out[j++] = numbers[i];\n }\n return out;\n}", + "test": "#include \n#include \n\nint issame(const int a[], const int b[], int size_a, int size_b) {\n if (size_a != size_b) return 0;\n for (int i = 0; i < size_a; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int out_size;\n\n // Test with an empty array\n int *result_empty = func0((const int[]){}, 0, 7, &out_size);\n assert(issame(result_empty, (const int[]){}, out_size, 0));\n free(result_empty);\n\n // Test with an array with elements\n int result_expected1[] = {5, 8, 6, 8, 3, 8, 2};\n int *result1 = func0((const int[]){5, 6, 3, 2}, 4, 8, &out_size);\n assert(issame(result1, result_expected1, out_size, 7));\n free(result1);\n\n // Test with an array with delimiters equal to elements\n int result_expected2[] = {2, 2, 2, 2, 2};\n int *result2 = func0((const int[]){2, 2, 2}, 3, 2, &out_size);\n assert(issame(result2, result_expected2, out_size, 5));\n free(result2);\n \n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\ntest esi, esi\njle short loc_11F9\nmov rbx, rdi\nmov r12d, esi\nmov ebp, edx\nlea edi, [rsi+rsi-1]\nmov [rcx], edi\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov edx, [rbx]\nmov [rax], edx\ncmp r12d, 1\njle short loc_11F4\nmov esi, r12d\nmov edx, 1\nloc_11E1:\nmov [rax+rdx*8-4], ebp\nmov ecx, [rbx+rdx*4]\nmov [rax+rdx*8], ecx\nadd rdx, 1\ncmp rsi, rdx\njnz short loc_11E1\nloc_11F4:\npop rbx\npop rbp\npop r12\nretn\nloc_11F9:\nmov dword ptr [rcx], 0\nmov edi, 0; size\ncall _malloc\njmp short loc_11F4", + "ida_pseudo": "_DWORD *__fastcall func0(_DWORD *a1, int a2, int a3, int *a4)\n{\n int v6; // edi\n _DWORD *result; // rax\n __int64 i; // rdx\n\n if ( a2 <= 0 )\n {\n *a4 = 0;\n return malloc(0LL);\n }\n else\n {\n v6 = 2 * a2 - 1;\n *a4 = v6;\n result = malloc(4LL * v6);\n *result = *a1;\n if ( a2 > 1 )\n {\n for ( i = 1LL; i != a2; ++i )\n {\n result[2 * i - 1] = a3;\n result[2 * i] = a1[i];\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r12\npush rbp\npush rbx\ntest esi, esi\njle short loc_11F9\nmov rbx, rdi\nmov r12d, esi\nmov ebp, edx\nlea edi, [rsi+rsi-1]\nmov [rcx], edi\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov edx, [rbx]\nmov [rax], edx\ncmp r12d, 1\njle short loc_11F4\nmov esi, r12d\nmov edx, 1\nloc_11E1:\nmov [rax+rdx*8-4], ebp\nmov ecx, [rbx+rdx*4]\nmov [rax+rdx*8], ecx\nadd rdx, 1\ncmp rsi, rdx\njnz short loc_11E1\nloc_11F4:\npop rbx\npop rbp\npop r12\nretn\nloc_11F9:\nmov dword ptr [rcx], 0\nmov edi, 0; size\ncall _malloc\njmp short loc_11F4", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(_DWORD *a1, int a2, int a3, int *a4)\n{\n int v6; // edi\n _DWORD *result; // rax\n __int64 i; // rdx\n\n if ( a2 <= 0 )\n {\n *a4 = 0;\n return malloc(0LL);\n }\n else\n {\n v6 = 2 * a2 - 1;\n *a4 = v6;\n result = malloc(4LL * v6);\n *result = *a1;\n if ( a2 > 1 )\n {\n for ( i = 1LL; i != a2; ++i )\n {\n result[2 * i - 1] = a3;\n result[2 * i] = a1[i];\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(uint32_t *a1, int a2, int a3, int *a4) {\n int v6;\n uint32_t *result;\n long long i;\n if (a2 <= 0) {\n *a4 = 0;\n return malloc(0LL);\n } else {\n v6 = 2 * a2 - 1;\n *a4 = v6;\n result = malloc(4LL * v6);\n *result = *a1;\n if (a2 > 1) {\n for (i = 1LL; i != a2; ++i) {\n result[2 * i - 1] = a3;\n result[2 * i] = a1[i];\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(uint32_t *a1, int a2, int a3, int *a4) {\n int v6;\n uint32_t *result;\n long long i;\n if (a2 <= 0) {\n *a4 = 0;\n return malloc(0LL);\n } else {\n v6 = 2 * a2 - 1;\n *a4 = v6;\n result = malloc(4LL * v6);\n *result = *a1;\n if (a2 > 1) {\n for (i = 1LL; i != a2; ++i) {\n result[2 * i - 1] = a3;\n result[2 * i] = a1[i];\n }\n }\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-5", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int *func0(const int numbers[], int size, int delimiter, int *out_size) {\n *out_size = size > 0 ? (size * 2) - 1 : 0;\n int *out = (int *)malloc(*out_size * sizeof(int));\n if (size > 0) out[0] = numbers[0];\n for (int i = 1, j = 1; i < size; ++i) {\n out[j++] = delimiter;\n out[j++] = numbers[i];\n }\n return out;\n}", + "test": "#include \n#include \n\nint issame(const int a[], const int b[], int size_a, int size_b) {\n if (size_a != size_b) return 0;\n for (int i = 0; i < size_a; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int out_size;\n\n // Test with an empty array\n int *result_empty = func0((const int[]){}, 0, 7, &out_size);\n assert(issame(result_empty, (const int[]){}, out_size, 0));\n free(result_empty);\n\n // Test with an array with elements\n int result_expected1[] = {5, 8, 6, 8, 3, 8, 2};\n int *result1 = func0((const int[]){5, 6, 3, 2}, 4, 8, &out_size);\n assert(issame(result1, result_expected1, out_size, 7));\n free(result1);\n\n // Test with an array with delimiters equal to elements\n int result_expected2[] = {2, 2, 2, 2, 2};\n int *result2 = func0((const int[]){2, 2, 2}, 3, 2, &out_size);\n assert(issame(result2, result_expected2, out_size, 5));\n free(result2);\n \n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+28h+var_1C], edx\ntest esi, esi\njle short loc_13F8\nmov rbx, rdi\nlea edi, [rsi+rsi-1]\nmov ebp, esi\nmov [rcx], edi\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov edx, [rbx]\ncmp ebp, 1\nmovd xmm1, [rsp+28h+var_1C]\nmov ecx, 1\nmov [rax], edx\nmov edx, ebp\njz short loc_13EC\nnop\nloc_13D0:\nmovd xmm2, dword ptr [rbx+rcx*4]\nmovdqa xmm0, xmm1\npunpckldq xmm0, xmm2\nmovq qword ptr [rax+rcx*8-4], xmm0\nadd rcx, 1\ncmp rcx, rdx\njnz short loc_13D0\nloc_13EC:\nadd rsp, 18h\npop rbx\npop rbp\nretn\nloc_13F8:\nmov dword ptr [rcx], 0\nadd rsp, 18h\nxor edi, edi; size\npop rbx\npop rbp\njmp _malloc", + "ida_pseudo": "_DWORD *__fastcall func0(_DWORD *a1, int a2, unsigned int a3, int *a4)\n{\n int v5; // edi\n _DWORD *result; // rax\n __m128i v7; // xmm1\n __int64 v8; // rcx\n\n if ( a2 <= 0 )\n {\n *a4 = 0;\n return malloc(0LL);\n }\n else\n {\n v5 = 2 * a2 - 1;\n *a4 = v5;\n result = malloc(4LL * v5);\n v7 = _mm_cvtsi32_si128(a3);\n v8 = 1LL;\n *result = *a1;\n if ( a2 != 1 )\n {\n do\n {\n *(_QWORD *)&result[2 * v8 - 1] = _mm_unpacklo_epi32(v7, _mm_cvtsi32_si128(a1[v8])).m128i_u64[0];\n ++v8;\n }\n while ( v8 != a2 );\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1390:\nendbr64\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+28h+var_1C], edx\ntest esi, esi\njle short loc_13F8\nmov rbx, rdi\nlea edi, [rsi+rsi-1]\nmov ebp, esi\nmov [rcx], edi\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov edx, [rbx]\ncmp ebp, 1\nmovd xmm1, [rsp+28h+var_1C]\nmov ecx, 1\nmov [rax], edx\nmov edx, ebp\njz short loc_13EC\nnop\nloc_13D0:\nmovd xmm2, dword ptr [rbx+rcx*4]\nmovdqa xmm0, xmm1\npunpckldq xmm0, xmm2\nmovq qword ptr [rax+rcx*8-4], xmm0\nadd rcx, 1\ncmp rcx, rdx\njnz short loc_13D0\nloc_13EC:\nadd rsp, 18h\npop rbx\npop rbp\nretn\nloc_13F8:\nmov dword ptr [rcx], 0\nadd rsp, 18h\nxor edi, edi; size\npop rbx\npop rbp\njmp _malloc", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1390(_DWORD *a1, int a2, unsigned int a3, int *a4)\n{\n int v5; // edi\n _DWORD *result; // rax\n __m128i v7; // xmm1\n __int64 v8; // rcx\n\n if ( a2 <= 0 )\n {\n *a4 = 0;\n return malloc(0LL);\n }\n else\n {\n v5 = 2 * a2 - 1;\n *a4 = v5;\n result = malloc(4LL * v5);\n v7 = _mm_cvtsi32_si128(a3);\n v8 = 1LL;\n *result = *a1;\n if ( a2 != 1 )\n {\n do\n {\n *(_QWORD *)&result[2 * v8 - 1] = _mm_unpacklo_epi32(v7, _mm_cvtsi32_si128(a1[v8])).m128i_u64[0];\n ++v8;\n }\n while ( v8 != a2 );\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1390(uint32_t *a1, int a2, unsigned int a3, int *a4) {\n int v5;\n uint32_t *result;\n __m128i v7;\n long long v8;\n if (a2 <= 0) {\n *a4 = 0;\n return malloc(0LL);\n } else {\n v5 = 2 * a2 - 1;\n *a4 = v5;\n result = malloc(4LL * v5);\n v7 = _mm_cvtsi32_si128(a3);\n v8 = 1LL;\n *result = *a1;\n if (a2 != 1) {\n do {\n *(uint64_t *)&result[2 * v8 - 1] =\n _mm_unpacklo_epi32(v7, _mm_cvtsi32_si128(a1[v8])).m128i_u64[0];\n ++v8;\n } while (v8 != a2);\n }\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(uint32_t *a1, int a2, unsigned int a3, int *a4) {\n int v5;\n uint32_t *result;\n __m128i v7;\n long long v8;\n if (a2 <= 0) {\n *a4 = 0;\n return malloc(0LL);\n } else {\n v5 = 2 * a2 - 1;\n *a4 = v5;\n result = malloc(4LL * v5);\n v7 = _mm_cvtsi32_si128(a3);\n v8 = 1LL;\n *result = *a1;\n if (a2 != 1) {\n do {\n *(uint64_t *)&result[2 * v8 - 1] =\n _mm_unpacklo_epi32(v7, _mm_cvtsi32_si128(a1[v8])).m128i_u64[0];\n ++v8;\n } while (v8 != a2);\n }\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-5", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int *func0(const int numbers[], int size, int delimiter, int *out_size) {\n *out_size = size > 0 ? (size * 2) - 1 : 0;\n int *out = (int *)malloc(*out_size * sizeof(int));\n if (size > 0) out[0] = numbers[0];\n for (int i = 1, j = 1; i < size; ++i) {\n out[j++] = delimiter;\n out[j++] = numbers[i];\n }\n return out;\n}", + "test": "#include \n#include \n\nint issame(const int a[], const int b[], int size_a, int size_b) {\n if (size_a != size_b) return 0;\n for (int i = 0; i < size_a; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int out_size;\n\n // Test with an empty array\n int *result_empty = func0((const int[]){}, 0, 7, &out_size);\n assert(issame(result_empty, (const int[]){}, out_size, 0));\n free(result_empty);\n\n // Test with an array with elements\n int result_expected1[] = {5, 8, 6, 8, 3, 8, 2};\n int *result1 = func0((const int[]){5, 6, 3, 2}, 4, 8, &out_size);\n assert(issame(result1, result_expected1, out_size, 7));\n free(result1);\n\n // Test with an array with delimiters equal to elements\n int result_expected2[] = {2, 2, 2, 2, 2};\n int *result2 = func0((const int[]){2, 2, 2}, 3, 2, &out_size);\n assert(issame(result2, result_expected2, out_size, 5));\n free(result2);\n \n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+28h+var_1C], edx\ntest esi, esi\njle loc_14A0\nmov rbx, rdi\nlea edi, [rsi+rsi-1]\nmov ebp, esi\nmov [rcx], edi\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\ncmp ebp, 1\nmovd xmm2, [rsp+28h+var_1C]\nmov rcx, rax\nmov eax, [rbx]\nmov [rcx], eax\njz loc_148C\nlea eax, [rbp-2]\nlea edx, [rbp-1]\ncmp eax, 2\njbe loc_14B3\nmov esi, edx\npshufd xmm0, xmm2, 0\nxor eax, eax\nshr esi, 2\nshl rsi, 4\nnop word ptr [rax+rax+00h]\nloc_13F8:\nmovdqu xmm3, xmmword ptr [rbx+rax+4]\nmovdqa xmm1, xmm0\npunpckldq xmm1, xmm3\nmovups xmmword ptr [rcx+rax*2+4], xmm1\nmovdqa xmm1, xmm0\npunpckhdq xmm1, xmm3\nmovups xmmword ptr [rcx+rax*2+14h], xmm1\nadd rax, 10h\ncmp rsi, rax\njnz short loc_13F8\ntest dl, 3\njz short loc_148C\nand edx, 0FFFFFFFCh\nlea eax, [rdx+1]\nlea edx, [rdx+rdx+1]\nloc_1430:\nmovsxd rsi, eax\nmovdqa xmm0, xmm2\nmovsxd rdx, edx\nmovd xmm1, dword ptr [rbx+rsi*4]\nlea rdi, ds:0[rdx*4]\nlea r8, ds:0[rsi*4]\npunpckldq xmm0, xmm1\nmovq qword ptr [rcx+rdx*4], xmm0\nlea edx, [rax+1]\ncmp ebp, edx\njle short loc_148C\nmovd xmm5, dword ptr [rbx+r8+4]\nmovdqa xmm0, xmm2\nadd eax, 2\npunpckldq xmm0, xmm5\nmovq qword ptr [rcx+rdi+8], xmm0\ncmp ebp, eax\njle short loc_148C\nmovd xmm0, dword ptr [rbx+r8+8]\npunpckldq xmm2, xmm0\nmovq qword ptr [rcx+rdi+10h], xmm2\nloc_148C:\nadd rsp, 18h\nmov rax, rcx\npop rbx\npop rbp\nretn\nloc_14A0:\nmov dword ptr [rcx], 0\nadd rsp, 18h\nxor edi, edi; size\npop rbx\npop rbp\njmp _malloc\nloc_14B3:\nmov edx, 1\nmov eax, 1\njmp loc_1430", + "ida_pseudo": "_DWORD *__fastcall func0(_DWORD *a1, int a2, unsigned int a3, int *a4)\n{\n int v5; // edi\n __m128i v6; // xmm2\n _DWORD *v7; // rcx\n unsigned int v8; // edx\n __m128i v9; // xmm0\n unsigned __int64 v10; // rax\n __m128i v11; // xmm3\n unsigned int v12; // edx\n int v13; // eax\n int v14; // edx\n __int64 v15; // rdi\n __int64 v16; // r8\n\n if ( a2 > 0 )\n {\n v5 = 2 * a2 - 1;\n *a4 = v5;\n v6 = _mm_cvtsi32_si128(a3);\n v7 = malloc(4LL * v5);\n *v7 = *a1;\n if ( a2 != 1 )\n {\n v8 = a2 - 1;\n if ( (unsigned int)(a2 - 2) <= 2 )\n {\n v14 = 1;\n v13 = 1;\nLABEL_8:\n v15 = v14;\n v16 = v13;\n *(_QWORD *)&v7[v15] = _mm_unpacklo_epi32(v6, _mm_cvtsi32_si128(a1[v16])).m128i_u64[0];\n if ( a2 > v13 + 1 )\n {\n *(_QWORD *)&v7[v15 + 2] = _mm_unpacklo_epi32(v6, _mm_cvtsi32_si128(a1[v16 + 1])).m128i_u64[0];\n if ( a2 > v13 + 2 )\n *(_QWORD *)&v7[v15 + 4] = _mm_unpacklo_epi32(v6, _mm_cvtsi32_si128(a1[v16 + 2])).m128i_u64[0];\n }\n return v7;\n }\n v9 = _mm_shuffle_epi32(v6, 0);\n v10 = 0LL;\n do\n {\n v11 = _mm_loadu_si128((const __m128i *)&a1[v10 / 2 + 1]);\n *(__m128i *)&v7[v10 + 1] = _mm_unpacklo_epi32(v9, v11);\n *(__m128i *)&v7[v10 + 5] = _mm_unpackhi_epi32(v9, v11);\n v10 += 8LL;\n }\n while ( 8LL * (v8 >> 2) != v10 );\n if ( (v8 & 3) != 0 )\n {\n v12 = v8 & 0xFFFFFFFC;\n v13 = v12 + 1;\n v14 = 2 * v12 + 1;\n goto LABEL_8;\n }\n }\n return v7;\n }\n *a4 = 0;\n return malloc(0LL);\n}", + "ida_strip_asm": "sub_1390:\nendbr64\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+28h+var_1C], edx\ntest esi, esi\njle loc_14A0\nmov rbx, rdi\nlea edi, [rsi+rsi-1]\nmov ebp, esi\nmov [rcx], edi\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\ncmp ebp, 1\nmovd xmm2, [rsp+28h+var_1C]\nmov rcx, rax\nmov eax, [rbx]\nmov [rcx], eax\njz loc_148C\nlea eax, [rbp-2]\nlea edx, [rbp-1]\ncmp eax, 2\njbe loc_14B3\nmov esi, edx\npshufd xmm0, xmm2, 0\nxor eax, eax\nshr esi, 2\nshl rsi, 4\nnop word ptr [rax+rax+00h]\nloc_13F8:\nmovdqu xmm3, xmmword ptr [rbx+rax+4]\nmovdqa xmm1, xmm0\npunpckldq xmm1, xmm3\nmovups xmmword ptr [rcx+rax*2+4], xmm1\nmovdqa xmm1, xmm0\npunpckhdq xmm1, xmm3\nmovups xmmword ptr [rcx+rax*2+14h], xmm1\nadd rax, 10h\ncmp rsi, rax\njnz short loc_13F8\ntest dl, 3\njz short loc_148C\nand edx, 0FFFFFFFCh\nlea eax, [rdx+1]\nlea edx, [rdx+rdx+1]\nloc_1430:\nmovsxd rsi, eax\nmovdqa xmm0, xmm2\nmovsxd rdx, edx\nmovd xmm1, dword ptr [rbx+rsi*4]\nlea rdi, ds:0[rdx*4]\nlea r8, ds:0[rsi*4]\npunpckldq xmm0, xmm1\nmovq qword ptr [rcx+rdx*4], xmm0\nlea edx, [rax+1]\ncmp ebp, edx\njle short loc_148C\nmovd xmm5, dword ptr [rbx+r8+4]\nmovdqa xmm0, xmm2\nadd eax, 2\npunpckldq xmm0, xmm5\nmovq qword ptr [rcx+rdi+8], xmm0\ncmp ebp, eax\njle short loc_148C\nmovd xmm0, dword ptr [rbx+r8+8]\npunpckldq xmm2, xmm0\nmovq qword ptr [rcx+rdi+10h], xmm2\nloc_148C:\nadd rsp, 18h\nmov rax, rcx\npop rbx\npop rbp\nretn\nloc_14A0:\nmov dword ptr [rcx], 0\nadd rsp, 18h\nxor edi, edi; size\npop rbx\npop rbp\njmp _malloc\nloc_14B3:\nmov edx, 1\nmov eax, 1\njmp loc_1430", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1390(_DWORD *a1, int a2, unsigned int a3, int *a4)\n{\n int v5; // edi\n __m128i v6; // xmm2\n _DWORD *v7; // rcx\n unsigned int v8; // edx\n __m128i v9; // xmm0\n unsigned __int64 v10; // rax\n __m128i v11; // xmm3\n unsigned int v12; // edx\n int v13; // eax\n int v14; // edx\n __int64 v15; // rdi\n __int64 v16; // r8\n\n if ( a2 > 0 )\n {\n v5 = 2 * a2 - 1;\n *a4 = v5;\n v6 = _mm_cvtsi32_si128(a3);\n v7 = malloc(4LL * v5);\n *v7 = *a1;\n if ( a2 != 1 )\n {\n v8 = a2 - 1;\n if ( (unsigned int)(a2 - 2) <= 2 )\n {\n v14 = 1;\n v13 = 1;\nLABEL_8:\n v15 = v14;\n v16 = v13;\n *(_QWORD *)&v7[v15] = _mm_unpacklo_epi32(v6, _mm_cvtsi32_si128(a1[v16])).m128i_u64[0];\n if ( a2 > v13 + 1 )\n {\n *(_QWORD *)&v7[v15 + 2] = _mm_unpacklo_epi32(v6, _mm_cvtsi32_si128(a1[v16 + 1])).m128i_u64[0];\n if ( a2 > v13 + 2 )\n *(_QWORD *)&v7[v15 + 4] = _mm_unpacklo_epi32(v6, _mm_cvtsi32_si128(a1[v16 + 2])).m128i_u64[0];\n }\n return v7;\n }\n v9 = _mm_shuffle_epi32(v6, 0);\n v10 = 0LL;\n do\n {\n v11 = _mm_loadu_si128((const __m128i *)&a1[v10 / 2 + 1]);\n *(__m128i *)&v7[v10 + 1] = _mm_unpacklo_epi32(v9, v11);\n *(__m128i *)&v7[v10 + 5] = _mm_unpackhi_epi32(v9, v11);\n v10 += 8LL;\n }\n while ( 8LL * (v8 >> 2) != v10 );\n if ( (v8 & 3) != 0 )\n {\n v12 = v8 & 0xFFFFFFFC;\n v13 = v12 + 1;\n v14 = 2 * v12 + 1;\n goto LABEL_8;\n }\n }\n return v7;\n }\n *a4 = 0;\n return malloc(0LL);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1390(uint32_t *a1, int a2, unsigned int a3, int *a4) {\n int v5;\n __m128i v6;\n uint32_t *v7;\n unsigned int v8;\n __m128i v9;\n unsigned long long v10;\n __m128i v11;\n unsigned int v12;\n int v13;\n int v14;\n long long v15;\n long long v16;\n if (a2 > 0) {\n v5 = 2 * a2 - 1;\n *a4 = v5;\n v6 = _mm_cvtsi32_si128(a3);\n v7 = malloc(4LL * v5);\n *v7 = *a1;\n if (a2 != 1) {\n v8 = a2 - 1;\n if ((unsigned int)(a2 - 2) <= 2) {\n v14 = 1;\n v13 = 1;\n LABEL_8:\n v15 = v14;\n v16 = v13;\n *(uint64_t *)&v7[v15] =\n _mm_unpacklo_epi32(v6, _mm_cvtsi32_si128(a1[v16])).m128i_u64[0];\n if (a2 > v13 + 1) {\n *(uint64_t *)&v7[v15 + 2] =\n _mm_unpacklo_epi32(v6, _mm_cvtsi32_si128(a1[v16 + 1]))\n .m128i_u64[0];\n if (a2 > v13 + 2)\n *(uint64_t *)&v7[v15 + 4] =\n _mm_unpacklo_epi32(v6, _mm_cvtsi32_si128(a1[v16 + 2]))\n .m128i_u64[0];\n }\n return v7;\n }\n v9 = _mm_shuffle_epi32(v6, 0);\n v10 = 0LL;\n do {\n v11 = _mm_loadu_si128((const __m128i *)&a1[v10 / 2 + 1]);\n *(__m128i *)&v7[v10 + 1] = _mm_unpacklo_epi32(v9, v11);\n *(__m128i *)&v7[v10 + 5] = _mm_unpackhi_epi32(v9, v11);\n v10 += 8LL;\n } while (8LL * (v8 >> 2) != v10);\n if ((v8 & 3) != 0) {\n v12 = v8 & 4294967292;\n v13 = v12 + 1;\n v14 = 2 * v12 + 1;\n goto LABEL_8;\n }\n }\n return v7;\n }\n *a4 = 0;\n return malloc(0LL);\n}", + "ida_pseudo_norm": "uint32_t *func0(uint32_t *a1, int a2, unsigned int a3, int *a4) {\n int v5;\n __m128i v6;\n uint32_t *v7;\n unsigned int v8;\n __m128i v9;\n unsigned long long v10;\n __m128i v11;\n unsigned int v12;\n int v13;\n int v14;\n long long v15;\n long long v16;\n if (a2 > 0) {\n v5 = 2 * a2 - 1;\n *a4 = v5;\n v6 = _mm_cvtsi32_si128(a3);\n v7 = malloc(4LL * v5);\n *v7 = *a1;\n if (a2 != 1) {\n v8 = a2 - 1;\n if ((unsigned int)(a2 - 2) <= 2) {\n v14 = 1;\n v13 = 1;\n LABEL_8:\n v15 = v14;\n v16 = v13;\n *(uint64_t *)&v7[v15] =\n _mm_unpacklo_epi32(v6, _mm_cvtsi32_si128(a1[v16])).m128i_u64[0];\n if (a2 > v13 + 1) {\n *(uint64_t *)&v7[v15 + 2] =\n _mm_unpacklo_epi32(v6, _mm_cvtsi32_si128(a1[v16 + 1]))\n .m128i_u64[0];\n if (a2 > v13 + 2)\n *(uint64_t *)&v7[v15 + 4] =\n _mm_unpacklo_epi32(v6, _mm_cvtsi32_si128(a1[v16 + 2]))\n .m128i_u64[0];\n }\n return v7;\n }\n v9 = _mm_shuffle_epi32(v6, 0);\n v10 = 0LL;\n do {\n v11 = _mm_loadu_si128((const __m128i *)&a1[v10 / 2 + 1]);\n *(__m128i *)&v7[v10 + 1] = _mm_unpacklo_epi32(v9, v11);\n *(__m128i *)&v7[v10 + 5] = _mm_unpackhi_epi32(v9, v11);\n v10 += 8LL;\n } while (8LL * (v8 >> 2) != v10);\n if ((v8 & 3) != 0) {\n v12 = v8 & 4294967292;\n v13 = v12 + 1;\n v14 = 2 * v12 + 1;\n goto LABEL_8;\n }\n }\n return v7;\n }\n *a4 = 0;\n return malloc(0LL);\n}" + }, + { + "index": "HumanEval-C-6", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int* func0(const char* paren_string, int* returnSize) {\n int* all_levels = NULL;\n int level = 0, max_level = 0, i = 0, count = 0;\n char chr;\n for (i = 0; paren_string[i] != '\\0'; i++) {\n chr = paren_string[i];\n if (chr == '(') {\n level += 1;\n if (level > max_level) max_level = level;\n } else if (chr == ')') {\n level -= 1;\n if (level == 0) {\n all_levels = (int*)realloc(all_levels, sizeof(int) * (count + 1));\n all_levels[count++] = max_level;\n max_level = 0;\n }\n }\n }\n *returnSize = count;\n return all_levels;\n}", + "test": "#include \n\nint issame(const int* a, const int* b, int size_a, int size_b) {\n if (size_a != size_b) return 0;\n for (int i = 0; i < size_a; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int returnSize;\n int* result;\n\n result = func0(\"(()()) ((())) () ((())()())\", &returnSize);\n assert(issame(result, (const int[]){2, 3, 1, 3}, returnSize, 4));\n free(result);\n\n result = func0(\"() (()) ((())) (((())))\", &returnSize);\n assert(issame(result, (const int[]){1, 2, 3, 4}, returnSize, 4));\n free(result);\n\n result = func0(\"(()(())((())))\", &returnSize);\n assert(issame(result, (const int[]){4}, returnSize, 1));\n free(result);\n \n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_30], rsi\nmov [rbp+ptr], 0\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\nmov [rbp+var_10], 0\njmp loc_1277\nloc_11ED:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_19], al\ncmp [rbp+var_19], 28h ; '('\njnz short loc_121A\nadd [rbp+var_18], 1\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_14]\njle short loc_1273\nmov eax, [rbp+var_18]\nmov [rbp+var_14], eax\njmp short loc_1273\nloc_121A:\ncmp [rbp+var_19], 29h ; ')'\njnz short loc_1273\nsub [rbp+var_18], 1\ncmp [rbp+var_18], 0\njnz short loc_1273\nmov eax, [rbp+var_C]\nadd eax, 1\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nmov rsi, rdx; size\nmov rdi, rax; ptr\ncall _realloc\nmov [rbp+ptr], rax\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov eax, [rbp+var_14]\nmov [rdx], eax\nmov [rbp+var_14], 0\nloc_1273:\nadd [rbp+var_10], 1\nloc_1277:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_11ED\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_C]\nmov [rax], edx\nmov rax, [rbp+ptr]\nleave\nretn", + "ida_pseudo": "void *__fastcall func0(__int64 a1, _DWORD *a2)\n{\n int v2; // eax\n char v4; // [rsp+17h] [rbp-19h]\n int v5; // [rsp+18h] [rbp-18h]\n int v6; // [rsp+1Ch] [rbp-14h]\n int i; // [rsp+20h] [rbp-10h]\n int v8; // [rsp+24h] [rbp-Ch]\n void *ptr; // [rsp+28h] [rbp-8h]\n\n ptr = 0LL;\n v5 = 0;\n v6 = 0;\n v8 = 0;\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n {\n v4 = *(_BYTE *)(i + a1);\n if ( v4 == 40 )\n {\n if ( ++v5 > v6 )\n v6 = v5;\n }\n else if ( v4 == 41 && !--v5 )\n {\n ptr = realloc(ptr, 4LL * (v8 + 1));\n v2 = v8++;\n *((_DWORD *)ptr + v2) = v6;\n v6 = 0;\n }\n }\n *a2 = v8;\n return ptr;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_30], rsi\nmov [rbp+ptr], 0\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\nmov [rbp+var_10], 0\njmp loc_1277\nloc_11ED:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_19], al\ncmp [rbp+var_19], 28h ; '('\njnz short loc_121A\nadd [rbp+var_18], 1\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_14]\njle short loc_1273\nmov eax, [rbp+var_18]\nmov [rbp+var_14], eax\njmp short loc_1273\nloc_121A:\ncmp [rbp+var_19], 29h ; ')'\njnz short loc_1273\nsub [rbp+var_18], 1\ncmp [rbp+var_18], 0\njnz short loc_1273\nmov eax, [rbp+var_C]\nadd eax, 1\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nmov rsi, rdx; size\nmov rdi, rax; ptr\ncall _realloc\nmov [rbp+ptr], rax\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov eax, [rbp+var_14]\nmov [rdx], eax\nmov [rbp+var_14], 0\nloc_1273:\nadd [rbp+var_10], 1\nloc_1277:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_11ED\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_C]\nmov [rax], edx\nmov rax, [rbp+ptr]\nleave\nretn", + "ida_strip_pseudo": "void *__fastcall sub_11A9(__int64 a1, _DWORD *a2)\n{\n int v2; // eax\n char v4; // [rsp+17h] [rbp-19h]\n int v5; // [rsp+18h] [rbp-18h]\n int v6; // [rsp+1Ch] [rbp-14h]\n int i; // [rsp+20h] [rbp-10h]\n int v8; // [rsp+24h] [rbp-Ch]\n void *ptr; // [rsp+28h] [rbp-8h]\n\n ptr = 0LL;\n v5 = 0;\n v6 = 0;\n v8 = 0;\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n {\n v4 = *(_BYTE *)(i + a1);\n if ( v4 == 40 )\n {\n if ( ++v5 > v6 )\n v6 = v5;\n }\n else if ( v4 == 41 && !--v5 )\n {\n ptr = realloc(ptr, 4LL * (v8 + 1));\n v2 = v8++;\n *((_DWORD *)ptr + v2) = v6;\n v6 = 0;\n }\n }\n *a2 = v8;\n return ptr;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_11A9(long long a1, uint32_t *a2) {\n int v2;\n char v4;\n int v5;\n int v6;\n int i;\n int v8;\n void *ptr;\n ptr = 0LL;\n v5 = 0;\n v6 = 0;\n v8 = 0;\n for (i = 0; *(uint8_t *)(i + a1); ++i) {\n v4 = *(uint8_t *)(i + a1);\n if (v4 == 40) {\n if (++v5 > v6) v6 = v5;\n } else if (v4 == 41 && !--v5) {\n ptr = realloc(ptr, 4LL * (v8 + 1));\n v2 = v8++;\n *((uint32_t *)ptr + v2) = v6;\n v6 = 0;\n }\n }\n *a2 = v8;\n return ptr;\n}", + "ida_pseudo_norm": "void *func0(long long a1, uint32_t *a2) {\n int v2;\n char v4;\n int v5;\n int v6;\n int i;\n int v8;\n void *ptr;\n ptr = 0LL;\n v5 = 0;\n v6 = 0;\n v8 = 0;\n for (i = 0; *(uint8_t *)(i + a1); ++i) {\n v4 = *(uint8_t *)(i + a1);\n if (v4 == 40) {\n if (++v5 > v6) v6 = v5;\n } else if (v4 == 41 && !--v5) {\n ptr = realloc(ptr, 4LL * (v8 + 1));\n v2 = v8++;\n *((uint32_t *)ptr + v2) = v6;\n v6 = 0;\n }\n }\n *a2 = v8;\n return ptr;\n}" + }, + { + "index": "HumanEval-C-6", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int* func0(const char* paren_string, int* returnSize) {\n int* all_levels = NULL;\n int level = 0, max_level = 0, i = 0, count = 0;\n char chr;\n for (i = 0; paren_string[i] != '\\0'; i++) {\n chr = paren_string[i];\n if (chr == '(') {\n level += 1;\n if (level > max_level) max_level = level;\n } else if (chr == ')') {\n level -= 1;\n if (level == 0) {\n all_levels = (int*)realloc(all_levels, sizeof(int) * (count + 1));\n all_levels[count++] = max_level;\n max_level = 0;\n }\n }\n }\n *returnSize = count;\n return all_levels;\n}", + "test": "#include \n\nint issame(const int* a, const int* b, int size_a, int size_b) {\n if (size_a != size_b) return 0;\n for (int i = 0; i < size_a; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int returnSize;\n int* result;\n\n result = func0(\"(()()) ((())) () ((())()())\", &returnSize);\n assert(issame(result, (const int[]){2, 3, 1, 3}, returnSize, 4));\n free(result);\n\n result = func0(\"() (()) ((())) (((())))\", &returnSize);\n assert(issame(result, (const int[]){1, 2, 3, 4}, returnSize, 4));\n free(result);\n\n result = func0(\"(()(())((())))\", &returnSize);\n assert(issame(result, (const int[]){4}, returnSize, 1));\n free(result);\n \n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r13, rsi\nmovzx edx, byte ptr [rdi]\ntest dl, dl\njz short loc_1226\nlea rbx, [rdi+1]\nmov r14d, 0\nmov r12d, 0\nmov ebp, 0\nmov eax, 0\njmp short loc_11F7\nloc_11E1:\nadd ebp, 1\ncmp r12d, ebp\ncmovl r12d, ebp\nloc_11EB:\nadd rbx, 1\nmovzx edx, byte ptr [rbx-1]\ntest dl, dl\njz short loc_1231\nloc_11F7:\ncmp dl, 28h ; '('\njz short loc_11E1\ncmp dl, 29h ; ')'\njnz short loc_11EB\nsub ebp, 1\njnz short loc_11EB\nadd r14d, 1\nmovsxd r15, r14d\nshl r15, 2\nmov rsi, r15; size\nmov rdi, rax; ptr\ncall _realloc\nmov [rax+r15-4], r12d\nmov r12d, ebp\njmp short loc_11EB\nloc_1226:\nmov r14d, 0\nmov eax, 0\nloc_1231:\nmov [r13+0], r14d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "void *__fastcall func0(char *a1, _DWORD *a2)\n{\n char v2; // dl\n char *v3; // rbx\n int v4; // r14d\n int v5; // r12d\n int v6; // ebp\n void *result; // rax\n\n v2 = *a1;\n if ( *a1 )\n {\n v3 = a1 + 1;\n v4 = 0;\n v5 = 0;\n v6 = 0;\n result = 0LL;\n do\n {\n if ( v2 == 40 )\n {\n if ( v5 < ++v6 )\n v5 = v6;\n }\n else if ( v2 == 41 && !--v6 )\n {\n result = realloc(result, 4LL * ++v4);\n *((_DWORD *)result + v4 - 1) = v5;\n v5 = 0;\n }\n v2 = *v3++;\n }\n while ( v2 );\n }\n else\n {\n v4 = 0;\n result = 0LL;\n }\n *a2 = v4;\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r13, rsi\nmovzx edx, byte ptr [rdi]\ntest dl, dl\njz short loc_1226\nlea rbx, [rdi+1]\nmov r14d, 0\nmov r12d, 0\nmov ebp, 0\nmov eax, 0\njmp short loc_11F7\nloc_11E1:\nadd ebp, 1\ncmp r12d, ebp\ncmovl r12d, ebp\nloc_11EB:\nadd rbx, 1\nmovzx edx, byte ptr [rbx-1]\ntest dl, dl\njz short loc_1231\nloc_11F7:\ncmp dl, 28h ; '('\njz short loc_11E1\ncmp dl, 29h ; ')'\njnz short loc_11EB\nsub ebp, 1\njnz short loc_11EB\nadd r14d, 1\nmovsxd r15, r14d\nshl r15, 2\nmov rsi, r15; size\nmov rdi, rax; ptr\ncall _realloc\nmov [rax+r15-4], r12d\nmov r12d, ebp\njmp short loc_11EB\nloc_1226:\nmov r14d, 0\nmov eax, 0\nloc_1231:\nmov [r13+0], r14d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "void *__fastcall sub_11A9(char *a1, _DWORD *a2)\n{\n char v2; // dl\n char *v3; // rbx\n int v4; // r14d\n int v5; // r12d\n int v6; // ebp\n void *result; // rax\n\n v2 = *a1;\n if ( *a1 )\n {\n v3 = a1 + 1;\n v4 = 0;\n v5 = 0;\n v6 = 0;\n result = 0LL;\n do\n {\n if ( v2 == 40 )\n {\n if ( v5 < ++v6 )\n v5 = v6;\n }\n else if ( v2 == 41 && !--v6 )\n {\n result = realloc(result, 4LL * ++v4);\n *((_DWORD *)result + v4 - 1) = v5;\n v5 = 0;\n }\n v2 = *v3++;\n }\n while ( v2 );\n }\n else\n {\n v4 = 0;\n result = 0LL;\n }\n *a2 = v4;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_11A9(char *a1, uint32_t *a2) {\n char v2;\n char *v3;\n int v4;\n int v5;\n int v6;\n void *result;\n v2 = *a1;\n if (*a1) {\n v3 = a1 + 1;\n v4 = 0;\n v5 = 0;\n v6 = 0;\n result = 0LL;\n do {\n if (v2 == 40) {\n if (v5 < ++v6) v5 = v6;\n } else if (v2 == 41 && !--v6) {\n result = realloc(result, 4LL * ++v4);\n *((uint32_t *)result + v4 - 1) = v5;\n v5 = 0;\n }\n v2 = *v3++;\n } while (v2);\n } else {\n v4 = 0;\n result = 0LL;\n }\n *a2 = v4;\n return result;\n}", + "ida_pseudo_norm": "void *func0(char *a1, uint32_t *a2) {\n char v2;\n char *v3;\n int v4;\n int v5;\n int v6;\n void *result;\n v2 = *a1;\n if (*a1) {\n v3 = a1 + 1;\n v4 = 0;\n v5 = 0;\n v6 = 0;\n result = 0LL;\n do {\n if (v2 == 40) {\n if (v5 < ++v6) v5 = v6;\n } else if (v2 == 41 && !--v6) {\n result = realloc(result, 4LL * ++v4);\n *((uint32_t *)result + v4 - 1) = v5;\n v5 = 0;\n }\n v2 = *v3++;\n } while (v2);\n } else {\n v4 = 0;\n result = 0LL;\n }\n *a2 = v4;\n return result;\n}" + }, + { + "index": "HumanEval-C-6", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int* func0(const char* paren_string, int* returnSize) {\n int* all_levels = NULL;\n int level = 0, max_level = 0, i = 0, count = 0;\n char chr;\n for (i = 0; paren_string[i] != '\\0'; i++) {\n chr = paren_string[i];\n if (chr == '(') {\n level += 1;\n if (level > max_level) max_level = level;\n } else if (chr == ')') {\n level -= 1;\n if (level == 0) {\n all_levels = (int*)realloc(all_levels, sizeof(int) * (count + 1));\n all_levels[count++] = max_level;\n max_level = 0;\n }\n }\n }\n *returnSize = count;\n return all_levels;\n}", + "test": "#include \n\nint issame(const int* a, const int* b, int size_a, int size_b) {\n if (size_a != size_b) return 0;\n for (int i = 0; i < size_a; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int returnSize;\n int* result;\n\n result = func0(\"(()()) ((())) () ((())()())\", &returnSize);\n assert(issame(result, (const int[]){2, 3, 1, 3}, returnSize, 4));\n free(result);\n\n result = func0(\"() (()) ((())) (((())))\", &returnSize);\n assert(issame(result, (const int[]){1, 2, 3, 4}, returnSize, 4));\n free(result);\n\n result = func0(\"(()(())((())))\", &returnSize);\n assert(issame(result, (const int[]){4}, returnSize, 1));\n free(result);\n \n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\nmov r13, rsi\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmovzx edx, byte ptr [rdi]\ntest dl, dl\njz short loc_13D8\nlea rbx, [rdi+1]\nxor r14d, r14d\nxor r12d, r12d\nxor ebp, ebp\nxor eax, eax\njmp short loc_1380\nloc_1370:\ncmp dl, 29h ; ')'\njz short loc_13B0\nloc_1375:\nmovzx edx, byte ptr [rbx]\nadd rbx, 1\ntest dl, dl\njz short loc_139A\nloc_1380:\ncmp dl, 28h ; '('\njnz short loc_1370\nadd ebp, 1\ncmp r12d, ebp\ncmovl r12d, ebp\nmovzx edx, byte ptr [rbx]\nadd rbx, 1\ntest dl, dl\njnz short loc_1380\nloc_139A:\nmov [r13+0], r14d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_13B0:\nsub ebp, 1\njnz short loc_1375\nadd r14d, 1\nmov rdi, rax; ptr\nmovsxd r15, r14d\nshl r15, 2\nmov rsi, r15; size\ncall _realloc\nmov [rax+r15-4], r12d\nxor r12d, r12d\njmp short loc_1375\nloc_13D8:\nxor r14d, r14d\nxor eax, eax\njmp short loc_139A", + "ida_pseudo": "void *__fastcall func0(char *a1, _DWORD *a2)\n{\n char v2; // dl\n char *v3; // rbx\n int v4; // r14d\n int v5; // r12d\n int v6; // ebp\n void *result; // rax\n\n v2 = *a1;\n if ( *a1 )\n {\n v3 = a1 + 1;\n v4 = 0;\n v5 = 0;\n v6 = 0;\n result = 0LL;\n do\n {\n while ( v2 == 40 )\n {\n if ( v5 < ++v6 )\n v5 = v6;\n v2 = *v3++;\n if ( !v2 )\n goto LABEL_9;\n }\n if ( v2 == 41 && !--v6 )\n {\n result = realloc(result, 4LL * ++v4);\n *((_DWORD *)result + v4 - 1) = v5;\n v5 = 0;\n }\n v2 = *v3++;\n }\n while ( v2 );\n }\n else\n {\n v4 = 0;\n result = 0LL;\n }\nLABEL_9:\n *a2 = v4;\n return result;\n}", + "ida_strip_asm": "sub_1340:\nendbr64\npush r15\npush r14\npush r13\nmov r13, rsi\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmovzx edx, byte ptr [rdi]\ntest dl, dl\njz short loc_13D8\nlea rbx, [rdi+1]\nxor r14d, r14d\nxor r12d, r12d\nxor ebp, ebp\nxor eax, eax\njmp short loc_1380\nloc_1370:\ncmp dl, 29h ; ')'\njz short loc_13B0\nloc_1375:\nmovzx edx, byte ptr [rbx]\nadd rbx, 1\ntest dl, dl\njz short loc_139A\nloc_1380:\ncmp dl, 28h ; '('\njnz short loc_1370\nadd ebp, 1\ncmp r12d, ebp\ncmovl r12d, ebp\nmovzx edx, byte ptr [rbx]\nadd rbx, 1\ntest dl, dl\njnz short loc_1380\nloc_139A:\nmov [r13+0], r14d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_13B0:\nsub ebp, 1\njnz short loc_1375\nadd r14d, 1\nmov rdi, rax; ptr\nmovsxd r15, r14d\nshl r15, 2\nmov rsi, r15; size\ncall _realloc\nmov [rax+r15-4], r12d\nxor r12d, r12d\njmp short loc_1375\nloc_13D8:\nxor r14d, r14d\nxor eax, eax\njmp short loc_139A", + "ida_strip_pseudo": "void *__fastcall sub_1340(char *a1, _DWORD *a2)\n{\n char v2; // dl\n char *v3; // rbx\n int v4; // r14d\n int v5; // r12d\n int v6; // ebp\n void *result; // rax\n\n v2 = *a1;\n if ( *a1 )\n {\n v3 = a1 + 1;\n v4 = 0;\n v5 = 0;\n v6 = 0;\n result = 0LL;\n do\n {\n while ( v2 == 40 )\n {\n if ( v5 < ++v6 )\n v5 = v6;\n v2 = *v3++;\n if ( !v2 )\n goto LABEL_9;\n }\n if ( v2 == 41 && !--v6 )\n {\n result = realloc(result, 4LL * ++v4);\n *((_DWORD *)result + v4 - 1) = v5;\n v5 = 0;\n }\n v2 = *v3++;\n }\n while ( v2 );\n }\n else\n {\n v4 = 0;\n result = 0LL;\n }\nLABEL_9:\n *a2 = v4;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1340(char *a1, uint32_t *a2) {\n char v2;\n char *v3;\n int v4;\n int v5;\n int v6;\n void *result;\n v2 = *a1;\n if (*a1) {\n v3 = a1 + 1;\n v4 = 0;\n v5 = 0;\n v6 = 0;\n result = 0LL;\n do {\n while (v2 == 40) {\n if (v5 < ++v6) v5 = v6;\n v2 = *v3++;\n if (!v2) goto LABEL_9;\n }\n if (v2 == 41 && !--v6) {\n result = realloc(result, 4LL * ++v4);\n *((uint32_t *)result + v4 - 1) = v5;\n v5 = 0;\n }\n v2 = *v3++;\n } while (v2);\n } else {\n v4 = 0;\n result = 0LL;\n }\nLABEL_9:\n *a2 = v4;\n return result;\n}", + "ida_pseudo_norm": "void *func0(char *a1, uint32_t *a2) {\n char v2;\n char *v3;\n int v4;\n int v5;\n int v6;\n void *result;\n v2 = *a1;\n if (*a1) {\n v3 = a1 + 1;\n v4 = 0;\n v5 = 0;\n v6 = 0;\n result = 0LL;\n do {\n while (v2 == 40) {\n if (v5 < ++v6) v5 = v6;\n v2 = *v3++;\n if (!v2) goto LABEL_9;\n }\n if (v2 == 41 && !--v6) {\n result = realloc(result, 4LL * ++v4);\n *((uint32_t *)result + v4 - 1) = v5;\n v5 = 0;\n }\n v2 = *v3++;\n } while (v2);\n } else {\n v4 = 0;\n result = 0LL;\n }\nLABEL_9:\n *a2 = v4;\n return result;\n}" + }, + { + "index": "HumanEval-C-6", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int* func0(const char* paren_string, int* returnSize) {\n int* all_levels = NULL;\n int level = 0, max_level = 0, i = 0, count = 0;\n char chr;\n for (i = 0; paren_string[i] != '\\0'; i++) {\n chr = paren_string[i];\n if (chr == '(') {\n level += 1;\n if (level > max_level) max_level = level;\n } else if (chr == ')') {\n level -= 1;\n if (level == 0) {\n all_levels = (int*)realloc(all_levels, sizeof(int) * (count + 1));\n all_levels[count++] = max_level;\n max_level = 0;\n }\n }\n }\n *returnSize = count;\n return all_levels;\n}", + "test": "#include \n\nint issame(const int* a, const int* b, int size_a, int size_b) {\n if (size_a != size_b) return 0;\n for (int i = 0; i < size_a; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int returnSize;\n int* result;\n\n result = func0(\"(()()) ((())) () ((())()())\", &returnSize);\n assert(issame(result, (const int[]){2, 3, 1, 3}, returnSize, 4));\n free(result);\n\n result = func0(\"() (()) ((())) (((())))\", &returnSize);\n assert(issame(result, (const int[]){1, 2, 3, 4}, returnSize, 4));\n free(result);\n\n result = func0(\"(()(())((())))\", &returnSize);\n assert(issame(result, (const int[]){4}, returnSize, 1));\n free(result);\n \n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\nmov r13, rsi\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmovzx edx, byte ptr [rdi]\ntest dl, dl\njz short loc_13D8\nlea rbx, [rdi+1]\nxor r14d, r14d\nxor r12d, r12d\nxor ebp, ebp\nxor eax, eax\njmp short loc_1380\nloc_1370:\ncmp dl, 29h ; ')'\njz short loc_13B0\nloc_1375:\nmovzx edx, byte ptr [rbx]\nadd rbx, 1\ntest dl, dl\njz short loc_139A\nloc_1380:\ncmp dl, 28h ; '('\njnz short loc_1370\nadd ebp, 1\ncmp r12d, ebp\ncmovl r12d, ebp\nmovzx edx, byte ptr [rbx]\nadd rbx, 1\ntest dl, dl\njnz short loc_1380\nloc_139A:\nmov [r13+0], r14d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_13B0:\nsub ebp, 1\njnz short loc_1375\nadd r14d, 1\nmov rdi, rax; ptr\nmovsxd r15, r14d\nshl r15, 2\nmov rsi, r15; size\ncall _realloc\nmov [rax+r15-4], r12d\nxor r12d, r12d\njmp short loc_1375\nloc_13D8:\nxor r14d, r14d\nxor eax, eax\njmp short loc_139A", + "ida_pseudo": "void *__fastcall func0(char *a1, _DWORD *a2)\n{\n char v2; // dl\n char *v3; // rbx\n int v4; // r14d\n int v5; // r12d\n int v6; // ebp\n void *result; // rax\n\n v2 = *a1;\n if ( *a1 )\n {\n v3 = a1 + 1;\n v4 = 0;\n v5 = 0;\n v6 = 0;\n result = 0LL;\n do\n {\n while ( v2 == 40 )\n {\n if ( v5 < ++v6 )\n v5 = v6;\n v2 = *v3++;\n if ( !v2 )\n goto LABEL_9;\n }\n if ( v2 == 41 && !--v6 )\n {\n result = realloc(result, 4LL * ++v4);\n *((_DWORD *)result + v4 - 1) = v5;\n v5 = 0;\n }\n v2 = *v3++;\n }\n while ( v2 );\n }\n else\n {\n v4 = 0;\n result = 0LL;\n }\nLABEL_9:\n *a2 = v4;\n return result;\n}", + "ida_strip_asm": "sub_1340:\nendbr64\npush r15\npush r14\npush r13\nmov r13, rsi\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmovzx edx, byte ptr [rdi]\ntest dl, dl\njz short loc_13D8\nlea rbx, [rdi+1]\nxor r14d, r14d\nxor r12d, r12d\nxor ebp, ebp\nxor eax, eax\njmp short loc_1380\nloc_1370:\ncmp dl, 29h ; ')'\njz short loc_13B0\nloc_1375:\nmovzx edx, byte ptr [rbx]\nadd rbx, 1\ntest dl, dl\njz short loc_139A\nloc_1380:\ncmp dl, 28h ; '('\njnz short loc_1370\nadd ebp, 1\ncmp r12d, ebp\ncmovl r12d, ebp\nmovzx edx, byte ptr [rbx]\nadd rbx, 1\ntest dl, dl\njnz short loc_1380\nloc_139A:\nmov [r13+0], r14d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_13B0:\nsub ebp, 1\njnz short loc_1375\nadd r14d, 1\nmov rdi, rax; ptr\nmovsxd r15, r14d\nshl r15, 2\nmov rsi, r15; size\ncall _realloc\nmov [rax+r15-4], r12d\nxor r12d, r12d\njmp short loc_1375\nloc_13D8:\nxor r14d, r14d\nxor eax, eax\njmp short loc_139A", + "ida_strip_pseudo": "void *__fastcall sub_1340(char *a1, _DWORD *a2)\n{\n char v2; // dl\n char *v3; // rbx\n int v4; // r14d\n int v5; // r12d\n int v6; // ebp\n void *result; // rax\n\n v2 = *a1;\n if ( *a1 )\n {\n v3 = a1 + 1;\n v4 = 0;\n v5 = 0;\n v6 = 0;\n result = 0LL;\n do\n {\n while ( v2 == 40 )\n {\n if ( v5 < ++v6 )\n v5 = v6;\n v2 = *v3++;\n if ( !v2 )\n goto LABEL_9;\n }\n if ( v2 == 41 && !--v6 )\n {\n result = realloc(result, 4LL * ++v4);\n *((_DWORD *)result + v4 - 1) = v5;\n v5 = 0;\n }\n v2 = *v3++;\n }\n while ( v2 );\n }\n else\n {\n v4 = 0;\n result = 0LL;\n }\nLABEL_9:\n *a2 = v4;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1340(char *a1, uint32_t *a2) {\n char v2;\n char *v3;\n int v4;\n int v5;\n int v6;\n void *result;\n v2 = *a1;\n if (*a1) {\n v3 = a1 + 1;\n v4 = 0;\n v5 = 0;\n v6 = 0;\n result = 0LL;\n do {\n while (v2 == 40) {\n if (v5 < ++v6) v5 = v6;\n v2 = *v3++;\n if (!v2) goto LABEL_9;\n }\n if (v2 == 41 && !--v6) {\n result = realloc(result, 4LL * ++v4);\n *((uint32_t *)result + v4 - 1) = v5;\n v5 = 0;\n }\n v2 = *v3++;\n } while (v2);\n } else {\n v4 = 0;\n result = 0LL;\n }\nLABEL_9:\n *a2 = v4;\n return result;\n}", + "ida_pseudo_norm": "void *func0(char *a1, uint32_t *a2) {\n char v2;\n char *v3;\n int v4;\n int v5;\n int v6;\n void *result;\n v2 = *a1;\n if (*a1) {\n v3 = a1 + 1;\n v4 = 0;\n v5 = 0;\n v6 = 0;\n result = 0LL;\n do {\n while (v2 == 40) {\n if (v5 < ++v6) v5 = v6;\n v2 = *v3++;\n if (!v2) goto LABEL_9;\n }\n if (v2 == 41 && !--v6) {\n result = realloc(result, 4LL * ++v4);\n *((uint32_t *)result + v4 - 1) = v5;\n v5 = 0;\n }\n v2 = *v3++;\n } while (v2);\n } else {\n v4 = 0;\n result = 0LL;\n }\nLABEL_9:\n *a2 = v4;\n return result;\n}" + }, + { + "index": "HumanEval-C-7", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char **func0(char **strings, int size, const char *substring, int *out_size) {\n char **out = NULL;\n int count = 0;\n for (int i = 0; i < size; i++) {\n if (strstr(strings[i], substring) != NULL) {\n out = (char **)realloc(out, sizeof(char *) * (count + 1));\n out[count] = strings[i];\n count++;\n }\n }\n *out_size = count;\n return out;\n}", + "test": "#include \n#include \n#include \n#include \n\nint issame(char **a, char **b, int size_a, int size_b) {\n if (size_a != size_b) return 0;\n for (int i = 0; i < size_a; i++) {\n if (strcmp(a[i], b[i]) != 0) return 0;\n }\n return 1;\n}\n\nint main() {\n int out_size;\n char **result;\n\n // First test case with empty array and substring \"john\"\n result = func0(NULL, 0, \"john\", &out_size);\n assert(out_size == 0 && result == NULL);\n\n // Second test case\n char *strings1[] = {\"xxx\", \"asd\", \"xxy\", \"john doe\", \"xxxAAA\", \"xxx\"};\n char *expected1[] = {\"xxx\", \"xxxAAA\", \"xxx\"};\n result = func0(strings1, 6, \"xxx\", &out_size);\n assert(issame(result, expected1, out_size, 3));\n free(result);\n\n // Third test case\n char *strings2[] = {\"xxx\", \"asd\", \"aaaxxy\", \"john doe\", \"xxxAAA\", \"xxx\"};\n char *expected2[] = {\"xxx\", \"aaaxxy\", \"xxxAAA\", \"xxx\"};\n result = func0(strings2, 6, \"xx\", &out_size);\n assert(issame(result, expected2, out_size, 4));\n free(result);\n\n // Fourth test case\n char *strings3[] = {\"grunt\", \"trumpet\", \"prune\", \"gruesome\"};\n char *expected3[] = {\"grunt\", \"prune\"};\n result = func0(strings3, 4, \"run\", &out_size);\n assert(issame(result, expected3, out_size, 2));\n free(result);\n \n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+needle], rdx\nmov [rbp+var_30], rcx\nmov [rbp+ptr], 0\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp loc_12A4\nloc_121F:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov rdx, [rbp+needle]\nmov rsi, rdx; needle\nmov rdi, rax; haystack\ncall _strstr\ntest rax, rax\njz short loc_12A0\nmov eax, [rbp+var_10]\nadd eax, 1\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nmov rsi, rdx; size\nmov rdi, rax; ptr\ncall _realloc\nmov [rbp+ptr], rax\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+ptr]\nadd rdx, rcx\nmov rax, [rax]\nmov [rdx], rax\nadd [rbp+var_10], 1\nloc_12A0:\nadd [rbp+var_C], 1\nloc_12A4:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl loc_121F\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_10]\nmov [rax], edx\nmov rax, [rbp+ptr]\nleave\nretn", + "ida_pseudo": "void *__fastcall func0(__int64 a1, int a2, const char *a3, _DWORD *a4)\n{\n int v7; // [rsp+20h] [rbp-10h]\n int i; // [rsp+24h] [rbp-Ch]\n void *ptr; // [rsp+28h] [rbp-8h]\n\n ptr = 0LL;\n v7 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( strstr(*(const char **)(8LL * i + a1), a3) )\n {\n ptr = realloc(ptr, 8LL * (v7 + 1));\n *((_QWORD *)ptr + v7++) = *(_QWORD *)(8LL * i + a1);\n }\n }\n *a4 = v7;\n return ptr;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+needle], rdx\nmov [rbp+var_30], rcx\nmov [rbp+ptr], 0\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp loc_12A4\nloc_121F:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov rdx, [rbp+needle]\nmov rsi, rdx; needle\nmov rdi, rax; haystack\ncall _strstr\ntest rax, rax\njz short loc_12A0\nmov eax, [rbp+var_10]\nadd eax, 1\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nmov rsi, rdx; size\nmov rdi, rax; ptr\ncall _realloc\nmov [rbp+ptr], rax\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+ptr]\nadd rdx, rcx\nmov rax, [rax]\nmov [rdx], rax\nadd [rbp+var_10], 1\nloc_12A0:\nadd [rbp+var_C], 1\nloc_12A4:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl loc_121F\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_10]\nmov [rax], edx\nmov rax, [rbp+ptr]\nleave\nretn", + "ida_strip_pseudo": "void *__fastcall sub_11E9(__int64 a1, int a2, const char *a3, _DWORD *a4)\n{\n int v7; // [rsp+20h] [rbp-10h]\n int i; // [rsp+24h] [rbp-Ch]\n void *ptr; // [rsp+28h] [rbp-8h]\n\n ptr = 0LL;\n v7 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( strstr(*(const char **)(8LL * i + a1), a3) )\n {\n ptr = realloc(ptr, 8LL * (v7 + 1));\n *((_QWORD *)ptr + v7++) = *(_QWORD *)(8LL * i + a1);\n }\n }\n *a4 = v7;\n return ptr;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_11E9(long long a1, int a2, const char *a3, uint32_t *a4) {\n int v7;\n int i;\n void *ptr;\n ptr = 0LL;\n v7 = 0;\n for (i = 0; i < a2; ++i) {\n if (strstr(*(const char **)(8LL * i + a1), a3)) {\n ptr = realloc(ptr, 8LL * (v7 + 1));\n *((uint64_t *)ptr + v7++) = *(uint64_t *)(8LL * i + a1);\n }\n }\n *a4 = v7;\n return ptr;\n}", + "ida_pseudo_norm": "void *func0(long long a1, int a2, const char *a3, uint32_t *a4) {\n int v7;\n int i;\n void *ptr;\n ptr = 0LL;\n v7 = 0;\n for (i = 0; i < a2; ++i) {\n if (strstr(*(const char **)(8LL * i + a1), a3)) {\n ptr = realloc(ptr, 8LL * (v7 + 1));\n *((uint64_t *)ptr + v7++) = *(uint64_t *)(8LL * i + a1);\n }\n }\n *a4 = v7;\n return ptr;\n}" + }, + { + "index": "HumanEval-C-7", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char **func0(char **strings, int size, const char *substring, int *out_size) {\n char **out = NULL;\n int count = 0;\n for (int i = 0; i < size; i++) {\n if (strstr(strings[i], substring) != NULL) {\n out = (char **)realloc(out, sizeof(char *) * (count + 1));\n out[count] = strings[i];\n count++;\n }\n }\n *out_size = count;\n return out;\n}", + "test": "#include \n#include \n#include \n#include \n\nint issame(char **a, char **b, int size_a, int size_b) {\n if (size_a != size_b) return 0;\n for (int i = 0; i < size_a; i++) {\n if (strcmp(a[i], b[i]) != 0) return 0;\n }\n return 1;\n}\n\nint main() {\n int out_size;\n char **result;\n\n // First test case with empty array and substring \"john\"\n result = func0(NULL, 0, \"john\", &out_size);\n assert(out_size == 0 && result == NULL);\n\n // Second test case\n char *strings1[] = {\"xxx\", \"asd\", \"xxy\", \"john doe\", \"xxxAAA\", \"xxx\"};\n char *expected1[] = {\"xxx\", \"xxxAAA\", \"xxx\"};\n result = func0(strings1, 6, \"xxx\", &out_size);\n assert(issame(result, expected1, out_size, 3));\n free(result);\n\n // Third test case\n char *strings2[] = {\"xxx\", \"asd\", \"aaaxxy\", \"john doe\", \"xxxAAA\", \"xxx\"};\n char *expected2[] = {\"xxx\", \"aaaxxy\", \"xxxAAA\", \"xxx\"};\n result = func0(strings2, 6, \"xx\", &out_size);\n assert(issame(result, expected2, out_size, 4));\n free(result);\n\n // Fourth test case\n char *strings3[] = {\"grunt\", \"trumpet\", \"prune\", \"gruesome\"};\n char *expected3[] = {\"grunt\", \"prune\"};\n result = func0(strings3, 4, \"run\", &out_size);\n assert(issame(result, expected3, out_size, 2));\n free(result);\n \n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+needle], rdx\nmov [rsp+48h+var_40], rcx\ntest esi, esi\njle short loc_125C\nmov rbx, rdi\nmovsxd rsi, esi\nlea r15, [rdi+rsi*8]\nmov r14d, 0\nmov ebp, 0\njmp short loc_1228\nloc_121F:\nadd rbx, 8\ncmp rbx, r15\njz short loc_1267\nloc_1228:\nmov r13, [rbx]\nmov rsi, [rsp+48h+needle]; needle\nmov rdi, r13; haystack\ncall _strstr\ntest rax, rax\njz short loc_121F\nadd r14d, 1\nmovsxd r12, r14d\nshl r12, 3\nmov rsi, r12; size\nmov rdi, rbp; ptr\ncall _realloc\nmov rbp, rax\nmov [rax+r12-8], r13\njmp short loc_121F\nloc_125C:\nmov r14d, 0\nmov ebp, 0\nloc_1267:\nmov rax, [rsp+48h+var_40]\nmov [rax], r14d\nmov rax, rbp\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "void *__fastcall func0(const char **a1, int a2, const char *a3, _DWORD *a4)\n{\n const char **v4; // rbx\n int v5; // r14d\n void *v6; // rbp\n const char *v7; // r13\n\n if ( a2 <= 0 )\n {\n v5 = 0;\n v6 = 0LL;\n }\n else\n {\n v4 = a1;\n v5 = 0;\n v6 = 0LL;\n do\n {\n v7 = *v4;\n if ( strstr(*v4, a3) )\n {\n v6 = realloc(v6, 8LL * ++v5);\n *((_QWORD *)v6 + v5 - 1) = v7;\n }\n ++v4;\n }\n while ( v4 != &a1[a2] );\n }\n *a4 = v5;\n return v6;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+needle], rdx\nmov [rsp+48h+var_40], rcx\ntest esi, esi\njle short loc_125C\nmov rbx, rdi\nmovsxd rsi, esi\nlea r15, [rdi+rsi*8]\nmov r14d, 0\nmov ebp, 0\njmp short loc_1228\nloc_121F:\nadd rbx, 8\ncmp rbx, r15\njz short loc_1267\nloc_1228:\nmov r13, [rbx]\nmov rsi, [rsp+48h+needle]; needle\nmov rdi, r13; haystack\ncall _strstr\ntest rax, rax\njz short loc_121F\nadd r14d, 1\nmovsxd r12, r14d\nshl r12, 3\nmov rsi, r12; size\nmov rdi, rbp; ptr\ncall _realloc\nmov rbp, rax\nmov [rax+r12-8], r13\njmp short loc_121F\nloc_125C:\nmov r14d, 0\nmov ebp, 0\nloc_1267:\nmov rax, [rsp+48h+var_40]\nmov [rax], r14d\nmov rax, rbp\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "void *__fastcall sub_11E9(const char **a1, int a2, const char *a3, _DWORD *a4)\n{\n const char **v4; // rbx\n int v5; // r14d\n void *v6; // rbp\n const char *v7; // r13\n\n if ( a2 <= 0 )\n {\n v5 = 0;\n v6 = 0LL;\n }\n else\n {\n v4 = a1;\n v5 = 0;\n v6 = 0LL;\n do\n {\n v7 = *v4;\n if ( strstr(*v4, a3) )\n {\n v6 = realloc(v6, 8LL * ++v5);\n *((_QWORD *)v6 + v5 - 1) = v7;\n }\n ++v4;\n }\n while ( v4 != &a1[a2] );\n }\n *a4 = v5;\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_11E9(const char **a1, int a2, const char *a3, uint32_t *a4) {\n const char **v4;\n int v5;\n void *v6;\n const char *v7;\n if (a2 <= 0) {\n v5 = 0;\n v6 = 0LL;\n } else {\n v4 = a1;\n v5 = 0;\n v6 = 0LL;\n do {\n v7 = *v4;\n if (strstr(*v4, a3)) {\n v6 = realloc(v6, 8LL * ++v5);\n *((uint64_t *)v6 + v5 - 1) = v7;\n }\n ++v4;\n } while (v4 != &a1[a2]);\n }\n *a4 = v5;\n return v6;\n}", + "ida_pseudo_norm": "void *func0(const char **a1, int a2, const char *a3, uint32_t *a4) {\n const char **v4;\n int v5;\n void *v6;\n const char *v7;\n if (a2 <= 0) {\n v5 = 0;\n v6 = 0LL;\n } else {\n v4 = a1;\n v5 = 0;\n v6 = 0LL;\n do {\n v7 = *v4;\n if (strstr(*v4, a3)) {\n v6 = realloc(v6, 8LL * ++v5);\n *((uint64_t *)v6 + v5 - 1) = v7;\n }\n ++v4;\n } while (v4 != &a1[a2]);\n }\n *a4 = v5;\n return v6;\n}" + }, + { + "index": "HumanEval-C-7", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char **func0(char **strings, int size, const char *substring, int *out_size) {\n char **out = NULL;\n int count = 0;\n for (int i = 0; i < size; i++) {\n if (strstr(strings[i], substring) != NULL) {\n out = (char **)realloc(out, sizeof(char *) * (count + 1));\n out[count] = strings[i];\n count++;\n }\n }\n *out_size = count;\n return out;\n}", + "test": "#include \n#include \n#include \n#include \n\nint issame(char **a, char **b, int size_a, int size_b) {\n if (size_a != size_b) return 0;\n for (int i = 0; i < size_a; i++) {\n if (strcmp(a[i], b[i]) != 0) return 0;\n }\n return 1;\n}\n\nint main() {\n int out_size;\n char **result;\n\n // First test case with empty array and substring \"john\"\n result = func0(NULL, 0, \"john\", &out_size);\n assert(out_size == 0 && result == NULL);\n\n // Second test case\n char *strings1[] = {\"xxx\", \"asd\", \"xxy\", \"john doe\", \"xxxAAA\", \"xxx\"};\n char *expected1[] = {\"xxx\", \"xxxAAA\", \"xxx\"};\n result = func0(strings1, 6, \"xxx\", &out_size);\n assert(issame(result, expected1, out_size, 3));\n free(result);\n\n // Third test case\n char *strings2[] = {\"xxx\", \"asd\", \"aaaxxy\", \"john doe\", \"xxxAAA\", \"xxx\"};\n char *expected2[] = {\"xxx\", \"aaaxxy\", \"xxxAAA\", \"xxx\"};\n result = func0(strings2, 6, \"xx\", &out_size);\n assert(issame(result, expected2, out_size, 4));\n free(result);\n\n // Fourth test case\n char *strings3[] = {\"grunt\", \"trumpet\", \"prune\", \"gruesome\"};\n char *expected3[] = {\"grunt\", \"prune\"};\n result = func0(strings3, 4, \"run\", &out_size);\n assert(issame(result, expected3, out_size, 2));\n free(result);\n \n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+needle], rdx\nmov [rsp+48h+var_40], rcx\ntest esi, esi\njle short loc_1610\nmovsxd rsi, esi\nmov r15, rdi\nxor r12d, r12d\nxor ebx, ebx\nlea r14, [rdi+rsi*8]\nxchg ax, ax\nloc_15B0:\nmov rbp, [r15]\nmov rsi, [rsp+48h+needle]; needle\nmov rdi, rbp; haystack\ncall _strstr\ntest rax, rax\njz short loc_15E6\nadd r12d, 1\nmov rdi, rbx; ptr\nmovsxd rcx, r12d\nlea r13, ds:0[rcx*8]\nmov rsi, r13; size\ncall _realloc\nmov [rax+r13-8], rbp\nmov rbx, rax\nloc_15E6:\nadd r15, 8\ncmp r15, r14\njnz short loc_15B0\nloc_15EF:\nmov rax, [rsp+48h+var_40]\nmov [rax], r12d\nadd rsp, 18h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1610:\nxor r12d, r12d\nxor ebx, ebx\njmp short loc_15EF", + "ida_pseudo": "void *__fastcall func0(const char **a1, int a2, const char *a3, _DWORD *a4)\n{\n const char **v4; // r15\n int v5; // r12d\n void *v6; // rbx\n const char *v7; // rbp\n _QWORD *v8; // rax\n\n if ( a2 <= 0 )\n {\n v5 = 0;\n v6 = 0LL;\n }\n else\n {\n v4 = a1;\n v5 = 0;\n v6 = 0LL;\n do\n {\n v7 = *v4;\n if ( strstr(*v4, a3) )\n {\n v8 = realloc(v6, 8LL * ++v5);\n v8[v5 - 1] = v7;\n v6 = v8;\n }\n ++v4;\n }\n while ( v4 != &a1[a2] );\n }\n *a4 = v5;\n return v6;\n}", + "ida_strip_asm": "sub_1580:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+needle], rdx\nmov [rsp+48h+var_40], rcx\ntest esi, esi\njle short loc_1610\nmovsxd rsi, esi\nmov r15, rdi\nxor r12d, r12d\nxor ebx, ebx\nlea r14, [rdi+rsi*8]\nxchg ax, ax\nloc_15B0:\nmov rbp, [r15]\nmov rsi, [rsp+48h+needle]; needle\nmov rdi, rbp; haystack\ncall _strstr\ntest rax, rax\njz short loc_15E6\nadd r12d, 1\nmov rdi, rbx; ptr\nmovsxd rcx, r12d\nlea r13, ds:0[rcx*8]\nmov rsi, r13; size\ncall _realloc\nmov [rax+r13-8], rbp\nmov rbx, rax\nloc_15E6:\nadd r15, 8\ncmp r15, r14\njnz short loc_15B0\nloc_15EF:\nmov rax, [rsp+48h+var_40]\nmov [rax], r12d\nadd rsp, 18h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1610:\nxor r12d, r12d\nxor ebx, ebx\njmp short loc_15EF", + "ida_strip_pseudo": "void *__fastcall sub_1580(const char **a1, int a2, const char *a3, _DWORD *a4)\n{\n const char **v4; // r15\n int v5; // r12d\n void *v6; // rbx\n const char *v7; // rbp\n _QWORD *v8; // rax\n\n if ( a2 <= 0 )\n {\n v5 = 0;\n v6 = 0LL;\n }\n else\n {\n v4 = a1;\n v5 = 0;\n v6 = 0LL;\n do\n {\n v7 = *v4;\n if ( strstr(*v4, a3) )\n {\n v8 = realloc(v6, 8LL * ++v5);\n v8[v5 - 1] = v7;\n v6 = v8;\n }\n ++v4;\n }\n while ( v4 != &a1[a2] );\n }\n *a4 = v5;\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1580(const char **a1, int a2, const char *a3, uint32_t *a4) {\n const char **v4;\n int v5;\n void *v6;\n const char *v7;\n uint64_t *v8;\n if (a2 <= 0) {\n v5 = 0;\n v6 = 0LL;\n } else {\n v4 = a1;\n v5 = 0;\n v6 = 0LL;\n do {\n v7 = *v4;\n if (strstr(*v4, a3)) {\n v8 = realloc(v6, 8LL * ++v5);\n v8[v5 - 1] = v7;\n v6 = v8;\n }\n ++v4;\n } while (v4 != &a1[a2]);\n }\n *a4 = v5;\n return v6;\n}", + "ida_pseudo_norm": "void *func0(const char **a1, int a2, const char *a3, uint32_t *a4) {\n const char **v4;\n int v5;\n void *v6;\n const char *v7;\n uint64_t *v8;\n if (a2 <= 0) {\n v5 = 0;\n v6 = 0LL;\n } else {\n v4 = a1;\n v5 = 0;\n v6 = 0LL;\n do {\n v7 = *v4;\n if (strstr(*v4, a3)) {\n v8 = realloc(v6, 8LL * ++v5);\n v8[v5 - 1] = v7;\n v6 = v8;\n }\n ++v4;\n } while (v4 != &a1[a2]);\n }\n *a4 = v5;\n return v6;\n}" + }, + { + "index": "HumanEval-C-7", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char **func0(char **strings, int size, const char *substring, int *out_size) {\n char **out = NULL;\n int count = 0;\n for (int i = 0; i < size; i++) {\n if (strstr(strings[i], substring) != NULL) {\n out = (char **)realloc(out, sizeof(char *) * (count + 1));\n out[count] = strings[i];\n count++;\n }\n }\n *out_size = count;\n return out;\n}", + "test": "#include \n#include \n#include \n#include \n\nint issame(char **a, char **b, int size_a, int size_b) {\n if (size_a != size_b) return 0;\n for (int i = 0; i < size_a; i++) {\n if (strcmp(a[i], b[i]) != 0) return 0;\n }\n return 1;\n}\n\nint main() {\n int out_size;\n char **result;\n\n // First test case with empty array and substring \"john\"\n result = func0(NULL, 0, \"john\", &out_size);\n assert(out_size == 0 && result == NULL);\n\n // Second test case\n char *strings1[] = {\"xxx\", \"asd\", \"xxy\", \"john doe\", \"xxxAAA\", \"xxx\"};\n char *expected1[] = {\"xxx\", \"xxxAAA\", \"xxx\"};\n result = func0(strings1, 6, \"xxx\", &out_size);\n assert(issame(result, expected1, out_size, 3));\n free(result);\n\n // Third test case\n char *strings2[] = {\"xxx\", \"asd\", \"aaaxxy\", \"john doe\", \"xxxAAA\", \"xxx\"};\n char *expected2[] = {\"xxx\", \"aaaxxy\", \"xxxAAA\", \"xxx\"};\n result = func0(strings2, 6, \"xx\", &out_size);\n assert(issame(result, expected2, out_size, 4));\n free(result);\n\n // Fourth test case\n char *strings3[] = {\"grunt\", \"trumpet\", \"prune\", \"gruesome\"};\n char *expected3[] = {\"grunt\", \"prune\"};\n result = func0(strings3, 4, \"run\", &out_size);\n assert(issame(result, expected3, out_size, 2));\n free(result);\n \n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+needle], rdx\nmov [rsp+48h+var_40], rcx\ntest esi, esi\njle short loc_1610\nmovsxd rsi, esi\nmov r15, rdi\nxor r12d, r12d\nxor ebx, ebx\nlea r14, [rdi+rsi*8]\nxchg ax, ax\nloc_15B0:\nmov rbp, [r15]\nmov rsi, [rsp+48h+needle]; needle\nmov rdi, rbp; haystack\ncall _strstr\ntest rax, rax\njz short loc_15E6\nadd r12d, 1\nmov rdi, rbx; ptr\nmovsxd rcx, r12d\nlea r13, ds:0[rcx*8]\nmov rsi, r13; size\ncall _realloc\nmov [rax+r13-8], rbp\nmov rbx, rax\nloc_15E6:\nadd r15, 8\ncmp r15, r14\njnz short loc_15B0\nloc_15EF:\nmov rax, [rsp+48h+var_40]\nmov [rax], r12d\nadd rsp, 18h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1610:\nxor r12d, r12d\nxor ebx, ebx\njmp short loc_15EF", + "ida_pseudo": "void *__fastcall func0(const char **a1, int a2, const char *a3, _DWORD *a4)\n{\n const char **v4; // r15\n int v5; // r12d\n void *v6; // rbx\n const char *v7; // rbp\n _QWORD *v8; // rax\n\n if ( a2 <= 0 )\n {\n v5 = 0;\n v6 = 0LL;\n }\n else\n {\n v4 = a1;\n v5 = 0;\n v6 = 0LL;\n do\n {\n v7 = *v4;\n if ( strstr(*v4, a3) )\n {\n v8 = realloc(v6, 8LL * ++v5);\n v8[v5 - 1] = v7;\n v6 = v8;\n }\n ++v4;\n }\n while ( v4 != &a1[a2] );\n }\n *a4 = v5;\n return v6;\n}", + "ida_strip_asm": "sub_1580:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+needle], rdx\nmov [rsp+48h+var_40], rcx\ntest esi, esi\njle short loc_1610\nmovsxd rsi, esi\nmov r15, rdi\nxor r12d, r12d\nxor ebx, ebx\nlea r14, [rdi+rsi*8]\nxchg ax, ax\nloc_15B0:\nmov rbp, [r15]\nmov rsi, [rsp+48h+needle]; needle\nmov rdi, rbp; haystack\ncall _strstr\ntest rax, rax\njz short loc_15E6\nadd r12d, 1\nmov rdi, rbx; ptr\nmovsxd rcx, r12d\nlea r13, ds:0[rcx*8]\nmov rsi, r13; size\ncall _realloc\nmov [rax+r13-8], rbp\nmov rbx, rax\nloc_15E6:\nadd r15, 8\ncmp r15, r14\njnz short loc_15B0\nloc_15EF:\nmov rax, [rsp+48h+var_40]\nmov [rax], r12d\nadd rsp, 18h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1610:\nxor r12d, r12d\nxor ebx, ebx\njmp short loc_15EF", + "ida_strip_pseudo": "void *__fastcall sub_1580(const char **a1, int a2, const char *a3, _DWORD *a4)\n{\n const char **v4; // r15\n int v5; // r12d\n void *v6; // rbx\n const char *v7; // rbp\n _QWORD *v8; // rax\n\n if ( a2 <= 0 )\n {\n v5 = 0;\n v6 = 0LL;\n }\n else\n {\n v4 = a1;\n v5 = 0;\n v6 = 0LL;\n do\n {\n v7 = *v4;\n if ( strstr(*v4, a3) )\n {\n v8 = realloc(v6, 8LL * ++v5);\n v8[v5 - 1] = v7;\n v6 = v8;\n }\n ++v4;\n }\n while ( v4 != &a1[a2] );\n }\n *a4 = v5;\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1580(const char **a1, int a2, const char *a3, uint32_t *a4) {\n const char **v4;\n int v5;\n void *v6;\n const char *v7;\n uint64_t *v8;\n if (a2 <= 0) {\n v5 = 0;\n v6 = 0LL;\n } else {\n v4 = a1;\n v5 = 0;\n v6 = 0LL;\n do {\n v7 = *v4;\n if (strstr(*v4, a3)) {\n v8 = realloc(v6, 8LL * ++v5);\n v8[v5 - 1] = v7;\n v6 = v8;\n }\n ++v4;\n } while (v4 != &a1[a2]);\n }\n *a4 = v5;\n return v6;\n}", + "ida_pseudo_norm": "void *func0(const char **a1, int a2, const char *a3, uint32_t *a4) {\n const char **v4;\n int v5;\n void *v6;\n const char *v7;\n uint64_t *v8;\n if (a2 <= 0) {\n v5 = 0;\n v6 = 0LL;\n } else {\n v4 = a1;\n v5 = 0;\n v6 = 0LL;\n do {\n v7 = *v4;\n if (strstr(*v4, a3)) {\n v8 = realloc(v6, 8LL * ++v5);\n v8[v5 - 1] = v7;\n v6 = v8;\n }\n ++v4;\n } while (v4 != &a1[a2]);\n }\n *a4 = v5;\n return v6;\n}" + }, + { + "index": "HumanEval-C-8", + "func_name": "func0", + "func_dep": "#include \n", + "func": "void func0(int *numbers, int size, int *result) {\n int sum = 0, product = 1;\n for (int i = 0; i < size; i++) {\n sum += numbers[i];\n product *= numbers[i];\n }\n result[0] = sum;\n result[1] = product;\n}", + "test": "#include \n\nint issame(const int *a, const int *b, int size) {\n for (int i = 0; i < size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int result[2];\n\n // First test case\n func0((const int[]){}, 0, result);\n assert(issame(result, (const int[]){0, 1}, 2));\n\n // Second test case\n func0((const int[]){1, 1, 1}, 3, result);\n assert(issame(result, (const int[]){3, 1}, 2));\n\n // Third test case\n func0((const int[]){100, 0}, 2, result);\n assert(issame(result, (const int[]){100, 0}, 2));\n\n // Fourth test case\n func0((const int[]){3, 5, 7}, 3, result);\n assert(issame(result, (const int[]){3 + 5 + 7, 3 * 5 * 7}, 2));\n\n // Fifth test case\n func0((const int[]){10}, 1, result);\n assert(issame(result, (const int[]){10, 10}, 2));\n \n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_C], 0\nmov [rbp+var_8], 1\nmov [rbp+var_4], 0\njmp short loc_11CF\nloc_1193:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_C], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_8]\nimul eax, edx\nmov [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_11CF:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1193\nmov rax, [rbp+var_28]\nmov edx, [rbp+var_C]\nmov [rax], edx\nmov rax, [rbp+var_28]\nlea rdx, [rax+4]\nmov eax, [rbp+var_8]\nmov [rdx], eax\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, _DWORD *a3)\n{\n __int64 result; // rax\n int v4; // [rsp+1Ch] [rbp-Ch]\n unsigned int v5; // [rsp+20h] [rbp-8h]\n int i; // [rsp+24h] [rbp-4h]\n\n v4 = 0;\n v5 = 1;\n for ( i = 0; i < a2; ++i )\n {\n v4 += *(_DWORD *)(4LL * i + a1);\n v5 *= *(_DWORD *)(4LL * i + a1);\n }\n *a3 = v4;\n result = v5;\n a3[1] = v5;\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_C], 0\nmov [rbp+var_8], 1\nmov [rbp+var_4], 0\njmp short loc_11CF\nloc_1193:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_C], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_8]\nimul eax, edx\nmov [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_11CF:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1193\nmov rax, [rbp+var_28]\nmov edx, [rbp+var_C]\nmov [rax], edx\nmov rax, [rbp+var_28]\nlea rdx, [rax+4]\nmov eax, [rbp+var_8]\nmov [rdx], eax\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, _DWORD *a3)\n{\n __int64 result; // rax\n int v4; // [rsp+1Ch] [rbp-Ch]\n unsigned int v5; // [rsp+20h] [rbp-8h]\n int i; // [rsp+24h] [rbp-4h]\n\n v4 = 0;\n v5 = 1;\n for ( i = 0; i < a2; ++i )\n {\n v4 += *(_DWORD *)(4LL * i + a1);\n v5 *= *(_DWORD *)(4LL * i + a1);\n }\n *a3 = v4;\n result = v5;\n a3[1] = v5;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, uint32_t *a3) {\n long long result;\n int v4;\n unsigned int v5;\n int i;\n v4 = 0;\n v5 = 1;\n for (i = 0; i < a2; ++i) {\n v4 += *(uint32_t *)(4LL * i + a1);\n v5 *= *(uint32_t *)(4LL * i + a1);\n }\n *a3 = v4;\n result = v5;\n a3[1] = v5;\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, uint32_t *a3) {\n long long result;\n int v4;\n unsigned int v5;\n int i;\n v4 = 0;\n v5 = 1;\n for (i = 0; i < a2; ++i) {\n v4 += *(uint32_t *)(4LL * i + a1);\n v5 *= *(uint32_t *)(4LL * i + a1);\n }\n *a3 = v4;\n result = v5;\n a3[1] = v5;\n return result;\n}" + }, + { + "index": "HumanEval-C-8", + "func_name": "func0", + "func_dep": "#include \n", + "func": "void func0(int *numbers, int size, int *result) {\n int sum = 0, product = 1;\n for (int i = 0; i < size; i++) {\n sum += numbers[i];\n product *= numbers[i];\n }\n result[0] = sum;\n result[1] = product;\n}", + "test": "#include \n\nint issame(const int *a, const int *b, int size) {\n for (int i = 0; i < size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int result[2];\n\n // First test case\n func0((const int[]){}, 0, result);\n assert(issame(result, (const int[]){0, 1}, 2));\n\n // Second test case\n func0((const int[]){1, 1, 1}, 3, result);\n assert(issame(result, (const int[]){3, 1}, 2));\n\n // Third test case\n func0((const int[]){100, 0}, 2, result);\n assert(issame(result, (const int[]){100, 0}, 2));\n\n // Fourth test case\n func0((const int[]){3, 5, 7}, 3, result);\n assert(issame(result, (const int[]){3 + 5 + 7, 3 * 5 * 7}, 2));\n\n // Fifth test case\n func0((const int[]){10}, 1, result);\n assert(issame(result, (const int[]){10, 10}, 2));\n \n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_119B\nmov rax, rdi\nmovsxd rsi, esi\nlea r8, [rdi+rsi*4]\nmov esi, 1\nmov edi, 0\nloc_1185:\nmov ecx, [rax]\nadd edi, ecx\nimul esi, ecx\nadd rax, 4\ncmp rax, r8\njnz short loc_1185\nloc_1195:\nmov [rdx], edi\nmov [rdx+4], esi\nretn\nloc_119B:\nmov esi, 1\nmov edi, 0\njmp short loc_1195", + "ida_pseudo": "void __fastcall func0(_DWORD *a1, int a2, _DWORD *a3)\n{\n _DWORD *v3; // rax\n _DWORD *v4; // r8\n int v5; // esi\n int v6; // edi\n\n if ( a2 <= 0 )\n {\n v5 = 1;\n v6 = 0;\n }\n else\n {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 1;\n v6 = 0;\n do\n {\n v6 += *v3;\n v5 *= *v3++;\n }\n while ( v3 != v4 );\n }\n *a3 = v6;\n a3[1] = v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_119B\nmov rax, rdi\nmovsxd rsi, esi\nlea r8, [rdi+rsi*4]\nmov esi, 1\nmov edi, 0\nloc_1185:\nmov ecx, [rax]\nadd edi, ecx\nimul esi, ecx\nadd rax, 4\ncmp rax, r8\njnz short loc_1185\nloc_1195:\nmov [rdx], edi\nmov [rdx+4], esi\nretn\nloc_119B:\nmov esi, 1\nmov edi, 0\njmp short loc_1195", + "ida_strip_pseudo": "void __fastcall sub_1169(_DWORD *a1, int a2, _DWORD *a3)\n{\n _DWORD *v3; // rax\n _DWORD *v4; // r8\n int v5; // esi\n int v6; // edi\n\n if ( a2 <= 0 )\n {\n v5 = 1;\n v6 = 0;\n }\n else\n {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 1;\n v6 = 0;\n do\n {\n v6 += *v3;\n v5 *= *v3++;\n }\n while ( v3 != v4 );\n }\n *a3 = v6;\n a3[1] = v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1169(uint32_t *a1, int a2, uint32_t *a3) {\n uint32_t *v3;\n uint32_t *v4;\n int v5;\n int v6;\n if (a2 <= 0) {\n v5 = 1;\n v6 = 0;\n } else {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 1;\n v6 = 0;\n do {\n v6 += *v3;\n v5 *= *v3++;\n } while (v3 != v4);\n }\n *a3 = v6;\n a3[1] = v5;\n}", + "ida_pseudo_norm": "void func0(uint32_t *a1, int a2, uint32_t *a3) {\n uint32_t *v3;\n uint32_t *v4;\n int v5;\n int v6;\n if (a2 <= 0) {\n v5 = 1;\n v6 = 0;\n } else {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 1;\n v6 = 0;\n do {\n v6 += *v3;\n v5 *= *v3++;\n } while (v3 != v4);\n }\n *a3 = v6;\n a3[1] = v5;\n}" + }, + { + "index": "HumanEval-C-9", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int *func0(int *numbers, int size) {\n if (size <= 0) {\n return NULL;\n }\n int *out = malloc(size * sizeof(int));\n if (!out) {\n return NULL;\n }\n int max = numbers[0];\n for (int i = 0; i < size; i++) {\n if (numbers[i] > max) max = numbers[i];\n out[i] = max;\n }\n return out;\n}", + "test": "#include \n#include \n#include \n\nint issame(int *a, int *b, int size) {\n for (int i = 0; i < size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int *result;\n\n // First test case\n result = func0((const int[]){}, 0);\n assert(result == NULL);\n free(result);\n\n // Second test case\n int test1[] = {1, 2, 3, 4};\n result = func0(test1, 4);\n assert(issame(result, (const int[]){1, 2, 3, 4}, 4));\n free(result);\n\n // Third test case\n int test2[] = {4, 3, 2, 1};\n result = func0(test2, 4);\n assert(issame(result, (const int[]){4, 4, 4, 4}, 4));\n free(result);\n\n // Fourth test case\n int test3[] = {3, 2, 3, 100, 3};\n result = func0(test3, 5);\n assert(issame(result, (const int[]){3, 3, 3, 100, 100}, 5));\n free(result);\n \n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\ncmp [rbp+var_1C], 0\njg short loc_11CC\nmov eax, 0\njmp locret_125E\nloc_11CC:\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\ncmp [rbp+var_8], 0\njnz short loc_11EF\nmov eax, 0\njmp short locret_125E\nloc_11EF:\nmov rax, [rbp+var_18]\nmov eax, [rax]\nmov [rbp+var_10], eax\nmov [rbp+var_C], 0\njmp short loc_1252\nloc_1201:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_10], eax\njge short loc_1235\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_10], eax\nloc_1235:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_10]\nmov [rdx], eax\nadd [rbp+var_C], 1\nloc_1252:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_1201\nmov rax, [rbp+var_8]\nlocret_125E:\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2)\n{\n int v3; // [rsp+10h] [rbp-10h]\n int i; // [rsp+14h] [rbp-Ch]\n _DWORD *v5; // [rsp+18h] [rbp-8h]\n\n if ( a2 <= 0 )\n return 0LL;\n v5 = malloc(4LL * a2);\n if ( !v5 )\n return 0LL;\n v3 = *a1;\n for ( i = 0; i < a2; ++i )\n {\n if ( v3 < a1[i] )\n v3 = a1[i];\n v5[i] = v3;\n }\n return v5;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\ncmp [rbp+var_1C], 0\njg short loc_11CC\nmov eax, 0\njmp locret_125E\nloc_11CC:\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\ncmp [rbp+var_8], 0\njnz short loc_11EF\nmov eax, 0\njmp short locret_125E\nloc_11EF:\nmov rax, [rbp+var_18]\nmov eax, [rax]\nmov [rbp+var_10], eax\nmov [rbp+var_C], 0\njmp short loc_1252\nloc_1201:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_10], eax\njge short loc_1235\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_10], eax\nloc_1235:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_10]\nmov [rdx], eax\nadd [rbp+var_C], 1\nloc_1252:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_1201\nmov rax, [rbp+var_8]\nlocret_125E:\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(int *a1, int a2)\n{\n int v3; // [rsp+10h] [rbp-10h]\n int i; // [rsp+14h] [rbp-Ch]\n _DWORD *v5; // [rsp+18h] [rbp-8h]\n\n if ( a2 <= 0 )\n return 0LL;\n v5 = malloc(4LL * a2);\n if ( !v5 )\n return 0LL;\n v3 = *a1;\n for ( i = 0; i < a2; ++i )\n {\n if ( v3 < a1[i] )\n v3 = a1[i];\n v5[i] = v3;\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(int *a1, int a2) {\n int v3;\n int i;\n uint32_t *v5;\n if (a2 <= 0) return 0LL;\n v5 = malloc(4LL * a2);\n if (!v5) return 0LL;\n v3 = *a1;\n for (i = 0; i < a2; ++i) {\n if (v3 < a1[i]) v3 = a1[i];\n v5[i] = v3;\n }\n return v5;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2) {\n int v3;\n int i;\n uint32_t *v5;\n if (a2 <= 0) return 0LL;\n v5 = malloc(4LL * a2);\n if (!v5) return 0LL;\n v3 = *a1;\n for (i = 0; i < a2; ++i) {\n if (v3 < a1[i]) v3 = a1[i];\n v5[i] = v3;\n }\n return v5;\n}" + }, + { + "index": "HumanEval-C-9", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int *func0(int *numbers, int size) {\n if (size <= 0) {\n return NULL;\n }\n int *out = malloc(size * sizeof(int));\n if (!out) {\n return NULL;\n }\n int max = numbers[0];\n for (int i = 0; i < size; i++) {\n if (numbers[i] > max) max = numbers[i];\n out[i] = max;\n }\n return out;\n}", + "test": "#include \n#include \n#include \n\nint issame(int *a, int *b, int size) {\n for (int i = 0; i < size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int *result;\n\n // First test case\n result = func0((const int[]){}, 0);\n assert(result == NULL);\n free(result);\n\n // Second test case\n int test1[] = {1, 2, 3, 4};\n result = func0(test1, 4);\n assert(issame(result, (const int[]){1, 2, 3, 4}, 4));\n free(result);\n\n // Third test case\n int test2[] = {4, 3, 2, 1};\n result = func0(test2, 4);\n assert(issame(result, (const int[]){4, 4, 4, 4}, 4));\n free(result);\n\n // Fourth test case\n int test3[] = {3, 2, 3, 100, 3};\n result = func0(test3, 5);\n assert(issame(result, (const int[]){3, 3, 3, 100, 100}, 5));\n free(result);\n \n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmov eax, 0\ntest esi, esi\njle short locret_11FB\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmovsxd rsi, esi\nlea rbx, ds:0[rsi*4]\nmov rdi, rbx; size\ncall _malloc\ntest rax, rax\njz short loc_11F4\nmov ecx, [rbp+0]\nmov edx, 0\nloc_11DF:\nmov esi, [rbp+rdx+0]\ncmp ecx, esi\ncmovl ecx, esi\nmov [rax+rdx], ecx\nadd rdx, 4\ncmp rbx, rdx\njnz short loc_11DF\nloc_11F4:\nadd rsp, 8\npop rbx\npop rbp\nretn\nlocret_11FB:\nretn", + "ida_pseudo": "char *__fastcall func0(int *a1, int a2)\n{\n char *result; // rax\n int v3; // ecx\n __int64 i; // rdx\n\n result = 0LL;\n if ( a2 > 0 )\n {\n result = (char *)malloc(4LL * a2);\n if ( result )\n {\n v3 = *a1;\n for ( i = 0LL; i != a2; ++i )\n {\n if ( v3 < a1[i] )\n v3 = a1[i];\n *(_DWORD *)&result[i * 4] = v3;\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\nmov eax, 0\ntest esi, esi\njle short locret_11FB\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmovsxd rsi, esi\nlea rbx, ds:0[rsi*4]\nmov rdi, rbx; size\ncall _malloc\ntest rax, rax\njz short loc_11F4\nmov ecx, [rbp+0]\nmov edx, 0\nloc_11DF:\nmov esi, [rbp+rdx+0]\ncmp ecx, esi\ncmovl ecx, esi\nmov [rax+rdx], ecx\nadd rdx, 4\ncmp rbx, rdx\njnz short loc_11DF\nloc_11F4:\nadd rsp, 8\npop rbx\npop rbp\nretn\nlocret_11FB:\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11A9(int *a1, int a2)\n{\n char *result; // rax\n int v3; // ecx\n __int64 i; // rdx\n\n result = 0LL;\n if ( a2 > 0 )\n {\n result = (char *)malloc(4LL * a2);\n if ( result )\n {\n v3 = *a1;\n for ( i = 0LL; i != a2; ++i )\n {\n if ( v3 < a1[i] )\n v3 = a1[i];\n *(_DWORD *)&result[i * 4] = v3;\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11A9(int *a1, int a2) {\n char *result;\n int v3;\n long long i;\n result = 0LL;\n if (a2 > 0) {\n result = (char *)malloc(4LL * a2);\n if (result) {\n v3 = *a1;\n for (i = 0LL; i != a2; ++i) {\n if (v3 < a1[i]) v3 = a1[i];\n *(uint32_t *)&result[i * 4] = v3;\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(int *a1, int a2) {\n char *result;\n int v3;\n long long i;\n result = 0LL;\n if (a2 > 0) {\n result = (char *)malloc(4LL * a2);\n if (result) {\n v3 = *a1;\n for (i = 0LL; i != a2; ++i) {\n if (v3 < a1[i]) v3 = a1[i];\n *(uint32_t *)&result[i * 4] = v3;\n }\n }\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-9", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int *func0(int *numbers, int size) {\n if (size <= 0) {\n return NULL;\n }\n int *out = malloc(size * sizeof(int));\n if (!out) {\n return NULL;\n }\n int max = numbers[0];\n for (int i = 0; i < size; i++) {\n if (numbers[i] > max) max = numbers[i];\n out[i] = max;\n }\n return out;\n}", + "test": "#include \n#include \n#include \n\nint issame(int *a, int *b, int size) {\n for (int i = 0; i < size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int *result;\n\n // First test case\n result = func0((const int[]){}, 0);\n assert(result == NULL);\n free(result);\n\n // Second test case\n int test1[] = {1, 2, 3, 4};\n result = func0(test1, 4);\n assert(issame(result, (const int[]){1, 2, 3, 4}, 4));\n free(result);\n\n // Third test case\n int test2[] = {4, 3, 2, 1};\n result = func0(test2, 4);\n assert(issame(result, (const int[]){4, 4, 4, 4}, 4));\n free(result);\n\n // Fourth test case\n int test3[] = {3, 2, 3, 100, 3};\n result = func0(test3, 5);\n assert(issame(result, (const int[]){3, 3, 3, 100, 100}, 5));\n free(result);\n \n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_13A8\npush rbp\nmovsxd rsi, esi\nmov rbp, rdi\npush rbx\nlea rbx, ds:0[rsi*4]\nmov rdi, rbx; size\nsub rsp, 8\ncall _malloc\ntest rax, rax\njz short loc_139C\nmov ecx, [rbp+0]\nxor edx, edx\nxchg ax, ax\nloc_1380:\nmov esi, [rbp+rdx+0]\ncmp ecx, esi\ncmovl ecx, esi\nmov [rax+rdx], ecx\nadd rdx, 4\ncmp rbx, rdx\njnz short loc_1380\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_139C:\nadd rsp, 8\nxor eax, eax\npop rbx\npop rbp\nretn\nloc_13A8:\nxor eax, eax\nretn", + "ida_pseudo": "char *__fastcall func0(int *a1, int a2)\n{\n char *result; // rax\n int v3; // ecx\n __int64 i; // rdx\n\n if ( a2 <= 0 )\n return 0LL;\n result = (char *)malloc(4LL * a2);\n if ( !result )\n return 0LL;\n v3 = *a1;\n for ( i = 0LL; i != a2; ++i )\n {\n if ( v3 < a1[i] )\n v3 = a1[i];\n *(_DWORD *)&result[i * 4] = v3;\n }\n return result;\n}", + "ida_strip_asm": "sub_1350:\nendbr64\ntest esi, esi\njle short loc_13A8\npush rbp\nmovsxd rsi, esi\nmov rbp, rdi\npush rbx\nlea rbx, ds:0[rsi*4]\nmov rdi, rbx; size\nsub rsp, 8\ncall _malloc\ntest rax, rax\njz short loc_139C\nmov ecx, [rbp+0]\nxor edx, edx\nxchg ax, ax\nloc_1380:\nmov esi, [rbp+rdx+0]\ncmp ecx, esi\ncmovl ecx, esi\nmov [rax+rdx], ecx\nadd rdx, 4\ncmp rbx, rdx\njnz short loc_1380\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_139C:\nadd rsp, 8\nxor eax, eax\npop rbx\npop rbp\nretn\nloc_13A8:\nxor eax, eax\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1350(int *a1, int a2)\n{\n char *result; // rax\n int v3; // ecx\n __int64 i; // rdx\n\n if ( a2 <= 0 )\n return 0LL;\n result = (char *)malloc(4LL * a2);\n if ( !result )\n return 0LL;\n v3 = *a1;\n for ( i = 0LL; i != a2; ++i )\n {\n if ( v3 < a1[i] )\n v3 = a1[i];\n *(_DWORD *)&result[i * 4] = v3;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1350(int *a1, int a2) {\n char *result;\n int v3;\n long long i;\n if (a2 <= 0) return 0LL;\n result = (char *)malloc(4LL * a2);\n if (!result) return 0LL;\n v3 = *a1;\n for (i = 0LL; i != a2; ++i) {\n if (v3 < a1[i]) v3 = a1[i];\n *(uint32_t *)&result[i * 4] = v3;\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(int *a1, int a2) {\n char *result;\n int v3;\n long long i;\n if (a2 <= 0) return 0LL;\n result = (char *)malloc(4LL * a2);\n if (!result) return 0LL;\n v3 = *a1;\n for (i = 0LL; i != a2; ++i) {\n if (v3 < a1[i]) v3 = a1[i];\n *(uint32_t *)&result[i * 4] = v3;\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-9", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int *func0(int *numbers, int size) {\n if (size <= 0) {\n return NULL;\n }\n int *out = malloc(size * sizeof(int));\n if (!out) {\n return NULL;\n }\n int max = numbers[0];\n for (int i = 0; i < size; i++) {\n if (numbers[i] > max) max = numbers[i];\n out[i] = max;\n }\n return out;\n}", + "test": "#include \n#include \n#include \n\nint issame(int *a, int *b, int size) {\n for (int i = 0; i < size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int *result;\n\n // First test case\n result = func0((const int[]){}, 0);\n assert(result == NULL);\n free(result);\n\n // Second test case\n int test1[] = {1, 2, 3, 4};\n result = func0(test1, 4);\n assert(issame(result, (const int[]){1, 2, 3, 4}, 4));\n free(result);\n\n // Third test case\n int test2[] = {4, 3, 2, 1};\n result = func0(test2, 4);\n assert(issame(result, (const int[]){4, 4, 4, 4}, 4));\n free(result);\n\n // Fourth test case\n int test3[] = {3, 2, 3, 100, 3};\n result = func0(test3, 5);\n assert(issame(result, (const int[]){3, 3, 3, 100, 100}, 5));\n free(result);\n \n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1378\npush rbp\nmovsxd rsi, esi\nmov rbp, rdi\npush rbx\nlea rbx, ds:0[rsi*4]\nmov rdi, rbx; size\nsub rsp, 8\ncall _malloc\ntest rax, rax\njz short loc_136C\nmov ecx, [rbp+0]\nxor edx, edx\nxchg ax, ax\nloc_1350:\nmov esi, [rbp+rdx+0]\ncmp ecx, esi\ncmovl ecx, esi\nmov [rax+rdx], ecx\nadd rdx, 4\ncmp rbx, rdx\njnz short loc_1350\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_136C:\nadd rsp, 8\nxor eax, eax\npop rbx\npop rbp\nretn\nloc_1378:\nxor eax, eax\nretn", + "ida_pseudo": "char *__fastcall func0(int *a1, int a2)\n{\n char *result; // rax\n int v3; // ecx\n __int64 i; // rdx\n\n if ( a2 <= 0 )\n return 0LL;\n result = (char *)malloc(4LL * a2);\n if ( !result )\n return 0LL;\n v3 = *a1;\n for ( i = 0LL; i != a2; ++i )\n {\n if ( v3 < a1[i] )\n v3 = a1[i];\n *(_DWORD *)&result[i * 4] = v3;\n }\n return result;\n}", + "ida_strip_asm": "sub_1320:\nendbr64\ntest esi, esi\njle short loc_1378\npush rbp\nmovsxd rsi, esi\nmov rbp, rdi\npush rbx\nlea rbx, ds:0[rsi*4]\nmov rdi, rbx; size\nsub rsp, 8\ncall _malloc\ntest rax, rax\njz short loc_136C\nmov ecx, [rbp+0]\nxor edx, edx\nxchg ax, ax\nloc_1350:\nmov esi, [rbp+rdx+0]\ncmp ecx, esi\ncmovl ecx, esi\nmov [rax+rdx], ecx\nadd rdx, 4\ncmp rbx, rdx\njnz short loc_1350\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_136C:\nadd rsp, 8\nxor eax, eax\npop rbx\npop rbp\nretn\nloc_1378:\nxor eax, eax\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1320(int *a1, int a2)\n{\n char *result; // rax\n int v3; // ecx\n __int64 i; // rdx\n\n if ( a2 <= 0 )\n return 0LL;\n result = (char *)malloc(4LL * a2);\n if ( !result )\n return 0LL;\n v3 = *a1;\n for ( i = 0LL; i != a2; ++i )\n {\n if ( v3 < a1[i] )\n v3 = a1[i];\n *(_DWORD *)&result[i * 4] = v3;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1320(int *a1, int a2) {\n char *result;\n int v3;\n long long i;\n if (a2 <= 0) return 0LL;\n result = (char *)malloc(4LL * a2);\n if (!result) return 0LL;\n v3 = *a1;\n for (i = 0LL; i != a2; ++i) {\n if (v3 < a1[i]) v3 = a1[i];\n *(uint32_t *)&result[i * 4] = v3;\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(int *a1, int a2) {\n char *result;\n int v3;\n long long i;\n if (a2 <= 0) return 0LL;\n result = (char *)malloc(4LL * a2);\n if (!result) return 0LL;\n v3 = *a1;\n for (i = 0LL; i != a2; ++i) {\n if (v3 < a1[i]) v3 = a1[i];\n *(uint32_t *)&result[i * 4] = v3;\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-10", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char *func0(const char *str) {\n int len = strlen(str), i, j;\n char *result = (char *)malloc(2 * len + 1);\n if (!result) {\n return NULL;\n }\n for (i = 0; i < len; i++) {\n int is_palindrome = 1;\n for (j = 0; j < (len - i) / 2; j++) {\n if (str[i + j] != str[len - 1 - j]) {\n is_palindrome = 0;\n break;\n }\n }\n if (is_palindrome) {\n strncpy(result, str, len);\n for (j = 0; j < i; j++) {\n result[len + j] = str[i - j - 1];\n }\n result[len + i] = '\\0';\n return result;\n }\n }\n strncpy(result, str, len);\n for (j = 0; j < len; j++) {\n result[len + j] = str[len - j - 1];\n }\n result[2 * len] = '\\0';\n return result;\n}", + "test": "#include \n#include \n\nint main() {\n char *palindrome;\n\n // First test case\n palindrome = func0(\"\");\n assert(strcmp(palindrome, \"\") == 0);\n free(palindrome);\n\n // Second test case\n palindrome = func0(\"x\");\n assert(strcmp(palindrome, \"x\") == 0);\n free(palindrome);\n\n // Third test case\n palindrome = func0(\"xyz\");\n assert(strcmp(palindrome, \"xyzyx\") == 0);\n free(palindrome);\n\n // Fourth test case\n palindrome = func0(\"xyx\");\n assert(strcmp(palindrome, \"xyx\") == 0);\n free(palindrome);\n\n // Fifth test case\n palindrome = func0(\"jerry\");\n assert(strcmp(palindrome, \"jerryrrej\") == 0);\n free(palindrome);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_C], eax\nmov eax, [rbp+var_C]\nadd eax, eax\nadd eax, 1\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+dest], rax\ncmp [rbp+dest], 0\njnz short loc_122F\nmov eax, 0\njmp locret_1392\nloc_122F:\nmov [rbp+var_18], 0\njmp loc_1318\nloc_123B:\nmov [rbp+var_10], 1\nmov [rbp+var_14], 0\njmp short loc_1287\nloc_124B:\nmov edx, [rbp+var_18]\nmov eax, [rbp+var_14]\nadd eax, edx\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_C]\nsub eax, 1\nsub eax, [rbp+var_14]\nmovsxd rcx, eax\nmov rax, [rbp+s]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njz short loc_1283\nmov [rbp+var_10], 0\njmp short loc_129B\nloc_1283:\nadd [rbp+var_14], 1\nloc_1287:\nmov eax, [rbp+var_C]\nsub eax, [rbp+var_18]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\ncmp [rbp+var_14], eax\njl short loc_124B\nloc_129B:\ncmp [rbp+var_10], 0\njz short loc_1314\nmov eax, [rbp+var_C]\nmovsxd rdx, eax; n\nmov rcx, [rbp+s]\nmov rax, [rbp+dest]\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strncpy\nmov [rbp+var_14], 0\njmp short loc_12F1\nloc_12C3:\nmov eax, [rbp+var_18]\nsub eax, [rbp+var_14]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rdx\nmov ecx, [rbp+var_C]\nmov edx, [rbp+var_14]\nadd edx, ecx\nmovsxd rcx, edx\nmov rdx, [rbp+dest]\nadd rdx, rcx\nmovzx eax, byte ptr [rax]\nmov [rdx], al\nadd [rbp+var_14], 1\nloc_12F1:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_18]\njl short loc_12C3\nmov edx, [rbp+var_C]\nmov eax, [rbp+var_18]\nadd eax, edx\nmovsxd rdx, eax\nmov rax, [rbp+dest]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+dest]\njmp short locret_1392\nloc_1314:\nadd [rbp+var_18], 1\nloc_1318:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_C]\njl loc_123B\nmov eax, [rbp+var_C]\nmovsxd rdx, eax; n\nmov rcx, [rbp+s]\nmov rax, [rbp+dest]\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strncpy\nmov [rbp+var_14], 0\njmp short loc_1374\nloc_1346:\nmov eax, [rbp+var_C]\nsub eax, [rbp+var_14]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rdx\nmov ecx, [rbp+var_C]\nmov edx, [rbp+var_14]\nadd edx, ecx\nmovsxd rcx, edx\nmov rdx, [rbp+dest]\nadd rdx, rcx\nmovzx eax, byte ptr [rax]\nmov [rdx], al\nadd [rbp+var_14], 1\nloc_1374:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_C]\njl short loc_1346\nmov eax, [rbp+var_C]\nadd eax, eax\nmovsxd rdx, eax\nmov rax, [rbp+dest]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+dest]\nlocret_1392:\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(const char *a1)\n{\n int i; // [rsp+18h] [rbp-18h]\n int k; // [rsp+1Ch] [rbp-14h]\n int m; // [rsp+1Ch] [rbp-14h]\n int j; // [rsp+1Ch] [rbp-14h]\n int v6; // [rsp+20h] [rbp-10h]\n int v7; // [rsp+24h] [rbp-Ch]\n char *dest; // [rsp+28h] [rbp-8h]\n\n v7 = strlen(a1);\n dest = (char *)malloc(2 * v7 + 1);\n if ( !dest )\n return 0LL;\n for ( i = 0; ; ++i )\n {\n if ( i >= v7 )\n {\n strncpy(dest, a1, v7);\n for ( j = 0; j < v7; ++j )\n dest[v7 + j] = a1[v7 - j - 1];\n dest[2 * v7] = 0;\n return dest;\n }\n v6 = 1;\n for ( k = 0; k < (v7 - i) / 2; ++k )\n {\n if ( a1[i + k] != a1[v7 - 1 - k] )\n {\n v6 = 0;\n break;\n }\n }\n if ( v6 )\n break;\n }\n strncpy(dest, a1, v7);\n for ( m = 0; m < i; ++m )\n dest[v7 + m] = a1[i - m - 1];\n dest[v7 + i] = 0;\n return dest;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_C], eax\nmov eax, [rbp+var_C]\nadd eax, eax\nadd eax, 1\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+dest], rax\ncmp [rbp+dest], 0\njnz short loc_122F\nmov eax, 0\njmp locret_1392\nloc_122F:\nmov [rbp+var_18], 0\njmp loc_1318\nloc_123B:\nmov [rbp+var_10], 1\nmov [rbp+var_14], 0\njmp short loc_1287\nloc_124B:\nmov edx, [rbp+var_18]\nmov eax, [rbp+var_14]\nadd eax, edx\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_C]\nsub eax, 1\nsub eax, [rbp+var_14]\nmovsxd rcx, eax\nmov rax, [rbp+s]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njz short loc_1283\nmov [rbp+var_10], 0\njmp short loc_129B\nloc_1283:\nadd [rbp+var_14], 1\nloc_1287:\nmov eax, [rbp+var_C]\nsub eax, [rbp+var_18]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\ncmp [rbp+var_14], eax\njl short loc_124B\nloc_129B:\ncmp [rbp+var_10], 0\njz short loc_1314\nmov eax, [rbp+var_C]\nmovsxd rdx, eax; n\nmov rcx, [rbp+s]\nmov rax, [rbp+dest]\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strncpy\nmov [rbp+var_14], 0\njmp short loc_12F1\nloc_12C3:\nmov eax, [rbp+var_18]\nsub eax, [rbp+var_14]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rdx\nmov ecx, [rbp+var_C]\nmov edx, [rbp+var_14]\nadd edx, ecx\nmovsxd rcx, edx\nmov rdx, [rbp+dest]\nadd rdx, rcx\nmovzx eax, byte ptr [rax]\nmov [rdx], al\nadd [rbp+var_14], 1\nloc_12F1:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_18]\njl short loc_12C3\nmov edx, [rbp+var_C]\nmov eax, [rbp+var_18]\nadd eax, edx\nmovsxd rdx, eax\nmov rax, [rbp+dest]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+dest]\njmp short locret_1392\nloc_1314:\nadd [rbp+var_18], 1\nloc_1318:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_C]\njl loc_123B\nmov eax, [rbp+var_C]\nmovsxd rdx, eax; n\nmov rcx, [rbp+s]\nmov rax, [rbp+dest]\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strncpy\nmov [rbp+var_14], 0\njmp short loc_1374\nloc_1346:\nmov eax, [rbp+var_C]\nsub eax, [rbp+var_14]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rdx\nmov ecx, [rbp+var_C]\nmov edx, [rbp+var_14]\nadd edx, ecx\nmovsxd rcx, edx\nmov rdx, [rbp+dest]\nadd rdx, rcx\nmovzx eax, byte ptr [rax]\nmov [rdx], al\nadd [rbp+var_14], 1\nloc_1374:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_C]\njl short loc_1346\nmov eax, [rbp+var_C]\nadd eax, eax\nmovsxd rdx, eax\nmov rax, [rbp+dest]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+dest]\nlocret_1392:\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11E9(const char *a1)\n{\n int i; // [rsp+18h] [rbp-18h]\n int k; // [rsp+1Ch] [rbp-14h]\n int m; // [rsp+1Ch] [rbp-14h]\n int j; // [rsp+1Ch] [rbp-14h]\n int v6; // [rsp+20h] [rbp-10h]\n int v7; // [rsp+24h] [rbp-Ch]\n char *dest; // [rsp+28h] [rbp-8h]\n\n v7 = strlen(a1);\n dest = (char *)malloc(2 * v7 + 1);\n if ( !dest )\n return 0LL;\n for ( i = 0; ; ++i )\n {\n if ( i >= v7 )\n {\n strncpy(dest, a1, v7);\n for ( j = 0; j < v7; ++j )\n dest[v7 + j] = a1[v7 - j - 1];\n dest[2 * v7] = 0;\n return dest;\n }\n v6 = 1;\n for ( k = 0; k < (v7 - i) / 2; ++k )\n {\n if ( a1[i + k] != a1[v7 - 1 - k] )\n {\n v6 = 0;\n break;\n }\n }\n if ( v6 )\n break;\n }\n strncpy(dest, a1, v7);\n for ( m = 0; m < i; ++m )\n dest[v7 + m] = a1[i - m - 1];\n dest[v7 + i] = 0;\n return dest;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11E9(const char *a1) {\n int i;\n int k;\n int m;\n int j;\n int v6;\n int v7;\n char *dest;\n v7 = strlen(a1);\n dest = (char *)malloc(2 * v7 + 1);\n if (!dest) return 0LL;\n for (i = 0;; ++i) {\n if (i >= v7) {\n strncpy(dest, a1, v7);\n for (j = 0; j < v7; ++j) dest[v7 + j] = a1[v7 - j - 1];\n dest[2 * v7] = 0;\n return dest;\n }\n v6 = 1;\n for (k = 0; k < (v7 - i) / 2; ++k) {\n if (a1[i + k] != a1[v7 - 1 - k]) {\n v6 = 0;\n break;\n }\n }\n if (v6) break;\n }\n strncpy(dest, a1, v7);\n for (m = 0; m < i; ++m) dest[v7 + m] = a1[i - m - 1];\n dest[v7 + i] = 0;\n return dest;\n}", + "ida_pseudo_norm": "char *func0(const char *a1) {\n int i;\n int k;\n int m;\n int j;\n int v6;\n int v7;\n char *dest;\n v7 = strlen(a1);\n dest = (char *)malloc(2 * v7 + 1);\n if (!dest) return 0LL;\n for (i = 0;; ++i) {\n if (i >= v7) {\n strncpy(dest, a1, v7);\n for (j = 0; j < v7; ++j) dest[v7 + j] = a1[v7 - j - 1];\n dest[2 * v7] = 0;\n return dest;\n }\n v6 = 1;\n for (k = 0; k < (v7 - i) / 2; ++k) {\n if (a1[i + k] != a1[v7 - 1 - k]) {\n v6 = 0;\n break;\n }\n }\n if (v6) break;\n }\n strncpy(dest, a1, v7);\n for (m = 0; m < i; ++m) dest[v7 + m] = a1[i - m - 1];\n dest[v7 + i] = 0;\n return dest;\n}" + }, + { + "index": "HumanEval-C-10", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char *func0(const char *str) {\n int len = strlen(str), i, j;\n char *result = (char *)malloc(2 * len + 1);\n if (!result) {\n return NULL;\n }\n for (i = 0; i < len; i++) {\n int is_palindrome = 1;\n for (j = 0; j < (len - i) / 2; j++) {\n if (str[i + j] != str[len - 1 - j]) {\n is_palindrome = 0;\n break;\n }\n }\n if (is_palindrome) {\n strncpy(result, str, len);\n for (j = 0; j < i; j++) {\n result[len + j] = str[i - j - 1];\n }\n result[len + i] = '\\0';\n return result;\n }\n }\n strncpy(result, str, len);\n for (j = 0; j < len; j++) {\n result[len + j] = str[len - j - 1];\n }\n result[2 * len] = '\\0';\n return result;\n}", + "test": "#include \n#include \n\nint main() {\n char *palindrome;\n\n // First test case\n palindrome = func0(\"\");\n assert(strcmp(palindrome, \"\") == 0);\n free(palindrome);\n\n // Second test case\n palindrome = func0(\"x\");\n assert(strcmp(palindrome, \"x\") == 0);\n free(palindrome);\n\n // Third test case\n palindrome = func0(\"xyz\");\n assert(strcmp(palindrome, \"xyzyx\") == 0);\n free(palindrome);\n\n // Fourth test case\n palindrome = func0(\"xyx\");\n assert(strcmp(palindrome, \"xyx\") == 0);\n free(palindrome);\n\n // Fifth test case\n palindrome = func0(\"jerry\");\n assert(strcmp(palindrome, \"jerryrrej\") == 0);\n free(palindrome);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov rbp, rdi\ncall _strlen\nmov r13, rax\nmov r14d, eax\nlea eax, [rax+rax]\nmov [rsp+48h+var_3C], eax\nadd eax, 1\ncdqe\nmov [rsp+48h+var_48], rax\nmov rdi, rax; size\ncall _malloc\nmov r15, rax\ntest rax, rax\njz loc_1323\ntest r13d, r13d\njle loc_1335\nmov r8d, r13d\nlea r12d, [r13-1]\nmov rsi, rbp\nmov ebx, 0\nmovsxd rdi, r13d\nsub rdi, 1\njmp short loc_125E\nloc_124E:\nadd ebx, 1\nadd rsi, 1\ncmp r14d, ebx\njz loc_12DE\nloc_125E:\nmov eax, r8d\nsub eax, ebx\nmov ecx, eax\nshr ecx, 1Fh\nadd ecx, eax\nsar ecx, 1\ncmp ebx, r12d\njz short loc_12D9\nlea rdx, [rbp+rdi+0]\nmov eax, 0\nloc_127B:\nmovzx r9d, byte ptr [rdx]\ncmp [rsi+rax], r9b\njnz short loc_124E\nadd rax, 1\nsub rdx, 1\ncmp ecx, eax\njg short loc_127B\nloc_1291:\nmovsxd r12, r13d\nmov rcx, [rsp+48h+var_48]\nmov rdx, r12\nmov rsi, rbp\nmov rdi, r15\ncall ___strncpy_chk\ntest ebx, ebx\njle short loc_12CC\nmovsxd rax, ebx\nlea rax, [rbp+rax-1]\nadd r12, r15\nloc_12B5:\nmovzx edx, byte ptr [rax]\nmov [r12], dl\nmov rdx, rax\nsub rax, 1\nadd r12, 1\ncmp rdx, rbp\njnz short loc_12B5\nloc_12CC:\nlea eax, [rbx+r13]\ncdqe\nmov byte ptr [r15+rax], 0\njmp short loc_1323\nloc_12D9:\nmov ebx, r12d\njmp short loc_1291\nloc_12DE:\nmovsxd rbx, ebx\nmov rcx, [rsp+48h+var_48]\nmov rdx, rbx\nmov rsi, rbp\nmov rdi, r15\ncall ___strncpy_chk\nlea rax, [rbp+rbx-1]\nlea rdx, [r15+rbx]\nlea rsi, [rbp+rbx-2]\nmov r12d, r12d\nsub rsi, r12\nloc_1307:\nmovzx ecx, byte ptr [rax]\nmov [rdx], cl\nsub rax, 1\nadd rdx, 1\ncmp rax, rsi\njnz short loc_1307\nloc_1319:\nmovsxd rax, [rsp+48h+var_3C]\nmov byte ptr [r15+rax], 0\nloc_1323:\nmov rax, r15\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1335:\nmovsxd rdx, r13d\nmov rcx, [rsp+48h+var_48]\nmov rsi, rbp\nmov rdi, rax\ncall ___strncpy_chk\njmp short loc_1319", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1)\n{\n int v1; // r13d\n _BYTE *v2; // rax\n _BYTE *v3; // r15\n int v4; // r12d\n const char *v5; // rsi\n int v6; // ebx\n const char *v7; // rdx\n __int64 v8; // rax\n const char *v9; // rax\n char *v10; // r12\n const char *v11; // rdx\n const char *v12; // rax\n _BYTE *v13; // rdx\n size_t v15; // [rsp+0h] [rbp-48h]\n\n v1 = strlen(a1);\n v15 = 2 * v1 + 1;\n v2 = malloc(v15);\n v3 = v2;\n if ( v2 )\n {\n if ( v1 <= 0 )\n {\n __strncpy_chk(v2, a1, v1, v15);\nLABEL_16:\n v3[2 * v1] = 0;\n }\n else\n {\n v4 = v1 - 1;\n v5 = a1;\n v6 = 0;\n while ( v6 != v4 )\n {\n v7 = &a1[v1 - 1];\n v8 = 0LL;\n while ( v5[v8] == *v7 )\n {\n ++v8;\n --v7;\n if ( (v1 - v6) / 2 <= (int)v8 )\n goto LABEL_9;\n }\n ++v6;\n ++v5;\n if ( v1 == v6 )\n {\n __strncpy_chk(v3, a1, v6, v15);\n v12 = &a1[v6 - 1];\n v13 = &v3[v6];\n do\n *v13++ = *v12--;\n while ( v12 != &a1[v6 - 2 - v4] );\n goto LABEL_16;\n }\n }\n v6 = v1 - 1;\nLABEL_9:\n __strncpy_chk(v3, a1, v1, v15);\n if ( v6 > 0 )\n {\n v9 = &a1[v6 - 1];\n v10 = &v3[v1];\n do\n {\n *v10 = *v9;\n v11 = v9--;\n ++v10;\n }\n while ( v11 != a1 );\n }\n v3[v6 + v1] = 0;\n }\n }\n return v3;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov rbp, rdi\ncall _strlen\nmov r13, rax\nmov r14d, eax\nlea eax, [rax+rax]\nmov [rsp+48h+var_3C], eax\nadd eax, 1\ncdqe\nmov [rsp+48h+var_48], rax\nmov rdi, rax; size\ncall _malloc\nmov r15, rax\ntest rax, rax\njz loc_1323\ntest r13d, r13d\njle loc_1335\nmov r8d, r13d\nlea r12d, [r13-1]\nmov rsi, rbp\nmov ebx, 0\nmovsxd rdi, r13d\nsub rdi, 1\njmp short loc_125E\nloc_124E:\nadd ebx, 1\nadd rsi, 1\ncmp r14d, ebx\njz loc_12DE\nloc_125E:\nmov eax, r8d\nsub eax, ebx\nmov ecx, eax\nshr ecx, 1Fh\nadd ecx, eax\nsar ecx, 1\ncmp ebx, r12d\njz short loc_12D9\nlea rdx, [rbp+rdi+0]\nmov eax, 0\nloc_127B:\nmovzx r9d, byte ptr [rdx]\ncmp [rsi+rax], r9b\njnz short loc_124E\nadd rax, 1\nsub rdx, 1\ncmp ecx, eax\njg short loc_127B\nloc_1291:\nmovsxd r12, r13d\nmov rcx, [rsp+48h+var_48]\nmov rdx, r12\nmov rsi, rbp\nmov rdi, r15\ncall ___strncpy_chk\ntest ebx, ebx\njle short loc_12CC\nmovsxd rax, ebx\nlea rax, [rbp+rax-1]\nadd r12, r15\nloc_12B5:\nmovzx edx, byte ptr [rax]\nmov [r12], dl\nmov rdx, rax\nsub rax, 1\nadd r12, 1\ncmp rdx, rbp\njnz short loc_12B5\nloc_12CC:\nlea eax, [rbx+r13]\ncdqe\nmov byte ptr [r15+rax], 0\njmp short loc_1323\nloc_12D9:\nmov ebx, r12d\njmp short loc_1291\nloc_12DE:\nmovsxd rbx, ebx\nmov rcx, [rsp+48h+var_48]\nmov rdx, rbx\nmov rsi, rbp\nmov rdi, r15\ncall ___strncpy_chk\nlea rax, [rbp+rbx-1]\nlea rdx, [r15+rbx]\nlea rsi, [rbp+rbx-2]\nmov r12d, r12d\nsub rsi, r12\nloc_1307:\nmovzx ecx, byte ptr [rax]\nmov [rdx], cl\nsub rax, 1\nadd rdx, 1\ncmp rax, rsi\njnz short loc_1307\nloc_1319:\nmovsxd rax, [rsp+48h+var_3C]\nmov byte ptr [r15+rax], 0\nloc_1323:\nmov rax, r15\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1335:\nmovsxd rdx, r13d\nmov rcx, [rsp+48h+var_48]\nmov rsi, rbp\nmov rdi, rax\ncall ___strncpy_chk\njmp short loc_1319", + "ida_strip_pseudo": "_BYTE *__fastcall sub_11E9(const char *a1)\n{\n int v1; // r13d\n _BYTE *v2; // rax\n _BYTE *v3; // r15\n int v4; // r12d\n const char *v5; // rsi\n int v6; // ebx\n const char *v7; // rdx\n __int64 v8; // rax\n const char *v9; // rax\n char *v10; // r12\n const char *v11; // rdx\n const char *v12; // rax\n _BYTE *v13; // rdx\n size_t v15; // [rsp+0h] [rbp-48h]\n\n v1 = strlen(a1);\n v15 = 2 * v1 + 1;\n v2 = malloc(v15);\n v3 = v2;\n if ( v2 )\n {\n if ( v1 <= 0 )\n {\n __strncpy_chk(v2, a1, v1, v15);\nLABEL_16:\n v3[2 * v1] = 0;\n }\n else\n {\n v4 = v1 - 1;\n v5 = a1;\n v6 = 0;\n while ( v6 != v4 )\n {\n v7 = &a1[v1 - 1];\n v8 = 0LL;\n while ( v5[v8] == *v7 )\n {\n ++v8;\n --v7;\n if ( (v1 - v6) / 2 <= (int)v8 )\n goto LABEL_9;\n }\n ++v6;\n ++v5;\n if ( v1 == v6 )\n {\n __strncpy_chk(v3, a1, v6, v15);\n v12 = &a1[v6 - 1];\n v13 = &v3[v6];\n do\n *v13++ = *v12--;\n while ( v12 != &a1[v6 - 2 - v4] );\n goto LABEL_16;\n }\n }\n v6 = v1 - 1;\nLABEL_9:\n __strncpy_chk(v3, a1, v1, v15);\n if ( v6 > 0 )\n {\n v9 = &a1[v6 - 1];\n v10 = &v3[v1];\n do\n {\n *v10 = *v9;\n v11 = v9--;\n ++v10;\n }\n while ( v11 != a1 );\n }\n v3[v6 + v1] = 0;\n }\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_11E9(const char *a1) {\n int v1;\n uint8_t *v2;\n uint8_t *v3;\n int v4;\n const char *v5;\n int v6;\n const char *v7;\n long long v8;\n const char *v9;\n char *v10;\n const char *v11;\n const char *v12;\n uint8_t *v13;\n unsigned int v15;\n v1 = strlen(a1);\n v15 = 2 * v1 + 1;\n v2 = malloc(v15);\n v3 = v2;\n if (v2) {\n if (v1 <= 0) {\n __strncpy_chk(v2, a1, v1, v15);\n LABEL_16:\n v3[2 * v1] = 0;\n } else {\n v4 = v1 - 1;\n v5 = a1;\n v6 = 0;\n while (v6 != v4) {\n v7 = &a1[v1 - 1];\n v8 = 0LL;\n while (v5[v8] == *v7) {\n ++v8;\n --v7;\n if ((v1 - v6) / 2 <= (int)v8) goto LABEL_9;\n }\n ++v6;\n ++v5;\n if (v1 == v6) {\n __strncpy_chk(v3, a1, v6, v15);\n v12 = &a1[v6 - 1];\n v13 = &v3[v6];\n do\n *v13++ = *v12--;\n while (v12 != &a1[v6 - 2 - v4]);\n goto LABEL_16;\n }\n }\n v6 = v1 - 1;\n LABEL_9:\n __strncpy_chk(v3, a1, v1, v15);\n if (v6 > 0) {\n v9 = &a1[v6 - 1];\n v10 = &v3[v1];\n do {\n *v10 = *v9;\n v11 = v9--;\n ++v10;\n } while (v11 != a1);\n }\n v3[v6 + v1] = 0;\n }\n }\n return v3;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1) {\n int v1;\n uint8_t *v2;\n uint8_t *v3;\n int v4;\n const char *v5;\n int v6;\n const char *v7;\n long long v8;\n const char *v9;\n char *v10;\n const char *v11;\n const char *v12;\n uint8_t *v13;\n unsigned int v15;\n v1 = strlen(a1);\n v15 = 2 * v1 + 1;\n v2 = malloc(v15);\n v3 = v2;\n if (v2) {\n if (v1 <= 0) {\n __strncpy_chk(v2, a1, v1, v15);\n LABEL_16:\n v3[2 * v1] = 0;\n } else {\n v4 = v1 - 1;\n v5 = a1;\n v6 = 0;\n while (v6 != v4) {\n v7 = &a1[v1 - 1];\n v8 = 0LL;\n while (v5[v8] == *v7) {\n ++v8;\n --v7;\n if ((v1 - v6) / 2 <= (int)v8) goto LABEL_9;\n }\n ++v6;\n ++v5;\n if (v1 == v6) {\n __strncpy_chk(v3, a1, v6, v15);\n v12 = &a1[v6 - 1];\n v13 = &v3[v6];\n do\n *v13++ = *v12--;\n while (v12 != &a1[v6 - 2 - v4]);\n goto LABEL_16;\n }\n }\n v6 = v1 - 1;\n LABEL_9:\n __strncpy_chk(v3, a1, v1, v15);\n if (v6 > 0) {\n v9 = &a1[v6 - 1];\n v10 = &v3[v1];\n do {\n *v10 = *v9;\n v11 = v9--;\n ++v10;\n } while (v11 != a1);\n }\n v3[v6 + v1] = 0;\n }\n }\n return v3;\n}" + }, + { + "index": "HumanEval-C-10", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char *func0(const char *str) {\n int len = strlen(str), i, j;\n char *result = (char *)malloc(2 * len + 1);\n if (!result) {\n return NULL;\n }\n for (i = 0; i < len; i++) {\n int is_palindrome = 1;\n for (j = 0; j < (len - i) / 2; j++) {\n if (str[i + j] != str[len - 1 - j]) {\n is_palindrome = 0;\n break;\n }\n }\n if (is_palindrome) {\n strncpy(result, str, len);\n for (j = 0; j < i; j++) {\n result[len + j] = str[i - j - 1];\n }\n result[len + i] = '\\0';\n return result;\n }\n }\n strncpy(result, str, len);\n for (j = 0; j < len; j++) {\n result[len + j] = str[len - j - 1];\n }\n result[2 * len] = '\\0';\n return result;\n}", + "test": "#include \n#include \n\nint main() {\n char *palindrome;\n\n // First test case\n palindrome = func0(\"\");\n assert(strcmp(palindrome, \"\") == 0);\n free(palindrome);\n\n // Second test case\n palindrome = func0(\"x\");\n assert(strcmp(palindrome, \"x\") == 0);\n free(palindrome);\n\n // Third test case\n palindrome = func0(\"xyz\");\n assert(strcmp(palindrome, \"xyzyx\") == 0);\n free(palindrome);\n\n // Fourth test case\n palindrome = func0(\"xyx\");\n assert(strcmp(palindrome, \"xyx\") == 0);\n free(palindrome);\n\n // Fifth test case\n palindrome = func0(\"jerry\");\n assert(strcmp(palindrome, \"jerryrrej\") == 0);\n free(palindrome);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 18h\ncall _strlen\nlea ebx, [rax+rax]\nmov r13, rax\nmov r15d, eax\nlea r8d, [rbx+1]\nmovsxd r8, r8d\nmov rdi, r8; size\nmov [rsp+48h+var_40], r8\ncall _malloc\nmov rdi, rax\ntest rax, rax\njz loc_145A\ntest r13d, r13d\nmov r8, [rsp+48h+var_40]\nmovsxd r14, r13d\njle loc_14B4\nlea r9d, [r13-1]\nmov rsi, r12\nxor ebp, ebp\nmovsxd r9, r9d\nloc_13D0:\nmov ecx, r13d\nsub ecx, ebp\nsar ecx, 1\njz loc_1470\nmovsxd rcx, ecx\nlea rdx, [r12+r9]\nmov rax, rsi\nadd rcx, rsi\njmp short loc_13FD\nloc_13F0:\nadd rax, 1\nsub rdx, 1\ncmp rax, rcx\njz short loc_1470\nloc_13FD:\nmovzx r10d, byte ptr [rdx]\ncmp [rax], r10b\njz short loc_13F0\nadd ebp, 1\nadd rsi, 1\ncmp r15d, ebp\njnz short loc_13D0\nmov rcx, r8\nmov rdx, r14\nmov rsi, r12\ncall ___strncpy_chk\nlea rsi, [r12+r14-2]\nlea ecx, [r13-1]\nmov rdi, rax\nsub rsi, rcx\nlea rax, [r12+r14-1]\nlea rdx, [rdi+r14]\nnop dword ptr [rax+rax+00000000h]\nloc_1440:\nmovzx ecx, byte ptr [rax]\nsub rax, 1\nadd rdx, 1\nmov [rdx-1], cl\ncmp rsi, rax\njnz short loc_1440\nloc_1453:\nmovsxd rbx, ebx\nmov byte ptr [rdi+rbx], 0\nloc_145A:\nadd rsp, 18h\nmov rax, rdi\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1470:\nmov rcx, r8\nmov rdx, r14\nmov rsi, r12\ncall ___strncpy_chk\nmov rdi, rax\ntest ebp, ebp\njz short loc_14A7\nmovsxd rax, ebp\nadd r14, rdi\nlea rax, [r12+rax-1]\nloc_1490:\nmovzx edx, byte ptr [rax]\nadd r14, 1\nmov [r14-1], dl\nmov rdx, rax\nsub rax, 1\ncmp rdx, r12\njnz short loc_1490\nloc_14A7:\nlea eax, [rbp+r13+0]\ncdqe\nmov byte ptr [rdi+rax], 0\njmp short loc_145A\nloc_14B4:\nmov rcx, r8\nmov rdx, r14\nmov rsi, r12\ncall ___strncpy_chk\nmov rdi, rax\njmp short loc_1453", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1)\n{\n int v2; // eax\n int v3; // ebx\n int v4; // r13d\n int v5; // r15d\n _BYTE *v6; // rdi\n const char *v7; // rsi\n int v8; // ebp\n const char *v9; // rdx\n const char *v10; // rax\n const char *v11; // rax\n _BYTE *v12; // rdx\n char v13; // cl\n __int64 v15; // rax\n char *v16; // r14\n const char *v17; // rax\n const char *v18; // rdx\n size_t v19; // [rsp+8h] [rbp-40h]\n\n v2 = strlen(a1);\n v3 = 2 * v2;\n v4 = v2;\n v5 = v2;\n v19 = 2 * v2 + 1;\n v6 = malloc(v19);\n if ( v6 )\n {\n if ( v4 <= 0 )\n {\n v6 = (_BYTE *)__strncpy_chk(v6, a1, v4, v19);\nLABEL_11:\n v6[v3] = 0;\n }\n else\n {\n v7 = a1;\n v8 = 0;\n while ( (v4 - v8) >> 1 )\n {\n v9 = &a1[v4 - 1];\n v10 = v7;\n while ( *v10 == *v9 )\n {\n ++v10;\n --v9;\n if ( v10 == &v7[(v4 - v8) >> 1] )\n goto LABEL_13;\n }\n ++v8;\n ++v7;\n if ( v5 == v8 )\n {\n v6 = (_BYTE *)__strncpy_chk(v6, a1, v4, v19);\n v11 = &a1[v4 - 1];\n v12 = &v6[v4];\n do\n {\n v13 = *v11--;\n *v12++ = v13;\n }\n while ( &a1[v4 - 2 - (v4 - 1)] != v11 );\n goto LABEL_11;\n }\n }\nLABEL_13:\n v15 = __strncpy_chk(v6, a1, v4, v19);\n v6 = (_BYTE *)v15;\n if ( v8 )\n {\n v16 = (char *)(v15 + v4);\n v17 = &a1[v8 - 1];\n do\n {\n *v16++ = *v17;\n v18 = v17--;\n }\n while ( v18 != a1 );\n }\n v6[v8 + v4] = 0;\n }\n }\n return v6;\n}", + "ida_strip_asm": "sub_1370:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 18h\ncall _strlen\nlea ebx, [rax+rax]\nmov r13, rax\nmov r15d, eax\nlea r8d, [rbx+1]\nmovsxd r8, r8d\nmov rdi, r8; size\nmov [rsp+48h+var_40], r8\ncall _malloc\nmov rdi, rax\ntest rax, rax\njz loc_145A\ntest r13d, r13d\nmov r8, [rsp+48h+var_40]\nmovsxd r14, r13d\njle loc_14B4\nlea r9d, [r13-1]\nmov rsi, r12\nxor ebp, ebp\nmovsxd r9, r9d\nloc_13D0:\nmov ecx, r13d\nsub ecx, ebp\nsar ecx, 1\njz loc_1470\nmovsxd rcx, ecx\nlea rdx, [r12+r9]\nmov rax, rsi\nadd rcx, rsi\njmp short loc_13FD\nloc_13F0:\nadd rax, 1\nsub rdx, 1\ncmp rax, rcx\njz short loc_1470\nloc_13FD:\nmovzx r10d, byte ptr [rdx]\ncmp [rax], r10b\njz short loc_13F0\nadd ebp, 1\nadd rsi, 1\ncmp r15d, ebp\njnz short loc_13D0\nmov rcx, r8\nmov rdx, r14\nmov rsi, r12\ncall ___strncpy_chk\nlea rsi, [r12+r14-2]\nlea ecx, [r13-1]\nmov rdi, rax\nsub rsi, rcx\nlea rax, [r12+r14-1]\nlea rdx, [rdi+r14]\nnop dword ptr [rax+rax+00000000h]\nloc_1440:\nmovzx ecx, byte ptr [rax]\nsub rax, 1\nadd rdx, 1\nmov [rdx-1], cl\ncmp rsi, rax\njnz short loc_1440\nloc_1453:\nmovsxd rbx, ebx\nmov byte ptr [rdi+rbx], 0\nloc_145A:\nadd rsp, 18h\nmov rax, rdi\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1470:\nmov rcx, r8\nmov rdx, r14\nmov rsi, r12\ncall ___strncpy_chk\nmov rdi, rax\ntest ebp, ebp\njz short loc_14A7\nmovsxd rax, ebp\nadd r14, rdi\nlea rax, [r12+rax-1]\nloc_1490:\nmovzx edx, byte ptr [rax]\nadd r14, 1\nmov [r14-1], dl\nmov rdx, rax\nsub rax, 1\ncmp rdx, r12\njnz short loc_1490\nloc_14A7:\nlea eax, [rbp+r13+0]\ncdqe\nmov byte ptr [rdi+rax], 0\njmp short loc_145A\nloc_14B4:\nmov rcx, r8\nmov rdx, r14\nmov rsi, r12\ncall ___strncpy_chk\nmov rdi, rax\njmp short loc_1453", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1370(const char *a1)\n{\n int v2; // eax\n int v3; // ebx\n int v4; // r13d\n int v5; // r15d\n _BYTE *v6; // rdi\n const char *v7; // rsi\n int v8; // ebp\n const char *v9; // rdx\n const char *v10; // rax\n const char *v11; // rax\n _BYTE *v12; // rdx\n char v13; // cl\n __int64 v15; // rax\n char *v16; // r14\n const char *v17; // rax\n const char *v18; // rdx\n size_t v19; // [rsp+8h] [rbp-40h]\n\n v2 = strlen(a1);\n v3 = 2 * v2;\n v4 = v2;\n v5 = v2;\n v19 = 2 * v2 + 1;\n v6 = malloc(v19);\n if ( v6 )\n {\n if ( v4 <= 0 )\n {\n v6 = (_BYTE *)__strncpy_chk(v6, a1, v4, v19);\nLABEL_11:\n v6[v3] = 0;\n }\n else\n {\n v7 = a1;\n v8 = 0;\n while ( (v4 - v8) >> 1 )\n {\n v9 = &a1[v4 - 1];\n v10 = v7;\n while ( *v10 == *v9 )\n {\n ++v10;\n --v9;\n if ( v10 == &v7[(v4 - v8) >> 1] )\n goto LABEL_13;\n }\n ++v8;\n ++v7;\n if ( v5 == v8 )\n {\n v6 = (_BYTE *)__strncpy_chk(v6, a1, v4, v19);\n v11 = &a1[v4 - 1];\n v12 = &v6[v4];\n do\n {\n v13 = *v11--;\n *v12++ = v13;\n }\n while ( &a1[v4 - 2 - (v4 - 1)] != v11 );\n goto LABEL_11;\n }\n }\nLABEL_13:\n v15 = __strncpy_chk(v6, a1, v4, v19);\n v6 = (_BYTE *)v15;\n if ( v8 )\n {\n v16 = (char *)(v15 + v4);\n v17 = &a1[v8 - 1];\n do\n {\n *v16++ = *v17;\n v18 = v17--;\n }\n while ( v18 != a1 );\n }\n v6[v8 + v4] = 0;\n }\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1370(const char *a1) {\n int v2;\n int v3;\n int v4;\n int v5;\n uint8_t *v6;\n const char *v7;\n int v8;\n const char *v9;\n const char *v10;\n const char *v11;\n uint8_t *v12;\n char v13;\n long long v15;\n char *v16;\n const char *v17;\n const char *v18;\n unsigned int v19;\n v2 = strlen(a1);\n v3 = 2 * v2;\n v4 = v2;\n v5 = v2;\n v19 = 2 * v2 + 1;\n v6 = malloc(v19);\n if (v6) {\n if (v4 <= 0) {\n v6 = (uint8_t *)__strncpy_chk(v6, a1, v4, v19);\n LABEL_11:\n v6[v3] = 0;\n } else {\n v7 = a1;\n v8 = 0;\n while ((v4 - v8) >> 1) {\n v9 = &a1[v4 - 1];\n v10 = v7;\n while (*v10 == *v9) {\n ++v10;\n --v9;\n if (v10 == &v7[(v4 - v8) >> 1]) goto LABEL_13;\n }\n ++v8;\n ++v7;\n if (v5 == v8) {\n v6 = (uint8_t *)__strncpy_chk(v6, a1, v4, v19);\n v11 = &a1[v4 - 1];\n v12 = &v6[v4];\n do {\n v13 = *v11--;\n *v12++ = v13;\n } while (&a1[v4 - 2 - (v4 - 1)] != v11);\n goto LABEL_11;\n }\n }\n LABEL_13:\n v15 = __strncpy_chk(v6, a1, v4, v19);\n v6 = (uint8_t *)v15;\n if (v8) {\n v16 = (char *)(v15 + v4);\n v17 = &a1[v8 - 1];\n do {\n *v16++ = *v17;\n v18 = v17--;\n } while (v18 != a1);\n }\n v6[v8 + v4] = 0;\n }\n }\n return v6;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1) {\n int v2;\n int v3;\n int v4;\n int v5;\n uint8_t *v6;\n const char *v7;\n int v8;\n const char *v9;\n const char *v10;\n const char *v11;\n uint8_t *v12;\n char v13;\n long long v15;\n char *v16;\n const char *v17;\n const char *v18;\n unsigned int v19;\n v2 = strlen(a1);\n v3 = 2 * v2;\n v4 = v2;\n v5 = v2;\n v19 = 2 * v2 + 1;\n v6 = malloc(v19);\n if (v6) {\n if (v4 <= 0) {\n v6 = (uint8_t *)__strncpy_chk(v6, a1, v4, v19);\n LABEL_11:\n v6[v3] = 0;\n } else {\n v7 = a1;\n v8 = 0;\n while ((v4 - v8) >> 1) {\n v9 = &a1[v4 - 1];\n v10 = v7;\n while (*v10 == *v9) {\n ++v10;\n --v9;\n if (v10 == &v7[(v4 - v8) >> 1]) goto LABEL_13;\n }\n ++v8;\n ++v7;\n if (v5 == v8) {\n v6 = (uint8_t *)__strncpy_chk(v6, a1, v4, v19);\n v11 = &a1[v4 - 1];\n v12 = &v6[v4];\n do {\n v13 = *v11--;\n *v12++ = v13;\n } while (&a1[v4 - 2 - (v4 - 1)] != v11);\n goto LABEL_11;\n }\n }\n LABEL_13:\n v15 = __strncpy_chk(v6, a1, v4, v19);\n v6 = (uint8_t *)v15;\n if (v8) {\n v16 = (char *)(v15 + v4);\n v17 = &a1[v8 - 1];\n do {\n *v16++ = *v17;\n v18 = v17--;\n } while (v18 != a1);\n }\n v6[v8 + v4] = 0;\n }\n }\n return v6;\n}" + }, + { + "index": "HumanEval-C-10", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char *func0(const char *str) {\n int len = strlen(str), i, j;\n char *result = (char *)malloc(2 * len + 1);\n if (!result) {\n return NULL;\n }\n for (i = 0; i < len; i++) {\n int is_palindrome = 1;\n for (j = 0; j < (len - i) / 2; j++) {\n if (str[i + j] != str[len - 1 - j]) {\n is_palindrome = 0;\n break;\n }\n }\n if (is_palindrome) {\n strncpy(result, str, len);\n for (j = 0; j < i; j++) {\n result[len + j] = str[i - j - 1];\n }\n result[len + i] = '\\0';\n return result;\n }\n }\n strncpy(result, str, len);\n for (j = 0; j < len; j++) {\n result[len + j] = str[len - j - 1];\n }\n result[2 * len] = '\\0';\n return result;\n}", + "test": "#include \n#include \n\nint main() {\n char *palindrome;\n\n // First test case\n palindrome = func0(\"\");\n assert(strcmp(palindrome, \"\") == 0);\n free(palindrome);\n\n // Second test case\n palindrome = func0(\"x\");\n assert(strcmp(palindrome, \"x\") == 0);\n free(palindrome);\n\n // Third test case\n palindrome = func0(\"xyz\");\n assert(strcmp(palindrome, \"xyzyx\") == 0);\n free(palindrome);\n\n // Fourth test case\n palindrome = func0(\"xyx\");\n assert(strcmp(palindrome, \"xyx\") == 0);\n free(palindrome);\n\n // Fifth test case\n palindrome = func0(\"jerry\");\n assert(strcmp(palindrome, \"jerryrrej\") == 0);\n free(palindrome);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 18h\ncall _strlen\nlea ebx, [rax+rax]\nmov r13, rax\nmov r15d, eax\nlea r8d, [rbx+1]\nmovsxd r8, r8d\nmov rdi, r8; size\nmov [rsp+48h+var_40], r8\ncall _malloc\nmov rdi, rax\ntest rax, rax\njz loc_145A\ntest r13d, r13d\nmov r8, [rsp+48h+var_40]\nmovsxd r14, r13d\njle loc_14B4\nlea r9d, [r13-1]\nmov rsi, r12\nxor ebp, ebp\nmovsxd r9, r9d\nloc_13D0:\nmov ecx, r13d\nsub ecx, ebp\nsar ecx, 1\njz loc_1470\nmovsxd rcx, ecx\nlea rdx, [r12+r9]\nmov rax, rsi\nadd rcx, rsi\njmp short loc_13FD\nloc_13F0:\nadd rax, 1\nsub rdx, 1\ncmp rax, rcx\njz short loc_1470\nloc_13FD:\nmovzx r10d, byte ptr [rdx]\ncmp [rax], r10b\njz short loc_13F0\nadd ebp, 1\nadd rsi, 1\ncmp r15d, ebp\njnz short loc_13D0\nmov rcx, r8\nmov rdx, r14\nmov rsi, r12\ncall ___strncpy_chk\nlea rsi, [r12+r14-2]\nlea ecx, [r13-1]\nmov rdi, rax\nsub rsi, rcx\nlea rax, [r12+r14-1]\nlea rdx, [rdi+r14]\nnop dword ptr [rax+rax+00000000h]\nloc_1440:\nmovzx ecx, byte ptr [rax]\nsub rax, 1\nadd rdx, 1\nmov [rdx-1], cl\ncmp rsi, rax\njnz short loc_1440\nloc_1453:\nmovsxd rbx, ebx\nmov byte ptr [rdi+rbx], 0\nloc_145A:\nadd rsp, 18h\nmov rax, rdi\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1470:\nmov rcx, r8\nmov rdx, r14\nmov rsi, r12\ncall ___strncpy_chk\nmov rdi, rax\ntest ebp, ebp\njz short loc_14A7\nmovsxd rax, ebp\nadd r14, rdi\nlea rax, [r12+rax-1]\nloc_1490:\nmovzx edx, byte ptr [rax]\nadd r14, 1\nmov [r14-1], dl\nmov rdx, rax\nsub rax, 1\ncmp rdx, r12\njnz short loc_1490\nloc_14A7:\nlea eax, [rbp+r13+0]\ncdqe\nmov byte ptr [rdi+rax], 0\njmp short loc_145A\nloc_14B4:\nmov rcx, r8\nmov rdx, r14\nmov rsi, r12\ncall ___strncpy_chk\nmov rdi, rax\njmp short loc_1453", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1)\n{\n int v2; // eax\n int v3; // ebx\n int v4; // r13d\n int v5; // r15d\n _BYTE *v6; // rdi\n const char *v7; // rsi\n int v8; // ebp\n const char *v9; // rdx\n const char *v10; // rax\n const char *v11; // rax\n _BYTE *v12; // rdx\n char v13; // cl\n __int64 v15; // rax\n char *v16; // r14\n const char *v17; // rax\n const char *v18; // rdx\n size_t v19; // [rsp+8h] [rbp-40h]\n\n v2 = strlen(a1);\n v3 = 2 * v2;\n v4 = v2;\n v5 = v2;\n v19 = 2 * v2 + 1;\n v6 = malloc(v19);\n if ( v6 )\n {\n if ( v4 <= 0 )\n {\n v6 = (_BYTE *)__strncpy_chk(v6, a1, v4, v19);\nLABEL_11:\n v6[v3] = 0;\n }\n else\n {\n v7 = a1;\n v8 = 0;\n while ( (v4 - v8) >> 1 )\n {\n v9 = &a1[v4 - 1];\n v10 = v7;\n while ( *v10 == *v9 )\n {\n ++v10;\n --v9;\n if ( v10 == &v7[(v4 - v8) >> 1] )\n goto LABEL_13;\n }\n ++v8;\n ++v7;\n if ( v5 == v8 )\n {\n v6 = (_BYTE *)__strncpy_chk(v6, a1, v4, v19);\n v11 = &a1[v4 - 1];\n v12 = &v6[v4];\n do\n {\n v13 = *v11--;\n *v12++ = v13;\n }\n while ( &a1[v4 - 2 - (v4 - 1)] != v11 );\n goto LABEL_11;\n }\n }\nLABEL_13:\n v15 = __strncpy_chk(v6, a1, v4, v19);\n v6 = (_BYTE *)v15;\n if ( v8 )\n {\n v16 = (char *)(v15 + v4);\n v17 = &a1[v8 - 1];\n do\n {\n *v16++ = *v17;\n v18 = v17--;\n }\n while ( v18 != a1 );\n }\n v6[v8 + v4] = 0;\n }\n }\n return v6;\n}", + "ida_strip_asm": "sub_1370:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 18h\ncall _strlen\nlea ebx, [rax+rax]\nmov r13, rax\nmov r15d, eax\nlea r8d, [rbx+1]\nmovsxd r8, r8d\nmov rdi, r8; size\nmov [rsp+48h+var_40], r8\ncall _malloc\nmov rdi, rax\ntest rax, rax\njz loc_145A\ntest r13d, r13d\nmov r8, [rsp+48h+var_40]\nmovsxd r14, r13d\njle loc_14B4\nlea r9d, [r13-1]\nmov rsi, r12\nxor ebp, ebp\nmovsxd r9, r9d\nloc_13D0:\nmov ecx, r13d\nsub ecx, ebp\nsar ecx, 1\njz loc_1470\nmovsxd rcx, ecx\nlea rdx, [r12+r9]\nmov rax, rsi\nadd rcx, rsi\njmp short loc_13FD\nloc_13F0:\nadd rax, 1\nsub rdx, 1\ncmp rax, rcx\njz short loc_1470\nloc_13FD:\nmovzx r10d, byte ptr [rdx]\ncmp [rax], r10b\njz short loc_13F0\nadd ebp, 1\nadd rsi, 1\ncmp r15d, ebp\njnz short loc_13D0\nmov rcx, r8\nmov rdx, r14\nmov rsi, r12\ncall ___strncpy_chk\nlea rsi, [r12+r14-2]\nlea ecx, [r13-1]\nmov rdi, rax\nsub rsi, rcx\nlea rax, [r12+r14-1]\nlea rdx, [rdi+r14]\nnop dword ptr [rax+rax+00000000h]\nloc_1440:\nmovzx ecx, byte ptr [rax]\nsub rax, 1\nadd rdx, 1\nmov [rdx-1], cl\ncmp rsi, rax\njnz short loc_1440\nloc_1453:\nmovsxd rbx, ebx\nmov byte ptr [rdi+rbx], 0\nloc_145A:\nadd rsp, 18h\nmov rax, rdi\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1470:\nmov rcx, r8\nmov rdx, r14\nmov rsi, r12\ncall ___strncpy_chk\nmov rdi, rax\ntest ebp, ebp\njz short loc_14A7\nmovsxd rax, ebp\nadd r14, rdi\nlea rax, [r12+rax-1]\nloc_1490:\nmovzx edx, byte ptr [rax]\nadd r14, 1\nmov [r14-1], dl\nmov rdx, rax\nsub rax, 1\ncmp rdx, r12\njnz short loc_1490\nloc_14A7:\nlea eax, [rbp+r13+0]\ncdqe\nmov byte ptr [rdi+rax], 0\njmp short loc_145A\nloc_14B4:\nmov rcx, r8\nmov rdx, r14\nmov rsi, r12\ncall ___strncpy_chk\nmov rdi, rax\njmp short loc_1453", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1370(const char *a1)\n{\n int v2; // eax\n int v3; // ebx\n int v4; // r13d\n int v5; // r15d\n _BYTE *v6; // rdi\n const char *v7; // rsi\n int v8; // ebp\n const char *v9; // rdx\n const char *v10; // rax\n const char *v11; // rax\n _BYTE *v12; // rdx\n char v13; // cl\n __int64 v15; // rax\n char *v16; // r14\n const char *v17; // rax\n const char *v18; // rdx\n size_t v19; // [rsp+8h] [rbp-40h]\n\n v2 = strlen(a1);\n v3 = 2 * v2;\n v4 = v2;\n v5 = v2;\n v19 = 2 * v2 + 1;\n v6 = malloc(v19);\n if ( v6 )\n {\n if ( v4 <= 0 )\n {\n v6 = (_BYTE *)__strncpy_chk(v6, a1, v4, v19);\nLABEL_11:\n v6[v3] = 0;\n }\n else\n {\n v7 = a1;\n v8 = 0;\n while ( (v4 - v8) >> 1 )\n {\n v9 = &a1[v4 - 1];\n v10 = v7;\n while ( *v10 == *v9 )\n {\n ++v10;\n --v9;\n if ( v10 == &v7[(v4 - v8) >> 1] )\n goto LABEL_13;\n }\n ++v8;\n ++v7;\n if ( v5 == v8 )\n {\n v6 = (_BYTE *)__strncpy_chk(v6, a1, v4, v19);\n v11 = &a1[v4 - 1];\n v12 = &v6[v4];\n do\n {\n v13 = *v11--;\n *v12++ = v13;\n }\n while ( &a1[v4 - 2 - (v4 - 1)] != v11 );\n goto LABEL_11;\n }\n }\nLABEL_13:\n v15 = __strncpy_chk(v6, a1, v4, v19);\n v6 = (_BYTE *)v15;\n if ( v8 )\n {\n v16 = (char *)(v15 + v4);\n v17 = &a1[v8 - 1];\n do\n {\n *v16++ = *v17;\n v18 = v17--;\n }\n while ( v18 != a1 );\n }\n v6[v8 + v4] = 0;\n }\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1370(const char *a1) {\n int v2;\n int v3;\n int v4;\n int v5;\n uint8_t *v6;\n const char *v7;\n int v8;\n const char *v9;\n const char *v10;\n const char *v11;\n uint8_t *v12;\n char v13;\n long long v15;\n char *v16;\n const char *v17;\n const char *v18;\n unsigned int v19;\n v2 = strlen(a1);\n v3 = 2 * v2;\n v4 = v2;\n v5 = v2;\n v19 = 2 * v2 + 1;\n v6 = malloc(v19);\n if (v6) {\n if (v4 <= 0) {\n v6 = (uint8_t *)__strncpy_chk(v6, a1, v4, v19);\n LABEL_11:\n v6[v3] = 0;\n } else {\n v7 = a1;\n v8 = 0;\n while ((v4 - v8) >> 1) {\n v9 = &a1[v4 - 1];\n v10 = v7;\n while (*v10 == *v9) {\n ++v10;\n --v9;\n if (v10 == &v7[(v4 - v8) >> 1]) goto LABEL_13;\n }\n ++v8;\n ++v7;\n if (v5 == v8) {\n v6 = (uint8_t *)__strncpy_chk(v6, a1, v4, v19);\n v11 = &a1[v4 - 1];\n v12 = &v6[v4];\n do {\n v13 = *v11--;\n *v12++ = v13;\n } while (&a1[v4 - 2 - (v4 - 1)] != v11);\n goto LABEL_11;\n }\n }\n LABEL_13:\n v15 = __strncpy_chk(v6, a1, v4, v19);\n v6 = (uint8_t *)v15;\n if (v8) {\n v16 = (char *)(v15 + v4);\n v17 = &a1[v8 - 1];\n do {\n *v16++ = *v17;\n v18 = v17--;\n } while (v18 != a1);\n }\n v6[v8 + v4] = 0;\n }\n }\n return v6;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1) {\n int v2;\n int v3;\n int v4;\n int v5;\n uint8_t *v6;\n const char *v7;\n int v8;\n const char *v9;\n const char *v10;\n const char *v11;\n uint8_t *v12;\n char v13;\n long long v15;\n char *v16;\n const char *v17;\n const char *v18;\n unsigned int v19;\n v2 = strlen(a1);\n v3 = 2 * v2;\n v4 = v2;\n v5 = v2;\n v19 = 2 * v2 + 1;\n v6 = malloc(v19);\n if (v6) {\n if (v4 <= 0) {\n v6 = (uint8_t *)__strncpy_chk(v6, a1, v4, v19);\n LABEL_11:\n v6[v3] = 0;\n } else {\n v7 = a1;\n v8 = 0;\n while ((v4 - v8) >> 1) {\n v9 = &a1[v4 - 1];\n v10 = v7;\n while (*v10 == *v9) {\n ++v10;\n --v9;\n if (v10 == &v7[(v4 - v8) >> 1]) goto LABEL_13;\n }\n ++v8;\n ++v7;\n if (v5 == v8) {\n v6 = (uint8_t *)__strncpy_chk(v6, a1, v4, v19);\n v11 = &a1[v4 - 1];\n v12 = &v6[v4];\n do {\n v13 = *v11--;\n *v12++ = v13;\n } while (&a1[v4 - 2 - (v4 - 1)] != v11);\n goto LABEL_11;\n }\n }\n LABEL_13:\n v15 = __strncpy_chk(v6, a1, v4, v19);\n v6 = (uint8_t *)v15;\n if (v8) {\n v16 = (char *)(v15 + v4);\n v17 = &a1[v8 - 1];\n do {\n *v16++ = *v17;\n v18 = v17--;\n } while (v18 != a1);\n }\n v6[v8 + v4] = 0;\n }\n }\n return v6;\n}" + }, + { + "index": "HumanEval-C-11", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char *func0(const char *a, const char *b) {\n int len_a = strlen(a);\n int len_b = strlen(b);\n int min_len = len_a < len_b ? len_a : len_b;\n char *output = malloc((min_len + 1) * sizeof(char));\n if (!output) return NULL;\n for (int i = 0; i < min_len; i++) {\n output[i] = (a[i] == b[i]) ? '0' : '1';\n }\n output[min_len] = '\\0';\n return output;\n}", + "test": "#include \n#include \n#include \n#include \n\nint main() {\n char *result;\n\n result = func0(\"111000\", \"101010\");\n assert(strcmp(result, \"010010\") == 0);\n free(result);\n\n result = func0(\"1\", \"1\");\n assert(strcmp(result, \"0\") == 0);\n free(result);\n\n result = func0(\"0101\", \"0000\");\n assert(strcmp(result, \"0101\") == 0);\n free(result);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov [rbp+var_30], rsi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_14], eax\nmov rax, [rbp+var_30]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_10], eax\nmov edx, [rbp+var_10]\nmov eax, [rbp+var_14]\ncmp edx, eax\ncmovle eax, edx\nmov [rbp+var_C], eax\nmov eax, [rbp+var_C]\nadd eax, 1\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\ncmp [rbp+var_8], 0\njnz short loc_122B\nmov eax, 0\njmp short locret_1293\nloc_122B:\nmov [rbp+var_18], 0\njmp short loc_1277\nloc_1234:\nmov eax, [rbp+var_18]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_18]\nmovsxd rcx, eax\nmov rax, [rbp+var_30]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njnz short loc_125F\nmov ecx, 30h ; '0'\njmp short loc_1264\nloc_125F:\nmov ecx, 31h ; '1'\nloc_1264:\nmov eax, [rbp+var_18]\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov [rax], cl\nadd [rbp+var_18], 1\nloc_1277:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_C]\njl short loc_1234\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+var_8]\nlocret_1293:\nleave\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1, const char *a2)\n{\n int v2; // edx\n int v3; // eax\n char v5; // cl\n int i; // [rsp+18h] [rbp-18h]\n int v7; // [rsp+1Ch] [rbp-14h]\n int v8; // [rsp+24h] [rbp-Ch]\n _BYTE *v9; // [rsp+28h] [rbp-8h]\n\n v7 = strlen(a1);\n v2 = strlen(a2);\n v3 = v7;\n if ( v2 <= v7 )\n v3 = v2;\n v8 = v3;\n v9 = malloc(v3 + 1);\n if ( !v9 )\n return 0LL;\n for ( i = 0; i < v8; ++i )\n {\n if ( a1[i] == a2[i] )\n v5 = 48;\n else\n v5 = 49;\n v9[i] = v5;\n }\n v9[v8] = 0;\n return v9;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov [rbp+var_30], rsi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_14], eax\nmov rax, [rbp+var_30]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_10], eax\nmov edx, [rbp+var_10]\nmov eax, [rbp+var_14]\ncmp edx, eax\ncmovle eax, edx\nmov [rbp+var_C], eax\nmov eax, [rbp+var_C]\nadd eax, 1\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\ncmp [rbp+var_8], 0\njnz short loc_122B\nmov eax, 0\njmp short locret_1293\nloc_122B:\nmov [rbp+var_18], 0\njmp short loc_1277\nloc_1234:\nmov eax, [rbp+var_18]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_18]\nmovsxd rcx, eax\nmov rax, [rbp+var_30]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njnz short loc_125F\nmov ecx, 30h ; '0'\njmp short loc_1264\nloc_125F:\nmov ecx, 31h ; '1'\nloc_1264:\nmov eax, [rbp+var_18]\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov [rax], cl\nadd [rbp+var_18], 1\nloc_1277:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_C]\njl short loc_1234\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+var_8]\nlocret_1293:\nleave\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_11C9(const char *a1, const char *a2)\n{\n int v2; // edx\n int v3; // eax\n char v5; // cl\n int i; // [rsp+18h] [rbp-18h]\n int v7; // [rsp+1Ch] [rbp-14h]\n int v8; // [rsp+24h] [rbp-Ch]\n _BYTE *v9; // [rsp+28h] [rbp-8h]\n\n v7 = strlen(a1);\n v2 = strlen(a2);\n v3 = v7;\n if ( v2 <= v7 )\n v3 = v2;\n v8 = v3;\n v9 = malloc(v3 + 1);\n if ( !v9 )\n return 0LL;\n for ( i = 0; i < v8; ++i )\n {\n if ( a1[i] == a2[i] )\n v5 = 48;\n else\n v5 = 49;\n v9[i] = v5;\n }\n v9[v8] = 0;\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_11C9(const char *a1, const char *a2) {\n int v2;\n int v3;\n char v5;\n int i;\n int v7;\n int v8;\n uint8_t *v9;\n v7 = strlen(a1);\n v2 = strlen(a2);\n v3 = v7;\n if (v2 <= v7) v3 = v2;\n v8 = v3;\n v9 = malloc(v3 + 1);\n if (!v9) return 0LL;\n for (i = 0; i < v8; ++i) {\n if (a1[i] == a2[i])\n v5 = 48;\n else\n v5 = 49;\n v9[i] = v5;\n }\n v9[v8] = 0;\n return v9;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1, const char *a2) {\n int v2;\n int v3;\n char v5;\n int i;\n int v7;\n int v8;\n uint8_t *v9;\n v7 = strlen(a1);\n v2 = strlen(a2);\n v3 = v7;\n if (v2 <= v7) v3 = v2;\n v8 = v3;\n v9 = malloc(v3 + 1);\n if (!v9) return 0LL;\n for (i = 0; i < v8; ++i) {\n if (a1[i] == a2[i])\n v5 = 48;\n else\n v5 = 49;\n v9[i] = v5;\n }\n v9[v8] = 0;\n return v9;\n}" + }, + { + "index": "HumanEval-C-11", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char *func0(const char *a, const char *b) {\n int len_a = strlen(a);\n int len_b = strlen(b);\n int min_len = len_a < len_b ? len_a : len_b;\n char *output = malloc((min_len + 1) * sizeof(char));\n if (!output) return NULL;\n for (int i = 0; i < min_len; i++) {\n output[i] = (a[i] == b[i]) ? '0' : '1';\n }\n output[min_len] = '\\0';\n return output;\n}", + "test": "#include \n#include \n#include \n#include \n\nint main() {\n char *result;\n\n result = func0(\"111000\", \"101010\");\n assert(strcmp(result, \"010010\") == 0);\n free(result);\n\n result = func0(\"1\", \"1\");\n assert(strcmp(result, \"0\") == 0);\n free(result);\n\n result = func0(\"0101\", \"0000\");\n assert(strcmp(result, \"0101\") == 0);\n free(result);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nmov rbp, rsi\ncall _strlen\nmov r12, rax\nmov rdi, rbp; s\ncall _strlen\ncmp r12d, eax\ncmovg r12d, eax\nlea edi, [r12+1]\nmovsxd rdi, edi; size\ncall _malloc\ntest rax, rax\njz short loc_1230\ntest r12d, r12d\njle short loc_1228\nmovsxd rsi, r12d\nmov edx, 0\nloc_120D:\nmovzx edi, byte ptr [rbp+rdx+0]\ncmp [rbx+rdx], dil\nsetnz cl\nadd ecx, 30h ; '0'\nmov [rax+rdx], cl\nadd rdx, 1\ncmp rdx, rsi\njnz short loc_120D\nloc_1228:\nmovsxd r12, r12d\nmov byte ptr [rax+r12], 0\nloc_1230:\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1, const char *a2)\n{\n int v2; // r12d\n int v3; // eax\n _BYTE *result; // rax\n __int64 i; // rdx\n\n v2 = strlen(a1);\n v3 = strlen(a2);\n if ( v2 > v3 )\n v2 = v3;\n result = malloc(v2 + 1);\n if ( result )\n {\n if ( v2 > 0 )\n {\n for ( i = 0LL; i != v2; ++i )\n result[i] = (a1[i] != a2[i]) + 48;\n }\n result[v2] = 0;\n }\n return result;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nmov rbp, rsi\ncall _strlen\nmov r12, rax\nmov rdi, rbp; s\ncall _strlen\ncmp r12d, eax\ncmovg r12d, eax\nlea edi, [r12+1]\nmovsxd rdi, edi; size\ncall _malloc\ntest rax, rax\njz short loc_1230\ntest r12d, r12d\njle short loc_1228\nmovsxd rsi, r12d\nmov edx, 0\nloc_120D:\nmovzx edi, byte ptr [rbp+rdx+0]\ncmp [rbx+rdx], dil\nsetnz cl\nadd ecx, 30h ; '0'\nmov [rax+rdx], cl\nadd rdx, 1\ncmp rdx, rsi\njnz short loc_120D\nloc_1228:\nmovsxd r12, r12d\nmov byte ptr [rax+r12], 0\nloc_1230:\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_11C9(const char *a1, const char *a2)\n{\n int v2; // r12d\n int v3; // eax\n _BYTE *result; // rax\n __int64 i; // rdx\n\n v2 = strlen(a1);\n v3 = strlen(a2);\n if ( v2 > v3 )\n v2 = v3;\n result = malloc(v2 + 1);\n if ( result )\n {\n if ( v2 > 0 )\n {\n for ( i = 0LL; i != v2; ++i )\n result[i] = (a1[i] != a2[i]) + 48;\n }\n result[v2] = 0;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_11C9(const char *a1, const char *a2) {\n int v2;\n int v3;\n uint8_t *result;\n long long i;\n v2 = strlen(a1);\n v3 = strlen(a2);\n if (v2 > v3) v2 = v3;\n result = malloc(v2 + 1);\n if (result) {\n if (v2 > 0) {\n for (i = 0LL; i != v2; ++i) result[i] = (a1[i] != a2[i]) + 48;\n }\n result[v2] = 0;\n }\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1, const char *a2) {\n int v2;\n int v3;\n uint8_t *result;\n long long i;\n v2 = strlen(a1);\n v3 = strlen(a2);\n if (v2 > v3) v2 = v3;\n result = malloc(v2 + 1);\n if (result) {\n if (v2 > 0) {\n for (i = 0LL; i != v2; ++i) result[i] = (a1[i] != a2[i]) + 48;\n }\n result[v2] = 0;\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-11", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char *func0(const char *a, const char *b) {\n int len_a = strlen(a);\n int len_b = strlen(b);\n int min_len = len_a < len_b ? len_a : len_b;\n char *output = malloc((min_len + 1) * sizeof(char));\n if (!output) return NULL;\n for (int i = 0; i < min_len; i++) {\n output[i] = (a[i] == b[i]) ? '0' : '1';\n }\n output[min_len] = '\\0';\n return output;\n}", + "test": "#include \n#include \n#include \n#include \n\nint main() {\n char *result;\n\n result = func0(\"111000\", \"101010\");\n assert(strcmp(result, \"010010\") == 0);\n free(result);\n\n result = func0(\"1\", \"1\");\n assert(strcmp(result, \"0\") == 0);\n free(result);\n\n result = func0(\"0101\", \"0000\");\n assert(strcmp(result, \"0101\") == 0);\n free(result);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r12\nmov r12, rsi\npush rbp\nmov rbp, rdi\npush rbx\ncall _strlen\nmov rdi, r12; s\nmov rbx, rax\ncall _strlen\ncmp ebx, eax\ncmovg ebx, eax\nlea edi, [rbx+1]\nmovsxd rdi, edi; size\ncall _malloc\ntest rax, rax\njz short loc_132F\nmovsxd rsi, ebx\nxor edx, edx\ntest ebx, ebx\njle short loc_132B\nnop dword ptr [rax+00h]\nloc_1310:\nmovzx ebx, byte ptr [r12+rdx]\ncmp [rbp+rdx+0], bl\nsetnz cl\nadd ecx, 30h ; '0'\nmov [rax+rdx], cl\nadd rdx, 1\ncmp rsi, rdx\njnz short loc_1310\nloc_132B:\nmov byte ptr [rax+rsi], 0\nloc_132F:\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1, const char *a2)\n{\n int v2; // ebx\n int v3; // eax\n _BYTE *result; // rax\n __int64 v5; // rdx\n\n v2 = strlen(a1);\n v3 = strlen(a2);\n if ( v2 > v3 )\n v2 = v3;\n result = malloc(v2 + 1);\n if ( result )\n {\n v5 = 0LL;\n if ( v2 > 0 )\n {\n do\n {\n result[v5] = (a1[v5] != a2[v5]) + 48;\n ++v5;\n }\n while ( v2 != v5 );\n }\n result[v2] = 0;\n }\n return result;\n}", + "ida_strip_asm": "sub_12D0:\nendbr64\npush r12\nmov r12, rsi\npush rbp\nmov rbp, rdi\npush rbx\ncall _strlen\nmov rdi, r12; s\nmov rbx, rax\ncall _strlen\ncmp ebx, eax\ncmovg ebx, eax\nlea edi, [rbx+1]\nmovsxd rdi, edi; size\ncall _malloc\ntest rax, rax\njz short loc_132F\nmovsxd rsi, ebx\nxor edx, edx\ntest ebx, ebx\njle short loc_132B\nnop dword ptr [rax+00h]\nloc_1310:\nmovzx ebx, byte ptr [r12+rdx]\ncmp [rbp+rdx+0], bl\nsetnz cl\nadd ecx, 30h ; '0'\nmov [rax+rdx], cl\nadd rdx, 1\ncmp rsi, rdx\njnz short loc_1310\nloc_132B:\nmov byte ptr [rax+rsi], 0\nloc_132F:\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_12D0(const char *a1, const char *a2)\n{\n int v2; // ebx\n int v3; // eax\n _BYTE *result; // rax\n __int64 v5; // rdx\n\n v2 = strlen(a1);\n v3 = strlen(a2);\n if ( v2 > v3 )\n v2 = v3;\n result = malloc(v2 + 1);\n if ( result )\n {\n v5 = 0LL;\n if ( v2 > 0 )\n {\n do\n {\n result[v5] = (a1[v5] != a2[v5]) + 48;\n ++v5;\n }\n while ( v2 != v5 );\n }\n result[v2] = 0;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_12D0(const char *a1, const char *a2) {\n int v2;\n int v3;\n uint8_t *result;\n long long v5;\n v2 = strlen(a1);\n v3 = strlen(a2);\n if (v2 > v3) v2 = v3;\n result = malloc(v2 + 1);\n if (result) {\n v5 = 0LL;\n if (v2 > 0) {\n do {\n result[v5] = (a1[v5] != a2[v5]) + 48;\n ++v5;\n } while (v2 != v5);\n }\n result[v2] = 0;\n }\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1, const char *a2) {\n int v2;\n int v3;\n uint8_t *result;\n long long v5;\n v2 = strlen(a1);\n v3 = strlen(a2);\n if (v2 > v3) v2 = v3;\n result = malloc(v2 + 1);\n if (result) {\n v5 = 0LL;\n if (v2 > 0) {\n do {\n result[v5] = (a1[v5] != a2[v5]) + 48;\n ++v5;\n } while (v2 != v5);\n }\n result[v2] = 0;\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-11", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char *func0(const char *a, const char *b) {\n int len_a = strlen(a);\n int len_b = strlen(b);\n int min_len = len_a < len_b ? len_a : len_b;\n char *output = malloc((min_len + 1) * sizeof(char));\n if (!output) return NULL;\n for (int i = 0; i < min_len; i++) {\n output[i] = (a[i] == b[i]) ? '0' : '1';\n }\n output[min_len] = '\\0';\n return output;\n}", + "test": "#include \n#include \n#include \n#include \n\nint main() {\n char *result;\n\n result = func0(\"111000\", \"101010\");\n assert(strcmp(result, \"010010\") == 0);\n free(result);\n\n result = func0(\"1\", \"1\");\n assert(strcmp(result, \"0\") == 0);\n free(result);\n\n result = func0(\"0101\", \"0000\");\n assert(strcmp(result, \"0101\") == 0);\n free(result);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r12\nmov r12, rdi\npush rbp\nmov rbp, rsi\npush rbx\ncall _strlen\nmov rdi, rbp; s\nmov rbx, rax\ncall _strlen\ncmp ebx, eax\ncmovg ebx, eax\nlea edi, [rbx+1]\nmovsxd rdi, edi; size\ncall _malloc\nmov rdx, rax\ntest rax, rax\njz loc_14A0\ntest ebx, ebx\njle loc_1499\nlea eax, [rbx-1]\ncmp eax, 0Eh\njbe loc_14A8\nmov ecx, ebx\nmovdqa xmm3, cs:xmmword_20A0\nmovdqa xmm2, cs:xmmword_20B0\nxor eax, eax\nshr ecx, 4\nshl rcx, 4\nnop dword ptr [rax+00000000h]\nloc_1340:\nmovdqu xmm0, xmmword ptr [r12+rax]\nmovdqu xmm4, xmmword ptr [rbp+rax+0]\nmovdqa xmm1, xmm3\npcmpeqb xmm0, xmm4\npand xmm1, xmm0\npandn xmm0, xmm2\npor xmm0, xmm1\nmovups xmmword ptr [rdx+rax], xmm0\nadd rax, 10h\ncmp rcx, rax\njnz short loc_1340\nmov eax, ebx\nand eax, 0FFFFFFF0h\nmov ecx, eax\ncmp ebx, eax\njz loc_1499\nloc_137C:\nmov esi, ebx\nsub esi, ecx\nlea edi, [rsi-1]\ncmp edi, 6\njbe short loc_13C9\nmovq xmm1, qword ptr [rbp+rcx+0]\nmovq xmm0, qword ptr [r12+rcx]\nmovq xmm2, qword ptr cs:xmmword_20B0\npcmpeqb xmm0, xmm1\nmovq xmm1, qword ptr cs:xmmword_20A0\npand xmm1, xmm0\npandn xmm0, xmm2\npor xmm0, xmm1\nmovq qword ptr [rdx+rcx], xmm0\nmov ecx, esi\nand ecx, 0FFFFFFF8h\nadd eax, ecx\nand esi, 7\njz loc_1499\nloc_13C9:\nmovsxd rcx, eax\nmovzx edi, byte ptr [rbp+rcx+0]\ncmp [r12+rcx], dil\nsetnz sil\nadd esi, 30h ; '0'\nmov [rdx+rcx], sil\nlea ecx, [rax+1]\ncmp ebx, ecx\njle loc_1499\nmovsxd rcx, ecx\nmovzx edi, byte ptr [rbp+rcx+0]\ncmp [r12+rcx], dil\nsetnz sil\nadd esi, 30h ; '0'\nmov [rdx+rcx], sil\nlea ecx, [rax+2]\ncmp ebx, ecx\njle loc_1499\nmovsxd rcx, ecx\nmovzx edi, byte ptr [rbp+rcx+0]\ncmp [r12+rcx], dil\nsetnz sil\nadd esi, 30h ; '0'\nmov [rdx+rcx], sil\nlea ecx, [rax+3]\ncmp ebx, ecx\njle short loc_1499\nmovsxd rcx, ecx\nmovzx edi, byte ptr [rbp+rcx+0]\ncmp [r12+rcx], dil\nsetnz sil\nadd esi, 30h ; '0'\nmov [rdx+rcx], sil\nlea ecx, [rax+4]\ncmp ebx, ecx\njle short loc_1499\nmovsxd rcx, ecx\nmovzx edi, byte ptr [rbp+rcx+0]\ncmp [r12+rcx], dil\nsetnz sil\nadd esi, 30h ; '0'\nmov [rdx+rcx], sil\nlea ecx, [rax+5]\ncmp ebx, ecx\njle short loc_1499\nmovsxd rcx, ecx\nmovzx edi, byte ptr [rbp+rcx+0]\ncmp [r12+rcx], dil\nsetnz sil\nadd eax, 6\nadd esi, 30h ; '0'\nmov [rdx+rcx], sil\ncmp ebx, eax\njle short loc_1499\ncdqe\nmovzx edi, byte ptr [rbp+rax+0]\ncmp [r12+rax], dil\nsetnz cl\nadd ecx, 30h ; '0'\nmov [rdx+rax], cl\nloc_1499:\nmovsxd rbx, ebx\nmov byte ptr [rdx+rbx], 0\nloc_14A0:\npop rbx\nmov rax, rdx\npop rbp\npop r12\nretn\nloc_14A8:\nxor ecx, ecx\nxor eax, eax\njmp loc_137C", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1, const char *a2)\n{\n int v3; // ebx\n int v4; // eax\n _BYTE *v5; // rdx\n __m128i si128; // xmm3\n __m128i v7; // xmm2\n __int64 v8; // rax\n __m128i v9; // xmm0\n int v10; // eax\n __int64 v11; // rcx\n int v12; // esi\n __m128i v13; // xmm0\n int v14; // ecx\n int v15; // eax\n\n v3 = strlen(a1);\n v4 = strlen(a2);\n if ( v3 > v4 )\n v3 = v4;\n v5 = malloc(v3 + 1);\n if ( v5 )\n {\n if ( v3 > 0 )\n {\n if ( (unsigned int)(v3 - 1) <= 0xE )\n {\n v11 = 0LL;\n v10 = 0;\n goto LABEL_9;\n }\n si128 = _mm_load_si128((const __m128i *)&xmmword_20A0);\n v7 = _mm_load_si128((const __m128i *)&xmmword_20B0);\n v8 = 0LL;\n do\n {\n v9 = _mm_cmpeq_epi8(_mm_loadu_si128((const __m128i *)&a1[v8]), _mm_loadu_si128((const __m128i *)&a2[v8]));\n *(__m128i *)&v5[v8] = _mm_or_si128(_mm_andnot_si128(v9, v7), _mm_and_si128(si128, v9));\n v8 += 16LL;\n }\n while ( 16LL * ((unsigned int)v3 >> 4) != v8 );\n v10 = v3 & 0x7FFFFFF0;\n v11 = v3 & 0xFFFFFFF0;\n if ( v3 != (v3 & 0xFFFFFFF0) )\n {\nLABEL_9:\n v12 = v3 - v11;\n if ( (unsigned int)(v3 - v11 - 1) <= 6\n || (v13 = _mm_cmpeq_epi8(\n _mm_loadl_epi64((const __m128i *)&a1[v11]),\n _mm_loadl_epi64((const __m128i *)&a2[v11])),\n *(_QWORD *)&v5[v11] = _mm_or_si128(\n _mm_andnot_si128(v13, _mm_loadl_epi64((const __m128i *)&xmmword_20B0)),\n _mm_and_si128(_mm_loadl_epi64((const __m128i *)&xmmword_20A0), v13)).m128i_u64[0],\n v10 += v12 & 0xFFFFFFF8,\n (v12 & 7) != 0) )\n {\n v5[v10] = (a1[v10] != a2[v10]) + 48;\n if ( v3 > v10 + 1 )\n {\n v5[v10 + 1] = (a1[v10 + 1] != a2[v10 + 1]) + 48;\n if ( v3 > v10 + 2 )\n {\n v5[v10 + 2] = (a1[v10 + 2] != a2[v10 + 2]) + 48;\n if ( v3 > v10 + 3 )\n {\n v5[v10 + 3] = (a1[v10 + 3] != a2[v10 + 3]) + 48;\n if ( v3 > v10 + 4 )\n {\n v5[v10 + 4] = (a1[v10 + 4] != a2[v10 + 4]) + 48;\n v14 = v10 + 5;\n if ( v3 > v10 + 5 )\n {\n v15 = v10 + 6;\n v5[v14] = (a1[v14] != a2[v14]) + 48;\n if ( v3 > v15 )\n v5[v15] = (a1[v15] != a2[v15]) + 48;\n }\n }\n }\n }\n }\n }\n }\n }\n v5[v3] = 0;\n }\n return v5;\n}", + "ida_strip_asm": "sub_12D0:\nendbr64\npush r12\nmov r12, rdi\npush rbp\nmov rbp, rsi\npush rbx\ncall _strlen\nmov rdi, rbp; s\nmov rbx, rax\ncall _strlen\ncmp ebx, eax\ncmovg ebx, eax\nlea edi, [rbx+1]\nmovsxd rdi, edi; size\ncall _malloc\nmov rdx, rax\ntest rax, rax\njz loc_14A0\ntest ebx, ebx\njle loc_1499\nlea eax, [rbx-1]\ncmp eax, 0Eh\njbe loc_14A8\nmov ecx, ebx\nmovdqa xmm3, cs:xmmword_20A0\nmovdqa xmm2, cs:xmmword_20B0\nxor eax, eax\nshr ecx, 4\nshl rcx, 4\nnop dword ptr [rax+00000000h]\nloc_1340:\nmovdqu xmm0, xmmword ptr [r12+rax]\nmovdqu xmm4, xmmword ptr [rbp+rax+0]\nmovdqa xmm1, xmm3\npcmpeqb xmm0, xmm4\npand xmm1, xmm0\npandn xmm0, xmm2\npor xmm0, xmm1\nmovups xmmword ptr [rdx+rax], xmm0\nadd rax, 10h\ncmp rcx, rax\njnz short loc_1340\nmov eax, ebx\nand eax, 0FFFFFFF0h\nmov ecx, eax\ncmp ebx, eax\njz loc_1499\nloc_137C:\nmov esi, ebx\nsub esi, ecx\nlea edi, [rsi-1]\ncmp edi, 6\njbe short loc_13C9\nmovq xmm1, qword ptr [rbp+rcx+0]\nmovq xmm0, qword ptr [r12+rcx]\nmovq xmm2, qword ptr cs:xmmword_20B0\npcmpeqb xmm0, xmm1\nmovq xmm1, qword ptr cs:xmmword_20A0\npand xmm1, xmm0\npandn xmm0, xmm2\npor xmm0, xmm1\nmovq qword ptr [rdx+rcx], xmm0\nmov ecx, esi\nand ecx, 0FFFFFFF8h\nadd eax, ecx\nand esi, 7\njz loc_1499\nloc_13C9:\nmovsxd rcx, eax\nmovzx edi, byte ptr [rbp+rcx+0]\ncmp [r12+rcx], dil\nsetnz sil\nadd esi, 30h ; '0'\nmov [rdx+rcx], sil\nlea ecx, [rax+1]\ncmp ebx, ecx\njle loc_1499\nmovsxd rcx, ecx\nmovzx edi, byte ptr [rbp+rcx+0]\ncmp [r12+rcx], dil\nsetnz sil\nadd esi, 30h ; '0'\nmov [rdx+rcx], sil\nlea ecx, [rax+2]\ncmp ebx, ecx\njle loc_1499\nmovsxd rcx, ecx\nmovzx edi, byte ptr [rbp+rcx+0]\ncmp [r12+rcx], dil\nsetnz sil\nadd esi, 30h ; '0'\nmov [rdx+rcx], sil\nlea ecx, [rax+3]\ncmp ebx, ecx\njle short loc_1499\nmovsxd rcx, ecx\nmovzx edi, byte ptr [rbp+rcx+0]\ncmp [r12+rcx], dil\nsetnz sil\nadd esi, 30h ; '0'\nmov [rdx+rcx], sil\nlea ecx, [rax+4]\ncmp ebx, ecx\njle short loc_1499\nmovsxd rcx, ecx\nmovzx edi, byte ptr [rbp+rcx+0]\ncmp [r12+rcx], dil\nsetnz sil\nadd esi, 30h ; '0'\nmov [rdx+rcx], sil\nlea ecx, [rax+5]\ncmp ebx, ecx\njle short loc_1499\nmovsxd rcx, ecx\nmovzx edi, byte ptr [rbp+rcx+0]\ncmp [r12+rcx], dil\nsetnz sil\nadd eax, 6\nadd esi, 30h ; '0'\nmov [rdx+rcx], sil\ncmp ebx, eax\njle short loc_1499\ncdqe\nmovzx edi, byte ptr [rbp+rax+0]\ncmp [r12+rax], dil\nsetnz cl\nadd ecx, 30h ; '0'\nmov [rdx+rax], cl\nloc_1499:\nmovsxd rbx, ebx\nmov byte ptr [rdx+rbx], 0\nloc_14A0:\npop rbx\nmov rax, rdx\npop rbp\npop r12\nretn\nloc_14A8:\nxor ecx, ecx\nxor eax, eax\njmp loc_137C", + "ida_strip_pseudo": "_BYTE *__fastcall sub_12D0(const char *a1, const char *a2)\n{\n int v3; // ebx\n int v4; // eax\n _BYTE *v5; // rdx\n __m128i si128; // xmm3\n __m128i v7; // xmm2\n __int64 v8; // rax\n __m128i v9; // xmm0\n int v10; // eax\n __int64 v11; // rcx\n int v12; // esi\n __m128i v13; // xmm0\n int v14; // ecx\n int v15; // eax\n\n v3 = strlen(a1);\n v4 = strlen(a2);\n if ( v3 > v4 )\n v3 = v4;\n v5 = malloc(v3 + 1);\n if ( v5 )\n {\n if ( v3 > 0 )\n {\n if ( (unsigned int)(v3 - 1) <= 0xE )\n {\n v11 = 0LL;\n v10 = 0;\n goto LABEL_9;\n }\n si128 = _mm_load_si128((const __m128i *)&xmmword_20A0);\n v7 = _mm_load_si128((const __m128i *)&xmmword_20B0);\n v8 = 0LL;\n do\n {\n v9 = _mm_cmpeq_epi8(_mm_loadu_si128((const __m128i *)&a1[v8]), _mm_loadu_si128((const __m128i *)&a2[v8]));\n *(__m128i *)&v5[v8] = _mm_or_si128(_mm_andnot_si128(v9, v7), _mm_and_si128(si128, v9));\n v8 += 16LL;\n }\n while ( 16LL * ((unsigned int)v3 >> 4) != v8 );\n v10 = v3 & 0x7FFFFFF0;\n v11 = v3 & 0xFFFFFFF0;\n if ( v3 != (v3 & 0xFFFFFFF0) )\n {\nLABEL_9:\n v12 = v3 - v11;\n if ( (unsigned int)(v3 - v11 - 1) <= 6\n || (v13 = _mm_cmpeq_epi8(\n _mm_loadl_epi64((const __m128i *)&a1[v11]),\n _mm_loadl_epi64((const __m128i *)&a2[v11])),\n *(_QWORD *)&v5[v11] = _mm_or_si128(\n _mm_andnot_si128(v13, _mm_loadl_epi64((const __m128i *)&xmmword_20B0)),\n _mm_and_si128(_mm_loadl_epi64((const __m128i *)&xmmword_20A0), v13)).m128i_u64[0],\n v10 += v12 & 0xFFFFFFF8,\n (v12 & 7) != 0) )\n {\n v5[v10] = (a1[v10] != a2[v10]) + 48;\n if ( v3 > v10 + 1 )\n {\n v5[v10 + 1] = (a1[v10 + 1] != a2[v10 + 1]) + 48;\n if ( v3 > v10 + 2 )\n {\n v5[v10 + 2] = (a1[v10 + 2] != a2[v10 + 2]) + 48;\n if ( v3 > v10 + 3 )\n {\n v5[v10 + 3] = (a1[v10 + 3] != a2[v10 + 3]) + 48;\n if ( v3 > v10 + 4 )\n {\n v5[v10 + 4] = (a1[v10 + 4] != a2[v10 + 4]) + 48;\n v14 = v10 + 5;\n if ( v3 > v10 + 5 )\n {\n v15 = v10 + 6;\n v5[v14] = (a1[v14] != a2[v14]) + 48;\n if ( v3 > v15 )\n v5[v15] = (a1[v15] != a2[v15]) + 48;\n }\n }\n }\n }\n }\n }\n }\n }\n v5[v3] = 0;\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_12D0(const char *a1, const char *a2) {\n int v3;\n int v4;\n uint8_t *v5;\n __m128i si128;\n __m128i v7;\n long long v8;\n __m128i v9;\n int v10;\n long long v11;\n int v12;\n __m128i v13;\n int v14;\n int v15;\n v3 = strlen(a1);\n v4 = strlen(a2);\n if (v3 > v4) v3 = v4;\n v5 = malloc(v3 + 1);\n if (v5) {\n if (v3 > 0) {\n if ((unsigned int)(v3 - 1) <= 14) {\n v11 = 0LL;\n v10 = 0;\n goto LABEL_9;\n }\n si128 = _mm_load_si128((const __m128i *)&xmmword_20A0);\n v7 = _mm_load_si128((const __m128i *)&xmmword_20B0);\n v8 = 0LL;\n do {\n v9 = _mm_cmpeq_epi8(_mm_loadu_si128((const __m128i *)&a1[v8]),\n _mm_loadu_si128((const __m128i *)&a2[v8]));\n *(__m128i *)&v5[v8] =\n _mm_or_si128(_mm_andnot_si128(v9, v7), _mm_and_si128(si128, v9));\n v8 += 16LL;\n } while (16LL * ((unsigned int)v3 >> 4) != v8);\n v10 = v3 & 2147483632;\n v11 = v3 & 4294967280;\n if (v3 != (v3 & 4294967280)) {\n LABEL_9:\n v12 = v3 - v11;\n if ((unsigned int)(v3 - v11 - 1) <= 6 ||\n (v13 = _mm_cmpeq_epi8(_mm_loadl_epi64((const __m128i *)&a1[v11]),\n _mm_loadl_epi64((const __m128i *)&a2[v11])),\n *(uint64_t *)&v5[v11] =\n _mm_or_si128(\n _mm_andnot_si128(\n v13, _mm_loadl_epi64((const __m128i *)&xmmword_20B0)),\n _mm_and_si128(\n _mm_loadl_epi64((const __m128i *)&xmmword_20A0), v13))\n .m128i_u64[0],\n v10 += v12 & 4294967288, (v12 & 7) != 0)) {\n v5[v10] = (a1[v10] != a2[v10]) + 48;\n if (v3 > v10 + 1) {\n v5[v10 + 1] = (a1[v10 + 1] != a2[v10 + 1]) + 48;\n if (v3 > v10 + 2) {\n v5[v10 + 2] = (a1[v10 + 2] != a2[v10 + 2]) + 48;\n if (v3 > v10 + 3) {\n v5[v10 + 3] = (a1[v10 + 3] != a2[v10 + 3]) + 48;\n if (v3 > v10 + 4) {\n v5[v10 + 4] = (a1[v10 + 4] != a2[v10 + 4]) + 48;\n v14 = v10 + 5;\n if (v3 > v10 + 5) {\n v15 = v10 + 6;\n v5[v14] = (a1[v14] != a2[v14]) + 48;\n if (v3 > v15) v5[v15] = (a1[v15] != a2[v15]) + 48;\n }\n }\n }\n }\n }\n }\n }\n }\n v5[v3] = 0;\n }\n return v5;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1, const char *a2) {\n int v3;\n int v4;\n uint8_t *v5;\n __m128i si128;\n __m128i v7;\n long long v8;\n __m128i v9;\n int v10;\n long long v11;\n int v12;\n __m128i v13;\n int v14;\n int v15;\n v3 = strlen(a1);\n v4 = strlen(a2);\n if (v3 > v4) v3 = v4;\n v5 = malloc(v3 + 1);\n if (v5) {\n if (v3 > 0) {\n if ((unsigned int)(v3 - 1) <= 14) {\n v11 = 0LL;\n v10 = 0;\n goto LABEL_9;\n }\n si128 = _mm_load_si128((const __m128i *)&xmmword_20A0);\n v7 = _mm_load_si128((const __m128i *)&xmmword_20B0);\n v8 = 0LL;\n do {\n v9 = _mm_cmpeq_epi8(_mm_loadu_si128((const __m128i *)&a1[v8]),\n _mm_loadu_si128((const __m128i *)&a2[v8]));\n *(__m128i *)&v5[v8] =\n _mm_or_si128(_mm_andnot_si128(v9, v7), _mm_and_si128(si128, v9));\n v8 += 16LL;\n } while (16LL * ((unsigned int)v3 >> 4) != v8);\n v10 = v3 & 2147483632;\n v11 = v3 & 4294967280;\n if (v3 != (v3 & 4294967280)) {\n LABEL_9:\n v12 = v3 - v11;\n if ((unsigned int)(v3 - v11 - 1) <= 6 ||\n (v13 = _mm_cmpeq_epi8(_mm_loadl_epi64((const __m128i *)&a1[v11]),\n _mm_loadl_epi64((const __m128i *)&a2[v11])),\n *(uint64_t *)&v5[v11] =\n _mm_or_si128(\n _mm_andnot_si128(\n v13, _mm_loadl_epi64((const __m128i *)&xmmword_20B0)),\n _mm_and_si128(\n _mm_loadl_epi64((const __m128i *)&xmmword_20A0), v13))\n .m128i_u64[0],\n v10 += v12 & 4294967288, (v12 & 7) != 0)) {\n v5[v10] = (a1[v10] != a2[v10]) + 48;\n if (v3 > v10 + 1) {\n v5[v10 + 1] = (a1[v10 + 1] != a2[v10 + 1]) + 48;\n if (v3 > v10 + 2) {\n v5[v10 + 2] = (a1[v10 + 2] != a2[v10 + 2]) + 48;\n if (v3 > v10 + 3) {\n v5[v10 + 3] = (a1[v10 + 3] != a2[v10 + 3]) + 48;\n if (v3 > v10 + 4) {\n v5[v10 + 4] = (a1[v10 + 4] != a2[v10 + 4]) + 48;\n v14 = v10 + 5;\n if (v3 > v10 + 5) {\n v15 = v10 + 6;\n v5[v14] = (a1[v14] != a2[v14]) + 48;\n if (v3 > v15) v5[v15] = (a1[v15] != a2[v15]) + 48;\n }\n }\n }\n }\n }\n }\n }\n }\n v5[v3] = 0;\n }\n return v5;\n}" + }, + { + "index": "HumanEval-C-12", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "char *func0(char **strings, int count) {\n char *out = \"\";\n int longest_length = 0;\n for (int i = 0; i < count; i++) {\n int current_length = strlen(strings[i]);\n if (current_length > longest_length) {\n out = strings[i];\n longest_length = current_length;\n }\n }\n return out;\n}", + "test": "#include \n#include \n#include \n\nint main() {\n char *empty_array[] = {\"\"};\n char *array1[] = {\"x\", \"y\", \"z\"};\n char *array2[] = {\"x\", \"yyy\", \"zzzz\", \"www\", \"kkkk\", \"abc\"};\n\n assert(strcmp(func0(empty_array, 0), \"\") == 0);\n assert(strcmp(func0(array1, 3), \"x\") == 0);\n assert(strcmp(func0(array2, 6), \"zzzz\") == 0);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nlea rax, unk_2008\nmov [rbp+var_8], rax\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\njmp short loc_1226\nloc_11D7:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_C], eax\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_14]\njle short loc_1222\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov [rbp+var_8], rax\nmov eax, [rbp+var_C]\nmov [rbp+var_14], eax\nloc_1222:\nadd [rbp+var_10], 1\nloc_1226:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_2C]\njl short loc_11D7\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "void *__fastcall func0(__int64 a1, int a2)\n{\n int v3; // [rsp+1Ch] [rbp-14h]\n int i; // [rsp+20h] [rbp-10h]\n int v5; // [rsp+24h] [rbp-Ch]\n void *v6; // [rsp+28h] [rbp-8h]\n\n v6 = &unk_2008;\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v5 = strlen(*(const char **)(8LL * i + a1));\n if ( v5 > v3 )\n {\n v6 = *(void **)(8LL * i + a1);\n v3 = v5;\n }\n }\n return v6;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nlea rax, unk_2008\nmov [rbp+var_8], rax\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\njmp short loc_1226\nloc_11D7:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_C], eax\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_14]\njle short loc_1222\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov [rbp+var_8], rax\nmov eax, [rbp+var_C]\nmov [rbp+var_14], eax\nloc_1222:\nadd [rbp+var_10], 1\nloc_1226:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_2C]\njl short loc_11D7\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "void *__fastcall sub_11A9(__int64 a1, int a2)\n{\n int v3; // [rsp+1Ch] [rbp-14h]\n int i; // [rsp+20h] [rbp-10h]\n int v5; // [rsp+24h] [rbp-Ch]\n void *v6; // [rsp+28h] [rbp-8h]\n\n v6 = &unk_2008;\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v5 = strlen(*(const char **)(8LL * i + a1));\n if ( v5 > v3 )\n {\n v6 = *(void **)(8LL * i + a1);\n v3 = v5;\n }\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_11A9(long long a1, int a2) {\n int v3;\n int i;\n int v5;\n void *v6;\n v6 = &unk_2008;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n v5 = strlen(*(const char **)(8LL * i + a1));\n if (v5 > v3) {\n v6 = *(void **)(8LL * i + a1);\n v3 = v5;\n }\n }\n return v6;\n}", + "ida_pseudo_norm": "void *func0(long long a1, int a2) {\n int v3;\n int i;\n int v5;\n void *v6;\n v6 = &unk_2008;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n v5 = strlen(*(const char **)(8LL * i + a1));\n if (v5 > v3) {\n v6 = *(void **)(8LL * i + a1);\n v3 = v5;\n }\n }\n return v6;\n}" + }, + { + "index": "HumanEval-C-12", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "char *func0(char **strings, int count) {\n char *out = \"\";\n int longest_length = 0;\n for (int i = 0; i < count; i++) {\n int current_length = strlen(strings[i]);\n if (current_length > longest_length) {\n out = strings[i];\n longest_length = current_length;\n }\n }\n return out;\n}", + "test": "#include \n#include \n#include \n\nint main() {\n char *empty_array[] = {\"\"};\n char *array1[] = {\"x\", \"y\", \"z\"};\n char *array2[] = {\"x\", \"yyy\", \"zzzz\", \"www\", \"kkkk\", \"abc\"};\n\n assert(strcmp(func0(empty_array, 0), \"\") == 0);\n assert(strcmp(func0(array1, 3), \"x\") == 0);\n assert(strcmp(func0(array2, 6), \"zzzz\") == 0);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nlea r13, aAbc+3; \"\"\ntest esi, esi\njle short loc_11EC\nmov rbx, rdi\nmovsxd rsi, esi\nlea r14, [rdi+rsi*8]\nmov ebp, 0\nloc_11CF:\nmov r12, [rbx]\nmov rdi, r12; s\ncall _strlen\ncmp eax, ebp\ncmovg ebp, eax\ncmovg r13, r12\nadd rbx, 8\ncmp rbx, r14\njnz short loc_11CF\nloc_11EC:\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "char *__fastcall func0(const char **a1, int a2)\n{\n char *v2; // r13\n const char **v3; // rbx\n int v4; // ebp\n const char *v5; // r12\n int v6; // eax\n\n v2 = \"\";\n if ( a2 > 0 )\n {\n v3 = a1;\n v4 = 0;\n do\n {\n v5 = *v3;\n v6 = strlen(*v3);\n if ( v6 > v4 )\n {\n v4 = v6;\n v2 = (char *)v5;\n }\n ++v3;\n }\n while ( v3 != &a1[a2] );\n }\n return v2;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nlea r13, aAbc+3; \"\"\ntest esi, esi\njle short loc_11EC\nmov rbx, rdi\nmovsxd rsi, esi\nlea r14, [rdi+rsi*8]\nmov ebp, 0\nloc_11CF:\nmov r12, [rbx]\nmov rdi, r12; s\ncall _strlen\ncmp eax, ebp\ncmovg ebp, eax\ncmovg r13, r12\nadd rbx, 8\ncmp rbx, r14\njnz short loc_11CF\nloc_11EC:\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11A9(const char **a1, int a2)\n{\n char *v2; // r13\n const char **v3; // rbx\n int v4; // ebp\n const char *v5; // r12\n int v6; // eax\n\n v2 = \"\";\n if ( a2 > 0 )\n {\n v3 = a1;\n v4 = 0;\n do\n {\n v5 = *v3;\n v6 = strlen(*v3);\n if ( v6 > v4 )\n {\n v4 = v6;\n v2 = (char *)v5;\n }\n ++v3;\n }\n while ( v3 != &a1[a2] );\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11A9(const char **a1, int a2) {\n char *v2;\n const char **v3;\n int v4;\n const char *v5;\n int v6;\n v2 = \"\";\n if (a2 > 0) {\n v3 = a1;\n v4 = 0;\n do {\n v5 = *v3;\n v6 = strlen(*v3);\n if (v6 > v4) {\n v4 = v6;\n v2 = (char *)v5;\n }\n ++v3;\n } while (v3 != &a1[a2]);\n }\n return v2;\n}", + "ida_pseudo_norm": "char *func0(const char **a1, int a2) {\n char *v2;\n const char **v3;\n int v4;\n const char *v5;\n int v6;\n v2 = \"\";\n if (a2 > 0) {\n v3 = a1;\n v4 = 0;\n do {\n v5 = *v3;\n v6 = strlen(*v3);\n if (v6 > v4) {\n v4 = v6;\n v2 = (char *)v5;\n }\n ++v3;\n } while (v3 != &a1[a2]);\n }\n return v2;\n}" + }, + { + "index": "HumanEval-C-12", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "char *func0(char **strings, int count) {\n char *out = \"\";\n int longest_length = 0;\n for (int i = 0; i < count; i++) {\n int current_length = strlen(strings[i]);\n if (current_length > longest_length) {\n out = strings[i];\n longest_length = current_length;\n }\n }\n return out;\n}", + "test": "#include \n#include \n#include \n\nint main() {\n char *empty_array[] = {\"\"};\n char *array1[] = {\"x\", \"y\", \"z\"};\n char *array2[] = {\"x\", \"yyy\", \"zzzz\", \"www\", \"kkkk\", \"abc\"};\n\n assert(strcmp(func0(empty_array, 0), \"\") == 0);\n assert(strcmp(func0(array1, 3), \"x\") == 0);\n assert(strcmp(func0(array2, 6), \"zzzz\") == 0);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r14\nlea r14, aAbc+3; \"\"\npush r13\npush r12\npush rbp\npush rbx\ntest esi, esi\njle short loc_1365\nmovsxd rsi, esi\nmov rbx, rdi\nxor ebp, ebp\nlea r13, [rdi+rsi*8]\nnop dword ptr [rax+rax+00h]\nloc_1348:\nmov r12, [rbx]\nmov rdi, r12; s\ncall _strlen\ncmp eax, ebp\ncmovg ebp, eax\ncmovg r14, r12\nadd rbx, 8\ncmp rbx, r13\njnz short loc_1348\nloc_1365:\npop rbx\nmov rax, r14\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "char *__fastcall func0(const char **a1, int a2)\n{\n char *v2; // r14\n const char **v3; // rbx\n int v4; // ebp\n const char *v5; // r12\n int v6; // eax\n\n v2 = \"\";\n if ( a2 > 0 )\n {\n v3 = a1;\n v4 = 0;\n do\n {\n v5 = *v3;\n v6 = strlen(*v3);\n if ( v6 > v4 )\n {\n v4 = v6;\n v2 = (char *)v5;\n }\n ++v3;\n }\n while ( v3 != &a1[a2] );\n }\n return v2;\n}", + "ida_strip_asm": "sub_1320:\nendbr64\npush r14\nlea r14, aAbc+3; \"\"\npush r13\npush r12\npush rbp\npush rbx\ntest esi, esi\njle short loc_1365\nmovsxd rsi, esi\nmov rbx, rdi\nxor ebp, ebp\nlea r13, [rdi+rsi*8]\nnop dword ptr [rax+rax+00h]\nloc_1348:\nmov r12, [rbx]\nmov rdi, r12; s\ncall _strlen\ncmp eax, ebp\ncmovg ebp, eax\ncmovg r14, r12\nadd rbx, 8\ncmp rbx, r13\njnz short loc_1348\nloc_1365:\npop rbx\nmov rax, r14\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1320(const char **a1, int a2)\n{\n char *v2; // r14\n const char **v3; // rbx\n int v4; // ebp\n const char *v5; // r12\n int v6; // eax\n\n v2 = \"\";\n if ( a2 > 0 )\n {\n v3 = a1;\n v4 = 0;\n do\n {\n v5 = *v3;\n v6 = strlen(*v3);\n if ( v6 > v4 )\n {\n v4 = v6;\n v2 = (char *)v5;\n }\n ++v3;\n }\n while ( v3 != &a1[a2] );\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1320(const char **a1, int a2) {\n char *v2;\n const char **v3;\n int v4;\n const char *v5;\n int v6;\n v2 = \"\";\n if (a2 > 0) {\n v3 = a1;\n v4 = 0;\n do {\n v5 = *v3;\n v6 = strlen(*v3);\n if (v6 > v4) {\n v4 = v6;\n v2 = (char *)v5;\n }\n ++v3;\n } while (v3 != &a1[a2]);\n }\n return v2;\n}", + "ida_pseudo_norm": "char *func0(const char **a1, int a2) {\n char *v2;\n const char **v3;\n int v4;\n const char *v5;\n int v6;\n v2 = \"\";\n if (a2 > 0) {\n v3 = a1;\n v4 = 0;\n do {\n v5 = *v3;\n v6 = strlen(*v3);\n if (v6 > v4) {\n v4 = v6;\n v2 = (char *)v5;\n }\n ++v3;\n } while (v3 != &a1[a2]);\n }\n return v2;\n}" + }, + { + "index": "HumanEval-C-12", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "char *func0(char **strings, int count) {\n char *out = \"\";\n int longest_length = 0;\n for (int i = 0; i < count; i++) {\n int current_length = strlen(strings[i]);\n if (current_length > longest_length) {\n out = strings[i];\n longest_length = current_length;\n }\n }\n return out;\n}", + "test": "#include \n#include \n#include \n\nint main() {\n char *empty_array[] = {\"\"};\n char *array1[] = {\"x\", \"y\", \"z\"};\n char *array2[] = {\"x\", \"yyy\", \"zzzz\", \"www\", \"kkkk\", \"abc\"};\n\n assert(strcmp(func0(empty_array, 0), \"\") == 0);\n assert(strcmp(func0(array1, 3), \"x\") == 0);\n assert(strcmp(func0(array2, 6), \"zzzz\") == 0);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r14\nlea r14, unk_2004\npush r13\npush r12\npush rbp\npush rbx\ntest esi, esi\njle short loc_11A5\nmovsxd rsi, esi\nmov rbx, rdi\nxor ebp, ebp\nlea r13, [rdi+rsi*8]\nnop dword ptr [rax+rax+00h]\nloc_1188:\nmov r12, [rbx]\nmov rdi, r12; s\ncall _strlen\ncmp eax, ebp\ncmovg ebp, eax\ncmovg r14, r12\nadd rbx, 8\ncmp rbx, r13\njnz short loc_1188\nloc_11A5:\npop rbx\nmov rax, r14\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "const char *__fastcall func0(const char **a1, int a2)\n{\n const char *v2; // r14\n const char **v3; // rbx\n int v4; // ebp\n const char *v5; // r12\n int v6; // eax\n\n v2 = (const char *)&unk_2004;\n if ( a2 > 0 )\n {\n v3 = a1;\n v4 = 0;\n do\n {\n v5 = *v3;\n v6 = strlen(*v3);\n if ( v6 > v4 )\n {\n v4 = v6;\n v2 = v5;\n }\n ++v3;\n }\n while ( v3 != &a1[a2] );\n }\n return v2;\n}", + "ida_strip_asm": "sub_1160:\nendbr64\npush r14\nlea r14, unk_2004\npush r13\npush r12\npush rbp\npush rbx\ntest esi, esi\njle short loc_11A5\nmovsxd rsi, esi\nmov rbx, rdi\nxor ebp, ebp\nlea r13, [rdi+rsi*8]\nnop dword ptr [rax+rax+00h]\nloc_1188:\nmov r12, [rbx]\nmov rdi, r12; s\ncall _strlen\ncmp eax, ebp\ncmovg ebp, eax\ncmovg r14, r12\nadd rbx, 8\ncmp rbx, r13\njnz short loc_1188\nloc_11A5:\npop rbx\nmov rax, r14\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1160(const char **a1, int a2)\n{\n const char *v2; // r14\n const char **v3; // rbx\n int v4; // ebp\n const char *v5; // r12\n int v6; // eax\n\n v2 = (const char *)&unk_2004;\n if ( a2 > 0 )\n {\n v3 = a1;\n v4 = 0;\n do\n {\n v5 = *v3;\n v6 = strlen(*v3);\n if ( v6 > v4 )\n {\n v4 = v6;\n v2 = v5;\n }\n ++v3;\n }\n while ( v3 != &a1[a2] );\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1160(const char **a1, int a2) {\n const char *v2;\n const char **v3;\n int v4;\n const char *v5;\n int v6;\n v2 = (const char *)&unk_2004;\n if (a2 > 0) {\n v3 = a1;\n v4 = 0;\n do {\n v5 = *v3;\n v6 = strlen(*v3);\n if (v6 > v4) {\n v4 = v6;\n v2 = v5;\n }\n ++v3;\n } while (v3 != &a1[a2]);\n }\n return v2;\n}", + "ida_pseudo_norm": "const char *func0(const char **a1, int a2) {\n const char *v2;\n const char **v3;\n int v4;\n const char *v5;\n int v6;\n v2 = (const char *)&unk_2004;\n if (a2 > 0) {\n v3 = a1;\n v4 = 0;\n do {\n v5 = *v3;\n v6 = strlen(*v3);\n if (v6 > v4) {\n v4 = v6;\n v2 = v5;\n }\n ++v3;\n } while (v3 != &a1[a2]);\n }\n return v2;\n}" + }, + { + "index": "HumanEval-C-13", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int a, int b) {\n while (b != 0) {\n int m = a % b;\n a = b;\n b = m;\n }\n return a;\n}", + "test": "#include \n\nint main() {\n assert(func0(3, 7) == 1);\n assert(func0(10, 15) == 5);\n assert(func0(49, 14) == 7);\n assert(func0(144, 60) == 12);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\njmp short loc_116F\nloc_1159:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_18]\nmov [rbp+var_4], edx\nmov eax, [rbp+var_18]\nmov [rbp+var_14], eax\nmov eax, [rbp+var_4]\nmov [rbp+var_18], eax\nloc_116F:\ncmp [rbp+var_18], 0\njnz short loc_1159\nmov eax, [rbp+var_14]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n int v5; // [rsp+14h] [rbp-4h]\n\n while ( a2 )\n {\n v5 = a1 % a2;\n a1 = a2;\n a2 = v5;\n }\n return (unsigned int)a1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\njmp short loc_116F\nloc_1159:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_18]\nmov [rbp+var_4], edx\nmov eax, [rbp+var_18]\nmov [rbp+var_14], eax\nmov eax, [rbp+var_4]\nmov [rbp+var_18], eax\nloc_116F:\ncmp [rbp+var_18], 0\njnz short loc_1159\nmov eax, [rbp+var_14]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2)\n{\n int v5; // [rsp+14h] [rbp-4h]\n\n while ( a2 )\n {\n v5 = a1 % a2;\n a1 = a2;\n a2 = v5;\n }\n return (unsigned int)a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2) {\n int v5;\n while (a2) {\n v5 = a1 % a2;\n a1 = a2;\n a2 = v5;\n }\n return (unsigned int)a1;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n int v5;\n while (a2) {\n v5 = a1 % a2;\n a1 = a2;\n a2 = v5;\n }\n return (unsigned int)a1;\n}" + }, + { + "index": "HumanEval-C-14", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char **func0(const char *str, int *count) {\n int len = strlen(str);\n char **out = malloc(len * sizeof(char *));\n char *current = malloc(len + 1);\n current[0] = '\\0';\n for (int i = 0; i < len; ++i) {\n size_t current_len = strlen(current);\n current = realloc(current, current_len + 2);\n current[current_len] = str[i];\n current[current_len + 1] = '\\0';\n out[i] = malloc(strlen(current) + 1);\n strcpy(out[i], current);\n }\n free(current);\n *count = len;\n return out;\n}", + "test": "#include \n#include \n\nint issame(char **a, int a_size, char **b, int b_size) {\n if (a_size != b_size) return 0;\n for (int i = 0; i < a_size; i++) {\n if (strcmp(a[i], b[i]) != 0) return 0;\n }\n return 1;\n}\n\nvoid free_prefixes(char **prefixes, int count) {\n for (int i = 0; i < count; i++) {\n free(prefixes[i]);\n }\n free(prefixes);\n}\n\nint main() {\n int count;\n char **result;\n \n result = func0(\"\", &count);\n assert(issame(result, 0, NULL, 0));\n free_prefixes(result, count);\n\n char *expected1[] = {\"a\", \"as\", \"asd\", \"asdf\", \"asdfg\", \"asdfgh\"};\n result = func0(\"asdfgh\", &count);\n assert(issame(result, count, expected1, 6));\n free_prefixes(result, count);\n\n char *expected2[] = {\"W\", \"WW\", \"WWW\"};\n result = func0(\"WWW\", &count);\n assert(issame(result, count, expected2, 3));\n free_prefixes(result, count);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+s], rdi\nmov [rbp+var_40], rsi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_2C], eax\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_20], rax\nmov eax, [rbp+var_2C]\nadd eax, 1\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+src], rax\nmov rax, [rbp+src]\nmov byte ptr [rax], 0\nmov [rbp+var_30], 0\njmp loc_133E\nloc_1289:\nmov rax, [rbp+src]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_18], rax\nmov rax, [rbp+var_18]\nlea rdx, [rax+2]\nmov rax, [rbp+src]\nmov rsi, rdx; size\nmov rdi, rax; ptr\ncall _realloc\nmov [rbp+src], rax\nmov eax, [rbp+var_30]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmov rcx, [rbp+src]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmovzx eax, byte ptr [rax]\nmov [rdx], al\nmov rax, [rbp+var_18]\nlea rdx, [rax+1]\nmov rax, [rbp+src]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+src]\nmov rdi, rax; s\ncall _strlen\nadd rax, 1\nmov edx, [rbp+var_30]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_20]\nlea rbx, [rcx+rdx]\nmov rdi, rax; size\ncall _malloc\nmov [rbx], rax\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov rax, [rax]\nmov rdx, [rbp+src]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\nadd [rbp+var_30], 1\nloc_133E:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_2C]\njl loc_1289\nmov rax, [rbp+src]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_40]\nmov edx, [rbp+var_2C]\nmov [rax], edx\nmov rax, [rbp+var_20]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(const char *a1, _DWORD *a2)\n{\n size_t v2; // rax\n int i; // [rsp+10h] [rbp-30h]\n int v5; // [rsp+14h] [rbp-2Ch]\n char *src; // [rsp+18h] [rbp-28h]\n _QWORD *v7; // [rsp+20h] [rbp-20h]\n size_t v8; // [rsp+28h] [rbp-18h]\n\n v5 = strlen(a1);\n v7 = malloc(8LL * v5);\n src = (char *)malloc(v5 + 1);\n *src = 0;\n for ( i = 0; i < v5; ++i )\n {\n v8 = strlen(src);\n src = (char *)realloc(src, v8 + 2);\n src[v8] = a1[i];\n src[v8 + 1] = 0;\n v2 = strlen(src);\n v7[i] = malloc(v2 + 1);\n strcpy((char *)v7[i], src);\n }\n free(src);\n *a2 = v5;\n return v7;\n}", + "ida_strip_asm": "sub_1229:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+s], rdi\nmov [rbp+var_40], rsi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_2C], eax\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_20], rax\nmov eax, [rbp+var_2C]\nadd eax, 1\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+src], rax\nmov rax, [rbp+src]\nmov byte ptr [rax], 0\nmov [rbp+var_30], 0\njmp loc_133E\nloc_1289:\nmov rax, [rbp+src]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_18], rax\nmov rax, [rbp+var_18]\nlea rdx, [rax+2]\nmov rax, [rbp+src]\nmov rsi, rdx; size\nmov rdi, rax; ptr\ncall _realloc\nmov [rbp+src], rax\nmov eax, [rbp+var_30]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmov rcx, [rbp+src]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmovzx eax, byte ptr [rax]\nmov [rdx], al\nmov rax, [rbp+var_18]\nlea rdx, [rax+1]\nmov rax, [rbp+src]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+src]\nmov rdi, rax; s\ncall _strlen\nadd rax, 1\nmov edx, [rbp+var_30]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_20]\nlea rbx, [rcx+rdx]\nmov rdi, rax; size\ncall _malloc\nmov [rbx], rax\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov rax, [rax]\nmov rdx, [rbp+src]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\nadd [rbp+var_30], 1\nloc_133E:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_2C]\njl loc_1289\nmov rax, [rbp+src]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_40]\nmov edx, [rbp+var_2C]\nmov [rax], edx\nmov rax, [rbp+var_20]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1229(const char *a1, _DWORD *a2)\n{\n size_t v2; // rax\n int i; // [rsp+10h] [rbp-30h]\n int v5; // [rsp+14h] [rbp-2Ch]\n char *src; // [rsp+18h] [rbp-28h]\n _QWORD *v7; // [rsp+20h] [rbp-20h]\n size_t v8; // [rsp+28h] [rbp-18h]\n\n v5 = strlen(a1);\n v7 = malloc(8LL * v5);\n src = (char *)malloc(v5 + 1);\n *src = 0;\n for ( i = 0; i < v5; ++i )\n {\n v8 = strlen(src);\n src = (char *)realloc(src, v8 + 2);\n src[v8] = a1[i];\n src[v8 + 1] = 0;\n v2 = strlen(src);\n v7[i] = malloc(v2 + 1);\n strcpy((char *)v7[i], src);\n }\n free(src);\n *a2 = v5;\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1229(const char *a1, uint32_t *a2) {\n unsigned int v2;\n int i;\n int v5;\n char *src;\n uint64_t *v7;\n unsigned int v8;\n v5 = strlen(a1);\n v7 = malloc(8LL * v5);\n src = (char *)malloc(v5 + 1);\n *src = 0;\n for (i = 0; i < v5; ++i) {\n v8 = strlen(src);\n src = (char *)realloc(src, v8 + 2);\n src[v8] = a1[i];\n src[v8 + 1] = 0;\n v2 = strlen(src);\n v7[i] = malloc(v2 + 1);\n strcpy((char *)v7[i], src);\n }\n free(src);\n *a2 = v5;\n return v7;\n}", + "ida_pseudo_norm": "uint64_t *func0(const char *a1, uint32_t *a2) {\n unsigned int v2;\n int i;\n int v5;\n char *src;\n uint64_t *v7;\n unsigned int v8;\n v5 = strlen(a1);\n v7 = malloc(8LL * v5);\n src = (char *)malloc(v5 + 1);\n *src = 0;\n for (i = 0; i < v5; ++i) {\n v8 = strlen(src);\n src = (char *)realloc(src, v8 + 2);\n src[v8] = a1[i];\n src[v8 + 1] = 0;\n v2 = strlen(src);\n v7[i] = malloc(v2 + 1);\n strcpy((char *)v7[i], src);\n }\n free(src);\n *a2 = v5;\n return v7;\n}" + }, + { + "index": "HumanEval-C-14", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char **func0(const char *str, int *count) {\n int len = strlen(str);\n char **out = malloc(len * sizeof(char *));\n char *current = malloc(len + 1);\n current[0] = '\\0';\n for (int i = 0; i < len; ++i) {\n size_t current_len = strlen(current);\n current = realloc(current, current_len + 2);\n current[current_len] = str[i];\n current[current_len + 1] = '\\0';\n out[i] = malloc(strlen(current) + 1);\n strcpy(out[i], current);\n }\n free(current);\n *count = len;\n return out;\n}", + "test": "#include \n#include \n\nint issame(char **a, int a_size, char **b, int b_size) {\n if (a_size != b_size) return 0;\n for (int i = 0; i < a_size; i++) {\n if (strcmp(a[i], b[i]) != 0) return 0;\n }\n return 1;\n}\n\nvoid free_prefixes(char **prefixes, int count) {\n for (int i = 0; i < count; i++) {\n free(prefixes[i]);\n }\n free(prefixes);\n}\n\nint main() {\n int count;\n char **result;\n \n result = func0(\"\", &count);\n assert(issame(result, 0, NULL, 0));\n free_prefixes(result, count);\n\n char *expected1[] = {\"a\", \"as\", \"asd\", \"asdf\", \"asdfg\", \"asdfgh\"};\n result = func0(\"asdfgh\", &count);\n assert(issame(result, count, expected1, 6));\n free_prefixes(result, count);\n\n char *expected2[] = {\"W\", \"WW\", \"WWW\"};\n result = func0(\"WWW\", &count);\n assert(issame(result, count, expected2, 3));\n free_prefixes(result, count);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov r14, rdi\nmov [rsp+48h+var_48], rsi\ncall _strlen\nmov r15, rax\nmov [rsp+48h+var_40], rax\nmovsxd rdi, eax\nshl rdi, 3; size\ncall _malloc\nmov r13, rax\nlea edi, [r15+1]\nmovsxd rdi, edi; size\ncall _malloc\nmov rbx, rax\nmov byte ptr [rax], 0\ntest r15d, r15d\njle short loc_12D9\nlea r15d, [r15-1]\nmov r12d, 0\nloc_127F:\nmov rdi, rbx; s\ncall _strlen\nmov rbp, rax\nlea rsi, [rax+2]; size\nmov rdi, rbx; ptr\ncall _realloc\nmov rbx, rax\nmovzx eax, byte ptr [r14+r12]\nmov [rbx+rbp], al\nmov byte ptr [rbx+rbp+1], 0\nmov rdi, rbx; s\ncall _strlen\nlea rbp, [rax+1]\nmov rdi, rbp; size\ncall _malloc\nmov rdi, rax\nmov [r13+r12*8+0], rax\nmov rdx, rbp\nmov rsi, rbx\ncall ___strcpy_chk\nmov rax, r12\nadd r12, 1\ncmp rax, r15\njnz short loc_127F\nloc_12D9:\nmov rdi, rbx; ptr\ncall _free\nmov rax, [rsp+48h+var_48]\nmov ecx, dword ptr [rsp+48h+var_40]\nmov [rax], ecx\nmov rax, r13\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(const char *a1, int *a2)\n{\n int v2; // r15d\n _QWORD *v3; // r13\n char *v4; // rbx\n __int64 v5; // r15\n __int64 v6; // r12\n size_t v7; // rbp\n size_t v8; // rbp\n void *v9; // rax\n __int64 v10; // rax\n int v12; // [rsp+8h] [rbp-40h]\n\n v2 = strlen(a1);\n v12 = v2;\n v3 = malloc(8LL * v2);\n v4 = (char *)malloc(v2 + 1);\n *v4 = 0;\n if ( v2 > 0 )\n {\n v5 = (unsigned int)(v2 - 1);\n v6 = 0LL;\n do\n {\n v7 = strlen(v4);\n v4 = (char *)realloc(v4, v7 + 2);\n *(_WORD *)&v4[v7] = (unsigned __int8)a1[v6];\n v8 = strlen(v4) + 1;\n v9 = malloc(v8);\n v3[v6] = v9;\n __strcpy_chk(v9, v4, v8);\n v10 = v6++;\n }\n while ( v10 != v5 );\n }\n free(v4);\n *a2 = v12;\n return v3;\n}", + "ida_strip_asm": "sub_1229:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov r14, rdi\nmov [rsp+48h+var_48], rsi\ncall _strlen\nmov r15, rax\nmov [rsp+48h+var_40], rax\nmovsxd rdi, eax\nshl rdi, 3; size\ncall _malloc\nmov r13, rax\nlea edi, [r15+1]\nmovsxd rdi, edi; size\ncall _malloc\nmov rbx, rax\nmov byte ptr [rax], 0\ntest r15d, r15d\njle short loc_12D9\nlea r15d, [r15-1]\nmov r12d, 0\nloc_127F:\nmov rdi, rbx; s\ncall _strlen\nmov rbp, rax\nlea rsi, [rax+2]; size\nmov rdi, rbx; ptr\ncall _realloc\nmov rbx, rax\nmovzx eax, byte ptr [r14+r12]\nmov [rbx+rbp], al\nmov byte ptr [rbx+rbp+1], 0\nmov rdi, rbx; s\ncall _strlen\nlea rbp, [rax+1]\nmov rdi, rbp; size\ncall _malloc\nmov rdi, rax\nmov [r13+r12*8+0], rax\nmov rdx, rbp\nmov rsi, rbx\ncall ___strcpy_chk\nmov rax, r12\nadd r12, 1\ncmp rax, r15\njnz short loc_127F\nloc_12D9:\nmov rdi, rbx; ptr\ncall _free\nmov rax, [rsp+48h+var_48]\nmov ecx, dword ptr [rsp+48h+var_40]\nmov [rax], ecx\nmov rax, r13\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1229(const char *a1, int *a2)\n{\n int v2; // r15d\n _QWORD *v3; // r13\n char *v4; // rbx\n __int64 v5; // r15\n __int64 v6; // r12\n size_t v7; // rbp\n size_t v8; // rbp\n void *v9; // rax\n __int64 v10; // rax\n int v12; // [rsp+8h] [rbp-40h]\n\n v2 = strlen(a1);\n v12 = v2;\n v3 = malloc(8LL * v2);\n v4 = (char *)malloc(v2 + 1);\n *v4 = 0;\n if ( v2 > 0 )\n {\n v5 = (unsigned int)(v2 - 1);\n v6 = 0LL;\n do\n {\n v7 = strlen(v4);\n v4 = (char *)realloc(v4, v7 + 2);\n *(_WORD *)&v4[v7] = (unsigned __int8)a1[v6];\n v8 = strlen(v4) + 1;\n v9 = malloc(v8);\n v3[v6] = v9;\n __strcpy_chk(v9, v4, v8);\n v10 = v6++;\n }\n while ( v10 != v5 );\n }\n free(v4);\n *a2 = v12;\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1229(const char *a1, int *a2) {\n int v2;\n uint64_t *v3;\n char *v4;\n long long v5;\n long long v6;\n unsigned int v7;\n unsigned int v8;\n void *v9;\n long long v10;\n int v12;\n v2 = strlen(a1);\n v12 = v2;\n v3 = malloc(8LL * v2);\n v4 = (char *)malloc(v2 + 1);\n *v4 = 0;\n if (v2 > 0) {\n v5 = (unsigned int)(v2 - 1);\n v6 = 0LL;\n do {\n v7 = strlen(v4);\n v4 = (char *)realloc(v4, v7 + 2);\n *(unsigned short *)&v4[v7] = (unsigned char)a1[v6];\n v8 = strlen(v4) + 1;\n v9 = malloc(v8);\n v3[v6] = v9;\n __strcpy_chk(v9, v4, v8);\n v10 = v6++;\n } while (v10 != v5);\n }\n free(v4);\n *a2 = v12;\n return v3;\n}", + "ida_pseudo_norm": "uint64_t *func0(const char *a1, int *a2) {\n int v2;\n uint64_t *v3;\n char *v4;\n long long v5;\n long long v6;\n unsigned int v7;\n unsigned int v8;\n void *v9;\n long long v10;\n int v12;\n v2 = strlen(a1);\n v12 = v2;\n v3 = malloc(8LL * v2);\n v4 = (char *)malloc(v2 + 1);\n *v4 = 0;\n if (v2 > 0) {\n v5 = (unsigned int)(v2 - 1);\n v6 = 0LL;\n do {\n v7 = strlen(v4);\n v4 = (char *)realloc(v4, v7 + 2);\n *(unsigned short *)&v4[v7] = (unsigned char)a1[v6];\n v8 = strlen(v4) + 1;\n v9 = malloc(v8);\n v3[v6] = v9;\n __strcpy_chk(v9, v4, v8);\n v10 = v6++;\n } while (v10 != v5);\n }\n free(v4);\n *a2 = v12;\n return v3;\n}" + }, + { + "index": "HumanEval-C-14", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char **func0(const char *str, int *count) {\n int len = strlen(str);\n char **out = malloc(len * sizeof(char *));\n char *current = malloc(len + 1);\n current[0] = '\\0';\n for (int i = 0; i < len; ++i) {\n size_t current_len = strlen(current);\n current = realloc(current, current_len + 2);\n current[current_len] = str[i];\n current[current_len + 1] = '\\0';\n out[i] = malloc(strlen(current) + 1);\n strcpy(out[i], current);\n }\n free(current);\n *count = len;\n return out;\n}", + "test": "#include \n#include \n\nint issame(char **a, int a_size, char **b, int b_size) {\n if (a_size != b_size) return 0;\n for (int i = 0; i < a_size; i++) {\n if (strcmp(a[i], b[i]) != 0) return 0;\n }\n return 1;\n}\n\nvoid free_prefixes(char **prefixes, int count) {\n for (int i = 0; i < count; i++) {\n free(prefixes[i]);\n }\n free(prefixes);\n}\n\nint main() {\n int count;\n char **result;\n \n result = func0(\"\", &count);\n assert(issame(result, 0, NULL, 0));\n free_prefixes(result, count);\n\n char *expected1[] = {\"a\", \"as\", \"asd\", \"asdf\", \"asdfg\", \"asdfgh\"};\n result = func0(\"asdfgh\", &count);\n assert(issame(result, count, expected1, 6));\n free_prefixes(result, count);\n\n char *expected2[] = {\"W\", \"WW\", \"WWW\"};\n result = func0(\"WWW\", &count);\n assert(issame(result, count, expected2, 3));\n free_prefixes(result, count);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\nmov r13, rdi\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_48], rsi\ncall _strlen\nmovsxd rdi, eax\nmov r14, rax\nmov [rsp+48h+var_40], rax\nshl rdi, 3; size\ncall _malloc\nlea edi, [r14+1]\nmovsxd rdi, edi; size\nmov r12, rax\ncall _malloc\nmov byte ptr [rax], 0\nmov rbx, rax\ntest r14d, r14d\njle short loc_1527\nsub r14d, 1\nxor ebp, ebp\nnop word ptr [rax+rax+00h]\nloc_14C8:\nmov rdi, rbx; s\ncall _strlen\nmov rdi, rbx; ptr\nlea rsi, [rax+2]; size\nmov r15, rax\ncall _realloc\nmov rbx, rax\nmovzx eax, byte ptr [r13+rbp+0]\nmov byte ptr [rbx+r15+1], 0\nmov rdi, rbx; s\nmov [rbx+r15], al\ncall _strlen\nlea r15, [rax+1]\nmov rdi, r15; size\ncall _malloc\nmov rcx, r15\nmov rdx, r15\nmov rsi, rbx\nmov [r12+rbp*8], rax\nmov rdi, rax\ncall ___memcpy_chk\nmov rax, rbp\nadd rbp, 1\ncmp rax, r14\njnz short loc_14C8\nloc_1527:\nmov rdi, rbx; ptr\ncall _free\nmov rax, [rsp+48h+var_48]\nmov edx, dword ptr [rsp+48h+var_40]\nmov [rax], edx\nadd rsp, 18h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(const char *a1, int *a2)\n{\n int v2; // r14d\n _QWORD *v3; // r12\n char *v4; // rax\n char *v5; // rbx\n __int64 v6; // r14\n __int64 v7; // rbp\n size_t v8; // r15\n char v9; // al\n size_t v10; // r15\n void *v11; // rax\n __int64 v12; // rax\n int v14; // [rsp+8h] [rbp-40h]\n\n v2 = strlen(a1);\n v14 = v2;\n v3 = malloc(8LL * v2);\n v4 = (char *)malloc(v2 + 1);\n *v4 = 0;\n v5 = v4;\n if ( v2 > 0 )\n {\n v6 = (unsigned int)(v2 - 1);\n v7 = 0LL;\n do\n {\n v8 = strlen(v5);\n v5 = (char *)realloc(v5, v8 + 2);\n v9 = a1[v7];\n v5[v8 + 1] = 0;\n v5[v8] = v9;\n v10 = strlen(v5) + 1;\n v11 = malloc(v10);\n v3[v7] = v11;\n __memcpy_chk(v11, v5, v10, v10);\n v12 = v7++;\n }\n while ( v12 != v6 );\n }\n free(v5);\n *a2 = v14;\n return v3;\n}", + "ida_strip_asm": "sub_1470:\nendbr64\npush r15\npush r14\npush r13\nmov r13, rdi\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_48], rsi\ncall _strlen\nmovsxd rdi, eax\nmov r14, rax\nmov [rsp+48h+var_40], rax\nshl rdi, 3; size\ncall _malloc\nlea edi, [r14+1]\nmovsxd rdi, edi; size\nmov r12, rax\ncall _malloc\nmov byte ptr [rax], 0\nmov rbx, rax\ntest r14d, r14d\njle short loc_1527\nsub r14d, 1\nxor ebp, ebp\nnop word ptr [rax+rax+00h]\nloc_14C8:\nmov rdi, rbx; s\ncall _strlen\nmov rdi, rbx; ptr\nlea rsi, [rax+2]; size\nmov r15, rax\ncall _realloc\nmov rbx, rax\nmovzx eax, byte ptr [r13+rbp+0]\nmov byte ptr [rbx+r15+1], 0\nmov rdi, rbx; s\nmov [rbx+r15], al\ncall _strlen\nlea r15, [rax+1]\nmov rdi, r15; size\ncall _malloc\nmov rcx, r15\nmov rdx, r15\nmov rsi, rbx\nmov [r12+rbp*8], rax\nmov rdi, rax\ncall ___memcpy_chk\nmov rax, rbp\nadd rbp, 1\ncmp rax, r14\njnz short loc_14C8\nloc_1527:\nmov rdi, rbx; ptr\ncall _free\nmov rax, [rsp+48h+var_48]\nmov edx, dword ptr [rsp+48h+var_40]\nmov [rax], edx\nadd rsp, 18h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1470(const char *a1, int *a2)\n{\n int v2; // r14d\n _QWORD *v3; // r12\n char *v4; // rax\n char *v5; // rbx\n __int64 v6; // r14\n __int64 v7; // rbp\n size_t v8; // r15\n char v9; // al\n size_t v10; // r15\n void *v11; // rax\n __int64 v12; // rax\n int v14; // [rsp+8h] [rbp-40h]\n\n v2 = strlen(a1);\n v14 = v2;\n v3 = malloc(8LL * v2);\n v4 = (char *)malloc(v2 + 1);\n *v4 = 0;\n v5 = v4;\n if ( v2 > 0 )\n {\n v6 = (unsigned int)(v2 - 1);\n v7 = 0LL;\n do\n {\n v8 = strlen(v5);\n v5 = (char *)realloc(v5, v8 + 2);\n v9 = a1[v7];\n v5[v8 + 1] = 0;\n v5[v8] = v9;\n v10 = strlen(v5) + 1;\n v11 = malloc(v10);\n v3[v7] = v11;\n __memcpy_chk(v11, v5, v10, v10);\n v12 = v7++;\n }\n while ( v12 != v6 );\n }\n free(v5);\n *a2 = v14;\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1470(const char *a1, int *a2) {\n int v2;\n uint64_t *v3;\n char *v4;\n char *v5;\n long long v6;\n long long v7;\n unsigned int v8;\n char v9;\n unsigned int v10;\n void *v11;\n long long v12;\n int v14;\n v2 = strlen(a1);\n v14 = v2;\n v3 = malloc(8LL * v2);\n v4 = (char *)malloc(v2 + 1);\n *v4 = 0;\n v5 = v4;\n if (v2 > 0) {\n v6 = (unsigned int)(v2 - 1);\n v7 = 0LL;\n do {\n v8 = strlen(v5);\n v5 = (char *)realloc(v5, v8 + 2);\n v9 = a1[v7];\n v5[v8 + 1] = 0;\n v5[v8] = v9;\n v10 = strlen(v5) + 1;\n v11 = malloc(v10);\n v3[v7] = v11;\n __memcpy_chk(v11, v5, v10, v10);\n v12 = v7++;\n } while (v12 != v6);\n }\n free(v5);\n *a2 = v14;\n return v3;\n}", + "ida_pseudo_norm": "uint64_t *func0(const char *a1, int *a2) {\n int v2;\n uint64_t *v3;\n char *v4;\n char *v5;\n long long v6;\n long long v7;\n unsigned int v8;\n char v9;\n unsigned int v10;\n void *v11;\n long long v12;\n int v14;\n v2 = strlen(a1);\n v14 = v2;\n v3 = malloc(8LL * v2);\n v4 = (char *)malloc(v2 + 1);\n *v4 = 0;\n v5 = v4;\n if (v2 > 0) {\n v6 = (unsigned int)(v2 - 1);\n v7 = 0LL;\n do {\n v8 = strlen(v5);\n v5 = (char *)realloc(v5, v8 + 2);\n v9 = a1[v7];\n v5[v8 + 1] = 0;\n v5[v8] = v9;\n v10 = strlen(v5) + 1;\n v11 = malloc(v10);\n v3[v7] = v11;\n __memcpy_chk(v11, v5, v10, v10);\n v12 = v7++;\n } while (v12 != v6);\n }\n free(v5);\n *a2 = v14;\n return v3;\n}" + }, + { + "index": "HumanEval-C-14", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char **func0(const char *str, int *count) {\n int len = strlen(str);\n char **out = malloc(len * sizeof(char *));\n char *current = malloc(len + 1);\n current[0] = '\\0';\n for (int i = 0; i < len; ++i) {\n size_t current_len = strlen(current);\n current = realloc(current, current_len + 2);\n current[current_len] = str[i];\n current[current_len + 1] = '\\0';\n out[i] = malloc(strlen(current) + 1);\n strcpy(out[i], current);\n }\n free(current);\n *count = len;\n return out;\n}", + "test": "#include \n#include \n\nint issame(char **a, int a_size, char **b, int b_size) {\n if (a_size != b_size) return 0;\n for (int i = 0; i < a_size; i++) {\n if (strcmp(a[i], b[i]) != 0) return 0;\n }\n return 1;\n}\n\nvoid free_prefixes(char **prefixes, int count) {\n for (int i = 0; i < count; i++) {\n free(prefixes[i]);\n }\n free(prefixes);\n}\n\nint main() {\n int count;\n char **result;\n \n result = func0(\"\", &count);\n assert(issame(result, 0, NULL, 0));\n free_prefixes(result, count);\n\n char *expected1[] = {\"a\", \"as\", \"asd\", \"asdf\", \"asdfg\", \"asdfgh\"};\n result = func0(\"asdfgh\", &count);\n assert(issame(result, count, expected1, 6));\n free_prefixes(result, count);\n\n char *expected2[] = {\"W\", \"WW\", \"WWW\"};\n result = func0(\"WWW\", &count);\n assert(issame(result, count, expected2, 3));\n free_prefixes(result, count);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\nmov r13, rdi\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_48], rsi\ncall _strlen\nmovsxd rdi, eax\nmov r14, rax\nmov [rsp+48h+var_40], rax\nshl rdi, 3; size\ncall _malloc\nlea edi, [r14+1]\nmovsxd rdi, edi; size\nmov r12, rax\ncall _malloc\nmov byte ptr [rax], 0\nmov rbx, rax\ntest r14d, r14d\njle short loc_1527\nsub r14d, 1\nxor ebp, ebp\nnop word ptr [rax+rax+00h]\nloc_14C8:\nmov rdi, rbx; s\ncall _strlen\nmov rdi, rbx; ptr\nlea rsi, [rax+2]; size\nmov r15, rax\ncall _realloc\nmov rbx, rax\nmovzx eax, byte ptr [r13+rbp+0]\nmov byte ptr [rbx+r15+1], 0\nmov rdi, rbx; s\nmov [rbx+r15], al\ncall _strlen\nlea r15, [rax+1]\nmov rdi, r15; size\ncall _malloc\nmov rcx, r15\nmov rdx, r15\nmov rsi, rbx\nmov [r12+rbp*8], rax\nmov rdi, rax\ncall ___memcpy_chk\nmov rax, rbp\nadd rbp, 1\ncmp r14, rax\njnz short loc_14C8\nloc_1527:\nmov rdi, rbx; ptr\ncall _free\nmov rax, [rsp+48h+var_48]\nmov edx, dword ptr [rsp+48h+var_40]\nmov [rax], edx\nadd rsp, 18h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(const char *a1, int *a2)\n{\n int v2; // r14d\n _QWORD *v3; // r12\n char *v4; // rax\n char *v5; // rbx\n __int64 v6; // r14\n __int64 v7; // rbp\n size_t v8; // r15\n char v9; // al\n size_t v10; // r15\n void *v11; // rax\n __int64 v12; // rax\n int v14; // [rsp+8h] [rbp-40h]\n\n v2 = strlen(a1);\n v14 = v2;\n v3 = malloc(8LL * v2);\n v4 = (char *)malloc(v2 + 1);\n *v4 = 0;\n v5 = v4;\n if ( v2 > 0 )\n {\n v6 = (unsigned int)(v2 - 1);\n v7 = 0LL;\n do\n {\n v8 = strlen(v5);\n v5 = (char *)realloc(v5, v8 + 2);\n v9 = a1[v7];\n v5[v8 + 1] = 0;\n v5[v8] = v9;\n v10 = strlen(v5) + 1;\n v11 = malloc(v10);\n v3[v7] = v11;\n __memcpy_chk(v11, v5, v10, v10);\n v12 = v7++;\n }\n while ( v6 != v12 );\n }\n free(v5);\n *a2 = v14;\n return v3;\n}", + "ida_strip_asm": "sub_1470:\nendbr64\npush r15\npush r14\npush r13\nmov r13, rdi\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_48], rsi\ncall _strlen\nmovsxd rdi, eax\nmov r14, rax\nmov [rsp+48h+var_40], rax\nshl rdi, 3; size\ncall _malloc\nlea edi, [r14+1]\nmovsxd rdi, edi; size\nmov r12, rax\ncall _malloc\nmov byte ptr [rax], 0\nmov rbx, rax\ntest r14d, r14d\njle short loc_1527\nsub r14d, 1\nxor ebp, ebp\nnop word ptr [rax+rax+00h]\nloc_14C8:\nmov rdi, rbx; s\ncall _strlen\nmov rdi, rbx; ptr\nlea rsi, [rax+2]; size\nmov r15, rax\ncall _realloc\nmov rbx, rax\nmovzx eax, byte ptr [r13+rbp+0]\nmov byte ptr [rbx+r15+1], 0\nmov rdi, rbx; s\nmov [rbx+r15], al\ncall _strlen\nlea r15, [rax+1]\nmov rdi, r15; size\ncall _malloc\nmov rcx, r15\nmov rdx, r15\nmov rsi, rbx\nmov [r12+rbp*8], rax\nmov rdi, rax\ncall ___memcpy_chk\nmov rax, rbp\nadd rbp, 1\ncmp r14, rax\njnz short loc_14C8\nloc_1527:\nmov rdi, rbx; ptr\ncall _free\nmov rax, [rsp+48h+var_48]\nmov edx, dword ptr [rsp+48h+var_40]\nmov [rax], edx\nadd rsp, 18h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1470(const char *a1, int *a2)\n{\n int v2; // r14d\n _QWORD *v3; // r12\n char *v4; // rax\n char *v5; // rbx\n __int64 v6; // r14\n __int64 v7; // rbp\n size_t v8; // r15\n char v9; // al\n size_t v10; // r15\n void *v11; // rax\n __int64 v12; // rax\n int v14; // [rsp+8h] [rbp-40h]\n\n v2 = strlen(a1);\n v14 = v2;\n v3 = malloc(8LL * v2);\n v4 = (char *)malloc(v2 + 1);\n *v4 = 0;\n v5 = v4;\n if ( v2 > 0 )\n {\n v6 = (unsigned int)(v2 - 1);\n v7 = 0LL;\n do\n {\n v8 = strlen(v5);\n v5 = (char *)realloc(v5, v8 + 2);\n v9 = a1[v7];\n v5[v8 + 1] = 0;\n v5[v8] = v9;\n v10 = strlen(v5) + 1;\n v11 = malloc(v10);\n v3[v7] = v11;\n __memcpy_chk(v11, v5, v10, v10);\n v12 = v7++;\n }\n while ( v6 != v12 );\n }\n free(v5);\n *a2 = v14;\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1470(const char *a1, int *a2) {\n int v2;\n uint64_t *v3;\n char *v4;\n char *v5;\n long long v6;\n long long v7;\n unsigned int v8;\n char v9;\n unsigned int v10;\n void *v11;\n long long v12;\n int v14;\n v2 = strlen(a1);\n v14 = v2;\n v3 = malloc(8LL * v2);\n v4 = (char *)malloc(v2 + 1);\n *v4 = 0;\n v5 = v4;\n if (v2 > 0) {\n v6 = (unsigned int)(v2 - 1);\n v7 = 0LL;\n do {\n v8 = strlen(v5);\n v5 = (char *)realloc(v5, v8 + 2);\n v9 = a1[v7];\n v5[v8 + 1] = 0;\n v5[v8] = v9;\n v10 = strlen(v5) + 1;\n v11 = malloc(v10);\n v3[v7] = v11;\n __memcpy_chk(v11, v5, v10, v10);\n v12 = v7++;\n } while (v6 != v12);\n }\n free(v5);\n *a2 = v14;\n return v3;\n}", + "ida_pseudo_norm": "uint64_t *func0(const char *a1, int *a2) {\n int v2;\n uint64_t *v3;\n char *v4;\n char *v5;\n long long v6;\n long long v7;\n unsigned int v8;\n char v9;\n unsigned int v10;\n void *v11;\n long long v12;\n int v14;\n v2 = strlen(a1);\n v14 = v2;\n v3 = malloc(8LL * v2);\n v4 = (char *)malloc(v2 + 1);\n *v4 = 0;\n v5 = v4;\n if (v2 > 0) {\n v6 = (unsigned int)(v2 - 1);\n v7 = 0LL;\n do {\n v8 = strlen(v5);\n v5 = (char *)realloc(v5, v8 + 2);\n v9 = a1[v7];\n v5[v8 + 1] = 0;\n v5[v8] = v9;\n v10 = strlen(v5) + 1;\n v11 = malloc(v10);\n v3[v7] = v11;\n __memcpy_chk(v11, v5, v10, v10);\n v12 = v7++;\n } while (v6 != v12);\n }\n free(v5);\n *a2 = v14;\n return v3;\n}" + }, + { + "index": "HumanEval-C-15", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "char *func0(int n) {\n int len = 2;\n for (int i = 1; i <= n; ++i) {\n len += snprintf(NULL, 0, \" %d\", i);\n }\n char *out = malloc(len);\n if (!out) {\n return NULL;\n }\n char *ptr = out;\n ptr += sprintf(ptr, \"0\");\n for (int i = 1; i <= n; ++i) {\n ptr += sprintf(ptr, \" %d\", i);\n }\n return out;\n}", + "test": "#include \n#include \n\nint main() {\n char *result;\n\n result = func0(0);\n assert(strcmp(result, \"0\") == 0);\n free(result);\n\n result = func0(3);\n assert(strcmp(result, \"0 1 2 3\") == 0);\n free(result);\n\n result = func0(10);\n assert(strcmp(result, \"0 1 2 3 4 5 6 7 8 9 10\") == 0);\n free(result);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_24], edi\nmov [rbp+var_1C], 2\nmov [rbp+var_18], 1\njmp short loc_1232\nloc_1208:\nmov eax, [rbp+var_18]\nmov ecx, eax\nlea rax, format; \" %d\"\nmov rdx, rax; format\nmov esi, 0; maxlen\nmov edi, 0; s\nmov eax, 0\ncall _snprintf\nadd [rbp+var_1C], eax\nadd [rbp+var_18], 1\nloc_1232:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_24]\njle short loc_1208\nmov eax, [rbp+var_1C]\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\ncmp [rbp+var_8], 0\njnz short loc_1259\nmov eax, 0\njmp short locret_12BF\nloc_1259:\nmov rax, [rbp+var_8]\nmov [rbp+s], rax\nmov rax, [rbp+s]\nlea rdx, s2; \"0\"\nmov rsi, rdx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\ncdqe\nadd [rbp+s], rax\nmov [rbp+var_14], 1\njmp short loc_12B3\nloc_128B:\nmov edx, [rbp+var_14]\nmov rax, [rbp+s]\nlea rcx, format; \" %d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\ncdqe\nadd [rbp+s], rax\nadd [rbp+var_14], 1\nloc_12B3:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_24]\njle short loc_128B\nmov rax, [rbp+var_8]\nlocret_12BF:\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(int a1)\n{\n int v2; // [rsp+14h] [rbp-1Ch]\n int i; // [rsp+18h] [rbp-18h]\n int j; // [rsp+1Ch] [rbp-14h]\n char *s; // [rsp+20h] [rbp-10h]\n char *v6; // [rsp+28h] [rbp-8h]\n\n v2 = 2;\n for ( i = 1; i <= a1; ++i )\n v2 += snprintf(0LL, 0LL, \" %d\", i);\n v6 = (char *)malloc(v2);\n if ( !v6 )\n return 0LL;\n s = &v6[sprintf(v6, \"0\")];\n for ( j = 1; j <= a1; ++j )\n s += sprintf(s, \" %d\", j);\n return v6;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_24], edi\nmov [rbp+var_1C], 2\nmov [rbp+var_18], 1\njmp short loc_1232\nloc_1208:\nmov eax, [rbp+var_18]\nmov ecx, eax\nlea rax, format; \" %d\"\nmov rdx, rax; format\nmov esi, 0; maxlen\nmov edi, 0; s\nmov eax, 0\ncall _snprintf\nadd [rbp+var_1C], eax\nadd [rbp+var_18], 1\nloc_1232:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_24]\njle short loc_1208\nmov eax, [rbp+var_1C]\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\ncmp [rbp+var_8], 0\njnz short loc_1259\nmov eax, 0\njmp short locret_12BF\nloc_1259:\nmov rax, [rbp+var_8]\nmov [rbp+s], rax\nmov rax, [rbp+s]\nlea rdx, s2; \"0\"\nmov rsi, rdx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\ncdqe\nadd [rbp+s], rax\nmov [rbp+var_14], 1\njmp short loc_12B3\nloc_128B:\nmov edx, [rbp+var_14]\nmov rax, [rbp+s]\nlea rcx, format; \" %d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\ncdqe\nadd [rbp+s], rax\nadd [rbp+var_14], 1\nloc_12B3:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_24]\njle short loc_128B\nmov rax, [rbp+var_8]\nlocret_12BF:\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11E9(int a1)\n{\n int v2; // [rsp+14h] [rbp-1Ch]\n int i; // [rsp+18h] [rbp-18h]\n int j; // [rsp+1Ch] [rbp-14h]\n char *s; // [rsp+20h] [rbp-10h]\n char *v6; // [rsp+28h] [rbp-8h]\n\n v2 = 2;\n for ( i = 1; i <= a1; ++i )\n v2 += snprintf(0LL, 0LL, \" %d\", i);\n v6 = (char *)malloc(v2);\n if ( !v6 )\n return 0LL;\n s = &v6[sprintf(v6, \"0\")];\n for ( j = 1; j <= a1; ++j )\n s += sprintf(s, \" %d\", j);\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11E9(int a1) {\n int v2;\n int i;\n int j;\n char *s;\n char *v6;\n v2 = 2;\n for (i = 1; i <= a1; ++i) v2 += snprintf(0LL, 0LL, \" %d\", i);\n v6 = (char *)malloc(v2);\n if (!v6) return 0LL;\n s = &v6[sprintf(v6, \"0\")];\n for (j = 1; j <= a1; ++j) s += sprintf(s, \" %d\", j);\n return v6;\n}", + "ida_pseudo_norm": "char *func0(int a1) {\n int v2;\n int i;\n int j;\n char *s;\n char *v6;\n v2 = 2;\n for (i = 1; i <= a1; ++i) v2 += snprintf(0LL, 0LL, \" %d\", i);\n v6 = (char *)malloc(v2);\n if (!v6) return 0LL;\n s = &v6[sprintf(v6, \"0\")];\n for (j = 1; j <= a1; ++j) s += sprintf(s, \" %d\", j);\n return v6;\n}" + }, + { + "index": "HumanEval-C-15", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "char *func0(int n) {\n int len = 2;\n for (int i = 1; i <= n; ++i) {\n len += snprintf(NULL, 0, \" %d\", i);\n }\n char *out = malloc(len);\n if (!out) {\n return NULL;\n }\n char *ptr = out;\n ptr += sprintf(ptr, \"0\");\n for (int i = 1; i <= n; ++i) {\n ptr += sprintf(ptr, \" %d\", i);\n }\n return out;\n}", + "test": "#include \n#include \n\nint main() {\n char *result;\n\n result = func0(0);\n assert(strcmp(result, \"0\") == 0);\n free(result);\n\n result = func0(3);\n assert(strcmp(result, \"0 1 2 3\") == 0);\n free(result);\n\n result = func0(10);\n assert(strcmp(result, \"0 1 2 3 4 5 6 7 8 9 10\") == 0);\n free(result);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov r14d, edi\ntest edi, edi\njle loc_1328\nlea r13d, [rdi+1]\nmov ebx, 1\nmov ebp, 2\nlea r12, unk_2004\nloc_123B:\nmov r9d, ebx\nmov r8, r12\nmov rcx, 0FFFFFFFFFFFFFFFFh\nmov edx, 2\nmov esi, 0\nmov edi, 0\nmov eax, 0\ncall ___snprintf_chk\nadd ebp, eax\nadd ebx, 1\ncmp r13d, ebx\njnz short loc_123B\nmovsxd rbp, ebp\nmov rdi, rbp; size\ncall _malloc\nmov [rsp+48h+var_40], rax\ntest rax, rax\njz loc_1314\nlea rcx, assertion+17h; \"0\"\nmov rdx, rbp\nmov esi, 2\nmov r15, [rsp+48h+var_40]\nmov rdi, r15\nmov eax, 0\ncall ___sprintf_chk\ntest rbp, rbp\nmov ebx, 1\ncmovnz rbx, rbp\nsub rbx, 1\nlea r13, [r15+1]\nloc_12B9:\nadd r14d, 1\nmov r12d, 1\nlea r15, unk_2004\nloc_12CA:\nmov r8d, r12d\nmov rcx, r15\nmov rdx, rbx\nmov esi, 2\nmov rdi, r13\nmov eax, 0\ncall ___sprintf_chk\ncdqe\ncmp rbx, rbp\nmov rcx, rbp\ncmovnb rcx, rbx\nlea rsi, [rax+rcx]\nmov rdx, rsi\nsub rdx, rbx\ncmp rdx, rcx\ncmovb rdx, rcx\nsub rbx, rsi\nadd rbx, rdx\nadd r13, rax\nadd r12d, 1\ncmp r12d, r14d\njnz short loc_12CA\nloc_1314:\nmov rax, [rsp+48h+var_40]\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1328:\nmov edi, 2; size\ncall _malloc\nmov rdi, rax; s\nmov [rsp+48h+var_40], rax\ntest rax, rax\njz short loc_1314\nlea rsi, assertion+17h; format\nmov eax, 0\ncall _sprintf\ntest r14d, r14d\njle short loc_1314\nmov rax, [rsp+48h+var_40]\nlea r13, [rax+1]\nmov ebx, 1\nmov ebp, 2\njmp loc_12B9", + "ida_pseudo": "char *__fastcall func0(int a1)\n{\n unsigned int v2; // ebx\n unsigned __int64 v3; // rbp\n __int64 v4; // rbx\n unsigned __int64 v5; // rbx\n char *v6; // r13\n int v7; // r14d\n int v8; // r12d\n int v9; // eax\n unsigned __int64 v10; // rcx\n unsigned __int64 v11; // rdx\n char *v13; // rdi\n char *v14; // [rsp+8h] [rbp-40h]\n\n if ( a1 <= 0 )\n {\n v13 = (char *)malloc(2uLL);\n v14 = v13;\n if ( !v13 )\n return v14;\n sprintf(v13, \"0\");\n if ( a1 <= 0 )\n return v14;\n v6 = v13 + 1;\n v5 = 1LL;\n v3 = 2LL;\n }\n else\n {\n v2 = 1;\n LODWORD(v3) = 2;\n do\n LODWORD(v3) = __snprintf_chk(0LL, 0LL, 2LL, -1LL, &unk_2004, v2++) + v3;\n while ( a1 + 1 != v2 );\n v3 = (int)v3;\n v14 = (char *)malloc((int)v3);\n if ( !v14 )\n return v14;\n __sprintf_chk(v14, 2LL, (int)v3, \"0\");\n v4 = 1LL;\n if ( (_DWORD)v3 )\n v4 = (int)v3;\n v5 = v4 - 1;\n v6 = v14 + 1;\n }\n v7 = a1 + 1;\n v8 = 1;\n do\n {\n v9 = __sprintf_chk(v6, 2LL, v5, &unk_2004);\n v10 = v3;\n if ( v5 >= v3 )\n v10 = v5;\n v11 = v9 + v10 - v5;\n if ( v11 < v10 )\n v11 = v10;\n v5 = v11 + v5 - (v9 + v10);\n v6 += v9;\n ++v8;\n }\n while ( v8 != v7 );\n return v14;\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov r14d, edi\ntest edi, edi\njle loc_1328\nlea r13d, [rdi+1]\nmov ebx, 1\nmov ebp, 2\nlea r12, unk_2004\nloc_123B:\nmov r9d, ebx\nmov r8, r12\nmov rcx, 0FFFFFFFFFFFFFFFFh\nmov edx, 2\nmov esi, 0\nmov edi, 0\nmov eax, 0\ncall ___snprintf_chk\nadd ebp, eax\nadd ebx, 1\ncmp r13d, ebx\njnz short loc_123B\nmovsxd rbp, ebp\nmov rdi, rbp; size\ncall _malloc\nmov [rsp+48h+var_40], rax\ntest rax, rax\njz loc_1314\nlea rcx, assertion+17h; \"0\"\nmov rdx, rbp\nmov esi, 2\nmov r15, [rsp+48h+var_40]\nmov rdi, r15\nmov eax, 0\ncall ___sprintf_chk\ntest rbp, rbp\nmov ebx, 1\ncmovnz rbx, rbp\nsub rbx, 1\nlea r13, [r15+1]\nloc_12B9:\nadd r14d, 1\nmov r12d, 1\nlea r15, unk_2004\nloc_12CA:\nmov r8d, r12d\nmov rcx, r15\nmov rdx, rbx\nmov esi, 2\nmov rdi, r13\nmov eax, 0\ncall ___sprintf_chk\ncdqe\ncmp rbx, rbp\nmov rcx, rbp\ncmovnb rcx, rbx\nlea rsi, [rax+rcx]\nmov rdx, rsi\nsub rdx, rbx\ncmp rdx, rcx\ncmovb rdx, rcx\nsub rbx, rsi\nadd rbx, rdx\nadd r13, rax\nadd r12d, 1\ncmp r12d, r14d\njnz short loc_12CA\nloc_1314:\nmov rax, [rsp+48h+var_40]\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1328:\nmov edi, 2; size\ncall _malloc\nmov rdi, rax; s\nmov [rsp+48h+var_40], rax\ntest rax, rax\njz short loc_1314\nlea rsi, assertion+17h; format\nmov eax, 0\ncall _sprintf\ntest r14d, r14d\njle short loc_1314\nmov rax, [rsp+48h+var_40]\nlea r13, [rax+1]\nmov ebx, 1\nmov ebp, 2\njmp loc_12B9", + "ida_strip_pseudo": "char *__fastcall sub_1209(int a1)\n{\n unsigned int v2; // ebx\n unsigned __int64 v3; // rbp\n __int64 v4; // rbx\n unsigned __int64 v5; // rbx\n char *v6; // r13\n int v7; // r14d\n int v8; // r12d\n int v9; // eax\n unsigned __int64 v10; // rcx\n unsigned __int64 v11; // rdx\n char *v13; // rdi\n char *v14; // [rsp+8h] [rbp-40h]\n\n if ( a1 <= 0 )\n {\n v13 = (char *)malloc(2uLL);\n v14 = v13;\n if ( !v13 )\n return v14;\n sprintf(v13, \"0\");\n if ( a1 <= 0 )\n return v14;\n v6 = v13 + 1;\n v5 = 1LL;\n v3 = 2LL;\n }\n else\n {\n v2 = 1;\n LODWORD(v3) = 2;\n do\n LODWORD(v3) = __snprintf_chk(0LL, 0LL, 2LL, -1LL, &unk_2004, v2++) + v3;\n while ( a1 + 1 != v2 );\n v3 = (int)v3;\n v14 = (char *)malloc((int)v3);\n if ( !v14 )\n return v14;\n __sprintf_chk(v14, 2LL, (int)v3, \"0\");\n v4 = 1LL;\n if ( (_DWORD)v3 )\n v4 = (int)v3;\n v5 = v4 - 1;\n v6 = v14 + 1;\n }\n v7 = a1 + 1;\n v8 = 1;\n do\n {\n v9 = __sprintf_chk(v6, 2LL, v5, &unk_2004);\n v10 = v3;\n if ( v5 >= v3 )\n v10 = v5;\n v11 = v9 + v10 - v5;\n if ( v11 < v10 )\n v11 = v10;\n v5 = v11 + v5 - (v9 + v10);\n v6 += v9;\n ++v8;\n }\n while ( v8 != v7 );\n return v14;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1209(int a1) {\n unsigned int v2;\n unsigned long long v3;\n long long v4;\n unsigned long long v5;\n char *v6;\n int v7;\n int v8;\n int v9;\n unsigned long long v10;\n unsigned long long v11;\n char *v13;\n char *v14;\n if (a1 <= 0) {\n v13 = (char *)malloc(2uLL);\n v14 = v13;\n if (!v13) return v14;\n sprintf(v13, \"0\");\n if (a1 <= 0) return v14;\n v6 = v13 + 1;\n v5 = 1LL;\n v3 = 2LL;\n } else {\n v2 = 1;\n LODWORD(v3) = 2;\n do\n LODWORD(v3) = __snprintf_chk(0LL, 0LL, 2LL, -1LL, &unk_2004, v2++) + v3;\n while (a1 + 1 != v2);\n v3 = (int)v3;\n v14 = (char *)malloc((int)v3);\n if (!v14) return v14;\n __sprintf_chk(v14, 2LL, (int)v3, \"0\");\n v4 = 1LL;\n if ((uint32_t)v3) v4 = (int)v3;\n v5 = v4 - 1;\n v6 = v14 + 1;\n }\n v7 = a1 + 1;\n v8 = 1;\n do {\n v9 = __sprintf_chk(v6, 2LL, v5, &unk_2004);\n v10 = v3;\n if (v5 >= v3) v10 = v5;\n v11 = v9 + v10 - v5;\n if (v11 < v10) v11 = v10;\n v5 = v11 + v5 - (v9 + v10);\n v6 += v9;\n ++v8;\n } while (v8 != v7);\n return v14;\n}", + "ida_pseudo_norm": "char *func0(int a1) {\n unsigned int v2;\n unsigned long long v3;\n long long v4;\n unsigned long long v5;\n char *v6;\n int v7;\n int v8;\n int v9;\n unsigned long long v10;\n unsigned long long v11;\n char *v13;\n char *v14;\n if (a1 <= 0) {\n v13 = (char *)malloc(2uLL);\n v14 = v13;\n if (!v13) return v14;\n sprintf(v13, \"0\");\n if (a1 <= 0) return v14;\n v6 = v13 + 1;\n v5 = 1LL;\n v3 = 2LL;\n } else {\n v2 = 1;\n LODWORD(v3) = 2;\n do\n LODWORD(v3) = __snprintf_chk(0LL, 0LL, 2LL, -1LL, &unk_2004, v2++) + v3;\n while (a1 + 1 != v2);\n v3 = (int)v3;\n v14 = (char *)malloc((int)v3);\n if (!v14) return v14;\n __sprintf_chk(v14, 2LL, (int)v3, \"0\");\n v4 = 1LL;\n if ((uint32_t)v3) v4 = (int)v3;\n v5 = v4 - 1;\n v6 = v14 + 1;\n }\n v7 = a1 + 1;\n v8 = 1;\n do {\n v9 = __sprintf_chk(v6, 2LL, v5, &unk_2004);\n v10 = v3;\n if (v5 >= v3) v10 = v5;\n v11 = v9 + v10 - v5;\n if (v11 < v10) v11 = v10;\n v5 = v11 + v5 - (v9 + v10);\n v6 += v9;\n ++v8;\n } while (v8 != v7);\n return v14;\n}" + }, + { + "index": "HumanEval-C-15", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "char *func0(int n) {\n int len = 2;\n for (int i = 1; i <= n; ++i) {\n len += snprintf(NULL, 0, \" %d\", i);\n }\n char *out = malloc(len);\n if (!out) {\n return NULL;\n }\n char *ptr = out;\n ptr += sprintf(ptr, \"0\");\n for (int i = 1; i <= n; ++i) {\n ptr += sprintf(ptr, \" %d\", i);\n }\n return out;\n}", + "test": "#include \n#include \n\nint main() {\n char *result;\n\n result = func0(0);\n assert(strcmp(result, \"0\") == 0);\n free(result);\n\n result = func0(3);\n assert(strcmp(result, \"0 1 2 3\") == 0);\n free(result);\n\n result = func0(10);\n assert(strcmp(result, \"0 1 2 3 4 5 6 7 8 9 10\") == 0);\n free(result);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\ntest edi, edi\njle loc_13F0\nlea r12d, [rdi+1]\nmov ebx, 1\nmov ebp, 2\nlea r13, unk_2004\nnop\nloc_1310:\nmov r9d, ebx\nmov r8, r13\nmov rcx, 0FFFFFFFFFFFFFFFFh\nxor esi, esi\nmov edx, 2\nxor edi, edi\nxor eax, eax\nadd ebx, 1\ncall ___snprintf_chk\nadd ebp, eax\ncmp r12d, ebx\njnz short loc_1310\nmovsxd rbp, ebp\nmov rdi, rbp; size\ncall _malloc\nmov [rsp+48h+var_40], rax\ntest rax, rax\njz loc_13D7\nmov r14, [rsp+48h+var_40]\nxor eax, eax\nmov rdx, rbp\nmov esi, 2\nlea rcx, assertion+17h; \"0\"\nmov ebx, 1\nmov r15d, 1\nmov rdi, r14\nlea r13, unk_2004\ncall ___sprintf_chk\ntest rbp, rbp\ncmovnz rbx, rbp\nadd r14, 1\nsub rbx, 1\nnop\nloc_1390:\nmov rdx, rbx\nmov r8d, r15d\nmov rcx, r13\nmov esi, 2\nmov rdi, r14\nxor eax, eax\ncall ___sprintf_chk\ncmp rbp, rbx\nmov rcx, rbx\ncmovnb rcx, rbp\ncdqe\nlea rsi, [rax+rcx]\nmov rdx, rsi\nsub rdx, rbx\ncmp rdx, rcx\ncmovb rdx, rcx\nsub rbx, rsi\nadd r15d, 1\nadd r14, rax\nadd rbx, rdx\ncmp r15d, r12d\njnz short loc_1390\nloc_13D7:\nmov rax, [rsp+48h+var_40]\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_13F0:\nmov edi, 2; size\ncall _malloc\nmov [rsp+48h+var_40], rax\nmov rdi, rax; s\ntest rax, rax\njz short loc_13D7\nlea rsi, assertion+17h; format\nxor eax, eax\ncall _sprintf\njmp short loc_13D7", + "ida_pseudo": "char *__fastcall func0(int a1)\n{\n int v1; // r12d\n unsigned int v2; // ebx\n int v3; // ebp\n __int64 v4; // r9\n __int64 v5; // rbx\n int v6; // r15d\n char *v7; // r14\n unsigned __int64 v8; // rbx\n int v9; // eax\n unsigned __int64 v10; // rcx\n unsigned __int64 v11; // rdx\n char *v13; // [rsp+8h] [rbp-40h]\n\n if ( a1 <= 0 )\n {\n v13 = (char *)malloc(2uLL);\n if ( v13 )\n sprintf(v13, \"0\");\n }\n else\n {\n v1 = a1 + 1;\n v2 = 1;\n v3 = 2;\n do\n {\n v4 = v2++;\n v3 += __snprintf_chk(0LL, 0LL, 2LL, -1LL, &unk_2004, v4);\n }\n while ( v1 != v2 );\n v13 = (char *)malloc(v3);\n if ( v13 )\n {\n v5 = 1LL;\n v6 = 1;\n __sprintf_chk(v13, 2LL, v3, \"0\");\n if ( v3 )\n v5 = v3;\n v7 = v13 + 1;\n v8 = v5 - 1;\n do\n {\n v9 = __sprintf_chk(v7, 2LL, v8, &unk_2004);\n v10 = v8;\n if ( v3 >= v8 )\n v10 = v3;\n v11 = v9 + v10 - v8;\n if ( v11 < v10 )\n v11 = v10;\n ++v6;\n v7 += v9;\n v8 = v11 + v8 - (v9 + v10);\n }\n while ( v6 != v1 );\n }\n }\n return v13;\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\ntest edi, edi\njle loc_13F0\nlea r12d, [rdi+1]\nmov ebx, 1\nmov ebp, 2\nlea r13, unk_2004\nnop\nloc_1310:\nmov r9d, ebx\nmov r8, r13\nmov rcx, 0FFFFFFFFFFFFFFFFh\nxor esi, esi\nmov edx, 2\nxor edi, edi\nxor eax, eax\nadd ebx, 1\ncall ___snprintf_chk\nadd ebp, eax\ncmp r12d, ebx\njnz short loc_1310\nmovsxd rbp, ebp\nmov rdi, rbp; size\ncall _malloc\nmov [rsp+48h+var_40], rax\ntest rax, rax\njz loc_13D7\nmov r14, [rsp+48h+var_40]\nxor eax, eax\nmov rdx, rbp\nmov esi, 2\nlea rcx, assertion+17h; \"0\"\nmov ebx, 1\nmov r15d, 1\nmov rdi, r14\nlea r13, unk_2004\ncall ___sprintf_chk\ntest rbp, rbp\ncmovnz rbx, rbp\nadd r14, 1\nsub rbx, 1\nnop\nloc_1390:\nmov rdx, rbx\nmov r8d, r15d\nmov rcx, r13\nmov esi, 2\nmov rdi, r14\nxor eax, eax\ncall ___sprintf_chk\ncmp rbp, rbx\nmov rcx, rbx\ncmovnb rcx, rbp\ncdqe\nlea rsi, [rax+rcx]\nmov rdx, rsi\nsub rdx, rbx\ncmp rdx, rcx\ncmovb rdx, rcx\nsub rbx, rsi\nadd r15d, 1\nadd r14, rax\nadd rbx, rdx\ncmp r15d, r12d\njnz short loc_1390\nloc_13D7:\nmov rax, [rsp+48h+var_40]\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_13F0:\nmov edi, 2; size\ncall _malloc\nmov [rsp+48h+var_40], rax\nmov rdi, rax; s\ntest rax, rax\njz short loc_13D7\nlea rsi, assertion+17h; format\nxor eax, eax\ncall _sprintf\njmp short loc_13D7", + "ida_strip_pseudo": "char *__fastcall sub_12E0(int a1)\n{\n int v1; // r12d\n unsigned int v2; // ebx\n int v3; // ebp\n __int64 v4; // r9\n __int64 v5; // rbx\n int v6; // r15d\n char *v7; // r14\n unsigned __int64 v8; // rbx\n int v9; // eax\n unsigned __int64 v10; // rcx\n unsigned __int64 v11; // rdx\n char *v13; // [rsp+8h] [rbp-40h]\n\n if ( a1 <= 0 )\n {\n v13 = (char *)malloc(2uLL);\n if ( v13 )\n sprintf(v13, \"0\");\n }\n else\n {\n v1 = a1 + 1;\n v2 = 1;\n v3 = 2;\n do\n {\n v4 = v2++;\n v3 += __snprintf_chk(0LL, 0LL, 2LL, -1LL, &unk_2004, v4);\n }\n while ( v1 != v2 );\n v13 = (char *)malloc(v3);\n if ( v13 )\n {\n v5 = 1LL;\n v6 = 1;\n __sprintf_chk(v13, 2LL, v3, \"0\");\n if ( v3 )\n v5 = v3;\n v7 = v13 + 1;\n v8 = v5 - 1;\n do\n {\n v9 = __sprintf_chk(v7, 2LL, v8, &unk_2004);\n v10 = v8;\n if ( v3 >= v8 )\n v10 = v3;\n v11 = v9 + v10 - v8;\n if ( v11 < v10 )\n v11 = v10;\n ++v6;\n v7 += v9;\n v8 = v11 + v8 - (v9 + v10);\n }\n while ( v6 != v1 );\n }\n }\n return v13;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_12E0(int a1) {\n int v1;\n unsigned int v2;\n int v3;\n long long v4;\n long long v5;\n int v6;\n char *v7;\n unsigned long long v8;\n int v9;\n unsigned long long v10;\n unsigned long long v11;\n char *v13;\n if (a1 <= 0) {\n v13 = (char *)malloc(2uLL);\n if (v13) sprintf(v13, \"0\");\n } else {\n v1 = a1 + 1;\n v2 = 1;\n v3 = 2;\n do {\n v4 = v2++;\n v3 += __snprintf_chk(0LL, 0LL, 2LL, -1LL, &unk_2004, v4);\n } while (v1 != v2);\n v13 = (char *)malloc(v3);\n if (v13) {\n v5 = 1LL;\n v6 = 1;\n __sprintf_chk(v13, 2LL, v3, \"0\");\n if (v3) v5 = v3;\n v7 = v13 + 1;\n v8 = v5 - 1;\n do {\n v9 = __sprintf_chk(v7, 2LL, v8, &unk_2004);\n v10 = v8;\n if (v3 >= v8) v10 = v3;\n v11 = v9 + v10 - v8;\n if (v11 < v10) v11 = v10;\n ++v6;\n v7 += v9;\n v8 = v11 + v8 - (v9 + v10);\n } while (v6 != v1);\n }\n }\n return v13;\n}", + "ida_pseudo_norm": "char *func0(int a1) {\n int v1;\n unsigned int v2;\n int v3;\n long long v4;\n long long v5;\n int v6;\n char *v7;\n unsigned long long v8;\n int v9;\n unsigned long long v10;\n unsigned long long v11;\n char *v13;\n if (a1 <= 0) {\n v13 = (char *)malloc(2uLL);\n if (v13) sprintf(v13, \"0\");\n } else {\n v1 = a1 + 1;\n v2 = 1;\n v3 = 2;\n do {\n v4 = v2++;\n v3 += __snprintf_chk(0LL, 0LL, 2LL, -1LL, &unk_2004, v4);\n } while (v1 != v2);\n v13 = (char *)malloc(v3);\n if (v13) {\n v5 = 1LL;\n v6 = 1;\n __sprintf_chk(v13, 2LL, v3, \"0\");\n if (v3) v5 = v3;\n v7 = v13 + 1;\n v8 = v5 - 1;\n do {\n v9 = __sprintf_chk(v7, 2LL, v8, &unk_2004);\n v10 = v8;\n if (v3 >= v8) v10 = v3;\n v11 = v9 + v10 - v8;\n if (v11 < v10) v11 = v10;\n ++v6;\n v7 += v9;\n v8 = v11 + v8 - (v9 + v10);\n } while (v6 != v1);\n }\n }\n return v13;\n}" + }, + { + "index": "HumanEval-C-15", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "char *func0(int n) {\n int len = 2;\n for (int i = 1; i <= n; ++i) {\n len += snprintf(NULL, 0, \" %d\", i);\n }\n char *out = malloc(len);\n if (!out) {\n return NULL;\n }\n char *ptr = out;\n ptr += sprintf(ptr, \"0\");\n for (int i = 1; i <= n; ++i) {\n ptr += sprintf(ptr, \" %d\", i);\n }\n return out;\n}", + "test": "#include \n#include \n\nint main() {\n char *result;\n\n result = func0(0);\n assert(strcmp(result, \"0\") == 0);\n free(result);\n\n result = func0(3);\n assert(strcmp(result, \"0 1 2 3\") == 0);\n free(result);\n\n result = func0(10);\n assert(strcmp(result, \"0 1 2 3 4 5 6 7 8 9 10\") == 0);\n free(result);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\ntest edi, edi\njle loc_13F0\nlea r12d, [rdi+1]\nmov ebx, 1\nmov ebp, 2\nlea r13, unk_2004\nnop\nloc_1310:\nmov r9d, ebx\nmov r8, r13\nmov rcx, 0FFFFFFFFFFFFFFFFh\nxor esi, esi\nmov edx, 2\nxor edi, edi\nxor eax, eax\nadd ebx, 1\ncall ___snprintf_chk\nadd ebp, eax\ncmp r12d, ebx\njnz short loc_1310\nmovsxd rbp, ebp\nmov rdi, rbp; size\ncall _malloc\nmov [rsp+48h+var_40], rax\ntest rax, rax\njz loc_13D7\nmov r14, rax\nmov rdi, rax\nlea rcx, assertion+17h; \"0\"\nxor eax, eax\nmov rdx, rbp\nmov esi, 2\nmov ebx, 1\nmov r15d, 1\ncall ___sprintf_chk\ntest rbp, rbp\nlea r13, unk_2004\ncmovnz rbx, rbp\nadd r14, 1\nsub rbx, 1\nnop dword ptr [rax]\nloc_1390:\nmov rdx, rbx\nmov r8d, r15d\nmov rcx, r13\nmov esi, 2\nmov rdi, r14\nxor eax, eax\ncall ___sprintf_chk\ncmp rbp, rbx\nmov rcx, rbx\ncmovnb rcx, rbp\ncdqe\nlea rsi, [rax+rcx]\nmov rdx, rsi\nsub rdx, rbx\ncmp rdx, rcx\ncmovb rdx, rcx\nsub rbx, rsi\nadd r15d, 1\nadd r14, rax\nadd rbx, rdx\ncmp r12d, r15d\njnz short loc_1390\nloc_13D7:\nmov rax, [rsp+48h+var_40]\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_13F0:\nmov edi, 2; size\ncall _malloc\nmov [rsp+48h+var_40], rax\nmov rdi, rax; s\ntest rax, rax\njz short loc_13D7\nlea rsi, assertion+17h; format\nxor eax, eax\ncall _sprintf\njmp short loc_13D7", + "ida_pseudo": "char *__fastcall func0(int a1)\n{\n int v1; // r12d\n unsigned int v2; // ebx\n int v3; // ebp\n __int64 v4; // r9\n char *v5; // rax\n char *v6; // r14\n __int64 v7; // rbx\n int v8; // r15d\n char *v9; // r14\n unsigned __int64 v10; // rbx\n int v11; // eax\n unsigned __int64 v12; // rcx\n unsigned __int64 v13; // rdx\n char *v15; // [rsp+8h] [rbp-40h]\n\n if ( a1 <= 0 )\n {\n v15 = (char *)malloc(2uLL);\n if ( v15 )\n sprintf(v15, \"0\");\n }\n else\n {\n v1 = a1 + 1;\n v2 = 1;\n v3 = 2;\n do\n {\n v4 = v2++;\n v3 += __snprintf_chk(0LL, 0LL, 2LL, -1LL, &unk_2004, v4);\n }\n while ( v1 != v2 );\n v5 = (char *)malloc(v3);\n v15 = v5;\n if ( v5 )\n {\n v6 = v5;\n v7 = 1LL;\n v8 = 1;\n __sprintf_chk(v5, 2LL, v3, \"0\");\n if ( v3 )\n v7 = v3;\n v9 = v6 + 1;\n v10 = v7 - 1;\n do\n {\n v11 = __sprintf_chk(v9, 2LL, v10, &unk_2004);\n v12 = v10;\n if ( v3 >= v10 )\n v12 = v3;\n v13 = v11 + v12 - v10;\n if ( v13 < v12 )\n v13 = v12;\n ++v8;\n v9 += v11;\n v10 = v13 + v10 - (v11 + v12);\n }\n while ( v1 != v8 );\n }\n }\n return v15;\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\ntest edi, edi\njle loc_13F0\nlea r12d, [rdi+1]\nmov ebx, 1\nmov ebp, 2\nlea r13, unk_2004\nnop\nloc_1310:\nmov r9d, ebx\nmov r8, r13\nmov rcx, 0FFFFFFFFFFFFFFFFh\nxor esi, esi\nmov edx, 2\nxor edi, edi\nxor eax, eax\nadd ebx, 1\ncall ___snprintf_chk\nadd ebp, eax\ncmp r12d, ebx\njnz short loc_1310\nmovsxd rbp, ebp\nmov rdi, rbp; size\ncall _malloc\nmov [rsp+48h+var_40], rax\ntest rax, rax\njz loc_13D7\nmov r14, rax\nmov rdi, rax\nlea rcx, assertion+17h; \"0\"\nxor eax, eax\nmov rdx, rbp\nmov esi, 2\nmov ebx, 1\nmov r15d, 1\ncall ___sprintf_chk\ntest rbp, rbp\nlea r13, unk_2004\ncmovnz rbx, rbp\nadd r14, 1\nsub rbx, 1\nnop dword ptr [rax]\nloc_1390:\nmov rdx, rbx\nmov r8d, r15d\nmov rcx, r13\nmov esi, 2\nmov rdi, r14\nxor eax, eax\ncall ___sprintf_chk\ncmp rbp, rbx\nmov rcx, rbx\ncmovnb rcx, rbp\ncdqe\nlea rsi, [rax+rcx]\nmov rdx, rsi\nsub rdx, rbx\ncmp rdx, rcx\ncmovb rdx, rcx\nsub rbx, rsi\nadd r15d, 1\nadd r14, rax\nadd rbx, rdx\ncmp r12d, r15d\njnz short loc_1390\nloc_13D7:\nmov rax, [rsp+48h+var_40]\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_13F0:\nmov edi, 2; size\ncall _malloc\nmov [rsp+48h+var_40], rax\nmov rdi, rax; s\ntest rax, rax\njz short loc_13D7\nlea rsi, assertion+17h; format\nxor eax, eax\ncall _sprintf\njmp short loc_13D7", + "ida_strip_pseudo": "char *__fastcall sub_12E0(int a1)\n{\n int v1; // r12d\n unsigned int v2; // ebx\n int v3; // ebp\n __int64 v4; // r9\n char *v5; // rax\n char *v6; // r14\n __int64 v7; // rbx\n int v8; // r15d\n char *v9; // r14\n unsigned __int64 v10; // rbx\n int v11; // eax\n unsigned __int64 v12; // rcx\n unsigned __int64 v13; // rdx\n char *v15; // [rsp+8h] [rbp-40h]\n\n if ( a1 <= 0 )\n {\n v15 = (char *)malloc(2uLL);\n if ( v15 )\n sprintf(v15, \"0\");\n }\n else\n {\n v1 = a1 + 1;\n v2 = 1;\n v3 = 2;\n do\n {\n v4 = v2++;\n v3 += __snprintf_chk(0LL, 0LL, 2LL, -1LL, &unk_2004, v4);\n }\n while ( v1 != v2 );\n v5 = (char *)malloc(v3);\n v15 = v5;\n if ( v5 )\n {\n v6 = v5;\n v7 = 1LL;\n v8 = 1;\n __sprintf_chk(v5, 2LL, v3, \"0\");\n if ( v3 )\n v7 = v3;\n v9 = v6 + 1;\n v10 = v7 - 1;\n do\n {\n v11 = __sprintf_chk(v9, 2LL, v10, &unk_2004);\n v12 = v10;\n if ( v3 >= v10 )\n v12 = v3;\n v13 = v11 + v12 - v10;\n if ( v13 < v12 )\n v13 = v12;\n ++v8;\n v9 += v11;\n v10 = v13 + v10 - (v11 + v12);\n }\n while ( v1 != v8 );\n }\n }\n return v15;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_12E0(int a1) {\n int v1;\n unsigned int v2;\n int v3;\n long long v4;\n char *v5;\n char *v6;\n long long v7;\n int v8;\n char *v9;\n unsigned long long v10;\n int v11;\n unsigned long long v12;\n unsigned long long v13;\n char *v15;\n if (a1 <= 0) {\n v15 = (char *)malloc(2uLL);\n if (v15) sprintf(v15, \"0\");\n } else {\n v1 = a1 + 1;\n v2 = 1;\n v3 = 2;\n do {\n v4 = v2++;\n v3 += __snprintf_chk(0LL, 0LL, 2LL, -1LL, &unk_2004, v4);\n } while (v1 != v2);\n v5 = (char *)malloc(v3);\n v15 = v5;\n if (v5) {\n v6 = v5;\n v7 = 1LL;\n v8 = 1;\n __sprintf_chk(v5, 2LL, v3, \"0\");\n if (v3) v7 = v3;\n v9 = v6 + 1;\n v10 = v7 - 1;\n do {\n v11 = __sprintf_chk(v9, 2LL, v10, &unk_2004);\n v12 = v10;\n if (v3 >= v10) v12 = v3;\n v13 = v11 + v12 - v10;\n if (v13 < v12) v13 = v12;\n ++v8;\n v9 += v11;\n v10 = v13 + v10 - (v11 + v12);\n } while (v1 != v8);\n }\n }\n return v15;\n}", + "ida_pseudo_norm": "char *func0(int a1) {\n int v1;\n unsigned int v2;\n int v3;\n long long v4;\n char *v5;\n char *v6;\n long long v7;\n int v8;\n char *v9;\n unsigned long long v10;\n int v11;\n unsigned long long v12;\n unsigned long long v13;\n char *v15;\n if (a1 <= 0) {\n v15 = (char *)malloc(2uLL);\n if (v15) sprintf(v15, \"0\");\n } else {\n v1 = a1 + 1;\n v2 = 1;\n v3 = 2;\n do {\n v4 = v2++;\n v3 += __snprintf_chk(0LL, 0LL, 2LL, -1LL, &unk_2004, v4);\n } while (v1 != v2);\n v5 = (char *)malloc(v3);\n v15 = v5;\n if (v5) {\n v6 = v5;\n v7 = 1LL;\n v8 = 1;\n __sprintf_chk(v5, 2LL, v3, \"0\");\n if (v3) v7 = v3;\n v9 = v6 + 1;\n v10 = v7 - 1;\n do {\n v11 = __sprintf_chk(v9, 2LL, v10, &unk_2004);\n v12 = v10;\n if (v3 >= v10) v12 = v3;\n v13 = v11 + v12 - v10;\n if (v13 < v12) v13 = v12;\n ++v8;\n v9 += v11;\n v10 = v13 + v10 - (v11 + v12);\n } while (v1 != v8);\n }\n }\n return v15;\n}" + }, + { + "index": "HumanEval-C-16", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int func0(const char *str) {\n int count = 0;\n int char_map[256] = {0};\n int index;\n for (index = 0; str[index]; index++) {\n char ch = tolower((unsigned char)str[index]);\n if (char_map[ch] == 0 && isalpha((unsigned char)ch)) {\n char_map[ch] = 1;\n count++;\n }\n }\n return count;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"\") == 0);\n assert(func0(\"abcde\") == 5);\n assert(func0(\"abcdecadeCADE\") == 5);\n assert(func0(\"aaaaAAAAaaaa\") == 1);\n assert(func0(\"Jerry jERRY JeRRRY\") == 4);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 430h\nmov [rbp+var_428], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_418], 0\nlea rdx, [rbp+var_410]\nmov eax, 0\nmov ecx, 80h\nmov rdi, rdx\nrep stosq\nmov [rbp+var_414], 0\njmp loc_1281\nloc_11FE:\nmov eax, [rbp+var_414]\nmovsxd rdx, eax\nmov rax, [rbp+var_428]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovzx eax, al\nmov edi, eax; c\ncall _tolower\nmov [rbp+var_419], al\nmovsx eax, [rbp+var_419]\ncdqe\nmov eax, [rbp+rax*4+var_410]\ntest eax, eax\njnz short loc_127A\ncall ___ctype_b_loc\nmov rax, [rax]\nmovzx edx, [rbp+var_419]\nmovzx edx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 400h\ntest eax, eax\njz short loc_127A\nmovsx eax, [rbp+var_419]\ncdqe\nmov [rbp+rax*4+var_410], 1\nadd [rbp+var_418], 1\nloc_127A:\nadd [rbp+var_414], 1\nloc_1281:\nmov eax, [rbp+var_414]\nmovsxd rdx, eax\nmov rax, [rbp+var_428]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_11FE\nmov eax, [rbp+var_418]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12B9\ncall ___stack_chk_fail\nlocret_12B9:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1)\n{\n unsigned __int8 v2; // [rsp+17h] [rbp-419h]\n unsigned int v3; // [rsp+18h] [rbp-418h]\n int i; // [rsp+1Ch] [rbp-414h]\n _DWORD v5[258]; // [rsp+20h] [rbp-410h] BYREF\n unsigned __int64 v6; // [rsp+428h] [rbp-8h]\n\n v6 = __readfsqword(0x28u);\n v3 = 0;\n memset(v5, 0, 0x400uLL);\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n {\n v2 = tolower(*(unsigned __int8 *)(i + a1));\n if ( !v5[(char)v2] && ((*__ctype_b_loc())[v2] & 0x400) != 0 )\n {\n v5[(char)v2] = 1;\n ++v3;\n }\n }\n return v3;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 430h\nmov [rbp+var_428], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_418], 0\nlea rdx, [rbp+var_410]\nmov eax, 0\nmov ecx, 80h\nmov rdi, rdx\nrep stosq\nmov [rbp+var_414], 0\njmp loc_1281\nloc_11FE:\nmov eax, [rbp+var_414]\nmovsxd rdx, eax\nmov rax, [rbp+var_428]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovzx eax, al\nmov edi, eax; c\ncall _tolower\nmov [rbp+var_419], al\nmovsx eax, [rbp+var_419]\ncdqe\nmov eax, [rbp+rax*4+var_410]\ntest eax, eax\njnz short loc_127A\ncall ___ctype_b_loc\nmov rax, [rax]\nmovzx edx, [rbp+var_419]\nmovzx edx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 400h\ntest eax, eax\njz short loc_127A\nmovsx eax, [rbp+var_419]\ncdqe\nmov [rbp+rax*4+var_410], 1\nadd [rbp+var_418], 1\nloc_127A:\nadd [rbp+var_414], 1\nloc_1281:\nmov eax, [rbp+var_414]\nmovsxd rdx, eax\nmov rax, [rbp+var_428]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_11FE\nmov eax, [rbp+var_418]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12B9\ncall ___stack_chk_fail\nlocret_12B9:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(__int64 a1)\n{\n unsigned __int8 v2; // [rsp+17h] [rbp-419h]\n unsigned int v3; // [rsp+18h] [rbp-418h]\n int i; // [rsp+1Ch] [rbp-414h]\n _DWORD v5[258]; // [rsp+20h] [rbp-410h] BYREF\n unsigned __int64 v6; // [rsp+428h] [rbp-8h]\n\n v6 = __readfsqword(0x28u);\n v3 = 0;\n memset(v5, 0, 0x400uLL);\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n {\n v2 = tolower(*(unsigned __int8 *)(i + a1));\n if ( !v5[(char)v2] && ((*__ctype_b_loc())[v2] & 0x400) != 0 )\n {\n v5[(char)v2] = 1;\n ++v3;\n }\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(long long a1) {\n unsigned char v2;\n unsigned int v3;\n int i;\n uint32_t v5[258];\n unsigned long long v6;\n v6 = __readfsqword(40u);\n v3 = 0;\n memset(v5, 0, 1024uLL);\n for (i = 0; *(uint8_t *)(i + a1); ++i) {\n v2 = tolower(*(unsigned char *)(i + a1));\n if (!v5[(char)v2] && ((*__ctype_b_loc())[v2] & 1024) != 0) {\n v5[(char)v2] = 1;\n ++v3;\n }\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1) {\n unsigned char v2;\n unsigned int v3;\n int i;\n uint32_t v5[258];\n unsigned long long v6;\n v6 = __readfsqword(40u);\n v3 = 0;\n memset(v5, 0, 1024uLL);\n for (i = 0; *(uint8_t *)(i + a1); ++i) {\n v2 = tolower(*(unsigned char *)(i + a1));\n if (!v5[(char)v2] && ((*__ctype_b_loc())[v2] & 1024) != 0) {\n v5[(char)v2] = 1;\n ++v3;\n }\n }\n return v3;\n}" + }, + { + "index": "HumanEval-C-16", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int func0(const char *str) {\n int count = 0;\n int char_map[256] = {0};\n int index;\n for (index = 0; str[index]; index++) {\n char ch = tolower((unsigned char)str[index]);\n if (char_map[ch] == 0 && isalpha((unsigned char)ch)) {\n char_map[ch] = 1;\n count++;\n }\n }\n return count;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"\") == 0);\n assert(func0(\"abcde\") == 5);\n assert(func0(\"abcdecadeCADE\") == 5);\n assert(func0(\"aaaaAAAAaaaa\") == 1);\n assert(func0(\"Jerry jERRY JeRRRY\") == 4);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 410h\nmov rbp, rdi\nmov rax, fs:28h\nmov [rsp+438h+var_30], rax\nxor eax, eax\nmov rdi, rsp\nmov ecx, 80h\nrep stosq\nmovzx ebx, byte ptr [rbp+0]\ntest bl, bl\njz short loc_123D\ncall ___ctype_tolower_loc\nmov r12, [rax]\nadd rbp, 1\nmov r13d, 0\njmp short loc_1205\nloc_11F9:\nadd rbp, 1\nmovzx ebx, byte ptr [rbp-1]\ntest bl, bl\njz short loc_1243\nloc_1205:\nmovzx ebx, bl\nmov ebx, [r12+rbx*4]\nmovsx r14d, bl\nmovsx rax, bl\ncmp [rsp+rax*4+438h+var_438], 0\njnz short loc_11F9\ncall ___ctype_b_loc\nmovzx ebx, bl\nmov rax, [rax]\ntest byte ptr [rax+rbx*2+1], 4\njz short loc_11F9\nmovsxd r14, r14d\nmov [rsp+r14*4+438h+var_438], 1\nadd r13d, 1\njmp short loc_11F9\nloc_123D:\nmov r13d, 0\nloc_1243:\nmov rax, [rsp+438h+var_30]\nsub rax, fs:28h\njnz short loc_1269\nmov eax, r13d\nadd rsp, 410h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1269:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(unsigned __int8 *a1)\n{\n unsigned __int8 v1; // bl\n const __int32_t *v2; // r12\n unsigned __int8 *v3; // rbp\n unsigned int v4; // r13d\n __int32_t v5; // ebx\n _DWORD v7[258]; // [rsp+0h] [rbp-438h] BYREF\n unsigned __int64 v8; // [rsp+408h] [rbp-30h]\n\n v8 = __readfsqword(0x28u);\n memset(v7, 0, 0x400uLL);\n v1 = *a1;\n if ( *a1 )\n {\n v2 = *__ctype_tolower_loc();\n v3 = a1 + 1;\n v4 = 0;\n do\n {\n v5 = v2[v1];\n if ( !v7[(char)v5] && ((*__ctype_b_loc())[(unsigned __int8)v5] & 0x400) != 0 )\n {\n v7[(char)v5] = 1;\n ++v4;\n }\n v1 = *v3++;\n }\n while ( v1 );\n }\n else\n {\n return 0;\n }\n return v4;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 410h\nmov rbp, rdi\nmov rax, fs:28h\nmov [rsp+438h+var_30], rax\nxor eax, eax\nmov rdi, rsp\nmov ecx, 80h\nrep stosq\nmovzx ebx, byte ptr [rbp+0]\ntest bl, bl\njz short loc_123D\ncall ___ctype_tolower_loc\nmov r12, [rax]\nadd rbp, 1\nmov r13d, 0\njmp short loc_1205\nloc_11F9:\nadd rbp, 1\nmovzx ebx, byte ptr [rbp-1]\ntest bl, bl\njz short loc_1243\nloc_1205:\nmovzx ebx, bl\nmov ebx, [r12+rbx*4]\nmovsx r14d, bl\nmovsx rax, bl\ncmp [rsp+rax*4+438h+var_438], 0\njnz short loc_11F9\ncall ___ctype_b_loc\nmovzx ebx, bl\nmov rax, [rax]\ntest byte ptr [rax+rbx*2+1], 4\njz short loc_11F9\nmovsxd r14, r14d\nmov [rsp+r14*4+438h+var_438], 1\nadd r13d, 1\njmp short loc_11F9\nloc_123D:\nmov r13d, 0\nloc_1243:\nmov rax, [rsp+438h+var_30]\nsub rax, fs:28h\njnz short loc_1269\nmov eax, r13d\nadd rsp, 410h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1269:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(unsigned __int8 *a1)\n{\n unsigned __int8 v1; // bl\n const __int32_t *v2; // r12\n unsigned __int8 *v3; // rbp\n unsigned int v4; // r13d\n __int32_t v5; // ebx\n _DWORD v7[258]; // [rsp+0h] [rbp-438h] BYREF\n unsigned __int64 v8; // [rsp+408h] [rbp-30h]\n\n v8 = __readfsqword(0x28u);\n memset(v7, 0, 0x400uLL);\n v1 = *a1;\n if ( *a1 )\n {\n v2 = *__ctype_tolower_loc();\n v3 = a1 + 1;\n v4 = 0;\n do\n {\n v5 = v2[v1];\n if ( !v7[(char)v5] && ((*__ctype_b_loc())[(unsigned __int8)v5] & 0x400) != 0 )\n {\n v7[(char)v5] = 1;\n ++v4;\n }\n v1 = *v3++;\n }\n while ( v1 );\n }\n else\n {\n return 0;\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(unsigned char *a1) {\n unsigned char v1;\n const __int32_t *v2;\n unsigned char *v3;\n unsigned int v4;\n __int32_t v5;\n uint32_t v7[258];\n unsigned long long v8;\n v8 = __readfsqword(40u);\n memset(v7, 0, 1024uLL);\n v1 = *a1;\n if (*a1) {\n v2 = *__ctype_tolower_loc();\n v3 = a1 + 1;\n v4 = 0;\n do {\n v5 = v2[v1];\n if (!v7[(char)v5] &&\n ((*__ctype_b_loc())[(unsigned char)v5] & 1024) != 0) {\n v7[(char)v5] = 1;\n ++v4;\n }\n v1 = *v3++;\n } while (v1);\n } else {\n return 0;\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(unsigned char *a1) {\n unsigned char v1;\n const __int32_t *v2;\n unsigned char *v3;\n unsigned int v4;\n __int32_t v5;\n uint32_t v7[258];\n unsigned long long v8;\n v8 = __readfsqword(40u);\n memset(v7, 0, 1024uLL);\n v1 = *a1;\n if (*a1) {\n v2 = *__ctype_tolower_loc();\n v3 = a1 + 1;\n v4 = 0;\n do {\n v5 = v2[v1];\n if (!v7[(char)v5] &&\n ((*__ctype_b_loc())[(unsigned char)v5] & 1024) != 0) {\n v7[(char)v5] = 1;\n ++v4;\n }\n v1 = *v3++;\n } while (v1);\n } else {\n return 0;\n }\n return v4;\n}" + }, + { + "index": "HumanEval-C-16", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int func0(const char *str) {\n int count = 0;\n int char_map[256] = {0};\n int index;\n for (index = 0; str[index]; index++) {\n char ch = tolower((unsigned char)str[index]);\n if (char_map[ch] == 0 && isalpha((unsigned char)ch)) {\n char_map[ch] = 1;\n count++;\n }\n }\n return count;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"\") == 0);\n assert(func0(\"abcde\") == 5);\n assert(func0(\"abcdecadeCADE\") == 5);\n assert(func0(\"aaaaAAAAaaaa\") == 1);\n assert(func0(\"Jerry jERRY JeRRRY\") == 4);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r14\nmov ecx, 80h\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 410h\nmovzx ebx, byte ptr [rbp+0]\nmov rax, fs:28h\nmov [rsp+438h+var_30], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\ntest bl, bl\njz short loc_1370\ncall ___ctype_tolower_loc\nadd rbp, 1\nxor r12d, r12d\nmov r14, [rax]\nnop dword ptr [rax+rax+00h]\nloc_1310:\nmov ebx, [r14+rbx*4]\nmovsx r13, bl\nmov eax, [rsp+r13*4+438h+var_438]\ntest eax, eax\njnz short loc_133E\ncall ___ctype_b_loc\nmovzx ebx, bl\nmov rax, [rax]\ntest byte ptr [rax+rbx*2+1], 4\njz short loc_133E\nmov [rsp+r13*4+438h+var_438], 1\nadd r12d, 1\nloc_133E:\nmovzx ebx, byte ptr [rbp+0]\nadd rbp, 1\ntest bl, bl\njnz short loc_1310\nloc_134A:\nmov rax, [rsp+438h+var_30]\nsub rax, fs:28h\njnz short loc_1375\nadd rsp, 410h\nmov eax, r12d\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1370:\nxor r12d, r12d\njmp short loc_134A\nloc_1375:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(unsigned __int8 *a1)\n{\n __int64 v1; // rbx\n unsigned __int8 *v2; // rbp\n unsigned int v3; // r12d\n const __int32_t *v4; // r14\n __int32_t v5; // ebx\n _DWORD v7[258]; // [rsp+0h] [rbp-438h] BYREF\n unsigned __int64 v8; // [rsp+408h] [rbp-30h]\n\n v1 = *a1;\n v8 = __readfsqword(0x28u);\n memset(v7, 0, 0x400uLL);\n if ( (_BYTE)v1 )\n {\n v2 = a1 + 1;\n v3 = 0;\n v4 = *__ctype_tolower_loc();\n do\n {\n v5 = v4[v1];\n if ( !v7[(char)v5] && ((*__ctype_b_loc())[(unsigned __int8)v5] & 0x400) != 0 )\n {\n v7[(char)v5] = 1;\n ++v3;\n }\n v1 = *v2++;\n }\n while ( (_BYTE)v1 );\n }\n else\n {\n return 0;\n }\n return v3;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\npush r14\nmov ecx, 80h\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 410h\nmovzx ebx, byte ptr [rbp+0]\nmov rax, fs:28h\nmov [rsp+438h+var_30], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\ntest bl, bl\njz short loc_1370\ncall ___ctype_tolower_loc\nadd rbp, 1\nxor r12d, r12d\nmov r14, [rax]\nnop dword ptr [rax+rax+00h]\nloc_1310:\nmov ebx, [r14+rbx*4]\nmovsx r13, bl\nmov eax, [rsp+r13*4+438h+var_438]\ntest eax, eax\njnz short loc_133E\ncall ___ctype_b_loc\nmovzx ebx, bl\nmov rax, [rax]\ntest byte ptr [rax+rbx*2+1], 4\njz short loc_133E\nmov [rsp+r13*4+438h+var_438], 1\nadd r12d, 1\nloc_133E:\nmovzx ebx, byte ptr [rbp+0]\nadd rbp, 1\ntest bl, bl\njnz short loc_1310\nloc_134A:\nmov rax, [rsp+438h+var_30]\nsub rax, fs:28h\njnz short loc_1375\nadd rsp, 410h\nmov eax, r12d\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1370:\nxor r12d, r12d\njmp short loc_134A\nloc_1375:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12C0(unsigned __int8 *a1)\n{\n __int64 v1; // rbx\n unsigned __int8 *v2; // rbp\n unsigned int v3; // r12d\n const __int32_t *v4; // r14\n __int32_t v5; // ebx\n _DWORD v7[258]; // [rsp+0h] [rbp-438h] BYREF\n unsigned __int64 v8; // [rsp+408h] [rbp-30h]\n\n v1 = *a1;\n v8 = __readfsqword(0x28u);\n memset(v7, 0, 0x400uLL);\n if ( (_BYTE)v1 )\n {\n v2 = a1 + 1;\n v3 = 0;\n v4 = *__ctype_tolower_loc();\n do\n {\n v5 = v4[v1];\n if ( !v7[(char)v5] && ((*__ctype_b_loc())[(unsigned __int8)v5] & 0x400) != 0 )\n {\n v7[(char)v5] = 1;\n ++v3;\n }\n v1 = *v2++;\n }\n while ( (_BYTE)v1 );\n }\n else\n {\n return 0;\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12C0(unsigned char *a1) {\n long long v1;\n unsigned char *v2;\n unsigned int v3;\n const __int32_t *v4;\n __int32_t v5;\n uint32_t v7[258];\n unsigned long long v8;\n v1 = *a1;\n v8 = __readfsqword(40u);\n memset(v7, 0, 1024uLL);\n if ((uint8_t)v1) {\n v2 = a1 + 1;\n v3 = 0;\n v4 = *__ctype_tolower_loc();\n do {\n v5 = v4[v1];\n if (!v7[(char)v5] &&\n ((*__ctype_b_loc())[(unsigned char)v5] & 1024) != 0) {\n v7[(char)v5] = 1;\n ++v3;\n }\n v1 = *v2++;\n } while ((uint8_t)v1);\n } else {\n return 0;\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(unsigned char *a1) {\n long long v1;\n unsigned char *v2;\n unsigned int v3;\n const __int32_t *v4;\n __int32_t v5;\n uint32_t v7[258];\n unsigned long long v8;\n v1 = *a1;\n v8 = __readfsqword(40u);\n memset(v7, 0, 1024uLL);\n if ((uint8_t)v1) {\n v2 = a1 + 1;\n v3 = 0;\n v4 = *__ctype_tolower_loc();\n do {\n v5 = v4[v1];\n if (!v7[(char)v5] &&\n ((*__ctype_b_loc())[(unsigned char)v5] & 1024) != 0) {\n v7[(char)v5] = 1;\n ++v3;\n }\n v1 = *v2++;\n } while ((uint8_t)v1);\n } else {\n return 0;\n }\n return v3;\n}" + }, + { + "index": "HumanEval-C-16", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int func0(const char *str) {\n int count = 0;\n int char_map[256] = {0};\n int index;\n for (index = 0; str[index]; index++) {\n char ch = tolower((unsigned char)str[index]);\n if (char_map[ch] == 0 && isalpha((unsigned char)ch)) {\n char_map[ch] = 1;\n count++;\n }\n }\n return count;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"\") == 0);\n assert(func0(\"abcde\") == 5);\n assert(func0(\"abcdecadeCADE\") == 5);\n assert(func0(\"aaaaAAAAaaaa\") == 1);\n assert(func0(\"Jerry jERRY JeRRRY\") == 4);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r14\nmov ecx, 80h\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 410h\nmovzx ebx, byte ptr [rbp+0]\nmov rax, fs:28h\nmov [rsp+438h+var_30], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\ntest bl, bl\njz short loc_1370\ncall ___ctype_tolower_loc\nadd rbp, 1\nxor r12d, r12d\nmov r14, [rax]\nnop dword ptr [rax+rax+00h]\nloc_1310:\nmov ebx, [r14+rbx*4]\nmovsx r13, bl\nmov eax, [rsp+r13*4+438h+var_438]\ntest eax, eax\njnz short loc_133E\ncall ___ctype_b_loc\nmovzx ebx, bl\nmov rax, [rax]\ntest byte ptr [rax+rbx*2+1], 4\njz short loc_133E\nmov [rsp+r13*4+438h+var_438], 1\nadd r12d, 1\nloc_133E:\nmovzx ebx, byte ptr [rbp+0]\nadd rbp, 1\ntest bl, bl\njnz short loc_1310\nloc_134A:\nmov rax, [rsp+438h+var_30]\nsub rax, fs:28h\njnz short loc_1375\nadd rsp, 410h\nmov eax, r12d\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1370:\nxor r12d, r12d\njmp short loc_134A\nloc_1375:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(unsigned __int8 *a1)\n{\n __int64 v1; // rbx\n unsigned __int8 *v2; // rbp\n unsigned int v3; // r12d\n const __int32_t *v4; // r14\n __int32_t v5; // ebx\n _DWORD v7[258]; // [rsp+0h] [rbp-438h] BYREF\n unsigned __int64 v8; // [rsp+408h] [rbp-30h]\n\n v1 = *a1;\n v8 = __readfsqword(0x28u);\n memset(v7, 0, 0x400uLL);\n if ( (_BYTE)v1 )\n {\n v2 = a1 + 1;\n v3 = 0;\n v4 = *__ctype_tolower_loc();\n do\n {\n v5 = v4[v1];\n if ( !v7[(char)v5] && ((*__ctype_b_loc())[(unsigned __int8)v5] & 0x400) != 0 )\n {\n v7[(char)v5] = 1;\n ++v3;\n }\n v1 = *v2++;\n }\n while ( (_BYTE)v1 );\n }\n else\n {\n return 0;\n }\n return v3;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\npush r14\nmov ecx, 80h\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 410h\nmovzx ebx, byte ptr [rbp+0]\nmov rax, fs:28h\nmov [rsp+438h+var_30], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\ntest bl, bl\njz short loc_1370\ncall ___ctype_tolower_loc\nadd rbp, 1\nxor r12d, r12d\nmov r14, [rax]\nnop dword ptr [rax+rax+00h]\nloc_1310:\nmov ebx, [r14+rbx*4]\nmovsx r13, bl\nmov eax, [rsp+r13*4+438h+var_438]\ntest eax, eax\njnz short loc_133E\ncall ___ctype_b_loc\nmovzx ebx, bl\nmov rax, [rax]\ntest byte ptr [rax+rbx*2+1], 4\njz short loc_133E\nmov [rsp+r13*4+438h+var_438], 1\nadd r12d, 1\nloc_133E:\nmovzx ebx, byte ptr [rbp+0]\nadd rbp, 1\ntest bl, bl\njnz short loc_1310\nloc_134A:\nmov rax, [rsp+438h+var_30]\nsub rax, fs:28h\njnz short loc_1375\nadd rsp, 410h\nmov eax, r12d\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1370:\nxor r12d, r12d\njmp short loc_134A\nloc_1375:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12C0(unsigned __int8 *a1)\n{\n __int64 v1; // rbx\n unsigned __int8 *v2; // rbp\n unsigned int v3; // r12d\n const __int32_t *v4; // r14\n __int32_t v5; // ebx\n _DWORD v7[258]; // [rsp+0h] [rbp-438h] BYREF\n unsigned __int64 v8; // [rsp+408h] [rbp-30h]\n\n v1 = *a1;\n v8 = __readfsqword(0x28u);\n memset(v7, 0, 0x400uLL);\n if ( (_BYTE)v1 )\n {\n v2 = a1 + 1;\n v3 = 0;\n v4 = *__ctype_tolower_loc();\n do\n {\n v5 = v4[v1];\n if ( !v7[(char)v5] && ((*__ctype_b_loc())[(unsigned __int8)v5] & 0x400) != 0 )\n {\n v7[(char)v5] = 1;\n ++v3;\n }\n v1 = *v2++;\n }\n while ( (_BYTE)v1 );\n }\n else\n {\n return 0;\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12C0(unsigned char *a1) {\n long long v1;\n unsigned char *v2;\n unsigned int v3;\n const __int32_t *v4;\n __int32_t v5;\n uint32_t v7[258];\n unsigned long long v8;\n v1 = *a1;\n v8 = __readfsqword(40u);\n memset(v7, 0, 1024uLL);\n if ((uint8_t)v1) {\n v2 = a1 + 1;\n v3 = 0;\n v4 = *__ctype_tolower_loc();\n do {\n v5 = v4[v1];\n if (!v7[(char)v5] &&\n ((*__ctype_b_loc())[(unsigned char)v5] & 1024) != 0) {\n v7[(char)v5] = 1;\n ++v3;\n }\n v1 = *v2++;\n } while ((uint8_t)v1);\n } else {\n return 0;\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(unsigned char *a1) {\n long long v1;\n unsigned char *v2;\n unsigned int v3;\n const __int32_t *v4;\n __int32_t v5;\n uint32_t v7[258];\n unsigned long long v8;\n v1 = *a1;\n v8 = __readfsqword(40u);\n memset(v7, 0, 1024uLL);\n if ((uint8_t)v1) {\n v2 = a1 + 1;\n v3 = 0;\n v4 = *__ctype_tolower_loc();\n do {\n v5 = v4[v1];\n if (!v7[(char)v5] &&\n ((*__ctype_b_loc())[(unsigned char)v5] & 1024) != 0) {\n v7[(char)v5] = 1;\n ++v3;\n }\n v1 = *v2++;\n } while ((uint8_t)v1);\n } else {\n return 0;\n }\n return v3;\n}" + }, + { + "index": "HumanEval-C-17", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int *func0(const char *music_string, int *count) {\n int *out = NULL;\n int size = 0;\n int capacity = 0;\n char current[3] = \"\";\n int music_string_length = strlen(music_string) + 1;\n char *temp_music_string = malloc(music_string_length + 1);\n strcpy(temp_music_string, music_string);\n strcat(temp_music_string, \" \");\n for (int i = 0; i < music_string_length; i++) {\n if (temp_music_string[i] == ' ') {\n if (strcmp(current, \"o\") == 0) {\n if (size == capacity) {\n capacity = capacity > 0 ? 2 * capacity : 4;\n out = realloc(out, capacity * sizeof(int));\n }\n out[size++] = 4;\n }\n if (strcmp(current, \"o|\") == 0) {\n if (size == capacity) {\n capacity = capacity > 0 ? 2 * capacity : 4;\n out = realloc(out, capacity * sizeof(int));\n }\n out[size++] = 2;\n }\n if (strcmp(current, \".|\") == 0) {\n if (size == capacity) {\n capacity = capacity > 0 ? 2 * capacity : 4;\n out = realloc(out, capacity * sizeof(int));\n }\n out[size++] = 1;\n }\n strcpy(current, \"\");\n } else {\n size_t len = strlen(current);\n if (len < sizeof(current) - 1) {\n current[len] = temp_music_string[i];\n current[len + 1] = '\\0';\n }\n }\n }\n free(temp_music_string);\n *count = size;\n return out;\n}", + "test": "#include \n#include \n\nint issame(const int *a, int a_size, const int *b, int b_size) {\n if (a_size != b_size) return 0;\n for (int i = 0; i < a_size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int count;\n int *result;\n\n result = func0(\"\", &count);\n assert(issame(result, count, (const int[]){}, 0));\n free(result);\n\n result = func0(\"o o o o\", &count);\n assert(issame(result, count, (const int[]){4, 4, 4, 4}, 4));\n free(result);\n\n result = func0(\".| .| .| .|\", &count);\n assert(issame(result, count, (const int[]){1, 1, 1, 1}, 4));\n free(result);\n\n result = func0(\"o| o| .| .| o o o o\", &count);\n assert(issame(result, count, (const int[]){2, 2, 1, 1, 4, 4, 4, 4}, 8));\n free(result);\n\n result = func0(\"o| .| o| .| o o| o o|\", &count);\n assert(issame(result, count, (const int[]){2, 1, 2, 1, 4, 2, 4, 2}, 8));\n free(result);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+s], rdi\nmov [rbp+var_50], rsi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+ptr], 0\nmov [rbp+var_38], 0\nmov [rbp+var_34], 0\nmov word ptr [rbp+s1], 0\nmov [rbp+var_9], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nadd eax, 1\nmov [rbp+var_2C], eax\nmov eax, [rbp+var_2C]\nadd eax, 1\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+dest], rax\nmov rdx, [rbp+s]\nmov rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\nmov rax, [rbp+dest]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+dest]\nadd rax, rdx\nmov word ptr [rax], 20h ; ' '\nmov [rbp+var_30], 0\njmp loc_1494\nloc_12CC:\nmov eax, [rbp+var_30]\nmovsxd rdx, eax\nmov rax, [rbp+dest]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njnz loc_144F\nlea rax, [rbp+s1]\nlea rdx, s2; \"o\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_135B\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_34]\njnz short loc_133B\ncmp [rbp+var_34], 0\njle short loc_1313\nmov eax, [rbp+var_34]\nadd eax, eax\njmp short loc_1318\nloc_1313:\nmov eax, 4\nloc_1318:\nmov [rbp+var_34], eax\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nmov rsi, rdx; size\nmov rdi, rax; ptr\ncall _realloc\nmov [rbp+ptr], rax\nloc_133B:\nmov eax, [rbp+var_38]\nlea edx, [rax+1]\nmov [rbp+var_38], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov dword ptr [rax], 4\nloc_135B:\nlea rax, [rbp+s1]\nlea rdx, aO; \"o|\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_13D2\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_34]\njnz short loc_13B2\ncmp [rbp+var_34], 0\njle short loc_138A\nmov eax, [rbp+var_34]\nadd eax, eax\njmp short loc_138F\nloc_138A:\nmov eax, 4\nloc_138F:\nmov [rbp+var_34], eax\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nmov rsi, rdx; size\nmov rdi, rax; ptr\ncall _realloc\nmov [rbp+ptr], rax\nloc_13B2:\nmov eax, [rbp+var_38]\nlea edx, [rax+1]\nmov [rbp+var_38], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov dword ptr [rax], 2\nloc_13D2:\nlea rax, [rbp+s1]\nlea rdx, asc_200D; \".|\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1449\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_34]\njnz short loc_1429\ncmp [rbp+var_34], 0\njle short loc_1401\nmov eax, [rbp+var_34]\nadd eax, eax\njmp short loc_1406\nloc_1401:\nmov eax, 4\nloc_1406:\nmov [rbp+var_34], eax\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nmov rsi, rdx; size\nmov rdi, rax; ptr\ncall _realloc\nmov [rbp+ptr], rax\nloc_1429:\nmov eax, [rbp+var_38]\nlea edx, [rax+1]\nmov [rbp+var_38], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov dword ptr [rax], 1\nloc_1449:\nmov [rbp+s1], 0\njmp short loc_1490\nloc_144F:\nlea rax, [rbp+s1]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_18], rax\ncmp [rbp+var_18], 1\nja short loc_1490\nmov eax, [rbp+var_30]\nmovsxd rdx, eax\nmov rax, [rbp+dest]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nlea rcx, [rbp+s1]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov [rdx], al\nmov rax, [rbp+var_18]\nadd rax, 1\nmov [rbp+rax+s1], 0\nloc_1490:\nadd [rbp+var_30], 1\nloc_1494:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_2C]\njl loc_12CC\nmov rax, [rbp+dest]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_50]\nmov edx, [rbp+var_38]\nmov [rax], edx\nmov rax, [rbp+ptr]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_14CD\ncall ___stack_chk_fail\nlocret_14CD:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, _DWORD *a2)\n{\n int v2; // eax\n int v3; // eax\n int v4; // eax\n int v5; // eax\n int v6; // eax\n int v7; // eax\n int v8; // eax\n int v10; // [rsp+18h] [rbp-38h]\n int v11; // [rsp+1Ch] [rbp-34h]\n int i; // [rsp+20h] [rbp-30h]\n _BYTE v13[12]; // [rsp+24h] [rbp-2Ch]\n char *dest; // [rsp+30h] [rbp-20h]\n size_t v15; // [rsp+38h] [rbp-18h]\n char s1[2]; // [rsp+45h] [rbp-Bh] BYREF\n char v17; // [rsp+47h] [rbp-9h]\n unsigned __int64 v18; // [rsp+48h] [rbp-8h]\n\n v18 = __readfsqword(0x28u);\n *(_DWORD *)&v13[8] = 0;\n v10 = 0;\n v11 = 0;\n *(_WORD *)s1 = 0;\n v17 = 0;\n v2 = strlen(a1);\n *(_QWORD *)v13 = (unsigned int)(v2 + 1);\n dest = (char *)malloc(v2 + 2);\n strcpy(dest, a1);\n *(_WORD *)&dest[strlen(dest)] = 32;\n for ( i = 0; i < *(int *)v13; ++i )\n {\n if ( dest[i] == 32 )\n {\n if ( !strcmp(s1, \"o\") )\n {\n if ( v10 == v11 )\n {\n if ( v11 <= 0 )\n v3 = 4;\n else\n v3 = 2 * v11;\n v11 = v3;\n *(_QWORD *)&v13[4] = realloc(*(void **)&v13[4], 4LL * v3);\n }\n v4 = v10++;\n *(_DWORD *)(4LL * v4 + *(_QWORD *)&v13[4]) = 4;\n }\n if ( !strcmp(s1, \"o|\") )\n {\n if ( v10 == v11 )\n {\n if ( v11 <= 0 )\n v5 = 4;\n else\n v5 = 2 * v11;\n v11 = v5;\n *(_QWORD *)&v13[4] = realloc(*(void **)&v13[4], 4LL * v5);\n }\n v6 = v10++;\n *(_DWORD *)(4LL * v6 + *(_QWORD *)&v13[4]) = 2;\n }\n if ( !strcmp(s1, \".|\") )\n {\n if ( v10 == v11 )\n {\n if ( v11 <= 0 )\n v7 = 4;\n else\n v7 = 2 * v11;\n v11 = v7;\n *(_QWORD *)&v13[4] = realloc(*(void **)&v13[4], 4LL * v7);\n }\n v8 = v10++;\n *(_DWORD *)(4LL * v8 + *(_QWORD *)&v13[4]) = 1;\n }\n s1[0] = 0;\n }\n else\n {\n v15 = strlen(s1);\n if ( v15 <= 1 )\n {\n s1[v15] = dest[i];\n s1[v15 + 1] = 0;\n }\n }\n }\n free(dest);\n *a2 = v10;\n return *(_QWORD *)&v13[4];\n}", + "ida_strip_asm": "sub_1229:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+s], rdi\nmov [rbp+var_50], rsi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+ptr], 0\nmov [rbp+var_38], 0\nmov [rbp+var_34], 0\nmov word ptr [rbp+s1], 0\nmov [rbp+var_9], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nadd eax, 1\nmov [rbp+var_2C], eax\nmov eax, [rbp+var_2C]\nadd eax, 1\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+dest], rax\nmov rdx, [rbp+s]\nmov rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\nmov rax, [rbp+dest]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+dest]\nadd rax, rdx\nmov word ptr [rax], 20h ; ' '\nmov [rbp+var_30], 0\njmp loc_1494\nloc_12CC:\nmov eax, [rbp+var_30]\nmovsxd rdx, eax\nmov rax, [rbp+dest]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njnz loc_144F\nlea rax, [rbp+s1]\nlea rdx, s2; \"o\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_135B\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_34]\njnz short loc_133B\ncmp [rbp+var_34], 0\njle short loc_1313\nmov eax, [rbp+var_34]\nadd eax, eax\njmp short loc_1318\nloc_1313:\nmov eax, 4\nloc_1318:\nmov [rbp+var_34], eax\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nmov rsi, rdx; size\nmov rdi, rax; ptr\ncall _realloc\nmov [rbp+ptr], rax\nloc_133B:\nmov eax, [rbp+var_38]\nlea edx, [rax+1]\nmov [rbp+var_38], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov dword ptr [rax], 4\nloc_135B:\nlea rax, [rbp+s1]\nlea rdx, aO; \"o|\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_13D2\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_34]\njnz short loc_13B2\ncmp [rbp+var_34], 0\njle short loc_138A\nmov eax, [rbp+var_34]\nadd eax, eax\njmp short loc_138F\nloc_138A:\nmov eax, 4\nloc_138F:\nmov [rbp+var_34], eax\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nmov rsi, rdx; size\nmov rdi, rax; ptr\ncall _realloc\nmov [rbp+ptr], rax\nloc_13B2:\nmov eax, [rbp+var_38]\nlea edx, [rax+1]\nmov [rbp+var_38], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov dword ptr [rax], 2\nloc_13D2:\nlea rax, [rbp+s1]\nlea rdx, asc_200D; \".|\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1449\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_34]\njnz short loc_1429\ncmp [rbp+var_34], 0\njle short loc_1401\nmov eax, [rbp+var_34]\nadd eax, eax\njmp short loc_1406\nloc_1401:\nmov eax, 4\nloc_1406:\nmov [rbp+var_34], eax\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nmov rsi, rdx; size\nmov rdi, rax; ptr\ncall _realloc\nmov [rbp+ptr], rax\nloc_1429:\nmov eax, [rbp+var_38]\nlea edx, [rax+1]\nmov [rbp+var_38], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov dword ptr [rax], 1\nloc_1449:\nmov [rbp+s1], 0\njmp short loc_1490\nloc_144F:\nlea rax, [rbp+s1]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_18], rax\ncmp [rbp+var_18], 1\nja short loc_1490\nmov eax, [rbp+var_30]\nmovsxd rdx, eax\nmov rax, [rbp+dest]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nlea rcx, [rbp+s1]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov [rdx], al\nmov rax, [rbp+var_18]\nadd rax, 1\nmov [rbp+rax+s1], 0\nloc_1490:\nadd [rbp+var_30], 1\nloc_1494:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_2C]\njl loc_12CC\nmov rax, [rbp+dest]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_50]\nmov edx, [rbp+var_38]\nmov [rax], edx\nmov rax, [rbp+ptr]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_14CD\ncall ___stack_chk_fail\nlocret_14CD:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1229(const char *a1, _DWORD *a2)\n{\n int v2; // eax\n int v3; // eax\n int v4; // eax\n int v5; // eax\n int v6; // eax\n int v7; // eax\n int v8; // eax\n int v10; // [rsp+18h] [rbp-38h]\n int v11; // [rsp+1Ch] [rbp-34h]\n int i; // [rsp+20h] [rbp-30h]\n _BYTE v13[12]; // [rsp+24h] [rbp-2Ch]\n char *dest; // [rsp+30h] [rbp-20h]\n size_t v15; // [rsp+38h] [rbp-18h]\n char s1[2]; // [rsp+45h] [rbp-Bh] BYREF\n char v17; // [rsp+47h] [rbp-9h]\n unsigned __int64 v18; // [rsp+48h] [rbp-8h]\n\n v18 = __readfsqword(0x28u);\n *(_DWORD *)&v13[8] = 0;\n v10 = 0;\n v11 = 0;\n *(_WORD *)s1 = 0;\n v17 = 0;\n v2 = strlen(a1);\n *(_QWORD *)v13 = (unsigned int)(v2 + 1);\n dest = (char *)malloc(v2 + 2);\n strcpy(dest, a1);\n *(_WORD *)&dest[strlen(dest)] = 32;\n for ( i = 0; i < *(int *)v13; ++i )\n {\n if ( dest[i] == 32 )\n {\n if ( !strcmp(s1, \"o\") )\n {\n if ( v10 == v11 )\n {\n if ( v11 <= 0 )\n v3 = 4;\n else\n v3 = 2 * v11;\n v11 = v3;\n *(_QWORD *)&v13[4] = realloc(*(void **)&v13[4], 4LL * v3);\n }\n v4 = v10++;\n *(_DWORD *)(4LL * v4 + *(_QWORD *)&v13[4]) = 4;\n }\n if ( !strcmp(s1, \"o|\") )\n {\n if ( v10 == v11 )\n {\n if ( v11 <= 0 )\n v5 = 4;\n else\n v5 = 2 * v11;\n v11 = v5;\n *(_QWORD *)&v13[4] = realloc(*(void **)&v13[4], 4LL * v5);\n }\n v6 = v10++;\n *(_DWORD *)(4LL * v6 + *(_QWORD *)&v13[4]) = 2;\n }\n if ( !strcmp(s1, \".|\") )\n {\n if ( v10 == v11 )\n {\n if ( v11 <= 0 )\n v7 = 4;\n else\n v7 = 2 * v11;\n v11 = v7;\n *(_QWORD *)&v13[4] = realloc(*(void **)&v13[4], 4LL * v7);\n }\n v8 = v10++;\n *(_DWORD *)(4LL * v8 + *(_QWORD *)&v13[4]) = 1;\n }\n s1[0] = 0;\n }\n else\n {\n v15 = strlen(s1);\n if ( v15 <= 1 )\n {\n s1[v15] = dest[i];\n s1[v15 + 1] = 0;\n }\n }\n }\n free(dest);\n *a2 = v10;\n return *(_QWORD *)&v13[4];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1229(const char *a1, uint32_t *a2) {\n int v2;\n int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n int v8;\n int v10;\n int v11;\n int i;\n uint8_t v13[12];\n char *dest;\n unsigned int v15;\n char s1[2];\n char v17;\n unsigned long long v18;\n v18 = __readfsqword(40u);\n *(uint32_t *)&v13[8] = 0;\n v10 = 0;\n v11 = 0;\n *(unsigned short *)s1 = 0;\n v17 = 0;\n v2 = strlen(a1);\n *(uint64_t *)v13 = (unsigned int)(v2 + 1);\n dest = (char *)malloc(v2 + 2);\n strcpy(dest, a1);\n *(unsigned short *)&dest[strlen(dest)] = 32;\n for (i = 0; i < *(int *)v13; ++i) {\n if (dest[i] == 32) {\n if (!strcmp(s1, \"o\")) {\n if (v10 == v11) {\n if (v11 <= 0)\n v3 = 4;\n else\n v3 = 2 * v11;\n v11 = v3;\n *(uint64_t *)&v13[4] = realloc(*(void **)&v13[4], 4LL * v3);\n }\n v4 = v10++;\n *(uint32_t *)(4LL * v4 + *(uint64_t *)&v13[4]) = 4;\n }\n if (!strcmp(s1, \"o|\")) {\n if (v10 == v11) {\n if (v11 <= 0)\n v5 = 4;\n else\n v5 = 2 * v11;\n v11 = v5;\n *(uint64_t *)&v13[4] = realloc(*(void **)&v13[4], 4LL * v5);\n }\n v6 = v10++;\n *(uint32_t *)(4LL * v6 + *(uint64_t *)&v13[4]) = 2;\n }\n if (!strcmp(s1, \".|\")) {\n if (v10 == v11) {\n if (v11 <= 0)\n v7 = 4;\n else\n v7 = 2 * v11;\n v11 = v7;\n *(uint64_t *)&v13[4] = realloc(*(void **)&v13[4], 4LL * v7);\n }\n v8 = v10++;\n *(uint32_t *)(4LL * v8 + *(uint64_t *)&v13[4]) = 1;\n }\n s1[0] = 0;\n } else {\n v15 = strlen(s1);\n if (v15 <= 1) {\n s1[v15] = dest[i];\n s1[v15 + 1] = 0;\n }\n }\n }\n free(dest);\n *a2 = v10;\n return *(uint64_t *)&v13[4];\n}", + "ida_pseudo_norm": "long long func0(const char *a1, uint32_t *a2) {\n int v2;\n int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n int v8;\n int v10;\n int v11;\n int i;\n uint8_t v13[12];\n char *dest;\n unsigned int v15;\n char s1[2];\n char v17;\n unsigned long long v18;\n v18 = __readfsqword(40u);\n *(uint32_t *)&v13[8] = 0;\n v10 = 0;\n v11 = 0;\n *(unsigned short *)s1 = 0;\n v17 = 0;\n v2 = strlen(a1);\n *(uint64_t *)v13 = (unsigned int)(v2 + 1);\n dest = (char *)malloc(v2 + 2);\n strcpy(dest, a1);\n *(unsigned short *)&dest[strlen(dest)] = 32;\n for (i = 0; i < *(int *)v13; ++i) {\n if (dest[i] == 32) {\n if (!strcmp(s1, \"o\")) {\n if (v10 == v11) {\n if (v11 <= 0)\n v3 = 4;\n else\n v3 = 2 * v11;\n v11 = v3;\n *(uint64_t *)&v13[4] = realloc(*(void **)&v13[4], 4LL * v3);\n }\n v4 = v10++;\n *(uint32_t *)(4LL * v4 + *(uint64_t *)&v13[4]) = 4;\n }\n if (!strcmp(s1, \"o|\")) {\n if (v10 == v11) {\n if (v11 <= 0)\n v5 = 4;\n else\n v5 = 2 * v11;\n v11 = v5;\n *(uint64_t *)&v13[4] = realloc(*(void **)&v13[4], 4LL * v5);\n }\n v6 = v10++;\n *(uint32_t *)(4LL * v6 + *(uint64_t *)&v13[4]) = 2;\n }\n if (!strcmp(s1, \".|\")) {\n if (v10 == v11) {\n if (v11 <= 0)\n v7 = 4;\n else\n v7 = 2 * v11;\n v11 = v7;\n *(uint64_t *)&v13[4] = realloc(*(void **)&v13[4], 4LL * v7);\n }\n v8 = v10++;\n *(uint32_t *)(4LL * v8 + *(uint64_t *)&v13[4]) = 1;\n }\n s1[0] = 0;\n } else {\n v15 = strlen(s1);\n if (v15 <= 1) {\n s1[v15] = dest[i];\n s1[v15 + 1] = 0;\n }\n }\n }\n free(dest);\n *a2 = v10;\n return *(uint64_t *)&v13[4];\n}" + }, + { + "index": "HumanEval-C-17", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int *func0(const char *music_string, int *count) {\n int *out = NULL;\n int size = 0;\n int capacity = 0;\n char current[3] = \"\";\n int music_string_length = strlen(music_string) + 1;\n char *temp_music_string = malloc(music_string_length + 1);\n strcpy(temp_music_string, music_string);\n strcat(temp_music_string, \" \");\n for (int i = 0; i < music_string_length; i++) {\n if (temp_music_string[i] == ' ') {\n if (strcmp(current, \"o\") == 0) {\n if (size == capacity) {\n capacity = capacity > 0 ? 2 * capacity : 4;\n out = realloc(out, capacity * sizeof(int));\n }\n out[size++] = 4;\n }\n if (strcmp(current, \"o|\") == 0) {\n if (size == capacity) {\n capacity = capacity > 0 ? 2 * capacity : 4;\n out = realloc(out, capacity * sizeof(int));\n }\n out[size++] = 2;\n }\n if (strcmp(current, \".|\") == 0) {\n if (size == capacity) {\n capacity = capacity > 0 ? 2 * capacity : 4;\n out = realloc(out, capacity * sizeof(int));\n }\n out[size++] = 1;\n }\n strcpy(current, \"\");\n } else {\n size_t len = strlen(current);\n if (len < sizeof(current) - 1) {\n current[len] = temp_music_string[i];\n current[len + 1] = '\\0';\n }\n }\n }\n free(temp_music_string);\n *count = size;\n return out;\n}", + "test": "#include \n#include \n\nint issame(const int *a, int a_size, const int *b, int b_size) {\n if (a_size != b_size) return 0;\n for (int i = 0; i < a_size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int count;\n int *result;\n\n result = func0(\"\", &count);\n assert(issame(result, count, (const int[]){}, 0));\n free(result);\n\n result = func0(\"o o o o\", &count);\n assert(issame(result, count, (const int[]){4, 4, 4, 4}, 4));\n free(result);\n\n result = func0(\".| .| .| .|\", &count);\n assert(issame(result, count, (const int[]){1, 1, 1, 1}, 4));\n free(result);\n\n result = func0(\"o| o| .| .| o o o o\", &count);\n assert(issame(result, count, (const int[]){2, 2, 1, 1, 4, 4, 4, 4}, 8));\n free(result);\n\n result = func0(\"o| .| o| .| o o| o o|\", &count);\n assert(issame(result, count, (const int[]){2, 1, 2, 1, 4, 2, 4, 2}, 8));\n free(result);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 38h\nmov r12, rdi\nmov [rsp+68h+var_50], rsi\nmov rax, fs:28h\nmov [rsp+68h+var_40], rax\nxor eax, eax\nmov word ptr [rsp+68h+s1], 0\nmov [rsp+68h+var_41], 0\ncall _strlen\nmov rbp, rax\nlea ebx, [rax+2]\nmovsxd rbx, ebx\nmov rdi, rbx; size\ncall _malloc\nmov r15, rax\nmov [rsp+68h+var_58], rax\nmov rdx, rbx\nmov rsi, r12\nmov rdi, rax\ncall ___strcpy_chk\nmov rdx, rbx\nlea rsi, unk_2004\nmov rdi, r15\ncall ___strcat_chk\nlea eax, [rbp+1]\ntest eax, eax\njle loc_1438\nmov rbx, r15\nmov ebp, ebp\nlea r15, [r15+rbp+1]\nmov r14d, 0\nmov ebp, 0\nmov [rsp+68h+ptr], 0\nlea r13, [rsp+68h+s1]\njmp loc_138C\nloc_12F0:\nlea rsi, aOOOOOO+12h; s2\nmov rdi, r13; s1\ncall _strcmp\ntest eax, eax\njnz short loc_131E\ncmp ebp, r14d\njz loc_13B4\nloc_130C:\nmovsxd rax, ebp\nmov rcx, [rsp+68h+ptr]\nmov dword ptr [rcx+rax*4], 4\nlea ebp, [rbp+1]\nloc_131E:\nlea rsi, aOOOOOO_0+13h; s2\nmov rdi, r13; s1\ncall _strcmp\ntest eax, eax\njnz short loc_134C\ncmp ebp, r14d\njz loc_13E0\nloc_133A:\nmovsxd rax, ebp\nmov rdx, [rsp+68h+ptr]\nmov dword ptr [rdx+rax*4], 2\nlea ebp, [rbp+1]\nloc_134C:\nlea rsi, asc_2006+9; s2\nmov rdi, r13; s1\ncall _strcmp\ntest eax, eax\njnz short loc_137A\ncmp ebp, r14d\njz loc_140C\nloc_1368:\nmovsxd rax, ebp\nmov rcx, [rsp+68h+ptr]\nmov dword ptr [rcx+rax*4], 1\nlea ebp, [rbp+1]\nloc_137A:\nmov [rsp+68h+s1], 0\nloc_137F:\nadd rbx, 1\ncmp rbx, r15\njz loc_1446\nloc_138C:\nmovzx r12d, byte ptr [rbx]\ncmp r12b, 20h ; ' '\njz loc_12F0\nmov rdi, r13; s\ncall _strlen\ncmp rax, 1\nja short loc_137F\nmov [rsp+rax+68h+s1], r12b\nmov [rsp+rax+68h+s1+1], 0\njmp short loc_137F\nloc_13B4:\nlea eax, [r14+r14]\ntest r14d, r14d\nmov r14d, 4\ncmovg r14d, eax\nmovsxd rsi, r14d\nshl rsi, 2; size\nmov rdi, [rsp+68h+ptr]; ptr\ncall _realloc\nmov [rsp+68h+ptr], rax\njmp loc_130C\nloc_13E0:\nlea eax, [r14+r14]\ntest r14d, r14d\nmov r14d, 4\ncmovg r14d, eax\nmovsxd rsi, r14d\nshl rsi, 2; size\nmov rdi, [rsp+68h+ptr]; ptr\ncall _realloc\nmov [rsp+68h+ptr], rax\njmp loc_133A\nloc_140C:\nlea eax, [r14+r14]\ntest r14d, r14d\nmov r14d, 4\ncmovg r14d, eax\nmovsxd rsi, r14d\nshl rsi, 2; size\nmov rdi, [rsp+68h+ptr]; ptr\ncall _realloc\nmov [rsp+68h+ptr], rax\njmp loc_1368\nloc_1438:\nmov ebp, 0\nmov [rsp+68h+ptr], 0\nloc_1446:\nmov rdi, [rsp+68h+var_58]; ptr\ncall _free\nmov rax, [rsp+68h+var_50]\nmov [rax], ebp\nmov rax, [rsp+68h+var_40]\nsub rax, fs:28h\njnz short loc_147B\nmov rax, [rsp+68h+ptr]\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_147B:\ncall ___stack_chk_fail", + "ida_pseudo": "void *__fastcall func0(const char *a1, _DWORD *a2)\n{\n unsigned int v2; // ebp\n size_t v3; // rbx\n void *v4; // r15\n char *v5; // rbx\n __int64 v6; // r15\n int v7; // r14d\n int v8; // ebp\n char v9; // r12\n size_t v10; // rax\n int v11; // eax\n bool v12; // cc\n int v13; // eax\n int v14; // eax\n void *ptr; // [rsp+8h] [rbp-60h]\n void *v17; // [rsp+10h] [rbp-58h]\n char s1[2]; // [rsp+25h] [rbp-43h] BYREF\n char v19; // [rsp+27h] [rbp-41h]\n unsigned __int64 v20; // [rsp+28h] [rbp-40h]\n\n v20 = __readfsqword(0x28u);\n *(_WORD *)s1 = 0;\n v19 = 0;\n v2 = strlen(a1);\n v3 = (int)(v2 + 2);\n v4 = malloc(v3);\n v17 = v4;\n __strcpy_chk(v4, a1, v3);\n __strcat_chk(v4, &unk_2004, v3);\n if ( (int)(v2 + 1) <= 0 )\n {\n v8 = 0;\n ptr = 0LL;\n }\n else\n {\n v5 = (char *)v4;\n v6 = (__int64)v4 + v2 + 1;\n v7 = 0;\n v8 = 0;\n ptr = 0LL;\n do\n {\n v9 = *v5;\n if ( *v5 == 32 )\n {\n if ( !strcmp(s1, \"o\") )\n {\n if ( v8 == v7 )\n {\n v11 = 2 * v7;\n v12 = v7 <= 0;\n v7 = 4;\n if ( !v12 )\n v7 = v11;\n ptr = realloc(ptr, 4LL * v7);\n }\n *((_DWORD *)ptr + v8++) = 4;\n }\n if ( !strcmp(s1, \"o|\") )\n {\n if ( v8 == v7 )\n {\n v13 = 2 * v7;\n v12 = v7 <= 0;\n v7 = 4;\n if ( !v12 )\n v7 = v13;\n ptr = realloc(ptr, 4LL * v7);\n }\n *((_DWORD *)ptr + v8++) = 2;\n }\n if ( !strcmp(s1, \".|\") )\n {\n if ( v8 == v7 )\n {\n v14 = 2 * v7;\n v12 = v7 <= 0;\n v7 = 4;\n if ( !v12 )\n v7 = v14;\n ptr = realloc(ptr, 4LL * v7);\n }\n *((_DWORD *)ptr + v8++) = 1;\n }\n s1[0] = 0;\n }\n else\n {\n v10 = strlen(s1);\n if ( v10 <= 1 )\n {\n s1[v10] = v9;\n s1[v10 + 1] = 0;\n }\n }\n ++v5;\n }\n while ( v5 != (char *)v6 );\n }\n free(v17);\n *a2 = v8;\n return ptr;\n}", + "ida_strip_asm": "sub_1249:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 38h\nmov r12, rdi\nmov [rsp+68h+var_50], rsi\nmov rax, fs:28h\nmov [rsp+68h+var_40], rax\nxor eax, eax\nmov word ptr [rsp+68h+s1], 0\nmov [rsp+68h+var_41], 0\ncall _strlen\nmov rbp, rax\nlea ebx, [rax+2]\nmovsxd rbx, ebx\nmov rdi, rbx; size\ncall _malloc\nmov r15, rax\nmov [rsp+68h+var_58], rax\nmov rdx, rbx\nmov rsi, r12\nmov rdi, rax\ncall ___strcpy_chk\nmov rdx, rbx\nlea rsi, unk_2004\nmov rdi, r15\ncall ___strcat_chk\nlea eax, [rbp+1]\ntest eax, eax\njle loc_1438\nmov rbx, r15\nmov ebp, ebp\nlea r15, [r15+rbp+1]\nmov r14d, 0\nmov ebp, 0\nmov [rsp+68h+ptr], 0\nlea r13, [rsp+68h+s1]\njmp loc_138C\nloc_12F0:\nlea rsi, aOOOOOO+12h; s2\nmov rdi, r13; s1\ncall _strcmp\ntest eax, eax\njnz short loc_131E\ncmp ebp, r14d\njz loc_13B4\nloc_130C:\nmovsxd rax, ebp\nmov rcx, [rsp+68h+ptr]\nmov dword ptr [rcx+rax*4], 4\nlea ebp, [rbp+1]\nloc_131E:\nlea rsi, aOOOOOO_0+13h; s2\nmov rdi, r13; s1\ncall _strcmp\ntest eax, eax\njnz short loc_134C\ncmp ebp, r14d\njz loc_13E0\nloc_133A:\nmovsxd rax, ebp\nmov rdx, [rsp+68h+ptr]\nmov dword ptr [rdx+rax*4], 2\nlea ebp, [rbp+1]\nloc_134C:\nlea rsi, asc_2006+9; s2\nmov rdi, r13; s1\ncall _strcmp\ntest eax, eax\njnz short loc_137A\ncmp ebp, r14d\njz loc_140C\nloc_1368:\nmovsxd rax, ebp\nmov rcx, [rsp+68h+ptr]\nmov dword ptr [rcx+rax*4], 1\nlea ebp, [rbp+1]\nloc_137A:\nmov [rsp+68h+s1], 0\nloc_137F:\nadd rbx, 1\ncmp rbx, r15\njz loc_1446\nloc_138C:\nmovzx r12d, byte ptr [rbx]\ncmp r12b, 20h ; ' '\njz loc_12F0\nmov rdi, r13; s\ncall _strlen\ncmp rax, 1\nja short loc_137F\nmov [rsp+rax+68h+s1], r12b\nmov [rsp+rax+68h+s1+1], 0\njmp short loc_137F\nloc_13B4:\nlea eax, [r14+r14]\ntest r14d, r14d\nmov r14d, 4\ncmovg r14d, eax\nmovsxd rsi, r14d\nshl rsi, 2; size\nmov rdi, [rsp+68h+ptr]; ptr\ncall _realloc\nmov [rsp+68h+ptr], rax\njmp loc_130C\nloc_13E0:\nlea eax, [r14+r14]\ntest r14d, r14d\nmov r14d, 4\ncmovg r14d, eax\nmovsxd rsi, r14d\nshl rsi, 2; size\nmov rdi, [rsp+68h+ptr]; ptr\ncall _realloc\nmov [rsp+68h+ptr], rax\njmp loc_133A\nloc_140C:\nlea eax, [r14+r14]\ntest r14d, r14d\nmov r14d, 4\ncmovg r14d, eax\nmovsxd rsi, r14d\nshl rsi, 2; size\nmov rdi, [rsp+68h+ptr]; ptr\ncall _realloc\nmov [rsp+68h+ptr], rax\njmp loc_1368\nloc_1438:\nmov ebp, 0\nmov [rsp+68h+ptr], 0\nloc_1446:\nmov rdi, [rsp+68h+var_58]; ptr\ncall _free\nmov rax, [rsp+68h+var_50]\nmov [rax], ebp\nmov rax, [rsp+68h+var_40]\nsub rax, fs:28h\njnz short loc_147B\nmov rax, [rsp+68h+ptr]\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_147B:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "void *__fastcall sub_1249(const char *a1, _DWORD *a2)\n{\n unsigned int v2; // ebp\n size_t v3; // rbx\n void *v4; // r15\n char *v5; // rbx\n __int64 v6; // r15\n int v7; // r14d\n int v8; // ebp\n char v9; // r12\n size_t v10; // rax\n int v11; // eax\n bool v12; // cc\n int v13; // eax\n int v14; // eax\n void *ptr; // [rsp+8h] [rbp-60h]\n void *v17; // [rsp+10h] [rbp-58h]\n char s1[2]; // [rsp+25h] [rbp-43h] BYREF\n char v19; // [rsp+27h] [rbp-41h]\n unsigned __int64 v20; // [rsp+28h] [rbp-40h]\n\n v20 = __readfsqword(0x28u);\n *(_WORD *)s1 = 0;\n v19 = 0;\n v2 = strlen(a1);\n v3 = (int)(v2 + 2);\n v4 = malloc(v3);\n v17 = v4;\n __strcpy_chk(v4, a1, v3);\n __strcat_chk(v4, &unk_2004, v3);\n if ( (int)(v2 + 1) <= 0 )\n {\n v8 = 0;\n ptr = 0LL;\n }\n else\n {\n v5 = (char *)v4;\n v6 = (__int64)v4 + v2 + 1;\n v7 = 0;\n v8 = 0;\n ptr = 0LL;\n do\n {\n v9 = *v5;\n if ( *v5 == 32 )\n {\n if ( !strcmp(s1, \"o\") )\n {\n if ( v8 == v7 )\n {\n v11 = 2 * v7;\n v12 = v7 <= 0;\n v7 = 4;\n if ( !v12 )\n v7 = v11;\n ptr = realloc(ptr, 4LL * v7);\n }\n *((_DWORD *)ptr + v8++) = 4;\n }\n if ( !strcmp(s1, \"o|\") )\n {\n if ( v8 == v7 )\n {\n v13 = 2 * v7;\n v12 = v7 <= 0;\n v7 = 4;\n if ( !v12 )\n v7 = v13;\n ptr = realloc(ptr, 4LL * v7);\n }\n *((_DWORD *)ptr + v8++) = 2;\n }\n if ( !strcmp(s1, \".|\") )\n {\n if ( v8 == v7 )\n {\n v14 = 2 * v7;\n v12 = v7 <= 0;\n v7 = 4;\n if ( !v12 )\n v7 = v14;\n ptr = realloc(ptr, 4LL * v7);\n }\n *((_DWORD *)ptr + v8++) = 1;\n }\n s1[0] = 0;\n }\n else\n {\n v10 = strlen(s1);\n if ( v10 <= 1 )\n {\n s1[v10] = v9;\n s1[v10 + 1] = 0;\n }\n }\n ++v5;\n }\n while ( v5 != (char *)v6 );\n }\n free(v17);\n *a2 = v8;\n return ptr;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1249(const char *a1, uint32_t *a2) {\n unsigned int v2;\n unsigned int v3;\n void *v4;\n char *v5;\n long long v6;\n int v7;\n int v8;\n char v9;\n unsigned int v10;\n int v11;\n bool v12;\n int v13;\n int v14;\n void *ptr;\n void *v17;\n char s1[2];\n char v19;\n unsigned long long v20;\n v20 = __readfsqword(40u);\n *(unsigned short *)s1 = 0;\n v19 = 0;\n v2 = strlen(a1);\n v3 = (int)(v2 + 2);\n v4 = malloc(v3);\n v17 = v4;\n __strcpy_chk(v4, a1, v3);\n __strcat_chk(v4, &unk_2004, v3);\n if ((int)(v2 + 1) <= 0) {\n v8 = 0;\n ptr = 0LL;\n } else {\n v5 = (char *)v4;\n v6 = (long long)v4 + v2 + 1;\n v7 = 0;\n v8 = 0;\n ptr = 0LL;\n do {\n v9 = *v5;\n if (*v5 == 32) {\n if (!strcmp(s1, \"o\")) {\n if (v8 == v7) {\n v11 = 2 * v7;\n v12 = v7 <= 0;\n v7 = 4;\n if (!v12) v7 = v11;\n ptr = realloc(ptr, 4LL * v7);\n }\n *((uint32_t *)ptr + v8++) = 4;\n }\n if (!strcmp(s1, \"o|\")) {\n if (v8 == v7) {\n v13 = 2 * v7;\n v12 = v7 <= 0;\n v7 = 4;\n if (!v12) v7 = v13;\n ptr = realloc(ptr, 4LL * v7);\n }\n *((uint32_t *)ptr + v8++) = 2;\n }\n if (!strcmp(s1, \".|\")) {\n if (v8 == v7) {\n v14 = 2 * v7;\n v12 = v7 <= 0;\n v7 = 4;\n if (!v12) v7 = v14;\n ptr = realloc(ptr, 4LL * v7);\n }\n *((uint32_t *)ptr + v8++) = 1;\n }\n s1[0] = 0;\n } else {\n v10 = strlen(s1);\n if (v10 <= 1) {\n s1[v10] = v9;\n s1[v10 + 1] = 0;\n }\n }\n ++v5;\n } while (v5 != (char *)v6);\n }\n free(v17);\n *a2 = v8;\n return ptr;\n}", + "ida_pseudo_norm": "void *func0(const char *a1, uint32_t *a2) {\n unsigned int v2;\n unsigned int v3;\n void *v4;\n char *v5;\n long long v6;\n int v7;\n int v8;\n char v9;\n unsigned int v10;\n int v11;\n bool v12;\n int v13;\n int v14;\n void *ptr;\n void *v17;\n char s1[2];\n char v19;\n unsigned long long v20;\n v20 = __readfsqword(40u);\n *(unsigned short *)s1 = 0;\n v19 = 0;\n v2 = strlen(a1);\n v3 = (int)(v2 + 2);\n v4 = malloc(v3);\n v17 = v4;\n __strcpy_chk(v4, a1, v3);\n __strcat_chk(v4, &unk_2004, v3);\n if ((int)(v2 + 1) <= 0) {\n v8 = 0;\n ptr = 0LL;\n } else {\n v5 = (char *)v4;\n v6 = (long long)v4 + v2 + 1;\n v7 = 0;\n v8 = 0;\n ptr = 0LL;\n do {\n v9 = *v5;\n if (*v5 == 32) {\n if (!strcmp(s1, \"o\")) {\n if (v8 == v7) {\n v11 = 2 * v7;\n v12 = v7 <= 0;\n v7 = 4;\n if (!v12) v7 = v11;\n ptr = realloc(ptr, 4LL * v7);\n }\n *((uint32_t *)ptr + v8++) = 4;\n }\n if (!strcmp(s1, \"o|\")) {\n if (v8 == v7) {\n v13 = 2 * v7;\n v12 = v7 <= 0;\n v7 = 4;\n if (!v12) v7 = v13;\n ptr = realloc(ptr, 4LL * v7);\n }\n *((uint32_t *)ptr + v8++) = 2;\n }\n if (!strcmp(s1, \".|\")) {\n if (v8 == v7) {\n v14 = 2 * v7;\n v12 = v7 <= 0;\n v7 = 4;\n if (!v12) v7 = v14;\n ptr = realloc(ptr, 4LL * v7);\n }\n *((uint32_t *)ptr + v8++) = 1;\n }\n s1[0] = 0;\n } else {\n v10 = strlen(s1);\n if (v10 <= 1) {\n s1[v10] = v9;\n s1[v10 + 1] = 0;\n }\n }\n ++v5;\n } while (v5 != (char *)v6);\n }\n free(v17);\n *a2 = v8;\n return ptr;\n}" + }, + { + "index": "HumanEval-C-17", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int *func0(const char *music_string, int *count) {\n int *out = NULL;\n int size = 0;\n int capacity = 0;\n char current[3] = \"\";\n int music_string_length = strlen(music_string) + 1;\n char *temp_music_string = malloc(music_string_length + 1);\n strcpy(temp_music_string, music_string);\n strcat(temp_music_string, \" \");\n for (int i = 0; i < music_string_length; i++) {\n if (temp_music_string[i] == ' ') {\n if (strcmp(current, \"o\") == 0) {\n if (size == capacity) {\n capacity = capacity > 0 ? 2 * capacity : 4;\n out = realloc(out, capacity * sizeof(int));\n }\n out[size++] = 4;\n }\n if (strcmp(current, \"o|\") == 0) {\n if (size == capacity) {\n capacity = capacity > 0 ? 2 * capacity : 4;\n out = realloc(out, capacity * sizeof(int));\n }\n out[size++] = 2;\n }\n if (strcmp(current, \".|\") == 0) {\n if (size == capacity) {\n capacity = capacity > 0 ? 2 * capacity : 4;\n out = realloc(out, capacity * sizeof(int));\n }\n out[size++] = 1;\n }\n strcpy(current, \"\");\n } else {\n size_t len = strlen(current);\n if (len < sizeof(current) - 1) {\n current[len] = temp_music_string[i];\n current[len + 1] = '\\0';\n }\n }\n }\n free(temp_music_string);\n *count = size;\n return out;\n}", + "test": "#include \n#include \n\nint issame(const int *a, int a_size, const int *b, int b_size) {\n if (a_size != b_size) return 0;\n for (int i = 0; i < a_size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int count;\n int *result;\n\n result = func0(\"\", &count);\n assert(issame(result, count, (const int[]){}, 0));\n free(result);\n\n result = func0(\"o o o o\", &count);\n assert(issame(result, count, (const int[]){4, 4, 4, 4}, 4));\n free(result);\n\n result = func0(\".| .| .| .|\", &count);\n assert(issame(result, count, (const int[]){1, 1, 1, 1}, 4));\n free(result);\n\n result = func0(\"o| o| .| .| o o o o\", &count);\n assert(issame(result, count, (const int[]){2, 2, 1, 1, 4, 4, 4, 4}, 8));\n free(result);\n\n result = func0(\"o| .| o| .| o o| o o|\", &count);\n assert(issame(result, count, (const int[]){2, 1, 2, 1, 4, 2, 4, 2}, 8));\n free(result);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 38h\nmov [rsp+68h+var_50], rsi\nmov rax, fs:28h\nmov [rsp+68h+var_40], rax\nxor eax, eax\nxor eax, eax\nmov [rsp+68h+var_41], 0\nmov word ptr [rsp+68h+s], ax\ncall _strlen\nlea ebx, [rax+2]\nmov rbp, rax\nmovsxd rbx, ebx\nmov rdi, rbx; size\ncall _malloc\nmov rcx, rbx\nmov rdx, rbp\nmov rsi, r12\nmov rdi, rax\nmov r15, rax\nmov [rsp+68h+ptr], rax\ncall ___memcpy_chk\nmov rcx, rbx\nlea rdi, [r15+rbp]\nmov edx, 2\nsub rcx, rbp\nlea rsi, unk_2004\ncall ___memcpy_chk\nlea eax, [rbp+1]\ntest eax, eax\njle loc_16F0\nmov ebp, ebp\nmov rbx, r15\nlea r13, [rsp+68h+s]\nmov [rsp+68h+var_5C], 0\nlea r12, [r15+rbp+1]\nxor r15d, r15d\nxor ebp, ebp\njmp short loc_1565\nloc_1540:\nmov rdi, r13; s\ncall _strlen\ncmp rax, 2\njz short loc_1558\nmov [rsp+rax+68h+s], r14b\nmov [rsp+rax+68h+s+1], 0\nloc_1558:\nadd rbx, 1\ncmp r12, rbx\njz loc_160D\nloc_1565:\nmovzx r14d, byte ptr [rbx]\ncmp r14b, 20h ; ' '\njnz short loc_1540\ncmp byte ptr [r13+0], 6Fh ; 'o'\njnz short loc_1599\ncmp byte ptr [r13+1], 0\njnz short loc_1599\nmov eax, [rsp+68h+var_5C]\ncmp r15d, eax\njz loc_1648\nloc_158A:\nmovsxd rax, r15d\nadd r15d, 1\nmov dword ptr [rbp+rax*4+0], 4\nloc_1599:\ncmp byte ptr [r13+0], 6Fh ; 'o'\njnz short loc_15CA\ncmp byte ptr [r13+1], 7Ch ; '|'\njnz short loc_15CA\ncmp byte ptr [r13+2], 0\njnz short loc_15CA\nmov eax, [rsp+68h+var_5C]\ncmp r15d, eax\njz loc_1698\nloc_15BB:\nmovsxd rax, r15d\nadd r15d, 1\nmov dword ptr [rbp+rax*4+0], 2\nloc_15CA:\ncmp byte ptr [r13+0], 2Eh ; '.'\njnz short loc_15FB\ncmp byte ptr [r13+1], 7Ch ; '|'\njnz short loc_15FB\ncmp byte ptr [r13+2], 0\njnz short loc_15FB\nmov eax, [rsp+68h+var_5C]\ncmp r15d, eax\njz loc_1670\nloc_15EC:\nmovsxd rax, r15d\nadd r15d, 1\nmov dword ptr [rbp+rax*4+0], 1\nloc_15FB:\nadd rbx, 1\nmov [rsp+68h+s], 0\ncmp r12, rbx\njnz loc_1565\nloc_160D:\nmov rdi, [rsp+68h+ptr]; ptr\ncall _free\nmov rax, [rsp+68h+var_50]\nmov [rax], r15d\nmov rax, [rsp+68h+var_40]\nsub rax, fs:28h\njnz loc_16FA\nadd rsp, 38h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1648:\ntest r15d, r15d\njle short loc_16C0\nlea eax, [r15+r15]\nmov [rsp+68h+var_5C], eax\nmovsxd rsi, eax\nshl rsi, 2; size\nloc_165C:\nmov rdi, rbp; ptr\ncall _realloc\nmov rbp, rax\njmp loc_158A\nloc_1670:\ntest r15d, r15d\njle short loc_16E0\nlea eax, [r15+r15]\nmov [rsp+68h+var_5C], eax\nmovsxd rsi, eax\nshl rsi, 2; size\nloc_1684:\nmov rdi, rbp; ptr\ncall _realloc\nmov rbp, rax\njmp loc_15EC\nloc_1698:\ntest r15d, r15d\njle short loc_16D0\nlea eax, [r15+r15]\nmov [rsp+68h+var_5C], eax\nmovsxd rsi, eax\nshl rsi, 2; size\nloc_16AC:\nmov rdi, rbp; ptr\ncall _realloc\nmov rbp, rax\njmp loc_15BB\nloc_16C0:\nmov [rsp+68h+var_5C], 4\nmov esi, 10h\njmp short loc_165C\nloc_16D0:\nmov [rsp+68h+var_5C], 4\nmov esi, 10h\njmp short loc_16AC\nloc_16E0:\nmov [rsp+68h+var_5C], 4\nmov esi, 10h\njmp short loc_1684\nloc_16F0:\nxor r15d, r15d\nxor ebp, ebp\njmp loc_160D\nloc_16FA:\ncall ___stack_chk_fail", + "ida_pseudo": "void *__fastcall func0(const char *a1, int *a2)\n{\n size_t v2; // rbp\n size_t v3; // rbx\n char *v4; // r15\n char *v5; // rbx\n __int64 v6; // r12\n int v7; // r15d\n void *v8; // rbp\n size_t v9; // rax\n char v10; // r14\n __int64 v11; // rax\n __int64 v12; // rax\n __int64 v13; // rax\n size_t v15; // rsi\n size_t v16; // rsi\n size_t v17; // rsi\n int v18; // [rsp+Ch] [rbp-5Ch]\n void *ptr; // [rsp+10h] [rbp-58h]\n char s[2]; // [rsp+25h] [rbp-43h] BYREF\n char v22; // [rsp+27h] [rbp-41h]\n unsigned __int64 v23; // [rsp+28h] [rbp-40h]\n\n v23 = __readfsqword(0x28u);\n v22 = 0;\n *(_WORD *)s = 0;\n v2 = strlen(a1);\n v3 = (int)v2 + 2;\n v4 = (char *)malloc(v3);\n ptr = v4;\n __memcpy_chk(v4, a1, v2, v3);\n __memcpy_chk(&v4[v2], &unk_2004, 2LL, v3 - v2);\n if ( (int)v2 + 1 <= 0 )\n {\n v7 = 0;\n v8 = 0LL;\n }\n else\n {\n v5 = v4;\n v18 = 0;\n v6 = (__int64)&v4[(unsigned int)v2 + 1];\n v7 = 0;\n v8 = 0LL;\n do\n {\n while ( 1 )\n {\n v10 = *v5;\n if ( *v5 != 32 )\n break;\n if ( s[0] == 111 && !s[1] )\n {\n if ( v7 == v18 )\n {\n if ( v7 <= 0 )\n {\n v18 = 4;\n v15 = 16LL;\n }\n else\n {\n v18 = 2 * v7;\n v15 = 8LL * v7;\n }\n v8 = realloc(v8, v15);\n }\n v11 = v7++;\n *((_DWORD *)v8 + v11) = 4;\n }\n if ( s[0] == 111 && s[1] == 124 && !v22 )\n {\n if ( v7 == v18 )\n {\n if ( v7 <= 0 )\n {\n v18 = 4;\n v17 = 16LL;\n }\n else\n {\n v18 = 2 * v7;\n v17 = 8LL * v7;\n }\n v8 = realloc(v8, v17);\n }\n v12 = v7++;\n *((_DWORD *)v8 + v12) = 2;\n }\n if ( s[0] == 46 && s[1] == 124 && !v22 )\n {\n if ( v7 == v18 )\n {\n if ( v7 <= 0 )\n {\n v18 = 4;\n v16 = 16LL;\n }\n else\n {\n v18 = 2 * v7;\n v16 = 8LL * v7;\n }\n v8 = realloc(v8, v16);\n }\n v13 = v7++;\n *((_DWORD *)v8 + v13) = 1;\n }\n ++v5;\n s[0] = 0;\n if ( (char *)v6 == v5 )\n goto LABEL_22;\n }\n v9 = strlen(s);\n if ( v9 != 2 )\n {\n s[v9] = v10;\n s[v9 + 1] = 0;\n }\n ++v5;\n }\n while ( (char *)v6 != v5 );\n }\nLABEL_22:\n free(ptr);\n *a2 = v7;\n return v8;\n}", + "ida_strip_asm": "sub_1490:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 38h\nmov [rsp+68h+var_50], rsi\nmov rax, fs:28h\nmov [rsp+68h+var_40], rax\nxor eax, eax\nxor eax, eax\nmov [rsp+68h+var_41], 0\nmov word ptr [rsp+68h+s], ax\ncall _strlen\nlea ebx, [rax+2]\nmov rbp, rax\nmovsxd rbx, ebx\nmov rdi, rbx; size\ncall _malloc\nmov rcx, rbx\nmov rdx, rbp\nmov rsi, r12\nmov rdi, rax\nmov r15, rax\nmov [rsp+68h+ptr], rax\ncall ___memcpy_chk\nmov rcx, rbx\nlea rdi, [r15+rbp]\nmov edx, 2\nsub rcx, rbp\nlea rsi, unk_2004\ncall ___memcpy_chk\nlea eax, [rbp+1]\ntest eax, eax\njle loc_16F0\nmov ebp, ebp\nmov rbx, r15\nlea r13, [rsp+68h+s]\nmov [rsp+68h+var_5C], 0\nlea r12, [r15+rbp+1]\nxor r15d, r15d\nxor ebp, ebp\njmp short loc_1565\nloc_1540:\nmov rdi, r13; s\ncall _strlen\ncmp rax, 2\njz short loc_1558\nmov [rsp+rax+68h+s], r14b\nmov [rsp+rax+68h+s+1], 0\nloc_1558:\nadd rbx, 1\ncmp r12, rbx\njz loc_160D\nloc_1565:\nmovzx r14d, byte ptr [rbx]\ncmp r14b, 20h ; ' '\njnz short loc_1540\ncmp byte ptr [r13+0], 6Fh ; 'o'\njnz short loc_1599\ncmp byte ptr [r13+1], 0\njnz short loc_1599\nmov eax, [rsp+68h+var_5C]\ncmp r15d, eax\njz loc_1648\nloc_158A:\nmovsxd rax, r15d\nadd r15d, 1\nmov dword ptr [rbp+rax*4+0], 4\nloc_1599:\ncmp byte ptr [r13+0], 6Fh ; 'o'\njnz short loc_15CA\ncmp byte ptr [r13+1], 7Ch ; '|'\njnz short loc_15CA\ncmp byte ptr [r13+2], 0\njnz short loc_15CA\nmov eax, [rsp+68h+var_5C]\ncmp r15d, eax\njz loc_1698\nloc_15BB:\nmovsxd rax, r15d\nadd r15d, 1\nmov dword ptr [rbp+rax*4+0], 2\nloc_15CA:\ncmp byte ptr [r13+0], 2Eh ; '.'\njnz short loc_15FB\ncmp byte ptr [r13+1], 7Ch ; '|'\njnz short loc_15FB\ncmp byte ptr [r13+2], 0\njnz short loc_15FB\nmov eax, [rsp+68h+var_5C]\ncmp r15d, eax\njz loc_1670\nloc_15EC:\nmovsxd rax, r15d\nadd r15d, 1\nmov dword ptr [rbp+rax*4+0], 1\nloc_15FB:\nadd rbx, 1\nmov [rsp+68h+s], 0\ncmp r12, rbx\njnz loc_1565\nloc_160D:\nmov rdi, [rsp+68h+ptr]; ptr\ncall _free\nmov rax, [rsp+68h+var_50]\nmov [rax], r15d\nmov rax, [rsp+68h+var_40]\nsub rax, fs:28h\njnz loc_16FA\nadd rsp, 38h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1648:\ntest r15d, r15d\njle short loc_16C0\nlea eax, [r15+r15]\nmov [rsp+68h+var_5C], eax\nmovsxd rsi, eax\nshl rsi, 2; size\nloc_165C:\nmov rdi, rbp; ptr\ncall _realloc\nmov rbp, rax\njmp loc_158A\nloc_1670:\ntest r15d, r15d\njle short loc_16E0\nlea eax, [r15+r15]\nmov [rsp+68h+var_5C], eax\nmovsxd rsi, eax\nshl rsi, 2; size\nloc_1684:\nmov rdi, rbp; ptr\ncall _realloc\nmov rbp, rax\njmp loc_15EC\nloc_1698:\ntest r15d, r15d\njle short loc_16D0\nlea eax, [r15+r15]\nmov [rsp+68h+var_5C], eax\nmovsxd rsi, eax\nshl rsi, 2; size\nloc_16AC:\nmov rdi, rbp; ptr\ncall _realloc\nmov rbp, rax\njmp loc_15BB\nloc_16C0:\nmov [rsp+68h+var_5C], 4\nmov esi, 10h\njmp short loc_165C\nloc_16D0:\nmov [rsp+68h+var_5C], 4\nmov esi, 10h\njmp short loc_16AC\nloc_16E0:\nmov [rsp+68h+var_5C], 4\nmov esi, 10h\njmp short loc_1684\nloc_16F0:\nxor r15d, r15d\nxor ebp, ebp\njmp loc_160D\nloc_16FA:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "void *__fastcall sub_1490(const char *a1, int *a2)\n{\n size_t v2; // rbp\n size_t v3; // rbx\n char *v4; // r15\n char *v5; // rbx\n __int64 v6; // r12\n int v7; // r15d\n void *v8; // rbp\n size_t v9; // rax\n char v10; // r14\n __int64 v11; // rax\n __int64 v12; // rax\n __int64 v13; // rax\n size_t v15; // rsi\n size_t v16; // rsi\n size_t v17; // rsi\n int v18; // [rsp+Ch] [rbp-5Ch]\n void *ptr; // [rsp+10h] [rbp-58h]\n char s[2]; // [rsp+25h] [rbp-43h] BYREF\n char v22; // [rsp+27h] [rbp-41h]\n unsigned __int64 v23; // [rsp+28h] [rbp-40h]\n\n v23 = __readfsqword(0x28u);\n v22 = 0;\n *(_WORD *)s = 0;\n v2 = strlen(a1);\n v3 = (int)v2 + 2;\n v4 = (char *)malloc(v3);\n ptr = v4;\n __memcpy_chk(v4, a1, v2, v3);\n __memcpy_chk(&v4[v2], &unk_2004, 2LL, v3 - v2);\n if ( (int)v2 + 1 <= 0 )\n {\n v7 = 0;\n v8 = 0LL;\n }\n else\n {\n v5 = v4;\n v18 = 0;\n v6 = (__int64)&v4[(unsigned int)v2 + 1];\n v7 = 0;\n v8 = 0LL;\n do\n {\n while ( 1 )\n {\n v10 = *v5;\n if ( *v5 != 32 )\n break;\n if ( s[0] == 111 && !s[1] )\n {\n if ( v7 == v18 )\n {\n if ( v7 <= 0 )\n {\n v18 = 4;\n v15 = 16LL;\n }\n else\n {\n v18 = 2 * v7;\n v15 = 8LL * v7;\n }\n v8 = realloc(v8, v15);\n }\n v11 = v7++;\n *((_DWORD *)v8 + v11) = 4;\n }\n if ( s[0] == 111 && s[1] == 124 && !v22 )\n {\n if ( v7 == v18 )\n {\n if ( v7 <= 0 )\n {\n v18 = 4;\n v17 = 16LL;\n }\n else\n {\n v18 = 2 * v7;\n v17 = 8LL * v7;\n }\n v8 = realloc(v8, v17);\n }\n v12 = v7++;\n *((_DWORD *)v8 + v12) = 2;\n }\n if ( s[0] == 46 && s[1] == 124 && !v22 )\n {\n if ( v7 == v18 )\n {\n if ( v7 <= 0 )\n {\n v18 = 4;\n v16 = 16LL;\n }\n else\n {\n v18 = 2 * v7;\n v16 = 8LL * v7;\n }\n v8 = realloc(v8, v16);\n }\n v13 = v7++;\n *((_DWORD *)v8 + v13) = 1;\n }\n ++v5;\n s[0] = 0;\n if ( (char *)v6 == v5 )\n goto LABEL_22;\n }\n v9 = strlen(s);\n if ( v9 != 2 )\n {\n s[v9] = v10;\n s[v9 + 1] = 0;\n }\n ++v5;\n }\n while ( (char *)v6 != v5 );\n }\nLABEL_22:\n free(ptr);\n *a2 = v7;\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1490(const char *a1, int *a2) {\n unsigned int v2;\n unsigned int v3;\n char *v4;\n char *v5;\n long long v6;\n int v7;\n void *v8;\n unsigned int v9;\n char v10;\n long long v11;\n long long v12;\n long long v13;\n unsigned int v15;\n unsigned int v16;\n unsigned int v17;\n int v18;\n void *ptr;\n char s[2];\n char v22;\n unsigned long long v23;\n v23 = __readfsqword(40u);\n v22 = 0;\n *(unsigned short *)s = 0;\n v2 = strlen(a1);\n v3 = (int)v2 + 2;\n v4 = (char *)malloc(v3);\n ptr = v4;\n __memcpy_chk(v4, a1, v2, v3);\n __memcpy_chk(&v4[v2], &unk_2004, 2LL, v3 - v2);\n if ((int)v2 + 1 <= 0) {\n v7 = 0;\n v8 = 0LL;\n } else {\n v5 = v4;\n v18 = 0;\n v6 = (long long)&v4[(unsigned int)v2 + 1];\n v7 = 0;\n v8 = 0LL;\n do {\n while (1) {\n v10 = *v5;\n if (*v5 != 32) break;\n if (s[0] == 111 && !s[1]) {\n if (v7 == v18) {\n if (v7 <= 0) {\n v18 = 4;\n v15 = 16LL;\n } else {\n v18 = 2 * v7;\n v15 = 8LL * v7;\n }\n v8 = realloc(v8, v15);\n }\n v11 = v7++;\n *((uint32_t *)v8 + v11) = 4;\n }\n if (s[0] == 111 && s[1] == 124 && !v22) {\n if (v7 == v18) {\n if (v7 <= 0) {\n v18 = 4;\n v17 = 16LL;\n } else {\n v18 = 2 * v7;\n v17 = 8LL * v7;\n }\n v8 = realloc(v8, v17);\n }\n v12 = v7++;\n *((uint32_t *)v8 + v12) = 2;\n }\n if (s[0] == 46 && s[1] == 124 && !v22) {\n if (v7 == v18) {\n if (v7 <= 0) {\n v18 = 4;\n v16 = 16LL;\n } else {\n v18 = 2 * v7;\n v16 = 8LL * v7;\n }\n v8 = realloc(v8, v16);\n }\n v13 = v7++;\n *((uint32_t *)v8 + v13) = 1;\n }\n ++v5;\n s[0] = 0;\n if ((char *)v6 == v5) goto LABEL_22;\n }\n v9 = strlen(s);\n if (v9 != 2) {\n s[v9] = v10;\n s[v9 + 1] = 0;\n }\n ++v5;\n } while ((char *)v6 != v5);\n }\nLABEL_22:\n free(ptr);\n *a2 = v7;\n return v8;\n}", + "ida_pseudo_norm": "void *func0(const char *a1, int *a2) {\n unsigned int v2;\n unsigned int v3;\n char *v4;\n char *v5;\n long long v6;\n int v7;\n void *v8;\n unsigned int v9;\n char v10;\n long long v11;\n long long v12;\n long long v13;\n unsigned int v15;\n unsigned int v16;\n unsigned int v17;\n int v18;\n void *ptr;\n char s[2];\n char v22;\n unsigned long long v23;\n v23 = __readfsqword(40u);\n v22 = 0;\n *(unsigned short *)s = 0;\n v2 = strlen(a1);\n v3 = (int)v2 + 2;\n v4 = (char *)malloc(v3);\n ptr = v4;\n __memcpy_chk(v4, a1, v2, v3);\n __memcpy_chk(&v4[v2], &unk_2004, 2LL, v3 - v2);\n if ((int)v2 + 1 <= 0) {\n v7 = 0;\n v8 = 0LL;\n } else {\n v5 = v4;\n v18 = 0;\n v6 = (long long)&v4[(unsigned int)v2 + 1];\n v7 = 0;\n v8 = 0LL;\n do {\n while (1) {\n v10 = *v5;\n if (*v5 != 32) break;\n if (s[0] == 111 && !s[1]) {\n if (v7 == v18) {\n if (v7 <= 0) {\n v18 = 4;\n v15 = 16LL;\n } else {\n v18 = 2 * v7;\n v15 = 8LL * v7;\n }\n v8 = realloc(v8, v15);\n }\n v11 = v7++;\n *((uint32_t *)v8 + v11) = 4;\n }\n if (s[0] == 111 && s[1] == 124 && !v22) {\n if (v7 == v18) {\n if (v7 <= 0) {\n v18 = 4;\n v17 = 16LL;\n } else {\n v18 = 2 * v7;\n v17 = 8LL * v7;\n }\n v8 = realloc(v8, v17);\n }\n v12 = v7++;\n *((uint32_t *)v8 + v12) = 2;\n }\n if (s[0] == 46 && s[1] == 124 && !v22) {\n if (v7 == v18) {\n if (v7 <= 0) {\n v18 = 4;\n v16 = 16LL;\n } else {\n v18 = 2 * v7;\n v16 = 8LL * v7;\n }\n v8 = realloc(v8, v16);\n }\n v13 = v7++;\n *((uint32_t *)v8 + v13) = 1;\n }\n ++v5;\n s[0] = 0;\n if ((char *)v6 == v5) goto LABEL_22;\n }\n v9 = strlen(s);\n if (v9 != 2) {\n s[v9] = v10;\n s[v9 + 1] = 0;\n }\n ++v5;\n } while ((char *)v6 != v5);\n }\nLABEL_22:\n free(ptr);\n *a2 = v7;\n return v8;\n}" + }, + { + "index": "HumanEval-C-17", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int *func0(const char *music_string, int *count) {\n int *out = NULL;\n int size = 0;\n int capacity = 0;\n char current[3] = \"\";\n int music_string_length = strlen(music_string) + 1;\n char *temp_music_string = malloc(music_string_length + 1);\n strcpy(temp_music_string, music_string);\n strcat(temp_music_string, \" \");\n for (int i = 0; i < music_string_length; i++) {\n if (temp_music_string[i] == ' ') {\n if (strcmp(current, \"o\") == 0) {\n if (size == capacity) {\n capacity = capacity > 0 ? 2 * capacity : 4;\n out = realloc(out, capacity * sizeof(int));\n }\n out[size++] = 4;\n }\n if (strcmp(current, \"o|\") == 0) {\n if (size == capacity) {\n capacity = capacity > 0 ? 2 * capacity : 4;\n out = realloc(out, capacity * sizeof(int));\n }\n out[size++] = 2;\n }\n if (strcmp(current, \".|\") == 0) {\n if (size == capacity) {\n capacity = capacity > 0 ? 2 * capacity : 4;\n out = realloc(out, capacity * sizeof(int));\n }\n out[size++] = 1;\n }\n strcpy(current, \"\");\n } else {\n size_t len = strlen(current);\n if (len < sizeof(current) - 1) {\n current[len] = temp_music_string[i];\n current[len + 1] = '\\0';\n }\n }\n }\n free(temp_music_string);\n *count = size;\n return out;\n}", + "test": "#include \n#include \n\nint issame(const int *a, int a_size, const int *b, int b_size) {\n if (a_size != b_size) return 0;\n for (int i = 0; i < a_size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int count;\n int *result;\n\n result = func0(\"\", &count);\n assert(issame(result, count, (const int[]){}, 0));\n free(result);\n\n result = func0(\"o o o o\", &count);\n assert(issame(result, count, (const int[]){4, 4, 4, 4}, 4));\n free(result);\n\n result = func0(\".| .| .| .|\", &count);\n assert(issame(result, count, (const int[]){1, 1, 1, 1}, 4));\n free(result);\n\n result = func0(\"o| o| .| .| o o o o\", &count);\n assert(issame(result, count, (const int[]){2, 2, 1, 1, 4, 4, 4, 4}, 8));\n free(result);\n\n result = func0(\"o| .| o| .| o o| o o|\", &count);\n assert(issame(result, count, (const int[]){2, 1, 2, 1, 4, 2, 4, 2}, 8));\n free(result);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 38h\nmov [rsp+68h+var_50], rsi\nmov rax, fs:28h\nmov [rsp+68h+var_40], rax\nxor eax, eax\nxor eax, eax\nmov [rsp+68h+var_41], 0\nmov word ptr [rsp+68h+s], ax\ncall _strlen\nlea ebx, [rax+2]\nmov rbp, rax\nmovsxd rbx, ebx\nmov rdi, rbx; size\ncall _malloc\nmov rcx, rbx\nmov rdx, rbp\nmov rsi, r12\nmov rdi, rax\nmov r15, rax\nmov [rsp+68h+ptr], rax\ncall ___memcpy_chk\nmov rcx, rbx\nlea rdi, [r15+rbp]\nmov edx, 2\nsub rcx, rbp\nlea rsi, unk_2004\ncall ___memcpy_chk\nlea eax, [rbp+1]\ntest eax, eax\njle loc_16F0\nmov ebp, ebp\nmov rbx, r15\nlea r13, [rsp+68h+s]\nmov [rsp+68h+var_5C], 0\nlea r12, [r15+rbp+1]\nxor r15d, r15d\nxor ebp, ebp\njmp short loc_1565\nloc_1540:\nmov rdi, r13; s\ncall _strlen\ncmp rax, 2\njz short loc_1558\nmov [rsp+rax+68h+s], r14b\nmov [rsp+rax+68h+s+1], 0\nloc_1558:\nadd rbx, 1\ncmp rbx, r12\njz loc_160D\nloc_1565:\nmovzx r14d, byte ptr [rbx]\ncmp r14b, 20h ; ' '\njnz short loc_1540\ncmp byte ptr [r13+0], 6Fh ; 'o'\njnz short loc_1599\ncmp byte ptr [r13+1], 0\njnz short loc_1599\nmov eax, [rsp+68h+var_5C]\ncmp r15d, eax\njz loc_1648\nloc_158A:\nmovsxd rax, r15d\nadd r15d, 1\nmov dword ptr [rbp+rax*4+0], 4\nloc_1599:\ncmp byte ptr [r13+0], 6Fh ; 'o'\njnz short loc_15CA\ncmp byte ptr [r13+1], 7Ch ; '|'\njnz short loc_15CA\ncmp byte ptr [r13+2], 0\njnz short loc_15CA\nmov eax, [rsp+68h+var_5C]\ncmp r15d, eax\njz loc_1698\nloc_15BB:\nmovsxd rax, r15d\nadd r15d, 1\nmov dword ptr [rbp+rax*4+0], 2\nloc_15CA:\ncmp byte ptr [r13+0], 2Eh ; '.'\njnz short loc_15FB\ncmp byte ptr [r13+1], 7Ch ; '|'\njnz short loc_15FB\ncmp byte ptr [r13+2], 0\njnz short loc_15FB\nmov eax, [rsp+68h+var_5C]\ncmp r15d, eax\njz loc_1670\nloc_15EC:\nmovsxd rax, r15d\nadd r15d, 1\nmov dword ptr [rbp+rax*4+0], 1\nloc_15FB:\nadd rbx, 1\nmov [rsp+68h+s], 0\ncmp rbx, r12\njnz loc_1565\nloc_160D:\nmov rdi, [rsp+68h+ptr]; ptr\ncall _free\nmov rax, [rsp+68h+var_50]\nmov [rax], r15d\nmov rax, [rsp+68h+var_40]\nsub rax, fs:28h\njnz loc_16FA\nadd rsp, 38h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1648:\ntest r15d, r15d\njle short loc_16C0\nlea eax, [r15+r15]\nmov [rsp+68h+var_5C], eax\nmovsxd rsi, eax\nshl rsi, 2; size\nloc_165C:\nmov rdi, rbp; ptr\ncall _realloc\nmov rbp, rax\njmp loc_158A\nloc_1670:\ntest r15d, r15d\njle short loc_16E0\nlea eax, [r15+r15]\nmov [rsp+68h+var_5C], eax\nmovsxd rsi, eax\nshl rsi, 2; size\nloc_1684:\nmov rdi, rbp; ptr\ncall _realloc\nmov rbp, rax\njmp loc_15EC\nloc_1698:\ntest r15d, r15d\njle short loc_16D0\nlea eax, [r15+r15]\nmov [rsp+68h+var_5C], eax\nmovsxd rsi, eax\nshl rsi, 2; size\nloc_16AC:\nmov rdi, rbp; ptr\ncall _realloc\nmov rbp, rax\njmp loc_15BB\nloc_16C0:\nmov [rsp+68h+var_5C], 4\nmov esi, 10h\njmp short loc_165C\nloc_16D0:\nmov [rsp+68h+var_5C], 4\nmov esi, 10h\njmp short loc_16AC\nloc_16E0:\nmov [rsp+68h+var_5C], 4\nmov esi, 10h\njmp short loc_1684\nloc_16F0:\nxor r15d, r15d\nxor ebp, ebp\njmp loc_160D\nloc_16FA:\ncall ___stack_chk_fail", + "ida_pseudo": "void *__fastcall func0(const char *a1, int *a2)\n{\n size_t v2; // rbp\n size_t v3; // rbx\n char *v4; // r15\n char *v5; // rbx\n __int64 v6; // r12\n int v7; // r15d\n void *v8; // rbp\n size_t v9; // rax\n char v10; // r14\n __int64 v11; // rax\n __int64 v12; // rax\n __int64 v13; // rax\n size_t v15; // rsi\n size_t v16; // rsi\n size_t v17; // rsi\n int v18; // [rsp+Ch] [rbp-5Ch]\n void *ptr; // [rsp+10h] [rbp-58h]\n char s[2]; // [rsp+25h] [rbp-43h] BYREF\n char v22; // [rsp+27h] [rbp-41h]\n unsigned __int64 v23; // [rsp+28h] [rbp-40h]\n\n v23 = __readfsqword(0x28u);\n v22 = 0;\n *(_WORD *)s = 0;\n v2 = strlen(a1);\n v3 = (int)v2 + 2;\n v4 = (char *)malloc(v3);\n ptr = v4;\n __memcpy_chk(v4, a1, v2, v3);\n __memcpy_chk(&v4[v2], &unk_2004, 2LL, v3 - v2);\n if ( (int)v2 + 1 <= 0 )\n {\n v7 = 0;\n v8 = 0LL;\n }\n else\n {\n v5 = v4;\n v18 = 0;\n v6 = (__int64)&v4[(unsigned int)v2 + 1];\n v7 = 0;\n v8 = 0LL;\n do\n {\n while ( 1 )\n {\n v10 = *v5;\n if ( *v5 != 32 )\n break;\n if ( s[0] == 111 && !s[1] )\n {\n if ( v7 == v18 )\n {\n if ( v7 <= 0 )\n {\n v18 = 4;\n v15 = 16LL;\n }\n else\n {\n v18 = 2 * v7;\n v15 = 8LL * v7;\n }\n v8 = realloc(v8, v15);\n }\n v11 = v7++;\n *((_DWORD *)v8 + v11) = 4;\n }\n if ( s[0] == 111 && s[1] == 124 && !v22 )\n {\n if ( v7 == v18 )\n {\n if ( v7 <= 0 )\n {\n v18 = 4;\n v17 = 16LL;\n }\n else\n {\n v18 = 2 * v7;\n v17 = 8LL * v7;\n }\n v8 = realloc(v8, v17);\n }\n v12 = v7++;\n *((_DWORD *)v8 + v12) = 2;\n }\n if ( s[0] == 46 && s[1] == 124 && !v22 )\n {\n if ( v7 == v18 )\n {\n if ( v7 <= 0 )\n {\n v18 = 4;\n v16 = 16LL;\n }\n else\n {\n v18 = 2 * v7;\n v16 = 8LL * v7;\n }\n v8 = realloc(v8, v16);\n }\n v13 = v7++;\n *((_DWORD *)v8 + v13) = 1;\n }\n ++v5;\n s[0] = 0;\n if ( v5 == (char *)v6 )\n goto LABEL_22;\n }\n v9 = strlen(s);\n if ( v9 != 2 )\n {\n s[v9] = v10;\n s[v9 + 1] = 0;\n }\n ++v5;\n }\n while ( v5 != (char *)v6 );\n }\nLABEL_22:\n free(ptr);\n *a2 = v7;\n return v8;\n}", + "ida_strip_asm": "sub_1490:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 38h\nmov [rsp+68h+var_50], rsi\nmov rax, fs:28h\nmov [rsp+68h+var_40], rax\nxor eax, eax\nxor eax, eax\nmov [rsp+68h+var_41], 0\nmov word ptr [rsp+68h+s], ax\ncall _strlen\nlea ebx, [rax+2]\nmov rbp, rax\nmovsxd rbx, ebx\nmov rdi, rbx; size\ncall _malloc\nmov rcx, rbx\nmov rdx, rbp\nmov rsi, r12\nmov rdi, rax\nmov r15, rax\nmov [rsp+68h+ptr], rax\ncall ___memcpy_chk\nmov rcx, rbx\nlea rdi, [r15+rbp]\nmov edx, 2\nsub rcx, rbp\nlea rsi, unk_2004\ncall ___memcpy_chk\nlea eax, [rbp+1]\ntest eax, eax\njle loc_16F0\nmov ebp, ebp\nmov rbx, r15\nlea r13, [rsp+68h+s]\nmov [rsp+68h+var_5C], 0\nlea r12, [r15+rbp+1]\nxor r15d, r15d\nxor ebp, ebp\njmp short loc_1565\nloc_1540:\nmov rdi, r13; s\ncall _strlen\ncmp rax, 2\njz short loc_1558\nmov [rsp+rax+68h+s], r14b\nmov [rsp+rax+68h+s+1], 0\nloc_1558:\nadd rbx, 1\ncmp rbx, r12\njz loc_160D\nloc_1565:\nmovzx r14d, byte ptr [rbx]\ncmp r14b, 20h ; ' '\njnz short loc_1540\ncmp byte ptr [r13+0], 6Fh ; 'o'\njnz short loc_1599\ncmp byte ptr [r13+1], 0\njnz short loc_1599\nmov eax, [rsp+68h+var_5C]\ncmp r15d, eax\njz loc_1648\nloc_158A:\nmovsxd rax, r15d\nadd r15d, 1\nmov dword ptr [rbp+rax*4+0], 4\nloc_1599:\ncmp byte ptr [r13+0], 6Fh ; 'o'\njnz short loc_15CA\ncmp byte ptr [r13+1], 7Ch ; '|'\njnz short loc_15CA\ncmp byte ptr [r13+2], 0\njnz short loc_15CA\nmov eax, [rsp+68h+var_5C]\ncmp r15d, eax\njz loc_1698\nloc_15BB:\nmovsxd rax, r15d\nadd r15d, 1\nmov dword ptr [rbp+rax*4+0], 2\nloc_15CA:\ncmp byte ptr [r13+0], 2Eh ; '.'\njnz short loc_15FB\ncmp byte ptr [r13+1], 7Ch ; '|'\njnz short loc_15FB\ncmp byte ptr [r13+2], 0\njnz short loc_15FB\nmov eax, [rsp+68h+var_5C]\ncmp r15d, eax\njz loc_1670\nloc_15EC:\nmovsxd rax, r15d\nadd r15d, 1\nmov dword ptr [rbp+rax*4+0], 1\nloc_15FB:\nadd rbx, 1\nmov [rsp+68h+s], 0\ncmp rbx, r12\njnz loc_1565\nloc_160D:\nmov rdi, [rsp+68h+ptr]; ptr\ncall _free\nmov rax, [rsp+68h+var_50]\nmov [rax], r15d\nmov rax, [rsp+68h+var_40]\nsub rax, fs:28h\njnz loc_16FA\nadd rsp, 38h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1648:\ntest r15d, r15d\njle short loc_16C0\nlea eax, [r15+r15]\nmov [rsp+68h+var_5C], eax\nmovsxd rsi, eax\nshl rsi, 2; size\nloc_165C:\nmov rdi, rbp; ptr\ncall _realloc\nmov rbp, rax\njmp loc_158A\nloc_1670:\ntest r15d, r15d\njle short loc_16E0\nlea eax, [r15+r15]\nmov [rsp+68h+var_5C], eax\nmovsxd rsi, eax\nshl rsi, 2; size\nloc_1684:\nmov rdi, rbp; ptr\ncall _realloc\nmov rbp, rax\njmp loc_15EC\nloc_1698:\ntest r15d, r15d\njle short loc_16D0\nlea eax, [r15+r15]\nmov [rsp+68h+var_5C], eax\nmovsxd rsi, eax\nshl rsi, 2; size\nloc_16AC:\nmov rdi, rbp; ptr\ncall _realloc\nmov rbp, rax\njmp loc_15BB\nloc_16C0:\nmov [rsp+68h+var_5C], 4\nmov esi, 10h\njmp short loc_165C\nloc_16D0:\nmov [rsp+68h+var_5C], 4\nmov esi, 10h\njmp short loc_16AC\nloc_16E0:\nmov [rsp+68h+var_5C], 4\nmov esi, 10h\njmp short loc_1684\nloc_16F0:\nxor r15d, r15d\nxor ebp, ebp\njmp loc_160D\nloc_16FA:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "void *__fastcall sub_1490(const char *a1, int *a2)\n{\n size_t v2; // rbp\n size_t v3; // rbx\n char *v4; // r15\n char *v5; // rbx\n __int64 v6; // r12\n int v7; // r15d\n void *v8; // rbp\n size_t v9; // rax\n char v10; // r14\n __int64 v11; // rax\n __int64 v12; // rax\n __int64 v13; // rax\n size_t v15; // rsi\n size_t v16; // rsi\n size_t v17; // rsi\n int v18; // [rsp+Ch] [rbp-5Ch]\n void *ptr; // [rsp+10h] [rbp-58h]\n char s[2]; // [rsp+25h] [rbp-43h] BYREF\n char v22; // [rsp+27h] [rbp-41h]\n unsigned __int64 v23; // [rsp+28h] [rbp-40h]\n\n v23 = __readfsqword(0x28u);\n v22 = 0;\n *(_WORD *)s = 0;\n v2 = strlen(a1);\n v3 = (int)v2 + 2;\n v4 = (char *)malloc(v3);\n ptr = v4;\n __memcpy_chk(v4, a1, v2, v3);\n __memcpy_chk(&v4[v2], &unk_2004, 2LL, v3 - v2);\n if ( (int)v2 + 1 <= 0 )\n {\n v7 = 0;\n v8 = 0LL;\n }\n else\n {\n v5 = v4;\n v18 = 0;\n v6 = (__int64)&v4[(unsigned int)v2 + 1];\n v7 = 0;\n v8 = 0LL;\n do\n {\n while ( 1 )\n {\n v10 = *v5;\n if ( *v5 != 32 )\n break;\n if ( s[0] == 111 && !s[1] )\n {\n if ( v7 == v18 )\n {\n if ( v7 <= 0 )\n {\n v18 = 4;\n v15 = 16LL;\n }\n else\n {\n v18 = 2 * v7;\n v15 = 8LL * v7;\n }\n v8 = realloc(v8, v15);\n }\n v11 = v7++;\n *((_DWORD *)v8 + v11) = 4;\n }\n if ( s[0] == 111 && s[1] == 124 && !v22 )\n {\n if ( v7 == v18 )\n {\n if ( v7 <= 0 )\n {\n v18 = 4;\n v17 = 16LL;\n }\n else\n {\n v18 = 2 * v7;\n v17 = 8LL * v7;\n }\n v8 = realloc(v8, v17);\n }\n v12 = v7++;\n *((_DWORD *)v8 + v12) = 2;\n }\n if ( s[0] == 46 && s[1] == 124 && !v22 )\n {\n if ( v7 == v18 )\n {\n if ( v7 <= 0 )\n {\n v18 = 4;\n v16 = 16LL;\n }\n else\n {\n v18 = 2 * v7;\n v16 = 8LL * v7;\n }\n v8 = realloc(v8, v16);\n }\n v13 = v7++;\n *((_DWORD *)v8 + v13) = 1;\n }\n ++v5;\n s[0] = 0;\n if ( v5 == (char *)v6 )\n goto LABEL_22;\n }\n v9 = strlen(s);\n if ( v9 != 2 )\n {\n s[v9] = v10;\n s[v9 + 1] = 0;\n }\n ++v5;\n }\n while ( v5 != (char *)v6 );\n }\nLABEL_22:\n free(ptr);\n *a2 = v7;\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1490(const char *a1, int *a2) {\n unsigned int v2;\n unsigned int v3;\n char *v4;\n char *v5;\n long long v6;\n int v7;\n void *v8;\n unsigned int v9;\n char v10;\n long long v11;\n long long v12;\n long long v13;\n unsigned int v15;\n unsigned int v16;\n unsigned int v17;\n int v18;\n void *ptr;\n char s[2];\n char v22;\n unsigned long long v23;\n v23 = __readfsqword(40u);\n v22 = 0;\n *(unsigned short *)s = 0;\n v2 = strlen(a1);\n v3 = (int)v2 + 2;\n v4 = (char *)malloc(v3);\n ptr = v4;\n __memcpy_chk(v4, a1, v2, v3);\n __memcpy_chk(&v4[v2], &unk_2004, 2LL, v3 - v2);\n if ((int)v2 + 1 <= 0) {\n v7 = 0;\n v8 = 0LL;\n } else {\n v5 = v4;\n v18 = 0;\n v6 = (long long)&v4[(unsigned int)v2 + 1];\n v7 = 0;\n v8 = 0LL;\n do {\n while (1) {\n v10 = *v5;\n if (*v5 != 32) break;\n if (s[0] == 111 && !s[1]) {\n if (v7 == v18) {\n if (v7 <= 0) {\n v18 = 4;\n v15 = 16LL;\n } else {\n v18 = 2 * v7;\n v15 = 8LL * v7;\n }\n v8 = realloc(v8, v15);\n }\n v11 = v7++;\n *((uint32_t *)v8 + v11) = 4;\n }\n if (s[0] == 111 && s[1] == 124 && !v22) {\n if (v7 == v18) {\n if (v7 <= 0) {\n v18 = 4;\n v17 = 16LL;\n } else {\n v18 = 2 * v7;\n v17 = 8LL * v7;\n }\n v8 = realloc(v8, v17);\n }\n v12 = v7++;\n *((uint32_t *)v8 + v12) = 2;\n }\n if (s[0] == 46 && s[1] == 124 && !v22) {\n if (v7 == v18) {\n if (v7 <= 0) {\n v18 = 4;\n v16 = 16LL;\n } else {\n v18 = 2 * v7;\n v16 = 8LL * v7;\n }\n v8 = realloc(v8, v16);\n }\n v13 = v7++;\n *((uint32_t *)v8 + v13) = 1;\n }\n ++v5;\n s[0] = 0;\n if (v5 == (char *)v6) goto LABEL_22;\n }\n v9 = strlen(s);\n if (v9 != 2) {\n s[v9] = v10;\n s[v9 + 1] = 0;\n }\n ++v5;\n } while (v5 != (char *)v6);\n }\nLABEL_22:\n free(ptr);\n *a2 = v7;\n return v8;\n}", + "ida_pseudo_norm": "void *func0(const char *a1, int *a2) {\n unsigned int v2;\n unsigned int v3;\n char *v4;\n char *v5;\n long long v6;\n int v7;\n void *v8;\n unsigned int v9;\n char v10;\n long long v11;\n long long v12;\n long long v13;\n unsigned int v15;\n unsigned int v16;\n unsigned int v17;\n int v18;\n void *ptr;\n char s[2];\n char v22;\n unsigned long long v23;\n v23 = __readfsqword(40u);\n v22 = 0;\n *(unsigned short *)s = 0;\n v2 = strlen(a1);\n v3 = (int)v2 + 2;\n v4 = (char *)malloc(v3);\n ptr = v4;\n __memcpy_chk(v4, a1, v2, v3);\n __memcpy_chk(&v4[v2], &unk_2004, 2LL, v3 - v2);\n if ((int)v2 + 1 <= 0) {\n v7 = 0;\n v8 = 0LL;\n } else {\n v5 = v4;\n v18 = 0;\n v6 = (long long)&v4[(unsigned int)v2 + 1];\n v7 = 0;\n v8 = 0LL;\n do {\n while (1) {\n v10 = *v5;\n if (*v5 != 32) break;\n if (s[0] == 111 && !s[1]) {\n if (v7 == v18) {\n if (v7 <= 0) {\n v18 = 4;\n v15 = 16LL;\n } else {\n v18 = 2 * v7;\n v15 = 8LL * v7;\n }\n v8 = realloc(v8, v15);\n }\n v11 = v7++;\n *((uint32_t *)v8 + v11) = 4;\n }\n if (s[0] == 111 && s[1] == 124 && !v22) {\n if (v7 == v18) {\n if (v7 <= 0) {\n v18 = 4;\n v17 = 16LL;\n } else {\n v18 = 2 * v7;\n v17 = 8LL * v7;\n }\n v8 = realloc(v8, v17);\n }\n v12 = v7++;\n *((uint32_t *)v8 + v12) = 2;\n }\n if (s[0] == 46 && s[1] == 124 && !v22) {\n if (v7 == v18) {\n if (v7 <= 0) {\n v18 = 4;\n v16 = 16LL;\n } else {\n v18 = 2 * v7;\n v16 = 8LL * v7;\n }\n v8 = realloc(v8, v16);\n }\n v13 = v7++;\n *((uint32_t *)v8 + v13) = 1;\n }\n ++v5;\n s[0] = 0;\n if (v5 == (char *)v6) goto LABEL_22;\n }\n v9 = strlen(s);\n if (v9 != 2) {\n s[v9] = v10;\n s[v9 + 1] = 0;\n }\n ++v5;\n } while (v5 != (char *)v6);\n }\nLABEL_22:\n free(ptr);\n *a2 = v7;\n return v8;\n}" + }, + { + "index": "HumanEval-C-18", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(const char *str, const char *substring) {\n int out = 0;\n int str_len = strlen(str);\n int sub_len = strlen(substring);\n if (str_len == 0) return 0;\n for (int i = 0; i <= str_len - sub_len; i++) {\n if (strncmp(&str[i], substring, sub_len) == 0) out++;\n }\n return out;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"\", \"x\") == 0);\n assert(func0(\"xyxyxyx\", \"x\") == 4);\n assert(func0(\"cacacacac\", \"cac\") == 4);\n assert(func0(\"john doe\", \"john\") == 1);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov [rbp+s2], rsi\nmov [rbp+var_10], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_8], eax\nmov rax, [rbp+s2]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\ncmp [rbp+var_8], 0\njnz short loc_11CF\nmov eax, 0\njmp short locret_1214\nloc_11CF:\nmov [rbp+var_C], 0\njmp short loc_1206\nloc_11D8:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax; n\nmov eax, [rbp+var_C]\nmovsxd rcx, eax\nmov rax, [rbp+s]\nadd rcx, rax\nmov rax, [rbp+s2]\nmov rsi, rax; s2\nmov rdi, rcx; s1\ncall _strncmp\ntest eax, eax\njnz short loc_1202\nadd [rbp+var_10], 1\nloc_1202:\nadd [rbp+var_C], 1\nloc_1206:\nmov eax, [rbp+var_8]\nsub eax, [rbp+var_4]\ncmp [rbp+var_C], eax\njle short loc_11D8\nmov eax, [rbp+var_10]\nlocret_1214:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, const char *a2)\n{\n unsigned int v3; // [rsp+10h] [rbp-10h]\n int i; // [rsp+14h] [rbp-Ch]\n int v5; // [rsp+18h] [rbp-8h]\n int v6; // [rsp+1Ch] [rbp-4h]\n\n v3 = 0;\n v5 = strlen(a1);\n v6 = strlen(a2);\n if ( !v5 )\n return 0LL;\n for ( i = 0; i <= v5 - v6; ++i )\n {\n if ( !strncmp(&a1[i], a2, v6) )\n ++v3;\n }\n return v3;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov [rbp+s2], rsi\nmov [rbp+var_10], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_8], eax\nmov rax, [rbp+s2]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\ncmp [rbp+var_8], 0\njnz short loc_11CF\nmov eax, 0\njmp short locret_1214\nloc_11CF:\nmov [rbp+var_C], 0\njmp short loc_1206\nloc_11D8:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax; n\nmov eax, [rbp+var_C]\nmovsxd rcx, eax\nmov rax, [rbp+s]\nadd rcx, rax\nmov rax, [rbp+s2]\nmov rsi, rax; s2\nmov rdi, rcx; s1\ncall _strncmp\ntest eax, eax\njnz short loc_1202\nadd [rbp+var_10], 1\nloc_1202:\nadd [rbp+var_C], 1\nloc_1206:\nmov eax, [rbp+var_8]\nsub eax, [rbp+var_4]\ncmp [rbp+var_C], eax\njle short loc_11D8\nmov eax, [rbp+var_10]\nlocret_1214:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(const char *a1, const char *a2)\n{\n unsigned int v3; // [rsp+10h] [rbp-10h]\n int i; // [rsp+14h] [rbp-Ch]\n int v5; // [rsp+18h] [rbp-8h]\n int v6; // [rsp+1Ch] [rbp-4h]\n\n v3 = 0;\n v5 = strlen(a1);\n v6 = strlen(a2);\n if ( !v5 )\n return 0LL;\n for ( i = 0; i <= v5 - v6; ++i )\n {\n if ( !strncmp(&a1[i], a2, v6) )\n ++v3;\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(const char *a1, const char *a2) {\n unsigned int v3;\n int i;\n int v5;\n int v6;\n v3 = 0;\n v5 = strlen(a1);\n v6 = strlen(a2);\n if (!v5) return 0LL;\n for (i = 0; i <= v5 - v6; ++i) {\n if (!strncmp(&a1[i], a2, v6)) ++v3;\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, const char *a2) {\n unsigned int v3;\n int i;\n int v5;\n int v6;\n v3 = 0;\n v5 = strlen(a1);\n v6 = strlen(a2);\n if (!v5) return 0LL;\n for (i = 0; i <= v5 - v6; ++i) {\n if (!strncmp(&a1[i], a2, v6)) ++v3;\n }\n return v3;\n}" + }, + { + "index": "HumanEval-C-18", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(const char *str, const char *substring) {\n int out = 0;\n int str_len = strlen(str);\n int sub_len = strlen(substring);\n if (str_len == 0) return 0;\n for (int i = 0; i <= str_len - sub_len; i++) {\n if (strncmp(&str[i], substring, sub_len) == 0) out++;\n }\n return out;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"\", \"x\") == 0);\n assert(func0(\"xyxyxyx\", \"x\") == 4);\n assert(func0(\"cacacacac\", \"cac\") == 4);\n assert(func0(\"john doe\", \"john\") == 1);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r14, rdi\nmov r12, rsi\ncall _strlen\nmov ebp, eax\ntest eax, eax\njz short loc_11E3\nmov rdi, r12; s\ncall _strlen\nmov edx, ebp\nsub edx, eax\njs short loc_11EE\nmov rbx, r14\nmov edx, edx\nlea r14, [r14+rdx+1]\nmov ebp, 0\nmovsxd r13, eax\nloc_11C6:\nmov rdx, r13; n\nmov rsi, r12; s2\nmov rdi, rbx; s1\ncall _strncmp\ncmp eax, 1\nadc ebp, 0\nadd rbx, 1\ncmp rbx, r14\njnz short loc_11C6\nloc_11E3:\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_11EE:\nmov ebp, 0\njmp short loc_11E3", + "ida_pseudo": "__int64 __fastcall func0(char *s1, char *s2)\n{\n unsigned int v2; // ebp\n int v3; // eax\n const char *v4; // rbx\n char *v5; // r14\n size_t v6; // r13\n\n v2 = strlen(s1);\n if ( v2 )\n {\n v3 = strlen(s2);\n if ( (int)(v2 - v3) < 0 )\n {\n return 0;\n }\n else\n {\n v4 = s1;\n v5 = &s1[v2 - v3 + 1];\n v2 = 0;\n v6 = v3;\n do\n v2 += strncmp(v4++, s2, v6) == 0;\n while ( v4 != v5 );\n }\n }\n return v2;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r14, rdi\nmov r12, rsi\ncall _strlen\nmov ebp, eax\ntest eax, eax\njz short loc_11E3\nmov rdi, r12; s\ncall _strlen\nmov edx, ebp\nsub edx, eax\njs short loc_11EE\nmov rbx, r14\nmov edx, edx\nlea r14, [r14+rdx+1]\nmov ebp, 0\nmovsxd r13, eax\nloc_11C6:\nmov rdx, r13; n\nmov rsi, r12; s2\nmov rdi, rbx; s1\ncall _strncmp\ncmp eax, 1\nadc ebp, 0\nadd rbx, 1\ncmp rbx, r14\njnz short loc_11C6\nloc_11E3:\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_11EE:\nmov ebp, 0\njmp short loc_11E3", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(char *s1, char *s2)\n{\n unsigned int v2; // ebp\n int v3; // eax\n const char *v4; // rbx\n char *v5; // r14\n size_t v6; // r13\n\n v2 = strlen(s1);\n if ( v2 )\n {\n v3 = strlen(s2);\n if ( (int)(v2 - v3) < 0 )\n {\n return 0;\n }\n else\n {\n v4 = s1;\n v5 = &s1[v2 - v3 + 1];\n v2 = 0;\n v6 = v3;\n do\n v2 += strncmp(v4++, s2, v6) == 0;\n while ( v4 != v5 );\n }\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(char *s1, char *s2) {\n unsigned int v2;\n int v3;\n const char *v4;\n char *v5;\n unsigned int v6;\n v2 = strlen(s1);\n if (v2) {\n v3 = strlen(s2);\n if ((int)(v2 - v3) < 0) {\n return 0;\n } else {\n v4 = s1;\n v5 = &s1[v2 - v3 + 1];\n v2 = 0;\n v6 = v3;\n do\n v2 += strncmp(v4++, s2, v6) == 0;\n while (v4 != v5);\n }\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(char *s1, char *s2) {\n unsigned int v2;\n int v3;\n const char *v4;\n char *v5;\n unsigned int v6;\n v2 = strlen(s1);\n if (v2) {\n v3 = strlen(s2);\n if ((int)(v2 - v3) < 0) {\n return 0;\n } else {\n v4 = s1;\n v5 = &s1[v2 - v3 + 1];\n v2 = 0;\n v6 = v3;\n do\n v2 += strncmp(v4++, s2, v6) == 0;\n while (v4 != v5);\n }\n }\n return v2;\n}" + }, + { + "index": "HumanEval-C-18", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(const char *str, const char *substring) {\n int out = 0;\n int str_len = strlen(str);\n int sub_len = strlen(substring);\n if (str_len == 0) return 0;\n for (int i = 0; i <= str_len - sub_len; i++) {\n if (strncmp(&str[i], substring, sub_len) == 0) out++;\n }\n return out;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"\", \"x\") == 0);\n assert(func0(\"xyxyxyx\", \"x\") == 4);\n assert(func0(\"cacacacac\", \"cac\") == 4);\n assert(func0(\"john doe\", \"john\") == 1);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\nmov r13, rsi\npush r12\npush rbp\npush rbx\nmov rbx, rdi\ncall _strlen\nmov ebp, eax\ntest eax, eax\njz short loc_12DD\nmov rdi, r13; s\nmov r14, rax\ncall _strlen\nsub r14d, eax\njs short loc_12F0\nmovsxd r14, r14d\nmovsxd r12, eax\nxor ebp, ebp\nlea r14, [rbx+r14+1]\nnop word ptr [rax+rax+00h]\nloc_12C0:\nmov rdi, rbx; s1\nmov rdx, r12; n\nmov rsi, r13; s2\ncall _strncmp\ncmp eax, 1\nadc ebp, 0\nadd rbx, 1\ncmp rbx, r14\njnz short loc_12C0\nloc_12DD:\npop rbx\nmov eax, ebp\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_12F0:\nxor ebp, ebp\njmp short loc_12DD", + "ida_pseudo": "__int64 __fastcall func0(char *s1, char *s2)\n{\n const char *v2; // rbx\n unsigned int v3; // eax\n unsigned int v4; // ebp\n unsigned int v5; // r14d\n int v6; // eax\n int v7; // r14d\n size_t v8; // r12\n char *v9; // r14\n\n v2 = s1;\n v3 = strlen(s1);\n v4 = v3;\n if ( v3 )\n {\n v5 = v3;\n v6 = strlen(s2);\n v7 = v5 - v6;\n if ( v7 < 0 )\n {\n return 0;\n }\n else\n {\n v8 = v6;\n v4 = 0;\n v9 = &s1[v7 + 1];\n do\n v4 += strncmp(v2++, s2, v8) == 0;\n while ( v2 != v9 );\n }\n }\n return v4;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\npush r14\npush r13\nmov r13, rsi\npush r12\npush rbp\npush rbx\nmov rbx, rdi\ncall _strlen\nmov ebp, eax\ntest eax, eax\njz short loc_12DD\nmov rdi, r13; s\nmov r14, rax\ncall _strlen\nsub r14d, eax\njs short loc_12F0\nmovsxd r14, r14d\nmovsxd r12, eax\nxor ebp, ebp\nlea r14, [rbx+r14+1]\nnop word ptr [rax+rax+00h]\nloc_12C0:\nmov rdi, rbx; s1\nmov rdx, r12; n\nmov rsi, r13; s2\ncall _strncmp\ncmp eax, 1\nadc ebp, 0\nadd rbx, 1\ncmp rbx, r14\njnz short loc_12C0\nloc_12DD:\npop rbx\nmov eax, ebp\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_12F0:\nxor ebp, ebp\njmp short loc_12DD", + "ida_strip_pseudo": "__int64 __fastcall sub_1280(char *s1, char *s2)\n{\n const char *v2; // rbx\n unsigned int v3; // eax\n unsigned int v4; // ebp\n unsigned int v5; // r14d\n int v6; // eax\n int v7; // r14d\n size_t v8; // r12\n char *v9; // r14\n\n v2 = s1;\n v3 = strlen(s1);\n v4 = v3;\n if ( v3 )\n {\n v5 = v3;\n v6 = strlen(s2);\n v7 = v5 - v6;\n if ( v7 < 0 )\n {\n return 0;\n }\n else\n {\n v8 = v6;\n v4 = 0;\n v9 = &s1[v7 + 1];\n do\n v4 += strncmp(v2++, s2, v8) == 0;\n while ( v2 != v9 );\n }\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1280(char *s1, char *s2) {\n const char *v2;\n unsigned int v3;\n unsigned int v4;\n unsigned int v5;\n int v6;\n int v7;\n unsigned int v8;\n char *v9;\n v2 = s1;\n v3 = strlen(s1);\n v4 = v3;\n if (v3) {\n v5 = v3;\n v6 = strlen(s2);\n v7 = v5 - v6;\n if (v7 < 0) {\n return 0;\n } else {\n v8 = v6;\n v4 = 0;\n v9 = &s1[v7 + 1];\n do\n v4 += strncmp(v2++, s2, v8) == 0;\n while (v2 != v9);\n }\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(char *s1, char *s2) {\n const char *v2;\n unsigned int v3;\n unsigned int v4;\n unsigned int v5;\n int v6;\n int v7;\n unsigned int v8;\n char *v9;\n v2 = s1;\n v3 = strlen(s1);\n v4 = v3;\n if (v3) {\n v5 = v3;\n v6 = strlen(s2);\n v7 = v5 - v6;\n if (v7 < 0) {\n return 0;\n } else {\n v8 = v6;\n v4 = 0;\n v9 = &s1[v7 + 1];\n do\n v4 += strncmp(v2++, s2, v8) == 0;\n while (v2 != v9);\n }\n }\n return v4;\n}" + }, + { + "index": "HumanEval-C-18", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(const char *str, const char *substring) {\n int out = 0;\n int str_len = strlen(str);\n int sub_len = strlen(substring);\n if (str_len == 0) return 0;\n for (int i = 0; i <= str_len - sub_len; i++) {\n if (strncmp(&str[i], substring, sub_len) == 0) out++;\n }\n return out;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"\", \"x\") == 0);\n assert(func0(\"xyxyxyx\", \"x\") == 4);\n assert(func0(\"cacacacac\", \"cac\") == 4);\n assert(func0(\"john doe\", \"john\") == 1);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\nmov r13, rsi\npush r12\npush rbp\npush rbx\nmov rbx, rdi\ncall _strlen\nmov ebp, eax\ntest eax, eax\njz short loc_12DD\nmov rdi, r13; s\nmov r14, rax\ncall _strlen\nsub r14d, eax\njs short loc_12F0\nmovsxd r14, r14d\nmovsxd r12, eax\nxor ebp, ebp\nlea r14, [rbx+r14+1]\nnop word ptr [rax+rax+00h]\nloc_12C0:\nmov rdi, rbx; s1\nmov rdx, r12; n\nmov rsi, r13; s2\ncall _strncmp\ncmp eax, 1\nadc ebp, 0\nadd rbx, 1\ncmp rbx, r14\njnz short loc_12C0\nloc_12DD:\npop rbx\nmov eax, ebp\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_12F0:\nxor ebp, ebp\njmp short loc_12DD", + "ida_pseudo": "__int64 __fastcall func0(char *s1, char *s2)\n{\n const char *v2; // rbx\n unsigned int v3; // eax\n unsigned int v4; // ebp\n unsigned int v5; // r14d\n int v6; // eax\n int v7; // r14d\n size_t v8; // r12\n char *v9; // r14\n\n v2 = s1;\n v3 = strlen(s1);\n v4 = v3;\n if ( v3 )\n {\n v5 = v3;\n v6 = strlen(s2);\n v7 = v5 - v6;\n if ( v7 < 0 )\n {\n return 0;\n }\n else\n {\n v8 = v6;\n v4 = 0;\n v9 = &s1[v7 + 1];\n do\n v4 += strncmp(v2++, s2, v8) == 0;\n while ( v2 != v9 );\n }\n }\n return v4;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\npush r14\npush r13\nmov r13, rsi\npush r12\npush rbp\npush rbx\nmov rbx, rdi\ncall _strlen\nmov ebp, eax\ntest eax, eax\njz short loc_12DD\nmov rdi, r13; s\nmov r14, rax\ncall _strlen\nsub r14d, eax\njs short loc_12F0\nmovsxd r14, r14d\nmovsxd r12, eax\nxor ebp, ebp\nlea r14, [rbx+r14+1]\nnop word ptr [rax+rax+00h]\nloc_12C0:\nmov rdi, rbx; s1\nmov rdx, r12; n\nmov rsi, r13; s2\ncall _strncmp\ncmp eax, 1\nadc ebp, 0\nadd rbx, 1\ncmp rbx, r14\njnz short loc_12C0\nloc_12DD:\npop rbx\nmov eax, ebp\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_12F0:\nxor ebp, ebp\njmp short loc_12DD", + "ida_strip_pseudo": "__int64 __fastcall sub_1280(char *s1, char *s2)\n{\n const char *v2; // rbx\n unsigned int v3; // eax\n unsigned int v4; // ebp\n unsigned int v5; // r14d\n int v6; // eax\n int v7; // r14d\n size_t v8; // r12\n char *v9; // r14\n\n v2 = s1;\n v3 = strlen(s1);\n v4 = v3;\n if ( v3 )\n {\n v5 = v3;\n v6 = strlen(s2);\n v7 = v5 - v6;\n if ( v7 < 0 )\n {\n return 0;\n }\n else\n {\n v8 = v6;\n v4 = 0;\n v9 = &s1[v7 + 1];\n do\n v4 += strncmp(v2++, s2, v8) == 0;\n while ( v2 != v9 );\n }\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1280(char *s1, char *s2) {\n const char *v2;\n unsigned int v3;\n unsigned int v4;\n unsigned int v5;\n int v6;\n int v7;\n unsigned int v8;\n char *v9;\n v2 = s1;\n v3 = strlen(s1);\n v4 = v3;\n if (v3) {\n v5 = v3;\n v6 = strlen(s2);\n v7 = v5 - v6;\n if (v7 < 0) {\n return 0;\n } else {\n v8 = v6;\n v4 = 0;\n v9 = &s1[v7 + 1];\n do\n v4 += strncmp(v2++, s2, v8) == 0;\n while (v2 != v9);\n }\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(char *s1, char *s2) {\n const char *v2;\n unsigned int v3;\n unsigned int v4;\n unsigned int v5;\n int v6;\n int v7;\n unsigned int v8;\n char *v9;\n v2 = s1;\n v3 = strlen(s1);\n v4 = v3;\n if (v3) {\n v5 = v3;\n v6 = strlen(s2);\n v7 = v5 - v6;\n if (v7 < 0) {\n return 0;\n } else {\n v8 = v6;\n v4 = 0;\n v9 = &s1[v7 + 1];\n do\n v4 += strncmp(v2++, s2, v8) == 0;\n while (v2 != v9);\n }\n }\n return v4;\n}" + }, + { + "index": "HumanEval-C-19", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "const char* func0(const char* numbers) {\n int count[10] = {0};\n const char* numto[10] = {\"zero\", \"one\", \"two\", \"three\", \"four\",\n \"five\", \"six\", \"seven\", \"eight\", \"nine\"};\n int index, i, j, k;\n static char out[1000];\n char current[6];\n index = 0;\n if (*numbers) {\n do {\n for (i = 0; numbers[i] != ' ' && numbers[i] != '\\0'; ++i) {\n current[i] = numbers[i];\n }\n current[i] = '\\0';\n for (j = 0; j < 10; ++j) {\n if (strcmp(current, numto[j]) == 0) {\n count[j]++;\n break;\n }\n }\n numbers += i + 1;\n } while (numbers[-1]);\n }\n for (i = 0; i < 10; ++i) {\n for (j = 0; j < count[i]; ++j) {\n for (k = 0; numto[i][k] != '\\0'; ++k, ++index) {\n out[index] = numto[i][k];\n }\n out[index++] = ' ';\n }\n }\n if (index > 0) {\n out[index - 1] = '\\0';\n } else {\n out[0] = '\\0';\n }\n return out;\n}", + "test": "#include \n#include \n\nint main() {\n assert(strcmp(func0(\"\"), \"\") == 0);\n assert(strcmp(func0(\"three\"), \"three\") == 0);\n assert(strcmp(func0(\"three five nine\"), \"three five nine\") == 0);\n assert(strcmp(func0(\"five zero four seven nine eight\"), \"zero four five seven eight nine\") == 0);\n assert(strcmp(func0(\"six five four three two one zero\"), \"zero one two three four five six\") == 0);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0B0h\nmov [rbp+var_A8], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\npxor xmm0, xmm0\nmovaps [rbp+var_90], xmm0\nmovaps [rbp+var_80], xmm0\nmovq [rbp+var_70], xmm0\nlea rax, aZero; \"zero\"\nmov [rbp+s2], rax\nlea rax, aOne; \"one\"\nmov [rbp+var_58], rax\nlea rax, aTwo; \"two\"\nmov [rbp+var_50], rax\nlea rax, s2; \"three\"\nmov [rbp+var_48], rax\nlea rax, aFour; \"four\"\nmov [rbp+var_40], rax\nlea rax, aFive; \"five\"\nmov [rbp+var_38], rax\nlea rax, aSix; \"six\"\nmov [rbp+var_30], rax\nlea rax, aSeven; \"seven\"\nmov [rbp+var_28], rax\nlea rax, aEight; \"eight\"\nmov [rbp+var_20], rax\nlea rax, aNine; \"nine\"\nmov [rbp+var_18], rax\nmov [rbp+var_A0], 0\nmov rax, [rbp+var_A8]\nmovzx eax, byte ptr [rax]\ntest al, al\njz loc_134A\nloc_124C:\nmov [rbp+var_9C], 0\njmp short loc_1281\nloc_1258:\nmov eax, [rbp+var_9C]\nmovsxd rdx, eax\nmov rax, [rbp+var_A8]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_9C]\ncdqe\nmov [rbp+rax+s1], dl\nadd [rbp+var_9C], 1\nloc_1281:\nmov eax, [rbp+var_9C]\nmovsxd rdx, eax\nmov rax, [rbp+var_A8]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njz short loc_12B5\nmov eax, [rbp+var_9C]\nmovsxd rdx, eax\nmov rax, [rbp+var_A8]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1258\nloc_12B5:\nmov eax, [rbp+var_9C]\ncdqe\nmov [rbp+rax+s1], 0\nmov [rbp+var_98], 0\njmp short loc_1318\nloc_12CE:\nmov eax, [rbp+var_98]\ncdqe\nmov rdx, [rbp+rax*8+s2]\nlea rax, [rbp+s1]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1311\nmov eax, [rbp+var_98]\ncdqe\nmov eax, dword ptr [rbp+rax*4+var_90]\nlea edx, [rax+1]\nmov eax, [rbp+var_98]\ncdqe\nmov dword ptr [rbp+rax*4+var_90], edx\njmp short loc_1321\nloc_1311:\nadd [rbp+var_98], 1\nloc_1318:\ncmp [rbp+var_98], 9\njle short loc_12CE\nloc_1321:\nmov eax, [rbp+var_9C]\ncdqe\nadd rax, 1\nadd [rbp+var_A8], rax\nmov rax, [rbp+var_A8]\nsub rax, 1\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_124C\nloc_134A:\nmov [rbp+var_9C], 0\njmp loc_1413\nloc_1359:\nmov [rbp+var_98], 0\njmp loc_13F1\nloc_1368:\nmov [rbp+var_94], 0\njmp short loc_13AF\nloc_1374:\nmov eax, [rbp+var_9C]\ncdqe\nmov rdx, [rbp+rax*8+s2]\nmov eax, [rbp+var_94]\ncdqe\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_A0]\ncdqe\nlea rcx, out_1\nmov [rax+rcx], dl\nadd [rbp+var_94], 1\nadd [rbp+var_A0], 1\nloc_13AF:\nmov eax, [rbp+var_9C]\ncdqe\nmov rdx, [rbp+rax*8+s2]\nmov eax, [rbp+var_94]\ncdqe\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1374\nmov eax, [rbp+var_A0]\nlea edx, [rax+1]\nmov [rbp+var_A0], edx\ncdqe\nlea rdx, out_1\nmov byte ptr [rax+rdx], 20h ; ' '\nadd [rbp+var_98], 1\nloc_13F1:\nmov eax, [rbp+var_9C]\ncdqe\nmov eax, dword ptr [rbp+rax*4+var_90]\ncmp [rbp+var_98], eax\njl loc_1368\nadd [rbp+var_9C], 1\nloc_1413:\ncmp [rbp+var_9C], 9\njle loc_1359\ncmp [rbp+var_A0], 0\njle short loc_1441\nmov eax, [rbp+var_A0]\nsub eax, 1\ncdqe\nlea rdx, out_1\nmov byte ptr [rax+rdx], 0\njmp short loc_1448\nloc_1441:\nmov cs:out_1, 0\nloc_1448:\nlea rax, out_1\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1463\ncall ___stack_chk_fail\nlocret_1463:\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(_BYTE *a1)\n{\n int v1; // eax\n _BYTE *v3; // [rsp+8h] [rbp-A8h]\n int v4; // [rsp+10h] [rbp-A0h]\n int i; // [rsp+14h] [rbp-9Ch]\n int k; // [rsp+14h] [rbp-9Ch]\n int j; // [rsp+18h] [rbp-98h]\n int m; // [rsp+18h] [rbp-98h]\n int n; // [rsp+1Ch] [rbp-94h]\n _OWORD v10[2]; // [rsp+20h] [rbp-90h] BYREF\n __int64 v11; // [rsp+40h] [rbp-70h]\n char *s2[10]; // [rsp+50h] [rbp-60h]\n char s1[6]; // [rsp+A2h] [rbp-Eh] BYREF\n unsigned __int64 v14; // [rsp+A8h] [rbp-8h]\n\n v3 = a1;\n v14 = __readfsqword(0x28u);\n memset(v10, 0, sizeof(v10));\n v11 = 0LL;\n s2[0] = \"zero\";\n s2[1] = \"one\";\n s2[2] = \"two\";\n s2[3] = \"three\";\n s2[4] = \"four\";\n s2[5] = \"five\";\n s2[6] = \"six\";\n s2[7] = \"seven\";\n s2[8] = \"eight\";\n s2[9] = \"nine\";\n v4 = 0;\n if ( *a1 )\n {\n do\n {\n for ( i = 0; v3[i] != 32 && v3[i]; ++i )\n s1[i] = v3[i];\n s1[i] = 0;\n for ( j = 0; j <= 9; ++j )\n {\n if ( !strcmp(s1, s2[j]) )\n {\n ++*((_DWORD *)v10 + j);\n break;\n }\n }\n v3 += i + 1;\n }\n while ( *(v3 - 1) );\n }\n for ( k = 0; k <= 9; ++k )\n {\n for ( m = 0; m < *((_DWORD *)v10 + k); ++m )\n {\n for ( n = 0; s2[k][n]; ++n )\n out_1[v4++] = s2[k][n];\n v1 = v4++;\n out_1[v1] = 32;\n }\n }\n if ( v4 <= 0 )\n out_1[0] = 0;\n else\n out_1[v4 - 1] = 0;\n return out_1;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0B0h\nmov [rbp+var_A8], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\npxor xmm0, xmm0\nmovaps [rbp+var_90], xmm0\nmovaps [rbp+var_80], xmm0\nmovq [rbp+var_70], xmm0\nlea rax, aZero; \"zero\"\nmov [rbp+s2], rax\nlea rax, aOne; \"one\"\nmov [rbp+var_58], rax\nlea rax, aTwo; \"two\"\nmov [rbp+var_50], rax\nlea rax, s2; \"three\"\nmov [rbp+var_48], rax\nlea rax, aFour; \"four\"\nmov [rbp+var_40], rax\nlea rax, aFive; \"five\"\nmov [rbp+var_38], rax\nlea rax, aSix; \"six\"\nmov [rbp+var_30], rax\nlea rax, aSeven; \"seven\"\nmov [rbp+var_28], rax\nlea rax, aEight; \"eight\"\nmov [rbp+var_20], rax\nlea rax, aNine; \"nine\"\nmov [rbp+var_18], rax\nmov [rbp+var_A0], 0\nmov rax, [rbp+var_A8]\nmovzx eax, byte ptr [rax]\ntest al, al\njz loc_134A\nloc_124C:\nmov [rbp+var_9C], 0\njmp short loc_1281\nloc_1258:\nmov eax, [rbp+var_9C]\nmovsxd rdx, eax\nmov rax, [rbp+var_A8]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_9C]\ncdqe\nmov [rbp+rax+s1], dl\nadd [rbp+var_9C], 1\nloc_1281:\nmov eax, [rbp+var_9C]\nmovsxd rdx, eax\nmov rax, [rbp+var_A8]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njz short loc_12B5\nmov eax, [rbp+var_9C]\nmovsxd rdx, eax\nmov rax, [rbp+var_A8]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1258\nloc_12B5:\nmov eax, [rbp+var_9C]\ncdqe\nmov [rbp+rax+s1], 0\nmov [rbp+var_98], 0\njmp short loc_1318\nloc_12CE:\nmov eax, [rbp+var_98]\ncdqe\nmov rdx, [rbp+rax*8+s2]\nlea rax, [rbp+s1]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1311\nmov eax, [rbp+var_98]\ncdqe\nmov eax, dword ptr [rbp+rax*4+var_90]\nlea edx, [rax+1]\nmov eax, [rbp+var_98]\ncdqe\nmov dword ptr [rbp+rax*4+var_90], edx\njmp short loc_1321\nloc_1311:\nadd [rbp+var_98], 1\nloc_1318:\ncmp [rbp+var_98], 9\njle short loc_12CE\nloc_1321:\nmov eax, [rbp+var_9C]\ncdqe\nadd rax, 1\nadd [rbp+var_A8], rax\nmov rax, [rbp+var_A8]\nsub rax, 1\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_124C\nloc_134A:\nmov [rbp+var_9C], 0\njmp loc_1413\nloc_1359:\nmov [rbp+var_98], 0\njmp loc_13F1\nloc_1368:\nmov [rbp+var_94], 0\njmp short loc_13AF\nloc_1374:\nmov eax, [rbp+var_9C]\ncdqe\nmov rdx, [rbp+rax*8+s2]\nmov eax, [rbp+var_94]\ncdqe\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_A0]\ncdqe\nlea rcx, byte_4040\nmov [rax+rcx], dl\nadd [rbp+var_94], 1\nadd [rbp+var_A0], 1\nloc_13AF:\nmov eax, [rbp+var_9C]\ncdqe\nmov rdx, [rbp+rax*8+s2]\nmov eax, [rbp+var_94]\ncdqe\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1374\nmov eax, [rbp+var_A0]\nlea edx, [rax+1]\nmov [rbp+var_A0], edx\ncdqe\nlea rdx, byte_4040\nmov byte ptr [rax+rdx], 20h ; ' '\nadd [rbp+var_98], 1\nloc_13F1:\nmov eax, [rbp+var_9C]\ncdqe\nmov eax, dword ptr [rbp+rax*4+var_90]\ncmp [rbp+var_98], eax\njl loc_1368\nadd [rbp+var_9C], 1\nloc_1413:\ncmp [rbp+var_9C], 9\njle loc_1359\ncmp [rbp+var_A0], 0\njle short loc_1441\nmov eax, [rbp+var_A0]\nsub eax, 1\ncdqe\nlea rdx, byte_4040\nmov byte ptr [rax+rdx], 0\njmp short loc_1448\nloc_1441:\nmov cs:byte_4040, 0\nloc_1448:\nlea rax, byte_4040\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1463\ncall ___stack_chk_fail\nlocret_1463:\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1189(_BYTE *a1)\n{\n int v1; // eax\n _BYTE *v3; // [rsp+8h] [rbp-A8h]\n int v4; // [rsp+10h] [rbp-A0h]\n int i; // [rsp+14h] [rbp-9Ch]\n int k; // [rsp+14h] [rbp-9Ch]\n int j; // [rsp+18h] [rbp-98h]\n int m; // [rsp+18h] [rbp-98h]\n int n; // [rsp+1Ch] [rbp-94h]\n _OWORD v10[2]; // [rsp+20h] [rbp-90h] BYREF\n __int64 v11; // [rsp+40h] [rbp-70h]\n char *s2[10]; // [rsp+50h] [rbp-60h]\n char s1[6]; // [rsp+A2h] [rbp-Eh] BYREF\n unsigned __int64 v14; // [rsp+A8h] [rbp-8h]\n\n v3 = a1;\n v14 = __readfsqword(0x28u);\n memset(v10, 0, sizeof(v10));\n v11 = 0LL;\n s2[0] = \"zero\";\n s2[1] = \"one\";\n s2[2] = \"two\";\n s2[3] = \"three\";\n s2[4] = \"four\";\n s2[5] = \"five\";\n s2[6] = \"six\";\n s2[7] = \"seven\";\n s2[8] = \"eight\";\n s2[9] = \"nine\";\n v4 = 0;\n if ( *a1 )\n {\n do\n {\n for ( i = 0; v3[i] != 32 && v3[i]; ++i )\n s1[i] = v3[i];\n s1[i] = 0;\n for ( j = 0; j <= 9; ++j )\n {\n if ( !strcmp(s1, s2[j]) )\n {\n ++*((_DWORD *)v10 + j);\n break;\n }\n }\n v3 += i + 1;\n }\n while ( *(v3 - 1) );\n }\n for ( k = 0; k <= 9; ++k )\n {\n for ( m = 0; m < *((_DWORD *)v10 + k); ++m )\n {\n for ( n = 0; s2[k][n]; ++n )\n byte_4040[v4++] = s2[k][n];\n v1 = v4++;\n byte_4040[v1] = 32;\n }\n }\n if ( v4 <= 0 )\n byte_4040[0] = 0;\n else\n byte_4040[v4 - 1] = 0;\n return byte_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1189(uint8_t *a1) {\n int v1;\n uint8_t *v3;\n int v4;\n int i;\n int k;\n int j;\n int m;\n int n;\n long double v10[2];\n long long v11;\n char *s2[10];\n char s1[6];\n unsigned long long v14;\n v3 = a1;\n v14 = __readfsqword(40u);\n memset(v10, 0, sizeof(v10));\n v11 = 0LL;\n s2[0] = \"zero\";\n s2[1] = \"one\";\n s2[2] = \"two\";\n s2[3] = \"three\";\n s2[4] = \"four\";\n s2[5] = \"five\";\n s2[6] = \"six\";\n s2[7] = \"seven\";\n s2[8] = \"eight\";\n s2[9] = \"nine\";\n v4 = 0;\n if (*a1) {\n do {\n for (i = 0; v3[i] != 32 && v3[i]; ++i) s1[i] = v3[i];\n s1[i] = 0;\n for (j = 0; j <= 9; ++j) {\n if (!strcmp(s1, s2[j])) {\n ++*((uint32_t *)v10 + j);\n break;\n }\n }\n v3 += i + 1;\n } while (*(v3 - 1));\n }\n for (k = 0; k <= 9; ++k) {\n for (m = 0; m < *((uint32_t *)v10 + k); ++m) {\n for (n = 0; s2[k][n]; ++n) byte_4040[v4++] = s2[k][n];\n v1 = v4++;\n byte_4040[v1] = 32;\n }\n }\n if (v4 <= 0)\n byte_4040[0] = 0;\n else\n byte_4040[v4 - 1] = 0;\n return byte_4040;\n}", + "ida_pseudo_norm": "char *func0(uint8_t *a1) {\n int v1;\n uint8_t *v3;\n int v4;\n int i;\n int k;\n int j;\n int m;\n int n;\n long double v10[2];\n long long v11;\n char *s2[10];\n char s1[6];\n unsigned long long v14;\n v3 = a1;\n v14 = __readfsqword(40u);\n memset(v10, 0, sizeof(v10));\n v11 = 0LL;\n s2[0] = \"zero\";\n s2[1] = \"one\";\n s2[2] = \"two\";\n s2[3] = \"three\";\n s2[4] = \"four\";\n s2[5] = \"five\";\n s2[6] = \"six\";\n s2[7] = \"seven\";\n s2[8] = \"eight\";\n s2[9] = \"nine\";\n v4 = 0;\n if (*a1) {\n do {\n for (i = 0; v3[i] != 32 && v3[i]; ++i) s1[i] = v3[i];\n s1[i] = 0;\n for (j = 0; j <= 9; ++j) {\n if (!strcmp(s1, s2[j])) {\n ++*((uint32_t *)v10 + j);\n break;\n }\n }\n v3 += i + 1;\n } while (*(v3 - 1));\n }\n for (k = 0; k <= 9; ++k) {\n for (m = 0; m < *((uint32_t *)v10 + k); ++m) {\n for (n = 0; s2[k][n]; ++n) out_1[v4++] = s2[k][n];\n v1 = v4++;\n out_1[v1] = 32;\n }\n }\n if (v4 <= 0)\n out_1[0] = 0;\n else\n out_1[v4 - 1] = 0;\n return out_1;\n}" + }, + { + "index": "HumanEval-C-19", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "const char* func0(const char* numbers) {\n int count[10] = {0};\n const char* numto[10] = {\"zero\", \"one\", \"two\", \"three\", \"four\",\n \"five\", \"six\", \"seven\", \"eight\", \"nine\"};\n int index, i, j, k;\n static char out[1000];\n char current[6];\n index = 0;\n if (*numbers) {\n do {\n for (i = 0; numbers[i] != ' ' && numbers[i] != '\\0'; ++i) {\n current[i] = numbers[i];\n }\n current[i] = '\\0';\n for (j = 0; j < 10; ++j) {\n if (strcmp(current, numto[j]) == 0) {\n count[j]++;\n break;\n }\n }\n numbers += i + 1;\n } while (numbers[-1]);\n }\n for (i = 0; i < 10; ++i) {\n for (j = 0; j < count[i]; ++j) {\n for (k = 0; numto[i][k] != '\\0'; ++k, ++index) {\n out[index] = numto[i][k];\n }\n out[index++] = ' ';\n }\n }\n if (index > 0) {\n out[index - 1] = '\\0';\n } else {\n out[0] = '\\0';\n }\n return out;\n}", + "test": "#include \n#include \n\nint main() {\n assert(strcmp(func0(\"\"), \"\") == 0);\n assert(strcmp(func0(\"three\"), \"three\") == 0);\n assert(strcmp(func0(\"three five nine\"), \"three five nine\") == 0);\n assert(strcmp(func0(\"five zero four seven nine eight\"), \"zero four five seven eight nine\") == 0);\n assert(strcmp(func0(\"six five four three two one zero\"), \"zero one two three four five six\") == 0);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 98h\nmov rax, fs:28h\nmov [rsp+0C8h+var_40], rax\nxor eax, eax\npxor xmm0, xmm0\nmovaps [rsp+0C8h+var_C8], xmm0\nmovaps [rsp+0C8h+var_B8], xmm0\nmov [rsp+0C8h+var_A8], 0\nlea rax, aZero; \"zero\"\nmov [rsp+0C8h+s2], rax\nlea rax, aOne; \"one\"\nmov [rsp+0C8h+var_90], rax\nlea rax, aTwo; \"two\"\nmov [rsp+0C8h+var_88], rax\nlea rax, s2; \"three\"\nmov [rsp+0C8h+var_80], rax\nlea rax, aFour; \"four\"\nmov [rsp+0C8h+var_78], rax\nlea rax, aFive; \"five\"\nmov [rsp+0C8h+var_70], rax\nlea rax, aSix; \"six\"\nmov [rsp+0C8h+var_68], rax\nlea rax, aSeven; \"seven\"\nmov [rsp+0C8h+var_60], rax\nlea rax, aEight; \"eight\"\nmov [rsp+0C8h+var_58], rax\nlea rax, aThreeFiveNine+0Bh; \"nine\"\nmov [rsp+0C8h+var_50], rax\ncmp byte ptr [rdi], 0\njz loc_12D1\nmov rbp, rdi\nmov r15d, 0\nlea r14, [rsp+0C8h+var_47]\nlea r13, [rsp+0C8h+s1]\njmp short loc_127F\nloc_1263:\nmov eax, 0\nmov r12, r15\njmp short loc_12A5\nloc_126D:\nmovsxd rbx, ebx\nadd dword ptr [rsp+rbx*4+0C8h+var_C8], 1\nloc_1274:\nlea rbp, [rbp+r12+1]\ncmp byte ptr [rbp-1], 0\njz short loc_12D1\nloc_127F:\nmovzx edx, byte ptr [rbp+0]\ntest dl, 0DFh\njz short loc_1263\nmov eax, 1\nloc_128D:\nmov [r14+rax], dl\nmovzx edx, byte ptr [rbp+rax+0]\nmov r12, rax\nadd rax, 1\ntest dl, 0DFh\njnz short loc_128D\nmov eax, r12d\nloc_12A5:\ncdqe\nmov [rsp+rax+0C8h+s1], 0\nmov ebx, 0\nloc_12B4:\nmov rsi, [rsp+rbx*8+0C8h+s2]; s2\nmov rdi, r13; s1\ncall _strcmp\ntest eax, eax\njz short loc_126D\nadd rbx, 1\ncmp rbx, 0Ah\njnz short loc_12B4\njmp short loc_1274\nloc_12D1:\nmov r12d, 0\nmov r8d, 0\nlea rdi, unk_403F\nlea rbp, [rdi+1]\njmp short loc_1338\nloc_12EA:\nmov [rax+rdi], dl\nmov rcx, rax\nadd rax, 1\nmovzx edx, byte ptr [rsi+rax-1]\ntest dl, dl\njnz short loc_12EA\nloc_12FD:\nlea r8d, [rcx+1]\nmovsxd rcx, ecx\nmov byte ptr [rbp+rcx+0], 20h ; ' '\nadd r9d, 1\ncmp r9d, r11d\njz short loc_132E\nloc_1312:\nlea eax, [r8+1]\ncdqe\nmov edx, r10d\nmovsxd rcx, r8d\nmov rsi, rbx\nsub rsi, rcx\nmov ecx, r8d\ntest r10b, r10b\njnz short loc_12EA\njmp short loc_12FD\nloc_132E:\nadd r12, 1\ncmp r12, 0Ah\njz short loc_1352\nloc_1338:\nmov r11d, dword ptr [rsp+r12*4+0C8h+var_C8]\ntest r11d, r11d\njle short loc_132E\nmov rbx, [rsp+r12*8+0C8h+s2]\nmovzx r10d, byte ptr [rbx]\nmov r9d, 0\njmp short loc_1312\nloc_1352:\ntest r8d, r8d\njle short loc_1394\nlea eax, [r8-1]\ncdqe\nlea rdx, out_1\nmov byte ptr [rdx+rax], 0\nloc_1368:\nmov rax, [rsp+0C8h+var_40]\nsub rax, fs:28h\njnz short loc_139D\nlea rax, out_1\nadd rsp, 98h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1394:\nmov cs:out_1, 0\njmp short loc_1368\nloc_139D:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(char *a1)\n{\n char *v1; // rbp\n int v2; // eax\n __int64 v3; // r12\n char v4; // dl\n __int64 v5; // rax\n __int64 v6; // rbx\n __int64 v7; // r12\n int v8; // r8d\n int j; // ecx\n __int64 v10; // rax\n char v11; // dl\n int i; // r9d\n int v13; // r11d\n char *v14; // rbx\n char v15; // r10\n _OWORD v17[2]; // [rsp+0h] [rbp-C8h] BYREF\n __int64 v18; // [rsp+20h] [rbp-A8h]\n _WORD s2[41]; // [rsp+30h] [rbp-98h]\n char s1[6]; // [rsp+82h] [rbp-46h] BYREF\n unsigned __int64 v21; // [rsp+88h] [rbp-40h]\n\n v21 = __readfsqword(0x28u);\n memset(v17, 0, sizeof(v17));\n v18 = 0LL;\n *(_QWORD *)s2 = \"zero\";\n *(_QWORD *)&s2[4] = \"one\";\n *(_QWORD *)&s2[8] = \"two\";\n *(_QWORD *)&s2[12] = \"three\";\n *(_QWORD *)&s2[16] = \"four\";\n *(_QWORD *)&s2[20] = \"five\";\n *(_QWORD *)&s2[24] = \"six\";\n *(_QWORD *)&s2[28] = \"seven\";\n *(_QWORD *)&s2[32] = \"eight\";\n *(_QWORD *)&s2[36] = \"nine\";\n if ( *a1 )\n {\n v1 = a1;\n do\n {\n v4 = *v1;\n if ( (*v1 & 0xDF) != 0 )\n {\n v5 = 1LL;\n do\n {\n *((_BYTE *)&s2[40] + v5 + 1) = v4;\n v4 = v1[v5];\n v3 = v5++;\n }\n while ( (v4 & 0xDF) != 0 );\n v2 = v3;\n }\n else\n {\n v2 = 0;\n v3 = 0LL;\n }\n s1[v2] = 0;\n v6 = 0LL;\n while ( strcmp(s1, *(const char **)&s2[4 * v6]) )\n {\n if ( ++v6 == 10 )\n goto LABEL_5;\n }\n ++*((_DWORD *)v17 + (int)v6);\nLABEL_5:\n v1 += v3 + 1;\n }\n while ( *(v1 - 1) );\n }\n v7 = 0LL;\n v8 = 0;\n do\n {\n v13 = *((_DWORD *)v17 + v7);\n if ( v13 > 0 )\n {\n v14 = *(char **)&s2[4 * v7];\n v15 = *v14;\n for ( i = 0; i != v13; ++i )\n {\n v10 = v8 + 1;\n v11 = v15;\n for ( j = v8; v11; v11 = v14[v10 - v8 - 1] )\n {\n *((_BYTE *)&unk_403F + v10) = v11;\n j = v10++;\n }\n v8 = j + 1;\n *((_BYTE *)&unk_403F + j + 1) = 32;\n }\n }\n ++v7;\n }\n while ( v7 != 10 );\n if ( v8 <= 0 )\n out_1[0] = 0;\n else\n out_1[v8 - 1] = 0;\n return out_1;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 98h\nmov rax, fs:28h\nmov [rsp+0C8h+var_40], rax\nxor eax, eax\npxor xmm0, xmm0\nmovaps [rsp+0C8h+var_C8], xmm0\nmovaps [rsp+0C8h+var_B8], xmm0\nmov [rsp+0C8h+var_A8], 0\nlea rax, aZero; \"zero\"\nmov [rsp+0C8h+s2], rax\nlea rax, aOne; \"one\"\nmov [rsp+0C8h+var_90], rax\nlea rax, aTwo; \"two\"\nmov [rsp+0C8h+var_88], rax\nlea rax, s2; \"three\"\nmov [rsp+0C8h+var_80], rax\nlea rax, aFour; \"four\"\nmov [rsp+0C8h+var_78], rax\nlea rax, aFive; \"five\"\nmov [rsp+0C8h+var_70], rax\nlea rax, aSix; \"six\"\nmov [rsp+0C8h+var_68], rax\nlea rax, aSeven; \"seven\"\nmov [rsp+0C8h+var_60], rax\nlea rax, aEight; \"eight\"\nmov [rsp+0C8h+var_58], rax\nlea rax, aThreeFiveNine+0Bh; \"nine\"\nmov [rsp+0C8h+var_50], rax\ncmp byte ptr [rdi], 0\njz loc_12D1\nmov rbp, rdi\nmov r15d, 0\nlea r14, [rsp+0C8h+var_47]\nlea r13, [rsp+0C8h+s1]\njmp short loc_127F\nloc_1263:\nmov eax, 0\nmov r12, r15\njmp short loc_12A5\nloc_126D:\nmovsxd rbx, ebx\nadd dword ptr [rsp+rbx*4+0C8h+var_C8], 1\nloc_1274:\nlea rbp, [rbp+r12+1]\ncmp byte ptr [rbp-1], 0\njz short loc_12D1\nloc_127F:\nmovzx edx, byte ptr [rbp+0]\ntest dl, 0DFh\njz short loc_1263\nmov eax, 1\nloc_128D:\nmov [r14+rax], dl\nmovzx edx, byte ptr [rbp+rax+0]\nmov r12, rax\nadd rax, 1\ntest dl, 0DFh\njnz short loc_128D\nmov eax, r12d\nloc_12A5:\ncdqe\nmov [rsp+rax+0C8h+s1], 0\nmov ebx, 0\nloc_12B4:\nmov rsi, [rsp+rbx*8+0C8h+s2]; s2\nmov rdi, r13; s1\ncall _strcmp\ntest eax, eax\njz short loc_126D\nadd rbx, 1\ncmp rbx, 0Ah\njnz short loc_12B4\njmp short loc_1274\nloc_12D1:\nmov r12d, 0\nmov r8d, 0\nlea rdi, unk_403F\nlea rbp, [rdi+1]\njmp short loc_1338\nloc_12EA:\nmov [rax+rdi], dl\nmov rcx, rax\nadd rax, 1\nmovzx edx, byte ptr [rsi+rax-1]\ntest dl, dl\njnz short loc_12EA\nloc_12FD:\nlea r8d, [rcx+1]\nmovsxd rcx, ecx\nmov byte ptr [rbp+rcx+0], 20h ; ' '\nadd r9d, 1\ncmp r9d, r11d\njz short loc_132E\nloc_1312:\nlea eax, [r8+1]\ncdqe\nmov edx, r10d\nmovsxd rcx, r8d\nmov rsi, rbx\nsub rsi, rcx\nmov ecx, r8d\ntest r10b, r10b\njnz short loc_12EA\njmp short loc_12FD\nloc_132E:\nadd r12, 1\ncmp r12, 0Ah\njz short loc_1352\nloc_1338:\nmov r11d, dword ptr [rsp+r12*4+0C8h+var_C8]\ntest r11d, r11d\njle short loc_132E\nmov rbx, [rsp+r12*8+0C8h+s2]\nmovzx r10d, byte ptr [rbx]\nmov r9d, 0\njmp short loc_1312\nloc_1352:\ntest r8d, r8d\njle short loc_1394\nlea eax, [r8-1]\ncdqe\nlea rdx, byte_4040\nmov byte ptr [rdx+rax], 0\nloc_1368:\nmov rax, [rsp+0C8h+var_40]\nsub rax, fs:28h\njnz short loc_139D\nlea rax, byte_4040\nadd rsp, 98h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1394:\nmov cs:byte_4040, 0\njmp short loc_1368\nloc_139D:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_1189(char *a1)\n{\n char *v1; // rbp\n int v2; // eax\n __int64 v3; // r12\n char v4; // dl\n __int64 v5; // rax\n __int64 v6; // rbx\n __int64 v7; // r12\n int v8; // r8d\n int j; // ecx\n __int64 v10; // rax\n char v11; // dl\n int i; // r9d\n int v13; // r11d\n char *v14; // rbx\n char v15; // r10\n _OWORD v17[2]; // [rsp+0h] [rbp-C8h] BYREF\n __int64 v18; // [rsp+20h] [rbp-A8h]\n _WORD s2[41]; // [rsp+30h] [rbp-98h]\n char s1[6]; // [rsp+82h] [rbp-46h] BYREF\n unsigned __int64 v21; // [rsp+88h] [rbp-40h]\n\n v21 = __readfsqword(0x28u);\n memset(v17, 0, sizeof(v17));\n v18 = 0LL;\n *(_QWORD *)s2 = \"zero\";\n *(_QWORD *)&s2[4] = \"one\";\n *(_QWORD *)&s2[8] = \"two\";\n *(_QWORD *)&s2[12] = \"three\";\n *(_QWORD *)&s2[16] = \"four\";\n *(_QWORD *)&s2[20] = \"five\";\n *(_QWORD *)&s2[24] = \"six\";\n *(_QWORD *)&s2[28] = \"seven\";\n *(_QWORD *)&s2[32] = \"eight\";\n *(_QWORD *)&s2[36] = \"nine\";\n if ( *a1 )\n {\n v1 = a1;\n do\n {\n v4 = *v1;\n if ( (*v1 & 0xDF) != 0 )\n {\n v5 = 1LL;\n do\n {\n *((_BYTE *)&s2[40] + v5 + 1) = v4;\n v4 = v1[v5];\n v3 = v5++;\n }\n while ( (v4 & 0xDF) != 0 );\n v2 = v3;\n }\n else\n {\n v2 = 0;\n v3 = 0LL;\n }\n s1[v2] = 0;\n v6 = 0LL;\n while ( strcmp(s1, *(const char **)&s2[4 * v6]) )\n {\n if ( ++v6 == 10 )\n goto LABEL_5;\n }\n ++*((_DWORD *)v17 + (int)v6);\nLABEL_5:\n v1 += v3 + 1;\n }\n while ( *(v1 - 1) );\n }\n v7 = 0LL;\n v8 = 0;\n do\n {\n v13 = *((_DWORD *)v17 + v7);\n if ( v13 > 0 )\n {\n v14 = *(char **)&s2[4 * v7];\n v15 = *v14;\n for ( i = 0; i != v13; ++i )\n {\n v10 = v8 + 1;\n v11 = v15;\n for ( j = v8; v11; v11 = v14[v10 - v8 - 1] )\n {\n *((_BYTE *)&unk_403F + v10) = v11;\n j = v10++;\n }\n v8 = j + 1;\n *((_BYTE *)&unk_403F + j + 1) = 32;\n }\n }\n ++v7;\n }\n while ( v7 != 10 );\n if ( v8 <= 0 )\n byte_4040[0] = 0;\n else\n byte_4040[v8 - 1] = 0;\n return byte_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1189(char *a1) {\n char *v1;\n int v2;\n long long v3;\n char v4;\n long long v5;\n long long v6;\n long long v7;\n int v8;\n int j;\n long long v10;\n char v11;\n int i;\n int v13;\n char *v14;\n char v15;\n long double v17[2];\n long long v18;\n unsigned short s2[41];\n char s1[6];\n unsigned long long v21;\n v21 = __readfsqword(40u);\n memset(v17, 0, sizeof(v17));\n v18 = 0LL;\n *(uint64_t *)s2 = \"zero\";\n *(uint64_t *)&s2[4] = \"one\";\n *(uint64_t *)&s2[8] = \"two\";\n *(uint64_t *)&s2[12] = \"three\";\n *(uint64_t *)&s2[16] = \"four\";\n *(uint64_t *)&s2[20] = \"five\";\n *(uint64_t *)&s2[24] = \"six\";\n *(uint64_t *)&s2[28] = \"seven\";\n *(uint64_t *)&s2[32] = \"eight\";\n *(uint64_t *)&s2[36] = \"nine\";\n if (*a1) {\n v1 = a1;\n do {\n v4 = *v1;\n if ((*v1 & 223) != 0) {\n v5 = 1LL;\n do {\n *((uint8_t *)&s2[40] + v5 + 1) = v4;\n v4 = v1[v5];\n v3 = v5++;\n } while ((v4 & 223) != 0);\n v2 = v3;\n } else {\n v2 = 0;\n v3 = 0LL;\n }\n s1[v2] = 0;\n v6 = 0LL;\n while (strcmp(s1, *(const char **)&s2[4 * v6])) {\n if (++v6 == 10) goto LABEL_5;\n }\n ++*((uint32_t *)v17 + (int)v6);\n LABEL_5:\n v1 += v3 + 1;\n } while (*(v1 - 1));\n }\n v7 = 0LL;\n v8 = 0;\n do {\n v13 = *((uint32_t *)v17 + v7);\n if (v13 > 0) {\n v14 = *(char **)&s2[4 * v7];\n v15 = *v14;\n for (i = 0; i != v13; ++i) {\n v10 = v8 + 1;\n v11 = v15;\n for (j = v8; v11; v11 = v14[v10 - v8 - 1]) {\n *((uint8_t *)&unk_403F + v10) = v11;\n j = v10++;\n }\n v8 = j + 1;\n *((uint8_t *)&unk_403F + j + 1) = 32;\n }\n }\n ++v7;\n } while (v7 != 10);\n if (v8 <= 0)\n byte_4040[0] = 0;\n else\n byte_4040[v8 - 1] = 0;\n return byte_4040;\n}", + "ida_pseudo_norm": "char *func0(char *a1) {\n char *v1;\n int v2;\n long long v3;\n char v4;\n long long v5;\n long long v6;\n long long v7;\n int v8;\n int j;\n long long v10;\n char v11;\n int i;\n int v13;\n char *v14;\n char v15;\n long double v17[2];\n long long v18;\n unsigned short s2[41];\n char s1[6];\n unsigned long long v21;\n v21 = __readfsqword(40u);\n memset(v17, 0, sizeof(v17));\n v18 = 0LL;\n *(uint64_t *)s2 = \"zero\";\n *(uint64_t *)&s2[4] = \"one\";\n *(uint64_t *)&s2[8] = \"two\";\n *(uint64_t *)&s2[12] = \"three\";\n *(uint64_t *)&s2[16] = \"four\";\n *(uint64_t *)&s2[20] = \"five\";\n *(uint64_t *)&s2[24] = \"six\";\n *(uint64_t *)&s2[28] = \"seven\";\n *(uint64_t *)&s2[32] = \"eight\";\n *(uint64_t *)&s2[36] = \"nine\";\n if (*a1) {\n v1 = a1;\n do {\n v4 = *v1;\n if ((*v1 & 223) != 0) {\n v5 = 1LL;\n do {\n *((uint8_t *)&s2[40] + v5 + 1) = v4;\n v4 = v1[v5];\n v3 = v5++;\n } while ((v4 & 223) != 0);\n v2 = v3;\n } else {\n v2 = 0;\n v3 = 0LL;\n }\n s1[v2] = 0;\n v6 = 0LL;\n while (strcmp(s1, *(const char **)&s2[4 * v6])) {\n if (++v6 == 10) goto LABEL_5;\n }\n ++*((uint32_t *)v17 + (int)v6);\n LABEL_5:\n v1 += v3 + 1;\n } while (*(v1 - 1));\n }\n v7 = 0LL;\n v8 = 0;\n do {\n v13 = *((uint32_t *)v17 + v7);\n if (v13 > 0) {\n v14 = *(char **)&s2[4 * v7];\n v15 = *v14;\n for (i = 0; i != v13; ++i) {\n v10 = v8 + 1;\n v11 = v15;\n for (j = v8; v11; v11 = v14[v10 - v8 - 1]) {\n *((uint8_t *)&unk_403F + v10) = v11;\n j = v10++;\n }\n v8 = j + 1;\n *((uint8_t *)&unk_403F + j + 1) = 32;\n }\n }\n ++v7;\n } while (v7 != 10);\n if (v8 <= 0)\n out_1[0] = 0;\n else\n out_1[v8 - 1] = 0;\n return out_1;\n}" + }, + { + "index": "HumanEval-C-19", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "const char* func0(const char* numbers) {\n int count[10] = {0};\n const char* numto[10] = {\"zero\", \"one\", \"two\", \"three\", \"four\",\n \"five\", \"six\", \"seven\", \"eight\", \"nine\"};\n int index, i, j, k;\n static char out[1000];\n char current[6];\n index = 0;\n if (*numbers) {\n do {\n for (i = 0; numbers[i] != ' ' && numbers[i] != '\\0'; ++i) {\n current[i] = numbers[i];\n }\n current[i] = '\\0';\n for (j = 0; j < 10; ++j) {\n if (strcmp(current, numto[j]) == 0) {\n count[j]++;\n break;\n }\n }\n numbers += i + 1;\n } while (numbers[-1]);\n }\n for (i = 0; i < 10; ++i) {\n for (j = 0; j < count[i]; ++j) {\n for (k = 0; numto[i][k] != '\\0'; ++k, ++index) {\n out[index] = numto[i][k];\n }\n out[index++] = ' ';\n }\n }\n if (index > 0) {\n out[index - 1] = '\\0';\n } else {\n out[0] = '\\0';\n }\n return out;\n}", + "test": "#include \n#include \n\nint main() {\n assert(strcmp(func0(\"\"), \"\") == 0);\n assert(strcmp(func0(\"three\"), \"three\") == 0);\n assert(strcmp(func0(\"three five nine\"), \"three five nine\") == 0);\n assert(strcmp(func0(\"five zero four seven nine eight\"), \"zero four five seven eight nine\") == 0);\n assert(strcmp(func0(\"six five four three two one zero\"), \"zero one two three four five six\") == 0);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npxor xmm0, xmm0\npush r14\npush r13\npush r12\npush rbp\npush rbx\nlea rbx, aZero; \"zero\"\nsub rsp, 98h\nmov rax, fs:28h\nmov [rsp+0C8h+var_40], rax\nxor eax, eax\nlea rax, aOne; \"one\"\nmovaps [rsp+0C8h+var_C8], xmm0\nmovq xmm1, rax\nmovaps [rsp+0C8h+var_B8], xmm0\nmovq xmm0, rbx\nlea rax, s2; \"three\"\npunpcklqdq xmm0, xmm1\nlea rbx, aTwo; \"two\"\nmovq xmm2, rax\nmov [rsp+0C8h+var_A8], 0\nmovaps [rsp+0C8h+var_98], xmm0\nmovq xmm0, rbx\nlea rax, aFive; \"five\"\nlea rbx, aFour; \"four\"\npunpcklqdq xmm0, xmm2\nmovq xmm3, rax\nlea rax, aSeven; \"seven\"\nmovaps [rsp+0C8h+var_88], xmm0\nmovq xmm0, rbx\nmovq xmm4, rax\nlea rbx, aSix; \"six\"\npunpcklqdq xmm0, xmm3\nlea rax, aThreeFiveNine+0Bh; \"nine\"\nmovaps [rsp+0C8h+var_78], xmm0\nmovq xmm0, rbx\nmovq xmm5, rax\nlea rbx, aEight; \"eight\"\npunpcklqdq xmm0, xmm4\nmovzx eax, byte ptr [rdi]\nmovaps [rsp+0C8h+var_68], xmm0\nmovq xmm0, rbx\npunpcklqdq xmm0, xmm5\nmovaps [rsp+0C8h+var_58], xmm0\ntest al, al\njz loc_1451\nmov r12, rdi\nlea r15, [rsp+0C8h+var_98]\nlea r13, [rsp+0C8h+s1]\nmov ebx, 1\nlea r14, [rsp+0C8h+var_47]\ntest al, 0DFh\njz short loc_143B\nnop\nloc_13E0:\nmov [r14+rbx], al\nmovzx eax, byte ptr [r12+rbx]\nmov rdx, rbx\nadd rbx, 1\ntest al, 0DFh\njnz short loc_13E0\nloc_13F4:\nmovsxd rax, edx\nxor ebp, ebp\nmov [rsp+rax+0C8h+s1], 0\nnop dword ptr [rax+00000000h]\nloc_1408:\nmov rsi, [r15+rbp*8]; s2\nmov rdi, r13; s1\ncall _strcmp\ntest eax, eax\njz short loc_143F\nadd rbp, 1\ncmp rbp, 0Ah\njnz short loc_1408\nadd r12, rbx\ncmp byte ptr [r12-1], 0\njz short loc_1451\nloc_142D:\nmovzx eax, byte ptr [r12]\nmov ebx, 1\ntest al, 0DFh\njnz short loc_13E0\nloc_143B:\nxor edx, edx\njmp short loc_13F4\nloc_143F:\nmovsxd rbp, ebp\nadd r12, rbx\nadd dword ptr [rsp+rbp*4+0C8h+var_C8], 1\ncmp byte ptr [r12-1], 0\njnz short loc_142D\nloc_1451:\nlea rbx, out_1\nxor ebp, ebp\nxor esi, esi\nmov r12, rsp\nlea rdi, [rbx-1]\nnop dword ptr [rax+rax+00h]\nloc_1468:\nmov r10d, [r12+rbp*4]\ntest r10d, r10d\njle short loc_14C6\nmov r11, qword ptr [rsp+rbp*8+0C8h+var_98]\nxor r8d, r8d\nmovzx r9d, byte ptr [r11]\nnop dword ptr [rax]\nloc_1480:\nmov ecx, esi\ntest r9b, r9b\njz short loc_14B3\nlea eax, [rsi+1]\nmovsxd rcx, esi\nmov rsi, r11\nmov edx, r9d\ncdqe\nsub rsi, rcx\nnop dword ptr [rax+rax+00000000h]\nloc_14A0:\nmov [rdi+rax], dl\nmov rcx, rax\nadd rax, 1\nmovzx edx, byte ptr [rsi+rax-1]\ntest dl, dl\njnz short loc_14A0\nloc_14B3:\nlea esi, [rcx+1]\nadd r8d, 1\nmovsxd rcx, ecx\nmov byte ptr [rbx+rcx], 20h ; ' '\ncmp r8d, r10d\njnz short loc_1480\nloc_14C6:\nadd rbp, 1\ncmp rbp, 0Ah\njnz short loc_1468\ntest esi, esi\njle short loc_1505\nlea eax, [rsi-1]\ncdqe\nmov byte ptr [rbx+rax], 0\nloc_14DD:\nmov rax, [rsp+0C8h+var_40]\nsub rax, fs:28h\njnz short loc_150E\nadd rsp, 98h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1505:\nmov cs:out_1, 0\njmp short loc_14DD\nloc_150E:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(char *a1)\n{\n char v1; // al\n char *v2; // r12\n __int64 v3; // rbx\n int v4; // edx\n __int64 v5; // rbp\n __int64 v6; // rbp\n int v7; // esi\n int v8; // r10d\n char *v9; // r11\n int v10; // r8d\n char v11; // r9\n int v12; // ecx\n char v13; // dl\n __int64 v14; // rax\n char *v15; // rsi\n _OWORD v17[2]; // [rsp+0h] [rbp-C8h] BYREF\n __int64 v18; // [rsp+20h] [rbp-A8h]\n _WORD v19[41]; // [rsp+30h] [rbp-98h]\n char s1[6]; // [rsp+82h] [rbp-46h] BYREF\n unsigned __int64 v21; // [rsp+88h] [rbp-40h]\n\n v21 = __readfsqword(0x28u);\n memset(v17, 0, sizeof(v17));\n v18 = 0LL;\n *(__m128i *)v19 = _mm_unpacklo_epi64((__m128i)(unsigned __int64)\"zero\", (__m128i)(unsigned __int64)\"one\");\n *(__m128i *)&v19[8] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)\"two\", (__m128i)(unsigned __int64)\"three\");\n *(__m128i *)&v19[16] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)\"four\", (__m128i)(unsigned __int64)\"five\");\n v1 = *a1;\n *(__m128i *)&v19[24] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)\"six\", (__m128i)(unsigned __int64)\"seven\");\n *(__m128i *)&v19[32] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)\"eight\", (__m128i)(unsigned __int64)\"nine\");\n if ( v1 )\n {\n v2 = a1;\n v3 = 1LL;\n if ( (v1 & 0xDF) != 0 )\n {\n do\n {\nLABEL_3:\n *((_BYTE *)&v19[40] + v3 + 1) = v1;\n v1 = v2[v3];\n v4 = v3++;\n }\n while ( (v1 & 0xDF) != 0 );\n }\n else\n {\nLABEL_9:\n v4 = 0;\n }\n v5 = 0LL;\n s1[v4] = 0;\n while ( strcmp(s1, *(const char **)&v19[4 * v5]) )\n {\n if ( ++v5 == 10 )\n {\n v2 += v3;\n if ( !*(v2 - 1) )\n goto LABEL_11;\nLABEL_8:\n v1 = *v2;\n v3 = 1LL;\n if ( (*v2 & 0xDF) != 0 )\n goto LABEL_3;\n goto LABEL_9;\n }\n }\n v2 += v3;\n ++*((_DWORD *)v17 + (int)v5);\n if ( *(v2 - 1) )\n goto LABEL_8;\n }\nLABEL_11:\n v6 = 0LL;\n v7 = 0;\n do\n {\n v8 = *((_DWORD *)v17 + v6);\n if ( v8 > 0 )\n {\n v9 = *(char **)&v19[4 * v6];\n v10 = 0;\n v11 = *v9;\n do\n {\n v12 = v7;\n if ( v11 )\n {\n v13 = v11;\n v14 = v7 + 1;\n v15 = &v9[-v7];\n do\n {\n out_1[v14 - 1] = v13;\n v12 = v14++;\n v13 = v15[v14 - 1];\n }\n while ( v13 );\n }\n v7 = v12 + 1;\n ++v10;\n out_1[v12] = 32;\n }\n while ( v10 != v8 );\n }\n ++v6;\n }\n while ( v6 != 10 );\n if ( v7 <= 0 )\n out_1[0] = 0;\n else\n out_1[v7 - 1] = 0;\n return out_1;\n}", + "ida_strip_asm": "sub_12D0:\nendbr64\npush r15\npxor xmm0, xmm0\npush r14\npush r13\npush r12\npush rbp\npush rbx\nlea rbx, aZero; \"zero\"\nsub rsp, 98h\nmov rax, fs:28h\nmov [rsp+0C8h+var_40], rax\nxor eax, eax\nlea rax, aOne; \"one\"\nmovaps [rsp+0C8h+var_C8], xmm0\nmovq xmm1, rax\nmovaps [rsp+0C8h+var_B8], xmm0\nmovq xmm0, rbx\nlea rax, s2; \"three\"\npunpcklqdq xmm0, xmm1\nlea rbx, aTwo; \"two\"\nmovq xmm2, rax\nmov [rsp+0C8h+var_A8], 0\nmovaps [rsp+0C8h+var_98], xmm0\nmovq xmm0, rbx\nlea rax, aFive; \"five\"\nlea rbx, aFour; \"four\"\npunpcklqdq xmm0, xmm2\nmovq xmm3, rax\nlea rax, aSeven; \"seven\"\nmovaps [rsp+0C8h+var_88], xmm0\nmovq xmm0, rbx\nmovq xmm4, rax\nlea rbx, aSix; \"six\"\npunpcklqdq xmm0, xmm3\nlea rax, aThreeFiveNine+0Bh; \"nine\"\nmovaps [rsp+0C8h+var_78], xmm0\nmovq xmm0, rbx\nmovq xmm5, rax\nlea rbx, aEight; \"eight\"\npunpcklqdq xmm0, xmm4\nmovzx eax, byte ptr [rdi]\nmovaps [rsp+0C8h+var_68], xmm0\nmovq xmm0, rbx\npunpcklqdq xmm0, xmm5\nmovaps [rsp+0C8h+var_58], xmm0\ntest al, al\njz loc_1451\nmov r12, rdi\nlea r15, [rsp+0C8h+var_98]\nlea r13, [rsp+0C8h+s1]\nmov ebx, 1\nlea r14, [rsp+0C8h+var_47]\ntest al, 0DFh\njz short loc_143B\nnop\nloc_13E0:\nmov [r14+rbx], al\nmovzx eax, byte ptr [r12+rbx]\nmov rdx, rbx\nadd rbx, 1\ntest al, 0DFh\njnz short loc_13E0\nloc_13F4:\nmovsxd rax, edx\nxor ebp, ebp\nmov [rsp+rax+0C8h+s1], 0\nnop dword ptr [rax+00000000h]\nloc_1408:\nmov rsi, [r15+rbp*8]; s2\nmov rdi, r13; s1\ncall _strcmp\ntest eax, eax\njz short loc_143F\nadd rbp, 1\ncmp rbp, 0Ah\njnz short loc_1408\nadd r12, rbx\ncmp byte ptr [r12-1], 0\njz short loc_1451\nloc_142D:\nmovzx eax, byte ptr [r12]\nmov ebx, 1\ntest al, 0DFh\njnz short loc_13E0\nloc_143B:\nxor edx, edx\njmp short loc_13F4\nloc_143F:\nmovsxd rbp, ebp\nadd r12, rbx\nadd dword ptr [rsp+rbp*4+0C8h+var_C8], 1\ncmp byte ptr [r12-1], 0\njnz short loc_142D\nloc_1451:\nlea rbx, byte_4040\nxor ebp, ebp\nxor esi, esi\nmov r12, rsp\nlea rdi, [rbx-1]\nnop dword ptr [rax+rax+00h]\nloc_1468:\nmov r10d, [r12+rbp*4]\ntest r10d, r10d\njle short loc_14C6\nmov r11, qword ptr [rsp+rbp*8+0C8h+var_98]\nxor r8d, r8d\nmovzx r9d, byte ptr [r11]\nnop dword ptr [rax]\nloc_1480:\nmov ecx, esi\ntest r9b, r9b\njz short loc_14B3\nlea eax, [rsi+1]\nmovsxd rcx, esi\nmov rsi, r11\nmov edx, r9d\ncdqe\nsub rsi, rcx\nnop dword ptr [rax+rax+00000000h]\nloc_14A0:\nmov [rdi+rax], dl\nmov rcx, rax\nadd rax, 1\nmovzx edx, byte ptr [rsi+rax-1]\ntest dl, dl\njnz short loc_14A0\nloc_14B3:\nlea esi, [rcx+1]\nadd r8d, 1\nmovsxd rcx, ecx\nmov byte ptr [rbx+rcx], 20h ; ' '\ncmp r8d, r10d\njnz short loc_1480\nloc_14C6:\nadd rbp, 1\ncmp rbp, 0Ah\njnz short loc_1468\ntest esi, esi\njle short loc_1505\nlea eax, [rsi-1]\ncdqe\nmov byte ptr [rbx+rax], 0\nloc_14DD:\nmov rax, [rsp+0C8h+var_40]\nsub rax, fs:28h\njnz short loc_150E\nadd rsp, 98h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1505:\nmov cs:byte_4040, 0\njmp short loc_14DD\nloc_150E:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_12D0(char *a1)\n{\n char v1; // al\n char *v2; // r12\n __int64 v3; // rbx\n int v4; // edx\n __int64 v5; // rbp\n __int64 v6; // rbp\n int v7; // esi\n int v8; // r10d\n char *v9; // r11\n int v10; // r8d\n char v11; // r9\n int v12; // ecx\n char v13; // dl\n __int64 v14; // rax\n char *v15; // rsi\n _OWORD v17[2]; // [rsp+0h] [rbp-C8h] BYREF\n __int64 v18; // [rsp+20h] [rbp-A8h]\n _WORD v19[41]; // [rsp+30h] [rbp-98h]\n char s1[6]; // [rsp+82h] [rbp-46h] BYREF\n unsigned __int64 v21; // [rsp+88h] [rbp-40h]\n\n v21 = __readfsqword(0x28u);\n memset(v17, 0, sizeof(v17));\n v18 = 0LL;\n *(__m128i *)v19 = _mm_unpacklo_epi64((__m128i)(unsigned __int64)\"zero\", (__m128i)(unsigned __int64)\"one\");\n *(__m128i *)&v19[8] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)\"two\", (__m128i)(unsigned __int64)\"three\");\n *(__m128i *)&v19[16] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)\"four\", (__m128i)(unsigned __int64)\"five\");\n v1 = *a1;\n *(__m128i *)&v19[24] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)\"six\", (__m128i)(unsigned __int64)\"seven\");\n *(__m128i *)&v19[32] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)\"eight\", (__m128i)(unsigned __int64)\"nine\");\n if ( v1 )\n {\n v2 = a1;\n v3 = 1LL;\n if ( (v1 & 0xDF) != 0 )\n {\n do\n {\nLABEL_3:\n *((_BYTE *)&v19[40] + v3 + 1) = v1;\n v1 = v2[v3];\n v4 = v3++;\n }\n while ( (v1 & 0xDF) != 0 );\n }\n else\n {\nLABEL_9:\n v4 = 0;\n }\n v5 = 0LL;\n s1[v4] = 0;\n while ( strcmp(s1, *(const char **)&v19[4 * v5]) )\n {\n if ( ++v5 == 10 )\n {\n v2 += v3;\n if ( !*(v2 - 1) )\n goto LABEL_11;\nLABEL_8:\n v1 = *v2;\n v3 = 1LL;\n if ( (*v2 & 0xDF) != 0 )\n goto LABEL_3;\n goto LABEL_9;\n }\n }\n v2 += v3;\n ++*((_DWORD *)v17 + (int)v5);\n if ( *(v2 - 1) )\n goto LABEL_8;\n }\nLABEL_11:\n v6 = 0LL;\n v7 = 0;\n do\n {\n v8 = *((_DWORD *)v17 + v6);\n if ( v8 > 0 )\n {\n v9 = *(char **)&v19[4 * v6];\n v10 = 0;\n v11 = *v9;\n do\n {\n v12 = v7;\n if ( v11 )\n {\n v13 = v11;\n v14 = v7 + 1;\n v15 = &v9[-v7];\n do\n {\n byte_4040[v14 - 1] = v13;\n v12 = v14++;\n v13 = v15[v14 - 1];\n }\n while ( v13 );\n }\n v7 = v12 + 1;\n ++v10;\n byte_4040[v12] = 32;\n }\n while ( v10 != v8 );\n }\n ++v6;\n }\n while ( v6 != 10 );\n if ( v7 <= 0 )\n byte_4040[0] = 0;\n else\n byte_4040[v7 - 1] = 0;\n return byte_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_12D0(char *a1) {\n char v1;\n char *v2;\n long long v3;\n int v4;\n long long v5;\n long long v6;\n int v7;\n int v8;\n char *v9;\n int v10;\n char v11;\n int v12;\n char v13;\n long long v14;\n char *v15;\n long double v17[2];\n long long v18;\n unsigned short v19[41];\n char s1[6];\n unsigned long long v21;\n v21 = __readfsqword(40u);\n memset(v17, 0, sizeof(v17));\n v18 = 0LL;\n *(__m128i *)v19 = _mm_unpacklo_epi64((__m128i)(unsigned long long)\"zero\",\n (__m128i)(unsigned long long)\"one\");\n *(__m128i *)&v19[8] = _mm_unpacklo_epi64(\n (__m128i)(unsigned long long)\"two\", (__m128i)(unsigned long long)\"three\");\n *(__m128i *)&v19[16] = _mm_unpacklo_epi64(\n (__m128i)(unsigned long long)\"four\", (__m128i)(unsigned long long)\"five\");\n v1 = *a1;\n *(__m128i *)&v19[24] = _mm_unpacklo_epi64(\n (__m128i)(unsigned long long)\"six\", (__m128i)(unsigned long long)\"seven\");\n *(__m128i *)&v19[32] =\n _mm_unpacklo_epi64((__m128i)(unsigned long long)\"eight\",\n (__m128i)(unsigned long long)\"nine\");\n if (v1) {\n v2 = a1;\n v3 = 1LL;\n if ((v1 & 223) != 0) {\n do {\n LABEL_3:\n *((uint8_t *)&v19[40] + v3 + 1) = v1;\n v1 = v2[v3];\n v4 = v3++;\n } while ((v1 & 223) != 0);\n } else {\n LABEL_9:\n v4 = 0;\n }\n v5 = 0LL;\n s1[v4] = 0;\n while (strcmp(s1, *(const char **)&v19[4 * v5])) {\n if (++v5 == 10) {\n v2 += v3;\n if (!*(v2 - 1)) goto LABEL_11;\n LABEL_8:\n v1 = *v2;\n v3 = 1LL;\n if ((*v2 & 223) != 0) goto LABEL_3;\n goto LABEL_9;\n }\n }\n v2 += v3;\n ++*((uint32_t *)v17 + (int)v5);\n if (*(v2 - 1)) goto LABEL_8;\n }\nLABEL_11:\n v6 = 0LL;\n v7 = 0;\n do {\n v8 = *((uint32_t *)v17 + v6);\n if (v8 > 0) {\n v9 = *(char **)&v19[4 * v6];\n v10 = 0;\n v11 = *v9;\n do {\n v12 = v7;\n if (v11) {\n v13 = v11;\n v14 = v7 + 1;\n v15 = &v9[-v7];\n do {\n byte_4040[v14 - 1] = v13;\n v12 = v14++;\n v13 = v15[v14 - 1];\n } while (v13);\n }\n v7 = v12 + 1;\n ++v10;\n byte_4040[v12] = 32;\n } while (v10 != v8);\n }\n ++v6;\n } while (v6 != 10);\n if (v7 <= 0)\n byte_4040[0] = 0;\n else\n byte_4040[v7 - 1] = 0;\n return byte_4040;\n}", + "ida_pseudo_norm": "char *func0(char *a1) {\n char v1;\n char *v2;\n long long v3;\n int v4;\n long long v5;\n long long v6;\n int v7;\n int v8;\n char *v9;\n int v10;\n char v11;\n int v12;\n char v13;\n long long v14;\n char *v15;\n long double v17[2];\n long long v18;\n unsigned short v19[41];\n char s1[6];\n unsigned long long v21;\n v21 = __readfsqword(40u);\n memset(v17, 0, sizeof(v17));\n v18 = 0LL;\n *(__m128i *)v19 = _mm_unpacklo_epi64((__m128i)(unsigned long long)\"zero\",\n (__m128i)(unsigned long long)\"one\");\n *(__m128i *)&v19[8] = _mm_unpacklo_epi64(\n (__m128i)(unsigned long long)\"two\", (__m128i)(unsigned long long)\"three\");\n *(__m128i *)&v19[16] = _mm_unpacklo_epi64(\n (__m128i)(unsigned long long)\"four\", (__m128i)(unsigned long long)\"five\");\n v1 = *a1;\n *(__m128i *)&v19[24] = _mm_unpacklo_epi64(\n (__m128i)(unsigned long long)\"six\", (__m128i)(unsigned long long)\"seven\");\n *(__m128i *)&v19[32] =\n _mm_unpacklo_epi64((__m128i)(unsigned long long)\"eight\",\n (__m128i)(unsigned long long)\"nine\");\n if (v1) {\n v2 = a1;\n v3 = 1LL;\n if ((v1 & 223) != 0) {\n do {\n LABEL_3:\n *((uint8_t *)&v19[40] + v3 + 1) = v1;\n v1 = v2[v3];\n v4 = v3++;\n } while ((v1 & 223) != 0);\n } else {\n LABEL_9:\n v4 = 0;\n }\n v5 = 0LL;\n s1[v4] = 0;\n while (strcmp(s1, *(const char **)&v19[4 * v5])) {\n if (++v5 == 10) {\n v2 += v3;\n if (!*(v2 - 1)) goto LABEL_11;\n LABEL_8:\n v1 = *v2;\n v3 = 1LL;\n if ((*v2 & 223) != 0) goto LABEL_3;\n goto LABEL_9;\n }\n }\n v2 += v3;\n ++*((uint32_t *)v17 + (int)v5);\n if (*(v2 - 1)) goto LABEL_8;\n }\nLABEL_11:\n v6 = 0LL;\n v7 = 0;\n do {\n v8 = *((uint32_t *)v17 + v6);\n if (v8 > 0) {\n v9 = *(char **)&v19[4 * v6];\n v10 = 0;\n v11 = *v9;\n do {\n v12 = v7;\n if (v11) {\n v13 = v11;\n v14 = v7 + 1;\n v15 = &v9[-v7];\n do {\n out_1[v14 - 1] = v13;\n v12 = v14++;\n v13 = v15[v14 - 1];\n } while (v13);\n }\n v7 = v12 + 1;\n ++v10;\n out_1[v12] = 32;\n } while (v10 != v8);\n }\n ++v6;\n } while (v6 != 10);\n if (v7 <= 0)\n out_1[0] = 0;\n else\n out_1[v7 - 1] = 0;\n return out_1;\n}" + }, + { + "index": "HumanEval-C-19", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "const char* func0(const char* numbers) {\n int count[10] = {0};\n const char* numto[10] = {\"zero\", \"one\", \"two\", \"three\", \"four\",\n \"five\", \"six\", \"seven\", \"eight\", \"nine\"};\n int index, i, j, k;\n static char out[1000];\n char current[6];\n index = 0;\n if (*numbers) {\n do {\n for (i = 0; numbers[i] != ' ' && numbers[i] != '\\0'; ++i) {\n current[i] = numbers[i];\n }\n current[i] = '\\0';\n for (j = 0; j < 10; ++j) {\n if (strcmp(current, numto[j]) == 0) {\n count[j]++;\n break;\n }\n }\n numbers += i + 1;\n } while (numbers[-1]);\n }\n for (i = 0; i < 10; ++i) {\n for (j = 0; j < count[i]; ++j) {\n for (k = 0; numto[i][k] != '\\0'; ++k, ++index) {\n out[index] = numto[i][k];\n }\n out[index++] = ' ';\n }\n }\n if (index > 0) {\n out[index - 1] = '\\0';\n } else {\n out[0] = '\\0';\n }\n return out;\n}", + "test": "#include \n#include \n\nint main() {\n assert(strcmp(func0(\"\"), \"\") == 0);\n assert(strcmp(func0(\"three\"), \"three\") == 0);\n assert(strcmp(func0(\"three five nine\"), \"three five nine\") == 0);\n assert(strcmp(func0(\"five zero four seven nine eight\"), \"zero four five seven eight nine\") == 0);\n assert(strcmp(func0(\"six five four three two one zero\"), \"zero one two three four five six\") == 0);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npxor xmm0, xmm0\nlea r15, aSix; \"six\"\npush r14\nlea r14, aTwo; \"two\"\npush r13\nlea r13, aZero; \"zero\"\npush r12\npush rbp\npush rbx\nsub rsp, 98h\nmov rax, fs:28h\nmov [rsp+0C8h+var_40], rax\nxor eax, eax\nmovaps [rsp+0C8h+var_C8], xmm0\nmovzx eax, byte ptr [rdi]\nmovaps [rsp+0C8h+var_B8], xmm0\nmovq xmm0, r13\nmov [rsp+0C8h+var_A8], 0\nmovhps xmm0, cs:off_3D80; \"one\"\nmovaps [rsp+0C8h+var_98], xmm0\nmovq xmm0, r14\nmovhps xmm0, cs:off_3D88; \"three\"\nmovaps [rsp+0C8h+var_88], xmm0\nmovq xmm0, cs:off_3D90; \"four\"\nmovhps xmm0, cs:off_3D98; \"five\"\nmovaps [rsp+0C8h+var_78], xmm0\nmovq xmm0, r15\nmovhps xmm0, cs:off_3DA0; \"seven\"\nmovaps [rsp+0C8h+var_68], xmm0\nmovq xmm0, cs:off_3DA8; \"eight\"\nmovhps xmm0, cs:off_3DB0; \"nine\"\nmovaps [rsp+0C8h+var_58], xmm0\ntest al, al\njz loc_1526\nmov rbp, rdi\nlea rbx, [rsp+0C8h+s1]\njmp loc_14FD\nloc_1399:\nmov [rsp+0C8h+s1], al\nmovzx eax, byte ptr [rbp+1]\ntest al, 0DFh\njz loc_15D9\nmov [rsp+0C8h+var_45], al\nmovzx eax, byte ptr [rbp+2]\ntest al, 0DFh\njz loc_15E9\nmov [rsp+0C8h+var_44], al\nmovzx eax, byte ptr [rbp+3]\ntest al, 0DFh\njz loc_1602\nmov [rsp+0C8h+var_43], al\nmovzx eax, byte ptr [rbp+4]\ntest al, 0DFh\njz loc_1612\nmov [rsp+0C8h+var_42], al\nmovzx eax, byte ptr [rbp+5]\ntest al, 0DFh\njz loc_1622\nmov [rsp+0C8h+var_41], al\nmov r12d, 6\nmov eax, 6\nloc_140A:\nadd r12, 1\nloc_140E:\nmov rsi, r13; s2\nmov rdi, rbx; s1\nmov [rsp+rax+0C8h+s1], 0\ncall _strcmp\ntest eax, eax\njz loc_1517\nlea rsi, aOne; \"one\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz loc_1512\nmov rsi, r14; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz loc_1642\nlea rsi, s2; \"three\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz loc_1632\nlea rsi, aFour; \"four\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz loc_1662\nlea rsi, aFive; \"five\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz loc_1652\nmov rsi, r15; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz loc_1682\nlea rsi, aSeven; \"seven\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz loc_1692\nlea rsi, aEight; \"eight\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz loc_16A2\nlea rsi, aThreeFiveNine+0Bh; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz loc_1672\nadd rbp, r12\ncmp byte ptr [rbp-1], 0\njz short loc_1526\nloc_14F9:\nmovzx eax, byte ptr [rbp+0]\nloc_14FD:\ntest al, 0DFh\njnz loc_1399\nmov r12d, 1\nxor eax, eax\njmp loc_140E\nloc_1512:\nmov eax, 1\nloc_1517:\ncdqe\nadd dword ptr [rsp+rax*4+0C8h+var_C8], 1\nloc_151D:\nadd rbp, r12\ncmp byte ptr [rbp-1], 0\njnz short loc_14F9\nloc_1526:\nlea rbx, out_1\nxor ebp, ebp\nxor esi, esi\nmov r12, rsp\nlea rdi, [rbx-1]\nnop dword ptr [rax+rax+00000000h]\nloc_1540:\nmov r10d, [r12+rbp*4]\ntest r10d, r10d\njle short loc_1596\nmov r11, qword ptr [rsp+rbp*8+0C8h+var_98]\nxor r8d, r8d\nmovzx r9d, byte ptr [r11]\nnop dword ptr [rax]\nloc_1558:\nmov ecx, esi\ntest r9b, r9b\njz short loc_1583\nlea eax, [rsi+1]\nmovsxd rcx, esi\nmov rsi, r11\nmov edx, r9d\ncdqe\nsub rsi, rcx\nloc_1570:\nmov [rdi+rax], dl\nmov rcx, rax\nadd rax, 1\nmovzx edx, byte ptr [rsi+rax-1]\ntest dl, dl\njnz short loc_1570\nloc_1583:\nlea esi, [rcx+1]\nadd r8d, 1\nmovsxd rcx, ecx\nmov byte ptr [rbx+rcx], 20h ; ' '\ncmp r8d, r10d\njnz short loc_1558\nloc_1596:\nadd rbp, 1\ncmp rbp, 0Ah\njnz short loc_1540\ntest esi, esi\njle short loc_15F9\nlea eax, [rsi-1]\ncdqe\nmov byte ptr [rbx+rax], 0\nloc_15AD:\nmov rax, [rsp+0C8h+var_40]\nsub rax, fs:28h\njnz loc_16B2\nadd rsp, 98h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15D9:\nmov eax, 1\nmov r12d, 1\njmp loc_140A\nloc_15E9:\nmov eax, 2\nmov r12d, 2\njmp loc_140A\nloc_15F9:\nmov cs:out_1, 0\njmp short loc_15AD\nloc_1602:\nmov eax, 3\nmov r12d, 3\njmp loc_140A\nloc_1612:\nmov eax, 4\nmov r12d, 4\njmp loc_140A\nloc_1622:\nmov eax, 5\nmov r12d, 5\njmp loc_140A\nloc_1632:\nmov eax, 3\ncdqe\nadd dword ptr [rsp+rax*4+0C8h+var_C8], 1\njmp loc_151D\nloc_1642:\nmov eax, 2\ncdqe\nadd dword ptr [rsp+rax*4+0C8h+var_C8], 1\njmp loc_151D\nloc_1652:\nmov eax, 5\ncdqe\nadd dword ptr [rsp+rax*4+0C8h+var_C8], 1\njmp loc_151D\nloc_1662:\nmov eax, 4\ncdqe\nadd dword ptr [rsp+rax*4+0C8h+var_C8], 1\njmp loc_151D\nloc_1672:\nmov eax, 9\ncdqe\nadd dword ptr [rsp+rax*4+0C8h+var_C8], 1\njmp loc_151D\nloc_1682:\nmov eax, 6\ncdqe\nadd dword ptr [rsp+rax*4+0C8h+var_C8], 1\njmp loc_151D\nloc_1692:\nmov eax, 7\ncdqe\nadd dword ptr [rsp+rax*4+0C8h+var_C8], 1\njmp loc_151D\nloc_16A2:\nmov eax, 8\ncdqe\nadd dword ptr [rsp+rax*4+0C8h+var_C8], 1\njmp loc_151D\nloc_16B2:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(char *a1)\n{\n char v1; // al\n char *i; // rbp\n __int64 v3; // r12\n __int64 v4; // rax\n __int64 v5; // r12\n int v6; // eax\n __int64 v7; // rbp\n int v8; // esi\n int v9; // r10d\n char *v10; // r11\n int v11; // r8d\n char v12; // r9\n int v13; // ecx\n char v14; // dl\n __int64 v15; // rax\n char *v16; // rsi\n __int128 v18; // [rsp+0h] [rbp-C8h]\n __int128 v19; // [rsp+10h] [rbp-B8h]\n __int64 v20; // [rsp+20h] [rbp-A8h]\n _OWORD v21[5]; // [rsp+30h] [rbp-98h]\n char s1[6]; // [rsp+82h] [rbp-46h] BYREF\n unsigned __int64 v23; // [rsp+88h] [rbp-40h]\n\n v23 = __readfsqword(0x28u);\n v18 = 0LL;\n v1 = *a1;\n v19 = 0LL;\n v20 = 0LL;\n v21[0] = _mm_loadh_ps((const double *)off_3D80);\n v21[1] = _mm_loadh_ps((const double *)off_3D88);\n v21[2] = _mm_loadh_ps((const double *)off_3D98);\n v21[3] = _mm_loadh_ps((const double *)off_3DA0);\n v21[4] = _mm_loadh_ps((const double *)&off_3DB0);\n if ( v1 )\n {\n for ( i = a1; ; v1 = *i )\n {\n if ( (v1 & 0xDF) != 0 )\n {\n s1[0] = v1;\n if ( (i[1] & 0xDF) != 0 )\n {\n s1[1] = i[1];\n if ( (i[2] & 0xDF) != 0 )\n {\n s1[2] = i[2];\n if ( (i[3] & 0xDF) != 0 )\n {\n s1[3] = i[3];\n if ( (i[4] & 0xDF) != 0 )\n {\n s1[4] = i[4];\n if ( (i[5] & 0xDF) != 0 )\n {\n s1[5] = i[5];\n v3 = 6LL;\n v4 = 6LL;\n }\n else\n {\n v4 = 5LL;\n v3 = 5LL;\n }\n }\n else\n {\n v4 = 4LL;\n v3 = 4LL;\n }\n }\n else\n {\n v4 = 3LL;\n v3 = 3LL;\n }\n }\n else\n {\n v4 = 2LL;\n v3 = 2LL;\n }\n }\n else\n {\n v4 = 1LL;\n v3 = 1LL;\n }\n v5 = v3 + 1;\n }\n else\n {\n v5 = 1LL;\n v4 = 0LL;\n }\n s1[v4] = 0;\n v6 = strcmp(s1, \"zero\");\n if ( !v6 )\n goto LABEL_25;\n if ( !strcmp(s1, \"one\") )\n break;\n if ( !strcmp(s1, \"two\") )\n {\n ++DWORD2(v18);\n }\n else if ( !strcmp(s1, \"three\") )\n {\n ++HIDWORD(v18);\n }\n else if ( !strcmp(s1, \"four\") )\n {\n LODWORD(v19) = v19 + 1;\n }\n else if ( !strcmp(s1, \"five\") )\n {\n ++DWORD1(v19);\n }\n else if ( !strcmp(s1, \"six\") )\n {\n ++DWORD2(v19);\n }\n else if ( !strcmp(s1, \"seven\") )\n {\n ++HIDWORD(v19);\n }\n else if ( !strcmp(s1, \"eight\") )\n {\n LODWORD(v20) = v20 + 1;\n }\n else\n {\n if ( strcmp(s1, \"nine\") )\n {\n i += v5;\n if ( !*(i - 1) )\n goto LABEL_27;\n continue;\n }\n ++HIDWORD(v20);\n }\nLABEL_26:\n i += v5;\n if ( !*(i - 1) )\n goto LABEL_27;\n }\n v6 = 1;\nLABEL_25:\n ++*((_DWORD *)&v18 + v6);\n goto LABEL_26;\n }\nLABEL_27:\n v7 = 0LL;\n v8 = 0;\n do\n {\n v9 = *((_DWORD *)&v18 + v7);\n if ( v9 > 0 )\n {\n v10 = (char *)*((_QWORD *)v21 + v7);\n v11 = 0;\n v12 = *v10;\n do\n {\n v13 = v8;\n if ( v12 )\n {\n v14 = v12;\n v15 = v8 + 1;\n v16 = &v10[-v8];\n do\n {\n out_1[v15 - 1] = v14;\n v13 = v15++;\n v14 = v16[v15 - 1];\n }\n while ( v14 );\n }\n v8 = v13 + 1;\n ++v11;\n out_1[v13] = 32;\n }\n while ( v11 != v9 );\n }\n ++v7;\n }\n while ( v7 != 10 );\n if ( v8 <= 0 )\n out_1[0] = 0;\n else\n out_1[v8 - 1] = 0;\n return out_1;\n}", + "ida_strip_asm": "sub_12D0:\nendbr64\npush r15\npxor xmm0, xmm0\nlea r15, aSix; \"six\"\npush r14\nlea r14, aTwo; \"two\"\npush r13\nlea r13, aZero; \"zero\"\npush r12\npush rbp\npush rbx\nsub rsp, 98h\nmov rax, fs:28h\nmov [rsp+0C8h+var_40], rax\nxor eax, eax\nmovaps [rsp+0C8h+var_C8], xmm0\nmovzx eax, byte ptr [rdi]\nmovaps [rsp+0C8h+var_B8], xmm0\nmovq xmm0, r13\nmov [rsp+0C8h+var_A8], 0\nmovhps xmm0, cs:off_3D80; \"one\"\nmovaps [rsp+0C8h+var_98], xmm0\nmovq xmm0, r14\nmovhps xmm0, cs:off_3D88; \"three\"\nmovaps [rsp+0C8h+var_88], xmm0\nmovq xmm0, cs:off_3D90; \"four\"\nmovhps xmm0, cs:off_3D98; \"five\"\nmovaps [rsp+0C8h+var_78], xmm0\nmovq xmm0, r15\nmovhps xmm0, cs:off_3DA0; \"seven\"\nmovaps [rsp+0C8h+var_68], xmm0\nmovq xmm0, cs:off_3DA8; \"eight\"\nmovhps xmm0, cs:off_3DB0; \"nine\"\nmovaps [rsp+0C8h+var_58], xmm0\ntest al, al\njz loc_1526\nmov rbp, rdi\nlea rbx, [rsp+0C8h+s1]\njmp loc_14FD\nloc_1399:\nmov [rsp+0C8h+s1], al\nmovzx eax, byte ptr [rbp+1]\ntest al, 0DFh\njz loc_15D9\nmov [rsp+0C8h+var_45], al\nmovzx eax, byte ptr [rbp+2]\ntest al, 0DFh\njz loc_15E9\nmov [rsp+0C8h+var_44], al\nmovzx eax, byte ptr [rbp+3]\ntest al, 0DFh\njz loc_1602\nmov [rsp+0C8h+var_43], al\nmovzx eax, byte ptr [rbp+4]\ntest al, 0DFh\njz loc_1612\nmov [rsp+0C8h+var_42], al\nmovzx eax, byte ptr [rbp+5]\ntest al, 0DFh\njz loc_1622\nmov [rsp+0C8h+var_41], al\nmov r12d, 6\nmov eax, 6\nloc_140A:\nadd r12, 1\nloc_140E:\nmov rsi, r13; s2\nmov rdi, rbx; s1\nmov [rsp+rax+0C8h+s1], 0\ncall _strcmp\ntest eax, eax\njz loc_1517\nlea rsi, aOne; \"one\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz loc_1512\nmov rsi, r14; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz loc_1642\nlea rsi, s2; \"three\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz loc_1632\nlea rsi, aFour; \"four\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz loc_1662\nlea rsi, aFive; \"five\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz loc_1652\nmov rsi, r15; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz loc_1682\nlea rsi, aSeven; \"seven\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz loc_1692\nlea rsi, aEight; \"eight\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz loc_16A2\nlea rsi, aThreeFiveNine+0Bh; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz loc_1672\nadd rbp, r12\ncmp byte ptr [rbp-1], 0\njz short loc_1526\nloc_14F9:\nmovzx eax, byte ptr [rbp+0]\nloc_14FD:\ntest al, 0DFh\njnz loc_1399\nmov r12d, 1\nxor eax, eax\njmp loc_140E\nloc_1512:\nmov eax, 1\nloc_1517:\ncdqe\nadd dword ptr [rsp+rax*4+0C8h+var_C8], 1\nloc_151D:\nadd rbp, r12\ncmp byte ptr [rbp-1], 0\njnz short loc_14F9\nloc_1526:\nlea rbx, byte_4040\nxor ebp, ebp\nxor esi, esi\nmov r12, rsp\nlea rdi, [rbx-1]\nnop dword ptr [rax+rax+00000000h]\nloc_1540:\nmov r10d, [r12+rbp*4]\ntest r10d, r10d\njle short loc_1596\nmov r11, qword ptr [rsp+rbp*8+0C8h+var_98]\nxor r8d, r8d\nmovzx r9d, byte ptr [r11]\nnop dword ptr [rax]\nloc_1558:\nmov ecx, esi\ntest r9b, r9b\njz short loc_1583\nlea eax, [rsi+1]\nmovsxd rcx, esi\nmov rsi, r11\nmov edx, r9d\ncdqe\nsub rsi, rcx\nloc_1570:\nmov [rdi+rax], dl\nmov rcx, rax\nadd rax, 1\nmovzx edx, byte ptr [rsi+rax-1]\ntest dl, dl\njnz short loc_1570\nloc_1583:\nlea esi, [rcx+1]\nadd r8d, 1\nmovsxd rcx, ecx\nmov byte ptr [rbx+rcx], 20h ; ' '\ncmp r8d, r10d\njnz short loc_1558\nloc_1596:\nadd rbp, 1\ncmp rbp, 0Ah\njnz short loc_1540\ntest esi, esi\njle short loc_15F9\nlea eax, [rsi-1]\ncdqe\nmov byte ptr [rbx+rax], 0\nloc_15AD:\nmov rax, [rsp+0C8h+var_40]\nsub rax, fs:28h\njnz loc_16B2\nadd rsp, 98h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15D9:\nmov eax, 1\nmov r12d, 1\njmp loc_140A\nloc_15E9:\nmov eax, 2\nmov r12d, 2\njmp loc_140A\nloc_15F9:\nmov cs:byte_4040, 0\njmp short loc_15AD\nloc_1602:\nmov eax, 3\nmov r12d, 3\njmp loc_140A\nloc_1612:\nmov eax, 4\nmov r12d, 4\njmp loc_140A\nloc_1622:\nmov eax, 5\nmov r12d, 5\njmp loc_140A\nloc_1632:\nmov eax, 3\ncdqe\nadd dword ptr [rsp+rax*4+0C8h+var_C8], 1\njmp loc_151D\nloc_1642:\nmov eax, 2\ncdqe\nadd dword ptr [rsp+rax*4+0C8h+var_C8], 1\njmp loc_151D\nloc_1652:\nmov eax, 5\ncdqe\nadd dword ptr [rsp+rax*4+0C8h+var_C8], 1\njmp loc_151D\nloc_1662:\nmov eax, 4\ncdqe\nadd dword ptr [rsp+rax*4+0C8h+var_C8], 1\njmp loc_151D\nloc_1672:\nmov eax, 9\ncdqe\nadd dword ptr [rsp+rax*4+0C8h+var_C8], 1\njmp loc_151D\nloc_1682:\nmov eax, 6\ncdqe\nadd dword ptr [rsp+rax*4+0C8h+var_C8], 1\njmp loc_151D\nloc_1692:\nmov eax, 7\ncdqe\nadd dword ptr [rsp+rax*4+0C8h+var_C8], 1\njmp loc_151D\nloc_16A2:\nmov eax, 8\ncdqe\nadd dword ptr [rsp+rax*4+0C8h+var_C8], 1\njmp loc_151D\nloc_16B2:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_12D0(char *a1)\n{\n char v1; // al\n char *i; // rbp\n __int64 v3; // r12\n __int64 v4; // rax\n __int64 v5; // r12\n int v6; // eax\n __int64 v7; // rbp\n int v8; // esi\n int v9; // r10d\n char *v10; // r11\n int v11; // r8d\n char v12; // r9\n int v13; // ecx\n char v14; // dl\n __int64 v15; // rax\n char *v16; // rsi\n __int128 v18; // [rsp+0h] [rbp-C8h]\n __int128 v19; // [rsp+10h] [rbp-B8h]\n __int64 v20; // [rsp+20h] [rbp-A8h]\n _OWORD v21[5]; // [rsp+30h] [rbp-98h]\n char s1[6]; // [rsp+82h] [rbp-46h] BYREF\n unsigned __int64 v23; // [rsp+88h] [rbp-40h]\n\n v23 = __readfsqword(0x28u);\n v18 = 0LL;\n v1 = *a1;\n v19 = 0LL;\n v20 = 0LL;\n v21[0] = _mm_loadh_ps((const double *)off_3D80);\n v21[1] = _mm_loadh_ps((const double *)off_3D88);\n v21[2] = _mm_loadh_ps((const double *)off_3D98);\n v21[3] = _mm_loadh_ps((const double *)off_3DA0);\n v21[4] = _mm_loadh_ps((const double *)&off_3DB0);\n if ( v1 )\n {\n for ( i = a1; ; v1 = *i )\n {\n if ( (v1 & 0xDF) != 0 )\n {\n s1[0] = v1;\n if ( (i[1] & 0xDF) != 0 )\n {\n s1[1] = i[1];\n if ( (i[2] & 0xDF) != 0 )\n {\n s1[2] = i[2];\n if ( (i[3] & 0xDF) != 0 )\n {\n s1[3] = i[3];\n if ( (i[4] & 0xDF) != 0 )\n {\n s1[4] = i[4];\n if ( (i[5] & 0xDF) != 0 )\n {\n s1[5] = i[5];\n v3 = 6LL;\n v4 = 6LL;\n }\n else\n {\n v4 = 5LL;\n v3 = 5LL;\n }\n }\n else\n {\n v4 = 4LL;\n v3 = 4LL;\n }\n }\n else\n {\n v4 = 3LL;\n v3 = 3LL;\n }\n }\n else\n {\n v4 = 2LL;\n v3 = 2LL;\n }\n }\n else\n {\n v4 = 1LL;\n v3 = 1LL;\n }\n v5 = v3 + 1;\n }\n else\n {\n v5 = 1LL;\n v4 = 0LL;\n }\n s1[v4] = 0;\n v6 = strcmp(s1, \"zero\");\n if ( !v6 )\n goto LABEL_25;\n if ( !strcmp(s1, \"one\") )\n break;\n if ( !strcmp(s1, \"two\") )\n {\n ++DWORD2(v18);\n }\n else if ( !strcmp(s1, \"three\") )\n {\n ++HIDWORD(v18);\n }\n else if ( !strcmp(s1, \"four\") )\n {\n LODWORD(v19) = v19 + 1;\n }\n else if ( !strcmp(s1, \"five\") )\n {\n ++DWORD1(v19);\n }\n else if ( !strcmp(s1, \"six\") )\n {\n ++DWORD2(v19);\n }\n else if ( !strcmp(s1, \"seven\") )\n {\n ++HIDWORD(v19);\n }\n else if ( !strcmp(s1, \"eight\") )\n {\n LODWORD(v20) = v20 + 1;\n }\n else\n {\n if ( strcmp(s1, \"nine\") )\n {\n i += v5;\n if ( !*(i - 1) )\n goto LABEL_27;\n continue;\n }\n ++HIDWORD(v20);\n }\nLABEL_26:\n i += v5;\n if ( !*(i - 1) )\n goto LABEL_27;\n }\n v6 = 1;\nLABEL_25:\n ++*((_DWORD *)&v18 + v6);\n goto LABEL_26;\n }\nLABEL_27:\n v7 = 0LL;\n v8 = 0;\n do\n {\n v9 = *((_DWORD *)&v18 + v7);\n if ( v9 > 0 )\n {\n v10 = (char *)*((_QWORD *)v21 + v7);\n v11 = 0;\n v12 = *v10;\n do\n {\n v13 = v8;\n if ( v12 )\n {\n v14 = v12;\n v15 = v8 + 1;\n v16 = &v10[-v8];\n do\n {\n byte_4040[v15 - 1] = v14;\n v13 = v15++;\n v14 = v16[v15 - 1];\n }\n while ( v14 );\n }\n v8 = v13 + 1;\n ++v11;\n byte_4040[v13] = 32;\n }\n while ( v11 != v9 );\n }\n ++v7;\n }\n while ( v7 != 10 );\n if ( v8 <= 0 )\n byte_4040[0] = 0;\n else\n byte_4040[v8 - 1] = 0;\n return byte_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_12D0(char *a1) {\n char v1;\n char *i;\n long long v3;\n long long v4;\n long long v5;\n int v6;\n long long v7;\n int v8;\n int v9;\n char *v10;\n int v11;\n char v12;\n int v13;\n char v14;\n long long v15;\n char *v16;\n __int128 v18;\n __int128 v19;\n long long v20;\n long double v21[5];\n char s1[6];\n unsigned long long v23;\n v23 = __readfsqword(40u);\n v18 = 0LL;\n v1 = *a1;\n v19 = 0LL;\n v20 = 0LL;\n v21[0] = _mm_loadh_ps((const double *)off_3D80);\n v21[1] = _mm_loadh_ps((const double *)off_3D88);\n v21[2] = _mm_loadh_ps((const double *)off_3D98);\n v21[3] = _mm_loadh_ps((const double *)off_3DA0);\n v21[4] = _mm_loadh_ps((const double *)&off_3DB0);\n if (v1) {\n for (i = a1;; v1 = *i) {\n if ((v1 & 223) != 0) {\n s1[0] = v1;\n if ((i[1] & 223) != 0) {\n s1[1] = i[1];\n if ((i[2] & 223) != 0) {\n s1[2] = i[2];\n if ((i[3] & 223) != 0) {\n s1[3] = i[3];\n if ((i[4] & 223) != 0) {\n s1[4] = i[4];\n if ((i[5] & 223) != 0) {\n s1[5] = i[5];\n v3 = 6LL;\n v4 = 6LL;\n } else {\n v4 = 5LL;\n v3 = 5LL;\n }\n } else {\n v4 = 4LL;\n v3 = 4LL;\n }\n } else {\n v4 = 3LL;\n v3 = 3LL;\n }\n } else {\n v4 = 2LL;\n v3 = 2LL;\n }\n } else {\n v4 = 1LL;\n v3 = 1LL;\n }\n v5 = v3 + 1;\n } else {\n v5 = 1LL;\n v4 = 0LL;\n }\n s1[v4] = 0;\n v6 = strcmp(s1, \"zero\");\n if (!v6) goto LABEL_25;\n if (!strcmp(s1, \"one\")) break;\n if (!strcmp(s1, \"two\")) {\n ++DWORD2(v18);\n } else if (!strcmp(s1, \"three\")) {\n ++HIDWORD(v18);\n } else if (!strcmp(s1, \"four\")) {\n LODWORD(v19) = v19 + 1;\n } else if (!strcmp(s1, \"five\")) {\n ++DWORD1(v19);\n } else if (!strcmp(s1, \"six\")) {\n ++DWORD2(v19);\n } else if (!strcmp(s1, \"seven\")) {\n ++HIDWORD(v19);\n } else if (!strcmp(s1, \"eight\")) {\n LODWORD(v20) = v20 + 1;\n } else {\n if (strcmp(s1, \"nine\")) {\n i += v5;\n if (!*(i - 1)) goto LABEL_27;\n continue;\n }\n ++HIDWORD(v20);\n }\n LABEL_26:\n i += v5;\n if (!*(i - 1)) goto LABEL_27;\n }\n v6 = 1;\n LABEL_25:\n ++*((uint32_t *)&v18 + v6);\n goto LABEL_26;\n }\nLABEL_27:\n v7 = 0LL;\n v8 = 0;\n do {\n v9 = *((uint32_t *)&v18 + v7);\n if (v9 > 0) {\n v10 = (char *)*((uint64_t *)v21 + v7);\n v11 = 0;\n v12 = *v10;\n do {\n v13 = v8;\n if (v12) {\n v14 = v12;\n v15 = v8 + 1;\n v16 = &v10[-v8];\n do {\n byte_4040[v15 - 1] = v14;\n v13 = v15++;\n v14 = v16[v15 - 1];\n } while (v14);\n }\n v8 = v13 + 1;\n ++v11;\n byte_4040[v13] = 32;\n } while (v11 != v9);\n }\n ++v7;\n } while (v7 != 10);\n if (v8 <= 0)\n byte_4040[0] = 0;\n else\n byte_4040[v8 - 1] = 0;\n return byte_4040;\n}", + "ida_pseudo_norm": "char *func0(char *a1) {\n char v1;\n char *i;\n long long v3;\n long long v4;\n long long v5;\n int v6;\n long long v7;\n int v8;\n int v9;\n char *v10;\n int v11;\n char v12;\n int v13;\n char v14;\n long long v15;\n char *v16;\n __int128 v18;\n __int128 v19;\n long long v20;\n long double v21[5];\n char s1[6];\n unsigned long long v23;\n v23 = __readfsqword(40u);\n v18 = 0LL;\n v1 = *a1;\n v19 = 0LL;\n v20 = 0LL;\n v21[0] = _mm_loadh_ps((const double *)off_3D80);\n v21[1] = _mm_loadh_ps((const double *)off_3D88);\n v21[2] = _mm_loadh_ps((const double *)off_3D98);\n v21[3] = _mm_loadh_ps((const double *)off_3DA0);\n v21[4] = _mm_loadh_ps((const double *)&off_3DB0);\n if (v1) {\n for (i = a1;; v1 = *i) {\n if ((v1 & 223) != 0) {\n s1[0] = v1;\n if ((i[1] & 223) != 0) {\n s1[1] = i[1];\n if ((i[2] & 223) != 0) {\n s1[2] = i[2];\n if ((i[3] & 223) != 0) {\n s1[3] = i[3];\n if ((i[4] & 223) != 0) {\n s1[4] = i[4];\n if ((i[5] & 223) != 0) {\n s1[5] = i[5];\n v3 = 6LL;\n v4 = 6LL;\n } else {\n v4 = 5LL;\n v3 = 5LL;\n }\n } else {\n v4 = 4LL;\n v3 = 4LL;\n }\n } else {\n v4 = 3LL;\n v3 = 3LL;\n }\n } else {\n v4 = 2LL;\n v3 = 2LL;\n }\n } else {\n v4 = 1LL;\n v3 = 1LL;\n }\n v5 = v3 + 1;\n } else {\n v5 = 1LL;\n v4 = 0LL;\n }\n s1[v4] = 0;\n v6 = strcmp(s1, \"zero\");\n if (!v6) goto LABEL_25;\n if (!strcmp(s1, \"one\")) break;\n if (!strcmp(s1, \"two\")) {\n ++DWORD2(v18);\n } else if (!strcmp(s1, \"three\")) {\n ++HIDWORD(v18);\n } else if (!strcmp(s1, \"four\")) {\n LODWORD(v19) = v19 + 1;\n } else if (!strcmp(s1, \"five\")) {\n ++DWORD1(v19);\n } else if (!strcmp(s1, \"six\")) {\n ++DWORD2(v19);\n } else if (!strcmp(s1, \"seven\")) {\n ++HIDWORD(v19);\n } else if (!strcmp(s1, \"eight\")) {\n LODWORD(v20) = v20 + 1;\n } else {\n if (strcmp(s1, \"nine\")) {\n i += v5;\n if (!*(i - 1)) goto LABEL_27;\n continue;\n }\n ++HIDWORD(v20);\n }\n LABEL_26:\n i += v5;\n if (!*(i - 1)) goto LABEL_27;\n }\n v6 = 1;\n LABEL_25:\n ++*((uint32_t *)&v18 + v6);\n goto LABEL_26;\n }\nLABEL_27:\n v7 = 0LL;\n v8 = 0;\n do {\n v9 = *((uint32_t *)&v18 + v7);\n if (v9 > 0) {\n v10 = (char *)*((uint64_t *)v21 + v7);\n v11 = 0;\n v12 = *v10;\n do {\n v13 = v8;\n if (v12) {\n v14 = v12;\n v15 = v8 + 1;\n v16 = &v10[-v8];\n do {\n out_1[v15 - 1] = v14;\n v13 = v15++;\n v14 = v16[v15 - 1];\n } while (v14);\n }\n v8 = v13 + 1;\n ++v11;\n out_1[v13] = 32;\n } while (v11 != v9);\n }\n ++v7;\n } while (v7 != 10);\n if (v8 <= 0)\n out_1[0] = 0;\n else\n out_1[v8 - 1] = 0;\n return out_1;\n}" + }, + { + "index": "HumanEval-C-20", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "void func0(float numbers[], int size, float out[2]) {\n float min_diff = FLT_MAX;\n int i, j;\n out[0] = numbers[0];\n out[1] = numbers[1];\n for (i = 0; i < size; i++) {\n for (j = i + 1; j < size; j++) {\n float diff = fabs(numbers[i] - numbers[j]);\n if (diff < min_diff) {\n min_diff = diff;\n out[0] = numbers[i];\n out[1] = numbers[j];\n }\n }\n }\n if (out[0] > out[1]) {\n float temp = out[0];\n out[0] = out[1];\n out[1] = temp;\n }\n}", + "test": "#include \n#include \n\nint issame(float a[], float b[], int size) {\n const float EPSILON = 1e-4;\n for (int i = 0; i < size; i++) {\n if (fabs(a[i] - b[i]) > EPSILON) return 0;\n }\n return 1;\n}\n\nint main() {\n float result[2];\n\n float test1[] = {1.0, 2.0, 3.9, 4.0, 5.0, 2.2};\n float expected1[] = {3.9, 4.0};\n func0(test1, 6, result);\n assert(issame(result, expected1, 2));\n\n float test2[] = {1.0, 2.0, 5.9, 4.0, 5.0};\n float expected2[] = {5.0, 5.9};\n func0(test2, 5, result);\n assert(issame(result, expected2, 2));\n\n float test3[] = {1.0, 2.0, 3.0, 4.0, 5.0, 2.2};\n float expected3[] = {2.0, 2.2};\n func0(test3, 6, result);\n assert(issame(result, expected3, 2));\n\n float test4[] = {1.0, 2.0, 3.0, 4.0, 5.0, 2.0};\n float expected4[] = {2.0, 2.0};\n func0(test4, 6, result);\n assert(issame(result, expected4, 2));\n\n float test5[] = {1.1, 2.2, 3.1, 4.1, 5.1};\n float expected5[] = {2.2, 3.1};\n func0(test5, 5, result);\n assert(issame(result, expected5, 2));\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmovss xmm0, cs:dword_20C8\nmovss [rbp+var_14], xmm0\nmov rax, [rbp+var_28]\nmovss xmm0, dword ptr [rax]\nmov rax, [rbp+var_38]\nmovss dword ptr [rax], xmm0\nmov rax, [rbp+var_38]\nlea rdx, [rax+4]\nmov rax, [rbp+var_28]\nmovss xmm0, dword ptr [rax+4]\nmovss dword ptr [rdx], xmm0\nmov [rbp+var_10], 0\njmp loc_1279\nloc_11BA:\nmov eax, [rbp+var_10]\nadd eax, 1\nmov [rbp+var_C], eax\njmp loc_1269\nloc_11C8:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovss xmm1, dword ptr [rax]\nsubss xmm0, xmm1\nmovss xmm1, cs:dword_20D0\nandps xmm0, xmm1\nmovss [rbp+var_4], xmm0\nmovss xmm0, [rbp+var_14]\ncomiss xmm0, [rbp+var_4]\njbe short loc_1265\nmovss xmm0, [rbp+var_4]\nmovss [rbp+var_14], xmm0\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\nmov rax, [rbp+var_38]\nmovss dword ptr [rax], xmm0\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov rax, [rbp+var_38]\nadd rax, 4\nmovss xmm0, dword ptr [rdx]\nmovss dword ptr [rax], xmm0\nloc_1265:\nadd [rbp+var_C], 1\nloc_1269:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_2C]\njl loc_11C8\nadd [rbp+var_10], 1\nloc_1279:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_2C]\njl loc_11BA\nmov rax, [rbp+var_38]\nmovss xmm0, dword ptr [rax]\nmov rax, [rbp+var_38]\nadd rax, 4\nmovss xmm1, dword ptr [rax]\ncomiss xmm0, xmm1\nja short loc_12A0\njmp short loc_12CF\nloc_12A0:\nmov rax, [rbp+var_38]\nmovss xmm0, dword ptr [rax]\nmovss [rbp+var_8], xmm0\nmov rax, [rbp+var_38]\nmovss xmm0, dword ptr [rax+4]\nmov rax, [rbp+var_38]\nmovss dword ptr [rax], xmm0\nmov rax, [rbp+var_38]\nadd rax, 4\nmovss xmm0, [rbp+var_8]\nmovss dword ptr [rax], xmm0\nloc_12CF:\nnop\npop rbp\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(float *a1, int a2, float *a3)\n{\n _DWORD *result; // rax\n float v4; // [rsp+24h] [rbp-14h]\n int i; // [rsp+28h] [rbp-10h]\n int j; // [rsp+2Ch] [rbp-Ch]\n float v7; // [rsp+30h] [rbp-8h]\n float v8; // [rsp+34h] [rbp-4h]\n\n v4 = 3.4028235e38;\n *a3 = *a1;\n a3[1] = a1[1];\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n v8 = fabs(a1[i] - a1[j]);\n if ( v4 > v8 )\n {\n v4 = v8;\n *a3 = a1[i];\n a3[1] = a1[j];\n }\n }\n }\n result = a3 + 1;\n if ( *a3 > a3[1] )\n {\n v7 = *a3;\n *a3 = a3[1];\n result = a3 + 1;\n a3[1] = v7;\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmovss xmm0, cs:dword_20C8\nmovss [rbp+var_14], xmm0\nmov rax, [rbp+var_28]\nmovss xmm0, dword ptr [rax]\nmov rax, [rbp+var_38]\nmovss dword ptr [rax], xmm0\nmov rax, [rbp+var_38]\nlea rdx, [rax+4]\nmov rax, [rbp+var_28]\nmovss xmm0, dword ptr [rax+4]\nmovss dword ptr [rdx], xmm0\nmov [rbp+var_10], 0\njmp loc_1279\nloc_11BA:\nmov eax, [rbp+var_10]\nadd eax, 1\nmov [rbp+var_C], eax\njmp loc_1269\nloc_11C8:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovss xmm1, dword ptr [rax]\nsubss xmm0, xmm1\nmovss xmm1, cs:dword_20D0\nandps xmm0, xmm1\nmovss [rbp+var_4], xmm0\nmovss xmm0, [rbp+var_14]\ncomiss xmm0, [rbp+var_4]\njbe short loc_1265\nmovss xmm0, [rbp+var_4]\nmovss [rbp+var_14], xmm0\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\nmov rax, [rbp+var_38]\nmovss dword ptr [rax], xmm0\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov rax, [rbp+var_38]\nadd rax, 4\nmovss xmm0, dword ptr [rdx]\nmovss dword ptr [rax], xmm0\nloc_1265:\nadd [rbp+var_C], 1\nloc_1269:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_2C]\njl loc_11C8\nadd [rbp+var_10], 1\nloc_1279:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_2C]\njl loc_11BA\nmov rax, [rbp+var_38]\nmovss xmm0, dword ptr [rax]\nmov rax, [rbp+var_38]\nadd rax, 4\nmovss xmm1, dword ptr [rax]\ncomiss xmm0, xmm1\nja short loc_12A0\njmp short loc_12CF\nloc_12A0:\nmov rax, [rbp+var_38]\nmovss xmm0, dword ptr [rax]\nmovss [rbp+var_8], xmm0\nmov rax, [rbp+var_38]\nmovss xmm0, dword ptr [rax+4]\nmov rax, [rbp+var_38]\nmovss dword ptr [rax], xmm0\nmov rax, [rbp+var_38]\nadd rax, 4\nmovss xmm0, [rbp+var_8]\nmovss dword ptr [rax], xmm0\nloc_12CF:\nnop\npop rbp\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1169(float *a1, int a2, float *a3)\n{\n _DWORD *result; // rax\n float v4; // [rsp+24h] [rbp-14h]\n int i; // [rsp+28h] [rbp-10h]\n int j; // [rsp+2Ch] [rbp-Ch]\n float v7; // [rsp+30h] [rbp-8h]\n float v8; // [rsp+34h] [rbp-4h]\n\n v4 = 3.4028235e38;\n *a3 = *a1;\n a3[1] = a1[1];\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n v8 = fabs(a1[i] - a1[j]);\n if ( v4 > v8 )\n {\n v4 = v8;\n *a3 = a1[i];\n a3[1] = a1[j];\n }\n }\n }\n result = a3 + 1;\n if ( *a3 > a3[1] )\n {\n v7 = *a3;\n *a3 = a3[1];\n result = a3 + 1;\n a3[1] = v7;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1169(float *a1, int a2, float *a3) {\n uint32_t *result;\n float v4;\n int i;\n int j;\n float v7;\n float v8;\n v4 = 3.4028235e38;\n *a3 = *a1;\n a3[1] = a1[1];\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n v8 = fabs(a1[i] - a1[j]);\n if (v4 > v8) {\n v4 = v8;\n *a3 = a1[i];\n a3[1] = a1[j];\n }\n }\n }\n result = a3 + 1;\n if (*a3 > a3[1]) {\n v7 = *a3;\n *a3 = a3[1];\n result = a3 + 1;\n a3[1] = v7;\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(float *a1, int a2, float *a3) {\n uint32_t *result;\n float v4;\n int i;\n int j;\n float v7;\n float v8;\n v4 = 3.4028235e38;\n *a3 = *a1;\n a3[1] = a1[1];\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n v8 = fabs(a1[i] - a1[j]);\n if (v4 > v8) {\n v4 = v8;\n *a3 = a1[i];\n a3[1] = a1[j];\n }\n }\n }\n result = a3 + 1;\n if (*a3 > a3[1]) {\n v7 = *a3;\n *a3 = a3[1];\n result = a3 + 1;\n a3[1] = v7;\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-20", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "void func0(float numbers[], int size, float out[2]) {\n float min_diff = FLT_MAX;\n int i, j;\n out[0] = numbers[0];\n out[1] = numbers[1];\n for (i = 0; i < size; i++) {\n for (j = i + 1; j < size; j++) {\n float diff = fabs(numbers[i] - numbers[j]);\n if (diff < min_diff) {\n min_diff = diff;\n out[0] = numbers[i];\n out[1] = numbers[j];\n }\n }\n }\n if (out[0] > out[1]) {\n float temp = out[0];\n out[0] = out[1];\n out[1] = temp;\n }\n}", + "test": "#include \n#include \n\nint issame(float a[], float b[], int size) {\n const float EPSILON = 1e-4;\n for (int i = 0; i < size; i++) {\n if (fabs(a[i] - b[i]) > EPSILON) return 0;\n }\n return 1;\n}\n\nint main() {\n float result[2];\n\n float test1[] = {1.0, 2.0, 3.9, 4.0, 5.0, 2.2};\n float expected1[] = {3.9, 4.0};\n func0(test1, 6, result);\n assert(issame(result, expected1, 2));\n\n float test2[] = {1.0, 2.0, 5.9, 4.0, 5.0};\n float expected2[] = {5.0, 5.9};\n func0(test2, 5, result);\n assert(issame(result, expected2, 2));\n\n float test3[] = {1.0, 2.0, 3.0, 4.0, 5.0, 2.2};\n float expected3[] = {2.0, 2.2};\n func0(test3, 6, result);\n assert(issame(result, expected3, 2));\n\n float test4[] = {1.0, 2.0, 3.0, 4.0, 5.0, 2.0};\n float expected4[] = {2.0, 2.0};\n func0(test4, 6, result);\n assert(issame(result, expected4, 2));\n\n float test5[] = {1.1, 2.2, 3.1, 4.1, 5.1};\n float expected5[] = {2.2, 3.1};\n func0(test5, 5, result);\n assert(issame(result, expected5, 2));\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmov rcx, rdx\nmovss xmm0, dword ptr [rdi]\nmovss dword ptr [rdx], xmm0\nmovss xmm0, dword ptr [rdi+4]\nmovss dword ptr [rdx+4], xmm0\ntest esi, esi\njle loc_120C\nlea rdx, [rdi+4]\nlea r11d, [rsi-1]\nmov r10d, esi\nmovsxd r9, esi\nmov r8d, 1\nmovss xmm2, cs:dword_2004\nadd rdi, 8\nmovss xmm3, cs:dword_20E0\njmp short loc_11F3\nloc_11B4:\nadd rax, 4\ncmp rax, rsi\njz short loc_11E3\nloc_11BD:\nmovss xmm1, dword ptr [rdx-4]\nmovaps xmm0, xmm1\nsubss xmm0, dword ptr [rax]\nandps xmm0, xmm3\ncomiss xmm2, xmm0\njbe short loc_11B4\nmovss dword ptr [rcx], xmm1\nmovss xmm1, dword ptr [rax]\nmovss dword ptr [rcx+4], xmm1\nmovaps xmm2, xmm0\njmp short loc_11B4\nloc_11E3:\nlea rax, [r8+1]\nadd rdx, 4\ncmp r8, r9\njz short loc_120C\nmov r8, rax\nloc_11F3:\ncmp r8, r10\njz short loc_120C\nmov eax, r11d\nsub eax, r8d\nlea rax, [r8+rax-1]\nlea rsi, [rdi+rax*4]\nmov rax, rdx\njmp short loc_11BD\nloc_120C:\nmovss xmm0, dword ptr [rcx]\nmovss xmm1, dword ptr [rcx+4]\ncomiss xmm0, xmm1\njbe short locret_1223\nmovss dword ptr [rcx], xmm1\nmovss dword ptr [rcx+4], xmm0\nlocret_1223:\nretn", + "ida_pseudo": "void __fastcall func0(_DWORD *a1, int a2, float *a3)\n{\n float *v4; // rdx\n __int64 v5; // r8\n float v6; // xmm2_4\n _DWORD *v7; // rdi\n float *v8; // rax\n float v9; // xmm0_4\n float v10; // xmm0_4\n float v11; // xmm1_4\n\n *a3 = *(float *)a1;\n a3[1] = *((float *)a1 + 1);\n if ( a2 > 0 )\n {\n v4 = (float *)(a1 + 1);\n v5 = 1LL;\n v6 = 3.4028235e38;\n v7 = a1 + 2;\n while ( v5 != a2 )\n {\n v8 = v4;\n do\n {\n v9 = fabs(*(v4 - 1) - *v8);\n if ( v6 > v9 )\n {\n *a3 = *(v4 - 1);\n a3[1] = *v8;\n v6 = v9;\n }\n ++v8;\n }\n while ( v8 != (float *)&v7[v5 - 1 + (unsigned int)(a2 - 1 - v5)] );\n ++v4;\n if ( v5 == a2 )\n break;\n ++v5;\n }\n }\n v10 = *a3;\n v11 = a3[1];\n if ( *a3 > v11 )\n {\n *a3 = v11;\n a3[1] = v10;\n }\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov rcx, rdx\nmovss xmm0, dword ptr [rdi]\nmovss dword ptr [rdx], xmm0\nmovss xmm0, dword ptr [rdi+4]\nmovss dword ptr [rdx+4], xmm0\ntest esi, esi\njle loc_120C\nlea rdx, [rdi+4]\nlea r11d, [rsi-1]\nmov r10d, esi\nmovsxd r9, esi\nmov r8d, 1\nmovss xmm2, cs:dword_2004\nadd rdi, 8\nmovss xmm3, cs:dword_20E0\njmp short loc_11F3\nloc_11B4:\nadd rax, 4\ncmp rax, rsi\njz short loc_11E3\nloc_11BD:\nmovss xmm1, dword ptr [rdx-4]\nmovaps xmm0, xmm1\nsubss xmm0, dword ptr [rax]\nandps xmm0, xmm3\ncomiss xmm2, xmm0\njbe short loc_11B4\nmovss dword ptr [rcx], xmm1\nmovss xmm1, dword ptr [rax]\nmovss dword ptr [rcx+4], xmm1\nmovaps xmm2, xmm0\njmp short loc_11B4\nloc_11E3:\nlea rax, [r8+1]\nadd rdx, 4\ncmp r8, r9\njz short loc_120C\nmov r8, rax\nloc_11F3:\ncmp r8, r10\njz short loc_120C\nmov eax, r11d\nsub eax, r8d\nlea rax, [r8+rax-1]\nlea rsi, [rdi+rax*4]\nmov rax, rdx\njmp short loc_11BD\nloc_120C:\nmovss xmm0, dword ptr [rcx]\nmovss xmm1, dword ptr [rcx+4]\ncomiss xmm0, xmm1\njbe short locret_1223\nmovss dword ptr [rcx], xmm1\nmovss dword ptr [rcx+4], xmm0\nlocret_1223:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1169(_DWORD *a1, int a2, float *a3)\n{\n float *v4; // rdx\n __int64 v5; // r8\n float v6; // xmm2_4\n _DWORD *v7; // rdi\n float *v8; // rax\n float v9; // xmm0_4\n float v10; // xmm0_4\n float v11; // xmm1_4\n\n *a3 = *(float *)a1;\n a3[1] = *((float *)a1 + 1);\n if ( a2 > 0 )\n {\n v4 = (float *)(a1 + 1);\n v5 = 1LL;\n v6 = 3.4028235e38;\n v7 = a1 + 2;\n while ( v5 != a2 )\n {\n v8 = v4;\n do\n {\n v9 = fabs(*(v4 - 1) - *v8);\n if ( v6 > v9 )\n {\n *a3 = *(v4 - 1);\n a3[1] = *v8;\n v6 = v9;\n }\n ++v8;\n }\n while ( v8 != (float *)&v7[v5 - 1 + (unsigned int)(a2 - 1 - v5)] );\n ++v4;\n if ( v5 == a2 )\n break;\n ++v5;\n }\n }\n v10 = *a3;\n v11 = a3[1];\n if ( *a3 > v11 )\n {\n *a3 = v11;\n a3[1] = v10;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1169(uint32_t *a1, int a2, float *a3) {\n float *v4;\n long long v5;\n float v6;\n uint32_t *v7;\n float *v8;\n float v9;\n float v10;\n float v11;\n *a3 = *(float *)a1;\n a3[1] = *((float *)a1 + 1);\n if (a2 > 0) {\n v4 = (float *)(a1 + 1);\n v5 = 1LL;\n v6 = 3.4028235e38;\n v7 = a1 + 2;\n while (v5 != a2) {\n v8 = v4;\n do {\n v9 = fabs(*(v4 - 1) - *v8);\n if (v6 > v9) {\n *a3 = *(v4 - 1);\n a3[1] = *v8;\n v6 = v9;\n }\n ++v8;\n } while (v8 != (float *)&v7[v5 - 1 + (unsigned int)(a2 - 1 - v5)]);\n ++v4;\n if (v5 == a2) break;\n ++v5;\n }\n }\n v10 = *a3;\n v11 = a3[1];\n if (*a3 > v11) {\n *a3 = v11;\n a3[1] = v10;\n }\n}", + "ida_pseudo_norm": "void func0(uint32_t *a1, int a2, float *a3) {\n float *v4;\n long long v5;\n float v6;\n uint32_t *v7;\n float *v8;\n float v9;\n float v10;\n float v11;\n *a3 = *(float *)a1;\n a3[1] = *((float *)a1 + 1);\n if (a2 > 0) {\n v4 = (float *)(a1 + 1);\n v5 = 1LL;\n v6 = 3.4028235e38;\n v7 = a1 + 2;\n while (v5 != a2) {\n v8 = v4;\n do {\n v9 = fabs(*(v4 - 1) - *v8);\n if (v6 > v9) {\n *a3 = *(v4 - 1);\n a3[1] = *v8;\n v6 = v9;\n }\n ++v8;\n } while (v8 != (float *)&v7[v5 - 1 + (unsigned int)(a2 - 1 - v5)]);\n ++v4;\n if (v5 == a2) break;\n ++v5;\n }\n }\n v10 = *a3;\n v11 = a3[1];\n if (*a3 > v11) {\n *a3 = v11;\n a3[1] = v10;\n }\n}" + }, + { + "index": "HumanEval-C-20", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "void func0(float numbers[], int size, float out[2]) {\n float min_diff = FLT_MAX;\n int i, j;\n out[0] = numbers[0];\n out[1] = numbers[1];\n for (i = 0; i < size; i++) {\n for (j = i + 1; j < size; j++) {\n float diff = fabs(numbers[i] - numbers[j]);\n if (diff < min_diff) {\n min_diff = diff;\n out[0] = numbers[i];\n out[1] = numbers[j];\n }\n }\n }\n if (out[0] > out[1]) {\n float temp = out[0];\n out[0] = out[1];\n out[1] = temp;\n }\n}", + "test": "#include \n#include \n\nint issame(float a[], float b[], int size) {\n const float EPSILON = 1e-4;\n for (int i = 0; i < size; i++) {\n if (fabs(a[i] - b[i]) > EPSILON) return 0;\n }\n return 1;\n}\n\nint main() {\n float result[2];\n\n float test1[] = {1.0, 2.0, 3.9, 4.0, 5.0, 2.2};\n float expected1[] = {3.9, 4.0};\n func0(test1, 6, result);\n assert(issame(result, expected1, 2));\n\n float test2[] = {1.0, 2.0, 5.9, 4.0, 5.0};\n float expected2[] = {5.0, 5.9};\n func0(test2, 5, result);\n assert(issame(result, expected2, 2));\n\n float test3[] = {1.0, 2.0, 3.0, 4.0, 5.0, 2.2};\n float expected3[] = {2.0, 2.2};\n func0(test3, 6, result);\n assert(issame(result, expected3, 2));\n\n float test4[] = {1.0, 2.0, 3.0, 4.0, 5.0, 2.0};\n float expected4[] = {2.0, 2.0};\n func0(test4, 6, result);\n assert(issame(result, expected4, 2));\n\n float test5[] = {1.1, 2.2, 3.1, 4.1, 5.1};\n float expected5[] = {2.2, 3.1};\n func0(test5, 5, result);\n assert(issame(result, expected5, 2));\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmovss xmm0, dword ptr [rdi]\nmovss dword ptr [rdx], xmm0\nmovss xmm1, dword ptr [rdi+4]\nmovss dword ptr [rdx+4], xmm1\ntest esi, esi\njle short loc_146B\ncmp esi, 1\njz short loc_1462\nmovss xmm2, cs:dword_2004\nmov rcx, rdi\nmov r9d, esi\nmov r8d, 1\nmovss xmm3, cs:dword_20D0\nnop dword ptr [rax+rax+00h]\nloc_1420:\nmov rax, r8\nnop dword ptr [rax+rax+00h]\nloc_1428:\nmovss xmm1, dword ptr [rcx]\nmovaps xmm0, xmm1\nsubss xmm0, dword ptr [rdi+rax*4]\nandps xmm0, xmm3\ncomiss xmm2, xmm0\njbe short loc_144D\nmovss dword ptr [rdx], xmm1\nmovss xmm1, dword ptr [rdi+rax*4]\nmovaps xmm2, xmm0\nmovss dword ptr [rdx+4], xmm1\nloc_144D:\nadd rax, 1\ncmp esi, eax\njg short loc_1428\nadd r8, 1\nadd rcx, 4\ncmp r8, r9\njnz short loc_1420\nloc_1462:\nmovss xmm0, dword ptr [rdx]\nmovss xmm1, dword ptr [rdx+4]\nloc_146B:\ncomiss xmm0, xmm1\njbe short locret_1479\nmovss dword ptr [rdx], xmm1\nmovss dword ptr [rdx+4], xmm0\nlocret_1479:\nretn", + "ida_pseudo": "void __fastcall func0(float *a1, int a2, float *a3)\n{\n float v3; // xmm0_4\n float v4; // xmm1_4\n float v5; // xmm2_4\n float *v6; // rcx\n __int64 i; // r8\n __int64 v8; // rax\n float v9; // xmm0_4\n\n v3 = *a1;\n *a3 = *a1;\n v4 = a1[1];\n a3[1] = v4;\n if ( a2 > 0 )\n {\n if ( a2 != 1 )\n {\n v5 = 3.4028235e38;\n v6 = a1;\n for ( i = 1LL; i != a2; ++i )\n {\n v8 = i;\n do\n {\n v9 = fabs(*v6 - a1[v8]);\n if ( v5 > v9 )\n {\n *a3 = *v6;\n v5 = v9;\n a3[1] = a1[v8];\n }\n ++v8;\n }\n while ( a2 > (int)v8 );\n ++v6;\n }\n }\n v3 = *a3;\n v4 = a3[1];\n }\n if ( v3 > v4 )\n {\n *a3 = v4;\n a3[1] = v3;\n }\n}", + "ida_strip_asm": "sub_13E0:\nendbr64\nmovss xmm0, dword ptr [rdi]\nmovss dword ptr [rdx], xmm0\nmovss xmm1, dword ptr [rdi+4]\nmovss dword ptr [rdx+4], xmm1\ntest esi, esi\njle short loc_146B\ncmp esi, 1\njz short loc_1462\nmovss xmm2, cs:dword_2004\nmov rcx, rdi\nmov r9d, esi\nmov r8d, 1\nmovss xmm3, cs:dword_20D0\nnop dword ptr [rax+rax+00h]\nloc_1420:\nmov rax, r8\nnop dword ptr [rax+rax+00h]\nloc_1428:\nmovss xmm1, dword ptr [rcx]\nmovaps xmm0, xmm1\nsubss xmm0, dword ptr [rdi+rax*4]\nandps xmm0, xmm3\ncomiss xmm2, xmm0\njbe short loc_144D\nmovss dword ptr [rdx], xmm1\nmovss xmm1, dword ptr [rdi+rax*4]\nmovaps xmm2, xmm0\nmovss dword ptr [rdx+4], xmm1\nloc_144D:\nadd rax, 1\ncmp esi, eax\njg short loc_1428\nadd r8, 1\nadd rcx, 4\ncmp r8, r9\njnz short loc_1420\nloc_1462:\nmovss xmm0, dword ptr [rdx]\nmovss xmm1, dword ptr [rdx+4]\nloc_146B:\ncomiss xmm0, xmm1\njbe short locret_1479\nmovss dword ptr [rdx], xmm1\nmovss dword ptr [rdx+4], xmm0\nlocret_1479:\nretn", + "ida_strip_pseudo": "void __fastcall sub_13E0(float *a1, int a2, float *a3)\n{\n float v3; // xmm0_4\n float v4; // xmm1_4\n float v5; // xmm2_4\n float *v6; // rcx\n __int64 i; // r8\n __int64 v8; // rax\n float v9; // xmm0_4\n\n v3 = *a1;\n *a3 = *a1;\n v4 = a1[1];\n a3[1] = v4;\n if ( a2 > 0 )\n {\n if ( a2 != 1 )\n {\n v5 = 3.4028235e38;\n v6 = a1;\n for ( i = 1LL; i != a2; ++i )\n {\n v8 = i;\n do\n {\n v9 = fabs(*v6 - a1[v8]);\n if ( v5 > v9 )\n {\n *a3 = *v6;\n v5 = v9;\n a3[1] = a1[v8];\n }\n ++v8;\n }\n while ( a2 > (int)v8 );\n ++v6;\n }\n }\n v3 = *a3;\n v4 = a3[1];\n }\n if ( v3 > v4 )\n {\n *a3 = v4;\n a3[1] = v3;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_13E0(float *a1, int a2, float *a3) {\n float v3;\n float v4;\n float v5;\n float *v6;\n long long i;\n long long v8;\n float v9;\n v3 = *a1;\n *a3 = *a1;\n v4 = a1[1];\n a3[1] = v4;\n if (a2 > 0) {\n if (a2 != 1) {\n v5 = 3.4028235e38;\n v6 = a1;\n for (i = 1LL; i != a2; ++i) {\n v8 = i;\n do {\n v9 = fabs(*v6 - a1[v8]);\n if (v5 > v9) {\n *a3 = *v6;\n v5 = v9;\n a3[1] = a1[v8];\n }\n ++v8;\n } while (a2 > (int)v8);\n ++v6;\n }\n }\n v3 = *a3;\n v4 = a3[1];\n }\n if (v3 > v4) {\n *a3 = v4;\n a3[1] = v3;\n }\n}", + "ida_pseudo_norm": "void func0(float *a1, int a2, float *a3) {\n float v3;\n float v4;\n float v5;\n float *v6;\n long long i;\n long long v8;\n float v9;\n v3 = *a1;\n *a3 = *a1;\n v4 = a1[1];\n a3[1] = v4;\n if (a2 > 0) {\n if (a2 != 1) {\n v5 = 3.4028235e38;\n v6 = a1;\n for (i = 1LL; i != a2; ++i) {\n v8 = i;\n do {\n v9 = fabs(*v6 - a1[v8]);\n if (v5 > v9) {\n *a3 = *v6;\n v5 = v9;\n a3[1] = a1[v8];\n }\n ++v8;\n } while (a2 > (int)v8);\n ++v6;\n }\n }\n v3 = *a3;\n v4 = a3[1];\n }\n if (v3 > v4) {\n *a3 = v4;\n a3[1] = v3;\n }\n}" + }, + { + "index": "HumanEval-C-20", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "void func0(float numbers[], int size, float out[2]) {\n float min_diff = FLT_MAX;\n int i, j;\n out[0] = numbers[0];\n out[1] = numbers[1];\n for (i = 0; i < size; i++) {\n for (j = i + 1; j < size; j++) {\n float diff = fabs(numbers[i] - numbers[j]);\n if (diff < min_diff) {\n min_diff = diff;\n out[0] = numbers[i];\n out[1] = numbers[j];\n }\n }\n }\n if (out[0] > out[1]) {\n float temp = out[0];\n out[0] = out[1];\n out[1] = temp;\n }\n}", + "test": "#include \n#include \n\nint issame(float a[], float b[], int size) {\n const float EPSILON = 1e-4;\n for (int i = 0; i < size; i++) {\n if (fabs(a[i] - b[i]) > EPSILON) return 0;\n }\n return 1;\n}\n\nint main() {\n float result[2];\n\n float test1[] = {1.0, 2.0, 3.9, 4.0, 5.0, 2.2};\n float expected1[] = {3.9, 4.0};\n func0(test1, 6, result);\n assert(issame(result, expected1, 2));\n\n float test2[] = {1.0, 2.0, 5.9, 4.0, 5.0};\n float expected2[] = {5.0, 5.9};\n func0(test2, 5, result);\n assert(issame(result, expected2, 2));\n\n float test3[] = {1.0, 2.0, 3.0, 4.0, 5.0, 2.2};\n float expected3[] = {2.0, 2.2};\n func0(test3, 6, result);\n assert(issame(result, expected3, 2));\n\n float test4[] = {1.0, 2.0, 3.0, 4.0, 5.0, 2.0};\n float expected4[] = {2.0, 2.0};\n func0(test4, 6, result);\n assert(issame(result, expected4, 2));\n\n float test5[] = {1.1, 2.2, 3.1, 4.1, 5.1};\n float expected5[] = {2.2, 3.1};\n func0(test5, 5, result);\n assert(issame(result, expected5, 2));\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmovss xmm0, dword ptr [rdi]\nmovss dword ptr [rdx], xmm0\nmovss xmm1, dword ptr [rdi+4]\nmovss dword ptr [rdx+4], xmm1\ntest esi, esi\njle short loc_14CB\ncmp esi, 1\njz short loc_14C2\nmovss xmm2, cs:dword_2004\nmov rcx, rdi\nmov r9d, esi\nmov r8d, 1\nmovss xmm3, cs:dword_20D0\nnop dword ptr [rax+rax+00h]\nloc_1480:\nmov rax, r8\nnop dword ptr [rax+rax+00h]\nloc_1488:\nmovss xmm1, dword ptr [rcx]\nmovaps xmm0, xmm1\nsubss xmm0, dword ptr [rdi+rax*4]\nandps xmm0, xmm3\ncomiss xmm2, xmm0\njbe short loc_14AD\nmovss dword ptr [rdx], xmm1\nmovss xmm1, dword ptr [rdi+rax*4]\nmovaps xmm2, xmm0\nmovss dword ptr [rdx+4], xmm1\nloc_14AD:\nadd rax, 1\ncmp esi, eax\njg short loc_1488\nadd r8, 1\nadd rcx, 4\ncmp r9, r8\njnz short loc_1480\nloc_14C2:\nmovss xmm0, dword ptr [rdx]\nmovss xmm1, dword ptr [rdx+4]\nloc_14CB:\ncomiss xmm0, xmm1\njbe short locret_14D9\nmovss dword ptr [rdx], xmm1\nmovss dword ptr [rdx+4], xmm0\nlocret_14D9:\nretn", + "ida_pseudo": "void __fastcall func0(float *a1, int a2, float *a3)\n{\n float v3; // xmm0_4\n float v4; // xmm1_4\n float v5; // xmm2_4\n float *v6; // rcx\n __int64 i; // r8\n __int64 v8; // rax\n float v9; // xmm0_4\n\n v3 = *a1;\n *a3 = *a1;\n v4 = a1[1];\n a3[1] = v4;\n if ( a2 > 0 )\n {\n if ( a2 != 1 )\n {\n v5 = 3.4028235e38;\n v6 = a1;\n for ( i = 1LL; i != a2; ++i )\n {\n v8 = i;\n do\n {\n v9 = fabs(*v6 - a1[v8]);\n if ( v5 > v9 )\n {\n *a3 = *v6;\n v5 = v9;\n a3[1] = a1[v8];\n }\n ++v8;\n }\n while ( a2 > (int)v8 );\n ++v6;\n }\n }\n v3 = *a3;\n v4 = a3[1];\n }\n if ( v3 > v4 )\n {\n *a3 = v4;\n a3[1] = v3;\n }\n}", + "ida_strip_asm": "sub_1440:\nendbr64\nmovss xmm0, dword ptr [rdi]\nmovss dword ptr [rdx], xmm0\nmovss xmm1, dword ptr [rdi+4]\nmovss dword ptr [rdx+4], xmm1\ntest esi, esi\njle short loc_14CB\ncmp esi, 1\njz short loc_14C2\nmovss xmm2, cs:dword_2004\nmov rcx, rdi\nmov r9d, esi\nmov r8d, 1\nmovss xmm3, cs:dword_20D0\nnop dword ptr [rax+rax+00h]\nloc_1480:\nmov rax, r8\nnop dword ptr [rax+rax+00h]\nloc_1488:\nmovss xmm1, dword ptr [rcx]\nmovaps xmm0, xmm1\nsubss xmm0, dword ptr [rdi+rax*4]\nandps xmm0, xmm3\ncomiss xmm2, xmm0\njbe short loc_14AD\nmovss dword ptr [rdx], xmm1\nmovss xmm1, dword ptr [rdi+rax*4]\nmovaps xmm2, xmm0\nmovss dword ptr [rdx+4], xmm1\nloc_14AD:\nadd rax, 1\ncmp esi, eax\njg short loc_1488\nadd r8, 1\nadd rcx, 4\ncmp r9, r8\njnz short loc_1480\nloc_14C2:\nmovss xmm0, dword ptr [rdx]\nmovss xmm1, dword ptr [rdx+4]\nloc_14CB:\ncomiss xmm0, xmm1\njbe short locret_14D9\nmovss dword ptr [rdx], xmm1\nmovss dword ptr [rdx+4], xmm0\nlocret_14D9:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1440(float *a1, int a2, float *a3)\n{\n float v3; // xmm0_4\n float v4; // xmm1_4\n float v5; // xmm2_4\n float *v6; // rcx\n __int64 i; // r8\n __int64 v8; // rax\n float v9; // xmm0_4\n\n v3 = *a1;\n *a3 = *a1;\n v4 = a1[1];\n a3[1] = v4;\n if ( a2 > 0 )\n {\n if ( a2 != 1 )\n {\n v5 = 3.4028235e38;\n v6 = a1;\n for ( i = 1LL; i != a2; ++i )\n {\n v8 = i;\n do\n {\n v9 = fabs(*v6 - a1[v8]);\n if ( v5 > v9 )\n {\n *a3 = *v6;\n v5 = v9;\n a3[1] = a1[v8];\n }\n ++v8;\n }\n while ( a2 > (int)v8 );\n ++v6;\n }\n }\n v3 = *a3;\n v4 = a3[1];\n }\n if ( v3 > v4 )\n {\n *a3 = v4;\n a3[1] = v3;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1440(float *a1, int a2, float *a3) {\n float v3;\n float v4;\n float v5;\n float *v6;\n long long i;\n long long v8;\n float v9;\n v3 = *a1;\n *a3 = *a1;\n v4 = a1[1];\n a3[1] = v4;\n if (a2 > 0) {\n if (a2 != 1) {\n v5 = 3.4028235e38;\n v6 = a1;\n for (i = 1LL; i != a2; ++i) {\n v8 = i;\n do {\n v9 = fabs(*v6 - a1[v8]);\n if (v5 > v9) {\n *a3 = *v6;\n v5 = v9;\n a3[1] = a1[v8];\n }\n ++v8;\n } while (a2 > (int)v8);\n ++v6;\n }\n }\n v3 = *a3;\n v4 = a3[1];\n }\n if (v3 > v4) {\n *a3 = v4;\n a3[1] = v3;\n }\n}", + "ida_pseudo_norm": "void func0(float *a1, int a2, float *a3) {\n float v3;\n float v4;\n float v5;\n float *v6;\n long long i;\n long long v8;\n float v9;\n v3 = *a1;\n *a3 = *a1;\n v4 = a1[1];\n a3[1] = v4;\n if (a2 > 0) {\n if (a2 != 1) {\n v5 = 3.4028235e38;\n v6 = a1;\n for (i = 1LL; i != a2; ++i) {\n v8 = i;\n do {\n v9 = fabs(*v6 - a1[v8]);\n if (v5 > v9) {\n *a3 = *v6;\n v5 = v9;\n a3[1] = a1[v8];\n }\n ++v8;\n } while (a2 > (int)v8);\n ++v6;\n }\n }\n v3 = *a3;\n v4 = a3[1];\n }\n if (v3 > v4) {\n *a3 = v4;\n a3[1] = v3;\n }\n}" + }, + { + "index": "HumanEval-C-21", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(float *numbers, int size) {\n float min = numbers[0], max = numbers[0];\n for (int i = 1; i < size; i++) {\n if (numbers[i] < min) min = numbers[i];\n if (numbers[i] > max) max = numbers[i];\n }\n for (int i = 0; i < size; i++) {\n numbers[i] = (numbers[i] - min) / (max - min);\n }\n}", + "test": "#include \n\nint issame(float *a, float *b, int size) {\n const float EPSILON = 1e-4;\n for (int i = 0; i < size; i++) {\n if (fabs(a[i] - b[i]) > EPSILON) return 0;\n }\n return 1;\n}\n\nint main() {\n float test1[] = {2.0, 49.9};\n float expected1[] = {0.0, 1.0};\n func0(test1, 2);\n assert(issame(test1, expected1, 2));\n\n float test2[] = {100.0, 49.9};\n float expected2[] = {1.0, 0.0};\n func0(test2, 2);\n assert(issame(test2, expected2, 2));\n\n float test3[] = {1.0, 2.0, 3.0, 4.0, 5.0};\n float expected3[] = {0.0, 0.25, 0.5, 0.75, 1.0};\n func0(test3, 5);\n assert(issame(test3, expected3, 5));\n\n float test4[] = {2.0, 1.0, 5.0, 3.0, 4.0};\n float expected4[] = {0.25, 0.0, 1.0, 0.5, 0.75};\n func0(test4, 5);\n assert(issame(test4, expected4, 5));\n\n float test5[] = {12.0, 11.0, 15.0, 13.0, 14.0};\n float expected5[] = {0.25, 0.0, 1.0, 0.5, 0.75};\n func0(test5, 5);\n assert(issame(test5, expected5, 5));\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov rax, [rbp+var_18]\nmovss xmm0, dword ptr [rax]\nmovss [rbp+var_10], xmm0\nmov rax, [rbp+var_18]\nmovss xmm0, dword ptr [rax]\nmovss [rbp+var_C], xmm0\nmov [rbp+var_8], 1\njmp short loc_1219\nloc_119B:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm1, dword ptr [rax]\nmovss xmm0, [rbp+var_10]\ncomiss xmm0, xmm1\njbe short loc_11DA\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\nmovss [rbp+var_10], xmm0\nloc_11DA:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\ncomiss xmm0, [rbp+var_C]\njbe short loc_1215\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\nmovss [rbp+var_C], xmm0\nloc_1215:\nadd [rbp+var_8], 1\nloc_1219:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl loc_119B\nmov [rbp+var_4], 0\njmp short loc_1275\nloc_122E:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\nsubss xmm0, [rbp+var_10]\nmovss xmm1, [rbp+var_C]\nsubss xmm1, [rbp+var_10]\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\ndivss xmm0, xmm1\nmovss dword ptr [rax], xmm0\nadd [rbp+var_4], 1\nloc_1275:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_122E\nnop\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(float *a1, int a2)\n{\n __int64 result; // rax\n float v3; // [rsp+Ch] [rbp-10h]\n float v4; // [rsp+10h] [rbp-Ch]\n int i; // [rsp+14h] [rbp-8h]\n int j; // [rsp+18h] [rbp-4h]\n\n v3 = *a1;\n v4 = *a1;\n for ( i = 1; i < a2; ++i )\n {\n if ( v3 > a1[i] )\n v3 = a1[i];\n if ( a1[i] > v4 )\n v4 = a1[i];\n }\n for ( j = 0; ; ++j )\n {\n result = (unsigned int)j;\n if ( j >= a2 )\n break;\n a1[j] = (float)(a1[j] - v3) / (float)(v4 - v3);\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov rax, [rbp+var_18]\nmovss xmm0, dword ptr [rax]\nmovss [rbp+var_10], xmm0\nmov rax, [rbp+var_18]\nmovss xmm0, dword ptr [rax]\nmovss [rbp+var_C], xmm0\nmov [rbp+var_8], 1\njmp short loc_1219\nloc_119B:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm1, dword ptr [rax]\nmovss xmm0, [rbp+var_10]\ncomiss xmm0, xmm1\njbe short loc_11DA\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\nmovss [rbp+var_10], xmm0\nloc_11DA:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\ncomiss xmm0, [rbp+var_C]\njbe short loc_1215\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\nmovss [rbp+var_C], xmm0\nloc_1215:\nadd [rbp+var_8], 1\nloc_1219:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl loc_119B\nmov [rbp+var_4], 0\njmp short loc_1275\nloc_122E:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\nsubss xmm0, [rbp+var_10]\nmovss xmm1, [rbp+var_C]\nsubss xmm1, [rbp+var_10]\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\ndivss xmm0, xmm1\nmovss dword ptr [rax], xmm0\nadd [rbp+var_4], 1\nloc_1275:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_122E\nnop\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(float *a1, int a2)\n{\n __int64 result; // rax\n float v3; // [rsp+Ch] [rbp-10h]\n float v4; // [rsp+10h] [rbp-Ch]\n int i; // [rsp+14h] [rbp-8h]\n int j; // [rsp+18h] [rbp-4h]\n\n v3 = *a1;\n v4 = *a1;\n for ( i = 1; i < a2; ++i )\n {\n if ( v3 > a1[i] )\n v3 = a1[i];\n if ( a1[i] > v4 )\n v4 = a1[i];\n }\n for ( j = 0; ; ++j )\n {\n result = (unsigned int)j;\n if ( j >= a2 )\n break;\n a1[j] = (float)(a1[j] - v3) / (float)(v4 - v3);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(float *a1, int a2) {\n long long result;\n float v3;\n float v4;\n int i;\n int j;\n v3 = *a1;\n v4 = *a1;\n for (i = 1; i < a2; ++i) {\n if (v3 > a1[i]) v3 = a1[i];\n if (a1[i] > v4) v4 = a1[i];\n }\n for (j = 0;; ++j) {\n result = (unsigned int)j;\n if (j >= a2) break;\n a1[j] = (float)(a1[j] - v3) / (float)(v4 - v3);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(float *a1, int a2) {\n long long result;\n float v3;\n float v4;\n int i;\n int j;\n v3 = *a1;\n v4 = *a1;\n for (i = 1; i < a2; ++i) {\n if (v3 > a1[i]) v3 = a1[i];\n if (a1[i] > v4) v4 = a1[i];\n }\n for (j = 0;; ++j) {\n result = (unsigned int)j;\n if (j >= a2) break;\n a1[j] = (float)(a1[j] - v3) / (float)(v4 - v3);\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-21", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(float *numbers, int size) {\n float min = numbers[0], max = numbers[0];\n for (int i = 1; i < size; i++) {\n if (numbers[i] < min) min = numbers[i];\n if (numbers[i] > max) max = numbers[i];\n }\n for (int i = 0; i < size; i++) {\n numbers[i] = (numbers[i] - min) / (max - min);\n }\n}", + "test": "#include \n\nint issame(float *a, float *b, int size) {\n const float EPSILON = 1e-4;\n for (int i = 0; i < size; i++) {\n if (fabs(a[i] - b[i]) > EPSILON) return 0;\n }\n return 1;\n}\n\nint main() {\n float test1[] = {2.0, 49.9};\n float expected1[] = {0.0, 1.0};\n func0(test1, 2);\n assert(issame(test1, expected1, 2));\n\n float test2[] = {100.0, 49.9};\n float expected2[] = {1.0, 0.0};\n func0(test2, 2);\n assert(issame(test2, expected2, 2));\n\n float test3[] = {1.0, 2.0, 3.0, 4.0, 5.0};\n float expected3[] = {0.0, 0.25, 0.5, 0.75, 1.0};\n func0(test3, 5);\n assert(issame(test3, expected3, 5));\n\n float test4[] = {2.0, 1.0, 5.0, 3.0, 4.0};\n float expected4[] = {0.25, 0.0, 1.0, 0.5, 0.75};\n func0(test4, 5);\n assert(issame(test4, expected4, 5));\n\n float test5[] = {12.0, 11.0, 15.0, 13.0, 14.0};\n float expected5[] = {0.25, 0.0, 1.0, 0.5, 0.75};\n func0(test5, 5);\n assert(issame(test5, expected5, 5));\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmovss xmm1, dword ptr [rdi]\ncmp esi, 1\njle short loc_11CE\nlea rax, [rdi+4]\nlea edx, [rsi-2]\nlea rdx, [rdi+rdx*4+8]\nmovaps xmm0, xmm1\nloc_1185:\nmovss xmm2, dword ptr [rax]\nmovaps xmm3, xmm2\nminss xmm3, xmm1\nmovaps xmm1, xmm3\nmaxss xmm2, xmm0\nmovaps xmm0, xmm2\nadd rax, 4\ncmp rax, rdx\njnz short loc_1185\nloc_11A3:\nmov rax, rdi\nmovsxd rsi, esi\nlea rdx, [rdi+rsi*4]\nmovaps xmm2, xmm0\nsubss xmm2, xmm1\nloc_11B4:\nmovss xmm0, dword ptr [rax]\nsubss xmm0, xmm1\ndivss xmm0, xmm2\nmovss dword ptr [rax], xmm0\nadd rax, 4\ncmp rax, rdx\njnz short loc_11B4\nlocret_11CD:\nretn\nloc_11CE:\ntest esi, esi\njle short locret_11CD\nmovaps xmm0, xmm1\njmp short loc_11A3", + "ida_pseudo": "void __fastcall func0(float *a1, int a2)\n{\n float v2; // xmm1_4\n float *v3; // rax\n float v4; // xmm0_4\n float *v5; // rax\n\n v2 = *a1;\n if ( a2 <= 1 )\n {\n if ( a2 <= 0 )\n return;\n v4 = *a1;\n }\n else\n {\n v3 = a1 + 1;\n v4 = *a1;\n do\n {\n v2 = fminf(*v3, v2);\n v4 = fmaxf(*v3++, v4);\n }\n while ( v3 != &a1[a2 - 2 + 2] );\n }\n v5 = a1;\n do\n {\n *v5 = (float)(*v5 - v2) / (float)(v4 - v2);\n ++v5;\n }\n while ( v5 != &a1[a2] );\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmovss xmm1, dword ptr [rdi]\ncmp esi, 1\njle short loc_11CE\nlea rax, [rdi+4]\nlea edx, [rsi-2]\nlea rdx, [rdi+rdx*4+8]\nmovaps xmm0, xmm1\nloc_1185:\nmovss xmm2, dword ptr [rax]\nmovaps xmm3, xmm2\nminss xmm3, xmm1\nmovaps xmm1, xmm3\nmaxss xmm2, xmm0\nmovaps xmm0, xmm2\nadd rax, 4\ncmp rax, rdx\njnz short loc_1185\nloc_11A3:\nmov rax, rdi\nmovsxd rsi, esi\nlea rdx, [rdi+rsi*4]\nmovaps xmm2, xmm0\nsubss xmm2, xmm1\nloc_11B4:\nmovss xmm0, dword ptr [rax]\nsubss xmm0, xmm1\ndivss xmm0, xmm2\nmovss dword ptr [rax], xmm0\nadd rax, 4\ncmp rax, rdx\njnz short loc_11B4\nlocret_11CD:\nretn\nloc_11CE:\ntest esi, esi\njle short locret_11CD\nmovaps xmm0, xmm1\njmp short loc_11A3", + "ida_strip_pseudo": "void __fastcall sub_1169(float *a1, int a2)\n{\n float v2; // xmm1_4\n float *v3; // rax\n float v4; // xmm0_4\n float *v5; // rax\n\n v2 = *a1;\n if ( a2 <= 1 )\n {\n if ( a2 <= 0 )\n return;\n v4 = *a1;\n }\n else\n {\n v3 = a1 + 1;\n v4 = *a1;\n do\n {\n v2 = fminf(*v3, v2);\n v4 = fmaxf(*v3++, v4);\n }\n while ( v3 != &a1[a2 - 2 + 2] );\n }\n v5 = a1;\n do\n {\n *v5 = (float)(*v5 - v2) / (float)(v4 - v2);\n ++v5;\n }\n while ( v5 != &a1[a2] );\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1169(float *a1, int a2) {\n float v2;\n float *v3;\n float v4;\n float *v5;\n v2 = *a1;\n if (a2 <= 1) {\n if (a2 <= 0) return;\n v4 = *a1;\n } else {\n v3 = a1 + 1;\n v4 = *a1;\n do {\n v2 = fminf(*v3, v2);\n v4 = fmaxf(*v3++, v4);\n } while (v3 != &a1[a2 - 2 + 2]);\n }\n v5 = a1;\n do {\n *v5 = (float)(*v5 - v2) / (float)(v4 - v2);\n ++v5;\n } while (v5 != &a1[a2]);\n}", + "ida_pseudo_norm": "void func0(float *a1, int a2) {\n float v2;\n float *v3;\n float v4;\n float *v5;\n v2 = *a1;\n if (a2 <= 1) {\n if (a2 <= 0) return;\n v4 = *a1;\n } else {\n v3 = a1 + 1;\n v4 = *a1;\n do {\n v2 = fminf(*v3, v2);\n v4 = fmaxf(*v3++, v4);\n } while (v3 != &a1[a2 - 2 + 2]);\n }\n v5 = a1;\n do {\n *v5 = (float)(*v5 - v2) / (float)(v4 - v2);\n ++v5;\n } while (v5 != &a1[a2]);\n}" + }, + { + "index": "HumanEval-C-21", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(float *numbers, int size) {\n float min = numbers[0], max = numbers[0];\n for (int i = 1; i < size; i++) {\n if (numbers[i] < min) min = numbers[i];\n if (numbers[i] > max) max = numbers[i];\n }\n for (int i = 0; i < size; i++) {\n numbers[i] = (numbers[i] - min) / (max - min);\n }\n}", + "test": "#include \n\nint issame(float *a, float *b, int size) {\n const float EPSILON = 1e-4;\n for (int i = 0; i < size; i++) {\n if (fabs(a[i] - b[i]) > EPSILON) return 0;\n }\n return 1;\n}\n\nint main() {\n float test1[] = {2.0, 49.9};\n float expected1[] = {0.0, 1.0};\n func0(test1, 2);\n assert(issame(test1, expected1, 2));\n\n float test2[] = {100.0, 49.9};\n float expected2[] = {1.0, 0.0};\n func0(test2, 2);\n assert(issame(test2, expected2, 2));\n\n float test3[] = {1.0, 2.0, 3.0, 4.0, 5.0};\n float expected3[] = {0.0, 0.25, 0.5, 0.75, 1.0};\n func0(test3, 5);\n assert(issame(test3, expected3, 5));\n\n float test4[] = {2.0, 1.0, 5.0, 3.0, 4.0};\n float expected4[] = {0.25, 0.0, 1.0, 0.5, 0.75};\n func0(test4, 5);\n assert(issame(test4, expected4, 5));\n\n float test5[] = {12.0, 11.0, 15.0, 13.0, 14.0};\n float expected5[] = {0.25, 0.0, 1.0, 0.5, 0.75};\n func0(test5, 5);\n assert(issame(test5, expected5, 5));\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmovss xmm1, dword ptr [rdi]\ncmp esi, 1\njle short loc_1450\nlea edx, [rsi-2]\nlea rax, [rdi+4]\nmovaps xmm0, xmm1\nlea rdx, [rdi+rdx*4+8]\nnop dword ptr [rax+00h]\nloc_1400:\nmovss xmm2, dword ptr [rax]\nadd rax, 4\nmovaps xmm3, xmm2\nmaxss xmm2, xmm0\nminss xmm3, xmm1\nmovaps xmm0, xmm2\nmovaps xmm1, xmm3\ncmp rax, rdx\njnz short loc_1400\nloc_141E:\nmovaps xmm2, xmm0\nmovsxd rsi, esi\nsubss xmm2, xmm1\nlea rax, [rdi+rsi*4]\nnop dword ptr [rax+00h]\nloc_1430:\nmovss xmm0, dword ptr [rdi]\nadd rdi, 4\nsubss xmm0, xmm1\ndivss xmm0, xmm2\nmovss dword ptr [rdi-4], xmm0\ncmp rax, rdi\njnz short loc_1430\nlocret_144A:\nretn\nloc_1450:\njnz short locret_144A\nmovaps xmm0, xmm1\njmp short loc_141E", + "ida_pseudo": "void __fastcall func0(float *a1, int a2)\n{\n float v2; // xmm1_4\n float *v3; // rax\n float v4; // xmm0_4\n float v5; // xmm2_4\n float v6; // xmm2_4\n float *v7; // rax\n float v8; // xmm0_4\n\n v2 = *a1;\n if ( a2 <= 1 )\n {\n if ( a2 != 1 )\n return;\n v4 = *a1;\n }\n else\n {\n v3 = a1 + 1;\n v4 = *a1;\n do\n {\n v5 = *v3++;\n v4 = fmaxf(v5, v4);\n v2 = fminf(v5, v2);\n }\n while ( v3 != &a1[a2 - 2 + 2] );\n }\n v6 = v4 - v2;\n v7 = &a1[a2];\n do\n {\n v8 = *a1++;\n *(a1 - 1) = (float)(v8 - v2) / v6;\n }\n while ( v7 != a1 );\n}", + "ida_strip_asm": "sub_13E0:\nendbr64\nmovss xmm1, dword ptr [rdi]\ncmp esi, 1\njle short loc_1450\nlea edx, [rsi-2]\nlea rax, [rdi+4]\nmovaps xmm0, xmm1\nlea rdx, [rdi+rdx*4+8]\nnop dword ptr [rax+00h]\nloc_1400:\nmovss xmm2, dword ptr [rax]\nadd rax, 4\nmovaps xmm3, xmm2\nmaxss xmm2, xmm0\nminss xmm3, xmm1\nmovaps xmm0, xmm2\nmovaps xmm1, xmm3\ncmp rax, rdx\njnz short loc_1400\nloc_141E:\nmovaps xmm2, xmm0\nmovsxd rsi, esi\nsubss xmm2, xmm1\nlea rax, [rdi+rsi*4]\nnop dword ptr [rax+00h]\nloc_1430:\nmovss xmm0, dword ptr [rdi]\nadd rdi, 4\nsubss xmm0, xmm1\ndivss xmm0, xmm2\nmovss dword ptr [rdi-4], xmm0\ncmp rax, rdi\njnz short loc_1430\nlocret_144A:\nretn\nloc_1450:\njnz short locret_144A\nmovaps xmm0, xmm1\njmp short loc_141E", + "ida_strip_pseudo": "void __fastcall sub_13E0(float *a1, int a2)\n{\n float v2; // xmm1_4\n float *v3; // rax\n float v4; // xmm0_4\n float v5; // xmm2_4\n float v6; // xmm2_4\n float *v7; // rax\n float v8; // xmm0_4\n\n v2 = *a1;\n if ( a2 <= 1 )\n {\n if ( a2 != 1 )\n return;\n v4 = *a1;\n }\n else\n {\n v3 = a1 + 1;\n v4 = *a1;\n do\n {\n v5 = *v3++;\n v4 = fmaxf(v5, v4);\n v2 = fminf(v5, v2);\n }\n while ( v3 != &a1[a2 - 2 + 2] );\n }\n v6 = v4 - v2;\n v7 = &a1[a2];\n do\n {\n v8 = *a1++;\n *(a1 - 1) = (float)(v8 - v2) / v6;\n }\n while ( v7 != a1 );\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_13E0(float *a1, int a2) {\n float v2;\n float *v3;\n float v4;\n float v5;\n float v6;\n float *v7;\n float v8;\n v2 = *a1;\n if (a2 <= 1) {\n if (a2 != 1) return;\n v4 = *a1;\n } else {\n v3 = a1 + 1;\n v4 = *a1;\n do {\n v5 = *v3++;\n v4 = fmaxf(v5, v4);\n v2 = fminf(v5, v2);\n } while (v3 != &a1[a2 - 2 + 2]);\n }\n v6 = v4 - v2;\n v7 = &a1[a2];\n do {\n v8 = *a1++;\n *(a1 - 1) = (float)(v8 - v2) / v6;\n } while (v7 != a1);\n}", + "ida_pseudo_norm": "void func0(float *a1, int a2) {\n float v2;\n float *v3;\n float v4;\n float v5;\n float v6;\n float *v7;\n float v8;\n v2 = *a1;\n if (a2 <= 1) {\n if (a2 != 1) return;\n v4 = *a1;\n } else {\n v3 = a1 + 1;\n v4 = *a1;\n do {\n v5 = *v3++;\n v4 = fmaxf(v5, v4);\n v2 = fminf(v5, v2);\n } while (v3 != &a1[a2 - 2 + 2]);\n }\n v6 = v4 - v2;\n v7 = &a1[a2];\n do {\n v8 = *a1++;\n *(a1 - 1) = (float)(v8 - v2) / v6;\n } while (v7 != a1);\n}" + }, + { + "index": "HumanEval-C-21", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(float *numbers, int size) {\n float min = numbers[0], max = numbers[0];\n for (int i = 1; i < size; i++) {\n if (numbers[i] < min) min = numbers[i];\n if (numbers[i] > max) max = numbers[i];\n }\n for (int i = 0; i < size; i++) {\n numbers[i] = (numbers[i] - min) / (max - min);\n }\n}", + "test": "#include \n\nint issame(float *a, float *b, int size) {\n const float EPSILON = 1e-4;\n for (int i = 0; i < size; i++) {\n if (fabs(a[i] - b[i]) > EPSILON) return 0;\n }\n return 1;\n}\n\nint main() {\n float test1[] = {2.0, 49.9};\n float expected1[] = {0.0, 1.0};\n func0(test1, 2);\n assert(issame(test1, expected1, 2));\n\n float test2[] = {100.0, 49.9};\n float expected2[] = {1.0, 0.0};\n func0(test2, 2);\n assert(issame(test2, expected2, 2));\n\n float test3[] = {1.0, 2.0, 3.0, 4.0, 5.0};\n float expected3[] = {0.0, 0.25, 0.5, 0.75, 1.0};\n func0(test3, 5);\n assert(issame(test3, expected3, 5));\n\n float test4[] = {2.0, 1.0, 5.0, 3.0, 4.0};\n float expected4[] = {0.25, 0.0, 1.0, 0.5, 0.75};\n func0(test4, 5);\n assert(issame(test4, expected4, 5));\n\n float test5[] = {12.0, 11.0, 15.0, 13.0, 14.0};\n float expected5[] = {0.25, 0.0, 1.0, 0.5, 0.75};\n func0(test5, 5);\n assert(issame(test5, expected5, 5));\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmovss xmm1, dword ptr [rdi]\nmov rcx, rdi\ncmp esi, 1\njle loc_15D8\nlea rax, [rdi+4]\nmov rdx, rdi\nlea edi, [rsi-2]\nmov r8d, esi\nlea rdi, [rcx+rdi*4+8]\nmovaps xmm0, xmm1\nnop dword ptr [rax+00000000h]\nloc_1510:\nmovss xmm2, dword ptr [rax]\nadd rax, 4\nmovaps xmm5, xmm2\nmaxss xmm2, xmm0\nminss xmm5, xmm1\nmovaps xmm0, xmm2\nmovaps xmm1, xmm5\ncmp rdi, rax\njnz short loc_1510\nlea eax, [rsi-1]\nsubss xmm2, xmm5\ncmp eax, 2\njbe loc_15E5\nmov eax, esi\nmovaps xmm4, xmm5\nmovaps xmm3, xmm2\nshr eax, 2\nshufps xmm4, xmm4, 0\nshufps xmm3, xmm3, 0\nshl rax, 4\nadd rax, rcx\nnop dword ptr [rax+rax+00000000h]\nloc_1560:\nmovups xmm0, xmmword ptr [rdx]\nadd rdx, 10h\nsubps xmm0, xmm4\ndivps xmm0, xmm3\nmovups xmmword ptr [rdx-10h], xmm0\ncmp rax, rdx\njnz short loc_1560\nmov eax, esi\nand eax, 0FFFFFFFCh\nmov edx, eax\ncmp eax, esi\njz short locret_15D4\nsub esi, eax\nmov r8d, esi\ncmp esi, 1\njz short loc_15BE\nloc_158B:\nlea rdx, [rcx+rdx*4]\nmovaps xmm3, xmm1\nmovq xmm0, qword ptr [rdx]\nshufps xmm3, xmm3, 0E0h\nsubps xmm0, xmm3\nmovaps xmm3, xmm2\nshufps xmm3, xmm3, 0E0h\nmovhps xmm3, cs:qword_20C8\ndivps xmm0, xmm3\nmovlps qword ptr [rdx], xmm0\ntest r8b, 1\njz short locret_15D4\nand r8d, 0FFFFFFFEh\nadd eax, r8d\nloc_15BE:\ncdqe\nlea rax, [rcx+rax*4]\nmovss xmm0, dword ptr [rax]\nsubss xmm0, xmm1\ndivss xmm0, xmm2\nmovss dword ptr [rax], xmm0\nlocret_15D4:\nretn\nloc_15D8:\njnz short locret_15D4\nmovaps xmm2, xmm1\nxor eax, eax\nsubss xmm2, xmm1\njmp short loc_15BE\nloc_15E5:\nxor edx, edx\nxor eax, eax\njmp short loc_158B", + "ida_pseudo": "void __fastcall func0(float *a1, int a2)\n{\n float v2; // xmm1_4\n unsigned int *v4; // rax\n __m128 *v5; // rdx\n int v6; // r8d\n __int64 v7; // rdi\n float v8; // xmm0_4\n __m128 v9; // xmm2\n __m128 v10; // xmm5\n __m128 v11; // xmm4\n __m128 v12; // xmm3\n __m128 v13; // xmm0\n signed int v14; // eax\n __int64 v15; // rdx\n\n v2 = *a1;\n if ( a2 <= 1 )\n {\n if ( a2 == 1 )\n {\n v14 = 0;\n v9.m128_f32[0] = v2 - v2;\n goto LABEL_11;\n }\n }\n else\n {\n v4 = (unsigned int *)(a1 + 1);\n v5 = (__m128 *)a1;\n v6 = a2;\n v7 = (__int64)&a1[a2 - 2 + 2];\n v8 = v2;\n do\n {\n v9 = (__m128)*v4++;\n v10 = v9;\n v9.m128_f32[0] = fmaxf(v9.m128_f32[0], v8);\n v10.m128_f32[0] = fminf(v10.m128_f32[0], v2);\n v8 = v9.m128_f32[0];\n v2 = v10.m128_f32[0];\n }\n while ( (unsigned int *)v7 != v4 );\n v9.m128_f32[0] = v9.m128_f32[0] - v10.m128_f32[0];\n if ( (unsigned int)(a2 - 1) <= 2 )\n {\n v15 = 0LL;\n v14 = 0;\n goto LABEL_9;\n }\n v11 = _mm_shuffle_ps(v10, v10, 0);\n v12 = _mm_shuffle_ps(v9, v9, 0);\n do\n {\n v13 = *v5++;\n v5[-1] = _mm_div_ps(_mm_sub_ps(v13, v11), v12);\n }\n while ( &a1[4 * ((unsigned int)a2 >> 2)] != (float *)v5 );\n v14 = a2 & 0xFFFFFFFC;\n v15 = a2 & 0xFFFFFFFC;\n if ( (a2 & 0xFFFFFFFC) != a2 )\n {\n v6 = a2 - v14;\n if ( a2 - v14 != 1 )\n {\nLABEL_9:\n _mm_storel_ps(\n (double *)&a1[v15],\n _mm_div_ps(\n _mm_sub_ps((__m128)_mm_loadl_epi64((const __m128i *)&a1[v15]), _mm_shuffle_ps(v10, v10, 224)),\n _mm_loadh_ps((const double *)&qword_20C8)));\n if ( (v6 & 1) == 0 )\n return;\n v14 += v6 & 0xFFFFFFFE;\n }\nLABEL_11:\n a1[v14] = (float)(a1[v14] - v2) / v9.m128_f32[0];\n }\n }\n}", + "ida_strip_asm": "sub_14E0:\nendbr64\nmovss xmm1, dword ptr [rdi]\nmov rcx, rdi\ncmp esi, 1\njle loc_15D8\nlea rax, [rdi+4]\nmov rdx, rdi\nlea edi, [rsi-2]\nmov r8d, esi\nlea rdi, [rcx+rdi*4+8]\nmovaps xmm0, xmm1\nnop dword ptr [rax+00000000h]\nloc_1510:\nmovss xmm2, dword ptr [rax]\nadd rax, 4\nmovaps xmm5, xmm2\nmaxss xmm2, xmm0\nminss xmm5, xmm1\nmovaps xmm0, xmm2\nmovaps xmm1, xmm5\ncmp rdi, rax\njnz short loc_1510\nlea eax, [rsi-1]\nsubss xmm2, xmm5\ncmp eax, 2\njbe loc_15E5\nmov eax, esi\nmovaps xmm4, xmm5\nmovaps xmm3, xmm2\nshr eax, 2\nshufps xmm4, xmm4, 0\nshufps xmm3, xmm3, 0\nshl rax, 4\nadd rax, rcx\nnop dword ptr [rax+rax+00000000h]\nloc_1560:\nmovups xmm0, xmmword ptr [rdx]\nadd rdx, 10h\nsubps xmm0, xmm4\ndivps xmm0, xmm3\nmovups xmmword ptr [rdx-10h], xmm0\ncmp rax, rdx\njnz short loc_1560\nmov eax, esi\nand eax, 0FFFFFFFCh\nmov edx, eax\ncmp eax, esi\njz short locret_15D4\nsub esi, eax\nmov r8d, esi\ncmp esi, 1\njz short loc_15BE\nloc_158B:\nlea rdx, [rcx+rdx*4]\nmovaps xmm3, xmm1\nmovq xmm0, qword ptr [rdx]\nshufps xmm3, xmm3, 0E0h\nsubps xmm0, xmm3\nmovaps xmm3, xmm2\nshufps xmm3, xmm3, 0E0h\nmovhps xmm3, cs:qword_20C8\ndivps xmm0, xmm3\nmovlps qword ptr [rdx], xmm0\ntest r8b, 1\njz short locret_15D4\nand r8d, 0FFFFFFFEh\nadd eax, r8d\nloc_15BE:\ncdqe\nlea rax, [rcx+rax*4]\nmovss xmm0, dword ptr [rax]\nsubss xmm0, xmm1\ndivss xmm0, xmm2\nmovss dword ptr [rax], xmm0\nlocret_15D4:\nretn\nloc_15D8:\njnz short locret_15D4\nmovaps xmm2, xmm1\nxor eax, eax\nsubss xmm2, xmm1\njmp short loc_15BE\nloc_15E5:\nxor edx, edx\nxor eax, eax\njmp short loc_158B", + "ida_strip_pseudo": "void __fastcall sub_14E0(float *a1, int a2)\n{\n float v2; // xmm1_4\n unsigned int *v4; // rax\n __m128 *v5; // rdx\n int v6; // r8d\n __int64 v7; // rdi\n float v8; // xmm0_4\n __m128 v9; // xmm2\n __m128 v10; // xmm5\n __m128 v11; // xmm4\n __m128 v12; // xmm3\n __m128 v13; // xmm0\n signed int v14; // eax\n __int64 v15; // rdx\n\n v2 = *a1;\n if ( a2 <= 1 )\n {\n if ( a2 == 1 )\n {\n v14 = 0;\n v9.m128_f32[0] = v2 - v2;\n goto LABEL_11;\n }\n }\n else\n {\n v4 = (unsigned int *)(a1 + 1);\n v5 = (__m128 *)a1;\n v6 = a2;\n v7 = (__int64)&a1[a2 - 2 + 2];\n v8 = v2;\n do\n {\n v9 = (__m128)*v4++;\n v10 = v9;\n v9.m128_f32[0] = fmaxf(v9.m128_f32[0], v8);\n v10.m128_f32[0] = fminf(v10.m128_f32[0], v2);\n v8 = v9.m128_f32[0];\n v2 = v10.m128_f32[0];\n }\n while ( (unsigned int *)v7 != v4 );\n v9.m128_f32[0] = v9.m128_f32[0] - v10.m128_f32[0];\n if ( (unsigned int)(a2 - 1) <= 2 )\n {\n v15 = 0LL;\n v14 = 0;\n goto LABEL_9;\n }\n v11 = _mm_shuffle_ps(v10, v10, 0);\n v12 = _mm_shuffle_ps(v9, v9, 0);\n do\n {\n v13 = *v5++;\n v5[-1] = _mm_div_ps(_mm_sub_ps(v13, v11), v12);\n }\n while ( &a1[4 * ((unsigned int)a2 >> 2)] != (float *)v5 );\n v14 = a2 & 0xFFFFFFFC;\n v15 = a2 & 0xFFFFFFFC;\n if ( (a2 & 0xFFFFFFFC) != a2 )\n {\n v6 = a2 - v14;\n if ( a2 - v14 != 1 )\n {\nLABEL_9:\n _mm_storel_ps(\n (double *)&a1[v15],\n _mm_div_ps(\n _mm_sub_ps((__m128)_mm_loadl_epi64((const __m128i *)&a1[v15]), _mm_shuffle_ps(v10, v10, 224)),\n _mm_loadh_ps((const double *)&qword_20C8)));\n if ( (v6 & 1) == 0 )\n return;\n v14 += v6 & 0xFFFFFFFE;\n }\nLABEL_11:\n a1[v14] = (float)(a1[v14] - v2) / v9.m128_f32[0];\n }\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_14E0(float *a1, int a2) {\n float v2;\n unsigned int *v4;\n __m128 *v5;\n int v6;\n long long v7;\n float v8;\n __m128 v9;\n __m128 v10;\n __m128 v11;\n __m128 v12;\n __m128 v13;\n signed int v14;\n long long v15;\n v2 = *a1;\n if (a2 <= 1) {\n if (a2 == 1) {\n v14 = 0;\n v9.m128_f32[0] = v2 - v2;\n goto LABEL_11;\n }\n } else {\n v4 = (unsigned int *)(a1 + 1);\n v5 = (__m128 *)a1;\n v6 = a2;\n v7 = (long long)&a1[a2 - 2 + 2];\n v8 = v2;\n do {\n v9 = (__m128)*v4++;\n v10 = v9;\n v9.m128_f32[0] = fmaxf(v9.m128_f32[0], v8);\n v10.m128_f32[0] = fminf(v10.m128_f32[0], v2);\n v8 = v9.m128_f32[0];\n v2 = v10.m128_f32[0];\n } while ((unsigned int *)v7 != v4);\n v9.m128_f32[0] = v9.m128_f32[0] - v10.m128_f32[0];\n if ((unsigned int)(a2 - 1) <= 2) {\n v15 = 0LL;\n v14 = 0;\n goto LABEL_9;\n }\n v11 = _mm_shuffle_ps(v10, v10, 0);\n v12 = _mm_shuffle_ps(v9, v9, 0);\n do {\n v13 = *v5++;\n v5[-1] = _mm_div_ps(_mm_sub_ps(v13, v11), v12);\n } while (&a1[4 * ((unsigned int)a2 >> 2)] != (float *)v5);\n v14 = a2 & 4294967292;\n v15 = a2 & 4294967292;\n if ((a2 & 4294967292) != a2) {\n v6 = a2 - v14;\n if (a2 - v14 != 1) {\n LABEL_9:\n _mm_storel_ps(\n (double *)&a1[v15],\n _mm_div_ps(\n _mm_sub_ps((__m128)_mm_loadl_epi64((const __m128i *)&a1[v15]),\n _mm_shuffle_ps(v10, v10, 224)),\n _mm_loadh_ps((const double *)&qword_20C8)));\n if ((v6 & 1) == 0) return;\n v14 += v6 & 4294967294;\n }\n LABEL_11:\n a1[v14] = (float)(a1[v14] - v2) / v9.m128_f32[0];\n }\n }\n}", + "ida_pseudo_norm": "void func0(float *a1, int a2) {\n float v2;\n unsigned int *v4;\n __m128 *v5;\n int v6;\n long long v7;\n float v8;\n __m128 v9;\n __m128 v10;\n __m128 v11;\n __m128 v12;\n __m128 v13;\n signed int v14;\n long long v15;\n v2 = *a1;\n if (a2 <= 1) {\n if (a2 == 1) {\n v14 = 0;\n v9.m128_f32[0] = v2 - v2;\n goto LABEL_11;\n }\n } else {\n v4 = (unsigned int *)(a1 + 1);\n v5 = (__m128 *)a1;\n v6 = a2;\n v7 = (long long)&a1[a2 - 2 + 2];\n v8 = v2;\n do {\n v9 = (__m128)*v4++;\n v10 = v9;\n v9.m128_f32[0] = fmaxf(v9.m128_f32[0], v8);\n v10.m128_f32[0] = fminf(v10.m128_f32[0], v2);\n v8 = v9.m128_f32[0];\n v2 = v10.m128_f32[0];\n } while ((unsigned int *)v7 != v4);\n v9.m128_f32[0] = v9.m128_f32[0] - v10.m128_f32[0];\n if ((unsigned int)(a2 - 1) <= 2) {\n v15 = 0LL;\n v14 = 0;\n goto LABEL_9;\n }\n v11 = _mm_shuffle_ps(v10, v10, 0);\n v12 = _mm_shuffle_ps(v9, v9, 0);\n do {\n v13 = *v5++;\n v5[-1] = _mm_div_ps(_mm_sub_ps(v13, v11), v12);\n } while (&a1[4 * ((unsigned int)a2 >> 2)] != (float *)v5);\n v14 = a2 & 4294967292;\n v15 = a2 & 4294967292;\n if ((a2 & 4294967292) != a2) {\n v6 = a2 - v14;\n if (a2 - v14 != 1) {\n LABEL_9:\n _mm_storel_ps(\n (double *)&a1[v15],\n _mm_div_ps(\n _mm_sub_ps((__m128)_mm_loadl_epi64((const __m128i *)&a1[v15]),\n _mm_shuffle_ps(v10, v10, 224)),\n _mm_loadh_ps((const double *)&qword_20C8)));\n if ((v6 & 1) == 0) return;\n v14 += v6 & 4294967294;\n }\n LABEL_11:\n a1[v14] = (float)(a1[v14] - v2) / v9.m128_f32[0];\n }\n }\n}" + }, + { + "index": "HumanEval-C-22", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n#include \n", + "func": "int *func0(const char *values, int *size) {\n static int out[256];\n int count = 0;\n const char *start = values;\n char *end;\n while (*start) {\n while (*start && !isdigit(*start) && *start != '-') {\n start++;\n }\n if (!*start) {\n break;\n }\n int val = (int)strtol(start, &end, 10);\n if (start != end && (*end == ',' || *end == '\\0')) {\n out[count++] = val;\n } else {\n while (*end && *end != ',') {\n end++;\n }\n }\n start = end;\n }\n *size = count;\n return out;\n}", + "test": "#include \n#include \n#include \n#include \n#include \n\nint issame(int *a, int size_a, int *b, int size_b) {\n if (size_a != size_b) return 0;\n for (int i = 0; i < size_a; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int size;\n\n // Test 1\n int *result1 = func0(\"\", &size);\n assert(issame(result1, size, (const int[]){}, 0));\n\n // Test 2\n int *result2 = func0(\"4,,23.2,9,adasd\", &size);\n assert(issame(result2, size, (const int[]){4, 9}, 2));\n\n // Test 3\n int *result3 = func0(\"3,c,3,3,a,b\", &size);\n assert(issame(result3, size, (const int[]){3, 3, 3}, 3));\n\n printf(\"All tests passed.\\n\");\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_30], rsi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_20], 0\nmov rax, [rbp+var_28]\nmov [rbp+nptr], rax\njmp loc_12D9\nloc_1200:\nadd [rbp+nptr], 1\nloc_1205:\nmov rax, [rbp+nptr]\nmovzx eax, byte ptr [rax]\ntest al, al\njz short loc_1243\ncall ___ctype_b_loc\nmov rdx, [rax]\nmov rax, [rbp+nptr]\nmovzx eax, byte ptr [rax]\nmovsx rax, al\nadd rax, rax\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 800h\ntest eax, eax\njnz short loc_1243\nmov rax, [rbp+nptr]\nmovzx eax, byte ptr [rax]\ncmp al, 2Dh ; '-'\njnz short loc_1200\nloc_1243:\nmov rax, [rbp+nptr]\nmovzx eax, byte ptr [rax]\ntest al, al\njz loc_12EA\nlea rcx, [rbp+endptr]\nmov rax, [rbp+nptr]\nmov edx, 0Ah; base\nmov rsi, rcx; endptr\nmov rdi, rax; nptr\ncall _strtol\nmov [rbp+var_1C], eax\nmov rax, [rbp+endptr]\ncmp [rbp+nptr], rax\njz short loc_12BB\nmov rax, [rbp+endptr]\nmovzx eax, byte ptr [rax]\ncmp al, 2Ch ; ','\njz short loc_128D\nmov rax, [rbp+endptr]\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_12BB\nloc_128D:\nmov eax, [rbp+var_20]\nlea edx, [rax+1]\nmov [rbp+var_20], edx\ncdqe\nlea rcx, ds:0[rax*4]\nlea rdx, out_1\nmov eax, [rbp+var_1C]\nmov [rcx+rdx], eax\njmp short loc_12D1\nloc_12AF:\nmov rax, [rbp+endptr]\nadd rax, 1\nmov [rbp+endptr], rax\nloc_12BB:\nmov rax, [rbp+endptr]\nmovzx eax, byte ptr [rax]\ntest al, al\njz short loc_12D1\nmov rax, [rbp+endptr]\nmovzx eax, byte ptr [rax]\ncmp al, 2Ch ; ','\njnz short loc_12AF\nloc_12D1:\nmov rax, [rbp+endptr]\nmov [rbp+nptr], rax\nloc_12D9:\nmov rax, [rbp+nptr]\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_1205\njmp short loc_12EB\nloc_12EA:\nnop\nloc_12EB:\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_20]\nmov [rax], edx\nlea rax, out_1\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_130F\ncall ___stack_chk_fail\nlocret_130F:\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(char *a1, _DWORD *a2)\n{\n int v2; // eax\n int v4; // [rsp+10h] [rbp-20h]\n int v5; // [rsp+14h] [rbp-1Ch]\n char *endptr; // [rsp+18h] [rbp-18h] BYREF\n char *nptr; // [rsp+20h] [rbp-10h]\n unsigned __int64 v8; // [rsp+28h] [rbp-8h]\n\n v8 = __readfsqword(0x28u);\n v4 = 0;\n for ( nptr = a1; *nptr; nptr = endptr )\n {\n while ( *nptr && ((*__ctype_b_loc())[*nptr] & 0x800) == 0 && *nptr != 45 )\n ++nptr;\n if ( !*nptr )\n break;\n v5 = strtol(nptr, &endptr, 10);\n if ( nptr == endptr || *endptr != 44 && *endptr )\n {\n while ( *endptr && *endptr != 44 )\n ++endptr;\n }\n else\n {\n v2 = v4++;\n out_1[v2] = v5;\n }\n }\n *a2 = v4;\n return out_1;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_30], rsi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_20], 0\nmov rax, [rbp+var_28]\nmov [rbp+nptr], rax\njmp loc_12D9\nloc_1200:\nadd [rbp+nptr], 1\nloc_1205:\nmov rax, [rbp+nptr]\nmovzx eax, byte ptr [rax]\ntest al, al\njz short loc_1243\ncall ___ctype_b_loc\nmov rdx, [rax]\nmov rax, [rbp+nptr]\nmovzx eax, byte ptr [rax]\nmovsx rax, al\nadd rax, rax\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 800h\ntest eax, eax\njnz short loc_1243\nmov rax, [rbp+nptr]\nmovzx eax, byte ptr [rax]\ncmp al, 2Dh ; '-'\njnz short loc_1200\nloc_1243:\nmov rax, [rbp+nptr]\nmovzx eax, byte ptr [rax]\ntest al, al\njz loc_12EA\nlea rcx, [rbp+endptr]\nmov rax, [rbp+nptr]\nmov edx, 0Ah; base\nmov rsi, rcx; endptr\nmov rdi, rax; nptr\ncall _strtol\nmov [rbp+var_1C], eax\nmov rax, [rbp+endptr]\ncmp [rbp+nptr], rax\njz short loc_12BB\nmov rax, [rbp+endptr]\nmovzx eax, byte ptr [rax]\ncmp al, 2Ch ; ','\njz short loc_128D\nmov rax, [rbp+endptr]\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_12BB\nloc_128D:\nmov eax, [rbp+var_20]\nlea edx, [rax+1]\nmov [rbp+var_20], edx\ncdqe\nlea rcx, ds:0[rax*4]\nlea rdx, unk_4040\nmov eax, [rbp+var_1C]\nmov [rcx+rdx], eax\njmp short loc_12D1\nloc_12AF:\nmov rax, [rbp+endptr]\nadd rax, 1\nmov [rbp+endptr], rax\nloc_12BB:\nmov rax, [rbp+endptr]\nmovzx eax, byte ptr [rax]\ntest al, al\njz short loc_12D1\nmov rax, [rbp+endptr]\nmovzx eax, byte ptr [rax]\ncmp al, 2Ch ; ','\njnz short loc_12AF\nloc_12D1:\nmov rax, [rbp+endptr]\nmov [rbp+nptr], rax\nloc_12D9:\nmov rax, [rbp+nptr]\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_1205\njmp short loc_12EB\nloc_12EA:\nnop\nloc_12EB:\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_20]\nmov [rax], edx\nlea rax, unk_4040\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_130F\ncall ___stack_chk_fail\nlocret_130F:\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11C9(char *a1, _DWORD *a2)\n{\n int v2; // eax\n int v4; // [rsp+10h] [rbp-20h]\n int v5; // [rsp+14h] [rbp-1Ch]\n char *endptr; // [rsp+18h] [rbp-18h] BYREF\n char *nptr; // [rsp+20h] [rbp-10h]\n unsigned __int64 v8; // [rsp+28h] [rbp-8h]\n\n v8 = __readfsqword(0x28u);\n v4 = 0;\n for ( nptr = a1; *nptr; nptr = endptr )\n {\n while ( *nptr && ((*__ctype_b_loc())[*nptr] & 0x800) == 0 && *nptr != 45 )\n ++nptr;\n if ( !*nptr )\n break;\n v5 = strtol(nptr, &endptr, 10);\n if ( nptr == endptr || *endptr != 44 && *endptr )\n {\n while ( *endptr && *endptr != 44 )\n ++endptr;\n }\n else\n {\n v2 = v4++;\n dword_4040[v2] = v5;\n }\n }\n *a2 = v4;\n return dword_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11C9(char *a1, uint32_t *a2) {\n int v2;\n int v4;\n int v5;\n char *endptr;\n char *nptr;\n unsigned long long v8;\n v8 = __readfsqword(40u);\n v4 = 0;\n for (nptr = a1; *nptr; nptr = endptr) {\n while (*nptr && ((*__ctype_b_loc())[*nptr] & 2048) == 0 && *nptr != 45)\n ++nptr;\n if (!*nptr) break;\n v5 = strtol(nptr, &endptr, 10);\n if (nptr == endptr || *endptr != 44 && *endptr) {\n while (*endptr && *endptr != 44) ++endptr;\n } else {\n v2 = v4++;\n dword_4040[v2] = v5;\n }\n }\n *a2 = v4;\n return dword_4040;\n}", + "ida_pseudo_norm": "uint32_t *func0(char *a1, uint32_t *a2) {\n int v2;\n int v4;\n int v5;\n char *endptr;\n char *nptr;\n unsigned long long v8;\n v8 = __readfsqword(40u);\n v4 = 0;\n for (nptr = a1; *nptr; nptr = endptr) {\n while (*nptr && ((*__ctype_b_loc())[*nptr] & 2048) == 0 && *nptr != 45)\n ++nptr;\n if (!*nptr) break;\n v5 = strtol(nptr, &endptr, 10);\n if (nptr == endptr || *endptr != 44 && *endptr) {\n while (*endptr && *endptr != 44) ++endptr;\n } else {\n v2 = v4++;\n out_1[v2] = v5;\n }\n }\n *a2 = v4;\n return out_1;\n}" + }, + { + "index": "HumanEval-C-22", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n#include \n", + "func": "int *func0(const char *values, int *size) {\n static int out[256];\n int count = 0;\n const char *start = values;\n char *end;\n while (*start) {\n while (*start && !isdigit(*start) && *start != '-') {\n start++;\n }\n if (!*start) {\n break;\n }\n int val = (int)strtol(start, &end, 10);\n if (start != end && (*end == ',' || *end == '\\0')) {\n out[count++] = val;\n } else {\n while (*end && *end != ',') {\n end++;\n }\n }\n start = end;\n }\n *size = count;\n return out;\n}", + "test": "#include \n#include \n#include \n#include \n#include \n\nint issame(int *a, int size_a, int *b, int size_b) {\n if (size_a != size_b) return 0;\n for (int i = 0; i < size_a; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int size;\n\n // Test 1\n int *result1 = func0(\"\", &size);\n assert(issame(result1, size, (const int[]){}, 0));\n\n // Test 2\n int *result2 = func0(\"4,,23.2,9,adasd\", &size);\n assert(issame(result2, size, (const int[]){4, 9}, 2));\n\n // Test 3\n int *result3 = func0(\"3,c,3,3,a,b\", &size);\n assert(issame(result3, size, (const int[]){3, 3, 3}, 3));\n\n printf(\"All tests passed.\\n\");\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 10h\nmov rbp, rdi\nmov r14, rsi\nmov rax, fs:28h\nmov [rsp+38h+var_30], rax\nxor eax, eax\nmov r12d, 0\nlea r13, out_1\ncmp byte ptr [rdi], 0\njnz short loc_123F\njmp short loc_126B\nloc_1203:\nmov rsi, rsp; endptr\nmov edx, 0Ah; base\nmov rdi, rbp; nptr\ncall _strtol\nmov rdx, [rsp+38h+var_38]\ncmp rdx, rbp\njz short loc_1292\nmovzx ecx, byte ptr [rdx]\ncmp cl, 2Ch ; ','\njz short loc_1228\ntest cl, cl\njnz short loc_129D\nloc_1228:\nmovsxd rdx, r12d\nmov [r13+rdx*4+0], eax\nlea r12d, [r12+1]\nloc_1235:\nmov rbp, [rsp+38h+var_38]\ncmp byte ptr [rbp+0], 0\njz short loc_126B\nloc_123F:\nmovzx ebx, byte ptr [rbp+0]\ntest bl, bl\njz short loc_126B\ncall ___ctype_b_loc\nmov rdx, [rax]\nloc_124F:\nmovsx rax, bl\ntest byte ptr [rdx+rax*2+1], 8\njnz short loc_1203\ncmp bl, 2Dh ; '-'\njz short loc_1203\nadd rbp, 1\nmovzx ebx, byte ptr [rbp+0]\ntest bl, bl\njnz short loc_124F\nloc_126B:\nmov [r14], r12d\nmov rax, [rsp+38h+var_30]\nsub rax, fs:28h\njnz short loc_12BA\nlea rax, out_1\nadd rsp, 10h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1292:\nmovzx eax, byte ptr [rdx]\ntest al, al\njz short loc_1235\ncmp al, 2Ch ; ','\njz short loc_1235\nloc_129D:\nlea rax, [rdx+1]\nloc_12A1:\nmov [rsp+38h+var_38], rax\nmovzx edx, byte ptr [rax]\nadd rax, 1\ntest dl, dl\njz short loc_1235\ncmp dl, 2Ch ; ','\njnz short loc_12A1\njmp loc_1235\nloc_12BA:\ncall ___stack_chk_fail", + "ida_pseudo": "_DWORD *__fastcall func0(char *nptr, _DWORD *a2)\n{\n char *v2; // rbp\n int v3; // r12d\n int v4; // eax\n char v5; // bl\n const unsigned __int16 *v6; // rdx\n char *v8; // rax\n char v9; // dl\n char *v10[7]; // [rsp+0h] [rbp-38h] BYREF\n\n v2 = nptr;\n v10[1] = (char *)__readfsqword(0x28u);\n v3 = 0;\n if ( *nptr )\n {\n do\n {\n v5 = *v2;\n if ( !*v2 )\n break;\n v6 = *__ctype_b_loc();\n while ( (v6[v5] & 0x800) == 0 && v5 != 45 )\n {\n v5 = *++v2;\n if ( !*v2 )\n goto LABEL_13;\n }\n v4 = strtol(v2, v10, 10);\n if ( v10[0] == v2 )\n {\n if ( *v10[0] && *v10[0] != 44 )\n {\nLABEL_16:\n v8 = v10[0] + 1;\n do\n {\n v10[0] = v8;\n v9 = *v8++;\n }\n while ( v9 && v9 != 44 );\n }\n }\n else\n {\n if ( *v10[0] != 44 && *v10[0] )\n goto LABEL_16;\n out_1[v3++] = v4;\n }\n v2 = v10[0];\n }\n while ( *v10[0] );\n }\nLABEL_13:\n *a2 = v3;\n return out_1;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 10h\nmov rbp, rdi\nmov r14, rsi\nmov rax, fs:28h\nmov [rsp+38h+var_30], rax\nxor eax, eax\nmov r12d, 0\nlea r13, unk_4040\ncmp byte ptr [rdi], 0\njnz short loc_123F\njmp short loc_126B\nloc_1203:\nmov rsi, rsp; endptr\nmov edx, 0Ah; base\nmov rdi, rbp; nptr\ncall _strtol\nmov rdx, [rsp+38h+var_38]\ncmp rdx, rbp\njz short loc_1292\nmovzx ecx, byte ptr [rdx]\ncmp cl, 2Ch ; ','\njz short loc_1228\ntest cl, cl\njnz short loc_129D\nloc_1228:\nmovsxd rdx, r12d\nmov [r13+rdx*4+0], eax\nlea r12d, [r12+1]\nloc_1235:\nmov rbp, [rsp+38h+var_38]\ncmp byte ptr [rbp+0], 0\njz short loc_126B\nloc_123F:\nmovzx ebx, byte ptr [rbp+0]\ntest bl, bl\njz short loc_126B\ncall ___ctype_b_loc\nmov rdx, [rax]\nloc_124F:\nmovsx rax, bl\ntest byte ptr [rdx+rax*2+1], 8\njnz short loc_1203\ncmp bl, 2Dh ; '-'\njz short loc_1203\nadd rbp, 1\nmovzx ebx, byte ptr [rbp+0]\ntest bl, bl\njnz short loc_124F\nloc_126B:\nmov [r14], r12d\nmov rax, [rsp+38h+var_30]\nsub rax, fs:28h\njnz short loc_12BA\nlea rax, unk_4040\nadd rsp, 10h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1292:\nmovzx eax, byte ptr [rdx]\ntest al, al\njz short loc_1235\ncmp al, 2Ch ; ','\njz short loc_1235\nloc_129D:\nlea rax, [rdx+1]\nloc_12A1:\nmov [rsp+38h+var_38], rax\nmovzx edx, byte ptr [rax]\nadd rax, 1\ntest dl, dl\njz short loc_1235\ncmp dl, 2Ch ; ','\njnz short loc_12A1\njmp loc_1235\nloc_12BA:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11C9(char *nptr, _DWORD *a2)\n{\n char *v2; // rbp\n int v3; // r12d\n int v4; // eax\n char v5; // bl\n const unsigned __int16 *v6; // rdx\n char *v8; // rax\n char v9; // dl\n char *v10[7]; // [rsp+0h] [rbp-38h] BYREF\n\n v2 = nptr;\n v10[1] = (char *)__readfsqword(0x28u);\n v3 = 0;\n if ( *nptr )\n {\n do\n {\n v5 = *v2;\n if ( !*v2 )\n break;\n v6 = *__ctype_b_loc();\n while ( (v6[v5] & 0x800) == 0 && v5 != 45 )\n {\n v5 = *++v2;\n if ( !*v2 )\n goto LABEL_13;\n }\n v4 = strtol(v2, v10, 10);\n if ( v10[0] == v2 )\n {\n if ( *v10[0] && *v10[0] != 44 )\n {\nLABEL_16:\n v8 = v10[0] + 1;\n do\n {\n v10[0] = v8;\n v9 = *v8++;\n }\n while ( v9 && v9 != 44 );\n }\n }\n else\n {\n if ( *v10[0] != 44 && *v10[0] )\n goto LABEL_16;\n dword_4040[v3++] = v4;\n }\n v2 = v10[0];\n }\n while ( *v10[0] );\n }\nLABEL_13:\n *a2 = v3;\n return dword_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11C9(char *nptr, uint32_t *a2) {\n char *v2;\n int v3;\n int v4;\n char v5;\n const unsigned short *v6;\n char *v8;\n char v9;\n char *v10[7];\n v2 = nptr;\n v10[1] = (char *)__readfsqword(40u);\n v3 = 0;\n if (*nptr) {\n do {\n v5 = *v2;\n if (!*v2) break;\n v6 = *__ctype_b_loc();\n while ((v6[v5] & 2048) == 0 && v5 != 45) {\n v5 = *++v2;\n if (!*v2) goto LABEL_13;\n }\n v4 = strtol(v2, v10, 10);\n if (v10[0] == v2) {\n if (*v10[0] && *v10[0] != 44) {\n LABEL_16:\n v8 = v10[0] + 1;\n do {\n v10[0] = v8;\n v9 = *v8++;\n } while (v9 && v9 != 44);\n }\n } else {\n if (*v10[0] != 44 && *v10[0]) goto LABEL_16;\n dword_4040[v3++] = v4;\n }\n v2 = v10[0];\n } while (*v10[0]);\n }\nLABEL_13:\n *a2 = v3;\n return dword_4040;\n}", + "ida_pseudo_norm": "uint32_t *func0(char *nptr, uint32_t *a2) {\n char *v2;\n int v3;\n int v4;\n char v5;\n const unsigned short *v6;\n char *v8;\n char v9;\n char *v10[7];\n v2 = nptr;\n v10[1] = (char *)__readfsqword(40u);\n v3 = 0;\n if (*nptr) {\n do {\n v5 = *v2;\n if (!*v2) break;\n v6 = *__ctype_b_loc();\n while ((v6[v5] & 2048) == 0 && v5 != 45) {\n v5 = *++v2;\n if (!*v2) goto LABEL_13;\n }\n v4 = strtol(v2, v10, 10);\n if (v10[0] == v2) {\n if (*v10[0] && *v10[0] != 44) {\n LABEL_16:\n v8 = v10[0] + 1;\n do {\n v10[0] = v8;\n v9 = *v8++;\n } while (v9 && v9 != 44);\n }\n } else {\n if (*v10[0] != 44 && *v10[0]) goto LABEL_16;\n out_1[v3++] = v4;\n }\n v2 = v10[0];\n } while (*v10[0]);\n }\nLABEL_13:\n *a2 = v3;\n return out_1;\n}" + }, + { + "index": "HumanEval-C-22", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n#include \n", + "func": "int *func0(const char *values, int *size) {\n static int out[256];\n int count = 0;\n const char *start = values;\n char *end;\n while (*start) {\n while (*start && !isdigit(*start) && *start != '-') {\n start++;\n }\n if (!*start) {\n break;\n }\n int val = (int)strtol(start, &end, 10);\n if (start != end && (*end == ',' || *end == '\\0')) {\n out[count++] = val;\n } else {\n while (*end && *end != ',') {\n end++;\n }\n }\n start = end;\n }\n *size = count;\n return out;\n}", + "test": "#include \n#include \n#include \n#include \n#include \n\nint issame(int *a, int size_a, int *b, int size_b) {\n if (size_a != size_b) return 0;\n for (int i = 0; i < size_a; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int size;\n\n // Test 1\n int *result1 = func0(\"\", &size);\n assert(issame(result1, size, (const int[]){}, 0));\n\n // Test 2\n int *result2 = func0(\"4,,23.2,9,adasd\", &size);\n assert(issame(result2, size, (const int[]){4, 9}, 2));\n\n // Test 3\n int *result3 = func0(\"3,c,3,3,a,b\", &size);\n assert(issame(result3, size, (const int[]){3, 3, 3}, 3));\n\n printf(\"All tests passed.\\n\");\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\nmov r15, rsi\npush r14\nlea r14, out_1\npush r13\npush r12\nxor r12d, r12d\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 18h\nmovzx ebx, byte ptr [rdi]\nmov rax, fs:28h\nmov [rsp+48h+var_40], rax\nxor eax, eax\nmov r13, rsp\ntest bl, bl\njz short loc_1420\nnop dword ptr [rax+00h]\nloc_13B0:\ncall ___ctype_b_loc\nmov rdx, [rax]\njmp short loc_13D1\nloc_13C0:\ncmp bl, 2Dh ; '-'\njz short loc_13DC\nmovzx ebx, byte ptr [rbp+1]\nadd rbp, 1\ntest bl, bl\njz short loc_1420\nloc_13D1:\nmovsx rax, bl\ntest byte ptr [rdx+rax*2+1], 8\njz short loc_13C0\nloc_13DC:\nmov edx, 0Ah; base\nmov rsi, r13; endptr\nmov rdi, rbp; nptr\ncall _strtol\nmov rdx, [rsp+48h+var_48]\ncmp rdx, rbp\njz short loc_1448\nmovzx ecx, byte ptr [rdx]\ncmp cl, 2Ch ; ','\njz short loc_1401\ntest cl, cl\njnz short loc_1455\nloc_1401:\nmovsxd rcx, r12d\nmov rbp, rdx\nadd r12d, 1\nmov [r14+rcx*4], eax\nmovzx ebx, byte ptr [rdx]\nloc_1412:\ntest bl, bl\njnz short loc_13B0\nnop word ptr [rax+rax+00000000h]\nloc_1420:\nmov [r15], r12d\nmov rax, [rsp+48h+var_40]\nsub rax, fs:28h\njnz short loc_1479\nadd rsp, 18h\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1448:\nmovzx ebx, byte ptr [rbp+0]\ntest bl, bl\njz short loc_1420\ncmp bl, 2Ch ; ','\njz short loc_1412\nloc_1455:\nlea rax, [rdx+1]\njmp short loc_1465\nloc_1460:\ncmp bl, 2Ch ; ','\njz short loc_1412\nloc_1465:\nmov [rsp+48h+var_48], rax\nmovzx ebx, byte ptr [rax]\nmov rbp, rax\nadd rax, 1\ntest bl, bl\njnz short loc_1460\njmp short loc_1420\nloc_1479:\ncall ___stack_chk_fail", + "ida_pseudo": "_DWORD *__fastcall func0(char *nptr, _DWORD *a2)\n{\n int v2; // r12d\n const char *v3; // rbp\n char v4; // bl\n const unsigned __int16 *v5; // rdx\n int v6; // eax\n char *v7; // rdx\n __int64 v8; // rcx\n char *v10; // rax\n char *v11[9]; // [rsp+0h] [rbp-48h] BYREF\n\n v2 = 0;\n v3 = nptr;\n v4 = *nptr;\n v11[1] = (char *)__readfsqword(0x28u);\n if ( !v4 )\n goto LABEL_11;\n while ( 1 )\n {\n v5 = *__ctype_b_loc();\n while ( (v5[v4] & 0x800) == 0 && v4 != 45 )\n {\n v4 = *++v3;\n if ( !v4 )\n goto LABEL_11;\n }\n v6 = strtol(v3, v11, 10);\n v7 = v11[0];\n if ( v11[0] == v3 )\n break;\n if ( *v11[0] != 44 && *v11[0] )\n goto LABEL_14;\n v8 = v2;\n v3 = v11[0];\n ++v2;\n out_1[v8] = v6;\n v4 = *v7;\nLABEL_10:\n if ( !v4 )\n goto LABEL_11;\n }\n v4 = *v3;\n if ( !*v3 )\n goto LABEL_11;\n if ( v4 == 44 )\n goto LABEL_10;\nLABEL_14:\n v10 = v11[0] + 1;\n while ( 1 )\n {\n v11[0] = v10;\n v4 = *v10;\n v3 = v10++;\n if ( !v4 )\n break;\n if ( v4 == 44 )\n goto LABEL_10;\n }\nLABEL_11:\n *a2 = v2;\n return out_1;\n}", + "ida_strip_asm": "sub_1370:\nendbr64\npush r15\nmov r15, rsi\npush r14\nlea r14, unk_4040\npush r13\npush r12\nxor r12d, r12d\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 18h\nmovzx ebx, byte ptr [rdi]\nmov rax, fs:28h\nmov [rsp+48h+var_40], rax\nxor eax, eax\nmov r13, rsp\ntest bl, bl\njz short loc_1420\nnop dword ptr [rax+00h]\nloc_13B0:\ncall ___ctype_b_loc\nmov rdx, [rax]\njmp short loc_13D1\nloc_13C0:\ncmp bl, 2Dh ; '-'\njz short loc_13DC\nmovzx ebx, byte ptr [rbp+1]\nadd rbp, 1\ntest bl, bl\njz short loc_1420\nloc_13D1:\nmovsx rax, bl\ntest byte ptr [rdx+rax*2+1], 8\njz short loc_13C0\nloc_13DC:\nmov edx, 0Ah; base\nmov rsi, r13; endptr\nmov rdi, rbp; nptr\ncall _strtol\nmov rdx, [rsp+48h+var_48]\ncmp rdx, rbp\njz short loc_1448\nmovzx ecx, byte ptr [rdx]\ncmp cl, 2Ch ; ','\njz short loc_1401\ntest cl, cl\njnz short loc_1455\nloc_1401:\nmovsxd rcx, r12d\nmov rbp, rdx\nadd r12d, 1\nmov [r14+rcx*4], eax\nmovzx ebx, byte ptr [rdx]\nloc_1412:\ntest bl, bl\njnz short loc_13B0\nnop word ptr [rax+rax+00000000h]\nloc_1420:\nmov [r15], r12d\nmov rax, [rsp+48h+var_40]\nsub rax, fs:28h\njnz short loc_1479\nadd rsp, 18h\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1448:\nmovzx ebx, byte ptr [rbp+0]\ntest bl, bl\njz short loc_1420\ncmp bl, 2Ch ; ','\njz short loc_1412\nloc_1455:\nlea rax, [rdx+1]\njmp short loc_1465\nloc_1460:\ncmp bl, 2Ch ; ','\njz short loc_1412\nloc_1465:\nmov [rsp+48h+var_48], rax\nmovzx ebx, byte ptr [rax]\nmov rbp, rax\nadd rax, 1\ntest bl, bl\njnz short loc_1460\njmp short loc_1420\nloc_1479:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1370(char *nptr, _DWORD *a2)\n{\n int v2; // r12d\n const char *v3; // rbp\n char v4; // bl\n const unsigned __int16 *v5; // rdx\n int v6; // eax\n char *v7; // rdx\n __int64 v8; // rcx\n char *v10; // rax\n char *v11[9]; // [rsp+0h] [rbp-48h] BYREF\n\n v2 = 0;\n v3 = nptr;\n v4 = *nptr;\n v11[1] = (char *)__readfsqword(0x28u);\n if ( !v4 )\n goto LABEL_11;\n while ( 1 )\n {\n v5 = *__ctype_b_loc();\n while ( (v5[v4] & 0x800) == 0 && v4 != 45 )\n {\n v4 = *++v3;\n if ( !v4 )\n goto LABEL_11;\n }\n v6 = strtol(v3, v11, 10);\n v7 = v11[0];\n if ( v11[0] == v3 )\n break;\n if ( *v11[0] != 44 && *v11[0] )\n goto LABEL_14;\n v8 = v2;\n v3 = v11[0];\n ++v2;\n dword_4040[v8] = v6;\n v4 = *v7;\nLABEL_10:\n if ( !v4 )\n goto LABEL_11;\n }\n v4 = *v3;\n if ( !*v3 )\n goto LABEL_11;\n if ( v4 == 44 )\n goto LABEL_10;\nLABEL_14:\n v10 = v11[0] + 1;\n while ( 1 )\n {\n v11[0] = v10;\n v4 = *v10;\n v3 = v10++;\n if ( !v4 )\n break;\n if ( v4 == 44 )\n goto LABEL_10;\n }\nLABEL_11:\n *a2 = v2;\n return dword_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1370(char *nptr, uint32_t *a2) {\n int v2;\n const char *v3;\n char v4;\n const unsigned short *v5;\n int v6;\n char *v7;\n long long v8;\n char *v10;\n char *v11[9];\n v2 = 0;\n v3 = nptr;\n v4 = *nptr;\n v11[1] = (char *)__readfsqword(40u);\n if (!v4) goto LABEL_11;\n while (1) {\n v5 = *__ctype_b_loc();\n while ((v5[v4] & 2048) == 0 && v4 != 45) {\n v4 = *++v3;\n if (!v4) goto LABEL_11;\n }\n v6 = strtol(v3, v11, 10);\n v7 = v11[0];\n if (v11[0] == v3) break;\n if (*v11[0] != 44 && *v11[0]) goto LABEL_14;\n v8 = v2;\n v3 = v11[0];\n ++v2;\n dword_4040[v8] = v6;\n v4 = *v7;\n LABEL_10:\n if (!v4) goto LABEL_11;\n }\n v4 = *v3;\n if (!*v3) goto LABEL_11;\n if (v4 == 44) goto LABEL_10;\nLABEL_14:\n v10 = v11[0] + 1;\n while (1) {\n v11[0] = v10;\n v4 = *v10;\n v3 = v10++;\n if (!v4) break;\n if (v4 == 44) goto LABEL_10;\n }\nLABEL_11:\n *a2 = v2;\n return dword_4040;\n}", + "ida_pseudo_norm": "uint32_t *func0(char *nptr, uint32_t *a2) {\n int v2;\n const char *v3;\n char v4;\n const unsigned short *v5;\n int v6;\n char *v7;\n long long v8;\n char *v10;\n char *v11[9];\n v2 = 0;\n v3 = nptr;\n v4 = *nptr;\n v11[1] = (char *)__readfsqword(40u);\n if (!v4) goto LABEL_11;\n while (1) {\n v5 = *__ctype_b_loc();\n while ((v5[v4] & 2048) == 0 && v4 != 45) {\n v4 = *++v3;\n if (!v4) goto LABEL_11;\n }\n v6 = strtol(v3, v11, 10);\n v7 = v11[0];\n if (v11[0] == v3) break;\n if (*v11[0] != 44 && *v11[0]) goto LABEL_14;\n v8 = v2;\n v3 = v11[0];\n ++v2;\n out_1[v8] = v6;\n v4 = *v7;\n LABEL_10:\n if (!v4) goto LABEL_11;\n }\n v4 = *v3;\n if (!*v3) goto LABEL_11;\n if (v4 == 44) goto LABEL_10;\nLABEL_14:\n v10 = v11[0] + 1;\n while (1) {\n v11[0] = v10;\n v4 = *v10;\n v3 = v10++;\n if (!v4) break;\n if (v4 == 44) goto LABEL_10;\n }\nLABEL_11:\n *a2 = v2;\n return out_1;\n}" + }, + { + "index": "HumanEval-C-22", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n#include \n", + "func": "int *func0(const char *values, int *size) {\n static int out[256];\n int count = 0;\n const char *start = values;\n char *end;\n while (*start) {\n while (*start && !isdigit(*start) && *start != '-') {\n start++;\n }\n if (!*start) {\n break;\n }\n int val = (int)strtol(start, &end, 10);\n if (start != end && (*end == ',' || *end == '\\0')) {\n out[count++] = val;\n } else {\n while (*end && *end != ',') {\n end++;\n }\n }\n start = end;\n }\n *size = count;\n return out;\n}", + "test": "#include \n#include \n#include \n#include \n#include \n\nint issame(int *a, int size_a, int *b, int size_b) {\n if (size_a != size_b) return 0;\n for (int i = 0; i < size_a; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int size;\n\n // Test 1\n int *result1 = func0(\"\", &size);\n assert(issame(result1, size, (const int[]){}, 0));\n\n // Test 2\n int *result2 = func0(\"4,,23.2,9,adasd\", &size);\n assert(issame(result2, size, (const int[]){4, 9}, 2));\n\n // Test 3\n int *result3 = func0(\"3,c,3,3,a,b\", &size);\n assert(issame(result3, size, (const int[]){3, 3, 3}, 3));\n\n printf(\"All tests passed.\\n\");\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\nmov r15, rsi\npush r14\nlea r14, out_1\npush r13\npush r12\nxor r12d, r12d\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 18h\nmovzx ebx, byte ptr [rdi]\nmov rax, fs:28h\nmov [rsp+48h+var_40], rax\nxor eax, eax\nmov r13, rsp\ntest bl, bl\njz short loc_1420\nnop dword ptr [rax+00h]\nloc_13B0:\ncall ___ctype_b_loc\nmov rdx, [rax]\njmp short loc_13D1\nloc_13C0:\ncmp bl, 2Dh ; '-'\njz short loc_13DC\nmovzx ebx, byte ptr [rbp+1]\nadd rbp, 1\ntest bl, bl\njz short loc_1420\nloc_13D1:\nmovsx rax, bl\ntest byte ptr [rdx+rax*2+1], 8\njz short loc_13C0\nloc_13DC:\nmov edx, 0Ah; base\nmov rsi, r13; endptr\nmov rdi, rbp; nptr\ncall _strtol\nmov rdx, [rsp+48h+var_48]\ncmp rdx, rbp\njz short loc_1448\nmovzx ecx, byte ptr [rdx]\ncmp cl, 2Ch ; ','\njz short loc_1401\ntest cl, cl\njnz short loc_1455\nloc_1401:\nmovsxd rcx, r12d\nmov rbp, rdx\nadd r12d, 1\nmov [r14+rcx*4], eax\nmovzx ebx, byte ptr [rdx]\nloc_1412:\ntest bl, bl\njnz short loc_13B0\nnop word ptr [rax+rax+00000000h]\nloc_1420:\nmov [r15], r12d\nmov rax, [rsp+48h+var_40]\nsub rax, fs:28h\njnz short loc_1479\nadd rsp, 18h\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1448:\nmovzx ebx, byte ptr [rbp+0]\ntest bl, bl\njz short loc_1420\ncmp bl, 2Ch ; ','\njz short loc_1412\nloc_1455:\nlea rax, [rdx+1]\njmp short loc_1465\nloc_1460:\ncmp bl, 2Ch ; ','\njz short loc_1412\nloc_1465:\nmov [rsp+48h+var_48], rax\nmovzx ebx, byte ptr [rax]\nmov rbp, rax\nadd rax, 1\ntest bl, bl\njnz short loc_1460\njmp short loc_1420\nloc_1479:\ncall ___stack_chk_fail", + "ida_pseudo": "_DWORD *__fastcall func0(char *nptr, _DWORD *a2)\n{\n int v2; // r12d\n const char *v3; // rbp\n char v4; // bl\n const unsigned __int16 *v5; // rdx\n int v6; // eax\n char *v7; // rdx\n __int64 v8; // rcx\n char *v10; // rax\n char *v11[9]; // [rsp+0h] [rbp-48h] BYREF\n\n v2 = 0;\n v3 = nptr;\n v4 = *nptr;\n v11[1] = (char *)__readfsqword(0x28u);\n if ( !v4 )\n goto LABEL_11;\n while ( 1 )\n {\n v5 = *__ctype_b_loc();\n while ( (v5[v4] & 0x800) == 0 && v4 != 45 )\n {\n v4 = *++v3;\n if ( !v4 )\n goto LABEL_11;\n }\n v6 = strtol(v3, v11, 10);\n v7 = v11[0];\n if ( v11[0] == v3 )\n break;\n if ( *v11[0] != 44 && *v11[0] )\n goto LABEL_14;\n v8 = v2;\n v3 = v11[0];\n ++v2;\n out_1[v8] = v6;\n v4 = *v7;\nLABEL_10:\n if ( !v4 )\n goto LABEL_11;\n }\n v4 = *v3;\n if ( !*v3 )\n goto LABEL_11;\n if ( v4 == 44 )\n goto LABEL_10;\nLABEL_14:\n v10 = v11[0] + 1;\n while ( 1 )\n {\n v11[0] = v10;\n v4 = *v10;\n v3 = v10++;\n if ( !v4 )\n break;\n if ( v4 == 44 )\n goto LABEL_10;\n }\nLABEL_11:\n *a2 = v2;\n return out_1;\n}", + "ida_strip_asm": "sub_1370:\nendbr64\npush r15\nmov r15, rsi\npush r14\nlea r14, unk_4040\npush r13\npush r12\nxor r12d, r12d\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 18h\nmovzx ebx, byte ptr [rdi]\nmov rax, fs:28h\nmov [rsp+48h+var_40], rax\nxor eax, eax\nmov r13, rsp\ntest bl, bl\njz short loc_1420\nnop dword ptr [rax+00h]\nloc_13B0:\ncall ___ctype_b_loc\nmov rdx, [rax]\njmp short loc_13D1\nloc_13C0:\ncmp bl, 2Dh ; '-'\njz short loc_13DC\nmovzx ebx, byte ptr [rbp+1]\nadd rbp, 1\ntest bl, bl\njz short loc_1420\nloc_13D1:\nmovsx rax, bl\ntest byte ptr [rdx+rax*2+1], 8\njz short loc_13C0\nloc_13DC:\nmov edx, 0Ah; base\nmov rsi, r13; endptr\nmov rdi, rbp; nptr\ncall _strtol\nmov rdx, [rsp+48h+var_48]\ncmp rdx, rbp\njz short loc_1448\nmovzx ecx, byte ptr [rdx]\ncmp cl, 2Ch ; ','\njz short loc_1401\ntest cl, cl\njnz short loc_1455\nloc_1401:\nmovsxd rcx, r12d\nmov rbp, rdx\nadd r12d, 1\nmov [r14+rcx*4], eax\nmovzx ebx, byte ptr [rdx]\nloc_1412:\ntest bl, bl\njnz short loc_13B0\nnop word ptr [rax+rax+00000000h]\nloc_1420:\nmov [r15], r12d\nmov rax, [rsp+48h+var_40]\nsub rax, fs:28h\njnz short loc_1479\nadd rsp, 18h\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1448:\nmovzx ebx, byte ptr [rbp+0]\ntest bl, bl\njz short loc_1420\ncmp bl, 2Ch ; ','\njz short loc_1412\nloc_1455:\nlea rax, [rdx+1]\njmp short loc_1465\nloc_1460:\ncmp bl, 2Ch ; ','\njz short loc_1412\nloc_1465:\nmov [rsp+48h+var_48], rax\nmovzx ebx, byte ptr [rax]\nmov rbp, rax\nadd rax, 1\ntest bl, bl\njnz short loc_1460\njmp short loc_1420\nloc_1479:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1370(char *nptr, _DWORD *a2)\n{\n int v2; // r12d\n const char *v3; // rbp\n char v4; // bl\n const unsigned __int16 *v5; // rdx\n int v6; // eax\n char *v7; // rdx\n __int64 v8; // rcx\n char *v10; // rax\n char *v11[9]; // [rsp+0h] [rbp-48h] BYREF\n\n v2 = 0;\n v3 = nptr;\n v4 = *nptr;\n v11[1] = (char *)__readfsqword(0x28u);\n if ( !v4 )\n goto LABEL_11;\n while ( 1 )\n {\n v5 = *__ctype_b_loc();\n while ( (v5[v4] & 0x800) == 0 && v4 != 45 )\n {\n v4 = *++v3;\n if ( !v4 )\n goto LABEL_11;\n }\n v6 = strtol(v3, v11, 10);\n v7 = v11[0];\n if ( v11[0] == v3 )\n break;\n if ( *v11[0] != 44 && *v11[0] )\n goto LABEL_14;\n v8 = v2;\n v3 = v11[0];\n ++v2;\n dword_4040[v8] = v6;\n v4 = *v7;\nLABEL_10:\n if ( !v4 )\n goto LABEL_11;\n }\n v4 = *v3;\n if ( !*v3 )\n goto LABEL_11;\n if ( v4 == 44 )\n goto LABEL_10;\nLABEL_14:\n v10 = v11[0] + 1;\n while ( 1 )\n {\n v11[0] = v10;\n v4 = *v10;\n v3 = v10++;\n if ( !v4 )\n break;\n if ( v4 == 44 )\n goto LABEL_10;\n }\nLABEL_11:\n *a2 = v2;\n return dword_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1370(char *nptr, uint32_t *a2) {\n int v2;\n const char *v3;\n char v4;\n const unsigned short *v5;\n int v6;\n char *v7;\n long long v8;\n char *v10;\n char *v11[9];\n v2 = 0;\n v3 = nptr;\n v4 = *nptr;\n v11[1] = (char *)__readfsqword(40u);\n if (!v4) goto LABEL_11;\n while (1) {\n v5 = *__ctype_b_loc();\n while ((v5[v4] & 2048) == 0 && v4 != 45) {\n v4 = *++v3;\n if (!v4) goto LABEL_11;\n }\n v6 = strtol(v3, v11, 10);\n v7 = v11[0];\n if (v11[0] == v3) break;\n if (*v11[0] != 44 && *v11[0]) goto LABEL_14;\n v8 = v2;\n v3 = v11[0];\n ++v2;\n dword_4040[v8] = v6;\n v4 = *v7;\n LABEL_10:\n if (!v4) goto LABEL_11;\n }\n v4 = *v3;\n if (!*v3) goto LABEL_11;\n if (v4 == 44) goto LABEL_10;\nLABEL_14:\n v10 = v11[0] + 1;\n while (1) {\n v11[0] = v10;\n v4 = *v10;\n v3 = v10++;\n if (!v4) break;\n if (v4 == 44) goto LABEL_10;\n }\nLABEL_11:\n *a2 = v2;\n return dword_4040;\n}", + "ida_pseudo_norm": "uint32_t *func0(char *nptr, uint32_t *a2) {\n int v2;\n const char *v3;\n char v4;\n const unsigned short *v5;\n int v6;\n char *v7;\n long long v8;\n char *v10;\n char *v11[9];\n v2 = 0;\n v3 = nptr;\n v4 = *nptr;\n v11[1] = (char *)__readfsqword(40u);\n if (!v4) goto LABEL_11;\n while (1) {\n v5 = *__ctype_b_loc();\n while ((v5[v4] & 2048) == 0 && v4 != 45) {\n v4 = *++v3;\n if (!v4) goto LABEL_11;\n }\n v6 = strtol(v3, v11, 10);\n v7 = v11[0];\n if (v11[0] == v3) break;\n if (*v11[0] != 44 && *v11[0]) goto LABEL_14;\n v8 = v2;\n v3 = v11[0];\n ++v2;\n out_1[v8] = v6;\n v4 = *v7;\n LABEL_10:\n if (!v4) goto LABEL_11;\n }\n v4 = *v3;\n if (!*v3) goto LABEL_11;\n if (v4 == 44) goto LABEL_10;\nLABEL_14:\n v10 = v11[0] + 1;\n while (1) {\n v11[0] = v10;\n v4 = *v10;\n v3 = v10++;\n if (!v4) break;\n if (v4 == 44) goto LABEL_10;\n }\nLABEL_11:\n *a2 = v2;\n return out_1;\n}" + }, + { + "index": "HumanEval-C-23", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(const char *str) {\n int length = 0;\n while (str[length] != '\\0') {\n length++;\n }\n return length;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"\") == 0);\n assert(func0(\"x\") == 1);\n assert(func0(\"asdasnakj\") == 9);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_4], 0\njmp short loc_1162\nloc_115E:\nadd [rbp+var_4], 1\nloc_1162:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_115E\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1)\n{\n unsigned int i; // [rsp+14h] [rbp-4h]\n\n for ( i = 0; *(_BYTE *)((int)i + a1); ++i )\n ;\n return i;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_4], 0\njmp short loc_1162\nloc_115E:\nadd [rbp+var_4], 1\nloc_1162:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_115E\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(__int64 a1)\n{\n unsigned int i; // [rsp+14h] [rbp-4h]\n\n for ( i = 0; *(_BYTE *)((int)i + a1); ++i )\n ;\n return i;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(long long a1) {\n unsigned int i;\n for (i = 0; *(uint8_t *)((int)i + a1); ++i)\n ;\n return i;\n}", + "ida_pseudo_norm": "long long func0(long long a1) {\n unsigned int i;\n for (i = 0; *(uint8_t *)((int)i + a1); ++i)\n ;\n return i;\n}" + }, + { + "index": "HumanEval-C-23", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(const char *str) {\n int length = 0;\n while (str[length] != '\\0') {\n length++;\n }\n return length;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"\") == 0);\n assert(func0(\"x\") == 1);\n assert(func0(\"asdasnakj\") == 9);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ncmp byte ptr [rdi], 0\njz short loc_1166\nmov edx, 1\nloc_1157:\nmov rax, rdx\nadd rdx, 1\ncmp byte ptr [rdi+rdx-1], 0\njnz short loc_1157\nretn\nloc_1166:\nmov eax, 0\nretn", + "ida_pseudo": "__int64 __fastcall func0(_BYTE *a1)\n{\n __int64 v1; // rdx\n __int64 result; // rax\n\n if ( !*a1 )\n return 0LL;\n v1 = 1LL;\n do\n result = v1++;\n while ( a1[v1 - 1] );\n return result;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ncmp byte ptr [rdi], 0\njz short loc_1166\nmov edx, 1\nloc_1157:\nmov rax, rdx\nadd rdx, 1\ncmp byte ptr [rdi+rdx-1], 0\njnz short loc_1157\nretn\nloc_1166:\nmov eax, 0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(_BYTE *a1)\n{\n __int64 v1; // rdx\n __int64 result; // rax\n\n if ( !*a1 )\n return 0LL;\n v1 = 1LL;\n do\n result = v1++;\n while ( a1[v1 - 1] );\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(uint8_t *a1) {\n long long v1;\n long long result;\n if (!*a1) return 0LL;\n v1 = 1LL;\n do\n result = v1++;\n while (a1[v1 - 1]);\n return result;\n}", + "ida_pseudo_norm": "long long func0(uint8_t *a1) {\n long long v1;\n long long result;\n if (!*a1) return 0LL;\n v1 = 1LL;\n do\n result = v1++;\n while (a1[v1 - 1]);\n return result;\n}" + }, + { + "index": "HumanEval-C-24", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int n) {\n for (int i = 2; i * i <= n; i++)\n if (n % i == 0) return n / i;\n return 1;\n}", + "test": "#include \n\nint main() {\n assert(func0(3) == 1);\n assert(func0(7) == 1);\n assert(func0(10) == 5);\n assert(func0(100) == 50);\n assert(func0(49) == 7);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_4], 2\njmp short loc_1177\nloc_115D:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njnz short loc_1173\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\njmp short loc_1187\nloc_1173:\nadd [rbp+var_4], 1\nloc_1177:\nmov eax, [rbp+var_4]\nimul eax, eax\ncmp [rbp+var_14], eax\njge short loc_115D\nmov eax, 1\nloc_1187:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int i; // [rsp+10h] [rbp-4h]\n\n for ( i = 2; a1 >= i * i; ++i )\n {\n if ( !(a1 % i) )\n return (unsigned int)(a1 / i);\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_4], 2\njmp short loc_1177\nloc_115D:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njnz short loc_1173\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\njmp short loc_1187\nloc_1173:\nadd [rbp+var_4], 1\nloc_1177:\nmov eax, [rbp+var_4]\nimul eax, eax\ncmp [rbp+var_14], eax\njge short loc_115D\nmov eax, 1\nloc_1187:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int i; // [rsp+10h] [rbp-4h]\n\n for ( i = 2; a1 >= i * i; ++i )\n {\n if ( !(a1 % i) )\n return (unsigned int)(a1 / i);\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int i;\n for (i = 2; a1 >= i * i; ++i) {\n if (!(a1 % i)) return (unsigned int)(a1 / i);\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int i;\n for (i = 2; a1 >= i * i; ++i) {\n if (!(a1 % i)) return (unsigned int)(a1 / i);\n }\n return 1LL;\n}" + }, + { + "index": "HumanEval-C-24", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int n) {\n for (int i = 2; i * i <= n; i++)\n if (n % i == 0) return n / i;\n return 1;\n}", + "test": "#include \n\nint main() {\n assert(func0(3) == 1);\n assert(func0(7) == 1);\n assert(func0(10) == 5);\n assert(func0(100) == 50);\n assert(func0(49) == 7);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ncmp edi, 3\njle short loc_1184\nmov esi, edi\nand esi, 1\njz short loc_117D\nmov ecx, 2\nloc_115E:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, edi\njg short loc_117A\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_115E\nloc_1173:\nmov eax, edi\ncdq\nidiv ecx\nmov esi, eax\nloc_117A:\nmov eax, esi\nretn\nloc_117D:\nmov ecx, 2\njmp short loc_1173\nloc_1184:\nmov esi, 1\njmp short loc_117A", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v1; // esi\n int v2; // ecx\n\n if ( a1 <= 3 )\n {\n return 1;\n }\n else\n {\n v1 = a1 & 1;\n if ( (a1 & 1) != 0 )\n {\n v2 = 2;\n while ( 1 )\n {\n ++v2;\n if ( v2 * v2 > a1 )\n break;\n if ( !(a1 % v2) )\n return (unsigned int)(a1 / v2);\n }\n }\n else\n {\n v2 = 2;\n return (unsigned int)(a1 / v2);\n }\n }\n return v1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ncmp edi, 3\njle short loc_1184\nmov esi, edi\nand esi, 1\njz short loc_117D\nmov ecx, 2\nloc_115E:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, edi\njg short loc_117A\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_115E\nloc_1173:\nmov eax, edi\ncdq\nidiv ecx\nmov esi, eax\nloc_117A:\nmov eax, esi\nretn\nloc_117D:\nmov ecx, 2\njmp short loc_1173\nloc_1184:\nmov esi, 1\njmp short loc_117A", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n unsigned int v1; // esi\n int v2; // ecx\n\n if ( a1 <= 3 )\n {\n return 1;\n }\n else\n {\n v1 = a1 & 1;\n if ( (a1 & 1) != 0 )\n {\n v2 = 2;\n while ( 1 )\n {\n ++v2;\n if ( v2 * v2 > a1 )\n break;\n if ( !(a1 % v2) )\n return (unsigned int)(a1 / v2);\n }\n }\n else\n {\n v2 = 2;\n return (unsigned int)(a1 / v2);\n }\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n unsigned int v1;\n int v2;\n if (a1 <= 3) {\n return 1;\n } else {\n v1 = a1 & 1;\n if ((a1 & 1) != 0) {\n v2 = 2;\n while (1) {\n ++v2;\n if (v2 * v2 > a1) break;\n if (!(a1 % v2)) return (unsigned int)(a1 / v2);\n }\n } else {\n v2 = 2;\n return (unsigned int)(a1 / v2);\n }\n }\n return v1;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v1;\n int v2;\n if (a1 <= 3) {\n return 1;\n } else {\n v1 = a1 & 1;\n if ((a1 & 1) != 0) {\n v2 = 2;\n while (1) {\n ++v2;\n if (v2 * v2 > a1) break;\n if (!(a1 % v2)) return (unsigned int)(a1 / v2);\n }\n } else {\n v2 = 2;\n return (unsigned int)(a1 / v2);\n }\n }\n return v1;\n}" + }, + { + "index": "HumanEval-C-25", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int* func0(int n, int* size) {\n int* out = malloc(sizeof(int) * 64);\n *size = 0;\n for (int i = 2; i * i <= n; i++) {\n while (n % i == 0) {\n n = n / i;\n out[(*size)++] = i;\n }\n }\n if (n > 1) {\n out[(*size)++] = n;\n }\n return out;\n}", + "test": "#include \n#include \n#include \n\nint issame(int* a, int a_size, int* b, int b_size) {\n if (a_size != b_size) return 0;\n for (int i = 0; i < a_size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int size;\n int* result;\n\n result = func0(2, &size);\n assert(issame(result, size, (const int[]){2}, 1));\n free(result);\n\n result = func0(4, &size);\n assert(issame(result, size, (const int[]){2, 2}, 2));\n free(result);\n\n result = func0(8, &size);\n assert(issame(result, size, (const int[]){2, 2, 2}, 3));\n free(result);\n\n result = func0(3 * 19, &size);\n assert(issame(result, size, (const int[]){3, 19}, 2));\n free(result);\n\n result = func0(3 * 19 * 3 * 19, &size);\n assert(issame(result, size, (const int[]){3, 3, 19, 19}, 4));\n free(result);\n\n result = func0(3 * 19 * 3 * 19 * 3 * 19, &size);\n assert(issame(result, size, (const int[]){3, 3, 3, 19, 19, 19}, 6));\n free(result);\n\n result = func0(3 * 19 * 19 * 19, &size);\n assert(issame(result, size, (const int[]){3, 19, 19, 19}, 4));\n free(result);\n\n result = func0(3 * 2 * 3, &size);\n assert(issame(result, size, (const int[]){2, 3, 3}, 3));\n free(result);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov [rbp+var_20], rsi\nmov edi, 100h; size\ncall _malloc\nmov [rbp+var_8], rax\nmov rax, [rbp+var_20]\nmov dword ptr [rax], 0\nmov [rbp+var_C], 2\njmp short loc_121D\nloc_11DD:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_C]\nmov [rbp+var_14], eax\nmov rax, [rbp+var_20]\nmov eax, [rax]\nlea ecx, [rax+1]\nmov rdx, [rbp+var_20]\nmov [rdx], ecx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_C]\nmov [rdx], eax\nloc_120C:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_C]\nmov eax, edx\ntest eax, eax\njz short loc_11DD\nadd [rbp+var_C], 1\nloc_121D:\nmov eax, [rbp+var_C]\nimul eax, eax\ncmp [rbp+var_14], eax\njge short loc_120C\ncmp [rbp+var_14], 1\njle short loc_1253\nmov rax, [rbp+var_20]\nmov eax, [rax]\nlea ecx, [rax+1]\nmov rdx, [rbp+var_20]\nmov [rdx], ecx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_14]\nmov [rdx], eax\nloc_1253:\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int a1, _DWORD *a2)\n{\n int v2; // eax\n int v3; // eax\n int i; // [rsp+14h] [rbp-Ch]\n _DWORD *v7; // [rsp+18h] [rbp-8h]\n\n v7 = malloc(0x100uLL);\n *a2 = 0;\n for ( i = 2; a1 >= i * i; ++i )\n {\n while ( !(a1 % i) )\n {\n a1 /= i;\n v2 = (*a2)++;\n v7[v2] = i;\n }\n }\n if ( a1 > 1 )\n {\n v3 = (*a2)++;\n v7[v3] = a1;\n }\n return v7;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov [rbp+var_20], rsi\nmov edi, 100h; size\ncall _malloc\nmov [rbp+var_8], rax\nmov rax, [rbp+var_20]\nmov dword ptr [rax], 0\nmov [rbp+var_C], 2\njmp short loc_121D\nloc_11DD:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_C]\nmov [rbp+var_14], eax\nmov rax, [rbp+var_20]\nmov eax, [rax]\nlea ecx, [rax+1]\nmov rdx, [rbp+var_20]\nmov [rdx], ecx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_C]\nmov [rdx], eax\nloc_120C:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_C]\nmov eax, edx\ntest eax, eax\njz short loc_11DD\nadd [rbp+var_C], 1\nloc_121D:\nmov eax, [rbp+var_C]\nimul eax, eax\ncmp [rbp+var_14], eax\njge short loc_120C\ncmp [rbp+var_14], 1\njle short loc_1253\nmov rax, [rbp+var_20]\nmov eax, [rax]\nlea ecx, [rax+1]\nmov rdx, [rbp+var_20]\nmov [rdx], ecx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_14]\nmov [rdx], eax\nloc_1253:\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(int a1, _DWORD *a2)\n{\n int v2; // eax\n int v3; // eax\n int i; // [rsp+14h] [rbp-Ch]\n _DWORD *v7; // [rsp+18h] [rbp-8h]\n\n v7 = malloc(0x100uLL);\n *a2 = 0;\n for ( i = 2; a1 >= i * i; ++i )\n {\n while ( !(a1 % i) )\n {\n a1 /= i;\n v2 = (*a2)++;\n v7[v2] = i;\n }\n }\n if ( a1 > 1 )\n {\n v3 = (*a2)++;\n v7[v3] = a1;\n }\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(int a1, uint32_t *a2) {\n int v2;\n int v3;\n int i;\n uint32_t *v7;\n v7 = malloc(256uLL);\n *a2 = 0;\n for (i = 2; a1 >= i * i; ++i) {\n while (!(a1 % i)) {\n a1 /= i;\n v2 = (*a2)++;\n v7[v2] = i;\n }\n }\n if (a1 > 1) {\n v3 = (*a2)++;\n v7[v3] = a1;\n }\n return v7;\n}", + "ida_pseudo_norm": "uint32_t *func0(int a1, uint32_t *a2) {\n int v2;\n int v3;\n int i;\n uint32_t *v7;\n v7 = malloc(256uLL);\n *a2 = 0;\n for (i = 2; a1 >= i * i; ++i) {\n while (!(a1 % i)) {\n a1 /= i;\n v2 = (*a2)++;\n v7[v2] = i;\n }\n }\n if (a1 > 1) {\n v3 = (*a2)++;\n v7[v3] = a1;\n }\n return v7;\n}" + }, + { + "index": "HumanEval-C-25", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int* func0(int n, int* size) {\n int* out = malloc(sizeof(int) * 64);\n *size = 0;\n for (int i = 2; i * i <= n; i++) {\n while (n % i == 0) {\n n = n / i;\n out[(*size)++] = i;\n }\n }\n if (n > 1) {\n out[(*size)++] = n;\n }\n return out;\n}", + "test": "#include \n#include \n#include \n\nint issame(int* a, int a_size, int* b, int b_size) {\n if (a_size != b_size) return 0;\n for (int i = 0; i < a_size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int size;\n int* result;\n\n result = func0(2, &size);\n assert(issame(result, size, (const int[]){2}, 1));\n free(result);\n\n result = func0(4, &size);\n assert(issame(result, size, (const int[]){2, 2}, 2));\n free(result);\n\n result = func0(8, &size);\n assert(issame(result, size, (const int[]){2, 2, 2}, 3));\n free(result);\n\n result = func0(3 * 19, &size);\n assert(issame(result, size, (const int[]){3, 19}, 2));\n free(result);\n\n result = func0(3 * 19 * 3 * 19, &size);\n assert(issame(result, size, (const int[]){3, 3, 19, 19}, 4));\n free(result);\n\n result = func0(3 * 19 * 3 * 19 * 3 * 19, &size);\n assert(issame(result, size, (const int[]){3, 3, 3, 19, 19, 19}, 6));\n free(result);\n\n result = func0(3 * 19 * 19 * 19, &size);\n assert(issame(result, size, (const int[]){3, 19, 19, 19}, 4));\n free(result);\n\n result = func0(3 * 2 * 3, &size);\n assert(issame(result, size, (const int[]){2, 3, 3}, 3));\n free(result);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov ebx, edi\nmov rbp, rsi\nmov edi, 100h; size\ncall _malloc\nmov r10, rax\nmov dword ptr [rbp+0], 0\nmov ecx, 2\ncmp ebx, 3\njg short loc_122E\nloc_11D6:\ncmp ebx, 1\njle short loc_11EA\nmov eax, [rbp+0]\nlea edx, [rax+1]\nmov [rbp+0], edx\ncdqe\nmov [r10+rax*4], ebx\nloc_11EA:\nmov rax, r10\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_11F4:\nmov eax, [rbp+0]\nlea edi, [rax+1]\nmovsxd rdi, edi\ncdqe\nlea rsi, [r10+rax*4]\nloc_1203:\nmov eax, ebx\ncdq\nidiv ecx\nmov ebx, eax\nmov [rsi], ecx\nmov r9, rdi\nadd rdi, 1\nadd rsi, 4\ncdq\nidiv ecx\ntest edx, edx\njz short loc_1203\nmov [rbp+0], r9d\nloc_1222:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, ebx\njg short loc_11D6\nloc_122E:\nmov eax, ebx\ncdq\nidiv ecx\ntest edx, edx\njz short loc_11F4\njmp short loc_1222", + "ida_pseudo": "_DWORD *__fastcall func0(int a1, int *a2)\n{\n int v2; // ebx\n _DWORD *v4; // r10\n int v5; // ecx\n int v6; // eax\n __int64 v8; // rdi\n int *v9; // rsi\n int v10; // r9d\n\n v2 = a1;\n v4 = malloc(0x100uLL);\n *a2 = 0;\n v5 = 2;\n if ( a1 > 3 )\n {\n do\n {\n if ( !(v2 % v5) )\n {\n v8 = *a2 + 1;\n v9 = &v4[*a2];\n do\n {\n v2 /= v5;\n *v9 = v5;\n v10 = v8++;\n ++v9;\n }\n while ( !(v2 % v5) );\n *a2 = v10;\n }\n ++v5;\n }\n while ( v5 * v5 <= v2 );\n }\n if ( v2 > 1 )\n {\n v6 = (*a2)++;\n v4[v6] = v2;\n }\n return v4;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov ebx, edi\nmov rbp, rsi\nmov edi, 100h; size\ncall _malloc\nmov r10, rax\nmov dword ptr [rbp+0], 0\nmov ecx, 2\ncmp ebx, 3\njg short loc_122E\nloc_11D6:\ncmp ebx, 1\njle short loc_11EA\nmov eax, [rbp+0]\nlea edx, [rax+1]\nmov [rbp+0], edx\ncdqe\nmov [r10+rax*4], ebx\nloc_11EA:\nmov rax, r10\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_11F4:\nmov eax, [rbp+0]\nlea edi, [rax+1]\nmovsxd rdi, edi\ncdqe\nlea rsi, [r10+rax*4]\nloc_1203:\nmov eax, ebx\ncdq\nidiv ecx\nmov ebx, eax\nmov [rsi], ecx\nmov r9, rdi\nadd rdi, 1\nadd rsi, 4\ncdq\nidiv ecx\ntest edx, edx\njz short loc_1203\nmov [rbp+0], r9d\nloc_1222:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, ebx\njg short loc_11D6\nloc_122E:\nmov eax, ebx\ncdq\nidiv ecx\ntest edx, edx\njz short loc_11F4\njmp short loc_1222", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(int a1, int *a2)\n{\n int v2; // ebx\n _DWORD *v4; // r10\n int v5; // ecx\n int v6; // eax\n __int64 v8; // rdi\n int *v9; // rsi\n int v10; // r9d\n\n v2 = a1;\n v4 = malloc(0x100uLL);\n *a2 = 0;\n v5 = 2;\n if ( a1 > 3 )\n {\n do\n {\n if ( !(v2 % v5) )\n {\n v8 = *a2 + 1;\n v9 = &v4[*a2];\n do\n {\n v2 /= v5;\n *v9 = v5;\n v10 = v8++;\n ++v9;\n }\n while ( !(v2 % v5) );\n *a2 = v10;\n }\n ++v5;\n }\n while ( v5 * v5 <= v2 );\n }\n if ( v2 > 1 )\n {\n v6 = (*a2)++;\n v4[v6] = v2;\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(int a1, int *a2) {\n int v2;\n uint32_t *v4;\n int v5;\n int v6;\n long long v8;\n int *v9;\n int v10;\n v2 = a1;\n v4 = malloc(256uLL);\n *a2 = 0;\n v5 = 2;\n if (a1 > 3) {\n do {\n if (!(v2 % v5)) {\n v8 = *a2 + 1;\n v9 = &v4[*a2];\n do {\n v2 /= v5;\n *v9 = v5;\n v10 = v8++;\n ++v9;\n } while (!(v2 % v5));\n *a2 = v10;\n }\n ++v5;\n } while (v5 * v5 <= v2);\n }\n if (v2 > 1) {\n v6 = (*a2)++;\n v4[v6] = v2;\n }\n return v4;\n}", + "ida_pseudo_norm": "uint32_t *func0(int a1, int *a2) {\n int v2;\n uint32_t *v4;\n int v5;\n int v6;\n long long v8;\n int *v9;\n int v10;\n v2 = a1;\n v4 = malloc(256uLL);\n *a2 = 0;\n v5 = 2;\n if (a1 > 3) {\n do {\n if (!(v2 % v5)) {\n v8 = *a2 + 1;\n v9 = &v4[*a2];\n do {\n v2 /= v5;\n *v9 = v5;\n v10 = v8++;\n ++v9;\n } while (!(v2 % v5));\n *a2 = v10;\n }\n ++v5;\n } while (v5 * v5 <= v2);\n }\n if (v2 > 1) {\n v6 = (*a2)++;\n v4[v6] = v2;\n }\n return v4;\n}" + }, + { + "index": "HumanEval-C-25", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int* func0(int n, int* size) {\n int* out = malloc(sizeof(int) * 64);\n *size = 0;\n for (int i = 2; i * i <= n; i++) {\n while (n % i == 0) {\n n = n / i;\n out[(*size)++] = i;\n }\n }\n if (n > 1) {\n out[(*size)++] = n;\n }\n return out;\n}", + "test": "#include \n#include \n#include \n\nint issame(int* a, int a_size, int* b, int b_size) {\n if (a_size != b_size) return 0;\n for (int i = 0; i < a_size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int size;\n int* result;\n\n result = func0(2, &size);\n assert(issame(result, size, (const int[]){2}, 1));\n free(result);\n\n result = func0(4, &size);\n assert(issame(result, size, (const int[]){2, 2}, 2));\n free(result);\n\n result = func0(8, &size);\n assert(issame(result, size, (const int[]){2, 2, 2}, 3));\n free(result);\n\n result = func0(3 * 19, &size);\n assert(issame(result, size, (const int[]){3, 19}, 2));\n free(result);\n\n result = func0(3 * 19 * 3 * 19, &size);\n assert(issame(result, size, (const int[]){3, 3, 19, 19}, 4));\n free(result);\n\n result = func0(3 * 19 * 3 * 19 * 3 * 19, &size);\n assert(issame(result, size, (const int[]){3, 3, 3, 19, 19, 19}, 6));\n free(result);\n\n result = func0(3 * 19 * 19 * 19, &size);\n assert(issame(result, size, (const int[]){3, 19, 19, 19}, 4));\n free(result);\n\n result = func0(3 * 2 * 3, &size);\n assert(issame(result, size, (const int[]){2, 3, 3}, 3));\n free(result);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsi\npush rbx\nmov ebx, edi\nmov edi, 100h; size\nsub rsp, 8\ncall _malloc\nmov dword ptr [rbp+0], 0\nmov ecx, 2\nmov r8, rax\ncmp ebx, 3\njle short loc_15C1\nnop dword ptr [rax]\nloc_1580:\nmov eax, ebx\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_15B5\nmov eax, [rbp+0]\nlea esi, [rax+1]\nmovsxd rsi, esi\nnop word ptr [rax+rax+00h]\nloc_1598:\nmov eax, ebx\nmov [r8+rsi*4-4], ecx\nmov rdi, rsi\nadd rsi, 1\ncdq\nidiv ecx\ncdq\nmov ebx, eax\nidiv ecx\ntest edx, edx\njz short loc_1598\nmov [rbp+0], edi\nloc_15B5:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, ebx\njle short loc_1580\nloc_15C1:\ncmp ebx, 1\njle short loc_15D4\nmovsxd rax, dword ptr [rbp+0]\nlea edx, [rax+1]\nmov [r8+rax*4], ebx\nmov [rbp+0], edx\nloc_15D4:\nadd rsp, 8\nmov rax, r8\npop rbx\npop rbp\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int a1, int *a2)\n{\n int v3; // ebx\n _DWORD *v4; // rax\n int v5; // ecx\n _DWORD *v6; // r8\n __int64 v7; // rsi\n int v8; // edi\n int v9; // edx\n __int64 v10; // rax\n\n v3 = a1;\n v4 = malloc(0x100uLL);\n *a2 = 0;\n v5 = 2;\n v6 = v4;\n if ( a1 > 3 )\n {\n do\n {\n if ( !(v3 % v5) )\n {\n v7 = *a2 + 1;\n do\n {\n v4[v7 - 1] = v5;\n v8 = v7++;\n v9 = (v3 / v5) >> 31;\n v3 /= v5;\n }\n while ( !(unsigned int)(__SPAIR64__(v9, v3) % v5) );\n *a2 = v8;\n }\n ++v5;\n }\n while ( v5 * v5 <= v3 );\n }\n if ( v3 > 1 )\n {\n v10 = *a2;\n v6[v10] = v3;\n *a2 = v10 + 1;\n }\n return v6;\n}", + "ida_strip_asm": "sub_1550:\nendbr64\npush rbp\nmov rbp, rsi\npush rbx\nmov ebx, edi\nmov edi, 100h; size\nsub rsp, 8\ncall _malloc\nmov dword ptr [rbp+0], 0\nmov ecx, 2\nmov r8, rax\ncmp ebx, 3\njle short loc_15C1\nnop dword ptr [rax]\nloc_1580:\nmov eax, ebx\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_15B5\nmov eax, [rbp+0]\nlea esi, [rax+1]\nmovsxd rsi, esi\nnop word ptr [rax+rax+00h]\nloc_1598:\nmov eax, ebx\nmov [r8+rsi*4-4], ecx\nmov rdi, rsi\nadd rsi, 1\ncdq\nidiv ecx\ncdq\nmov ebx, eax\nidiv ecx\ntest edx, edx\njz short loc_1598\nmov [rbp+0], edi\nloc_15B5:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, ebx\njle short loc_1580\nloc_15C1:\ncmp ebx, 1\njle short loc_15D4\nmovsxd rax, dword ptr [rbp+0]\nlea edx, [rax+1]\nmov [r8+rax*4], ebx\nmov [rbp+0], edx\nloc_15D4:\nadd rsp, 8\nmov rax, r8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1550(int a1, int *a2)\n{\n int v3; // ebx\n _DWORD *v4; // rax\n int v5; // ecx\n _DWORD *v6; // r8\n __int64 v7; // rsi\n int v8; // edi\n int v9; // edx\n __int64 v10; // rax\n\n v3 = a1;\n v4 = malloc(0x100uLL);\n *a2 = 0;\n v5 = 2;\n v6 = v4;\n if ( a1 > 3 )\n {\n do\n {\n if ( !(v3 % v5) )\n {\n v7 = *a2 + 1;\n do\n {\n v4[v7 - 1] = v5;\n v8 = v7++;\n v9 = (v3 / v5) >> 31;\n v3 /= v5;\n }\n while ( !(unsigned int)(__SPAIR64__(v9, v3) % v5) );\n *a2 = v8;\n }\n ++v5;\n }\n while ( v5 * v5 <= v3 );\n }\n if ( v3 > 1 )\n {\n v10 = *a2;\n v6[v10] = v3;\n *a2 = v10 + 1;\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1550(int a1, int *a2) {\n int v3;\n uint32_t *v4;\n int v5;\n uint32_t *v6;\n long long v7;\n int v8;\n int v9;\n long long v10;\n v3 = a1;\n v4 = malloc(256uLL);\n *a2 = 0;\n v5 = 2;\n v6 = v4;\n if (a1 > 3) {\n do {\n if (!(v3 % v5)) {\n v7 = *a2 + 1;\n do {\n v4[v7 - 1] = v5;\n v8 = v7++;\n v9 = (v3 / v5) >> 31;\n v3 /= v5;\n } while (!(unsigned int)(__SPAIR64__(v9, v3) % v5));\n *a2 = v8;\n }\n ++v5;\n } while (v5 * v5 <= v3);\n }\n if (v3 > 1) {\n v10 = *a2;\n v6[v10] = v3;\n *a2 = v10 + 1;\n }\n return v6;\n}", + "ida_pseudo_norm": "uint32_t *func0(int a1, int *a2) {\n int v3;\n uint32_t *v4;\n int v5;\n uint32_t *v6;\n long long v7;\n int v8;\n int v9;\n long long v10;\n v3 = a1;\n v4 = malloc(256uLL);\n *a2 = 0;\n v5 = 2;\n v6 = v4;\n if (a1 > 3) {\n do {\n if (!(v3 % v5)) {\n v7 = *a2 + 1;\n do {\n v4[v7 - 1] = v5;\n v8 = v7++;\n v9 = (v3 / v5) >> 31;\n v3 /= v5;\n } while (!(unsigned int)(__SPAIR64__(v9, v3) % v5));\n *a2 = v8;\n }\n ++v5;\n } while (v5 * v5 <= v3);\n }\n if (v3 > 1) {\n v10 = *a2;\n v6[v10] = v3;\n *a2 = v10 + 1;\n }\n return v6;\n}" + }, + { + "index": "HumanEval-C-25", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int* func0(int n, int* size) {\n int* out = malloc(sizeof(int) * 64);\n *size = 0;\n for (int i = 2; i * i <= n; i++) {\n while (n % i == 0) {\n n = n / i;\n out[(*size)++] = i;\n }\n }\n if (n > 1) {\n out[(*size)++] = n;\n }\n return out;\n}", + "test": "#include \n#include \n#include \n\nint issame(int* a, int a_size, int* b, int b_size) {\n if (a_size != b_size) return 0;\n for (int i = 0; i < a_size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int size;\n int* result;\n\n result = func0(2, &size);\n assert(issame(result, size, (const int[]){2}, 1));\n free(result);\n\n result = func0(4, &size);\n assert(issame(result, size, (const int[]){2, 2}, 2));\n free(result);\n\n result = func0(8, &size);\n assert(issame(result, size, (const int[]){2, 2, 2}, 3));\n free(result);\n\n result = func0(3 * 19, &size);\n assert(issame(result, size, (const int[]){3, 19}, 2));\n free(result);\n\n result = func0(3 * 19 * 3 * 19, &size);\n assert(issame(result, size, (const int[]){3, 3, 19, 19}, 4));\n free(result);\n\n result = func0(3 * 19 * 3 * 19 * 3 * 19, &size);\n assert(issame(result, size, (const int[]){3, 3, 3, 19, 19, 19}, 6));\n free(result);\n\n result = func0(3 * 19 * 19 * 19, &size);\n assert(issame(result, size, (const int[]){3, 19, 19, 19}, 4));\n free(result);\n\n result = func0(3 * 2 * 3, &size);\n assert(issame(result, size, (const int[]){2, 3, 3}, 3));\n free(result);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsi\npush rbx\nmov ebx, edi\nmov edi, 100h; size\nsub rsp, 8\ncall _malloc\nmov dword ptr [rbp+0], 0\nmov ecx, 2\nmov r8, rax\ncmp ebx, 3\njle short loc_15C1\nnop dword ptr [rax]\nloc_1580:\nmov eax, ebx\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_15B5\nmov eax, [rbp+0]\nlea esi, [rax+1]\nmovsxd rsi, esi\nnop word ptr [rax+rax+00h]\nloc_1598:\nmov eax, ebx\nmov [r8+rsi*4-4], ecx\nmov rdi, rsi\nadd rsi, 1\ncdq\nidiv ecx\ncdq\nmov ebx, eax\nidiv ecx\ntest edx, edx\njz short loc_1598\nmov [rbp+0], edi\nloc_15B5:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, ebx\njle short loc_1580\nloc_15C1:\ncmp ebx, 1\njle short loc_15D4\nmovsxd rax, dword ptr [rbp+0]\nlea edx, [rax+1]\nmov [r8+rax*4], ebx\nmov [rbp+0], edx\nloc_15D4:\nadd rsp, 8\nmov rax, r8\npop rbx\npop rbp\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int a1, int *a2)\n{\n int v3; // ebx\n _DWORD *v4; // rax\n int v5; // ecx\n _DWORD *v6; // r8\n __int64 v7; // rsi\n int v8; // edi\n int v9; // edx\n __int64 v10; // rax\n\n v3 = a1;\n v4 = malloc(0x100uLL);\n *a2 = 0;\n v5 = 2;\n v6 = v4;\n if ( a1 > 3 )\n {\n do\n {\n if ( !(v3 % v5) )\n {\n v7 = *a2 + 1;\n do\n {\n v4[v7 - 1] = v5;\n v8 = v7++;\n v9 = (v3 / v5) >> 31;\n v3 /= v5;\n }\n while ( !(unsigned int)(__SPAIR64__(v9, v3) % v5) );\n *a2 = v8;\n }\n ++v5;\n }\n while ( v5 * v5 <= v3 );\n }\n if ( v3 > 1 )\n {\n v10 = *a2;\n v6[v10] = v3;\n *a2 = v10 + 1;\n }\n return v6;\n}", + "ida_strip_asm": "sub_1550:\nendbr64\npush rbp\nmov rbp, rsi\npush rbx\nmov ebx, edi\nmov edi, 100h; size\nsub rsp, 8\ncall _malloc\nmov dword ptr [rbp+0], 0\nmov ecx, 2\nmov r8, rax\ncmp ebx, 3\njle short loc_15C1\nnop dword ptr [rax]\nloc_1580:\nmov eax, ebx\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_15B5\nmov eax, [rbp+0]\nlea esi, [rax+1]\nmovsxd rsi, esi\nnop word ptr [rax+rax+00h]\nloc_1598:\nmov eax, ebx\nmov [r8+rsi*4-4], ecx\nmov rdi, rsi\nadd rsi, 1\ncdq\nidiv ecx\ncdq\nmov ebx, eax\nidiv ecx\ntest edx, edx\njz short loc_1598\nmov [rbp+0], edi\nloc_15B5:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, ebx\njle short loc_1580\nloc_15C1:\ncmp ebx, 1\njle short loc_15D4\nmovsxd rax, dword ptr [rbp+0]\nlea edx, [rax+1]\nmov [r8+rax*4], ebx\nmov [rbp+0], edx\nloc_15D4:\nadd rsp, 8\nmov rax, r8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1550(int a1, int *a2)\n{\n int v3; // ebx\n _DWORD *v4; // rax\n int v5; // ecx\n _DWORD *v6; // r8\n __int64 v7; // rsi\n int v8; // edi\n int v9; // edx\n __int64 v10; // rax\n\n v3 = a1;\n v4 = malloc(0x100uLL);\n *a2 = 0;\n v5 = 2;\n v6 = v4;\n if ( a1 > 3 )\n {\n do\n {\n if ( !(v3 % v5) )\n {\n v7 = *a2 + 1;\n do\n {\n v4[v7 - 1] = v5;\n v8 = v7++;\n v9 = (v3 / v5) >> 31;\n v3 /= v5;\n }\n while ( !(unsigned int)(__SPAIR64__(v9, v3) % v5) );\n *a2 = v8;\n }\n ++v5;\n }\n while ( v5 * v5 <= v3 );\n }\n if ( v3 > 1 )\n {\n v10 = *a2;\n v6[v10] = v3;\n *a2 = v10 + 1;\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1550(int a1, int *a2) {\n int v3;\n uint32_t *v4;\n int v5;\n uint32_t *v6;\n long long v7;\n int v8;\n int v9;\n long long v10;\n v3 = a1;\n v4 = malloc(256uLL);\n *a2 = 0;\n v5 = 2;\n v6 = v4;\n if (a1 > 3) {\n do {\n if (!(v3 % v5)) {\n v7 = *a2 + 1;\n do {\n v4[v7 - 1] = v5;\n v8 = v7++;\n v9 = (v3 / v5) >> 31;\n v3 /= v5;\n } while (!(unsigned int)(__SPAIR64__(v9, v3) % v5));\n *a2 = v8;\n }\n ++v5;\n } while (v5 * v5 <= v3);\n }\n if (v3 > 1) {\n v10 = *a2;\n v6[v10] = v3;\n *a2 = v10 + 1;\n }\n return v6;\n}", + "ida_pseudo_norm": "uint32_t *func0(int a1, int *a2) {\n int v3;\n uint32_t *v4;\n int v5;\n uint32_t *v6;\n long long v7;\n int v8;\n int v9;\n long long v10;\n v3 = a1;\n v4 = malloc(256uLL);\n *a2 = 0;\n v5 = 2;\n v6 = v4;\n if (a1 > 3) {\n do {\n if (!(v3 % v5)) {\n v7 = *a2 + 1;\n do {\n v4[v7 - 1] = v5;\n v8 = v7++;\n v9 = (v3 / v5) >> 31;\n v3 /= v5;\n } while (!(unsigned int)(__SPAIR64__(v9, v3) % v5));\n *a2 = v8;\n }\n ++v5;\n } while (v5 * v5 <= v3);\n }\n if (v3 > 1) {\n v10 = *a2;\n v6[v10] = v3;\n *a2 = v10 + 1;\n }\n return v6;\n}" + }, + { + "index": "HumanEval-C-26", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int* func0(int* numbers, int size, int* new_size) {\n int* out = (int*)malloc(size * sizeof(int));\n int* has1 = (int*)calloc(size, sizeof(int));\n int* has2 = (int*)calloc(size, sizeof(int));\n int has1_count = 0;\n int has2_count = 0;\n int out_count = 0;\n for (int i = 0; i < size; i++) {\n int num = numbers[i];\n int in_has2 = 0;\n for (int j = 0; j < has2_count; j++) {\n if (has2[j] == num) {\n in_has2 = 1;\n break;\n }\n }\n if (in_has2) continue;\n int in_has1 = 0;\n for (int j = 0; j < has1_count; j++) {\n if (has1[j] == num) {\n in_has1 = 1;\n break;\n }\n }\n if (in_has1) {\n has2[has2_count++] = num;\n } else {\n has1[has1_count++] = num;\n }\n }\n for (int i = 0; i < size; i++) {\n int num = numbers[i];\n int in_has2 = 0;\n for (int j = 0; j < has2_count; j++) {\n if (has2[j] == num) {\n in_has2 = 1;\n break;\n }\n }\n if (!in_has2) {\n out[out_count++] = num;\n }\n }\n *new_size = out_count;\n free(has1);\n free(has2);\n return out;\n}", + "test": "#include \n#include \n\nint issame(int* a, int a_size, int* b, int b_size) {\n if (a_size != b_size) return 0;\n for (int i = 0; i < a_size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int new_size;\n int* result;\n\n result = func0((const int[]){}, 0, &new_size);\n assert(issame(result, new_size, (const int[]){}, 0));\n free(result);\n\n result = func0((const int[]){1, 2, 3, 4}, 4, &new_size);\n assert(issame(result, new_size, (const int[]){1, 2, 3, 4}, 4));\n free(result);\n\n result = func0((const int[]){1, 2, 3, 2, 4, 3, 5}, 7, &new_size);\n assert(issame(result, new_size, (const int[]){1, 4, 5}, 3));\n free(result);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+var_58], rdi\nmov [rbp+var_5C], esi\nmov [rbp+var_68], rdx\nmov eax, [rbp+var_5C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov eax, [rbp+var_5C]\ncdqe\nmov esi, 4; size\nmov rdi, rax; nmemb\ncall _calloc\nmov [rbp+ptr], rax\nmov eax, [rbp+var_5C]\ncdqe\nmov esi, 4; size\nmov rdi, rax; nmemb\ncall _calloc\nmov [rbp+var_8], rax\nmov [rbp+var_4C], 0\nmov [rbp+var_48], 0\nmov [rbp+var_44], 0\nmov [rbp+var_40], 0\njmp loc_1332\nloc_1242:\nmov eax, [rbp+var_40]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_1C], eax\nmov [rbp+var_3C], 0\nmov [rbp+var_38], 0\njmp short loc_1293\nloc_126B:\nmov eax, [rbp+var_38]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_1C], eax\njnz short loc_128F\nmov [rbp+var_3C], 1\njmp short loc_129B\nloc_128F:\nadd [rbp+var_38], 1\nloc_1293:\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_48]\njl short loc_126B\nloc_129B:\ncmp [rbp+var_3C], 0\njnz loc_132D\nmov [rbp+var_34], 0\nmov [rbp+var_30], 0\njmp short loc_12DD\nloc_12B5:\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_1C], eax\njnz short loc_12D9\nmov [rbp+var_34], 1\njmp short loc_12E5\nloc_12D9:\nadd [rbp+var_30], 1\nloc_12DD:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_4C]\njl short loc_12B5\nloc_12E5:\ncmp [rbp+var_34], 0\njz short loc_130C\nmov eax, [rbp+var_48]\nlea edx, [rax+1]\nmov [rbp+var_48], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_1C]\nmov [rdx], eax\njmp short loc_132E\nloc_130C:\nmov eax, [rbp+var_4C]\nlea edx, [rax+1]\nmov [rbp+var_4C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov eax, [rbp+var_1C]\nmov [rdx], eax\njmp short loc_132E\nloc_132D:\nnop\nloc_132E:\nadd [rbp+var_40], 1\nloc_1332:\nmov eax, [rbp+var_40]\ncmp eax, [rbp+var_5C]\njl loc_1242\nmov [rbp+var_2C], 0\njmp loc_13CC\nloc_134A:\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_20], eax\nmov [rbp+var_28], 0\nmov [rbp+var_24], 0\njmp short loc_139B\nloc_1373:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njnz short loc_1397\nmov [rbp+var_28], 1\njmp short loc_13A3\nloc_1397:\nadd [rbp+var_24], 1\nloc_139B:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_48]\njl short loc_1373\nloc_13A3:\ncmp [rbp+var_28], 0\njnz short loc_13C8\nmov eax, [rbp+var_44]\nlea edx, [rax+1]\nmov [rbp+var_44], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_20]\nmov [rdx], eax\nloc_13C8:\nadd [rbp+var_2C], 1\nloc_13CC:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_5C]\njl loc_134A\nmov rax, [rbp+var_68]\nmov edx, [rbp+var_44]\nmov [rax], edx\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_8]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_18]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, _DWORD *a3)\n{\n int v3; // eax\n _DWORD *v4; // rdx\n int v5; // eax\n int v6; // eax\n int v9; // [rsp+24h] [rbp-4Ch]\n int v10; // [rsp+28h] [rbp-48h]\n int v11; // [rsp+2Ch] [rbp-44h]\n int i; // [rsp+30h] [rbp-40h]\n int v13; // [rsp+34h] [rbp-3Ch]\n int j; // [rsp+38h] [rbp-38h]\n int v15; // [rsp+3Ch] [rbp-34h]\n int k; // [rsp+40h] [rbp-30h]\n int m; // [rsp+44h] [rbp-2Ch]\n int v18; // [rsp+48h] [rbp-28h]\n int n; // [rsp+4Ch] [rbp-24h]\n int v20; // [rsp+50h] [rbp-20h]\n int v21; // [rsp+54h] [rbp-1Ch]\n _DWORD *v22; // [rsp+58h] [rbp-18h]\n _DWORD *ptr; // [rsp+60h] [rbp-10h]\n _DWORD *v24; // [rsp+68h] [rbp-8h]\n\n v22 = malloc(4LL * a2);\n ptr = calloc(a2, 4uLL);\n v24 = calloc(a2, 4uLL);\n v9 = 0;\n v10 = 0;\n v11 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v21 = *(_DWORD *)(4LL * i + a1);\n v13 = 0;\n for ( j = 0; j < v10; ++j )\n {\n if ( v21 == v24[j] )\n {\n v13 = 1;\n break;\n }\n }\n if ( !v13 )\n {\n v15 = 0;\n for ( k = 0; k < v9; ++k )\n {\n if ( v21 == ptr[k] )\n {\n v15 = 1;\n break;\n }\n }\n if ( v15 )\n {\n v3 = v10++;\n v4 = &v24[v3];\n }\n else\n {\n v5 = v9++;\n v4 = &ptr[v5];\n }\n *v4 = v21;\n }\n }\n for ( m = 0; m < a2; ++m )\n {\n v20 = *(_DWORD *)(4LL * m + a1);\n v18 = 0;\n for ( n = 0; n < v10; ++n )\n {\n if ( v20 == v24[n] )\n {\n v18 = 1;\n break;\n }\n }\n if ( !v18 )\n {\n v6 = v11++;\n v22[v6] = v20;\n }\n }\n *a3 = v11;\n free(ptr);\n free(v24);\n return v22;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+var_58], rdi\nmov [rbp+var_5C], esi\nmov [rbp+var_68], rdx\nmov eax, [rbp+var_5C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov eax, [rbp+var_5C]\ncdqe\nmov esi, 4; size\nmov rdi, rax; nmemb\ncall _calloc\nmov [rbp+ptr], rax\nmov eax, [rbp+var_5C]\ncdqe\nmov esi, 4; size\nmov rdi, rax; nmemb\ncall _calloc\nmov [rbp+var_8], rax\nmov [rbp+var_4C], 0\nmov [rbp+var_48], 0\nmov [rbp+var_44], 0\nmov [rbp+var_40], 0\njmp loc_1332\nloc_1242:\nmov eax, [rbp+var_40]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_1C], eax\nmov [rbp+var_3C], 0\nmov [rbp+var_38], 0\njmp short loc_1293\nloc_126B:\nmov eax, [rbp+var_38]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_1C], eax\njnz short loc_128F\nmov [rbp+var_3C], 1\njmp short loc_129B\nloc_128F:\nadd [rbp+var_38], 1\nloc_1293:\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_48]\njl short loc_126B\nloc_129B:\ncmp [rbp+var_3C], 0\njnz loc_132D\nmov [rbp+var_34], 0\nmov [rbp+var_30], 0\njmp short loc_12DD\nloc_12B5:\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_1C], eax\njnz short loc_12D9\nmov [rbp+var_34], 1\njmp short loc_12E5\nloc_12D9:\nadd [rbp+var_30], 1\nloc_12DD:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_4C]\njl short loc_12B5\nloc_12E5:\ncmp [rbp+var_34], 0\njz short loc_130C\nmov eax, [rbp+var_48]\nlea edx, [rax+1]\nmov [rbp+var_48], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_1C]\nmov [rdx], eax\njmp short loc_132E\nloc_130C:\nmov eax, [rbp+var_4C]\nlea edx, [rax+1]\nmov [rbp+var_4C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov eax, [rbp+var_1C]\nmov [rdx], eax\njmp short loc_132E\nloc_132D:\nnop\nloc_132E:\nadd [rbp+var_40], 1\nloc_1332:\nmov eax, [rbp+var_40]\ncmp eax, [rbp+var_5C]\njl loc_1242\nmov [rbp+var_2C], 0\njmp loc_13CC\nloc_134A:\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_20], eax\nmov [rbp+var_28], 0\nmov [rbp+var_24], 0\njmp short loc_139B\nloc_1373:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njnz short loc_1397\nmov [rbp+var_28], 1\njmp short loc_13A3\nloc_1397:\nadd [rbp+var_24], 1\nloc_139B:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_48]\njl short loc_1373\nloc_13A3:\ncmp [rbp+var_28], 0\njnz short loc_13C8\nmov eax, [rbp+var_44]\nlea edx, [rax+1]\nmov [rbp+var_44], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_20]\nmov [rdx], eax\nloc_13C8:\nadd [rbp+var_2C], 1\nloc_13CC:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_5C]\njl loc_134A\nmov rax, [rbp+var_68]\nmov edx, [rbp+var_44]\nmov [rax], edx\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_8]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_18]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11C9(__int64 a1, int a2, _DWORD *a3)\n{\n int v3; // eax\n _DWORD *v4; // rdx\n int v5; // eax\n int v6; // eax\n int v9; // [rsp+24h] [rbp-4Ch]\n int v10; // [rsp+28h] [rbp-48h]\n int v11; // [rsp+2Ch] [rbp-44h]\n int i; // [rsp+30h] [rbp-40h]\n int v13; // [rsp+34h] [rbp-3Ch]\n int j; // [rsp+38h] [rbp-38h]\n int v15; // [rsp+3Ch] [rbp-34h]\n int k; // [rsp+40h] [rbp-30h]\n int m; // [rsp+44h] [rbp-2Ch]\n int v18; // [rsp+48h] [rbp-28h]\n int n; // [rsp+4Ch] [rbp-24h]\n int v20; // [rsp+50h] [rbp-20h]\n int v21; // [rsp+54h] [rbp-1Ch]\n _DWORD *v22; // [rsp+58h] [rbp-18h]\n _DWORD *ptr; // [rsp+60h] [rbp-10h]\n _DWORD *v24; // [rsp+68h] [rbp-8h]\n\n v22 = malloc(4LL * a2);\n ptr = calloc(a2, 4uLL);\n v24 = calloc(a2, 4uLL);\n v9 = 0;\n v10 = 0;\n v11 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v21 = *(_DWORD *)(4LL * i + a1);\n v13 = 0;\n for ( j = 0; j < v10; ++j )\n {\n if ( v21 == v24[j] )\n {\n v13 = 1;\n break;\n }\n }\n if ( !v13 )\n {\n v15 = 0;\n for ( k = 0; k < v9; ++k )\n {\n if ( v21 == ptr[k] )\n {\n v15 = 1;\n break;\n }\n }\n if ( v15 )\n {\n v3 = v10++;\n v4 = &v24[v3];\n }\n else\n {\n v5 = v9++;\n v4 = &ptr[v5];\n }\n *v4 = v21;\n }\n }\n for ( m = 0; m < a2; ++m )\n {\n v20 = *(_DWORD *)(4LL * m + a1);\n v18 = 0;\n for ( n = 0; n < v10; ++n )\n {\n if ( v20 == v24[n] )\n {\n v18 = 1;\n break;\n }\n }\n if ( !v18 )\n {\n v6 = v11++;\n v22[v6] = v20;\n }\n }\n *a3 = v11;\n free(ptr);\n free(v24);\n return v22;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11C9(long long a1, int a2, uint32_t *a3) {\n int v3;\n uint32_t *v4;\n int v5;\n int v6;\n int v9;\n int v10;\n int v11;\n int i;\n int v13;\n int j;\n int v15;\n int k;\n int m;\n int v18;\n int n;\n int v20;\n int v21;\n uint32_t *v22;\n uint32_t *ptr;\n uint32_t *v24;\n v22 = malloc(4LL * a2);\n ptr = calloc(a2, 4uLL);\n v24 = calloc(a2, 4uLL);\n v9 = 0;\n v10 = 0;\n v11 = 0;\n for (i = 0; i < a2; ++i) {\n v21 = *(uint32_t *)(4LL * i + a1);\n v13 = 0;\n for (j = 0; j < v10; ++j) {\n if (v21 == v24[j]) {\n v13 = 1;\n break;\n }\n }\n if (!v13) {\n v15 = 0;\n for (k = 0; k < v9; ++k) {\n if (v21 == ptr[k]) {\n v15 = 1;\n break;\n }\n }\n if (v15) {\n v3 = v10++;\n v4 = &v24[v3];\n } else {\n v5 = v9++;\n v4 = &ptr[v5];\n }\n *v4 = v21;\n }\n }\n for (m = 0; m < a2; ++m) {\n v20 = *(uint32_t *)(4LL * m + a1);\n v18 = 0;\n for (n = 0; n < v10; ++n) {\n if (v20 == v24[n]) {\n v18 = 1;\n break;\n }\n }\n if (!v18) {\n v6 = v11++;\n v22[v6] = v20;\n }\n }\n *a3 = v11;\n free(ptr);\n free(v24);\n return v22;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, uint32_t *a3) {\n int v3;\n uint32_t *v4;\n int v5;\n int v6;\n int v9;\n int v10;\n int v11;\n int i;\n int v13;\n int j;\n int v15;\n int k;\n int m;\n int v18;\n int n;\n int v20;\n int v21;\n uint32_t *v22;\n uint32_t *ptr;\n uint32_t *v24;\n v22 = malloc(4LL * a2);\n ptr = calloc(a2, 4uLL);\n v24 = calloc(a2, 4uLL);\n v9 = 0;\n v10 = 0;\n v11 = 0;\n for (i = 0; i < a2; ++i) {\n v21 = *(uint32_t *)(4LL * i + a1);\n v13 = 0;\n for (j = 0; j < v10; ++j) {\n if (v21 == v24[j]) {\n v13 = 1;\n break;\n }\n }\n if (!v13) {\n v15 = 0;\n for (k = 0; k < v9; ++k) {\n if (v21 == ptr[k]) {\n v15 = 1;\n break;\n }\n }\n if (v15) {\n v3 = v10++;\n v4 = &v24[v3];\n } else {\n v5 = v9++;\n v4 = &ptr[v5];\n }\n *v4 = v21;\n }\n }\n for (m = 0; m < a2; ++m) {\n v20 = *(uint32_t *)(4LL * m + a1);\n v18 = 0;\n for (n = 0; n < v10; ++n) {\n if (v20 == v24[n]) {\n v18 = 1;\n break;\n }\n }\n if (!v18) {\n v6 = v11++;\n v22[v6] = v20;\n }\n }\n *a3 = v11;\n free(ptr);\n free(v24);\n return v22;\n}" + }, + { + "index": "HumanEval-C-26", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int* func0(int* numbers, int size, int* new_size) {\n int* out = (int*)malloc(size * sizeof(int));\n int* has1 = (int*)calloc(size, sizeof(int));\n int* has2 = (int*)calloc(size, sizeof(int));\n int has1_count = 0;\n int has2_count = 0;\n int out_count = 0;\n for (int i = 0; i < size; i++) {\n int num = numbers[i];\n int in_has2 = 0;\n for (int j = 0; j < has2_count; j++) {\n if (has2[j] == num) {\n in_has2 = 1;\n break;\n }\n }\n if (in_has2) continue;\n int in_has1 = 0;\n for (int j = 0; j < has1_count; j++) {\n if (has1[j] == num) {\n in_has1 = 1;\n break;\n }\n }\n if (in_has1) {\n has2[has2_count++] = num;\n } else {\n has1[has1_count++] = num;\n }\n }\n for (int i = 0; i < size; i++) {\n int num = numbers[i];\n int in_has2 = 0;\n for (int j = 0; j < has2_count; j++) {\n if (has2[j] == num) {\n in_has2 = 1;\n break;\n }\n }\n if (!in_has2) {\n out[out_count++] = num;\n }\n }\n *new_size = out_count;\n free(has1);\n free(has2);\n return out;\n}", + "test": "#include \n#include \n\nint issame(int* a, int a_size, int* b, int b_size) {\n if (a_size != b_size) return 0;\n for (int i = 0; i < a_size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int new_size;\n int* result;\n\n result = func0((const int[]){}, 0, &new_size);\n assert(issame(result, new_size, (const int[]){}, 0));\n free(result);\n\n result = func0((const int[]){1, 2, 3, 4}, 4, &new_size);\n assert(issame(result, new_size, (const int[]){1, 2, 3, 4}, 4));\n free(result);\n\n result = func0((const int[]){1, 2, 3, 2, 4, 3, 5}, 7, &new_size);\n assert(issame(result, new_size, (const int[]){1, 4, 5}, 3));\n free(result);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov rbx, rdi\nmov r15d, esi\nmov [rsp+48h+var_40], rdx\nmovsxd rbp, esi\nlea r12, ds:0[rbp*4]\nmov rdi, r12; size\ncall _malloc\nmov r14, rax\nmov esi, 4; size\nmov rdi, rbp; nmemb\ncall _calloc\nmov r13, rax\nmov esi, 4; size\nmov rdi, rbp; nmemb\ncall _calloc\nmov rbp, rax\ntest r15d, r15d\njle loc_12C6\nmov rsi, rbx\nadd r12, rbx\nmov edi, 0\nmov r8d, 0\njmp short loc_124D\nloc_1238:\nmovsxd rax, r8d\nmov [r13+rax*4+0], edx\nlea r8d, [r8+1]\nloc_1244:\nadd rbx, 4\ncmp rbx, r12\njz short loc_128A\nloc_124D:\nmov edx, [rbx]\ntest edi, edi\njle short loc_126B\nmov rax, rbp\nmovsxd rcx, edi\nlea rcx, [rbp+rcx*4+0]\nloc_125E:\ncmp [rax], edx\njz short loc_1244\nadd rax, 4\ncmp rax, rcx\njnz short loc_125E\nloc_126B:\ntest r8d, r8d\njle short loc_1238\nmov rax, r13\nmovsxd rcx, r8d\nlea rcx, [r13+rcx*4+0]\nloc_127B:\ncmp [rax], edx\njz short loc_12F6\nadd rax, 4\ncmp rax, rcx\njnz short loc_127B\njmp short loc_1238\nloc_128A:\nmovsxd rax, edi\nlea rcx, [rbp+rax*4+0]\nmov r8d, 0\njmp short loc_12AE\nloc_129A:\nmovsxd rax, r8d\nmov [r14+rax*4], edx\nlea r8d, [r8+1]\nloc_12A5:\nadd rsi, 4\ncmp rsi, r12\njz short loc_12CC\nloc_12AE:\nmov edx, [rsi]\ntest edi, edi\njle short loc_129A\nmov rax, rbp\nloc_12B7:\ncmp [rax], edx\njz short loc_12A5\nadd rax, 4\ncmp rcx, rax\njnz short loc_12B7\njmp short loc_129A\nloc_12C6:\nmov r8d, 0\nloc_12CC:\nmov rax, [rsp+48h+var_40]\nmov [rax], r8d\nmov rdi, r13; ptr\ncall _free\nmov rdi, rbp; ptr\ncall _free\nmov rax, r14\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_12F6:\nmovsxd rax, edi\nmov [rbp+rax*4+0], edx\nlea edi, [rdi+1]\njmp loc_1244", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2, _DWORD *a3)\n{\n int *v3; // rbx\n size_t v4; // r12\n _DWORD *v5; // r14\n _DWORD *v6; // r13\n _DWORD *v7; // rbp\n int *v8; // rsi\n int *v9; // r12\n int v10; // edi\n int v11; // r8d\n int v12; // edx\n _DWORD *v13; // rax\n _DWORD *v14; // rax\n int v15; // r8d\n int v16; // edx\n _DWORD *v17; // rax\n\n v3 = a1;\n v4 = a2;\n v5 = malloc(v4 * 4);\n v6 = calloc(a2, 4uLL);\n v7 = calloc(a2, 4uLL);\n if ( a2 <= 0 )\n {\n v15 = 0;\n }\n else\n {\n v8 = a1;\n v9 = &a1[v4];\n v10 = 0;\n v11 = 0;\n do\n {\n v12 = *v3;\n if ( v10 <= 0 )\n {\nLABEL_9:\n if ( v11 <= 0 )\n {\nLABEL_3:\n v6[v11++] = v12;\n }\n else\n {\n v14 = v6;\n while ( *v14 != v12 )\n {\n if ( ++v14 == &v6[v11] )\n goto LABEL_3;\n }\n v7[v10++] = v12;\n }\n }\n else\n {\n v13 = v7;\n while ( *v13 != v12 )\n {\n if ( ++v13 == &v7[v10] )\n goto LABEL_9;\n }\n }\n ++v3;\n }\n while ( v3 != v9 );\n v15 = 0;\n do\n {\n v16 = *v8;\n if ( v10 <= 0 )\n {\nLABEL_15:\n v5[v15++] = v16;\n }\n else\n {\n v17 = v7;\n while ( *v17 != v16 )\n {\n if ( &v7[v10] == ++v17 )\n goto LABEL_15;\n }\n }\n ++v8;\n }\n while ( v8 != v9 );\n }\n *a3 = v15;\n free(v6);\n free(v7);\n return v5;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov rbx, rdi\nmov r15d, esi\nmov [rsp+48h+var_40], rdx\nmovsxd rbp, esi\nlea r12, ds:0[rbp*4]\nmov rdi, r12; size\ncall _malloc\nmov r14, rax\nmov esi, 4; size\nmov rdi, rbp; nmemb\ncall _calloc\nmov r13, rax\nmov esi, 4; size\nmov rdi, rbp; nmemb\ncall _calloc\nmov rbp, rax\ntest r15d, r15d\njle loc_12C6\nmov rsi, rbx\nadd r12, rbx\nmov edi, 0\nmov r8d, 0\njmp short loc_124D\nloc_1238:\nmovsxd rax, r8d\nmov [r13+rax*4+0], edx\nlea r8d, [r8+1]\nloc_1244:\nadd rbx, 4\ncmp rbx, r12\njz short loc_128A\nloc_124D:\nmov edx, [rbx]\ntest edi, edi\njle short loc_126B\nmov rax, rbp\nmovsxd rcx, edi\nlea rcx, [rbp+rcx*4+0]\nloc_125E:\ncmp [rax], edx\njz short loc_1244\nadd rax, 4\ncmp rax, rcx\njnz short loc_125E\nloc_126B:\ntest r8d, r8d\njle short loc_1238\nmov rax, r13\nmovsxd rcx, r8d\nlea rcx, [r13+rcx*4+0]\nloc_127B:\ncmp [rax], edx\njz short loc_12F6\nadd rax, 4\ncmp rax, rcx\njnz short loc_127B\njmp short loc_1238\nloc_128A:\nmovsxd rax, edi\nlea rcx, [rbp+rax*4+0]\nmov r8d, 0\njmp short loc_12AE\nloc_129A:\nmovsxd rax, r8d\nmov [r14+rax*4], edx\nlea r8d, [r8+1]\nloc_12A5:\nadd rsi, 4\ncmp rsi, r12\njz short loc_12CC\nloc_12AE:\nmov edx, [rsi]\ntest edi, edi\njle short loc_129A\nmov rax, rbp\nloc_12B7:\ncmp [rax], edx\njz short loc_12A5\nadd rax, 4\ncmp rcx, rax\njnz short loc_12B7\njmp short loc_129A\nloc_12C6:\nmov r8d, 0\nloc_12CC:\nmov rax, [rsp+48h+var_40]\nmov [rax], r8d\nmov rdi, r13; ptr\ncall _free\nmov rdi, rbp; ptr\ncall _free\nmov rax, r14\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_12F6:\nmovsxd rax, edi\nmov [rbp+rax*4+0], edx\nlea edi, [rdi+1]\njmp loc_1244", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11C9(int *a1, int a2, _DWORD *a3)\n{\n int *v3; // rbx\n size_t v4; // r12\n _DWORD *v5; // r14\n _DWORD *v6; // r13\n _DWORD *v7; // rbp\n int *v8; // rsi\n int *v9; // r12\n int v10; // edi\n int v11; // r8d\n int v12; // edx\n _DWORD *v13; // rax\n _DWORD *v14; // rax\n int v15; // r8d\n int v16; // edx\n _DWORD *v17; // rax\n\n v3 = a1;\n v4 = a2;\n v5 = malloc(v4 * 4);\n v6 = calloc(a2, 4uLL);\n v7 = calloc(a2, 4uLL);\n if ( a2 <= 0 )\n {\n v15 = 0;\n }\n else\n {\n v8 = a1;\n v9 = &a1[v4];\n v10 = 0;\n v11 = 0;\n do\n {\n v12 = *v3;\n if ( v10 <= 0 )\n {\nLABEL_9:\n if ( v11 <= 0 )\n {\nLABEL_3:\n v6[v11++] = v12;\n }\n else\n {\n v14 = v6;\n while ( *v14 != v12 )\n {\n if ( ++v14 == &v6[v11] )\n goto LABEL_3;\n }\n v7[v10++] = v12;\n }\n }\n else\n {\n v13 = v7;\n while ( *v13 != v12 )\n {\n if ( ++v13 == &v7[v10] )\n goto LABEL_9;\n }\n }\n ++v3;\n }\n while ( v3 != v9 );\n v15 = 0;\n do\n {\n v16 = *v8;\n if ( v10 <= 0 )\n {\nLABEL_15:\n v5[v15++] = v16;\n }\n else\n {\n v17 = v7;\n while ( *v17 != v16 )\n {\n if ( &v7[v10] == ++v17 )\n goto LABEL_15;\n }\n }\n ++v8;\n }\n while ( v8 != v9 );\n }\n *a3 = v15;\n free(v6);\n free(v7);\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11C9(int *a1, int a2, uint32_t *a3) {\n int *v3;\n unsigned int v4;\n uint32_t *v5;\n uint32_t *v6;\n uint32_t *v7;\n int *v8;\n int *v9;\n int v10;\n int v11;\n int v12;\n uint32_t *v13;\n uint32_t *v14;\n int v15;\n int v16;\n uint32_t *v17;\n v3 = a1;\n v4 = a2;\n v5 = malloc(v4 * 4);\n v6 = calloc(a2, 4uLL);\n v7 = calloc(a2, 4uLL);\n if (a2 <= 0) {\n v15 = 0;\n } else {\n v8 = a1;\n v9 = &a1[v4];\n v10 = 0;\n v11 = 0;\n do {\n v12 = *v3;\n if (v10 <= 0) {\n LABEL_9:\n if (v11 <= 0) {\n LABEL_3:\n v6[v11++] = v12;\n } else {\n v14 = v6;\n while (*v14 != v12) {\n if (++v14 == &v6[v11]) goto LABEL_3;\n }\n v7[v10++] = v12;\n }\n } else {\n v13 = v7;\n while (*v13 != v12) {\n if (++v13 == &v7[v10]) goto LABEL_9;\n }\n }\n ++v3;\n } while (v3 != v9);\n v15 = 0;\n do {\n v16 = *v8;\n if (v10 <= 0) {\n LABEL_15:\n v5[v15++] = v16;\n } else {\n v17 = v7;\n while (*v17 != v16) {\n if (&v7[v10] == ++v17) goto LABEL_15;\n }\n }\n ++v8;\n } while (v8 != v9);\n }\n *a3 = v15;\n free(v6);\n free(v7);\n return v5;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2, uint32_t *a3) {\n int *v3;\n unsigned int v4;\n uint32_t *v5;\n uint32_t *v6;\n uint32_t *v7;\n int *v8;\n int *v9;\n int v10;\n int v11;\n int v12;\n uint32_t *v13;\n uint32_t *v14;\n int v15;\n int v16;\n uint32_t *v17;\n v3 = a1;\n v4 = a2;\n v5 = malloc(v4 * 4);\n v6 = calloc(a2, 4uLL);\n v7 = calloc(a2, 4uLL);\n if (a2 <= 0) {\n v15 = 0;\n } else {\n v8 = a1;\n v9 = &a1[v4];\n v10 = 0;\n v11 = 0;\n do {\n v12 = *v3;\n if (v10 <= 0) {\n LABEL_9:\n if (v11 <= 0) {\n LABEL_3:\n v6[v11++] = v12;\n } else {\n v14 = v6;\n while (*v14 != v12) {\n if (++v14 == &v6[v11]) goto LABEL_3;\n }\n v7[v10++] = v12;\n }\n } else {\n v13 = v7;\n while (*v13 != v12) {\n if (++v13 == &v7[v10]) goto LABEL_9;\n }\n }\n ++v3;\n } while (v3 != v9);\n v15 = 0;\n do {\n v16 = *v8;\n if (v10 <= 0) {\n LABEL_15:\n v5[v15++] = v16;\n } else {\n v17 = v7;\n while (*v17 != v16) {\n if (&v7[v10] == ++v17) goto LABEL_15;\n }\n }\n ++v8;\n } while (v8 != v9);\n }\n *a3 = v15;\n free(v6);\n free(v7);\n return v5;\n}" + }, + { + "index": "HumanEval-C-26", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int* func0(int* numbers, int size, int* new_size) {\n int* out = (int*)malloc(size * sizeof(int));\n int* has1 = (int*)calloc(size, sizeof(int));\n int* has2 = (int*)calloc(size, sizeof(int));\n int has1_count = 0;\n int has2_count = 0;\n int out_count = 0;\n for (int i = 0; i < size; i++) {\n int num = numbers[i];\n int in_has2 = 0;\n for (int j = 0; j < has2_count; j++) {\n if (has2[j] == num) {\n in_has2 = 1;\n break;\n }\n }\n if (in_has2) continue;\n int in_has1 = 0;\n for (int j = 0; j < has1_count; j++) {\n if (has1[j] == num) {\n in_has1 = 1;\n break;\n }\n }\n if (in_has1) {\n has2[has2_count++] = num;\n } else {\n has1[has1_count++] = num;\n }\n }\n for (int i = 0; i < size; i++) {\n int num = numbers[i];\n int in_has2 = 0;\n for (int j = 0; j < has2_count; j++) {\n if (has2[j] == num) {\n in_has2 = 1;\n break;\n }\n }\n if (!in_has2) {\n out[out_count++] = num;\n }\n }\n *new_size = out_count;\n free(has1);\n free(has2);\n return out;\n}", + "test": "#include \n#include \n\nint issame(int* a, int a_size, int* b, int b_size) {\n if (a_size != b_size) return 0;\n for (int i = 0; i < a_size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int new_size;\n int* result;\n\n result = func0((const int[]){}, 0, &new_size);\n assert(issame(result, new_size, (const int[]){}, 0));\n free(result);\n\n result = func0((const int[]){1, 2, 3, 4}, 4, &new_size);\n assert(issame(result, new_size, (const int[]){1, 2, 3, 4}, 4));\n free(result);\n\n result = func0((const int[]){1, 2, 3, 2, 4, 3, 5}, 7, &new_size);\n assert(issame(result, new_size, (const int[]){1, 4, 5}, 3));\n free(result);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\nmovsxd r13, esi\npush r12\nlea r15, ds:0[r13*4]\nmov r12, rdx\nmov r14, r13\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rdi\nmov rdi, r15; size\ncall _malloc\nmov rdi, r13; nmemb\nmov esi, 4; size\nmov rbp, rax\ncall _calloc\nmov rdi, r13; nmemb\nmov esi, 4; size\nmov rbx, rax\ncall _calloc\nmov r13, rax\ntest r14d, r14d\njle loc_151A\nmov rsi, [rsp+48h+var_40]\nxor r9d, r9d\nxor r10d, r10d\nxor r11d, r11d\nlea r8, [rsi+r15]\nmov rdi, rsi\nnop dword ptr [rax+00000000h]\nloc_1418:\nmov edx, [rdi]\ntest r9d, r9d\njle short loc_1450\nlea rcx, [r13+r11*4+0]\nloc_1424:\nmov rax, r13\njmp short loc_1439\nloc_1430:\nadd rax, 4\ncmp rax, rcx\njz short loc_1450\nloc_1439:\ncmp [rax], edx\njnz short loc_1430\nadd rdi, 4\ncmp rdi, r8\njz short loc_1492\nmov edx, [rdi]\njmp short loc_1424\nloc_1450:\nmovsxd r14, r10d\ntest r10d, r10d\njle loc_14E8\nmovsxd r14, r10d\nmov rax, rbx\nlea rcx, [rbx+r14*4]\njmp short loc_1479\nloc_1470:\nadd rax, 4\ncmp rax, rcx\njz short loc_14E8\nloc_1479:\ncmp edx, [rax]\njnz short loc_1470\nadd r9d, 1\nmov [r13+r11*4+0], edx\nmovsxd r11, r9d\nloc_1489:\nadd rdi, 4\ncmp rdi, r8\njnz short loc_1418\nloc_1492:\nlea rcx, [r13+r11*4+0]\nxor edi, edi\nnop dword ptr [rax+00000000h]\nloc_14A0:\nmov edx, [rsi]\ntest r9d, r9d\njle short loc_14D0\nloc_14A7:\nmov rax, r13\njmp short loc_14B9\nloc_14B0:\nadd rax, 4\ncmp rcx, rax\njz short loc_14D0\nloc_14B9:\ncmp edx, [rax]\njnz short loc_14B0\nadd rsi, 4\ncmp rsi, r8\njz short loc_14F2\nmov edx, [rsi]\njmp short loc_14A7\nloc_14D0:\nadd rsi, 4\nmov [rbp+rdi*4+0], edx\nlea eax, [rdi+1]\ncmp rsi, r8\njz short loc_14F4\nmovsxd rdi, eax\njmp short loc_14A0\nloc_14E8:\nmov [rbx+r14*4], edx\nadd r10d, 1\njmp short loc_1489\nloc_14F2:\nmov eax, edi\nloc_14F4:\nmov [r12], eax\nmov rdi, rbx; ptr\ncall _free\nmov rdi, r13; ptr\ncall _free\nadd rsp, 18h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_151A:\nxor eax, eax\njmp short loc_14F4", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2, _DWORD *a3)\n{\n size_t v3; // r15\n _DWORD *v5; // rbp\n _DWORD *v6; // rbx\n _DWORD *v7; // r13\n int *v8; // rsi\n int v9; // r9d\n int v10; // r10d\n __int64 v11; // r11\n int *v12; // r8\n int v13; // edx\n _DWORD *v14; // rax\n __int64 v15; // r14\n _DWORD *v16; // rax\n __int64 i; // rdi\n int v18; // edx\n _DWORD *v19; // rax\n int v20; // eax\n\n v3 = a2;\n v5 = malloc(v3 * 4);\n v6 = calloc(a2, 4uLL);\n v7 = calloc(a2, 4uLL);\n if ( a2 <= 0 )\n {\n v20 = 0;\n }\n else\n {\n v8 = a1;\n v9 = 0;\n v10 = 0;\n v11 = 0LL;\n v12 = &a1[v3];\n while ( 1 )\n {\n v13 = *a1;\n if ( v9 > 0 )\n break;\nLABEL_9:\n v15 = v10;\n if ( v10 <= 0 )\n {\nLABEL_24:\n v6[v15] = v13;\n ++v10;\n }\n else\n {\n v15 = v10;\n v16 = v6;\n while ( v13 != *v16 )\n {\n if ( ++v16 == &v6[v10] )\n goto LABEL_24;\n }\n ++v9;\n v7[v11] = v13;\n v11 = v9;\n }\n if ( ++a1 == v12 )\n goto LABEL_15;\n }\n while ( 1 )\n {\n v14 = v7;\n while ( *v14 != v13 )\n {\n if ( ++v14 == &v7[v11] )\n goto LABEL_9;\n }\n if ( ++a1 == v12 )\n break;\n v13 = *a1;\n }\nLABEL_15:\n for ( i = 0LL; ; i = v20 )\n {\n v18 = *v8;\n if ( v9 > 0 )\n break;\nLABEL_22:\n ++v8;\n v5[i] = v18;\n v20 = i + 1;\n if ( v8 == v12 )\n goto LABEL_26;\n }\n while ( 1 )\n {\n v19 = v7;\n while ( v18 != *v19 )\n {\n if ( &v7[v11] == ++v19 )\n goto LABEL_22;\n }\n if ( ++v8 == v12 )\n break;\n v18 = *v8;\n }\n v20 = i;\n }\nLABEL_26:\n *a3 = v20;\n free(v6);\n free(v7);\n return v5;\n}", + "ida_strip_asm": "sub_13A0:\nendbr64\npush r15\npush r14\npush r13\nmovsxd r13, esi\npush r12\nlea r15, ds:0[r13*4]\nmov r12, rdx\nmov r14, r13\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rdi\nmov rdi, r15; size\ncall _malloc\nmov rdi, r13; nmemb\nmov esi, 4; size\nmov rbp, rax\ncall _calloc\nmov rdi, r13; nmemb\nmov esi, 4; size\nmov rbx, rax\ncall _calloc\nmov r13, rax\ntest r14d, r14d\njle loc_151A\nmov rsi, [rsp+48h+var_40]\nxor r9d, r9d\nxor r10d, r10d\nxor r11d, r11d\nlea r8, [rsi+r15]\nmov rdi, rsi\nnop dword ptr [rax+00000000h]\nloc_1418:\nmov edx, [rdi]\ntest r9d, r9d\njle short loc_1450\nlea rcx, [r13+r11*4+0]\nloc_1424:\nmov rax, r13\njmp short loc_1439\nloc_1430:\nadd rax, 4\ncmp rax, rcx\njz short loc_1450\nloc_1439:\ncmp [rax], edx\njnz short loc_1430\nadd rdi, 4\ncmp rdi, r8\njz short loc_1492\nmov edx, [rdi]\njmp short loc_1424\nloc_1450:\nmovsxd r14, r10d\ntest r10d, r10d\njle loc_14E8\nmovsxd r14, r10d\nmov rax, rbx\nlea rcx, [rbx+r14*4]\njmp short loc_1479\nloc_1470:\nadd rax, 4\ncmp rax, rcx\njz short loc_14E8\nloc_1479:\ncmp edx, [rax]\njnz short loc_1470\nadd r9d, 1\nmov [r13+r11*4+0], edx\nmovsxd r11, r9d\nloc_1489:\nadd rdi, 4\ncmp rdi, r8\njnz short loc_1418\nloc_1492:\nlea rcx, [r13+r11*4+0]\nxor edi, edi\nnop dword ptr [rax+00000000h]\nloc_14A0:\nmov edx, [rsi]\ntest r9d, r9d\njle short loc_14D0\nloc_14A7:\nmov rax, r13\njmp short loc_14B9\nloc_14B0:\nadd rax, 4\ncmp rcx, rax\njz short loc_14D0\nloc_14B9:\ncmp edx, [rax]\njnz short loc_14B0\nadd rsi, 4\ncmp rsi, r8\njz short loc_14F2\nmov edx, [rsi]\njmp short loc_14A7\nloc_14D0:\nadd rsi, 4\nmov [rbp+rdi*4+0], edx\nlea eax, [rdi+1]\ncmp rsi, r8\njz short loc_14F4\nmovsxd rdi, eax\njmp short loc_14A0\nloc_14E8:\nmov [rbx+r14*4], edx\nadd r10d, 1\njmp short loc_1489\nloc_14F2:\nmov eax, edi\nloc_14F4:\nmov [r12], eax\nmov rdi, rbx; ptr\ncall _free\nmov rdi, r13; ptr\ncall _free\nadd rsp, 18h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_151A:\nxor eax, eax\njmp short loc_14F4", + "ida_strip_pseudo": "_DWORD *__fastcall sub_13A0(int *a1, int a2, _DWORD *a3)\n{\n size_t v3; // r15\n _DWORD *v5; // rbp\n _DWORD *v6; // rbx\n _DWORD *v7; // r13\n int *v8; // rsi\n int v9; // r9d\n int v10; // r10d\n __int64 v11; // r11\n int *v12; // r8\n int v13; // edx\n _DWORD *v14; // rax\n __int64 v15; // r14\n _DWORD *v16; // rax\n __int64 i; // rdi\n int v18; // edx\n _DWORD *v19; // rax\n int v20; // eax\n\n v3 = a2;\n v5 = malloc(v3 * 4);\n v6 = calloc(a2, 4uLL);\n v7 = calloc(a2, 4uLL);\n if ( a2 <= 0 )\n {\n v20 = 0;\n }\n else\n {\n v8 = a1;\n v9 = 0;\n v10 = 0;\n v11 = 0LL;\n v12 = &a1[v3];\n while ( 1 )\n {\n v13 = *a1;\n if ( v9 > 0 )\n break;\nLABEL_9:\n v15 = v10;\n if ( v10 <= 0 )\n {\nLABEL_24:\n v6[v15] = v13;\n ++v10;\n }\n else\n {\n v15 = v10;\n v16 = v6;\n while ( v13 != *v16 )\n {\n if ( ++v16 == &v6[v10] )\n goto LABEL_24;\n }\n ++v9;\n v7[v11] = v13;\n v11 = v9;\n }\n if ( ++a1 == v12 )\n goto LABEL_15;\n }\n while ( 1 )\n {\n v14 = v7;\n while ( *v14 != v13 )\n {\n if ( ++v14 == &v7[v11] )\n goto LABEL_9;\n }\n if ( ++a1 == v12 )\n break;\n v13 = *a1;\n }\nLABEL_15:\n for ( i = 0LL; ; i = v20 )\n {\n v18 = *v8;\n if ( v9 > 0 )\n break;\nLABEL_22:\n ++v8;\n v5[i] = v18;\n v20 = i + 1;\n if ( v8 == v12 )\n goto LABEL_26;\n }\n while ( 1 )\n {\n v19 = v7;\n while ( v18 != *v19 )\n {\n if ( &v7[v11] == ++v19 )\n goto LABEL_22;\n }\n if ( ++v8 == v12 )\n break;\n v18 = *v8;\n }\n v20 = i;\n }\nLABEL_26:\n *a3 = v20;\n free(v6);\n free(v7);\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_13A0(int *a1, int a2, uint32_t *a3) {\n unsigned int v3;\n uint32_t *v5;\n uint32_t *v6;\n uint32_t *v7;\n int *v8;\n int v9;\n int v10;\n long long v11;\n int *v12;\n int v13;\n uint32_t *v14;\n long long v15;\n uint32_t *v16;\n long long i;\n int v18;\n uint32_t *v19;\n int v20;\n v3 = a2;\n v5 = malloc(v3 * 4);\n v6 = calloc(a2, 4uLL);\n v7 = calloc(a2, 4uLL);\n if (a2 <= 0) {\n v20 = 0;\n } else {\n v8 = a1;\n v9 = 0;\n v10 = 0;\n v11 = 0LL;\n v12 = &a1[v3];\n while (1) {\n v13 = *a1;\n if (v9 > 0) break;\n LABEL_9:\n v15 = v10;\n if (v10 <= 0) {\n LABEL_24:\n v6[v15] = v13;\n ++v10;\n } else {\n v15 = v10;\n v16 = v6;\n while (v13 != *v16) {\n if (++v16 == &v6[v10]) goto LABEL_24;\n }\n ++v9;\n v7[v11] = v13;\n v11 = v9;\n }\n if (++a1 == v12) goto LABEL_15;\n }\n while (1) {\n v14 = v7;\n while (*v14 != v13) {\n if (++v14 == &v7[v11]) goto LABEL_9;\n }\n if (++a1 == v12) break;\n v13 = *a1;\n }\n LABEL_15:\n for (i = 0LL;; i = v20) {\n v18 = *v8;\n if (v9 > 0) break;\n LABEL_22:\n ++v8;\n v5[i] = v18;\n v20 = i + 1;\n if (v8 == v12) goto LABEL_26;\n }\n while (1) {\n v19 = v7;\n while (v18 != *v19) {\n if (&v7[v11] == ++v19) goto LABEL_22;\n }\n if (++v8 == v12) break;\n v18 = *v8;\n }\n v20 = i;\n }\nLABEL_26:\n *a3 = v20;\n free(v6);\n free(v7);\n return v5;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2, uint32_t *a3) {\n unsigned int v3;\n uint32_t *v5;\n uint32_t *v6;\n uint32_t *v7;\n int *v8;\n int v9;\n int v10;\n long long v11;\n int *v12;\n int v13;\n uint32_t *v14;\n long long v15;\n uint32_t *v16;\n long long i;\n int v18;\n uint32_t *v19;\n int v20;\n v3 = a2;\n v5 = malloc(v3 * 4);\n v6 = calloc(a2, 4uLL);\n v7 = calloc(a2, 4uLL);\n if (a2 <= 0) {\n v20 = 0;\n } else {\n v8 = a1;\n v9 = 0;\n v10 = 0;\n v11 = 0LL;\n v12 = &a1[v3];\n while (1) {\n v13 = *a1;\n if (v9 > 0) break;\n LABEL_9:\n v15 = v10;\n if (v10 <= 0) {\n LABEL_24:\n v6[v15] = v13;\n ++v10;\n } else {\n v15 = v10;\n v16 = v6;\n while (v13 != *v16) {\n if (++v16 == &v6[v10]) goto LABEL_24;\n }\n ++v9;\n v7[v11] = v13;\n v11 = v9;\n }\n if (++a1 == v12) goto LABEL_15;\n }\n while (1) {\n v14 = v7;\n while (*v14 != v13) {\n if (++v14 == &v7[v11]) goto LABEL_9;\n }\n if (++a1 == v12) break;\n v13 = *a1;\n }\n LABEL_15:\n for (i = 0LL;; i = v20) {\n v18 = *v8;\n if (v9 > 0) break;\n LABEL_22:\n ++v8;\n v5[i] = v18;\n v20 = i + 1;\n if (v8 == v12) goto LABEL_26;\n }\n while (1) {\n v19 = v7;\n while (v18 != *v19) {\n if (&v7[v11] == ++v19) goto LABEL_22;\n }\n if (++v8 == v12) break;\n v18 = *v8;\n }\n v20 = i;\n }\nLABEL_26:\n *a3 = v20;\n free(v6);\n free(v7);\n return v5;\n}" + }, + { + "index": "HumanEval-C-26", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int* func0(int* numbers, int size, int* new_size) {\n int* out = (int*)malloc(size * sizeof(int));\n int* has1 = (int*)calloc(size, sizeof(int));\n int* has2 = (int*)calloc(size, sizeof(int));\n int has1_count = 0;\n int has2_count = 0;\n int out_count = 0;\n for (int i = 0; i < size; i++) {\n int num = numbers[i];\n int in_has2 = 0;\n for (int j = 0; j < has2_count; j++) {\n if (has2[j] == num) {\n in_has2 = 1;\n break;\n }\n }\n if (in_has2) continue;\n int in_has1 = 0;\n for (int j = 0; j < has1_count; j++) {\n if (has1[j] == num) {\n in_has1 = 1;\n break;\n }\n }\n if (in_has1) {\n has2[has2_count++] = num;\n } else {\n has1[has1_count++] = num;\n }\n }\n for (int i = 0; i < size; i++) {\n int num = numbers[i];\n int in_has2 = 0;\n for (int j = 0; j < has2_count; j++) {\n if (has2[j] == num) {\n in_has2 = 1;\n break;\n }\n }\n if (!in_has2) {\n out[out_count++] = num;\n }\n }\n *new_size = out_count;\n free(has1);\n free(has2);\n return out;\n}", + "test": "#include \n#include \n\nint issame(int* a, int a_size, int* b, int b_size) {\n if (a_size != b_size) return 0;\n for (int i = 0; i < a_size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int new_size;\n int* result;\n\n result = func0((const int[]){}, 0, &new_size);\n assert(issame(result, new_size, (const int[]){}, 0));\n free(result);\n\n result = func0((const int[]){1, 2, 3, 4}, 4, &new_size);\n assert(issame(result, new_size, (const int[]){1, 2, 3, 4}, 4));\n free(result);\n\n result = func0((const int[]){1, 2, 3, 2, 4, 3, 5}, 7, &new_size);\n assert(issame(result, new_size, (const int[]){1, 4, 5}, 3));\n free(result);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\nmovsxd r13, esi\npush r12\nlea r15, ds:0[r13*4]\nmov r12, rdx\nmov r14, r13\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rdi\nmov rdi, r15; size\ncall _malloc\nmov rdi, r13; nmemb\nmov esi, 4; size\nmov rbp, rax\ncall _calloc\nmov rdi, r13; nmemb\nmov esi, 4; size\nmov rbx, rax\ncall _calloc\nmov r13, rax\ntest r14d, r14d\njle loc_151A\nmov rsi, [rsp+48h+var_40]\nxor r9d, r9d\nxor r10d, r10d\nxor r11d, r11d\nlea r8, [rsi+r15]\nmov rdi, rsi\nnop dword ptr [rax+00000000h]\nloc_1418:\nmov edx, [rdi]\ntest r9d, r9d\njle short loc_1450\nlea rcx, [r13+r11*4+0]\nloc_1424:\nmov rax, r13\njmp short loc_1439\nloc_1430:\nadd rax, 4\ncmp rax, rcx\njz short loc_1450\nloc_1439:\ncmp [rax], edx\njnz short loc_1430\nadd rdi, 4\ncmp rdi, r8\njz short loc_1492\nmov edx, [rdi]\njmp short loc_1424\nloc_1450:\nmovsxd r14, r10d\ntest r10d, r10d\njle loc_14E8\nmovsxd r14, r10d\nmov rax, rbx\nlea rcx, [rbx+r14*4]\njmp short loc_1479\nloc_1470:\nadd rax, 4\ncmp rax, rcx\njz short loc_14E8\nloc_1479:\ncmp edx, [rax]\njnz short loc_1470\nadd r9d, 1\nmov [r13+r11*4+0], edx\nmovsxd r11, r9d\nloc_1489:\nadd rdi, 4\ncmp rdi, r8\njnz short loc_1418\nloc_1492:\nlea rcx, [r13+r11*4+0]\nxor edi, edi\nnop dword ptr [rax+00000000h]\nloc_14A0:\nmov edx, [rsi]\ntest r9d, r9d\njle short loc_14D0\nloc_14A7:\nmov rax, r13\njmp short loc_14B9\nloc_14B0:\nadd rax, 4\ncmp rcx, rax\njz short loc_14D0\nloc_14B9:\ncmp edx, [rax]\njnz short loc_14B0\nadd rsi, 4\ncmp rsi, r8\njz short loc_14F2\nmov edx, [rsi]\njmp short loc_14A7\nloc_14D0:\nadd rsi, 4\nmov [rbp+rdi*4+0], edx\nlea eax, [rdi+1]\ncmp rsi, r8\njz short loc_14F4\nmovsxd rdi, eax\njmp short loc_14A0\nloc_14E8:\nmov [rbx+r14*4], edx\nadd r10d, 1\njmp short loc_1489\nloc_14F2:\nmov eax, edi\nloc_14F4:\nmov [r12], eax\nmov rdi, rbx; ptr\ncall _free\nmov rdi, r13; ptr\ncall _free\nadd rsp, 18h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_151A:\nxor eax, eax\njmp short loc_14F4", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2, _DWORD *a3)\n{\n size_t v3; // r15\n _DWORD *v5; // rbp\n _DWORD *v6; // rbx\n _DWORD *v7; // r13\n int *v8; // rsi\n int v9; // r9d\n int v10; // r10d\n __int64 v11; // r11\n int *v12; // r8\n int v13; // edx\n _DWORD *v14; // rax\n __int64 v15; // r14\n _DWORD *v16; // rax\n __int64 i; // rdi\n int v18; // edx\n _DWORD *v19; // rax\n int v20; // eax\n\n v3 = a2;\n v5 = malloc(v3 * 4);\n v6 = calloc(a2, 4uLL);\n v7 = calloc(a2, 4uLL);\n if ( a2 <= 0 )\n {\n v20 = 0;\n }\n else\n {\n v8 = a1;\n v9 = 0;\n v10 = 0;\n v11 = 0LL;\n v12 = &a1[v3];\n while ( 1 )\n {\n v13 = *a1;\n if ( v9 > 0 )\n break;\nLABEL_9:\n v15 = v10;\n if ( v10 <= 0 )\n {\nLABEL_24:\n v6[v15] = v13;\n ++v10;\n }\n else\n {\n v15 = v10;\n v16 = v6;\n while ( v13 != *v16 )\n {\n if ( ++v16 == &v6[v10] )\n goto LABEL_24;\n }\n ++v9;\n v7[v11] = v13;\n v11 = v9;\n }\n if ( ++a1 == v12 )\n goto LABEL_15;\n }\n while ( 1 )\n {\n v14 = v7;\n while ( *v14 != v13 )\n {\n if ( ++v14 == &v7[v11] )\n goto LABEL_9;\n }\n if ( ++a1 == v12 )\n break;\n v13 = *a1;\n }\nLABEL_15:\n for ( i = 0LL; ; i = v20 )\n {\n v18 = *v8;\n if ( v9 > 0 )\n break;\nLABEL_22:\n ++v8;\n v5[i] = v18;\n v20 = i + 1;\n if ( v8 == v12 )\n goto LABEL_26;\n }\n while ( 1 )\n {\n v19 = v7;\n while ( v18 != *v19 )\n {\n if ( &v7[v11] == ++v19 )\n goto LABEL_22;\n }\n if ( ++v8 == v12 )\n break;\n v18 = *v8;\n }\n v20 = i;\n }\nLABEL_26:\n *a3 = v20;\n free(v6);\n free(v7);\n return v5;\n}", + "ida_strip_asm": "sub_13A0:\nendbr64\npush r15\npush r14\npush r13\nmovsxd r13, esi\npush r12\nlea r15, ds:0[r13*4]\nmov r12, rdx\nmov r14, r13\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rdi\nmov rdi, r15; size\ncall _malloc\nmov rdi, r13; nmemb\nmov esi, 4; size\nmov rbp, rax\ncall _calloc\nmov rdi, r13; nmemb\nmov esi, 4; size\nmov rbx, rax\ncall _calloc\nmov r13, rax\ntest r14d, r14d\njle loc_151A\nmov rsi, [rsp+48h+var_40]\nxor r9d, r9d\nxor r10d, r10d\nxor r11d, r11d\nlea r8, [rsi+r15]\nmov rdi, rsi\nnop dword ptr [rax+00000000h]\nloc_1418:\nmov edx, [rdi]\ntest r9d, r9d\njle short loc_1450\nlea rcx, [r13+r11*4+0]\nloc_1424:\nmov rax, r13\njmp short loc_1439\nloc_1430:\nadd rax, 4\ncmp rax, rcx\njz short loc_1450\nloc_1439:\ncmp [rax], edx\njnz short loc_1430\nadd rdi, 4\ncmp rdi, r8\njz short loc_1492\nmov edx, [rdi]\njmp short loc_1424\nloc_1450:\nmovsxd r14, r10d\ntest r10d, r10d\njle loc_14E8\nmovsxd r14, r10d\nmov rax, rbx\nlea rcx, [rbx+r14*4]\njmp short loc_1479\nloc_1470:\nadd rax, 4\ncmp rax, rcx\njz short loc_14E8\nloc_1479:\ncmp edx, [rax]\njnz short loc_1470\nadd r9d, 1\nmov [r13+r11*4+0], edx\nmovsxd r11, r9d\nloc_1489:\nadd rdi, 4\ncmp rdi, r8\njnz short loc_1418\nloc_1492:\nlea rcx, [r13+r11*4+0]\nxor edi, edi\nnop dword ptr [rax+00000000h]\nloc_14A0:\nmov edx, [rsi]\ntest r9d, r9d\njle short loc_14D0\nloc_14A7:\nmov rax, r13\njmp short loc_14B9\nloc_14B0:\nadd rax, 4\ncmp rcx, rax\njz short loc_14D0\nloc_14B9:\ncmp edx, [rax]\njnz short loc_14B0\nadd rsi, 4\ncmp rsi, r8\njz short loc_14F2\nmov edx, [rsi]\njmp short loc_14A7\nloc_14D0:\nadd rsi, 4\nmov [rbp+rdi*4+0], edx\nlea eax, [rdi+1]\ncmp rsi, r8\njz short loc_14F4\nmovsxd rdi, eax\njmp short loc_14A0\nloc_14E8:\nmov [rbx+r14*4], edx\nadd r10d, 1\njmp short loc_1489\nloc_14F2:\nmov eax, edi\nloc_14F4:\nmov [r12], eax\nmov rdi, rbx; ptr\ncall _free\nmov rdi, r13; ptr\ncall _free\nadd rsp, 18h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_151A:\nxor eax, eax\njmp short loc_14F4", + "ida_strip_pseudo": "_DWORD *__fastcall sub_13A0(int *a1, int a2, _DWORD *a3)\n{\n size_t v3; // r15\n _DWORD *v5; // rbp\n _DWORD *v6; // rbx\n _DWORD *v7; // r13\n int *v8; // rsi\n int v9; // r9d\n int v10; // r10d\n __int64 v11; // r11\n int *v12; // r8\n int v13; // edx\n _DWORD *v14; // rax\n __int64 v15; // r14\n _DWORD *v16; // rax\n __int64 i; // rdi\n int v18; // edx\n _DWORD *v19; // rax\n int v20; // eax\n\n v3 = a2;\n v5 = malloc(v3 * 4);\n v6 = calloc(a2, 4uLL);\n v7 = calloc(a2, 4uLL);\n if ( a2 <= 0 )\n {\n v20 = 0;\n }\n else\n {\n v8 = a1;\n v9 = 0;\n v10 = 0;\n v11 = 0LL;\n v12 = &a1[v3];\n while ( 1 )\n {\n v13 = *a1;\n if ( v9 > 0 )\n break;\nLABEL_9:\n v15 = v10;\n if ( v10 <= 0 )\n {\nLABEL_24:\n v6[v15] = v13;\n ++v10;\n }\n else\n {\n v15 = v10;\n v16 = v6;\n while ( v13 != *v16 )\n {\n if ( ++v16 == &v6[v10] )\n goto LABEL_24;\n }\n ++v9;\n v7[v11] = v13;\n v11 = v9;\n }\n if ( ++a1 == v12 )\n goto LABEL_15;\n }\n while ( 1 )\n {\n v14 = v7;\n while ( *v14 != v13 )\n {\n if ( ++v14 == &v7[v11] )\n goto LABEL_9;\n }\n if ( ++a1 == v12 )\n break;\n v13 = *a1;\n }\nLABEL_15:\n for ( i = 0LL; ; i = v20 )\n {\n v18 = *v8;\n if ( v9 > 0 )\n break;\nLABEL_22:\n ++v8;\n v5[i] = v18;\n v20 = i + 1;\n if ( v8 == v12 )\n goto LABEL_26;\n }\n while ( 1 )\n {\n v19 = v7;\n while ( v18 != *v19 )\n {\n if ( &v7[v11] == ++v19 )\n goto LABEL_22;\n }\n if ( ++v8 == v12 )\n break;\n v18 = *v8;\n }\n v20 = i;\n }\nLABEL_26:\n *a3 = v20;\n free(v6);\n free(v7);\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_13A0(int *a1, int a2, uint32_t *a3) {\n unsigned int v3;\n uint32_t *v5;\n uint32_t *v6;\n uint32_t *v7;\n int *v8;\n int v9;\n int v10;\n long long v11;\n int *v12;\n int v13;\n uint32_t *v14;\n long long v15;\n uint32_t *v16;\n long long i;\n int v18;\n uint32_t *v19;\n int v20;\n v3 = a2;\n v5 = malloc(v3 * 4);\n v6 = calloc(a2, 4uLL);\n v7 = calloc(a2, 4uLL);\n if (a2 <= 0) {\n v20 = 0;\n } else {\n v8 = a1;\n v9 = 0;\n v10 = 0;\n v11 = 0LL;\n v12 = &a1[v3];\n while (1) {\n v13 = *a1;\n if (v9 > 0) break;\n LABEL_9:\n v15 = v10;\n if (v10 <= 0) {\n LABEL_24:\n v6[v15] = v13;\n ++v10;\n } else {\n v15 = v10;\n v16 = v6;\n while (v13 != *v16) {\n if (++v16 == &v6[v10]) goto LABEL_24;\n }\n ++v9;\n v7[v11] = v13;\n v11 = v9;\n }\n if (++a1 == v12) goto LABEL_15;\n }\n while (1) {\n v14 = v7;\n while (*v14 != v13) {\n if (++v14 == &v7[v11]) goto LABEL_9;\n }\n if (++a1 == v12) break;\n v13 = *a1;\n }\n LABEL_15:\n for (i = 0LL;; i = v20) {\n v18 = *v8;\n if (v9 > 0) break;\n LABEL_22:\n ++v8;\n v5[i] = v18;\n v20 = i + 1;\n if (v8 == v12) goto LABEL_26;\n }\n while (1) {\n v19 = v7;\n while (v18 != *v19) {\n if (&v7[v11] == ++v19) goto LABEL_22;\n }\n if (++v8 == v12) break;\n v18 = *v8;\n }\n v20 = i;\n }\nLABEL_26:\n *a3 = v20;\n free(v6);\n free(v7);\n return v5;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2, uint32_t *a3) {\n unsigned int v3;\n uint32_t *v5;\n uint32_t *v6;\n uint32_t *v7;\n int *v8;\n int v9;\n int v10;\n long long v11;\n int *v12;\n int v13;\n uint32_t *v14;\n long long v15;\n uint32_t *v16;\n long long i;\n int v18;\n uint32_t *v19;\n int v20;\n v3 = a2;\n v5 = malloc(v3 * 4);\n v6 = calloc(a2, 4uLL);\n v7 = calloc(a2, 4uLL);\n if (a2 <= 0) {\n v20 = 0;\n } else {\n v8 = a1;\n v9 = 0;\n v10 = 0;\n v11 = 0LL;\n v12 = &a1[v3];\n while (1) {\n v13 = *a1;\n if (v9 > 0) break;\n LABEL_9:\n v15 = v10;\n if (v10 <= 0) {\n LABEL_24:\n v6[v15] = v13;\n ++v10;\n } else {\n v15 = v10;\n v16 = v6;\n while (v13 != *v16) {\n if (++v16 == &v6[v10]) goto LABEL_24;\n }\n ++v9;\n v7[v11] = v13;\n v11 = v9;\n }\n if (++a1 == v12) goto LABEL_15;\n }\n while (1) {\n v14 = v7;\n while (*v14 != v13) {\n if (++v14 == &v7[v11]) goto LABEL_9;\n }\n if (++a1 == v12) break;\n v13 = *a1;\n }\n LABEL_15:\n for (i = 0LL;; i = v20) {\n v18 = *v8;\n if (v9 > 0) break;\n LABEL_22:\n ++v8;\n v5[i] = v18;\n v20 = i + 1;\n if (v8 == v12) goto LABEL_26;\n }\n while (1) {\n v19 = v7;\n while (v18 != *v19) {\n if (&v7[v11] == ++v19) goto LABEL_22;\n }\n if (++v8 == v12) break;\n v18 = *v8;\n }\n v20 = i;\n }\nLABEL_26:\n *a3 = v20;\n free(v6);\n free(v7);\n return v5;\n}" + }, + { + "index": "HumanEval-C-27", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(const char* str, char* out) {\n int length = strlen(str);\n for (int i = 0; i < length; i++) {\n char w = str[i];\n if (w >= 'a' && w <= 'z') {\n w -= 32;\n } else if (w >= 'A' && w <= 'Z') {\n w += 32;\n }\n out[i] = w;\n }\n out[length] = '\\0';\n}", + "test": "#include \n#include \n\nint main() {\n char result[100]; // Buffer large enough for test cases\n\n func0(\"\", result);\n assert(strcmp(result, \"\") == 0);\n\n func0(\"Hello!\", result);\n assert(strcmp(result, \"hELLO!\") == 0);\n\n func0(\"These violent delights have violent ends\", result);\n assert(strcmp(result, \"tHESE VIOLENT DELIGHTS HAVE VIOLENT ENDS\") == 0);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov [rbp+var_20], rsi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_8], 0\njmp short loc_122D\nloc_11D5:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_9], al\ncmp [rbp+var_9], 60h ; '`'\njle short loc_1200\ncmp [rbp+var_9], 7Ah ; 'z'\njg short loc_1200\nmovzx eax, [rbp+var_9]\nsub eax, 20h ; ' '\nmov [rbp+var_9], al\njmp short loc_1216\nloc_1200:\ncmp [rbp+var_9], 40h ; '@'\njle short loc_1216\ncmp [rbp+var_9], 5Ah ; 'Z'\njg short loc_1216\nmovzx eax, [rbp+var_9]\nadd eax, 20h ; ' '\nmov [rbp+var_9], al\nloc_1216:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+var_20]\nadd rdx, rax\nmovzx eax, [rbp+var_9]\nmov [rdx], al\nadd [rbp+var_8], 1\nloc_122D:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njl short loc_11D5\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov byte ptr [rax], 0\nnop\nleave\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1, __int64 a2)\n{\n _BYTE *result; // rax\n char v3; // [rsp+17h] [rbp-9h]\n int i; // [rsp+18h] [rbp-8h]\n int v5; // [rsp+1Ch] [rbp-4h]\n\n v5 = strlen(a1);\n for ( i = 0; i < v5; ++i )\n {\n v3 = a1[i];\n if ( v3 <= 96 || v3 > 122 )\n {\n if ( v3 > 64 && v3 <= 90 )\n v3 += 32;\n }\n else\n {\n v3 -= 32;\n }\n *(_BYTE *)(a2 + i) = v3;\n }\n result = (_BYTE *)(v5 + a2);\n *result = 0;\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov [rbp+var_20], rsi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_8], 0\njmp short loc_122D\nloc_11D5:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_9], al\ncmp [rbp+var_9], 60h ; '`'\njle short loc_1200\ncmp [rbp+var_9], 7Ah ; 'z'\njg short loc_1200\nmovzx eax, [rbp+var_9]\nsub eax, 20h ; ' '\nmov [rbp+var_9], al\njmp short loc_1216\nloc_1200:\ncmp [rbp+var_9], 40h ; '@'\njle short loc_1216\ncmp [rbp+var_9], 5Ah ; 'Z'\njg short loc_1216\nmovzx eax, [rbp+var_9]\nadd eax, 20h ; ' '\nmov [rbp+var_9], al\nloc_1216:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+var_20]\nadd rdx, rax\nmovzx eax, [rbp+var_9]\nmov [rdx], al\nadd [rbp+var_8], 1\nloc_122D:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njl short loc_11D5\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov byte ptr [rax], 0\nnop\nleave\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_11A9(const char *a1, __int64 a2)\n{\n _BYTE *result; // rax\n char v3; // [rsp+17h] [rbp-9h]\n int i; // [rsp+18h] [rbp-8h]\n int v5; // [rsp+1Ch] [rbp-4h]\n\n v5 = strlen(a1);\n for ( i = 0; i < v5; ++i )\n {\n v3 = a1[i];\n if ( v3 <= 96 || v3 > 122 )\n {\n if ( v3 > 64 && v3 <= 90 )\n v3 += 32;\n }\n else\n {\n v3 -= 32;\n }\n *(_BYTE *)(a2 + i) = v3;\n }\n result = (_BYTE *)(v5 + a2);\n *result = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_11A9(const char *a1, long long a2) {\n uint8_t *result;\n char v3;\n int i;\n int v5;\n v5 = strlen(a1);\n for (i = 0; i < v5; ++i) {\n v3 = a1[i];\n if (v3 <= 96 || v3 > 122) {\n if (v3 > 64 && v3 <= 90) v3 += 32;\n } else {\n v3 -= 32;\n }\n *(uint8_t *)(a2 + i) = v3;\n }\n result = (uint8_t *)(v5 + a2);\n *result = 0;\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1, long long a2) {\n uint8_t *result;\n char v3;\n int i;\n int v5;\n v5 = strlen(a1);\n for (i = 0; i < v5; ++i) {\n v3 = a1[i];\n if (v3 <= 96 || v3 > 122) {\n if (v3 > 64 && v3 <= 90) v3 += 32;\n } else {\n v3 -= 32;\n }\n *(uint8_t *)(a2 + i) = v3;\n }\n result = (uint8_t *)(v5 + a2);\n *result = 0;\n return result;\n}" + }, + { + "index": "HumanEval-C-27", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(const char* str, char* out) {\n int length = strlen(str);\n for (int i = 0; i < length; i++) {\n char w = str[i];\n if (w >= 'a' && w <= 'z') {\n w -= 32;\n } else if (w >= 'A' && w <= 'Z') {\n w += 32;\n }\n out[i] = w;\n }\n out[length] = '\\0';\n}", + "test": "#include \n#include \n\nint main() {\n char result[100]; // Buffer large enough for test cases\n\n func0(\"\", result);\n assert(strcmp(result, \"\") == 0);\n\n func0(\"Hello!\", result);\n assert(strcmp(result, \"hELLO!\") == 0);\n\n func0(\"These violent delights have violent ends\", result);\n assert(strcmp(result, \"tHESE VIOLENT DELIGHTS HAVE VIOLENT ENDS\") == 0);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov rbx, rsi\ncall _strlen\ntest eax, eax\njle short loc_11FE\nlea r8d, [rax-1]\nmov ecx, 0\njmp short loc_11E9\nloc_11CD:\nlea edi, [rdx-41h]\nadd esi, 20h ; ' '\ncmp dil, 1Ah\ncmovb edx, esi\nloc_11DA:\nmov [rbx+rcx], dl\nlea rdx, [rcx+1]\ncmp rcx, r8\njz short loc_11FE\nmov rcx, rdx\nloc_11E9:\nmovzx edx, byte ptr [rbp+rcx+0]\nmov esi, edx\nlea edi, [rdx-61h]\ncmp dil, 19h\nja short loc_11CD\nsub edx, 20h ; ' '\njmp short loc_11DA\nloc_11FE:\ncdqe\nmov byte ptr [rbx+rax], 0\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, __int64 a2)\n{\n __int64 result; // rax\n __int64 i; // rcx\n char v4; // dl\n\n LODWORD(result) = strlen(a1);\n if ( (int)result > 0 )\n {\n for ( i = 0LL; ; ++i )\n {\n v4 = a1[i];\n if ( (unsigned __int8)(v4 - 97) > 0x19u )\n {\n if ( (unsigned __int8)(v4 - 65) < 0x1Au )\n v4 = a1[i] + 32;\n }\n else\n {\n v4 -= 32;\n }\n *(_BYTE *)(a2 + i) = v4;\n if ( i == (_DWORD)result - 1 )\n break;\n }\n }\n result = (int)result;\n *(_BYTE *)(a2 + (int)result) = 0;\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov rbx, rsi\ncall _strlen\ntest eax, eax\njle short loc_11FE\nlea r8d, [rax-1]\nmov ecx, 0\njmp short loc_11E9\nloc_11CD:\nlea edi, [rdx-41h]\nadd esi, 20h ; ' '\ncmp dil, 1Ah\ncmovb edx, esi\nloc_11DA:\nmov [rbx+rcx], dl\nlea rdx, [rcx+1]\ncmp rcx, r8\njz short loc_11FE\nmov rcx, rdx\nloc_11E9:\nmovzx edx, byte ptr [rbp+rcx+0]\nmov esi, edx\nlea edi, [rdx-61h]\ncmp dil, 19h\nja short loc_11CD\nsub edx, 20h ; ' '\njmp short loc_11DA\nloc_11FE:\ncdqe\nmov byte ptr [rbx+rax], 0\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(const char *a1, __int64 a2)\n{\n __int64 result; // rax\n __int64 i; // rcx\n char v4; // dl\n\n LODWORD(result) = strlen(a1);\n if ( (int)result > 0 )\n {\n for ( i = 0LL; ; ++i )\n {\n v4 = a1[i];\n if ( (unsigned __int8)(v4 - 97) > 0x19u )\n {\n if ( (unsigned __int8)(v4 - 65) < 0x1Au )\n v4 = a1[i] + 32;\n }\n else\n {\n v4 -= 32;\n }\n *(_BYTE *)(a2 + i) = v4;\n if ( i == (_DWORD)result - 1 )\n break;\n }\n }\n result = (int)result;\n *(_BYTE *)(a2 + (int)result) = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(const char *a1, long long a2) {\n long long result;\n long long i;\n char v4;\n LODWORD(result) = strlen(a1);\n if ((int)result > 0) {\n for (i = 0LL;; ++i) {\n v4 = a1[i];\n if ((unsigned char)(v4 - 97) > 25u) {\n if ((unsigned char)(v4 - 65) < 26u) v4 = a1[i] + 32;\n } else {\n v4 -= 32;\n }\n *(uint8_t *)(a2 + i) = v4;\n if (i == (uint32_t)result - 1) break;\n }\n }\n result = (int)result;\n *(uint8_t *)(a2 + (int)result) = 0;\n return result;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, long long a2) {\n long long result;\n long long i;\n char v4;\n LODWORD(result) = strlen(a1);\n if ((int)result > 0) {\n for (i = 0LL;; ++i) {\n v4 = a1[i];\n if ((unsigned char)(v4 - 97) > 25u) {\n if ((unsigned char)(v4 - 65) < 26u) v4 = a1[i] + 32;\n } else {\n v4 -= 32;\n }\n *(uint8_t *)(a2 + i) = v4;\n if (i == (uint32_t)result - 1) break;\n }\n }\n result = (int)result;\n *(uint8_t *)(a2 + (int)result) = 0;\n return result;\n}" + }, + { + "index": "HumanEval-C-27", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(const char* str, char* out) {\n int length = strlen(str);\n for (int i = 0; i < length; i++) {\n char w = str[i];\n if (w >= 'a' && w <= 'z') {\n w -= 32;\n } else if (w >= 'A' && w <= 'Z') {\n w += 32;\n }\n out[i] = w;\n }\n out[length] = '\\0';\n}", + "test": "#include \n#include \n\nint main() {\n char result[100]; // Buffer large enough for test cases\n\n func0(\"\", result);\n assert(strcmp(result, \"\") == 0);\n\n func0(\"Hello!\", result);\n assert(strcmp(result, \"hELLO!\") == 0);\n\n func0(\"These violent delights have violent ends\", result);\n assert(strcmp(result, \"tHESE VIOLENT DELIGHTS HAVE VIOLENT ENDS\") == 0);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rdi\npush rbx\nmov rbx, rsi\nsub rsp, 8\ncall _strlen\ntest eax, eax\njle short loc_133B\nlea esi, [rax-1]\nxor ecx, ecx\njmp short loc_1312\nloc_1300:\nsub edx, 20h ; ' '\nmov [rbx+rcx], dl\nlea rdx, [rcx+1]\ncmp rsi, rcx\njz short loc_133B\nloc_130F:\nmov rcx, rdx\nloc_1312:\nmovzx edx, byte ptr [rbp+rcx+0]\nlea r8d, [rdx-61h]\ncmp r8b, 19h\njbe short loc_1300\nlea r8d, [rdx-41h]\nlea edi, [rdx+20h]\ncmp r8b, 1Ah\ncmovb edx, edi\nmov [rbx+rcx], dl\nlea rdx, [rcx+1]\ncmp rsi, rcx\njnz short loc_130F\nloc_133B:\ncdqe\nmov byte ptr [rbx+rax], 0\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, __int64 a2)\n{\n __int64 result; // rax\n __int64 v4; // rsi\n __int64 i; // rcx\n __int64 v6; // rdx\n char v7; // dl\n\n LODWORD(result) = strlen(a1);\n if ( (int)result > 0 )\n {\n v4 = (unsigned int)(result - 1);\n for ( i = 0LL; ; i = v6 )\n {\n v7 = a1[i];\n if ( (unsigned __int8)(v7 - 97) <= 0x19u )\n {\n *(_BYTE *)(a2 + i) = v7 - 32;\n v6 = i + 1;\n if ( v4 == i )\n break;\n }\n else\n {\n if ( (unsigned __int8)(v7 - 65) < 0x1Au )\n v7 += 32;\n *(_BYTE *)(a2 + i) = v7;\n v6 = i + 1;\n if ( v4 == i )\n break;\n }\n }\n }\n result = (int)result;\n *(_BYTE *)(a2 + (int)result) = 0;\n return result;\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\npush rbp\nmov rbp, rdi\npush rbx\nmov rbx, rsi\nsub rsp, 8\ncall _strlen\ntest eax, eax\njle short loc_133B\nlea esi, [rax-1]\nxor ecx, ecx\njmp short loc_1312\nloc_1300:\nsub edx, 20h ; ' '\nmov [rbx+rcx], dl\nlea rdx, [rcx+1]\ncmp rsi, rcx\njz short loc_133B\nloc_130F:\nmov rcx, rdx\nloc_1312:\nmovzx edx, byte ptr [rbp+rcx+0]\nlea r8d, [rdx-61h]\ncmp r8b, 19h\njbe short loc_1300\nlea r8d, [rdx-41h]\nlea edi, [rdx+20h]\ncmp r8b, 1Ah\ncmovb edx, edi\nmov [rbx+rcx], dl\nlea rdx, [rcx+1]\ncmp rsi, rcx\njnz short loc_130F\nloc_133B:\ncdqe\nmov byte ptr [rbx+rax], 0\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12E0(const char *a1, __int64 a2)\n{\n __int64 result; // rax\n __int64 v4; // rsi\n __int64 i; // rcx\n __int64 v6; // rdx\n char v7; // dl\n\n LODWORD(result) = strlen(a1);\n if ( (int)result > 0 )\n {\n v4 = (unsigned int)(result - 1);\n for ( i = 0LL; ; i = v6 )\n {\n v7 = a1[i];\n if ( (unsigned __int8)(v7 - 97) <= 0x19u )\n {\n *(_BYTE *)(a2 + i) = v7 - 32;\n v6 = i + 1;\n if ( v4 == i )\n break;\n }\n else\n {\n if ( (unsigned __int8)(v7 - 65) < 0x1Au )\n v7 += 32;\n *(_BYTE *)(a2 + i) = v7;\n v6 = i + 1;\n if ( v4 == i )\n break;\n }\n }\n }\n result = (int)result;\n *(_BYTE *)(a2 + (int)result) = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12E0(const char *a1, long long a2) {\n long long result;\n long long v4;\n long long i;\n long long v6;\n char v7;\n LODWORD(result) = strlen(a1);\n if ((int)result > 0) {\n v4 = (unsigned int)(result - 1);\n for (i = 0LL;; i = v6) {\n v7 = a1[i];\n if ((unsigned char)(v7 - 97) <= 25u) {\n *(uint8_t *)(a2 + i) = v7 - 32;\n v6 = i + 1;\n if (v4 == i) break;\n } else {\n if ((unsigned char)(v7 - 65) < 26u) v7 += 32;\n *(uint8_t *)(a2 + i) = v7;\n v6 = i + 1;\n if (v4 == i) break;\n }\n }\n }\n result = (int)result;\n *(uint8_t *)(a2 + (int)result) = 0;\n return result;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, long long a2) {\n long long result;\n long long v4;\n long long i;\n long long v6;\n char v7;\n LODWORD(result) = strlen(a1);\n if ((int)result > 0) {\n v4 = (unsigned int)(result - 1);\n for (i = 0LL;; i = v6) {\n v7 = a1[i];\n if ((unsigned char)(v7 - 97) <= 25u) {\n *(uint8_t *)(a2 + i) = v7 - 32;\n v6 = i + 1;\n if (v4 == i) break;\n } else {\n if ((unsigned char)(v7 - 65) < 26u) v7 += 32;\n *(uint8_t *)(a2 + i) = v7;\n v6 = i + 1;\n if (v4 == i) break;\n }\n }\n }\n result = (int)result;\n *(uint8_t *)(a2 + (int)result) = 0;\n return result;\n}" + }, + { + "index": "HumanEval-C-27", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(const char* str, char* out) {\n int length = strlen(str);\n for (int i = 0; i < length; i++) {\n char w = str[i];\n if (w >= 'a' && w <= 'z') {\n w -= 32;\n } else if (w >= 'A' && w <= 'Z') {\n w += 32;\n }\n out[i] = w;\n }\n out[length] = '\\0';\n}", + "test": "#include \n#include \n\nint main() {\n char result[100]; // Buffer large enough for test cases\n\n func0(\"\", result);\n assert(strcmp(result, \"\") == 0);\n\n func0(\"Hello!\", result);\n assert(strcmp(result, \"hELLO!\") == 0);\n\n func0(\"These violent delights have violent ends\", result);\n assert(strcmp(result, \"tHESE VIOLENT DELIGHTS HAVE VIOLENT ENDS\") == 0);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rdi\npush rbx\nmov rbx, rsi\nsub rsp, 8\ncall _strlen\nmov rcx, rax\ntest eax, eax\njle short loc_135A\nlea edi, [rax-1]\nmov esi, eax\ncmp edi, 6\njbe short loc_1316\nlea rdx, [rbp+1]\nmov rax, rbx\nsub rax, rdx\ncmp rax, 0Eh\nja short loc_1370\nloc_1316:\nxor edx, edx\njmp short loc_1332\nloc_1320:\nsub eax, 20h ; ' '\nmov [rbx+rdx], al\nlea rax, [rdx+1]\ncmp rdx, rdi\njz short loc_135A\nloc_132F:\nmov rdx, rax\nloc_1332:\nmovzx eax, byte ptr [rbp+rdx+0]\nlea esi, [rax-61h]\ncmp sil, 19h\njbe short loc_1320\nlea r8d, [rax-41h]\nlea esi, [rax+20h]\ncmp r8b, 1Ah\ncmovb eax, esi\nmov [rbx+rdx], al\nlea rax, [rdx+1]\ncmp rdx, rdi\njnz short loc_132F\nloc_135A:\nmovsxd rcx, ecx\nmov byte ptr [rbx+rcx], 0\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1370:\ncmp edi, 0Eh\njbe loc_1690\nmov edx, ecx\nmovdqa xmm7, cs:xmmword_2130\nxor eax, eax\npxor xmm3, xmm3\nshr edx, 4\nmovdqa xmm4, cs:xmmword_2140\nmovdqa xmm8, cs:xmmword_2120\nmovdqa xmm6, cs:xmmword_2150\nmovdqa xmm5, cs:xmmword_2160\nshl rdx, 4\nloc_13B1:\nmovdqu xmm2, xmmword ptr [rbp+rax+0]\nmovdqa xmm1, xmm2\nmovdqa xmm0, xmm2\nmovdqa xmm10, xmm2\npaddb xmm1, xmm8\npaddb xmm0, xmm7\npsubusb xmm1, xmm4\npsubusb xmm0, xmm4\npcmpeqb xmm1, xmm3\npcmpeqb xmm0, xmm3\npaddb xmm10, xmm6\nmovdqa xmm9, xmm1\npcmpeqb xmm0, xmm3\npcmpeqb xmm9, xmm3\npand xmm0, xmm9\nmovdqa xmm9, xmm2\npaddb xmm2, xmm5\npand xmm9, xmm0\npandn xmm0, xmm10\npand xmm2, xmm1\npor xmm0, xmm9\npandn xmm1, xmm0\npor xmm1, xmm2\nmovups xmmword ptr [rbx+rax], xmm1\nadd rax, 10h\ncmp rax, rdx\njnz short loc_13B1\nmov edx, ecx\nand edx, 0FFFFFFF0h\nmov eax, edx\ntest cl, 0Fh\njz loc_135A\nmov esi, ecx\nsub esi, edx\nlea edi, [rsi-1]\ncmp edi, 6\njbe loc_14D5\nloc_1446:\nmovq xmm2, qword ptr [rbp+rdx+0]\npxor xmm3, xmm3\nmovq xmm1, qword ptr cs:xmmword_2120\nmovq xmm0, qword ptr cs:xmmword_2130\nmovq xmm4, qword ptr cs:xmmword_2140\npaddb xmm1, xmm2\npaddb xmm0, xmm2\npsubusb xmm1, xmm4\npsubusb xmm0, xmm4\nmovdqa xmm4, xmm2\npcmpeqb xmm1, xmm3\npcmpeqb xmm0, xmm3\npcmpeqb xmm0, xmm3\npcmpeqb xmm3, xmm1\npand xmm0, xmm3\nmovq xmm3, qword ptr cs:xmmword_2150\npand xmm4, xmm0\npaddb xmm3, xmm2\npandn xmm0, xmm3\nmovq xmm3, qword ptr cs:xmmword_2160\npor xmm0, xmm4\npaddb xmm2, xmm3\npand xmm2, xmm1\npandn xmm1, xmm0\npor xmm1, xmm2\nmovq qword ptr [rbx+rdx], xmm1\nmov edx, esi\nand edx, 0FFFFFFF8h\nadd eax, edx\nand esi, 7\njz loc_135A\nloc_14D5:\nmovsxd rsi, eax\nmovzx edx, byte ptr [rbp+rsi+0]\nlea edi, [rdx-61h]\ncmp dil, 19h\njbe loc_1600\nlea r8d, [rdx-41h]\nlea edi, [rdx+20h]\ncmp r8b, 1Ah\ncmovb edx, edi\nloc_14F8:\nmov [rbx+rsi], dl\nlea edx, [rax+1]\ncmp ecx, edx\njle loc_135A\nmovsxd rdx, edx\nmovzx esi, byte ptr [rbp+rdx+0]\nlea edi, [rsi-61h]\ncmp dil, 19h\nja loc_1610\nsub esi, 20h ; ' '\nloc_151E:\nmov [rbx+rdx], sil\nlea edx, [rax+2]\ncmp ecx, edx\njle loc_135A\nmovsxd rdx, edx\nmovzx esi, byte ptr [rbp+rdx+0]\nlea edi, [rsi-61h]\ncmp dil, 19h\nja loc_1628\nsub esi, 20h ; ' '\nloc_1545:\nmov [rbx+rdx], sil\nlea edx, [rax+3]\ncmp ecx, edx\njle loc_135A\nmovsxd rdx, edx\nmovzx esi, byte ptr [rbp+rdx+0]\nlea edi, [rsi-61h]\ncmp dil, 19h\nja loc_1640\nsub esi, 20h ; ' '\nloc_156C:\nmov [rbx+rdx], sil\nlea edx, [rax+4]\ncmp ecx, edx\njle loc_135A\nmovsxd rdx, edx\nmovzx esi, byte ptr [rbp+rdx+0]\nlea edi, [rsi-61h]\ncmp dil, 19h\nja loc_1658\nsub esi, 20h ; ' '\nloc_1593:\nmov [rbx+rdx], sil\nlea edx, [rax+5]\ncmp ecx, edx\njle loc_135A\nmovsxd rdx, edx\nmovzx esi, byte ptr [rbp+rdx+0]\nlea edi, [rsi-61h]\ncmp dil, 19h\nja loc_1670\nsub esi, 20h ; ' '\nloc_15BA:\nadd eax, 6\nmov [rbx+rdx], sil\ncmp ecx, eax\njle loc_135A\ncdqe\nmovzx edx, byte ptr [rbp+rax+0]\nlea esi, [rdx-61h]\ncmp sil, 19h\njbe loc_1688\nlea edi, [rdx-41h]\nlea esi, [rdx+20h]\ncmp dil, 1Ah\ncmovb edx, esi\nloc_15EA:\nmovsxd rcx, ecx\nmov [rbx+rax], dl\nmov byte ptr [rbx+rcx], 0\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1600:\nsub edx, 20h ; ' '\njmp loc_14F8\nloc_1610:\nlea r8d, [rsi-41h]\nlea edi, [rsi+20h]\ncmp r8b, 1Ah\ncmovb esi, edi\njmp loc_151E\nloc_1628:\nlea r8d, [rsi-41h]\nlea edi, [rsi+20h]\ncmp r8b, 1Ah\ncmovb esi, edi\njmp loc_1545\nloc_1640:\nlea r8d, [rsi-41h]\nlea edi, [rsi+20h]\ncmp r8b, 1Ah\ncmovb esi, edi\njmp loc_156C\nloc_1658:\nlea r8d, [rsi-41h]\nlea edi, [rsi+20h]\ncmp r8b, 1Ah\ncmovb esi, edi\njmp loc_1593\nloc_1670:\nlea r8d, [rsi-41h]\nlea edi, [rsi+20h]\ncmp r8b, 1Ah\ncmovb esi, edi\njmp loc_15BA\nloc_1688:\nsub edx, 20h ; ' '\njmp loc_15EA\nloc_1690:\nxor edx, edx\nxor eax, eax\njmp loc_1446", + "ida_pseudo": "size_t __fastcall func0(const char *a1, __int64 a2)\n{\n size_t result; // rax\n int v5; // ecx\n __int64 v6; // rdi\n int v7; // esi\n size_t i; // rdx\n char v9; // al\n __m128i si128; // xmm7\n __int64 v11; // rax\n __m128i v12; // xmm4\n __m128i v13; // xmm8\n __m128i v14; // xmm6\n __m128i v15; // xmm5\n __m128i v16; // xmm2\n __m128i v17; // xmm1\n __m128i v18; // xmm0\n size_t v19; // rdx\n __m128i v20; // xmm2\n __m128i v21; // xmm4\n __m128i v22; // xmm1\n __m128i v23; // xmm0\n char v24; // dl\n int v25; // edx\n char v26; // si\n int v27; // edx\n char v28; // si\n int v29; // edx\n char v30; // si\n int v31; // edx\n char v32; // si\n int v33; // edx\n char v34; // si\n char v35; // dl\n\n result = strlen(a1);\n v5 = result;\n if ( (int)result <= 0 )\n goto LABEL_11;\n v6 = (unsigned int)(result - 1);\n v7 = result;\n if ( (unsigned int)v6 <= 6 || (unsigned __int64)(a2 - (_QWORD)(a1 + 1)) <= 0xE )\n {\n for ( i = 0LL; ; i = result )\n {\n v9 = a1[i];\n if ( (unsigned __int8)(v9 - 97) <= 0x19u )\n {\n *(_BYTE *)(a2 + i) = v9 - 32;\n result = i + 1;\n if ( i == v6 )\n goto LABEL_11;\n }\n else\n {\n if ( (unsigned __int8)(v9 - 65) < 0x1Au )\n v9 += 32;\n *(_BYTE *)(a2 + i) = v9;\n result = i + 1;\n if ( i == v6 )\n goto LABEL_11;\n }\n }\n }\n if ( (unsigned int)v6 <= 0xE )\n {\n v19 = 0LL;\n LODWORD(result) = 0;\n }\n else\n {\n si128 = _mm_load_si128((const __m128i *)&xmmword_2130);\n v11 = 0LL;\n v12 = _mm_load_si128((const __m128i *)&xmmword_2140);\n v13 = _mm_load_si128((const __m128i *)&xmmword_2120);\n v14 = _mm_load_si128((const __m128i *)&xmmword_2150);\n v15 = _mm_load_si128((const __m128i *)&xmmword_2160);\n do\n {\n v16 = _mm_loadu_si128((const __m128i *)&a1[v11]);\n v17 = _mm_cmpeq_epi8(_mm_subs_epu8(_mm_add_epi8(v16, v13), v12), (__m128i)0LL);\n v18 = _mm_and_si128(\n _mm_cmpeq_epi8(_mm_cmpeq_epi8(_mm_subs_epu8(_mm_add_epi8(v16, si128), v12), (__m128i)0LL), (__m128i)0LL),\n _mm_cmpeq_epi8(v17, (__m128i)0LL));\n *(__m128i *)(a2 + v11) = _mm_or_si128(\n _mm_andnot_si128(\n v17,\n _mm_or_si128(_mm_andnot_si128(v18, _mm_add_epi8(v16, v14)), _mm_and_si128(v16, v18))),\n _mm_and_si128(_mm_add_epi8(v16, v15), v17));\n v11 += 16LL;\n }\n while ( v11 != 16LL * ((unsigned int)v5 >> 4) );\n v19 = v5 & 0xFFFFFFF0;\n result = v19;\n if ( (v5 & 0xF) == 0 )\n goto LABEL_11;\n v7 = v5 - v19;\n if ( (unsigned int)(v5 - v19 - 1) <= 6 )\n goto LABEL_18;\n }\n v20 = _mm_loadl_epi64((const __m128i *)&a1[v19]);\n v21 = _mm_loadl_epi64((const __m128i *)&xmmword_2140);\n v22 = _mm_cmpeq_epi8(\n _mm_subs_epu8(_mm_add_epi8(_mm_loadl_epi64((const __m128i *)&xmmword_2120), v20), v21),\n (__m128i)0LL);\n v23 = _mm_and_si128(\n _mm_cmpeq_epi8(\n _mm_cmpeq_epi8(\n _mm_subs_epu8(_mm_add_epi8(_mm_loadl_epi64((const __m128i *)&xmmword_2130), v20), v21),\n (__m128i)0LL),\n (__m128i)0LL),\n _mm_cmpeq_epi8((__m128i)0LL, v22));\n *(_QWORD *)(a2 + v19) = _mm_or_si128(\n _mm_andnot_si128(\n v22,\n _mm_or_si128(\n _mm_andnot_si128(\n v23,\n _mm_add_epi8(_mm_loadl_epi64((const __m128i *)&xmmword_2150), v20)),\n _mm_and_si128(v20, v23))),\n _mm_and_si128(_mm_add_epi8(v20, _mm_loadl_epi64((const __m128i *)&xmmword_2160)), v22)).m128i_u64[0];\n result = (v7 & 0xFFFFFFF8) + (unsigned int)result;\n if ( (v7 & 7) == 0 )\n {\nLABEL_11:\n *(_BYTE *)(a2 + v5) = 0;\n return result;\n }\nLABEL_18:\n v24 = a1[(int)result];\n if ( (unsigned __int8)(v24 - 97) <= 0x19u )\n {\n v24 -= 32;\n }\n else if ( (unsigned __int8)(v24 - 65) < 0x1Au )\n {\n v24 += 32;\n }\n *(_BYTE *)(a2 + (int)result) = v24;\n v25 = result + 1;\n if ( v5 <= (int)result + 1 )\n goto LABEL_11;\n v26 = a1[v25];\n if ( (unsigned __int8)(v26 - 97) > 0x19u )\n {\n if ( (unsigned __int8)(v26 - 65) < 0x1Au )\n v26 += 32;\n }\n else\n {\n v26 -= 32;\n }\n *(_BYTE *)(a2 + v25) = v26;\n v27 = result + 2;\n if ( v5 <= (int)result + 2 )\n goto LABEL_11;\n v28 = a1[v27];\n if ( (unsigned __int8)(v28 - 97) > 0x19u )\n {\n if ( (unsigned __int8)(v28 - 65) < 0x1Au )\n v28 += 32;\n }\n else\n {\n v28 -= 32;\n }\n *(_BYTE *)(a2 + v27) = v28;\n v29 = result + 3;\n if ( v5 <= (int)result + 3 )\n goto LABEL_11;\n v30 = a1[v29];\n if ( (unsigned __int8)(v30 - 97) > 0x19u )\n {\n if ( (unsigned __int8)(v30 - 65) < 0x1Au )\n v30 += 32;\n }\n else\n {\n v30 -= 32;\n }\n *(_BYTE *)(a2 + v29) = v30;\n v31 = result + 4;\n if ( v5 <= (int)result + 4 )\n goto LABEL_11;\n v32 = a1[v31];\n if ( (unsigned __int8)(v32 - 97) > 0x19u )\n {\n if ( (unsigned __int8)(v32 - 65) < 0x1Au )\n v32 += 32;\n }\n else\n {\n v32 -= 32;\n }\n *(_BYTE *)(a2 + v31) = v32;\n v33 = result + 5;\n if ( v5 <= (int)result + 5 )\n goto LABEL_11;\n v34 = a1[v33];\n if ( (unsigned __int8)(v34 - 97) > 0x19u )\n {\n if ( (unsigned __int8)(v34 - 65) < 0x1Au )\n v34 += 32;\n }\n else\n {\n v34 -= 32;\n }\n result = (unsigned int)(result + 6);\n *(_BYTE *)(a2 + v33) = v34;\n if ( v5 <= (int)result )\n goto LABEL_11;\n result = (int)result;\n v35 = a1[(int)result];\n if ( (unsigned __int8)(v35 - 97) <= 0x19u )\n {\n v35 -= 32;\n }\n else if ( (unsigned __int8)(v35 - 65) < 0x1Au )\n {\n v35 += 32;\n }\n *(_BYTE *)(a2 + (int)result) = v35;\n *(_BYTE *)(a2 + v5) = 0;\n return result;\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\npush rbp\nmov rbp, rdi\npush rbx\nmov rbx, rsi\nsub rsp, 8\ncall _strlen\nmov rcx, rax\ntest eax, eax\njle short loc_135A\nlea edi, [rax-1]\nmov esi, eax\ncmp edi, 6\njbe short loc_1316\nlea rdx, [rbp+1]\nmov rax, rbx\nsub rax, rdx\ncmp rax, 0Eh\nja short loc_1370\nloc_1316:\nxor edx, edx\njmp short loc_1332\nloc_1320:\nsub eax, 20h ; ' '\nmov [rbx+rdx], al\nlea rax, [rdx+1]\ncmp rdx, rdi\njz short loc_135A\nloc_132F:\nmov rdx, rax\nloc_1332:\nmovzx eax, byte ptr [rbp+rdx+0]\nlea esi, [rax-61h]\ncmp sil, 19h\njbe short loc_1320\nlea r8d, [rax-41h]\nlea esi, [rax+20h]\ncmp r8b, 1Ah\ncmovb eax, esi\nmov [rbx+rdx], al\nlea rax, [rdx+1]\ncmp rdx, rdi\njnz short loc_132F\nloc_135A:\nmovsxd rcx, ecx\nmov byte ptr [rbx+rcx], 0\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1370:\ncmp edi, 0Eh\njbe loc_1690\nmov edx, ecx\nmovdqa xmm7, cs:xmmword_2130\nxor eax, eax\npxor xmm3, xmm3\nshr edx, 4\nmovdqa xmm4, cs:xmmword_2140\nmovdqa xmm8, cs:xmmword_2120\nmovdqa xmm6, cs:xmmword_2150\nmovdqa xmm5, cs:xmmword_2160\nshl rdx, 4\nloc_13B1:\nmovdqu xmm2, xmmword ptr [rbp+rax+0]\nmovdqa xmm1, xmm2\nmovdqa xmm0, xmm2\nmovdqa xmm10, xmm2\npaddb xmm1, xmm8\npaddb xmm0, xmm7\npsubusb xmm1, xmm4\npsubusb xmm0, xmm4\npcmpeqb xmm1, xmm3\npcmpeqb xmm0, xmm3\npaddb xmm10, xmm6\nmovdqa xmm9, xmm1\npcmpeqb xmm0, xmm3\npcmpeqb xmm9, xmm3\npand xmm0, xmm9\nmovdqa xmm9, xmm2\npaddb xmm2, xmm5\npand xmm9, xmm0\npandn xmm0, xmm10\npand xmm2, xmm1\npor xmm0, xmm9\npandn xmm1, xmm0\npor xmm1, xmm2\nmovups xmmword ptr [rbx+rax], xmm1\nadd rax, 10h\ncmp rax, rdx\njnz short loc_13B1\nmov edx, ecx\nand edx, 0FFFFFFF0h\nmov eax, edx\ntest cl, 0Fh\njz loc_135A\nmov esi, ecx\nsub esi, edx\nlea edi, [rsi-1]\ncmp edi, 6\njbe loc_14D5\nloc_1446:\nmovq xmm2, qword ptr [rbp+rdx+0]\npxor xmm3, xmm3\nmovq xmm1, qword ptr cs:xmmword_2120\nmovq xmm0, qword ptr cs:xmmword_2130\nmovq xmm4, qword ptr cs:xmmword_2140\npaddb xmm1, xmm2\npaddb xmm0, xmm2\npsubusb xmm1, xmm4\npsubusb xmm0, xmm4\nmovdqa xmm4, xmm2\npcmpeqb xmm1, xmm3\npcmpeqb xmm0, xmm3\npcmpeqb xmm0, xmm3\npcmpeqb xmm3, xmm1\npand xmm0, xmm3\nmovq xmm3, qword ptr cs:xmmword_2150\npand xmm4, xmm0\npaddb xmm3, xmm2\npandn xmm0, xmm3\nmovq xmm3, qword ptr cs:xmmword_2160\npor xmm0, xmm4\npaddb xmm2, xmm3\npand xmm2, xmm1\npandn xmm1, xmm0\npor xmm1, xmm2\nmovq qword ptr [rbx+rdx], xmm1\nmov edx, esi\nand edx, 0FFFFFFF8h\nadd eax, edx\nand esi, 7\njz loc_135A\nloc_14D5:\nmovsxd rsi, eax\nmovzx edx, byte ptr [rbp+rsi+0]\nlea edi, [rdx-61h]\ncmp dil, 19h\njbe loc_1600\nlea r8d, [rdx-41h]\nlea edi, [rdx+20h]\ncmp r8b, 1Ah\ncmovb edx, edi\nloc_14F8:\nmov [rbx+rsi], dl\nlea edx, [rax+1]\ncmp ecx, edx\njle loc_135A\nmovsxd rdx, edx\nmovzx esi, byte ptr [rbp+rdx+0]\nlea edi, [rsi-61h]\ncmp dil, 19h\nja loc_1610\nsub esi, 20h ; ' '\nloc_151E:\nmov [rbx+rdx], sil\nlea edx, [rax+2]\ncmp ecx, edx\njle loc_135A\nmovsxd rdx, edx\nmovzx esi, byte ptr [rbp+rdx+0]\nlea edi, [rsi-61h]\ncmp dil, 19h\nja loc_1628\nsub esi, 20h ; ' '\nloc_1545:\nmov [rbx+rdx], sil\nlea edx, [rax+3]\ncmp ecx, edx\njle loc_135A\nmovsxd rdx, edx\nmovzx esi, byte ptr [rbp+rdx+0]\nlea edi, [rsi-61h]\ncmp dil, 19h\nja loc_1640\nsub esi, 20h ; ' '\nloc_156C:\nmov [rbx+rdx], sil\nlea edx, [rax+4]\ncmp ecx, edx\njle loc_135A\nmovsxd rdx, edx\nmovzx esi, byte ptr [rbp+rdx+0]\nlea edi, [rsi-61h]\ncmp dil, 19h\nja loc_1658\nsub esi, 20h ; ' '\nloc_1593:\nmov [rbx+rdx], sil\nlea edx, [rax+5]\ncmp ecx, edx\njle loc_135A\nmovsxd rdx, edx\nmovzx esi, byte ptr [rbp+rdx+0]\nlea edi, [rsi-61h]\ncmp dil, 19h\nja loc_1670\nsub esi, 20h ; ' '\nloc_15BA:\nadd eax, 6\nmov [rbx+rdx], sil\ncmp ecx, eax\njle loc_135A\ncdqe\nmovzx edx, byte ptr [rbp+rax+0]\nlea esi, [rdx-61h]\ncmp sil, 19h\njbe loc_1688\nlea edi, [rdx-41h]\nlea esi, [rdx+20h]\ncmp dil, 1Ah\ncmovb edx, esi\nloc_15EA:\nmovsxd rcx, ecx\nmov [rbx+rax], dl\nmov byte ptr [rbx+rcx], 0\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1600:\nsub edx, 20h ; ' '\njmp loc_14F8\nloc_1610:\nlea r8d, [rsi-41h]\nlea edi, [rsi+20h]\ncmp r8b, 1Ah\ncmovb esi, edi\njmp loc_151E\nloc_1628:\nlea r8d, [rsi-41h]\nlea edi, [rsi+20h]\ncmp r8b, 1Ah\ncmovb esi, edi\njmp loc_1545\nloc_1640:\nlea r8d, [rsi-41h]\nlea edi, [rsi+20h]\ncmp r8b, 1Ah\ncmovb esi, edi\njmp loc_156C\nloc_1658:\nlea r8d, [rsi-41h]\nlea edi, [rsi+20h]\ncmp r8b, 1Ah\ncmovb esi, edi\njmp loc_1593\nloc_1670:\nlea r8d, [rsi-41h]\nlea edi, [rsi+20h]\ncmp r8b, 1Ah\ncmovb esi, edi\njmp loc_15BA\nloc_1688:\nsub edx, 20h ; ' '\njmp loc_15EA\nloc_1690:\nxor edx, edx\nxor eax, eax\njmp loc_1446", + "ida_strip_pseudo": "size_t __fastcall sub_12E0(const char *a1, __int64 a2)\n{\n size_t result; // rax\n int v5; // ecx\n __int64 v6; // rdi\n int v7; // esi\n size_t i; // rdx\n char v9; // al\n __m128i si128; // xmm7\n __int64 v11; // rax\n __m128i v12; // xmm4\n __m128i v13; // xmm8\n __m128i v14; // xmm6\n __m128i v15; // xmm5\n __m128i v16; // xmm2\n __m128i v17; // xmm1\n __m128i v18; // xmm0\n size_t v19; // rdx\n __m128i v20; // xmm2\n __m128i v21; // xmm4\n __m128i v22; // xmm1\n __m128i v23; // xmm0\n char v24; // dl\n int v25; // edx\n char v26; // si\n int v27; // edx\n char v28; // si\n int v29; // edx\n char v30; // si\n int v31; // edx\n char v32; // si\n int v33; // edx\n char v34; // si\n char v35; // dl\n\n result = strlen(a1);\n v5 = result;\n if ( (int)result <= 0 )\n goto LABEL_11;\n v6 = (unsigned int)(result - 1);\n v7 = result;\n if ( (unsigned int)v6 <= 6 || (unsigned __int64)(a2 - (_QWORD)(a1 + 1)) <= 0xE )\n {\n for ( i = 0LL; ; i = result )\n {\n v9 = a1[i];\n if ( (unsigned __int8)(v9 - 97) <= 0x19u )\n {\n *(_BYTE *)(a2 + i) = v9 - 32;\n result = i + 1;\n if ( i == v6 )\n goto LABEL_11;\n }\n else\n {\n if ( (unsigned __int8)(v9 - 65) < 0x1Au )\n v9 += 32;\n *(_BYTE *)(a2 + i) = v9;\n result = i + 1;\n if ( i == v6 )\n goto LABEL_11;\n }\n }\n }\n if ( (unsigned int)v6 <= 0xE )\n {\n v19 = 0LL;\n LODWORD(result) = 0;\n }\n else\n {\n si128 = _mm_load_si128((const __m128i *)&xmmword_2130);\n v11 = 0LL;\n v12 = _mm_load_si128((const __m128i *)&xmmword_2140);\n v13 = _mm_load_si128((const __m128i *)&xmmword_2120);\n v14 = _mm_load_si128((const __m128i *)&xmmword_2150);\n v15 = _mm_load_si128((const __m128i *)&xmmword_2160);\n do\n {\n v16 = _mm_loadu_si128((const __m128i *)&a1[v11]);\n v17 = _mm_cmpeq_epi8(_mm_subs_epu8(_mm_add_epi8(v16, v13), v12), (__m128i)0LL);\n v18 = _mm_and_si128(\n _mm_cmpeq_epi8(_mm_cmpeq_epi8(_mm_subs_epu8(_mm_add_epi8(v16, si128), v12), (__m128i)0LL), (__m128i)0LL),\n _mm_cmpeq_epi8(v17, (__m128i)0LL));\n *(__m128i *)(a2 + v11) = _mm_or_si128(\n _mm_andnot_si128(\n v17,\n _mm_or_si128(_mm_andnot_si128(v18, _mm_add_epi8(v16, v14)), _mm_and_si128(v16, v18))),\n _mm_and_si128(_mm_add_epi8(v16, v15), v17));\n v11 += 16LL;\n }\n while ( v11 != 16LL * ((unsigned int)v5 >> 4) );\n v19 = v5 & 0xFFFFFFF0;\n result = v19;\n if ( (v5 & 0xF) == 0 )\n goto LABEL_11;\n v7 = v5 - v19;\n if ( (unsigned int)(v5 - v19 - 1) <= 6 )\n goto LABEL_18;\n }\n v20 = _mm_loadl_epi64((const __m128i *)&a1[v19]);\n v21 = _mm_loadl_epi64((const __m128i *)&xmmword_2140);\n v22 = _mm_cmpeq_epi8(\n _mm_subs_epu8(_mm_add_epi8(_mm_loadl_epi64((const __m128i *)&xmmword_2120), v20), v21),\n (__m128i)0LL);\n v23 = _mm_and_si128(\n _mm_cmpeq_epi8(\n _mm_cmpeq_epi8(\n _mm_subs_epu8(_mm_add_epi8(_mm_loadl_epi64((const __m128i *)&xmmword_2130), v20), v21),\n (__m128i)0LL),\n (__m128i)0LL),\n _mm_cmpeq_epi8((__m128i)0LL, v22));\n *(_QWORD *)(a2 + v19) = _mm_or_si128(\n _mm_andnot_si128(\n v22,\n _mm_or_si128(\n _mm_andnot_si128(\n v23,\n _mm_add_epi8(_mm_loadl_epi64((const __m128i *)&xmmword_2150), v20)),\n _mm_and_si128(v20, v23))),\n _mm_and_si128(_mm_add_epi8(v20, _mm_loadl_epi64((const __m128i *)&xmmword_2160)), v22)).m128i_u64[0];\n result = (v7 & 0xFFFFFFF8) + (unsigned int)result;\n if ( (v7 & 7) == 0 )\n {\nLABEL_11:\n *(_BYTE *)(a2 + v5) = 0;\n return result;\n }\nLABEL_18:\n v24 = a1[(int)result];\n if ( (unsigned __int8)(v24 - 97) <= 0x19u )\n {\n v24 -= 32;\n }\n else if ( (unsigned __int8)(v24 - 65) < 0x1Au )\n {\n v24 += 32;\n }\n *(_BYTE *)(a2 + (int)result) = v24;\n v25 = result + 1;\n if ( v5 <= (int)result + 1 )\n goto LABEL_11;\n v26 = a1[v25];\n if ( (unsigned __int8)(v26 - 97) > 0x19u )\n {\n if ( (unsigned __int8)(v26 - 65) < 0x1Au )\n v26 += 32;\n }\n else\n {\n v26 -= 32;\n }\n *(_BYTE *)(a2 + v25) = v26;\n v27 = result + 2;\n if ( v5 <= (int)result + 2 )\n goto LABEL_11;\n v28 = a1[v27];\n if ( (unsigned __int8)(v28 - 97) > 0x19u )\n {\n if ( (unsigned __int8)(v28 - 65) < 0x1Au )\n v28 += 32;\n }\n else\n {\n v28 -= 32;\n }\n *(_BYTE *)(a2 + v27) = v28;\n v29 = result + 3;\n if ( v5 <= (int)result + 3 )\n goto LABEL_11;\n v30 = a1[v29];\n if ( (unsigned __int8)(v30 - 97) > 0x19u )\n {\n if ( (unsigned __int8)(v30 - 65) < 0x1Au )\n v30 += 32;\n }\n else\n {\n v30 -= 32;\n }\n *(_BYTE *)(a2 + v29) = v30;\n v31 = result + 4;\n if ( v5 <= (int)result + 4 )\n goto LABEL_11;\n v32 = a1[v31];\n if ( (unsigned __int8)(v32 - 97) > 0x19u )\n {\n if ( (unsigned __int8)(v32 - 65) < 0x1Au )\n v32 += 32;\n }\n else\n {\n v32 -= 32;\n }\n *(_BYTE *)(a2 + v31) = v32;\n v33 = result + 5;\n if ( v5 <= (int)result + 5 )\n goto LABEL_11;\n v34 = a1[v33];\n if ( (unsigned __int8)(v34 - 97) > 0x19u )\n {\n if ( (unsigned __int8)(v34 - 65) < 0x1Au )\n v34 += 32;\n }\n else\n {\n v34 -= 32;\n }\n result = (unsigned int)(result + 6);\n *(_BYTE *)(a2 + v33) = v34;\n if ( v5 <= (int)result )\n goto LABEL_11;\n result = (int)result;\n v35 = a1[(int)result];\n if ( (unsigned __int8)(v35 - 97) <= 0x19u )\n {\n v35 -= 32;\n }\n else if ( (unsigned __int8)(v35 - 65) < 0x1Au )\n {\n v35 += 32;\n }\n *(_BYTE *)(a2 + (int)result) = v35;\n *(_BYTE *)(a2 + v5) = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned int sub_12E0(const char *a1, long long a2) {\n unsigned int result;\n int v5;\n long long v6;\n int v7;\n unsigned int i;\n char v9;\n __m128i si128;\n long long v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n __m128i v15;\n __m128i v16;\n __m128i v17;\n __m128i v18;\n unsigned int v19;\n __m128i v20;\n __m128i v21;\n __m128i v22;\n __m128i v23;\n char v24;\n int v25;\n char v26;\n int v27;\n char v28;\n int v29;\n char v30;\n int v31;\n char v32;\n int v33;\n char v34;\n char v35;\n result = strlen(a1);\n v5 = result;\n if ((int)result <= 0) goto LABEL_11;\n v6 = (unsigned int)(result - 1);\n v7 = result;\n if ((unsigned int)v6 <= 6 ||\n (unsigned long long)(a2 - (uint64_t)(a1 + 1)) <= 14) {\n for (i = 0LL;; i = result) {\n v9 = a1[i];\n if ((unsigned char)(v9 - 97) <= 25u) {\n *(uint8_t *)(a2 + i) = v9 - 32;\n result = i + 1;\n if (i == v6) goto LABEL_11;\n } else {\n if ((unsigned char)(v9 - 65) < 26u) v9 += 32;\n *(uint8_t *)(a2 + i) = v9;\n result = i + 1;\n if (i == v6) goto LABEL_11;\n }\n }\n }\n if ((unsigned int)v6 <= 14) {\n v19 = 0LL;\n LODWORD(result) = 0;\n } else {\n si128 = _mm_load_si128((const __m128i *)&xmmword_2130);\n v11 = 0LL;\n v12 = _mm_load_si128((const __m128i *)&xmmword_2140);\n v13 = _mm_load_si128((const __m128i *)&xmmword_2120);\n v14 = _mm_load_si128((const __m128i *)&xmmword_2150);\n v15 = _mm_load_si128((const __m128i *)&xmmword_2160);\n do {\n v16 = _mm_loadu_si128((const __m128i *)&a1[v11]);\n v17 = _mm_cmpeq_epi8(_mm_subs_epu8(_mm_add_epi8(v16, v13), v12),\n (__m128i)0LL);\n v18 = _mm_and_si128(\n _mm_cmpeq_epi8(\n _mm_cmpeq_epi8(_mm_subs_epu8(_mm_add_epi8(v16, si128), v12),\n (__m128i)0LL),\n (__m128i)0LL),\n _mm_cmpeq_epi8(v17, (__m128i)0LL));\n *(__m128i *)(a2 + v11) = _mm_or_si128(\n _mm_andnot_si128(\n v17, _mm_or_si128(_mm_andnot_si128(v18, _mm_add_epi8(v16, v14)),\n _mm_and_si128(v16, v18))),\n _mm_and_si128(_mm_add_epi8(v16, v15), v17));\n v11 += 16LL;\n } while (v11 != 16LL * ((unsigned int)v5 >> 4));\n v19 = v5 & 4294967280;\n result = v19;\n if ((v5 & 15) == 0) goto LABEL_11;\n v7 = v5 - v19;\n if ((unsigned int)(v5 - v19 - 1) <= 6) goto LABEL_18;\n }\n v20 = _mm_loadl_epi64((const __m128i *)&a1[v19]);\n v21 = _mm_loadl_epi64((const __m128i *)&xmmword_2140);\n v22 = _mm_cmpeq_epi8(\n _mm_subs_epu8(\n _mm_add_epi8(_mm_loadl_epi64((const __m128i *)&xmmword_2120), v20),\n v21),\n (__m128i)0LL);\n v23 = _mm_and_si128(\n _mm_cmpeq_epi8(\n _mm_cmpeq_epi8(\n _mm_subs_epu8(\n _mm_add_epi8(_mm_loadl_epi64((const __m128i *)&xmmword_2130),\n v20),\n v21),\n (__m128i)0LL),\n (__m128i)0LL),\n _mm_cmpeq_epi8((__m128i)0LL, v22));\n *(uint64_t *)(a2 + v19) =\n _mm_or_si128(\n _mm_andnot_si128(\n v22, _mm_or_si128(\n _mm_andnot_si128(\n v23, _mm_add_epi8(_mm_loadl_epi64((\n const __m128i *)&xmmword_2150),\n v20)),\n _mm_and_si128(v20, v23))),\n _mm_and_si128(_mm_add_epi8(v20, _mm_loadl_epi64(\n (const __m128i *)&xmmword_2160)),\n v22))\n .m128i_u64[0];\n result = (v7 & 4294967288) + (unsigned int)result;\n if ((v7 & 7) == 0) {\n LABEL_11:\n *(uint8_t *)(a2 + v5) = 0;\n return result;\n }\nLABEL_18:\n v24 = a1[(int)result];\n if ((unsigned char)(v24 - 97) <= 25u) {\n v24 -= 32;\n } else if ((unsigned char)(v24 - 65) < 26u) {\n v24 += 32;\n }\n *(uint8_t *)(a2 + (int)result) = v24;\n v25 = result + 1;\n if (v5 <= (int)result + 1) goto LABEL_11;\n v26 = a1[v25];\n if ((unsigned char)(v26 - 97) > 25u) {\n if ((unsigned char)(v26 - 65) < 26u) v26 += 32;\n } else {\n v26 -= 32;\n }\n *(uint8_t *)(a2 + v25) = v26;\n v27 = result + 2;\n if (v5 <= (int)result + 2) goto LABEL_11;\n v28 = a1[v27];\n if ((unsigned char)(v28 - 97) > 25u) {\n if ((unsigned char)(v28 - 65) < 26u) v28 += 32;\n } else {\n v28 -= 32;\n }\n *(uint8_t *)(a2 + v27) = v28;\n v29 = result + 3;\n if (v5 <= (int)result + 3) goto LABEL_11;\n v30 = a1[v29];\n if ((unsigned char)(v30 - 97) > 25u) {\n if ((unsigned char)(v30 - 65) < 26u) v30 += 32;\n } else {\n v30 -= 32;\n }\n *(uint8_t *)(a2 + v29) = v30;\n v31 = result + 4;\n if (v5 <= (int)result + 4) goto LABEL_11;\n v32 = a1[v31];\n if ((unsigned char)(v32 - 97) > 25u) {\n if ((unsigned char)(v32 - 65) < 26u) v32 += 32;\n } else {\n v32 -= 32;\n }\n *(uint8_t *)(a2 + v31) = v32;\n v33 = result + 5;\n if (v5 <= (int)result + 5) goto LABEL_11;\n v34 = a1[v33];\n if ((unsigned char)(v34 - 97) > 25u) {\n if ((unsigned char)(v34 - 65) < 26u) v34 += 32;\n } else {\n v34 -= 32;\n }\n result = (unsigned int)(result + 6);\n *(uint8_t *)(a2 + v33) = v34;\n if (v5 <= (int)result) goto LABEL_11;\n result = (int)result;\n v35 = a1[(int)result];\n if ((unsigned char)(v35 - 97) <= 25u) {\n v35 -= 32;\n } else if ((unsigned char)(v35 - 65) < 26u) {\n v35 += 32;\n }\n *(uint8_t *)(a2 + (int)result) = v35;\n *(uint8_t *)(a2 + v5) = 0;\n return result;\n}", + "ida_pseudo_norm": "unsigned int func0(const char *a1, long long a2) {\n unsigned int result;\n int v5;\n long long v6;\n int v7;\n unsigned int i;\n char v9;\n __m128i si128;\n long long v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n __m128i v15;\n __m128i v16;\n __m128i v17;\n __m128i v18;\n unsigned int v19;\n __m128i v20;\n __m128i v21;\n __m128i v22;\n __m128i v23;\n char v24;\n int v25;\n char v26;\n int v27;\n char v28;\n int v29;\n char v30;\n int v31;\n char v32;\n int v33;\n char v34;\n char v35;\n result = strlen(a1);\n v5 = result;\n if ((int)result <= 0) goto LABEL_11;\n v6 = (unsigned int)(result - 1);\n v7 = result;\n if ((unsigned int)v6 <= 6 ||\n (unsigned long long)(a2 - (uint64_t)(a1 + 1)) <= 14) {\n for (i = 0LL;; i = result) {\n v9 = a1[i];\n if ((unsigned char)(v9 - 97) <= 25u) {\n *(uint8_t *)(a2 + i) = v9 - 32;\n result = i + 1;\n if (i == v6) goto LABEL_11;\n } else {\n if ((unsigned char)(v9 - 65) < 26u) v9 += 32;\n *(uint8_t *)(a2 + i) = v9;\n result = i + 1;\n if (i == v6) goto LABEL_11;\n }\n }\n }\n if ((unsigned int)v6 <= 14) {\n v19 = 0LL;\n LODWORD(result) = 0;\n } else {\n si128 = _mm_load_si128((const __m128i *)&xmmword_2130);\n v11 = 0LL;\n v12 = _mm_load_si128((const __m128i *)&xmmword_2140);\n v13 = _mm_load_si128((const __m128i *)&xmmword_2120);\n v14 = _mm_load_si128((const __m128i *)&xmmword_2150);\n v15 = _mm_load_si128((const __m128i *)&xmmword_2160);\n do {\n v16 = _mm_loadu_si128((const __m128i *)&a1[v11]);\n v17 = _mm_cmpeq_epi8(_mm_subs_epu8(_mm_add_epi8(v16, v13), v12),\n (__m128i)0LL);\n v18 = _mm_and_si128(\n _mm_cmpeq_epi8(\n _mm_cmpeq_epi8(_mm_subs_epu8(_mm_add_epi8(v16, si128), v12),\n (__m128i)0LL),\n (__m128i)0LL),\n _mm_cmpeq_epi8(v17, (__m128i)0LL));\n *(__m128i *)(a2 + v11) = _mm_or_si128(\n _mm_andnot_si128(\n v17, _mm_or_si128(_mm_andnot_si128(v18, _mm_add_epi8(v16, v14)),\n _mm_and_si128(v16, v18))),\n _mm_and_si128(_mm_add_epi8(v16, v15), v17));\n v11 += 16LL;\n } while (v11 != 16LL * ((unsigned int)v5 >> 4));\n v19 = v5 & 4294967280;\n result = v19;\n if ((v5 & 15) == 0) goto LABEL_11;\n v7 = v5 - v19;\n if ((unsigned int)(v5 - v19 - 1) <= 6) goto LABEL_18;\n }\n v20 = _mm_loadl_epi64((const __m128i *)&a1[v19]);\n v21 = _mm_loadl_epi64((const __m128i *)&xmmword_2140);\n v22 = _mm_cmpeq_epi8(\n _mm_subs_epu8(\n _mm_add_epi8(_mm_loadl_epi64((const __m128i *)&xmmword_2120), v20),\n v21),\n (__m128i)0LL);\n v23 = _mm_and_si128(\n _mm_cmpeq_epi8(\n _mm_cmpeq_epi8(\n _mm_subs_epu8(\n _mm_add_epi8(_mm_loadl_epi64((const __m128i *)&xmmword_2130),\n v20),\n v21),\n (__m128i)0LL),\n (__m128i)0LL),\n _mm_cmpeq_epi8((__m128i)0LL, v22));\n *(uint64_t *)(a2 + v19) =\n _mm_or_si128(\n _mm_andnot_si128(\n v22, _mm_or_si128(\n _mm_andnot_si128(\n v23, _mm_add_epi8(_mm_loadl_epi64((\n const __m128i *)&xmmword_2150),\n v20)),\n _mm_and_si128(v20, v23))),\n _mm_and_si128(_mm_add_epi8(v20, _mm_loadl_epi64(\n (const __m128i *)&xmmword_2160)),\n v22))\n .m128i_u64[0];\n result = (v7 & 4294967288) + (unsigned int)result;\n if ((v7 & 7) == 0) {\n LABEL_11:\n *(uint8_t *)(a2 + v5) = 0;\n return result;\n }\nLABEL_18:\n v24 = a1[(int)result];\n if ((unsigned char)(v24 - 97) <= 25u) {\n v24 -= 32;\n } else if ((unsigned char)(v24 - 65) < 26u) {\n v24 += 32;\n }\n *(uint8_t *)(a2 + (int)result) = v24;\n v25 = result + 1;\n if (v5 <= (int)result + 1) goto LABEL_11;\n v26 = a1[v25];\n if ((unsigned char)(v26 - 97) > 25u) {\n if ((unsigned char)(v26 - 65) < 26u) v26 += 32;\n } else {\n v26 -= 32;\n }\n *(uint8_t *)(a2 + v25) = v26;\n v27 = result + 2;\n if (v5 <= (int)result + 2) goto LABEL_11;\n v28 = a1[v27];\n if ((unsigned char)(v28 - 97) > 25u) {\n if ((unsigned char)(v28 - 65) < 26u) v28 += 32;\n } else {\n v28 -= 32;\n }\n *(uint8_t *)(a2 + v27) = v28;\n v29 = result + 3;\n if (v5 <= (int)result + 3) goto LABEL_11;\n v30 = a1[v29];\n if ((unsigned char)(v30 - 97) > 25u) {\n if ((unsigned char)(v30 - 65) < 26u) v30 += 32;\n } else {\n v30 -= 32;\n }\n *(uint8_t *)(a2 + v29) = v30;\n v31 = result + 4;\n if (v5 <= (int)result + 4) goto LABEL_11;\n v32 = a1[v31];\n if ((unsigned char)(v32 - 97) > 25u) {\n if ((unsigned char)(v32 - 65) < 26u) v32 += 32;\n } else {\n v32 -= 32;\n }\n *(uint8_t *)(a2 + v31) = v32;\n v33 = result + 5;\n if (v5 <= (int)result + 5) goto LABEL_11;\n v34 = a1[v33];\n if ((unsigned char)(v34 - 97) > 25u) {\n if ((unsigned char)(v34 - 65) < 26u) v34 += 32;\n } else {\n v34 -= 32;\n }\n result = (unsigned int)(result + 6);\n *(uint8_t *)(a2 + v33) = v34;\n if (v5 <= (int)result) goto LABEL_11;\n result = (int)result;\n v35 = a1[(int)result];\n if ((unsigned char)(v35 - 97) <= 25u) {\n v35 -= 32;\n } else if ((unsigned char)(v35 - 65) < 26u) {\n v35 += 32;\n }\n *(uint8_t *)(a2 + (int)result) = v35;\n *(uint8_t *)(a2 + v5) = 0;\n return result;\n}" + }, + { + "index": "HumanEval-C-28", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char* func0(char** strings, int count) {\n int length = 0;\n for (int i = 0; i < count; i++) {\n length += strlen(strings[i]);\n }\n char* out = (char*)malloc(length + 1);\n if (!out) {\n return NULL;\n }\n out[0] = '\\0';\n for (int i = 0; i < count; i++) {\n strcat(out, strings[i]);\n }\n return out;\n}", + "test": "#include \n#include \n\nint main() {\n char* result;\n char* empty_strings[] = {};\n result = func0(empty_strings, 0);\n assert(strcmp(result, \"\") == 0);\n free(result);\n\n char* strings1[] = {\"x\", \"y\", \"z\"};\n result = func0(strings1, 3);\n assert(strcmp(result, \"xyz\") == 0);\n free(result);\n\n char* strings2[] = {\"x\", \"y\", \"z\", \"w\", \"k\"};\n result = func0(strings2, 5);\n assert(strcmp(result, \"xyzwk\") == 0);\n free(result);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\njmp short loc_1259\nloc_122C:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; s\ncall _strlen\nmov edx, eax\nmov eax, [rbp+var_14]\nadd eax, edx\nmov [rbp+var_14], eax\nadd [rbp+var_10], 1\nloc_1259:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_2C]\njl short loc_122C\nmov eax, [rbp+var_14]\nadd eax, 1\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+dest], rax\ncmp [rbp+dest], 0\njnz short loc_1283\nmov eax, 0\njmp short locret_12C9\nloc_1283:\nmov rax, [rbp+dest]\nmov byte ptr [rax], 0\nmov [rbp+var_C], 0\njmp short loc_12BD\nloc_1293:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rdx, [rax]\nmov rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\nadd [rbp+var_C], 1\nloc_12BD:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_2C]\njl short loc_1293\nmov rax, [rbp+dest]\nlocret_12C9:\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2)\n{\n int v3; // [rsp+1Ch] [rbp-14h]\n int i; // [rsp+20h] [rbp-10h]\n int j; // [rsp+24h] [rbp-Ch]\n char *dest; // [rsp+28h] [rbp-8h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n v3 += strlen(*(const char **)(8LL * i + a1));\n dest = (char *)malloc(v3 + 1);\n if ( !dest )\n return 0LL;\n *dest = 0;\n for ( j = 0; j < a2; ++j )\n strcat(dest, *(const char **)(8LL * j + a1));\n return dest;\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\njmp short loc_1259\nloc_122C:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; s\ncall _strlen\nmov edx, eax\nmov eax, [rbp+var_14]\nadd eax, edx\nmov [rbp+var_14], eax\nadd [rbp+var_10], 1\nloc_1259:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_2C]\njl short loc_122C\nmov eax, [rbp+var_14]\nadd eax, 1\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+dest], rax\ncmp [rbp+dest], 0\njnz short loc_1283\nmov eax, 0\njmp short locret_12C9\nloc_1283:\nmov rax, [rbp+dest]\nmov byte ptr [rax], 0\nmov [rbp+var_C], 0\njmp short loc_12BD\nloc_1293:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rdx, [rax]\nmov rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\nadd [rbp+var_C], 1\nloc_12BD:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_2C]\njl short loc_1293\nmov rax, [rbp+dest]\nlocret_12C9:\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1209(__int64 a1, int a2)\n{\n int v3; // [rsp+1Ch] [rbp-14h]\n int i; // [rsp+20h] [rbp-10h]\n int j; // [rsp+24h] [rbp-Ch]\n char *dest; // [rsp+28h] [rbp-8h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n v3 += strlen(*(const char **)(8LL * i + a1));\n dest = (char *)malloc(v3 + 1);\n if ( !dest )\n return 0LL;\n *dest = 0;\n for ( j = 0; j < a2; ++j )\n strcat(dest, *(const char **)(8LL * j + a1));\n return dest;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1209(long long a1, int a2) {\n int v3;\n int i;\n int j;\n char *dest;\n v3 = 0;\n for (i = 0; i < a2; ++i) v3 += strlen(*(const char **)(8LL * i + a1));\n dest = (char *)malloc(v3 + 1);\n if (!dest) return 0LL;\n *dest = 0;\n for (j = 0; j < a2; ++j) strcat(dest, *(const char **)(8LL * j + a1));\n return dest;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2) {\n int v3;\n int i;\n int j;\n char *dest;\n v3 = 0;\n for (i = 0; i < a2; ++i) v3 += strlen(*(const char **)(8LL * i + a1));\n dest = (char *)malloc(v3 + 1);\n if (!dest) return 0LL;\n *dest = 0;\n for (j = 0; j < a2; ++j) strcat(dest, *(const char **)(8LL * j + a1));\n return dest;\n}" + }, + { + "index": "HumanEval-C-28", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char* func0(char** strings, int count) {\n int length = 0;\n for (int i = 0; i < count; i++) {\n length += strlen(strings[i]);\n }\n char* out = (char*)malloc(length + 1);\n if (!out) {\n return NULL;\n }\n out[0] = '\\0';\n for (int i = 0; i < count; i++) {\n strcat(out, strings[i]);\n }\n return out;\n}", + "test": "#include \n#include \n\nint main() {\n char* result;\n char* empty_strings[] = {};\n result = func0(empty_strings, 0);\n assert(strcmp(result, \"\") == 0);\n free(result);\n\n char* strings1[] = {\"x\", \"y\", \"z\"};\n result = func0(strings1, 3);\n assert(strcmp(result, \"xyz\") == 0);\n free(result);\n\n char* strings2[] = {\"x\", \"y\", \"z\", \"w\", \"k\"};\n result = func0(strings2, 5);\n assert(strcmp(result, \"xyzwk\") == 0);\n free(result);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r14, rdi\nmov r13d, esi\ntest esi, esi\njle short loc_128C\nmov rbx, rdi\nmovsxd rax, esi\nlea r12, [rdi+rax*8]\nmov ebp, 0\nloc_122E:\nmov rdi, [rbx]; s\ncall _strlen\nadd eax, ebp\nmov ebp, eax\nadd rbx, 8\ncmp rbx, r12\njnz short loc_122E\nadd eax, 1\nmovsxd rbx, eax\nmov rdi, rbx; size\ncall _malloc\nmov r12, rax\ntest rax, rax\njz short loc_1280\nmov byte ptr [r12], 0\nloc_125E:\nmov rbp, r14\nmovsxd r13, r13d\nlea r13, [r14+r13*8]\nloc_1268:\nmov rsi, [rbp+0]\nmov rdx, rbx\nmov rdi, r12\ncall ___strcat_chk\nadd rbp, 8\ncmp rbp, r13\njnz short loc_1268\nloc_1280:\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_128C:\nmov edi, 1; size\ncall _malloc\nmov r12, rax\ntest rax, rax\njz short loc_1280\nmov byte ptr [rax], 0\ntest r13d, r13d\njle short loc_1280\nmov ebx, 1\njmp short loc_125E", + "ida_pseudo": "_BYTE *__fastcall func0(const char **a1, int a2)\n{\n const char **v2; // rbx\n int v3; // ebp\n int v4; // eax\n size_t v5; // rbx\n _BYTE *v6; // rax\n _BYTE *v7; // r12\n const char **v8; // rbp\n _BYTE *v10; // rax\n\n if ( a2 <= 0 )\n {\n v10 = malloc(1uLL);\n v7 = v10;\n if ( v10 )\n *v10 = 0;\n }\n else\n {\n v2 = a1;\n v3 = 0;\n do\n {\n v4 = v3 + strlen(*v2);\n v3 = v4;\n ++v2;\n }\n while ( v2 != &a1[a2] );\n v5 = v4 + 1;\n v6 = malloc(v5);\n v7 = v6;\n if ( v6 )\n {\n *v6 = 0;\n v8 = a1;\n do\n __strcat_chk(v7, *v8++, v5);\n while ( v8 != &a1[a2] );\n }\n }\n return v7;\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r14, rdi\nmov r13d, esi\ntest esi, esi\njle short loc_128C\nmov rbx, rdi\nmovsxd rax, esi\nlea r12, [rdi+rax*8]\nmov ebp, 0\nloc_122E:\nmov rdi, [rbx]; s\ncall _strlen\nadd eax, ebp\nmov ebp, eax\nadd rbx, 8\ncmp rbx, r12\njnz short loc_122E\nadd eax, 1\nmovsxd rbx, eax\nmov rdi, rbx; size\ncall _malloc\nmov r12, rax\ntest rax, rax\njz short loc_1280\nmov byte ptr [r12], 0\nloc_125E:\nmov rbp, r14\nmovsxd r13, r13d\nlea r13, [r14+r13*8]\nloc_1268:\nmov rsi, [rbp+0]\nmov rdx, rbx\nmov rdi, r12\ncall ___strcat_chk\nadd rbp, 8\ncmp rbp, r13\njnz short loc_1268\nloc_1280:\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_128C:\nmov edi, 1; size\ncall _malloc\nmov r12, rax\ntest rax, rax\njz short loc_1280\nmov byte ptr [rax], 0\ntest r13d, r13d\njle short loc_1280\nmov ebx, 1\njmp short loc_125E", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1209(const char **a1, int a2)\n{\n const char **v2; // rbx\n int v3; // ebp\n int v4; // eax\n size_t v5; // rbx\n _BYTE *v6; // rax\n _BYTE *v7; // r12\n const char **v8; // rbp\n _BYTE *v10; // rax\n\n if ( a2 <= 0 )\n {\n v10 = malloc(1uLL);\n v7 = v10;\n if ( v10 )\n *v10 = 0;\n }\n else\n {\n v2 = a1;\n v3 = 0;\n do\n {\n v4 = v3 + strlen(*v2);\n v3 = v4;\n ++v2;\n }\n while ( v2 != &a1[a2] );\n v5 = v4 + 1;\n v6 = malloc(v5);\n v7 = v6;\n if ( v6 )\n {\n *v6 = 0;\n v8 = a1;\n do\n __strcat_chk(v7, *v8++, v5);\n while ( v8 != &a1[a2] );\n }\n }\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1209(const char **a1, int a2) {\n const char **v2;\n int v3;\n int v4;\n unsigned int v5;\n uint8_t *v6;\n uint8_t *v7;\n const char **v8;\n uint8_t *v10;\n if (a2 <= 0) {\n v10 = malloc(1uLL);\n v7 = v10;\n if (v10) *v10 = 0;\n } else {\n v2 = a1;\n v3 = 0;\n do {\n v4 = v3 + strlen(*v2);\n v3 = v4;\n ++v2;\n } while (v2 != &a1[a2]);\n v5 = v4 + 1;\n v6 = malloc(v5);\n v7 = v6;\n if (v6) {\n *v6 = 0;\n v8 = a1;\n do\n __strcat_chk(v7, *v8++, v5);\n while (v8 != &a1[a2]);\n }\n }\n return v7;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char **a1, int a2) {\n const char **v2;\n int v3;\n int v4;\n unsigned int v5;\n uint8_t *v6;\n uint8_t *v7;\n const char **v8;\n uint8_t *v10;\n if (a2 <= 0) {\n v10 = malloc(1uLL);\n v7 = v10;\n if (v10) *v10 = 0;\n } else {\n v2 = a1;\n v3 = 0;\n do {\n v4 = v3 + strlen(*v2);\n v3 = v4;\n ++v2;\n } while (v2 != &a1[a2]);\n v5 = v4 + 1;\n v6 = malloc(v5);\n v7 = v6;\n if (v6) {\n *v6 = 0;\n v8 = a1;\n do\n __strcat_chk(v7, *v8++, v5);\n while (v8 != &a1[a2]);\n }\n }\n return v7;\n}" + }, + { + "index": "HumanEval-C-28", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char* func0(char** strings, int count) {\n int length = 0;\n for (int i = 0; i < count; i++) {\n length += strlen(strings[i]);\n }\n char* out = (char*)malloc(length + 1);\n if (!out) {\n return NULL;\n }\n out[0] = '\\0';\n for (int i = 0; i < count; i++) {\n strcat(out, strings[i]);\n }\n return out;\n}", + "test": "#include \n#include \n\nint main() {\n char* result;\n char* empty_strings[] = {};\n result = func0(empty_strings, 0);\n assert(strcmp(result, \"\") == 0);\n free(result);\n\n char* strings1[] = {\"x\", \"y\", \"z\"};\n result = func0(strings1, 3);\n assert(strcmp(result, \"xyz\") == 0);\n free(result);\n\n char* strings2[] = {\"x\", \"y\", \"z\", \"w\", \"k\"};\n result = func0(strings2, 5);\n assert(strcmp(result, \"xyzwk\") == 0);\n free(result);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\ntest esi, esi\njle short loc_1420\nmovsxd rsi, esi\nmov rbx, rdi\nmov rbp, rdi\nxor r12d, r12d\nlea r13, [rdi+rsi*8]\nnop word ptr [rax+rax+00h]\nloc_13B8:\nmov rdi, [rbp+0]; s\nadd rbp, 8\ncall _strlen\nadd r12d, eax\ncmp r13, rbp\njnz short loc_13B8\nadd r12d, 1\nmovsxd r12, r12d\nmov rdi, r12; size\ncall _malloc\nmov rcx, rax\ntest rax, rax\njz short loc_140A\nmov byte ptr [rax], 0\nnop word ptr [rax+rax+00000000h]\nloc_13F0:\nmov rsi, [rbx]\nmov rdi, rcx\nmov rdx, r12\nadd rbx, 8\ncall ___strcat_chk\nmov rcx, rax\ncmp r13, rbx\njnz short loc_13F0\nloc_140A:\nadd rsp, 8\nmov rax, rcx\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1420:\nmov edi, 1; size\ncall _malloc\nmov rcx, rax\ntest rax, rax\njz short loc_140A\nmov byte ptr [rax], 0\nadd rsp, 8\nmov rax, rcx\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(const char **a1, int a2)\n{\n const char **v2; // rbx\n const char **v3; // rbp\n int v4; // r12d\n const char **v5; // r13\n const char *v6; // rdi\n size_t v7; // r12\n _BYTE *v8; // rax\n __int64 v9; // rcx\n __int64 v10; // rsi\n _BYTE *result; // rax\n\n if ( a2 > 0 )\n {\n v2 = a1;\n v3 = a1;\n v4 = 0;\n v5 = &a1[a2];\n do\n {\n v6 = *v3++;\n v4 += strlen(v6);\n }\n while ( v5 != v3 );\n v7 = v4 + 1;\n v8 = malloc(v7);\n v9 = (__int64)v8;\n if ( v8 )\n {\n *v8 = 0;\n do\n {\n v10 = (__int64)*v2++;\n v9 = __strcat_chk(v9, v10, v7);\n }\n while ( v5 != v2 );\n }\n return (_BYTE *)v9;\n }\n result = malloc(1uLL);\n v9 = (__int64)result;\n if ( !result )\n return (_BYTE *)v9;\n *result = 0;\n return result;\n}", + "ida_strip_asm": "sub_1390:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\ntest esi, esi\njle short loc_1420\nmovsxd rsi, esi\nmov rbx, rdi\nmov rbp, rdi\nxor r12d, r12d\nlea r13, [rdi+rsi*8]\nnop word ptr [rax+rax+00h]\nloc_13B8:\nmov rdi, [rbp+0]; s\nadd rbp, 8\ncall _strlen\nadd r12d, eax\ncmp r13, rbp\njnz short loc_13B8\nadd r12d, 1\nmovsxd r12, r12d\nmov rdi, r12; size\ncall _malloc\nmov rcx, rax\ntest rax, rax\njz short loc_140A\nmov byte ptr [rax], 0\nnop word ptr [rax+rax+00000000h]\nloc_13F0:\nmov rsi, [rbx]\nmov rdi, rcx\nmov rdx, r12\nadd rbx, 8\ncall ___strcat_chk\nmov rcx, rax\ncmp r13, rbx\njnz short loc_13F0\nloc_140A:\nadd rsp, 8\nmov rax, rcx\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1420:\nmov edi, 1; size\ncall _malloc\nmov rcx, rax\ntest rax, rax\njz short loc_140A\nmov byte ptr [rax], 0\nadd rsp, 8\nmov rax, rcx\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1390(const char **a1, int a2)\n{\n const char **v2; // rbx\n const char **v3; // rbp\n int v4; // r12d\n const char **v5; // r13\n const char *v6; // rdi\n size_t v7; // r12\n _BYTE *v8; // rax\n __int64 v9; // rcx\n __int64 v10; // rsi\n _BYTE *result; // rax\n\n if ( a2 > 0 )\n {\n v2 = a1;\n v3 = a1;\n v4 = 0;\n v5 = &a1[a2];\n do\n {\n v6 = *v3++;\n v4 += strlen(v6);\n }\n while ( v5 != v3 );\n v7 = v4 + 1;\n v8 = malloc(v7);\n v9 = (__int64)v8;\n if ( v8 )\n {\n *v8 = 0;\n do\n {\n v10 = (__int64)*v2++;\n v9 = __strcat_chk(v9, v10, v7);\n }\n while ( v5 != v2 );\n }\n return (_BYTE *)v9;\n }\n result = malloc(1uLL);\n v9 = (__int64)result;\n if ( !result )\n return (_BYTE *)v9;\n *result = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1390(const char **a1, int a2) {\n const char **v2;\n const char **v3;\n int v4;\n const char **v5;\n const char *v6;\n unsigned int v7;\n uint8_t *v8;\n long long v9;\n long long v10;\n uint8_t *result;\n if (a2 > 0) {\n v2 = a1;\n v3 = a1;\n v4 = 0;\n v5 = &a1[a2];\n do {\n v6 = *v3++;\n v4 += strlen(v6);\n } while (v5 != v3);\n v7 = v4 + 1;\n v8 = malloc(v7);\n v9 = (long long)v8;\n if (v8) {\n *v8 = 0;\n do {\n v10 = (long long)*v2++;\n v9 = __strcat_chk(v9, v10, v7);\n } while (v5 != v2);\n }\n return (uint8_t *)v9;\n }\n result = malloc(1uLL);\n v9 = (long long)result;\n if (!result) return (uint8_t *)v9;\n *result = 0;\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char **a1, int a2) {\n const char **v2;\n const char **v3;\n int v4;\n const char **v5;\n const char *v6;\n unsigned int v7;\n uint8_t *v8;\n long long v9;\n long long v10;\n uint8_t *result;\n if (a2 > 0) {\n v2 = a1;\n v3 = a1;\n v4 = 0;\n v5 = &a1[a2];\n do {\n v6 = *v3++;\n v4 += strlen(v6);\n } while (v5 != v3);\n v7 = v4 + 1;\n v8 = malloc(v7);\n v9 = (long long)v8;\n if (v8) {\n *v8 = 0;\n do {\n v10 = (long long)*v2++;\n v9 = __strcat_chk(v9, v10, v7);\n } while (v5 != v2);\n }\n return (uint8_t *)v9;\n }\n result = malloc(1uLL);\n v9 = (long long)result;\n if (!result) return (uint8_t *)v9;\n *result = 0;\n return result;\n}" + }, + { + "index": "HumanEval-C-28", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char* func0(char** strings, int count) {\n int length = 0;\n for (int i = 0; i < count; i++) {\n length += strlen(strings[i]);\n }\n char* out = (char*)malloc(length + 1);\n if (!out) {\n return NULL;\n }\n out[0] = '\\0';\n for (int i = 0; i < count; i++) {\n strcat(out, strings[i]);\n }\n return out;\n}", + "test": "#include \n#include \n\nint main() {\n char* result;\n char* empty_strings[] = {};\n result = func0(empty_strings, 0);\n assert(strcmp(result, \"\") == 0);\n free(result);\n\n char* strings1[] = {\"x\", \"y\", \"z\"};\n result = func0(strings1, 3);\n assert(strcmp(result, \"xyz\") == 0);\n free(result);\n\n char* strings2[] = {\"x\", \"y\", \"z\", \"w\", \"k\"};\n result = func0(strings2, 5);\n assert(strcmp(result, \"xyzwk\") == 0);\n free(result);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\ntest esi, esi\njle short loc_1420\nmovsxd rsi, esi\nmov rbx, rdi\nmov rbp, rdi\nxor r12d, r12d\nlea r13, [rdi+rsi*8]\nnop word ptr [rax+rax+00h]\nloc_13B8:\nmov rdi, [rbp+0]; s\nadd rbp, 8\ncall _strlen\nadd r12d, eax\ncmp r13, rbp\njnz short loc_13B8\nadd r12d, 1\nmovsxd r12, r12d\nmov rdi, r12; size\ncall _malloc\nmov rcx, rax\ntest rax, rax\njz short loc_140A\nmov byte ptr [rax], 0\nnop word ptr [rax+rax+00000000h]\nloc_13F0:\nmov rsi, [rbx]\nmov rdi, rcx\nmov rdx, r12\nadd rbx, 8\ncall ___strcat_chk\nmov rcx, rax\ncmp r13, rbx\njnz short loc_13F0\nloc_140A:\nadd rsp, 8\nmov rax, rcx\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1420:\nmov edi, 1; size\ncall _malloc\nmov rcx, rax\ntest rax, rax\njz short loc_140A\nmov byte ptr [rax], 0\nadd rsp, 8\nmov rax, rcx\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(const char **a1, int a2)\n{\n const char **v2; // rbx\n const char **v3; // rbp\n int v4; // r12d\n const char **v5; // r13\n const char *v6; // rdi\n size_t v7; // r12\n _BYTE *v8; // rax\n __int64 v9; // rcx\n __int64 v10; // rsi\n _BYTE *result; // rax\n\n if ( a2 > 0 )\n {\n v2 = a1;\n v3 = a1;\n v4 = 0;\n v5 = &a1[a2];\n do\n {\n v6 = *v3++;\n v4 += strlen(v6);\n }\n while ( v5 != v3 );\n v7 = v4 + 1;\n v8 = malloc(v7);\n v9 = (__int64)v8;\n if ( v8 )\n {\n *v8 = 0;\n do\n {\n v10 = (__int64)*v2++;\n v9 = __strcat_chk(v9, v10, v7);\n }\n while ( v5 != v2 );\n }\n return (_BYTE *)v9;\n }\n result = malloc(1uLL);\n v9 = (__int64)result;\n if ( !result )\n return (_BYTE *)v9;\n *result = 0;\n return result;\n}", + "ida_strip_asm": "sub_1390:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\ntest esi, esi\njle short loc_1420\nmovsxd rsi, esi\nmov rbx, rdi\nmov rbp, rdi\nxor r12d, r12d\nlea r13, [rdi+rsi*8]\nnop word ptr [rax+rax+00h]\nloc_13B8:\nmov rdi, [rbp+0]; s\nadd rbp, 8\ncall _strlen\nadd r12d, eax\ncmp r13, rbp\njnz short loc_13B8\nadd r12d, 1\nmovsxd r12, r12d\nmov rdi, r12; size\ncall _malloc\nmov rcx, rax\ntest rax, rax\njz short loc_140A\nmov byte ptr [rax], 0\nnop word ptr [rax+rax+00000000h]\nloc_13F0:\nmov rsi, [rbx]\nmov rdi, rcx\nmov rdx, r12\nadd rbx, 8\ncall ___strcat_chk\nmov rcx, rax\ncmp r13, rbx\njnz short loc_13F0\nloc_140A:\nadd rsp, 8\nmov rax, rcx\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1420:\nmov edi, 1; size\ncall _malloc\nmov rcx, rax\ntest rax, rax\njz short loc_140A\nmov byte ptr [rax], 0\nadd rsp, 8\nmov rax, rcx\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1390(const char **a1, int a2)\n{\n const char **v2; // rbx\n const char **v3; // rbp\n int v4; // r12d\n const char **v5; // r13\n const char *v6; // rdi\n size_t v7; // r12\n _BYTE *v8; // rax\n __int64 v9; // rcx\n __int64 v10; // rsi\n _BYTE *result; // rax\n\n if ( a2 > 0 )\n {\n v2 = a1;\n v3 = a1;\n v4 = 0;\n v5 = &a1[a2];\n do\n {\n v6 = *v3++;\n v4 += strlen(v6);\n }\n while ( v5 != v3 );\n v7 = v4 + 1;\n v8 = malloc(v7);\n v9 = (__int64)v8;\n if ( v8 )\n {\n *v8 = 0;\n do\n {\n v10 = (__int64)*v2++;\n v9 = __strcat_chk(v9, v10, v7);\n }\n while ( v5 != v2 );\n }\n return (_BYTE *)v9;\n }\n result = malloc(1uLL);\n v9 = (__int64)result;\n if ( !result )\n return (_BYTE *)v9;\n *result = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1390(const char **a1, int a2) {\n const char **v2;\n const char **v3;\n int v4;\n const char **v5;\n const char *v6;\n unsigned int v7;\n uint8_t *v8;\n long long v9;\n long long v10;\n uint8_t *result;\n if (a2 > 0) {\n v2 = a1;\n v3 = a1;\n v4 = 0;\n v5 = &a1[a2];\n do {\n v6 = *v3++;\n v4 += strlen(v6);\n } while (v5 != v3);\n v7 = v4 + 1;\n v8 = malloc(v7);\n v9 = (long long)v8;\n if (v8) {\n *v8 = 0;\n do {\n v10 = (long long)*v2++;\n v9 = __strcat_chk(v9, v10, v7);\n } while (v5 != v2);\n }\n return (uint8_t *)v9;\n }\n result = malloc(1uLL);\n v9 = (long long)result;\n if (!result) return (uint8_t *)v9;\n *result = 0;\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char **a1, int a2) {\n const char **v2;\n const char **v3;\n int v4;\n const char **v5;\n const char *v6;\n unsigned int v7;\n uint8_t *v8;\n long long v9;\n long long v10;\n uint8_t *result;\n if (a2 > 0) {\n v2 = a1;\n v3 = a1;\n v4 = 0;\n v5 = &a1[a2];\n do {\n v6 = *v3++;\n v4 += strlen(v6);\n } while (v5 != v3);\n v7 = v4 + 1;\n v8 = malloc(v7);\n v9 = (long long)v8;\n if (v8) {\n *v8 = 0;\n do {\n v10 = (long long)*v2++;\n v9 = __strcat_chk(v9, v10, v7);\n } while (v5 != v2);\n }\n return (uint8_t *)v9;\n }\n result = malloc(1uLL);\n v9 = (long long)result;\n if (!result) return (uint8_t *)v9;\n *result = 0;\n return result;\n}" + }, + { + "index": "HumanEval-C-29", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int func0(char** strings, int count, const char* prefix, char*** out) {\n int prefix_length = strlen(prefix);\n *out = (char**)malloc(count * sizeof(char*));\n int out_count = 0;\n for (int i = 0; i < count; i++) {\n if (strncmp(strings[i], prefix, prefix_length) == 0) {\n (*out)[out_count++] = strings[i];\n }\n }\n return out_count;\n}", + "test": "#include \n#include \n\n// Helper function to compare two arrays of strings\nint issame(char** a, int a_count, char** b, int b_count) {\n if (a_count != b_count) return 0;\n for (int i = 0; i < a_count; i++) {\n if (strcmp(a[i], b[i]) != 0) return 0;\n }\n return 1;\n}\n\nint main() {\n char** result;\n int count;\n const char* empty[] = {};\n count = func0(empty, 0, \"john\", &result);\n assert(issame(result, count, empty, 0));\n free(result);\n\n char* strings[] = {\"xxx\", \"asd\", \"xxy\", \"john doe\", \"xxxAAA\", \"xxx\"};\n char* expected[] = {\"xxx\", \"xxxAAA\", \"xxx\"};\n count = func0(strings, 6, \"xxx\", &result);\n assert(issame(result, count, expected, 3));\n free(result);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+s], rdx\nmov [rbp+var_30], rcx\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov rdx, rax\nmov rax, [rbp+var_30]\nmov [rax], rdx\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_12C7\nloc_125E:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax; n\nmov eax, [rbp+var_8]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov rax, [rax]\nmov rcx, [rbp+s]\nmov rsi, rcx; s2\nmov rdi, rax; s1\ncall _strncmp\ntest eax, eax\njnz short loc_12C3\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov rax, [rbp+var_30]\nmov rsi, [rax]\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\ncdqe\nshl rax, 3\nlea rdx, [rsi+rax]\nmov rax, [rcx]\nmov [rdx], rax\nloc_12C3:\nadd [rbp+var_8], 1\nloc_12C7:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_125E\nmov eax, [rbp+var_C]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, const char *a3, void **a4)\n{\n int v4; // eax\n unsigned int v8; // [rsp+24h] [rbp-Ch]\n int i; // [rsp+28h] [rbp-8h]\n int v10; // [rsp+2Ch] [rbp-4h]\n\n v10 = strlen(a3);\n *a4 = malloc(8LL * a2);\n v8 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( !strncmp(*(const char **)(8LL * i + a1), a3, v10) )\n {\n v4 = v8++;\n *((_QWORD *)*a4 + v4) = *(_QWORD *)(8LL * i + a1);\n }\n }\n return v8;\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+s], rdx\nmov [rbp+var_30], rcx\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov rdx, rax\nmov rax, [rbp+var_30]\nmov [rax], rdx\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_12C7\nloc_125E:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax; n\nmov eax, [rbp+var_8]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov rax, [rax]\nmov rcx, [rbp+s]\nmov rsi, rcx; s2\nmov rdi, rax; s1\ncall _strncmp\ntest eax, eax\njnz short loc_12C3\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov rax, [rbp+var_30]\nmov rsi, [rax]\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\ncdqe\nshl rax, 3\nlea rdx, [rsi+rax]\nmov rax, [rcx]\nmov [rdx], rax\nloc_12C3:\nadd [rbp+var_8], 1\nloc_12C7:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_125E\nmov eax, [rbp+var_C]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1209(__int64 a1, int a2, const char *a3, void **a4)\n{\n int v4; // eax\n unsigned int v8; // [rsp+24h] [rbp-Ch]\n int i; // [rsp+28h] [rbp-8h]\n int v10; // [rsp+2Ch] [rbp-4h]\n\n v10 = strlen(a3);\n *a4 = malloc(8LL * a2);\n v8 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( !strncmp(*(const char **)(8LL * i + a1), a3, v10) )\n {\n v4 = v8++;\n *((_QWORD *)*a4 + v4) = *(_QWORD *)(8LL * i + a1);\n }\n }\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1209(long long a1, int a2, const char *a3, void **a4) {\n int v4;\n unsigned int v8;\n int i;\n int v10;\n v10 = strlen(a3);\n *a4 = malloc(8LL * a2);\n v8 = 0;\n for (i = 0; i < a2; ++i) {\n if (!strncmp(*(const char **)(8LL * i + a1), a3, v10)) {\n v4 = v8++;\n *((uint64_t *)*a4 + v4) = *(uint64_t *)(8LL * i + a1);\n }\n }\n return v8;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, const char *a3, void **a4) {\n int v4;\n unsigned int v8;\n int i;\n int v10;\n v10 = strlen(a3);\n *a4 = malloc(8LL * a2);\n v8 = 0;\n for (i = 0; i < a2; ++i) {\n if (!strncmp(*(const char **)(8LL * i + a1), a3, v10)) {\n v4 = v8++;\n *((uint64_t *)*a4 + v4) = *(uint64_t *)(8LL * i + a1);\n }\n }\n return v8;\n}" + }, + { + "index": "HumanEval-C-29", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int func0(char** strings, int count, const char* prefix, char*** out) {\n int prefix_length = strlen(prefix);\n *out = (char**)malloc(count * sizeof(char*));\n int out_count = 0;\n for (int i = 0; i < count; i++) {\n if (strncmp(strings[i], prefix, prefix_length) == 0) {\n (*out)[out_count++] = strings[i];\n }\n }\n return out_count;\n}", + "test": "#include \n#include \n\n// Helper function to compare two arrays of strings\nint issame(char** a, int a_count, char** b, int b_count) {\n if (a_count != b_count) return 0;\n for (int i = 0; i < a_count; i++) {\n if (strcmp(a[i], b[i]) != 0) return 0;\n }\n return 1;\n}\n\nint main() {\n char** result;\n int count;\n const char* empty[] = {};\n count = func0(empty, 0, \"john\", &result);\n assert(issame(result, count, empty, 0));\n free(result);\n\n char* strings[] = {\"xxx\", \"asd\", \"xxy\", \"john doe\", \"xxxAAA\", \"xxx\"};\n char* expected[] = {\"xxx\", \"xxxAAA\", \"xxx\"};\n count = func0(strings, 6, \"xxx\", &result);\n assert(issame(result, count, expected, 3));\n free(result);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov r13, rdi\nmov ebx, esi\nmov rdi, rdx; s\nmov [rsp+48h+s2], rdx\nmov r15, rcx\ncall _strlen\nmov r14d, eax\nmovsxd rbp, ebx\nshl rbp, 3\nmov rdi, rbp; size\ncall _malloc\nmov [r15], rax\ntest ebx, ebx\njle short loc_128B\nmov rbx, r13\nadd r13, rbp\nmov r12d, 0\nmovsxd r14, r14d\njmp short loc_1263\nloc_125A:\nadd rbx, 8\ncmp rbx, r13\njz short loc_1291\nloc_1263:\nmov rbp, [rbx]\nmov rdx, r14; n\nmov rsi, [rsp+48h+s2]; s2\nmov rdi, rbp; s1\ncall _strncmp\ntest eax, eax\njnz short loc_125A\nmovsxd rdx, r12d\nmov rax, [r15]\nmov [rax+rdx*8], rbp\nlea r12d, [r12+1]\njmp short loc_125A\nloc_128B:\nmov r12d, 0\nloc_1291:\nmov eax, r12d\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char **a1, int a2, const char *a3, void **a4)\n{\n int v5; // r14d\n const char **v6; // rbx\n unsigned int v7; // r12d\n const char *v8; // rbp\n\n v5 = strlen(a3);\n *a4 = malloc(8LL * a2);\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v6 = a1;\n v7 = 0;\n do\n {\n v8 = *v6;\n if ( !strncmp(*v6, a3, v5) )\n *((_QWORD *)*a4 + (int)v7++) = v8;\n ++v6;\n }\n while ( v6 != &a1[a2] );\n }\n return v7;\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov r13, rdi\nmov ebx, esi\nmov rdi, rdx; s\nmov [rsp+48h+s2], rdx\nmov r15, rcx\ncall _strlen\nmov r14d, eax\nmovsxd rbp, ebx\nshl rbp, 3\nmov rdi, rbp; size\ncall _malloc\nmov [r15], rax\ntest ebx, ebx\njle short loc_128B\nmov rbx, r13\nadd r13, rbp\nmov r12d, 0\nmovsxd r14, r14d\njmp short loc_1263\nloc_125A:\nadd rbx, 8\ncmp rbx, r13\njz short loc_1291\nloc_1263:\nmov rbp, [rbx]\nmov rdx, r14; n\nmov rsi, [rsp+48h+s2]; s2\nmov rdi, rbp; s1\ncall _strncmp\ntest eax, eax\njnz short loc_125A\nmovsxd rdx, r12d\nmov rax, [r15]\nmov [rax+rdx*8], rbp\nlea r12d, [r12+1]\njmp short loc_125A\nloc_128B:\nmov r12d, 0\nloc_1291:\nmov eax, r12d\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1209(const char **a1, int a2, const char *a3, void **a4)\n{\n int v5; // r14d\n const char **v6; // rbx\n unsigned int v7; // r12d\n const char *v8; // rbp\n\n v5 = strlen(a3);\n *a4 = malloc(8LL * a2);\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v6 = a1;\n v7 = 0;\n do\n {\n v8 = *v6;\n if ( !strncmp(*v6, a3, v5) )\n *((_QWORD *)*a4 + (int)v7++) = v8;\n ++v6;\n }\n while ( v6 != &a1[a2] );\n }\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1209(const char **a1, int a2, const char *a3, void **a4) {\n int v5;\n const char **v6;\n unsigned int v7;\n const char *v8;\n v5 = strlen(a3);\n *a4 = malloc(8LL * a2);\n if (a2 <= 0) {\n return 0;\n } else {\n v6 = a1;\n v7 = 0;\n do {\n v8 = *v6;\n if (!strncmp(*v6, a3, v5)) *((uint64_t *)*a4 + (int)v7++) = v8;\n ++v6;\n } while (v6 != &a1[a2]);\n }\n return v7;\n}", + "ida_pseudo_norm": "long long func0(const char **a1, int a2, const char *a3, void **a4) {\n int v5;\n const char **v6;\n unsigned int v7;\n const char *v8;\n v5 = strlen(a3);\n *a4 = malloc(8LL * a2);\n if (a2 <= 0) {\n return 0;\n } else {\n v6 = a1;\n v7 = 0;\n do {\n v8 = *v6;\n if (!strncmp(*v6, a3, v5)) *((uint64_t *)*a4 + (int)v7++) = v8;\n ++v6;\n } while (v6 != &a1[a2]);\n }\n return v7;\n}" + }, + { + "index": "HumanEval-C-29", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int func0(char** strings, int count, const char* prefix, char*** out) {\n int prefix_length = strlen(prefix);\n *out = (char**)malloc(count * sizeof(char*));\n int out_count = 0;\n for (int i = 0; i < count; i++) {\n if (strncmp(strings[i], prefix, prefix_length) == 0) {\n (*out)[out_count++] = strings[i];\n }\n }\n return out_count;\n}", + "test": "#include \n#include \n\n// Helper function to compare two arrays of strings\nint issame(char** a, int a_count, char** b, int b_count) {\n if (a_count != b_count) return 0;\n for (int i = 0; i < a_count; i++) {\n if (strcmp(a[i], b[i]) != 0) return 0;\n }\n return 1;\n}\n\nint main() {\n char** result;\n int count;\n const char* empty[] = {};\n count = func0(empty, 0, \"john\", &result);\n assert(issame(result, count, empty, 0));\n free(result);\n\n char* strings[] = {\"xxx\", \"asd\", \"xxy\", \"john doe\", \"xxxAAA\", \"xxx\"};\n char* expected[] = {\"xxx\", \"xxxAAA\", \"xxx\"};\n count = func0(strings, 6, \"xxx\", &result);\n assert(issame(result, count, expected, 3));\n free(result);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\nmovsxd r15, esi\npush r14\npush r13\nmov r13, rdx\npush r12\npush rbp\nmov rbp, r15\nshl r15, 3\npush rbx\nmov rbx, rdi\nmov rdi, rdx; s\nsub rsp, 18h\nmov [rsp+48h+var_40], rcx\ncall _strlen\nmov rdi, r15; size\nmov r12, rax\ncall _malloc\nmov rcx, [rsp+48h+var_40]\nmov [rsp+48h+var_48], rax\nmov [rcx], rax\ntest ebp, ebp\njle short loc_1478\nmovsxd r12, r12d\nadd r15, rbx\nxor ebp, ebp\nnop word ptr [rax+rax+00h]\nloc_1438:\nmov r14, [rbx]\nmov rdx, r12; n\nmov rsi, r13; s2\nmov rdi, r14; s1\ncall _strncmp\ntest eax, eax\njnz short loc_145B\nmov rcx, [rsp+48h+var_48]\nmovsxd rax, ebp\nadd ebp, 1\nmov [rcx+rax*8], r14\nloc_145B:\nadd rbx, 8\ncmp rbx, r15\njnz short loc_1438\nloc_1464:\nadd rsp, 18h\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1478:\nxor ebp, ebp\njmp short loc_1464", + "ida_pseudo": "__int64 __fastcall func0(const char **a1, int a2, const char *a3, _QWORD *a4)\n{\n const char **v5; // rbx\n int v6; // r12d\n unsigned int v7; // ebp\n const char *v8; // r14\n __int64 v9; // rax\n _QWORD *v11; // [rsp+0h] [rbp-48h]\n\n v5 = a1;\n v6 = strlen(a3);\n v11 = malloc(8LL * a2);\n *a4 = v11;\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v7 = 0;\n do\n {\n v8 = *v5;\n if ( !strncmp(*v5, a3, v6) )\n {\n v9 = (int)v7++;\n v11[v9] = v8;\n }\n ++v5;\n }\n while ( v5 != &a1[a2] );\n }\n return v7;\n}", + "ida_strip_asm": "sub_13E0:\nendbr64\npush r15\nmovsxd r15, esi\npush r14\npush r13\nmov r13, rdx\npush r12\npush rbp\nmov rbp, r15\nshl r15, 3\npush rbx\nmov rbx, rdi\nmov rdi, rdx; s\nsub rsp, 18h\nmov [rsp+48h+var_40], rcx\ncall _strlen\nmov rdi, r15; size\nmov r12, rax\ncall _malloc\nmov rcx, [rsp+48h+var_40]\nmov [rsp+48h+var_48], rax\nmov [rcx], rax\ntest ebp, ebp\njle short loc_1478\nmovsxd r12, r12d\nadd r15, rbx\nxor ebp, ebp\nnop word ptr [rax+rax+00h]\nloc_1438:\nmov r14, [rbx]\nmov rdx, r12; n\nmov rsi, r13; s2\nmov rdi, r14; s1\ncall _strncmp\ntest eax, eax\njnz short loc_145B\nmov rcx, [rsp+48h+var_48]\nmovsxd rax, ebp\nadd ebp, 1\nmov [rcx+rax*8], r14\nloc_145B:\nadd rbx, 8\ncmp rbx, r15\njnz short loc_1438\nloc_1464:\nadd rsp, 18h\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1478:\nxor ebp, ebp\njmp short loc_1464", + "ida_strip_pseudo": "__int64 __fastcall sub_13E0(const char **a1, int a2, const char *a3, _QWORD *a4)\n{\n const char **v5; // rbx\n int v6; // r12d\n unsigned int v7; // ebp\n const char *v8; // r14\n __int64 v9; // rax\n _QWORD *v11; // [rsp+0h] [rbp-48h]\n\n v5 = a1;\n v6 = strlen(a3);\n v11 = malloc(8LL * a2);\n *a4 = v11;\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v7 = 0;\n do\n {\n v8 = *v5;\n if ( !strncmp(*v5, a3, v6) )\n {\n v9 = (int)v7++;\n v11[v9] = v8;\n }\n ++v5;\n }\n while ( v5 != &a1[a2] );\n }\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_13E0(const char **a1, int a2, const char *a3, uint64_t *a4) {\n const char **v5;\n int v6;\n unsigned int v7;\n const char *v8;\n long long v9;\n uint64_t *v11;\n v5 = a1;\n v6 = strlen(a3);\n v11 = malloc(8LL * a2);\n *a4 = v11;\n if (a2 <= 0) {\n return 0;\n } else {\n v7 = 0;\n do {\n v8 = *v5;\n if (!strncmp(*v5, a3, v6)) {\n v9 = (int)v7++;\n v11[v9] = v8;\n }\n ++v5;\n } while (v5 != &a1[a2]);\n }\n return v7;\n}", + "ida_pseudo_norm": "long long func0(const char **a1, int a2, const char *a3, uint64_t *a4) {\n const char **v5;\n int v6;\n unsigned int v7;\n const char *v8;\n long long v9;\n uint64_t *v11;\n v5 = a1;\n v6 = strlen(a3);\n v11 = malloc(8LL * a2);\n *a4 = v11;\n if (a2 <= 0) {\n return 0;\n } else {\n v7 = 0;\n do {\n v8 = *v5;\n if (!strncmp(*v5, a3, v6)) {\n v9 = (int)v7++;\n v11[v9] = v8;\n }\n ++v5;\n } while (v5 != &a1[a2]);\n }\n return v7;\n}" + }, + { + "index": "HumanEval-C-29", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int func0(char** strings, int count, const char* prefix, char*** out) {\n int prefix_length = strlen(prefix);\n *out = (char**)malloc(count * sizeof(char*));\n int out_count = 0;\n for (int i = 0; i < count; i++) {\n if (strncmp(strings[i], prefix, prefix_length) == 0) {\n (*out)[out_count++] = strings[i];\n }\n }\n return out_count;\n}", + "test": "#include \n#include \n\n// Helper function to compare two arrays of strings\nint issame(char** a, int a_count, char** b, int b_count) {\n if (a_count != b_count) return 0;\n for (int i = 0; i < a_count; i++) {\n if (strcmp(a[i], b[i]) != 0) return 0;\n }\n return 1;\n}\n\nint main() {\n char** result;\n int count;\n const char* empty[] = {};\n count = func0(empty, 0, \"john\", &result);\n assert(issame(result, count, empty, 0));\n free(result);\n\n char* strings[] = {\"xxx\", \"asd\", \"xxy\", \"john doe\", \"xxxAAA\", \"xxx\"};\n char* expected[] = {\"xxx\", \"xxxAAA\", \"xxx\"};\n count = func0(strings, 6, \"xxx\", &result);\n assert(issame(result, count, expected, 3));\n free(result);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\nmovsxd r15, esi\npush r14\npush r13\nmov r13, rdx\npush r12\npush rbp\nmov rbp, r15\nshl r15, 3\npush rbx\nmov rbx, rdi\nmov rdi, rdx; s\nsub rsp, 18h\nmov [rsp+48h+var_40], rcx\ncall _strlen\nmov rdi, r15; size\nmov r12, rax\ncall _malloc\nmov rcx, [rsp+48h+var_40]\nmov [rsp+48h+var_48], rax\nmov [rcx], rax\ntest ebp, ebp\njle short loc_1478\nmovsxd r12, r12d\nadd r15, rbx\nxor ebp, ebp\nnop word ptr [rax+rax+00h]\nloc_1438:\nmov r14, [rbx]\nmov rdx, r12; n\nmov rsi, r13; s2\nmov rdi, r14; s1\ncall _strncmp\ntest eax, eax\njnz short loc_145B\nmov rcx, [rsp+48h+var_48]\nmovsxd rax, ebp\nadd ebp, 1\nmov [rcx+rax*8], r14\nloc_145B:\nadd rbx, 8\ncmp rbx, r15\njnz short loc_1438\nloc_1464:\nadd rsp, 18h\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1478:\nxor ebp, ebp\njmp short loc_1464", + "ida_pseudo": "__int64 __fastcall func0(const char **a1, int a2, const char *a3, _QWORD *a4)\n{\n const char **v5; // rbx\n int v6; // r12d\n unsigned int v7; // ebp\n const char *v8; // r14\n __int64 v9; // rax\n _QWORD *v11; // [rsp+0h] [rbp-48h]\n\n v5 = a1;\n v6 = strlen(a3);\n v11 = malloc(8LL * a2);\n *a4 = v11;\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v7 = 0;\n do\n {\n v8 = *v5;\n if ( !strncmp(*v5, a3, v6) )\n {\n v9 = (int)v7++;\n v11[v9] = v8;\n }\n ++v5;\n }\n while ( v5 != &a1[a2] );\n }\n return v7;\n}", + "ida_strip_asm": "sub_13E0:\nendbr64\npush r15\nmovsxd r15, esi\npush r14\npush r13\nmov r13, rdx\npush r12\npush rbp\nmov rbp, r15\nshl r15, 3\npush rbx\nmov rbx, rdi\nmov rdi, rdx; s\nsub rsp, 18h\nmov [rsp+48h+var_40], rcx\ncall _strlen\nmov rdi, r15; size\nmov r12, rax\ncall _malloc\nmov rcx, [rsp+48h+var_40]\nmov [rsp+48h+var_48], rax\nmov [rcx], rax\ntest ebp, ebp\njle short loc_1478\nmovsxd r12, r12d\nadd r15, rbx\nxor ebp, ebp\nnop word ptr [rax+rax+00h]\nloc_1438:\nmov r14, [rbx]\nmov rdx, r12; n\nmov rsi, r13; s2\nmov rdi, r14; s1\ncall _strncmp\ntest eax, eax\njnz short loc_145B\nmov rcx, [rsp+48h+var_48]\nmovsxd rax, ebp\nadd ebp, 1\nmov [rcx+rax*8], r14\nloc_145B:\nadd rbx, 8\ncmp rbx, r15\njnz short loc_1438\nloc_1464:\nadd rsp, 18h\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1478:\nxor ebp, ebp\njmp short loc_1464", + "ida_strip_pseudo": "__int64 __fastcall sub_13E0(const char **a1, int a2, const char *a3, _QWORD *a4)\n{\n const char **v5; // rbx\n int v6; // r12d\n unsigned int v7; // ebp\n const char *v8; // r14\n __int64 v9; // rax\n _QWORD *v11; // [rsp+0h] [rbp-48h]\n\n v5 = a1;\n v6 = strlen(a3);\n v11 = malloc(8LL * a2);\n *a4 = v11;\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v7 = 0;\n do\n {\n v8 = *v5;\n if ( !strncmp(*v5, a3, v6) )\n {\n v9 = (int)v7++;\n v11[v9] = v8;\n }\n ++v5;\n }\n while ( v5 != &a1[a2] );\n }\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_13E0(const char **a1, int a2, const char *a3, uint64_t *a4) {\n const char **v5;\n int v6;\n unsigned int v7;\n const char *v8;\n long long v9;\n uint64_t *v11;\n v5 = a1;\n v6 = strlen(a3);\n v11 = malloc(8LL * a2);\n *a4 = v11;\n if (a2 <= 0) {\n return 0;\n } else {\n v7 = 0;\n do {\n v8 = *v5;\n if (!strncmp(*v5, a3, v6)) {\n v9 = (int)v7++;\n v11[v9] = v8;\n }\n ++v5;\n } while (v5 != &a1[a2]);\n }\n return v7;\n}", + "ida_pseudo_norm": "long long func0(const char **a1, int a2, const char *a3, uint64_t *a4) {\n const char **v5;\n int v6;\n unsigned int v7;\n const char *v8;\n long long v9;\n uint64_t *v11;\n v5 = a1;\n v6 = strlen(a3);\n v11 = malloc(8LL * a2);\n *a4 = v11;\n if (a2 <= 0) {\n return 0;\n } else {\n v7 = 0;\n do {\n v8 = *v5;\n if (!strncmp(*v5, a3, v6)) {\n v9 = (int)v7++;\n v11[v9] = v8;\n }\n ++v5;\n } while (v5 != &a1[a2]);\n }\n return v7;\n}" + }, + { + "index": "HumanEval-C-30", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "float* func0(const float* l, int count, int* out_count) {\n float* out = (float*)malloc(count * sizeof(float));\n *out_count = 0;\n for (int i = 0; i < count; i++) {\n if (l[i] > 0) {\n out[(*out_count)++] = l[i];\n }\n }\n return out;\n}", + "test": "#include \n#include \n\n// Helper function to compare two arrays of floats\nint issame(const float* a, int a_count, const float* b, int b_count) {\n if (a_count != b_count) return 0;\n for (int i = 0; i < a_count; i++) {\n if (fabs(a[i] - b[i]) > 1e-4) return 0;\n }\n return 1;\n}\n\nint main() {\n float* result;\n int count;\n\n result = func0((const float[]){-1, -2, 4, 5, 6}, 5, &count);\n assert(issame(result, count, (const float[]){4, 5, 6}, 3));\n free(result);\n\n result = func0((const float[]){5, 3, -5, 2, 3, 3, 9, 0, 123, 1, -10}, 11, &count);\n assert(issame(result, count, (const float[]){5, 3, 2, 3, 3, 9, 123, 1}, 8));\n free(result);\n\n result = func0((const float[]){-1, -2}, 2, &count);\n assert(issame(result, count, (const float[]){}, 0));\n free(result);\n\n result = func0((const float[]){}, 0, &count);\n assert(issame(result, count, (const float[]){}, 0));\n free(result);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov rax, [rbp+var_28]\nmov dword ptr [rax], 0\nmov [rbp+var_C], 0\njmp short loc_124A\nloc_11E8:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\npxor xmm1, xmm1\ncomiss xmm0, xmm1\njbe short loc_1246\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nlea rsi, [rdx+rax]\nmov rax, [rbp+var_28]\nmov eax, [rax]\nlea ecx, [rax+1]\nmov rdx, [rbp+var_28]\nmov [rdx], ecx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmovss xmm0, dword ptr [rsi]\nmovss dword ptr [rax], xmm0\nloc_1246:\nadd [rbp+var_C], 1\nloc_124A:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_11E8\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, _DWORD *a3)\n{\n int v3; // eax\n int i; // [rsp+24h] [rbp-Ch]\n _DWORD *v7; // [rsp+28h] [rbp-8h]\n\n v7 = malloc(4LL * a2);\n *a3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(float *)(4LL * i + a1) > 0.0 )\n {\n v3 = (*a3)++;\n v7[v3] = *(_DWORD *)(4LL * i + a1);\n }\n }\n return v7;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov rax, [rbp+var_28]\nmov dword ptr [rax], 0\nmov [rbp+var_C], 0\njmp short loc_124A\nloc_11E8:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\npxor xmm1, xmm1\ncomiss xmm0, xmm1\njbe short loc_1246\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nlea rsi, [rdx+rax]\nmov rax, [rbp+var_28]\nmov eax, [rax]\nlea ecx, [rax+1]\nmov rdx, [rbp+var_28]\nmov [rdx], ecx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmovss xmm0, dword ptr [rsi]\nmovss dword ptr [rax], xmm0\nloc_1246:\nadd [rbp+var_C], 1\nloc_124A:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_11E8\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(__int64 a1, int a2, _DWORD *a3)\n{\n int v3; // eax\n int i; // [rsp+24h] [rbp-Ch]\n _DWORD *v7; // [rsp+28h] [rbp-8h]\n\n v7 = malloc(4LL * a2);\n *a3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(float *)(4LL * i + a1) > 0.0 )\n {\n v3 = (*a3)++;\n v7[v3] = *(_DWORD *)(4LL * i + a1);\n }\n }\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(long long a1, int a2, uint32_t *a3) {\n int v3;\n int i;\n uint32_t *v7;\n v7 = malloc(4LL * a2);\n *a3 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(float *)(4LL * i + a1) > 0.0) {\n v3 = (*a3)++;\n v7[v3] = *(uint32_t *)(4LL * i + a1);\n }\n }\n return v7;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, uint32_t *a3) {\n int v3;\n int i;\n uint32_t *v7;\n v7 = malloc(4LL * a2);\n *a3 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(float *)(4LL * i + a1) > 0.0) {\n v3 = (*a3)++;\n v7[v3] = *(uint32_t *)(4LL * i + a1);\n }\n }\n return v7;\n}" + }, + { + "index": "HumanEval-C-30", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "float* func0(const float* l, int count, int* out_count) {\n float* out = (float*)malloc(count * sizeof(float));\n *out_count = 0;\n for (int i = 0; i < count; i++) {\n if (l[i] > 0) {\n out[(*out_count)++] = l[i];\n }\n }\n return out;\n}", + "test": "#include \n#include \n\n// Helper function to compare two arrays of floats\nint issame(const float* a, int a_count, const float* b, int b_count) {\n if (a_count != b_count) return 0;\n for (int i = 0; i < a_count; i++) {\n if (fabs(a[i] - b[i]) > 1e-4) return 0;\n }\n return 1;\n}\n\nint main() {\n float* result;\n int count;\n\n result = func0((const float[]){-1, -2, 4, 5, 6}, 5, &count);\n assert(issame(result, count, (const float[]){4, 5, 6}, 3));\n free(result);\n\n result = func0((const float[]){5, 3, -5, 2, 3, 3, 9, 0, 123, 1, -10}, 11, &count);\n assert(issame(result, count, (const float[]){5, 3, 2, 3, 3, 9, 123, 1}, 8));\n free(result);\n\n result = func0((const float[]){-1, -2}, 2, &count);\n assert(issame(result, count, (const float[]){}, 0));\n free(result);\n\n result = func0((const float[]){}, 0, &count);\n assert(issame(result, count, (const float[]){}, 0));\n free(result);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov r13d, esi\nmov rbp, rdx\nmovsxd r12, esi\nshl r12, 2\nmov rdi, r12; size\ncall _malloc\nmov dword ptr [rbp+0], 0\ntest r13d, r13d\njle short loc_1211\nmov rdx, rbx\nlea rsi, [rbx+r12]\npxor xmm1, xmm1\njmp short loc_1206\nloc_11E8:\nmov ecx, [rbp+0]\nlea edi, [rcx+1]\nmov [rbp+0], edi\nmovsxd rcx, ecx\nmovss xmm0, dword ptr [rdx]\nmovss dword ptr [rax+rcx*4], xmm0\nloc_11FD:\nadd rdx, 4\ncmp rdx, rsi\njz short loc_1211\nloc_1206:\nmovss xmm0, dword ptr [rdx]\ncomiss xmm0, xmm1\nja short loc_11E8\njmp short loc_11FD\nloc_1211:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(_DWORD *a1, int a2, _DWORD *a3)\n{\n _DWORD *result; // rax\n _DWORD *v5; // rdx\n int v6; // ecx\n\n result = malloc(4LL * a2);\n *a3 = 0;\n if ( a2 > 0 )\n {\n v5 = a1;\n do\n {\n if ( *(float *)v5 > 0.0 )\n {\n v6 = (*a3)++;\n result[v6] = *v5;\n }\n ++v5;\n }\n while ( v5 != &a1[a2] );\n }\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov r13d, esi\nmov rbp, rdx\nmovsxd r12, esi\nshl r12, 2\nmov rdi, r12; size\ncall _malloc\nmov dword ptr [rbp+0], 0\ntest r13d, r13d\njle short loc_1211\nmov rdx, rbx\nlea rsi, [rbx+r12]\npxor xmm1, xmm1\njmp short loc_1206\nloc_11E8:\nmov ecx, [rbp+0]\nlea edi, [rcx+1]\nmov [rbp+0], edi\nmovsxd rcx, ecx\nmovss xmm0, dword ptr [rdx]\nmovss dword ptr [rax+rcx*4], xmm0\nloc_11FD:\nadd rdx, 4\ncmp rdx, rsi\njz short loc_1211\nloc_1206:\nmovss xmm0, dword ptr [rdx]\ncomiss xmm0, xmm1\nja short loc_11E8\njmp short loc_11FD\nloc_1211:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(_DWORD *a1, int a2, _DWORD *a3)\n{\n _DWORD *result; // rax\n _DWORD *v5; // rdx\n int v6; // ecx\n\n result = malloc(4LL * a2);\n *a3 = 0;\n if ( a2 > 0 )\n {\n v5 = a1;\n do\n {\n if ( *(float *)v5 > 0.0 )\n {\n v6 = (*a3)++;\n result[v6] = *v5;\n }\n ++v5;\n }\n while ( v5 != &a1[a2] );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(uint32_t *a1, int a2, uint32_t *a3) {\n uint32_t *result;\n uint32_t *v5;\n int v6;\n result = malloc(4LL * a2);\n *a3 = 0;\n if (a2 > 0) {\n v5 = a1;\n do {\n if (*(float *)v5 > 0.0) {\n v6 = (*a3)++;\n result[v6] = *v5;\n }\n ++v5;\n } while (v5 != &a1[a2]);\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(uint32_t *a1, int a2, uint32_t *a3) {\n uint32_t *result;\n uint32_t *v5;\n int v6;\n result = malloc(4LL * a2);\n *a3 = 0;\n if (a2 > 0) {\n v5 = a1;\n do {\n if (*(float *)v5 > 0.0) {\n v6 = (*a3)++;\n result[v6] = *v5;\n }\n ++v5;\n } while (v5 != &a1[a2]);\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-30", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "float* func0(const float* l, int count, int* out_count) {\n float* out = (float*)malloc(count * sizeof(float));\n *out_count = 0;\n for (int i = 0; i < count; i++) {\n if (l[i] > 0) {\n out[(*out_count)++] = l[i];\n }\n }\n return out;\n}", + "test": "#include \n#include \n\n// Helper function to compare two arrays of floats\nint issame(const float* a, int a_count, const float* b, int b_count) {\n if (a_count != b_count) return 0;\n for (int i = 0; i < a_count; i++) {\n if (fabs(a[i] - b[i]) > 1e-4) return 0;\n }\n return 1;\n}\n\nint main() {\n float* result;\n int count;\n\n result = func0((const float[]){-1, -2, 4, 5, 6}, 5, &count);\n assert(issame(result, count, (const float[]){4, 5, 6}, 3));\n free(result);\n\n result = func0((const float[]){5, 3, -5, 2, 3, 3, 9, 0, 123, 1, -10}, 11, &count);\n assert(issame(result, count, (const float[]){5, 3, 2, 3, 3, 9, 123, 1}, 8));\n free(result);\n\n result = func0((const float[]){-1, -2}, 2, &count);\n assert(issame(result, count, (const float[]){}, 0));\n free(result);\n\n result = func0((const float[]){}, 0, &count);\n assert(issame(result, count, (const float[]){}, 0));\n free(result);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\nmov r12, rdx\npush rbp\npush rbx\nmov rbx, rdi\nmovsxd rdi, esi\nlea rbp, ds:0[rdi*4]\nmov r13, rdi\nmov rdi, rbp; size\nsub rsp, 8\ncall _malloc\nmov dword ptr [r12], 0\ntest r13d, r13d\njle short loc_14AA\nmov rcx, rbx\nlea rdi, [rbx+rbp]\npxor xmm1, xmm1\nnop word ptr [rax+rax+00h]\nloc_1488:\nmovss xmm0, dword ptr [rcx]\ncomiss xmm0, xmm1\njbe short loc_14A1\nmovsxd rsi, dword ptr [r12]\nlea edx, [rsi+1]\nmovss dword ptr [rax+rsi*4], xmm0\nmov [r12], edx\nloc_14A1:\nadd rcx, 4\ncmp rcx, rdi\njnz short loc_1488\nloc_14AA:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(_DWORD *a1, int a2, int *a3)\n{\n size_t v4; // rbp\n _DWORD *result; // rax\n _DWORD *v6; // rcx\n __int64 v7; // rsi\n\n v4 = a2;\n result = malloc(v4 * 4);\n *a3 = 0;\n if ( a2 > 0 )\n {\n v6 = a1;\n do\n {\n if ( *(float *)v6 > 0.0 )\n {\n v7 = *a3;\n result[v7] = *v6;\n *a3 = v7 + 1;\n }\n ++v6;\n }\n while ( v6 != &a1[v4] );\n }\n return result;\n}", + "ida_strip_asm": "sub_1440:\nendbr64\npush r13\npush r12\nmov r12, rdx\npush rbp\npush rbx\nmov rbx, rdi\nmovsxd rdi, esi\nlea rbp, ds:0[rdi*4]\nmov r13, rdi\nmov rdi, rbp; size\nsub rsp, 8\ncall _malloc\nmov dword ptr [r12], 0\ntest r13d, r13d\njle short loc_14AA\nmov rcx, rbx\nlea rdi, [rbx+rbp]\npxor xmm1, xmm1\nnop word ptr [rax+rax+00h]\nloc_1488:\nmovss xmm0, dword ptr [rcx]\ncomiss xmm0, xmm1\njbe short loc_14A1\nmovsxd rsi, dword ptr [r12]\nlea edx, [rsi+1]\nmovss dword ptr [rax+rsi*4], xmm0\nmov [r12], edx\nloc_14A1:\nadd rcx, 4\ncmp rcx, rdi\njnz short loc_1488\nloc_14AA:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1440(_DWORD *a1, int a2, int *a3)\n{\n size_t v4; // rbp\n _DWORD *result; // rax\n _DWORD *v6; // rcx\n __int64 v7; // rsi\n\n v4 = a2;\n result = malloc(v4 * 4);\n *a3 = 0;\n if ( a2 > 0 )\n {\n v6 = a1;\n do\n {\n if ( *(float *)v6 > 0.0 )\n {\n v7 = *a3;\n result[v7] = *v6;\n *a3 = v7 + 1;\n }\n ++v6;\n }\n while ( v6 != &a1[v4] );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1440(uint32_t *a1, int a2, int *a3) {\n unsigned int v4;\n uint32_t *result;\n uint32_t *v6;\n long long v7;\n v4 = a2;\n result = malloc(v4 * 4);\n *a3 = 0;\n if (a2 > 0) {\n v6 = a1;\n do {\n if (*(float *)v6 > 0.0) {\n v7 = *a3;\n result[v7] = *v6;\n *a3 = v7 + 1;\n }\n ++v6;\n } while (v6 != &a1[v4]);\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(uint32_t *a1, int a2, int *a3) {\n unsigned int v4;\n uint32_t *result;\n uint32_t *v6;\n long long v7;\n v4 = a2;\n result = malloc(v4 * 4);\n *a3 = 0;\n if (a2 > 0) {\n v6 = a1;\n do {\n if (*(float *)v6 > 0.0) {\n v7 = *a3;\n result[v7] = *v6;\n *a3 = v7 + 1;\n }\n ++v6;\n } while (v6 != &a1[v4]);\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-30", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "float* func0(const float* l, int count, int* out_count) {\n float* out = (float*)malloc(count * sizeof(float));\n *out_count = 0;\n for (int i = 0; i < count; i++) {\n if (l[i] > 0) {\n out[(*out_count)++] = l[i];\n }\n }\n return out;\n}", + "test": "#include \n#include \n\n// Helper function to compare two arrays of floats\nint issame(const float* a, int a_count, const float* b, int b_count) {\n if (a_count != b_count) return 0;\n for (int i = 0; i < a_count; i++) {\n if (fabs(a[i] - b[i]) > 1e-4) return 0;\n }\n return 1;\n}\n\nint main() {\n float* result;\n int count;\n\n result = func0((const float[]){-1, -2, 4, 5, 6}, 5, &count);\n assert(issame(result, count, (const float[]){4, 5, 6}, 3));\n free(result);\n\n result = func0((const float[]){5, 3, -5, 2, 3, 3, 9, 0, 123, 1, -10}, 11, &count);\n assert(issame(result, count, (const float[]){5, 3, 2, 3, 3, 9, 123, 1}, 8));\n free(result);\n\n result = func0((const float[]){-1, -2}, 2, &count);\n assert(issame(result, count, (const float[]){}, 0));\n free(result);\n\n result = func0((const float[]){}, 0, &count);\n assert(issame(result, count, (const float[]){}, 0));\n free(result);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\nmov r12, rdx\npush rbp\npush rbx\nmov rbx, rdi\nmovsxd rdi, esi\nlea rbp, ds:0[rdi*4]\nmov r13, rdi\nmov rdi, rbp; size\nsub rsp, 8\ncall _malloc\nmov dword ptr [r12], 0\ntest r13d, r13d\njle short loc_14AA\nmov rcx, rbx\nlea rdi, [rbx+rbp]\npxor xmm1, xmm1\nnop word ptr [rax+rax+00h]\nloc_1488:\nmovss xmm0, dword ptr [rcx]\ncomiss xmm0, xmm1\njbe short loc_14A1\nmovsxd rsi, dword ptr [r12]\nlea edx, [rsi+1]\nmovss dword ptr [rax+rsi*4], xmm0\nmov [r12], edx\nloc_14A1:\nadd rcx, 4\ncmp rcx, rdi\njnz short loc_1488\nloc_14AA:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(_DWORD *a1, int a2, int *a3)\n{\n size_t v4; // rbp\n _DWORD *result; // rax\n _DWORD *v6; // rcx\n __int64 v7; // rsi\n\n v4 = a2;\n result = malloc(v4 * 4);\n *a3 = 0;\n if ( a2 > 0 )\n {\n v6 = a1;\n do\n {\n if ( *(float *)v6 > 0.0 )\n {\n v7 = *a3;\n result[v7] = *v6;\n *a3 = v7 + 1;\n }\n ++v6;\n }\n while ( v6 != &a1[v4] );\n }\n return result;\n}", + "ida_strip_asm": "sub_1440:\nendbr64\npush r13\npush r12\nmov r12, rdx\npush rbp\npush rbx\nmov rbx, rdi\nmovsxd rdi, esi\nlea rbp, ds:0[rdi*4]\nmov r13, rdi\nmov rdi, rbp; size\nsub rsp, 8\ncall _malloc\nmov dword ptr [r12], 0\ntest r13d, r13d\njle short loc_14AA\nmov rcx, rbx\nlea rdi, [rbx+rbp]\npxor xmm1, xmm1\nnop word ptr [rax+rax+00h]\nloc_1488:\nmovss xmm0, dword ptr [rcx]\ncomiss xmm0, xmm1\njbe short loc_14A1\nmovsxd rsi, dword ptr [r12]\nlea edx, [rsi+1]\nmovss dword ptr [rax+rsi*4], xmm0\nmov [r12], edx\nloc_14A1:\nadd rcx, 4\ncmp rcx, rdi\njnz short loc_1488\nloc_14AA:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1440(_DWORD *a1, int a2, int *a3)\n{\n size_t v4; // rbp\n _DWORD *result; // rax\n _DWORD *v6; // rcx\n __int64 v7; // rsi\n\n v4 = a2;\n result = malloc(v4 * 4);\n *a3 = 0;\n if ( a2 > 0 )\n {\n v6 = a1;\n do\n {\n if ( *(float *)v6 > 0.0 )\n {\n v7 = *a3;\n result[v7] = *v6;\n *a3 = v7 + 1;\n }\n ++v6;\n }\n while ( v6 != &a1[v4] );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1440(uint32_t *a1, int a2, int *a3) {\n unsigned int v4;\n uint32_t *result;\n uint32_t *v6;\n long long v7;\n v4 = a2;\n result = malloc(v4 * 4);\n *a3 = 0;\n if (a2 > 0) {\n v6 = a1;\n do {\n if (*(float *)v6 > 0.0) {\n v7 = *a3;\n result[v7] = *v6;\n *a3 = v7 + 1;\n }\n ++v6;\n } while (v6 != &a1[v4]);\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(uint32_t *a1, int a2, int *a3) {\n unsigned int v4;\n uint32_t *result;\n uint32_t *v6;\n long long v7;\n v4 = a2;\n result = malloc(v4 * 4);\n *a3 = 0;\n if (a2 > 0) {\n v6 = a1;\n do {\n if (*(float *)v6 > 0.0) {\n v7 = *a3;\n result[v7] = *v6;\n *a3 = v7 + 1;\n }\n ++v6;\n } while (v6 != &a1[v4]);\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-31", + "func_name": "func0", + "func_dep": "#include \n", + "func": "bool func0(long long n) {\n if (n < 2) return false;\n for (long long i = 2; i * i <= n; i++)\n if (n % i == 0) return false;\n return true;\n}", + "test": "#include \n\nint main() {\n assert(func0(6) == false);\n assert(func0(101) == true);\n assert(func0(11) == true);\n assert(func0(13441) == true);\n assert(func0(61) == true);\n assert(func0(4) == false);\n assert(func0(1) == false);\n assert(func0(5) == true);\n assert(func0(11) == true);\n assert(func0(17) == true);\n assert(func0(5 * 17) == false);\n assert(func0(11 * 7) == false);\n assert(func0(13441 * 19) == false);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\ncmp [rbp+var_18], 1\njg short loc_1163\nmov eax, 0\njmp short loc_119E\nloc_1163:\nmov [rbp+var_8], 2\njmp short loc_118B\nloc_116D:\nmov rax, [rbp+var_18]\ncqo\nidiv [rbp+var_8]\nmov rax, rdx\ntest rax, rax\njnz short loc_1186\nmov eax, 0\njmp short loc_119E\nloc_1186:\nadd [rbp+var_8], 1\nloc_118B:\nmov rax, [rbp+var_8]\nimul rax, rax\ncmp [rbp+var_18], rax\njge short loc_116D\nmov eax, 1\nloc_119E:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1)\n{\n __int64 i; // [rsp+10h] [rbp-8h]\n\n if ( a1 <= 1 )\n return 0LL;\n for ( i = 2LL; a1 >= i * i; ++i )\n {\n if ( !(a1 % i) )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\ncmp [rbp+var_18], 1\njg short loc_1163\nmov eax, 0\njmp short loc_119E\nloc_1163:\nmov [rbp+var_8], 2\njmp short loc_118B\nloc_116D:\nmov rax, [rbp+var_18]\ncqo\nidiv [rbp+var_8]\nmov rax, rdx\ntest rax, rax\njnz short loc_1186\nmov eax, 0\njmp short loc_119E\nloc_1186:\nadd [rbp+var_8], 1\nloc_118B:\nmov rax, [rbp+var_8]\nimul rax, rax\ncmp [rbp+var_18], rax\njge short loc_116D\nmov eax, 1\nloc_119E:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(__int64 a1)\n{\n __int64 i; // [rsp+10h] [rbp-8h]\n\n if ( a1 <= 1 )\n return 0LL;\n for ( i = 2LL; a1 >= i * i; ++i )\n {\n if ( !(a1 % i) )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(long long a1) {\n long long i;\n if (a1 <= 1) return 0LL;\n for (i = 2LL; a1 >= i * i; ++i) {\n if (!(a1 % i)) return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1) {\n long long i;\n if (a1 <= 1) return 0LL;\n for (i = 2LL; a1 >= i * i; ++i) {\n if (!(a1 % i)) return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": "HumanEval-C-31", + "func_name": "func0", + "func_dep": "#include \n", + "func": "bool func0(long long n) {\n if (n < 2) return false;\n for (long long i = 2; i * i <= n; i++)\n if (n % i == 0) return false;\n return true;\n}", + "test": "#include \n\nint main() {\n assert(func0(6) == false);\n assert(func0(101) == true);\n assert(func0(11) == true);\n assert(func0(13441) == true);\n assert(func0(61) == true);\n assert(func0(4) == false);\n assert(func0(1) == false);\n assert(func0(5) == true);\n assert(func0(11) == true);\n assert(func0(17) == true);\n assert(func0(5 * 17) == false);\n assert(func0(11 * 7) == false);\n assert(func0(13441 * 19) == false);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmov eax, 0\ncmp rdi, 1\njle short locret_118B\ncmp rdi, 3\njle short loc_1192\ntest dil, 1\njz short loc_1198\nmov ecx, 2\nloc_1169:\nadd rcx, 1\nmov rax, rcx\nimul rax, rcx\ncmp rax, rdi\njg short loc_118C\nmov rax, rdi\ncqo\nidiv rcx\ntest rdx, rdx\njnz short loc_1169\nmov eax, 0\nlocret_118B:\nretn\nloc_118C:\nmov eax, 1\nretn\nloc_1192:\nmov eax, 1\nretn\nloc_1198:\nmov eax, 0\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1)\n{\n __int64 result; // rax\n __int64 v2; // rcx\n\n result = 0LL;\n if ( a1 > 1 )\n {\n if ( a1 <= 3 )\n {\n return 1LL;\n }\n else if ( (a1 & 1) != 0 )\n {\n v2 = 2LL;\n while ( 1 )\n {\n ++v2;\n if ( v2 * v2 > a1 )\n break;\n if ( !(a1 % v2) )\n return 0LL;\n }\n return 1LL;\n }\n else\n {\n return 0LL;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmov eax, 0\ncmp rdi, 1\njle short locret_118B\ncmp rdi, 3\njle short loc_1192\ntest dil, 1\njz short loc_1198\nmov ecx, 2\nloc_1169:\nadd rcx, 1\nmov rax, rcx\nimul rax, rcx\ncmp rax, rdi\njg short loc_118C\nmov rax, rdi\ncqo\nidiv rcx\ntest rdx, rdx\njnz short loc_1169\nmov eax, 0\nlocret_118B:\nretn\nloc_118C:\nmov eax, 1\nretn\nloc_1192:\nmov eax, 1\nretn\nloc_1198:\nmov eax, 0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(__int64 a1)\n{\n __int64 result; // rax\n __int64 v2; // rcx\n\n result = 0LL;\n if ( a1 > 1 )\n {\n if ( a1 <= 3 )\n {\n return 1LL;\n }\n else if ( (a1 & 1) != 0 )\n {\n v2 = 2LL;\n while ( 1 )\n {\n ++v2;\n if ( v2 * v2 > a1 )\n break;\n if ( !(a1 % v2) )\n return 0LL;\n }\n return 1LL;\n }\n else\n {\n return 0LL;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(long long a1) {\n long long result;\n long long v2;\n result = 0LL;\n if (a1 > 1) {\n if (a1 <= 3) {\n return 1LL;\n } else if ((a1 & 1) != 0) {\n v2 = 2LL;\n while (1) {\n ++v2;\n if (v2 * v2 > a1) break;\n if (!(a1 % v2)) return 0LL;\n }\n return 1LL;\n } else {\n return 0LL;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1) {\n long long result;\n long long v2;\n result = 0LL;\n if (a1 > 1) {\n if (a1 <= 3) {\n return 1LL;\n } else if ((a1 & 1) != 0) {\n v2 = 2LL;\n while (1) {\n ++v2;\n if (v2 * v2 > a1) break;\n if (!(a1 % v2)) return 0LL;\n }\n return 1LL;\n } else {\n return 0LL;\n }\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-31", + "func_name": "func0", + "func_dep": "#include \n", + "func": "bool func0(long long n) {\n if (n < 2) return false;\n for (long long i = 2; i * i <= n; i++)\n if (n % i == 0) return false;\n return true;\n}", + "test": "#include \n\nint main() {\n assert(func0(6) == false);\n assert(func0(101) == true);\n assert(func0(11) == true);\n assert(func0(13441) == true);\n assert(func0(61) == true);\n assert(func0(4) == false);\n assert(func0(1) == false);\n assert(func0(5) == true);\n assert(func0(11) == true);\n assert(func0(17) == true);\n assert(func0(5 * 17) == false);\n assert(func0(11 * 7) == false);\n assert(func0(13441 * 19) == false);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0_part_0:\ncmp rdi, 3\njle short loc_13B5\ntest dil, 1\njz short loc_13C0\nmov ecx, 2\njmp short loc_13A5\nloc_1398:\nmov rax, rdi\ncqo\nidiv rcx\ntest rdx, rdx\njz short loc_13C0\nloc_13A5:\nadd rcx, 1\nmov rax, rcx\nimul rax, rcx\ncmp rdi, rax\njge short loc_1398\nloc_13B5:\nmov eax, 1\nretn\nloc_13C0:\nxor eax, eax\nretn", + "ida_pseudo": "__int64 __fastcall func0_part_0(__int64 a1)\n{\n __int64 v1; // rcx\n\n if ( a1 <= 3 )\n return 1LL;\n if ( (a1 & 1) != 0 )\n {\n v1 = 2LL;\n while ( 1 )\n {\n ++v1;\n if ( a1 < v1 * v1 )\n break;\n if ( !(a1 % v1) )\n return 0LL;\n }\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1380:\ncmp rdi, 3\njle short loc_13B5\ntest dil, 1\njz short loc_13C0\nmov ecx, 2\njmp short loc_13A5\nloc_1398:\nmov rax, rdi\ncqo\nidiv rcx\ntest rdx, rdx\njz short loc_13C0\nloc_13A5:\nadd rcx, 1\nmov rax, rcx\nimul rax, rcx\ncmp rdi, rax\njge short loc_1398\nloc_13B5:\nmov eax, 1\nretn\nloc_13C0:\nxor eax, eax\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1380(__int64 a1)\n{\n __int64 v1; // rcx\n\n if ( a1 <= 3 )\n return 1LL;\n if ( (a1 & 1) != 0 )\n {\n v1 = 2LL;\n while ( 1 )\n {\n ++v1;\n if ( a1 < v1 * v1 )\n break;\n if ( !(a1 % v1) )\n return 0LL;\n }\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1380(long long a1) {\n long long v1;\n if (a1 <= 3) return 1LL;\n if ((a1 & 1) != 0) {\n v1 = 2LL;\n while (1) {\n ++v1;\n if (a1 < v1 * v1) break;\n if (!(a1 % v1)) return 0LL;\n }\n return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0_part_0(long long a1) {\n long long v1;\n if (a1 <= 3) return 1LL;\n if ((a1 & 1) != 0) {\n v1 = 2LL;\n while (1) {\n ++v1;\n if (a1 < v1 * v1) break;\n if (!(a1 % v1)) return 0LL;\n }\n return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": "HumanEval-C-31", + "func_name": "func0", + "func_dep": "#include \n", + "func": "bool func0(long long n) {\n if (n < 2) return false;\n for (long long i = 2; i * i <= n; i++)\n if (n % i == 0) return false;\n return true;\n}", + "test": "#include \n\nint main() {\n assert(func0(6) == false);\n assert(func0(101) == true);\n assert(func0(11) == true);\n assert(func0(13441) == true);\n assert(func0(61) == true);\n assert(func0(4) == false);\n assert(func0(1) == false);\n assert(func0(5) == true);\n assert(func0(11) == true);\n assert(func0(17) == true);\n assert(func0(5 * 17) == false);\n assert(func0(11 * 7) == false);\n assert(func0(13441 * 19) == false);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0_part_0:\ncmp rdi, 3\njle short loc_13B5\ntest dil, 1\njz short loc_13C0\nmov ecx, 2\njmp short loc_13A5\nloc_1398:\nmov rax, rdi\ncqo\nidiv rcx\ntest rdx, rdx\njz short loc_13C0\nloc_13A5:\nadd rcx, 1\nmov rax, rcx\nimul rax, rcx\ncmp rdi, rax\njge short loc_1398\nloc_13B5:\nmov eax, 1\nretn\nloc_13C0:\nxor eax, eax\nretn", + "ida_pseudo": "__int64 __fastcall func0_part_0(__int64 a1)\n{\n __int64 v1; // rcx\n\n if ( a1 <= 3 )\n return 1LL;\n if ( (a1 & 1) != 0 )\n {\n v1 = 2LL;\n while ( 1 )\n {\n ++v1;\n if ( a1 < v1 * v1 )\n break;\n if ( !(a1 % v1) )\n return 0LL;\n }\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1380:\ncmp rdi, 3\njle short loc_13B5\ntest dil, 1\njz short loc_13C0\nmov ecx, 2\njmp short loc_13A5\nloc_1398:\nmov rax, rdi\ncqo\nidiv rcx\ntest rdx, rdx\njz short loc_13C0\nloc_13A5:\nadd rcx, 1\nmov rax, rcx\nimul rax, rcx\ncmp rdi, rax\njge short loc_1398\nloc_13B5:\nmov eax, 1\nretn\nloc_13C0:\nxor eax, eax\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1380(__int64 a1)\n{\n __int64 v1; // rcx\n\n if ( a1 <= 3 )\n return 1LL;\n if ( (a1 & 1) != 0 )\n {\n v1 = 2LL;\n while ( 1 )\n {\n ++v1;\n if ( a1 < v1 * v1 )\n break;\n if ( !(a1 % v1) )\n return 0LL;\n }\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1380(long long a1) {\n long long v1;\n if (a1 <= 3) return 1LL;\n if ((a1 & 1) != 0) {\n v1 = 2LL;\n while (1) {\n ++v1;\n if (a1 < v1 * v1) break;\n if (!(a1 % v1)) return 0LL;\n }\n return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0_part_0(long long a1) {\n long long v1;\n if (a1 <= 3) return 1LL;\n if ((a1 & 1) != 0) {\n v1 = 2LL;\n while (1) {\n ++v1;\n if (a1 < v1 * v1) break;\n if (!(a1 % v1)) return 0LL;\n }\n return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": "HumanEval-C-32", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "double func0(const double *xs, int size) {\n double ans = 0.0;\n double value, driv, x_pow;\n int i;\n value = xs[0];\n for (i = 1; i < size; i++) {\n x_pow = 1.0;\n for (int j = 0; j < i; j++) {\n x_pow *= ans;\n }\n value += xs[i] * x_pow;\n }\n while (fabs(value) > 1e-6) {\n driv = 0.0;\n for (i = 1; i < size; i++) {\n x_pow = 1.0;\n for (int j = 1; j < i; j++) {\n x_pow *= ans;\n }\n driv += i * xs[i] * x_pow;\n }\n ans = ans - value / driv;\n value = xs[0];\n for (i = 1; i < size; i++) {\n x_pow = 1.0;\n for (int j = 0; j < i; j++) {\n x_pow *= ans;\n }\n value += xs[i] * x_pow;\n }\n }\n return ans;\n}", + "test": "#include \n#include \n#include \n#include \n\n\ndouble evaluate_polynomial(const double *coeffs, int size, double x) {\n double result = 0.0;\n double term = 1.0; \n for (int i = 0; i < size; i++) {\n if (i > 0) {\n term *= x; \n }\n result += coeffs[i] * term;\n }\n return result;\n}\n\nint main() {\n double solution;\n int ncoeff;\n \n for (int i = 0; i < 100; i++) {\n ncoeff = 2 * (1 + rand() % 4);\n double coeffs[ncoeff];\n for (int j = 0; j < ncoeff; j++) {\n double coeff = -10 + rand() % 21;\n if (coeff == 0) coeff = 1;\n coeffs[j] = coeff;\n }\n \n solution = func0(coeffs, ncoeff);\n\n assert(fabs(evaluate_polynomial(coeffs, ncoeff, solution)) < 1e-3);\n }\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\npxor xmm0, xmm0\nmovsd [rbp+var_20], xmm0\nmov rax, [rbp+var_38]\nmovsd xmm0, qword ptr [rax]\nmovsd [rbp+var_18], xmm0\nmov [rbp+var_30], 1\njmp short loc_1217\nloc_11B7:\nmovsd xmm0, cs:qword_2070\nmovsd [rbp+var_8], xmm0\nmov [rbp+var_2C], 0\njmp short loc_11E0\nloc_11CD:\nmovsd xmm0, [rbp+var_8]\nmulsd xmm0, [rbp+var_20]\nmovsd [rbp+var_8], xmm0\nadd [rbp+var_2C], 1\nloc_11E0:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_30]\njl short loc_11CD\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmovsd xmm0, qword ptr [rax]\nmulsd xmm0, [rbp+var_8]\nmovsd xmm1, [rbp+var_18]\naddsd xmm0, xmm1\nmovsd [rbp+var_18], xmm0\nadd [rbp+var_30], 1\nloc_1217:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_3C]\njl short loc_11B7\njmp loc_1345\nloc_1224:\npxor xmm0, xmm0\nmovsd [rbp+var_10], xmm0\nmov [rbp+var_30], 1\njmp short loc_12A3\nloc_1236:\nmovsd xmm0, cs:qword_2070\nmovsd [rbp+var_8], xmm0\nmov [rbp+var_28], 1\njmp short loc_125F\nloc_124C:\nmovsd xmm0, [rbp+var_8]\nmulsd xmm0, [rbp+var_20]\nmovsd [rbp+var_8], xmm0\nadd [rbp+var_28], 1\nloc_125F:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_30]\njl short loc_124C\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_30]\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmovsd xmm0, qword ptr [rax]\nmulsd xmm0, xmm1\nmulsd xmm0, [rbp+var_8]\nmovsd xmm1, [rbp+var_10]\naddsd xmm0, xmm1\nmovsd [rbp+var_10], xmm0\nadd [rbp+var_30], 1\nloc_12A3:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_3C]\njl short loc_1236\nmovsd xmm0, [rbp+var_18]\nmovapd xmm1, xmm0\ndivsd xmm1, [rbp+var_10]\nmovsd xmm0, [rbp+var_20]\nsubsd xmm0, xmm1\nmovsd [rbp+var_20], xmm0\nmov rax, [rbp+var_38]\nmovsd xmm0, qword ptr [rax]\nmovsd [rbp+var_18], xmm0\nmov [rbp+var_30], 1\njmp short loc_133D\nloc_12DD:\nmovsd xmm0, cs:qword_2070\nmovsd [rbp+var_8], xmm0\nmov [rbp+var_24], 0\njmp short loc_1306\nloc_12F3:\nmovsd xmm0, [rbp+var_8]\nmulsd xmm0, [rbp+var_20]\nmovsd [rbp+var_8], xmm0\nadd [rbp+var_24], 1\nloc_1306:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_30]\njl short loc_12F3\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmovsd xmm0, qword ptr [rax]\nmulsd xmm0, [rbp+var_8]\nmovsd xmm1, [rbp+var_18]\naddsd xmm0, xmm1\nmovsd [rbp+var_18], xmm0\nadd [rbp+var_30], 1\nloc_133D:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_3C]\njl short loc_12DD\nloc_1345:\nmovsd xmm0, [rbp+var_18]\nmovq xmm1, cs:qword_2080\nandpd xmm0, xmm1\ncomisd xmm0, cs:qword_2090\nja loc_1224\nmovsd xmm0, [rbp+var_20]\npop rbp\nretn", + "ida_pseudo": "double __fastcall func0(double *a1, int a2)\n{\n int i; // [rsp+Ch] [rbp-30h]\n int k; // [rsp+Ch] [rbp-30h]\n int n; // [rsp+Ch] [rbp-30h]\n int j; // [rsp+10h] [rbp-2Ch]\n int m; // [rsp+14h] [rbp-28h]\n int ii; // [rsp+18h] [rbp-24h]\n double v9; // [rsp+1Ch] [rbp-20h]\n double v10; // [rsp+24h] [rbp-18h]\n double v11; // [rsp+2Ch] [rbp-10h]\n double v12; // [rsp+34h] [rbp-8h]\n double v13; // [rsp+34h] [rbp-8h]\n double v14; // [rsp+34h] [rbp-8h]\n\n v9 = 0.0;\n v10 = *a1;\n for ( i = 1; i < a2; ++i )\n {\n v12 = 1.0;\n for ( j = 0; j < i; ++j )\n v12 = v12 * 0.0;\n v10 = a1[i] * v12 + v10;\n }\n while ( fabs(v10) > 0.000001 )\n {\n v11 = 0.0;\n for ( k = 1; k < a2; ++k )\n {\n v13 = 1.0;\n for ( m = 1; m < k; ++m )\n v13 = v13 * v9;\n v11 = a1[k] * (double)k * v13 + v11;\n }\n v9 = v9 - v10 / v11;\n v10 = *a1;\n for ( n = 1; n < a2; ++n )\n {\n v14 = 1.0;\n for ( ii = 0; ii < n; ++ii )\n v14 = v14 * v9;\n v10 = a1[n] * v14 + v10;\n }\n }\n return v9;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\npxor xmm0, xmm0\nmovsd [rbp+var_20], xmm0\nmov rax, [rbp+var_38]\nmovsd xmm0, qword ptr [rax]\nmovsd [rbp+var_18], xmm0\nmov [rbp+var_30], 1\njmp short loc_1217\nloc_11B7:\nmovsd xmm0, cs:qword_2070\nmovsd [rbp+var_8], xmm0\nmov [rbp+var_2C], 0\njmp short loc_11E0\nloc_11CD:\nmovsd xmm0, [rbp+var_8]\nmulsd xmm0, [rbp+var_20]\nmovsd [rbp+var_8], xmm0\nadd [rbp+var_2C], 1\nloc_11E0:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_30]\njl short loc_11CD\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmovsd xmm0, qword ptr [rax]\nmulsd xmm0, [rbp+var_8]\nmovsd xmm1, [rbp+var_18]\naddsd xmm0, xmm1\nmovsd [rbp+var_18], xmm0\nadd [rbp+var_30], 1\nloc_1217:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_3C]\njl short loc_11B7\njmp loc_1345\nloc_1224:\npxor xmm0, xmm0\nmovsd [rbp+var_10], xmm0\nmov [rbp+var_30], 1\njmp short loc_12A3\nloc_1236:\nmovsd xmm0, cs:qword_2070\nmovsd [rbp+var_8], xmm0\nmov [rbp+var_28], 1\njmp short loc_125F\nloc_124C:\nmovsd xmm0, [rbp+var_8]\nmulsd xmm0, [rbp+var_20]\nmovsd [rbp+var_8], xmm0\nadd [rbp+var_28], 1\nloc_125F:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_30]\njl short loc_124C\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_30]\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmovsd xmm0, qword ptr [rax]\nmulsd xmm0, xmm1\nmulsd xmm0, [rbp+var_8]\nmovsd xmm1, [rbp+var_10]\naddsd xmm0, xmm1\nmovsd [rbp+var_10], xmm0\nadd [rbp+var_30], 1\nloc_12A3:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_3C]\njl short loc_1236\nmovsd xmm0, [rbp+var_18]\nmovapd xmm1, xmm0\ndivsd xmm1, [rbp+var_10]\nmovsd xmm0, [rbp+var_20]\nsubsd xmm0, xmm1\nmovsd [rbp+var_20], xmm0\nmov rax, [rbp+var_38]\nmovsd xmm0, qword ptr [rax]\nmovsd [rbp+var_18], xmm0\nmov [rbp+var_30], 1\njmp short loc_133D\nloc_12DD:\nmovsd xmm0, cs:qword_2070\nmovsd [rbp+var_8], xmm0\nmov [rbp+var_24], 0\njmp short loc_1306\nloc_12F3:\nmovsd xmm0, [rbp+var_8]\nmulsd xmm0, [rbp+var_20]\nmovsd [rbp+var_8], xmm0\nadd [rbp+var_24], 1\nloc_1306:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_30]\njl short loc_12F3\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmovsd xmm0, qword ptr [rax]\nmulsd xmm0, [rbp+var_8]\nmovsd xmm1, [rbp+var_18]\naddsd xmm0, xmm1\nmovsd [rbp+var_18], xmm0\nadd [rbp+var_30], 1\nloc_133D:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_3C]\njl short loc_12DD\nloc_1345:\nmovsd xmm0, [rbp+var_18]\nmovq xmm1, cs:qword_2080\nandpd xmm0, xmm1\ncomisd xmm0, cs:qword_2090\nja loc_1224\nmovsd xmm0, [rbp+var_20]\npop rbp\nretn", + "ida_strip_pseudo": "double __fastcall sub_1189(double *a1, int a2)\n{\n int i; // [rsp+Ch] [rbp-30h]\n int k; // [rsp+Ch] [rbp-30h]\n int n; // [rsp+Ch] [rbp-30h]\n int j; // [rsp+10h] [rbp-2Ch]\n int m; // [rsp+14h] [rbp-28h]\n int ii; // [rsp+18h] [rbp-24h]\n double v9; // [rsp+1Ch] [rbp-20h]\n double v10; // [rsp+24h] [rbp-18h]\n double v11; // [rsp+2Ch] [rbp-10h]\n double v12; // [rsp+34h] [rbp-8h]\n double v13; // [rsp+34h] [rbp-8h]\n double v14; // [rsp+34h] [rbp-8h]\n\n v9 = 0.0;\n v10 = *a1;\n for ( i = 1; i < a2; ++i )\n {\n v12 = 1.0;\n for ( j = 0; j < i; ++j )\n v12 = v12 * 0.0;\n v10 = a1[i] * v12 + v10;\n }\n while ( fabs(v10) > 0.000001 )\n {\n v11 = 0.0;\n for ( k = 1; k < a2; ++k )\n {\n v13 = 1.0;\n for ( m = 1; m < k; ++m )\n v13 = v13 * v9;\n v11 = a1[k] * (double)k * v13 + v11;\n }\n v9 = v9 - v10 / v11;\n v10 = *a1;\n for ( n = 1; n < a2; ++n )\n {\n v14 = 1.0;\n for ( ii = 0; ii < n; ++ii )\n v14 = v14 * v9;\n v10 = a1[n] * v14 + v10;\n }\n }\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1189(double *a1, int a2) {\n int i;\n int k;\n int n;\n int j;\n int m;\n int ii;\n double v9;\n double v10;\n double v11;\n double v12;\n double v13;\n double v14;\n v9 = 0.0;\n v10 = *a1;\n for (i = 1; i < a2; ++i) {\n v12 = 1.0;\n for (j = 0; j < i; ++j) v12 = v12 * 0.0;\n v10 = a1[i] * v12 + v10;\n }\n while (fabs(v10) > 0.000001) {\n v11 = 0.0;\n for (k = 1; k < a2; ++k) {\n v13 = 1.0;\n for (m = 1; m < k; ++m) v13 = v13 * v9;\n v11 = a1[k] * (double)k * v13 + v11;\n }\n v9 = v9 - v10 / v11;\n v10 = *a1;\n for (n = 1; n < a2; ++n) {\n v14 = 1.0;\n for (ii = 0; ii < n; ++ii) v14 = v14 * v9;\n v10 = a1[n] * v14 + v10;\n }\n }\n return v9;\n}", + "ida_pseudo_norm": "double func0(double *a1, int a2) {\n int i;\n int k;\n int n;\n int j;\n int m;\n int ii;\n double v9;\n double v10;\n double v11;\n double v12;\n double v13;\n double v14;\n v9 = 0.0;\n v10 = *a1;\n for (i = 1; i < a2; ++i) {\n v12 = 1.0;\n for (j = 0; j < i; ++j) v12 = v12 * 0.0;\n v10 = a1[i] * v12 + v10;\n }\n while (fabs(v10) > 0.000001) {\n v11 = 0.0;\n for (k = 1; k < a2; ++k) {\n v13 = 1.0;\n for (m = 1; m < k; ++m) v13 = v13 * v9;\n v11 = a1[k] * (double)k * v13 + v11;\n }\n v9 = v9 - v10 / v11;\n v10 = *a1;\n for (n = 1; n < a2; ++n) {\n v14 = 1.0;\n for (ii = 0; ii < n; ++ii) v14 = v14 * v9;\n v10 = a1[n] * v14 + v10;\n }\n }\n return v9;\n}" + }, + { + "index": "HumanEval-C-32", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "double func0(const double *xs, int size) {\n double ans = 0.0;\n double value, driv, x_pow;\n int i;\n value = xs[0];\n for (i = 1; i < size; i++) {\n x_pow = 1.0;\n for (int j = 0; j < i; j++) {\n x_pow *= ans;\n }\n value += xs[i] * x_pow;\n }\n while (fabs(value) > 1e-6) {\n driv = 0.0;\n for (i = 1; i < size; i++) {\n x_pow = 1.0;\n for (int j = 1; j < i; j++) {\n x_pow *= ans;\n }\n driv += i * xs[i] * x_pow;\n }\n ans = ans - value / driv;\n value = xs[0];\n for (i = 1; i < size; i++) {\n x_pow = 1.0;\n for (int j = 0; j < i; j++) {\n x_pow *= ans;\n }\n value += xs[i] * x_pow;\n }\n }\n return ans;\n}", + "test": "#include \n#include \n#include \n#include \n\n\ndouble evaluate_polynomial(const double *coeffs, int size, double x) {\n double result = 0.0;\n double term = 1.0; \n for (int i = 0; i < size; i++) {\n if (i > 0) {\n term *= x; \n }\n result += coeffs[i] * term;\n }\n return result;\n}\n\nint main() {\n double solution;\n int ncoeff;\n \n for (int i = 0; i < 100; i++) {\n ncoeff = 2 * (1 + rand() % 4);\n double coeffs[ncoeff];\n for (int j = 0; j < ncoeff; j++) {\n double coeff = -10 + rand() % 21;\n if (coeff == 0) coeff = 1;\n coeffs[j] = coeff;\n }\n \n solution = func0(coeffs, ncoeff);\n\n assert(fabs(evaluate_polynomial(coeffs, ncoeff, solution)) < 1e-3);\n }\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmov r9d, esi\nmovsd xmm5, qword ptr [rdi]\ncmp esi, 1\njle short loc_1213\nmov esi, esi\nmovapd xmm3, xmm5\nmov ecx, 1\npxor xmm1, xmm1\nloc_11A8:\nmov edx, ecx\nmov eax, 0\nmovsd xmm0, cs:qword_2068\ntest ecx, ecx\njle loc_12E1\nloc_11BF:\nmulsd xmm0, xmm1\nadd eax, 1\ncmp eax, edx\njnz short loc_11BF\nmulsd xmm0, qword ptr [rdi+rcx*8]\naddsd xmm3, xmm0\nadd rcx, 1\ncmp rcx, rsi\njnz short loc_11A8\nloc_11DC:\nmovapd xmm0, xmm3\nandpd xmm0, cs:xmmword_2080\npxor xmm1, xmm1\ncomisd xmm0, cs:qword_2070\njbe short loc_1219\nmovapd xmm8, xmm1\nmov r8d, r9d\nmovq xmm7, qword ptr cs:xmmword_2080\nmovsd xmm6, cs:qword_2070\njmp loc_12B6\nloc_1213:\nmovapd xmm3, xmm5\njmp short loc_11DC\nloc_1219:\npxor xmm1, xmm1\nloc_121D:\nmovapd xmm0, xmm1\nretn\nloc_1222:\nmulsd xmm0, xmm1\nadd eax, 1\ncmp eax, edx\njnz short loc_1222\nloc_122D:\npxor xmm2, xmm2\ncvtsi2sd xmm2, esi\nmulsd xmm2, qword ptr [rdi+rcx*8]\nmulsd xmm0, xmm2\naddsd xmm4, xmm0\nadd rcx, 1\ncmp r8, rcx\njz short loc_1263\nloc_124B:\nmov esi, ecx\nmov edx, ecx\nmov eax, 1\nmovsd xmm0, cs:qword_2068\ncmp ecx, 1\njg short loc_1222\njmp short loc_122D\nloc_1263:\ndivsd xmm3, xmm4\nsubsd xmm1, xmm3\nmovapd xmm3, xmm5\nmov ecx, 1\nloc_1274:\nmov edx, ecx\nmov eax, 0\nmovsd xmm0, cs:qword_2068\ntest ecx, ecx\njle short loc_12D6\nloc_1287:\nmulsd xmm0, xmm1\nadd eax, 1\ncmp edx, eax\njnz short loc_1287\nmulsd xmm0, qword ptr [rdi+rcx*8]\naddsd xmm3, xmm0\nadd rcx, 1\ncmp rcx, r8\njnz short loc_1274\nloc_12A4:\nmovapd xmm0, xmm3\nandpd xmm0, xmm7\ncomisd xmm0, xmm6\njbe loc_121D\nloc_12B6:\ncmp r9d, 1\njle short loc_12C7\nmov ecx, 1\npxor xmm4, xmm4\njmp short loc_124B\nloc_12C7:\ndivsd xmm3, xmm8\nsubsd xmm1, xmm3\nmovapd xmm3, xmm5\njmp short loc_12A4\nloc_12D6:\naddsd xmm3, qword ptr [rdi+rcx*8]\nadd rcx, 1\njmp short loc_1274\nloc_12E1:\naddsd xmm3, qword ptr [rdi+rcx*8]\nadd rcx, 1\njmp loc_11A8", + "ida_pseudo": "__int128 __usercall func0@(double *a1@, int a2@)\n{\n double v2; // xmm3_8\n __int64 i; // rcx\n int v4; // eax\n double v5; // xmm0_8\n __int128 v6; // xmm1\n double v8; // xmm0_8\n int v9; // eax\n double v10; // xmm4_8\n __int64 v11; // rcx\n __int64 j; // rcx\n int v13; // eax\n double v14; // xmm0_8\n\n if ( a2 <= 1 )\n {\n v2 = *a1;\n }\n else\n {\n v2 = *a1;\n for ( i = 1LL; i != a2; v2 = v2 + v5 * a1[i++] )\n {\n while ( 1 )\n {\n v4 = 0;\n v5 = 1.0;\n if ( (int)i > 0 )\n break;\n v2 = v2 + a1[i++];\n }\n do\n {\n v5 = v5 * 0.0;\n ++v4;\n }\n while ( v4 != (_DWORD)i );\n }\n }\n v6 = 0LL;\n if ( fabs(v2) <= 0.000001 )\n return 0LL;\n do\n {\n if ( a2 <= 1 )\n {\n *(double *)&v6 = *(double *)&v6 - v2 / 0.0;\n v2 = *a1;\n }\n else\n {\n v11 = 1LL;\n v10 = 0.0;\n do\n {\n v9 = 1;\n v8 = 1.0;\n if ( (int)v11 > 1 )\n {\n do\n {\n v8 = v8 * *(double *)&v6;\n ++v9;\n }\n while ( v9 != (_DWORD)v11 );\n }\n v10 = v10 + v8 * ((double)(int)v11 * a1[v11]);\n ++v11;\n }\n while ( a2 != v11 );\n *(double *)&v6 = *(double *)&v6 - v2 / v10;\n v2 = *a1;\n for ( j = 1LL; j != a2; v2 = v2 + v14 * a1[j++] )\n {\n while ( 1 )\n {\n v13 = 0;\n v14 = 1.0;\n if ( (int)j > 0 )\n break;\n v2 = v2 + a1[j++];\n }\n do\n {\n v14 = v14 * *(double *)&v6;\n ++v13;\n }\n while ( (_DWORD)j != v13 );\n }\n }\n }\n while ( fabs(v2) > 0.000001 );\n return v6;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\nmov r9d, esi\nmovsd xmm5, qword ptr [rdi]\ncmp esi, 1\njle short loc_1213\nmov esi, esi\nmovapd xmm3, xmm5\nmov ecx, 1\npxor xmm1, xmm1\nloc_11A8:\nmov edx, ecx\nmov eax, 0\nmovsd xmm0, cs:qword_2068\ntest ecx, ecx\njle loc_12E1\nloc_11BF:\nmulsd xmm0, xmm1\nadd eax, 1\ncmp eax, edx\njnz short loc_11BF\nmulsd xmm0, qword ptr [rdi+rcx*8]\naddsd xmm3, xmm0\nadd rcx, 1\ncmp rcx, rsi\njnz short loc_11A8\nloc_11DC:\nmovapd xmm0, xmm3\nandpd xmm0, cs:xmmword_2080\npxor xmm1, xmm1\ncomisd xmm0, cs:qword_2070\njbe short loc_1219\nmovapd xmm8, xmm1\nmov r8d, r9d\nmovq xmm7, qword ptr cs:xmmword_2080\nmovsd xmm6, cs:qword_2070\njmp loc_12B6\nloc_1213:\nmovapd xmm3, xmm5\njmp short loc_11DC\nloc_1219:\npxor xmm1, xmm1\nloc_121D:\nmovapd xmm0, xmm1\nretn\nloc_1222:\nmulsd xmm0, xmm1\nadd eax, 1\ncmp eax, edx\njnz short loc_1222\nloc_122D:\npxor xmm2, xmm2\ncvtsi2sd xmm2, esi\nmulsd xmm2, qword ptr [rdi+rcx*8]\nmulsd xmm0, xmm2\naddsd xmm4, xmm0\nadd rcx, 1\ncmp r8, rcx\njz short loc_1263\nloc_124B:\nmov esi, ecx\nmov edx, ecx\nmov eax, 1\nmovsd xmm0, cs:qword_2068\ncmp ecx, 1\njg short loc_1222\njmp short loc_122D\nloc_1263:\ndivsd xmm3, xmm4\nsubsd xmm1, xmm3\nmovapd xmm3, xmm5\nmov ecx, 1\nloc_1274:\nmov edx, ecx\nmov eax, 0\nmovsd xmm0, cs:qword_2068\ntest ecx, ecx\njle short loc_12D6\nloc_1287:\nmulsd xmm0, xmm1\nadd eax, 1\ncmp edx, eax\njnz short loc_1287\nmulsd xmm0, qword ptr [rdi+rcx*8]\naddsd xmm3, xmm0\nadd rcx, 1\ncmp rcx, r8\njnz short loc_1274\nloc_12A4:\nmovapd xmm0, xmm3\nandpd xmm0, xmm7\ncomisd xmm0, xmm6\njbe loc_121D\nloc_12B6:\ncmp r9d, 1\njle short loc_12C7\nmov ecx, 1\npxor xmm4, xmm4\njmp short loc_124B\nloc_12C7:\ndivsd xmm3, xmm8\nsubsd xmm1, xmm3\nmovapd xmm3, xmm5\njmp short loc_12A4\nloc_12D6:\naddsd xmm3, qword ptr [rdi+rcx*8]\nadd rcx, 1\njmp short loc_1274\nloc_12E1:\naddsd xmm3, qword ptr [rdi+rcx*8]\nadd rcx, 1\njmp loc_11A8", + "ida_strip_pseudo": "__int128 __usercall sub_1189@(double *a1@, int a2@)\n{\n double v2; // xmm3_8\n __int64 i; // rcx\n int v4; // eax\n double v5; // xmm0_8\n __int128 v6; // xmm1\n double v8; // xmm0_8\n int v9; // eax\n double v10; // xmm4_8\n __int64 v11; // rcx\n __int64 j; // rcx\n int v13; // eax\n double v14; // xmm0_8\n\n if ( a2 <= 1 )\n {\n v2 = *a1;\n }\n else\n {\n v2 = *a1;\n for ( i = 1LL; i != a2; v2 = v2 + v5 * a1[i++] )\n {\n while ( 1 )\n {\n v4 = 0;\n v5 = 1.0;\n if ( (int)i > 0 )\n break;\n v2 = v2 + a1[i++];\n }\n do\n {\n v5 = v5 * 0.0;\n ++v4;\n }\n while ( v4 != (_DWORD)i );\n }\n }\n v6 = 0LL;\n if ( fabs(v2) <= 0.000001 )\n return 0LL;\n do\n {\n if ( a2 <= 1 )\n {\n *(double *)&v6 = *(double *)&v6 - v2 / 0.0;\n v2 = *a1;\n }\n else\n {\n v11 = 1LL;\n v10 = 0.0;\n do\n {\n v9 = 1;\n v8 = 1.0;\n if ( (int)v11 > 1 )\n {\n do\n {\n v8 = v8 * *(double *)&v6;\n ++v9;\n }\n while ( v9 != (_DWORD)v11 );\n }\n v10 = v10 + v8 * ((double)(int)v11 * a1[v11]);\n ++v11;\n }\n while ( a2 != v11 );\n *(double *)&v6 = *(double *)&v6 - v2 / v10;\n v2 = *a1;\n for ( j = 1LL; j != a2; v2 = v2 + v14 * a1[j++] )\n {\n while ( 1 )\n {\n v13 = 0;\n v14 = 1.0;\n if ( (int)j > 0 )\n break;\n v2 = v2 + a1[j++];\n }\n do\n {\n v14 = v14 * *(double *)&v6;\n ++v13;\n }\n while ( (_DWORD)j != v13 );\n }\n }\n }\n while ( fabs(v2) > 0.000001 );\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__int128 __usercall sub_1189 @(double *a1 @, int a2 @) {\n double v2;\n long long i;\n int v4;\n double v5;\n __int128 v6;\n double v8;\n int v9;\n double v10;\n long long v11;\n long long j;\n int v13;\n double v14;\n if (a2 <= 1) {\n v2 = *a1;\n } else {\n v2 = *a1;\n for (i = 1LL; i != a2; v2 = v2 + v5 * a1[i++]) {\n while (1) {\n v4 = 0;\n v5 = 1.0;\n if ((int)i > 0) break;\n v2 = v2 + a1[i++];\n }\n do {\n v5 = v5 * 0.0;\n ++v4;\n } while (v4 != (uint32_t)i);\n }\n }\n v6 = 0LL;\n if (fabs(v2) <= 0.000001) return 0LL;\n do {\n if (a2 <= 1) {\n *(double *)&v6 = *(double *)&v6 - v2 / 0.0;\n v2 = *a1;\n } else {\n v11 = 1LL;\n v10 = 0.0;\n do {\n v9 = 1;\n v8 = 1.0;\n if ((int)v11 > 1) {\n do {\n v8 = v8 * *(double *)&v6;\n ++v9;\n } while (v9 != (uint32_t)v11);\n }\n v10 = v10 + v8 * ((double)(int)v11 * a1[v11]);\n ++v11;\n } while (a2 != v11);\n *(double *)&v6 = *(double *)&v6 - v2 / v10;\n v2 = *a1;\n for (j = 1LL; j != a2; v2 = v2 + v14 * a1[j++]) {\n while (1) {\n v13 = 0;\n v14 = 1.0;\n if ((int)j > 0) break;\n v2 = v2 + a1[j++];\n }\n do {\n v14 = v14 * *(double *)&v6;\n ++v13;\n } while ((uint32_t)j != v13);\n }\n }\n } while (fabs(v2) > 0.000001);\n return v6;\n}", + "ida_pseudo_norm": "__int128 __usercall func0 @(double *a1 @, int a2 @) {\n double v2;\n long long i;\n int v4;\n double v5;\n __int128 v6;\n double v8;\n int v9;\n double v10;\n long long v11;\n long long j;\n int v13;\n double v14;\n if (a2 <= 1) {\n v2 = *a1;\n } else {\n v2 = *a1;\n for (i = 1LL; i != a2; v2 = v2 + v5 * a1[i++]) {\n while (1) {\n v4 = 0;\n v5 = 1.0;\n if ((int)i > 0) break;\n v2 = v2 + a1[i++];\n }\n do {\n v5 = v5 * 0.0;\n ++v4;\n } while (v4 != (uint32_t)i);\n }\n }\n v6 = 0LL;\n if (fabs(v2) <= 0.000001) return 0LL;\n do {\n if (a2 <= 1) {\n *(double *)&v6 = *(double *)&v6 - v2 / 0.0;\n v2 = *a1;\n } else {\n v11 = 1LL;\n v10 = 0.0;\n do {\n v9 = 1;\n v8 = 1.0;\n if ((int)v11 > 1) {\n do {\n v8 = v8 * *(double *)&v6;\n ++v9;\n } while (v9 != (uint32_t)v11);\n }\n v10 = v10 + v8 * ((double)(int)v11 * a1[v11]);\n ++v11;\n } while (a2 != v11);\n *(double *)&v6 = *(double *)&v6 - v2 / v10;\n v2 = *a1;\n for (j = 1LL; j != a2; v2 = v2 + v14 * a1[j++]) {\n while (1) {\n v13 = 0;\n v14 = 1.0;\n if ((int)j > 0) break;\n v2 = v2 + a1[j++];\n }\n do {\n v14 = v14 * *(double *)&v6;\n ++v13;\n } while ((uint32_t)j != v13);\n }\n }\n } while (fabs(v2) > 0.000001);\n return v6;\n}" + }, + { + "index": "HumanEval-C-32", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "double func0(const double *xs, int size) {\n double ans = 0.0;\n double value, driv, x_pow;\n int i;\n value = xs[0];\n for (i = 1; i < size; i++) {\n x_pow = 1.0;\n for (int j = 0; j < i; j++) {\n x_pow *= ans;\n }\n value += xs[i] * x_pow;\n }\n while (fabs(value) > 1e-6) {\n driv = 0.0;\n for (i = 1; i < size; i++) {\n x_pow = 1.0;\n for (int j = 1; j < i; j++) {\n x_pow *= ans;\n }\n driv += i * xs[i] * x_pow;\n }\n ans = ans - value / driv;\n value = xs[0];\n for (i = 1; i < size; i++) {\n x_pow = 1.0;\n for (int j = 0; j < i; j++) {\n x_pow *= ans;\n }\n value += xs[i] * x_pow;\n }\n }\n return ans;\n}", + "test": "#include \n#include \n#include \n#include \n\n\ndouble evaluate_polynomial(const double *coeffs, int size, double x) {\n double result = 0.0;\n double term = 1.0; \n for (int i = 0; i < size; i++) {\n if (i > 0) {\n term *= x; \n }\n result += coeffs[i] * term;\n }\n return result;\n}\n\nint main() {\n double solution;\n int ncoeff;\n \n for (int i = 0; i < 100; i++) {\n ncoeff = 2 * (1 + rand() % 4);\n double coeffs[ncoeff];\n for (int j = 0; j < ncoeff; j++) {\n double coeff = -10 + rand() % 21;\n if (coeff == 0) coeff = 1;\n coeffs[j] = coeff;\n }\n \n solution = func0(coeffs, ncoeff);\n\n assert(fabs(evaluate_polynomial(coeffs, ncoeff, solution)) < 1e-3);\n }\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmovsd xmm6, qword ptr [rdi]\nmov ecx, esi\ncmp esi, 1\njle loc_14C9\nmov r8d, esi\nmovapd xmm3, xmm6\npxor xmm1, xmm1\nmov edx, 1\nmovsd xmm5, cs:qword_2068\nnop dword ptr [rax+rax+00h]\nloc_1370:\nxor eax, eax\nmovapd xmm0, xmm5\ntest dl, 1\njz short loc_1390\nmov eax, 1\npxor xmm0, xmm0\ncmp eax, edx\njz short loc_139F\nnop dword ptr [rax+rax+00000000h]\nloc_1390:\nmulsd xmm0, xmm1\nadd eax, 2\nmulsd xmm0, xmm1\ncmp eax, edx\njnz short loc_1390\nloc_139F:\nmulsd xmm0, qword ptr [rdi+rdx*8]\nadd rdx, 1\naddsd xmm3, xmm0\ncmp r8, rdx\njnz short loc_1370\nloc_13B1:\nmovq xmm7, qword ptr cs:xmmword_2080\nmovapd xmm0, xmm3\npxor xmm1, xmm1\nmovsd xmm8, cs:qword_2070\nandpd xmm0, xmm7\ncomisd xmm0, xmm8\njbe loc_14C4\ncmp ecx, 1\njle loc_14D2\nmovsd xmm5, cs:qword_2068\nmov r8d, ecx\nnop dword ptr [rax]\nloc_13F0:\nmov edx, 1\npxor xmm4, xmm4\nnop dword ptr [rax+00000000h]\nloc_1400:\nmov esi, edx\nmov ecx, edx\nmovapd xmm0, xmm5\nmov eax, 1\ncmp edx, 1\njz short loc_1437\ntest dl, 1\njnz short loc_1428\nmulsd xmm0, xmm1\nmov eax, 2\ncmp eax, edx\njz short loc_1437\nnop dword ptr [rax+00h]\nloc_1428:\nmulsd xmm0, xmm1\nadd eax, 2\nmulsd xmm0, xmm1\ncmp eax, ecx\njnz short loc_1428\nloc_1437:\npxor xmm2, xmm2\ncvtsi2sd xmm2, esi\nmulsd xmm2, qword ptr [rdi+rdx*8]\nadd rdx, 1\nmulsd xmm0, xmm2\naddsd xmm4, xmm0\ncmp r8, rdx\njnz short loc_1400\ndivsd xmm3, xmm4\nmov edx, 1\nsubsd xmm1, xmm3\nmovapd xmm3, xmm6\nnop word ptr [rax+rax+00000000h]\nloc_1470:\nxor eax, eax\nmovapd xmm0, xmm5\ntest dl, 1\njz short loc_1490\nmov eax, 1\nmovapd xmm0, xmm1\ncmp eax, edx\njz short loc_149F\nnop dword ptr [rax+rax+00000000h]\nloc_1490:\nmulsd xmm0, xmm1\nadd eax, 2\nmulsd xmm0, xmm1\ncmp eax, edx\njnz short loc_1490\nloc_149F:\nmulsd xmm0, qword ptr [rdi+rdx*8]\nadd rdx, 1\naddsd xmm3, xmm0\ncmp r8, rdx\njnz short loc_1470\nmovapd xmm0, xmm3\nandpd xmm0, xmm7\ncomisd xmm0, xmm8\nja loc_13F0\nloc_14C4:\nmovapd xmm0, xmm1\nretn\nloc_14C9:\nmovapd xmm3, xmm6\njmp loc_13B1\nloc_14D2:\nmovapd xmm0, xmm1\nandpd xmm7, xmm6\njmp short loc_14E0\nloc_14DC:\nmovapd xmm3, xmm6\nloc_14E0:\ndivsd xmm3, xmm0\ncomisd xmm7, xmm8\nsubsd xmm1, xmm3\nja short loc_14DC\njmp short loc_14C4", + "ida_pseudo": "__int128 __usercall func0@(double *a1@, int a2@)\n{\n double v2; // xmm3_8\n __int64 v3; // rdx\n int v4; // eax\n double v5; // xmm0_8\n double v6; // xmm0_8\n __int128 v7; // xmm1\n __int64 v8; // rdx\n double v9; // xmm4_8\n double v10; // xmm0_8\n int v11; // eax\n double v12; // xmm2_8\n __int64 v13; // rdx\n int v14; // eax\n double v15; // xmm0_8\n double v16; // xmm0_8\n double v18; // xmm7_8\n\n if ( a2 <= 1 )\n {\n v2 = *a1;\n }\n else\n {\n v2 = *a1;\n v3 = 1LL;\n do\n {\n v4 = 0;\n v5 = 1.0;\n if ( (v3 & 1) == 0 || (v4 = 1, v5 = 0.0, (_DWORD)v3 != 1) )\n {\n do\n {\n v4 += 2;\n v5 = v5 * 0.0 * 0.0;\n }\n while ( v4 != (_DWORD)v3 );\n }\n v6 = v5 * a1[v3++];\n v2 = v2 + v6;\n }\n while ( a2 != v3 );\n }\n v7 = 0LL;\n if ( fabs(v2) > 0.000001 )\n {\n if ( a2 <= 1 )\n {\n v18 = fabs(*a1);\n while ( 1 )\n {\n *(double *)&v7 = *(double *)&v7 - v2 / 0.0;\n if ( v18 <= 0.000001 )\n break;\n v2 = *a1;\n }\n }\n else\n {\n do\n {\n v8 = 1LL;\n v9 = 0.0;\n do\n {\n v10 = 1.0;\n v11 = 1;\n if ( (_DWORD)v8 != 1 )\n {\n if ( (v8 & 1) != 0 || (v10 = 1.0 * *(double *)&v7, v11 = 2, (_DWORD)v8 != 2) )\n {\n do\n {\n v11 += 2;\n v10 = v10 * *(double *)&v7 * *(double *)&v7;\n }\n while ( v11 != (_DWORD)v8 );\n }\n }\n v12 = (double)(int)v8 * a1[v8];\n ++v8;\n v9 = v9 + v10 * v12;\n }\n while ( a2 != v8 );\n v13 = 1LL;\n *(double *)&v7 = *(double *)&v7 - v2 / v9;\n v2 = *a1;\n do\n {\n v14 = 0;\n v15 = 1.0;\n if ( (v13 & 1) == 0 || (v14 = 1, v15 = *(double *)&v7, (_DWORD)v13 != 1) )\n {\n do\n {\n v14 += 2;\n v15 = v15 * *(double *)&v7 * *(double *)&v7;\n }\n while ( v14 != (_DWORD)v13 );\n }\n v16 = v15 * a1[v13++];\n v2 = v2 + v16;\n }\n while ( a2 != v13 );\n }\n while ( fabs(v2) > 0.000001 );\n }\n }\n return v7;\n}", + "ida_strip_asm": "sub_1340:\nendbr64\nmovsd xmm6, qword ptr [rdi]\nmov ecx, esi\ncmp esi, 1\njle loc_14C9\nmov r8d, esi\nmovapd xmm3, xmm6\npxor xmm1, xmm1\nmov edx, 1\nmovsd xmm5, cs:qword_2068\nnop dword ptr [rax+rax+00h]\nloc_1370:\nxor eax, eax\nmovapd xmm0, xmm5\ntest dl, 1\njz short loc_1390\nmov eax, 1\npxor xmm0, xmm0\ncmp eax, edx\njz short loc_139F\nnop dword ptr [rax+rax+00000000h]\nloc_1390:\nmulsd xmm0, xmm1\nadd eax, 2\nmulsd xmm0, xmm1\ncmp eax, edx\njnz short loc_1390\nloc_139F:\nmulsd xmm0, qword ptr [rdi+rdx*8]\nadd rdx, 1\naddsd xmm3, xmm0\ncmp r8, rdx\njnz short loc_1370\nloc_13B1:\nmovq xmm7, qword ptr cs:xmmword_2080\nmovapd xmm0, xmm3\npxor xmm1, xmm1\nmovsd xmm8, cs:qword_2070\nandpd xmm0, xmm7\ncomisd xmm0, xmm8\njbe loc_14C4\ncmp ecx, 1\njle loc_14D2\nmovsd xmm5, cs:qword_2068\nmov r8d, ecx\nnop dword ptr [rax]\nloc_13F0:\nmov edx, 1\npxor xmm4, xmm4\nnop dword ptr [rax+00000000h]\nloc_1400:\nmov esi, edx\nmov ecx, edx\nmovapd xmm0, xmm5\nmov eax, 1\ncmp edx, 1\njz short loc_1437\ntest dl, 1\njnz short loc_1428\nmulsd xmm0, xmm1\nmov eax, 2\ncmp eax, edx\njz short loc_1437\nnop dword ptr [rax+00h]\nloc_1428:\nmulsd xmm0, xmm1\nadd eax, 2\nmulsd xmm0, xmm1\ncmp eax, ecx\njnz short loc_1428\nloc_1437:\npxor xmm2, xmm2\ncvtsi2sd xmm2, esi\nmulsd xmm2, qword ptr [rdi+rdx*8]\nadd rdx, 1\nmulsd xmm0, xmm2\naddsd xmm4, xmm0\ncmp r8, rdx\njnz short loc_1400\ndivsd xmm3, xmm4\nmov edx, 1\nsubsd xmm1, xmm3\nmovapd xmm3, xmm6\nnop word ptr [rax+rax+00000000h]\nloc_1470:\nxor eax, eax\nmovapd xmm0, xmm5\ntest dl, 1\njz short loc_1490\nmov eax, 1\nmovapd xmm0, xmm1\ncmp eax, edx\njz short loc_149F\nnop dword ptr [rax+rax+00000000h]\nloc_1490:\nmulsd xmm0, xmm1\nadd eax, 2\nmulsd xmm0, xmm1\ncmp eax, edx\njnz short loc_1490\nloc_149F:\nmulsd xmm0, qword ptr [rdi+rdx*8]\nadd rdx, 1\naddsd xmm3, xmm0\ncmp r8, rdx\njnz short loc_1470\nmovapd xmm0, xmm3\nandpd xmm0, xmm7\ncomisd xmm0, xmm8\nja loc_13F0\nloc_14C4:\nmovapd xmm0, xmm1\nretn\nloc_14C9:\nmovapd xmm3, xmm6\njmp loc_13B1\nloc_14D2:\nmovapd xmm0, xmm1\nandpd xmm7, xmm6\njmp short loc_14E0\nloc_14DC:\nmovapd xmm3, xmm6\nloc_14E0:\ndivsd xmm3, xmm0\ncomisd xmm7, xmm8\nsubsd xmm1, xmm3\nja short loc_14DC\njmp short loc_14C4", + "ida_strip_pseudo": "__int128 __usercall sub_1340@(double *a1@, int a2@)\n{\n double v2; // xmm3_8\n __int64 v3; // rdx\n int v4; // eax\n double v5; // xmm0_8\n double v6; // xmm0_8\n __int128 v7; // xmm1\n __int64 v8; // rdx\n double v9; // xmm4_8\n double v10; // xmm0_8\n int v11; // eax\n double v12; // xmm2_8\n __int64 v13; // rdx\n int v14; // eax\n double v15; // xmm0_8\n double v16; // xmm0_8\n double v18; // xmm7_8\n\n if ( a2 <= 1 )\n {\n v2 = *a1;\n }\n else\n {\n v2 = *a1;\n v3 = 1LL;\n do\n {\n v4 = 0;\n v5 = 1.0;\n if ( (v3 & 1) == 0 || (v4 = 1, v5 = 0.0, (_DWORD)v3 != 1) )\n {\n do\n {\n v4 += 2;\n v5 = v5 * 0.0 * 0.0;\n }\n while ( v4 != (_DWORD)v3 );\n }\n v6 = v5 * a1[v3++];\n v2 = v2 + v6;\n }\n while ( a2 != v3 );\n }\n v7 = 0LL;\n if ( fabs(v2) > 0.000001 )\n {\n if ( a2 <= 1 )\n {\n v18 = fabs(*a1);\n while ( 1 )\n {\n *(double *)&v7 = *(double *)&v7 - v2 / 0.0;\n if ( v18 <= 0.000001 )\n break;\n v2 = *a1;\n }\n }\n else\n {\n do\n {\n v8 = 1LL;\n v9 = 0.0;\n do\n {\n v10 = 1.0;\n v11 = 1;\n if ( (_DWORD)v8 != 1 )\n {\n if ( (v8 & 1) != 0 || (v10 = 1.0 * *(double *)&v7, v11 = 2, (_DWORD)v8 != 2) )\n {\n do\n {\n v11 += 2;\n v10 = v10 * *(double *)&v7 * *(double *)&v7;\n }\n while ( v11 != (_DWORD)v8 );\n }\n }\n v12 = (double)(int)v8 * a1[v8];\n ++v8;\n v9 = v9 + v10 * v12;\n }\n while ( a2 != v8 );\n v13 = 1LL;\n *(double *)&v7 = *(double *)&v7 - v2 / v9;\n v2 = *a1;\n do\n {\n v14 = 0;\n v15 = 1.0;\n if ( (v13 & 1) == 0 || (v14 = 1, v15 = *(double *)&v7, (_DWORD)v13 != 1) )\n {\n do\n {\n v14 += 2;\n v15 = v15 * *(double *)&v7 * *(double *)&v7;\n }\n while ( v14 != (_DWORD)v13 );\n }\n v16 = v15 * a1[v13++];\n v2 = v2 + v16;\n }\n while ( a2 != v13 );\n }\n while ( fabs(v2) > 0.000001 );\n }\n }\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__int128 __usercall sub_1340 @(double *a1 @, int a2 @) {\n double v2;\n long long v3;\n int v4;\n double v5;\n double v6;\n __int128 v7;\n long long v8;\n double v9;\n double v10;\n int v11;\n double v12;\n long long v13;\n int v14;\n double v15;\n double v16;\n double v18;\n if (a2 <= 1) {\n v2 = *a1;\n } else {\n v2 = *a1;\n v3 = 1LL;\n do {\n v4 = 0;\n v5 = 1.0;\n if ((v3 & 1) == 0 || (v4 = 1, v5 = 0.0, (uint32_t)v3 != 1)) {\n do {\n v4 += 2;\n v5 = v5 * 0.0 * 0.0;\n } while (v4 != (uint32_t)v3);\n }\n v6 = v5 * a1[v3++];\n v2 = v2 + v6;\n } while (a2 != v3);\n }\n v7 = 0LL;\n if (fabs(v2) > 0.000001) {\n if (a2 <= 1) {\n v18 = fabs(*a1);\n while (1) {\n *(double *)&v7 = *(double *)&v7 - v2 / 0.0;\n if (v18 <= 0.000001) break;\n v2 = *a1;\n }\n } else {\n do {\n v8 = 1LL;\n v9 = 0.0;\n do {\n v10 = 1.0;\n v11 = 1;\n if ((uint32_t)v8 != 1) {\n if ((v8 & 1) != 0 ||\n (v10 = 1.0 * *(double *)&v7, v11 = 2, (uint32_t)v8 != 2)) {\n do {\n v11 += 2;\n v10 = v10 * *(double *)&v7 * *(double *)&v7;\n } while (v11 != (uint32_t)v8);\n }\n }\n v12 = (double)(int)v8 * a1[v8];\n ++v8;\n v9 = v9 + v10 * v12;\n } while (a2 != v8);\n v13 = 1LL;\n *(double *)&v7 = *(double *)&v7 - v2 / v9;\n v2 = *a1;\n do {\n v14 = 0;\n v15 = 1.0;\n if ((v13 & 1) == 0 ||\n (v14 = 1, v15 = *(double *)&v7, (uint32_t)v13 != 1)) {\n do {\n v14 += 2;\n v15 = v15 * *(double *)&v7 * *(double *)&v7;\n } while (v14 != (uint32_t)v13);\n }\n v16 = v15 * a1[v13++];\n v2 = v2 + v16;\n } while (a2 != v13);\n } while (fabs(v2) > 0.000001);\n }\n }\n return v7;\n}", + "ida_pseudo_norm": "__int128 __usercall func0 @(double *a1 @, int a2 @) {\n double v2;\n long long v3;\n int v4;\n double v5;\n double v6;\n __int128 v7;\n long long v8;\n double v9;\n double v10;\n int v11;\n double v12;\n long long v13;\n int v14;\n double v15;\n double v16;\n double v18;\n if (a2 <= 1) {\n v2 = *a1;\n } else {\n v2 = *a1;\n v3 = 1LL;\n do {\n v4 = 0;\n v5 = 1.0;\n if ((v3 & 1) == 0 || (v4 = 1, v5 = 0.0, (uint32_t)v3 != 1)) {\n do {\n v4 += 2;\n v5 = v5 * 0.0 * 0.0;\n } while (v4 != (uint32_t)v3);\n }\n v6 = v5 * a1[v3++];\n v2 = v2 + v6;\n } while (a2 != v3);\n }\n v7 = 0LL;\n if (fabs(v2) > 0.000001) {\n if (a2 <= 1) {\n v18 = fabs(*a1);\n while (1) {\n *(double *)&v7 = *(double *)&v7 - v2 / 0.0;\n if (v18 <= 0.000001) break;\n v2 = *a1;\n }\n } else {\n do {\n v8 = 1LL;\n v9 = 0.0;\n do {\n v10 = 1.0;\n v11 = 1;\n if ((uint32_t)v8 != 1) {\n if ((v8 & 1) != 0 ||\n (v10 = 1.0 * *(double *)&v7, v11 = 2, (uint32_t)v8 != 2)) {\n do {\n v11 += 2;\n v10 = v10 * *(double *)&v7 * *(double *)&v7;\n } while (v11 != (uint32_t)v8);\n }\n }\n v12 = (double)(int)v8 * a1[v8];\n ++v8;\n v9 = v9 + v10 * v12;\n } while (a2 != v8);\n v13 = 1LL;\n *(double *)&v7 = *(double *)&v7 - v2 / v9;\n v2 = *a1;\n do {\n v14 = 0;\n v15 = 1.0;\n if ((v13 & 1) == 0 ||\n (v14 = 1, v15 = *(double *)&v7, (uint32_t)v13 != 1)) {\n do {\n v14 += 2;\n v15 = v15 * *(double *)&v7 * *(double *)&v7;\n } while (v14 != (uint32_t)v13);\n }\n v16 = v15 * a1[v13++];\n v2 = v2 + v16;\n } while (a2 != v13);\n } while (fabs(v2) > 0.000001);\n }\n }\n return v7;\n}" + }, + { + "index": "HumanEval-C-32", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "double func0(const double *xs, int size) {\n double ans = 0.0;\n double value, driv, x_pow;\n int i;\n value = xs[0];\n for (i = 1; i < size; i++) {\n x_pow = 1.0;\n for (int j = 0; j < i; j++) {\n x_pow *= ans;\n }\n value += xs[i] * x_pow;\n }\n while (fabs(value) > 1e-6) {\n driv = 0.0;\n for (i = 1; i < size; i++) {\n x_pow = 1.0;\n for (int j = 1; j < i; j++) {\n x_pow *= ans;\n }\n driv += i * xs[i] * x_pow;\n }\n ans = ans - value / driv;\n value = xs[0];\n for (i = 1; i < size; i++) {\n x_pow = 1.0;\n for (int j = 0; j < i; j++) {\n x_pow *= ans;\n }\n value += xs[i] * x_pow;\n }\n }\n return ans;\n}", + "test": "#include \n#include \n#include \n#include \n\n\ndouble evaluate_polynomial(const double *coeffs, int size, double x) {\n double result = 0.0;\n double term = 1.0; \n for (int i = 0; i < size; i++) {\n if (i > 0) {\n term *= x; \n }\n result += coeffs[i] * term;\n }\n return result;\n}\n\nint main() {\n double solution;\n int ncoeff;\n \n for (int i = 0; i < 100; i++) {\n ncoeff = 2 * (1 + rand() % 4);\n double coeffs[ncoeff];\n for (int j = 0; j < ncoeff; j++) {\n double coeff = -10 + rand() % 21;\n if (coeff == 0) coeff = 1;\n coeffs[j] = coeff;\n }\n \n solution = func0(coeffs, ncoeff);\n\n assert(fabs(evaluate_polynomial(coeffs, ncoeff, solution)) < 1e-3);\n }\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmov rcx, rdi\nmov edi, esi\nmovsd xmm7, qword ptr [rcx]\ncmp esi, 1\njle loc_15A9\nmov esi, esi\nmovapd xmm2, xmm7\npxor xmm1, xmm1\nmov edx, 1\nmovsd xmm5, cs:qword_2068\nnop dword ptr [rax]\nloc_1440:\nxor eax, eax\nmovapd xmm0, xmm5\ntest dl, 1\njz short loc_1460\nmov eax, 1\npxor xmm0, xmm0\ncmp eax, edx\njz short loc_146F\nnop dword ptr [rax+rax+00000000h]\nloc_1460:\nmulsd xmm0, xmm1\nadd eax, 2\nmulsd xmm0, xmm1\ncmp eax, edx\njnz short loc_1460\nloc_146F:\nmulsd xmm0, qword ptr [rcx+rdx*8]\nadd rdx, 1\naddsd xmm2, xmm0\ncmp rsi, rdx\njnz short loc_1440\nloc_1481:\nmovq xmm6, qword ptr cs:xmmword_2080\nmovapd xmm0, xmm2\npxor xmm1, xmm1\nmovsd xmm8, cs:qword_2070\nandpd xmm0, xmm6\ncomisd xmm0, xmm8\njbe loc_15A4\ncmp edi, 1\njle loc_15B2\nmovsd xmm5, cs:qword_2068\nmov esi, edi\nlea r10, [rcx+8]\nmovapd xmm9, xmm1\nnop dword ptr [rax]\nloc_14C8:\nmovsd xmm4, qword ptr [r10]\nmov edx, 2\naddsd xmm4, xmm9\ncmp edi, 2\njz short loc_153D\nloc_14DC:\nmov r9d, edx\nmovapd xmm0, xmm5\nmov eax, 2\nmov r8d, edx\nmulsd xmm0, xmm1\nand r9d, 1\ncmp eax, edx\njge short loc_151F\ntest r9d, r9d\njz short loc_1510\nmulsd xmm0, xmm1\nmov eax, 3\ncmp eax, edx\njge short loc_151F\nnop dword ptr [rax+00000000h]\nloc_1510:\nmulsd xmm0, xmm1\nadd eax, 2\nmulsd xmm0, xmm1\ncmp eax, edx\njl short loc_1510\nloc_151F:\npxor xmm3, xmm3\ncvtsi2sd xmm3, r8d\nmulsd xmm3, qword ptr [rcx+rdx*8]\nadd rdx, 1\nmulsd xmm0, xmm3\naddsd xmm4, xmm0\ncmp edi, edx\njg short loc_14DC\nloc_153D:\ndivsd xmm2, xmm4\nmov edx, 1\nsubsd xmm1, xmm2\nmovapd xmm2, xmm7\nxchg ax, ax\nloc_1550:\nxor eax, eax\nmovapd xmm0, xmm5\ntest dl, 1\njz short loc_1570\nmov eax, 1\nmovapd xmm0, xmm1\ncmp eax, edx\njz short loc_157F\nnop dword ptr [rax+rax+00000000h]\nloc_1570:\nmulsd xmm0, xmm1\nadd eax, 2\nmulsd xmm0, xmm1\ncmp eax, edx\njnz short loc_1570\nloc_157F:\nmulsd xmm0, qword ptr [rcx+rdx*8]\nadd rdx, 1\naddsd xmm2, xmm0\ncmp rdx, rsi\njnz short loc_1550\nmovapd xmm0, xmm2\nandpd xmm0, xmm6\ncomisd xmm0, xmm8\nja loc_14C8\nloc_15A4:\nmovapd xmm0, xmm1\nretn\nloc_15A9:\nmovapd xmm2, xmm7\njmp loc_1481\nloc_15B2:\nmovapd xmm0, xmm1\nandpd xmm6, xmm7\njmp short loc_15C0\nloc_15BC:\nmovapd xmm2, xmm7\nloc_15C0:\ndivsd xmm2, xmm0\ncomisd xmm6, xmm8\nsubsd xmm1, xmm2\nja short loc_15BC\njmp short loc_15A4", + "ida_pseudo": "__int128 __usercall func0@(double *a1@, int a2@)\n{\n double v2; // xmm2_8\n __int64 v3; // rdx\n int v4; // eax\n double v5; // xmm0_8\n double v6; // xmm0_8\n __int128 v7; // xmm1\n __int64 v8; // rdx\n double v9; // xmm4_8\n int v10; // eax\n double v11; // xmm0_8\n double v12; // xmm3_8\n __int64 v13; // rdx\n int v14; // eax\n double v15; // xmm0_8\n double v16; // xmm0_8\n double v18; // xmm6_8\n\n if ( a2 <= 1 )\n {\n v2 = *a1;\n }\n else\n {\n v2 = *a1;\n v3 = 1LL;\n do\n {\n v4 = 0;\n v5 = 1.0;\n if ( (v3 & 1) == 0 || (v4 = 1, v5 = 0.0, (_DWORD)v3 != 1) )\n {\n do\n {\n v4 += 2;\n v5 = v5 * 0.0 * 0.0;\n }\n while ( v4 != (_DWORD)v3 );\n }\n v6 = v5 * a1[v3++];\n v2 = v2 + v6;\n }\n while ( a2 != v3 );\n }\n v7 = 0LL;\n if ( fabs(v2) > 0.000001 )\n {\n if ( a2 <= 1 )\n {\n v18 = fabs(*a1);\n while ( 1 )\n {\n *(double *)&v7 = *(double *)&v7 - v2 / 0.0;\n if ( v18 <= 0.000001 )\n break;\n v2 = *a1;\n }\n }\n else\n {\n do\n {\n v8 = 2LL;\n v9 = a1[1] + 0.0;\n if ( a2 != 2 )\n {\n do\n {\n v10 = 2;\n v11 = 1.0 * *(double *)&v7;\n if ( (int)v8 > 2 )\n {\n if ( (v8 & 1) == 0 || (v11 = v11 * *(double *)&v7, v10 = 3, (int)v8 > 3) )\n {\n do\n {\n v10 += 2;\n v11 = v11 * *(double *)&v7 * *(double *)&v7;\n }\n while ( v10 < (int)v8 );\n }\n }\n v12 = (double)(int)v8 * a1[v8];\n ++v8;\n v9 = v9 + v11 * v12;\n }\n while ( a2 > (int)v8 );\n }\n v13 = 1LL;\n *(double *)&v7 = *(double *)&v7 - v2 / v9;\n v2 = *a1;\n do\n {\n v14 = 0;\n v15 = 1.0;\n if ( (v13 & 1) == 0 || (v14 = 1, v15 = *(double *)&v7, (_DWORD)v13 != 1) )\n {\n do\n {\n v14 += 2;\n v15 = v15 * *(double *)&v7 * *(double *)&v7;\n }\n while ( v14 != (_DWORD)v13 );\n }\n v16 = v15 * a1[v13++];\n v2 = v2 + v16;\n }\n while ( v13 != a2 );\n }\n while ( fabs(v2) > 0.000001 );\n }\n }\n return v7;\n}", + "ida_strip_asm": "sub_1410:\nendbr64\nmov rcx, rdi\nmov edi, esi\nmovsd xmm7, qword ptr [rcx]\ncmp esi, 1\njle loc_15A9\nmov esi, esi\nmovapd xmm2, xmm7\npxor xmm1, xmm1\nmov edx, 1\nmovsd xmm5, cs:qword_2068\nnop dword ptr [rax]\nloc_1440:\nxor eax, eax\nmovapd xmm0, xmm5\ntest dl, 1\njz short loc_1460\nmov eax, 1\npxor xmm0, xmm0\ncmp eax, edx\njz short loc_146F\nnop dword ptr [rax+rax+00000000h]\nloc_1460:\nmulsd xmm0, xmm1\nadd eax, 2\nmulsd xmm0, xmm1\ncmp eax, edx\njnz short loc_1460\nloc_146F:\nmulsd xmm0, qword ptr [rcx+rdx*8]\nadd rdx, 1\naddsd xmm2, xmm0\ncmp rsi, rdx\njnz short loc_1440\nloc_1481:\nmovq xmm6, qword ptr cs:xmmword_2080\nmovapd xmm0, xmm2\npxor xmm1, xmm1\nmovsd xmm8, cs:qword_2070\nandpd xmm0, xmm6\ncomisd xmm0, xmm8\njbe loc_15A4\ncmp edi, 1\njle loc_15B2\nmovsd xmm5, cs:qword_2068\nmov esi, edi\nlea r10, [rcx+8]\nmovapd xmm9, xmm1\nnop dword ptr [rax]\nloc_14C8:\nmovsd xmm4, qword ptr [r10]\nmov edx, 2\naddsd xmm4, xmm9\ncmp edi, 2\njz short loc_153D\nloc_14DC:\nmov r9d, edx\nmovapd xmm0, xmm5\nmov eax, 2\nmov r8d, edx\nmulsd xmm0, xmm1\nand r9d, 1\ncmp eax, edx\njge short loc_151F\ntest r9d, r9d\njz short loc_1510\nmulsd xmm0, xmm1\nmov eax, 3\ncmp eax, edx\njge short loc_151F\nnop dword ptr [rax+00000000h]\nloc_1510:\nmulsd xmm0, xmm1\nadd eax, 2\nmulsd xmm0, xmm1\ncmp eax, edx\njl short loc_1510\nloc_151F:\npxor xmm3, xmm3\ncvtsi2sd xmm3, r8d\nmulsd xmm3, qword ptr [rcx+rdx*8]\nadd rdx, 1\nmulsd xmm0, xmm3\naddsd xmm4, xmm0\ncmp edi, edx\njg short loc_14DC\nloc_153D:\ndivsd xmm2, xmm4\nmov edx, 1\nsubsd xmm1, xmm2\nmovapd xmm2, xmm7\nxchg ax, ax\nloc_1550:\nxor eax, eax\nmovapd xmm0, xmm5\ntest dl, 1\njz short loc_1570\nmov eax, 1\nmovapd xmm0, xmm1\ncmp eax, edx\njz short loc_157F\nnop dword ptr [rax+rax+00000000h]\nloc_1570:\nmulsd xmm0, xmm1\nadd eax, 2\nmulsd xmm0, xmm1\ncmp eax, edx\njnz short loc_1570\nloc_157F:\nmulsd xmm0, qword ptr [rcx+rdx*8]\nadd rdx, 1\naddsd xmm2, xmm0\ncmp rdx, rsi\njnz short loc_1550\nmovapd xmm0, xmm2\nandpd xmm0, xmm6\ncomisd xmm0, xmm8\nja loc_14C8\nloc_15A4:\nmovapd xmm0, xmm1\nretn\nloc_15A9:\nmovapd xmm2, xmm7\njmp loc_1481\nloc_15B2:\nmovapd xmm0, xmm1\nandpd xmm6, xmm7\njmp short loc_15C0\nloc_15BC:\nmovapd xmm2, xmm7\nloc_15C0:\ndivsd xmm2, xmm0\ncomisd xmm6, xmm8\nsubsd xmm1, xmm2\nja short loc_15BC\njmp short loc_15A4", + "ida_strip_pseudo": "__int128 __usercall sub_1410@(double *a1@, int a2@)\n{\n double v2; // xmm2_8\n __int64 v3; // rdx\n int v4; // eax\n double v5; // xmm0_8\n double v6; // xmm0_8\n __int128 v7; // xmm1\n __int64 v8; // rdx\n double v9; // xmm4_8\n int v10; // eax\n double v11; // xmm0_8\n double v12; // xmm3_8\n __int64 v13; // rdx\n int v14; // eax\n double v15; // xmm0_8\n double v16; // xmm0_8\n double v18; // xmm6_8\n\n if ( a2 <= 1 )\n {\n v2 = *a1;\n }\n else\n {\n v2 = *a1;\n v3 = 1LL;\n do\n {\n v4 = 0;\n v5 = 1.0;\n if ( (v3 & 1) == 0 || (v4 = 1, v5 = 0.0, (_DWORD)v3 != 1) )\n {\n do\n {\n v4 += 2;\n v5 = v5 * 0.0 * 0.0;\n }\n while ( v4 != (_DWORD)v3 );\n }\n v6 = v5 * a1[v3++];\n v2 = v2 + v6;\n }\n while ( a2 != v3 );\n }\n v7 = 0LL;\n if ( fabs(v2) > 0.000001 )\n {\n if ( a2 <= 1 )\n {\n v18 = fabs(*a1);\n while ( 1 )\n {\n *(double *)&v7 = *(double *)&v7 - v2 / 0.0;\n if ( v18 <= 0.000001 )\n break;\n v2 = *a1;\n }\n }\n else\n {\n do\n {\n v8 = 2LL;\n v9 = a1[1] + 0.0;\n if ( a2 != 2 )\n {\n do\n {\n v10 = 2;\n v11 = 1.0 * *(double *)&v7;\n if ( (int)v8 > 2 )\n {\n if ( (v8 & 1) == 0 || (v11 = v11 * *(double *)&v7, v10 = 3, (int)v8 > 3) )\n {\n do\n {\n v10 += 2;\n v11 = v11 * *(double *)&v7 * *(double *)&v7;\n }\n while ( v10 < (int)v8 );\n }\n }\n v12 = (double)(int)v8 * a1[v8];\n ++v8;\n v9 = v9 + v11 * v12;\n }\n while ( a2 > (int)v8 );\n }\n v13 = 1LL;\n *(double *)&v7 = *(double *)&v7 - v2 / v9;\n v2 = *a1;\n do\n {\n v14 = 0;\n v15 = 1.0;\n if ( (v13 & 1) == 0 || (v14 = 1, v15 = *(double *)&v7, (_DWORD)v13 != 1) )\n {\n do\n {\n v14 += 2;\n v15 = v15 * *(double *)&v7 * *(double *)&v7;\n }\n while ( v14 != (_DWORD)v13 );\n }\n v16 = v15 * a1[v13++];\n v2 = v2 + v16;\n }\n while ( v13 != a2 );\n }\n while ( fabs(v2) > 0.000001 );\n }\n }\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__int128 __usercall sub_1410 @(double *a1 @, int a2 @) {\n double v2;\n long long v3;\n int v4;\n double v5;\n double v6;\n __int128 v7;\n long long v8;\n double v9;\n int v10;\n double v11;\n double v12;\n long long v13;\n int v14;\n double v15;\n double v16;\n double v18;\n if (a2 <= 1) {\n v2 = *a1;\n } else {\n v2 = *a1;\n v3 = 1LL;\n do {\n v4 = 0;\n v5 = 1.0;\n if ((v3 & 1) == 0 || (v4 = 1, v5 = 0.0, (uint32_t)v3 != 1)) {\n do {\n v4 += 2;\n v5 = v5 * 0.0 * 0.0;\n } while (v4 != (uint32_t)v3);\n }\n v6 = v5 * a1[v3++];\n v2 = v2 + v6;\n } while (a2 != v3);\n }\n v7 = 0LL;\n if (fabs(v2) > 0.000001) {\n if (a2 <= 1) {\n v18 = fabs(*a1);\n while (1) {\n *(double *)&v7 = *(double *)&v7 - v2 / 0.0;\n if (v18 <= 0.000001) break;\n v2 = *a1;\n }\n } else {\n do {\n v8 = 2LL;\n v9 = a1[1] + 0.0;\n if (a2 != 2) {\n do {\n v10 = 2;\n v11 = 1.0 * *(double *)&v7;\n if ((int)v8 > 2) {\n if ((v8 & 1) == 0 ||\n (v11 = v11 * *(double *)&v7, v10 = 3, (int)v8 > 3)) {\n do {\n v10 += 2;\n v11 = v11 * *(double *)&v7 * *(double *)&v7;\n } while (v10 < (int)v8);\n }\n }\n v12 = (double)(int)v8 * a1[v8];\n ++v8;\n v9 = v9 + v11 * v12;\n } while (a2 > (int)v8);\n }\n v13 = 1LL;\n *(double *)&v7 = *(double *)&v7 - v2 / v9;\n v2 = *a1;\n do {\n v14 = 0;\n v15 = 1.0;\n if ((v13 & 1) == 0 ||\n (v14 = 1, v15 = *(double *)&v7, (uint32_t)v13 != 1)) {\n do {\n v14 += 2;\n v15 = v15 * *(double *)&v7 * *(double *)&v7;\n } while (v14 != (uint32_t)v13);\n }\n v16 = v15 * a1[v13++];\n v2 = v2 + v16;\n } while (v13 != a2);\n } while (fabs(v2) > 0.000001);\n }\n }\n return v7;\n}", + "ida_pseudo_norm": "__int128 __usercall func0 @(double *a1 @, int a2 @) {\n double v2;\n long long v3;\n int v4;\n double v5;\n double v6;\n __int128 v7;\n long long v8;\n double v9;\n int v10;\n double v11;\n double v12;\n long long v13;\n int v14;\n double v15;\n double v16;\n double v18;\n if (a2 <= 1) {\n v2 = *a1;\n } else {\n v2 = *a1;\n v3 = 1LL;\n do {\n v4 = 0;\n v5 = 1.0;\n if ((v3 & 1) == 0 || (v4 = 1, v5 = 0.0, (uint32_t)v3 != 1)) {\n do {\n v4 += 2;\n v5 = v5 * 0.0 * 0.0;\n } while (v4 != (uint32_t)v3);\n }\n v6 = v5 * a1[v3++];\n v2 = v2 + v6;\n } while (a2 != v3);\n }\n v7 = 0LL;\n if (fabs(v2) > 0.000001) {\n if (a2 <= 1) {\n v18 = fabs(*a1);\n while (1) {\n *(double *)&v7 = *(double *)&v7 - v2 / 0.0;\n if (v18 <= 0.000001) break;\n v2 = *a1;\n }\n } else {\n do {\n v8 = 2LL;\n v9 = a1[1] + 0.0;\n if (a2 != 2) {\n do {\n v10 = 2;\n v11 = 1.0 * *(double *)&v7;\n if ((int)v8 > 2) {\n if ((v8 & 1) == 0 ||\n (v11 = v11 * *(double *)&v7, v10 = 3, (int)v8 > 3)) {\n do {\n v10 += 2;\n v11 = v11 * *(double *)&v7 * *(double *)&v7;\n } while (v10 < (int)v8);\n }\n }\n v12 = (double)(int)v8 * a1[v8];\n ++v8;\n v9 = v9 + v11 * v12;\n } while (a2 > (int)v8);\n }\n v13 = 1LL;\n *(double *)&v7 = *(double *)&v7 - v2 / v9;\n v2 = *a1;\n do {\n v14 = 0;\n v15 = 1.0;\n if ((v13 & 1) == 0 ||\n (v14 = 1, v15 = *(double *)&v7, (uint32_t)v13 != 1)) {\n do {\n v14 += 2;\n v15 = v15 * *(double *)&v7 * *(double *)&v7;\n } while (v14 != (uint32_t)v13);\n }\n v16 = v15 * a1[v13++];\n v2 = v2 + v16;\n } while (v13 != a2);\n } while (fabs(v2) > 0.000001);\n }\n }\n return v7;\n}" + }, + { + "index": "HumanEval-C-33", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(int *l, int size, int *out) {\n int *third = malloc((size / 3 + 1) * sizeof(int));\n int i, k = 0, third_size = 0;\n for (i = 0; i * 3 < size; i++) {\n third[i] = l[i * 3];\n third_size++;\n }\n for (i = 0; i < third_size - 1; i++) {\n int min_idx = i;\n for (k = i + 1; k < third_size; k++) {\n if (third[k] < third[min_idx]) min_idx = k;\n }\n if (min_idx != i) {\n int temp = third[i];\n third[i] = third[min_idx];\n third[min_idx] = temp;\n }\n }\n for (i = 0; i < size; i++) {\n if (i % 3 == 0) {\n out[i] = third[i / 3];\n } else {\n out[i] = l[i];\n }\n }\n free(third);\n}", + "test": "#include \n#include \n\n\nint issame(int *a, int *b, int size) {\n for (int i = 0; i < size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int test1[] = {1, 2, 3};\n int result1[3];\n func0(test1, 3, result1);\n assert(issame(result1, result1, 3));\n\n int test2[] = {5, 3, -5, 2, -3, 3, 9, 0, 123, 1, -10};\n int result2[11];\n func0(test2, 11, result2);\n assert(issame(result2, result2, 11));\n\n int test3[] = {5, 8, -12, 4, 23, 2, 3, 11, 12, -10};\n int result3[10];\n func0(test3, 10, result3);\n assert(issame(result3, result3, 10));\n\n int test4[] = {5, 6, 3, 4, 8, 9, 2};\n int correct4[] = {2, 6, 3, 4, 8, 9, 5};\n int result4[7];\n func0(test4, 7, result4);\n assert(issame(result4, correct4, 7));\n\n int test5[] = {5, 8, 3, 4, 6, 9, 2};\n int correct5[] = {2, 8, 3, 4, 6, 9, 5};\n int result5[7];\n func0(test5, 7, result5);\n assert(issame(result5, correct5, 7));\n\n int test6[] = {5, 6, 9, 4, 8, 3, 2};\n int correct6[] = {2, 6, 9, 4, 8, 3, 5};\n int result6[7];\n func0(test6, 7, result6);\n assert(issame(result6, correct6, 7));\n\n int test7[] = {5, 6, 3, 4, 8, 9, 2, 1};\n int correct7[] = {2, 6, 3, 4, 8, 9, 5, 1};\n int result7[8];\n func0(test7, 8, result7);\n assert(issame(result7, correct7, 8));\n\n printf(\"All tests passed!\\n\");\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmov eax, [rbp+var_2C]\nmovsxd rdx, eax\nimul rdx, 55555556h\nshr rdx, 20h\nsar eax, 1Fh\nsub edx, eax\nlea eax, [rdx+1]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\nmov [rbp+var_1C], 0\njmp short loc_125D\nloc_1222:\nmov edx, [rbp+var_1C]\nmov eax, edx\nadd eax, eax\nadd eax, edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+ptr]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_14], 1\nadd [rbp+var_1C], 1\nloc_125D:\nmov edx, [rbp+var_1C]\nmov eax, edx\nadd eax, eax\nadd eax, edx\ncmp [rbp+var_2C], eax\njg short loc_1222\nmov [rbp+var_1C], 0\njmp loc_1335\nloc_1277:\nmov eax, [rbp+var_1C]\nmov [rbp+var_10], eax\nmov eax, [rbp+var_1C]\nadd eax, 1\nmov [rbp+var_18], eax\njmp short loc_12C2\nloc_1288:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njge short loc_12BE\nmov eax, [rbp+var_18]\nmov [rbp+var_10], eax\nloc_12BE:\nadd [rbp+var_18], 1\nloc_12C2:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_14]\njl short loc_1288\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_1C]\njz short loc_1331\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+ptr]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov eax, [rbp+var_C]\nmov [rdx], eax\nloc_1331:\nadd [rbp+var_1C], 1\nloc_1335:\nmov eax, [rbp+var_14]\nsub eax, 1\ncmp [rbp+var_1C], eax\njl loc_1277\nmov [rbp+var_1C], 0\njmp loc_13ED\nloc_1350:\nmov ecx, [rbp+var_1C]\nmovsxd rax, ecx\nimul rax, 55555556h\nshr rax, 20h\nmov rdx, rax\nmov eax, ecx\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\nadd eax, eax\nadd eax, edx\nsub ecx, eax\nmov edx, ecx\ntest edx, edx\njnz short loc_13BC\nmov eax, [rbp+var_1C]\nmovsxd rdx, eax\nimul rdx, 55555556h\nshr rdx, 20h\nsar eax, 1Fh\nsub edx, eax\nmovsxd rax, edx\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_38]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\njmp short loc_13E9\nloc_13BC:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_38]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nloc_13E9:\nadd [rbp+var_1C], 1\nloc_13ED:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_2C]\njl loc_1350\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nnop\nleave\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2, __int64 a3)\n{\n int v3; // eax\n int i; // [rsp+24h] [rbp-1Ch]\n int j; // [rsp+24h] [rbp-1Ch]\n int m; // [rsp+24h] [rbp-1Ch]\n int k; // [rsp+28h] [rbp-18h]\n int v9; // [rsp+2Ch] [rbp-14h]\n int v10; // [rsp+30h] [rbp-10h]\n int v11; // [rsp+34h] [rbp-Ch]\n _DWORD *ptr; // [rsp+38h] [rbp-8h]\n\n ptr = malloc(4LL * (a2 / 3 + 1));\n v9 = 0;\n for ( i = 0; a2 > 3 * i; ++i )\n {\n ptr[i] = *(_DWORD *)(12LL * i + a1);\n ++v9;\n }\n for ( j = 0; j < v9 - 1; ++j )\n {\n v10 = j;\n for ( k = j + 1; k < v9; ++k )\n {\n if ( ptr[k] < ptr[v10] )\n v10 = k;\n }\n if ( v10 != j )\n {\n v11 = ptr[j];\n ptr[j] = ptr[v10];\n ptr[v10] = v11;\n }\n }\n for ( m = 0; m < a2; ++m )\n {\n if ( m % 3 )\n v3 = *(_DWORD *)(4LL * m + a1);\n else\n v3 = ptr[m / 3];\n *(_DWORD *)(4LL * m + a3) = v3;\n }\n free(ptr);\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmov eax, [rbp+var_2C]\nmovsxd rdx, eax\nimul rdx, 55555556h\nshr rdx, 20h\nsar eax, 1Fh\nsub edx, eax\nlea eax, [rdx+1]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\nmov [rbp+var_1C], 0\njmp short loc_125D\nloc_1222:\nmov edx, [rbp+var_1C]\nmov eax, edx\nadd eax, eax\nadd eax, edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+ptr]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_14], 1\nadd [rbp+var_1C], 1\nloc_125D:\nmov edx, [rbp+var_1C]\nmov eax, edx\nadd eax, eax\nadd eax, edx\ncmp [rbp+var_2C], eax\njg short loc_1222\nmov [rbp+var_1C], 0\njmp loc_1335\nloc_1277:\nmov eax, [rbp+var_1C]\nmov [rbp+var_10], eax\nmov eax, [rbp+var_1C]\nadd eax, 1\nmov [rbp+var_18], eax\njmp short loc_12C2\nloc_1288:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njge short loc_12BE\nmov eax, [rbp+var_18]\nmov [rbp+var_10], eax\nloc_12BE:\nadd [rbp+var_18], 1\nloc_12C2:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_14]\njl short loc_1288\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_1C]\njz short loc_1331\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+ptr]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov eax, [rbp+var_C]\nmov [rdx], eax\nloc_1331:\nadd [rbp+var_1C], 1\nloc_1335:\nmov eax, [rbp+var_14]\nsub eax, 1\ncmp [rbp+var_1C], eax\njl loc_1277\nmov [rbp+var_1C], 0\njmp loc_13ED\nloc_1350:\nmov ecx, [rbp+var_1C]\nmovsxd rax, ecx\nimul rax, 55555556h\nshr rax, 20h\nmov rdx, rax\nmov eax, ecx\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\nadd eax, eax\nadd eax, edx\nsub ecx, eax\nmov edx, ecx\ntest edx, edx\njnz short loc_13BC\nmov eax, [rbp+var_1C]\nmovsxd rdx, eax\nimul rdx, 55555556h\nshr rdx, 20h\nsar eax, 1Fh\nsub edx, eax\nmovsxd rax, edx\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_38]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\njmp short loc_13E9\nloc_13BC:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_38]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nloc_13E9:\nadd [rbp+var_1C], 1\nloc_13ED:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_2C]\njl loc_1350\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nnop\nleave\nretn", + "ida_strip_pseudo": "void __fastcall sub_11C9(__int64 a1, int a2, __int64 a3)\n{\n int v3; // eax\n int i; // [rsp+24h] [rbp-1Ch]\n int j; // [rsp+24h] [rbp-1Ch]\n int m; // [rsp+24h] [rbp-1Ch]\n int k; // [rsp+28h] [rbp-18h]\n int v9; // [rsp+2Ch] [rbp-14h]\n int v10; // [rsp+30h] [rbp-10h]\n int v11; // [rsp+34h] [rbp-Ch]\n _DWORD *ptr; // [rsp+38h] [rbp-8h]\n\n ptr = malloc(4LL * (a2 / 3 + 1));\n v9 = 0;\n for ( i = 0; a2 > 3 * i; ++i )\n {\n ptr[i] = *(_DWORD *)(12LL * i + a1);\n ++v9;\n }\n for ( j = 0; j < v9 - 1; ++j )\n {\n v10 = j;\n for ( k = j + 1; k < v9; ++k )\n {\n if ( ptr[k] < ptr[v10] )\n v10 = k;\n }\n if ( v10 != j )\n {\n v11 = ptr[j];\n ptr[j] = ptr[v10];\n ptr[v10] = v11;\n }\n }\n for ( m = 0; m < a2; ++m )\n {\n if ( m % 3 )\n v3 = *(_DWORD *)(4LL * m + a1);\n else\n v3 = ptr[m / 3];\n *(_DWORD *)(4LL * m + a3) = v3;\n }\n free(ptr);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_11C9(long long a1, int a2, long long a3) {\n int v3;\n int i;\n int j;\n int m;\n int k;\n int v9;\n int v10;\n int v11;\n uint32_t *ptr;\n ptr = malloc(4LL * (a2 / 3 + 1));\n v9 = 0;\n for (i = 0; a2 > 3 * i; ++i) {\n ptr[i] = *(uint32_t *)(12LL * i + a1);\n ++v9;\n }\n for (j = 0; j < v9 - 1; ++j) {\n v10 = j;\n for (k = j + 1; k < v9; ++k) {\n if (ptr[k] < ptr[v10]) v10 = k;\n }\n if (v10 != j) {\n v11 = ptr[j];\n ptr[j] = ptr[v10];\n ptr[v10] = v11;\n }\n }\n for (m = 0; m < a2; ++m) {\n if (m % 3)\n v3 = *(uint32_t *)(4LL * m + a1);\n else\n v3 = ptr[m / 3];\n *(uint32_t *)(4LL * m + a3) = v3;\n }\n free(ptr);\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2, long long a3) {\n int v3;\n int i;\n int j;\n int m;\n int k;\n int v9;\n int v10;\n int v11;\n uint32_t *ptr;\n ptr = malloc(4LL * (a2 / 3 + 1));\n v9 = 0;\n for (i = 0; a2 > 3 * i; ++i) {\n ptr[i] = *(uint32_t *)(12LL * i + a1);\n ++v9;\n }\n for (j = 0; j < v9 - 1; ++j) {\n v10 = j;\n for (k = j + 1; k < v9; ++k) {\n if (ptr[k] < ptr[v10]) v10 = k;\n }\n if (v10 != j) {\n v11 = ptr[j];\n ptr[j] = ptr[v10];\n ptr[v10] = v11;\n }\n }\n for (m = 0; m < a2; ++m) {\n if (m % 3)\n v3 = *(uint32_t *)(4LL * m + a1);\n else\n v3 = ptr[m / 3];\n *(uint32_t *)(4LL * m + a3) = v3;\n }\n free(ptr);\n}" + }, + { + "index": "HumanEval-C-33", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(int *l, int size, int *out) {\n int *third = malloc((size / 3 + 1) * sizeof(int));\n int i, k = 0, third_size = 0;\n for (i = 0; i * 3 < size; i++) {\n third[i] = l[i * 3];\n third_size++;\n }\n for (i = 0; i < third_size - 1; i++) {\n int min_idx = i;\n for (k = i + 1; k < third_size; k++) {\n if (third[k] < third[min_idx]) min_idx = k;\n }\n if (min_idx != i) {\n int temp = third[i];\n third[i] = third[min_idx];\n third[min_idx] = temp;\n }\n }\n for (i = 0; i < size; i++) {\n if (i % 3 == 0) {\n out[i] = third[i / 3];\n } else {\n out[i] = l[i];\n }\n }\n free(third);\n}", + "test": "#include \n#include \n\n\nint issame(int *a, int *b, int size) {\n for (int i = 0; i < size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int test1[] = {1, 2, 3};\n int result1[3];\n func0(test1, 3, result1);\n assert(issame(result1, result1, 3));\n\n int test2[] = {5, 3, -5, 2, -3, 3, 9, 0, 123, 1, -10};\n int result2[11];\n func0(test2, 11, result2);\n assert(issame(result2, result2, 11));\n\n int test3[] = {5, 8, -12, 4, 23, 2, 3, 11, 12, -10};\n int result3[10];\n func0(test3, 10, result3);\n assert(issame(result3, result3, 10));\n\n int test4[] = {5, 6, 3, 4, 8, 9, 2};\n int correct4[] = {2, 6, 3, 4, 8, 9, 5};\n int result4[7];\n func0(test4, 7, result4);\n assert(issame(result4, correct4, 7));\n\n int test5[] = {5, 8, 3, 4, 6, 9, 2};\n int correct5[] = {2, 8, 3, 4, 6, 9, 5};\n int result5[7];\n func0(test5, 7, result5);\n assert(issame(result5, correct5, 7));\n\n int test6[] = {5, 6, 9, 4, 8, 3, 2};\n int correct6[] = {2, 6, 9, 4, 8, 3, 5};\n int result6[7];\n func0(test6, 7, result6);\n assert(issame(result6, correct6, 7));\n\n int test7[] = {5, 6, 3, 4, 8, 9, 2, 1};\n int correct7[] = {2, 6, 3, 4, 8, 9, 5, 1};\n int result7[8];\n func0(test7, 8, result7);\n assert(issame(result7, correct7, 8));\n\n printf(\"All tests passed!\\n\");\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbp, rdi\nmov ebx, esi\nmov r12, rdx\nmovsxd rdi, esi\nimul rdi, 55555556h\nshr rdi, 20h\nmov eax, esi\nsar eax, 1Fh\nsub edi, eax\nadd edi, 1\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov rdi, rax; ptr\ntest ebx, ebx\njle loc_12DB\nmov rcx, rax\nmov eax, 0\nmov edx, 0\nloc_1215:\nmov esi, [rbp+rax*4+0]\nmov [rcx], esi\nmov r9d, edx\nadd edx, 1\nadd rax, 3\nadd rcx, 4\ncmp ebx, eax\njg short loc_1215\ncmp edx, 1\njle loc_12E5\nmov r8d, 0\njmp short loc_124B\nloc_123E:\nadd r8, 1\ncmp r9d, r8d\njle loc_12E5\nloc_124B:\nmov edx, r8d\nmov r10d, r8d\ncmp r8d, r9d\njge short loc_123E\nlea rax, [r8+1]\nmov esi, r9d\nsub esi, r8d\nadd rsi, rax\nloc_1263:\nmovsxd rcx, edx\nmov ecx, [rdi+rcx*4]\ncmp [rdi+rax*4], ecx\ncmovl edx, eax\nadd rax, 1\ncmp rax, rsi\njnz short loc_1263\ncmp edx, r10d\njz short loc_123E\nmov ecx, [rdi+r8*4]\nmovsxd rdx, edx\nlea rax, [rdi+rdx*4]\nmov edx, [rax]\nmov [rdi+r8*4], edx\nmov [rax], ecx\njmp short loc_123E\nloc_1292:\nmov eax, [rbp+rdx*4+0]\nloc_1296:\nmov [r12+rdx*4], eax\nadd rdx, 1\ncmp rbx, rdx\njz short loc_12DB\nloc_12A3:\nmovsxd rax, edx\nimul rax, 55555556h\nshr rax, 20h\nmov ecx, edx\nsar ecx, 1Fh\nsub eax, ecx\nlea eax, [rax+rax*2]\ncmp eax, edx\njnz short loc_1292\nmovsxd rax, edx\nimul rax, 55555556h\nshr rax, 20h\nmov ecx, edx\nsar ecx, 1Fh\nsub eax, ecx\ncdqe\nmov eax, [rdi+rax*4]\njmp short loc_1296\nloc_12DB:\ncall _free\npop rbx\npop rbp\npop r12\nretn\nloc_12E5:\nmovsxd rbx, ebx\nmov edx, 0\njmp short loc_12A3", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2, __int64 a3)\n{\n _DWORD *v5; // rax\n _DWORD *v6; // rdi\n _DWORD *v7; // rcx\n __int64 v8; // rax\n int v9; // edx\n int v10; // r9d\n __int64 v11; // r8\n int v12; // edx\n __int64 v13; // rax\n int v14; // ecx\n _DWORD *v15; // rax\n int v16; // eax\n __int64 i; // rdx\n\n v5 = malloc(4LL * (a2 / 3 + 1));\n v6 = v5;\n if ( a2 > 0 )\n {\n v7 = v5;\n v8 = 0LL;\n v9 = 0;\n do\n {\n *v7 = *(_DWORD *)(a1 + 4 * v8);\n v10 = v9++;\n v8 += 3LL;\n ++v7;\n }\n while ( a2 > (int)v8 );\n if ( v9 > 1 )\n {\n v11 = 0LL;\n do\n {\n v12 = v11;\n if ( (int)v11 < v10 )\n {\n v13 = v11 + 1;\n do\n {\n if ( v6[v13] < v6[v12] )\n v12 = v13;\n ++v13;\n }\n while ( v13 != v11 + 1 + (unsigned int)(v10 - v11) );\n if ( v12 != (_DWORD)v11 )\n {\n v14 = v6[v11];\n v15 = &v6[v12];\n v6[v11] = *v15;\n *v15 = v14;\n }\n }\n ++v11;\n }\n while ( v10 > (int)v11 );\n }\n for ( i = 0LL; i != a2; *(_DWORD *)(a3 + 4 * i++) = v16 )\n {\n if ( 3 * ((int)i / 3) == (_DWORD)i )\n v16 = v6[(int)i / 3];\n else\n v16 = *(_DWORD *)(a1 + 4 * i);\n }\n }\n free(v6);\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbp, rdi\nmov ebx, esi\nmov r12, rdx\nmovsxd rdi, esi\nimul rdi, 55555556h\nshr rdi, 20h\nmov eax, esi\nsar eax, 1Fh\nsub edi, eax\nadd edi, 1\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov rdi, rax; ptr\ntest ebx, ebx\njle loc_12DB\nmov rcx, rax\nmov eax, 0\nmov edx, 0\nloc_1215:\nmov esi, [rbp+rax*4+0]\nmov [rcx], esi\nmov r9d, edx\nadd edx, 1\nadd rax, 3\nadd rcx, 4\ncmp ebx, eax\njg short loc_1215\ncmp edx, 1\njle loc_12E5\nmov r8d, 0\njmp short loc_124B\nloc_123E:\nadd r8, 1\ncmp r9d, r8d\njle loc_12E5\nloc_124B:\nmov edx, r8d\nmov r10d, r8d\ncmp r8d, r9d\njge short loc_123E\nlea rax, [r8+1]\nmov esi, r9d\nsub esi, r8d\nadd rsi, rax\nloc_1263:\nmovsxd rcx, edx\nmov ecx, [rdi+rcx*4]\ncmp [rdi+rax*4], ecx\ncmovl edx, eax\nadd rax, 1\ncmp rax, rsi\njnz short loc_1263\ncmp edx, r10d\njz short loc_123E\nmov ecx, [rdi+r8*4]\nmovsxd rdx, edx\nlea rax, [rdi+rdx*4]\nmov edx, [rax]\nmov [rdi+r8*4], edx\nmov [rax], ecx\njmp short loc_123E\nloc_1292:\nmov eax, [rbp+rdx*4+0]\nloc_1296:\nmov [r12+rdx*4], eax\nadd rdx, 1\ncmp rbx, rdx\njz short loc_12DB\nloc_12A3:\nmovsxd rax, edx\nimul rax, 55555556h\nshr rax, 20h\nmov ecx, edx\nsar ecx, 1Fh\nsub eax, ecx\nlea eax, [rax+rax*2]\ncmp eax, edx\njnz short loc_1292\nmovsxd rax, edx\nimul rax, 55555556h\nshr rax, 20h\nmov ecx, edx\nsar ecx, 1Fh\nsub eax, ecx\ncdqe\nmov eax, [rdi+rax*4]\njmp short loc_1296\nloc_12DB:\ncall _free\npop rbx\npop rbp\npop r12\nretn\nloc_12E5:\nmovsxd rbx, ebx\nmov edx, 0\njmp short loc_12A3", + "ida_strip_pseudo": "void __fastcall sub_11C9(__int64 a1, int a2, __int64 a3)\n{\n _DWORD *v5; // rax\n _DWORD *v6; // rdi\n _DWORD *v7; // rcx\n __int64 v8; // rax\n int v9; // edx\n int v10; // r9d\n __int64 v11; // r8\n int v12; // edx\n __int64 v13; // rax\n int v14; // ecx\n _DWORD *v15; // rax\n int v16; // eax\n __int64 i; // rdx\n\n v5 = malloc(4LL * (a2 / 3 + 1));\n v6 = v5;\n if ( a2 > 0 )\n {\n v7 = v5;\n v8 = 0LL;\n v9 = 0;\n do\n {\n *v7 = *(_DWORD *)(a1 + 4 * v8);\n v10 = v9++;\n v8 += 3LL;\n ++v7;\n }\n while ( a2 > (int)v8 );\n if ( v9 > 1 )\n {\n v11 = 0LL;\n do\n {\n v12 = v11;\n if ( (int)v11 < v10 )\n {\n v13 = v11 + 1;\n do\n {\n if ( v6[v13] < v6[v12] )\n v12 = v13;\n ++v13;\n }\n while ( v13 != v11 + 1 + (unsigned int)(v10 - v11) );\n if ( v12 != (_DWORD)v11 )\n {\n v14 = v6[v11];\n v15 = &v6[v12];\n v6[v11] = *v15;\n *v15 = v14;\n }\n }\n ++v11;\n }\n while ( v10 > (int)v11 );\n }\n for ( i = 0LL; i != a2; *(_DWORD *)(a3 + 4 * i++) = v16 )\n {\n if ( 3 * ((int)i / 3) == (_DWORD)i )\n v16 = v6[(int)i / 3];\n else\n v16 = *(_DWORD *)(a1 + 4 * i);\n }\n }\n free(v6);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_11C9(long long a1, int a2, long long a3) {\n uint32_t *v5;\n uint32_t *v6;\n uint32_t *v7;\n long long v8;\n int v9;\n int v10;\n long long v11;\n int v12;\n long long v13;\n int v14;\n uint32_t *v15;\n int v16;\n long long i;\n v5 = malloc(4LL * (a2 / 3 + 1));\n v6 = v5;\n if (a2 > 0) {\n v7 = v5;\n v8 = 0LL;\n v9 = 0;\n do {\n *v7 = *(uint32_t *)(a1 + 4 * v8);\n v10 = v9++;\n v8 += 3LL;\n ++v7;\n } while (a2 > (int)v8);\n if (v9 > 1) {\n v11 = 0LL;\n do {\n v12 = v11;\n if ((int)v11 < v10) {\n v13 = v11 + 1;\n do {\n if (v6[v13] < v6[v12]) v12 = v13;\n ++v13;\n } while (v13 != v11 + 1 + (unsigned int)(v10 - v11));\n if (v12 != (uint32_t)v11) {\n v14 = v6[v11];\n v15 = &v6[v12];\n v6[v11] = *v15;\n *v15 = v14;\n }\n }\n ++v11;\n } while (v10 > (int)v11);\n }\n for (i = 0LL; i != a2; *(uint32_t *)(a3 + 4 * i++) = v16) {\n if (3 * ((int)i / 3) == (uint32_t)i)\n v16 = v6[(int)i / 3];\n else\n v16 = *(uint32_t *)(a1 + 4 * i);\n }\n }\n free(v6);\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2, long long a3) {\n uint32_t *v5;\n uint32_t *v6;\n uint32_t *v7;\n long long v8;\n int v9;\n int v10;\n long long v11;\n int v12;\n long long v13;\n int v14;\n uint32_t *v15;\n int v16;\n long long i;\n v5 = malloc(4LL * (a2 / 3 + 1));\n v6 = v5;\n if (a2 > 0) {\n v7 = v5;\n v8 = 0LL;\n v9 = 0;\n do {\n *v7 = *(uint32_t *)(a1 + 4 * v8);\n v10 = v9++;\n v8 += 3LL;\n ++v7;\n } while (a2 > (int)v8);\n if (v9 > 1) {\n v11 = 0LL;\n do {\n v12 = v11;\n if ((int)v11 < v10) {\n v13 = v11 + 1;\n do {\n if (v6[v13] < v6[v12]) v12 = v13;\n ++v13;\n } while (v13 != v11 + 1 + (unsigned int)(v10 - v11));\n if (v12 != (uint32_t)v11) {\n v14 = v6[v11];\n v15 = &v6[v12];\n v6[v11] = *v15;\n *v15 = v14;\n }\n }\n ++v11;\n } while (v10 > (int)v11);\n }\n for (i = 0LL; i != a2; *(uint32_t *)(a3 + 4 * i++) = v16) {\n if (3 * ((int)i / 3) == (uint32_t)i)\n v16 = v6[(int)i / 3];\n else\n v16 = *(uint32_t *)(a1 + 4 * i);\n }\n }\n free(v6);\n}" + }, + { + "index": "HumanEval-C-33", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(int *l, int size, int *out) {\n int *third = malloc((size / 3 + 1) * sizeof(int));\n int i, k = 0, third_size = 0;\n for (i = 0; i * 3 < size; i++) {\n third[i] = l[i * 3];\n third_size++;\n }\n for (i = 0; i < third_size - 1; i++) {\n int min_idx = i;\n for (k = i + 1; k < third_size; k++) {\n if (third[k] < third[min_idx]) min_idx = k;\n }\n if (min_idx != i) {\n int temp = third[i];\n third[i] = third[min_idx];\n third[min_idx] = temp;\n }\n }\n for (i = 0; i < size; i++) {\n if (i % 3 == 0) {\n out[i] = third[i / 3];\n } else {\n out[i] = l[i];\n }\n }\n free(third);\n}", + "test": "#include \n#include \n\n\nint issame(int *a, int *b, int size) {\n for (int i = 0; i < size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int test1[] = {1, 2, 3};\n int result1[3];\n func0(test1, 3, result1);\n assert(issame(result1, result1, 3));\n\n int test2[] = {5, 3, -5, 2, -3, 3, 9, 0, 123, 1, -10};\n int result2[11];\n func0(test2, 11, result2);\n assert(issame(result2, result2, 11));\n\n int test3[] = {5, 8, -12, 4, 23, 2, 3, 11, 12, -10};\n int result3[10];\n func0(test3, 10, result3);\n assert(issame(result3, result3, 10));\n\n int test4[] = {5, 6, 3, 4, 8, 9, 2};\n int correct4[] = {2, 6, 3, 4, 8, 9, 5};\n int result4[7];\n func0(test4, 7, result4);\n assert(issame(result4, correct4, 7));\n\n int test5[] = {5, 8, 3, 4, 6, 9, 2};\n int correct5[] = {2, 8, 3, 4, 6, 9, 5};\n int result5[7];\n func0(test5, 7, result5);\n assert(issame(result5, correct5, 7));\n\n int test6[] = {5, 6, 9, 4, 8, 3, 2};\n int correct6[] = {2, 6, 9, 4, 8, 3, 5};\n int result6[7];\n func0(test6, 7, result6);\n assert(issame(result6, correct6, 7));\n\n int test7[] = {5, 6, 3, 4, 8, 9, 2, 1};\n int correct7[] = {2, 6, 3, 4, 8, 9, 5, 1};\n int result7[8];\n func0(test7, 8, result7);\n assert(issame(result7, correct7, 8));\n\n printf(\"All tests passed!\\n\");\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\nmovsxd r12, esi\npush rbp\nmov eax, r12d\nmov rbp, rdx\npush rbx\nmov rbx, rdi\nimul rdi, r12, 55555556h\nsar eax, 1Fh\nshr rdi, 20h\nsub rsp, 8\nsub edi, eax\nadd edi, 1\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov rdi, rax; ptr\ntest r12d, r12d\njle loc_1698\nmov rdx, rax\nmov r13, r12\nxor eax, eax\nxor ecx, ecx\nnop\nloc_15D0:\nmov esi, [rbx+rax*4]\nadd rax, 3\nmov r9d, ecx\nadd rdx, 4\nlea ecx, [rcx+1]\nmov [rdx-4], esi\ncmp r13d, eax\njg short loc_15D0\nxor r8d, r8d\ncmp ecx, 1\njz short loc_164F\nnop dword ptr [rax+00000000h]\nloc_15F8:\nmov edx, r8d\nmov r11d, r8d\nlea r10, [r8+1]\ncmp r8d, r9d\njge short loc_1647\nmov esi, r9d\nmov rax, r10\nsub esi, r8d\nadd rsi, r10\nnop dword ptr [rax+rax+00h]\nloc_1618:\nmovsxd rcx, edx\nmov r13d, [rdi+rax*4]\ncmp [rdi+rcx*4], r13d\ncmovg edx, eax\nadd rax, 1\ncmp rax, rsi\njnz short loc_1618\ncmp edx, r11d\njz short loc_1647\nmovsxd rdx, edx\nmov ecx, [rdi+r8*4]\nlea rax, [rdi+rdx*4]\nmov edx, [rax]\nmov [rdi+r8*4], edx\nmov [rax], ecx\nloc_1647:\nmov r8, r10\ncmp r9d, r10d\njg short loc_15F8\nloc_164F:\nxor eax, eax\nmov ecx, 0AAAAAAABh\njmp short loc_167A\nloc_1660:\nmov edx, eax\nimul rdx, rcx\nshr rdx, 21h\nmov edx, [rdi+rdx*4]\nmov [rbp+rax*4+0], edx\nadd rax, 1\ncmp r12, rax\njz short loc_1698\nloc_167A:\nimul edx, eax, 0AAAAAAABh\ncmp edx, 55555555h\njbe short loc_1660\nmov edx, [rbx+rax*4]\nmov [rbp+rax*4+0], edx\nadd rax, 1\ncmp r12, rax\njnz short loc_167A\nloc_1698:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\njmp _free", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2, __int64 a3)\n{\n __int64 v3; // r12\n _DWORD *v6; // rax\n _DWORD *v7; // rdi\n _DWORD *v8; // rdx\n __int64 v9; // rax\n int v10; // ecx\n int v11; // esi\n int v12; // r9d\n __int64 v13; // r8\n int v14; // edx\n __int64 v15; // r10\n __int64 v16; // rax\n int v17; // ecx\n _DWORD *v18; // rax\n __int64 v19; // rax\n\n v3 = a2;\n v6 = malloc(4LL * (a2 / 3 + 1));\n v7 = v6;\n if ( a2 > 0 )\n {\n v8 = v6;\n v9 = 0LL;\n v10 = 0;\n do\n {\n v11 = *(_DWORD *)(a1 + 4 * v9);\n v9 += 3LL;\n v12 = v10;\n ++v8;\n ++v10;\n *(v8 - 1) = v11;\n }\n while ( (int)v3 > (int)v9 );\n v13 = 0LL;\n if ( v10 != 1 )\n {\n do\n {\n v14 = v13;\n v15 = v13 + 1;\n if ( (int)v13 < v12 )\n {\n v16 = v13 + 1;\n do\n {\n if ( v7[v14] > v7[v16] )\n v14 = v16;\n ++v16;\n }\n while ( v16 != v15 + (unsigned int)(v12 - v13) );\n if ( v14 != (_DWORD)v13 )\n {\n v17 = v7[v13];\n v18 = &v7[v14];\n v7[v13] = *v18;\n *v18 = v17;\n }\n }\n ++v13;\n }\n while ( v12 > (int)v15 );\n }\n v19 = 0LL;\n do\n {\n while ( (unsigned int)(-1431655765 * v19) <= 0x55555555 )\n {\n *(_DWORD *)(a3 + 4 * v19) = v7[(unsigned int)v19 / 3uLL];\n if ( v3 == ++v19 )\n goto LABEL_17;\n }\n *(_DWORD *)(a3 + 4 * v19) = *(_DWORD *)(a1 + 4 * v19);\n ++v19;\n }\n while ( v3 != v19 );\n }\nLABEL_17:\n free(v7);\n}", + "ida_strip_asm": "sub_1580:\nendbr64\npush r13\npush r12\nmovsxd r12, esi\npush rbp\nmov eax, r12d\nmov rbp, rdx\npush rbx\nmov rbx, rdi\nimul rdi, r12, 55555556h\nsar eax, 1Fh\nshr rdi, 20h\nsub rsp, 8\nsub edi, eax\nadd edi, 1\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov rdi, rax; ptr\ntest r12d, r12d\njle loc_1698\nmov rdx, rax\nmov r13, r12\nxor eax, eax\nxor ecx, ecx\nnop\nloc_15D0:\nmov esi, [rbx+rax*4]\nadd rax, 3\nmov r9d, ecx\nadd rdx, 4\nlea ecx, [rcx+1]\nmov [rdx-4], esi\ncmp r13d, eax\njg short loc_15D0\nxor r8d, r8d\ncmp ecx, 1\njz short loc_164F\nnop dword ptr [rax+00000000h]\nloc_15F8:\nmov edx, r8d\nmov r11d, r8d\nlea r10, [r8+1]\ncmp r8d, r9d\njge short loc_1647\nmov esi, r9d\nmov rax, r10\nsub esi, r8d\nadd rsi, r10\nnop dword ptr [rax+rax+00h]\nloc_1618:\nmovsxd rcx, edx\nmov r13d, [rdi+rax*4]\ncmp [rdi+rcx*4], r13d\ncmovg edx, eax\nadd rax, 1\ncmp rax, rsi\njnz short loc_1618\ncmp edx, r11d\njz short loc_1647\nmovsxd rdx, edx\nmov ecx, [rdi+r8*4]\nlea rax, [rdi+rdx*4]\nmov edx, [rax]\nmov [rdi+r8*4], edx\nmov [rax], ecx\nloc_1647:\nmov r8, r10\ncmp r9d, r10d\njg short loc_15F8\nloc_164F:\nxor eax, eax\nmov ecx, 0AAAAAAABh\njmp short loc_167A\nloc_1660:\nmov edx, eax\nimul rdx, rcx\nshr rdx, 21h\nmov edx, [rdi+rdx*4]\nmov [rbp+rax*4+0], edx\nadd rax, 1\ncmp r12, rax\njz short loc_1698\nloc_167A:\nimul edx, eax, 0AAAAAAABh\ncmp edx, 55555555h\njbe short loc_1660\nmov edx, [rbx+rax*4]\nmov [rbp+rax*4+0], edx\nadd rax, 1\ncmp r12, rax\njnz short loc_167A\nloc_1698:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\njmp _free", + "ida_strip_pseudo": "void __fastcall sub_1580(__int64 a1, int a2, __int64 a3)\n{\n __int64 v3; // r12\n _DWORD *v6; // rax\n _DWORD *v7; // rdi\n _DWORD *v8; // rdx\n __int64 v9; // rax\n int v10; // ecx\n int v11; // esi\n int v12; // r9d\n __int64 v13; // r8\n int v14; // edx\n __int64 v15; // r10\n __int64 v16; // rax\n int v17; // ecx\n _DWORD *v18; // rax\n __int64 v19; // rax\n\n v3 = a2;\n v6 = malloc(4LL * (a2 / 3 + 1));\n v7 = v6;\n if ( a2 > 0 )\n {\n v8 = v6;\n v9 = 0LL;\n v10 = 0;\n do\n {\n v11 = *(_DWORD *)(a1 + 4 * v9);\n v9 += 3LL;\n v12 = v10;\n ++v8;\n ++v10;\n *(v8 - 1) = v11;\n }\n while ( (int)v3 > (int)v9 );\n v13 = 0LL;\n if ( v10 != 1 )\n {\n do\n {\n v14 = v13;\n v15 = v13 + 1;\n if ( (int)v13 < v12 )\n {\n v16 = v13 + 1;\n do\n {\n if ( v7[v14] > v7[v16] )\n v14 = v16;\n ++v16;\n }\n while ( v16 != v15 + (unsigned int)(v12 - v13) );\n if ( v14 != (_DWORD)v13 )\n {\n v17 = v7[v13];\n v18 = &v7[v14];\n v7[v13] = *v18;\n *v18 = v17;\n }\n }\n ++v13;\n }\n while ( v12 > (int)v15 );\n }\n v19 = 0LL;\n do\n {\n while ( (unsigned int)(-1431655765 * v19) <= 0x55555555 )\n {\n *(_DWORD *)(a3 + 4 * v19) = v7[(unsigned int)v19 / 3uLL];\n if ( v3 == ++v19 )\n goto LABEL_17;\n }\n *(_DWORD *)(a3 + 4 * v19) = *(_DWORD *)(a1 + 4 * v19);\n ++v19;\n }\n while ( v3 != v19 );\n }\nLABEL_17:\n free(v7);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1580(long long a1, int a2, long long a3) {\n long long v3;\n uint32_t *v6;\n uint32_t *v7;\n uint32_t *v8;\n long long v9;\n int v10;\n int v11;\n int v12;\n long long v13;\n int v14;\n long long v15;\n long long v16;\n int v17;\n uint32_t *v18;\n long long v19;\n v3 = a2;\n v6 = malloc(4LL * (a2 / 3 + 1));\n v7 = v6;\n if (a2 > 0) {\n v8 = v6;\n v9 = 0LL;\n v10 = 0;\n do {\n v11 = *(uint32_t *)(a1 + 4 * v9);\n v9 += 3LL;\n v12 = v10;\n ++v8;\n ++v10;\n *(v8 - 1) = v11;\n } while ((int)v3 > (int)v9);\n v13 = 0LL;\n if (v10 != 1) {\n do {\n v14 = v13;\n v15 = v13 + 1;\n if ((int)v13 < v12) {\n v16 = v13 + 1;\n do {\n if (v7[v14] > v7[v16]) v14 = v16;\n ++v16;\n } while (v16 != v15 + (unsigned int)(v12 - v13));\n if (v14 != (uint32_t)v13) {\n v17 = v7[v13];\n v18 = &v7[v14];\n v7[v13] = *v18;\n *v18 = v17;\n }\n }\n ++v13;\n } while (v12 > (int)v15);\n }\n v19 = 0LL;\n do {\n while ((unsigned int)(-1431655765 * v19) <= 1431655765) {\n *(uint32_t *)(a3 + 4 * v19) = v7[(unsigned int)v19 / 3uLL];\n if (v3 == ++v19) goto LABEL_17;\n }\n *(uint32_t *)(a3 + 4 * v19) = *(uint32_t *)(a1 + 4 * v19);\n ++v19;\n } while (v3 != v19);\n }\nLABEL_17:\n free(v7);\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2, long long a3) {\n long long v3;\n uint32_t *v6;\n uint32_t *v7;\n uint32_t *v8;\n long long v9;\n int v10;\n int v11;\n int v12;\n long long v13;\n int v14;\n long long v15;\n long long v16;\n int v17;\n uint32_t *v18;\n long long v19;\n v3 = a2;\n v6 = malloc(4LL * (a2 / 3 + 1));\n v7 = v6;\n if (a2 > 0) {\n v8 = v6;\n v9 = 0LL;\n v10 = 0;\n do {\n v11 = *(uint32_t *)(a1 + 4 * v9);\n v9 += 3LL;\n v12 = v10;\n ++v8;\n ++v10;\n *(v8 - 1) = v11;\n } while ((int)v3 > (int)v9);\n v13 = 0LL;\n if (v10 != 1) {\n do {\n v14 = v13;\n v15 = v13 + 1;\n if ((int)v13 < v12) {\n v16 = v13 + 1;\n do {\n if (v7[v14] > v7[v16]) v14 = v16;\n ++v16;\n } while (v16 != v15 + (unsigned int)(v12 - v13));\n if (v14 != (uint32_t)v13) {\n v17 = v7[v13];\n v18 = &v7[v14];\n v7[v13] = *v18;\n *v18 = v17;\n }\n }\n ++v13;\n } while (v12 > (int)v15);\n }\n v19 = 0LL;\n do {\n while ((unsigned int)(-1431655765 * v19) <= 1431655765) {\n *(uint32_t *)(a3 + 4 * v19) = v7[(unsigned int)v19 / 3uLL];\n if (v3 == ++v19) goto LABEL_17;\n }\n *(uint32_t *)(a3 + 4 * v19) = *(uint32_t *)(a1 + 4 * v19);\n ++v19;\n } while (v3 != v19);\n }\nLABEL_17:\n free(v7);\n}" + }, + { + "index": "HumanEval-C-33", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(int *l, int size, int *out) {\n int *third = malloc((size / 3 + 1) * sizeof(int));\n int i, k = 0, third_size = 0;\n for (i = 0; i * 3 < size; i++) {\n third[i] = l[i * 3];\n third_size++;\n }\n for (i = 0; i < third_size - 1; i++) {\n int min_idx = i;\n for (k = i + 1; k < third_size; k++) {\n if (third[k] < third[min_idx]) min_idx = k;\n }\n if (min_idx != i) {\n int temp = third[i];\n third[i] = third[min_idx];\n third[min_idx] = temp;\n }\n }\n for (i = 0; i < size; i++) {\n if (i % 3 == 0) {\n out[i] = third[i / 3];\n } else {\n out[i] = l[i];\n }\n }\n free(third);\n}", + "test": "#include \n#include \n\n\nint issame(int *a, int *b, int size) {\n for (int i = 0; i < size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int test1[] = {1, 2, 3};\n int result1[3];\n func0(test1, 3, result1);\n assert(issame(result1, result1, 3));\n\n int test2[] = {5, 3, -5, 2, -3, 3, 9, 0, 123, 1, -10};\n int result2[11];\n func0(test2, 11, result2);\n assert(issame(result2, result2, 11));\n\n int test3[] = {5, 8, -12, 4, 23, 2, 3, 11, 12, -10};\n int result3[10];\n func0(test3, 10, result3);\n assert(issame(result3, result3, 10));\n\n int test4[] = {5, 6, 3, 4, 8, 9, 2};\n int correct4[] = {2, 6, 3, 4, 8, 9, 5};\n int result4[7];\n func0(test4, 7, result4);\n assert(issame(result4, correct4, 7));\n\n int test5[] = {5, 8, 3, 4, 6, 9, 2};\n int correct5[] = {2, 8, 3, 4, 6, 9, 5};\n int result5[7];\n func0(test5, 7, result5);\n assert(issame(result5, correct5, 7));\n\n int test6[] = {5, 6, 9, 4, 8, 3, 2};\n int correct6[] = {2, 6, 9, 4, 8, 3, 5};\n int result6[7];\n func0(test6, 7, result6);\n assert(issame(result6, correct6, 7));\n\n int test7[] = {5, 6, 3, 4, 8, 9, 2, 1};\n int correct7[] = {2, 6, 3, 4, 8, 9, 5, 1};\n int result7[8];\n func0(test7, 8, result7);\n assert(issame(result7, correct7, 8));\n\n printf(\"All tests passed!\\n\");\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\nmovsxd r13, esi\npush r12\nmov eax, r13d\nmov r12, rdx\npush rbp\nmov rbp, rdi\nimul rdi, r13, 55555556h\nsar eax, 1Fh\npush rbx\nshr rdi, 20h\nsub edi, eax\nsub rsp, 8\nadd edi, 1\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov r10, rax\ntest r13d, r13d\njle loc_1789\nlea eax, [r13-1]\nmov ecx, 0AAAAAAABh\nmov rbx, r13\nmov rdx, rax\nimul rax, rcx\nmov rcx, rax\nshr rax, 21h\nshr rcx, 20h\nmov rsi, rax\ncmp edx, 0Bh\njbe loc_17C8\nshr rcx, 3\nmov rax, rbp\nmov rdx, r10\nshl rcx, 4\nadd rcx, r10\nnop dword ptr [rax+00h]\nloc_1648:\nmovdqu xmm2, xmmword ptr [rax]\nmovdqu xmm1, xmmword ptr [rax+10h]\nadd rdx, 10h\nadd rax, 30h ; '0'\nmovdqa xmm0, xmm2\nshufps xmm1, xmm2, 0Ah\nshufps xmm0, xmm1, 8Ch\nmovdqu xmm1, xmmword ptr [rax-10h]\nshufps xmm1, xmm0, 0A5h\nshufps xmm0, xmm1, 24h ; '$'\nmovups xmmword ptr [rdx-10h], xmm0\ncmp rdx, rcx\njnz short loc_1648\nmov eax, esi\nand eax, 0FFFFFFFCh\nlea edx, [rax+rax*2]\nloc_1683:\nmovsxd rdx, edx\nmovsxd rsi, eax\nlea r9d, [rax+1]\nmov edx, [rbp+rdx*4+0]\nlea rcx, ds:0[rsi*4]\nmov [r10+rsi*4], edx\nlea edx, [r9+r9*2]\ncmp ebx, edx\njle loc_17B3\nmovsxd rsi, edx\nlea rdi, ds:0[rsi*4]\nmov esi, [rbp+rsi*4+0]\nmov [r10+rcx+4], esi\nlea esi, [rdx+3]\ncmp ebx, esi\njle short loc_16E5\nmov esi, [rbp+rdi+0Ch]\nadd edx, 6\nlea r9d, [rax+3]\nmov [r10+rcx+8], esi\ncmp edx, ebx\njge loc_17D1\nmov eax, [rbp+rdi+18h]\nmov [r10+rcx+0Ch], eax\nloc_16E5:\nlea rbx, [r10+4]\nxor r11d, r11d\nnop dword ptr [rax+00h]\nloc_16F0:\nmov r15d, [rbx-4]\nmov r14d, r11d\nadd r11d, 1\nmov rax, rbx\nmov r8d, r14d\nmov edx, r11d\nmov esi, r15d\njmp short loc_1725\nloc_1710:\nmovsxd rcx, r8d\nadd rax, 4\nlea rdi, [r10+rcx*4]\nlea ecx, [rdx+1]\ncmp edx, r9d\njge short loc_173F\nloc_1723:\nmov edx, ecx\nloc_1725:\nmov ecx, [rax]\nmov rdi, rax\ncmp esi, ecx\njle short loc_1710\nmov esi, ecx\nmov r8d, edx\nlea ecx, [rdx+1]\nadd rax, 4\ncmp edx, r9d\njl short loc_1723\nloc_173F:\ncmp r8d, r14d\njz short loc_174A\nmov [rbx-4], esi\nmov [rdi], r15d\nloc_174A:\nadd rbx, 4\ncmp r11d, r9d\njnz short loc_16F0\nloc_1753:\nxor eax, eax\nmov ecx, 0AAAAAAABh\nnop word ptr [rax+rax+00h]\nloc_1760:\nimul edx, eax, 0AAAAAAABh\ncmp edx, 55555555h\nja short loc_17A0\nmov edx, eax\nimul rdx, rcx\nshr rdx, 21h\nmov edx, [r10+rdx*4]\nmov [r12+rax*4], edx\nadd rax, 1\ncmp rax, r13\njnz short loc_1760\nloc_1789:\nadd rsp, 8\nmov rdi, r10; ptr\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\njmp _free\nloc_17A0:\nmov edx, [rbp+rax*4+0]\nmov [r12+rax*4], edx\nadd rax, 1\ncmp rax, r13\njnz short loc_1760\njmp short loc_1789\nloc_17B3:\ncmp r9d, 1\njz short loc_1753\ntest eax, eax\njle short loc_1753\nmov r9d, eax\njmp loc_16E5\nloc_17C8:\nxor eax, eax\nxor edx, edx\njmp loc_1683\nloc_17D1:\nlea r9d, [rax+2]\njmp loc_16E5", + "ida_pseudo": "void __fastcall func0(const __m128i *a1, int a2, __int64 a3)\n{\n __int64 v3; // r13\n __m128 *v6; // r10\n __int64 v7; // rdx\n unsigned __int64 v8; // rcx\n unsigned int v9; // esi\n const __m128i *v10; // rax\n __m128 *v11; // rdx\n __m128 *v12; // rcx\n __m128 v13; // xmm2\n __m128 v14; // xmm1\n __m128 v15; // xmm0\n signed int v16; // eax\n signed int v17; // edx\n signed int v18; // r9d\n __int64 v19; // rcx\n int v20; // edx\n __int64 v21; // rdi\n __int32 *v22; // rbx\n signed int v23; // r11d\n int v24; // r15d\n int v25; // r14d\n __int32 *v26; // rax\n signed int v27; // r8d\n signed int v28; // edx\n int v29; // esi\n __int32 *v30; // rdi\n signed int v31; // ecx\n __int64 v32; // rax\n\n v3 = a2;\n v6 = (__m128 *)malloc(4LL * (a2 / 3 + 1));\n if ( a2 > 0 )\n {\n v7 = (unsigned int)(a2 - 1);\n v8 = (unsigned __int64)(2863311531LL * v7) >> 32;\n v9 = (a2 - 1) / 3u;\n if ( (unsigned int)v7 <= 0xB )\n {\n v16 = 0;\n v17 = 0;\n }\n else\n {\n v10 = a1;\n v11 = v6;\n v12 = &v6[v8 >> 3];\n do\n {\n v13 = (__m128)_mm_loadu_si128(v10);\n v14 = (__m128)_mm_loadu_si128(v10 + 1);\n ++v11;\n v10 += 3;\n v15 = _mm_shuffle_ps(v13, _mm_shuffle_ps(v14, v13, 10), 140);\n v11[-1] = _mm_shuffle_ps(v15, _mm_shuffle_ps((__m128)_mm_loadu_si128(v10 - 1), v15, 165), 36);\n }\n while ( v11 != v12 );\n v16 = v9 & 0xFFFFFFFC;\n v17 = 3 * (v9 & 0xFFFFFFFC);\n }\n v18 = v16 + 1;\n v19 = v16;\n v6->m128_i32[v19] = a1->m128i_i32[v17];\n v20 = 3 * (v16 + 1);\n if ( (int)v3 > v20 )\n {\n v21 = v20;\n v6->m128_i32[v19 + 1] = a1->m128i_i32[v21];\n if ( (int)v3 > v20 + 3 )\n {\n v18 = v16 + 3;\n v6->m128_i32[v19 + 2] = a1->m128i_i32[v21 + 3];\n if ( v20 + 6 >= (int)v3 )\n v18 = v16 + 2;\n else\n v6->m128_i32[v19 + 3] = a1[1].m128i_i32[v21 + 2];\n }\n goto LABEL_10;\n }\n if ( v16 > 0 )\n {\n v18 = v16;\nLABEL_10:\n v22 = &v6->m128_i32[1];\n v23 = 0;\n do\n {\n v24 = *(v22 - 1);\n v25 = v23++;\n v26 = v22;\n v27 = v25;\n v28 = v23;\n v29 = v24;\n while ( 1 )\n {\n v30 = v26;\n if ( v29 > *v26 )\n break;\n ++v26;\n v30 = &v6->m128_i32[v27];\n v31 = v28 + 1;\n if ( v28 >= v18 )\n goto LABEL_16;\nLABEL_13:\n v28 = v31;\n }\n v29 = *v26;\n v27 = v28;\n v31 = v28 + 1;\n ++v26;\n if ( v28 < v18 )\n goto LABEL_13;\nLABEL_16:\n if ( v27 != v25 )\n {\n *(v22 - 1) = v29;\n *v30 = v24;\n }\n ++v22;\n }\n while ( v23 != v18 );\n }\n v32 = 0LL;\n do\n {\n while ( (unsigned int)(-1431655765 * v32) <= 0x55555555 )\n {\n *(_DWORD *)(a3 + 4 * v32) = v6->m128_i32[(unsigned int)v32 / 3uLL];\n if ( ++v32 == v3 )\n goto LABEL_22;\n }\n *(_DWORD *)(a3 + 4 * v32) = a1->m128i_i32[v32];\n ++v32;\n }\n while ( v32 != v3 );\n }\nLABEL_22:\n free(v6);\n}", + "ida_strip_asm": "sub_15C0:\nendbr64\npush r15\npush r14\npush r13\nmovsxd r13, esi\npush r12\nmov eax, r13d\nmov r12, rdx\npush rbp\nmov rbp, rdi\nimul rdi, r13, 55555556h\nsar eax, 1Fh\npush rbx\nshr rdi, 20h\nsub edi, eax\nsub rsp, 8\nadd edi, 1\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov r10, rax\ntest r13d, r13d\njle loc_1789\nlea eax, [r13-1]\nmov ecx, 0AAAAAAABh\nmov rbx, r13\nmov rdx, rax\nimul rax, rcx\nmov rcx, rax\nshr rax, 21h\nshr rcx, 20h\nmov rsi, rax\ncmp edx, 0Bh\njbe loc_17C8\nshr rcx, 3\nmov rax, rbp\nmov rdx, r10\nshl rcx, 4\nadd rcx, r10\nnop dword ptr [rax+00h]\nloc_1648:\nmovdqu xmm2, xmmword ptr [rax]\nmovdqu xmm1, xmmword ptr [rax+10h]\nadd rdx, 10h\nadd rax, 30h ; '0'\nmovdqa xmm0, xmm2\nshufps xmm1, xmm2, 0Ah\nshufps xmm0, xmm1, 8Ch\nmovdqu xmm1, xmmword ptr [rax-10h]\nshufps xmm1, xmm0, 0A5h\nshufps xmm0, xmm1, 24h ; '$'\nmovups xmmword ptr [rdx-10h], xmm0\ncmp rdx, rcx\njnz short loc_1648\nmov eax, esi\nand eax, 0FFFFFFFCh\nlea edx, [rax+rax*2]\nloc_1683:\nmovsxd rdx, edx\nmovsxd rsi, eax\nlea r9d, [rax+1]\nmov edx, [rbp+rdx*4+0]\nlea rcx, ds:0[rsi*4]\nmov [r10+rsi*4], edx\nlea edx, [r9+r9*2]\ncmp ebx, edx\njle loc_17B3\nmovsxd rsi, edx\nlea rdi, ds:0[rsi*4]\nmov esi, [rbp+rsi*4+0]\nmov [r10+rcx+4], esi\nlea esi, [rdx+3]\ncmp ebx, esi\njle short loc_16E5\nmov esi, [rbp+rdi+0Ch]\nadd edx, 6\nlea r9d, [rax+3]\nmov [r10+rcx+8], esi\ncmp edx, ebx\njge loc_17D1\nmov eax, [rbp+rdi+18h]\nmov [r10+rcx+0Ch], eax\nloc_16E5:\nlea rbx, [r10+4]\nxor r11d, r11d\nnop dword ptr [rax+00h]\nloc_16F0:\nmov r15d, [rbx-4]\nmov r14d, r11d\nadd r11d, 1\nmov rax, rbx\nmov r8d, r14d\nmov edx, r11d\nmov esi, r15d\njmp short loc_1725\nloc_1710:\nmovsxd rcx, r8d\nadd rax, 4\nlea rdi, [r10+rcx*4]\nlea ecx, [rdx+1]\ncmp edx, r9d\njge short loc_173F\nloc_1723:\nmov edx, ecx\nloc_1725:\nmov ecx, [rax]\nmov rdi, rax\ncmp esi, ecx\njle short loc_1710\nmov esi, ecx\nmov r8d, edx\nlea ecx, [rdx+1]\nadd rax, 4\ncmp edx, r9d\njl short loc_1723\nloc_173F:\ncmp r8d, r14d\njz short loc_174A\nmov [rbx-4], esi\nmov [rdi], r15d\nloc_174A:\nadd rbx, 4\ncmp r11d, r9d\njnz short loc_16F0\nloc_1753:\nxor eax, eax\nmov ecx, 0AAAAAAABh\nnop word ptr [rax+rax+00h]\nloc_1760:\nimul edx, eax, 0AAAAAAABh\ncmp edx, 55555555h\nja short loc_17A0\nmov edx, eax\nimul rdx, rcx\nshr rdx, 21h\nmov edx, [r10+rdx*4]\nmov [r12+rax*4], edx\nadd rax, 1\ncmp rax, r13\njnz short loc_1760\nloc_1789:\nadd rsp, 8\nmov rdi, r10; ptr\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\njmp _free\nloc_17A0:\nmov edx, [rbp+rax*4+0]\nmov [r12+rax*4], edx\nadd rax, 1\ncmp rax, r13\njnz short loc_1760\njmp short loc_1789\nloc_17B3:\ncmp r9d, 1\njz short loc_1753\ntest eax, eax\njle short loc_1753\nmov r9d, eax\njmp loc_16E5\nloc_17C8:\nxor eax, eax\nxor edx, edx\njmp loc_1683\nloc_17D1:\nlea r9d, [rax+2]\njmp loc_16E5", + "ida_strip_pseudo": "void __fastcall sub_15C0(const __m128i *a1, int a2, __int64 a3)\n{\n __int64 v3; // r13\n __m128 *v6; // r10\n __int64 v7; // rdx\n unsigned __int64 v8; // rcx\n unsigned int v9; // esi\n const __m128i *v10; // rax\n __m128 *v11; // rdx\n __m128 *v12; // rcx\n __m128 v13; // xmm2\n __m128 v14; // xmm1\n __m128 v15; // xmm0\n signed int v16; // eax\n signed int v17; // edx\n signed int v18; // r9d\n __int64 v19; // rcx\n int v20; // edx\n __int64 v21; // rdi\n __int32 *v22; // rbx\n signed int v23; // r11d\n int v24; // r15d\n int v25; // r14d\n __int32 *v26; // rax\n signed int v27; // r8d\n signed int v28; // edx\n int v29; // esi\n __int32 *v30; // rdi\n signed int v31; // ecx\n __int64 v32; // rax\n\n v3 = a2;\n v6 = (__m128 *)malloc(4LL * (a2 / 3 + 1));\n if ( a2 > 0 )\n {\n v7 = (unsigned int)(a2 - 1);\n v8 = (unsigned __int64)(2863311531LL * v7) >> 32;\n v9 = (a2 - 1) / 3u;\n if ( (unsigned int)v7 <= 0xB )\n {\n v16 = 0;\n v17 = 0;\n }\n else\n {\n v10 = a1;\n v11 = v6;\n v12 = &v6[v8 >> 3];\n do\n {\n v13 = (__m128)_mm_loadu_si128(v10);\n v14 = (__m128)_mm_loadu_si128(v10 + 1);\n ++v11;\n v10 += 3;\n v15 = _mm_shuffle_ps(v13, _mm_shuffle_ps(v14, v13, 10), 140);\n v11[-1] = _mm_shuffle_ps(v15, _mm_shuffle_ps((__m128)_mm_loadu_si128(v10 - 1), v15, 165), 36);\n }\n while ( v11 != v12 );\n v16 = v9 & 0xFFFFFFFC;\n v17 = 3 * (v9 & 0xFFFFFFFC);\n }\n v18 = v16 + 1;\n v19 = v16;\n v6->m128_i32[v19] = a1->m128i_i32[v17];\n v20 = 3 * (v16 + 1);\n if ( (int)v3 > v20 )\n {\n v21 = v20;\n v6->m128_i32[v19 + 1] = a1->m128i_i32[v21];\n if ( (int)v3 > v20 + 3 )\n {\n v18 = v16 + 3;\n v6->m128_i32[v19 + 2] = a1->m128i_i32[v21 + 3];\n if ( v20 + 6 >= (int)v3 )\n v18 = v16 + 2;\n else\n v6->m128_i32[v19 + 3] = a1[1].m128i_i32[v21 + 2];\n }\n goto LABEL_10;\n }\n if ( v16 > 0 )\n {\n v18 = v16;\nLABEL_10:\n v22 = &v6->m128_i32[1];\n v23 = 0;\n do\n {\n v24 = *(v22 - 1);\n v25 = v23++;\n v26 = v22;\n v27 = v25;\n v28 = v23;\n v29 = v24;\n while ( 1 )\n {\n v30 = v26;\n if ( v29 > *v26 )\n break;\n ++v26;\n v30 = &v6->m128_i32[v27];\n v31 = v28 + 1;\n if ( v28 >= v18 )\n goto LABEL_16;\nLABEL_13:\n v28 = v31;\n }\n v29 = *v26;\n v27 = v28;\n v31 = v28 + 1;\n ++v26;\n if ( v28 < v18 )\n goto LABEL_13;\nLABEL_16:\n if ( v27 != v25 )\n {\n *(v22 - 1) = v29;\n *v30 = v24;\n }\n ++v22;\n }\n while ( v23 != v18 );\n }\n v32 = 0LL;\n do\n {\n while ( (unsigned int)(-1431655765 * v32) <= 0x55555555 )\n {\n *(_DWORD *)(a3 + 4 * v32) = v6->m128_i32[(unsigned int)v32 / 3uLL];\n if ( ++v32 == v3 )\n goto LABEL_22;\n }\n *(_DWORD *)(a3 + 4 * v32) = a1->m128i_i32[v32];\n ++v32;\n }\n while ( v32 != v3 );\n }\nLABEL_22:\n free(v6);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_15C0(const __m128i *a1, int a2, long long a3) {\n long long v3;\n __m128 *v6;\n long long v7;\n unsigned long long v8;\n unsigned int v9;\n const __m128i *v10;\n __m128 *v11;\n __m128 *v12;\n __m128 v13;\n __m128 v14;\n __m128 v15;\n signed int v16;\n signed int v17;\n signed int v18;\n long long v19;\n int v20;\n long long v21;\n int *v22;\n signed int v23;\n int v24;\n int v25;\n int *v26;\n signed int v27;\n signed int v28;\n int v29;\n int *v30;\n signed int v31;\n long long v32;\n v3 = a2;\n v6 = (__m128 *)malloc(4LL * (a2 / 3 + 1));\n if (a2 > 0) {\n v7 = (unsigned int)(a2 - 1);\n v8 = (unsigned long long)(2863311531LL * v7) >> 32;\n v9 = (a2 - 1) / 3u;\n if ((unsigned int)v7 <= 11) {\n v16 = 0;\n v17 = 0;\n } else {\n v10 = a1;\n v11 = v6;\n v12 = &v6[v8 >> 3];\n do {\n v13 = (__m128)_mm_loadu_si128(v10);\n v14 = (__m128)_mm_loadu_si128(v10 + 1);\n ++v11;\n v10 += 3;\n v15 = _mm_shuffle_ps(v13, _mm_shuffle_ps(v14, v13, 10), 140);\n v11[-1] = _mm_shuffle_ps(\n v15, _mm_shuffle_ps((__m128)_mm_loadu_si128(v10 - 1), v15, 165),\n 36);\n } while (v11 != v12);\n v16 = v9 & 4294967292;\n v17 = 3 * (v9 & 4294967292);\n }\n v18 = v16 + 1;\n v19 = v16;\n v6->m128_i32[v19] = a1->m128i_i32[v17];\n v20 = 3 * (v16 + 1);\n if ((int)v3 > v20) {\n v21 = v20;\n v6->m128_i32[v19 + 1] = a1->m128i_i32[v21];\n if ((int)v3 > v20 + 3) {\n v18 = v16 + 3;\n v6->m128_i32[v19 + 2] = a1->m128i_i32[v21 + 3];\n if (v20 + 6 >= (int)v3)\n v18 = v16 + 2;\n else\n v6->m128_i32[v19 + 3] = a1[1].m128i_i32[v21 + 2];\n }\n goto LABEL_10;\n }\n if (v16 > 0) {\n v18 = v16;\n LABEL_10:\n v22 = &v6->m128_i32[1];\n v23 = 0;\n do {\n v24 = *(v22 - 1);\n v25 = v23++;\n v26 = v22;\n v27 = v25;\n v28 = v23;\n v29 = v24;\n while (1) {\n v30 = v26;\n if (v29 > *v26) break;\n ++v26;\n v30 = &v6->m128_i32[v27];\n v31 = v28 + 1;\n if (v28 >= v18) goto LABEL_16;\n LABEL_13:\n v28 = v31;\n }\n v29 = *v26;\n v27 = v28;\n v31 = v28 + 1;\n ++v26;\n if (v28 < v18) goto LABEL_13;\n LABEL_16:\n if (v27 != v25) {\n *(v22 - 1) = v29;\n *v30 = v24;\n }\n ++v22;\n } while (v23 != v18);\n }\n v32 = 0LL;\n do {\n while ((unsigned int)(-1431655765 * v32) <= 1431655765) {\n *(uint32_t *)(a3 + 4 * v32) = v6->m128_i32[(unsigned int)v32 / 3uLL];\n if (++v32 == v3) goto LABEL_22;\n }\n *(uint32_t *)(a3 + 4 * v32) = a1->m128i_i32[v32];\n ++v32;\n } while (v32 != v3);\n }\nLABEL_22:\n free(v6);\n}", + "ida_pseudo_norm": "void func0(const __m128i *a1, int a2, long long a3) {\n long long v3;\n __m128 *v6;\n long long v7;\n unsigned long long v8;\n unsigned int v9;\n const __m128i *v10;\n __m128 *v11;\n __m128 *v12;\n __m128 v13;\n __m128 v14;\n __m128 v15;\n signed int v16;\n signed int v17;\n signed int v18;\n long long v19;\n int v20;\n long long v21;\n int *v22;\n signed int v23;\n int v24;\n int v25;\n int *v26;\n signed int v27;\n signed int v28;\n int v29;\n int *v30;\n signed int v31;\n long long v32;\n v3 = a2;\n v6 = (__m128 *)malloc(4LL * (a2 / 3 + 1));\n if (a2 > 0) {\n v7 = (unsigned int)(a2 - 1);\n v8 = (unsigned long long)(2863311531LL * v7) >> 32;\n v9 = (a2 - 1) / 3u;\n if ((unsigned int)v7 <= 11) {\n v16 = 0;\n v17 = 0;\n } else {\n v10 = a1;\n v11 = v6;\n v12 = &v6[v8 >> 3];\n do {\n v13 = (__m128)_mm_loadu_si128(v10);\n v14 = (__m128)_mm_loadu_si128(v10 + 1);\n ++v11;\n v10 += 3;\n v15 = _mm_shuffle_ps(v13, _mm_shuffle_ps(v14, v13, 10), 140);\n v11[-1] = _mm_shuffle_ps(\n v15, _mm_shuffle_ps((__m128)_mm_loadu_si128(v10 - 1), v15, 165),\n 36);\n } while (v11 != v12);\n v16 = v9 & 4294967292;\n v17 = 3 * (v9 & 4294967292);\n }\n v18 = v16 + 1;\n v19 = v16;\n v6->m128_i32[v19] = a1->m128i_i32[v17];\n v20 = 3 * (v16 + 1);\n if ((int)v3 > v20) {\n v21 = v20;\n v6->m128_i32[v19 + 1] = a1->m128i_i32[v21];\n if ((int)v3 > v20 + 3) {\n v18 = v16 + 3;\n v6->m128_i32[v19 + 2] = a1->m128i_i32[v21 + 3];\n if (v20 + 6 >= (int)v3)\n v18 = v16 + 2;\n else\n v6->m128_i32[v19 + 3] = a1[1].m128i_i32[v21 + 2];\n }\n goto LABEL_10;\n }\n if (v16 > 0) {\n v18 = v16;\n LABEL_10:\n v22 = &v6->m128_i32[1];\n v23 = 0;\n do {\n v24 = *(v22 - 1);\n v25 = v23++;\n v26 = v22;\n v27 = v25;\n v28 = v23;\n v29 = v24;\n while (1) {\n v30 = v26;\n if (v29 > *v26) break;\n ++v26;\n v30 = &v6->m128_i32[v27];\n v31 = v28 + 1;\n if (v28 >= v18) goto LABEL_16;\n LABEL_13:\n v28 = v31;\n }\n v29 = *v26;\n v27 = v28;\n v31 = v28 + 1;\n ++v26;\n if (v28 < v18) goto LABEL_13;\n LABEL_16:\n if (v27 != v25) {\n *(v22 - 1) = v29;\n *v30 = v24;\n }\n ++v22;\n } while (v23 != v18);\n }\n v32 = 0LL;\n do {\n while ((unsigned int)(-1431655765 * v32) <= 1431655765) {\n *(uint32_t *)(a3 + 4 * v32) = v6->m128_i32[(unsigned int)v32 / 3uLL];\n if (++v32 == v3) goto LABEL_22;\n }\n *(uint32_t *)(a3 + 4 * v32) = a1->m128i_i32[v32];\n ++v32;\n } while (v32 != v3);\n }\nLABEL_22:\n free(v6);\n}" + }, + { + "index": "HumanEval-C-34", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int *func0(int *l, int size, int *out_size) {\n int *out = malloc(size * sizeof(int));\n int found, out_count = 0, i, j;\n for (i = 0; i < size; i++) {\n found = 0;\n for (j = 0; j < out_count; j++) {\n if (l[i] == out[j]) {\n found = 1;\n break;\n }\n }\n if (!found) {\n out[out_count++] = l[i];\n }\n }\n for (i = 0; i < out_count - 1; i++) {\n for (j = i + 1; j < out_count; j++) {\n if (out[i] > out[j]) {\n int temp = out[i];\n out[i] = out[j];\n out[j] = temp;\n }\n }\n }\n *out_size = out_count;\n return out;\n}", + "test": "#include \n#include \n#include \n\nint main() {\n int test_array[] = {5, 3, 5, 2, 3, 3, 9, 0, 123};\n int expected_array[] = {0, 2, 3, 5, 9, 123};\n int unique_size;\n int *unique_array = func0(test_array, sizeof(test_array) / sizeof(test_array[0]), &unique_size);\n\n assert(unique_size == sizeof(expected_array) / sizeof(expected_array[0]));\n for (int i = 0; i < unique_size; i++) {\n assert(unique_array[i] == expected_array[i]);\n }\n\n free(unique_array);\n printf(\"All tests passed!\\n\");\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp loc_129A\nloc_1208:\nmov [rbp+var_1C], 0\nmov [rbp+var_10], 0\njmp short loc_1255\nloc_1218:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_1251\nmov [rbp+var_1C], 1\njmp short loc_125D\nloc_1251:\nadd [rbp+var_10], 1\nloc_1255:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_18]\njl short loc_1218\nloc_125D:\ncmp [rbp+var_1C], 0\njnz short loc_1296\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_1296:\nadd [rbp+var_14], 1\nloc_129A:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl loc_1208\nmov [rbp+var_14], 0\njmp loc_1363\nloc_12B2:\nmov eax, [rbp+var_14]\nadd eax, 1\nmov [rbp+var_10], eax\njmp loc_1353\nloc_12C0:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_134F\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_C]\nmov [rdx], eax\nloc_134F:\nadd [rbp+var_10], 1\nloc_1353:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_18]\njl loc_12C0\nadd [rbp+var_14], 1\nloc_1363:\nmov eax, [rbp+var_18]\nsub eax, 1\ncmp [rbp+var_14], eax\njl loc_12B2\nmov rax, [rbp+var_38]\nmov edx, [rbp+var_18]\nmov [rax], edx\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, _DWORD *a3)\n{\n int v3; // eax\n int v6; // [rsp+24h] [rbp-1Ch]\n int v7; // [rsp+28h] [rbp-18h]\n int i; // [rsp+2Ch] [rbp-14h]\n int k; // [rsp+2Ch] [rbp-14h]\n int j; // [rsp+30h] [rbp-10h]\n int m; // [rsp+30h] [rbp-10h]\n int v12; // [rsp+34h] [rbp-Ch]\n _DWORD *v13; // [rsp+38h] [rbp-8h]\n\n v13 = malloc(4LL * a2);\n v7 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v6 = 0;\n for ( j = 0; j < v7; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a1) == v13[j] )\n {\n v6 = 1;\n break;\n }\n }\n if ( !v6 )\n {\n v3 = v7++;\n v13[v3] = *(_DWORD *)(4LL * i + a1);\n }\n }\n for ( k = 0; k < v7 - 1; ++k )\n {\n for ( m = k + 1; m < v7; ++m )\n {\n if ( v13[k] > v13[m] )\n {\n v12 = v13[k];\n v13[k] = v13[m];\n v13[m] = v12;\n }\n }\n }\n *a3 = v7;\n return v13;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp loc_129A\nloc_1208:\nmov [rbp+var_1C], 0\nmov [rbp+var_10], 0\njmp short loc_1255\nloc_1218:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_1251\nmov [rbp+var_1C], 1\njmp short loc_125D\nloc_1251:\nadd [rbp+var_10], 1\nloc_1255:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_18]\njl short loc_1218\nloc_125D:\ncmp [rbp+var_1C], 0\njnz short loc_1296\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_1296:\nadd [rbp+var_14], 1\nloc_129A:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl loc_1208\nmov [rbp+var_14], 0\njmp loc_1363\nloc_12B2:\nmov eax, [rbp+var_14]\nadd eax, 1\nmov [rbp+var_10], eax\njmp loc_1353\nloc_12C0:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_134F\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_C]\nmov [rdx], eax\nloc_134F:\nadd [rbp+var_10], 1\nloc_1353:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_18]\njl loc_12C0\nadd [rbp+var_14], 1\nloc_1363:\nmov eax, [rbp+var_18]\nsub eax, 1\ncmp [rbp+var_14], eax\njl loc_12B2\nmov rax, [rbp+var_38]\nmov edx, [rbp+var_18]\nmov [rax], edx\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11C9(__int64 a1, int a2, _DWORD *a3)\n{\n int v3; // eax\n int v6; // [rsp+24h] [rbp-1Ch]\n int v7; // [rsp+28h] [rbp-18h]\n int i; // [rsp+2Ch] [rbp-14h]\n int k; // [rsp+2Ch] [rbp-14h]\n int j; // [rsp+30h] [rbp-10h]\n int m; // [rsp+30h] [rbp-10h]\n int v12; // [rsp+34h] [rbp-Ch]\n _DWORD *v13; // [rsp+38h] [rbp-8h]\n\n v13 = malloc(4LL * a2);\n v7 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v6 = 0;\n for ( j = 0; j < v7; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a1) == v13[j] )\n {\n v6 = 1;\n break;\n }\n }\n if ( !v6 )\n {\n v3 = v7++;\n v13[v3] = *(_DWORD *)(4LL * i + a1);\n }\n }\n for ( k = 0; k < v7 - 1; ++k )\n {\n for ( m = k + 1; m < v7; ++m )\n {\n if ( v13[k] > v13[m] )\n {\n v12 = v13[k];\n v13[k] = v13[m];\n v13[m] = v12;\n }\n }\n }\n *a3 = v7;\n return v13;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11C9(long long a1, int a2, uint32_t *a3) {\n int v3;\n int v6;\n int v7;\n int i;\n int k;\n int j;\n int m;\n int v12;\n uint32_t *v13;\n v13 = malloc(4LL * a2);\n v7 = 0;\n for (i = 0; i < a2; ++i) {\n v6 = 0;\n for (j = 0; j < v7; ++j) {\n if (*(uint32_t *)(4LL * i + a1) == v13[j]) {\n v6 = 1;\n break;\n }\n }\n if (!v6) {\n v3 = v7++;\n v13[v3] = *(uint32_t *)(4LL * i + a1);\n }\n }\n for (k = 0; k < v7 - 1; ++k) {\n for (m = k + 1; m < v7; ++m) {\n if (v13[k] > v13[m]) {\n v12 = v13[k];\n v13[k] = v13[m];\n v13[m] = v12;\n }\n }\n }\n *a3 = v7;\n return v13;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, uint32_t *a3) {\n int v3;\n int v6;\n int v7;\n int i;\n int k;\n int j;\n int m;\n int v12;\n uint32_t *v13;\n v13 = malloc(4LL * a2);\n v7 = 0;\n for (i = 0; i < a2; ++i) {\n v6 = 0;\n for (j = 0; j < v7; ++j) {\n if (*(uint32_t *)(4LL * i + a1) == v13[j]) {\n v6 = 1;\n break;\n }\n }\n if (!v6) {\n v3 = v7++;\n v13[v3] = *(uint32_t *)(4LL * i + a1);\n }\n }\n for (k = 0; k < v7 - 1; ++k) {\n for (m = k + 1; m < v7; ++m) {\n if (v13[k] > v13[m]) {\n v12 = v13[k];\n v13[k] = v13[m];\n v13[m] = v12;\n }\n }\n }\n *a3 = v7;\n return v13;\n}" + }, + { + "index": "HumanEval-C-34", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int *func0(int *l, int size, int *out_size) {\n int *out = malloc(size * sizeof(int));\n int found, out_count = 0, i, j;\n for (i = 0; i < size; i++) {\n found = 0;\n for (j = 0; j < out_count; j++) {\n if (l[i] == out[j]) {\n found = 1;\n break;\n }\n }\n if (!found) {\n out[out_count++] = l[i];\n }\n }\n for (i = 0; i < out_count - 1; i++) {\n for (j = i + 1; j < out_count; j++) {\n if (out[i] > out[j]) {\n int temp = out[i];\n out[i] = out[j];\n out[j] = temp;\n }\n }\n }\n *out_size = out_count;\n return out;\n}", + "test": "#include \n#include \n#include \n\nint main() {\n int test_array[] = {5, 3, 5, 2, 3, 3, 9, 0, 123};\n int expected_array[] = {0, 2, 3, 5, 9, 123};\n int unique_size;\n int *unique_array = func0(test_array, sizeof(test_array) / sizeof(test_array[0]), &unique_size);\n\n assert(unique_size == sizeof(expected_array) / sizeof(expected_array[0]));\n for (int i = 0; i < unique_size; i++) {\n assert(unique_array[i] == expected_array[i]);\n }\n\n free(unique_array);\n printf(\"All tests passed!\\n\");\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov r12d, esi\nmov rbx, rdx\nmovsxd r13, esi\nshl r13, 2\nmov rdi, r13; size\ncall _malloc\nmov r10, rax\ntest r12d, r12d\njle loc_129E\nmov rsi, rbp\nlea rdi, [rbp+r13+0]\nmov r9d, 0\njmp short loc_1221\nloc_120B:\nmovsxd rax, r9d\nmov edx, [rsi]\nmov [r10+rax*4], edx\nlea r9d, [r9+1]\nloc_1218:\nadd rsi, 4\ncmp rsi, rdi\njz short loc_1241\nloc_1221:\ntest r9d, r9d\njle short loc_120B\nmov edx, [rsi]\nmov rax, r10\nmovsxd rcx, r9d\nlea rcx, [r10+rcx*4]\nloc_1232:\ncmp edx, [rax]\njz short loc_1218\nadd rax, 4\ncmp rax, rcx\njnz short loc_1232\njmp short loc_120B\nloc_1241:\ncmp r9d, 1\njle short loc_12A4\nlea rsi, [r10+4]\nmov r11d, r9d\nmov r8d, 1\nlea r12d, [r9-1]\nlea rbp, [r10+8]\njmp short loc_1284\nloc_125E:\nadd rax, 4\ncmp rax, rdi\njz short loc_1277\nloc_1267:\nmov edx, [rsi-4]\nmov ecx, [rax]\ncmp edx, ecx\njle short loc_125E\nmov [rsi-4], ecx\nmov [rax], edx\njmp short loc_125E\nloc_1277:\nadd r8, 1\nadd rsi, 4\ncmp r8, r11\njz short loc_12A4\nloc_1284:\ncmp r9d, r8d\njle short loc_1277\nmov eax, r12d\nsub eax, r8d\nlea rax, [r8+rax-1]\nlea rdi, [rbp+rax*4+0]\nmov rax, rsi\njmp short loc_1267\nloc_129E:\nmov r9d, 0\nloc_12A4:\nmov [rbx], r9d\nmov rax, r10\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(_DWORD *a1, int a2, int *a3)\n{\n size_t v4; // r13\n _DWORD *v5; // r10\n _DWORD *v6; // rsi\n int v7; // r9d\n _DWORD *v8; // rax\n _DWORD *v9; // rsi\n __int64 i; // r8\n _DWORD *v11; // rax\n int v12; // edx\n\n v4 = a2;\n v5 = malloc(v4 * 4);\n if ( a2 <= 0 )\n {\n v7 = 0;\n }\n else\n {\n v6 = a1;\n v7 = 0;\n do\n {\n if ( v7 <= 0 )\n {\nLABEL_3:\n v5[v7++] = *v6;\n }\n else\n {\n v8 = v5;\n while ( *v6 != *v8 )\n {\n if ( ++v8 == &v5[v7] )\n goto LABEL_3;\n }\n }\n ++v6;\n }\n while ( v6 != &a1[v4] );\n if ( v7 > 1 )\n {\n v9 = v5 + 1;\n for ( i = 1LL; i != v7; ++i )\n {\n if ( v7 > (int)i )\n {\n v11 = v9;\n do\n {\n v12 = *(v9 - 1);\n if ( v12 > *v11 )\n {\n *(v9 - 1) = *v11;\n *v11 = v12;\n }\n ++v11;\n }\n while ( v11 != &v5[i + 1 + (unsigned int)(v7 - 1 - i)] );\n }\n ++v9;\n }\n }\n }\n *a3 = v7;\n return v5;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov r12d, esi\nmov rbx, rdx\nmovsxd r13, esi\nshl r13, 2\nmov rdi, r13; size\ncall _malloc\nmov r10, rax\ntest r12d, r12d\njle loc_129E\nmov rsi, rbp\nlea rdi, [rbp+r13+0]\nmov r9d, 0\njmp short loc_1221\nloc_120B:\nmovsxd rax, r9d\nmov edx, [rsi]\nmov [r10+rax*4], edx\nlea r9d, [r9+1]\nloc_1218:\nadd rsi, 4\ncmp rsi, rdi\njz short loc_1241\nloc_1221:\ntest r9d, r9d\njle short loc_120B\nmov edx, [rsi]\nmov rax, r10\nmovsxd rcx, r9d\nlea rcx, [r10+rcx*4]\nloc_1232:\ncmp edx, [rax]\njz short loc_1218\nadd rax, 4\ncmp rax, rcx\njnz short loc_1232\njmp short loc_120B\nloc_1241:\ncmp r9d, 1\njle short loc_12A4\nlea rsi, [r10+4]\nmov r11d, r9d\nmov r8d, 1\nlea r12d, [r9-1]\nlea rbp, [r10+8]\njmp short loc_1284\nloc_125E:\nadd rax, 4\ncmp rax, rdi\njz short loc_1277\nloc_1267:\nmov edx, [rsi-4]\nmov ecx, [rax]\ncmp edx, ecx\njle short loc_125E\nmov [rsi-4], ecx\nmov [rax], edx\njmp short loc_125E\nloc_1277:\nadd r8, 1\nadd rsi, 4\ncmp r8, r11\njz short loc_12A4\nloc_1284:\ncmp r9d, r8d\njle short loc_1277\nmov eax, r12d\nsub eax, r8d\nlea rax, [r8+rax-1]\nlea rdi, [rbp+rax*4+0]\nmov rax, rsi\njmp short loc_1267\nloc_129E:\nmov r9d, 0\nloc_12A4:\nmov [rbx], r9d\nmov rax, r10\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11C9(_DWORD *a1, int a2, int *a3)\n{\n size_t v4; // r13\n _DWORD *v5; // r10\n _DWORD *v6; // rsi\n int v7; // r9d\n _DWORD *v8; // rax\n _DWORD *v9; // rsi\n __int64 i; // r8\n _DWORD *v11; // rax\n int v12; // edx\n\n v4 = a2;\n v5 = malloc(v4 * 4);\n if ( a2 <= 0 )\n {\n v7 = 0;\n }\n else\n {\n v6 = a1;\n v7 = 0;\n do\n {\n if ( v7 <= 0 )\n {\nLABEL_3:\n v5[v7++] = *v6;\n }\n else\n {\n v8 = v5;\n while ( *v6 != *v8 )\n {\n if ( ++v8 == &v5[v7] )\n goto LABEL_3;\n }\n }\n ++v6;\n }\n while ( v6 != &a1[v4] );\n if ( v7 > 1 )\n {\n v9 = v5 + 1;\n for ( i = 1LL; i != v7; ++i )\n {\n if ( v7 > (int)i )\n {\n v11 = v9;\n do\n {\n v12 = *(v9 - 1);\n if ( v12 > *v11 )\n {\n *(v9 - 1) = *v11;\n *v11 = v12;\n }\n ++v11;\n }\n while ( v11 != &v5[i + 1 + (unsigned int)(v7 - 1 - i)] );\n }\n ++v9;\n }\n }\n }\n *a3 = v7;\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11C9(uint32_t *a1, int a2, int *a3) {\n unsigned int v4;\n uint32_t *v5;\n uint32_t *v6;\n int v7;\n uint32_t *v8;\n uint32_t *v9;\n long long i;\n uint32_t *v11;\n int v12;\n v4 = a2;\n v5 = malloc(v4 * 4);\n if (a2 <= 0) {\n v7 = 0;\n } else {\n v6 = a1;\n v7 = 0;\n do {\n if (v7 <= 0) {\n LABEL_3:\n v5[v7++] = *v6;\n } else {\n v8 = v5;\n while (*v6 != *v8) {\n if (++v8 == &v5[v7]) goto LABEL_3;\n }\n }\n ++v6;\n } while (v6 != &a1[v4]);\n if (v7 > 1) {\n v9 = v5 + 1;\n for (i = 1LL; i != v7; ++i) {\n if (v7 > (int)i) {\n v11 = v9;\n do {\n v12 = *(v9 - 1);\n if (v12 > *v11) {\n *(v9 - 1) = *v11;\n *v11 = v12;\n }\n ++v11;\n } while (v11 != &v5[i + 1 + (unsigned int)(v7 - 1 - i)]);\n }\n ++v9;\n }\n }\n }\n *a3 = v7;\n return v5;\n}", + "ida_pseudo_norm": "uint32_t *func0(uint32_t *a1, int a2, int *a3) {\n unsigned int v4;\n uint32_t *v5;\n uint32_t *v6;\n int v7;\n uint32_t *v8;\n uint32_t *v9;\n long long i;\n uint32_t *v11;\n int v12;\n v4 = a2;\n v5 = malloc(v4 * 4);\n if (a2 <= 0) {\n v7 = 0;\n } else {\n v6 = a1;\n v7 = 0;\n do {\n if (v7 <= 0) {\n LABEL_3:\n v5[v7++] = *v6;\n } else {\n v8 = v5;\n while (*v6 != *v8) {\n if (++v8 == &v5[v7]) goto LABEL_3;\n }\n }\n ++v6;\n } while (v6 != &a1[v4]);\n if (v7 > 1) {\n v9 = v5 + 1;\n for (i = 1LL; i != v7; ++i) {\n if (v7 > (int)i) {\n v11 = v9;\n do {\n v12 = *(v9 - 1);\n if (v12 > *v11) {\n *(v9 - 1) = *v11;\n *v11 = v12;\n }\n ++v11;\n } while (v11 != &v5[i + 1 + (unsigned int)(v7 - 1 - i)]);\n }\n ++v9;\n }\n }\n }\n *a3 = v7;\n return v5;\n}" + }, + { + "index": "HumanEval-C-34", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int *func0(int *l, int size, int *out_size) {\n int *out = malloc(size * sizeof(int));\n int found, out_count = 0, i, j;\n for (i = 0; i < size; i++) {\n found = 0;\n for (j = 0; j < out_count; j++) {\n if (l[i] == out[j]) {\n found = 1;\n break;\n }\n }\n if (!found) {\n out[out_count++] = l[i];\n }\n }\n for (i = 0; i < out_count - 1; i++) {\n for (j = i + 1; j < out_count; j++) {\n if (out[i] > out[j]) {\n int temp = out[i];\n out[i] = out[j];\n out[j] = temp;\n }\n }\n }\n *out_size = out_count;\n return out;\n}", + "test": "#include \n#include \n#include \n\nint main() {\n int test_array[] = {5, 3, 5, 2, 3, 3, 9, 0, 123};\n int expected_array[] = {0, 2, 3, 5, 9, 123};\n int unique_size;\n int *unique_array = func0(test_array, sizeof(test_array) / sizeof(test_array[0]), &unique_size);\n\n assert(unique_size == sizeof(expected_array) / sizeof(expected_array[0]));\n for (int i = 0; i < unique_size; i++) {\n assert(unique_array[i] == expected_array[i]);\n }\n\n free(unique_array);\n printf(\"All tests passed!\\n\");\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\nmov rbp, rdx\npush rbx\nmov rbx, rdi\nmovsxd rdi, esi\nlea r12, ds:0[rdi*4]\nmov r13, rdi\nmov rdi, r12; size\nsub rsp, 8\ncall _malloc\nmov r10, rax\ntest r13d, r13d\njle loc_13C6\nmov rsi, rbx\nlea rdi, [rbx+r12]\nxor r9d, r9d\nloc_1310:\nmovsxd r8, r9d\nmov edx, [rsi]\nlea rcx, [r10+r8*4]\ntest r9d, r9d\njle short loc_1348\nloc_131E:\nmov rax, r10\njmp short loc_1331\nloc_1328:\nadd rax, 4\ncmp rax, rcx\njz short loc_1348\nloc_1331:\ncmp [rax], edx\njnz short loc_1328\nadd rsi, 4\ncmp rsi, rdi\njz short loc_1359\nmov edx, [rsi]\njmp short loc_131E\nloc_1348:\nadd rsi, 4\nmov [r10+r8*4], edx\nadd r9d, 1\ncmp rsi, rdi\njnz short loc_1310\nloc_1359:\ncmp r9d, 1\njle short loc_13B4\nlea rsi, [r10+4]\nmov r11d, r9d\nmov r8d, 1\nlea r12d, [r9-1]\nlea rbx, [r10+8]\nnop dword ptr [rax+00h]\nloc_1378:\ncmp r9d, r8d\njle short loc_13A7\nmov eax, r12d\nsub eax, r8d\nlea rax, [r8+rax-1]\nlea rdi, [rbx+rax*4]\nmov rax, rsi\nnop\nloc_1390:\nmov edx, [rsi-4]\nmov ecx, [rax]\ncmp edx, ecx\njle short loc_139E\nmov [rsi-4], ecx\nmov [rax], edx\nloc_139E:\nadd rax, 4\ncmp rax, rdi\njnz short loc_1390\nloc_13A7:\nadd r8, 1\nadd rsi, 4\ncmp r8, r11\njnz short loc_1378\nloc_13B4:\nmov [rbp+0], r9d\nadd rsp, 8\nmov rax, r10\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_13C6:\nxor r9d, r9d\njmp short loc_13B4", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2, int *a3)\n{\n size_t v4; // r12\n _DWORD *v5; // r10\n int *v6; // rsi\n int *v7; // rdi\n int v8; // r9d\n int v9; // edx\n _DWORD *v10; // rax\n _DWORD *v11; // rsi\n __int64 i; // r8\n _DWORD *v13; // rax\n int v14; // edx\n\n v4 = a2;\n v5 = malloc(v4 * 4);\n if ( a2 <= 0 )\n {\n v8 = 0;\n }\n else\n {\n v6 = a1;\n v7 = &a1[v4];\n v8 = 0;\n while ( 1 )\n {\n v9 = *v6;\n if ( v8 > 0 )\n break;\nLABEL_9:\n ++v6;\n v5[v8++] = v9;\n if ( v6 == v7 )\n goto LABEL_10;\n }\n while ( 1 )\n {\n v10 = v5;\n while ( *v10 != v9 )\n {\n if ( ++v10 == &v5[v8] )\n goto LABEL_9;\n }\n if ( ++v6 == v7 )\n break;\n v9 = *v6;\n }\nLABEL_10:\n if ( v8 > 1 )\n {\n v11 = v5 + 1;\n for ( i = 1LL; i != v8; ++i )\n {\n if ( v8 > (int)i )\n {\n v13 = v11;\n do\n {\n v14 = *(v11 - 1);\n if ( v14 > *v13 )\n {\n *(v11 - 1) = *v13;\n *v13 = v14;\n }\n ++v13;\n }\n while ( v13 != &v5[i + 1 + (unsigned int)(v8 - 1 - i)] );\n }\n ++v11;\n }\n }\n }\n *a3 = v8;\n return v5;\n}", + "ida_strip_asm": "sub_12D0:\nendbr64\npush r13\npush r12\npush rbp\nmov rbp, rdx\npush rbx\nmov rbx, rdi\nmovsxd rdi, esi\nlea r12, ds:0[rdi*4]\nmov r13, rdi\nmov rdi, r12; size\nsub rsp, 8\ncall _malloc\nmov r10, rax\ntest r13d, r13d\njle loc_13C6\nmov rsi, rbx\nlea rdi, [rbx+r12]\nxor r9d, r9d\nloc_1310:\nmovsxd r8, r9d\nmov edx, [rsi]\nlea rcx, [r10+r8*4]\ntest r9d, r9d\njle short loc_1348\nloc_131E:\nmov rax, r10\njmp short loc_1331\nloc_1328:\nadd rax, 4\ncmp rax, rcx\njz short loc_1348\nloc_1331:\ncmp [rax], edx\njnz short loc_1328\nadd rsi, 4\ncmp rsi, rdi\njz short loc_1359\nmov edx, [rsi]\njmp short loc_131E\nloc_1348:\nadd rsi, 4\nmov [r10+r8*4], edx\nadd r9d, 1\ncmp rsi, rdi\njnz short loc_1310\nloc_1359:\ncmp r9d, 1\njle short loc_13B4\nlea rsi, [r10+4]\nmov r11d, r9d\nmov r8d, 1\nlea r12d, [r9-1]\nlea rbx, [r10+8]\nnop dword ptr [rax+00h]\nloc_1378:\ncmp r9d, r8d\njle short loc_13A7\nmov eax, r12d\nsub eax, r8d\nlea rax, [r8+rax-1]\nlea rdi, [rbx+rax*4]\nmov rax, rsi\nnop\nloc_1390:\nmov edx, [rsi-4]\nmov ecx, [rax]\ncmp edx, ecx\njle short loc_139E\nmov [rsi-4], ecx\nmov [rax], edx\nloc_139E:\nadd rax, 4\ncmp rax, rdi\njnz short loc_1390\nloc_13A7:\nadd r8, 1\nadd rsi, 4\ncmp r8, r11\njnz short loc_1378\nloc_13B4:\nmov [rbp+0], r9d\nadd rsp, 8\nmov rax, r10\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_13C6:\nxor r9d, r9d\njmp short loc_13B4", + "ida_strip_pseudo": "_DWORD *__fastcall sub_12D0(int *a1, int a2, int *a3)\n{\n size_t v4; // r12\n _DWORD *v5; // r10\n int *v6; // rsi\n int *v7; // rdi\n int v8; // r9d\n int v9; // edx\n _DWORD *v10; // rax\n _DWORD *v11; // rsi\n __int64 i; // r8\n _DWORD *v13; // rax\n int v14; // edx\n\n v4 = a2;\n v5 = malloc(v4 * 4);\n if ( a2 <= 0 )\n {\n v8 = 0;\n }\n else\n {\n v6 = a1;\n v7 = &a1[v4];\n v8 = 0;\n while ( 1 )\n {\n v9 = *v6;\n if ( v8 > 0 )\n break;\nLABEL_9:\n ++v6;\n v5[v8++] = v9;\n if ( v6 == v7 )\n goto LABEL_10;\n }\n while ( 1 )\n {\n v10 = v5;\n while ( *v10 != v9 )\n {\n if ( ++v10 == &v5[v8] )\n goto LABEL_9;\n }\n if ( ++v6 == v7 )\n break;\n v9 = *v6;\n }\nLABEL_10:\n if ( v8 > 1 )\n {\n v11 = v5 + 1;\n for ( i = 1LL; i != v8; ++i )\n {\n if ( v8 > (int)i )\n {\n v13 = v11;\n do\n {\n v14 = *(v11 - 1);\n if ( v14 > *v13 )\n {\n *(v11 - 1) = *v13;\n *v13 = v14;\n }\n ++v13;\n }\n while ( v13 != &v5[i + 1 + (unsigned int)(v8 - 1 - i)] );\n }\n ++v11;\n }\n }\n }\n *a3 = v8;\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_12D0(int *a1, int a2, int *a3) {\n unsigned int v4;\n uint32_t *v5;\n int *v6;\n int *v7;\n int v8;\n int v9;\n uint32_t *v10;\n uint32_t *v11;\n long long i;\n uint32_t *v13;\n int v14;\n v4 = a2;\n v5 = malloc(v4 * 4);\n if (a2 <= 0) {\n v8 = 0;\n } else {\n v6 = a1;\n v7 = &a1[v4];\n v8 = 0;\n while (1) {\n v9 = *v6;\n if (v8 > 0) break;\n LABEL_9:\n ++v6;\n v5[v8++] = v9;\n if (v6 == v7) goto LABEL_10;\n }\n while (1) {\n v10 = v5;\n while (*v10 != v9) {\n if (++v10 == &v5[v8]) goto LABEL_9;\n }\n if (++v6 == v7) break;\n v9 = *v6;\n }\n LABEL_10:\n if (v8 > 1) {\n v11 = v5 + 1;\n for (i = 1LL; i != v8; ++i) {\n if (v8 > (int)i) {\n v13 = v11;\n do {\n v14 = *(v11 - 1);\n if (v14 > *v13) {\n *(v11 - 1) = *v13;\n *v13 = v14;\n }\n ++v13;\n } while (v13 != &v5[i + 1 + (unsigned int)(v8 - 1 - i)]);\n }\n ++v11;\n }\n }\n }\n *a3 = v8;\n return v5;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2, int *a3) {\n unsigned int v4;\n uint32_t *v5;\n int *v6;\n int *v7;\n int v8;\n int v9;\n uint32_t *v10;\n uint32_t *v11;\n long long i;\n uint32_t *v13;\n int v14;\n v4 = a2;\n v5 = malloc(v4 * 4);\n if (a2 <= 0) {\n v8 = 0;\n } else {\n v6 = a1;\n v7 = &a1[v4];\n v8 = 0;\n while (1) {\n v9 = *v6;\n if (v8 > 0) break;\n LABEL_9:\n ++v6;\n v5[v8++] = v9;\n if (v6 == v7) goto LABEL_10;\n }\n while (1) {\n v10 = v5;\n while (*v10 != v9) {\n if (++v10 == &v5[v8]) goto LABEL_9;\n }\n if (++v6 == v7) break;\n v9 = *v6;\n }\n LABEL_10:\n if (v8 > 1) {\n v11 = v5 + 1;\n for (i = 1LL; i != v8; ++i) {\n if (v8 > (int)i) {\n v13 = v11;\n do {\n v14 = *(v11 - 1);\n if (v14 > *v13) {\n *(v11 - 1) = *v13;\n *v13 = v14;\n }\n ++v13;\n } while (v13 != &v5[i + 1 + (unsigned int)(v8 - 1 - i)]);\n }\n ++v11;\n }\n }\n }\n *a3 = v8;\n return v5;\n}" + }, + { + "index": "HumanEval-C-34", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int *func0(int *l, int size, int *out_size) {\n int *out = malloc(size * sizeof(int));\n int found, out_count = 0, i, j;\n for (i = 0; i < size; i++) {\n found = 0;\n for (j = 0; j < out_count; j++) {\n if (l[i] == out[j]) {\n found = 1;\n break;\n }\n }\n if (!found) {\n out[out_count++] = l[i];\n }\n }\n for (i = 0; i < out_count - 1; i++) {\n for (j = i + 1; j < out_count; j++) {\n if (out[i] > out[j]) {\n int temp = out[i];\n out[i] = out[j];\n out[j] = temp;\n }\n }\n }\n *out_size = out_count;\n return out;\n}", + "test": "#include \n#include \n#include \n\nint main() {\n int test_array[] = {5, 3, 5, 2, 3, 3, 9, 0, 123};\n int expected_array[] = {0, 2, 3, 5, 9, 123};\n int unique_size;\n int *unique_array = func0(test_array, sizeof(test_array) / sizeof(test_array[0]), &unique_size);\n\n assert(unique_size == sizeof(expected_array) / sizeof(expected_array[0]));\n for (int i = 0; i < unique_size; i++) {\n assert(unique_array[i] == expected_array[i]);\n }\n\n free(unique_array);\n printf(\"All tests passed!\\n\");\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\nmov rbp, rdx\npush rbx\nmov rbx, rdi\nmovsxd rdi, esi\nlea r12, ds:0[rdi*4]\nmov r13, rdi\nmov rdi, r12; size\nsub rsp, 8\ncall _malloc\nmov r10, rax\ntest r13d, r13d\njle loc_13B6\nmov rsi, rbx\nlea rdi, [rbx+r12]\nxor r9d, r9d\nloc_1300:\nmovsxd r8, r9d\nmov edx, [rsi]\nlea rcx, [r10+r8*4]\ntest r9d, r9d\njle short loc_1338\nloc_130E:\nmov rax, r10\njmp short loc_1321\nloc_1318:\nadd rax, 4\ncmp rax, rcx\njz short loc_1338\nloc_1321:\ncmp [rax], edx\njnz short loc_1318\nadd rsi, 4\ncmp rsi, rdi\njz short loc_1349\nmov edx, [rsi]\njmp short loc_130E\nloc_1338:\nadd rsi, 4\nmov [r10+r8*4], edx\nadd r9d, 1\ncmp rsi, rdi\njnz short loc_1300\nloc_1349:\ncmp r9d, 1\njle short loc_13A4\nlea rsi, [r10+4]\nmov r11d, r9d\nmov r8d, 1\nlea r12d, [r9-1]\nlea rbx, [r10+8]\nnop dword ptr [rax+00h]\nloc_1368:\ncmp r9d, r8d\njle short loc_1397\nmov eax, r12d\nsub eax, r8d\nlea rax, [r8+rax-1]\nlea rdi, [rbx+rax*4]\nmov rax, rsi\nnop\nloc_1380:\nmov edx, [rsi-4]\nmov ecx, [rax]\ncmp edx, ecx\njle short loc_138E\nmov [rsi-4], ecx\nmov [rax], edx\nloc_138E:\nadd rax, 4\ncmp rdi, rax\njnz short loc_1380\nloc_1397:\nadd r8, 1\nadd rsi, 4\ncmp r8, r11\njnz short loc_1368\nloc_13A4:\nmov [rbp+0], r9d\nadd rsp, 8\nmov rax, r10\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_13B6:\nxor r9d, r9d\njmp short loc_13A4", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2, int *a3)\n{\n size_t v4; // r12\n _DWORD *v5; // r10\n int *v6; // rsi\n int *v7; // rdi\n int v8; // r9d\n int v9; // edx\n _DWORD *v10; // rax\n _DWORD *v11; // rsi\n __int64 i; // r8\n _DWORD *v13; // rax\n int v14; // edx\n\n v4 = a2;\n v5 = malloc(v4 * 4);\n if ( a2 <= 0 )\n {\n v8 = 0;\n }\n else\n {\n v6 = a1;\n v7 = &a1[v4];\n v8 = 0;\n while ( 1 )\n {\n v9 = *v6;\n if ( v8 > 0 )\n break;\nLABEL_9:\n ++v6;\n v5[v8++] = v9;\n if ( v6 == v7 )\n goto LABEL_10;\n }\n while ( 1 )\n {\n v10 = v5;\n while ( *v10 != v9 )\n {\n if ( ++v10 == &v5[v8] )\n goto LABEL_9;\n }\n if ( ++v6 == v7 )\n break;\n v9 = *v6;\n }\nLABEL_10:\n if ( v8 > 1 )\n {\n v11 = v5 + 1;\n for ( i = 1LL; i != v8; ++i )\n {\n if ( v8 > (int)i )\n {\n v13 = v11;\n do\n {\n v14 = *(v11 - 1);\n if ( v14 > *v13 )\n {\n *(v11 - 1) = *v13;\n *v13 = v14;\n }\n ++v13;\n }\n while ( &v5[i + 1 + (unsigned int)(v8 - 1 - i)] != v13 );\n }\n ++v11;\n }\n }\n }\n *a3 = v8;\n return v5;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\npush r13\npush r12\npush rbp\nmov rbp, rdx\npush rbx\nmov rbx, rdi\nmovsxd rdi, esi\nlea r12, ds:0[rdi*4]\nmov r13, rdi\nmov rdi, r12; size\nsub rsp, 8\ncall _malloc\nmov r10, rax\ntest r13d, r13d\njle loc_13B6\nmov rsi, rbx\nlea rdi, [rbx+r12]\nxor r9d, r9d\nloc_1300:\nmovsxd r8, r9d\nmov edx, [rsi]\nlea rcx, [r10+r8*4]\ntest r9d, r9d\njle short loc_1338\nloc_130E:\nmov rax, r10\njmp short loc_1321\nloc_1318:\nadd rax, 4\ncmp rax, rcx\njz short loc_1338\nloc_1321:\ncmp [rax], edx\njnz short loc_1318\nadd rsi, 4\ncmp rsi, rdi\njz short loc_1349\nmov edx, [rsi]\njmp short loc_130E\nloc_1338:\nadd rsi, 4\nmov [r10+r8*4], edx\nadd r9d, 1\ncmp rsi, rdi\njnz short loc_1300\nloc_1349:\ncmp r9d, 1\njle short loc_13A4\nlea rsi, [r10+4]\nmov r11d, r9d\nmov r8d, 1\nlea r12d, [r9-1]\nlea rbx, [r10+8]\nnop dword ptr [rax+00h]\nloc_1368:\ncmp r9d, r8d\njle short loc_1397\nmov eax, r12d\nsub eax, r8d\nlea rax, [r8+rax-1]\nlea rdi, [rbx+rax*4]\nmov rax, rsi\nnop\nloc_1380:\nmov edx, [rsi-4]\nmov ecx, [rax]\ncmp edx, ecx\njle short loc_138E\nmov [rsi-4], ecx\nmov [rax], edx\nloc_138E:\nadd rax, 4\ncmp rdi, rax\njnz short loc_1380\nloc_1397:\nadd r8, 1\nadd rsi, 4\ncmp r8, r11\njnz short loc_1368\nloc_13A4:\nmov [rbp+0], r9d\nadd rsp, 8\nmov rax, r10\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_13B6:\nxor r9d, r9d\njmp short loc_13A4", + "ida_strip_pseudo": "_DWORD *__fastcall sub_12C0(int *a1, int a2, int *a3)\n{\n size_t v4; // r12\n _DWORD *v5; // r10\n int *v6; // rsi\n int *v7; // rdi\n int v8; // r9d\n int v9; // edx\n _DWORD *v10; // rax\n _DWORD *v11; // rsi\n __int64 i; // r8\n _DWORD *v13; // rax\n int v14; // edx\n\n v4 = a2;\n v5 = malloc(v4 * 4);\n if ( a2 <= 0 )\n {\n v8 = 0;\n }\n else\n {\n v6 = a1;\n v7 = &a1[v4];\n v8 = 0;\n while ( 1 )\n {\n v9 = *v6;\n if ( v8 > 0 )\n break;\nLABEL_9:\n ++v6;\n v5[v8++] = v9;\n if ( v6 == v7 )\n goto LABEL_10;\n }\n while ( 1 )\n {\n v10 = v5;\n while ( *v10 != v9 )\n {\n if ( ++v10 == &v5[v8] )\n goto LABEL_9;\n }\n if ( ++v6 == v7 )\n break;\n v9 = *v6;\n }\nLABEL_10:\n if ( v8 > 1 )\n {\n v11 = v5 + 1;\n for ( i = 1LL; i != v8; ++i )\n {\n if ( v8 > (int)i )\n {\n v13 = v11;\n do\n {\n v14 = *(v11 - 1);\n if ( v14 > *v13 )\n {\n *(v11 - 1) = *v13;\n *v13 = v14;\n }\n ++v13;\n }\n while ( &v5[i + 1 + (unsigned int)(v8 - 1 - i)] != v13 );\n }\n ++v11;\n }\n }\n }\n *a3 = v8;\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_12C0(int *a1, int a2, int *a3) {\n unsigned int v4;\n uint32_t *v5;\n int *v6;\n int *v7;\n int v8;\n int v9;\n uint32_t *v10;\n uint32_t *v11;\n long long i;\n uint32_t *v13;\n int v14;\n v4 = a2;\n v5 = malloc(v4 * 4);\n if (a2 <= 0) {\n v8 = 0;\n } else {\n v6 = a1;\n v7 = &a1[v4];\n v8 = 0;\n while (1) {\n v9 = *v6;\n if (v8 > 0) break;\n LABEL_9:\n ++v6;\n v5[v8++] = v9;\n if (v6 == v7) goto LABEL_10;\n }\n while (1) {\n v10 = v5;\n while (*v10 != v9) {\n if (++v10 == &v5[v8]) goto LABEL_9;\n }\n if (++v6 == v7) break;\n v9 = *v6;\n }\n LABEL_10:\n if (v8 > 1) {\n v11 = v5 + 1;\n for (i = 1LL; i != v8; ++i) {\n if (v8 > (int)i) {\n v13 = v11;\n do {\n v14 = *(v11 - 1);\n if (v14 > *v13) {\n *(v11 - 1) = *v13;\n *v13 = v14;\n }\n ++v13;\n } while (&v5[i + 1 + (unsigned int)(v8 - 1 - i)] != v13);\n }\n ++v11;\n }\n }\n }\n *a3 = v8;\n return v5;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2, int *a3) {\n unsigned int v4;\n uint32_t *v5;\n int *v6;\n int *v7;\n int v8;\n int v9;\n uint32_t *v10;\n uint32_t *v11;\n long long i;\n uint32_t *v13;\n int v14;\n v4 = a2;\n v5 = malloc(v4 * 4);\n if (a2 <= 0) {\n v8 = 0;\n } else {\n v6 = a1;\n v7 = &a1[v4];\n v8 = 0;\n while (1) {\n v9 = *v6;\n if (v8 > 0) break;\n LABEL_9:\n ++v6;\n v5[v8++] = v9;\n if (v6 == v7) goto LABEL_10;\n }\n while (1) {\n v10 = v5;\n while (*v10 != v9) {\n if (++v10 == &v5[v8]) goto LABEL_9;\n }\n if (++v6 == v7) break;\n v9 = *v6;\n }\n LABEL_10:\n if (v8 > 1) {\n v11 = v5 + 1;\n for (i = 1LL; i != v8; ++i) {\n if (v8 > (int)i) {\n v13 = v11;\n do {\n v14 = *(v11 - 1);\n if (v14 > *v13) {\n *(v11 - 1) = *v13;\n *v13 = v14;\n }\n ++v13;\n } while (&v5[i + 1 + (unsigned int)(v8 - 1 - i)] != v13);\n }\n ++v11;\n }\n }\n }\n *a3 = v8;\n return v5;\n}" + }, + { + "index": "HumanEval-C-35", + "func_name": "func0", + "func_dep": "#include \n", + "func": "float func0(float *l, int size) {\n float max = -10000;\n for (int i = 0; i < size; i++)\n if (max < l[i]) max = l[i];\n return max;\n}", + "test": "#include \n#include \n#include \n\nint main() {\n float list1[] = {1, 2, 3};\n assert(fabs(func0(list1, 3) - 3) < 1e-4);\n\n float list2[] = {5, 3, -5, 2, -3, 3, 9, 0, 124, 1, -10};\n assert(fabs(func0(list2, 11) - 124) < 1e-4);\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmovss xmm0, cs:dword_2084\nmovss [rbp+var_8], xmm0\nmov [rbp+var_4], 0\njmp short loc_11CD\nloc_118E:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\ncomiss xmm0, [rbp+var_8]\njbe short loc_11C9\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\nmovss [rbp+var_8], xmm0\nloc_11C9:\nadd [rbp+var_4], 1\nloc_11CD:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_118E\nmovss xmm0, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "float __fastcall func0(__int64 a1, int a2)\n{\n float v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = -10000.0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(float *)(4LL * i + a1) > v3 )\n v3 = *(float *)(4LL * i + a1);\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmovss xmm0, cs:dword_2084\nmovss [rbp+var_8], xmm0\nmov [rbp+var_4], 0\njmp short loc_11CD\nloc_118E:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\ncomiss xmm0, [rbp+var_8]\njbe short loc_11C9\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\nmovss [rbp+var_8], xmm0\nloc_11C9:\nadd [rbp+var_4], 1\nloc_11CD:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_118E\nmovss xmm0, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "float __fastcall sub_1169(__int64 a1, int a2)\n{\n float v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = -10000.0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(float *)(4LL * i + a1) > v3 )\n v3 = *(float *)(4LL * i + a1);\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "float sub_1169(long long a1, int a2) {\n float v3;\n int i;\n v3 = -10000.0;\n for (i = 0; i < a2; ++i) {\n if (*(float *)(4LL * i + a1) > v3) v3 = *(float *)(4LL * i + a1);\n }\n return v3;\n}", + "ida_pseudo_norm": "float func0(long long a1, int a2) {\n float v3;\n int i;\n v3 = -10000.0;\n for (i = 0; i < a2; ++i) {\n if (*(float *)(4LL * i + a1) > v3) v3 = *(float *)(4LL * i + a1);\n }\n return v3;\n}" + }, + { + "index": "HumanEval-C-35", + "func_name": "func0", + "func_dep": "#include \n", + "func": "float func0(float *l, int size) {\n float max = -10000;\n for (int i = 0; i < size; i++)\n if (max < l[i]) max = l[i];\n return max;\n}", + "test": "#include \n#include \n#include \n\nint main() {\n float list1[] = {1, 2, 3};\n assert(fabs(func0(list1, 3) - 3) < 1e-4);\n\n float list2[] = {5, 3, -5, 2, -3, 3, 9, 0, 124, 1, -10};\n assert(fabs(func0(list2, 11) - 124) < 1e-4);\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1198\nmov rax, rdi\nmovsxd rsi, esi\nlea rdx, [rdi+rsi*4]\nmovss xmm0, cs:dword_2004\nloc_1183:\nmovss xmm1, dword ptr [rax]\nmaxss xmm1, xmm0\nmovaps xmm0, xmm1\nadd rax, 4\ncmp rax, rdx\njnz short loc_1183\nretn\nloc_1198:\nmovss xmm0, cs:dword_2004\nretn", + "ida_pseudo": "float __fastcall func0(float *a1, int a2)\n{\n float *v2; // rax\n float result; // xmm0_4\n\n if ( a2 <= 0 )\n return -10000.0;\n v2 = a1;\n result = -10000.0;\n do\n result = fmaxf(*v2++, result);\n while ( v2 != &a1[a2] );\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_1198\nmov rax, rdi\nmovsxd rsi, esi\nlea rdx, [rdi+rsi*4]\nmovss xmm0, cs:dword_2004\nloc_1183:\nmovss xmm1, dword ptr [rax]\nmaxss xmm1, xmm0\nmovaps xmm0, xmm1\nadd rax, 4\ncmp rax, rdx\njnz short loc_1183\nretn\nloc_1198:\nmovss xmm0, cs:dword_2004\nretn", + "ida_strip_pseudo": "float __fastcall sub_1169(float *a1, int a2)\n{\n float *v2; // rax\n float result; // xmm0_4\n\n if ( a2 <= 0 )\n return -10000.0;\n v2 = a1;\n result = -10000.0;\n do\n result = fmaxf(*v2++, result);\n while ( v2 != &a1[a2] );\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "float sub_1169(float *a1, int a2) {\n float *v2;\n float result;\n if (a2 <= 0) return -10000.0;\n v2 = a1;\n result = -10000.0;\n do\n result = fmaxf(*v2++, result);\n while (v2 != &a1[a2]);\n return result;\n}", + "ida_pseudo_norm": "float func0(float *a1, int a2) {\n float *v2;\n float result;\n if (a2 <= 0) return -10000.0;\n v2 = a1;\n result = -10000.0;\n do\n result = fmaxf(*v2++, result);\n while (v2 != &a1[a2]);\n return result;\n}" + }, + { + "index": "HumanEval-C-36", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int n) {\n int count = 0;\n for (int i = 0; i < n; i++)\n if (i % 11 == 0 || i % 13 == 0) {\n int q = i;\n while (q > 0) {\n if (q % 10 == 7) count += 1;\n q = q / 10;\n }\n }\n return count;\n}", + "test": "#include \n#include \n\nint main() {\n assert(func0(50) == 0);\n assert(func0(78) == 2);\n assert(func0(79) == 3);\n assert(func0(100) == 3);\n assert(func0(200) == 6);\n assert(func0(4000) == 192);\n assert(func0(10000) == 639);\n assert(func0(100000) == 8026);\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp loc_1229\nloc_1167:\nmov ecx, [rbp+var_8]\nmovsxd rax, ecx\nimul rax, 2E8BA2E9h\nshr rax, 20h\nmov edx, eax\nsar edx, 1\nmov eax, ecx\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nadd eax, edx\nsub ecx, eax\nmov edx, ecx\ntest edx, edx\njz short loc_11C6\nmov ecx, [rbp+var_8]\nmovsxd rax, ecx\nimul rax, 4EC4EC4Fh\nshr rax, 20h\nmov edx, eax\nsar edx, 2\nmov eax, ecx\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\nadd eax, eax\nadd eax, edx\nshl eax, 2\nadd eax, edx\nsub ecx, eax\nmov edx, ecx\ntest edx, edx\njnz short loc_1225\nloc_11C6:\nmov eax, [rbp+var_8]\nmov [rbp+var_4], eax\njmp short loc_121F\nloc_11CE:\nmov ecx, [rbp+var_4]\nmovsxd rax, ecx\nimul rax, 66666667h\nshr rax, 20h\nmov edx, eax\nsar edx, 2\nmov eax, ecx\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nsub ecx, eax\nmov edx, ecx\ncmp edx, 7\njnz short loc_1201\nadd [rbp+var_C], 1\nloc_1201:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_4], eax\nloc_121F:\ncmp [rbp+var_4], 0\njg short loc_11CE\nloc_1225:\nadd [rbp+var_8], 1\nloc_1229:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_14]\njl loc_1167\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v2; // [rsp+8h] [rbp-Ch]\n int i; // [rsp+Ch] [rbp-8h]\n int j; // [rsp+10h] [rbp-4h]\n\n v2 = 0;\n for ( i = 0; i < a1; ++i )\n {\n if ( !(i % 11) || !(i % 13) )\n {\n for ( j = i; j > 0; j /= 10 )\n {\n if ( j % 10 == 7 )\n ++v2;\n }\n }\n }\n return v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp loc_1229\nloc_1167:\nmov ecx, [rbp+var_8]\nmovsxd rax, ecx\nimul rax, 2E8BA2E9h\nshr rax, 20h\nmov edx, eax\nsar edx, 1\nmov eax, ecx\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nadd eax, edx\nsub ecx, eax\nmov edx, ecx\ntest edx, edx\njz short loc_11C6\nmov ecx, [rbp+var_8]\nmovsxd rax, ecx\nimul rax, 4EC4EC4Fh\nshr rax, 20h\nmov edx, eax\nsar edx, 2\nmov eax, ecx\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\nadd eax, eax\nadd eax, edx\nshl eax, 2\nadd eax, edx\nsub ecx, eax\nmov edx, ecx\ntest edx, edx\njnz short loc_1225\nloc_11C6:\nmov eax, [rbp+var_8]\nmov [rbp+var_4], eax\njmp short loc_121F\nloc_11CE:\nmov ecx, [rbp+var_4]\nmovsxd rax, ecx\nimul rax, 66666667h\nshr rax, 20h\nmov edx, eax\nsar edx, 2\nmov eax, ecx\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nsub ecx, eax\nmov edx, ecx\ncmp edx, 7\njnz short loc_1201\nadd [rbp+var_C], 1\nloc_1201:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_4], eax\nloc_121F:\ncmp [rbp+var_4], 0\njg short loc_11CE\nloc_1225:\nadd [rbp+var_8], 1\nloc_1229:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_14]\njl loc_1167\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n unsigned int v2; // [rsp+8h] [rbp-Ch]\n int i; // [rsp+Ch] [rbp-8h]\n int j; // [rsp+10h] [rbp-4h]\n\n v2 = 0;\n for ( i = 0; i < a1; ++i )\n {\n if ( !(i % 11) || !(i % 13) )\n {\n for ( j = i; j > 0; j /= 10 )\n {\n if ( j % 10 == 7 )\n ++v2;\n }\n }\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n unsigned int v2;\n int i;\n int j;\n v2 = 0;\n for (i = 0; i < a1; ++i) {\n if (!(i % 11) || !(i % 13)) {\n for (j = i; j > 0; j /= 10) {\n if (j % 10 == 7) ++v2;\n }\n }\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v2;\n int i;\n int j;\n v2 = 0;\n for (i = 0; i < a1; ++i) {\n if (!(i % 11) || !(i % 13)) {\n for (j = i; j > 0; j /= 10) {\n if (j % 10 == 7) ++v2;\n }\n }\n }\n return v2;\n}" + }, + { + "index": "HumanEval-C-36", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int n) {\n int count = 0;\n for (int i = 0; i < n; i++)\n if (i % 11 == 0 || i % 13 == 0) {\n int q = i;\n while (q > 0) {\n if (q % 10 == 7) count += 1;\n q = q / 10;\n }\n }\n return count;\n}", + "test": "#include \n#include \n\nint main() {\n assert(func0(50) == 0);\n assert(func0(78) == 2);\n assert(func0(79) == 3);\n assert(func0(100) == 3);\n assert(func0(200) == 6);\n assert(func0(4000) == 192);\n assert(func0(10000) == 639);\n assert(func0(100000) == 8026);\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njle loc_1200\nmov ecx, 0\nmov esi, 0\njmp short loc_11B6\nloc_1161:\nmov edx, eax\nloc_1163:\nmovsxd rax, edx\nimul rax, 66666667h\nsar rax, 22h\nmov r8d, edx\nsar r8d, 1Fh\nsub eax, r8d\nlea eax, [rax+rax*4]\nadd eax, eax\nmov r8d, edx\nsub r8d, eax\ncmp r8d, 7\nsetz al\nmovzx eax, al\nadd esi, eax\nmovsxd rax, edx\nimul rax, 66666667h\nsar rax, 22h\nmov r8d, edx\nsar r8d, 1Fh\nsub eax, r8d\ncmp edx, 9\njg short loc_1161\nloc_11AF:\nadd ecx, 1\ncmp edi, ecx\njz short loc_1205\nloc_11B6:\nmovsxd rax, ecx\nimul rax, 2E8BA2E9h\nsar rax, 21h\nmov edx, ecx\nsar edx, 1Fh\nsub eax, edx\nlea edx, [rax+rax*4]\nlea eax, [rax+rdx*2]\ncmp ecx, eax\njz short loc_11F4\nmovsxd rax, ecx\nimul rax, 4EC4EC4Fh\nsar rax, 22h\nmov edx, ecx\nsar edx, 1Fh\nsub eax, edx\nlea edx, [rax+rax*2]\nlea eax, [rax+rdx*4]\ncmp ecx, eax\njnz short loc_11AF\nloc_11F4:\nmov edx, ecx\ntest ecx, ecx\njg loc_1163\njmp short loc_11AF\nloc_1200:\nmov esi, 0\nloc_1205:\nmov eax, esi\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // ecx\n unsigned int v2; // esi\n int v3; // edx\n\n if ( a1 <= 0 )\n {\n return 0;\n }\n else\n {\n v1 = 0;\n v2 = 0;\n do\n {\n if ( v1 == 11 * (v1 / 11) || v1 == 13 * (v1 / 13) )\n {\n v3 = v1;\n if ( v1 > 0 )\n {\n while ( 1 )\n {\n v2 += v3 % 10 == 7;\n if ( v3 <= 9 )\n break;\n v3 /= 10;\n }\n }\n }\n ++v1;\n }\n while ( a1 != v1 );\n }\n return v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ntest edi, edi\njle loc_1200\nmov ecx, 0\nmov esi, 0\njmp short loc_11B6\nloc_1161:\nmov edx, eax\nloc_1163:\nmovsxd rax, edx\nimul rax, 66666667h\nsar rax, 22h\nmov r8d, edx\nsar r8d, 1Fh\nsub eax, r8d\nlea eax, [rax+rax*4]\nadd eax, eax\nmov r8d, edx\nsub r8d, eax\ncmp r8d, 7\nsetz al\nmovzx eax, al\nadd esi, eax\nmovsxd rax, edx\nimul rax, 66666667h\nsar rax, 22h\nmov r8d, edx\nsar r8d, 1Fh\nsub eax, r8d\ncmp edx, 9\njg short loc_1161\nloc_11AF:\nadd ecx, 1\ncmp edi, ecx\njz short loc_1205\nloc_11B6:\nmovsxd rax, ecx\nimul rax, 2E8BA2E9h\nsar rax, 21h\nmov edx, ecx\nsar edx, 1Fh\nsub eax, edx\nlea edx, [rax+rax*4]\nlea eax, [rax+rdx*2]\ncmp ecx, eax\njz short loc_11F4\nmovsxd rax, ecx\nimul rax, 4EC4EC4Fh\nsar rax, 22h\nmov edx, ecx\nsar edx, 1Fh\nsub eax, edx\nlea edx, [rax+rax*2]\nlea eax, [rax+rdx*4]\ncmp ecx, eax\njnz short loc_11AF\nloc_11F4:\nmov edx, ecx\ntest ecx, ecx\njg loc_1163\njmp short loc_11AF\nloc_1200:\nmov esi, 0\nloc_1205:\nmov eax, esi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v1; // ecx\n unsigned int v2; // esi\n int v3; // edx\n\n if ( a1 <= 0 )\n {\n return 0;\n }\n else\n {\n v1 = 0;\n v2 = 0;\n do\n {\n if ( v1 == 11 * (v1 / 11) || v1 == 13 * (v1 / 13) )\n {\n v3 = v1;\n if ( v1 > 0 )\n {\n while ( 1 )\n {\n v2 += v3 % 10 == 7;\n if ( v3 <= 9 )\n break;\n v3 /= 10;\n }\n }\n }\n ++v1;\n }\n while ( a1 != v1 );\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v1;\n unsigned int v2;\n int v3;\n if (a1 <= 0) {\n return 0;\n } else {\n v1 = 0;\n v2 = 0;\n do {\n if (v1 == 11 * (v1 / 11) || v1 == 13 * (v1 / 13)) {\n v3 = v1;\n if (v1 > 0) {\n while (1) {\n v2 += v3 % 10 == 7;\n if (v3 <= 9) break;\n v3 /= 10;\n }\n }\n }\n ++v1;\n } while (a1 != v1);\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n unsigned int v2;\n int v3;\n if (a1 <= 0) {\n return 0;\n } else {\n v1 = 0;\n v2 = 0;\n do {\n if (v1 == 11 * (v1 / 11) || v1 == 13 * (v1 / 13)) {\n v3 = v1;\n if (v1 > 0) {\n while (1) {\n v2 += v3 % 10 == 7;\n if (v3 <= 9) break;\n v3 /= 10;\n }\n }\n }\n ++v1;\n } while (a1 != v1);\n }\n return v2;\n}" + }, + { + "index": "HumanEval-C-36", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int n) {\n int count = 0;\n for (int i = 0; i < n; i++)\n if (i % 11 == 0 || i % 13 == 0) {\n int q = i;\n while (q > 0) {\n if (q % 10 == 7) count += 1;\n q = q / 10;\n }\n }\n return count;\n}", + "test": "#include \n#include \n\nint main() {\n assert(func0(50) == 0);\n assert(func0(78) == 2);\n assert(func0(79) == 3);\n assert(func0(100) == 3);\n assert(func0(200) == 6);\n assert(func0(4000) == 192);\n assert(func0(10000) == 639);\n assert(func0(100000) == 8026);\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nxor r8d, r8d\nxor esi, esi\nmov r9d, 0CCCCCCCDh\ntest edi, edi\njle short loc_135B\nnop dword ptr [rax+rax+00h]\nloc_1308:\nadd r8d, 1\ncmp edi, r8d\njz short loc_135B\nloc_1311:\nimul eax, r8d, 0BA2E8BA3h\ncmp eax, 1745D174h\njbe short loc_132D\nimul eax, r8d, 0C4EC4EC5h\ncmp eax, 13B13B13h\nja short loc_1308\nloc_132D:\nmov edx, r8d\nloc_1330:\nmov eax, edx\nimul rax, r9\nshr rax, 23h\nlea ecx, [rax+rax*4]\nadd ecx, ecx\nsub edx, ecx\ncmp edx, 7\nsetz dl\nmovzx edx, dl\nadd esi, edx\nmov edx, eax\ntest eax, eax\njnz short loc_1330\nadd r8d, 1\ncmp edi, r8d\njnz short loc_1311\nloc_135B:\nmov eax, esi\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v1; // r8d\n unsigned int v2; // esi\n unsigned int v3; // edx\n\n v1 = 0;\n v2 = 0;\n if ( a1 > 0 )\n {\n while ( a1 != ++v1 )\n {\n while ( -1171354717 * v1 <= 0x1745D174 || -991146299 * v1 <= 0x13B13B13 )\n {\n v3 = v1;\n do\n {\n v2 += v3 % 0xA == 7;\n v3 /= 0xAu;\n }\n while ( v3 );\n if ( a1 == ++v1 )\n return v2;\n }\n }\n }\n return v2;\n}", + "ida_strip_asm": "sub_12F0:\nendbr64\nxor r8d, r8d\nxor esi, esi\nmov r9d, 0CCCCCCCDh\ntest edi, edi\njle short loc_135B\nnop dword ptr [rax+rax+00h]\nloc_1308:\nadd r8d, 1\ncmp edi, r8d\njz short loc_135B\nloc_1311:\nimul eax, r8d, 0BA2E8BA3h\ncmp eax, 1745D174h\njbe short loc_132D\nimul eax, r8d, 0C4EC4EC5h\ncmp eax, 13B13B13h\nja short loc_1308\nloc_132D:\nmov edx, r8d\nloc_1330:\nmov eax, edx\nimul rax, r9\nshr rax, 23h\nlea ecx, [rax+rax*4]\nadd ecx, ecx\nsub edx, ecx\ncmp edx, 7\nsetz dl\nmovzx edx, dl\nadd esi, edx\nmov edx, eax\ntest eax, eax\njnz short loc_1330\nadd r8d, 1\ncmp edi, r8d\njnz short loc_1311\nloc_135B:\nmov eax, esi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12F0(int a1)\n{\n unsigned int v1; // r8d\n unsigned int v2; // esi\n unsigned int v3; // edx\n\n v1 = 0;\n v2 = 0;\n if ( a1 > 0 )\n {\n while ( a1 != ++v1 )\n {\n while ( -1171354717 * v1 <= 0x1745D174 || -991146299 * v1 <= 0x13B13B13 )\n {\n v3 = v1;\n do\n {\n v2 += v3 % 0xA == 7;\n v3 /= 0xAu;\n }\n while ( v3 );\n if ( a1 == ++v1 )\n return v2;\n }\n }\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12F0(int a1) {\n unsigned int v1;\n unsigned int v2;\n unsigned int v3;\n v1 = 0;\n v2 = 0;\n if (a1 > 0) {\n while (a1 != ++v1) {\n while (-1171354717 * v1 <= 390451572 || -991146299 * v1 <= 330382099) {\n v3 = v1;\n do {\n v2 += v3 % 10 == 7;\n v3 /= 10u;\n } while (v3);\n if (a1 == ++v1) return v2;\n }\n }\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v1;\n unsigned int v2;\n unsigned int v3;\n v1 = 0;\n v2 = 0;\n if (a1 > 0) {\n while (a1 != ++v1) {\n while (-1171354717 * v1 <= 390451572 || -991146299 * v1 <= 330382099) {\n v3 = v1;\n do {\n v2 += v3 % 10 == 7;\n v3 /= 10u;\n } while (v3);\n if (a1 == ++v1) return v2;\n }\n }\n }\n return v2;\n}" + }, + { + "index": "HumanEval-C-37", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "void func0(float *l, int size, float *out) {\n float *even = malloc((size / 2 + 1) * sizeof(float));\n int i, j, even_count = 0;\n for (i = 0; i < size; i += 2) {\n even[even_count++] = l[i];\n }\n for (i = 0; i < even_count - 1; i++) {\n for (j = 0; j < even_count - i - 1; j++) {\n if (even[j] > even[j + 1]) {\n float temp = even[j];\n even[j] = even[j + 1];\n even[j + 1] = temp;\n }\n }\n }\n for (i = 0; i < size; i++) {\n if (i % 2 == 0) {\n out[i] = even[i / 2];\n } else {\n out[i] = l[i];\n }\n }\n free(even);\n}", + "test": "#include \n#include \n#include \n\n\nint issame(float *a, float *b, int size) {\n for (int i = 0; i < size; i++) {\n if (fabs(a[i] - b[i]) > 1e-4) {\n return 0;\n }\n }\n return 1;\n}\n\nint main() {\n float test1[] = {1, 2, 3};\n float result1[3];\n func0(test1, 3, result1);\n float expected1[] = {1, 2, 3};\n assert(issame(result1, expected1, 3));\n\n float test2[] = {5, 3, -5, 2, -3, 3, 9, 0, 123, 1, -10};\n float result2[11];\n func0(test2, 11, result2);\n float expected2[] = {-10, 3, -5, 2, -3, 3, 5, 0, 9, 1, 123};\n assert(issame(result2, expected2, 11));\n\n float test3[] = {5, 8, -12, 4, 23, 2, 3, 11, 12, -10};\n float result3[10];\n func0(test3, 10, result3);\n float expected3[] = {-12, 8, 3, 4, 5, 2, 12, 11, 23, -10};\n assert(issame(result3, expected3, 10));\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmov eax, [rbp+var_2C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nadd eax, 1\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov [rbp+var_10], 0\nmov [rbp+var_18], 0\njmp short loc_122C\nloc_11F1:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmovss xmm0, dword ptr [rcx]\nmovss dword ptr [rax], xmm0\nadd [rbp+var_18], 2\nloc_122C:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_2C]\njl short loc_11F1\nmov [rbp+var_18], 0\njmp loc_1311\nloc_1240:\nmov [rbp+var_14], 0\njmp loc_12FB\nloc_124C:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\nmov eax, [rbp+var_14]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmovss xmm1, dword ptr [rax]\ncomiss xmm0, xmm1\njbe short loc_12F7\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\nmovss [rbp+var_C], xmm0\nmov eax, [rbp+var_14]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov eax, [rbp+var_14]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rcx\nmovss xmm0, dword ptr [rdx]\nmovss dword ptr [rax], xmm0\nmov eax, [rbp+var_14]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmovss xmm0, [rbp+var_C]\nmovss dword ptr [rax], xmm0\nloc_12F7:\nadd [rbp+var_14], 1\nloc_12FB:\nmov eax, [rbp+var_10]\nsub eax, [rbp+var_18]\nsub eax, 1\ncmp [rbp+var_14], eax\njl loc_124C\nadd [rbp+var_18], 1\nloc_1311:\nmov eax, [rbp+var_10]\nsub eax, 1\ncmp [rbp+var_18], eax\njl loc_1240\nmov [rbp+var_18], 0\njmp short loc_13A2\nloc_1329:\nmov eax, [rbp+var_18]\nand eax, 1\ntest eax, eax\njnz short loc_136E\nmov eax, [rbp+var_18]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov eax, [rbp+var_18]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmovss xmm0, dword ptr [rdx]\nmovss dword ptr [rax], xmm0\njmp short loc_139E\nloc_136E:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov eax, [rbp+var_18]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmovss xmm0, dword ptr [rdx]\nmovss dword ptr [rax], xmm0\nloc_139E:\nadd [rbp+var_18], 1\nloc_13A2:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_2C]\njl loc_1329\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nnop\nleave\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2, __int64 a3)\n{\n int v3; // eax\n _DWORD *v4; // rdx\n int i; // [rsp+28h] [rbp-18h]\n int j; // [rsp+28h] [rbp-18h]\n int m; // [rsp+28h] [rbp-18h]\n int k; // [rsp+2Ch] [rbp-14h]\n int v10; // [rsp+30h] [rbp-10h]\n int v11; // [rsp+34h] [rbp-Ch]\n _DWORD *ptr; // [rsp+38h] [rbp-8h]\n\n ptr = malloc(4LL * (a2 / 2 + 1));\n v10 = 0;\n for ( i = 0; i < a2; i += 2 )\n {\n v3 = v10++;\n ptr[v3] = *(_DWORD *)(4LL * i + a1);\n }\n for ( j = 0; j < v10 - 1; ++j )\n {\n for ( k = 0; k < v10 - j - 1; ++k )\n {\n if ( *(float *)&ptr[k] > *(float *)&ptr[k + 1] )\n {\n v11 = ptr[k];\n ptr[k] = ptr[k + 1];\n ptr[k + 1] = v11;\n }\n }\n }\n for ( m = 0; m < a2; ++m )\n {\n if ( (m & 1) != 0 )\n v4 = (_DWORD *)(a1 + 4LL * m);\n else\n v4 = &ptr[m / 2];\n *(_DWORD *)(4LL * m + a3) = *v4;\n }\n free(ptr);\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmov eax, [rbp+var_2C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nadd eax, 1\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov [rbp+var_10], 0\nmov [rbp+var_18], 0\njmp short loc_122C\nloc_11F1:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmovss xmm0, dword ptr [rcx]\nmovss dword ptr [rax], xmm0\nadd [rbp+var_18], 2\nloc_122C:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_2C]\njl short loc_11F1\nmov [rbp+var_18], 0\njmp loc_1311\nloc_1240:\nmov [rbp+var_14], 0\njmp loc_12FB\nloc_124C:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\nmov eax, [rbp+var_14]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmovss xmm1, dword ptr [rax]\ncomiss xmm0, xmm1\njbe short loc_12F7\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\nmovss [rbp+var_C], xmm0\nmov eax, [rbp+var_14]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov eax, [rbp+var_14]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rcx\nmovss xmm0, dword ptr [rdx]\nmovss dword ptr [rax], xmm0\nmov eax, [rbp+var_14]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmovss xmm0, [rbp+var_C]\nmovss dword ptr [rax], xmm0\nloc_12F7:\nadd [rbp+var_14], 1\nloc_12FB:\nmov eax, [rbp+var_10]\nsub eax, [rbp+var_18]\nsub eax, 1\ncmp [rbp+var_14], eax\njl loc_124C\nadd [rbp+var_18], 1\nloc_1311:\nmov eax, [rbp+var_10]\nsub eax, 1\ncmp [rbp+var_18], eax\njl loc_1240\nmov [rbp+var_18], 0\njmp short loc_13A2\nloc_1329:\nmov eax, [rbp+var_18]\nand eax, 1\ntest eax, eax\njnz short loc_136E\nmov eax, [rbp+var_18]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov eax, [rbp+var_18]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmovss xmm0, dword ptr [rdx]\nmovss dword ptr [rax], xmm0\njmp short loc_139E\nloc_136E:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov eax, [rbp+var_18]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmovss xmm0, dword ptr [rdx]\nmovss dword ptr [rax], xmm0\nloc_139E:\nadd [rbp+var_18], 1\nloc_13A2:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_2C]\njl loc_1329\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nnop\nleave\nretn", + "ida_strip_pseudo": "void __fastcall sub_11A9(__int64 a1, int a2, __int64 a3)\n{\n int v3; // eax\n _DWORD *v4; // rdx\n int i; // [rsp+28h] [rbp-18h]\n int j; // [rsp+28h] [rbp-18h]\n int m; // [rsp+28h] [rbp-18h]\n int k; // [rsp+2Ch] [rbp-14h]\n int v10; // [rsp+30h] [rbp-10h]\n int v11; // [rsp+34h] [rbp-Ch]\n _DWORD *ptr; // [rsp+38h] [rbp-8h]\n\n ptr = malloc(4LL * (a2 / 2 + 1));\n v10 = 0;\n for ( i = 0; i < a2; i += 2 )\n {\n v3 = v10++;\n ptr[v3] = *(_DWORD *)(4LL * i + a1);\n }\n for ( j = 0; j < v10 - 1; ++j )\n {\n for ( k = 0; k < v10 - j - 1; ++k )\n {\n if ( *(float *)&ptr[k] > *(float *)&ptr[k + 1] )\n {\n v11 = ptr[k];\n ptr[k] = ptr[k + 1];\n ptr[k + 1] = v11;\n }\n }\n }\n for ( m = 0; m < a2; ++m )\n {\n if ( (m & 1) != 0 )\n v4 = (_DWORD *)(a1 + 4LL * m);\n else\n v4 = &ptr[m / 2];\n *(_DWORD *)(4LL * m + a3) = *v4;\n }\n free(ptr);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_11A9(long long a1, int a2, long long a3) {\n int v3;\n uint32_t *v4;\n int i;\n int j;\n int m;\n int k;\n int v10;\n int v11;\n uint32_t *ptr;\n ptr = malloc(4LL * (a2 / 2 + 1));\n v10 = 0;\n for (i = 0; i < a2; i += 2) {\n v3 = v10++;\n ptr[v3] = *(uint32_t *)(4LL * i + a1);\n }\n for (j = 0; j < v10 - 1; ++j) {\n for (k = 0; k < v10 - j - 1; ++k) {\n if (*(float *)&ptr[k] > *(float *)&ptr[k + 1]) {\n v11 = ptr[k];\n ptr[k] = ptr[k + 1];\n ptr[k + 1] = v11;\n }\n }\n }\n for (m = 0; m < a2; ++m) {\n if ((m & 1) != 0)\n v4 = (uint32_t *)(a1 + 4LL * m);\n else\n v4 = &ptr[m / 2];\n *(uint32_t *)(4LL * m + a3) = *v4;\n }\n free(ptr);\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2, long long a3) {\n int v3;\n uint32_t *v4;\n int i;\n int j;\n int m;\n int k;\n int v10;\n int v11;\n uint32_t *ptr;\n ptr = malloc(4LL * (a2 / 2 + 1));\n v10 = 0;\n for (i = 0; i < a2; i += 2) {\n v3 = v10++;\n ptr[v3] = *(uint32_t *)(4LL * i + a1);\n }\n for (j = 0; j < v10 - 1; ++j) {\n for (k = 0; k < v10 - j - 1; ++k) {\n if (*(float *)&ptr[k] > *(float *)&ptr[k + 1]) {\n v11 = ptr[k];\n ptr[k] = ptr[k + 1];\n ptr[k + 1] = v11;\n }\n }\n }\n for (m = 0; m < a2; ++m) {\n if ((m & 1) != 0)\n v4 = (uint32_t *)(a1 + 4LL * m);\n else\n v4 = &ptr[m / 2];\n *(uint32_t *)(4LL * m + a3) = *v4;\n }\n free(ptr);\n}" + }, + { + "index": "HumanEval-C-37", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "void func0(float *l, int size, float *out) {\n float *even = malloc((size / 2 + 1) * sizeof(float));\n int i, j, even_count = 0;\n for (i = 0; i < size; i += 2) {\n even[even_count++] = l[i];\n }\n for (i = 0; i < even_count - 1; i++) {\n for (j = 0; j < even_count - i - 1; j++) {\n if (even[j] > even[j + 1]) {\n float temp = even[j];\n even[j] = even[j + 1];\n even[j + 1] = temp;\n }\n }\n }\n for (i = 0; i < size; i++) {\n if (i % 2 == 0) {\n out[i] = even[i / 2];\n } else {\n out[i] = l[i];\n }\n }\n free(even);\n}", + "test": "#include \n#include \n#include \n\n\nint issame(float *a, float *b, int size) {\n for (int i = 0; i < size; i++) {\n if (fabs(a[i] - b[i]) > 1e-4) {\n return 0;\n }\n }\n return 1;\n}\n\nint main() {\n float test1[] = {1, 2, 3};\n float result1[3];\n func0(test1, 3, result1);\n float expected1[] = {1, 2, 3};\n assert(issame(result1, expected1, 3));\n\n float test2[] = {5, 3, -5, 2, -3, 3, 9, 0, 123, 1, -10};\n float result2[11];\n func0(test2, 11, result2);\n float expected2[] = {-10, 3, -5, 2, -3, 3, 5, 0, 9, 1, 123};\n assert(issame(result2, expected2, 11));\n\n float test3[] = {5, 8, -12, 4, 23, 2, 3, 11, 12, -10};\n float result3[10];\n func0(test3, 10, result3);\n float expected3[] = {-12, 8, 3, 4, 5, 2, 12, 11, 23, -10};\n assert(issame(result3, expected3, 10));\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbp, rdi\nmov ebx, esi\nmov r12, rdx\nmov edi, esi\nshr edi, 1Fh\nadd edi, esi\nsar edi, 1\nadd edi, 1\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov rdi, rax; ptr\ntest ebx, ebx\njle loc_127F\nmov eax, 0\nloc_11E1:\nmovss xmm0, dword ptr [rbp+rax*4+0]\nmovss dword ptr [rdi+rax*2], xmm0\nadd rax, 2\ncmp ebx, eax\njg short loc_11E1\nlea esi, [rbx-1]\nshr esi, 1\njz loc_1289\nmov ecx, 0\nlea r8d, [rsi+1]\nlea r10d, [rsi-1]\nlea r9, [rdi+4]\njmp short loc_123B\nloc_1212:\nadd rax, 4\ncmp rax, rdx\njz short loc_1234\nloc_121B:\nmovss xmm0, dword ptr [rax]\nmovss xmm1, dword ptr [rax+4]\ncomiss xmm0, xmm1\njbe short loc_1212\nmovss dword ptr [rax], xmm1\nmovss dword ptr [rax+4], xmm0\njmp short loc_1212\nloc_1234:\nadd ecx, 1\ncmp esi, ecx\njle short loc_1289\nloc_123B:\nmov eax, r8d\nsub eax, ecx\ncmp eax, 1\njle short loc_1234\nmov rax, rdi\nmov edx, r10d\nsub edx, ecx\nlea rdx, [r9+rdx*4]\njmp short loc_121B\nloc_1253:\nmovss xmm0, dword ptr [rbp+rax*4+0]\nloc_1259:\nmovss dword ptr [r12+rax*4], xmm0\nadd rax, 1\ncmp rax, rbx\njz short loc_127F\nloc_1268:\ntest al, 1\njnz short loc_1253\nmov edx, eax\nshr edx, 1Fh\nadd edx, eax\nsar edx, 1\nmovsxd rdx, edx\nmovss xmm0, dword ptr [rdi+rdx*4]\njmp short loc_1259\nloc_127F:\ncall _free\npop rbx\npop rbp\npop r12\nretn\nloc_1289:\nmovsxd rbx, ebx\nmov eax, 0\njmp short loc_1268", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2, __int64 a3)\n{\n float *v6; // rdi\n __int64 v7; // rax\n signed int v8; // esi\n signed int v9; // ecx\n float *v10; // rax\n float v11; // xmm0_4\n float v12; // xmm1_4\n float v13; // xmm0_4\n __int64 v14; // rax\n\n v6 = (float *)malloc(4LL * (a2 / 2 + 1));\n if ( a2 > 0 )\n {\n v7 = 0LL;\n do\n {\n v6[v7] = *(float *)(a1 + 2 * v7);\n ++v7;\n }\n while ( a2 > (int)(v7 * 2) );\n v8 = (unsigned int)(a2 - 1) >> 1;\n if ( (unsigned int)(a2 - 1) >> 1 )\n {\n v9 = 0;\n do\n {\n if ( v8 + 1 - v9 > 1 )\n {\n v10 = v6;\n do\n {\n v11 = *v10;\n v12 = v10[1];\n if ( *v10 > v12 )\n {\n *v10 = v12;\n v10[1] = v11;\n }\n ++v10;\n }\n while ( v10 != &v6[v8 - 1 - v9 + 1] );\n }\n ++v9;\n }\n while ( v8 > v9 );\n }\n v14 = 0LL;\n do\n {\n if ( (v14 & 1) != 0 )\n v13 = *(float *)(a1 + 4 * v14);\n else\n v13 = v6[(int)v14 / 2];\n *(float *)(a3 + 4 * v14++) = v13;\n }\n while ( v14 != a2 );\n }\n free(v6);\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbp, rdi\nmov ebx, esi\nmov r12, rdx\nmov edi, esi\nshr edi, 1Fh\nadd edi, esi\nsar edi, 1\nadd edi, 1\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov rdi, rax; ptr\ntest ebx, ebx\njle loc_127F\nmov eax, 0\nloc_11E1:\nmovss xmm0, dword ptr [rbp+rax*4+0]\nmovss dword ptr [rdi+rax*2], xmm0\nadd rax, 2\ncmp ebx, eax\njg short loc_11E1\nlea esi, [rbx-1]\nshr esi, 1\njz loc_1289\nmov ecx, 0\nlea r8d, [rsi+1]\nlea r10d, [rsi-1]\nlea r9, [rdi+4]\njmp short loc_123B\nloc_1212:\nadd rax, 4\ncmp rax, rdx\njz short loc_1234\nloc_121B:\nmovss xmm0, dword ptr [rax]\nmovss xmm1, dword ptr [rax+4]\ncomiss xmm0, xmm1\njbe short loc_1212\nmovss dword ptr [rax], xmm1\nmovss dword ptr [rax+4], xmm0\njmp short loc_1212\nloc_1234:\nadd ecx, 1\ncmp esi, ecx\njle short loc_1289\nloc_123B:\nmov eax, r8d\nsub eax, ecx\ncmp eax, 1\njle short loc_1234\nmov rax, rdi\nmov edx, r10d\nsub edx, ecx\nlea rdx, [r9+rdx*4]\njmp short loc_121B\nloc_1253:\nmovss xmm0, dword ptr [rbp+rax*4+0]\nloc_1259:\nmovss dword ptr [r12+rax*4], xmm0\nadd rax, 1\ncmp rax, rbx\njz short loc_127F\nloc_1268:\ntest al, 1\njnz short loc_1253\nmov edx, eax\nshr edx, 1Fh\nadd edx, eax\nsar edx, 1\nmovsxd rdx, edx\nmovss xmm0, dword ptr [rdi+rdx*4]\njmp short loc_1259\nloc_127F:\ncall _free\npop rbx\npop rbp\npop r12\nretn\nloc_1289:\nmovsxd rbx, ebx\nmov eax, 0\njmp short loc_1268", + "ida_strip_pseudo": "void __fastcall sub_11A9(__int64 a1, int a2, __int64 a3)\n{\n float *v6; // rdi\n __int64 v7; // rax\n signed int v8; // esi\n signed int v9; // ecx\n float *v10; // rax\n float v11; // xmm0_4\n float v12; // xmm1_4\n float v13; // xmm0_4\n __int64 v14; // rax\n\n v6 = (float *)malloc(4LL * (a2 / 2 + 1));\n if ( a2 > 0 )\n {\n v7 = 0LL;\n do\n {\n v6[v7] = *(float *)(a1 + 2 * v7);\n ++v7;\n }\n while ( a2 > (int)(v7 * 2) );\n v8 = (unsigned int)(a2 - 1) >> 1;\n if ( (unsigned int)(a2 - 1) >> 1 )\n {\n v9 = 0;\n do\n {\n if ( v8 + 1 - v9 > 1 )\n {\n v10 = v6;\n do\n {\n v11 = *v10;\n v12 = v10[1];\n if ( *v10 > v12 )\n {\n *v10 = v12;\n v10[1] = v11;\n }\n ++v10;\n }\n while ( v10 != &v6[v8 - 1 - v9 + 1] );\n }\n ++v9;\n }\n while ( v8 > v9 );\n }\n v14 = 0LL;\n do\n {\n if ( (v14 & 1) != 0 )\n v13 = *(float *)(a1 + 4 * v14);\n else\n v13 = v6[(int)v14 / 2];\n *(float *)(a3 + 4 * v14++) = v13;\n }\n while ( v14 != a2 );\n }\n free(v6);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_11A9(long long a1, int a2, long long a3) {\n float *v6;\n long long v7;\n signed int v8;\n signed int v9;\n float *v10;\n float v11;\n float v12;\n float v13;\n long long v14;\n v6 = (float *)malloc(4LL * (a2 / 2 + 1));\n if (a2 > 0) {\n v7 = 0LL;\n do {\n v6[v7] = *(float *)(a1 + 2 * v7);\n ++v7;\n } while (a2 > (int)(v7 * 2));\n v8 = (unsigned int)(a2 - 1) >> 1;\n if ((unsigned int)(a2 - 1) >> 1) {\n v9 = 0;\n do {\n if (v8 + 1 - v9 > 1) {\n v10 = v6;\n do {\n v11 = *v10;\n v12 = v10[1];\n if (*v10 > v12) {\n *v10 = v12;\n v10[1] = v11;\n }\n ++v10;\n } while (v10 != &v6[v8 - 1 - v9 + 1]);\n }\n ++v9;\n } while (v8 > v9);\n }\n v14 = 0LL;\n do {\n if ((v14 & 1) != 0)\n v13 = *(float *)(a1 + 4 * v14);\n else\n v13 = v6[(int)v14 / 2];\n *(float *)(a3 + 4 * v14++) = v13;\n } while (v14 != a2);\n }\n free(v6);\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2, long long a3) {\n float *v6;\n long long v7;\n signed int v8;\n signed int v9;\n float *v10;\n float v11;\n float v12;\n float v13;\n long long v14;\n v6 = (float *)malloc(4LL * (a2 / 2 + 1));\n if (a2 > 0) {\n v7 = 0LL;\n do {\n v6[v7] = *(float *)(a1 + 2 * v7);\n ++v7;\n } while (a2 > (int)(v7 * 2));\n v8 = (unsigned int)(a2 - 1) >> 1;\n if ((unsigned int)(a2 - 1) >> 1) {\n v9 = 0;\n do {\n if (v8 + 1 - v9 > 1) {\n v10 = v6;\n do {\n v11 = *v10;\n v12 = v10[1];\n if (*v10 > v12) {\n *v10 = v12;\n v10[1] = v11;\n }\n ++v10;\n } while (v10 != &v6[v8 - 1 - v9 + 1]);\n }\n ++v9;\n } while (v8 > v9);\n }\n v14 = 0LL;\n do {\n if ((v14 & 1) != 0)\n v13 = *(float *)(a1 + 4 * v14);\n else\n v13 = v6[(int)v14 / 2];\n *(float *)(a3 + 4 * v14++) = v13;\n } while (v14 != a2);\n }\n free(v6);\n}" + }, + { + "index": "HumanEval-C-37", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "void func0(float *l, int size, float *out) {\n float *even = malloc((size / 2 + 1) * sizeof(float));\n int i, j, even_count = 0;\n for (i = 0; i < size; i += 2) {\n even[even_count++] = l[i];\n }\n for (i = 0; i < even_count - 1; i++) {\n for (j = 0; j < even_count - i - 1; j++) {\n if (even[j] > even[j + 1]) {\n float temp = even[j];\n even[j] = even[j + 1];\n even[j + 1] = temp;\n }\n }\n }\n for (i = 0; i < size; i++) {\n if (i % 2 == 0) {\n out[i] = even[i / 2];\n } else {\n out[i] = l[i];\n }\n }\n free(even);\n}", + "test": "#include \n#include \n#include \n\n\nint issame(float *a, float *b, int size) {\n for (int i = 0; i < size; i++) {\n if (fabs(a[i] - b[i]) > 1e-4) {\n return 0;\n }\n }\n return 1;\n}\n\nint main() {\n float test1[] = {1, 2, 3};\n float result1[3];\n func0(test1, 3, result1);\n float expected1[] = {1, 2, 3};\n assert(issame(result1, expected1, 3));\n\n float test2[] = {5, 3, -5, 2, -3, 3, 9, 0, 123, 1, -10};\n float result2[11];\n func0(test2, 11, result2);\n float expected2[] = {-10, 3, -5, 2, -3, 3, 5, 0, 9, 1, 123};\n assert(issame(result2, expected2, 11));\n\n float test3[] = {5, 8, -12, 4, 23, 2, 3, 11, 12, -10};\n float result3[10];\n func0(test3, 10, result3);\n float expected3[] = {-12, 8, 3, 4, 5, 2, 12, 11, 23, -10};\n assert(issame(result3, expected3, 10));\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r12\nmov r12, rdx\npush rbp\nmov rbp, rdi\npush rbx\nmovsxd rbx, esi\nmov edi, ebx\nshr edi, 1Fh\nadd edi, ebx\nsar edi, 1\nadd edi, 1\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov rdi, rax; ptr\nxor eax, eax\ntest ebx, ebx\njle loc_14C4\nnop word ptr [rax+rax+00000000h]\nloc_1410:\nmovss xmm0, dword ptr [rbp+rax*4+0]\nmovss dword ptr [rdi+rax*2], xmm0\nadd rax, 2\ncmp ebx, eax\njg short loc_1410\nlea esi, [rbx-1]\nmov ecx, 0\nlea r9, [rdi+4]\nshr esi, 1\nlea r8d, [rsi+1]\nlea r10d, [rsi-1]\njz short loc_1487\nnop dword ptr [rax+rax+00h]\nloc_1440:\nmov eax, r8d\nsub eax, ecx\ncmp eax, 1\njle short loc_1480\nmov edx, r10d\nmov rax, rdi\nsub edx, ecx\nlea rdx, [r9+rdx*4]\nnop word ptr [rax+rax+00000000h]\nloc_1460:\nmovq xmm0, qword ptr [rax]\nmovaps xmm3, xmm0\nshufps xmm3, xmm3, 0E5h\ncomiss xmm0, xmm3\njbe short loc_1477\nshufps xmm0, xmm0, 0E1h\nmovlps qword ptr [rax], xmm0\nloc_1477:\nadd rax, 4\ncmp rax, rdx\njnz short loc_1460\nloc_1480:\nadd ecx, 1\ncmp ecx, esi\njl short loc_1440\nloc_1487:\nxor eax, eax\njmp short loc_14AB\nloc_1490:\nmov edx, eax\nsar edx, 1\nmovsxd rdx, edx\nmovss xmm0, dword ptr [rdi+rdx*4]\nmovss dword ptr [r12+rax*4], xmm0\nadd rax, 1\ncmp rax, rbx\njz short loc_14C4\nloc_14AB:\ntest al, 1\njz short loc_1490\nmovss xmm0, dword ptr [rbp+rax*4+0]\nmovss dword ptr [r12+rax*4], xmm0\nadd rax, 1\ncmp rax, rbx\njnz short loc_14AB\nloc_14C4:\npop rbx\npop rbp\npop r12\njmp _free", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2, __int64 a3)\n{\n __int64 v5; // rbx\n __m128i *v6; // rdi\n __int64 v7; // rax\n signed int v8; // ecx\n signed int v9; // esi\n __m128i *v10; // rax\n __m128 v11; // xmm0\n __int64 v12; // rax\n\n v5 = a2;\n v6 = (__m128i *)malloc(4LL * (a2 / 2 + 1));\n v7 = 0LL;\n if ( a2 > 0 )\n {\n do\n {\n v6->m128i_i32[v7] = *(_DWORD *)(a1 + 2 * v7);\n ++v7;\n }\n while ( a2 > (int)(v7 * 2) );\n v8 = 0;\n v9 = (unsigned int)(a2 - 1) >> 1;\n if ( v9 )\n {\n do\n {\n if ( v9 + 1 - v8 > 1 )\n {\n v10 = v6;\n do\n {\n v11 = (__m128)_mm_loadl_epi64(v10);\n if ( v11.m128_f32[0] > _mm_shuffle_ps(v11, v11, 229).m128_f32[0] )\n _mm_storel_ps((double *)v10->m128i_i64, _mm_shuffle_ps(v11, v11, 225));\n v10 = (__m128i *)((char *)v10 + 4);\n }\n while ( v10 != (__m128i *)((char *)v6->m128i_i64 + 4 * (unsigned int)(v9 - 1 - v8) + 4) );\n }\n ++v8;\n }\n while ( v8 < v9 );\n }\n v12 = 0LL;\n do\n {\n while ( (v12 & 1) == 0 )\n {\n *(_DWORD *)(a3 + 4 * v12) = v6->m128i_i32[(int)v12 >> 1];\n if ( ++v12 == v5 )\n goto LABEL_14;\n }\n *(_DWORD *)(a3 + 4 * v12) = *(_DWORD *)(a1 + 4 * v12);\n ++v12;\n }\n while ( v12 != v5 );\n }\nLABEL_14:\n free(v6);\n}", + "ida_strip_asm": "sub_13D0:\nendbr64\npush r12\nmov r12, rdx\npush rbp\nmov rbp, rdi\npush rbx\nmovsxd rbx, esi\nmov edi, ebx\nshr edi, 1Fh\nadd edi, ebx\nsar edi, 1\nadd edi, 1\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov rdi, rax; ptr\nxor eax, eax\ntest ebx, ebx\njle loc_14C4\nnop word ptr [rax+rax+00000000h]\nloc_1410:\nmovss xmm0, dword ptr [rbp+rax*4+0]\nmovss dword ptr [rdi+rax*2], xmm0\nadd rax, 2\ncmp ebx, eax\njg short loc_1410\nlea esi, [rbx-1]\nmov ecx, 0\nlea r9, [rdi+4]\nshr esi, 1\nlea r8d, [rsi+1]\nlea r10d, [rsi-1]\njz short loc_1487\nnop dword ptr [rax+rax+00h]\nloc_1440:\nmov eax, r8d\nsub eax, ecx\ncmp eax, 1\njle short loc_1480\nmov edx, r10d\nmov rax, rdi\nsub edx, ecx\nlea rdx, [r9+rdx*4]\nnop word ptr [rax+rax+00000000h]\nloc_1460:\nmovq xmm0, qword ptr [rax]\nmovaps xmm3, xmm0\nshufps xmm3, xmm3, 0E5h\ncomiss xmm0, xmm3\njbe short loc_1477\nshufps xmm0, xmm0, 0E1h\nmovlps qword ptr [rax], xmm0\nloc_1477:\nadd rax, 4\ncmp rax, rdx\njnz short loc_1460\nloc_1480:\nadd ecx, 1\ncmp ecx, esi\njl short loc_1440\nloc_1487:\nxor eax, eax\njmp short loc_14AB\nloc_1490:\nmov edx, eax\nsar edx, 1\nmovsxd rdx, edx\nmovss xmm0, dword ptr [rdi+rdx*4]\nmovss dword ptr [r12+rax*4], xmm0\nadd rax, 1\ncmp rax, rbx\njz short loc_14C4\nloc_14AB:\ntest al, 1\njz short loc_1490\nmovss xmm0, dword ptr [rbp+rax*4+0]\nmovss dword ptr [r12+rax*4], xmm0\nadd rax, 1\ncmp rax, rbx\njnz short loc_14AB\nloc_14C4:\npop rbx\npop rbp\npop r12\njmp _free", + "ida_strip_pseudo": "void __fastcall sub_13D0(__int64 a1, int a2, __int64 a3)\n{\n __int64 v5; // rbx\n __m128i *v6; // rdi\n __int64 v7; // rax\n signed int v8; // ecx\n signed int v9; // esi\n __m128i *v10; // rax\n __m128 v11; // xmm0\n __int64 v12; // rax\n\n v5 = a2;\n v6 = (__m128i *)malloc(4LL * (a2 / 2 + 1));\n v7 = 0LL;\n if ( a2 > 0 )\n {\n do\n {\n v6->m128i_i32[v7] = *(_DWORD *)(a1 + 2 * v7);\n ++v7;\n }\n while ( a2 > (int)(v7 * 2) );\n v8 = 0;\n v9 = (unsigned int)(a2 - 1) >> 1;\n if ( v9 )\n {\n do\n {\n if ( v9 + 1 - v8 > 1 )\n {\n v10 = v6;\n do\n {\n v11 = (__m128)_mm_loadl_epi64(v10);\n if ( v11.m128_f32[0] > _mm_shuffle_ps(v11, v11, 229).m128_f32[0] )\n _mm_storel_ps((double *)v10->m128i_i64, _mm_shuffle_ps(v11, v11, 225));\n v10 = (__m128i *)((char *)v10 + 4);\n }\n while ( v10 != (__m128i *)((char *)v6->m128i_i64 + 4 * (unsigned int)(v9 - 1 - v8) + 4) );\n }\n ++v8;\n }\n while ( v8 < v9 );\n }\n v12 = 0LL;\n do\n {\n while ( (v12 & 1) == 0 )\n {\n *(_DWORD *)(a3 + 4 * v12) = v6->m128i_i32[(int)v12 >> 1];\n if ( ++v12 == v5 )\n goto LABEL_14;\n }\n *(_DWORD *)(a3 + 4 * v12) = *(_DWORD *)(a1 + 4 * v12);\n ++v12;\n }\n while ( v12 != v5 );\n }\nLABEL_14:\n free(v6);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_13D0(long long a1, int a2, long long a3) {\n long long v5;\n __m128i *v6;\n long long v7;\n signed int v8;\n signed int v9;\n __m128i *v10;\n __m128 v11;\n long long v12;\n v5 = a2;\n v6 = (__m128i *)malloc(4LL * (a2 / 2 + 1));\n v7 = 0LL;\n if (a2 > 0) {\n do {\n v6->m128i_i32[v7] = *(uint32_t *)(a1 + 2 * v7);\n ++v7;\n } while (a2 > (int)(v7 * 2));\n v8 = 0;\n v9 = (unsigned int)(a2 - 1) >> 1;\n if (v9) {\n do {\n if (v9 + 1 - v8 > 1) {\n v10 = v6;\n do {\n v11 = (__m128)_mm_loadl_epi64(v10);\n if (v11.m128_f32[0] > _mm_shuffle_ps(v11, v11, 229).m128_f32[0])\n _mm_storel_ps((double *)v10->m128i_i64,\n _mm_shuffle_ps(v11, v11, 225));\n v10 = (__m128i *)((char *)v10 + 4);\n } while (v10 != (__m128i *)((char *)v6->m128i_i64 +\n 4 * (unsigned int)(v9 - 1 - v8) + 4));\n }\n ++v8;\n } while (v8 < v9);\n }\n v12 = 0LL;\n do {\n while ((v12 & 1) == 0) {\n *(uint32_t *)(a3 + 4 * v12) = v6->m128i_i32[(int)v12 >> 1];\n if (++v12 == v5) goto LABEL_14;\n }\n *(uint32_t *)(a3 + 4 * v12) = *(uint32_t *)(a1 + 4 * v12);\n ++v12;\n } while (v12 != v5);\n }\nLABEL_14:\n free(v6);\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2, long long a3) {\n long long v5;\n __m128i *v6;\n long long v7;\n signed int v8;\n signed int v9;\n __m128i *v10;\n __m128 v11;\n long long v12;\n v5 = a2;\n v6 = (__m128i *)malloc(4LL * (a2 / 2 + 1));\n v7 = 0LL;\n if (a2 > 0) {\n do {\n v6->m128i_i32[v7] = *(uint32_t *)(a1 + 2 * v7);\n ++v7;\n } while (a2 > (int)(v7 * 2));\n v8 = 0;\n v9 = (unsigned int)(a2 - 1) >> 1;\n if (v9) {\n do {\n if (v9 + 1 - v8 > 1) {\n v10 = v6;\n do {\n v11 = (__m128)_mm_loadl_epi64(v10);\n if (v11.m128_f32[0] > _mm_shuffle_ps(v11, v11, 229).m128_f32[0])\n _mm_storel_ps((double *)v10->m128i_i64,\n _mm_shuffle_ps(v11, v11, 225));\n v10 = (__m128i *)((char *)v10 + 4);\n } while (v10 != (__m128i *)((char *)v6->m128i_i64 +\n 4 * (unsigned int)(v9 - 1 - v8) + 4));\n }\n ++v8;\n } while (v8 < v9);\n }\n v12 = 0LL;\n do {\n while ((v12 & 1) == 0) {\n *(uint32_t *)(a3 + 4 * v12) = v6->m128i_i32[(int)v12 >> 1];\n if (++v12 == v5) goto LABEL_14;\n }\n *(uint32_t *)(a3 + 4 * v12) = *(uint32_t *)(a1 + 4 * v12);\n ++v12;\n } while (v12 != v5);\n }\nLABEL_14:\n free(v6);\n}" + }, + { + "index": "HumanEval-C-37", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "void func0(float *l, int size, float *out) {\n float *even = malloc((size / 2 + 1) * sizeof(float));\n int i, j, even_count = 0;\n for (i = 0; i < size; i += 2) {\n even[even_count++] = l[i];\n }\n for (i = 0; i < even_count - 1; i++) {\n for (j = 0; j < even_count - i - 1; j++) {\n if (even[j] > even[j + 1]) {\n float temp = even[j];\n even[j] = even[j + 1];\n even[j + 1] = temp;\n }\n }\n }\n for (i = 0; i < size; i++) {\n if (i % 2 == 0) {\n out[i] = even[i / 2];\n } else {\n out[i] = l[i];\n }\n }\n free(even);\n}", + "test": "#include \n#include \n#include \n\n\nint issame(float *a, float *b, int size) {\n for (int i = 0; i < size; i++) {\n if (fabs(a[i] - b[i]) > 1e-4) {\n return 0;\n }\n }\n return 1;\n}\n\nint main() {\n float test1[] = {1, 2, 3};\n float result1[3];\n func0(test1, 3, result1);\n float expected1[] = {1, 2, 3};\n assert(issame(result1, expected1, 3));\n\n float test2[] = {5, 3, -5, 2, -3, 3, 9, 0, 123, 1, -10};\n float result2[11];\n func0(test2, 11, result2);\n float expected2[] = {-10, 3, -5, 2, -3, 3, 5, 0, 9, 1, 123};\n assert(issame(result2, expected2, 11));\n\n float test3[] = {5, 8, -12, 4, 23, 2, 3, 11, 12, -10};\n float result3[10];\n func0(test3, 10, result3);\n float expected3[] = {-12, 8, 3, 4, 5, 2, 12, 11, 23, -10};\n assert(issame(result3, expected3, 10));\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r12\nmov r12, rdx\npush rbp\nmovsxd rbp, esi\npush rbx\nmov rbx, rdi\nmov edi, ebp\nshr edi, 1Fh\nadd edi, ebp\nsar edi, 1\nadd edi, 1\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov rdi, rax; ptr\ntest ebp, ebp\njle loc_1787\nlea eax, [rbp-1]\nmov esi, eax\nshr esi, 1\ncmp eax, 7\njbe loc_17C5\nshr eax, 3\nmov ecx, eax\nxor eax, eax\nmov rdx, rcx\nshl rcx, 4\nnop word ptr [rax+rax+00h]\nloc_1688:\nmovups xmm0, xmmword ptr [rbx+rax*2]\nmovups xmm4, xmmword ptr [rbx+rax*2+10h]\nshufps xmm0, xmm4, 88h\nmovups xmmword ptr [rdi+rax], xmm0\nadd rax, 10h\ncmp rcx, rax\njnz short loc_1688\nlea ecx, ds:0[rdx*4]\nlea eax, ds:0[rdx*8]\nloc_16B0:\nmovsxd r9, eax\nmovsxd rdx, ecx\nmovss xmm0, dword ptr [rbx+r9*4]\nlea rcx, ds:0[rdx*4]\nlea r8, ds:0[r9*4]\nmovss dword ptr [rdi+rdx*4], xmm0\nlea edx, [rax+2]\ncmp ebp, edx\njle loc_17B8\nmovss xmm0, dword ptr [rbx+r8+8]\nlea edx, [rax+4]\nmovss dword ptr [rdi+rcx+4], xmm0\ncmp ebp, edx\njle short loc_1711\nmovss xmm0, dword ptr [rbx+r8+10h]\nadd eax, 6\nmovss dword ptr [rdi+rcx+8], xmm0\ncmp ebp, eax\njle short loc_1711\nmovss xmm0, dword ptr [rbx+r8+18h]\nmovss dword ptr [rdi+rcx+0Ch], xmm0\nloc_1711:\nlea ecx, [rsi+1]\nloc_1714:\nlea rsi, [rdi+4]\nnop dword ptr [rax+rax+00000000h]\nloc_1720:\ncmp ecx, 1\njle loc_17B0\nlea edx, [rcx-2]\nmov rax, rdi\nlea rdx, [rsi+rdx*4]\nnop dword ptr [rax+rax+00h]\nloc_1738:\nmovq xmm0, qword ptr [rax]\nmovaps xmm3, xmm0\nshufps xmm3, xmm3, 0E5h\ncomiss xmm0, xmm3\njbe short loc_174F\nshufps xmm0, xmm0, 0E1h\nmovlps qword ptr [rax], xmm0\nloc_174F:\nadd rax, 4\ncmp rdx, rax\njnz short loc_1738\nsub ecx, 1\ncmp ecx, 1\njnz short loc_1720\nloc_1760:\nxor eax, eax\nnop word ptr [rax+rax+00h]\nloc_1768:\ntest al, 1\njnz short loc_1790\nmov edx, eax\nsar edx, 1\nmovsxd rdx, edx\nmovss xmm0, dword ptr [rdi+rdx*4]\nmovss dword ptr [r12+rax*4], xmm0\nadd rax, 1\ncmp rax, rbp\njnz short loc_1768\nloc_1787:\npop rbx\npop rbp\npop r12\njmp _free\nloc_1790:\nmovss xmm0, dword ptr [rbx+rax*4]\nmovss dword ptr [r12+rax*4], xmm0\nadd rax, 1\ncmp rbp, rax\njnz short loc_1768\npop rbx\npop rbp\npop r12\njmp _free\nloc_17B0:\nsub ecx, 1\njmp loc_1720\nloc_17B8:\nlea ecx, [rsi+1]\ntest esi, esi\njnz loc_1714\njmp short loc_1760\nloc_17C5:\nxor ecx, ecx\nxor eax, eax\njmp loc_16B0", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2, __int64 a3)\n{\n __int64 v4; // rbp\n __m128i *v6; // rdi\n unsigned int v7; // esi\n unsigned __int64 v8; // rax\n unsigned int v9; // edx\n int v10; // ecx\n int v11; // eax\n __int64 v12; // rcx\n __int64 v13; // r8\n int v14; // ecx\n __m128i *v15; // rax\n __m128 v16; // xmm0\n __int64 v17; // rax\n\n v4 = a2;\n v6 = (__m128i *)malloc(4LL * (a2 / 2 + 1));\n if ( a2 <= 0 )\n goto LABEL_20;\n v7 = (unsigned int)(a2 - 1) >> 1;\n if ( (unsigned int)(v4 - 1) <= 7 )\n {\n v10 = 0;\n v11 = 0;\n }\n else\n {\n v8 = 0LL;\n v9 = (unsigned int)(v4 - 1) >> 3;\n do\n {\n v6[v8 / 0x10] = (__m128i)_mm_shuffle_ps(*(__m128 *)(a1 + 2 * v8), *(__m128 *)(a1 + 2 * v8 + 16), 136);\n v8 += 16LL;\n }\n while ( 16LL * ((unsigned int)(v4 - 1) >> 3) != v8 );\n v10 = 4 * v9;\n v11 = 8 * v9;\n }\n v12 = v10;\n v13 = 4LL * v11;\n v6->m128i_i32[v12] = *(_DWORD *)(a1 + v13);\n if ( (int)v4 <= v11 + 2 )\n {\n v14 = v7 + 1;\n if ( !v7 )\n goto LABEL_17;\n }\n else\n {\n v6->m128i_i32[v12 + 1] = *(_DWORD *)(a1 + v13 + 8);\n if ( (int)v4 > v11 + 4 )\n {\n v6->m128i_i32[v12 + 2] = *(_DWORD *)(a1 + v13 + 16);\n if ( (int)v4 > v11 + 6 )\n v6->m128i_i32[v12 + 3] = *(_DWORD *)(a1 + v13 + 24);\n }\n v14 = v7 + 1;\n }\n do\n {\n while ( v14 <= 1 )\n --v14;\n v15 = v6;\n do\n {\n v16 = (__m128)_mm_loadl_epi64(v15);\n if ( v16.m128_f32[0] > _mm_shuffle_ps(v16, v16, 229).m128_f32[0] )\n _mm_storel_ps((double *)v15->m128i_i64, _mm_shuffle_ps(v16, v16, 225));\n v15 = (__m128i *)((char *)v15 + 4);\n }\n while ( (__m128i *)((char *)v6->m128i_i64 + 4 * (unsigned int)(v14 - 2) + 4) != v15 );\n --v14;\n }\n while ( v14 != 1 );\nLABEL_17:\n v17 = 0LL;\n do\n {\n while ( (v17 & 1) == 0 )\n {\n *(_DWORD *)(a3 + 4 * v17) = v6->m128i_i32[(int)v17 >> 1];\n if ( ++v17 == v4 )\n goto LABEL_20;\n }\n *(_DWORD *)(a3 + 4 * v17) = *(_DWORD *)(a1 + 4 * v17);\n ++v17;\n }\n while ( v4 != v17 );\nLABEL_20:\n free(v6);\n}", + "ida_strip_asm": "sub_1630:\nendbr64\npush r12\nmov r12, rdx\npush rbp\nmovsxd rbp, esi\npush rbx\nmov rbx, rdi\nmov edi, ebp\nshr edi, 1Fh\nadd edi, ebp\nsar edi, 1\nadd edi, 1\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov rdi, rax; ptr\ntest ebp, ebp\njle loc_1787\nlea eax, [rbp-1]\nmov esi, eax\nshr esi, 1\ncmp eax, 7\njbe loc_17C5\nshr eax, 3\nmov ecx, eax\nxor eax, eax\nmov rdx, rcx\nshl rcx, 4\nnop word ptr [rax+rax+00h]\nloc_1688:\nmovups xmm0, xmmword ptr [rbx+rax*2]\nmovups xmm4, xmmword ptr [rbx+rax*2+10h]\nshufps xmm0, xmm4, 88h\nmovups xmmword ptr [rdi+rax], xmm0\nadd rax, 10h\ncmp rcx, rax\njnz short loc_1688\nlea ecx, ds:0[rdx*4]\nlea eax, ds:0[rdx*8]\nloc_16B0:\nmovsxd r9, eax\nmovsxd rdx, ecx\nmovss xmm0, dword ptr [rbx+r9*4]\nlea rcx, ds:0[rdx*4]\nlea r8, ds:0[r9*4]\nmovss dword ptr [rdi+rdx*4], xmm0\nlea edx, [rax+2]\ncmp ebp, edx\njle loc_17B8\nmovss xmm0, dword ptr [rbx+r8+8]\nlea edx, [rax+4]\nmovss dword ptr [rdi+rcx+4], xmm0\ncmp ebp, edx\njle short loc_1711\nmovss xmm0, dword ptr [rbx+r8+10h]\nadd eax, 6\nmovss dword ptr [rdi+rcx+8], xmm0\ncmp ebp, eax\njle short loc_1711\nmovss xmm0, dword ptr [rbx+r8+18h]\nmovss dword ptr [rdi+rcx+0Ch], xmm0\nloc_1711:\nlea ecx, [rsi+1]\nloc_1714:\nlea rsi, [rdi+4]\nnop dword ptr [rax+rax+00000000h]\nloc_1720:\ncmp ecx, 1\njle loc_17B0\nlea edx, [rcx-2]\nmov rax, rdi\nlea rdx, [rsi+rdx*4]\nnop dword ptr [rax+rax+00h]\nloc_1738:\nmovq xmm0, qword ptr [rax]\nmovaps xmm3, xmm0\nshufps xmm3, xmm3, 0E5h\ncomiss xmm0, xmm3\njbe short loc_174F\nshufps xmm0, xmm0, 0E1h\nmovlps qword ptr [rax], xmm0\nloc_174F:\nadd rax, 4\ncmp rdx, rax\njnz short loc_1738\nsub ecx, 1\ncmp ecx, 1\njnz short loc_1720\nloc_1760:\nxor eax, eax\nnop word ptr [rax+rax+00h]\nloc_1768:\ntest al, 1\njnz short loc_1790\nmov edx, eax\nsar edx, 1\nmovsxd rdx, edx\nmovss xmm0, dword ptr [rdi+rdx*4]\nmovss dword ptr [r12+rax*4], xmm0\nadd rax, 1\ncmp rax, rbp\njnz short loc_1768\nloc_1787:\npop rbx\npop rbp\npop r12\njmp _free\nloc_1790:\nmovss xmm0, dword ptr [rbx+rax*4]\nmovss dword ptr [r12+rax*4], xmm0\nadd rax, 1\ncmp rbp, rax\njnz short loc_1768\npop rbx\npop rbp\npop r12\njmp _free\nloc_17B0:\nsub ecx, 1\njmp loc_1720\nloc_17B8:\nlea ecx, [rsi+1]\ntest esi, esi\njnz loc_1714\njmp short loc_1760\nloc_17C5:\nxor ecx, ecx\nxor eax, eax\njmp loc_16B0", + "ida_strip_pseudo": "void __fastcall sub_1630(__int64 a1, int a2, __int64 a3)\n{\n __int64 v4; // rbp\n __m128i *v6; // rdi\n unsigned int v7; // esi\n unsigned __int64 v8; // rax\n unsigned int v9; // edx\n int v10; // ecx\n int v11; // eax\n __int64 v12; // rcx\n __int64 v13; // r8\n int v14; // ecx\n __m128i *v15; // rax\n __m128 v16; // xmm0\n __int64 v17; // rax\n\n v4 = a2;\n v6 = (__m128i *)malloc(4LL * (a2 / 2 + 1));\n if ( a2 <= 0 )\n goto LABEL_20;\n v7 = (unsigned int)(a2 - 1) >> 1;\n if ( (unsigned int)(v4 - 1) <= 7 )\n {\n v10 = 0;\n v11 = 0;\n }\n else\n {\n v8 = 0LL;\n v9 = (unsigned int)(v4 - 1) >> 3;\n do\n {\n v6[v8 / 0x10] = (__m128i)_mm_shuffle_ps(*(__m128 *)(a1 + 2 * v8), *(__m128 *)(a1 + 2 * v8 + 16), 136);\n v8 += 16LL;\n }\n while ( 16LL * ((unsigned int)(v4 - 1) >> 3) != v8 );\n v10 = 4 * v9;\n v11 = 8 * v9;\n }\n v12 = v10;\n v13 = 4LL * v11;\n v6->m128i_i32[v12] = *(_DWORD *)(a1 + v13);\n if ( (int)v4 <= v11 + 2 )\n {\n v14 = v7 + 1;\n if ( !v7 )\n goto LABEL_17;\n }\n else\n {\n v6->m128i_i32[v12 + 1] = *(_DWORD *)(a1 + v13 + 8);\n if ( (int)v4 > v11 + 4 )\n {\n v6->m128i_i32[v12 + 2] = *(_DWORD *)(a1 + v13 + 16);\n if ( (int)v4 > v11 + 6 )\n v6->m128i_i32[v12 + 3] = *(_DWORD *)(a1 + v13 + 24);\n }\n v14 = v7 + 1;\n }\n do\n {\n while ( v14 <= 1 )\n --v14;\n v15 = v6;\n do\n {\n v16 = (__m128)_mm_loadl_epi64(v15);\n if ( v16.m128_f32[0] > _mm_shuffle_ps(v16, v16, 229).m128_f32[0] )\n _mm_storel_ps((double *)v15->m128i_i64, _mm_shuffle_ps(v16, v16, 225));\n v15 = (__m128i *)((char *)v15 + 4);\n }\n while ( (__m128i *)((char *)v6->m128i_i64 + 4 * (unsigned int)(v14 - 2) + 4) != v15 );\n --v14;\n }\n while ( v14 != 1 );\nLABEL_17:\n v17 = 0LL;\n do\n {\n while ( (v17 & 1) == 0 )\n {\n *(_DWORD *)(a3 + 4 * v17) = v6->m128i_i32[(int)v17 >> 1];\n if ( ++v17 == v4 )\n goto LABEL_20;\n }\n *(_DWORD *)(a3 + 4 * v17) = *(_DWORD *)(a1 + 4 * v17);\n ++v17;\n }\n while ( v4 != v17 );\nLABEL_20:\n free(v6);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1630(long long a1, int a2, long long a3) {\n long long v4;\n __m128i *v6;\n unsigned int v7;\n unsigned long long v8;\n unsigned int v9;\n int v10;\n int v11;\n long long v12;\n long long v13;\n int v14;\n __m128i *v15;\n __m128 v16;\n long long v17;\n v4 = a2;\n v6 = (__m128i *)malloc(4LL * (a2 / 2 + 1));\n if (a2 <= 0) goto LABEL_20;\n v7 = (unsigned int)(a2 - 1) >> 1;\n if ((unsigned int)(v4 - 1) <= 7) {\n v10 = 0;\n v11 = 0;\n } else {\n v8 = 0LL;\n v9 = (unsigned int)(v4 - 1) >> 3;\n do {\n v6[v8 / 16] = (__m128i)_mm_shuffle_ps(*(__m128 *)(a1 + 2 * v8),\n *(__m128 *)(a1 + 2 * v8 + 16), 136);\n v8 += 16LL;\n } while (16LL * ((unsigned int)(v4 - 1) >> 3) != v8);\n v10 = 4 * v9;\n v11 = 8 * v9;\n }\n v12 = v10;\n v13 = 4LL * v11;\n v6->m128i_i32[v12] = *(uint32_t *)(a1 + v13);\n if ((int)v4 <= v11 + 2) {\n v14 = v7 + 1;\n if (!v7) goto LABEL_17;\n } else {\n v6->m128i_i32[v12 + 1] = *(uint32_t *)(a1 + v13 + 8);\n if ((int)v4 > v11 + 4) {\n v6->m128i_i32[v12 + 2] = *(uint32_t *)(a1 + v13 + 16);\n if ((int)v4 > v11 + 6)\n v6->m128i_i32[v12 + 3] = *(uint32_t *)(a1 + v13 + 24);\n }\n v14 = v7 + 1;\n }\n do {\n while (v14 <= 1) --v14;\n v15 = v6;\n do {\n v16 = (__m128)_mm_loadl_epi64(v15);\n if (v16.m128_f32[0] > _mm_shuffle_ps(v16, v16, 229).m128_f32[0])\n _mm_storel_ps((double *)v15->m128i_i64, _mm_shuffle_ps(v16, v16, 225));\n v15 = (__m128i *)((char *)v15 + 4);\n } while ((__m128i *)((char *)v6->m128i_i64 + 4 * (unsigned int)(v14 - 2) +\n 4) != v15);\n --v14;\n } while (v14 != 1);\nLABEL_17:\n v17 = 0LL;\n do {\n while ((v17 & 1) == 0) {\n *(uint32_t *)(a3 + 4 * v17) = v6->m128i_i32[(int)v17 >> 1];\n if (++v17 == v4) goto LABEL_20;\n }\n *(uint32_t *)(a3 + 4 * v17) = *(uint32_t *)(a1 + 4 * v17);\n ++v17;\n } while (v4 != v17);\nLABEL_20:\n free(v6);\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2, long long a3) {\n long long v4;\n __m128i *v6;\n unsigned int v7;\n unsigned long long v8;\n unsigned int v9;\n int v10;\n int v11;\n long long v12;\n long long v13;\n int v14;\n __m128i *v15;\n __m128 v16;\n long long v17;\n v4 = a2;\n v6 = (__m128i *)malloc(4LL * (a2 / 2 + 1));\n if (a2 <= 0) goto LABEL_20;\n v7 = (unsigned int)(a2 - 1) >> 1;\n if ((unsigned int)(v4 - 1) <= 7) {\n v10 = 0;\n v11 = 0;\n } else {\n v8 = 0LL;\n v9 = (unsigned int)(v4 - 1) >> 3;\n do {\n v6[v8 / 16] = (__m128i)_mm_shuffle_ps(*(__m128 *)(a1 + 2 * v8),\n *(__m128 *)(a1 + 2 * v8 + 16), 136);\n v8 += 16LL;\n } while (16LL * ((unsigned int)(v4 - 1) >> 3) != v8);\n v10 = 4 * v9;\n v11 = 8 * v9;\n }\n v12 = v10;\n v13 = 4LL * v11;\n v6->m128i_i32[v12] = *(uint32_t *)(a1 + v13);\n if ((int)v4 <= v11 + 2) {\n v14 = v7 + 1;\n if (!v7) goto LABEL_17;\n } else {\n v6->m128i_i32[v12 + 1] = *(uint32_t *)(a1 + v13 + 8);\n if ((int)v4 > v11 + 4) {\n v6->m128i_i32[v12 + 2] = *(uint32_t *)(a1 + v13 + 16);\n if ((int)v4 > v11 + 6)\n v6->m128i_i32[v12 + 3] = *(uint32_t *)(a1 + v13 + 24);\n }\n v14 = v7 + 1;\n }\n do {\n while (v14 <= 1) --v14;\n v15 = v6;\n do {\n v16 = (__m128)_mm_loadl_epi64(v15);\n if (v16.m128_f32[0] > _mm_shuffle_ps(v16, v16, 229).m128_f32[0])\n _mm_storel_ps((double *)v15->m128i_i64, _mm_shuffle_ps(v16, v16, 225));\n v15 = (__m128i *)((char *)v15 + 4);\n } while ((__m128i *)((char *)v6->m128i_i64 + 4 * (unsigned int)(v14 - 2) +\n 4) != v15);\n --v14;\n } while (v14 != 1);\nLABEL_17:\n v17 = 0LL;\n do {\n while ((v17 & 1) == 0) {\n *(uint32_t *)(a3 + 4 * v17) = v6->m128i_i32[(int)v17 >> 1];\n if (++v17 == v4) goto LABEL_20;\n }\n *(uint32_t *)(a3 + 4 * v17) = *(uint32_t *)(a1 + 4 * v17);\n ++v17;\n } while (v4 != v17);\nLABEL_20:\n free(v6);\n}" + }, + { + "index": "HumanEval-C-38", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(char *s, int encode) {\n int l = strlen(s);\n int num = (l + 2) / 3;\n char x[4];\n for (int i = 0; i < num; ++i) {\n int len = (i * 3 + 3 <= l) ? 3 : l - i * 3;\n strncpy(x, s + i * 3, len);\n x[len] = '\\0';\n if (len == 3) {\n if (encode) {\n char temp = x[2];\n x[2] = x[1];\n x[1] = x[0];\n x[0] = temp;\n } else {\n char temp = x[0];\n x[0] = x[1];\n x[1] = x[2];\n x[2] = temp;\n }\n }\n strncpy(s + i * 3, x, len);\n }\n}", + "test": "#include \n#include \n#include \n#include \n#include \n\nint main(){\n srand((unsigned int)time(NULL));\n char str[22], temp[22], decoded_str[22];\n\n for (int i = 0; i < 100; i++) {\n int l = 10 + rand() % 11;\n for (int j = 0; j < l; j++) {\n str[j] = 'a' + rand() % 26;\n }\n str[l] = '\\0';\n strcpy(temp, str);\n\n func0(temp, 1); // Encode\n strcpy(decoded_str, temp);\n func0(decoded_str, 0); // Decode\n\n assert(strcmp(decoded_str, str) == 0);\n }\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov [rbp+var_2C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_18], eax\nmov eax, [rbp+var_18]\nadd eax, 2\nmovsxd rdx, eax\nimul rdx, 55555556h\nmov rcx, rdx\nshr rcx, 20h\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_14], eax\nmov [rbp+var_1C], 0\njmp loc_1375\nloc_12A5:\nmov eax, [rbp+var_1C]\nlea edx, [rax+1]\nmov eax, edx\nadd eax, eax\nadd eax, edx\ncmp [rbp+var_18], eax\njge short loc_12C7\nmov eax, [rbp+var_1C]\nmov edx, eax\nshl eax, 2\nsub edx, eax\nmov eax, [rbp+var_18]\nadd eax, edx\njmp short loc_12CC\nloc_12C7:\nmov eax, 3\nloc_12CC:\nmov [rbp+var_10], eax\nmov eax, [rbp+var_10]\nmovsxd rcx, eax\nmov edx, [rbp+var_1C]\nmov eax, edx\nadd eax, eax\nadd eax, edx\nmovsxd rdx, eax\nmov rax, [rbp+s]\nlea rsi, [rdx+rax]; src\nlea rax, [rbp+dest]\nmov rdx, rcx; n\nmov rdi, rax; dest\ncall _strncpy\nmov eax, [rbp+var_10]\ncdqe\nmov [rbp+rax+dest], 0\ncmp [rbp+var_10], 3\njnz short loc_1348\ncmp [rbp+var_2C], 0\njz short loc_132C\nmovzx eax, [rbp+var_A]\nmov [rbp+var_1D], al\nmovzx eax, [rbp+var_B]\nmov [rbp+var_A], al\nmovzx eax, [rbp+dest]\nmov [rbp+var_B], al\nmovzx eax, [rbp+var_1D]\nmov [rbp+dest], al\njmp short loc_1348\nloc_132C:\nmovzx eax, [rbp+dest]\nmov [rbp+var_1E], al\nmovzx eax, [rbp+var_B]\nmov [rbp+dest], al\nmovzx eax, [rbp+var_A]\nmov [rbp+var_B], al\nmovzx eax, [rbp+var_1E]\nmov [rbp+var_A], al\nloc_1348:\nmov eax, [rbp+var_10]\nmovsxd rcx, eax\nmov edx, [rbp+var_1C]\nmov eax, edx\nadd eax, eax\nadd eax, edx\nmovsxd rdx, eax\nmov rax, [rbp+s]\nlea rdi, [rdx+rax]; dest\nlea rax, [rbp+dest]\nmov rdx, rcx; n\nmov rsi, rax; src\ncall _strncpy\nadd [rbp+var_1C], 1\nloc_1375:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_14]\njl loc_12A5\nnop\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njz short locret_1396\ncall ___stack_chk_fail\nlocret_1396:\nleave\nretn", + "ida_pseudo": "unsigned __int64 __fastcall func0(const char *a1, int a2)\n{\n int v2; // eax\n char v4; // [rsp+12h] [rbp-1Eh]\n char v5; // [rsp+13h] [rbp-1Dh]\n int i; // [rsp+14h] [rbp-1Ch]\n int v7; // [rsp+18h] [rbp-18h]\n int v8; // [rsp+20h] [rbp-10h]\n char dest; // [rsp+24h] [rbp-Ch] BYREF\n char v10; // [rsp+25h] [rbp-Bh]\n char v11; // [rsp+26h] [rbp-Ah]\n unsigned __int64 v12; // [rsp+28h] [rbp-8h]\n\n v12 = __readfsqword(0x28u);\n v7 = strlen(a1);\n for ( i = 0; i < (v7 + 2) / 3; ++i )\n {\n if ( v7 >= 3 * (i + 1) )\n v2 = 3;\n else\n v2 = -3 * i + v7;\n v8 = v2;\n strncpy(&dest, &a1[3 * i], v2);\n *(&dest + v8) = 0;\n if ( v8 == 3 )\n {\n if ( a2 )\n {\n v5 = v11;\n v11 = v10;\n v10 = dest;\n dest = v5;\n }\n else\n {\n v4 = dest;\n dest = v10;\n v10 = v11;\n v11 = v4;\n }\n }\n strncpy((char *)&a1[3 * i], &dest, v8);\n }\n return v12 - __readfsqword(0x28u);\n}", + "ida_strip_asm": "sub_1249:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov [rbp+var_2C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_18], eax\nmov eax, [rbp+var_18]\nadd eax, 2\nmovsxd rdx, eax\nimul rdx, 55555556h\nmov rcx, rdx\nshr rcx, 20h\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_14], eax\nmov [rbp+var_1C], 0\njmp loc_1375\nloc_12A5:\nmov eax, [rbp+var_1C]\nlea edx, [rax+1]\nmov eax, edx\nadd eax, eax\nadd eax, edx\ncmp [rbp+var_18], eax\njge short loc_12C7\nmov eax, [rbp+var_1C]\nmov edx, eax\nshl eax, 2\nsub edx, eax\nmov eax, [rbp+var_18]\nadd eax, edx\njmp short loc_12CC\nloc_12C7:\nmov eax, 3\nloc_12CC:\nmov [rbp+var_10], eax\nmov eax, [rbp+var_10]\nmovsxd rcx, eax\nmov edx, [rbp+var_1C]\nmov eax, edx\nadd eax, eax\nadd eax, edx\nmovsxd rdx, eax\nmov rax, [rbp+s]\nlea rsi, [rdx+rax]; src\nlea rax, [rbp+dest]\nmov rdx, rcx; n\nmov rdi, rax; dest\ncall _strncpy\nmov eax, [rbp+var_10]\ncdqe\nmov [rbp+rax+dest], 0\ncmp [rbp+var_10], 3\njnz short loc_1348\ncmp [rbp+var_2C], 0\njz short loc_132C\nmovzx eax, [rbp+var_A]\nmov [rbp+var_1D], al\nmovzx eax, [rbp+var_B]\nmov [rbp+var_A], al\nmovzx eax, [rbp+dest]\nmov [rbp+var_B], al\nmovzx eax, [rbp+var_1D]\nmov [rbp+dest], al\njmp short loc_1348\nloc_132C:\nmovzx eax, [rbp+dest]\nmov [rbp+var_1E], al\nmovzx eax, [rbp+var_B]\nmov [rbp+dest], al\nmovzx eax, [rbp+var_A]\nmov [rbp+var_B], al\nmovzx eax, [rbp+var_1E]\nmov [rbp+var_A], al\nloc_1348:\nmov eax, [rbp+var_10]\nmovsxd rcx, eax\nmov edx, [rbp+var_1C]\nmov eax, edx\nadd eax, eax\nadd eax, edx\nmovsxd rdx, eax\nmov rax, [rbp+s]\nlea rdi, [rdx+rax]; dest\nlea rax, [rbp+dest]\nmov rdx, rcx; n\nmov rsi, rax; src\ncall _strncpy\nadd [rbp+var_1C], 1\nloc_1375:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_14]\njl loc_12A5\nnop\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njz short locret_1396\ncall ___stack_chk_fail\nlocret_1396:\nleave\nretn", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_1249(const char *a1, int a2)\n{\n int v2; // eax\n char v4; // [rsp+12h] [rbp-1Eh]\n char v5; // [rsp+13h] [rbp-1Dh]\n int i; // [rsp+14h] [rbp-1Ch]\n int v7; // [rsp+18h] [rbp-18h]\n int v8; // [rsp+20h] [rbp-10h]\n char dest; // [rsp+24h] [rbp-Ch] BYREF\n char v10; // [rsp+25h] [rbp-Bh]\n char v11; // [rsp+26h] [rbp-Ah]\n unsigned __int64 v12; // [rsp+28h] [rbp-8h]\n\n v12 = __readfsqword(0x28u);\n v7 = strlen(a1);\n for ( i = 0; i < (v7 + 2) / 3; ++i )\n {\n if ( v7 >= 3 * (i + 1) )\n v2 = 3;\n else\n v2 = -3 * i + v7;\n v8 = v2;\n strncpy(&dest, &a1[3 * i], v2);\n *(&dest + v8) = 0;\n if ( v8 == 3 )\n {\n if ( a2 )\n {\n v5 = v11;\n v11 = v10;\n v10 = dest;\n dest = v5;\n }\n else\n {\n v4 = dest;\n dest = v10;\n v10 = v11;\n v11 = v4;\n }\n }\n strncpy((char *)&a1[3 * i], &dest, v8);\n }\n return v12 - __readfsqword(0x28u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_1249(const char *a1, int a2) {\n int v2;\n char v4;\n char v5;\n int i;\n int v7;\n int v8;\n char dest;\n char v10;\n char v11;\n unsigned long long v12;\n v12 = __readfsqword(40u);\n v7 = strlen(a1);\n for (i = 0; i < (v7 + 2) / 3; ++i) {\n if (v7 >= 3 * (i + 1))\n v2 = 3;\n else\n v2 = -3 * i + v7;\n v8 = v2;\n strncpy(&dest, &a1[3 * i], v2);\n *(&dest + v8) = 0;\n if (v8 == 3) {\n if (a2) {\n v5 = v11;\n v11 = v10;\n v10 = dest;\n dest = v5;\n } else {\n v4 = dest;\n dest = v10;\n v10 = v11;\n v11 = v4;\n }\n }\n strncpy((char *)&a1[3 * i], &dest, v8);\n }\n return v12 - __readfsqword(40u);\n}", + "ida_pseudo_norm": "unsigned long long func0(const char *a1, int a2) {\n int v2;\n char v4;\n char v5;\n int i;\n int v7;\n int v8;\n char dest;\n char v10;\n char v11;\n unsigned long long v12;\n v12 = __readfsqword(40u);\n v7 = strlen(a1);\n for (i = 0; i < (v7 + 2) / 3; ++i) {\n if (v7 >= 3 * (i + 1))\n v2 = 3;\n else\n v2 = -3 * i + v7;\n v8 = v2;\n strncpy(&dest, &a1[3 * i], v2);\n *(&dest + v8) = 0;\n if (v8 == 3) {\n if (a2) {\n v5 = v11;\n v11 = v10;\n v10 = dest;\n dest = v5;\n } else {\n v4 = dest;\n dest = v10;\n v10 = v11;\n v11 = v4;\n }\n }\n strncpy((char *)&a1[3 * i], &dest, v8);\n }\n return v12 - __readfsqword(40u);\n}" + }, + { + "index": "HumanEval-C-38", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(char *s, int encode) {\n int l = strlen(s);\n int num = (l + 2) / 3;\n char x[4];\n for (int i = 0; i < num; ++i) {\n int len = (i * 3 + 3 <= l) ? 3 : l - i * 3;\n strncpy(x, s + i * 3, len);\n x[len] = '\\0';\n if (len == 3) {\n if (encode) {\n char temp = x[2];\n x[2] = x[1];\n x[1] = x[0];\n x[0] = temp;\n } else {\n char temp = x[0];\n x[0] = x[1];\n x[1] = x[2];\n x[2] = temp;\n }\n }\n strncpy(s + i * 3, x, len);\n }\n}", + "test": "#include \n#include \n#include \n#include \n#include \n\nint main(){\n srand((unsigned int)time(NULL));\n char str[22], temp[22], decoded_str[22];\n\n for (int i = 0; i < 100; i++) {\n int l = 10 + rand() % 11;\n for (int j = 0; j < l; j++) {\n str[j] = 'a' + rand() % 26;\n }\n str[l] = '\\0';\n strcpy(temp, str);\n\n func0(temp, 1); // Encode\n strcpy(decoded_str, temp);\n func0(decoded_str, 0); // Decode\n\n assert(strcmp(decoded_str, str) == 0);\n }\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov rbp, rdi\nmov [rsp+58h+var_4C], esi\nmov rax, fs:28h\nmov [rsp+58h+var_40], rax\nxor eax, eax\ncall _strlen\nmov r12, rax\nmov [rsp+58h+var_50], eax\nlea eax, [rax+2]\nmovsxd r15, eax\nimul r15, 55555556h\nshr r15, 20h\nsar eax, 1Fh\nsub r15d, eax\ntest r12d, r12d\njle loc_137B\nmov ebx, 0\nlea r14, [rsp+58h+src]\njmp short loc_130C\nloc_12CA:\nmovsxd r13, r12d\nmov [rsp+58h+dest], rbp\nmov ecx, 4\nmov rdx, r13\nmov rsi, rbp\nmov rdi, r14\ncall ___strncpy_chk\nmov [rsp+r13+58h+src], 0\ncmp r12d, 3\njz short loc_1337\nloc_12F0:\nmov rdx, r13; n\nmov rsi, r14; src\nmov rdi, [rsp+58h+dest]; dest\ncall _strncpy\nadd rbp, 3\nsub r12d, 3\ncmp ebx, r15d\njge short loc_137B\nloc_130C:\nadd ebx, 1\nlea eax, [rbx+rbx*2]\ncmp [rsp+58h+var_50], eax\njl short loc_12CA\nmov [rsp+58h+dest], rbp\nmov edx, 3; n\nmov rsi, rbp; src\nmov rdi, r14; dest\ncall _strncpy\nmov [rsp+58h+var_41], 0\nmov r13d, 3\nloc_1337:\ncmp [rsp+58h+var_4C], 0\njz short loc_135B\nmovzx eax, [rsp+58h+var_42]\nmovzx edx, [rsp+58h+var_43]\nmov [rsp+58h+var_42], dl\nmovzx edx, [rsp+58h+src]\nmov [rsp+58h+var_43], dl\nmov [rsp+58h+src], al\njmp short loc_12F0\nloc_135B:\nmovzx eax, [rsp+58h+src]\nmovzx edx, [rsp+58h+var_43]\nmov [rsp+58h+src], dl\nmovzx edx, [rsp+58h+var_42]\nmov [rsp+58h+var_43], dl\nmov [rsp+58h+var_42], al\njmp loc_12F0\nloc_137B:\nmov rax, [rsp+58h+var_40]\nsub rax, fs:28h\njnz short loc_139A\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_139A:\ncall ___stack_chk_fail", + "ida_pseudo": "unsigned __int64 __fastcall func0(char *src, int a2)\n{\n const char *v2; // rbp\n int v3; // r12d\n int v4; // r15d\n int v5; // ebx\n size_t v6; // r13\n char v7; // al\n char v8; // al\n char *dest; // [rsp+0h] [rbp-58h]\n int v11; // [rsp+8h] [rbp-50h]\n char srca[4]; // [rsp+14h] [rbp-44h] BYREF\n unsigned __int64 v13; // [rsp+18h] [rbp-40h]\n\n v2 = src;\n v13 = __readfsqword(0x28u);\n v3 = strlen(src);\n v11 = v3;\n v4 = (v3 + 2) / 3;\n if ( v3 > 0 )\n {\n v5 = 0;\n while ( 1 )\n {\n ++v5;\n if ( v11 >= 3 * v5 )\n break;\n v6 = v3;\n dest = (char *)v2;\n __strncpy_chk(srca, v2, v3, 4LL);\n srca[v3] = 0;\n if ( v3 == 3 )\n goto LABEL_7;\nLABEL_4:\n strncpy(dest, srca, v6);\n v2 += 3;\n v3 -= 3;\n if ( v5 >= v4 )\n return v13 - __readfsqword(0x28u);\n }\n dest = (char *)v2;\n strncpy(srca, v2, 3uLL);\n srca[3] = 0;\n v6 = 3LL;\nLABEL_7:\n if ( a2 )\n {\n v7 = srca[2];\n *(_WORD *)&srca[1] = *(_WORD *)srca;\n srca[0] = v7;\n }\n else\n {\n v8 = srca[0];\n *(_WORD *)srca = *(_WORD *)&srca[1];\n srca[2] = v8;\n }\n goto LABEL_4;\n }\n return v13 - __readfsqword(0x28u);\n}", + "ida_strip_asm": "sub_1269:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov rbp, rdi\nmov [rsp+58h+var_4C], esi\nmov rax, fs:28h\nmov [rsp+58h+var_40], rax\nxor eax, eax\ncall _strlen\nmov r12, rax\nmov [rsp+58h+var_50], eax\nlea eax, [rax+2]\nmovsxd r15, eax\nimul r15, 55555556h\nshr r15, 20h\nsar eax, 1Fh\nsub r15d, eax\ntest r12d, r12d\njle loc_137B\nmov ebx, 0\nlea r14, [rsp+58h+src]\njmp short loc_130C\nloc_12CA:\nmovsxd r13, r12d\nmov [rsp+58h+dest], rbp\nmov ecx, 4\nmov rdx, r13\nmov rsi, rbp\nmov rdi, r14\ncall ___strncpy_chk\nmov [rsp+r13+58h+src], 0\ncmp r12d, 3\njz short loc_1337\nloc_12F0:\nmov rdx, r13; n\nmov rsi, r14; src\nmov rdi, [rsp+58h+dest]; dest\ncall _strncpy\nadd rbp, 3\nsub r12d, 3\ncmp ebx, r15d\njge short loc_137B\nloc_130C:\nadd ebx, 1\nlea eax, [rbx+rbx*2]\ncmp [rsp+58h+var_50], eax\njl short loc_12CA\nmov [rsp+58h+dest], rbp\nmov edx, 3; n\nmov rsi, rbp; src\nmov rdi, r14; dest\ncall _strncpy\nmov [rsp+58h+var_41], 0\nmov r13d, 3\nloc_1337:\ncmp [rsp+58h+var_4C], 0\njz short loc_135B\nmovzx eax, [rsp+58h+var_42]\nmovzx edx, [rsp+58h+var_43]\nmov [rsp+58h+var_42], dl\nmovzx edx, [rsp+58h+src]\nmov [rsp+58h+var_43], dl\nmov [rsp+58h+src], al\njmp short loc_12F0\nloc_135B:\nmovzx eax, [rsp+58h+src]\nmovzx edx, [rsp+58h+var_43]\nmov [rsp+58h+src], dl\nmovzx edx, [rsp+58h+var_42]\nmov [rsp+58h+var_43], dl\nmov [rsp+58h+var_42], al\njmp loc_12F0\nloc_137B:\nmov rax, [rsp+58h+var_40]\nsub rax, fs:28h\njnz short loc_139A\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_139A:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_1269(char *src, int a2)\n{\n const char *v2; // rbp\n int v3; // r12d\n int v4; // r15d\n int v5; // ebx\n size_t v6; // r13\n char v7; // al\n char v8; // al\n char *dest; // [rsp+0h] [rbp-58h]\n int v11; // [rsp+8h] [rbp-50h]\n char srca[4]; // [rsp+14h] [rbp-44h] BYREF\n unsigned __int64 v13; // [rsp+18h] [rbp-40h]\n\n v2 = src;\n v13 = __readfsqword(0x28u);\n v3 = strlen(src);\n v11 = v3;\n v4 = (v3 + 2) / 3;\n if ( v3 > 0 )\n {\n v5 = 0;\n while ( 1 )\n {\n ++v5;\n if ( v11 >= 3 * v5 )\n break;\n v6 = v3;\n dest = (char *)v2;\n __strncpy_chk(srca, v2, v3, 4LL);\n srca[v3] = 0;\n if ( v3 == 3 )\n goto LABEL_7;\nLABEL_4:\n strncpy(dest, srca, v6);\n v2 += 3;\n v3 -= 3;\n if ( v5 >= v4 )\n return v13 - __readfsqword(0x28u);\n }\n dest = (char *)v2;\n strncpy(srca, v2, 3uLL);\n srca[3] = 0;\n v6 = 3LL;\nLABEL_7:\n if ( a2 )\n {\n v7 = srca[2];\n *(_WORD *)&srca[1] = *(_WORD *)srca;\n srca[0] = v7;\n }\n else\n {\n v8 = srca[0];\n *(_WORD *)srca = *(_WORD *)&srca[1];\n srca[2] = v8;\n }\n goto LABEL_4;\n }\n return v13 - __readfsqword(0x28u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_1269(char *src, int a2) {\n const char *v2;\n int v3;\n int v4;\n int v5;\n unsigned int v6;\n char v7;\n char v8;\n char *dest;\n int v11;\n char srca[4];\n unsigned long long v13;\n v2 = src;\n v13 = __readfsqword(40u);\n v3 = strlen(src);\n v11 = v3;\n v4 = (v3 + 2) / 3;\n if (v3 > 0) {\n v5 = 0;\n while (1) {\n ++v5;\n if (v11 >= 3 * v5) break;\n v6 = v3;\n dest = (char *)v2;\n __strncpy_chk(srca, v2, v3, 4LL);\n srca[v3] = 0;\n if (v3 == 3) goto LABEL_7;\n LABEL_4:\n strncpy(dest, srca, v6);\n v2 += 3;\n v3 -= 3;\n if (v5 >= v4) return v13 - __readfsqword(40u);\n }\n dest = (char *)v2;\n strncpy(srca, v2, 3uLL);\n srca[3] = 0;\n v6 = 3LL;\n LABEL_7:\n if (a2) {\n v7 = srca[2];\n *(unsigned short *)&srca[1] = *(unsigned short *)srca;\n srca[0] = v7;\n } else {\n v8 = srca[0];\n *(unsigned short *)srca = *(unsigned short *)&srca[1];\n srca[2] = v8;\n }\n goto LABEL_4;\n }\n return v13 - __readfsqword(40u);\n}", + "ida_pseudo_norm": "unsigned long long func0(char *src, int a2) {\n const char *v2;\n int v3;\n int v4;\n int v5;\n unsigned int v6;\n char v7;\n char v8;\n char *dest;\n int v11;\n char srca[4];\n unsigned long long v13;\n v2 = src;\n v13 = __readfsqword(40u);\n v3 = strlen(src);\n v11 = v3;\n v4 = (v3 + 2) / 3;\n if (v3 > 0) {\n v5 = 0;\n while (1) {\n ++v5;\n if (v11 >= 3 * v5) break;\n v6 = v3;\n dest = (char *)v2;\n __strncpy_chk(srca, v2, v3, 4LL);\n srca[v3] = 0;\n if (v3 == 3) goto LABEL_7;\n LABEL_4:\n strncpy(dest, srca, v6);\n v2 += 3;\n v3 -= 3;\n if (v5 >= v4) return v13 - __readfsqword(40u);\n }\n dest = (char *)v2;\n strncpy(srca, v2, 3uLL);\n srca[3] = 0;\n v6 = 3LL;\n LABEL_7:\n if (a2) {\n v7 = srca[2];\n *(unsigned short *)&srca[1] = *(unsigned short *)srca;\n srca[0] = v7;\n } else {\n v8 = srca[0];\n *(unsigned short *)srca = *(unsigned short *)&srca[1];\n srca[2] = v8;\n }\n goto LABEL_4;\n }\n return v13 - __readfsqword(40u);\n}" + }, + { + "index": "HumanEval-C-38", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(char *s, int encode) {\n int l = strlen(s);\n int num = (l + 2) / 3;\n char x[4];\n for (int i = 0; i < num; ++i) {\n int len = (i * 3 + 3 <= l) ? 3 : l - i * 3;\n strncpy(x, s + i * 3, len);\n x[len] = '\\0';\n if (len == 3) {\n if (encode) {\n char temp = x[2];\n x[2] = x[1];\n x[1] = x[0];\n x[0] = temp;\n } else {\n char temp = x[0];\n x[0] = x[1];\n x[1] = x[2];\n x[2] = temp;\n }\n }\n strncpy(s + i * 3, x, len);\n }\n}", + "test": "#include \n#include \n#include \n#include \n#include \n\nint main(){\n srand((unsigned int)time(NULL));\n char str[22], temp[22], decoded_str[22];\n\n for (int i = 0; i < 100; i++) {\n int l = 10 + rand() % 11;\n for (int j = 0; j < l; j++) {\n str[j] = 'a' + rand() % 26;\n }\n str[l] = '\\0';\n strcpy(temp, str);\n\n func0(temp, 1); // Encode\n strcpy(decoded_str, temp);\n func0(decoded_str, 0); // Decode\n\n assert(strcmp(decoded_str, str) == 0);\n }\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 28h\nmov [rsp+58h+var_4C], esi\nmov rax, fs:28h\nmov [rsp+58h+var_40], rax\nxor eax, eax\ncall _strlen\nmov rbp, rax\nmov r14d, eax\nadd eax, 2\nmovsxd r13, eax\nsar eax, 1Fh\nimul r13, 55555556h\nshr r13, 20h\nsub r13d, eax\ntest ebp, ebp\njle loc_14D0\nxor r15d, r15d\nlea r12, [rsp+58h+dest]\njmp short loc_1486\nloc_1430:\nmov edx, 3; n\nmov rsi, rbx; src\nmov rdi, r12; dest\ncall _strncpy\nmov [rsp+58h+var_41], 0\nloc_1445:\nmov esi, [rsp+58h+var_4C]\nmovzx eax, word ptr [rsp+58h+dest+1]\nmovzx ecx, [rsp+58h+var_42]\nmovzx edx, [rsp+58h+dest]\ntest esi, esi\njz short loc_14C0\nmov [rsp+58h+var_42], al\nmovzx eax, cl\nmov ah, dl\nmov word ptr [rsp+58h+dest], ax\nloc_146A:\nmov edx, 3; n\nloc_146F:\nmov rdi, rbx; dest\nmov rsi, r12; src\nadd rbx, 3\nsub ebp, 3\ncall _strncpy\ncmp r15d, r13d\njge short loc_14D0\nloc_1486:\nadd r15d, 1\nlea eax, [r15+r15*2]\ncmp eax, r14d\njle short loc_1430\nmovsxd rdx, ebp\nmov ecx, 4\nmov rsi, rbx\nmov rdi, r12\nmov [rsp+58h+var_58], rdx\ncall ___strncpy_chk\nmov rdx, [rsp+58h+var_58]\nmov [rsp+rdx+58h+dest], 0\ncmp ebp, 3\njnz short loc_146F\njmp short loc_1445\nloc_14C0:\nmov word ptr [rsp+58h+dest], ax\nmov [rsp+58h+var_42], dl\njmp short loc_146A\nloc_14D0:\nmov rax, [rsp+58h+var_40]\nsub rax, fs:28h\njnz short loc_14EF\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14EF:\ncall ___stack_chk_fail", + "ida_pseudo": "unsigned __int64 __fastcall func0(char *dest, int a2)\n{\n const char *v2; // rbx\n int v3; // ebp\n int v4; // r14d\n int v5; // r13d\n int v6; // r15d\n char v7; // cl\n char v8; // dl\n __int16 v9; // ax\n size_t v10; // rdx\n char *v11; // rdi\n _BYTE desta[3]; // [rsp+14h] [rbp-44h] BYREF\n char v14; // [rsp+17h] [rbp-41h]\n unsigned __int64 v15; // [rsp+18h] [rbp-40h]\n\n v2 = dest;\n v15 = __readfsqword(0x28u);\n v3 = strlen(dest);\n v4 = v3;\n v5 = (v3 + 2) / 3;\n if ( v3 > 0 )\n {\n v6 = 0;\n while ( 1 )\n {\n ++v6;\n if ( 3 * v6 <= v4 )\n break;\n __strncpy_chk(desta, v2, v3, 4LL);\n v10 = v3;\n desta[v3] = 0;\n if ( v3 == 3 )\n goto LABEL_4;\nLABEL_7:\n v11 = (char *)v2;\n v2 += 3;\n v3 -= 3;\n strncpy(v11, desta, v10);\n if ( v6 >= v5 )\n return v15 - __readfsqword(0x28u);\n }\n strncpy(desta, v2, 3uLL);\n v14 = 0;\nLABEL_4:\n v7 = desta[2];\n v8 = desta[0];\n if ( a2 )\n {\n desta[2] = desta[1];\n LOBYTE(v9) = v7;\n HIBYTE(v9) = desta[0];\n *(_WORD *)desta = v9;\n }\n else\n {\n *(_WORD *)desta = *(_WORD *)&desta[1];\n desta[2] = v8;\n }\n v10 = 3LL;\n goto LABEL_7;\n }\n return v15 - __readfsqword(0x28u);\n}", + "ida_strip_asm": "sub_13D0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 28h\nmov [rsp+58h+var_4C], esi\nmov rax, fs:28h\nmov [rsp+58h+var_40], rax\nxor eax, eax\ncall _strlen\nmov rbp, rax\nmov r14d, eax\nadd eax, 2\nmovsxd r13, eax\nsar eax, 1Fh\nimul r13, 55555556h\nshr r13, 20h\nsub r13d, eax\ntest ebp, ebp\njle loc_14D0\nxor r15d, r15d\nlea r12, [rsp+58h+dest]\njmp short loc_1486\nloc_1430:\nmov edx, 3; n\nmov rsi, rbx; src\nmov rdi, r12; dest\ncall _strncpy\nmov [rsp+58h+var_41], 0\nloc_1445:\nmov esi, [rsp+58h+var_4C]\nmovzx eax, word ptr [rsp+58h+dest+1]\nmovzx ecx, [rsp+58h+var_42]\nmovzx edx, [rsp+58h+dest]\ntest esi, esi\njz short loc_14C0\nmov [rsp+58h+var_42], al\nmovzx eax, cl\nmov ah, dl\nmov word ptr [rsp+58h+dest], ax\nloc_146A:\nmov edx, 3; n\nloc_146F:\nmov rdi, rbx; dest\nmov rsi, r12; src\nadd rbx, 3\nsub ebp, 3\ncall _strncpy\ncmp r15d, r13d\njge short loc_14D0\nloc_1486:\nadd r15d, 1\nlea eax, [r15+r15*2]\ncmp eax, r14d\njle short loc_1430\nmovsxd rdx, ebp\nmov ecx, 4\nmov rsi, rbx\nmov rdi, r12\nmov [rsp+58h+var_58], rdx\ncall ___strncpy_chk\nmov rdx, [rsp+58h+var_58]\nmov [rsp+rdx+58h+dest], 0\ncmp ebp, 3\njnz short loc_146F\njmp short loc_1445\nloc_14C0:\nmov word ptr [rsp+58h+dest], ax\nmov [rsp+58h+var_42], dl\njmp short loc_146A\nloc_14D0:\nmov rax, [rsp+58h+var_40]\nsub rax, fs:28h\njnz short loc_14EF\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14EF:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_13D0(char *dest, int a2)\n{\n const char *v2; // rbx\n int v3; // ebp\n int v4; // r14d\n int v5; // r13d\n int v6; // r15d\n char v7; // cl\n char v8; // dl\n __int16 v9; // ax\n size_t v10; // rdx\n char *v11; // rdi\n _BYTE desta[3]; // [rsp+14h] [rbp-44h] BYREF\n char v14; // [rsp+17h] [rbp-41h]\n unsigned __int64 v15; // [rsp+18h] [rbp-40h]\n\n v2 = dest;\n v15 = __readfsqword(0x28u);\n v3 = strlen(dest);\n v4 = v3;\n v5 = (v3 + 2) / 3;\n if ( v3 > 0 )\n {\n v6 = 0;\n while ( 1 )\n {\n ++v6;\n if ( 3 * v6 <= v4 )\n break;\n __strncpy_chk(desta, v2, v3, 4LL);\n v10 = v3;\n desta[v3] = 0;\n if ( v3 == 3 )\n goto LABEL_4;\nLABEL_7:\n v11 = (char *)v2;\n v2 += 3;\n v3 -= 3;\n strncpy(v11, desta, v10);\n if ( v6 >= v5 )\n return v15 - __readfsqword(0x28u);\n }\n strncpy(desta, v2, 3uLL);\n v14 = 0;\nLABEL_4:\n v7 = desta[2];\n v8 = desta[0];\n if ( a2 )\n {\n desta[2] = desta[1];\n LOBYTE(v9) = v7;\n HIBYTE(v9) = desta[0];\n *(_WORD *)desta = v9;\n }\n else\n {\n *(_WORD *)desta = *(_WORD *)&desta[1];\n desta[2] = v8;\n }\n v10 = 3LL;\n goto LABEL_7;\n }\n return v15 - __readfsqword(0x28u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_13D0(char *dest, int a2) {\n const char *v2;\n int v3;\n int v4;\n int v5;\n int v6;\n char v7;\n char v8;\n short v9;\n unsigned int v10;\n char *v11;\n uint8_t desta[3];\n char v14;\n unsigned long long v15;\n v2 = dest;\n v15 = __readfsqword(40u);\n v3 = strlen(dest);\n v4 = v3;\n v5 = (v3 + 2) / 3;\n if (v3 > 0) {\n v6 = 0;\n while (1) {\n ++v6;\n if (3 * v6 <= v4) break;\n __strncpy_chk(desta, v2, v3, 4LL);\n v10 = v3;\n desta[v3] = 0;\n if (v3 == 3) goto LABEL_4;\n LABEL_7:\n v11 = (char *)v2;\n v2 += 3;\n v3 -= 3;\n strncpy(v11, desta, v10);\n if (v6 >= v5) return v15 - __readfsqword(40u);\n }\n strncpy(desta, v2, 3uLL);\n v14 = 0;\n LABEL_4:\n v7 = desta[2];\n v8 = desta[0];\n if (a2) {\n desta[2] = desta[1];\n LOBYTE(v9) = v7;\n HIBYTE(v9) = desta[0];\n *(unsigned short *)desta = v9;\n } else {\n *(unsigned short *)desta = *(unsigned short *)&desta[1];\n desta[2] = v8;\n }\n v10 = 3LL;\n goto LABEL_7;\n }\n return v15 - __readfsqword(40u);\n}", + "ida_pseudo_norm": "unsigned long long func0(char *dest, int a2) {\n const char *v2;\n int v3;\n int v4;\n int v5;\n int v6;\n char v7;\n char v8;\n short v9;\n unsigned int v10;\n char *v11;\n uint8_t desta[3];\n char v14;\n unsigned long long v15;\n v2 = dest;\n v15 = __readfsqword(40u);\n v3 = strlen(dest);\n v4 = v3;\n v5 = (v3 + 2) / 3;\n if (v3 > 0) {\n v6 = 0;\n while (1) {\n ++v6;\n if (3 * v6 <= v4) break;\n __strncpy_chk(desta, v2, v3, 4LL);\n v10 = v3;\n desta[v3] = 0;\n if (v3 == 3) goto LABEL_4;\n LABEL_7:\n v11 = (char *)v2;\n v2 += 3;\n v3 -= 3;\n strncpy(v11, desta, v10);\n if (v6 >= v5) return v15 - __readfsqword(40u);\n }\n strncpy(desta, v2, 3uLL);\n v14 = 0;\n LABEL_4:\n v7 = desta[2];\n v8 = desta[0];\n if (a2) {\n desta[2] = desta[1];\n LOBYTE(v9) = v7;\n HIBYTE(v9) = desta[0];\n *(unsigned short *)desta = v9;\n } else {\n *(unsigned short *)desta = *(unsigned short *)&desta[1];\n desta[2] = v8;\n }\n v10 = 3LL;\n goto LABEL_7;\n }\n return v15 - __readfsqword(40u);\n}" + }, + { + "index": "HumanEval-C-38", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(char *s, int encode) {\n int l = strlen(s);\n int num = (l + 2) / 3;\n char x[4];\n for (int i = 0; i < num; ++i) {\n int len = (i * 3 + 3 <= l) ? 3 : l - i * 3;\n strncpy(x, s + i * 3, len);\n x[len] = '\\0';\n if (len == 3) {\n if (encode) {\n char temp = x[2];\n x[2] = x[1];\n x[1] = x[0];\n x[0] = temp;\n } else {\n char temp = x[0];\n x[0] = x[1];\n x[1] = x[2];\n x[2] = temp;\n }\n }\n strncpy(s + i * 3, x, len);\n }\n}", + "test": "#include \n#include \n#include \n#include \n#include \n\nint main(){\n srand((unsigned int)time(NULL));\n char str[22], temp[22], decoded_str[22];\n\n for (int i = 0; i < 100; i++) {\n int l = 10 + rand() % 11;\n for (int j = 0; j < l; j++) {\n str[j] = 'a' + rand() % 26;\n }\n str[l] = '\\0';\n strcpy(temp, str);\n\n func0(temp, 1); // Encode\n strcpy(decoded_str, temp);\n func0(decoded_str, 0); // Decode\n\n assert(strcmp(decoded_str, str) == 0);\n }\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\nmov r15d, esi\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 28h\nmov rax, fs:28h\nmov [rsp+58h+var_40], rax\nxor eax, eax\ncall _strlen\nmov rbp, rax\nmov r14d, eax\nadd eax, 2\nmovsxd r13, eax\nsar eax, 1Fh\nimul r13, 55555556h\nshr r13, 20h\nsub r13d, eax\ntest ebp, ebp\njle loc_1698\ntest r15d, r15d\njnz loc_16C0\nlea r12, [rsp+58h+dest]\njmp short loc_165C\nloc_1618:\nmov edx, 3; n\nmov rsi, rbx; src\nmov rdi, r12; dest\ncall _strncpy\nmov [rsp+58h+var_41], 0\nloc_162D:\nmovzx eax, [rsp+58h+dest]\nmovzx edx, word ptr [rsp+58h+dest+1]\nmov [rsp+58h+var_42], al\nmov word ptr [rsp+58h+dest], dx\nmov edx, 3; n\nloc_1645:\nmov rdi, rbx; dest\nmov rsi, r12; src\nadd rbx, 3\nsub ebp, 3\ncall _strncpy\ncmp r13d, r15d\njle short loc_1698\nloc_165C:\nadd r15d, 1\nlea eax, [r15+r15*2]\ncmp r14d, eax\njge short loc_1618\nmovsxd rdx, ebp\nmov ecx, 4\nmov rsi, rbx\nmov rdi, r12\nmov [rsp+58h+var_50], rdx\ncall ___strncpy_chk\nmov rdx, [rsp+58h+var_50]\nmov [rsp+rdx+58h+dest], 0\ncmp ebp, 3\njnz short loc_1645\njmp short loc_162D\nloc_1698:\nmov rax, [rsp+58h+var_40]\nsub rax, fs:28h\njnz loc_174E\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_16C0:\nxor r15d, r15d\nlea r12, [rsp+58h+dest]\njmp short loc_1718\nloc_16D0:\nmov edx, 3; n\nmov rsi, rbx; src\nmov rdi, r12; dest\ncall _strncpy\nmov [rsp+58h+var_41], 0\nloc_16E5:\nmovzx eax, [rsp+58h+var_42]\nmov ah, [rsp+58h+dest]\nmovzx edx, [rsp+58h+dest+1]\nmov word ptr [rsp+58h+dest], ax\nmov [rsp+58h+var_42], dl\nmov edx, 3; n\nloc_1701:\nmov rdi, rbx; dest\nmov rsi, r12; src\nadd rbx, 3\nsub ebp, 3\ncall _strncpy\ncmp r15d, r13d\njge short loc_1698\nloc_1718:\nadd r15d, 1\nlea eax, [r15+r15*2]\ncmp r14d, eax\njge short loc_16D0\nmovsxd rdx, ebp\nmov ecx, 4\nmov rsi, rbx\nmov rdi, r12\nmov [rsp+58h+var_50], rdx\ncall ___strncpy_chk\nmov rdx, [rsp+58h+var_50]\nmov [rsp+rdx+58h+dest], 0\ncmp ebp, 3\njnz short loc_1701\njmp short loc_16E5\nloc_174E:\ncall ___stack_chk_fail", + "ida_pseudo": "unsigned __int64 __fastcall func0(char *dest, int a2)\n{\n int v2; // r15d\n const char *v3; // rbx\n int v4; // ebp\n int v5; // r14d\n int v6; // r13d\n __int16 v7; // dx\n size_t v8; // rdx\n char *v9; // rdi\n int v11; // r15d\n __int16 v12; // ax\n char v13; // dl\n size_t v14; // rdx\n char *v15; // rdi\n _BYTE desta[3]; // [rsp+14h] [rbp-44h] BYREF\n char v17; // [rsp+17h] [rbp-41h]\n unsigned __int64 v18; // [rsp+18h] [rbp-40h]\n\n v2 = a2;\n v3 = dest;\n v18 = __readfsqword(0x28u);\n v4 = strlen(dest);\n v5 = v4;\n v6 = (v4 + 2) / 3;\n if ( v4 > 0 )\n {\n if ( !a2 )\n {\n while ( 1 )\n {\n ++v2;\n if ( v5 >= 3 * v2 )\n {\n strncpy(desta, v3, 3uLL);\n v17 = 0;\n }\n else\n {\n __strncpy_chk(desta, v3, v4, 4LL);\n v8 = v4;\n desta[v4] = 0;\n if ( v4 != 3 )\n goto LABEL_6;\n }\n v7 = *(_WORD *)&desta[1];\n desta[2] = desta[0];\n *(_WORD *)desta = v7;\n v8 = 3LL;\nLABEL_6:\n v9 = (char *)v3;\n v3 += 3;\n v4 -= 3;\n strncpy(v9, desta, v8);\n if ( v6 <= v2 )\n return v18 - __readfsqword(0x28u);\n }\n }\n v11 = 0;\n do\n {\n ++v11;\n if ( v5 >= 3 * v11 )\n {\n strncpy(desta, v3, 3uLL);\n v17 = 0;\n }\n else\n {\n __strncpy_chk(desta, v3, v4, 4LL);\n v14 = v4;\n desta[v4] = 0;\n if ( v4 != 3 )\n goto LABEL_14;\n }\n LOBYTE(v12) = desta[2];\n HIBYTE(v12) = desta[0];\n v13 = desta[1];\n *(_WORD *)desta = v12;\n desta[2] = v13;\n v14 = 3LL;\nLABEL_14:\n v15 = (char *)v3;\n v3 += 3;\n v4 -= 3;\n strncpy(v15, desta, v14);\n }\n while ( v11 < v6 );\n }\n return v18 - __readfsqword(0x28u);\n}", + "ida_strip_asm": "sub_15B0:\nendbr64\npush r15\nmov r15d, esi\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 28h\nmov rax, fs:28h\nmov [rsp+58h+var_40], rax\nxor eax, eax\ncall _strlen\nmov rbp, rax\nmov r14d, eax\nadd eax, 2\nmovsxd r13, eax\nsar eax, 1Fh\nimul r13, 55555556h\nshr r13, 20h\nsub r13d, eax\ntest ebp, ebp\njle loc_1698\ntest r15d, r15d\njnz loc_16C0\nlea r12, [rsp+58h+dest]\njmp short loc_165C\nloc_1618:\nmov edx, 3; n\nmov rsi, rbx; src\nmov rdi, r12; dest\ncall _strncpy\nmov [rsp+58h+var_41], 0\nloc_162D:\nmovzx eax, [rsp+58h+dest]\nmovzx edx, word ptr [rsp+58h+dest+1]\nmov [rsp+58h+var_42], al\nmov word ptr [rsp+58h+dest], dx\nmov edx, 3; n\nloc_1645:\nmov rdi, rbx; dest\nmov rsi, r12; src\nadd rbx, 3\nsub ebp, 3\ncall _strncpy\ncmp r13d, r15d\njle short loc_1698\nloc_165C:\nadd r15d, 1\nlea eax, [r15+r15*2]\ncmp r14d, eax\njge short loc_1618\nmovsxd rdx, ebp\nmov ecx, 4\nmov rsi, rbx\nmov rdi, r12\nmov [rsp+58h+var_50], rdx\ncall ___strncpy_chk\nmov rdx, [rsp+58h+var_50]\nmov [rsp+rdx+58h+dest], 0\ncmp ebp, 3\njnz short loc_1645\njmp short loc_162D\nloc_1698:\nmov rax, [rsp+58h+var_40]\nsub rax, fs:28h\njnz loc_174E\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_16C0:\nxor r15d, r15d\nlea r12, [rsp+58h+dest]\njmp short loc_1718\nloc_16D0:\nmov edx, 3; n\nmov rsi, rbx; src\nmov rdi, r12; dest\ncall _strncpy\nmov [rsp+58h+var_41], 0\nloc_16E5:\nmovzx eax, [rsp+58h+var_42]\nmov ah, [rsp+58h+dest]\nmovzx edx, [rsp+58h+dest+1]\nmov word ptr [rsp+58h+dest], ax\nmov [rsp+58h+var_42], dl\nmov edx, 3; n\nloc_1701:\nmov rdi, rbx; dest\nmov rsi, r12; src\nadd rbx, 3\nsub ebp, 3\ncall _strncpy\ncmp r15d, r13d\njge short loc_1698\nloc_1718:\nadd r15d, 1\nlea eax, [r15+r15*2]\ncmp r14d, eax\njge short loc_16D0\nmovsxd rdx, ebp\nmov ecx, 4\nmov rsi, rbx\nmov rdi, r12\nmov [rsp+58h+var_50], rdx\ncall ___strncpy_chk\nmov rdx, [rsp+58h+var_50]\nmov [rsp+rdx+58h+dest], 0\ncmp ebp, 3\njnz short loc_1701\njmp short loc_16E5\nloc_174E:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_15B0(char *dest, int a2)\n{\n int v2; // r15d\n const char *v3; // rbx\n int v4; // ebp\n int v5; // r14d\n int v6; // r13d\n __int16 v7; // dx\n size_t v8; // rdx\n char *v9; // rdi\n int v11; // r15d\n __int16 v12; // ax\n char v13; // dl\n size_t v14; // rdx\n char *v15; // rdi\n _BYTE desta[3]; // [rsp+14h] [rbp-44h] BYREF\n char v17; // [rsp+17h] [rbp-41h]\n unsigned __int64 v18; // [rsp+18h] [rbp-40h]\n\n v2 = a2;\n v3 = dest;\n v18 = __readfsqword(0x28u);\n v4 = strlen(dest);\n v5 = v4;\n v6 = (v4 + 2) / 3;\n if ( v4 > 0 )\n {\n if ( !a2 )\n {\n while ( 1 )\n {\n ++v2;\n if ( v5 >= 3 * v2 )\n {\n strncpy(desta, v3, 3uLL);\n v17 = 0;\n }\n else\n {\n __strncpy_chk(desta, v3, v4, 4LL);\n v8 = v4;\n desta[v4] = 0;\n if ( v4 != 3 )\n goto LABEL_6;\n }\n v7 = *(_WORD *)&desta[1];\n desta[2] = desta[0];\n *(_WORD *)desta = v7;\n v8 = 3LL;\nLABEL_6:\n v9 = (char *)v3;\n v3 += 3;\n v4 -= 3;\n strncpy(v9, desta, v8);\n if ( v6 <= v2 )\n return v18 - __readfsqword(0x28u);\n }\n }\n v11 = 0;\n do\n {\n ++v11;\n if ( v5 >= 3 * v11 )\n {\n strncpy(desta, v3, 3uLL);\n v17 = 0;\n }\n else\n {\n __strncpy_chk(desta, v3, v4, 4LL);\n v14 = v4;\n desta[v4] = 0;\n if ( v4 != 3 )\n goto LABEL_14;\n }\n LOBYTE(v12) = desta[2];\n HIBYTE(v12) = desta[0];\n v13 = desta[1];\n *(_WORD *)desta = v12;\n desta[2] = v13;\n v14 = 3LL;\nLABEL_14:\n v15 = (char *)v3;\n v3 += 3;\n v4 -= 3;\n strncpy(v15, desta, v14);\n }\n while ( v11 < v6 );\n }\n return v18 - __readfsqword(0x28u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_15B0(char *dest, int a2) {\n int v2;\n const char *v3;\n int v4;\n int v5;\n int v6;\n short v7;\n unsigned int v8;\n char *v9;\n int v11;\n short v12;\n char v13;\n unsigned int v14;\n char *v15;\n uint8_t desta[3];\n char v17;\n unsigned long long v18;\n v2 = a2;\n v3 = dest;\n v18 = __readfsqword(40u);\n v4 = strlen(dest);\n v5 = v4;\n v6 = (v4 + 2) / 3;\n if (v4 > 0) {\n if (!a2) {\n while (1) {\n ++v2;\n if (v5 >= 3 * v2) {\n strncpy(desta, v3, 3uLL);\n v17 = 0;\n } else {\n __strncpy_chk(desta, v3, v4, 4LL);\n v8 = v4;\n desta[v4] = 0;\n if (v4 != 3) goto LABEL_6;\n }\n v7 = *(unsigned short *)&desta[1];\n desta[2] = desta[0];\n *(unsigned short *)desta = v7;\n v8 = 3LL;\n LABEL_6:\n v9 = (char *)v3;\n v3 += 3;\n v4 -= 3;\n strncpy(v9, desta, v8);\n if (v6 <= v2) return v18 - __readfsqword(40u);\n }\n }\n v11 = 0;\n do {\n ++v11;\n if (v5 >= 3 * v11) {\n strncpy(desta, v3, 3uLL);\n v17 = 0;\n } else {\n __strncpy_chk(desta, v3, v4, 4LL);\n v14 = v4;\n desta[v4] = 0;\n if (v4 != 3) goto LABEL_14;\n }\n LOBYTE(v12) = desta[2];\n HIBYTE(v12) = desta[0];\n v13 = desta[1];\n *(unsigned short *)desta = v12;\n desta[2] = v13;\n v14 = 3LL;\n LABEL_14:\n v15 = (char *)v3;\n v3 += 3;\n v4 -= 3;\n strncpy(v15, desta, v14);\n } while (v11 < v6);\n }\n return v18 - __readfsqword(40u);\n}", + "ida_pseudo_norm": "unsigned long long func0(char *dest, int a2) {\n int v2;\n const char *v3;\n int v4;\n int v5;\n int v6;\n short v7;\n unsigned int v8;\n char *v9;\n int v11;\n short v12;\n char v13;\n unsigned int v14;\n char *v15;\n uint8_t desta[3];\n char v17;\n unsigned long long v18;\n v2 = a2;\n v3 = dest;\n v18 = __readfsqword(40u);\n v4 = strlen(dest);\n v5 = v4;\n v6 = (v4 + 2) / 3;\n if (v4 > 0) {\n if (!a2) {\n while (1) {\n ++v2;\n if (v5 >= 3 * v2) {\n strncpy(desta, v3, 3uLL);\n v17 = 0;\n } else {\n __strncpy_chk(desta, v3, v4, 4LL);\n v8 = v4;\n desta[v4] = 0;\n if (v4 != 3) goto LABEL_6;\n }\n v7 = *(unsigned short *)&desta[1];\n desta[2] = desta[0];\n *(unsigned short *)desta = v7;\n v8 = 3LL;\n LABEL_6:\n v9 = (char *)v3;\n v3 += 3;\n v4 -= 3;\n strncpy(v9, desta, v8);\n if (v6 <= v2) return v18 - __readfsqword(40u);\n }\n }\n v11 = 0;\n do {\n ++v11;\n if (v5 >= 3 * v11) {\n strncpy(desta, v3, 3uLL);\n v17 = 0;\n } else {\n __strncpy_chk(desta, v3, v4, 4LL);\n v14 = v4;\n desta[v4] = 0;\n if (v4 != 3) goto LABEL_14;\n }\n LOBYTE(v12) = desta[2];\n HIBYTE(v12) = desta[0];\n v13 = desta[1];\n *(unsigned short *)desta = v12;\n desta[2] = v13;\n v14 = 3LL;\n LABEL_14:\n v15 = (char *)v3;\n v3 += 3;\n v4 -= 3;\n strncpy(v15, desta, v14);\n } while (v11 < v6);\n }\n return v18 - __readfsqword(40u);\n}" + }, + { + "index": "HumanEval-C-39", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int n) {\n int f1 = 1, f2 = 2, m;\n int count = 0;\n while (count < n) {\n f1 = f1 + f2;\n m = f1;\n f1 = f2;\n f2 = m;\n int isprime = 1;\n for (int w = 2; w * w <= f1; w++) {\n if (f1 % w == 0) {\n isprime = 0;\n break;\n }\n }\n if (isprime) count += 1;\n if (count == n) return f1;\n }\n return 0;\n}", + "test": "#include \n#include \n\nint main() {\n assert(func0(1) == 2);\n assert(func0(2) == 3);\n assert(func0(3) == 5);\n assert(func0(4) == 13);\n assert(func0(5) == 89);\n assert(func0(6) == 233);\n assert(func0(7) == 1597);\n assert(func0(8) == 28657);\n assert(func0(9) == 514229);\n assert(func0(10) == 433494437);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_24], edi\nmov [rbp+var_18], 1\nmov [rbp+var_14], 2\nmov [rbp+var_10], 0\njmp short loc_11CF\nloc_116B:\nmov eax, [rbp+var_14]\nadd [rbp+var_18], eax\nmov eax, [rbp+var_18]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_14]\nmov [rbp+var_18], eax\nmov eax, [rbp+var_4]\nmov [rbp+var_14], eax\nmov [rbp+var_C], 1\nmov [rbp+var_8], 2\njmp short loc_11AD\nloc_1193:\nmov eax, [rbp+var_18]\ncdq\nidiv [rbp+var_8]\nmov eax, edx\ntest eax, eax\njnz short loc_11A9\nmov [rbp+var_C], 0\njmp short loc_11B8\nloc_11A9:\nadd [rbp+var_8], 1\nloc_11AD:\nmov eax, [rbp+var_8]\nimul eax, eax\ncmp [rbp+var_18], eax\njge short loc_1193\nloc_11B8:\ncmp [rbp+var_C], 0\njz short loc_11C2\nadd [rbp+var_10], 1\nloc_11C2:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_24]\njnz short loc_11CF\nmov eax, [rbp+var_18]\njmp short loc_11DC\nloc_11CF:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_24]\njl short loc_116B\nmov eax, 0\nloc_11DC:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v2; // [rsp+Ch] [rbp-18h]\n int v3; // [rsp+10h] [rbp-14h]\n int v4; // [rsp+14h] [rbp-10h]\n int v5; // [rsp+18h] [rbp-Ch]\n int i; // [rsp+1Ch] [rbp-8h]\n int v7; // [rsp+20h] [rbp-4h]\n\n v2 = 1;\n v3 = 2;\n v4 = 0;\n while ( v4 < a1 )\n {\n v7 = v3 + v2;\n v2 = v3;\n v3 = v7;\n v5 = 1;\n for ( i = 2; v2 >= i * i; ++i )\n {\n if ( !(v2 % i) )\n {\n v5 = 0;\n break;\n }\n }\n if ( v5 )\n ++v4;\n if ( v4 == a1 )\n return (unsigned int)v2;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_24], edi\nmov [rbp+var_18], 1\nmov [rbp+var_14], 2\nmov [rbp+var_10], 0\njmp short loc_11CF\nloc_116B:\nmov eax, [rbp+var_14]\nadd [rbp+var_18], eax\nmov eax, [rbp+var_18]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_14]\nmov [rbp+var_18], eax\nmov eax, [rbp+var_4]\nmov [rbp+var_14], eax\nmov [rbp+var_C], 1\nmov [rbp+var_8], 2\njmp short loc_11AD\nloc_1193:\nmov eax, [rbp+var_18]\ncdq\nidiv [rbp+var_8]\nmov eax, edx\ntest eax, eax\njnz short loc_11A9\nmov [rbp+var_C], 0\njmp short loc_11B8\nloc_11A9:\nadd [rbp+var_8], 1\nloc_11AD:\nmov eax, [rbp+var_8]\nimul eax, eax\ncmp [rbp+var_18], eax\njge short loc_1193\nloc_11B8:\ncmp [rbp+var_C], 0\njz short loc_11C2\nadd [rbp+var_10], 1\nloc_11C2:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_24]\njnz short loc_11CF\nmov eax, [rbp+var_18]\njmp short loc_11DC\nloc_11CF:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_24]\njl short loc_116B\nmov eax, 0\nloc_11DC:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v2; // [rsp+Ch] [rbp-18h]\n int v3; // [rsp+10h] [rbp-14h]\n int v4; // [rsp+14h] [rbp-10h]\n int v5; // [rsp+18h] [rbp-Ch]\n int i; // [rsp+1Ch] [rbp-8h]\n int v7; // [rsp+20h] [rbp-4h]\n\n v2 = 1;\n v3 = 2;\n v4 = 0;\n while ( v4 < a1 )\n {\n v7 = v3 + v2;\n v2 = v3;\n v3 = v7;\n v5 = 1;\n for ( i = 2; v2 >= i * i; ++i )\n {\n if ( !(v2 % i) )\n {\n v5 = 0;\n break;\n }\n }\n if ( v5 )\n ++v4;\n if ( v4 == a1 )\n return (unsigned int)v2;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v2;\n int v3;\n int v4;\n int v5;\n int i;\n int v7;\n v2 = 1;\n v3 = 2;\n v4 = 0;\n while (v4 < a1) {\n v7 = v3 + v2;\n v2 = v3;\n v3 = v7;\n v5 = 1;\n for (i = 2; v2 >= i * i; ++i) {\n if (!(v2 % i)) {\n v5 = 0;\n break;\n }\n }\n if (v5) ++v4;\n if (v4 == a1) return (unsigned int)v2;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v2;\n int v3;\n int v4;\n int v5;\n int i;\n int v7;\n v2 = 1;\n v3 = 2;\n v4 = 0;\n while (v4 < a1) {\n v7 = v3 + v2;\n v2 = v3;\n v3 = v7;\n v5 = 1;\n for (i = 2; v2 >= i * i; ++i) {\n if (!(v2 % i)) {\n v5 = 0;\n break;\n }\n }\n if (v5) ++v4;\n if (v4 == a1) return (unsigned int)v2;\n }\n return 0LL;\n}" + }, + { + "index": "HumanEval-C-39", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int n) {\n int f1 = 1, f2 = 2, m;\n int count = 0;\n while (count < n) {\n f1 = f1 + f2;\n m = f1;\n f1 = f2;\n f2 = m;\n int isprime = 1;\n for (int w = 2; w * w <= f1; w++) {\n if (f1 % w == 0) {\n isprime = 0;\n break;\n }\n }\n if (isprime) count += 1;\n if (count == n) return f1;\n }\n return 0;\n}", + "test": "#include \n#include \n\nint main() {\n assert(func0(1) == 2);\n assert(func0(2) == 3);\n assert(func0(3) == 5);\n assert(func0(4) == 13);\n assert(func0(5) == 89);\n assert(func0(6) == 233);\n assert(func0(7) == 1597);\n assert(func0(8) == 28657);\n assert(func0(9) == 514229);\n assert(func0(10) == 433494437);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmov r8d, 0\nmov esi, 2\nmov eax, 1\njmp short loc_116D\nloc_115F:\nadd r8d, 1\ncmp edi, r8d\njz short loc_11A2\nloc_1168:\nmov eax, esi\nmov esi, r9d\nloc_116D:\ncmp r8d, edi\njge short loc_119D\nlea r9d, [rax+rsi]\ncmp esi, 3\njle short loc_115F\ntest sil, 1\njz short loc_1168\nmov ecx, 2\nloc_1186:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, esi\njg short loc_115F\nmov eax, esi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_1186\njmp short loc_1168\nloc_119D:\nmov esi, 0\nloc_11A2:\nmov eax, esi\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // r8d\n int v2; // esi\n int v3; // eax\n int v4; // r9d\n int v5; // ecx\n\n v1 = 0;\n v2 = 2;\n v3 = 1;\n while ( v1 < a1 )\n {\n v4 = v3 + v2;\n if ( v2 > 3 )\n {\n if ( (v2 & 1) == 0 )\n goto LABEL_3;\n v5 = 2;\n while ( 1 )\n {\n ++v5;\n if ( v5 * v5 > v2 )\n break;\n if ( !(v2 % v5) )\n goto LABEL_3;\n }\n }\n if ( a1 == ++v1 )\n return (unsigned int)v2;\nLABEL_3:\n v3 = v2;\n v2 = v4;\n }\n return 0;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmov r8d, 0\nmov esi, 2\nmov eax, 1\njmp short loc_116D\nloc_115F:\nadd r8d, 1\ncmp edi, r8d\njz short loc_11A2\nloc_1168:\nmov eax, esi\nmov esi, r9d\nloc_116D:\ncmp r8d, edi\njge short loc_119D\nlea r9d, [rax+rsi]\ncmp esi, 3\njle short loc_115F\ntest sil, 1\njz short loc_1168\nmov ecx, 2\nloc_1186:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, esi\njg short loc_115F\nmov eax, esi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_1186\njmp short loc_1168\nloc_119D:\nmov esi, 0\nloc_11A2:\nmov eax, esi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v1; // r8d\n int v2; // esi\n int v3; // eax\n int v4; // r9d\n int v5; // ecx\n\n v1 = 0;\n v2 = 2;\n v3 = 1;\n while ( v1 < a1 )\n {\n v4 = v3 + v2;\n if ( v2 > 3 )\n {\n if ( (v2 & 1) == 0 )\n goto LABEL_3;\n v5 = 2;\n while ( 1 )\n {\n ++v5;\n if ( v5 * v5 > v2 )\n break;\n if ( !(v2 % v5) )\n goto LABEL_3;\n }\n }\n if ( a1 == ++v1 )\n return (unsigned int)v2;\nLABEL_3:\n v3 = v2;\n v2 = v4;\n }\n return 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v1;\n int v2;\n int v3;\n int v4;\n int v5;\n v1 = 0;\n v2 = 2;\n v3 = 1;\n while (v1 < a1) {\n v4 = v3 + v2;\n if (v2 > 3) {\n if ((v2 & 1) == 0) goto LABEL_3;\n v5 = 2;\n while (1) {\n ++v5;\n if (v5 * v5 > v2) break;\n if (!(v2 % v5)) goto LABEL_3;\n }\n }\n if (a1 == ++v1) return (unsigned int)v2;\n LABEL_3:\n v3 = v2;\n v2 = v4;\n }\n return 0;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v2;\n int v3;\n int v4;\n int v5;\n v1 = 0;\n v2 = 2;\n v3 = 1;\n while (v1 < a1) {\n v4 = v3 + v2;\n if (v2 > 3) {\n if ((v2 & 1) == 0) goto LABEL_3;\n v5 = 2;\n while (1) {\n ++v5;\n if (v5 * v5 > v2) break;\n if (!(v2 % v5)) goto LABEL_3;\n }\n }\n if (a1 == ++v1) return (unsigned int)v2;\n LABEL_3:\n v3 = v2;\n v2 = v4;\n }\n return 0;\n}" + }, + { + "index": "HumanEval-C-39", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int n) {\n int f1 = 1, f2 = 2, m;\n int count = 0;\n while (count < n) {\n f1 = f1 + f2;\n m = f1;\n f1 = f2;\n f2 = m;\n int isprime = 1;\n for (int w = 2; w * w <= f1; w++) {\n if (f1 % w == 0) {\n isprime = 0;\n break;\n }\n }\n if (isprime) count += 1;\n if (count == n) return f1;\n }\n return 0;\n}", + "test": "#include \n#include \n\nint main() {\n assert(func0(1) == 2);\n assert(func0(2) == 3);\n assert(func0(3) == 5);\n assert(func0(4) == 13);\n assert(func0(5) == 89);\n assert(func0(6) == 233);\n assert(func0(7) == 1597);\n assert(func0(8) == 28657);\n assert(func0(9) == 514229);\n assert(func0(10) == 433494437);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nxor r8d, r8d\nmov esi, 2\nmov eax, 1\ncmp r8d, edi\njge short loc_13C8\nnop word ptr [rax+rax+00000000h]\nloc_1380:\nlea r9d, [rax+rsi]\ncmp esi, 3\njle short loc_13B5\ntest sil, 1\njz short loc_13BE\nmov ecx, 2\njmp short loc_13A9\nloc_13A0:\nmov eax, esi\ncdq\nidiv ecx\ntest edx, edx\njz short loc_13BE\nloc_13A9:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, esi\njle short loc_13A0\nloc_13B5:\nadd r8d, 1\ncmp edi, r8d\njz short loc_13CA\nloc_13BE:\nmov eax, esi\nmov esi, r9d\ncmp r8d, edi\njl short loc_1380\nloc_13C8:\nxor esi, esi\nloc_13CA:\nmov eax, esi\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // r8d\n int v2; // esi\n int v3; // eax\n int v4; // r9d\n int v5; // ecx\n\n v1 = 0;\n v2 = 2;\n v3 = 1;\n if ( a1 > 0 )\n {\n while ( 1 )\n {\n v4 = v3 + v2;\n if ( v2 <= 3 )\n goto LABEL_7;\n if ( (v2 & 1) != 0 )\n break;\nLABEL_8:\n v3 = v2;\n v2 = v4;\n if ( v1 >= a1 )\n return 0;\n }\n v5 = 2;\n while ( 1 )\n {\n ++v5;\n if ( v5 * v5 > v2 )\n break;\n if ( !(v2 % v5) )\n goto LABEL_8;\n }\nLABEL_7:\n if ( a1 == ++v1 )\n return (unsigned int)v2;\n goto LABEL_8;\n }\n return 0;\n}", + "ida_strip_asm": "sub_1360:\nendbr64\nxor r8d, r8d\nmov esi, 2\nmov eax, 1\ncmp r8d, edi\njge short loc_13C8\nnop word ptr [rax+rax+00000000h]\nloc_1380:\nlea r9d, [rax+rsi]\ncmp esi, 3\njle short loc_13B5\ntest sil, 1\njz short loc_13BE\nmov ecx, 2\njmp short loc_13A9\nloc_13A0:\nmov eax, esi\ncdq\nidiv ecx\ntest edx, edx\njz short loc_13BE\nloc_13A9:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, esi\njle short loc_13A0\nloc_13B5:\nadd r8d, 1\ncmp edi, r8d\njz short loc_13CA\nloc_13BE:\nmov eax, esi\nmov esi, r9d\ncmp r8d, edi\njl short loc_1380\nloc_13C8:\nxor esi, esi\nloc_13CA:\nmov eax, esi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1360(int a1)\n{\n int v1; // r8d\n int v2; // esi\n int v3; // eax\n int v4; // r9d\n int v5; // ecx\n\n v1 = 0;\n v2 = 2;\n v3 = 1;\n if ( a1 > 0 )\n {\n while ( 1 )\n {\n v4 = v3 + v2;\n if ( v2 <= 3 )\n goto LABEL_7;\n if ( (v2 & 1) != 0 )\n break;\nLABEL_8:\n v3 = v2;\n v2 = v4;\n if ( v1 >= a1 )\n return 0;\n }\n v5 = 2;\n while ( 1 )\n {\n ++v5;\n if ( v5 * v5 > v2 )\n break;\n if ( !(v2 % v5) )\n goto LABEL_8;\n }\nLABEL_7:\n if ( a1 == ++v1 )\n return (unsigned int)v2;\n goto LABEL_8;\n }\n return 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1360(int a1) {\n int v1;\n int v2;\n int v3;\n int v4;\n int v5;\n v1 = 0;\n v2 = 2;\n v3 = 1;\n if (a1 > 0) {\n while (1) {\n v4 = v3 + v2;\n if (v2 <= 3) goto LABEL_7;\n if ((v2 & 1) != 0) break;\n LABEL_8:\n v3 = v2;\n v2 = v4;\n if (v1 >= a1) return 0;\n }\n v5 = 2;\n while (1) {\n ++v5;\n if (v5 * v5 > v2) break;\n if (!(v2 % v5)) goto LABEL_8;\n }\n LABEL_7:\n if (a1 == ++v1) return (unsigned int)v2;\n goto LABEL_8;\n }\n return 0;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v2;\n int v3;\n int v4;\n int v5;\n v1 = 0;\n v2 = 2;\n v3 = 1;\n if (a1 > 0) {\n while (1) {\n v4 = v3 + v2;\n if (v2 <= 3) goto LABEL_7;\n if ((v2 & 1) != 0) break;\n LABEL_8:\n v3 = v2;\n v2 = v4;\n if (v1 >= a1) return 0;\n }\n v5 = 2;\n while (1) {\n ++v5;\n if (v5 * v5 > v2) break;\n if (!(v2 % v5)) goto LABEL_8;\n }\n LABEL_7:\n if (a1 == ++v1) return (unsigned int)v2;\n goto LABEL_8;\n }\n return 0;\n}" + }, + { + "index": "HumanEval-C-40", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "bool func0(int *l, int size) {\n for (int i = 0; i < size; i++)\n for (int j = i + 1; j < size; j++)\n for (int k = j + 1; k < size; k++)\n if (l[i] + l[j] + l[k] == 0) return true;\n return false;\n}", + "test": "#include \n#include \n\nint main() {\n int test1[] = {1, 3, 5, 0};\n assert(func0(test1, 4) == false);\n \n int test2[] = {1, 3, 5, -1};\n assert(func0(test2, 4) == false);\n \n int test3[] = {1, 3, -2, 1};\n assert(func0(test3, 4) == true);\n \n int test4[] = {1, 2, 3, 7};\n assert(func0(test4, 4) == false);\n \n int test5[] = {1, 2, 5, 7};\n assert(func0(test5, 4) == false);\n \n int test6[] = {2, 4, -5, 3, 9, 7};\n assert(func0(test6, 6) == true);\n \n int test7[] = {1};\n assert(func0(test7, 1) == false);\n \n int test8[] = {1, 3, 5, -100};\n assert(func0(test8, 4) == false);\n \n int test9[] = {100, 3, 5, -100};\n assert(func0(test9, 4) == false);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0\njmp loc_1207\nloc_1184:\nmov eax, [rbp+var_C]\nadd eax, 1\nmov [rbp+var_8], eax\njmp short loc_11FB\nloc_118F:\nmov eax, [rbp+var_8]\nadd eax, 1\nmov [rbp+var_4], eax\njmp short loc_11EF\nloc_119A:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nadd edx, eax\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nadd eax, edx\ntest eax, eax\njnz short loc_11EB\nmov eax, 1\njmp short loc_1218\nloc_11EB:\nadd [rbp+var_4], 1\nloc_11EF:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_119A\nadd [rbp+var_8], 1\nloc_11FB:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_118F\nadd [rbp+var_C], 1\nloc_1207:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl loc_1184\nmov eax, 0\nloc_1218:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+10h] [rbp-Ch]\n int j; // [rsp+14h] [rbp-8h]\n int k; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n for ( k = j + 1; k < a2; ++k )\n {\n if ( !(*(_DWORD *)(4LL * j + a1) + *(_DWORD *)(4LL * i + a1) + *(_DWORD *)(4LL * k + a1)) )\n return 1LL;\n }\n }\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0\njmp loc_1207\nloc_1184:\nmov eax, [rbp+var_C]\nadd eax, 1\nmov [rbp+var_8], eax\njmp short loc_11FB\nloc_118F:\nmov eax, [rbp+var_8]\nadd eax, 1\nmov [rbp+var_4], eax\njmp short loc_11EF\nloc_119A:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nadd edx, eax\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nadd eax, edx\ntest eax, eax\njnz short loc_11EB\nmov eax, 1\njmp short loc_1218\nloc_11EB:\nadd [rbp+var_4], 1\nloc_11EF:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_119A\nadd [rbp+var_8], 1\nloc_11FB:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_118F\nadd [rbp+var_C], 1\nloc_1207:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl loc_1184\nmov eax, 0\nloc_1218:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int i; // [rsp+10h] [rbp-Ch]\n int j; // [rsp+14h] [rbp-8h]\n int k; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n for ( k = j + 1; k < a2; ++k )\n {\n if ( !(*(_DWORD *)(4LL * j + a1) + *(_DWORD *)(4LL * i + a1) + *(_DWORD *)(4LL * k + a1)) )\n return 1LL;\n }\n }\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int i;\n int j;\n int k;\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n for (k = j + 1; k < a2; ++k) {\n if (!(*(uint32_t *)(4LL * j + a1) + *(uint32_t *)(4LL * i + a1) +\n *(uint32_t *)(4LL * k + a1)))\n return 1LL;\n }\n }\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int i;\n int j;\n int k;\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n for (k = j + 1; k < a2; ++k) {\n if (!(*(uint32_t *)(4LL * j + a1) + *(uint32_t *)(4LL * i + a1) +\n *(uint32_t *)(4LL * k + a1)))\n return 1LL;\n }\n }\n }\n return 0LL;\n}" + }, + { + "index": "HumanEval-C-40", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "bool func0(int *l, int size) {\n for (int i = 0; i < size; i++)\n for (int j = i + 1; j < size; j++)\n for (int k = j + 1; k < size; k++)\n if (l[i] + l[j] + l[k] == 0) return true;\n return false;\n}", + "test": "#include \n#include \n\nint main() {\n int test1[] = {1, 3, 5, 0};\n assert(func0(test1, 4) == false);\n \n int test2[] = {1, 3, 5, -1};\n assert(func0(test2, 4) == false);\n \n int test3[] = {1, 3, -2, 1};\n assert(func0(test3, 4) == true);\n \n int test4[] = {1, 2, 3, 7};\n assert(func0(test4, 4) == false);\n \n int test5[] = {1, 2, 5, 7};\n assert(func0(test5, 4) == false);\n \n int test6[] = {2, 4, -5, 3, 9, 7};\n assert(func0(test6, 6) == true);\n \n int test7[] = {1};\n assert(func0(test7, 1) == false);\n \n int test8[] = {1, 3, 5, -100};\n assert(func0(test8, 4) == false);\n \n int test9[] = {100, 3, 5, -100};\n assert(func0(test9, 4) == false);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11D8\nlea r11d, [rsi+1]\nmovsxd rax, esi\nlea r10, [rax+2]\nmov r9d, 2\ncmp r9, r11\njz short loc_11EC\npush rbx\njmp short loc_1198\nloc_118A:\nadd r9, 1\ncmp r9, r10\njz short loc_11D1\ncmp r9, r11\njz short loc_11DE\nloc_1198:\nmov eax, esi\nsub eax, r9d\nlea rbx, [r9+rax+1]\nmov r8, r9\nloc_11A5:\ncmp esi, r8d\njle short loc_118A\nmov edx, [rdi+r8*4-4]\nadd edx, [rdi+r9*4-8]\nmov rax, r8\nloc_11B7:\nmov ecx, edx\nadd ecx, [rdi+rax*4]\njz short loc_11E5\nadd rax, 1\ncmp esi, eax\njg short loc_11B7\nadd r8, 1\ncmp r8, rbx\njnz short loc_11A5\njmp short loc_118A\nloc_11D1:\nmov eax, 0\njmp short loc_11EA\nloc_11D8:\nmov eax, 0\nretn\nloc_11DE:\nmov eax, 0\njmp short loc_11EA\nloc_11E5:\nmov eax, 1\nloc_11EA:\npop rbx\nretn\nloc_11EC:\nmov eax, 0\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // r11\n __int64 v3; // r9\n __int64 v4; // r8\n __int64 v5; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = (unsigned int)(a2 + 1);\n v3 = 2LL;\n if ( v2 == 2 )\n return 0LL;\n do\n {\n v4 = v3;\n while ( 2 )\n {\n if ( a2 > (int)v4 )\n {\n v5 = v4;\n do\n {\n if ( !(*(_DWORD *)(a1 + 4 * v5) + *(_DWORD *)(a1 + 4 * v3 - 8) + *(_DWORD *)(a1 + 4 * v4 - 4)) )\n return 1LL;\n ++v5;\n }\n while ( a2 > (int)v5 );\n if ( ++v4 != v3 + (unsigned int)(a2 - v3) + 1 )\n continue;\n }\n break;\n }\n if ( ++v3 == a2 + 2LL )\n return 0LL;\n }\n while ( v3 != v2 );\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11D8\nlea r11d, [rsi+1]\nmovsxd rax, esi\nlea r10, [rax+2]\nmov r9d, 2\ncmp r9, r11\njz short loc_11EC\npush rbx\njmp short loc_1198\nloc_118A:\nadd r9, 1\ncmp r9, r10\njz short loc_11D1\ncmp r9, r11\njz short loc_11DE\nloc_1198:\nmov eax, esi\nsub eax, r9d\nlea rbx, [r9+rax+1]\nmov r8, r9\nloc_11A5:\ncmp esi, r8d\njle short loc_118A\nmov edx, [rdi+r8*4-4]\nadd edx, [rdi+r9*4-8]\nmov rax, r8\nloc_11B7:\nmov ecx, edx\nadd ecx, [rdi+rax*4]\njz short loc_11E5\nadd rax, 1\ncmp esi, eax\njg short loc_11B7\nadd r8, 1\ncmp r8, rbx\njnz short loc_11A5\njmp short loc_118A\nloc_11D1:\nmov eax, 0\njmp short loc_11EA\nloc_11D8:\nmov eax, 0\nretn\nloc_11DE:\nmov eax, 0\njmp short loc_11EA\nloc_11E5:\nmov eax, 1\nloc_11EA:\npop rbx\nretn\nloc_11EC:\nmov eax, 0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n __int64 v2; // r11\n __int64 v3; // r9\n __int64 v4; // r8\n __int64 v5; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = (unsigned int)(a2 + 1);\n v3 = 2LL;\n if ( v2 == 2 )\n return 0LL;\n do\n {\n v4 = v3;\n while ( 2 )\n {\n if ( a2 > (int)v4 )\n {\n v5 = v4;\n do\n {\n if ( !(*(_DWORD *)(a1 + 4 * v5) + *(_DWORD *)(a1 + 4 * v3 - 8) + *(_DWORD *)(a1 + 4 * v4 - 4)) )\n return 1LL;\n ++v5;\n }\n while ( a2 > (int)v5 );\n if ( ++v4 != v3 + (unsigned int)(a2 - v3) + 1 )\n continue;\n }\n break;\n }\n if ( ++v3 == a2 + 2LL )\n return 0LL;\n }\n while ( v3 != v2 );\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n long long v2;\n long long v3;\n long long v4;\n long long v5;\n if (a2 <= 0) return 0LL;\n v2 = (unsigned int)(a2 + 1);\n v3 = 2LL;\n if (v2 == 2) return 0LL;\n do {\n v4 = v3;\n while (2) {\n if (a2 > (int)v4) {\n v5 = v4;\n do {\n if (!(*(uint32_t *)(a1 + 4 * v5) + *(uint32_t *)(a1 + 4 * v3 - 8) +\n *(uint32_t *)(a1 + 4 * v4 - 4)))\n return 1LL;\n ++v5;\n } while (a2 > (int)v5);\n if (++v4 != v3 + (unsigned int)(a2 - v3) + 1) continue;\n }\n break;\n }\n if (++v3 == a2 + 2LL) return 0LL;\n } while (v3 != v2);\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n long long v3;\n long long v4;\n long long v5;\n if (a2 <= 0) return 0LL;\n v2 = (unsigned int)(a2 + 1);\n v3 = 2LL;\n if (v2 == 2) return 0LL;\n do {\n v4 = v3;\n while (2) {\n if (a2 > (int)v4) {\n v5 = v4;\n do {\n if (!(*(uint32_t *)(a1 + 4 * v5) + *(uint32_t *)(a1 + 4 * v3 - 8) +\n *(uint32_t *)(a1 + 4 * v4 - 4)))\n return 1LL;\n ++v5;\n } while (a2 > (int)v5);\n if (++v4 != v3 + (unsigned int)(a2 - v3) + 1) continue;\n }\n break;\n }\n if (++v3 == a2 + 2LL) return 0LL;\n } while (v3 != v2);\n return 0LL;\n}" + }, + { + "index": "HumanEval-C-40", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "bool func0(int *l, int size) {\n for (int i = 0; i < size; i++)\n for (int j = i + 1; j < size; j++)\n for (int k = j + 1; k < size; k++)\n if (l[i] + l[j] + l[k] == 0) return true;\n return false;\n}", + "test": "#include \n#include \n\nint main() {\n int test1[] = {1, 3, 5, 0};\n assert(func0(test1, 4) == false);\n \n int test2[] = {1, 3, 5, -1};\n assert(func0(test2, 4) == false);\n \n int test3[] = {1, 3, -2, 1};\n assert(func0(test3, 4) == true);\n \n int test4[] = {1, 2, 3, 7};\n assert(func0(test4, 4) == false);\n \n int test5[] = {1, 2, 5, 7};\n assert(func0(test5, 4) == false);\n \n int test6[] = {2, 4, -5, 3, 9, 7};\n assert(func0(test6, 6) == true);\n \n int test7[] = {1};\n assert(func0(test7, 1) == false);\n \n int test8[] = {1, 3, 5, -100};\n assert(func0(test8, 4) == false);\n \n int test9[] = {100, 3, 5, -100};\n assert(func0(test9, 4) == false);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1477\nlea r10d, [rsi+1]\nmov r9d, 2\nloc_1432:\ncmp r10, r9\njz short loc_1477\nmov r8, r9\ncmp esi, r8d\njle short loc_1471\nloc_143F:\nmov edx, [rdi+r8*4-4]\nmov rax, r8\nadd edx, [rdi+r9*4-8]\njmp short loc_1458\nloc_1450:\nadd rax, 1\ncmp esi, eax\njle short loc_1468\nloc_1458:\nmov ecx, edx\nadd ecx, [rdi+rax*4]\njnz short loc_1450\nmov eax, 1\nretn\nloc_1468:\nadd r8, 1\ncmp esi, r8d\njg short loc_143F\nloc_1471:\nadd r9, 1\njmp short loc_1432\nloc_1477:\nxor eax, eax\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 i; // r9\n __int64 j; // r8\n __int64 v4; // rax\n\n if ( a2 > 0 )\n {\n for ( i = 2LL; a2 + 1 != i; ++i )\n {\n for ( j = i; a2 > (int)j; ++j )\n {\n v4 = j;\n do\n {\n if ( !(*(_DWORD *)(a1 + 4 * v4) + *(_DWORD *)(a1 + 4 * i - 8) + *(_DWORD *)(a1 + 4 * j - 4)) )\n return 1LL;\n ++v4;\n }\n while ( a2 > (int)v4 );\n }\n }\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1420:\nendbr64\ntest esi, esi\njle short loc_1477\nlea r10d, [rsi+1]\nmov r9d, 2\nloc_1432:\ncmp r10, r9\njz short loc_1477\nmov r8, r9\ncmp esi, r8d\njle short loc_1471\nloc_143F:\nmov edx, [rdi+r8*4-4]\nmov rax, r8\nadd edx, [rdi+r9*4-8]\njmp short loc_1458\nloc_1450:\nadd rax, 1\ncmp esi, eax\njle short loc_1468\nloc_1458:\nmov ecx, edx\nadd ecx, [rdi+rax*4]\njnz short loc_1450\nmov eax, 1\nretn\nloc_1468:\nadd r8, 1\ncmp esi, r8d\njg short loc_143F\nloc_1471:\nadd r9, 1\njmp short loc_1432\nloc_1477:\nxor eax, eax\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1420(__int64 a1, int a2)\n{\n __int64 i; // r9\n __int64 j; // r8\n __int64 v4; // rax\n\n if ( a2 > 0 )\n {\n for ( i = 2LL; a2 + 1 != i; ++i )\n {\n for ( j = i; a2 > (int)j; ++j )\n {\n v4 = j;\n do\n {\n if ( !(*(_DWORD *)(a1 + 4 * v4) + *(_DWORD *)(a1 + 4 * i - 8) + *(_DWORD *)(a1 + 4 * j - 4)) )\n return 1LL;\n ++v4;\n }\n while ( a2 > (int)v4 );\n }\n }\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1420(long long a1, int a2) {\n long long i;\n long long j;\n long long v4;\n if (a2 > 0) {\n for (i = 2LL; a2 + 1 != i; ++i) {\n for (j = i; a2 > (int)j; ++j) {\n v4 = j;\n do {\n if (!(*(uint32_t *)(a1 + 4 * v4) + *(uint32_t *)(a1 + 4 * i - 8) +\n *(uint32_t *)(a1 + 4 * j - 4)))\n return 1LL;\n ++v4;\n } while (a2 > (int)v4);\n }\n }\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long i;\n long long j;\n long long v4;\n if (a2 > 0) {\n for (i = 2LL; a2 + 1 != i; ++i) {\n for (j = i; a2 > (int)j; ++j) {\n v4 = j;\n do {\n if (!(*(uint32_t *)(a1 + 4 * v4) + *(uint32_t *)(a1 + 4 * i - 8) +\n *(uint32_t *)(a1 + 4 * j - 4)))\n return 1LL;\n ++v4;\n } while (a2 > (int)v4);\n }\n }\n }\n return 0LL;\n}" + }, + { + "index": "HumanEval-C-40", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "bool func0(int *l, int size) {\n for (int i = 0; i < size; i++)\n for (int j = i + 1; j < size; j++)\n for (int k = j + 1; k < size; k++)\n if (l[i] + l[j] + l[k] == 0) return true;\n return false;\n}", + "test": "#include \n#include \n\nint main() {\n int test1[] = {1, 3, 5, 0};\n assert(func0(test1, 4) == false);\n \n int test2[] = {1, 3, 5, -1};\n assert(func0(test2, 4) == false);\n \n int test3[] = {1, 3, -2, 1};\n assert(func0(test3, 4) == true);\n \n int test4[] = {1, 2, 3, 7};\n assert(func0(test4, 4) == false);\n \n int test5[] = {1, 2, 5, 7};\n assert(func0(test5, 4) == false);\n \n int test6[] = {2, 4, -5, 3, 9, 7};\n assert(func0(test6, 6) == true);\n \n int test7[] = {1};\n assert(func0(test7, 1) == false);\n \n int test8[] = {1, 3, 5, -100};\n assert(func0(test8, 4) == false);\n \n int test9[] = {100, 3, 5, -100};\n assert(func0(test9, 4) == false);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1477\nlea r10d, [rsi+1]\nmov r9d, 2\nloc_1432:\ncmp r10, r9\njz short loc_1477\nmov r8, r9\ncmp esi, r8d\njle short loc_1471\nloc_143F:\nmov edx, [rdi+r8*4-4]\nmov rax, r8\nadd edx, [rdi+r9*4-8]\njmp short loc_1458\nloc_1450:\nadd rax, 1\ncmp esi, eax\njle short loc_1468\nloc_1458:\nmov ecx, edx\nadd ecx, [rdi+rax*4]\njnz short loc_1450\nmov eax, 1\nretn\nloc_1468:\nadd r8, 1\ncmp esi, r8d\njg short loc_143F\nloc_1471:\nadd r9, 1\njmp short loc_1432\nloc_1477:\nxor eax, eax\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 i; // r9\n __int64 j; // r8\n __int64 v4; // rax\n\n if ( a2 > 0 )\n {\n for ( i = 2LL; a2 + 1 != i; ++i )\n {\n for ( j = i; a2 > (int)j; ++j )\n {\n v4 = j;\n do\n {\n if ( !(*(_DWORD *)(a1 + 4 * v4) + *(_DWORD *)(a1 + 4 * i - 8) + *(_DWORD *)(a1 + 4 * j - 4)) )\n return 1LL;\n ++v4;\n }\n while ( a2 > (int)v4 );\n }\n }\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1420:\nendbr64\ntest esi, esi\njle short loc_1477\nlea r10d, [rsi+1]\nmov r9d, 2\nloc_1432:\ncmp r10, r9\njz short loc_1477\nmov r8, r9\ncmp esi, r8d\njle short loc_1471\nloc_143F:\nmov edx, [rdi+r8*4-4]\nmov rax, r8\nadd edx, [rdi+r9*4-8]\njmp short loc_1458\nloc_1450:\nadd rax, 1\ncmp esi, eax\njle short loc_1468\nloc_1458:\nmov ecx, edx\nadd ecx, [rdi+rax*4]\njnz short loc_1450\nmov eax, 1\nretn\nloc_1468:\nadd r8, 1\ncmp esi, r8d\njg short loc_143F\nloc_1471:\nadd r9, 1\njmp short loc_1432\nloc_1477:\nxor eax, eax\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1420(__int64 a1, int a2)\n{\n __int64 i; // r9\n __int64 j; // r8\n __int64 v4; // rax\n\n if ( a2 > 0 )\n {\n for ( i = 2LL; a2 + 1 != i; ++i )\n {\n for ( j = i; a2 > (int)j; ++j )\n {\n v4 = j;\n do\n {\n if ( !(*(_DWORD *)(a1 + 4 * v4) + *(_DWORD *)(a1 + 4 * i - 8) + *(_DWORD *)(a1 + 4 * j - 4)) )\n return 1LL;\n ++v4;\n }\n while ( a2 > (int)v4 );\n }\n }\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1420(long long a1, int a2) {\n long long i;\n long long j;\n long long v4;\n if (a2 > 0) {\n for (i = 2LL; a2 + 1 != i; ++i) {\n for (j = i; a2 > (int)j; ++j) {\n v4 = j;\n do {\n if (!(*(uint32_t *)(a1 + 4 * v4) + *(uint32_t *)(a1 + 4 * i - 8) +\n *(uint32_t *)(a1 + 4 * j - 4)))\n return 1LL;\n ++v4;\n } while (a2 > (int)v4);\n }\n }\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long i;\n long long j;\n long long v4;\n if (a2 > 0) {\n for (i = 2LL; a2 + 1 != i; ++i) {\n for (j = i; a2 > (int)j; ++j) {\n v4 = j;\n do {\n if (!(*(uint32_t *)(a1 + 4 * v4) + *(uint32_t *)(a1 + 4 * i - 8) +\n *(uint32_t *)(a1 + 4 * j - 4)))\n return 1LL;\n ++v4;\n } while (a2 > (int)v4);\n }\n }\n }\n return 0LL;\n}" + }, + { + "index": "HumanEval-C-41", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int n) { return n * n; }", + "test": "#include \n#include \n\nint main() {\n assert(func0(2) == 4);\n assert(func0(3) == 9);\n assert(func0(4) == 16);\n assert(func0(8) == 64);\n assert(func0(10) == 100);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov eax, [rbp+var_4]\nimul eax, eax\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n return (unsigned int)(a1 * a1);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov eax, [rbp+var_4]\nimul eax, eax\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n return (unsigned int)(a1 * a1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) { return (unsigned int)(a1 * a1); }", + "ida_pseudo_norm": "long long func0(int a1) { return (unsigned int)(a1 * a1); }" + }, + { + "index": "HumanEval-C-42", + "func_name": "func0", + "func_dep": "#include \n", + "func": "void func0(int *l, int size) {\n for (int i = 0; i < size; i++) l[i] += 1;\n}", + "test": "#include \n#include \n\nint issame(int *a, int size_a, int *b, int size_b) {\n if (size_a != size_b) return 0;\n for (int i = 0; i < size_a; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int list1[] = {};\n int result1[] = {};\n func0(list1, 0);\n assert(issame(list1, 0, result1, 0));\n\n int list2[] = {3, 2, 1};\n int result2[] = {4, 3, 2};\n func0(list2, 3);\n assert(issame(list2, 3, result2, 3));\n\n int list3[] = {5, 2, 5, 2, 3, 3, 9, 0, 123};\n int result3[] = {6, 3, 6, 3, 4, 4, 10, 1, 124};\n func0(list3, 9);\n assert(issame(list3, 9, result3, 9));\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 0\njmp short loc_11B4\nloc_1181:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nadd edx, 1\nmov [rax], edx\nadd [rbp+var_4], 1\nloc_11B4:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1181\nnop\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a2 )\n break;\n ++*(_DWORD *)(4LL * (int)i + a1);\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 0\njmp short loc_11B4\nloc_1181:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nadd edx, 1\nmov [rax], edx\nadd [rbp+var_4], 1\nloc_11B4:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1181\nnop\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a2 )\n break;\n ++*(_DWORD *)(4LL * (int)i + a1);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n long long result;\n unsigned int i;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a2) break;\n ++*(uint32_t *)(4LL * (int)i + a1);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long result;\n unsigned int i;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a2) break;\n ++*(uint32_t *)(4LL * (int)i + a1);\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-42", + "func_name": "func0", + "func_dep": "#include \n", + "func": "void func0(int *l, int size) {\n for (int i = 0; i < size; i++) l[i] += 1;\n}", + "test": "#include \n#include \n\nint issame(int *a, int size_a, int *b, int size_b) {\n if (size_a != size_b) return 0;\n for (int i = 0; i < size_a; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int list1[] = {};\n int result1[] = {};\n func0(list1, 0);\n assert(issame(list1, 0, result1, 0));\n\n int list2[] = {3, 2, 1};\n int result2[] = {4, 3, 2};\n func0(list2, 3);\n assert(issame(list2, 3, result2, 3));\n\n int list3[] = {5, 2, 5, 2, 3, 3, 9, 0, 123};\n int result3[] = {6, 3, 6, 3, 4, 4, 10, 1, 124};\n func0(list3, 9);\n assert(issame(list3, 9, result3, 9));\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short locret_1187\nmov rax, rdi\nmovsxd rsi, esi\nlea rdx, [rdi+rsi*4]\nloc_117B:\nadd dword ptr [rax], 1\nadd rax, 4\ncmp rax, rdx\njnz short loc_117B\nlocret_1187:\nretn", + "ida_pseudo": "void __fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n\n if ( a2 > 0 )\n {\n v2 = a1;\n do\n ++*v2++;\n while ( v2 != &a1[a2] );\n }\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short locret_1187\nmov rax, rdi\nmovsxd rsi, esi\nlea rdx, [rdi+rsi*4]\nloc_117B:\nadd dword ptr [rax], 1\nadd rax, 4\ncmp rax, rdx\njnz short loc_117B\nlocret_1187:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1169(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n\n if ( a2 > 0 )\n {\n v2 = a1;\n do\n ++*v2++;\n while ( v2 != &a1[a2] );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1169(uint32_t *a1, int a2) {\n uint32_t *v2;\n if (a2 > 0) {\n v2 = a1;\n do\n ++*v2++;\n while (v2 != &a1[a2]);\n }\n}", + "ida_pseudo_norm": "void func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n if (a2 > 0) {\n v2 = a1;\n do\n ++*v2++;\n while (v2 != &a1[a2]);\n }\n}" + }, + { + "index": "HumanEval-C-43", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "bool func0(int *l, int size) {\n for (int i = 0; i < size; i++)\n for (int j = i + 1; j < size; j++)\n if (l[i] + l[j] == 0) return true;\n return false;\n}", + "test": "#include \n#include \n\nint main() {\n int test1[] = {1, 3, 5, 0};\n assert(func0(test1, 4) == false);\n \n int test2[] = {1, 3, -2, 1};\n assert(func0(test2, 4) == false);\n \n int test3[] = {1, 2, 3, 7};\n assert(func0(test3, 4) == false);\n \n int test4[] = {2, 4, -5, 3, 5, 7};\n assert(func0(test4, 6) == true);\n \n int test5[] = {1};\n assert(func0(test5, 1) == false);\n \n int test6[] = {-3, 9, -1, 3, 2, 30};\n assert(func0(test6, 6) == true);\n \n int test7[] = {-3, 9, -1, 3, 2, 31};\n assert(func0(test7, 6) == true);\n \n int test8[] = {-3, 9, -1, 4, 2, 30};\n assert(func0(test8, 6) == false);\n \n int test9[] = {-3, 9, -1, 4, 2, 31};\n assert(func0(test9, 6) == false);\n \n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\njmp short loc_11D5\nloc_1181:\nmov eax, [rbp+var_8]\nadd eax, 1\nmov [rbp+var_4], eax\njmp short loc_11C9\nloc_118C:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nadd eax, edx\ntest eax, eax\njnz short loc_11C5\nmov eax, 1\njmp short loc_11E2\nloc_11C5:\nadd [rbp+var_4], 1\nloc_11C9:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_118C\nadd [rbp+var_8], 1\nloc_11D5:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_1181\nmov eax, 0\nloc_11E2:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+14h] [rbp-8h]\n int j; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( !(*(_DWORD *)(4LL * i + a1) + *(_DWORD *)(4LL * j + a1)) )\n return 1LL;\n }\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\njmp short loc_11D5\nloc_1181:\nmov eax, [rbp+var_8]\nadd eax, 1\nmov [rbp+var_4], eax\njmp short loc_11C9\nloc_118C:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nadd eax, edx\ntest eax, eax\njnz short loc_11C5\nmov eax, 1\njmp short loc_11E2\nloc_11C5:\nadd [rbp+var_4], 1\nloc_11C9:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_118C\nadd [rbp+var_8], 1\nloc_11D5:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_1181\nmov eax, 0\nloc_11E2:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int i; // [rsp+14h] [rbp-8h]\n int j; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( !(*(_DWORD *)(4LL * i + a1) + *(_DWORD *)(4LL * j + a1)) )\n return 1LL;\n }\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int i;\n int j;\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if (!(*(uint32_t *)(4LL * i + a1) + *(uint32_t *)(4LL * j + a1)))\n return 1LL;\n }\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int i;\n int j;\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if (!(*(uint32_t *)(4LL * i + a1) + *(uint32_t *)(4LL * j + a1)))\n return 1LL;\n }\n }\n return 0LL;\n}" + }, + { + "index": "HumanEval-C-43", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "bool func0(int *l, int size) {\n for (int i = 0; i < size; i++)\n for (int j = i + 1; j < size; j++)\n if (l[i] + l[j] == 0) return true;\n return false;\n}", + "test": "#include \n#include \n\nint main() {\n int test1[] = {1, 3, 5, 0};\n assert(func0(test1, 4) == false);\n \n int test2[] = {1, 3, -2, 1};\n assert(func0(test2, 4) == false);\n \n int test3[] = {1, 2, 3, 7};\n assert(func0(test3, 4) == false);\n \n int test4[] = {2, 4, -5, 3, 5, 7};\n assert(func0(test4, 6) == true);\n \n int test5[] = {1};\n assert(func0(test5, 1) == false);\n \n int test6[] = {-3, 9, -1, 3, 2, 30};\n assert(func0(test6, 6) == true);\n \n int test7[] = {-3, 9, -1, 3, 2, 31};\n assert(func0(test7, 6) == true);\n \n int test8[] = {-3, 9, -1, 4, 2, 30};\n assert(func0(test8, 6) == false);\n \n int test9[] = {-3, 9, -1, 4, 2, 31};\n assert(func0(test9, 6) == false);\n \n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11AD\nmov r9d, esi\nmovsxd r10, esi\nmov r8d, 1\nloc_117D:\ncmp r8, r9\njz short loc_11B3\nmov edx, [rdi+r8*4-4]\nmov rax, r8\nloc_118A:\nmov ecx, edx\nadd ecx, [rdi+rax*4]\njz short loc_11B9\nadd rax, 1\ncmp esi, eax\njg short loc_118A\nlea rax, [r8+1]\ncmp r8, r10\njz short loc_11A7\nmov r8, rax\njmp short loc_117D\nloc_11A7:\nmov eax, 0\nretn\nloc_11AD:\nmov eax, 0\nretn\nloc_11B3:\nmov eax, 0\nretn\nloc_11B9:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // r8\n __int64 v3; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 1LL;\n while ( 2 )\n {\n if ( v2 == a2 )\n return 0LL;\n v3 = v2;\n do\n {\n if ( !(*(_DWORD *)(a1 + 4 * v3) + *(_DWORD *)(a1 + 4 * v2 - 4)) )\n return 1LL;\n ++v3;\n }\n while ( a2 > (int)v3 );\n if ( v2 != a2 )\n {\n ++v2;\n continue;\n }\n break;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11AD\nmov r9d, esi\nmovsxd r10, esi\nmov r8d, 1\nloc_117D:\ncmp r8, r9\njz short loc_11B3\nmov edx, [rdi+r8*4-4]\nmov rax, r8\nloc_118A:\nmov ecx, edx\nadd ecx, [rdi+rax*4]\njz short loc_11B9\nadd rax, 1\ncmp esi, eax\njg short loc_118A\nlea rax, [r8+1]\ncmp r8, r10\njz short loc_11A7\nmov r8, rax\njmp short loc_117D\nloc_11A7:\nmov eax, 0\nretn\nloc_11AD:\nmov eax, 0\nretn\nloc_11B3:\nmov eax, 0\nretn\nloc_11B9:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n __int64 v2; // r8\n __int64 v3; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 1LL;\n while ( 2 )\n {\n if ( v2 == a2 )\n return 0LL;\n v3 = v2;\n do\n {\n if ( !(*(_DWORD *)(a1 + 4 * v3) + *(_DWORD *)(a1 + 4 * v2 - 4)) )\n return 1LL;\n ++v3;\n }\n while ( a2 > (int)v3 );\n if ( v2 != a2 )\n {\n ++v2;\n continue;\n }\n break;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n long long v2;\n long long v3;\n if (a2 <= 0) return 0LL;\n v2 = 1LL;\n while (2) {\n if (v2 == a2) return 0LL;\n v3 = v2;\n do {\n if (!(*(uint32_t *)(a1 + 4 * v3) + *(uint32_t *)(a1 + 4 * v2 - 4)))\n return 1LL;\n ++v3;\n } while (a2 > (int)v3);\n if (v2 != a2) {\n ++v2;\n continue;\n }\n break;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n long long v3;\n if (a2 <= 0) return 0LL;\n v2 = 1LL;\n while (2) {\n if (v2 == a2) return 0LL;\n v3 = v2;\n do {\n if (!(*(uint32_t *)(a1 + 4 * v3) + *(uint32_t *)(a1 + 4 * v2 - 4)))\n return 1LL;\n ++v3;\n } while (a2 > (int)v3);\n if (v2 != a2) {\n ++v2;\n continue;\n }\n break;\n }\n return 0LL;\n}" + }, + { + "index": "HumanEval-C-43", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "bool func0(int *l, int size) {\n for (int i = 0; i < size; i++)\n for (int j = i + 1; j < size; j++)\n if (l[i] + l[j] == 0) return true;\n return false;\n}", + "test": "#include \n#include \n\nint main() {\n int test1[] = {1, 3, 5, 0};\n assert(func0(test1, 4) == false);\n \n int test2[] = {1, 3, -2, 1};\n assert(func0(test2, 4) == false);\n \n int test3[] = {1, 2, 3, 7};\n assert(func0(test3, 4) == false);\n \n int test4[] = {2, 4, -5, 3, 5, 7};\n assert(func0(test4, 6) == true);\n \n int test5[] = {1};\n assert(func0(test5, 1) == false);\n \n int test6[] = {-3, 9, -1, 3, 2, 30};\n assert(func0(test6, 6) == true);\n \n int test7[] = {-3, 9, -1, 3, 2, 31};\n assert(func0(test7, 6) == true);\n \n int test8[] = {-3, 9, -1, 4, 2, 30};\n assert(func0(test8, 6) == false);\n \n int test9[] = {-3, 9, -1, 4, 2, 31};\n assert(func0(test9, 6) == false);\n \n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1481\nmov r9d, esi\nmov r8d, 1\ncmp r8, r9\njz short loc_1481\nloc_1456:\nmov edx, [rdi+r8*4-4]\nmov rax, r8\njmp short loc_1468\nloc_1460:\nadd rax, 1\ncmp esi, eax\njle short loc_1478\nloc_1468:\nmov ecx, edx\nadd ecx, [rdi+rax*4]\njnz short loc_1460\nmov eax, 1\nretn\nloc_1478:\nadd r8, 1\ncmp r8, r9\njnz short loc_1456\nloc_1481:\nxor eax, eax\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 i; // r8\n __int64 v3; // rax\n\n if ( a2 > 0 )\n {\n for ( i = 1LL; i != a2; ++i )\n {\n v3 = i;\n do\n {\n if ( !(*(_DWORD *)(a1 + 4 * v3) + *(_DWORD *)(a1 + 4 * i - 4)) )\n return 1LL;\n ++v3;\n }\n while ( a2 > (int)v3 );\n }\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1440:\nendbr64\ntest esi, esi\njle short loc_1481\nmov r9d, esi\nmov r8d, 1\ncmp r8, r9\njz short loc_1481\nloc_1456:\nmov edx, [rdi+r8*4-4]\nmov rax, r8\njmp short loc_1468\nloc_1460:\nadd rax, 1\ncmp esi, eax\njle short loc_1478\nloc_1468:\nmov ecx, edx\nadd ecx, [rdi+rax*4]\njnz short loc_1460\nmov eax, 1\nretn\nloc_1478:\nadd r8, 1\ncmp r8, r9\njnz short loc_1456\nloc_1481:\nxor eax, eax\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1440(__int64 a1, int a2)\n{\n __int64 i; // r8\n __int64 v3; // rax\n\n if ( a2 > 0 )\n {\n for ( i = 1LL; i != a2; ++i )\n {\n v3 = i;\n do\n {\n if ( !(*(_DWORD *)(a1 + 4 * v3) + *(_DWORD *)(a1 + 4 * i - 4)) )\n return 1LL;\n ++v3;\n }\n while ( a2 > (int)v3 );\n }\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1440(long long a1, int a2) {\n long long i;\n long long v3;\n if (a2 > 0) {\n for (i = 1LL; i != a2; ++i) {\n v3 = i;\n do {\n if (!(*(uint32_t *)(a1 + 4 * v3) + *(uint32_t *)(a1 + 4 * i - 4)))\n return 1LL;\n ++v3;\n } while (a2 > (int)v3);\n }\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long i;\n long long v3;\n if (a2 > 0) {\n for (i = 1LL; i != a2; ++i) {\n v3 = i;\n do {\n if (!(*(uint32_t *)(a1 + 4 * v3) + *(uint32_t *)(a1 + 4 * i - 4)))\n return 1LL;\n ++v3;\n } while (a2 > (int)v3);\n }\n }\n return 0LL;\n}" + }, + { + "index": "HumanEval-C-44", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "void func0(int x, int base, char *out) {\n int index = 0;\n char temp[33];\n while (x > 0) {\n temp[index++] = (x % base) + '0';\n x = x / base;\n }\n int j = 0;\n while (index > 0) {\n out[j++] = temp[--index];\n }\n out[j] = '\\0';\n}", + "test": "#include \n#include \n#include \n\nint main() {\n char buffer[33];\n \n func0(8, 3, buffer);\n assert(strcmp(buffer, \"22\") == 0);\n \n func0(9, 3, buffer);\n assert(strcmp(buffer, \"100\") == 0);\n \n func0(234, 2, buffer);\n assert(strcmp(buffer, \"11101010\") == 0);\n \n func0(16, 2, buffer);\n assert(strcmp(buffer, \"10000\") == 0);\n \n func0(8, 2, buffer);\n assert(strcmp(buffer, \"1000\") == 0);\n \n func0(7, 2, buffer);\n assert(strcmp(buffer, \"111\") == 0);\n \n for (int x = 2; x < 8; x++) {\n char expected[33];\n sprintf(expected, \"%d\", x);\n func0(x, x + 1, buffer);\n assert(strcmp(buffer, expected) == 0);\n }\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+var_44], edi\nmov [rbp+var_48], esi\nmov [rbp+var_50], rdx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_38], 0\njmp short loc_11FE\nloc_11D7:\nmov eax, [rbp+var_44]\ncdq\nidiv [rbp+var_48]\nmov eax, edx\nlea ecx, [rax+30h]\nmov eax, [rbp+var_38]\nlea edx, [rax+1]\nmov [rbp+var_38], edx\nmov edx, ecx\ncdqe\nmov [rbp+rax+var_30], dl\nmov eax, [rbp+var_44]\ncdq\nidiv [rbp+var_48]\nmov [rbp+var_44], eax\nloc_11FE:\ncmp [rbp+var_44], 0\njg short loc_11D7\nmov [rbp+var_34], 0\njmp short loc_1230\nloc_120D:\nsub [rbp+var_38], 1\nmov eax, [rbp+var_34]\nlea edx, [rax+1]\nmov [rbp+var_34], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_50]\nadd rdx, rax\nmov eax, [rbp+var_38]\ncdqe\nmovzx eax, [rbp+rax+var_30]\nmov [rdx], al\nloc_1230:\ncmp [rbp+var_38], 0\njg short loc_120D\nmov eax, [rbp+var_34]\nmovsxd rdx, eax\nmov rax, [rbp+var_50]\nadd rax, rdx\nmov byte ptr [rax], 0\nnop\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njz short locret_125B\ncall ___stack_chk_fail\nlocret_125B:\nleave\nretn", + "ida_pseudo": "unsigned __int64 __fastcall func0(int a1, int a2, __int64 a3)\n{\n int v3; // eax\n int v4; // eax\n int v7; // [rsp+18h] [rbp-38h]\n int v8; // [rsp+1Ch] [rbp-34h]\n _BYTE v9[40]; // [rsp+20h] [rbp-30h]\n unsigned __int64 v10; // [rsp+48h] [rbp-8h]\n\n v10 = __readfsqword(0x28u);\n v7 = 0;\n while ( a1 > 0 )\n {\n v3 = v7++;\n v9[v3] = a1 % a2 + 48;\n a1 /= a2;\n }\n v8 = 0;\n while ( v7 > 0 )\n {\n --v7;\n v4 = v8++;\n *(_BYTE *)(a3 + v4) = v9[v7];\n }\n *(_BYTE *)(v8 + a3) = 0;\n return v10 - __readfsqword(0x28u);\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+var_44], edi\nmov [rbp+var_48], esi\nmov [rbp+var_50], rdx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_38], 0\njmp short loc_11FE\nloc_11D7:\nmov eax, [rbp+var_44]\ncdq\nidiv [rbp+var_48]\nmov eax, edx\nlea ecx, [rax+30h]\nmov eax, [rbp+var_38]\nlea edx, [rax+1]\nmov [rbp+var_38], edx\nmov edx, ecx\ncdqe\nmov [rbp+rax+var_30], dl\nmov eax, [rbp+var_44]\ncdq\nidiv [rbp+var_48]\nmov [rbp+var_44], eax\nloc_11FE:\ncmp [rbp+var_44], 0\njg short loc_11D7\nmov [rbp+var_34], 0\njmp short loc_1230\nloc_120D:\nsub [rbp+var_38], 1\nmov eax, [rbp+var_34]\nlea edx, [rax+1]\nmov [rbp+var_34], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_50]\nadd rdx, rax\nmov eax, [rbp+var_38]\ncdqe\nmovzx eax, [rbp+rax+var_30]\nmov [rdx], al\nloc_1230:\ncmp [rbp+var_38], 0\njg short loc_120D\nmov eax, [rbp+var_34]\nmovsxd rdx, eax\nmov rax, [rbp+var_50]\nadd rax, rdx\nmov byte ptr [rax], 0\nnop\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njz short locret_125B\ncall ___stack_chk_fail\nlocret_125B:\nleave\nretn", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_11A9(int a1, int a2, __int64 a3)\n{\n int v3; // eax\n int v4; // eax\n int v7; // [rsp+18h] [rbp-38h]\n int v8; // [rsp+1Ch] [rbp-34h]\n _BYTE v9[40]; // [rsp+20h] [rbp-30h]\n unsigned __int64 v10; // [rsp+48h] [rbp-8h]\n\n v10 = __readfsqword(0x28u);\n v7 = 0;\n while ( a1 > 0 )\n {\n v3 = v7++;\n v9[v3] = a1 % a2 + 48;\n a1 /= a2;\n }\n v8 = 0;\n while ( v7 > 0 )\n {\n --v7;\n v4 = v8++;\n *(_BYTE *)(a3 + v4) = v9[v7];\n }\n *(_BYTE *)(v8 + a3) = 0;\n return v10 - __readfsqword(0x28u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_11A9(int a1, int a2, long long a3) {\n int v3;\n int v4;\n int v7;\n int v8;\n uint8_t v9[40];\n unsigned long long v10;\n v10 = __readfsqword(40u);\n v7 = 0;\n while (a1 > 0) {\n v3 = v7++;\n v9[v3] = a1 % a2 + 48;\n a1 /= a2;\n }\n v8 = 0;\n while (v7 > 0) {\n --v7;\n v4 = v8++;\n *(uint8_t *)(a3 + v4) = v9[v7];\n }\n *(uint8_t *)(v8 + a3) = 0;\n return v10 - __readfsqword(40u);\n}", + "ida_pseudo_norm": "unsigned long long func0(int a1, int a2, long long a3) {\n int v3;\n int v4;\n int v7;\n int v8;\n uint8_t v9[40];\n unsigned long long v10;\n v10 = __readfsqword(40u);\n v7 = 0;\n while (a1 > 0) {\n v3 = v7++;\n v9[v3] = a1 % a2 + 48;\n a1 /= a2;\n }\n v8 = 0;\n while (v7 > 0) {\n --v7;\n v4 = v8++;\n *(uint8_t *)(a3 + v4) = v9[v7];\n }\n *(uint8_t *)(v8 + a3) = 0;\n return v10 - __readfsqword(40u);\n}" + }, + { + "index": "HumanEval-C-44", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "void func0(int x, int base, char *out) {\n int index = 0;\n char temp[33];\n while (x > 0) {\n temp[index++] = (x % base) + '0';\n x = x / base;\n }\n int j = 0;\n while (index > 0) {\n out[j++] = temp[--index];\n }\n out[j] = '\\0';\n}", + "test": "#include \n#include \n#include \n\nint main() {\n char buffer[33];\n \n func0(8, 3, buffer);\n assert(strcmp(buffer, \"22\") == 0);\n \n func0(9, 3, buffer);\n assert(strcmp(buffer, \"100\") == 0);\n \n func0(234, 2, buffer);\n assert(strcmp(buffer, \"11101010\") == 0);\n \n func0(16, 2, buffer);\n assert(strcmp(buffer, \"10000\") == 0);\n \n func0(8, 2, buffer);\n assert(strcmp(buffer, \"1000\") == 0);\n \n func0(7, 2, buffer);\n assert(strcmp(buffer, \"111\") == 0);\n \n for (int x = 2; x < 8; x++) {\n char expected[33];\n sprintf(expected, \"%d\", x);\n func0(x, x + 1, buffer);\n assert(strcmp(buffer, expected) == 0);\n }\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nsub rsp, 38h\nmov r10, rdx\nmov rax, fs:28h\nmov [rsp+38h+var_10], rax\nxor eax, eax\ntest edi, edi\njle short loc_1236\nmov ecx, 1\nlea r9, [rsp+38h+var_39]\nloc_11D2:\nmov eax, edi\ncdq\nidiv esi\nadd edx, 30h ; '0'\nmov [r9+rcx], dl\nmov edi, eax\nmov r8, rcx\nadd rcx, 1\ntest eax, eax\njg short loc_11D2\nmov edi, r8d\ntest r8d, r8d\njle short loc_123D\nmovsxd rax, r8d\nlea rdx, [rsp+rax+38h+var_39]\nmov rax, r10\nlea ecx, [r8-1]\nlea rsi, [r10+rcx+1]\nloc_1207:\nmovzx ecx, byte ptr [rdx]\nmov [rax], cl\nsub rdx, 1\nadd rax, 1\ncmp rax, rsi\njnz short loc_1207\nloc_1219:\nmovsxd rax, edi\nmov byte ptr [r10+rax], 0\nmov rax, [rsp+38h+var_10]\nsub rax, fs:28h\njnz short loc_1244\nadd rsp, 38h\nretn\nloc_1236:\nmov edi, 0\njmp short loc_1219\nloc_123D:\nmov edi, 0\njmp short loc_1219\nloc_1244:\ncall ___stack_chk_fail", + "ida_pseudo": "unsigned __int64 __fastcall func0(int a1, int a2, _BYTE *a3)\n{\n __int64 v4; // rcx\n int v5; // r8d\n int v6; // edi\n _BYTE *v7; // rdx\n _BYTE *v8; // rax\n _BYTE v10[41]; // [rsp+1h] [rbp-39h] BYREF\n unsigned __int64 v11; // [rsp+2Ah] [rbp-10h]\n\n v11 = __readfsqword(0x28u);\n if ( a1 <= 0 )\n {\n v6 = 0;\n }\n else\n {\n v4 = 1LL;\n do\n {\n v10[v4] = a1 % a2 + 48;\n a1 /= a2;\n v5 = v4++;\n }\n while ( a1 > 0 );\n v6 = v5;\n if ( v5 <= 0 )\n {\n v6 = 0;\n }\n else\n {\n v7 = &v10[v5];\n v8 = a3;\n do\n *v8++ = *v7--;\n while ( v8 != &a3[v5 - 1 + 1] );\n }\n }\n a3[v6] = 0;\n return v11 - __readfsqword(0x28u);\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\nsub rsp, 38h\nmov r10, rdx\nmov rax, fs:28h\nmov [rsp+38h+var_10], rax\nxor eax, eax\ntest edi, edi\njle short loc_1236\nmov ecx, 1\nlea r9, [rsp+38h+var_39]\nloc_11D2:\nmov eax, edi\ncdq\nidiv esi\nadd edx, 30h ; '0'\nmov [r9+rcx], dl\nmov edi, eax\nmov r8, rcx\nadd rcx, 1\ntest eax, eax\njg short loc_11D2\nmov edi, r8d\ntest r8d, r8d\njle short loc_123D\nmovsxd rax, r8d\nlea rdx, [rsp+rax+38h+var_39]\nmov rax, r10\nlea ecx, [r8-1]\nlea rsi, [r10+rcx+1]\nloc_1207:\nmovzx ecx, byte ptr [rdx]\nmov [rax], cl\nsub rdx, 1\nadd rax, 1\ncmp rax, rsi\njnz short loc_1207\nloc_1219:\nmovsxd rax, edi\nmov byte ptr [r10+rax], 0\nmov rax, [rsp+38h+var_10]\nsub rax, fs:28h\njnz short loc_1244\nadd rsp, 38h\nretn\nloc_1236:\nmov edi, 0\njmp short loc_1219\nloc_123D:\nmov edi, 0\njmp short loc_1219\nloc_1244:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_11A9(int a1, int a2, _BYTE *a3)\n{\n __int64 v4; // rcx\n int v5; // r8d\n int v6; // edi\n _BYTE *v7; // rdx\n _BYTE *v8; // rax\n _BYTE v10[41]; // [rsp+1h] [rbp-39h] BYREF\n unsigned __int64 v11; // [rsp+2Ah] [rbp-10h]\n\n v11 = __readfsqword(0x28u);\n if ( a1 <= 0 )\n {\n v6 = 0;\n }\n else\n {\n v4 = 1LL;\n do\n {\n v10[v4] = a1 % a2 + 48;\n a1 /= a2;\n v5 = v4++;\n }\n while ( a1 > 0 );\n v6 = v5;\n if ( v5 <= 0 )\n {\n v6 = 0;\n }\n else\n {\n v7 = &v10[v5];\n v8 = a3;\n do\n *v8++ = *v7--;\n while ( v8 != &a3[v5 - 1 + 1] );\n }\n }\n a3[v6] = 0;\n return v11 - __readfsqword(0x28u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_11A9(int a1, int a2, uint8_t *a3) {\n long long v4;\n int v5;\n int v6;\n uint8_t *v7;\n uint8_t *v8;\n uint8_t v10[41];\n unsigned long long v11;\n v11 = __readfsqword(40u);\n if (a1 <= 0) {\n v6 = 0;\n } else {\n v4 = 1LL;\n do {\n v10[v4] = a1 % a2 + 48;\n a1 /= a2;\n v5 = v4++;\n } while (a1 > 0);\n v6 = v5;\n if (v5 <= 0) {\n v6 = 0;\n } else {\n v7 = &v10[v5];\n v8 = a3;\n do\n *v8++ = *v7--;\n while (v8 != &a3[v5 - 1 + 1]);\n }\n }\n a3[v6] = 0;\n return v11 - __readfsqword(40u);\n}", + "ida_pseudo_norm": "unsigned long long func0(int a1, int a2, uint8_t *a3) {\n long long v4;\n int v5;\n int v6;\n uint8_t *v7;\n uint8_t *v8;\n uint8_t v10[41];\n unsigned long long v11;\n v11 = __readfsqword(40u);\n if (a1 <= 0) {\n v6 = 0;\n } else {\n v4 = 1LL;\n do {\n v10[v4] = a1 % a2 + 48;\n a1 /= a2;\n v5 = v4++;\n } while (a1 > 0);\n v6 = v5;\n if (v5 <= 0) {\n v6 = 0;\n } else {\n v7 = &v10[v5];\n v8 = a3;\n do\n *v8++ = *v7--;\n while (v8 != &a3[v5 - 1 + 1]);\n }\n }\n a3[v6] = 0;\n return v11 - __readfsqword(40u);\n}" + }, + { + "index": "HumanEval-C-44", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "void func0(int x, int base, char *out) {\n int index = 0;\n char temp[33];\n while (x > 0) {\n temp[index++] = (x % base) + '0';\n x = x / base;\n }\n int j = 0;\n while (index > 0) {\n out[j++] = temp[--index];\n }\n out[j] = '\\0';\n}", + "test": "#include \n#include \n#include \n\nint main() {\n char buffer[33];\n \n func0(8, 3, buffer);\n assert(strcmp(buffer, \"22\") == 0);\n \n func0(9, 3, buffer);\n assert(strcmp(buffer, \"100\") == 0);\n \n func0(234, 2, buffer);\n assert(strcmp(buffer, \"11101010\") == 0);\n \n func0(16, 2, buffer);\n assert(strcmp(buffer, \"10000\") == 0);\n \n func0(8, 2, buffer);\n assert(strcmp(buffer, \"1000\") == 0);\n \n func0(7, 2, buffer);\n assert(strcmp(buffer, \"111\") == 0);\n \n for (int x = 2; x < 8; x++) {\n char expected[33];\n sprintf(expected, \"%d\", x);\n func0(x, x + 1, buffer);\n assert(strcmp(buffer, expected) == 0);\n }\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nsub rsp, 38h\nmov r9, rdx\nmov rdx, fs:28h\nmov [rsp+38h+var_10], rdx\nxor edx, edx\ntest edi, edi\njle short loc_14C6\nmov eax, edi\nmov ecx, 1\nlea r8, [rsp+38h+var_39]\nnop dword ptr [rax+rax+00h]\nloc_1480:\ncdq\nmov rdi, rcx\nidiv esi\nadd edx, 30h ; '0'\nmov [r8+rcx], dl\nadd rcx, 1\ntest eax, eax\njg short loc_1480\nmov rax, rsp\nmovsxd r8, edi\nlea ecx, [rdi-1]\nlea rdx, [rax+r8-1]\nlea rsi, [r9+rcx+1]\nmov rax, r9\nnop dword ptr [rax+rax+00h]\nloc_14B0:\nmovzx ecx, byte ptr [rdx]\nadd rax, 1\nsub rdx, 1\nmov [rax-1], cl\ncmp rax, rsi\njnz short loc_14B0\nadd r9, r8\nloc_14C6:\nmov byte ptr [r9], 0\nmov rax, [rsp+38h+var_10]\nsub rax, fs:28h\njnz short loc_14DF\nadd rsp, 38h\nretn\nloc_14DF:\ncall ___stack_chk_fail", + "ida_pseudo": "unsigned __int64 __fastcall func0(int a1, int a2, _BYTE *a3)\n{\n int v4; // eax\n __int64 v5; // rcx\n int v6; // edi\n int v7; // et2\n char *v8; // rdx\n _BYTE *v9; // rax\n char v10; // cl\n _BYTE v12[41]; // [rsp+1h] [rbp-39h] BYREF\n unsigned __int64 v13; // [rsp+2Ah] [rbp-10h]\n\n v13 = __readfsqword(0x28u);\n if ( a1 > 0 )\n {\n v4 = a1;\n v5 = 1LL;\n do\n {\n v6 = v5;\n v7 = v4 % a2;\n v4 /= a2;\n v12[v5++] = v7 + 48;\n }\n while ( v4 > 0 );\n v8 = &v12[v6];\n v9 = a3;\n do\n {\n v10 = *v8;\n ++v9;\n --v8;\n *(v9 - 1) = v10;\n }\n while ( v9 != &a3[v6 - 1 + 1] );\n a3 += v6;\n }\n *a3 = 0;\n return v13 - __readfsqword(0x28u);\n}", + "ida_strip_asm": "sub_1450:\nendbr64\nsub rsp, 38h\nmov r9, rdx\nmov rdx, fs:28h\nmov [rsp+38h+var_10], rdx\nxor edx, edx\ntest edi, edi\njle short loc_14C6\nmov eax, edi\nmov ecx, 1\nlea r8, [rsp+38h+var_39]\nnop dword ptr [rax+rax+00h]\nloc_1480:\ncdq\nmov rdi, rcx\nidiv esi\nadd edx, 30h ; '0'\nmov [r8+rcx], dl\nadd rcx, 1\ntest eax, eax\njg short loc_1480\nmov rax, rsp\nmovsxd r8, edi\nlea ecx, [rdi-1]\nlea rdx, [rax+r8-1]\nlea rsi, [r9+rcx+1]\nmov rax, r9\nnop dword ptr [rax+rax+00h]\nloc_14B0:\nmovzx ecx, byte ptr [rdx]\nadd rax, 1\nsub rdx, 1\nmov [rax-1], cl\ncmp rax, rsi\njnz short loc_14B0\nadd r9, r8\nloc_14C6:\nmov byte ptr [r9], 0\nmov rax, [rsp+38h+var_10]\nsub rax, fs:28h\njnz short loc_14DF\nadd rsp, 38h\nretn\nloc_14DF:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_1450(int a1, int a2, _BYTE *a3)\n{\n int v4; // eax\n __int64 v5; // rcx\n int v6; // edi\n int v7; // et2\n char *v8; // rdx\n _BYTE *v9; // rax\n char v10; // cl\n _BYTE v12[41]; // [rsp+1h] [rbp-39h] BYREF\n unsigned __int64 v13; // [rsp+2Ah] [rbp-10h]\n\n v13 = __readfsqword(0x28u);\n if ( a1 > 0 )\n {\n v4 = a1;\n v5 = 1LL;\n do\n {\n v6 = v5;\n v7 = v4 % a2;\n v4 /= a2;\n v12[v5++] = v7 + 48;\n }\n while ( v4 > 0 );\n v8 = &v12[v6];\n v9 = a3;\n do\n {\n v10 = *v8;\n ++v9;\n --v8;\n *(v9 - 1) = v10;\n }\n while ( v9 != &a3[v6 - 1 + 1] );\n a3 += v6;\n }\n *a3 = 0;\n return v13 - __readfsqword(0x28u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_1450(int a1, int a2, uint8_t *a3) {\n int v4;\n long long v5;\n int v6;\n int v7;\n char *v8;\n uint8_t *v9;\n char v10;\n uint8_t v12[41];\n unsigned long long v13;\n v13 = __readfsqword(40u);\n if (a1 > 0) {\n v4 = a1;\n v5 = 1LL;\n do {\n v6 = v5;\n v7 = v4 % a2;\n v4 /= a2;\n v12[v5++] = v7 + 48;\n } while (v4 > 0);\n v8 = &v12[v6];\n v9 = a3;\n do {\n v10 = *v8;\n ++v9;\n --v8;\n *(v9 - 1) = v10;\n } while (v9 != &a3[v6 - 1 + 1]);\n a3 += v6;\n }\n *a3 = 0;\n return v13 - __readfsqword(40u);\n}", + "ida_pseudo_norm": "unsigned long long func0(int a1, int a2, uint8_t *a3) {\n int v4;\n long long v5;\n int v6;\n int v7;\n char *v8;\n uint8_t *v9;\n char v10;\n uint8_t v12[41];\n unsigned long long v13;\n v13 = __readfsqword(40u);\n if (a1 > 0) {\n v4 = a1;\n v5 = 1LL;\n do {\n v6 = v5;\n v7 = v4 % a2;\n v4 /= a2;\n v12[v5++] = v7 + 48;\n } while (v4 > 0);\n v8 = &v12[v6];\n v9 = a3;\n do {\n v10 = *v8;\n ++v9;\n --v8;\n *(v9 - 1) = v10;\n } while (v9 != &a3[v6 - 1 + 1]);\n a3 += v6;\n }\n *a3 = 0;\n return v13 - __readfsqword(40u);\n}" + }, + { + "index": "HumanEval-C-44", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "void func0(int x, int base, char *out) {\n int index = 0;\n char temp[33];\n while (x > 0) {\n temp[index++] = (x % base) + '0';\n x = x / base;\n }\n int j = 0;\n while (index > 0) {\n out[j++] = temp[--index];\n }\n out[j] = '\\0';\n}", + "test": "#include \n#include \n#include \n\nint main() {\n char buffer[33];\n \n func0(8, 3, buffer);\n assert(strcmp(buffer, \"22\") == 0);\n \n func0(9, 3, buffer);\n assert(strcmp(buffer, \"100\") == 0);\n \n func0(234, 2, buffer);\n assert(strcmp(buffer, \"11101010\") == 0);\n \n func0(16, 2, buffer);\n assert(strcmp(buffer, \"10000\") == 0);\n \n func0(8, 2, buffer);\n assert(strcmp(buffer, \"1000\") == 0);\n \n func0(7, 2, buffer);\n assert(strcmp(buffer, \"111\") == 0);\n \n for (int x = 2; x < 8; x++) {\n char expected[33];\n sprintf(expected, \"%d\", x);\n func0(x, x + 1, buffer);\n assert(strcmp(buffer, expected) == 0);\n }\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nsub rsp, 38h\nmov r9, rdx\nmov rdx, fs:28h\nmov [rsp+38h+var_10], rdx\nxor edx, edx\ntest edi, edi\njle short loc_1456\nmov eax, edi\nmov ecx, 1\nlea r8, [rsp+38h+var_39]\nnop dword ptr [rax+rax+00h]\nloc_1410:\ncdq\nmov rdi, rcx\nidiv esi\nadd edx, 30h ; '0'\nmov [r8+rcx], dl\nadd rcx, 1\ntest eax, eax\njg short loc_1410\nmov rax, rsp\nmovsxd r8, edi\nlea ecx, [rdi-1]\nlea rdx, [rax+r8-1]\nlea rsi, [r9+rcx+1]\nmov rax, r9\nnop dword ptr [rax+rax+00h]\nloc_1440:\nmovzx ecx, byte ptr [rdx]\nadd rax, 1\nsub rdx, 1\nmov [rax-1], cl\ncmp rax, rsi\njnz short loc_1440\nadd r9, r8\nloc_1456:\nmov byte ptr [r9], 0\nmov rax, [rsp+38h+var_10]\nsub rax, fs:28h\njnz short loc_146F\nadd rsp, 38h\nretn\nloc_146F:\ncall ___stack_chk_fail", + "ida_pseudo": "unsigned __int64 __fastcall func0(int a1, int a2, _BYTE *a3)\n{\n int v4; // eax\n __int64 v5; // rcx\n int v6; // edi\n int v7; // et2\n char *v8; // rdx\n _BYTE *v9; // rax\n char v10; // cl\n _BYTE v12[41]; // [rsp+1h] [rbp-39h] BYREF\n unsigned __int64 v13; // [rsp+2Ah] [rbp-10h]\n\n v13 = __readfsqword(0x28u);\n if ( a1 > 0 )\n {\n v4 = a1;\n v5 = 1LL;\n do\n {\n v6 = v5;\n v7 = v4 % a2;\n v4 /= a2;\n v12[v5++] = v7 + 48;\n }\n while ( v4 > 0 );\n v8 = &v12[v6];\n v9 = a3;\n do\n {\n v10 = *v8;\n ++v9;\n --v8;\n *(v9 - 1) = v10;\n }\n while ( v9 != &a3[v6 - 1 + 1] );\n a3 += v6;\n }\n *a3 = 0;\n return v13 - __readfsqword(0x28u);\n}", + "ida_strip_asm": "sub_13E0:\nendbr64\nsub rsp, 38h\nmov r9, rdx\nmov rdx, fs:28h\nmov [rsp+38h+var_10], rdx\nxor edx, edx\ntest edi, edi\njle short loc_1456\nmov eax, edi\nmov ecx, 1\nlea r8, [rsp+38h+var_39]\nnop dword ptr [rax+rax+00h]\nloc_1410:\ncdq\nmov rdi, rcx\nidiv esi\nadd edx, 30h ; '0'\nmov [r8+rcx], dl\nadd rcx, 1\ntest eax, eax\njg short loc_1410\nmov rax, rsp\nmovsxd r8, edi\nlea ecx, [rdi-1]\nlea rdx, [rax+r8-1]\nlea rsi, [r9+rcx+1]\nmov rax, r9\nnop dword ptr [rax+rax+00h]\nloc_1440:\nmovzx ecx, byte ptr [rdx]\nadd rax, 1\nsub rdx, 1\nmov [rax-1], cl\ncmp rax, rsi\njnz short loc_1440\nadd r9, r8\nloc_1456:\nmov byte ptr [r9], 0\nmov rax, [rsp+38h+var_10]\nsub rax, fs:28h\njnz short loc_146F\nadd rsp, 38h\nretn\nloc_146F:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_13E0(int a1, int a2, _BYTE *a3)\n{\n int v4; // eax\n __int64 v5; // rcx\n int v6; // edi\n int v7; // et2\n char *v8; // rdx\n _BYTE *v9; // rax\n char v10; // cl\n _BYTE v12[41]; // [rsp+1h] [rbp-39h] BYREF\n unsigned __int64 v13; // [rsp+2Ah] [rbp-10h]\n\n v13 = __readfsqword(0x28u);\n if ( a1 > 0 )\n {\n v4 = a1;\n v5 = 1LL;\n do\n {\n v6 = v5;\n v7 = v4 % a2;\n v4 /= a2;\n v12[v5++] = v7 + 48;\n }\n while ( v4 > 0 );\n v8 = &v12[v6];\n v9 = a3;\n do\n {\n v10 = *v8;\n ++v9;\n --v8;\n *(v9 - 1) = v10;\n }\n while ( v9 != &a3[v6 - 1 + 1] );\n a3 += v6;\n }\n *a3 = 0;\n return v13 - __readfsqword(0x28u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_13E0(int a1, int a2, uint8_t *a3) {\n int v4;\n long long v5;\n int v6;\n int v7;\n char *v8;\n uint8_t *v9;\n char v10;\n uint8_t v12[41];\n unsigned long long v13;\n v13 = __readfsqword(40u);\n if (a1 > 0) {\n v4 = a1;\n v5 = 1LL;\n do {\n v6 = v5;\n v7 = v4 % a2;\n v4 /= a2;\n v12[v5++] = v7 + 48;\n } while (v4 > 0);\n v8 = &v12[v6];\n v9 = a3;\n do {\n v10 = *v8;\n ++v9;\n --v8;\n *(v9 - 1) = v10;\n } while (v9 != &a3[v6 - 1 + 1]);\n a3 += v6;\n }\n *a3 = 0;\n return v13 - __readfsqword(40u);\n}", + "ida_pseudo_norm": "unsigned long long func0(int a1, int a2, uint8_t *a3) {\n int v4;\n long long v5;\n int v6;\n int v7;\n char *v8;\n uint8_t *v9;\n char v10;\n uint8_t v12[41];\n unsigned long long v13;\n v13 = __readfsqword(40u);\n if (a1 > 0) {\n v4 = a1;\n v5 = 1LL;\n do {\n v6 = v5;\n v7 = v4 % a2;\n v4 /= a2;\n v12[v5++] = v7 + 48;\n } while (v4 > 0);\n v8 = &v12[v6];\n v9 = a3;\n do {\n v10 = *v8;\n ++v9;\n --v8;\n *(v9 - 1) = v10;\n } while (v9 != &a3[v6 - 1 + 1]);\n a3 += v6;\n }\n *a3 = 0;\n return v13 - __readfsqword(40u);\n}" + }, + { + "index": "HumanEval-C-45", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "float func0(float a, float h) { return (a * h) * 0.5; }", + "test": "#include \n#include \n#include \n\nint main() {\n assert(fabs(func0(5, 3) - 7.5) < 1e-4);\n assert(fabs(func0(2, 2) - 2.0) < 1e-4);\n assert(fabs(func0(10, 8) - 40.0) < 1e-4);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmovss [rbp+var_4], xmm0\nmovss [rbp+var_8], xmm1\nmovss xmm0, [rbp+var_4]\nmovaps xmm1, xmm0\nmulss xmm1, [rbp+var_8]\nmovss xmm0, cs:dword_2098\nmulss xmm0, xmm1\npop rbp\nretn", + "ida_pseudo": "float __fastcall func0(float a1, float a2)\n{\n return 0.5 * (float)(a1 * a2);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmovss [rbp+var_4], xmm0\nmovss [rbp+var_8], xmm1\nmovss xmm0, [rbp+var_4]\nmovaps xmm1, xmm0\nmulss xmm1, [rbp+var_8]\nmovss xmm0, cs:dword_2098\nmulss xmm0, xmm1\npop rbp\nretn", + "ida_strip_pseudo": "float __fastcall sub_1149(float a1, float a2)\n{\n return 0.5 * (float)(a1 * a2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "float sub_1149(float a1, float a2) { return 0.5 * (float)(a1 * a2); }", + "ida_pseudo_norm": "float func0(float a1, float a2) { return 0.5 * (float)(a1 * a2); }" + }, + { + "index": "HumanEval-C-46", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int n) {\n int f[100];\n f[0] = 0;\n f[1] = 0;\n f[2] = 2;\n f[3] = 0;\n for (int i = 4; i <= n; i++) {\n f[i] = f[i - 1] + f[i - 2] + f[i - 3] + f[i - 4];\n }\n return f[n];\n}", + "test": "#include \n#include \n\nint main() {\n assert(func0(5) == 4);\n assert(func0(8) == 28);\n assert(func0(10) == 104);\n assert(func0(12) == 386);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 1C0h\nmov [rbp+var_1B4], edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_1A0], 0\nmov [rbp+var_19C], 0\nmov [rbp+var_198], 2\nmov [rbp+var_194], 0\nmov [rbp+var_1A4], 4\njmp short loc_1225\nloc_11C1:\nmov eax, [rbp+var_1A4]\nsub eax, 1\ncdqe\nmov edx, [rbp+rax*4+var_1A0]\nmov eax, [rbp+var_1A4]\nsub eax, 2\ncdqe\nmov eax, [rbp+rax*4+var_1A0]\nadd edx, eax\nmov eax, [rbp+var_1A4]\nsub eax, 3\ncdqe\nmov eax, [rbp+rax*4+var_1A0]\nadd edx, eax\nmov eax, [rbp+var_1A4]\nsub eax, 4\ncdqe\nmov eax, [rbp+rax*4+var_1A0]\nadd edx, eax\nmov eax, [rbp+var_1A4]\ncdqe\nmov [rbp+rax*4+var_1A0], edx\nadd [rbp+var_1A4], 1\nloc_1225:\nmov eax, [rbp+var_1A4]\ncmp eax, [rbp+var_1B4]\njle short loc_11C1\nmov eax, [rbp+var_1B4]\ncdqe\nmov eax, [rbp+rax*4+var_1A0]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1256\ncall ___stack_chk_fail\nlocret_1256:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int i; // [rsp+1Ch] [rbp-1A4h]\n _DWORD v3[102]; // [rsp+20h] [rbp-1A0h]\n unsigned __int64 v4; // [rsp+1B8h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n v3[0] = 0;\n v3[1] = 0;\n v3[2] = 2;\n v3[3] = 0;\n for ( i = 4; i <= a1; ++i )\n v3[i] = v3[i - 4] + v3[i - 3] + v3[i - 2] + v3[i - 1];\n return (unsigned int)v3[a1];\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 1C0h\nmov [rbp+var_1B4], edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_1A0], 0\nmov [rbp+var_19C], 0\nmov [rbp+var_198], 2\nmov [rbp+var_194], 0\nmov [rbp+var_1A4], 4\njmp short loc_1225\nloc_11C1:\nmov eax, [rbp+var_1A4]\nsub eax, 1\ncdqe\nmov edx, [rbp+rax*4+var_1A0]\nmov eax, [rbp+var_1A4]\nsub eax, 2\ncdqe\nmov eax, [rbp+rax*4+var_1A0]\nadd edx, eax\nmov eax, [rbp+var_1A4]\nsub eax, 3\ncdqe\nmov eax, [rbp+rax*4+var_1A0]\nadd edx, eax\nmov eax, [rbp+var_1A4]\nsub eax, 4\ncdqe\nmov eax, [rbp+rax*4+var_1A0]\nadd edx, eax\nmov eax, [rbp+var_1A4]\ncdqe\nmov [rbp+rax*4+var_1A0], edx\nadd [rbp+var_1A4], 1\nloc_1225:\nmov eax, [rbp+var_1A4]\ncmp eax, [rbp+var_1B4]\njle short loc_11C1\nmov eax, [rbp+var_1B4]\ncdqe\nmov eax, [rbp+rax*4+var_1A0]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1256\ncall ___stack_chk_fail\nlocret_1256:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n int i; // [rsp+1Ch] [rbp-1A4h]\n _DWORD v3[102]; // [rsp+20h] [rbp-1A0h]\n unsigned __int64 v4; // [rsp+1B8h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n v3[0] = 0;\n v3[1] = 0;\n v3[2] = 2;\n v3[3] = 0;\n for ( i = 4; i <= a1; ++i )\n v3[i] = v3[i - 4] + v3[i - 3] + v3[i - 2] + v3[i - 1];\n return (unsigned int)v3[a1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n int i;\n uint32_t v3[102];\n unsigned long long v4;\n v4 = __readfsqword(40u);\n v3[0] = 0;\n v3[1] = 0;\n v3[2] = 2;\n v3[3] = 0;\n for (i = 4; i <= a1; ++i)\n v3[i] = v3[i - 4] + v3[i - 3] + v3[i - 2] + v3[i - 1];\n return (unsigned int)v3[a1];\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int i;\n uint32_t v3[102];\n unsigned long long v4;\n v4 = __readfsqword(40u);\n v3[0] = 0;\n v3[1] = 0;\n v3[2] = 2;\n v3[3] = 0;\n for (i = 4; i <= a1; ++i)\n v3[i] = v3[i - 4] + v3[i - 3] + v3[i - 2] + v3[i - 1];\n return (unsigned int)v3[a1];\n}" + }, + { + "index": "HumanEval-C-46", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int n) {\n int f[100];\n f[0] = 0;\n f[1] = 0;\n f[2] = 2;\n f[3] = 0;\n for (int i = 4; i <= n; i++) {\n f[i] = f[i - 1] + f[i - 2] + f[i - 3] + f[i - 4];\n }\n return f[n];\n}", + "test": "#include \n#include \n\nint main() {\n assert(func0(5) == 4);\n assert(func0(8) == 28);\n assert(func0(10) == 104);\n assert(func0(12) == 386);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nsub rsp, 1A8h\nmov rax, fs:28h\nmov [rsp+1A8h+var_10], rax\nxor eax, eax\nmov [rsp+1A8h+var_1A8], 0\nmov [rsp+1A8h+var_1A4], 0\nmov [rsp+1A8h+var_1A0], 2\nmov [rsp+1A8h+var_19C], 0\ncmp edi, 3\njle short loc_11CD\nmov rax, rsp\nlea edx, [rdi-4]\nlea rcx, [rsp+rdx*4+1A8h+var_1A4]\nloc_11B6:\nmov edx, [rax+8]\nadd edx, [rax+0Ch]\nadd edx, [rax+4]\nadd edx, [rax]\nmov [rax+10h], edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_11B6\nloc_11CD:\nmovsxd rdi, edi\nmov eax, [rsp+rdi*4+1A8h+var_1A8]\nmov rdx, [rsp+1A8h+var_10]\nsub rdx, fs:28h\njnz short loc_11EE\nadd rsp, 1A8h\nretn\nloc_11EE:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int *v1; // rax\n int v3; // [rsp+0h] [rbp-1A8h] BYREF\n _DWORD v4[101]; // [rsp+4h] [rbp-1A4h] BYREF\n unsigned __int64 v5; // [rsp+198h] [rbp-10h]\n\n v5 = __readfsqword(0x28u);\n v3 = 0;\n v4[0] = 0;\n v4[1] = 2;\n v4[2] = 0;\n if ( a1 > 3 )\n {\n v1 = &v3;\n do\n {\n v1[4] = *v1 + v1[1] + v1[3] + v1[2];\n ++v1;\n }\n while ( v1 != &v4[a1 - 4] );\n }\n return (unsigned int)v4[a1 - 1];\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nsub rsp, 1A8h\nmov rax, fs:28h\nmov [rsp+1A8h+var_10], rax\nxor eax, eax\nmov [rsp+1A8h+var_1A8], 0\nmov [rsp+1A8h+var_1A4], 0\nmov [rsp+1A8h+var_1A0], 2\nmov [rsp+1A8h+var_19C], 0\ncmp edi, 3\njle short loc_11CD\nmov rax, rsp\nlea edx, [rdi-4]\nlea rcx, [rsp+rdx*4+1A8h+var_1A4]\nloc_11B6:\nmov edx, [rax+8]\nadd edx, [rax+0Ch]\nadd edx, [rax+4]\nadd edx, [rax]\nmov [rax+10h], edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_11B6\nloc_11CD:\nmovsxd rdi, edi\nmov eax, [rsp+rdi*4+1A8h+var_1A8]\nmov rdx, [rsp+1A8h+var_10]\nsub rdx, fs:28h\njnz short loc_11EE\nadd rsp, 1A8h\nretn\nloc_11EE:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n int *v1; // rax\n int v3; // [rsp+0h] [rbp-1A8h] BYREF\n _DWORD v4[101]; // [rsp+4h] [rbp-1A4h] BYREF\n unsigned __int64 v5; // [rsp+198h] [rbp-10h]\n\n v5 = __readfsqword(0x28u);\n v3 = 0;\n v4[0] = 0;\n v4[1] = 2;\n v4[2] = 0;\n if ( a1 > 3 )\n {\n v1 = &v3;\n do\n {\n v1[4] = *v1 + v1[1] + v1[3] + v1[2];\n ++v1;\n }\n while ( v1 != &v4[a1 - 4] );\n }\n return (unsigned int)v4[a1 - 1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n int *v1;\n int v3;\n uint32_t v4[101];\n unsigned long long v5;\n v5 = __readfsqword(40u);\n v3 = 0;\n v4[0] = 0;\n v4[1] = 2;\n v4[2] = 0;\n if (a1 > 3) {\n v1 = &v3;\n do {\n v1[4] = *v1 + v1[1] + v1[3] + v1[2];\n ++v1;\n } while (v1 != &v4[a1 - 4]);\n }\n return (unsigned int)v4[a1 - 1];\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int *v1;\n int v3;\n uint32_t v4[101];\n unsigned long long v5;\n v5 = __readfsqword(40u);\n v3 = 0;\n v4[0] = 0;\n v4[1] = 2;\n v4[2] = 0;\n if (a1 > 3) {\n v1 = &v3;\n do {\n v1[4] = *v1 + v1[1] + v1[3] + v1[2];\n ++v1;\n } while (v1 != &v4[a1 - 4]);\n }\n return (unsigned int)v4[a1 - 1];\n}" + }, + { + "index": "HumanEval-C-46", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int n) {\n int f[100];\n f[0] = 0;\n f[1] = 0;\n f[2] = 2;\n f[3] = 0;\n for (int i = 4; i <= n; i++) {\n f[i] = f[i - 1] + f[i - 2] + f[i - 3] + f[i - 4];\n }\n return f[n];\n}", + "test": "#include \n#include \n\nint main() {\n assert(func0(5) == 4);\n assert(func0(8) == 28);\n assert(func0(10) == 104);\n assert(func0(12) == 386);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nsub rsp, 1A8h\nmovdqa xmm0, cs:xmmword_2070\nmov rax, fs:28h\nmov [rsp+1A8h+var_10], rax\nxor eax, eax\nmovaps [rsp+1A8h+var_1A8], xmm0\ncmp edi, 3\njle short loc_12A4\nlea eax, [rdi-4]\nmov rdx, rsp\nmov ecx, 2\nxor r8d, r8d\nlea r9, [rsp+rax*4+1A8h+var_1A8+4]\nxor eax, eax\nnop dword ptr [rax+00h]\nloc_1288:\nmov esi, eax\nlea eax, [rax+rcx]\nadd rdx, 4\nadd eax, r8d\nadd eax, [rdx-4]\nmov r8d, ecx\nmov ecx, esi\nmov [rdx+0Ch], eax\ncmp r9, rdx\njnz short loc_1288\nloc_12A4:\nmovsxd rdi, edi\nmov eax, dword ptr [rsp+rdi*4+1A8h+var_1A8]\nmov rdx, [rsp+1A8h+var_10]\nsub rdx, fs:28h\njnz short loc_12C5\nadd rsp, 1A8h\nretn\nloc_12C5:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n __m128i *p_si128; // rdx\n int v2; // ecx\n int v3; // r8d\n int v4; // eax\n int v5; // esi\n __m128i si128; // [rsp+0h] [rbp-1A8h] BYREF\n unsigned __int64 v8; // [rsp+198h] [rbp-10h]\n\n v8 = __readfsqword(0x28u);\n si128 = _mm_load_si128((const __m128i *)&xmmword_2070);\n if ( a1 > 3 )\n {\n p_si128 = &si128;\n v2 = 2;\n v3 = 0;\n v4 = 0;\n do\n {\n v5 = v4;\n p_si128 = (__m128i *)((char *)p_si128 + 4);\n v4 += p_si128[-1].m128i_i32[3] + v3 + v2;\n v3 = v2;\n v2 = v5;\n p_si128->m128i_i32[3] = v4;\n }\n while ( (__m128i *)((char *)si128.m128i_i64 + 4 * (unsigned int)(a1 - 4) + 4) != p_si128 );\n }\n return si128.m128i_u32[a1];\n}", + "ida_strip_asm": "sub_1240:\nendbr64\nsub rsp, 1A8h\nmovdqa xmm0, cs:xmmword_2070\nmov rax, fs:28h\nmov [rsp+1A8h+var_10], rax\nxor eax, eax\nmovaps [rsp+1A8h+var_1A8], xmm0\ncmp edi, 3\njle short loc_12A4\nlea eax, [rdi-4]\nmov rdx, rsp\nmov ecx, 2\nxor r8d, r8d\nlea r9, [rsp+rax*4+1A8h+var_1A8+4]\nxor eax, eax\nnop dword ptr [rax+00h]\nloc_1288:\nmov esi, eax\nlea eax, [rax+rcx]\nadd rdx, 4\nadd eax, r8d\nadd eax, [rdx-4]\nmov r8d, ecx\nmov ecx, esi\nmov [rdx+0Ch], eax\ncmp r9, rdx\njnz short loc_1288\nloc_12A4:\nmovsxd rdi, edi\nmov eax, dword ptr [rsp+rdi*4+1A8h+var_1A8]\nmov rdx, [rsp+1A8h+var_10]\nsub rdx, fs:28h\njnz short loc_12C5\nadd rsp, 1A8h\nretn\nloc_12C5:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1240(int a1)\n{\n __m128i *p_si128; // rdx\n int v2; // ecx\n int v3; // r8d\n int v4; // eax\n int v5; // esi\n __m128i si128; // [rsp+0h] [rbp-1A8h] BYREF\n unsigned __int64 v8; // [rsp+198h] [rbp-10h]\n\n v8 = __readfsqword(0x28u);\n si128 = _mm_load_si128((const __m128i *)&xmmword_2070);\n if ( a1 > 3 )\n {\n p_si128 = &si128;\n v2 = 2;\n v3 = 0;\n v4 = 0;\n do\n {\n v5 = v4;\n p_si128 = (__m128i *)((char *)p_si128 + 4);\n v4 += p_si128[-1].m128i_i32[3] + v3 + v2;\n v3 = v2;\n v2 = v5;\n p_si128->m128i_i32[3] = v4;\n }\n while ( (__m128i *)((char *)si128.m128i_i64 + 4 * (unsigned int)(a1 - 4) + 4) != p_si128 );\n }\n return si128.m128i_u32[a1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1240(int a1) {\n __m128i *p_si128;\n int v2;\n int v3;\n int v4;\n int v5;\n __m128i si128;\n unsigned long long v8;\n v8 = __readfsqword(40u);\n si128 = _mm_load_si128((const __m128i *)&xmmword_2070);\n if (a1 > 3) {\n p_si128 = &si128;\n v2 = 2;\n v3 = 0;\n v4 = 0;\n do {\n v5 = v4;\n p_si128 = (__m128i *)((char *)p_si128 + 4);\n v4 += p_si128[-1].m128i_i32[3] + v3 + v2;\n v3 = v2;\n v2 = v5;\n p_si128->m128i_i32[3] = v4;\n } while ((__m128i *)((char *)si128.m128i_i64 + 4 * (unsigned int)(a1 - 4) +\n 4) != p_si128);\n }\n return si128.m128i_u32[a1];\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n __m128i *p_si128;\n int v2;\n int v3;\n int v4;\n int v5;\n __m128i si128;\n unsigned long long v8;\n v8 = __readfsqword(40u);\n si128 = _mm_load_si128((const __m128i *)&xmmword_2070);\n if (a1 > 3) {\n p_si128 = &si128;\n v2 = 2;\n v3 = 0;\n v4 = 0;\n do {\n v5 = v4;\n p_si128 = (__m128i *)((char *)p_si128 + 4);\n v4 += p_si128[-1].m128i_i32[3] + v3 + v2;\n v3 = v2;\n v2 = v5;\n p_si128->m128i_i32[3] = v4;\n } while ((__m128i *)((char *)si128.m128i_i64 + 4 * (unsigned int)(a1 - 4) +\n 4) != p_si128);\n }\n return si128.m128i_u32[a1];\n}" + }, + { + "index": "HumanEval-C-46", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int n) {\n int f[100];\n f[0] = 0;\n f[1] = 0;\n f[2] = 2;\n f[3] = 0;\n for (int i = 4; i <= n; i++) {\n f[i] = f[i - 1] + f[i - 2] + f[i - 3] + f[i - 4];\n }\n return f[n];\n}", + "test": "#include \n#include \n\nint main() {\n assert(func0(5) == 4);\n assert(func0(8) == 28);\n assert(func0(10) == 104);\n assert(func0(12) == 386);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nsub rsp, 1A8h\nmovdqa xmm0, cs:xmmword_2070\nmovsxd rsi, edi\nmov rax, fs:28h\nmov [rsp+1A8h+var_10], rax\nxor eax, eax\nmovaps [rsp+1A8h+var_1A8], xmm0\ncmp esi, 3\njle loc_12FA\nlea r11d, [rsi-1]\ncmp esi, 6\njle loc_1318\nmov r10, rsp\nxor r8d, r8d\nmov edi, 2\nxor edx, edx\nmov rax, r10\nmov ecx, 4\nloc_1298:\nlea r9d, [r8+rdi]\nadd rax, 0Ch\nadd edx, r9d\nadd edx, [rax-0Ch]\nlea r9d, [rdx+r8]\nmov [rax+4], edx\nadd edi, r9d\nadd edi, [rax-8]\nlea r9d, [rdx+rdi]\nmov [rax+8], edi\nadd r8d, r9d\nmov r9d, ecx\nadd r8d, [rax-4]\nadd ecx, 3\nadd r9d, 4\nmov [rax+0Ch], r8d\ncmp r11d, r9d\njg short loc_1298\nloc_12D4:\nmovsxd rax, ecx\nlea rdx, [r10+rax*4]\nnop dword ptr [rax+rax+00h]\nloc_12E0:\nmov eax, [rdx-4]\nadd ecx, 1\nadd eax, [rdx-8]\nadd rdx, 4\nadd eax, [rdx-10h]\nadd eax, [rdx-14h]\nmov [rdx-4], eax\ncmp esi, ecx\njge short loc_12E0\nloc_12FA:\nmov eax, dword ptr [rsp+rsi*4+1A8h+var_1A8]\nmov rdx, [rsp+1A8h+var_10]\nsub rdx, fs:28h\njnz short loc_1322\nadd rsp, 1A8h\nretn\nloc_1318:\nmov ecx, 4\nmov r10, rsp\njmp short loc_12D4\nloc_1322:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n __int64 v1; // rsi\n int v2; // r8d\n int v3; // edi\n int v4; // edx\n __m128i *p_si128; // rax\n int v6; // ecx\n int v7; // r9d\n char *v8; // rdx\n int v9; // eax\n __m128i si128; // [rsp+0h] [rbp-1A8h] BYREF\n unsigned __int64 v12; // [rsp+198h] [rbp-10h]\n\n v1 = a1;\n v12 = __readfsqword(0x28u);\n si128 = _mm_load_si128((const __m128i *)&xmmword_2070);\n if ( a1 > 3 )\n {\n if ( a1 <= 6 )\n {\n v6 = 4;\n }\n else\n {\n v2 = 0;\n v3 = 2;\n v4 = 0;\n p_si128 = &si128;\n v6 = 4;\n do\n {\n p_si128 = (__m128i *)((char *)p_si128 + 12);\n v4 += p_si128[-1].m128i_i32[1] + v2 + v3;\n p_si128->m128i_i32[1] = v4;\n v3 += p_si128[-1].m128i_i32[2] + v4 + v2;\n p_si128->m128i_i32[2] = v3;\n v7 = v6;\n v2 += p_si128[-1].m128i_i32[3] + v4 + v3;\n v6 += 3;\n p_si128->m128i_i32[3] = v2;\n }\n while ( (int)v1 - 1 > v7 + 4 );\n }\n v8 = &si128.m128i_i8[4 * v6];\n do\n {\n ++v6;\n v9 = *((_DWORD *)v8 - 2) + *((_DWORD *)v8 - 1);\n v8 += 4;\n *((_DWORD *)v8 - 1) = *((_DWORD *)v8 - 5) + *((_DWORD *)v8 - 4) + v9;\n }\n while ( (int)v1 >= v6 );\n }\n return si128.m128i_u32[v1];\n}", + "ida_strip_asm": "sub_1240:\nendbr64\nsub rsp, 1A8h\nmovdqa xmm0, cs:xmmword_2070\nmovsxd rsi, edi\nmov rax, fs:28h\nmov [rsp+1A8h+var_10], rax\nxor eax, eax\nmovaps [rsp+1A8h+var_1A8], xmm0\ncmp esi, 3\njle loc_12FA\nlea r11d, [rsi-1]\ncmp esi, 6\njle loc_1318\nmov r10, rsp\nxor r8d, r8d\nmov edi, 2\nxor edx, edx\nmov rax, r10\nmov ecx, 4\nloc_1298:\nlea r9d, [r8+rdi]\nadd rax, 0Ch\nadd edx, r9d\nadd edx, [rax-0Ch]\nlea r9d, [rdx+r8]\nmov [rax+4], edx\nadd edi, r9d\nadd edi, [rax-8]\nlea r9d, [rdx+rdi]\nmov [rax+8], edi\nadd r8d, r9d\nmov r9d, ecx\nadd r8d, [rax-4]\nadd ecx, 3\nadd r9d, 4\nmov [rax+0Ch], r8d\ncmp r11d, r9d\njg short loc_1298\nloc_12D4:\nmovsxd rax, ecx\nlea rdx, [r10+rax*4]\nnop dword ptr [rax+rax+00h]\nloc_12E0:\nmov eax, [rdx-4]\nadd ecx, 1\nadd eax, [rdx-8]\nadd rdx, 4\nadd eax, [rdx-10h]\nadd eax, [rdx-14h]\nmov [rdx-4], eax\ncmp esi, ecx\njge short loc_12E0\nloc_12FA:\nmov eax, dword ptr [rsp+rsi*4+1A8h+var_1A8]\nmov rdx, [rsp+1A8h+var_10]\nsub rdx, fs:28h\njnz short loc_1322\nadd rsp, 1A8h\nretn\nloc_1318:\nmov ecx, 4\nmov r10, rsp\njmp short loc_12D4\nloc_1322:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1240(int a1)\n{\n __int64 v1; // rsi\n int v2; // r8d\n int v3; // edi\n int v4; // edx\n __m128i *p_si128; // rax\n int v6; // ecx\n int v7; // r9d\n char *v8; // rdx\n int v9; // eax\n __m128i si128; // [rsp+0h] [rbp-1A8h] BYREF\n unsigned __int64 v12; // [rsp+198h] [rbp-10h]\n\n v1 = a1;\n v12 = __readfsqword(0x28u);\n si128 = _mm_load_si128((const __m128i *)&xmmword_2070);\n if ( a1 > 3 )\n {\n if ( a1 <= 6 )\n {\n v6 = 4;\n }\n else\n {\n v2 = 0;\n v3 = 2;\n v4 = 0;\n p_si128 = &si128;\n v6 = 4;\n do\n {\n p_si128 = (__m128i *)((char *)p_si128 + 12);\n v4 += p_si128[-1].m128i_i32[1] + v2 + v3;\n p_si128->m128i_i32[1] = v4;\n v3 += p_si128[-1].m128i_i32[2] + v4 + v2;\n p_si128->m128i_i32[2] = v3;\n v7 = v6;\n v2 += p_si128[-1].m128i_i32[3] + v4 + v3;\n v6 += 3;\n p_si128->m128i_i32[3] = v2;\n }\n while ( (int)v1 - 1 > v7 + 4 );\n }\n v8 = &si128.m128i_i8[4 * v6];\n do\n {\n ++v6;\n v9 = *((_DWORD *)v8 - 2) + *((_DWORD *)v8 - 1);\n v8 += 4;\n *((_DWORD *)v8 - 1) = *((_DWORD *)v8 - 5) + *((_DWORD *)v8 - 4) + v9;\n }\n while ( (int)v1 >= v6 );\n }\n return si128.m128i_u32[v1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1240(int a1) {\n long long v1;\n int v2;\n int v3;\n int v4;\n __m128i *p_si128;\n int v6;\n int v7;\n char *v8;\n int v9;\n __m128i si128;\n unsigned long long v12;\n v1 = a1;\n v12 = __readfsqword(40u);\n si128 = _mm_load_si128((const __m128i *)&xmmword_2070);\n if (a1 > 3) {\n if (a1 <= 6) {\n v6 = 4;\n } else {\n v2 = 0;\n v3 = 2;\n v4 = 0;\n p_si128 = &si128;\n v6 = 4;\n do {\n p_si128 = (__m128i *)((char *)p_si128 + 12);\n v4 += p_si128[-1].m128i_i32[1] + v2 + v3;\n p_si128->m128i_i32[1] = v4;\n v3 += p_si128[-1].m128i_i32[2] + v4 + v2;\n p_si128->m128i_i32[2] = v3;\n v7 = v6;\n v2 += p_si128[-1].m128i_i32[3] + v4 + v3;\n v6 += 3;\n p_si128->m128i_i32[3] = v2;\n } while ((int)v1 - 1 > v7 + 4);\n }\n v8 = &si128.m128i_i8[4 * v6];\n do {\n ++v6;\n v9 = *((uint32_t *)v8 - 2) + *((uint32_t *)v8 - 1);\n v8 += 4;\n *((uint32_t *)v8 - 1) =\n *((uint32_t *)v8 - 5) + *((uint32_t *)v8 - 4) + v9;\n } while ((int)v1 >= v6);\n }\n return si128.m128i_u32[v1];\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n long long v1;\n int v2;\n int v3;\n int v4;\n __m128i *p_si128;\n int v6;\n int v7;\n char *v8;\n int v9;\n __m128i si128;\n unsigned long long v12;\n v1 = a1;\n v12 = __readfsqword(40u);\n si128 = _mm_load_si128((const __m128i *)&xmmword_2070);\n if (a1 > 3) {\n if (a1 <= 6) {\n v6 = 4;\n } else {\n v2 = 0;\n v3 = 2;\n v4 = 0;\n p_si128 = &si128;\n v6 = 4;\n do {\n p_si128 = (__m128i *)((char *)p_si128 + 12);\n v4 += p_si128[-1].m128i_i32[1] + v2 + v3;\n p_si128->m128i_i32[1] = v4;\n v3 += p_si128[-1].m128i_i32[2] + v4 + v2;\n p_si128->m128i_i32[2] = v3;\n v7 = v6;\n v2 += p_si128[-1].m128i_i32[3] + v4 + v3;\n v6 += 3;\n p_si128->m128i_i32[3] = v2;\n } while ((int)v1 - 1 > v7 + 4);\n }\n v8 = &si128.m128i_i8[4 * v6];\n do {\n ++v6;\n v9 = *((uint32_t *)v8 - 2) + *((uint32_t *)v8 - 1);\n v8 += 4;\n *((uint32_t *)v8 - 1) =\n *((uint32_t *)v8 - 5) + *((uint32_t *)v8 - 4) + v9;\n } while ((int)v1 >= v6);\n }\n return si128.m128i_u32[v1];\n}" + }, + { + "index": "HumanEval-C-47", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "float func0(float *l, int size) {\n for (int i = 0; i < size; i++) {\n for (int j = i + 1; j < size; j++) {\n if (l[i] > l[j]) {\n float temp = l[i];\n l[i] = l[j];\n l[j] = temp;\n }\n }\n }\n if (size % 2 == 1) return l[size / 2];\n return 0.5 * (l[size / 2] + l[size / 2 - 1]);\n}", + "test": "#include \n#include \n#include \n\nint main() {\n float list1[] = {3, 1, 2, 4, 5};\n assert(fabs(func0(list1, 5) - 3) < 1e-4);\n\n float list2[] = {-10, 4, 6, 1000, 10, 20};\n assert(fabs(func0(list2, 6) - 8.0) < 1e-4);\n\n float list3[] = {5};\n assert(fabs(func0(list3, 1) - 5) < 1e-4);\n\n float list4[] = {6, 5};\n assert(fabs(func0(list4, 2) - 5.5) < 1e-4);\n\n float list5[] = {8, 1, 3, 9, 9, 2, 7};\n assert(fabs(func0(list5, 7) - 7) < 1e-4);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0\njmp loc_1245\nloc_1184:\nmov eax, [rbp+var_C]\nadd eax, 1\nmov [rbp+var_8], eax\njmp loc_1235\nloc_1192:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm1, dword ptr [rax]\ncomiss xmm0, xmm1\njbe short loc_1231\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\nmovss [rbp+var_4], xmm0\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_C]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmovss xmm0, dword ptr [rdx]\nmovss dword ptr [rax], xmm0\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, [rbp+var_4]\nmovss dword ptr [rax], xmm0\nloc_1231:\nadd [rbp+var_8], 1\nloc_1235:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl loc_1192\nadd [rbp+var_C], 1\nloc_1245:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl loc_1184\nmov edx, [rbp+var_1C]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\ncmp eax, 1\njnz short loc_128D\nmov eax, [rbp+var_1C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\njmp short loc_12DF\nloc_128D:\nmov eax, [rbp+var_1C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm1, dword ptr [rax]\nmov eax, [rbp+var_1C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\naddss xmm1, xmm0\nmovss xmm0, cs:dword_20F8\nmulss xmm0, xmm1\nloc_12DF:\npop rbp\nretn", + "ida_pseudo": "float __fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+10h] [rbp-Ch]\n int j; // [rsp+14h] [rbp-8h]\n int v5; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( *(float *)(4LL * i + a1) > *(float *)(4LL * j + a1) )\n {\n v5 = *(_DWORD *)(4LL * i + a1);\n *(_DWORD *)(4LL * i + a1) = *(_DWORD *)(a1 + 4LL * j);\n *(_DWORD *)(4LL * j + a1) = v5;\n }\n }\n }\n if ( a2 % 2 == 1 )\n return *(float *)(4LL * (a2 / 2) + a1);\n else\n return 0.5 * (float)(*(float *)(4LL * (a2 / 2) + a1) + *(float *)(4LL * (a2 / 2) - 4 + a1));\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0\njmp loc_1245\nloc_1184:\nmov eax, [rbp+var_C]\nadd eax, 1\nmov [rbp+var_8], eax\njmp loc_1235\nloc_1192:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm1, dword ptr [rax]\ncomiss xmm0, xmm1\njbe short loc_1231\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\nmovss [rbp+var_4], xmm0\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_C]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmovss xmm0, dword ptr [rdx]\nmovss dword ptr [rax], xmm0\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, [rbp+var_4]\nmovss dword ptr [rax], xmm0\nloc_1231:\nadd [rbp+var_8], 1\nloc_1235:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl loc_1192\nadd [rbp+var_C], 1\nloc_1245:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl loc_1184\nmov edx, [rbp+var_1C]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\ncmp eax, 1\njnz short loc_128D\nmov eax, [rbp+var_1C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\njmp short loc_12DF\nloc_128D:\nmov eax, [rbp+var_1C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm1, dword ptr [rax]\nmov eax, [rbp+var_1C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\naddss xmm1, xmm0\nmovss xmm0, cs:dword_20F8\nmulss xmm0, xmm1\nloc_12DF:\npop rbp\nretn", + "ida_strip_pseudo": "float __fastcall sub_1169(__int64 a1, int a2)\n{\n int i; // [rsp+10h] [rbp-Ch]\n int j; // [rsp+14h] [rbp-8h]\n int v5; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( *(float *)(4LL * i + a1) > *(float *)(4LL * j + a1) )\n {\n v5 = *(_DWORD *)(4LL * i + a1);\n *(_DWORD *)(4LL * i + a1) = *(_DWORD *)(a1 + 4LL * j);\n *(_DWORD *)(4LL * j + a1) = v5;\n }\n }\n }\n if ( a2 % 2 == 1 )\n return *(float *)(4LL * (a2 / 2) + a1);\n else\n return 0.5 * (float)(*(float *)(4LL * (a2 / 2) + a1) + *(float *)(4LL * (a2 / 2) - 4 + a1));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "float sub_1169(long long a1, int a2) {\n int i;\n int j;\n int v5;\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if (*(float *)(4LL * i + a1) > *(float *)(4LL * j + a1)) {\n v5 = *(uint32_t *)(4LL * i + a1);\n *(uint32_t *)(4LL * i + a1) = *(uint32_t *)(a1 + 4LL * j);\n *(uint32_t *)(4LL * j + a1) = v5;\n }\n }\n }\n if (a2 % 2 == 1)\n return *(float *)(4LL * (a2 / 2) + a1);\n else\n return 0.5 * (float)(*(float *)(4LL * (a2 / 2) + a1) +\n *(float *)(4LL * (a2 / 2) - 4 + a1));\n}", + "ida_pseudo_norm": "float func0(long long a1, int a2) {\n int i;\n int j;\n int v5;\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if (*(float *)(4LL * i + a1) > *(float *)(4LL * j + a1)) {\n v5 = *(uint32_t *)(4LL * i + a1);\n *(uint32_t *)(4LL * i + a1) = *(uint32_t *)(a1 + 4LL * j);\n *(uint32_t *)(4LL * j + a1) = v5;\n }\n }\n }\n if (a2 % 2 == 1)\n return *(float *)(4LL * (a2 / 2) + a1);\n else\n return 0.5 * (float)(*(float *)(4LL * (a2 / 2) + a1) +\n *(float *)(4LL * (a2 / 2) - 4 + a1));\n}" + }, + { + "index": "HumanEval-C-47", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "float func0(float *l, int size) {\n for (int i = 0; i < size; i++) {\n for (int j = i + 1; j < size; j++) {\n if (l[i] > l[j]) {\n float temp = l[i];\n l[i] = l[j];\n l[j] = temp;\n }\n }\n }\n if (size % 2 == 1) return l[size / 2];\n return 0.5 * (l[size / 2] + l[size / 2 - 1]);\n}", + "test": "#include \n#include \n#include \n\nint main() {\n float list1[] = {3, 1, 2, 4, 5};\n assert(fabs(func0(list1, 5) - 3) < 1e-4);\n\n float list2[] = {-10, 4, 6, 1000, 10, 20};\n assert(fabs(func0(list2, 6) - 8.0) < 1e-4);\n\n float list3[] = {5};\n assert(fabs(func0(list3, 1) - 5) < 1e-4);\n\n float list4[] = {6, 5};\n assert(fabs(func0(list4, 2) - 5.5) < 1e-4);\n\n float list5[] = {8, 1, 3, 9, 9, 2, 7};\n assert(fabs(func0(list5, 7) - 7) < 1e-4);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbx\nmov r11, rdi\nmov edi, esi\ntest esi, esi\njle short loc_11EA\nlea rdx, [r11+4]\nlea ebx, [rsi-1]\nmov r8d, esi\nmovsxd r10, esi\nmov esi, 1\nlea r9, [r11+8]\njmp short loc_11C1\nloc_118F:\nadd rax, 4\ncmp rax, rcx\njz short loc_11B1\nloc_1198:\nmovss xmm0, dword ptr [rdx-4]\nmovss xmm1, dword ptr [rax]\ncomiss xmm0, xmm1\njbe short loc_118F\nmovss dword ptr [rdx-4], xmm1\nmovss dword ptr [rax], xmm0\njmp short loc_118F\nloc_11B1:\nlea rax, [rsi+1]\nadd rdx, 4\ncmp rsi, r10\njz short loc_11D8\nmov rsi, rax\nloc_11C1:\ncmp rsi, r8\njz short loc_11D8\nmov eax, ebx\nsub eax, esi\nlea rax, [rsi+rax-1]\nlea rcx, [r9+rax*4]\nmov rax, rdx\njmp short loc_1198\nloc_11D8:\nmov edx, edi\nshr edx, 1Fh\nlea eax, [rdi+rdx]\nand eax, 1\nsub eax, edx\ncmp eax, 1\njz short loc_120C\nloc_11EA:\nmov eax, edi\nshr eax, 1Fh\nadd eax, edi\nsar eax, 1\ncdqe\nmovss xmm0, dword ptr [r11+rax*4-4]\naddss xmm0, dword ptr [r11+rax*4]\nmulss xmm0, cs:dword_2004\nloc_120A:\npop rbx\nretn\nloc_120C:\nmov eax, edx\nadd eax, edi\nsar eax, 1\ncdqe\nmovss xmm0, dword ptr [r11+rax*4]\njmp short loc_120A", + "ida_pseudo": "float __fastcall func0(__int64 a1, int a2)\n{\n _DWORD *v4; // rdx\n int v5; // ebx\n __int64 v6; // r8\n __int64 v7; // r10\n __int64 i; // rsi\n _DWORD *v9; // rax\n float v10; // xmm0_4\n\n if ( a2 <= 0 )\n return (float)(*(float *)(a1 + 4LL * (a2 / 2) - 4) + *(float *)(a1 + 4LL * (a2 / 2))) * 0.5;\n v4 = (_DWORD *)(a1 + 4);\n v5 = a2 - 1;\n v6 = (unsigned int)a2;\n v7 = a2;\n for ( i = 1LL; i != v6; ++i )\n {\n v9 = v4;\n do\n {\n v10 = *((float *)v4 - 1);\n if ( v10 > *(float *)v9 )\n {\n *(v4 - 1) = *v9;\n *(float *)v9 = v10;\n }\n ++v9;\n }\n while ( v9 != (_DWORD *)(a1 + 8 + 4 * (i + (unsigned int)(v5 - i) - 1)) );\n ++v4;\n if ( i == v7 )\n break;\n }\n if ( a2 % 2 == 1 )\n return *(float *)(a1 + 4LL * (a2 / 2));\n else\n return (float)(*(float *)(a1 + 4LL * (a2 / 2) - 4) + *(float *)(a1 + 4LL * (a2 / 2))) * 0.5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbx\nmov r11, rdi\nmov edi, esi\ntest esi, esi\njle short loc_11EA\nlea rdx, [r11+4]\nlea ebx, [rsi-1]\nmov r8d, esi\nmovsxd r10, esi\nmov esi, 1\nlea r9, [r11+8]\njmp short loc_11C1\nloc_118F:\nadd rax, 4\ncmp rax, rcx\njz short loc_11B1\nloc_1198:\nmovss xmm0, dword ptr [rdx-4]\nmovss xmm1, dword ptr [rax]\ncomiss xmm0, xmm1\njbe short loc_118F\nmovss dword ptr [rdx-4], xmm1\nmovss dword ptr [rax], xmm0\njmp short loc_118F\nloc_11B1:\nlea rax, [rsi+1]\nadd rdx, 4\ncmp rsi, r10\njz short loc_11D8\nmov rsi, rax\nloc_11C1:\ncmp rsi, r8\njz short loc_11D8\nmov eax, ebx\nsub eax, esi\nlea rax, [rsi+rax-1]\nlea rcx, [r9+rax*4]\nmov rax, rdx\njmp short loc_1198\nloc_11D8:\nmov edx, edi\nshr edx, 1Fh\nlea eax, [rdi+rdx]\nand eax, 1\nsub eax, edx\ncmp eax, 1\njz short loc_120C\nloc_11EA:\nmov eax, edi\nshr eax, 1Fh\nadd eax, edi\nsar eax, 1\ncdqe\nmovss xmm0, dword ptr [r11+rax*4-4]\naddss xmm0, dword ptr [r11+rax*4]\nmulss xmm0, cs:dword_2004\nloc_120A:\npop rbx\nretn\nloc_120C:\nmov eax, edx\nadd eax, edi\nsar eax, 1\ncdqe\nmovss xmm0, dword ptr [r11+rax*4]\njmp short loc_120A", + "ida_strip_pseudo": "float __fastcall sub_1169(__int64 a1, int a2)\n{\n _DWORD *v4; // rdx\n int v5; // ebx\n __int64 v6; // r8\n __int64 v7; // r10\n __int64 i; // rsi\n _DWORD *v9; // rax\n float v10; // xmm0_4\n\n if ( a2 <= 0 )\n return (float)(*(float *)(a1 + 4LL * (a2 / 2) - 4) + *(float *)(a1 + 4LL * (a2 / 2))) * 0.5;\n v4 = (_DWORD *)(a1 + 4);\n v5 = a2 - 1;\n v6 = (unsigned int)a2;\n v7 = a2;\n for ( i = 1LL; i != v6; ++i )\n {\n v9 = v4;\n do\n {\n v10 = *((float *)v4 - 1);\n if ( v10 > *(float *)v9 )\n {\n *(v4 - 1) = *v9;\n *(float *)v9 = v10;\n }\n ++v9;\n }\n while ( v9 != (_DWORD *)(a1 + 8 + 4 * (i + (unsigned int)(v5 - i) - 1)) );\n ++v4;\n if ( i == v7 )\n break;\n }\n if ( a2 % 2 == 1 )\n return *(float *)(a1 + 4LL * (a2 / 2));\n else\n return (float)(*(float *)(a1 + 4LL * (a2 / 2) - 4) + *(float *)(a1 + 4LL * (a2 / 2))) * 0.5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "float sub_1169(long long a1, int a2) {\n uint32_t *v4;\n int v5;\n long long v6;\n long long v7;\n long long i;\n uint32_t *v9;\n float v10;\n if (a2 <= 0)\n return (float)(*(float *)(a1 + 4LL * (a2 / 2) - 4) +\n *(float *)(a1 + 4LL * (a2 / 2))) *\n 0.5;\n v4 = (uint32_t *)(a1 + 4);\n v5 = a2 - 1;\n v6 = (unsigned int)a2;\n v7 = a2;\n for (i = 1LL; i != v6; ++i) {\n v9 = v4;\n do {\n v10 = *((float *)v4 - 1);\n if (v10 > *(float *)v9) {\n *(v4 - 1) = *v9;\n *(float *)v9 = v10;\n }\n ++v9;\n } while (v9 != (uint32_t *)(a1 + 8 + 4 * (i + (unsigned int)(v5 - i) - 1)));\n ++v4;\n if (i == v7) break;\n }\n if (a2 % 2 == 1)\n return *(float *)(a1 + 4LL * (a2 / 2));\n else\n return (float)(*(float *)(a1 + 4LL * (a2 / 2) - 4) +\n *(float *)(a1 + 4LL * (a2 / 2))) *\n 0.5;\n}", + "ida_pseudo_norm": "float func0(long long a1, int a2) {\n uint32_t *v4;\n int v5;\n long long v6;\n long long v7;\n long long i;\n uint32_t *v9;\n float v10;\n if (a2 <= 0)\n return (float)(*(float *)(a1 + 4LL * (a2 / 2) - 4) +\n *(float *)(a1 + 4LL * (a2 / 2))) *\n 0.5;\n v4 = (uint32_t *)(a1 + 4);\n v5 = a2 - 1;\n v6 = (unsigned int)a2;\n v7 = a2;\n for (i = 1LL; i != v6; ++i) {\n v9 = v4;\n do {\n v10 = *((float *)v4 - 1);\n if (v10 > *(float *)v9) {\n *(v4 - 1) = *v9;\n *(float *)v9 = v10;\n }\n ++v9;\n } while (v9 != (uint32_t *)(a1 + 8 + 4 * (i + (unsigned int)(v5 - i) - 1)));\n ++v4;\n if (i == v7) break;\n }\n if (a2 % 2 == 1)\n return *(float *)(a1 + 4LL * (a2 / 2));\n else\n return (float)(*(float *)(a1 + 4LL * (a2 / 2) - 4) +\n *(float *)(a1 + 4LL * (a2 / 2))) *\n 0.5;\n}" + }, + { + "index": "HumanEval-C-47", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "float func0(float *l, int size) {\n for (int i = 0; i < size; i++) {\n for (int j = i + 1; j < size; j++) {\n if (l[i] > l[j]) {\n float temp = l[i];\n l[i] = l[j];\n l[j] = temp;\n }\n }\n }\n if (size % 2 == 1) return l[size / 2];\n return 0.5 * (l[size / 2] + l[size / 2 - 1]);\n}", + "test": "#include \n#include \n#include \n\nint main() {\n float list1[] = {3, 1, 2, 4, 5};\n assert(fabs(func0(list1, 5) - 3) < 1e-4);\n\n float list2[] = {-10, 4, 6, 1000, 10, 20};\n assert(fabs(func0(list2, 6) - 8.0) < 1e-4);\n\n float list3[] = {5};\n assert(fabs(func0(list3, 1) - 5) < 1e-4);\n\n float list4[] = {6, 5};\n assert(fabs(func0(list4, 2) - 5.5) < 1e-4);\n\n float list5[] = {8, 1, 3, 9, 9, 2, 7};\n assert(fabs(func0(list5, 7) - 7) < 1e-4);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_13EA\ncmp esi, 1\njz short loc_1409\nmov rdx, rdi\nmov r8d, esi\nmov ecx, 1\nnop dword ptr [rax+rax+00000000h]\nloc_13B0:\nmov rax, rcx\nnop dword ptr [rax+rax+00h]\nloc_13B8:\nmovss xmm0, dword ptr [rdx]\nmovss xmm1, dword ptr [rdi+rax*4]\ncomiss xmm0, xmm1\njbe short loc_13CF\nmovss dword ptr [rdx], xmm1\nmovss dword ptr [rdi+rax*4], xmm0\nloc_13CF:\nadd rax, 1\ncmp esi, eax\njg short loc_13B8\nadd rcx, 1\nadd rdx, 4\ncmp rcx, r8\njnz short loc_13B0\ntest sil, 1\njnz short loc_1409\nloc_13EA:\nmov eax, esi\nshr eax, 1Fh\nadd eax, esi\nsar eax, 1\ncdqe\nmovss xmm0, dword ptr [rdi+rax*4-4]\naddss xmm0, dword ptr [rdi+rax*4]\nmulss xmm0, cs:dword_2004\nretn\nloc_1409:\nsar esi, 1\nmovsxd rax, esi\nmovss xmm0, dword ptr [rdi+rax*4]\nretn", + "ida_pseudo": "float __fastcall func0(float *a1, int a2)\n{\n float *v2; // rdx\n __int64 i; // rcx\n __int64 v4; // rax\n float v5; // xmm0_4\n float v6; // xmm1_4\n\n if ( a2 <= 0 )\n return (float)(a1[a2 / 2 - 1] + a1[a2 / 2]) * 0.5;\n if ( a2 == 1 )\n return a1[a2 >> 1];\n v2 = a1;\n for ( i = 1LL; i != a2; ++i )\n {\n v4 = i;\n do\n {\n v5 = *v2;\n v6 = a1[v4];\n if ( *v2 > v6 )\n {\n *v2 = v6;\n a1[v4] = v5;\n }\n ++v4;\n }\n while ( a2 > (int)v4 );\n ++v2;\n }\n if ( (a2 & 1) != 0 )\n return a1[a2 >> 1];\n else\n return (float)(a1[a2 / 2 - 1] + a1[a2 / 2]) * 0.5;\n}", + "ida_strip_asm": "sub_1390:\nendbr64\ntest esi, esi\njle short loc_13EA\ncmp esi, 1\njz short loc_1409\nmov rdx, rdi\nmov r8d, esi\nmov ecx, 1\nnop dword ptr [rax+rax+00000000h]\nloc_13B0:\nmov rax, rcx\nnop dword ptr [rax+rax+00h]\nloc_13B8:\nmovss xmm0, dword ptr [rdx]\nmovss xmm1, dword ptr [rdi+rax*4]\ncomiss xmm0, xmm1\njbe short loc_13CF\nmovss dword ptr [rdx], xmm1\nmovss dword ptr [rdi+rax*4], xmm0\nloc_13CF:\nadd rax, 1\ncmp esi, eax\njg short loc_13B8\nadd rcx, 1\nadd rdx, 4\ncmp rcx, r8\njnz short loc_13B0\ntest sil, 1\njnz short loc_1409\nloc_13EA:\nmov eax, esi\nshr eax, 1Fh\nadd eax, esi\nsar eax, 1\ncdqe\nmovss xmm0, dword ptr [rdi+rax*4-4]\naddss xmm0, dword ptr [rdi+rax*4]\nmulss xmm0, cs:dword_2004\nretn\nloc_1409:\nsar esi, 1\nmovsxd rax, esi\nmovss xmm0, dword ptr [rdi+rax*4]\nretn", + "ida_strip_pseudo": "float __fastcall sub_1390(float *a1, int a2)\n{\n float *v2; // rdx\n __int64 i; // rcx\n __int64 v4; // rax\n float v5; // xmm0_4\n float v6; // xmm1_4\n\n if ( a2 <= 0 )\n return (float)(a1[a2 / 2 - 1] + a1[a2 / 2]) * 0.5;\n if ( a2 == 1 )\n return a1[a2 >> 1];\n v2 = a1;\n for ( i = 1LL; i != a2; ++i )\n {\n v4 = i;\n do\n {\n v5 = *v2;\n v6 = a1[v4];\n if ( *v2 > v6 )\n {\n *v2 = v6;\n a1[v4] = v5;\n }\n ++v4;\n }\n while ( a2 > (int)v4 );\n ++v2;\n }\n if ( (a2 & 1) != 0 )\n return a1[a2 >> 1];\n else\n return (float)(a1[a2 / 2 - 1] + a1[a2 / 2]) * 0.5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "float sub_1390(float *a1, int a2) {\n float *v2;\n long long i;\n long long v4;\n float v5;\n float v6;\n if (a2 <= 0) return (float)(a1[a2 / 2 - 1] + a1[a2 / 2]) * 0.5;\n if (a2 == 1) return a1[a2 >> 1];\n v2 = a1;\n for (i = 1LL; i != a2; ++i) {\n v4 = i;\n do {\n v5 = *v2;\n v6 = a1[v4];\n if (*v2 > v6) {\n *v2 = v6;\n a1[v4] = v5;\n }\n ++v4;\n } while (a2 > (int)v4);\n ++v2;\n }\n if ((a2 & 1) != 0)\n return a1[a2 >> 1];\n else\n return (float)(a1[a2 / 2 - 1] + a1[a2 / 2]) * 0.5;\n}", + "ida_pseudo_norm": "float func0(float *a1, int a2) {\n float *v2;\n long long i;\n long long v4;\n float v5;\n float v6;\n if (a2 <= 0) return (float)(a1[a2 / 2 - 1] + a1[a2 / 2]) * 0.5;\n if (a2 == 1) return a1[a2 >> 1];\n v2 = a1;\n for (i = 1LL; i != a2; ++i) {\n v4 = i;\n do {\n v5 = *v2;\n v6 = a1[v4];\n if (*v2 > v6) {\n *v2 = v6;\n a1[v4] = v5;\n }\n ++v4;\n } while (a2 > (int)v4);\n ++v2;\n }\n if ((a2 & 1) != 0)\n return a1[a2 >> 1];\n else\n return (float)(a1[a2 / 2 - 1] + a1[a2 / 2]) * 0.5;\n}" + }, + { + "index": "HumanEval-C-47", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "float func0(float *l, int size) {\n for (int i = 0; i < size; i++) {\n for (int j = i + 1; j < size; j++) {\n if (l[i] > l[j]) {\n float temp = l[i];\n l[i] = l[j];\n l[j] = temp;\n }\n }\n }\n if (size % 2 == 1) return l[size / 2];\n return 0.5 * (l[size / 2] + l[size / 2 - 1]);\n}", + "test": "#include \n#include \n#include \n\nint main() {\n float list1[] = {3, 1, 2, 4, 5};\n assert(fabs(func0(list1, 5) - 3) < 1e-4);\n\n float list2[] = {-10, 4, 6, 1000, 10, 20};\n assert(fabs(func0(list2, 6) - 8.0) < 1e-4);\n\n float list3[] = {5};\n assert(fabs(func0(list3, 1) - 5) < 1e-4);\n\n float list4[] = {6, 5};\n assert(fabs(func0(list4, 2) - 5.5) < 1e-4);\n\n float list5[] = {8, 1, 3, 9, 9, 2, 7};\n assert(fabs(func0(list5, 7) - 7) < 1e-4);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_12BA\ncmp esi, 1\njz short loc_12D9\nmov rdx, rdi\nmov r8d, esi\nmov ecx, 1\nnop dword ptr [rax+rax+00000000h]\nloc_1280:\nmov rax, rcx\nnop dword ptr [rax+rax+00h]\nloc_1288:\nmovss xmm0, dword ptr [rdx]\nmovss xmm1, dword ptr [rdi+rax*4]\ncomiss xmm0, xmm1\njbe short loc_129F\nmovss dword ptr [rdx], xmm1\nmovss dword ptr [rdi+rax*4], xmm0\nloc_129F:\nadd rax, 1\ncmp esi, eax\njg short loc_1288\nadd rcx, 1\nadd rdx, 4\ncmp r8, rcx\njnz short loc_1280\ntest sil, 1\njnz short loc_12D9\nloc_12BA:\nmov eax, esi\nshr eax, 1Fh\nadd eax, esi\nsar eax, 1\ncdqe\nmovss xmm0, dword ptr [rdi+rax*4-4]\naddss xmm0, dword ptr [rdi+rax*4]\nmulss xmm0, cs:dword_2004\nretn\nloc_12D9:\nsar esi, 1\nmovsxd rax, esi\nmovss xmm0, dword ptr [rdi+rax*4]\nretn", + "ida_pseudo": "float __fastcall func0(float *a1, int a2)\n{\n float *v2; // rdx\n __int64 i; // rcx\n __int64 v4; // rax\n float v5; // xmm0_4\n float v6; // xmm1_4\n\n if ( a2 <= 0 )\n return (float)(a1[a2 / 2 - 1] + a1[a2 / 2]) * 0.5;\n if ( a2 == 1 )\n return a1[a2 >> 1];\n v2 = a1;\n for ( i = 1LL; i != a2; ++i )\n {\n v4 = i;\n do\n {\n v5 = *v2;\n v6 = a1[v4];\n if ( *v2 > v6 )\n {\n *v2 = v6;\n a1[v4] = v5;\n }\n ++v4;\n }\n while ( a2 > (int)v4 );\n ++v2;\n }\n if ( (a2 & 1) != 0 )\n return a1[a2 >> 1];\n else\n return (float)(a1[a2 / 2 - 1] + a1[a2 / 2]) * 0.5;\n}", + "ida_strip_asm": "sub_1260:\nendbr64\ntest esi, esi\njle short loc_12BA\ncmp esi, 1\njz short loc_12D9\nmov rdx, rdi\nmov r8d, esi\nmov ecx, 1\nnop dword ptr [rax+rax+00000000h]\nloc_1280:\nmov rax, rcx\nnop dword ptr [rax+rax+00h]\nloc_1288:\nmovss xmm0, dword ptr [rdx]\nmovss xmm1, dword ptr [rdi+rax*4]\ncomiss xmm0, xmm1\njbe short loc_129F\nmovss dword ptr [rdx], xmm1\nmovss dword ptr [rdi+rax*4], xmm0\nloc_129F:\nadd rax, 1\ncmp esi, eax\njg short loc_1288\nadd rcx, 1\nadd rdx, 4\ncmp r8, rcx\njnz short loc_1280\ntest sil, 1\njnz short loc_12D9\nloc_12BA:\nmov eax, esi\nshr eax, 1Fh\nadd eax, esi\nsar eax, 1\ncdqe\nmovss xmm0, dword ptr [rdi+rax*4-4]\naddss xmm0, dword ptr [rdi+rax*4]\nmulss xmm0, cs:dword_2004\nretn\nloc_12D9:\nsar esi, 1\nmovsxd rax, esi\nmovss xmm0, dword ptr [rdi+rax*4]\nretn", + "ida_strip_pseudo": "float __fastcall sub_1260(float *a1, int a2)\n{\n float *v2; // rdx\n __int64 i; // rcx\n __int64 v4; // rax\n float v5; // xmm0_4\n float v6; // xmm1_4\n\n if ( a2 <= 0 )\n return (float)(a1[a2 / 2 - 1] + a1[a2 / 2]) * 0.5;\n if ( a2 == 1 )\n return a1[a2 >> 1];\n v2 = a1;\n for ( i = 1LL; i != a2; ++i )\n {\n v4 = i;\n do\n {\n v5 = *v2;\n v6 = a1[v4];\n if ( *v2 > v6 )\n {\n *v2 = v6;\n a1[v4] = v5;\n }\n ++v4;\n }\n while ( a2 > (int)v4 );\n ++v2;\n }\n if ( (a2 & 1) != 0 )\n return a1[a2 >> 1];\n else\n return (float)(a1[a2 / 2 - 1] + a1[a2 / 2]) * 0.5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "float sub_1260(float *a1, int a2) {\n float *v2;\n long long i;\n long long v4;\n float v5;\n float v6;\n if (a2 <= 0) return (float)(a1[a2 / 2 - 1] + a1[a2 / 2]) * 0.5;\n if (a2 == 1) return a1[a2 >> 1];\n v2 = a1;\n for (i = 1LL; i != a2; ++i) {\n v4 = i;\n do {\n v5 = *v2;\n v6 = a1[v4];\n if (*v2 > v6) {\n *v2 = v6;\n a1[v4] = v5;\n }\n ++v4;\n } while (a2 > (int)v4);\n ++v2;\n }\n if ((a2 & 1) != 0)\n return a1[a2 >> 1];\n else\n return (float)(a1[a2 / 2 - 1] + a1[a2 / 2]) * 0.5;\n}", + "ida_pseudo_norm": "float func0(float *a1, int a2) {\n float *v2;\n long long i;\n long long v4;\n float v5;\n float v6;\n if (a2 <= 0) return (float)(a1[a2 / 2 - 1] + a1[a2 / 2]) * 0.5;\n if (a2 == 1) return a1[a2 >> 1];\n v2 = a1;\n for (i = 1LL; i != a2; ++i) {\n v4 = i;\n do {\n v5 = *v2;\n v6 = a1[v4];\n if (*v2 > v6) {\n *v2 = v6;\n a1[v4] = v5;\n }\n ++v4;\n } while (a2 > (int)v4);\n ++v2;\n }\n if ((a2 & 1) != 0)\n return a1[a2 >> 1];\n else\n return (float)(a1[a2 / 2 - 1] + a1[a2 / 2]) * 0.5;\n}" + }, + { + "index": "HumanEval-C-48", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "bool func0(const char *text) {\n int len = strlen(text);\n for (int i = 0; i < len / 2; i++) {\n if (text[i] != text[len - 1 - i]) {\n return false;\n }\n }\n return true;\n}", + "test": "#include \n#include \n\nint main() {\n assert(func0(\"\") == true);\n assert(func0(\"aba\") == true);\n assert(func0(\"aaaaa\") == true);\n assert(func0(\"zbcd\") == false);\n assert(func0(\"xywyx\") == true);\n assert(func0(\"xywyz\") == false);\n assert(func0(\"xywzx\") == false);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_8], 0\njmp short loc_11C6\nloc_1191:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_4]\nsub eax, 1\nsub eax, [rbp+var_8]\nmovsxd rcx, eax\nmov rax, [rbp+s]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njz short loc_11C2\nmov eax, 0\njmp short locret_11DC\nloc_11C2:\nadd [rbp+var_8], 1\nloc_11C6:\nmov eax, [rbp+var_4]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\ncmp [rbp+var_8], eax\njl short loc_1191\nmov eax, 1\nlocret_11DC:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int i; // [rsp+18h] [rbp-8h]\n int v3; // [rsp+1Ch] [rbp-4h]\n\n v3 = strlen(a1);\n for ( i = 0; i < v3 / 2; ++i )\n {\n if ( a1[i] != a1[v3 - 1 - i] )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_8], 0\njmp short loc_11C6\nloc_1191:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_4]\nsub eax, 1\nsub eax, [rbp+var_8]\nmovsxd rcx, eax\nmov rax, [rbp+s]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njz short loc_11C2\nmov eax, 0\njmp short locret_11DC\nloc_11C2:\nadd [rbp+var_8], 1\nloc_11C6:\nmov eax, [rbp+var_4]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\ncmp [rbp+var_8], eax\njl short loc_1191\nmov eax, 1\nlocret_11DC:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1)\n{\n int i; // [rsp+18h] [rbp-8h]\n int v3; // [rsp+1Ch] [rbp-4h]\n\n v3 = strlen(a1);\n for ( i = 0; i < v3 / 2; ++i )\n {\n if ( a1[i] != a1[v3 - 1 - i] )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1) {\n int i;\n int v3;\n v3 = strlen(a1);\n for (i = 0; i < v3 / 2; ++i) {\n if (a1[i] != a1[v3 - 1 - i]) return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int i;\n int v3;\n v3 = strlen(a1);\n for (i = 0; i < v3 / 2; ++i) {\n if (a1[i] != a1[v3 - 1 - i]) return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": "HumanEval-C-48", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "bool func0(const char *text) {\n int len = strlen(text);\n for (int i = 0; i < len / 2; i++) {\n if (text[i] != text[len - 1 - i]) {\n return false;\n }\n }\n return true;\n}", + "test": "#include \n#include \n\nint main() {\n assert(func0(\"\") == true);\n assert(func0(\"aba\") == true);\n assert(func0(\"aaaaa\") == true);\n assert(func0(\"zbcd\") == false);\n assert(func0(\"xywyx\") == true);\n assert(func0(\"xywyz\") == false);\n assert(func0(\"xywzx\") == false);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmov ecx, eax\nshr ecx, 1Fh\nadd ecx, eax\nsar ecx, 1\ncmp eax, 1\njle short loc_11AC\ncdqe\nlea rdx, [rbx+rax-1]\nmov eax, 0\nloc_1190:\nmovzx esi, byte ptr [rdx]\ncmp [rbx+rax], sil\njnz short loc_11B3\nadd rax, 1\nsub rdx, 1\ncmp ecx, eax\njg short loc_1190\nmov eax, 1\njmp short loc_11B8\nloc_11AC:\nmov eax, 1\njmp short loc_11B8\nloc_11B3:\nmov eax, 0\nloc_11B8:\npop rbx\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v1; // eax\n int v2; // ecx\n const char *v3; // rdx\n __int64 v4; // rax\n\n v1 = strlen(a1);\n v2 = v1 / 2;\n if ( v1 <= 1 )\n return 1LL;\n v3 = &a1[v1 - 1];\n v4 = 0LL;\n while ( a1[v4] == *v3 )\n {\n ++v4;\n --v3;\n if ( v2 <= (int)v4 )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmov ecx, eax\nshr ecx, 1Fh\nadd ecx, eax\nsar ecx, 1\ncmp eax, 1\njle short loc_11AC\ncdqe\nlea rdx, [rbx+rax-1]\nmov eax, 0\nloc_1190:\nmovzx esi, byte ptr [rdx]\ncmp [rbx+rax], sil\njnz short loc_11B3\nadd rax, 1\nsub rdx, 1\ncmp ecx, eax\njg short loc_1190\nmov eax, 1\njmp short loc_11B8\nloc_11AC:\nmov eax, 1\njmp short loc_11B8\nloc_11B3:\nmov eax, 0\nloc_11B8:\npop rbx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1)\n{\n int v1; // eax\n int v2; // ecx\n const char *v3; // rdx\n __int64 v4; // rax\n\n v1 = strlen(a1);\n v2 = v1 / 2;\n if ( v1 <= 1 )\n return 1LL;\n v3 = &a1[v1 - 1];\n v4 = 0LL;\n while ( a1[v4] == *v3 )\n {\n ++v4;\n --v3;\n if ( v2 <= (int)v4 )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1) {\n int v1;\n int v2;\n const char *v3;\n long long v4;\n v1 = strlen(a1);\n v2 = v1 / 2;\n if (v1 <= 1) return 1LL;\n v3 = &a1[v1 - 1];\n v4 = 0LL;\n while (a1[v4] == *v3) {\n ++v4;\n --v3;\n if (v2 <= (int)v4) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v1;\n int v2;\n const char *v3;\n long long v4;\n v1 = strlen(a1);\n v2 = v1 / 2;\n if (v1 <= 1) return 1LL;\n v3 = &a1[v1 - 1];\n v4 = 0LL;\n while (a1[v4] == *v3) {\n ++v4;\n --v3;\n if (v2 <= (int)v4) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": "HumanEval-C-48", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "bool func0(const char *text) {\n int len = strlen(text);\n for (int i = 0; i < len / 2; i++) {\n if (text[i] != text[len - 1 - i]) {\n return false;\n }\n }\n return true;\n}", + "test": "#include \n#include \n\nint main() {\n assert(func0(\"\") == true);\n assert(func0(\"aba\") == true);\n assert(func0(\"aaaaa\") == true);\n assert(func0(\"zbcd\") == false);\n assert(func0(\"xywyx\") == true);\n assert(func0(\"xywyz\") == false);\n assert(func0(\"xywzx\") == false);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmov ecx, eax\nshr ecx, 1Fh\nadd ecx, eax\nsar ecx, 1\ncmp eax, 1\njle short loc_1330\nsub eax, 1\nxor edx, edx\ncdqe\nadd rax, rbx\njmp short loc_131C\nloc_1310:\nadd rdx, 1\nsub rax, 1\ncmp ecx, edx\njle short loc_1330\nloc_131C:\nmovzx esi, byte ptr [rax]\ncmp [rbx+rdx], sil\njz short loc_1310\nxor eax, eax\npop rbx\nretn\nloc_1330:\nmov eax, 1\npop rbx\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v1; // eax\n int v2; // ecx\n __int64 v3; // rdx\n const char *i; // rax\n\n v1 = strlen(a1);\n v2 = v1 / 2;\n if ( v1 <= 1 )\n return 1LL;\n v3 = 0LL;\n for ( i = &a1[v1 - 1]; a1[v3] == *i; --i )\n {\n if ( v2 <= (int)++v3 )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmov ecx, eax\nshr ecx, 1Fh\nadd ecx, eax\nsar ecx, 1\ncmp eax, 1\njle short loc_1330\nsub eax, 1\nxor edx, edx\ncdqe\nadd rax, rbx\njmp short loc_131C\nloc_1310:\nadd rdx, 1\nsub rax, 1\ncmp ecx, edx\njle short loc_1330\nloc_131C:\nmovzx esi, byte ptr [rax]\ncmp [rbx+rdx], sil\njz short loc_1310\nxor eax, eax\npop rbx\nretn\nloc_1330:\nmov eax, 1\npop rbx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12E0(const char *a1)\n{\n int v1; // eax\n int v2; // ecx\n __int64 v3; // rdx\n const char *i; // rax\n\n v1 = strlen(a1);\n v2 = v1 / 2;\n if ( v1 <= 1 )\n return 1LL;\n v3 = 0LL;\n for ( i = &a1[v1 - 1]; a1[v3] == *i; --i )\n {\n if ( v2 <= (int)++v3 )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12E0(const char *a1) {\n int v1;\n int v2;\n long long v3;\n const char *i;\n v1 = strlen(a1);\n v2 = v1 / 2;\n if (v1 <= 1) return 1LL;\n v3 = 0LL;\n for (i = &a1[v1 - 1]; a1[v3] == *i; --i) {\n if (v2 <= (int)++v3) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v1;\n int v2;\n long long v3;\n const char *i;\n v1 = strlen(a1);\n v2 = v1 / 2;\n if (v1 <= 1) return 1LL;\n v3 = 0LL;\n for (i = &a1[v1 - 1]; a1[v3] == *i; --i) {\n if (v2 <= (int)++v3) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": "HumanEval-C-48", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "bool func0(const char *text) {\n int len = strlen(text);\n for (int i = 0; i < len / 2; i++) {\n if (text[i] != text[len - 1 - i]) {\n return false;\n }\n }\n return true;\n}", + "test": "#include \n#include \n\nint main() {\n assert(func0(\"\") == true);\n assert(func0(\"aba\") == true);\n assert(func0(\"aaaaa\") == true);\n assert(func0(\"zbcd\") == false);\n assert(func0(\"xywyx\") == true);\n assert(func0(\"xywyz\") == false);\n assert(func0(\"xywzx\") == false);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmov ecx, eax\nshr ecx, 1Fh\nadd ecx, eax\nsar ecx, 1\ncmp eax, 1\njle short loc_1330\nsub eax, 1\nxor edx, edx\ncdqe\nadd rax, rbx\njmp short loc_131C\nloc_1310:\nadd rdx, 1\nsub rax, 1\ncmp ecx, edx\njle short loc_1330\nloc_131C:\nmovzx esi, byte ptr [rax]\ncmp [rbx+rdx], sil\njz short loc_1310\nxor eax, eax\npop rbx\nretn\nloc_1330:\nmov eax, 1\npop rbx\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v1; // eax\n int v2; // ecx\n __int64 v3; // rdx\n const char *i; // rax\n\n v1 = strlen(a1);\n v2 = v1 / 2;\n if ( v1 <= 1 )\n return 1LL;\n v3 = 0LL;\n for ( i = &a1[v1 - 1]; a1[v3] == *i; --i )\n {\n if ( v2 <= (int)++v3 )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmov ecx, eax\nshr ecx, 1Fh\nadd ecx, eax\nsar ecx, 1\ncmp eax, 1\njle short loc_1330\nsub eax, 1\nxor edx, edx\ncdqe\nadd rax, rbx\njmp short loc_131C\nloc_1310:\nadd rdx, 1\nsub rax, 1\ncmp ecx, edx\njle short loc_1330\nloc_131C:\nmovzx esi, byte ptr [rax]\ncmp [rbx+rdx], sil\njz short loc_1310\nxor eax, eax\npop rbx\nretn\nloc_1330:\nmov eax, 1\npop rbx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12E0(const char *a1)\n{\n int v1; // eax\n int v2; // ecx\n __int64 v3; // rdx\n const char *i; // rax\n\n v1 = strlen(a1);\n v2 = v1 / 2;\n if ( v1 <= 1 )\n return 1LL;\n v3 = 0LL;\n for ( i = &a1[v1 - 1]; a1[v3] == *i; --i )\n {\n if ( v2 <= (int)++v3 )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12E0(const char *a1) {\n int v1;\n int v2;\n long long v3;\n const char *i;\n v1 = strlen(a1);\n v2 = v1 / 2;\n if (v1 <= 1) return 1LL;\n v3 = 0LL;\n for (i = &a1[v1 - 1]; a1[v3] == *i; --i) {\n if (v2 <= (int)++v3) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v1;\n int v2;\n long long v3;\n const char *i;\n v1 = strlen(a1);\n v2 = v1 / 2;\n if (v1 <= 1) return 1LL;\n v3 = 0LL;\n for (i = &a1[v1 - 1]; a1[v3] == *i; --i) {\n if (v2 <= (int)++v3) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": "HumanEval-C-49", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int n, int p) {\n int out = 1;\n for (int i = 0; i < n; i++) out = (out * 2) % p;\n return out;\n}", + "test": "#include \n#include \n\nint main() {\n assert(func0(3, 5) == 3);\n assert(func0(1101, 101) == 2);\n assert(func0(0, 101) == 1);\n assert(func0(3, 11) == 8);\n assert(func0(100, 101) == 1);\n assert(func0(30, 5) == 4);\n assert(func0(31, 5) == 3);\n\n printf(\"All tests passed.\\n\");\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_8], 1\nmov [rbp+var_4], 0\njmp short loc_1197\nloc_1187:\nmov eax, [rbp+var_8]\nadd eax, eax\ncdq\nidiv [rbp+var_18]\nmov [rbp+var_8], edx\nadd [rbp+var_4], 1\nloc_1197:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_14]\njl short loc_1187\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n unsigned int v3; // [rsp+10h] [rbp-8h]\n int i; // [rsp+14h] [rbp-4h]\n\n v3 = 1;\n for ( i = 0; i < a1; ++i )\n v3 = (int)(2 * v3) % a2;\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_8], 1\nmov [rbp+var_4], 0\njmp short loc_1197\nloc_1187:\nmov eax, [rbp+var_8]\nadd eax, eax\ncdq\nidiv [rbp+var_18]\nmov [rbp+var_8], edx\nadd [rbp+var_4], 1\nloc_1197:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_14]\njl short loc_1187\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1, int a2)\n{\n unsigned int v3; // [rsp+10h] [rbp-8h]\n int i; // [rsp+14h] [rbp-4h]\n\n v3 = 1;\n for ( i = 0; i < a1; ++i )\n v3 = (int)(2 * v3) % a2;\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 1;\n for (i = 0; i < a1; ++i) v3 = (int)(2 * v3) % a2;\n return v3;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 1;\n for (i = 0; i < a1; ++i) v3 = (int)(2 * v3) % a2;\n return v3;\n}" + }, + { + "index": "HumanEval-C-49", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int n, int p) {\n int out = 1;\n for (int i = 0; i < n; i++) out = (out * 2) % p;\n return out;\n}", + "test": "#include \n#include \n\nint main() {\n assert(func0(3, 5) == 3);\n assert(func0(1101, 101) == 2);\n assert(func0(0, 101) == 1);\n assert(func0(3, 11) == 8);\n assert(func0(100, 101) == 1);\n assert(func0(30, 5) == 4);\n assert(func0(31, 5) == 3);\n\n printf(\"All tests passed.\\n\");\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njle short loc_118B\nmov ecx, 0\nmov edx, 1\nloc_117B:\nlea eax, [rdx+rdx]\ncdq\nidiv esi\nadd ecx, 1\ncmp edi, ecx\njnz short loc_117B\nloc_1188:\nmov eax, edx\nretn\nloc_118B:\nmov edx, 1\njmp short loc_1188", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n int v2; // ecx\n unsigned int v3; // edx\n\n if ( a1 <= 0 )\n {\n return 1;\n }\n else\n {\n v2 = 0;\n v3 = 1;\n do\n {\n v3 = (int)(2 * v3) % a2;\n ++v2;\n }\n while ( a1 != v2 );\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest edi, edi\njle short loc_118B\nmov ecx, 0\nmov edx, 1\nloc_117B:\nlea eax, [rdx+rdx]\ncdq\nidiv esi\nadd ecx, 1\ncmp edi, ecx\njnz short loc_117B\nloc_1188:\nmov eax, edx\nretn\nloc_118B:\nmov edx, 1\njmp short loc_1188", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1, int a2)\n{\n int v2; // ecx\n unsigned int v3; // edx\n\n if ( a1 <= 0 )\n {\n return 1;\n }\n else\n {\n v2 = 0;\n v3 = 1;\n do\n {\n v3 = (int)(2 * v3) % a2;\n ++v2;\n }\n while ( a1 != v2 );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1, int a2) {\n int v2;\n unsigned int v3;\n if (a1 <= 0) {\n return 1;\n } else {\n v2 = 0;\n v3 = 1;\n do {\n v3 = (int)(2 * v3) % a2;\n ++v2;\n } while (a1 != v2);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n int v2;\n unsigned int v3;\n if (a1 <= 0) {\n return 1;\n } else {\n v2 = 0;\n v3 = 1;\n do {\n v3 = (int)(2 * v3) % a2;\n ++v2;\n } while (a1 != v2);\n }\n return v3;\n}" + }, + { + "index": "HumanEval-C-50", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "void func0(char *s, int encode) {\n int shift = encode ? 5 : 21;\n size_t len = strlen(s);\n for (size_t i = 0; i < len; i++) {\n int w = ((s[i] - 'a' + shift) % 26) + 'a';\n s[i] = (char)w;\n }\n}", + "test": "#include \n#include \n#include \n#include \n#include \n\nint main() {\n srand((unsigned int)time(NULL));\n\n for (int i = 0; i < 100; i++) {\n int l = 10 + rand() % 11;\n char *str = (char *)malloc(l + 1);\n for (int j = 0; j < l; j++) {\n char chr = 'a' + rand() % 26;\n str[j] = chr;\n }\n str[l] = '\\0';\n\n char *encoded_str = (char *)malloc(l + 1);\n strcpy(encoded_str, str);\n func0(encoded_str, 1);\n func0(encoded_str, 0);\n assert(strcmp(encoded_str, str) == 0);\n\n free(str);\n free(encoded_str);\n }\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov [rbp+var_2C], esi\ncmp [rbp+var_2C], 0\njz short loc_1269\nmov eax, 5\njmp short loc_126E\nloc_1269:\nmov eax, 15h\nloc_126E:\nmov [rbp+var_18], eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_8], rax\nmov [rbp+var_10], 0\njmp short loc_12DE\nloc_128B:\nmov rdx, [rbp+s]\nmov rax, [rbp+var_10]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nlea edx, [rax-61h]\nmov eax, [rbp+var_18]\nadd edx, eax\nmovsxd rax, edx\nimul rax, 4EC4EC4Fh\nshr rax, 20h\nsar eax, 3\nmov ecx, edx\nsar ecx, 1Fh\nsub eax, ecx\nimul ecx, eax, 1Ah\nmov eax, edx\nsub eax, ecx\nadd eax, 61h ; 'a'\nmov [rbp+var_14], eax\nmov rdx, [rbp+s]\nmov rax, [rbp+var_10]\nadd rax, rdx\nmov edx, [rbp+var_14]\nmov [rax], dl\nadd [rbp+var_10], 1\nloc_12DE:\nmov rax, [rbp+var_10]\ncmp rax, [rbp+var_8]\njb short loc_128B\nnop\nnop\nleave\nretn", + "ida_pseudo": "size_t __fastcall func0(const char *a1, int a2)\n{\n int v2; // eax\n size_t result; // rax\n int v4; // [rsp+18h] [rbp-18h]\n size_t i; // [rsp+20h] [rbp-10h]\n size_t v6; // [rsp+28h] [rbp-8h]\n\n if ( a2 )\n v2 = 5;\n else\n v2 = 21;\n v4 = v2;\n v6 = strlen(a1);\n for ( i = 0LL; ; ++i )\n {\n result = i;\n if ( i >= v6 )\n break;\n a1[i] = (v4 + a1[i] - 97) % 26 + 97;\n }\n return result;\n}", + "ida_strip_asm": "sub_1249:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov [rbp+var_2C], esi\ncmp [rbp+var_2C], 0\njz short loc_1269\nmov eax, 5\njmp short loc_126E\nloc_1269:\nmov eax, 15h\nloc_126E:\nmov [rbp+var_18], eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_8], rax\nmov [rbp+var_10], 0\njmp short loc_12DE\nloc_128B:\nmov rdx, [rbp+s]\nmov rax, [rbp+var_10]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nlea edx, [rax-61h]\nmov eax, [rbp+var_18]\nadd edx, eax\nmovsxd rax, edx\nimul rax, 4EC4EC4Fh\nshr rax, 20h\nsar eax, 3\nmov ecx, edx\nsar ecx, 1Fh\nsub eax, ecx\nimul ecx, eax, 1Ah\nmov eax, edx\nsub eax, ecx\nadd eax, 61h ; 'a'\nmov [rbp+var_14], eax\nmov rdx, [rbp+s]\nmov rax, [rbp+var_10]\nadd rax, rdx\nmov edx, [rbp+var_14]\nmov [rax], dl\nadd [rbp+var_10], 1\nloc_12DE:\nmov rax, [rbp+var_10]\ncmp rax, [rbp+var_8]\njb short loc_128B\nnop\nnop\nleave\nretn", + "ida_strip_pseudo": "size_t __fastcall sub_1249(const char *a1, int a2)\n{\n int v2; // eax\n size_t result; // rax\n int v4; // [rsp+18h] [rbp-18h]\n size_t i; // [rsp+20h] [rbp-10h]\n size_t v6; // [rsp+28h] [rbp-8h]\n\n if ( a2 )\n v2 = 5;\n else\n v2 = 21;\n v4 = v2;\n v6 = strlen(a1);\n for ( i = 0LL; ; ++i )\n {\n result = i;\n if ( i >= v6 )\n break;\n a1[i] = (v4 + a1[i] - 97) % 26 + 97;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned int sub_1249(const char *a1, int a2) {\n int v2;\n unsigned int result;\n int v4;\n unsigned int i;\n unsigned int v6;\n if (a2)\n v2 = 5;\n else\n v2 = 21;\n v4 = v2;\n v6 = strlen(a1);\n for (i = 0LL;; ++i) {\n result = i;\n if (i >= v6) break;\n a1[i] = (v4 + a1[i] - 97) % 26 + 97;\n }\n return result;\n}", + "ida_pseudo_norm": "unsigned int func0(const char *a1, int a2) {\n int v2;\n unsigned int result;\n int v4;\n unsigned int i;\n unsigned int v6;\n if (a2)\n v2 = 5;\n else\n v2 = 21;\n v4 = v2;\n v6 = strlen(a1);\n for (i = 0LL;; ++i) {\n result = i;\n if (i >= v6) break;\n a1[i] = (v4 + a1[i] - 97) % 26 + 97;\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-50", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "void func0(char *s, int encode) {\n int shift = encode ? 5 : 21;\n size_t len = strlen(s);\n for (size_t i = 0; i < len; i++) {\n int w = ((s[i] - 'a' + shift) % 26) + 'a';\n s[i] = (char)w;\n }\n}", + "test": "#include \n#include \n#include \n#include \n#include \n\nint main() {\n srand((unsigned int)time(NULL));\n\n for (int i = 0; i < 100; i++) {\n int l = 10 + rand() % 11;\n char *str = (char *)malloc(l + 1);\n for (int j = 0; j < l; j++) {\n char chr = 'a' + rand() % 26;\n str[j] = chr;\n }\n str[l] = '\\0';\n\n char *encoded_str = (char *)malloc(l + 1);\n strcpy(encoded_str, str);\n func0(encoded_str, 1);\n func0(encoded_str, 0);\n assert(strcmp(encoded_str, str) == 0);\n\n free(str);\n free(encoded_str);\n }\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\ncmp esi, 1\nsbb ebx, ebx\nand ebx, 10h\nadd ebx, 5\ncall _strlen\ntest rax, rax\njz short loc_12A2\nmov rcx, rbp\nlea rdi, [rbp+rax+0]\nloc_1273:\nmovsx eax, byte ptr [rcx]\nlea edx, [rbx+rax-61h]\nmovsxd rax, edx\nimul rax, 4EC4EC4Fh\nsar rax, 23h\nmov esi, edx\nsar esi, 1Fh\nsub eax, esi\nimul eax, 1Ah\nsub edx, eax\nadd edx, 61h ; 'a'\nmov [rcx], dl\nadd rcx, 1\ncmp rcx, rdi\njnz short loc_1273\nloc_12A2:\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_pseudo": "size_t __fastcall func0(const char *a1, int a2)\n{\n size_t result; // rax\n char *v3; // rcx\n char *v4; // rdi\n int v5; // edx\n\n result = strlen(a1);\n if ( result )\n {\n v3 = (char *)a1;\n v4 = (char *)&a1[result];\n do\n {\n v5 = (a2 == 0 ? 21 : 5) + *v3 - 97;\n result = (unsigned int)(26 * (v5 / 26));\n *v3++ = v5 % 26 + 97;\n }\n while ( v3 != v4 );\n }\n return result;\n}", + "ida_strip_asm": "sub_1249:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\ncmp esi, 1\nsbb ebx, ebx\nand ebx, 10h\nadd ebx, 5\ncall _strlen\ntest rax, rax\njz short loc_12A2\nmov rcx, rbp\nlea rdi, [rbp+rax+0]\nloc_1273:\nmovsx eax, byte ptr [rcx]\nlea edx, [rbx+rax-61h]\nmovsxd rax, edx\nimul rax, 4EC4EC4Fh\nsar rax, 23h\nmov esi, edx\nsar esi, 1Fh\nsub eax, esi\nimul eax, 1Ah\nsub edx, eax\nadd edx, 61h ; 'a'\nmov [rcx], dl\nadd rcx, 1\ncmp rcx, rdi\njnz short loc_1273\nloc_12A2:\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "size_t __fastcall sub_1249(const char *a1, int a2)\n{\n size_t result; // rax\n char *v3; // rcx\n char *v4; // rdi\n int v5; // edx\n\n result = strlen(a1);\n if ( result )\n {\n v3 = (char *)a1;\n v4 = (char *)&a1[result];\n do\n {\n v5 = (a2 == 0 ? 21 : 5) + *v3 - 97;\n result = (unsigned int)(26 * (v5 / 26));\n *v3++ = v5 % 26 + 97;\n }\n while ( v3 != v4 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned int sub_1249(const char *a1, int a2) {\n unsigned int result;\n char *v3;\n char *v4;\n int v5;\n result = strlen(a1);\n if (result) {\n v3 = (char *)a1;\n v4 = (char *)&a1[result];\n do {\n v5 = (a2 == 0 ? 21 : 5) + *v3 - 97;\n result = (unsigned int)(26 * (v5 / 26));\n *v3++ = v5 % 26 + 97;\n } while (v3 != v4);\n }\n return result;\n}", + "ida_pseudo_norm": "unsigned int func0(const char *a1, int a2) {\n unsigned int result;\n char *v3;\n char *v4;\n int v5;\n result = strlen(a1);\n if (result) {\n v3 = (char *)a1;\n v4 = (char *)&a1[result];\n do {\n v5 = (a2 == 0 ? 21 : 5) + *v3 - 97;\n result = (unsigned int)(26 * (v5 / 26));\n *v3++ = v5 % 26 + 97;\n } while (v3 != v4);\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-50", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "void func0(char *s, int encode) {\n int shift = encode ? 5 : 21;\n size_t len = strlen(s);\n for (size_t i = 0; i < len; i++) {\n int w = ((s[i] - 'a' + shift) % 26) + 'a';\n s[i] = (char)w;\n }\n}", + "test": "#include \n#include \n#include \n#include \n#include \n\nint main() {\n srand((unsigned int)time(NULL));\n\n for (int i = 0; i < 100; i++) {\n int l = 10 + rand() % 11;\n char *str = (char *)malloc(l + 1);\n for (int j = 0; j < l; j++) {\n char chr = 'a' + rand() % 26;\n str[j] = chr;\n }\n str[l] = '\\0';\n\n char *encoded_str = (char *)malloc(l + 1);\n strcpy(encoded_str, str);\n func0(encoded_str, 1);\n func0(encoded_str, 0);\n assert(strcmp(encoded_str, str) == 0);\n\n free(str);\n free(encoded_str);\n }\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncmp esi, 1\nsbb ebp, ebp\nand ebp, 10h\nadd ebp, 5\ncall _strlen\ntest rax, rax\njz short loc_1460\nmov rdi, rbx\nadd rax, rbx\nnop dword ptr [rax+rax+00000000h]\nloc_1430:\nmovsx edx, byte ptr [rdi]\nadd rdi, 1\nlea ecx, [rbp+rdx-61h]\nmovsxd rdx, ecx\nmov esi, ecx\nimul rdx, 4EC4EC4Fh\nsar esi, 1Fh\nsar rdx, 23h\nsub edx, esi\nimul edx, 1Ah\nsub ecx, edx\nadd ecx, 61h ; 'a'\nmov [rdi-1], cl\ncmp rdi, rax\njnz short loc_1430\nloc_1460:\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_pseudo": "size_t __fastcall func0(const char *a1, int a2)\n{\n size_t result; // rax\n int v3; // edx\n\n result = strlen(a1);\n if ( result )\n {\n result += (size_t)a1;\n do\n {\n v3 = *a1++;\n *((_BYTE *)a1 - 1) = ((a2 == 0 ? 21 : 5) + v3 - 97) % 26 + 97;\n }\n while ( a1 != (const char *)result );\n }\n return result;\n}", + "ida_strip_asm": "sub_1400:\nendbr64\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncmp esi, 1\nsbb ebp, ebp\nand ebp, 10h\nadd ebp, 5\ncall _strlen\ntest rax, rax\njz short loc_1460\nmov rdi, rbx\nadd rax, rbx\nnop dword ptr [rax+rax+00000000h]\nloc_1430:\nmovsx edx, byte ptr [rdi]\nadd rdi, 1\nlea ecx, [rbp+rdx-61h]\nmovsxd rdx, ecx\nmov esi, ecx\nimul rdx, 4EC4EC4Fh\nsar esi, 1Fh\nsar rdx, 23h\nsub edx, esi\nimul edx, 1Ah\nsub ecx, edx\nadd ecx, 61h ; 'a'\nmov [rdi-1], cl\ncmp rdi, rax\njnz short loc_1430\nloc_1460:\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "size_t __fastcall sub_1400(const char *a1, int a2)\n{\n size_t result; // rax\n int v3; // edx\n\n result = strlen(a1);\n if ( result )\n {\n result += (size_t)a1;\n do\n {\n v3 = *a1++;\n *((_BYTE *)a1 - 1) = ((a2 == 0 ? 21 : 5) + v3 - 97) % 26 + 97;\n }\n while ( a1 != (const char *)result );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned int sub_1400(const char *a1, int a2) {\n unsigned int result;\n int v3;\n result = strlen(a1);\n if (result) {\n result += (unsigned int)a1;\n do {\n v3 = *a1++;\n *((uint8_t *)a1 - 1) = ((a2 == 0 ? 21 : 5) + v3 - 97) % 26 + 97;\n } while (a1 != (const char *)result);\n }\n return result;\n}", + "ida_pseudo_norm": "unsigned int func0(const char *a1, int a2) {\n unsigned int result;\n int v3;\n result = strlen(a1);\n if (result) {\n result += (unsigned int)a1;\n do {\n v3 = *a1++;\n *((uint8_t *)a1 - 1) = ((a2 == 0 ? 21 : 5) + v3 - 97) % 26 + 97;\n } while (a1 != (const char *)result);\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-50", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "void func0(char *s, int encode) {\n int shift = encode ? 5 : 21;\n size_t len = strlen(s);\n for (size_t i = 0; i < len; i++) {\n int w = ((s[i] - 'a' + shift) % 26) + 'a';\n s[i] = (char)w;\n }\n}", + "test": "#include \n#include \n#include \n#include \n#include \n\nint main() {\n srand((unsigned int)time(NULL));\n\n for (int i = 0; i < 100; i++) {\n int l = 10 + rand() % 11;\n char *str = (char *)malloc(l + 1);\n for (int j = 0; j < l; j++) {\n char chr = 'a' + rand() % 26;\n str[j] = chr;\n }\n str[l] = '\\0';\n\n char *encoded_str = (char *)malloc(l + 1);\n strcpy(encoded_str, str);\n func0(encoded_str, 1);\n func0(encoded_str, 0);\n assert(strcmp(encoded_str, str) == 0);\n\n free(str);\n free(encoded_str);\n }\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 8\ncmp esi, 1\nsbb ebx, ebx\nand ebx, 10h\nadd ebx, 5\ncall _strlen\ntest rax, rax\njz loc_294C\nmov rdx, rax\nlea rax, [rax-1]\ncmp rax, 0Eh\njbe loc_2953\npxor xmm5, xmm5\nmovd xmm7, ebx\nmov rcx, rdx\nmov rax, rbp\nmovdqa xmm4, cs:xmmword_3060\nmovdqa xmm6, xmm5\npunpcklwd xmm7, xmm7\nand rcx, 0FFFFFFFFFFFFFFF0h\npshufd xmm7, xmm7, 0\nlea rsi, [rbp+rcx+0]\npxor xmm10, xmm10\nmovdqa xmm9, cs:xmmword_3070\npcmpgtd xmm6, xmm4\npaddw xmm7, cs:xmmword_3050\npxor xmm8, xmm8\nmovdqa xmm11, cs:xmmword_3080\nnop dword ptr [rax+rax+00h]\nloc_2270:\nmovdqu xmm2, xmmword ptr [rax]\nmovdqa xmm0, xmm10\nmovdqa xmm3, xmm8\nmovdqa xmm13, xmm5\nmovdqa xmm12, xmm8\nmovdqa xmm14, xmm6\nmovdqa xmm15, xmm6\nadd rax, 10h\npcmpgtb xmm0, xmm2\nmovdqa xmm1, xmm2\npunpcklbw xmm1, xmm0\npunpckhbw xmm2, xmm0\npaddw xmm1, xmm7\npaddw xmm2, xmm7\npcmpgtw xmm3, xmm1\npcmpgtw xmm12, xmm2\nmovdqa xmm0, xmm1\npunpcklwd xmm0, xmm3\npunpckhwd xmm1, xmm3\nmovdqa xmm3, xmm2\npcmpgtd xmm13, xmm0\npmuludq xmm14, xmm0\npunpcklwd xmm3, xmm12\npunpckhwd xmm2, xmm12\nmovdqa xmm12, xmm0\npmuludq xmm12, xmm4\npmuludq xmm13, xmm4\npaddq xmm13, xmm14\nmovdqa xmm14, xmm5\npsllq xmm13, 20h ; ' '\npaddq xmm12, xmm13\nmovdqa xmm13, xmm0\npsrlq xmm13, 20h ; ' '\npcmpgtd xmm14, xmm13\npmuludq xmm15, xmm13\npmuludq xmm13, xmm4\npmuludq xmm14, xmm4\npaddq xmm14, xmm15\nmovdqa xmm15, xmm6\npsllq xmm14, 20h ; ' '\npaddq xmm13, xmm14\nmovdqa xmm14, xmm6\nshufps xmm12, xmm13, 0DDh\nmovdqa xmm13, xmm0\npshufd xmm12, xmm12, 0D8h\npsrad xmm13, 1Fh\npsrad xmm12, 3\npsubd xmm12, xmm13\npmuludq xmm14, xmm1\nmovdqa xmm13, xmm12\npslld xmm13, 1\npaddd xmm13, xmm12\npslld xmm13, 2\npaddd xmm12, xmm13\nmovdqa xmm13, xmm5\npcmpgtd xmm13, xmm1\npslld xmm12, 1\npsubd xmm0, xmm12\nmovdqa xmm12, xmm1\npmuludq xmm12, xmm4\npmuludq xmm13, xmm4\npaddq xmm13, xmm14\nmovdqa xmm14, xmm5\npsllq xmm13, 20h ; ' '\npaddq xmm12, xmm13\nmovdqa xmm13, xmm1\npsrlq xmm13, 20h ; ' '\npcmpgtd xmm14, xmm13\npmuludq xmm15, xmm13\npmuludq xmm13, xmm4\npmuludq xmm14, xmm4\npaddq xmm14, xmm15\npsllq xmm14, 20h ; ' '\npaddq xmm13, xmm14\nmovdqa xmm14, xmm6\nshufps xmm12, xmm13, 0DDh\nmovdqa xmm13, xmm1\npshufd xmm12, xmm12, 0D8h\npsrad xmm13, 1Fh\npsrad xmm12, 3\npsubd xmm12, xmm13\nmovdqa xmm13, xmm12\npslld xmm13, 1\npaddd xmm13, xmm12\npslld xmm13, 2\npaddd xmm12, xmm13\nmovdqa xmm13, xmm6\npslld xmm12, 1\npmuludq xmm13, xmm3\npsubd xmm1, xmm12\nmovdqa xmm12, xmm0\npunpcklwd xmm0, xmm1\npunpckhwd xmm12, xmm1\nmovdqa xmm1, xmm0\npunpcklwd xmm0, xmm12\npunpckhwd xmm1, xmm12\nmovdqa xmm12, xmm5\npcmpgtd xmm12, xmm3\npunpcklwd xmm0, xmm1\nmovdqa xmm1, xmm3\npmuludq xmm1, xmm4\npand xmm0, xmm9\npmuludq xmm12, xmm4\npaddq xmm12, xmm13\nmovdqa xmm13, xmm5\npsllq xmm12, 20h ; ' '\npaddq xmm1, xmm12\nmovdqa xmm12, xmm3\npsrlq xmm12, 20h ; ' '\npcmpgtd xmm13, xmm12\npmuludq xmm14, xmm12\npmuludq xmm12, xmm4\npmuludq xmm13, xmm4\npaddq xmm13, xmm14\nmovdqa xmm14, xmm6\npsllq xmm13, 20h ; ' '\npaddq xmm12, xmm13\nmovdqa xmm13, xmm6\nshufps xmm1, xmm12, 0DDh\nmovdqa xmm12, xmm3\npshufd xmm1, xmm1, 0D8h\npsrad xmm12, 1Fh\npsrad xmm1, 3\npsubd xmm1, xmm12\npmuludq xmm13, xmm2\nmovdqa xmm12, xmm1\npslld xmm12, 1\npaddd xmm12, xmm1\npslld xmm12, 2\npaddd xmm12, xmm1\nmovdqa xmm1, xmm3\nmovdqa xmm3, xmm5\npcmpgtd xmm3, xmm2\npslld xmm12, 1\npsubd xmm1, xmm12\nmovdqa xmm12, xmm2\npmuludq xmm12, xmm4\npmuludq xmm3, xmm4\npaddq xmm3, xmm13\nmovdqa xmm13, xmm5\npsllq xmm3, 20h ; ' '\npaddq xmm12, xmm3\nmovdqa xmm3, xmm2\npsrlq xmm3, 20h ; ' '\npcmpgtd xmm13, xmm3\npmuludq xmm14, xmm3\npmuludq xmm3, xmm4\npmuludq xmm13, xmm4\npaddq xmm13, xmm14\npsllq xmm13, 20h ; ' '\npaddq xmm3, xmm13\nshufps xmm12, xmm3, 0DDh\nmovdqa xmm3, xmm2\npshufd xmm12, xmm12, 0D8h\npsrad xmm3, 1Fh\npsrad xmm12, 3\npsubd xmm12, xmm3\nmovdqa xmm3, xmm12\npslld xmm3, 1\npaddd xmm3, xmm12\npslld xmm3, 2\npaddd xmm3, xmm12\npslld xmm3, 1\npsubd xmm2, xmm3\nmovdqa xmm3, xmm1\npunpcklwd xmm1, xmm2\npunpckhwd xmm3, xmm2\nmovdqa xmm2, xmm1\npunpcklwd xmm1, xmm3\npunpckhwd xmm2, xmm3\npunpcklwd xmm1, xmm2\npand xmm1, xmm9\npackuswb xmm0, xmm1\npaddb xmm0, xmm11\nmovups xmmword ptr [rax-10h], xmm0\ncmp rsi, rax\njnz loc_2270\ncmp rdx, rcx\njz loc_294C\nloc_25E6:\nmovsx eax, byte ptr [rsi]\nlea edi, [rbx+rax-61h]\nmovsxd rax, edi\nmov r8d, edi\nimul rax, 4EC4EC4Fh\nsar r8d, 1Fh\nsar rax, 23h\nsub eax, r8d\nimul eax, 1Ah\nsub edi, eax\nlea rax, [rcx+1]\nadd edi, 61h ; 'a'\nmov [rsi], dil\ncmp rax, rdx\njnb loc_294C\nlea rdi, [rbp+rax+0]\nmovsx eax, byte ptr [rdi]\nlea esi, [rbx+rax-61h]\nmovsxd rax, esi\nmov r8d, esi\nimul rax, 4EC4EC4Fh\nsar r8d, 1Fh\nsar rax, 23h\nsub eax, r8d\nimul eax, 1Ah\nsub esi, eax\nlea rax, [rcx+2]\nadd esi, 61h ; 'a'\nmov [rdi], sil\ncmp rax, rdx\njnb loc_294C\nlea rdi, [rbp+rax+0]\nmovsx eax, byte ptr [rdi]\nlea esi, [rbx+rax-61h]\nmovsxd rax, esi\nmov r8d, esi\nimul rax, 4EC4EC4Fh\nsar r8d, 1Fh\nsar rax, 23h\nsub eax, r8d\nimul eax, 1Ah\nsub esi, eax\nlea rax, [rcx+3]\nadd esi, 61h ; 'a'\nmov [rdi], sil\ncmp rax, rdx\njnb loc_294C\nlea rdi, [rbp+rax+0]\nmovsx eax, byte ptr [rdi]\nlea esi, [rbx+rax-61h]\nmovsxd rax, esi\nmov r8d, esi\nimul rax, 4EC4EC4Fh\nsar r8d, 1Fh\nsar rax, 23h\nsub eax, r8d\nimul eax, 1Ah\nsub esi, eax\nlea rax, [rcx+4]\nadd esi, 61h ; 'a'\nmov [rdi], sil\ncmp rax, rdx\njnb loc_294C\nlea rdi, [rbp+rax+0]\nmovsx eax, byte ptr [rdi]\nlea esi, [rbx+rax-61h]\nmovsxd rax, esi\nmov r8d, esi\nimul rax, 4EC4EC4Fh\nsar r8d, 1Fh\nsar rax, 23h\nsub eax, r8d\nimul eax, 1Ah\nsub esi, eax\nlea rax, [rcx+5]\nadd esi, 61h ; 'a'\nmov [rdi], sil\ncmp rax, rdx\njnb loc_294C\nlea rdi, [rbp+rax+0]\nmovsx eax, byte ptr [rdi]\nlea esi, [rbx+rax-61h]\nmovsxd rax, esi\nmov r8d, esi\nimul rax, 4EC4EC4Fh\nsar r8d, 1Fh\nsar rax, 23h\nsub eax, r8d\nimul eax, 1Ah\nsub esi, eax\nlea rax, [rcx+6]\nadd esi, 61h ; 'a'\nmov [rdi], sil\ncmp rax, rdx\njnb loc_294C\nlea rdi, [rbp+rax+0]\nmovsx eax, byte ptr [rdi]\nlea esi, [rbx+rax-61h]\nmovsxd rax, esi\nmov r8d, esi\nimul rax, 4EC4EC4Fh\nsar r8d, 1Fh\nsar rax, 23h\nsub eax, r8d\nimul eax, 1Ah\nsub esi, eax\nlea rax, [rcx+7]\nadd esi, 61h ; 'a'\nmov [rdi], sil\ncmp rax, rdx\njnb loc_294C\nlea rdi, [rbp+rax+0]\nmovsx eax, byte ptr [rdi]\nlea esi, [rbx+rax-61h]\nmovsxd rax, esi\nmov r8d, esi\nimul rax, 4EC4EC4Fh\nsar r8d, 1Fh\nsar rax, 23h\nsub eax, r8d\nimul eax, 1Ah\nsub esi, eax\nlea rax, [rcx+8]\nadd esi, 61h ; 'a'\nmov [rdi], sil\ncmp rax, rdx\njnb loc_294C\nlea rdi, [rbp+rax+0]\nmovsx eax, byte ptr [rdi]\nlea esi, [rbx+rax-61h]\nmovsxd rax, esi\nmov r8d, esi\nimul rax, 4EC4EC4Fh\nsar r8d, 1Fh\nsar rax, 23h\nsub eax, r8d\nimul eax, 1Ah\nsub esi, eax\nlea rax, [rcx+9]\nadd esi, 61h ; 'a'\nmov [rdi], sil\ncmp rax, rdx\njnb loc_294C\nlea rdi, [rbp+rax+0]\nmovsx eax, byte ptr [rdi]\nlea esi, [rbx+rax-61h]\nmovsxd rax, esi\nmov r8d, esi\nimul rax, 4EC4EC4Fh\nsar r8d, 1Fh\nsar rax, 23h\nsub eax, r8d\nimul eax, 1Ah\nsub esi, eax\nlea rax, [rcx+0Ah]\nadd esi, 61h ; 'a'\nmov [rdi], sil\ncmp rax, rdx\njnb loc_294C\nlea rdi, [rbp+rax+0]\nmovsx eax, byte ptr [rdi]\nlea esi, [rbx+rax-61h]\nmovsxd rax, esi\nmov r8d, esi\nimul rax, 4EC4EC4Fh\nsar r8d, 1Fh\nsar rax, 23h\nsub eax, r8d\nimul eax, 1Ah\nsub esi, eax\nlea rax, [rcx+0Bh]\nadd esi, 61h ; 'a'\nmov [rdi], sil\ncmp rax, rdx\njnb loc_294C\nlea rdi, [rbp+rax+0]\nmovsx eax, byte ptr [rdi]\nlea esi, [rbx+rax-61h]\nmovsxd rax, esi\nmov r8d, esi\nimul rax, 4EC4EC4Fh\nsar r8d, 1Fh\nsar rax, 23h\nsub eax, r8d\nimul eax, 1Ah\nsub esi, eax\nlea rax, [rcx+0Ch]\nadd esi, 61h ; 'a'\nmov [rdi], sil\ncmp rax, rdx\njnb loc_294C\nlea rdi, [rbp+rax+0]\nmovsx eax, byte ptr [rdi]\nlea esi, [rbx+rax-61h]\nmovsxd rax, esi\nmov r8d, esi\nimul rax, 4EC4EC4Fh\nsar r8d, 1Fh\nsar rax, 23h\nsub eax, r8d\nimul eax, 1Ah\nsub esi, eax\nlea rax, [rcx+0Dh]\nadd esi, 61h ; 'a'\nmov [rdi], sil\ncmp rax, rdx\njnb short loc_294C\nlea rdi, [rbp+rax+0]\nadd rcx, 0Eh\nmovsx eax, byte ptr [rdi]\nlea esi, [rbx+rax-61h]\nmovsxd rax, esi\nmov r8d, esi\nimul rax, 4EC4EC4Fh\nsar r8d, 1Fh\nsar rax, 23h\nsub eax, r8d\nimul eax, 1Ah\nsub esi, eax\nadd esi, 61h ; 'a'\nmov [rdi], sil\ncmp rcx, rdx\njnb short loc_294C\nadd rbp, rcx\nmovsx eax, byte ptr [rbp+0]\nlea edx, [rbx+rax-61h]\nmovsxd rax, edx\nmov ecx, edx\nimul rax, 4EC4EC4Fh\nsar ecx, 1Fh\nsar rax, 23h\nsub eax, ecx\nimul eax, 1Ah\nsub edx, eax\nadd edx, 61h ; 'a'\nmov [rbp+0], dl\nloc_294C:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_2953:\nxor ecx, ecx\nmov rsi, rbp\njmp loc_25E6", + "ida_pseudo": "size_t __fastcall func0(const char *a1, int a2)\n{\n unsigned int v3; // ebx\n size_t result; // rax\n unsigned __int64 v5; // rdx\n __m128i v6; // xmm7\n __m128i si128; // xmm4\n unsigned __int64 v8; // rcx\n char *v9; // rsi\n __m128i v10; // xmm9\n __m128i v11; // xmm6\n __m128i v12; // xmm7\n __m128i v13; // xmm11\n __m128i v14; // xmm2\n __m128i v15; // xmm0\n __m128i v16; // xmm1\n __m128i v17; // xmm2\n __m128i v18; // xmm3\n __m128i v19; // xmm12\n __m128i v20; // xmm0\n __m128i v21; // xmm1\n __m128i v22; // xmm3\n __m128i v23; // xmm2\n __m128i v24; // xmm13\n __m128i v25; // xmm12\n __m128i v26; // xmm0\n __m128i v27; // xmm13\n __m128i v28; // xmm12\n __m128i v29; // xmm1\n __m128i v30; // xmm12\n __m128i v31; // xmm1\n __m128i v32; // xmm0\n __m128i v33; // xmm12\n __m128i v34; // xmm1\n __m128i v35; // xmm1\n __m128i v36; // xmm3\n __m128i v37; // xmm12\n __m128i v38; // xmm2\n __m128i v39; // xmm3\n __m128i v40; // xmm2\n char *v41; // rdi\n int v42; // esi\n char *v43; // rdi\n int v44; // esi\n char *v45; // rdi\n int v46; // esi\n char *v47; // rdi\n int v48; // esi\n char *v49; // rdi\n int v50; // esi\n char *v51; // rdi\n int v52; // esi\n char *v53; // rdi\n int v54; // esi\n char *v55; // rdi\n int v56; // esi\n char *v57; // rdi\n int v58; // esi\n char *v59; // rdi\n int v60; // esi\n char *v61; // rdi\n int v62; // esi\n char *v63; // rdi\n int v64; // esi\n char *v65; // rdi\n unsigned __int64 v66; // rcx\n int v67; // esi\n char *v68; // rbp\n int v69; // edx\n\n v3 = a2 == 0 ? 21 : 5;\n result = strlen(a1);\n if ( result )\n {\n v5 = result;\n if ( result - 1 <= 0xE )\n {\n v8 = 0LL;\n v9 = (char *)a1;\n }\n else\n {\n v6 = _mm_cvtsi32_si128(v3);\n result = (size_t)a1;\n si128 = _mm_load_si128((const __m128i *)&xmmword_3060);\n v8 = v5 & 0xFFFFFFFFFFFFFFF0LL;\n v9 = (char *)&a1[v5 & 0xFFFFFFFFFFFFFFF0LL];\n v10 = _mm_load_si128((const __m128i *)&xmmword_3070);\n v11 = _mm_cmpgt_epi32((__m128i)0LL, si128);\n v12 = _mm_add_epi16(_mm_shuffle_epi32(_mm_unpacklo_epi16(v6, v6), 0), (__m128i)xmmword_3050);\n v13 = _mm_load_si128((const __m128i *)&xmmword_3080);\n do\n {\n v14 = _mm_loadu_si128((const __m128i *)result);\n result += 16LL;\n v15 = _mm_cmpgt_epi8((__m128i)0LL, v14);\n v16 = _mm_add_epi16(_mm_unpacklo_epi8(v14, v15), v12);\n v17 = _mm_add_epi16(_mm_unpackhi_epi8(v14, v15), v12);\n v18 = _mm_cmpgt_epi16((__m128i)0LL, v16);\n v19 = _mm_cmpgt_epi16((__m128i)0LL, v17);\n v20 = _mm_unpacklo_epi16(v16, v18);\n v21 = _mm_unpackhi_epi16(v16, v18);\n v22 = _mm_unpacklo_epi16(v17, v19);\n v23 = _mm_unpackhi_epi16(v17, v19);\n v24 = _mm_srli_epi64(v20, 0x20u);\n v25 = _mm_sub_epi32(\n _mm_srai_epi32(\n _mm_shuffle_epi32(\n (__m128i)_mm_shuffle_ps(\n (__m128)_mm_add_epi64(\n _mm_mul_epu32(v20, si128),\n _mm_slli_epi64(\n _mm_add_epi64(\n _mm_mul_epu32(_mm_cmpgt_epi32((__m128i)0LL, v20), si128),\n _mm_mul_epu32(v11, v20)),\n 0x20u)),\n (__m128)_mm_add_epi64(\n _mm_mul_epu32(v24, si128),\n _mm_slli_epi64(\n _mm_add_epi64(\n _mm_mul_epu32(_mm_cmpgt_epi32((__m128i)0LL, v24), si128),\n _mm_mul_epu32(v11, v24)),\n 0x20u)),\n 221),\n 216),\n 3u),\n _mm_srai_epi32(v20, 0x1Fu));\n v26 = _mm_sub_epi32(\n v20,\n _mm_slli_epi32(_mm_add_epi32(v25, _mm_slli_epi32(_mm_add_epi32(_mm_slli_epi32(v25, 1u), v25), 2u)), 1u));\n v27 = _mm_srli_epi64(v21, 0x20u);\n v28 = _mm_sub_epi32(\n _mm_srai_epi32(\n _mm_shuffle_epi32(\n (__m128i)_mm_shuffle_ps(\n (__m128)_mm_add_epi64(\n _mm_mul_epu32(v21, si128),\n _mm_slli_epi64(\n _mm_add_epi64(\n _mm_mul_epu32(_mm_cmpgt_epi32((__m128i)0LL, v21), si128),\n _mm_mul_epu32(v11, v21)),\n 0x20u)),\n (__m128)_mm_add_epi64(\n _mm_mul_epu32(v27, si128),\n _mm_slli_epi64(\n _mm_add_epi64(\n _mm_mul_epu32(_mm_cmpgt_epi32((__m128i)0LL, v27), si128),\n _mm_mul_epu32(v11, v27)),\n 0x20u)),\n 221),\n 216),\n 3u),\n _mm_srai_epi32(v21, 0x1Fu));\n v29 = _mm_sub_epi32(\n v21,\n _mm_slli_epi32(_mm_add_epi32(v28, _mm_slli_epi32(_mm_add_epi32(_mm_slli_epi32(v28, 1u), v28), 2u)), 1u));\n v30 = _mm_unpackhi_epi16(v26, v29);\n v31 = _mm_unpacklo_epi16(v26, v29);\n v32 = _mm_unpacklo_epi16(_mm_unpacklo_epi16(v31, v30), _mm_unpackhi_epi16(v31, v30));\n v33 = _mm_srli_epi64(v22, 0x20u);\n v34 = _mm_sub_epi32(\n _mm_srai_epi32(\n _mm_shuffle_epi32(\n (__m128i)_mm_shuffle_ps(\n (__m128)_mm_add_epi64(\n _mm_mul_epu32(v22, si128),\n _mm_slli_epi64(\n _mm_add_epi64(\n _mm_mul_epu32(_mm_cmpgt_epi32((__m128i)0LL, v22), si128),\n _mm_mul_epu32(v11, v22)),\n 0x20u)),\n (__m128)_mm_add_epi64(\n _mm_mul_epu32(v33, si128),\n _mm_slli_epi64(\n _mm_add_epi64(\n _mm_mul_epu32(_mm_cmpgt_epi32((__m128i)0LL, v33), si128),\n _mm_mul_epu32(v11, v33)),\n 0x20u)),\n 221),\n 216),\n 3u),\n _mm_srai_epi32(v22, 0x1Fu));\n v35 = _mm_sub_epi32(\n v22,\n _mm_slli_epi32(_mm_add_epi32(_mm_slli_epi32(_mm_add_epi32(_mm_slli_epi32(v34, 1u), v34), 2u), v34), 1u));\n v36 = _mm_srli_epi64(v23, 0x20u);\n v37 = _mm_sub_epi32(\n _mm_srai_epi32(\n _mm_shuffle_epi32(\n (__m128i)_mm_shuffle_ps(\n (__m128)_mm_add_epi64(\n _mm_mul_epu32(v23, si128),\n _mm_slli_epi64(\n _mm_add_epi64(\n _mm_mul_epu32(_mm_cmpgt_epi32((__m128i)0LL, v23), si128),\n _mm_mul_epu32(v11, v23)),\n 0x20u)),\n (__m128)_mm_add_epi64(\n _mm_mul_epu32(v36, si128),\n _mm_slli_epi64(\n _mm_add_epi64(\n _mm_mul_epu32(_mm_cmpgt_epi32((__m128i)0LL, v36), si128),\n _mm_mul_epu32(v11, v36)),\n 0x20u)),\n 221),\n 216),\n 3u),\n _mm_srai_epi32(v23, 0x1Fu));\n v38 = _mm_sub_epi32(\n v23,\n _mm_slli_epi32(_mm_add_epi32(_mm_slli_epi32(_mm_add_epi32(_mm_slli_epi32(v37, 1u), v37), 2u), v37), 1u));\n v39 = _mm_unpackhi_epi16(v35, v38);\n v40 = _mm_unpacklo_epi16(v35, v38);\n *(__m128i *)(result - 16) = _mm_add_epi8(\n _mm_packus_epi16(\n _mm_and_si128(v32, v10),\n _mm_and_si128(\n _mm_unpacklo_epi16(_mm_unpacklo_epi16(v40, v39), _mm_unpackhi_epi16(v40, v39)),\n v10)),\n v13);\n }\n while ( v9 != (char *)result );\n if ( v5 == v8 )\n return result;\n }\n result = v8 + 1;\n *v9 = (int)(v3 + *v9 - 97) % 26 + 97;\n if ( v8 + 1 < v5 )\n {\n v41 = (char *)&a1[result];\n v42 = v3 + a1[result] - 97;\n result = v8 + 2;\n *v41 = v42 % 26 + 97;\n if ( v8 + 2 < v5 )\n {\n v43 = (char *)&a1[result];\n v44 = v3 + a1[result] - 97;\n result = v8 + 3;\n *v43 = v44 % 26 + 97;\n if ( v8 + 3 < v5 )\n {\n v45 = (char *)&a1[result];\n v46 = v3 + a1[result] - 97;\n result = v8 + 4;\n *v45 = v46 % 26 + 97;\n if ( v8 + 4 < v5 )\n {\n v47 = (char *)&a1[result];\n v48 = v3 + a1[result] - 97;\n result = v8 + 5;\n *v47 = v48 % 26 + 97;\n if ( v8 + 5 < v5 )\n {\n v49 = (char *)&a1[result];\n v50 = v3 + a1[result] - 97;\n result = v8 + 6;\n *v49 = v50 % 26 + 97;\n if ( v8 + 6 < v5 )\n {\n v51 = (char *)&a1[result];\n v52 = v3 + a1[result] - 97;\n result = v8 + 7;\n *v51 = v52 % 26 + 97;\n if ( v8 + 7 < v5 )\n {\n v53 = (char *)&a1[result];\n v54 = v3 + a1[result] - 97;\n result = v8 + 8;\n *v53 = v54 % 26 + 97;\n if ( v8 + 8 < v5 )\n {\n v55 = (char *)&a1[result];\n v56 = v3 + a1[result] - 97;\n result = v8 + 9;\n *v55 = v56 % 26 + 97;\n if ( v8 + 9 < v5 )\n {\n v57 = (char *)&a1[result];\n v58 = v3 + a1[result] - 97;\n result = v8 + 10;\n *v57 = v58 % 26 + 97;\n if ( v8 + 10 < v5 )\n {\n v59 = (char *)&a1[result];\n v60 = v3 + a1[result] - 97;\n result = v8 + 11;\n *v59 = v60 % 26 + 97;\n if ( v8 + 11 < v5 )\n {\n v61 = (char *)&a1[result];\n v62 = v3 + a1[result] - 97;\n result = v8 + 12;\n *v61 = v62 % 26 + 97;\n if ( v8 + 12 < v5 )\n {\n v63 = (char *)&a1[result];\n v64 = v3 + a1[result] - 97;\n result = v8 + 13;\n *v63 = v64 % 26 + 97;\n if ( v8 + 13 < v5 )\n {\n v65 = (char *)&a1[result];\n v66 = v8 + 14;\n v67 = v3 + a1[result] - 97;\n result = (unsigned int)(26 * (v67 / 26));\n *v65 = v67 % 26 + 97;\n if ( v66 < v5 )\n {\n v68 = (char *)&a1[v66];\n v69 = v3 + *v68 - 97;\n result = (unsigned int)(26 * (v69 / 26));\n *v68 = v69 % 26 + 97;\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_21E0:\nendbr64\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 8\ncmp esi, 1\nsbb ebx, ebx\nand ebx, 10h\nadd ebx, 5\ncall _strlen\ntest rax, rax\njz loc_294C\nmov rdx, rax\nlea rax, [rax-1]\ncmp rax, 0Eh\njbe loc_2953\npxor xmm5, xmm5\nmovd xmm7, ebx\nmov rcx, rdx\nmov rax, rbp\nmovdqa xmm4, cs:xmmword_3060\nmovdqa xmm6, xmm5\npunpcklwd xmm7, xmm7\nand rcx, 0FFFFFFFFFFFFFFF0h\npshufd xmm7, xmm7, 0\nlea rsi, [rbp+rcx+0]\npxor xmm10, xmm10\nmovdqa xmm9, cs:xmmword_3070\npcmpgtd xmm6, xmm4\npaddw xmm7, cs:xmmword_3050\npxor xmm8, xmm8\nmovdqa xmm11, cs:xmmword_3080\nnop dword ptr [rax+rax+00h]\nloc_2270:\nmovdqu xmm2, xmmword ptr [rax]\nmovdqa xmm0, xmm10\nmovdqa xmm3, xmm8\nmovdqa xmm13, xmm5\nmovdqa xmm12, xmm8\nmovdqa xmm14, xmm6\nmovdqa xmm15, xmm6\nadd rax, 10h\npcmpgtb xmm0, xmm2\nmovdqa xmm1, xmm2\npunpcklbw xmm1, xmm0\npunpckhbw xmm2, xmm0\npaddw xmm1, xmm7\npaddw xmm2, xmm7\npcmpgtw xmm3, xmm1\npcmpgtw xmm12, xmm2\nmovdqa xmm0, xmm1\npunpcklwd xmm0, xmm3\npunpckhwd xmm1, xmm3\nmovdqa xmm3, xmm2\npcmpgtd xmm13, xmm0\npmuludq xmm14, xmm0\npunpcklwd xmm3, xmm12\npunpckhwd xmm2, xmm12\nmovdqa xmm12, xmm0\npmuludq xmm12, xmm4\npmuludq xmm13, xmm4\npaddq xmm13, xmm14\nmovdqa xmm14, xmm5\npsllq xmm13, 20h ; ' '\npaddq xmm12, xmm13\nmovdqa xmm13, xmm0\npsrlq xmm13, 20h ; ' '\npcmpgtd xmm14, xmm13\npmuludq xmm15, xmm13\npmuludq xmm13, xmm4\npmuludq xmm14, xmm4\npaddq xmm14, xmm15\nmovdqa xmm15, xmm6\npsllq xmm14, 20h ; ' '\npaddq xmm13, xmm14\nmovdqa xmm14, xmm6\nshufps xmm12, xmm13, 0DDh\nmovdqa xmm13, xmm0\npshufd xmm12, xmm12, 0D8h\npsrad xmm13, 1Fh\npsrad xmm12, 3\npsubd xmm12, xmm13\npmuludq xmm14, xmm1\nmovdqa xmm13, xmm12\npslld xmm13, 1\npaddd xmm13, xmm12\npslld xmm13, 2\npaddd xmm12, xmm13\nmovdqa xmm13, xmm5\npcmpgtd xmm13, xmm1\npslld xmm12, 1\npsubd xmm0, xmm12\nmovdqa xmm12, xmm1\npmuludq xmm12, xmm4\npmuludq xmm13, xmm4\npaddq xmm13, xmm14\nmovdqa xmm14, xmm5\npsllq xmm13, 20h ; ' '\npaddq xmm12, xmm13\nmovdqa xmm13, xmm1\npsrlq xmm13, 20h ; ' '\npcmpgtd xmm14, xmm13\npmuludq xmm15, xmm13\npmuludq xmm13, xmm4\npmuludq xmm14, xmm4\npaddq xmm14, xmm15\npsllq xmm14, 20h ; ' '\npaddq xmm13, xmm14\nmovdqa xmm14, xmm6\nshufps xmm12, xmm13, 0DDh\nmovdqa xmm13, xmm1\npshufd xmm12, xmm12, 0D8h\npsrad xmm13, 1Fh\npsrad xmm12, 3\npsubd xmm12, xmm13\nmovdqa xmm13, xmm12\npslld xmm13, 1\npaddd xmm13, xmm12\npslld xmm13, 2\npaddd xmm12, xmm13\nmovdqa xmm13, xmm6\npslld xmm12, 1\npmuludq xmm13, xmm3\npsubd xmm1, xmm12\nmovdqa xmm12, xmm0\npunpcklwd xmm0, xmm1\npunpckhwd xmm12, xmm1\nmovdqa xmm1, xmm0\npunpcklwd xmm0, xmm12\npunpckhwd xmm1, xmm12\nmovdqa xmm12, xmm5\npcmpgtd xmm12, xmm3\npunpcklwd xmm0, xmm1\nmovdqa xmm1, xmm3\npmuludq xmm1, xmm4\npand xmm0, xmm9\npmuludq xmm12, xmm4\npaddq xmm12, xmm13\nmovdqa xmm13, xmm5\npsllq xmm12, 20h ; ' '\npaddq xmm1, xmm12\nmovdqa xmm12, xmm3\npsrlq xmm12, 20h ; ' '\npcmpgtd xmm13, xmm12\npmuludq xmm14, xmm12\npmuludq xmm12, xmm4\npmuludq xmm13, xmm4\npaddq xmm13, xmm14\nmovdqa xmm14, xmm6\npsllq xmm13, 20h ; ' '\npaddq xmm12, xmm13\nmovdqa xmm13, xmm6\nshufps xmm1, xmm12, 0DDh\nmovdqa xmm12, xmm3\npshufd xmm1, xmm1, 0D8h\npsrad xmm12, 1Fh\npsrad xmm1, 3\npsubd xmm1, xmm12\npmuludq xmm13, xmm2\nmovdqa xmm12, xmm1\npslld xmm12, 1\npaddd xmm12, xmm1\npslld xmm12, 2\npaddd xmm12, xmm1\nmovdqa xmm1, xmm3\nmovdqa xmm3, xmm5\npcmpgtd xmm3, xmm2\npslld xmm12, 1\npsubd xmm1, xmm12\nmovdqa xmm12, xmm2\npmuludq xmm12, xmm4\npmuludq xmm3, xmm4\npaddq xmm3, xmm13\nmovdqa xmm13, xmm5\npsllq xmm3, 20h ; ' '\npaddq xmm12, xmm3\nmovdqa xmm3, xmm2\npsrlq xmm3, 20h ; ' '\npcmpgtd xmm13, xmm3\npmuludq xmm14, xmm3\npmuludq xmm3, xmm4\npmuludq xmm13, xmm4\npaddq xmm13, xmm14\npsllq xmm13, 20h ; ' '\npaddq xmm3, xmm13\nshufps xmm12, xmm3, 0DDh\nmovdqa xmm3, xmm2\npshufd xmm12, xmm12, 0D8h\npsrad xmm3, 1Fh\npsrad xmm12, 3\npsubd xmm12, xmm3\nmovdqa xmm3, xmm12\npslld xmm3, 1\npaddd xmm3, xmm12\npslld xmm3, 2\npaddd xmm3, xmm12\npslld xmm3, 1\npsubd xmm2, xmm3\nmovdqa xmm3, xmm1\npunpcklwd xmm1, xmm2\npunpckhwd xmm3, xmm2\nmovdqa xmm2, xmm1\npunpcklwd xmm1, xmm3\npunpckhwd xmm2, xmm3\npunpcklwd xmm1, xmm2\npand xmm1, xmm9\npackuswb xmm0, xmm1\npaddb xmm0, xmm11\nmovups xmmword ptr [rax-10h], xmm0\ncmp rsi, rax\njnz loc_2270\ncmp rdx, rcx\njz loc_294C\nloc_25E6:\nmovsx eax, byte ptr [rsi]\nlea edi, [rbx+rax-61h]\nmovsxd rax, edi\nmov r8d, edi\nimul rax, 4EC4EC4Fh\nsar r8d, 1Fh\nsar rax, 23h\nsub eax, r8d\nimul eax, 1Ah\nsub edi, eax\nlea rax, [rcx+1]\nadd edi, 61h ; 'a'\nmov [rsi], dil\ncmp rax, rdx\njnb loc_294C\nlea rdi, [rbp+rax+0]\nmovsx eax, byte ptr [rdi]\nlea esi, [rbx+rax-61h]\nmovsxd rax, esi\nmov r8d, esi\nimul rax, 4EC4EC4Fh\nsar r8d, 1Fh\nsar rax, 23h\nsub eax, r8d\nimul eax, 1Ah\nsub esi, eax\nlea rax, [rcx+2]\nadd esi, 61h ; 'a'\nmov [rdi], sil\ncmp rax, rdx\njnb loc_294C\nlea rdi, [rbp+rax+0]\nmovsx eax, byte ptr [rdi]\nlea esi, [rbx+rax-61h]\nmovsxd rax, esi\nmov r8d, esi\nimul rax, 4EC4EC4Fh\nsar r8d, 1Fh\nsar rax, 23h\nsub eax, r8d\nimul eax, 1Ah\nsub esi, eax\nlea rax, [rcx+3]\nadd esi, 61h ; 'a'\nmov [rdi], sil\ncmp rax, rdx\njnb loc_294C\nlea rdi, [rbp+rax+0]\nmovsx eax, byte ptr [rdi]\nlea esi, [rbx+rax-61h]\nmovsxd rax, esi\nmov r8d, esi\nimul rax, 4EC4EC4Fh\nsar r8d, 1Fh\nsar rax, 23h\nsub eax, r8d\nimul eax, 1Ah\nsub esi, eax\nlea rax, [rcx+4]\nadd esi, 61h ; 'a'\nmov [rdi], sil\ncmp rax, rdx\njnb loc_294C\nlea rdi, [rbp+rax+0]\nmovsx eax, byte ptr [rdi]\nlea esi, [rbx+rax-61h]\nmovsxd rax, esi\nmov r8d, esi\nimul rax, 4EC4EC4Fh\nsar r8d, 1Fh\nsar rax, 23h\nsub eax, r8d\nimul eax, 1Ah\nsub esi, eax\nlea rax, [rcx+5]\nadd esi, 61h ; 'a'\nmov [rdi], sil\ncmp rax, rdx\njnb loc_294C\nlea rdi, [rbp+rax+0]\nmovsx eax, byte ptr [rdi]\nlea esi, [rbx+rax-61h]\nmovsxd rax, esi\nmov r8d, esi\nimul rax, 4EC4EC4Fh\nsar r8d, 1Fh\nsar rax, 23h\nsub eax, r8d\nimul eax, 1Ah\nsub esi, eax\nlea rax, [rcx+6]\nadd esi, 61h ; 'a'\nmov [rdi], sil\ncmp rax, rdx\njnb loc_294C\nlea rdi, [rbp+rax+0]\nmovsx eax, byte ptr [rdi]\nlea esi, [rbx+rax-61h]\nmovsxd rax, esi\nmov r8d, esi\nimul rax, 4EC4EC4Fh\nsar r8d, 1Fh\nsar rax, 23h\nsub eax, r8d\nimul eax, 1Ah\nsub esi, eax\nlea rax, [rcx+7]\nadd esi, 61h ; 'a'\nmov [rdi], sil\ncmp rax, rdx\njnb loc_294C\nlea rdi, [rbp+rax+0]\nmovsx eax, byte ptr [rdi]\nlea esi, [rbx+rax-61h]\nmovsxd rax, esi\nmov r8d, esi\nimul rax, 4EC4EC4Fh\nsar r8d, 1Fh\nsar rax, 23h\nsub eax, r8d\nimul eax, 1Ah\nsub esi, eax\nlea rax, [rcx+8]\nadd esi, 61h ; 'a'\nmov [rdi], sil\ncmp rax, rdx\njnb loc_294C\nlea rdi, [rbp+rax+0]\nmovsx eax, byte ptr [rdi]\nlea esi, [rbx+rax-61h]\nmovsxd rax, esi\nmov r8d, esi\nimul rax, 4EC4EC4Fh\nsar r8d, 1Fh\nsar rax, 23h\nsub eax, r8d\nimul eax, 1Ah\nsub esi, eax\nlea rax, [rcx+9]\nadd esi, 61h ; 'a'\nmov [rdi], sil\ncmp rax, rdx\njnb loc_294C\nlea rdi, [rbp+rax+0]\nmovsx eax, byte ptr [rdi]\nlea esi, [rbx+rax-61h]\nmovsxd rax, esi\nmov r8d, esi\nimul rax, 4EC4EC4Fh\nsar r8d, 1Fh\nsar rax, 23h\nsub eax, r8d\nimul eax, 1Ah\nsub esi, eax\nlea rax, [rcx+0Ah]\nadd esi, 61h ; 'a'\nmov [rdi], sil\ncmp rax, rdx\njnb loc_294C\nlea rdi, [rbp+rax+0]\nmovsx eax, byte ptr [rdi]\nlea esi, [rbx+rax-61h]\nmovsxd rax, esi\nmov r8d, esi\nimul rax, 4EC4EC4Fh\nsar r8d, 1Fh\nsar rax, 23h\nsub eax, r8d\nimul eax, 1Ah\nsub esi, eax\nlea rax, [rcx+0Bh]\nadd esi, 61h ; 'a'\nmov [rdi], sil\ncmp rax, rdx\njnb loc_294C\nlea rdi, [rbp+rax+0]\nmovsx eax, byte ptr [rdi]\nlea esi, [rbx+rax-61h]\nmovsxd rax, esi\nmov r8d, esi\nimul rax, 4EC4EC4Fh\nsar r8d, 1Fh\nsar rax, 23h\nsub eax, r8d\nimul eax, 1Ah\nsub esi, eax\nlea rax, [rcx+0Ch]\nadd esi, 61h ; 'a'\nmov [rdi], sil\ncmp rax, rdx\njnb loc_294C\nlea rdi, [rbp+rax+0]\nmovsx eax, byte ptr [rdi]\nlea esi, [rbx+rax-61h]\nmovsxd rax, esi\nmov r8d, esi\nimul rax, 4EC4EC4Fh\nsar r8d, 1Fh\nsar rax, 23h\nsub eax, r8d\nimul eax, 1Ah\nsub esi, eax\nlea rax, [rcx+0Dh]\nadd esi, 61h ; 'a'\nmov [rdi], sil\ncmp rax, rdx\njnb short loc_294C\nlea rdi, [rbp+rax+0]\nadd rcx, 0Eh\nmovsx eax, byte ptr [rdi]\nlea esi, [rbx+rax-61h]\nmovsxd rax, esi\nmov r8d, esi\nimul rax, 4EC4EC4Fh\nsar r8d, 1Fh\nsar rax, 23h\nsub eax, r8d\nimul eax, 1Ah\nsub esi, eax\nadd esi, 61h ; 'a'\nmov [rdi], sil\ncmp rcx, rdx\njnb short loc_294C\nadd rbp, rcx\nmovsx eax, byte ptr [rbp+0]\nlea edx, [rbx+rax-61h]\nmovsxd rax, edx\nmov ecx, edx\nimul rax, 4EC4EC4Fh\nsar ecx, 1Fh\nsar rax, 23h\nsub eax, ecx\nimul eax, 1Ah\nsub edx, eax\nadd edx, 61h ; 'a'\nmov [rbp+0], dl\nloc_294C:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_2953:\nxor ecx, ecx\nmov rsi, rbp\njmp loc_25E6", + "ida_strip_pseudo": "size_t __fastcall sub_21E0(const char *a1, int a2)\n{\n unsigned int v3; // ebx\n size_t result; // rax\n unsigned __int64 v5; // rdx\n __m128i v6; // xmm7\n __m128i si128; // xmm4\n unsigned __int64 v8; // rcx\n char *v9; // rsi\n __m128i v10; // xmm9\n __m128i v11; // xmm6\n __m128i v12; // xmm7\n __m128i v13; // xmm11\n __m128i v14; // xmm2\n __m128i v15; // xmm0\n __m128i v16; // xmm1\n __m128i v17; // xmm2\n __m128i v18; // xmm3\n __m128i v19; // xmm12\n __m128i v20; // xmm0\n __m128i v21; // xmm1\n __m128i v22; // xmm3\n __m128i v23; // xmm2\n __m128i v24; // xmm13\n __m128i v25; // xmm12\n __m128i v26; // xmm0\n __m128i v27; // xmm13\n __m128i v28; // xmm12\n __m128i v29; // xmm1\n __m128i v30; // xmm12\n __m128i v31; // xmm1\n __m128i v32; // xmm0\n __m128i v33; // xmm12\n __m128i v34; // xmm1\n __m128i v35; // xmm1\n __m128i v36; // xmm3\n __m128i v37; // xmm12\n __m128i v38; // xmm2\n __m128i v39; // xmm3\n __m128i v40; // xmm2\n char *v41; // rdi\n int v42; // esi\n char *v43; // rdi\n int v44; // esi\n char *v45; // rdi\n int v46; // esi\n char *v47; // rdi\n int v48; // esi\n char *v49; // rdi\n int v50; // esi\n char *v51; // rdi\n int v52; // esi\n char *v53; // rdi\n int v54; // esi\n char *v55; // rdi\n int v56; // esi\n char *v57; // rdi\n int v58; // esi\n char *v59; // rdi\n int v60; // esi\n char *v61; // rdi\n int v62; // esi\n char *v63; // rdi\n int v64; // esi\n char *v65; // rdi\n unsigned __int64 v66; // rcx\n int v67; // esi\n char *v68; // rbp\n int v69; // edx\n\n v3 = a2 == 0 ? 21 : 5;\n result = strlen(a1);\n if ( result )\n {\n v5 = result;\n if ( result - 1 <= 0xE )\n {\n v8 = 0LL;\n v9 = (char *)a1;\n }\n else\n {\n v6 = _mm_cvtsi32_si128(v3);\n result = (size_t)a1;\n si128 = _mm_load_si128((const __m128i *)&xmmword_3060);\n v8 = v5 & 0xFFFFFFFFFFFFFFF0LL;\n v9 = (char *)&a1[v5 & 0xFFFFFFFFFFFFFFF0LL];\n v10 = _mm_load_si128((const __m128i *)&xmmword_3070);\n v11 = _mm_cmpgt_epi32((__m128i)0LL, si128);\n v12 = _mm_add_epi16(_mm_shuffle_epi32(_mm_unpacklo_epi16(v6, v6), 0), (__m128i)xmmword_3050);\n v13 = _mm_load_si128((const __m128i *)&xmmword_3080);\n do\n {\n v14 = _mm_loadu_si128((const __m128i *)result);\n result += 16LL;\n v15 = _mm_cmpgt_epi8((__m128i)0LL, v14);\n v16 = _mm_add_epi16(_mm_unpacklo_epi8(v14, v15), v12);\n v17 = _mm_add_epi16(_mm_unpackhi_epi8(v14, v15), v12);\n v18 = _mm_cmpgt_epi16((__m128i)0LL, v16);\n v19 = _mm_cmpgt_epi16((__m128i)0LL, v17);\n v20 = _mm_unpacklo_epi16(v16, v18);\n v21 = _mm_unpackhi_epi16(v16, v18);\n v22 = _mm_unpacklo_epi16(v17, v19);\n v23 = _mm_unpackhi_epi16(v17, v19);\n v24 = _mm_srli_epi64(v20, 0x20u);\n v25 = _mm_sub_epi32(\n _mm_srai_epi32(\n _mm_shuffle_epi32(\n (__m128i)_mm_shuffle_ps(\n (__m128)_mm_add_epi64(\n _mm_mul_epu32(v20, si128),\n _mm_slli_epi64(\n _mm_add_epi64(\n _mm_mul_epu32(_mm_cmpgt_epi32((__m128i)0LL, v20), si128),\n _mm_mul_epu32(v11, v20)),\n 0x20u)),\n (__m128)_mm_add_epi64(\n _mm_mul_epu32(v24, si128),\n _mm_slli_epi64(\n _mm_add_epi64(\n _mm_mul_epu32(_mm_cmpgt_epi32((__m128i)0LL, v24), si128),\n _mm_mul_epu32(v11, v24)),\n 0x20u)),\n 221),\n 216),\n 3u),\n _mm_srai_epi32(v20, 0x1Fu));\n v26 = _mm_sub_epi32(\n v20,\n _mm_slli_epi32(_mm_add_epi32(v25, _mm_slli_epi32(_mm_add_epi32(_mm_slli_epi32(v25, 1u), v25), 2u)), 1u));\n v27 = _mm_srli_epi64(v21, 0x20u);\n v28 = _mm_sub_epi32(\n _mm_srai_epi32(\n _mm_shuffle_epi32(\n (__m128i)_mm_shuffle_ps(\n (__m128)_mm_add_epi64(\n _mm_mul_epu32(v21, si128),\n _mm_slli_epi64(\n _mm_add_epi64(\n _mm_mul_epu32(_mm_cmpgt_epi32((__m128i)0LL, v21), si128),\n _mm_mul_epu32(v11, v21)),\n 0x20u)),\n (__m128)_mm_add_epi64(\n _mm_mul_epu32(v27, si128),\n _mm_slli_epi64(\n _mm_add_epi64(\n _mm_mul_epu32(_mm_cmpgt_epi32((__m128i)0LL, v27), si128),\n _mm_mul_epu32(v11, v27)),\n 0x20u)),\n 221),\n 216),\n 3u),\n _mm_srai_epi32(v21, 0x1Fu));\n v29 = _mm_sub_epi32(\n v21,\n _mm_slli_epi32(_mm_add_epi32(v28, _mm_slli_epi32(_mm_add_epi32(_mm_slli_epi32(v28, 1u), v28), 2u)), 1u));\n v30 = _mm_unpackhi_epi16(v26, v29);\n v31 = _mm_unpacklo_epi16(v26, v29);\n v32 = _mm_unpacklo_epi16(_mm_unpacklo_epi16(v31, v30), _mm_unpackhi_epi16(v31, v30));\n v33 = _mm_srli_epi64(v22, 0x20u);\n v34 = _mm_sub_epi32(\n _mm_srai_epi32(\n _mm_shuffle_epi32(\n (__m128i)_mm_shuffle_ps(\n (__m128)_mm_add_epi64(\n _mm_mul_epu32(v22, si128),\n _mm_slli_epi64(\n _mm_add_epi64(\n _mm_mul_epu32(_mm_cmpgt_epi32((__m128i)0LL, v22), si128),\n _mm_mul_epu32(v11, v22)),\n 0x20u)),\n (__m128)_mm_add_epi64(\n _mm_mul_epu32(v33, si128),\n _mm_slli_epi64(\n _mm_add_epi64(\n _mm_mul_epu32(_mm_cmpgt_epi32((__m128i)0LL, v33), si128),\n _mm_mul_epu32(v11, v33)),\n 0x20u)),\n 221),\n 216),\n 3u),\n _mm_srai_epi32(v22, 0x1Fu));\n v35 = _mm_sub_epi32(\n v22,\n _mm_slli_epi32(_mm_add_epi32(_mm_slli_epi32(_mm_add_epi32(_mm_slli_epi32(v34, 1u), v34), 2u), v34), 1u));\n v36 = _mm_srli_epi64(v23, 0x20u);\n v37 = _mm_sub_epi32(\n _mm_srai_epi32(\n _mm_shuffle_epi32(\n (__m128i)_mm_shuffle_ps(\n (__m128)_mm_add_epi64(\n _mm_mul_epu32(v23, si128),\n _mm_slli_epi64(\n _mm_add_epi64(\n _mm_mul_epu32(_mm_cmpgt_epi32((__m128i)0LL, v23), si128),\n _mm_mul_epu32(v11, v23)),\n 0x20u)),\n (__m128)_mm_add_epi64(\n _mm_mul_epu32(v36, si128),\n _mm_slli_epi64(\n _mm_add_epi64(\n _mm_mul_epu32(_mm_cmpgt_epi32((__m128i)0LL, v36), si128),\n _mm_mul_epu32(v11, v36)),\n 0x20u)),\n 221),\n 216),\n 3u),\n _mm_srai_epi32(v23, 0x1Fu));\n v38 = _mm_sub_epi32(\n v23,\n _mm_slli_epi32(_mm_add_epi32(_mm_slli_epi32(_mm_add_epi32(_mm_slli_epi32(v37, 1u), v37), 2u), v37), 1u));\n v39 = _mm_unpackhi_epi16(v35, v38);\n v40 = _mm_unpacklo_epi16(v35, v38);\n *(__m128i *)(result - 16) = _mm_add_epi8(\n _mm_packus_epi16(\n _mm_and_si128(v32, v10),\n _mm_and_si128(\n _mm_unpacklo_epi16(_mm_unpacklo_epi16(v40, v39), _mm_unpackhi_epi16(v40, v39)),\n v10)),\n v13);\n }\n while ( v9 != (char *)result );\n if ( v5 == v8 )\n return result;\n }\n result = v8 + 1;\n *v9 = (int)(v3 + *v9 - 97) % 26 + 97;\n if ( v8 + 1 < v5 )\n {\n v41 = (char *)&a1[result];\n v42 = v3 + a1[result] - 97;\n result = v8 + 2;\n *v41 = v42 % 26 + 97;\n if ( v8 + 2 < v5 )\n {\n v43 = (char *)&a1[result];\n v44 = v3 + a1[result] - 97;\n result = v8 + 3;\n *v43 = v44 % 26 + 97;\n if ( v8 + 3 < v5 )\n {\n v45 = (char *)&a1[result];\n v46 = v3 + a1[result] - 97;\n result = v8 + 4;\n *v45 = v46 % 26 + 97;\n if ( v8 + 4 < v5 )\n {\n v47 = (char *)&a1[result];\n v48 = v3 + a1[result] - 97;\n result = v8 + 5;\n *v47 = v48 % 26 + 97;\n if ( v8 + 5 < v5 )\n {\n v49 = (char *)&a1[result];\n v50 = v3 + a1[result] - 97;\n result = v8 + 6;\n *v49 = v50 % 26 + 97;\n if ( v8 + 6 < v5 )\n {\n v51 = (char *)&a1[result];\n v52 = v3 + a1[result] - 97;\n result = v8 + 7;\n *v51 = v52 % 26 + 97;\n if ( v8 + 7 < v5 )\n {\n v53 = (char *)&a1[result];\n v54 = v3 + a1[result] - 97;\n result = v8 + 8;\n *v53 = v54 % 26 + 97;\n if ( v8 + 8 < v5 )\n {\n v55 = (char *)&a1[result];\n v56 = v3 + a1[result] - 97;\n result = v8 + 9;\n *v55 = v56 % 26 + 97;\n if ( v8 + 9 < v5 )\n {\n v57 = (char *)&a1[result];\n v58 = v3 + a1[result] - 97;\n result = v8 + 10;\n *v57 = v58 % 26 + 97;\n if ( v8 + 10 < v5 )\n {\n v59 = (char *)&a1[result];\n v60 = v3 + a1[result] - 97;\n result = v8 + 11;\n *v59 = v60 % 26 + 97;\n if ( v8 + 11 < v5 )\n {\n v61 = (char *)&a1[result];\n v62 = v3 + a1[result] - 97;\n result = v8 + 12;\n *v61 = v62 % 26 + 97;\n if ( v8 + 12 < v5 )\n {\n v63 = (char *)&a1[result];\n v64 = v3 + a1[result] - 97;\n result = v8 + 13;\n *v63 = v64 % 26 + 97;\n if ( v8 + 13 < v5 )\n {\n v65 = (char *)&a1[result];\n v66 = v8 + 14;\n v67 = v3 + a1[result] - 97;\n result = (unsigned int)(26 * (v67 / 26));\n *v65 = v67 % 26 + 97;\n if ( v66 < v5 )\n {\n v68 = (char *)&a1[v66];\n v69 = v3 + *v68 - 97;\n result = (unsigned int)(26 * (v69 / 26));\n *v68 = v69 % 26 + 97;\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned int sub_21E0(const char *a1, int a2) {\n unsigned int v3;\n unsigned int result;\n unsigned long long v5;\n __m128i v6;\n __m128i si128;\n unsigned long long v8;\n char *v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n __m128i v15;\n __m128i v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n __m128i v20;\n __m128i v21;\n __m128i v22;\n __m128i v23;\n __m128i v24;\n __m128i v25;\n __m128i v26;\n __m128i v27;\n __m128i v28;\n __m128i v29;\n __m128i v30;\n __m128i v31;\n __m128i v32;\n __m128i v33;\n __m128i v34;\n __m128i v35;\n __m128i v36;\n __m128i v37;\n __m128i v38;\n __m128i v39;\n __m128i v40;\n char *v41;\n int v42;\n char *v43;\n int v44;\n char *v45;\n int v46;\n char *v47;\n int v48;\n char *v49;\n int v50;\n char *v51;\n int v52;\n char *v53;\n int v54;\n char *v55;\n int v56;\n char *v57;\n int v58;\n char *v59;\n int v60;\n char *v61;\n int v62;\n char *v63;\n int v64;\n char *v65;\n unsigned long long v66;\n int v67;\n char *v68;\n int v69;\n v3 = a2 == 0 ? 21 : 5;\n result = strlen(a1);\n if (result) {\n v5 = result;\n if (result - 1 <= 14) {\n v8 = 0LL;\n v9 = (char *)a1;\n } else {\n v6 = _mm_cvtsi32_si128(v3);\n result = (unsigned int)a1;\n si128 = _mm_load_si128((const __m128i *)&xmmword_3060);\n v8 = v5 & 18446744073709551600LL;\n v9 = (char *)&a1[v5 & 18446744073709551600LL];\n v10 = _mm_load_si128((const __m128i *)&xmmword_3070);\n v11 = _mm_cmpgt_epi32((__m128i)0LL, si128);\n v12 = _mm_add_epi16(_mm_shuffle_epi32(_mm_unpacklo_epi16(v6, v6), 0),\n (__m128i)xmmword_3050);\n v13 = _mm_load_si128((const __m128i *)&xmmword_3080);\n do {\n v14 = _mm_loadu_si128((const __m128i *)result);\n result += 16LL;\n v15 = _mm_cmpgt_epi8((__m128i)0LL, v14);\n v16 = _mm_add_epi16(_mm_unpacklo_epi8(v14, v15), v12);\n v17 = _mm_add_epi16(_mm_unpackhi_epi8(v14, v15), v12);\n v18 = _mm_cmpgt_epi16((__m128i)0LL, v16);\n v19 = _mm_cmpgt_epi16((__m128i)0LL, v17);\n v20 = _mm_unpacklo_epi16(v16, v18);\n v21 = _mm_unpackhi_epi16(v16, v18);\n v22 = _mm_unpacklo_epi16(v17, v19);\n v23 = _mm_unpackhi_epi16(v17, v19);\n v24 = _mm_srli_epi64(v20, 32u);\n v25 = _mm_sub_epi32(\n _mm_srai_epi32(\n _mm_shuffle_epi32(\n (__m128i)_mm_shuffle_ps(\n (__m128)_mm_add_epi64(\n _mm_mul_epu32(v20, si128),\n _mm_slli_epi64(\n _mm_add_epi64(\n _mm_mul_epu32(\n _mm_cmpgt_epi32((__m128i)0LL, v20),\n si128),\n _mm_mul_epu32(v11, v20)),\n 32u)),\n (__m128)_mm_add_epi64(\n _mm_mul_epu32(v24, si128),\n _mm_slli_epi64(\n _mm_add_epi64(\n _mm_mul_epu32(\n _mm_cmpgt_epi32((__m128i)0LL, v24),\n si128),\n _mm_mul_epu32(v11, v24)),\n 32u)),\n 221),\n 216),\n 3u),\n _mm_srai_epi32(v20, 31u));\n v26 = _mm_sub_epi32(\n v20,\n _mm_slli_epi32(\n _mm_add_epi32(\n v25, _mm_slli_epi32(\n _mm_add_epi32(_mm_slli_epi32(v25, 1u), v25), 2u)),\n 1u));\n v27 = _mm_srli_epi64(v21, 32u);\n v28 = _mm_sub_epi32(\n _mm_srai_epi32(\n _mm_shuffle_epi32(\n (__m128i)_mm_shuffle_ps(\n (__m128)_mm_add_epi64(\n _mm_mul_epu32(v21, si128),\n _mm_slli_epi64(\n _mm_add_epi64(\n _mm_mul_epu32(\n _mm_cmpgt_epi32((__m128i)0LL, v21),\n si128),\n _mm_mul_epu32(v11, v21)),\n 32u)),\n (__m128)_mm_add_epi64(\n _mm_mul_epu32(v27, si128),\n _mm_slli_epi64(\n _mm_add_epi64(\n _mm_mul_epu32(\n _mm_cmpgt_epi32((__m128i)0LL, v27),\n si128),\n _mm_mul_epu32(v11, v27)),\n 32u)),\n 221),\n 216),\n 3u),\n _mm_srai_epi32(v21, 31u));\n v29 = _mm_sub_epi32(\n v21,\n _mm_slli_epi32(\n _mm_add_epi32(\n v28, _mm_slli_epi32(\n _mm_add_epi32(_mm_slli_epi32(v28, 1u), v28), 2u)),\n 1u));\n v30 = _mm_unpackhi_epi16(v26, v29);\n v31 = _mm_unpacklo_epi16(v26, v29);\n v32 = _mm_unpacklo_epi16(_mm_unpacklo_epi16(v31, v30),\n _mm_unpackhi_epi16(v31, v30));\n v33 = _mm_srli_epi64(v22, 32u);\n v34 = _mm_sub_epi32(\n _mm_srai_epi32(\n _mm_shuffle_epi32(\n (__m128i)_mm_shuffle_ps(\n (__m128)_mm_add_epi64(\n _mm_mul_epu32(v22, si128),\n _mm_slli_epi64(\n _mm_add_epi64(\n _mm_mul_epu32(\n _mm_cmpgt_epi32((__m128i)0LL, v22),\n si128),\n _mm_mul_epu32(v11, v22)),\n 32u)),\n (__m128)_mm_add_epi64(\n _mm_mul_epu32(v33, si128),\n _mm_slli_epi64(\n _mm_add_epi64(\n _mm_mul_epu32(\n _mm_cmpgt_epi32((__m128i)0LL, v33),\n si128),\n _mm_mul_epu32(v11, v33)),\n 32u)),\n 221),\n 216),\n 3u),\n _mm_srai_epi32(v22, 31u));\n v35 = _mm_sub_epi32(\n v22, _mm_slli_epi32(\n _mm_add_epi32(\n _mm_slli_epi32(\n _mm_add_epi32(_mm_slli_epi32(v34, 1u), v34), 2u),\n v34),\n 1u));\n v36 = _mm_srli_epi64(v23, 32u);\n v37 = _mm_sub_epi32(\n _mm_srai_epi32(\n _mm_shuffle_epi32(\n (__m128i)_mm_shuffle_ps(\n (__m128)_mm_add_epi64(\n _mm_mul_epu32(v23, si128),\n _mm_slli_epi64(\n _mm_add_epi64(\n _mm_mul_epu32(\n _mm_cmpgt_epi32((__m128i)0LL, v23),\n si128),\n _mm_mul_epu32(v11, v23)),\n 32u)),\n (__m128)_mm_add_epi64(\n _mm_mul_epu32(v36, si128),\n _mm_slli_epi64(\n _mm_add_epi64(\n _mm_mul_epu32(\n _mm_cmpgt_epi32((__m128i)0LL, v36),\n si128),\n _mm_mul_epu32(v11, v36)),\n 32u)),\n 221),\n 216),\n 3u),\n _mm_srai_epi32(v23, 31u));\n v38 = _mm_sub_epi32(\n v23, _mm_slli_epi32(\n _mm_add_epi32(\n _mm_slli_epi32(\n _mm_add_epi32(_mm_slli_epi32(v37, 1u), v37), 2u),\n v37),\n 1u));\n v39 = _mm_unpackhi_epi16(v35, v38);\n v40 = _mm_unpacklo_epi16(v35, v38);\n *(__m128i *)(result - 16) = _mm_add_epi8(\n _mm_packus_epi16(\n _mm_and_si128(v32, v10),\n _mm_and_si128(_mm_unpacklo_epi16(_mm_unpacklo_epi16(v40, v39),\n _mm_unpackhi_epi16(v40, v39)),\n v10)),\n v13);\n } while (v9 != (char *)result);\n if (v5 == v8) return result;\n }\n result = v8 + 1;\n *v9 = (int)(v3 + *v9 - 97) % 26 + 97;\n if (v8 + 1 < v5) {\n v41 = (char *)&a1[result];\n v42 = v3 + a1[result] - 97;\n result = v8 + 2;\n *v41 = v42 % 26 + 97;\n if (v8 + 2 < v5) {\n v43 = (char *)&a1[result];\n v44 = v3 + a1[result] - 97;\n result = v8 + 3;\n *v43 = v44 % 26 + 97;\n if (v8 + 3 < v5) {\n v45 = (char *)&a1[result];\n v46 = v3 + a1[result] - 97;\n result = v8 + 4;\n *v45 = v46 % 26 + 97;\n if (v8 + 4 < v5) {\n v47 = (char *)&a1[result];\n v48 = v3 + a1[result] - 97;\n result = v8 + 5;\n *v47 = v48 % 26 + 97;\n if (v8 + 5 < v5) {\n v49 = (char *)&a1[result];\n v50 = v3 + a1[result] - 97;\n result = v8 + 6;\n *v49 = v50 % 26 + 97;\n if (v8 + 6 < v5) {\n v51 = (char *)&a1[result];\n v52 = v3 + a1[result] - 97;\n result = v8 + 7;\n *v51 = v52 % 26 + 97;\n if (v8 + 7 < v5) {\n v53 = (char *)&a1[result];\n v54 = v3 + a1[result] - 97;\n result = v8 + 8;\n *v53 = v54 % 26 + 97;\n if (v8 + 8 < v5) {\n v55 = (char *)&a1[result];\n v56 = v3 + a1[result] - 97;\n result = v8 + 9;\n *v55 = v56 % 26 + 97;\n if (v8 + 9 < v5) {\n v57 = (char *)&a1[result];\n v58 = v3 + a1[result] - 97;\n result = v8 + 10;\n *v57 = v58 % 26 + 97;\n if (v8 + 10 < v5) {\n v59 = (char *)&a1[result];\n v60 = v3 + a1[result] - 97;\n result = v8 + 11;\n *v59 = v60 % 26 + 97;\n if (v8 + 11 < v5) {\n v61 = (char *)&a1[result];\n v62 = v3 + a1[result] - 97;\n result = v8 + 12;\n *v61 = v62 % 26 + 97;\n if (v8 + 12 < v5) {\n v63 = (char *)&a1[result];\n v64 = v3 + a1[result] - 97;\n result = v8 + 13;\n *v63 = v64 % 26 + 97;\n if (v8 + 13 < v5) {\n v65 = (char *)&a1[result];\n v66 = v8 + 14;\n v67 = v3 + a1[result] - 97;\n result = (unsigned int)(26 * (v67 / 26));\n *v65 = v67 % 26 + 97;\n if (v66 < v5) {\n v68 = (char *)&a1[v66];\n v69 = v3 + *v68 - 97;\n result = (unsigned int)(26 * (v69 / 26));\n *v68 = v69 % 26 + 97;\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "unsigned int func0(const char *a1, int a2) {\n unsigned int v3;\n unsigned int result;\n unsigned long long v5;\n __m128i v6;\n __m128i si128;\n unsigned long long v8;\n char *v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n __m128i v15;\n __m128i v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n __m128i v20;\n __m128i v21;\n __m128i v22;\n __m128i v23;\n __m128i v24;\n __m128i v25;\n __m128i v26;\n __m128i v27;\n __m128i v28;\n __m128i v29;\n __m128i v30;\n __m128i v31;\n __m128i v32;\n __m128i v33;\n __m128i v34;\n __m128i v35;\n __m128i v36;\n __m128i v37;\n __m128i v38;\n __m128i v39;\n __m128i v40;\n char *v41;\n int v42;\n char *v43;\n int v44;\n char *v45;\n int v46;\n char *v47;\n int v48;\n char *v49;\n int v50;\n char *v51;\n int v52;\n char *v53;\n int v54;\n char *v55;\n int v56;\n char *v57;\n int v58;\n char *v59;\n int v60;\n char *v61;\n int v62;\n char *v63;\n int v64;\n char *v65;\n unsigned long long v66;\n int v67;\n char *v68;\n int v69;\n v3 = a2 == 0 ? 21 : 5;\n result = strlen(a1);\n if (result) {\n v5 = result;\n if (result - 1 <= 14) {\n v8 = 0LL;\n v9 = (char *)a1;\n } else {\n v6 = _mm_cvtsi32_si128(v3);\n result = (unsigned int)a1;\n si128 = _mm_load_si128((const __m128i *)&xmmword_3060);\n v8 = v5 & 18446744073709551600LL;\n v9 = (char *)&a1[v5 & 18446744073709551600LL];\n v10 = _mm_load_si128((const __m128i *)&xmmword_3070);\n v11 = _mm_cmpgt_epi32((__m128i)0LL, si128);\n v12 = _mm_add_epi16(_mm_shuffle_epi32(_mm_unpacklo_epi16(v6, v6), 0),\n (__m128i)xmmword_3050);\n v13 = _mm_load_si128((const __m128i *)&xmmword_3080);\n do {\n v14 = _mm_loadu_si128((const __m128i *)result);\n result += 16LL;\n v15 = _mm_cmpgt_epi8((__m128i)0LL, v14);\n v16 = _mm_add_epi16(_mm_unpacklo_epi8(v14, v15), v12);\n v17 = _mm_add_epi16(_mm_unpackhi_epi8(v14, v15), v12);\n v18 = _mm_cmpgt_epi16((__m128i)0LL, v16);\n v19 = _mm_cmpgt_epi16((__m128i)0LL, v17);\n v20 = _mm_unpacklo_epi16(v16, v18);\n v21 = _mm_unpackhi_epi16(v16, v18);\n v22 = _mm_unpacklo_epi16(v17, v19);\n v23 = _mm_unpackhi_epi16(v17, v19);\n v24 = _mm_srli_epi64(v20, 32u);\n v25 = _mm_sub_epi32(\n _mm_srai_epi32(\n _mm_shuffle_epi32(\n (__m128i)_mm_shuffle_ps(\n (__m128)_mm_add_epi64(\n _mm_mul_epu32(v20, si128),\n _mm_slli_epi64(\n _mm_add_epi64(\n _mm_mul_epu32(\n _mm_cmpgt_epi32((__m128i)0LL, v20),\n si128),\n _mm_mul_epu32(v11, v20)),\n 32u)),\n (__m128)_mm_add_epi64(\n _mm_mul_epu32(v24, si128),\n _mm_slli_epi64(\n _mm_add_epi64(\n _mm_mul_epu32(\n _mm_cmpgt_epi32((__m128i)0LL, v24),\n si128),\n _mm_mul_epu32(v11, v24)),\n 32u)),\n 221),\n 216),\n 3u),\n _mm_srai_epi32(v20, 31u));\n v26 = _mm_sub_epi32(\n v20,\n _mm_slli_epi32(\n _mm_add_epi32(\n v25, _mm_slli_epi32(\n _mm_add_epi32(_mm_slli_epi32(v25, 1u), v25), 2u)),\n 1u));\n v27 = _mm_srli_epi64(v21, 32u);\n v28 = _mm_sub_epi32(\n _mm_srai_epi32(\n _mm_shuffle_epi32(\n (__m128i)_mm_shuffle_ps(\n (__m128)_mm_add_epi64(\n _mm_mul_epu32(v21, si128),\n _mm_slli_epi64(\n _mm_add_epi64(\n _mm_mul_epu32(\n _mm_cmpgt_epi32((__m128i)0LL, v21),\n si128),\n _mm_mul_epu32(v11, v21)),\n 32u)),\n (__m128)_mm_add_epi64(\n _mm_mul_epu32(v27, si128),\n _mm_slli_epi64(\n _mm_add_epi64(\n _mm_mul_epu32(\n _mm_cmpgt_epi32((__m128i)0LL, v27),\n si128),\n _mm_mul_epu32(v11, v27)),\n 32u)),\n 221),\n 216),\n 3u),\n _mm_srai_epi32(v21, 31u));\n v29 = _mm_sub_epi32(\n v21,\n _mm_slli_epi32(\n _mm_add_epi32(\n v28, _mm_slli_epi32(\n _mm_add_epi32(_mm_slli_epi32(v28, 1u), v28), 2u)),\n 1u));\n v30 = _mm_unpackhi_epi16(v26, v29);\n v31 = _mm_unpacklo_epi16(v26, v29);\n v32 = _mm_unpacklo_epi16(_mm_unpacklo_epi16(v31, v30),\n _mm_unpackhi_epi16(v31, v30));\n v33 = _mm_srli_epi64(v22, 32u);\n v34 = _mm_sub_epi32(\n _mm_srai_epi32(\n _mm_shuffle_epi32(\n (__m128i)_mm_shuffle_ps(\n (__m128)_mm_add_epi64(\n _mm_mul_epu32(v22, si128),\n _mm_slli_epi64(\n _mm_add_epi64(\n _mm_mul_epu32(\n _mm_cmpgt_epi32((__m128i)0LL, v22),\n si128),\n _mm_mul_epu32(v11, v22)),\n 32u)),\n (__m128)_mm_add_epi64(\n _mm_mul_epu32(v33, si128),\n _mm_slli_epi64(\n _mm_add_epi64(\n _mm_mul_epu32(\n _mm_cmpgt_epi32((__m128i)0LL, v33),\n si128),\n _mm_mul_epu32(v11, v33)),\n 32u)),\n 221),\n 216),\n 3u),\n _mm_srai_epi32(v22, 31u));\n v35 = _mm_sub_epi32(\n v22, _mm_slli_epi32(\n _mm_add_epi32(\n _mm_slli_epi32(\n _mm_add_epi32(_mm_slli_epi32(v34, 1u), v34), 2u),\n v34),\n 1u));\n v36 = _mm_srli_epi64(v23, 32u);\n v37 = _mm_sub_epi32(\n _mm_srai_epi32(\n _mm_shuffle_epi32(\n (__m128i)_mm_shuffle_ps(\n (__m128)_mm_add_epi64(\n _mm_mul_epu32(v23, si128),\n _mm_slli_epi64(\n _mm_add_epi64(\n _mm_mul_epu32(\n _mm_cmpgt_epi32((__m128i)0LL, v23),\n si128),\n _mm_mul_epu32(v11, v23)),\n 32u)),\n (__m128)_mm_add_epi64(\n _mm_mul_epu32(v36, si128),\n _mm_slli_epi64(\n _mm_add_epi64(\n _mm_mul_epu32(\n _mm_cmpgt_epi32((__m128i)0LL, v36),\n si128),\n _mm_mul_epu32(v11, v36)),\n 32u)),\n 221),\n 216),\n 3u),\n _mm_srai_epi32(v23, 31u));\n v38 = _mm_sub_epi32(\n v23, _mm_slli_epi32(\n _mm_add_epi32(\n _mm_slli_epi32(\n _mm_add_epi32(_mm_slli_epi32(v37, 1u), v37), 2u),\n v37),\n 1u));\n v39 = _mm_unpackhi_epi16(v35, v38);\n v40 = _mm_unpacklo_epi16(v35, v38);\n *(__m128i *)(result - 16) = _mm_add_epi8(\n _mm_packus_epi16(\n _mm_and_si128(v32, v10),\n _mm_and_si128(_mm_unpacklo_epi16(_mm_unpacklo_epi16(v40, v39),\n _mm_unpackhi_epi16(v40, v39)),\n v10)),\n v13);\n } while (v9 != (char *)result);\n if (v5 == v8) return result;\n }\n result = v8 + 1;\n *v9 = (int)(v3 + *v9 - 97) % 26 + 97;\n if (v8 + 1 < v5) {\n v41 = (char *)&a1[result];\n v42 = v3 + a1[result] - 97;\n result = v8 + 2;\n *v41 = v42 % 26 + 97;\n if (v8 + 2 < v5) {\n v43 = (char *)&a1[result];\n v44 = v3 + a1[result] - 97;\n result = v8 + 3;\n *v43 = v44 % 26 + 97;\n if (v8 + 3 < v5) {\n v45 = (char *)&a1[result];\n v46 = v3 + a1[result] - 97;\n result = v8 + 4;\n *v45 = v46 % 26 + 97;\n if (v8 + 4 < v5) {\n v47 = (char *)&a1[result];\n v48 = v3 + a1[result] - 97;\n result = v8 + 5;\n *v47 = v48 % 26 + 97;\n if (v8 + 5 < v5) {\n v49 = (char *)&a1[result];\n v50 = v3 + a1[result] - 97;\n result = v8 + 6;\n *v49 = v50 % 26 + 97;\n if (v8 + 6 < v5) {\n v51 = (char *)&a1[result];\n v52 = v3 + a1[result] - 97;\n result = v8 + 7;\n *v51 = v52 % 26 + 97;\n if (v8 + 7 < v5) {\n v53 = (char *)&a1[result];\n v54 = v3 + a1[result] - 97;\n result = v8 + 8;\n *v53 = v54 % 26 + 97;\n if (v8 + 8 < v5) {\n v55 = (char *)&a1[result];\n v56 = v3 + a1[result] - 97;\n result = v8 + 9;\n *v55 = v56 % 26 + 97;\n if (v8 + 9 < v5) {\n v57 = (char *)&a1[result];\n v58 = v3 + a1[result] - 97;\n result = v8 + 10;\n *v57 = v58 % 26 + 97;\n if (v8 + 10 < v5) {\n v59 = (char *)&a1[result];\n v60 = v3 + a1[result] - 97;\n result = v8 + 11;\n *v59 = v60 % 26 + 97;\n if (v8 + 11 < v5) {\n v61 = (char *)&a1[result];\n v62 = v3 + a1[result] - 97;\n result = v8 + 12;\n *v61 = v62 % 26 + 97;\n if (v8 + 12 < v5) {\n v63 = (char *)&a1[result];\n v64 = v3 + a1[result] - 97;\n result = v8 + 13;\n *v63 = v64 % 26 + 97;\n if (v8 + 13 < v5) {\n v65 = (char *)&a1[result];\n v66 = v8 + 14;\n v67 = v3 + a1[result] - 97;\n result = (unsigned int)(26 * (v67 / 26));\n *v65 = v67 % 26 + 97;\n if (v66 < v5) {\n v68 = (char *)&a1[v66];\n v69 = v3 + *v68 - 97;\n result = (unsigned int)(26 * (v69 / 26));\n *v68 = v69 % 26 + 97;\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-51", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "void func0(char *text) {\n const char *vowels = \"AEIOUaeiou\";\n char *out = text;\n while (*text != '\\0') {\n if (strchr(vowels, *text) == NULL) {\n *out++ = *text;\n }\n text++;\n }\n *out = '\\0';\n}", + "test": "#include \n#include \n#include \n\nint main() {\n char test1[] = \"\";\n func0(test1);\n assert(strcmp(test1, \"\") == 0);\n \n char test2[] = \"abcdef\\nghijklm\";\n func0(test2);\n assert(strcmp(test2, \"bcdf\\nghjklm\") == 0);\n \n char test3[] = \"fedcba\";\n func0(test3);\n assert(strcmp(test3, \"fdcb\") == 0);\n \n char test4[] = \"eeeee\";\n func0(test4);\n assert(strcmp(test4, \"\") == 0);\n \n char test5[] = \"acBAA\";\n func0(test5);\n assert(strcmp(test5, \"cB\") == 0);\n \n char test6[] = \"EcBOO\";\n func0(test6);\n assert(strcmp(test6, \"cB\") == 0);\n \n char test7[] = \"ybcd\";\n func0(test7);\n assert(strcmp(test7, \"ybcd\") == 0);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nlea rax, aAeiouaeiou; \"AEIOUaeiou\"\nmov [rbp+s], rax\nmov rax, [rbp+var_18]\nmov [rbp+var_10], rax\njmp short loc_1205\nloc_11CE:\nmov rax, [rbp+var_18]\nmovzx eax, byte ptr [rax]\nmovsx edx, al\nmov rax, [rbp+s]\nmov esi, edx; c\nmov rdi, rax; s\ncall _strchr\ntest rax, rax\njnz short loc_1200\nmov rax, [rbp+var_10]\nlea rdx, [rax+1]\nmov [rbp+var_10], rdx\nmov rdx, [rbp+var_18]\nmovzx edx, byte ptr [rdx]\nmov [rax], dl\nloc_1200:\nadd [rbp+var_18], 1\nloc_1205:\nmov rax, [rbp+var_18]\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_11CE\nmov rax, [rbp+var_10]\nmov byte ptr [rax], 0\nnop\nleave\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(_BYTE *a1)\n{\n _BYTE *v1; // rax\n _BYTE *result; // rax\n _BYTE *v3; // [rsp+8h] [rbp-18h]\n _BYTE *v4; // [rsp+10h] [rbp-10h]\n\n v3 = a1;\n v4 = a1;\n while ( *v3 )\n {\n if ( !strchr(\"AEIOUaeiou\", (char)*v3) )\n {\n v1 = v4++;\n *v1 = *v3;\n }\n ++v3;\n }\n result = v4;\n *v4 = 0;\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nlea rax, aAeiouaeiou; \"AEIOUaeiou\"\nmov [rbp+s], rax\nmov rax, [rbp+var_18]\nmov [rbp+var_10], rax\njmp short loc_1205\nloc_11CE:\nmov rax, [rbp+var_18]\nmovzx eax, byte ptr [rax]\nmovsx edx, al\nmov rax, [rbp+s]\nmov esi, edx; c\nmov rdi, rax; s\ncall _strchr\ntest rax, rax\njnz short loc_1200\nmov rax, [rbp+var_10]\nlea rdx, [rax+1]\nmov [rbp+var_10], rdx\nmov rdx, [rbp+var_18]\nmovzx edx, byte ptr [rdx]\nmov [rax], dl\nloc_1200:\nadd [rbp+var_18], 1\nloc_1205:\nmov rax, [rbp+var_18]\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_11CE\nmov rax, [rbp+var_10]\nmov byte ptr [rax], 0\nnop\nleave\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_11A9(_BYTE *a1)\n{\n _BYTE *v1; // rax\n _BYTE *result; // rax\n _BYTE *v3; // [rsp+8h] [rbp-18h]\n _BYTE *v4; // [rsp+10h] [rbp-10h]\n\n v3 = a1;\n v4 = a1;\n while ( *v3 )\n {\n if ( !strchr(\"AEIOUaeiou\", (char)*v3) )\n {\n v1 = v4++;\n *v1 = *v3;\n }\n ++v3;\n }\n result = v4;\n *v4 = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_11A9(uint8_t *a1) {\n uint8_t *v1;\n uint8_t *result;\n uint8_t *v3;\n uint8_t *v4;\n v3 = a1;\n v4 = a1;\n while (*v3) {\n if (!strchr(\"AEIOUaeiou\", (char)*v3)) {\n v1 = v4++;\n *v1 = *v3;\n }\n ++v3;\n }\n result = v4;\n *v4 = 0;\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(uint8_t *a1) {\n uint8_t *v1;\n uint8_t *result;\n uint8_t *v3;\n uint8_t *v4;\n v3 = a1;\n v4 = a1;\n while (*v3) {\n if (!strchr(\"AEIOUaeiou\", (char)*v3)) {\n v1 = v4++;\n *v1 = *v3;\n }\n ++v3;\n }\n result = v4;\n *v4 = 0;\n return result;\n}" + }, + { + "index": "HumanEval-C-51", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "void func0(char *text) {\n const char *vowels = \"AEIOUaeiou\";\n char *out = text;\n while (*text != '\\0') {\n if (strchr(vowels, *text) == NULL) {\n *out++ = *text;\n }\n text++;\n }\n *out = '\\0';\n}", + "test": "#include \n#include \n#include \n\nint main() {\n char test1[] = \"\";\n func0(test1);\n assert(strcmp(test1, \"\") == 0);\n \n char test2[] = \"abcdef\\nghijklm\";\n func0(test2);\n assert(strcmp(test2, \"bcdf\\nghjklm\") == 0);\n \n char test3[] = \"fedcba\";\n func0(test3);\n assert(strcmp(test3, \"fdcb\") == 0);\n \n char test4[] = \"eeeee\";\n func0(test4);\n assert(strcmp(test4, \"\") == 0);\n \n char test5[] = \"acBAA\";\n func0(test5);\n assert(strcmp(test5, \"cB\") == 0);\n \n char test6[] = \"EcBOO\";\n func0(test6);\n assert(strcmp(test6, \"cB\") == 0);\n \n char test7[] = \"ybcd\";\n func0(test7);\n assert(strcmp(test7, \"ybcd\") == 0);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmovzx ebp, byte ptr [rdi]\ntest bpl, bpl\njz short loc_11F6\nmov r12, rdi\nlea r13, s; \"AEIOUaeiou\"\njmp short loc_11DA\nloc_11CE:\nadd rbx, 1\nmovzx ebp, byte ptr [rbx]\ntest bpl, bpl\njz short loc_11F9\nloc_11DA:\nmovsx esi, bpl; c\nmov rdi, r13; s\ncall _strchr\ntest rax, rax\njnz short loc_11CE\nmov [r12], bpl\nlea r12, [r12+1]\njmp short loc_11CE\nloc_11F6:\nmov r12, rdi\nloc_11F9:\nmov byte ptr [r12], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "void __fastcall func0(_BYTE *a1)\n{\n _BYTE *v1; // rbx\n char v2; // bp\n _BYTE *v3; // r12\n\n v1 = a1;\n v2 = *a1;\n if ( *a1 )\n {\n v3 = a1;\n do\n {\n if ( !strchr(\"AEIOUaeiou\", v2) )\n *v3++ = v2;\n v2 = *++v1;\n }\n while ( *v1 );\n }\n else\n {\n v3 = a1;\n }\n *v3 = 0;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmovzx ebp, byte ptr [rdi]\ntest bpl, bpl\njz short loc_11F6\nmov r12, rdi\nlea r13, s; \"AEIOUaeiou\"\njmp short loc_11DA\nloc_11CE:\nadd rbx, 1\nmovzx ebp, byte ptr [rbx]\ntest bpl, bpl\njz short loc_11F9\nloc_11DA:\nmovsx esi, bpl; c\nmov rdi, r13; s\ncall _strchr\ntest rax, rax\njnz short loc_11CE\nmov [r12], bpl\nlea r12, [r12+1]\njmp short loc_11CE\nloc_11F6:\nmov r12, rdi\nloc_11F9:\nmov byte ptr [r12], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "void __fastcall sub_11A9(_BYTE *a1)\n{\n _BYTE *v1; // rbx\n char v2; // bp\n _BYTE *v3; // r12\n\n v1 = a1;\n v2 = *a1;\n if ( *a1 )\n {\n v3 = a1;\n do\n {\n if ( !strchr(\"AEIOUaeiou\", v2) )\n *v3++ = v2;\n v2 = *++v1;\n }\n while ( *v1 );\n }\n else\n {\n v3 = a1;\n }\n *v3 = 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_11A9(uint8_t *a1) {\n uint8_t *v1;\n char v2;\n uint8_t *v3;\n v1 = a1;\n v2 = *a1;\n if (*a1) {\n v3 = a1;\n do {\n if (!strchr(\"AEIOUaeiou\", v2)) *v3++ = v2;\n v2 = *++v1;\n } while (*v1);\n } else {\n v3 = a1;\n }\n *v3 = 0;\n}", + "ida_pseudo_norm": "void func0(uint8_t *a1) {\n uint8_t *v1;\n char v2;\n uint8_t *v3;\n v1 = a1;\n v2 = *a1;\n if (*a1) {\n v3 = a1;\n do {\n if (!strchr(\"AEIOUaeiou\", v2)) *v3++ = v2;\n v2 = *++v1;\n } while (*v1);\n } else {\n v3 = a1;\n }\n *v3 = 0;\n}" + }, + { + "index": "HumanEval-C-51", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "void func0(char *text) {\n const char *vowels = \"AEIOUaeiou\";\n char *out = text;\n while (*text != '\\0') {\n if (strchr(vowels, *text) == NULL) {\n *out++ = *text;\n }\n text++;\n }\n *out = '\\0';\n}", + "test": "#include \n#include \n#include \n\nint main() {\n char test1[] = \"\";\n func0(test1);\n assert(strcmp(test1, \"\") == 0);\n \n char test2[] = \"abcdef\\nghijklm\";\n func0(test2);\n assert(strcmp(test2, \"bcdf\\nghjklm\") == 0);\n \n char test3[] = \"fedcba\";\n func0(test3);\n assert(strcmp(test3, \"fdcb\") == 0);\n \n char test4[] = \"eeeee\";\n func0(test4);\n assert(strcmp(test4, \"\") == 0);\n \n char test5[] = \"acBAA\";\n func0(test5);\n assert(strcmp(test5, \"cB\") == 0);\n \n char test6[] = \"EcBOO\";\n func0(test6);\n assert(strcmp(test6, \"cB\") == 0);\n \n char test7[] = \"ybcd\";\n func0(test7);\n assert(strcmp(test7, \"ybcd\") == 0);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 8\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_1468\nmov rbp, rdi\nlea r13, s; \"AEIOUaeiou\"\njmp short loc_1444\nloc_1438:\nmovzx ebx, byte ptr [rbp+1]\nadd rbp, 1\ntest bl, bl\njz short loc_1468\nloc_1444:\nmovsx esi, bl; c\nmov rdi, r13; s\ncall _strchr\ntest rax, rax\njnz short loc_1438\nadd rbp, 1\nmov [r12], bl\nadd r12, 1\nmovzx ebx, byte ptr [rbp+0]\ntest bl, bl\njnz short loc_1444\nloc_1468:\nmov byte ptr [r12], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "void __fastcall func0(_BYTE *a1)\n{\n _BYTE *v1; // r12\n char v2; // bl\n char *v3; // rbp\n\n v1 = a1;\n v2 = *a1;\n if ( *a1 )\n {\n v3 = a1;\n do\n {\n while ( strchr(\"AEIOUaeiou\", v2) )\n {\n v2 = *++v3;\n if ( !v2 )\n goto LABEL_6;\n }\n ++v3;\n *v1++ = v2;\n v2 = *v3;\n }\n while ( *v3 );\n }\nLABEL_6:\n *v1 = 0;\n}", + "ida_strip_asm": "sub_1410:\nendbr64\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 8\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_1468\nmov rbp, rdi\nlea r13, s; \"AEIOUaeiou\"\njmp short loc_1444\nloc_1438:\nmovzx ebx, byte ptr [rbp+1]\nadd rbp, 1\ntest bl, bl\njz short loc_1468\nloc_1444:\nmovsx esi, bl; c\nmov rdi, r13; s\ncall _strchr\ntest rax, rax\njnz short loc_1438\nadd rbp, 1\nmov [r12], bl\nadd r12, 1\nmovzx ebx, byte ptr [rbp+0]\ntest bl, bl\njnz short loc_1444\nloc_1468:\nmov byte ptr [r12], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "void __fastcall sub_1410(_BYTE *a1)\n{\n _BYTE *v1; // r12\n char v2; // bl\n char *v3; // rbp\n\n v1 = a1;\n v2 = *a1;\n if ( *a1 )\n {\n v3 = a1;\n do\n {\n while ( strchr(\"AEIOUaeiou\", v2) )\n {\n v2 = *++v3;\n if ( !v2 )\n goto LABEL_6;\n }\n ++v3;\n *v1++ = v2;\n v2 = *v3;\n }\n while ( *v3 );\n }\nLABEL_6:\n *v1 = 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1410(uint8_t *a1) {\n uint8_t *v1;\n char v2;\n char *v3;\n v1 = a1;\n v2 = *a1;\n if (*a1) {\n v3 = a1;\n do {\n while (strchr(\"AEIOUaeiou\", v2)) {\n v2 = *++v3;\n if (!v2) goto LABEL_6;\n }\n ++v3;\n *v1++ = v2;\n v2 = *v3;\n } while (*v3);\n }\nLABEL_6:\n *v1 = 0;\n}", + "ida_pseudo_norm": "void func0(uint8_t *a1) {\n uint8_t *v1;\n char v2;\n char *v3;\n v1 = a1;\n v2 = *a1;\n if (*a1) {\n v3 = a1;\n do {\n while (strchr(\"AEIOUaeiou\", v2)) {\n v2 = *++v3;\n if (!v2) goto LABEL_6;\n }\n ++v3;\n *v1++ = v2;\n v2 = *v3;\n } while (*v3);\n }\nLABEL_6:\n *v1 = 0;\n}" + }, + { + "index": "HumanEval-C-51", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "void func0(char *text) {\n const char *vowels = \"AEIOUaeiou\";\n char *out = text;\n while (*text != '\\0') {\n if (strchr(vowels, *text) == NULL) {\n *out++ = *text;\n }\n text++;\n }\n *out = '\\0';\n}", + "test": "#include \n#include \n#include \n\nint main() {\n char test1[] = \"\";\n func0(test1);\n assert(strcmp(test1, \"\") == 0);\n \n char test2[] = \"abcdef\\nghijklm\";\n func0(test2);\n assert(strcmp(test2, \"bcdf\\nghjklm\") == 0);\n \n char test3[] = \"fedcba\";\n func0(test3);\n assert(strcmp(test3, \"fdcb\") == 0);\n \n char test4[] = \"eeeee\";\n func0(test4);\n assert(strcmp(test4, \"\") == 0);\n \n char test5[] = \"acBAA\";\n func0(test5);\n assert(strcmp(test5, \"cB\") == 0);\n \n char test6[] = \"EcBOO\";\n func0(test6);\n assert(strcmp(test6, \"cB\") == 0);\n \n char test7[] = \"ybcd\";\n func0(test7);\n assert(strcmp(test7, \"ybcd\") == 0);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 8\nmovzx ebp, byte ptr [rdi]\ntest bpl, bpl\njz short loc_1456\nlea r13, s; \"AEIOUaeiou\"\nnop dword ptr [rax+rax+00h]\nloc_1438:\nmovsx esi, bpl; c\nmov rdi, r13; s\ncall _strchr\ntest rax, rax\njz short loc_1470\nmovzx ebp, byte ptr [rbx+1]\nadd rbx, 1\ntest bpl, bpl\njnz short loc_1438\nloc_1456:\nmov byte ptr [r12], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1470:\nadd rbx, 1\nmov [r12], bpl\nlea rax, [r12+1]\nmovzx ebp, byte ptr [rbx]\nmov r12, rax\ntest bpl, bpl\njnz short loc_1438\nmov byte ptr [r12], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "void __fastcall func0(_BYTE *a1)\n{\n _BYTE *v1; // r12\n char *v2; // rbx\n char v3; // bp\n\n v1 = a1;\n v2 = a1;\n v3 = *a1;\n if ( *a1 )\n {\n do\n {\n while ( strchr(\"AEIOUaeiou\", v3) )\n {\n v3 = *++v2;\n if ( !v3 )\n goto LABEL_4;\n }\n ++v2;\n *v1 = v3;\n v3 = *v2;\n ++v1;\n }\n while ( *v2 );\n *v1 = 0;\n }\n else\n {\nLABEL_4:\n *v1 = 0;\n }\n}", + "ida_strip_asm": "sub_1410:\nendbr64\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 8\nmovzx ebp, byte ptr [rdi]\ntest bpl, bpl\njz short loc_1456\nlea r13, s; \"AEIOUaeiou\"\nnop dword ptr [rax+rax+00h]\nloc_1438:\nmovsx esi, bpl; c\nmov rdi, r13; s\ncall _strchr\ntest rax, rax\njz short loc_1470\nmovzx ebp, byte ptr [rbx+1]\nadd rbx, 1\ntest bpl, bpl\njnz short loc_1438\nloc_1456:\nmov byte ptr [r12], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1470:\nadd rbx, 1\nmov [r12], bpl\nlea rax, [r12+1]\nmovzx ebp, byte ptr [rbx]\nmov r12, rax\ntest bpl, bpl\njnz short loc_1438\nmov byte ptr [r12], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "void __fastcall sub_1410(_BYTE *a1)\n{\n _BYTE *v1; // r12\n char *v2; // rbx\n char v3; // bp\n\n v1 = a1;\n v2 = a1;\n v3 = *a1;\n if ( *a1 )\n {\n do\n {\n while ( strchr(\"AEIOUaeiou\", v3) )\n {\n v3 = *++v2;\n if ( !v3 )\n goto LABEL_4;\n }\n ++v2;\n *v1 = v3;\n v3 = *v2;\n ++v1;\n }\n while ( *v2 );\n *v1 = 0;\n }\n else\n {\nLABEL_4:\n *v1 = 0;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1410(uint8_t *a1) {\n uint8_t *v1;\n char *v2;\n char v3;\n v1 = a1;\n v2 = a1;\n v3 = *a1;\n if (*a1) {\n do {\n while (strchr(\"AEIOUaeiou\", v3)) {\n v3 = *++v2;\n if (!v3) goto LABEL_4;\n }\n ++v2;\n *v1 = v3;\n v3 = *v2;\n ++v1;\n } while (*v2);\n *v1 = 0;\n } else {\n LABEL_4:\n *v1 = 0;\n }\n}", + "ida_pseudo_norm": "void func0(uint8_t *a1) {\n uint8_t *v1;\n char *v2;\n char v3;\n v1 = a1;\n v2 = a1;\n v3 = *a1;\n if (*a1) {\n do {\n while (strchr(\"AEIOUaeiou\", v3)) {\n v3 = *++v2;\n if (!v3) goto LABEL_4;\n }\n ++v2;\n *v1 = v3;\n v3 = *v2;\n ++v1;\n } while (*v2);\n *v1 = 0;\n } else {\n LABEL_4:\n *v1 = 0;\n }\n}" + }, + { + "index": "HumanEval-C-52", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "bool func0(int *l, int size, int t) {\n for (int i = 0; i < size; i++)\n if (l[i] >= t) return false;\n return true;\n}", + "test": "#include \n\nint main() {\n int list1[] = {1, 2, 4, 10};\n assert(func0(list1, 4, 100));\n\n int list2[] = {1, 20, 4, 10};\n assert(!func0(list2, 4, 5));\n \n int list3[] = {1, 20, 4, 10};\n assert(func0(list3, 4, 21));\n \n int list4[] = {1, 20, 4, 10};\n assert(func0(list4, 4, 22));\n \n int list5[] = {1, 8, 4, 10};\n assert(func0(list5, 4, 11));\n \n int list6[] = {1, 8, 4, 10};\n assert(!func0(list6, 4, 10));\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_4], 0\njmp short loc_11AA\nloc_1184:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njg short loc_11A6\nmov eax, 0\njmp short loc_11B7\nloc_11A6:\nadd [rbp+var_4], 1\nloc_11AA:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1184\nmov eax, 1\nloc_11B7:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n int i; // [rsp+1Ch] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n if ( a3 <= *(_DWORD *)(4LL * i + a1) )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_4], 0\njmp short loc_11AA\nloc_1184:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njg short loc_11A6\nmov eax, 0\njmp short loc_11B7\nloc_11A6:\nadd [rbp+var_4], 1\nloc_11AA:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1184\nmov eax, 1\nloc_11B7:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n int i; // [rsp+1Ch] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n if ( a3 <= *(_DWORD *)(4LL * i + a1) )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n int i;\n for (i = 0; i < a2; ++i) {\n if (a3 <= *(uint32_t *)(4LL * i + a1)) return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n int i;\n for (i = 0; i < a2; ++i) {\n if (a3 <= *(uint32_t *)(4LL * i + a1)) return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": "HumanEval-C-52", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "bool func0(int *l, int size, int t) {\n for (int i = 0; i < size; i++)\n if (l[i] >= t) return false;\n return true;\n}", + "test": "#include \n\nint main() {\n int list1[] = {1, 2, 4, 10};\n assert(func0(list1, 4, 100));\n\n int list2[] = {1, 20, 4, 10};\n assert(!func0(list2, 4, 5));\n \n int list3[] = {1, 20, 4, 10};\n assert(func0(list3, 4, 21));\n \n int list4[] = {1, 20, 4, 10};\n assert(func0(list4, 4, 22));\n \n int list5[] = {1, 8, 4, 10};\n assert(func0(list5, 4, 11));\n \n int list6[] = {1, 8, 4, 10};\n assert(!func0(list6, 4, 10));\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_118E\nmov rax, rdi\nmovsxd rsi, esi\nlea rcx, [rdi+rsi*4]\nloc_117B:\ncmp [rax], edx\njge short loc_1194\nadd rax, 4\ncmp rax, rcx\njnz short loc_117B\nmov eax, 1\nretn\nloc_118E:\nmov eax, 1\nretn\nloc_1194:\nmov eax, 0\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2, int a3)\n{\n _DWORD *v3; // rax\n\n if ( a2 <= 0 )\n return 1LL;\n v3 = a1;\n while ( *v3 < a3 )\n {\n if ( ++v3 == &a1[a2] )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_118E\nmov rax, rdi\nmovsxd rsi, esi\nlea rcx, [rdi+rsi*4]\nloc_117B:\ncmp [rax], edx\njge short loc_1194\nadd rax, 4\ncmp rax, rcx\njnz short loc_117B\nmov eax, 1\nretn\nloc_118E:\nmov eax, 1\nretn\nloc_1194:\nmov eax, 0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2, int a3)\n{\n _DWORD *v3; // rax\n\n if ( a2 <= 0 )\n return 1LL;\n v3 = a1;\n while ( *v3 < a3 )\n {\n if ( ++v3 == &a1[a2] )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2, int a3) {\n uint32_t *v3;\n if (a2 <= 0) return 1LL;\n v3 = a1;\n while (*v3 < a3) {\n if (++v3 == &a1[a2]) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2, int a3) {\n uint32_t *v3;\n if (a2 <= 0) return 1LL;\n v3 = a1;\n while (*v3 < a3) {\n if (++v3 == &a1[a2]) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": "HumanEval-C-53", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int x, int y) { return x + y; }", + "test": "#include \n#include \n\nint main() {\n assert(func0(0, 1) == 1);\n assert(func0(1, 0) == 1);\n assert(func0(2, 3) == 5);\n assert(func0(5, 7) == 12);\n assert(func0(7, 5) == 12);\n for (int i = 0; i < 100; i += 1) {\n int x = rand() % 1000;\n int y = rand() % 1000;\n assert(func0(x, y) == x + y);\n }\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov edx, [rbp+var_4]\nmov eax, [rbp+var_8]\nadd eax, edx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n return (unsigned int)(a1 + a2);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov edx, [rbp+var_4]\nmov eax, [rbp+var_8]\nadd eax, edx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1, int a2)\n{\n return (unsigned int)(a1 + a2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1, int a2) { return (unsigned int)(a1 + a2); }", + "ida_pseudo_norm": "long long func0(int a1, int a2) { return (unsigned int)(a1 + a2); }" + }, + { + "index": "HumanEval-C-54", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "bool func0(const char *s0, const char *s1) {\n int len0 = strlen(s0), len1 = strlen(s1);\n for (int i = 0; i < len0; i++) {\n bool found = false;\n for (int j = 0; j < len1; j++) {\n if (s0[i] == s1[j]) {\n found = true;\n break;\n }\n }\n if (!found) return false;\n }\n for (int i = 0; i < len1; i++) {\n bool found = false;\n for (int j = 0; j < len0; j++) {\n if (s1[i] == s0[j]) {\n found = true;\n break;\n }\n }\n if (!found) return false;\n }\n return true;\n}", + "test": "#include \n#include \n\nint main() {\n assert(func0(\"eabcdzzzz\", \"dddzzzzzzzddeddabc\") == true);\n assert(func0(\"abcd\", \"dddddddabc\") == true);\n assert(func0(\"dddddddabc\", \"abcd\") == true);\n assert(func0(\"eabcd\", \"dddddddabc\") == false);\n assert(func0(\"abcd\", \"dddddddabce\") == false);\n assert(func0(\"eabcdzzzz\", \"dddzzzzzzzddddabc\") == false);\n assert(func0(\"aabb\", \"aaccc\") == false);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov [rbp+var_30], rsi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_8], eax\nmov rax, [rbp+var_30]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_18], 0\njmp short loc_11FD\nloc_11A4:\nmov [rbp+var_1A], 0\nmov [rbp+var_14], 0\njmp short loc_11DF\nloc_11B1:\nmov eax, [rbp+var_18]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_14]\nmovsxd rcx, eax\nmov rax, [rbp+var_30]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njnz short loc_11DB\nmov [rbp+var_1A], 1\njmp short loc_11E7\nloc_11DB:\nadd [rbp+var_14], 1\nloc_11DF:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_4]\njl short loc_11B1\nloc_11E7:\nmovzx eax, [rbp+var_1A]\nxor eax, 1\ntest al, al\njz short loc_11F9\nmov eax, 0\njmp short locret_1274\nloc_11F9:\nadd [rbp+var_18], 1\nloc_11FD:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_8]\njl short loc_11A4\nmov [rbp+var_10], 0\njmp short loc_1267\nloc_120E:\nmov [rbp+var_19], 0\nmov [rbp+var_C], 0\njmp short loc_1249\nloc_121B:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_C]\nmovsxd rcx, eax\nmov rax, [rbp+s]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njnz short loc_1245\nmov [rbp+var_19], 1\njmp short loc_1251\nloc_1245:\nadd [rbp+var_C], 1\nloc_1249:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_8]\njl short loc_121B\nloc_1251:\nmovzx eax, [rbp+var_19]\nxor eax, 1\ntest al, al\njz short loc_1263\nmov eax, 0\njmp short locret_1274\nloc_1263:\nadd [rbp+var_10], 1\nloc_1267:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_4]\njl short loc_120E\nmov eax, 1\nlocret_1274:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, const char *a2)\n{\n char v3; // [rsp+16h] [rbp-1Ah]\n char v4; // [rsp+17h] [rbp-19h]\n int i; // [rsp+18h] [rbp-18h]\n int j; // [rsp+1Ch] [rbp-14h]\n int k; // [rsp+20h] [rbp-10h]\n int m; // [rsp+24h] [rbp-Ch]\n int v9; // [rsp+28h] [rbp-8h]\n int v10; // [rsp+2Ch] [rbp-4h]\n\n v9 = strlen(a1);\n v10 = strlen(a2);\n for ( i = 0; i < v9; ++i )\n {\n v3 = 0;\n for ( j = 0; j < v10; ++j )\n {\n if ( a1[i] == a2[j] )\n {\n v3 = 1;\n break;\n }\n }\n if ( v3 != 1 )\n return 0LL;\n }\n for ( k = 0; k < v10; ++k )\n {\n v4 = 0;\n for ( m = 0; m < v9; ++m )\n {\n if ( a2[k] == a1[m] )\n {\n v4 = 1;\n break;\n }\n }\n if ( v4 != 1 )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov [rbp+var_30], rsi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_8], eax\nmov rax, [rbp+var_30]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_18], 0\njmp short loc_11FD\nloc_11A4:\nmov [rbp+var_1A], 0\nmov [rbp+var_14], 0\njmp short loc_11DF\nloc_11B1:\nmov eax, [rbp+var_18]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_14]\nmovsxd rcx, eax\nmov rax, [rbp+var_30]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njnz short loc_11DB\nmov [rbp+var_1A], 1\njmp short loc_11E7\nloc_11DB:\nadd [rbp+var_14], 1\nloc_11DF:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_4]\njl short loc_11B1\nloc_11E7:\nmovzx eax, [rbp+var_1A]\nxor eax, 1\ntest al, al\njz short loc_11F9\nmov eax, 0\njmp short locret_1274\nloc_11F9:\nadd [rbp+var_18], 1\nloc_11FD:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_8]\njl short loc_11A4\nmov [rbp+var_10], 0\njmp short loc_1267\nloc_120E:\nmov [rbp+var_19], 0\nmov [rbp+var_C], 0\njmp short loc_1249\nloc_121B:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_C]\nmovsxd rcx, eax\nmov rax, [rbp+s]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njnz short loc_1245\nmov [rbp+var_19], 1\njmp short loc_1251\nloc_1245:\nadd [rbp+var_C], 1\nloc_1249:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_8]\njl short loc_121B\nloc_1251:\nmovzx eax, [rbp+var_19]\nxor eax, 1\ntest al, al\njz short loc_1263\nmov eax, 0\njmp short locret_1274\nloc_1263:\nadd [rbp+var_10], 1\nloc_1267:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_4]\njl short loc_120E\nmov eax, 1\nlocret_1274:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1, const char *a2)\n{\n char v3; // [rsp+16h] [rbp-1Ah]\n char v4; // [rsp+17h] [rbp-19h]\n int i; // [rsp+18h] [rbp-18h]\n int j; // [rsp+1Ch] [rbp-14h]\n int k; // [rsp+20h] [rbp-10h]\n int m; // [rsp+24h] [rbp-Ch]\n int v9; // [rsp+28h] [rbp-8h]\n int v10; // [rsp+2Ch] [rbp-4h]\n\n v9 = strlen(a1);\n v10 = strlen(a2);\n for ( i = 0; i < v9; ++i )\n {\n v3 = 0;\n for ( j = 0; j < v10; ++j )\n {\n if ( a1[i] == a2[j] )\n {\n v3 = 1;\n break;\n }\n }\n if ( v3 != 1 )\n return 0LL;\n }\n for ( k = 0; k < v10; ++k )\n {\n v4 = 0;\n for ( m = 0; m < v9; ++m )\n {\n if ( a2[k] == a1[m] )\n {\n v4 = 1;\n break;\n }\n }\n if ( v4 != 1 )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1, const char *a2) {\n char v3;\n char v4;\n int i;\n int j;\n int k;\n int m;\n int v9;\n int v10;\n v9 = strlen(a1);\n v10 = strlen(a2);\n for (i = 0; i < v9; ++i) {\n v3 = 0;\n for (j = 0; j < v10; ++j) {\n if (a1[i] == a2[j]) {\n v3 = 1;\n break;\n }\n }\n if (v3 != 1) return 0LL;\n }\n for (k = 0; k < v10; ++k) {\n v4 = 0;\n for (m = 0; m < v9; ++m) {\n if (a2[k] == a1[m]) {\n v4 = 1;\n break;\n }\n }\n if (v4 != 1) return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, const char *a2) {\n char v3;\n char v4;\n int i;\n int j;\n int k;\n int m;\n int v9;\n int v10;\n v9 = strlen(a1);\n v10 = strlen(a2);\n for (i = 0; i < v9; ++i) {\n v3 = 0;\n for (j = 0; j < v10; ++j) {\n if (a1[i] == a2[j]) {\n v3 = 1;\n break;\n }\n }\n if (v3 != 1) return 0LL;\n }\n for (k = 0; k < v10; ++k) {\n v4 = 0;\n for (m = 0; m < v9; ++m) {\n if (a2[k] == a1[m]) {\n v4 = 1;\n break;\n }\n }\n if (v4 != 1) return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": "HumanEval-C-54", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "bool func0(const char *s0, const char *s1) {\n int len0 = strlen(s0), len1 = strlen(s1);\n for (int i = 0; i < len0; i++) {\n bool found = false;\n for (int j = 0; j < len1; j++) {\n if (s0[i] == s1[j]) {\n found = true;\n break;\n }\n }\n if (!found) return false;\n }\n for (int i = 0; i < len1; i++) {\n bool found = false;\n for (int j = 0; j < len0; j++) {\n if (s1[i] == s0[j]) {\n found = true;\n break;\n }\n }\n if (!found) return false;\n }\n return true;\n}", + "test": "#include \n#include \n\nint main() {\n assert(func0(\"eabcdzzzz\", \"dddzzzzzzzddeddabc\") == true);\n assert(func0(\"abcd\", \"dddddddabc\") == true);\n assert(func0(\"dddddddabc\", \"abcd\") == true);\n assert(func0(\"eabcd\", \"dddddddabc\") == false);\n assert(func0(\"abcd\", \"dddddddabce\") == false);\n assert(func0(\"eabcdzzzz\", \"dddzzzzzzzddddabc\") == false);\n assert(func0(\"aabb\", \"aaccc\") == false);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov rbx, rsi\ncall _strlen\nmov r13, rax\nmov r12d, eax\nmov rdi, rbx; s\ncall _strlen\nmov r10, rax\ntest r13d, r13d\njle short loc_11EA\nmov r8d, eax\nmov rdi, rbp\nlea eax, [r13-1]\nlea r9, [rbp+rax+1]\nlea eax, [r10-1]\nlea rsi, [rbx+rax+1]\njmp short loc_11BB\nloc_11B2:\nadd rdi, 1\ncmp rdi, r9\njz short loc_11F4\nloc_11BB:\ntest r8d, r8d\njle short loc_11E3\nmovzx ecx, byte ptr [rdi]\nmov rdx, rbx\nloc_11C6:\ncmp cl, [rdx]\njz short loc_11B2\nadd rdx, 1\ncmp rdx, rsi\njnz short loc_11C6\nmov eax, 0\nloc_11D8:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_11E3:\nmov eax, 0\njmp short loc_11D8\nloc_11EA:\nmov eax, 1\ntest r10d, r10d\njle short loc_11D8\nloc_11F4:\nmov rsi, rbx\nlea eax, [r10-1]\nlea rdi, [rbx+rax+1]\nlea eax, [r13-1]\nlea rcx, [rbp+rax+1]\njmp short loc_1214\nloc_120B:\nadd rsi, 1\ncmp rsi, rdi\njz short loc_123A\nloc_1214:\ntest r12d, r12d\njle short loc_1233\nmovzx edx, byte ptr [rsi]\nmov rax, rbp\nloc_121F:\ncmp dl, [rax]\njz short loc_120B\nadd rax, 1\ncmp rax, rcx\njnz short loc_121F\nmov eax, 0\njmp short loc_11D8\nloc_1233:\nmov eax, 0\njmp short loc_11D8\nloc_123A:\nmov eax, 1\njmp short loc_11D8", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, const char *a2)\n{\n const char *v2; // rbp\n int v4; // r13d\n int v5; // eax\n int v6; // r10d\n __int64 v7; // rsi\n const char *v8; // rdx\n __int64 result; // rax\n const char *v10; // rsi\n const char *v11; // rax\n\n v2 = a1;\n v4 = strlen(a1);\n v5 = strlen(a2);\n v6 = v5;\n if ( v4 <= 0 )\n {\n result = 1LL;\n if ( v6 > 0 )\n {\nLABEL_12:\n v10 = a2;\n while ( 2 )\n {\n if ( v4 <= 0 )\n {\n return 0LL;\n }\n else\n {\n v11 = v2;\n while ( *v10 != *v11 )\n {\n if ( ++v11 == &v2[v4 - 1 + 1] )\n return 0LL;\n }\n if ( ++v10 != &a2[v6 - 1 + 1] )\n continue;\n return 1LL;\n }\n }\n }\n }\n else\n {\n v7 = (__int64)&a2[v5 - 1 + 1];\n while ( v5 > 0 )\n {\n v8 = a2;\n while ( *a1 != *v8 )\n {\n if ( ++v8 == (const char *)v7 )\n return 0LL;\n }\n if ( ++a1 == &v2[v4 - 1 + 1] )\n goto LABEL_12;\n }\n return 0LL;\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov rbx, rsi\ncall _strlen\nmov r13, rax\nmov r12d, eax\nmov rdi, rbx; s\ncall _strlen\nmov r10, rax\ntest r13d, r13d\njle short loc_11EA\nmov r8d, eax\nmov rdi, rbp\nlea eax, [r13-1]\nlea r9, [rbp+rax+1]\nlea eax, [r10-1]\nlea rsi, [rbx+rax+1]\njmp short loc_11BB\nloc_11B2:\nadd rdi, 1\ncmp rdi, r9\njz short loc_11F4\nloc_11BB:\ntest r8d, r8d\njle short loc_11E3\nmovzx ecx, byte ptr [rdi]\nmov rdx, rbx\nloc_11C6:\ncmp cl, [rdx]\njz short loc_11B2\nadd rdx, 1\ncmp rdx, rsi\njnz short loc_11C6\nmov eax, 0\nloc_11D8:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_11E3:\nmov eax, 0\njmp short loc_11D8\nloc_11EA:\nmov eax, 1\ntest r10d, r10d\njle short loc_11D8\nloc_11F4:\nmov rsi, rbx\nlea eax, [r10-1]\nlea rdi, [rbx+rax+1]\nlea eax, [r13-1]\nlea rcx, [rbp+rax+1]\njmp short loc_1214\nloc_120B:\nadd rsi, 1\ncmp rsi, rdi\njz short loc_123A\nloc_1214:\ntest r12d, r12d\njle short loc_1233\nmovzx edx, byte ptr [rsi]\nmov rax, rbp\nloc_121F:\ncmp dl, [rax]\njz short loc_120B\nadd rax, 1\ncmp rax, rcx\njnz short loc_121F\nmov eax, 0\njmp short loc_11D8\nloc_1233:\nmov eax, 0\njmp short loc_11D8\nloc_123A:\nmov eax, 1\njmp short loc_11D8", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1, const char *a2)\n{\n const char *v2; // rbp\n int v4; // r13d\n int v5; // eax\n int v6; // r10d\n __int64 v7; // rsi\n const char *v8; // rdx\n __int64 result; // rax\n const char *v10; // rsi\n const char *v11; // rax\n\n v2 = a1;\n v4 = strlen(a1);\n v5 = strlen(a2);\n v6 = v5;\n if ( v4 <= 0 )\n {\n result = 1LL;\n if ( v6 > 0 )\n {\nLABEL_12:\n v10 = a2;\n while ( 2 )\n {\n if ( v4 <= 0 )\n {\n return 0LL;\n }\n else\n {\n v11 = v2;\n while ( *v10 != *v11 )\n {\n if ( ++v11 == &v2[v4 - 1 + 1] )\n return 0LL;\n }\n if ( ++v10 != &a2[v6 - 1 + 1] )\n continue;\n return 1LL;\n }\n }\n }\n }\n else\n {\n v7 = (__int64)&a2[v5 - 1 + 1];\n while ( v5 > 0 )\n {\n v8 = a2;\n while ( *a1 != *v8 )\n {\n if ( ++v8 == (const char *)v7 )\n return 0LL;\n }\n if ( ++a1 == &v2[v4 - 1 + 1] )\n goto LABEL_12;\n }\n return 0LL;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1, const char *a2) {\n const char *v2;\n int v4;\n int v5;\n int v6;\n long long v7;\n const char *v8;\n long long result;\n const char *v10;\n const char *v11;\n v2 = a1;\n v4 = strlen(a1);\n v5 = strlen(a2);\n v6 = v5;\n if (v4 <= 0) {\n result = 1LL;\n if (v6 > 0) {\n LABEL_12:\n v10 = a2;\n while (2) {\n if (v4 <= 0) {\n return 0LL;\n } else {\n v11 = v2;\n while (*v10 != *v11) {\n if (++v11 == &v2[v4 - 1 + 1]) return 0LL;\n }\n if (++v10 != &a2[v6 - 1 + 1]) continue;\n return 1LL;\n }\n }\n }\n } else {\n v7 = (long long)&a2[v5 - 1 + 1];\n while (v5 > 0) {\n v8 = a2;\n while (*a1 != *v8) {\n if (++v8 == (const char *)v7) return 0LL;\n }\n if (++a1 == &v2[v4 - 1 + 1]) goto LABEL_12;\n }\n return 0LL;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, const char *a2) {\n const char *v2;\n int v4;\n int v5;\n int v6;\n long long v7;\n const char *v8;\n long long result;\n const char *v10;\n const char *v11;\n v2 = a1;\n v4 = strlen(a1);\n v5 = strlen(a2);\n v6 = v5;\n if (v4 <= 0) {\n result = 1LL;\n if (v6 > 0) {\n LABEL_12:\n v10 = a2;\n while (2) {\n if (v4 <= 0) {\n return 0LL;\n } else {\n v11 = v2;\n while (*v10 != *v11) {\n if (++v11 == &v2[v4 - 1 + 1]) return 0LL;\n }\n if (++v10 != &a2[v6 - 1 + 1]) continue;\n return 1LL;\n }\n }\n }\n } else {\n v7 = (long long)&a2[v5 - 1 + 1];\n while (v5 > 0) {\n v8 = a2;\n while (*a1 != *v8) {\n if (++v8 == (const char *)v7) return 0LL;\n }\n if (++a1 == &v2[v4 - 1 + 1]) goto LABEL_12;\n }\n return 0LL;\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-54", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "bool func0(const char *s0, const char *s1) {\n int len0 = strlen(s0), len1 = strlen(s1);\n for (int i = 0; i < len0; i++) {\n bool found = false;\n for (int j = 0; j < len1; j++) {\n if (s0[i] == s1[j]) {\n found = true;\n break;\n }\n }\n if (!found) return false;\n }\n for (int i = 0; i < len1; i++) {\n bool found = false;\n for (int j = 0; j < len0; j++) {\n if (s1[i] == s0[j]) {\n found = true;\n break;\n }\n }\n if (!found) return false;\n }\n return true;\n}", + "test": "#include \n#include \n\nint main() {\n assert(func0(\"eabcdzzzz\", \"dddzzzzzzzddeddabc\") == true);\n assert(func0(\"abcd\", \"dddddddabc\") == true);\n assert(func0(\"dddddddabc\", \"abcd\") == true);\n assert(func0(\"eabcd\", \"dddddddabc\") == false);\n assert(func0(\"abcd\", \"dddddddabce\") == false);\n assert(func0(\"eabcdzzzz\", \"dddzzzzzzzddddabc\") == false);\n assert(func0(\"aabb\", \"aaccc\") == false);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nmov rbx, rsi\ncall _strlen\nmov rdi, rbx; s\nmov r12, rax\ncall _strlen\nmov rdx, rax\ntest r12d, r12d\njle loc_13D7\nlea eax, [r12-1]\nmov rsi, rbp\nlea rdi, [rbp+rax+1]\ntest edx, edx\njle loc_13D0\nlea ecx, [rdx-1]\nlea r8, [rbx+1]\nmov r9, rcx\nadd rcx, r8\nnop dword ptr [rax+00h]\nloc_1360:\nmovzx edx, byte ptr [rsi]\nmov rax, rbx\njmp short loc_1379\nloc_1370:\nadd rax, 1\ncmp rax, rcx\njz short loc_13D0\nloc_1379:\ncmp dl, [rax]\njnz short loc_1370\nadd rsi, 1\ncmp rsi, rdi\njnz short loc_1360\nloc_1386:\nmov rsi, rbx\nlea rdi, [r8+r9]\ntest r12d, r12d\njle short loc_13D0\nlea eax, [r12-1]\nlea rcx, [rbp+rax+1]\nnop dword ptr [rax+00h]\nloc_13A0:\nmovzx edx, byte ptr [rsi]\nmov rax, rbp\njmp short loc_13B9\nloc_13B0:\nadd rax, 1\ncmp rax, rcx\njz short loc_13D0\nloc_13B9:\ncmp dl, [rax]\njnz short loc_13B0\nadd rsi, 1\ncmp rsi, rdi\njnz short loc_13A0\npop rbx\nmov eax, 1\npop rbp\npop r12\nretn\nloc_13D0:\nxor eax, eax\nloc_13D2:\npop rbx\npop rbp\npop r12\nretn\nloc_13D7:\nmov eax, 1\ntest edx, edx\njle short loc_13D2\nlea r8, [rbx+1]\nlea r9d, [rdx-1]\njmp short loc_1386", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, const char *a2)\n{\n int v3; // r12d\n int v4; // edx\n const char *v5; // rsi\n const char *v6; // r8\n __int64 v7; // r9\n const char *v8; // rax\n const char *v9; // rsi\n const char *v10; // rax\n __int64 result; // rax\n\n v3 = strlen(a1);\n v4 = strlen(a2);\n if ( v3 <= 0 )\n {\n result = 1LL;\n if ( v4 <= 0 )\n return result;\n v6 = a2 + 1;\n v7 = (unsigned int)(v4 - 1);\n }\n else\n {\n v5 = a1;\n if ( v4 <= 0 )\n return 0LL;\n v6 = a2 + 1;\n v7 = (unsigned int)(v4 - 1);\n do\n {\n v8 = a2;\n while ( *v5 != *v8 )\n {\n if ( ++v8 == &a2[v7 + 1] )\n return 0LL;\n }\n ++v5;\n }\n while ( v5 != &a1[v3 - 1 + 1] );\n }\n v9 = a2;\n if ( v3 <= 0 )\n return 0LL;\n do\n {\n v10 = a1;\n while ( *v9 != *v10 )\n {\n if ( ++v10 == &a1[v3 - 1 + 1] )\n return 0LL;\n }\n ++v9;\n }\n while ( v9 != &v6[v7] );\n return 1LL;\n}", + "ida_strip_asm": "sub_1310:\nendbr64\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nmov rbx, rsi\ncall _strlen\nmov rdi, rbx; s\nmov r12, rax\ncall _strlen\nmov rdx, rax\ntest r12d, r12d\njle loc_13D7\nlea eax, [r12-1]\nmov rsi, rbp\nlea rdi, [rbp+rax+1]\ntest edx, edx\njle loc_13D0\nlea ecx, [rdx-1]\nlea r8, [rbx+1]\nmov r9, rcx\nadd rcx, r8\nnop dword ptr [rax+00h]\nloc_1360:\nmovzx edx, byte ptr [rsi]\nmov rax, rbx\njmp short loc_1379\nloc_1370:\nadd rax, 1\ncmp rax, rcx\njz short loc_13D0\nloc_1379:\ncmp dl, [rax]\njnz short loc_1370\nadd rsi, 1\ncmp rsi, rdi\njnz short loc_1360\nloc_1386:\nmov rsi, rbx\nlea rdi, [r8+r9]\ntest r12d, r12d\njle short loc_13D0\nlea eax, [r12-1]\nlea rcx, [rbp+rax+1]\nnop dword ptr [rax+00h]\nloc_13A0:\nmovzx edx, byte ptr [rsi]\nmov rax, rbp\njmp short loc_13B9\nloc_13B0:\nadd rax, 1\ncmp rax, rcx\njz short loc_13D0\nloc_13B9:\ncmp dl, [rax]\njnz short loc_13B0\nadd rsi, 1\ncmp rsi, rdi\njnz short loc_13A0\npop rbx\nmov eax, 1\npop rbp\npop r12\nretn\nloc_13D0:\nxor eax, eax\nloc_13D2:\npop rbx\npop rbp\npop r12\nretn\nloc_13D7:\nmov eax, 1\ntest edx, edx\njle short loc_13D2\nlea r8, [rbx+1]\nlea r9d, [rdx-1]\njmp short loc_1386", + "ida_strip_pseudo": "__int64 __fastcall sub_1310(const char *a1, const char *a2)\n{\n int v3; // r12d\n int v4; // edx\n const char *v5; // rsi\n const char *v6; // r8\n __int64 v7; // r9\n const char *v8; // rax\n const char *v9; // rsi\n const char *v10; // rax\n __int64 result; // rax\n\n v3 = strlen(a1);\n v4 = strlen(a2);\n if ( v3 <= 0 )\n {\n result = 1LL;\n if ( v4 <= 0 )\n return result;\n v6 = a2 + 1;\n v7 = (unsigned int)(v4 - 1);\n }\n else\n {\n v5 = a1;\n if ( v4 <= 0 )\n return 0LL;\n v6 = a2 + 1;\n v7 = (unsigned int)(v4 - 1);\n do\n {\n v8 = a2;\n while ( *v5 != *v8 )\n {\n if ( ++v8 == &a2[v7 + 1] )\n return 0LL;\n }\n ++v5;\n }\n while ( v5 != &a1[v3 - 1 + 1] );\n }\n v9 = a2;\n if ( v3 <= 0 )\n return 0LL;\n do\n {\n v10 = a1;\n while ( *v9 != *v10 )\n {\n if ( ++v10 == &a1[v3 - 1 + 1] )\n return 0LL;\n }\n ++v9;\n }\n while ( v9 != &v6[v7] );\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1310(const char *a1, const char *a2) {\n int v3;\n int v4;\n const char *v5;\n const char *v6;\n long long v7;\n const char *v8;\n const char *v9;\n const char *v10;\n long long result;\n v3 = strlen(a1);\n v4 = strlen(a2);\n if (v3 <= 0) {\n result = 1LL;\n if (v4 <= 0) return result;\n v6 = a2 + 1;\n v7 = (unsigned int)(v4 - 1);\n } else {\n v5 = a1;\n if (v4 <= 0) return 0LL;\n v6 = a2 + 1;\n v7 = (unsigned int)(v4 - 1);\n do {\n v8 = a2;\n while (*v5 != *v8) {\n if (++v8 == &a2[v7 + 1]) return 0LL;\n }\n ++v5;\n } while (v5 != &a1[v3 - 1 + 1]);\n }\n v9 = a2;\n if (v3 <= 0) return 0LL;\n do {\n v10 = a1;\n while (*v9 != *v10) {\n if (++v10 == &a1[v3 - 1 + 1]) return 0LL;\n }\n ++v9;\n } while (v9 != &v6[v7]);\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, const char *a2) {\n int v3;\n int v4;\n const char *v5;\n const char *v6;\n long long v7;\n const char *v8;\n const char *v9;\n const char *v10;\n long long result;\n v3 = strlen(a1);\n v4 = strlen(a2);\n if (v3 <= 0) {\n result = 1LL;\n if (v4 <= 0) return result;\n v6 = a2 + 1;\n v7 = (unsigned int)(v4 - 1);\n } else {\n v5 = a1;\n if (v4 <= 0) return 0LL;\n v6 = a2 + 1;\n v7 = (unsigned int)(v4 - 1);\n do {\n v8 = a2;\n while (*v5 != *v8) {\n if (++v8 == &a2[v7 + 1]) return 0LL;\n }\n ++v5;\n } while (v5 != &a1[v3 - 1 + 1]);\n }\n v9 = a2;\n if (v3 <= 0) return 0LL;\n do {\n v10 = a1;\n while (*v9 != *v10) {\n if (++v10 == &a1[v3 - 1 + 1]) return 0LL;\n }\n ++v9;\n } while (v9 != &v6[v7]);\n return 1LL;\n}" + }, + { + "index": "HumanEval-C-54", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "bool func0(const char *s0, const char *s1) {\n int len0 = strlen(s0), len1 = strlen(s1);\n for (int i = 0; i < len0; i++) {\n bool found = false;\n for (int j = 0; j < len1; j++) {\n if (s0[i] == s1[j]) {\n found = true;\n break;\n }\n }\n if (!found) return false;\n }\n for (int i = 0; i < len1; i++) {\n bool found = false;\n for (int j = 0; j < len0; j++) {\n if (s1[i] == s0[j]) {\n found = true;\n break;\n }\n }\n if (!found) return false;\n }\n return true;\n}", + "test": "#include \n#include \n\nint main() {\n assert(func0(\"eabcdzzzz\", \"dddzzzzzzzddeddabc\") == true);\n assert(func0(\"abcd\", \"dddddddabc\") == true);\n assert(func0(\"dddddddabc\", \"abcd\") == true);\n assert(func0(\"eabcd\", \"dddddddabc\") == false);\n assert(func0(\"abcd\", \"dddddddabce\") == false);\n assert(func0(\"eabcdzzzz\", \"dddzzzzzzzddddabc\") == false);\n assert(func0(\"aabb\", \"aaccc\") == false);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nmov rbx, rsi\ncall _strlen\nmov rdi, rbx; s\nmov r12, rax\ncall _strlen\nmov rdx, rax\ntest r12d, r12d\njle loc_13D7\nlea eax, [r12-1]\nmov rsi, rbp\nlea rdi, [rbp+rax+1]\ntest edx, edx\njle loc_13D0\nlea ecx, [rdx-1]\nlea r8, [rbx+1]\nmov r9, rcx\nadd rcx, r8\nnop dword ptr [rax+00h]\nloc_1360:\nmovzx edx, byte ptr [rsi]\nmov rax, rbx\njmp short loc_1379\nloc_1370:\nadd rax, 1\ncmp rax, rcx\njz short loc_13D0\nloc_1379:\ncmp dl, [rax]\njnz short loc_1370\nadd rsi, 1\ncmp rsi, rdi\njnz short loc_1360\nloc_1386:\nmov rsi, rbx\nlea rdi, [r8+r9]\ntest r12d, r12d\njle short loc_13D0\nlea eax, [r12-1]\nlea rcx, [rbp+rax+1]\nnop dword ptr [rax+00h]\nloc_13A0:\nmovzx edx, byte ptr [rsi]\nmov rax, rbp\njmp short loc_13B9\nloc_13B0:\nadd rax, 1\ncmp rcx, rax\njz short loc_13D0\nloc_13B9:\ncmp dl, [rax]\njnz short loc_13B0\nadd rsi, 1\ncmp rsi, rdi\njnz short loc_13A0\npop rbx\nmov eax, 1\npop rbp\npop r12\nretn\nloc_13D0:\nxor eax, eax\nloc_13D2:\npop rbx\npop rbp\npop r12\nretn\nloc_13D7:\nmov eax, 1\ntest edx, edx\njle short loc_13D2\nlea r8, [rbx+1]\nlea r9d, [rdx-1]\njmp short loc_1386", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, const char *a2)\n{\n int v3; // r12d\n int v4; // edx\n const char *v5; // rsi\n const char *v6; // r8\n __int64 v7; // r9\n const char *v8; // rax\n const char *v9; // rsi\n const char *v10; // rax\n __int64 result; // rax\n\n v3 = strlen(a1);\n v4 = strlen(a2);\n if ( v3 <= 0 )\n {\n result = 1LL;\n if ( v4 <= 0 )\n return result;\n v6 = a2 + 1;\n v7 = (unsigned int)(v4 - 1);\n }\n else\n {\n v5 = a1;\n if ( v4 <= 0 )\n return 0LL;\n v6 = a2 + 1;\n v7 = (unsigned int)(v4 - 1);\n do\n {\n v8 = a2;\n while ( *v5 != *v8 )\n {\n if ( ++v8 == &a2[v7 + 1] )\n return 0LL;\n }\n ++v5;\n }\n while ( v5 != &a1[v3 - 1 + 1] );\n }\n v9 = a2;\n if ( v3 <= 0 )\n return 0LL;\n do\n {\n v10 = a1;\n while ( *v9 != *v10 )\n {\n if ( &a1[v3 - 1 + 1] == ++v10 )\n return 0LL;\n }\n ++v9;\n }\n while ( v9 != &v6[v7] );\n return 1LL;\n}", + "ida_strip_asm": "sub_1310:\nendbr64\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nmov rbx, rsi\ncall _strlen\nmov rdi, rbx; s\nmov r12, rax\ncall _strlen\nmov rdx, rax\ntest r12d, r12d\njle loc_13D7\nlea eax, [r12-1]\nmov rsi, rbp\nlea rdi, [rbp+rax+1]\ntest edx, edx\njle loc_13D0\nlea ecx, [rdx-1]\nlea r8, [rbx+1]\nmov r9, rcx\nadd rcx, r8\nnop dword ptr [rax+00h]\nloc_1360:\nmovzx edx, byte ptr [rsi]\nmov rax, rbx\njmp short loc_1379\nloc_1370:\nadd rax, 1\ncmp rax, rcx\njz short loc_13D0\nloc_1379:\ncmp dl, [rax]\njnz short loc_1370\nadd rsi, 1\ncmp rsi, rdi\njnz short loc_1360\nloc_1386:\nmov rsi, rbx\nlea rdi, [r8+r9]\ntest r12d, r12d\njle short loc_13D0\nlea eax, [r12-1]\nlea rcx, [rbp+rax+1]\nnop dword ptr [rax+00h]\nloc_13A0:\nmovzx edx, byte ptr [rsi]\nmov rax, rbp\njmp short loc_13B9\nloc_13B0:\nadd rax, 1\ncmp rcx, rax\njz short loc_13D0\nloc_13B9:\ncmp dl, [rax]\njnz short loc_13B0\nadd rsi, 1\ncmp rsi, rdi\njnz short loc_13A0\npop rbx\nmov eax, 1\npop rbp\npop r12\nretn\nloc_13D0:\nxor eax, eax\nloc_13D2:\npop rbx\npop rbp\npop r12\nretn\nloc_13D7:\nmov eax, 1\ntest edx, edx\njle short loc_13D2\nlea r8, [rbx+1]\nlea r9d, [rdx-1]\njmp short loc_1386", + "ida_strip_pseudo": "__int64 __fastcall sub_1310(const char *a1, const char *a2)\n{\n int v3; // r12d\n int v4; // edx\n const char *v5; // rsi\n const char *v6; // r8\n __int64 v7; // r9\n const char *v8; // rax\n const char *v9; // rsi\n const char *v10; // rax\n __int64 result; // rax\n\n v3 = strlen(a1);\n v4 = strlen(a2);\n if ( v3 <= 0 )\n {\n result = 1LL;\n if ( v4 <= 0 )\n return result;\n v6 = a2 + 1;\n v7 = (unsigned int)(v4 - 1);\n }\n else\n {\n v5 = a1;\n if ( v4 <= 0 )\n return 0LL;\n v6 = a2 + 1;\n v7 = (unsigned int)(v4 - 1);\n do\n {\n v8 = a2;\n while ( *v5 != *v8 )\n {\n if ( ++v8 == &a2[v7 + 1] )\n return 0LL;\n }\n ++v5;\n }\n while ( v5 != &a1[v3 - 1 + 1] );\n }\n v9 = a2;\n if ( v3 <= 0 )\n return 0LL;\n do\n {\n v10 = a1;\n while ( *v9 != *v10 )\n {\n if ( &a1[v3 - 1 + 1] == ++v10 )\n return 0LL;\n }\n ++v9;\n }\n while ( v9 != &v6[v7] );\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1310(const char *a1, const char *a2) {\n int v3;\n int v4;\n const char *v5;\n const char *v6;\n long long v7;\n const char *v8;\n const char *v9;\n const char *v10;\n long long result;\n v3 = strlen(a1);\n v4 = strlen(a2);\n if (v3 <= 0) {\n result = 1LL;\n if (v4 <= 0) return result;\n v6 = a2 + 1;\n v7 = (unsigned int)(v4 - 1);\n } else {\n v5 = a1;\n if (v4 <= 0) return 0LL;\n v6 = a2 + 1;\n v7 = (unsigned int)(v4 - 1);\n do {\n v8 = a2;\n while (*v5 != *v8) {\n if (++v8 == &a2[v7 + 1]) return 0LL;\n }\n ++v5;\n } while (v5 != &a1[v3 - 1 + 1]);\n }\n v9 = a2;\n if (v3 <= 0) return 0LL;\n do {\n v10 = a1;\n while (*v9 != *v10) {\n if (&a1[v3 - 1 + 1] == ++v10) return 0LL;\n }\n ++v9;\n } while (v9 != &v6[v7]);\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, const char *a2) {\n int v3;\n int v4;\n const char *v5;\n const char *v6;\n long long v7;\n const char *v8;\n const char *v9;\n const char *v10;\n long long result;\n v3 = strlen(a1);\n v4 = strlen(a2);\n if (v3 <= 0) {\n result = 1LL;\n if (v4 <= 0) return result;\n v6 = a2 + 1;\n v7 = (unsigned int)(v4 - 1);\n } else {\n v5 = a1;\n if (v4 <= 0) return 0LL;\n v6 = a2 + 1;\n v7 = (unsigned int)(v4 - 1);\n do {\n v8 = a2;\n while (*v5 != *v8) {\n if (++v8 == &a2[v7 + 1]) return 0LL;\n }\n ++v5;\n } while (v5 != &a1[v3 - 1 + 1]);\n }\n v9 = a2;\n if (v3 <= 0) return 0LL;\n do {\n v10 = a1;\n while (*v9 != *v10) {\n if (&a1[v3 - 1 + 1] == ++v10) return 0LL;\n }\n ++v9;\n } while (v9 != &v6[v7]);\n return 1LL;\n}" + }, + { + "index": "HumanEval-C-55", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int n) {\n int f[1000] = {0};\n f[0] = 0;\n f[1] = 1;\n for (int i = 2; i <= n; i++) f[i] = f[i - 1] + f[i - 2];\n return f[n];\n}", + "test": "#include \n\nint main() {\n assert(func0(10) == 55);\n assert(func0(1) == 1);\n assert(func0(8) == 21);\n assert(func0(11) == 89);\n assert(func0(12) == 144);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0FD0h\nmov [rbp+var_FC4], edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rdx, [rbp+var_FB0]\nmov eax, 0\nmov ecx, 1F4h\nmov rdi, rdx\nrep stosq\nmov [rbp+var_FB0], 0\nmov [rbp+var_FAC], 1\nmov [rbp+var_FB4], 2\njmp short loc_1200\nloc_11C4:\nmov eax, [rbp+var_FB4]\nsub eax, 1\ncdqe\nmov edx, [rbp+rax*4+var_FB0]\nmov eax, [rbp+var_FB4]\nsub eax, 2\ncdqe\nmov eax, [rbp+rax*4+var_FB0]\nadd edx, eax\nmov eax, [rbp+var_FB4]\ncdqe\nmov [rbp+rax*4+var_FB0], edx\nadd [rbp+var_FB4], 1\nloc_1200:\nmov eax, [rbp+var_FB4]\ncmp eax, [rbp+var_FC4]\njle short loc_11C4\nmov eax, [rbp+var_FC4]\ncdqe\nmov eax, [rbp+rax*4+var_FB0]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1231\ncall ___stack_chk_fail\nlocret_1231:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int i; // [rsp+1Ch] [rbp-FB4h]\n _DWORD v3[1002]; // [rsp+20h] [rbp-FB0h] BYREF\n unsigned __int64 v4; // [rsp+FC8h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n memset(v3, 0, 0xFA0uLL);\n v3[0] = 0;\n v3[1] = 1;\n for ( i = 2; i <= a1; ++i )\n v3[i] = v3[i - 2] + v3[i - 1];\n return (unsigned int)v3[a1];\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0FD0h\nmov [rbp+var_FC4], edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rdx, [rbp+var_FB0]\nmov eax, 0\nmov ecx, 1F4h\nmov rdi, rdx\nrep stosq\nmov [rbp+var_FB0], 0\nmov [rbp+var_FAC], 1\nmov [rbp+var_FB4], 2\njmp short loc_1200\nloc_11C4:\nmov eax, [rbp+var_FB4]\nsub eax, 1\ncdqe\nmov edx, [rbp+rax*4+var_FB0]\nmov eax, [rbp+var_FB4]\nsub eax, 2\ncdqe\nmov eax, [rbp+rax*4+var_FB0]\nadd edx, eax\nmov eax, [rbp+var_FB4]\ncdqe\nmov [rbp+rax*4+var_FB0], edx\nadd [rbp+var_FB4], 1\nloc_1200:\nmov eax, [rbp+var_FB4]\ncmp eax, [rbp+var_FC4]\njle short loc_11C4\nmov eax, [rbp+var_FC4]\ncdqe\nmov eax, [rbp+rax*4+var_FB0]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1231\ncall ___stack_chk_fail\nlocret_1231:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n int i; // [rsp+1Ch] [rbp-FB4h]\n _DWORD v3[1002]; // [rsp+20h] [rbp-FB0h] BYREF\n unsigned __int64 v4; // [rsp+FC8h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n memset(v3, 0, 0xFA0uLL);\n v3[0] = 0;\n v3[1] = 1;\n for ( i = 2; i <= a1; ++i )\n v3[i] = v3[i - 2] + v3[i - 1];\n return (unsigned int)v3[a1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n int i;\n uint32_t v3[1002];\n unsigned long long v4;\n v4 = __readfsqword(40u);\n memset(v3, 0, 4000uLL);\n v3[0] = 0;\n v3[1] = 1;\n for (i = 2; i <= a1; ++i) v3[i] = v3[i - 2] + v3[i - 1];\n return (unsigned int)v3[a1];\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int i;\n uint32_t v3[1002];\n unsigned long long v4;\n v4 = __readfsqword(40u);\n memset(v3, 0, 4000uLL);\n v3[0] = 0;\n v3[1] = 1;\n for (i = 2; i <= a1; ++i) v3[i] = v3[i - 2] + v3[i - 1];\n return (unsigned int)v3[a1];\n}" + }, + { + "index": "HumanEval-C-55", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int n) {\n int f[1000] = {0};\n f[0] = 0;\n f[1] = 1;\n for (int i = 2; i <= n; i++) f[i] = f[i - 1] + f[i - 2];\n return f[n];\n}", + "test": "#include \n\nint main() {\n assert(func0(10) == 55);\n assert(func0(1) == 1);\n assert(func0(8) == 21);\n assert(func0(11) == 89);\n assert(func0(12) == 144);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nsub rsp, 0FB8h\nmov esi, edi\nmov rax, fs:28h\nmov [rsp+0FB8h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nmov ecx, 1F4h\nrep stosq\nmov [rsp+0FB8h+var_FB4], 1\ncmp esi, 1\njle short loc_11BD\nmov rax, rsp\nlea edx, [rsi-2]\nlea rcx, [rsp+rdx*4+0FB8h+var_FB4]\nloc_11AC:\nmov edx, [rax]\nadd edx, [rax+4]\nmov [rax+8], edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_11AC\nloc_11BD:\nmovsxd rsi, esi\nmov eax, [rsp+rsi*4+0FB8h+var_FB8]\nmov rdx, [rsp+0FB8h+var_10]\nsub rdx, fs:28h\njnz short loc_11DE\nadd rsp, 0FB8h\nretn\nloc_11DE:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n _DWORD *v1; // rax\n _DWORD v3[1002]; // [rsp+0h] [rbp-FB8h] BYREF\n unsigned __int64 v4; // [rsp+FA8h] [rbp-10h]\n\n v4 = __readfsqword(0x28u);\n memset(v3, 0, 0xFA0uLL);\n v3[1] = 1;\n if ( a1 > 1 )\n {\n v1 = v3;\n do\n {\n v1[2] = v1[1] + *v1;\n ++v1;\n }\n while ( v1 != &v3[a1 - 2 + 1] );\n }\n return (unsigned int)v3[a1];\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nsub rsp, 0FB8h\nmov esi, edi\nmov rax, fs:28h\nmov [rsp+0FB8h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nmov ecx, 1F4h\nrep stosq\nmov [rsp+0FB8h+var_FB4], 1\ncmp esi, 1\njle short loc_11BD\nmov rax, rsp\nlea edx, [rsi-2]\nlea rcx, [rsp+rdx*4+0FB8h+var_FB4]\nloc_11AC:\nmov edx, [rax]\nadd edx, [rax+4]\nmov [rax+8], edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_11AC\nloc_11BD:\nmovsxd rsi, esi\nmov eax, [rsp+rsi*4+0FB8h+var_FB8]\nmov rdx, [rsp+0FB8h+var_10]\nsub rdx, fs:28h\njnz short loc_11DE\nadd rsp, 0FB8h\nretn\nloc_11DE:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n _DWORD *v1; // rax\n _DWORD v3[1002]; // [rsp+0h] [rbp-FB8h] BYREF\n unsigned __int64 v4; // [rsp+FA8h] [rbp-10h]\n\n v4 = __readfsqword(0x28u);\n memset(v3, 0, 0xFA0uLL);\n v3[1] = 1;\n if ( a1 > 1 )\n {\n v1 = v3;\n do\n {\n v1[2] = v1[1] + *v1;\n ++v1;\n }\n while ( v1 != &v3[a1 - 2 + 1] );\n }\n return (unsigned int)v3[a1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n uint32_t *v1;\n uint32_t v3[1002];\n unsigned long long v4;\n v4 = __readfsqword(40u);\n memset(v3, 0, 4000uLL);\n v3[1] = 1;\n if (a1 > 1) {\n v1 = v3;\n do {\n v1[2] = v1[1] + *v1;\n ++v1;\n } while (v1 != &v3[a1 - 2 + 1]);\n }\n return (unsigned int)v3[a1];\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n uint32_t *v1;\n uint32_t v3[1002];\n unsigned long long v4;\n v4 = __readfsqword(40u);\n memset(v3, 0, 4000uLL);\n v3[1] = 1;\n if (a1 > 1) {\n v1 = v3;\n do {\n v1[2] = v1[1] + *v1;\n ++v1;\n } while (v1 != &v3[a1 - 2 + 1]);\n }\n return (unsigned int)v3[a1];\n}" + }, + { + "index": "HumanEval-C-55", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int n) {\n int f[1000] = {0};\n f[0] = 0;\n f[1] = 1;\n for (int i = 2; i <= n; i++) f[i] = f[i - 1] + f[i - 2];\n return f[n];\n}", + "test": "#include \n\nint main() {\n assert(func0(10) == 55);\n assert(func0(1) == 1);\n assert(func0(8) == 21);\n assert(func0(11) == 89);\n assert(func0(12) == 144);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nsub rsp, 0FB8h\nmovsxd r8, edi\nmov ecx, 1F4h\nmov rax, fs:28h\nmov [rsp+0FB8h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\nmov [rsp+0FB8h+var_FB4], 1\ncmp r8d, 1\njle short loc_12D2\nlea eax, [r8-2]\nlea rdx, [rsp+0FB8h+var_FB0]\nlea rdi, [rsp+rax*4+0FB8h+var_FAC]\nmov eax, 1\nnop dword ptr [rax]\nloc_12C0:\nmov esi, eax\nadd eax, ecx\nadd rdx, 4\nmov [rdx-4], eax\nmov ecx, esi\ncmp rdx, rdi\njnz short loc_12C0\nloc_12D2:\nmov eax, [rsp+r8*4+0FB8h+var_FB8]\nmov rdx, [rsp+0FB8h+var_10]\nsub rdx, fs:28h\njnz short loc_12F1\nadd rsp, 0FB8h\nretn\nloc_12F1:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // ecx\n _DWORD *v2; // rdx\n int v3; // eax\n int v4; // esi\n _DWORD v6[1002]; // [rsp+0h] [rbp-FB8h] BYREF\n unsigned __int64 v7; // [rsp+FA8h] [rbp-10h]\n\n v7 = __readfsqword(0x28u);\n memset(v6, 0, 0xFA0uLL);\n v1 = 0;\n v6[1] = 1;\n if ( a1 > 1 )\n {\n v2 = &v6[2];\n v3 = 1;\n do\n {\n v4 = v3;\n v3 += v1;\n *v2++ = v3;\n v1 = v4;\n }\n while ( v2 != &v6[a1 - 2 + 3] );\n }\n return (unsigned int)v6[a1];\n}", + "ida_strip_asm": "sub_1270:\nendbr64\nsub rsp, 0FB8h\nmovsxd r8, edi\nmov ecx, 1F4h\nmov rax, fs:28h\nmov [rsp+0FB8h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\nmov [rsp+0FB8h+var_FB4], 1\ncmp r8d, 1\njle short loc_12D2\nlea eax, [r8-2]\nlea rdx, [rsp+0FB8h+var_FB0]\nlea rdi, [rsp+rax*4+0FB8h+var_FAC]\nmov eax, 1\nnop dword ptr [rax]\nloc_12C0:\nmov esi, eax\nadd eax, ecx\nadd rdx, 4\nmov [rdx-4], eax\nmov ecx, esi\ncmp rdx, rdi\njnz short loc_12C0\nloc_12D2:\nmov eax, [rsp+r8*4+0FB8h+var_FB8]\nmov rdx, [rsp+0FB8h+var_10]\nsub rdx, fs:28h\njnz short loc_12F1\nadd rsp, 0FB8h\nretn\nloc_12F1:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1270(int a1)\n{\n int v1; // ecx\n _DWORD *v2; // rdx\n int v3; // eax\n int v4; // esi\n _DWORD v6[1002]; // [rsp+0h] [rbp-FB8h] BYREF\n unsigned __int64 v7; // [rsp+FA8h] [rbp-10h]\n\n v7 = __readfsqword(0x28u);\n memset(v6, 0, 0xFA0uLL);\n v1 = 0;\n v6[1] = 1;\n if ( a1 > 1 )\n {\n v2 = &v6[2];\n v3 = 1;\n do\n {\n v4 = v3;\n v3 += v1;\n *v2++ = v3;\n v1 = v4;\n }\n while ( v2 != &v6[a1 - 2 + 3] );\n }\n return (unsigned int)v6[a1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1270(int a1) {\n int v1;\n uint32_t *v2;\n int v3;\n int v4;\n uint32_t v6[1002];\n unsigned long long v7;\n v7 = __readfsqword(40u);\n memset(v6, 0, 4000uLL);\n v1 = 0;\n v6[1] = 1;\n if (a1 > 1) {\n v2 = &v6[2];\n v3 = 1;\n do {\n v4 = v3;\n v3 += v1;\n *v2++ = v3;\n v1 = v4;\n } while (v2 != &v6[a1 - 2 + 3]);\n }\n return (unsigned int)v6[a1];\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n uint32_t *v2;\n int v3;\n int v4;\n uint32_t v6[1002];\n unsigned long long v7;\n v7 = __readfsqword(40u);\n memset(v6, 0, 4000uLL);\n v1 = 0;\n v6[1] = 1;\n if (a1 > 1) {\n v2 = &v6[2];\n v3 = 1;\n do {\n v4 = v3;\n v3 += v1;\n *v2++ = v3;\n v1 = v4;\n } while (v2 != &v6[a1 - 2 + 3]);\n }\n return (unsigned int)v6[a1];\n}" + }, + { + "index": "HumanEval-C-55", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int n) {\n int f[1000] = {0};\n f[0] = 0;\n f[1] = 1;\n for (int i = 2; i <= n; i++) f[i] = f[i - 1] + f[i - 2];\n return f[n];\n}", + "test": "#include \n\nint main() {\n assert(func0(10) == 55);\n assert(func0(1) == 1);\n assert(func0(8) == 21);\n assert(func0(11) == 89);\n assert(func0(12) == 144);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nsub rsp, 0FB8h\nmovsxd rsi, edi\nmov ecx, 1F4h\nmov rax, fs:28h\nmov [rsp+0FB8h+var_10], rax\nxor eax, eax\nmov r8, rsp\nmov rdi, r8\nrep stosq\nmov [rsp+0FB8h+var_FB4], 1\ncmp esi, 1\njle short loc_1304\ncmp esi, 3\njle short loc_1322\nlea ecx, [rsi-4]\nlea rdi, [rsp+0FB8h+var_FB0]\nmov edx, 1\nmov r9d, 2\nand ecx, 0FFFFFFFEh\nadd ecx, 4\nloc_12CA:\nadd eax, edx\nadd r9d, 2\nadd rdi, 8\nadd edx, eax\nmov [rdi-8], eax\nmov [rdi-4], edx\ncmp r9d, ecx\njnz short loc_12CA\nloc_12E1:\nmovsxd rax, ecx\nlea rax, [r8+rax*4]\nnop dword ptr [rax+rax+00000000h]\nloc_12F0:\nmov edx, [rax-8]\nadd ecx, 1\nadd edx, [rax-4]\nadd rax, 4\nmov [rax-4], edx\ncmp esi, ecx\njge short loc_12F0\nloc_1304:\nmov eax, [rsp+rsi*4+0FB8h+var_FB8]\nmov rdx, [rsp+0FB8h+var_10]\nsub rdx, fs:28h\njnz short loc_1329\nadd rsp, 0FB8h\nretn\nloc_1322:\nmov ecx, 2\njmp short loc_12E1\nloc_1329:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n __int64 v1; // rsi\n int v2; // eax\n _DWORD *v3; // rdi\n int v4; // edx\n int v5; // r9d\n int v6; // ecx\n _DWORD *v7; // rax\n int v8; // edx\n _DWORD v10[1002]; // [rsp+0h] [rbp-FB8h] BYREF\n unsigned __int64 v11; // [rsp+FA8h] [rbp-10h]\n\n v1 = a1;\n v11 = __readfsqword(0x28u);\n v2 = 0;\n memset(v10, 0, 0xFA0uLL);\n v10[1] = 1;\n if ( a1 > 1 )\n {\n if ( a1 <= 3 )\n {\n v6 = 2;\n }\n else\n {\n v3 = &v10[2];\n v4 = 1;\n v5 = 2;\n v6 = ((v1 - 4) & 0xFFFFFFFE) + 4;\n do\n {\n v2 += v4;\n v5 += 2;\n v3 += 2;\n v4 += v2;\n *(v3 - 2) = v2;\n *(v3 - 1) = v4;\n }\n while ( v5 != v6 );\n }\n v7 = &v10[v6];\n do\n {\n ++v6;\n v8 = *(v7 - 1) + *(v7 - 2);\n *v7++ = v8;\n }\n while ( (int)v1 >= v6 );\n }\n return (unsigned int)v10[v1];\n}", + "ida_strip_asm": "sub_1270:\nendbr64\nsub rsp, 0FB8h\nmovsxd rsi, edi\nmov ecx, 1F4h\nmov rax, fs:28h\nmov [rsp+0FB8h+var_10], rax\nxor eax, eax\nmov r8, rsp\nmov rdi, r8\nrep stosq\nmov [rsp+0FB8h+var_FB4], 1\ncmp esi, 1\njle short loc_1304\ncmp esi, 3\njle short loc_1322\nlea ecx, [rsi-4]\nlea rdi, [rsp+0FB8h+var_FB0]\nmov edx, 1\nmov r9d, 2\nand ecx, 0FFFFFFFEh\nadd ecx, 4\nloc_12CA:\nadd eax, edx\nadd r9d, 2\nadd rdi, 8\nadd edx, eax\nmov [rdi-8], eax\nmov [rdi-4], edx\ncmp r9d, ecx\njnz short loc_12CA\nloc_12E1:\nmovsxd rax, ecx\nlea rax, [r8+rax*4]\nnop dword ptr [rax+rax+00000000h]\nloc_12F0:\nmov edx, [rax-8]\nadd ecx, 1\nadd edx, [rax-4]\nadd rax, 4\nmov [rax-4], edx\ncmp esi, ecx\njge short loc_12F0\nloc_1304:\nmov eax, [rsp+rsi*4+0FB8h+var_FB8]\nmov rdx, [rsp+0FB8h+var_10]\nsub rdx, fs:28h\njnz short loc_1329\nadd rsp, 0FB8h\nretn\nloc_1322:\nmov ecx, 2\njmp short loc_12E1\nloc_1329:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1270(int a1)\n{\n __int64 v1; // rsi\n int v2; // eax\n _DWORD *v3; // rdi\n int v4; // edx\n int v5; // r9d\n int v6; // ecx\n _DWORD *v7; // rax\n int v8; // edx\n _DWORD v10[1002]; // [rsp+0h] [rbp-FB8h] BYREF\n unsigned __int64 v11; // [rsp+FA8h] [rbp-10h]\n\n v1 = a1;\n v11 = __readfsqword(0x28u);\n v2 = 0;\n memset(v10, 0, 0xFA0uLL);\n v10[1] = 1;\n if ( a1 > 1 )\n {\n if ( a1 <= 3 )\n {\n v6 = 2;\n }\n else\n {\n v3 = &v10[2];\n v4 = 1;\n v5 = 2;\n v6 = ((v1 - 4) & 0xFFFFFFFE) + 4;\n do\n {\n v2 += v4;\n v5 += 2;\n v3 += 2;\n v4 += v2;\n *(v3 - 2) = v2;\n *(v3 - 1) = v4;\n }\n while ( v5 != v6 );\n }\n v7 = &v10[v6];\n do\n {\n ++v6;\n v8 = *(v7 - 1) + *(v7 - 2);\n *v7++ = v8;\n }\n while ( (int)v1 >= v6 );\n }\n return (unsigned int)v10[v1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1270(int a1) {\n long long v1;\n int v2;\n uint32_t *v3;\n int v4;\n int v5;\n int v6;\n uint32_t *v7;\n int v8;\n uint32_t v10[1002];\n unsigned long long v11;\n v1 = a1;\n v11 = __readfsqword(40u);\n v2 = 0;\n memset(v10, 0, 4000uLL);\n v10[1] = 1;\n if (a1 > 1) {\n if (a1 <= 3) {\n v6 = 2;\n } else {\n v3 = &v10[2];\n v4 = 1;\n v5 = 2;\n v6 = ((v1 - 4) & 4294967294) + 4;\n do {\n v2 += v4;\n v5 += 2;\n v3 += 2;\n v4 += v2;\n *(v3 - 2) = v2;\n *(v3 - 1) = v4;\n } while (v5 != v6);\n }\n v7 = &v10[v6];\n do {\n ++v6;\n v8 = *(v7 - 1) + *(v7 - 2);\n *v7++ = v8;\n } while ((int)v1 >= v6);\n }\n return (unsigned int)v10[v1];\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n long long v1;\n int v2;\n uint32_t *v3;\n int v4;\n int v5;\n int v6;\n uint32_t *v7;\n int v8;\n uint32_t v10[1002];\n unsigned long long v11;\n v1 = a1;\n v11 = __readfsqword(40u);\n v2 = 0;\n memset(v10, 0, 4000uLL);\n v10[1] = 1;\n if (a1 > 1) {\n if (a1 <= 3) {\n v6 = 2;\n } else {\n v3 = &v10[2];\n v4 = 1;\n v5 = 2;\n v6 = ((v1 - 4) & 4294967294) + 4;\n do {\n v2 += v4;\n v5 += 2;\n v3 += 2;\n v4 += v2;\n *(v3 - 2) = v2;\n *(v3 - 1) = v4;\n } while (v5 != v6);\n }\n v7 = &v10[v6];\n do {\n ++v6;\n v8 = *(v7 - 1) + *(v7 - 2);\n *v7++ = v8;\n } while ((int)v1 >= v6);\n }\n return (unsigned int)v10[v1];\n}" + }, + { + "index": "HumanEval-C-56", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "bool func0(const char *brackets) {\n int level = 0;\n int i = 0;\n while (brackets[i]) {\n if (brackets[i] == '<') level++;\n if (brackets[i] == '>') level--;\n if (level < 0) return false;\n i++;\n }\n if (level != 0) return false;\n return true;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"<>\"));\n assert(func0(\"<<><>>\"));\n assert(func0(\"<><><<><>><>\"));\n assert(func0(\"<><><<<><><>><>><<><><<>>>\"));\n assert(!func0(\"<<<><>>>>\"));\n assert(!func0(\"><<>\"));\n assert(!func0(\"<\"));\n assert(!func0(\"<<<<\"));\n assert(!func0(\">\"));\n assert(!func0(\"<<>\"));\n assert(!func0(\"<><><<><>><>><<>\"));\n assert(!func0(\"<><><<><>><>>><>\"));\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11A6\nloc_1165:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 3Ch ; '<'\njnz short loc_117D\nadd [rbp+var_8], 1\nloc_117D:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 3Eh ; '>'\njnz short loc_1195\nsub [rbp+var_8], 1\nloc_1195:\ncmp [rbp+var_8], 0\njns short loc_11A2\nmov eax, 0\njmp short loc_11CC\nloc_11A2:\nadd [rbp+var_4], 1\nloc_11A6:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1165\ncmp [rbp+var_8], 0\njz short loc_11C7\nmov eax, 0\njmp short loc_11CC\nloc_11C7:\nmov eax, 1\nloc_11CC:\npop rbp\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(__int64 a1)\n{\n int v2; // [rsp+10h] [rbp-8h]\n int i; // [rsp+14h] [rbp-4h]\n\n v2 = 0;\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n {\n if ( *(_BYTE *)(i + a1) == 60 )\n ++v2;\n if ( *(_BYTE *)(i + a1) == 62 )\n --v2;\n if ( v2 < 0 )\n return 0LL;\n }\n return v2 == 0;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11A6\nloc_1165:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 3Ch ; '<'\njnz short loc_117D\nadd [rbp+var_8], 1\nloc_117D:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 3Eh ; '>'\njnz short loc_1195\nsub [rbp+var_8], 1\nloc_1195:\ncmp [rbp+var_8], 0\njns short loc_11A2\nmov eax, 0\njmp short loc_11CC\nloc_11A2:\nadd [rbp+var_4], 1\nloc_11A6:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1165\ncmp [rbp+var_8], 0\njz short loc_11C7\nmov eax, 0\njmp short loc_11CC\nloc_11C7:\nmov eax, 1\nloc_11CC:\npop rbp\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1149(__int64 a1)\n{\n int v2; // [rsp+10h] [rbp-8h]\n int i; // [rsp+14h] [rbp-4h]\n\n v2 = 0;\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n {\n if ( *(_BYTE *)(i + a1) == 60 )\n ++v2;\n if ( *(_BYTE *)(i + a1) == 62 )\n --v2;\n if ( v2 < 0 )\n return 0LL;\n }\n return v2 == 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1149(long long a1) {\n int v2;\n int i;\n v2 = 0;\n for (i = 0; *(uint8_t *)(i + a1); ++i) {\n if (*(uint8_t *)(i + a1) == 60) ++v2;\n if (*(uint8_t *)(i + a1) == 62) --v2;\n if (v2 < 0) return 0LL;\n }\n return v2 == 0;\n}", + "ida_pseudo_norm": "uint8_t func0(long long a1) {\n int v2;\n int i;\n v2 = 0;\n for (i = 0; *(uint8_t *)(i + a1); ++i) {\n if (*(uint8_t *)(i + a1) == 60) ++v2;\n if (*(uint8_t *)(i + a1) == 62) --v2;\n if (v2 < 0) return 0LL;\n }\n return v2 == 0;\n}" + }, + { + "index": "HumanEval-C-56", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "bool func0(const char *brackets) {\n int level = 0;\n int i = 0;\n while (brackets[i]) {\n if (brackets[i] == '<') level++;\n if (brackets[i] == '>') level--;\n if (level < 0) return false;\n i++;\n }\n if (level != 0) return false;\n return true;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"<>\"));\n assert(func0(\"<<><>>\"));\n assert(func0(\"<><><<><>><>\"));\n assert(func0(\"<><><<<><><>><>><<><><<>>>\"));\n assert(!func0(\"<<<><>>>>\"));\n assert(!func0(\"><<>\"));\n assert(!func0(\"<\"));\n assert(!func0(\"<<<<\"));\n assert(!func0(\">\"));\n assert(!func0(\"<<>\"));\n assert(!func0(\"<><><<><>><>><<>\"));\n assert(!func0(\"<><><<><>><>>><>\"));\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmovzx eax, byte ptr [rdi]\ntest al, al\njz short loc_1181\nadd rdi, 1\nmov edx, 0\njmp short loc_116E\nloc_115F:\nadd edx, 1\nloc_1162:\nadd rdi, 1\nmovzx eax, byte ptr [rdi-1]\ntest al, al\njz short loc_1186\nloc_116E:\ncmp al, 3Ch ; '<'\njz short loc_115F\ncmp al, 3Eh ; '>'\njnz short loc_1162\nsub edx, 1\njns short loc_1162\nmov eax, 0\nretn\nloc_1181:\nmov edx, 0\nloc_1186:\ntest edx, edx\nsetz al\nretn", + "ida_pseudo": "bool __fastcall func0(char *a1)\n{\n char v1; // al\n char *v2; // rdi\n int v3; // edx\n\n v1 = *a1;\n if ( *a1 )\n {\n v2 = a1 + 1;\n v3 = 0;\n while ( 1 )\n {\n if ( v1 == 60 )\n {\n ++v3;\n }\n else if ( v1 == 62 && --v3 < 0 )\n {\n return 0;\n }\n v1 = *v2++;\n if ( !v1 )\n return v3 == 0;\n }\n }\n v3 = 0;\n return v3 == 0;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmovzx eax, byte ptr [rdi]\ntest al, al\njz short loc_1181\nadd rdi, 1\nmov edx, 0\njmp short loc_116E\nloc_115F:\nadd edx, 1\nloc_1162:\nadd rdi, 1\nmovzx eax, byte ptr [rdi-1]\ntest al, al\njz short loc_1186\nloc_116E:\ncmp al, 3Ch ; '<'\njz short loc_115F\ncmp al, 3Eh ; '>'\njnz short loc_1162\nsub edx, 1\njns short loc_1162\nmov eax, 0\nretn\nloc_1181:\nmov edx, 0\nloc_1186:\ntest edx, edx\nsetz al\nretn", + "ida_strip_pseudo": "bool __fastcall sub_1149(char *a1)\n{\n char v1; // al\n char *v2; // rdi\n int v3; // edx\n\n v1 = *a1;\n if ( *a1 )\n {\n v2 = a1 + 1;\n v3 = 0;\n while ( 1 )\n {\n if ( v1 == 60 )\n {\n ++v3;\n }\n else if ( v1 == 62 && --v3 < 0 )\n {\n return 0;\n }\n v1 = *v2++;\n if ( !v1 )\n return v3 == 0;\n }\n }\n v3 = 0;\n return v3 == 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_1149(char *a1) {\n char v1;\n char *v2;\n int v3;\n v1 = *a1;\n if (*a1) {\n v2 = a1 + 1;\n v3 = 0;\n while (1) {\n if (v1 == 60) {\n ++v3;\n } else if (v1 == 62 && --v3 < 0) {\n return 0;\n }\n v1 = *v2++;\n if (!v1) return v3 == 0;\n }\n }\n v3 = 0;\n return v3 == 0;\n}", + "ida_pseudo_norm": "bool func0(char *a1) {\n char v1;\n char *v2;\n int v3;\n v1 = *a1;\n if (*a1) {\n v2 = a1 + 1;\n v3 = 0;\n while (1) {\n if (v1 == 60) {\n ++v3;\n } else if (v1 == 62 && --v3 < 0) {\n return 0;\n }\n v1 = *v2++;\n if (!v1) return v3 == 0;\n }\n }\n v3 = 0;\n return v3 == 0;\n}" + }, + { + "index": "HumanEval-C-56", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "bool func0(const char *brackets) {\n int level = 0;\n int i = 0;\n while (brackets[i]) {\n if (brackets[i] == '<') level++;\n if (brackets[i] == '>') level--;\n if (level < 0) return false;\n i++;\n }\n if (level != 0) return false;\n return true;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"<>\"));\n assert(func0(\"<<><>>\"));\n assert(func0(\"<><><<><>><>\"));\n assert(func0(\"<><><<<><><>><>><<><><<>>>\"));\n assert(!func0(\"<<<><>>>>\"));\n assert(!func0(\"><<>\"));\n assert(!func0(\"<\"));\n assert(!func0(\"<<<<\"));\n assert(!func0(\">\"));\n assert(!func0(\"<<>\"));\n assert(!func0(\"<><><<><>><>><<>\"));\n assert(!func0(\"<><><<><>><>>><>\"));\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmovzx eax, byte ptr [rdi]\ntest al, al\njz short loc_140B\nadd rdi, 1\nxor edx, edx\njmp short loc_13EC\nloc_13D8:\ncmp al, 3Eh ; '>'\njnz short loc_13E1\nsub edx, 1\njb short loc_1408\nloc_13E1:\nmovzx eax, byte ptr [rdi]\nadd rdi, 1\ntest al, al\njz short loc_13FE\nloc_13EC:\ncmp al, 3Ch ; '<'\njnz short loc_13D8\nmovzx eax, byte ptr [rdi]\nadd rdi, 1\nadd edx, 1\ntest al, al\njnz short loc_13EC\nloc_13FE:\ntest edx, edx\nsetz al\nretn\nloc_1408:\nxor eax, eax\nretn\nloc_140B:\nmov eax, 1\nretn", + "ida_pseudo": "char __fastcall func0(char *a1)\n{\n char v1; // al\n char *v2; // rdi\n int v3; // edx\n\n v1 = *a1;\n if ( !*a1 )\n return 1;\n v2 = a1 + 1;\n v3 = 0;\n while ( 1 )\n {\n while ( v1 == 60 )\n {\n v1 = *v2++;\n ++v3;\n if ( !v1 )\n return v3 == 0;\n }\n if ( v1 == 62 && v3-- == 0 )\n break;\n v1 = *v2++;\n if ( !v1 )\n return v3 == 0;\n }\n return 0;\n}", + "ida_strip_asm": "sub_13C0:\nendbr64\nmovzx eax, byte ptr [rdi]\ntest al, al\njz short loc_140B\nadd rdi, 1\nxor edx, edx\njmp short loc_13EC\nloc_13D8:\ncmp al, 3Eh ; '>'\njnz short loc_13E1\nsub edx, 1\njb short loc_1408\nloc_13E1:\nmovzx eax, byte ptr [rdi]\nadd rdi, 1\ntest al, al\njz short loc_13FE\nloc_13EC:\ncmp al, 3Ch ; '<'\njnz short loc_13D8\nmovzx eax, byte ptr [rdi]\nadd rdi, 1\nadd edx, 1\ntest al, al\njnz short loc_13EC\nloc_13FE:\ntest edx, edx\nsetz al\nretn\nloc_1408:\nxor eax, eax\nretn\nloc_140B:\nmov eax, 1\nretn", + "ida_strip_pseudo": "char __fastcall sub_13C0(char *a1)\n{\n char v1; // al\n char *v2; // rdi\n int v3; // edx\n\n v1 = *a1;\n if ( !*a1 )\n return 1;\n v2 = a1 + 1;\n v3 = 0;\n while ( 1 )\n {\n while ( v1 == 60 )\n {\n v1 = *v2++;\n ++v3;\n if ( !v1 )\n return v3 == 0;\n }\n if ( v1 == 62 && v3-- == 0 )\n break;\n v1 = *v2++;\n if ( !v1 )\n return v3 == 0;\n }\n return 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char sub_13C0(char *a1) {\n char v1;\n char *v2;\n int v3;\n v1 = *a1;\n if (!*a1) return 1;\n v2 = a1 + 1;\n v3 = 0;\n while (1) {\n while (v1 == 60) {\n v1 = *v2++;\n ++v3;\n if (!v1) return v3 == 0;\n }\n if (v1 == 62 && v3-- == 0) break;\n v1 = *v2++;\n if (!v1) return v3 == 0;\n }\n return 0;\n}", + "ida_pseudo_norm": "char func0(char *a1) {\n char v1;\n char *v2;\n int v3;\n v1 = *a1;\n if (!*a1) return 1;\n v2 = a1 + 1;\n v3 = 0;\n while (1) {\n while (v1 == 60) {\n v1 = *v2++;\n ++v3;\n if (!v1) return v3 == 0;\n }\n if (v1 == 62 && v3-- == 0) break;\n v1 = *v2++;\n if (!v1) return v3 == 0;\n }\n return 0;\n}" + }, + { + "index": "HumanEval-C-57", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "bool func0(float *l, int size) {\n int incr, decr;\n incr = decr = 0;\n for (int i = 1; i < size; i++) {\n if (l[i] > l[i - 1]) incr = 1;\n if (l[i] < l[i - 1]) decr = 1;\n }\n if (incr + decr == 2) return false;\n return true;\n}", + "test": "#include \n\nint main() {\n float list1[] = {1, 2, 4, 10};\n float list2[] = {1, 2, 4, 20};\n float list3[] = {1, 20, 4, 10};\n float list4[] = {4, 1, 0, -10};\n float list5[] = {4, 1, 1, 0};\n float list6[] = {1, 2, 3, 2, 5, 60};\n float list7[] = {1, 2, 3, 4, 5, 60};\n float list8[] = {9, 9, 9, 9};\n\n assert(func0(list1, 4) == true);\n assert(func0(list2, 4) == true);\n assert(func0(list3, 4) == false);\n assert(func0(list4, 4) == true);\n assert(func0(list5, 4) == true);\n assert(func0(list6, 6) == false);\n assert(func0(list7, 6) == true);\n assert(func0(list8, 4) == true);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov eax, [rbp+var_8]\nmov [rbp+var_C], eax\nmov [rbp+var_4], 1\njmp short loc_120A\nloc_118E:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\nmov eax, [rbp+var_4]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm1, dword ptr [rax]\ncomiss xmm0, xmm1\njbe short loc_11CA\nmov [rbp+var_C], 1\nloc_11CA:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm1, dword ptr [rax]\nmov eax, [rbp+var_4]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\ncomiss xmm0, xmm1\njbe short loc_1206\nmov [rbp+var_8], 1\nloc_1206:\nadd [rbp+var_4], 1\nloc_120A:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl loc_118E\nmov edx, [rbp+var_C]\nmov eax, [rbp+var_8]\nadd eax, edx\ncmp eax, 2\njnz short loc_122A\nmov eax, 0\njmp short loc_122F\nloc_122A:\nmov eax, 1\nloc_122F:\npop rbp\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(__int64 a1, int a2)\n{\n int v3; // [rsp+10h] [rbp-Ch]\n int v4; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v4 = 0;\n v3 = 0;\n for ( i = 1; i < a2; ++i )\n {\n if ( *(float *)(4LL * i + a1) > *(float *)(4LL * i - 4 + a1) )\n v3 = 1;\n if ( *(float *)(4LL * i - 4 + a1) > *(float *)(4LL * i + a1) )\n v4 = 1;\n }\n return v3 + v4 != 2;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov eax, [rbp+var_8]\nmov [rbp+var_C], eax\nmov [rbp+var_4], 1\njmp short loc_120A\nloc_118E:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\nmov eax, [rbp+var_4]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm1, dword ptr [rax]\ncomiss xmm0, xmm1\njbe short loc_11CA\nmov [rbp+var_C], 1\nloc_11CA:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm1, dword ptr [rax]\nmov eax, [rbp+var_4]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\ncomiss xmm0, xmm1\njbe short loc_1206\nmov [rbp+var_8], 1\nloc_1206:\nadd [rbp+var_4], 1\nloc_120A:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl loc_118E\nmov edx, [rbp+var_C]\nmov eax, [rbp+var_8]\nadd eax, edx\ncmp eax, 2\njnz short loc_122A\nmov eax, 0\njmp short loc_122F\nloc_122A:\nmov eax, 1\nloc_122F:\npop rbp\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1169(__int64 a1, int a2)\n{\n int v3; // [rsp+10h] [rbp-Ch]\n int v4; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v4 = 0;\n v3 = 0;\n for ( i = 1; i < a2; ++i )\n {\n if ( *(float *)(4LL * i + a1) > *(float *)(4LL * i - 4 + a1) )\n v3 = 1;\n if ( *(float *)(4LL * i - 4 + a1) > *(float *)(4LL * i + a1) )\n v4 = 1;\n }\n return v3 + v4 != 2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1169(long long a1, int a2) {\n int v3;\n int v4;\n int i;\n v4 = 0;\n v3 = 0;\n for (i = 1; i < a2; ++i) {\n if (*(float *)(4LL * i + a1) > *(float *)(4LL * i - 4 + a1)) v3 = 1;\n if (*(float *)(4LL * i - 4 + a1) > *(float *)(4LL * i + a1)) v4 = 1;\n }\n return v3 + v4 != 2;\n}", + "ida_pseudo_norm": "uint8_t func0(long long a1, int a2) {\n int v3;\n int v4;\n int i;\n v4 = 0;\n v3 = 0;\n for (i = 1; i < a2; ++i) {\n if (*(float *)(4LL * i + a1) > *(float *)(4LL * i - 4 + a1)) v3 = 1;\n if (*(float *)(4LL * i - 4 + a1) > *(float *)(4LL * i + a1)) v4 = 1;\n }\n return v3 + v4 != 2;\n}" + }, + { + "index": "HumanEval-C-57", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "bool func0(float *l, int size) {\n int incr, decr;\n incr = decr = 0;\n for (int i = 1; i < size; i++) {\n if (l[i] > l[i - 1]) incr = 1;\n if (l[i] < l[i - 1]) decr = 1;\n }\n if (incr + decr == 2) return false;\n return true;\n}", + "test": "#include \n\nint main() {\n float list1[] = {1, 2, 4, 10};\n float list2[] = {1, 2, 4, 20};\n float list3[] = {1, 20, 4, 10};\n float list4[] = {4, 1, 0, -10};\n float list5[] = {4, 1, 1, 0};\n float list6[] = {1, 2, 3, 2, 5, 60};\n float list7[] = {1, 2, 3, 4, 5, 60};\n float list8[] = {9, 9, 9, 9};\n\n assert(func0(list1, 4) == true);\n assert(func0(list2, 4) == true);\n assert(func0(list3, 4) == false);\n assert(func0(list4, 4) == true);\n assert(func0(list5, 4) == true);\n assert(func0(list6, 6) == false);\n assert(func0(list7, 6) == true);\n assert(func0(list8, 4) == true);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ncmp esi, 1\njle short loc_11AF\nmov rax, rdi\nlea edx, [rsi-2]\nlea rsi, [rdi+rdx*4+4]\nmov edx, 0\nmov edi, 0\nmov ecx, 1\njmp short loc_1199\nloc_118E:\nmov edi, ecx\nloc_1190:\nadd rax, 4\ncmp rax, rsi\njz short loc_11B9\nloc_1199:\nmovss xmm0, dword ptr [rax+4]\nmovss xmm1, dword ptr [rax]\ncomiss xmm0, xmm1\nja short loc_118E\nucomiss xmm1, xmm0\ncmova edx, ecx\njmp short loc_1190\nloc_11AF:\nmov edx, 0\nmov edi, 0\nloc_11B9:\nadd edi, edx\ncmp edi, 2\nsetnz al\nretn", + "ida_pseudo": "bool __fastcall func0(float *a1, int a2)\n{\n float *v2; // rax\n __int64 v3; // rsi\n int v4; // edx\n int v5; // edi\n float v6; // xmm0_4\n\n if ( a2 <= 1 )\n {\n v4 = 0;\n v5 = 0;\n }\n else\n {\n v2 = a1;\n v3 = (__int64)&a1[a2 - 2 + 1];\n v4 = 0;\n v5 = 0;\n do\n {\n v6 = v2[1];\n if ( v6 > *v2 )\n {\n v5 = 1;\n }\n else if ( *v2 > v6 )\n {\n v4 = 1;\n }\n ++v2;\n }\n while ( v2 != (float *)v3 );\n }\n return v4 + v5 != 2;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ncmp esi, 1\njle short loc_11AF\nmov rax, rdi\nlea edx, [rsi-2]\nlea rsi, [rdi+rdx*4+4]\nmov edx, 0\nmov edi, 0\nmov ecx, 1\njmp short loc_1199\nloc_118E:\nmov edi, ecx\nloc_1190:\nadd rax, 4\ncmp rax, rsi\njz short loc_11B9\nloc_1199:\nmovss xmm0, dword ptr [rax+4]\nmovss xmm1, dword ptr [rax]\ncomiss xmm0, xmm1\nja short loc_118E\nucomiss xmm1, xmm0\ncmova edx, ecx\njmp short loc_1190\nloc_11AF:\nmov edx, 0\nmov edi, 0\nloc_11B9:\nadd edi, edx\ncmp edi, 2\nsetnz al\nretn", + "ida_strip_pseudo": "bool __fastcall sub_1169(float *a1, int a2)\n{\n float *v2; // rax\n __int64 v3; // rsi\n int v4; // edx\n int v5; // edi\n float v6; // xmm0_4\n\n if ( a2 <= 1 )\n {\n v4 = 0;\n v5 = 0;\n }\n else\n {\n v2 = a1;\n v3 = (__int64)&a1[a2 - 2 + 1];\n v4 = 0;\n v5 = 0;\n do\n {\n v6 = v2[1];\n if ( v6 > *v2 )\n {\n v5 = 1;\n }\n else if ( *v2 > v6 )\n {\n v4 = 1;\n }\n ++v2;\n }\n while ( v2 != (float *)v3 );\n }\n return v4 + v5 != 2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_1169(float *a1, int a2) {\n float *v2;\n long long v3;\n int v4;\n int v5;\n float v6;\n if (a2 <= 1) {\n v4 = 0;\n v5 = 0;\n } else {\n v2 = a1;\n v3 = (long long)&a1[a2 - 2 + 1];\n v4 = 0;\n v5 = 0;\n do {\n v6 = v2[1];\n if (v6 > *v2) {\n v5 = 1;\n } else if (*v2 > v6) {\n v4 = 1;\n }\n ++v2;\n } while (v2 != (float *)v3);\n }\n return v4 + v5 != 2;\n}", + "ida_pseudo_norm": "bool func0(float *a1, int a2) {\n float *v2;\n long long v3;\n int v4;\n int v5;\n float v6;\n if (a2 <= 1) {\n v4 = 0;\n v5 = 0;\n } else {\n v2 = a1;\n v3 = (long long)&a1[a2 - 2 + 1];\n v4 = 0;\n v5 = 0;\n do {\n v6 = v2[1];\n if (v6 > *v2) {\n v5 = 1;\n } else if (*v2 > v6) {\n v4 = 1;\n }\n ++v2;\n } while (v2 != (float *)v3);\n }\n return v4 + v5 != 2;\n}" + }, + { + "index": "HumanEval-C-57", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "bool func0(float *l, int size) {\n int incr, decr;\n incr = decr = 0;\n for (int i = 1; i < size; i++) {\n if (l[i] > l[i - 1]) incr = 1;\n if (l[i] < l[i - 1]) decr = 1;\n }\n if (incr + decr == 2) return false;\n return true;\n}", + "test": "#include \n\nint main() {\n float list1[] = {1, 2, 4, 10};\n float list2[] = {1, 2, 4, 20};\n float list3[] = {1, 20, 4, 10};\n float list4[] = {4, 1, 0, -10};\n float list5[] = {4, 1, 1, 0};\n float list6[] = {1, 2, 3, 2, 5, 60};\n float list7[] = {1, 2, 3, 4, 5, 60};\n float list8[] = {9, 9, 9, 9};\n\n assert(func0(list1, 4) == true);\n assert(func0(list2, 4) == true);\n assert(func0(list3, 4) == false);\n assert(func0(list4, 4) == true);\n assert(func0(list5, 4) == true);\n assert(func0(list6, 6) == false);\n assert(func0(list7, 6) == true);\n assert(func0(list8, 4) == true);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ncmp esi, 1\njle short loc_1440\nlea edx, [rsi-2]\nmovss xmm0, dword ptr [rdi]\nlea rax, [rdi+4]\nxor esi, esi\nlea rcx, [rdi+rdx*4+8]\nxor edx, edx\nmov edi, 1\njmp short loc_1417\nloc_1408:\nucomiss xmm1, xmm0\ncmova edx, edi\nadd rax, 4\ncmp rax, rcx\njz short loc_1431\nloc_1417:\nmovaps xmm1, xmm0\nmovss xmm0, dword ptr [rax]\ncomiss xmm0, xmm1\njbe short loc_1408\nadd rax, 4\nmov esi, 1\ncmp rax, rcx\njnz short loc_1417\nloc_1431:\nadd edx, esi\ncmp edx, 2\nsetnz al\nretn\nloc_1440:\nmov eax, 1\nretn", + "ida_pseudo": "char __fastcall func0(float *a1, int a2)\n{\n __int64 v2; // rdx\n float v3; // xmm0_4\n float *v4; // rax\n int v5; // esi\n __int64 v6; // rcx\n int v7; // edx\n float v8; // xmm1_4\n\n if ( a2 <= 1 )\n return 1;\n v2 = (unsigned int)(a2 - 2);\n v3 = *a1;\n v4 = a1 + 1;\n v5 = 0;\n v6 = (__int64)&a1[v2 + 2];\n v7 = 0;\n do\n {\n while ( 1 )\n {\n v8 = v3;\n v3 = *v4;\n if ( *v4 <= v8 )\n break;\n ++v4;\n v5 = 1;\n if ( v4 == (float *)v6 )\n return v5 + v7 != 2;\n }\n if ( v8 > v3 )\n v7 = 1;\n ++v4;\n }\n while ( v4 != (float *)v6 );\n return v5 + v7 != 2;\n}", + "ida_strip_asm": "sub_13E0:\nendbr64\ncmp esi, 1\njle short loc_1440\nlea edx, [rsi-2]\nmovss xmm0, dword ptr [rdi]\nlea rax, [rdi+4]\nxor esi, esi\nlea rcx, [rdi+rdx*4+8]\nxor edx, edx\nmov edi, 1\njmp short loc_1417\nloc_1408:\nucomiss xmm1, xmm0\ncmova edx, edi\nadd rax, 4\ncmp rax, rcx\njz short loc_1431\nloc_1417:\nmovaps xmm1, xmm0\nmovss xmm0, dword ptr [rax]\ncomiss xmm0, xmm1\njbe short loc_1408\nadd rax, 4\nmov esi, 1\ncmp rax, rcx\njnz short loc_1417\nloc_1431:\nadd edx, esi\ncmp edx, 2\nsetnz al\nretn\nloc_1440:\nmov eax, 1\nretn", + "ida_strip_pseudo": "char __fastcall sub_13E0(float *a1, int a2)\n{\n __int64 v2; // rdx\n float v3; // xmm0_4\n float *v4; // rax\n int v5; // esi\n __int64 v6; // rcx\n int v7; // edx\n float v8; // xmm1_4\n\n if ( a2 <= 1 )\n return 1;\n v2 = (unsigned int)(a2 - 2);\n v3 = *a1;\n v4 = a1 + 1;\n v5 = 0;\n v6 = (__int64)&a1[v2 + 2];\n v7 = 0;\n do\n {\n while ( 1 )\n {\n v8 = v3;\n v3 = *v4;\n if ( *v4 <= v8 )\n break;\n ++v4;\n v5 = 1;\n if ( v4 == (float *)v6 )\n return v5 + v7 != 2;\n }\n if ( v8 > v3 )\n v7 = 1;\n ++v4;\n }\n while ( v4 != (float *)v6 );\n return v5 + v7 != 2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char sub_13E0(float *a1, int a2) {\n long long v2;\n float v3;\n float *v4;\n int v5;\n long long v6;\n int v7;\n float v8;\n if (a2 <= 1) return 1;\n v2 = (unsigned int)(a2 - 2);\n v3 = *a1;\n v4 = a1 + 1;\n v5 = 0;\n v6 = (long long)&a1[v2 + 2];\n v7 = 0;\n do {\n while (1) {\n v8 = v3;\n v3 = *v4;\n if (*v4 <= v8) break;\n ++v4;\n v5 = 1;\n if (v4 == (float *)v6) return v5 + v7 != 2;\n }\n if (v8 > v3) v7 = 1;\n ++v4;\n } while (v4 != (float *)v6);\n return v5 + v7 != 2;\n}", + "ida_pseudo_norm": "char func0(float *a1, int a2) {\n long long v2;\n float v3;\n float *v4;\n int v5;\n long long v6;\n int v7;\n float v8;\n if (a2 <= 1) return 1;\n v2 = (unsigned int)(a2 - 2);\n v3 = *a1;\n v4 = a1 + 1;\n v5 = 0;\n v6 = (long long)&a1[v2 + 2];\n v7 = 0;\n do {\n while (1) {\n v8 = v3;\n v3 = *v4;\n if (*v4 <= v8) break;\n ++v4;\n v5 = 1;\n if (v4 == (float *)v6) return v5 + v7 != 2;\n }\n if (v8 > v3) v7 = 1;\n ++v4;\n } while (v4 != (float *)v6);\n return v5 + v7 != 2;\n}" + }, + { + "index": "HumanEval-C-58", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int *func0(int *l1, int size1, int *l2, int size2, int *out_size) {\n int *out = malloc(size1 * sizeof(int));\n int k = 0, i, j, m;\n for (i = 0; i < size1; i++) {\n int exists_in_out = 0;\n for (m = 0; m < k; m++) {\n if (out[m] == l1[i]) {\n exists_in_out = 1;\n break;\n }\n }\n if (!exists_in_out) {\n for (j = 0; j < size2; j++) {\n if (l1[i] == l2[j]) {\n out[k++] = l1[i];\n break;\n }\n }\n }\n }\n for (i = 0; i < k - 1; i++) {\n for (j = 0; j < k - i - 1; j++) {\n if (out[j] > out[j + 1]) {\n int temp = out[j];\n out[j] = out[j + 1];\n out[j + 1] = temp;\n }\n }\n }\n *out_size = k;\n return out;\n}", + "test": "#include \n#include \n#include \n\nint main() {\n int size;\n\n int l1[] = {1, 4, 3, 34, 653, 2, 5};\n int l2[] = {5, 7, 1, 5, 9, 653, 121};\n int expected1[] = {1, 5, 653};\n int *result1 = func0(l1, 7, l2, 7, &size);\n for (int i = 0; i < size; i++) {\n assert(result1[i] == expected1[i]);\n }\n free(result1);\n\n int l3[] = {5, 3, 2, 8};\n int l4[] = {3, 2};\n int expected2[] = {2, 3};\n int *result2 = func0(l3, 4, l4, 2, &size);\n for (int i = 0; i < size; i++) {\n assert(result2[i] == expected2[i]);\n }\n free(result2);\n\n int l5[] = {4, 3, 2, 8};\n int l6[] = {3, 2, 4};\n int expected3[] = {2, 3, 4};\n int *result3 = func0(l5, 4, l6, 3, &size);\n for (int i = 0; i < size; i++) {\n assert(result3[i] == expected3[i]);\n }\n free(result3);\n\n int l7[] = {4, 3, 2, 8};\n int l8[] = {};\n int *result4 = func0(l7, 4, l8, 0, &size);\n assert(size == 0); // Since l8 is empty, result4 should be empty as well\n free(result4);\n\n return 0;\n}\n", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmov [rbp+var_30], ecx\nmov [rbp+var_40], r8\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_20], 0\nmov [rbp+var_1C], 0\njmp loc_12C8\nloc_11EF:\nmov [rbp+var_10], 0\nmov [rbp+var_14], 0\njmp short loc_123C\nloc_11FF:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_1C]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_1238\nmov [rbp+var_10], 1\njmp short loc_1244\nloc_1238:\nadd [rbp+var_14], 1\nloc_123C:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_20]\njl short loc_11FF\nloc_1244:\ncmp [rbp+var_10], 0\njnz short loc_12C4\nmov [rbp+var_18], 0\njmp short loc_12BC\nloc_1253:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_18]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_12B8\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_20]\nlea edx, [rax+1]\nmov [rbp+var_20], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\njmp short loc_12C4\nloc_12B8:\nadd [rbp+var_18], 1\nloc_12BC:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_30]\njl short loc_1253\nloc_12C4:\nadd [rbp+var_1C], 1\nloc_12C8:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_2C]\njl loc_11EF\nmov [rbp+var_1C], 0\njmp loc_13A1\nloc_12E0:\nmov [rbp+var_18], 0\njmp loc_138B\nloc_12EC:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_18]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_1387\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nmov eax, [rbp+var_18]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rbp+var_18]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_18]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_C]\nmov [rdx], eax\nloc_1387:\nadd [rbp+var_18], 1\nloc_138B:\nmov eax, [rbp+var_20]\nsub eax, [rbp+var_1C]\nsub eax, 1\ncmp [rbp+var_18], eax\njl loc_12EC\nadd [rbp+var_1C], 1\nloc_13A1:\nmov eax, [rbp+var_20]\nsub eax, 1\ncmp [rbp+var_1C], eax\njl loc_12E0\nmov rax, [rbp+var_40]\nmov edx, [rbp+var_20]\nmov [rax], edx\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, __int64 a3, int a4, _DWORD *a5)\n{\n int v5; // eax\n int v10; // [rsp+20h] [rbp-20h]\n int i; // [rsp+24h] [rbp-1Ch]\n int m; // [rsp+24h] [rbp-1Ch]\n int k; // [rsp+28h] [rbp-18h]\n int n; // [rsp+28h] [rbp-18h]\n int j; // [rsp+2Ch] [rbp-14h]\n int v16; // [rsp+30h] [rbp-10h]\n int v17; // [rsp+34h] [rbp-Ch]\n _DWORD *v18; // [rsp+38h] [rbp-8h]\n\n v18 = malloc(4LL * a2);\n v10 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v16 = 0;\n for ( j = 0; j < v10; ++j )\n {\n if ( v18[j] == *(_DWORD *)(4LL * i + a1) )\n {\n v16 = 1;\n break;\n }\n }\n if ( !v16 )\n {\n for ( k = 0; k < a4; ++k )\n {\n if ( *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4LL * k + a3) )\n {\n v5 = v10++;\n v18[v5] = *(_DWORD *)(4LL * i + a1);\n break;\n }\n }\n }\n }\n for ( m = 0; m < v10 - 1; ++m )\n {\n for ( n = 0; n < v10 - m - 1; ++n )\n {\n if ( v18[n] > v18[n + 1] )\n {\n v17 = v18[n];\n v18[n] = v18[n + 1];\n v18[n + 1] = v17;\n }\n }\n }\n *a5 = v10;\n return v18;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmov [rbp+var_30], ecx\nmov [rbp+var_40], r8\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_20], 0\nmov [rbp+var_1C], 0\njmp loc_12C8\nloc_11EF:\nmov [rbp+var_10], 0\nmov [rbp+var_14], 0\njmp short loc_123C\nloc_11FF:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_1C]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_1238\nmov [rbp+var_10], 1\njmp short loc_1244\nloc_1238:\nadd [rbp+var_14], 1\nloc_123C:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_20]\njl short loc_11FF\nloc_1244:\ncmp [rbp+var_10], 0\njnz short loc_12C4\nmov [rbp+var_18], 0\njmp short loc_12BC\nloc_1253:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_18]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_12B8\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_20]\nlea edx, [rax+1]\nmov [rbp+var_20], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\njmp short loc_12C4\nloc_12B8:\nadd [rbp+var_18], 1\nloc_12BC:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_30]\njl short loc_1253\nloc_12C4:\nadd [rbp+var_1C], 1\nloc_12C8:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_2C]\njl loc_11EF\nmov [rbp+var_1C], 0\njmp loc_13A1\nloc_12E0:\nmov [rbp+var_18], 0\njmp loc_138B\nloc_12EC:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_18]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_1387\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nmov eax, [rbp+var_18]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rbp+var_18]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_18]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_C]\nmov [rdx], eax\nloc_1387:\nadd [rbp+var_18], 1\nloc_138B:\nmov eax, [rbp+var_20]\nsub eax, [rbp+var_1C]\nsub eax, 1\ncmp [rbp+var_18], eax\njl loc_12EC\nadd [rbp+var_1C], 1\nloc_13A1:\nmov eax, [rbp+var_20]\nsub eax, 1\ncmp [rbp+var_1C], eax\njl loc_12E0\nmov rax, [rbp+var_40]\nmov edx, [rbp+var_20]\nmov [rax], edx\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(__int64 a1, int a2, __int64 a3, int a4, _DWORD *a5)\n{\n int v5; // eax\n int v10; // [rsp+20h] [rbp-20h]\n int i; // [rsp+24h] [rbp-1Ch]\n int m; // [rsp+24h] [rbp-1Ch]\n int k; // [rsp+28h] [rbp-18h]\n int n; // [rsp+28h] [rbp-18h]\n int j; // [rsp+2Ch] [rbp-14h]\n int v16; // [rsp+30h] [rbp-10h]\n int v17; // [rsp+34h] [rbp-Ch]\n _DWORD *v18; // [rsp+38h] [rbp-8h]\n\n v18 = malloc(4LL * a2);\n v10 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v16 = 0;\n for ( j = 0; j < v10; ++j )\n {\n if ( v18[j] == *(_DWORD *)(4LL * i + a1) )\n {\n v16 = 1;\n break;\n }\n }\n if ( !v16 )\n {\n for ( k = 0; k < a4; ++k )\n {\n if ( *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4LL * k + a3) )\n {\n v5 = v10++;\n v18[v5] = *(_DWORD *)(4LL * i + a1);\n break;\n }\n }\n }\n }\n for ( m = 0; m < v10 - 1; ++m )\n {\n for ( n = 0; n < v10 - m - 1; ++n )\n {\n if ( v18[n] > v18[n + 1] )\n {\n v17 = v18[n];\n v18[n] = v18[n + 1];\n v18[n + 1] = v17;\n }\n }\n }\n *a5 = v10;\n return v18;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(long long a1, int a2, long long a3, int a4, uint32_t *a5) {\n int v5;\n int v10;\n int i;\n int m;\n int k;\n int n;\n int j;\n int v16;\n int v17;\n uint32_t *v18;\n v18 = malloc(4LL * a2);\n v10 = 0;\n for (i = 0; i < a2; ++i) {\n v16 = 0;\n for (j = 0; j < v10; ++j) {\n if (v18[j] == *(uint32_t *)(4LL * i + a1)) {\n v16 = 1;\n break;\n }\n }\n if (!v16) {\n for (k = 0; k < a4; ++k) {\n if (*(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4LL * k + a3)) {\n v5 = v10++;\n v18[v5] = *(uint32_t *)(4LL * i + a1);\n break;\n }\n }\n }\n }\n for (m = 0; m < v10 - 1; ++m) {\n for (n = 0; n < v10 - m - 1; ++n) {\n if (v18[n] > v18[n + 1]) {\n v17 = v18[n];\n v18[n] = v18[n + 1];\n v18[n + 1] = v17;\n }\n }\n }\n *a5 = v10;\n return v18;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, long long a3, int a4, uint32_t *a5) {\n int v5;\n int v10;\n int i;\n int m;\n int k;\n int n;\n int j;\n int v16;\n int v17;\n uint32_t *v18;\n v18 = malloc(4LL * a2);\n v10 = 0;\n for (i = 0; i < a2; ++i) {\n v16 = 0;\n for (j = 0; j < v10; ++j) {\n if (v18[j] == *(uint32_t *)(4LL * i + a1)) {\n v16 = 1;\n break;\n }\n }\n if (!v16) {\n for (k = 0; k < a4; ++k) {\n if (*(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4LL * k + a3)) {\n v5 = v10++;\n v18[v5] = *(uint32_t *)(4LL * i + a1);\n break;\n }\n }\n }\n }\n for (m = 0; m < v10 - 1; ++m) {\n for (n = 0; n < v10 - m - 1; ++n) {\n if (v18[n] > v18[n + 1]) {\n v17 = v18[n];\n v18[n] = v18[n + 1];\n v18[n + 1] = v17;\n }\n }\n }\n *a5 = v10;\n return v18;\n}" + }, + { + "index": "HumanEval-C-58", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int *func0(int *l1, int size1, int *l2, int size2, int *out_size) {\n int *out = malloc(size1 * sizeof(int));\n int k = 0, i, j, m;\n for (i = 0; i < size1; i++) {\n int exists_in_out = 0;\n for (m = 0; m < k; m++) {\n if (out[m] == l1[i]) {\n exists_in_out = 1;\n break;\n }\n }\n if (!exists_in_out) {\n for (j = 0; j < size2; j++) {\n if (l1[i] == l2[j]) {\n out[k++] = l1[i];\n break;\n }\n }\n }\n }\n for (i = 0; i < k - 1; i++) {\n for (j = 0; j < k - i - 1; j++) {\n if (out[j] > out[j + 1]) {\n int temp = out[j];\n out[j] = out[j + 1];\n out[j + 1] = temp;\n }\n }\n }\n *out_size = k;\n return out;\n}", + "test": "#include \n#include \n#include \n\nint main() {\n int size;\n\n int l1[] = {1, 4, 3, 34, 653, 2, 5};\n int l2[] = {5, 7, 1, 5, 9, 653, 121};\n int expected1[] = {1, 5, 653};\n int *result1 = func0(l1, 7, l2, 7, &size);\n for (int i = 0; i < size; i++) {\n assert(result1[i] == expected1[i]);\n }\n free(result1);\n\n int l3[] = {5, 3, 2, 8};\n int l4[] = {3, 2};\n int expected2[] = {2, 3};\n int *result2 = func0(l3, 4, l4, 2, &size);\n for (int i = 0; i < size; i++) {\n assert(result2[i] == expected2[i]);\n }\n free(result2);\n\n int l5[] = {4, 3, 2, 8};\n int l6[] = {3, 2, 4};\n int expected3[] = {2, 3, 4};\n int *result3 = func0(l5, 4, l6, 3, &size);\n for (int i = 0; i < size; i++) {\n assert(result3[i] == expected3[i]);\n }\n free(result3);\n\n int l7[] = {4, 3, 2, 8};\n int l8[] = {};\n int *result4 = func0(l7, 4, l8, 0, &size);\n assert(size == 0); // Since l8 is empty, result4 should be empty as well\n free(result4);\n\n return 0;\n}\n", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r15, rdi\nmov r14d, esi\nmov r12, rdx\nmov ebp, ecx\nmov rbx, r8\nmovsxd r13, esi\nshl r13, 2\nmov rdi, r13; size\ncall _malloc\nmov rdi, rax\ntest r14d, r14d\njle loc_1287\nmov rsi, r15\nadd r13, r15\nmovsxd rax, ebp\nlea r8, [r12+rax*4]\nmov r9d, 0\njmp short loc_120C\nloc_11F9:\nmovsxd rax, r9d\nmov [rdi+rax*4], edx\nlea r9d, [r9+1]\nloc_1203:\nadd rsi, 4\ncmp rsi, r13\njz short loc_1242\nloc_120C:\ntest r9d, r9d\njle short loc_122A\nmov edx, [rsi]\nmov rax, rdi\nmovsxd rcx, r9d\nlea rcx, [rdi+rcx*4]\nloc_121D:\ncmp [rax], edx\njz short loc_1203\nadd rax, 4\ncmp rax, rcx\njnz short loc_121D\nloc_122A:\ntest ebp, ebp\njle short loc_1203\nmov edx, [rsi]\nmov rax, r12\nloc_1233:\ncmp edx, [rax]\njz short loc_11F9\nadd rax, 4\ncmp rax, r8\njnz short loc_1233\njmp short loc_1203\nloc_1242:\ncmp r9d, 1\njle short loc_128D\nmov r8d, r9d\nlea r10, [rdi+4]\njmp short loc_1274\nloc_1251:\nadd rax, 4\ncmp rsi, rax\njz short loc_126A\nloc_125A:\nmov edx, [rax]\nmov ecx, [rax+4]\ncmp edx, ecx\njle short loc_1251\nmov [rax], ecx\nmov [rax+4], edx\njmp short loc_1251\nloc_126A:\nsub r8d, 1\ncmp r8d, 1\njz short loc_128D\nloc_1274:\ncmp r8d, 1\njle short loc_12A2\nmov rax, rdi\nlea edx, [r8-2]\nlea rsi, [r10+rdx*4]\njmp short loc_125A\nloc_1287:\nmov r9d, 0\nloc_128D:\nmov [rbx], r9d\nmov rax, rdi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_12A2:\nsub r8d, 1\njmp short loc_1274", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2, _DWORD *a3, int a4, int *a5)\n{\n size_t v9; // r13\n _DWORD *v10; // rdi\n int *v11; // rsi\n int *v12; // r13\n int v13; // r9d\n _DWORD *v14; // rax\n int v15; // edx\n _DWORD *v16; // rax\n int i; // r8d\n int *v18; // rax\n int v19; // edx\n int v20; // ecx\n\n v9 = a2;\n v10 = malloc(v9 * 4);\n if ( a2 <= 0 )\n {\n v13 = 0;\n }\n else\n {\n v11 = a1;\n v12 = &a1[v9];\n v13 = 0;\n do\n {\n if ( v13 <= 0 )\n {\nLABEL_9:\n if ( a4 > 0 )\n {\n v15 = *v11;\n v16 = a3;\n while ( v15 != *v16 )\n {\n if ( ++v16 == &a3[a4] )\n goto LABEL_4;\n }\n v10[v13++] = v15;\n }\n }\n else\n {\n v14 = v10;\n while ( *v14 != *v11 )\n {\n if ( ++v14 == &v10[v13] )\n goto LABEL_9;\n }\n }\nLABEL_4:\n ++v11;\n }\n while ( v11 != v12 );\n if ( v13 > 1 )\n {\n for ( i = v13; i != 1; --i )\n {\n while ( i <= 1 )\n --i;\n v18 = v10;\n do\n {\n v19 = *v18;\n v20 = v18[1];\n if ( *v18 > v20 )\n {\n *v18 = v20;\n v18[1] = v19;\n }\n ++v18;\n }\n while ( &v10[i - 2 + 1] != v18 );\n }\n }\n }\n *a5 = v13;\n return v10;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r15, rdi\nmov r14d, esi\nmov r12, rdx\nmov ebp, ecx\nmov rbx, r8\nmovsxd r13, esi\nshl r13, 2\nmov rdi, r13; size\ncall _malloc\nmov rdi, rax\ntest r14d, r14d\njle loc_1287\nmov rsi, r15\nadd r13, r15\nmovsxd rax, ebp\nlea r8, [r12+rax*4]\nmov r9d, 0\njmp short loc_120C\nloc_11F9:\nmovsxd rax, r9d\nmov [rdi+rax*4], edx\nlea r9d, [r9+1]\nloc_1203:\nadd rsi, 4\ncmp rsi, r13\njz short loc_1242\nloc_120C:\ntest r9d, r9d\njle short loc_122A\nmov edx, [rsi]\nmov rax, rdi\nmovsxd rcx, r9d\nlea rcx, [rdi+rcx*4]\nloc_121D:\ncmp [rax], edx\njz short loc_1203\nadd rax, 4\ncmp rax, rcx\njnz short loc_121D\nloc_122A:\ntest ebp, ebp\njle short loc_1203\nmov edx, [rsi]\nmov rax, r12\nloc_1233:\ncmp edx, [rax]\njz short loc_11F9\nadd rax, 4\ncmp rax, r8\njnz short loc_1233\njmp short loc_1203\nloc_1242:\ncmp r9d, 1\njle short loc_128D\nmov r8d, r9d\nlea r10, [rdi+4]\njmp short loc_1274\nloc_1251:\nadd rax, 4\ncmp rsi, rax\njz short loc_126A\nloc_125A:\nmov edx, [rax]\nmov ecx, [rax+4]\ncmp edx, ecx\njle short loc_1251\nmov [rax], ecx\nmov [rax+4], edx\njmp short loc_1251\nloc_126A:\nsub r8d, 1\ncmp r8d, 1\njz short loc_128D\nloc_1274:\ncmp r8d, 1\njle short loc_12A2\nmov rax, rdi\nlea edx, [r8-2]\nlea rsi, [r10+rdx*4]\njmp short loc_125A\nloc_1287:\nmov r9d, 0\nloc_128D:\nmov [rbx], r9d\nmov rax, rdi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_12A2:\nsub r8d, 1\njmp short loc_1274", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(int *a1, int a2, _DWORD *a3, int a4, int *a5)\n{\n size_t v9; // r13\n _DWORD *v10; // rdi\n int *v11; // rsi\n int *v12; // r13\n int v13; // r9d\n _DWORD *v14; // rax\n int v15; // edx\n _DWORD *v16; // rax\n int i; // r8d\n int *v18; // rax\n int v19; // edx\n int v20; // ecx\n\n v9 = a2;\n v10 = malloc(v9 * 4);\n if ( a2 <= 0 )\n {\n v13 = 0;\n }\n else\n {\n v11 = a1;\n v12 = &a1[v9];\n v13 = 0;\n do\n {\n if ( v13 <= 0 )\n {\nLABEL_9:\n if ( a4 > 0 )\n {\n v15 = *v11;\n v16 = a3;\n while ( v15 != *v16 )\n {\n if ( ++v16 == &a3[a4] )\n goto LABEL_4;\n }\n v10[v13++] = v15;\n }\n }\n else\n {\n v14 = v10;\n while ( *v14 != *v11 )\n {\n if ( ++v14 == &v10[v13] )\n goto LABEL_9;\n }\n }\nLABEL_4:\n ++v11;\n }\n while ( v11 != v12 );\n if ( v13 > 1 )\n {\n for ( i = v13; i != 1; --i )\n {\n while ( i <= 1 )\n --i;\n v18 = v10;\n do\n {\n v19 = *v18;\n v20 = v18[1];\n if ( *v18 > v20 )\n {\n *v18 = v20;\n v18[1] = v19;\n }\n ++v18;\n }\n while ( &v10[i - 2 + 1] != v18 );\n }\n }\n }\n *a5 = v13;\n return v10;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(int *a1, int a2, uint32_t *a3, int a4, int *a5) {\n unsigned int v9;\n uint32_t *v10;\n int *v11;\n int *v12;\n int v13;\n uint32_t *v14;\n int v15;\n uint32_t *v16;\n int i;\n int *v18;\n int v19;\n int v20;\n v9 = a2;\n v10 = malloc(v9 * 4);\n if (a2 <= 0) {\n v13 = 0;\n } else {\n v11 = a1;\n v12 = &a1[v9];\n v13 = 0;\n do {\n if (v13 <= 0) {\n LABEL_9:\n if (a4 > 0) {\n v15 = *v11;\n v16 = a3;\n while (v15 != *v16) {\n if (++v16 == &a3[a4]) goto LABEL_4;\n }\n v10[v13++] = v15;\n }\n } else {\n v14 = v10;\n while (*v14 != *v11) {\n if (++v14 == &v10[v13]) goto LABEL_9;\n }\n }\n LABEL_4:\n ++v11;\n } while (v11 != v12);\n if (v13 > 1) {\n for (i = v13; i != 1; --i) {\n while (i <= 1) --i;\n v18 = v10;\n do {\n v19 = *v18;\n v20 = v18[1];\n if (*v18 > v20) {\n *v18 = v20;\n v18[1] = v19;\n }\n ++v18;\n } while (&v10[i - 2 + 1] != v18);\n }\n }\n }\n *a5 = v13;\n return v10;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2, uint32_t *a3, int a4, int *a5) {\n unsigned int v9;\n uint32_t *v10;\n int *v11;\n int *v12;\n int v13;\n uint32_t *v14;\n int v15;\n uint32_t *v16;\n int i;\n int *v18;\n int v19;\n int v20;\n v9 = a2;\n v10 = malloc(v9 * 4);\n if (a2 <= 0) {\n v13 = 0;\n } else {\n v11 = a1;\n v12 = &a1[v9];\n v13 = 0;\n do {\n if (v13 <= 0) {\n LABEL_9:\n if (a4 > 0) {\n v15 = *v11;\n v16 = a3;\n while (v15 != *v16) {\n if (++v16 == &a3[a4]) goto LABEL_4;\n }\n v10[v13++] = v15;\n }\n } else {\n v14 = v10;\n while (*v14 != *v11) {\n if (++v14 == &v10[v13]) goto LABEL_9;\n }\n }\n LABEL_4:\n ++v11;\n } while (v11 != v12);\n if (v13 > 1) {\n for (i = v13; i != 1; --i) {\n while (i <= 1) --i;\n v18 = v10;\n do {\n v19 = *v18;\n v20 = v18[1];\n if (*v18 > v20) {\n *v18 = v20;\n v18[1] = v19;\n }\n ++v18;\n } while (&v10[i - 2 + 1] != v18);\n }\n }\n }\n *a5 = v13;\n return v10;\n}" + }, + { + "index": "HumanEval-C-58", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int *func0(int *l1, int size1, int *l2, int size2, int *out_size) {\n int *out = malloc(size1 * sizeof(int));\n int k = 0, i, j, m;\n for (i = 0; i < size1; i++) {\n int exists_in_out = 0;\n for (m = 0; m < k; m++) {\n if (out[m] == l1[i]) {\n exists_in_out = 1;\n break;\n }\n }\n if (!exists_in_out) {\n for (j = 0; j < size2; j++) {\n if (l1[i] == l2[j]) {\n out[k++] = l1[i];\n break;\n }\n }\n }\n }\n for (i = 0; i < k - 1; i++) {\n for (j = 0; j < k - i - 1; j++) {\n if (out[j] > out[j + 1]) {\n int temp = out[j];\n out[j] = out[j + 1];\n out[j + 1] = temp;\n }\n }\n }\n *out_size = k;\n return out;\n}", + "test": "#include \n#include \n#include \n\nint main() {\n int size;\n\n int l1[] = {1, 4, 3, 34, 653, 2, 5};\n int l2[] = {5, 7, 1, 5, 9, 653, 121};\n int expected1[] = {1, 5, 653};\n int *result1 = func0(l1, 7, l2, 7, &size);\n for (int i = 0; i < size; i++) {\n assert(result1[i] == expected1[i]);\n }\n free(result1);\n\n int l3[] = {5, 3, 2, 8};\n int l4[] = {3, 2};\n int expected2[] = {2, 3};\n int *result2 = func0(l3, 4, l4, 2, &size);\n for (int i = 0; i < size; i++) {\n assert(result2[i] == expected2[i]);\n }\n free(result2);\n\n int l5[] = {4, 3, 2, 8};\n int l6[] = {3, 2, 4};\n int expected3[] = {2, 3, 4};\n int *result3 = func0(l5, 4, l6, 3, &size);\n for (int i = 0; i < size; i++) {\n assert(result3[i] == expected3[i]);\n }\n free(result3);\n\n int l7[] = {4, 3, 2, 8};\n int l8[] = {};\n int *result4 = func0(l7, 4, l8, 0, &size);\n assert(size == 0); // Since l8 is empty, result4 should be empty as well\n free(result4);\n\n return 0;\n}\n", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\nmovsxd r10, esi\npush r14\nlea r14, ds:0[r10*4]\nmov r15, r10\npush r13\nmov r13d, ecx\npush r12\nmov r12, rdx\npush rbp\nmov rbp, r8\npush rbx\nmov rbx, rdi\nmov rdi, r14; size\nsub rsp, 8\ncall _malloc\nmov r8, rax\ntest r15d, r15d\njle loc_1580\nmovsxd rax, r13d\nmov rsi, rbx\nlea r10, [rbx+r14]\nxor r9d, r9d\nlea rdi, [r12+rax*4]\nnop dword ptr [rax+00000000h]\nloc_1498:\nmovsxd rax, r9d\nlea rcx, [r8+rax*4]\ntest r9d, r9d\njle loc_1538\nloc_14A8:\nmov edx, [rsi]\nmov rax, r8\njmp short loc_14B9\nloc_14B0:\nadd rax, 4\ncmp rax, rcx\njz short loc_1538\nloc_14B9:\ncmp [rax], edx\njnz short loc_14B0\nadd rsi, 4\ncmp rsi, r10\njnz short loc_14A8\nloc_14C6:\ncmp r9d, 1\njle short loc_151F\nmov edi, r9d\nlea r10, [r8+4]\nnop dword ptr [rax+rax+00h]\nloc_14D8:\ncmp edi, 1\njle loc_1578\nlea edx, [rdi-2]\nmov rax, r8\nlea rsi, [r10+rdx*4]\nnop dword ptr [rax+rax+00h]\nloc_14F0:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd edx, xmm0\nmovd ecx, xmm1\ncmp ecx, edx\njge short loc_150E\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_150E:\nadd rax, 4\ncmp rsi, rax\njnz short loc_14F0\nsub edi, 1\ncmp edi, 1\njnz short loc_14D8\nloc_151F:\nmov [rbp+0], r9d\nadd rsp, 8\nmov rax, r8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1538:\ntest r13d, r13d\njle short loc_1560\nmov edx, [rsi]\nmov rax, r12\njmp short loc_1551\nloc_1548:\nadd rax, 4\ncmp rax, rdi\njz short loc_1560\nloc_1551:\ncmp edx, [rax]\njnz short loc_1548\nmovsxd rax, r9d\nadd r9d, 1\nmov [r8+rax*4], edx\nloc_1560:\nadd rsi, 4\ncmp rsi, r10\njnz loc_1498\njmp loc_14C6\nloc_1578:\nsub edi, 1\njmp loc_14D8\nloc_1580:\nxor r9d, r9d\njmp short loc_151F", + "ida_pseudo": "__m128i *__fastcall func0(__int32 *a1, int a2, _DWORD *a3, int a4, int *a5)\n{\n size_t v5; // r14\n __m128i *v9; // r8\n __int32 *v10; // rsi\n __int32 *v11; // r10\n int v12; // r9d\n __m128i *v13; // rax\n int i; // edi\n __m128i *v15; // rax\n __m128i v16; // xmm0\n __int32 v18; // edx\n _DWORD *v19; // rax\n __int64 v20; // rax\n\n v5 = a2;\n v9 = (__m128i *)malloc(v5 * 4);\n if ( a2 <= 0 )\n {\n v12 = 0;\n }\n else\n {\n v10 = a1;\n v11 = &a1[v5];\n v12 = 0;\n while ( v12 <= 0 )\n {\nLABEL_17:\n if ( a4 > 0 )\n {\n v18 = *v10;\n v19 = a3;\n while ( v18 != *v19 )\n {\n if ( ++v19 == &a3[a4] )\n goto LABEL_22;\n }\n v20 = v12++;\n v9->m128i_i32[v20] = v18;\n }\nLABEL_22:\n if ( ++v10 == v11 )\n goto LABEL_8;\n }\n do\n {\n v13 = v9;\n while ( v13->m128i_i32[0] != *v10 )\n {\n v13 = (__m128i *)((char *)v13 + 4);\n if ( v13 == (__m128i *)((char *)v9 + 4 * v12) )\n goto LABEL_17;\n }\n ++v10;\n }\n while ( v10 != v11 );\nLABEL_8:\n if ( v12 > 1 )\n {\n for ( i = v12; i != 1; --i )\n {\n while ( i <= 1 )\n --i;\n v15 = v9;\n do\n {\n v16 = _mm_loadl_epi64(v15);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v16, 229)) < _mm_cvtsi128_si32(v16) )\n v15->m128i_i64[0] = _mm_shuffle_epi32(v16, 225).m128i_u64[0];\n v15 = (__m128i *)((char *)v15 + 4);\n }\n while ( (__m128i *)((char *)v9->m128i_i64 + 4 * (unsigned int)(i - 2) + 4) != v15 );\n }\n }\n }\n *a5 = v12;\n return v9;\n}", + "ida_strip_asm": "sub_1440:\nendbr64\npush r15\nmovsxd r10, esi\npush r14\nlea r14, ds:0[r10*4]\nmov r15, r10\npush r13\nmov r13d, ecx\npush r12\nmov r12, rdx\npush rbp\nmov rbp, r8\npush rbx\nmov rbx, rdi\nmov rdi, r14; size\nsub rsp, 8\ncall _malloc\nmov r8, rax\ntest r15d, r15d\njle loc_1580\nmovsxd rax, r13d\nmov rsi, rbx\nlea r10, [rbx+r14]\nxor r9d, r9d\nlea rdi, [r12+rax*4]\nnop dword ptr [rax+00000000h]\nloc_1498:\nmovsxd rax, r9d\nlea rcx, [r8+rax*4]\ntest r9d, r9d\njle loc_1538\nloc_14A8:\nmov edx, [rsi]\nmov rax, r8\njmp short loc_14B9\nloc_14B0:\nadd rax, 4\ncmp rax, rcx\njz short loc_1538\nloc_14B9:\ncmp [rax], edx\njnz short loc_14B0\nadd rsi, 4\ncmp rsi, r10\njnz short loc_14A8\nloc_14C6:\ncmp r9d, 1\njle short loc_151F\nmov edi, r9d\nlea r10, [r8+4]\nnop dword ptr [rax+rax+00h]\nloc_14D8:\ncmp edi, 1\njle loc_1578\nlea edx, [rdi-2]\nmov rax, r8\nlea rsi, [r10+rdx*4]\nnop dword ptr [rax+rax+00h]\nloc_14F0:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd edx, xmm0\nmovd ecx, xmm1\ncmp ecx, edx\njge short loc_150E\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_150E:\nadd rax, 4\ncmp rsi, rax\njnz short loc_14F0\nsub edi, 1\ncmp edi, 1\njnz short loc_14D8\nloc_151F:\nmov [rbp+0], r9d\nadd rsp, 8\nmov rax, r8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1538:\ntest r13d, r13d\njle short loc_1560\nmov edx, [rsi]\nmov rax, r12\njmp short loc_1551\nloc_1548:\nadd rax, 4\ncmp rax, rdi\njz short loc_1560\nloc_1551:\ncmp edx, [rax]\njnz short loc_1548\nmovsxd rax, r9d\nadd r9d, 1\nmov [r8+rax*4], edx\nloc_1560:\nadd rsi, 4\ncmp rsi, r10\njnz loc_1498\njmp loc_14C6\nloc_1578:\nsub edi, 1\njmp loc_14D8\nloc_1580:\nxor r9d, r9d\njmp short loc_151F", + "ida_strip_pseudo": "__m128i *__fastcall sub_1440(__int32 *a1, int a2, _DWORD *a3, int a4, int *a5)\n{\n size_t v5; // r14\n __m128i *v9; // r8\n __int32 *v10; // rsi\n __int32 *v11; // r10\n int v12; // r9d\n __m128i *v13; // rax\n int i; // edi\n __m128i *v15; // rax\n __m128i v16; // xmm0\n __int32 v18; // edx\n _DWORD *v19; // rax\n __int64 v20; // rax\n\n v5 = a2;\n v9 = (__m128i *)malloc(v5 * 4);\n if ( a2 <= 0 )\n {\n v12 = 0;\n }\n else\n {\n v10 = a1;\n v11 = &a1[v5];\n v12 = 0;\n while ( v12 <= 0 )\n {\nLABEL_17:\n if ( a4 > 0 )\n {\n v18 = *v10;\n v19 = a3;\n while ( v18 != *v19 )\n {\n if ( ++v19 == &a3[a4] )\n goto LABEL_22;\n }\n v20 = v12++;\n v9->m128i_i32[v20] = v18;\n }\nLABEL_22:\n if ( ++v10 == v11 )\n goto LABEL_8;\n }\n do\n {\n v13 = v9;\n while ( v13->m128i_i32[0] != *v10 )\n {\n v13 = (__m128i *)((char *)v13 + 4);\n if ( v13 == (__m128i *)((char *)v9 + 4 * v12) )\n goto LABEL_17;\n }\n ++v10;\n }\n while ( v10 != v11 );\nLABEL_8:\n if ( v12 > 1 )\n {\n for ( i = v12; i != 1; --i )\n {\n while ( i <= 1 )\n --i;\n v15 = v9;\n do\n {\n v16 = _mm_loadl_epi64(v15);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v16, 229)) < _mm_cvtsi128_si32(v16) )\n v15->m128i_i64[0] = _mm_shuffle_epi32(v16, 225).m128i_u64[0];\n v15 = (__m128i *)((char *)v15 + 4);\n }\n while ( (__m128i *)((char *)v9->m128i_i64 + 4 * (unsigned int)(i - 2) + 4) != v15 );\n }\n }\n }\n *a5 = v12;\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__m128i *sub_1440(int *a1, int a2, uint32_t *a3, int a4, int *a5) {\n unsigned int v5;\n __m128i *v9;\n int *v10;\n int *v11;\n int v12;\n __m128i *v13;\n int i;\n __m128i *v15;\n __m128i v16;\n int v18;\n uint32_t *v19;\n long long v20;\n v5 = a2;\n v9 = (__m128i *)malloc(v5 * 4);\n if (a2 <= 0) {\n v12 = 0;\n } else {\n v10 = a1;\n v11 = &a1[v5];\n v12 = 0;\n while (v12 <= 0) {\n LABEL_17:\n if (a4 > 0) {\n v18 = *v10;\n v19 = a3;\n while (v18 != *v19) {\n if (++v19 == &a3[a4]) goto LABEL_22;\n }\n v20 = v12++;\n v9->m128i_i32[v20] = v18;\n }\n LABEL_22:\n if (++v10 == v11) goto LABEL_8;\n }\n do {\n v13 = v9;\n while (v13->m128i_i32[0] != *v10) {\n v13 = (__m128i *)((char *)v13 + 4);\n if (v13 == (__m128i *)((char *)v9 + 4 * v12)) goto LABEL_17;\n }\n ++v10;\n } while (v10 != v11);\n LABEL_8:\n if (v12 > 1) {\n for (i = v12; i != 1; --i) {\n while (i <= 1) --i;\n v15 = v9;\n do {\n v16 = _mm_loadl_epi64(v15);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v16, 229)) <\n _mm_cvtsi128_si32(v16))\n v15->m128i_i64[0] = _mm_shuffle_epi32(v16, 225).m128i_u64[0];\n v15 = (__m128i *)((char *)v15 + 4);\n } while ((__m128i *)((char *)v9->m128i_i64 + 4 * (unsigned int)(i - 2) +\n 4) != v15);\n }\n }\n }\n *a5 = v12;\n return v9;\n}", + "ida_pseudo_norm": "__m128i *func0(int *a1, int a2, uint32_t *a3, int a4, int *a5) {\n unsigned int v5;\n __m128i *v9;\n int *v10;\n int *v11;\n int v12;\n __m128i *v13;\n int i;\n __m128i *v15;\n __m128i v16;\n int v18;\n uint32_t *v19;\n long long v20;\n v5 = a2;\n v9 = (__m128i *)malloc(v5 * 4);\n if (a2 <= 0) {\n v12 = 0;\n } else {\n v10 = a1;\n v11 = &a1[v5];\n v12 = 0;\n while (v12 <= 0) {\n LABEL_17:\n if (a4 > 0) {\n v18 = *v10;\n v19 = a3;\n while (v18 != *v19) {\n if (++v19 == &a3[a4]) goto LABEL_22;\n }\n v20 = v12++;\n v9->m128i_i32[v20] = v18;\n }\n LABEL_22:\n if (++v10 == v11) goto LABEL_8;\n }\n do {\n v13 = v9;\n while (v13->m128i_i32[0] != *v10) {\n v13 = (__m128i *)((char *)v13 + 4);\n if (v13 == (__m128i *)((char *)v9 + 4 * v12)) goto LABEL_17;\n }\n ++v10;\n } while (v10 != v11);\n LABEL_8:\n if (v12 > 1) {\n for (i = v12; i != 1; --i) {\n while (i <= 1) --i;\n v15 = v9;\n do {\n v16 = _mm_loadl_epi64(v15);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v16, 229)) <\n _mm_cvtsi128_si32(v16))\n v15->m128i_i64[0] = _mm_shuffle_epi32(v16, 225).m128i_u64[0];\n v15 = (__m128i *)((char *)v15 + 4);\n } while ((__m128i *)((char *)v9->m128i_i64 + 4 * (unsigned int)(i - 2) +\n 4) != v15);\n }\n }\n }\n *a5 = v12;\n return v9;\n}" + }, + { + "index": "HumanEval-C-58", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int *func0(int *l1, int size1, int *l2, int size2, int *out_size) {\n int *out = malloc(size1 * sizeof(int));\n int k = 0, i, j, m;\n for (i = 0; i < size1; i++) {\n int exists_in_out = 0;\n for (m = 0; m < k; m++) {\n if (out[m] == l1[i]) {\n exists_in_out = 1;\n break;\n }\n }\n if (!exists_in_out) {\n for (j = 0; j < size2; j++) {\n if (l1[i] == l2[j]) {\n out[k++] = l1[i];\n break;\n }\n }\n }\n }\n for (i = 0; i < k - 1; i++) {\n for (j = 0; j < k - i - 1; j++) {\n if (out[j] > out[j + 1]) {\n int temp = out[j];\n out[j] = out[j + 1];\n out[j + 1] = temp;\n }\n }\n }\n *out_size = k;\n return out;\n}", + "test": "#include \n#include \n#include \n\nint main() {\n int size;\n\n int l1[] = {1, 4, 3, 34, 653, 2, 5};\n int l2[] = {5, 7, 1, 5, 9, 653, 121};\n int expected1[] = {1, 5, 653};\n int *result1 = func0(l1, 7, l2, 7, &size);\n for (int i = 0; i < size; i++) {\n assert(result1[i] == expected1[i]);\n }\n free(result1);\n\n int l3[] = {5, 3, 2, 8};\n int l4[] = {3, 2};\n int expected2[] = {2, 3};\n int *result2 = func0(l3, 4, l4, 2, &size);\n for (int i = 0; i < size; i++) {\n assert(result2[i] == expected2[i]);\n }\n free(result2);\n\n int l5[] = {4, 3, 2, 8};\n int l6[] = {3, 2, 4};\n int expected3[] = {2, 3, 4};\n int *result3 = func0(l5, 4, l6, 3, &size);\n for (int i = 0; i < size; i++) {\n assert(result3[i] == expected3[i]);\n }\n free(result3);\n\n int l7[] = {4, 3, 2, 8};\n int l8[] = {};\n int *result4 = func0(l7, 4, l8, 0, &size);\n assert(size == 0); // Since l8 is empty, result4 should be empty as well\n free(result4);\n\n return 0;\n}\n", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\nmovsxd r10, esi\npush r14\nlea r14, ds:0[r10*4]\nmov r15, r10\npush r13\nmov r13d, ecx\npush r12\nmov r12, rdx\npush rbp\nmov rbp, r8\npush rbx\nmov rbx, rdi\nmov rdi, r14; size\nsub rsp, 8\ncall _malloc\nmov r8, rax\ntest r15d, r15d\njle loc_1550\nmovsxd rax, r13d\nmov rsi, rbx\nlea r10, [rbx+r14]\nxor r9d, r9d\nlea rdi, [r12+rax*4]\nnop dword ptr [rax+00000000h]\nloc_1468:\nmovsxd rax, r9d\nlea rcx, [r8+rax*4]\ntest r9d, r9d\njle loc_1508\nloc_1478:\nmov edx, [rsi]\nmov rax, r8\njmp short loc_1489\nloc_1480:\nadd rax, 4\ncmp rax, rcx\njz short loc_1508\nloc_1489:\ncmp [rax], edx\njnz short loc_1480\nadd rsi, 4\ncmp rsi, r10\njnz short loc_1478\nloc_1496:\ncmp r9d, 1\njle short loc_14EF\nmov edi, r9d\nlea r10, [r8+4]\nnop dword ptr [rax+rax+00h]\nloc_14A8:\ncmp edi, 1\njle loc_1548\nlea edx, [rdi-2]\nmov rax, r8\nlea rsi, [r10+rdx*4]\nnop dword ptr [rax+rax+00h]\nloc_14C0:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd ecx, xmm0\nmovd edx, xmm1\ncmp ecx, edx\njle short loc_14DE\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_14DE:\nadd rax, 4\ncmp rax, rsi\njnz short loc_14C0\nsub edi, 1\ncmp edi, 1\njnz short loc_14A8\nloc_14EF:\nmov [rbp+0], r9d\nadd rsp, 8\nmov rax, r8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1508:\ntest r13d, r13d\njle short loc_1530\nmov edx, [rsi]\nmov rax, r12\njmp short loc_1521\nloc_1518:\nadd rax, 4\ncmp rax, rdi\njz short loc_1530\nloc_1521:\ncmp edx, [rax]\njnz short loc_1518\nmovsxd rax, r9d\nadd r9d, 1\nmov [r8+rax*4], edx\nloc_1530:\nadd rsi, 4\ncmp rsi, r10\njnz loc_1468\njmp loc_1496\nloc_1548:\nsub edi, 1\njmp loc_14A8\nloc_1550:\nxor r9d, r9d\njmp short loc_14EF", + "ida_pseudo": "__m128i *__fastcall func0(__int32 *a1, int a2, _DWORD *a3, int a4, int *a5)\n{\n size_t v5; // r14\n __m128i *v9; // r8\n __int32 *v10; // rsi\n __int32 *v11; // r10\n int v12; // r9d\n __m128i *v13; // rax\n int i; // edi\n __m128i *v15; // rax\n __m128i v16; // xmm0\n __int32 v18; // edx\n _DWORD *v19; // rax\n __int64 v20; // rax\n\n v5 = a2;\n v9 = (__m128i *)malloc(v5 * 4);\n if ( a2 <= 0 )\n {\n v12 = 0;\n }\n else\n {\n v10 = a1;\n v11 = &a1[v5];\n v12 = 0;\n while ( v12 <= 0 )\n {\nLABEL_17:\n if ( a4 > 0 )\n {\n v18 = *v10;\n v19 = a3;\n while ( v18 != *v19 )\n {\n if ( ++v19 == &a3[a4] )\n goto LABEL_22;\n }\n v20 = v12++;\n v9->m128i_i32[v20] = v18;\n }\nLABEL_22:\n if ( ++v10 == v11 )\n goto LABEL_8;\n }\n do\n {\n v13 = v9;\n while ( v13->m128i_i32[0] != *v10 )\n {\n v13 = (__m128i *)((char *)v13 + 4);\n if ( v13 == (__m128i *)((char *)v9 + 4 * v12) )\n goto LABEL_17;\n }\n ++v10;\n }\n while ( v10 != v11 );\nLABEL_8:\n if ( v12 > 1 )\n {\n for ( i = v12; i != 1; --i )\n {\n while ( i <= 1 )\n --i;\n v15 = v9;\n do\n {\n v16 = _mm_loadl_epi64(v15);\n if ( _mm_cvtsi128_si32(v16) > _mm_cvtsi128_si32(_mm_shuffle_epi32(v16, 229)) )\n v15->m128i_i64[0] = _mm_shuffle_epi32(v16, 225).m128i_u64[0];\n v15 = (__m128i *)((char *)v15 + 4);\n }\n while ( v15 != (__m128i *)((char *)v9->m128i_i64 + 4 * (unsigned int)(i - 2) + 4) );\n }\n }\n }\n *a5 = v12;\n return v9;\n}", + "ida_strip_asm": "sub_1410:\nendbr64\npush r15\nmovsxd r10, esi\npush r14\nlea r14, ds:0[r10*4]\nmov r15, r10\npush r13\nmov r13d, ecx\npush r12\nmov r12, rdx\npush rbp\nmov rbp, r8\npush rbx\nmov rbx, rdi\nmov rdi, r14; size\nsub rsp, 8\ncall _malloc\nmov r8, rax\ntest r15d, r15d\njle loc_1550\nmovsxd rax, r13d\nmov rsi, rbx\nlea r10, [rbx+r14]\nxor r9d, r9d\nlea rdi, [r12+rax*4]\nnop dword ptr [rax+00000000h]\nloc_1468:\nmovsxd rax, r9d\nlea rcx, [r8+rax*4]\ntest r9d, r9d\njle loc_1508\nloc_1478:\nmov edx, [rsi]\nmov rax, r8\njmp short loc_1489\nloc_1480:\nadd rax, 4\ncmp rax, rcx\njz short loc_1508\nloc_1489:\ncmp [rax], edx\njnz short loc_1480\nadd rsi, 4\ncmp rsi, r10\njnz short loc_1478\nloc_1496:\ncmp r9d, 1\njle short loc_14EF\nmov edi, r9d\nlea r10, [r8+4]\nnop dword ptr [rax+rax+00h]\nloc_14A8:\ncmp edi, 1\njle loc_1548\nlea edx, [rdi-2]\nmov rax, r8\nlea rsi, [r10+rdx*4]\nnop dword ptr [rax+rax+00h]\nloc_14C0:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd ecx, xmm0\nmovd edx, xmm1\ncmp ecx, edx\njle short loc_14DE\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_14DE:\nadd rax, 4\ncmp rax, rsi\njnz short loc_14C0\nsub edi, 1\ncmp edi, 1\njnz short loc_14A8\nloc_14EF:\nmov [rbp+0], r9d\nadd rsp, 8\nmov rax, r8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1508:\ntest r13d, r13d\njle short loc_1530\nmov edx, [rsi]\nmov rax, r12\njmp short loc_1521\nloc_1518:\nadd rax, 4\ncmp rax, rdi\njz short loc_1530\nloc_1521:\ncmp edx, [rax]\njnz short loc_1518\nmovsxd rax, r9d\nadd r9d, 1\nmov [r8+rax*4], edx\nloc_1530:\nadd rsi, 4\ncmp rsi, r10\njnz loc_1468\njmp loc_1496\nloc_1548:\nsub edi, 1\njmp loc_14A8\nloc_1550:\nxor r9d, r9d\njmp short loc_14EF", + "ida_strip_pseudo": "__m128i *__fastcall sub_1410(__int32 *a1, int a2, _DWORD *a3, int a4, int *a5)\n{\n size_t v5; // r14\n __m128i *v9; // r8\n __int32 *v10; // rsi\n __int32 *v11; // r10\n int v12; // r9d\n __m128i *v13; // rax\n int i; // edi\n __m128i *v15; // rax\n __m128i v16; // xmm0\n __int32 v18; // edx\n _DWORD *v19; // rax\n __int64 v20; // rax\n\n v5 = a2;\n v9 = (__m128i *)malloc(v5 * 4);\n if ( a2 <= 0 )\n {\n v12 = 0;\n }\n else\n {\n v10 = a1;\n v11 = &a1[v5];\n v12 = 0;\n while ( v12 <= 0 )\n {\nLABEL_17:\n if ( a4 > 0 )\n {\n v18 = *v10;\n v19 = a3;\n while ( v18 != *v19 )\n {\n if ( ++v19 == &a3[a4] )\n goto LABEL_22;\n }\n v20 = v12++;\n v9->m128i_i32[v20] = v18;\n }\nLABEL_22:\n if ( ++v10 == v11 )\n goto LABEL_8;\n }\n do\n {\n v13 = v9;\n while ( v13->m128i_i32[0] != *v10 )\n {\n v13 = (__m128i *)((char *)v13 + 4);\n if ( v13 == (__m128i *)((char *)v9 + 4 * v12) )\n goto LABEL_17;\n }\n ++v10;\n }\n while ( v10 != v11 );\nLABEL_8:\n if ( v12 > 1 )\n {\n for ( i = v12; i != 1; --i )\n {\n while ( i <= 1 )\n --i;\n v15 = v9;\n do\n {\n v16 = _mm_loadl_epi64(v15);\n if ( _mm_cvtsi128_si32(v16) > _mm_cvtsi128_si32(_mm_shuffle_epi32(v16, 229)) )\n v15->m128i_i64[0] = _mm_shuffle_epi32(v16, 225).m128i_u64[0];\n v15 = (__m128i *)((char *)v15 + 4);\n }\n while ( v15 != (__m128i *)((char *)v9->m128i_i64 + 4 * (unsigned int)(i - 2) + 4) );\n }\n }\n }\n *a5 = v12;\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__m128i *sub_1410(int *a1, int a2, uint32_t *a3, int a4, int *a5) {\n unsigned int v5;\n __m128i *v9;\n int *v10;\n int *v11;\n int v12;\n __m128i *v13;\n int i;\n __m128i *v15;\n __m128i v16;\n int v18;\n uint32_t *v19;\n long long v20;\n v5 = a2;\n v9 = (__m128i *)malloc(v5 * 4);\n if (a2 <= 0) {\n v12 = 0;\n } else {\n v10 = a1;\n v11 = &a1[v5];\n v12 = 0;\n while (v12 <= 0) {\n LABEL_17:\n if (a4 > 0) {\n v18 = *v10;\n v19 = a3;\n while (v18 != *v19) {\n if (++v19 == &a3[a4]) goto LABEL_22;\n }\n v20 = v12++;\n v9->m128i_i32[v20] = v18;\n }\n LABEL_22:\n if (++v10 == v11) goto LABEL_8;\n }\n do {\n v13 = v9;\n while (v13->m128i_i32[0] != *v10) {\n v13 = (__m128i *)((char *)v13 + 4);\n if (v13 == (__m128i *)((char *)v9 + 4 * v12)) goto LABEL_17;\n }\n ++v10;\n } while (v10 != v11);\n LABEL_8:\n if (v12 > 1) {\n for (i = v12; i != 1; --i) {\n while (i <= 1) --i;\n v15 = v9;\n do {\n v16 = _mm_loadl_epi64(v15);\n if (_mm_cvtsi128_si32(v16) >\n _mm_cvtsi128_si32(_mm_shuffle_epi32(v16, 229)))\n v15->m128i_i64[0] = _mm_shuffle_epi32(v16, 225).m128i_u64[0];\n v15 = (__m128i *)((char *)v15 + 4);\n } while (v15 != (__m128i *)((char *)v9->m128i_i64 +\n 4 * (unsigned int)(i - 2) + 4));\n }\n }\n }\n *a5 = v12;\n return v9;\n}", + "ida_pseudo_norm": "__m128i *func0(int *a1, int a2, uint32_t *a3, int a4, int *a5) {\n unsigned int v5;\n __m128i *v9;\n int *v10;\n int *v11;\n int v12;\n __m128i *v13;\n int i;\n __m128i *v15;\n __m128i v16;\n int v18;\n uint32_t *v19;\n long long v20;\n v5 = a2;\n v9 = (__m128i *)malloc(v5 * 4);\n if (a2 <= 0) {\n v12 = 0;\n } else {\n v10 = a1;\n v11 = &a1[v5];\n v12 = 0;\n while (v12 <= 0) {\n LABEL_17:\n if (a4 > 0) {\n v18 = *v10;\n v19 = a3;\n while (v18 != *v19) {\n if (++v19 == &a3[a4]) goto LABEL_22;\n }\n v20 = v12++;\n v9->m128i_i32[v20] = v18;\n }\n LABEL_22:\n if (++v10 == v11) goto LABEL_8;\n }\n do {\n v13 = v9;\n while (v13->m128i_i32[0] != *v10) {\n v13 = (__m128i *)((char *)v13 + 4);\n if (v13 == (__m128i *)((char *)v9 + 4 * v12)) goto LABEL_17;\n }\n ++v10;\n } while (v10 != v11);\n LABEL_8:\n if (v12 > 1) {\n for (i = v12; i != 1; --i) {\n while (i <= 1) --i;\n v15 = v9;\n do {\n v16 = _mm_loadl_epi64(v15);\n if (_mm_cvtsi128_si32(v16) >\n _mm_cvtsi128_si32(_mm_shuffle_epi32(v16, 229)))\n v15->m128i_i64[0] = _mm_shuffle_epi32(v16, 225).m128i_u64[0];\n v15 = (__m128i *)((char *)v15 + 4);\n } while (v15 != (__m128i *)((char *)v9->m128i_i64 +\n 4 * (unsigned int)(i - 2) + 4));\n }\n }\n }\n *a5 = v12;\n return v9;\n}" + }, + { + "index": "HumanEval-C-59", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int n) {\n for (int i = 2; i * i <= n; i++)\n while (n % i == 0 && n > i) n = n / i;\n return n;\n}", + "test": "#include \n\nint main() {\n assert(func0(15) == 5);\n assert(func0(27) == 3);\n assert(func0(63) == 7);\n assert(func0(330) == 11);\n assert(func0(13195) == 29);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_4], 2\njmp short loc_1180\nloc_115D:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\nmov [rbp+var_14], eax\nloc_1167:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njnz short loc_117C\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_4]\njg short loc_115D\nloc_117C:\nadd [rbp+var_4], 1\nloc_1180:\nmov eax, [rbp+var_4]\nimul eax, eax\ncmp [rbp+var_14], eax\njge short loc_1167\nmov eax, [rbp+var_14]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int i; // [rsp+10h] [rbp-4h]\n\n for ( i = 2; a1 >= i * i; ++i )\n {\n while ( !(a1 % i) && a1 > i )\n a1 /= i;\n }\n return (unsigned int)a1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_4], 2\njmp short loc_1180\nloc_115D:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\nmov [rbp+var_14], eax\nloc_1167:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njnz short loc_117C\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_4]\njg short loc_115D\nloc_117C:\nadd [rbp+var_4], 1\nloc_1180:\nmov eax, [rbp+var_4]\nimul eax, eax\ncmp [rbp+var_14], eax\njge short loc_1167\nmov eax, [rbp+var_14]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int i; // [rsp+10h] [rbp-4h]\n\n for ( i = 2; a1 >= i * i; ++i )\n {\n while ( !(a1 % i) && a1 > i )\n a1 /= i;\n }\n return (unsigned int)a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int i;\n for (i = 2; a1 >= i * i; ++i) {\n while (!(a1 % i) && a1 > i) a1 /= i;\n }\n return (unsigned int)a1;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int i;\n for (i = 2; a1 >= i * i; ++i) {\n while (!(a1 % i) && a1 > i) a1 /= i;\n }\n return (unsigned int)a1;\n}" + }, + { + "index": "HumanEval-C-59", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int n) {\n for (int i = 2; i * i <= n; i++)\n while (n % i == 0 && n > i) n = n / i;\n return n;\n}", + "test": "#include \n\nint main() {\n assert(func0(15) == 5);\n assert(func0(27) == 3);\n assert(func0(63) == 7);\n assert(func0(330) == 11);\n assert(func0(13195) == 29);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmov ecx, 2\ncmp edi, 3\njg short loc_1166\nloc_1157:\nmov eax, edi\nretn\nloc_115A:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, edi\njg short loc_1157\nloc_1166:\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_115A\ncmp edi, ecx\njle short loc_115A\nloc_1173:\nmov eax, edi\ncdq\nidiv ecx\nmov esi, eax\nmov edi, eax\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_115A\ncmp esi, ecx\njg short loc_1173\njmp short loc_115A", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // ecx\n int v3; // esi\n\n v1 = 2;\n if ( a1 > 3 )\n {\n do\n {\n if ( !(a1 % v1) && a1 > v1 )\n {\n do\n {\n v3 = a1 / v1;\n a1 = v3;\n }\n while ( !(v3 % v1) && v3 > v1 );\n }\n ++v1;\n }\n while ( v1 * v1 <= a1 );\n }\n return (unsigned int)a1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmov ecx, 2\ncmp edi, 3\njg short loc_1166\nloc_1157:\nmov eax, edi\nretn\nloc_115A:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, edi\njg short loc_1157\nloc_1166:\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_115A\ncmp edi, ecx\njle short loc_115A\nloc_1173:\nmov eax, edi\ncdq\nidiv ecx\nmov esi, eax\nmov edi, eax\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_115A\ncmp esi, ecx\njg short loc_1173\njmp short loc_115A", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v1; // ecx\n int v3; // esi\n\n v1 = 2;\n if ( a1 > 3 )\n {\n do\n {\n if ( !(a1 % v1) && a1 > v1 )\n {\n do\n {\n v3 = a1 / v1;\n a1 = v3;\n }\n while ( !(v3 % v1) && v3 > v1 );\n }\n ++v1;\n }\n while ( v1 * v1 <= a1 );\n }\n return (unsigned int)a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v1;\n int v3;\n v1 = 2;\n if (a1 > 3) {\n do {\n if (!(a1 % v1) && a1 > v1) {\n do {\n v3 = a1 / v1;\n a1 = v3;\n } while (!(v3 % v1) && v3 > v1);\n }\n ++v1;\n } while (v1 * v1 <= a1);\n }\n return (unsigned int)a1;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v3;\n v1 = 2;\n if (a1 > 3) {\n do {\n if (!(a1 % v1) && a1 > v1) {\n do {\n v3 = a1 / v1;\n a1 = v3;\n } while (!(v3 % v1) && v3 > v1);\n }\n ++v1;\n } while (v1 * v1 <= a1);\n }\n return (unsigned int)a1;\n}" + }, + { + "index": "HumanEval-C-59", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int n) {\n for (int i = 2; i * i <= n; i++)\n while (n % i == 0 && n > i) n = n / i;\n return n;\n}", + "test": "#include \n\nint main() {\n assert(func0(15) == 5);\n assert(func0(27) == 3);\n assert(func0(63) == 7);\n assert(func0(330) == 11);\n assert(func0(13195) == 29);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmov ecx, 2\ncmp edi, 3\njle short loc_128E\nxchg ax, ax\nloc_1260:\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njz short loc_127E\njmp short loc_1282\nloc_1270:\nmov eax, edi\ncdq\nidiv ecx\ncdq\nmov edi, eax\nidiv ecx\ntest edx, edx\njnz short loc_1282\nloc_127E:\ncmp edi, ecx\njg short loc_1270\nloc_1282:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, edi\njle short loc_1260\nloc_128E:\nmov eax, edi\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // ecx\n int v2; // edx\n\n v1 = 2;\n if ( a1 > 3 )\n {\n do\n {\n if ( !(a1 % v1) )\n {\n do\n {\n if ( a1 <= v1 )\n break;\n v2 = (a1 / v1) >> 31;\n a1 /= v1;\n }\n while ( !(unsigned int)(__SPAIR64__(v2, a1) % v1) );\n }\n ++v1;\n }\n while ( v1 * v1 <= a1 );\n }\n return (unsigned int)a1;\n}", + "ida_strip_asm": "sub_1250:\nendbr64\nmov ecx, 2\ncmp edi, 3\njle short loc_128E\nxchg ax, ax\nloc_1260:\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njz short loc_127E\njmp short loc_1282\nloc_1270:\nmov eax, edi\ncdq\nidiv ecx\ncdq\nmov edi, eax\nidiv ecx\ntest edx, edx\njnz short loc_1282\nloc_127E:\ncmp edi, ecx\njg short loc_1270\nloc_1282:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, edi\njle short loc_1260\nloc_128E:\nmov eax, edi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1250(int a1)\n{\n int v1; // ecx\n int v2; // edx\n\n v1 = 2;\n if ( a1 > 3 )\n {\n do\n {\n if ( !(a1 % v1) )\n {\n do\n {\n if ( a1 <= v1 )\n break;\n v2 = (a1 / v1) >> 31;\n a1 /= v1;\n }\n while ( !(unsigned int)(__SPAIR64__(v2, a1) % v1) );\n }\n ++v1;\n }\n while ( v1 * v1 <= a1 );\n }\n return (unsigned int)a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1250(int a1) {\n int v1;\n int v2;\n v1 = 2;\n if (a1 > 3) {\n do {\n if (!(a1 % v1)) {\n do {\n if (a1 <= v1) break;\n v2 = (a1 / v1) >> 31;\n a1 /= v1;\n } while (!(unsigned int)(__SPAIR64__(v2, a1) % v1));\n }\n ++v1;\n } while (v1 * v1 <= a1);\n }\n return (unsigned int)a1;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v2;\n v1 = 2;\n if (a1 > 3) {\n do {\n if (!(a1 % v1)) {\n do {\n if (a1 <= v1) break;\n v2 = (a1 / v1) >> 31;\n a1 /= v1;\n } while (!(unsigned int)(__SPAIR64__(v2, a1) % v1));\n }\n ++v1;\n } while (v1 * v1 <= a1);\n }\n return (unsigned int)a1;\n}" + }, + { + "index": "HumanEval-C-60", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int n) { return n * (n + 1) / 2; }", + "test": "#include \n\nint main() {\n assert(func0(1) == 1);\n assert(func0(6) == 21);\n assert(func0(11) == 66);\n assert(func0(30) == 465);\n assert(func0(100) == 5050);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov eax, [rbp+var_4]\nadd eax, 1\nimul eax, [rbp+var_4]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n return (unsigned int)(a1 * (a1 + 1) / 2);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov eax, [rbp+var_4]\nadd eax, 1\nimul eax, [rbp+var_4]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n return (unsigned int)(a1 * (a1 + 1) / 2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) { return (unsigned int)(a1 * (a1 + 1) / 2); }", + "ida_pseudo_norm": "long long func0(int a1) { return (unsigned int)(a1 * (a1 + 1) / 2); }" + }, + { + "index": "HumanEval-C-61", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "bool func0(const char *brackets) {\n int level = 0;\n for (int i = 0; i < strlen(brackets); i++) {\n if (brackets[i] == '(') level += 1;\n if (brackets[i] == ')') level -= 1;\n if (level < 0) return false;\n }\n return level == 0;\n}", + "test": "#include \n#include \n\nint main() {\n assert(func0(\"()\"));\n assert(func0(\"(()())\"));\n assert(func0(\"()()(()())()\"));\n assert(func0(\"()()((()()())())(()()(()))\"));\n assert(!func0(\"((()())))\"));\n assert(!func0(\")(()\"));\n assert(!func0(\"(\"));\n assert(!func0(\"((((\"));\n assert(!func0(\")\"));\n assert(!func0(\"(()\"));\n assert(!func0(\"()()(()())())(()\"));\n assert(!func0(\"()()(()())()))()\"));\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+s], rdi\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp short loc_11CB\nloc_118A:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 28h ; '('\njnz short loc_11A2\nadd [rbp+var_18], 1\nloc_11A2:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 29h ; ')'\njnz short loc_11BA\nsub [rbp+var_18], 1\nloc_11BA:\ncmp [rbp+var_18], 0\njns short loc_11C7\nmov eax, 0\njmp short loc_11E9\nloc_11C7:\nadd [rbp+var_14], 1\nloc_11CB:\nmov eax, [rbp+var_14]\nmovsxd rbx, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rbx, rax\njb short loc_118A\ncmp [rbp+var_18], 0\nsetz al\nloc_11E9:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "bool __fastcall func0(const char *a1)\n{\n int v2; // [rsp+18h] [rbp-18h]\n int i; // [rsp+1Ch] [rbp-14h]\n\n v2 = 0;\n for ( i = 0; i < strlen(a1); ++i )\n {\n if ( a1[i] == 40 )\n ++v2;\n if ( a1[i] == 41 )\n --v2;\n if ( v2 < 0 )\n return 0;\n }\n return v2 == 0;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+s], rdi\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp short loc_11CB\nloc_118A:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 28h ; '('\njnz short loc_11A2\nadd [rbp+var_18], 1\nloc_11A2:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 29h ; ')'\njnz short loc_11BA\nsub [rbp+var_18], 1\nloc_11BA:\ncmp [rbp+var_18], 0\njns short loc_11C7\nmov eax, 0\njmp short loc_11E9\nloc_11C7:\nadd [rbp+var_14], 1\nloc_11CB:\nmov eax, [rbp+var_14]\nmovsxd rbx, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rbx, rax\njb short loc_118A\ncmp [rbp+var_18], 0\nsetz al\nloc_11E9:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "bool __fastcall sub_1169(const char *a1)\n{\n int v2; // [rsp+18h] [rbp-18h]\n int i; // [rsp+1Ch] [rbp-14h]\n\n v2 = 0;\n for ( i = 0; i < strlen(a1); ++i )\n {\n if ( a1[i] == 40 )\n ++v2;\n if ( a1[i] == 41 )\n --v2;\n if ( v2 < 0 )\n return 0;\n }\n return v2 == 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_1169(const char *a1) {\n int v2;\n int i;\n v2 = 0;\n for (i = 0; i < strlen(a1); ++i) {\n if (a1[i] == 40) ++v2;\n if (a1[i] == 41) --v2;\n if (v2 < 0) return 0;\n }\n return v2 == 0;\n}", + "ida_pseudo_norm": "bool func0(const char *a1) {\n int v2;\n int i;\n v2 = 0;\n for (i = 0; i < strlen(a1); ++i) {\n if (a1[i] == 40) ++v2;\n if (a1[i] == 41) --v2;\n if (v2 < 0) return 0;\n }\n return v2 == 0;\n}" + }, + { + "index": "HumanEval-C-61", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "bool func0(const char *brackets) {\n int level = 0;\n for (int i = 0; i < strlen(brackets); i++) {\n if (brackets[i] == '(') level += 1;\n if (brackets[i] == ')') level -= 1;\n if (level < 0) return false;\n }\n return level == 0;\n}", + "test": "#include \n#include \n\nint main() {\n assert(func0(\"()\"));\n assert(func0(\"(()())\"));\n assert(func0(\"()()(()())()\"));\n assert(func0(\"()()((()()())())(()()(()))\"));\n assert(!func0(\"((()())))\"));\n assert(!func0(\")(()\"));\n assert(!func0(\"(\"));\n assert(!func0(\"((((\"));\n assert(!func0(\")\"));\n assert(!func0(\"(()\"));\n assert(!func0(\"()()(()())())(()\"));\n assert(!func0(\"()()(()())()))()\"));\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmov rdi, rax\nmov rax, rbx\nadd rdi, rbx\nmov ecx, 0\njmp short loc_118D\nloc_1186:\nadd ecx, 1\nloc_1189:\nadd rax, 1\nloc_118D:\ncmp rax, rdi\njz short loc_11AB\nmovzx edx, byte ptr [rax]\ncmp dl, 28h ; '('\njz short loc_1186\ncmp dl, 29h ; ')'\njnz short loc_1189\nsub ecx, 1\njns short loc_1189\nmov eax, 0\njmp short loc_11B0\nloc_11AB:\ntest ecx, ecx\nsetz al\nloc_11B0:\npop rbx\nretn", + "ida_pseudo": "bool __fastcall func0(const char *a1)\n{\n size_t v2; // rdi\n const char *v3; // rax\n const char *v4; // rdi\n int v5; // ecx\n\n v2 = strlen(a1);\n v3 = a1;\n v4 = &a1[v2];\n v5 = 0;\n while ( v3 != v4 )\n {\n if ( *v3 == 40 )\n {\n ++v5;\n }\n else if ( *v3 == 41 && --v5 < 0 )\n {\n return 0;\n }\n ++v3;\n }\n return v5 == 0;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmov rdi, rax\nmov rax, rbx\nadd rdi, rbx\nmov ecx, 0\njmp short loc_118D\nloc_1186:\nadd ecx, 1\nloc_1189:\nadd rax, 1\nloc_118D:\ncmp rax, rdi\njz short loc_11AB\nmovzx edx, byte ptr [rax]\ncmp dl, 28h ; '('\njz short loc_1186\ncmp dl, 29h ; ')'\njnz short loc_1189\nsub ecx, 1\njns short loc_1189\nmov eax, 0\njmp short loc_11B0\nloc_11AB:\ntest ecx, ecx\nsetz al\nloc_11B0:\npop rbx\nretn", + "ida_strip_pseudo": "bool __fastcall sub_1169(const char *a1)\n{\n size_t v2; // rdi\n const char *v3; // rax\n const char *v4; // rdi\n int v5; // ecx\n\n v2 = strlen(a1);\n v3 = a1;\n v4 = &a1[v2];\n v5 = 0;\n while ( v3 != v4 )\n {\n if ( *v3 == 40 )\n {\n ++v5;\n }\n else if ( *v3 == 41 && --v5 < 0 )\n {\n return 0;\n }\n ++v3;\n }\n return v5 == 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_1169(const char *a1) {\n unsigned int v2;\n const char *v3;\n const char *v4;\n int v5;\n v2 = strlen(a1);\n v3 = a1;\n v4 = &a1[v2];\n v5 = 0;\n while (v3 != v4) {\n if (*v3 == 40) {\n ++v5;\n } else if (*v3 == 41 && --v5 < 0) {\n return 0;\n }\n ++v3;\n }\n return v5 == 0;\n}", + "ida_pseudo_norm": "bool func0(const char *a1) {\n unsigned int v2;\n const char *v3;\n const char *v4;\n int v5;\n v2 = strlen(a1);\n v3 = a1;\n v4 = &a1[v2];\n v5 = 0;\n while (v3 != v4) {\n if (*v3 == 40) {\n ++v5;\n } else if (*v3 == 41 && --v5 < 0) {\n return 0;\n }\n ++v3;\n }\n return v5 == 0;\n}" + }, + { + "index": "HumanEval-C-61", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "bool func0(const char *brackets) {\n int level = 0;\n for (int i = 0; i < strlen(brackets); i++) {\n if (brackets[i] == '(') level += 1;\n if (brackets[i] == ')') level -= 1;\n if (level < 0) return false;\n }\n return level == 0;\n}", + "test": "#include \n#include \n\nint main() {\n assert(func0(\"()\"));\n assert(func0(\"(()())\"));\n assert(func0(\"()()(()())()\"));\n assert(func0(\"()()((()()())())(()()(()))\"));\n assert(!func0(\"((()())))\"));\n assert(!func0(\")(()\"));\n assert(!func0(\"(\"));\n assert(!func0(\"((((\"));\n assert(!func0(\")\"));\n assert(!func0(\"(()\"));\n assert(!func0(\"()()(()())())(()\"));\n assert(!func0(\"()()(()())()))()\"));\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmov rdi, rbx\nxor ecx, ecx\nadd rax, rbx\njmp short loc_140E\nloc_1400:\ncmp dl, 29h ; ')'\njnz short loc_140A\nsub ecx, 1\njb short loc_1420\nloc_140A:\nadd rdi, 1\nloc_140E:\ncmp rdi, rax\njz short loc_1428\nmovzx edx, byte ptr [rdi]\ncmp dl, 28h ; '('\njnz short loc_1400\nadd ecx, 1\njmp short loc_140A\nloc_1420:\nxor eax, eax\npop rbx\nretn\nloc_1428:\ntest ecx, ecx\npop rbx\nsetz al\nretn", + "ida_pseudo": "bool __fastcall func0(const char *a1)\n{\n size_t v1; // rax\n int v2; // ecx\n const char *v3; // rax\n\n v1 = strlen(a1);\n v2 = 0;\n v3 = &a1[v1];\n while ( a1 != v3 )\n {\n if ( *a1 == 40 )\n {\n ++v2;\n }\n else if ( *a1 == 41 && v2-- == 0 )\n {\n return 0;\n }\n ++a1;\n }\n return v2 == 0;\n}", + "ida_strip_asm": "sub_13E0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmov rdi, rbx\nxor ecx, ecx\nadd rax, rbx\njmp short loc_140E\nloc_1400:\ncmp dl, 29h ; ')'\njnz short loc_140A\nsub ecx, 1\njb short loc_1420\nloc_140A:\nadd rdi, 1\nloc_140E:\ncmp rdi, rax\njz short loc_1428\nmovzx edx, byte ptr [rdi]\ncmp dl, 28h ; '('\njnz short loc_1400\nadd ecx, 1\njmp short loc_140A\nloc_1420:\nxor eax, eax\npop rbx\nretn\nloc_1428:\ntest ecx, ecx\npop rbx\nsetz al\nretn", + "ida_strip_pseudo": "bool __fastcall sub_13E0(const char *a1)\n{\n size_t v1; // rax\n int v2; // ecx\n const char *v3; // rax\n\n v1 = strlen(a1);\n v2 = 0;\n v3 = &a1[v1];\n while ( a1 != v3 )\n {\n if ( *a1 == 40 )\n {\n ++v2;\n }\n else if ( *a1 == 41 && v2-- == 0 )\n {\n return 0;\n }\n ++a1;\n }\n return v2 == 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_13E0(const char *a1) {\n unsigned int v1;\n int v2;\n const char *v3;\n v1 = strlen(a1);\n v2 = 0;\n v3 = &a1[v1];\n while (a1 != v3) {\n if (*a1 == 40) {\n ++v2;\n } else if (*a1 == 41 && v2-- == 0) {\n return 0;\n }\n ++a1;\n }\n return v2 == 0;\n}", + "ida_pseudo_norm": "bool func0(const char *a1) {\n unsigned int v1;\n int v2;\n const char *v3;\n v1 = strlen(a1);\n v2 = 0;\n v3 = &a1[v1];\n while (a1 != v3) {\n if (*a1 == 40) {\n ++v2;\n } else if (*a1 == 41 && v2-- == 0) {\n return 0;\n }\n ++a1;\n }\n return v2 == 0;\n}" + }, + { + "index": "HumanEval-C-61", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "bool func0(const char *brackets) {\n int level = 0;\n for (int i = 0; i < strlen(brackets); i++) {\n if (brackets[i] == '(') level += 1;\n if (brackets[i] == ')') level -= 1;\n if (level < 0) return false;\n }\n return level == 0;\n}", + "test": "#include \n#include \n\nint main() {\n assert(func0(\"()\"));\n assert(func0(\"(()())\"));\n assert(func0(\"()()(()())()\"));\n assert(func0(\"()()((()()())())(()()(()))\"));\n assert(!func0(\"((()())))\"));\n assert(!func0(\")(()\"));\n assert(!func0(\"(\"));\n assert(!func0(\"((((\"));\n assert(!func0(\")\"));\n assert(!func0(\"(()\"));\n assert(!func0(\"()()(()())())(()\"));\n assert(!func0(\"()()(()())()))()\"));\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmov rdi, rbx\nxor ecx, ecx\nadd rax, rbx\njmp short loc_140E\nloc_1400:\ncmp dl, 29h ; ')'\njnz short loc_140A\nsub ecx, 1\njb short loc_1420\nloc_140A:\nadd rdi, 1\nloc_140E:\ncmp rdi, rax\njz short loc_1428\nmovzx edx, byte ptr [rdi]\ncmp dl, 28h ; '('\njnz short loc_1400\nadd ecx, 1\njmp short loc_140A\nloc_1420:\nxor eax, eax\npop rbx\nretn\nloc_1428:\ntest ecx, ecx\npop rbx\nsetz al\nretn", + "ida_pseudo": "bool __fastcall func0(const char *a1)\n{\n size_t v1; // rax\n int v2; // ecx\n const char *v3; // rax\n\n v1 = strlen(a1);\n v2 = 0;\n v3 = &a1[v1];\n while ( a1 != v3 )\n {\n if ( *a1 == 40 )\n {\n ++v2;\n }\n else if ( *a1 == 41 && v2-- == 0 )\n {\n return 0;\n }\n ++a1;\n }\n return v2 == 0;\n}", + "ida_strip_asm": "sub_13E0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmov rdi, rbx\nxor ecx, ecx\nadd rax, rbx\njmp short loc_140E\nloc_1400:\ncmp dl, 29h ; ')'\njnz short loc_140A\nsub ecx, 1\njb short loc_1420\nloc_140A:\nadd rdi, 1\nloc_140E:\ncmp rdi, rax\njz short loc_1428\nmovzx edx, byte ptr [rdi]\ncmp dl, 28h ; '('\njnz short loc_1400\nadd ecx, 1\njmp short loc_140A\nloc_1420:\nxor eax, eax\npop rbx\nretn\nloc_1428:\ntest ecx, ecx\npop rbx\nsetz al\nretn", + "ida_strip_pseudo": "bool __fastcall sub_13E0(const char *a1)\n{\n size_t v1; // rax\n int v2; // ecx\n const char *v3; // rax\n\n v1 = strlen(a1);\n v2 = 0;\n v3 = &a1[v1];\n while ( a1 != v3 )\n {\n if ( *a1 == 40 )\n {\n ++v2;\n }\n else if ( *a1 == 41 && v2-- == 0 )\n {\n return 0;\n }\n ++a1;\n }\n return v2 == 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_13E0(const char *a1) {\n unsigned int v1;\n int v2;\n const char *v3;\n v1 = strlen(a1);\n v2 = 0;\n v3 = &a1[v1];\n while (a1 != v3) {\n if (*a1 == 40) {\n ++v2;\n } else if (*a1 == 41 && v2-- == 0) {\n return 0;\n }\n ++a1;\n }\n return v2 == 0;\n}", + "ida_pseudo_norm": "bool func0(const char *a1) {\n unsigned int v1;\n int v2;\n const char *v3;\n v1 = strlen(a1);\n v2 = 0;\n v3 = &a1[v1];\n while (a1 != v3) {\n if (*a1 == 40) {\n ++v2;\n } else if (*a1 == 41 && v2-- == 0) {\n return 0;\n }\n ++a1;\n }\n return v2 == 0;\n}" + }, + { + "index": "HumanEval-C-62", + "func_name": "func0", + "func_dep": "#include \n", + "func": "void func0(const float *xs, int xs_size, float *out) {\n for (int i = 1; i < xs_size; i++) {\n out[i - 1] = i * xs[i];\n }\n}", + "test": "#include \n#include \n#include \n#include \n\nbool issame(const float *a, int a_size, const float *b, int b_size) {\n if (a_size != b_size) return false;\n for (int i = 0; i < a_size; i++) {\n if (fabs(a[i] - b[i]) > 1e-4) return false;\n }\n return true;\n}\n\nint main() {\n float result[4];\n\n float case1[] = {3, 1, 2, 4, 5};\n float expected1[] = {1, 4, 12, 20};\n func0(case1, 5, result);\n assert(issame(result, 4, expected1, 4));\n\n float case2[] = {1, 2, 3};\n float expected2[] = {2, 6};\n func0(case2, 3, result);\n assert(issame(result, 2, expected2, 2));\n\n float case3[] = {3, 2, 1};\n float expected3[] = {2, 2};\n func0(case3, 3, result);\n assert(issame(result, 2, expected3, 2));\n\n float case4[] = {3, 2, 1, 0, 4};\n float expected4[] = {2, 2, 0, 16};\n func0(case4, 5, result);\n assert(issame(result, 4, expected4, 4));\n\n float case5[] = {1};\n func0(case5, 1, result);\n assert(issame(result, 0, NULL, 0));\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_4], 1\njmp short loc_11C6\nloc_1185:\npxor xmm1, xmm1\ncvtsi2ss xmm1, [rbp+var_4]\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\nmov eax, [rbp+var_4]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmulss xmm0, xmm1\nmovss dword ptr [rax], xmm0\nadd [rbp+var_4], 1\nloc_11C6:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1185\nnop\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3)\n{\n __int64 result; // rax\n int i; // [rsp+24h] [rbp-4h]\n\n for ( i = 1; ; ++i )\n {\n result = (unsigned int)i;\n if ( i >= a2 )\n break;\n *(float *)(4LL * i - 4 + a3) = *(float *)(4LL * i + a1) * (float)i;\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_4], 1\njmp short loc_11C6\nloc_1185:\npxor xmm1, xmm1\ncvtsi2ss xmm1, [rbp+var_4]\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\nmov eax, [rbp+var_4]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmulss xmm0, xmm1\nmovss dword ptr [rax], xmm0\nadd [rbp+var_4], 1\nloc_11C6:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1185\nnop\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, __int64 a3)\n{\n __int64 result; // rax\n int i; // [rsp+24h] [rbp-4h]\n\n for ( i = 1; ; ++i )\n {\n result = (unsigned int)i;\n if ( i >= a2 )\n break;\n *(float *)(4LL * i - 4 + a3) = *(float *)(4LL * i + a1) * (float)i;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, long long a3) {\n long long result;\n int i;\n for (i = 1;; ++i) {\n result = (unsigned int)i;\n if (i >= a2) break;\n *(float *)(4LL * i - 4 + a3) = *(float *)(4LL * i + a1) * (float)i;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3) {\n long long result;\n int i;\n for (i = 1;; ++i) {\n result = (unsigned int)i;\n if (i >= a2) break;\n *(float *)(4LL * i - 4 + a3) = *(float *)(4LL * i + a1) * (float)i;\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-62", + "func_name": "func0", + "func_dep": "#include \n", + "func": "void func0(const float *xs, int xs_size, float *out) {\n for (int i = 1; i < xs_size; i++) {\n out[i - 1] = i * xs[i];\n }\n}", + "test": "#include \n#include \n#include \n#include \n\nbool issame(const float *a, int a_size, const float *b, int b_size) {\n if (a_size != b_size) return false;\n for (int i = 0; i < a_size; i++) {\n if (fabs(a[i] - b[i]) > 1e-4) return false;\n }\n return true;\n}\n\nint main() {\n float result[4];\n\n float case1[] = {3, 1, 2, 4, 5};\n float expected1[] = {1, 4, 12, 20};\n func0(case1, 5, result);\n assert(issame(result, 4, expected1, 4));\n\n float case2[] = {1, 2, 3};\n float expected2[] = {2, 6};\n func0(case2, 3, result);\n assert(issame(result, 2, expected2, 2));\n\n float case3[] = {3, 2, 1};\n float expected3[] = {2, 2};\n func0(case3, 3, result);\n assert(issame(result, 2, expected3, 2));\n\n float case4[] = {3, 2, 1, 0, 4};\n float expected4[] = {2, 2, 0, 16};\n func0(case4, 5, result);\n assert(issame(result, 4, expected4, 4));\n\n float case5[] = {1};\n func0(case5, 1, result);\n assert(issame(result, 0, NULL, 0));\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ncmp esi, 1\njle short locret_1195\nmov esi, esi\nmov eax, 1\nloc_1179:\npxor xmm0, xmm0\ncvtsi2ss xmm0, eax\nmulss xmm0, dword ptr [rdi+rax*4]\nmovss dword ptr [rdx+rax*4-4], xmm0\nadd rax, 1\ncmp rax, rsi\njnz short loc_1179\nlocret_1195:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2, __int64 a3)\n{\n __int64 i; // rax\n\n if ( a2 > 1 )\n {\n for ( i = 1LL; i != a2; ++i )\n *(float *)(a3 + 4 * i - 4) = (float)(int)i * *(float *)(a1 + 4 * i);\n }\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ncmp esi, 1\njle short locret_1195\nmov esi, esi\nmov eax, 1\nloc_1179:\npxor xmm0, xmm0\ncvtsi2ss xmm0, eax\nmulss xmm0, dword ptr [rdi+rax*4]\nmovss dword ptr [rdx+rax*4-4], xmm0\nadd rax, 1\ncmp rax, rsi\njnz short loc_1179\nlocret_1195:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1169(__int64 a1, int a2, __int64 a3)\n{\n __int64 i; // rax\n\n if ( a2 > 1 )\n {\n for ( i = 1LL; i != a2; ++i )\n *(float *)(a3 + 4 * i - 4) = (float)(int)i * *(float *)(a1 + 4 * i);\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1169(long long a1, int a2, long long a3) {\n long long i;\n if (a2 > 1) {\n for (i = 1LL; i != a2; ++i)\n *(float *)(a3 + 4 * i - 4) = (float)(int)i * *(float *)(a1 + 4 * i);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2, long long a3) {\n long long i;\n if (a2 > 1) {\n for (i = 1LL; i != a2; ++i)\n *(float *)(a3 + 4 * i - 4) = (float)(int)i * *(float *)(a1 + 4 * i);\n }\n}" + }, + { + "index": "HumanEval-C-62", + "func_name": "func0", + "func_dep": "#include \n", + "func": "void func0(const float *xs, int xs_size, float *out) {\n for (int i = 1; i < xs_size; i++) {\n out[i - 1] = i * xs[i];\n }\n}", + "test": "#include \n#include \n#include \n#include \n\nbool issame(const float *a, int a_size, const float *b, int b_size) {\n if (a_size != b_size) return false;\n for (int i = 0; i < a_size; i++) {\n if (fabs(a[i] - b[i]) > 1e-4) return false;\n }\n return true;\n}\n\nint main() {\n float result[4];\n\n float case1[] = {3, 1, 2, 4, 5};\n float expected1[] = {1, 4, 12, 20};\n func0(case1, 5, result);\n assert(issame(result, 4, expected1, 4));\n\n float case2[] = {1, 2, 3};\n float expected2[] = {2, 6};\n func0(case2, 3, result);\n assert(issame(result, 2, expected2, 2));\n\n float case3[] = {3, 2, 1};\n float expected3[] = {2, 2};\n func0(case3, 3, result);\n assert(issame(result, 2, expected3, 2));\n\n float case4[] = {3, 2, 1, 0, 4};\n float expected4[] = {2, 2, 0, 16};\n func0(case4, 5, result);\n assert(issame(result, 4, expected4, 4));\n\n float case5[] = {1};\n func0(case5, 1, result);\n assert(issame(result, 0, NULL, 0));\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ncmp esi, 1\njle short locret_144C\nmov esi, esi\nmov eax, 1\nloc_1430:\npxor xmm0, xmm0\ncvtsi2ss xmm0, eax\nmulss xmm0, dword ptr [rdi+rax*4]\nmovss dword ptr [rdx+rax*4-4], xmm0\nadd rax, 1\ncmp rsi, rax\njnz short loc_1430\nlocret_144C:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2, __int64 a3)\n{\n __int64 i; // rax\n\n if ( a2 > 1 )\n {\n for ( i = 1LL; i != a2; ++i )\n *(float *)(a3 + 4 * i - 4) = (float)(int)i * *(float *)(a1 + 4 * i);\n }\n}", + "ida_strip_asm": "sub_1420:\nendbr64\ncmp esi, 1\njle short locret_144C\nmov esi, esi\nmov eax, 1\nloc_1430:\npxor xmm0, xmm0\ncvtsi2ss xmm0, eax\nmulss xmm0, dword ptr [rdi+rax*4]\nmovss dword ptr [rdx+rax*4-4], xmm0\nadd rax, 1\ncmp rsi, rax\njnz short loc_1430\nlocret_144C:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1420(__int64 a1, int a2, __int64 a3)\n{\n __int64 i; // rax\n\n if ( a2 > 1 )\n {\n for ( i = 1LL; i != a2; ++i )\n *(float *)(a3 + 4 * i - 4) = (float)(int)i * *(float *)(a1 + 4 * i);\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1420(long long a1, int a2, long long a3) {\n long long i;\n if (a2 > 1) {\n for (i = 1LL; i != a2; ++i)\n *(float *)(a3 + 4 * i - 4) = (float)(int)i * *(float *)(a1 + 4 * i);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2, long long a3) {\n long long i;\n if (a2 > 1) {\n for (i = 1LL; i != a2; ++i)\n *(float *)(a3 + 4 * i - 4) = (float)(int)i * *(float *)(a1 + 4 * i);\n }\n}" + }, + { + "index": "HumanEval-C-63", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int n) {\n int ff[100] = {0};\n ff[1] = 0;\n ff[2] = 1;\n for (int i = 3; i <= n; ++i) {\n ff[i] = ff[i - 1] + ff[i - 2] + ff[i - 3];\n }\n return ff[n];\n}", + "test": "#include \n\nint main() {\n assert(func0(2) == 1);\n assert(func0(1) == 0);\n assert(func0(5) == 4);\n assert(func0(8) == 24);\n assert(func0(10) == 81);\n assert(func0(12) == 274);\n assert(func0(14) == 927);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 1C0h\nmov [rbp+var_1B4], edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rdx, [rbp+var_1A0]\nmov eax, 0\nmov ecx, 32h ; '2'\nmov rdi, rdx\nrep stosq\nmov [rbp+var_19C], 0\nmov [rbp+var_198], 1\nmov [rbp+var_1A4], 3\njmp short loc_1214\nloc_11C4:\nmov eax, [rbp+var_1A4]\nsub eax, 1\ncdqe\nmov edx, [rbp+rax*4+var_1A0]\nmov eax, [rbp+var_1A4]\nsub eax, 2\ncdqe\nmov eax, [rbp+rax*4+var_1A0]\nadd edx, eax\nmov eax, [rbp+var_1A4]\nsub eax, 3\ncdqe\nmov eax, [rbp+rax*4+var_1A0]\nadd edx, eax\nmov eax, [rbp+var_1A4]\ncdqe\nmov [rbp+rax*4+var_1A0], edx\nadd [rbp+var_1A4], 1\nloc_1214:\nmov eax, [rbp+var_1A4]\ncmp eax, [rbp+var_1B4]\njle short loc_11C4\nmov eax, [rbp+var_1B4]\ncdqe\nmov eax, [rbp+rax*4+var_1A0]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1245\ncall ___stack_chk_fail\nlocret_1245:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int i; // [rsp+1Ch] [rbp-1A4h]\n _DWORD v3[102]; // [rsp+20h] [rbp-1A0h] BYREF\n unsigned __int64 v4; // [rsp+1B8h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n memset(v3, 0, 0x190uLL);\n v3[1] = 0;\n v3[2] = 1;\n for ( i = 3; i <= a1; ++i )\n v3[i] = v3[i - 3] + v3[i - 2] + v3[i - 1];\n return (unsigned int)v3[a1];\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 1C0h\nmov [rbp+var_1B4], edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rdx, [rbp+var_1A0]\nmov eax, 0\nmov ecx, 32h ; '2'\nmov rdi, rdx\nrep stosq\nmov [rbp+var_19C], 0\nmov [rbp+var_198], 1\nmov [rbp+var_1A4], 3\njmp short loc_1214\nloc_11C4:\nmov eax, [rbp+var_1A4]\nsub eax, 1\ncdqe\nmov edx, [rbp+rax*4+var_1A0]\nmov eax, [rbp+var_1A4]\nsub eax, 2\ncdqe\nmov eax, [rbp+rax*4+var_1A0]\nadd edx, eax\nmov eax, [rbp+var_1A4]\nsub eax, 3\ncdqe\nmov eax, [rbp+rax*4+var_1A0]\nadd edx, eax\nmov eax, [rbp+var_1A4]\ncdqe\nmov [rbp+rax*4+var_1A0], edx\nadd [rbp+var_1A4], 1\nloc_1214:\nmov eax, [rbp+var_1A4]\ncmp eax, [rbp+var_1B4]\njle short loc_11C4\nmov eax, [rbp+var_1B4]\ncdqe\nmov eax, [rbp+rax*4+var_1A0]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1245\ncall ___stack_chk_fail\nlocret_1245:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n int i; // [rsp+1Ch] [rbp-1A4h]\n _DWORD v3[102]; // [rsp+20h] [rbp-1A0h] BYREF\n unsigned __int64 v4; // [rsp+1B8h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n memset(v3, 0, 0x190uLL);\n v3[1] = 0;\n v3[2] = 1;\n for ( i = 3; i <= a1; ++i )\n v3[i] = v3[i - 3] + v3[i - 2] + v3[i - 1];\n return (unsigned int)v3[a1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n int i;\n uint32_t v3[102];\n unsigned long long v4;\n v4 = __readfsqword(40u);\n memset(v3, 0, 400uLL);\n v3[1] = 0;\n v3[2] = 1;\n for (i = 3; i <= a1; ++i) v3[i] = v3[i - 3] + v3[i - 2] + v3[i - 1];\n return (unsigned int)v3[a1];\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int i;\n uint32_t v3[102];\n unsigned long long v4;\n v4 = __readfsqword(40u);\n memset(v3, 0, 400uLL);\n v3[1] = 0;\n v3[2] = 1;\n for (i = 3; i <= a1; ++i) v3[i] = v3[i - 3] + v3[i - 2] + v3[i - 1];\n return (unsigned int)v3[a1];\n}" + }, + { + "index": "HumanEval-C-63", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int n) {\n int ff[100] = {0};\n ff[1] = 0;\n ff[2] = 1;\n for (int i = 3; i <= n; ++i) {\n ff[i] = ff[i - 1] + ff[i - 2] + ff[i - 3];\n }\n return ff[n];\n}", + "test": "#include \n\nint main() {\n assert(func0(2) == 1);\n assert(func0(1) == 0);\n assert(func0(5) == 4);\n assert(func0(8) == 24);\n assert(func0(10) == 81);\n assert(func0(12) == 274);\n assert(func0(14) == 927);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nsub rsp, 1A8h\nmov esi, edi\nmov rax, fs:28h\nmov [rsp+1A8h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nmov ecx, 32h ; '2'\nrep stosq\nmov [rsp+1A8h+var_1A0], 1\ncmp esi, 2\njle short loc_11C0\nmov rax, rsp\nlea edx, [rsi-3]\nlea rcx, [rsp+rdx*4+1A8h+var_1A4]\nloc_11AC:\nmov edx, [rax+4]\nadd edx, [rax+8]\nadd edx, [rax]\nmov [rax+0Ch], edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_11AC\nloc_11C0:\nmovsxd rsi, esi\nmov eax, [rsp+rsi*4+1A8h+var_1A8]\nmov rdx, [rsp+1A8h+var_10]\nsub rdx, fs:28h\njnz short loc_11E1\nadd rsp, 1A8h\nretn\nloc_11E1:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n _DWORD *v1; // rax\n _DWORD v3[102]; // [rsp+0h] [rbp-1A8h] BYREF\n unsigned __int64 v4; // [rsp+198h] [rbp-10h]\n\n v4 = __readfsqword(0x28u);\n memset(v3, 0, 0x190uLL);\n v3[2] = 1;\n if ( a1 > 2 )\n {\n v1 = v3;\n do\n {\n v1[3] = *v1 + v1[2] + v1[1];\n ++v1;\n }\n while ( v1 != &v3[a1 - 3 + 1] );\n }\n return (unsigned int)v3[a1];\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nsub rsp, 1A8h\nmov esi, edi\nmov rax, fs:28h\nmov [rsp+1A8h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nmov ecx, 32h ; '2'\nrep stosq\nmov [rsp+1A8h+var_1A0], 1\ncmp esi, 2\njle short loc_11C0\nmov rax, rsp\nlea edx, [rsi-3]\nlea rcx, [rsp+rdx*4+1A8h+var_1A4]\nloc_11AC:\nmov edx, [rax+4]\nadd edx, [rax+8]\nadd edx, [rax]\nmov [rax+0Ch], edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_11AC\nloc_11C0:\nmovsxd rsi, esi\nmov eax, [rsp+rsi*4+1A8h+var_1A8]\nmov rdx, [rsp+1A8h+var_10]\nsub rdx, fs:28h\njnz short loc_11E1\nadd rsp, 1A8h\nretn\nloc_11E1:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n _DWORD *v1; // rax\n _DWORD v3[102]; // [rsp+0h] [rbp-1A8h] BYREF\n unsigned __int64 v4; // [rsp+198h] [rbp-10h]\n\n v4 = __readfsqword(0x28u);\n memset(v3, 0, 0x190uLL);\n v3[2] = 1;\n if ( a1 > 2 )\n {\n v1 = v3;\n do\n {\n v1[3] = *v1 + v1[2] + v1[1];\n ++v1;\n }\n while ( v1 != &v3[a1 - 3 + 1] );\n }\n return (unsigned int)v3[a1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n uint32_t *v1;\n uint32_t v3[102];\n unsigned long long v4;\n v4 = __readfsqword(40u);\n memset(v3, 0, 400uLL);\n v3[2] = 1;\n if (a1 > 2) {\n v1 = v3;\n do {\n v1[3] = *v1 + v1[2] + v1[1];\n ++v1;\n } while (v1 != &v3[a1 - 3 + 1]);\n }\n return (unsigned int)v3[a1];\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n uint32_t *v1;\n uint32_t v3[102];\n unsigned long long v4;\n v4 = __readfsqword(40u);\n memset(v3, 0, 400uLL);\n v3[2] = 1;\n if (a1 > 2) {\n v1 = v3;\n do {\n v1[3] = *v1 + v1[2] + v1[1];\n ++v1;\n } while (v1 != &v3[a1 - 3 + 1]);\n }\n return (unsigned int)v3[a1];\n}" + }, + { + "index": "HumanEval-C-63", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int n) {\n int ff[100] = {0};\n ff[1] = 0;\n ff[2] = 1;\n for (int i = 3; i <= n; ++i) {\n ff[i] = ff[i - 1] + ff[i - 2] + ff[i - 3];\n }\n return ff[n];\n}", + "test": "#include \n\nint main() {\n assert(func0(2) == 1);\n assert(func0(1) == 0);\n assert(func0(5) == 4);\n assert(func0(8) == 24);\n assert(func0(10) == 81);\n assert(func0(12) == 274);\n assert(func0(14) == 927);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nsub rsp, 1A8h\nmovsxd r9, edi\nmov ecx, 32h ; '2'\nmov rax, fs:28h\nmov [rsp+1A8h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\nmov [rsp+1A8h+var_1A0], 1\ncmp r9d, 2\njle short loc_1347\nlea eax, [r9-3]\nlea rdx, [rsp+1A8h+var_19C]\nxor edi, edi\nlea r8, [rsp+rax*4+1A8h+var_198]\nmov eax, 1\nnop\nloc_1330:\nmov esi, eax\nlea eax, [rax+rcx]\nadd rdx, 4\nadd eax, edi\nmov edi, ecx\nmov ecx, esi\nmov [rdx-4], eax\ncmp rdx, r8\njnz short loc_1330\nloc_1347:\nmov eax, [rsp+r9*4+1A8h+var_1A8]\nmov rdx, [rsp+1A8h+var_10]\nsub rdx, fs:28h\njnz short loc_1366\nadd rsp, 1A8h\nretn\nloc_1366:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n __int64 v1; // r9\n int v2; // ecx\n _DWORD *v3; // rdx\n int v4; // edi\n int v5; // eax\n int v6; // esi\n _DWORD v8[102]; // [rsp+0h] [rbp-1A8h] BYREF\n unsigned __int64 v9; // [rsp+198h] [rbp-10h]\n\n v1 = a1;\n v9 = __readfsqword(0x28u);\n memset(v8, 0, 0x190uLL);\n v2 = 0;\n v8[2] = 1;\n if ( a1 > 2 )\n {\n v3 = &v8[3];\n v4 = 0;\n v5 = 1;\n do\n {\n v6 = v5;\n ++v3;\n v5 += v4 + v2;\n v4 = v2;\n v2 = v6;\n *(v3 - 1) = v5;\n }\n while ( v3 != &v8[(unsigned int)(v1 - 3) + 4] );\n }\n return (unsigned int)v8[v1];\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\nsub rsp, 1A8h\nmovsxd r9, edi\nmov ecx, 32h ; '2'\nmov rax, fs:28h\nmov [rsp+1A8h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\nmov [rsp+1A8h+var_1A0], 1\ncmp r9d, 2\njle short loc_1347\nlea eax, [r9-3]\nlea rdx, [rsp+1A8h+var_19C]\nxor edi, edi\nlea r8, [rsp+rax*4+1A8h+var_198]\nmov eax, 1\nnop\nloc_1330:\nmov esi, eax\nlea eax, [rax+rcx]\nadd rdx, 4\nadd eax, edi\nmov edi, ecx\nmov ecx, esi\nmov [rdx-4], eax\ncmp rdx, r8\njnz short loc_1330\nloc_1347:\nmov eax, [rsp+r9*4+1A8h+var_1A8]\nmov rdx, [rsp+1A8h+var_10]\nsub rdx, fs:28h\njnz short loc_1366\nadd rsp, 1A8h\nretn\nloc_1366:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12E0(int a1)\n{\n __int64 v1; // r9\n int v2; // ecx\n _DWORD *v3; // rdx\n int v4; // edi\n int v5; // eax\n int v6; // esi\n _DWORD v8[102]; // [rsp+0h] [rbp-1A8h] BYREF\n unsigned __int64 v9; // [rsp+198h] [rbp-10h]\n\n v1 = a1;\n v9 = __readfsqword(0x28u);\n memset(v8, 0, 0x190uLL);\n v2 = 0;\n v8[2] = 1;\n if ( a1 > 2 )\n {\n v3 = &v8[3];\n v4 = 0;\n v5 = 1;\n do\n {\n v6 = v5;\n ++v3;\n v5 += v4 + v2;\n v4 = v2;\n v2 = v6;\n *(v3 - 1) = v5;\n }\n while ( v3 != &v8[(unsigned int)(v1 - 3) + 4] );\n }\n return (unsigned int)v8[v1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12E0(int a1) {\n long long v1;\n int v2;\n uint32_t *v3;\n int v4;\n int v5;\n int v6;\n uint32_t v8[102];\n unsigned long long v9;\n v1 = a1;\n v9 = __readfsqword(40u);\n memset(v8, 0, 400uLL);\n v2 = 0;\n v8[2] = 1;\n if (a1 > 2) {\n v3 = &v8[3];\n v4 = 0;\n v5 = 1;\n do {\n v6 = v5;\n ++v3;\n v5 += v4 + v2;\n v4 = v2;\n v2 = v6;\n *(v3 - 1) = v5;\n } while (v3 != &v8[(unsigned int)(v1 - 3) + 4]);\n }\n return (unsigned int)v8[v1];\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n long long v1;\n int v2;\n uint32_t *v3;\n int v4;\n int v5;\n int v6;\n uint32_t v8[102];\n unsigned long long v9;\n v1 = a1;\n v9 = __readfsqword(40u);\n memset(v8, 0, 400uLL);\n v2 = 0;\n v8[2] = 1;\n if (a1 > 2) {\n v3 = &v8[3];\n v4 = 0;\n v5 = 1;\n do {\n v6 = v5;\n ++v3;\n v5 += v4 + v2;\n v4 = v2;\n v2 = v6;\n *(v3 - 1) = v5;\n } while (v3 != &v8[(unsigned int)(v1 - 3) + 4]);\n }\n return (unsigned int)v8[v1];\n}" + }, + { + "index": "HumanEval-C-63", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int n) {\n int ff[100] = {0};\n ff[1] = 0;\n ff[2] = 1;\n for (int i = 3; i <= n; ++i) {\n ff[i] = ff[i - 1] + ff[i - 2] + ff[i - 3];\n }\n return ff[n];\n}", + "test": "#include \n\nint main() {\n assert(func0(2) == 1);\n assert(func0(1) == 0);\n assert(func0(5) == 4);\n assert(func0(8) == 24);\n assert(func0(10) == 81);\n assert(func0(12) == 274);\n assert(func0(14) == 927);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nsub rsp, 1A8h\nmovsxd rsi, edi\nmov ecx, 32h ; '2'\nmov rax, fs:28h\nmov [rsp+1A8h+var_10], rax\nxor eax, eax\nmov r9, rsp\nmov rdi, r9\nrep stosq\nmov [rsp+1A8h+var_1A0], 1\ncmp esi, 2\njle short loc_138F\nlea r11d, [rsi-1]\ncmp esi, 5\njle loc_13AD\nlea r8, [rsp+1A8h+var_19C]\nmov edi, 1\nxor edx, edx\nmov ecx, 3\nloc_133A:\nlea r10d, [rdx+rdi]\nadd r8, 0Ch\nadd eax, r10d\nlea r10d, [rax+rdi]\nmov [r8-0Ch], eax\nadd edx, r10d\nlea r10d, [rax+rdx]\nmov [r8-8], edx\nadd edi, r10d\nmov r10d, ecx\nadd ecx, 3\nadd r10d, 4\nmov [r8-4], edi\ncmp r11d, r10d\njg short loc_133A\nloc_136E:\nmovsxd rax, ecx\nlea rax, [r9+rax*4]\nnop dword ptr [rax]\nloc_1378:\nmov edx, [rax-4]\nadd ecx, 1\nadd edx, [rax-8]\nadd rax, 4\nadd edx, [rax-10h]\nmov [rax-4], edx\ncmp esi, ecx\njge short loc_1378\nloc_138F:\nmov eax, [rsp+rsi*4+1A8h+var_1A8]\nmov rdx, [rsp+1A8h+var_10]\nsub rdx, fs:28h\njnz short loc_13B4\nadd rsp, 1A8h\nretn\nloc_13AD:\nmov ecx, 3\njmp short loc_136E\nloc_13B4:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n __int64 v1; // rsi\n int v2; // eax\n _DWORD *v3; // r8\n int v4; // edi\n int v5; // edx\n int v6; // ecx\n int v7; // r10d\n _DWORD *v8; // rax\n int v9; // edx\n _DWORD v11[102]; // [rsp+0h] [rbp-1A8h] BYREF\n unsigned __int64 v12; // [rsp+198h] [rbp-10h]\n\n v1 = a1;\n v12 = __readfsqword(0x28u);\n v2 = 0;\n memset(v11, 0, 0x190uLL);\n v11[2] = 1;\n if ( a1 > 2 )\n {\n if ( a1 <= 5 )\n {\n v6 = 3;\n }\n else\n {\n v3 = &v11[3];\n v4 = 1;\n v5 = 0;\n v6 = 3;\n do\n {\n v3 += 3;\n v2 += v5 + v4;\n *(v3 - 3) = v2;\n v5 += v2 + v4;\n *(v3 - 2) = v5;\n v4 += v2 + v5;\n v7 = v6;\n v6 += 3;\n *(v3 - 1) = v4;\n }\n while ( (int)v1 - 1 > v7 + 4 );\n }\n v8 = &v11[v6];\n do\n {\n ++v6;\n v9 = *(v8 - 2) + *(v8 - 1);\n ++v8;\n *(v8 - 1) = *(v8 - 4) + v9;\n }\n while ( (int)v1 >= v6 );\n }\n return (unsigned int)v11[v1];\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\nsub rsp, 1A8h\nmovsxd rsi, edi\nmov ecx, 32h ; '2'\nmov rax, fs:28h\nmov [rsp+1A8h+var_10], rax\nxor eax, eax\nmov r9, rsp\nmov rdi, r9\nrep stosq\nmov [rsp+1A8h+var_1A0], 1\ncmp esi, 2\njle short loc_138F\nlea r11d, [rsi-1]\ncmp esi, 5\njle loc_13AD\nlea r8, [rsp+1A8h+var_19C]\nmov edi, 1\nxor edx, edx\nmov ecx, 3\nloc_133A:\nlea r10d, [rdx+rdi]\nadd r8, 0Ch\nadd eax, r10d\nlea r10d, [rax+rdi]\nmov [r8-0Ch], eax\nadd edx, r10d\nlea r10d, [rax+rdx]\nmov [r8-8], edx\nadd edi, r10d\nmov r10d, ecx\nadd ecx, 3\nadd r10d, 4\nmov [r8-4], edi\ncmp r11d, r10d\njg short loc_133A\nloc_136E:\nmovsxd rax, ecx\nlea rax, [r9+rax*4]\nnop dword ptr [rax]\nloc_1378:\nmov edx, [rax-4]\nadd ecx, 1\nadd edx, [rax-8]\nadd rax, 4\nadd edx, [rax-10h]\nmov [rax-4], edx\ncmp esi, ecx\njge short loc_1378\nloc_138F:\nmov eax, [rsp+rsi*4+1A8h+var_1A8]\nmov rdx, [rsp+1A8h+var_10]\nsub rdx, fs:28h\njnz short loc_13B4\nadd rsp, 1A8h\nretn\nloc_13AD:\nmov ecx, 3\njmp short loc_136E\nloc_13B4:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12E0(int a1)\n{\n __int64 v1; // rsi\n int v2; // eax\n _DWORD *v3; // r8\n int v4; // edi\n int v5; // edx\n int v6; // ecx\n int v7; // r10d\n _DWORD *v8; // rax\n int v9; // edx\n _DWORD v11[102]; // [rsp+0h] [rbp-1A8h] BYREF\n unsigned __int64 v12; // [rsp+198h] [rbp-10h]\n\n v1 = a1;\n v12 = __readfsqword(0x28u);\n v2 = 0;\n memset(v11, 0, 0x190uLL);\n v11[2] = 1;\n if ( a1 > 2 )\n {\n if ( a1 <= 5 )\n {\n v6 = 3;\n }\n else\n {\n v3 = &v11[3];\n v4 = 1;\n v5 = 0;\n v6 = 3;\n do\n {\n v3 += 3;\n v2 += v5 + v4;\n *(v3 - 3) = v2;\n v5 += v2 + v4;\n *(v3 - 2) = v5;\n v4 += v2 + v5;\n v7 = v6;\n v6 += 3;\n *(v3 - 1) = v4;\n }\n while ( (int)v1 - 1 > v7 + 4 );\n }\n v8 = &v11[v6];\n do\n {\n ++v6;\n v9 = *(v8 - 2) + *(v8 - 1);\n ++v8;\n *(v8 - 1) = *(v8 - 4) + v9;\n }\n while ( (int)v1 >= v6 );\n }\n return (unsigned int)v11[v1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12E0(int a1) {\n long long v1;\n int v2;\n uint32_t *v3;\n int v4;\n int v5;\n int v6;\n int v7;\n uint32_t *v8;\n int v9;\n uint32_t v11[102];\n unsigned long long v12;\n v1 = a1;\n v12 = __readfsqword(40u);\n v2 = 0;\n memset(v11, 0, 400uLL);\n v11[2] = 1;\n if (a1 > 2) {\n if (a1 <= 5) {\n v6 = 3;\n } else {\n v3 = &v11[3];\n v4 = 1;\n v5 = 0;\n v6 = 3;\n do {\n v3 += 3;\n v2 += v5 + v4;\n *(v3 - 3) = v2;\n v5 += v2 + v4;\n *(v3 - 2) = v5;\n v4 += v2 + v5;\n v7 = v6;\n v6 += 3;\n *(v3 - 1) = v4;\n } while ((int)v1 - 1 > v7 + 4);\n }\n v8 = &v11[v6];\n do {\n ++v6;\n v9 = *(v8 - 2) + *(v8 - 1);\n ++v8;\n *(v8 - 1) = *(v8 - 4) + v9;\n } while ((int)v1 >= v6);\n }\n return (unsigned int)v11[v1];\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n long long v1;\n int v2;\n uint32_t *v3;\n int v4;\n int v5;\n int v6;\n int v7;\n uint32_t *v8;\n int v9;\n uint32_t v11[102];\n unsigned long long v12;\n v1 = a1;\n v12 = __readfsqword(40u);\n v2 = 0;\n memset(v11, 0, 400uLL);\n v11[2] = 1;\n if (a1 > 2) {\n if (a1 <= 5) {\n v6 = 3;\n } else {\n v3 = &v11[3];\n v4 = 1;\n v5 = 0;\n v6 = 3;\n do {\n v3 += 3;\n v2 += v5 + v4;\n *(v3 - 3) = v2;\n v5 += v2 + v4;\n *(v3 - 2) = v5;\n v4 += v2 + v5;\n v7 = v6;\n v6 += 3;\n *(v3 - 1) = v4;\n } while ((int)v1 - 1 > v7 + 4);\n }\n v8 = &v11[v6];\n do {\n ++v6;\n v9 = *(v8 - 2) + *(v8 - 1);\n ++v8;\n *(v8 - 1) = *(v8 - 4) + v9;\n } while ((int)v1 >= v6);\n }\n return (unsigned int)v11[v1];\n}" + }, + { + "index": "HumanEval-C-64", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int func0(const char *s) {\n const char *vowels = \"aeiouAEIOU\";\n int count = 0;\n int length = strlen(s);\n for (int i = 0; i < length; i++) {\n if (strchr(vowels, s[i])) {\n count++;\n }\n }\n if (length > 0 && (s[length - 1] == 'y' || s[length - 1] == 'Y')) {\n count++;\n }\n return count;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"abcde\") == 2);\n assert(func0(\"Alone\") == 3);\n assert(func0(\"key\") == 2);\n assert(func0(\"bye\") == 1);\n assert(func0(\"keY\") == 2);\n assert(func0(\"bYe\") == 1);\n assert(func0(\"ACEDY\") == 3);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nlea rax, aAeiouaeiou; \"aeiouAEIOU\"\nmov [rbp+var_8], rax\nmov [rbp+var_14], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_C], eax\nmov [rbp+var_10], 0\njmp short loc_11F1\nloc_11C3:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx edx, al\nmov rax, [rbp+var_8]\nmov esi, edx; c\nmov rdi, rax; s\ncall _strchr\ntest rax, rax\njz short loc_11ED\nadd [rbp+var_14], 1\nloc_11ED:\nadd [rbp+var_10], 1\nloc_11F1:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_C]\njl short loc_11C3\ncmp [rbp+var_C], 0\njle short loc_1231\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 79h ; 'y'\njz short loc_122D\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 59h ; 'Y'\njnz short loc_1231\nloc_122D:\nadd [rbp+var_14], 1\nloc_1231:\nmov eax, [rbp+var_14]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n unsigned int v2; // [rsp+1Ch] [rbp-14h]\n int i; // [rsp+20h] [rbp-10h]\n int v4; // [rsp+24h] [rbp-Ch]\n\n v2 = 0;\n v4 = strlen(a1);\n for ( i = 0; i < v4; ++i )\n {\n if ( strchr(\"aeiouAEIOU\", a1[i]) )\n ++v2;\n }\n if ( v4 > 0 && (a1[v4 - 1] == 121 || a1[v4 - 1] == 89) )\n ++v2;\n return v2;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nlea rax, aAeiouaeiou; \"aeiouAEIOU\"\nmov [rbp+var_8], rax\nmov [rbp+var_14], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_C], eax\nmov [rbp+var_10], 0\njmp short loc_11F1\nloc_11C3:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx edx, al\nmov rax, [rbp+var_8]\nmov esi, edx; c\nmov rdi, rax; s\ncall _strchr\ntest rax, rax\njz short loc_11ED\nadd [rbp+var_14], 1\nloc_11ED:\nadd [rbp+var_10], 1\nloc_11F1:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_C]\njl short loc_11C3\ncmp [rbp+var_C], 0\njle short loc_1231\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 79h ; 'y'\njz short loc_122D\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 59h ; 'Y'\njnz short loc_1231\nloc_122D:\nadd [rbp+var_14], 1\nloc_1231:\nmov eax, [rbp+var_14]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(const char *a1)\n{\n unsigned int v2; // [rsp+1Ch] [rbp-14h]\n int i; // [rsp+20h] [rbp-10h]\n int v4; // [rsp+24h] [rbp-Ch]\n\n v2 = 0;\n v4 = strlen(a1);\n for ( i = 0; i < v4; ++i )\n {\n if ( strchr(\"aeiouAEIOU\", a1[i]) )\n ++v2;\n }\n if ( v4 > 0 && (a1[v4 - 1] == 121 || a1[v4 - 1] == 89) )\n ++v2;\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(const char *a1) {\n unsigned int v2;\n int i;\n int v4;\n v2 = 0;\n v4 = strlen(a1);\n for (i = 0; i < v4; ++i) {\n if (strchr(\"aeiouAEIOU\", a1[i])) ++v2;\n }\n if (v4 > 0 && (a1[v4 - 1] == 121 || a1[v4 - 1] == 89)) ++v2;\n return v2;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n unsigned int v2;\n int i;\n int v4;\n v2 = 0;\n v4 = strlen(a1);\n for (i = 0; i < v4; ++i) {\n if (strchr(\"aeiouAEIOU\", a1[i])) ++v2;\n }\n if (v4 > 0 && (a1[v4 - 1] == 121 || a1[v4 - 1] == 89)) ++v2;\n return v2;\n}" + }, + { + "index": "HumanEval-C-64", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int func0(const char *s) {\n const char *vowels = \"aeiouAEIOU\";\n int count = 0;\n int length = strlen(s);\n for (int i = 0; i < length; i++) {\n if (strchr(vowels, s[i])) {\n count++;\n }\n }\n if (length > 0 && (s[length - 1] == 'y' || s[length - 1] == 'Y')) {\n count++;\n }\n return count;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"abcde\") == 2);\n assert(func0(\"Alone\") == 3);\n assert(func0(\"key\") == 2);\n assert(func0(\"bye\") == 1);\n assert(func0(\"keY\") == 2);\n assert(func0(\"bYe\") == 1);\n assert(func0(\"ACEDY\") == 3);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r15, rdi\ncall _strlen\ntest eax, eax\njle short loc_1203\nmov r14, rax\nmov rbx, r15\nlea eax, [rax-1]\nlea r13, [r15+rax+1]\nmov ebp, 0\nlea r12, s; \"aeiouAEIOU\"\nloc_11C1:\nmovsx esi, byte ptr [rbx]; c\nmov rdi, r12; s\ncall _strchr\ncmp rax, 1\nsbb ebp, 0FFFFFFFFh\nadd rbx, 1\ncmp rbx, r13\njnz short loc_11C1\nmovsxd r14, r14d\nmovzx eax, byte ptr [r15+r14-1]\nand eax, 0FFFFFFDFh\ncmp al, 59h ; 'Y'\nsetz al\nmovzx eax, al\nadd ebp, eax\nloc_11F2:\nmov eax, ebp\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1203:\nmov ebp, 0\njmp short loc_11F2", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v1; // eax\n int v2; // r14d\n const char *v3; // rbx\n __int64 v4; // r13\n int v5; // ebp\n\n v1 = strlen(a1);\n if ( v1 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = v1;\n v3 = a1;\n v4 = (__int64)&a1[v1 - 1 + 1];\n v5 = 0;\n do\n v5 -= (strchr(\"aeiouAEIOU\", *v3++) == 0LL) - 1;\n while ( v3 != (const char *)v4 );\n return (unsigned int)(((a1[v2 - 1] & 0xDF) == 89) + v5);\n }\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r15, rdi\ncall _strlen\ntest eax, eax\njle short loc_1203\nmov r14, rax\nmov rbx, r15\nlea eax, [rax-1]\nlea r13, [r15+rax+1]\nmov ebp, 0\nlea r12, s; \"aeiouAEIOU\"\nloc_11C1:\nmovsx esi, byte ptr [rbx]; c\nmov rdi, r12; s\ncall _strchr\ncmp rax, 1\nsbb ebp, 0FFFFFFFFh\nadd rbx, 1\ncmp rbx, r13\njnz short loc_11C1\nmovsxd r14, r14d\nmovzx eax, byte ptr [r15+r14-1]\nand eax, 0FFFFFFDFh\ncmp al, 59h ; 'Y'\nsetz al\nmovzx eax, al\nadd ebp, eax\nloc_11F2:\nmov eax, ebp\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1203:\nmov ebp, 0\njmp short loc_11F2", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(const char *a1)\n{\n int v1; // eax\n int v2; // r14d\n const char *v3; // rbx\n __int64 v4; // r13\n int v5; // ebp\n\n v1 = strlen(a1);\n if ( v1 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = v1;\n v3 = a1;\n v4 = (__int64)&a1[v1 - 1 + 1];\n v5 = 0;\n do\n v5 -= (strchr(\"aeiouAEIOU\", *v3++) == 0LL) - 1;\n while ( v3 != (const char *)v4 );\n return (unsigned int)(((a1[v2 - 1] & 0xDF) == 89) + v5);\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(const char *a1) {\n int v1;\n int v2;\n const char *v3;\n long long v4;\n int v5;\n v1 = strlen(a1);\n if (v1 <= 0) {\n return 0;\n } else {\n v2 = v1;\n v3 = a1;\n v4 = (long long)&a1[v1 - 1 + 1];\n v5 = 0;\n do\n v5 -= (strchr(\"aeiouAEIOU\", *v3++) == 0LL) - 1;\n while (v3 != (const char *)v4);\n return (unsigned int)(((a1[v2 - 1] & 223) == 89) + v5);\n }\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v1;\n int v2;\n const char *v3;\n long long v4;\n int v5;\n v1 = strlen(a1);\n if (v1 <= 0) {\n return 0;\n } else {\n v2 = v1;\n v3 = a1;\n v4 = (long long)&a1[v1 - 1 + 1];\n v5 = 0;\n do\n v5 -= (strchr(\"aeiouAEIOU\", *v3++) == 0LL) - 1;\n while (v3 != (const char *)v4);\n return (unsigned int)(((a1[v2 - 1] & 223) == 89) + v5);\n }\n}" + }, + { + "index": "HumanEval-C-64", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int func0(const char *s) {\n const char *vowels = \"aeiouAEIOU\";\n int count = 0;\n int length = strlen(s);\n for (int i = 0; i < length; i++) {\n if (strchr(vowels, s[i])) {\n count++;\n }\n }\n if (length > 0 && (s[length - 1] == 'y' || s[length - 1] == 'Y')) {\n count++;\n }\n return count;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"abcde\") == 2);\n assert(func0(\"Alone\") == 3);\n assert(func0(\"key\") == 2);\n assert(func0(\"bye\") == 1);\n assert(func0(\"keY\") == 2);\n assert(func0(\"bYe\") == 1);\n assert(func0(\"ACEDY\") == 3);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\nmov r15, rdi\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\ncall _strlen\ntest eax, eax\njle short loc_1380\nmov r14, rax\nlea eax, [rax-1]\nmov rbx, r15\nxor ebp, ebp\nlea r13, [r15+rax+1]\nlea r12, s; \"aeiouAEIOU\"\nnop dword ptr [rax]\nloc_1338:\nmovsx esi, byte ptr [rbx]; c\nmov rdi, r12; s\ncall _strchr\ncmp rax, 1\nsbb ebp, 0FFFFFFFFh\nadd rbx, 1\ncmp rbx, r13\njnz short loc_1338\nmovsxd r14, r14d\nmovzx eax, byte ptr [r15+r14-1]\nand eax, 0FFFFFFDFh\ncmp al, 59h ; 'Y'\nsetz al\nmovzx eax, al\nadd ebp, eax\nloc_1369:\nadd rsp, 8\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1380:\nxor ebp, ebp\njmp short loc_1369", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v1; // eax\n int v2; // r14d\n const char *v3; // rbx\n int v4; // ebp\n __int64 v5; // r13\n\n v1 = strlen(a1);\n if ( v1 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = v1;\n v3 = a1;\n v4 = 0;\n v5 = (__int64)&a1[v1 - 1 + 1];\n do\n v4 -= (strchr(\"aeiouAEIOU\", *v3++) == 0LL) - 1;\n while ( v3 != (const char *)v5 );\n return (unsigned int)(((a1[v2 - 1] & 0xDF) == 89) + v4);\n }\n}", + "ida_strip_asm": "sub_1300:\nendbr64\npush r15\nmov r15, rdi\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\ncall _strlen\ntest eax, eax\njle short loc_1380\nmov r14, rax\nlea eax, [rax-1]\nmov rbx, r15\nxor ebp, ebp\nlea r13, [r15+rax+1]\nlea r12, s; \"aeiouAEIOU\"\nnop dword ptr [rax]\nloc_1338:\nmovsx esi, byte ptr [rbx]; c\nmov rdi, r12; s\ncall _strchr\ncmp rax, 1\nsbb ebp, 0FFFFFFFFh\nadd rbx, 1\ncmp rbx, r13\njnz short loc_1338\nmovsxd r14, r14d\nmovzx eax, byte ptr [r15+r14-1]\nand eax, 0FFFFFFDFh\ncmp al, 59h ; 'Y'\nsetz al\nmovzx eax, al\nadd ebp, eax\nloc_1369:\nadd rsp, 8\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1380:\nxor ebp, ebp\njmp short loc_1369", + "ida_strip_pseudo": "__int64 __fastcall sub_1300(const char *a1)\n{\n int v1; // eax\n int v2; // r14d\n const char *v3; // rbx\n int v4; // ebp\n __int64 v5; // r13\n\n v1 = strlen(a1);\n if ( v1 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = v1;\n v3 = a1;\n v4 = 0;\n v5 = (__int64)&a1[v1 - 1 + 1];\n do\n v4 -= (strchr(\"aeiouAEIOU\", *v3++) == 0LL) - 1;\n while ( v3 != (const char *)v5 );\n return (unsigned int)(((a1[v2 - 1] & 0xDF) == 89) + v4);\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1300(const char *a1) {\n int v1;\n int v2;\n const char *v3;\n int v4;\n long long v5;\n v1 = strlen(a1);\n if (v1 <= 0) {\n return 0;\n } else {\n v2 = v1;\n v3 = a1;\n v4 = 0;\n v5 = (long long)&a1[v1 - 1 + 1];\n do\n v4 -= (strchr(\"aeiouAEIOU\", *v3++) == 0LL) - 1;\n while (v3 != (const char *)v5);\n return (unsigned int)(((a1[v2 - 1] & 223) == 89) + v4);\n }\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v1;\n int v2;\n const char *v3;\n int v4;\n long long v5;\n v1 = strlen(a1);\n if (v1 <= 0) {\n return 0;\n } else {\n v2 = v1;\n v3 = a1;\n v4 = 0;\n v5 = (long long)&a1[v1 - 1 + 1];\n do\n v4 -= (strchr(\"aeiouAEIOU\", *v3++) == 0LL) - 1;\n while (v3 != (const char *)v5);\n return (unsigned int)(((a1[v2 - 1] & 223) == 89) + v4);\n }\n}" + }, + { + "index": "HumanEval-C-64", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int func0(const char *s) {\n const char *vowels = \"aeiouAEIOU\";\n int count = 0;\n int length = strlen(s);\n for (int i = 0; i < length; i++) {\n if (strchr(vowels, s[i])) {\n count++;\n }\n }\n if (length > 0 && (s[length - 1] == 'y' || s[length - 1] == 'Y')) {\n count++;\n }\n return count;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"abcde\") == 2);\n assert(func0(\"Alone\") == 3);\n assert(func0(\"key\") == 2);\n assert(func0(\"bye\") == 1);\n assert(func0(\"keY\") == 2);\n assert(func0(\"bYe\") == 1);\n assert(func0(\"ACEDY\") == 3);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\nmov r15, rdi\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\ncall _strlen\ntest eax, eax\njle short loc_1380\nmov r14, rax\nlea eax, [rax-1]\nmov rbx, r15\nxor ebp, ebp\nlea r13, [r15+rax+1]\nlea r12, s; \"aeiouAEIOU\"\nnop dword ptr [rax]\nloc_1338:\nmovsx esi, byte ptr [rbx]; c\nmov rdi, r12; s\ncall _strchr\ncmp rax, 1\nsbb ebp, 0FFFFFFFFh\nadd rbx, 1\ncmp rbx, r13\njnz short loc_1338\nmovsxd r14, r14d\nmovzx eax, byte ptr [r15+r14-1]\nand eax, 0FFFFFFDFh\ncmp al, 59h ; 'Y'\nsetz al\nmovzx eax, al\nadd ebp, eax\nloc_1369:\nadd rsp, 8\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1380:\nxor ebp, ebp\njmp short loc_1369", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v1; // eax\n int v2; // r14d\n const char *v3; // rbx\n int v4; // ebp\n __int64 v5; // r13\n\n v1 = strlen(a1);\n if ( v1 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = v1;\n v3 = a1;\n v4 = 0;\n v5 = (__int64)&a1[v1 - 1 + 1];\n do\n v4 -= (strchr(\"aeiouAEIOU\", *v3++) == 0LL) - 1;\n while ( v3 != (const char *)v5 );\n return (unsigned int)(((a1[v2 - 1] & 0xDF) == 89) + v4);\n }\n}", + "ida_strip_asm": "sub_1300:\nendbr64\npush r15\nmov r15, rdi\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\ncall _strlen\ntest eax, eax\njle short loc_1380\nmov r14, rax\nlea eax, [rax-1]\nmov rbx, r15\nxor ebp, ebp\nlea r13, [r15+rax+1]\nlea r12, s; \"aeiouAEIOU\"\nnop dword ptr [rax]\nloc_1338:\nmovsx esi, byte ptr [rbx]; c\nmov rdi, r12; s\ncall _strchr\ncmp rax, 1\nsbb ebp, 0FFFFFFFFh\nadd rbx, 1\ncmp rbx, r13\njnz short loc_1338\nmovsxd r14, r14d\nmovzx eax, byte ptr [r15+r14-1]\nand eax, 0FFFFFFDFh\ncmp al, 59h ; 'Y'\nsetz al\nmovzx eax, al\nadd ebp, eax\nloc_1369:\nadd rsp, 8\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1380:\nxor ebp, ebp\njmp short loc_1369", + "ida_strip_pseudo": "__int64 __fastcall sub_1300(const char *a1)\n{\n int v1; // eax\n int v2; // r14d\n const char *v3; // rbx\n int v4; // ebp\n __int64 v5; // r13\n\n v1 = strlen(a1);\n if ( v1 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = v1;\n v3 = a1;\n v4 = 0;\n v5 = (__int64)&a1[v1 - 1 + 1];\n do\n v4 -= (strchr(\"aeiouAEIOU\", *v3++) == 0LL) - 1;\n while ( v3 != (const char *)v5 );\n return (unsigned int)(((a1[v2 - 1] & 0xDF) == 89) + v4);\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1300(const char *a1) {\n int v1;\n int v2;\n const char *v3;\n int v4;\n long long v5;\n v1 = strlen(a1);\n if (v1 <= 0) {\n return 0;\n } else {\n v2 = v1;\n v3 = a1;\n v4 = 0;\n v5 = (long long)&a1[v1 - 1 + 1];\n do\n v4 -= (strchr(\"aeiouAEIOU\", *v3++) == 0LL) - 1;\n while (v3 != (const char *)v5);\n return (unsigned int)(((a1[v2 - 1] & 223) == 89) + v4);\n }\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v1;\n int v2;\n const char *v3;\n int v4;\n long long v5;\n v1 = strlen(a1);\n if (v1 <= 0) {\n return 0;\n } else {\n v2 = v1;\n v3 = a1;\n v4 = 0;\n v5 = (long long)&a1[v1 - 1 + 1];\n do\n v4 -= (strchr(\"aeiouAEIOU\", *v3++) == 0LL) - 1;\n while (v3 != (const char *)v5);\n return (unsigned int)(((a1[v2 - 1] & 223) == 89) + v4);\n }\n}" + }, + { + "index": "HumanEval-C-65", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char* func0(int x, int shift) {\n static char xs[50];\n sprintf(xs, \"%d\", x);\n int len = strlen(xs);\n if (len < shift) {\n for (int i = 0; i < len / 2; i++) {\n char temp = xs[i];\n xs[i] = xs[len - 1 - i];\n xs[len - 1 - i] = temp;\n }\n } else {\n char temp[50];\n strcpy(temp, xs + len - shift);\n temp[shift] = '\\0';\n strncat(temp, xs, len - shift);\n strcpy(xs, temp);\n }\n return xs;\n}", + "test": "#include \n#include \n\nint main() {\n assert(strcmp(func0(100, 2), \"001\") == 0);\n assert(strcmp(func0(12, 2), \"12\") == 0);\n assert(strcmp(func0(97, 8), \"79\") == 0);\n assert(strcmp(func0(12, 1), \"21\") == 0);\n assert(strcmp(func0(11, 101), \"11\") == 0);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 60h\nmov [rbp+var_54], edi\nmov [rbp+var_58], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov eax, [rbp+var_54]\nmov edx, eax\nlea rax, format; \"%d\"\nmov rsi, rax; format\nlea rax, xs_1\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rax, xs_1\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_44], eax\nmov eax, [rbp+var_44]\ncmp eax, [rbp+var_58]\njge short loc_12D8\nmov [rbp+var_48], 0\njmp short loc_12C5\nloc_1270:\nmov eax, [rbp+var_48]\ncdqe\nlea rdx, xs_1\nmovzx eax, byte ptr [rax+rdx]\nmov [rbp+var_49], al\nmov eax, [rbp+var_44]\nsub eax, 1\nsub eax, [rbp+var_48]\ncdqe\nlea rdx, xs_1\nmovzx edx, byte ptr [rax+rdx]\nmov eax, [rbp+var_48]\ncdqe\nlea rcx, xs_1\nmov [rax+rcx], dl\nmov eax, [rbp+var_44]\nsub eax, 1\nsub eax, [rbp+var_48]\ncdqe\nlea rcx, xs_1\nmovzx edx, [rbp+var_49]\nmov [rax+rcx], dl\nadd [rbp+var_48], 1\nloc_12C5:\nmov eax, [rbp+var_44]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\ncmp [rbp+var_48], eax\njl short loc_1270\njmp short loc_133E\nloc_12D8:\nmov eax, [rbp+var_44]\nmovsxd rdx, eax\nmov eax, [rbp+var_58]\ncdqe\nsub rdx, rax\nlea rax, xs_1\nadd rdx, rax\nlea rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\nmov eax, [rbp+var_58]\ncdqe\nmov [rbp+rax+dest], 0\nmov eax, [rbp+var_44]\nsub eax, [rbp+var_58]\nmovsxd rdx, eax; n\nlea rax, [rbp+dest]\nlea rcx, xs_1\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strncat\nlea rax, [rbp+dest]\nmov rsi, rax; src\nlea rax, xs_1\nmov rdi, rax; dest\ncall _strcpy\nloc_133E:\nlea rax, xs_1\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1359\ncall ___stack_chk_fail\nlocret_1359:\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(int a1, int a2)\n{\n char v3; // [rsp+17h] [rbp-49h]\n int i; // [rsp+18h] [rbp-48h]\n int v5; // [rsp+1Ch] [rbp-44h]\n char dest[56]; // [rsp+20h] [rbp-40h] BYREF\n unsigned __int64 v7; // [rsp+58h] [rbp-8h]\n\n v7 = __readfsqword(0x28u);\n sprintf(xs_1, \"%d\", a1);\n v5 = strlen(xs_1);\n if ( v5 >= a2 )\n {\n strcpy(dest, &xs_1[v5 - (__int64)a2]);\n dest[a2] = 0;\n strncat(dest, xs_1, v5 - a2);\n strcpy(xs_1, dest);\n }\n else\n {\n for ( i = 0; i < v5 / 2; ++i )\n {\n v3 = xs_1[i];\n xs_1[i] = xs_1[v5 - 1 - i];\n xs_1[v5 - 1 - i] = v3;\n }\n }\n return xs_1;\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 60h\nmov [rbp+var_54], edi\nmov [rbp+var_58], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov eax, [rbp+var_54]\nmov edx, eax\nlea rax, format; \"%d\"\nmov rsi, rax; format\nlea rax, dest\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rax, dest\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_44], eax\nmov eax, [rbp+var_44]\ncmp eax, [rbp+var_58]\njge short loc_12D8\nmov [rbp+var_48], 0\njmp short loc_12C5\nloc_1270:\nmov eax, [rbp+var_48]\ncdqe\nlea rdx, dest\nmovzx eax, byte ptr [rax+rdx]\nmov [rbp+var_49], al\nmov eax, [rbp+var_44]\nsub eax, 1\nsub eax, [rbp+var_48]\ncdqe\nlea rdx, dest\nmovzx edx, byte ptr [rax+rdx]\nmov eax, [rbp+var_48]\ncdqe\nlea rcx, dest\nmov [rax+rcx], dl\nmov eax, [rbp+var_44]\nsub eax, 1\nsub eax, [rbp+var_48]\ncdqe\nlea rcx, dest\nmovzx edx, [rbp+var_49]\nmov [rax+rcx], dl\nadd [rbp+var_48], 1\nloc_12C5:\nmov eax, [rbp+var_44]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\ncmp [rbp+var_48], eax\njl short loc_1270\njmp short loc_133E\nloc_12D8:\nmov eax, [rbp+var_44]\nmovsxd rdx, eax\nmov eax, [rbp+var_58]\ncdqe\nsub rdx, rax\nlea rax, dest\nadd rdx, rax\nlea rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\nmov eax, [rbp+var_58]\ncdqe\nmov [rbp+rax+dest], 0\nmov eax, [rbp+var_44]\nsub eax, [rbp+var_58]\nmovsxd rdx, eax; n\nlea rax, [rbp+dest]\nlea rcx, dest\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strncat\nlea rax, [rbp+dest]\nmov rsi, rax; src\nlea rax, dest\nmov rdi, rax; dest\ncall _strcpy\nloc_133E:\nlea rax, dest\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1359\ncall ___stack_chk_fail\nlocret_1359:\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1209(int a1, int a2)\n{\n char v3; // [rsp+17h] [rbp-49h]\n int i; // [rsp+18h] [rbp-48h]\n int v5; // [rsp+1Ch] [rbp-44h]\n char dest[56]; // [rsp+20h] [rbp-40h] BYREF\n unsigned __int64 v7; // [rsp+58h] [rbp-8h]\n\n v7 = __readfsqword(0x28u);\n sprintf(::dest, \"%d\", a1);\n v5 = strlen(::dest);\n if ( v5 >= a2 )\n {\n strcpy(dest, &::dest[v5 - (__int64)a2]);\n dest[a2] = 0;\n strncat(dest, ::dest, v5 - a2);\n strcpy(::dest, dest);\n }\n else\n {\n for ( i = 0; i < v5 / 2; ++i )\n {\n v3 = ::dest[i];\n ::dest[i] = ::dest[v5 - 1 - i];\n ::dest[v5 - 1 - i] = v3;\n }\n }\n return ::dest;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char* sub_1209(int a1, int a2) {\n char v3;\n int i;\n int v5;\n char dest[56];\n unsigned long long v7;\n v7 = __readfsqword(40u);\n sprintf(::dest, \"%d\", a1);\n v5 = strlen(::dest);\n if (v5 >= a2) {\n strcpy(dest, &::dest[v5 - (long long)a2]);\n dest[a2] = 0;\n strncat(dest, ::dest, v5 - a2);\n strcpy(::dest, dest);\n } else {\n for (i = 0; i < v5 / 2; ++i) {\n v3 = ::dest[i];\n ::dest[i] = ::dest[v5 - 1 - i];\n ::dest[v5 - 1 - i] = v3;\n }\n }\n return ::dest;\n}", + "ida_pseudo_norm": "char* func0(int a1, int a2) {\n char v3;\n int i;\n int v5;\n char dest[56];\n unsigned long long v7;\n v7 = __readfsqword(40u);\n sprintf(xs_1, \"%d\", a1);\n v5 = strlen(xs_1);\n if (v5 >= a2) {\n strcpy(dest, &xs_1[v5 - (long long)a2]);\n dest[a2] = 0;\n strncat(dest, xs_1, v5 - a2);\n strcpy(xs_1, dest);\n } else {\n for (i = 0; i < v5 / 2; ++i) {\n v3 = xs_1[i];\n xs_1[i] = xs_1[v5 - 1 - i];\n xs_1[v5 - 1 - i] = v3;\n }\n }\n return xs_1;\n}" + }, + { + "index": "HumanEval-C-65", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char* func0(int x, int shift) {\n static char xs[50];\n sprintf(xs, \"%d\", x);\n int len = strlen(xs);\n if (len < shift) {\n for (int i = 0; i < len / 2; i++) {\n char temp = xs[i];\n xs[i] = xs[len - 1 - i];\n xs[len - 1 - i] = temp;\n }\n } else {\n char temp[50];\n strcpy(temp, xs + len - shift);\n temp[shift] = '\\0';\n strncat(temp, xs, len - shift);\n strcpy(xs, temp);\n }\n return xs;\n}", + "test": "#include \n#include \n\nint main() {\n assert(strcmp(func0(100, 2), \"001\") == 0);\n assert(strcmp(func0(12, 2), \"12\") == 0);\n assert(strcmp(func0(97, 8), \"79\") == 0);\n assert(strcmp(func0(12, 1), \"21\") == 0);\n assert(strcmp(func0(11, 101), \"11\") == 0);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 48h\nmov r8d, edi\nmov ebp, esi\nmov rax, fs:28h\nmov [rsp+68h+var_30], rax\nxor eax, eax\nlea rcx, unk_2004\nmov edx, 32h ; '2'\nmov esi, 2\nlea rbx, xs_1\nmov rdi, rbx\ncall ___sprintf_chk\nmov rdi, rbx; s\ncall _strlen\ncmp eax, ebp\njge short loc_12B6\nmov r8d, eax\nshr r8d, 1Fh\nadd r8d, eax\nsar r8d, 1\ncmp eax, 1\njle short loc_1294\ncdqe\nadd rax, rbx\nmov edx, 0\nmov rcx, rbx\nloc_1277:\nmovzx esi, byte ptr [rcx+rdx]\nmovzx edi, byte ptr [rax-1]\nmov [rcx+rdx], dil\nmov [rax-1], sil\nadd rdx, 1\nsub rax, 1\ncmp r8d, edx\njg short loc_1277\nloc_1294:\nmov rax, [rsp+68h+var_30]\nsub rax, fs:28h\njnz short loc_1303\nlea rax, xs_1\nadd rsp, 48h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_12B6:\nmovsxd rbx, eax\nmovsxd rbp, ebp\nsub rbx, rbp\nlea r12, xs_1\nlea rsi, [rbx+r12]\nmov r13, rsp\nmov edx, 32h ; '2'\nmov rdi, r13\ncall ___strcpy_chk\nmov [rsp+rbp+68h+var_68], 0\nmov ecx, 32h ; '2'\nmov rdx, rbx\nmov rsi, r12\nmov rdi, r13\ncall ___strncat_chk\nmov edx, 32h ; '2'\nmov rsi, r13\nmov rdi, r12\ncall ___strcpy_chk\njmp short loc_1294\nloc_1303:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(unsigned int a1, int a2)\n{\n int v2; // eax\n int v3; // r8d\n char *v4; // rax\n __int64 v5; // rdx\n char v6; // si\n __int64 v8; // rbx\n _BYTE v9[56]; // [rsp+0h] [rbp-68h] BYREF\n unsigned __int64 v10; // [rsp+38h] [rbp-30h]\n\n v10 = __readfsqword(0x28u);\n __sprintf_chk(xs_1, 2LL, 50LL, &unk_2004, a1);\n v2 = strlen(xs_1);\n if ( v2 >= a2 )\n {\n v8 = v2 - (__int64)a2;\n __strcpy_chk(v9, &xs_1[v8], 50LL);\n v9[a2] = 0;\n __strncat_chk(v9, xs_1, v8, 50LL);\n __strcpy_chk(xs_1, v9, 50LL);\n }\n else\n {\n v3 = v2 / 2;\n if ( v2 > 1 )\n {\n v4 = &xs_1[v2];\n v5 = 0LL;\n do\n {\n v6 = xs_1[v5];\n xs_1[v5] = *(v4 - 1);\n *(v4 - 1) = v6;\n ++v5;\n --v4;\n }\n while ( v3 > (int)v5 );\n }\n }\n return xs_1;\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 48h\nmov r8d, edi\nmov ebp, esi\nmov rax, fs:28h\nmov [rsp+68h+var_30], rax\nxor eax, eax\nlea rcx, unk_2004\nmov edx, 32h ; '2'\nmov esi, 2\nlea rbx, s\nmov rdi, rbx\ncall ___sprintf_chk\nmov rdi, rbx; s\ncall _strlen\ncmp eax, ebp\njge short loc_12B6\nmov r8d, eax\nshr r8d, 1Fh\nadd r8d, eax\nsar r8d, 1\ncmp eax, 1\njle short loc_1294\ncdqe\nadd rax, rbx\nmov edx, 0\nmov rcx, rbx\nloc_1277:\nmovzx esi, byte ptr [rcx+rdx]\nmovzx edi, byte ptr [rax-1]\nmov [rcx+rdx], dil\nmov [rax-1], sil\nadd rdx, 1\nsub rax, 1\ncmp r8d, edx\njg short loc_1277\nloc_1294:\nmov rax, [rsp+68h+var_30]\nsub rax, fs:28h\njnz short loc_1303\nlea rax, s\nadd rsp, 48h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_12B6:\nmovsxd rbx, eax\nmovsxd rbp, ebp\nsub rbx, rbp\nlea r12, s\nlea rsi, [rbx+r12]\nmov r13, rsp\nmov edx, 32h ; '2'\nmov rdi, r13\ncall ___strcpy_chk\nmov [rsp+rbp+68h+var_68], 0\nmov ecx, 32h ; '2'\nmov rdx, rbx\nmov rsi, r12\nmov rdi, r13\ncall ___strncat_chk\nmov edx, 32h ; '2'\nmov rsi, r13\nmov rdi, r12\ncall ___strcpy_chk\njmp short loc_1294\nloc_1303:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_1209(unsigned int a1, int a2)\n{\n int v2; // eax\n int v3; // r8d\n char *v4; // rax\n __int64 v5; // rdx\n char v6; // si\n __int64 v8; // rbx\n _BYTE v9[56]; // [rsp+0h] [rbp-68h] BYREF\n unsigned __int64 v10; // [rsp+38h] [rbp-30h]\n\n v10 = __readfsqword(0x28u);\n __sprintf_chk(s, 2LL, 50LL, &unk_2004, a1);\n v2 = strlen(s);\n if ( v2 >= a2 )\n {\n v8 = v2 - (__int64)a2;\n __strcpy_chk(v9, &s[v8], 50LL);\n v9[a2] = 0;\n __strncat_chk(v9, s, v8, 50LL);\n __strcpy_chk(s, v9, 50LL);\n }\n else\n {\n v3 = v2 / 2;\n if ( v2 > 1 )\n {\n v4 = &s[v2];\n v5 = 0LL;\n do\n {\n v6 = s[v5];\n s[v5] = *(v4 - 1);\n *(v4 - 1) = v6;\n ++v5;\n --v4;\n }\n while ( v3 > (int)v5 );\n }\n }\n return s;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1209(unsigned int a1, int a2) {\n int v2;\n int v3;\n char *v4;\n long long v5;\n char v6;\n long long v8;\n uint8_t v9[56];\n unsigned long long v10;\n v10 = __readfsqword(40u);\n __sprintf_chk(s, 2LL, 50LL, &unk_2004, a1);\n v2 = strlen(s);\n if (v2 >= a2) {\n v8 = v2 - (long long)a2;\n __strcpy_chk(v9, &s[v8], 50LL);\n v9[a2] = 0;\n __strncat_chk(v9, s, v8, 50LL);\n __strcpy_chk(s, v9, 50LL);\n } else {\n v3 = v2 / 2;\n if (v2 > 1) {\n v4 = &s[v2];\n v5 = 0LL;\n do {\n v6 = s[v5];\n s[v5] = *(v4 - 1);\n *(v4 - 1) = v6;\n ++v5;\n --v4;\n } while (v3 > (int)v5);\n }\n }\n return s;\n}", + "ida_pseudo_norm": "char *func0(unsigned int a1, int a2) {\n int v2;\n int v3;\n char *v4;\n long long v5;\n char v6;\n long long v8;\n uint8_t v9[56];\n unsigned long long v10;\n v10 = __readfsqword(40u);\n __sprintf_chk(xs_1, 2LL, 50LL, &unk_2004, a1);\n v2 = strlen(xs_1);\n if (v2 >= a2) {\n v8 = v2 - (long long)a2;\n __strcpy_chk(v9, &xs_1[v8], 50LL);\n v9[a2] = 0;\n __strncat_chk(v9, xs_1, v8, 50LL);\n __strcpy_chk(xs_1, v9, 50LL);\n } else {\n v3 = v2 / 2;\n if (v2 > 1) {\n v4 = &xs_1[v2];\n v5 = 0LL;\n do {\n v6 = xs_1[v5];\n xs_1[v5] = *(v4 - 1);\n *(v4 - 1) = v6;\n ++v5;\n --v4;\n } while (v3 > (int)v5);\n }\n }\n return xs_1;\n}" + }, + { + "index": "HumanEval-C-65", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char* func0(int x, int shift) {\n static char xs[50];\n sprintf(xs, \"%d\", x);\n int len = strlen(xs);\n if (len < shift) {\n for (int i = 0; i < len / 2; i++) {\n char temp = xs[i];\n xs[i] = xs[len - 1 - i];\n xs[len - 1 - i] = temp;\n }\n } else {\n char temp[50];\n strcpy(temp, xs + len - shift);\n temp[shift] = '\\0';\n strncat(temp, xs, len - shift);\n strcpy(xs, temp);\n }\n return xs;\n}", + "test": "#include \n#include \n\nint main() {\n assert(strcmp(func0(100, 2), \"001\") == 0);\n assert(strcmp(func0(12, 2), \"12\") == 0);\n assert(strcmp(func0(97, 8), \"79\") == 0);\n assert(strcmp(func0(12, 1), \"21\") == 0);\n assert(strcmp(func0(11, 101), \"11\") == 0);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r12\nmov r8d, edi\nmovsxd r12, esi\nmov edx, 32h ; '2'\npush rbp\nlea rcx, unk_2004\nmov esi, 2\npush rbx\nlea rbx, xs_1\nmov rdi, rbx\nsub rsp, 40h\nmov rax, fs:28h\nmov [rsp+58h+var_20], rax\nxor eax, eax\ncall ___sprintf_chk\nmov rdi, rbx; s\ncall _strlen\ncmp eax, r12d\njge short loc_1400\nmov edi, eax\nsar edi, 1\njz short loc_13E2\nmovsxd rdi, edi\nmov rdx, rbx\nlea rax, [rbx+rax-1]\nadd rdi, rbx\nnop dword ptr [rax+rax+00h]\nloc_13C8:\nmovzx esi, byte ptr [rax]\nmovzx ecx, byte ptr [rdx]\nadd rdx, 1\nsub rax, 1\nmov [rdx-1], sil\nmov [rax+1], cl\ncmp rdx, rdi\njnz short loc_13C8\nloc_13E2:\nmov rax, [rsp+58h+var_20]\nsub rax, fs:28h\njnz short loc_1441\nadd rsp, 40h\nmov rax, rbx\npop rbx\npop rbp\npop r12\nretn\nloc_1400:\nsub rax, r12\nmov rdi, rsp\nmov edx, 32h ; '2'\nlea rsi, [rbx+rax]\nmov rbp, rax\ncall ___strcpy_chk\nmov rdx, rbp\nmov rsi, rbx\nmov ecx, 32h ; '2'\nmov rdi, rax\nmov [rsp+r12+58h+var_58], 0\ncall ___strncat_chk\nmov edx, 32h ; '2'\nmov rdi, rbx\nmov rsi, rax\ncall ___strcpy_chk\njmp short loc_13E2\nloc_1441:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(unsigned int a1, int a2)\n{\n size_t v2; // rax\n int v3; // edi\n char *v4; // rdx\n char *v5; // rax\n char *v6; // rdi\n char v7; // si\n char v8; // cl\n size_t v10; // rbp\n __int64 v11; // rax\n __int64 v12; // rax\n _BYTE v13[56]; // [rsp+0h] [rbp-58h] BYREF\n unsigned __int64 v14; // [rsp+38h] [rbp-20h]\n\n v14 = __readfsqword(0x28u);\n __sprintf_chk(xs_1, 2LL, 50LL, &unk_2004, a1);\n v2 = strlen(xs_1);\n if ( (int)v2 >= a2 )\n {\n v10 = v2 - a2;\n v11 = __strcpy_chk(v13, &xs_1[v10], 50LL);\n v13[a2] = 0;\n v12 = __strncat_chk(v11, xs_1, v10, 50LL);\n __strcpy_chk(xs_1, v12, 50LL);\n }\n else\n {\n v3 = (int)v2 >> 1;\n if ( (int)v2 >> 1 )\n {\n v4 = xs_1;\n v5 = &xs_1[v2 - 1];\n v6 = &xs_1[v3];\n do\n {\n v7 = *v5;\n v8 = *v4++;\n --v5;\n *(v4 - 1) = v7;\n v5[1] = v8;\n }\n while ( v4 != v6 );\n }\n }\n return xs_1;\n}", + "ida_strip_asm": "sub_1360:\nendbr64\npush r12\nmov r8d, edi\nmovsxd r12, esi\nmov edx, 32h ; '2'\npush rbp\nlea rcx, unk_2004\nmov esi, 2\npush rbx\nlea rbx, s\nmov rdi, rbx\nsub rsp, 40h\nmov rax, fs:28h\nmov [rsp+58h+var_20], rax\nxor eax, eax\ncall ___sprintf_chk\nmov rdi, rbx; s\ncall _strlen\ncmp eax, r12d\njge short loc_1400\nmov edi, eax\nsar edi, 1\njz short loc_13E2\nmovsxd rdi, edi\nmov rdx, rbx\nlea rax, [rbx+rax-1]\nadd rdi, rbx\nnop dword ptr [rax+rax+00h]\nloc_13C8:\nmovzx esi, byte ptr [rax]\nmovzx ecx, byte ptr [rdx]\nadd rdx, 1\nsub rax, 1\nmov [rdx-1], sil\nmov [rax+1], cl\ncmp rdx, rdi\njnz short loc_13C8\nloc_13E2:\nmov rax, [rsp+58h+var_20]\nsub rax, fs:28h\njnz short loc_1441\nadd rsp, 40h\nmov rax, rbx\npop rbx\npop rbp\npop r12\nretn\nloc_1400:\nsub rax, r12\nmov rdi, rsp\nmov edx, 32h ; '2'\nlea rsi, [rbx+rax]\nmov rbp, rax\ncall ___strcpy_chk\nmov rdx, rbp\nmov rsi, rbx\nmov ecx, 32h ; '2'\nmov rdi, rax\nmov [rsp+r12+58h+var_58], 0\ncall ___strncat_chk\nmov edx, 32h ; '2'\nmov rdi, rbx\nmov rsi, rax\ncall ___strcpy_chk\njmp short loc_13E2\nloc_1441:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_1360(unsigned int a1, int a2)\n{\n size_t v2; // rax\n int v3; // edi\n char *v4; // rdx\n char *v5; // rax\n char *v6; // rdi\n char v7; // si\n char v8; // cl\n size_t v10; // rbp\n __int64 v11; // rax\n __int64 v12; // rax\n _BYTE v13[56]; // [rsp+0h] [rbp-58h] BYREF\n unsigned __int64 v14; // [rsp+38h] [rbp-20h]\n\n v14 = __readfsqword(0x28u);\n __sprintf_chk(s, 2LL, 50LL, &unk_2004, a1);\n v2 = strlen(s);\n if ( (int)v2 >= a2 )\n {\n v10 = v2 - a2;\n v11 = __strcpy_chk(v13, &s[v10], 50LL);\n v13[a2] = 0;\n v12 = __strncat_chk(v11, s, v10, 50LL);\n __strcpy_chk(s, v12, 50LL);\n }\n else\n {\n v3 = (int)v2 >> 1;\n if ( (int)v2 >> 1 )\n {\n v4 = s;\n v5 = &s[v2 - 1];\n v6 = &s[v3];\n do\n {\n v7 = *v5;\n v8 = *v4++;\n --v5;\n *(v4 - 1) = v7;\n v5[1] = v8;\n }\n while ( v4 != v6 );\n }\n }\n return s;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1360(unsigned int a1, int a2) {\n unsigned int v2;\n int v3;\n char *v4;\n char *v5;\n char *v6;\n char v7;\n char v8;\n unsigned int v10;\n long long v11;\n long long v12;\n uint8_t v13[56];\n unsigned long long v14;\n v14 = __readfsqword(40u);\n __sprintf_chk(s, 2LL, 50LL, &unk_2004, a1);\n v2 = strlen(s);\n if ((int)v2 >= a2) {\n v10 = v2 - a2;\n v11 = __strcpy_chk(v13, &s[v10], 50LL);\n v13[a2] = 0;\n v12 = __strncat_chk(v11, s, v10, 50LL);\n __strcpy_chk(s, v12, 50LL);\n } else {\n v3 = (int)v2 >> 1;\n if ((int)v2 >> 1) {\n v4 = s;\n v5 = &s[v2 - 1];\n v6 = &s[v3];\n do {\n v7 = *v5;\n v8 = *v4++;\n --v5;\n *(v4 - 1) = v7;\n v5[1] = v8;\n } while (v4 != v6);\n }\n }\n return s;\n}", + "ida_pseudo_norm": "char *func0(unsigned int a1, int a2) {\n unsigned int v2;\n int v3;\n char *v4;\n char *v5;\n char *v6;\n char v7;\n char v8;\n unsigned int v10;\n long long v11;\n long long v12;\n uint8_t v13[56];\n unsigned long long v14;\n v14 = __readfsqword(40u);\n __sprintf_chk(xs_1, 2LL, 50LL, &unk_2004, a1);\n v2 = strlen(xs_1);\n if ((int)v2 >= a2) {\n v10 = v2 - a2;\n v11 = __strcpy_chk(v13, &xs_1[v10], 50LL);\n v13[a2] = 0;\n v12 = __strncat_chk(v11, xs_1, v10, 50LL);\n __strcpy_chk(xs_1, v12, 50LL);\n } else {\n v3 = (int)v2 >> 1;\n if ((int)v2 >> 1) {\n v4 = xs_1;\n v5 = &xs_1[v2 - 1];\n v6 = &xs_1[v3];\n do {\n v7 = *v5;\n v8 = *v4++;\n --v5;\n *(v4 - 1) = v7;\n v5[1] = v8;\n } while (v4 != v6);\n }\n }\n return xs_1;\n}" + }, + { + "index": "HumanEval-C-65", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char* func0(int x, int shift) {\n static char xs[50];\n sprintf(xs, \"%d\", x);\n int len = strlen(xs);\n if (len < shift) {\n for (int i = 0; i < len / 2; i++) {\n char temp = xs[i];\n xs[i] = xs[len - 1 - i];\n xs[len - 1 - i] = temp;\n }\n } else {\n char temp[50];\n strcpy(temp, xs + len - shift);\n temp[shift] = '\\0';\n strncat(temp, xs, len - shift);\n strcpy(xs, temp);\n }\n return xs;\n}", + "test": "#include \n#include \n\nint main() {\n assert(strcmp(func0(100, 2), \"001\") == 0);\n assert(strcmp(func0(12, 2), \"12\") == 0);\n assert(strcmp(func0(97, 8), \"79\") == 0);\n assert(strcmp(func0(12, 1), \"21\") == 0);\n assert(strcmp(func0(11, 101), \"11\") == 0);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r12\nmov r8d, edi\nmovsxd r12, esi\nmov edx, 32h ; '2'\npush rbp\nlea rcx, unk_2004\nmov esi, 2\npush rbx\nlea rbx, xs_1\nmov rdi, rbx\nsub rsp, 40h\nmov rax, fs:28h\nmov [rsp+58h+var_20], rax\nxor eax, eax\ncall ___sprintf_chk\nmov rdi, rbx; s\ncall _strlen\ncmp eax, r12d\njge short loc_1400\nmov edi, eax\nsar edi, 1\njz short loc_13E2\nmovsxd rdi, edi\nmov rdx, rbx\nlea rax, [rbx+rax-1]\nadd rdi, rbx\nnop dword ptr [rax+rax+00h]\nloc_13C8:\nmovzx esi, byte ptr [rax]\nmovzx ecx, byte ptr [rdx]\nadd rdx, 1\nsub rax, 1\nmov [rdx-1], sil\nmov [rax+1], cl\ncmp rdx, rdi\njnz short loc_13C8\nloc_13E2:\nmov rax, [rsp+58h+var_20]\nsub rax, fs:28h\njnz short loc_1441\nadd rsp, 40h\nmov rax, rbx\npop rbx\npop rbp\npop r12\nretn\nloc_1400:\nsub rax, r12\nmov rdi, rsp\nmov edx, 32h ; '2'\nlea rsi, [rbx+rax]\nmov rbp, rax\ncall ___strcpy_chk\nmov rdx, rbp\nmov rsi, rbx\nmov ecx, 32h ; '2'\nmov rdi, rax\nmov [rsp+r12+58h+var_58], 0\ncall ___strncat_chk\nmov edx, 32h ; '2'\nmov rdi, rbx\nmov rsi, rax\ncall ___strcpy_chk\njmp short loc_13E2\nloc_1441:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(unsigned int a1, int a2)\n{\n size_t v2; // rax\n int v3; // edi\n char *v4; // rdx\n char *v5; // rax\n char *v6; // rdi\n char v7; // si\n char v8; // cl\n size_t v10; // rbp\n __int64 v11; // rax\n __int64 v12; // rax\n _BYTE v13[56]; // [rsp+0h] [rbp-58h] BYREF\n unsigned __int64 v14; // [rsp+38h] [rbp-20h]\n\n v14 = __readfsqword(0x28u);\n __sprintf_chk(xs_1, 2LL, 50LL, &unk_2004, a1);\n v2 = strlen(xs_1);\n if ( (int)v2 >= a2 )\n {\n v10 = v2 - a2;\n v11 = __strcpy_chk(v13, &xs_1[v10], 50LL);\n v13[a2] = 0;\n v12 = __strncat_chk(v11, xs_1, v10, 50LL);\n __strcpy_chk(xs_1, v12, 50LL);\n }\n else\n {\n v3 = (int)v2 >> 1;\n if ( (int)v2 >> 1 )\n {\n v4 = xs_1;\n v5 = &xs_1[v2 - 1];\n v6 = &xs_1[v3];\n do\n {\n v7 = *v5;\n v8 = *v4++;\n --v5;\n *(v4 - 1) = v7;\n v5[1] = v8;\n }\n while ( v4 != v6 );\n }\n }\n return xs_1;\n}", + "ida_strip_asm": "sub_1360:\nendbr64\npush r12\nmov r8d, edi\nmovsxd r12, esi\nmov edx, 32h ; '2'\npush rbp\nlea rcx, unk_2004\nmov esi, 2\npush rbx\nlea rbx, s\nmov rdi, rbx\nsub rsp, 40h\nmov rax, fs:28h\nmov [rsp+58h+var_20], rax\nxor eax, eax\ncall ___sprintf_chk\nmov rdi, rbx; s\ncall _strlen\ncmp eax, r12d\njge short loc_1400\nmov edi, eax\nsar edi, 1\njz short loc_13E2\nmovsxd rdi, edi\nmov rdx, rbx\nlea rax, [rbx+rax-1]\nadd rdi, rbx\nnop dword ptr [rax+rax+00h]\nloc_13C8:\nmovzx esi, byte ptr [rax]\nmovzx ecx, byte ptr [rdx]\nadd rdx, 1\nsub rax, 1\nmov [rdx-1], sil\nmov [rax+1], cl\ncmp rdx, rdi\njnz short loc_13C8\nloc_13E2:\nmov rax, [rsp+58h+var_20]\nsub rax, fs:28h\njnz short loc_1441\nadd rsp, 40h\nmov rax, rbx\npop rbx\npop rbp\npop r12\nretn\nloc_1400:\nsub rax, r12\nmov rdi, rsp\nmov edx, 32h ; '2'\nlea rsi, [rbx+rax]\nmov rbp, rax\ncall ___strcpy_chk\nmov rdx, rbp\nmov rsi, rbx\nmov ecx, 32h ; '2'\nmov rdi, rax\nmov [rsp+r12+58h+var_58], 0\ncall ___strncat_chk\nmov edx, 32h ; '2'\nmov rdi, rbx\nmov rsi, rax\ncall ___strcpy_chk\njmp short loc_13E2\nloc_1441:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_1360(unsigned int a1, int a2)\n{\n size_t v2; // rax\n int v3; // edi\n char *v4; // rdx\n char *v5; // rax\n char *v6; // rdi\n char v7; // si\n char v8; // cl\n size_t v10; // rbp\n __int64 v11; // rax\n __int64 v12; // rax\n _BYTE v13[56]; // [rsp+0h] [rbp-58h] BYREF\n unsigned __int64 v14; // [rsp+38h] [rbp-20h]\n\n v14 = __readfsqword(0x28u);\n __sprintf_chk(s, 2LL, 50LL, &unk_2004, a1);\n v2 = strlen(s);\n if ( (int)v2 >= a2 )\n {\n v10 = v2 - a2;\n v11 = __strcpy_chk(v13, &s[v10], 50LL);\n v13[a2] = 0;\n v12 = __strncat_chk(v11, s, v10, 50LL);\n __strcpy_chk(s, v12, 50LL);\n }\n else\n {\n v3 = (int)v2 >> 1;\n if ( (int)v2 >> 1 )\n {\n v4 = s;\n v5 = &s[v2 - 1];\n v6 = &s[v3];\n do\n {\n v7 = *v5;\n v8 = *v4++;\n --v5;\n *(v4 - 1) = v7;\n v5[1] = v8;\n }\n while ( v4 != v6 );\n }\n }\n return s;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1360(unsigned int a1, int a2) {\n unsigned int v2;\n int v3;\n char *v4;\n char *v5;\n char *v6;\n char v7;\n char v8;\n unsigned int v10;\n long long v11;\n long long v12;\n uint8_t v13[56];\n unsigned long long v14;\n v14 = __readfsqword(40u);\n __sprintf_chk(s, 2LL, 50LL, &unk_2004, a1);\n v2 = strlen(s);\n if ((int)v2 >= a2) {\n v10 = v2 - a2;\n v11 = __strcpy_chk(v13, &s[v10], 50LL);\n v13[a2] = 0;\n v12 = __strncat_chk(v11, s, v10, 50LL);\n __strcpy_chk(s, v12, 50LL);\n } else {\n v3 = (int)v2 >> 1;\n if ((int)v2 >> 1) {\n v4 = s;\n v5 = &s[v2 - 1];\n v6 = &s[v3];\n do {\n v7 = *v5;\n v8 = *v4++;\n --v5;\n *(v4 - 1) = v7;\n v5[1] = v8;\n } while (v4 != v6);\n }\n }\n return s;\n}", + "ida_pseudo_norm": "char *func0(unsigned int a1, int a2) {\n unsigned int v2;\n int v3;\n char *v4;\n char *v5;\n char *v6;\n char v7;\n char v8;\n unsigned int v10;\n long long v11;\n long long v12;\n uint8_t v13[56];\n unsigned long long v14;\n v14 = __readfsqword(40u);\n __sprintf_chk(xs_1, 2LL, 50LL, &unk_2004, a1);\n v2 = strlen(xs_1);\n if ((int)v2 >= a2) {\n v10 = v2 - a2;\n v11 = __strcpy_chk(v13, &xs_1[v10], 50LL);\n v13[a2] = 0;\n v12 = __strncat_chk(v11, xs_1, v10, 50LL);\n __strcpy_chk(xs_1, v12, 50LL);\n } else {\n v3 = (int)v2 >> 1;\n if ((int)v2 >> 1) {\n v4 = xs_1;\n v5 = &xs_1[v2 - 1];\n v6 = &xs_1[v3];\n do {\n v7 = *v5;\n v8 = *v4++;\n --v5;\n *(v4 - 1) = v7;\n v5[1] = v8;\n } while (v4 != v6);\n }\n }\n return xs_1;\n}" + }, + { + "index": "HumanEval-C-66", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(const char *s) {\n int sum = 0;\n for (int i = 0; s[i] != '\\0'; i++)\n if (s[i] >= 'A' && s[i] <= 'Z') sum += s[i];\n return sum;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"\") == 0);\n assert(func0(\"abAB\") == 131);\n assert(func0(\"abcCd\") == 67);\n assert(func0(\"helloE\") == 69);\n assert(func0(\"woArBld\") == 131);\n assert(func0(\"aAaaaXa\") == 153);\n assert(func0(\" How are yOu?\") == 151);\n assert(func0(\"You arE Very Smart\") == 327);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11A7\nloc_1165:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 40h ; '@'\njle short loc_11A3\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 5Ah ; 'Z'\njg short loc_11A3\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nadd [rbp+var_8], eax\nloc_11A3:\nadd [rbp+var_4], 1\nloc_11A7:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1165\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1)\n{\n unsigned int v2; // [rsp+10h] [rbp-8h]\n int i; // [rsp+14h] [rbp-4h]\n\n v2 = 0;\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n {\n if ( *(char *)(i + a1) > 64 && *(char *)(i + a1) <= 90 )\n v2 += *(char *)(i + a1);\n }\n return v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11A7\nloc_1165:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 40h ; '@'\njle short loc_11A3\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 5Ah ; 'Z'\njg short loc_11A3\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nadd [rbp+var_8], eax\nloc_11A3:\nadd [rbp+var_4], 1\nloc_11A7:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1165\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(__int64 a1)\n{\n unsigned int v2; // [rsp+10h] [rbp-8h]\n int i; // [rsp+14h] [rbp-4h]\n\n v2 = 0;\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n {\n if ( *(char *)(i + a1) > 64 && *(char *)(i + a1) <= 90 )\n v2 += *(char *)(i + a1);\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(long long a1) {\n unsigned int v2;\n int i;\n v2 = 0;\n for (i = 0; *(uint8_t *)(i + a1); ++i) {\n if (*(char *)(i + a1) > 64 && *(char *)(i + a1) <= 90)\n v2 += *(char *)(i + a1);\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(long long a1) {\n unsigned int v2;\n int i;\n v2 = 0;\n for (i = 0; *(uint8_t *)(i + a1); ++i) {\n if (*(char *)(i + a1) > 64 && *(char *)(i + a1) <= 90)\n v2 += *(char *)(i + a1);\n }\n return v2;\n}" + }, + { + "index": "HumanEval-C-66", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(const char *s) {\n int sum = 0;\n for (int i = 0; s[i] != '\\0'; i++)\n if (s[i] >= 'A' && s[i] <= 'Z') sum += s[i];\n return sum;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"\") == 0);\n assert(func0(\"abAB\") == 131);\n assert(func0(\"abcCd\") == 67);\n assert(func0(\"helloE\") == 69);\n assert(func0(\"woArBld\") == 131);\n assert(func0(\"aAaaaXa\") == 153);\n assert(func0(\" How are yOu?\") == 151);\n assert(func0(\"You arE Very Smart\") == 327);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmovzx eax, byte ptr [rdi]\ntest al, al\njz short loc_117A\nadd rdi, 1\nmov edx, 0\nloc_115D:\nlea ecx, [rax-41h]\nmovsx eax, al\nadd eax, edx\ncmp cl, 1Ah\ncmovb edx, eax\nadd rdi, 1\nmovzx eax, byte ptr [rdi-1]\ntest al, al\njnz short loc_115D\nloc_1177:\nmov eax, edx\nretn\nloc_117A:\nmov edx, 0\njmp short loc_1177", + "ida_pseudo": "__int64 __fastcall func0(char *a1)\n{\n char v1; // al\n char *v2; // rdi\n unsigned int v3; // edx\n unsigned __int8 v4; // cl\n unsigned int v5; // eax\n\n v1 = *a1;\n if ( *a1 )\n {\n v2 = a1 + 1;\n v3 = 0;\n do\n {\n v4 = v1 - 65;\n v5 = v3 + v1;\n if ( v4 < 0x1Au )\n v3 = v5;\n v1 = *v2++;\n }\n while ( v1 );\n }\n else\n {\n return 0;\n }\n return v3;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmovzx eax, byte ptr [rdi]\ntest al, al\njz short loc_117A\nadd rdi, 1\nmov edx, 0\nloc_115D:\nlea ecx, [rax-41h]\nmovsx eax, al\nadd eax, edx\ncmp cl, 1Ah\ncmovb edx, eax\nadd rdi, 1\nmovzx eax, byte ptr [rdi-1]\ntest al, al\njnz short loc_115D\nloc_1177:\nmov eax, edx\nretn\nloc_117A:\nmov edx, 0\njmp short loc_1177", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(char *a1)\n{\n char v1; // al\n char *v2; // rdi\n unsigned int v3; // edx\n unsigned __int8 v4; // cl\n unsigned int v5; // eax\n\n v1 = *a1;\n if ( *a1 )\n {\n v2 = a1 + 1;\n v3 = 0;\n do\n {\n v4 = v1 - 65;\n v5 = v3 + v1;\n if ( v4 < 0x1Au )\n v3 = v5;\n v1 = *v2++;\n }\n while ( v1 );\n }\n else\n {\n return 0;\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(char *a1) {\n char v1;\n char *v2;\n unsigned int v3;\n unsigned char v4;\n unsigned int v5;\n v1 = *a1;\n if (*a1) {\n v2 = a1 + 1;\n v3 = 0;\n do {\n v4 = v1 - 65;\n v5 = v3 + v1;\n if (v4 < 26u) v3 = v5;\n v1 = *v2++;\n } while (v1);\n } else {\n return 0;\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(char *a1) {\n char v1;\n char *v2;\n unsigned int v3;\n unsigned char v4;\n unsigned int v5;\n v1 = *a1;\n if (*a1) {\n v2 = a1 + 1;\n v3 = 0;\n do {\n v4 = v1 - 65;\n v5 = v3 + v1;\n if (v4 < 26u) v3 = v5;\n v1 = *v2++;\n } while (v1);\n } else {\n return 0;\n }\n return v3;\n}" + }, + { + "index": "HumanEval-C-67", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int func0(const char *s, int n) {\n char num1[10] = \"\";\n char num2[10] = \"\";\n int is12 = 0, j = 0;\n for (int i = 0; s[i] != '\\0'; i++) {\n if (isdigit(s[i])) {\n if (is12 == 0) {\n num1[j++] = s[i];\n } else {\n num2[j++] = s[i];\n }\n } else {\n if (is12 == 0 && j > 0) {\n is12 = 1;\n j = 0;\n }\n }\n }\n return n - atoi(num1) - atoi(num2);\n}", + "test": "#include \n\nint main() {\n assert(func0(\"5 apples and 6 oranges\", 19) == 8);\n assert(func0(\"5 apples and 6 oranges\", 21) == 10);\n assert(func0(\"0 apples and 1 oranges\", 3) == 2);\n assert(func0(\"1 apples and 0 oranges\", 3) == 2);\n assert(func0(\"2 apples and 3 oranges\", 100) == 95);\n assert(func0(\"2 apples and 3 oranges\", 5) == 0);\n assert(func0(\"1 apples and 100 oranges\", 120) == 19);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 48h\nmov [rbp+var_48], rdi\nmov [rbp+var_4C], esi\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov qword ptr [rbp+nptr], 0\nmov [rbp+var_24], 0\nmov qword ptr [rbp+var_22], 0\nmov [rbp+var_1A], 0\nmov [rbp+var_38], 0\nmov [rbp+var_34], 0\nmov [rbp+var_30], 0\njmp loc_129B\nloc_1202:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_30]\nmovsxd rcx, edx\nmov rdx, [rbp+var_48]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 800h\ntest eax, eax\njz short loc_127D\ncmp [rbp+var_38], 0\njnz short loc_125B\nmov eax, [rbp+var_30]\nmovsxd rdx, eax\nmov rax, [rbp+var_48]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_34]\nlea edx, [rax+1]\nmov [rbp+var_34], edx\nmovzx edx, byte ptr [rcx]\ncdqe\nmov [rbp+rax+nptr], dl\njmp short loc_1297\nloc_125B:\nmov eax, [rbp+var_30]\nmovsxd rdx, eax\nmov rax, [rbp+var_48]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_34]\nlea edx, [rax+1]\nmov [rbp+var_34], edx\nmovzx edx, byte ptr [rcx]\ncdqe\nmov [rbp+rax+var_22], dl\njmp short loc_1297\nloc_127D:\ncmp [rbp+var_38], 0\njnz short loc_1297\ncmp [rbp+var_34], 0\njle short loc_1297\nmov [rbp+var_38], 1\nmov [rbp+var_34], 0\nloc_1297:\nadd [rbp+var_30], 1\nloc_129B:\nmov eax, [rbp+var_30]\nmovsxd rdx, eax\nmov rax, [rbp+var_48]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_1202\nlea rax, [rbp+nptr]\nmov rdi, rax; nptr\ncall _atoi\nmov edx, [rbp+var_4C]\nmov ebx, edx\nsub ebx, eax\nlea rax, [rbp+var_22]\nmov rdi, rax; nptr\ncall _atoi\nsub ebx, eax\nmov edx, ebx\nmov eax, edx\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njz short loc_12EC\ncall ___stack_chk_fail\nloc_12EC:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int v2; // eax\n int v3; // ebx\n int v5; // [rsp+18h] [rbp-38h]\n int v6; // [rsp+1Ch] [rbp-34h]\n int i; // [rsp+20h] [rbp-30h]\n char nptr[8]; // [rsp+24h] [rbp-2Ch] BYREF\n __int16 v9; // [rsp+2Ch] [rbp-24h]\n char v10[8]; // [rsp+2Eh] [rbp-22h] BYREF\n __int16 v11; // [rsp+36h] [rbp-1Ah]\n unsigned __int64 v12; // [rsp+38h] [rbp-18h]\n\n v12 = __readfsqword(0x28u);\n *(_QWORD *)nptr = 0LL;\n v9 = 0;\n *(_QWORD *)v10 = 0LL;\n v11 = 0;\n v5 = 0;\n v6 = 0;\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n {\n if ( ((*__ctype_b_loc())[*(char *)(i + a1)] & 0x800) != 0 )\n {\n v2 = v6++;\n if ( v5 )\n v10[v2] = *(_BYTE *)(i + a1);\n else\n nptr[v2] = *(_BYTE *)(i + a1);\n }\n else if ( !v5 && v6 > 0 )\n {\n v5 = 1;\n v6 = 0;\n }\n }\n v3 = a2 - atoi(nptr);\n return (unsigned int)(v3 - atoi(v10));\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 48h\nmov [rbp+var_48], rdi\nmov [rbp+var_4C], esi\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov qword ptr [rbp+nptr], 0\nmov [rbp+var_24], 0\nmov qword ptr [rbp+var_22], 0\nmov [rbp+var_1A], 0\nmov [rbp+var_38], 0\nmov [rbp+var_34], 0\nmov [rbp+var_30], 0\njmp loc_129B\nloc_1202:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_30]\nmovsxd rcx, edx\nmov rdx, [rbp+var_48]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 800h\ntest eax, eax\njz short loc_127D\ncmp [rbp+var_38], 0\njnz short loc_125B\nmov eax, [rbp+var_30]\nmovsxd rdx, eax\nmov rax, [rbp+var_48]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_34]\nlea edx, [rax+1]\nmov [rbp+var_34], edx\nmovzx edx, byte ptr [rcx]\ncdqe\nmov [rbp+rax+nptr], dl\njmp short loc_1297\nloc_125B:\nmov eax, [rbp+var_30]\nmovsxd rdx, eax\nmov rax, [rbp+var_48]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_34]\nlea edx, [rax+1]\nmov [rbp+var_34], edx\nmovzx edx, byte ptr [rcx]\ncdqe\nmov [rbp+rax+var_22], dl\njmp short loc_1297\nloc_127D:\ncmp [rbp+var_38], 0\njnz short loc_1297\ncmp [rbp+var_34], 0\njle short loc_1297\nmov [rbp+var_38], 1\nmov [rbp+var_34], 0\nloc_1297:\nadd [rbp+var_30], 1\nloc_129B:\nmov eax, [rbp+var_30]\nmovsxd rdx, eax\nmov rax, [rbp+var_48]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_1202\nlea rax, [rbp+nptr]\nmov rdi, rax; nptr\ncall _atoi\nmov edx, [rbp+var_4C]\nmov ebx, edx\nsub ebx, eax\nlea rax, [rbp+var_22]\nmov rdi, rax; nptr\ncall _atoi\nsub ebx, eax\nmov edx, ebx\nmov eax, edx\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njz short loc_12EC\ncall ___stack_chk_fail\nloc_12EC:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(__int64 a1, int a2)\n{\n int v2; // eax\n int v3; // ebx\n int v5; // [rsp+18h] [rbp-38h]\n int v6; // [rsp+1Ch] [rbp-34h]\n int i; // [rsp+20h] [rbp-30h]\n char nptr[8]; // [rsp+24h] [rbp-2Ch] BYREF\n __int16 v9; // [rsp+2Ch] [rbp-24h]\n char v10[8]; // [rsp+2Eh] [rbp-22h] BYREF\n __int16 v11; // [rsp+36h] [rbp-1Ah]\n unsigned __int64 v12; // [rsp+38h] [rbp-18h]\n\n v12 = __readfsqword(0x28u);\n *(_QWORD *)nptr = 0LL;\n v9 = 0;\n *(_QWORD *)v10 = 0LL;\n v11 = 0;\n v5 = 0;\n v6 = 0;\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n {\n if ( ((*__ctype_b_loc())[*(char *)(i + a1)] & 0x800) != 0 )\n {\n v2 = v6++;\n if ( v5 )\n v10[v2] = *(_BYTE *)(i + a1);\n else\n nptr[v2] = *(_BYTE *)(i + a1);\n }\n else if ( !v5 && v6 > 0 )\n {\n v5 = 1;\n v6 = 0;\n }\n }\n v3 = a2 - atoi(nptr);\n return (unsigned int)(v3 - atoi(v10));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(long long a1, int a2) {\n int v2;\n int v3;\n int v5;\n int v6;\n int i;\n char nptr[8];\n short v9;\n char v10[8];\n short v11;\n unsigned long long v12;\n v12 = __readfsqword(40u);\n *(uint64_t *)nptr = 0LL;\n v9 = 0;\n *(uint64_t *)v10 = 0LL;\n v11 = 0;\n v5 = 0;\n v6 = 0;\n for (i = 0; *(uint8_t *)(i + a1); ++i) {\n if (((*__ctype_b_loc())[*(char *)(i + a1)] & 2048) != 0) {\n v2 = v6++;\n if (v5)\n v10[v2] = *(uint8_t *)(i + a1);\n else\n nptr[v2] = *(uint8_t *)(i + a1);\n } else if (!v5 && v6 > 0) {\n v5 = 1;\n v6 = 0;\n }\n }\n v3 = a2 - atoi(nptr);\n return (unsigned int)(v3 - atoi(v10));\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int v2;\n int v3;\n int v5;\n int v6;\n int i;\n char nptr[8];\n short v9;\n char v10[8];\n short v11;\n unsigned long long v12;\n v12 = __readfsqword(40u);\n *(uint64_t *)nptr = 0LL;\n v9 = 0;\n *(uint64_t *)v10 = 0LL;\n v11 = 0;\n v5 = 0;\n v6 = 0;\n for (i = 0; *(uint8_t *)(i + a1); ++i) {\n if (((*__ctype_b_loc())[*(char *)(i + a1)] & 2048) != 0) {\n v2 = v6++;\n if (v5)\n v10[v2] = *(uint8_t *)(i + a1);\n else\n nptr[v2] = *(uint8_t *)(i + a1);\n } else if (!v5 && v6 > 0) {\n v5 = 1;\n v6 = 0;\n }\n }\n v3 = a2 - atoi(nptr);\n return (unsigned int)(v3 - atoi(v10));\n}" + }, + { + "index": "HumanEval-C-67", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int func0(const char *s, int n) {\n char num1[10] = \"\";\n char num2[10] = \"\";\n int is12 = 0, j = 0;\n for (int i = 0; s[i] != '\\0'; i++) {\n if (isdigit(s[i])) {\n if (is12 == 0) {\n num1[j++] = s[i];\n } else {\n num2[j++] = s[i];\n }\n } else {\n if (is12 == 0 && j > 0) {\n is12 = 1;\n j = 0;\n }\n }\n }\n return n - atoi(num1) - atoi(num2);\n}", + "test": "#include \n\nint main() {\n assert(func0(\"5 apples and 6 oranges\", 19) == 8);\n assert(func0(\"5 apples and 6 oranges\", 21) == 10);\n assert(func0(\"0 apples and 1 oranges\", 3) == 2);\n assert(func0(\"1 apples and 0 oranges\", 3) == 2);\n assert(func0(\"2 apples and 3 oranges\", 100) == 95);\n assert(func0(\"2 apples and 3 oranges\", 5) == 0);\n assert(func0(\"1 apples and 100 oranges\", 120) == 19);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 20h\nmov r12d, esi\nmov rax, fs:28h\nmov [rsp+38h+var_20], rax\nxor eax, eax\nmov qword ptr [rsp+38h+nptr], 0\nmov [rsp+38h+var_2C], 0\nmov qword ptr [rsp+38h+var_2A], 0\nmov [rsp+38h+var_22], 0\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_125E\nmov rbp, rdi\ncall ___ctype_b_loc\nmov rdi, [rax]\nlea rdx, [rbp+1]\nmov ecx, 0\nmov eax, 0\nmov r9d, 0\nmov r8d, 1\njmp short loc_1243\nloc_1216:\nmovsxd rsi, ecx\nmov [rsp+rsi+38h+var_2A], bl\nlea ecx, [rcx+1]\njmp short loc_1237\nloc_1222:\ntest eax, eax\njnz short loc_1237\ntest ecx, ecx\nsetnle sil\ntest sil, sil\ncmovnz ecx, r9d\ncmovnz eax, r8d\nloc_1237:\nadd rdx, 1\nmovzx ebx, byte ptr [rdx-1]\ntest bl, bl\njz short loc_125E\nloc_1243:\nmovsx rsi, bl\ntest byte ptr [rdi+rsi*2+1], 8\njz short loc_1222\ntest eax, eax\njnz short loc_1216\nmovsxd rsi, ecx\nmov [rsp+rsi+38h+nptr], bl\nlea ecx, [rcx+1]\njmp short loc_1237\nloc_125E:\nlea rdi, [rsp+38h+nptr]; nptr\nmov edx, 0Ah; base\nmov esi, 0; endptr\ncall _strtol\nsub r12d, eax\nlea rdi, [rsp+38h+var_2A]; nptr\nmov edx, 0Ah; base\nmov esi, 0; endptr\ncall _strtol\nsub r12d, eax\nmov rax, [rsp+38h+var_20]\nsub rax, fs:28h\njnz short loc_12A8\nmov eax, r12d\nadd rsp, 20h\npop rbx\npop rbp\npop r12\nretn\nloc_12A8:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(char *a1, int a2)\n{\n char v2; // bl\n const unsigned __int16 *v4; // rdi\n char *v5; // rdx\n int v6; // ecx\n int v7; // eax\n int v8; // r12d\n char nptr[8]; // [rsp+4h] [rbp-34h] BYREF\n __int16 v11; // [rsp+Ch] [rbp-2Ch]\n char v12[8]; // [rsp+Eh] [rbp-2Ah] BYREF\n __int16 v13; // [rsp+16h] [rbp-22h]\n unsigned __int64 v14; // [rsp+18h] [rbp-20h]\n\n v14 = __readfsqword(0x28u);\n *(_QWORD *)nptr = 0LL;\n v11 = 0;\n *(_QWORD *)v12 = 0LL;\n v13 = 0;\n v2 = *a1;\n if ( *a1 )\n {\n v4 = *__ctype_b_loc();\n v5 = a1 + 1;\n v6 = 0;\n v7 = 0;\n do\n {\n if ( (v4[v2] & 0x800) != 0 )\n {\n if ( v7 )\n v12[v6] = v2;\n else\n nptr[v6] = v2;\n ++v6;\n }\n else if ( !v7 && v6 > 0 )\n {\n v6 = 0;\n v7 = 1;\n }\n v2 = *v5++;\n }\n while ( v2 );\n }\n v8 = a2 - strtol(nptr, 0LL, 10);\n return v8 - (unsigned int)strtol(v12, 0LL, 10);\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 20h\nmov r12d, esi\nmov rax, fs:28h\nmov [rsp+38h+var_20], rax\nxor eax, eax\nmov qword ptr [rsp+38h+nptr], 0\nmov [rsp+38h+var_2C], 0\nmov qword ptr [rsp+38h+var_2A], 0\nmov [rsp+38h+var_22], 0\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_125E\nmov rbp, rdi\ncall ___ctype_b_loc\nmov rdi, [rax]\nlea rdx, [rbp+1]\nmov ecx, 0\nmov eax, 0\nmov r9d, 0\nmov r8d, 1\njmp short loc_1243\nloc_1216:\nmovsxd rsi, ecx\nmov [rsp+rsi+38h+var_2A], bl\nlea ecx, [rcx+1]\njmp short loc_1237\nloc_1222:\ntest eax, eax\njnz short loc_1237\ntest ecx, ecx\nsetnle sil\ntest sil, sil\ncmovnz ecx, r9d\ncmovnz eax, r8d\nloc_1237:\nadd rdx, 1\nmovzx ebx, byte ptr [rdx-1]\ntest bl, bl\njz short loc_125E\nloc_1243:\nmovsx rsi, bl\ntest byte ptr [rdi+rsi*2+1], 8\njz short loc_1222\ntest eax, eax\njnz short loc_1216\nmovsxd rsi, ecx\nmov [rsp+rsi+38h+nptr], bl\nlea ecx, [rcx+1]\njmp short loc_1237\nloc_125E:\nlea rdi, [rsp+38h+nptr]; nptr\nmov edx, 0Ah; base\nmov esi, 0; endptr\ncall _strtol\nsub r12d, eax\nlea rdi, [rsp+38h+var_2A]; nptr\nmov edx, 0Ah; base\nmov esi, 0; endptr\ncall _strtol\nsub r12d, eax\nmov rax, [rsp+38h+var_20]\nsub rax, fs:28h\njnz short loc_12A8\nmov eax, r12d\nadd rsp, 20h\npop rbx\npop rbp\npop r12\nretn\nloc_12A8:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(char *a1, int a2)\n{\n char v2; // bl\n const unsigned __int16 *v4; // rdi\n char *v5; // rdx\n int v6; // ecx\n int v7; // eax\n int v8; // r12d\n char nptr[8]; // [rsp+4h] [rbp-34h] BYREF\n __int16 v11; // [rsp+Ch] [rbp-2Ch]\n char v12[8]; // [rsp+Eh] [rbp-2Ah] BYREF\n __int16 v13; // [rsp+16h] [rbp-22h]\n unsigned __int64 v14; // [rsp+18h] [rbp-20h]\n\n v14 = __readfsqword(0x28u);\n *(_QWORD *)nptr = 0LL;\n v11 = 0;\n *(_QWORD *)v12 = 0LL;\n v13 = 0;\n v2 = *a1;\n if ( *a1 )\n {\n v4 = *__ctype_b_loc();\n v5 = a1 + 1;\n v6 = 0;\n v7 = 0;\n do\n {\n if ( (v4[v2] & 0x800) != 0 )\n {\n if ( v7 )\n v12[v6] = v2;\n else\n nptr[v6] = v2;\n ++v6;\n }\n else if ( !v7 && v6 > 0 )\n {\n v6 = 0;\n v7 = 1;\n }\n v2 = *v5++;\n }\n while ( v2 );\n }\n v8 = a2 - strtol(nptr, 0LL, 10);\n return v8 - (unsigned int)strtol(v12, 0LL, 10);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(char *a1, int a2) {\n char v2;\n const unsigned short *v4;\n char *v5;\n int v6;\n int v7;\n int v8;\n char nptr[8];\n short v11;\n char v12[8];\n short v13;\n unsigned long long v14;\n v14 = __readfsqword(40u);\n *(uint64_t *)nptr = 0LL;\n v11 = 0;\n *(uint64_t *)v12 = 0LL;\n v13 = 0;\n v2 = *a1;\n if (*a1) {\n v4 = *__ctype_b_loc();\n v5 = a1 + 1;\n v6 = 0;\n v7 = 0;\n do {\n if ((v4[v2] & 2048) != 0) {\n if (v7)\n v12[v6] = v2;\n else\n nptr[v6] = v2;\n ++v6;\n } else if (!v7 && v6 > 0) {\n v6 = 0;\n v7 = 1;\n }\n v2 = *v5++;\n } while (v2);\n }\n v8 = a2 - strtol(nptr, 0LL, 10);\n return v8 - (unsigned int)strtol(v12, 0LL, 10);\n}", + "ida_pseudo_norm": "long long func0(char *a1, int a2) {\n char v2;\n const unsigned short *v4;\n char *v5;\n int v6;\n int v7;\n int v8;\n char nptr[8];\n short v11;\n char v12[8];\n short v13;\n unsigned long long v14;\n v14 = __readfsqword(40u);\n *(uint64_t *)nptr = 0LL;\n v11 = 0;\n *(uint64_t *)v12 = 0LL;\n v13 = 0;\n v2 = *a1;\n if (*a1) {\n v4 = *__ctype_b_loc();\n v5 = a1 + 1;\n v6 = 0;\n v7 = 0;\n do {\n if ((v4[v2] & 2048) != 0) {\n if (v7)\n v12[v6] = v2;\n else\n nptr[v6] = v2;\n ++v6;\n } else if (!v7 && v6 > 0) {\n v6 = 0;\n v7 = 1;\n }\n v2 = *v5++;\n } while (v2);\n }\n v8 = a2 - strtol(nptr, 0LL, 10);\n return v8 - (unsigned int)strtol(v12, 0LL, 10);\n}" + }, + { + "index": "HumanEval-C-67", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int func0(const char *s, int n) {\n char num1[10] = \"\";\n char num2[10] = \"\";\n int is12 = 0, j = 0;\n for (int i = 0; s[i] != '\\0'; i++) {\n if (isdigit(s[i])) {\n if (is12 == 0) {\n num1[j++] = s[i];\n } else {\n num2[j++] = s[i];\n }\n } else {\n if (is12 == 0 && j > 0) {\n is12 = 1;\n j = 0;\n }\n }\n }\n return n - atoi(num1) - atoi(num2);\n}", + "test": "#include \n\nint main() {\n assert(func0(\"5 apples and 6 oranges\", 19) == 8);\n assert(func0(\"5 apples and 6 oranges\", 21) == 10);\n assert(func0(\"0 apples and 1 oranges\", 3) == 2);\n assert(func0(\"1 apples and 0 oranges\", 3) == 2);\n assert(func0(\"2 apples and 3 oranges\", 100) == 95);\n assert(func0(\"2 apples and 3 oranges\", 5) == 0);\n assert(func0(\"1 apples and 100 oranges\", 120) == 19);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r12\nxor edx, edx\nmov r12d, esi\npush rbp\npush rbx\nsub rsp, 20h\nmovzx ebx, byte ptr [rdi]\nmov rax, fs:28h\nmov [rsp+38h+var_20], rax\nxor eax, eax\nxor eax, eax\nmov [rsp+38h+var_22], dx\nmov qword ptr [rsp+38h+nptr], 0\nmov [rsp+38h+var_2C], ax\nmov qword ptr [rsp+38h+var_2A], 0\ntest bl, bl\njz short loc_13EE\nmov rbp, rdi\ncall ___ctype_b_loc\nlea rdi, [rbp+1]\nxor edx, edx\nxor r9d, r9d\nmov rsi, [rax]\nmov r8d, 1\nxor eax, eax\njmp short loc_13C5\nloc_13A8:\nmovsxd rcx, edx\ntest eax, eax\njnz loc_1438\nmov [rsp+rcx+38h+nptr], bl\nadd edx, 1\nloc_13BA:\nmovzx ebx, byte ptr [rdi]\nadd rdi, 1\ntest bl, bl\njz short loc_13EE\nloc_13C5:\nmovsx rcx, bl\ntest byte ptr [rsi+rcx*2+1], 8\njnz short loc_13A8\ntest al, 1\njnz short loc_13BA\ntest edx, edx\nsetnle cl\ntest cl, cl\ncmovnz edx, r9d\ncmovnz eax, r8d\nmovzx ebx, byte ptr [rdi]\nadd rdi, 1\ntest bl, bl\njnz short loc_13C5\nloc_13EE:\nlea rdi, [rsp+38h+nptr]; nptr\nmov edx, 0Ah; base\nxor esi, esi; endptr\ncall _strtol\nlea rdi, [rsp+38h+var_2A]; nptr\nmov edx, 0Ah; base\nxor esi, esi; endptr\nsub r12d, eax\ncall _strtol\nsub r12d, eax\nmov rax, [rsp+38h+var_20]\nsub rax, fs:28h\njnz short loc_1444\nadd rsp, 20h\nmov eax, r12d\npop rbx\npop rbp\npop r12\nretn\nloc_1438:\nmov [rsp+rcx+38h+var_2A], bl\nadd edx, 1\njmp loc_13BA\nloc_1444:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(char *a1, int a2)\n{\n char v3; // bl\n const unsigned __int16 **v4; // rax\n char *v5; // rdi\n int v6; // edx\n const unsigned __int16 *v7; // rsi\n int v8; // eax\n int v9; // r12d\n char nptr[8]; // [rsp+4h] [rbp-34h] BYREF\n __int16 v12; // [rsp+Ch] [rbp-2Ch]\n char v13[8]; // [rsp+Eh] [rbp-2Ah] BYREF\n __int16 v14; // [rsp+16h] [rbp-22h]\n unsigned __int64 v15; // [rsp+18h] [rbp-20h]\n\n v3 = *a1;\n v15 = __readfsqword(0x28u);\n v14 = 0;\n *(_QWORD *)nptr = 0LL;\n v12 = 0;\n *(_QWORD *)v13 = 0LL;\n if ( v3 )\n {\n v4 = __ctype_b_loc();\n v5 = a1 + 1;\n v6 = 0;\n v7 = *v4;\n v8 = 0;\n while ( (v7[v3] & 0x800) == 0 )\n {\n if ( (v8 & 1) != 0 )\n {\nLABEL_6:\n v3 = *v5++;\n if ( !v3 )\n goto LABEL_12;\n }\n else\n {\n if ( v6 > 0 )\n {\n v6 = 0;\n v8 = 1;\n }\n v3 = *v5++;\n if ( !v3 )\n goto LABEL_12;\n }\n }\n if ( v8 )\n v13[v6] = v3;\n else\n nptr[v6] = v3;\n ++v6;\n goto LABEL_6;\n }\nLABEL_12:\n v9 = a2 - strtol(nptr, 0LL, 10);\n return v9 - (unsigned int)strtol(v13, 0LL, 10);\n}", + "ida_strip_asm": "sub_1340:\nendbr64\npush r12\nxor edx, edx\nmov r12d, esi\npush rbp\npush rbx\nsub rsp, 20h\nmovzx ebx, byte ptr [rdi]\nmov rax, fs:28h\nmov [rsp+38h+var_20], rax\nxor eax, eax\nxor eax, eax\nmov [rsp+38h+var_22], dx\nmov qword ptr [rsp+38h+nptr], 0\nmov [rsp+38h+var_2C], ax\nmov qword ptr [rsp+38h+var_2A], 0\ntest bl, bl\njz short loc_13EE\nmov rbp, rdi\ncall ___ctype_b_loc\nlea rdi, [rbp+1]\nxor edx, edx\nxor r9d, r9d\nmov rsi, [rax]\nmov r8d, 1\nxor eax, eax\njmp short loc_13C5\nloc_13A8:\nmovsxd rcx, edx\ntest eax, eax\njnz loc_1438\nmov [rsp+rcx+38h+nptr], bl\nadd edx, 1\nloc_13BA:\nmovzx ebx, byte ptr [rdi]\nadd rdi, 1\ntest bl, bl\njz short loc_13EE\nloc_13C5:\nmovsx rcx, bl\ntest byte ptr [rsi+rcx*2+1], 8\njnz short loc_13A8\ntest al, 1\njnz short loc_13BA\ntest edx, edx\nsetnle cl\ntest cl, cl\ncmovnz edx, r9d\ncmovnz eax, r8d\nmovzx ebx, byte ptr [rdi]\nadd rdi, 1\ntest bl, bl\njnz short loc_13C5\nloc_13EE:\nlea rdi, [rsp+38h+nptr]; nptr\nmov edx, 0Ah; base\nxor esi, esi; endptr\ncall _strtol\nlea rdi, [rsp+38h+var_2A]; nptr\nmov edx, 0Ah; base\nxor esi, esi; endptr\nsub r12d, eax\ncall _strtol\nsub r12d, eax\nmov rax, [rsp+38h+var_20]\nsub rax, fs:28h\njnz short loc_1444\nadd rsp, 20h\nmov eax, r12d\npop rbx\npop rbp\npop r12\nretn\nloc_1438:\nmov [rsp+rcx+38h+var_2A], bl\nadd edx, 1\njmp loc_13BA\nloc_1444:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1340(char *a1, int a2)\n{\n char v3; // bl\n const unsigned __int16 **v4; // rax\n char *v5; // rdi\n int v6; // edx\n const unsigned __int16 *v7; // rsi\n int v8; // eax\n int v9; // r12d\n char nptr[8]; // [rsp+4h] [rbp-34h] BYREF\n __int16 v12; // [rsp+Ch] [rbp-2Ch]\n char v13[8]; // [rsp+Eh] [rbp-2Ah] BYREF\n __int16 v14; // [rsp+16h] [rbp-22h]\n unsigned __int64 v15; // [rsp+18h] [rbp-20h]\n\n v3 = *a1;\n v15 = __readfsqword(0x28u);\n v14 = 0;\n *(_QWORD *)nptr = 0LL;\n v12 = 0;\n *(_QWORD *)v13 = 0LL;\n if ( v3 )\n {\n v4 = __ctype_b_loc();\n v5 = a1 + 1;\n v6 = 0;\n v7 = *v4;\n v8 = 0;\n while ( (v7[v3] & 0x800) == 0 )\n {\n if ( (v8 & 1) != 0 )\n {\nLABEL_6:\n v3 = *v5++;\n if ( !v3 )\n goto LABEL_12;\n }\n else\n {\n if ( v6 > 0 )\n {\n v6 = 0;\n v8 = 1;\n }\n v3 = *v5++;\n if ( !v3 )\n goto LABEL_12;\n }\n }\n if ( v8 )\n v13[v6] = v3;\n else\n nptr[v6] = v3;\n ++v6;\n goto LABEL_6;\n }\nLABEL_12:\n v9 = a2 - strtol(nptr, 0LL, 10);\n return v9 - (unsigned int)strtol(v13, 0LL, 10);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1340(char *a1, int a2) {\n char v3;\n const unsigned short **v4;\n char *v5;\n int v6;\n const unsigned short *v7;\n int v8;\n int v9;\n char nptr[8];\n short v12;\n char v13[8];\n short v14;\n unsigned long long v15;\n v3 = *a1;\n v15 = __readfsqword(40u);\n v14 = 0;\n *(uint64_t *)nptr = 0LL;\n v12 = 0;\n *(uint64_t *)v13 = 0LL;\n if (v3) {\n v4 = __ctype_b_loc();\n v5 = a1 + 1;\n v6 = 0;\n v7 = *v4;\n v8 = 0;\n while ((v7[v3] & 2048) == 0) {\n if ((v8 & 1) != 0) {\n LABEL_6:\n v3 = *v5++;\n if (!v3) goto LABEL_12;\n } else {\n if (v6 > 0) {\n v6 = 0;\n v8 = 1;\n }\n v3 = *v5++;\n if (!v3) goto LABEL_12;\n }\n }\n if (v8)\n v13[v6] = v3;\n else\n nptr[v6] = v3;\n ++v6;\n goto LABEL_6;\n }\nLABEL_12:\n v9 = a2 - strtol(nptr, 0LL, 10);\n return v9 - (unsigned int)strtol(v13, 0LL, 10);\n}", + "ida_pseudo_norm": "long long func0(char *a1, int a2) {\n char v3;\n const unsigned short **v4;\n char *v5;\n int v6;\n const unsigned short *v7;\n int v8;\n int v9;\n char nptr[8];\n short v12;\n char v13[8];\n short v14;\n unsigned long long v15;\n v3 = *a1;\n v15 = __readfsqword(40u);\n v14 = 0;\n *(uint64_t *)nptr = 0LL;\n v12 = 0;\n *(uint64_t *)v13 = 0LL;\n if (v3) {\n v4 = __ctype_b_loc();\n v5 = a1 + 1;\n v6 = 0;\n v7 = *v4;\n v8 = 0;\n while ((v7[v3] & 2048) == 0) {\n if ((v8 & 1) != 0) {\n LABEL_6:\n v3 = *v5++;\n if (!v3) goto LABEL_12;\n } else {\n if (v6 > 0) {\n v6 = 0;\n v8 = 1;\n }\n v3 = *v5++;\n if (!v3) goto LABEL_12;\n }\n }\n if (v8)\n v13[v6] = v3;\n else\n nptr[v6] = v3;\n ++v6;\n goto LABEL_6;\n }\nLABEL_12:\n v9 = a2 - strtol(nptr, 0LL, 10);\n return v9 - (unsigned int)strtol(v13, 0LL, 10);\n}" + }, + { + "index": "HumanEval-C-67", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int func0(const char *s, int n) {\n char num1[10] = \"\";\n char num2[10] = \"\";\n int is12 = 0, j = 0;\n for (int i = 0; s[i] != '\\0'; i++) {\n if (isdigit(s[i])) {\n if (is12 == 0) {\n num1[j++] = s[i];\n } else {\n num2[j++] = s[i];\n }\n } else {\n if (is12 == 0 && j > 0) {\n is12 = 1;\n j = 0;\n }\n }\n }\n return n - atoi(num1) - atoi(num2);\n}", + "test": "#include \n\nint main() {\n assert(func0(\"5 apples and 6 oranges\", 19) == 8);\n assert(func0(\"5 apples and 6 oranges\", 21) == 10);\n assert(func0(\"0 apples and 1 oranges\", 3) == 2);\n assert(func0(\"1 apples and 0 oranges\", 3) == 2);\n assert(func0(\"2 apples and 3 oranges\", 100) == 95);\n assert(func0(\"2 apples and 3 oranges\", 5) == 0);\n assert(func0(\"1 apples and 100 oranges\", 120) == 19);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r12\nxor edx, edx\nmov r12d, esi\npush rbp\npush rbx\nsub rsp, 20h\nmovzx ebx, byte ptr [rdi]\nmov rax, fs:28h\nmov [rsp+38h+var_20], rax\nxor eax, eax\nxor eax, eax\nmov [rsp+38h+var_22], dx\nmov qword ptr [rsp+38h+nptr], 0\nmov [rsp+38h+var_2C], ax\nmov qword ptr [rsp+38h+var_2A], 0\ntest bl, bl\njz short loc_13EE\nmov rbp, rdi\ncall ___ctype_b_loc\nlea rdi, [rbp+1]\nxor edx, edx\nxor r9d, r9d\nmov rsi, [rax]\nmov r8d, 1\nxor eax, eax\njmp short loc_13C5\nloc_13A8:\nmovsxd rcx, edx\ntest eax, eax\njnz loc_1438\nmov [rsp+rcx+38h+nptr], bl\nadd edx, 1\nloc_13BA:\nmovzx ebx, byte ptr [rdi]\nadd rdi, 1\ntest bl, bl\njz short loc_13EE\nloc_13C5:\nmovsx rcx, bl\ntest byte ptr [rsi+rcx*2+1], 8\njnz short loc_13A8\ntest al, 1\njnz short loc_13BA\ntest edx, edx\nsetnle cl\ntest cl, cl\ncmovnz edx, r9d\ncmovnz eax, r8d\nmovzx ebx, byte ptr [rdi]\nadd rdi, 1\ntest bl, bl\njnz short loc_13C5\nloc_13EE:\nlea rdi, [rsp+38h+nptr]; nptr\nmov edx, 0Ah; base\nxor esi, esi; endptr\ncall _strtol\nlea rdi, [rsp+38h+var_2A]; nptr\nmov edx, 0Ah; base\nxor esi, esi; endptr\nsub r12d, eax\ncall _strtol\nsub r12d, eax\nmov rax, [rsp+38h+var_20]\nsub rax, fs:28h\njnz short loc_1444\nadd rsp, 20h\nmov eax, r12d\npop rbx\npop rbp\npop r12\nretn\nloc_1438:\nmov [rsp+rcx+38h+var_2A], bl\nadd edx, 1\njmp loc_13BA\nloc_1444:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(char *a1, int a2)\n{\n char v3; // bl\n const unsigned __int16 **v4; // rax\n char *v5; // rdi\n int v6; // edx\n const unsigned __int16 *v7; // rsi\n int v8; // eax\n int v9; // r12d\n char nptr[8]; // [rsp+4h] [rbp-34h] BYREF\n __int16 v12; // [rsp+Ch] [rbp-2Ch]\n char v13[8]; // [rsp+Eh] [rbp-2Ah] BYREF\n __int16 v14; // [rsp+16h] [rbp-22h]\n unsigned __int64 v15; // [rsp+18h] [rbp-20h]\n\n v3 = *a1;\n v15 = __readfsqword(0x28u);\n v14 = 0;\n *(_QWORD *)nptr = 0LL;\n v12 = 0;\n *(_QWORD *)v13 = 0LL;\n if ( v3 )\n {\n v4 = __ctype_b_loc();\n v5 = a1 + 1;\n v6 = 0;\n v7 = *v4;\n v8 = 0;\n while ( (v7[v3] & 0x800) == 0 )\n {\n if ( (v8 & 1) != 0 )\n {\nLABEL_6:\n v3 = *v5++;\n if ( !v3 )\n goto LABEL_12;\n }\n else\n {\n if ( v6 > 0 )\n {\n v6 = 0;\n v8 = 1;\n }\n v3 = *v5++;\n if ( !v3 )\n goto LABEL_12;\n }\n }\n if ( v8 )\n v13[v6] = v3;\n else\n nptr[v6] = v3;\n ++v6;\n goto LABEL_6;\n }\nLABEL_12:\n v9 = a2 - strtol(nptr, 0LL, 10);\n return v9 - (unsigned int)strtol(v13, 0LL, 10);\n}", + "ida_strip_asm": "sub_1340:\nendbr64\npush r12\nxor edx, edx\nmov r12d, esi\npush rbp\npush rbx\nsub rsp, 20h\nmovzx ebx, byte ptr [rdi]\nmov rax, fs:28h\nmov [rsp+38h+var_20], rax\nxor eax, eax\nxor eax, eax\nmov [rsp+38h+var_22], dx\nmov qword ptr [rsp+38h+nptr], 0\nmov [rsp+38h+var_2C], ax\nmov qword ptr [rsp+38h+var_2A], 0\ntest bl, bl\njz short loc_13EE\nmov rbp, rdi\ncall ___ctype_b_loc\nlea rdi, [rbp+1]\nxor edx, edx\nxor r9d, r9d\nmov rsi, [rax]\nmov r8d, 1\nxor eax, eax\njmp short loc_13C5\nloc_13A8:\nmovsxd rcx, edx\ntest eax, eax\njnz loc_1438\nmov [rsp+rcx+38h+nptr], bl\nadd edx, 1\nloc_13BA:\nmovzx ebx, byte ptr [rdi]\nadd rdi, 1\ntest bl, bl\njz short loc_13EE\nloc_13C5:\nmovsx rcx, bl\ntest byte ptr [rsi+rcx*2+1], 8\njnz short loc_13A8\ntest al, 1\njnz short loc_13BA\ntest edx, edx\nsetnle cl\ntest cl, cl\ncmovnz edx, r9d\ncmovnz eax, r8d\nmovzx ebx, byte ptr [rdi]\nadd rdi, 1\ntest bl, bl\njnz short loc_13C5\nloc_13EE:\nlea rdi, [rsp+38h+nptr]; nptr\nmov edx, 0Ah; base\nxor esi, esi; endptr\ncall _strtol\nlea rdi, [rsp+38h+var_2A]; nptr\nmov edx, 0Ah; base\nxor esi, esi; endptr\nsub r12d, eax\ncall _strtol\nsub r12d, eax\nmov rax, [rsp+38h+var_20]\nsub rax, fs:28h\njnz short loc_1444\nadd rsp, 20h\nmov eax, r12d\npop rbx\npop rbp\npop r12\nretn\nloc_1438:\nmov [rsp+rcx+38h+var_2A], bl\nadd edx, 1\njmp loc_13BA\nloc_1444:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1340(char *a1, int a2)\n{\n char v3; // bl\n const unsigned __int16 **v4; // rax\n char *v5; // rdi\n int v6; // edx\n const unsigned __int16 *v7; // rsi\n int v8; // eax\n int v9; // r12d\n char nptr[8]; // [rsp+4h] [rbp-34h] BYREF\n __int16 v12; // [rsp+Ch] [rbp-2Ch]\n char v13[8]; // [rsp+Eh] [rbp-2Ah] BYREF\n __int16 v14; // [rsp+16h] [rbp-22h]\n unsigned __int64 v15; // [rsp+18h] [rbp-20h]\n\n v3 = *a1;\n v15 = __readfsqword(0x28u);\n v14 = 0;\n *(_QWORD *)nptr = 0LL;\n v12 = 0;\n *(_QWORD *)v13 = 0LL;\n if ( v3 )\n {\n v4 = __ctype_b_loc();\n v5 = a1 + 1;\n v6 = 0;\n v7 = *v4;\n v8 = 0;\n while ( (v7[v3] & 0x800) == 0 )\n {\n if ( (v8 & 1) != 0 )\n {\nLABEL_6:\n v3 = *v5++;\n if ( !v3 )\n goto LABEL_12;\n }\n else\n {\n if ( v6 > 0 )\n {\n v6 = 0;\n v8 = 1;\n }\n v3 = *v5++;\n if ( !v3 )\n goto LABEL_12;\n }\n }\n if ( v8 )\n v13[v6] = v3;\n else\n nptr[v6] = v3;\n ++v6;\n goto LABEL_6;\n }\nLABEL_12:\n v9 = a2 - strtol(nptr, 0LL, 10);\n return v9 - (unsigned int)strtol(v13, 0LL, 10);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1340(char *a1, int a2) {\n char v3;\n const unsigned short **v4;\n char *v5;\n int v6;\n const unsigned short *v7;\n int v8;\n int v9;\n char nptr[8];\n short v12;\n char v13[8];\n short v14;\n unsigned long long v15;\n v3 = *a1;\n v15 = __readfsqword(40u);\n v14 = 0;\n *(uint64_t *)nptr = 0LL;\n v12 = 0;\n *(uint64_t *)v13 = 0LL;\n if (v3) {\n v4 = __ctype_b_loc();\n v5 = a1 + 1;\n v6 = 0;\n v7 = *v4;\n v8 = 0;\n while ((v7[v3] & 2048) == 0) {\n if ((v8 & 1) != 0) {\n LABEL_6:\n v3 = *v5++;\n if (!v3) goto LABEL_12;\n } else {\n if (v6 > 0) {\n v6 = 0;\n v8 = 1;\n }\n v3 = *v5++;\n if (!v3) goto LABEL_12;\n }\n }\n if (v8)\n v13[v6] = v3;\n else\n nptr[v6] = v3;\n ++v6;\n goto LABEL_6;\n }\nLABEL_12:\n v9 = a2 - strtol(nptr, 0LL, 10);\n return v9 - (unsigned int)strtol(v13, 0LL, 10);\n}", + "ida_pseudo_norm": "long long func0(char *a1, int a2) {\n char v3;\n const unsigned short **v4;\n char *v5;\n int v6;\n const unsigned short *v7;\n int v8;\n int v9;\n char nptr[8];\n short v12;\n char v13[8];\n short v14;\n unsigned long long v15;\n v3 = *a1;\n v15 = __readfsqword(40u);\n v14 = 0;\n *(uint64_t *)nptr = 0LL;\n v12 = 0;\n *(uint64_t *)v13 = 0LL;\n if (v3) {\n v4 = __ctype_b_loc();\n v5 = a1 + 1;\n v6 = 0;\n v7 = *v4;\n v8 = 0;\n while ((v7[v3] & 2048) == 0) {\n if ((v8 & 1) != 0) {\n LABEL_6:\n v3 = *v5++;\n if (!v3) goto LABEL_12;\n } else {\n if (v6 > 0) {\n v6 = 0;\n v8 = 1;\n }\n v3 = *v5++;\n if (!v3) goto LABEL_12;\n }\n }\n if (v8)\n v13[v6] = v3;\n else\n nptr[v6] = v3;\n ++v6;\n goto LABEL_6;\n }\nLABEL_12:\n v9 = a2 - strtol(nptr, 0LL, 10);\n return v9 - (unsigned int)strtol(v13, 0LL, 10);\n}" + }, + { + "index": "HumanEval-C-68", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int *func0(int arr[], int length, int output[2]) {\n int smallestEven = INT_MAX;\n int index = -1;\n for (int i = 0; i < length; ++i) {\n if (arr[i] % 2 == 0 && (arr[i] < smallestEven || index == -1)) {\n smallestEven = arr[i];\n index = i;\n }\n }\n if (index == -1) {\n return NULL;\n }\n output[0] = smallestEven;\n output[1] = index;\n return output;\n}", + "test": "#include \n#include \n#include \n\nint issame(const int *a, const int *b, int a_length, int b_length) {\n if (a_length != b_length) return 0;\n for (int i = 0; i < a_length; ++i) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int output[2];\n int *result;\n \n int test1[] = {4, 2, 3};\n int expect1[] = {2, 1};\n result = func0(test1, 3, output);\n assert(issame(result, expect1, 2, 2));\n\n int test2[] = {1, 2, 3};\n int expect2[] = {2, 1};\n result = func0(test2, 3, output);\n assert(issame(result, expect2, 2, 2));\n\n int test3[] = {};\n result = func0(test3, 0, output);\n assert(result == NULL);\n\n int test4[] = {5, 0, 3, 0, 4, 2};\n int expect4[] = {0, 1};\n result = func0(test4, 6, output);\n assert(issame(result, expect4, 2, 2));\n\n int test5[] = {1, 2, 3, 0, 5, 3};\n int expect5[] = {0, 3};\n result = func0(test5, 6, output);\n assert(issame(result, expect5, 2, 2));\n\n int test6[] = {5, 4, 8, 4, 8};\n int expect6[] = {4, 1};\n result = func0(test6, 5, output);\n assert(issame(result, expect6, 2, 2));\n\n int test7[] = {7, 6, 7, 1};\n int expect7[] = {6, 1};\n result = func0(test7, 4, output);\n assert(issame(result, expect7, 2, 2));\n\n int test8[] = {7, 9, 7, 1};\n result = func0(test8, 4, output);\n assert(result == NULL);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_C], 7FFFFFFFh\nmov [rbp+var_8], 0FFFFFFFFh\nmov [rbp+var_4], 0\njmp short loc_11F4\nloc_1193:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njnz short loc_11F0\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_C], eax\njg short loc_11D1\ncmp [rbp+var_8], 0FFFFFFFFh\njnz short loc_11F0\nloc_11D1:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nmov eax, [rbp+var_4]\nmov [rbp+var_8], eax\nloc_11F0:\nadd [rbp+var_4], 1\nloc_11F4:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1193\ncmp [rbp+var_8], 0FFFFFFFFh\njnz short loc_1209\nmov eax, 0\njmp short loc_1223\nloc_1209:\nmov rax, [rbp+var_28]\nmov edx, [rbp+var_C]\nmov [rax], edx\nmov rax, [rbp+var_28]\nlea rdx, [rax+4]\nmov eax, [rbp+var_8]\nmov [rdx], eax\nmov rax, [rbp+var_28]\nloc_1223:\npop rbp\nretn", + "ida_pseudo": "int *__fastcall func0(__int64 a1, int a2, int *a3)\n{\n int v4; // [rsp+1Ch] [rbp-Ch]\n int v5; // [rsp+20h] [rbp-8h]\n int i; // [rsp+24h] [rbp-4h]\n\n v4 = 0x7FFFFFFF;\n v5 = -1;\n for ( i = 0; i < a2; ++i )\n {\n if ( (*(_DWORD *)(4LL * i + a1) & 1) == 0 && (v4 > *(_DWORD *)(4LL * i + a1) || v5 == -1) )\n {\n v4 = *(_DWORD *)(4LL * i + a1);\n v5 = i;\n }\n }\n if ( v5 == -1 )\n return 0LL;\n *a3 = v4;\n a3[1] = v5;\n return a3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_C], 7FFFFFFFh\nmov [rbp+var_8], 0FFFFFFFFh\nmov [rbp+var_4], 0\njmp short loc_11F4\nloc_1193:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njnz short loc_11F0\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_C], eax\njg short loc_11D1\ncmp [rbp+var_8], 0FFFFFFFFh\njnz short loc_11F0\nloc_11D1:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nmov eax, [rbp+var_4]\nmov [rbp+var_8], eax\nloc_11F0:\nadd [rbp+var_4], 1\nloc_11F4:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1193\ncmp [rbp+var_8], 0FFFFFFFFh\njnz short loc_1209\nmov eax, 0\njmp short loc_1223\nloc_1209:\nmov rax, [rbp+var_28]\nmov edx, [rbp+var_C]\nmov [rax], edx\nmov rax, [rbp+var_28]\nlea rdx, [rax+4]\nmov eax, [rbp+var_8]\nmov [rdx], eax\nmov rax, [rbp+var_28]\nloc_1223:\npop rbp\nretn", + "ida_strip_pseudo": "int *__fastcall sub_1169(__int64 a1, int a2, int *a3)\n{\n int v4; // [rsp+1Ch] [rbp-Ch]\n int v5; // [rsp+20h] [rbp-8h]\n int i; // [rsp+24h] [rbp-4h]\n\n v4 = 0x7FFFFFFF;\n v5 = -1;\n for ( i = 0; i < a2; ++i )\n {\n if ( (*(_DWORD *)(4LL * i + a1) & 1) == 0 && (v4 > *(_DWORD *)(4LL * i + a1) || v5 == -1) )\n {\n v4 = *(_DWORD *)(4LL * i + a1);\n v5 = i;\n }\n }\n if ( v5 == -1 )\n return 0LL;\n *a3 = v4;\n a3[1] = v5;\n return a3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "int *sub_1169(long long a1, int a2, int *a3) {\n int v4;\n int v5;\n int i;\n v4 = 2147483647;\n v5 = -1;\n for (i = 0; i < a2; ++i) {\n if ((*(uint32_t *)(4LL * i + a1) & 1) == 0 &&\n (v4 > *(uint32_t *)(4LL * i + a1) || v5 == -1)) {\n v4 = *(uint32_t *)(4LL * i + a1);\n v5 = i;\n }\n }\n if (v5 == -1) return 0LL;\n *a3 = v4;\n a3[1] = v5;\n return a3;\n}", + "ida_pseudo_norm": "int *func0(long long a1, int a2, int *a3) {\n int v4;\n int v5;\n int i;\n v4 = 2147483647;\n v5 = -1;\n for (i = 0; i < a2; ++i) {\n if ((*(uint32_t *)(4LL * i + a1) & 1) == 0 &&\n (v4 > *(uint32_t *)(4LL * i + a1) || v5 == -1)) {\n v4 = *(uint32_t *)(4LL * i + a1);\n v5 = i;\n }\n }\n if (v5 == -1) return 0LL;\n *a3 = v4;\n a3[1] = v5;\n return a3;\n}" + }, + { + "index": "HumanEval-C-68", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int *func0(int arr[], int length, int output[2]) {\n int smallestEven = INT_MAX;\n int index = -1;\n for (int i = 0; i < length; ++i) {\n if (arr[i] % 2 == 0 && (arr[i] < smallestEven || index == -1)) {\n smallestEven = arr[i];\n index = i;\n }\n }\n if (index == -1) {\n return NULL;\n }\n output[0] = smallestEven;\n output[1] = index;\n return output;\n}", + "test": "#include \n#include \n#include \n\nint issame(const int *a, const int *b, int a_length, int b_length) {\n if (a_length != b_length) return 0;\n for (int i = 0; i < a_length; ++i) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int output[2];\n int *result;\n \n int test1[] = {4, 2, 3};\n int expect1[] = {2, 1};\n result = func0(test1, 3, output);\n assert(issame(result, expect1, 2, 2));\n\n int test2[] = {1, 2, 3};\n int expect2[] = {2, 1};\n result = func0(test2, 3, output);\n assert(issame(result, expect2, 2, 2));\n\n int test3[] = {};\n result = func0(test3, 0, output);\n assert(result == NULL);\n\n int test4[] = {5, 0, 3, 0, 4, 2};\n int expect4[] = {0, 1};\n result = func0(test4, 6, output);\n assert(issame(result, expect4, 2, 2));\n\n int test5[] = {1, 2, 3, 0, 5, 3};\n int expect5[] = {0, 3};\n result = func0(test5, 6, output);\n assert(issame(result, expect5, 2, 2));\n\n int test6[] = {5, 4, 8, 4, 8};\n int expect6[] = {4, 1};\n result = func0(test6, 5, output);\n assert(issame(result, expect6, 2, 2));\n\n int test7[] = {7, 6, 7, 1};\n int expect7[] = {6, 1};\n result = func0(test7, 4, output);\n assert(issame(result, expect7, 2, 2));\n\n int test8[] = {7, 9, 7, 1};\n result = func0(test8, 4, output);\n assert(result == NULL);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11BC\nmovsxd rsi, esi\nmov ecx, 0\nmov r9d, 0FFFFFFFFh\nmov eax, 7FFFFFFFh\njmp short loc_1195\nloc_1186:\nmov r9d, ecx\nmov eax, r8d\nloc_118C:\nadd rcx, 1\ncmp rsi, rcx\njz short loc_11AC\nloc_1195:\nmov r8d, [rdi+rcx*4]\ntest r8b, 1\njnz short loc_118C\ncmp r9d, 0FFFFFFFFh\njz short loc_1186\ncmp r8d, eax\njl short loc_1186\njmp short loc_118C\nloc_11AC:\ncmp r9d, 0FFFFFFFFh\njz short loc_11C2\nmov [rdx], eax\nmov [rdx+4], r9d\nmov rax, rdx\nretn\nloc_11BC:\nmov eax, 0\nretn\nloc_11C2:\nmov eax, 0\nretn", + "ida_pseudo": "int *__fastcall func0(__int64 a1, int a2, int *a3)\n{\n __int64 v3; // rcx\n int v4; // r9d\n int v5; // eax\n int v6; // r8d\n\n if ( a2 <= 0 )\n return 0LL;\n v3 = 0LL;\n v4 = -1;\n v5 = 0x7FFFFFFF;\n do\n {\n v6 = *(_DWORD *)(a1 + 4 * v3);\n if ( (v6 & 1) == 0 && (v4 == -1 || v6 < v5) )\n {\n v4 = v3;\n v5 = *(_DWORD *)(a1 + 4 * v3);\n }\n ++v3;\n }\n while ( a2 != v3 );\n if ( v4 == -1 )\n return 0LL;\n *a3 = v5;\n a3[1] = v4;\n return a3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11BC\nmovsxd rsi, esi\nmov ecx, 0\nmov r9d, 0FFFFFFFFh\nmov eax, 7FFFFFFFh\njmp short loc_1195\nloc_1186:\nmov r9d, ecx\nmov eax, r8d\nloc_118C:\nadd rcx, 1\ncmp rsi, rcx\njz short loc_11AC\nloc_1195:\nmov r8d, [rdi+rcx*4]\ntest r8b, 1\njnz short loc_118C\ncmp r9d, 0FFFFFFFFh\njz short loc_1186\ncmp r8d, eax\njl short loc_1186\njmp short loc_118C\nloc_11AC:\ncmp r9d, 0FFFFFFFFh\njz short loc_11C2\nmov [rdx], eax\nmov [rdx+4], r9d\nmov rax, rdx\nretn\nloc_11BC:\nmov eax, 0\nretn\nloc_11C2:\nmov eax, 0\nretn", + "ida_strip_pseudo": "int *__fastcall sub_1169(__int64 a1, int a2, int *a3)\n{\n __int64 v3; // rcx\n int v4; // r9d\n int v5; // eax\n int v6; // r8d\n\n if ( a2 <= 0 )\n return 0LL;\n v3 = 0LL;\n v4 = -1;\n v5 = 0x7FFFFFFF;\n do\n {\n v6 = *(_DWORD *)(a1 + 4 * v3);\n if ( (v6 & 1) == 0 && (v4 == -1 || v6 < v5) )\n {\n v4 = v3;\n v5 = *(_DWORD *)(a1 + 4 * v3);\n }\n ++v3;\n }\n while ( a2 != v3 );\n if ( v4 == -1 )\n return 0LL;\n *a3 = v5;\n a3[1] = v4;\n return a3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "int *sub_1169(long long a1, int a2, int *a3) {\n long long v3;\n int v4;\n int v5;\n int v6;\n if (a2 <= 0) return 0LL;\n v3 = 0LL;\n v4 = -1;\n v5 = 2147483647;\n do {\n v6 = *(uint32_t *)(a1 + 4 * v3);\n if ((v6 & 1) == 0 && (v4 == -1 || v6 < v5)) {\n v4 = v3;\n v5 = *(uint32_t *)(a1 + 4 * v3);\n }\n ++v3;\n } while (a2 != v3);\n if (v4 == -1) return 0LL;\n *a3 = v5;\n a3[1] = v4;\n return a3;\n}", + "ida_pseudo_norm": "int *func0(long long a1, int a2, int *a3) {\n long long v3;\n int v4;\n int v5;\n int v6;\n if (a2 <= 0) return 0LL;\n v3 = 0LL;\n v4 = -1;\n v5 = 2147483647;\n do {\n v6 = *(uint32_t *)(a1 + 4 * v3);\n if ((v6 & 1) == 0 && (v4 == -1 || v6 < v5)) {\n v4 = v3;\n v5 = *(uint32_t *)(a1 + 4 * v3);\n }\n ++v3;\n } while (a2 != v3);\n if (v4 == -1) return 0LL;\n *a3 = v5;\n a3[1] = v4;\n return a3;\n}" + }, + { + "index": "HumanEval-C-68", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int *func0(int arr[], int length, int output[2]) {\n int smallestEven = INT_MAX;\n int index = -1;\n for (int i = 0; i < length; ++i) {\n if (arr[i] % 2 == 0 && (arr[i] < smallestEven || index == -1)) {\n smallestEven = arr[i];\n index = i;\n }\n }\n if (index == -1) {\n return NULL;\n }\n output[0] = smallestEven;\n output[1] = index;\n return output;\n}", + "test": "#include \n#include \n#include \n\nint issame(const int *a, const int *b, int a_length, int b_length) {\n if (a_length != b_length) return 0;\n for (int i = 0; i < a_length; ++i) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int output[2];\n int *result;\n \n int test1[] = {4, 2, 3};\n int expect1[] = {2, 1};\n result = func0(test1, 3, output);\n assert(issame(result, expect1, 2, 2));\n\n int test2[] = {1, 2, 3};\n int expect2[] = {2, 1};\n result = func0(test2, 3, output);\n assert(issame(result, expect2, 2, 2));\n\n int test3[] = {};\n result = func0(test3, 0, output);\n assert(result == NULL);\n\n int test4[] = {5, 0, 3, 0, 4, 2};\n int expect4[] = {0, 1};\n result = func0(test4, 6, output);\n assert(issame(result, expect4, 2, 2));\n\n int test5[] = {1, 2, 3, 0, 5, 3};\n int expect5[] = {0, 3};\n result = func0(test5, 6, output);\n assert(issame(result, expect5, 2, 2));\n\n int test6[] = {5, 4, 8, 4, 8};\n int expect6[] = {4, 1};\n result = func0(test6, 5, output);\n assert(issame(result, expect6, 2, 2));\n\n int test7[] = {7, 6, 7, 1};\n int expect7[] = {6, 1};\n result = func0(test7, 4, output);\n assert(issame(result, expect7, 2, 2));\n\n int test8[] = {7, 9, 7, 1};\n result = func0(test8, 4, output);\n assert(result == NULL);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1558\nmovsxd rsi, esi\nxor ecx, ecx\nmov r9d, 0FFFFFFFFh\nmov eax, 7FFFFFFFh\nnop dword ptr [rax+rax+00000000h]\nloc_1520:\nmov r8d, [rdi+rcx*4]\ntest r8b, 1\njnz short loc_153B\ncmp r9d, 0FFFFFFFFh\njz short loc_1535\ncmp eax, r8d\njle short loc_153B\nloc_1535:\nmov r9d, ecx\nmov eax, r8d\nloc_153B:\nadd rcx, 1\ncmp rsi, rcx\njnz short loc_1520\ncmp r9d, 0FFFFFFFFh\njz short loc_1558\nmov [rdx], eax\nmov rax, rdx\nmov [rdx+4], r9d\nretn\nloc_1558:\nxor eax, eax\nretn", + "ida_pseudo": "int *__fastcall func0(__int64 a1, int a2, int *a3)\n{\n __int64 v3; // rcx\n int v4; // r9d\n int v5; // eax\n int v6; // r8d\n int *result; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v3 = 0LL;\n v4 = -1;\n v5 = 0x7FFFFFFF;\n do\n {\n v6 = *(_DWORD *)(a1 + 4 * v3);\n if ( (v6 & 1) == 0 && (v4 == -1 || v5 > v6) )\n {\n v4 = v3;\n v5 = *(_DWORD *)(a1 + 4 * v3);\n }\n ++v3;\n }\n while ( a2 != v3 );\n if ( v4 == -1 )\n return 0LL;\n *a3 = v5;\n result = a3;\n a3[1] = v4;\n return result;\n}", + "ida_strip_asm": "sub_1500:\nendbr64\ntest esi, esi\njle short loc_1558\nmovsxd rsi, esi\nxor ecx, ecx\nmov r9d, 0FFFFFFFFh\nmov eax, 7FFFFFFFh\nnop dword ptr [rax+rax+00000000h]\nloc_1520:\nmov r8d, [rdi+rcx*4]\ntest r8b, 1\njnz short loc_153B\ncmp r9d, 0FFFFFFFFh\njz short loc_1535\ncmp eax, r8d\njle short loc_153B\nloc_1535:\nmov r9d, ecx\nmov eax, r8d\nloc_153B:\nadd rcx, 1\ncmp rsi, rcx\njnz short loc_1520\ncmp r9d, 0FFFFFFFFh\njz short loc_1558\nmov [rdx], eax\nmov rax, rdx\nmov [rdx+4], r9d\nretn\nloc_1558:\nxor eax, eax\nretn", + "ida_strip_pseudo": "int *__fastcall sub_1500(__int64 a1, int a2, int *a3)\n{\n __int64 v3; // rcx\n int v4; // r9d\n int v5; // eax\n int v6; // r8d\n int *result; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v3 = 0LL;\n v4 = -1;\n v5 = 0x7FFFFFFF;\n do\n {\n v6 = *(_DWORD *)(a1 + 4 * v3);\n if ( (v6 & 1) == 0 && (v4 == -1 || v5 > v6) )\n {\n v4 = v3;\n v5 = *(_DWORD *)(a1 + 4 * v3);\n }\n ++v3;\n }\n while ( a2 != v3 );\n if ( v4 == -1 )\n return 0LL;\n *a3 = v5;\n result = a3;\n a3[1] = v4;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "int *sub_1500(long long a1, int a2, int *a3) {\n long long v3;\n int v4;\n int v5;\n int v6;\n int *result;\n if (a2 <= 0) return 0LL;\n v3 = 0LL;\n v4 = -1;\n v5 = 2147483647;\n do {\n v6 = *(uint32_t *)(a1 + 4 * v3);\n if ((v6 & 1) == 0 && (v4 == -1 || v5 > v6)) {\n v4 = v3;\n v5 = *(uint32_t *)(a1 + 4 * v3);\n }\n ++v3;\n } while (a2 != v3);\n if (v4 == -1) return 0LL;\n *a3 = v5;\n result = a3;\n a3[1] = v4;\n return result;\n}", + "ida_pseudo_norm": "int *func0(long long a1, int a2, int *a3) {\n long long v3;\n int v4;\n int v5;\n int v6;\n int *result;\n if (a2 <= 0) return 0LL;\n v3 = 0LL;\n v4 = -1;\n v5 = 2147483647;\n do {\n v6 = *(uint32_t *)(a1 + 4 * v3);\n if ((v6 & 1) == 0 && (v4 == -1 || v5 > v6)) {\n v4 = v3;\n v5 = *(uint32_t *)(a1 + 4 * v3);\n }\n ++v3;\n } while (a2 != v3);\n if (v4 == -1) return 0LL;\n *a3 = v5;\n result = a3;\n a3[1] = v4;\n return result;\n}" + }, + { + "index": "HumanEval-C-69", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(int *lst, int size) {\n int *freq = (int *)calloc(size + 1, sizeof(int));\n int max = -1;\n for (int i = 0; i < size; i++) {\n freq[lst[i]]++;\n if ((freq[lst[i]] >= lst[i]) && (lst[i] > max)) {\n max = lst[i];\n }\n }\n free(freq);\n return max;\n}", + "test": "#include \n\nint main() {\n int arr1[] = {5, 5, 5, 5, 1};\n int arr2[] = {4, 1, 4, 1, 4, 4};\n int arr3[] = {3, 3};\n int arr4[] = {8, 8, 8, 8, 8, 8, 8, 8};\n int arr5[] = {2, 3, 3, 2, 2};\n int arr6[] = {2, 7, 8, 8, 4, 8, 7, 3, 9, 6, 5, 10, 4, 3, 6, 7, 1, 7, 4, 10, 8, 1};\n int arr7[] = {3, 2, 8, 2};\n int arr8[] = {6, 7, 1, 8, 8, 10, 5, 8, 5, 3, 10};\n int arr9[] = {8, 8, 3, 6, 5, 6, 4};\n int arr10[] = {6, 9, 6, 7, 1, 4, 7, 1, 8, 8, 9, 8, 10, 10, 8, 4, 10, 4, 10, 1, 2, 9, 5, 7, 9};\n int arr11[] = {1, 9, 10, 1, 3};\n int arr12[] = {6, 9, 7, 5, 8, 7, 5, 3, 7, 5, 10, 10, 3, 6, 10, 2, 8, 6, 5, 4, 9, 5, 3, 10};\n int arr13[] = {1};\n int arr14[] = {8, 8, 10, 6, 4, 3, 5, 8, 2, 4, 2, 8, 4, 6, 10, 4, 2, 1, 10, 2, 1, 1, 5};\n int arr15[] = {2, 10, 4, 8, 2, 10, 5, 1, 2, 9, 5, 5, 6, 3, 8, 6, 4, 10};\n int arr16[] = {1, 6, 10, 1, 6, 9, 10, 8, 6, 8, 7, 3};\n int arr17[] = {9, 2, 4, 1, 5, 1, 5, 2, 5, 7, 7, 7, 3, 10, 1, 5, 4, 2, 8, 4, 1, 9, 10, 7, 10, 2, 8, 10, 9, 4};\n int arr18[] = {2, 6, 4, 2, 8, 7, 5, 6, 4, 10, 4, 6, 3, 7, 8, 8, 3, 1, 4, 2, 2, 10, 7};\n int arr19[] = {9, 8, 6, 10, 2, 6, 10, 2, 7, 8, 10, 3, 8, 2, 6, 2, 3, 1};\n int arr20[] = {5, 5, 3, 9, 5, 6, 3, 2, 8, 5, 6, 10, 10, 6, 8, 4, 10, 7, 7, 10, 8};\n int arr21[] = {10};\n int arr22[] = {9, 7, 7, 2, 4,7, 2, 10, 9, 7, 5, 7, 2};\n int arr23[] = {5, 4, 10, 2, 1, 1, 10, 3, 6, 1, 8};\n int arr24[] = {7, 9, 9, 9, 3, 4, 1, 5, 9, 1, 2, 1, 1, 10, 7, 5, 6, 7, 6, 7, 7, 6};\n int arr25[] = {3, 10, 10, 9, 2};\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov eax, [rbp+var_1C]\nadd eax, 1\ncdqe\nmov esi, 4; size\nmov rdi, rax; nmemb\ncall _calloc\nmov [rbp+ptr], rax\nmov [rbp+var_10], 0FFFFFFFFh\nmov [rbp+var_C], 0\njmp loc_1271\nloc_11C8:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nadd edx, 1\nmov [rax], edx\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njl short loc_126D\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_10], eax\njge short loc_126D\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_10], eax\nloc_126D:\nadd [rbp+var_C], 1\nloc_1271:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl loc_11C8\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov eax, [rbp+var_10]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n _DWORD *v2; // rax\n int v4; // [rsp+10h] [rbp-10h]\n int i; // [rsp+14h] [rbp-Ch]\n _DWORD *ptr; // [rsp+18h] [rbp-8h]\n\n ptr = calloc(a2 + 1, 4uLL);\n v4 = -1;\n for ( i = 0; i < a2; ++i )\n {\n v2 = &ptr[*(int *)(4LL * i + a1)];\n ++*v2;\n if ( ptr[*(int *)(4LL * i + a1)] >= *(_DWORD *)(4LL * i + a1) && v4 < *(_DWORD *)(4LL * i + a1) )\n v4 = *(_DWORD *)(4LL * i + a1);\n }\n free(ptr);\n return (unsigned int)v4;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov eax, [rbp+var_1C]\nadd eax, 1\ncdqe\nmov esi, 4; size\nmov rdi, rax; nmemb\ncall _calloc\nmov [rbp+ptr], rax\nmov [rbp+var_10], 0FFFFFFFFh\nmov [rbp+var_C], 0\njmp loc_1271\nloc_11C8:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nadd edx, 1\nmov [rax], edx\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njl short loc_126D\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_10], eax\njge short loc_126D\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_10], eax\nloc_126D:\nadd [rbp+var_C], 1\nloc_1271:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl loc_11C8\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov eax, [rbp+var_10]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2)\n{\n _DWORD *v2; // rax\n int v4; // [rsp+10h] [rbp-10h]\n int i; // [rsp+14h] [rbp-Ch]\n _DWORD *ptr; // [rsp+18h] [rbp-8h]\n\n ptr = calloc(a2 + 1, 4uLL);\n v4 = -1;\n for ( i = 0; i < a2; ++i )\n {\n v2 = &ptr[*(int *)(4LL * i + a1)];\n ++*v2;\n if ( ptr[*(int *)(4LL * i + a1)] >= *(_DWORD *)(4LL * i + a1) && v4 < *(_DWORD *)(4LL * i + a1) )\n v4 = *(_DWORD *)(4LL * i + a1);\n }\n free(ptr);\n return (unsigned int)v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2) {\n uint32_t *v2;\n int v4;\n int i;\n uint32_t *ptr;\n ptr = calloc(a2 + 1, 4uLL);\n v4 = -1;\n for (i = 0; i < a2; ++i) {\n v2 = &ptr[*(int *)(4LL * i + a1)];\n ++*v2;\n if (ptr[*(int *)(4LL * i + a1)] >= *(uint32_t *)(4LL * i + a1) &&\n v4 < *(uint32_t *)(4LL * i + a1))\n v4 = *(uint32_t *)(4LL * i + a1);\n }\n free(ptr);\n return (unsigned int)v4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n uint32_t *v2;\n int v4;\n int i;\n uint32_t *ptr;\n ptr = calloc(a2 + 1, 4uLL);\n v4 = -1;\n for (i = 0; i < a2; ++i) {\n v2 = &ptr[*(int *)(4LL * i + a1)];\n ++*v2;\n if (ptr[*(int *)(4LL * i + a1)] >= *(uint32_t *)(4LL * i + a1) &&\n v4 < *(uint32_t *)(4LL * i + a1))\n v4 = *(uint32_t *)(4LL * i + a1);\n }\n free(ptr);\n return (unsigned int)v4;\n}" + }, + { + "index": "HumanEval-C-69", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(int *lst, int size) {\n int *freq = (int *)calloc(size + 1, sizeof(int));\n int max = -1;\n for (int i = 0; i < size; i++) {\n freq[lst[i]]++;\n if ((freq[lst[i]] >= lst[i]) && (lst[i] > max)) {\n max = lst[i];\n }\n }\n free(freq);\n return max;\n}", + "test": "#include \n\nint main() {\n int arr1[] = {5, 5, 5, 5, 1};\n int arr2[] = {4, 1, 4, 1, 4, 4};\n int arr3[] = {3, 3};\n int arr4[] = {8, 8, 8, 8, 8, 8, 8, 8};\n int arr5[] = {2, 3, 3, 2, 2};\n int arr6[] = {2, 7, 8, 8, 4, 8, 7, 3, 9, 6, 5, 10, 4, 3, 6, 7, 1, 7, 4, 10, 8, 1};\n int arr7[] = {3, 2, 8, 2};\n int arr8[] = {6, 7, 1, 8, 8, 10, 5, 8, 5, 3, 10};\n int arr9[] = {8, 8, 3, 6, 5, 6, 4};\n int arr10[] = {6, 9, 6, 7, 1, 4, 7, 1, 8, 8, 9, 8, 10, 10, 8, 4, 10, 4, 10, 1, 2, 9, 5, 7, 9};\n int arr11[] = {1, 9, 10, 1, 3};\n int arr12[] = {6, 9, 7, 5, 8, 7, 5, 3, 7, 5, 10, 10, 3, 6, 10, 2, 8, 6, 5, 4, 9, 5, 3, 10};\n int arr13[] = {1};\n int arr14[] = {8, 8, 10, 6, 4, 3, 5, 8, 2, 4, 2, 8, 4, 6, 10, 4, 2, 1, 10, 2, 1, 1, 5};\n int arr15[] = {2, 10, 4, 8, 2, 10, 5, 1, 2, 9, 5, 5, 6, 3, 8, 6, 4, 10};\n int arr16[] = {1, 6, 10, 1, 6, 9, 10, 8, 6, 8, 7, 3};\n int arr17[] = {9, 2, 4, 1, 5, 1, 5, 2, 5, 7, 7, 7, 3, 10, 1, 5, 4, 2, 8, 4, 1, 9, 10, 7, 10, 2, 8, 10, 9, 4};\n int arr18[] = {2, 6, 4, 2, 8, 7, 5, 6, 4, 10, 4, 6, 3, 7, 8, 8, 3, 1, 4, 2, 2, 10, 7};\n int arr19[] = {9, 8, 6, 10, 2, 6, 10, 2, 7, 8, 10, 3, 8, 2, 6, 2, 3, 1};\n int arr20[] = {5, 5, 3, 9, 5, 6, 3, 2, 8, 5, 6, 10, 10, 6, 8, 4, 10, 7, 7, 10, 8};\n int arr21[] = {10};\n int arr22[] = {9, 7, 7, 2, 4,7, 2, 10, 9, 7, 5, 7, 2};\n int arr23[] = {5, 4, 10, 2, 1, 1, 10, 3, 6, 1, 8};\n int arr24[] = {7, 9, 9, 9, 3, 4, 1, 5, 9, 1, 2, 1, 1, 10, 7, 5, 6, 7, 6, 7, 7, 6};\n int arr25[] = {3, 10, 10, 9, 2};\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov ebx, esi\nlea edi, [rsi+1]\nmovsxd rdi, edi; nmemb\nmov esi, 4; size\ncall _calloc\nmov rdi, rax; ptr\ntest ebx, ebx\njle short loc_11D7\nmov rsi, rbp\nmovsxd rbx, ebx\nlea rax, [rbp+rbx*4+0]\nmov ebx, 0FFFFFFFFh\nloc_119F:\nmov ecx, [rsi]\nmovsxd rdx, ecx\nlea r8, [rdi+rdx*4]\nmov edx, [r8]\nadd edx, 1\nmov [r8], edx\ncmp ebx, ecx\nmov r8d, ecx\ncmovge r8d, ebx\ncmp ecx, edx\ncmovle ebx, r8d\nadd rsi, 4\ncmp rsi, rax\njnz short loc_119F\nloc_11C9:\ncall _free\nmov eax, ebx\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_11D7:\nmov ebx, 0FFFFFFFFh\njmp short loc_11C9", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n char *v4; // rdi\n int *v5; // rsi\n int *v6; // rax\n int v7; // ebx\n int v8; // ecx\n int *v9; // r8\n int v10; // edx\n int v11; // r8d\n\n v4 = (char *)calloc(a2 + 1, 4uLL);\n if ( a2 <= 0 )\n {\n v7 = -1;\n }\n else\n {\n v5 = a1;\n v6 = &a1[a2];\n v7 = -1;\n do\n {\n v8 = *v5;\n v9 = (int *)&v4[4 * *v5];\n v10 = *v9 + 1;\n *v9 = v10;\n v11 = v8;\n if ( v7 >= v8 )\n v11 = v7;\n if ( v8 <= v10 )\n v7 = v11;\n ++v5;\n }\n while ( v5 != v6 );\n }\n free(v4);\n return (unsigned int)v7;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov ebx, esi\nlea edi, [rsi+1]\nmovsxd rdi, edi; nmemb\nmov esi, 4; size\ncall _calloc\nmov rdi, rax; ptr\ntest ebx, ebx\njle short loc_11D7\nmov rsi, rbp\nmovsxd rbx, ebx\nlea rax, [rbp+rbx*4+0]\nmov ebx, 0FFFFFFFFh\nloc_119F:\nmov ecx, [rsi]\nmovsxd rdx, ecx\nlea r8, [rdi+rdx*4]\nmov edx, [r8]\nadd edx, 1\nmov [r8], edx\ncmp ebx, ecx\nmov r8d, ecx\ncmovge r8d, ebx\ncmp ecx, edx\ncmovle ebx, r8d\nadd rsi, 4\ncmp rsi, rax\njnz short loc_119F\nloc_11C9:\ncall _free\nmov eax, ebx\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_11D7:\nmov ebx, 0FFFFFFFFh\njmp short loc_11C9", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int *a1, int a2)\n{\n char *v4; // rdi\n int *v5; // rsi\n int *v6; // rax\n int v7; // ebx\n int v8; // ecx\n int *v9; // r8\n int v10; // edx\n int v11; // r8d\n\n v4 = (char *)calloc(a2 + 1, 4uLL);\n if ( a2 <= 0 )\n {\n v7 = -1;\n }\n else\n {\n v5 = a1;\n v6 = &a1[a2];\n v7 = -1;\n do\n {\n v8 = *v5;\n v9 = (int *)&v4[4 * *v5];\n v10 = *v9 + 1;\n *v9 = v10;\n v11 = v8;\n if ( v7 >= v8 )\n v11 = v7;\n if ( v8 <= v10 )\n v7 = v11;\n ++v5;\n }\n while ( v5 != v6 );\n }\n free(v4);\n return (unsigned int)v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int *a1, int a2) {\n char *v4;\n int *v5;\n int *v6;\n int v7;\n int v8;\n int *v9;\n int v10;\n int v11;\n v4 = (char *)calloc(a2 + 1, 4uLL);\n if (a2 <= 0) {\n v7 = -1;\n } else {\n v5 = a1;\n v6 = &a1[a2];\n v7 = -1;\n do {\n v8 = *v5;\n v9 = (int *)&v4[4 * *v5];\n v10 = *v9 + 1;\n *v9 = v10;\n v11 = v8;\n if (v7 >= v8) v11 = v7;\n if (v8 <= v10) v7 = v11;\n ++v5;\n } while (v5 != v6);\n }\n free(v4);\n return (unsigned int)v7;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n char *v4;\n int *v5;\n int *v6;\n int v7;\n int v8;\n int *v9;\n int v10;\n int v11;\n v4 = (char *)calloc(a2 + 1, 4uLL);\n if (a2 <= 0) {\n v7 = -1;\n } else {\n v5 = a1;\n v6 = &a1[a2];\n v7 = -1;\n do {\n v8 = *v5;\n v9 = (int *)&v4[4 * *v5];\n v10 = *v9 + 1;\n *v9 = v10;\n v11 = v8;\n if (v7 >= v8) v11 = v7;\n if (v8 <= v10) v7 = v11;\n ++v5;\n } while (v5 != v6);\n }\n free(v4);\n return (unsigned int)v7;\n}" + }, + { + "index": "HumanEval-C-69", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(int *lst, int size) {\n int *freq = (int *)calloc(size + 1, sizeof(int));\n int max = -1;\n for (int i = 0; i < size; i++) {\n freq[lst[i]]++;\n if ((freq[lst[i]] >= lst[i]) && (lst[i] > max)) {\n max = lst[i];\n }\n }\n free(freq);\n return max;\n}", + "test": "#include \n\nint main() {\n int arr1[] = {5, 5, 5, 5, 1};\n int arr2[] = {4, 1, 4, 1, 4, 4};\n int arr3[] = {3, 3};\n int arr4[] = {8, 8, 8, 8, 8, 8, 8, 8};\n int arr5[] = {2, 3, 3, 2, 2};\n int arr6[] = {2, 7, 8, 8, 4, 8, 7, 3, 9, 6, 5, 10, 4, 3, 6, 7, 1, 7, 4, 10, 8, 1};\n int arr7[] = {3, 2, 8, 2};\n int arr8[] = {6, 7, 1, 8, 8, 10, 5, 8, 5, 3, 10};\n int arr9[] = {8, 8, 3, 6, 5, 6, 4};\n int arr10[] = {6, 9, 6, 7, 1, 4, 7, 1, 8, 8, 9, 8, 10, 10, 8, 4, 10, 4, 10, 1, 2, 9, 5, 7, 9};\n int arr11[] = {1, 9, 10, 1, 3};\n int arr12[] = {6, 9, 7, 5, 8, 7, 5, 3, 7, 5, 10, 10, 3, 6, 10, 2, 8, 6, 5, 4, 9, 5, 3, 10};\n int arr13[] = {1};\n int arr14[] = {8, 8, 10, 6, 4, 3, 5, 8, 2, 4, 2, 8, 4, 6, 10, 4, 2, 1, 10, 2, 1, 1, 5};\n int arr15[] = {2, 10, 4, 8, 2, 10, 5, 1, 2, 9, 5, 5, 6, 3, 8, 6, 4, 10};\n int arr16[] = {1, 6, 10, 1, 6, 9, 10, 8, 6, 8, 7, 3};\n int arr17[] = {9, 2, 4, 1, 5, 1, 5, 2, 5, 7, 7, 7, 3, 10, 1, 5, 4, 2, 8, 4, 1, 9, 10, 7, 10, 2, 8, 10, 9, 4};\n int arr18[] = {2, 6, 4, 2, 8, 7, 5, 6, 4, 10, 4, 6, 3, 7, 8, 8, 3, 1, 4, 2, 2, 10, 7};\n int arr19[] = {9, 8, 6, 10, 2, 6, 10, 2, 7, 8, 10, 3, 8, 2, 6, 2, 3, 1};\n int arr20[] = {5, 5, 3, 9, 5, 6, 3, 2, 8, 5, 6, 10, 10, 6, 8, 4, 10, 7, 7, 10, 8};\n int arr21[] = {10};\n int arr22[] = {9, 7, 7, 2, 4,7, 2, 10, 9, 7, 5, 7, 2};\n int arr23[] = {5, 4, 10, 2, 1, 1, 10, 3, 6, 1, 8};\n int arr24[] = {7, 9, 9, 9, 3, 4, 1, 5, 9, 1, 2, 1, 1, 10, 7, 5, 6, 7, 6, 7, 7, 6};\n int arr25[] = {3, 10, 10, 9, 2};\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmovsxd rbp, esi\nmov esi, 4; size\npush rbx\nmov rbx, rdi\nlea edi, [rbp+1]\nmovsxd rdi, edi; nmemb\nsub rsp, 8\ncall _calloc\nmov rdi, rax; ptr\ntest ebp, ebp\njle short loc_11F0\nmov r8, rbx\nlea rax, [rbx+rbp*4]\nmov ebx, 0FFFFFFFFh\nnop dword ptr [rax+rax+00h]\nloc_11B8:\nmovsxd rdx, dword ptr [r8]\nlea rsi, [rdi+rdx*4]\nmov rcx, rdx\nmov edx, [rsi]\nadd edx, 1\ncmp ebx, ecx\nmov [rsi], edx\nmov esi, ecx\ncmovge esi, ebx\ncmp ecx, edx\ncmovle ebx, esi\nadd r8, 4\ncmp rax, r8\njnz short loc_11B8\ncall _free\nadd rsp, 8\nmov eax, ebx\npop rbx\npop rbp\nretn\nloc_11F0:\ncall _free\nmov ebx, 0FFFFFFFFh\nadd rsp, 8\nmov eax, ebx\npop rbx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n char *v3; // rdi\n int *v4; // r8\n int *v5; // rax\n int v6; // ebx\n int *v7; // rsi\n int v8; // ecx\n int v9; // edx\n int v10; // esi\n\n v3 = (char *)calloc(a2 + 1, 4uLL);\n if ( a2 <= 0 )\n {\n free(v3);\n return 0xFFFFFFFFLL;\n }\n else\n {\n v4 = a1;\n v5 = &a1[a2];\n v6 = -1;\n do\n {\n v7 = (int *)&v3[4 * *v4];\n v8 = *v4;\n v9 = *v7 + 1;\n *v7 = v9;\n v10 = v8;\n if ( v6 >= v8 )\n v10 = v6;\n if ( v8 <= v9 )\n v6 = v10;\n ++v4;\n }\n while ( v5 != v4 );\n free(v3);\n return (unsigned int)v6;\n }\n}", + "ida_strip_asm": "sub_1180:\nendbr64\npush rbp\nmovsxd rbp, esi\nmov esi, 4; size\npush rbx\nmov rbx, rdi\nlea edi, [rbp+1]\nmovsxd rdi, edi; nmemb\nsub rsp, 8\ncall _calloc\nmov rdi, rax; ptr\ntest ebp, ebp\njle short loc_11F0\nmov r8, rbx\nlea rax, [rbx+rbp*4]\nmov ebx, 0FFFFFFFFh\nnop dword ptr [rax+rax+00h]\nloc_11B8:\nmovsxd rdx, dword ptr [r8]\nlea rsi, [rdi+rdx*4]\nmov rcx, rdx\nmov edx, [rsi]\nadd edx, 1\ncmp ebx, ecx\nmov [rsi], edx\nmov esi, ecx\ncmovge esi, ebx\ncmp ecx, edx\ncmovle ebx, esi\nadd r8, 4\ncmp rax, r8\njnz short loc_11B8\ncall _free\nadd rsp, 8\nmov eax, ebx\npop rbx\npop rbp\nretn\nloc_11F0:\ncall _free\nmov ebx, 0FFFFFFFFh\nadd rsp, 8\nmov eax, ebx\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1180(int *a1, int a2)\n{\n char *v3; // rdi\n int *v4; // r8\n int *v5; // rax\n int v6; // ebx\n int *v7; // rsi\n int v8; // ecx\n int v9; // edx\n int v10; // esi\n\n v3 = (char *)calloc(a2 + 1, 4uLL);\n if ( a2 <= 0 )\n {\n free(v3);\n return 0xFFFFFFFFLL;\n }\n else\n {\n v4 = a1;\n v5 = &a1[a2];\n v6 = -1;\n do\n {\n v7 = (int *)&v3[4 * *v4];\n v8 = *v4;\n v9 = *v7 + 1;\n *v7 = v9;\n v10 = v8;\n if ( v6 >= v8 )\n v10 = v6;\n if ( v8 <= v9 )\n v6 = v10;\n ++v4;\n }\n while ( v5 != v4 );\n free(v3);\n return (unsigned int)v6;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1180(int *a1, int a2) {\n char *v3;\n int *v4;\n int *v5;\n int v6;\n int *v7;\n int v8;\n int v9;\n int v10;\n v3 = (char *)calloc(a2 + 1, 4uLL);\n if (a2 <= 0) {\n free(v3);\n return 4294967295LL;\n } else {\n v4 = a1;\n v5 = &a1[a2];\n v6 = -1;\n do {\n v7 = (int *)&v3[4 * *v4];\n v8 = *v4;\n v9 = *v7 + 1;\n *v7 = v9;\n v10 = v8;\n if (v6 >= v8) v10 = v6;\n if (v8 <= v9) v6 = v10;\n ++v4;\n } while (v5 != v4);\n free(v3);\n return (unsigned int)v6;\n }\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n char *v3;\n int *v4;\n int *v5;\n int v6;\n int *v7;\n int v8;\n int v9;\n int v10;\n v3 = (char *)calloc(a2 + 1, 4uLL);\n if (a2 <= 0) {\n free(v3);\n return 4294967295LL;\n } else {\n v4 = a1;\n v5 = &a1[a2];\n v6 = -1;\n do {\n v7 = (int *)&v3[4 * *v4];\n v8 = *v4;\n v9 = *v7 + 1;\n *v7 = v9;\n v10 = v8;\n if (v6 >= v8) v10 = v6;\n if (v8 <= v9) v6 = v10;\n ++v4;\n } while (v5 != v4);\n free(v3);\n return (unsigned int)v6;\n }\n}" + }, + { + "index": "HumanEval-C-69", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(int *lst, int size) {\n int *freq = (int *)calloc(size + 1, sizeof(int));\n int max = -1;\n for (int i = 0; i < size; i++) {\n freq[lst[i]]++;\n if ((freq[lst[i]] >= lst[i]) && (lst[i] > max)) {\n max = lst[i];\n }\n }\n free(freq);\n return max;\n}", + "test": "#include \n\nint main() {\n int arr1[] = {5, 5, 5, 5, 1};\n int arr2[] = {4, 1, 4, 1, 4, 4};\n int arr3[] = {3, 3};\n int arr4[] = {8, 8, 8, 8, 8, 8, 8, 8};\n int arr5[] = {2, 3, 3, 2, 2};\n int arr6[] = {2, 7, 8, 8, 4, 8, 7, 3, 9, 6, 5, 10, 4, 3, 6, 7, 1, 7, 4, 10, 8, 1};\n int arr7[] = {3, 2, 8, 2};\n int arr8[] = {6, 7, 1, 8, 8, 10, 5, 8, 5, 3, 10};\n int arr9[] = {8, 8, 3, 6, 5, 6, 4};\n int arr10[] = {6, 9, 6, 7, 1, 4, 7, 1, 8, 8, 9, 8, 10, 10, 8, 4, 10, 4, 10, 1, 2, 9, 5, 7, 9};\n int arr11[] = {1, 9, 10, 1, 3};\n int arr12[] = {6, 9, 7, 5, 8, 7, 5, 3, 7, 5, 10, 10, 3, 6, 10, 2, 8, 6, 5, 4, 9, 5, 3, 10};\n int arr13[] = {1};\n int arr14[] = {8, 8, 10, 6, 4, 3, 5, 8, 2, 4, 2, 8, 4, 6, 10, 4, 2, 1, 10, 2, 1, 1, 5};\n int arr15[] = {2, 10, 4, 8, 2, 10, 5, 1, 2, 9, 5, 5, 6, 3, 8, 6, 4, 10};\n int arr16[] = {1, 6, 10, 1, 6, 9, 10, 8, 6, 8, 7, 3};\n int arr17[] = {9, 2, 4, 1, 5, 1, 5, 2, 5, 7, 7, 7, 3, 10, 1, 5, 4, 2, 8, 4, 1, 9, 10, 7, 10, 2, 8, 10, 9, 4};\n int arr18[] = {2, 6, 4, 2, 8, 7, 5, 6, 4, 10, 4, 6, 3, 7, 8, 8, 3, 1, 4, 2, 2, 10, 7};\n int arr19[] = {9, 8, 6, 10, 2, 6, 10, 2, 7, 8, 10, 3, 8, 2, 6, 2, 3, 1};\n int arr20[] = {5, 5, 3, 9, 5, 6, 3, 2, 8, 5, 6, 10, 10, 6, 8, 4, 10, 7, 7, 10, 8};\n int arr21[] = {10};\n int arr22[] = {9, 7, 7, 2, 4,7, 2, 10, 9, 7, 5, 7, 2};\n int arr23[] = {5, 4, 10, 2, 1, 1, 10, 3, 6, 1, 8};\n int arr24[] = {7, 9, 9, 9, 3, 4, 1, 5, 9, 1, 2, 1, 1, 10, 7, 5, 6, 7, 6, 7, 7, 6};\n int arr25[] = {3, 10, 10, 9, 2};\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmovsxd rbp, esi\nmov esi, 4; size\npush rbx\nmov rbx, rdi\nlea edi, [rbp+1]\nmovsxd rdi, edi; nmemb\nsub rsp, 8\ncall _calloc\nmov rdi, rax; ptr\ntest ebp, ebp\njle short loc_11F0\nmov r8, rbx\nlea rax, [rbx+rbp*4]\nmov ebx, 0FFFFFFFFh\nnop dword ptr [rax+rax+00h]\nloc_11B8:\nmovsxd rdx, dword ptr [r8]\nlea rsi, [rdi+rdx*4]\nmov rcx, rdx\nmov edx, [rsi]\nadd edx, 1\ncmp ebx, ecx\nmov [rsi], edx\nmov esi, ecx\ncmovge esi, ebx\ncmp ecx, edx\ncmovle ebx, esi\nadd r8, 4\ncmp rax, r8\njnz short loc_11B8\ncall _free\nadd rsp, 8\nmov eax, ebx\npop rbx\npop rbp\nretn\nloc_11F0:\ncall _free\nmov ebx, 0FFFFFFFFh\nadd rsp, 8\nmov eax, ebx\npop rbx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n char *v3; // rdi\n int *v4; // r8\n int *v5; // rax\n int v6; // ebx\n int *v7; // rsi\n int v8; // ecx\n int v9; // edx\n int v10; // esi\n\n v3 = (char *)calloc(a2 + 1, 4uLL);\n if ( a2 <= 0 )\n {\n free(v3);\n return 0xFFFFFFFFLL;\n }\n else\n {\n v4 = a1;\n v5 = &a1[a2];\n v6 = -1;\n do\n {\n v7 = (int *)&v3[4 * *v4];\n v8 = *v4;\n v9 = *v7 + 1;\n *v7 = v9;\n v10 = v8;\n if ( v6 >= v8 )\n v10 = v6;\n if ( v8 <= v9 )\n v6 = v10;\n ++v4;\n }\n while ( v5 != v4 );\n free(v3);\n return (unsigned int)v6;\n }\n}", + "ida_strip_asm": "sub_1180:\nendbr64\npush rbp\nmovsxd rbp, esi\nmov esi, 4; size\npush rbx\nmov rbx, rdi\nlea edi, [rbp+1]\nmovsxd rdi, edi; nmemb\nsub rsp, 8\ncall _calloc\nmov rdi, rax; ptr\ntest ebp, ebp\njle short loc_11F0\nmov r8, rbx\nlea rax, [rbx+rbp*4]\nmov ebx, 0FFFFFFFFh\nnop dword ptr [rax+rax+00h]\nloc_11B8:\nmovsxd rdx, dword ptr [r8]\nlea rsi, [rdi+rdx*4]\nmov rcx, rdx\nmov edx, [rsi]\nadd edx, 1\ncmp ebx, ecx\nmov [rsi], edx\nmov esi, ecx\ncmovge esi, ebx\ncmp ecx, edx\ncmovle ebx, esi\nadd r8, 4\ncmp rax, r8\njnz short loc_11B8\ncall _free\nadd rsp, 8\nmov eax, ebx\npop rbx\npop rbp\nretn\nloc_11F0:\ncall _free\nmov ebx, 0FFFFFFFFh\nadd rsp, 8\nmov eax, ebx\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1180(int *a1, int a2)\n{\n char *v3; // rdi\n int *v4; // r8\n int *v5; // rax\n int v6; // ebx\n int *v7; // rsi\n int v8; // ecx\n int v9; // edx\n int v10; // esi\n\n v3 = (char *)calloc(a2 + 1, 4uLL);\n if ( a2 <= 0 )\n {\n free(v3);\n return 0xFFFFFFFFLL;\n }\n else\n {\n v4 = a1;\n v5 = &a1[a2];\n v6 = -1;\n do\n {\n v7 = (int *)&v3[4 * *v4];\n v8 = *v4;\n v9 = *v7 + 1;\n *v7 = v9;\n v10 = v8;\n if ( v6 >= v8 )\n v10 = v6;\n if ( v8 <= v9 )\n v6 = v10;\n ++v4;\n }\n while ( v5 != v4 );\n free(v3);\n return (unsigned int)v6;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1180(int *a1, int a2) {\n char *v3;\n int *v4;\n int *v5;\n int v6;\n int *v7;\n int v8;\n int v9;\n int v10;\n v3 = (char *)calloc(a2 + 1, 4uLL);\n if (a2 <= 0) {\n free(v3);\n return 4294967295LL;\n } else {\n v4 = a1;\n v5 = &a1[a2];\n v6 = -1;\n do {\n v7 = (int *)&v3[4 * *v4];\n v8 = *v4;\n v9 = *v7 + 1;\n *v7 = v9;\n v10 = v8;\n if (v6 >= v8) v10 = v6;\n if (v8 <= v9) v6 = v10;\n ++v4;\n } while (v5 != v4);\n free(v3);\n return (unsigned int)v6;\n }\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n char *v3;\n int *v4;\n int *v5;\n int v6;\n int *v7;\n int v8;\n int v9;\n int v10;\n v3 = (char *)calloc(a2 + 1, 4uLL);\n if (a2 <= 0) {\n free(v3);\n return 4294967295LL;\n } else {\n v4 = a1;\n v5 = &a1[a2];\n v6 = -1;\n do {\n v7 = (int *)&v3[4 * *v4];\n v8 = *v4;\n v9 = *v7 + 1;\n *v7 = v9;\n v10 = v8;\n if (v6 >= v8) v10 = v6;\n if (v8 <= v9) v6 = v10;\n ++v4;\n } while (v5 != v4);\n free(v3);\n return (unsigned int)v6;\n }\n}" + }, + { + "index": "HumanEval-C-70", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(int *lst, int size, int *out) {\n for (int i = 0; i < size - 1; i++) {\n for (int j = i + 1; j < size; j++) {\n if (lst[i] > lst[j]) {\n int temp = lst[i];\n lst[i] = lst[j];\n lst[j] = temp;\n }\n }\n }\n int l = 0, r = size - 1;\n int index = 0;\n while (l <= r) {\n if (l == r) {\n out[index++] = lst[l++];\n } else {\n out[index++] = lst[l++];\n out[index++] = lst[r--];\n }\n }\n}", + "test": "#include \n#include \n\nint issame(int *a, int *b, int size) {\n for (int i = 0; i < size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int a1[] = {1, 2, 3, 4};\n int e1[] = {1, 4, 2, 3};\n int out1[4];\n func0(a1, 4, out1);\n assert(issame(e1, out1, 4));\n\n int a2[] = {5, 6, 7, 8, 9};\n int e2[] = {5, 9, 6, 8, 7};\n int out2[5];\n func0(a2, 5, out2);\n assert(issame(e2, out2, 5));\n\n int a3[] = {1, 2, 3, 4, 5};\n int e3[] = {1, 5, 2, 4, 3};\n int out3[5];\n func0(a3, 5, out3);\n assert(issame(e3, out3, 5));\n\n int a4[] = {5, 6, 7, 8, 9, 1};\n int e4[] = {1, 9, 5, 8, 6, 7};\n int out4[6];\n func0(a4, 6, out4);\n assert(issame(e4, out4, 6));\n\n int a5[] = {5, 5, 5, 5};\n int e5[] = {5, 5, 5, 5};\n int out5[4];\n func0(a5, 4, out5);\n assert(issame(e5, out5, 4));\n\n int a6[] = {};\n int e6[] = {};\n int out6[0];\n func0(a6, 0, out6);\n assert(issame(e6, out6, 0));\n\n int a7[] = {1, 2, 3, 4, 5, 6, 7, 8};\n int e7[] = {1, 8, 2, 7, 3, 6, 4, 5};\n int out7[8];\n func0(a7, 8, out7);\n assert(issame(e7, out7, 8));\n\n int a8[] = {0, 2, 2, 2, 5, 5, -5, -5};\n int e8[] = {-5, 5, -5, 5, 0, 2, 2, 2};\n int out8[8];\n func0(a8, 8, out8);\n assert(issame(e8, out8, 8));\n\n int a9[] = {111111};\n int e9[] = {111111};\n int out9[1];\n func0(a9, 1, out9);\n assert(issame(e9, out9, 1));\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmov [rbp+var_18], 0\njmp loc_1239\nloc_1188:\nmov eax, [rbp+var_18]\nadd eax, 1\nmov [rbp+var_14], eax\njmp loc_1229\nloc_1196:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_14]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_1225\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_18]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nloc_1225:\nadd [rbp+var_14], 1\nloc_1229:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl loc_1196\nadd [rbp+var_18], 1\nloc_1239:\nmov eax, [rbp+var_2C]\nsub eax, 1\ncmp [rbp+var_18], eax\njl loc_1188\nmov [rbp+var_10], 0\nmov eax, [rbp+var_2C]\nsub eax, 1\nmov [rbp+var_C], eax\nmov [rbp+var_8], 0\njmp loc_1319\nloc_1264:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_C]\njnz short loc_12A7\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_8]\nlea edx, [rax+1]\nmov [rbp+var_8], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\njmp short loc_1319\nloc_12A7:\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_8]\nlea edx, [rax+1]\nmov [rbp+var_8], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nmov eax, [rbp+var_C]\nlea edx, [rax-1]\nmov [rbp+var_C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_8]\nlea edx, [rax+1]\nmov [rbp+var_8], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_1319:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_C]\njle loc_1264\nnop\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3)\n{\n int v3; // eax\n _DWORD *v4; // rcx\n int v5; // eax\n _DWORD *v6; // rcx\n int v7; // eax\n __int64 result; // rax\n int i; // [rsp+20h] [rbp-18h]\n int j; // [rsp+24h] [rbp-14h]\n unsigned int v11; // [rsp+28h] [rbp-10h]\n int v12; // [rsp+2Ch] [rbp-Ch]\n int k; // [rsp+30h] [rbp-8h]\n int v14; // [rsp+34h] [rbp-4h]\n\n for ( i = 0; i < a2 - 1; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a1) > *(_DWORD *)(4LL * j + a1) )\n {\n v14 = *(_DWORD *)(4LL * i + a1);\n *(_DWORD *)(4LL * i + a1) = *(_DWORD *)(4LL * j + a1);\n *(_DWORD *)(a1 + 4LL * j) = v14;\n }\n }\n }\n v11 = 0;\n v12 = a2 - 1;\n for ( k = 0; ; ++k )\n {\n result = v11;\n if ( (int)v11 > v12 )\n break;\n v3 = v11;\n if ( v11 == v12 )\n {\n ++v11;\n }\n else\n {\n ++v11;\n v6 = (_DWORD *)(4LL * v3 + a1);\n v7 = k++;\n *(_DWORD *)(a3 + 4LL * v7) = *v6;\n v3 = v12--;\n }\n v4 = (_DWORD *)(4LL * v3 + a1);\n v5 = k;\n *(_DWORD *)(a3 + 4LL * v5) = *v4;\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmov [rbp+var_18], 0\njmp loc_1239\nloc_1188:\nmov eax, [rbp+var_18]\nadd eax, 1\nmov [rbp+var_14], eax\njmp loc_1229\nloc_1196:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_14]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_1225\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_18]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nloc_1225:\nadd [rbp+var_14], 1\nloc_1229:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl loc_1196\nadd [rbp+var_18], 1\nloc_1239:\nmov eax, [rbp+var_2C]\nsub eax, 1\ncmp [rbp+var_18], eax\njl loc_1188\nmov [rbp+var_10], 0\nmov eax, [rbp+var_2C]\nsub eax, 1\nmov [rbp+var_C], eax\nmov [rbp+var_8], 0\njmp loc_1319\nloc_1264:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_C]\njnz short loc_12A7\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_8]\nlea edx, [rax+1]\nmov [rbp+var_8], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\njmp short loc_1319\nloc_12A7:\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_8]\nlea edx, [rax+1]\nmov [rbp+var_8], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nmov eax, [rbp+var_C]\nlea edx, [rax-1]\nmov [rbp+var_C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_8]\nlea edx, [rax+1]\nmov [rbp+var_8], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_1319:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_C]\njle loc_1264\nnop\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, __int64 a3)\n{\n int v3; // eax\n _DWORD *v4; // rcx\n int v5; // eax\n _DWORD *v6; // rcx\n int v7; // eax\n __int64 result; // rax\n int i; // [rsp+20h] [rbp-18h]\n int j; // [rsp+24h] [rbp-14h]\n unsigned int v11; // [rsp+28h] [rbp-10h]\n int v12; // [rsp+2Ch] [rbp-Ch]\n int k; // [rsp+30h] [rbp-8h]\n int v14; // [rsp+34h] [rbp-4h]\n\n for ( i = 0; i < a2 - 1; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a1) > *(_DWORD *)(4LL * j + a1) )\n {\n v14 = *(_DWORD *)(4LL * i + a1);\n *(_DWORD *)(4LL * i + a1) = *(_DWORD *)(4LL * j + a1);\n *(_DWORD *)(a1 + 4LL * j) = v14;\n }\n }\n }\n v11 = 0;\n v12 = a2 - 1;\n for ( k = 0; ; ++k )\n {\n result = v11;\n if ( (int)v11 > v12 )\n break;\n v3 = v11;\n if ( v11 == v12 )\n {\n ++v11;\n }\n else\n {\n ++v11;\n v6 = (_DWORD *)(4LL * v3 + a1);\n v7 = k++;\n *(_DWORD *)(a3 + 4LL * v7) = *v6;\n v3 = v12--;\n }\n v4 = (_DWORD *)(4LL * v3 + a1);\n v5 = k;\n *(_DWORD *)(a3 + 4LL * v5) = *v4;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, long long a3) {\n int v3;\n uint32_t *v4;\n int v5;\n uint32_t *v6;\n int v7;\n long long result;\n int i;\n int j;\n unsigned int v11;\n int v12;\n int k;\n int v14;\n for (i = 0; i < a2 - 1; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if (*(uint32_t *)(4LL * i + a1) > *(uint32_t *)(4LL * j + a1)) {\n v14 = *(uint32_t *)(4LL * i + a1);\n *(uint32_t *)(4LL * i + a1) = *(uint32_t *)(4LL * j + a1);\n *(uint32_t *)(a1 + 4LL * j) = v14;\n }\n }\n }\n v11 = 0;\n v12 = a2 - 1;\n for (k = 0;; ++k) {\n result = v11;\n if ((int)v11 > v12) break;\n v3 = v11;\n if (v11 == v12) {\n ++v11;\n } else {\n ++v11;\n v6 = (uint32_t *)(4LL * v3 + a1);\n v7 = k++;\n *(uint32_t *)(a3 + 4LL * v7) = *v6;\n v3 = v12--;\n }\n v4 = (uint32_t *)(4LL * v3 + a1);\n v5 = k;\n *(uint32_t *)(a3 + 4LL * v5) = *v4;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3) {\n int v3;\n uint32_t *v4;\n int v5;\n uint32_t *v6;\n int v7;\n long long result;\n int i;\n int j;\n unsigned int v11;\n int v12;\n int k;\n int v14;\n for (i = 0; i < a2 - 1; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if (*(uint32_t *)(4LL * i + a1) > *(uint32_t *)(4LL * j + a1)) {\n v14 = *(uint32_t *)(4LL * i + a1);\n *(uint32_t *)(4LL * i + a1) = *(uint32_t *)(4LL * j + a1);\n *(uint32_t *)(a1 + 4LL * j) = v14;\n }\n }\n }\n v11 = 0;\n v12 = a2 - 1;\n for (k = 0;; ++k) {\n result = v11;\n if ((int)v11 > v12) break;\n v3 = v11;\n if (v11 == v12) {\n ++v11;\n } else {\n ++v11;\n v6 = (uint32_t *)(4LL * v3 + a1);\n v7 = k++;\n *(uint32_t *)(a3 + 4LL * v7) = *v6;\n v3 = v12--;\n }\n v4 = (uint32_t *)(4LL * v3 + a1);\n v5 = k;\n *(uint32_t *)(a3 + 4LL * v5) = *v4;\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-70", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(int *lst, int size, int *out) {\n for (int i = 0; i < size - 1; i++) {\n for (int j = i + 1; j < size; j++) {\n if (lst[i] > lst[j]) {\n int temp = lst[i];\n lst[i] = lst[j];\n lst[j] = temp;\n }\n }\n }\n int l = 0, r = size - 1;\n int index = 0;\n while (l <= r) {\n if (l == r) {\n out[index++] = lst[l++];\n } else {\n out[index++] = lst[l++];\n out[index++] = lst[r--];\n }\n }\n}", + "test": "#include \n#include \n\nint issame(int *a, int *b, int size) {\n for (int i = 0; i < size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int a1[] = {1, 2, 3, 4};\n int e1[] = {1, 4, 2, 3};\n int out1[4];\n func0(a1, 4, out1);\n assert(issame(e1, out1, 4));\n\n int a2[] = {5, 6, 7, 8, 9};\n int e2[] = {5, 9, 6, 8, 7};\n int out2[5];\n func0(a2, 5, out2);\n assert(issame(e2, out2, 5));\n\n int a3[] = {1, 2, 3, 4, 5};\n int e3[] = {1, 5, 2, 4, 3};\n int out3[5];\n func0(a3, 5, out3);\n assert(issame(e3, out3, 5));\n\n int a4[] = {5, 6, 7, 8, 9, 1};\n int e4[] = {1, 9, 5, 8, 6, 7};\n int out4[6];\n func0(a4, 6, out4);\n assert(issame(e4, out4, 6));\n\n int a5[] = {5, 5, 5, 5};\n int e5[] = {5, 5, 5, 5};\n int out5[4];\n func0(a5, 4, out5);\n assert(issame(e5, out5, 4));\n\n int a6[] = {};\n int e6[] = {};\n int out6[0];\n func0(a6, 0, out6);\n assert(issame(e6, out6, 0));\n\n int a7[] = {1, 2, 3, 4, 5, 6, 7, 8};\n int e7[] = {1, 8, 2, 7, 3, 6, 4, 5};\n int out7[8];\n func0(a7, 8, out7);\n assert(issame(e7, out7, 8));\n\n int a8[] = {0, 2, 2, 2, 5, 5, -5, -5};\n int e8[] = {-5, 5, -5, 5, 0, 2, 2, 2};\n int out8[8];\n func0(a8, 8, out8);\n assert(issame(e8, out8, 8));\n\n int a9[] = {111111};\n int e9[] = {111111};\n int out9[1];\n func0(a9, 1, out9);\n assert(issame(e9, out9, 1));\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nmov r10, rdi\nmov r11, rdx\nlea r9d, [rsi-1]\ntest r9d, r9d\njle short loc_11D8\nmov ebx, esi\nlea rsi, [rdi+4]\nmov ebp, ebx\nmov r8d, 1\nmov r13d, r9d\nlea r12, [rdi+8]\njmp short loc_11BF\nloc_1199:\nadd rax, 4\ncmp rax, rdi\njz short loc_11B2\nloc_11A2:\nmov edx, [rsi-4]\nmov ecx, [rax]\ncmp edx, ecx\njle short loc_1199\nmov [rsi-4], ecx\nmov [rax], edx\njmp short loc_1199\nloc_11B2:\nadd r8, 1\nadd rsi, 4\ncmp r8, rbp\njz short loc_11DA\nloc_11BF:\ncmp ebx, r8d\njle short loc_11B2\nmov eax, r13d\nsub eax, r8d\nlea rax, [r8+rax-1]\nlea rdi, [r12+rax*4]\nmov rax, rsi\njmp short loc_11A2\nloc_11D8:\njs short loc_1214\nloc_11DA:\nmovsxd rdx, r9d\nmov eax, 0\njmp short loc_1201\nloc_11E4:\nmov ecx, [r10+rax*4]\nmov [r11+rax*8], ecx\nmov ecx, [r10+rdx*4]\nmov [r11+rax*8+4], ecx\nadd rax, 1\nsub rdx, 1\ncmp eax, edx\njg short loc_1214\nloc_1201:\ncmp edx, eax\njnz short loc_11E4\nmovsxd rdx, eax\nmov edx, [r10+rdx*4]\nadd eax, eax\ncdqe\nmov [r11+rax*4], edx\nloc_1214:\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2, __int64 a3)\n{\n int v4; // r9d\n _DWORD *v6; // rsi\n __int64 v7; // r8\n _DWORD *v8; // rax\n int v9; // edx\n __int64 v10; // rdx\n __int64 v11; // rax\n\n v4 = a2 - 1;\n if ( a2 - 1 <= 0 )\n {\n if ( v4 < 0 )\n return;\n }\n else\n {\n v6 = (_DWORD *)(a1 + 4);\n v7 = 1LL;\n do\n {\n if ( a2 > (int)v7 )\n {\n v8 = v6;\n do\n {\n v9 = *(v6 - 1);\n if ( v9 > *v8 )\n {\n *(v6 - 1) = *v8;\n *v8 = v9;\n }\n ++v8;\n }\n while ( v8 != (_DWORD *)(a1 + 8 + 4 * (v7 + (unsigned int)(v4 - v7) - 1)) );\n }\n ++v7;\n ++v6;\n }\n while ( v7 != a2 );\n }\n v10 = v4;\n v11 = 0LL;\n while ( (_DWORD)v10 != (_DWORD)v11 )\n {\n *(_DWORD *)(a3 + 8 * v11) = *(_DWORD *)(a1 + 4 * v11);\n *(_DWORD *)(a3 + 8 * v11++ + 4) = *(_DWORD *)(a1 + 4 * v10);\n if ( (int)v11 > (int)--v10 )\n return;\n }\n *(_DWORD *)(a3 + 8LL * (_DWORD)v11) = *(_DWORD *)(a1 + 4LL * (int)v11);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nmov r10, rdi\nmov r11, rdx\nlea r9d, [rsi-1]\ntest r9d, r9d\njle short loc_11D8\nmov ebx, esi\nlea rsi, [rdi+4]\nmov ebp, ebx\nmov r8d, 1\nmov r13d, r9d\nlea r12, [rdi+8]\njmp short loc_11BF\nloc_1199:\nadd rax, 4\ncmp rax, rdi\njz short loc_11B2\nloc_11A2:\nmov edx, [rsi-4]\nmov ecx, [rax]\ncmp edx, ecx\njle short loc_1199\nmov [rsi-4], ecx\nmov [rax], edx\njmp short loc_1199\nloc_11B2:\nadd r8, 1\nadd rsi, 4\ncmp r8, rbp\njz short loc_11DA\nloc_11BF:\ncmp ebx, r8d\njle short loc_11B2\nmov eax, r13d\nsub eax, r8d\nlea rax, [r8+rax-1]\nlea rdi, [r12+rax*4]\nmov rax, rsi\njmp short loc_11A2\nloc_11D8:\njs short loc_1214\nloc_11DA:\nmovsxd rdx, r9d\nmov eax, 0\njmp short loc_1201\nloc_11E4:\nmov ecx, [r10+rax*4]\nmov [r11+rax*8], ecx\nmov ecx, [r10+rdx*4]\nmov [r11+rax*8+4], ecx\nadd rax, 1\nsub rdx, 1\ncmp eax, edx\njg short loc_1214\nloc_1201:\ncmp edx, eax\njnz short loc_11E4\nmovsxd rdx, eax\nmov edx, [r10+rdx*4]\nadd eax, eax\ncdqe\nmov [r11+rax*4], edx\nloc_1214:\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "void __fastcall sub_1169(__int64 a1, int a2, __int64 a3)\n{\n int v4; // r9d\n _DWORD *v6; // rsi\n __int64 v7; // r8\n _DWORD *v8; // rax\n int v9; // edx\n __int64 v10; // rdx\n __int64 v11; // rax\n\n v4 = a2 - 1;\n if ( a2 - 1 <= 0 )\n {\n if ( v4 < 0 )\n return;\n }\n else\n {\n v6 = (_DWORD *)(a1 + 4);\n v7 = 1LL;\n do\n {\n if ( a2 > (int)v7 )\n {\n v8 = v6;\n do\n {\n v9 = *(v6 - 1);\n if ( v9 > *v8 )\n {\n *(v6 - 1) = *v8;\n *v8 = v9;\n }\n ++v8;\n }\n while ( v8 != (_DWORD *)(a1 + 8 + 4 * (v7 + (unsigned int)(v4 - v7) - 1)) );\n }\n ++v7;\n ++v6;\n }\n while ( v7 != a2 );\n }\n v10 = v4;\n v11 = 0LL;\n while ( (_DWORD)v10 != (_DWORD)v11 )\n {\n *(_DWORD *)(a3 + 8 * v11) = *(_DWORD *)(a1 + 4 * v11);\n *(_DWORD *)(a3 + 8 * v11++ + 4) = *(_DWORD *)(a1 + 4 * v10);\n if ( (int)v11 > (int)--v10 )\n return;\n }\n *(_DWORD *)(a3 + 8LL * (_DWORD)v11) = *(_DWORD *)(a1 + 4LL * (int)v11);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1169(long long a1, int a2, long long a3) {\n int v4;\n uint32_t *v6;\n long long v7;\n uint32_t *v8;\n int v9;\n long long v10;\n long long v11;\n v4 = a2 - 1;\n if (a2 - 1 <= 0) {\n if (v4 < 0) return;\n } else {\n v6 = (uint32_t *)(a1 + 4);\n v7 = 1LL;\n do {\n if (a2 > (int)v7) {\n v8 = v6;\n do {\n v9 = *(v6 - 1);\n if (v9 > *v8) {\n *(v6 - 1) = *v8;\n *v8 = v9;\n }\n ++v8;\n } while (v8 !=\n (uint32_t *)(a1 + 8 + 4 * (v7 + (unsigned int)(v4 - v7) - 1)));\n }\n ++v7;\n ++v6;\n } while (v7 != a2);\n }\n v10 = v4;\n v11 = 0LL;\n while ((uint32_t)v10 != (uint32_t)v11) {\n *(uint32_t *)(a3 + 8 * v11) = *(uint32_t *)(a1 + 4 * v11);\n *(uint32_t *)(a3 + 8 * v11++ + 4) = *(uint32_t *)(a1 + 4 * v10);\n if ((int)v11 > (int)--v10) return;\n }\n *(uint32_t *)(a3 + 8LL * (uint32_t)v11) = *(uint32_t *)(a1 + 4LL * (int)v11);\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2, long long a3) {\n int v4;\n uint32_t *v6;\n long long v7;\n uint32_t *v8;\n int v9;\n long long v10;\n long long v11;\n v4 = a2 - 1;\n if (a2 - 1 <= 0) {\n if (v4 < 0) return;\n } else {\n v6 = (uint32_t *)(a1 + 4);\n v7 = 1LL;\n do {\n if (a2 > (int)v7) {\n v8 = v6;\n do {\n v9 = *(v6 - 1);\n if (v9 > *v8) {\n *(v6 - 1) = *v8;\n *v8 = v9;\n }\n ++v8;\n } while (v8 !=\n (uint32_t *)(a1 + 8 + 4 * (v7 + (unsigned int)(v4 - v7) - 1)));\n }\n ++v7;\n ++v6;\n } while (v7 != a2);\n }\n v10 = v4;\n v11 = 0LL;\n while ((uint32_t)v10 != (uint32_t)v11) {\n *(uint32_t *)(a3 + 8 * v11) = *(uint32_t *)(a1 + 4 * v11);\n *(uint32_t *)(a3 + 8 * v11++ + 4) = *(uint32_t *)(a1 + 4 * v10);\n if ((int)v11 > (int)--v10) return;\n }\n *(uint32_t *)(a3 + 8LL * (uint32_t)v11) = *(uint32_t *)(a1 + 4LL * (int)v11);\n}" + }, + { + "index": "HumanEval-C-70", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(int *lst, int size, int *out) {\n for (int i = 0; i < size - 1; i++) {\n for (int j = i + 1; j < size; j++) {\n if (lst[i] > lst[j]) {\n int temp = lst[i];\n lst[i] = lst[j];\n lst[j] = temp;\n }\n }\n }\n int l = 0, r = size - 1;\n int index = 0;\n while (l <= r) {\n if (l == r) {\n out[index++] = lst[l++];\n } else {\n out[index++] = lst[l++];\n out[index++] = lst[r--];\n }\n }\n}", + "test": "#include \n#include \n\nint issame(int *a, int *b, int size) {\n for (int i = 0; i < size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int a1[] = {1, 2, 3, 4};\n int e1[] = {1, 4, 2, 3};\n int out1[4];\n func0(a1, 4, out1);\n assert(issame(e1, out1, 4));\n\n int a2[] = {5, 6, 7, 8, 9};\n int e2[] = {5, 9, 6, 8, 7};\n int out2[5];\n func0(a2, 5, out2);\n assert(issame(e2, out2, 5));\n\n int a3[] = {1, 2, 3, 4, 5};\n int e3[] = {1, 5, 2, 4, 3};\n int out3[5];\n func0(a3, 5, out3);\n assert(issame(e3, out3, 5));\n\n int a4[] = {5, 6, 7, 8, 9, 1};\n int e4[] = {1, 9, 5, 8, 6, 7};\n int out4[6];\n func0(a4, 6, out4);\n assert(issame(e4, out4, 6));\n\n int a5[] = {5, 5, 5, 5};\n int e5[] = {5, 5, 5, 5};\n int out5[4];\n func0(a5, 4, out5);\n assert(issame(e5, out5, 4));\n\n int a6[] = {};\n int e6[] = {};\n int out6[0];\n func0(a6, 0, out6);\n assert(issame(e6, out6, 0));\n\n int a7[] = {1, 2, 3, 4, 5, 6, 7, 8};\n int e7[] = {1, 8, 2, 7, 3, 6, 4, 5};\n int out7[8];\n func0(a7, 8, out7);\n assert(issame(e7, out7, 8));\n\n int a8[] = {0, 2, 2, 2, 5, 5, -5, -5};\n int e8[] = {-5, 5, -5, 5, 0, 2, 2, 2};\n int out8[8];\n func0(a8, 8, out8);\n assert(issame(e8, out8, 8));\n\n int a9[] = {111111};\n int e9[] = {111111};\n int out9[1];\n func0(a9, 1, out9);\n assert(issame(e9, out9, 1));\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r12\nmov r11, rdi\npush rbp\nmov ebp, esi\nlea r10d, [rbp-1]\npush rbx\ntest r10d, r10d\njle loc_1696\nmov rbx, rbp\nadd rdi, 4\nmov r9d, 1\nlea r12, [r11+8]\nnop dword ptr [rax+rax+00h]\nloc_1620:\ncmp ebx, r9d\njle short loc_1657\nmov eax, r10d\nsub eax, r9d\nlea rax, [r9+rax-1]\nlea r8, [r12+rax*4]\nmov rax, rdi\nnop word ptr [rax+rax+00000000h]\nloc_1640:\nmov ecx, [rdi-4]\nmov esi, [rax]\ncmp ecx, esi\njle short loc_164E\nmov [rdi-4], esi\nmov [rax], ecx\nloc_164E:\nadd rax, 4\ncmp rax, r8\njnz short loc_1640\nloc_1657:\nadd r9, 1\nadd rdi, 4\ncmp r9, rbp\njnz short loc_1620\nloc_1664:\nmovsxd rax, r10d\nxor ecx, ecx\njmp short loc_1687\nloc_1670:\nmov esi, [r11+rax*4]\nadd rcx, 1\nsub rax, 1\nadd rdx, 8\nmov [rdx-4], esi\ncmp ecx, eax\njg short loc_1691\nloc_1687:\nmov esi, [r11+rcx*4]\nmov [rdx], esi\ncmp ecx, eax\njnz short loc_1670\nloc_1691:\npop rbx\npop rbp\npop r12\nretn\nloc_1696:\njz short loc_1664\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2, _DWORD *a3)\n{\n int v4; // r10d\n _DWORD *v5; // rdi\n __int64 v6; // r9\n _DWORD *v7; // rax\n int v8; // ecx\n __int64 v9; // rax\n __int64 v10; // rcx\n int v11; // esi\n\n v4 = a2 - 1;\n if ( a2 - 1 <= 0 )\n {\n if ( a2 != 1 )\n return;\n }\n else\n {\n v5 = (_DWORD *)(a1 + 4);\n v6 = 1LL;\n do\n {\n if ( a2 > (int)v6 )\n {\n v7 = v5;\n do\n {\n v8 = *(v5 - 1);\n if ( v8 > *v7 )\n {\n *(v5 - 1) = *v7;\n *v7 = v8;\n }\n ++v7;\n }\n while ( v7 != (_DWORD *)(a1 + 8 + 4 * (v6 + (unsigned int)(v4 - v6) - 1)) );\n }\n ++v6;\n ++v5;\n }\n while ( v6 != a2 );\n }\n v9 = v4;\n v10 = 0LL;\n do\n {\n *a3 = *(_DWORD *)(a1 + 4 * v10);\n if ( (_DWORD)v10 == (_DWORD)v9 )\n break;\n v11 = *(_DWORD *)(a1 + 4 * v9);\n ++v10;\n --v9;\n a3 += 2;\n *(a3 - 1) = v11;\n }\n while ( (int)v10 <= (int)v9 );\n}", + "ida_strip_asm": "sub_15F0:\nendbr64\npush r12\nmov r11, rdi\npush rbp\nmov ebp, esi\nlea r10d, [rbp-1]\npush rbx\ntest r10d, r10d\njle loc_1696\nmov rbx, rbp\nadd rdi, 4\nmov r9d, 1\nlea r12, [r11+8]\nnop dword ptr [rax+rax+00h]\nloc_1620:\ncmp ebx, r9d\njle short loc_1657\nmov eax, r10d\nsub eax, r9d\nlea rax, [r9+rax-1]\nlea r8, [r12+rax*4]\nmov rax, rdi\nnop word ptr [rax+rax+00000000h]\nloc_1640:\nmov ecx, [rdi-4]\nmov esi, [rax]\ncmp ecx, esi\njle short loc_164E\nmov [rdi-4], esi\nmov [rax], ecx\nloc_164E:\nadd rax, 4\ncmp rax, r8\njnz short loc_1640\nloc_1657:\nadd r9, 1\nadd rdi, 4\ncmp r9, rbp\njnz short loc_1620\nloc_1664:\nmovsxd rax, r10d\nxor ecx, ecx\njmp short loc_1687\nloc_1670:\nmov esi, [r11+rax*4]\nadd rcx, 1\nsub rax, 1\nadd rdx, 8\nmov [rdx-4], esi\ncmp ecx, eax\njg short loc_1691\nloc_1687:\nmov esi, [r11+rcx*4]\nmov [rdx], esi\ncmp ecx, eax\njnz short loc_1670\nloc_1691:\npop rbx\npop rbp\npop r12\nretn\nloc_1696:\njz short loc_1664\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "void __fastcall sub_15F0(__int64 a1, int a2, _DWORD *a3)\n{\n int v4; // r10d\n _DWORD *v5; // rdi\n __int64 v6; // r9\n _DWORD *v7; // rax\n int v8; // ecx\n __int64 v9; // rax\n __int64 v10; // rcx\n int v11; // esi\n\n v4 = a2 - 1;\n if ( a2 - 1 <= 0 )\n {\n if ( a2 != 1 )\n return;\n }\n else\n {\n v5 = (_DWORD *)(a1 + 4);\n v6 = 1LL;\n do\n {\n if ( a2 > (int)v6 )\n {\n v7 = v5;\n do\n {\n v8 = *(v5 - 1);\n if ( v8 > *v7 )\n {\n *(v5 - 1) = *v7;\n *v7 = v8;\n }\n ++v7;\n }\n while ( v7 != (_DWORD *)(a1 + 8 + 4 * (v6 + (unsigned int)(v4 - v6) - 1)) );\n }\n ++v6;\n ++v5;\n }\n while ( v6 != a2 );\n }\n v9 = v4;\n v10 = 0LL;\n do\n {\n *a3 = *(_DWORD *)(a1 + 4 * v10);\n if ( (_DWORD)v10 == (_DWORD)v9 )\n break;\n v11 = *(_DWORD *)(a1 + 4 * v9);\n ++v10;\n --v9;\n a3 += 2;\n *(a3 - 1) = v11;\n }\n while ( (int)v10 <= (int)v9 );\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_15F0(long long a1, int a2, uint32_t *a3) {\n int v4;\n uint32_t *v5;\n long long v6;\n uint32_t *v7;\n int v8;\n long long v9;\n long long v10;\n int v11;\n v4 = a2 - 1;\n if (a2 - 1 <= 0) {\n if (a2 != 1) return;\n } else {\n v5 = (uint32_t *)(a1 + 4);\n v6 = 1LL;\n do {\n if (a2 > (int)v6) {\n v7 = v5;\n do {\n v8 = *(v5 - 1);\n if (v8 > *v7) {\n *(v5 - 1) = *v7;\n *v7 = v8;\n }\n ++v7;\n } while (v7 !=\n (uint32_t *)(a1 + 8 + 4 * (v6 + (unsigned int)(v4 - v6) - 1)));\n }\n ++v6;\n ++v5;\n } while (v6 != a2);\n }\n v9 = v4;\n v10 = 0LL;\n do {\n *a3 = *(uint32_t *)(a1 + 4 * v10);\n if ((uint32_t)v10 == (uint32_t)v9) break;\n v11 = *(uint32_t *)(a1 + 4 * v9);\n ++v10;\n --v9;\n a3 += 2;\n *(a3 - 1) = v11;\n } while ((int)v10 <= (int)v9);\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2, uint32_t *a3) {\n int v4;\n uint32_t *v5;\n long long v6;\n uint32_t *v7;\n int v8;\n long long v9;\n long long v10;\n int v11;\n v4 = a2 - 1;\n if (a2 - 1 <= 0) {\n if (a2 != 1) return;\n } else {\n v5 = (uint32_t *)(a1 + 4);\n v6 = 1LL;\n do {\n if (a2 > (int)v6) {\n v7 = v5;\n do {\n v8 = *(v5 - 1);\n if (v8 > *v7) {\n *(v5 - 1) = *v7;\n *v7 = v8;\n }\n ++v7;\n } while (v7 !=\n (uint32_t *)(a1 + 8 + 4 * (v6 + (unsigned int)(v4 - v6) - 1)));\n }\n ++v6;\n ++v5;\n } while (v6 != a2);\n }\n v9 = v4;\n v10 = 0LL;\n do {\n *a3 = *(uint32_t *)(a1 + 4 * v10);\n if ((uint32_t)v10 == (uint32_t)v9) break;\n v11 = *(uint32_t *)(a1 + 4 * v9);\n ++v10;\n --v9;\n a3 += 2;\n *(a3 - 1) = v11;\n } while ((int)v10 <= (int)v9);\n}" + }, + { + "index": "HumanEval-C-70", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(int *lst, int size, int *out) {\n for (int i = 0; i < size - 1; i++) {\n for (int j = i + 1; j < size; j++) {\n if (lst[i] > lst[j]) {\n int temp = lst[i];\n lst[i] = lst[j];\n lst[j] = temp;\n }\n }\n }\n int l = 0, r = size - 1;\n int index = 0;\n while (l <= r) {\n if (l == r) {\n out[index++] = lst[l++];\n } else {\n out[index++] = lst[l++];\n out[index++] = lst[r--];\n }\n }\n}", + "test": "#include \n#include \n\nint issame(int *a, int *b, int size) {\n for (int i = 0; i < size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int a1[] = {1, 2, 3, 4};\n int e1[] = {1, 4, 2, 3};\n int out1[4];\n func0(a1, 4, out1);\n assert(issame(e1, out1, 4));\n\n int a2[] = {5, 6, 7, 8, 9};\n int e2[] = {5, 9, 6, 8, 7};\n int out2[5];\n func0(a2, 5, out2);\n assert(issame(e2, out2, 5));\n\n int a3[] = {1, 2, 3, 4, 5};\n int e3[] = {1, 5, 2, 4, 3};\n int out3[5];\n func0(a3, 5, out3);\n assert(issame(e3, out3, 5));\n\n int a4[] = {5, 6, 7, 8, 9, 1};\n int e4[] = {1, 9, 5, 8, 6, 7};\n int out4[6];\n func0(a4, 6, out4);\n assert(issame(e4, out4, 6));\n\n int a5[] = {5, 5, 5, 5};\n int e5[] = {5, 5, 5, 5};\n int out5[4];\n func0(a5, 4, out5);\n assert(issame(e5, out5, 4));\n\n int a6[] = {};\n int e6[] = {};\n int out6[0];\n func0(a6, 0, out6);\n assert(issame(e6, out6, 0));\n\n int a7[] = {1, 2, 3, 4, 5, 6, 7, 8};\n int e7[] = {1, 8, 2, 7, 3, 6, 4, 5};\n int out7[8];\n func0(a7, 8, out7);\n assert(issame(e7, out7, 8));\n\n int a8[] = {0, 2, 2, 2, 5, 5, -5, -5};\n int e8[] = {-5, 5, -5, 5, 0, 2, 2, 2};\n int out8[8];\n func0(a8, 8, out8);\n assert(issame(e8, out8, 8));\n\n int a9[] = {111111};\n int e9[] = {111111};\n int out9[1];\n func0(a9, 1, out9);\n assert(issame(e9, out9, 1));\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r12\nmov r11, rdi\npush rbp\nmov ebp, esi\nlea r10d, [rbp-1]\npush rbx\ntest r10d, r10d\njle loc_16B6\nmov rbx, rbp\nadd rdi, 4\nmov r9d, 1\nlea r12, [r11+8]\nnop dword ptr [rax+rax+00h]\nloc_1640:\ncmp ebx, r9d\njle short loc_1677\nmov eax, r10d\nsub eax, r9d\nlea rax, [r9+rax-1]\nlea r8, [r12+rax*4]\nmov rax, rdi\nnop word ptr [rax+rax+00000000h]\nloc_1660:\nmov ecx, [rdi-4]\nmov esi, [rax]\ncmp ecx, esi\njle short loc_166E\nmov [rdi-4], esi\nmov [rax], ecx\nloc_166E:\nadd rax, 4\ncmp r8, rax\njnz short loc_1660\nloc_1677:\nadd r9, 1\nadd rdi, 4\ncmp r9, rbp\njnz short loc_1640\nloc_1684:\nmovsxd rax, r10d\nxor ecx, ecx\njmp short loc_16A7\nloc_1690:\nmov esi, [r11+rax*4]\nadd rcx, 1\nsub rax, 1\nadd rdx, 8\nmov [rdx-4], esi\ncmp eax, ecx\njl short loc_16B1\nloc_16A7:\nmov esi, [r11+rcx*4]\nmov [rdx], esi\ncmp ecx, eax\njnz short loc_1690\nloc_16B1:\npop rbx\npop rbp\npop r12\nretn\nloc_16B6:\njz short loc_1684\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2, _DWORD *a3)\n{\n int v4; // r10d\n _DWORD *v5; // rdi\n __int64 v6; // r9\n _DWORD *v7; // rax\n int v8; // ecx\n __int64 v9; // rax\n __int64 v10; // rcx\n int v11; // esi\n\n v4 = a2 - 1;\n if ( a2 - 1 <= 0 )\n {\n if ( a2 != 1 )\n return;\n }\n else\n {\n v5 = (_DWORD *)(a1 + 4);\n v6 = 1LL;\n do\n {\n if ( a2 > (int)v6 )\n {\n v7 = v5;\n do\n {\n v8 = *(v5 - 1);\n if ( v8 > *v7 )\n {\n *(v5 - 1) = *v7;\n *v7 = v8;\n }\n ++v7;\n }\n while ( (_DWORD *)(a1 + 8 + 4 * (v6 + (unsigned int)(v4 - v6) - 1)) != v7 );\n }\n ++v6;\n ++v5;\n }\n while ( v6 != a2 );\n }\n v9 = v4;\n v10 = 0LL;\n do\n {\n *a3 = *(_DWORD *)(a1 + 4 * v10);\n if ( (_DWORD)v10 == (_DWORD)v9 )\n break;\n v11 = *(_DWORD *)(a1 + 4 * v9);\n ++v10;\n --v9;\n a3 += 2;\n *(a3 - 1) = v11;\n }\n while ( (int)v9 >= (int)v10 );\n}", + "ida_strip_asm": "sub_1610:\nendbr64\npush r12\nmov r11, rdi\npush rbp\nmov ebp, esi\nlea r10d, [rbp-1]\npush rbx\ntest r10d, r10d\njle loc_16B6\nmov rbx, rbp\nadd rdi, 4\nmov r9d, 1\nlea r12, [r11+8]\nnop dword ptr [rax+rax+00h]\nloc_1640:\ncmp ebx, r9d\njle short loc_1677\nmov eax, r10d\nsub eax, r9d\nlea rax, [r9+rax-1]\nlea r8, [r12+rax*4]\nmov rax, rdi\nnop word ptr [rax+rax+00000000h]\nloc_1660:\nmov ecx, [rdi-4]\nmov esi, [rax]\ncmp ecx, esi\njle short loc_166E\nmov [rdi-4], esi\nmov [rax], ecx\nloc_166E:\nadd rax, 4\ncmp r8, rax\njnz short loc_1660\nloc_1677:\nadd r9, 1\nadd rdi, 4\ncmp r9, rbp\njnz short loc_1640\nloc_1684:\nmovsxd rax, r10d\nxor ecx, ecx\njmp short loc_16A7\nloc_1690:\nmov esi, [r11+rax*4]\nadd rcx, 1\nsub rax, 1\nadd rdx, 8\nmov [rdx-4], esi\ncmp eax, ecx\njl short loc_16B1\nloc_16A7:\nmov esi, [r11+rcx*4]\nmov [rdx], esi\ncmp ecx, eax\njnz short loc_1690\nloc_16B1:\npop rbx\npop rbp\npop r12\nretn\nloc_16B6:\njz short loc_1684\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "void __fastcall sub_1610(__int64 a1, int a2, _DWORD *a3)\n{\n int v4; // r10d\n _DWORD *v5; // rdi\n __int64 v6; // r9\n _DWORD *v7; // rax\n int v8; // ecx\n __int64 v9; // rax\n __int64 v10; // rcx\n int v11; // esi\n\n v4 = a2 - 1;\n if ( a2 - 1 <= 0 )\n {\n if ( a2 != 1 )\n return;\n }\n else\n {\n v5 = (_DWORD *)(a1 + 4);\n v6 = 1LL;\n do\n {\n if ( a2 > (int)v6 )\n {\n v7 = v5;\n do\n {\n v8 = *(v5 - 1);\n if ( v8 > *v7 )\n {\n *(v5 - 1) = *v7;\n *v7 = v8;\n }\n ++v7;\n }\n while ( (_DWORD *)(a1 + 8 + 4 * (v6 + (unsigned int)(v4 - v6) - 1)) != v7 );\n }\n ++v6;\n ++v5;\n }\n while ( v6 != a2 );\n }\n v9 = v4;\n v10 = 0LL;\n do\n {\n *a3 = *(_DWORD *)(a1 + 4 * v10);\n if ( (_DWORD)v10 == (_DWORD)v9 )\n break;\n v11 = *(_DWORD *)(a1 + 4 * v9);\n ++v10;\n --v9;\n a3 += 2;\n *(a3 - 1) = v11;\n }\n while ( (int)v9 >= (int)v10 );\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1610(long long a1, int a2, uint32_t *a3) {\n int v4;\n uint32_t *v5;\n long long v6;\n uint32_t *v7;\n int v8;\n long long v9;\n long long v10;\n int v11;\n v4 = a2 - 1;\n if (a2 - 1 <= 0) {\n if (a2 != 1) return;\n } else {\n v5 = (uint32_t *)(a1 + 4);\n v6 = 1LL;\n do {\n if (a2 > (int)v6) {\n v7 = v5;\n do {\n v8 = *(v5 - 1);\n if (v8 > *v7) {\n *(v5 - 1) = *v7;\n *v7 = v8;\n }\n ++v7;\n } while ((uint32_t *)(a1 + 8 +\n 4 * (v6 + (unsigned int)(v4 - v6) - 1)) != v7);\n }\n ++v6;\n ++v5;\n } while (v6 != a2);\n }\n v9 = v4;\n v10 = 0LL;\n do {\n *a3 = *(uint32_t *)(a1 + 4 * v10);\n if ((uint32_t)v10 == (uint32_t)v9) break;\n v11 = *(uint32_t *)(a1 + 4 * v9);\n ++v10;\n --v9;\n a3 += 2;\n *(a3 - 1) = v11;\n } while ((int)v9 >= (int)v10);\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2, uint32_t *a3) {\n int v4;\n uint32_t *v5;\n long long v6;\n uint32_t *v7;\n int v8;\n long long v9;\n long long v10;\n int v11;\n v4 = a2 - 1;\n if (a2 - 1 <= 0) {\n if (a2 != 1) return;\n } else {\n v5 = (uint32_t *)(a1 + 4);\n v6 = 1LL;\n do {\n if (a2 > (int)v6) {\n v7 = v5;\n do {\n v8 = *(v5 - 1);\n if (v8 > *v7) {\n *(v5 - 1) = *v7;\n *v7 = v8;\n }\n ++v7;\n } while ((uint32_t *)(a1 + 8 +\n 4 * (v6 + (unsigned int)(v4 - v6) - 1)) != v7);\n }\n ++v6;\n ++v5;\n } while (v6 != a2);\n }\n v9 = v4;\n v10 = 0LL;\n do {\n *a3 = *(uint32_t *)(a1 + 4 * v10);\n if ((uint32_t)v10 == (uint32_t)v9) break;\n v11 = *(uint32_t *)(a1 + 4 * v9);\n ++v10;\n --v9;\n a3 += 2;\n *(a3 - 1) = v11;\n } while ((int)v9 >= (int)v10);\n}" + }, + { + "index": "HumanEval-C-71", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "float func0(float a, float b, float c) {\n if (a + b <= c || a + c <= b || b + c <= a) return -1;\n float s = (a + b + c) / 2;\n float area = sqrtf(s * (s - a) * (s - b) * (s - c));\n return roundf(area * 100) / 100;\n}", + "test": "#include \n#include \n#include \n\nint main() {\n assert(fabs(func0(3, 4, 5) - 6.00) < 0.01);\n assert(fabs(func0(1, 2, 10) + 1) < 0.01);\n assert(fabs(func0(4, 8, 5) - 8.18) < 0.01);\n assert(fabs(func0(2, 2, 2) - 1.73) < 0.01);\n assert(fabs(func0(1, 2, 3) + 1) < 0.01);\n assert(fabs(func0(10, 5, 7) - 16.25) < 0.01);\n assert(fabs(func0(2, 6, 3) + 1) < 0.01);\n assert(fabs(func0(1, 1, 1) - 0.43) < 0.01);\n assert(fabs(func0(2, 2, 10) + 1) < 0.01);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmovss [rbp+var_14], xmm0\nmovss [rbp+var_18], xmm1\nmovss [rbp+var_1C], xmm2\nmovss xmm0, [rbp+var_14]\nmovaps xmm1, xmm0\naddss xmm1, [rbp+var_18]\nmovss xmm0, [rbp+var_1C]\ncomiss xmm0, xmm1\njnb short loc_11E9\nmovss xmm0, [rbp+var_14]\nmovaps xmm1, xmm0\naddss xmm1, [rbp+var_1C]\nmovss xmm0, [rbp+var_18]\ncomiss xmm0, xmm1\njnb short loc_11E9\nmovss xmm0, [rbp+var_18]\nmovaps xmm1, xmm0\naddss xmm1, [rbp+var_1C]\nmovss xmm0, [rbp+var_14]\ncomiss xmm0, xmm1\njb short loc_11F6\nloc_11E9:\nmovss xmm0, cs:dword_2188\njmp locret_128A\nloc_11F6:\nmovss xmm0, [rbp+var_14]\naddss xmm0, [rbp+var_18]\naddss xmm0, [rbp+var_1C]\nmovss xmm1, cs:dword_218C\ndivss xmm0, xmm1\nmovss [rbp+var_8], xmm0\nmovss xmm0, [rbp+var_8]\nsubss xmm0, [rbp+var_14]\nmovaps xmm1, xmm0\nmulss xmm1, [rbp+var_8]\nmovss xmm0, [rbp+var_8]\nsubss xmm0, [rbp+var_18]\nmulss xmm1, xmm0\nmovss xmm0, [rbp+var_8]\nsubss xmm0, [rbp+var_1C]\nmulss xmm1, xmm0\nmovd eax, xmm1\nmovd xmm0, eax; x\ncall _sqrtf\nmovd eax, xmm0\nmov [rbp+var_4], eax\nmovss xmm1, [rbp+var_4]\nmovss xmm0, cs:dword_2190\nmulss xmm1, xmm0\nmovd eax, xmm1\nmovd xmm0, eax; x\ncall _roundf\nmovd eax, xmm0\nmovss xmm1, cs:dword_2190\nmovd xmm0, eax\ndivss xmm0, xmm1\nlocret_128A:\nleave\nretn", + "ida_pseudo": "float __fastcall func0(float a1, float a2, float a3)\n{\n __m128i v4; // xmm0\n __m128i v5; // xmm1\n __m128i v6; // xmm0\n __m128i v7; // xmm1\n __m128i v8; // xmm0\n unsigned int v11; // [rsp+18h] [rbp-8h]\n float v12; // [rsp+1Ch] [rbp-4h]\n\n if ( a3 >= (float)(a1 + a2) || a2 >= (float)(a1 + a3) || a1 >= (float)(a2 + a3) )\n return -1.0;\n *(float *)&v11 = (float)((float)(a1 + a2) + a3) / 2.0;\n v4 = (__m128i)v11;\n *(float *)v4.m128i_i32 = *(float *)&v11 - a1;\n v5 = v4;\n *(float *)v5.m128i_i32 = (float)((float)((float)(*(float *)&v11 - a1) * *(float *)&v11)\n * (float)((float)((float)((float)(a1 + a2) + a3) / 2.0) - a2))\n * (float)((float)((float)((float)(a1 + a2) + a3) / 2.0) - a3);\n v6 = _mm_cvtsi32_si128(_mm_cvtsi128_si32(v5));\n *(float *)v6.m128i_i32 = sqrtf(*(float *)v6.m128i_i32);\n v12 = COERCE_FLOAT(_mm_cvtsi128_si32(v6));\n v7 = (__m128i)LODWORD(v12);\n *(float *)v7.m128i_i32 = v12 * 100.0;\n v8 = _mm_cvtsi32_si128(_mm_cvtsi128_si32(v7));\n *(float *)v8.m128i_i32 = roundf(*(float *)v8.m128i_i32);\n return COERCE_FLOAT(_mm_cvtsi128_si32(v8)) / 100.0;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmovss [rbp+var_14], xmm0\nmovss [rbp+var_18], xmm1\nmovss [rbp+var_1C], xmm2\nmovss xmm0, [rbp+var_14]\nmovaps xmm1, xmm0\naddss xmm1, [rbp+var_18]\nmovss xmm0, [rbp+var_1C]\ncomiss xmm0, xmm1\njnb short loc_11E9\nmovss xmm0, [rbp+var_14]\nmovaps xmm1, xmm0\naddss xmm1, [rbp+var_1C]\nmovss xmm0, [rbp+var_18]\ncomiss xmm0, xmm1\njnb short loc_11E9\nmovss xmm0, [rbp+var_18]\nmovaps xmm1, xmm0\naddss xmm1, [rbp+var_1C]\nmovss xmm0, [rbp+var_14]\ncomiss xmm0, xmm1\njb short loc_11F6\nloc_11E9:\nmovss xmm0, cs:dword_2188\njmp locret_128A\nloc_11F6:\nmovss xmm0, [rbp+var_14]\naddss xmm0, [rbp+var_18]\naddss xmm0, [rbp+var_1C]\nmovss xmm1, cs:dword_218C\ndivss xmm0, xmm1\nmovss [rbp+var_8], xmm0\nmovss xmm0, [rbp+var_8]\nsubss xmm0, [rbp+var_14]\nmovaps xmm1, xmm0\nmulss xmm1, [rbp+var_8]\nmovss xmm0, [rbp+var_8]\nsubss xmm0, [rbp+var_18]\nmulss xmm1, xmm0\nmovss xmm0, [rbp+var_8]\nsubss xmm0, [rbp+var_1C]\nmulss xmm1, xmm0\nmovd eax, xmm1\nmovd xmm0, eax; x\ncall _sqrtf\nmovd eax, xmm0\nmov [rbp+var_4], eax\nmovss xmm1, [rbp+var_4]\nmovss xmm0, cs:dword_2190\nmulss xmm1, xmm0\nmovd eax, xmm1\nmovd xmm0, eax; x\ncall _roundf\nmovd eax, xmm0\nmovss xmm1, cs:dword_2190\nmovd xmm0, eax\ndivss xmm0, xmm1\nlocret_128A:\nleave\nretn", + "ida_strip_pseudo": "float __fastcall sub_1189(float a1, float a2, float a3)\n{\n __m128i v4; // xmm0\n __m128i v5; // xmm1\n __m128i v6; // xmm0\n __m128i v7; // xmm1\n __m128i v8; // xmm0\n unsigned int v11; // [rsp+18h] [rbp-8h]\n float v12; // [rsp+1Ch] [rbp-4h]\n\n if ( a3 >= (float)(a1 + a2) || a2 >= (float)(a1 + a3) || a1 >= (float)(a2 + a3) )\n return -1.0;\n *(float *)&v11 = (float)((float)(a1 + a2) + a3) / 2.0;\n v4 = (__m128i)v11;\n *(float *)v4.m128i_i32 = *(float *)&v11 - a1;\n v5 = v4;\n *(float *)v5.m128i_i32 = (float)((float)((float)(*(float *)&v11 - a1) * *(float *)&v11)\n * (float)((float)((float)((float)(a1 + a2) + a3) / 2.0) - a2))\n * (float)((float)((float)((float)(a1 + a2) + a3) / 2.0) - a3);\n v6 = _mm_cvtsi32_si128(_mm_cvtsi128_si32(v5));\n *(float *)v6.m128i_i32 = sqrtf(*(float *)v6.m128i_i32);\n v12 = COERCE_FLOAT(_mm_cvtsi128_si32(v6));\n v7 = (__m128i)LODWORD(v12);\n *(float *)v7.m128i_i32 = v12 * 100.0;\n v8 = _mm_cvtsi32_si128(_mm_cvtsi128_si32(v7));\n *(float *)v8.m128i_i32 = roundf(*(float *)v8.m128i_i32);\n return COERCE_FLOAT(_mm_cvtsi128_si32(v8)) / 100.0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "float sub_1189(float a1, float a2, float a3) {\n __m128i v4;\n __m128i v5;\n __m128i v6;\n __m128i v7;\n __m128i v8;\n unsigned int v11;\n float v12;\n if (a3 >= (float)(a1 + a2) || a2 >= (float)(a1 + a3) ||\n a1 >= (float)(a2 + a3))\n return -1.0;\n *(float *)&v11 = (float)((float)(a1 + a2) + a3) / 2.0;\n v4 = (__m128i)v11;\n *(float *)v4.m128i_i32 = *(float *)&v11 - a1;\n v5 = v4;\n *(float *)v5.m128i_i32 =\n (float)((float)((float)(*(float *)&v11 - a1) * *(float *)&v11) *\n (float)((float)((float)((float)(a1 + a2) + a3) / 2.0) - a2)) *\n (float)((float)((float)((float)(a1 + a2) + a3) / 2.0) - a3);\n v6 = _mm_cvtsi32_si128(_mm_cvtsi128_si32(v5));\n *(float *)v6.m128i_i32 = sqrtf(*(float *)v6.m128i_i32);\n v12 = COERCE_FLOAT(_mm_cvtsi128_si32(v6));\n v7 = (__m128i)LODWORD(v12);\n *(float *)v7.m128i_i32 = v12 * 100.0;\n v8 = _mm_cvtsi32_si128(_mm_cvtsi128_si32(v7));\n *(float *)v8.m128i_i32 = roundf(*(float *)v8.m128i_i32);\n return COERCE_FLOAT(_mm_cvtsi128_si32(v8)) / 100.0;\n}", + "ida_pseudo_norm": "float func0(float a1, float a2, float a3) {\n __m128i v4;\n __m128i v5;\n __m128i v6;\n __m128i v7;\n __m128i v8;\n unsigned int v11;\n float v12;\n if (a3 >= (float)(a1 + a2) || a2 >= (float)(a1 + a3) ||\n a1 >= (float)(a2 + a3))\n return -1.0;\n *(float *)&v11 = (float)((float)(a1 + a2) + a3) / 2.0;\n v4 = (__m128i)v11;\n *(float *)v4.m128i_i32 = *(float *)&v11 - a1;\n v5 = v4;\n *(float *)v5.m128i_i32 =\n (float)((float)((float)(*(float *)&v11 - a1) * *(float *)&v11) *\n (float)((float)((float)((float)(a1 + a2) + a3) / 2.0) - a2)) *\n (float)((float)((float)((float)(a1 + a2) + a3) / 2.0) - a3);\n v6 = _mm_cvtsi32_si128(_mm_cvtsi128_si32(v5));\n *(float *)v6.m128i_i32 = sqrtf(*(float *)v6.m128i_i32);\n v12 = COERCE_FLOAT(_mm_cvtsi128_si32(v6));\n v7 = (__m128i)LODWORD(v12);\n *(float *)v7.m128i_i32 = v12 * 100.0;\n v8 = _mm_cvtsi32_si128(_mm_cvtsi128_si32(v7));\n *(float *)v8.m128i_i32 = roundf(*(float *)v8.m128i_i32);\n return COERCE_FLOAT(_mm_cvtsi128_si32(v8)) / 100.0;\n}" + }, + { + "index": "HumanEval-C-71", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "float func0(float a, float b, float c) {\n if (a + b <= c || a + c <= b || b + c <= a) return -1;\n float s = (a + b + c) / 2;\n float area = sqrtf(s * (s - a) * (s - b) * (s - c));\n return roundf(area * 100) / 100;\n}", + "test": "#include \n#include \n#include \n\nint main() {\n assert(fabs(func0(3, 4, 5) - 6.00) < 0.01);\n assert(fabs(func0(1, 2, 10) + 1) < 0.01);\n assert(fabs(func0(4, 8, 5) - 8.18) < 0.01);\n assert(fabs(func0(2, 2, 2) - 1.73) < 0.01);\n assert(fabs(func0(1, 2, 3) + 1) < 0.01);\n assert(fabs(func0(10, 5, 7) - 16.25) < 0.01);\n assert(fabs(func0(2, 6, 3) + 1) < 0.01);\n assert(fabs(func0(1, 1, 1) - 0.43) < 0.01);\n assert(fabs(func0(2, 2, 10) + 1) < 0.01);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmovaps xmm4, xmm0\naddss xmm4, xmm1\ncomiss xmm2, xmm4\njnb short loc_1216\nmovaps xmm3, xmm0\naddss xmm0, xmm2\ncomiss xmm1, xmm0\njnb short loc_121F\nmovss xmm0, cs:dword_2004\nmovaps xmm5, xmm1\naddss xmm5, xmm2\ncomiss xmm3, xmm5\njb short loc_11BA\nretn\nloc_11BA:\nsub rsp, 8\naddss xmm4, xmm2\nmulss xmm4, cs:dword_2008\nmovaps xmm0, xmm4\nsubss xmm0, xmm3\nmulss xmm0, xmm4\nmovaps xmm3, xmm4\nsubss xmm3, xmm1\nmulss xmm0, xmm3\nsubss xmm4, xmm2\nmulss xmm0, xmm4; x\npxor xmm1, xmm1\nucomiss xmm1, xmm0\nja short loc_120F\nsqrtss xmm0, xmm0\nloc_11F5:\nmulss xmm0, cs:dword_200C; x\ncall _roundf\ndivss xmm0, cs:dword_200C\nadd rsp, 8\nretn\nloc_120F:\ncall _sqrtf\njmp short loc_11F5\nloc_1216:\nmovss xmm0, cs:dword_2004\nretn\nloc_121F:\nmovss xmm0, cs:dword_2004\nretn", + "ida_pseudo": "float __fastcall func0(float a1, float a2, float a3)\n{\n float v3; // xmm4_4\n float result; // xmm0_4\n float v6; // xmm0_4\n float v7; // xmm0_4\n\n v3 = a1 + a2;\n if ( a3 >= (float)(a1 + a2) )\n return -1.0;\n if ( a2 >= (float)(a1 + a3) )\n return -1.0;\n result = -1.0;\n if ( a1 < (float)(a2 + a3) )\n {\n v6 = (float)((float)((float)((float)((float)(v3 + a3) * 0.5) - a1) * (float)((float)(v3 + a3) * 0.5))\n * (float)((float)((float)(v3 + a3) * 0.5) - a2))\n * (float)((float)((float)(v3 + a3) * 0.5) - a3);\n if ( v6 < 0.0 )\n v7 = sqrtf(v6);\n else\n v7 = fsqrt(v6);\n return roundf(v7 * 100.0) / 100.0;\n }\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\nmovaps xmm4, xmm0\naddss xmm4, xmm1\ncomiss xmm2, xmm4\njnb short loc_1216\nmovaps xmm3, xmm0\naddss xmm0, xmm2\ncomiss xmm1, xmm0\njnb short loc_121F\nmovss xmm0, cs:dword_2004\nmovaps xmm5, xmm1\naddss xmm5, xmm2\ncomiss xmm3, xmm5\njb short loc_11BA\nretn\nloc_11BA:\nsub rsp, 8\naddss xmm4, xmm2\nmulss xmm4, cs:dword_2008\nmovaps xmm0, xmm4\nsubss xmm0, xmm3\nmulss xmm0, xmm4\nmovaps xmm3, xmm4\nsubss xmm3, xmm1\nmulss xmm0, xmm3\nsubss xmm4, xmm2\nmulss xmm0, xmm4; x\npxor xmm1, xmm1\nucomiss xmm1, xmm0\nja short loc_120F\nsqrtss xmm0, xmm0\nloc_11F5:\nmulss xmm0, cs:dword_200C; x\ncall _roundf\ndivss xmm0, cs:dword_200C\nadd rsp, 8\nretn\nloc_120F:\ncall _sqrtf\njmp short loc_11F5\nloc_1216:\nmovss xmm0, cs:dword_2004\nretn\nloc_121F:\nmovss xmm0, cs:dword_2004\nretn", + "ida_strip_pseudo": "float __fastcall sub_1189(float a1, float a2, float a3)\n{\n float v3; // xmm4_4\n float result; // xmm0_4\n float v6; // xmm0_4\n float v7; // xmm0_4\n\n v3 = a1 + a2;\n if ( a3 >= (float)(a1 + a2) )\n return -1.0;\n if ( a2 >= (float)(a1 + a3) )\n return -1.0;\n result = -1.0;\n if ( a1 < (float)(a2 + a3) )\n {\n v6 = (float)((float)((float)((float)((float)(v3 + a3) * 0.5) - a1) * (float)((float)(v3 + a3) * 0.5))\n * (float)((float)((float)(v3 + a3) * 0.5) - a2))\n * (float)((float)((float)(v3 + a3) * 0.5) - a3);\n if ( v6 < 0.0 )\n v7 = sqrtf(v6);\n else\n v7 = fsqrt(v6);\n return roundf(v7 * 100.0) / 100.0;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "float sub_1189(float a1, float a2, float a3) {\n float v3;\n float result;\n float v6;\n float v7;\n v3 = a1 + a2;\n if (a3 >= (float)(a1 + a2)) return -1.0;\n if (a2 >= (float)(a1 + a3)) return -1.0;\n result = -1.0;\n if (a1 < (float)(a2 + a3)) {\n v6 = (float)((float)((float)((float)((float)(v3 + a3) * 0.5) - a1) *\n (float)((float)(v3 + a3) * 0.5)) *\n (float)((float)((float)(v3 + a3) * 0.5) - a2)) *\n (float)((float)((float)(v3 + a3) * 0.5) - a3);\n if (v6 < 0.0)\n v7 = sqrtf(v6);\n else\n v7 = fsqrt(v6);\n return roundf(v7 * 100.0) / 100.0;\n }\n return result;\n}", + "ida_pseudo_norm": "float func0(float a1, float a2, float a3) {\n float v3;\n float result;\n float v6;\n float v7;\n v3 = a1 + a2;\n if (a3 >= (float)(a1 + a2)) return -1.0;\n if (a2 >= (float)(a1 + a3)) return -1.0;\n result = -1.0;\n if (a1 < (float)(a2 + a3)) {\n v6 = (float)((float)((float)((float)((float)(v3 + a3) * 0.5) - a1) *\n (float)((float)(v3 + a3) * 0.5)) *\n (float)((float)((float)(v3 + a3) * 0.5) - a2)) *\n (float)((float)((float)(v3 + a3) * 0.5) - a3);\n if (v6 < 0.0)\n v7 = sqrtf(v6);\n else\n v7 = fsqrt(v6);\n return roundf(v7 * 100.0) / 100.0;\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-71", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "float func0(float a, float b, float c) {\n if (a + b <= c || a + c <= b || b + c <= a) return -1;\n float s = (a + b + c) / 2;\n float area = sqrtf(s * (s - a) * (s - b) * (s - c));\n return roundf(area * 100) / 100;\n}", + "test": "#include \n#include \n#include \n\nint main() {\n assert(fabs(func0(3, 4, 5) - 6.00) < 0.01);\n assert(fabs(func0(1, 2, 10) + 1) < 0.01);\n assert(fabs(func0(4, 8, 5) - 8.18) < 0.01);\n assert(fabs(func0(2, 2, 2) - 1.73) < 0.01);\n assert(fabs(func0(1, 2, 3) + 1) < 0.01);\n assert(fabs(func0(10, 5, 7) - 16.25) < 0.01);\n assert(fabs(func0(2, 6, 3) + 1) < 0.01);\n assert(fabs(func0(1, 1, 1) - 0.43) < 0.01);\n assert(fabs(func0(2, 2, 10) + 1) < 0.01);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmovaps xmm4, xmm0\naddss xmm4, xmm1\ncomiss xmm2, xmm4\njnb loc_1590\nmovaps xmm3, xmm0\naddss xmm0, xmm2\ncomiss xmm1, xmm0\nmovss xmm0, cs:dword_2004\njnb short locret_1580\nmovaps xmm5, xmm1\naddss xmm5, xmm2\ncomiss xmm3, xmm5\njnb short locret_1588\nsub rsp, 8\naddss xmm4, xmm2\nmulss xmm4, cs:dword_2008\nmovaps xmm0, xmm4\nsubss xmm0, xmm3\nmovaps xmm3, xmm4\nsubss xmm3, xmm1\npxor xmm1, xmm1\nmulss xmm0, xmm4\nsubss xmm4, xmm2\nmulss xmm0, xmm3\nmulss xmm0, xmm4; x\nucomiss xmm1, xmm0\nja short loc_1599\nsqrtss xmm0, xmm0\nloc_155F:\nmulss xmm0, cs:dword_200C; x\ncall _roundf\ndivss xmm0, cs:dword_200C\nadd rsp, 8\nretn\nlocret_1580:\nretn\nlocret_1588:\nretn\nloc_1590:\nmovss xmm0, cs:dword_2004\nretn\nloc_1599:\ncall _sqrtf\njmp short loc_155F", + "ida_pseudo": "float __fastcall func0(float a1, float a2, float a3)\n{\n float v3; // xmm4_4\n bool v5; // cf\n float result; // xmm0_4\n float v7; // xmm0_4\n float v8; // xmm0_4\n\n v3 = a1 + a2;\n if ( a3 >= (float)(a1 + a2) )\n return -1.0;\n v5 = a2 < (float)(a1 + a3);\n result = -1.0;\n if ( v5 && a1 < (float)(a2 + a3) )\n {\n v7 = (float)((float)((float)((float)((float)(v3 + a3) * 0.5) - a1) * (float)((float)(v3 + a3) * 0.5))\n * (float)((float)((float)(v3 + a3) * 0.5) - a2))\n * (float)((float)((float)(v3 + a3) * 0.5) - a3);\n if ( v7 < 0.0 )\n v8 = sqrtf(v7);\n else\n v8 = fsqrt(v7);\n return roundf(v8 * 100.0) / 100.0;\n }\n return result;\n}", + "ida_strip_asm": "sub_14F0:\nendbr64\nmovaps xmm4, xmm0\naddss xmm4, xmm1\ncomiss xmm2, xmm4\njnb loc_1590\nmovaps xmm3, xmm0\naddss xmm0, xmm2\ncomiss xmm1, xmm0\nmovss xmm0, cs:dword_2004\njnb short locret_1580\nmovaps xmm5, xmm1\naddss xmm5, xmm2\ncomiss xmm3, xmm5\njnb short locret_1588\nsub rsp, 8\naddss xmm4, xmm2\nmulss xmm4, cs:dword_2008\nmovaps xmm0, xmm4\nsubss xmm0, xmm3\nmovaps xmm3, xmm4\nsubss xmm3, xmm1\npxor xmm1, xmm1\nmulss xmm0, xmm4\nsubss xmm4, xmm2\nmulss xmm0, xmm3\nmulss xmm0, xmm4; x\nucomiss xmm1, xmm0\nja short loc_1599\nsqrtss xmm0, xmm0\nloc_155F:\nmulss xmm0, cs:dword_200C; x\ncall _roundf\ndivss xmm0, cs:dword_200C\nadd rsp, 8\nretn\nlocret_1580:\nretn\nlocret_1588:\nretn\nloc_1590:\nmovss xmm0, cs:dword_2004\nretn\nloc_1599:\ncall _sqrtf\njmp short loc_155F", + "ida_strip_pseudo": "float __fastcall sub_14F0(float a1, float a2, float a3)\n{\n float v3; // xmm4_4\n bool v5; // cf\n float result; // xmm0_4\n float v7; // xmm0_4\n float v8; // xmm0_4\n\n v3 = a1 + a2;\n if ( a3 >= (float)(a1 + a2) )\n return -1.0;\n v5 = a2 < (float)(a1 + a3);\n result = -1.0;\n if ( v5 && a1 < (float)(a2 + a3) )\n {\n v7 = (float)((float)((float)((float)((float)(v3 + a3) * 0.5) - a1) * (float)((float)(v3 + a3) * 0.5))\n * (float)((float)((float)(v3 + a3) * 0.5) - a2))\n * (float)((float)((float)(v3 + a3) * 0.5) - a3);\n if ( v7 < 0.0 )\n v8 = sqrtf(v7);\n else\n v8 = fsqrt(v7);\n return roundf(v8 * 100.0) / 100.0;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "float sub_14F0(float a1, float a2, float a3) {\n float v3;\n bool v5;\n float result;\n float v7;\n float v8;\n v3 = a1 + a2;\n if (a3 >= (float)(a1 + a2)) return -1.0;\n v5 = a2 < (float)(a1 + a3);\n result = -1.0;\n if (v5 && a1 < (float)(a2 + a3)) {\n v7 = (float)((float)((float)((float)((float)(v3 + a3) * 0.5) - a1) *\n (float)((float)(v3 + a3) * 0.5)) *\n (float)((float)((float)(v3 + a3) * 0.5) - a2)) *\n (float)((float)((float)(v3 + a3) * 0.5) - a3);\n if (v7 < 0.0)\n v8 = sqrtf(v7);\n else\n v8 = fsqrt(v7);\n return roundf(v8 * 100.0) / 100.0;\n }\n return result;\n}", + "ida_pseudo_norm": "float func0(float a1, float a2, float a3) {\n float v3;\n bool v5;\n float result;\n float v7;\n float v8;\n v3 = a1 + a2;\n if (a3 >= (float)(a1 + a2)) return -1.0;\n v5 = a2 < (float)(a1 + a3);\n result = -1.0;\n if (v5 && a1 < (float)(a2 + a3)) {\n v7 = (float)((float)((float)((float)((float)(v3 + a3) * 0.5) - a1) *\n (float)((float)(v3 + a3) * 0.5)) *\n (float)((float)((float)(v3 + a3) * 0.5) - a2)) *\n (float)((float)((float)(v3 + a3) * 0.5) - a3);\n if (v7 < 0.0)\n v8 = sqrtf(v7);\n else\n v8 = fsqrt(v7);\n return roundf(v8 * 100.0) / 100.0;\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-72", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "bool func0(int q[], int size, int w) {\n int sum = 0;\n for (int i = 0; i < size / 2; i++) {\n if (q[i] != q[size - 1 - i]) return false;\n sum += q[i] + q[size - 1 - i];\n }\n if (size % 2 == 1) sum += q[size / 2];\n return sum <= w;\n}", + "test": "#include \n#include \n\nint main() {\n int test1[] = {3, 2, 3};\n assert(func0(test1, 3, 9) == true);\n\n int test2[] = {1, 2};\n assert(func0(test2, 2, 5) == false);\n\n int test3[] = {3};\n assert(func0(test3, 1, 5) == true);\n\n int test4[] = {3, 2, 3};\n assert(func0(test4, 3, 1) == false);\n\n int test5[] = {1, 2, 3};\n assert(func0(test5, 3, 6) == false);\n\n int test6[] = {5};\n assert(func0(test6, 1, 5) == true);\n\n printf(\"All tests passed.\\n\");\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_1226\nloc_11AB:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_1C]\nsub eax, 1\nsub eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_11EB\nmov eax, 0\njmp loc_127F\nloc_11EB:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_1C]\nsub eax, 1\nsub eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nadd eax, edx\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_1226:\nmov eax, [rbp+var_1C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\ncmp [rbp+var_4], eax\njl loc_11AB\nmov edx, [rbp+var_1C]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\ncmp eax, 1\njnz short loc_1276\nmov eax, [rbp+var_1C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nloc_1276:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_20]\nsetle al\nloc_127F:\npop rbp\nretn", + "ida_pseudo": "bool __fastcall func0(__int64 a1, int a2, int a3)\n{\n int v4; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v4 = 0;\n for ( i = 0; i < a2 / 2; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) != *(_DWORD *)(4LL * (a2 - 1 - i) + a1) )\n return 0;\n v4 += *(_DWORD *)(4LL * i + a1) + *(_DWORD *)(4LL * (a2 - 1 - i) + a1);\n }\n if ( a2 % 2 == 1 )\n v4 += *(_DWORD *)(4LL * (a2 / 2) + a1);\n return v4 <= a3;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_1226\nloc_11AB:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_1C]\nsub eax, 1\nsub eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_11EB\nmov eax, 0\njmp loc_127F\nloc_11EB:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_1C]\nsub eax, 1\nsub eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nadd eax, edx\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_1226:\nmov eax, [rbp+var_1C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\ncmp [rbp+var_4], eax\njl loc_11AB\nmov edx, [rbp+var_1C]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\ncmp eax, 1\njnz short loc_1276\nmov eax, [rbp+var_1C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nloc_1276:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_20]\nsetle al\nloc_127F:\npop rbp\nretn", + "ida_strip_pseudo": "bool __fastcall sub_1189(__int64 a1, int a2, int a3)\n{\n int v4; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v4 = 0;\n for ( i = 0; i < a2 / 2; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) != *(_DWORD *)(4LL * (a2 - 1 - i) + a1) )\n return 0;\n v4 += *(_DWORD *)(4LL * i + a1) + *(_DWORD *)(4LL * (a2 - 1 - i) + a1);\n }\n if ( a2 % 2 == 1 )\n v4 += *(_DWORD *)(4LL * (a2 / 2) + a1);\n return v4 <= a3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_1189(long long a1, int a2, int a3) {\n int v4;\n int i;\n v4 = 0;\n for (i = 0; i < a2 / 2; ++i) {\n if (*(uint32_t *)(4LL * i + a1) != *(uint32_t *)(4LL * (a2 - 1 - i) + a1))\n return 0;\n v4 += *(uint32_t *)(4LL * i + a1) + *(uint32_t *)(4LL * (a2 - 1 - i) + a1);\n }\n if (a2 % 2 == 1) v4 += *(uint32_t *)(4LL * (a2 / 2) + a1);\n return v4 <= a3;\n}", + "ida_pseudo_norm": "bool func0(long long a1, int a2, int a3) {\n int v4;\n int i;\n v4 = 0;\n for (i = 0; i < a2 / 2; ++i) {\n if (*(uint32_t *)(4LL * i + a1) != *(uint32_t *)(4LL * (a2 - 1 - i) + a1))\n return 0;\n v4 += *(uint32_t *)(4LL * i + a1) + *(uint32_t *)(4LL * (a2 - 1 - i) + a1);\n }\n if (a2 % 2 == 1) v4 += *(uint32_t *)(4LL * (a2 / 2) + a1);\n return v4 <= a3;\n}" + }, + { + "index": "HumanEval-C-72", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "bool func0(int q[], int size, int w) {\n int sum = 0;\n for (int i = 0; i < size / 2; i++) {\n if (q[i] != q[size - 1 - i]) return false;\n sum += q[i] + q[size - 1 - i];\n }\n if (size % 2 == 1) sum += q[size / 2];\n return sum <= w;\n}", + "test": "#include \n#include \n\nint main() {\n int test1[] = {3, 2, 3};\n assert(func0(test1, 3, 9) == true);\n\n int test2[] = {1, 2};\n assert(func0(test2, 2, 5) == false);\n\n int test3[] = {3};\n assert(func0(test3, 1, 5) == true);\n\n int test4[] = {3, 2, 3};\n assert(func0(test4, 3, 1) == false);\n\n int test5[] = {1, 2, 3};\n assert(func0(test5, 3, 6) == false);\n\n int test6[] = {5};\n assert(func0(test6, 1, 5) == true);\n\n printf(\"All tests passed.\\n\");\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmov r9, rdi\nmov r10d, esi\nmov r11d, edx\nmov r8d, esi\nshr r8d, 1Fh\nadd r8d, esi\nsar r8d, 1\ncmp esi, 1\njle short loc_11F2\nmovsxd rax, esi\nlea rcx, [rdi+rax*4]\nmov edx, 0\nmov edi, 0\nloc_11B9:\nmov eax, [r9+rdx*4]\nmov esi, [rcx-4]\ncmp eax, esi\njnz short loc_1202\nadd eax, esi\nadd edi, eax\nadd rdx, 1\nsub rcx, 4\ncmp r8d, edx\njg short loc_11B9\nloc_11D5:\nmov eax, r10d\nshr eax, 1Fh\nadd r10d, eax\nand r10d, 1\nsub r10d, eax\ncmp r10d, 1\njz short loc_11F9\nloc_11EB:\ncmp edi, r11d\nsetle al\nretn\nloc_11F2:\nmov edi, 0\njmp short loc_11D5\nloc_11F9:\nmovsxd r8, r8d\nadd edi, [r9+r8*4]\njmp short loc_11EB\nloc_1202:\nmov eax, 0\nretn", + "ida_pseudo": "bool __fastcall func0(__int64 a1, int a2, int a3)\n{\n int v6; // r8d\n __int64 v7; // rcx\n __int64 v8; // rdx\n int v9; // edi\n int v10; // eax\n int v11; // esi\n\n v6 = a2 / 2;\n if ( a2 <= 1 )\n {\n v9 = 0;\nLABEL_5:\n if ( a2 % 2 == 1 )\n v9 += *(_DWORD *)(a1 + 4LL * v6);\n return v9 <= a3;\n }\n else\n {\n v7 = a1 + 4LL * a2;\n v8 = 0LL;\n v9 = 0;\n while ( 1 )\n {\n v10 = *(_DWORD *)(a1 + 4 * v8);\n v11 = *(_DWORD *)(v7 - 4);\n if ( v10 != v11 )\n return 0;\n v9 += v11 + v10;\n ++v8;\n v7 -= 4LL;\n if ( v6 <= (int)v8 )\n goto LABEL_5;\n }\n }\n}", + "ida_strip_asm": "sub_1189:\nendbr64\nmov r9, rdi\nmov r10d, esi\nmov r11d, edx\nmov r8d, esi\nshr r8d, 1Fh\nadd r8d, esi\nsar r8d, 1\ncmp esi, 1\njle short loc_11F2\nmovsxd rax, esi\nlea rcx, [rdi+rax*4]\nmov edx, 0\nmov edi, 0\nloc_11B9:\nmov eax, [r9+rdx*4]\nmov esi, [rcx-4]\ncmp eax, esi\njnz short loc_1202\nadd eax, esi\nadd edi, eax\nadd rdx, 1\nsub rcx, 4\ncmp r8d, edx\njg short loc_11B9\nloc_11D5:\nmov eax, r10d\nshr eax, 1Fh\nadd r10d, eax\nand r10d, 1\nsub r10d, eax\ncmp r10d, 1\njz short loc_11F9\nloc_11EB:\ncmp edi, r11d\nsetle al\nretn\nloc_11F2:\nmov edi, 0\njmp short loc_11D5\nloc_11F9:\nmovsxd r8, r8d\nadd edi, [r9+r8*4]\njmp short loc_11EB\nloc_1202:\nmov eax, 0\nretn", + "ida_strip_pseudo": "bool __fastcall sub_1189(__int64 a1, int a2, int a3)\n{\n int v6; // r8d\n __int64 v7; // rcx\n __int64 v8; // rdx\n int v9; // edi\n int v10; // eax\n int v11; // esi\n\n v6 = a2 / 2;\n if ( a2 <= 1 )\n {\n v9 = 0;\nLABEL_5:\n if ( a2 % 2 == 1 )\n v9 += *(_DWORD *)(a1 + 4LL * v6);\n return v9 <= a3;\n }\n else\n {\n v7 = a1 + 4LL * a2;\n v8 = 0LL;\n v9 = 0;\n while ( 1 )\n {\n v10 = *(_DWORD *)(a1 + 4 * v8);\n v11 = *(_DWORD *)(v7 - 4);\n if ( v10 != v11 )\n return 0;\n v9 += v11 + v10;\n ++v8;\n v7 -= 4LL;\n if ( v6 <= (int)v8 )\n goto LABEL_5;\n }\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_1189(long long a1, int a2, int a3) {\n int v6;\n long long v7;\n long long v8;\n int v9;\n int v10;\n int v11;\n v6 = a2 / 2;\n if (a2 <= 1) {\n v9 = 0;\n LABEL_5:\n if (a2 % 2 == 1) v9 += *(uint32_t *)(a1 + 4LL * v6);\n return v9 <= a3;\n } else {\n v7 = a1 + 4LL * a2;\n v8 = 0LL;\n v9 = 0;\n while (1) {\n v10 = *(uint32_t *)(a1 + 4 * v8);\n v11 = *(uint32_t *)(v7 - 4);\n if (v10 != v11) return 0;\n v9 += v11 + v10;\n ++v8;\n v7 -= 4LL;\n if (v6 <= (int)v8) goto LABEL_5;\n }\n }\n}", + "ida_pseudo_norm": "bool func0(long long a1, int a2, int a3) {\n int v6;\n long long v7;\n long long v8;\n int v9;\n int v10;\n int v11;\n v6 = a2 / 2;\n if (a2 <= 1) {\n v9 = 0;\n LABEL_5:\n if (a2 % 2 == 1) v9 += *(uint32_t *)(a1 + 4LL * v6);\n return v9 <= a3;\n } else {\n v7 = a1 + 4LL * a2;\n v8 = 0LL;\n v9 = 0;\n while (1) {\n v10 = *(uint32_t *)(a1 + 4 * v8);\n v11 = *(uint32_t *)(v7 - 4);\n if (v10 != v11) return 0;\n v9 += v11 + v10;\n ++v8;\n v7 -= 4LL;\n if (v6 <= (int)v8) goto LABEL_5;\n }\n }\n}" + }, + { + "index": "HumanEval-C-72", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "bool func0(int q[], int size, int w) {\n int sum = 0;\n for (int i = 0; i < size / 2; i++) {\n if (q[i] != q[size - 1 - i]) return false;\n sum += q[i] + q[size - 1 - i];\n }\n if (size % 2 == 1) sum += q[size / 2];\n return sum <= w;\n}", + "test": "#include \n#include \n\nint main() {\n int test1[] = {3, 2, 3};\n assert(func0(test1, 3, 9) == true);\n\n int test2[] = {1, 2};\n assert(func0(test2, 2, 5) == false);\n\n int test3[] = {3};\n assert(func0(test3, 1, 5) == true);\n\n int test4[] = {3, 2, 3};\n assert(func0(test4, 3, 1) == false);\n\n int test5[] = {1, 2, 3};\n assert(func0(test5, 3, 6) == false);\n\n int test6[] = {5};\n assert(func0(test6, 1, 5) == true);\n\n printf(\"All tests passed.\\n\");\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmov r8d, esi\nmov r9, rdi\nmov r10d, edx\nshr r8d, 1Fh\nadd r8d, esi\nsar r8d, 1\ncmp esi, 1\njle short loc_13CB\nlea eax, [rsi-1]\ncdqe\nlea rdx, [rdi+rax*4]\nxor eax, eax\nxor edi, edi\njmp short loc_13C0\nloc_13B0:\nadd rax, 1\nlea edi, [rdi+rcx*2]\nsub rdx, 4\ncmp r8d, eax\njle short loc_13D0\nloc_13C0:\nmov ecx, [r9+rax*4]\ncmp ecx, [rdx]\njz short loc_13B0\nxor eax, eax\nretn\nloc_13CB:\nxor edi, edi\nnop dword ptr [rax]\nloc_13D0:\nmov eax, esi\nshr eax, 1Fh\nadd esi, eax\nand esi, 1\nsub esi, eax\ncmp esi, 1\njz short loc_13F0\ncmp edi, r10d\nsetle al\nretn\nloc_13F0:\nmovsxd r8, r8d\nadd edi, [r9+r8*4]\ncmp edi, r10d\nsetle al\nretn", + "ida_pseudo": "bool __fastcall func0(__int64 a1, int a2, int a3)\n{\n int v5; // r8d\n _DWORD *v6; // rdx\n __int64 v7; // rax\n int v8; // edi\n int v9; // ecx\n\n v5 = a2 / 2;\n if ( a2 <= 1 )\n {\n v8 = 0;\nLABEL_7:\n if ( a2 % 2 == 1 )\n v8 += *(_DWORD *)(a1 + 4LL * v5);\n return v8 <= a3;\n }\n else\n {\n v6 = (_DWORD *)(a1 + 4LL * (a2 - 1));\n v7 = 0LL;\n v8 = 0;\n while ( 1 )\n {\n v9 = *(_DWORD *)(a1 + 4 * v7);\n if ( v9 != *v6 )\n return 0;\n ++v7;\n v8 += 2 * v9;\n --v6;\n if ( v5 <= (int)v7 )\n goto LABEL_7;\n }\n }\n}", + "ida_strip_asm": "sub_1380:\nendbr64\nmov r8d, esi\nmov r9, rdi\nmov r10d, edx\nshr r8d, 1Fh\nadd r8d, esi\nsar r8d, 1\ncmp esi, 1\njle short loc_13CB\nlea eax, [rsi-1]\ncdqe\nlea rdx, [rdi+rax*4]\nxor eax, eax\nxor edi, edi\njmp short loc_13C0\nloc_13B0:\nadd rax, 1\nlea edi, [rdi+rcx*2]\nsub rdx, 4\ncmp r8d, eax\njle short loc_13D0\nloc_13C0:\nmov ecx, [r9+rax*4]\ncmp ecx, [rdx]\njz short loc_13B0\nxor eax, eax\nretn\nloc_13CB:\nxor edi, edi\nnop dword ptr [rax]\nloc_13D0:\nmov eax, esi\nshr eax, 1Fh\nadd esi, eax\nand esi, 1\nsub esi, eax\ncmp esi, 1\njz short loc_13F0\ncmp edi, r10d\nsetle al\nretn\nloc_13F0:\nmovsxd r8, r8d\nadd edi, [r9+r8*4]\ncmp edi, r10d\nsetle al\nretn", + "ida_strip_pseudo": "bool __fastcall sub_1380(__int64 a1, int a2, int a3)\n{\n int v5; // r8d\n _DWORD *v6; // rdx\n __int64 v7; // rax\n int v8; // edi\n int v9; // ecx\n\n v5 = a2 / 2;\n if ( a2 <= 1 )\n {\n v8 = 0;\nLABEL_7:\n if ( a2 % 2 == 1 )\n v8 += *(_DWORD *)(a1 + 4LL * v5);\n return v8 <= a3;\n }\n else\n {\n v6 = (_DWORD *)(a1 + 4LL * (a2 - 1));\n v7 = 0LL;\n v8 = 0;\n while ( 1 )\n {\n v9 = *(_DWORD *)(a1 + 4 * v7);\n if ( v9 != *v6 )\n return 0;\n ++v7;\n v8 += 2 * v9;\n --v6;\n if ( v5 <= (int)v7 )\n goto LABEL_7;\n }\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_1380(long long a1, int a2, int a3) {\n int v5;\n uint32_t *v6;\n long long v7;\n int v8;\n int v9;\n v5 = a2 / 2;\n if (a2 <= 1) {\n v8 = 0;\n LABEL_7:\n if (a2 % 2 == 1) v8 += *(uint32_t *)(a1 + 4LL * v5);\n return v8 <= a3;\n } else {\n v6 = (uint32_t *)(a1 + 4LL * (a2 - 1));\n v7 = 0LL;\n v8 = 0;\n while (1) {\n v9 = *(uint32_t *)(a1 + 4 * v7);\n if (v9 != *v6) return 0;\n ++v7;\n v8 += 2 * v9;\n --v6;\n if (v5 <= (int)v7) goto LABEL_7;\n }\n }\n}", + "ida_pseudo_norm": "bool func0(long long a1, int a2, int a3) {\n int v5;\n uint32_t *v6;\n long long v7;\n int v8;\n int v9;\n v5 = a2 / 2;\n if (a2 <= 1) {\n v8 = 0;\n LABEL_7:\n if (a2 % 2 == 1) v8 += *(uint32_t *)(a1 + 4LL * v5);\n return v8 <= a3;\n } else {\n v6 = (uint32_t *)(a1 + 4LL * (a2 - 1));\n v7 = 0LL;\n v8 = 0;\n while (1) {\n v9 = *(uint32_t *)(a1 + 4 * v7);\n if (v9 != *v6) return 0;\n ++v7;\n v8 += 2 * v9;\n --v6;\n if (v5 <= (int)v7) goto LABEL_7;\n }\n }\n}" + }, + { + "index": "HumanEval-C-73", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int arr[], int size) {\n int out = 0;\n for (int i = 0; i < size / 2; i++) {\n if (arr[i] != arr[size - 1 - i]) {\n out++;\n }\n }\n return out;\n}", + "test": "#include \n#include \n\nint main() {\n int test1[] = {1, 2, 3, 5, 4, 7, 9, 6};\n assert(func0(test1, 8) == 4);\n\n int test2[] = {1, 2, 3, 4, 3, 2, 2};\n assert(func0(test2, 7) == 1);\n\n int test3[] = {1, 4, 2};\n assert(func0(test3, 3) == 1);\n\n int test4[] = {1, 4, 4, 2};\n assert(func0(test4, 4) == 1);\n\n int test5[] = {1, 2, 3, 2, 1};\n assert(func0(test5, 5) == 0);\n\n int test6[] = {3, 1, 1, 3};\n assert(func0(test6, 4) == 0);\n\n int test7[] = {1};\n assert(func0(test7, 1) == 0);\n\n int test8[] = {0, 1};\n assert(func0(test8, 2) == 1);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11C6\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_1C]\nsub eax, 1\nsub eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_11C2\nadd [rbp+var_8], 1\nloc_11C2:\nadd [rbp+var_4], 1\nloc_11C6:\nmov eax, [rbp+var_1C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\ncmp [rbp+var_4], eax\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2 / 2; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) != *(_DWORD *)(4LL * (a2 - 1 - i) + a1) )\n ++v3;\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11C6\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_1C]\nsub eax, 1\nsub eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_11C2\nadd [rbp+var_8], 1\nloc_11C2:\nadd [rbp+var_4], 1\nloc_11C6:\nmov eax, [rbp+var_1C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\ncmp [rbp+var_4], eax\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2 / 2; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) != *(_DWORD *)(4LL * (a2 - 1 - i) + a1) )\n ++v3;\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2 / 2; ++i) {\n if (*(uint32_t *)(4LL * i + a1) != *(uint32_t *)(4LL * (a2 - 1 - i) + a1))\n ++v3;\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2 / 2; ++i) {\n if (*(uint32_t *)(4LL * i + a1) != *(uint32_t *)(4LL * (a2 - 1 - i) + a1))\n ++v3;\n }\n return v3;\n}" + }, + { + "index": "HumanEval-C-73", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int arr[], int size) {\n int out = 0;\n for (int i = 0; i < size / 2; i++) {\n if (arr[i] != arr[size - 1 - i]) {\n out++;\n }\n }\n return out;\n}", + "test": "#include \n#include \n\nint main() {\n int test1[] = {1, 2, 3, 5, 4, 7, 9, 6};\n assert(func0(test1, 8) == 4);\n\n int test2[] = {1, 2, 3, 4, 3, 2, 2};\n assert(func0(test2, 7) == 1);\n\n int test3[] = {1, 4, 2};\n assert(func0(test3, 3) == 1);\n\n int test4[] = {1, 4, 4, 2};\n assert(func0(test4, 4) == 1);\n\n int test5[] = {1, 2, 3, 2, 1};\n assert(func0(test5, 5) == 0);\n\n int test6[] = {3, 1, 1, 3};\n assert(func0(test6, 4) == 0);\n\n int test7[] = {1};\n assert(func0(test7, 1) == 0);\n\n int test8[] = {0, 1};\n assert(func0(test8, 2) == 1);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmov ecx, esi\nshr ecx, 1Fh\nadd ecx, esi\nsar ecx, 1\ncmp esi, 1\njle short loc_11A9\nmovsxd rsi, esi\nlea rdx, [rdi+rsi*4]\nmov eax, 0\nmov esi, 0\njmp short loc_119A\nloc_118E:\nadd rax, 1\nsub rdx, 4\ncmp ecx, eax\njle short loc_11AE\nloc_119A:\nmov r8d, [rdx-4]\ncmp [rdi+rax*4], r8d\njz short loc_118E\nadd esi, 1\njmp short loc_118E\nloc_11A9:\nmov esi, 0\nloc_11AE:\nmov eax, esi\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int v2; // ecx\n __int64 v3; // rdx\n __int64 v4; // rax\n unsigned int v5; // esi\n\n v2 = a2 / 2;\n if ( a2 <= 1 )\n {\n return 0;\n }\n else\n {\n v3 = a1 + 4LL * a2;\n v4 = 0LL;\n v5 = 0;\n do\n {\n if ( *(_DWORD *)(a1 + 4 * v4) != *(_DWORD *)(v3 - 4) )\n ++v5;\n ++v4;\n v3 -= 4LL;\n }\n while ( v2 > (int)v4 );\n }\n return v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov ecx, esi\nshr ecx, 1Fh\nadd ecx, esi\nsar ecx, 1\ncmp esi, 1\njle short loc_11A9\nmovsxd rsi, esi\nlea rdx, [rdi+rsi*4]\nmov eax, 0\nmov esi, 0\njmp short loc_119A\nloc_118E:\nadd rax, 1\nsub rdx, 4\ncmp ecx, eax\njle short loc_11AE\nloc_119A:\nmov r8d, [rdx-4]\ncmp [rdi+rax*4], r8d\njz short loc_118E\nadd esi, 1\njmp short loc_118E\nloc_11A9:\nmov esi, 0\nloc_11AE:\nmov eax, esi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int v2; // ecx\n __int64 v3; // rdx\n __int64 v4; // rax\n unsigned int v5; // esi\n\n v2 = a2 / 2;\n if ( a2 <= 1 )\n {\n return 0;\n }\n else\n {\n v3 = a1 + 4LL * a2;\n v4 = 0LL;\n v5 = 0;\n do\n {\n if ( *(_DWORD *)(a1 + 4 * v4) != *(_DWORD *)(v3 - 4) )\n ++v5;\n ++v4;\n v3 -= 4LL;\n }\n while ( v2 > (int)v4 );\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int v2;\n long long v3;\n long long v4;\n unsigned int v5;\n v2 = a2 / 2;\n if (a2 <= 1) {\n return 0;\n } else {\n v3 = a1 + 4LL * a2;\n v4 = 0LL;\n v5 = 0;\n do {\n if (*(uint32_t *)(a1 + 4 * v4) != *(uint32_t *)(v3 - 4)) ++v5;\n ++v4;\n v3 -= 4LL;\n } while (v2 > (int)v4);\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int v2;\n long long v3;\n long long v4;\n unsigned int v5;\n v2 = a2 / 2;\n if (a2 <= 1) {\n return 0;\n } else {\n v3 = a1 + 4LL * a2;\n v4 = 0LL;\n v5 = 0;\n do {\n if (*(uint32_t *)(a1 + 4 * v4) != *(uint32_t *)(v3 - 4)) ++v5;\n ++v4;\n v3 -= 4LL;\n } while (v2 > (int)v4);\n }\n return v5;\n}" + }, + { + "index": "HumanEval-C-73", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int arr[], int size) {\n int out = 0;\n for (int i = 0; i < size / 2; i++) {\n if (arr[i] != arr[size - 1 - i]) {\n out++;\n }\n }\n return out;\n}", + "test": "#include \n#include \n\nint main() {\n int test1[] = {1, 2, 3, 5, 4, 7, 9, 6};\n assert(func0(test1, 8) == 4);\n\n int test2[] = {1, 2, 3, 4, 3, 2, 2};\n assert(func0(test2, 7) == 1);\n\n int test3[] = {1, 4, 2};\n assert(func0(test3, 3) == 1);\n\n int test4[] = {1, 4, 4, 2};\n assert(func0(test4, 4) == 1);\n\n int test5[] = {1, 2, 3, 2, 1};\n assert(func0(test5, 5) == 0);\n\n int test6[] = {3, 1, 1, 3};\n assert(func0(test6, 4) == 0);\n\n int test7[] = {1};\n assert(func0(test7, 1) == 0);\n\n int test8[] = {0, 1};\n assert(func0(test8, 2) == 1);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmov r8d, esi\nshr r8d, 1Fh\nadd r8d, esi\nsar r8d, 1\ncmp esi, 1\njle short loc_1450\nsub esi, 1\nxor eax, eax\nxor ecx, ecx\nmovsxd rsi, esi\nlea rdx, [rdi+rsi*4]\nnop dword ptr [rax+00h]\nloc_1428:\nmov esi, [rdx]\ncmp [rdi+rax*4], esi\nsetnz sil\nadd rax, 1\nsub rdx, 4\nmovzx esi, sil\nadd ecx, esi\ncmp r8d, eax\njg short loc_1428\nmov eax, ecx\nretn\nloc_1450:\nxor ecx, ecx\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int v2; // r8d\n __int64 v3; // rax\n unsigned int v4; // ecx\n _DWORD *v5; // rdx\n bool v6; // si\n\n v2 = a2 / 2;\n if ( a2 <= 1 )\n return 0LL;\n v3 = 0LL;\n v4 = 0;\n v5 = (_DWORD *)(a1 + 4LL * (a2 - 1));\n do\n {\n v6 = *(_DWORD *)(a1 + 4 * v3++) != *v5--;\n v4 += v6;\n }\n while ( v2 > (int)v3 );\n return v4;\n}", + "ida_strip_asm": "sub_1400:\nendbr64\nmov r8d, esi\nshr r8d, 1Fh\nadd r8d, esi\nsar r8d, 1\ncmp esi, 1\njle short loc_1450\nsub esi, 1\nxor eax, eax\nxor ecx, ecx\nmovsxd rsi, esi\nlea rdx, [rdi+rsi*4]\nnop dword ptr [rax+00h]\nloc_1428:\nmov esi, [rdx]\ncmp [rdi+rax*4], esi\nsetnz sil\nadd rax, 1\nsub rdx, 4\nmovzx esi, sil\nadd ecx, esi\ncmp r8d, eax\njg short loc_1428\nmov eax, ecx\nretn\nloc_1450:\nxor ecx, ecx\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1400(__int64 a1, int a2)\n{\n int v2; // r8d\n __int64 v3; // rax\n unsigned int v4; // ecx\n _DWORD *v5; // rdx\n bool v6; // si\n\n v2 = a2 / 2;\n if ( a2 <= 1 )\n return 0LL;\n v3 = 0LL;\n v4 = 0;\n v5 = (_DWORD *)(a1 + 4LL * (a2 - 1));\n do\n {\n v6 = *(_DWORD *)(a1 + 4 * v3++) != *v5--;\n v4 += v6;\n }\n while ( v2 > (int)v3 );\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1400(long long a1, int a2) {\n int v2;\n long long v3;\n unsigned int v4;\n uint32_t *v5;\n bool v6;\n v2 = a2 / 2;\n if (a2 <= 1) return 0LL;\n v3 = 0LL;\n v4 = 0;\n v5 = (uint32_t *)(a1 + 4LL * (a2 - 1));\n do {\n v6 = *(uint32_t *)(a1 + 4 * v3++) != *v5--;\n v4 += v6;\n } while (v2 > (int)v3);\n return v4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int v2;\n long long v3;\n unsigned int v4;\n uint32_t *v5;\n bool v6;\n v2 = a2 / 2;\n if (a2 <= 1) return 0LL;\n v3 = 0LL;\n v4 = 0;\n v5 = (uint32_t *)(a1 + 4LL * (a2 - 1));\n do {\n v6 = *(uint32_t *)(a1 + 4 * v3++) != *v5--;\n v4 += v6;\n } while (v2 > (int)v3);\n return v4;\n}" + }, + { + "index": "HumanEval-C-74", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char** func0(char** arr1, int n1, char** arr2, int n2) {\n int i, sum1 = 0, sum2 = 0;\n for (i = 0; i < n1; i++) {\n sum1 += strlen(arr1[i]);\n }\n for (i = 0; i < n2; i++) {\n sum2 += strlen(arr2[i]);\n }\n if (sum1 < sum2) {\n return arr1;\n } else if (sum1 > sum2) {\n return arr2;\n } else {\n return arr1;\n }\n}", + "test": "int issame(char** arr1, int n1, char** arr2, int n2){\n\n int i;\n if(n1 != n2) return 0;\n\n for(i=0; i\n#include \n#include \n\nint main(){\n\n char* arr1[] = {};\n char* arr2[] = {};\n int n1 = 0, n2 = 0;\n issame(func0(arr1, n1, arr2, n2), n1, arr2, n2);\n\n char* arr3[] = {\"hi\", \"admin\"};\n char* arr4[] = {\"hi\", \"hi\"};\n n1 = 2; n2 = 2;\n issame(func0(arr3, n1, arr4, n2), n1, arr4, n2);\n\n char* arr5[] = {\"hi\", \"admin\"};\n char* arr6[] = {\"hi\", \"hi\", \"admin\", \"project\"};\n n1 = 2; n2 = 4;\n issame(func0(arr5, n1, arr6, n2), n1, arr5, n1);\n\n // Other test cases\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\nmov [rbp+var_C], 0\njmp short loc_11E7\nloc_11BA:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; s\ncall _strlen\nmov edx, eax\nmov eax, [rbp+var_8]\nadd eax, edx\nmov [rbp+var_8], eax\nadd [rbp+var_C], 1\nloc_11E7:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_11BA\nmov [rbp+var_C], 0\njmp short loc_1225\nloc_11F8:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; s\ncall _strlen\nmov edx, eax\nmov eax, [rbp+var_4]\nadd eax, edx\nmov [rbp+var_4], eax\nadd [rbp+var_C], 1\nloc_1225:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_20]\njl short loc_11F8\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njge short loc_123B\nmov rax, [rbp+var_18]\njmp short locret_124D\nloc_123B:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njle short loc_1249\nmov rax, [rbp+var_28]\njmp short locret_124D\nloc_1249:\nmov rax, [rbp+var_18]\nlocret_124D:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3, int a4)\n{\n int i; // [rsp+24h] [rbp-Ch]\n int j; // [rsp+24h] [rbp-Ch]\n int v9; // [rsp+28h] [rbp-8h]\n int v10; // [rsp+2Ch] [rbp-4h]\n\n v9 = 0;\n v10 = 0;\n for ( i = 0; i < a2; ++i )\n v9 += strlen(*(const char **)(8LL * i + a1));\n for ( j = 0; j < a4; ++j )\n v10 += strlen(*(const char **)(8LL * j + a3));\n if ( v9 < v10 )\n return a1;\n if ( v9 <= v10 )\n return a1;\n return a3;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\nmov [rbp+var_C], 0\njmp short loc_11E7\nloc_11BA:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; s\ncall _strlen\nmov edx, eax\nmov eax, [rbp+var_8]\nadd eax, edx\nmov [rbp+var_8], eax\nadd [rbp+var_C], 1\nloc_11E7:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_11BA\nmov [rbp+var_C], 0\njmp short loc_1225\nloc_11F8:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; s\ncall _strlen\nmov edx, eax\nmov eax, [rbp+var_4]\nadd eax, edx\nmov [rbp+var_4], eax\nadd [rbp+var_C], 1\nloc_1225:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_20]\njl short loc_11F8\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njge short loc_123B\nmov rax, [rbp+var_18]\njmp short locret_124D\nloc_123B:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njle short loc_1249\nmov rax, [rbp+var_28]\njmp short locret_124D\nloc_1249:\nmov rax, [rbp+var_18]\nlocret_124D:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2, __int64 a3, int a4)\n{\n int i; // [rsp+24h] [rbp-Ch]\n int j; // [rsp+24h] [rbp-Ch]\n int v9; // [rsp+28h] [rbp-8h]\n int v10; // [rsp+2Ch] [rbp-4h]\n\n v9 = 0;\n v10 = 0;\n for ( i = 0; i < a2; ++i )\n v9 += strlen(*(const char **)(8LL * i + a1));\n for ( j = 0; j < a4; ++j )\n v10 += strlen(*(const char **)(8LL * j + a3));\n if ( v9 < v10 )\n return a1;\n if ( v9 <= v10 )\n return a1;\n return a3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2, long long a3, int a4) {\n int i;\n int j;\n int v9;\n int v10;\n v9 = 0;\n v10 = 0;\n for (i = 0; i < a2; ++i) v9 += strlen(*(const char **)(8LL * i + a1));\n for (j = 0; j < a4; ++j) v10 += strlen(*(const char **)(8LL * j + a3));\n if (v9 < v10) return a1;\n if (v9 <= v10) return a1;\n return a3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3, int a4) {\n int i;\n int j;\n int v9;\n int v10;\n v9 = 0;\n v10 = 0;\n for (i = 0; i < a2; ++i) v9 += strlen(*(const char **)(8LL * i + a1));\n for (j = 0; j < a4; ++j) v10 += strlen(*(const char **)(8LL * j + a3));\n if (v9 < v10) return a1;\n if (v9 <= v10) return a1;\n return a3;\n}" + }, + { + "index": "HumanEval-C-74", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char** func0(char** arr1, int n1, char** arr2, int n2) {\n int i, sum1 = 0, sum2 = 0;\n for (i = 0; i < n1; i++) {\n sum1 += strlen(arr1[i]);\n }\n for (i = 0; i < n2; i++) {\n sum2 += strlen(arr2[i]);\n }\n if (sum1 < sum2) {\n return arr1;\n } else if (sum1 > sum2) {\n return arr2;\n } else {\n return arr1;\n }\n}", + "test": "int issame(char** arr1, int n1, char** arr2, int n2){\n\n int i;\n if(n1 != n2) return 0;\n\n for(i=0; i\n#include \n#include \n\nint main(){\n\n char* arr1[] = {};\n char* arr2[] = {};\n int n1 = 0, n2 = 0;\n issame(func0(arr1, n1, arr2, n2), n1, arr2, n2);\n\n char* arr3[] = {\"hi\", \"admin\"};\n char* arr4[] = {\"hi\", \"hi\"};\n n1 = 2; n2 = 2;\n issame(func0(arr3, n1, arr4, n2), n1, arr4, n2);\n\n char* arr5[] = {\"hi\", \"admin\"};\n char* arr6[] = {\"hi\", \"hi\", \"admin\", \"project\"};\n n1 = 2; n2 = 4;\n issame(func0(arr5, n1, arr6, n2), n1, arr5, n1);\n\n // Other test cases\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r14, rdi\nmov r13, rdx\nmov r12d, ecx\ntest esi, esi\njle short loc_11F1\nmov rbx, rdi\nmovsxd rsi, esi\nlea r15, [rdi+rsi*8]\nmov ebp, 0\nloc_1197:\nmov rdi, [rbx]; s\ncall _strlen\nadd ebp, eax\nadd rbx, 8\ncmp rbx, r15\njnz short loc_1197\ntest r12d, r12d\njle short loc_11E9\nloc_11AF:\nmov ebx, 0\nmov r15d, 0\nloc_11BA:\nmov rdi, [r13+rbx*8+0]; s\ncall _strlen\nadd r15d, eax\nadd rbx, 1\ncmp r12d, ebx\njg short loc_11BA\nloc_11D0:\ncmp ebp, r15d\nmov rax, r13\ncmovle rax, r14\nloc_11DA:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_11E9:\nmov r15d, 0\njmp short loc_11D0\nloc_11F1:\nmov ebp, 0\ntest ecx, ecx\njg short loc_11AF\nmov rax, rdi\njmp short loc_11DA", + "ida_pseudo": "const char **__fastcall func0(const char **a1, int a2, const char **a3, int a4)\n{\n const char **v6; // rbx\n int v7; // ebp\n __int64 v8; // rbx\n int v9; // r15d\n const char **result; // rax\n\n if ( a2 <= 0 )\n {\n v7 = 0;\n if ( a4 <= 0 )\n return a1;\n goto LABEL_5;\n }\n v6 = a1;\n v7 = 0;\n do\n v7 += strlen(*v6++);\n while ( v6 != &a1[a2] );\n if ( a4 > 0 )\n {\nLABEL_5:\n v8 = 0LL;\n v9 = 0;\n do\n v9 += strlen(a3[v8++]);\n while ( a4 > (int)v8 );\n goto LABEL_7;\n }\n v9 = 0;\nLABEL_7:\n result = a3;\n if ( v7 <= v9 )\n return a1;\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r14, rdi\nmov r13, rdx\nmov r12d, ecx\ntest esi, esi\njle short loc_11F1\nmov rbx, rdi\nmovsxd rsi, esi\nlea r15, [rdi+rsi*8]\nmov ebp, 0\nloc_1197:\nmov rdi, [rbx]; s\ncall _strlen\nadd ebp, eax\nadd rbx, 8\ncmp rbx, r15\njnz short loc_1197\ntest r12d, r12d\njle short loc_11E9\nloc_11AF:\nmov ebx, 0\nmov r15d, 0\nloc_11BA:\nmov rdi, [r13+rbx*8+0]; s\ncall _strlen\nadd r15d, eax\nadd rbx, 1\ncmp r12d, ebx\njg short loc_11BA\nloc_11D0:\ncmp ebp, r15d\nmov rax, r13\ncmovle rax, r14\nloc_11DA:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_11E9:\nmov r15d, 0\njmp short loc_11D0\nloc_11F1:\nmov ebp, 0\ntest ecx, ecx\njg short loc_11AF\nmov rax, rdi\njmp short loc_11DA", + "ida_strip_pseudo": "const char **__fastcall sub_1169(const char **a1, int a2, const char **a3, int a4)\n{\n const char **v6; // rbx\n int v7; // ebp\n __int64 v8; // rbx\n int v9; // r15d\n const char **result; // rax\n\n if ( a2 <= 0 )\n {\n v7 = 0;\n if ( a4 <= 0 )\n return a1;\n goto LABEL_5;\n }\n v6 = a1;\n v7 = 0;\n do\n v7 += strlen(*v6++);\n while ( v6 != &a1[a2] );\n if ( a4 > 0 )\n {\nLABEL_5:\n v8 = 0LL;\n v9 = 0;\n do\n v9 += strlen(a3[v8++]);\n while ( a4 > (int)v8 );\n goto LABEL_7;\n }\n v9 = 0;\nLABEL_7:\n result = a3;\n if ( v7 <= v9 )\n return a1;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char **sub_1169(const char **a1, int a2, const char **a3, int a4) {\n const char **v6;\n int v7;\n long long v8;\n int v9;\n const char **result;\n if (a2 <= 0) {\n v7 = 0;\n if (a4 <= 0) return a1;\n goto LABEL_5;\n }\n v6 = a1;\n v7 = 0;\n do\n v7 += strlen(*v6++);\n while (v6 != &a1[a2]);\n if (a4 > 0) {\n LABEL_5:\n v8 = 0LL;\n v9 = 0;\n do\n v9 += strlen(a3[v8++]);\n while (a4 > (int)v8);\n goto LABEL_7;\n }\n v9 = 0;\nLABEL_7:\n result = a3;\n if (v7 <= v9) return a1;\n return result;\n}", + "ida_pseudo_norm": "const char **func0(const char **a1, int a2, const char **a3, int a4) {\n const char **v6;\n int v7;\n long long v8;\n int v9;\n const char **result;\n if (a2 <= 0) {\n v7 = 0;\n if (a4 <= 0) return a1;\n goto LABEL_5;\n }\n v6 = a1;\n v7 = 0;\n do\n v7 += strlen(*v6++);\n while (v6 != &a1[a2]);\n if (a4 > 0) {\n LABEL_5:\n v8 = 0LL;\n v9 = 0;\n do\n v9 += strlen(a3[v8++]);\n while (a4 > (int)v8);\n goto LABEL_7;\n }\n v9 = 0;\nLABEL_7:\n result = a3;\n if (v7 <= v9) return a1;\n return result;\n}" + }, + { + "index": "HumanEval-C-74", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char** func0(char** arr1, int n1, char** arr2, int n2) {\n int i, sum1 = 0, sum2 = 0;\n for (i = 0; i < n1; i++) {\n sum1 += strlen(arr1[i]);\n }\n for (i = 0; i < n2; i++) {\n sum2 += strlen(arr2[i]);\n }\n if (sum1 < sum2) {\n return arr1;\n } else if (sum1 > sum2) {\n return arr2;\n } else {\n return arr1;\n }\n}", + "test": "int issame(char** arr1, int n1, char** arr2, int n2){\n\n int i;\n if(n1 != n2) return 0;\n\n for(i=0; i\n#include \n#include \n\nint main(){\n\n char* arr1[] = {};\n char* arr2[] = {};\n int n1 = 0, n2 = 0;\n issame(func0(arr1, n1, arr2, n2), n1, arr2, n2);\n\n char* arr3[] = {\"hi\", \"admin\"};\n char* arr4[] = {\"hi\", \"hi\"};\n n1 = 2; n2 = 2;\n issame(func0(arr3, n1, arr4, n2), n1, arr4, n2);\n\n char* arr5[] = {\"hi\", \"admin\"};\n char* arr6[] = {\"hi\", \"hi\", \"admin\", \"project\"};\n n1 = 2; n2 = 4;\n issame(func0(arr5, n1, arr6, n2), n1, arr5, n1);\n\n // Other test cases\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14, rdi\npush r13\nmov r13d, ecx\npush r12\nmov r12, rdx\npush rbp\npush rbx\nsub rsp, 8\ntest esi, esi\njle short loc_1200\nmovsxd rsi, esi\nmov rbx, rdi\nxor ebp, ebp\nlea r15, [rdi+rsi*8]\nnop dword ptr [rax+rax+00h]\nloc_11B0:\nmov rdi, [rbx]; s\nadd rbx, 8\ncall _strlen\nadd ebp, eax\ncmp r15, rbx\njnz short loc_11B0\ntest r13d, r13d\njle short loc_1210\nloc_11C8:\nxor ebx, ebx\nxor r15d, r15d\nnop dword ptr [rax]\nloc_11D0:\nmov rdi, [r12+rbx*8]; s\nadd rbx, 1\ncall _strlen\nadd r15d, eax\ncmp r13d, ebx\njg short loc_11D0\nloc_11E5:\ncmp ebp, r15d\ncmovle r12, r14\nloc_11EC:\nadd rsp, 8\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1200:\nxor ebp, ebp\ntest ecx, ecx\njg short loc_11C8\nmov r12, rdi\njmp short loc_11EC\nloc_1210:\nxor r15d, r15d\njmp short loc_11E5", + "ida_pseudo": "const char **__fastcall func0(const char **a1, int a2, __int64 a3, int a4)\n{\n const char **v7; // rbx\n int v8; // ebp\n const char **v9; // r15\n const char *v10; // rdi\n __int64 v11; // rbx\n int v12; // r15d\n const char *v13; // rdi\n\n if ( a2 <= 0 )\n {\n v8 = 0;\n if ( a4 <= 0 )\n return a1;\n }\n else\n {\n v7 = a1;\n v8 = 0;\n v9 = &a1[a2];\n do\n {\n v10 = *v7++;\n v8 += strlen(v10);\n }\n while ( v9 != v7 );\n if ( a4 <= 0 )\n {\n v12 = 0;\n goto LABEL_7;\n }\n }\n v11 = 0LL;\n v12 = 0;\n do\n {\n v13 = *(const char **)(a3 + 8 * v11++);\n v12 += strlen(v13);\n }\n while ( a4 > (int)v11 );\nLABEL_7:\n if ( v8 <= v12 )\n return a1;\n return (const char **)a3;\n}", + "ida_strip_asm": "sub_1180:\nendbr64\npush r15\npush r14\nmov r14, rdi\npush r13\nmov r13d, ecx\npush r12\nmov r12, rdx\npush rbp\npush rbx\nsub rsp, 8\ntest esi, esi\njle short loc_1200\nmovsxd rsi, esi\nmov rbx, rdi\nxor ebp, ebp\nlea r15, [rdi+rsi*8]\nnop dword ptr [rax+rax+00h]\nloc_11B0:\nmov rdi, [rbx]; s\nadd rbx, 8\ncall _strlen\nadd ebp, eax\ncmp r15, rbx\njnz short loc_11B0\ntest r13d, r13d\njle short loc_1210\nloc_11C8:\nxor ebx, ebx\nxor r15d, r15d\nnop dword ptr [rax]\nloc_11D0:\nmov rdi, [r12+rbx*8]; s\nadd rbx, 1\ncall _strlen\nadd r15d, eax\ncmp r13d, ebx\njg short loc_11D0\nloc_11E5:\ncmp ebp, r15d\ncmovle r12, r14\nloc_11EC:\nadd rsp, 8\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1200:\nxor ebp, ebp\ntest ecx, ecx\njg short loc_11C8\nmov r12, rdi\njmp short loc_11EC\nloc_1210:\nxor r15d, r15d\njmp short loc_11E5", + "ida_strip_pseudo": "const char **__fastcall sub_1180(const char **a1, int a2, __int64 a3, int a4)\n{\n const char **v7; // rbx\n int v8; // ebp\n const char **v9; // r15\n const char *v10; // rdi\n __int64 v11; // rbx\n int v12; // r15d\n const char *v13; // rdi\n\n if ( a2 <= 0 )\n {\n v8 = 0;\n if ( a4 <= 0 )\n return a1;\n }\n else\n {\n v7 = a1;\n v8 = 0;\n v9 = &a1[a2];\n do\n {\n v10 = *v7++;\n v8 += strlen(v10);\n }\n while ( v9 != v7 );\n if ( a4 <= 0 )\n {\n v12 = 0;\n goto LABEL_7;\n }\n }\n v11 = 0LL;\n v12 = 0;\n do\n {\n v13 = *(const char **)(a3 + 8 * v11++);\n v12 += strlen(v13);\n }\n while ( a4 > (int)v11 );\nLABEL_7:\n if ( v8 <= v12 )\n return a1;\n return (const char **)a3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char **sub_1180(const char **a1, int a2, long long a3, int a4) {\n const char **v7;\n int v8;\n const char **v9;\n const char *v10;\n long long v11;\n int v12;\n const char *v13;\n if (a2 <= 0) {\n v8 = 0;\n if (a4 <= 0) return a1;\n } else {\n v7 = a1;\n v8 = 0;\n v9 = &a1[a2];\n do {\n v10 = *v7++;\n v8 += strlen(v10);\n } while (v9 != v7);\n if (a4 <= 0) {\n v12 = 0;\n goto LABEL_7;\n }\n }\n v11 = 0LL;\n v12 = 0;\n do {\n v13 = *(const char **)(a3 + 8 * v11++);\n v12 += strlen(v13);\n } while (a4 > (int)v11);\nLABEL_7:\n if (v8 <= v12) return a1;\n return (const char **)a3;\n}", + "ida_pseudo_norm": "const char **func0(const char **a1, int a2, long long a3, int a4) {\n const char **v7;\n int v8;\n const char **v9;\n const char *v10;\n long long v11;\n int v12;\n const char *v13;\n if (a2 <= 0) {\n v8 = 0;\n if (a4 <= 0) return a1;\n } else {\n v7 = a1;\n v8 = 0;\n v9 = &a1[a2];\n do {\n v10 = *v7++;\n v8 += strlen(v10);\n } while (v9 != v7);\n if (a4 <= 0) {\n v12 = 0;\n goto LABEL_7;\n }\n }\n v11 = 0LL;\n v12 = 0;\n do {\n v13 = *(const char **)(a3 + 8 * v11++);\n v12 += strlen(v13);\n } while (a4 > (int)v11);\nLABEL_7:\n if (v8 <= v12) return a1;\n return (const char **)a3;\n}" + }, + { + "index": "HumanEval-C-74", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char** func0(char** arr1, int n1, char** arr2, int n2) {\n int i, sum1 = 0, sum2 = 0;\n for (i = 0; i < n1; i++) {\n sum1 += strlen(arr1[i]);\n }\n for (i = 0; i < n2; i++) {\n sum2 += strlen(arr2[i]);\n }\n if (sum1 < sum2) {\n return arr1;\n } else if (sum1 > sum2) {\n return arr2;\n } else {\n return arr1;\n }\n}", + "test": "int issame(char** arr1, int n1, char** arr2, int n2){\n\n int i;\n if(n1 != n2) return 0;\n\n for(i=0; i\n#include \n#include \n\nint main(){\n\n char* arr1[] = {};\n char* arr2[] = {};\n int n1 = 0, n2 = 0;\n issame(func0(arr1, n1, arr2, n2), n1, arr2, n2);\n\n char* arr3[] = {\"hi\", \"admin\"};\n char* arr4[] = {\"hi\", \"hi\"};\n n1 = 2; n2 = 2;\n issame(func0(arr3, n1, arr4, n2), n1, arr4, n2);\n\n char* arr5[] = {\"hi\", \"admin\"};\n char* arr6[] = {\"hi\", \"hi\", \"admin\", \"project\"};\n n1 = 2; n2 = 4;\n issame(func0(arr5, n1, arr6, n2), n1, arr5, n1);\n\n // Other test cases\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14, rdi\npush r13\nmov r13d, ecx\npush r12\nmov r12, rdx\npush rbp\npush rbx\nsub rsp, 8\ntest esi, esi\njle short loc_1200\nmovsxd rsi, esi\nmov rbx, rdi\nxor ebp, ebp\nlea r15, [rdi+rsi*8]\nnop dword ptr [rax+rax+00h]\nloc_11B0:\nmov rdi, [rbx]; s\nadd rbx, 8\ncall _strlen\nadd ebp, eax\ncmp r15, rbx\njnz short loc_11B0\ntest r13d, r13d\njle short loc_1210\nloc_11C8:\nxor ebx, ebx\nxor r15d, r15d\nnop dword ptr [rax]\nloc_11D0:\nmov rdi, [r12+rbx*8]; s\nadd rbx, 1\ncall _strlen\nadd r15d, eax\ncmp r13d, ebx\njg short loc_11D0\nloc_11E5:\ncmp ebp, r15d\ncmovle r12, r14\nloc_11EC:\nadd rsp, 8\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1200:\nxor ebp, ebp\ntest ecx, ecx\njg short loc_11C8\nmov r12, rdi\njmp short loc_11EC\nloc_1210:\nxor r15d, r15d\njmp short loc_11E5", + "ida_pseudo": "const char **__fastcall func0(const char **a1, int a2, __int64 a3, int a4)\n{\n const char **v7; // rbx\n int v8; // ebp\n const char **v9; // r15\n const char *v10; // rdi\n __int64 v11; // rbx\n int v12; // r15d\n const char *v13; // rdi\n\n if ( a2 <= 0 )\n {\n v8 = 0;\n if ( a4 <= 0 )\n return a1;\n }\n else\n {\n v7 = a1;\n v8 = 0;\n v9 = &a1[a2];\n do\n {\n v10 = *v7++;\n v8 += strlen(v10);\n }\n while ( v9 != v7 );\n if ( a4 <= 0 )\n {\n v12 = 0;\n goto LABEL_7;\n }\n }\n v11 = 0LL;\n v12 = 0;\n do\n {\n v13 = *(const char **)(a3 + 8 * v11++);\n v12 += strlen(v13);\n }\n while ( a4 > (int)v11 );\nLABEL_7:\n if ( v8 <= v12 )\n return a1;\n return (const char **)a3;\n}", + "ida_strip_asm": "sub_1180:\nendbr64\npush r15\npush r14\nmov r14, rdi\npush r13\nmov r13d, ecx\npush r12\nmov r12, rdx\npush rbp\npush rbx\nsub rsp, 8\ntest esi, esi\njle short loc_1200\nmovsxd rsi, esi\nmov rbx, rdi\nxor ebp, ebp\nlea r15, [rdi+rsi*8]\nnop dword ptr [rax+rax+00h]\nloc_11B0:\nmov rdi, [rbx]; s\nadd rbx, 8\ncall _strlen\nadd ebp, eax\ncmp r15, rbx\njnz short loc_11B0\ntest r13d, r13d\njle short loc_1210\nloc_11C8:\nxor ebx, ebx\nxor r15d, r15d\nnop dword ptr [rax]\nloc_11D0:\nmov rdi, [r12+rbx*8]; s\nadd rbx, 1\ncall _strlen\nadd r15d, eax\ncmp r13d, ebx\njg short loc_11D0\nloc_11E5:\ncmp ebp, r15d\ncmovle r12, r14\nloc_11EC:\nadd rsp, 8\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1200:\nxor ebp, ebp\ntest ecx, ecx\njg short loc_11C8\nmov r12, rdi\njmp short loc_11EC\nloc_1210:\nxor r15d, r15d\njmp short loc_11E5", + "ida_strip_pseudo": "const char **__fastcall sub_1180(const char **a1, int a2, __int64 a3, int a4)\n{\n const char **v7; // rbx\n int v8; // ebp\n const char **v9; // r15\n const char *v10; // rdi\n __int64 v11; // rbx\n int v12; // r15d\n const char *v13; // rdi\n\n if ( a2 <= 0 )\n {\n v8 = 0;\n if ( a4 <= 0 )\n return a1;\n }\n else\n {\n v7 = a1;\n v8 = 0;\n v9 = &a1[a2];\n do\n {\n v10 = *v7++;\n v8 += strlen(v10);\n }\n while ( v9 != v7 );\n if ( a4 <= 0 )\n {\n v12 = 0;\n goto LABEL_7;\n }\n }\n v11 = 0LL;\n v12 = 0;\n do\n {\n v13 = *(const char **)(a3 + 8 * v11++);\n v12 += strlen(v13);\n }\n while ( a4 > (int)v11 );\nLABEL_7:\n if ( v8 <= v12 )\n return a1;\n return (const char **)a3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char **sub_1180(const char **a1, int a2, long long a3, int a4) {\n const char **v7;\n int v8;\n const char **v9;\n const char *v10;\n long long v11;\n int v12;\n const char *v13;\n if (a2 <= 0) {\n v8 = 0;\n if (a4 <= 0) return a1;\n } else {\n v7 = a1;\n v8 = 0;\n v9 = &a1[a2];\n do {\n v10 = *v7++;\n v8 += strlen(v10);\n } while (v9 != v7);\n if (a4 <= 0) {\n v12 = 0;\n goto LABEL_7;\n }\n }\n v11 = 0LL;\n v12 = 0;\n do {\n v13 = *(const char **)(a3 + 8 * v11++);\n v12 += strlen(v13);\n } while (a4 > (int)v11);\nLABEL_7:\n if (v8 <= v12) return a1;\n return (const char **)a3;\n}", + "ida_pseudo_norm": "const char **func0(const char **a1, int a2, long long a3, int a4) {\n const char **v7;\n int v8;\n const char **v9;\n const char *v10;\n long long v11;\n int v12;\n const char *v13;\n if (a2 <= 0) {\n v8 = 0;\n if (a4 <= 0) return a1;\n } else {\n v7 = a1;\n v8 = 0;\n v9 = &a1[a2];\n do {\n v10 = *v7++;\n v8 += strlen(v10);\n } while (v9 != v7);\n if (a4 <= 0) {\n v12 = 0;\n goto LABEL_7;\n }\n }\n v11 = 0LL;\n v12 = 0;\n do {\n v13 = *(const char **)(a3 + 8 * v11++);\n v12 += strlen(v13);\n } while (a4 > (int)v11);\nLABEL_7:\n if (v8 <= v12) return a1;\n return (const char **)a3;\n}" + }, + { + "index": "HumanEval-C-75", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(int a) {\n if (a < 2) return 0;\n int num = 0;\n for (int i = 2; i * i <= a; i++) {\n while (a % i == 0) {\n a = a / i;\n num++;\n }\n }\n if (a > 1) num++;\n return num == 3;\n}", + "test": "#include \n\nint main() {\n assert(func0(5) == 0);\n assert(func0(30) == 1);\n assert(func0(8) == 1); // 8 = 2 * 2 * 2\n assert(func0(10) == 0);\n assert(func0(125) == 1); // 125 = 5 * 5 * 5 (three times the same prime)\n assert(func0(3 * 5 * 7) == 1);\n assert(func0(3 * 6 * 7) == 0);\n assert(func0(9 * 9 * 9) == 0);\n assert(func0(11 * 9 * 9) == 0);\n assert(func0(11 * 13 * 7) == 1);\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\ncmp [rbp+var_14], 1\njg short loc_1181\nmov eax, 0\njmp short loc_11CF\nloc_1181:\nmov [rbp+var_8], 0\nmov [rbp+var_4], 2\njmp short loc_11B0\nloc_1191:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\nmov [rbp+var_14], eax\nadd [rbp+var_8], 1\nloc_119F:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njz short loc_1191\nadd [rbp+var_4], 1\nloc_11B0:\nmov eax, [rbp+var_4]\nimul eax, eax\ncmp [rbp+var_14], eax\njge short loc_119F\ncmp [rbp+var_14], 1\njle short loc_11C5\nadd [rbp+var_8], 1\nloc_11C5:\ncmp [rbp+var_8], 3\nsetz al\nmovzx eax, al\nloc_11CF:\npop rbp\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(int a1)\n{\n int v2; // [rsp+0h] [rbp-14h]\n int v3; // [rsp+Ch] [rbp-8h]\n int i; // [rsp+10h] [rbp-4h]\n\n v2 = a1;\n if ( a1 <= 1 )\n return 0LL;\n v3 = 0;\n for ( i = 2; v2 >= i * i; ++i )\n {\n while ( !(v2 % i) )\n {\n v2 /= i;\n ++v3;\n }\n }\n if ( v2 > 1 )\n ++v3;\n return v3 == 3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\ncmp [rbp+var_14], 1\njg short loc_1181\nmov eax, 0\njmp short loc_11CF\nloc_1181:\nmov [rbp+var_8], 0\nmov [rbp+var_4], 2\njmp short loc_11B0\nloc_1191:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\nmov [rbp+var_14], eax\nadd [rbp+var_8], 1\nloc_119F:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njz short loc_1191\nadd [rbp+var_4], 1\nloc_11B0:\nmov eax, [rbp+var_4]\nimul eax, eax\ncmp [rbp+var_14], eax\njge short loc_119F\ncmp [rbp+var_14], 1\njle short loc_11C5\nadd [rbp+var_8], 1\nloc_11C5:\ncmp [rbp+var_8], 3\nsetz al\nmovzx eax, al\nloc_11CF:\npop rbp\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1169(int a1)\n{\n int v2; // [rsp+0h] [rbp-14h]\n int v3; // [rsp+Ch] [rbp-8h]\n int i; // [rsp+10h] [rbp-4h]\n\n v2 = a1;\n if ( a1 <= 1 )\n return 0LL;\n v3 = 0;\n for ( i = 2; v2 >= i * i; ++i )\n {\n while ( !(v2 % i) )\n {\n v2 /= i;\n ++v3;\n }\n }\n if ( v2 > 1 )\n ++v3;\n return v3 == 3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1169(int a1) {\n int v2;\n int v3;\n int i;\n v2 = a1;\n if (a1 <= 1) return 0LL;\n v3 = 0;\n for (i = 2; v2 >= i * i; ++i) {\n while (!(v2 % i)) {\n v2 /= i;\n ++v3;\n }\n }\n if (v2 > 1) ++v3;\n return v3 == 3;\n}", + "ida_pseudo_norm": "uint8_t func0(int a1) {\n int v2;\n int v3;\n int i;\n v2 = a1;\n if (a1 <= 1) return 0LL;\n v3 = 0;\n for (i = 2; v2 >= i * i; ++i) {\n while (!(v2 % i)) {\n v2 /= i;\n ++v3;\n }\n }\n if (v2 > 1) ++v3;\n return v3 == 3;\n}" + }, + { + "index": "HumanEval-C-75", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(int a) {\n if (a < 2) return 0;\n int num = 0;\n for (int i = 2; i * i <= a; i++) {\n while (a % i == 0) {\n a = a / i;\n num++;\n }\n }\n if (a > 1) num++;\n return num == 3;\n}", + "test": "#include \n\nint main() {\n assert(func0(5) == 0);\n assert(func0(30) == 1);\n assert(func0(8) == 1); // 8 = 2 * 2 * 2\n assert(func0(10) == 0);\n assert(func0(125) == 1); // 125 = 5 * 5 * 5 (three times the same prime)\n assert(func0(3 * 5 * 7) == 1);\n assert(func0(3 * 6 * 7) == 0);\n assert(func0(9 * 9 * 9) == 0);\n assert(func0(11 * 9 * 9) == 0);\n assert(func0(11 * 13 * 7) == 1);\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmov eax, 0\ncmp edi, 1\njle short locret_11C1\nmov ecx, 2\nmov esi, 0\ncmp edi, 3\njg short loc_11A5\njmp short loc_11B5\nloc_1188:\nmov eax, edi\ncdq\nidiv ecx\nmov edi, eax\nadd esi, 1\ncdq\nidiv ecx\ntest edx, edx\njz short loc_1188\nloc_1199:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, edi\njg short loc_11B0\nloc_11A5:\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njz short loc_1188\njmp short loc_1199\nloc_11B0:\ncmp edi, 1\njle short loc_11B8\nloc_11B5:\nadd esi, 1\nloc_11B8:\ncmp esi, 3\nsetz al\nmovzx eax, al\nlocret_11C1:\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(int a1)\n{\n _BOOL8 result; // rax\n int v2; // ecx\n int v3; // esi\n\n result = 0LL;\n if ( a1 > 1 )\n {\n v2 = 2;\n v3 = 0;\n if ( a1 <= 3 )\n goto LABEL_9;\n do\n {\n for ( ; !(a1 % v2); ++v3 )\n a1 /= v2;\n ++v2;\n }\n while ( v2 * v2 <= a1 );\n if ( a1 > 1 )\nLABEL_9:\n ++v3;\n return v3 == 3;\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov eax, 0\ncmp edi, 1\njle short locret_11C1\nmov ecx, 2\nmov esi, 0\ncmp edi, 3\njg short loc_11A5\njmp short loc_11B5\nloc_1188:\nmov eax, edi\ncdq\nidiv ecx\nmov edi, eax\nadd esi, 1\ncdq\nidiv ecx\ntest edx, edx\njz short loc_1188\nloc_1199:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, edi\njg short loc_11B0\nloc_11A5:\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njz short loc_1188\njmp short loc_1199\nloc_11B0:\ncmp edi, 1\njle short loc_11B8\nloc_11B5:\nadd esi, 1\nloc_11B8:\ncmp esi, 3\nsetz al\nmovzx eax, al\nlocret_11C1:\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1169(int a1)\n{\n _BOOL8 result; // rax\n int v2; // ecx\n int v3; // esi\n\n result = 0LL;\n if ( a1 > 1 )\n {\n v2 = 2;\n v3 = 0;\n if ( a1 <= 3 )\n goto LABEL_9;\n do\n {\n for ( ; !(a1 % v2); ++v3 )\n a1 /= v2;\n ++v2;\n }\n while ( v2 * v2 <= a1 );\n if ( a1 > 1 )\nLABEL_9:\n ++v3;\n return v3 == 3;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1169(int a1) {\n uint8_t result;\n int v2;\n int v3;\n result = 0LL;\n if (a1 > 1) {\n v2 = 2;\n v3 = 0;\n if (a1 <= 3) goto LABEL_9;\n do {\n for (; !(a1 % v2); ++v3) a1 /= v2;\n ++v2;\n } while (v2 * v2 <= a1);\n if (a1 > 1)\n LABEL_9:\n ++v3;\n return v3 == 3;\n }\n return result;\n}", + "ida_pseudo_norm": "uint8_t func0(int a1) {\n uint8_t result;\n int v2;\n int v3;\n result = 0LL;\n if (a1 > 1) {\n v2 = 2;\n v3 = 0;\n if (a1 <= 3) goto LABEL_9;\n do {\n for (; !(a1 % v2); ++v3) a1 /= v2;\n ++v2;\n } while (v2 * v2 <= a1);\n if (a1 > 1)\n LABEL_9:\n ++v3;\n return v3 == 3;\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-75", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(int a) {\n if (a < 2) return 0;\n int num = 0;\n for (int i = 2; i * i <= a; i++) {\n while (a % i == 0) {\n a = a / i;\n num++;\n }\n }\n if (a > 1) num++;\n return num == 3;\n}", + "test": "#include \n\nint main() {\n assert(func0(5) == 0);\n assert(func0(30) == 1);\n assert(func0(8) == 1); // 8 = 2 * 2 * 2\n assert(func0(10) == 0);\n assert(func0(125) == 1); // 125 = 5 * 5 * 5 (three times the same prime)\n assert(func0(3 * 5 * 7) == 1);\n assert(func0(3 * 6 * 7) == 0);\n assert(func0(9 * 9 * 9) == 0);\n assert(func0(11 * 9 * 9) == 0);\n assert(func0(11 * 13 * 7) == 1);\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0_part_0:\nxor esi, esi\nmov ecx, 2\ncmp edi, 3\njle short loc_13BD\nnop dword ptr [rax+00h]\nloc_1390:\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_13B1\nnop dword ptr [rax+00000000h]\nloc_13A0:\nmov eax, edi\nadd esi, 1\ncdq\nidiv ecx\ncdq\nmov edi, eax\nidiv ecx\ntest edx, edx\njz short loc_13A0\nloc_13B1:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, edi\njle short loc_1390\nloc_13BD:\nxor eax, eax\ncmp edi, 1\nsetnle al\nadd esi, eax\nxor eax, eax\ncmp esi, 3\nsetz al\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0_part_0(int a1)\n{\n int v1; // esi\n int v2; // ecx\n int v3; // edx\n\n v1 = 0;\n v2 = 2;\n if ( a1 > 3 )\n {\n do\n {\n if ( !(a1 % v2) )\n {\n do\n {\n ++v1;\n v3 = (a1 / v2) >> 31;\n a1 /= v2;\n }\n while ( !(unsigned int)(__SPAIR64__(v3, a1) % v2) );\n }\n ++v2;\n }\n while ( v2 * v2 <= a1 );\n }\n return (a1 > 1) + v1 == 3;\n}", + "ida_strip_asm": "sub_1380:\nxor esi, esi\nmov ecx, 2\ncmp edi, 3\njle short loc_13BD\nnop dword ptr [rax+00h]\nloc_1390:\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_13B1\nnop dword ptr [rax+00000000h]\nloc_13A0:\nmov eax, edi\nadd esi, 1\ncdq\nidiv ecx\ncdq\nmov edi, eax\nidiv ecx\ntest edx, edx\njz short loc_13A0\nloc_13B1:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, edi\njle short loc_1390\nloc_13BD:\nxor eax, eax\ncmp edi, 1\nsetnle al\nadd esi, eax\nxor eax, eax\ncmp esi, 3\nsetz al\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1380(int a1)\n{\n int v1; // esi\n int v2; // ecx\n int v3; // edx\n\n v1 = 0;\n v2 = 2;\n if ( a1 > 3 )\n {\n do\n {\n if ( !(a1 % v2) )\n {\n do\n {\n ++v1;\n v3 = (a1 / v2) >> 31;\n a1 /= v2;\n }\n while ( !(unsigned int)(__SPAIR64__(v3, a1) % v2) );\n }\n ++v2;\n }\n while ( v2 * v2 <= a1 );\n }\n return (a1 > 1) + v1 == 3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1380(int a1) {\n int v1;\n int v2;\n int v3;\n v1 = 0;\n v2 = 2;\n if (a1 > 3) {\n do {\n if (!(a1 % v2)) {\n do {\n ++v1;\n v3 = (a1 / v2) >> 31;\n a1 /= v2;\n } while (!(unsigned int)(__SPAIR64__(v3, a1) % v2));\n }\n ++v2;\n } while (v2 * v2 <= a1);\n }\n return (a1 > 1) + v1 == 3;\n}", + "ida_pseudo_norm": "uint8_t func0_part_0(int a1) {\n int v1;\n int v2;\n int v3;\n v1 = 0;\n v2 = 2;\n if (a1 > 3) {\n do {\n if (!(a1 % v2)) {\n do {\n ++v1;\n v3 = (a1 / v2) >> 31;\n a1 /= v2;\n } while (!(unsigned int)(__SPAIR64__(v3, a1) % v2));\n }\n ++v2;\n } while (v2 * v2 <= a1);\n }\n return (a1 > 1) + v1 == 3;\n}" + }, + { + "index": "HumanEval-C-75", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(int a) {\n if (a < 2) return 0;\n int num = 0;\n for (int i = 2; i * i <= a; i++) {\n while (a % i == 0) {\n a = a / i;\n num++;\n }\n }\n if (a > 1) num++;\n return num == 3;\n}", + "test": "#include \n\nint main() {\n assert(func0(5) == 0);\n assert(func0(30) == 1);\n assert(func0(8) == 1); // 8 = 2 * 2 * 2\n assert(func0(10) == 0);\n assert(func0(125) == 1); // 125 = 5 * 5 * 5 (three times the same prime)\n assert(func0(3 * 5 * 7) == 1);\n assert(func0(3 * 6 * 7) == 0);\n assert(func0(9 * 9 * 9) == 0);\n assert(func0(11 * 9 * 9) == 0);\n assert(func0(11 * 13 * 7) == 1);\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0_part_0:\nxor esi, esi\nmov ecx, 2\ncmp edi, 3\njle short loc_13BD\nnop dword ptr [rax+00h]\nloc_1390:\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_13B1\nnop dword ptr [rax+00000000h]\nloc_13A0:\nmov eax, edi\nadd esi, 1\ncdq\nidiv ecx\ncdq\nmov edi, eax\nidiv ecx\ntest edx, edx\njz short loc_13A0\nloc_13B1:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, edi\njle short loc_1390\nloc_13BD:\nxor eax, eax\ncmp edi, 1\nsetnle al\nadd esi, eax\nxor eax, eax\ncmp esi, 3\nsetz al\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0_part_0(int a1)\n{\n int v1; // esi\n int v2; // ecx\n int v3; // edx\n\n v1 = 0;\n v2 = 2;\n if ( a1 > 3 )\n {\n do\n {\n if ( !(a1 % v2) )\n {\n do\n {\n ++v1;\n v3 = (a1 / v2) >> 31;\n a1 /= v2;\n }\n while ( !(unsigned int)(__SPAIR64__(v3, a1) % v2) );\n }\n ++v2;\n }\n while ( v2 * v2 <= a1 );\n }\n return (a1 > 1) + v1 == 3;\n}", + "ida_strip_asm": "sub_1380:\nxor esi, esi\nmov ecx, 2\ncmp edi, 3\njle short loc_13BD\nnop dword ptr [rax+00h]\nloc_1390:\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_13B1\nnop dword ptr [rax+00000000h]\nloc_13A0:\nmov eax, edi\nadd esi, 1\ncdq\nidiv ecx\ncdq\nmov edi, eax\nidiv ecx\ntest edx, edx\njz short loc_13A0\nloc_13B1:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, edi\njle short loc_1390\nloc_13BD:\nxor eax, eax\ncmp edi, 1\nsetnle al\nadd esi, eax\nxor eax, eax\ncmp esi, 3\nsetz al\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1380(int a1)\n{\n int v1; // esi\n int v2; // ecx\n int v3; // edx\n\n v1 = 0;\n v2 = 2;\n if ( a1 > 3 )\n {\n do\n {\n if ( !(a1 % v2) )\n {\n do\n {\n ++v1;\n v3 = (a1 / v2) >> 31;\n a1 /= v2;\n }\n while ( !(unsigned int)(__SPAIR64__(v3, a1) % v2) );\n }\n ++v2;\n }\n while ( v2 * v2 <= a1 );\n }\n return (a1 > 1) + v1 == 3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1380(int a1) {\n int v1;\n int v2;\n int v3;\n v1 = 0;\n v2 = 2;\n if (a1 > 3) {\n do {\n if (!(a1 % v2)) {\n do {\n ++v1;\n v3 = (a1 / v2) >> 31;\n a1 /= v2;\n } while (!(unsigned int)(__SPAIR64__(v3, a1) % v2));\n }\n ++v2;\n } while (v2 * v2 <= a1);\n }\n return (a1 > 1) + v1 == 3;\n}", + "ida_pseudo_norm": "uint8_t func0_part_0(int a1) {\n int v1;\n int v2;\n int v3;\n v1 = 0;\n v2 = 2;\n if (a1 > 3) {\n do {\n if (!(a1 % v2)) {\n do {\n ++v1;\n v3 = (a1 / v2) >> 31;\n a1 /= v2;\n } while (!(unsigned int)(__SPAIR64__(v3, a1) % v2));\n }\n ++v2;\n } while (v2 * v2 <= a1);\n }\n return (a1 > 1) + v1 == 3;\n}" + }, + { + "index": "HumanEval-C-76", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int x, int n) {\n int p = 1, count = 0;\n while (p <= x && count < 100) {\n if (p == x) return 1;\n p = p * n;\n count += 1;\n }\n return 0;\n}", + "test": "#include \n\nint main() {\n assert(func0(1, 4) == 1);\n assert(func0(2, 2) == 1);\n assert(func0(8, 2) == 1);\n assert(func0(3, 2) == 0);\n assert(func0(3, 1) == 0);\n assert(func0(5, 3) == 0);\n assert(func0(16, 2) == 1);\n assert(func0(143214, 16) == 0);\n assert(func0(4, 2) == 1);\n assert(func0(9, 3) == 1);\n assert(func0(16, 4) == 1);\n assert(func0(24, 2) == 0);\n assert(func0(128, 4) == 0);\n assert(func0(12, 6) == 0);\n assert(func0(1, 1) == 1);\n assert(func0(1, 12) == 1);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_8], 1\nmov [rbp+var_4], 0\njmp short loc_1184\nloc_1167:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_14]\njnz short loc_1176\nmov eax, 1\njmp short loc_1197\nloc_1176:\nmov eax, [rbp+var_8]\nimul eax, [rbp+var_18]\nmov [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_1184:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_14]\njg short loc_1192\ncmp [rbp+var_4], 63h ; 'c'\njle short loc_1167\nloc_1192:\nmov eax, 0\nloc_1197:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n int v3; // [rsp+10h] [rbp-8h]\n int i; // [rsp+14h] [rbp-4h]\n\n v3 = 1;\n for ( i = 0; v3 <= a1 && i <= 99; ++i )\n {\n if ( v3 == a1 )\n return 1LL;\n v3 *= a2;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_8], 1\nmov [rbp+var_4], 0\njmp short loc_1184\nloc_1167:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_14]\njnz short loc_1176\nmov eax, 1\njmp short loc_1197\nloc_1176:\nmov eax, [rbp+var_8]\nimul eax, [rbp+var_18]\nmov [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_1184:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_14]\njg short loc_1192\ncmp [rbp+var_4], 63h ; 'c'\njle short loc_1167\nloc_1192:\nmov eax, 0\nloc_1197:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2)\n{\n int v3; // [rsp+10h] [rbp-8h]\n int i; // [rsp+14h] [rbp-4h]\n\n v3 = 1;\n for ( i = 0; v3 <= a1 && i <= 99; ++i )\n {\n if ( v3 == a1 )\n return 1LL;\n v3 *= a2;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2) {\n int v3;\n int i;\n v3 = 1;\n for (i = 0; v3 <= a1 && i <= 99; ++i) {\n if (v3 == a1) return 1LL;\n v3 *= a2;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n int v3;\n int i;\n v3 = 1;\n for (i = 0; v3 <= a1 && i <= 99; ++i) {\n if (v3 == a1) return 1LL;\n v3 *= a2;\n }\n return 0LL;\n}" + }, + { + "index": "HumanEval-C-76", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int x, int n) {\n int p = 1, count = 0;\n while (p <= x && count < 100) {\n if (p == x) return 1;\n p = p * n;\n count += 1;\n }\n return 0;\n}", + "test": "#include \n\nint main() {\n assert(func0(1, 4) == 1);\n assert(func0(2, 2) == 1);\n assert(func0(8, 2) == 1);\n assert(func0(3, 2) == 0);\n assert(func0(3, 1) == 0);\n assert(func0(5, 3) == 0);\n assert(func0(16, 2) == 1);\n assert(func0(143214, 16) == 0);\n assert(func0(4, 2) == 1);\n assert(func0(9, 3) == 1);\n assert(func0(16, 4) == 1);\n assert(func0(24, 2) == 0);\n assert(func0(128, 4) == 0);\n assert(func0(12, 6) == 0);\n assert(func0(1, 1) == 1);\n assert(func0(1, 12) == 1);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njle short loc_117F\ncmp edi, 1\njz short loc_1185\nmov ecx, 0\nmov edx, 1\nloc_1160:\nimul edx, esi\nadd ecx, 1\ncmp edi, edx\njl short loc_1179\ncmp ecx, 63h ; 'c'\njg short loc_1179\ncmp edi, edx\njnz short loc_1160\nmov eax, 1\nretn\nloc_1179:\nmov eax, 0\nretn\nloc_117F:\nmov eax, 0\nretn\nloc_1185:\nmov eax, edi\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n int v2; // ecx\n int v3; // edx\n\n if ( a1 <= 0 )\n return 0LL;\n if ( a1 == 1 )\n return 1LL;\n v2 = 0;\n v3 = 1;\n while ( 1 )\n {\n v3 *= a2;\n ++v2;\n if ( a1 < v3 || v2 > 99 )\n break;\n if ( a1 == v3 )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ntest edi, edi\njle short loc_117F\ncmp edi, 1\njz short loc_1185\nmov ecx, 0\nmov edx, 1\nloc_1160:\nimul edx, esi\nadd ecx, 1\ncmp edi, edx\njl short loc_1179\ncmp ecx, 63h ; 'c'\njg short loc_1179\ncmp edi, edx\njnz short loc_1160\nmov eax, 1\nretn\nloc_1179:\nmov eax, 0\nretn\nloc_117F:\nmov eax, 0\nretn\nloc_1185:\nmov eax, edi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2)\n{\n int v2; // ecx\n int v3; // edx\n\n if ( a1 <= 0 )\n return 0LL;\n if ( a1 == 1 )\n return 1LL;\n v2 = 0;\n v3 = 1;\n while ( 1 )\n {\n v3 *= a2;\n ++v2;\n if ( a1 < v3 || v2 > 99 )\n break;\n if ( a1 == v3 )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2) {\n int v2;\n int v3;\n if (a1 <= 0) return 0LL;\n if (a1 == 1) return 1LL;\n v2 = 0;\n v3 = 1;\n while (1) {\n v3 *= a2;\n ++v2;\n if (a1 < v3 || v2 > 99) break;\n if (a1 == v3) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n int v2;\n int v3;\n if (a1 <= 0) return 0LL;\n if (a1 == 1) return 1LL;\n v2 = 0;\n v3 = 1;\n while (1) {\n v3 *= a2;\n ++v2;\n if (a1 < v3 || v2 > 99) break;\n if (a1 == v3) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": "HumanEval-C-77", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int func0(int a) {\n for (int i = 0; i * i * i <= abs(a); i++)\n if (i * i * i == abs(a)) return 1;\n return 0;\n}", + "test": "#include \n\nint main() {\n assert(func0(1) == 1);\n assert(func0(2) == 0);\n assert(func0(-1) == 1);\n assert(func0(64) == 1);\n assert(func0(180) == 0);\n assert(func0(1000) == 1);\n assert(func0(0) == 1);\n assert(func0(1729) == 0);\n\n printf(\"All tests passed.\\n\");\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_4], 0\njmp short loc_11A2\nloc_117D:\nmov eax, [rbp+var_4]\nimul eax, eax\nimul eax, [rbp+var_4]\nmov edx, eax\nmov eax, [rbp+var_14]\nmov ecx, eax\nneg ecx\ncmovns eax, ecx\ncmp edx, eax\njnz short loc_119E\nmov eax, 1\njmp short loc_11C1\nloc_119E:\nadd [rbp+var_4], 1\nloc_11A2:\nmov eax, [rbp+var_4]\nimul eax, eax\nimul eax, [rbp+var_4]\nmov edx, eax\nmov eax, [rbp+var_14]\nmov ecx, eax\nneg ecx\ncmovns eax, ecx\ncmp edx, eax\njle short loc_117D\nmov eax, 0\nloc_11C1:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // eax\n int v3; // eax\n int i; // [rsp+10h] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n v3 = a1;\n if ( a1 <= 0 )\n v3 = -a1;\n if ( i * i * i > v3 )\n break;\n v1 = a1;\n if ( a1 <= 0 )\n v1 = -a1;\n if ( i * i * i == v1 )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_4], 0\njmp short loc_11A2\nloc_117D:\nmov eax, [rbp+var_4]\nimul eax, eax\nimul eax, [rbp+var_4]\nmov edx, eax\nmov eax, [rbp+var_14]\nmov ecx, eax\nneg ecx\ncmovns eax, ecx\ncmp edx, eax\njnz short loc_119E\nmov eax, 1\njmp short loc_11C1\nloc_119E:\nadd [rbp+var_4], 1\nloc_11A2:\nmov eax, [rbp+var_4]\nimul eax, eax\nimul eax, [rbp+var_4]\nmov edx, eax\nmov eax, [rbp+var_14]\nmov ecx, eax\nneg ecx\ncmovns eax, ecx\ncmp edx, eax\njle short loc_117D\nmov eax, 0\nloc_11C1:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n int v1; // eax\n int v3; // eax\n int i; // [rsp+10h] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n v3 = a1;\n if ( a1 <= 0 )\n v3 = -a1;\n if ( i * i * i > v3 )\n break;\n v1 = a1;\n if ( a1 <= 0 )\n v1 = -a1;\n if ( i * i * i == v1 )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n int v1;\n int v3;\n int i;\n for (i = 0;; ++i) {\n v3 = a1;\n if (a1 <= 0) v3 = -a1;\n if (i * i * i > v3) break;\n v1 = a1;\n if (a1 <= 0) v1 = -a1;\n if (i * i * i == v1) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v3;\n int i;\n for (i = 0;; ++i) {\n v3 = a1;\n if (a1 <= 0) v3 = -a1;\n if (i * i * i > v3) break;\n v1 = a1;\n if (a1 <= 0) v1 = -a1;\n if (i * i * i == v1) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": "HumanEval-C-77", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int func0(int a) {\n for (int i = 0; i * i * i <= abs(a); i++)\n if (i * i * i == abs(a)) return 1;\n return 0;\n}", + "test": "#include \n\nint main() {\n assert(func0(1) == 1);\n assert(func0(2) == 0);\n assert(func0(-1) == 1);\n assert(func0(64) == 1);\n assert(func0(180) == 0);\n assert(func0(1000) == 1);\n assert(func0(0) == 1);\n assert(func0(1729) == 0);\n\n printf(\"All tests passed.\\n\");\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmov ecx, edi\nneg ecx\ncmovs ecx, edi\ntest edi, edi\njz short loc_119A\nmov eax, 0\nloc_117D:\nadd eax, 1\nmov edx, eax\nimul edx, eax\nimul edx, eax\ncmp edx, ecx\njg short loc_1194\njnz short loc_117D\nmov eax, 1\nretn\nloc_1194:\nmov eax, 0\nretn\nloc_119A:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // ecx\n int v2; // eax\n int v3; // edx\n\n v1 = -a1;\n if ( a1 > 0 )\n v1 = a1;\n if ( !a1 )\n return 1LL;\n v2 = 0;\n while ( 1 )\n {\n ++v2;\n v3 = v2 * v2 * v2;\n if ( v3 > v1 )\n break;\n if ( v3 == v1 )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov ecx, edi\nneg ecx\ncmovs ecx, edi\ntest edi, edi\njz short loc_119A\nmov eax, 0\nloc_117D:\nadd eax, 1\nmov edx, eax\nimul edx, eax\nimul edx, eax\ncmp edx, ecx\njg short loc_1194\njnz short loc_117D\nmov eax, 1\nretn\nloc_1194:\nmov eax, 0\nretn\nloc_119A:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n int v1; // ecx\n int v2; // eax\n int v3; // edx\n\n v1 = -a1;\n if ( a1 > 0 )\n v1 = a1;\n if ( !a1 )\n return 1LL;\n v2 = 0;\n while ( 1 )\n {\n ++v2;\n v3 = v2 * v2 * v2;\n if ( v3 > v1 )\n break;\n if ( v3 == v1 )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n int v1;\n int v2;\n int v3;\n v1 = -a1;\n if (a1 > 0) v1 = a1;\n if (!a1) return 1LL;\n v2 = 0;\n while (1) {\n ++v2;\n v3 = v2 * v2 * v2;\n if (v3 > v1) break;\n if (v3 == v1) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v2;\n int v3;\n v1 = -a1;\n if (a1 > 0) v1 = a1;\n if (!a1) return 1LL;\n v2 = 0;\n while (1) {\n ++v2;\n v3 = v2 * v2 * v2;\n if (v3 > v1) break;\n if (v3 == v1) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": "HumanEval-C-78", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(const char* num) {\n const char* key = \"2357BD\";\n int out = 0;\n for (int i = 0; i < strlen(num); i++) {\n if (strchr(key, num[i])) out += 1;\n }\n return out;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"AB\") == 1);\n assert(func0(\"1077E\") == 2);\n assert(func0(\"ABED1A33\") == 4);\n assert(func0(\"2020\") == 2);\n assert(func0(\"123456789ABCDEF0\") == 6);\n assert(func0(\"112233445566778899AABBCCDDEEFF00\") == 12);\n assert(func0(\"\") == 0);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+var_28], rdi\nlea rax, a2357bd; \"2357BD\"\nmov [rbp+s], rax\nmov [rbp+var_20], 0\nmov [rbp+var_1C], 0\njmp short loc_11E3\nloc_11B5:\nmov eax, [rbp+var_1C]\nmovsxd rdx, eax\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx edx, al\nmov rax, [rbp+s]\nmov esi, edx; c\nmov rdi, rax; s\ncall _strchr\ntest rax, rax\njz short loc_11DF\nadd [rbp+var_20], 1\nloc_11DF:\nadd [rbp+var_1C], 1\nloc_11E3:\nmov eax, [rbp+var_1C]\nmovsxd rbx, eax\nmov rax, [rbp+var_28]\nmov rdi, rax; s\ncall _strlen\ncmp rbx, rax\njb short loc_11B5\nmov eax, [rbp+var_20]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n unsigned int v2; // [rsp+10h] [rbp-20h]\n int i; // [rsp+14h] [rbp-1Ch]\n\n v2 = 0;\n for ( i = 0; i < strlen(a1); ++i )\n {\n if ( strchr(\"2357BD\", a1[i]) )\n ++v2;\n }\n return v2;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+var_28], rdi\nlea rax, a2357bd; \"2357BD\"\nmov [rbp+s], rax\nmov [rbp+var_20], 0\nmov [rbp+var_1C], 0\njmp short loc_11E3\nloc_11B5:\nmov eax, [rbp+var_1C]\nmovsxd rdx, eax\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx edx, al\nmov rax, [rbp+s]\nmov esi, edx; c\nmov rdi, rax; s\ncall _strchr\ntest rax, rax\njz short loc_11DF\nadd [rbp+var_20], 1\nloc_11DF:\nadd [rbp+var_1C], 1\nloc_11E3:\nmov eax, [rbp+var_1C]\nmovsxd rbx, eax\nmov rax, [rbp+var_28]\nmov rdi, rax; s\ncall _strlen\ncmp rbx, rax\njb short loc_11B5\nmov eax, [rbp+var_20]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(const char *a1)\n{\n unsigned int v2; // [rsp+10h] [rbp-20h]\n int i; // [rsp+14h] [rbp-1Ch]\n\n v2 = 0;\n for ( i = 0; i < strlen(a1); ++i )\n {\n if ( strchr(\"2357BD\", a1[i]) )\n ++v2;\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(const char *a1) {\n unsigned int v2;\n int i;\n v2 = 0;\n for (i = 0; i < strlen(a1); ++i) {\n if (strchr(\"2357BD\", a1[i])) ++v2;\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n unsigned int v2;\n int i;\n v2 = 0;\n for (i = 0; i < strlen(a1); ++i) {\n if (strchr(\"2357BD\", a1[i])) ++v2;\n }\n return v2;\n}" + }, + { + "index": "HumanEval-C-78", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(const char* num) {\n const char* key = \"2357BD\";\n int out = 0;\n for (int i = 0; i < strlen(num); i++) {\n if (strchr(key, num[i])) out += 1;\n }\n return out;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"AB\") == 1);\n assert(func0(\"1077E\") == 2);\n assert(func0(\"ABED1A33\") == 4);\n assert(func0(\"2020\") == 2);\n assert(func0(\"123456789ABCDEF0\") == 6);\n assert(func0(\"112233445566778899AABBCCDDEEFF00\") == 12);\n assert(func0(\"\") == 0);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12, rdi\ncall _strlen\nmov rbx, r12\nadd r12, rax\nmov ebp, 0\nlea r13, s; \"2357BD\"\njmp short loc_11C9\nloc_11B3:\nmovsx esi, byte ptr [rbx]; c\nmov rdi, r13; s\ncall _strchr\ncmp rax, 1\nsbb ebp, 0FFFFFFFFh\nadd rbx, 1\nloc_11C9:\ncmp rbx, r12\njnz short loc_11B3\nmov eax, ebp\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n const char *v1; // rbx\n char *v2; // r12\n unsigned int v3; // ebp\n\n v1 = a1;\n v2 = (char *)&a1[strlen(a1)];\n v3 = 0;\n while ( v1 != v2 )\n v3 -= (strchr(\"2357BD\", *v1++) == 0LL) - 1;\n return v3;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12, rdi\ncall _strlen\nmov rbx, r12\nadd r12, rax\nmov ebp, 0\nlea r13, s; \"2357BD\"\njmp short loc_11C9\nloc_11B3:\nmovsx esi, byte ptr [rbx]; c\nmov rdi, r13; s\ncall _strchr\ncmp rax, 1\nsbb ebp, 0FFFFFFFFh\nadd rbx, 1\nloc_11C9:\ncmp rbx, r12\njnz short loc_11B3\nmov eax, ebp\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(const char *a1)\n{\n const char *v1; // rbx\n char *v2; // r12\n unsigned int v3; // ebp\n\n v1 = a1;\n v2 = (char *)&a1[strlen(a1)];\n v3 = 0;\n while ( v1 != v2 )\n v3 -= (strchr(\"2357BD\", *v1++) == 0LL) - 1;\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(const char *a1) {\n const char *v1;\n char *v2;\n unsigned int v3;\n v1 = a1;\n v2 = (char *)&a1[strlen(a1)];\n v3 = 0;\n while (v1 != v2) v3 -= (strchr(\"2357BD\", *v1++) == 0LL) - 1;\n return v3;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n const char *v1;\n char *v2;\n unsigned int v3;\n v1 = a1;\n v2 = (char *)&a1[strlen(a1)];\n v3 = 0;\n while (v1 != v2) v3 -= (strchr(\"2357BD\", *v1++) == 0LL) - 1;\n return v3;\n}" + }, + { + "index": "HumanEval-C-78", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(const char* num) {\n const char* key = \"2357BD\";\n int out = 0;\n for (int i = 0; i < strlen(num); i++) {\n if (strchr(key, num[i])) out += 1;\n }\n return out;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"AB\") == 1);\n assert(func0(\"1077E\") == 2);\n assert(func0(\"ABED1A33\") == 4);\n assert(func0(\"2020\") == 2);\n assert(func0(\"123456789ABCDEF0\") == 6);\n assert(func0(\"112233445566778899AABBCCDDEEFF00\") == 12);\n assert(func0(\"\") == 0);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\ntest rax, rax\njz short loc_1360\nlea r12, [rbx+rax]\nxor ebp, ebp\nlea r13, s; \"2357BD\"\nnop dword ptr [rax+rax+00000000h]\nloc_1330:\nmovsx esi, byte ptr [rbx]; c\nmov rdi, r13; s\ncall _strchr\ncmp rax, 1\nsbb ebp, 0FFFFFFFFh\nadd rbx, 1\ncmp rbx, r12\njnz short loc_1330\nadd rsp, 8\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1360:\nadd rsp, 8\nxor ebp, ebp\npop rbx\nmov eax, ebp\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n const char *v1; // rbx\n size_t v2; // rax\n char *v3; // r12\n unsigned int v4; // ebp\n\n v1 = a1;\n v2 = strlen(a1);\n if ( !v2 )\n return 0LL;\n v3 = (char *)&a1[v2];\n v4 = 0;\n do\n v4 -= (strchr(\"2357BD\", *v1++) == 0LL) - 1;\n while ( v1 != v3 );\n return v4;\n}", + "ida_strip_asm": "sub_1300:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\ntest rax, rax\njz short loc_1360\nlea r12, [rbx+rax]\nxor ebp, ebp\nlea r13, s; \"2357BD\"\nnop dword ptr [rax+rax+00000000h]\nloc_1330:\nmovsx esi, byte ptr [rbx]; c\nmov rdi, r13; s\ncall _strchr\ncmp rax, 1\nsbb ebp, 0FFFFFFFFh\nadd rbx, 1\ncmp rbx, r12\njnz short loc_1330\nadd rsp, 8\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1360:\nadd rsp, 8\nxor ebp, ebp\npop rbx\nmov eax, ebp\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1300(const char *a1)\n{\n const char *v1; // rbx\n size_t v2; // rax\n char *v3; // r12\n unsigned int v4; // ebp\n\n v1 = a1;\n v2 = strlen(a1);\n if ( !v2 )\n return 0LL;\n v3 = (char *)&a1[v2];\n v4 = 0;\n do\n v4 -= (strchr(\"2357BD\", *v1++) == 0LL) - 1;\n while ( v1 != v3 );\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1300(const char *a1) {\n const char *v1;\n unsigned int v2;\n char *v3;\n unsigned int v4;\n v1 = a1;\n v2 = strlen(a1);\n if (!v2) return 0LL;\n v3 = (char *)&a1[v2];\n v4 = 0;\n do\n v4 -= (strchr(\"2357BD\", *v1++) == 0LL) - 1;\n while (v1 != v3);\n return v4;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n const char *v1;\n unsigned int v2;\n char *v3;\n unsigned int v4;\n v1 = a1;\n v2 = strlen(a1);\n if (!v2) return 0LL;\n v3 = (char *)&a1[v2];\n v4 = 0;\n do\n v4 -= (strchr(\"2357BD\", *v1++) == 0LL) - 1;\n while (v1 != v3);\n return v4;\n}" + }, + { + "index": "HumanEval-C-78", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(const char* num) {\n const char* key = \"2357BD\";\n int out = 0;\n for (int i = 0; i < strlen(num); i++) {\n if (strchr(key, num[i])) out += 1;\n }\n return out;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"AB\") == 1);\n assert(func0(\"1077E\") == 2);\n assert(func0(\"ABED1A33\") == 4);\n assert(func0(\"2020\") == 2);\n assert(func0(\"123456789ABCDEF0\") == 6);\n assert(func0(\"112233445566778899AABBCCDDEEFF00\") == 12);\n assert(func0(\"\") == 0);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\ntest rax, rax\njz short loc_1360\nlea r12, [rbx+rax]\nxor ebp, ebp\nlea r13, s; \"2357BD\"\nnop dword ptr [rax+rax+00000000h]\nloc_1330:\nmovsx esi, byte ptr [rbx]; c\nmov rdi, r13; s\ncall _strchr\ncmp rax, 1\nsbb ebp, 0FFFFFFFFh\nadd rbx, 1\ncmp rbx, r12\njnz short loc_1330\nadd rsp, 8\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1360:\nadd rsp, 8\nxor ebp, ebp\npop rbx\nmov eax, ebp\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n const char *v1; // rbx\n size_t v2; // rax\n char *v3; // r12\n unsigned int v4; // ebp\n\n v1 = a1;\n v2 = strlen(a1);\n if ( !v2 )\n return 0LL;\n v3 = (char *)&a1[v2];\n v4 = 0;\n do\n v4 -= (strchr(\"2357BD\", *v1++) == 0LL) - 1;\n while ( v1 != v3 );\n return v4;\n}", + "ida_strip_asm": "sub_1300:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\ntest rax, rax\njz short loc_1360\nlea r12, [rbx+rax]\nxor ebp, ebp\nlea r13, s; \"2357BD\"\nnop dword ptr [rax+rax+00000000h]\nloc_1330:\nmovsx esi, byte ptr [rbx]; c\nmov rdi, r13; s\ncall _strchr\ncmp rax, 1\nsbb ebp, 0FFFFFFFFh\nadd rbx, 1\ncmp rbx, r12\njnz short loc_1330\nadd rsp, 8\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1360:\nadd rsp, 8\nxor ebp, ebp\npop rbx\nmov eax, ebp\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1300(const char *a1)\n{\n const char *v1; // rbx\n size_t v2; // rax\n char *v3; // r12\n unsigned int v4; // ebp\n\n v1 = a1;\n v2 = strlen(a1);\n if ( !v2 )\n return 0LL;\n v3 = (char *)&a1[v2];\n v4 = 0;\n do\n v4 -= (strchr(\"2357BD\", *v1++) == 0LL) - 1;\n while ( v1 != v3 );\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1300(const char *a1) {\n const char *v1;\n unsigned int v2;\n char *v3;\n unsigned int v4;\n v1 = a1;\n v2 = strlen(a1);\n if (!v2) return 0LL;\n v3 = (char *)&a1[v2];\n v4 = 0;\n do\n v4 -= (strchr(\"2357BD\", *v1++) == 0LL) - 1;\n while (v1 != v3);\n return v4;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n const char *v1;\n unsigned int v2;\n char *v3;\n unsigned int v4;\n v1 = a1;\n v2 = strlen(a1);\n if (!v2) return 0LL;\n v3 = (char *)&a1[v2];\n v4 = 0;\n do\n v4 -= (strchr(\"2357BD\", *v1++) == 0LL) - 1;\n while (v1 != v3);\n return v4;\n}" + }, + { + "index": "HumanEval-C-79", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char* func0(int decimal) {\n char* out = malloc(64);\n if (!out) {\n return NULL;\n }\n int index = 62;\n out[63] = '\\0';\n if (decimal == 0) {\n out[index--] = '0';\n } else {\n while (decimal > 0) {\n out[index--] = '0' + (decimal % 2);\n decimal /= 2;\n }\n }\n out[index--] = 'b';\n out[index--] = 'd';\n int start = index + 1;\n int len = 62 - start;\n char* formatted_out = malloc(len + 3);\n if (!formatted_out) {\n free(out);\n return NULL;\n }\n strcpy(formatted_out, &out[start]);\n strcat(formatted_out, \"db\");\n free(out);\n return formatted_out;\n}", + "test": "#include \n#include \n\nint main() {\n char* binary;\n\n binary = func0(0);\n assert(strcmp(binary, \"db0db\") == 0);\n free(binary);\n\n binary = func0(32);\n assert(strcmp(binary, \"db100000db\") == 0);\n free(binary);\n\n binary = func0(103);\n assert(strcmp(binary, \"db1100111db\") == 0);\n free(binary);\n\n binary = func0(15);\n assert(strcmp(binary, \"db1111db\") == 0);\n free(binary);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_24], edi\nmov edi, 40h ; '@'; size\ncall _malloc\nmov [rbp+ptr], rax\ncmp [rbp+ptr], 0\njnz short loc_1217\nmov eax, 0\njmp locret_1343\nloc_1217:\nmov [rbp+var_1C], 3Eh ; '>'\nmov rax, [rbp+ptr]\nadd rax, 3Fh ; '?'\nmov byte ptr [rax], 0\ncmp [rbp+var_24], 0\njnz short loc_1284\nmov eax, [rbp+var_1C]\nlea edx, [rax-1]\nmov [rbp+var_1C], edx\nmovsxd rdx, eax\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov byte ptr [rax], 30h ; '0'\njmp short loc_128A\nloc_1247:\nmov edx, [rbp+var_24]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\nlea ecx, [rax+30h]\nmov eax, [rbp+var_1C]\nlea edx, [rax-1]\nmov [rbp+var_1C], edx\nmovsxd rdx, eax\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, ecx\nmov [rax], dl\nmov eax, [rbp+var_24]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_24], eax\nloc_1284:\ncmp [rbp+var_24], 0\njg short loc_1247\nloc_128A:\nmov eax, [rbp+var_1C]\nlea edx, [rax-1]\nmov [rbp+var_1C], edx\nmovsxd rdx, eax\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov byte ptr [rax], 62h ; 'b'\nmov eax, [rbp+var_1C]\nlea edx, [rax-1]\nmov [rbp+var_1C], edx\nmovsxd rdx, eax\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov byte ptr [rax], 64h ; 'd'\nmov eax, [rbp+var_1C]\nadd eax, 1\nmov [rbp+var_18], eax\nmov eax, 3Eh ; '>'\nsub eax, [rbp+var_18]\nmov [rbp+var_14], eax\nmov eax, [rbp+var_14]\nadd eax, 3\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+dest], rax\ncmp [rbp+dest], 0\njnz short loc_12F8\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov eax, 0\njmp short locret_1343\nloc_12F8:\nmov eax, [rbp+var_18]\nmovsxd rdx, eax\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\nmov rax, [rbp+dest]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+dest]\nadd rax, rdx\nmov word ptr [rax], 6264h\nmov byte ptr [rax+2], 0\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+dest]\nlocret_1343:\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(int a1)\n{\n int v2; // eax\n int v3; // [rsp+Ch] [rbp-24h]\n int v4; // [rsp+14h] [rbp-1Ch]\n int v5; // [rsp+18h] [rbp-18h]\n _BYTE *ptr; // [rsp+20h] [rbp-10h]\n char *dest; // [rsp+28h] [rbp-8h]\n\n v3 = a1;\n ptr = malloc(0x40uLL);\n if ( !ptr )\n return 0LL;\n v4 = 62;\n ptr[63] = 0;\n if ( a1 )\n {\n while ( v3 > 0 )\n {\n v2 = v4--;\n ptr[v2] = v3 % 2 + 48;\n v3 /= 2;\n }\n }\n else\n {\n v4 = 61;\n ptr[62] = 48;\n }\n ptr[v4] = 98;\n ptr[v4 - 1] = 100;\n v5 = v4 - 2 + 1;\n dest = (char *)malloc(62 - v5 + 3);\n if ( dest )\n {\n strcpy(dest, &ptr[v5]);\n strcpy(&dest[strlen(dest)], \"db\");\n free(ptr);\n return dest;\n }\n else\n {\n free(ptr);\n return 0LL;\n }\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_24], edi\nmov edi, 40h ; '@'; size\ncall _malloc\nmov [rbp+ptr], rax\ncmp [rbp+ptr], 0\njnz short loc_1217\nmov eax, 0\njmp locret_1343\nloc_1217:\nmov [rbp+var_1C], 3Eh ; '>'\nmov rax, [rbp+ptr]\nadd rax, 3Fh ; '?'\nmov byte ptr [rax], 0\ncmp [rbp+var_24], 0\njnz short loc_1284\nmov eax, [rbp+var_1C]\nlea edx, [rax-1]\nmov [rbp+var_1C], edx\nmovsxd rdx, eax\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov byte ptr [rax], 30h ; '0'\njmp short loc_128A\nloc_1247:\nmov edx, [rbp+var_24]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\nlea ecx, [rax+30h]\nmov eax, [rbp+var_1C]\nlea edx, [rax-1]\nmov [rbp+var_1C], edx\nmovsxd rdx, eax\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, ecx\nmov [rax], dl\nmov eax, [rbp+var_24]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_24], eax\nloc_1284:\ncmp [rbp+var_24], 0\njg short loc_1247\nloc_128A:\nmov eax, [rbp+var_1C]\nlea edx, [rax-1]\nmov [rbp+var_1C], edx\nmovsxd rdx, eax\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov byte ptr [rax], 62h ; 'b'\nmov eax, [rbp+var_1C]\nlea edx, [rax-1]\nmov [rbp+var_1C], edx\nmovsxd rdx, eax\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov byte ptr [rax], 64h ; 'd'\nmov eax, [rbp+var_1C]\nadd eax, 1\nmov [rbp+var_18], eax\nmov eax, 3Eh ; '>'\nsub eax, [rbp+var_18]\nmov [rbp+var_14], eax\nmov eax, [rbp+var_14]\nadd eax, 3\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+dest], rax\ncmp [rbp+dest], 0\njnz short loc_12F8\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov eax, 0\njmp short locret_1343\nloc_12F8:\nmov eax, [rbp+var_18]\nmovsxd rdx, eax\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\nmov rax, [rbp+dest]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+dest]\nadd rax, rdx\nmov word ptr [rax], 6264h\nmov byte ptr [rax+2], 0\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+dest]\nlocret_1343:\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11E9(int a1)\n{\n int v2; // eax\n int v3; // [rsp+Ch] [rbp-24h]\n int v4; // [rsp+14h] [rbp-1Ch]\n int v5; // [rsp+18h] [rbp-18h]\n _BYTE *ptr; // [rsp+20h] [rbp-10h]\n char *dest; // [rsp+28h] [rbp-8h]\n\n v3 = a1;\n ptr = malloc(0x40uLL);\n if ( !ptr )\n return 0LL;\n v4 = 62;\n ptr[63] = 0;\n if ( a1 )\n {\n while ( v3 > 0 )\n {\n v2 = v4--;\n ptr[v2] = v3 % 2 + 48;\n v3 /= 2;\n }\n }\n else\n {\n v4 = 61;\n ptr[62] = 48;\n }\n ptr[v4] = 98;\n ptr[v4 - 1] = 100;\n v5 = v4 - 2 + 1;\n dest = (char *)malloc(62 - v5 + 3);\n if ( dest )\n {\n strcpy(dest, &ptr[v5]);\n strcpy(&dest[strlen(dest)], \"db\");\n free(ptr);\n return dest;\n }\n else\n {\n free(ptr);\n return 0LL;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11E9(int a1) {\n int v2;\n int v3;\n int v4;\n int v5;\n uint8_t *ptr;\n char *dest;\n v3 = a1;\n ptr = malloc(64uLL);\n if (!ptr) return 0LL;\n v4 = 62;\n ptr[63] = 0;\n if (a1) {\n while (v3 > 0) {\n v2 = v4--;\n ptr[v2] = v3 % 2 + 48;\n v3 /= 2;\n }\n } else {\n v4 = 61;\n ptr[62] = 48;\n }\n ptr[v4] = 98;\n ptr[v4 - 1] = 100;\n v5 = v4 - 2 + 1;\n dest = (char *)malloc(62 - v5 + 3);\n if (dest) {\n strcpy(dest, &ptr[v5]);\n strcpy(&dest[strlen(dest)], \"db\");\n free(ptr);\n return dest;\n } else {\n free(ptr);\n return 0LL;\n }\n}", + "ida_pseudo_norm": "char *func0(int a1) {\n int v2;\n int v3;\n int v4;\n int v5;\n uint8_t *ptr;\n char *dest;\n v3 = a1;\n ptr = malloc(64uLL);\n if (!ptr) return 0LL;\n v4 = 62;\n ptr[63] = 0;\n if (a1) {\n while (v3 > 0) {\n v2 = v4--;\n ptr[v2] = v3 % 2 + 48;\n v3 /= 2;\n }\n } else {\n v4 = 61;\n ptr[62] = 48;\n }\n ptr[v4] = 98;\n ptr[v4 - 1] = 100;\n v5 = v4 - 2 + 1;\n dest = (char *)malloc(62 - v5 + 3);\n if (dest) {\n strcpy(dest, &ptr[v5]);\n strcpy(&dest[strlen(dest)], \"db\");\n free(ptr);\n return dest;\n } else {\n free(ptr);\n return 0LL;\n }\n}" + }, + { + "index": "HumanEval-C-79", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char* func0(int decimal) {\n char* out = malloc(64);\n if (!out) {\n return NULL;\n }\n int index = 62;\n out[63] = '\\0';\n if (decimal == 0) {\n out[index--] = '0';\n } else {\n while (decimal > 0) {\n out[index--] = '0' + (decimal % 2);\n decimal /= 2;\n }\n }\n out[index--] = 'b';\n out[index--] = 'd';\n int start = index + 1;\n int len = 62 - start;\n char* formatted_out = malloc(len + 3);\n if (!formatted_out) {\n free(out);\n return NULL;\n }\n strcpy(formatted_out, &out[start]);\n strcat(formatted_out, \"db\");\n free(out);\n return formatted_out;\n}", + "test": "#include \n#include \n\nint main() {\n char* binary;\n\n binary = func0(0);\n assert(strcmp(binary, \"db0db\") == 0);\n free(binary);\n\n binary = func0(32);\n assert(strcmp(binary, \"db100000db\") == 0);\n free(binary);\n\n binary = func0(103);\n assert(strcmp(binary, \"db1100111db\") == 0);\n free(binary);\n\n binary = func0(15);\n assert(strcmp(binary, \"db1111db\") == 0);\n free(binary);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov ebx, edi\nmov edi, 40h ; '@'; size\ncall _malloc\nmov rbp, rax\ntest rax, rax\njz loc_12CA\nmov byte ptr [rax+3Fh], 0\ntest ebx, ebx\njz short loc_1252\nmov edx, 3Dh ; '='\nmov eax, 3Eh ; '>'\njle short loc_125B\nloc_1223:\nmov ecx, ebx\nshr ecx, 1Fh\nlea eax, [rbx+rcx]\nand eax, 1\nsub eax, ecx\nadd eax, 30h ; '0'\nmov [rbp+rdx+1], al\nmov ecx, ebx\nmov eax, ebx\nshr eax, 1Fh\nadd eax, ebx\nsar eax, 1\nmov ebx, eax\nmov rax, rdx\nsub rdx, 1\ncmp ecx, 1\njg short loc_1223\njmp short loc_125B\nloc_1252:\nmov byte ptr [rax+3Eh], 30h ; '0'\nmov eax, 3Dh ; '='\nloc_125B:\nlea edx, [rax-1]\ncdqe\nmov byte ptr [rbp+rax+0], 62h ; 'b'\nmovsxd r13, edx\nadd r13, rbp\nmov byte ptr [r13+0], 64h ; 'd'\nmov ebx, 41h ; 'A'\nsub ebx, edx\nmovsxd rbx, ebx\nmov rdi, rbx; size\ncall _malloc\nmov r12, rax\ntest rax, rax\njz short loc_12C0\nmov rdx, rbx\nmov rsi, r13\nmov rdi, rax\ncall ___strcpy_chk\nmov rdx, rbx\nlea rsi, aDb100000db+8; \"db\"\nmov rdi, r12\ncall ___strcat_chk\nmov rdi, rbp; ptr\ncall _free\nloc_12B2:\nmov rax, r12\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_12C0:\nmov rdi, rbp; ptr\ncall _free\njmp short loc_12B2\nloc_12CA:\nmov r12, rax\njmp short loc_12B2", + "ida_pseudo": "void *__fastcall func0(int a1)\n{\n int v1; // ebx\n _BYTE *v2; // rax\n _BYTE *v3; // rbp\n __int64 v4; // rdx\n int v5; // eax\n int v6; // ecx\n _BYTE *v7; // r13\n size_t v8; // rbx\n void *v9; // rax\n void *v10; // r12\n\n v1 = a1;\n v2 = malloc(0x40uLL);\n v3 = v2;\n if ( !v2 )\n return 0LL;\n v2[63] = 0;\n if ( a1 )\n {\n v4 = 61LL;\n v5 = 62;\n if ( a1 > 0 )\n {\n do\n {\n v3[v4 + 1] = v1 % 2 + 48;\n v6 = v1;\n v1 /= 2;\n v5 = v4--;\n }\n while ( v6 > 1 );\n }\n }\n else\n {\n v2[62] = 48;\n v5 = 61;\n }\n v3[v5] = 98;\n v7 = &v3[v5 - 1];\n *v7 = 100;\n v8 = 65 - (v5 - 1);\n v9 = malloc(v8);\n v10 = v9;\n if ( v9 )\n {\n __strcpy_chk(v9, v7, v8);\n __strcat_chk(v10, \"db\", v8);\n }\n free(v3);\n return v10;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov ebx, edi\nmov edi, 40h ; '@'; size\ncall _malloc\nmov rbp, rax\ntest rax, rax\njz loc_12CA\nmov byte ptr [rax+3Fh], 0\ntest ebx, ebx\njz short loc_1252\nmov edx, 3Dh ; '='\nmov eax, 3Eh ; '>'\njle short loc_125B\nloc_1223:\nmov ecx, ebx\nshr ecx, 1Fh\nlea eax, [rbx+rcx]\nand eax, 1\nsub eax, ecx\nadd eax, 30h ; '0'\nmov [rbp+rdx+1], al\nmov ecx, ebx\nmov eax, ebx\nshr eax, 1Fh\nadd eax, ebx\nsar eax, 1\nmov ebx, eax\nmov rax, rdx\nsub rdx, 1\ncmp ecx, 1\njg short loc_1223\njmp short loc_125B\nloc_1252:\nmov byte ptr [rax+3Eh], 30h ; '0'\nmov eax, 3Dh ; '='\nloc_125B:\nlea edx, [rax-1]\ncdqe\nmov byte ptr [rbp+rax+0], 62h ; 'b'\nmovsxd r13, edx\nadd r13, rbp\nmov byte ptr [r13+0], 64h ; 'd'\nmov ebx, 41h ; 'A'\nsub ebx, edx\nmovsxd rbx, ebx\nmov rdi, rbx; size\ncall _malloc\nmov r12, rax\ntest rax, rax\njz short loc_12C0\nmov rdx, rbx\nmov rsi, r13\nmov rdi, rax\ncall ___strcpy_chk\nmov rdx, rbx\nlea rsi, aDb100000db+8; \"db\"\nmov rdi, r12\ncall ___strcat_chk\nmov rdi, rbp; ptr\ncall _free\nloc_12B2:\nmov rax, r12\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_12C0:\nmov rdi, rbp; ptr\ncall _free\njmp short loc_12B2\nloc_12CA:\nmov r12, rax\njmp short loc_12B2", + "ida_strip_pseudo": "void *__fastcall sub_11E9(int a1)\n{\n int v1; // ebx\n _BYTE *v2; // rax\n _BYTE *v3; // rbp\n __int64 v4; // rdx\n int v5; // eax\n int v6; // ecx\n _BYTE *v7; // r13\n size_t v8; // rbx\n void *v9; // rax\n void *v10; // r12\n\n v1 = a1;\n v2 = malloc(0x40uLL);\n v3 = v2;\n if ( !v2 )\n return 0LL;\n v2[63] = 0;\n if ( a1 )\n {\n v4 = 61LL;\n v5 = 62;\n if ( a1 > 0 )\n {\n do\n {\n v3[v4 + 1] = v1 % 2 + 48;\n v6 = v1;\n v1 /= 2;\n v5 = v4--;\n }\n while ( v6 > 1 );\n }\n }\n else\n {\n v2[62] = 48;\n v5 = 61;\n }\n v3[v5] = 98;\n v7 = &v3[v5 - 1];\n *v7 = 100;\n v8 = 65 - (v5 - 1);\n v9 = malloc(v8);\n v10 = v9;\n if ( v9 )\n {\n __strcpy_chk(v9, v7, v8);\n __strcat_chk(v10, \"db\", v8);\n }\n free(v3);\n return v10;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_11E9(int a1) {\n int v1;\n uint8_t *v2;\n uint8_t *v3;\n long long v4;\n int v5;\n int v6;\n uint8_t *v7;\n unsigned int v8;\n void *v9;\n void *v10;\n v1 = a1;\n v2 = malloc(64uLL);\n v3 = v2;\n if (!v2) return 0LL;\n v2[63] = 0;\n if (a1) {\n v4 = 61LL;\n v5 = 62;\n if (a1 > 0) {\n do {\n v3[v4 + 1] = v1 % 2 + 48;\n v6 = v1;\n v1 /= 2;\n v5 = v4--;\n } while (v6 > 1);\n }\n } else {\n v2[62] = 48;\n v5 = 61;\n }\n v3[v5] = 98;\n v7 = &v3[v5 - 1];\n *v7 = 100;\n v8 = 65 - (v5 - 1);\n v9 = malloc(v8);\n v10 = v9;\n if (v9) {\n __strcpy_chk(v9, v7, v8);\n __strcat_chk(v10, \"db\", v8);\n }\n free(v3);\n return v10;\n}", + "ida_pseudo_norm": "void *func0(int a1) {\n int v1;\n uint8_t *v2;\n uint8_t *v3;\n long long v4;\n int v5;\n int v6;\n uint8_t *v7;\n unsigned int v8;\n void *v9;\n void *v10;\n v1 = a1;\n v2 = malloc(64uLL);\n v3 = v2;\n if (!v2) return 0LL;\n v2[63] = 0;\n if (a1) {\n v4 = 61LL;\n v5 = 62;\n if (a1 > 0) {\n do {\n v3[v4 + 1] = v1 % 2 + 48;\n v6 = v1;\n v1 /= 2;\n v5 = v4--;\n } while (v6 > 1);\n }\n } else {\n v2[62] = 48;\n v5 = 61;\n }\n v3[v5] = 98;\n v7 = &v3[v5 - 1];\n *v7 = 100;\n v8 = 65 - (v5 - 1);\n v9 = malloc(v8);\n v10 = v9;\n if (v9) {\n __strcpy_chk(v9, v7, v8);\n __strcat_chk(v10, \"db\", v8);\n }\n free(v3);\n return v10;\n}" + }, + { + "index": "HumanEval-C-79", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char* func0(int decimal) {\n char* out = malloc(64);\n if (!out) {\n return NULL;\n }\n int index = 62;\n out[63] = '\\0';\n if (decimal == 0) {\n out[index--] = '0';\n } else {\n while (decimal > 0) {\n out[index--] = '0' + (decimal % 2);\n decimal /= 2;\n }\n }\n out[index--] = 'b';\n out[index--] = 'd';\n int start = index + 1;\n int len = 62 - start;\n char* formatted_out = malloc(len + 3);\n if (!formatted_out) {\n free(out);\n return NULL;\n }\n strcpy(formatted_out, &out[start]);\n strcat(formatted_out, \"db\");\n free(out);\n return formatted_out;\n}", + "test": "#include \n#include \n\nint main() {\n char* binary;\n\n binary = func0(0);\n assert(strcmp(binary, \"db0db\") == 0);\n free(binary);\n\n binary = func0(32);\n assert(strcmp(binary, \"db100000db\") == 0);\n free(binary);\n\n binary = func0(103);\n assert(strcmp(binary, \"db1100111db\") == 0);\n free(binary);\n\n binary = func0(15);\n assert(strcmp(binary, \"db1111db\") == 0);\n free(binary);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nmov ebx, edi\nmov edi, 40h ; '@'; size\nsub rsp, 8\ncall _malloc\ntest rax, rax\njz loc_1426\nmov byte ptr [rax+3Fh], 0\nmov rbp, rax\ntest ebx, ebx\njnz short loc_13C8\nmov byte ptr [rax+3Eh], 30h ; '0'\nmov r12d, 5\nmov r13d, 3Ch ; '<'\nmov eax, 3Dh ; '='\nloc_1363:\nadd r13, rbp\nmov byte ptr [rbp+rax+0], 62h ; 'b'\nmov rdi, r12; size\nmov byte ptr [r13+0], 64h ; 'd'\ncall _malloc\nmov rbx, rax\ntest rax, rax\njz loc_141E\nmov rdx, r12\nmov rsi, r13\nmov rdi, rax\ncall ___stpcpy_chk\nmov rcx, rbx\nmov edx, 3\nlea rsi, aDb100000db+8; \"db\"\nsub rcx, rax\nmov rdi, rax\nadd rcx, r12\ncall ___memcpy_chk\nmov rdi, rbp; ptr\ncall _free\nloc_13B7:\nadd rsp, 8\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_13C8:\nmov eax, 3Dh ; '='\njle short loc_1408\nnop\nloc_13D0:\nmov edx, ebx\nand edx, 1\nadd edx, 30h ; '0'\nmov [rbp+rax+1], dl\nmov rdx, rax\nsub rax, 1\nsar ebx, 1\njnz short loc_13D0\nmovsxd rax, edx\nmov r12d, 41h ; 'A'\nsub edx, 1\nsub r12d, edx\nmovsxd r13, edx\nmovsxd r12, r12d\njmp loc_1363\nloc_1408:\nmov r12d, 4\nmov r13d, 3Dh ; '='\nmov eax, 3Eh ; '>'\njmp loc_1363\nloc_141E:\nmov rdi, rbp; ptr\ncall _free\nloc_1426:\nxor ebx, ebx\njmp short loc_13B7", + "ida_pseudo": "char *__fastcall func0(int a1)\n{\n int v1; // ebx\n _BYTE *v2; // rax\n _BYTE *v3; // rbp\n size_t v4; // r12\n __int64 v5; // r13\n __int64 v6; // rax\n _BYTE *v7; // r13\n char *v8; // rax\n char *v9; // rbx\n __int64 v10; // rax\n __int64 v12; // rax\n int v13; // edx\n int v14; // edx\n\n v1 = a1;\n v2 = malloc(0x40uLL);\n if ( !v2 )\n return 0LL;\n v2[63] = 0;\n v3 = v2;\n if ( a1 )\n {\n v12 = 61LL;\n if ( a1 <= 0 )\n {\n v4 = 4LL;\n v5 = 61LL;\n v6 = 62LL;\n }\n else\n {\n do\n {\n v3[v12 + 1] = (v1 & 1) + 48;\n v13 = v12--;\n v1 >>= 1;\n }\n while ( v1 );\n v6 = v13;\n v14 = v13 - 1;\n v5 = v14;\n v4 = 65 - v14;\n }\n }\n else\n {\n v2[62] = 48;\n v4 = 5LL;\n v5 = 60LL;\n v6 = 61LL;\n }\n v7 = &v3[v5];\n v3[v6] = 98;\n *v7 = 100;\n v8 = (char *)malloc(v4);\n v9 = v8;\n if ( !v8 )\n {\n free(v3);\n return 0LL;\n }\n v10 = __stpcpy_chk(v8, v7, v4);\n __memcpy_chk(v10, \"db\", 3LL, &v9[v4 - v10]);\n free(v3);\n return v9;\n}", + "ida_strip_asm": "sub_1320:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nmov ebx, edi\nmov edi, 40h ; '@'; size\nsub rsp, 8\ncall _malloc\ntest rax, rax\njz loc_1426\nmov byte ptr [rax+3Fh], 0\nmov rbp, rax\ntest ebx, ebx\njnz short loc_13C8\nmov byte ptr [rax+3Eh], 30h ; '0'\nmov r12d, 5\nmov r13d, 3Ch ; '<'\nmov eax, 3Dh ; '='\nloc_1363:\nadd r13, rbp\nmov byte ptr [rbp+rax+0], 62h ; 'b'\nmov rdi, r12; size\nmov byte ptr [r13+0], 64h ; 'd'\ncall _malloc\nmov rbx, rax\ntest rax, rax\njz loc_141E\nmov rdx, r12\nmov rsi, r13\nmov rdi, rax\ncall ___stpcpy_chk\nmov rcx, rbx\nmov edx, 3\nlea rsi, aDb100000db+8; \"db\"\nsub rcx, rax\nmov rdi, rax\nadd rcx, r12\ncall ___memcpy_chk\nmov rdi, rbp; ptr\ncall _free\nloc_13B7:\nadd rsp, 8\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_13C8:\nmov eax, 3Dh ; '='\njle short loc_1408\nnop\nloc_13D0:\nmov edx, ebx\nand edx, 1\nadd edx, 30h ; '0'\nmov [rbp+rax+1], dl\nmov rdx, rax\nsub rax, 1\nsar ebx, 1\njnz short loc_13D0\nmovsxd rax, edx\nmov r12d, 41h ; 'A'\nsub edx, 1\nsub r12d, edx\nmovsxd r13, edx\nmovsxd r12, r12d\njmp loc_1363\nloc_1408:\nmov r12d, 4\nmov r13d, 3Dh ; '='\nmov eax, 3Eh ; '>'\njmp loc_1363\nloc_141E:\nmov rdi, rbp; ptr\ncall _free\nloc_1426:\nxor ebx, ebx\njmp short loc_13B7", + "ida_strip_pseudo": "char *__fastcall sub_1320(int a1)\n{\n int v1; // ebx\n _BYTE *v2; // rax\n _BYTE *v3; // rbp\n size_t v4; // r12\n __int64 v5; // r13\n __int64 v6; // rax\n _BYTE *v7; // r13\n char *v8; // rax\n char *v9; // rbx\n __int64 v10; // rax\n __int64 v12; // rax\n int v13; // edx\n int v14; // edx\n\n v1 = a1;\n v2 = malloc(0x40uLL);\n if ( !v2 )\n return 0LL;\n v2[63] = 0;\n v3 = v2;\n if ( a1 )\n {\n v12 = 61LL;\n if ( a1 <= 0 )\n {\n v4 = 4LL;\n v5 = 61LL;\n v6 = 62LL;\n }\n else\n {\n do\n {\n v3[v12 + 1] = (v1 & 1) + 48;\n v13 = v12--;\n v1 >>= 1;\n }\n while ( v1 );\n v6 = v13;\n v14 = v13 - 1;\n v5 = v14;\n v4 = 65 - v14;\n }\n }\n else\n {\n v2[62] = 48;\n v4 = 5LL;\n v5 = 60LL;\n v6 = 61LL;\n }\n v7 = &v3[v5];\n v3[v6] = 98;\n *v7 = 100;\n v8 = (char *)malloc(v4);\n v9 = v8;\n if ( !v8 )\n {\n free(v3);\n return 0LL;\n }\n v10 = __stpcpy_chk(v8, v7, v4);\n __memcpy_chk(v10, \"db\", 3LL, &v9[v4 - v10]);\n free(v3);\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1320(int a1) {\n int v1;\n uint8_t *v2;\n uint8_t *v3;\n unsigned int v4;\n long long v5;\n long long v6;\n uint8_t *v7;\n char *v8;\n char *v9;\n long long v10;\n long long v12;\n int v13;\n int v14;\n v1 = a1;\n v2 = malloc(64uLL);\n if (!v2) return 0LL;\n v2[63] = 0;\n v3 = v2;\n if (a1) {\n v12 = 61LL;\n if (a1 <= 0) {\n v4 = 4LL;\n v5 = 61LL;\n v6 = 62LL;\n } else {\n do {\n v3[v12 + 1] = (v1 & 1) + 48;\n v13 = v12--;\n v1 >>= 1;\n } while (v1);\n v6 = v13;\n v14 = v13 - 1;\n v5 = v14;\n v4 = 65 - v14;\n }\n } else {\n v2[62] = 48;\n v4 = 5LL;\n v5 = 60LL;\n v6 = 61LL;\n }\n v7 = &v3[v5];\n v3[v6] = 98;\n *v7 = 100;\n v8 = (char *)malloc(v4);\n v9 = v8;\n if (!v8) {\n free(v3);\n return 0LL;\n }\n v10 = __stpcpy_chk(v8, v7, v4);\n __memcpy_chk(v10, \"db\", 3LL, &v9[v4 - v10]);\n free(v3);\n return v9;\n}", + "ida_pseudo_norm": "char *func0(int a1) {\n int v1;\n uint8_t *v2;\n uint8_t *v3;\n unsigned int v4;\n long long v5;\n long long v6;\n uint8_t *v7;\n char *v8;\n char *v9;\n long long v10;\n long long v12;\n int v13;\n int v14;\n v1 = a1;\n v2 = malloc(64uLL);\n if (!v2) return 0LL;\n v2[63] = 0;\n v3 = v2;\n if (a1) {\n v12 = 61LL;\n if (a1 <= 0) {\n v4 = 4LL;\n v5 = 61LL;\n v6 = 62LL;\n } else {\n do {\n v3[v12 + 1] = (v1 & 1) + 48;\n v13 = v12--;\n v1 >>= 1;\n } while (v1);\n v6 = v13;\n v14 = v13 - 1;\n v5 = v14;\n v4 = 65 - v14;\n }\n } else {\n v2[62] = 48;\n v4 = 5LL;\n v5 = 60LL;\n v6 = 61LL;\n }\n v7 = &v3[v5];\n v3[v6] = 98;\n *v7 = 100;\n v8 = (char *)malloc(v4);\n v9 = v8;\n if (!v8) {\n free(v3);\n return 0LL;\n }\n v10 = __stpcpy_chk(v8, v7, v4);\n __memcpy_chk(v10, \"db\", 3LL, &v9[v4 - v10]);\n free(v3);\n return v9;\n}" + }, + { + "index": "HumanEval-C-79", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char* func0(int decimal) {\n char* out = malloc(64);\n if (!out) {\n return NULL;\n }\n int index = 62;\n out[63] = '\\0';\n if (decimal == 0) {\n out[index--] = '0';\n } else {\n while (decimal > 0) {\n out[index--] = '0' + (decimal % 2);\n decimal /= 2;\n }\n }\n out[index--] = 'b';\n out[index--] = 'd';\n int start = index + 1;\n int len = 62 - start;\n char* formatted_out = malloc(len + 3);\n if (!formatted_out) {\n free(out);\n return NULL;\n }\n strcpy(formatted_out, &out[start]);\n strcat(formatted_out, \"db\");\n free(out);\n return formatted_out;\n}", + "test": "#include \n#include \n\nint main() {\n char* binary;\n\n binary = func0(0);\n assert(strcmp(binary, \"db0db\") == 0);\n free(binary);\n\n binary = func0(32);\n assert(strcmp(binary, \"db100000db\") == 0);\n free(binary);\n\n binary = func0(103);\n assert(strcmp(binary, \"db1100111db\") == 0);\n free(binary);\n\n binary = func0(15);\n assert(strcmp(binary, \"db1111db\") == 0);\n free(binary);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nmov ebx, edi\nmov edi, 40h ; '@'; size\nsub rsp, 8\ncall _malloc\ntest rax, rax\njz loc_1426\nmov byte ptr [rax+3Fh], 0\nmov rbp, rax\ntest ebx, ebx\njnz short loc_13C8\nmov byte ptr [rax+3Eh], 30h ; '0'\nmov r12d, 5\nmov r13d, 3Ch ; '<'\nmov eax, 3Dh ; '='\nloc_1363:\nadd r13, rbp\nmov byte ptr [rbp+rax+0], 62h ; 'b'\nmov rdi, r12; size\nmov byte ptr [r13+0], 64h ; 'd'\ncall _malloc\nmov rbx, rax\ntest rax, rax\njz loc_141E\nmov rdx, r12\nmov rsi, r13\nmov rdi, rax\ncall ___stpcpy_chk\nmov rcx, rbx\nmov edx, 3\nlea rsi, aDb100000db+8; \"db\"\nsub rcx, rax\nmov rdi, rax\nadd rcx, r12\ncall ___memcpy_chk\nmov rdi, rbp; ptr\ncall _free\nloc_13B7:\nadd rsp, 8\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_13C8:\nmov eax, 3Dh ; '='\njle short loc_1408\nnop\nloc_13D0:\nmov edx, ebx\nand edx, 1\nadd edx, 30h ; '0'\nmov [rbp+rax+1], dl\nmov rdx, rax\nsub rax, 1\nsar ebx, 1\njnz short loc_13D0\nmovsxd rax, edx\nmov r12d, 41h ; 'A'\nsub edx, 1\nsub r12d, edx\nmovsxd r13, edx\nmovsxd r12, r12d\njmp loc_1363\nloc_1408:\nmov r12d, 4\nmov r13d, 3Dh ; '='\nmov eax, 3Eh ; '>'\njmp loc_1363\nloc_141E:\nmov rdi, rbp; ptr\ncall _free\nloc_1426:\nxor ebx, ebx\njmp short loc_13B7", + "ida_pseudo": "char *__fastcall func0(int a1)\n{\n int v1; // ebx\n _BYTE *v2; // rax\n _BYTE *v3; // rbp\n size_t v4; // r12\n __int64 v5; // r13\n __int64 v6; // rax\n _BYTE *v7; // r13\n char *v8; // rax\n char *v9; // rbx\n __int64 v10; // rax\n __int64 v12; // rax\n int v13; // edx\n int v14; // edx\n\n v1 = a1;\n v2 = malloc(0x40uLL);\n if ( !v2 )\n return 0LL;\n v2[63] = 0;\n v3 = v2;\n if ( a1 )\n {\n v12 = 61LL;\n if ( a1 <= 0 )\n {\n v4 = 4LL;\n v5 = 61LL;\n v6 = 62LL;\n }\n else\n {\n do\n {\n v3[v12 + 1] = (v1 & 1) + 48;\n v13 = v12--;\n v1 >>= 1;\n }\n while ( v1 );\n v6 = v13;\n v14 = v13 - 1;\n v5 = v14;\n v4 = 65 - v14;\n }\n }\n else\n {\n v2[62] = 48;\n v4 = 5LL;\n v5 = 60LL;\n v6 = 61LL;\n }\n v7 = &v3[v5];\n v3[v6] = 98;\n *v7 = 100;\n v8 = (char *)malloc(v4);\n v9 = v8;\n if ( !v8 )\n {\n free(v3);\n return 0LL;\n }\n v10 = __stpcpy_chk(v8, v7, v4);\n __memcpy_chk(v10, \"db\", 3LL, &v9[v4 - v10]);\n free(v3);\n return v9;\n}", + "ida_strip_asm": "sub_1320:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nmov ebx, edi\nmov edi, 40h ; '@'; size\nsub rsp, 8\ncall _malloc\ntest rax, rax\njz loc_1426\nmov byte ptr [rax+3Fh], 0\nmov rbp, rax\ntest ebx, ebx\njnz short loc_13C8\nmov byte ptr [rax+3Eh], 30h ; '0'\nmov r12d, 5\nmov r13d, 3Ch ; '<'\nmov eax, 3Dh ; '='\nloc_1363:\nadd r13, rbp\nmov byte ptr [rbp+rax+0], 62h ; 'b'\nmov rdi, r12; size\nmov byte ptr [r13+0], 64h ; 'd'\ncall _malloc\nmov rbx, rax\ntest rax, rax\njz loc_141E\nmov rdx, r12\nmov rsi, r13\nmov rdi, rax\ncall ___stpcpy_chk\nmov rcx, rbx\nmov edx, 3\nlea rsi, aDb100000db+8; \"db\"\nsub rcx, rax\nmov rdi, rax\nadd rcx, r12\ncall ___memcpy_chk\nmov rdi, rbp; ptr\ncall _free\nloc_13B7:\nadd rsp, 8\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_13C8:\nmov eax, 3Dh ; '='\njle short loc_1408\nnop\nloc_13D0:\nmov edx, ebx\nand edx, 1\nadd edx, 30h ; '0'\nmov [rbp+rax+1], dl\nmov rdx, rax\nsub rax, 1\nsar ebx, 1\njnz short loc_13D0\nmovsxd rax, edx\nmov r12d, 41h ; 'A'\nsub edx, 1\nsub r12d, edx\nmovsxd r13, edx\nmovsxd r12, r12d\njmp loc_1363\nloc_1408:\nmov r12d, 4\nmov r13d, 3Dh ; '='\nmov eax, 3Eh ; '>'\njmp loc_1363\nloc_141E:\nmov rdi, rbp; ptr\ncall _free\nloc_1426:\nxor ebx, ebx\njmp short loc_13B7", + "ida_strip_pseudo": "char *__fastcall sub_1320(int a1)\n{\n int v1; // ebx\n _BYTE *v2; // rax\n _BYTE *v3; // rbp\n size_t v4; // r12\n __int64 v5; // r13\n __int64 v6; // rax\n _BYTE *v7; // r13\n char *v8; // rax\n char *v9; // rbx\n __int64 v10; // rax\n __int64 v12; // rax\n int v13; // edx\n int v14; // edx\n\n v1 = a1;\n v2 = malloc(0x40uLL);\n if ( !v2 )\n return 0LL;\n v2[63] = 0;\n v3 = v2;\n if ( a1 )\n {\n v12 = 61LL;\n if ( a1 <= 0 )\n {\n v4 = 4LL;\n v5 = 61LL;\n v6 = 62LL;\n }\n else\n {\n do\n {\n v3[v12 + 1] = (v1 & 1) + 48;\n v13 = v12--;\n v1 >>= 1;\n }\n while ( v1 );\n v6 = v13;\n v14 = v13 - 1;\n v5 = v14;\n v4 = 65 - v14;\n }\n }\n else\n {\n v2[62] = 48;\n v4 = 5LL;\n v5 = 60LL;\n v6 = 61LL;\n }\n v7 = &v3[v5];\n v3[v6] = 98;\n *v7 = 100;\n v8 = (char *)malloc(v4);\n v9 = v8;\n if ( !v8 )\n {\n free(v3);\n return 0LL;\n }\n v10 = __stpcpy_chk(v8, v7, v4);\n __memcpy_chk(v10, \"db\", 3LL, &v9[v4 - v10]);\n free(v3);\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1320(int a1) {\n int v1;\n uint8_t *v2;\n uint8_t *v3;\n unsigned int v4;\n long long v5;\n long long v6;\n uint8_t *v7;\n char *v8;\n char *v9;\n long long v10;\n long long v12;\n int v13;\n int v14;\n v1 = a1;\n v2 = malloc(64uLL);\n if (!v2) return 0LL;\n v2[63] = 0;\n v3 = v2;\n if (a1) {\n v12 = 61LL;\n if (a1 <= 0) {\n v4 = 4LL;\n v5 = 61LL;\n v6 = 62LL;\n } else {\n do {\n v3[v12 + 1] = (v1 & 1) + 48;\n v13 = v12--;\n v1 >>= 1;\n } while (v1);\n v6 = v13;\n v14 = v13 - 1;\n v5 = v14;\n v4 = 65 - v14;\n }\n } else {\n v2[62] = 48;\n v4 = 5LL;\n v5 = 60LL;\n v6 = 61LL;\n }\n v7 = &v3[v5];\n v3[v6] = 98;\n *v7 = 100;\n v8 = (char *)malloc(v4);\n v9 = v8;\n if (!v8) {\n free(v3);\n return 0LL;\n }\n v10 = __stpcpy_chk(v8, v7, v4);\n __memcpy_chk(v10, \"db\", 3LL, &v9[v4 - v10]);\n free(v3);\n return v9;\n}", + "ida_pseudo_norm": "char *func0(int a1) {\n int v1;\n uint8_t *v2;\n uint8_t *v3;\n unsigned int v4;\n long long v5;\n long long v6;\n uint8_t *v7;\n char *v8;\n char *v9;\n long long v10;\n long long v12;\n int v13;\n int v14;\n v1 = a1;\n v2 = malloc(64uLL);\n if (!v2) return 0LL;\n v2[63] = 0;\n v3 = v2;\n if (a1) {\n v12 = 61LL;\n if (a1 <= 0) {\n v4 = 4LL;\n v5 = 61LL;\n v6 = 62LL;\n } else {\n do {\n v3[v12 + 1] = (v1 & 1) + 48;\n v13 = v12--;\n v1 >>= 1;\n } while (v1);\n v6 = v13;\n v14 = v13 - 1;\n v5 = v14;\n v4 = 65 - v14;\n }\n } else {\n v2[62] = 48;\n v4 = 5LL;\n v5 = 60LL;\n v6 = 61LL;\n }\n v7 = &v3[v5];\n v3[v6] = 98;\n *v7 = 100;\n v8 = (char *)malloc(v4);\n v9 = v8;\n if (!v8) {\n free(v3);\n return 0LL;\n }\n v10 = __stpcpy_chk(v8, v7, v4);\n __memcpy_chk(v10, \"db\", 3LL, &v9[v4 - v10]);\n free(v3);\n return v9;\n}" + }, + { + "index": "HumanEval-C-80", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "bool func0(const char* s) {\n if (strlen(s) < 3) return false;\n for (int i = 2; i < strlen(s); i++)\n if (s[i] == s[i - 1] || s[i] == s[i - 2]) return false;\n return true;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"a\") == false);\n assert(func0(\"aa\") == false);\n assert(func0(\"abcd\") == true);\n assert(func0(\"aabb\") == false);\n assert(func0(\"adb\") == true);\n assert(func0(\"xyy\") == false);\n assert(func0(\"iopaxpoi\") == true);\n assert(func0(\"iopaxioi\") == false);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rax, 2\nja short loc_1193\nmov eax, 0\njmp short loc_1211\nloc_1193:\nmov [rbp+var_14], 2\njmp short loc_11F5\nloc_119C:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_14]\ncdqe\nlea rcx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njz short loc_11EA\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_14]\ncdqe\nlea rcx, [rax-2]\nmov rax, [rbp+s]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njnz short loc_11F1\nloc_11EA:\nmov eax, 0\njmp short loc_1211\nloc_11F1:\nadd [rbp+var_14], 1\nloc_11F5:\nmov eax, [rbp+var_14]\nmovsxd rbx, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rbx, rax\njb short loc_119C\nmov eax, 1\nloc_1211:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int i; // [rsp+1Ch] [rbp-14h]\n\n if ( strlen(a1) <= 2 )\n return 0LL;\n for ( i = 2; i < strlen(a1); ++i )\n {\n if ( a1[i] == a1[i - 1] || a1[i] == a1[i - 2] )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rax, 2\nja short loc_1193\nmov eax, 0\njmp short loc_1211\nloc_1193:\nmov [rbp+var_14], 2\njmp short loc_11F5\nloc_119C:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_14]\ncdqe\nlea rcx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njz short loc_11EA\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_14]\ncdqe\nlea rcx, [rax-2]\nmov rax, [rbp+s]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njnz short loc_11F1\nloc_11EA:\nmov eax, 0\njmp short loc_1211\nloc_11F1:\nadd [rbp+var_14], 1\nloc_11F5:\nmov eax, [rbp+var_14]\nmovsxd rbx, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rbx, rax\njb short loc_119C\nmov eax, 1\nloc_1211:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1)\n{\n int i; // [rsp+1Ch] [rbp-14h]\n\n if ( strlen(a1) <= 2 )\n return 0LL;\n for ( i = 2; i < strlen(a1); ++i )\n {\n if ( a1[i] == a1[i - 1] || a1[i] == a1[i - 2] )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1) {\n int i;\n if (strlen(a1) <= 2) return 0LL;\n for (i = 2; i < strlen(a1); ++i) {\n if (a1[i] == a1[i - 1] || a1[i] == a1[i - 2]) return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int i;\n if (strlen(a1) <= 2) return 0LL;\n for (i = 2; i < strlen(a1); ++i) {\n if (a1[i] == a1[i - 1] || a1[i] == a1[i - 2]) return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": "HumanEval-C-80", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "bool func0(const char* s) {\n if (strlen(s) < 3) return false;\n for (int i = 2; i < strlen(s); i++)\n if (s[i] == s[i - 1] || s[i] == s[i - 2]) return false;\n return true;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"a\") == false);\n assert(func0(\"aa\") == false);\n assert(func0(\"abcd\") == true);\n assert(func0(\"aabb\") == false);\n assert(func0(\"adb\") == true);\n assert(func0(\"xyy\") == false);\n assert(func0(\"iopaxpoi\") == true);\n assert(func0(\"iopaxioi\") == false);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmov edx, 0\ncmp rax, 2\njbe short loc_11AB\nmov rdx, rbx\nlea rcx, [rbx+rax-2]\nloc_1189:\nmovzx eax, byte ptr [rdx+2]\ncmp al, [rdx+1]\njz short loc_11A6\ncmp al, [rdx]\njz short loc_11AF\nadd rdx, 1\ncmp rdx, rcx\njnz short loc_1189\nmov edx, 1\njmp short loc_11AB\nloc_11A6:\nmov edx, 0\nloc_11AB:\nmov eax, edx\npop rbx\nretn\nloc_11AF:\nmov edx, 0\njmp short loc_11AB", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n size_t v1; // rax\n unsigned int v2; // edx\n const char *v3; // rdx\n __int64 v4; // rcx\n char v5; // al\n\n v1 = strlen(a1);\n v2 = 0;\n if ( v1 > 2 )\n {\n v3 = a1;\n v4 = (__int64)&a1[v1 - 2];\n while ( 1 )\n {\n v5 = v3[2];\n if ( v5 == v3[1] )\n return 0;\n if ( v5 == *v3 )\n break;\n if ( ++v3 == (const char *)v4 )\n return 1;\n }\n return 0;\n }\n return v2;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmov edx, 0\ncmp rax, 2\njbe short loc_11AB\nmov rdx, rbx\nlea rcx, [rbx+rax-2]\nloc_1189:\nmovzx eax, byte ptr [rdx+2]\ncmp al, [rdx+1]\njz short loc_11A6\ncmp al, [rdx]\njz short loc_11AF\nadd rdx, 1\ncmp rdx, rcx\njnz short loc_1189\nmov edx, 1\njmp short loc_11AB\nloc_11A6:\nmov edx, 0\nloc_11AB:\nmov eax, edx\npop rbx\nretn\nloc_11AF:\nmov edx, 0\njmp short loc_11AB", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1)\n{\n size_t v1; // rax\n unsigned int v2; // edx\n const char *v3; // rdx\n __int64 v4; // rcx\n char v5; // al\n\n v1 = strlen(a1);\n v2 = 0;\n if ( v1 > 2 )\n {\n v3 = a1;\n v4 = (__int64)&a1[v1 - 2];\n while ( 1 )\n {\n v5 = v3[2];\n if ( v5 == v3[1] )\n return 0;\n if ( v5 == *v3 )\n break;\n if ( ++v3 == (const char *)v4 )\n return 1;\n }\n return 0;\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1) {\n unsigned int v1;\n unsigned int v2;\n const char *v3;\n long long v4;\n char v5;\n v1 = strlen(a1);\n v2 = 0;\n if (v1 > 2) {\n v3 = a1;\n v4 = (long long)&a1[v1 - 2];\n while (1) {\n v5 = v3[2];\n if (v5 == v3[1]) return 0;\n if (v5 == *v3) break;\n if (++v3 == (const char *)v4) return 1;\n }\n return 0;\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n unsigned int v1;\n unsigned int v2;\n const char *v3;\n long long v4;\n char v5;\n v1 = strlen(a1);\n v2 = 0;\n if (v1 > 2) {\n v3 = a1;\n v4 = (long long)&a1[v1 - 2];\n while (1) {\n v5 = v3[2];\n if (v5 == v3[1]) return 0;\n if (v5 == *v3) break;\n if (++v3 == (const char *)v4) return 1;\n }\n return 0;\n }\n return v2;\n}" + }, + { + "index": "HumanEval-C-80", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "bool func0(const char* s) {\n if (strlen(s) < 3) return false;\n for (int i = 2; i < strlen(s); i++)\n if (s[i] == s[i - 1] || s[i] == s[i - 2]) return false;\n return true;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"a\") == false);\n assert(func0(\"aa\") == false);\n assert(func0(\"abcd\") == true);\n assert(func0(\"aabb\") == false);\n assert(func0(\"adb\") == true);\n assert(func0(\"xyy\") == false);\n assert(func0(\"iopaxpoi\") == true);\n assert(func0(\"iopaxioi\") == false);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nxor edx, edx\ncmp rax, 2\njbe short loc_1348\nmov rdi, rbx\nlea rdx, [rbx+rax-2]\njmp short loc_133D\nloc_1330:\ncmp al, [rdi]\njz short loc_1346\nadd rdi, 1\ncmp rdi, rdx\njz short loc_1350\nloc_133D:\nmovzx eax, byte ptr [rdi+2]\ncmp al, [rdi+1]\njnz short loc_1330\nloc_1346:\nxor edx, edx\nloc_1348:\nmov eax, edx\npop rbx\nretn\nloc_1350:\nmov edx, 1\npop rbx\nmov eax, edx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1)\n{\n size_t v1; // rax\n __int64 v2; // rdx\n char v3; // al\n\n v1 = strlen((const char *)a1);\n if ( v1 > 2 )\n {\n v2 = a1 + v1 - 2;\n while ( 1 )\n {\n v3 = *(_BYTE *)(a1 + 2);\n if ( v3 == *(_BYTE *)(a1 + 1) || v3 == *(_BYTE *)a1 )\n break;\n if ( ++a1 == v2 )\n return 1LL;\n }\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1310:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nxor edx, edx\ncmp rax, 2\njbe short loc_1348\nmov rdi, rbx\nlea rdx, [rbx+rax-2]\njmp short loc_133D\nloc_1330:\ncmp al, [rdi]\njz short loc_1346\nadd rdi, 1\ncmp rdi, rdx\njz short loc_1350\nloc_133D:\nmovzx eax, byte ptr [rdi+2]\ncmp al, [rdi+1]\njnz short loc_1330\nloc_1346:\nxor edx, edx\nloc_1348:\nmov eax, edx\npop rbx\nretn\nloc_1350:\nmov edx, 1\npop rbx\nmov eax, edx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1310(__int64 a1)\n{\n size_t v1; // rax\n __int64 v2; // rdx\n char v3; // al\n\n v1 = strlen((const char *)a1);\n if ( v1 > 2 )\n {\n v2 = a1 + v1 - 2;\n while ( 1 )\n {\n v3 = *(_BYTE *)(a1 + 2);\n if ( v3 == *(_BYTE *)(a1 + 1) || v3 == *(_BYTE *)a1 )\n break;\n if ( ++a1 == v2 )\n return 1LL;\n }\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1310(long long a1) {\n unsigned int v1;\n long long v2;\n char v3;\n v1 = strlen((const char *)a1);\n if (v1 > 2) {\n v2 = a1 + v1 - 2;\n while (1) {\n v3 = *(uint8_t *)(a1 + 2);\n if (v3 == *(uint8_t *)(a1 + 1) || v3 == *(uint8_t *)a1) break;\n if (++a1 == v2) return 1LL;\n }\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1) {\n unsigned int v1;\n long long v2;\n char v3;\n v1 = strlen((const char *)a1);\n if (v1 > 2) {\n v2 = a1 + v1 - 2;\n while (1) {\n v3 = *(uint8_t *)(a1 + 2);\n if (v3 == *(uint8_t *)(a1 + 1) || v3 == *(uint8_t *)a1) break;\n if (++a1 == v2) return 1LL;\n }\n }\n return 0LL;\n}" + }, + { + "index": "HumanEval-C-80", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "bool func0(const char* s) {\n if (strlen(s) < 3) return false;\n for (int i = 2; i < strlen(s); i++)\n if (s[i] == s[i - 1] || s[i] == s[i - 2]) return false;\n return true;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"a\") == false);\n assert(func0(\"aa\") == false);\n assert(func0(\"abcd\") == true);\n assert(func0(\"aabb\") == false);\n assert(func0(\"adb\") == true);\n assert(func0(\"xyy\") == false);\n assert(func0(\"iopaxpoi\") == true);\n assert(func0(\"iopaxioi\") == false);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nxor edx, edx\ncmp rax, 2\njbe short loc_1348\nmov rdi, rbx\nlea rdx, [rbx+rax-2]\njmp short loc_133D\nloc_1330:\ncmp al, [rdi]\njz short loc_1346\nadd rdi, 1\ncmp rdi, rdx\njz short loc_1350\nloc_133D:\nmovzx eax, byte ptr [rdi+2]\ncmp al, [rdi+1]\njnz short loc_1330\nloc_1346:\nxor edx, edx\nloc_1348:\nmov eax, edx\npop rbx\nretn\nloc_1350:\nmov edx, 1\npop rbx\nmov eax, edx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1)\n{\n size_t v1; // rax\n __int64 v2; // rdx\n char v3; // al\n\n v1 = strlen((const char *)a1);\n if ( v1 > 2 )\n {\n v2 = a1 + v1 - 2;\n while ( 1 )\n {\n v3 = *(_BYTE *)(a1 + 2);\n if ( v3 == *(_BYTE *)(a1 + 1) || v3 == *(_BYTE *)a1 )\n break;\n if ( ++a1 == v2 )\n return 1LL;\n }\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1310:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nxor edx, edx\ncmp rax, 2\njbe short loc_1348\nmov rdi, rbx\nlea rdx, [rbx+rax-2]\njmp short loc_133D\nloc_1330:\ncmp al, [rdi]\njz short loc_1346\nadd rdi, 1\ncmp rdi, rdx\njz short loc_1350\nloc_133D:\nmovzx eax, byte ptr [rdi+2]\ncmp al, [rdi+1]\njnz short loc_1330\nloc_1346:\nxor edx, edx\nloc_1348:\nmov eax, edx\npop rbx\nretn\nloc_1350:\nmov edx, 1\npop rbx\nmov eax, edx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1310(__int64 a1)\n{\n size_t v1; // rax\n __int64 v2; // rdx\n char v3; // al\n\n v1 = strlen((const char *)a1);\n if ( v1 > 2 )\n {\n v2 = a1 + v1 - 2;\n while ( 1 )\n {\n v3 = *(_BYTE *)(a1 + 2);\n if ( v3 == *(_BYTE *)(a1 + 1) || v3 == *(_BYTE *)a1 )\n break;\n if ( ++a1 == v2 )\n return 1LL;\n }\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1310(long long a1) {\n unsigned int v1;\n long long v2;\n char v3;\n v1 = strlen((const char *)a1);\n if (v1 > 2) {\n v2 = a1 + v1 - 2;\n while (1) {\n v3 = *(uint8_t *)(a1 + 2);\n if (v3 == *(uint8_t *)(a1 + 1) || v3 == *(uint8_t *)a1) break;\n if (++a1 == v2) return 1LL;\n }\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1) {\n unsigned int v1;\n long long v2;\n char v3;\n v1 = strlen((const char *)a1);\n if (v1 > 2) {\n v2 = a1 + v1 - 2;\n while (1) {\n v3 = *(uint8_t *)(a1 + 2);\n if (v3 == *(uint8_t *)(a1 + 1) || v3 == *(uint8_t *)a1) break;\n if (++a1 == v2) return 1LL;\n }\n }\n return 0LL;\n}" + }, + { + "index": "HumanEval-C-81", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "char** func0(float* grades, int size) {\n char** out = malloc(size * sizeof(char*));\n for (int i = 0; i < size; ++i) {\n if (grades[i] >= 3.9999)\n out[i] = \"A+\";\n else if (grades[i] > 3.7001)\n out[i] = \"A\";\n else if (grades[i] > 3.3001)\n out[i] = \"A-\";\n else if (grades[i] > 3.0001)\n out[i] = \"B+\";\n else if (grades[i] > 2.7001)\n out[i] = \"B\";\n else if (grades[i] > 2.3001)\n out[i] = \"B-\";\n else if (grades[i] > 2.0001)\n out[i] = \"C+\";\n else if (grades[i] > 1.7001)\n out[i] = \"C\";\n else if (grades[i] > 1.3001)\n out[i] = \"C-\";\n else if (grades[i] > 1.0001)\n out[i] = \"D+\";\n else if (grades[i] > 0.7001)\n out[i] = \"D\";\n else if (grades[i] > 0.0001)\n out[i] = \"D-\";\n else\n out[i] = \"E\";\n }\n return out;\n}", + "test": "#include \n#include \n#include \n\nbool issame(char** a, char** b, int size) {\n for (int i = 0; i < size; i++) {\n if (strcmp(a[i], b[i]) != 0) return false;\n }\n return true;\n}\n\nint main() {\n float grades1[] = {4.0, 3, 1.7, 2, 3.5};\n char* expected1[] = {\"A+\", \"B\", \"C-\", \"C\", \"A-\"};\n char** result1 = func0(grades1, 5);\n assert(issame(result1, expected1, 5));\n free(result1);\n\n float grades2[] = {1.2};\n char* expected2[] = {\"D+\"};\n char** result2 = func0(grades2, 1);\n assert(issame(result2, expected2, 1));\n free(result2);\n\n float grades3[] = {0.5};\n char* expected3[] = {\"D-\"};\n char** result3 = func0(grades3, 1);\n assert(issame(result3, expected3, 1));\n free(result3);\n\n float grades4[] = {0.0};\n char* expected4[] = {\"E\"};\n char** result4 = func0(grades4, 1);\n assert(issame(result4, expected4, 1));\n free(result4);\n\n float grades5[] = {1, 0.3, 1.5, 2.8, 3.3};\n char* expected5[] = {\"D\", \"D-\", \"C-\", \"B\", \"B+\"};\n char** result5 = func0(grades5, 5);\n assert(issame(result5, expected5, 5));\n free(result5);\n\n float grades6[] = {0, 0.7};\n char* expected6[] = {\"E\", \"D-\"};\n char** result6 = func0(grades6, 2);\n assert(issame(result6, expected6, 2));\n free(result6);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp loc_1585\nloc_11FD:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\ncvtss2sd xmm0, xmm0\ncomisd xmm0, cs:qword_2108\njb short loc_1246\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rdx\nlea rdx, unk_2008\nmov [rax], rdx\njmp loc_1581\nloc_1246:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\ncvtss2sd xmm0, xmm0\ncomisd xmm0, cs:qword_2110\njbe short loc_128F\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rdx\nlea rdx, unk_200B\nmov [rax], rdx\njmp loc_1581\nloc_128F:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\ncvtss2sd xmm0, xmm0\ncomisd xmm0, cs:qword_2118\njbe short loc_12D8\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rdx\nlea rdx, unk_200D\nmov [rax], rdx\njmp loc_1581\nloc_12D8:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\ncvtss2sd xmm0, xmm0\ncomisd xmm0, cs:qword_2120\njbe short loc_1321\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rdx\nlea rdx, unk_2010\nmov [rax], rdx\njmp loc_1581\nloc_1321:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\ncvtss2sd xmm0, xmm0\ncomisd xmm0, cs:qword_2128\njbe short loc_136A\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rdx\nlea rdx, unk_2013\nmov [rax], rdx\njmp loc_1581\nloc_136A:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\ncvtss2sd xmm0, xmm0\ncomisd xmm0, cs:qword_2130\njbe short loc_13B3\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rdx\nlea rdx, unk_2015\nmov [rax], rdx\njmp loc_1581\nloc_13B3:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\ncvtss2sd xmm0, xmm0\ncomisd xmm0, cs:qword_2138\njbe short loc_13FC\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rdx\nlea rdx, unk_2018\nmov [rax], rdx\njmp loc_1581\nloc_13FC:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\ncvtss2sd xmm0, xmm0\ncomisd xmm0, cs:qword_2140\njbe short loc_1445\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rdx\nlea rdx, unk_201B\nmov [rax], rdx\njmp loc_1581\nloc_1445:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\ncvtss2sd xmm0, xmm0\ncomisd xmm0, cs:qword_2148\njbe short loc_148E\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rdx\nlea rdx, unk_201D\nmov [rax], rdx\njmp loc_1581\nloc_148E:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\ncvtss2sd xmm0, xmm0\ncomisd xmm0, cs:qword_2150\njbe short loc_14D7\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rdx\nlea rdx, unk_2020\nmov [rax], rdx\njmp loc_1581\nloc_14D7:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\ncvtss2sd xmm0, xmm0\ncomisd xmm0, cs:qword_2158\njbe short loc_151D\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rdx\nlea rdx, unk_2023\nmov [rax], rdx\njmp short loc_1581\nloc_151D:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\ncvtss2sd xmm0, xmm0\ncomisd xmm0, cs:qword_2160\njbe short loc_1563\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rdx\nlea rdx, unk_2025\nmov [rax], rdx\njmp short loc_1581\nloc_1563:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rdx\nlea rdx, unk_2028\nmov [rax], rdx\nloc_1581:\nadd [rbp+var_C], 1\nloc_1585:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl loc_11FD\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+14h] [rbp-Ch]\n _QWORD *v4; // [rsp+18h] [rbp-8h]\n\n v4 = malloc(8LL * a2);\n for ( i = 0; i < a2; ++i )\n {\n if ( *(float *)(4LL * i + a1) < 3.9999 )\n {\n if ( *(float *)(4LL * i + a1) <= 3.7001 )\n {\n if ( *(float *)(4LL * i + a1) <= 3.3001 )\n {\n if ( *(float *)(4LL * i + a1) <= 3.0001 )\n {\n if ( *(float *)(4LL * i + a1) <= 2.7001 )\n {\n if ( *(float *)(4LL * i + a1) <= 2.3001 )\n {\n if ( *(float *)(4LL * i + a1) <= 2.0001 )\n {\n if ( *(float *)(4LL * i + a1) <= 1.7001 )\n {\n if ( *(float *)(4LL * i + a1) <= 1.3001 )\n {\n if ( *(float *)(4LL * i + a1) <= 1.0001 )\n {\n if ( *(float *)(4LL * i + a1) <= 0.7000999999999999 )\n {\n if ( *(float *)(4LL * i + a1) <= 0.0001 )\n v4[i] = &unk_2028;\n else\n v4[i] = &unk_2025;\n }\n else\n {\n v4[i] = &unk_2023;\n }\n }\n else\n {\n v4[i] = &unk_2020;\n }\n }\n else\n {\n v4[i] = &unk_201D;\n }\n }\n else\n {\n v4[i] = &unk_201B;\n }\n }\n else\n {\n v4[i] = &unk_2018;\n }\n }\n else\n {\n v4[i] = &unk_2015;\n }\n }\n else\n {\n v4[i] = &unk_2013;\n }\n }\n else\n {\n v4[i] = &unk_2010;\n }\n }\n else\n {\n v4[i] = &unk_200D;\n }\n }\n else\n {\n v4[i] = &unk_200B;\n }\n }\n else\n {\n v4[i] = &unk_2008;\n }\n }\n return v4;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp loc_1585\nloc_11FD:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\ncvtss2sd xmm0, xmm0\ncomisd xmm0, cs:qword_2108\njb short loc_1246\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rdx\nlea rdx, unk_2008\nmov [rax], rdx\njmp loc_1581\nloc_1246:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\ncvtss2sd xmm0, xmm0\ncomisd xmm0, cs:qword_2110\njbe short loc_128F\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rdx\nlea rdx, unk_200B\nmov [rax], rdx\njmp loc_1581\nloc_128F:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\ncvtss2sd xmm0, xmm0\ncomisd xmm0, cs:qword_2118\njbe short loc_12D8\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rdx\nlea rdx, unk_200D\nmov [rax], rdx\njmp loc_1581\nloc_12D8:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\ncvtss2sd xmm0, xmm0\ncomisd xmm0, cs:qword_2120\njbe short loc_1321\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rdx\nlea rdx, unk_2010\nmov [rax], rdx\njmp loc_1581\nloc_1321:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\ncvtss2sd xmm0, xmm0\ncomisd xmm0, cs:qword_2128\njbe short loc_136A\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rdx\nlea rdx, unk_2013\nmov [rax], rdx\njmp loc_1581\nloc_136A:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\ncvtss2sd xmm0, xmm0\ncomisd xmm0, cs:qword_2130\njbe short loc_13B3\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rdx\nlea rdx, unk_2015\nmov [rax], rdx\njmp loc_1581\nloc_13B3:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\ncvtss2sd xmm0, xmm0\ncomisd xmm0, cs:qword_2138\njbe short loc_13FC\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rdx\nlea rdx, unk_2018\nmov [rax], rdx\njmp loc_1581\nloc_13FC:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\ncvtss2sd xmm0, xmm0\ncomisd xmm0, cs:qword_2140\njbe short loc_1445\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rdx\nlea rdx, unk_201B\nmov [rax], rdx\njmp loc_1581\nloc_1445:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\ncvtss2sd xmm0, xmm0\ncomisd xmm0, cs:qword_2148\njbe short loc_148E\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rdx\nlea rdx, unk_201D\nmov [rax], rdx\njmp loc_1581\nloc_148E:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\ncvtss2sd xmm0, xmm0\ncomisd xmm0, cs:qword_2150\njbe short loc_14D7\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rdx\nlea rdx, unk_2020\nmov [rax], rdx\njmp loc_1581\nloc_14D7:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\ncvtss2sd xmm0, xmm0\ncomisd xmm0, cs:qword_2158\njbe short loc_151D\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rdx\nlea rdx, unk_2023\nmov [rax], rdx\njmp short loc_1581\nloc_151D:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\ncvtss2sd xmm0, xmm0\ncomisd xmm0, cs:qword_2160\njbe short loc_1563\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rdx\nlea rdx, unk_2025\nmov [rax], rdx\njmp short loc_1581\nloc_1563:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rdx\nlea rdx, unk_2028\nmov [rax], rdx\nloc_1581:\nadd [rbp+var_C], 1\nloc_1585:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl loc_11FD\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11C9(__int64 a1, int a2)\n{\n int i; // [rsp+14h] [rbp-Ch]\n _QWORD *v4; // [rsp+18h] [rbp-8h]\n\n v4 = malloc(8LL * a2);\n for ( i = 0; i < a2; ++i )\n {\n if ( *(float *)(4LL * i + a1) < 3.9999 )\n {\n if ( *(float *)(4LL * i + a1) <= 3.7001 )\n {\n if ( *(float *)(4LL * i + a1) <= 3.3001 )\n {\n if ( *(float *)(4LL * i + a1) <= 3.0001 )\n {\n if ( *(float *)(4LL * i + a1) <= 2.7001 )\n {\n if ( *(float *)(4LL * i + a1) <= 2.3001 )\n {\n if ( *(float *)(4LL * i + a1) <= 2.0001 )\n {\n if ( *(float *)(4LL * i + a1) <= 1.7001 )\n {\n if ( *(float *)(4LL * i + a1) <= 1.3001 )\n {\n if ( *(float *)(4LL * i + a1) <= 1.0001 )\n {\n if ( *(float *)(4LL * i + a1) <= 0.7000999999999999 )\n {\n if ( *(float *)(4LL * i + a1) <= 0.0001 )\n v4[i] = &unk_2028;\n else\n v4[i] = &unk_2025;\n }\n else\n {\n v4[i] = &unk_2023;\n }\n }\n else\n {\n v4[i] = &unk_2020;\n }\n }\n else\n {\n v4[i] = &unk_201D;\n }\n }\n else\n {\n v4[i] = &unk_201B;\n }\n }\n else\n {\n v4[i] = &unk_2018;\n }\n }\n else\n {\n v4[i] = &unk_2015;\n }\n }\n else\n {\n v4[i] = &unk_2013;\n }\n }\n else\n {\n v4[i] = &unk_2010;\n }\n }\n else\n {\n v4[i] = &unk_200D;\n }\n }\n else\n {\n v4[i] = &unk_200B;\n }\n }\n else\n {\n v4[i] = &unk_2008;\n }\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11C9(long long a1, int a2) {\n int i;\n uint64_t *v4;\n v4 = malloc(8LL * a2);\n for (i = 0; i < a2; ++i) {\n if (*(float *)(4LL * i + a1) < 3.9999) {\n if (*(float *)(4LL * i + a1) <= 3.7001) {\n if (*(float *)(4LL * i + a1) <= 3.3001) {\n if (*(float *)(4LL * i + a1) <= 3.0001) {\n if (*(float *)(4LL * i + a1) <= 2.7001) {\n if (*(float *)(4LL * i + a1) <= 2.3001) {\n if (*(float *)(4LL * i + a1) <= 2.0001) {\n if (*(float *)(4LL * i + a1) <= 1.7001) {\n if (*(float *)(4LL * i + a1) <= 1.3001) {\n if (*(float *)(4LL * i + a1) <= 1.0001) {\n if (*(float *)(4LL * i + a1) <= 0.7000999999999999) {\n if (*(float *)(4LL * i + a1) <= 0.0001)\n v4[i] = &unk_2028;\n else\n v4[i] = &unk_2025;\n } else {\n v4[i] = &unk_2023;\n }\n } else {\n v4[i] = &unk_2020;\n }\n } else {\n v4[i] = &unk_201D;\n }\n } else {\n v4[i] = &unk_201B;\n }\n } else {\n v4[i] = &unk_2018;\n }\n } else {\n v4[i] = &unk_2015;\n }\n } else {\n v4[i] = &unk_2013;\n }\n } else {\n v4[i] = &unk_2010;\n }\n } else {\n v4[i] = &unk_200D;\n }\n } else {\n v4[i] = &unk_200B;\n }\n } else {\n v4[i] = &unk_2008;\n }\n }\n return v4;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, int a2) {\n int i;\n uint64_t *v4;\n v4 = malloc(8LL * a2);\n for (i = 0; i < a2; ++i) {\n if (*(float *)(4LL * i + a1) < 3.9999) {\n if (*(float *)(4LL * i + a1) <= 3.7001) {\n if (*(float *)(4LL * i + a1) <= 3.3001) {\n if (*(float *)(4LL * i + a1) <= 3.0001) {\n if (*(float *)(4LL * i + a1) <= 2.7001) {\n if (*(float *)(4LL * i + a1) <= 2.3001) {\n if (*(float *)(4LL * i + a1) <= 2.0001) {\n if (*(float *)(4LL * i + a1) <= 1.7001) {\n if (*(float *)(4LL * i + a1) <= 1.3001) {\n if (*(float *)(4LL * i + a1) <= 1.0001) {\n if (*(float *)(4LL * i + a1) <= 0.7000999999999999) {\n if (*(float *)(4LL * i + a1) <= 0.0001)\n v4[i] = &unk_2028;\n else\n v4[i] = &unk_2025;\n } else {\n v4[i] = &unk_2023;\n }\n } else {\n v4[i] = &unk_2020;\n }\n } else {\n v4[i] = &unk_201D;\n }\n } else {\n v4[i] = &unk_201B;\n }\n } else {\n v4[i] = &unk_2018;\n }\n } else {\n v4[i] = &unk_2015;\n }\n } else {\n v4[i] = &unk_2013;\n }\n } else {\n v4[i] = &unk_2010;\n }\n } else {\n v4[i] = &unk_200D;\n }\n } else {\n v4[i] = &unk_200B;\n }\n } else {\n v4[i] = &unk_2008;\n }\n }\n return v4;\n}" + }, + { + "index": "HumanEval-C-81", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "char** func0(float* grades, int size) {\n char** out = malloc(size * sizeof(char*));\n for (int i = 0; i < size; ++i) {\n if (grades[i] >= 3.9999)\n out[i] = \"A+\";\n else if (grades[i] > 3.7001)\n out[i] = \"A\";\n else if (grades[i] > 3.3001)\n out[i] = \"A-\";\n else if (grades[i] > 3.0001)\n out[i] = \"B+\";\n else if (grades[i] > 2.7001)\n out[i] = \"B\";\n else if (grades[i] > 2.3001)\n out[i] = \"B-\";\n else if (grades[i] > 2.0001)\n out[i] = \"C+\";\n else if (grades[i] > 1.7001)\n out[i] = \"C\";\n else if (grades[i] > 1.3001)\n out[i] = \"C-\";\n else if (grades[i] > 1.0001)\n out[i] = \"D+\";\n else if (grades[i] > 0.7001)\n out[i] = \"D\";\n else if (grades[i] > 0.0001)\n out[i] = \"D-\";\n else\n out[i] = \"E\";\n }\n return out;\n}", + "test": "#include \n#include \n#include \n\nbool issame(char** a, char** b, int size) {\n for (int i = 0; i < size; i++) {\n if (strcmp(a[i], b[i]) != 0) return false;\n }\n return true;\n}\n\nint main() {\n float grades1[] = {4.0, 3, 1.7, 2, 3.5};\n char* expected1[] = {\"A+\", \"B\", \"C-\", \"C\", \"A-\"};\n char** result1 = func0(grades1, 5);\n assert(issame(result1, expected1, 5));\n free(result1);\n\n float grades2[] = {1.2};\n char* expected2[] = {\"D+\"};\n char** result2 = func0(grades2, 1);\n assert(issame(result2, expected2, 1));\n free(result2);\n\n float grades3[] = {0.5};\n char* expected3[] = {\"D-\"};\n char** result3 = func0(grades3, 1);\n assert(issame(result3, expected3, 1));\n free(result3);\n\n float grades4[] = {0.0};\n char* expected4[] = {\"E\"};\n char** result4 = func0(grades4, 1);\n assert(issame(result4, expected4, 1));\n free(result4);\n\n float grades5[] = {1, 0.3, 1.5, 2.8, 3.3};\n char* expected5[] = {\"D\", \"D-\", \"C-\", \"B\", \"B+\"};\n char** result5 = func0(grades5, 5);\n assert(issame(result5, expected5, 5));\n free(result5);\n\n float grades6[] = {0, 0.7};\n char* expected6[] = {\"E\", \"D-\"};\n char** result6 = func0(grades6, 2);\n assert(issame(result6, expected6, 2));\n free(result6);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nmov r12d, esi\nmovsxd rsi, esi\nlea rbp, ds:0[rsi*8]\nmov rdi, rbp; size\ncall _malloc\ntest r12d, r12d\njle loc_134C\nmov rcx, rbx\nmov rdx, rax\nlea rsi, [rbp+rax+0]\nmovsd xmm1, cs:qword_2108\nmovsd xmm2, cs:qword_2110\nmovsd xmm3, cs:qword_2118\nlea r9, unk_2009\nlea r8, unk_2007\nlea rdi, unk_2004\njmp short loc_1247\nloc_122D:\ncomisd xmm0, xmm2\njbe short loc_125A\nmov [rdx], r8\nloc_1236:\nadd rcx, 4\nadd rdx, 8\ncmp rdx, rsi\njz loc_134C\nloc_1247:\npxor xmm0, xmm0\ncvtss2sd xmm0, dword ptr [rcx]\ncomisd xmm0, xmm1\njb short loc_122D\nmov [rdx], rdi\njmp short loc_1236\nloc_125A:\ncomisd xmm0, xmm3\njbe short loc_1265\nmov [rdx], r9\njmp short loc_1236\nloc_1265:\ncomisd xmm0, cs:qword_2120\njbe short loc_127B\nlea rbx, unk_200C\nmov [rdx], rbx\njmp short loc_1236\nloc_127B:\ncomisd xmm0, cs:qword_2128\njbe short loc_1291\nlea rbx, unk_200F\nmov [rdx], rbx\njmp short loc_1236\nloc_1291:\ncomisd xmm0, cs:qword_2130\njbe short loc_12A7\nlea rbx, unk_2011\nmov [rdx], rbx\njmp short loc_1236\nloc_12A7:\ncomisd xmm0, cs:qword_2138\njbe short loc_12C0\nlea rbx, unk_2014\nmov [rdx], rbx\njmp loc_1236\nloc_12C0:\ncomisd xmm0, cs:qword_2140\njbe short loc_12D9\nlea rbx, unk_2017\nmov [rdx], rbx\njmp loc_1236\nloc_12D9:\ncomisd xmm0, cs:qword_2148\njbe short loc_12F2\nlea rbx, unk_2019\nmov [rdx], rbx\njmp loc_1236\nloc_12F2:\ncomisd xmm0, cs:qword_2150\njbe short loc_130B\nlea rbx, unk_201C\nmov [rdx], rbx\njmp loc_1236\nloc_130B:\ncomisd xmm0, cs:qword_2158\njbe short loc_1324\nlea rbx, unk_201F\nmov [rdx], rbx\njmp loc_1236\nloc_1324:\ncomisd xmm0, cs:qword_2160\njbe short loc_133D\nlea rbx, unk_2021\nmov [rdx], rbx\njmp loc_1236\nloc_133D:\nlea rbx, unk_2024\nmov [rdx], rbx\njmp loc_1236\nloc_134C:\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(float *a1, int a2)\n{\n _QWORD *result; // rax\n _QWORD *v4; // rdx\n double v5; // xmm0_8\n\n result = malloc(8LL * a2);\n if ( a2 > 0 )\n {\n v4 = result;\n do\n {\n v5 = *a1;\n if ( v5 < 3.9999 )\n {\n if ( v5 <= 3.7001 )\n {\n if ( v5 <= 3.3001 )\n {\n if ( v5 <= 3.0001 )\n {\n if ( v5 <= 2.7001 )\n {\n if ( v5 <= 2.3001 )\n {\n if ( v5 <= 2.0001 )\n {\n if ( v5 <= 1.7001 )\n {\n if ( v5 <= 1.3001 )\n {\n if ( v5 <= 1.0001 )\n {\n if ( v5 <= 0.7000999999999999 )\n {\n if ( v5 <= 0.0001 )\n *v4 = &unk_2024;\n else\n *v4 = &unk_2021;\n }\n else\n {\n *v4 = &unk_201F;\n }\n }\n else\n {\n *v4 = &unk_201C;\n }\n }\n else\n {\n *v4 = &unk_2019;\n }\n }\n else\n {\n *v4 = &unk_2017;\n }\n }\n else\n {\n *v4 = &unk_2014;\n }\n }\n else\n {\n *v4 = &unk_2011;\n }\n }\n else\n {\n *v4 = &unk_200F;\n }\n }\n else\n {\n *v4 = &unk_200C;\n }\n }\n else\n {\n *v4 = &unk_2009;\n }\n }\n else\n {\n *v4 = &unk_2007;\n }\n }\n else\n {\n *v4 = &unk_2004;\n }\n ++a1;\n ++v4;\n }\n while ( v4 != &result[a2] );\n }\n return result;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nmov r12d, esi\nmovsxd rsi, esi\nlea rbp, ds:0[rsi*8]\nmov rdi, rbp; size\ncall _malloc\ntest r12d, r12d\njle loc_134C\nmov rcx, rbx\nmov rdx, rax\nlea rsi, [rbp+rax+0]\nmovsd xmm1, cs:qword_2108\nmovsd xmm2, cs:qword_2110\nmovsd xmm3, cs:qword_2118\nlea r9, unk_2009\nlea r8, unk_2007\nlea rdi, unk_2004\njmp short loc_1247\nloc_122D:\ncomisd xmm0, xmm2\njbe short loc_125A\nmov [rdx], r8\nloc_1236:\nadd rcx, 4\nadd rdx, 8\ncmp rdx, rsi\njz loc_134C\nloc_1247:\npxor xmm0, xmm0\ncvtss2sd xmm0, dword ptr [rcx]\ncomisd xmm0, xmm1\njb short loc_122D\nmov [rdx], rdi\njmp short loc_1236\nloc_125A:\ncomisd xmm0, xmm3\njbe short loc_1265\nmov [rdx], r9\njmp short loc_1236\nloc_1265:\ncomisd xmm0, cs:qword_2120\njbe short loc_127B\nlea rbx, unk_200C\nmov [rdx], rbx\njmp short loc_1236\nloc_127B:\ncomisd xmm0, cs:qword_2128\njbe short loc_1291\nlea rbx, unk_200F\nmov [rdx], rbx\njmp short loc_1236\nloc_1291:\ncomisd xmm0, cs:qword_2130\njbe short loc_12A7\nlea rbx, unk_2011\nmov [rdx], rbx\njmp short loc_1236\nloc_12A7:\ncomisd xmm0, cs:qword_2138\njbe short loc_12C0\nlea rbx, unk_2014\nmov [rdx], rbx\njmp loc_1236\nloc_12C0:\ncomisd xmm0, cs:qword_2140\njbe short loc_12D9\nlea rbx, unk_2017\nmov [rdx], rbx\njmp loc_1236\nloc_12D9:\ncomisd xmm0, cs:qword_2148\njbe short loc_12F2\nlea rbx, unk_2019\nmov [rdx], rbx\njmp loc_1236\nloc_12F2:\ncomisd xmm0, cs:qword_2150\njbe short loc_130B\nlea rbx, unk_201C\nmov [rdx], rbx\njmp loc_1236\nloc_130B:\ncomisd xmm0, cs:qword_2158\njbe short loc_1324\nlea rbx, unk_201F\nmov [rdx], rbx\njmp loc_1236\nloc_1324:\ncomisd xmm0, cs:qword_2160\njbe short loc_133D\nlea rbx, unk_2021\nmov [rdx], rbx\njmp loc_1236\nloc_133D:\nlea rbx, unk_2024\nmov [rdx], rbx\njmp loc_1236\nloc_134C:\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11C9(float *a1, int a2)\n{\n _QWORD *result; // rax\n _QWORD *v4; // rdx\n double v5; // xmm0_8\n\n result = malloc(8LL * a2);\n if ( a2 > 0 )\n {\n v4 = result;\n do\n {\n v5 = *a1;\n if ( v5 < 3.9999 )\n {\n if ( v5 <= 3.7001 )\n {\n if ( v5 <= 3.3001 )\n {\n if ( v5 <= 3.0001 )\n {\n if ( v5 <= 2.7001 )\n {\n if ( v5 <= 2.3001 )\n {\n if ( v5 <= 2.0001 )\n {\n if ( v5 <= 1.7001 )\n {\n if ( v5 <= 1.3001 )\n {\n if ( v5 <= 1.0001 )\n {\n if ( v5 <= 0.7000999999999999 )\n {\n if ( v5 <= 0.0001 )\n *v4 = &unk_2024;\n else\n *v4 = &unk_2021;\n }\n else\n {\n *v4 = &unk_201F;\n }\n }\n else\n {\n *v4 = &unk_201C;\n }\n }\n else\n {\n *v4 = &unk_2019;\n }\n }\n else\n {\n *v4 = &unk_2017;\n }\n }\n else\n {\n *v4 = &unk_2014;\n }\n }\n else\n {\n *v4 = &unk_2011;\n }\n }\n else\n {\n *v4 = &unk_200F;\n }\n }\n else\n {\n *v4 = &unk_200C;\n }\n }\n else\n {\n *v4 = &unk_2009;\n }\n }\n else\n {\n *v4 = &unk_2007;\n }\n }\n else\n {\n *v4 = &unk_2004;\n }\n ++a1;\n ++v4;\n }\n while ( v4 != &result[a2] );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11C9(float *a1, int a2) {\n uint64_t *result;\n uint64_t *v4;\n double v5;\n result = malloc(8LL * a2);\n if (a2 > 0) {\n v4 = result;\n do {\n v5 = *a1;\n if (v5 < 3.9999) {\n if (v5 <= 3.7001) {\n if (v5 <= 3.3001) {\n if (v5 <= 3.0001) {\n if (v5 <= 2.7001) {\n if (v5 <= 2.3001) {\n if (v5 <= 2.0001) {\n if (v5 <= 1.7001) {\n if (v5 <= 1.3001) {\n if (v5 <= 1.0001) {\n if (v5 <= 0.7000999999999999) {\n if (v5 <= 0.0001)\n *v4 = &unk_2024;\n else\n *v4 = &unk_2021;\n } else {\n *v4 = &unk_201F;\n }\n } else {\n *v4 = &unk_201C;\n }\n } else {\n *v4 = &unk_2019;\n }\n } else {\n *v4 = &unk_2017;\n }\n } else {\n *v4 = &unk_2014;\n }\n } else {\n *v4 = &unk_2011;\n }\n } else {\n *v4 = &unk_200F;\n }\n } else {\n *v4 = &unk_200C;\n }\n } else {\n *v4 = &unk_2009;\n }\n } else {\n *v4 = &unk_2007;\n }\n } else {\n *v4 = &unk_2004;\n }\n ++a1;\n ++v4;\n } while (v4 != &result[a2]);\n }\n return result;\n}", + "ida_pseudo_norm": "uint64_t *func0(float *a1, int a2) {\n uint64_t *result;\n uint64_t *v4;\n double v5;\n result = malloc(8LL * a2);\n if (a2 > 0) {\n v4 = result;\n do {\n v5 = *a1;\n if (v5 < 3.9999) {\n if (v5 <= 3.7001) {\n if (v5 <= 3.3001) {\n if (v5 <= 3.0001) {\n if (v5 <= 2.7001) {\n if (v5 <= 2.3001) {\n if (v5 <= 2.0001) {\n if (v5 <= 1.7001) {\n if (v5 <= 1.3001) {\n if (v5 <= 1.0001) {\n if (v5 <= 0.7000999999999999) {\n if (v5 <= 0.0001)\n *v4 = &unk_2024;\n else\n *v4 = &unk_2021;\n } else {\n *v4 = &unk_201F;\n }\n } else {\n *v4 = &unk_201C;\n }\n } else {\n *v4 = &unk_2019;\n }\n } else {\n *v4 = &unk_2017;\n }\n } else {\n *v4 = &unk_2014;\n }\n } else {\n *v4 = &unk_2011;\n }\n } else {\n *v4 = &unk_200F;\n }\n } else {\n *v4 = &unk_200C;\n }\n } else {\n *v4 = &unk_2009;\n }\n } else {\n *v4 = &unk_2007;\n }\n } else {\n *v4 = &unk_2004;\n }\n ++a1;\n ++v4;\n } while (v4 != &result[a2]);\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-81", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "char** func0(float* grades, int size) {\n char** out = malloc(size * sizeof(char*));\n for (int i = 0; i < size; ++i) {\n if (grades[i] >= 3.9999)\n out[i] = \"A+\";\n else if (grades[i] > 3.7001)\n out[i] = \"A\";\n else if (grades[i] > 3.3001)\n out[i] = \"A-\";\n else if (grades[i] > 3.0001)\n out[i] = \"B+\";\n else if (grades[i] > 2.7001)\n out[i] = \"B\";\n else if (grades[i] > 2.3001)\n out[i] = \"B-\";\n else if (grades[i] > 2.0001)\n out[i] = \"C+\";\n else if (grades[i] > 1.7001)\n out[i] = \"C\";\n else if (grades[i] > 1.3001)\n out[i] = \"C-\";\n else if (grades[i] > 1.0001)\n out[i] = \"D+\";\n else if (grades[i] > 0.7001)\n out[i] = \"D\";\n else if (grades[i] > 0.0001)\n out[i] = \"D-\";\n else\n out[i] = \"E\";\n }\n return out;\n}", + "test": "#include \n#include \n#include \n\nbool issame(char** a, char** b, int size) {\n for (int i = 0; i < size; i++) {\n if (strcmp(a[i], b[i]) != 0) return false;\n }\n return true;\n}\n\nint main() {\n float grades1[] = {4.0, 3, 1.7, 2, 3.5};\n char* expected1[] = {\"A+\", \"B\", \"C-\", \"C\", \"A-\"};\n char** result1 = func0(grades1, 5);\n assert(issame(result1, expected1, 5));\n free(result1);\n\n float grades2[] = {1.2};\n char* expected2[] = {\"D+\"};\n char** result2 = func0(grades2, 1);\n assert(issame(result2, expected2, 1));\n free(result2);\n\n float grades3[] = {0.5};\n char* expected3[] = {\"D-\"};\n char** result3 = func0(grades3, 1);\n assert(issame(result3, expected3, 1));\n free(result3);\n\n float grades4[] = {0.0};\n char* expected4[] = {\"E\"};\n char** result4 = func0(grades4, 1);\n assert(issame(result4, expected4, 1));\n free(result4);\n\n float grades5[] = {1, 0.3, 1.5, 2.8, 3.3};\n char* expected5[] = {\"D\", \"D-\", \"C-\", \"B\", \"B+\"};\n char** result5 = func0(grades5, 5);\n assert(issame(result5, expected5, 5));\n free(result5);\n\n float grades6[] = {0, 0.7};\n char* expected6[] = {\"E\", \"D-\"};\n char** result6 = func0(grades6, 2);\n assert(issame(result6, expected6, 2));\n free(result6);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\nmovsxd rbp, esi\npush rbx\nmov rbx, rdi\nlea rdi, ds:0[rbp*8]; size\ncall _malloc\nmovsd xmm1, cs:qword_2108\ntest ebp, ebp\njle loc_1605\nxor edx, edx\nmovsd xmm2, cs:qword_2110\nmovsd xmm3, cs:qword_2118\nlea rsi, unk_2004\nlea rdi, unk_2007\nlea r8, unk_2009\nlea r9, unk_200C\nnop dword ptr [rax+00000000h]\nloc_15B0:\npxor xmm0, xmm0\nmov rcx, rsi\ncvtss2sd xmm0, dword ptr [rbx+rdx*4]\ncomisd xmm0, xmm1\njnb short loc_15F8\ncomisd xmm0, xmm2\nmov rcx, rdi\nja short loc_15F8\ncomisd xmm0, xmm3\nmov rcx, r8\nja short loc_15F8\ncomisd xmm0, cs:qword_2120\nmov rcx, r9\nja short loc_15F8\ncomisd xmm0, cs:qword_2128\nlea rcx, unk_200F\njbe short loc_1610\nnop word ptr [rax+rax+00h]\nloc_15F8:\nmov [rax+rdx*8], rcx\nadd rdx, 1\ncmp rbp, rdx\njnz short loc_15B0\nloc_1605:\npop rbx\npop rbp\npop r12\nretn\nloc_1610:\ncomisd xmm0, cs:qword_2130\nlea rcx, unk_2011\nja short loc_15F8\ncomisd xmm0, cs:qword_2138\nlea rcx, unk_2014\nja short loc_15F8\ncomisd xmm0, cs:qword_2140\nlea rcx, unk_2017\nja short loc_15F8\ncomisd xmm0, cs:qword_2148\nlea rcx, unk_2019\nja short loc_15F8\ncomisd xmm0, cs:qword_2150\nlea rcx, unk_201C\nja short loc_15F8\ncomisd xmm0, cs:qword_2158\nlea rcx, unk_201F\nja short loc_15F8\ncomisd xmm0, cs:qword_2160\nlea rcx, unk_2021\nlea r10, unk_2024\ncmovbe rcx, r10\njmp loc_15F8", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, int a2)\n{\n _QWORD *result; // rax\n __int64 i; // rdx\n void *v4; // rcx\n double v5; // xmm0_8\n\n result = malloc(8LL * a2);\n if ( a2 > 0 )\n {\n for ( i = 0LL; i != a2; result[i++] = v4 )\n {\n v4 = &unk_2004;\n v5 = *(float *)(a1 + 4 * i);\n if ( v5 < 3.9999 )\n {\n v4 = &unk_2007;\n if ( v5 <= 3.7001 )\n {\n v4 = &unk_2009;\n if ( v5 <= 3.3001 )\n {\n v4 = &unk_200C;\n if ( v5 <= 3.0001 )\n {\n v4 = &unk_200F;\n if ( v5 <= 2.7001 )\n {\n v4 = &unk_2011;\n if ( v5 <= 2.3001 )\n {\n v4 = &unk_2014;\n if ( v5 <= 2.0001 )\n {\n v4 = &unk_2017;\n if ( v5 <= 1.7001 )\n {\n v4 = &unk_2019;\n if ( v5 <= 1.3001 )\n {\n v4 = &unk_201C;\n if ( v5 <= 1.0001 )\n {\n v4 = &unk_201F;\n if ( v5 <= 0.7000999999999999 )\n {\n v4 = &unk_2021;\n if ( v5 <= 0.0001 )\n v4 = &unk_2024;\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1550:\nendbr64\npush r12\npush rbp\nmovsxd rbp, esi\npush rbx\nmov rbx, rdi\nlea rdi, ds:0[rbp*8]; size\ncall _malloc\nmovsd xmm1, cs:qword_2108\ntest ebp, ebp\njle loc_1605\nxor edx, edx\nmovsd xmm2, cs:qword_2110\nmovsd xmm3, cs:qword_2118\nlea rsi, unk_2004\nlea rdi, unk_2007\nlea r8, unk_2009\nlea r9, unk_200C\nnop dword ptr [rax+00000000h]\nloc_15B0:\npxor xmm0, xmm0\nmov rcx, rsi\ncvtss2sd xmm0, dword ptr [rbx+rdx*4]\ncomisd xmm0, xmm1\njnb short loc_15F8\ncomisd xmm0, xmm2\nmov rcx, rdi\nja short loc_15F8\ncomisd xmm0, xmm3\nmov rcx, r8\nja short loc_15F8\ncomisd xmm0, cs:qword_2120\nmov rcx, r9\nja short loc_15F8\ncomisd xmm0, cs:qword_2128\nlea rcx, unk_200F\njbe short loc_1610\nnop word ptr [rax+rax+00h]\nloc_15F8:\nmov [rax+rdx*8], rcx\nadd rdx, 1\ncmp rbp, rdx\njnz short loc_15B0\nloc_1605:\npop rbx\npop rbp\npop r12\nretn\nloc_1610:\ncomisd xmm0, cs:qword_2130\nlea rcx, unk_2011\nja short loc_15F8\ncomisd xmm0, cs:qword_2138\nlea rcx, unk_2014\nja short loc_15F8\ncomisd xmm0, cs:qword_2140\nlea rcx, unk_2017\nja short loc_15F8\ncomisd xmm0, cs:qword_2148\nlea rcx, unk_2019\nja short loc_15F8\ncomisd xmm0, cs:qword_2150\nlea rcx, unk_201C\nja short loc_15F8\ncomisd xmm0, cs:qword_2158\nlea rcx, unk_201F\nja short loc_15F8\ncomisd xmm0, cs:qword_2160\nlea rcx, unk_2021\nlea r10, unk_2024\ncmovbe rcx, r10\njmp loc_15F8", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1550(__int64 a1, int a2)\n{\n _QWORD *result; // rax\n __int64 i; // rdx\n void *v4; // rcx\n double v5; // xmm0_8\n\n result = malloc(8LL * a2);\n if ( a2 > 0 )\n {\n for ( i = 0LL; i != a2; result[i++] = v4 )\n {\n v4 = &unk_2004;\n v5 = *(float *)(a1 + 4 * i);\n if ( v5 < 3.9999 )\n {\n v4 = &unk_2007;\n if ( v5 <= 3.7001 )\n {\n v4 = &unk_2009;\n if ( v5 <= 3.3001 )\n {\n v4 = &unk_200C;\n if ( v5 <= 3.0001 )\n {\n v4 = &unk_200F;\n if ( v5 <= 2.7001 )\n {\n v4 = &unk_2011;\n if ( v5 <= 2.3001 )\n {\n v4 = &unk_2014;\n if ( v5 <= 2.0001 )\n {\n v4 = &unk_2017;\n if ( v5 <= 1.7001 )\n {\n v4 = &unk_2019;\n if ( v5 <= 1.3001 )\n {\n v4 = &unk_201C;\n if ( v5 <= 1.0001 )\n {\n v4 = &unk_201F;\n if ( v5 <= 0.7000999999999999 )\n {\n v4 = &unk_2021;\n if ( v5 <= 0.0001 )\n v4 = &unk_2024;\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1550(long long a1, int a2) {\n uint64_t *result;\n long long i;\n void *v4;\n double v5;\n result = malloc(8LL * a2);\n if (a2 > 0) {\n for (i = 0LL; i != a2; result[i++] = v4) {\n v4 = &unk_2004;\n v5 = *(float *)(a1 + 4 * i);\n if (v5 < 3.9999) {\n v4 = &unk_2007;\n if (v5 <= 3.7001) {\n v4 = &unk_2009;\n if (v5 <= 3.3001) {\n v4 = &unk_200C;\n if (v5 <= 3.0001) {\n v4 = &unk_200F;\n if (v5 <= 2.7001) {\n v4 = &unk_2011;\n if (v5 <= 2.3001) {\n v4 = &unk_2014;\n if (v5 <= 2.0001) {\n v4 = &unk_2017;\n if (v5 <= 1.7001) {\n v4 = &unk_2019;\n if (v5 <= 1.3001) {\n v4 = &unk_201C;\n if (v5 <= 1.0001) {\n v4 = &unk_201F;\n if (v5 <= 0.7000999999999999) {\n v4 = &unk_2021;\n if (v5 <= 0.0001) v4 = &unk_2024;\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, int a2) {\n uint64_t *result;\n long long i;\n void *v4;\n double v5;\n result = malloc(8LL * a2);\n if (a2 > 0) {\n for (i = 0LL; i != a2; result[i++] = v4) {\n v4 = &unk_2004;\n v5 = *(float *)(a1 + 4 * i);\n if (v5 < 3.9999) {\n v4 = &unk_2007;\n if (v5 <= 3.7001) {\n v4 = &unk_2009;\n if (v5 <= 3.3001) {\n v4 = &unk_200C;\n if (v5 <= 3.0001) {\n v4 = &unk_200F;\n if (v5 <= 2.7001) {\n v4 = &unk_2011;\n if (v5 <= 2.3001) {\n v4 = &unk_2014;\n if (v5 <= 2.0001) {\n v4 = &unk_2017;\n if (v5 <= 1.7001) {\n v4 = &unk_2019;\n if (v5 <= 1.3001) {\n v4 = &unk_201C;\n if (v5 <= 1.0001) {\n v4 = &unk_201F;\n if (v5 <= 0.7000999999999999) {\n v4 = &unk_2021;\n if (v5 <= 0.0001) v4 = &unk_2024;\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-81", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "char** func0(float* grades, int size) {\n char** out = malloc(size * sizeof(char*));\n for (int i = 0; i < size; ++i) {\n if (grades[i] >= 3.9999)\n out[i] = \"A+\";\n else if (grades[i] > 3.7001)\n out[i] = \"A\";\n else if (grades[i] > 3.3001)\n out[i] = \"A-\";\n else if (grades[i] > 3.0001)\n out[i] = \"B+\";\n else if (grades[i] > 2.7001)\n out[i] = \"B\";\n else if (grades[i] > 2.3001)\n out[i] = \"B-\";\n else if (grades[i] > 2.0001)\n out[i] = \"C+\";\n else if (grades[i] > 1.7001)\n out[i] = \"C\";\n else if (grades[i] > 1.3001)\n out[i] = \"C-\";\n else if (grades[i] > 1.0001)\n out[i] = \"D+\";\n else if (grades[i] > 0.7001)\n out[i] = \"D\";\n else if (grades[i] > 0.0001)\n out[i] = \"D-\";\n else\n out[i] = \"E\";\n }\n return out;\n}", + "test": "#include \n#include \n#include \n\nbool issame(char** a, char** b, int size) {\n for (int i = 0; i < size; i++) {\n if (strcmp(a[i], b[i]) != 0) return false;\n }\n return true;\n}\n\nint main() {\n float grades1[] = {4.0, 3, 1.7, 2, 3.5};\n char* expected1[] = {\"A+\", \"B\", \"C-\", \"C\", \"A-\"};\n char** result1 = func0(grades1, 5);\n assert(issame(result1, expected1, 5));\n free(result1);\n\n float grades2[] = {1.2};\n char* expected2[] = {\"D+\"};\n char** result2 = func0(grades2, 1);\n assert(issame(result2, expected2, 1));\n free(result2);\n\n float grades3[] = {0.5};\n char* expected3[] = {\"D-\"};\n char** result3 = func0(grades3, 1);\n assert(issame(result3, expected3, 1));\n free(result3);\n\n float grades4[] = {0.0};\n char* expected4[] = {\"E\"};\n char** result4 = func0(grades4, 1);\n assert(issame(result4, expected4, 1));\n free(result4);\n\n float grades5[] = {1, 0.3, 1.5, 2.8, 3.3};\n char* expected5[] = {\"D\", \"D-\", \"C-\", \"B\", \"B+\"};\n char** result5 = func0(grades5, 5);\n assert(issame(result5, expected5, 5));\n free(result5);\n\n float grades6[] = {0, 0.7};\n char* expected6[] = {\"E\", \"D-\"};\n char** result6 = func0(grades6, 2);\n assert(issame(result6, expected6, 2));\n free(result6);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\nmovsxd rbp, esi\npush rbx\nmov rbx, rdi\nlea rdi, ds:0[rbp*8]; size\ncall _malloc\nmovsd xmm1, cs:qword_2108\ntest ebp, ebp\njle loc_1605\nxor edx, edx\nmovsd xmm2, cs:qword_2110\nmovsd xmm3, cs:qword_2118\nlea rsi, unk_2004\nlea rdi, unk_2007\nlea r8, unk_2009\nlea r9, unk_200C\nnop dword ptr [rax+00000000h]\nloc_15B0:\npxor xmm0, xmm0\nmov rcx, rsi\ncvtss2sd xmm0, dword ptr [rbx+rdx*4]\ncomisd xmm0, xmm1\njnb short loc_15F8\ncomisd xmm0, xmm2\nmov rcx, rdi\nja short loc_15F8\ncomisd xmm0, xmm3\nmov rcx, r8\nja short loc_15F8\ncomisd xmm0, cs:qword_2120\nmov rcx, r9\nja short loc_15F8\ncomisd xmm0, cs:qword_2128\nlea rcx, unk_200F\njbe short loc_1610\nnop word ptr [rax+rax+00h]\nloc_15F8:\nmov [rax+rdx*8], rcx\nadd rdx, 1\ncmp rbp, rdx\njnz short loc_15B0\nloc_1605:\npop rbx\npop rbp\npop r12\nretn\nloc_1610:\ncomisd xmm0, cs:qword_2130\nlea rcx, unk_2011\nja short loc_15F8\ncomisd xmm0, cs:qword_2138\nlea rcx, unk_2014\nja short loc_15F8\ncomisd xmm0, cs:qword_2140\nlea rcx, unk_2017\nja short loc_15F8\ncomisd xmm0, cs:qword_2148\nlea rcx, unk_2019\nja short loc_15F8\ncomisd xmm0, cs:qword_2150\nlea rcx, unk_201C\nja short loc_15F8\ncomisd xmm0, cs:qword_2158\nlea rcx, unk_201F\nja short loc_15F8\ncomisd xmm0, cs:qword_2160\nlea rcx, unk_2021\nlea r10, unk_2024\ncmovbe rcx, r10\njmp loc_15F8", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, int a2)\n{\n _QWORD *result; // rax\n __int64 i; // rdx\n void *v4; // rcx\n double v5; // xmm0_8\n\n result = malloc(8LL * a2);\n if ( a2 > 0 )\n {\n for ( i = 0LL; i != a2; result[i++] = v4 )\n {\n v4 = &unk_2004;\n v5 = *(float *)(a1 + 4 * i);\n if ( v5 < 3.9999 )\n {\n v4 = &unk_2007;\n if ( v5 <= 3.7001 )\n {\n v4 = &unk_2009;\n if ( v5 <= 3.3001 )\n {\n v4 = &unk_200C;\n if ( v5 <= 3.0001 )\n {\n v4 = &unk_200F;\n if ( v5 <= 2.7001 )\n {\n v4 = &unk_2011;\n if ( v5 <= 2.3001 )\n {\n v4 = &unk_2014;\n if ( v5 <= 2.0001 )\n {\n v4 = &unk_2017;\n if ( v5 <= 1.7001 )\n {\n v4 = &unk_2019;\n if ( v5 <= 1.3001 )\n {\n v4 = &unk_201C;\n if ( v5 <= 1.0001 )\n {\n v4 = &unk_201F;\n if ( v5 <= 0.7000999999999999 )\n {\n v4 = &unk_2021;\n if ( v5 <= 0.0001 )\n v4 = &unk_2024;\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1550:\nendbr64\npush r12\npush rbp\nmovsxd rbp, esi\npush rbx\nmov rbx, rdi\nlea rdi, ds:0[rbp*8]; size\ncall _malloc\nmovsd xmm1, cs:qword_2108\ntest ebp, ebp\njle loc_1605\nxor edx, edx\nmovsd xmm2, cs:qword_2110\nmovsd xmm3, cs:qword_2118\nlea rsi, unk_2004\nlea rdi, unk_2007\nlea r8, unk_2009\nlea r9, unk_200C\nnop dword ptr [rax+00000000h]\nloc_15B0:\npxor xmm0, xmm0\nmov rcx, rsi\ncvtss2sd xmm0, dword ptr [rbx+rdx*4]\ncomisd xmm0, xmm1\njnb short loc_15F8\ncomisd xmm0, xmm2\nmov rcx, rdi\nja short loc_15F8\ncomisd xmm0, xmm3\nmov rcx, r8\nja short loc_15F8\ncomisd xmm0, cs:qword_2120\nmov rcx, r9\nja short loc_15F8\ncomisd xmm0, cs:qword_2128\nlea rcx, unk_200F\njbe short loc_1610\nnop word ptr [rax+rax+00h]\nloc_15F8:\nmov [rax+rdx*8], rcx\nadd rdx, 1\ncmp rbp, rdx\njnz short loc_15B0\nloc_1605:\npop rbx\npop rbp\npop r12\nretn\nloc_1610:\ncomisd xmm0, cs:qword_2130\nlea rcx, unk_2011\nja short loc_15F8\ncomisd xmm0, cs:qword_2138\nlea rcx, unk_2014\nja short loc_15F8\ncomisd xmm0, cs:qword_2140\nlea rcx, unk_2017\nja short loc_15F8\ncomisd xmm0, cs:qword_2148\nlea rcx, unk_2019\nja short loc_15F8\ncomisd xmm0, cs:qword_2150\nlea rcx, unk_201C\nja short loc_15F8\ncomisd xmm0, cs:qword_2158\nlea rcx, unk_201F\nja short loc_15F8\ncomisd xmm0, cs:qword_2160\nlea rcx, unk_2021\nlea r10, unk_2024\ncmovbe rcx, r10\njmp loc_15F8", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1550(__int64 a1, int a2)\n{\n _QWORD *result; // rax\n __int64 i; // rdx\n void *v4; // rcx\n double v5; // xmm0_8\n\n result = malloc(8LL * a2);\n if ( a2 > 0 )\n {\n for ( i = 0LL; i != a2; result[i++] = v4 )\n {\n v4 = &unk_2004;\n v5 = *(float *)(a1 + 4 * i);\n if ( v5 < 3.9999 )\n {\n v4 = &unk_2007;\n if ( v5 <= 3.7001 )\n {\n v4 = &unk_2009;\n if ( v5 <= 3.3001 )\n {\n v4 = &unk_200C;\n if ( v5 <= 3.0001 )\n {\n v4 = &unk_200F;\n if ( v5 <= 2.7001 )\n {\n v4 = &unk_2011;\n if ( v5 <= 2.3001 )\n {\n v4 = &unk_2014;\n if ( v5 <= 2.0001 )\n {\n v4 = &unk_2017;\n if ( v5 <= 1.7001 )\n {\n v4 = &unk_2019;\n if ( v5 <= 1.3001 )\n {\n v4 = &unk_201C;\n if ( v5 <= 1.0001 )\n {\n v4 = &unk_201F;\n if ( v5 <= 0.7000999999999999 )\n {\n v4 = &unk_2021;\n if ( v5 <= 0.0001 )\n v4 = &unk_2024;\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1550(long long a1, int a2) {\n uint64_t *result;\n long long i;\n void *v4;\n double v5;\n result = malloc(8LL * a2);\n if (a2 > 0) {\n for (i = 0LL; i != a2; result[i++] = v4) {\n v4 = &unk_2004;\n v5 = *(float *)(a1 + 4 * i);\n if (v5 < 3.9999) {\n v4 = &unk_2007;\n if (v5 <= 3.7001) {\n v4 = &unk_2009;\n if (v5 <= 3.3001) {\n v4 = &unk_200C;\n if (v5 <= 3.0001) {\n v4 = &unk_200F;\n if (v5 <= 2.7001) {\n v4 = &unk_2011;\n if (v5 <= 2.3001) {\n v4 = &unk_2014;\n if (v5 <= 2.0001) {\n v4 = &unk_2017;\n if (v5 <= 1.7001) {\n v4 = &unk_2019;\n if (v5 <= 1.3001) {\n v4 = &unk_201C;\n if (v5 <= 1.0001) {\n v4 = &unk_201F;\n if (v5 <= 0.7000999999999999) {\n v4 = &unk_2021;\n if (v5 <= 0.0001) v4 = &unk_2024;\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, int a2) {\n uint64_t *result;\n long long i;\n void *v4;\n double v5;\n result = malloc(8LL * a2);\n if (a2 > 0) {\n for (i = 0LL; i != a2; result[i++] = v4) {\n v4 = &unk_2004;\n v5 = *(float *)(a1 + 4 * i);\n if (v5 < 3.9999) {\n v4 = &unk_2007;\n if (v5 <= 3.7001) {\n v4 = &unk_2009;\n if (v5 <= 3.3001) {\n v4 = &unk_200C;\n if (v5 <= 3.0001) {\n v4 = &unk_200F;\n if (v5 <= 2.7001) {\n v4 = &unk_2011;\n if (v5 <= 2.3001) {\n v4 = &unk_2014;\n if (v5 <= 2.0001) {\n v4 = &unk_2017;\n if (v5 <= 1.7001) {\n v4 = &unk_2019;\n if (v5 <= 1.3001) {\n v4 = &unk_201C;\n if (v5 <= 1.0001) {\n v4 = &unk_201F;\n if (v5 <= 0.7000999999999999) {\n v4 = &unk_2021;\n if (v5 <= 0.0001) v4 = &unk_2024;\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-82", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "bool func0(const char* str) {\n int l = strlen(str);\n if (l < 2) return false;\n for (int i = 2; i * i <= l; i++) {\n if (l % i == 0) return false;\n }\n return true;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"Hello\") == true);\n assert(func0(\"abcdcba\") == true);\n assert(func0(\"kittens\") == true);\n assert(func0(\"orange\") == false);\n assert(func0(\"wow\") == true);\n assert(func0(\"world\") == true);\n assert(func0(\"MadaM\") == true);\n assert(func0(\"Wow\") == true);\n assert(func0(\"\") == false);\n assert(func0(\"HI\") == true);\n assert(func0(\"go\") == true);\n assert(func0(\"gogo\") == false);\n assert(func0(\"aaaaaaaaaaaaaaa\") == false);\n assert(func0(\"Madam\") == true);\n assert(func0(\"M\") == false);\n assert(func0(\"0\") == false);\n \n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\ncmp [rbp+var_4], 1\njg short loc_1195\nmov eax, 0\njmp short locret_11C6\nloc_1195:\nmov [rbp+var_8], 2\njmp short loc_11B6\nloc_119E:\nmov eax, [rbp+var_4]\ncdq\nidiv [rbp+var_8]\nmov eax, edx\ntest eax, eax\njnz short loc_11B2\nmov eax, 0\njmp short locret_11C6\nloc_11B2:\nadd [rbp+var_8], 1\nloc_11B6:\nmov eax, [rbp+var_8]\nimul eax, eax\ncmp [rbp+var_4], eax\njge short loc_119E\nmov eax, 1\nlocret_11C6:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int i; // [rsp+18h] [rbp-8h]\n int v3; // [rsp+1Ch] [rbp-4h]\n\n v3 = strlen(a1);\n if ( v3 <= 1 )\n return 0LL;\n for ( i = 2; v3 >= i * i; ++i )\n {\n if ( !(v3 % i) )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\ncmp [rbp+var_4], 1\njg short loc_1195\nmov eax, 0\njmp short locret_11C6\nloc_1195:\nmov [rbp+var_8], 2\njmp short loc_11B6\nloc_119E:\nmov eax, [rbp+var_4]\ncdq\nidiv [rbp+var_8]\nmov eax, edx\ntest eax, eax\njnz short loc_11B2\nmov eax, 0\njmp short locret_11C6\nloc_11B2:\nadd [rbp+var_8], 1\nloc_11B6:\nmov eax, [rbp+var_8]\nimul eax, eax\ncmp [rbp+var_4], eax\njge short loc_119E\nmov eax, 1\nlocret_11C6:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1)\n{\n int i; // [rsp+18h] [rbp-8h]\n int v3; // [rsp+1Ch] [rbp-4h]\n\n v3 = strlen(a1);\n if ( v3 <= 1 )\n return 0LL;\n for ( i = 2; v3 >= i * i; ++i )\n {\n if ( !(v3 % i) )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1) {\n int i;\n int v3;\n v3 = strlen(a1);\n if (v3 <= 1) return 0LL;\n for (i = 2; v3 >= i * i; ++i) {\n if (!(v3 % i)) return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int i;\n int v3;\n v3 = strlen(a1);\n if (v3 <= 1) return 0LL;\n for (i = 2; v3 >= i * i; ++i) {\n if (!(v3 % i)) return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": "HumanEval-C-82", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "bool func0(const char* str) {\n int l = strlen(str);\n if (l < 2) return false;\n for (int i = 2; i * i <= l; i++) {\n if (l % i == 0) return false;\n }\n return true;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"Hello\") == true);\n assert(func0(\"abcdcba\") == true);\n assert(func0(\"kittens\") == true);\n assert(func0(\"orange\") == false);\n assert(func0(\"wow\") == true);\n assert(func0(\"world\") == true);\n assert(func0(\"MadaM\") == true);\n assert(func0(\"Wow\") == true);\n assert(func0(\"\") == false);\n assert(func0(\"HI\") == true);\n assert(func0(\"go\") == true);\n assert(func0(\"gogo\") == false);\n assert(func0(\"aaaaaaaaaaaaaaa\") == false);\n assert(func0(\"Madam\") == true);\n assert(func0(\"M\") == false);\n assert(func0(\"0\") == false);\n \n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\ncall _strlen\nmov edx, 0\ncmp eax, 1\njle short loc_11B1\nmov esi, eax\ncmp eax, 3\njle short loc_11B8\ntest al, 1\njz short loc_11BF\nmov ecx, 2\nloc_1190:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, esi\njg short loc_11AC\nmov eax, esi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_1190\nmov edx, 0\njmp short loc_11B1\nloc_11AC:\nmov edx, 1\nloc_11B1:\nmov eax, edx\nadd rsp, 8\nretn\nloc_11B8:\nmov edx, 1\njmp short loc_11B1\nloc_11BF:\nmov edx, 0\njmp short loc_11B1", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v1; // eax\n unsigned int v2; // edx\n int v3; // ecx\n\n v1 = strlen(a1);\n v2 = 0;\n if ( v1 > 1 )\n {\n if ( v1 <= 3 )\n {\n return 1;\n }\n else if ( (v1 & 1) != 0 )\n {\n v3 = 2;\n while ( 1 )\n {\n ++v3;\n if ( v3 * v3 > v1 )\n break;\n if ( !(v1 % v3) )\n return 0;\n }\n return 1;\n }\n else\n {\n return 0;\n }\n }\n return v2;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nsub rsp, 8\ncall _strlen\nmov edx, 0\ncmp eax, 1\njle short loc_11B1\nmov esi, eax\ncmp eax, 3\njle short loc_11B8\ntest al, 1\njz short loc_11BF\nmov ecx, 2\nloc_1190:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, esi\njg short loc_11AC\nmov eax, esi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_1190\nmov edx, 0\njmp short loc_11B1\nloc_11AC:\nmov edx, 1\nloc_11B1:\nmov eax, edx\nadd rsp, 8\nretn\nloc_11B8:\nmov edx, 1\njmp short loc_11B1\nloc_11BF:\nmov edx, 0\njmp short loc_11B1", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1)\n{\n int v1; // eax\n unsigned int v2; // edx\n int v3; // ecx\n\n v1 = strlen(a1);\n v2 = 0;\n if ( v1 > 1 )\n {\n if ( v1 <= 3 )\n {\n return 1;\n }\n else if ( (v1 & 1) != 0 )\n {\n v3 = 2;\n while ( 1 )\n {\n ++v3;\n if ( v3 * v3 > v1 )\n break;\n if ( !(v1 % v3) )\n return 0;\n }\n return 1;\n }\n else\n {\n return 0;\n }\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1) {\n int v1;\n unsigned int v2;\n int v3;\n v1 = strlen(a1);\n v2 = 0;\n if (v1 > 1) {\n if (v1 <= 3) {\n return 1;\n } else if ((v1 & 1) != 0) {\n v3 = 2;\n while (1) {\n ++v3;\n if (v3 * v3 > v1) break;\n if (!(v1 % v3)) return 0;\n }\n return 1;\n } else {\n return 0;\n }\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v1;\n unsigned int v2;\n int v3;\n v1 = strlen(a1);\n v2 = 0;\n if (v1 > 1) {\n if (v1 <= 3) {\n return 1;\n } else if ((v1 & 1) != 0) {\n v3 = 2;\n while (1) {\n ++v3;\n if (v3 * v3 > v1) break;\n if (!(v1 % v3)) return 0;\n }\n return 1;\n } else {\n return 0;\n }\n }\n return v2;\n}" + }, + { + "index": "HumanEval-C-82", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "bool func0(const char* str) {\n int l = strlen(str);\n if (l < 2) return false;\n for (int i = 2; i * i <= l; i++) {\n if (l % i == 0) return false;\n }\n return true;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"Hello\") == true);\n assert(func0(\"abcdcba\") == true);\n assert(func0(\"kittens\") == true);\n assert(func0(\"orange\") == false);\n assert(func0(\"wow\") == true);\n assert(func0(\"world\") == true);\n assert(func0(\"MadaM\") == true);\n assert(func0(\"Wow\") == true);\n assert(func0(\"\") == false);\n assert(func0(\"HI\") == true);\n assert(func0(\"go\") == true);\n assert(func0(\"gogo\") == false);\n assert(func0(\"aaaaaaaaaaaaaaa\") == false);\n assert(func0(\"Madam\") == true);\n assert(func0(\"M\") == false);\n assert(func0(\"0\") == false);\n \n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\ncall _strlen\nxor edx, edx\ncmp eax, 1\njle short loc_14FA\ncmp eax, 3\njle short loc_14F5\ntest al, 1\njz short loc_14FA\nmov esi, eax\nmov ecx, 2\njmp short loc_14E9\nloc_14E0:\nmov eax, esi\ncdq\nidiv ecx\ntest edx, edx\njz short loc_1508\nloc_14E9:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, esi\njle short loc_14E0\nloc_14F5:\nmov edx, 1\nloc_14FA:\nmov eax, edx\nadd rsp, 8\nretn\nloc_1508:\nxor edx, edx\nadd rsp, 8\nmov eax, edx\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v1; // eax\n unsigned int v2; // edx\n int v3; // ecx\n\n v1 = strlen(a1);\n v2 = 0;\n if ( v1 <= 1 )\n return v2;\n if ( v1 <= 3 )\n return 1;\n if ( (v1 & 1) != 0 )\n {\n v3 = 2;\n while ( 1 )\n {\n ++v3;\n if ( v3 * v3 > v1 )\n break;\n if ( !(v1 % v3) )\n return 0LL;\n }\n return 1;\n }\n return v2;\n}", + "ida_strip_asm": "sub_14B0:\nendbr64\nsub rsp, 8\ncall _strlen\nxor edx, edx\ncmp eax, 1\njle short loc_14FA\ncmp eax, 3\njle short loc_14F5\ntest al, 1\njz short loc_14FA\nmov esi, eax\nmov ecx, 2\njmp short loc_14E9\nloc_14E0:\nmov eax, esi\ncdq\nidiv ecx\ntest edx, edx\njz short loc_1508\nloc_14E9:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, esi\njle short loc_14E0\nloc_14F5:\nmov edx, 1\nloc_14FA:\nmov eax, edx\nadd rsp, 8\nretn\nloc_1508:\nxor edx, edx\nadd rsp, 8\nmov eax, edx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_14B0(const char *a1)\n{\n int v1; // eax\n unsigned int v2; // edx\n int v3; // ecx\n\n v1 = strlen(a1);\n v2 = 0;\n if ( v1 <= 1 )\n return v2;\n if ( v1 <= 3 )\n return 1;\n if ( (v1 & 1) != 0 )\n {\n v3 = 2;\n while ( 1 )\n {\n ++v3;\n if ( v3 * v3 > v1 )\n break;\n if ( !(v1 % v3) )\n return 0LL;\n }\n return 1;\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_14B0(const char *a1) {\n int v1;\n unsigned int v2;\n int v3;\n v1 = strlen(a1);\n v2 = 0;\n if (v1 <= 1) return v2;\n if (v1 <= 3) return 1;\n if ((v1 & 1) != 0) {\n v3 = 2;\n while (1) {\n ++v3;\n if (v3 * v3 > v1) break;\n if (!(v1 % v3)) return 0LL;\n }\n return 1;\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v1;\n unsigned int v2;\n int v3;\n v1 = strlen(a1);\n v2 = 0;\n if (v1 <= 1) return v2;\n if (v1 <= 3) return 1;\n if ((v1 & 1) != 0) {\n v3 = 2;\n while (1) {\n ++v3;\n if (v3 * v3 > v1) break;\n if (!(v1 % v3)) return 0LL;\n }\n return 1;\n }\n return v2;\n}" + }, + { + "index": "HumanEval-C-82", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "bool func0(const char* str) {\n int l = strlen(str);\n if (l < 2) return false;\n for (int i = 2; i * i <= l; i++) {\n if (l % i == 0) return false;\n }\n return true;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"Hello\") == true);\n assert(func0(\"abcdcba\") == true);\n assert(func0(\"kittens\") == true);\n assert(func0(\"orange\") == false);\n assert(func0(\"wow\") == true);\n assert(func0(\"world\") == true);\n assert(func0(\"MadaM\") == true);\n assert(func0(\"Wow\") == true);\n assert(func0(\"\") == false);\n assert(func0(\"HI\") == true);\n assert(func0(\"go\") == true);\n assert(func0(\"gogo\") == false);\n assert(func0(\"aaaaaaaaaaaaaaa\") == false);\n assert(func0(\"Madam\") == true);\n assert(func0(\"M\") == false);\n assert(func0(\"0\") == false);\n \n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\ncall _strlen\nxor edx, edx\ncmp eax, 1\njle short loc_14FA\ncmp eax, 3\njle short loc_14F5\ntest al, 1\njz short loc_14FA\nmov esi, eax\nmov ecx, 2\njmp short loc_14E9\nloc_14E0:\nmov eax, esi\ncdq\nidiv ecx\ntest edx, edx\njz short loc_1508\nloc_14E9:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, esi\njle short loc_14E0\nloc_14F5:\nmov edx, 1\nloc_14FA:\nmov eax, edx\nadd rsp, 8\nretn\nloc_1508:\nxor edx, edx\nadd rsp, 8\nmov eax, edx\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v1; // eax\n unsigned int v2; // edx\n int v3; // ecx\n\n v1 = strlen(a1);\n v2 = 0;\n if ( v1 <= 1 )\n return v2;\n if ( v1 <= 3 )\n return 1;\n if ( (v1 & 1) != 0 )\n {\n v3 = 2;\n while ( 1 )\n {\n ++v3;\n if ( v3 * v3 > v1 )\n break;\n if ( !(v1 % v3) )\n return 0LL;\n }\n return 1;\n }\n return v2;\n}", + "ida_strip_asm": "sub_14B0:\nendbr64\nsub rsp, 8\ncall _strlen\nxor edx, edx\ncmp eax, 1\njle short loc_14FA\ncmp eax, 3\njle short loc_14F5\ntest al, 1\njz short loc_14FA\nmov esi, eax\nmov ecx, 2\njmp short loc_14E9\nloc_14E0:\nmov eax, esi\ncdq\nidiv ecx\ntest edx, edx\njz short loc_1508\nloc_14E9:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, esi\njle short loc_14E0\nloc_14F5:\nmov edx, 1\nloc_14FA:\nmov eax, edx\nadd rsp, 8\nretn\nloc_1508:\nxor edx, edx\nadd rsp, 8\nmov eax, edx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_14B0(const char *a1)\n{\n int v1; // eax\n unsigned int v2; // edx\n int v3; // ecx\n\n v1 = strlen(a1);\n v2 = 0;\n if ( v1 <= 1 )\n return v2;\n if ( v1 <= 3 )\n return 1;\n if ( (v1 & 1) != 0 )\n {\n v3 = 2;\n while ( 1 )\n {\n ++v3;\n if ( v3 * v3 > v1 )\n break;\n if ( !(v1 % v3) )\n return 0LL;\n }\n return 1;\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_14B0(const char *a1) {\n int v1;\n unsigned int v2;\n int v3;\n v1 = strlen(a1);\n v2 = 0;\n if (v1 <= 1) return v2;\n if (v1 <= 3) return 1;\n if ((v1 & 1) != 0) {\n v3 = 2;\n while (1) {\n ++v3;\n if (v3 * v3 > v1) break;\n if (!(v1 % v3)) return 0LL;\n }\n return 1;\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v1;\n unsigned int v2;\n int v3;\n v1 = strlen(a1);\n v2 = 0;\n if (v1 <= 1) return v2;\n if (v1 <= 3) return 1;\n if ((v1 & 1) != 0) {\n v3 = 2;\n while (1) {\n ++v3;\n if (v3 * v3 > v1) break;\n if (!(v1 % v3)) return 0LL;\n }\n return 1;\n }\n return v2;\n}" + }, + { + "index": "HumanEval-C-83", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int n) {\n if (n < 1) return 0;\n if (n == 1) return 1;\n int out = 18;\n for (int i = 2; i < n; i++) out = out * 10;\n return out;\n}", + "test": "#include \n\nint main() {\n assert(func0(1) == 1);\n assert(func0(2) == 18);\n assert(func0(3) == 180);\n assert(func0(4) == 1800);\n assert(func0(5) == 18000);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\ncmp [rbp+var_14], 0\njg short loc_1161\nmov eax, 0\njmp short loc_119C\nloc_1161:\ncmp [rbp+var_14], 1\njnz short loc_116E\nmov eax, 1\njmp short loc_119C\nloc_116E:\nmov [rbp+var_8], 12h\nmov [rbp+var_4], 2\njmp short loc_1191\nloc_117E:\nmov edx, [rbp+var_8]\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nmov [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_1191:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_14]\njl short loc_117E\nmov eax, [rbp+var_8]\nloc_119C:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v2; // [rsp+Ch] [rbp-8h]\n int i; // [rsp+10h] [rbp-4h]\n\n if ( a1 <= 0 )\n return 0LL;\n if ( a1 == 1 )\n return 1LL;\n v2 = 18;\n for ( i = 2; i < a1; ++i )\n v2 *= 10;\n return v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\ncmp [rbp+var_14], 0\njg short loc_1161\nmov eax, 0\njmp short loc_119C\nloc_1161:\ncmp [rbp+var_14], 1\njnz short loc_116E\nmov eax, 1\njmp short loc_119C\nloc_116E:\nmov [rbp+var_8], 12h\nmov [rbp+var_4], 2\njmp short loc_1191\nloc_117E:\nmov edx, [rbp+var_8]\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nmov [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_1191:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_14]\njl short loc_117E\nmov eax, [rbp+var_8]\nloc_119C:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n unsigned int v2; // [rsp+Ch] [rbp-8h]\n int i; // [rsp+10h] [rbp-4h]\n\n if ( a1 <= 0 )\n return 0LL;\n if ( a1 == 1 )\n return 1LL;\n v2 = 18;\n for ( i = 2; i < a1; ++i )\n v2 *= 10;\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n unsigned int v2;\n int i;\n if (a1 <= 0) return 0LL;\n if (a1 == 1) return 1LL;\n v2 = 18;\n for (i = 2; i < a1; ++i) v2 *= 10;\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v2;\n int i;\n if (a1 <= 0) return 0LL;\n if (a1 == 1) return 1LL;\n v2 = 18;\n for (i = 2; i < a1; ++i) v2 *= 10;\n return v2;\n}" + }, + { + "index": "HumanEval-C-83", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int n) {\n if (n < 1) return 0;\n if (n == 1) return 1;\n int out = 18;\n for (int i = 2; i < n; i++) out = out * 10;\n return out;\n}", + "test": "#include \n\nint main() {\n assert(func0(1) == 1);\n assert(func0(2) == 18);\n assert(func0(3) == 180);\n assert(func0(4) == 1800);\n assert(func0(5) == 18000);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmov eax, 0\ntest edi, edi\njle short locret_117E\nmov eax, edi\ncmp edi, 1\njz short locret_117E\ncmp edi, 2\njle short loc_1179\nmov edx, 2\nmov eax, 12h\nloc_116C:\nlea eax, [rax+rax*4]\nadd eax, eax\nadd edx, 1\ncmp edi, edx\njnz short loc_116C\nretn\nloc_1179:\nmov eax, 12h\nlocret_117E:\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n __int64 result; // rax\n int v2; // edx\n\n result = 0LL;\n if ( a1 > 0 )\n {\n result = (unsigned int)a1;\n if ( a1 != 1 )\n {\n if ( a1 <= 2 )\n {\n return 18LL;\n }\n else\n {\n v2 = 2;\n LODWORD(result) = 18;\n do\n {\n result = (unsigned int)(10 * result);\n ++v2;\n }\n while ( a1 != v2 );\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmov eax, 0\ntest edi, edi\njle short locret_117E\nmov eax, edi\ncmp edi, 1\njz short locret_117E\ncmp edi, 2\njle short loc_1179\nmov edx, 2\nmov eax, 12h\nloc_116C:\nlea eax, [rax+rax*4]\nadd eax, eax\nadd edx, 1\ncmp edi, edx\njnz short loc_116C\nretn\nloc_1179:\nmov eax, 12h\nlocret_117E:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n __int64 result; // rax\n int v2; // edx\n\n result = 0LL;\n if ( a1 > 0 )\n {\n result = (unsigned int)a1;\n if ( a1 != 1 )\n {\n if ( a1 <= 2 )\n {\n return 18LL;\n }\n else\n {\n v2 = 2;\n LODWORD(result) = 18;\n do\n {\n result = (unsigned int)(10 * result);\n ++v2;\n }\n while ( a1 != v2 );\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n long long result;\n int v2;\n result = 0LL;\n if (a1 > 0) {\n result = (unsigned int)a1;\n if (a1 != 1) {\n if (a1 <= 2) {\n return 18LL;\n } else {\n v2 = 2;\n LODWORD(result) = 18;\n do {\n result = (unsigned int)(10 * result);\n ++v2;\n } while (a1 != v2);\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n long long result;\n int v2;\n result = 0LL;\n if (a1 > 0) {\n result = (unsigned int)a1;\n if (a1 != 1) {\n if (a1 <= 2) {\n return 18LL;\n } else {\n v2 = 2;\n LODWORD(result) = 18;\n do {\n result = (unsigned int)(10 * result);\n ++v2;\n } while (a1 != v2);\n }\n }\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-84", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "char* func0(int N) {\n char str[6];\n sprintf(str, \"%d\", N);\n int sum = 0;\n for (int i = 0; str[i] != '\\0'; i++) sum += str[i] - '0';\n char* bi = malloc(33);\n int index = 0;\n if (sum == 0) {\n bi[index++] = '0';\n } else {\n while (sum > 0) {\n bi[index++] = (sum % 2) + '0';\n sum /= 2;\n }\n }\n bi[index] = '\\0';\n for (int i = 0; i < index / 2; i++) {\n char temp = bi[i];\n bi[i] = bi[index - i - 1];\n bi[index - i - 1] = temp;\n }\n return bi;\n}", + "test": "#include \n#include \n\nint main() {\n char* result;\n\n result = func0(1000);\n assert(strcmp(result, \"1\") == 0);\n free(result);\n\n result = func0(150);\n assert(strcmp(result, \"110\") == 0);\n free(result);\n\n result = func0(147);\n assert(strcmp(result, \"1100\") == 0);\n free(result);\n\n result = func0(333);\n assert(strcmp(result, \"1001\") == 0);\n free(result);\n\n result = func0(963);\n assert(strcmp(result, \"10010\") == 0);\n free(result);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_34], edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov edx, [rbp+var_34]\nlea rax, [rbp+s]\nlea rcx, format; \"%d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nmov [rbp+var_28], 0\nmov [rbp+var_24], 0\njmp short loc_124C\nloc_1235:\nmov eax, [rbp+var_24]\ncdqe\nmovzx eax, [rbp+rax+s]\nmovsx eax, al\nsub eax, 30h ; '0'\nadd [rbp+var_28], eax\nadd [rbp+var_24], 1\nloc_124C:\nmov eax, [rbp+var_24]\ncdqe\nmovzx eax, [rbp+rax+s]\ntest al, al\njnz short loc_1235\nmov edi, 21h ; '!'; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_20], 0\ncmp [rbp+var_28], 0\njnz short loc_12CA\nmov eax, [rbp+var_20]\nlea edx, [rax+1]\nmov [rbp+var_20], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov byte ptr [rax], 30h ; '0'\njmp short loc_12D0\nloc_128D:\nmov edx, [rbp+var_28]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\nlea ecx, [rax+30h]\nmov eax, [rbp+var_20]\nlea edx, [rax+1]\nmov [rbp+var_20], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, ecx\nmov [rax], dl\nmov eax, [rbp+var_28]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_28], eax\nloc_12CA:\ncmp [rbp+var_28], 0\njg short loc_128D\nloc_12D0:\nmov eax, [rbp+var_20]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov [rbp+var_1C], 0\njmp short loc_133E\nloc_12E9:\nmov eax, [rbp+var_1C]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_29], al\nmov eax, [rbp+var_20]\nsub eax, [rbp+var_1C]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_1C]\nmovsxd rcx, edx\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmovzx eax, byte ptr [rax]\nmov [rdx], al\nmov eax, [rbp+var_20]\nsub eax, [rbp+var_1C]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmovzx eax, [rbp+var_29]\nmov [rdx], al\nadd [rbp+var_1C], 1\nloc_133E:\nmov eax, [rbp+var_20]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\ncmp [rbp+var_1C], eax\njl short loc_12E9\nmov rax, [rbp+var_18]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1367\ncall ___stack_chk_fail\nlocret_1367:\nleave\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(int a1)\n{\n int v1; // eax\n char v3; // [rsp+17h] [rbp-29h]\n int v4; // [rsp+18h] [rbp-28h]\n int i; // [rsp+1Ch] [rbp-24h]\n int v6; // [rsp+20h] [rbp-20h]\n int j; // [rsp+24h] [rbp-1Ch]\n _BYTE *v8; // [rsp+28h] [rbp-18h]\n char s[6]; // [rsp+32h] [rbp-Eh] BYREF\n unsigned __int64 v10; // [rsp+38h] [rbp-8h]\n\n v10 = __readfsqword(0x28u);\n sprintf(s, \"%d\", a1);\n v4 = 0;\n for ( i = 0; s[i]; ++i )\n v4 += s[i] - 48;\n v8 = malloc(0x21uLL);\n v6 = 0;\n if ( v4 )\n {\n while ( v4 > 0 )\n {\n v1 = v6++;\n v8[v1] = v4 % 2 + 48;\n v4 /= 2;\n }\n }\n else\n {\n v6 = 1;\n *v8 = 48;\n }\n v8[v6] = 0;\n for ( j = 0; j < v6 / 2; ++j )\n {\n v3 = v8[j];\n v8[j] = v8[v6 - j - 1];\n v8[v6 - j - 1] = v3;\n }\n return v8;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_34], edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov edx, [rbp+var_34]\nlea rax, [rbp+s]\nlea rcx, format; \"%d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nmov [rbp+var_28], 0\nmov [rbp+var_24], 0\njmp short loc_124C\nloc_1235:\nmov eax, [rbp+var_24]\ncdqe\nmovzx eax, [rbp+rax+s]\nmovsx eax, al\nsub eax, 30h ; '0'\nadd [rbp+var_28], eax\nadd [rbp+var_24], 1\nloc_124C:\nmov eax, [rbp+var_24]\ncdqe\nmovzx eax, [rbp+rax+s]\ntest al, al\njnz short loc_1235\nmov edi, 21h ; '!'; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_20], 0\ncmp [rbp+var_28], 0\njnz short loc_12CA\nmov eax, [rbp+var_20]\nlea edx, [rax+1]\nmov [rbp+var_20], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov byte ptr [rax], 30h ; '0'\njmp short loc_12D0\nloc_128D:\nmov edx, [rbp+var_28]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\nlea ecx, [rax+30h]\nmov eax, [rbp+var_20]\nlea edx, [rax+1]\nmov [rbp+var_20], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, ecx\nmov [rax], dl\nmov eax, [rbp+var_28]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_28], eax\nloc_12CA:\ncmp [rbp+var_28], 0\njg short loc_128D\nloc_12D0:\nmov eax, [rbp+var_20]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov [rbp+var_1C], 0\njmp short loc_133E\nloc_12E9:\nmov eax, [rbp+var_1C]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_29], al\nmov eax, [rbp+var_20]\nsub eax, [rbp+var_1C]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_1C]\nmovsxd rcx, edx\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmovzx eax, byte ptr [rax]\nmov [rdx], al\nmov eax, [rbp+var_20]\nsub eax, [rbp+var_1C]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmovzx eax, [rbp+var_29]\nmov [rdx], al\nadd [rbp+var_1C], 1\nloc_133E:\nmov eax, [rbp+var_20]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\ncmp [rbp+var_1C], eax\njl short loc_12E9\nmov rax, [rbp+var_18]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1367\ncall ___stack_chk_fail\nlocret_1367:\nleave\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_11E9(int a1)\n{\n int v1; // eax\n char v3; // [rsp+17h] [rbp-29h]\n int v4; // [rsp+18h] [rbp-28h]\n int i; // [rsp+1Ch] [rbp-24h]\n int v6; // [rsp+20h] [rbp-20h]\n int j; // [rsp+24h] [rbp-1Ch]\n _BYTE *v8; // [rsp+28h] [rbp-18h]\n char s[6]; // [rsp+32h] [rbp-Eh] BYREF\n unsigned __int64 v10; // [rsp+38h] [rbp-8h]\n\n v10 = __readfsqword(0x28u);\n sprintf(s, \"%d\", a1);\n v4 = 0;\n for ( i = 0; s[i]; ++i )\n v4 += s[i] - 48;\n v8 = malloc(0x21uLL);\n v6 = 0;\n if ( v4 )\n {\n while ( v4 > 0 )\n {\n v1 = v6++;\n v8[v1] = v4 % 2 + 48;\n v4 /= 2;\n }\n }\n else\n {\n v6 = 1;\n *v8 = 48;\n }\n v8[v6] = 0;\n for ( j = 0; j < v6 / 2; ++j )\n {\n v3 = v8[j];\n v8[j] = v8[v6 - j - 1];\n v8[v6 - j - 1] = v3;\n }\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_11E9(int a1) {\n int v1;\n char v3;\n int v4;\n int i;\n int v6;\n int j;\n uint8_t *v8;\n char s[6];\n unsigned long long v10;\n v10 = __readfsqword(40u);\n sprintf(s, \"%d\", a1);\n v4 = 0;\n for (i = 0; s[i]; ++i) v4 += s[i] - 48;\n v8 = malloc(33uLL);\n v6 = 0;\n if (v4) {\n while (v4 > 0) {\n v1 = v6++;\n v8[v1] = v4 % 2 + 48;\n v4 /= 2;\n }\n } else {\n v6 = 1;\n *v8 = 48;\n }\n v8[v6] = 0;\n for (j = 0; j < v6 / 2; ++j) {\n v3 = v8[j];\n v8[j] = v8[v6 - j - 1];\n v8[v6 - j - 1] = v3;\n }\n return v8;\n}", + "ida_pseudo_norm": "uint8_t *func0(int a1) {\n int v1;\n char v3;\n int v4;\n int i;\n int v6;\n int j;\n uint8_t *v8;\n char s[6];\n unsigned long long v10;\n v10 = __readfsqword(40u);\n sprintf(s, \"%d\", a1);\n v4 = 0;\n for (i = 0; s[i]; ++i) v4 += s[i] - 48;\n v8 = malloc(33uLL);\n v6 = 0;\n if (v4) {\n while (v4 > 0) {\n v1 = v6++;\n v8[v1] = v4 % 2 + 48;\n v4 /= 2;\n }\n } else {\n v6 = 1;\n *v8 = 48;\n }\n v8[v6] = 0;\n for (j = 0; j < v6 / 2; ++j) {\n v3 = v8[j];\n v8[j] = v8[v6 - j - 1];\n v8[v6 - j - 1] = v3;\n }\n return v8;\n}" + }, + { + "index": "HumanEval-C-84", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "char* func0(int N) {\n char str[6];\n sprintf(str, \"%d\", N);\n int sum = 0;\n for (int i = 0; str[i] != '\\0'; i++) sum += str[i] - '0';\n char* bi = malloc(33);\n int index = 0;\n if (sum == 0) {\n bi[index++] = '0';\n } else {\n while (sum > 0) {\n bi[index++] = (sum % 2) + '0';\n sum /= 2;\n }\n }\n bi[index] = '\\0';\n for (int i = 0; i < index / 2; i++) {\n char temp = bi[i];\n bi[i] = bi[index - i - 1];\n bi[index - i - 1] = temp;\n }\n return bi;\n}", + "test": "#include \n#include \n\nint main() {\n char* result;\n\n result = func0(1000);\n assert(strcmp(result, \"1\") == 0);\n free(result);\n\n result = func0(150);\n assert(strcmp(result, \"110\") == 0);\n free(result);\n\n result = func0(147);\n assert(strcmp(result, \"1100\") == 0);\n free(result);\n\n result = func0(333);\n assert(strcmp(result, \"1001\") == 0);\n free(result);\n\n result = func0(963);\n assert(strcmp(result, \"10010\") == 0);\n free(result);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbx\nsub rsp, 10h\nmov r8d, edi\nmov rax, fs:28h\nmov [rsp+18h+var_10], rax\nxor eax, eax\nlea rdi, [rsp+18h+var_16]\nlea rcx, unk_2004\nmov edx, 6\nmov esi, 2\ncall ___sprintf_chk\nmovzx eax, [rsp+18h+var_16]\ntest al, al\njz loc_12F2\nlea rdx, [rsp+18h+var_16]\nmov ebx, 0\nloc_1237:\nmovsx eax, al\nlea ebx, [rbx+rax-30h]\nadd rdx, 1\nmovzx eax, byte ptr [rdx]\ntest al, al\njnz short loc_1237\nmov edi, 21h ; '!'; size\ncall _malloc\nmov rcx, rax\ntest ebx, ebx\njz loc_12FF\nmov edx, 1\nmov eax, 0\njle loc_1307\nloc_126E:\nmov esi, ebx\nshr esi, 1Fh\nlea eax, [rbx+rsi]\nand eax, 1\nsub eax, esi\nadd eax, 30h ; '0'\nmov [rcx+rdx-1], al\nmov esi, ebx\nmov eax, ebx\nshr eax, 1Fh\nadd eax, ebx\nsar eax, 1\nmov ebx, eax\nmov rax, rdx\nadd rdx, 1\ncmp esi, 1\njg short loc_126E\nmovsxd rdx, eax\nmov byte ptr [rcx+rdx], 0\nmov r8d, eax\nshr r8d, 1Fh\nadd r8d, eax\nsar r8d, 1\ncmp eax, 1\njle short loc_12D9\nlea rdx, [rcx+rdx-1]\nmov eax, 0\nloc_12BE:\nmovzx esi, byte ptr [rcx+rax]\nmovzx edi, byte ptr [rdx]\nmov [rcx+rax], dil\nmov [rdx], sil\nadd rax, 1\nsub rdx, 1\ncmp r8d, eax\njg short loc_12BE\nloc_12D9:\nmov rax, [rsp+18h+var_10]\nsub rax, fs:28h\njnz short loc_130F\nmov rax, rcx\nadd rsp, 10h\npop rbx\nretn\nloc_12F2:\nmov edi, 21h ; '!'; size\ncall _malloc\nmov rcx, rax\nloc_12FF:\nmov byte ptr [rcx], 30h ; '0'\nmov eax, 1\nloc_1307:\ncdqe\nmov byte ptr [rcx+rax], 0\njmp short loc_12D9\nloc_130F:\ncall ___stack_chk_fail", + "ida_pseudo": "_BYTE *__fastcall func0(unsigned int a1)\n{\n char v1; // al\n _BYTE *v2; // rdx\n int v3; // ebx\n _BYTE *v4; // rcx\n __int64 v5; // rdx\n int v6; // eax\n int v7; // esi\n int v8; // eax\n int v9; // r8d\n _BYTE *v10; // rdx\n __int64 v11; // rax\n char v12; // si\n _BYTE v14[6]; // [rsp+2h] [rbp-16h] BYREF\n unsigned __int64 v15; // [rsp+8h] [rbp-10h]\n\n v15 = __readfsqword(0x28u);\n __sprintf_chk(v14, 2LL, 6LL, &unk_2004, a1);\n v1 = v14[0];\n if ( !v14[0] )\n {\n v4 = malloc(0x21uLL);\nLABEL_12:\n *v4 = 48;\n v6 = 1;\n goto LABEL_13;\n }\n v2 = v14;\n v3 = 0;\n do\n {\n v3 = v3 + v1 - 48;\n v1 = *++v2;\n }\n while ( *v2 );\n v4 = malloc(0x21uLL);\n if ( !v3 )\n goto LABEL_12;\n v5 = 1LL;\n v6 = 0;\n if ( v3 <= 0 )\n {\nLABEL_13:\n v4[v6] = 0;\n return v4;\n }\n do\n {\n v4[v5 - 1] = v3 % 2 + 48;\n v7 = v3;\n v3 /= 2;\n v8 = v5++;\n }\n while ( v7 > 1 );\n v4[v8] = 0;\n v9 = v8 / 2;\n if ( v8 > 1 )\n {\n v10 = &v4[v8 - 1];\n v11 = 0LL;\n do\n {\n v12 = v4[v11];\n v4[v11] = *v10;\n *v10 = v12;\n ++v11;\n --v10;\n }\n while ( v9 > (int)v11 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbx\nsub rsp, 10h\nmov r8d, edi\nmov rax, fs:28h\nmov [rsp+18h+var_10], rax\nxor eax, eax\nlea rdi, [rsp+18h+var_16]\nlea rcx, unk_2004\nmov edx, 6\nmov esi, 2\ncall ___sprintf_chk\nmovzx eax, [rsp+18h+var_16]\ntest al, al\njz loc_12F2\nlea rdx, [rsp+18h+var_16]\nmov ebx, 0\nloc_1237:\nmovsx eax, al\nlea ebx, [rbx+rax-30h]\nadd rdx, 1\nmovzx eax, byte ptr [rdx]\ntest al, al\njnz short loc_1237\nmov edi, 21h ; '!'; size\ncall _malloc\nmov rcx, rax\ntest ebx, ebx\njz loc_12FF\nmov edx, 1\nmov eax, 0\njle loc_1307\nloc_126E:\nmov esi, ebx\nshr esi, 1Fh\nlea eax, [rbx+rsi]\nand eax, 1\nsub eax, esi\nadd eax, 30h ; '0'\nmov [rcx+rdx-1], al\nmov esi, ebx\nmov eax, ebx\nshr eax, 1Fh\nadd eax, ebx\nsar eax, 1\nmov ebx, eax\nmov rax, rdx\nadd rdx, 1\ncmp esi, 1\njg short loc_126E\nmovsxd rdx, eax\nmov byte ptr [rcx+rdx], 0\nmov r8d, eax\nshr r8d, 1Fh\nadd r8d, eax\nsar r8d, 1\ncmp eax, 1\njle short loc_12D9\nlea rdx, [rcx+rdx-1]\nmov eax, 0\nloc_12BE:\nmovzx esi, byte ptr [rcx+rax]\nmovzx edi, byte ptr [rdx]\nmov [rcx+rax], dil\nmov [rdx], sil\nadd rax, 1\nsub rdx, 1\ncmp r8d, eax\njg short loc_12BE\nloc_12D9:\nmov rax, [rsp+18h+var_10]\nsub rax, fs:28h\njnz short loc_130F\nmov rax, rcx\nadd rsp, 10h\npop rbx\nretn\nloc_12F2:\nmov edi, 21h ; '!'; size\ncall _malloc\nmov rcx, rax\nloc_12FF:\nmov byte ptr [rcx], 30h ; '0'\nmov eax, 1\nloc_1307:\ncdqe\nmov byte ptr [rcx+rax], 0\njmp short loc_12D9\nloc_130F:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_BYTE *__fastcall sub_11E9(unsigned int a1)\n{\n char v1; // al\n _BYTE *v2; // rdx\n int v3; // ebx\n _BYTE *v4; // rcx\n __int64 v5; // rdx\n int v6; // eax\n int v7; // esi\n int v8; // eax\n int v9; // r8d\n _BYTE *v10; // rdx\n __int64 v11; // rax\n char v12; // si\n _BYTE v14[6]; // [rsp+2h] [rbp-16h] BYREF\n unsigned __int64 v15; // [rsp+8h] [rbp-10h]\n\n v15 = __readfsqword(0x28u);\n __sprintf_chk(v14, 2LL, 6LL, &unk_2004, a1);\n v1 = v14[0];\n if ( !v14[0] )\n {\n v4 = malloc(0x21uLL);\nLABEL_12:\n *v4 = 48;\n v6 = 1;\n goto LABEL_13;\n }\n v2 = v14;\n v3 = 0;\n do\n {\n v3 = v3 + v1 - 48;\n v1 = *++v2;\n }\n while ( *v2 );\n v4 = malloc(0x21uLL);\n if ( !v3 )\n goto LABEL_12;\n v5 = 1LL;\n v6 = 0;\n if ( v3 <= 0 )\n {\nLABEL_13:\n v4[v6] = 0;\n return v4;\n }\n do\n {\n v4[v5 - 1] = v3 % 2 + 48;\n v7 = v3;\n v3 /= 2;\n v8 = v5++;\n }\n while ( v7 > 1 );\n v4[v8] = 0;\n v9 = v8 / 2;\n if ( v8 > 1 )\n {\n v10 = &v4[v8 - 1];\n v11 = 0LL;\n do\n {\n v12 = v4[v11];\n v4[v11] = *v10;\n *v10 = v12;\n ++v11;\n --v10;\n }\n while ( v9 > (int)v11 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_11E9(unsigned int a1) {\n char v1;\n uint8_t *v2;\n int v3;\n uint8_t *v4;\n long long v5;\n int v6;\n int v7;\n int v8;\n int v9;\n uint8_t *v10;\n long long v11;\n char v12;\n uint8_t v14[6];\n unsigned long long v15;\n v15 = __readfsqword(40u);\n __sprintf_chk(v14, 2LL, 6LL, &unk_2004, a1);\n v1 = v14[0];\n if (!v14[0]) {\n v4 = malloc(33uLL);\n LABEL_12:\n *v4 = 48;\n v6 = 1;\n goto LABEL_13;\n }\n v2 = v14;\n v3 = 0;\n do {\n v3 = v3 + v1 - 48;\n v1 = *++v2;\n } while (*v2);\n v4 = malloc(33uLL);\n if (!v3) goto LABEL_12;\n v5 = 1LL;\n v6 = 0;\n if (v3 <= 0) {\n LABEL_13:\n v4[v6] = 0;\n return v4;\n }\n do {\n v4[v5 - 1] = v3 % 2 + 48;\n v7 = v3;\n v3 /= 2;\n v8 = v5++;\n } while (v7 > 1);\n v4[v8] = 0;\n v9 = v8 / 2;\n if (v8 > 1) {\n v10 = &v4[v8 - 1];\n v11 = 0LL;\n do {\n v12 = v4[v11];\n v4[v11] = *v10;\n *v10 = v12;\n ++v11;\n --v10;\n } while (v9 > (int)v11);\n }\n return v4;\n}", + "ida_pseudo_norm": "uint8_t *func0(unsigned int a1) {\n char v1;\n uint8_t *v2;\n int v3;\n uint8_t *v4;\n long long v5;\n int v6;\n int v7;\n int v8;\n int v9;\n uint8_t *v10;\n long long v11;\n char v12;\n uint8_t v14[6];\n unsigned long long v15;\n v15 = __readfsqword(40u);\n __sprintf_chk(v14, 2LL, 6LL, &unk_2004, a1);\n v1 = v14[0];\n if (!v14[0]) {\n v4 = malloc(33uLL);\n LABEL_12:\n *v4 = 48;\n v6 = 1;\n goto LABEL_13;\n }\n v2 = v14;\n v3 = 0;\n do {\n v3 = v3 + v1 - 48;\n v1 = *++v2;\n } while (*v2);\n v4 = malloc(33uLL);\n if (!v3) goto LABEL_12;\n v5 = 1LL;\n v6 = 0;\n if (v3 <= 0) {\n LABEL_13:\n v4[v6] = 0;\n return v4;\n }\n do {\n v4[v5 - 1] = v3 % 2 + 48;\n v7 = v3;\n v3 /= 2;\n v8 = v5++;\n } while (v7 > 1);\n v4[v8] = 0;\n v9 = v8 / 2;\n if (v8 > 1) {\n v10 = &v4[v8 - 1];\n v11 = 0LL;\n do {\n v12 = v4[v11];\n v4[v11] = *v10;\n *v10 = v12;\n ++v11;\n --v10;\n } while (v9 > (int)v11);\n }\n return v4;\n}" + }, + { + "index": "HumanEval-C-84", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "char* func0(int N) {\n char str[6];\n sprintf(str, \"%d\", N);\n int sum = 0;\n for (int i = 0; str[i] != '\\0'; i++) sum += str[i] - '0';\n char* bi = malloc(33);\n int index = 0;\n if (sum == 0) {\n bi[index++] = '0';\n } else {\n while (sum > 0) {\n bi[index++] = (sum % 2) + '0';\n sum /= 2;\n }\n }\n bi[index] = '\\0';\n for (int i = 0; i < index / 2; i++) {\n char temp = bi[i];\n bi[i] = bi[index - i - 1];\n bi[index - i - 1] = temp;\n }\n return bi;\n}", + "test": "#include \n#include \n\nint main() {\n char* result;\n\n result = func0(1000);\n assert(strcmp(result, \"1\") == 0);\n free(result);\n\n result = func0(150);\n assert(strcmp(result, \"110\") == 0);\n free(result);\n\n result = func0(147);\n assert(strcmp(result, \"1100\") == 0);\n free(result);\n\n result = func0(333);\n assert(strcmp(result, \"1001\") == 0);\n free(result);\n\n result = func0(963);\n assert(strcmp(result, \"10010\") == 0);\n free(result);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbx\nmov r8d, edi\nlea rcx, unk_2004\nmov edx, 6\nmov esi, 2\nsub rsp, 10h\nmov rax, fs:28h\nmov [rsp+18h+var_10], rax\nxor eax, eax\nlea rbx, [rsp+18h+var_16]\nmov rdi, rbx\ncall ___sprintf_chk\nmovsx eax, [rsp+18h+var_16]\ntest al, al\njz loc_1438\nmov rdx, rbx\nxor ebx, ebx\nnop dword ptr [rax+00h]\nloc_13B0:\nadd rdx, 1\nlea ebx, [rbx+rax-30h]\nmovsx eax, byte ptr [rdx]\ntest al, al\njnz short loc_13B0\nmov edi, 21h ; '!'; size\ncall _malloc\ntest ebx, ebx\njz short loc_1442\nmov edx, 1\njle loc_1460\nnop dword ptr [rax+rax+00000000h]\nloc_13E0:\nmov ecx, ebx\nmov r8, rdx\nand ecx, 1\nadd ecx, 30h ; '0'\nmov [rax+rdx-1], cl\nadd rdx, 1\nsar ebx, 1\njnz short loc_13E0\nmovsxd rcx, r8d\nsar r8d, 1\nmov byte ptr [rax+rcx], 0\njz short loc_144A\nmovsxd r8, r8d\nmov rdx, rax\nlea rcx, [rax+rcx-1]\nadd r8, rax\nnop dword ptr [rax+00000000h]\nloc_1418:\nmovzx edi, byte ptr [rcx]\nmovzx esi, byte ptr [rdx]\nadd rdx, 1\nsub rcx, 1\nmov [rdx-1], dil\nmov [rcx+1], sil\ncmp rdx, r8\njnz short loc_1418\njmp short loc_144A\nloc_1438:\nmov edi, 21h ; '!'; size\ncall _malloc\nloc_1442:\nmov edx, 30h ; '0'\nmov [rax], dx\nloc_144A:\nmov rdx, [rsp+18h+var_10]\nsub rdx, fs:28h\njnz short loc_1465\nadd rsp, 10h\npop rbx\nretn\nloc_1460:\nmov byte ptr [rax], 0\njmp short loc_144A\nloc_1465:\ncall ___stack_chk_fail", + "ida_pseudo": "_WORD *__fastcall func0(unsigned int a1)\n{\n int v1; // eax\n _BYTE *v2; // rdx\n int v3; // ebx\n _WORD *result; // rax\n __int64 v5; // rdx\n int v6; // r8d\n __int64 v7; // rcx\n int v8; // r8d\n char *v9; // rdx\n char *v10; // rcx\n char *v11; // r8\n char v12; // di\n char v13; // si\n _BYTE v14[6]; // [rsp+2h] [rbp-16h] BYREF\n unsigned __int64 v15; // [rsp+8h] [rbp-10h]\n\n v15 = __readfsqword(0x28u);\n __sprintf_chk(v14, 2LL, 6LL, &unk_2004, a1);\n v1 = v14[0];\n if ( !v14[0] )\n {\n result = malloc(0x21uLL);\nLABEL_12:\n *result = 48;\n return result;\n }\n v2 = v14;\n v3 = 0;\n do\n {\n ++v2;\n v3 = v3 + v1 - 48;\n v1 = (char)*v2;\n }\n while ( *v2 );\n result = malloc(0x21uLL);\n if ( !v3 )\n goto LABEL_12;\n v5 = 1LL;\n if ( v3 <= 0 )\n {\n *(_BYTE *)result = 0;\n }\n else\n {\n do\n {\n v6 = v5;\n *((_BYTE *)result + v5++ - 1) = (v3 & 1) + 48;\n v3 >>= 1;\n }\n while ( v3 );\n v7 = v6;\n v8 = v6 >> 1;\n *((_BYTE *)result + v7) = 0;\n if ( v8 )\n {\n v9 = (char *)result;\n v10 = (char *)result + v7 - 1;\n v11 = (char *)result + v8;\n do\n {\n v12 = *v10;\n v13 = *v9++;\n --v10;\n *(v9 - 1) = v12;\n v10[1] = v13;\n }\n while ( v9 != v11 );\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1360:\nendbr64\npush rbx\nmov r8d, edi\nlea rcx, unk_2004\nmov edx, 6\nmov esi, 2\nsub rsp, 10h\nmov rax, fs:28h\nmov [rsp+18h+var_10], rax\nxor eax, eax\nlea rbx, [rsp+18h+var_16]\nmov rdi, rbx\ncall ___sprintf_chk\nmovsx eax, [rsp+18h+var_16]\ntest al, al\njz loc_1438\nmov rdx, rbx\nxor ebx, ebx\nnop dword ptr [rax+00h]\nloc_13B0:\nadd rdx, 1\nlea ebx, [rbx+rax-30h]\nmovsx eax, byte ptr [rdx]\ntest al, al\njnz short loc_13B0\nmov edi, 21h ; '!'; size\ncall _malloc\ntest ebx, ebx\njz short loc_1442\nmov edx, 1\njle loc_1460\nnop dword ptr [rax+rax+00000000h]\nloc_13E0:\nmov ecx, ebx\nmov r8, rdx\nand ecx, 1\nadd ecx, 30h ; '0'\nmov [rax+rdx-1], cl\nadd rdx, 1\nsar ebx, 1\njnz short loc_13E0\nmovsxd rcx, r8d\nsar r8d, 1\nmov byte ptr [rax+rcx], 0\njz short loc_144A\nmovsxd r8, r8d\nmov rdx, rax\nlea rcx, [rax+rcx-1]\nadd r8, rax\nnop dword ptr [rax+00000000h]\nloc_1418:\nmovzx edi, byte ptr [rcx]\nmovzx esi, byte ptr [rdx]\nadd rdx, 1\nsub rcx, 1\nmov [rdx-1], dil\nmov [rcx+1], sil\ncmp rdx, r8\njnz short loc_1418\njmp short loc_144A\nloc_1438:\nmov edi, 21h ; '!'; size\ncall _malloc\nloc_1442:\nmov edx, 30h ; '0'\nmov [rax], dx\nloc_144A:\nmov rdx, [rsp+18h+var_10]\nsub rdx, fs:28h\njnz short loc_1465\nadd rsp, 10h\npop rbx\nretn\nloc_1460:\nmov byte ptr [rax], 0\njmp short loc_144A\nloc_1465:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_WORD *__fastcall sub_1360(unsigned int a1)\n{\n int v1; // eax\n _BYTE *v2; // rdx\n int v3; // ebx\n _WORD *result; // rax\n __int64 v5; // rdx\n int v6; // r8d\n __int64 v7; // rcx\n int v8; // r8d\n char *v9; // rdx\n char *v10; // rcx\n char *v11; // r8\n char v12; // di\n char v13; // si\n _BYTE v14[6]; // [rsp+2h] [rbp-16h] BYREF\n unsigned __int64 v15; // [rsp+8h] [rbp-10h]\n\n v15 = __readfsqword(0x28u);\n __sprintf_chk(v14, 2LL, 6LL, &unk_2004, a1);\n v1 = v14[0];\n if ( !v14[0] )\n {\n result = malloc(0x21uLL);\nLABEL_12:\n *result = 48;\n return result;\n }\n v2 = v14;\n v3 = 0;\n do\n {\n ++v2;\n v3 = v3 + v1 - 48;\n v1 = (char)*v2;\n }\n while ( *v2 );\n result = malloc(0x21uLL);\n if ( !v3 )\n goto LABEL_12;\n v5 = 1LL;\n if ( v3 <= 0 )\n {\n *(_BYTE *)result = 0;\n }\n else\n {\n do\n {\n v6 = v5;\n *((_BYTE *)result + v5++ - 1) = (v3 & 1) + 48;\n v3 >>= 1;\n }\n while ( v3 );\n v7 = v6;\n v8 = v6 >> 1;\n *((_BYTE *)result + v7) = 0;\n if ( v8 )\n {\n v9 = (char *)result;\n v10 = (char *)result + v7 - 1;\n v11 = (char *)result + v8;\n do\n {\n v12 = *v10;\n v13 = *v9++;\n --v10;\n *(v9 - 1) = v12;\n v10[1] = v13;\n }\n while ( v9 != v11 );\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned short *sub_1360(unsigned int a1) {\n int v1;\n uint8_t *v2;\n int v3;\n unsigned short *result;\n long long v5;\n int v6;\n long long v7;\n int v8;\n char *v9;\n char *v10;\n char *v11;\n char v12;\n char v13;\n uint8_t v14[6];\n unsigned long long v15;\n v15 = __readfsqword(40u);\n __sprintf_chk(v14, 2LL, 6LL, &unk_2004, a1);\n v1 = v14[0];\n if (!v14[0]) {\n result = malloc(33uLL);\n LABEL_12:\n *result = 48;\n return result;\n }\n v2 = v14;\n v3 = 0;\n do {\n ++v2;\n v3 = v3 + v1 - 48;\n v1 = (char)*v2;\n } while (*v2);\n result = malloc(33uLL);\n if (!v3) goto LABEL_12;\n v5 = 1LL;\n if (v3 <= 0) {\n *(uint8_t *)result = 0;\n } else {\n do {\n v6 = v5;\n *((uint8_t *)result + v5++ - 1) = (v3 & 1) + 48;\n v3 >>= 1;\n } while (v3);\n v7 = v6;\n v8 = v6 >> 1;\n *((uint8_t *)result + v7) = 0;\n if (v8) {\n v9 = (char *)result;\n v10 = (char *)result + v7 - 1;\n v11 = (char *)result + v8;\n do {\n v12 = *v10;\n v13 = *v9++;\n --v10;\n *(v9 - 1) = v12;\n v10[1] = v13;\n } while (v9 != v11);\n }\n }\n return result;\n}", + "ida_pseudo_norm": "unsigned short *func0(unsigned int a1) {\n int v1;\n uint8_t *v2;\n int v3;\n unsigned short *result;\n long long v5;\n int v6;\n long long v7;\n int v8;\n char *v9;\n char *v10;\n char *v11;\n char v12;\n char v13;\n uint8_t v14[6];\n unsigned long long v15;\n v15 = __readfsqword(40u);\n __sprintf_chk(v14, 2LL, 6LL, &unk_2004, a1);\n v1 = v14[0];\n if (!v14[0]) {\n result = malloc(33uLL);\n LABEL_12:\n *result = 48;\n return result;\n }\n v2 = v14;\n v3 = 0;\n do {\n ++v2;\n v3 = v3 + v1 - 48;\n v1 = (char)*v2;\n } while (*v2);\n result = malloc(33uLL);\n if (!v3) goto LABEL_12;\n v5 = 1LL;\n if (v3 <= 0) {\n *(uint8_t *)result = 0;\n } else {\n do {\n v6 = v5;\n *((uint8_t *)result + v5++ - 1) = (v3 & 1) + 48;\n v3 >>= 1;\n } while (v3);\n v7 = v6;\n v8 = v6 >> 1;\n *((uint8_t *)result + v7) = 0;\n if (v8) {\n v9 = (char *)result;\n v10 = (char *)result + v7 - 1;\n v11 = (char *)result + v8;\n do {\n v12 = *v10;\n v13 = *v9++;\n --v10;\n *(v9 - 1) = v12;\n v10[1] = v13;\n } while (v9 != v11);\n }\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-84", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "char* func0(int N) {\n char str[6];\n sprintf(str, \"%d\", N);\n int sum = 0;\n for (int i = 0; str[i] != '\\0'; i++) sum += str[i] - '0';\n char* bi = malloc(33);\n int index = 0;\n if (sum == 0) {\n bi[index++] = '0';\n } else {\n while (sum > 0) {\n bi[index++] = (sum % 2) + '0';\n sum /= 2;\n }\n }\n bi[index] = '\\0';\n for (int i = 0; i < index / 2; i++) {\n char temp = bi[i];\n bi[i] = bi[index - i - 1];\n bi[index - i - 1] = temp;\n }\n return bi;\n}", + "test": "#include \n#include \n\nint main() {\n char* result;\n\n result = func0(1000);\n assert(strcmp(result, \"1\") == 0);\n free(result);\n\n result = func0(150);\n assert(strcmp(result, \"110\") == 0);\n free(result);\n\n result = func0(147);\n assert(strcmp(result, \"1100\") == 0);\n free(result);\n\n result = func0(333);\n assert(strcmp(result, \"1001\") == 0);\n free(result);\n\n result = func0(963);\n assert(strcmp(result, \"10010\") == 0);\n free(result);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbx\nmov r8d, edi\nlea rcx, unk_2004\nmov edx, 6\nmov esi, 2\nsub rsp, 10h\nmov rax, fs:28h\nmov [rsp+18h+var_10], rax\nxor eax, eax\nlea rdi, [rsp+18h+var_16]\ncall ___sprintf_chk\nmovsx ebx, [rsp+18h+var_16]\ntest bl, bl\njz loc_1450\nmovsx eax, [rsp+18h+var_15]\nsub ebx, 30h ; '0'\ntest al, al\njz short loc_13DB\nlea ebx, [rbx+rax-30h]\nmovsx eax, [rsp+18h+var_14]\ntest al, al\njz short loc_13DB\nlea ebx, [rbx+rax-30h]\nmovsx eax, [rsp+18h+var_13]\ntest al, al\njz short loc_13DB\nlea ebx, [rbx+rax-30h]\nmovsx eax, [rsp+18h+var_12]\ntest al, al\njz short loc_13DB\nlea ebx, [rbx+rax-30h]\nloc_13DB:\nmov edi, 21h ; '!'; size\ncall _malloc\ntest ebx, ebx\njz short loc_145A\nmov edx, 1\njle loc_1478\nnop dword ptr [rax+00h]\nloc_13F8:\nmov ecx, ebx\nmov r8, rdx\nand ecx, 1\nadd ecx, 30h ; '0'\nmov [rax+rdx-1], cl\nadd rdx, 1\nsar ebx, 1\njnz short loc_13F8\nmovsxd rcx, r8d\nsar r8d, 1\nmov byte ptr [rax+rcx], 0\njz short loc_1462\nmovsxd r8, r8d\nmov rdx, rax\nlea rcx, [rax+rcx-1]\nadd r8, rax\nnop dword ptr [rax+00000000h]\nloc_1430:\nmovzx edi, byte ptr [rcx]\nmovzx esi, byte ptr [rdx]\nadd rdx, 1\nsub rcx, 1\nmov [rdx-1], dil\nmov [rcx+1], sil\ncmp r8, rdx\njnz short loc_1430\njmp short loc_1462\nloc_1450:\nmov edi, 21h ; '!'; size\ncall _malloc\nloc_145A:\nmov edx, 30h ; '0'\nmov [rax], dx\nloc_1462:\nmov rdx, [rsp+18h+var_10]\nsub rdx, fs:28h\njnz short loc_147D\nadd rsp, 10h\npop rbx\nretn\nloc_1478:\nmov byte ptr [rax], 0\njmp short loc_1462\nloc_147D:\ncall ___stack_chk_fail", + "ida_pseudo": "_WORD *__fastcall func0(unsigned int a1)\n{\n int v1; // ebx\n _WORD *result; // rax\n __int64 v3; // rdx\n int v4; // r8d\n __int64 v5; // rcx\n int v6; // r8d\n char *v7; // rdx\n char *v8; // rcx\n char *v9; // r8\n char v10; // di\n char v11; // si\n char v12; // [rsp+2h] [rbp-16h] BYREF\n char v13; // [rsp+3h] [rbp-15h]\n char v14; // [rsp+4h] [rbp-14h]\n char v15; // [rsp+5h] [rbp-13h]\n char v16; // [rsp+6h] [rbp-12h]\n unsigned __int64 v17; // [rsp+8h] [rbp-10h]\n\n v17 = __readfsqword(0x28u);\n __sprintf_chk(&v12, 2LL, 6LL, &unk_2004, a1);\n if ( !v12 )\n {\n result = malloc(0x21uLL);\nLABEL_15:\n *result = 48;\n return result;\n }\n v1 = v12 - 48;\n if ( v13 )\n {\n v1 = v1 + v13 - 48;\n if ( v14 )\n {\n v1 = v1 + v14 - 48;\n if ( v15 )\n {\n v1 = v1 + v15 - 48;\n if ( v16 )\n v1 = v1 + v16 - 48;\n }\n }\n }\n result = malloc(0x21uLL);\n if ( !v1 )\n goto LABEL_15;\n v3 = 1LL;\n if ( v1 <= 0 )\n {\n *(_BYTE *)result = 0;\n }\n else\n {\n do\n {\n v4 = v3;\n *((_BYTE *)result + v3++ - 1) = (v1 & 1) + 48;\n v1 >>= 1;\n }\n while ( v1 );\n v5 = v4;\n v6 = v4 >> 1;\n *((_BYTE *)result + v5) = 0;\n if ( v6 )\n {\n v7 = (char *)result;\n v8 = (char *)result + v5 - 1;\n v9 = (char *)result + v6;\n do\n {\n v10 = *v8;\n v11 = *v7++;\n --v8;\n *(v7 - 1) = v10;\n v8[1] = v11;\n }\n while ( v9 != v7 );\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1360:\nendbr64\npush rbx\nmov r8d, edi\nlea rcx, unk_2004\nmov edx, 6\nmov esi, 2\nsub rsp, 10h\nmov rax, fs:28h\nmov [rsp+18h+var_10], rax\nxor eax, eax\nlea rdi, [rsp+18h+var_16]\ncall ___sprintf_chk\nmovsx ebx, [rsp+18h+var_16]\ntest bl, bl\njz loc_1450\nmovsx eax, [rsp+18h+var_15]\nsub ebx, 30h ; '0'\ntest al, al\njz short loc_13DB\nlea ebx, [rbx+rax-30h]\nmovsx eax, [rsp+18h+var_14]\ntest al, al\njz short loc_13DB\nlea ebx, [rbx+rax-30h]\nmovsx eax, [rsp+18h+var_13]\ntest al, al\njz short loc_13DB\nlea ebx, [rbx+rax-30h]\nmovsx eax, [rsp+18h+var_12]\ntest al, al\njz short loc_13DB\nlea ebx, [rbx+rax-30h]\nloc_13DB:\nmov edi, 21h ; '!'; size\ncall _malloc\ntest ebx, ebx\njz short loc_145A\nmov edx, 1\njle loc_1478\nnop dword ptr [rax+00h]\nloc_13F8:\nmov ecx, ebx\nmov r8, rdx\nand ecx, 1\nadd ecx, 30h ; '0'\nmov [rax+rdx-1], cl\nadd rdx, 1\nsar ebx, 1\njnz short loc_13F8\nmovsxd rcx, r8d\nsar r8d, 1\nmov byte ptr [rax+rcx], 0\njz short loc_1462\nmovsxd r8, r8d\nmov rdx, rax\nlea rcx, [rax+rcx-1]\nadd r8, rax\nnop dword ptr [rax+00000000h]\nloc_1430:\nmovzx edi, byte ptr [rcx]\nmovzx esi, byte ptr [rdx]\nadd rdx, 1\nsub rcx, 1\nmov [rdx-1], dil\nmov [rcx+1], sil\ncmp r8, rdx\njnz short loc_1430\njmp short loc_1462\nloc_1450:\nmov edi, 21h ; '!'; size\ncall _malloc\nloc_145A:\nmov edx, 30h ; '0'\nmov [rax], dx\nloc_1462:\nmov rdx, [rsp+18h+var_10]\nsub rdx, fs:28h\njnz short loc_147D\nadd rsp, 10h\npop rbx\nretn\nloc_1478:\nmov byte ptr [rax], 0\njmp short loc_1462\nloc_147D:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_WORD *__fastcall sub_1360(unsigned int a1)\n{\n int v1; // ebx\n _WORD *result; // rax\n __int64 v3; // rdx\n int v4; // r8d\n __int64 v5; // rcx\n int v6; // r8d\n char *v7; // rdx\n char *v8; // rcx\n char *v9; // r8\n char v10; // di\n char v11; // si\n char v12; // [rsp+2h] [rbp-16h] BYREF\n char v13; // [rsp+3h] [rbp-15h]\n char v14; // [rsp+4h] [rbp-14h]\n char v15; // [rsp+5h] [rbp-13h]\n char v16; // [rsp+6h] [rbp-12h]\n unsigned __int64 v17; // [rsp+8h] [rbp-10h]\n\n v17 = __readfsqword(0x28u);\n __sprintf_chk(&v12, 2LL, 6LL, &unk_2004, a1);\n if ( !v12 )\n {\n result = malloc(0x21uLL);\nLABEL_15:\n *result = 48;\n return result;\n }\n v1 = v12 - 48;\n if ( v13 )\n {\n v1 = v1 + v13 - 48;\n if ( v14 )\n {\n v1 = v1 + v14 - 48;\n if ( v15 )\n {\n v1 = v1 + v15 - 48;\n if ( v16 )\n v1 = v1 + v16 - 48;\n }\n }\n }\n result = malloc(0x21uLL);\n if ( !v1 )\n goto LABEL_15;\n v3 = 1LL;\n if ( v1 <= 0 )\n {\n *(_BYTE *)result = 0;\n }\n else\n {\n do\n {\n v4 = v3;\n *((_BYTE *)result + v3++ - 1) = (v1 & 1) + 48;\n v1 >>= 1;\n }\n while ( v1 );\n v5 = v4;\n v6 = v4 >> 1;\n *((_BYTE *)result + v5) = 0;\n if ( v6 )\n {\n v7 = (char *)result;\n v8 = (char *)result + v5 - 1;\n v9 = (char *)result + v6;\n do\n {\n v10 = *v8;\n v11 = *v7++;\n --v8;\n *(v7 - 1) = v10;\n v8[1] = v11;\n }\n while ( v9 != v7 );\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned short *sub_1360(unsigned int a1) {\n int v1;\n unsigned short *result;\n long long v3;\n int v4;\n long long v5;\n int v6;\n char *v7;\n char *v8;\n char *v9;\n char v10;\n char v11;\n char v12;\n char v13;\n char v14;\n char v15;\n char v16;\n unsigned long long v17;\n v17 = __readfsqword(40u);\n __sprintf_chk(&v12, 2LL, 6LL, &unk_2004, a1);\n if (!v12) {\n result = malloc(33uLL);\n LABEL_15:\n *result = 48;\n return result;\n }\n v1 = v12 - 48;\n if (v13) {\n v1 = v1 + v13 - 48;\n if (v14) {\n v1 = v1 + v14 - 48;\n if (v15) {\n v1 = v1 + v15 - 48;\n if (v16) v1 = v1 + v16 - 48;\n }\n }\n }\n result = malloc(33uLL);\n if (!v1) goto LABEL_15;\n v3 = 1LL;\n if (v1 <= 0) {\n *(uint8_t *)result = 0;\n } else {\n do {\n v4 = v3;\n *((uint8_t *)result + v3++ - 1) = (v1 & 1) + 48;\n v1 >>= 1;\n } while (v1);\n v5 = v4;\n v6 = v4 >> 1;\n *((uint8_t *)result + v5) = 0;\n if (v6) {\n v7 = (char *)result;\n v8 = (char *)result + v5 - 1;\n v9 = (char *)result + v6;\n do {\n v10 = *v8;\n v11 = *v7++;\n --v8;\n *(v7 - 1) = v10;\n v8[1] = v11;\n } while (v9 != v7);\n }\n }\n return result;\n}", + "ida_pseudo_norm": "unsigned short *func0(unsigned int a1) {\n int v1;\n unsigned short *result;\n long long v3;\n int v4;\n long long v5;\n int v6;\n char *v7;\n char *v8;\n char *v9;\n char v10;\n char v11;\n char v12;\n char v13;\n char v14;\n char v15;\n char v16;\n unsigned long long v17;\n v17 = __readfsqword(40u);\n __sprintf_chk(&v12, 2LL, 6LL, &unk_2004, a1);\n if (!v12) {\n result = malloc(33uLL);\n LABEL_15:\n *result = 48;\n return result;\n }\n v1 = v12 - 48;\n if (v13) {\n v1 = v1 + v13 - 48;\n if (v14) {\n v1 = v1 + v14 - 48;\n if (v15) {\n v1 = v1 + v15 - 48;\n if (v16) v1 = v1 + v16 - 48;\n }\n }\n }\n result = malloc(33uLL);\n if (!v1) goto LABEL_15;\n v3 = 1LL;\n if (v1 <= 0) {\n *(uint8_t *)result = 0;\n } else {\n do {\n v4 = v3;\n *((uint8_t *)result + v3++ - 1) = (v1 & 1) + 48;\n v1 >>= 1;\n } while (v1);\n v5 = v4;\n v6 = v4 >> 1;\n *((uint8_t *)result + v5) = 0;\n if (v6) {\n v7 = (char *)result;\n v8 = (char *)result + v5 - 1;\n v9 = (char *)result + v6;\n do {\n v10 = *v8;\n v11 = *v7++;\n --v8;\n *(v7 - 1) = v10;\n v8[1] = v11;\n } while (v9 != v7);\n }\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-85", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int lst[], int size) {\n int sum = 0;\n for (int i = 0; i * 2 + 1 < size; i++)\n if (lst[i * 2 + 1] % 2 == 0) sum += lst[i * 2 + 1];\n return sum;\n}", + "test": "#include \n\nint main() {\n int array1[] = {4, 88};\n assert(func0(array1, sizeof(array1) / sizeof(array1[0])) == 88);\n\n int array2[] = {4, 5, 6, 7, 2, 122};\n assert(func0(array2, sizeof(array2) / sizeof(array2[0])) == 122);\n\n int array3[] = {4, 0, 6, 7};\n assert(func0(array3, sizeof(array3) / sizeof(array3[0])) == 0);\n\n int array4[] = {4, 4, 6, 8};\n assert(func0(array4, sizeof(array4) / sizeof(array4[0])) == 12);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11CE\nloc_1188:\nmov eax, [rbp+var_4]\nadd eax, eax\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njnz short loc_11CA\nmov eax, [rbp+var_4]\nadd eax, eax\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nloc_11CA:\nadd [rbp+var_4], 1\nloc_11CE:\nmov eax, [rbp+var_4]\nadd eax, eax\nadd eax, 1\ncmp [rbp+var_1C], eax\njg short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; a2 > 2 * i + 1; ++i )\n {\n if ( (*(_DWORD *)(4 * (2 * i + 1LL) + a1) & 1) == 0 )\n v3 += *(_DWORD *)(4 * (2 * i + 1LL) + a1);\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11CE\nloc_1188:\nmov eax, [rbp+var_4]\nadd eax, eax\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njnz short loc_11CA\nmov eax, [rbp+var_4]\nadd eax, eax\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nloc_11CA:\nadd [rbp+var_4], 1\nloc_11CE:\nmov eax, [rbp+var_4]\nadd eax, eax\nadd eax, 1\ncmp [rbp+var_1C], eax\njg short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; a2 > 2 * i + 1; ++i )\n {\n if ( (*(_DWORD *)(4 * (2 * i + 1LL) + a1) & 1) == 0 )\n v3 += *(_DWORD *)(4 * (2 * i + 1LL) + a1);\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; a2 > 2 * i + 1; ++i) {\n if ((*(uint32_t *)(4 * (2 * i + 1LL) + a1) & 1) == 0)\n v3 += *(uint32_t *)(4 * (2 * i + 1LL) + a1);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; a2 > 2 * i + 1; ++i) {\n if ((*(uint32_t *)(4 * (2 * i + 1LL) + a1) & 1) == 0)\n v3 += *(uint32_t *)(4 * (2 * i + 1LL) + a1);\n }\n return v3;\n}" + }, + { + "index": "HumanEval-C-85", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int lst[], int size) {\n int sum = 0;\n for (int i = 0; i * 2 + 1 < size; i++)\n if (lst[i * 2 + 1] % 2 == 0) sum += lst[i * 2 + 1];\n return sum;\n}", + "test": "#include \n\nint main() {\n int array1[] = {4, 88};\n assert(func0(array1, sizeof(array1) / sizeof(array1[0])) == 88);\n\n int array2[] = {4, 5, 6, 7, 2, 122};\n assert(func0(array2, sizeof(array2) / sizeof(array2[0])) == 122);\n\n int array3[] = {4, 0, 6, 7};\n assert(func0(array3, sizeof(array3) / sizeof(array3[0])) == 0);\n\n int array4[] = {4, 4, 6, 8};\n assert(func0(array4, sizeof(array4) / sizeof(array4[0])) == 12);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ncmp esi, 1\njle short loc_119E\nlea rax, [rdi+4]\nsub esi, 2\nshr esi, 1\nmov esi, esi\nlea rdi, [rdi+rsi*8+0Ch]\nmov edx, 0\nloc_1187:\nmov ecx, [rax]\nlea esi, [rdx+rcx]\ntest cl, 1\ncmovz edx, esi\nadd rax, 8\ncmp rax, rdi\njnz short loc_1187\nloc_119B:\nmov eax, edx\nretn\nloc_119E:\nmov edx, 0\njmp short loc_119B", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n _DWORD *v2; // rax\n __int64 v3; // rdi\n unsigned int v4; // edx\n\n if ( a2 <= 1 )\n {\n return 0;\n }\n else\n {\n v2 = (_DWORD *)(a1 + 4);\n v3 = a1 + 8LL * ((unsigned int)(a2 - 2) >> 1) + 12;\n v4 = 0;\n do\n {\n if ( (*v2 & 1) == 0 )\n v4 += *v2;\n v2 += 2;\n }\n while ( v2 != (_DWORD *)v3 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ncmp esi, 1\njle short loc_119E\nlea rax, [rdi+4]\nsub esi, 2\nshr esi, 1\nmov esi, esi\nlea rdi, [rdi+rsi*8+0Ch]\nmov edx, 0\nloc_1187:\nmov ecx, [rax]\nlea esi, [rdx+rcx]\ntest cl, 1\ncmovz edx, esi\nadd rax, 8\ncmp rax, rdi\njnz short loc_1187\nloc_119B:\nmov eax, edx\nretn\nloc_119E:\nmov edx, 0\njmp short loc_119B", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n _DWORD *v2; // rax\n __int64 v3; // rdi\n unsigned int v4; // edx\n\n if ( a2 <= 1 )\n {\n return 0;\n }\n else\n {\n v2 = (_DWORD *)(a1 + 4);\n v3 = a1 + 8LL * ((unsigned int)(a2 - 2) >> 1) + 12;\n v4 = 0;\n do\n {\n if ( (*v2 & 1) == 0 )\n v4 += *v2;\n v2 += 2;\n }\n while ( v2 != (_DWORD *)v3 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n uint32_t *v2;\n long long v3;\n unsigned int v4;\n if (a2 <= 1) {\n return 0;\n } else {\n v2 = (uint32_t *)(a1 + 4);\n v3 = a1 + 8LL * ((unsigned int)(a2 - 2) >> 1) + 12;\n v4 = 0;\n do {\n if ((*v2 & 1) == 0) v4 += *v2;\n v2 += 2;\n } while (v2 != (uint32_t *)v3);\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n uint32_t *v2;\n long long v3;\n unsigned int v4;\n if (a2 <= 1) {\n return 0;\n } else {\n v2 = (uint32_t *)(a1 + 4);\n v3 = a1 + 8LL * ((unsigned int)(a2 - 2) >> 1) + 12;\n v4 = 0;\n do {\n if ((*v2 & 1) == 0) v4 += *v2;\n v2 += 2;\n } while (v2 != (uint32_t *)v3);\n }\n return v4;\n}" + }, + { + "index": "HumanEval-C-85", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int lst[], int size) {\n int sum = 0;\n for (int i = 0; i * 2 + 1 < size; i++)\n if (lst[i * 2 + 1] % 2 == 0) sum += lst[i * 2 + 1];\n return sum;\n}", + "test": "#include \n\nint main() {\n int array1[] = {4, 88};\n assert(func0(array1, sizeof(array1) / sizeof(array1[0])) == 88);\n\n int array2[] = {4, 5, 6, 7, 2, 122};\n assert(func0(array2, sizeof(array2) / sizeof(array2[0])) == 122);\n\n int array3[] = {4, 0, 6, 7};\n assert(func0(array3, sizeof(array3) / sizeof(array3[0])) == 0);\n\n int array4[] = {4, 4, 6, 8};\n assert(func0(array4, sizeof(array4) / sizeof(array4[0])) == 12);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ncmp esi, 1\njle short loc_1300\nsub esi, 2\nlea rax, [rdi+4]\nxor edx, edx\nshr esi, 1\nlea rdi, [rdi+rsi*8+0Ch]\nnop dword ptr [rax+00000000h]\nloc_12E0:\nmov ecx, [rax]\nlea esi, [rdx+rcx]\nand ecx, 1\ncmovz edx, esi\nadd rax, 8\ncmp rdi, rax\njnz short loc_12E0\nmov eax, edx\nretn\nloc_1300:\nxor edx, edx\nmov eax, edx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n _DWORD *v2; // rax\n unsigned int v3; // edx\n __int64 v4; // rdi\n\n if ( a2 <= 1 )\n return 0LL;\n v2 = (_DWORD *)(a1 + 4);\n v3 = 0;\n v4 = a1 + 8LL * ((unsigned int)(a2 - 2) >> 1) + 12;\n do\n {\n if ( (*v2 & 1) == 0 )\n v3 += *v2;\n v2 += 2;\n }\n while ( (_DWORD *)v4 != v2 );\n return v3;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\ncmp esi, 1\njle short loc_1300\nsub esi, 2\nlea rax, [rdi+4]\nxor edx, edx\nshr esi, 1\nlea rdi, [rdi+rsi*8+0Ch]\nnop dword ptr [rax+00000000h]\nloc_12E0:\nmov ecx, [rax]\nlea esi, [rdx+rcx]\nand ecx, 1\ncmovz edx, esi\nadd rax, 8\ncmp rdi, rax\njnz short loc_12E0\nmov eax, edx\nretn\nloc_1300:\nxor edx, edx\nmov eax, edx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12C0(__int64 a1, int a2)\n{\n _DWORD *v2; // rax\n unsigned int v3; // edx\n __int64 v4; // rdi\n\n if ( a2 <= 1 )\n return 0LL;\n v2 = (_DWORD *)(a1 + 4);\n v3 = 0;\n v4 = a1 + 8LL * ((unsigned int)(a2 - 2) >> 1) + 12;\n do\n {\n if ( (*v2 & 1) == 0 )\n v3 += *v2;\n v2 += 2;\n }\n while ( (_DWORD *)v4 != v2 );\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12C0(long long a1, int a2) {\n uint32_t *v2;\n unsigned int v3;\n long long v4;\n if (a2 <= 1) return 0LL;\n v2 = (uint32_t *)(a1 + 4);\n v3 = 0;\n v4 = a1 + 8LL * ((unsigned int)(a2 - 2) >> 1) + 12;\n do {\n if ((*v2 & 1) == 0) v3 += *v2;\n v2 += 2;\n } while ((uint32_t *)v4 != v2);\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n uint32_t *v2;\n unsigned int v3;\n long long v4;\n if (a2 <= 1) return 0LL;\n v2 = (uint32_t *)(a1 + 4);\n v3 = 0;\n v4 = a1 + 8LL * ((unsigned int)(a2 - 2) >> 1) + 12;\n do {\n if ((*v2 & 1) == 0) v3 += *v2;\n v2 += 2;\n } while ((uint32_t *)v4 != v2);\n return v3;\n}" + }, + { + "index": "HumanEval-C-86", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char* func0(const char* s) {\n int len = strlen(s);\n char* out = malloc(len + 2);\n char current[51];\n int out_index = 0, current_index = 0;\n for (int i = 0; i <= len; i++) {\n if (s[i] == ' ' || s[i] == '\\0') {\n for (int j = 0; j < current_index - 1; j++) {\n for (int k = j + 1; k < current_index; k++) {\n if (current[j] > current[k]) {\n char temp = current[j];\n current[j] = current[k];\n current[k] = temp;\n }\n }\n }\n if (out_index > 0) out[out_index++] = ' ';\n for (int j = 0; j < current_index; j++) {\n out[out_index++] = current[j];\n }\n current_index = 0;\n } else {\n current[current_index++] = s[i];\n }\n }\n out[out_index] = '\\0';\n return out;\n}", + "test": "#include \n#include \n\nint main() {\n char* result;\n\n result = func0(\"Hi\");\n assert(strcmp(result, \"Hi\") == 0);\n free(result);\n\n result = func0(\"hello\");\n assert(strcmp(result, \"ehllo\") == 0);\n free(result);\n\n result = func0(\"number\");\n assert(strcmp(result, \"bemnru\") == 0);\n free(result);\n\n result = func0(\"abcd\");\n assert(strcmp(result, \"abcd\") == 0);\n free(result);\n\n result = func0(\"Hello World!!!\");\n assert(strcmp(result, \"Hello !!!Wdlor\") == 0);\n free(result);\n\n result = func0(\"\");\n assert(strcmp(result, \"\") == 0);\n free(result);\n\n result = func0(\"Hi. My name is Mister Robot. How are you?\");\n assert(strcmp(result, \".Hi My aemn is Meirst .Rboot How aer ?ouy\") == 0);\n free(result);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nadd rsp, 0FFFFFFFFFFFFFF80h\nmov [rbp+s], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4C], eax\nmov eax, [rbp+var_4C]\nadd eax, 2\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_48], rax\nmov [rbp+var_64], 0\nmov [rbp+var_60], 0\nmov [rbp+var_5C], 0\njmp loc_1362\nloc_1245:\nmov eax, [rbp+var_5C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njz short loc_1271\nmov eax, [rbp+var_5C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_133E\nloc_1271:\nmov [rbp+var_58], 0\njmp short loc_12DA\nloc_127A:\nmov eax, [rbp+var_58]\nadd eax, 1\nmov [rbp+var_54], eax\njmp short loc_12CE\nloc_1285:\nmov eax, [rbp+var_58]\ncdqe\nmovzx edx, [rbp+rax+var_40]\nmov eax, [rbp+var_54]\ncdqe\nmovzx eax, [rbp+rax+var_40]\ncmp dl, al\njle short loc_12CA\nmov eax, [rbp+var_58]\ncdqe\nmovzx eax, [rbp+rax+var_40]\nmov [rbp+var_65], al\nmov eax, [rbp+var_54]\ncdqe\nmovzx edx, [rbp+rax+var_40]\nmov eax, [rbp+var_58]\ncdqe\nmov [rbp+rax+var_40], dl\nmov eax, [rbp+var_54]\ncdqe\nmovzx edx, [rbp+var_65]\nmov [rbp+rax+var_40], dl\nloc_12CA:\nadd [rbp+var_54], 1\nloc_12CE:\nmov eax, [rbp+var_54]\ncmp eax, [rbp+var_60]\njl short loc_1285\nadd [rbp+var_58], 1\nloc_12DA:\nmov eax, [rbp+var_60]\nsub eax, 1\ncmp [rbp+var_58], eax\njl short loc_127A\ncmp [rbp+var_64], 0\njle short loc_1301\nmov eax, [rbp+var_64]\nlea edx, [rax+1]\nmov [rbp+var_64], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov byte ptr [rax], 20h ; ' '\nloc_1301:\nmov [rbp+var_50], 0\njmp short loc_132D\nloc_130A:\nmov eax, [rbp+var_64]\nlea edx, [rax+1]\nmov [rbp+var_64], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_48]\nadd rdx, rax\nmov eax, [rbp+var_50]\ncdqe\nmovzx eax, [rbp+rax+var_40]\nmov [rdx], al\nadd [rbp+var_50], 1\nloc_132D:\nmov eax, [rbp+var_50]\ncmp eax, [rbp+var_60]\njl short loc_130A\nmov [rbp+var_60], 0\njmp short loc_135E\nloc_133E:\nmov eax, [rbp+var_5C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_60]\nlea edx, [rax+1]\nmov [rbp+var_60], edx\nmovzx edx, byte ptr [rcx]\ncdqe\nmov [rbp+rax+var_40], dl\nloc_135E:\nadd [rbp+var_5C], 1\nloc_1362:\nmov eax, [rbp+var_5C]\ncmp eax, [rbp+var_4C]\njle loc_1245\nmov eax, [rbp+var_64]\nmovsxd rdx, eax\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+var_48]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1396\ncall ___stack_chk_fail\nlocret_1396:\nleave\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1)\n{\n int v1; // eax\n int v2; // eax\n int v3; // eax\n char v5; // [rsp+1Bh] [rbp-65h]\n int v6; // [rsp+1Ch] [rbp-64h]\n int v7; // [rsp+20h] [rbp-60h]\n int i; // [rsp+24h] [rbp-5Ch]\n int j; // [rsp+28h] [rbp-58h]\n int k; // [rsp+2Ch] [rbp-54h]\n int m; // [rsp+30h] [rbp-50h]\n int v12; // [rsp+34h] [rbp-4Ch]\n _BYTE *v13; // [rsp+38h] [rbp-48h]\n _BYTE v14[56]; // [rsp+40h] [rbp-40h]\n unsigned __int64 v15; // [rsp+78h] [rbp-8h]\n\n v15 = __readfsqword(0x28u);\n v12 = strlen(a1);\n v13 = malloc(v12 + 2);\n v6 = 0;\n v7 = 0;\n for ( i = 0; i <= v12; ++i )\n {\n if ( a1[i] != 32 && a1[i] )\n {\n v3 = v7++;\n v14[v3] = a1[i];\n }\n else\n {\n for ( j = 0; j < v7 - 1; ++j )\n {\n for ( k = j + 1; k < v7; ++k )\n {\n if ( v14[j] > v14[k] )\n {\n v5 = v14[j];\n v14[j] = v14[k];\n v14[k] = v5;\n }\n }\n }\n if ( v6 > 0 )\n {\n v1 = v6++;\n v13[v1] = 32;\n }\n for ( m = 0; m < v7; ++m )\n {\n v2 = v6++;\n v13[v2] = v14[m];\n }\n v7 = 0;\n }\n }\n v13[v6] = 0;\n return v13;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\nadd rsp, 0FFFFFFFFFFFFFF80h\nmov [rbp+s], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4C], eax\nmov eax, [rbp+var_4C]\nadd eax, 2\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_48], rax\nmov [rbp+var_64], 0\nmov [rbp+var_60], 0\nmov [rbp+var_5C], 0\njmp loc_1362\nloc_1245:\nmov eax, [rbp+var_5C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njz short loc_1271\nmov eax, [rbp+var_5C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_133E\nloc_1271:\nmov [rbp+var_58], 0\njmp short loc_12DA\nloc_127A:\nmov eax, [rbp+var_58]\nadd eax, 1\nmov [rbp+var_54], eax\njmp short loc_12CE\nloc_1285:\nmov eax, [rbp+var_58]\ncdqe\nmovzx edx, [rbp+rax+var_40]\nmov eax, [rbp+var_54]\ncdqe\nmovzx eax, [rbp+rax+var_40]\ncmp dl, al\njle short loc_12CA\nmov eax, [rbp+var_58]\ncdqe\nmovzx eax, [rbp+rax+var_40]\nmov [rbp+var_65], al\nmov eax, [rbp+var_54]\ncdqe\nmovzx edx, [rbp+rax+var_40]\nmov eax, [rbp+var_58]\ncdqe\nmov [rbp+rax+var_40], dl\nmov eax, [rbp+var_54]\ncdqe\nmovzx edx, [rbp+var_65]\nmov [rbp+rax+var_40], dl\nloc_12CA:\nadd [rbp+var_54], 1\nloc_12CE:\nmov eax, [rbp+var_54]\ncmp eax, [rbp+var_60]\njl short loc_1285\nadd [rbp+var_58], 1\nloc_12DA:\nmov eax, [rbp+var_60]\nsub eax, 1\ncmp [rbp+var_58], eax\njl short loc_127A\ncmp [rbp+var_64], 0\njle short loc_1301\nmov eax, [rbp+var_64]\nlea edx, [rax+1]\nmov [rbp+var_64], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov byte ptr [rax], 20h ; ' '\nloc_1301:\nmov [rbp+var_50], 0\njmp short loc_132D\nloc_130A:\nmov eax, [rbp+var_64]\nlea edx, [rax+1]\nmov [rbp+var_64], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_48]\nadd rdx, rax\nmov eax, [rbp+var_50]\ncdqe\nmovzx eax, [rbp+rax+var_40]\nmov [rdx], al\nadd [rbp+var_50], 1\nloc_132D:\nmov eax, [rbp+var_50]\ncmp eax, [rbp+var_60]\njl short loc_130A\nmov [rbp+var_60], 0\njmp short loc_135E\nloc_133E:\nmov eax, [rbp+var_5C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_60]\nlea edx, [rax+1]\nmov [rbp+var_60], edx\nmovzx edx, byte ptr [rcx]\ncdqe\nmov [rbp+rax+var_40], dl\nloc_135E:\nadd [rbp+var_5C], 1\nloc_1362:\nmov eax, [rbp+var_5C]\ncmp eax, [rbp+var_4C]\njle loc_1245\nmov eax, [rbp+var_64]\nmovsxd rdx, eax\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+var_48]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1396\ncall ___stack_chk_fail\nlocret_1396:\nleave\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_11E9(const char *a1)\n{\n int v1; // eax\n int v2; // eax\n int v3; // eax\n char v5; // [rsp+1Bh] [rbp-65h]\n int v6; // [rsp+1Ch] [rbp-64h]\n int v7; // [rsp+20h] [rbp-60h]\n int i; // [rsp+24h] [rbp-5Ch]\n int j; // [rsp+28h] [rbp-58h]\n int k; // [rsp+2Ch] [rbp-54h]\n int m; // [rsp+30h] [rbp-50h]\n int v12; // [rsp+34h] [rbp-4Ch]\n _BYTE *v13; // [rsp+38h] [rbp-48h]\n _BYTE v14[56]; // [rsp+40h] [rbp-40h]\n unsigned __int64 v15; // [rsp+78h] [rbp-8h]\n\n v15 = __readfsqword(0x28u);\n v12 = strlen(a1);\n v13 = malloc(v12 + 2);\n v6 = 0;\n v7 = 0;\n for ( i = 0; i <= v12; ++i )\n {\n if ( a1[i] != 32 && a1[i] )\n {\n v3 = v7++;\n v14[v3] = a1[i];\n }\n else\n {\n for ( j = 0; j < v7 - 1; ++j )\n {\n for ( k = j + 1; k < v7; ++k )\n {\n if ( v14[j] > v14[k] )\n {\n v5 = v14[j];\n v14[j] = v14[k];\n v14[k] = v5;\n }\n }\n }\n if ( v6 > 0 )\n {\n v1 = v6++;\n v13[v1] = 32;\n }\n for ( m = 0; m < v7; ++m )\n {\n v2 = v6++;\n v13[v2] = v14[m];\n }\n v7 = 0;\n }\n }\n v13[v6] = 0;\n return v13;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_11E9(const char *a1) {\n int v1;\n int v2;\n int v3;\n char v5;\n int v6;\n int v7;\n int i;\n int j;\n int k;\n int m;\n int v12;\n uint8_t *v13;\n uint8_t v14[56];\n unsigned long long v15;\n v15 = __readfsqword(40u);\n v12 = strlen(a1);\n v13 = malloc(v12 + 2);\n v6 = 0;\n v7 = 0;\n for (i = 0; i <= v12; ++i) {\n if (a1[i] != 32 && a1[i]) {\n v3 = v7++;\n v14[v3] = a1[i];\n } else {\n for (j = 0; j < v7 - 1; ++j) {\n for (k = j + 1; k < v7; ++k) {\n if (v14[j] > v14[k]) {\n v5 = v14[j];\n v14[j] = v14[k];\n v14[k] = v5;\n }\n }\n }\n if (v6 > 0) {\n v1 = v6++;\n v13[v1] = 32;\n }\n for (m = 0; m < v7; ++m) {\n v2 = v6++;\n v13[v2] = v14[m];\n }\n v7 = 0;\n }\n }\n v13[v6] = 0;\n return v13;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1) {\n int v1;\n int v2;\n int v3;\n char v5;\n int v6;\n int v7;\n int i;\n int j;\n int k;\n int m;\n int v12;\n uint8_t *v13;\n uint8_t v14[56];\n unsigned long long v15;\n v15 = __readfsqword(40u);\n v12 = strlen(a1);\n v13 = malloc(v12 + 2);\n v6 = 0;\n v7 = 0;\n for (i = 0; i <= v12; ++i) {\n if (a1[i] != 32 && a1[i]) {\n v3 = v7++;\n v14[v3] = a1[i];\n } else {\n for (j = 0; j < v7 - 1; ++j) {\n for (k = j + 1; k < v7; ++k) {\n if (v14[j] > v14[k]) {\n v5 = v14[j];\n v14[j] = v14[k];\n v14[k] = v5;\n }\n }\n }\n if (v6 > 0) {\n v1 = v6++;\n v13[v1] = 32;\n }\n for (m = 0; m < v7; ++m) {\n v2 = v6++;\n v13[v2] = v14[m];\n }\n v7 = 0;\n }\n }\n v13[v6] = 0;\n return v13;\n}" + }, + { + "index": "HumanEval-C-86", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char* func0(const char* s) {\n int len = strlen(s);\n char* out = malloc(len + 2);\n char current[51];\n int out_index = 0, current_index = 0;\n for (int i = 0; i <= len; i++) {\n if (s[i] == ' ' || s[i] == '\\0') {\n for (int j = 0; j < current_index - 1; j++) {\n for (int k = j + 1; k < current_index; k++) {\n if (current[j] > current[k]) {\n char temp = current[j];\n current[j] = current[k];\n current[k] = temp;\n }\n }\n }\n if (out_index > 0) out[out_index++] = ' ';\n for (int j = 0; j < current_index; j++) {\n out[out_index++] = current[j];\n }\n current_index = 0;\n } else {\n current[current_index++] = s[i];\n }\n }\n out[out_index] = '\\0';\n return out;\n}", + "test": "#include \n#include \n\nint main() {\n char* result;\n\n result = func0(\"Hi\");\n assert(strcmp(result, \"Hi\") == 0);\n free(result);\n\n result = func0(\"hello\");\n assert(strcmp(result, \"ehllo\") == 0);\n free(result);\n\n result = func0(\"number\");\n assert(strcmp(result, \"bemnru\") == 0);\n free(result);\n\n result = func0(\"abcd\");\n assert(strcmp(result, \"abcd\") == 0);\n free(result);\n\n result = func0(\"Hello World!!!\");\n assert(strcmp(result, \"Hello !!!Wdlor\") == 0);\n free(result);\n\n result = func0(\"\");\n assert(strcmp(result, \"\") == 0);\n free(result);\n\n result = func0(\"Hi. My name is Mister Robot. How are you?\");\n assert(strcmp(result, \".Hi My aemn is Meirst .Rboot How aer ?ouy\") == 0);\n free(result);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 40h\nmov rbp, rdi\nmov rax, fs:28h\nmov [rsp+68h+var_30], rax\nxor eax, eax\ncall _strlen\nmov rbx, rax\nlea edi, [rax+2]\nmovsxd rdi, edi; size\ncall _malloc\nmov r11, rax\ntest ebx, ebx\njs loc_12AD\nmov r10, rbp\nmov ebx, ebx\nlea rbp, [rbp+rbx+1]\nmov r9d, 0\nmov ebx, 0\nmov r13, rsp\nmov r12d, 0\njmp loc_1320\nloc_124D:\ncmp r9d, 1\njle short loc_129F\nmov rsi, rsp\nlea r14d, [r9-1]\nmov r8d, 0\njmp short loc_1286\nloc_1262:\nadd rax, 1\ncmp rax, rdi\njz short loc_127D\nloc_126B:\nmovzx edx, byte ptr [rsi]\nmovzx ecx, byte ptr [rax+1]\ncmp dl, cl\njle short loc_1262\nmov [rsi], cl\nmov [rax+1], dl\njmp short loc_1262\nloc_127D:\nadd rsi, 1\ncmp r8d, r14d\njz short loc_12DA\nloc_1286:\nadd r8d, 1\ncmp r8d, r9d\njge short loc_127D\nmov eax, r14d\nsub eax, r8d\nlea rdi, [rsi+rax+1]\nmov rax, rsi\njmp short loc_126B\nloc_129F:\ntest ebx, ebx\njg short loc_12DE\njmp short loc_12E9\nloc_12A5:\nmov r9d, 0\njmp short loc_1317\nloc_12AD:\nmov ebx, 0\nloc_12B2:\nmovsxd rbx, ebx\nmov byte ptr [r11+rbx], 0\nmov rax, [rsp+68h+var_30]\nsub rax, fs:28h\njnz short loc_1338\nmov rax, r11\nadd rsp, 40h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_12DA:\ntest ebx, ebx\njle short loc_12EE\nloc_12DE:\nmovsxd rax, ebx\nmov byte ptr [r11+rax], 20h ; ' '\nlea ebx, [rbx+1]\nloc_12E9:\ntest r9d, r9d\njle short loc_12A5\nloc_12EE:\nmovsxd rdx, ebx\nmovsxd rcx, r9d\nadd rcx, rdx\nmov rax, rdx\nmov rsi, r13\nsub rsi, rdx\nloc_1300:\nmovzx edx, byte ptr [rsi+rax]\nmov [r11+rax], dl\nadd rax, 1\ncmp rax, rcx\njnz short loc_1300\nadd ebx, r9d\nmov r9d, r12d\nloc_1317:\nadd r10, 1\ncmp r10, rbp\njz short loc_12B2\nloc_1320:\nmovzx eax, byte ptr [r10]\ntest al, 0DFh\njz loc_124D\nmovsxd rdx, r9d\nmov [rsp+rdx+68h+var_68], al\nlea r9d, [r9+1]\njmp short loc_1317\nloc_1338:\ncall ___stack_chk_fail", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1)\n{\n int v1; // ebx\n _BYTE *v2; // r11\n const char *v3; // r10\n __int64 v4; // rbp\n int v5; // r9d\n int v6; // ebx\n char *v7; // rsi\n int v8; // r14d\n int v9; // r8d\n char *v10; // rax\n char v11; // dl\n char v12; // cl\n __int64 v14; // rax\n _BYTE v15[56]; // [rsp+0h] [rbp-68h] BYREF\n unsigned __int64 v16; // [rsp+38h] [rbp-30h]\n\n v16 = __readfsqword(0x28u);\n v1 = strlen(a1);\n v2 = malloc(v1 + 2);\n if ( v1 >= 0 )\n {\n v3 = a1;\n v4 = (__int64)&a1[v1 + 1];\n v5 = 0;\n v6 = 0;\n while ( 1 )\n {\n if ( (*v3 & 0xDF) != 0 )\n {\n v15[v5++] = *v3;\n goto LABEL_22;\n }\n if ( v5 <= 1 )\n {\n if ( v6 <= 0 )\n goto LABEL_18;\n }\n else\n {\n v7 = v15;\n v8 = v5 - 1;\n v9 = 0;\n do\n {\n if ( ++v9 < v5 )\n {\n v10 = v7;\n do\n {\n v11 = *v7;\n v12 = v10[1];\n if ( *v7 > v12 )\n {\n *v7 = v12;\n v10[1] = v11;\n }\n ++v10;\n }\n while ( v10 != &v7[v8 - v9 + 1] );\n }\n ++v7;\n }\n while ( v9 != v8 );\n if ( v6 <= 0 )\n {\nLABEL_19:\n v14 = v6;\n do\n {\n v2[v14] = v15[v14 - v6];\n ++v14;\n }\n while ( v14 != v6 + (__int64)v5 );\n v6 += v5;\n v5 = 0;\n goto LABEL_22;\n }\n }\n v2[v6++] = 32;\nLABEL_18:\n if ( v5 > 0 )\n goto LABEL_19;\n v5 = 0;\nLABEL_22:\n if ( ++v3 == (const char *)v4 )\n goto LABEL_15;\n }\n }\n v6 = 0;\nLABEL_15:\n v2[v6] = 0;\n return v2;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 40h\nmov rbp, rdi\nmov rax, fs:28h\nmov [rsp+68h+var_30], rax\nxor eax, eax\ncall _strlen\nmov rbx, rax\nlea edi, [rax+2]\nmovsxd rdi, edi; size\ncall _malloc\nmov r11, rax\ntest ebx, ebx\njs loc_12AD\nmov r10, rbp\nmov ebx, ebx\nlea rbp, [rbp+rbx+1]\nmov r9d, 0\nmov ebx, 0\nmov r13, rsp\nmov r12d, 0\njmp loc_1320\nloc_124D:\ncmp r9d, 1\njle short loc_129F\nmov rsi, rsp\nlea r14d, [r9-1]\nmov r8d, 0\njmp short loc_1286\nloc_1262:\nadd rax, 1\ncmp rax, rdi\njz short loc_127D\nloc_126B:\nmovzx edx, byte ptr [rsi]\nmovzx ecx, byte ptr [rax+1]\ncmp dl, cl\njle short loc_1262\nmov [rsi], cl\nmov [rax+1], dl\njmp short loc_1262\nloc_127D:\nadd rsi, 1\ncmp r8d, r14d\njz short loc_12DA\nloc_1286:\nadd r8d, 1\ncmp r8d, r9d\njge short loc_127D\nmov eax, r14d\nsub eax, r8d\nlea rdi, [rsi+rax+1]\nmov rax, rsi\njmp short loc_126B\nloc_129F:\ntest ebx, ebx\njg short loc_12DE\njmp short loc_12E9\nloc_12A5:\nmov r9d, 0\njmp short loc_1317\nloc_12AD:\nmov ebx, 0\nloc_12B2:\nmovsxd rbx, ebx\nmov byte ptr [r11+rbx], 0\nmov rax, [rsp+68h+var_30]\nsub rax, fs:28h\njnz short loc_1338\nmov rax, r11\nadd rsp, 40h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_12DA:\ntest ebx, ebx\njle short loc_12EE\nloc_12DE:\nmovsxd rax, ebx\nmov byte ptr [r11+rax], 20h ; ' '\nlea ebx, [rbx+1]\nloc_12E9:\ntest r9d, r9d\njle short loc_12A5\nloc_12EE:\nmovsxd rdx, ebx\nmovsxd rcx, r9d\nadd rcx, rdx\nmov rax, rdx\nmov rsi, r13\nsub rsi, rdx\nloc_1300:\nmovzx edx, byte ptr [rsi+rax]\nmov [r11+rax], dl\nadd rax, 1\ncmp rax, rcx\njnz short loc_1300\nadd ebx, r9d\nmov r9d, r12d\nloc_1317:\nadd r10, 1\ncmp r10, rbp\njz short loc_12B2\nloc_1320:\nmovzx eax, byte ptr [r10]\ntest al, 0DFh\njz loc_124D\nmovsxd rdx, r9d\nmov [rsp+rdx+68h+var_68], al\nlea r9d, [r9+1]\njmp short loc_1317\nloc_1338:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_BYTE *__fastcall sub_11E9(const char *a1)\n{\n int v1; // ebx\n _BYTE *v2; // r11\n const char *v3; // r10\n __int64 v4; // rbp\n int v5; // r9d\n int v6; // ebx\n char *v7; // rsi\n int v8; // r14d\n int v9; // r8d\n char *v10; // rax\n char v11; // dl\n char v12; // cl\n __int64 v14; // rax\n _BYTE v15[56]; // [rsp+0h] [rbp-68h] BYREF\n unsigned __int64 v16; // [rsp+38h] [rbp-30h]\n\n v16 = __readfsqword(0x28u);\n v1 = strlen(a1);\n v2 = malloc(v1 + 2);\n if ( v1 >= 0 )\n {\n v3 = a1;\n v4 = (__int64)&a1[v1 + 1];\n v5 = 0;\n v6 = 0;\n while ( 1 )\n {\n if ( (*v3 & 0xDF) != 0 )\n {\n v15[v5++] = *v3;\n goto LABEL_22;\n }\n if ( v5 <= 1 )\n {\n if ( v6 <= 0 )\n goto LABEL_18;\n }\n else\n {\n v7 = v15;\n v8 = v5 - 1;\n v9 = 0;\n do\n {\n if ( ++v9 < v5 )\n {\n v10 = v7;\n do\n {\n v11 = *v7;\n v12 = v10[1];\n if ( *v7 > v12 )\n {\n *v7 = v12;\n v10[1] = v11;\n }\n ++v10;\n }\n while ( v10 != &v7[v8 - v9 + 1] );\n }\n ++v7;\n }\n while ( v9 != v8 );\n if ( v6 <= 0 )\n {\nLABEL_19:\n v14 = v6;\n do\n {\n v2[v14] = v15[v14 - v6];\n ++v14;\n }\n while ( v14 != v6 + (__int64)v5 );\n v6 += v5;\n v5 = 0;\n goto LABEL_22;\n }\n }\n v2[v6++] = 32;\nLABEL_18:\n if ( v5 > 0 )\n goto LABEL_19;\n v5 = 0;\nLABEL_22:\n if ( ++v3 == (const char *)v4 )\n goto LABEL_15;\n }\n }\n v6 = 0;\nLABEL_15:\n v2[v6] = 0;\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_11E9(const char *a1) {\n int v1;\n uint8_t *v2;\n const char *v3;\n long long v4;\n int v5;\n int v6;\n char *v7;\n int v8;\n int v9;\n char *v10;\n char v11;\n char v12;\n long long v14;\n uint8_t v15[56];\n unsigned long long v16;\n v16 = __readfsqword(40u);\n v1 = strlen(a1);\n v2 = malloc(v1 + 2);\n if (v1 >= 0) {\n v3 = a1;\n v4 = (long long)&a1[v1 + 1];\n v5 = 0;\n v6 = 0;\n while (1) {\n if ((*v3 & 223) != 0) {\n v15[v5++] = *v3;\n goto LABEL_22;\n }\n if (v5 <= 1) {\n if (v6 <= 0) goto LABEL_18;\n } else {\n v7 = v15;\n v8 = v5 - 1;\n v9 = 0;\n do {\n if (++v9 < v5) {\n v10 = v7;\n do {\n v11 = *v7;\n v12 = v10[1];\n if (*v7 > v12) {\n *v7 = v12;\n v10[1] = v11;\n }\n ++v10;\n } while (v10 != &v7[v8 - v9 + 1]);\n }\n ++v7;\n } while (v9 != v8);\n if (v6 <= 0) {\n LABEL_19:\n v14 = v6;\n do {\n v2[v14] = v15[v14 - v6];\n ++v14;\n } while (v14 != v6 + (long long)v5);\n v6 += v5;\n v5 = 0;\n goto LABEL_22;\n }\n }\n v2[v6++] = 32;\n LABEL_18:\n if (v5 > 0) goto LABEL_19;\n v5 = 0;\n LABEL_22:\n if (++v3 == (const char *)v4) goto LABEL_15;\n }\n }\n v6 = 0;\nLABEL_15:\n v2[v6] = 0;\n return v2;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1) {\n int v1;\n uint8_t *v2;\n const char *v3;\n long long v4;\n int v5;\n int v6;\n char *v7;\n int v8;\n int v9;\n char *v10;\n char v11;\n char v12;\n long long v14;\n uint8_t v15[56];\n unsigned long long v16;\n v16 = __readfsqword(40u);\n v1 = strlen(a1);\n v2 = malloc(v1 + 2);\n if (v1 >= 0) {\n v3 = a1;\n v4 = (long long)&a1[v1 + 1];\n v5 = 0;\n v6 = 0;\n while (1) {\n if ((*v3 & 223) != 0) {\n v15[v5++] = *v3;\n goto LABEL_22;\n }\n if (v5 <= 1) {\n if (v6 <= 0) goto LABEL_18;\n } else {\n v7 = v15;\n v8 = v5 - 1;\n v9 = 0;\n do {\n if (++v9 < v5) {\n v10 = v7;\n do {\n v11 = *v7;\n v12 = v10[1];\n if (*v7 > v12) {\n *v7 = v12;\n v10[1] = v11;\n }\n ++v10;\n } while (v10 != &v7[v8 - v9 + 1]);\n }\n ++v7;\n } while (v9 != v8);\n if (v6 <= 0) {\n LABEL_19:\n v14 = v6;\n do {\n v2[v14] = v15[v14 - v6];\n ++v14;\n } while (v14 != v6 + (long long)v5);\n v6 += v5;\n v5 = 0;\n goto LABEL_22;\n }\n }\n v2[v6++] = 32;\n LABEL_18:\n if (v5 > 0) goto LABEL_19;\n v5 = 0;\n LABEL_22:\n if (++v3 == (const char *)v4) goto LABEL_15;\n }\n }\n v6 = 0;\nLABEL_15:\n v2[v6] = 0;\n return v2;\n}" + }, + { + "index": "HumanEval-C-86", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char* func0(const char* s) {\n int len = strlen(s);\n char* out = malloc(len + 2);\n char current[51];\n int out_index = 0, current_index = 0;\n for (int i = 0; i <= len; i++) {\n if (s[i] == ' ' || s[i] == '\\0') {\n for (int j = 0; j < current_index - 1; j++) {\n for (int k = j + 1; k < current_index; k++) {\n if (current[j] > current[k]) {\n char temp = current[j];\n current[j] = current[k];\n current[k] = temp;\n }\n }\n }\n if (out_index > 0) out[out_index++] = ' ';\n for (int j = 0; j < current_index; j++) {\n out[out_index++] = current[j];\n }\n current_index = 0;\n } else {\n current[current_index++] = s[i];\n }\n }\n out[out_index] = '\\0';\n return out;\n}", + "test": "#include \n#include \n\nint main() {\n char* result;\n\n result = func0(\"Hi\");\n assert(strcmp(result, \"Hi\") == 0);\n free(result);\n\n result = func0(\"hello\");\n assert(strcmp(result, \"ehllo\") == 0);\n free(result);\n\n result = func0(\"number\");\n assert(strcmp(result, \"bemnru\") == 0);\n free(result);\n\n result = func0(\"abcd\");\n assert(strcmp(result, \"abcd\") == 0);\n free(result);\n\n result = func0(\"Hello World!!!\");\n assert(strcmp(result, \"Hello !!!Wdlor\") == 0);\n free(result);\n\n result = func0(\"\");\n assert(strcmp(result, \"\") == 0);\n free(result);\n\n result = func0(\"Hi. My name is Mister Robot. How are you?\");\n assert(strcmp(result, \".Hi My aemn is Meirst .Rboot How aer ?ouy\") == 0);\n free(result);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 48h\nmov rax, fs:28h\nmov [rsp+78h+var_40], rax\nxor eax, eax\ncall _strlen\nlea edi, [rax+2]\nmov rbx, rax\nmovsxd rdi, edi; size\ncall _malloc\nmov r14, rax\ntest ebx, ebx\njs loc_153A\nmov ebx, ebx\nxor r12d, r12d\nmov r15, rsp\nlea r13, [rbp+rbx+1]\nxor ebx, ebx\njmp short loc_149E\nloc_1488:\nmovsxd rdx, ebx\nadd ebx, 1\nmov [rsp+rdx+78h+var_78], al\nloc_1491:\nadd rbp, 1\ncmp rbp, r13\njz loc_1534\nloc_149E:\nmovzx eax, byte ptr [rbp+0]\ntest al, 0DFh\njnz short loc_1488\ncmp ebx, 1\njle loc_1572\nmov r10, r15\nmov rsi, r15\nlea r11d, [rbx-1]\nxor r8d, r8d\nnop dword ptr [rax+00h]\nloc_14C0:\nadd r8d, 1\ncmp r8d, ebx\njge loc_1560\nmov edi, r11d\nlea r9, [rsi+1]\nmov rax, rsi\nsub edi, r8d\nadd rdi, r9\nnop dword ptr [rax]\nloc_14E0:\nmovzx edx, byte ptr [rsi]\nmovzx ecx, byte ptr [rax+1]\ncmp dl, cl\njle short loc_14F0\nmov [rsi], cl\nmov [rax+1], dl\nloc_14F0:\nadd rax, 1\ncmp rdi, rax\njnz short loc_14E0\nmov rsi, r9\ncmp r8d, r11d\njnz short loc_14C0\nloc_1501:\ntest r12d, r12d\njle short loc_1512\nmovsxd rax, r12d\nadd r12d, 1\nmov byte ptr [r14+rax], 20h ; ' '\nloc_1512:\nmovsxd rdi, r12d\nmov edx, ebx; n\nmov rsi, r10; src\nadd rbp, 1\nadd rdi, r14; dest\nadd r12d, ebx\nxor ebx, ebx\ncall _memcpy\ncmp rbp, r13\njnz loc_149E\nloc_1534:\nmovsxd rax, r12d\nadd rax, r14\nloc_153A:\nmov byte ptr [rax], 0\nmov rax, [rsp+78h+var_40]\nsub rax, fs:28h\njnz short loc_1597\nadd rsp, 48h\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1560:\nlea r9, [rsi+1]\nmov rsi, r9\ncmp r8d, r11d\njnz loc_14C0\njmp short loc_1501\nloc_1572:\ntest r12d, r12d\njle short loc_1583\nmovsxd rax, r12d\nadd r12d, 1\nmov byte ptr [r14+rax], 20h ; ' '\nloc_1583:\ncmp ebx, 1\njz short loc_158F\nxor ebx, ebx\njmp loc_1491\nloc_158F:\nmov r10, rsp\njmp loc_1512\nloc_1597:\ncall ___stack_chk_fail", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1)\n{\n const char *v1; // rbp\n int v2; // ebx\n _BYTE *v3; // rax\n _BYTE *v4; // r14\n int v5; // r12d\n __int64 v6; // r13\n int v7; // ebx\n __int64 v8; // rdx\n char *v9; // rsi\n int v10; // r11d\n int v11; // r8d\n char *v12; // rax\n char v13; // dl\n char v14; // cl\n __int64 v15; // rax\n size_t v16; // rdx\n _BYTE *v17; // rdi\n __int64 v19; // rax\n _BYTE v20[56]; // [rsp+0h] [rbp-78h] BYREF\n unsigned __int64 v21; // [rsp+38h] [rbp-40h]\n\n v1 = a1;\n v21 = __readfsqword(0x28u);\n v2 = strlen(a1);\n v3 = malloc(v2 + 2);\n v4 = v3;\n if ( v2 >= 0 )\n {\n v5 = 0;\n v6 = (__int64)&a1[v2 + 1];\n v7 = 0;\n while ( 1 )\n {\n while ( (*v1 & 0xDF) != 0 )\n {\n v8 = v7++;\n v20[v8] = *v1;\nLABEL_4:\n if ( ++v1 == (const char *)v6 )\n goto LABEL_17;\n }\n if ( v7 > 1 )\n {\n v9 = v20;\n v10 = v7 - 1;\n v11 = 0;\n do\n {\n while ( ++v11 >= v7 )\n {\n ++v9;\n if ( v11 == v10 )\n goto LABEL_14;\n }\n v12 = v9;\n do\n {\n v13 = *v9;\n v14 = v12[1];\n if ( *v9 > v14 )\n {\n *v9 = v14;\n v12[1] = v13;\n }\n ++v12;\n }\n while ( &v9[v10 - v11 + 1] != v12 );\n ++v9;\n }\n while ( v11 != v10 );\nLABEL_14:\n if ( v5 > 0 )\n {\n v15 = v5++;\n v4[v15] = 32;\n }\n goto LABEL_16;\n }\n if ( v5 > 0 )\n {\n v19 = v5++;\n v4[v19] = 32;\n }\n if ( v7 != 1 )\n {\n v7 = 0;\n goto LABEL_4;\n }\nLABEL_16:\n v16 = (unsigned int)v7;\n ++v1;\n v17 = &v4[v5];\n v5 += v7;\n v7 = 0;\n memcpy(v17, v20, v16);\n if ( v1 == (const char *)v6 )\n {\nLABEL_17:\n v3 = &v4[v5];\n break;\n }\n }\n }\n *v3 = 0;\n return v4;\n}", + "ida_strip_asm": "sub_1430:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 48h\nmov rax, fs:28h\nmov [rsp+78h+var_40], rax\nxor eax, eax\ncall _strlen\nlea edi, [rax+2]\nmov rbx, rax\nmovsxd rdi, edi; size\ncall _malloc\nmov r14, rax\ntest ebx, ebx\njs loc_153A\nmov ebx, ebx\nxor r12d, r12d\nmov r15, rsp\nlea r13, [rbp+rbx+1]\nxor ebx, ebx\njmp short loc_149E\nloc_1488:\nmovsxd rdx, ebx\nadd ebx, 1\nmov [rsp+rdx+78h+var_78], al\nloc_1491:\nadd rbp, 1\ncmp rbp, r13\njz loc_1534\nloc_149E:\nmovzx eax, byte ptr [rbp+0]\ntest al, 0DFh\njnz short loc_1488\ncmp ebx, 1\njle loc_1572\nmov r10, r15\nmov rsi, r15\nlea r11d, [rbx-1]\nxor r8d, r8d\nnop dword ptr [rax+00h]\nloc_14C0:\nadd r8d, 1\ncmp r8d, ebx\njge loc_1560\nmov edi, r11d\nlea r9, [rsi+1]\nmov rax, rsi\nsub edi, r8d\nadd rdi, r9\nnop dword ptr [rax]\nloc_14E0:\nmovzx edx, byte ptr [rsi]\nmovzx ecx, byte ptr [rax+1]\ncmp dl, cl\njle short loc_14F0\nmov [rsi], cl\nmov [rax+1], dl\nloc_14F0:\nadd rax, 1\ncmp rdi, rax\njnz short loc_14E0\nmov rsi, r9\ncmp r8d, r11d\njnz short loc_14C0\nloc_1501:\ntest r12d, r12d\njle short loc_1512\nmovsxd rax, r12d\nadd r12d, 1\nmov byte ptr [r14+rax], 20h ; ' '\nloc_1512:\nmovsxd rdi, r12d\nmov edx, ebx; n\nmov rsi, r10; src\nadd rbp, 1\nadd rdi, r14; dest\nadd r12d, ebx\nxor ebx, ebx\ncall _memcpy\ncmp rbp, r13\njnz loc_149E\nloc_1534:\nmovsxd rax, r12d\nadd rax, r14\nloc_153A:\nmov byte ptr [rax], 0\nmov rax, [rsp+78h+var_40]\nsub rax, fs:28h\njnz short loc_1597\nadd rsp, 48h\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1560:\nlea r9, [rsi+1]\nmov rsi, r9\ncmp r8d, r11d\njnz loc_14C0\njmp short loc_1501\nloc_1572:\ntest r12d, r12d\njle short loc_1583\nmovsxd rax, r12d\nadd r12d, 1\nmov byte ptr [r14+rax], 20h ; ' '\nloc_1583:\ncmp ebx, 1\njz short loc_158F\nxor ebx, ebx\njmp loc_1491\nloc_158F:\nmov r10, rsp\njmp loc_1512\nloc_1597:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1430(const char *a1)\n{\n const char *v1; // rbp\n int v2; // ebx\n _BYTE *v3; // rax\n _BYTE *v4; // r14\n int v5; // r12d\n __int64 v6; // r13\n int v7; // ebx\n __int64 v8; // rdx\n char *v9; // rsi\n int v10; // r11d\n int v11; // r8d\n char *v12; // rax\n char v13; // dl\n char v14; // cl\n __int64 v15; // rax\n size_t v16; // rdx\n _BYTE *v17; // rdi\n __int64 v19; // rax\n _BYTE v20[56]; // [rsp+0h] [rbp-78h] BYREF\n unsigned __int64 v21; // [rsp+38h] [rbp-40h]\n\n v1 = a1;\n v21 = __readfsqword(0x28u);\n v2 = strlen(a1);\n v3 = malloc(v2 + 2);\n v4 = v3;\n if ( v2 >= 0 )\n {\n v5 = 0;\n v6 = (__int64)&a1[v2 + 1];\n v7 = 0;\n while ( 1 )\n {\n while ( (*v1 & 0xDF) != 0 )\n {\n v8 = v7++;\n v20[v8] = *v1;\nLABEL_4:\n if ( ++v1 == (const char *)v6 )\n goto LABEL_17;\n }\n if ( v7 > 1 )\n {\n v9 = v20;\n v10 = v7 - 1;\n v11 = 0;\n do\n {\n while ( ++v11 >= v7 )\n {\n ++v9;\n if ( v11 == v10 )\n goto LABEL_14;\n }\n v12 = v9;\n do\n {\n v13 = *v9;\n v14 = v12[1];\n if ( *v9 > v14 )\n {\n *v9 = v14;\n v12[1] = v13;\n }\n ++v12;\n }\n while ( &v9[v10 - v11 + 1] != v12 );\n ++v9;\n }\n while ( v11 != v10 );\nLABEL_14:\n if ( v5 > 0 )\n {\n v15 = v5++;\n v4[v15] = 32;\n }\n goto LABEL_16;\n }\n if ( v5 > 0 )\n {\n v19 = v5++;\n v4[v19] = 32;\n }\n if ( v7 != 1 )\n {\n v7 = 0;\n goto LABEL_4;\n }\nLABEL_16:\n v16 = (unsigned int)v7;\n ++v1;\n v17 = &v4[v5];\n v5 += v7;\n v7 = 0;\n memcpy(v17, v20, v16);\n if ( v1 == (const char *)v6 )\n {\nLABEL_17:\n v3 = &v4[v5];\n break;\n }\n }\n }\n *v3 = 0;\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1430(const char *a1) {\n const char *v1;\n int v2;\n uint8_t *v3;\n uint8_t *v4;\n int v5;\n long long v6;\n int v7;\n long long v8;\n char *v9;\n int v10;\n int v11;\n char *v12;\n char v13;\n char v14;\n long long v15;\n unsigned int v16;\n uint8_t *v17;\n long long v19;\n uint8_t v20[56];\n unsigned long long v21;\n v1 = a1;\n v21 = __readfsqword(40u);\n v2 = strlen(a1);\n v3 = malloc(v2 + 2);\n v4 = v3;\n if (v2 >= 0) {\n v5 = 0;\n v6 = (long long)&a1[v2 + 1];\n v7 = 0;\n while (1) {\n while ((*v1 & 223) != 0) {\n v8 = v7++;\n v20[v8] = *v1;\n LABEL_4:\n if (++v1 == (const char *)v6) goto LABEL_17;\n }\n if (v7 > 1) {\n v9 = v20;\n v10 = v7 - 1;\n v11 = 0;\n do {\n while (++v11 >= v7) {\n ++v9;\n if (v11 == v10) goto LABEL_14;\n }\n v12 = v9;\n do {\n v13 = *v9;\n v14 = v12[1];\n if (*v9 > v14) {\n *v9 = v14;\n v12[1] = v13;\n }\n ++v12;\n } while (&v9[v10 - v11 + 1] != v12);\n ++v9;\n } while (v11 != v10);\n LABEL_14:\n if (v5 > 0) {\n v15 = v5++;\n v4[v15] = 32;\n }\n goto LABEL_16;\n }\n if (v5 > 0) {\n v19 = v5++;\n v4[v19] = 32;\n }\n if (v7 != 1) {\n v7 = 0;\n goto LABEL_4;\n }\n LABEL_16:\n v16 = (unsigned int)v7;\n ++v1;\n v17 = &v4[v5];\n v5 += v7;\n v7 = 0;\n memcpy(v17, v20, v16);\n if (v1 == (const char *)v6) {\n LABEL_17:\n v3 = &v4[v5];\n break;\n }\n }\n }\n *v3 = 0;\n return v4;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1) {\n const char *v1;\n int v2;\n uint8_t *v3;\n uint8_t *v4;\n int v5;\n long long v6;\n int v7;\n long long v8;\n char *v9;\n int v10;\n int v11;\n char *v12;\n char v13;\n char v14;\n long long v15;\n unsigned int v16;\n uint8_t *v17;\n long long v19;\n uint8_t v20[56];\n unsigned long long v21;\n v1 = a1;\n v21 = __readfsqword(40u);\n v2 = strlen(a1);\n v3 = malloc(v2 + 2);\n v4 = v3;\n if (v2 >= 0) {\n v5 = 0;\n v6 = (long long)&a1[v2 + 1];\n v7 = 0;\n while (1) {\n while ((*v1 & 223) != 0) {\n v8 = v7++;\n v20[v8] = *v1;\n LABEL_4:\n if (++v1 == (const char *)v6) goto LABEL_17;\n }\n if (v7 > 1) {\n v9 = v20;\n v10 = v7 - 1;\n v11 = 0;\n do {\n while (++v11 >= v7) {\n ++v9;\n if (v11 == v10) goto LABEL_14;\n }\n v12 = v9;\n do {\n v13 = *v9;\n v14 = v12[1];\n if (*v9 > v14) {\n *v9 = v14;\n v12[1] = v13;\n }\n ++v12;\n } while (&v9[v10 - v11 + 1] != v12);\n ++v9;\n } while (v11 != v10);\n LABEL_14:\n if (v5 > 0) {\n v15 = v5++;\n v4[v15] = 32;\n }\n goto LABEL_16;\n }\n if (v5 > 0) {\n v19 = v5++;\n v4[v19] = 32;\n }\n if (v7 != 1) {\n v7 = 0;\n goto LABEL_4;\n }\n LABEL_16:\n v16 = (unsigned int)v7;\n ++v1;\n v17 = &v4[v5];\n v5 += v7;\n v7 = 0;\n memcpy(v17, v20, v16);\n if (v1 == (const char *)v6) {\n LABEL_17:\n v3 = &v4[v5];\n break;\n }\n }\n }\n *v3 = 0;\n return v4;\n}" + }, + { + "index": "HumanEval-C-86", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char* func0(const char* s) {\n int len = strlen(s);\n char* out = malloc(len + 2);\n char current[51];\n int out_index = 0, current_index = 0;\n for (int i = 0; i <= len; i++) {\n if (s[i] == ' ' || s[i] == '\\0') {\n for (int j = 0; j < current_index - 1; j++) {\n for (int k = j + 1; k < current_index; k++) {\n if (current[j] > current[k]) {\n char temp = current[j];\n current[j] = current[k];\n current[k] = temp;\n }\n }\n }\n if (out_index > 0) out[out_index++] = ' ';\n for (int j = 0; j < current_index; j++) {\n out[out_index++] = current[j];\n }\n current_index = 0;\n } else {\n current[current_index++] = s[i];\n }\n }\n out[out_index] = '\\0';\n return out;\n}", + "test": "#include \n#include \n\nint main() {\n char* result;\n\n result = func0(\"Hi\");\n assert(strcmp(result, \"Hi\") == 0);\n free(result);\n\n result = func0(\"hello\");\n assert(strcmp(result, \"ehllo\") == 0);\n free(result);\n\n result = func0(\"number\");\n assert(strcmp(result, \"bemnru\") == 0);\n free(result);\n\n result = func0(\"abcd\");\n assert(strcmp(result, \"abcd\") == 0);\n free(result);\n\n result = func0(\"Hello World!!!\");\n assert(strcmp(result, \"Hello !!!Wdlor\") == 0);\n free(result);\n\n result = func0(\"\");\n assert(strcmp(result, \"\") == 0);\n free(result);\n\n result = func0(\"Hi. My name is Mister Robot. How are you?\");\n assert(strcmp(result, \".Hi My aemn is Meirst .Rboot How aer ?ouy\") == 0);\n free(result);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 48h\nmov rax, fs:28h\nmov [rsp+78h+var_40], rax\nxor eax, eax\ncall _strlen\nlea edi, [rax+2]\nmov rbx, rax\nmovsxd rdi, edi; size\ncall _malloc\nmov r14, rax\ntest ebx, ebx\njs loc_153A\nmov ebx, ebx\nxor r12d, r12d\nmov r15, rsp\nlea r13, [rbp+rbx+1]\nxor ebx, ebx\njmp short loc_149E\nloc_1488:\nmovsxd rdx, ebx\nadd ebx, 1\nmov [rsp+rdx+78h+var_78], al\nloc_1491:\nadd rbp, 1\ncmp rbp, r13\njz loc_1534\nloc_149E:\nmovzx eax, byte ptr [rbp+0]\ntest al, 0DFh\njnz short loc_1488\ncmp ebx, 1\njle loc_1572\nmov r10, r15\nmov rsi, r15\nlea r11d, [rbx-1]\nxor r8d, r8d\nnop dword ptr [rax+00h]\nloc_14C0:\nadd r8d, 1\ncmp r8d, ebx\njge loc_1560\nmov edi, r11d\nlea r9, [rsi+1]\nmov rax, rsi\nsub edi, r8d\nadd rdi, r9\nnop dword ptr [rax]\nloc_14E0:\nmovzx edx, byte ptr [rsi]\nmovzx ecx, byte ptr [rax+1]\ncmp dl, cl\njle short loc_14F0\nmov [rsi], cl\nmov [rax+1], dl\nloc_14F0:\nadd rax, 1\ncmp rdi, rax\njnz short loc_14E0\nmov rsi, r9\ncmp r11d, r8d\njnz short loc_14C0\nloc_1501:\ntest r12d, r12d\njle short loc_1512\nmovsxd rax, r12d\nadd r12d, 1\nmov byte ptr [r14+rax], 20h ; ' '\nloc_1512:\nmovsxd rdi, r12d\nmov edx, ebx; n\nmov rsi, r10; src\nadd rbp, 1\nadd rdi, r14; dest\nadd r12d, ebx\nxor ebx, ebx\ncall _memcpy\ncmp rbp, r13\njnz loc_149E\nloc_1534:\nmovsxd rax, r12d\nadd rax, r14\nloc_153A:\nmov byte ptr [rax], 0\nmov rax, [rsp+78h+var_40]\nsub rax, fs:28h\njnz short loc_1597\nadd rsp, 48h\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1560:\nlea r9, [rsi+1]\nmov rsi, r9\ncmp r11d, r8d\njnz loc_14C0\njmp short loc_1501\nloc_1572:\ntest r12d, r12d\njle short loc_1583\nmovsxd rax, r12d\nadd r12d, 1\nmov byte ptr [r14+rax], 20h ; ' '\nloc_1583:\ncmp ebx, 1\njz short loc_158F\nxor ebx, ebx\njmp loc_1491\nloc_158F:\nmov r10, rsp\njmp loc_1512\nloc_1597:\ncall ___stack_chk_fail", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1)\n{\n const char *v1; // rbp\n int v2; // ebx\n _BYTE *v3; // rax\n _BYTE *v4; // r14\n int v5; // r12d\n __int64 v6; // r13\n int v7; // ebx\n __int64 v8; // rdx\n char *v9; // rsi\n int v10; // r11d\n int v11; // r8d\n char *v12; // rax\n char v13; // dl\n char v14; // cl\n __int64 v15; // rax\n size_t v16; // rdx\n _BYTE *v17; // rdi\n __int64 v19; // rax\n _BYTE v20[56]; // [rsp+0h] [rbp-78h] BYREF\n unsigned __int64 v21; // [rsp+38h] [rbp-40h]\n\n v1 = a1;\n v21 = __readfsqword(0x28u);\n v2 = strlen(a1);\n v3 = malloc(v2 + 2);\n v4 = v3;\n if ( v2 >= 0 )\n {\n v5 = 0;\n v6 = (__int64)&a1[v2 + 1];\n v7 = 0;\n while ( 1 )\n {\n while ( (*v1 & 0xDF) != 0 )\n {\n v8 = v7++;\n v20[v8] = *v1;\nLABEL_4:\n if ( ++v1 == (const char *)v6 )\n goto LABEL_17;\n }\n if ( v7 > 1 )\n {\n v9 = v20;\n v10 = v7 - 1;\n v11 = 0;\n do\n {\n while ( ++v11 >= v7 )\n {\n ++v9;\n if ( v10 == v11 )\n goto LABEL_14;\n }\n v12 = v9;\n do\n {\n v13 = *v9;\n v14 = v12[1];\n if ( *v9 > v14 )\n {\n *v9 = v14;\n v12[1] = v13;\n }\n ++v12;\n }\n while ( &v9[v10 - v11 + 1] != v12 );\n ++v9;\n }\n while ( v10 != v11 );\nLABEL_14:\n if ( v5 > 0 )\n {\n v15 = v5++;\n v4[v15] = 32;\n }\n goto LABEL_16;\n }\n if ( v5 > 0 )\n {\n v19 = v5++;\n v4[v19] = 32;\n }\n if ( v7 != 1 )\n {\n v7 = 0;\n goto LABEL_4;\n }\nLABEL_16:\n v16 = (unsigned int)v7;\n ++v1;\n v17 = &v4[v5];\n v5 += v7;\n v7 = 0;\n memcpy(v17, v20, v16);\n if ( v1 == (const char *)v6 )\n {\nLABEL_17:\n v3 = &v4[v5];\n break;\n }\n }\n }\n *v3 = 0;\n return v4;\n}", + "ida_strip_asm": "sub_1430:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 48h\nmov rax, fs:28h\nmov [rsp+78h+var_40], rax\nxor eax, eax\ncall _strlen\nlea edi, [rax+2]\nmov rbx, rax\nmovsxd rdi, edi; size\ncall _malloc\nmov r14, rax\ntest ebx, ebx\njs loc_153A\nmov ebx, ebx\nxor r12d, r12d\nmov r15, rsp\nlea r13, [rbp+rbx+1]\nxor ebx, ebx\njmp short loc_149E\nloc_1488:\nmovsxd rdx, ebx\nadd ebx, 1\nmov [rsp+rdx+78h+var_78], al\nloc_1491:\nadd rbp, 1\ncmp rbp, r13\njz loc_1534\nloc_149E:\nmovzx eax, byte ptr [rbp+0]\ntest al, 0DFh\njnz short loc_1488\ncmp ebx, 1\njle loc_1572\nmov r10, r15\nmov rsi, r15\nlea r11d, [rbx-1]\nxor r8d, r8d\nnop dword ptr [rax+00h]\nloc_14C0:\nadd r8d, 1\ncmp r8d, ebx\njge loc_1560\nmov edi, r11d\nlea r9, [rsi+1]\nmov rax, rsi\nsub edi, r8d\nadd rdi, r9\nnop dword ptr [rax]\nloc_14E0:\nmovzx edx, byte ptr [rsi]\nmovzx ecx, byte ptr [rax+1]\ncmp dl, cl\njle short loc_14F0\nmov [rsi], cl\nmov [rax+1], dl\nloc_14F0:\nadd rax, 1\ncmp rdi, rax\njnz short loc_14E0\nmov rsi, r9\ncmp r11d, r8d\njnz short loc_14C0\nloc_1501:\ntest r12d, r12d\njle short loc_1512\nmovsxd rax, r12d\nadd r12d, 1\nmov byte ptr [r14+rax], 20h ; ' '\nloc_1512:\nmovsxd rdi, r12d\nmov edx, ebx; n\nmov rsi, r10; src\nadd rbp, 1\nadd rdi, r14; dest\nadd r12d, ebx\nxor ebx, ebx\ncall _memcpy\ncmp rbp, r13\njnz loc_149E\nloc_1534:\nmovsxd rax, r12d\nadd rax, r14\nloc_153A:\nmov byte ptr [rax], 0\nmov rax, [rsp+78h+var_40]\nsub rax, fs:28h\njnz short loc_1597\nadd rsp, 48h\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1560:\nlea r9, [rsi+1]\nmov rsi, r9\ncmp r11d, r8d\njnz loc_14C0\njmp short loc_1501\nloc_1572:\ntest r12d, r12d\njle short loc_1583\nmovsxd rax, r12d\nadd r12d, 1\nmov byte ptr [r14+rax], 20h ; ' '\nloc_1583:\ncmp ebx, 1\njz short loc_158F\nxor ebx, ebx\njmp loc_1491\nloc_158F:\nmov r10, rsp\njmp loc_1512\nloc_1597:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1430(const char *a1)\n{\n const char *v1; // rbp\n int v2; // ebx\n _BYTE *v3; // rax\n _BYTE *v4; // r14\n int v5; // r12d\n __int64 v6; // r13\n int v7; // ebx\n __int64 v8; // rdx\n char *v9; // rsi\n int v10; // r11d\n int v11; // r8d\n char *v12; // rax\n char v13; // dl\n char v14; // cl\n __int64 v15; // rax\n size_t v16; // rdx\n _BYTE *v17; // rdi\n __int64 v19; // rax\n _BYTE v20[56]; // [rsp+0h] [rbp-78h] BYREF\n unsigned __int64 v21; // [rsp+38h] [rbp-40h]\n\n v1 = a1;\n v21 = __readfsqword(0x28u);\n v2 = strlen(a1);\n v3 = malloc(v2 + 2);\n v4 = v3;\n if ( v2 >= 0 )\n {\n v5 = 0;\n v6 = (__int64)&a1[v2 + 1];\n v7 = 0;\n while ( 1 )\n {\n while ( (*v1 & 0xDF) != 0 )\n {\n v8 = v7++;\n v20[v8] = *v1;\nLABEL_4:\n if ( ++v1 == (const char *)v6 )\n goto LABEL_17;\n }\n if ( v7 > 1 )\n {\n v9 = v20;\n v10 = v7 - 1;\n v11 = 0;\n do\n {\n while ( ++v11 >= v7 )\n {\n ++v9;\n if ( v10 == v11 )\n goto LABEL_14;\n }\n v12 = v9;\n do\n {\n v13 = *v9;\n v14 = v12[1];\n if ( *v9 > v14 )\n {\n *v9 = v14;\n v12[1] = v13;\n }\n ++v12;\n }\n while ( &v9[v10 - v11 + 1] != v12 );\n ++v9;\n }\n while ( v10 != v11 );\nLABEL_14:\n if ( v5 > 0 )\n {\n v15 = v5++;\n v4[v15] = 32;\n }\n goto LABEL_16;\n }\n if ( v5 > 0 )\n {\n v19 = v5++;\n v4[v19] = 32;\n }\n if ( v7 != 1 )\n {\n v7 = 0;\n goto LABEL_4;\n }\nLABEL_16:\n v16 = (unsigned int)v7;\n ++v1;\n v17 = &v4[v5];\n v5 += v7;\n v7 = 0;\n memcpy(v17, v20, v16);\n if ( v1 == (const char *)v6 )\n {\nLABEL_17:\n v3 = &v4[v5];\n break;\n }\n }\n }\n *v3 = 0;\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1430(const char *a1) {\n const char *v1;\n int v2;\n uint8_t *v3;\n uint8_t *v4;\n int v5;\n long long v6;\n int v7;\n long long v8;\n char *v9;\n int v10;\n int v11;\n char *v12;\n char v13;\n char v14;\n long long v15;\n unsigned int v16;\n uint8_t *v17;\n long long v19;\n uint8_t v20[56];\n unsigned long long v21;\n v1 = a1;\n v21 = __readfsqword(40u);\n v2 = strlen(a1);\n v3 = malloc(v2 + 2);\n v4 = v3;\n if (v2 >= 0) {\n v5 = 0;\n v6 = (long long)&a1[v2 + 1];\n v7 = 0;\n while (1) {\n while ((*v1 & 223) != 0) {\n v8 = v7++;\n v20[v8] = *v1;\n LABEL_4:\n if (++v1 == (const char *)v6) goto LABEL_17;\n }\n if (v7 > 1) {\n v9 = v20;\n v10 = v7 - 1;\n v11 = 0;\n do {\n while (++v11 >= v7) {\n ++v9;\n if (v10 == v11) goto LABEL_14;\n }\n v12 = v9;\n do {\n v13 = *v9;\n v14 = v12[1];\n if (*v9 > v14) {\n *v9 = v14;\n v12[1] = v13;\n }\n ++v12;\n } while (&v9[v10 - v11 + 1] != v12);\n ++v9;\n } while (v10 != v11);\n LABEL_14:\n if (v5 > 0) {\n v15 = v5++;\n v4[v15] = 32;\n }\n goto LABEL_16;\n }\n if (v5 > 0) {\n v19 = v5++;\n v4[v19] = 32;\n }\n if (v7 != 1) {\n v7 = 0;\n goto LABEL_4;\n }\n LABEL_16:\n v16 = (unsigned int)v7;\n ++v1;\n v17 = &v4[v5];\n v5 += v7;\n v7 = 0;\n memcpy(v17, v20, v16);\n if (v1 == (const char *)v6) {\n LABEL_17:\n v3 = &v4[v5];\n break;\n }\n }\n }\n *v3 = 0;\n return v4;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1) {\n const char *v1;\n int v2;\n uint8_t *v3;\n uint8_t *v4;\n int v5;\n long long v6;\n int v7;\n long long v8;\n char *v9;\n int v10;\n int v11;\n char *v12;\n char v13;\n char v14;\n long long v15;\n unsigned int v16;\n uint8_t *v17;\n long long v19;\n uint8_t v20[56];\n unsigned long long v21;\n v1 = a1;\n v21 = __readfsqword(40u);\n v2 = strlen(a1);\n v3 = malloc(v2 + 2);\n v4 = v3;\n if (v2 >= 0) {\n v5 = 0;\n v6 = (long long)&a1[v2 + 1];\n v7 = 0;\n while (1) {\n while ((*v1 & 223) != 0) {\n v8 = v7++;\n v20[v8] = *v1;\n LABEL_4:\n if (++v1 == (const char *)v6) goto LABEL_17;\n }\n if (v7 > 1) {\n v9 = v20;\n v10 = v7 - 1;\n v11 = 0;\n do {\n while (++v11 >= v7) {\n ++v9;\n if (v10 == v11) goto LABEL_14;\n }\n v12 = v9;\n do {\n v13 = *v9;\n v14 = v12[1];\n if (*v9 > v14) {\n *v9 = v14;\n v12[1] = v13;\n }\n ++v12;\n } while (&v9[v10 - v11 + 1] != v12);\n ++v9;\n } while (v10 != v11);\n LABEL_14:\n if (v5 > 0) {\n v15 = v5++;\n v4[v15] = 32;\n }\n goto LABEL_16;\n }\n if (v5 > 0) {\n v19 = v5++;\n v4[v19] = 32;\n }\n if (v7 != 1) {\n v7 = 0;\n goto LABEL_4;\n }\n LABEL_16:\n v16 = (unsigned int)v7;\n ++v1;\n v17 = &v4[v5];\n v5 += v7;\n v7 = 0;\n memcpy(v17, v20, v16);\n if (v1 == (const char *)v6) {\n LABEL_17:\n v3 = &v4[v5];\n break;\n }\n }\n }\n *v3 = 0;\n return v4;\n}" + }, + { + "index": "HumanEval-C-87", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int **func0(int **lst, int lst_size, int *row_sizes, int x, int *return_size) {\n int **out = (int **)malloc(100 * sizeof(int *));\n int count = 0;\n for (int i = 0; i < lst_size; i++) {\n for (int j = row_sizes[i] - 1; j >= 0; j--) {\n if (lst[i][j] == x) {\n out[count] = (int *)malloc(2 * sizeof(int));\n out[count][0] = i;\n out[count][1] = j;\n count++;\n }\n }\n }\n *return_size = count;\n return out;\n}", + "test": "#include \n#include \n#include \n\nint issame(int **a, int aSize, int **b, int bSize) {\n if (aSize != bSize) return 0;\n\n for (int i = 0; i < aSize; i++) {\n if (a[i][0] != b[i][0] || a[i][1] != b[i][1]) return 0;\n }\n return 1;\n}\n\nvoid free_result(int **result, int size) {\n for (int i = 0; i < size; ++i) {\n free(result[i]);\n }\n free(result);\n}\n\nint main() {\n int rows, returnSize;\n int **result;\n\n // Test case 1\n rows = 3;\n int cols1[] = {6, 6, 6};\n int *lst1[] = {(const int[]){1,2,3,4,5,6}, (const int[]){1,2,3,4,1,6}, (const int[]){1,2,3,4,5,1}};\n int *expected1[] = {(const int[]){0, 0}, (const int[]){1, 4}, (const int[]){1, 0}, (const int[]){2, 5}, (const int[]){2, 0}};\n result = func0(lst1, rows, cols1, 1, &returnSize);\n assert(issame(result, returnSize, expected1, 5));\n free_result(result, returnSize);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 48h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov [rbp+var_48], rdx\nmov [rbp+var_40], ecx\nmov [rbp+var_50], r8\nmov edi, 320h; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_24], 0\nmov [rbp+var_20], 0\njmp loc_12A9\nloc_11E9:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax]\nsub eax, 1\nmov [rbp+var_1C], eax\njmp loc_129B\nloc_120A:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_40], eax\njnz short loc_1297\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nlea rbx, [rdx+rax]\nmov edi, 8; size\ncall _malloc\nmov [rbx], rax\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_20]\nmov [rax], edx\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nlea rdx, [rax+4]\nmov eax, [rbp+var_1C]\nmov [rdx], eax\nadd [rbp+var_24], 1\nloc_1297:\nsub [rbp+var_1C], 1\nloc_129B:\ncmp [rbp+var_1C], 0\njns loc_120A\nadd [rbp+var_20], 1\nloc_12A9:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_3C]\njl loc_11E9\nmov rax, [rbp+var_50]\nmov edx, [rbp+var_24]\nmov [rax], edx\nmov rax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, int a2, __int64 a3, int a4, _DWORD *a5)\n{\n int v9; // [rsp+2Ch] [rbp-24h]\n int i; // [rsp+30h] [rbp-20h]\n int j; // [rsp+34h] [rbp-1Ch]\n _QWORD *v12; // [rsp+38h] [rbp-18h]\n\n v12 = malloc(0x320uLL);\n v9 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = *(_DWORD *)(4LL * i + a3) - 1; j >= 0; --j )\n {\n if ( a4 == *(_DWORD *)(4LL * j + *(_QWORD *)(8LL * i + a1)) )\n {\n v12[v9] = malloc(8uLL);\n *(_DWORD *)v12[v9] = i;\n *(_DWORD *)(v12[v9++] + 4LL) = j;\n }\n }\n }\n *a5 = v9;\n return v12;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 48h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov [rbp+var_48], rdx\nmov [rbp+var_40], ecx\nmov [rbp+var_50], r8\nmov edi, 320h; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_24], 0\nmov [rbp+var_20], 0\njmp loc_12A9\nloc_11E9:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax]\nsub eax, 1\nmov [rbp+var_1C], eax\njmp loc_129B\nloc_120A:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_40], eax\njnz short loc_1297\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nlea rbx, [rdx+rax]\nmov edi, 8; size\ncall _malloc\nmov [rbx], rax\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_20]\nmov [rax], edx\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nlea rdx, [rax+4]\nmov eax, [rbp+var_1C]\nmov [rdx], eax\nadd [rbp+var_24], 1\nloc_1297:\nsub [rbp+var_1C], 1\nloc_129B:\ncmp [rbp+var_1C], 0\njns loc_120A\nadd [rbp+var_20], 1\nloc_12A9:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_3C]\njl loc_11E9\nmov rax, [rbp+var_50]\nmov edx, [rbp+var_24]\nmov [rax], edx\nmov rax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11A9(__int64 a1, int a2, __int64 a3, int a4, _DWORD *a5)\n{\n int v9; // [rsp+2Ch] [rbp-24h]\n int i; // [rsp+30h] [rbp-20h]\n int j; // [rsp+34h] [rbp-1Ch]\n _QWORD *v12; // [rsp+38h] [rbp-18h]\n\n v12 = malloc(0x320uLL);\n v9 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = *(_DWORD *)(4LL * i + a3) - 1; j >= 0; --j )\n {\n if ( a4 == *(_DWORD *)(4LL * j + *(_QWORD *)(8LL * i + a1)) )\n {\n v12[v9] = malloc(8uLL);\n *(_DWORD *)v12[v9] = i;\n *(_DWORD *)(v12[v9++] + 4LL) = j;\n }\n }\n }\n *a5 = v9;\n return v12;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11A9(long long a1, int a2, long long a3, int a4, uint32_t *a5) {\n int v9;\n int i;\n int j;\n uint64_t *v12;\n v12 = malloc(800uLL);\n v9 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = *(uint32_t *)(4LL * i + a3) - 1; j >= 0; --j) {\n if (a4 == *(uint32_t *)(4LL * j + *(uint64_t *)(8LL * i + a1))) {\n v12[v9] = malloc(8uLL);\n *(uint32_t *)v12[v9] = i;\n *(uint32_t *)(v12[v9++] + 4LL) = j;\n }\n }\n }\n *a5 = v9;\n return v12;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, int a2, long long a3, int a4, uint32_t *a5) {\n int v9;\n int i;\n int j;\n uint64_t *v12;\n v12 = malloc(800uLL);\n v9 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = *(uint32_t *)(4LL * i + a3) - 1; j >= 0; --j) {\n if (a4 == *(uint32_t *)(4LL * j + *(uint64_t *)(8LL * i + a1))) {\n v12[v9] = malloc(8uLL);\n *(uint32_t *)v12[v9] = i;\n *(uint32_t *)(v12[v9++] + 4LL) = j;\n }\n }\n }\n *a5 = v9;\n return v12;\n}" + }, + { + "index": "HumanEval-C-87", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int **func0(int **lst, int lst_size, int *row_sizes, int x, int *return_size) {\n int **out = (int **)malloc(100 * sizeof(int *));\n int count = 0;\n for (int i = 0; i < lst_size; i++) {\n for (int j = row_sizes[i] - 1; j >= 0; j--) {\n if (lst[i][j] == x) {\n out[count] = (int *)malloc(2 * sizeof(int));\n out[count][0] = i;\n out[count][1] = j;\n count++;\n }\n }\n }\n *return_size = count;\n return out;\n}", + "test": "#include \n#include \n#include \n\nint issame(int **a, int aSize, int **b, int bSize) {\n if (aSize != bSize) return 0;\n\n for (int i = 0; i < aSize; i++) {\n if (a[i][0] != b[i][0] || a[i][1] != b[i][1]) return 0;\n }\n return 1;\n}\n\nvoid free_result(int **result, int size) {\n for (int i = 0; i < size; ++i) {\n free(result[i]);\n }\n free(result);\n}\n\nint main() {\n int rows, returnSize;\n int **result;\n\n // Test case 1\n rows = 3;\n int cols1[] = {6, 6, 6};\n int *lst1[] = {(const int[]){1,2,3,4,5,6}, (const int[]){1,2,3,4,1,6}, (const int[]){1,2,3,4,5,1}};\n int *expected1[] = {(const int[]){0, 0}, (const int[]){1, 4}, (const int[]){1, 0}, (const int[]){2, 5}, (const int[]){2, 0}};\n result = func0(lst1, rows, cols1, 1, &returnSize);\n assert(issame(result, returnSize, expected1, 5));\n free_result(result, returnSize);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 38h\nmov r12, rdi\nmov ebx, esi\nmov [rsp+68h+var_50], rdx\nmov r13d, ecx\nmov [rsp+68h+var_40], r8\nmov edi, 320h; size\ncall _malloc\nmov [rsp+68h+var_58], rax\ntest ebx, ebx\njle loc_1269\nmovsxd rax, ebx\nmov [rsp+68h+var_48], rax\nmov r15d, 0\nmov r14d, 0\njmp short loc_1247\nloc_11FA:\nmov edi, 8; size\ncall _malloc\nmovsxd rdx, r14d\nmov rcx, [rsp+68h+var_58]\nmov [rcx+rdx*8], rax\nmov esi, [rsp+68h+var_60]\nmov [rax], esi\nmov [rax+4], ebx\nadd r14d, 1\nloc_121D:\nsub ebx, 1\nsub rbp, 4\ncmp ebx, 0FFFFFFFFh\njz short loc_1235\nloc_1229:\nmov rax, [r12]\ncmp [rax+rbp], r13d\njnz short loc_121D\njmp short loc_11FA\nloc_1235:\nadd r15, 1\nadd r12, 8\nmov rax, [rsp+68h+var_48]\ncmp r15, rax\njz short loc_126F\nloc_1247:\nmov [rsp+68h+var_60], r15d\nmov rax, [rsp+68h+var_50]\nmov eax, [rax+r15*4]\nmov [rsp+68h+var_5C], eax\nmov ebx, eax\nsub ebx, 1\njs short loc_1235\nmovsxd rbp, ebx\nshl rbp, 2\njmp short loc_1229\nloc_1269:\nmov r14d, 0\nloc_126F:\nmov rax, [rsp+68h+var_40]\nmov [rax], r14d\nmov rax, [rsp+68h+var_58]\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(_QWORD *a1, int a2, __int64 a3, int a4, _DWORD *a5)\n{\n __int64 v7; // r15\n int v8; // r14d\n _DWORD *v9; // rax\n int v10; // ebx\n __int64 v11; // rbp\n _QWORD *v13; // [rsp+10h] [rbp-58h]\n\n v13 = malloc(0x320uLL);\n if ( a2 <= 0 )\n {\n v8 = 0;\n }\n else\n {\n v7 = 0LL;\n v8 = 0;\n do\n {\n v10 = *(_DWORD *)(a3 + 4 * v7) - 1;\n if ( v10 >= 0 )\n {\n v11 = 4LL * v10;\n do\n {\n if ( *(_DWORD *)(*a1 + v11) == a4 )\n {\n v9 = malloc(8uLL);\n v13[v8] = v9;\n *v9 = v7;\n v9[1] = v10;\n ++v8;\n }\n --v10;\n v11 -= 4LL;\n }\n while ( v10 != -1 );\n }\n ++v7;\n ++a1;\n }\n while ( v7 != a2 );\n }\n *a5 = v8;\n return v13;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 38h\nmov r12, rdi\nmov ebx, esi\nmov [rsp+68h+var_50], rdx\nmov r13d, ecx\nmov [rsp+68h+var_40], r8\nmov edi, 320h; size\ncall _malloc\nmov [rsp+68h+var_58], rax\ntest ebx, ebx\njle loc_1269\nmovsxd rax, ebx\nmov [rsp+68h+var_48], rax\nmov r15d, 0\nmov r14d, 0\njmp short loc_1247\nloc_11FA:\nmov edi, 8; size\ncall _malloc\nmovsxd rdx, r14d\nmov rcx, [rsp+68h+var_58]\nmov [rcx+rdx*8], rax\nmov esi, [rsp+68h+var_60]\nmov [rax], esi\nmov [rax+4], ebx\nadd r14d, 1\nloc_121D:\nsub ebx, 1\nsub rbp, 4\ncmp ebx, 0FFFFFFFFh\njz short loc_1235\nloc_1229:\nmov rax, [r12]\ncmp [rax+rbp], r13d\njnz short loc_121D\njmp short loc_11FA\nloc_1235:\nadd r15, 1\nadd r12, 8\nmov rax, [rsp+68h+var_48]\ncmp r15, rax\njz short loc_126F\nloc_1247:\nmov [rsp+68h+var_60], r15d\nmov rax, [rsp+68h+var_50]\nmov eax, [rax+r15*4]\nmov [rsp+68h+var_5C], eax\nmov ebx, eax\nsub ebx, 1\njs short loc_1235\nmovsxd rbp, ebx\nshl rbp, 2\njmp short loc_1229\nloc_1269:\nmov r14d, 0\nloc_126F:\nmov rax, [rsp+68h+var_40]\nmov [rax], r14d\nmov rax, [rsp+68h+var_58]\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11A9(_QWORD *a1, int a2, __int64 a3, int a4, _DWORD *a5)\n{\n __int64 v7; // r15\n int v8; // r14d\n _DWORD *v9; // rax\n int v10; // ebx\n __int64 v11; // rbp\n _QWORD *v13; // [rsp+10h] [rbp-58h]\n\n v13 = malloc(0x320uLL);\n if ( a2 <= 0 )\n {\n v8 = 0;\n }\n else\n {\n v7 = 0LL;\n v8 = 0;\n do\n {\n v10 = *(_DWORD *)(a3 + 4 * v7) - 1;\n if ( v10 >= 0 )\n {\n v11 = 4LL * v10;\n do\n {\n if ( *(_DWORD *)(*a1 + v11) == a4 )\n {\n v9 = malloc(8uLL);\n v13[v8] = v9;\n *v9 = v7;\n v9[1] = v10;\n ++v8;\n }\n --v10;\n v11 -= 4LL;\n }\n while ( v10 != -1 );\n }\n ++v7;\n ++a1;\n }\n while ( v7 != a2 );\n }\n *a5 = v8;\n return v13;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11A9(uint64_t *a1, int a2, long long a3, int a4, uint32_t *a5) {\n long long v7;\n int v8;\n uint32_t *v9;\n int v10;\n long long v11;\n uint64_t *v13;\n v13 = malloc(800uLL);\n if (a2 <= 0) {\n v8 = 0;\n } else {\n v7 = 0LL;\n v8 = 0;\n do {\n v10 = *(uint32_t *)(a3 + 4 * v7) - 1;\n if (v10 >= 0) {\n v11 = 4LL * v10;\n do {\n if (*(uint32_t *)(*a1 + v11) == a4) {\n v9 = malloc(8uLL);\n v13[v8] = v9;\n *v9 = v7;\n v9[1] = v10;\n ++v8;\n }\n --v10;\n v11 -= 4LL;\n } while (v10 != -1);\n }\n ++v7;\n ++a1;\n } while (v7 != a2);\n }\n *a5 = v8;\n return v13;\n}", + "ida_pseudo_norm": "uint64_t *func0(uint64_t *a1, int a2, long long a3, int a4, uint32_t *a5) {\n long long v7;\n int v8;\n uint32_t *v9;\n int v10;\n long long v11;\n uint64_t *v13;\n v13 = malloc(800uLL);\n if (a2 <= 0) {\n v8 = 0;\n } else {\n v7 = 0LL;\n v8 = 0;\n do {\n v10 = *(uint32_t *)(a3 + 4 * v7) - 1;\n if (v10 >= 0) {\n v11 = 4LL * v10;\n do {\n if (*(uint32_t *)(*a1 + v11) == a4) {\n v9 = malloc(8uLL);\n v13[v8] = v9;\n *v9 = v7;\n v9[1] = v10;\n ++v8;\n }\n --v10;\n v11 -= 4LL;\n } while (v10 != -1);\n }\n ++v7;\n ++a1;\n } while (v7 != a2);\n }\n *a5 = v8;\n return v13;\n}" + }, + { + "index": "HumanEval-C-87", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int **func0(int **lst, int lst_size, int *row_sizes, int x, int *return_size) {\n int **out = (int **)malloc(100 * sizeof(int *));\n int count = 0;\n for (int i = 0; i < lst_size; i++) {\n for (int j = row_sizes[i] - 1; j >= 0; j--) {\n if (lst[i][j] == x) {\n out[count] = (int *)malloc(2 * sizeof(int));\n out[count][0] = i;\n out[count][1] = j;\n count++;\n }\n }\n }\n *return_size = count;\n return out;\n}", + "test": "#include \n#include \n#include \n\nint issame(int **a, int aSize, int **b, int bSize) {\n if (aSize != bSize) return 0;\n\n for (int i = 0; i < aSize; i++) {\n if (a[i][0] != b[i][0] || a[i][1] != b[i][1]) return 0;\n }\n return 1;\n}\n\nvoid free_result(int **result, int size) {\n for (int i = 0; i < size; ++i) {\n free(result[i]);\n }\n free(result);\n}\n\nint main() {\n int rows, returnSize;\n int **result;\n\n // Test case 1\n rows = 3;\n int cols1[] = {6, 6, 6};\n int *lst1[] = {(const int[]){1,2,3,4,5,6}, (const int[]){1,2,3,4,1,6}, (const int[]){1,2,3,4,5,1}};\n int *expected1[] = {(const int[]){0, 0}, (const int[]){1, 4}, (const int[]){1, 0}, (const int[]){2, 5}, (const int[]){2, 0}};\n result = func0(lst1, rows, cols1, 1, &returnSize);\n assert(issame(result, returnSize, expected1, 5));\n free_result(result, returnSize);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12d, ecx\npush rbp\npush rbx\nmov ebx, esi\nsub rsp, 38h\nmov [rsp+68h+var_48], rdi\nmov edi, 320h; size\nmov [rsp+68h+var_58], rdx\nmov [rsp+68h+var_40], r8\ncall _malloc\nmov [rsp+68h+var_60], rax\ntest ebx, ebx\njle loc_145A\nmovsxd rax, ebx\nxor r14d, r14d\nxor r15d, r15d\nmov [rsp+68h+var_50], rax\nnop dword ptr [rax+rax+00h]\nloc_13D0:\nmov rax, [rsp+68h+var_58]\nmov ebx, r14d\nmov eax, [rax+r14*4]\nmov edx, eax\nmov [rsp+68h+var_64], eax\nsub edx, 1\njs short loc_1430\nmov rax, [rsp+68h+var_48]\nmovsxd rbp, edx\nmov r13, [rax+r14*8]\njmp short loc_1400\nloc_13F8:\nsub rbp, 1\ntest ebp, ebp\njs short loc_1430\nloc_1400:\ncmp [r13+rbp*4+0], r12d\njnz short loc_13F8\nmov edi, 8; size\ncall _malloc\nmov rcx, [rsp+68h+var_60]\nmovsxd rdi, r15d\nadd r15d, 1\nmov [rax+4], ebp\nsub rbp, 1\nmov [rcx+rdi*8], rax\nmov [rax], ebx\ntest ebp, ebp\njns short loc_1400\nxchg ax, ax\nloc_1430:\nmov rax, [rsp+68h+var_50]\nadd r14, 1\ncmp r14, rax\njnz short loc_13D0\nloc_143E:\nmov rax, [rsp+68h+var_40]\nmov [rax], r15d\nmov rax, [rsp+68h+var_60]\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_145A:\nxor r15d, r15d\njmp short loc_143E", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, int a2, __int64 a3, int a4, _DWORD *a5)\n{\n __int64 v6; // r14\n int v7; // r15d\n int v8; // edx\n __int64 v9; // rbp\n __int64 v10; // r13\n _DWORD *v11; // rax\n __int64 v12; // rdi\n _QWORD *v14; // [rsp+8h] [rbp-60h]\n\n v14 = malloc(0x320uLL);\n if ( a2 <= 0 )\n {\n v7 = 0;\n }\n else\n {\n v6 = 0LL;\n v7 = 0;\n do\n {\n v8 = *(_DWORD *)(a3 + 4 * v6) - 1;\n if ( v8 >= 0 )\n {\n v9 = v8;\n v10 = *(_QWORD *)(a1 + 8 * v6);\n do\n {\n while ( *(_DWORD *)(v10 + 4 * v9) != a4 )\n {\n if ( (int)--v9 < 0 )\n goto LABEL_8;\n }\n v11 = malloc(8uLL);\n v12 = v7++;\n v11[1] = v9--;\n v14[v12] = v11;\n *v11 = v6;\n }\n while ( (int)v9 >= 0 );\n }\nLABEL_8:\n ++v6;\n }\n while ( v6 != a2 );\n }\n *a5 = v7;\n return v14;\n}", + "ida_strip_asm": "sub_1380:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12d, ecx\npush rbp\npush rbx\nmov ebx, esi\nsub rsp, 38h\nmov [rsp+68h+var_48], rdi\nmov edi, 320h; size\nmov [rsp+68h+var_58], rdx\nmov [rsp+68h+var_40], r8\ncall _malloc\nmov [rsp+68h+var_60], rax\ntest ebx, ebx\njle loc_145A\nmovsxd rax, ebx\nxor r14d, r14d\nxor r15d, r15d\nmov [rsp+68h+var_50], rax\nnop dword ptr [rax+rax+00h]\nloc_13D0:\nmov rax, [rsp+68h+var_58]\nmov ebx, r14d\nmov eax, [rax+r14*4]\nmov edx, eax\nmov [rsp+68h+var_64], eax\nsub edx, 1\njs short loc_1430\nmov rax, [rsp+68h+var_48]\nmovsxd rbp, edx\nmov r13, [rax+r14*8]\njmp short loc_1400\nloc_13F8:\nsub rbp, 1\ntest ebp, ebp\njs short loc_1430\nloc_1400:\ncmp [r13+rbp*4+0], r12d\njnz short loc_13F8\nmov edi, 8; size\ncall _malloc\nmov rcx, [rsp+68h+var_60]\nmovsxd rdi, r15d\nadd r15d, 1\nmov [rax+4], ebp\nsub rbp, 1\nmov [rcx+rdi*8], rax\nmov [rax], ebx\ntest ebp, ebp\njns short loc_1400\nxchg ax, ax\nloc_1430:\nmov rax, [rsp+68h+var_50]\nadd r14, 1\ncmp r14, rax\njnz short loc_13D0\nloc_143E:\nmov rax, [rsp+68h+var_40]\nmov [rax], r15d\nmov rax, [rsp+68h+var_60]\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_145A:\nxor r15d, r15d\njmp short loc_143E", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1380(__int64 a1, int a2, __int64 a3, int a4, _DWORD *a5)\n{\n __int64 v6; // r14\n int v7; // r15d\n int v8; // edx\n __int64 v9; // rbp\n __int64 v10; // r13\n _DWORD *v11; // rax\n __int64 v12; // rdi\n _QWORD *v14; // [rsp+8h] [rbp-60h]\n\n v14 = malloc(0x320uLL);\n if ( a2 <= 0 )\n {\n v7 = 0;\n }\n else\n {\n v6 = 0LL;\n v7 = 0;\n do\n {\n v8 = *(_DWORD *)(a3 + 4 * v6) - 1;\n if ( v8 >= 0 )\n {\n v9 = v8;\n v10 = *(_QWORD *)(a1 + 8 * v6);\n do\n {\n while ( *(_DWORD *)(v10 + 4 * v9) != a4 )\n {\n if ( (int)--v9 < 0 )\n goto LABEL_8;\n }\n v11 = malloc(8uLL);\n v12 = v7++;\n v11[1] = v9--;\n v14[v12] = v11;\n *v11 = v6;\n }\n while ( (int)v9 >= 0 );\n }\nLABEL_8:\n ++v6;\n }\n while ( v6 != a2 );\n }\n *a5 = v7;\n return v14;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1380(long long a1, int a2, long long a3, int a4, uint32_t *a5) {\n long long v6;\n int v7;\n int v8;\n long long v9;\n long long v10;\n uint32_t *v11;\n long long v12;\n uint64_t *v14;\n v14 = malloc(800uLL);\n if (a2 <= 0) {\n v7 = 0;\n } else {\n v6 = 0LL;\n v7 = 0;\n do {\n v8 = *(uint32_t *)(a3 + 4 * v6) - 1;\n if (v8 >= 0) {\n v9 = v8;\n v10 = *(uint64_t *)(a1 + 8 * v6);\n do {\n while (*(uint32_t *)(v10 + 4 * v9) != a4) {\n if ((int)--v9 < 0) goto LABEL_8;\n }\n v11 = malloc(8uLL);\n v12 = v7++;\n v11[1] = v9--;\n v14[v12] = v11;\n *v11 = v6;\n } while ((int)v9 >= 0);\n }\n LABEL_8:\n ++v6;\n } while (v6 != a2);\n }\n *a5 = v7;\n return v14;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, int a2, long long a3, int a4, uint32_t *a5) {\n long long v6;\n int v7;\n int v8;\n long long v9;\n long long v10;\n uint32_t *v11;\n long long v12;\n uint64_t *v14;\n v14 = malloc(800uLL);\n if (a2 <= 0) {\n v7 = 0;\n } else {\n v6 = 0LL;\n v7 = 0;\n do {\n v8 = *(uint32_t *)(a3 + 4 * v6) - 1;\n if (v8 >= 0) {\n v9 = v8;\n v10 = *(uint64_t *)(a1 + 8 * v6);\n do {\n while (*(uint32_t *)(v10 + 4 * v9) != a4) {\n if ((int)--v9 < 0) goto LABEL_8;\n }\n v11 = malloc(8uLL);\n v12 = v7++;\n v11[1] = v9--;\n v14[v12] = v11;\n *v11 = v6;\n } while ((int)v9 >= 0);\n }\n LABEL_8:\n ++v6;\n } while (v6 != a2);\n }\n *a5 = v7;\n return v14;\n}" + }, + { + "index": "HumanEval-C-87", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int **func0(int **lst, int lst_size, int *row_sizes, int x, int *return_size) {\n int **out = (int **)malloc(100 * sizeof(int *));\n int count = 0;\n for (int i = 0; i < lst_size; i++) {\n for (int j = row_sizes[i] - 1; j >= 0; j--) {\n if (lst[i][j] == x) {\n out[count] = (int *)malloc(2 * sizeof(int));\n out[count][0] = i;\n out[count][1] = j;\n count++;\n }\n }\n }\n *return_size = count;\n return out;\n}", + "test": "#include \n#include \n#include \n\nint issame(int **a, int aSize, int **b, int bSize) {\n if (aSize != bSize) return 0;\n\n for (int i = 0; i < aSize; i++) {\n if (a[i][0] != b[i][0] || a[i][1] != b[i][1]) return 0;\n }\n return 1;\n}\n\nvoid free_result(int **result, int size) {\n for (int i = 0; i < size; ++i) {\n free(result[i]);\n }\n free(result);\n}\n\nint main() {\n int rows, returnSize;\n int **result;\n\n // Test case 1\n rows = 3;\n int cols1[] = {6, 6, 6};\n int *lst1[] = {(const int[]){1,2,3,4,5,6}, (const int[]){1,2,3,4,1,6}, (const int[]){1,2,3,4,5,1}};\n int *expected1[] = {(const int[]){0, 0}, (const int[]){1, 4}, (const int[]){1, 0}, (const int[]){2, 5}, (const int[]){2, 0}};\n result = func0(lst1, rows, cols1, 1, &returnSize);\n assert(issame(result, returnSize, expected1, 5));\n free_result(result, returnSize);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14d, ecx\npush r13\npush r12\nmov r12d, esi\npush rbp\npush rbx\nsub rsp, 38h\nmov [rsp+68h+var_48], rdi\nmov edi, 320h; size\nmov [rsp+68h+var_58], rdx\nmov [rsp+68h+var_40], r8\ncall _malloc\nmov [rsp+68h+var_60], rax\ntest r12d, r12d\njle loc_13E7\nmovsxd rax, r12d\nxor r15d, r15d\nxor r12d, r12d\nmov [rsp+68h+var_50], rax\nnop dword ptr [rax]\nloc_1360:\nmov rax, [rsp+68h+var_58]\nmov ebx, r12d\nmov eax, [rax+r12*4]\nmov edx, eax\nmov [rsp+68h+var_64], eax\nsub edx, 1\njs short loc_13C0\nmov rax, [rsp+68h+var_48]\nmovsxd rbp, edx\nmov r13, [rax+r12*8]\njmp short loc_1390\nloc_1388:\nsub rbp, 1\ntest ebp, ebp\njs short loc_13C0\nloc_1390:\ncmp [r13+rbp*4+0], r14d\njnz short loc_1388\nmov edi, 8; size\ncall _malloc\nmov rcx, [rsp+68h+var_60]\nmovsxd rdi, r15d\nadd r15d, 1\nmov [rax+4], ebp\nsub rbp, 1\nmov [rcx+rdi*8], rax\nmov [rax], ebx\ntest ebp, ebp\njns short loc_1390\nxchg ax, ax\nloc_13C0:\nadd r12, 1\ncmp [rsp+68h+var_50], r12\njnz short loc_1360\nloc_13CB:\nmov rax, [rsp+68h+var_40]\nmov [rax], r15d\nmov rax, [rsp+68h+var_60]\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_13E7:\nxor r15d, r15d\njmp short loc_13CB", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, int a2, __int64 a3, int a4, _DWORD *a5)\n{\n int v6; // r15d\n __int64 i; // r12\n int v8; // edx\n __int64 v9; // rbp\n __int64 v10; // r13\n _DWORD *v11; // rax\n __int64 v12; // rdi\n _QWORD *v14; // [rsp+8h] [rbp-60h]\n\n v14 = malloc(0x320uLL);\n if ( a2 <= 0 )\n {\n v6 = 0;\n }\n else\n {\n v6 = 0;\n for ( i = 0LL; i != a2; ++i )\n {\n v8 = *(_DWORD *)(a3 + 4 * i) - 1;\n if ( v8 >= 0 )\n {\n v9 = v8;\n v10 = *(_QWORD *)(a1 + 8 * i);\n do\n {\n while ( *(_DWORD *)(v10 + 4 * v9) != a4 )\n {\n if ( (int)--v9 < 0 )\n goto LABEL_8;\n }\n v11 = malloc(8uLL);\n v12 = v6++;\n v11[1] = v9--;\n v14[v12] = v11;\n *v11 = i;\n }\n while ( (int)v9 >= 0 );\n }\nLABEL_8:\n ;\n }\n }\n *a5 = v6;\n return v14;\n}", + "ida_strip_asm": "sub_1310:\nendbr64\npush r15\npush r14\nmov r14d, ecx\npush r13\npush r12\nmov r12d, esi\npush rbp\npush rbx\nsub rsp, 38h\nmov [rsp+68h+var_48], rdi\nmov edi, 320h; size\nmov [rsp+68h+var_58], rdx\nmov [rsp+68h+var_40], r8\ncall _malloc\nmov [rsp+68h+var_60], rax\ntest r12d, r12d\njle loc_13E7\nmovsxd rax, r12d\nxor r15d, r15d\nxor r12d, r12d\nmov [rsp+68h+var_50], rax\nnop dword ptr [rax]\nloc_1360:\nmov rax, [rsp+68h+var_58]\nmov ebx, r12d\nmov eax, [rax+r12*4]\nmov edx, eax\nmov [rsp+68h+var_64], eax\nsub edx, 1\njs short loc_13C0\nmov rax, [rsp+68h+var_48]\nmovsxd rbp, edx\nmov r13, [rax+r12*8]\njmp short loc_1390\nloc_1388:\nsub rbp, 1\ntest ebp, ebp\njs short loc_13C0\nloc_1390:\ncmp [r13+rbp*4+0], r14d\njnz short loc_1388\nmov edi, 8; size\ncall _malloc\nmov rcx, [rsp+68h+var_60]\nmovsxd rdi, r15d\nadd r15d, 1\nmov [rax+4], ebp\nsub rbp, 1\nmov [rcx+rdi*8], rax\nmov [rax], ebx\ntest ebp, ebp\njns short loc_1390\nxchg ax, ax\nloc_13C0:\nadd r12, 1\ncmp [rsp+68h+var_50], r12\njnz short loc_1360\nloc_13CB:\nmov rax, [rsp+68h+var_40]\nmov [rax], r15d\nmov rax, [rsp+68h+var_60]\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_13E7:\nxor r15d, r15d\njmp short loc_13CB", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1310(__int64 a1, int a2, __int64 a3, int a4, _DWORD *a5)\n{\n int v6; // r15d\n __int64 i; // r12\n int v8; // edx\n __int64 v9; // rbp\n __int64 v10; // r13\n _DWORD *v11; // rax\n __int64 v12; // rdi\n _QWORD *v14; // [rsp+8h] [rbp-60h]\n\n v14 = malloc(0x320uLL);\n if ( a2 <= 0 )\n {\n v6 = 0;\n }\n else\n {\n v6 = 0;\n for ( i = 0LL; i != a2; ++i )\n {\n v8 = *(_DWORD *)(a3 + 4 * i) - 1;\n if ( v8 >= 0 )\n {\n v9 = v8;\n v10 = *(_QWORD *)(a1 + 8 * i);\n do\n {\n while ( *(_DWORD *)(v10 + 4 * v9) != a4 )\n {\n if ( (int)--v9 < 0 )\n goto LABEL_8;\n }\n v11 = malloc(8uLL);\n v12 = v6++;\n v11[1] = v9--;\n v14[v12] = v11;\n *v11 = i;\n }\n while ( (int)v9 >= 0 );\n }\nLABEL_8:\n ;\n }\n }\n *a5 = v6;\n return v14;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1310(long long a1, int a2, long long a3, int a4, uint32_t *a5) {\n int v6;\n long long i;\n int v8;\n long long v9;\n long long v10;\n uint32_t *v11;\n long long v12;\n uint64_t *v14;\n v14 = malloc(800uLL);\n if (a2 <= 0) {\n v6 = 0;\n } else {\n v6 = 0;\n for (i = 0LL; i != a2; ++i) {\n v8 = *(uint32_t *)(a3 + 4 * i) - 1;\n if (v8 >= 0) {\n v9 = v8;\n v10 = *(uint64_t *)(a1 + 8 * i);\n do {\n while (*(uint32_t *)(v10 + 4 * v9) != a4) {\n if ((int)--v9 < 0) goto LABEL_8;\n }\n v11 = malloc(8uLL);\n v12 = v6++;\n v11[1] = v9--;\n v14[v12] = v11;\n *v11 = i;\n } while ((int)v9 >= 0);\n }\n LABEL_8:;\n }\n }\n *a5 = v6;\n return v14;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, int a2, long long a3, int a4, uint32_t *a5) {\n int v6;\n long long i;\n int v8;\n long long v9;\n long long v10;\n uint32_t *v11;\n long long v12;\n uint64_t *v14;\n v14 = malloc(800uLL);\n if (a2 <= 0) {\n v6 = 0;\n } else {\n v6 = 0;\n for (i = 0LL; i != a2; ++i) {\n v8 = *(uint32_t *)(a3 + 4 * i) - 1;\n if (v8 >= 0) {\n v9 = v8;\n v10 = *(uint64_t *)(a1 + 8 * i);\n do {\n while (*(uint32_t *)(v10 + 4 * v9) != a4) {\n if ((int)--v9 < 0) goto LABEL_8;\n }\n v11 = malloc(8uLL);\n v12 = v6++;\n v11[1] = v9--;\n v14[v12] = v11;\n *v11 = i;\n } while ((int)v9 >= 0);\n }\n LABEL_8:;\n }\n }\n *a5 = v6;\n return v14;\n}" + }, + { + "index": "HumanEval-C-88", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(int *array, int size, int **out_array, int *out_size) {\n *out_size = size;\n if (size == 0) {\n *out_array = NULL;\n return;\n }\n *out_array = (int *)malloc(sizeof(int) * size);\n if (*out_array == NULL) {\n exit(1);\n }\n for (int i = 0; i < size; i++) {\n (*out_array)[i] = array[i];\n }\n int shouldSortAscending = (array[0] + array[size - 1]) % 2 == 1;\n for (int i = 0; i < size - 1; i++) {\n for (int j = i + 1; j < size; j++) {\n if (shouldSortAscending) {\n if ((*out_array)[i] > (*out_array)[j]) {\n int temp = (*out_array)[i];\n (*out_array)[i] = (*out_array)[j];\n (*out_array)[j] = temp;\n }\n } else {\n if ((*out_array)[i] < (*out_array)[j]) {\n int temp = (*out_array)[i];\n (*out_array)[i] = (*out_array)[j];\n (*out_array)[j] = temp;\n }\n }\n }\n }\n}", + "test": "#include \n#include \n#include \n\nint issame(int *a, int aSize, int *b, int bSize) {\n if (aSize != bSize) return 0;\n for (int i = 0; i < aSize; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int *result, result_size;\n\n func0((const int[]){}, 0, &result, &result_size);\n assert(issame(result, result_size, (const int[]){}, 0));\n free(result);\n\n func0((const int[]){5}, 1, &result, &result_size);\n assert(issame(result, result_size, (const int[]){5}, 1));\n free(result);\n\n func0((const int[]){2, 4, 3, 0, 1, 5}, 6, &result, &result_size);\n assert(issame(result, result_size, (const int[]){0, 1, 2, 3, 4, 5}, 6));\n free(result);\n\n func0((const int[]){2, 4, 3, 0, 1, 5, 6}, 7, &result, &result_size);\n assert(issame(result, result_size, (const int[]){6, 5, 4, 3, 2, 1, 0}, 7));\n free(result);\n\n func0((const int[]){2, 1}, 2, &result, &result_size);\n assert(issame(result, result_size, (const int[]){1, 2}, 2));\n free(result);\n\n func0((const int[]){15, 42, 87, 32, 11, 0}, 6, &result, &result_size);\n assert(issame(result, result_size, (const int[]){0, 11, 15, 32, 42, 87}, 6));\n free(result);\n\n func0((const int[]){21, 14, 23, 11}, 4, &result, &result_size);\n assert(issame(result, result_size, (const int[]){23, 21, 14, 11}, 4));\n free(result);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmov [rbp+var_40], rcx\nmov rax, [rbp+var_40]\nmov edx, [rbp+var_2C]\nmov [rax], edx\ncmp [rbp+var_2C], 0\njnz short loc_1203\nmov rax, [rbp+var_38]\nmov qword ptr [rax], 0\njmp locret_141F\nloc_1203:\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov rdx, rax\nmov rax, [rbp+var_38]\nmov [rax], rdx\nmov rax, [rbp+var_38]\nmov rax, [rax]\ntest rax, rax\njnz short loc_1234\nmov edi, 1; status\ncall _exit\nloc_1234:\nmov [rbp+var_18], 0\njmp short loc_126E\nloc_123D:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov edx, [rbp+var_18]\nmovsxd rdx, edx\nshl rdx, 2\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nadd [rbp+var_18], 1\nloc_126E:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_2C]\njl short loc_123D\nmov rax, [rbp+var_28]\nmov edx, [rax]\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nlea rcx, [rax-4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\nadd edx, eax\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\ncmp eax, 1\nsetz al\nmovzx eax, al\nmov [rbp+var_C], eax\nmov [rbp+var_14], 0\njmp loc_1410\nloc_12BD:\nmov eax, [rbp+var_14]\nadd eax, 1\nmov [rbp+var_10], eax\njmp loc_1400\nloc_12CB:\ncmp [rbp+var_C], 0\njz loc_136D\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov ecx, [rbp+var_10]\nmovsxd rcx, ecx\nshl rcx, 2\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle loc_13FC\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nshl rdx, 2\nlea rcx, [rax+rdx]\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nshl rdx, 2\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nshl rdx, 2\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\njmp loc_13FC\nloc_136D:\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov ecx, [rbp+var_10]\nmovsxd rcx, ecx\nshl rcx, 2\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njge short loc_13FC\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_8], eax\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nshl rdx, 2\nlea rcx, [rax+rdx]\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nshl rdx, 2\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nshl rdx, 2\nadd rdx, rax\nmov eax, [rbp+var_8]\nmov [rdx], eax\nloc_13FC:\nadd [rbp+var_10], 1\nloc_1400:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_2C]\njl loc_12CB\nadd [rbp+var_14], 1\nloc_1410:\nmov eax, [rbp+var_2C]\nsub eax, 1\ncmp [rbp+var_14], eax\njl loc_12BD\nlocret_141F:\nleave\nretn", + "ida_pseudo": "void **__fastcall func0(_DWORD *a1, int a2, void **a3, int *a4)\n{\n void **result; // rax\n int i; // [rsp+28h] [rbp-18h]\n int j; // [rsp+2Ch] [rbp-14h]\n int k; // [rsp+30h] [rbp-10h]\n _BOOL4 v9; // [rsp+34h] [rbp-Ch]\n int v10; // [rsp+38h] [rbp-8h]\n int v11; // [rsp+3Ch] [rbp-4h]\n\n *a4 = a2;\n if ( a2 )\n {\n *a3 = malloc(4LL * a2);\n if ( !*a3 )\n exit(1);\n for ( i = 0; i < a2; ++i )\n *((_DWORD *)*a3 + i) = a1[i];\n v9 = (a1[a2 - 1] + *a1) % 2 == 1;\n for ( j = 0; ; ++j )\n {\n result = (void **)(unsigned int)(a2 - 1);\n if ( j >= (int)result )\n break;\n for ( k = j + 1; k < a2; ++k )\n {\n if ( v9 )\n {\n if ( *((_DWORD *)*a3 + j) > *((_DWORD *)*a3 + k) )\n {\n v11 = *((_DWORD *)*a3 + j);\n *((_DWORD *)*a3 + j) = *((_DWORD *)*a3 + k);\n *((_DWORD *)*a3 + k) = v11;\n }\n }\n else if ( *((_DWORD *)*a3 + j) < *((_DWORD *)*a3 + k) )\n {\n v10 = *((_DWORD *)*a3 + j);\n *((_DWORD *)*a3 + j) = *((_DWORD *)*a3 + k);\n *((_DWORD *)*a3 + k) = v10;\n }\n }\n }\n }\n else\n {\n result = a3;\n *a3 = 0LL;\n }\n return result;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmov [rbp+var_40], rcx\nmov rax, [rbp+var_40]\nmov edx, [rbp+var_2C]\nmov [rax], edx\ncmp [rbp+var_2C], 0\njnz short loc_1203\nmov rax, [rbp+var_38]\nmov qword ptr [rax], 0\njmp locret_141F\nloc_1203:\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov rdx, rax\nmov rax, [rbp+var_38]\nmov [rax], rdx\nmov rax, [rbp+var_38]\nmov rax, [rax]\ntest rax, rax\njnz short loc_1234\nmov edi, 1; status\ncall _exit\nloc_1234:\nmov [rbp+var_18], 0\njmp short loc_126E\nloc_123D:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov edx, [rbp+var_18]\nmovsxd rdx, edx\nshl rdx, 2\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nadd [rbp+var_18], 1\nloc_126E:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_2C]\njl short loc_123D\nmov rax, [rbp+var_28]\nmov edx, [rax]\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nlea rcx, [rax-4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\nadd edx, eax\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\ncmp eax, 1\nsetz al\nmovzx eax, al\nmov [rbp+var_C], eax\nmov [rbp+var_14], 0\njmp loc_1410\nloc_12BD:\nmov eax, [rbp+var_14]\nadd eax, 1\nmov [rbp+var_10], eax\njmp loc_1400\nloc_12CB:\ncmp [rbp+var_C], 0\njz loc_136D\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov ecx, [rbp+var_10]\nmovsxd rcx, ecx\nshl rcx, 2\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle loc_13FC\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nshl rdx, 2\nlea rcx, [rax+rdx]\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nshl rdx, 2\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nshl rdx, 2\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\njmp loc_13FC\nloc_136D:\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov ecx, [rbp+var_10]\nmovsxd rcx, ecx\nshl rcx, 2\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njge short loc_13FC\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_8], eax\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nshl rdx, 2\nlea rcx, [rax+rdx]\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nshl rdx, 2\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nshl rdx, 2\nadd rdx, rax\nmov eax, [rbp+var_8]\nmov [rdx], eax\nloc_13FC:\nadd [rbp+var_10], 1\nloc_1400:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_2C]\njl loc_12CB\nadd [rbp+var_14], 1\nloc_1410:\nmov eax, [rbp+var_2C]\nsub eax, 1\ncmp [rbp+var_14], eax\njl loc_12BD\nlocret_141F:\nleave\nretn", + "ida_strip_pseudo": "void **__fastcall sub_11C9(_DWORD *a1, int a2, void **a3, int *a4)\n{\n void **result; // rax\n int i; // [rsp+28h] [rbp-18h]\n int j; // [rsp+2Ch] [rbp-14h]\n int k; // [rsp+30h] [rbp-10h]\n _BOOL4 v9; // [rsp+34h] [rbp-Ch]\n int v10; // [rsp+38h] [rbp-8h]\n int v11; // [rsp+3Ch] [rbp-4h]\n\n *a4 = a2;\n if ( a2 )\n {\n *a3 = malloc(4LL * a2);\n if ( !*a3 )\n exit(1);\n for ( i = 0; i < a2; ++i )\n *((_DWORD *)*a3 + i) = a1[i];\n v9 = (a1[a2 - 1] + *a1) % 2 == 1;\n for ( j = 0; ; ++j )\n {\n result = (void **)(unsigned int)(a2 - 1);\n if ( j >= (int)result )\n break;\n for ( k = j + 1; k < a2; ++k )\n {\n if ( v9 )\n {\n if ( *((_DWORD *)*a3 + j) > *((_DWORD *)*a3 + k) )\n {\n v11 = *((_DWORD *)*a3 + j);\n *((_DWORD *)*a3 + j) = *((_DWORD *)*a3 + k);\n *((_DWORD *)*a3 + k) = v11;\n }\n }\n else if ( *((_DWORD *)*a3 + j) < *((_DWORD *)*a3 + k) )\n {\n v10 = *((_DWORD *)*a3 + j);\n *((_DWORD *)*a3 + j) = *((_DWORD *)*a3 + k);\n *((_DWORD *)*a3 + k) = v10;\n }\n }\n }\n }\n else\n {\n result = a3;\n *a3 = 0LL;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void **sub_11C9(uint32_t *a1, int a2, void **a3, int *a4) {\n void **result;\n int i;\n int j;\n int k;\n int v9;\n int v10;\n int v11;\n *a4 = a2;\n if (a2) {\n *a3 = malloc(4LL * a2);\n if (!*a3) exit(1);\n for (i = 0; i < a2; ++i) *((uint32_t *)*a3 + i) = a1[i];\n v9 = (a1[a2 - 1] + *a1) % 2 == 1;\n for (j = 0;; ++j) {\n result = (void **)(unsigned int)(a2 - 1);\n if (j >= (int)result) break;\n for (k = j + 1; k < a2; ++k) {\n if (v9) {\n if (*((uint32_t *)*a3 + j) > *((uint32_t *)*a3 + k)) {\n v11 = *((uint32_t *)*a3 + j);\n *((uint32_t *)*a3 + j) = *((uint32_t *)*a3 + k);\n *((uint32_t *)*a3 + k) = v11;\n }\n } else if (*((uint32_t *)*a3 + j) < *((uint32_t *)*a3 + k)) {\n v10 = *((uint32_t *)*a3 + j);\n *((uint32_t *)*a3 + j) = *((uint32_t *)*a3 + k);\n *((uint32_t *)*a3 + k) = v10;\n }\n }\n }\n } else {\n result = a3;\n *a3 = 0LL;\n }\n return result;\n}", + "ida_pseudo_norm": "void **func0(uint32_t *a1, int a2, void **a3, int *a4) {\n void **result;\n int i;\n int j;\n int k;\n int v9;\n int v10;\n int v11;\n *a4 = a2;\n if (a2) {\n *a3 = malloc(4LL * a2);\n if (!*a3) exit(1);\n for (i = 0; i < a2; ++i) *((uint32_t *)*a3 + i) = a1[i];\n v9 = (a1[a2 - 1] + *a1) % 2 == 1;\n for (j = 0;; ++j) {\n result = (void **)(unsigned int)(a2 - 1);\n if (j >= (int)result) break;\n for (k = j + 1; k < a2; ++k) {\n if (v9) {\n if (*((uint32_t *)*a3 + j) > *((uint32_t *)*a3 + k)) {\n v11 = *((uint32_t *)*a3 + j);\n *((uint32_t *)*a3 + j) = *((uint32_t *)*a3 + k);\n *((uint32_t *)*a3 + k) = v11;\n }\n } else if (*((uint32_t *)*a3 + j) < *((uint32_t *)*a3 + k)) {\n v10 = *((uint32_t *)*a3 + j);\n *((uint32_t *)*a3 + j) = *((uint32_t *)*a3 + k);\n *((uint32_t *)*a3 + k) = v10;\n }\n }\n }\n } else {\n result = a3;\n *a3 = 0LL;\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-88", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(int *array, int size, int **out_array, int *out_size) {\n *out_size = size;\n if (size == 0) {\n *out_array = NULL;\n return;\n }\n *out_array = (int *)malloc(sizeof(int) * size);\n if (*out_array == NULL) {\n exit(1);\n }\n for (int i = 0; i < size; i++) {\n (*out_array)[i] = array[i];\n }\n int shouldSortAscending = (array[0] + array[size - 1]) % 2 == 1;\n for (int i = 0; i < size - 1; i++) {\n for (int j = i + 1; j < size; j++) {\n if (shouldSortAscending) {\n if ((*out_array)[i] > (*out_array)[j]) {\n int temp = (*out_array)[i];\n (*out_array)[i] = (*out_array)[j];\n (*out_array)[j] = temp;\n }\n } else {\n if ((*out_array)[i] < (*out_array)[j]) {\n int temp = (*out_array)[i];\n (*out_array)[i] = (*out_array)[j];\n (*out_array)[j] = temp;\n }\n }\n }\n }\n}", + "test": "#include \n#include \n#include \n\nint issame(int *a, int aSize, int *b, int bSize) {\n if (aSize != bSize) return 0;\n for (int i = 0; i < aSize; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int *result, result_size;\n\n func0((const int[]){}, 0, &result, &result_size);\n assert(issame(result, result_size, (const int[]){}, 0));\n free(result);\n\n func0((const int[]){5}, 1, &result, &result_size);\n assert(issame(result, result_size, (const int[]){5}, 1));\n free(result);\n\n func0((const int[]){2, 4, 3, 0, 1, 5}, 6, &result, &result_size);\n assert(issame(result, result_size, (const int[]){0, 1, 2, 3, 4, 5}, 6));\n free(result);\n\n func0((const int[]){2, 4, 3, 0, 1, 5, 6}, 7, &result, &result_size);\n assert(issame(result, result_size, (const int[]){6, 5, 4, 3, 2, 1, 0}, 7));\n free(result);\n\n func0((const int[]){2, 1}, 2, &result, &result_size);\n assert(issame(result, result_size, (const int[]){1, 2}, 2));\n free(result);\n\n func0((const int[]){15, 42, 87, 32, 11, 0}, 6, &result, &result_size);\n assert(issame(result, result_size, (const int[]){0, 11, 15, 32, 42, 87}, 6));\n free(result);\n\n func0((const int[]){21, 14, 23, 11}, 4, &result, &result_size);\n assert(issame(result, result_size, (const int[]){23, 21, 14, 11}, 4));\n free(result);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdx\nmov [rcx], esi\ntest esi, esi\njnz short loc_11F2\nmov qword ptr [rdx], 0\nloc_11E7:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_11F2:\nmov r12, rdi\nmov ebp, esi\nmovsxd r13, esi\nshl r13, 2\nmov rdi, r13; size\ncall _malloc\nmov [rbx], rax\ntest rax, rax\njz short loc_125F\nmov eax, 0\ntest ebp, ebp\njle short loc_11E7\nloc_1217:\nmov ecx, [r12+rax]\nmov rdx, [rbx]\nmov [rdx+rax], ecx\nadd rax, 4\ncmp r13, rax\njnz short loc_1217\nmov eax, [r12]\nadd eax, [r12+r13-4]\nmov edx, eax\nshr edx, 1Fh\nlea r9d, [rax+rdx]\nand r9d, 1\nsub r9d, edx\ncmp ebp, 1\njle short loc_11E7\nlea r12d, [rbp-1]\nmov edi, 0\nmov r11d, 0\nmov r10d, 0\njmp short loc_12BB\nloc_125F:\nmov edi, 1; status\ncall _exit\nloc_1269:\nmov rdx, [rbx]\nlea rsi, [rdx+rdi]\nmov ecx, [rsi]\nmov edx, [rdx+rax]\ncmp ecx, edx\njle short loc_1281\nmov [rsi], edx\nmov rdx, [rbx]\nmov [rdx+rax], ecx\nloc_1281:\nadd rax, 4\ncmp rax, r8\njz short loc_12AA\nloc_128A:\ncmp r9d, 1\njz short loc_1269\nmov rdx, [rbx]\nlea rsi, [rdx+rdi]\nmov ecx, [rsi]\nmov edx, [rdx+rax]\ncmp ecx, edx\njge short loc_1281\nmov [rsi], edx\nmov rdx, [rbx]\nmov [rdx+rax], ecx\njmp short loc_1281\nloc_12AA:\nadd r11, 1\nadd rdi, 4\ncmp r10d, r12d\njz loc_11E7\nloc_12BB:\nadd r10d, 1\ncmp ebp, r10d\njle short loc_12AA\nlea rax, [rdi+4]\nmov edx, r12d\nsub edx, r10d\nlea r8, [r11+rdx+2]\nshl r8, 2\njmp short loc_128A", + "ida_pseudo": "void __fastcall func0(_DWORD *a1, int a2, _QWORD *a3, int *a4)\n{\n size_t v6; // r13\n void *v7; // rax\n unsigned __int64 v8; // rax\n int v9; // r9d\n int v10; // r12d\n __int64 v11; // rdi\n __int64 v12; // r11\n int v13; // r10d\n int *v14; // rsi\n int v15; // ecx\n int v16; // edx\n __int64 v17; // rax\n int *v18; // rsi\n int v19; // ecx\n int v20; // edx\n\n *a4 = a2;\n if ( a2 )\n {\n v6 = 4LL * a2;\n v7 = malloc(v6);\n *a3 = v7;\n if ( !v7 )\n exit(1);\n v8 = 0LL;\n if ( a2 > 0 )\n {\n do\n {\n *(_DWORD *)(*a3 + v8) = a1[v8 / 4];\n v8 += 4LL;\n }\n while ( v6 != v8 );\n v9 = (a1[v6 / 4 - 1] + *a1) % 2;\n if ( a2 > 1 )\n {\n v10 = a2 - 1;\n v11 = 0LL;\n v12 = 0LL;\n v13 = 0;\n do\n {\n if ( a2 > ++v13 )\n {\n v17 = v11 + 4;\n do\n {\n if ( v9 == 1 )\n {\n v14 = (int *)(*a3 + v11);\n v15 = *v14;\n v16 = *(_DWORD *)(*a3 + v17);\n if ( *v14 > v16 )\n {\n *v14 = v16;\n *(_DWORD *)(*a3 + v17) = v15;\n }\n }\n else\n {\n v18 = (int *)(*a3 + v11);\n v19 = *v18;\n v20 = *(_DWORD *)(*a3 + v17);\n if ( *v18 < v20 )\n {\n *v18 = v20;\n *(_DWORD *)(*a3 + v17) = v19;\n }\n }\n v17 += 4LL;\n }\n while ( v17 != 4 * (v12 + (unsigned int)(v10 - v13) + 2) );\n }\n ++v12;\n v11 += 4LL;\n }\n while ( v13 != v10 );\n }\n }\n }\n else\n {\n *a3 = 0LL;\n }\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdx\nmov [rcx], esi\ntest esi, esi\njnz short loc_11F2\nmov qword ptr [rdx], 0\nloc_11E7:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_11F2:\nmov r12, rdi\nmov ebp, esi\nmovsxd r13, esi\nshl r13, 2\nmov rdi, r13; size\ncall _malloc\nmov [rbx], rax\ntest rax, rax\njz short loc_125F\nmov eax, 0\ntest ebp, ebp\njle short loc_11E7\nloc_1217:\nmov ecx, [r12+rax]\nmov rdx, [rbx]\nmov [rdx+rax], ecx\nadd rax, 4\ncmp r13, rax\njnz short loc_1217\nmov eax, [r12]\nadd eax, [r12+r13-4]\nmov edx, eax\nshr edx, 1Fh\nlea r9d, [rax+rdx]\nand r9d, 1\nsub r9d, edx\ncmp ebp, 1\njle short loc_11E7\nlea r12d, [rbp-1]\nmov edi, 0\nmov r11d, 0\nmov r10d, 0\njmp short loc_12BB\nloc_125F:\nmov edi, 1; status\ncall _exit\nloc_1269:\nmov rdx, [rbx]\nlea rsi, [rdx+rdi]\nmov ecx, [rsi]\nmov edx, [rdx+rax]\ncmp ecx, edx\njle short loc_1281\nmov [rsi], edx\nmov rdx, [rbx]\nmov [rdx+rax], ecx\nloc_1281:\nadd rax, 4\ncmp rax, r8\njz short loc_12AA\nloc_128A:\ncmp r9d, 1\njz short loc_1269\nmov rdx, [rbx]\nlea rsi, [rdx+rdi]\nmov ecx, [rsi]\nmov edx, [rdx+rax]\ncmp ecx, edx\njge short loc_1281\nmov [rsi], edx\nmov rdx, [rbx]\nmov [rdx+rax], ecx\njmp short loc_1281\nloc_12AA:\nadd r11, 1\nadd rdi, 4\ncmp r10d, r12d\njz loc_11E7\nloc_12BB:\nadd r10d, 1\ncmp ebp, r10d\njle short loc_12AA\nlea rax, [rdi+4]\nmov edx, r12d\nsub edx, r10d\nlea r8, [r11+rdx+2]\nshl r8, 2\njmp short loc_128A", + "ida_strip_pseudo": "void __fastcall sub_11C9(_DWORD *a1, int a2, _QWORD *a3, int *a4)\n{\n size_t v6; // r13\n void *v7; // rax\n unsigned __int64 v8; // rax\n int v9; // r9d\n int v10; // r12d\n __int64 v11; // rdi\n __int64 v12; // r11\n int v13; // r10d\n int *v14; // rsi\n int v15; // ecx\n int v16; // edx\n __int64 v17; // rax\n int *v18; // rsi\n int v19; // ecx\n int v20; // edx\n\n *a4 = a2;\n if ( a2 )\n {\n v6 = 4LL * a2;\n v7 = malloc(v6);\n *a3 = v7;\n if ( !v7 )\n exit(1);\n v8 = 0LL;\n if ( a2 > 0 )\n {\n do\n {\n *(_DWORD *)(*a3 + v8) = a1[v8 / 4];\n v8 += 4LL;\n }\n while ( v6 != v8 );\n v9 = (a1[v6 / 4 - 1] + *a1) % 2;\n if ( a2 > 1 )\n {\n v10 = a2 - 1;\n v11 = 0LL;\n v12 = 0LL;\n v13 = 0;\n do\n {\n if ( a2 > ++v13 )\n {\n v17 = v11 + 4;\n do\n {\n if ( v9 == 1 )\n {\n v14 = (int *)(*a3 + v11);\n v15 = *v14;\n v16 = *(_DWORD *)(*a3 + v17);\n if ( *v14 > v16 )\n {\n *v14 = v16;\n *(_DWORD *)(*a3 + v17) = v15;\n }\n }\n else\n {\n v18 = (int *)(*a3 + v11);\n v19 = *v18;\n v20 = *(_DWORD *)(*a3 + v17);\n if ( *v18 < v20 )\n {\n *v18 = v20;\n *(_DWORD *)(*a3 + v17) = v19;\n }\n }\n v17 += 4LL;\n }\n while ( v17 != 4 * (v12 + (unsigned int)(v10 - v13) + 2) );\n }\n ++v12;\n v11 += 4LL;\n }\n while ( v13 != v10 );\n }\n }\n }\n else\n {\n *a3 = 0LL;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_11C9(uint32_t *a1, int a2, uint64_t *a3, int *a4) {\n unsigned int v6;\n void *v7;\n unsigned long long v8;\n int v9;\n int v10;\n long long v11;\n long long v12;\n int v13;\n int *v14;\n int v15;\n int v16;\n long long v17;\n int *v18;\n int v19;\n int v20;\n *a4 = a2;\n if (a2) {\n v6 = 4LL * a2;\n v7 = malloc(v6);\n *a3 = v7;\n if (!v7) exit(1);\n v8 = 0LL;\n if (a2 > 0) {\n do {\n *(uint32_t *)(*a3 + v8) = a1[v8 / 4];\n v8 += 4LL;\n } while (v6 != v8);\n v9 = (a1[v6 / 4 - 1] + *a1) % 2;\n if (a2 > 1) {\n v10 = a2 - 1;\n v11 = 0LL;\n v12 = 0LL;\n v13 = 0;\n do {\n if (a2 > ++v13) {\n v17 = v11 + 4;\n do {\n if (v9 == 1) {\n v14 = (int *)(*a3 + v11);\n v15 = *v14;\n v16 = *(uint32_t *)(*a3 + v17);\n if (*v14 > v16) {\n *v14 = v16;\n *(uint32_t *)(*a3 + v17) = v15;\n }\n } else {\n v18 = (int *)(*a3 + v11);\n v19 = *v18;\n v20 = *(uint32_t *)(*a3 + v17);\n if (*v18 < v20) {\n *v18 = v20;\n *(uint32_t *)(*a3 + v17) = v19;\n }\n }\n v17 += 4LL;\n } while (v17 != 4 * (v12 + (unsigned int)(v10 - v13) + 2));\n }\n ++v12;\n v11 += 4LL;\n } while (v13 != v10);\n }\n }\n } else {\n *a3 = 0LL;\n }\n}", + "ida_pseudo_norm": "void func0(uint32_t *a1, int a2, uint64_t *a3, int *a4) {\n unsigned int v6;\n void *v7;\n unsigned long long v8;\n int v9;\n int v10;\n long long v11;\n long long v12;\n int v13;\n int *v14;\n int v15;\n int v16;\n long long v17;\n int *v18;\n int v19;\n int v20;\n *a4 = a2;\n if (a2) {\n v6 = 4LL * a2;\n v7 = malloc(v6);\n *a3 = v7;\n if (!v7) exit(1);\n v8 = 0LL;\n if (a2 > 0) {\n do {\n *(uint32_t *)(*a3 + v8) = a1[v8 / 4];\n v8 += 4LL;\n } while (v6 != v8);\n v9 = (a1[v6 / 4 - 1] + *a1) % 2;\n if (a2 > 1) {\n v10 = a2 - 1;\n v11 = 0LL;\n v12 = 0LL;\n v13 = 0;\n do {\n if (a2 > ++v13) {\n v17 = v11 + 4;\n do {\n if (v9 == 1) {\n v14 = (int *)(*a3 + v11);\n v15 = *v14;\n v16 = *(uint32_t *)(*a3 + v17);\n if (*v14 > v16) {\n *v14 = v16;\n *(uint32_t *)(*a3 + v17) = v15;\n }\n } else {\n v18 = (int *)(*a3 + v11);\n v19 = *v18;\n v20 = *(uint32_t *)(*a3 + v17);\n if (*v18 < v20) {\n *v18 = v20;\n *(uint32_t *)(*a3 + v17) = v19;\n }\n }\n v17 += 4LL;\n } while (v17 != 4 * (v12 + (unsigned int)(v10 - v13) + 2));\n }\n ++v12;\n v11 += 4LL;\n } while (v13 != v10);\n }\n }\n } else {\n *a3 = 0LL;\n }\n}" + }, + { + "index": "HumanEval-C-88", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(int *array, int size, int **out_array, int *out_size) {\n *out_size = size;\n if (size == 0) {\n *out_array = NULL;\n return;\n }\n *out_array = (int *)malloc(sizeof(int) * size);\n if (*out_array == NULL) {\n exit(1);\n }\n for (int i = 0; i < size; i++) {\n (*out_array)[i] = array[i];\n }\n int shouldSortAscending = (array[0] + array[size - 1]) % 2 == 1;\n for (int i = 0; i < size - 1; i++) {\n for (int j = i + 1; j < size; j++) {\n if (shouldSortAscending) {\n if ((*out_array)[i] > (*out_array)[j]) {\n int temp = (*out_array)[i];\n (*out_array)[i] = (*out_array)[j];\n (*out_array)[j] = temp;\n }\n } else {\n if ((*out_array)[i] < (*out_array)[j]) {\n int temp = (*out_array)[i];\n (*out_array)[i] = (*out_array)[j];\n (*out_array)[j] = temp;\n }\n }\n }\n }\n}", + "test": "#include \n#include \n#include \n\nint issame(int *a, int aSize, int *b, int bSize) {\n if (aSize != bSize) return 0;\n for (int i = 0; i < aSize; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int *result, result_size;\n\n func0((const int[]){}, 0, &result, &result_size);\n assert(issame(result, result_size, (const int[]){}, 0));\n free(result);\n\n func0((const int[]){5}, 1, &result, &result_size);\n assert(issame(result, result_size, (const int[]){5}, 1));\n free(result);\n\n func0((const int[]){2, 4, 3, 0, 1, 5}, 6, &result, &result_size);\n assert(issame(result, result_size, (const int[]){0, 1, 2, 3, 4, 5}, 6));\n free(result);\n\n func0((const int[]){2, 4, 3, 0, 1, 5, 6}, 7, &result, &result_size);\n assert(issame(result, result_size, (const int[]){6, 5, 4, 3, 2, 1, 0}, 7));\n free(result);\n\n func0((const int[]){2, 1}, 2, &result, &result_size);\n assert(issame(result, result_size, (const int[]){1, 2}, 2));\n free(result);\n\n func0((const int[]){15, 42, 87, 32, 11, 0}, 6, &result, &result_size);\n assert(issame(result, result_size, (const int[]){0, 11, 15, 32, 42, 87}, 6));\n free(result);\n\n func0((const int[]){21, 14, 23, 11}, 4, &result, &result_size);\n assert(issame(result, result_size, (const int[]){23, 21, 14, 11}, 4));\n free(result);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0_part_0:\npush r14\nmov r14, rdi\npush r13\nmovsxd r13, esi\npush r12\npush rbp\nmov rbp, rdx\npush rbx\nmov rbx, r13\nshl r13, 2\nmov rdi, r13; size\ncall _malloc\nmov [rbp+0], rax\ntest rax, rax\njz loc_165D\ntest ebx, ebx\njle loc_1627\nmov ebp, ebx\nmov rsi, r14; src\nlea r12d, [rbx-1]\nmov rdi, rax; dest\nlea rdx, ds:0[rbp*4]; n\ncall _memcpy\nmov r11, rax\nmov eax, [r14]\nadd eax, [r14+r13-4]\nmov edx, eax\nshr edx, 1Fh\nlea r10d, [rax+rdx]\nand r10d, 1\nsub r10d, edx\ncmp ebx, 1\njz short loc_1627\nlea rsi, [r11+4]\nmov r9d, 1\nadd r11, 8\nnop dword ptr [rax+00h]\nloc_15D0:\ncmp ebx, r9d\njle short loc_161A\nmov eax, r12d\nmov edx, [rsi-4]\nmov ecx, [rsi]\nmov rdi, rsi\nsub eax, r9d\nlea rax, [r9+rax-1]\nlea r8, [r11+rax*4]\nmov rax, rsi\ncmp r10d, 1\njnz short loc_1608\njmp short loc_1638\nloc_1600:\nmov edx, [rsi-4]\nmov ecx, [rax]\nmov rdi, rax\nloc_1608:\ncmp edx, ecx\njge short loc_1611\nmov [rsi-4], ecx\nmov [rdi], edx\nloc_1611:\nadd rax, 4\ncmp r8, rax\njnz short loc_1600\nloc_161A:\nadd r9, 1\nadd rsi, 4\ncmp r9, rbp\njnz short loc_15D0\nloc_1627:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1630:\nmov edx, [rsi-4]\nmov ecx, [rax]\nmov rdi, rax\nloc_1638:\ncmp edx, ecx\njle short loc_1641\nmov [rsi-4], ecx\nmov [rdi], edx\nloc_1641:\nadd rax, 4\ncmp r8, rax\njnz short loc_1630\nadd r9, 1\nadd rsi, 4\ncmp r9, rbp\njnz loc_15D0\njmp short loc_1627\nloc_165D:\nmov edi, 1; status\ncall _exit", + "ida_pseudo": "int *__fastcall func0_part_0(char *src, int a2, int **a3)\n{\n size_t v5; // r13\n int *result; // rax\n int v7; // r12d\n char *v8; // r11\n int v9; // r10d\n int *v10; // rsi\n __int64 v11; // r9\n char *v12; // r11\n int v13; // edx\n int v14; // ecx\n int *v15; // rdi\n char *v16; // r8\n\n v5 = 4LL * a2;\n result = (int *)malloc(v5);\n *a3 = result;\n if ( !result )\n exit(1);\n if ( a2 > 0 )\n {\n v7 = a2 - 1;\n v8 = (char *)memcpy(result, src, 4LL * (unsigned int)a2);\n result = (int *)(unsigned int)(*(_DWORD *)&src[v5 - 4] + *(_DWORD *)src);\n v9 = (*(_DWORD *)&src[v5 - 4] + *(_DWORD *)src) % 2;\n if ( a2 != 1 )\n {\n v10 = (int *)(v8 + 4);\n v11 = 1LL;\n v12 = v8 + 8;\n do\n {\n while ( a2 <= (int)v11 )\n {\nLABEL_12:\n ++v11;\n ++v10;\n if ( v11 == a2 )\n return result;\n }\n v13 = *(v10 - 1);\n v14 = *v10;\n v15 = v10;\n v16 = &v12[4 * v11 - 4 + 4 * (unsigned int)(v7 - v11)];\n result = v10;\n if ( v9 != 1 )\n {\n while ( 1 )\n {\n if ( v13 < v14 )\n {\n *(v10 - 1) = v14;\n *v15 = v13;\n }\n if ( v16 == (char *)++result )\n break;\n v13 = *(v10 - 1);\n v14 = *result;\n v15 = result;\n }\n goto LABEL_12;\n }\n while ( 1 )\n {\n if ( v13 > v14 )\n {\n *(v10 - 1) = v14;\n *v15 = v13;\n }\n if ( v16 == (char *)++result )\n break;\n v13 = *(v10 - 1);\n v14 = *result;\n v15 = result;\n }\n ++v11;\n ++v10;\n }\n while ( v11 != a2 );\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1550:\npush r14\nmov r14, rdi\npush r13\nmovsxd r13, esi\npush r12\npush rbp\nmov rbp, rdx\npush rbx\nmov rbx, r13\nshl r13, 2\nmov rdi, r13; size\ncall _malloc\nmov [rbp+0], rax\ntest rax, rax\njz loc_165D\ntest ebx, ebx\njle loc_1627\nmov ebp, ebx\nmov rsi, r14; src\nlea r12d, [rbx-1]\nmov rdi, rax; dest\nlea rdx, ds:0[rbp*4]; n\ncall _memcpy\nmov r11, rax\nmov eax, [r14]\nadd eax, [r14+r13-4]\nmov edx, eax\nshr edx, 1Fh\nlea r10d, [rax+rdx]\nand r10d, 1\nsub r10d, edx\ncmp ebx, 1\njz short loc_1627\nlea rsi, [r11+4]\nmov r9d, 1\nadd r11, 8\nnop dword ptr [rax+00h]\nloc_15D0:\ncmp ebx, r9d\njle short loc_161A\nmov eax, r12d\nmov edx, [rsi-4]\nmov ecx, [rsi]\nmov rdi, rsi\nsub eax, r9d\nlea rax, [r9+rax-1]\nlea r8, [r11+rax*4]\nmov rax, rsi\ncmp r10d, 1\njnz short loc_1608\njmp short loc_1638\nloc_1600:\nmov edx, [rsi-4]\nmov ecx, [rax]\nmov rdi, rax\nloc_1608:\ncmp edx, ecx\njge short loc_1611\nmov [rsi-4], ecx\nmov [rdi], edx\nloc_1611:\nadd rax, 4\ncmp r8, rax\njnz short loc_1600\nloc_161A:\nadd r9, 1\nadd rsi, 4\ncmp r9, rbp\njnz short loc_15D0\nloc_1627:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1630:\nmov edx, [rsi-4]\nmov ecx, [rax]\nmov rdi, rax\nloc_1638:\ncmp edx, ecx\njle short loc_1641\nmov [rsi-4], ecx\nmov [rdi], edx\nloc_1641:\nadd rax, 4\ncmp r8, rax\njnz short loc_1630\nadd r9, 1\nadd rsi, 4\ncmp r9, rbp\njnz loc_15D0\njmp short loc_1627\nloc_165D:\nmov edi, 1; status\ncall _exit", + "ida_strip_pseudo": "int *__fastcall sub_1550(char *src, int a2, int **a3)\n{\n size_t v5; // r13\n int *result; // rax\n int v7; // r12d\n char *v8; // r11\n int v9; // r10d\n int *v10; // rsi\n __int64 v11; // r9\n char *v12; // r11\n int v13; // edx\n int v14; // ecx\n int *v15; // rdi\n char *v16; // r8\n\n v5 = 4LL * a2;\n result = (int *)malloc(v5);\n *a3 = result;\n if ( !result )\n exit(1);\n if ( a2 > 0 )\n {\n v7 = a2 - 1;\n v8 = (char *)memcpy(result, src, 4LL * (unsigned int)a2);\n result = (int *)(unsigned int)(*(_DWORD *)&src[v5 - 4] + *(_DWORD *)src);\n v9 = (*(_DWORD *)&src[v5 - 4] + *(_DWORD *)src) % 2;\n if ( a2 != 1 )\n {\n v10 = (int *)(v8 + 4);\n v11 = 1LL;\n v12 = v8 + 8;\n do\n {\n while ( a2 <= (int)v11 )\n {\nLABEL_12:\n ++v11;\n ++v10;\n if ( v11 == a2 )\n return result;\n }\n v13 = *(v10 - 1);\n v14 = *v10;\n v15 = v10;\n v16 = &v12[4 * v11 - 4 + 4 * (unsigned int)(v7 - v11)];\n result = v10;\n if ( v9 != 1 )\n {\n while ( 1 )\n {\n if ( v13 < v14 )\n {\n *(v10 - 1) = v14;\n *v15 = v13;\n }\n if ( v16 == (char *)++result )\n break;\n v13 = *(v10 - 1);\n v14 = *result;\n v15 = result;\n }\n goto LABEL_12;\n }\n while ( 1 )\n {\n if ( v13 > v14 )\n {\n *(v10 - 1) = v14;\n *v15 = v13;\n }\n if ( v16 == (char *)++result )\n break;\n v13 = *(v10 - 1);\n v14 = *result;\n v15 = result;\n }\n ++v11;\n ++v10;\n }\n while ( v11 != a2 );\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "int *sub_1550(char *src, int a2, int **a3) {\n unsigned int v5;\n int *result;\n int v7;\n char *v8;\n int v9;\n int *v10;\n long long v11;\n char *v12;\n int v13;\n int v14;\n int *v15;\n char *v16;\n v5 = 4LL * a2;\n result = (int *)malloc(v5);\n *a3 = result;\n if (!result) exit(1);\n if (a2 > 0) {\n v7 = a2 - 1;\n v8 = (char *)memcpy(result, src, 4LL * (unsigned int)a2);\n result =\n (int *)(unsigned int)(*(uint32_t *)&src[v5 - 4] + *(uint32_t *)src);\n v9 = (*(uint32_t *)&src[v5 - 4] + *(uint32_t *)src) % 2;\n if (a2 != 1) {\n v10 = (int *)(v8 + 4);\n v11 = 1LL;\n v12 = v8 + 8;\n do {\n while (a2 <= (int)v11) {\n LABEL_12:\n ++v11;\n ++v10;\n if (v11 == a2) return result;\n }\n v13 = *(v10 - 1);\n v14 = *v10;\n v15 = v10;\n v16 = &v12[4 * v11 - 4 + 4 * (unsigned int)(v7 - v11)];\n result = v10;\n if (v9 != 1) {\n while (1) {\n if (v13 < v14) {\n *(v10 - 1) = v14;\n *v15 = v13;\n }\n if (v16 == (char *)++result) break;\n v13 = *(v10 - 1);\n v14 = *result;\n v15 = result;\n }\n goto LABEL_12;\n }\n while (1) {\n if (v13 > v14) {\n *(v10 - 1) = v14;\n *v15 = v13;\n }\n if (v16 == (char *)++result) break;\n v13 = *(v10 - 1);\n v14 = *result;\n v15 = result;\n }\n ++v11;\n ++v10;\n } while (v11 != a2);\n }\n }\n return result;\n}", + "ida_pseudo_norm": "int *func0_part_0(char *src, int a2, int **a3) {\n unsigned int v5;\n int *result;\n int v7;\n char *v8;\n int v9;\n int *v10;\n long long v11;\n char *v12;\n int v13;\n int v14;\n int *v15;\n char *v16;\n v5 = 4LL * a2;\n result = (int *)malloc(v5);\n *a3 = result;\n if (!result) exit(1);\n if (a2 > 0) {\n v7 = a2 - 1;\n v8 = (char *)memcpy(result, src, 4LL * (unsigned int)a2);\n result =\n (int *)(unsigned int)(*(uint32_t *)&src[v5 - 4] + *(uint32_t *)src);\n v9 = (*(uint32_t *)&src[v5 - 4] + *(uint32_t *)src) % 2;\n if (a2 != 1) {\n v10 = (int *)(v8 + 4);\n v11 = 1LL;\n v12 = v8 + 8;\n do {\n while (a2 <= (int)v11) {\n LABEL_12:\n ++v11;\n ++v10;\n if (v11 == a2) return result;\n }\n v13 = *(v10 - 1);\n v14 = *v10;\n v15 = v10;\n v16 = &v12[4 * v11 - 4 + 4 * (unsigned int)(v7 - v11)];\n result = v10;\n if (v9 != 1) {\n while (1) {\n if (v13 < v14) {\n *(v10 - 1) = v14;\n *v15 = v13;\n }\n if (v16 == (char *)++result) break;\n v13 = *(v10 - 1);\n v14 = *result;\n v15 = result;\n }\n goto LABEL_12;\n }\n while (1) {\n if (v13 > v14) {\n *(v10 - 1) = v14;\n *v15 = v13;\n }\n if (v16 == (char *)++result) break;\n v13 = *(v10 - 1);\n v14 = *result;\n v15 = result;\n }\n ++v11;\n ++v10;\n } while (v11 != a2);\n }\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-88", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(int *array, int size, int **out_array, int *out_size) {\n *out_size = size;\n if (size == 0) {\n *out_array = NULL;\n return;\n }\n *out_array = (int *)malloc(sizeof(int) * size);\n if (*out_array == NULL) {\n exit(1);\n }\n for (int i = 0; i < size; i++) {\n (*out_array)[i] = array[i];\n }\n int shouldSortAscending = (array[0] + array[size - 1]) % 2 == 1;\n for (int i = 0; i < size - 1; i++) {\n for (int j = i + 1; j < size; j++) {\n if (shouldSortAscending) {\n if ((*out_array)[i] > (*out_array)[j]) {\n int temp = (*out_array)[i];\n (*out_array)[i] = (*out_array)[j];\n (*out_array)[j] = temp;\n }\n } else {\n if ((*out_array)[i] < (*out_array)[j]) {\n int temp = (*out_array)[i];\n (*out_array)[i] = (*out_array)[j];\n (*out_array)[j] = temp;\n }\n }\n }\n }\n}", + "test": "#include \n#include \n#include \n\nint issame(int *a, int aSize, int *b, int bSize) {\n if (aSize != bSize) return 0;\n for (int i = 0; i < aSize; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int *result, result_size;\n\n func0((const int[]){}, 0, &result, &result_size);\n assert(issame(result, result_size, (const int[]){}, 0));\n free(result);\n\n func0((const int[]){5}, 1, &result, &result_size);\n assert(issame(result, result_size, (const int[]){5}, 1));\n free(result);\n\n func0((const int[]){2, 4, 3, 0, 1, 5}, 6, &result, &result_size);\n assert(issame(result, result_size, (const int[]){0, 1, 2, 3, 4, 5}, 6));\n free(result);\n\n func0((const int[]){2, 4, 3, 0, 1, 5, 6}, 7, &result, &result_size);\n assert(issame(result, result_size, (const int[]){6, 5, 4, 3, 2, 1, 0}, 7));\n free(result);\n\n func0((const int[]){2, 1}, 2, &result, &result_size);\n assert(issame(result, result_size, (const int[]){1, 2}, 2));\n free(result);\n\n func0((const int[]){15, 42, 87, 32, 11, 0}, 6, &result, &result_size);\n assert(issame(result, result_size, (const int[]){0, 11, 15, 32, 42, 87}, 6));\n free(result);\n\n func0((const int[]){21, 14, 23, 11}, 4, &result, &result_size);\n assert(issame(result, result_size, (const int[]){23, 21, 14, 11}, 4));\n free(result);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0_part_0:\npush r14\nmov r14, rdi\npush r13\nmovsxd r13, esi\npush r12\npush rbp\nmov rbp, rdx\npush rbx\nmov rbx, r13\nshl r13, 2\nmov rdi, r13; size\ncall _malloc\nmov [rbp+0], rax\ntest rax, rax\njz loc_1676\ntest ebx, ebx\njle loc_1614\nmov ebp, ebx\nmov rsi, r14; src\nlea r12d, [rbx-1]\nmov rdi, rax; dest\nlea rdx, ds:0[rbp*4]; n\ncall _memcpy\nmov rcx, rax\nmov eax, [r14]\nadd eax, [r14+r13-4]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nand eax, 1\nsub eax, edx\ncmp ebx, 1\njz short loc_1614\nlea rsi, [rcx+4]\nmov r8d, 1\nlea r9, [rcx+8]\ncmp eax, 1\njz short loc_1630\nnop dword ptr [rax]\nloc_15D0:\ncmp ebx, r8d\njle short loc_1607\nmov eax, r12d\nsub eax, r8d\nlea rax, [r8+rax-1]\nlea rdi, [r9+rax*4]\nmov rax, rsi\nnop word ptr [rax+rax+00000000h]\nloc_15F0:\nmov edx, [rsi-4]\nmov ecx, [rax]\ncmp ecx, edx\njle short loc_15FE\nmov [rsi-4], ecx\nmov [rax], edx\nloc_15FE:\nadd rax, 4\ncmp rax, rdi\njnz short loc_15F0\nloc_1607:\nadd r8, 1\nadd rsi, 4\ncmp r8, rbp\njnz short loc_15D0\nloc_1614:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_161D:\nadd r8, 1\nadd rsi, 4\ncmp r8, rbp\njz short loc_1614\nnop word ptr [rax+rax+00h]\nloc_1630:\ncmp ebx, r8d\njle short loc_161D\nmov eax, r12d\nsub eax, r8d\nlea rax, [r8+rax-1]\nlea rdi, [r9+rax*4]\nmov rax, rsi\nnop word ptr [rax+rax+00000000h]\nloc_1650:\nmov edx, [rsi-4]\nmov ecx, [rax]\ncmp edx, ecx\njle short loc_165E\nmov [rsi-4], ecx\nmov [rax], edx\nloc_165E:\nadd rax, 4\ncmp rax, rdi\njnz short loc_1650\nadd r8, 1\nadd rsi, 4\ncmp r8, rbp\njnz short loc_1630\njmp short loc_1614\nloc_1676:\nmov edi, 1; status\ncall _exit", + "ida_pseudo": "__int64 __fastcall func0_part_0(_DWORD *src, int a2, _QWORD *a3)\n{\n __int64 result; // rax\n int v6; // r12d\n char *v7; // rcx\n __int64 v8; // rsi\n __int64 v9; // r8\n char *v10; // r9\n int v11; // edx\n int v12; // edx\n\n result = (__int64)malloc(4LL * a2);\n *a3 = result;\n if ( !result )\n exit(1);\n if ( a2 > 0 )\n {\n v6 = a2 - 1;\n v7 = (char *)memcpy((void *)result, src, 4LL * (unsigned int)a2);\n result = (unsigned int)((src[a2 - 1] + *src) % 2);\n if ( a2 != 1 )\n {\n v8 = (__int64)(v7 + 4);\n v9 = 1LL;\n v10 = v7 + 8;\n if ( (_DWORD)result == 1 )\n {\n do\n {\n while ( a2 <= (int)v9 )\n {\n ++v9;\n v8 += 4LL;\n if ( v9 == a2 )\n return result;\n }\n result = v8;\n do\n {\n v12 = *(_DWORD *)(v8 - 4);\n if ( v12 > *(_DWORD *)result )\n {\n *(_DWORD *)(v8 - 4) = *(_DWORD *)result;\n *(_DWORD *)result = v12;\n }\n result += 4LL;\n }\n while ( (char *)result != &v10[4 * v9 - 4 + 4 * (unsigned int)(v6 - v9)] );\n ++v9;\n v8 += 4LL;\n }\n while ( v9 != a2 );\n }\n else\n {\n do\n {\n if ( a2 > (int)v9 )\n {\n result = v8;\n do\n {\n v11 = *(_DWORD *)(v8 - 4);\n if ( *(_DWORD *)result > v11 )\n {\n *(_DWORD *)(v8 - 4) = *(_DWORD *)result;\n *(_DWORD *)result = v11;\n }\n result += 4LL;\n }\n while ( (char *)result != &v10[4 * v9 - 4 + 4 * (unsigned int)(v6 - v9)] );\n }\n ++v9;\n v8 += 4LL;\n }\n while ( v9 != a2 );\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1550:\npush r14\nmov r14, rdi\npush r13\nmovsxd r13, esi\npush r12\npush rbp\nmov rbp, rdx\npush rbx\nmov rbx, r13\nshl r13, 2\nmov rdi, r13; size\ncall _malloc\nmov [rbp+0], rax\ntest rax, rax\njz loc_1676\ntest ebx, ebx\njle loc_1614\nmov ebp, ebx\nmov rsi, r14; src\nlea r12d, [rbx-1]\nmov rdi, rax; dest\nlea rdx, ds:0[rbp*4]; n\ncall _memcpy\nmov rcx, rax\nmov eax, [r14]\nadd eax, [r14+r13-4]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nand eax, 1\nsub eax, edx\ncmp ebx, 1\njz short loc_1614\nlea rsi, [rcx+4]\nmov r8d, 1\nlea r9, [rcx+8]\ncmp eax, 1\njz short loc_1630\nnop dword ptr [rax]\nloc_15D0:\ncmp ebx, r8d\njle short loc_1607\nmov eax, r12d\nsub eax, r8d\nlea rax, [r8+rax-1]\nlea rdi, [r9+rax*4]\nmov rax, rsi\nnop word ptr [rax+rax+00000000h]\nloc_15F0:\nmov edx, [rsi-4]\nmov ecx, [rax]\ncmp ecx, edx\njle short loc_15FE\nmov [rsi-4], ecx\nmov [rax], edx\nloc_15FE:\nadd rax, 4\ncmp rax, rdi\njnz short loc_15F0\nloc_1607:\nadd r8, 1\nadd rsi, 4\ncmp r8, rbp\njnz short loc_15D0\nloc_1614:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_161D:\nadd r8, 1\nadd rsi, 4\ncmp r8, rbp\njz short loc_1614\nnop word ptr [rax+rax+00h]\nloc_1630:\ncmp ebx, r8d\njle short loc_161D\nmov eax, r12d\nsub eax, r8d\nlea rax, [r8+rax-1]\nlea rdi, [r9+rax*4]\nmov rax, rsi\nnop word ptr [rax+rax+00000000h]\nloc_1650:\nmov edx, [rsi-4]\nmov ecx, [rax]\ncmp edx, ecx\njle short loc_165E\nmov [rsi-4], ecx\nmov [rax], edx\nloc_165E:\nadd rax, 4\ncmp rax, rdi\njnz short loc_1650\nadd r8, 1\nadd rsi, 4\ncmp r8, rbp\njnz short loc_1630\njmp short loc_1614\nloc_1676:\nmov edi, 1; status\ncall _exit", + "ida_strip_pseudo": "__int64 __fastcall sub_1550(_DWORD *src, int a2, _QWORD *a3)\n{\n __int64 result; // rax\n int v6; // r12d\n char *v7; // rcx\n __int64 v8; // rsi\n __int64 v9; // r8\n char *v10; // r9\n int v11; // edx\n int v12; // edx\n\n result = (__int64)malloc(4LL * a2);\n *a3 = result;\n if ( !result )\n exit(1);\n if ( a2 > 0 )\n {\n v6 = a2 - 1;\n v7 = (char *)memcpy((void *)result, src, 4LL * (unsigned int)a2);\n result = (unsigned int)((src[a2 - 1] + *src) % 2);\n if ( a2 != 1 )\n {\n v8 = (__int64)(v7 + 4);\n v9 = 1LL;\n v10 = v7 + 8;\n if ( (_DWORD)result == 1 )\n {\n do\n {\n while ( a2 <= (int)v9 )\n {\n ++v9;\n v8 += 4LL;\n if ( v9 == a2 )\n return result;\n }\n result = v8;\n do\n {\n v12 = *(_DWORD *)(v8 - 4);\n if ( v12 > *(_DWORD *)result )\n {\n *(_DWORD *)(v8 - 4) = *(_DWORD *)result;\n *(_DWORD *)result = v12;\n }\n result += 4LL;\n }\n while ( (char *)result != &v10[4 * v9 - 4 + 4 * (unsigned int)(v6 - v9)] );\n ++v9;\n v8 += 4LL;\n }\n while ( v9 != a2 );\n }\n else\n {\n do\n {\n if ( a2 > (int)v9 )\n {\n result = v8;\n do\n {\n v11 = *(_DWORD *)(v8 - 4);\n if ( *(_DWORD *)result > v11 )\n {\n *(_DWORD *)(v8 - 4) = *(_DWORD *)result;\n *(_DWORD *)result = v11;\n }\n result += 4LL;\n }\n while ( (char *)result != &v10[4 * v9 - 4 + 4 * (unsigned int)(v6 - v9)] );\n }\n ++v9;\n v8 += 4LL;\n }\n while ( v9 != a2 );\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1550(uint32_t *src, int a2, uint64_t *a3) {\n long long result;\n int v6;\n char *v7;\n long long v8;\n long long v9;\n char *v10;\n int v11;\n int v12;\n result = (long long)malloc(4LL * a2);\n *a3 = result;\n if (!result) exit(1);\n if (a2 > 0) {\n v6 = a2 - 1;\n v7 = (char *)memcpy((void *)result, src, 4LL * (unsigned int)a2);\n result = (unsigned int)((src[a2 - 1] + *src) % 2);\n if (a2 != 1) {\n v8 = (long long)(v7 + 4);\n v9 = 1LL;\n v10 = v7 + 8;\n if ((uint32_t)result == 1) {\n do {\n while (a2 <= (int)v9) {\n ++v9;\n v8 += 4LL;\n if (v9 == a2) return result;\n }\n result = v8;\n do {\n v12 = *(uint32_t *)(v8 - 4);\n if (v12 > *(uint32_t *)result) {\n *(uint32_t *)(v8 - 4) = *(uint32_t *)result;\n *(uint32_t *)result = v12;\n }\n result += 4LL;\n } while ((char *)result !=\n &v10[4 * v9 - 4 + 4 * (unsigned int)(v6 - v9)]);\n ++v9;\n v8 += 4LL;\n } while (v9 != a2);\n } else {\n do {\n if (a2 > (int)v9) {\n result = v8;\n do {\n v11 = *(uint32_t *)(v8 - 4);\n if (*(uint32_t *)result > v11) {\n *(uint32_t *)(v8 - 4) = *(uint32_t *)result;\n *(uint32_t *)result = v11;\n }\n result += 4LL;\n } while ((char *)result !=\n &v10[4 * v9 - 4 + 4 * (unsigned int)(v6 - v9)]);\n }\n ++v9;\n v8 += 4LL;\n } while (v9 != a2);\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0_part_0(uint32_t *src, int a2, uint64_t *a3) {\n long long result;\n int v6;\n char *v7;\n long long v8;\n long long v9;\n char *v10;\n int v11;\n int v12;\n result = (long long)malloc(4LL * a2);\n *a3 = result;\n if (!result) exit(1);\n if (a2 > 0) {\n v6 = a2 - 1;\n v7 = (char *)memcpy((void *)result, src, 4LL * (unsigned int)a2);\n result = (unsigned int)((src[a2 - 1] + *src) % 2);\n if (a2 != 1) {\n v8 = (long long)(v7 + 4);\n v9 = 1LL;\n v10 = v7 + 8;\n if ((uint32_t)result == 1) {\n do {\n while (a2 <= (int)v9) {\n ++v9;\n v8 += 4LL;\n if (v9 == a2) return result;\n }\n result = v8;\n do {\n v12 = *(uint32_t *)(v8 - 4);\n if (v12 > *(uint32_t *)result) {\n *(uint32_t *)(v8 - 4) = *(uint32_t *)result;\n *(uint32_t *)result = v12;\n }\n result += 4LL;\n } while ((char *)result !=\n &v10[4 * v9 - 4 + 4 * (unsigned int)(v6 - v9)]);\n ++v9;\n v8 += 4LL;\n } while (v9 != a2);\n } else {\n do {\n if (a2 > (int)v9) {\n result = v8;\n do {\n v11 = *(uint32_t *)(v8 - 4);\n if (*(uint32_t *)result > v11) {\n *(uint32_t *)(v8 - 4) = *(uint32_t *)result;\n *(uint32_t *)result = v11;\n }\n result += 4LL;\n } while ((char *)result !=\n &v10[4 * v9 - 4 + 4 * (unsigned int)(v6 - v9)]);\n }\n ++v9;\n v8 += 4LL;\n } while (v9 != a2);\n }\n }\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-89", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(const char *s, char *out) {\n int i;\n for (i = 0; s[i] != '\\0'; i++) {\n int w = ((int)s[i] - 'a' + 4) % 26 + 'a';\n out[i] = (char)w;\n }\n out[i] = '\\0';\n}", + "test": "#include \n#include \n#include \n\nint main() {\n char encrypted[100]; // Buffer should be large enough to hold the encrypted string\n\n func0(\"hi\", encrypted);\n assert(strcmp(encrypted, \"lm\") == 0);\n\n func0(\"asdfghjkl\", encrypted);\n assert(strcmp(encrypted, \"ewhjklnop\") == 0);\n\n func0(\"gf\", encrypted);\n assert(strcmp(encrypted, \"kj\") == 0);\n\n func0(\"et\", encrypted);\n assert(strcmp(encrypted, \"ix\") == 0);\n\n func0(\"faewfawefaewg\", encrypted);\n assert(strcmp(encrypted, \"jeiajeaijeiak\") == 0);\n\n func0(\"hellomyfriend\", encrypted);\n assert(strcmp(encrypted, \"lippsqcjvmirh\") == 0);\n\n func0(\"dxzdlmnilfuhmilufhlihufnmlimnufhlimnufhfucufh\", encrypted);\n assert(strcmp(encrypted, \"hbdhpqrmpjylqmpyjlpmlyjrqpmqryjlpmqryjljygyjl\") == 0);\n\n func0(\"a\", encrypted);\n assert(strcmp(encrypted, \"e\") == 0);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_8], 0\njmp short loc_11F3\nloc_11A2:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nlea edx, [rax-5Dh]\nmovsxd rax, edx\nimul rax, 4EC4EC4Fh\nshr rax, 20h\nsar eax, 3\nmov ecx, edx\nsar ecx, 1Fh\nsub eax, ecx\nimul ecx, eax, 1Ah\nmov eax, edx\nsub eax, ecx\nadd eax, 61h ; 'a'\nmov [rbp+var_4], eax\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov edx, [rbp+var_4]\nmov [rax], dl\nadd [rbp+var_8], 1\nloc_11F3:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_11A2\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov byte ptr [rax], 0\nnop\npop rbp\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(__int64 a1, __int64 a2)\n{\n _BYTE *result; // rax\n int i; // [rsp+18h] [rbp-8h]\n\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n *(_BYTE *)(i + a2) = (*(char *)(i + a1) - 93) % 26 + 97;\n result = (_BYTE *)(i + a2);\n *result = 0;\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_8], 0\njmp short loc_11F3\nloc_11A2:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nlea edx, [rax-5Dh]\nmovsxd rax, edx\nimul rax, 4EC4EC4Fh\nshr rax, 20h\nsar eax, 3\nmov ecx, edx\nsar ecx, 1Fh\nsub eax, ecx\nimul ecx, eax, 1Ah\nmov eax, edx\nsub eax, ecx\nadd eax, 61h ; 'a'\nmov [rbp+var_4], eax\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov edx, [rbp+var_4]\nmov [rax], dl\nadd [rbp+var_8], 1\nloc_11F3:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_11A2\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov byte ptr [rax], 0\nnop\npop rbp\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1189(__int64 a1, __int64 a2)\n{\n _BYTE *result; // rax\n int i; // [rsp+18h] [rbp-8h]\n\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n *(_BYTE *)(i + a2) = (*(char *)(i + a1) - 93) % 26 + 97;\n result = (_BYTE *)(i + a2);\n *result = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1189(long long a1, long long a2) {\n uint8_t *result;\n int i;\n for (i = 0; *(uint8_t *)(i + a1); ++i)\n *(uint8_t *)(i + a2) = (*(char *)(i + a1) - 93) % 26 + 97;\n result = (uint8_t *)(i + a2);\n *result = 0;\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(long long a1, long long a2) {\n uint8_t *result;\n int i;\n for (i = 0; *(uint8_t *)(i + a1); ++i)\n *(uint8_t *)(i + a2) = (*(char *)(i + a1) - 93) % 26 + 97;\n result = (uint8_t *)(i + a2);\n *result = 0;\n return result;\n}" + }, + { + "index": "HumanEval-C-89", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(const char *s, char *out) {\n int i;\n for (i = 0; s[i] != '\\0'; i++) {\n int w = ((int)s[i] - 'a' + 4) % 26 + 'a';\n out[i] = (char)w;\n }\n out[i] = '\\0';\n}", + "test": "#include \n#include \n#include \n\nint main() {\n char encrypted[100]; // Buffer should be large enough to hold the encrypted string\n\n func0(\"hi\", encrypted);\n assert(strcmp(encrypted, \"lm\") == 0);\n\n func0(\"asdfghjkl\", encrypted);\n assert(strcmp(encrypted, \"ewhjklnop\") == 0);\n\n func0(\"gf\", encrypted);\n assert(strcmp(encrypted, \"kj\") == 0);\n\n func0(\"et\", encrypted);\n assert(strcmp(encrypted, \"ix\") == 0);\n\n func0(\"faewfawefaewg\", encrypted);\n assert(strcmp(encrypted, \"jeiajeaijeiak\") == 0);\n\n func0(\"hellomyfriend\", encrypted);\n assert(strcmp(encrypted, \"lippsqcjvmirh\") == 0);\n\n func0(\"dxzdlmnilfuhmilufhlihufnmlimnufhlimnufhfucufh\", encrypted);\n assert(strcmp(encrypted, \"hbdhpqrmpjylqmpyjlpmlyjrqpmqryjlpmqryjljygyjl\") == 0);\n\n func0(\"a\", encrypted);\n assert(strcmp(encrypted, \"e\") == 0);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmov r8, rdi\nmovzx eax, byte ptr [rdi]\ntest al, al\njz short loc_11D4\nmov ecx, 0\nloc_119C:\nmovsx eax, al\nsub eax, 5Dh ; ']'\nmovsxd rdx, eax\nimul rdx, 4EC4EC4Fh\nsar rdx, 23h\nmov edi, eax\nsar edi, 1Fh\nsub edx, edi\nimul edx, 1Ah\nsub eax, edx\nadd eax, 61h ; 'a'\nmov [rsi+rcx], al\nadd rcx, 1\nmovzx eax, byte ptr [r8+rcx]\ntest al, al\njnz short loc_119C\nloc_11CF:\nmov byte ptr [rsi+rcx], 0\nretn\nloc_11D4:\nmov ecx, 0\njmp short loc_11CF", + "ida_pseudo": "__int64 __fastcall func0(unsigned __int8 *a1, __int64 a2)\n{\n __int64 result; // rax\n __int64 v3; // rcx\n\n result = *a1;\n if ( (_BYTE)result )\n {\n v3 = 0LL;\n do\n {\n *(_BYTE *)(a2 + v3++) = ((char)result - 93) % 26 + 97;\n result = a1[v3];\n }\n while ( (_BYTE)result );\n }\n else\n {\n v3 = 0LL;\n }\n *(_BYTE *)(a2 + v3) = 0;\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\nmov r8, rdi\nmovzx eax, byte ptr [rdi]\ntest al, al\njz short loc_11D4\nmov ecx, 0\nloc_119C:\nmovsx eax, al\nsub eax, 5Dh ; ']'\nmovsxd rdx, eax\nimul rdx, 4EC4EC4Fh\nsar rdx, 23h\nmov edi, eax\nsar edi, 1Fh\nsub edx, edi\nimul edx, 1Ah\nsub eax, edx\nadd eax, 61h ; 'a'\nmov [rsi+rcx], al\nadd rcx, 1\nmovzx eax, byte ptr [r8+rcx]\ntest al, al\njnz short loc_119C\nloc_11CF:\nmov byte ptr [rsi+rcx], 0\nretn\nloc_11D4:\nmov ecx, 0\njmp short loc_11CF", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(unsigned __int8 *a1, __int64 a2)\n{\n __int64 result; // rax\n __int64 v3; // rcx\n\n result = *a1;\n if ( (_BYTE)result )\n {\n v3 = 0LL;\n do\n {\n *(_BYTE *)(a2 + v3++) = ((char)result - 93) % 26 + 97;\n result = a1[v3];\n }\n while ( (_BYTE)result );\n }\n else\n {\n v3 = 0LL;\n }\n *(_BYTE *)(a2 + v3) = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(unsigned char *a1, long long a2) {\n long long result;\n long long v3;\n result = *a1;\n if ((uint8_t)result) {\n v3 = 0LL;\n do {\n *(uint8_t *)(a2 + v3++) = ((char)result - 93) % 26 + 97;\n result = a1[v3];\n } while ((uint8_t)result);\n } else {\n v3 = 0LL;\n }\n *(uint8_t *)(a2 + v3) = 0;\n return result;\n}", + "ida_pseudo_norm": "long long func0(unsigned char *a1, long long a2) {\n long long result;\n long long v3;\n result = *a1;\n if ((uint8_t)result) {\n v3 = 0LL;\n do {\n *(uint8_t *)(a2 + v3++) = ((char)result - 93) % 26 + 97;\n result = a1[v3];\n } while ((uint8_t)result);\n } else {\n v3 = 0LL;\n }\n *(uint8_t *)(a2 + v3) = 0;\n return result;\n}" + }, + { + "index": "HumanEval-C-89", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(const char *s, char *out) {\n int i;\n for (i = 0; s[i] != '\\0'; i++) {\n int w = ((int)s[i] - 'a' + 4) % 26 + 'a';\n out[i] = (char)w;\n }\n out[i] = '\\0';\n}", + "test": "#include \n#include \n#include \n\nint main() {\n char encrypted[100]; // Buffer should be large enough to hold the encrypted string\n\n func0(\"hi\", encrypted);\n assert(strcmp(encrypted, \"lm\") == 0);\n\n func0(\"asdfghjkl\", encrypted);\n assert(strcmp(encrypted, \"ewhjklnop\") == 0);\n\n func0(\"gf\", encrypted);\n assert(strcmp(encrypted, \"kj\") == 0);\n\n func0(\"et\", encrypted);\n assert(strcmp(encrypted, \"ix\") == 0);\n\n func0(\"faewfawefaewg\", encrypted);\n assert(strcmp(encrypted, \"jeiajeaijeiak\") == 0);\n\n func0(\"hellomyfriend\", encrypted);\n assert(strcmp(encrypted, \"lippsqcjvmirh\") == 0);\n\n func0(\"dxzdlmnilfuhmilufhlihufnmlimnufhlimnufhfucufh\", encrypted);\n assert(strcmp(encrypted, \"hbdhpqrmpjylqmpyjlpmlyjrqpmqryjlpmqryjljygyjl\") == 0);\n\n func0(\"a\", encrypted);\n assert(strcmp(encrypted, \"e\") == 0);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmovsx eax, byte ptr [rdi]\nmov r8, rdi\ntest al, al\njz short loc_1423\nxor ecx, ecx\nloc_13F0:\nsub eax, 5Dh ; ']'\nmovsxd rdx, eax\nmov edi, eax\nimul rdx, 4EC4EC4Fh\nsar edi, 1Fh\nsar rdx, 23h\nsub edx, edi\nimul edx, 1Ah\nsub eax, edx\nadd eax, 61h ; 'a'\nmov [rsi+rcx], al\nadd rcx, 1\nmovsx eax, byte ptr [r8+rcx]\ntest al, al\njnz short loc_13F0\nadd rsi, rcx\nloc_1423:\nmov byte ptr [rsi], 0\nretn", + "ida_pseudo": "__int64 __fastcall func0(_BYTE *a1, _BYTE *a2)\n{\n __int64 result; // rax\n __int64 v3; // rcx\n\n result = (unsigned int)(char)*a1;\n if ( *a1 )\n {\n v3 = 0LL;\n do\n {\n a2[v3++] = ((int)result - 93) % 26 + 97;\n result = (unsigned int)(char)a1[v3];\n }\n while ( a1[v3] );\n a2 += v3;\n }\n *a2 = 0;\n return result;\n}", + "ida_strip_asm": "sub_13E0:\nendbr64\nmovsx eax, byte ptr [rdi]\nmov r8, rdi\ntest al, al\njz short loc_1423\nxor ecx, ecx\nloc_13F0:\nsub eax, 5Dh ; ']'\nmovsxd rdx, eax\nmov edi, eax\nimul rdx, 4EC4EC4Fh\nsar edi, 1Fh\nsar rdx, 23h\nsub edx, edi\nimul edx, 1Ah\nsub eax, edx\nadd eax, 61h ; 'a'\nmov [rsi+rcx], al\nadd rcx, 1\nmovsx eax, byte ptr [r8+rcx]\ntest al, al\njnz short loc_13F0\nadd rsi, rcx\nloc_1423:\nmov byte ptr [rsi], 0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_13E0(_BYTE *a1, _BYTE *a2)\n{\n __int64 result; // rax\n __int64 v3; // rcx\n\n result = (unsigned int)(char)*a1;\n if ( *a1 )\n {\n v3 = 0LL;\n do\n {\n a2[v3++] = ((int)result - 93) % 26 + 97;\n result = (unsigned int)(char)a1[v3];\n }\n while ( a1[v3] );\n a2 += v3;\n }\n *a2 = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_13E0(uint8_t *a1, uint8_t *a2) {\n long long result;\n long long v3;\n result = (unsigned int)(char)*a1;\n if (*a1) {\n v3 = 0LL;\n do {\n a2[v3++] = ((int)result - 93) % 26 + 97;\n result = (unsigned int)(char)a1[v3];\n } while (a1[v3]);\n a2 += v3;\n }\n *a2 = 0;\n return result;\n}", + "ida_pseudo_norm": "long long func0(uint8_t *a1, uint8_t *a2) {\n long long result;\n long long v3;\n result = (unsigned int)(char)*a1;\n if (*a1) {\n v3 = 0LL;\n do {\n a2[v3++] = ((int)result - 93) % 26 + 97;\n result = (unsigned int)(char)a1[v3];\n } while (a1[v3]);\n a2 += v3;\n }\n *a2 = 0;\n return result;\n}" + }, + { + "index": "HumanEval-C-90", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(int *lst, int size) {\n if (size < 2) return -1;\n int first = INT_MAX, second = INT_MAX;\n for (int i = 0; i < size; ++i) {\n if (lst[i] < first) {\n second = first;\n first = lst[i];\n } else if (lst[i] < second && lst[i] != first) {\n second = lst[i];\n }\n }\n if (second == INT_MAX) return -1;\n return second;\n}", + "test": "#include \n\nint main() {\n int test1[] = {1, 2, 3, 4, 5};\n assert(func0(test1, 5) == 2);\n\n int test2[] = {5, 1, 4, 3, 2};\n assert(func0(test2, 5) == 2);\n\n assert(func0((const int[]){}, 0) == -1);\n\n int test4[] = {1, 1};\n assert(func0(test4, 2) == -1);\n\n int test5[] = {1, 1, 1, 1, 0};\n assert(func0(test5, 5) == 1);\n\n int test6[] = {-35, 34, 12, -45};\n assert(func0(test6, 4) == -35);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\ncmp [rbp+var_1C], 1\njg short loc_1188\nmov eax, 0FFFFFFFFh\njmp loc_1250\nloc_1188:\nmov [rbp+var_C], 7FFFFFFFh\nmov [rbp+var_8], 7FFFFFFFh\nmov [rbp+var_4], 0\njmp loc_1231\nloc_11A2:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_C], eax\njle short loc_11DE\nmov eax, [rbp+var_C]\nmov [rbp+var_8], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\njmp short loc_122D\nloc_11DE:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_8], eax\njle short loc_122D\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_C], eax\njz short loc_122D\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_8], eax\nloc_122D:\nadd [rbp+var_4], 1\nloc_1231:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl loc_11A2\ncmp [rbp+var_8], 7FFFFFFFh\njnz short loc_124D\nmov eax, 0FFFFFFFFh\njmp short loc_1250\nloc_124D:\nmov eax, [rbp+var_8]\nloc_1250:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int v3; // [rsp+10h] [rbp-Ch]\n int v4; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n if ( a2 <= 1 )\n return 0xFFFFFFFFLL;\n v3 = 0x7FFFFFFF;\n v4 = 0x7FFFFFFF;\n for ( i = 0; i < a2; ++i )\n {\n if ( v3 <= *(_DWORD *)(4LL * i + a1) )\n {\n if ( v4 > *(_DWORD *)(4LL * i + a1) && v3 != *(_DWORD *)(4LL * i + a1) )\n v4 = *(_DWORD *)(4LL * i + a1);\n }\n else\n {\n v4 = v3;\n v3 = *(_DWORD *)(4LL * i + a1);\n }\n }\n if ( v4 == 0x7FFFFFFF )\n return 0xFFFFFFFFLL;\n else\n return (unsigned int)v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\ncmp [rbp+var_1C], 1\njg short loc_1188\nmov eax, 0FFFFFFFFh\njmp loc_1250\nloc_1188:\nmov [rbp+var_C], 7FFFFFFFh\nmov [rbp+var_8], 7FFFFFFFh\nmov [rbp+var_4], 0\njmp loc_1231\nloc_11A2:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_C], eax\njle short loc_11DE\nmov eax, [rbp+var_C]\nmov [rbp+var_8], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\njmp short loc_122D\nloc_11DE:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_8], eax\njle short loc_122D\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_C], eax\njz short loc_122D\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_8], eax\nloc_122D:\nadd [rbp+var_4], 1\nloc_1231:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl loc_11A2\ncmp [rbp+var_8], 7FFFFFFFh\njnz short loc_124D\nmov eax, 0FFFFFFFFh\njmp short loc_1250\nloc_124D:\nmov eax, [rbp+var_8]\nloc_1250:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int v3; // [rsp+10h] [rbp-Ch]\n int v4; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n if ( a2 <= 1 )\n return 0xFFFFFFFFLL;\n v3 = 0x7FFFFFFF;\n v4 = 0x7FFFFFFF;\n for ( i = 0; i < a2; ++i )\n {\n if ( v3 <= *(_DWORD *)(4LL * i + a1) )\n {\n if ( v4 > *(_DWORD *)(4LL * i + a1) && v3 != *(_DWORD *)(4LL * i + a1) )\n v4 = *(_DWORD *)(4LL * i + a1);\n }\n else\n {\n v4 = v3;\n v3 = *(_DWORD *)(4LL * i + a1);\n }\n }\n if ( v4 == 0x7FFFFFFF )\n return 0xFFFFFFFFLL;\n else\n return (unsigned int)v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int v3;\n int v4;\n int i;\n if (a2 <= 1) return 4294967295LL;\n v3 = 2147483647;\n v4 = 2147483647;\n for (i = 0; i < a2; ++i) {\n if (v3 <= *(uint32_t *)(4LL * i + a1)) {\n if (v4 > *(uint32_t *)(4LL * i + a1) && v3 != *(uint32_t *)(4LL * i + a1))\n v4 = *(uint32_t *)(4LL * i + a1);\n } else {\n v4 = v3;\n v3 = *(uint32_t *)(4LL * i + a1);\n }\n }\n if (v4 == 2147483647)\n return 4294967295LL;\n else\n return (unsigned int)v4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int v3;\n int v4;\n int i;\n if (a2 <= 1) return 4294967295LL;\n v3 = 2147483647;\n v4 = 2147483647;\n for (i = 0; i < a2; ++i) {\n if (v3 <= *(uint32_t *)(4LL * i + a1)) {\n if (v4 > *(uint32_t *)(4LL * i + a1) && v3 != *(uint32_t *)(4LL * i + a1))\n v4 = *(uint32_t *)(4LL * i + a1);\n } else {\n v4 = v3;\n v3 = *(uint32_t *)(4LL * i + a1);\n }\n }\n if (v4 == 2147483647)\n return 4294967295LL;\n else\n return (unsigned int)v4;\n}" + }, + { + "index": "HumanEval-C-90", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(int *lst, int size) {\n if (size < 2) return -1;\n int first = INT_MAX, second = INT_MAX;\n for (int i = 0; i < size; ++i) {\n if (lst[i] < first) {\n second = first;\n first = lst[i];\n } else if (lst[i] < second && lst[i] != first) {\n second = lst[i];\n }\n }\n if (second == INT_MAX) return -1;\n return second;\n}", + "test": "#include \n\nint main() {\n int test1[] = {1, 2, 3, 4, 5};\n assert(func0(test1, 5) == 2);\n\n int test2[] = {5, 1, 4, 3, 2};\n assert(func0(test2, 5) == 2);\n\n assert(func0((const int[]){}, 0) == -1);\n\n int test4[] = {1, 1};\n assert(func0(test4, 2) == -1);\n\n int test5[] = {1, 1, 1, 1, 0};\n assert(func0(test5, 5) == 1);\n\n int test6[] = {-35, 34, 12, -45};\n assert(func0(test6, 4) == -35);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ncmp esi, 1\njle short loc_11B3\nmov rcx, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*4]\nmov eax, 7FFFFFFFh\nmov esi, 7FFFFFFFh\njmp short loc_1195\nloc_1188:\nmov eax, esi\nmov esi, edx\nloc_118C:\nadd rcx, 4\ncmp rcx, rdi\njz short loc_11AB\nloc_1195:\nmov edx, [rcx]\ncmp edx, esi\njl short loc_1188\nmov r8d, eax\ncmp edx, eax\ncmovle eax, edx\ncmp edx, esi\ncmovz eax, r8d\njmp short loc_118C\nloc_11AB:\ncmp eax, 7FFFFFFFh\njz short loc_11B9\nretn\nloc_11B3:\nmov eax, 0FFFFFFFFh\nretn\nloc_11B9:\nmov eax, 0FFFFFFFFh\nretn", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int *v2; // rcx\n int *v3; // rdi\n __int64 result; // rax\n int v5; // esi\n int v6; // edx\n unsigned int v7; // r8d\n\n if ( a2 <= 1 )\n return 0xFFFFFFFFLL;\n v2 = a1;\n v3 = &a1[a2];\n result = 0x7FFFFFFFLL;\n v5 = 0x7FFFFFFF;\n do\n {\n v6 = *v2;\n if ( *v2 < v5 )\n {\n result = (unsigned int)v5;\n v5 = *v2;\n }\n else\n {\n v7 = result;\n if ( v6 <= (int)result )\n result = (unsigned int)v6;\n if ( v6 == v5 )\n result = v7;\n }\n ++v2;\n }\n while ( v2 != v3 );\n if ( (_DWORD)result == 0x7FFFFFFF )\n return 0xFFFFFFFFLL;\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ncmp esi, 1\njle short loc_11B3\nmov rcx, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*4]\nmov eax, 7FFFFFFFh\nmov esi, 7FFFFFFFh\njmp short loc_1195\nloc_1188:\nmov eax, esi\nmov esi, edx\nloc_118C:\nadd rcx, 4\ncmp rcx, rdi\njz short loc_11AB\nloc_1195:\nmov edx, [rcx]\ncmp edx, esi\njl short loc_1188\nmov r8d, eax\ncmp edx, eax\ncmovle eax, edx\ncmp edx, esi\ncmovz eax, r8d\njmp short loc_118C\nloc_11AB:\ncmp eax, 7FFFFFFFh\njz short loc_11B9\nretn\nloc_11B3:\nmov eax, 0FFFFFFFFh\nretn\nloc_11B9:\nmov eax, 0FFFFFFFFh\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int *a1, int a2)\n{\n int *v2; // rcx\n int *v3; // rdi\n __int64 result; // rax\n int v5; // esi\n int v6; // edx\n unsigned int v7; // r8d\n\n if ( a2 <= 1 )\n return 0xFFFFFFFFLL;\n v2 = a1;\n v3 = &a1[a2];\n result = 0x7FFFFFFFLL;\n v5 = 0x7FFFFFFF;\n do\n {\n v6 = *v2;\n if ( *v2 < v5 )\n {\n result = (unsigned int)v5;\n v5 = *v2;\n }\n else\n {\n v7 = result;\n if ( v6 <= (int)result )\n result = (unsigned int)v6;\n if ( v6 == v5 )\n result = v7;\n }\n ++v2;\n }\n while ( v2 != v3 );\n if ( (_DWORD)result == 0x7FFFFFFF )\n return 0xFFFFFFFFLL;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int *a1, int a2) {\n int *v2;\n int *v3;\n long long result;\n int v5;\n int v6;\n unsigned int v7;\n if (a2 <= 1) return 4294967295LL;\n v2 = a1;\n v3 = &a1[a2];\n result = 2147483647LL;\n v5 = 2147483647;\n do {\n v6 = *v2;\n if (*v2 < v5) {\n result = (unsigned int)v5;\n v5 = *v2;\n } else {\n v7 = result;\n if (v6 <= (int)result) result = (unsigned int)v6;\n if (v6 == v5) result = v7;\n }\n ++v2;\n } while (v2 != v3);\n if ((uint32_t)result == 2147483647) return 4294967295LL;\n return result;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int *v2;\n int *v3;\n long long result;\n int v5;\n int v6;\n unsigned int v7;\n if (a2 <= 1) return 4294967295LL;\n v2 = a1;\n v3 = &a1[a2];\n result = 2147483647LL;\n v5 = 2147483647;\n do {\n v6 = *v2;\n if (*v2 < v5) {\n result = (unsigned int)v5;\n v5 = *v2;\n } else {\n v7 = result;\n if (v6 <= (int)result) result = (unsigned int)v6;\n if (v6 == v5) result = v7;\n }\n ++v2;\n } while (v2 != v3);\n if ((uint32_t)result == 2147483647) return 4294967295LL;\n return result;\n}" + }, + { + "index": "HumanEval-C-90", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(int *lst, int size) {\n if (size < 2) return -1;\n int first = INT_MAX, second = INT_MAX;\n for (int i = 0; i < size; ++i) {\n if (lst[i] < first) {\n second = first;\n first = lst[i];\n } else if (lst[i] < second && lst[i] != first) {\n second = lst[i];\n }\n }\n if (second == INT_MAX) return -1;\n return second;\n}", + "test": "#include \n\nint main() {\n int test1[] = {1, 2, 3, 4, 5};\n assert(func0(test1, 5) == 2);\n\n int test2[] = {5, 1, 4, 3, 2};\n assert(func0(test2, 5) == 2);\n\n assert(func0((const int[]){}, 0) == -1);\n\n int test4[] = {1, 1};\n assert(func0(test4, 2) == -1);\n\n int test5[] = {1, 1, 1, 1, 0};\n assert(func0(test5, 5) == 1);\n\n int test6[] = {-35, 34, 12, -45};\n assert(func0(test6, 4) == -35);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0_part_0:\ntest esi, esi\njle short loc_1360\nmovsxd rsi, esi\nmov ecx, 7FFFFFFFh\nmov edx, 7FFFFFFFh\nlea rsi, [rdi+rsi*4]\njmp short loc_1340\nloc_1330:\njz short loc_1337\ncmp ecx, eax\ncmovg ecx, eax\nloc_1337:\nadd rdi, 4\ncmp rsi, rdi\njz short loc_1353\nloc_1340:\nmov eax, [rdi]\ncmp edx, eax\njle short loc_1330\nadd rdi, 4\nmov ecx, edx\nmov edx, eax\ncmp rsi, rdi\njnz short loc_1340\nloc_1353:\ncmp ecx, 7FFFFFFFh\njz short loc_1360\nmov eax, ecx\nretn\nloc_1360:\nmov ecx, 0FFFFFFFFh\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0_part_0(int *a1, int a2)\n{\n int v2; // ecx\n int v3; // edx\n int *v4; // rsi\n int v5; // eax\n\n if ( a2 <= 0 )\n return 0xFFFFFFFFLL;\n v2 = 0x7FFFFFFF;\n v3 = 0x7FFFFFFF;\n v4 = &a1[a2];\n do\n {\n while ( 1 )\n {\n v5 = *a1;\n if ( v3 <= *a1 )\n break;\n ++a1;\n v2 = v3;\n v3 = v5;\n if ( v4 == a1 )\n goto LABEL_9;\n }\n if ( v3 != v5 && v2 > v5 )\n v2 = *a1;\n ++a1;\n }\n while ( v4 != a1 );\nLABEL_9:\n if ( v2 == 0x7FFFFFFF )\n return 0xFFFFFFFFLL;\n else\n return (unsigned int)v2;\n}", + "ida_strip_asm": "sub_1310:\ntest esi, esi\njle short loc_1360\nmovsxd rsi, esi\nmov ecx, 7FFFFFFFh\nmov edx, 7FFFFFFFh\nlea rsi, [rdi+rsi*4]\njmp short loc_1340\nloc_1330:\njz short loc_1337\ncmp ecx, eax\ncmovg ecx, eax\nloc_1337:\nadd rdi, 4\ncmp rsi, rdi\njz short loc_1353\nloc_1340:\nmov eax, [rdi]\ncmp edx, eax\njle short loc_1330\nadd rdi, 4\nmov ecx, edx\nmov edx, eax\ncmp rsi, rdi\njnz short loc_1340\nloc_1353:\ncmp ecx, 7FFFFFFFh\njz short loc_1360\nmov eax, ecx\nretn\nloc_1360:\nmov ecx, 0FFFFFFFFh\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1310(int *a1, int a2)\n{\n int v2; // ecx\n int v3; // edx\n int *v4; // rsi\n int v5; // eax\n\n if ( a2 <= 0 )\n return 0xFFFFFFFFLL;\n v2 = 0x7FFFFFFF;\n v3 = 0x7FFFFFFF;\n v4 = &a1[a2];\n do\n {\n while ( 1 )\n {\n v5 = *a1;\n if ( v3 <= *a1 )\n break;\n ++a1;\n v2 = v3;\n v3 = v5;\n if ( v4 == a1 )\n goto LABEL_9;\n }\n if ( v3 != v5 && v2 > v5 )\n v2 = *a1;\n ++a1;\n }\n while ( v4 != a1 );\nLABEL_9:\n if ( v2 == 0x7FFFFFFF )\n return 0xFFFFFFFFLL;\n else\n return (unsigned int)v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1310(int *a1, int a2) {\n int v2;\n int v3;\n int *v4;\n int v5;\n if (a2 <= 0) return 4294967295LL;\n v2 = 2147483647;\n v3 = 2147483647;\n v4 = &a1[a2];\n do {\n while (1) {\n v5 = *a1;\n if (v3 <= *a1) break;\n ++a1;\n v2 = v3;\n v3 = v5;\n if (v4 == a1) goto LABEL_9;\n }\n if (v3 != v5 && v2 > v5) v2 = *a1;\n ++a1;\n } while (v4 != a1);\nLABEL_9:\n if (v2 == 2147483647)\n return 4294967295LL;\n else\n return (unsigned int)v2;\n}", + "ida_pseudo_norm": "long long func0_part_0(int *a1, int a2) {\n int v2;\n int v3;\n int *v4;\n int v5;\n if (a2 <= 0) return 4294967295LL;\n v2 = 2147483647;\n v3 = 2147483647;\n v4 = &a1[a2];\n do {\n while (1) {\n v5 = *a1;\n if (v3 <= *a1) break;\n ++a1;\n v2 = v3;\n v3 = v5;\n if (v4 == a1) goto LABEL_9;\n }\n if (v3 != v5 && v2 > v5) v2 = *a1;\n ++a1;\n } while (v4 != a1);\nLABEL_9:\n if (v2 == 2147483647)\n return 4294967295LL;\n else\n return (unsigned int)v2;\n}" + }, + { + "index": "HumanEval-C-90", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(int *lst, int size) {\n if (size < 2) return -1;\n int first = INT_MAX, second = INT_MAX;\n for (int i = 0; i < size; ++i) {\n if (lst[i] < first) {\n second = first;\n first = lst[i];\n } else if (lst[i] < second && lst[i] != first) {\n second = lst[i];\n }\n }\n if (second == INT_MAX) return -1;\n return second;\n}", + "test": "#include \n\nint main() {\n int test1[] = {1, 2, 3, 4, 5};\n assert(func0(test1, 5) == 2);\n\n int test2[] = {5, 1, 4, 3, 2};\n assert(func0(test2, 5) == 2);\n\n assert(func0((const int[]){}, 0) == -1);\n\n int test4[] = {1, 1};\n assert(func0(test4, 2) == -1);\n\n int test5[] = {1, 1, 1, 1, 0};\n assert(func0(test5, 5) == 1);\n\n int test6[] = {-35, 34, 12, -45};\n assert(func0(test6, 4) == -35);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0_part_0:\ntest esi, esi\njle short loc_1360\nmovsxd rsi, esi\nmov ecx, 7FFFFFFFh\nmov edx, 7FFFFFFFh\nlea rsi, [rdi+rsi*4]\njmp short loc_1340\nloc_1330:\njz short loc_1337\ncmp ecx, eax\ncmovg ecx, eax\nloc_1337:\nadd rdi, 4\ncmp rsi, rdi\njz short loc_1353\nloc_1340:\nmov eax, [rdi]\ncmp edx, eax\njle short loc_1330\nadd rdi, 4\nmov ecx, edx\nmov edx, eax\ncmp rsi, rdi\njnz short loc_1340\nloc_1353:\ncmp ecx, 7FFFFFFFh\njz short loc_1360\nmov eax, ecx\nretn\nloc_1360:\nmov ecx, 0FFFFFFFFh\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0_part_0(int *a1, int a2)\n{\n int v2; // ecx\n int v3; // edx\n int *v4; // rsi\n int v5; // eax\n\n if ( a2 <= 0 )\n return 0xFFFFFFFFLL;\n v2 = 0x7FFFFFFF;\n v3 = 0x7FFFFFFF;\n v4 = &a1[a2];\n do\n {\n while ( 1 )\n {\n v5 = *a1;\n if ( v3 <= *a1 )\n break;\n ++a1;\n v2 = v3;\n v3 = v5;\n if ( v4 == a1 )\n goto LABEL_9;\n }\n if ( v3 != v5 && v2 > v5 )\n v2 = *a1;\n ++a1;\n }\n while ( v4 != a1 );\nLABEL_9:\n if ( v2 == 0x7FFFFFFF )\n return 0xFFFFFFFFLL;\n else\n return (unsigned int)v2;\n}", + "ida_strip_asm": "sub_1310:\ntest esi, esi\njle short loc_1360\nmovsxd rsi, esi\nmov ecx, 7FFFFFFFh\nmov edx, 7FFFFFFFh\nlea rsi, [rdi+rsi*4]\njmp short loc_1340\nloc_1330:\njz short loc_1337\ncmp ecx, eax\ncmovg ecx, eax\nloc_1337:\nadd rdi, 4\ncmp rsi, rdi\njz short loc_1353\nloc_1340:\nmov eax, [rdi]\ncmp edx, eax\njle short loc_1330\nadd rdi, 4\nmov ecx, edx\nmov edx, eax\ncmp rsi, rdi\njnz short loc_1340\nloc_1353:\ncmp ecx, 7FFFFFFFh\njz short loc_1360\nmov eax, ecx\nretn\nloc_1360:\nmov ecx, 0FFFFFFFFh\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1310(int *a1, int a2)\n{\n int v2; // ecx\n int v3; // edx\n int *v4; // rsi\n int v5; // eax\n\n if ( a2 <= 0 )\n return 0xFFFFFFFFLL;\n v2 = 0x7FFFFFFF;\n v3 = 0x7FFFFFFF;\n v4 = &a1[a2];\n do\n {\n while ( 1 )\n {\n v5 = *a1;\n if ( v3 <= *a1 )\n break;\n ++a1;\n v2 = v3;\n v3 = v5;\n if ( v4 == a1 )\n goto LABEL_9;\n }\n if ( v3 != v5 && v2 > v5 )\n v2 = *a1;\n ++a1;\n }\n while ( v4 != a1 );\nLABEL_9:\n if ( v2 == 0x7FFFFFFF )\n return 0xFFFFFFFFLL;\n else\n return (unsigned int)v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1310(int *a1, int a2) {\n int v2;\n int v3;\n int *v4;\n int v5;\n if (a2 <= 0) return 4294967295LL;\n v2 = 2147483647;\n v3 = 2147483647;\n v4 = &a1[a2];\n do {\n while (1) {\n v5 = *a1;\n if (v3 <= *a1) break;\n ++a1;\n v2 = v3;\n v3 = v5;\n if (v4 == a1) goto LABEL_9;\n }\n if (v3 != v5 && v2 > v5) v2 = *a1;\n ++a1;\n } while (v4 != a1);\nLABEL_9:\n if (v2 == 2147483647)\n return 4294967295LL;\n else\n return (unsigned int)v2;\n}", + "ida_pseudo_norm": "long long func0_part_0(int *a1, int a2) {\n int v2;\n int v3;\n int *v4;\n int v5;\n if (a2 <= 0) return 4294967295LL;\n v2 = 2147483647;\n v3 = 2147483647;\n v4 = &a1[a2];\n do {\n while (1) {\n v5 = *a1;\n if (v3 <= *a1) break;\n ++a1;\n v2 = v3;\n v3 = v5;\n if (v4 == a1) goto LABEL_9;\n }\n if (v3 != v5 && v2 > v5) v2 = *a1;\n ++a1;\n } while (v4 != a1);\nLABEL_9:\n if (v2 == 2147483647)\n return 4294967295LL;\n else\n return (unsigned int)v2;\n}" + }, + { + "index": "HumanEval-C-91", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int func0(const char *S) {\n int isstart = 1;\n int isi = 0;\n int sum = 0;\n for (int i = 0; S[i] != '\\0'; i++) {\n if (isspace(S[i]) && isi) {\n isi = 0;\n sum += 1;\n }\n if (S[i] == 'I' && isstart) {\n isi = 1;\n } else if (!isspace(S[i])) {\n isi = 0;\n }\n if (!isspace(S[i])) {\n isstart = 0;\n }\n if (S[i] == '.' || S[i] == '?' || S[i] == '!') {\n isstart = 1;\n }\n }\n return sum;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"Hello world\") == 0);\n assert(func0(\"Is the sky blue?\") == 0);\n assert(func0(\"I love It !\") == 1);\n assert(func0(\"bIt\") == 0);\n assert(func0(\"I feel good today. I will be productive. will kill It\") == 2);\n assert(func0(\"You and I are going for a walk\") == 0);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_10], 1\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp loc_12B6\nloc_119A:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_4]\nmovsxd rcx, edx\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 2000h\ntest eax, eax\njz short loc_11DC\ncmp [rbp+var_C], 0\njz short loc_11DC\nmov [rbp+var_C], 0\nadd [rbp+var_8], 1\nloc_11DC:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 49h ; 'I'\njnz short loc_11FF\ncmp [rbp+var_10], 0\njz short loc_11FF\nmov [rbp+var_C], 1\njmp short loc_1237\nloc_11FF:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_4]\nmovsxd rcx, edx\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 2000h\ntest eax, eax\njnz short loc_1237\nmov [rbp+var_C], 0\nloc_1237:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_4]\nmovsxd rcx, edx\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 2000h\ntest eax, eax\njnz short loc_126F\nmov [rbp+var_10], 0\nloc_126F:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 2Eh ; '.'\njz short loc_12AB\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 3Fh ; '?'\njz short loc_12AB\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 21h ; '!'\njnz short loc_12B2\nloc_12AB:\nmov [rbp+var_10], 1\nloc_12B2:\nadd [rbp+var_4], 1\nloc_12B6:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_119A\nmov eax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1)\n{\n int v2; // [rsp+10h] [rbp-10h]\n int v3; // [rsp+14h] [rbp-Ch]\n unsigned int v4; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v2 = 1;\n v3 = 0;\n v4 = 0;\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n {\n if ( ((*__ctype_b_loc())[*(char *)(i + a1)] & 0x2000) != 0 && v3 )\n {\n v3 = 0;\n ++v4;\n }\n if ( *(_BYTE *)(i + a1) == 73 && v2 )\n {\n v3 = 1;\n }\n else if ( ((*__ctype_b_loc())[*(char *)(i + a1)] & 0x2000) == 0 )\n {\n v3 = 0;\n }\n if ( ((*__ctype_b_loc())[*(char *)(i + a1)] & 0x2000) == 0 )\n v2 = 0;\n if ( *(_BYTE *)(i + a1) == 46 || *(_BYTE *)(i + a1) == 63 || *(_BYTE *)(i + a1) == 33 )\n v2 = 1;\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_10], 1\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp loc_12B6\nloc_119A:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_4]\nmovsxd rcx, edx\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 2000h\ntest eax, eax\njz short loc_11DC\ncmp [rbp+var_C], 0\njz short loc_11DC\nmov [rbp+var_C], 0\nadd [rbp+var_8], 1\nloc_11DC:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 49h ; 'I'\njnz short loc_11FF\ncmp [rbp+var_10], 0\njz short loc_11FF\nmov [rbp+var_C], 1\njmp short loc_1237\nloc_11FF:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_4]\nmovsxd rcx, edx\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 2000h\ntest eax, eax\njnz short loc_1237\nmov [rbp+var_C], 0\nloc_1237:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_4]\nmovsxd rcx, edx\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 2000h\ntest eax, eax\njnz short loc_126F\nmov [rbp+var_10], 0\nloc_126F:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 2Eh ; '.'\njz short loc_12AB\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 3Fh ; '?'\njz short loc_12AB\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 21h ; '!'\njnz short loc_12B2\nloc_12AB:\nmov [rbp+var_10], 1\nloc_12B2:\nadd [rbp+var_4], 1\nloc_12B6:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_119A\nmov eax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1)\n{\n int v2; // [rsp+10h] [rbp-10h]\n int v3; // [rsp+14h] [rbp-Ch]\n unsigned int v4; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v2 = 1;\n v3 = 0;\n v4 = 0;\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n {\n if ( ((*__ctype_b_loc())[*(char *)(i + a1)] & 0x2000) != 0 && v3 )\n {\n v3 = 0;\n ++v4;\n }\n if ( *(_BYTE *)(i + a1) == 73 && v2 )\n {\n v3 = 1;\n }\n else if ( ((*__ctype_b_loc())[*(char *)(i + a1)] & 0x2000) == 0 )\n {\n v3 = 0;\n }\n if ( ((*__ctype_b_loc())[*(char *)(i + a1)] & 0x2000) == 0 )\n v2 = 0;\n if ( *(_BYTE *)(i + a1) == 46 || *(_BYTE *)(i + a1) == 63 || *(_BYTE *)(i + a1) == 33 )\n v2 = 1;\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1) {\n int v2;\n int v3;\n unsigned int v4;\n int i;\n v2 = 1;\n v3 = 0;\n v4 = 0;\n for (i = 0; *(uint8_t *)(i + a1); ++i) {\n if (((*__ctype_b_loc())[*(char *)(i + a1)] & 8192) != 0 && v3) {\n v3 = 0;\n ++v4;\n }\n if (*(uint8_t *)(i + a1) == 73 && v2) {\n v3 = 1;\n } else if (((*__ctype_b_loc())[*(char *)(i + a1)] & 8192) == 0) {\n v3 = 0;\n }\n if (((*__ctype_b_loc())[*(char *)(i + a1)] & 8192) == 0) v2 = 0;\n if (*(uint8_t *)(i + a1) == 46 || *(uint8_t *)(i + a1) == 63 ||\n *(uint8_t *)(i + a1) == 33)\n v2 = 1;\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(long long a1) {\n int v2;\n int v3;\n unsigned int v4;\n int i;\n v2 = 1;\n v3 = 0;\n v4 = 0;\n for (i = 0; *(uint8_t *)(i + a1); ++i) {\n if (((*__ctype_b_loc())[*(char *)(i + a1)] & 8192) != 0 && v3) {\n v3 = 0;\n ++v4;\n }\n if (*(uint8_t *)(i + a1) == 73 && v2) {\n v3 = 1;\n } else if (((*__ctype_b_loc())[*(char *)(i + a1)] & 8192) == 0) {\n v3 = 0;\n }\n if (((*__ctype_b_loc())[*(char *)(i + a1)] & 8192) == 0) v2 = 0;\n if (*(uint8_t *)(i + a1) == 46 || *(uint8_t *)(i + a1) == 63 ||\n *(uint8_t *)(i + a1) == 33)\n v2 = 1;\n }\n return v4;\n}" + }, + { + "index": "HumanEval-C-91", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int func0(const char *S) {\n int isstart = 1;\n int isi = 0;\n int sum = 0;\n for (int i = 0; S[i] != '\\0'; i++) {\n if (isspace(S[i]) && isi) {\n isi = 0;\n sum += 1;\n }\n if (S[i] == 'I' && isstart) {\n isi = 1;\n } else if (!isspace(S[i])) {\n isi = 0;\n }\n if (!isspace(S[i])) {\n isstart = 0;\n }\n if (S[i] == '.' || S[i] == '?' || S[i] == '!') {\n isstart = 1;\n }\n }\n return sum;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"Hello world\") == 0);\n assert(func0(\"Is the sky blue?\") == 0);\n assert(func0(\"I love It !\") == 1);\n assert(func0(\"bIt\") == 0);\n assert(func0(\"I feel good today. I will be productive. will kill It\") == 2);\n assert(func0(\"You and I are going for a walk\") == 0);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz loc_1219\nmov rbp, rdi\ncall ___ctype_b_loc\nmov r8, [rax]\nlea rdi, [rbp+1]\nmov r11d, 0\nmov ecx, 0\nmov edx, 1\nmov esi, 0\nmov r10, 8000400200000000h\nmov r9d, 1\njmp short loc_11ED\nloc_11B4:\nadd r11d, 1\ntest edx, edx\njz short loc_11C6\nmov ecx, 1\ncmp bl, 49h ; 'I'\njz short loc_11E1\nloc_11C6:\nmov ecx, 0\nloc_11CB:\ntest ax, ax\ncmovz ecx, esi\ncmovz edx, esi\ncmp bl, 3Fh ; '?'\nja short loc_11E1\nbt r10, rbx\ncmovb edx, r9d\nloc_11E1:\nadd rdi, 1\nmovzx ebx, byte ptr [rdi-1]\ntest bl, bl\njz short loc_121F\nloc_11ED:\nmovsx rax, bl\nmovzx eax, word ptr [r8+rax*2]\nand ax, 2000h\ntest ecx, ecx\njz short loc_1203\ntest ax, ax\njnz short loc_11B4\nloc_1203:\ntest edx, edx\njz short loc_11CB\ncmp bl, 49h ; 'I'\njnz short loc_11CB\nmov ecx, 1\ntest ax, ax\ncmovz edx, esi\njmp short loc_11E1\nloc_1219:\nmov r11d, 0\nloc_121F:\nmov eax, r11d\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned __int8 *a1)\n{\n unsigned __int64 v1; // rbx\n const unsigned __int16 *v2; // r8\n unsigned __int8 *v3; // rdi\n unsigned int v4; // r11d\n int v5; // ecx\n int v6; // edx\n unsigned __int64 v7; // r10\n __int16 v8; // ax\n\n v1 = *a1;\n if ( (_BYTE)v1 )\n {\n v2 = *__ctype_b_loc();\n v3 = a1 + 1;\n v4 = 0;\n v5 = 0;\n v6 = 1;\n v7 = 0x8000400200000000LL;\n while ( 1 )\n {\n v8 = v2[(char)v1] & 0x2000;\n if ( v5 && v8 )\n {\n ++v4;\n if ( !v6 || (v5 = 1, (_BYTE)v1 != 73) )\n {\n v5 = 0;\nLABEL_6:\n if ( !v8 )\n {\n v5 = 0;\n v6 = 0;\n }\n if ( (unsigned __int8)v1 <= 0x3Fu && _bittest64((const __int64 *)&v7, v1) )\n v6 = 1;\n }\n }\n else\n {\n if ( !v6 || (_BYTE)v1 != 73 )\n goto LABEL_6;\n v5 = 1;\n if ( !v8 )\n v6 = 0;\n }\n v1 = *v3++;\n if ( !(_BYTE)v1 )\n return v4;\n }\n }\n return 0;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz loc_1219\nmov rbp, rdi\ncall ___ctype_b_loc\nmov r8, [rax]\nlea rdi, [rbp+1]\nmov r11d, 0\nmov ecx, 0\nmov edx, 1\nmov esi, 0\nmov r10, 8000400200000000h\nmov r9d, 1\njmp short loc_11ED\nloc_11B4:\nadd r11d, 1\ntest edx, edx\njz short loc_11C6\nmov ecx, 1\ncmp bl, 49h ; 'I'\njz short loc_11E1\nloc_11C6:\nmov ecx, 0\nloc_11CB:\ntest ax, ax\ncmovz ecx, esi\ncmovz edx, esi\ncmp bl, 3Fh ; '?'\nja short loc_11E1\nbt r10, rbx\ncmovb edx, r9d\nloc_11E1:\nadd rdi, 1\nmovzx ebx, byte ptr [rdi-1]\ntest bl, bl\njz short loc_121F\nloc_11ED:\nmovsx rax, bl\nmovzx eax, word ptr [r8+rax*2]\nand ax, 2000h\ntest ecx, ecx\njz short loc_1203\ntest ax, ax\njnz short loc_11B4\nloc_1203:\ntest edx, edx\njz short loc_11CB\ncmp bl, 49h ; 'I'\njnz short loc_11CB\nmov ecx, 1\ntest ax, ax\ncmovz edx, esi\njmp short loc_11E1\nloc_1219:\nmov r11d, 0\nloc_121F:\nmov eax, r11d\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(unsigned __int8 *a1)\n{\n unsigned __int64 v1; // rbx\n const unsigned __int16 *v2; // r8\n unsigned __int8 *v3; // rdi\n unsigned int v4; // r11d\n int v5; // ecx\n int v6; // edx\n unsigned __int64 v7; // r10\n __int16 v8; // ax\n\n v1 = *a1;\n if ( (_BYTE)v1 )\n {\n v2 = *__ctype_b_loc();\n v3 = a1 + 1;\n v4 = 0;\n v5 = 0;\n v6 = 1;\n v7 = 0x8000400200000000LL;\n while ( 1 )\n {\n v8 = v2[(char)v1] & 0x2000;\n if ( v5 && v8 )\n {\n ++v4;\n if ( !v6 || (v5 = 1, (_BYTE)v1 != 73) )\n {\n v5 = 0;\nLABEL_6:\n if ( !v8 )\n {\n v5 = 0;\n v6 = 0;\n }\n if ( (unsigned __int8)v1 <= 0x3Fu && _bittest64((const __int64 *)&v7, v1) )\n v6 = 1;\n }\n }\n else\n {\n if ( !v6 || (_BYTE)v1 != 73 )\n goto LABEL_6;\n v5 = 1;\n if ( !v8 )\n v6 = 0;\n }\n v1 = *v3++;\n if ( !(_BYTE)v1 )\n return v4;\n }\n }\n return 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(unsigned char *a1) {\n unsigned long long v1;\n const unsigned short *v2;\n unsigned char *v3;\n unsigned int v4;\n int v5;\n int v6;\n unsigned long long v7;\n short v8;\n v1 = *a1;\n if ((uint8_t)v1) {\n v2 = *__ctype_b_loc();\n v3 = a1 + 1;\n v4 = 0;\n v5 = 0;\n v6 = 1;\n v7 = 9223442414188888064LL;\n while (1) {\n v8 = v2[(char)v1] & 8192;\n if (v5 && v8) {\n ++v4;\n if (!v6 || (v5 = 1, (uint8_t)v1 != 73)) {\n v5 = 0;\n LABEL_6:\n if (!v8) {\n v5 = 0;\n v6 = 0;\n }\n if ((unsigned char)v1 <= 63u &&\n _bittest64((const long long *)&v7, v1))\n v6 = 1;\n }\n } else {\n if (!v6 || (uint8_t)v1 != 73) goto LABEL_6;\n v5 = 1;\n if (!v8) v6 = 0;\n }\n v1 = *v3++;\n if (!(uint8_t)v1) return v4;\n }\n }\n return 0;\n}", + "ida_pseudo_norm": "long long func0(unsigned char *a1) {\n unsigned long long v1;\n const unsigned short *v2;\n unsigned char *v3;\n unsigned int v4;\n int v5;\n int v6;\n unsigned long long v7;\n short v8;\n v1 = *a1;\n if ((uint8_t)v1) {\n v2 = *__ctype_b_loc();\n v3 = a1 + 1;\n v4 = 0;\n v5 = 0;\n v6 = 1;\n v7 = 9223442414188888064LL;\n while (1) {\n v8 = v2[(char)v1] & 8192;\n if (v5 && v8) {\n ++v4;\n if (!v6 || (v5 = 1, (uint8_t)v1 != 73)) {\n v5 = 0;\n LABEL_6:\n if (!v8) {\n v5 = 0;\n v6 = 0;\n }\n if ((unsigned char)v1 <= 63u &&\n _bittest64((const long long *)&v7, v1))\n v6 = 1;\n }\n } else {\n if (!v6 || (uint8_t)v1 != 73) goto LABEL_6;\n v5 = 1;\n if (!v8) v6 = 0;\n }\n v1 = *v3++;\n if (!(uint8_t)v1) return v4;\n }\n }\n return 0;\n}" + }, + { + "index": "HumanEval-C-91", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int func0(const char *S) {\n int isstart = 1;\n int isi = 0;\n int sum = 0;\n for (int i = 0; S[i] != '\\0'; i++) {\n if (isspace(S[i]) && isi) {\n isi = 0;\n sum += 1;\n }\n if (S[i] == 'I' && isstart) {\n isi = 1;\n } else if (!isspace(S[i])) {\n isi = 0;\n }\n if (!isspace(S[i])) {\n isstart = 0;\n }\n if (S[i] == '.' || S[i] == '?' || S[i] == '!') {\n isstart = 1;\n }\n }\n return sum;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"Hello world\") == 0);\n assert(func0(\"Is the sky blue?\") == 0);\n assert(func0(\"I love It !\") == 1);\n assert(func0(\"bIt\") == 0);\n assert(func0(\"I feel good today. I will be productive. will kill It\") == 2);\n assert(func0(\"You and I are going for a walk\") == 0);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz loc_1370\nmov rbp, rdi\ncall ___ctype_b_loc\nlea rdi, [rbp+1]\nxor r11d, r11d\nxor esi, esi\nmov r8, [rax]\nmov ecx, 1\nmov r10, 8000400200000000h\nmov r9d, 1\njmp short loc_1310\nloc_12F0:\ntest dl, dl\njnz short loc_1333\nxor ecx, ecx\nloc_12F6:\nxor esi, esi\ncmp bl, 3Fh ; '?'\nja short loc_1305\nbt r10, rbx\ncmovb ecx, r9d\nloc_1305:\nmovzx ebx, byte ptr [rdi]\nadd rdi, 1\ntest bl, bl\njz short loc_134B\nloc_1310:\nmovsx rax, bl\ncmp bl, 49h ; 'I'\nmovzx eax, word ptr [r8+rax*2]\nsetz dl\nand edx, ecx\nand ax, 2000h\njz short loc_12F0\ntest esi, esi\njz short loc_1358\nadd r11d, 1\ntest dl, dl\njz short loc_12F6\nloc_1333:\nxor ecx, ecx\ntest ax, ax\nmov esi, 1\nsetnz cl\nloc_1340:\nmovzx ebx, byte ptr [rdi]\nadd rdi, 1\ntest bl, bl\njnz short loc_1310\nloc_134B:\nadd rsp, 8\nmov eax, r11d\npop rbx\npop rbp\nretn\nloc_1358:\ntest dl, dl\njz short loc_12F6\nxor ecx, ecx\ntest ax, ax\nmov esi, 1\nsetnz cl\njmp short loc_1340\nloc_1370:\nadd rsp, 8\nxor r11d, r11d\nmov eax, r11d\npop rbx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned __int8 *a1)\n{\n unsigned __int64 v1; // rbx\n const unsigned __int16 **v2; // rax\n unsigned __int8 *v3; // rdi\n unsigned int v4; // r11d\n int v5; // esi\n const unsigned __int16 *v6; // r8\n bool v7; // cl\n unsigned __int64 v8; // r10\n bool v9; // dl\n __int16 v10; // ax\n\n v1 = *a1;\n if ( (_BYTE)v1 )\n {\n v2 = __ctype_b_loc();\n v3 = a1 + 1;\n v4 = 0;\n v5 = 0;\n v6 = *v2;\n v7 = 1;\n v8 = 0x8000400200000000LL;\n while ( 1 )\n {\n while ( 1 )\n {\n v9 = v7 && (_BYTE)v1 == 73;\n v10 = v6[(char)v1] & 0x2000;\n if ( !v10 )\n break;\n if ( v5 )\n {\n ++v4;\n if ( v9 )\n goto LABEL_12;\n }\n else if ( v9 )\n {\n v5 = 1;\n v7 = v10 != 0;\n goto LABEL_13;\n }\nLABEL_5:\n v5 = 0;\n if ( (unsigned __int8)v1 <= 0x3Fu )\n {\n if ( _bittest64((const __int64 *)&v8, v1) )\n v7 = 1;\n }\n v1 = *v3++;\n if ( !(_BYTE)v1 )\n return v4;\n }\n if ( !v9 )\n {\n v7 = 0;\n goto LABEL_5;\n }\nLABEL_12:\n v5 = 1;\n v7 = v10 != 0;\nLABEL_13:\n v1 = *v3++;\n if ( !(_BYTE)v1 )\n return v4;\n }\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_12B0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz loc_1370\nmov rbp, rdi\ncall ___ctype_b_loc\nlea rdi, [rbp+1]\nxor r11d, r11d\nxor esi, esi\nmov r8, [rax]\nmov ecx, 1\nmov r10, 8000400200000000h\nmov r9d, 1\njmp short loc_1310\nloc_12F0:\ntest dl, dl\njnz short loc_1333\nxor ecx, ecx\nloc_12F6:\nxor esi, esi\ncmp bl, 3Fh ; '?'\nja short loc_1305\nbt r10, rbx\ncmovb ecx, r9d\nloc_1305:\nmovzx ebx, byte ptr [rdi]\nadd rdi, 1\ntest bl, bl\njz short loc_134B\nloc_1310:\nmovsx rax, bl\ncmp bl, 49h ; 'I'\nmovzx eax, word ptr [r8+rax*2]\nsetz dl\nand edx, ecx\nand ax, 2000h\njz short loc_12F0\ntest esi, esi\njz short loc_1358\nadd r11d, 1\ntest dl, dl\njz short loc_12F6\nloc_1333:\nxor ecx, ecx\ntest ax, ax\nmov esi, 1\nsetnz cl\nloc_1340:\nmovzx ebx, byte ptr [rdi]\nadd rdi, 1\ntest bl, bl\njnz short loc_1310\nloc_134B:\nadd rsp, 8\nmov eax, r11d\npop rbx\npop rbp\nretn\nloc_1358:\ntest dl, dl\njz short loc_12F6\nxor ecx, ecx\ntest ax, ax\nmov esi, 1\nsetnz cl\njmp short loc_1340\nloc_1370:\nadd rsp, 8\nxor r11d, r11d\nmov eax, r11d\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12B0(unsigned __int8 *a1)\n{\n unsigned __int64 v1; // rbx\n const unsigned __int16 **v2; // rax\n unsigned __int8 *v3; // rdi\n unsigned int v4; // r11d\n int v5; // esi\n const unsigned __int16 *v6; // r8\n bool v7; // cl\n unsigned __int64 v8; // r10\n bool v9; // dl\n __int16 v10; // ax\n\n v1 = *a1;\n if ( (_BYTE)v1 )\n {\n v2 = __ctype_b_loc();\n v3 = a1 + 1;\n v4 = 0;\n v5 = 0;\n v6 = *v2;\n v7 = 1;\n v8 = 0x8000400200000000LL;\n while ( 1 )\n {\n while ( 1 )\n {\n v9 = v7 && (_BYTE)v1 == 73;\n v10 = v6[(char)v1] & 0x2000;\n if ( !v10 )\n break;\n if ( v5 )\n {\n ++v4;\n if ( v9 )\n goto LABEL_12;\n }\n else if ( v9 )\n {\n v5 = 1;\n v7 = v10 != 0;\n goto LABEL_13;\n }\nLABEL_5:\n v5 = 0;\n if ( (unsigned __int8)v1 <= 0x3Fu )\n {\n if ( _bittest64((const __int64 *)&v8, v1) )\n v7 = 1;\n }\n v1 = *v3++;\n if ( !(_BYTE)v1 )\n return v4;\n }\n if ( !v9 )\n {\n v7 = 0;\n goto LABEL_5;\n }\nLABEL_12:\n v5 = 1;\n v7 = v10 != 0;\nLABEL_13:\n v1 = *v3++;\n if ( !(_BYTE)v1 )\n return v4;\n }\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12B0(unsigned char *a1) {\n unsigned long long v1;\n const unsigned short **v2;\n unsigned char *v3;\n unsigned int v4;\n int v5;\n const unsigned short *v6;\n bool v7;\n unsigned long long v8;\n bool v9;\n short v10;\n v1 = *a1;\n if ((uint8_t)v1) {\n v2 = __ctype_b_loc();\n v3 = a1 + 1;\n v4 = 0;\n v5 = 0;\n v6 = *v2;\n v7 = 1;\n v8 = 9223442414188888064LL;\n while (1) {\n while (1) {\n v9 = v7 && (uint8_t)v1 == 73;\n v10 = v6[(char)v1] & 8192;\n if (!v10) break;\n if (v5) {\n ++v4;\n if (v9) goto LABEL_12;\n } else if (v9) {\n v5 = 1;\n v7 = v10 != 0;\n goto LABEL_13;\n }\n LABEL_5:\n v5 = 0;\n if ((unsigned char)v1 <= 63u) {\n if (_bittest64((const long long *)&v8, v1)) v7 = 1;\n }\n v1 = *v3++;\n if (!(uint8_t)v1) return v4;\n }\n if (!v9) {\n v7 = 0;\n goto LABEL_5;\n }\n LABEL_12:\n v5 = 1;\n v7 = v10 != 0;\n LABEL_13:\n v1 = *v3++;\n if (!(uint8_t)v1) return v4;\n }\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(unsigned char *a1) {\n unsigned long long v1;\n const unsigned short **v2;\n unsigned char *v3;\n unsigned int v4;\n int v5;\n const unsigned short *v6;\n bool v7;\n unsigned long long v8;\n bool v9;\n short v10;\n v1 = *a1;\n if ((uint8_t)v1) {\n v2 = __ctype_b_loc();\n v3 = a1 + 1;\n v4 = 0;\n v5 = 0;\n v6 = *v2;\n v7 = 1;\n v8 = 9223442414188888064LL;\n while (1) {\n while (1) {\n v9 = v7 && (uint8_t)v1 == 73;\n v10 = v6[(char)v1] & 8192;\n if (!v10) break;\n if (v5) {\n ++v4;\n if (v9) goto LABEL_12;\n } else if (v9) {\n v5 = 1;\n v7 = v10 != 0;\n goto LABEL_13;\n }\n LABEL_5:\n v5 = 0;\n if ((unsigned char)v1 <= 63u) {\n if (_bittest64((const long long *)&v8, v1)) v7 = 1;\n }\n v1 = *v3++;\n if (!(uint8_t)v1) return v4;\n }\n if (!v9) {\n v7 = 0;\n goto LABEL_5;\n }\n LABEL_12:\n v5 = 1;\n v7 = v10 != 0;\n LABEL_13:\n v1 = *v3++;\n if (!(uint8_t)v1) return v4;\n }\n }\n return 0LL;\n}" + }, + { + "index": "HumanEval-C-91", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int func0(const char *S) {\n int isstart = 1;\n int isi = 0;\n int sum = 0;\n for (int i = 0; S[i] != '\\0'; i++) {\n if (isspace(S[i]) && isi) {\n isi = 0;\n sum += 1;\n }\n if (S[i] == 'I' && isstart) {\n isi = 1;\n } else if (!isspace(S[i])) {\n isi = 0;\n }\n if (!isspace(S[i])) {\n isstart = 0;\n }\n if (S[i] == '.' || S[i] == '?' || S[i] == '!') {\n isstart = 1;\n }\n }\n return sum;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"Hello world\") == 0);\n assert(func0(\"Is the sky blue?\") == 0);\n assert(func0(\"I love It !\") == 1);\n assert(func0(\"bIt\") == 0);\n assert(func0(\"I feel good today. I will be productive. will kill It\") == 2);\n assert(func0(\"You and I are going for a walk\") == 0);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz loc_1370\nmov rbp, rdi\ncall ___ctype_b_loc\nlea rdi, [rbp+1]\nxor r11d, r11d\nxor esi, esi\nmov r8, [rax]\nmov ecx, 1\nmov r10, 8000400200000000h\nmov r9d, 1\njmp short loc_1310\nloc_12F0:\ntest dl, dl\njnz short loc_1333\nxor ecx, ecx\nloc_12F6:\nxor esi, esi\ncmp bl, 3Fh ; '?'\nja short loc_1305\nbt r10, rbx\ncmovb ecx, r9d\nloc_1305:\nmovzx ebx, byte ptr [rdi]\nadd rdi, 1\ntest bl, bl\njz short loc_134B\nloc_1310:\nmovsx rax, bl\ncmp bl, 49h ; 'I'\nmovzx eax, word ptr [r8+rax*2]\nsetz dl\nand edx, ecx\nand ax, 2000h\njz short loc_12F0\ntest esi, esi\njz short loc_1358\nadd r11d, 1\ntest dl, dl\njz short loc_12F6\nloc_1333:\nxor ecx, ecx\ntest ax, ax\nmov esi, 1\nsetnz cl\nloc_1340:\nmovzx ebx, byte ptr [rdi]\nadd rdi, 1\ntest bl, bl\njnz short loc_1310\nloc_134B:\nadd rsp, 8\nmov eax, r11d\npop rbx\npop rbp\nretn\nloc_1358:\ntest dl, dl\njz short loc_12F6\nxor ecx, ecx\ntest ax, ax\nmov esi, 1\nsetnz cl\njmp short loc_1340\nloc_1370:\nadd rsp, 8\nxor r11d, r11d\nmov eax, r11d\npop rbx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned __int8 *a1)\n{\n unsigned __int64 v1; // rbx\n const unsigned __int16 **v2; // rax\n unsigned __int8 *v3; // rdi\n unsigned int v4; // r11d\n int v5; // esi\n const unsigned __int16 *v6; // r8\n bool v7; // cl\n unsigned __int64 v8; // r10\n bool v9; // dl\n __int16 v10; // ax\n\n v1 = *a1;\n if ( (_BYTE)v1 )\n {\n v2 = __ctype_b_loc();\n v3 = a1 + 1;\n v4 = 0;\n v5 = 0;\n v6 = *v2;\n v7 = 1;\n v8 = 0x8000400200000000LL;\n while ( 1 )\n {\n while ( 1 )\n {\n v9 = v7 && (_BYTE)v1 == 73;\n v10 = v6[(char)v1] & 0x2000;\n if ( !v10 )\n break;\n if ( v5 )\n {\n ++v4;\n if ( v9 )\n goto LABEL_12;\n }\n else if ( v9 )\n {\n v5 = 1;\n v7 = v10 != 0;\n goto LABEL_13;\n }\nLABEL_5:\n v5 = 0;\n if ( (unsigned __int8)v1 <= 0x3Fu )\n {\n if ( _bittest64((const __int64 *)&v8, v1) )\n v7 = 1;\n }\n v1 = *v3++;\n if ( !(_BYTE)v1 )\n return v4;\n }\n if ( !v9 )\n {\n v7 = 0;\n goto LABEL_5;\n }\nLABEL_12:\n v5 = 1;\n v7 = v10 != 0;\nLABEL_13:\n v1 = *v3++;\n if ( !(_BYTE)v1 )\n return v4;\n }\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_12B0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz loc_1370\nmov rbp, rdi\ncall ___ctype_b_loc\nlea rdi, [rbp+1]\nxor r11d, r11d\nxor esi, esi\nmov r8, [rax]\nmov ecx, 1\nmov r10, 8000400200000000h\nmov r9d, 1\njmp short loc_1310\nloc_12F0:\ntest dl, dl\njnz short loc_1333\nxor ecx, ecx\nloc_12F6:\nxor esi, esi\ncmp bl, 3Fh ; '?'\nja short loc_1305\nbt r10, rbx\ncmovb ecx, r9d\nloc_1305:\nmovzx ebx, byte ptr [rdi]\nadd rdi, 1\ntest bl, bl\njz short loc_134B\nloc_1310:\nmovsx rax, bl\ncmp bl, 49h ; 'I'\nmovzx eax, word ptr [r8+rax*2]\nsetz dl\nand edx, ecx\nand ax, 2000h\njz short loc_12F0\ntest esi, esi\njz short loc_1358\nadd r11d, 1\ntest dl, dl\njz short loc_12F6\nloc_1333:\nxor ecx, ecx\ntest ax, ax\nmov esi, 1\nsetnz cl\nloc_1340:\nmovzx ebx, byte ptr [rdi]\nadd rdi, 1\ntest bl, bl\njnz short loc_1310\nloc_134B:\nadd rsp, 8\nmov eax, r11d\npop rbx\npop rbp\nretn\nloc_1358:\ntest dl, dl\njz short loc_12F6\nxor ecx, ecx\ntest ax, ax\nmov esi, 1\nsetnz cl\njmp short loc_1340\nloc_1370:\nadd rsp, 8\nxor r11d, r11d\nmov eax, r11d\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12B0(unsigned __int8 *a1)\n{\n unsigned __int64 v1; // rbx\n const unsigned __int16 **v2; // rax\n unsigned __int8 *v3; // rdi\n unsigned int v4; // r11d\n int v5; // esi\n const unsigned __int16 *v6; // r8\n bool v7; // cl\n unsigned __int64 v8; // r10\n bool v9; // dl\n __int16 v10; // ax\n\n v1 = *a1;\n if ( (_BYTE)v1 )\n {\n v2 = __ctype_b_loc();\n v3 = a1 + 1;\n v4 = 0;\n v5 = 0;\n v6 = *v2;\n v7 = 1;\n v8 = 0x8000400200000000LL;\n while ( 1 )\n {\n while ( 1 )\n {\n v9 = v7 && (_BYTE)v1 == 73;\n v10 = v6[(char)v1] & 0x2000;\n if ( !v10 )\n break;\n if ( v5 )\n {\n ++v4;\n if ( v9 )\n goto LABEL_12;\n }\n else if ( v9 )\n {\n v5 = 1;\n v7 = v10 != 0;\n goto LABEL_13;\n }\nLABEL_5:\n v5 = 0;\n if ( (unsigned __int8)v1 <= 0x3Fu )\n {\n if ( _bittest64((const __int64 *)&v8, v1) )\n v7 = 1;\n }\n v1 = *v3++;\n if ( !(_BYTE)v1 )\n return v4;\n }\n if ( !v9 )\n {\n v7 = 0;\n goto LABEL_5;\n }\nLABEL_12:\n v5 = 1;\n v7 = v10 != 0;\nLABEL_13:\n v1 = *v3++;\n if ( !(_BYTE)v1 )\n return v4;\n }\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12B0(unsigned char *a1) {\n unsigned long long v1;\n const unsigned short **v2;\n unsigned char *v3;\n unsigned int v4;\n int v5;\n const unsigned short *v6;\n bool v7;\n unsigned long long v8;\n bool v9;\n short v10;\n v1 = *a1;\n if ((uint8_t)v1) {\n v2 = __ctype_b_loc();\n v3 = a1 + 1;\n v4 = 0;\n v5 = 0;\n v6 = *v2;\n v7 = 1;\n v8 = 9223442414188888064LL;\n while (1) {\n while (1) {\n v9 = v7 && (uint8_t)v1 == 73;\n v10 = v6[(char)v1] & 8192;\n if (!v10) break;\n if (v5) {\n ++v4;\n if (v9) goto LABEL_12;\n } else if (v9) {\n v5 = 1;\n v7 = v10 != 0;\n goto LABEL_13;\n }\n LABEL_5:\n v5 = 0;\n if ((unsigned char)v1 <= 63u) {\n if (_bittest64((const long long *)&v8, v1)) v7 = 1;\n }\n v1 = *v3++;\n if (!(uint8_t)v1) return v4;\n }\n if (!v9) {\n v7 = 0;\n goto LABEL_5;\n }\n LABEL_12:\n v5 = 1;\n v7 = v10 != 0;\n LABEL_13:\n v1 = *v3++;\n if (!(uint8_t)v1) return v4;\n }\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(unsigned char *a1) {\n unsigned long long v1;\n const unsigned short **v2;\n unsigned char *v3;\n unsigned int v4;\n int v5;\n const unsigned short *v6;\n bool v7;\n unsigned long long v8;\n bool v9;\n short v10;\n v1 = *a1;\n if ((uint8_t)v1) {\n v2 = __ctype_b_loc();\n v3 = a1 + 1;\n v4 = 0;\n v5 = 0;\n v6 = *v2;\n v7 = 1;\n v8 = 9223442414188888064LL;\n while (1) {\n while (1) {\n v9 = v7 && (uint8_t)v1 == 73;\n v10 = v6[(char)v1] & 8192;\n if (!v10) break;\n if (v5) {\n ++v4;\n if (v9) goto LABEL_12;\n } else if (v9) {\n v5 = 1;\n v7 = v10 != 0;\n goto LABEL_13;\n }\n LABEL_5:\n v5 = 0;\n if ((unsigned char)v1 <= 63u) {\n if (_bittest64((const long long *)&v8, v1)) v7 = 1;\n }\n v1 = *v3++;\n if (!(uint8_t)v1) return v4;\n }\n if (!v9) {\n v7 = 0;\n goto LABEL_5;\n }\n LABEL_12:\n v5 = 1;\n v7 = v10 != 0;\n LABEL_13:\n v1 = *v3++;\n if (!(uint8_t)v1) return v4;\n }\n }\n return 0LL;\n}" + }, + { + "index": "HumanEval-C-92", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(float a, float b, float c) {\n if (roundf(a) != a) return 0;\n if (roundf(b) != b) return 0;\n if (roundf(c) != c) return 0;\n if ((a + b == c) || (a + c == b) || (b + c == a)) return 1;\n return 0;\n}", + "test": "#include \n\nint main() {\n assert(func0(2, 3, 1) == 1);\n assert(func0(2.5, 2, 3) == 0);\n assert(func0(1.5, 5, 3.5) == 0);\n assert(func0(2, 6, 2) == 0);\n assert(func0(4, 2, 2) == 1);\n assert(func0(2.2, 2.2, 2.2) == 0);\n assert(func0(-4, 6, 2) == 1);\n assert(func0(2, 1, 1) == 1);\n assert(func0(3, 4, 7) == 1);\n assert(func0(3.01, 4, 7) == 0);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmovss [rbp+x], xmm0\nmovss [rbp+var_8], xmm1\nmovss [rbp+var_C], xmm2\nmov eax, [rbp+x]\nmovd xmm0, eax; x\ncall _roundf\nmovd eax, xmm0\nmovd xmm3, eax\nucomiss xmm3, [rbp+x]\njp short loc_11A8\nmovd xmm4, eax\nucomiss xmm4, [rbp+x]\njz short loc_11B2\nloc_11A8:\nmov eax, 0\njmp locret_1256\nloc_11B2:\nmov eax, [rbp+var_8]\nmovd xmm0, eax; x\ncall _roundf\nmovd eax, xmm0\nmovd xmm5, eax\nucomiss xmm5, [rbp+var_8]\njp short loc_11D6\nmovd xmm6, eax\nucomiss xmm6, [rbp+var_8]\njz short loc_11DD\nloc_11D6:\nmov eax, 0\njmp short locret_1256\nloc_11DD:\nmov eax, [rbp+var_C]\nmovd xmm0, eax; x\ncall _roundf\nmovd eax, xmm0\nmovd xmm7, eax\nucomiss xmm7, [rbp+var_C]\njp short loc_1201\nmovd xmm1, eax\nucomiss xmm1, [rbp+var_C]\njz short loc_1208\nloc_1201:\nmov eax, 0\njmp short locret_1256\nloc_1208:\nmovss xmm0, [rbp+x]\naddss xmm0, [rbp+var_8]\nucomiss xmm0, [rbp+var_C]\njp short loc_121E\nucomiss xmm0, [rbp+var_C]\njz short loc_124A\nloc_121E:\nmovss xmm0, [rbp+x]\naddss xmm0, [rbp+var_C]\nucomiss xmm0, [rbp+var_8]\njp short loc_1234\nucomiss xmm0, [rbp+var_8]\njz short loc_124A\nloc_1234:\nmovss xmm0, [rbp+var_8]\naddss xmm0, [rbp+var_C]\nucomiss xmm0, [rbp+x]\njp short loc_1251\nucomiss xmm0, [rbp+x]\njnz short loc_1251\nloc_124A:\nmov eax, 1\njmp short locret_1256\nloc_1251:\nmov eax, 0\nlocret_1256:\nleave\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(float a1, float a2, float a3)\n{\n __m128i v3; // xmm0\n __m128i v5; // xmm0\n __m128i v6; // xmm0\n\n v3 = _mm_cvtsi32_si128(LODWORD(a1));\n *(float *)v3.m128i_i32 = roundf(*(float *)v3.m128i_i32);\n if ( COERCE_FLOAT(_mm_cvtsi128_si32(v3)) != a1 )\n return 0LL;\n v5 = _mm_cvtsi32_si128(LODWORD(a2));\n *(float *)v5.m128i_i32 = roundf(*(float *)v5.m128i_i32);\n if ( COERCE_FLOAT(_mm_cvtsi128_si32(v5)) != a2 )\n return 0LL;\n v6 = _mm_cvtsi32_si128(LODWORD(a3));\n *(float *)v6.m128i_i32 = roundf(*(float *)v6.m128i_i32);\n if ( COERCE_FLOAT(_mm_cvtsi128_si32(v6)) != a3 )\n return 0LL;\n return (float)(a1 + a2) == a3 || (float)(a1 + a3) == a2 || (float)(a2 + a3) == a1;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmovss [rbp+x], xmm0\nmovss [rbp+var_8], xmm1\nmovss [rbp+var_C], xmm2\nmov eax, [rbp+x]\nmovd xmm0, eax; x\ncall _roundf\nmovd eax, xmm0\nmovd xmm3, eax\nucomiss xmm3, [rbp+x]\njp short loc_11A8\nmovd xmm4, eax\nucomiss xmm4, [rbp+x]\njz short loc_11B2\nloc_11A8:\nmov eax, 0\njmp locret_1256\nloc_11B2:\nmov eax, [rbp+var_8]\nmovd xmm0, eax; x\ncall _roundf\nmovd eax, xmm0\nmovd xmm5, eax\nucomiss xmm5, [rbp+var_8]\njp short loc_11D6\nmovd xmm6, eax\nucomiss xmm6, [rbp+var_8]\njz short loc_11DD\nloc_11D6:\nmov eax, 0\njmp short locret_1256\nloc_11DD:\nmov eax, [rbp+var_C]\nmovd xmm0, eax; x\ncall _roundf\nmovd eax, xmm0\nmovd xmm7, eax\nucomiss xmm7, [rbp+var_C]\njp short loc_1201\nmovd xmm1, eax\nucomiss xmm1, [rbp+var_C]\njz short loc_1208\nloc_1201:\nmov eax, 0\njmp short locret_1256\nloc_1208:\nmovss xmm0, [rbp+x]\naddss xmm0, [rbp+var_8]\nucomiss xmm0, [rbp+var_C]\njp short loc_121E\nucomiss xmm0, [rbp+var_C]\njz short loc_124A\nloc_121E:\nmovss xmm0, [rbp+x]\naddss xmm0, [rbp+var_C]\nucomiss xmm0, [rbp+var_8]\njp short loc_1234\nucomiss xmm0, [rbp+var_8]\njz short loc_124A\nloc_1234:\nmovss xmm0, [rbp+var_8]\naddss xmm0, [rbp+var_C]\nucomiss xmm0, [rbp+x]\njp short loc_1251\nucomiss xmm0, [rbp+x]\njnz short loc_1251\nloc_124A:\nmov eax, 1\njmp short locret_1256\nloc_1251:\nmov eax, 0\nlocret_1256:\nleave\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1169(float a1, float a2, float a3)\n{\n __m128i v3; // xmm0\n __m128i v5; // xmm0\n __m128i v6; // xmm0\n\n v3 = _mm_cvtsi32_si128(LODWORD(a1));\n *(float *)v3.m128i_i32 = roundf(*(float *)v3.m128i_i32);\n if ( COERCE_FLOAT(_mm_cvtsi128_si32(v3)) != a1 )\n return 0LL;\n v5 = _mm_cvtsi32_si128(LODWORD(a2));\n *(float *)v5.m128i_i32 = roundf(*(float *)v5.m128i_i32);\n if ( COERCE_FLOAT(_mm_cvtsi128_si32(v5)) != a2 )\n return 0LL;\n v6 = _mm_cvtsi32_si128(LODWORD(a3));\n *(float *)v6.m128i_i32 = roundf(*(float *)v6.m128i_i32);\n if ( COERCE_FLOAT(_mm_cvtsi128_si32(v6)) != a3 )\n return 0LL;\n return (float)(a1 + a2) == a3 || (float)(a1 + a3) == a2 || (float)(a2 + a3) == a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1169(float a1, float a2, float a3) {\n __m128i v3;\n __m128i v5;\n __m128i v6;\n v3 = _mm_cvtsi32_si128(LODWORD(a1));\n *(float *)v3.m128i_i32 = roundf(*(float *)v3.m128i_i32);\n if (COERCE_FLOAT(_mm_cvtsi128_si32(v3)) != a1) return 0LL;\n v5 = _mm_cvtsi32_si128(LODWORD(a2));\n *(float *)v5.m128i_i32 = roundf(*(float *)v5.m128i_i32);\n if (COERCE_FLOAT(_mm_cvtsi128_si32(v5)) != a2) return 0LL;\n v6 = _mm_cvtsi32_si128(LODWORD(a3));\n *(float *)v6.m128i_i32 = roundf(*(float *)v6.m128i_i32);\n if (COERCE_FLOAT(_mm_cvtsi128_si32(v6)) != a3) return 0LL;\n return (float)(a1 + a2) == a3 || (float)(a1 + a3) == a2 ||\n (float)(a2 + a3) == a1;\n}", + "ida_pseudo_norm": "uint8_t func0(float a1, float a2, float a3) {\n __m128i v3;\n __m128i v5;\n __m128i v6;\n v3 = _mm_cvtsi32_si128(LODWORD(a1));\n *(float *)v3.m128i_i32 = roundf(*(float *)v3.m128i_i32);\n if (COERCE_FLOAT(_mm_cvtsi128_si32(v3)) != a1) return 0LL;\n v5 = _mm_cvtsi32_si128(LODWORD(a2));\n *(float *)v5.m128i_i32 = roundf(*(float *)v5.m128i_i32);\n if (COERCE_FLOAT(_mm_cvtsi128_si32(v5)) != a2) return 0LL;\n v6 = _mm_cvtsi32_si128(LODWORD(a3));\n *(float *)v6.m128i_i32 = roundf(*(float *)v6.m128i_i32);\n if (COERCE_FLOAT(_mm_cvtsi128_si32(v6)) != a3) return 0LL;\n return (float)(a1 + a2) == a3 || (float)(a1 + a3) == a2 ||\n (float)(a2 + a3) == a1;\n}" + }, + { + "index": "HumanEval-C-92", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(float a, float b, float c) {\n if (roundf(a) != a) return 0;\n if (roundf(b) != b) return 0;\n if (roundf(c) != c) return 0;\n if ((a + b == c) || (a + c == b) || (b + c == a)) return 1;\n return 0;\n}", + "test": "#include \n\nint main() {\n assert(func0(2, 3, 1) == 1);\n assert(func0(2.5, 2, 3) == 0);\n assert(func0(1.5, 5, 3.5) == 0);\n assert(func0(2, 6, 2) == 0);\n assert(func0(4, 2, 2) == 1);\n assert(func0(2.2, 2.2, 2.2) == 0);\n assert(func0(-4, 6, 2) == 1);\n assert(func0(2, 1, 1) == 1);\n assert(func0(3, 4, 7) == 1);\n assert(func0(3.01, 4, 7) == 0);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nsub rsp, 18h\nmovss [rsp+18h+x], xmm1\nmovss [rsp+18h+var_C], xmm2\nmovss [rsp+18h+var_14], xmm0\ncall _roundf\nmovss xmm3, [rsp+18h+var_14]\nucomiss xmm0, xmm3\njp loc_1224\njnz loc_1224\nmovss xmm0, [rsp+18h+x]; x\ncall _roundf\nmovss xmm4, [rsp+18h+x]\nucomiss xmm0, xmm4\njp short loc_122E\njnz short loc_122E\nmovss xmm0, [rsp+18h+var_C]; x\ncall _roundf\nmovss xmm5, [rsp+18h+var_C]\nucomiss xmm0, xmm5\njp short loc_1235\njnz short loc_1235\nmovss xmm0, [rsp+18h+var_14]\naddss xmm0, [rsp+18h+x]\nucomiss xmm0, xmm5\njp short loc_11E5\nmov eax, 1\njz short loc_1229\nloc_11E5:\nmovss xmm0, [rsp+18h+var_14]\naddss xmm0, [rsp+18h+var_C]\nmovss xmm6, [rsp+18h+x]\nucomiss xmm0, xmm6\njp short loc_1203\nmov eax, 1\njz short loc_1229\nloc_1203:\nmovss xmm0, [rsp+18h+x]\naddss xmm0, [rsp+18h+var_C]\nucomiss xmm0, [rsp+18h+var_14]\nsetnp al\nmovzx eax, al\nmov edx, 0\ncmovnz eax, edx\njmp short loc_1229\nloc_1224:\nmov eax, 0\nloc_1229:\nadd rsp, 18h\nretn\nloc_122E:\nmov eax, 0\njmp short loc_1229\nloc_1235:\nmov eax, 0\njmp short loc_1229", + "ida_pseudo": "_BOOL8 __fastcall func0(float a1, float a2, float a3)\n{\n _BOOL8 result; // rax\n\n if ( roundf(a1) != a1 )\n return 0LL;\n if ( roundf(a2) != a2 )\n return 0LL;\n if ( roundf(a3) != a3 )\n return 0LL;\n result = 1LL;\n if ( (float)(a1 + a2) != a3 )\n {\n result = 1LL;\n if ( (float)(a1 + a3) != a2 )\n return (float)(a2 + a3) == a1;\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nsub rsp, 18h\nmovss [rsp+18h+x], xmm1\nmovss [rsp+18h+var_C], xmm2\nmovss [rsp+18h+var_14], xmm0\ncall _roundf\nmovss xmm3, [rsp+18h+var_14]\nucomiss xmm0, xmm3\njp loc_1224\njnz loc_1224\nmovss xmm0, [rsp+18h+x]; x\ncall _roundf\nmovss xmm4, [rsp+18h+x]\nucomiss xmm0, xmm4\njp short loc_122E\njnz short loc_122E\nmovss xmm0, [rsp+18h+var_C]; x\ncall _roundf\nmovss xmm5, [rsp+18h+var_C]\nucomiss xmm0, xmm5\njp short loc_1235\njnz short loc_1235\nmovss xmm0, [rsp+18h+var_14]\naddss xmm0, [rsp+18h+x]\nucomiss xmm0, xmm5\njp short loc_11E5\nmov eax, 1\njz short loc_1229\nloc_11E5:\nmovss xmm0, [rsp+18h+var_14]\naddss xmm0, [rsp+18h+var_C]\nmovss xmm6, [rsp+18h+x]\nucomiss xmm0, xmm6\njp short loc_1203\nmov eax, 1\njz short loc_1229\nloc_1203:\nmovss xmm0, [rsp+18h+x]\naddss xmm0, [rsp+18h+var_C]\nucomiss xmm0, [rsp+18h+var_14]\nsetnp al\nmovzx eax, al\nmov edx, 0\ncmovnz eax, edx\njmp short loc_1229\nloc_1224:\nmov eax, 0\nloc_1229:\nadd rsp, 18h\nretn\nloc_122E:\nmov eax, 0\njmp short loc_1229\nloc_1235:\nmov eax, 0\njmp short loc_1229", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1169(float a1, float a2, float a3)\n{\n _BOOL8 result; // rax\n\n if ( roundf(a1) != a1 )\n return 0LL;\n if ( roundf(a2) != a2 )\n return 0LL;\n if ( roundf(a3) != a3 )\n return 0LL;\n result = 1LL;\n if ( (float)(a1 + a2) != a3 )\n {\n result = 1LL;\n if ( (float)(a1 + a3) != a2 )\n return (float)(a2 + a3) == a1;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1169(float a1, float a2, float a3) {\n uint8_t result;\n if (roundf(a1) != a1) return 0LL;\n if (roundf(a2) != a2) return 0LL;\n if (roundf(a3) != a3) return 0LL;\n result = 1LL;\n if ((float)(a1 + a2) != a3) {\n result = 1LL;\n if ((float)(a1 + a3) != a2) return (float)(a2 + a3) == a1;\n }\n return result;\n}", + "ida_pseudo_norm": "uint8_t func0(float a1, float a2, float a3) {\n uint8_t result;\n if (roundf(a1) != a1) return 0LL;\n if (roundf(a2) != a2) return 0LL;\n if (roundf(a3) != a3) return 0LL;\n result = 1LL;\n if ((float)(a1 + a2) != a3) {\n result = 1LL;\n if ((float)(a1 + a3) != a2) return (float)(a2 + a3) == a1;\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-92", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(float a, float b, float c) {\n if (roundf(a) != a) return 0;\n if (roundf(b) != b) return 0;\n if (roundf(c) != c) return 0;\n if ((a + b == c) || (a + c == b) || (b + c == a)) return 1;\n return 0;\n}", + "test": "#include \n\nint main() {\n assert(func0(2, 3, 1) == 1);\n assert(func0(2.5, 2, 3) == 0);\n assert(func0(1.5, 5, 3.5) == 0);\n assert(func0(2, 6, 2) == 0);\n assert(func0(4, 2, 2) == 1);\n assert(func0(2.2, 2.2, 2.2) == 0);\n assert(func0(-4, 6, 2) == 1);\n assert(func0(2, 1, 1) == 1);\n assert(func0(3, 4, 7) == 1);\n assert(func0(3.01, 4, 7) == 0);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nsub rsp, 18h\nmovss [rsp+18h+x], xmm1\nmovss [rsp+18h+var_C], xmm2\nmovss [rsp+18h+var_10], xmm0\ncall _roundf\nucomiss xmm0, [rsp+18h+var_10]\njp loc_14C8\njnz loc_14C8\nmovss xmm0, [rsp+18h+x]; x\ncall _roundf\nucomiss xmm0, [rsp+18h+x]\njp short loc_14C8\njnz short loc_14C8\nmovss xmm0, [rsp+18h+var_C]; x\ncall _roundf\nmovss xmm5, [rsp+18h+var_C]\nucomiss xmm0, xmm5\njp short loc_14C8\njnz short loc_14C8\nmovss xmm0, [rsp+18h+var_10]\naddss xmm0, [rsp+18h+x]\nucomiss xmm5, xmm0\njp short loc_1484\nmov eax, 1\njz short loc_14CA\nloc_1484:\nmovss xmm0, [rsp+18h+var_10]\naddss xmm0, [rsp+18h+var_C]\nmovss xmm7, [rsp+18h+x]\nucomiss xmm7, xmm0\njp short loc_14A2\nmov eax, 1\njz short loc_14CA\nloc_14A2:\nmovss xmm0, [rsp+18h+x]\nxor eax, eax\nmov edx, 0\naddss xmm0, [rsp+18h+var_C]\nucomiss xmm0, [rsp+18h+var_10]\nsetnp al\ncmovnz eax, edx\nadd rsp, 18h\nretn\nloc_14C8:\nxor eax, eax\nloc_14CA:\nadd rsp, 18h\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(float a1, float a2, float a3)\n{\n _BOOL8 result; // rax\n\n if ( roundf(a1) != a1 || roundf(a2) != a2 || roundf(a3) != a3 )\n return 0LL;\n result = 1LL;\n if ( a3 != (float)(a1 + a2) )\n {\n result = 1LL;\n if ( a2 != (float)(a1 + a3) )\n return (float)(a2 + a3) == a1;\n }\n return result;\n}", + "ida_strip_asm": "sub_1410:\nendbr64\nsub rsp, 18h\nmovss [rsp+18h+x], xmm1\nmovss [rsp+18h+var_C], xmm2\nmovss [rsp+18h+var_10], xmm0\ncall _roundf\nucomiss xmm0, [rsp+18h+var_10]\njp loc_14C8\njnz loc_14C8\nmovss xmm0, [rsp+18h+x]; x\ncall _roundf\nucomiss xmm0, [rsp+18h+x]\njp short loc_14C8\njnz short loc_14C8\nmovss xmm0, [rsp+18h+var_C]; x\ncall _roundf\nmovss xmm5, [rsp+18h+var_C]\nucomiss xmm0, xmm5\njp short loc_14C8\njnz short loc_14C8\nmovss xmm0, [rsp+18h+var_10]\naddss xmm0, [rsp+18h+x]\nucomiss xmm5, xmm0\njp short loc_1484\nmov eax, 1\njz short loc_14CA\nloc_1484:\nmovss xmm0, [rsp+18h+var_10]\naddss xmm0, [rsp+18h+var_C]\nmovss xmm7, [rsp+18h+x]\nucomiss xmm7, xmm0\njp short loc_14A2\nmov eax, 1\njz short loc_14CA\nloc_14A2:\nmovss xmm0, [rsp+18h+x]\nxor eax, eax\nmov edx, 0\naddss xmm0, [rsp+18h+var_C]\nucomiss xmm0, [rsp+18h+var_10]\nsetnp al\ncmovnz eax, edx\nadd rsp, 18h\nretn\nloc_14C8:\nxor eax, eax\nloc_14CA:\nadd rsp, 18h\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1410(float a1, float a2, float a3)\n{\n _BOOL8 result; // rax\n\n if ( roundf(a1) != a1 || roundf(a2) != a2 || roundf(a3) != a3 )\n return 0LL;\n result = 1LL;\n if ( a3 != (float)(a1 + a2) )\n {\n result = 1LL;\n if ( a2 != (float)(a1 + a3) )\n return (float)(a2 + a3) == a1;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1410(float a1, float a2, float a3) {\n uint8_t result;\n if (roundf(a1) != a1 || roundf(a2) != a2 || roundf(a3) != a3) return 0LL;\n result = 1LL;\n if (a3 != (float)(a1 + a2)) {\n result = 1LL;\n if (a2 != (float)(a1 + a3)) return (float)(a2 + a3) == a1;\n }\n return result;\n}", + "ida_pseudo_norm": "uint8_t func0(float a1, float a2, float a3) {\n uint8_t result;\n if (roundf(a1) != a1 || roundf(a2) != a2 || roundf(a3) != a3) return 0LL;\n result = 1LL;\n if (a3 != (float)(a1 + a2)) {\n result = 1LL;\n if (a2 != (float)(a1 + a3)) return (float)(a2 + a3) == a1;\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-92", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(float a, float b, float c) {\n if (roundf(a) != a) return 0;\n if (roundf(b) != b) return 0;\n if (roundf(c) != c) return 0;\n if ((a + b == c) || (a + c == b) || (b + c == a)) return 1;\n return 0;\n}", + "test": "#include \n\nint main() {\n assert(func0(2, 3, 1) == 1);\n assert(func0(2.5, 2, 3) == 0);\n assert(func0(1.5, 5, 3.5) == 0);\n assert(func0(2, 6, 2) == 0);\n assert(func0(4, 2, 2) == 1);\n assert(func0(2.2, 2.2, 2.2) == 0);\n assert(func0(-4, 6, 2) == 1);\n assert(func0(2, 1, 1) == 1);\n assert(func0(3, 4, 7) == 1);\n assert(func0(3.01, 4, 7) == 0);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nsub rsp, 18h\nmovss [rsp+18h+x], xmm1\nmovss [rsp+18h+var_C], xmm2\nmovss [rsp+18h+var_10], xmm0\ncall _roundf\nucomiss xmm0, [rsp+18h+var_10]\njp loc_14C8\njnz loc_14C8\nmovss xmm0, [rsp+18h+x]; x\ncall _roundf\nucomiss xmm0, [rsp+18h+x]\njp short loc_14C8\njnz short loc_14C8\nmovss xmm0, [rsp+18h+var_C]; x\ncall _roundf\nmovss xmm5, [rsp+18h+var_C]\nucomiss xmm0, xmm5\njp short loc_14C8\njnz short loc_14C8\nmovss xmm0, [rsp+18h+var_10]\naddss xmm0, [rsp+18h+x]\nucomiss xmm5, xmm0\njp short loc_1484\nmov eax, 1\njz short loc_14CA\nloc_1484:\nmovss xmm0, [rsp+18h+var_10]\naddss xmm0, [rsp+18h+var_C]\nmovss xmm7, [rsp+18h+x]\nucomiss xmm7, xmm0\njp short loc_14A2\nmov eax, 1\njz short loc_14CA\nloc_14A2:\nmovss xmm0, [rsp+18h+x]\nxor eax, eax\nmov edx, 0\naddss xmm0, [rsp+18h+var_C]\nucomiss xmm0, [rsp+18h+var_10]\nsetnp al\ncmovnz eax, edx\nadd rsp, 18h\nretn\nloc_14C8:\nxor eax, eax\nloc_14CA:\nadd rsp, 18h\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(float a1, float a2, float a3)\n{\n _BOOL8 result; // rax\n\n if ( roundf(a1) != a1 || roundf(a2) != a2 || roundf(a3) != a3 )\n return 0LL;\n result = 1LL;\n if ( a3 != (float)(a1 + a2) )\n {\n result = 1LL;\n if ( a2 != (float)(a1 + a3) )\n return (float)(a2 + a3) == a1;\n }\n return result;\n}", + "ida_strip_asm": "sub_1410:\nendbr64\nsub rsp, 18h\nmovss [rsp+18h+x], xmm1\nmovss [rsp+18h+var_C], xmm2\nmovss [rsp+18h+var_10], xmm0\ncall _roundf\nucomiss xmm0, [rsp+18h+var_10]\njp loc_14C8\njnz loc_14C8\nmovss xmm0, [rsp+18h+x]; x\ncall _roundf\nucomiss xmm0, [rsp+18h+x]\njp short loc_14C8\njnz short loc_14C8\nmovss xmm0, [rsp+18h+var_C]; x\ncall _roundf\nmovss xmm5, [rsp+18h+var_C]\nucomiss xmm0, xmm5\njp short loc_14C8\njnz short loc_14C8\nmovss xmm0, [rsp+18h+var_10]\naddss xmm0, [rsp+18h+x]\nucomiss xmm5, xmm0\njp short loc_1484\nmov eax, 1\njz short loc_14CA\nloc_1484:\nmovss xmm0, [rsp+18h+var_10]\naddss xmm0, [rsp+18h+var_C]\nmovss xmm7, [rsp+18h+x]\nucomiss xmm7, xmm0\njp short loc_14A2\nmov eax, 1\njz short loc_14CA\nloc_14A2:\nmovss xmm0, [rsp+18h+x]\nxor eax, eax\nmov edx, 0\naddss xmm0, [rsp+18h+var_C]\nucomiss xmm0, [rsp+18h+var_10]\nsetnp al\ncmovnz eax, edx\nadd rsp, 18h\nretn\nloc_14C8:\nxor eax, eax\nloc_14CA:\nadd rsp, 18h\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1410(float a1, float a2, float a3)\n{\n _BOOL8 result; // rax\n\n if ( roundf(a1) != a1 || roundf(a2) != a2 || roundf(a3) != a3 )\n return 0LL;\n result = 1LL;\n if ( a3 != (float)(a1 + a2) )\n {\n result = 1LL;\n if ( a2 != (float)(a1 + a3) )\n return (float)(a2 + a3) == a1;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1410(float a1, float a2, float a3) {\n uint8_t result;\n if (roundf(a1) != a1 || roundf(a2) != a2 || roundf(a3) != a3) return 0LL;\n result = 1LL;\n if (a3 != (float)(a1 + a2)) {\n result = 1LL;\n if (a2 != (float)(a1 + a3)) return (float)(a2 + a3) == a1;\n }\n return result;\n}", + "ida_pseudo_norm": "uint8_t func0(float a1, float a2, float a3) {\n uint8_t result;\n if (roundf(a1) != a1 || roundf(a2) != a2 || roundf(a3) != a3) return 0LL;\n result = 1LL;\n if (a3 != (float)(a1 + a2)) {\n result = 1LL;\n if (a2 != (float)(a1 + a3)) return (float)(a2 + a3) == a1;\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-93", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "void func0(const char* message, char* out) {\n const char* vowels = \"aeiouAEIOU\";\n int i, j;\n for (i = 0; message[i] != '\\0'; ++i) {\n char w = message[i];\n if (islower(w)) {\n w = toupper(w);\n } else if (isupper(w)) {\n w = tolower(w);\n }\n for (j = 0; vowels[j] != '\\0'; ++j) {\n if (w == vowels[j]) {\n if (j < 10) {\n w = w + 2;\n }\n break;\n }\n }\n out[i] = w;\n }\n out[i] = '\\0';\n}", + "test": "#include \n#include \n\nint main() {\n char output[100];\n\n func0(\"TEST\", output);\n assert(strcmp(output, \"tgst\") == 0);\n\n func0(\"Mudasir\", output);\n assert(strcmp(output, \"mWDCSKR\") == 0);\n\n func0(\"YES\", output);\n assert(strcmp(output, \"ygs\") == 0);\n\n func0(\"This is a message\", output);\n assert(strcmp(output, \"tHKS KS C MGSSCGG\") == 0);\n\n func0(\"I DoNt KnOw WhAt tO WrItE\", output);\n assert(strcmp(output, \"k dQnT kNqW wHcT Tq wRkTg\") == 0);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_30], rsi\nlea rax, aAeiouaeiou; \"aeiouAEIOU\"\nmov [rbp+var_8], rax\nmov [rbp+var_10], 0\njmp loc_12EB\nloc_1214:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_11], al\ncall ___ctype_b_loc\nmov rax, [rax]\nmovsx rdx, [rbp+var_11]\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 200h\ntest eax, eax\njz short loc_1259\nmovsx eax, [rbp+var_11]\nmov edi, eax; c\ncall _toupper\nmov [rbp+var_11], al\njmp short loc_1289\nloc_1259:\ncall ___ctype_b_loc\nmov rax, [rax]\nmovsx rdx, [rbp+var_11]\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 100h\ntest eax, eax\njz short loc_1289\nmovsx eax, [rbp+var_11]\nmov edi, eax; c\ncall _tolower\nmov [rbp+var_11], al\nloc_1289:\nmov [rbp+var_C], 0\njmp short loc_12BD\nloc_1292:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp [rbp+var_11], al\njnz short loc_12B9\ncmp [rbp+var_C], 9\njg short loc_12D3\nmovzx eax, [rbp+var_11]\nadd eax, 2\nmov [rbp+var_11], al\njmp short loc_12D3\nloc_12B9:\nadd [rbp+var_C], 1\nloc_12BD:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1292\njmp short loc_12D4\nloc_12D3:\nnop\nloc_12D4:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rdx, rax\nmovzx eax, [rbp+var_11]\nmov [rdx], al\nadd [rbp+var_10], 1\nloc_12EB:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_1214\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov byte ptr [rax], 0\nnop\nleave\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(__int64 a1, __int64 a2)\n{\n _BYTE *result; // rax\n char v3; // [rsp+1Fh] [rbp-11h]\n int i; // [rsp+20h] [rbp-10h]\n int j; // [rsp+24h] [rbp-Ch]\n\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n {\n v3 = *(_BYTE *)(i + a1);\n if ( ((*__ctype_b_loc())[v3] & 0x200) != 0 )\n {\n v3 = toupper(v3);\n }\n else if ( ((*__ctype_b_loc())[v3] & 0x100) != 0 )\n {\n v3 = tolower(v3);\n }\n for ( j = 0; aAeiouaeiou[j]; ++j )\n {\n if ( v3 == aAeiouaeiou[j] )\n {\n if ( j <= 9 )\n v3 += 2;\n break;\n }\n }\n *(_BYTE *)(a2 + i) = v3;\n }\n result = (_BYTE *)(i + a2);\n *result = 0;\n return result;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_30], rsi\nlea rax, aAeiouaeiou; \"aeiouAEIOU\"\nmov [rbp+var_8], rax\nmov [rbp+var_10], 0\njmp loc_12EB\nloc_1214:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_11], al\ncall ___ctype_b_loc\nmov rax, [rax]\nmovsx rdx, [rbp+var_11]\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 200h\ntest eax, eax\njz short loc_1259\nmovsx eax, [rbp+var_11]\nmov edi, eax; c\ncall _toupper\nmov [rbp+var_11], al\njmp short loc_1289\nloc_1259:\ncall ___ctype_b_loc\nmov rax, [rax]\nmovsx rdx, [rbp+var_11]\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 100h\ntest eax, eax\njz short loc_1289\nmovsx eax, [rbp+var_11]\nmov edi, eax; c\ncall _tolower\nmov [rbp+var_11], al\nloc_1289:\nmov [rbp+var_C], 0\njmp short loc_12BD\nloc_1292:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp [rbp+var_11], al\njnz short loc_12B9\ncmp [rbp+var_C], 9\njg short loc_12D3\nmovzx eax, [rbp+var_11]\nadd eax, 2\nmov [rbp+var_11], al\njmp short loc_12D3\nloc_12B9:\nadd [rbp+var_C], 1\nloc_12BD:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1292\njmp short loc_12D4\nloc_12D3:\nnop\nloc_12D4:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rdx, rax\nmovzx eax, [rbp+var_11]\nmov [rdx], al\nadd [rbp+var_10], 1\nloc_12EB:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_1214\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov byte ptr [rax], 0\nnop\nleave\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_11E9(__int64 a1, __int64 a2)\n{\n _BYTE *result; // rax\n char v3; // [rsp+1Fh] [rbp-11h]\n int i; // [rsp+20h] [rbp-10h]\n int j; // [rsp+24h] [rbp-Ch]\n\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n {\n v3 = *(_BYTE *)(i + a1);\n if ( ((*__ctype_b_loc())[v3] & 0x200) != 0 )\n {\n v3 = toupper(v3);\n }\n else if ( ((*__ctype_b_loc())[v3] & 0x100) != 0 )\n {\n v3 = tolower(v3);\n }\n for ( j = 0; aAeiouaeiou[j]; ++j )\n {\n if ( v3 == aAeiouaeiou[j] )\n {\n if ( j <= 9 )\n v3 += 2;\n break;\n }\n }\n *(_BYTE *)(a2 + i) = v3;\n }\n result = (_BYTE *)(i + a2);\n *result = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_11E9(long long a1, long long a2) {\n uint8_t *result;\n char v3;\n int i;\n int j;\n for (i = 0; *(uint8_t *)(i + a1); ++i) {\n v3 = *(uint8_t *)(i + a1);\n if (((*__ctype_b_loc())[v3] & 512) != 0) {\n v3 = toupper(v3);\n } else if (((*__ctype_b_loc())[v3] & 256) != 0) {\n v3 = tolower(v3);\n }\n for (j = 0; aAeiouaeiou[j]; ++j) {\n if (v3 == aAeiouaeiou[j]) {\n if (j <= 9) v3 += 2;\n break;\n }\n }\n *(uint8_t *)(a2 + i) = v3;\n }\n result = (uint8_t *)(i + a2);\n *result = 0;\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(long long a1, long long a2) {\n uint8_t *result;\n char v3;\n int i;\n int j;\n for (i = 0; *(uint8_t *)(i + a1); ++i) {\n v3 = *(uint8_t *)(i + a1);\n if (((*__ctype_b_loc())[v3] & 512) != 0) {\n v3 = toupper(v3);\n } else if (((*__ctype_b_loc())[v3] & 256) != 0) {\n v3 = tolower(v3);\n }\n for (j = 0; aAeiouaeiou[j]; ++j) {\n if (v3 == aAeiouaeiou[j]) {\n if (j <= 9) v3 += 2;\n break;\n }\n }\n *(uint8_t *)(a2 + i) = v3;\n }\n result = (uint8_t *)(i + a2);\n *result = 0;\n return result;\n}" + }, + { + "index": "HumanEval-C-93", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "void func0(const char* message, char* out) {\n const char* vowels = \"aeiouAEIOU\";\n int i, j;\n for (i = 0; message[i] != '\\0'; ++i) {\n char w = message[i];\n if (islower(w)) {\n w = toupper(w);\n } else if (isupper(w)) {\n w = tolower(w);\n }\n for (j = 0; vowels[j] != '\\0'; ++j) {\n if (w == vowels[j]) {\n if (j < 10) {\n w = w + 2;\n }\n break;\n }\n }\n out[i] = w;\n }\n out[i] = '\\0';\n}", + "test": "#include \n#include \n\nint main() {\n char output[100];\n\n func0(\"TEST\", output);\n assert(strcmp(output, \"tgst\") == 0);\n\n func0(\"Mudasir\", output);\n assert(strcmp(output, \"mWDCSKR\") == 0);\n\n func0(\"YES\", output);\n assert(strcmp(output, \"ygs\") == 0);\n\n func0(\"This is a message\", output);\n assert(strcmp(output, \"tHKS KS C MGSSCGG\") == 0);\n\n func0(\"I DoNt KnOw WhAt tO WrItE\", output);\n assert(strcmp(output, \"k dQnT kNqW wHcT Tq wRkTg\") == 0);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rsi\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz loc_1293\nmov r14, rdi\ncall ___ctype_b_loc\nmov r15, rax\nmov r12d, 0\nlea rbp, aAeiouaeiou; \"aeiouAEIOU\"\njmp short loc_1258\nloc_1225:\ntest ah, 1\njz short loc_1276\ncall ___ctype_tolower_loc\nmov rax, [rax]\nmovzx ebx, byte ptr [rax+r13*4]\njmp short loc_1276\nloc_1239:\nlea edx, [rbx+2]\ncmp eax, 0Ah\ncmovl ebx, edx\nloc_1242:\nmov rax, [rsp+48h+var_40]\nmov [rax+r12], bl\nadd r12, 1\nmovzx ebx, byte ptr [r14+r12]\ntest bl, bl\njz short loc_1299\nloc_1258:\nmovsx r13, bl\nmov rax, [r15]\nmovzx eax, word ptr [rax+r13*2]\ntest ah, 2\njz short loc_1225\ncall ___ctype_toupper_loc\nmov rax, [rax]\nmovzx ebx, byte ptr [rax+r13*4]\nloc_1276:\nmov eax, 0\nmov edx, 61h ; 'a'\nloc_1280:\ncmp bl, dl\njz short loc_1239\nadd rax, 1\nmovzx edx, byte ptr [rbp+rax+0]\ntest dl, dl\njnz short loc_1280\njmp short loc_1242\nloc_1293:\nmov r12d, 0\nloc_1299:\nmov rax, [rsp+48h+var_40]\nmov byte ptr [rax+r12], 0\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "__int64 __fastcall func0(char *a1, __int64 a2)\n{\n char v2; // bl\n const unsigned __int16 **v3; // r15\n __int64 v4; // r12\n unsigned __int16 v5; // ax\n __int64 v6; // rax\n char v7; // dl\n __int64 result; // rax\n\n v2 = *a1;\n if ( *a1 )\n {\n v3 = __ctype_b_loc();\n v4 = 0LL;\n do\n {\n v5 = (*v3)[v2];\n if ( (v5 & 0x200) != 0 )\n {\n v2 = (*__ctype_toupper_loc())[v2];\n }\n else if ( (v5 & 0x100) != 0 )\n {\n v2 = (*__ctype_tolower_loc())[v2];\n }\n v6 = 0LL;\n v7 = 97;\n while ( v2 != v7 )\n {\n v7 = aAeiouaeiou[++v6];\n if ( !v7 )\n goto LABEL_7;\n }\n if ( (int)v6 < 10 )\n v2 += 2;\nLABEL_7:\n *(_BYTE *)(a2 + v4++) = v2;\n v2 = a1[v4];\n }\n while ( v2 );\n }\n else\n {\n v4 = 0LL;\n }\n result = a2;\n *(_BYTE *)(a2 + v4) = 0;\n return result;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rsi\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz loc_1293\nmov r14, rdi\ncall ___ctype_b_loc\nmov r15, rax\nmov r12d, 0\nlea rbp, aAeiouaeiou; \"aeiouAEIOU\"\njmp short loc_1258\nloc_1225:\ntest ah, 1\njz short loc_1276\ncall ___ctype_tolower_loc\nmov rax, [rax]\nmovzx ebx, byte ptr [rax+r13*4]\njmp short loc_1276\nloc_1239:\nlea edx, [rbx+2]\ncmp eax, 0Ah\ncmovl ebx, edx\nloc_1242:\nmov rax, [rsp+48h+var_40]\nmov [rax+r12], bl\nadd r12, 1\nmovzx ebx, byte ptr [r14+r12]\ntest bl, bl\njz short loc_1299\nloc_1258:\nmovsx r13, bl\nmov rax, [r15]\nmovzx eax, word ptr [rax+r13*2]\ntest ah, 2\njz short loc_1225\ncall ___ctype_toupper_loc\nmov rax, [rax]\nmovzx ebx, byte ptr [rax+r13*4]\nloc_1276:\nmov eax, 0\nmov edx, 61h ; 'a'\nloc_1280:\ncmp bl, dl\njz short loc_1239\nadd rax, 1\nmovzx edx, byte ptr [rbp+rax+0]\ntest dl, dl\njnz short loc_1280\njmp short loc_1242\nloc_1293:\nmov r12d, 0\nloc_1299:\nmov rax, [rsp+48h+var_40]\nmov byte ptr [rax+r12], 0\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11E9(char *a1, __int64 a2)\n{\n char v2; // bl\n const unsigned __int16 **v3; // r15\n __int64 v4; // r12\n unsigned __int16 v5; // ax\n __int64 v6; // rax\n char v7; // dl\n __int64 result; // rax\n\n v2 = *a1;\n if ( *a1 )\n {\n v3 = __ctype_b_loc();\n v4 = 0LL;\n do\n {\n v5 = (*v3)[v2];\n if ( (v5 & 0x200) != 0 )\n {\n v2 = (*__ctype_toupper_loc())[v2];\n }\n else if ( (v5 & 0x100) != 0 )\n {\n v2 = (*__ctype_tolower_loc())[v2];\n }\n v6 = 0LL;\n v7 = 97;\n while ( v2 != v7 )\n {\n v7 = aAeiouaeiou[++v6];\n if ( !v7 )\n goto LABEL_7;\n }\n if ( (int)v6 < 10 )\n v2 += 2;\nLABEL_7:\n *(_BYTE *)(a2 + v4++) = v2;\n v2 = a1[v4];\n }\n while ( v2 );\n }\n else\n {\n v4 = 0LL;\n }\n result = a2;\n *(_BYTE *)(a2 + v4) = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11E9(char *a1, long long a2) {\n char v2;\n const unsigned short **v3;\n long long v4;\n unsigned short v5;\n long long v6;\n char v7;\n long long result;\n v2 = *a1;\n if (*a1) {\n v3 = __ctype_b_loc();\n v4 = 0LL;\n do {\n v5 = (*v3)[v2];\n if ((v5 & 512) != 0) {\n v2 = (*__ctype_toupper_loc())[v2];\n } else if ((v5 & 256) != 0) {\n v2 = (*__ctype_tolower_loc())[v2];\n }\n v6 = 0LL;\n v7 = 97;\n while (v2 != v7) {\n v7 = aAeiouaeiou[++v6];\n if (!v7) goto LABEL_7;\n }\n if ((int)v6 < 10) v2 += 2;\n LABEL_7:\n *(uint8_t *)(a2 + v4++) = v2;\n v2 = a1[v4];\n } while (v2);\n } else {\n v4 = 0LL;\n }\n result = a2;\n *(uint8_t *)(a2 + v4) = 0;\n return result;\n}", + "ida_pseudo_norm": "long long func0(char *a1, long long a2) {\n char v2;\n const unsigned short **v3;\n long long v4;\n unsigned short v5;\n long long v6;\n char v7;\n long long result;\n v2 = *a1;\n if (*a1) {\n v3 = __ctype_b_loc();\n v4 = 0LL;\n do {\n v5 = (*v3)[v2];\n if ((v5 & 512) != 0) {\n v2 = (*__ctype_toupper_loc())[v2];\n } else if ((v5 & 256) != 0) {\n v2 = (*__ctype_tolower_loc())[v2];\n }\n v6 = 0LL;\n v7 = 97;\n while (v2 != v7) {\n v7 = aAeiouaeiou[++v6];\n if (!v7) goto LABEL_7;\n }\n if ((int)v6 < 10) v2 += 2;\n LABEL_7:\n *(uint8_t *)(a2 + v4++) = v2;\n v2 = a1[v4];\n } while (v2);\n } else {\n v4 = 0LL;\n }\n result = a2;\n *(uint8_t *)(a2 + v4) = 0;\n return result;\n}" + }, + { + "index": "HumanEval-C-93", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "void func0(const char* message, char* out) {\n const char* vowels = \"aeiouAEIOU\";\n int i, j;\n for (i = 0; message[i] != '\\0'; ++i) {\n char w = message[i];\n if (islower(w)) {\n w = toupper(w);\n } else if (isupper(w)) {\n w = tolower(w);\n }\n for (j = 0; vowels[j] != '\\0'; ++j) {\n if (w == vowels[j]) {\n if (j < 10) {\n w = w + 2;\n }\n break;\n }\n }\n out[i] = w;\n }\n out[i] = '\\0';\n}", + "test": "#include \n#include \n\nint main() {\n char output[100];\n\n func0(\"TEST\", output);\n assert(strcmp(output, \"tgst\") == 0);\n\n func0(\"Mudasir\", output);\n assert(strcmp(output, \"mWDCSKR\") == 0);\n\n func0(\"YES\", output);\n assert(strcmp(output, \"ygs\") == 0);\n\n func0(\"This is a message\", output);\n assert(strcmp(output, \"tHKS KS C MGSSCGG\") == 0);\n\n func0(\"I DoNt KnOw WhAt tO WrItE\", output);\n assert(strcmp(output, \"k dQnT kNqW wHcT Tq wRkTg\") == 0);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12, rsi\npush rbp\npush rbx\nsub rsp, 18h\nmovzx ebx, byte ptr [rdi]\nmov [rsp+48h+var_40], rdi\ntest bl, bl\njz short loc_1423\ncall ___ctype_b_loc\nxor r14d, r14d\nlea rbp, aAeiouaeiou; \"aeiouAEIOU\"\nmov r13, rax\nnop dword ptr [rax+rax+00h]\nloc_13C8:\nmov rax, [r13+0]\nmovsx r15, bl\nmovzx eax, word ptr [rax+r15*2]\ntest ah, 2\njz short loc_1440\ncall ___ctype_toupper_loc\nmov rax, [rax]\nmovzx ebx, byte ptr [rax+r15*4]\nloc_13E7:\nxor eax, eax\nmov edx, 61h ; 'a'\njmp short loc_13FD\nloc_13F0:\nadd rax, 1\nmovzx edx, byte ptr [rbp+rax+0]\ntest dl, dl\njz short loc_140A\nloc_13FD:\ncmp bl, dl\njnz short loc_13F0\nlea edx, [rbx+2]\ncmp eax, 0Ah\ncmovl ebx, edx\nloc_140A:\nmov rax, [rsp+48h+var_40]\nmov [r12+r14], bl\nadd r14, 1\nmovzx ebx, byte ptr [rax+r14]\ntest bl, bl\njnz short loc_13C8\nadd r12, r14\nloc_1423:\nmov byte ptr [r12], 0\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1440:\ntest ah, 1\njz short loc_13E7\ncall ___ctype_tolower_loc\nmov rax, [rax]\nmovzx ebx, byte ptr [rax+r15*4]\njmp short loc_13E7", + "ida_pseudo": "void __fastcall func0(char *a1, _BYTE *a2)\n{\n _BYTE *v2; // r12\n char v3; // bl\n __int64 v4; // r14\n const unsigned __int16 **v5; // r13\n unsigned __int16 v6; // ax\n __int64 v7; // rax\n char v8; // dl\n\n v2 = a2;\n v3 = *a1;\n if ( *a1 )\n {\n v4 = 0LL;\n v5 = __ctype_b_loc();\n do\n {\n v6 = (*v5)[v3];\n if ( (v6 & 0x200) != 0 )\n {\n v3 = (*__ctype_toupper_loc())[v3];\n }\n else if ( (v6 & 0x100) != 0 )\n {\n v3 = (*__ctype_tolower_loc())[v3];\n }\n v7 = 0LL;\n v8 = 97;\n while ( v3 != v8 )\n {\n v8 = aAeiouaeiou[++v7];\n if ( !v8 )\n goto LABEL_10;\n }\n if ( (int)v7 < 10 )\n v3 += 2;\nLABEL_10:\n a2[v4++] = v3;\n v3 = a1[v4];\n }\n while ( v3 );\n v2 = &a2[v4];\n }\n *v2 = 0;\n}", + "ida_strip_asm": "sub_1390:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12, rsi\npush rbp\npush rbx\nsub rsp, 18h\nmovzx ebx, byte ptr [rdi]\nmov [rsp+48h+var_40], rdi\ntest bl, bl\njz short loc_1423\ncall ___ctype_b_loc\nxor r14d, r14d\nlea rbp, aAeiouaeiou; \"aeiouAEIOU\"\nmov r13, rax\nnop dword ptr [rax+rax+00h]\nloc_13C8:\nmov rax, [r13+0]\nmovsx r15, bl\nmovzx eax, word ptr [rax+r15*2]\ntest ah, 2\njz short loc_1440\ncall ___ctype_toupper_loc\nmov rax, [rax]\nmovzx ebx, byte ptr [rax+r15*4]\nloc_13E7:\nxor eax, eax\nmov edx, 61h ; 'a'\njmp short loc_13FD\nloc_13F0:\nadd rax, 1\nmovzx edx, byte ptr [rbp+rax+0]\ntest dl, dl\njz short loc_140A\nloc_13FD:\ncmp bl, dl\njnz short loc_13F0\nlea edx, [rbx+2]\ncmp eax, 0Ah\ncmovl ebx, edx\nloc_140A:\nmov rax, [rsp+48h+var_40]\nmov [r12+r14], bl\nadd r14, 1\nmovzx ebx, byte ptr [rax+r14]\ntest bl, bl\njnz short loc_13C8\nadd r12, r14\nloc_1423:\nmov byte ptr [r12], 0\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1440:\ntest ah, 1\njz short loc_13E7\ncall ___ctype_tolower_loc\nmov rax, [rax]\nmovzx ebx, byte ptr [rax+r15*4]\njmp short loc_13E7", + "ida_strip_pseudo": "void __fastcall sub_1390(char *a1, _BYTE *a2)\n{\n _BYTE *v2; // r12\n char v3; // bl\n __int64 v4; // r14\n const unsigned __int16 **v5; // r13\n unsigned __int16 v6; // ax\n __int64 v7; // rax\n char v8; // dl\n\n v2 = a2;\n v3 = *a1;\n if ( *a1 )\n {\n v4 = 0LL;\n v5 = __ctype_b_loc();\n do\n {\n v6 = (*v5)[v3];\n if ( (v6 & 0x200) != 0 )\n {\n v3 = (*__ctype_toupper_loc())[v3];\n }\n else if ( (v6 & 0x100) != 0 )\n {\n v3 = (*__ctype_tolower_loc())[v3];\n }\n v7 = 0LL;\n v8 = 97;\n while ( v3 != v8 )\n {\n v8 = aAeiouaeiou[++v7];\n if ( !v8 )\n goto LABEL_10;\n }\n if ( (int)v7 < 10 )\n v3 += 2;\nLABEL_10:\n a2[v4++] = v3;\n v3 = a1[v4];\n }\n while ( v3 );\n v2 = &a2[v4];\n }\n *v2 = 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1390(char *a1, uint8_t *a2) {\n uint8_t *v2;\n char v3;\n long long v4;\n const unsigned short **v5;\n unsigned short v6;\n long long v7;\n char v8;\n v2 = a2;\n v3 = *a1;\n if (*a1) {\n v4 = 0LL;\n v5 = __ctype_b_loc();\n do {\n v6 = (*v5)[v3];\n if ((v6 & 512) != 0) {\n v3 = (*__ctype_toupper_loc())[v3];\n } else if ((v6 & 256) != 0) {\n v3 = (*__ctype_tolower_loc())[v3];\n }\n v7 = 0LL;\n v8 = 97;\n while (v3 != v8) {\n v8 = aAeiouaeiou[++v7];\n if (!v8) goto LABEL_10;\n }\n if ((int)v7 < 10) v3 += 2;\n LABEL_10:\n a2[v4++] = v3;\n v3 = a1[v4];\n } while (v3);\n v2 = &a2[v4];\n }\n *v2 = 0;\n}", + "ida_pseudo_norm": "void func0(char *a1, uint8_t *a2) {\n uint8_t *v2;\n char v3;\n long long v4;\n const unsigned short **v5;\n unsigned short v6;\n long long v7;\n char v8;\n v2 = a2;\n v3 = *a1;\n if (*a1) {\n v4 = 0LL;\n v5 = __ctype_b_loc();\n do {\n v6 = (*v5)[v3];\n if ((v6 & 512) != 0) {\n v3 = (*__ctype_toupper_loc())[v3];\n } else if ((v6 & 256) != 0) {\n v3 = (*__ctype_tolower_loc())[v3];\n }\n v7 = 0LL;\n v8 = 97;\n while (v3 != v8) {\n v8 = aAeiouaeiou[++v7];\n if (!v8) goto LABEL_10;\n }\n if ((int)v7 < 10) v3 += 2;\n LABEL_10:\n a2[v4++] = v3;\n v3 = a1[v4];\n } while (v3);\n v2 = &a2[v4];\n }\n *v2 = 0;\n}" + }, + { + "index": "HumanEval-C-93", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "void func0(const char* message, char* out) {\n const char* vowels = \"aeiouAEIOU\";\n int i, j;\n for (i = 0; message[i] != '\\0'; ++i) {\n char w = message[i];\n if (islower(w)) {\n w = toupper(w);\n } else if (isupper(w)) {\n w = tolower(w);\n }\n for (j = 0; vowels[j] != '\\0'; ++j) {\n if (w == vowels[j]) {\n if (j < 10) {\n w = w + 2;\n }\n break;\n }\n }\n out[i] = w;\n }\n out[i] = '\\0';\n}", + "test": "#include \n#include \n\nint main() {\n char output[100];\n\n func0(\"TEST\", output);\n assert(strcmp(output, \"tgst\") == 0);\n\n func0(\"Mudasir\", output);\n assert(strcmp(output, \"mWDCSKR\") == 0);\n\n func0(\"YES\", output);\n assert(strcmp(output, \"ygs\") == 0);\n\n func0(\"This is a message\", output);\n assert(strcmp(output, \"tHKS KS C MGSSCGG\") == 0);\n\n func0(\"I DoNt KnOw WhAt tO WrItE\", output);\n assert(strcmp(output, \"k dQnT kNqW wHcT Tq wRkTg\") == 0);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12, rsi\npush rbp\npush rbx\nsub rsp, 18h\nmovzx ebx, byte ptr [rdi]\nmov [rsp+48h+var_40], rdi\ntest bl, bl\njz short loc_1423\ncall ___ctype_b_loc\nxor r14d, r14d\nlea rbp, aAeiouaeiou; \"aeiouAEIOU\"\nmov r13, rax\nnop dword ptr [rax+rax+00h]\nloc_13C8:\nmov rax, [r13+0]\nmovsx r15, bl\nmovzx eax, word ptr [rax+r15*2]\ntest ah, 2\njz short loc_1440\ncall ___ctype_toupper_loc\nmov rax, [rax]\nmovzx ebx, byte ptr [rax+r15*4]\nloc_13E7:\nxor eax, eax\nmov edx, 61h ; 'a'\njmp short loc_13FD\nloc_13F0:\nadd rax, 1\nmovzx edx, byte ptr [rbp+rax+0]\ntest dl, dl\njz short loc_140A\nloc_13FD:\ncmp bl, dl\njnz short loc_13F0\nlea edx, [rbx+2]\ncmp eax, 0Ah\ncmovl ebx, edx\nloc_140A:\nmov rax, [rsp+48h+var_40]\nmov [r12+r14], bl\nadd r14, 1\nmovzx ebx, byte ptr [rax+r14]\ntest bl, bl\njnz short loc_13C8\nadd r12, r14\nloc_1423:\nmov byte ptr [r12], 0\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1440:\ntest ah, 1\njz short loc_13E7\ncall ___ctype_tolower_loc\nmov rax, [rax]\nmovzx ebx, byte ptr [rax+r15*4]\njmp short loc_13E7", + "ida_pseudo": "void __fastcall func0(char *a1, _BYTE *a2)\n{\n _BYTE *v2; // r12\n char v3; // bl\n __int64 v4; // r14\n const unsigned __int16 **v5; // r13\n unsigned __int16 v6; // ax\n __int64 v7; // rax\n char v8; // dl\n\n v2 = a2;\n v3 = *a1;\n if ( *a1 )\n {\n v4 = 0LL;\n v5 = __ctype_b_loc();\n do\n {\n v6 = (*v5)[v3];\n if ( (v6 & 0x200) != 0 )\n {\n v3 = (*__ctype_toupper_loc())[v3];\n }\n else if ( (v6 & 0x100) != 0 )\n {\n v3 = (*__ctype_tolower_loc())[v3];\n }\n v7 = 0LL;\n v8 = 97;\n while ( v3 != v8 )\n {\n v8 = aAeiouaeiou[++v7];\n if ( !v8 )\n goto LABEL_10;\n }\n if ( (int)v7 < 10 )\n v3 += 2;\nLABEL_10:\n a2[v4++] = v3;\n v3 = a1[v4];\n }\n while ( v3 );\n v2 = &a2[v4];\n }\n *v2 = 0;\n}", + "ida_strip_asm": "sub_1390:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12, rsi\npush rbp\npush rbx\nsub rsp, 18h\nmovzx ebx, byte ptr [rdi]\nmov [rsp+48h+var_40], rdi\ntest bl, bl\njz short loc_1423\ncall ___ctype_b_loc\nxor r14d, r14d\nlea rbp, aAeiouaeiou; \"aeiouAEIOU\"\nmov r13, rax\nnop dword ptr [rax+rax+00h]\nloc_13C8:\nmov rax, [r13+0]\nmovsx r15, bl\nmovzx eax, word ptr [rax+r15*2]\ntest ah, 2\njz short loc_1440\ncall ___ctype_toupper_loc\nmov rax, [rax]\nmovzx ebx, byte ptr [rax+r15*4]\nloc_13E7:\nxor eax, eax\nmov edx, 61h ; 'a'\njmp short loc_13FD\nloc_13F0:\nadd rax, 1\nmovzx edx, byte ptr [rbp+rax+0]\ntest dl, dl\njz short loc_140A\nloc_13FD:\ncmp bl, dl\njnz short loc_13F0\nlea edx, [rbx+2]\ncmp eax, 0Ah\ncmovl ebx, edx\nloc_140A:\nmov rax, [rsp+48h+var_40]\nmov [r12+r14], bl\nadd r14, 1\nmovzx ebx, byte ptr [rax+r14]\ntest bl, bl\njnz short loc_13C8\nadd r12, r14\nloc_1423:\nmov byte ptr [r12], 0\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1440:\ntest ah, 1\njz short loc_13E7\ncall ___ctype_tolower_loc\nmov rax, [rax]\nmovzx ebx, byte ptr [rax+r15*4]\njmp short loc_13E7", + "ida_strip_pseudo": "void __fastcall sub_1390(char *a1, _BYTE *a2)\n{\n _BYTE *v2; // r12\n char v3; // bl\n __int64 v4; // r14\n const unsigned __int16 **v5; // r13\n unsigned __int16 v6; // ax\n __int64 v7; // rax\n char v8; // dl\n\n v2 = a2;\n v3 = *a1;\n if ( *a1 )\n {\n v4 = 0LL;\n v5 = __ctype_b_loc();\n do\n {\n v6 = (*v5)[v3];\n if ( (v6 & 0x200) != 0 )\n {\n v3 = (*__ctype_toupper_loc())[v3];\n }\n else if ( (v6 & 0x100) != 0 )\n {\n v3 = (*__ctype_tolower_loc())[v3];\n }\n v7 = 0LL;\n v8 = 97;\n while ( v3 != v8 )\n {\n v8 = aAeiouaeiou[++v7];\n if ( !v8 )\n goto LABEL_10;\n }\n if ( (int)v7 < 10 )\n v3 += 2;\nLABEL_10:\n a2[v4++] = v3;\n v3 = a1[v4];\n }\n while ( v3 );\n v2 = &a2[v4];\n }\n *v2 = 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1390(char *a1, uint8_t *a2) {\n uint8_t *v2;\n char v3;\n long long v4;\n const unsigned short **v5;\n unsigned short v6;\n long long v7;\n char v8;\n v2 = a2;\n v3 = *a1;\n if (*a1) {\n v4 = 0LL;\n v5 = __ctype_b_loc();\n do {\n v6 = (*v5)[v3];\n if ((v6 & 512) != 0) {\n v3 = (*__ctype_toupper_loc())[v3];\n } else if ((v6 & 256) != 0) {\n v3 = (*__ctype_tolower_loc())[v3];\n }\n v7 = 0LL;\n v8 = 97;\n while (v3 != v8) {\n v8 = aAeiouaeiou[++v7];\n if (!v8) goto LABEL_10;\n }\n if ((int)v7 < 10) v3 += 2;\n LABEL_10:\n a2[v4++] = v3;\n v3 = a1[v4];\n } while (v3);\n v2 = &a2[v4];\n }\n *v2 = 0;\n}", + "ida_pseudo_norm": "void func0(char *a1, uint8_t *a2) {\n uint8_t *v2;\n char v3;\n long long v4;\n const unsigned short **v5;\n unsigned short v6;\n long long v7;\n char v8;\n v2 = a2;\n v3 = *a1;\n if (*a1) {\n v4 = 0LL;\n v5 = __ctype_b_loc();\n do {\n v6 = (*v5)[v3];\n if ((v6 & 512) != 0) {\n v3 = (*__ctype_toupper_loc())[v3];\n } else if ((v6 & 256) != 0) {\n v3 = (*__ctype_tolower_loc())[v3];\n }\n v7 = 0LL;\n v8 = 97;\n while (v3 != v8) {\n v8 = aAeiouaeiou[++v7];\n if (!v8) goto LABEL_10;\n }\n if ((int)v7 < 10) v3 += 2;\n LABEL_10:\n a2[v4++] = v3;\n v3 = a1[v4];\n } while (v3);\n v2 = &a2[v4];\n }\n *v2 = 0;\n}" + }, + { + "index": "HumanEval-C-94", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int lst[], int size) {\n int largest = 0, sum = 0, num, temp;\n for (int i = 0; i < size; ++i) {\n num = lst[i];\n if (num > 1) {\n int prime = 1;\n for (int j = 2; j * j <= num; ++j) {\n if (num % j == 0) {\n prime = 0;\n break;\n }\n }\n if (prime) {\n largest = num > largest ? num : largest;\n }\n }\n }\n while (largest > 0) {\n sum += largest % 10;\n largest /= 10;\n }\n return sum;\n}", + "test": "#include \n\nint main() {\n int lst1[] = {0,3,2,1,3,5,7,4,5,5,5,2,181,32,4,32,3,2,32,324,4,3};\n assert(func0(lst1, sizeof(lst1)/sizeof(lst1[0])) == 10);\n\n int lst2[] = {1,0,1,8,2,4597,2,1,3,40,1,2,1,2,4,2,5,1};\n assert(func0(lst2, sizeof(lst2)/sizeof(lst2[0])) == 25);\n\n int lst3[] = {1,3,1,32,5107,34,83278,109,163,23,2323,32,30,1,9,3};\n assert(func0(lst3, sizeof(lst3)/sizeof(lst3[0])) == 13);\n\n int lst4[] = {0,724,32,71,99,32,6,0,5,91,83,0,5,6};\n assert(func0(lst4, sizeof(lst4)/sizeof(lst4[0])) == 11);\n\n int lst5[] = {0,81,12,3,1,21};\n assert(func0(lst5, sizeof(lst5)/sizeof(lst5[0])) == 3);\n\n int lst6[] = {0,8,1,2,1,7};\n assert(func0(lst6, sizeof(lst6)/sizeof(lst6[0])) == 7);\n\n int lst7[] = {8191};\n assert(func0(lst7, sizeof(lst7)/sizeof(lst7[0])) == 19);\n\n int lst8[] = {8191, 123456, 127, 7};\n assert(func0(lst8, sizeof(lst8)/sizeof(lst8[0])) == 19);\n\n int lst9[] = {127, 97, 8192};\n assert(func0(lst9, sizeof(lst9)/sizeof(lst9[0])) == 10);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\njmp short loc_11FB\nloc_118F:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\ncmp [rbp+var_4], 1\njle short loc_11F7\nmov [rbp+var_C], 1\nmov [rbp+var_8], 2\njmp short loc_11D8\nloc_11BE:\nmov eax, [rbp+var_4]\ncdq\nidiv [rbp+var_8]\nmov eax, edx\ntest eax, eax\njnz short loc_11D4\nmov [rbp+var_C], 0\njmp short loc_11E3\nloc_11D4:\nadd [rbp+var_8], 1\nloc_11D8:\nmov eax, [rbp+var_8]\nimul eax, eax\ncmp [rbp+var_4], eax\njge short loc_11BE\nloc_11E3:\ncmp [rbp+var_C], 0\njz short loc_11F7\nmov edx, [rbp+var_18]\nmov eax, [rbp+var_4]\ncmp edx, eax\ncmovge eax, edx\nmov [rbp+var_18], eax\nloc_11F7:\nadd [rbp+var_10], 1\nloc_11FB:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_2C]\njl short loc_118F\njmp short loc_1250\nloc_1205:\nmov ecx, [rbp+var_18]\nmovsxd rax, ecx\nimul rax, 66666667h\nshr rax, 20h\nmov edx, eax\nsar edx, 2\nmov eax, ecx\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nsub ecx, eax\nmov edx, ecx\nadd [rbp+var_14], edx\nmov eax, [rbp+var_18]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_18], eax\nloc_1250:\ncmp [rbp+var_18], 0\njg short loc_1205\nmov eax, [rbp+var_14]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int v2; // eax\n int v4; // [rsp+14h] [rbp-18h]\n unsigned int v5; // [rsp+18h] [rbp-14h]\n int i; // [rsp+1Ch] [rbp-10h]\n int v7; // [rsp+20h] [rbp-Ch]\n int j; // [rsp+24h] [rbp-8h]\n int v9; // [rsp+28h] [rbp-4h]\n\n v4 = 0;\n v5 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v9 = *(_DWORD *)(4LL * i + a1);\n if ( v9 > 1 )\n {\n v7 = 1;\n for ( j = 2; v9 >= j * j; ++j )\n {\n if ( !(v9 % j) )\n {\n v7 = 0;\n break;\n }\n }\n if ( v7 )\n {\n v2 = *(_DWORD *)(4LL * i + a1);\n if ( v4 >= v9 )\n v2 = v4;\n v4 = v2;\n }\n }\n }\n while ( v4 > 0 )\n {\n v5 += v4 % 10;\n v4 /= 10;\n }\n return v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\njmp short loc_11FB\nloc_118F:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\ncmp [rbp+var_4], 1\njle short loc_11F7\nmov [rbp+var_C], 1\nmov [rbp+var_8], 2\njmp short loc_11D8\nloc_11BE:\nmov eax, [rbp+var_4]\ncdq\nidiv [rbp+var_8]\nmov eax, edx\ntest eax, eax\njnz short loc_11D4\nmov [rbp+var_C], 0\njmp short loc_11E3\nloc_11D4:\nadd [rbp+var_8], 1\nloc_11D8:\nmov eax, [rbp+var_8]\nimul eax, eax\ncmp [rbp+var_4], eax\njge short loc_11BE\nloc_11E3:\ncmp [rbp+var_C], 0\njz short loc_11F7\nmov edx, [rbp+var_18]\nmov eax, [rbp+var_4]\ncmp edx, eax\ncmovge eax, edx\nmov [rbp+var_18], eax\nloc_11F7:\nadd [rbp+var_10], 1\nloc_11FB:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_2C]\njl short loc_118F\njmp short loc_1250\nloc_1205:\nmov ecx, [rbp+var_18]\nmovsxd rax, ecx\nimul rax, 66666667h\nshr rax, 20h\nmov edx, eax\nsar edx, 2\nmov eax, ecx\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nsub ecx, eax\nmov edx, ecx\nadd [rbp+var_14], edx\nmov eax, [rbp+var_18]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_18], eax\nloc_1250:\ncmp [rbp+var_18], 0\njg short loc_1205\nmov eax, [rbp+var_14]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int v2; // eax\n int v4; // [rsp+14h] [rbp-18h]\n unsigned int v5; // [rsp+18h] [rbp-14h]\n int i; // [rsp+1Ch] [rbp-10h]\n int v7; // [rsp+20h] [rbp-Ch]\n int j; // [rsp+24h] [rbp-8h]\n int v9; // [rsp+28h] [rbp-4h]\n\n v4 = 0;\n v5 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v9 = *(_DWORD *)(4LL * i + a1);\n if ( v9 > 1 )\n {\n v7 = 1;\n for ( j = 2; v9 >= j * j; ++j )\n {\n if ( !(v9 % j) )\n {\n v7 = 0;\n break;\n }\n }\n if ( v7 )\n {\n v2 = *(_DWORD *)(4LL * i + a1);\n if ( v4 >= v9 )\n v2 = v4;\n v4 = v2;\n }\n }\n }\n while ( v4 > 0 )\n {\n v5 += v4 % 10;\n v4 /= 10;\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int v2;\n int v4;\n unsigned int v5;\n int i;\n int v7;\n int j;\n int v9;\n v4 = 0;\n v5 = 0;\n for (i = 0; i < a2; ++i) {\n v9 = *(uint32_t *)(4LL * i + a1);\n if (v9 > 1) {\n v7 = 1;\n for (j = 2; v9 >= j * j; ++j) {\n if (!(v9 % j)) {\n v7 = 0;\n break;\n }\n }\n if (v7) {\n v2 = *(uint32_t *)(4LL * i + a1);\n if (v4 >= v9) v2 = v4;\n v4 = v2;\n }\n }\n }\n while (v4 > 0) {\n v5 += v4 % 10;\n v4 /= 10;\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int v2;\n int v4;\n unsigned int v5;\n int i;\n int v7;\n int j;\n int v9;\n v4 = 0;\n v5 = 0;\n for (i = 0; i < a2; ++i) {\n v9 = *(uint32_t *)(4LL * i + a1);\n if (v9 > 1) {\n v7 = 1;\n for (j = 2; v9 >= j * j; ++j) {\n if (!(v9 % j)) {\n v7 = 0;\n break;\n }\n }\n if (v7) {\n v2 = *(uint32_t *)(4LL * i + a1);\n if (v4 >= v9) v2 = v4;\n v4 = v2;\n }\n }\n }\n while (v4 > 0) {\n v5 += v4 % 10;\n v4 /= 10;\n }\n return v5;\n}" + }, + { + "index": "HumanEval-C-94", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int lst[], int size) {\n int largest = 0, sum = 0, num, temp;\n for (int i = 0; i < size; ++i) {\n num = lst[i];\n if (num > 1) {\n int prime = 1;\n for (int j = 2; j * j <= num; ++j) {\n if (num % j == 0) {\n prime = 0;\n break;\n }\n }\n if (prime) {\n largest = num > largest ? num : largest;\n }\n }\n }\n while (largest > 0) {\n sum += largest % 10;\n largest /= 10;\n }\n return sum;\n}", + "test": "#include \n\nint main() {\n int lst1[] = {0,3,2,1,3,5,7,4,5,5,5,2,181,32,4,32,3,2,32,324,4,3};\n assert(func0(lst1, sizeof(lst1)/sizeof(lst1[0])) == 10);\n\n int lst2[] = {1,0,1,8,2,4597,2,1,3,40,1,2,1,2,4,2,5,1};\n assert(func0(lst2, sizeof(lst2)/sizeof(lst2[0])) == 25);\n\n int lst3[] = {1,3,1,32,5107,34,83278,109,163,23,2323,32,30,1,9,3};\n assert(func0(lst3, sizeof(lst3)/sizeof(lst3[0])) == 13);\n\n int lst4[] = {0,724,32,71,99,32,6,0,5,91,83,0,5,6};\n assert(func0(lst4, sizeof(lst4)/sizeof(lst4[0])) == 11);\n\n int lst5[] = {0,81,12,3,1,21};\n assert(func0(lst5, sizeof(lst5)/sizeof(lst5[0])) == 3);\n\n int lst6[] = {0,8,1,2,1,7};\n assert(func0(lst6, sizeof(lst6)/sizeof(lst6[0])) == 7);\n\n int lst7[] = {8191};\n assert(func0(lst7, sizeof(lst7)/sizeof(lst7[0])) == 19);\n\n int lst8[] = {8191, 123456, 127, 7};\n assert(func0(lst8, sizeof(lst8)/sizeof(lst8[0])) == 19);\n\n int lst9[] = {127, 97, 8192};\n assert(func0(lst9, sizeof(lst9)/sizeof(lst9[0])) == 10);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle loc_11F8\nmov r8, rdi\nmovsxd rsi, esi\nlea r9, [rdi+rsi*4]\nmov edi, 0\njmp short loc_1194\nloc_1186:\ncmp edi, esi\ncmovl edi, esi\nloc_118B:\nadd r8, 4\ncmp r9, r8\njz short loc_11C3\nloc_1194:\nmov esi, [r8]\ncmp esi, 1\njle short loc_118B\ncmp esi, 3\njle short loc_1186\ntest sil, 1\njz short loc_118B\nmov ecx, 2\nloc_11AC:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, esi\njg short loc_1186\nmov eax, esi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_11AC\njmp short loc_118B\nloc_11C3:\ntest edi, edi\njle short loc_11FF\nmov ecx, 0\nloc_11CC:\nmovsxd rax, edi\nimul rax, 66666667h\nsar rax, 22h\nmov edx, edi\nsar edx, 1Fh\nsub eax, edx\nlea edx, [rax+rax*4]\nadd edx, edx\nmov esi, edi\nsub esi, edx\nadd ecx, esi\nmov edx, edi\nmov edi, eax\ncmp edx, 9\njg short loc_11CC\nloc_11F5:\nmov eax, ecx\nretn\nloc_11F8:\nmov ecx, 0\njmp short loc_11F5\nloc_11FF:\nmov ecx, 0\njmp short loc_11F5", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int *v2; // r8\n int *v3; // r9\n int v4; // edi\n int v5; // esi\n int v6; // ecx\n unsigned int v7; // ecx\n int v8; // edx\n\n if ( a2 <= 0 )\n return 0;\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n {\n v5 = *v2;\n if ( *v2 <= 1 )\n goto LABEL_5;\n if ( v5 > 3 )\n {\n if ( (v5 & 1) == 0 )\n goto LABEL_5;\n v6 = 2;\n while ( 1 )\n {\n ++v6;\n if ( v6 * v6 > v5 )\n break;\n if ( !(v5 % v6) )\n goto LABEL_5;\n }\n }\n if ( v4 < v5 )\n v4 = *v2;\nLABEL_5:\n ++v2;\n }\n while ( v3 != v2 );\n if ( v4 <= 0 )\n {\n return 0;\n }\n else\n {\n v7 = 0;\n do\n {\n v7 += v4 % 10;\n v8 = v4;\n v4 /= 10;\n }\n while ( v8 > 9 );\n }\n return v7;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle loc_11F8\nmov r8, rdi\nmovsxd rsi, esi\nlea r9, [rdi+rsi*4]\nmov edi, 0\njmp short loc_1194\nloc_1186:\ncmp edi, esi\ncmovl edi, esi\nloc_118B:\nadd r8, 4\ncmp r9, r8\njz short loc_11C3\nloc_1194:\nmov esi, [r8]\ncmp esi, 1\njle short loc_118B\ncmp esi, 3\njle short loc_1186\ntest sil, 1\njz short loc_118B\nmov ecx, 2\nloc_11AC:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, esi\njg short loc_1186\nmov eax, esi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_11AC\njmp short loc_118B\nloc_11C3:\ntest edi, edi\njle short loc_11FF\nmov ecx, 0\nloc_11CC:\nmovsxd rax, edi\nimul rax, 66666667h\nsar rax, 22h\nmov edx, edi\nsar edx, 1Fh\nsub eax, edx\nlea edx, [rax+rax*4]\nadd edx, edx\nmov esi, edi\nsub esi, edx\nadd ecx, esi\nmov edx, edi\nmov edi, eax\ncmp edx, 9\njg short loc_11CC\nloc_11F5:\nmov eax, ecx\nretn\nloc_11F8:\nmov ecx, 0\njmp short loc_11F5\nloc_11FF:\nmov ecx, 0\njmp short loc_11F5", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int *a1, int a2)\n{\n int *v2; // r8\n int *v3; // r9\n int v4; // edi\n int v5; // esi\n int v6; // ecx\n unsigned int v7; // ecx\n int v8; // edx\n\n if ( a2 <= 0 )\n return 0;\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n {\n v5 = *v2;\n if ( *v2 <= 1 )\n goto LABEL_5;\n if ( v5 > 3 )\n {\n if ( (v5 & 1) == 0 )\n goto LABEL_5;\n v6 = 2;\n while ( 1 )\n {\n ++v6;\n if ( v6 * v6 > v5 )\n break;\n if ( !(v5 % v6) )\n goto LABEL_5;\n }\n }\n if ( v4 < v5 )\n v4 = *v2;\nLABEL_5:\n ++v2;\n }\n while ( v3 != v2 );\n if ( v4 <= 0 )\n {\n return 0;\n }\n else\n {\n v7 = 0;\n do\n {\n v7 += v4 % 10;\n v8 = v4;\n v4 /= 10;\n }\n while ( v8 > 9 );\n }\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int *a1, int a2) {\n int *v2;\n int *v3;\n int v4;\n int v5;\n int v6;\n unsigned int v7;\n int v8;\n if (a2 <= 0) return 0;\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do {\n v5 = *v2;\n if (*v2 <= 1) goto LABEL_5;\n if (v5 > 3) {\n if ((v5 & 1) == 0) goto LABEL_5;\n v6 = 2;\n while (1) {\n ++v6;\n if (v6 * v6 > v5) break;\n if (!(v5 % v6)) goto LABEL_5;\n }\n }\n if (v4 < v5) v4 = *v2;\n LABEL_5:\n ++v2;\n } while (v3 != v2);\n if (v4 <= 0) {\n return 0;\n } else {\n v7 = 0;\n do {\n v7 += v4 % 10;\n v8 = v4;\n v4 /= 10;\n } while (v8 > 9);\n }\n return v7;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int *v2;\n int *v3;\n int v4;\n int v5;\n int v6;\n unsigned int v7;\n int v8;\n if (a2 <= 0) return 0;\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do {\n v5 = *v2;\n if (*v2 <= 1) goto LABEL_5;\n if (v5 > 3) {\n if ((v5 & 1) == 0) goto LABEL_5;\n v6 = 2;\n while (1) {\n ++v6;\n if (v6 * v6 > v5) break;\n if (!(v5 % v6)) goto LABEL_5;\n }\n }\n if (v4 < v5) v4 = *v2;\n LABEL_5:\n ++v2;\n } while (v3 != v2);\n if (v4 <= 0) {\n return 0;\n } else {\n v7 = 0;\n do {\n v7 += v4 % 10;\n v8 = v4;\n v4 /= 10;\n } while (v8 > 9);\n }\n return v7;\n}" + }, + { + "index": "HumanEval-C-94", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int lst[], int size) {\n int largest = 0, sum = 0, num, temp;\n for (int i = 0; i < size; ++i) {\n num = lst[i];\n if (num > 1) {\n int prime = 1;\n for (int j = 2; j * j <= num; ++j) {\n if (num % j == 0) {\n prime = 0;\n break;\n }\n }\n if (prime) {\n largest = num > largest ? num : largest;\n }\n }\n }\n while (largest > 0) {\n sum += largest % 10;\n largest /= 10;\n }\n return sum;\n}", + "test": "#include \n\nint main() {\n int lst1[] = {0,3,2,1,3,5,7,4,5,5,5,2,181,32,4,32,3,2,32,324,4,3};\n assert(func0(lst1, sizeof(lst1)/sizeof(lst1[0])) == 10);\n\n int lst2[] = {1,0,1,8,2,4597,2,1,3,40,1,2,1,2,4,2,5,1};\n assert(func0(lst2, sizeof(lst2)/sizeof(lst2[0])) == 25);\n\n int lst3[] = {1,3,1,32,5107,34,83278,109,163,23,2323,32,30,1,9,3};\n assert(func0(lst3, sizeof(lst3)/sizeof(lst3[0])) == 13);\n\n int lst4[] = {0,724,32,71,99,32,6,0,5,91,83,0,5,6};\n assert(func0(lst4, sizeof(lst4)/sizeof(lst4[0])) == 11);\n\n int lst5[] = {0,81,12,3,1,21};\n assert(func0(lst5, sizeof(lst5)/sizeof(lst5[0])) == 3);\n\n int lst6[] = {0,8,1,2,1,7};\n assert(func0(lst6, sizeof(lst6)/sizeof(lst6[0])) == 7);\n\n int lst7[] = {8191};\n assert(func0(lst7, sizeof(lst7)/sizeof(lst7[0])) == 19);\n\n int lst8[] = {8191, 123456, 127, 7};\n assert(func0(lst8, sizeof(lst8)/sizeof(lst8[0])) == 19);\n\n int lst9[] = {127, 97, 8192};\n assert(func0(lst9, sizeof(lst9)/sizeof(lst9[0])) == 10);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle loc_15D5\nmovsxd rsi, esi\nxor r8d, r8d\nlea r9, [rdi+rsi*4]\njmp short loc_1559\nloc_1550:\nadd rdi, 4\ncmp r9, rdi\njz short loc_15A0\nloc_1559:\nmov esi, [rdi]\ncmp esi, 1\njle short loc_1550\ncmp esi, 3\njle short loc_158D\ntest sil, 1\njz short loc_1550\nmov ecx, 2\njmp short loc_1581\nloc_1578:\nmov eax, esi\ncdq\nidiv ecx\ntest edx, edx\njz short loc_1550\nloc_1581:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, esi\njle short loc_1578\nloc_158D:\ncmp r8d, esi\ncmovl r8d, esi\nadd rdi, 4\ncmp r9, rdi\njnz short loc_1559\nnop dword ptr [rax]\nloc_15A0:\nxor ecx, ecx\ntest r8d, r8d\njle short loc_15D2\nmov edi, 0CCCCCCCDh\nnop dword ptr [rax+00h]\nloc_15B0:\nmov eax, r8d\nmov esi, r8d\nimul rax, rdi\nshr rax, 23h\nlea edx, [rax+rax*4]\nadd edx, edx\nsub esi, edx\nmov edx, r8d\nmov r8d, eax\nadd ecx, esi\ncmp edx, 9\njg short loc_15B0\nloc_15D2:\nmov eax, ecx\nretn\nloc_15D5:\nxor ecx, ecx\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int v2; // r8d\n int *v3; // r9\n int v4; // esi\n int v5; // ecx\n unsigned int v6; // ecx\n unsigned int v7; // esi\n int v8; // edx\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 0;\n v3 = &a1[a2];\n do\n {\n while ( 1 )\n {\n v4 = *a1;\n if ( *a1 > 1 )\n {\n if ( v4 <= 3 )\n goto LABEL_10;\n if ( (v4 & 1) != 0 )\n break;\n }\nLABEL_3:\n if ( v3 == ++a1 )\n goto LABEL_13;\n }\n v5 = 2;\n while ( 1 )\n {\n ++v5;\n if ( v5 * v5 > v4 )\n break;\n if ( !(v4 % v5) )\n goto LABEL_3;\n }\nLABEL_10:\n if ( v2 < v4 )\n v2 = *a1;\n ++a1;\n }\n while ( v3 != a1 );\nLABEL_13:\n v6 = 0;\n if ( v2 > 0 )\n {\n do\n {\n v7 = v2 % 0xAu;\n v8 = v2;\n v2 /= 0xAu;\n v6 += v7;\n }\n while ( v8 > 9 );\n }\n return v6;\n}", + "ida_strip_asm": "sub_1530:\nendbr64\ntest esi, esi\njle loc_15D5\nmovsxd rsi, esi\nxor r8d, r8d\nlea r9, [rdi+rsi*4]\njmp short loc_1559\nloc_1550:\nadd rdi, 4\ncmp r9, rdi\njz short loc_15A0\nloc_1559:\nmov esi, [rdi]\ncmp esi, 1\njle short loc_1550\ncmp esi, 3\njle short loc_158D\ntest sil, 1\njz short loc_1550\nmov ecx, 2\njmp short loc_1581\nloc_1578:\nmov eax, esi\ncdq\nidiv ecx\ntest edx, edx\njz short loc_1550\nloc_1581:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, esi\njle short loc_1578\nloc_158D:\ncmp r8d, esi\ncmovl r8d, esi\nadd rdi, 4\ncmp r9, rdi\njnz short loc_1559\nnop dword ptr [rax]\nloc_15A0:\nxor ecx, ecx\ntest r8d, r8d\njle short loc_15D2\nmov edi, 0CCCCCCCDh\nnop dword ptr [rax+00h]\nloc_15B0:\nmov eax, r8d\nmov esi, r8d\nimul rax, rdi\nshr rax, 23h\nlea edx, [rax+rax*4]\nadd edx, edx\nsub esi, edx\nmov edx, r8d\nmov r8d, eax\nadd ecx, esi\ncmp edx, 9\njg short loc_15B0\nloc_15D2:\nmov eax, ecx\nretn\nloc_15D5:\nxor ecx, ecx\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1530(int *a1, int a2)\n{\n int v2; // r8d\n int *v3; // r9\n int v4; // esi\n int v5; // ecx\n unsigned int v6; // ecx\n unsigned int v7; // esi\n int v8; // edx\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 0;\n v3 = &a1[a2];\n do\n {\n while ( 1 )\n {\n v4 = *a1;\n if ( *a1 > 1 )\n {\n if ( v4 <= 3 )\n goto LABEL_10;\n if ( (v4 & 1) != 0 )\n break;\n }\nLABEL_3:\n if ( v3 == ++a1 )\n goto LABEL_13;\n }\n v5 = 2;\n while ( 1 )\n {\n ++v5;\n if ( v5 * v5 > v4 )\n break;\n if ( !(v4 % v5) )\n goto LABEL_3;\n }\nLABEL_10:\n if ( v2 < v4 )\n v2 = *a1;\n ++a1;\n }\n while ( v3 != a1 );\nLABEL_13:\n v6 = 0;\n if ( v2 > 0 )\n {\n do\n {\n v7 = v2 % 0xAu;\n v8 = v2;\n v2 /= 0xAu;\n v6 += v7;\n }\n while ( v8 > 9 );\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1530(int *a1, int a2) {\n int v2;\n int *v3;\n int v4;\n int v5;\n unsigned int v6;\n unsigned int v7;\n int v8;\n if (a2 <= 0) return 0LL;\n v2 = 0;\n v3 = &a1[a2];\n do {\n while (1) {\n v4 = *a1;\n if (*a1 > 1) {\n if (v4 <= 3) goto LABEL_10;\n if ((v4 & 1) != 0) break;\n }\n LABEL_3:\n if (v3 == ++a1) goto LABEL_13;\n }\n v5 = 2;\n while (1) {\n ++v5;\n if (v5 * v5 > v4) break;\n if (!(v4 % v5)) goto LABEL_3;\n }\n LABEL_10:\n if (v2 < v4) v2 = *a1;\n ++a1;\n } while (v3 != a1);\nLABEL_13:\n v6 = 0;\n if (v2 > 0) {\n do {\n v7 = v2 % 10u;\n v8 = v2;\n v2 /= 10u;\n v6 += v7;\n } while (v8 > 9);\n }\n return v6;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int v2;\n int *v3;\n int v4;\n int v5;\n unsigned int v6;\n unsigned int v7;\n int v8;\n if (a2 <= 0) return 0LL;\n v2 = 0;\n v3 = &a1[a2];\n do {\n while (1) {\n v4 = *a1;\n if (*a1 > 1) {\n if (v4 <= 3) goto LABEL_10;\n if ((v4 & 1) != 0) break;\n }\n LABEL_3:\n if (v3 == ++a1) goto LABEL_13;\n }\n v5 = 2;\n while (1) {\n ++v5;\n if (v5 * v5 > v4) break;\n if (!(v4 % v5)) goto LABEL_3;\n }\n LABEL_10:\n if (v2 < v4) v2 = *a1;\n ++a1;\n } while (v3 != a1);\nLABEL_13:\n v6 = 0;\n if (v2 > 0) {\n do {\n v7 = v2 % 10u;\n v8 = v2;\n v2 /= 10u;\n v6 += v7;\n } while (v8 > 9);\n }\n return v6;\n}" + }, + { + "index": "HumanEval-C-94", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int lst[], int size) {\n int largest = 0, sum = 0, num, temp;\n for (int i = 0; i < size; ++i) {\n num = lst[i];\n if (num > 1) {\n int prime = 1;\n for (int j = 2; j * j <= num; ++j) {\n if (num % j == 0) {\n prime = 0;\n break;\n }\n }\n if (prime) {\n largest = num > largest ? num : largest;\n }\n }\n }\n while (largest > 0) {\n sum += largest % 10;\n largest /= 10;\n }\n return sum;\n}", + "test": "#include \n\nint main() {\n int lst1[] = {0,3,2,1,3,5,7,4,5,5,5,2,181,32,4,32,3,2,32,324,4,3};\n assert(func0(lst1, sizeof(lst1)/sizeof(lst1[0])) == 10);\n\n int lst2[] = {1,0,1,8,2,4597,2,1,3,40,1,2,1,2,4,2,5,1};\n assert(func0(lst2, sizeof(lst2)/sizeof(lst2[0])) == 25);\n\n int lst3[] = {1,3,1,32,5107,34,83278,109,163,23,2323,32,30,1,9,3};\n assert(func0(lst3, sizeof(lst3)/sizeof(lst3[0])) == 13);\n\n int lst4[] = {0,724,32,71,99,32,6,0,5,91,83,0,5,6};\n assert(func0(lst4, sizeof(lst4)/sizeof(lst4[0])) == 11);\n\n int lst5[] = {0,81,12,3,1,21};\n assert(func0(lst5, sizeof(lst5)/sizeof(lst5[0])) == 3);\n\n int lst6[] = {0,8,1,2,1,7};\n assert(func0(lst6, sizeof(lst6)/sizeof(lst6[0])) == 7);\n\n int lst7[] = {8191};\n assert(func0(lst7, sizeof(lst7)/sizeof(lst7[0])) == 19);\n\n int lst8[] = {8191, 123456, 127, 7};\n assert(func0(lst8, sizeof(lst8)/sizeof(lst8[0])) == 19);\n\n int lst9[] = {127, 97, 8192};\n assert(func0(lst9, sizeof(lst9)/sizeof(lst9[0])) == 10);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle loc_15D5\nmovsxd rsi, esi\nxor r8d, r8d\nlea r9, [rdi+rsi*4]\njmp short loc_1559\nloc_1550:\nadd rdi, 4\ncmp r9, rdi\njz short loc_15A0\nloc_1559:\nmov esi, [rdi]\ncmp esi, 1\njle short loc_1550\ncmp esi, 3\njle short loc_158D\ntest sil, 1\njz short loc_1550\nmov ecx, 2\njmp short loc_1581\nloc_1578:\nmov eax, esi\ncdq\nidiv ecx\ntest edx, edx\njz short loc_1550\nloc_1581:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, esi\njle short loc_1578\nloc_158D:\ncmp r8d, esi\ncmovl r8d, esi\nadd rdi, 4\ncmp r9, rdi\njnz short loc_1559\nnop dword ptr [rax]\nloc_15A0:\nxor ecx, ecx\ntest r8d, r8d\njle short loc_15D2\nmov edi, 0CCCCCCCDh\nnop dword ptr [rax+00h]\nloc_15B0:\nmov eax, r8d\nmov esi, r8d\nimul rax, rdi\nshr rax, 23h\nlea edx, [rax+rax*4]\nadd edx, edx\nsub esi, edx\nmov edx, r8d\nmov r8d, eax\nadd ecx, esi\ncmp edx, 9\njg short loc_15B0\nloc_15D2:\nmov eax, ecx\nretn\nloc_15D5:\nxor ecx, ecx\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int v2; // r8d\n int *v3; // r9\n int v4; // esi\n int v5; // ecx\n unsigned int v6; // ecx\n unsigned int v7; // esi\n int v8; // edx\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 0;\n v3 = &a1[a2];\n do\n {\n while ( 1 )\n {\n v4 = *a1;\n if ( *a1 > 1 )\n {\n if ( v4 <= 3 )\n goto LABEL_10;\n if ( (v4 & 1) != 0 )\n break;\n }\nLABEL_3:\n if ( v3 == ++a1 )\n goto LABEL_13;\n }\n v5 = 2;\n while ( 1 )\n {\n ++v5;\n if ( v5 * v5 > v4 )\n break;\n if ( !(v4 % v5) )\n goto LABEL_3;\n }\nLABEL_10:\n if ( v2 < v4 )\n v2 = *a1;\n ++a1;\n }\n while ( v3 != a1 );\nLABEL_13:\n v6 = 0;\n if ( v2 > 0 )\n {\n do\n {\n v7 = v2 % 0xAu;\n v8 = v2;\n v2 /= 0xAu;\n v6 += v7;\n }\n while ( v8 > 9 );\n }\n return v6;\n}", + "ida_strip_asm": "sub_1530:\nendbr64\ntest esi, esi\njle loc_15D5\nmovsxd rsi, esi\nxor r8d, r8d\nlea r9, [rdi+rsi*4]\njmp short loc_1559\nloc_1550:\nadd rdi, 4\ncmp r9, rdi\njz short loc_15A0\nloc_1559:\nmov esi, [rdi]\ncmp esi, 1\njle short loc_1550\ncmp esi, 3\njle short loc_158D\ntest sil, 1\njz short loc_1550\nmov ecx, 2\njmp short loc_1581\nloc_1578:\nmov eax, esi\ncdq\nidiv ecx\ntest edx, edx\njz short loc_1550\nloc_1581:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, esi\njle short loc_1578\nloc_158D:\ncmp r8d, esi\ncmovl r8d, esi\nadd rdi, 4\ncmp r9, rdi\njnz short loc_1559\nnop dword ptr [rax]\nloc_15A0:\nxor ecx, ecx\ntest r8d, r8d\njle short loc_15D2\nmov edi, 0CCCCCCCDh\nnop dword ptr [rax+00h]\nloc_15B0:\nmov eax, r8d\nmov esi, r8d\nimul rax, rdi\nshr rax, 23h\nlea edx, [rax+rax*4]\nadd edx, edx\nsub esi, edx\nmov edx, r8d\nmov r8d, eax\nadd ecx, esi\ncmp edx, 9\njg short loc_15B0\nloc_15D2:\nmov eax, ecx\nretn\nloc_15D5:\nxor ecx, ecx\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1530(int *a1, int a2)\n{\n int v2; // r8d\n int *v3; // r9\n int v4; // esi\n int v5; // ecx\n unsigned int v6; // ecx\n unsigned int v7; // esi\n int v8; // edx\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 0;\n v3 = &a1[a2];\n do\n {\n while ( 1 )\n {\n v4 = *a1;\n if ( *a1 > 1 )\n {\n if ( v4 <= 3 )\n goto LABEL_10;\n if ( (v4 & 1) != 0 )\n break;\n }\nLABEL_3:\n if ( v3 == ++a1 )\n goto LABEL_13;\n }\n v5 = 2;\n while ( 1 )\n {\n ++v5;\n if ( v5 * v5 > v4 )\n break;\n if ( !(v4 % v5) )\n goto LABEL_3;\n }\nLABEL_10:\n if ( v2 < v4 )\n v2 = *a1;\n ++a1;\n }\n while ( v3 != a1 );\nLABEL_13:\n v6 = 0;\n if ( v2 > 0 )\n {\n do\n {\n v7 = v2 % 0xAu;\n v8 = v2;\n v2 /= 0xAu;\n v6 += v7;\n }\n while ( v8 > 9 );\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1530(int *a1, int a2) {\n int v2;\n int *v3;\n int v4;\n int v5;\n unsigned int v6;\n unsigned int v7;\n int v8;\n if (a2 <= 0) return 0LL;\n v2 = 0;\n v3 = &a1[a2];\n do {\n while (1) {\n v4 = *a1;\n if (*a1 > 1) {\n if (v4 <= 3) goto LABEL_10;\n if ((v4 & 1) != 0) break;\n }\n LABEL_3:\n if (v3 == ++a1) goto LABEL_13;\n }\n v5 = 2;\n while (1) {\n ++v5;\n if (v5 * v5 > v4) break;\n if (!(v4 % v5)) goto LABEL_3;\n }\n LABEL_10:\n if (v2 < v4) v2 = *a1;\n ++a1;\n } while (v3 != a1);\nLABEL_13:\n v6 = 0;\n if (v2 > 0) {\n do {\n v7 = v2 % 10u;\n v8 = v2;\n v2 /= 10u;\n v6 += v7;\n } while (v8 > 9);\n }\n return v6;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int v2;\n int *v3;\n int v4;\n int v5;\n unsigned int v6;\n unsigned int v7;\n int v8;\n if (a2 <= 0) return 0LL;\n v2 = 0;\n v3 = &a1[a2];\n do {\n while (1) {\n v4 = *a1;\n if (*a1 > 1) {\n if (v4 <= 3) goto LABEL_10;\n if ((v4 & 1) != 0) break;\n }\n LABEL_3:\n if (v3 == ++a1) goto LABEL_13;\n }\n v5 = 2;\n while (1) {\n ++v5;\n if (v5 * v5 > v4) break;\n if (!(v4 % v5)) goto LABEL_3;\n }\n LABEL_10:\n if (v2 < v4) v2 = *a1;\n ++a1;\n } while (v3 != a1);\nLABEL_13:\n v6 = 0;\n if (v2 > 0) {\n do {\n v7 = v2 % 10u;\n v8 = v2;\n v2 /= 10u;\n v6 += v7;\n } while (v8 > 9);\n }\n return v6;\n}" + }, + { + "index": "HumanEval-C-95", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n#include \n", + "func": "int func0(char* dict[][2], int size) {\n if (size == 0) return 0;\n int has_lower = 0, has_upper = 0;\n for (int i = 0; i < size; ++i) {\n char* key = dict[i][0];\n for (int j = 0; key[j]; ++j) {\n if (!isalpha((unsigned char)key[j])) return 0;\n if (isupper((unsigned char)key[j])) has_upper = 1;\n if (islower((unsigned char)key[j])) has_lower = 1;\n if (has_upper + has_lower == 2) return 0;\n }\n }\n return 1;\n}", + "test": "#include \n\nint main() {\n char* test1[][2] = {{\"p\",\"pineapple\"}, {\"b\",\"banana\"}};\n assert(func0(test1, 2) == 1);\n\n char* test2[][2] = {{\"p\",\"pineapple\"}, {\"A\",\"banana\"}, {\"B\",\"banana\"}};\n assert(func0(test2, 3) == 0);\n\n char* test3[][2] = {{\"p\",\"pineapple\"}, {\"5\",\"banana\"}, {\"a\",\"apple\"}};\n assert(func0(test3, 3) == 0);\n\n char* test4[][2] = {{\"Name\",\"John\"}, {\"Age\",\"36\"}, {\"City\",\"Houston\"}};\n assert(func0(test4, 3) == 0);\n\n char* test5[][2] = {{\"STATE\",\"NC\"}, {\"ZIP\",\"12345\"}};\n assert(func0(test5, 2) == 1);\n\n char* test6[][2] = {{\"fruit\",\"Orange\"}, {\"taste\",\"Sweet\"}};\n assert(func0(test6, 2) == 1);\n\n assert(func0(NULL, 0) == 0);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\ncmp [rbp+var_2C], 0\njnz short loc_11AC\nmov eax, 0\njmp locret_12D9\nloc_11AC:\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\njmp loc_12C8\nloc_11C6:\nmov eax, [rbp+var_10]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp loc_12AC\nloc_11EC:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_C]\nmovsxd rcx, edx\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovzx edx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 400h\ntest eax, eax\njnz short loc_1226\nmov eax, 0\njmp locret_12D9\nloc_1226:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_C]\nmovsxd rcx, edx\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovzx edx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 100h\ntest eax, eax\njz short loc_125D\nmov [rbp+var_14], 1\nloc_125D:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_C]\nmovsxd rcx, edx\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovzx edx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 200h\ntest eax, eax\njz short loc_1294\nmov [rbp+var_18], 1\nloc_1294:\nmov edx, [rbp+var_14]\nmov eax, [rbp+var_18]\nadd eax, edx\ncmp eax, 2\njnz short loc_12A8\nmov eax, 0\njmp short locret_12D9\nloc_12A8:\nadd [rbp+var_C], 1\nloc_12AC:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_11EC\nadd [rbp+var_10], 1\nloc_12C8:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_2C]\njl loc_11C6\nmov eax, 1\nlocret_12D9:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int v3; // [rsp+18h] [rbp-18h]\n int v4; // [rsp+1Ch] [rbp-14h]\n int i; // [rsp+20h] [rbp-10h]\n int j; // [rsp+24h] [rbp-Ch]\n __int64 v7; // [rsp+28h] [rbp-8h]\n\n if ( !a2 )\n return 0LL;\n v3 = 0;\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v7 = *(_QWORD *)(16LL * i + a1);\n for ( j = 0; *(_BYTE *)(j + v7); ++j )\n {\n if ( ((*__ctype_b_loc())[*(unsigned __int8 *)(j + v7)] & 0x400) == 0 )\n return 0LL;\n if ( ((*__ctype_b_loc())[*(unsigned __int8 *)(j + v7)] & 0x100) != 0 )\n v4 = 1;\n if ( ((*__ctype_b_loc())[*(unsigned __int8 *)(j + v7)] & 0x200) != 0 )\n v3 = 1;\n if ( v4 + v3 == 2 )\n return 0LL;\n }\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\ncmp [rbp+var_2C], 0\njnz short loc_11AC\nmov eax, 0\njmp locret_12D9\nloc_11AC:\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\njmp loc_12C8\nloc_11C6:\nmov eax, [rbp+var_10]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp loc_12AC\nloc_11EC:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_C]\nmovsxd rcx, edx\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovzx edx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 400h\ntest eax, eax\njnz short loc_1226\nmov eax, 0\njmp locret_12D9\nloc_1226:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_C]\nmovsxd rcx, edx\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovzx edx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 100h\ntest eax, eax\njz short loc_125D\nmov [rbp+var_14], 1\nloc_125D:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_C]\nmovsxd rcx, edx\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovzx edx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 200h\ntest eax, eax\njz short loc_1294\nmov [rbp+var_18], 1\nloc_1294:\nmov edx, [rbp+var_14]\nmov eax, [rbp+var_18]\nadd eax, edx\ncmp eax, 2\njnz short loc_12A8\nmov eax, 0\njmp short locret_12D9\nloc_12A8:\nadd [rbp+var_C], 1\nloc_12AC:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_11EC\nadd [rbp+var_10], 1\nloc_12C8:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_2C]\njl loc_11C6\nmov eax, 1\nlocret_12D9:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2)\n{\n int v3; // [rsp+18h] [rbp-18h]\n int v4; // [rsp+1Ch] [rbp-14h]\n int i; // [rsp+20h] [rbp-10h]\n int j; // [rsp+24h] [rbp-Ch]\n __int64 v7; // [rsp+28h] [rbp-8h]\n\n if ( !a2 )\n return 0LL;\n v3 = 0;\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v7 = *(_QWORD *)(16LL * i + a1);\n for ( j = 0; *(_BYTE *)(j + v7); ++j )\n {\n if ( ((*__ctype_b_loc())[*(unsigned __int8 *)(j + v7)] & 0x400) == 0 )\n return 0LL;\n if ( ((*__ctype_b_loc())[*(unsigned __int8 *)(j + v7)] & 0x100) != 0 )\n v4 = 1;\n if ( ((*__ctype_b_loc())[*(unsigned __int8 *)(j + v7)] & 0x200) != 0 )\n v3 = 1;\n if ( v4 + v3 == 2 )\n return 0LL;\n }\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2) {\n int v3;\n int v4;\n int i;\n int j;\n long long v7;\n if (!a2) return 0LL;\n v3 = 0;\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n v7 = *(uint64_t *)(16LL * i + a1);\n for (j = 0; *(uint8_t *)(j + v7); ++j) {\n if (((*__ctype_b_loc())[*(unsigned char *)(j + v7)] & 1024) == 0)\n return 0LL;\n if (((*__ctype_b_loc())[*(unsigned char *)(j + v7)] & 256) != 0) v4 = 1;\n if (((*__ctype_b_loc())[*(unsigned char *)(j + v7)] & 512) != 0) v3 = 1;\n if (v4 + v3 == 2) return 0LL;\n }\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int v3;\n int v4;\n int i;\n int j;\n long long v7;\n if (!a2) return 0LL;\n v3 = 0;\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n v7 = *(uint64_t *)(16LL * i + a1);\n for (j = 0; *(uint8_t *)(j + v7); ++j) {\n if (((*__ctype_b_loc())[*(unsigned char *)(j + v7)] & 1024) == 0)\n return 0LL;\n if (((*__ctype_b_loc())[*(unsigned char *)(j + v7)] & 256) != 0) v4 = 1;\n if (((*__ctype_b_loc())[*(unsigned char *)(j + v7)] & 512) != 0) v3 = 1;\n if (v4 + v3 == 2) return 0LL;\n }\n }\n return 1LL;\n}" + }, + { + "index": "HumanEval-C-95", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n#include \n", + "func": "int func0(char* dict[][2], int size) {\n if (size == 0) return 0;\n int has_lower = 0, has_upper = 0;\n for (int i = 0; i < size; ++i) {\n char* key = dict[i][0];\n for (int j = 0; key[j]; ++j) {\n if (!isalpha((unsigned char)key[j])) return 0;\n if (isupper((unsigned char)key[j])) has_upper = 1;\n if (islower((unsigned char)key[j])) has_lower = 1;\n if (has_upper + has_lower == 2) return 0;\n }\n }\n return 1;\n}", + "test": "#include \n\nint main() {\n char* test1[][2] = {{\"p\",\"pineapple\"}, {\"b\",\"banana\"}};\n assert(func0(test1, 2) == 1);\n\n char* test2[][2] = {{\"p\",\"pineapple\"}, {\"A\",\"banana\"}, {\"B\",\"banana\"}};\n assert(func0(test2, 3) == 0);\n\n char* test3[][2] = {{\"p\",\"pineapple\"}, {\"5\",\"banana\"}, {\"a\",\"apple\"}};\n assert(func0(test3, 3) == 0);\n\n char* test4[][2] = {{\"Name\",\"John\"}, {\"Age\",\"36\"}, {\"City\",\"Houston\"}};\n assert(func0(test4, 3) == 0);\n\n char* test5[][2] = {{\"STATE\",\"NC\"}, {\"ZIP\",\"12345\"}};\n assert(func0(test5, 2) == 1);\n\n char* test6[][2] = {{\"fruit\",\"Orange\"}, {\"taste\",\"Sweet\"}};\n assert(func0(test6, 2) == 1);\n\n assert(func0(NULL, 0) == 0);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmov eax, esi\ntest esi, esi\njz locret_1259\njle short loc_11FA\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov r15, rdi\nmovsxd rsi, esi\nshl rsi, 4\nlea rax, [rdi+rsi]\nmov [rsp+48h+var_40], rax\nmov r13d, 0\nmov r12d, 0\nmov r14d, 1\nloc_11CC:\nmov rbp, [r15]\nmovzx ebx, byte ptr [rbp+0]\ntest bl, bl\njz short loc_11E5\ncall ___ctype_b_loc\nmov rdx, [rax]\nadd rbp, 1\njmp short loc_123F\nloc_11E5:\nadd r15, 10h\nmov rax, [rsp+48h+var_40]\ncmp r15, rax\njnz short loc_11CC\nmov eax, 1\njmp short loc_1205\nloc_11FA:\nmov eax, 1\nretn\nloc_1200:\nmov eax, 0\nloc_1205:\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1214:\nmov eax, 0\njmp short loc_1205\nloc_121B:\nmov eax, 0\njmp short loc_1205\nloc_1222:\ntest ah, 2\njnz short loc_121B\nmov r13d, r14d\nloc_122A:\nlea eax, [r12+r13]\ncmp eax, 2\njz short loc_1214\nadd rbp, 1\nmovzx ebx, byte ptr [rbp-1]\ntest bl, bl\njz short loc_11E5\nloc_123F:\nmovzx ebx, bl\nmovzx eax, word ptr [rdx+rbx*2]\ntest ah, 4\njz short loc_1200\ntest ah, 1\njnz short loc_1222\ntest ah, 2\ncmovnz r12d, r14d\njmp short loc_122A\nlocret_1259:\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned __int8 **a1, int a2)\n{\n __int64 result; // rax\n unsigned __int8 **v3; // r15\n int v4; // r13d\n int v5; // r12d\n unsigned __int8 *v6; // rbp\n unsigned __int8 v7; // bl\n const unsigned __int16 *v8; // rdx\n unsigned __int8 *v9; // rbp\n unsigned __int16 v10; // ax\n\n result = (unsigned int)a2;\n if ( a2 )\n {\n if ( a2 <= 0 )\n return 1LL;\n v3 = a1;\n v4 = 0;\n v5 = 0;\n while ( 1 )\n {\n v6 = *v3;\n v7 = **v3;\n if ( v7 )\n break;\nLABEL_6:\n v3 += 2;\n if ( v3 == &a1[2 * a2] )\n return 1LL;\n }\n v8 = *__ctype_b_loc();\n v9 = v6 + 1;\n while ( 1 )\n {\n v10 = v8[v7];\n if ( (v10 & 0x400) == 0 )\n return 0LL;\n if ( (v10 & 0x100) != 0 )\n {\n if ( (v10 & 0x200) != 0 )\n return 0LL;\n v4 = 1;\n }\n else if ( (v10 & 0x200) != 0 )\n {\n v5 = 1;\n }\n if ( v5 + v4 == 2 )\n return 0LL;\n v7 = *v9++;\n if ( !v7 )\n goto LABEL_6;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\nmov eax, esi\ntest esi, esi\njz locret_1259\njle short loc_11FA\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov r15, rdi\nmovsxd rsi, esi\nshl rsi, 4\nlea rax, [rdi+rsi]\nmov [rsp+48h+var_40], rax\nmov r13d, 0\nmov r12d, 0\nmov r14d, 1\nloc_11CC:\nmov rbp, [r15]\nmovzx ebx, byte ptr [rbp+0]\ntest bl, bl\njz short loc_11E5\ncall ___ctype_b_loc\nmov rdx, [rax]\nadd rbp, 1\njmp short loc_123F\nloc_11E5:\nadd r15, 10h\nmov rax, [rsp+48h+var_40]\ncmp r15, rax\njnz short loc_11CC\nmov eax, 1\njmp short loc_1205\nloc_11FA:\nmov eax, 1\nretn\nloc_1200:\nmov eax, 0\nloc_1205:\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1214:\nmov eax, 0\njmp short loc_1205\nloc_121B:\nmov eax, 0\njmp short loc_1205\nloc_1222:\ntest ah, 2\njnz short loc_121B\nmov r13d, r14d\nloc_122A:\nlea eax, [r12+r13]\ncmp eax, 2\njz short loc_1214\nadd rbp, 1\nmovzx ebx, byte ptr [rbp-1]\ntest bl, bl\njz short loc_11E5\nloc_123F:\nmovzx ebx, bl\nmovzx eax, word ptr [rdx+rbx*2]\ntest ah, 4\njz short loc_1200\ntest ah, 1\njnz short loc_1222\ntest ah, 2\ncmovnz r12d, r14d\njmp short loc_122A\nlocret_1259:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(unsigned __int8 **a1, int a2)\n{\n __int64 result; // rax\n unsigned __int8 **v3; // r15\n int v4; // r13d\n int v5; // r12d\n unsigned __int8 *v6; // rbp\n unsigned __int8 v7; // bl\n const unsigned __int16 *v8; // rdx\n unsigned __int8 *v9; // rbp\n unsigned __int16 v10; // ax\n\n result = (unsigned int)a2;\n if ( a2 )\n {\n if ( a2 <= 0 )\n return 1LL;\n v3 = a1;\n v4 = 0;\n v5 = 0;\n while ( 1 )\n {\n v6 = *v3;\n v7 = **v3;\n if ( v7 )\n break;\nLABEL_6:\n v3 += 2;\n if ( v3 == &a1[2 * a2] )\n return 1LL;\n }\n v8 = *__ctype_b_loc();\n v9 = v6 + 1;\n while ( 1 )\n {\n v10 = v8[v7];\n if ( (v10 & 0x400) == 0 )\n return 0LL;\n if ( (v10 & 0x100) != 0 )\n {\n if ( (v10 & 0x200) != 0 )\n return 0LL;\n v4 = 1;\n }\n else if ( (v10 & 0x200) != 0 )\n {\n v5 = 1;\n }\n if ( v5 + v4 == 2 )\n return 0LL;\n v7 = *v9++;\n if ( !v7 )\n goto LABEL_6;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(unsigned char **a1, int a2) {\n long long result;\n unsigned char **v3;\n int v4;\n int v5;\n unsigned char *v6;\n unsigned char v7;\n const unsigned short *v8;\n unsigned char *v9;\n unsigned short v10;\n result = (unsigned int)a2;\n if (a2) {\n if (a2 <= 0) return 1LL;\n v3 = a1;\n v4 = 0;\n v5 = 0;\n while (1) {\n v6 = *v3;\n v7 = **v3;\n if (v7) break;\n LABEL_6:\n v3 += 2;\n if (v3 == &a1[2 * a2]) return 1LL;\n }\n v8 = *__ctype_b_loc();\n v9 = v6 + 1;\n while (1) {\n v10 = v8[v7];\n if ((v10 & 1024) == 0) return 0LL;\n if ((v10 & 256) != 0) {\n if ((v10 & 512) != 0) return 0LL;\n v4 = 1;\n } else if ((v10 & 512) != 0) {\n v5 = 1;\n }\n if (v5 + v4 == 2) return 0LL;\n v7 = *v9++;\n if (!v7) goto LABEL_6;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(unsigned char **a1, int a2) {\n long long result;\n unsigned char **v3;\n int v4;\n int v5;\n unsigned char *v6;\n unsigned char v7;\n const unsigned short *v8;\n unsigned char *v9;\n unsigned short v10;\n result = (unsigned int)a2;\n if (a2) {\n if (a2 <= 0) return 1LL;\n v3 = a1;\n v4 = 0;\n v5 = 0;\n while (1) {\n v6 = *v3;\n v7 = **v3;\n if (v7) break;\n LABEL_6:\n v3 += 2;\n if (v3 == &a1[2 * a2]) return 1LL;\n }\n v8 = *__ctype_b_loc();\n v9 = v6 + 1;\n while (1) {\n v10 = v8[v7];\n if ((v10 & 1024) == 0) return 0LL;\n if ((v10 & 256) != 0) {\n if ((v10 & 512) != 0) return 0LL;\n v4 = 1;\n } else if ((v10 & 512) != 0) {\n v5 = 1;\n }\n if (v5 + v4 == 2) return 0LL;\n v7 = *v9++;\n if (!v7) goto LABEL_6;\n }\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-95", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n#include \n", + "func": "int func0(char* dict[][2], int size) {\n if (size == 0) return 0;\n int has_lower = 0, has_upper = 0;\n for (int i = 0; i < size; ++i) {\n char* key = dict[i][0];\n for (int j = 0; key[j]; ++j) {\n if (!isalpha((unsigned char)key[j])) return 0;\n if (isupper((unsigned char)key[j])) has_upper = 1;\n if (islower((unsigned char)key[j])) has_lower = 1;\n if (has_upper + has_lower == 2) return 0;\n }\n }\n return 1;\n}", + "test": "#include \n\nint main() {\n char* test1[][2] = {{\"p\",\"pineapple\"}, {\"b\",\"banana\"}};\n assert(func0(test1, 2) == 1);\n\n char* test2[][2] = {{\"p\",\"pineapple\"}, {\"A\",\"banana\"}, {\"B\",\"banana\"}};\n assert(func0(test2, 3) == 0);\n\n char* test3[][2] = {{\"p\",\"pineapple\"}, {\"5\",\"banana\"}, {\"a\",\"apple\"}};\n assert(func0(test3, 3) == 0);\n\n char* test4[][2] = {{\"Name\",\"John\"}, {\"Age\",\"36\"}, {\"City\",\"Houston\"}};\n assert(func0(test4, 3) == 0);\n\n char* test5[][2] = {{\"STATE\",\"NC\"}, {\"ZIP\",\"12345\"}};\n assert(func0(test5, 2) == 1);\n\n char* test6[][2] = {{\"fruit\",\"Orange\"}, {\"taste\",\"Sweet\"}};\n assert(func0(test6, 2) == 1);\n\n assert(func0(NULL, 0) == 0);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0_part_0:\ntest esi, esi\njle loc_15CA\npush r15\nmovsxd rsi, esi\nmov r15, rdi\npush r14\nshl rsi, 4\nxor r14d, r14d\npush r13\nlea rax, [rdi+rsi]\nxor r13d, r13d\npush r12\nmov r12d, 1\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rax\nloc_1545:\nmov rbp, [r15]\nmovzx ebx, byte ptr [rbp+0]\ntest bl, bl\njz short loc_15B8\ncall ___ctype_b_loc\nlea rdx, [rbp+1]\nmov rsi, [rax]\njmp short loc_1580\nloc_1560:\ntest cx, cx\njnz short loc_15A0\nmov r14d, 1\nloc_156B:\nlea eax, [r13+r14+0]\ncmp eax, 2\njz short loc_15A0\nmovzx ebx, byte ptr [rdx]\nadd rdx, 1\ntest bl, bl\njz short loc_15B8\nloc_1580:\nmovzx eax, word ptr [rsi+rbx*2]\ntest ah, 4\njz short loc_15A0\nmov ecx, eax\nand cx, 200h\ntest ah, 1\njnz short loc_1560\ntest cx, cx\ncmovnz r13d, r12d\njmp short loc_156B\nloc_15A0:\nxor eax, eax\nloc_15A2:\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15B8:\nadd r15, 10h\ncmp [rsp+48h+var_40], r15\njnz short loc_1545\nmov eax, 1\njmp short loc_15A2\nloc_15CA:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0_part_0(unsigned __int8 **a1, int a2)\n{\n unsigned __int8 **v2; // r15\n int v3; // r14d\n int v4; // r13d\n unsigned __int8 *v5; // rbp\n __int64 v6; // rbx\n const unsigned __int16 **v7; // rax\n unsigned __int8 *v8; // rdx\n const unsigned __int16 *v9; // rsi\n unsigned __int16 v10; // ax\n __int16 v11; // cx\n unsigned __int8 **v13; // [rsp+0h] [rbp-40h]\n\n if ( a2 <= 0 )\n return 1LL;\n v2 = a1;\n v3 = 0;\n v4 = 0;\n v13 = &a1[2 * a2];\n while ( 1 )\n {\n v5 = *v2;\n v6 = **v2;\n if ( (_BYTE)v6 )\n break;\nLABEL_16:\n v2 += 2;\n if ( v13 == v2 )\n return 1LL;\n }\n v7 = __ctype_b_loc();\n v8 = v5 + 1;\n v9 = *v7;\n while ( 1 )\n {\n v10 = v9[v6];\n if ( (v10 & 0x400) == 0 )\n return 0LL;\n v11 = v10 & 0x200;\n if ( (v10 & 0x100) != 0 )\n {\n if ( v11 )\n return 0LL;\n v3 = 1;\n }\n else if ( v11 )\n {\n v4 = 1;\n }\n if ( v4 + v3 == 2 )\n return 0LL;\n v6 = *v8++;\n if ( !(_BYTE)v6 )\n goto LABEL_16;\n }\n}", + "ida_strip_asm": "sub_1510:\ntest esi, esi\njle loc_15CA\npush r15\nmovsxd rsi, esi\nmov r15, rdi\npush r14\nshl rsi, 4\nxor r14d, r14d\npush r13\nlea rax, [rdi+rsi]\nxor r13d, r13d\npush r12\nmov r12d, 1\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rax\nloc_1545:\nmov rbp, [r15]\nmovzx ebx, byte ptr [rbp+0]\ntest bl, bl\njz short loc_15B8\ncall ___ctype_b_loc\nlea rdx, [rbp+1]\nmov rsi, [rax]\njmp short loc_1580\nloc_1560:\ntest cx, cx\njnz short loc_15A0\nmov r14d, 1\nloc_156B:\nlea eax, [r13+r14+0]\ncmp eax, 2\njz short loc_15A0\nmovzx ebx, byte ptr [rdx]\nadd rdx, 1\ntest bl, bl\njz short loc_15B8\nloc_1580:\nmovzx eax, word ptr [rsi+rbx*2]\ntest ah, 4\njz short loc_15A0\nmov ecx, eax\nand cx, 200h\ntest ah, 1\njnz short loc_1560\ntest cx, cx\ncmovnz r13d, r12d\njmp short loc_156B\nloc_15A0:\nxor eax, eax\nloc_15A2:\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15B8:\nadd r15, 10h\ncmp [rsp+48h+var_40], r15\njnz short loc_1545\nmov eax, 1\njmp short loc_15A2\nloc_15CA:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1510(unsigned __int8 **a1, int a2)\n{\n unsigned __int8 **v2; // r15\n int v3; // r14d\n int v4; // r13d\n unsigned __int8 *v5; // rbp\n __int64 v6; // rbx\n const unsigned __int16 **v7; // rax\n unsigned __int8 *v8; // rdx\n const unsigned __int16 *v9; // rsi\n unsigned __int16 v10; // ax\n __int16 v11; // cx\n unsigned __int8 **v13; // [rsp+0h] [rbp-40h]\n\n if ( a2 <= 0 )\n return 1LL;\n v2 = a1;\n v3 = 0;\n v4 = 0;\n v13 = &a1[2 * a2];\n while ( 1 )\n {\n v5 = *v2;\n v6 = **v2;\n if ( (_BYTE)v6 )\n break;\nLABEL_16:\n v2 += 2;\n if ( v13 == v2 )\n return 1LL;\n }\n v7 = __ctype_b_loc();\n v8 = v5 + 1;\n v9 = *v7;\n while ( 1 )\n {\n v10 = v9[v6];\n if ( (v10 & 0x400) == 0 )\n return 0LL;\n v11 = v10 & 0x200;\n if ( (v10 & 0x100) != 0 )\n {\n if ( v11 )\n return 0LL;\n v3 = 1;\n }\n else if ( v11 )\n {\n v4 = 1;\n }\n if ( v4 + v3 == 2 )\n return 0LL;\n v6 = *v8++;\n if ( !(_BYTE)v6 )\n goto LABEL_16;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1510(unsigned char **a1, int a2) {\n unsigned char **v2;\n int v3;\n int v4;\n unsigned char *v5;\n long long v6;\n const unsigned short **v7;\n unsigned char *v8;\n const unsigned short *v9;\n unsigned short v10;\n short v11;\n unsigned char **v13;\n if (a2 <= 0) return 1LL;\n v2 = a1;\n v3 = 0;\n v4 = 0;\n v13 = &a1[2 * a2];\n while (1) {\n v5 = *v2;\n v6 = **v2;\n if ((uint8_t)v6) break;\n LABEL_16:\n v2 += 2;\n if (v13 == v2) return 1LL;\n }\n v7 = __ctype_b_loc();\n v8 = v5 + 1;\n v9 = *v7;\n while (1) {\n v10 = v9[v6];\n if ((v10 & 1024) == 0) return 0LL;\n v11 = v10 & 512;\n if ((v10 & 256) != 0) {\n if (v11) return 0LL;\n v3 = 1;\n } else if (v11) {\n v4 = 1;\n }\n if (v4 + v3 == 2) return 0LL;\n v6 = *v8++;\n if (!(uint8_t)v6) goto LABEL_16;\n }\n}", + "ida_pseudo_norm": "long long func0_part_0(unsigned char **a1, int a2) {\n unsigned char **v2;\n int v3;\n int v4;\n unsigned char *v5;\n long long v6;\n const unsigned short **v7;\n unsigned char *v8;\n const unsigned short *v9;\n unsigned short v10;\n short v11;\n unsigned char **v13;\n if (a2 <= 0) return 1LL;\n v2 = a1;\n v3 = 0;\n v4 = 0;\n v13 = &a1[2 * a2];\n while (1) {\n v5 = *v2;\n v6 = **v2;\n if ((uint8_t)v6) break;\n LABEL_16:\n v2 += 2;\n if (v13 == v2) return 1LL;\n }\n v7 = __ctype_b_loc();\n v8 = v5 + 1;\n v9 = *v7;\n while (1) {\n v10 = v9[v6];\n if ((v10 & 1024) == 0) return 0LL;\n v11 = v10 & 512;\n if ((v10 & 256) != 0) {\n if (v11) return 0LL;\n v3 = 1;\n } else if (v11) {\n v4 = 1;\n }\n if (v4 + v3 == 2) return 0LL;\n v6 = *v8++;\n if (!(uint8_t)v6) goto LABEL_16;\n }\n}" + }, + { + "index": "HumanEval-C-95", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n#include \n", + "func": "int func0(char* dict[][2], int size) {\n if (size == 0) return 0;\n int has_lower = 0, has_upper = 0;\n for (int i = 0; i < size; ++i) {\n char* key = dict[i][0];\n for (int j = 0; key[j]; ++j) {\n if (!isalpha((unsigned char)key[j])) return 0;\n if (isupper((unsigned char)key[j])) has_upper = 1;\n if (islower((unsigned char)key[j])) has_lower = 1;\n if (has_upper + has_lower == 2) return 0;\n }\n }\n return 1;\n}", + "test": "#include \n\nint main() {\n char* test1[][2] = {{\"p\",\"pineapple\"}, {\"b\",\"banana\"}};\n assert(func0(test1, 2) == 1);\n\n char* test2[][2] = {{\"p\",\"pineapple\"}, {\"A\",\"banana\"}, {\"B\",\"banana\"}};\n assert(func0(test2, 3) == 0);\n\n char* test3[][2] = {{\"p\",\"pineapple\"}, {\"5\",\"banana\"}, {\"a\",\"apple\"}};\n assert(func0(test3, 3) == 0);\n\n char* test4[][2] = {{\"Name\",\"John\"}, {\"Age\",\"36\"}, {\"City\",\"Houston\"}};\n assert(func0(test4, 3) == 0);\n\n char* test5[][2] = {{\"STATE\",\"NC\"}, {\"ZIP\",\"12345\"}};\n assert(func0(test5, 2) == 1);\n\n char* test6[][2] = {{\"fruit\",\"Orange\"}, {\"taste\",\"Sweet\"}};\n assert(func0(test6, 2) == 1);\n\n assert(func0(NULL, 0) == 0);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0_part_0:\ntest esi, esi\njle loc_15CA\npush r15\nmovsxd rsi, esi\nmov r15, rdi\npush r14\nshl rsi, 4\nxor r14d, r14d\npush r13\nlea rax, [rdi+rsi]\nxor r13d, r13d\npush r12\nmov r12d, 1\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rax\nloc_1545:\nmov rbp, [r15]\nmovzx ebx, byte ptr [rbp+0]\ntest bl, bl\njz short loc_15B8\ncall ___ctype_b_loc\nlea rdx, [rbp+1]\nmov rsi, [rax]\njmp short loc_1580\nloc_1560:\ntest cx, cx\njnz short loc_15A0\nmov r14d, 1\nloc_156B:\nlea eax, [r13+r14+0]\ncmp eax, 2\njz short loc_15A0\nmovzx ebx, byte ptr [rdx]\nadd rdx, 1\ntest bl, bl\njz short loc_15B8\nloc_1580:\nmovzx eax, word ptr [rsi+rbx*2]\ntest ah, 4\njz short loc_15A0\nmov ecx, eax\nand cx, 200h\ntest ah, 1\njnz short loc_1560\ntest cx, cx\ncmovnz r13d, r12d\njmp short loc_156B\nloc_15A0:\nxor eax, eax\nloc_15A2:\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15B8:\nadd r15, 10h\ncmp [rsp+48h+var_40], r15\njnz short loc_1545\nmov eax, 1\njmp short loc_15A2\nloc_15CA:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0_part_0(unsigned __int8 **a1, int a2)\n{\n unsigned __int8 **v2; // r15\n int v3; // r14d\n int v4; // r13d\n unsigned __int8 *v5; // rbp\n __int64 v6; // rbx\n const unsigned __int16 **v7; // rax\n unsigned __int8 *v8; // rdx\n const unsigned __int16 *v9; // rsi\n unsigned __int16 v10; // ax\n __int16 v11; // cx\n unsigned __int8 **v13; // [rsp+0h] [rbp-40h]\n\n if ( a2 <= 0 )\n return 1LL;\n v2 = a1;\n v3 = 0;\n v4 = 0;\n v13 = &a1[2 * a2];\n while ( 1 )\n {\n v5 = *v2;\n v6 = **v2;\n if ( (_BYTE)v6 )\n break;\nLABEL_16:\n v2 += 2;\n if ( v13 == v2 )\n return 1LL;\n }\n v7 = __ctype_b_loc();\n v8 = v5 + 1;\n v9 = *v7;\n while ( 1 )\n {\n v10 = v9[v6];\n if ( (v10 & 0x400) == 0 )\n return 0LL;\n v11 = v10 & 0x200;\n if ( (v10 & 0x100) != 0 )\n {\n if ( v11 )\n return 0LL;\n v3 = 1;\n }\n else if ( v11 )\n {\n v4 = 1;\n }\n if ( v4 + v3 == 2 )\n return 0LL;\n v6 = *v8++;\n if ( !(_BYTE)v6 )\n goto LABEL_16;\n }\n}", + "ida_strip_asm": "sub_1510:\ntest esi, esi\njle loc_15CA\npush r15\nmovsxd rsi, esi\nmov r15, rdi\npush r14\nshl rsi, 4\nxor r14d, r14d\npush r13\nlea rax, [rdi+rsi]\nxor r13d, r13d\npush r12\nmov r12d, 1\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rax\nloc_1545:\nmov rbp, [r15]\nmovzx ebx, byte ptr [rbp+0]\ntest bl, bl\njz short loc_15B8\ncall ___ctype_b_loc\nlea rdx, [rbp+1]\nmov rsi, [rax]\njmp short loc_1580\nloc_1560:\ntest cx, cx\njnz short loc_15A0\nmov r14d, 1\nloc_156B:\nlea eax, [r13+r14+0]\ncmp eax, 2\njz short loc_15A0\nmovzx ebx, byte ptr [rdx]\nadd rdx, 1\ntest bl, bl\njz short loc_15B8\nloc_1580:\nmovzx eax, word ptr [rsi+rbx*2]\ntest ah, 4\njz short loc_15A0\nmov ecx, eax\nand cx, 200h\ntest ah, 1\njnz short loc_1560\ntest cx, cx\ncmovnz r13d, r12d\njmp short loc_156B\nloc_15A0:\nxor eax, eax\nloc_15A2:\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15B8:\nadd r15, 10h\ncmp [rsp+48h+var_40], r15\njnz short loc_1545\nmov eax, 1\njmp short loc_15A2\nloc_15CA:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1510(unsigned __int8 **a1, int a2)\n{\n unsigned __int8 **v2; // r15\n int v3; // r14d\n int v4; // r13d\n unsigned __int8 *v5; // rbp\n __int64 v6; // rbx\n const unsigned __int16 **v7; // rax\n unsigned __int8 *v8; // rdx\n const unsigned __int16 *v9; // rsi\n unsigned __int16 v10; // ax\n __int16 v11; // cx\n unsigned __int8 **v13; // [rsp+0h] [rbp-40h]\n\n if ( a2 <= 0 )\n return 1LL;\n v2 = a1;\n v3 = 0;\n v4 = 0;\n v13 = &a1[2 * a2];\n while ( 1 )\n {\n v5 = *v2;\n v6 = **v2;\n if ( (_BYTE)v6 )\n break;\nLABEL_16:\n v2 += 2;\n if ( v13 == v2 )\n return 1LL;\n }\n v7 = __ctype_b_loc();\n v8 = v5 + 1;\n v9 = *v7;\n while ( 1 )\n {\n v10 = v9[v6];\n if ( (v10 & 0x400) == 0 )\n return 0LL;\n v11 = v10 & 0x200;\n if ( (v10 & 0x100) != 0 )\n {\n if ( v11 )\n return 0LL;\n v3 = 1;\n }\n else if ( v11 )\n {\n v4 = 1;\n }\n if ( v4 + v3 == 2 )\n return 0LL;\n v6 = *v8++;\n if ( !(_BYTE)v6 )\n goto LABEL_16;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1510(unsigned char **a1, int a2) {\n unsigned char **v2;\n int v3;\n int v4;\n unsigned char *v5;\n long long v6;\n const unsigned short **v7;\n unsigned char *v8;\n const unsigned short *v9;\n unsigned short v10;\n short v11;\n unsigned char **v13;\n if (a2 <= 0) return 1LL;\n v2 = a1;\n v3 = 0;\n v4 = 0;\n v13 = &a1[2 * a2];\n while (1) {\n v5 = *v2;\n v6 = **v2;\n if ((uint8_t)v6) break;\n LABEL_16:\n v2 += 2;\n if (v13 == v2) return 1LL;\n }\n v7 = __ctype_b_loc();\n v8 = v5 + 1;\n v9 = *v7;\n while (1) {\n v10 = v9[v6];\n if ((v10 & 1024) == 0) return 0LL;\n v11 = v10 & 512;\n if ((v10 & 256) != 0) {\n if (v11) return 0LL;\n v3 = 1;\n } else if (v11) {\n v4 = 1;\n }\n if (v4 + v3 == 2) return 0LL;\n v6 = *v8++;\n if (!(uint8_t)v6) goto LABEL_16;\n }\n}", + "ida_pseudo_norm": "long long func0_part_0(unsigned char **a1, int a2) {\n unsigned char **v2;\n int v3;\n int v4;\n unsigned char *v5;\n long long v6;\n const unsigned short **v7;\n unsigned char *v8;\n const unsigned short *v9;\n unsigned short v10;\n short v11;\n unsigned char **v13;\n if (a2 <= 0) return 1LL;\n v2 = a1;\n v3 = 0;\n v4 = 0;\n v13 = &a1[2 * a2];\n while (1) {\n v5 = *v2;\n v6 = **v2;\n if ((uint8_t)v6) break;\n LABEL_16:\n v2 += 2;\n if (v13 == v2) return 1LL;\n }\n v7 = __ctype_b_loc();\n v8 = v5 + 1;\n v9 = *v7;\n while (1) {\n v10 = v9[v6];\n if ((v10 & 1024) == 0) return 0LL;\n v11 = v10 & 512;\n if ((v10 & 256) != 0) {\n if (v11) return 0LL;\n v3 = 1;\n } else if (v11) {\n v4 = 1;\n }\n if (v4 + v3 == 2) return 0LL;\n v6 = *v8++;\n if (!(uint8_t)v6) goto LABEL_16;\n }\n}" + }, + { + "index": "HumanEval-C-96", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int *func0(int n, int *count) {\n int *out = malloc(n * sizeof(int));\n *count = 0;\n int i, j, isp, k;\n for (i = 2; i < n; i++) {\n isp = 1;\n for (j = 0; j < *count; j++) {\n k = out[j];\n if (k * k > i) break;\n if (i % k == 0) {\n isp = 0;\n break;\n }\n }\n if (isp) {\n out[*count] = i;\n (*count)++;\n }\n }\n return out;\n}", + "test": "#include \n#include \n\nint issame(int *a, int a_count, int *b, int b_count) {\n if (a_count != b_count) return 0;\n for (int i = 0; i < a_count; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int count;\n int expected[] = {2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53, 59, 61, 67, 71, 73, 79, 83, 89, 97};\n\n int *result = func0(5, &count);\n assert(issame(result, count, (const int[]){2, 3}, 2));\n free(result);\n\n result = func0(6, &count);\n assert(issame(result, count, (const int[]){2, 3, 5}, 3));\n free(result);\n\n result = func0(7, &count);\n assert(issame(result, count, (const int[]){2, 3, 5}, 3));\n free(result);\n\n result = func0(10, &count);\n assert(issame(result, count, (const int[]){2, 3, 5, 7}, 4));\n free(result);\n\n result = func0(0, &count);\n assert(count == 0);\n free(result);\n\n result = func0(22, &count);\n assert(issame(result, count, (const int[]){2, 3, 5, 7, 11, 13, 17, 19}, 8));\n free(result);\n\n result = func0(1, &count);\n assert(count == 0);\n free(result);\n\n result = func0(18, &count);\n assert(issame(result, count, (const int[]){2, 3, 5, 7, 11, 13, 17}, 7));\n free(result);\n\n result = func0(47, &count);\n assert(issame(result, count, (const int[]){2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43}, 14));\n free(result);\n\n result = func0(101, &count);\n assert(issame(result, count, expected, 25));\n free(result);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_24], edi\nmov [rbp+var_30], rsi\nmov eax, [rbp+var_24]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov rax, [rbp+var_30]\nmov dword ptr [rax], 0\nmov [rbp+var_18], 2\njmp loc_1278\nloc_11E7:\nmov [rbp+var_10], 1\nmov [rbp+var_14], 0\njmp short loc_1235\nloc_11F7:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nmov eax, [rbp+var_C]\nimul eax, eax\ncmp [rbp+var_18], eax\njl short loc_1242\nmov eax, [rbp+var_18]\ncdq\nidiv [rbp+var_C]\nmov eax, edx\ntest eax, eax\njnz short loc_1231\nmov [rbp+var_10], 0\njmp short loc_1243\nloc_1231:\nadd [rbp+var_14], 1\nloc_1235:\nmov rax, [rbp+var_30]\nmov eax, [rax]\ncmp [rbp+var_14], eax\njl short loc_11F7\njmp short loc_1243\nloc_1242:\nnop\nloc_1243:\ncmp [rbp+var_10], 0\njz short loc_1274\nmov rax, [rbp+var_30]\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_18]\nmov [rdx], eax\nmov rax, [rbp+var_30]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_30]\nmov [rax], edx\nloc_1274:\nadd [rbp+var_18], 1\nloc_1278:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_24]\njl loc_11E7\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int a1, _DWORD *a2)\n{\n int i; // [rsp+18h] [rbp-18h]\n int j; // [rsp+1Ch] [rbp-14h]\n int v5; // [rsp+20h] [rbp-10h]\n int v6; // [rsp+24h] [rbp-Ch]\n _DWORD *v7; // [rsp+28h] [rbp-8h]\n\n v7 = malloc(4LL * a1);\n *a2 = 0;\n for ( i = 2; i < a1; ++i )\n {\n v5 = 1;\n for ( j = 0; j < *a2; ++j )\n {\n v6 = v7[j];\n if ( i < v6 * v6 )\n break;\n if ( !(i % v6) )\n {\n v5 = 0;\n break;\n }\n }\n if ( v5 )\n v7[(*a2)++] = i;\n }\n return v7;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_24], edi\nmov [rbp+var_30], rsi\nmov eax, [rbp+var_24]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov rax, [rbp+var_30]\nmov dword ptr [rax], 0\nmov [rbp+var_18], 2\njmp loc_1278\nloc_11E7:\nmov [rbp+var_10], 1\nmov [rbp+var_14], 0\njmp short loc_1235\nloc_11F7:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nmov eax, [rbp+var_C]\nimul eax, eax\ncmp [rbp+var_18], eax\njl short loc_1242\nmov eax, [rbp+var_18]\ncdq\nidiv [rbp+var_C]\nmov eax, edx\ntest eax, eax\njnz short loc_1231\nmov [rbp+var_10], 0\njmp short loc_1243\nloc_1231:\nadd [rbp+var_14], 1\nloc_1235:\nmov rax, [rbp+var_30]\nmov eax, [rax]\ncmp [rbp+var_14], eax\njl short loc_11F7\njmp short loc_1243\nloc_1242:\nnop\nloc_1243:\ncmp [rbp+var_10], 0\njz short loc_1274\nmov rax, [rbp+var_30]\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_18]\nmov [rdx], eax\nmov rax, [rbp+var_30]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_30]\nmov [rax], edx\nloc_1274:\nadd [rbp+var_18], 1\nloc_1278:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_24]\njl loc_11E7\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(int a1, _DWORD *a2)\n{\n int i; // [rsp+18h] [rbp-18h]\n int j; // [rsp+1Ch] [rbp-14h]\n int v5; // [rsp+20h] [rbp-10h]\n int v6; // [rsp+24h] [rbp-Ch]\n _DWORD *v7; // [rsp+28h] [rbp-8h]\n\n v7 = malloc(4LL * a1);\n *a2 = 0;\n for ( i = 2; i < a1; ++i )\n {\n v5 = 1;\n for ( j = 0; j < *a2; ++j )\n {\n v6 = v7[j];\n if ( i < v6 * v6 )\n break;\n if ( !(i % v6) )\n {\n v5 = 0;\n break;\n }\n }\n if ( v5 )\n v7[(*a2)++] = i;\n }\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(int a1, uint32_t *a2) {\n int i;\n int j;\n int v5;\n int v6;\n uint32_t *v7;\n v7 = malloc(4LL * a1);\n *a2 = 0;\n for (i = 2; i < a1; ++i) {\n v5 = 1;\n for (j = 0; j < *a2; ++j) {\n v6 = v7[j];\n if (i < v6 * v6) break;\n if (!(i % v6)) {\n v5 = 0;\n break;\n }\n }\n if (v5) v7[(*a2)++] = i;\n }\n return v7;\n}", + "ida_pseudo_norm": "uint32_t *func0(int a1, uint32_t *a2) {\n int i;\n int j;\n int v5;\n int v6;\n uint32_t *v7;\n v7 = malloc(4LL * a1);\n *a2 = 0;\n for (i = 2; i < a1; ++i) {\n v5 = 1;\n for (j = 0; j < *a2; ++j) {\n v6 = v7[j];\n if (i < v6 * v6) break;\n if (!(i % v6)) {\n v5 = 0;\n break;\n }\n }\n if (v5) v7[(*a2)++] = i;\n }\n return v7;\n}" + }, + { + "index": "HumanEval-C-96", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int *func0(int n, int *count) {\n int *out = malloc(n * sizeof(int));\n *count = 0;\n int i, j, isp, k;\n for (i = 2; i < n; i++) {\n isp = 1;\n for (j = 0; j < *count; j++) {\n k = out[j];\n if (k * k > i) break;\n if (i % k == 0) {\n isp = 0;\n break;\n }\n }\n if (isp) {\n out[*count] = i;\n (*count)++;\n }\n }\n return out;\n}", + "test": "#include \n#include \n\nint issame(int *a, int a_count, int *b, int b_count) {\n if (a_count != b_count) return 0;\n for (int i = 0; i < a_count; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int count;\n int expected[] = {2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53, 59, 61, 67, 71, 73, 79, 83, 89, 97};\n\n int *result = func0(5, &count);\n assert(issame(result, count, (const int[]){2, 3}, 2));\n free(result);\n\n result = func0(6, &count);\n assert(issame(result, count, (const int[]){2, 3, 5}, 3));\n free(result);\n\n result = func0(7, &count);\n assert(issame(result, count, (const int[]){2, 3, 5}, 3));\n free(result);\n\n result = func0(10, &count);\n assert(issame(result, count, (const int[]){2, 3, 5, 7}, 4));\n free(result);\n\n result = func0(0, &count);\n assert(count == 0);\n free(result);\n\n result = func0(22, &count);\n assert(issame(result, count, (const int[]){2, 3, 5, 7, 11, 13, 17, 19}, 8));\n free(result);\n\n result = func0(1, &count);\n assert(count == 0);\n free(result);\n\n result = func0(18, &count);\n assert(issame(result, count, (const int[]){2, 3, 5, 7, 11, 13, 17}, 7));\n free(result);\n\n result = func0(47, &count);\n assert(issame(result, count, (const int[]){2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43}, 14));\n free(result);\n\n result = func0(101, &count);\n assert(issame(result, count, expected, 25));\n free(result);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov ebp, edi\nmov rbx, rsi\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov r10, rax\nmov dword ptr [rbx], 0\nmov edi, 2\ncmp ebp, 2\njg short loc_11F6\nloc_11D7:\nmov rax, r10\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_11E1:\nmovsxd rax, r9d\nmov [r10+rax*4], edi\nadd r9d, 1\nmov [rbx], r9d\nloc_11EF:\nadd edi, 1\ncmp ebp, edi\njz short loc_11D7\nloc_11F6:\nmov r9d, [rbx]\ntest r9d, r9d\njle short loc_11E1\nmov rsi, r10\nmovsxd rax, r9d\nlea r8, [r10+rax*4]\nloc_1208:\nmov ecx, [rsi]\nmov eax, ecx\nimul eax, ecx\ncmp eax, edi\njg short loc_11E1\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njz short loc_11EF\nadd rsi, 4\ncmp r8, rsi\njnz short loc_1208\njmp short loc_11E1", + "ida_pseudo": "int *__fastcall func0(int a1, int *a2)\n{\n int *v4; // r10\n int v5; // edi\n int v7; // r9d\n int *v8; // rsi\n int v9; // ecx\n\n v4 = (int *)malloc(4LL * a1);\n *a2 = 0;\n v5 = 2;\n if ( a1 > 2 )\n {\n do\n {\n v7 = *a2;\n if ( *a2 > 0 )\n {\n v8 = v4;\n do\n {\n v9 = *v8;\n if ( v9 * v9 > v5 )\n break;\n if ( !(v5 % v9) )\n goto LABEL_4;\n ++v8;\n }\n while ( &v4[v7] != v8 );\n }\n v4[v7] = v5;\n *a2 = v7 + 1;\nLABEL_4:\n ++v5;\n }\n while ( a1 != v5 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov ebp, edi\nmov rbx, rsi\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov r10, rax\nmov dword ptr [rbx], 0\nmov edi, 2\ncmp ebp, 2\njg short loc_11F6\nloc_11D7:\nmov rax, r10\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_11E1:\nmovsxd rax, r9d\nmov [r10+rax*4], edi\nadd r9d, 1\nmov [rbx], r9d\nloc_11EF:\nadd edi, 1\ncmp ebp, edi\njz short loc_11D7\nloc_11F6:\nmov r9d, [rbx]\ntest r9d, r9d\njle short loc_11E1\nmov rsi, r10\nmovsxd rax, r9d\nlea r8, [r10+rax*4]\nloc_1208:\nmov ecx, [rsi]\nmov eax, ecx\nimul eax, ecx\ncmp eax, edi\njg short loc_11E1\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njz short loc_11EF\nadd rsi, 4\ncmp r8, rsi\njnz short loc_1208\njmp short loc_11E1", + "ida_strip_pseudo": "int *__fastcall sub_11A9(int a1, int *a2)\n{\n int *v4; // r10\n int v5; // edi\n int v7; // r9d\n int *v8; // rsi\n int v9; // ecx\n\n v4 = (int *)malloc(4LL * a1);\n *a2 = 0;\n v5 = 2;\n if ( a1 > 2 )\n {\n do\n {\n v7 = *a2;\n if ( *a2 > 0 )\n {\n v8 = v4;\n do\n {\n v9 = *v8;\n if ( v9 * v9 > v5 )\n break;\n if ( !(v5 % v9) )\n goto LABEL_4;\n ++v8;\n }\n while ( &v4[v7] != v8 );\n }\n v4[v7] = v5;\n *a2 = v7 + 1;\nLABEL_4:\n ++v5;\n }\n while ( a1 != v5 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "int *sub_11A9(int a1, int *a2) {\n int *v4;\n int v5;\n int v7;\n int *v8;\n int v9;\n v4 = (int *)malloc(4LL * a1);\n *a2 = 0;\n v5 = 2;\n if (a1 > 2) {\n do {\n v7 = *a2;\n if (*a2 > 0) {\n v8 = v4;\n do {\n v9 = *v8;\n if (v9 * v9 > v5) break;\n if (!(v5 % v9)) goto LABEL_4;\n ++v8;\n } while (&v4[v7] != v8);\n }\n v4[v7] = v5;\n *a2 = v7 + 1;\n LABEL_4:\n ++v5;\n } while (a1 != v5);\n }\n return v4;\n}", + "ida_pseudo_norm": "int *func0(int a1, int *a2) {\n int *v4;\n int v5;\n int v7;\n int *v8;\n int v9;\n v4 = (int *)malloc(4LL * a1);\n *a2 = 0;\n v5 = 2;\n if (a1 > 2) {\n do {\n v7 = *a2;\n if (*a2 > 0) {\n v8 = v4;\n do {\n v9 = *v8;\n if (v9 * v9 > v5) break;\n if (!(v5 % v9)) goto LABEL_4;\n ++v8;\n } while (&v4[v7] != v8);\n }\n v4[v7] = v5;\n *a2 = v7 + 1;\n LABEL_4:\n ++v5;\n } while (a1 != v5);\n }\n return v4;\n}" + }, + { + "index": "HumanEval-C-96", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int *func0(int n, int *count) {\n int *out = malloc(n * sizeof(int));\n *count = 0;\n int i, j, isp, k;\n for (i = 2; i < n; i++) {\n isp = 1;\n for (j = 0; j < *count; j++) {\n k = out[j];\n if (k * k > i) break;\n if (i % k == 0) {\n isp = 0;\n break;\n }\n }\n if (isp) {\n out[*count] = i;\n (*count)++;\n }\n }\n return out;\n}", + "test": "#include \n#include \n\nint issame(int *a, int a_count, int *b, int b_count) {\n if (a_count != b_count) return 0;\n for (int i = 0; i < a_count; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int count;\n int expected[] = {2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53, 59, 61, 67, 71, 73, 79, 83, 89, 97};\n\n int *result = func0(5, &count);\n assert(issame(result, count, (const int[]){2, 3}, 2));\n free(result);\n\n result = func0(6, &count);\n assert(issame(result, count, (const int[]){2, 3, 5}, 3));\n free(result);\n\n result = func0(7, &count);\n assert(issame(result, count, (const int[]){2, 3, 5}, 3));\n free(result);\n\n result = func0(10, &count);\n assert(issame(result, count, (const int[]){2, 3, 5, 7}, 4));\n free(result);\n\n result = func0(0, &count);\n assert(count == 0);\n free(result);\n\n result = func0(22, &count);\n assert(issame(result, count, (const int[]){2, 3, 5, 7, 11, 13, 17, 19}, 8));\n free(result);\n\n result = func0(1, &count);\n assert(count == 0);\n free(result);\n\n result = func0(18, &count);\n assert(issame(result, count, (const int[]){2, 3, 5, 7, 11, 13, 17}, 7));\n free(result);\n\n result = func0(47, &count);\n assert(issame(result, count, (const int[]){2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43}, 14));\n free(result);\n\n result = func0(101, &count);\n assert(issame(result, count, expected, 25));\n free(result);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmovsxd rdi, edi\nmov rbp, rsi\npush rbx\nmov rbx, rdi\nshl rdi, 2; size\nsub rsp, 8\ncall _malloc\nmov dword ptr [rbp+0], 0\nxor r9d, r9d\nmov edi, 2\nmov r10, rax\ncmp ebx, 2\njle short loc_1700\nnop dword ptr [rax+rax+00h]\nloc_16A8:\nmovsxd r11, r9d\ntest r9d, r9d\njle short loc_16DD\nmovsxd r11, r9d\nmov rsi, r10\nlea r8, [r10+r11*4]\njmp short loc_16D2\nloc_16C0:\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njz short loc_16E9\nadd rsi, 4\ncmp rsi, r8\njz short loc_16DD\nloc_16D2:\nmov ecx, [rsi]\nmov eax, ecx\nimul eax, ecx\ncmp eax, edi\njle short loc_16C0\nloc_16DD:\nadd r9d, 1\nmov [r10+r11*4], edi\nmov [rbp+0], r9d\nloc_16E9:\nadd edi, 1\ncmp ebx, edi\njz short loc_1700\nmov r9d, [rbp+0]\njmp short loc_16A8\nloc_1700:\nadd rsp, 8\nmov rax, r10\npop rbx\npop rbp\nretn", + "ida_pseudo": "int *__fastcall func0(int a1, int *a2)\n{\n int *result; // rax\n int v5; // r9d\n int v6; // edi\n __int64 v7; // r11\n int *v8; // rsi\n int v9; // ecx\n\n result = (int *)malloc(4LL * a1);\n *a2 = 0;\n v5 = 0;\n v6 = 2;\n if ( a1 > 2 )\n {\n while ( 1 )\n {\n v7 = v5;\n if ( v5 > 0 )\n {\n v7 = v5;\n v8 = result;\n do\n {\n v9 = *v8;\n if ( v9 * v9 > v6 )\n break;\n if ( !(v6 % v9) )\n goto LABEL_8;\n ++v8;\n }\n while ( v8 != &result[v5] );\n }\n result[v7] = v6;\n *a2 = v5 + 1;\nLABEL_8:\n if ( a1 == ++v6 )\n break;\n v5 = *a2;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1670:\nendbr64\npush rbp\nmovsxd rdi, edi\nmov rbp, rsi\npush rbx\nmov rbx, rdi\nshl rdi, 2; size\nsub rsp, 8\ncall _malloc\nmov dword ptr [rbp+0], 0\nxor r9d, r9d\nmov edi, 2\nmov r10, rax\ncmp ebx, 2\njle short loc_1700\nnop dword ptr [rax+rax+00h]\nloc_16A8:\nmovsxd r11, r9d\ntest r9d, r9d\njle short loc_16DD\nmovsxd r11, r9d\nmov rsi, r10\nlea r8, [r10+r11*4]\njmp short loc_16D2\nloc_16C0:\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njz short loc_16E9\nadd rsi, 4\ncmp rsi, r8\njz short loc_16DD\nloc_16D2:\nmov ecx, [rsi]\nmov eax, ecx\nimul eax, ecx\ncmp eax, edi\njle short loc_16C0\nloc_16DD:\nadd r9d, 1\nmov [r10+r11*4], edi\nmov [rbp+0], r9d\nloc_16E9:\nadd edi, 1\ncmp ebx, edi\njz short loc_1700\nmov r9d, [rbp+0]\njmp short loc_16A8\nloc_1700:\nadd rsp, 8\nmov rax, r10\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "int *__fastcall sub_1670(int a1, int *a2)\n{\n int *result; // rax\n int v5; // r9d\n int v6; // edi\n __int64 v7; // r11\n int *v8; // rsi\n int v9; // ecx\n\n result = (int *)malloc(4LL * a1);\n *a2 = 0;\n v5 = 0;\n v6 = 2;\n if ( a1 > 2 )\n {\n while ( 1 )\n {\n v7 = v5;\n if ( v5 > 0 )\n {\n v7 = v5;\n v8 = result;\n do\n {\n v9 = *v8;\n if ( v9 * v9 > v6 )\n break;\n if ( !(v6 % v9) )\n goto LABEL_8;\n ++v8;\n }\n while ( v8 != &result[v5] );\n }\n result[v7] = v6;\n *a2 = v5 + 1;\nLABEL_8:\n if ( a1 == ++v6 )\n break;\n v5 = *a2;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "int *sub_1670(int a1, int *a2) {\n int *result;\n int v5;\n int v6;\n long long v7;\n int *v8;\n int v9;\n result = (int *)malloc(4LL * a1);\n *a2 = 0;\n v5 = 0;\n v6 = 2;\n if (a1 > 2) {\n while (1) {\n v7 = v5;\n if (v5 > 0) {\n v7 = v5;\n v8 = result;\n do {\n v9 = *v8;\n if (v9 * v9 > v6) break;\n if (!(v6 % v9)) goto LABEL_8;\n ++v8;\n } while (v8 != &result[v5]);\n }\n result[v7] = v6;\n *a2 = v5 + 1;\n LABEL_8:\n if (a1 == ++v6) break;\n v5 = *a2;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "int *func0(int a1, int *a2) {\n int *result;\n int v5;\n int v6;\n long long v7;\n int *v8;\n int v9;\n result = (int *)malloc(4LL * a1);\n *a2 = 0;\n v5 = 0;\n v6 = 2;\n if (a1 > 2) {\n while (1) {\n v7 = v5;\n if (v5 > 0) {\n v7 = v5;\n v8 = result;\n do {\n v9 = *v8;\n if (v9 * v9 > v6) break;\n if (!(v6 % v9)) goto LABEL_8;\n ++v8;\n } while (v8 != &result[v5]);\n }\n result[v7] = v6;\n *a2 = v5 + 1;\n LABEL_8:\n if (a1 == ++v6) break;\n v5 = *a2;\n }\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-96", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int *func0(int n, int *count) {\n int *out = malloc(n * sizeof(int));\n *count = 0;\n int i, j, isp, k;\n for (i = 2; i < n; i++) {\n isp = 1;\n for (j = 0; j < *count; j++) {\n k = out[j];\n if (k * k > i) break;\n if (i % k == 0) {\n isp = 0;\n break;\n }\n }\n if (isp) {\n out[*count] = i;\n (*count)++;\n }\n }\n return out;\n}", + "test": "#include \n#include \n\nint issame(int *a, int a_count, int *b, int b_count) {\n if (a_count != b_count) return 0;\n for (int i = 0; i < a_count; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int count;\n int expected[] = {2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53, 59, 61, 67, 71, 73, 79, 83, 89, 97};\n\n int *result = func0(5, &count);\n assert(issame(result, count, (const int[]){2, 3}, 2));\n free(result);\n\n result = func0(6, &count);\n assert(issame(result, count, (const int[]){2, 3, 5}, 3));\n free(result);\n\n result = func0(7, &count);\n assert(issame(result, count, (const int[]){2, 3, 5}, 3));\n free(result);\n\n result = func0(10, &count);\n assert(issame(result, count, (const int[]){2, 3, 5, 7}, 4));\n free(result);\n\n result = func0(0, &count);\n assert(count == 0);\n free(result);\n\n result = func0(22, &count);\n assert(issame(result, count, (const int[]){2, 3, 5, 7, 11, 13, 17, 19}, 8));\n free(result);\n\n result = func0(1, &count);\n assert(count == 0);\n free(result);\n\n result = func0(18, &count);\n assert(issame(result, count, (const int[]){2, 3, 5, 7, 11, 13, 17}, 7));\n free(result);\n\n result = func0(47, &count);\n assert(issame(result, count, (const int[]){2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43}, 14));\n free(result);\n\n result = func0(101, &count);\n assert(issame(result, count, expected, 25));\n free(result);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmovsxd rdi, edi\nmov rbp, rsi\npush rbx\nmov rbx, rdi\nshl rdi, 2; size\nsub rsp, 8\ncall _malloc\nmov dword ptr [rbp+0], 0\nxor r9d, r9d\nmov edi, 2\nmov r10, rax\ncmp ebx, 2\njle short loc_16F0\nnop dword ptr [rax+rax+00h]\nloc_16A8:\nmovsxd r11, r9d\nlea r8, [r10+r11*4]\ntest r9d, r9d\njle short loc_16DD\nloc_16B4:\nmov rsi, r10\njmp short loc_16D2\nloc_16C0:\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njz short loc_1700\nadd rsi, 4\ncmp r8, rsi\njz short loc_16DD\nloc_16D2:\nmov ecx, [rsi]\nmov eax, ecx\nimul eax, ecx\ncmp eax, edi\njle short loc_16C0\nloc_16DD:\nmov [r10+r11*4], edi\nadd r9d, 1\nadd edi, 1\nmov [rbp+0], r9d\ncmp ebx, edi\njnz short loc_16A8\nloc_16F0:\nadd rsp, 8\nmov rax, r10\npop rbx\npop rbp\nretn\nloc_1700:\nadd edi, 1\ncmp edi, ebx\njnz short loc_16B4\nadd rsp, 8\nmov rax, r10\npop rbx\npop rbp\nretn", + "ida_pseudo": "int *__fastcall func0(int a1, int *a2)\n{\n int *result; // rax\n int v5; // r9d\n int v6; // edi\n int *i; // rsi\n int v8; // ecx\n\n result = (int *)malloc(4LL * a1);\n *a2 = 0;\n v5 = 0;\n v6 = 2;\n if ( a1 > 2 )\n {\n do\n {\n if ( v5 > 0 )\n {\nLABEL_3:\n for ( i = result; &result[v5] != i; ++i )\n {\n v8 = *i;\n if ( v8 * v8 > v6 )\n break;\n if ( !(v6 % v8) )\n {\n if ( ++v6 != a1 )\n goto LABEL_3;\n return result;\n }\n }\n }\n result[v5++] = v6++;\n *a2 = v5;\n }\n while ( a1 != v6 );\n }\n return result;\n}", + "ida_strip_asm": "sub_1670:\nendbr64\npush rbp\nmovsxd rdi, edi\nmov rbp, rsi\npush rbx\nmov rbx, rdi\nshl rdi, 2; size\nsub rsp, 8\ncall _malloc\nmov dword ptr [rbp+0], 0\nxor r9d, r9d\nmov edi, 2\nmov r10, rax\ncmp ebx, 2\njle short loc_16F0\nnop dword ptr [rax+rax+00h]\nloc_16A8:\nmovsxd r11, r9d\nlea r8, [r10+r11*4]\ntest r9d, r9d\njle short loc_16DD\nloc_16B4:\nmov rsi, r10\njmp short loc_16D2\nloc_16C0:\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njz short loc_1700\nadd rsi, 4\ncmp r8, rsi\njz short loc_16DD\nloc_16D2:\nmov ecx, [rsi]\nmov eax, ecx\nimul eax, ecx\ncmp eax, edi\njle short loc_16C0\nloc_16DD:\nmov [r10+r11*4], edi\nadd r9d, 1\nadd edi, 1\nmov [rbp+0], r9d\ncmp ebx, edi\njnz short loc_16A8\nloc_16F0:\nadd rsp, 8\nmov rax, r10\npop rbx\npop rbp\nretn\nloc_1700:\nadd edi, 1\ncmp edi, ebx\njnz short loc_16B4\nadd rsp, 8\nmov rax, r10\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "int *__fastcall sub_1670(int a1, int *a2)\n{\n int *result; // rax\n int v5; // r9d\n int v6; // edi\n int *i; // rsi\n int v8; // ecx\n\n result = (int *)malloc(4LL * a1);\n *a2 = 0;\n v5 = 0;\n v6 = 2;\n if ( a1 > 2 )\n {\n do\n {\n if ( v5 > 0 )\n {\nLABEL_3:\n for ( i = result; &result[v5] != i; ++i )\n {\n v8 = *i;\n if ( v8 * v8 > v6 )\n break;\n if ( !(v6 % v8) )\n {\n if ( ++v6 != a1 )\n goto LABEL_3;\n return result;\n }\n }\n }\n result[v5++] = v6++;\n *a2 = v5;\n }\n while ( a1 != v6 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "int *sub_1670(int a1, int *a2) {\n int *result;\n int v5;\n int v6;\n int *i;\n int v8;\n result = (int *)malloc(4LL * a1);\n *a2 = 0;\n v5 = 0;\n v6 = 2;\n if (a1 > 2) {\n do {\n if (v5 > 0) {\n LABEL_3:\n for (i = result; &result[v5] != i; ++i) {\n v8 = *i;\n if (v8 * v8 > v6) break;\n if (!(v6 % v8)) {\n if (++v6 != a1) goto LABEL_3;\n return result;\n }\n }\n }\n result[v5++] = v6++;\n *a2 = v5;\n } while (a1 != v6);\n }\n return result;\n}", + "ida_pseudo_norm": "int *func0(int a1, int *a2) {\n int *result;\n int v5;\n int v6;\n int *i;\n int v8;\n result = (int *)malloc(4LL * a1);\n *a2 = 0;\n v5 = 0;\n v6 = 2;\n if (a1 > 2) {\n do {\n if (v5 > 0) {\n LABEL_3:\n for (i = result; &result[v5] != i; ++i) {\n v8 = *i;\n if (v8 * v8 > v6) break;\n if (!(v6 % v8)) {\n if (++v6 != a1) goto LABEL_3;\n return result;\n }\n }\n }\n result[v5++] = v6++;\n *a2 = v5;\n } while (a1 != v6);\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-97", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(int a, int b) { return (abs(a) % 10) * (abs(b) % 10); }", + "test": "#include \n\nint main() {\n assert(func0(148, 412) == 16);\n assert(func0(19, 28) == 72);\n assert(func0(2020, 1851) == 0);\n assert(func0(14, -15) == 20);\n assert(func0(76, 67) == 42);\n assert(func0(17, 27) == 49);\n assert(func0(0, 1) == 0);\n assert(func0(0, 0) == 0);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov eax, [rbp+var_4]\nmov edx, eax\nneg edx\ncmovs edx, eax\nmovsxd rax, edx\nimul rax, 66666667h\nshr rax, 20h\nmov ecx, eax\nsar ecx, 2\nmov eax, edx\nsar eax, 1Fh\nsub ecx, eax\nmov eax, ecx\nshl eax, 2\nadd eax, ecx\nadd eax, eax\nmov ecx, edx\nsub ecx, eax\nmov eax, [rbp+var_8]\nmov edx, eax\nneg edx\ncmovns eax, edx\nmov esi, eax\nmovsxd rax, esi\nimul rax, 66666667h\nshr rax, 20h\nmov edx, eax\nsar edx, 2\nmov eax, esi\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nsub esi, eax\nmov edx, esi\nmov eax, ecx\nimul eax, edx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n int v2; // edx\n int v3; // eax\n\n v2 = -a1;\n if ( a1 > 0 )\n v2 = a1;\n v3 = a2;\n if ( a2 <= 0 )\n v3 = -a2;\n return (unsigned int)(v3 % 10 * (v2 % 10));\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov eax, [rbp+var_4]\nmov edx, eax\nneg edx\ncmovs edx, eax\nmovsxd rax, edx\nimul rax, 66666667h\nshr rax, 20h\nmov ecx, eax\nsar ecx, 2\nmov eax, edx\nsar eax, 1Fh\nsub ecx, eax\nmov eax, ecx\nshl eax, 2\nadd eax, ecx\nadd eax, eax\nmov ecx, edx\nsub ecx, eax\nmov eax, [rbp+var_8]\nmov edx, eax\nneg edx\ncmovns eax, edx\nmov esi, eax\nmovsxd rax, esi\nimul rax, 66666667h\nshr rax, 20h\nmov edx, eax\nsar edx, 2\nmov eax, esi\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nsub esi, eax\nmov edx, esi\nmov eax, ecx\nimul eax, edx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2)\n{\n int v2; // edx\n int v3; // eax\n\n v2 = -a1;\n if ( a1 > 0 )\n v2 = a1;\n v3 = a2;\n if ( a2 <= 0 )\n v3 = -a2;\n return (unsigned int)(v3 % 10 * (v2 % 10));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2) {\n int v2;\n int v3;\n v2 = -a1;\n if (a1 > 0) v2 = a1;\n v3 = a2;\n if (a2 <= 0) v3 = -a2;\n return (unsigned int)(v3 % 10 * (v2 % 10));\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n int v2;\n int v3;\n v2 = -a1;\n if (a1 > 0) v2 = a1;\n v3 = a2;\n if (a2 <= 0) v3 = -a2;\n return (unsigned int)(v3 % 10 * (v2 % 10));\n}" + }, + { + "index": "HumanEval-C-98", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(const char *s) {\n const char *uvowel = \"AEIOU\";\n int count = 0;\n for (int i = 0; s[i] != '\\0' && i * 2 < strlen(s); i++) {\n if (strchr(uvowel, s[i * 2]) != NULL) {\n count += 1;\n }\n }\n return count;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"aBCdEf\") == 1);\n assert(func0(\"abcdefg\") == 0);\n assert(func0(\"dBBE\") == 0);\n assert(func0(\"B\") == 0);\n assert(func0(\"U\") == 1);\n assert(func0(\"\") == 0);\n assert(func0(\"EEEE\") == 2);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+var_28], rdi\nlea rax, aAeiou; \"AEIOU\"\nmov [rbp+s], rax\nmov [rbp+var_20], 0\nmov [rbp+var_1C], 0\njmp short loc_11E5\nloc_11B5:\nmov eax, [rbp+var_1C]\nadd eax, eax\nmovsxd rdx, eax\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx edx, al\nmov rax, [rbp+s]\nmov esi, edx; c\nmov rdi, rax; s\ncall _strchr\ntest rax, rax\njz short loc_11E1\nadd [rbp+var_20], 1\nloc_11E1:\nadd [rbp+var_1C], 1\nloc_11E5:\nmov eax, [rbp+var_1C]\nmovsxd rdx, eax\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njz short loc_1212\nmov eax, [rbp+var_1C]\nadd eax, eax\nmovsxd rbx, eax\nmov rax, [rbp+var_28]\nmov rdi, rax; s\ncall _strlen\ncmp rbx, rax\njb short loc_11B5\nloc_1212:\nmov eax, [rbp+var_20]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n unsigned int v2; // [rsp+10h] [rbp-20h]\n int i; // [rsp+14h] [rbp-1Ch]\n\n v2 = 0;\n for ( i = 0; a1[i] && 2 * i < strlen(a1); ++i )\n {\n if ( strchr(\"AEIOU\", a1[2 * i]) )\n ++v2;\n }\n return v2;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+var_28], rdi\nlea rax, aAeiou; \"AEIOU\"\nmov [rbp+s], rax\nmov [rbp+var_20], 0\nmov [rbp+var_1C], 0\njmp short loc_11E5\nloc_11B5:\nmov eax, [rbp+var_1C]\nadd eax, eax\nmovsxd rdx, eax\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx edx, al\nmov rax, [rbp+s]\nmov esi, edx; c\nmov rdi, rax; s\ncall _strchr\ntest rax, rax\njz short loc_11E1\nadd [rbp+var_20], 1\nloc_11E1:\nadd [rbp+var_1C], 1\nloc_11E5:\nmov eax, [rbp+var_1C]\nmovsxd rdx, eax\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njz short loc_1212\nmov eax, [rbp+var_1C]\nadd eax, eax\nmovsxd rbx, eax\nmov rax, [rbp+var_28]\nmov rdi, rax; s\ncall _strlen\ncmp rbx, rax\njb short loc_11B5\nloc_1212:\nmov eax, [rbp+var_20]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(const char *a1)\n{\n unsigned int v2; // [rsp+10h] [rbp-20h]\n int i; // [rsp+14h] [rbp-1Ch]\n\n v2 = 0;\n for ( i = 0; a1[i] && 2 * i < strlen(a1); ++i )\n {\n if ( strchr(\"AEIOU\", a1[2 * i]) )\n ++v2;\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(const char *a1) {\n unsigned int v2;\n int i;\n v2 = 0;\n for (i = 0; a1[i] && 2 * i < strlen(a1); ++i) {\n if (strchr(\"AEIOU\", a1[2 * i])) ++v2;\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n unsigned int v2;\n int i;\n v2 = 0;\n for (i = 0; a1[i] && 2 * i < strlen(a1); ++i) {\n if (strchr(\"AEIOU\", a1[2 * i])) ++v2;\n }\n return v2;\n}" + }, + { + "index": "HumanEval-C-98", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(const char *s) {\n const char *uvowel = \"AEIOU\";\n int count = 0;\n for (int i = 0; s[i] != '\\0' && i * 2 < strlen(s); i++) {\n if (strchr(uvowel, s[i * 2]) != NULL) {\n count += 1;\n }\n }\n return count;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"aBCdEf\") == 1);\n assert(func0(\"abcdefg\") == 0);\n assert(func0(\"dBBE\") == 0);\n assert(func0(\"B\") == 0);\n assert(func0(\"U\") == 1);\n assert(func0(\"\") == 0);\n assert(func0(\"EEEE\") == 2);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\ncmp byte ptr [rdi], 0\njz short loc_11EC\nmov rbp, rdi\ncall _strlen\nlea r13, [rax+1]\nshr r13, 1\nmov ebx, 0\nmov r12d, 0\nlea r14, s; \"AEIOU\"\nloc_11BB:\ncmp rbx, r13\njz short loc_11E0\nmovsx esi, byte ptr [rbp+rbx*2+0]; c\nmov rdi, r14; s\ncall _strchr\ncmp rax, 1\nsbb r12d, 0FFFFFFFFh\nadd rbx, 1\ncmp byte ptr [rbp+rbx+0], 0\njnz short loc_11BB\nloc_11E0:\nmov eax, r12d\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_11EC:\nmov r12d, 0\njmp short loc_11E0", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n size_t v1; // r13\n __int64 v2; // rbx\n unsigned int v3; // r12d\n\n if ( *a1 )\n {\n v1 = (strlen(a1) + 1) >> 1;\n v2 = 0LL;\n v3 = 0;\n do\n {\n if ( v2 == v1 )\n break;\n v3 -= (strchr(\"AEIOU\", a1[2 * v2++]) == 0LL) - 1;\n }\n while ( a1[v2] );\n }\n else\n {\n return 0;\n }\n return v3;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\ncmp byte ptr [rdi], 0\njz short loc_11EC\nmov rbp, rdi\ncall _strlen\nlea r13, [rax+1]\nshr r13, 1\nmov ebx, 0\nmov r12d, 0\nlea r14, s; \"AEIOU\"\nloc_11BB:\ncmp rbx, r13\njz short loc_11E0\nmovsx esi, byte ptr [rbp+rbx*2+0]; c\nmov rdi, r14; s\ncall _strchr\ncmp rax, 1\nsbb r12d, 0FFFFFFFFh\nadd rbx, 1\ncmp byte ptr [rbp+rbx+0], 0\njnz short loc_11BB\nloc_11E0:\nmov eax, r12d\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_11EC:\nmov r12d, 0\njmp short loc_11E0", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(const char *a1)\n{\n size_t v1; // r13\n __int64 v2; // rbx\n unsigned int v3; // r12d\n\n if ( *a1 )\n {\n v1 = (strlen(a1) + 1) >> 1;\n v2 = 0LL;\n v3 = 0;\n do\n {\n if ( v2 == v1 )\n break;\n v3 -= (strchr(\"AEIOU\", a1[2 * v2++]) == 0LL) - 1;\n }\n while ( a1[v2] );\n }\n else\n {\n return 0;\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(const char *a1) {\n unsigned int v1;\n long long v2;\n unsigned int v3;\n if (*a1) {\n v1 = (strlen(a1) + 1) >> 1;\n v2 = 0LL;\n v3 = 0;\n do {\n if (v2 == v1) break;\n v3 -= (strchr(\"AEIOU\", a1[2 * v2++]) == 0LL) - 1;\n } while (a1[v2]);\n } else {\n return 0;\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n unsigned int v1;\n long long v2;\n unsigned int v3;\n if (*a1) {\n v1 = (strlen(a1) + 1) >> 1;\n v2 = 0LL;\n v3 = 0;\n do {\n if (v2 == v1) break;\n v3 -= (strchr(\"AEIOU\", a1[2 * v2++]) == 0LL) - 1;\n } while (a1[v2]);\n } else {\n return 0;\n }\n return v3;\n}" + }, + { + "index": "HumanEval-C-98", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(const char *s) {\n const char *uvowel = \"AEIOU\";\n int count = 0;\n for (int i = 0; s[i] != '\\0' && i * 2 < strlen(s); i++) {\n if (strchr(uvowel, s[i * 2]) != NULL) {\n count += 1;\n }\n }\n return count;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"aBCdEf\") == 1);\n assert(func0(\"abcdefg\") == 0);\n assert(func0(\"dBBE\") == 0);\n assert(func0(\"B\") == 0);\n assert(func0(\"U\") == 1);\n assert(func0(\"\") == 0);\n assert(func0(\"EEEE\") == 2);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\ncmp byte ptr [rdi], 0\njz short loc_1361\nmov rbp, rdi\nxor ebx, ebx\nlea r14, s; \"AEIOU\"\nxor r12d, r12d\ncall _strlen\nlea r13, [rax+1]\nshr r13, 1\njmp short loc_1350\nloc_1330:\nmovsx esi, byte ptr [rbp+rbx*2+0]; c\nmov rdi, r14; s\ncall _strchr\ncmp rax, 1\nsbb r12d, 0FFFFFFFFh\nadd rbx, 1\ncmp byte ptr [rbp+rbx+0], 0\njz short loc_1355\nloc_1350:\ncmp rbx, r13\njnz short loc_1330\nloc_1355:\npop rbx\nmov eax, r12d\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1361:\nxor r12d, r12d\njmp short loc_1355", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n __int64 v1; // rbx\n unsigned int v2; // r12d\n size_t v3; // r13\n\n if ( *a1 )\n {\n v1 = 0LL;\n v2 = 0;\n v3 = (strlen(a1) + 1) >> 1;\n do\n {\n if ( v1 == v3 )\n break;\n v2 -= (strchr(\"AEIOU\", a1[2 * v1++]) == 0LL) - 1;\n }\n while ( a1[v1] );\n }\n else\n {\n return 0;\n }\n return v2;\n}", + "ida_strip_asm": "sub_1300:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\ncmp byte ptr [rdi], 0\njz short loc_1361\nmov rbp, rdi\nxor ebx, ebx\nlea r14, s; \"AEIOU\"\nxor r12d, r12d\ncall _strlen\nlea r13, [rax+1]\nshr r13, 1\njmp short loc_1350\nloc_1330:\nmovsx esi, byte ptr [rbp+rbx*2+0]; c\nmov rdi, r14; s\ncall _strchr\ncmp rax, 1\nsbb r12d, 0FFFFFFFFh\nadd rbx, 1\ncmp byte ptr [rbp+rbx+0], 0\njz short loc_1355\nloc_1350:\ncmp rbx, r13\njnz short loc_1330\nloc_1355:\npop rbx\nmov eax, r12d\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1361:\nxor r12d, r12d\njmp short loc_1355", + "ida_strip_pseudo": "__int64 __fastcall sub_1300(const char *a1)\n{\n __int64 v1; // rbx\n unsigned int v2; // r12d\n size_t v3; // r13\n\n if ( *a1 )\n {\n v1 = 0LL;\n v2 = 0;\n v3 = (strlen(a1) + 1) >> 1;\n do\n {\n if ( v1 == v3 )\n break;\n v2 -= (strchr(\"AEIOU\", a1[2 * v1++]) == 0LL) - 1;\n }\n while ( a1[v1] );\n }\n else\n {\n return 0;\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1300(const char *a1) {\n long long v1;\n unsigned int v2;\n unsigned int v3;\n if (*a1) {\n v1 = 0LL;\n v2 = 0;\n v3 = (strlen(a1) + 1) >> 1;\n do {\n if (v1 == v3) break;\n v2 -= (strchr(\"AEIOU\", a1[2 * v1++]) == 0LL) - 1;\n } while (a1[v1]);\n } else {\n return 0;\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n long long v1;\n unsigned int v2;\n unsigned int v3;\n if (*a1) {\n v1 = 0LL;\n v2 = 0;\n v3 = (strlen(a1) + 1) >> 1;\n do {\n if (v1 == v3) break;\n v2 -= (strchr(\"AEIOU\", a1[2 * v1++]) == 0LL) - 1;\n } while (a1[v1]);\n } else {\n return 0;\n }\n return v2;\n}" + }, + { + "index": "HumanEval-C-98", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(const char *s) {\n const char *uvowel = \"AEIOU\";\n int count = 0;\n for (int i = 0; s[i] != '\\0' && i * 2 < strlen(s); i++) {\n if (strchr(uvowel, s[i * 2]) != NULL) {\n count += 1;\n }\n }\n return count;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"aBCdEf\") == 1);\n assert(func0(\"abcdefg\") == 0);\n assert(func0(\"dBBE\") == 0);\n assert(func0(\"B\") == 0);\n assert(func0(\"U\") == 1);\n assert(func0(\"\") == 0);\n assert(func0(\"EEEE\") == 2);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\ncmp byte ptr [rdi], 0\njz short loc_1361\nmov rbp, rdi\nxor ebx, ebx\nlea r14, s; \"AEIOU\"\nxor r12d, r12d\ncall _strlen\nlea r13, [rax+1]\nshr r13, 1\njmp short loc_1350\nloc_1330:\nmovsx esi, byte ptr [rbp+rbx*2+0]; c\nmov rdi, r14; s\ncall _strchr\ncmp rax, 1\nsbb r12d, 0FFFFFFFFh\nadd rbx, 1\ncmp byte ptr [rbp+rbx+0], 0\njz short loc_1355\nloc_1350:\ncmp r13, rbx\njnz short loc_1330\nloc_1355:\npop rbx\nmov eax, r12d\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1361:\nxor r12d, r12d\njmp short loc_1355", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n __int64 v1; // rbx\n unsigned int v2; // r12d\n size_t v3; // r13\n\n if ( *a1 )\n {\n v1 = 0LL;\n v2 = 0;\n v3 = (strlen(a1) + 1) >> 1;\n do\n {\n if ( v3 == v1 )\n break;\n v2 -= (strchr(\"AEIOU\", a1[2 * v1++]) == 0LL) - 1;\n }\n while ( a1[v1] );\n }\n else\n {\n return 0;\n }\n return v2;\n}", + "ida_strip_asm": "sub_1300:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\ncmp byte ptr [rdi], 0\njz short loc_1361\nmov rbp, rdi\nxor ebx, ebx\nlea r14, s; \"AEIOU\"\nxor r12d, r12d\ncall _strlen\nlea r13, [rax+1]\nshr r13, 1\njmp short loc_1350\nloc_1330:\nmovsx esi, byte ptr [rbp+rbx*2+0]; c\nmov rdi, r14; s\ncall _strchr\ncmp rax, 1\nsbb r12d, 0FFFFFFFFh\nadd rbx, 1\ncmp byte ptr [rbp+rbx+0], 0\njz short loc_1355\nloc_1350:\ncmp r13, rbx\njnz short loc_1330\nloc_1355:\npop rbx\nmov eax, r12d\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1361:\nxor r12d, r12d\njmp short loc_1355", + "ida_strip_pseudo": "__int64 __fastcall sub_1300(const char *a1)\n{\n __int64 v1; // rbx\n unsigned int v2; // r12d\n size_t v3; // r13\n\n if ( *a1 )\n {\n v1 = 0LL;\n v2 = 0;\n v3 = (strlen(a1) + 1) >> 1;\n do\n {\n if ( v3 == v1 )\n break;\n v2 -= (strchr(\"AEIOU\", a1[2 * v1++]) == 0LL) - 1;\n }\n while ( a1[v1] );\n }\n else\n {\n return 0;\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1300(const char *a1) {\n long long v1;\n unsigned int v2;\n unsigned int v3;\n if (*a1) {\n v1 = 0LL;\n v2 = 0;\n v3 = (strlen(a1) + 1) >> 1;\n do {\n if (v3 == v1) break;\n v2 -= (strchr(\"AEIOU\", a1[2 * v1++]) == 0LL) - 1;\n } while (a1[v1]);\n } else {\n return 0;\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n long long v1;\n unsigned int v2;\n unsigned int v3;\n if (*a1) {\n v1 = 0LL;\n v2 = 0;\n v3 = (strlen(a1) + 1) >> 1;\n do {\n if (v3 == v1) break;\n v2 -= (strchr(\"AEIOU\", a1[2 * v1++]) == 0LL) - 1;\n } while (a1[v1]);\n } else {\n return 0;\n }\n return v2;\n}" + }, + { + "index": "HumanEval-C-99", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int func0(const char *value) {\n double w;\n w = atof(value);\n return (int)(w < 0 ? ceil(w - 0.5) : floor(w + 0.5));\n}", + "test": "#include \n\nint main() {\n assert(func0(\"10\") == 10);\n assert(func0(\"14.5\") == 15);\n assert(func0(\"-15.5\") == -16);\n assert(func0(\"15.3\") == 15);\n assert(func0(\"0\") == 0);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+nptr], rdi\nmov rax, [rbp+nptr]\nmov rdi, rax; nptr\ncall _atof\nmovq rax, xmm0\nmov [rbp+var_8], rax\npxor xmm0, xmm0\ncomisd xmm0, [rbp+var_8]\njbe short loc_11FF\nmovsd xmm0, [rbp+var_8]\nmovsd xmm1, cs:qword_20A8\nsubsd xmm0, xmm1\nmovq rax, xmm0\nmovq xmm0, rax; x\ncall _ceil\ncvttsd2si eax, xmm0\njmp short locret_1223\nloc_11FF:\nmovsd xmm1, [rbp+var_8]\nmovsd xmm0, cs:qword_20A8\naddsd xmm1, xmm0\nmovq rax, xmm1\nmovq xmm0, rax; x\ncall _floor\ncvttsd2si eax, xmm0\nlocret_1223:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n double v2; // [rsp+18h] [rbp-8h]\n\n v2 = atof(a1);\n if ( v2 >= 0.0 )\n return (unsigned int)(int)floor(v2 + 0.5);\n else\n return (unsigned int)(int)ceil(v2 - 0.5);\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+nptr], rdi\nmov rax, [rbp+nptr]\nmov rdi, rax; nptr\ncall _atof\nmovq rax, xmm0\nmov [rbp+var_8], rax\npxor xmm0, xmm0\ncomisd xmm0, [rbp+var_8]\njbe short loc_11FF\nmovsd xmm0, [rbp+var_8]\nmovsd xmm1, cs:qword_20A8\nsubsd xmm0, xmm1\nmovq rax, xmm0\nmovq xmm0, rax; x\ncall _ceil\ncvttsd2si eax, xmm0\njmp short locret_1223\nloc_11FF:\nmovsd xmm1, [rbp+var_8]\nmovsd xmm0, cs:qword_20A8\naddsd xmm1, xmm0\nmovq rax, xmm1\nmovq xmm0, rax; x\ncall _floor\ncvttsd2si eax, xmm0\nlocret_1223:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(const char *a1)\n{\n double v2; // [rsp+18h] [rbp-8h]\n\n v2 = atof(a1);\n if ( v2 >= 0.0 )\n return (unsigned int)(int)floor(v2 + 0.5);\n else\n return (unsigned int)(int)ceil(v2 - 0.5);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(const char *a1) {\n double v2;\n v2 = atof(a1);\n if (v2 >= 0.0)\n return (unsigned int)(int)floor(v2 + 0.5);\n else\n return (unsigned int)(int)ceil(v2 - 0.5);\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n double v2;\n v2 = atof(a1);\n if (v2 >= 0.0)\n return (unsigned int)(int)floor(v2 + 0.5);\n else\n return (unsigned int)(int)ceil(v2 - 0.5);\n}" + }, + { + "index": "HumanEval-C-99", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int func0(const char *value) {\n double w;\n w = atof(value);\n return (int)(w < 0 ? ceil(w - 0.5) : floor(w + 0.5));\n}", + "test": "#include \n\nint main() {\n assert(func0(\"10\") == 10);\n assert(func0(\"14.5\") == 15);\n assert(func0(\"-15.5\") == -16);\n assert(func0(\"15.3\") == 15);\n assert(func0(\"0\") == 0);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\nmov esi, 0; endptr\ncall _strtod\npxor xmm1, xmm1\ncomisd xmm1, xmm0\nja short loc_11EB\naddsd xmm0, cs:qword_20A0\nmovapd xmm3, xmm0\nmovsd xmm2, cs:qword_20B8\nmovapd xmm1, xmm0\nandpd xmm1, xmm2\nmovsd xmm4, cs:qword_20A8\nucomisd xmm4, xmm1\njbe short loc_11E2\ncvttsd2si rax, xmm0\npxor xmm1, xmm1\ncvtsi2sd xmm1, rax\nmovapd xmm3, xmm1\ncmpnlesd xmm3, xmm0\nmovsd xmm4, cs:qword_20B0\nandpd xmm3, xmm4\nsubsd xmm1, xmm3\nandnpd xmm2, xmm0\nmovapd xmm3, xmm1\norpd xmm3, xmm2\nloc_11E2:\ncvttsd2si eax, xmm3\nloc_11E6:\nadd rsp, 8\nretn\nloc_11EB:\nsubsd xmm0, cs:qword_20A0\nmovapd xmm3, xmm0\nmovsd xmm2, cs:qword_20B8\nmovapd xmm1, xmm0\nandpd xmm1, xmm2\nmovsd xmm4, cs:qword_20A8\nucomisd xmm4, xmm1\njbe short loc_1240\ncvttsd2si rax, xmm0\npxor xmm1, xmm1\ncvtsi2sd xmm1, rax\ncmpnlesd xmm3, xmm1\nmovsd xmm4, cs:qword_20B0\nandpd xmm3, xmm4\naddsd xmm3, xmm1\nandnpd xmm2, xmm0\norpd xmm3, xmm2\nloc_1240:\ncvttsd2si eax, xmm3\njmp short loc_11E6", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, __m128d a2)\n{\n double v2; // xmm0_8\n __m128d v3; // xmm0\n double v4; // xmm3_8\n __m128d v5; // xmm1\n unsigned __int64 v7; // xmm3_8\n __m128d v8; // xmm1\n\n v2 = strtod(a1, 0LL);\n if ( v2 < 0.0 )\n {\n a2.m128d_f64[0] = v2 - 0.5;\n v7 = *(unsigned __int64 *)&a2.m128d_f64[0];\n if ( fabs(a2.m128d_f64[0]) < 4.503599627370496e15 )\n {\n v8.m128d_f64[0] = (double)(int)a2.m128d_f64[0];\n v7 = COERCE_UNSIGNED_INT64(COERCE_DOUBLE(*(_OWORD *)&_mm_cmpgt_sd(a2, v8) & 0x3FF0000000000000LL) + v8.m128d_f64[0]) | *(_QWORD *)&a2.m128d_f64[0] & 0x8000000000000000LL;\n }\n return (unsigned int)(int)*(double *)&v7;\n }\n else\n {\n v3.m128d_f64[0] = v2 + 0.5;\n v4 = v3.m128d_f64[0];\n if ( fabs(v3.m128d_f64[0]) < 4.503599627370496e15 )\n {\n v5 = 0LL;\n v5.m128d_f64[0] = (double)(int)v3.m128d_f64[0];\n *(_QWORD *)&v4 = COERCE_UNSIGNED_INT64(v5.m128d_f64[0] - COERCE_DOUBLE(*(_OWORD *)&_mm_cmpgt_sd(v5, v3) & 0x3FF0000000000000LL)) | *(_QWORD *)&v3.m128d_f64[0] & 0x8000000000000000LL;\n }\n return (unsigned int)(int)v4;\n }\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nsub rsp, 8\nmov esi, 0; endptr\ncall _strtod\npxor xmm1, xmm1\ncomisd xmm1, xmm0\nja short loc_11EB\naddsd xmm0, cs:qword_20A0\nmovapd xmm3, xmm0\nmovsd xmm2, cs:qword_20B8\nmovapd xmm1, xmm0\nandpd xmm1, xmm2\nmovsd xmm4, cs:qword_20A8\nucomisd xmm4, xmm1\njbe short loc_11E2\ncvttsd2si rax, xmm0\npxor xmm1, xmm1\ncvtsi2sd xmm1, rax\nmovapd xmm3, xmm1\ncmpnlesd xmm3, xmm0\nmovsd xmm4, cs:qword_20B0\nandpd xmm3, xmm4\nsubsd xmm1, xmm3\nandnpd xmm2, xmm0\nmovapd xmm3, xmm1\norpd xmm3, xmm2\nloc_11E2:\ncvttsd2si eax, xmm3\nloc_11E6:\nadd rsp, 8\nretn\nloc_11EB:\nsubsd xmm0, cs:qword_20A0\nmovapd xmm3, xmm0\nmovsd xmm2, cs:qword_20B8\nmovapd xmm1, xmm0\nandpd xmm1, xmm2\nmovsd xmm4, cs:qword_20A8\nucomisd xmm4, xmm1\njbe short loc_1240\ncvttsd2si rax, xmm0\npxor xmm1, xmm1\ncvtsi2sd xmm1, rax\ncmpnlesd xmm3, xmm1\nmovsd xmm4, cs:qword_20B0\nandpd xmm3, xmm4\naddsd xmm3, xmm1\nandnpd xmm2, xmm0\norpd xmm3, xmm2\nloc_1240:\ncvttsd2si eax, xmm3\njmp short loc_11E6", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1, __m128d a2)\n{\n double v2; // xmm0_8\n __m128d v3; // xmm0\n double v4; // xmm3_8\n __m128d v5; // xmm1\n unsigned __int64 v7; // xmm3_8\n __m128d v8; // xmm1\n\n v2 = strtod(a1, 0LL);\n if ( v2 < 0.0 )\n {\n a2.m128d_f64[0] = v2 - 0.5;\n v7 = *(unsigned __int64 *)&a2.m128d_f64[0];\n if ( fabs(a2.m128d_f64[0]) < 4.503599627370496e15 )\n {\n v8.m128d_f64[0] = (double)(int)a2.m128d_f64[0];\n v7 = COERCE_UNSIGNED_INT64(COERCE_DOUBLE(*(_OWORD *)&_mm_cmpgt_sd(a2, v8) & 0x3FF0000000000000LL) + v8.m128d_f64[0]) | *(_QWORD *)&a2.m128d_f64[0] & 0x8000000000000000LL;\n }\n return (unsigned int)(int)*(double *)&v7;\n }\n else\n {\n v3.m128d_f64[0] = v2 + 0.5;\n v4 = v3.m128d_f64[0];\n if ( fabs(v3.m128d_f64[0]) < 4.503599627370496e15 )\n {\n v5 = 0LL;\n v5.m128d_f64[0] = (double)(int)v3.m128d_f64[0];\n *(_QWORD *)&v4 = COERCE_UNSIGNED_INT64(v5.m128d_f64[0] - COERCE_DOUBLE(*(_OWORD *)&_mm_cmpgt_sd(v5, v3) & 0x3FF0000000000000LL)) | *(_QWORD *)&v3.m128d_f64[0] & 0x8000000000000000LL;\n }\n return (unsigned int)(int)v4;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1, __m128d a2) {\n double v2;\n __m128d v3;\n double v4;\n __m128d v5;\n unsigned long long v7;\n __m128d v8;\n v2 = strtod(a1, 0LL);\n if (v2 < 0.0) {\n a2.m128d_f64[0] = v2 - 0.5;\n v7 = *(unsigned long long *)&a2.m128d_f64[0];\n if (fabs(a2.m128d_f64[0]) < 4.503599627370496e15) {\n v8.m128d_f64[0] = (double)(int)a2.m128d_f64[0];\n v7 = COERCE_UNSIGNED_INT64(\n COERCE_DOUBLE(*(long double *)&_mm_cmpgt_sd(a2, v8) &\n 4607182418800017408LL) +\n v8.m128d_f64[0]) |\n *(uint64_t *)&a2.m128d_f64[0] & 9223372036854775808LL;\n }\n return (unsigned int)(int)*(double *)&v7;\n } else {\n v3.m128d_f64[0] = v2 + 0.5;\n v4 = v3.m128d_f64[0];\n if (fabs(v3.m128d_f64[0]) < 4.503599627370496e15) {\n v5 = 0LL;\n v5.m128d_f64[0] = (double)(int)v3.m128d_f64[0];\n *(uint64_t *)&v4 =\n COERCE_UNSIGNED_INT64(\n v5.m128d_f64[0] -\n COERCE_DOUBLE(*(long double *)&_mm_cmpgt_sd(v5, v3) &\n 4607182418800017408LL)) |\n *(uint64_t *)&v3.m128d_f64[0] & 9223372036854775808LL;\n }\n return (unsigned int)(int)v4;\n }\n}", + "ida_pseudo_norm": "long long func0(const char *a1, __m128d a2) {\n double v2;\n __m128d v3;\n double v4;\n __m128d v5;\n unsigned long long v7;\n __m128d v8;\n v2 = strtod(a1, 0LL);\n if (v2 < 0.0) {\n a2.m128d_f64[0] = v2 - 0.5;\n v7 = *(unsigned long long *)&a2.m128d_f64[0];\n if (fabs(a2.m128d_f64[0]) < 4.503599627370496e15) {\n v8.m128d_f64[0] = (double)(int)a2.m128d_f64[0];\n v7 = COERCE_UNSIGNED_INT64(\n COERCE_DOUBLE(*(long double *)&_mm_cmpgt_sd(a2, v8) &\n 4607182418800017408LL) +\n v8.m128d_f64[0]) |\n *(uint64_t *)&a2.m128d_f64[0] & 9223372036854775808LL;\n }\n return (unsigned int)(int)*(double *)&v7;\n } else {\n v3.m128d_f64[0] = v2 + 0.5;\n v4 = v3.m128d_f64[0];\n if (fabs(v3.m128d_f64[0]) < 4.503599627370496e15) {\n v5 = 0LL;\n v5.m128d_f64[0] = (double)(int)v3.m128d_f64[0];\n *(uint64_t *)&v4 =\n COERCE_UNSIGNED_INT64(\n v5.m128d_f64[0] -\n COERCE_DOUBLE(*(long double *)&_mm_cmpgt_sd(v5, v3) &\n 4607182418800017408LL)) |\n *(uint64_t *)&v3.m128d_f64[0] & 9223372036854775808LL;\n }\n return (unsigned int)(int)v4;\n }\n}" + }, + { + "index": "HumanEval-C-99", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int func0(const char *value) {\n double w;\n w = atof(value);\n return (int)(w < 0 ? ceil(w - 0.5) : floor(w + 0.5));\n}", + "test": "#include \n\nint main() {\n assert(func0(\"10\") == 10);\n assert(func0(\"14.5\") == 15);\n assert(func0(\"-15.5\") == -16);\n assert(func0(\"15.3\") == 15);\n assert(func0(\"0\") == 0);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\nxor esi, esi; endptr\ncall _strtod\npxor xmm1, xmm1\ncomisd xmm1, xmm0\nja short loc_1310\naddsd xmm0, cs:qword_20A0\nmovsd xmm2, cs:qword_20B8\nmovsd xmm3, cs:qword_20A8\nmovapd xmm1, xmm0\nandpd xmm1, xmm2\nucomisd xmm3, xmm1\nja short loc_12D0\nloc_12BF:\ncvttsd2si eax, xmm0\nadd rsp, 8\nretn\nloc_12D0:\ncvttsd2si rax, xmm0\npxor xmm1, xmm1\nmovsd xmm4, cs:qword_20B0\nandnpd xmm2, xmm0\nadd rsp, 8\ncvtsi2sd xmm1, rax\nmovapd xmm3, xmm1\ncmpnlesd xmm3, xmm0\nandpd xmm3, xmm4\nsubsd xmm1, xmm3\norpd xmm1, xmm2\nmovapd xmm0, xmm1\ncvttsd2si eax, xmm0\nretn\nloc_1310:\nsubsd xmm0, cs:qword_20A0\nmovsd xmm2, cs:qword_20B8\nmovsd xmm3, cs:qword_20A8\nmovapd xmm1, xmm0\nandpd xmm1, xmm2\nucomisd xmm3, xmm1\njbe short loc_12BF\ncvttsd2si rax, xmm0\npxor xmm1, xmm1\nmovapd xmm3, xmm0\nmovsd xmm4, cs:qword_20B0\nandnpd xmm2, xmm0\nadd rsp, 8\ncvtsi2sd xmm1, rax\ncmpnlesd xmm3, xmm1\nandpd xmm3, xmm4\naddsd xmm1, xmm3\norpd xmm1, xmm2\nmovapd xmm0, xmm1\ncvttsd2si eax, xmm0\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, __m128d a2)\n{\n double v2; // xmm0_8\n __m128d v4; // xmm1\n __m128d v5; // xmm1\n\n v2 = strtod(a1, 0LL);\n if ( v2 < 0.0 )\n {\n a2.m128d_f64[0] = v2 - 0.5;\n if ( fabs(a2.m128d_f64[0]) >= 4.503599627370496e15 )\n return (unsigned int)(int)a2.m128d_f64[0];\n v5.m128d_f64[0] = (double)(int)a2.m128d_f64[0];\n return (unsigned int)(int)COERCE_DOUBLE(COERCE_UNSIGNED_INT64(\n v5.m128d_f64[0]\n + COERCE_DOUBLE(*(_OWORD *)&_mm_cmpgt_sd(a2, v5) & 0x3FF0000000000000LL)) | *(_QWORD *)&a2.m128d_f64[0] & 0x8000000000000000LL);\n }\n else\n {\n a2.m128d_f64[0] = v2 + 0.5;\n if ( fabs(a2.m128d_f64[0]) >= 4.503599627370496e15 )\n return (unsigned int)(int)a2.m128d_f64[0];\n v4 = 0LL;\n v4.m128d_f64[0] = (double)(int)a2.m128d_f64[0];\n return (unsigned int)(int)COERCE_DOUBLE(COERCE_UNSIGNED_INT64(\n v4.m128d_f64[0]\n - COERCE_DOUBLE(*(_OWORD *)&_mm_cmpgt_sd(v4, a2) & 0x3FF0000000000000LL)) | *(_QWORD *)&a2.m128d_f64[0] & 0x8000000000000000LL);\n }\n}", + "ida_strip_asm": "sub_1280:\nendbr64\nsub rsp, 8\nxor esi, esi; endptr\ncall _strtod\npxor xmm1, xmm1\ncomisd xmm1, xmm0\nja short loc_1310\naddsd xmm0, cs:qword_20A0\nmovsd xmm2, cs:qword_20B8\nmovsd xmm3, cs:qword_20A8\nmovapd xmm1, xmm0\nandpd xmm1, xmm2\nucomisd xmm3, xmm1\nja short loc_12D0\nloc_12BF:\ncvttsd2si eax, xmm0\nadd rsp, 8\nretn\nloc_12D0:\ncvttsd2si rax, xmm0\npxor xmm1, xmm1\nmovsd xmm4, cs:qword_20B0\nandnpd xmm2, xmm0\nadd rsp, 8\ncvtsi2sd xmm1, rax\nmovapd xmm3, xmm1\ncmpnlesd xmm3, xmm0\nandpd xmm3, xmm4\nsubsd xmm1, xmm3\norpd xmm1, xmm2\nmovapd xmm0, xmm1\ncvttsd2si eax, xmm0\nretn\nloc_1310:\nsubsd xmm0, cs:qword_20A0\nmovsd xmm2, cs:qword_20B8\nmovsd xmm3, cs:qword_20A8\nmovapd xmm1, xmm0\nandpd xmm1, xmm2\nucomisd xmm3, xmm1\njbe short loc_12BF\ncvttsd2si rax, xmm0\npxor xmm1, xmm1\nmovapd xmm3, xmm0\nmovsd xmm4, cs:qword_20B0\nandnpd xmm2, xmm0\nadd rsp, 8\ncvtsi2sd xmm1, rax\ncmpnlesd xmm3, xmm1\nandpd xmm3, xmm4\naddsd xmm1, xmm3\norpd xmm1, xmm2\nmovapd xmm0, xmm1\ncvttsd2si eax, xmm0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1280(const char *a1, __m128d a2)\n{\n double v2; // xmm0_8\n __m128d v4; // xmm1\n __m128d v5; // xmm1\n\n v2 = strtod(a1, 0LL);\n if ( v2 < 0.0 )\n {\n a2.m128d_f64[0] = v2 - 0.5;\n if ( fabs(a2.m128d_f64[0]) >= 4.503599627370496e15 )\n return (unsigned int)(int)a2.m128d_f64[0];\n v5.m128d_f64[0] = (double)(int)a2.m128d_f64[0];\n return (unsigned int)(int)COERCE_DOUBLE(COERCE_UNSIGNED_INT64(\n v5.m128d_f64[0]\n + COERCE_DOUBLE(*(_OWORD *)&_mm_cmpgt_sd(a2, v5) & 0x3FF0000000000000LL)) | *(_QWORD *)&a2.m128d_f64[0] & 0x8000000000000000LL);\n }\n else\n {\n a2.m128d_f64[0] = v2 + 0.5;\n if ( fabs(a2.m128d_f64[0]) >= 4.503599627370496e15 )\n return (unsigned int)(int)a2.m128d_f64[0];\n v4 = 0LL;\n v4.m128d_f64[0] = (double)(int)a2.m128d_f64[0];\n return (unsigned int)(int)COERCE_DOUBLE(COERCE_UNSIGNED_INT64(\n v4.m128d_f64[0]\n - COERCE_DOUBLE(*(_OWORD *)&_mm_cmpgt_sd(v4, a2) & 0x3FF0000000000000LL)) | *(_QWORD *)&a2.m128d_f64[0] & 0x8000000000000000LL);\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1280(const char *a1, __m128d a2) {\n double v2;\n __m128d v4;\n __m128d v5;\n v2 = strtod(a1, 0LL);\n if (v2 < 0.0) {\n a2.m128d_f64[0] = v2 - 0.5;\n if (fabs(a2.m128d_f64[0]) >= 4.503599627370496e15)\n return (unsigned int)(int)a2.m128d_f64[0];\n v5.m128d_f64[0] = (double)(int)a2.m128d_f64[0];\n return (unsigned int)(int)COERCE_DOUBLE(\n COERCE_UNSIGNED_INT64(\n v5.m128d_f64[0] +\n COERCE_DOUBLE(*(long double *)&_mm_cmpgt_sd(a2, v5) &\n 4607182418800017408LL)) |\n *(uint64_t *)&a2.m128d_f64[0] & 9223372036854775808LL);\n } else {\n a2.m128d_f64[0] = v2 + 0.5;\n if (fabs(a2.m128d_f64[0]) >= 4.503599627370496e15)\n return (unsigned int)(int)a2.m128d_f64[0];\n v4 = 0LL;\n v4.m128d_f64[0] = (double)(int)a2.m128d_f64[0];\n return (unsigned int)(int)COERCE_DOUBLE(\n COERCE_UNSIGNED_INT64(\n v4.m128d_f64[0] -\n COERCE_DOUBLE(*(long double *)&_mm_cmpgt_sd(v4, a2) &\n 4607182418800017408LL)) |\n *(uint64_t *)&a2.m128d_f64[0] & 9223372036854775808LL);\n }\n}", + "ida_pseudo_norm": "long long func0(const char *a1, __m128d a2) {\n double v2;\n __m128d v4;\n __m128d v5;\n v2 = strtod(a1, 0LL);\n if (v2 < 0.0) {\n a2.m128d_f64[0] = v2 - 0.5;\n if (fabs(a2.m128d_f64[0]) >= 4.503599627370496e15)\n return (unsigned int)(int)a2.m128d_f64[0];\n v5.m128d_f64[0] = (double)(int)a2.m128d_f64[0];\n return (unsigned int)(int)COERCE_DOUBLE(\n COERCE_UNSIGNED_INT64(\n v5.m128d_f64[0] +\n COERCE_DOUBLE(*(long double *)&_mm_cmpgt_sd(a2, v5) &\n 4607182418800017408LL)) |\n *(uint64_t *)&a2.m128d_f64[0] & 9223372036854775808LL);\n } else {\n a2.m128d_f64[0] = v2 + 0.5;\n if (fabs(a2.m128d_f64[0]) >= 4.503599627370496e15)\n return (unsigned int)(int)a2.m128d_f64[0];\n v4 = 0LL;\n v4.m128d_f64[0] = (double)(int)a2.m128d_f64[0];\n return (unsigned int)(int)COERCE_DOUBLE(\n COERCE_UNSIGNED_INT64(\n v4.m128d_f64[0] -\n COERCE_DOUBLE(*(long double *)&_mm_cmpgt_sd(v4, a2) &\n 4607182418800017408LL)) |\n *(uint64_t *)&a2.m128d_f64[0] & 9223372036854775808LL);\n }\n}" + }, + { + "index": "HumanEval-C-99", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int func0(const char *value) {\n double w;\n w = atof(value);\n return (int)(w < 0 ? ceil(w - 0.5) : floor(w + 0.5));\n}", + "test": "#include \n\nint main() {\n assert(func0(\"10\") == 10);\n assert(func0(\"14.5\") == 15);\n assert(func0(\"-15.5\") == -16);\n assert(func0(\"15.3\") == 15);\n assert(func0(\"0\") == 0);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\nxor esi, esi; endptr\ncall _strtod\npxor xmm1, xmm1\ncomisd xmm1, xmm0\nja short loc_1310\naddsd xmm0, cs:qword_20A0\nmovsd xmm2, cs:qword_20B8\nmovsd xmm3, cs:qword_20A8\nmovapd xmm1, xmm0\nandpd xmm1, xmm2\nucomisd xmm3, xmm1\nja short loc_12D0\nloc_12BF:\ncvttsd2si eax, xmm0\nadd rsp, 8\nretn\nloc_12D0:\ncvttsd2si rax, xmm0\npxor xmm1, xmm1\nmovsd xmm4, cs:qword_20B0\nandnpd xmm2, xmm0\nadd rsp, 8\ncvtsi2sd xmm1, rax\nmovapd xmm3, xmm1\ncmpnlesd xmm3, xmm0\nandpd xmm3, xmm4\nsubsd xmm1, xmm3\norpd xmm1, xmm2\nmovapd xmm0, xmm1\ncvttsd2si eax, xmm0\nretn\nloc_1310:\nsubsd xmm0, cs:qword_20A0\nmovsd xmm2, cs:qword_20B8\nmovsd xmm3, cs:qword_20A8\nmovapd xmm1, xmm0\nandpd xmm1, xmm2\nucomisd xmm3, xmm1\njbe short loc_12BF\ncvttsd2si rax, xmm0\npxor xmm1, xmm1\nmovapd xmm3, xmm0\nmovsd xmm4, cs:qword_20B0\nandnpd xmm2, xmm0\nadd rsp, 8\ncvtsi2sd xmm1, rax\ncmpnlesd xmm3, xmm1\nandpd xmm3, xmm4\naddsd xmm1, xmm3\norpd xmm1, xmm2\nmovapd xmm0, xmm1\ncvttsd2si eax, xmm0\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, __m128d a2)\n{\n double v2; // xmm0_8\n __m128d v4; // xmm1\n __m128d v5; // xmm1\n\n v2 = strtod(a1, 0LL);\n if ( v2 < 0.0 )\n {\n a2.m128d_f64[0] = v2 - 0.5;\n if ( fabs(a2.m128d_f64[0]) >= 4.503599627370496e15 )\n return (unsigned int)(int)a2.m128d_f64[0];\n v5.m128d_f64[0] = (double)(int)a2.m128d_f64[0];\n return (unsigned int)(int)COERCE_DOUBLE(COERCE_UNSIGNED_INT64(\n v5.m128d_f64[0]\n + COERCE_DOUBLE(*(_OWORD *)&_mm_cmpgt_sd(a2, v5) & 0x3FF0000000000000LL)) | *(_QWORD *)&a2.m128d_f64[0] & 0x8000000000000000LL);\n }\n else\n {\n a2.m128d_f64[0] = v2 + 0.5;\n if ( fabs(a2.m128d_f64[0]) >= 4.503599627370496e15 )\n return (unsigned int)(int)a2.m128d_f64[0];\n v4 = 0LL;\n v4.m128d_f64[0] = (double)(int)a2.m128d_f64[0];\n return (unsigned int)(int)COERCE_DOUBLE(COERCE_UNSIGNED_INT64(\n v4.m128d_f64[0]\n - COERCE_DOUBLE(*(_OWORD *)&_mm_cmpgt_sd(v4, a2) & 0x3FF0000000000000LL)) | *(_QWORD *)&a2.m128d_f64[0] & 0x8000000000000000LL);\n }\n}", + "ida_strip_asm": "sub_1280:\nendbr64\nsub rsp, 8\nxor esi, esi; endptr\ncall _strtod\npxor xmm1, xmm1\ncomisd xmm1, xmm0\nja short loc_1310\naddsd xmm0, cs:qword_20A0\nmovsd xmm2, cs:qword_20B8\nmovsd xmm3, cs:qword_20A8\nmovapd xmm1, xmm0\nandpd xmm1, xmm2\nucomisd xmm3, xmm1\nja short loc_12D0\nloc_12BF:\ncvttsd2si eax, xmm0\nadd rsp, 8\nretn\nloc_12D0:\ncvttsd2si rax, xmm0\npxor xmm1, xmm1\nmovsd xmm4, cs:qword_20B0\nandnpd xmm2, xmm0\nadd rsp, 8\ncvtsi2sd xmm1, rax\nmovapd xmm3, xmm1\ncmpnlesd xmm3, xmm0\nandpd xmm3, xmm4\nsubsd xmm1, xmm3\norpd xmm1, xmm2\nmovapd xmm0, xmm1\ncvttsd2si eax, xmm0\nretn\nloc_1310:\nsubsd xmm0, cs:qword_20A0\nmovsd xmm2, cs:qword_20B8\nmovsd xmm3, cs:qword_20A8\nmovapd xmm1, xmm0\nandpd xmm1, xmm2\nucomisd xmm3, xmm1\njbe short loc_12BF\ncvttsd2si rax, xmm0\npxor xmm1, xmm1\nmovapd xmm3, xmm0\nmovsd xmm4, cs:qword_20B0\nandnpd xmm2, xmm0\nadd rsp, 8\ncvtsi2sd xmm1, rax\ncmpnlesd xmm3, xmm1\nandpd xmm3, xmm4\naddsd xmm1, xmm3\norpd xmm1, xmm2\nmovapd xmm0, xmm1\ncvttsd2si eax, xmm0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1280(const char *a1, __m128d a2)\n{\n double v2; // xmm0_8\n __m128d v4; // xmm1\n __m128d v5; // xmm1\n\n v2 = strtod(a1, 0LL);\n if ( v2 < 0.0 )\n {\n a2.m128d_f64[0] = v2 - 0.5;\n if ( fabs(a2.m128d_f64[0]) >= 4.503599627370496e15 )\n return (unsigned int)(int)a2.m128d_f64[0];\n v5.m128d_f64[0] = (double)(int)a2.m128d_f64[0];\n return (unsigned int)(int)COERCE_DOUBLE(COERCE_UNSIGNED_INT64(\n v5.m128d_f64[0]\n + COERCE_DOUBLE(*(_OWORD *)&_mm_cmpgt_sd(a2, v5) & 0x3FF0000000000000LL)) | *(_QWORD *)&a2.m128d_f64[0] & 0x8000000000000000LL);\n }\n else\n {\n a2.m128d_f64[0] = v2 + 0.5;\n if ( fabs(a2.m128d_f64[0]) >= 4.503599627370496e15 )\n return (unsigned int)(int)a2.m128d_f64[0];\n v4 = 0LL;\n v4.m128d_f64[0] = (double)(int)a2.m128d_f64[0];\n return (unsigned int)(int)COERCE_DOUBLE(COERCE_UNSIGNED_INT64(\n v4.m128d_f64[0]\n - COERCE_DOUBLE(*(_OWORD *)&_mm_cmpgt_sd(v4, a2) & 0x3FF0000000000000LL)) | *(_QWORD *)&a2.m128d_f64[0] & 0x8000000000000000LL);\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1280(const char *a1, __m128d a2) {\n double v2;\n __m128d v4;\n __m128d v5;\n v2 = strtod(a1, 0LL);\n if (v2 < 0.0) {\n a2.m128d_f64[0] = v2 - 0.5;\n if (fabs(a2.m128d_f64[0]) >= 4.503599627370496e15)\n return (unsigned int)(int)a2.m128d_f64[0];\n v5.m128d_f64[0] = (double)(int)a2.m128d_f64[0];\n return (unsigned int)(int)COERCE_DOUBLE(\n COERCE_UNSIGNED_INT64(\n v5.m128d_f64[0] +\n COERCE_DOUBLE(*(long double *)&_mm_cmpgt_sd(a2, v5) &\n 4607182418800017408LL)) |\n *(uint64_t *)&a2.m128d_f64[0] & 9223372036854775808LL);\n } else {\n a2.m128d_f64[0] = v2 + 0.5;\n if (fabs(a2.m128d_f64[0]) >= 4.503599627370496e15)\n return (unsigned int)(int)a2.m128d_f64[0];\n v4 = 0LL;\n v4.m128d_f64[0] = (double)(int)a2.m128d_f64[0];\n return (unsigned int)(int)COERCE_DOUBLE(\n COERCE_UNSIGNED_INT64(\n v4.m128d_f64[0] -\n COERCE_DOUBLE(*(long double *)&_mm_cmpgt_sd(v4, a2) &\n 4607182418800017408LL)) |\n *(uint64_t *)&a2.m128d_f64[0] & 9223372036854775808LL);\n }\n}", + "ida_pseudo_norm": "long long func0(const char *a1, __m128d a2) {\n double v2;\n __m128d v4;\n __m128d v5;\n v2 = strtod(a1, 0LL);\n if (v2 < 0.0) {\n a2.m128d_f64[0] = v2 - 0.5;\n if (fabs(a2.m128d_f64[0]) >= 4.503599627370496e15)\n return (unsigned int)(int)a2.m128d_f64[0];\n v5.m128d_f64[0] = (double)(int)a2.m128d_f64[0];\n return (unsigned int)(int)COERCE_DOUBLE(\n COERCE_UNSIGNED_INT64(\n v5.m128d_f64[0] +\n COERCE_DOUBLE(*(long double *)&_mm_cmpgt_sd(a2, v5) &\n 4607182418800017408LL)) |\n *(uint64_t *)&a2.m128d_f64[0] & 9223372036854775808LL);\n } else {\n a2.m128d_f64[0] = v2 + 0.5;\n if (fabs(a2.m128d_f64[0]) >= 4.503599627370496e15)\n return (unsigned int)(int)a2.m128d_f64[0];\n v4 = 0LL;\n v4.m128d_f64[0] = (double)(int)a2.m128d_f64[0];\n return (unsigned int)(int)COERCE_DOUBLE(\n COERCE_UNSIGNED_INT64(\n v4.m128d_f64[0] -\n COERCE_DOUBLE(*(long double *)&_mm_cmpgt_sd(v4, a2) &\n 4607182418800017408LL)) |\n *(uint64_t *)&a2.m128d_f64[0] & 9223372036854775808LL);\n }\n}" + }, + { + "index": "HumanEval-C-100", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int* func0(int n) {\n int* out = (int*)malloc(n * sizeof(int));\n *out = n;\n for (int i = 1; i < n; i++) *(out + i) = *(out + i - 1) + 2;\n return out;\n}", + "test": "#include \n#include \n\nint main() {\n int* result;\n int test1[] = {3, 5, 7};\n int test2[] = {4, 6, 8, 10};\n int test3[] = {5, 7, 9, 11, 13};\n int test4[] = {6, 8, 10, 12, 14, 16};\n int test5[] = {8, 10, 12, 14, 16, 18, 20, 22};\n\n result = func0(3);\n for (int i = 0; i < 3; i++) assert(result[i] == test1[i]);\n free(result);\n\n result = func0(4);\n for (int i = 0; i < 4; i++) assert(result[i] == test2[i]);\n free(result);\n\n result = func0(5);\n for (int i = 0; i < 5; i++) assert(result[i] == test3[i]);\n free(result);\n\n result = func0(6);\n for (int i = 0; i < 6; i++) assert(result[i] == test4[i]);\n free(result);\n\n result = func0(8);\n for (int i = 0; i < 8; i++) assert(result[i] == test5[i]);\n free(result);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov eax, [rbp+var_14]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov rax, [rbp+var_8]\nmov edx, [rbp+var_14]\nmov [rax], edx\nmov [rbp+var_C], 1\njmp short loc_1212\nloc_11DF:\nmov eax, [rbp+var_C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rcx\nadd edx, 2\nmov [rax], edx\nadd [rbp+var_C], 1\nloc_1212:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_14]\njl short loc_11DF\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int a1)\n{\n int i; // [rsp+14h] [rbp-Ch]\n _DWORD *v3; // [rsp+18h] [rbp-8h]\n\n v3 = malloc(4LL * a1);\n *v3 = a1;\n for ( i = 1; i < a1; ++i )\n v3[i] = v3[i - 1] + 2;\n return v3;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov eax, [rbp+var_14]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov rax, [rbp+var_8]\nmov edx, [rbp+var_14]\nmov [rax], edx\nmov [rbp+var_C], 1\njmp short loc_1212\nloc_11DF:\nmov eax, [rbp+var_C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rcx\nadd edx, 2\nmov [rax], edx\nadd [rbp+var_C], 1\nloc_1212:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_14]\njl short loc_11DF\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(int a1)\n{\n int i; // [rsp+14h] [rbp-Ch]\n _DWORD *v3; // [rsp+18h] [rbp-8h]\n\n v3 = malloc(4LL * a1);\n *v3 = a1;\n for ( i = 1; i < a1; ++i )\n v3[i] = v3[i - 1] + 2;\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(int a1) {\n int i;\n uint32_t *v3;\n v3 = malloc(4LL * a1);\n *v3 = a1;\n for (i = 1; i < a1; ++i) v3[i] = v3[i - 1] + 2;\n return v3;\n}", + "ida_pseudo_norm": "uint32_t *func0(int a1) {\n int i;\n uint32_t *v3;\n v3 = malloc(4LL * a1);\n *v3 = a1;\n for (i = 1; i < a1; ++i) v3[i] = v3[i - 1] + 2;\n return v3;\n}" + }, + { + "index": "HumanEval-C-100", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int* func0(int n) {\n int* out = (int*)malloc(n * sizeof(int));\n *out = n;\n for (int i = 1; i < n; i++) *(out + i) = *(out + i - 1) + 2;\n return out;\n}", + "test": "#include \n#include \n\nint main() {\n int* result;\n int test1[] = {3, 5, 7};\n int test2[] = {4, 6, 8, 10};\n int test3[] = {5, 7, 9, 11, 13};\n int test4[] = {6, 8, 10, 12, 14, 16};\n int test5[] = {8, 10, 12, 14, 16, 18, 20, 22};\n\n result = func0(3);\n for (int i = 0; i < 3; i++) assert(result[i] == test1[i]);\n free(result);\n\n result = func0(4);\n for (int i = 0; i < 4; i++) assert(result[i] == test2[i]);\n free(result);\n\n result = func0(5);\n for (int i = 0; i < 5; i++) assert(result[i] == test3[i]);\n free(result);\n\n result = func0(6);\n for (int i = 0; i < 6; i++) assert(result[i] == test4[i]);\n free(result);\n\n result = func0(8);\n for (int i = 0; i < 8; i++) assert(result[i] == test5[i]);\n free(result);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbx\nmov ebx, edi\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov [rax], ebx\ncmp ebx, 1\njle short loc_11DE\nmov rdx, rax\nlea ecx, [rbx-1]\nlea rsi, [rax+rcx*4]\nloc_11CD:\nmov ebx, [rdx]\nlea ecx, [rbx+2]\nmov [rdx+4], ecx\nadd rdx, 4\ncmp rdx, rsi\njnz short loc_11CD\nloc_11DE:\npop rbx\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int a1)\n{\n _DWORD *result; // rax\n _DWORD *v2; // rdx\n\n result = malloc(4LL * a1);\n *result = a1;\n if ( a1 > 1 )\n {\n v2 = result;\n do\n {\n v2[1] = *v2 + 2;\n ++v2;\n }\n while ( v2 != &result[a1 - 1] );\n }\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbx\nmov ebx, edi\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov [rax], ebx\ncmp ebx, 1\njle short loc_11DE\nmov rdx, rax\nlea ecx, [rbx-1]\nlea rsi, [rax+rcx*4]\nloc_11CD:\nmov ebx, [rdx]\nlea ecx, [rbx+2]\nmov [rdx+4], ecx\nadd rdx, 4\ncmp rdx, rsi\njnz short loc_11CD\nloc_11DE:\npop rbx\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(int a1)\n{\n _DWORD *result; // rax\n _DWORD *v2; // rdx\n\n result = malloc(4LL * a1);\n *result = a1;\n if ( a1 > 1 )\n {\n v2 = result;\n do\n {\n v2[1] = *v2 + 2;\n ++v2;\n }\n while ( v2 != &result[a1 - 1] );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(int a1) {\n uint32_t *result;\n uint32_t *v2;\n result = malloc(4LL * a1);\n *result = a1;\n if (a1 > 1) {\n v2 = result;\n do {\n v2[1] = *v2 + 2;\n ++v2;\n } while (v2 != &result[a1 - 1]);\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(int a1) {\n uint32_t *result;\n uint32_t *v2;\n result = malloc(4LL * a1);\n *result = a1;\n if (a1 > 1) {\n v2 = result;\n do {\n v2[1] = *v2 + 2;\n ++v2;\n } while (v2 != &result[a1 - 1]);\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-100", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int* func0(int n) {\n int* out = (int*)malloc(n * sizeof(int));\n *out = n;\n for (int i = 1; i < n; i++) *(out + i) = *(out + i - 1) + 2;\n return out;\n}", + "test": "#include \n#include \n\nint main() {\n int* result;\n int test1[] = {3, 5, 7};\n int test2[] = {4, 6, 8, 10};\n int test3[] = {5, 7, 9, 11, 13};\n int test4[] = {6, 8, 10, 12, 14, 16};\n int test5[] = {8, 10, 12, 14, 16, 18, 20, 22};\n\n result = func0(3);\n for (int i = 0; i < 3; i++) assert(result[i] == test1[i]);\n free(result);\n\n result = func0(4);\n for (int i = 0; i < 4; i++) assert(result[i] == test2[i]);\n free(result);\n\n result = func0(5);\n for (int i = 0; i < 5; i++) assert(result[i] == test3[i]);\n free(result);\n\n result = func0(6);\n for (int i = 0; i < 6; i++) assert(result[i] == test4[i]);\n free(result);\n\n result = func0(8);\n for (int i = 0; i < 8; i++) assert(result[i] == test5[i]);\n free(result);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbx\nmovsxd rdi, edi\nmov rbx, rdi\nshl rdi, 2; size\ncall _malloc\nmov [rax], ebx\ncmp ebx, 1\njle short loc_140F\nlea ecx, [rbx-2]\nlea rdx, [rax+4]\nlea rcx, [rax+rcx*4+8]\nnop word ptr [rax+rax+00000000h]\nloc_1400:\nadd ebx, 2\nadd rdx, 4\nmov [rdx-4], ebx\ncmp rdx, rcx\njnz short loc_1400\nloc_140F:\npop rbx\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int a1)\n{\n int v1; // ebx\n _DWORD *result; // rax\n _DWORD *v3; // rdx\n\n v1 = a1;\n result = malloc(4LL * a1);\n *result = a1;\n if ( a1 > 1 )\n {\n v3 = result + 1;\n do\n {\n v1 += 2;\n *v3++ = v1;\n }\n while ( v3 != &result[a1 - 2 + 2] );\n }\n return result;\n}", + "ida_strip_asm": "sub_13D0:\nendbr64\npush rbx\nmovsxd rdi, edi\nmov rbx, rdi\nshl rdi, 2; size\ncall _malloc\nmov [rax], ebx\ncmp ebx, 1\njle short loc_140F\nlea ecx, [rbx-2]\nlea rdx, [rax+4]\nlea rcx, [rax+rcx*4+8]\nnop word ptr [rax+rax+00000000h]\nloc_1400:\nadd ebx, 2\nadd rdx, 4\nmov [rdx-4], ebx\ncmp rdx, rcx\njnz short loc_1400\nloc_140F:\npop rbx\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_13D0(int a1)\n{\n int v1; // ebx\n _DWORD *result; // rax\n _DWORD *v3; // rdx\n\n v1 = a1;\n result = malloc(4LL * a1);\n *result = a1;\n if ( a1 > 1 )\n {\n v3 = result + 1;\n do\n {\n v1 += 2;\n *v3++ = v1;\n }\n while ( v3 != &result[a1 - 2 + 2] );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_13D0(int a1) {\n int v1;\n uint32_t *result;\n uint32_t *v3;\n v1 = a1;\n result = malloc(4LL * a1);\n *result = a1;\n if (a1 > 1) {\n v3 = result + 1;\n do {\n v1 += 2;\n *v3++ = v1;\n } while (v3 != &result[a1 - 2 + 2]);\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(int a1) {\n int v1;\n uint32_t *result;\n uint32_t *v3;\n v1 = a1;\n result = malloc(4LL * a1);\n *result = a1;\n if (a1 > 1) {\n v3 = result + 1;\n do {\n v1 += 2;\n *v3++ = v1;\n } while (v3 != &result[a1 - 2 + 2]);\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-100", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int* func0(int n) {\n int* out = (int*)malloc(n * sizeof(int));\n *out = n;\n for (int i = 1; i < n; i++) *(out + i) = *(out + i - 1) + 2;\n return out;\n}", + "test": "#include \n#include \n\nint main() {\n int* result;\n int test1[] = {3, 5, 7};\n int test2[] = {4, 6, 8, 10};\n int test3[] = {5, 7, 9, 11, 13};\n int test4[] = {6, 8, 10, 12, 14, 16};\n int test5[] = {8, 10, 12, 14, 16, 18, 20, 22};\n\n result = func0(3);\n for (int i = 0; i < 3; i++) assert(result[i] == test1[i]);\n free(result);\n\n result = func0(4);\n for (int i = 0; i < 4; i++) assert(result[i] == test2[i]);\n free(result);\n\n result = func0(5);\n for (int i = 0; i < 5; i++) assert(result[i] == test3[i]);\n free(result);\n\n result = func0(6);\n for (int i = 0; i < 6; i++) assert(result[i] == test4[i]);\n free(result);\n\n result = func0(8);\n for (int i = 0; i < 8; i++) assert(result[i] == test5[i]);\n free(result);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbx\nmovsxd rdi, edi\nmov rbx, rdi\nshl rdi, 2; size\ncall _malloc\nmov [rax], ebx\ncmp ebx, 1\njle short loc_13AF\nlea ecx, [rbx-2]\nlea rdx, [rax+4]\nlea rcx, [rax+rcx*4+8]\nnop word ptr [rax+rax+00000000h]\nloc_13A0:\nadd ebx, 2\nadd rdx, 4\nmov [rdx-4], ebx\ncmp rdx, rcx\njnz short loc_13A0\nloc_13AF:\npop rbx\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int a1)\n{\n int v1; // ebx\n _DWORD *result; // rax\n _DWORD *v3; // rdx\n\n v1 = a1;\n result = malloc(4LL * a1);\n *result = a1;\n if ( a1 > 1 )\n {\n v3 = result + 1;\n do\n {\n v1 += 2;\n *v3++ = v1;\n }\n while ( v3 != &result[a1 - 2 + 2] );\n }\n return result;\n}", + "ida_strip_asm": "sub_1370:\nendbr64\npush rbx\nmovsxd rdi, edi\nmov rbx, rdi\nshl rdi, 2; size\ncall _malloc\nmov [rax], ebx\ncmp ebx, 1\njle short loc_13AF\nlea ecx, [rbx-2]\nlea rdx, [rax+4]\nlea rcx, [rax+rcx*4+8]\nnop word ptr [rax+rax+00000000h]\nloc_13A0:\nadd ebx, 2\nadd rdx, 4\nmov [rdx-4], ebx\ncmp rdx, rcx\njnz short loc_13A0\nloc_13AF:\npop rbx\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1370(int a1)\n{\n int v1; // ebx\n _DWORD *result; // rax\n _DWORD *v3; // rdx\n\n v1 = a1;\n result = malloc(4LL * a1);\n *result = a1;\n if ( a1 > 1 )\n {\n v3 = result + 1;\n do\n {\n v1 += 2;\n *v3++ = v1;\n }\n while ( v3 != &result[a1 - 2 + 2] );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1370(int a1) {\n int v1;\n uint32_t *result;\n uint32_t *v3;\n v1 = a1;\n result = malloc(4LL * a1);\n *result = a1;\n if (a1 > 1) {\n v3 = result + 1;\n do {\n v1 += 2;\n *v3++ = v1;\n } while (v3 != &result[a1 - 2 + 2]);\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(int a1) {\n int v1;\n uint32_t *result;\n uint32_t *v3;\n v1 = a1;\n result = malloc(4LL * a1);\n *result = a1;\n if (a1 > 1) {\n v3 = result + 1;\n do {\n v1 += 2;\n *v3++ = v1;\n } while (v3 != &result[a1 - 2 + 2]);\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-101", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char** func0(const char* s, int* count) {\n int capacity = 10;\n char** out = malloc(capacity * sizeof(char*));\n char* current = malloc(strlen(s) + 1);\n int word_count = 0;\n int current_length = 0;\n for (int i = 0; s[i]; i++) {\n if (s[i] == ' ' || s[i] == ',') {\n if (current_length > 0) {\n current[current_length] = '\\0';\n out[word_count++] = strdup(current);\n current_length = 0;\n if (word_count >= capacity) {\n capacity *= 2;\n out = realloc(out, capacity * sizeof(char*));\n }\n }\n } else {\n current[current_length++] = s[i];\n }\n }\n if (current_length > 0) {\n current[current_length] = '\\0';\n out[word_count++] = strdup(current);\n }\n free(current);\n *count = word_count;\n return out;\n}", + "test": "#include \n#include \n#include \n#include \n\nbool issame(char** a, int a_count, char** b, int b_count) {\n if (a_count != b_count) return false;\n for (int i = 0; i < a_count; i++) {\n if (strcmp(a[i], b[i]) != 0) return false;\n }\n return true;\n}\n\nvoid free_words(char** words, int count) {\n for (int i = 0; i < count; i++)\n free(words[i]);\n free(words);\n}\n\nint main() {\n int count;\n char** result;\n\n char* expected1[] = {\"Hi\", \"my\", \"name\", \"is\", \"John\"};\n result = func0(\"Hi, my name is John\", &count);\n assert(issame(result, count, expected1, 5));\n free_words(result, count);\n\n char* expected2[] = {\"One\", \"two\", \"three\", \"four\", \"five\", \"six\"};\n result = func0(\"One, two, three, four, five, six\", &count);\n assert(issame(result, count, expected2, 6));\n free_words(result, count);\n\n char* expected3[] = {\"Hi\", \"my\", \"name\"};\n result = func0(\"Hi, my name\", &count);\n assert(issame(result, count, expected3, 3));\n free_words(result, count);\n\n char* expected4[] = {\"One\", \"two\", \"three\", \"four\", \"five\", \"six\"};\n result = func0(\"One,, two, three, four, five, six,\", &count);\n assert(issame(result, count, expected4, 6));\n free_words(result, count);\n\n char* expected5[] = {};\n result = func0(\"\", &count);\n assert(issame(result, count, expected5, 0));\n free_words(result, count);\n\n char* expected6[] = {\"ahmed\", \"gamal\"};\n result = func0(\"ahmed , gamal\", &count);\n assert(issame(result, count, expected6, 2));\n free_words(result, count);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+s], rdi\nmov [rbp+var_40], rsi\nmov [rbp+var_30], 0Ah\nmov eax, [rbp+var_30]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nadd rax, 1\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_2C], 0\nmov [rbp+var_28], 0\nmov [rbp+var_24], 0\njmp loc_135D\nloc_1290:\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njz short loc_12B8\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 2Ch ; ','\njnz short loc_1330\nloc_12B8:\ncmp [rbp+var_28], 0\njle loc_1358\nmov eax, [rbp+var_28]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov eax, [rbp+var_2C]\nlea edx, [rax+1]\nmov [rbp+var_2C], edx\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nlea rbx, [rdx+rax]\nmov rax, [rbp+var_18]\nmov rdi, rax; s\ncall _strdup\nmov [rbx], rax\nmov [rbp+var_28], 0\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_30]\njl short loc_1358\nshl [rbp+var_30], 1\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nmov rsi, rdx; size\nmov rdi, rax; ptr\ncall _realloc\nmov [rbp+ptr], rax\njmp short loc_1358\nloc_1330:\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_28]\nlea edx, [rax+1]\nmov [rbp+var_28], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmovzx eax, byte ptr [rcx]\nmov [rdx], al\njmp short loc_1359\nloc_1358:\nnop\nloc_1359:\nadd [rbp+var_24], 1\nloc_135D:\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_1290\ncmp [rbp+var_28], 0\njle short loc_13B5\nmov eax, [rbp+var_28]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov eax, [rbp+var_2C]\nlea edx, [rax+1]\nmov [rbp+var_2C], edx\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nlea rbx, [rdx+rax]\nmov rax, [rbp+var_18]\nmov rdi, rax; s\ncall _strdup\nmov [rbx], rax\nloc_13B5:\nmov rax, [rbp+var_18]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_40]\nmov edx, [rbp+var_2C]\nmov [rax], edx\nmov rax, [rbp+ptr]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(const char *a1, int *a2)\n{\n size_t v2; // rax\n int v3; // eax\n int v4; // eax\n int v5; // eax\n int v7; // [rsp+10h] [rbp-30h]\n int v8; // [rsp+14h] [rbp-2Ch]\n int v9; // [rsp+18h] [rbp-28h]\n int i; // [rsp+1Ch] [rbp-24h]\n _QWORD *ptr; // [rsp+20h] [rbp-20h]\n char *v12; // [rsp+28h] [rbp-18h]\n\n v7 = 10;\n ptr = malloc(0x50uLL);\n v2 = strlen(a1);\n v12 = (char *)malloc(v2 + 1);\n v8 = 0;\n v9 = 0;\n for ( i = 0; a1[i]; ++i )\n {\n if ( a1[i] == 32 || a1[i] == 44 )\n {\n if ( v9 > 0 )\n {\n v12[v9] = 0;\n v3 = v8++;\n ptr[v3] = strdup(v12);\n v9 = 0;\n if ( v8 >= v7 )\n {\n v7 *= 2;\n ptr = realloc(ptr, 8LL * v7);\n }\n }\n }\n else\n {\n v4 = v9++;\n v12[v4] = a1[i];\n }\n }\n if ( v9 > 0 )\n {\n v12[v9] = 0;\n v5 = v8++;\n ptr[v5] = strdup(v12);\n }\n free(v12);\n *a2 = v8;\n return ptr;\n}", + "ida_strip_asm": "sub_1229:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+s], rdi\nmov [rbp+var_40], rsi\nmov [rbp+var_30], 0Ah\nmov eax, [rbp+var_30]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nadd rax, 1\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_2C], 0\nmov [rbp+var_28], 0\nmov [rbp+var_24], 0\njmp loc_135D\nloc_1290:\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njz short loc_12B8\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 2Ch ; ','\njnz short loc_1330\nloc_12B8:\ncmp [rbp+var_28], 0\njle loc_1358\nmov eax, [rbp+var_28]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov eax, [rbp+var_2C]\nlea edx, [rax+1]\nmov [rbp+var_2C], edx\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nlea rbx, [rdx+rax]\nmov rax, [rbp+var_18]\nmov rdi, rax; s\ncall _strdup\nmov [rbx], rax\nmov [rbp+var_28], 0\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_30]\njl short loc_1358\nshl [rbp+var_30], 1\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nmov rsi, rdx; size\nmov rdi, rax; ptr\ncall _realloc\nmov [rbp+ptr], rax\njmp short loc_1358\nloc_1330:\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_28]\nlea edx, [rax+1]\nmov [rbp+var_28], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmovzx eax, byte ptr [rcx]\nmov [rdx], al\njmp short loc_1359\nloc_1358:\nnop\nloc_1359:\nadd [rbp+var_24], 1\nloc_135D:\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_1290\ncmp [rbp+var_28], 0\njle short loc_13B5\nmov eax, [rbp+var_28]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov eax, [rbp+var_2C]\nlea edx, [rax+1]\nmov [rbp+var_2C], edx\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nlea rbx, [rdx+rax]\nmov rax, [rbp+var_18]\nmov rdi, rax; s\ncall _strdup\nmov [rbx], rax\nloc_13B5:\nmov rax, [rbp+var_18]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_40]\nmov edx, [rbp+var_2C]\nmov [rax], edx\nmov rax, [rbp+ptr]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1229(const char *a1, int *a2)\n{\n size_t v2; // rax\n int v3; // eax\n int v4; // eax\n int v5; // eax\n int v7; // [rsp+10h] [rbp-30h]\n int v8; // [rsp+14h] [rbp-2Ch]\n int v9; // [rsp+18h] [rbp-28h]\n int i; // [rsp+1Ch] [rbp-24h]\n _QWORD *ptr; // [rsp+20h] [rbp-20h]\n char *v12; // [rsp+28h] [rbp-18h]\n\n v7 = 10;\n ptr = malloc(0x50uLL);\n v2 = strlen(a1);\n v12 = (char *)malloc(v2 + 1);\n v8 = 0;\n v9 = 0;\n for ( i = 0; a1[i]; ++i )\n {\n if ( a1[i] == 32 || a1[i] == 44 )\n {\n if ( v9 > 0 )\n {\n v12[v9] = 0;\n v3 = v8++;\n ptr[v3] = strdup(v12);\n v9 = 0;\n if ( v8 >= v7 )\n {\n v7 *= 2;\n ptr = realloc(ptr, 8LL * v7);\n }\n }\n }\n else\n {\n v4 = v9++;\n v12[v4] = a1[i];\n }\n }\n if ( v9 > 0 )\n {\n v12[v9] = 0;\n v5 = v8++;\n ptr[v5] = strdup(v12);\n }\n free(v12);\n *a2 = v8;\n return ptr;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1229(const char *a1, int *a2) {\n unsigned int v2;\n int v3;\n int v4;\n int v5;\n int v7;\n int v8;\n int v9;\n int i;\n uint64_t *ptr;\n char *v12;\n v7 = 10;\n ptr = malloc(80uLL);\n v2 = strlen(a1);\n v12 = (char *)malloc(v2 + 1);\n v8 = 0;\n v9 = 0;\n for (i = 0; a1[i]; ++i) {\n if (a1[i] == 32 || a1[i] == 44) {\n if (v9 > 0) {\n v12[v9] = 0;\n v3 = v8++;\n ptr[v3] = strdup(v12);\n v9 = 0;\n if (v8 >= v7) {\n v7 *= 2;\n ptr = realloc(ptr, 8LL * v7);\n }\n }\n } else {\n v4 = v9++;\n v12[v4] = a1[i];\n }\n }\n if (v9 > 0) {\n v12[v9] = 0;\n v5 = v8++;\n ptr[v5] = strdup(v12);\n }\n free(v12);\n *a2 = v8;\n return ptr;\n}", + "ida_pseudo_norm": "uint64_t *func0(const char *a1, int *a2) {\n unsigned int v2;\n int v3;\n int v4;\n int v5;\n int v7;\n int v8;\n int v9;\n int i;\n uint64_t *ptr;\n char *v12;\n v7 = 10;\n ptr = malloc(80uLL);\n v2 = strlen(a1);\n v12 = (char *)malloc(v2 + 1);\n v8 = 0;\n v9 = 0;\n for (i = 0; a1[i]; ++i) {\n if (a1[i] == 32 || a1[i] == 44) {\n if (v9 > 0) {\n v12[v9] = 0;\n v3 = v8++;\n ptr[v3] = strdup(v12);\n v9 = 0;\n if (v8 >= v7) {\n v7 *= 2;\n ptr = realloc(ptr, 8LL * v7);\n }\n }\n } else {\n v4 = v9++;\n v12[v4] = a1[i];\n }\n }\n if (v9 > 0) {\n v12[v9] = 0;\n v5 = v8++;\n ptr[v5] = strdup(v12);\n }\n free(v12);\n *a2 = v8;\n return ptr;\n}" + }, + { + "index": "HumanEval-C-101", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char** func0(const char* s, int* count) {\n int capacity = 10;\n char** out = malloc(capacity * sizeof(char*));\n char* current = malloc(strlen(s) + 1);\n int word_count = 0;\n int current_length = 0;\n for (int i = 0; s[i]; i++) {\n if (s[i] == ' ' || s[i] == ',') {\n if (current_length > 0) {\n current[current_length] = '\\0';\n out[word_count++] = strdup(current);\n current_length = 0;\n if (word_count >= capacity) {\n capacity *= 2;\n out = realloc(out, capacity * sizeof(char*));\n }\n }\n } else {\n current[current_length++] = s[i];\n }\n }\n if (current_length > 0) {\n current[current_length] = '\\0';\n out[word_count++] = strdup(current);\n }\n free(current);\n *count = word_count;\n return out;\n}", + "test": "#include \n#include \n#include \n#include \n\nbool issame(char** a, int a_count, char** b, int b_count) {\n if (a_count != b_count) return false;\n for (int i = 0; i < a_count; i++) {\n if (strcmp(a[i], b[i]) != 0) return false;\n }\n return true;\n}\n\nvoid free_words(char** words, int count) {\n for (int i = 0; i < count; i++)\n free(words[i]);\n free(words);\n}\n\nint main() {\n int count;\n char** result;\n\n char* expected1[] = {\"Hi\", \"my\", \"name\", \"is\", \"John\"};\n result = func0(\"Hi, my name is John\", &count);\n assert(issame(result, count, expected1, 5));\n free_words(result, count);\n\n char* expected2[] = {\"One\", \"two\", \"three\", \"four\", \"five\", \"six\"};\n result = func0(\"One, two, three, four, five, six\", &count);\n assert(issame(result, count, expected2, 6));\n free_words(result, count);\n\n char* expected3[] = {\"Hi\", \"my\", \"name\"};\n result = func0(\"Hi, my name\", &count);\n assert(issame(result, count, expected3, 3));\n free_words(result, count);\n\n char* expected4[] = {\"One\", \"two\", \"three\", \"four\", \"five\", \"six\"};\n result = func0(\"One,, two, three, four, five, six,\", &count);\n assert(issame(result, count, expected4, 6));\n free_words(result, count);\n\n char* expected5[] = {};\n result = func0(\"\", &count);\n assert(issame(result, count, expected5, 0));\n free_words(result, count);\n\n char* expected6[] = {\"ahmed\", \"gamal\"};\n result = func0(\"ahmed , gamal\", &count);\n assert(issame(result, count, expected6, 2));\n free_words(result, count);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov rbx, rdi\nmov [rsp+48h+var_40], rsi\nmov edi, 50h ; 'P'; size\ncall _malloc\nmov r13, rax\nmov rdi, rbx; s\ncall _strlen\nlea rdi, [rax+1]; size\ncall _malloc\nmov r12, rax\nmovzx eax, byte ptr [rbx]\ntest al, al\njz loc_1330\nadd rbx, 1\nmov edx, 0\nmov ebp, 0\nmov r15d, 0Ah\njmp short loc_129B\nloc_1285:\nmovsxd rcx, edx\nmov [r12+rcx], al\nlea edx, [rdx+1]\nloc_128F:\nadd rbx, 1\nmovzx eax, byte ptr [rbx-1]\ntest al, al\njz short loc_12EC\nloc_129B:\ncmp al, 20h ; ' '\njz short loc_12A3\ncmp al, 2Ch ; ','\njnz short loc_1285\nloc_12A3:\ntest edx, edx\njle short loc_128F\nmovsxd rdx, edx\nmov byte ptr [r12+rdx], 0\nlea r14d, [rbp+1]\nmov rdi, r12; s\ncall _strdup\nmovsxd rbp, ebp\nmov [r13+rbp*8+0], rax\nmov ebp, r14d\nmov edx, 0\ncmp r14d, r15d\njl short loc_128F\nadd r15d, r15d\nmovsxd rsi, r15d\nshl rsi, 3; size\nmov rdi, r13; ptr\ncall _realloc\nmov r13, rax\nmov edx, 0\njmp short loc_128F\nloc_12EC:\ntest edx, edx\njg short loc_1311\nloc_12F0:\nmov rdi, r12; ptr\ncall _free\nmov rax, [rsp+48h+var_40]\nmov [rax], ebp\nmov rax, r13\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1311:\nmovsxd rdx, edx\nmov byte ptr [r12+rdx], 0\nlea ebx, [rbp+1]\nmov rdi, r12; s\ncall _strdup\nmovsxd rbp, ebp\nmov [r13+rbp*8+0], rax\nmov ebp, ebx\njmp short loc_12F0\nloc_1330:\nmov ebp, 0\njmp short loc_12F0", + "ida_pseudo": "_QWORD *__fastcall func0(char *s, int *a2)\n{\n _QWORD *v2; // r13\n size_t v3; // rax\n char *v4; // r12\n char v5; // al\n char *v6; // rbx\n int v7; // edx\n int v8; // ebp\n int v9; // r15d\n\n v2 = malloc(0x50uLL);\n v3 = strlen(s);\n v4 = (char *)malloc(v3 + 1);\n v5 = *s;\n if ( *s )\n {\n v6 = s + 1;\n v7 = 0;\n v8 = 0;\n v9 = 10;\n do\n {\n if ( v5 == 32 || v5 == 44 )\n {\n if ( v7 > 0 )\n {\n v4[v7] = 0;\n v2[v8++] = strdup(v4);\n v7 = 0;\n if ( v8 >= v9 )\n {\n v9 *= 2;\n v2 = realloc(v2, 8LL * v9);\n v7 = 0;\n }\n }\n }\n else\n {\n v4[v7++] = v5;\n }\n v5 = *v6++;\n }\n while ( v5 );\n if ( v7 > 0 )\n {\n v4[v7] = 0;\n v2[v8++] = strdup(v4);\n }\n }\n else\n {\n v8 = 0;\n }\n free(v4);\n *a2 = v8;\n return v2;\n}", + "ida_strip_asm": "sub_1229:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov rbx, rdi\nmov [rsp+48h+var_40], rsi\nmov edi, 50h ; 'P'; size\ncall _malloc\nmov r13, rax\nmov rdi, rbx; s\ncall _strlen\nlea rdi, [rax+1]; size\ncall _malloc\nmov r12, rax\nmovzx eax, byte ptr [rbx]\ntest al, al\njz loc_1330\nadd rbx, 1\nmov edx, 0\nmov ebp, 0\nmov r15d, 0Ah\njmp short loc_129B\nloc_1285:\nmovsxd rcx, edx\nmov [r12+rcx], al\nlea edx, [rdx+1]\nloc_128F:\nadd rbx, 1\nmovzx eax, byte ptr [rbx-1]\ntest al, al\njz short loc_12EC\nloc_129B:\ncmp al, 20h ; ' '\njz short loc_12A3\ncmp al, 2Ch ; ','\njnz short loc_1285\nloc_12A3:\ntest edx, edx\njle short loc_128F\nmovsxd rdx, edx\nmov byte ptr [r12+rdx], 0\nlea r14d, [rbp+1]\nmov rdi, r12; s\ncall _strdup\nmovsxd rbp, ebp\nmov [r13+rbp*8+0], rax\nmov ebp, r14d\nmov edx, 0\ncmp r14d, r15d\njl short loc_128F\nadd r15d, r15d\nmovsxd rsi, r15d\nshl rsi, 3; size\nmov rdi, r13; ptr\ncall _realloc\nmov r13, rax\nmov edx, 0\njmp short loc_128F\nloc_12EC:\ntest edx, edx\njg short loc_1311\nloc_12F0:\nmov rdi, r12; ptr\ncall _free\nmov rax, [rsp+48h+var_40]\nmov [rax], ebp\nmov rax, r13\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1311:\nmovsxd rdx, edx\nmov byte ptr [r12+rdx], 0\nlea ebx, [rbp+1]\nmov rdi, r12; s\ncall _strdup\nmovsxd rbp, ebp\nmov [r13+rbp*8+0], rax\nmov ebp, ebx\njmp short loc_12F0\nloc_1330:\nmov ebp, 0\njmp short loc_12F0", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1229(char *s, int *a2)\n{\n _QWORD *v2; // r13\n size_t v3; // rax\n char *v4; // r12\n char v5; // al\n char *v6; // rbx\n int v7; // edx\n int v8; // ebp\n int v9; // r15d\n\n v2 = malloc(0x50uLL);\n v3 = strlen(s);\n v4 = (char *)malloc(v3 + 1);\n v5 = *s;\n if ( *s )\n {\n v6 = s + 1;\n v7 = 0;\n v8 = 0;\n v9 = 10;\n do\n {\n if ( v5 == 32 || v5 == 44 )\n {\n if ( v7 > 0 )\n {\n v4[v7] = 0;\n v2[v8++] = strdup(v4);\n v7 = 0;\n if ( v8 >= v9 )\n {\n v9 *= 2;\n v2 = realloc(v2, 8LL * v9);\n v7 = 0;\n }\n }\n }\n else\n {\n v4[v7++] = v5;\n }\n v5 = *v6++;\n }\n while ( v5 );\n if ( v7 > 0 )\n {\n v4[v7] = 0;\n v2[v8++] = strdup(v4);\n }\n }\n else\n {\n v8 = 0;\n }\n free(v4);\n *a2 = v8;\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1229(char *s, int *a2) {\n uint64_t *v2;\n unsigned int v3;\n char *v4;\n char v5;\n char *v6;\n int v7;\n int v8;\n int v9;\n v2 = malloc(80uLL);\n v3 = strlen(s);\n v4 = (char *)malloc(v3 + 1);\n v5 = *s;\n if (*s) {\n v6 = s + 1;\n v7 = 0;\n v8 = 0;\n v9 = 10;\n do {\n if (v5 == 32 || v5 == 44) {\n if (v7 > 0) {\n v4[v7] = 0;\n v2[v8++] = strdup(v4);\n v7 = 0;\n if (v8 >= v9) {\n v9 *= 2;\n v2 = realloc(v2, 8LL * v9);\n v7 = 0;\n }\n }\n } else {\n v4[v7++] = v5;\n }\n v5 = *v6++;\n } while (v5);\n if (v7 > 0) {\n v4[v7] = 0;\n v2[v8++] = strdup(v4);\n }\n } else {\n v8 = 0;\n }\n free(v4);\n *a2 = v8;\n return v2;\n}", + "ida_pseudo_norm": "uint64_t *func0(char *s, int *a2) {\n uint64_t *v2;\n unsigned int v3;\n char *v4;\n char v5;\n char *v6;\n int v7;\n int v8;\n int v9;\n v2 = malloc(80uLL);\n v3 = strlen(s);\n v4 = (char *)malloc(v3 + 1);\n v5 = *s;\n if (*s) {\n v6 = s + 1;\n v7 = 0;\n v8 = 0;\n v9 = 10;\n do {\n if (v5 == 32 || v5 == 44) {\n if (v7 > 0) {\n v4[v7] = 0;\n v2[v8++] = strdup(v4);\n v7 = 0;\n if (v8 >= v9) {\n v9 *= 2;\n v2 = realloc(v2, 8LL * v9);\n v7 = 0;\n }\n }\n } else {\n v4[v7++] = v5;\n }\n v5 = *v6++;\n } while (v5);\n if (v7 > 0) {\n v4[v7] = 0;\n v2[v8++] = strdup(v4);\n }\n } else {\n v8 = 0;\n }\n free(v4);\n *a2 = v8;\n return v2;\n}" + }, + { + "index": "HumanEval-C-101", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char** func0(const char* s, int* count) {\n int capacity = 10;\n char** out = malloc(capacity * sizeof(char*));\n char* current = malloc(strlen(s) + 1);\n int word_count = 0;\n int current_length = 0;\n for (int i = 0; s[i]; i++) {\n if (s[i] == ' ' || s[i] == ',') {\n if (current_length > 0) {\n current[current_length] = '\\0';\n out[word_count++] = strdup(current);\n current_length = 0;\n if (word_count >= capacity) {\n capacity *= 2;\n out = realloc(out, capacity * sizeof(char*));\n }\n }\n } else {\n current[current_length++] = s[i];\n }\n }\n if (current_length > 0) {\n current[current_length] = '\\0';\n out[word_count++] = strdup(current);\n }\n free(current);\n *count = word_count;\n return out;\n}", + "test": "#include \n#include \n#include \n#include \n\nbool issame(char** a, int a_count, char** b, int b_count) {\n if (a_count != b_count) return false;\n for (int i = 0; i < a_count; i++) {\n if (strcmp(a[i], b[i]) != 0) return false;\n }\n return true;\n}\n\nvoid free_words(char** words, int count) {\n for (int i = 0; i < count; i++)\n free(words[i]);\n free(words);\n}\n\nint main() {\n int count;\n char** result;\n\n char* expected1[] = {\"Hi\", \"my\", \"name\", \"is\", \"John\"};\n result = func0(\"Hi, my name is John\", &count);\n assert(issame(result, count, expected1, 5));\n free_words(result, count);\n\n char* expected2[] = {\"One\", \"two\", \"three\", \"four\", \"five\", \"six\"};\n result = func0(\"One, two, three, four, five, six\", &count);\n assert(issame(result, count, expected2, 6));\n free_words(result, count);\n\n char* expected3[] = {\"Hi\", \"my\", \"name\"};\n result = func0(\"Hi, my name\", &count);\n assert(issame(result, count, expected3, 3));\n free_words(result, count);\n\n char* expected4[] = {\"One\", \"two\", \"three\", \"four\", \"five\", \"six\"};\n result = func0(\"One,, two, three, four, five, six,\", &count);\n assert(issame(result, count, expected4, 6));\n free_words(result, count);\n\n char* expected5[] = {};\n result = func0(\"\", &count);\n assert(issame(result, count, expected5, 0));\n free_words(result, count);\n\n char* expected6[] = {\"ahmed\", \"gamal\"};\n result = func0(\"ahmed , gamal\", &count);\n assert(issame(result, count, expected6, 2));\n free_words(result, count);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14, rdi\nmov edi, 50h ; 'P'; size\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rsi\ncall _malloc\nmov rdi, r14; s\nmov rbp, rax\ncall _strlen\nlea rdi, [rax+1]; size\ncall _malloc\nmov r12, rax\nmovzx eax, byte ptr [r14]\ntest al, al\njz loc_17A0\nadd r14, 1\nxor ebx, ebx\nxor r15d, r15d\nmov r13d, 0Ah\njmp short loc_16F6\nloc_16E0:\nmovsxd rcx, ebx\nadd ebx, 1\nmov [r12+rcx], al\nloc_16EA:\nmovzx eax, byte ptr [r14]\nadd r14, 1\ntest al, al\njz short loc_1750\nloc_16F6:\ncmp al, 20h ; ' '\njz short loc_16FE\ncmp al, 2Ch ; ','\njnz short loc_16E0\nloc_16FE:\ntest ebx, ebx\njle short loc_16EA\nmovsxd rbx, ebx\nmov rdi, r12; s\nmov byte ptr [r12+rbx], 0\nlea ebx, [r15+1]\ncall _strdup\nmov [rbp+r15*8+0], rax\nmovsxd r15, ebx\nxor ebx, ebx\ncmp r15d, r13d\njl short loc_16EA\nadd r13d, r13d\nmov rdi, rbp; ptr\nadd r14, 1\nmovsxd rsi, r13d\nshl rsi, 3; size\ncall _realloc\nmov rbp, rax\nmovzx eax, byte ptr [r14-1]\ntest al, al\njnz short loc_16F6\nnop word ptr [rax+rax+00000000h]\nloc_1750:\ntest ebx, ebx\njg short loc_1780\nloc_1754:\nmov rdi, r12; ptr\ncall _free\nmov rax, [rsp+48h+var_40]\nmov [rax], r15d\nadd rsp, 18h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1780:\nmovsxd rbx, ebx\nmov rdi, r12; s\nmov byte ptr [r12+rbx], 0\nlea ebx, [r15+1]\ncall _strdup\nmov [rbp+r15*8+0], rax\nmov r15d, ebx\njmp short loc_1754\nloc_17A0:\nxor r15d, r15d\njmp short loc_1754", + "ida_pseudo": "_QWORD *__fastcall func0(char *s, _DWORD *a2)\n{\n _QWORD *v2; // rbp\n size_t v3; // rax\n char *v4; // r12\n char v5; // al\n char *v6; // r14\n int v7; // ebx\n __int64 v8; // r15\n int v9; // r13d\n __int64 v10; // rcx\n\n v2 = malloc(0x50uLL);\n v3 = strlen(s);\n v4 = (char *)malloc(v3 + 1);\n v5 = *s;\n if ( !*s )\n {\n LODWORD(v8) = 0;\n goto LABEL_12;\n }\n v6 = s + 1;\n v7 = 0;\n v8 = 0LL;\n v9 = 10;\n do\n {\n while ( v5 != 32 && v5 != 44 )\n {\n v10 = v7++;\n v4[v10] = v5;\nLABEL_4:\n v5 = *v6++;\n if ( !v5 )\n goto LABEL_10;\n }\n if ( v7 <= 0 )\n goto LABEL_4;\n v4[v7] = 0;\n v2[v8] = strdup(v4);\n v8 = (int)v8 + 1;\n v7 = 0;\n if ( (int)v8 < v9 )\n goto LABEL_4;\n v9 *= 2;\n ++v6;\n v2 = realloc(v2, 8LL * v9);\n v5 = *(v6 - 1);\n }\n while ( v5 );\nLABEL_10:\n if ( v7 > 0 )\n {\n v4[v7] = 0;\n v2[v8] = strdup(v4);\n LODWORD(v8) = v8 + 1;\n }\nLABEL_12:\n free(v4);\n *a2 = v8;\n return v2;\n}", + "ida_strip_asm": "sub_1680:\nendbr64\npush r15\npush r14\nmov r14, rdi\nmov edi, 50h ; 'P'; size\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rsi\ncall _malloc\nmov rdi, r14; s\nmov rbp, rax\ncall _strlen\nlea rdi, [rax+1]; size\ncall _malloc\nmov r12, rax\nmovzx eax, byte ptr [r14]\ntest al, al\njz loc_17A0\nadd r14, 1\nxor ebx, ebx\nxor r15d, r15d\nmov r13d, 0Ah\njmp short loc_16F6\nloc_16E0:\nmovsxd rcx, ebx\nadd ebx, 1\nmov [r12+rcx], al\nloc_16EA:\nmovzx eax, byte ptr [r14]\nadd r14, 1\ntest al, al\njz short loc_1750\nloc_16F6:\ncmp al, 20h ; ' '\njz short loc_16FE\ncmp al, 2Ch ; ','\njnz short loc_16E0\nloc_16FE:\ntest ebx, ebx\njle short loc_16EA\nmovsxd rbx, ebx\nmov rdi, r12; s\nmov byte ptr [r12+rbx], 0\nlea ebx, [r15+1]\ncall _strdup\nmov [rbp+r15*8+0], rax\nmovsxd r15, ebx\nxor ebx, ebx\ncmp r15d, r13d\njl short loc_16EA\nadd r13d, r13d\nmov rdi, rbp; ptr\nadd r14, 1\nmovsxd rsi, r13d\nshl rsi, 3; size\ncall _realloc\nmov rbp, rax\nmovzx eax, byte ptr [r14-1]\ntest al, al\njnz short loc_16F6\nnop word ptr [rax+rax+00000000h]\nloc_1750:\ntest ebx, ebx\njg short loc_1780\nloc_1754:\nmov rdi, r12; ptr\ncall _free\nmov rax, [rsp+48h+var_40]\nmov [rax], r15d\nadd rsp, 18h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1780:\nmovsxd rbx, ebx\nmov rdi, r12; s\nmov byte ptr [r12+rbx], 0\nlea ebx, [r15+1]\ncall _strdup\nmov [rbp+r15*8+0], rax\nmov r15d, ebx\njmp short loc_1754\nloc_17A0:\nxor r15d, r15d\njmp short loc_1754", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1680(char *s, _DWORD *a2)\n{\n _QWORD *v2; // rbp\n size_t v3; // rax\n char *v4; // r12\n char v5; // al\n char *v6; // r14\n int v7; // ebx\n __int64 v8; // r15\n int v9; // r13d\n __int64 v10; // rcx\n\n v2 = malloc(0x50uLL);\n v3 = strlen(s);\n v4 = (char *)malloc(v3 + 1);\n v5 = *s;\n if ( !*s )\n {\n LODWORD(v8) = 0;\n goto LABEL_12;\n }\n v6 = s + 1;\n v7 = 0;\n v8 = 0LL;\n v9 = 10;\n do\n {\n while ( v5 != 32 && v5 != 44 )\n {\n v10 = v7++;\n v4[v10] = v5;\nLABEL_4:\n v5 = *v6++;\n if ( !v5 )\n goto LABEL_10;\n }\n if ( v7 <= 0 )\n goto LABEL_4;\n v4[v7] = 0;\n v2[v8] = strdup(v4);\n v8 = (int)v8 + 1;\n v7 = 0;\n if ( (int)v8 < v9 )\n goto LABEL_4;\n v9 *= 2;\n ++v6;\n v2 = realloc(v2, 8LL * v9);\n v5 = *(v6 - 1);\n }\n while ( v5 );\nLABEL_10:\n if ( v7 > 0 )\n {\n v4[v7] = 0;\n v2[v8] = strdup(v4);\n LODWORD(v8) = v8 + 1;\n }\nLABEL_12:\n free(v4);\n *a2 = v8;\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1680(char *s, uint32_t *a2) {\n uint64_t *v2;\n unsigned int v3;\n char *v4;\n char v5;\n char *v6;\n int v7;\n long long v8;\n int v9;\n long long v10;\n v2 = malloc(80uLL);\n v3 = strlen(s);\n v4 = (char *)malloc(v3 + 1);\n v5 = *s;\n if (!*s) {\n LODWORD(v8) = 0;\n goto LABEL_12;\n }\n v6 = s + 1;\n v7 = 0;\n v8 = 0LL;\n v9 = 10;\n do {\n while (v5 != 32 && v5 != 44) {\n v10 = v7++;\n v4[v10] = v5;\n LABEL_4:\n v5 = *v6++;\n if (!v5) goto LABEL_10;\n }\n if (v7 <= 0) goto LABEL_4;\n v4[v7] = 0;\n v2[v8] = strdup(v4);\n v8 = (int)v8 + 1;\n v7 = 0;\n if ((int)v8 < v9) goto LABEL_4;\n v9 *= 2;\n ++v6;\n v2 = realloc(v2, 8LL * v9);\n v5 = *(v6 - 1);\n } while (v5);\nLABEL_10:\n if (v7 > 0) {\n v4[v7] = 0;\n v2[v8] = strdup(v4);\n LODWORD(v8) = v8 + 1;\n }\nLABEL_12:\n free(v4);\n *a2 = v8;\n return v2;\n}", + "ida_pseudo_norm": "uint64_t *func0(char *s, uint32_t *a2) {\n uint64_t *v2;\n unsigned int v3;\n char *v4;\n char v5;\n char *v6;\n int v7;\n long long v8;\n int v9;\n long long v10;\n v2 = malloc(80uLL);\n v3 = strlen(s);\n v4 = (char *)malloc(v3 + 1);\n v5 = *s;\n if (!*s) {\n LODWORD(v8) = 0;\n goto LABEL_12;\n }\n v6 = s + 1;\n v7 = 0;\n v8 = 0LL;\n v9 = 10;\n do {\n while (v5 != 32 && v5 != 44) {\n v10 = v7++;\n v4[v10] = v5;\n LABEL_4:\n v5 = *v6++;\n if (!v5) goto LABEL_10;\n }\n if (v7 <= 0) goto LABEL_4;\n v4[v7] = 0;\n v2[v8] = strdup(v4);\n v8 = (int)v8 + 1;\n v7 = 0;\n if ((int)v8 < v9) goto LABEL_4;\n v9 *= 2;\n ++v6;\n v2 = realloc(v2, 8LL * v9);\n v5 = *(v6 - 1);\n } while (v5);\nLABEL_10:\n if (v7 > 0) {\n v4[v7] = 0;\n v2[v8] = strdup(v4);\n LODWORD(v8) = v8 + 1;\n }\nLABEL_12:\n free(v4);\n *a2 = v8;\n return v2;\n}" + }, + { + "index": "HumanEval-C-101", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char** func0(const char* s, int* count) {\n int capacity = 10;\n char** out = malloc(capacity * sizeof(char*));\n char* current = malloc(strlen(s) + 1);\n int word_count = 0;\n int current_length = 0;\n for (int i = 0; s[i]; i++) {\n if (s[i] == ' ' || s[i] == ',') {\n if (current_length > 0) {\n current[current_length] = '\\0';\n out[word_count++] = strdup(current);\n current_length = 0;\n if (word_count >= capacity) {\n capacity *= 2;\n out = realloc(out, capacity * sizeof(char*));\n }\n }\n } else {\n current[current_length++] = s[i];\n }\n }\n if (current_length > 0) {\n current[current_length] = '\\0';\n out[word_count++] = strdup(current);\n }\n free(current);\n *count = word_count;\n return out;\n}", + "test": "#include \n#include \n#include \n#include \n\nbool issame(char** a, int a_count, char** b, int b_count) {\n if (a_count != b_count) return false;\n for (int i = 0; i < a_count; i++) {\n if (strcmp(a[i], b[i]) != 0) return false;\n }\n return true;\n}\n\nvoid free_words(char** words, int count) {\n for (int i = 0; i < count; i++)\n free(words[i]);\n free(words);\n}\n\nint main() {\n int count;\n char** result;\n\n char* expected1[] = {\"Hi\", \"my\", \"name\", \"is\", \"John\"};\n result = func0(\"Hi, my name is John\", &count);\n assert(issame(result, count, expected1, 5));\n free_words(result, count);\n\n char* expected2[] = {\"One\", \"two\", \"three\", \"four\", \"five\", \"six\"};\n result = func0(\"One, two, three, four, five, six\", &count);\n assert(issame(result, count, expected2, 6));\n free_words(result, count);\n\n char* expected3[] = {\"Hi\", \"my\", \"name\"};\n result = func0(\"Hi, my name\", &count);\n assert(issame(result, count, expected3, 3));\n free_words(result, count);\n\n char* expected4[] = {\"One\", \"two\", \"three\", \"four\", \"five\", \"six\"};\n result = func0(\"One,, two, three, four, five, six,\", &count);\n assert(issame(result, count, expected4, 6));\n free_words(result, count);\n\n char* expected5[] = {};\n result = func0(\"\", &count);\n assert(issame(result, count, expected5, 0));\n free_words(result, count);\n\n char* expected6[] = {\"ahmed\", \"gamal\"};\n result = func0(\"ahmed , gamal\", &count);\n assert(issame(result, count, expected6, 2));\n free_words(result, count);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14, rdi\nmov edi, 50h ; 'P'; size\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rsi\ncall _malloc\nmov rdi, r14; s\nmov rbp, rax\ncall _strlen\nlea rdi, [rax+1]; size\ncall _malloc\nmov r12, rax\nmovzx eax, byte ptr [r14]\ntest al, al\njz loc_17A0\nadd r14, 1\nxor ebx, ebx\nxor r15d, r15d\nmov r13d, 0Ah\njmp short loc_16F6\nloc_16E0:\nmovsxd rcx, ebx\nadd ebx, 1\nmov [r12+rcx], al\nloc_16EA:\nmovzx eax, byte ptr [r14]\nadd r14, 1\ntest al, al\njz short loc_1750\nloc_16F6:\ncmp al, 20h ; ' '\njz short loc_16FE\ncmp al, 2Ch ; ','\njnz short loc_16E0\nloc_16FE:\ntest ebx, ebx\njle short loc_16EA\nmovsxd rbx, ebx\nmov rdi, r12; s\nmov byte ptr [r12+rbx], 0\nlea ebx, [r15+1]\ncall _strdup\nmov [rbp+r15*8+0], rax\nmovsxd r15, ebx\nxor ebx, ebx\ncmp r15d, r13d\njl short loc_16EA\nadd r13d, r13d\nmov rdi, rbp; ptr\nadd r14, 1\nmovsxd rsi, r13d\nshl rsi, 3; size\ncall _realloc\nmov rbp, rax\nmovzx eax, byte ptr [r14-1]\ntest al, al\njnz short loc_16F6\nnop word ptr [rax+rax+00000000h]\nloc_1750:\ntest ebx, ebx\njg short loc_1780\nloc_1754:\nmov rdi, r12; ptr\ncall _free\nmov rax, [rsp+48h+var_40]\nmov [rax], r15d\nadd rsp, 18h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1780:\nmovsxd rbx, ebx\nmov rdi, r12; s\nmov byte ptr [r12+rbx], 0\nlea ebx, [r15+1]\ncall _strdup\nmov [rbp+r15*8+0], rax\nmov r15d, ebx\njmp short loc_1754\nloc_17A0:\nxor r15d, r15d\njmp short loc_1754", + "ida_pseudo": "_QWORD *__fastcall func0(char *s, _DWORD *a2)\n{\n _QWORD *v2; // rbp\n size_t v3; // rax\n char *v4; // r12\n char v5; // al\n char *v6; // r14\n int v7; // ebx\n __int64 v8; // r15\n int v9; // r13d\n __int64 v10; // rcx\n\n v2 = malloc(0x50uLL);\n v3 = strlen(s);\n v4 = (char *)malloc(v3 + 1);\n v5 = *s;\n if ( !*s )\n {\n LODWORD(v8) = 0;\n goto LABEL_12;\n }\n v6 = s + 1;\n v7 = 0;\n v8 = 0LL;\n v9 = 10;\n do\n {\n while ( v5 != 32 && v5 != 44 )\n {\n v10 = v7++;\n v4[v10] = v5;\nLABEL_4:\n v5 = *v6++;\n if ( !v5 )\n goto LABEL_10;\n }\n if ( v7 <= 0 )\n goto LABEL_4;\n v4[v7] = 0;\n v2[v8] = strdup(v4);\n v8 = (int)v8 + 1;\n v7 = 0;\n if ( (int)v8 < v9 )\n goto LABEL_4;\n v9 *= 2;\n ++v6;\n v2 = realloc(v2, 8LL * v9);\n v5 = *(v6 - 1);\n }\n while ( v5 );\nLABEL_10:\n if ( v7 > 0 )\n {\n v4[v7] = 0;\n v2[v8] = strdup(v4);\n LODWORD(v8) = v8 + 1;\n }\nLABEL_12:\n free(v4);\n *a2 = v8;\n return v2;\n}", + "ida_strip_asm": "sub_1680:\nendbr64\npush r15\npush r14\nmov r14, rdi\nmov edi, 50h ; 'P'; size\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rsi\ncall _malloc\nmov rdi, r14; s\nmov rbp, rax\ncall _strlen\nlea rdi, [rax+1]; size\ncall _malloc\nmov r12, rax\nmovzx eax, byte ptr [r14]\ntest al, al\njz loc_17A0\nadd r14, 1\nxor ebx, ebx\nxor r15d, r15d\nmov r13d, 0Ah\njmp short loc_16F6\nloc_16E0:\nmovsxd rcx, ebx\nadd ebx, 1\nmov [r12+rcx], al\nloc_16EA:\nmovzx eax, byte ptr [r14]\nadd r14, 1\ntest al, al\njz short loc_1750\nloc_16F6:\ncmp al, 20h ; ' '\njz short loc_16FE\ncmp al, 2Ch ; ','\njnz short loc_16E0\nloc_16FE:\ntest ebx, ebx\njle short loc_16EA\nmovsxd rbx, ebx\nmov rdi, r12; s\nmov byte ptr [r12+rbx], 0\nlea ebx, [r15+1]\ncall _strdup\nmov [rbp+r15*8+0], rax\nmovsxd r15, ebx\nxor ebx, ebx\ncmp r15d, r13d\njl short loc_16EA\nadd r13d, r13d\nmov rdi, rbp; ptr\nadd r14, 1\nmovsxd rsi, r13d\nshl rsi, 3; size\ncall _realloc\nmov rbp, rax\nmovzx eax, byte ptr [r14-1]\ntest al, al\njnz short loc_16F6\nnop word ptr [rax+rax+00000000h]\nloc_1750:\ntest ebx, ebx\njg short loc_1780\nloc_1754:\nmov rdi, r12; ptr\ncall _free\nmov rax, [rsp+48h+var_40]\nmov [rax], r15d\nadd rsp, 18h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1780:\nmovsxd rbx, ebx\nmov rdi, r12; s\nmov byte ptr [r12+rbx], 0\nlea ebx, [r15+1]\ncall _strdup\nmov [rbp+r15*8+0], rax\nmov r15d, ebx\njmp short loc_1754\nloc_17A0:\nxor r15d, r15d\njmp short loc_1754", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1680(char *s, _DWORD *a2)\n{\n _QWORD *v2; // rbp\n size_t v3; // rax\n char *v4; // r12\n char v5; // al\n char *v6; // r14\n int v7; // ebx\n __int64 v8; // r15\n int v9; // r13d\n __int64 v10; // rcx\n\n v2 = malloc(0x50uLL);\n v3 = strlen(s);\n v4 = (char *)malloc(v3 + 1);\n v5 = *s;\n if ( !*s )\n {\n LODWORD(v8) = 0;\n goto LABEL_12;\n }\n v6 = s + 1;\n v7 = 0;\n v8 = 0LL;\n v9 = 10;\n do\n {\n while ( v5 != 32 && v5 != 44 )\n {\n v10 = v7++;\n v4[v10] = v5;\nLABEL_4:\n v5 = *v6++;\n if ( !v5 )\n goto LABEL_10;\n }\n if ( v7 <= 0 )\n goto LABEL_4;\n v4[v7] = 0;\n v2[v8] = strdup(v4);\n v8 = (int)v8 + 1;\n v7 = 0;\n if ( (int)v8 < v9 )\n goto LABEL_4;\n v9 *= 2;\n ++v6;\n v2 = realloc(v2, 8LL * v9);\n v5 = *(v6 - 1);\n }\n while ( v5 );\nLABEL_10:\n if ( v7 > 0 )\n {\n v4[v7] = 0;\n v2[v8] = strdup(v4);\n LODWORD(v8) = v8 + 1;\n }\nLABEL_12:\n free(v4);\n *a2 = v8;\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1680(char *s, uint32_t *a2) {\n uint64_t *v2;\n unsigned int v3;\n char *v4;\n char v5;\n char *v6;\n int v7;\n long long v8;\n int v9;\n long long v10;\n v2 = malloc(80uLL);\n v3 = strlen(s);\n v4 = (char *)malloc(v3 + 1);\n v5 = *s;\n if (!*s) {\n LODWORD(v8) = 0;\n goto LABEL_12;\n }\n v6 = s + 1;\n v7 = 0;\n v8 = 0LL;\n v9 = 10;\n do {\n while (v5 != 32 && v5 != 44) {\n v10 = v7++;\n v4[v10] = v5;\n LABEL_4:\n v5 = *v6++;\n if (!v5) goto LABEL_10;\n }\n if (v7 <= 0) goto LABEL_4;\n v4[v7] = 0;\n v2[v8] = strdup(v4);\n v8 = (int)v8 + 1;\n v7 = 0;\n if ((int)v8 < v9) goto LABEL_4;\n v9 *= 2;\n ++v6;\n v2 = realloc(v2, 8LL * v9);\n v5 = *(v6 - 1);\n } while (v5);\nLABEL_10:\n if (v7 > 0) {\n v4[v7] = 0;\n v2[v8] = strdup(v4);\n LODWORD(v8) = v8 + 1;\n }\nLABEL_12:\n free(v4);\n *a2 = v8;\n return v2;\n}", + "ida_pseudo_norm": "uint64_t *func0(char *s, uint32_t *a2) {\n uint64_t *v2;\n unsigned int v3;\n char *v4;\n char v5;\n char *v6;\n int v7;\n long long v8;\n int v9;\n long long v10;\n v2 = malloc(80uLL);\n v3 = strlen(s);\n v4 = (char *)malloc(v3 + 1);\n v5 = *s;\n if (!*s) {\n LODWORD(v8) = 0;\n goto LABEL_12;\n }\n v6 = s + 1;\n v7 = 0;\n v8 = 0LL;\n v9 = 10;\n do {\n while (v5 != 32 && v5 != 44) {\n v10 = v7++;\n v4[v10] = v5;\n LABEL_4:\n v5 = *v6++;\n if (!v5) goto LABEL_10;\n }\n if (v7 <= 0) goto LABEL_4;\n v4[v7] = 0;\n v2[v8] = strdup(v4);\n v8 = (int)v8 + 1;\n v7 = 0;\n if ((int)v8 < v9) goto LABEL_4;\n v9 *= 2;\n ++v6;\n v2 = realloc(v2, 8LL * v9);\n v5 = *(v6 - 1);\n } while (v5);\nLABEL_10:\n if (v7 > 0) {\n v4[v7] = 0;\n v2[v8] = strdup(v4);\n LODWORD(v8) = v8 + 1;\n }\nLABEL_12:\n free(v4);\n *a2 = v8;\n return v2;\n}" + }, + { + "index": "HumanEval-C-102", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int x, int y) {\n if (y < x) return -1;\n if (y == x && y % 2 == 1) return -1;\n if (y % 2 == 1) return y - 1;\n return y;\n}", + "test": "#include \n\nint main() {\n assert(func0(12, 15) == 14);\n assert(func0(13, 12) == -1);\n assert(func0(33, 12354) == 12354);\n assert(func0(5234, 5233) == -1);\n assert(func0(6, 29) == 28);\n assert(func0(27, 10) == -1);\n assert(func0(7, 7) == -1);\n assert(func0(546, 546) == 546);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njge short loc_1166\nmov eax, 0FFFFFFFFh\njmp short loc_11B2\nloc_1166:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njnz short loc_118E\nmov edx, [rbp+var_8]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\ncmp eax, 1\njnz short loc_118E\nmov eax, 0FFFFFFFFh\njmp short loc_11B2\nloc_118E:\nmov edx, [rbp+var_8]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\ncmp eax, 1\njnz short loc_11AF\nmov eax, [rbp+var_8]\nsub eax, 1\njmp short loc_11B2\nloc_11AF:\nmov eax, [rbp+var_8]\nloc_11B2:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, signed int a2)\n{\n if ( a2 < a1 )\n return 0xFFFFFFFFLL;\n if ( a2 == a1 && a2 % 2 == 1 )\n return 0xFFFFFFFFLL;\n if ( a2 % 2 == 1 )\n return (unsigned int)(a2 - 1);\n return (unsigned int)a2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njge short loc_1166\nmov eax, 0FFFFFFFFh\njmp short loc_11B2\nloc_1166:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njnz short loc_118E\nmov edx, [rbp+var_8]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\ncmp eax, 1\njnz short loc_118E\nmov eax, 0FFFFFFFFh\njmp short loc_11B2\nloc_118E:\nmov edx, [rbp+var_8]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\ncmp eax, 1\njnz short loc_11AF\nmov eax, [rbp+var_8]\nsub eax, 1\njmp short loc_11B2\nloc_11AF:\nmov eax, [rbp+var_8]\nloc_11B2:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, signed int a2)\n{\n if ( a2 < a1 )\n return 0xFFFFFFFFLL;\n if ( a2 == a1 && a2 % 2 == 1 )\n return 0xFFFFFFFFLL;\n if ( a2 % 2 == 1 )\n return (unsigned int)(a2 - 1);\n return (unsigned int)a2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, signed int a2) {\n if (a2 < a1) return 4294967295LL;\n if (a2 == a1 && a2 % 2 == 1) return 4294967295LL;\n if (a2 % 2 == 1) return (unsigned int)(a2 - 1);\n return (unsigned int)a2;\n}", + "ida_pseudo_norm": "long long func0(int a1, signed int a2) {\n if (a2 < a1) return 4294967295LL;\n if (a2 == a1 && a2 % 2 == 1) return 4294967295LL;\n if (a2 % 2 == 1) return (unsigned int)(a2 - 1);\n return (unsigned int)a2;\n}" + }, + { + "index": "HumanEval-C-103", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "char* func0(int n, int m) {\n if (n > m) return \"-1\";\n int num = (m + n) / 2;\n char* out = (char*)malloc(33);\n out[0] = '\\0';\n int index = 32;\n out[index--] = '\\0';\n do {\n out[index--] = '0' + num % 2;\n num /= 2;\n } while (num > 0);\n return &out[index + 1];\n}", + "test": "#include \n#include \n\nint main() {\n assert(strcmp(func0(1, 5), \"11\") == 0);\n assert(strcmp(func0(7, 13), \"1010\") == 0);\n assert(strcmp(func0(964, 977), \"1111001010\") == 0);\n assert(strcmp(func0(996, 997), \"1111100100\") == 0);\n assert(strcmp(func0(560, 851), \"1011000001\") == 0);\n assert(strcmp(func0(185, 546), \"101101101\") == 0);\n assert(strcmp(func0(362, 496), \"110101101\") == 0);\n assert(strcmp(func0(350, 902), \"1001110010\") == 0);\n assert(strcmp(func0(197, 233), \"11010111\") == 0);\n assert(strcmp(func0(7, 5), \"-1\") == 0);\n assert(strcmp(func0(5, 1), \"-1\") == 0);\n assert(strcmp(func0(5, 5), \"101\") == 0);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_18]\njle short loc_11AF\nlea rax, a1; \"-1\"\njmp locret_1248\nloc_11AF:\nmov edx, [rbp+var_18]\nmov eax, [rbp+var_14]\nadd eax, edx\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_10], eax\nmov edi, 21h ; '!'; size\ncall _malloc\nmov [rbp+var_8], rax\nmov rax, [rbp+var_8]\nmov byte ptr [rax], 0\nmov [rbp+var_C], 20h ; ' '\nmov eax, [rbp+var_C]\nlea edx, [rax-1]\nmov [rbp+var_C], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov byte ptr [rax], 0\nloc_11F5:\nmov edx, [rbp+var_10]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\nlea ecx, [rax+30h]\nmov eax, [rbp+var_C]\nlea edx, [rax-1]\nmov [rbp+var_C], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, ecx\nmov [rax], dl\nmov eax, [rbp+var_10]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_10], eax\ncmp [rbp+var_10], 0\njg short loc_11F5\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, [rax+1]\nmov rax, [rbp+var_8]\nadd rax, rdx\nlocret_1248:\nleave\nretn", + "ida_pseudo": "const char *__fastcall func0(int a1, int a2)\n{\n int v3; // eax\n int v4; // [rsp+10h] [rbp-10h]\n int v5; // [rsp+14h] [rbp-Ch]\n _BYTE *v6; // [rsp+18h] [rbp-8h]\n\n if ( a1 > a2 )\n return \"-1\";\n v4 = (a2 + a1) / 2;\n v6 = malloc(0x21uLL);\n *v6 = 0;\n v5 = 31;\n v6[32] = 0;\n do\n {\n v3 = v5--;\n v6[v3] = v4 % 2 + 48;\n v4 /= 2;\n }\n while ( v4 > 0 );\n return &v6[v5 + 1];\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_18]\njle short loc_11AF\nlea rax, a1; \"-1\"\njmp locret_1248\nloc_11AF:\nmov edx, [rbp+var_18]\nmov eax, [rbp+var_14]\nadd eax, edx\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_10], eax\nmov edi, 21h ; '!'; size\ncall _malloc\nmov [rbp+var_8], rax\nmov rax, [rbp+var_8]\nmov byte ptr [rax], 0\nmov [rbp+var_C], 20h ; ' '\nmov eax, [rbp+var_C]\nlea edx, [rax-1]\nmov [rbp+var_C], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov byte ptr [rax], 0\nloc_11F5:\nmov edx, [rbp+var_10]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\nlea ecx, [rax+30h]\nmov eax, [rbp+var_C]\nlea edx, [rax-1]\nmov [rbp+var_C], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, ecx\nmov [rax], dl\nmov eax, [rbp+var_10]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_10], eax\ncmp [rbp+var_10], 0\njg short loc_11F5\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, [rax+1]\nmov rax, [rbp+var_8]\nadd rax, rdx\nlocret_1248:\nleave\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1189(int a1, int a2)\n{\n int v3; // eax\n int v4; // [rsp+10h] [rbp-10h]\n int v5; // [rsp+14h] [rbp-Ch]\n _BYTE *v6; // [rsp+18h] [rbp-8h]\n\n if ( a1 > a2 )\n return \"-1\";\n v4 = (a2 + a1) / 2;\n v6 = malloc(0x21uLL);\n *v6 = 0;\n v5 = 31;\n v6[32] = 0;\n do\n {\n v3 = v5--;\n v6[v3] = v4 % 2 + 48;\n v4 /= 2;\n }\n while ( v4 > 0 );\n return &v6[v5 + 1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1189(int a1, int a2) {\n int v3;\n int v4;\n int v5;\n uint8_t *v6;\n if (a1 > a2) return \"-1\";\n v4 = (a2 + a1) / 2;\n v6 = malloc(33uLL);\n *v6 = 0;\n v5 = 31;\n v6[32] = 0;\n do {\n v3 = v5--;\n v6[v3] = v4 % 2 + 48;\n v4 /= 2;\n } while (v4 > 0);\n return &v6[v5 + 1];\n}", + "ida_pseudo_norm": "const char *func0(int a1, int a2) {\n int v3;\n int v4;\n int v5;\n uint8_t *v6;\n if (a1 > a2) return \"-1\";\n v4 = (a2 + a1) / 2;\n v6 = malloc(33uLL);\n *v6 = 0;\n v5 = 31;\n v6[32] = 0;\n do {\n v3 = v5--;\n v6[v3] = v4 % 2 + 48;\n v4 /= 2;\n } while (v4 > 0);\n return &v6[v5 + 1];\n}" + }, + { + "index": "HumanEval-C-103", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "char* func0(int n, int m) {\n if (n > m) return \"-1\";\n int num = (m + n) / 2;\n char* out = (char*)malloc(33);\n out[0] = '\\0';\n int index = 32;\n out[index--] = '\\0';\n do {\n out[index--] = '0' + num % 2;\n num /= 2;\n } while (num > 0);\n return &out[index + 1];\n}", + "test": "#include \n#include \n\nint main() {\n assert(strcmp(func0(1, 5), \"11\") == 0);\n assert(strcmp(func0(7, 13), \"1010\") == 0);\n assert(strcmp(func0(964, 977), \"1111001010\") == 0);\n assert(strcmp(func0(996, 997), \"1111100100\") == 0);\n assert(strcmp(func0(560, 851), \"1011000001\") == 0);\n assert(strcmp(func0(185, 546), \"101101101\") == 0);\n assert(strcmp(func0(362, 496), \"110101101\") == 0);\n assert(strcmp(func0(350, 902), \"1001110010\") == 0);\n assert(strcmp(func0(197, 233), \"11010111\") == 0);\n assert(strcmp(func0(7, 5), \"-1\") == 0);\n assert(strcmp(func0(5, 1), \"-1\") == 0);\n assert(strcmp(func0(5, 5), \"101\") == 0);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nlea r8, a1; \"-1\"\ncmp edi, esi\njle short loc_119C\nmov rax, r8\nretn\nloc_119C:\npush rbx\nadd edi, esi\nmov ebx, edi\nshr ebx, 1Fh\nadd ebx, edi\nsar ebx, 1\nmov edi, 21h ; '!'; size\ncall _malloc\nmov byte ptr [rax], 0\nmov byte ptr [rax+20h], 0\nadd rax, 1Fh\nloc_11BD:\nmov r8, rax\nmov ecx, ebx\nshr ecx, 1Fh\nlea edx, [rbx+rcx]\nand edx, 1\nsub edx, ecx\nadd edx, 30h ; '0'\nmov [rax], dl\nmov ecx, ebx\nmov edx, ebx\nshr edx, 1Fh\nadd edx, ebx\nmov ebx, edx\nsar ebx, 1\nsub rax, 1\ncmp ecx, 1\njg short loc_11BD\nmov rax, r8\npop rbx\nretn", + "ida_pseudo": "const char *__fastcall func0(int a1, int a2)\n{\n int v3; // ebx\n _BYTE *v4; // rax\n _BYTE *v5; // rax\n _BYTE *v6; // r8\n int v7; // ecx\n\n if ( a1 > a2 )\n return \"-1\";\n v3 = (a2 + a1) / 2;\n v4 = malloc(0x21uLL);\n *v4 = 0;\n v4[32] = 0;\n v5 = v4 + 31;\n do\n {\n v6 = v5;\n *v5 = v3 % 2 + 48;\n v7 = v3;\n v3 /= 2;\n --v5;\n }\n while ( v7 > 1 );\n return v6;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\nlea r8, a1; \"-1\"\ncmp edi, esi\njle short loc_119C\nmov rax, r8\nretn\nloc_119C:\npush rbx\nadd edi, esi\nmov ebx, edi\nshr ebx, 1Fh\nadd ebx, edi\nsar ebx, 1\nmov edi, 21h ; '!'; size\ncall _malloc\nmov byte ptr [rax], 0\nmov byte ptr [rax+20h], 0\nadd rax, 1Fh\nloc_11BD:\nmov r8, rax\nmov ecx, ebx\nshr ecx, 1Fh\nlea edx, [rbx+rcx]\nand edx, 1\nsub edx, ecx\nadd edx, 30h ; '0'\nmov [rax], dl\nmov ecx, ebx\nmov edx, ebx\nshr edx, 1Fh\nadd edx, ebx\nmov ebx, edx\nsar ebx, 1\nsub rax, 1\ncmp ecx, 1\njg short loc_11BD\nmov rax, r8\npop rbx\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1189(int a1, int a2)\n{\n int v3; // ebx\n _BYTE *v4; // rax\n _BYTE *v5; // rax\n _BYTE *v6; // r8\n int v7; // ecx\n\n if ( a1 > a2 )\n return \"-1\";\n v3 = (a2 + a1) / 2;\n v4 = malloc(0x21uLL);\n *v4 = 0;\n v4[32] = 0;\n v5 = v4 + 31;\n do\n {\n v6 = v5;\n *v5 = v3 % 2 + 48;\n v7 = v3;\n v3 /= 2;\n --v5;\n }\n while ( v7 > 1 );\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1189(int a1, int a2) {\n int v3;\n uint8_t *v4;\n uint8_t *v5;\n uint8_t *v6;\n int v7;\n if (a1 > a2) return \"-1\";\n v3 = (a2 + a1) / 2;\n v4 = malloc(33uLL);\n *v4 = 0;\n v4[32] = 0;\n v5 = v4 + 31;\n do {\n v6 = v5;\n *v5 = v3 % 2 + 48;\n v7 = v3;\n v3 /= 2;\n --v5;\n } while (v7 > 1);\n return v6;\n}", + "ida_pseudo_norm": "const char *func0(int a1, int a2) {\n int v3;\n uint8_t *v4;\n uint8_t *v5;\n uint8_t *v6;\n int v7;\n if (a1 > a2) return \"-1\";\n v3 = (a2 + a1) / 2;\n v4 = malloc(33uLL);\n *v4 = 0;\n v4[32] = 0;\n v5 = v4 + 31;\n do {\n v6 = v5;\n *v5 = v3 % 2 + 48;\n v7 = v3;\n v3 /= 2;\n --v5;\n } while (v7 > 1);\n return v6;\n}" + }, + { + "index": "HumanEval-C-103", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "char* func0(int n, int m) {\n if (n > m) return \"-1\";\n int num = (m + n) / 2;\n char* out = (char*)malloc(33);\n out[0] = '\\0';\n int index = 32;\n out[index--] = '\\0';\n do {\n out[index--] = '0' + num % 2;\n num /= 2;\n } while (num > 0);\n return &out[index + 1];\n}", + "test": "#include \n#include \n\nint main() {\n assert(strcmp(func0(1, 5), \"11\") == 0);\n assert(strcmp(func0(7, 13), \"1010\") == 0);\n assert(strcmp(func0(964, 977), \"1111001010\") == 0);\n assert(strcmp(func0(996, 997), \"1111100100\") == 0);\n assert(strcmp(func0(560, 851), \"1011000001\") == 0);\n assert(strcmp(func0(185, 546), \"101101101\") == 0);\n assert(strcmp(func0(362, 496), \"110101101\") == 0);\n assert(strcmp(func0(350, 902), \"1001110010\") == 0);\n assert(strcmp(func0(197, 233), \"11010111\") == 0);\n assert(strcmp(func0(7, 5), \"-1\") == 0);\n assert(strcmp(func0(5, 1), \"-1\") == 0);\n assert(strcmp(func0(5, 5), \"101\") == 0);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0_part_0:\nadd edi, esi\npush rbx\nmov ebx, edi\nshr ebx, 1Fh\nadd ebx, edi\nmov edi, 21h ; '!'; size\ncall _malloc\nsar ebx, 1\nmov byte ptr [rax], 0\nadd rax, 1Fh\nmov byte ptr [rax+1], 0\nnop dword ptr [rax+00000000h]\nloc_1478:\nmov ecx, ebx\nmov rsi, rax\nsub rax, 1\nshr ecx, 1Fh\nlea edx, [rbx+rcx]\nand edx, 1\nsub edx, ecx\nadd edx, 30h ; '0'\nmov [rax+1], dl\nmov edx, ebx\nmov ebx, ecx\nadd ebx, edx\nsar ebx, 1\ncmp edx, 1\njg short loc_1478\nmov rax, rsi\npop rbx\nretn", + "ida_pseudo": "_BYTE *__fastcall func0_part_0(int a1, int a2)\n{\n _BYTE *v2; // rax\n int v3; // ebx\n _BYTE *v4; // rax\n _BYTE *v5; // rsi\n int v6; // edx\n\n v2 = malloc(0x21uLL);\n v3 = (a2 + a1) / 2;\n *v2 = 0;\n v4 = v2 + 31;\n v4[1] = 0;\n do\n {\n v5 = v4--;\n v4[1] = v3 % 2 + 48;\n v6 = v3;\n v3 /= 2;\n }\n while ( v6 > 1 );\n return v5;\n}", + "ida_strip_asm": "sub_1450:\nadd edi, esi\npush rbx\nmov ebx, edi\nshr ebx, 1Fh\nadd ebx, edi\nmov edi, 21h ; '!'; size\ncall _malloc\nsar ebx, 1\nmov byte ptr [rax], 0\nadd rax, 1Fh\nmov byte ptr [rax+1], 0\nnop dword ptr [rax+00000000h]\nloc_1478:\nmov ecx, ebx\nmov rsi, rax\nsub rax, 1\nshr ecx, 1Fh\nlea edx, [rbx+rcx]\nand edx, 1\nsub edx, ecx\nadd edx, 30h ; '0'\nmov [rax+1], dl\nmov edx, ebx\nmov ebx, ecx\nadd ebx, edx\nsar ebx, 1\ncmp edx, 1\njg short loc_1478\nmov rax, rsi\npop rbx\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1450(int a1, int a2)\n{\n _BYTE *v2; // rax\n int v3; // ebx\n _BYTE *v4; // rax\n _BYTE *v5; // rsi\n int v6; // edx\n\n v2 = malloc(0x21uLL);\n v3 = (a2 + a1) / 2;\n *v2 = 0;\n v4 = v2 + 31;\n v4[1] = 0;\n do\n {\n v5 = v4--;\n v4[1] = v3 % 2 + 48;\n v6 = v3;\n v3 /= 2;\n }\n while ( v6 > 1 );\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1450(int a1, int a2) {\n uint8_t *v2;\n int v3;\n uint8_t *v4;\n uint8_t *v5;\n int v6;\n v2 = malloc(33uLL);\n v3 = (a2 + a1) / 2;\n *v2 = 0;\n v4 = v2 + 31;\n v4[1] = 0;\n do {\n v5 = v4--;\n v4[1] = v3 % 2 + 48;\n v6 = v3;\n v3 /= 2;\n } while (v6 > 1);\n return v5;\n}", + "ida_pseudo_norm": "uint8_t *func0_part_0(int a1, int a2) {\n uint8_t *v2;\n int v3;\n uint8_t *v4;\n uint8_t *v5;\n int v6;\n v2 = malloc(33uLL);\n v3 = (a2 + a1) / 2;\n *v2 = 0;\n v4 = v2 + 31;\n v4[1] = 0;\n do {\n v5 = v4--;\n v4[1] = v3 % 2 + 48;\n v6 = v3;\n v3 /= 2;\n } while (v6 > 1);\n return v5;\n}" + }, + { + "index": "HumanEval-C-103", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "char* func0(int n, int m) {\n if (n > m) return \"-1\";\n int num = (m + n) / 2;\n char* out = (char*)malloc(33);\n out[0] = '\\0';\n int index = 32;\n out[index--] = '\\0';\n do {\n out[index--] = '0' + num % 2;\n num /= 2;\n } while (num > 0);\n return &out[index + 1];\n}", + "test": "#include \n#include \n\nint main() {\n assert(strcmp(func0(1, 5), \"11\") == 0);\n assert(strcmp(func0(7, 13), \"1010\") == 0);\n assert(strcmp(func0(964, 977), \"1111001010\") == 0);\n assert(strcmp(func0(996, 997), \"1111100100\") == 0);\n assert(strcmp(func0(560, 851), \"1011000001\") == 0);\n assert(strcmp(func0(185, 546), \"101101101\") == 0);\n assert(strcmp(func0(362, 496), \"110101101\") == 0);\n assert(strcmp(func0(350, 902), \"1001110010\") == 0);\n assert(strcmp(func0(197, 233), \"11010111\") == 0);\n assert(strcmp(func0(7, 5), \"-1\") == 0);\n assert(strcmp(func0(5, 1), \"-1\") == 0);\n assert(strcmp(func0(5, 5), \"101\") == 0);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0_part_0:\nadd edi, esi\npush rbx\nmov ebx, edi\nshr ebx, 1Fh\nadd ebx, edi\nmov edi, 21h ; '!'; size\ncall _malloc\nsar ebx, 1\nmov byte ptr [rax], 0\nadd rax, 1Fh\nmov byte ptr [rax+1], 0\nnop dword ptr [rax+00000000h]\nloc_1478:\nmov ecx, ebx\nmov rsi, rax\nsub rax, 1\nshr ecx, 1Fh\nlea edx, [rbx+rcx]\nand edx, 1\nsub edx, ecx\nadd edx, 30h ; '0'\nmov [rax+1], dl\nmov edx, ebx\nmov ebx, ecx\nadd ebx, edx\nsar ebx, 1\ncmp edx, 1\njg short loc_1478\nmov rax, rsi\npop rbx\nretn", + "ida_pseudo": "_BYTE *__fastcall func0_part_0(int a1, int a2)\n{\n _BYTE *v2; // rax\n int v3; // ebx\n _BYTE *v4; // rax\n _BYTE *v5; // rsi\n int v6; // edx\n\n v2 = malloc(0x21uLL);\n v3 = (a2 + a1) / 2;\n *v2 = 0;\n v4 = v2 + 31;\n v4[1] = 0;\n do\n {\n v5 = v4--;\n v4[1] = v3 % 2 + 48;\n v6 = v3;\n v3 /= 2;\n }\n while ( v6 > 1 );\n return v5;\n}", + "ida_strip_asm": "sub_1450:\nadd edi, esi\npush rbx\nmov ebx, edi\nshr ebx, 1Fh\nadd ebx, edi\nmov edi, 21h ; '!'; size\ncall _malloc\nsar ebx, 1\nmov byte ptr [rax], 0\nadd rax, 1Fh\nmov byte ptr [rax+1], 0\nnop dword ptr [rax+00000000h]\nloc_1478:\nmov ecx, ebx\nmov rsi, rax\nsub rax, 1\nshr ecx, 1Fh\nlea edx, [rbx+rcx]\nand edx, 1\nsub edx, ecx\nadd edx, 30h ; '0'\nmov [rax+1], dl\nmov edx, ebx\nmov ebx, ecx\nadd ebx, edx\nsar ebx, 1\ncmp edx, 1\njg short loc_1478\nmov rax, rsi\npop rbx\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1450(int a1, int a2)\n{\n _BYTE *v2; // rax\n int v3; // ebx\n _BYTE *v4; // rax\n _BYTE *v5; // rsi\n int v6; // edx\n\n v2 = malloc(0x21uLL);\n v3 = (a2 + a1) / 2;\n *v2 = 0;\n v4 = v2 + 31;\n v4[1] = 0;\n do\n {\n v5 = v4--;\n v4[1] = v3 % 2 + 48;\n v6 = v3;\n v3 /= 2;\n }\n while ( v6 > 1 );\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1450(int a1, int a2) {\n uint8_t *v2;\n int v3;\n uint8_t *v4;\n uint8_t *v5;\n int v6;\n v2 = malloc(33uLL);\n v3 = (a2 + a1) / 2;\n *v2 = 0;\n v4 = v2 + 31;\n v4[1] = 0;\n do {\n v5 = v4--;\n v4[1] = v3 % 2 + 48;\n v6 = v3;\n v3 /= 2;\n } while (v6 > 1);\n return v5;\n}", + "ida_pseudo_norm": "uint8_t *func0_part_0(int a1, int a2) {\n uint8_t *v2;\n int v3;\n uint8_t *v4;\n uint8_t *v5;\n int v6;\n v2 = malloc(33uLL);\n v3 = (a2 + a1) / 2;\n *v2 = 0;\n v4 = v2 + 31;\n v4[1] = 0;\n do {\n v5 = v4--;\n v4[1] = v3 % 2 + 48;\n v6 = v3;\n v3 /= 2;\n } while (v6 > 1);\n return v5;\n}" + }, + { + "index": "HumanEval-C-104", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "void func0(int *x, int size, int **out, int *out_size) {\n *out = malloc(size * sizeof(int));\n *out_size = 0;\n for (int i = 0; i < size; i++) {\n int num = x[i];\n bool has_even_digit = false;\n if (num == 0) has_even_digit = true;\n while (num > 0 && !has_even_digit) {\n if (num % 2 == 0) has_even_digit = true;\n num = num / 10;\n }\n if (!has_even_digit) {\n (*out)[*out_size] = x[i];\n (*out_size)++;\n }\n }\n for (int i = 0; i < *out_size - 1; i++) {\n for (int j = 0; j < *out_size - i - 1; j++) {\n if ((*out)[j] > (*out)[j + 1]) {\n int temp = (*out)[j];\n (*out)[j] = (*out)[j + 1];\n (*out)[j + 1] = temp;\n }\n }\n }\n}", + "test": "#include \n#include \n#include \n#include \n\nbool issame(int *a, int a_size, int *b, int b_size) {\n if (a_size != b_size) return false;\n for (int i = 0; i < a_size; i++) {\n if (a[i] != b[i]) return false;\n }\n return true;\n}\n\nint main() {\n // Test cases\n int test1[] = {15, 33, 1422, 1};\n int expected1[] = {1, 15, 33};\n int *out1;\n int out1_size;\n func0(test1, 4, &out1, &out1_size);\n assert(issame(out1, out1_size, expected1, 3));\n free(out1);\n\n int test2[] = {152, 323, 1422, 10};\n int *out2;\n int out2_size;\n func0(test2, 4, &out2, &out2_size);\n assert(issame(out2, out2_size, NULL, 0));\n free(out2);\n\n int test3[] = {12345, 2033, 111, 151};\n int expected3[] = {111, 151};\n int *out3;\n int out3_size;\n func0(test3, 4, &out3, &out3_size);\n assert(issame(out3, out3_size, expected3, 2));\n free(out3);\n\n int test4[] = {135, 103, 31};\n int expected4[] = {31, 135};\n int *out4;\n int out4_size;\n func0(test4, 3, &out4, &out4_size);\n assert(issame(out4, out4_size, expected4, 2));\n free(out4);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmov [rbp+var_40], rcx\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov rdx, rax\nmov rax, [rbp+var_38]\nmov [rax], rdx\nmov rax, [rbp+var_40]\nmov dword ptr [rax], 0\nmov [rbp+var_14], 0\njmp loc_12A8\nloc_11F5:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_10], eax\nmov [rbp+var_15], 0\ncmp [rbp+var_10], 0\njnz short loc_124A\nmov [rbp+var_15], 1\njmp short loc_124A\nloc_121E:\nmov eax, [rbp+var_10]\nand eax, 1\ntest eax, eax\njnz short loc_122C\nmov [rbp+var_15], 1\nloc_122C:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_10], eax\nloc_124A:\ncmp [rbp+var_10], 0\njle short loc_125B\nmovzx eax, [rbp+var_15]\nxor eax, 1\ntest al, al\njnz short loc_121E\nloc_125B:\nmovzx eax, [rbp+var_15]\nxor eax, 1\ntest al, al\njz short loc_12A4\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov rax, [rbp+var_38]\nmov rdx, [rax]\nmov rax, [rbp+var_40]\nmov eax, [rax]\ncdqe\nshl rax, 2\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nmov rax, [rbp+var_40]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_40]\nmov [rax], edx\nloc_12A4:\nadd [rbp+var_14], 1\nloc_12A8:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl loc_11F5\nmov [rbp+var_C], 0\njmp loc_1384\nloc_12C0:\nmov [rbp+var_8], 0\njmp loc_136B\nloc_12CC:\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov ecx, [rbp+var_8]\nmovsxd rcx, ecx\nadd rcx, 1\nshl rcx, 2\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_1367\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nadd rdx, 1\nshl rdx, 2\nlea rcx, [rax+rdx]\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nshl rdx, 2\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nadd rdx, 1\nshl rdx, 2\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nloc_1367:\nadd [rbp+var_8], 1\nloc_136B:\nmov rax, [rbp+var_40]\nmov eax, [rax]\nsub eax, [rbp+var_C]\nsub eax, 1\ncmp [rbp+var_8], eax\njl loc_12CC\nadd [rbp+var_C], 1\nloc_1384:\nmov rax, [rbp+var_40]\nmov eax, [rax]\nsub eax, 1\ncmp [rbp+var_C], eax\njl loc_12C0\nnop\nnop\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, void **a3, _DWORD *a4)\n{\n __int64 result; // rax\n bool v7; // [rsp+2Bh] [rbp-15h]\n int i; // [rsp+2Ch] [rbp-14h]\n int v9; // [rsp+30h] [rbp-10h]\n int j; // [rsp+34h] [rbp-Ch]\n int k; // [rsp+38h] [rbp-8h]\n int v12; // [rsp+3Ch] [rbp-4h]\n\n *a3 = malloc(4LL * a2);\n *a4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v9 = *(_DWORD *)(4LL * i + a1);\n v7 = v9 == 0;\n while ( v9 > 0 && !v7 )\n {\n if ( (v9 & 1) == 0 )\n v7 = 1;\n v9 /= 10;\n }\n if ( !v7 )\n *((_DWORD *)*a3 + (int)(*a4)++) = *(_DWORD *)(4LL * i + a1);\n }\n for ( j = 0; ; ++j )\n {\n result = (unsigned int)(*a4 - 1);\n if ( j >= (int)result )\n break;\n for ( k = 0; k < *a4 - j - 1; ++k )\n {\n if ( *((_DWORD *)*a3 + k) > *((_DWORD *)*a3 + k + 1) )\n {\n v12 = *((_DWORD *)*a3 + k);\n *((_DWORD *)*a3 + k) = *((_DWORD *)*a3 + k + 1);\n *((_DWORD *)*a3 + k + 1) = v12;\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmov [rbp+var_40], rcx\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov rdx, rax\nmov rax, [rbp+var_38]\nmov [rax], rdx\nmov rax, [rbp+var_40]\nmov dword ptr [rax], 0\nmov [rbp+var_14], 0\njmp loc_12A8\nloc_11F5:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_10], eax\nmov [rbp+var_15], 0\ncmp [rbp+var_10], 0\njnz short loc_124A\nmov [rbp+var_15], 1\njmp short loc_124A\nloc_121E:\nmov eax, [rbp+var_10]\nand eax, 1\ntest eax, eax\njnz short loc_122C\nmov [rbp+var_15], 1\nloc_122C:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_10], eax\nloc_124A:\ncmp [rbp+var_10], 0\njle short loc_125B\nmovzx eax, [rbp+var_15]\nxor eax, 1\ntest al, al\njnz short loc_121E\nloc_125B:\nmovzx eax, [rbp+var_15]\nxor eax, 1\ntest al, al\njz short loc_12A4\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov rax, [rbp+var_38]\nmov rdx, [rax]\nmov rax, [rbp+var_40]\nmov eax, [rax]\ncdqe\nshl rax, 2\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nmov rax, [rbp+var_40]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_40]\nmov [rax], edx\nloc_12A4:\nadd [rbp+var_14], 1\nloc_12A8:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl loc_11F5\nmov [rbp+var_C], 0\njmp loc_1384\nloc_12C0:\nmov [rbp+var_8], 0\njmp loc_136B\nloc_12CC:\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov ecx, [rbp+var_8]\nmovsxd rcx, ecx\nadd rcx, 1\nshl rcx, 2\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_1367\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nadd rdx, 1\nshl rdx, 2\nlea rcx, [rax+rdx]\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nshl rdx, 2\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nadd rdx, 1\nshl rdx, 2\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nloc_1367:\nadd [rbp+var_8], 1\nloc_136B:\nmov rax, [rbp+var_40]\nmov eax, [rax]\nsub eax, [rbp+var_C]\nsub eax, 1\ncmp [rbp+var_8], eax\njl loc_12CC\nadd [rbp+var_C], 1\nloc_1384:\nmov rax, [rbp+var_40]\nmov eax, [rax]\nsub eax, 1\ncmp [rbp+var_C], eax\njl loc_12C0\nnop\nnop\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(__int64 a1, int a2, void **a3, _DWORD *a4)\n{\n __int64 result; // rax\n bool v7; // [rsp+2Bh] [rbp-15h]\n int i; // [rsp+2Ch] [rbp-14h]\n int v9; // [rsp+30h] [rbp-10h]\n int j; // [rsp+34h] [rbp-Ch]\n int k; // [rsp+38h] [rbp-8h]\n int v12; // [rsp+3Ch] [rbp-4h]\n\n *a3 = malloc(4LL * a2);\n *a4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v9 = *(_DWORD *)(4LL * i + a1);\n v7 = v9 == 0;\n while ( v9 > 0 && !v7 )\n {\n if ( (v9 & 1) == 0 )\n v7 = 1;\n v9 /= 10;\n }\n if ( !v7 )\n *((_DWORD *)*a3 + (int)(*a4)++) = *(_DWORD *)(4LL * i + a1);\n }\n for ( j = 0; ; ++j )\n {\n result = (unsigned int)(*a4 - 1);\n if ( j >= (int)result )\n break;\n for ( k = 0; k < *a4 - j - 1; ++k )\n {\n if ( *((_DWORD *)*a3 + k) > *((_DWORD *)*a3 + k + 1) )\n {\n v12 = *((_DWORD *)*a3 + k);\n *((_DWORD *)*a3 + k) = *((_DWORD *)*a3 + k + 1);\n *((_DWORD *)*a3 + k + 1) = v12;\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(long long a1, int a2, void **a3, uint32_t *a4) {\n long long result;\n bool v7;\n int i;\n int v9;\n int j;\n int k;\n int v12;\n *a3 = malloc(4LL * a2);\n *a4 = 0;\n for (i = 0; i < a2; ++i) {\n v9 = *(uint32_t *)(4LL * i + a1);\n v7 = v9 == 0;\n while (v9 > 0 && !v7) {\n if ((v9 & 1) == 0) v7 = 1;\n v9 /= 10;\n }\n if (!v7) *((uint32_t *)*a3 + (int)(*a4)++) = *(uint32_t *)(4LL * i + a1);\n }\n for (j = 0;; ++j) {\n result = (unsigned int)(*a4 - 1);\n if (j >= (int)result) break;\n for (k = 0; k < *a4 - j - 1; ++k) {\n if (*((uint32_t *)*a3 + k) > *((uint32_t *)*a3 + k + 1)) {\n v12 = *((uint32_t *)*a3 + k);\n *((uint32_t *)*a3 + k) = *((uint32_t *)*a3 + k + 1);\n *((uint32_t *)*a3 + k + 1) = v12;\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, void **a3, uint32_t *a4) {\n long long result;\n bool v7;\n int i;\n int v9;\n int j;\n int k;\n int v12;\n *a3 = malloc(4LL * a2);\n *a4 = 0;\n for (i = 0; i < a2; ++i) {\n v9 = *(uint32_t *)(4LL * i + a1);\n v7 = v9 == 0;\n while (v9 > 0 && !v7) {\n if ((v9 & 1) == 0) v7 = 1;\n v9 /= 10;\n }\n if (!v7) *((uint32_t *)*a3 + (int)(*a4)++) = *(uint32_t *)(4LL * i + a1);\n }\n for (j = 0;; ++j) {\n result = (unsigned int)(*a4 - 1);\n if (j >= (int)result) break;\n for (k = 0; k < *a4 - j - 1; ++k) {\n if (*((uint32_t *)*a3 + k) > *((uint32_t *)*a3 + k + 1)) {\n v12 = *((uint32_t *)*a3 + k);\n *((uint32_t *)*a3 + k) = *((uint32_t *)*a3 + k + 1);\n *((uint32_t *)*a3 + k + 1) = v12;\n }\n }\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-104", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "void func0(int *x, int size, int **out, int *out_size) {\n *out = malloc(size * sizeof(int));\n *out_size = 0;\n for (int i = 0; i < size; i++) {\n int num = x[i];\n bool has_even_digit = false;\n if (num == 0) has_even_digit = true;\n while (num > 0 && !has_even_digit) {\n if (num % 2 == 0) has_even_digit = true;\n num = num / 10;\n }\n if (!has_even_digit) {\n (*out)[*out_size] = x[i];\n (*out_size)++;\n }\n }\n for (int i = 0; i < *out_size - 1; i++) {\n for (int j = 0; j < *out_size - i - 1; j++) {\n if ((*out)[j] > (*out)[j + 1]) {\n int temp = (*out)[j];\n (*out)[j] = (*out)[j + 1];\n (*out)[j + 1] = temp;\n }\n }\n }\n}", + "test": "#include \n#include \n#include \n#include \n\nbool issame(int *a, int a_size, int *b, int b_size) {\n if (a_size != b_size) return false;\n for (int i = 0; i < a_size; i++) {\n if (a[i] != b[i]) return false;\n }\n return true;\n}\n\nint main() {\n // Test cases\n int test1[] = {15, 33, 1422, 1};\n int expected1[] = {1, 15, 33};\n int *out1;\n int out1_size;\n func0(test1, 4, &out1, &out1_size);\n assert(issame(out1, out1_size, expected1, 3));\n free(out1);\n\n int test2[] = {152, 323, 1422, 10};\n int *out2;\n int out2_size;\n func0(test2, 4, &out2, &out2_size);\n assert(issame(out2, out2_size, NULL, 0));\n free(out2);\n\n int test3[] = {12345, 2033, 111, 151};\n int expected3[] = {111, 151};\n int *out3;\n int out3_size;\n func0(test3, 4, &out3, &out3_size);\n assert(issame(out3, out3_size, expected3, 2));\n free(out3);\n\n int test4[] = {135, 103, 31};\n int expected4[] = {31, 135};\n int *out4;\n int out4_size;\n func0(test4, 3, &out4, &out4_size);\n assert(issame(out4, out4_size, expected4, 2));\n free(out4);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r12, rdi\nmov r13d, esi\nmov rbx, rdx\nmov rbp, rcx\nmovsxd r14, esi\nshl r14, 2\nmov rdi, r14; size\ncall _malloc\nmov [rbx], rax\nmov dword ptr [rbp+0], 0\ntest r13d, r13d\njle loc_1293\nmov rsi, r12\nlea r8, [r12+r14]\njmp short loc_1216\nloc_11EC:\nmovsxd rax, edx\nimul rax, 66666667h\nsar rax, 22h\nmov ecx, edx\nsar ecx, 1Fh\nsub eax, ecx\ncmp edx, 9\njle short loc_1222\nmov edx, eax\nloc_1208:\ntest dl, 1\njnz short loc_11EC\nloc_120D:\nadd rsi, 4\ncmp rsi, r8\njz short loc_1232\nloc_1216:\nmov edi, [rsi]\ntest edi, edi\njle short loc_1220\nmov edx, edi\njmp short loc_1208\nloc_1220:\njz short loc_120D\nloc_1222:\nmovsxd rdx, dword ptr [rbp+0]\nmov rax, [rbx]\nmov [rax+rdx*4], edi\nadd dword ptr [rbp+0], 1\njmp short loc_120D\nloc_1232:\ncmp dword ptr [rbp+0], 1\njle short loc_1293\nmov r8d, 0\njmp short loc_127C\nloc_1240:\nadd ecx, 1\nmov edx, r8d\nnot edx\nadd edx, [rbp+0]\ncmp edx, ecx\njle short loc_126D\nloc_124F:\nmov rdx, [rbx]\nlea rdi, [rdx+rax]\nmov esi, [rdi]\nadd rax, 4\nmov edx, [rdx+rax]\ncmp esi, edx\njle short loc_1240\nmov [rdi], edx\nmov rdx, [rbx]\nmov [rdx+rax], esi\njmp short loc_1240\nloc_126D:\nadd r8d, 1\nmov eax, [rbp+0]\nsub eax, 1\ncmp eax, r8d\njle short loc_1293\nloc_127C:\nmov edx, [rbp+0]\nsub edx, r8d\nmov eax, 0\nmov ecx, 0\ncmp edx, 1\njg short loc_124F\njmp short loc_126D\nloc_1293:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "unsigned __int64 __fastcall func0(int *a1, int a2, void **a3, int *a4)\n{\n size_t v7; // r14\n unsigned __int64 result; // rax\n int *v9; // rsi\n int i; // edx\n int v11; // edi\n int v12; // r8d\n int v13; // ecx\n int *v14; // rdi\n int v15; // esi\n __int64 v16; // rax\n int v17; // edx\n\n v7 = a2;\n result = (unsigned __int64)malloc(v7 * 4);\n *a3 = (void *)result;\n *a4 = 0;\n if ( a2 > 0 )\n {\n v9 = a1;\n do\n {\n v11 = *v9;\n if ( *v9 <= 0 )\n {\n if ( v11 )\n {\nLABEL_10:\n result = (unsigned __int64)*a3;\n *((_DWORD *)*a3 + (*a4)++) = v11;\n }\n }\n else\n {\n for ( i = *v9; (i & 1) != 0; i /= 10 )\n {\n result = (unsigned int)(i / 10);\n if ( i <= 9 )\n goto LABEL_10;\n }\n }\n ++v9;\n }\n while ( v9 != &a1[v7] );\n if ( *a4 > 1 )\n {\n v12 = 0;\n do\n {\n v16 = 0LL;\n v13 = 0;\n if ( *a4 - v12 > 1 )\n {\n do\n {\n v14 = (int *)((char *)*a3 + v16);\n v15 = *v14;\n v16 += 4LL;\n v17 = *(_DWORD *)((char *)*a3 + v16);\n if ( *v14 > v17 )\n {\n *v14 = v17;\n *(_DWORD *)((char *)*a3 + v16) = v15;\n }\n ++v13;\n }\n while ( *a4 + ~v12 > v13 );\n }\n ++v12;\n result = (unsigned int)(*a4 - 1);\n }\n while ( (int)result > v12 );\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r12, rdi\nmov r13d, esi\nmov rbx, rdx\nmov rbp, rcx\nmovsxd r14, esi\nshl r14, 2\nmov rdi, r14; size\ncall _malloc\nmov [rbx], rax\nmov dword ptr [rbp+0], 0\ntest r13d, r13d\njle loc_1293\nmov rsi, r12\nlea r8, [r12+r14]\njmp short loc_1216\nloc_11EC:\nmovsxd rax, edx\nimul rax, 66666667h\nsar rax, 22h\nmov ecx, edx\nsar ecx, 1Fh\nsub eax, ecx\ncmp edx, 9\njle short loc_1222\nmov edx, eax\nloc_1208:\ntest dl, 1\njnz short loc_11EC\nloc_120D:\nadd rsi, 4\ncmp rsi, r8\njz short loc_1232\nloc_1216:\nmov edi, [rsi]\ntest edi, edi\njle short loc_1220\nmov edx, edi\njmp short loc_1208\nloc_1220:\njz short loc_120D\nloc_1222:\nmovsxd rdx, dword ptr [rbp+0]\nmov rax, [rbx]\nmov [rax+rdx*4], edi\nadd dword ptr [rbp+0], 1\njmp short loc_120D\nloc_1232:\ncmp dword ptr [rbp+0], 1\njle short loc_1293\nmov r8d, 0\njmp short loc_127C\nloc_1240:\nadd ecx, 1\nmov edx, r8d\nnot edx\nadd edx, [rbp+0]\ncmp edx, ecx\njle short loc_126D\nloc_124F:\nmov rdx, [rbx]\nlea rdi, [rdx+rax]\nmov esi, [rdi]\nadd rax, 4\nmov edx, [rdx+rax]\ncmp esi, edx\njle short loc_1240\nmov [rdi], edx\nmov rdx, [rbx]\nmov [rdx+rax], esi\njmp short loc_1240\nloc_126D:\nadd r8d, 1\nmov eax, [rbp+0]\nsub eax, 1\ncmp eax, r8d\njle short loc_1293\nloc_127C:\nmov edx, [rbp+0]\nsub edx, r8d\nmov eax, 0\nmov ecx, 0\ncmp edx, 1\njg short loc_124F\njmp short loc_126D\nloc_1293:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_11A9(int *a1, int a2, void **a3, int *a4)\n{\n size_t v7; // r14\n unsigned __int64 result; // rax\n int *v9; // rsi\n int i; // edx\n int v11; // edi\n int v12; // r8d\n int v13; // ecx\n int *v14; // rdi\n int v15; // esi\n __int64 v16; // rax\n int v17; // edx\n\n v7 = a2;\n result = (unsigned __int64)malloc(v7 * 4);\n *a3 = (void *)result;\n *a4 = 0;\n if ( a2 > 0 )\n {\n v9 = a1;\n do\n {\n v11 = *v9;\n if ( *v9 <= 0 )\n {\n if ( v11 )\n {\nLABEL_10:\n result = (unsigned __int64)*a3;\n *((_DWORD *)*a3 + (*a4)++) = v11;\n }\n }\n else\n {\n for ( i = *v9; (i & 1) != 0; i /= 10 )\n {\n result = (unsigned int)(i / 10);\n if ( i <= 9 )\n goto LABEL_10;\n }\n }\n ++v9;\n }\n while ( v9 != &a1[v7] );\n if ( *a4 > 1 )\n {\n v12 = 0;\n do\n {\n v16 = 0LL;\n v13 = 0;\n if ( *a4 - v12 > 1 )\n {\n do\n {\n v14 = (int *)((char *)*a3 + v16);\n v15 = *v14;\n v16 += 4LL;\n v17 = *(_DWORD *)((char *)*a3 + v16);\n if ( *v14 > v17 )\n {\n *v14 = v17;\n *(_DWORD *)((char *)*a3 + v16) = v15;\n }\n ++v13;\n }\n while ( *a4 + ~v12 > v13 );\n }\n ++v12;\n result = (unsigned int)(*a4 - 1);\n }\n while ( (int)result > v12 );\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_11A9(int *a1, int a2, void **a3, int *a4) {\n unsigned int v7;\n unsigned long long result;\n int *v9;\n int i;\n int v11;\n int v12;\n int v13;\n int *v14;\n int v15;\n long long v16;\n int v17;\n v7 = a2;\n result = (unsigned long long)malloc(v7 * 4);\n *a3 = (void *)result;\n *a4 = 0;\n if (a2 > 0) {\n v9 = a1;\n do {\n v11 = *v9;\n if (*v9 <= 0) {\n if (v11) {\n LABEL_10:\n result = (unsigned long long)*a3;\n *((uint32_t *)*a3 + (*a4)++) = v11;\n }\n } else {\n for (i = *v9; (i & 1) != 0; i /= 10) {\n result = (unsigned int)(i / 10);\n if (i <= 9) goto LABEL_10;\n }\n }\n ++v9;\n } while (v9 != &a1[v7]);\n if (*a4 > 1) {\n v12 = 0;\n do {\n v16 = 0LL;\n v13 = 0;\n if (*a4 - v12 > 1) {\n do {\n v14 = (int *)((char *)*a3 + v16);\n v15 = *v14;\n v16 += 4LL;\n v17 = *(uint32_t *)((char *)*a3 + v16);\n if (*v14 > v17) {\n *v14 = v17;\n *(uint32_t *)((char *)*a3 + v16) = v15;\n }\n ++v13;\n } while (*a4 + ~v12 > v13);\n }\n ++v12;\n result = (unsigned int)(*a4 - 1);\n } while ((int)result > v12);\n }\n }\n return result;\n}", + "ida_pseudo_norm": "unsigned long long func0(int *a1, int a2, void **a3, int *a4) {\n unsigned int v7;\n unsigned long long result;\n int *v9;\n int i;\n int v11;\n int v12;\n int v13;\n int *v14;\n int v15;\n long long v16;\n int v17;\n v7 = a2;\n result = (unsigned long long)malloc(v7 * 4);\n *a3 = (void *)result;\n *a4 = 0;\n if (a2 > 0) {\n v9 = a1;\n do {\n v11 = *v9;\n if (*v9 <= 0) {\n if (v11) {\n LABEL_10:\n result = (unsigned long long)*a3;\n *((uint32_t *)*a3 + (*a4)++) = v11;\n }\n } else {\n for (i = *v9; (i & 1) != 0; i /= 10) {\n result = (unsigned int)(i / 10);\n if (i <= 9) goto LABEL_10;\n }\n }\n ++v9;\n } while (v9 != &a1[v7]);\n if (*a4 > 1) {\n v12 = 0;\n do {\n v16 = 0LL;\n v13 = 0;\n if (*a4 - v12 > 1) {\n do {\n v14 = (int *)((char *)*a3 + v16);\n v15 = *v14;\n v16 += 4LL;\n v17 = *(uint32_t *)((char *)*a3 + v16);\n if (*v14 > v17) {\n *v14 = v17;\n *(uint32_t *)((char *)*a3 + v16) = v15;\n }\n ++v13;\n } while (*a4 + ~v12 > v13);\n }\n ++v12;\n result = (unsigned int)(*a4 - 1);\n } while ((int)result > v12);\n }\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-104", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "void func0(int *x, int size, int **out, int *out_size) {\n *out = malloc(size * sizeof(int));\n *out_size = 0;\n for (int i = 0; i < size; i++) {\n int num = x[i];\n bool has_even_digit = false;\n if (num == 0) has_even_digit = true;\n while (num > 0 && !has_even_digit) {\n if (num % 2 == 0) has_even_digit = true;\n num = num / 10;\n }\n if (!has_even_digit) {\n (*out)[*out_size] = x[i];\n (*out_size)++;\n }\n }\n for (int i = 0; i < *out_size - 1; i++) {\n for (int j = 0; j < *out_size - i - 1; j++) {\n if ((*out)[j] > (*out)[j + 1]) {\n int temp = (*out)[j];\n (*out)[j] = (*out)[j + 1];\n (*out)[j + 1] = temp;\n }\n }\n }\n}", + "test": "#include \n#include \n#include \n#include \n\nbool issame(int *a, int a_size, int *b, int b_size) {\n if (a_size != b_size) return false;\n for (int i = 0; i < a_size; i++) {\n if (a[i] != b[i]) return false;\n }\n return true;\n}\n\nint main() {\n // Test cases\n int test1[] = {15, 33, 1422, 1};\n int expected1[] = {1, 15, 33};\n int *out1;\n int out1_size;\n func0(test1, 4, &out1, &out1_size);\n assert(issame(out1, out1_size, expected1, 3));\n free(out1);\n\n int test2[] = {152, 323, 1422, 10};\n int *out2;\n int out2_size;\n func0(test2, 4, &out2, &out2_size);\n assert(issame(out2, out2_size, NULL, 0));\n free(out2);\n\n int test3[] = {12345, 2033, 111, 151};\n int expected3[] = {111, 151};\n int *out3;\n int out3_size;\n func0(test3, 4, &out3, &out3_size);\n assert(issame(out3, out3_size, expected3, 2));\n free(out3);\n\n int test4[] = {135, 103, 31};\n int expected4[] = {31, 135};\n int *out4;\n int out4_size;\n func0(test4, 3, &out4, &out4_size);\n assert(issame(out4, out4_size, expected4, 2));\n free(out4);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r14\nmovsxd r11, esi\nmov r14, rdx\npush r13\nmov r13, r11\npush r12\nlea r12, ds:0[r11*4]\npush rbp\nmov rbp, rcx\npush rbx\nmov rbx, rdi\nmov rdi, r12; size\ncall _malloc\nmov [r14], rax\nmov dword ptr [rbp+0], 0\ntest r13d, r13d\njle loc_1507\nmov r8, rax\nmov r9, rbx\nlea r11, [rbx+r12]\nxor edi, edi\nmov esi, 0CCCCCCCDh\nnop\nloc_1480:\nmov r10d, [r9]\ntest r10d, r10d\njle loc_1530\nmov eax, r10d\nnop\nloc_1490:\nmov edx, eax\nmov eax, eax\nmov rcx, rax\nimul rax, rsi\nnot edx\nand edx, 1\nshr rax, 23h\ncmp ecx, 9\njle short loc_1510\ntest dl, dl\njz short loc_1490\nloc_14AD:\nadd r9, 4\ncmp r9, r11\njnz short loc_1480\nloc_14B6:\ncmp edi, 1\njle short loc_1507\nlea r9, [r8+4]\nnop\nloc_14C0:\ncmp edi, 1\njle loc_1548\nlea edx, [rdi-2]\nmov rax, r8\nlea rsi, [r9+rdx*4]\nnop dword ptr [rax+rax+00h]\nloc_14D8:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd edx, xmm0\nmovd ecx, xmm1\ncmp ecx, edx\njge short loc_14F6\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_14F6:\nadd rax, 4\ncmp rsi, rax\njnz short loc_14D8\nsub edi, 1\ncmp edi, 1\njnz short loc_14C0\nloc_1507:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1510:\ntest dl, dl\njnz short loc_14AD\nloc_1514:\nmovsxd rax, edi\nadd r9, 4\nadd edi, 1\nmov [r8+rax*4], r10d\nmov [rbp+0], edi\ncmp r9, r11\njnz loc_1480\njmp short loc_14B6\nloc_1530:\njnz short loc_1514\nadd r9, 4\ncmp r9, r11\njnz loc_1480\njmp loc_14B6\nloc_1548:\nsub edi, 1\njmp loc_14C0", + "ida_pseudo": "unsigned __int64 __fastcall func0(int *a1, int a2, unsigned __int64 *a3, int *a4)\n{\n unsigned __int64 result; // rax\n unsigned __int64 v7; // r8\n int *v8; // r9\n int *v9; // r11\n int v10; // edi\n int v11; // r10d\n int v12; // ecx\n bool v13; // dl\n __m128i v14; // xmm0\n\n result = (unsigned __int64)malloc(4LL * a2);\n *a3 = result;\n *a4 = 0;\n if ( a2 > 0 )\n {\n v7 = result;\n v8 = a1;\n v9 = &a1[a2];\n v10 = 0;\n while ( 2 )\n {\n while ( 1 )\n {\n v11 = *v8;\n if ( *v8 > 0 )\n break;\n if ( v11 )\n {\nLABEL_17:\n result = v10;\n ++v8;\n ++v10;\n *(_DWORD *)(v7 + 4 * result) = v11;\n *a4 = v10;\n if ( v8 == v9 )\n goto LABEL_8;\n }\n else if ( ++v8 == v9 )\n {\n goto LABEL_8;\n }\n }\n LODWORD(result) = *v8;\n while ( 1 )\n {\n v12 = result;\n v13 = (result & 1) == 0;\n result = (unsigned int)result / 0xAuLL;\n if ( v12 <= 9 )\n break;\n if ( v13 )\n goto LABEL_7;\n }\n if ( !v13 )\n goto LABEL_17;\nLABEL_7:\n if ( ++v8 != v9 )\n continue;\n break;\n }\nLABEL_8:\n if ( v10 > 1 )\n {\n do\n {\n while ( v10 <= 1 )\n --v10;\n result = v7;\n do\n {\n v14 = _mm_loadl_epi64((const __m128i *)result);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v14, 229)) < _mm_cvtsi128_si32(v14) )\n *(_QWORD *)result = _mm_shuffle_epi32(v14, 225).m128i_u64[0];\n result += 4LL;\n }\n while ( v7 + 4 + 4LL * (unsigned int)(v10 - 2) != result );\n --v10;\n }\n while ( v10 != 1 );\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1430:\nendbr64\npush r14\nmovsxd r11, esi\nmov r14, rdx\npush r13\nmov r13, r11\npush r12\nlea r12, ds:0[r11*4]\npush rbp\nmov rbp, rcx\npush rbx\nmov rbx, rdi\nmov rdi, r12; size\ncall _malloc\nmov [r14], rax\nmov dword ptr [rbp+0], 0\ntest r13d, r13d\njle loc_1507\nmov r8, rax\nmov r9, rbx\nlea r11, [rbx+r12]\nxor edi, edi\nmov esi, 0CCCCCCCDh\nnop\nloc_1480:\nmov r10d, [r9]\ntest r10d, r10d\njle loc_1530\nmov eax, r10d\nnop\nloc_1490:\nmov edx, eax\nmov eax, eax\nmov rcx, rax\nimul rax, rsi\nnot edx\nand edx, 1\nshr rax, 23h\ncmp ecx, 9\njle short loc_1510\ntest dl, dl\njz short loc_1490\nloc_14AD:\nadd r9, 4\ncmp r9, r11\njnz short loc_1480\nloc_14B6:\ncmp edi, 1\njle short loc_1507\nlea r9, [r8+4]\nnop\nloc_14C0:\ncmp edi, 1\njle loc_1548\nlea edx, [rdi-2]\nmov rax, r8\nlea rsi, [r9+rdx*4]\nnop dword ptr [rax+rax+00h]\nloc_14D8:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd edx, xmm0\nmovd ecx, xmm1\ncmp ecx, edx\njge short loc_14F6\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_14F6:\nadd rax, 4\ncmp rsi, rax\njnz short loc_14D8\nsub edi, 1\ncmp edi, 1\njnz short loc_14C0\nloc_1507:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1510:\ntest dl, dl\njnz short loc_14AD\nloc_1514:\nmovsxd rax, edi\nadd r9, 4\nadd edi, 1\nmov [r8+rax*4], r10d\nmov [rbp+0], edi\ncmp r9, r11\njnz loc_1480\njmp short loc_14B6\nloc_1530:\njnz short loc_1514\nadd r9, 4\ncmp r9, r11\njnz loc_1480\njmp loc_14B6\nloc_1548:\nsub edi, 1\njmp loc_14C0", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_1430(int *a1, int a2, unsigned __int64 *a3, int *a4)\n{\n unsigned __int64 result; // rax\n unsigned __int64 v7; // r8\n int *v8; // r9\n int *v9; // r11\n int v10; // edi\n int v11; // r10d\n int v12; // ecx\n bool v13; // dl\n __m128i v14; // xmm0\n\n result = (unsigned __int64)malloc(4LL * a2);\n *a3 = result;\n *a4 = 0;\n if ( a2 > 0 )\n {\n v7 = result;\n v8 = a1;\n v9 = &a1[a2];\n v10 = 0;\n while ( 2 )\n {\n while ( 1 )\n {\n v11 = *v8;\n if ( *v8 > 0 )\n break;\n if ( v11 )\n {\nLABEL_17:\n result = v10;\n ++v8;\n ++v10;\n *(_DWORD *)(v7 + 4 * result) = v11;\n *a4 = v10;\n if ( v8 == v9 )\n goto LABEL_8;\n }\n else if ( ++v8 == v9 )\n {\n goto LABEL_8;\n }\n }\n LODWORD(result) = *v8;\n while ( 1 )\n {\n v12 = result;\n v13 = (result & 1) == 0;\n result = (unsigned int)result / 0xAuLL;\n if ( v12 <= 9 )\n break;\n if ( v13 )\n goto LABEL_7;\n }\n if ( !v13 )\n goto LABEL_17;\nLABEL_7:\n if ( ++v8 != v9 )\n continue;\n break;\n }\nLABEL_8:\n if ( v10 > 1 )\n {\n do\n {\n while ( v10 <= 1 )\n --v10;\n result = v7;\n do\n {\n v14 = _mm_loadl_epi64((const __m128i *)result);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v14, 229)) < _mm_cvtsi128_si32(v14) )\n *(_QWORD *)result = _mm_shuffle_epi32(v14, 225).m128i_u64[0];\n result += 4LL;\n }\n while ( v7 + 4 + 4LL * (unsigned int)(v10 - 2) != result );\n --v10;\n }\n while ( v10 != 1 );\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_1430(int *a1, int a2, unsigned long long *a3, int *a4) {\n unsigned long long result;\n unsigned long long v7;\n int *v8;\n int *v9;\n int v10;\n int v11;\n int v12;\n bool v13;\n __m128i v14;\n result = (unsigned long long)malloc(4LL * a2);\n *a3 = result;\n *a4 = 0;\n if (a2 > 0) {\n v7 = result;\n v8 = a1;\n v9 = &a1[a2];\n v10 = 0;\n while (2) {\n while (1) {\n v11 = *v8;\n if (*v8 > 0) break;\n if (v11) {\n LABEL_17:\n result = v10;\n ++v8;\n ++v10;\n *(uint32_t *)(v7 + 4 * result) = v11;\n *a4 = v10;\n if (v8 == v9) goto LABEL_8;\n } else if (++v8 == v9) {\n goto LABEL_8;\n }\n }\n LODWORD(result) = *v8;\n while (1) {\n v12 = result;\n v13 = (result & 1) == 0;\n result = (unsigned int)result / 10uLL;\n if (v12 <= 9) break;\n if (v13) goto LABEL_7;\n }\n if (!v13) goto LABEL_17;\n LABEL_7:\n if (++v8 != v9) continue;\n break;\n }\n LABEL_8:\n if (v10 > 1) {\n do {\n while (v10 <= 1) --v10;\n result = v7;\n do {\n v14 = _mm_loadl_epi64((const __m128i *)result);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v14, 229)) <\n _mm_cvtsi128_si32(v14))\n *(uint64_t *)result = _mm_shuffle_epi32(v14, 225).m128i_u64[0];\n result += 4LL;\n } while (v7 + 4 + 4LL * (unsigned int)(v10 - 2) != result);\n --v10;\n } while (v10 != 1);\n }\n }\n return result;\n}", + "ida_pseudo_norm": "unsigned long long func0(int *a1, int a2, unsigned long long *a3, int *a4) {\n unsigned long long result;\n unsigned long long v7;\n int *v8;\n int *v9;\n int v10;\n int v11;\n int v12;\n bool v13;\n __m128i v14;\n result = (unsigned long long)malloc(4LL * a2);\n *a3 = result;\n *a4 = 0;\n if (a2 > 0) {\n v7 = result;\n v8 = a1;\n v9 = &a1[a2];\n v10 = 0;\n while (2) {\n while (1) {\n v11 = *v8;\n if (*v8 > 0) break;\n if (v11) {\n LABEL_17:\n result = v10;\n ++v8;\n ++v10;\n *(uint32_t *)(v7 + 4 * result) = v11;\n *a4 = v10;\n if (v8 == v9) goto LABEL_8;\n } else if (++v8 == v9) {\n goto LABEL_8;\n }\n }\n LODWORD(result) = *v8;\n while (1) {\n v12 = result;\n v13 = (result & 1) == 0;\n result = (unsigned int)result / 10uLL;\n if (v12 <= 9) break;\n if (v13) goto LABEL_7;\n }\n if (!v13) goto LABEL_17;\n LABEL_7:\n if (++v8 != v9) continue;\n break;\n }\n LABEL_8:\n if (v10 > 1) {\n do {\n while (v10 <= 1) --v10;\n result = v7;\n do {\n v14 = _mm_loadl_epi64((const __m128i *)result);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v14, 229)) <\n _mm_cvtsi128_si32(v14))\n *(uint64_t *)result = _mm_shuffle_epi32(v14, 225).m128i_u64[0];\n result += 4LL;\n } while (v7 + 4 + 4LL * (unsigned int)(v10 - 2) != result);\n --v10;\n } while (v10 != 1);\n }\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-104", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "void func0(int *x, int size, int **out, int *out_size) {\n *out = malloc(size * sizeof(int));\n *out_size = 0;\n for (int i = 0; i < size; i++) {\n int num = x[i];\n bool has_even_digit = false;\n if (num == 0) has_even_digit = true;\n while (num > 0 && !has_even_digit) {\n if (num % 2 == 0) has_even_digit = true;\n num = num / 10;\n }\n if (!has_even_digit) {\n (*out)[*out_size] = x[i];\n (*out_size)++;\n }\n }\n for (int i = 0; i < *out_size - 1; i++) {\n for (int j = 0; j < *out_size - i - 1; j++) {\n if ((*out)[j] > (*out)[j + 1]) {\n int temp = (*out)[j];\n (*out)[j] = (*out)[j + 1];\n (*out)[j + 1] = temp;\n }\n }\n }\n}", + "test": "#include \n#include \n#include \n#include \n\nbool issame(int *a, int a_size, int *b, int b_size) {\n if (a_size != b_size) return false;\n for (int i = 0; i < a_size; i++) {\n if (a[i] != b[i]) return false;\n }\n return true;\n}\n\nint main() {\n // Test cases\n int test1[] = {15, 33, 1422, 1};\n int expected1[] = {1, 15, 33};\n int *out1;\n int out1_size;\n func0(test1, 4, &out1, &out1_size);\n assert(issame(out1, out1_size, expected1, 3));\n free(out1);\n\n int test2[] = {152, 323, 1422, 10};\n int *out2;\n int out2_size;\n func0(test2, 4, &out2, &out2_size);\n assert(issame(out2, out2_size, NULL, 0));\n free(out2);\n\n int test3[] = {12345, 2033, 111, 151};\n int expected3[] = {111, 151};\n int *out3;\n int out3_size;\n func0(test3, 4, &out3, &out3_size);\n assert(issame(out3, out3_size, expected3, 2));\n free(out3);\n\n int test4[] = {135, 103, 31};\n int expected4[] = {31, 135};\n int *out4;\n int out4_size;\n func0(test4, 3, &out4, &out4_size);\n assert(issame(out4, out4_size, expected4, 2));\n free(out4);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r14\nmovsxd r11, esi\nmov r14, rdx\npush r13\nmov r13, r11\npush r12\nlea r12, ds:0[r11*4]\npush rbp\nmov rbp, rcx\npush rbx\nmov rbx, rdi\nmov rdi, r12; size\ncall _malloc\nmov [r14], rax\nmov dword ptr [rbp+0], 0\ntest r13d, r13d\njle loc_1507\nmov r8, rax\nmov r9, rbx\nlea r11, [rbx+r12]\nxor edi, edi\nmov esi, 0CCCCCCCDh\nnop\nloc_1480:\nmov r10d, [r9]\ntest r10d, r10d\njle loc_1530\nmov eax, r10d\nnop\nloc_1490:\nmov edx, eax\nmov eax, eax\nmov rcx, rax\nimul rax, rsi\nnot edx\nand edx, 1\nshr rax, 23h\ncmp ecx, 9\njle short loc_1510\ntest dl, dl\njz short loc_1490\nloc_14AD:\nadd r9, 4\ncmp r11, r9\njnz short loc_1480\nloc_14B6:\ncmp edi, 1\njle short loc_1507\nlea r9, [r8+4]\nnop\nloc_14C0:\ncmp edi, 1\njle loc_1548\nlea edx, [rdi-2]\nmov rax, r8\nlea rsi, [r9+rdx*4]\nnop dword ptr [rax+rax+00h]\nloc_14D8:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd edx, xmm0\nmovd ecx, xmm1\ncmp ecx, edx\njge short loc_14F6\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_14F6:\nadd rax, 4\ncmp rsi, rax\njnz short loc_14D8\nsub edi, 1\ncmp edi, 1\njnz short loc_14C0\nloc_1507:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1510:\ntest dl, dl\njnz short loc_14AD\nloc_1514:\nmovsxd rax, edi\nadd r9, 4\nadd edi, 1\nmov [r8+rax*4], r10d\nmov [rbp+0], edi\ncmp r11, r9\njnz loc_1480\njmp short loc_14B6\nloc_1530:\njnz short loc_1514\nadd r9, 4\ncmp r11, r9\njnz loc_1480\njmp loc_14B6\nloc_1548:\nsub edi, 1\njmp loc_14C0", + "ida_pseudo": "unsigned __int64 __fastcall func0(int *a1, int a2, unsigned __int64 *a3, int *a4)\n{\n unsigned __int64 result; // rax\n unsigned __int64 v7; // r8\n int *v8; // r9\n int *v9; // r11\n int v10; // edi\n int v11; // r10d\n int v12; // ecx\n bool v13; // dl\n __m128i v14; // xmm0\n\n result = (unsigned __int64)malloc(4LL * a2);\n *a3 = result;\n *a4 = 0;\n if ( a2 > 0 )\n {\n v7 = result;\n v8 = a1;\n v9 = &a1[a2];\n v10 = 0;\n while ( 2 )\n {\n while ( 1 )\n {\n v11 = *v8;\n if ( *v8 > 0 )\n break;\n if ( v11 )\n {\nLABEL_17:\n result = v10;\n ++v8;\n ++v10;\n *(_DWORD *)(v7 + 4 * result) = v11;\n *a4 = v10;\n if ( v9 == v8 )\n goto LABEL_8;\n }\n else if ( v9 == ++v8 )\n {\n goto LABEL_8;\n }\n }\n LODWORD(result) = *v8;\n while ( 1 )\n {\n v12 = result;\n v13 = (result & 1) == 0;\n result = (unsigned int)result / 0xAuLL;\n if ( v12 <= 9 )\n break;\n if ( v13 )\n goto LABEL_7;\n }\n if ( !v13 )\n goto LABEL_17;\nLABEL_7:\n if ( v9 != ++v8 )\n continue;\n break;\n }\nLABEL_8:\n if ( v10 > 1 )\n {\n do\n {\n while ( v10 <= 1 )\n --v10;\n result = v7;\n do\n {\n v14 = _mm_loadl_epi64((const __m128i *)result);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v14, 229)) < _mm_cvtsi128_si32(v14) )\n *(_QWORD *)result = _mm_shuffle_epi32(v14, 225).m128i_u64[0];\n result += 4LL;\n }\n while ( v7 + 4 + 4LL * (unsigned int)(v10 - 2) != result );\n --v10;\n }\n while ( v10 != 1 );\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1430:\nendbr64\npush r14\nmovsxd r11, esi\nmov r14, rdx\npush r13\nmov r13, r11\npush r12\nlea r12, ds:0[r11*4]\npush rbp\nmov rbp, rcx\npush rbx\nmov rbx, rdi\nmov rdi, r12; size\ncall _malloc\nmov [r14], rax\nmov dword ptr [rbp+0], 0\ntest r13d, r13d\njle loc_1507\nmov r8, rax\nmov r9, rbx\nlea r11, [rbx+r12]\nxor edi, edi\nmov esi, 0CCCCCCCDh\nnop\nloc_1480:\nmov r10d, [r9]\ntest r10d, r10d\njle loc_1530\nmov eax, r10d\nnop\nloc_1490:\nmov edx, eax\nmov eax, eax\nmov rcx, rax\nimul rax, rsi\nnot edx\nand edx, 1\nshr rax, 23h\ncmp ecx, 9\njle short loc_1510\ntest dl, dl\njz short loc_1490\nloc_14AD:\nadd r9, 4\ncmp r11, r9\njnz short loc_1480\nloc_14B6:\ncmp edi, 1\njle short loc_1507\nlea r9, [r8+4]\nnop\nloc_14C0:\ncmp edi, 1\njle loc_1548\nlea edx, [rdi-2]\nmov rax, r8\nlea rsi, [r9+rdx*4]\nnop dword ptr [rax+rax+00h]\nloc_14D8:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd edx, xmm0\nmovd ecx, xmm1\ncmp ecx, edx\njge short loc_14F6\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_14F6:\nadd rax, 4\ncmp rsi, rax\njnz short loc_14D8\nsub edi, 1\ncmp edi, 1\njnz short loc_14C0\nloc_1507:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1510:\ntest dl, dl\njnz short loc_14AD\nloc_1514:\nmovsxd rax, edi\nadd r9, 4\nadd edi, 1\nmov [r8+rax*4], r10d\nmov [rbp+0], edi\ncmp r11, r9\njnz loc_1480\njmp short loc_14B6\nloc_1530:\njnz short loc_1514\nadd r9, 4\ncmp r11, r9\njnz loc_1480\njmp loc_14B6\nloc_1548:\nsub edi, 1\njmp loc_14C0", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_1430(int *a1, int a2, unsigned __int64 *a3, int *a4)\n{\n unsigned __int64 result; // rax\n unsigned __int64 v7; // r8\n int *v8; // r9\n int *v9; // r11\n int v10; // edi\n int v11; // r10d\n int v12; // ecx\n bool v13; // dl\n __m128i v14; // xmm0\n\n result = (unsigned __int64)malloc(4LL * a2);\n *a3 = result;\n *a4 = 0;\n if ( a2 > 0 )\n {\n v7 = result;\n v8 = a1;\n v9 = &a1[a2];\n v10 = 0;\n while ( 2 )\n {\n while ( 1 )\n {\n v11 = *v8;\n if ( *v8 > 0 )\n break;\n if ( v11 )\n {\nLABEL_17:\n result = v10;\n ++v8;\n ++v10;\n *(_DWORD *)(v7 + 4 * result) = v11;\n *a4 = v10;\n if ( v9 == v8 )\n goto LABEL_8;\n }\n else if ( v9 == ++v8 )\n {\n goto LABEL_8;\n }\n }\n LODWORD(result) = *v8;\n while ( 1 )\n {\n v12 = result;\n v13 = (result & 1) == 0;\n result = (unsigned int)result / 0xAuLL;\n if ( v12 <= 9 )\n break;\n if ( v13 )\n goto LABEL_7;\n }\n if ( !v13 )\n goto LABEL_17;\nLABEL_7:\n if ( v9 != ++v8 )\n continue;\n break;\n }\nLABEL_8:\n if ( v10 > 1 )\n {\n do\n {\n while ( v10 <= 1 )\n --v10;\n result = v7;\n do\n {\n v14 = _mm_loadl_epi64((const __m128i *)result);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v14, 229)) < _mm_cvtsi128_si32(v14) )\n *(_QWORD *)result = _mm_shuffle_epi32(v14, 225).m128i_u64[0];\n result += 4LL;\n }\n while ( v7 + 4 + 4LL * (unsigned int)(v10 - 2) != result );\n --v10;\n }\n while ( v10 != 1 );\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_1430(int *a1, int a2, unsigned long long *a3, int *a4) {\n unsigned long long result;\n unsigned long long v7;\n int *v8;\n int *v9;\n int v10;\n int v11;\n int v12;\n bool v13;\n __m128i v14;\n result = (unsigned long long)malloc(4LL * a2);\n *a3 = result;\n *a4 = 0;\n if (a2 > 0) {\n v7 = result;\n v8 = a1;\n v9 = &a1[a2];\n v10 = 0;\n while (2) {\n while (1) {\n v11 = *v8;\n if (*v8 > 0) break;\n if (v11) {\n LABEL_17:\n result = v10;\n ++v8;\n ++v10;\n *(uint32_t *)(v7 + 4 * result) = v11;\n *a4 = v10;\n if (v9 == v8) goto LABEL_8;\n } else if (v9 == ++v8) {\n goto LABEL_8;\n }\n }\n LODWORD(result) = *v8;\n while (1) {\n v12 = result;\n v13 = (result & 1) == 0;\n result = (unsigned int)result / 10uLL;\n if (v12 <= 9) break;\n if (v13) goto LABEL_7;\n }\n if (!v13) goto LABEL_17;\n LABEL_7:\n if (v9 != ++v8) continue;\n break;\n }\n LABEL_8:\n if (v10 > 1) {\n do {\n while (v10 <= 1) --v10;\n result = v7;\n do {\n v14 = _mm_loadl_epi64((const __m128i *)result);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v14, 229)) <\n _mm_cvtsi128_si32(v14))\n *(uint64_t *)result = _mm_shuffle_epi32(v14, 225).m128i_u64[0];\n result += 4LL;\n } while (v7 + 4 + 4LL * (unsigned int)(v10 - 2) != result);\n --v10;\n } while (v10 != 1);\n }\n }\n return result;\n}", + "ida_pseudo_norm": "unsigned long long func0(int *a1, int a2, unsigned long long *a3, int *a4) {\n unsigned long long result;\n unsigned long long v7;\n int *v8;\n int *v9;\n int v10;\n int v11;\n int v12;\n bool v13;\n __m128i v14;\n result = (unsigned long long)malloc(4LL * a2);\n *a3 = result;\n *a4 = 0;\n if (a2 > 0) {\n v7 = result;\n v8 = a1;\n v9 = &a1[a2];\n v10 = 0;\n while (2) {\n while (1) {\n v11 = *v8;\n if (*v8 > 0) break;\n if (v11) {\n LABEL_17:\n result = v10;\n ++v8;\n ++v10;\n *(uint32_t *)(v7 + 4 * result) = v11;\n *a4 = v10;\n if (v9 == v8) goto LABEL_8;\n } else if (v9 == ++v8) {\n goto LABEL_8;\n }\n }\n LODWORD(result) = *v8;\n while (1) {\n v12 = result;\n v13 = (result & 1) == 0;\n result = (unsigned int)result / 10uLL;\n if (v12 <= 9) break;\n if (v13) goto LABEL_7;\n }\n if (!v13) goto LABEL_17;\n LABEL_7:\n if (v9 != ++v8) continue;\n break;\n }\n LABEL_8:\n if (v10 > 1) {\n do {\n while (v10 <= 1) --v10;\n result = v7;\n do {\n v14 = _mm_loadl_epi64((const __m128i *)result);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v14, 229)) <\n _mm_cvtsi128_si32(v14))\n *(uint64_t *)result = _mm_shuffle_epi32(v14, 225).m128i_u64[0];\n result += 4LL;\n } while (v7 + 4 + 4LL * (unsigned int)(v10 - 2) != result);\n --v10;\n } while (v10 != 1);\n }\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-105", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "void func0(int *arr, int size, char ***out, int *out_size) {\n char *names[] = {\"\", \"One\", \"Two\", \"Three\", \"Four\",\n \"Five\", \"Six\", \"Seven\", \"Eight\", \"Nine\"};\n int i, j;\n for (i = 0; i < size - 1; i++) {\n for (j = 0; j < size - i - 1; j++) {\n if (arr[j] > arr[j + 1]) {\n int temp = arr[j];\n arr[j] = arr[j + 1];\n arr[j + 1] = temp;\n }\n }\n }\n *out_size = 0;\n for (i = size - 1; i >= 0; i--) {\n if (arr[i] >= 1 && arr[i] <= 9) {\n (*out_size)++;\n }\n }\n *out = malloc(*out_size * sizeof(char *));\n for (i = size - 1, j = 0; i >= 0 && j < *out_size; i--) {\n if (arr[i] >= 1 && arr[i] <= 9) {\n (*out)[j++] = names[arr[i]];\n }\n }\n}", + "test": "#include \n#include \n#include \n#include \n\nint issame(char **a, int a_size, char **b, int b_size) {\n if (a_size != b_size) return 0;\n for (int i = 0; i < a_size; i++) {\n if (strcmp(a[i], b[i]) != 0) return 0;\n }\n return 1;\n}\n\nint main() {\n char **out;\n int out_size;\n\n int test1[] = {2, 1, 1, 4, 5, 8, 2, 3};\n char *expected1[] = {\"Eight\", \"Five\", \"Four\", \"Three\", \"Two\", \"Two\", \"One\", \"One\"};\n func0(test1, 8, &out, &out_size);\n assert(issame(out, out_size, expected1, 8));\n free(out);\n\n int test2[] = {};\n func0(test2, 0, &out, &out_size);\n assert(issame(out, out_size, NULL, 0));\n free(out);\n\n int test3[] = {1, -1, 55};\n char *expected3[] = {\"One\"};\n func0(test3, 3, &out, &out_size);\n assert(issame(out, out_size, expected3, 1));\n free(out);\n\n int test4[] = {1, -1, 3, 2};\n char *expected4[] = {\"Three\", \"Two\", \"One\"};\n func0(test4, 4, &out, &out_size);\n assert(issame(out, out_size, expected4, 3));\n free(out);\n\n int test5[] = {9, 4, 8};\n char *expected5[] = {\"Nine\", \"Eight\", \"Four\"};\n func0(test5, 3, &out, &out_size);\n assert(issame(out, out_size, expected5, 3));\n free(out);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 90h\nmov [rbp+var_78], rdi\nmov [rbp+var_7C], esi\nmov [rbp+var_88], rdx\nmov [rbp+var_90], rcx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, unk_2008\nmov [rbp+var_60], rax\nlea rax, unk_2009\nmov [rbp+var_58], rax\nlea rax, unk_200D\nmov [rbp+var_50], rax\nlea rax, aThree; \"Three\"\nmov [rbp+var_48], rax\nlea rax, aFour; \"Four\"\nmov [rbp+var_40], rax\nlea rax, aFive; \"Five\"\nmov [rbp+var_38], rax\nlea rax, aSix; \"Six\"\nmov [rbp+var_30], rax\nlea rax, aSeven; \"Seven\"\nmov [rbp+var_28], rax\nlea rax, aEight; \"Eight\"\nmov [rbp+var_20], rax\nlea rax, aNine; \"Nine\"\nmov [rbp+var_18], rax\nmov [rbp+var_6C], 0\njmp loc_1337\nloc_1276:\nmov [rbp+var_68], 0\njmp loc_1321\nloc_1282:\nmov eax, [rbp+var_68]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_78]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_68]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_78]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_131D\nmov eax, [rbp+var_68]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_78]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_64], eax\nmov eax, [rbp+var_68]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_78]\nadd rax, rdx\nmov edx, [rbp+var_68]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_78]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_68]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_78]\nadd rdx, rax\nmov eax, [rbp+var_64]\nmov [rdx], eax\nloc_131D:\nadd [rbp+var_68], 1\nloc_1321:\nmov eax, [rbp+var_7C]\nsub eax, [rbp+var_6C]\nsub eax, 1\ncmp [rbp+var_68], eax\njl loc_1282\nadd [rbp+var_6C], 1\nloc_1337:\nmov eax, [rbp+var_7C]\nsub eax, 1\ncmp [rbp+var_6C], eax\njl loc_1276\nmov rax, [rbp+var_90]\nmov dword ptr [rax], 0\nmov eax, [rbp+var_7C]\nsub eax, 1\nmov [rbp+var_6C], eax\njmp short loc_13AC\nloc_135E:\nmov eax, [rbp+var_6C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_78]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njle short loc_13A8\nmov eax, [rbp+var_6C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_78]\nadd rax, rdx\nmov eax, [rax]\ncmp eax, 9\njg short loc_13A8\nmov rax, [rbp+var_90]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_90]\nmov [rax], edx\nloc_13A8:\nsub [rbp+var_6C], 1\nloc_13AC:\ncmp [rbp+var_6C], 0\njns short loc_135E\nmov rax, [rbp+var_90]\nmov eax, [rax]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov rdx, rax\nmov rax, [rbp+var_88]\nmov [rax], rdx\nmov eax, [rbp+var_7C]\nsub eax, 1\nmov [rbp+var_6C], eax\nmov [rbp+var_68], 0\njmp short loc_145F\nloc_13E8:\nmov eax, [rbp+var_6C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_78]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njle short loc_145B\nmov eax, [rbp+var_6C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_78]\nadd rax, rdx\nmov eax, [rax]\ncmp eax, 9\njg short loc_145B\nmov eax, [rbp+var_6C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_78]\nadd rax, rdx\nmov ecx, [rax]\nmov rax, [rbp+var_88]\nmov rsi, [rax]\nmov eax, [rbp+var_68]\nlea edx, [rax+1]\nmov [rbp+var_68], edx\ncdqe\nshl rax, 3\nlea rdx, [rsi+rax]\nmovsxd rax, ecx\nmov rax, [rbp+rax*8+var_60]\nmov [rdx], rax\nloc_145B:\nsub [rbp+var_6C], 1\nloc_145F:\ncmp [rbp+var_6C], 0\njs short loc_1477\nmov rax, [rbp+var_90]\nmov eax, [rax]\ncmp [rbp+var_68], eax\njl loc_13E8\nloc_1477:\nnop\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njz short locret_148C\ncall ___stack_chk_fail\nlocret_148C:\nleave\nretn", + "ida_pseudo": "unsigned __int64 __fastcall func0(__int64 a1, int a2, void **a3, int *a4)\n{\n int v4; // eax\n int i; // [rsp+24h] [rbp-6Ch]\n int k; // [rsp+24h] [rbp-6Ch]\n int v10; // [rsp+24h] [rbp-6Ch]\n int j; // [rsp+28h] [rbp-68h]\n int v12; // [rsp+28h] [rbp-68h]\n int v13; // [rsp+2Ch] [rbp-64h]\n _QWORD v14[11]; // [rsp+30h] [rbp-60h]\n unsigned __int64 v15; // [rsp+88h] [rbp-8h]\n\n v15 = __readfsqword(0x28u);\n v14[0] = &unk_2008;\n v14[1] = &unk_2009;\n v14[2] = &unk_200D;\n v14[3] = \"Three\";\n v14[4] = \"Four\";\n v14[5] = \"Five\";\n v14[6] = \"Six\";\n v14[7] = \"Seven\";\n v14[8] = \"Eight\";\n v14[9] = \"Nine\";\n for ( i = 0; i < a2 - 1; ++i )\n {\n for ( j = 0; j < a2 - i - 1; ++j )\n {\n if ( *(_DWORD *)(4LL * j + a1) > *(_DWORD *)(4 * (j + 1LL) + a1) )\n {\n v13 = *(_DWORD *)(4LL * j + a1);\n *(_DWORD *)(4LL * j + a1) = *(_DWORD *)(4 * (j + 1LL) + a1);\n *(_DWORD *)(a1 + 4 * (j + 1LL)) = v13;\n }\n }\n }\n *a4 = 0;\n for ( k = a2 - 1; k >= 0; --k )\n {\n if ( *(int *)(4LL * k + a1) > 0 && *(int *)(4LL * k + a1) <= 9 )\n ++*a4;\n }\n *a3 = malloc(8LL * *a4);\n v10 = a2 - 1;\n v12 = 0;\n while ( v10 >= 0 && v12 < *a4 )\n {\n if ( *(int *)(4LL * v10 + a1) > 0 && *(int *)(4LL * v10 + a1) <= 9 )\n {\n v4 = v12++;\n *((_QWORD *)*a3 + v4) = v14[*(int *)(4LL * v10 + a1)];\n }\n --v10;\n }\n return v15 - __readfsqword(0x28u);\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 90h\nmov [rbp+var_78], rdi\nmov [rbp+var_7C], esi\nmov [rbp+var_88], rdx\nmov [rbp+var_90], rcx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, unk_2008\nmov [rbp+var_60], rax\nlea rax, unk_2009\nmov [rbp+var_58], rax\nlea rax, unk_200D\nmov [rbp+var_50], rax\nlea rax, aThree; \"Three\"\nmov [rbp+var_48], rax\nlea rax, aFour; \"Four\"\nmov [rbp+var_40], rax\nlea rax, aFive; \"Five\"\nmov [rbp+var_38], rax\nlea rax, aSix; \"Six\"\nmov [rbp+var_30], rax\nlea rax, aSeven; \"Seven\"\nmov [rbp+var_28], rax\nlea rax, aEight; \"Eight\"\nmov [rbp+var_20], rax\nlea rax, aNine; \"Nine\"\nmov [rbp+var_18], rax\nmov [rbp+var_6C], 0\njmp loc_1337\nloc_1276:\nmov [rbp+var_68], 0\njmp loc_1321\nloc_1282:\nmov eax, [rbp+var_68]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_78]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_68]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_78]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_131D\nmov eax, [rbp+var_68]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_78]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_64], eax\nmov eax, [rbp+var_68]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_78]\nadd rax, rdx\nmov edx, [rbp+var_68]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_78]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_68]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_78]\nadd rdx, rax\nmov eax, [rbp+var_64]\nmov [rdx], eax\nloc_131D:\nadd [rbp+var_68], 1\nloc_1321:\nmov eax, [rbp+var_7C]\nsub eax, [rbp+var_6C]\nsub eax, 1\ncmp [rbp+var_68], eax\njl loc_1282\nadd [rbp+var_6C], 1\nloc_1337:\nmov eax, [rbp+var_7C]\nsub eax, 1\ncmp [rbp+var_6C], eax\njl loc_1276\nmov rax, [rbp+var_90]\nmov dword ptr [rax], 0\nmov eax, [rbp+var_7C]\nsub eax, 1\nmov [rbp+var_6C], eax\njmp short loc_13AC\nloc_135E:\nmov eax, [rbp+var_6C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_78]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njle short loc_13A8\nmov eax, [rbp+var_6C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_78]\nadd rax, rdx\nmov eax, [rax]\ncmp eax, 9\njg short loc_13A8\nmov rax, [rbp+var_90]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_90]\nmov [rax], edx\nloc_13A8:\nsub [rbp+var_6C], 1\nloc_13AC:\ncmp [rbp+var_6C], 0\njns short loc_135E\nmov rax, [rbp+var_90]\nmov eax, [rax]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov rdx, rax\nmov rax, [rbp+var_88]\nmov [rax], rdx\nmov eax, [rbp+var_7C]\nsub eax, 1\nmov [rbp+var_6C], eax\nmov [rbp+var_68], 0\njmp short loc_145F\nloc_13E8:\nmov eax, [rbp+var_6C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_78]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njle short loc_145B\nmov eax, [rbp+var_6C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_78]\nadd rax, rdx\nmov eax, [rax]\ncmp eax, 9\njg short loc_145B\nmov eax, [rbp+var_6C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_78]\nadd rax, rdx\nmov ecx, [rax]\nmov rax, [rbp+var_88]\nmov rsi, [rax]\nmov eax, [rbp+var_68]\nlea edx, [rax+1]\nmov [rbp+var_68], edx\ncdqe\nshl rax, 3\nlea rdx, [rsi+rax]\nmovsxd rax, ecx\nmov rax, [rbp+rax*8+var_60]\nmov [rdx], rax\nloc_145B:\nsub [rbp+var_6C], 1\nloc_145F:\ncmp [rbp+var_6C], 0\njs short loc_1477\nmov rax, [rbp+var_90]\nmov eax, [rax]\ncmp [rbp+var_68], eax\njl loc_13E8\nloc_1477:\nnop\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njz short locret_148C\ncall ___stack_chk_fail\nlocret_148C:\nleave\nretn", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_11C9(__int64 a1, int a2, void **a3, int *a4)\n{\n int v4; // eax\n int i; // [rsp+24h] [rbp-6Ch]\n int k; // [rsp+24h] [rbp-6Ch]\n int v10; // [rsp+24h] [rbp-6Ch]\n int j; // [rsp+28h] [rbp-68h]\n int v12; // [rsp+28h] [rbp-68h]\n int v13; // [rsp+2Ch] [rbp-64h]\n _QWORD v14[11]; // [rsp+30h] [rbp-60h]\n unsigned __int64 v15; // [rsp+88h] [rbp-8h]\n\n v15 = __readfsqword(0x28u);\n v14[0] = &unk_2008;\n v14[1] = &unk_2009;\n v14[2] = &unk_200D;\n v14[3] = \"Three\";\n v14[4] = \"Four\";\n v14[5] = \"Five\";\n v14[6] = \"Six\";\n v14[7] = \"Seven\";\n v14[8] = \"Eight\";\n v14[9] = \"Nine\";\n for ( i = 0; i < a2 - 1; ++i )\n {\n for ( j = 0; j < a2 - i - 1; ++j )\n {\n if ( *(_DWORD *)(4LL * j + a1) > *(_DWORD *)(4 * (j + 1LL) + a1) )\n {\n v13 = *(_DWORD *)(4LL * j + a1);\n *(_DWORD *)(4LL * j + a1) = *(_DWORD *)(4 * (j + 1LL) + a1);\n *(_DWORD *)(a1 + 4 * (j + 1LL)) = v13;\n }\n }\n }\n *a4 = 0;\n for ( k = a2 - 1; k >= 0; --k )\n {\n if ( *(int *)(4LL * k + a1) > 0 && *(int *)(4LL * k + a1) <= 9 )\n ++*a4;\n }\n *a3 = malloc(8LL * *a4);\n v10 = a2 - 1;\n v12 = 0;\n while ( v10 >= 0 && v12 < *a4 )\n {\n if ( *(int *)(4LL * v10 + a1) > 0 && *(int *)(4LL * v10 + a1) <= 9 )\n {\n v4 = v12++;\n *((_QWORD *)*a3 + v4) = v14[*(int *)(4LL * v10 + a1)];\n }\n --v10;\n }\n return v15 - __readfsqword(0x28u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_11C9(long long a1, int a2, void **a3, int *a4) {\n int v4;\n int i;\n int k;\n int v10;\n int j;\n int v12;\n int v13;\n uint64_t v14[11];\n unsigned long long v15;\n v15 = __readfsqword(40u);\n v14[0] = &unk_2008;\n v14[1] = &unk_2009;\n v14[2] = &unk_200D;\n v14[3] = \"Three\";\n v14[4] = \"Four\";\n v14[5] = \"Five\";\n v14[6] = \"Six\";\n v14[7] = \"Seven\";\n v14[8] = \"Eight\";\n v14[9] = \"Nine\";\n for (i = 0; i < a2 - 1; ++i) {\n for (j = 0; j < a2 - i - 1; ++j) {\n if (*(uint32_t *)(4LL * j + a1) > *(uint32_t *)(4 * (j + 1LL) + a1)) {\n v13 = *(uint32_t *)(4LL * j + a1);\n *(uint32_t *)(4LL * j + a1) = *(uint32_t *)(4 * (j + 1LL) + a1);\n *(uint32_t *)(a1 + 4 * (j + 1LL)) = v13;\n }\n }\n }\n *a4 = 0;\n for (k = a2 - 1; k >= 0; --k) {\n if (*(int *)(4LL * k + a1) > 0 && *(int *)(4LL * k + a1) <= 9) ++*a4;\n }\n *a3 = malloc(8LL * *a4);\n v10 = a2 - 1;\n v12 = 0;\n while (v10 >= 0 && v12 < *a4) {\n if (*(int *)(4LL * v10 + a1) > 0 && *(int *)(4LL * v10 + a1) <= 9) {\n v4 = v12++;\n *((uint64_t *)*a3 + v4) = v14[*(int *)(4LL * v10 + a1)];\n }\n --v10;\n }\n return v15 - __readfsqword(40u);\n}", + "ida_pseudo_norm": "unsigned long long func0(long long a1, int a2, void **a3, int *a4) {\n int v4;\n int i;\n int k;\n int v10;\n int j;\n int v12;\n int v13;\n uint64_t v14[11];\n unsigned long long v15;\n v15 = __readfsqword(40u);\n v14[0] = &unk_2008;\n v14[1] = &unk_2009;\n v14[2] = &unk_200D;\n v14[3] = \"Three\";\n v14[4] = \"Four\";\n v14[5] = \"Five\";\n v14[6] = \"Six\";\n v14[7] = \"Seven\";\n v14[8] = \"Eight\";\n v14[9] = \"Nine\";\n for (i = 0; i < a2 - 1; ++i) {\n for (j = 0; j < a2 - i - 1; ++j) {\n if (*(uint32_t *)(4LL * j + a1) > *(uint32_t *)(4 * (j + 1LL) + a1)) {\n v13 = *(uint32_t *)(4LL * j + a1);\n *(uint32_t *)(4LL * j + a1) = *(uint32_t *)(4 * (j + 1LL) + a1);\n *(uint32_t *)(a1 + 4 * (j + 1LL)) = v13;\n }\n }\n }\n *a4 = 0;\n for (k = a2 - 1; k >= 0; --k) {\n if (*(int *)(4LL * k + a1) > 0 && *(int *)(4LL * k + a1) <= 9) ++*a4;\n }\n *a3 = malloc(8LL * *a4);\n v10 = a2 - 1;\n v12 = 0;\n while (v10 >= 0 && v12 < *a4) {\n if (*(int *)(4LL * v10 + a1) > 0 && *(int *)(4LL * v10 + a1) <= 9) {\n v4 = v12++;\n *((uint64_t *)*a3 + v4) = v14[*(int *)(4LL * v10 + a1)];\n }\n --v10;\n }\n return v15 - __readfsqword(40u);\n}" + }, + { + "index": "HumanEval-C-105", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "void func0(int *arr, int size, char ***out, int *out_size) {\n char *names[] = {\"\", \"One\", \"Two\", \"Three\", \"Four\",\n \"Five\", \"Six\", \"Seven\", \"Eight\", \"Nine\"};\n int i, j;\n for (i = 0; i < size - 1; i++) {\n for (j = 0; j < size - i - 1; j++) {\n if (arr[j] > arr[j + 1]) {\n int temp = arr[j];\n arr[j] = arr[j + 1];\n arr[j + 1] = temp;\n }\n }\n }\n *out_size = 0;\n for (i = size - 1; i >= 0; i--) {\n if (arr[i] >= 1 && arr[i] <= 9) {\n (*out_size)++;\n }\n }\n *out = malloc(*out_size * sizeof(char *));\n for (i = size - 1, j = 0; i >= 0 && j < *out_size; i--) {\n if (arr[i] >= 1 && arr[i] <= 9) {\n (*out)[j++] = names[arr[i]];\n }\n }\n}", + "test": "#include \n#include \n#include \n#include \n\nint issame(char **a, int a_size, char **b, int b_size) {\n if (a_size != b_size) return 0;\n for (int i = 0; i < a_size; i++) {\n if (strcmp(a[i], b[i]) != 0) return 0;\n }\n return 1;\n}\n\nint main() {\n char **out;\n int out_size;\n\n int test1[] = {2, 1, 1, 4, 5, 8, 2, 3};\n char *expected1[] = {\"Eight\", \"Five\", \"Four\", \"Three\", \"Two\", \"Two\", \"One\", \"One\"};\n func0(test1, 8, &out, &out_size);\n assert(issame(out, out_size, expected1, 8));\n free(out);\n\n int test2[] = {};\n func0(test2, 0, &out, &out_size);\n assert(issame(out, out_size, NULL, 0));\n free(out);\n\n int test3[] = {1, -1, 55};\n char *expected3[] = {\"One\"};\n func0(test3, 3, &out, &out_size);\n assert(issame(out, out_size, expected3, 1));\n free(out);\n\n int test4[] = {1, -1, 3, 2};\n char *expected4[] = {\"Three\", \"Two\", \"One\"};\n func0(test4, 4, &out, &out_size);\n assert(issame(out, out_size, expected4, 3));\n free(out);\n\n int test5[] = {9, 4, 8};\n char *expected5[] = {\"Nine\", \"Eight\", \"Four\"};\n func0(test5, 3, &out, &out_size);\n assert(issame(out, out_size, expected5, 3));\n free(out);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 68h\nmov rbx, rdi\nmov r12, rdx\nmov rbp, rcx\nmov rax, fs:28h\nmov [rsp+88h+var_30], rax\nxor eax, eax\nlea rax, aThree+5; \"\"\nmov [rsp+88h+var_88], rax\nlea rax, unk_2004\nmov [rsp+88h+var_80], rax\nlea rax, unk_2008\nmov [rsp+88h+var_78], rax\nlea rax, aThree; \"Three\"\nmov [rsp+88h+var_70], rax\nlea rax, aFour; \"Four\"\nmov [rsp+88h+var_68], rax\nlea rax, aFive; \"Five\"\nmov [rsp+88h+var_60], rax\nlea rax, aSix; \"Six\"\nmov [rsp+88h+var_58], rax\nlea rax, aSeven; \"Seven\"\nmov [rsp+88h+var_50], rax\nlea rax, aEight; \"Eight\"\nmov [rsp+88h+var_48], rax\nlea rax, aNine; \"Nine\"\nmov [rsp+88h+var_40], rax\nlea r13d, [rsi-1]\ntest r13d, r13d\njle short loc_12B0\nlea r8, [rdi+4]\njmp short loc_129B\nloc_1276:\nadd rax, 4\ncmp rax, rdi\njz short loc_128F\nloc_127F:\nmov edx, [rax]\nmov ecx, [rax+4]\ncmp edx, ecx\njle short loc_1276\nmov [rax], ecx\nmov [rax+4], edx\njmp short loc_1276\nloc_128F:\nsub esi, 1\ncmp esi, 1\njz loc_134A\nloc_129B:\ncmp esi, 1\njle loc_1359\nmov rax, rbx\nlea edx, [rsi-2]\nlea rdi, [r8+rdx*4]\njmp short loc_127F\nloc_12B0:\nmov dword ptr [rcx], 0\njns loc_1351\nmov edi, 0; size\ncall _malloc\nmov [r12], rax\nloc_12CA:\nmov rax, [rsp+88h+var_30]\nsub rax, fs:28h\njnz loc_1361\nadd rsp, 68h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_12E9:\nsub rax, 1\ntest eax, eax\njs short loc_1302\nloc_12F1:\nmov esi, [rbx+rax*4]\nlea edx, [rsi-1]\ncmp edx, 8\nja short loc_12E9\nadd dword ptr [rbp+0], 1\njmp short loc_12E9\nloc_1302:\nmovsxd rdi, dword ptr [rbp+0]\nshl rdi, 3; size\ncall _malloc\nmov [r12], rax\nmov edx, 0\njmp short loc_1323\nloc_131A:\nsub r13, 1\ntest r13d, r13d\njs short loc_12CA\nloc_1323:\ncmp [rbp+0], edx\njle short loc_12CA\nmov eax, [rbx+r13*4]\nlea ecx, [rax-1]\ncmp ecx, 8\nja short loc_131A\nmovsxd rsi, edx\nmov rcx, [r12]\ncdqe\nmov rax, [rsp+rax*8+88h+var_88]\nmov [rcx+rsi*8], rax\nlea edx, [rdx+1]\njmp short loc_131A\nloc_134A:\nmov dword ptr [rbp+0], 0\nloc_1351:\nmovsxd r13, r13d\nmov rax, r13\njmp short loc_12F1\nloc_1359:\nsub esi, 1\njmp loc_129B\nloc_1361:\ncall ___stack_chk_fail", + "ida_pseudo": "unsigned __int64 __fastcall func0(int *a1, int a2, void **a3, int *a4)\n{\n __int64 v6; // r13\n int *v7; // rax\n int v8; // edx\n int v9; // ecx\n __int64 v11; // rax\n int v12; // edx\n int v13; // eax\n _QWORD v14[11]; // [rsp+0h] [rbp-88h]\n unsigned __int64 v15; // [rsp+58h] [rbp-30h]\n\n v15 = __readfsqword(0x28u);\n v14[0] = \"\";\n v14[1] = &unk_2004;\n v14[2] = &unk_2008;\n v14[3] = \"Three\";\n v14[4] = \"Four\";\n v14[5] = \"Five\";\n v14[6] = \"Six\";\n v14[7] = \"Seven\";\n v14[8] = \"Eight\";\n v14[9] = \"Nine\";\n LODWORD(v6) = a2 - 1;\n if ( a2 - 1 <= 0 )\n {\n *a4 = 0;\n if ( (int)v6 < 0 )\n {\n *a3 = malloc(0LL);\n return v15 - __readfsqword(0x28u);\n }\n }\n else\n {\n do\n {\n while ( a2 <= 1 )\n --a2;\n v7 = a1;\n do\n {\n v8 = *v7;\n v9 = v7[1];\n if ( *v7 > v9 )\n {\n *v7 = v9;\n v7[1] = v8;\n }\n ++v7;\n }\n while ( v7 != &a1[a2 - 2 + 1] );\n --a2;\n }\n while ( a2 != 1 );\n *a4 = 0;\n }\n v6 = (int)v6;\n v11 = (int)v6;\n do\n {\n if ( (unsigned int)(a1[v11] - 1) <= 8 )\n ++*a4;\n --v11;\n }\n while ( (int)v11 >= 0 );\n *a3 = malloc(8LL * *a4);\n v12 = 0;\n do\n {\n if ( *a4 <= v12 )\n break;\n v13 = a1[v6];\n if ( (unsigned int)(v13 - 1) <= 8 )\n *((_QWORD *)*a3 + v12++) = v14[v13];\n --v6;\n }\n while ( (int)v6 >= 0 );\n return v15 - __readfsqword(0x28u);\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 68h\nmov rbx, rdi\nmov r12, rdx\nmov rbp, rcx\nmov rax, fs:28h\nmov [rsp+88h+var_30], rax\nxor eax, eax\nlea rax, aThree+5; \"\"\nmov [rsp+88h+var_88], rax\nlea rax, unk_2004\nmov [rsp+88h+var_80], rax\nlea rax, unk_2008\nmov [rsp+88h+var_78], rax\nlea rax, aThree; \"Three\"\nmov [rsp+88h+var_70], rax\nlea rax, aFour; \"Four\"\nmov [rsp+88h+var_68], rax\nlea rax, aFive; \"Five\"\nmov [rsp+88h+var_60], rax\nlea rax, aSix; \"Six\"\nmov [rsp+88h+var_58], rax\nlea rax, aSeven; \"Seven\"\nmov [rsp+88h+var_50], rax\nlea rax, aEight; \"Eight\"\nmov [rsp+88h+var_48], rax\nlea rax, aNine; \"Nine\"\nmov [rsp+88h+var_40], rax\nlea r13d, [rsi-1]\ntest r13d, r13d\njle short loc_12B0\nlea r8, [rdi+4]\njmp short loc_129B\nloc_1276:\nadd rax, 4\ncmp rax, rdi\njz short loc_128F\nloc_127F:\nmov edx, [rax]\nmov ecx, [rax+4]\ncmp edx, ecx\njle short loc_1276\nmov [rax], ecx\nmov [rax+4], edx\njmp short loc_1276\nloc_128F:\nsub esi, 1\ncmp esi, 1\njz loc_134A\nloc_129B:\ncmp esi, 1\njle loc_1359\nmov rax, rbx\nlea edx, [rsi-2]\nlea rdi, [r8+rdx*4]\njmp short loc_127F\nloc_12B0:\nmov dword ptr [rcx], 0\njns loc_1351\nmov edi, 0; size\ncall _malloc\nmov [r12], rax\nloc_12CA:\nmov rax, [rsp+88h+var_30]\nsub rax, fs:28h\njnz loc_1361\nadd rsp, 68h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_12E9:\nsub rax, 1\ntest eax, eax\njs short loc_1302\nloc_12F1:\nmov esi, [rbx+rax*4]\nlea edx, [rsi-1]\ncmp edx, 8\nja short loc_12E9\nadd dword ptr [rbp+0], 1\njmp short loc_12E9\nloc_1302:\nmovsxd rdi, dword ptr [rbp+0]\nshl rdi, 3; size\ncall _malloc\nmov [r12], rax\nmov edx, 0\njmp short loc_1323\nloc_131A:\nsub r13, 1\ntest r13d, r13d\njs short loc_12CA\nloc_1323:\ncmp [rbp+0], edx\njle short loc_12CA\nmov eax, [rbx+r13*4]\nlea ecx, [rax-1]\ncmp ecx, 8\nja short loc_131A\nmovsxd rsi, edx\nmov rcx, [r12]\ncdqe\nmov rax, [rsp+rax*8+88h+var_88]\nmov [rcx+rsi*8], rax\nlea edx, [rdx+1]\njmp short loc_131A\nloc_134A:\nmov dword ptr [rbp+0], 0\nloc_1351:\nmovsxd r13, r13d\nmov rax, r13\njmp short loc_12F1\nloc_1359:\nsub esi, 1\njmp loc_129B\nloc_1361:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_11C9(int *a1, int a2, void **a3, int *a4)\n{\n __int64 v6; // r13\n int *v7; // rax\n int v8; // edx\n int v9; // ecx\n __int64 v11; // rax\n int v12; // edx\n int v13; // eax\n _QWORD v14[11]; // [rsp+0h] [rbp-88h]\n unsigned __int64 v15; // [rsp+58h] [rbp-30h]\n\n v15 = __readfsqword(0x28u);\n v14[0] = \"\";\n v14[1] = &unk_2004;\n v14[2] = &unk_2008;\n v14[3] = \"Three\";\n v14[4] = \"Four\";\n v14[5] = \"Five\";\n v14[6] = \"Six\";\n v14[7] = \"Seven\";\n v14[8] = \"Eight\";\n v14[9] = \"Nine\";\n LODWORD(v6) = a2 - 1;\n if ( a2 - 1 <= 0 )\n {\n *a4 = 0;\n if ( (int)v6 < 0 )\n {\n *a3 = malloc(0LL);\n return v15 - __readfsqword(0x28u);\n }\n }\n else\n {\n do\n {\n while ( a2 <= 1 )\n --a2;\n v7 = a1;\n do\n {\n v8 = *v7;\n v9 = v7[1];\n if ( *v7 > v9 )\n {\n *v7 = v9;\n v7[1] = v8;\n }\n ++v7;\n }\n while ( v7 != &a1[a2 - 2 + 1] );\n --a2;\n }\n while ( a2 != 1 );\n *a4 = 0;\n }\n v6 = (int)v6;\n v11 = (int)v6;\n do\n {\n if ( (unsigned int)(a1[v11] - 1) <= 8 )\n ++*a4;\n --v11;\n }\n while ( (int)v11 >= 0 );\n *a3 = malloc(8LL * *a4);\n v12 = 0;\n do\n {\n if ( *a4 <= v12 )\n break;\n v13 = a1[v6];\n if ( (unsigned int)(v13 - 1) <= 8 )\n *((_QWORD *)*a3 + v12++) = v14[v13];\n --v6;\n }\n while ( (int)v6 >= 0 );\n return v15 - __readfsqword(0x28u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_11C9(int *a1, int a2, void **a3, int *a4) {\n long long v6;\n int *v7;\n int v8;\n int v9;\n long long v11;\n int v12;\n int v13;\n uint64_t v14[11];\n unsigned long long v15;\n v15 = __readfsqword(40u);\n v14[0] = \"\";\n v14[1] = &unk_2004;\n v14[2] = &unk_2008;\n v14[3] = \"Three\";\n v14[4] = \"Four\";\n v14[5] = \"Five\";\n v14[6] = \"Six\";\n v14[7] = \"Seven\";\n v14[8] = \"Eight\";\n v14[9] = \"Nine\";\n LODWORD(v6) = a2 - 1;\n if (a2 - 1 <= 0) {\n *a4 = 0;\n if ((int)v6 < 0) {\n *a3 = malloc(0LL);\n return v15 - __readfsqword(40u);\n }\n } else {\n do {\n while (a2 <= 1) --a2;\n v7 = a1;\n do {\n v8 = *v7;\n v9 = v7[1];\n if (*v7 > v9) {\n *v7 = v9;\n v7[1] = v8;\n }\n ++v7;\n } while (v7 != &a1[a2 - 2 + 1]);\n --a2;\n } while (a2 != 1);\n *a4 = 0;\n }\n v6 = (int)v6;\n v11 = (int)v6;\n do {\n if ((unsigned int)(a1[v11] - 1) <= 8) ++*a4;\n --v11;\n } while ((int)v11 >= 0);\n *a3 = malloc(8LL * *a4);\n v12 = 0;\n do {\n if (*a4 <= v12) break;\n v13 = a1[v6];\n if ((unsigned int)(v13 - 1) <= 8) *((uint64_t *)*a3 + v12++) = v14[v13];\n --v6;\n } while ((int)v6 >= 0);\n return v15 - __readfsqword(40u);\n}", + "ida_pseudo_norm": "unsigned long long func0(int *a1, int a2, void **a3, int *a4) {\n long long v6;\n int *v7;\n int v8;\n int v9;\n long long v11;\n int v12;\n int v13;\n uint64_t v14[11];\n unsigned long long v15;\n v15 = __readfsqword(40u);\n v14[0] = \"\";\n v14[1] = &unk_2004;\n v14[2] = &unk_2008;\n v14[3] = \"Three\";\n v14[4] = \"Four\";\n v14[5] = \"Five\";\n v14[6] = \"Six\";\n v14[7] = \"Seven\";\n v14[8] = \"Eight\";\n v14[9] = \"Nine\";\n LODWORD(v6) = a2 - 1;\n if (a2 - 1 <= 0) {\n *a4 = 0;\n if ((int)v6 < 0) {\n *a3 = malloc(0LL);\n return v15 - __readfsqword(40u);\n }\n } else {\n do {\n while (a2 <= 1) --a2;\n v7 = a1;\n do {\n v8 = *v7;\n v9 = v7[1];\n if (*v7 > v9) {\n *v7 = v9;\n v7[1] = v8;\n }\n ++v7;\n } while (v7 != &a1[a2 - 2 + 1]);\n --a2;\n } while (a2 != 1);\n *a4 = 0;\n }\n v6 = (int)v6;\n v11 = (int)v6;\n do {\n if ((unsigned int)(a1[v11] - 1) <= 8) ++*a4;\n --v11;\n } while ((int)v11 >= 0);\n *a3 = malloc(8LL * *a4);\n v12 = 0;\n do {\n if (*a4 <= v12) break;\n v13 = a1[v6];\n if ((unsigned int)(v13 - 1) <= 8) *((uint64_t *)*a3 + v12++) = v14[v13];\n --v6;\n } while ((int)v6 >= 0);\n return v15 - __readfsqword(40u);\n}" + }, + { + "index": "HumanEval-C-105", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "void func0(int *arr, int size, char ***out, int *out_size) {\n char *names[] = {\"\", \"One\", \"Two\", \"Three\", \"Four\",\n \"Five\", \"Six\", \"Seven\", \"Eight\", \"Nine\"};\n int i, j;\n for (i = 0; i < size - 1; i++) {\n for (j = 0; j < size - i - 1; j++) {\n if (arr[j] > arr[j + 1]) {\n int temp = arr[j];\n arr[j] = arr[j + 1];\n arr[j + 1] = temp;\n }\n }\n }\n *out_size = 0;\n for (i = size - 1; i >= 0; i--) {\n if (arr[i] >= 1 && arr[i] <= 9) {\n (*out_size)++;\n }\n }\n *out = malloc(*out_size * sizeof(char *));\n for (i = size - 1, j = 0; i >= 0 && j < *out_size; i--) {\n if (arr[i] >= 1 && arr[i] <= 9) {\n (*out)[j++] = names[arr[i]];\n }\n }\n}", + "test": "#include \n#include \n#include \n#include \n\nint issame(char **a, int a_size, char **b, int b_size) {\n if (a_size != b_size) return 0;\n for (int i = 0; i < a_size; i++) {\n if (strcmp(a[i], b[i]) != 0) return 0;\n }\n return 1;\n}\n\nint main() {\n char **out;\n int out_size;\n\n int test1[] = {2, 1, 1, 4, 5, 8, 2, 3};\n char *expected1[] = {\"Eight\", \"Five\", \"Four\", \"Three\", \"Two\", \"Two\", \"One\", \"One\"};\n func0(test1, 8, &out, &out_size);\n assert(issame(out, out_size, expected1, 8));\n free(out);\n\n int test2[] = {};\n func0(test2, 0, &out, &out_size);\n assert(issame(out, out_size, NULL, 0));\n free(out);\n\n int test3[] = {1, -1, 55};\n char *expected3[] = {\"One\"};\n func0(test3, 3, &out, &out_size);\n assert(issame(out, out_size, expected3, 1));\n free(out);\n\n int test4[] = {1, -1, 3, 2};\n char *expected4[] = {\"Three\", \"Two\", \"One\"};\n func0(test4, 4, &out, &out_size);\n assert(issame(out, out_size, expected4, 3));\n free(out);\n\n int test5[] = {9, 4, 8};\n char *expected5[] = {\"Nine\", \"Eight\", \"Four\"};\n func0(test5, 3, &out, &out_size);\n assert(issame(out, out_size, expected5, 3));\n free(out);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r13\nmov r13, rcx\npush r12\nmov r12, rdx\npush rbp\nmov rbp, rdi\npush rbx\nlea rbx, aThree+5; \"\"\nmovq xmm0, rbx\nlea rbx, unk_2008\nsub rsp, 68h\nmov rax, fs:28h\nmov [rsp+88h+var_30], rax\nlea rax, unk_2004\nmovq xmm2, rax\nlea rax, aThree; \"Three\"\npunpcklqdq xmm0, xmm2\nmovq xmm3, rax\nlea rax, aFive; \"Five\"\nmovaps [rsp+88h+var_88], xmm0\nmovq xmm0, rbx\nlea rbx, aFour; \"Four\"\nmovq xmm4, rax\npunpcklqdq xmm0, xmm3\nlea rax, aSeven; \"Seven\"\nmovaps [rsp+88h+var_78], xmm0\nmovq xmm0, rbx\nmovq xmm5, rax\nlea rbx, aSix; \"Six\"\npunpcklqdq xmm0, xmm4\nlea rax, aNine; \"Nine\"\nmovaps [rsp+88h+var_68], xmm0\nmovq xmm0, rbx\nmovq xmm6, rax\nlea rbx, aEight; \"Eight\"\npunpcklqdq xmm0, xmm5\nmovaps [rsp+88h+var_58], xmm0\nmovq xmm0, rbx\nlea ebx, [rsi-1]\npunpcklqdq xmm0, xmm6\nmovaps [rsp+88h+var_48], xmm0\ntest ebx, ebx\njle loc_1780\nmov edi, esi\nlea r8, [rbp+4]\nnop word ptr [rax+rax+00h]\nloc_1690:\ncmp edi, 1\njle loc_1778\nlea edx, [rdi-2]\nmov rax, rbp\nlea rsi, [r8+rdx*4]\nnop dword ptr [rax+rax+00h]\nloc_16A8:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd ecx, xmm0\nmovd edx, xmm1\ncmp ecx, edx\njle short loc_16C6\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_16C6:\nadd rax, 4\ncmp rax, rsi\njnz short loc_16A8\nsub edi, 1\ncmp edi, 1\njnz short loc_1690\nmov dword ptr [r13+0], 0\nloc_16DF:\nmovsxd rbx, ebx\nxor ecx, ecx\nmov rax, rbx\nnop word ptr [rax+rax+00000000h]\nloc_16F0:\nmov edi, [rbp+rax*4+0]\nlea edx, [rdi-1]\ncmp edx, 8\nja short loc_1703\nadd ecx, 1\nmov [r13+0], ecx\nloc_1703:\nsub rax, 1\ntest eax, eax\njns short loc_16F0\nmovsxd rcx, ecx\nlea rdi, ds:0[rcx*8]; size\ncall _malloc\nmov edi, [r13+0]\nxor ecx, ecx\nmov [r12], rax\njmp short loc_1753\nloc_1730:\nmovsxd rdx, dword ptr [rbp+rbx*4+0]\nlea esi, [rdx-1]\ncmp esi, 8\nja short loc_174B\nmov rdx, qword ptr [rsp+rdx*8+88h+var_88]\nmovsxd rsi, ecx\nadd ecx, 1\nmov [rax+rsi*8], rdx\nloc_174B:\nsub rbx, 1\ntest ebx, ebx\njs short loc_1757\nloc_1753:\ncmp edi, ecx\njg short loc_1730\nloc_1757:\nmov rax, [rsp+88h+var_30]\nsub rax, fs:28h\njnz short loc_1799\nadd rsp, 68h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1778:\nsub edi, 1\njmp loc_1690\nloc_1780:\nmov dword ptr [rcx], 0\njz loc_16DF\nxor edi, edi; size\ncall _malloc\nmov [r12], rax\njmp short loc_1757\nloc_1799:\ncall ___stack_chk_fail", + "ida_pseudo": "unsigned __int64 __fastcall func0(__m128i *a1, int a2, void **a3, int *a4)\n{\n __int64 v7; // rbx\n int v8; // edi\n __m128i *v9; // rax\n __m128i v10; // xmm0\n int v11; // ecx\n __int64 v12; // rax\n _QWORD *v13; // rax\n int v14; // edi\n int v15; // ecx\n __int64 v16; // rdx\n __int64 v17; // rsi\n _OWORD v19[5]; // [rsp+0h] [rbp-88h]\n unsigned __int64 v20; // [rsp+58h] [rbp-30h]\n\n v20 = __readfsqword(0x28u);\n v19[0] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)\"\", (__m128i)(unsigned __int64)&unk_2004);\n v19[1] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_2008, (__m128i)(unsigned __int64)\"Three\");\n v19[2] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)\"Four\", (__m128i)(unsigned __int64)\"Five\");\n v19[3] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)\"Six\", (__m128i)(unsigned __int64)\"Seven\");\n LODWORD(v7) = a2 - 1;\n v19[4] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)\"Eight\", (__m128i)(unsigned __int64)\"Nine\");\n if ( a2 - 1 <= 0 )\n {\n *a4 = 0;\n if ( a2 != 1 )\n {\n *a3 = malloc(0LL);\n return v20 - __readfsqword(0x28u);\n }\n }\n else\n {\n v8 = a2;\n do\n {\n while ( v8 <= 1 )\n --v8;\n v9 = a1;\n do\n {\n v10 = _mm_loadl_epi64(v9);\n if ( _mm_cvtsi128_si32(v10) > _mm_cvtsi128_si32(_mm_shuffle_epi32(v10, 229)) )\n v9->m128i_i64[0] = _mm_shuffle_epi32(v10, 225).m128i_u64[0];\n v9 = (__m128i *)((char *)v9 + 4);\n }\n while ( v9 != (__m128i *)((char *)a1->m128i_i64 + 4 * (unsigned int)(v8 - 2) + 4) );\n --v8;\n }\n while ( v8 != 1 );\n *a4 = 0;\n }\n v7 = (int)v7;\n v11 = 0;\n v12 = (int)v7;\n do\n {\n if ( (unsigned int)(a1->m128i_i32[v12] - 1) <= 8 )\n *a4 = ++v11;\n --v12;\n }\n while ( (int)v12 >= 0 );\n v13 = malloc(8LL * v11);\n v14 = *a4;\n v15 = 0;\n *a3 = v13;\n do\n {\n if ( v14 <= v15 )\n break;\n v16 = a1->m128i_i32[v7];\n if ( (unsigned int)(v16 - 1) <= 8 )\n {\n v17 = v15++;\n v13[v17] = *((_QWORD *)v19 + v16);\n }\n --v7;\n }\n while ( (int)v7 >= 0 );\n return v20 - __readfsqword(0x28u);\n}", + "ida_strip_asm": "sub_15B0:\nendbr64\npush r13\nmov r13, rcx\npush r12\nmov r12, rdx\npush rbp\nmov rbp, rdi\npush rbx\nlea rbx, aThree+5; \"\"\nmovq xmm0, rbx\nlea rbx, unk_2008\nsub rsp, 68h\nmov rax, fs:28h\nmov [rsp+88h+var_30], rax\nlea rax, unk_2004\nmovq xmm2, rax\nlea rax, aThree; \"Three\"\npunpcklqdq xmm0, xmm2\nmovq xmm3, rax\nlea rax, aFive; \"Five\"\nmovaps [rsp+88h+var_88], xmm0\nmovq xmm0, rbx\nlea rbx, aFour; \"Four\"\nmovq xmm4, rax\npunpcklqdq xmm0, xmm3\nlea rax, aSeven; \"Seven\"\nmovaps [rsp+88h+var_78], xmm0\nmovq xmm0, rbx\nmovq xmm5, rax\nlea rbx, aSix; \"Six\"\npunpcklqdq xmm0, xmm4\nlea rax, aNine; \"Nine\"\nmovaps [rsp+88h+var_68], xmm0\nmovq xmm0, rbx\nmovq xmm6, rax\nlea rbx, aEight; \"Eight\"\npunpcklqdq xmm0, xmm5\nmovaps [rsp+88h+var_58], xmm0\nmovq xmm0, rbx\nlea ebx, [rsi-1]\npunpcklqdq xmm0, xmm6\nmovaps [rsp+88h+var_48], xmm0\ntest ebx, ebx\njle loc_1780\nmov edi, esi\nlea r8, [rbp+4]\nnop word ptr [rax+rax+00h]\nloc_1690:\ncmp edi, 1\njle loc_1778\nlea edx, [rdi-2]\nmov rax, rbp\nlea rsi, [r8+rdx*4]\nnop dword ptr [rax+rax+00h]\nloc_16A8:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd ecx, xmm0\nmovd edx, xmm1\ncmp ecx, edx\njle short loc_16C6\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_16C6:\nadd rax, 4\ncmp rax, rsi\njnz short loc_16A8\nsub edi, 1\ncmp edi, 1\njnz short loc_1690\nmov dword ptr [r13+0], 0\nloc_16DF:\nmovsxd rbx, ebx\nxor ecx, ecx\nmov rax, rbx\nnop word ptr [rax+rax+00000000h]\nloc_16F0:\nmov edi, [rbp+rax*4+0]\nlea edx, [rdi-1]\ncmp edx, 8\nja short loc_1703\nadd ecx, 1\nmov [r13+0], ecx\nloc_1703:\nsub rax, 1\ntest eax, eax\njns short loc_16F0\nmovsxd rcx, ecx\nlea rdi, ds:0[rcx*8]; size\ncall _malloc\nmov edi, [r13+0]\nxor ecx, ecx\nmov [r12], rax\njmp short loc_1753\nloc_1730:\nmovsxd rdx, dword ptr [rbp+rbx*4+0]\nlea esi, [rdx-1]\ncmp esi, 8\nja short loc_174B\nmov rdx, qword ptr [rsp+rdx*8+88h+var_88]\nmovsxd rsi, ecx\nadd ecx, 1\nmov [rax+rsi*8], rdx\nloc_174B:\nsub rbx, 1\ntest ebx, ebx\njs short loc_1757\nloc_1753:\ncmp edi, ecx\njg short loc_1730\nloc_1757:\nmov rax, [rsp+88h+var_30]\nsub rax, fs:28h\njnz short loc_1799\nadd rsp, 68h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1778:\nsub edi, 1\njmp loc_1690\nloc_1780:\nmov dword ptr [rcx], 0\njz loc_16DF\nxor edi, edi; size\ncall _malloc\nmov [r12], rax\njmp short loc_1757\nloc_1799:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_15B0(__m128i *a1, int a2, void **a3, int *a4)\n{\n __int64 v7; // rbx\n int v8; // edi\n __m128i *v9; // rax\n __m128i v10; // xmm0\n int v11; // ecx\n __int64 v12; // rax\n _QWORD *v13; // rax\n int v14; // edi\n int v15; // ecx\n __int64 v16; // rdx\n __int64 v17; // rsi\n _OWORD v19[5]; // [rsp+0h] [rbp-88h]\n unsigned __int64 v20; // [rsp+58h] [rbp-30h]\n\n v20 = __readfsqword(0x28u);\n v19[0] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)\"\", (__m128i)(unsigned __int64)&unk_2004);\n v19[1] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_2008, (__m128i)(unsigned __int64)\"Three\");\n v19[2] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)\"Four\", (__m128i)(unsigned __int64)\"Five\");\n v19[3] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)\"Six\", (__m128i)(unsigned __int64)\"Seven\");\n LODWORD(v7) = a2 - 1;\n v19[4] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)\"Eight\", (__m128i)(unsigned __int64)\"Nine\");\n if ( a2 - 1 <= 0 )\n {\n *a4 = 0;\n if ( a2 != 1 )\n {\n *a3 = malloc(0LL);\n return v20 - __readfsqword(0x28u);\n }\n }\n else\n {\n v8 = a2;\n do\n {\n while ( v8 <= 1 )\n --v8;\n v9 = a1;\n do\n {\n v10 = _mm_loadl_epi64(v9);\n if ( _mm_cvtsi128_si32(v10) > _mm_cvtsi128_si32(_mm_shuffle_epi32(v10, 229)) )\n v9->m128i_i64[0] = _mm_shuffle_epi32(v10, 225).m128i_u64[0];\n v9 = (__m128i *)((char *)v9 + 4);\n }\n while ( v9 != (__m128i *)((char *)a1->m128i_i64 + 4 * (unsigned int)(v8 - 2) + 4) );\n --v8;\n }\n while ( v8 != 1 );\n *a4 = 0;\n }\n v7 = (int)v7;\n v11 = 0;\n v12 = (int)v7;\n do\n {\n if ( (unsigned int)(a1->m128i_i32[v12] - 1) <= 8 )\n *a4 = ++v11;\n --v12;\n }\n while ( (int)v12 >= 0 );\n v13 = malloc(8LL * v11);\n v14 = *a4;\n v15 = 0;\n *a3 = v13;\n do\n {\n if ( v14 <= v15 )\n break;\n v16 = a1->m128i_i32[v7];\n if ( (unsigned int)(v16 - 1) <= 8 )\n {\n v17 = v15++;\n v13[v17] = *((_QWORD *)v19 + v16);\n }\n --v7;\n }\n while ( (int)v7 >= 0 );\n return v20 - __readfsqword(0x28u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_15B0(__m128i *a1, int a2, void **a3, int *a4) {\n long long v7;\n int v8;\n __m128i *v9;\n __m128i v10;\n int v11;\n long long v12;\n uint64_t *v13;\n int v14;\n int v15;\n long long v16;\n long long v17;\n long double v19[5];\n unsigned long long v20;\n v20 = __readfsqword(40u);\n v19[0] = _mm_unpacklo_epi64((__m128i)(unsigned long long)\"\",\n (__m128i)(unsigned long long)&unk_2004);\n v19[1] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_2008,\n (__m128i)(unsigned long long)\"Three\");\n v19[2] = _mm_unpacklo_epi64((__m128i)(unsigned long long)\"Four\",\n (__m128i)(unsigned long long)\"Five\");\n v19[3] = _mm_unpacklo_epi64((__m128i)(unsigned long long)\"Six\",\n (__m128i)(unsigned long long)\"Seven\");\n LODWORD(v7) = a2 - 1;\n v19[4] = _mm_unpacklo_epi64((__m128i)(unsigned long long)\"Eight\",\n (__m128i)(unsigned long long)\"Nine\");\n if (a2 - 1 <= 0) {\n *a4 = 0;\n if (a2 != 1) {\n *a3 = malloc(0LL);\n return v20 - __readfsqword(40u);\n }\n } else {\n v8 = a2;\n do {\n while (v8 <= 1) --v8;\n v9 = a1;\n do {\n v10 = _mm_loadl_epi64(v9);\n if (_mm_cvtsi128_si32(v10) >\n _mm_cvtsi128_si32(_mm_shuffle_epi32(v10, 229)))\n v9->m128i_i64[0] = _mm_shuffle_epi32(v10, 225).m128i_u64[0];\n v9 = (__m128i *)((char *)v9 + 4);\n } while (v9 != (__m128i *)((char *)a1->m128i_i64 +\n 4 * (unsigned int)(v8 - 2) + 4));\n --v8;\n } while (v8 != 1);\n *a4 = 0;\n }\n v7 = (int)v7;\n v11 = 0;\n v12 = (int)v7;\n do {\n if ((unsigned int)(a1->m128i_i32[v12] - 1) <= 8) *a4 = ++v11;\n --v12;\n } while ((int)v12 >= 0);\n v13 = malloc(8LL * v11);\n v14 = *a4;\n v15 = 0;\n *a3 = v13;\n do {\n if (v14 <= v15) break;\n v16 = a1->m128i_i32[v7];\n if ((unsigned int)(v16 - 1) <= 8) {\n v17 = v15++;\n v13[v17] = *((uint64_t *)v19 + v16);\n }\n --v7;\n } while ((int)v7 >= 0);\n return v20 - __readfsqword(40u);\n}", + "ida_pseudo_norm": "unsigned long long func0(__m128i *a1, int a2, void **a3, int *a4) {\n long long v7;\n int v8;\n __m128i *v9;\n __m128i v10;\n int v11;\n long long v12;\n uint64_t *v13;\n int v14;\n int v15;\n long long v16;\n long long v17;\n long double v19[5];\n unsigned long long v20;\n v20 = __readfsqword(40u);\n v19[0] = _mm_unpacklo_epi64((__m128i)(unsigned long long)\"\",\n (__m128i)(unsigned long long)&unk_2004);\n v19[1] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_2008,\n (__m128i)(unsigned long long)\"Three\");\n v19[2] = _mm_unpacklo_epi64((__m128i)(unsigned long long)\"Four\",\n (__m128i)(unsigned long long)\"Five\");\n v19[3] = _mm_unpacklo_epi64((__m128i)(unsigned long long)\"Six\",\n (__m128i)(unsigned long long)\"Seven\");\n LODWORD(v7) = a2 - 1;\n v19[4] = _mm_unpacklo_epi64((__m128i)(unsigned long long)\"Eight\",\n (__m128i)(unsigned long long)\"Nine\");\n if (a2 - 1 <= 0) {\n *a4 = 0;\n if (a2 != 1) {\n *a3 = malloc(0LL);\n return v20 - __readfsqword(40u);\n }\n } else {\n v8 = a2;\n do {\n while (v8 <= 1) --v8;\n v9 = a1;\n do {\n v10 = _mm_loadl_epi64(v9);\n if (_mm_cvtsi128_si32(v10) >\n _mm_cvtsi128_si32(_mm_shuffle_epi32(v10, 229)))\n v9->m128i_i64[0] = _mm_shuffle_epi32(v10, 225).m128i_u64[0];\n v9 = (__m128i *)((char *)v9 + 4);\n } while (v9 != (__m128i *)((char *)a1->m128i_i64 +\n 4 * (unsigned int)(v8 - 2) + 4));\n --v8;\n } while (v8 != 1);\n *a4 = 0;\n }\n v7 = (int)v7;\n v11 = 0;\n v12 = (int)v7;\n do {\n if ((unsigned int)(a1->m128i_i32[v12] - 1) <= 8) *a4 = ++v11;\n --v12;\n } while ((int)v12 >= 0);\n v13 = malloc(8LL * v11);\n v14 = *a4;\n v15 = 0;\n *a3 = v13;\n do {\n if (v14 <= v15) break;\n v16 = a1->m128i_i32[v7];\n if ((unsigned int)(v16 - 1) <= 8) {\n v17 = v15++;\n v13[v17] = *((uint64_t *)v19 + v16);\n }\n --v7;\n } while ((int)v7 >= 0);\n return v20 - __readfsqword(40u);\n}" + }, + { + "index": "HumanEval-C-105", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "void func0(int *arr, int size, char ***out, int *out_size) {\n char *names[] = {\"\", \"One\", \"Two\", \"Three\", \"Four\",\n \"Five\", \"Six\", \"Seven\", \"Eight\", \"Nine\"};\n int i, j;\n for (i = 0; i < size - 1; i++) {\n for (j = 0; j < size - i - 1; j++) {\n if (arr[j] > arr[j + 1]) {\n int temp = arr[j];\n arr[j] = arr[j + 1];\n arr[j + 1] = temp;\n }\n }\n }\n *out_size = 0;\n for (i = size - 1; i >= 0; i--) {\n if (arr[i] >= 1 && arr[i] <= 9) {\n (*out_size)++;\n }\n }\n *out = malloc(*out_size * sizeof(char *));\n for (i = size - 1, j = 0; i >= 0 && j < *out_size; i--) {\n if (arr[i] >= 1 && arr[i] <= 9) {\n (*out)[j++] = names[arr[i]];\n }\n }\n}", + "test": "#include \n#include \n#include \n#include \n\nint issame(char **a, int a_size, char **b, int b_size) {\n if (a_size != b_size) return 0;\n for (int i = 0; i < a_size; i++) {\n if (strcmp(a[i], b[i]) != 0) return 0;\n }\n return 1;\n}\n\nint main() {\n char **out;\n int out_size;\n\n int test1[] = {2, 1, 1, 4, 5, 8, 2, 3};\n char *expected1[] = {\"Eight\", \"Five\", \"Four\", \"Three\", \"Two\", \"Two\", \"One\", \"One\"};\n func0(test1, 8, &out, &out_size);\n assert(issame(out, out_size, expected1, 8));\n free(out);\n\n int test2[] = {};\n func0(test2, 0, &out, &out_size);\n assert(issame(out, out_size, NULL, 0));\n free(out);\n\n int test3[] = {1, -1, 55};\n char *expected3[] = {\"One\"};\n func0(test3, 3, &out, &out_size);\n assert(issame(out, out_size, expected3, 1));\n free(out);\n\n int test4[] = {1, -1, 3, 2};\n char *expected4[] = {\"Three\", \"Two\", \"One\"};\n func0(test4, 4, &out, &out_size);\n assert(issame(out, out_size, expected4, 3));\n free(out);\n\n int test5[] = {9, 4, 8};\n char *expected5[] = {\"Nine\", \"Eight\", \"Four\"};\n func0(test5, 3, &out, &out_size);\n assert(issame(out, out_size, expected5, 3));\n free(out);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r13\nmov r13, rcx\npush r12\nmov r12, rdx\npush rbp\nmov rbp, rdi\npush rbx\nlea rbx, aThree+5; \"\"\nmovq xmm0, rbx\nlea rbx, unk_2008\nsub rsp, 68h\nmov rax, fs:28h\nmov [rsp+88h+var_30], rax\nlea rax, unk_2004\nmovq xmm2, rax\nlea rax, aThree; \"Three\"\npunpcklqdq xmm0, xmm2\nmovq xmm3, rax\nlea rax, aFive; \"Five\"\nmovaps [rsp+88h+var_88], xmm0\nmovq xmm0, rbx\nlea rbx, aFour; \"Four\"\nmovq xmm4, rax\npunpcklqdq xmm0, xmm3\nlea rax, aSeven; \"Seven\"\nmovaps [rsp+88h+var_78], xmm0\nmovq xmm0, rbx\nmovq xmm5, rax\nlea rbx, aSix; \"Six\"\npunpcklqdq xmm0, xmm4\nlea rax, aNine; \"Nine\"\nmovaps [rsp+88h+var_68], xmm0\nmovq xmm0, rbx\nmovq xmm6, rax\nlea rbx, aEight; \"Eight\"\npunpcklqdq xmm0, xmm5\nmovaps [rsp+88h+var_58], xmm0\nmovq xmm0, rbx\nlea ebx, [rsi-1]\npunpcklqdq xmm0, xmm6\nmovaps [rsp+88h+var_48], xmm0\ntest ebx, ebx\njle loc_1780\nmov edi, esi\nlea r8, [rbp+4]\nnop word ptr [rax+rax+00h]\nloc_1690:\ncmp edi, 1\njle loc_1778\nlea edx, [rdi-2]\nmov rax, rbp\nlea rsi, [r8+rdx*4]\nnop dword ptr [rax+rax+00h]\nloc_16A8:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd ecx, xmm0\nmovd edx, xmm1\ncmp ecx, edx\njle short loc_16C6\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_16C6:\nadd rax, 4\ncmp rax, rsi\njnz short loc_16A8\nsub edi, 1\ncmp edi, 1\njnz short loc_1690\nmov dword ptr [r13+0], 0\nloc_16DF:\nmovsxd rbx, ebx\nxor ecx, ecx\nmov rax, rbx\nnop word ptr [rax+rax+00000000h]\nloc_16F0:\nmov edi, [rbp+rax*4+0]\nlea edx, [rdi-1]\ncmp edx, 8\nja short loc_1703\nadd ecx, 1\nmov [r13+0], ecx\nloc_1703:\nsub rax, 1\ntest eax, eax\njns short loc_16F0\nmovsxd rcx, ecx\nlea rdi, ds:0[rcx*8]; size\ncall _malloc\nmov edi, [r13+0]\nxor ecx, ecx\nmov [r12], rax\njmp short loc_1753\nloc_1730:\nmovsxd rdx, dword ptr [rbp+rbx*4+0]\nlea esi, [rdx-1]\ncmp esi, 8\nja short loc_174B\nmov rdx, qword ptr [rsp+rdx*8+88h+var_88]\nmovsxd rsi, ecx\nadd ecx, 1\nmov [rax+rsi*8], rdx\nloc_174B:\nsub rbx, 1\ntest ebx, ebx\njs short loc_1757\nloc_1753:\ncmp edi, ecx\njg short loc_1730\nloc_1757:\nmov rax, [rsp+88h+var_30]\nsub rax, fs:28h\njnz short loc_1799\nadd rsp, 68h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1778:\nsub edi, 1\njmp loc_1690\nloc_1780:\nmov dword ptr [rcx], 0\njz loc_16DF\nxor edi, edi; size\ncall _malloc\nmov [r12], rax\njmp short loc_1757\nloc_1799:\ncall ___stack_chk_fail", + "ida_pseudo": "unsigned __int64 __fastcall func0(__m128i *a1, int a2, void **a3, int *a4)\n{\n __int64 v7; // rbx\n int v8; // edi\n __m128i *v9; // rax\n __m128i v10; // xmm0\n int v11; // ecx\n __int64 v12; // rax\n _QWORD *v13; // rax\n int v14; // edi\n int v15; // ecx\n __int64 v16; // rdx\n __int64 v17; // rsi\n _OWORD v19[5]; // [rsp+0h] [rbp-88h]\n unsigned __int64 v20; // [rsp+58h] [rbp-30h]\n\n v20 = __readfsqword(0x28u);\n v19[0] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)\"\", (__m128i)(unsigned __int64)&unk_2004);\n v19[1] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_2008, (__m128i)(unsigned __int64)\"Three\");\n v19[2] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)\"Four\", (__m128i)(unsigned __int64)\"Five\");\n v19[3] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)\"Six\", (__m128i)(unsigned __int64)\"Seven\");\n LODWORD(v7) = a2 - 1;\n v19[4] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)\"Eight\", (__m128i)(unsigned __int64)\"Nine\");\n if ( a2 - 1 <= 0 )\n {\n *a4 = 0;\n if ( a2 != 1 )\n {\n *a3 = malloc(0LL);\n return v20 - __readfsqword(0x28u);\n }\n }\n else\n {\n v8 = a2;\n do\n {\n while ( v8 <= 1 )\n --v8;\n v9 = a1;\n do\n {\n v10 = _mm_loadl_epi64(v9);\n if ( _mm_cvtsi128_si32(v10) > _mm_cvtsi128_si32(_mm_shuffle_epi32(v10, 229)) )\n v9->m128i_i64[0] = _mm_shuffle_epi32(v10, 225).m128i_u64[0];\n v9 = (__m128i *)((char *)v9 + 4);\n }\n while ( v9 != (__m128i *)((char *)a1->m128i_i64 + 4 * (unsigned int)(v8 - 2) + 4) );\n --v8;\n }\n while ( v8 != 1 );\n *a4 = 0;\n }\n v7 = (int)v7;\n v11 = 0;\n v12 = (int)v7;\n do\n {\n if ( (unsigned int)(a1->m128i_i32[v12] - 1) <= 8 )\n *a4 = ++v11;\n --v12;\n }\n while ( (int)v12 >= 0 );\n v13 = malloc(8LL * v11);\n v14 = *a4;\n v15 = 0;\n *a3 = v13;\n do\n {\n if ( v14 <= v15 )\n break;\n v16 = a1->m128i_i32[v7];\n if ( (unsigned int)(v16 - 1) <= 8 )\n {\n v17 = v15++;\n v13[v17] = *((_QWORD *)v19 + v16);\n }\n --v7;\n }\n while ( (int)v7 >= 0 );\n return v20 - __readfsqword(0x28u);\n}", + "ida_strip_asm": "sub_15B0:\nendbr64\npush r13\nmov r13, rcx\npush r12\nmov r12, rdx\npush rbp\nmov rbp, rdi\npush rbx\nlea rbx, aThree+5; \"\"\nmovq xmm0, rbx\nlea rbx, unk_2008\nsub rsp, 68h\nmov rax, fs:28h\nmov [rsp+88h+var_30], rax\nlea rax, unk_2004\nmovq xmm2, rax\nlea rax, aThree; \"Three\"\npunpcklqdq xmm0, xmm2\nmovq xmm3, rax\nlea rax, aFive; \"Five\"\nmovaps [rsp+88h+var_88], xmm0\nmovq xmm0, rbx\nlea rbx, aFour; \"Four\"\nmovq xmm4, rax\npunpcklqdq xmm0, xmm3\nlea rax, aSeven; \"Seven\"\nmovaps [rsp+88h+var_78], xmm0\nmovq xmm0, rbx\nmovq xmm5, rax\nlea rbx, aSix; \"Six\"\npunpcklqdq xmm0, xmm4\nlea rax, aNine; \"Nine\"\nmovaps [rsp+88h+var_68], xmm0\nmovq xmm0, rbx\nmovq xmm6, rax\nlea rbx, aEight; \"Eight\"\npunpcklqdq xmm0, xmm5\nmovaps [rsp+88h+var_58], xmm0\nmovq xmm0, rbx\nlea ebx, [rsi-1]\npunpcklqdq xmm0, xmm6\nmovaps [rsp+88h+var_48], xmm0\ntest ebx, ebx\njle loc_1780\nmov edi, esi\nlea r8, [rbp+4]\nnop word ptr [rax+rax+00h]\nloc_1690:\ncmp edi, 1\njle loc_1778\nlea edx, [rdi-2]\nmov rax, rbp\nlea rsi, [r8+rdx*4]\nnop dword ptr [rax+rax+00h]\nloc_16A8:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd ecx, xmm0\nmovd edx, xmm1\ncmp ecx, edx\njle short loc_16C6\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_16C6:\nadd rax, 4\ncmp rax, rsi\njnz short loc_16A8\nsub edi, 1\ncmp edi, 1\njnz short loc_1690\nmov dword ptr [r13+0], 0\nloc_16DF:\nmovsxd rbx, ebx\nxor ecx, ecx\nmov rax, rbx\nnop word ptr [rax+rax+00000000h]\nloc_16F0:\nmov edi, [rbp+rax*4+0]\nlea edx, [rdi-1]\ncmp edx, 8\nja short loc_1703\nadd ecx, 1\nmov [r13+0], ecx\nloc_1703:\nsub rax, 1\ntest eax, eax\njns short loc_16F0\nmovsxd rcx, ecx\nlea rdi, ds:0[rcx*8]; size\ncall _malloc\nmov edi, [r13+0]\nxor ecx, ecx\nmov [r12], rax\njmp short loc_1753\nloc_1730:\nmovsxd rdx, dword ptr [rbp+rbx*4+0]\nlea esi, [rdx-1]\ncmp esi, 8\nja short loc_174B\nmov rdx, qword ptr [rsp+rdx*8+88h+var_88]\nmovsxd rsi, ecx\nadd ecx, 1\nmov [rax+rsi*8], rdx\nloc_174B:\nsub rbx, 1\ntest ebx, ebx\njs short loc_1757\nloc_1753:\ncmp edi, ecx\njg short loc_1730\nloc_1757:\nmov rax, [rsp+88h+var_30]\nsub rax, fs:28h\njnz short loc_1799\nadd rsp, 68h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1778:\nsub edi, 1\njmp loc_1690\nloc_1780:\nmov dword ptr [rcx], 0\njz loc_16DF\nxor edi, edi; size\ncall _malloc\nmov [r12], rax\njmp short loc_1757\nloc_1799:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_15B0(__m128i *a1, int a2, void **a3, int *a4)\n{\n __int64 v7; // rbx\n int v8; // edi\n __m128i *v9; // rax\n __m128i v10; // xmm0\n int v11; // ecx\n __int64 v12; // rax\n _QWORD *v13; // rax\n int v14; // edi\n int v15; // ecx\n __int64 v16; // rdx\n __int64 v17; // rsi\n _OWORD v19[5]; // [rsp+0h] [rbp-88h]\n unsigned __int64 v20; // [rsp+58h] [rbp-30h]\n\n v20 = __readfsqword(0x28u);\n v19[0] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)\"\", (__m128i)(unsigned __int64)&unk_2004);\n v19[1] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_2008, (__m128i)(unsigned __int64)\"Three\");\n v19[2] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)\"Four\", (__m128i)(unsigned __int64)\"Five\");\n v19[3] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)\"Six\", (__m128i)(unsigned __int64)\"Seven\");\n LODWORD(v7) = a2 - 1;\n v19[4] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)\"Eight\", (__m128i)(unsigned __int64)\"Nine\");\n if ( a2 - 1 <= 0 )\n {\n *a4 = 0;\n if ( a2 != 1 )\n {\n *a3 = malloc(0LL);\n return v20 - __readfsqword(0x28u);\n }\n }\n else\n {\n v8 = a2;\n do\n {\n while ( v8 <= 1 )\n --v8;\n v9 = a1;\n do\n {\n v10 = _mm_loadl_epi64(v9);\n if ( _mm_cvtsi128_si32(v10) > _mm_cvtsi128_si32(_mm_shuffle_epi32(v10, 229)) )\n v9->m128i_i64[0] = _mm_shuffle_epi32(v10, 225).m128i_u64[0];\n v9 = (__m128i *)((char *)v9 + 4);\n }\n while ( v9 != (__m128i *)((char *)a1->m128i_i64 + 4 * (unsigned int)(v8 - 2) + 4) );\n --v8;\n }\n while ( v8 != 1 );\n *a4 = 0;\n }\n v7 = (int)v7;\n v11 = 0;\n v12 = (int)v7;\n do\n {\n if ( (unsigned int)(a1->m128i_i32[v12] - 1) <= 8 )\n *a4 = ++v11;\n --v12;\n }\n while ( (int)v12 >= 0 );\n v13 = malloc(8LL * v11);\n v14 = *a4;\n v15 = 0;\n *a3 = v13;\n do\n {\n if ( v14 <= v15 )\n break;\n v16 = a1->m128i_i32[v7];\n if ( (unsigned int)(v16 - 1) <= 8 )\n {\n v17 = v15++;\n v13[v17] = *((_QWORD *)v19 + v16);\n }\n --v7;\n }\n while ( (int)v7 >= 0 );\n return v20 - __readfsqword(0x28u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_15B0(__m128i *a1, int a2, void **a3, int *a4) {\n long long v7;\n int v8;\n __m128i *v9;\n __m128i v10;\n int v11;\n long long v12;\n uint64_t *v13;\n int v14;\n int v15;\n long long v16;\n long long v17;\n long double v19[5];\n unsigned long long v20;\n v20 = __readfsqword(40u);\n v19[0] = _mm_unpacklo_epi64((__m128i)(unsigned long long)\"\",\n (__m128i)(unsigned long long)&unk_2004);\n v19[1] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_2008,\n (__m128i)(unsigned long long)\"Three\");\n v19[2] = _mm_unpacklo_epi64((__m128i)(unsigned long long)\"Four\",\n (__m128i)(unsigned long long)\"Five\");\n v19[3] = _mm_unpacklo_epi64((__m128i)(unsigned long long)\"Six\",\n (__m128i)(unsigned long long)\"Seven\");\n LODWORD(v7) = a2 - 1;\n v19[4] = _mm_unpacklo_epi64((__m128i)(unsigned long long)\"Eight\",\n (__m128i)(unsigned long long)\"Nine\");\n if (a2 - 1 <= 0) {\n *a4 = 0;\n if (a2 != 1) {\n *a3 = malloc(0LL);\n return v20 - __readfsqword(40u);\n }\n } else {\n v8 = a2;\n do {\n while (v8 <= 1) --v8;\n v9 = a1;\n do {\n v10 = _mm_loadl_epi64(v9);\n if (_mm_cvtsi128_si32(v10) >\n _mm_cvtsi128_si32(_mm_shuffle_epi32(v10, 229)))\n v9->m128i_i64[0] = _mm_shuffle_epi32(v10, 225).m128i_u64[0];\n v9 = (__m128i *)((char *)v9 + 4);\n } while (v9 != (__m128i *)((char *)a1->m128i_i64 +\n 4 * (unsigned int)(v8 - 2) + 4));\n --v8;\n } while (v8 != 1);\n *a4 = 0;\n }\n v7 = (int)v7;\n v11 = 0;\n v12 = (int)v7;\n do {\n if ((unsigned int)(a1->m128i_i32[v12] - 1) <= 8) *a4 = ++v11;\n --v12;\n } while ((int)v12 >= 0);\n v13 = malloc(8LL * v11);\n v14 = *a4;\n v15 = 0;\n *a3 = v13;\n do {\n if (v14 <= v15) break;\n v16 = a1->m128i_i32[v7];\n if ((unsigned int)(v16 - 1) <= 8) {\n v17 = v15++;\n v13[v17] = *((uint64_t *)v19 + v16);\n }\n --v7;\n } while ((int)v7 >= 0);\n return v20 - __readfsqword(40u);\n}", + "ida_pseudo_norm": "unsigned long long func0(__m128i *a1, int a2, void **a3, int *a4) {\n long long v7;\n int v8;\n __m128i *v9;\n __m128i v10;\n int v11;\n long long v12;\n uint64_t *v13;\n int v14;\n int v15;\n long long v16;\n long long v17;\n long double v19[5];\n unsigned long long v20;\n v20 = __readfsqword(40u);\n v19[0] = _mm_unpacklo_epi64((__m128i)(unsigned long long)\"\",\n (__m128i)(unsigned long long)&unk_2004);\n v19[1] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_2008,\n (__m128i)(unsigned long long)\"Three\");\n v19[2] = _mm_unpacklo_epi64((__m128i)(unsigned long long)\"Four\",\n (__m128i)(unsigned long long)\"Five\");\n v19[3] = _mm_unpacklo_epi64((__m128i)(unsigned long long)\"Six\",\n (__m128i)(unsigned long long)\"Seven\");\n LODWORD(v7) = a2 - 1;\n v19[4] = _mm_unpacklo_epi64((__m128i)(unsigned long long)\"Eight\",\n (__m128i)(unsigned long long)\"Nine\");\n if (a2 - 1 <= 0) {\n *a4 = 0;\n if (a2 != 1) {\n *a3 = malloc(0LL);\n return v20 - __readfsqword(40u);\n }\n } else {\n v8 = a2;\n do {\n while (v8 <= 1) --v8;\n v9 = a1;\n do {\n v10 = _mm_loadl_epi64(v9);\n if (_mm_cvtsi128_si32(v10) >\n _mm_cvtsi128_si32(_mm_shuffle_epi32(v10, 229)))\n v9->m128i_i64[0] = _mm_shuffle_epi32(v10, 225).m128i_u64[0];\n v9 = (__m128i *)((char *)v9 + 4);\n } while (v9 != (__m128i *)((char *)a1->m128i_i64 +\n 4 * (unsigned int)(v8 - 2) + 4));\n --v8;\n } while (v8 != 1);\n *a4 = 0;\n }\n v7 = (int)v7;\n v11 = 0;\n v12 = (int)v7;\n do {\n if ((unsigned int)(a1->m128i_i32[v12] - 1) <= 8) *a4 = ++v11;\n --v12;\n } while ((int)v12 >= 0);\n v13 = malloc(8LL * v11);\n v14 = *a4;\n v15 = 0;\n *a3 = v13;\n do {\n if (v14 <= v15) break;\n v16 = a1->m128i_i32[v7];\n if ((unsigned int)(v16 - 1) <= 8) {\n v17 = v15++;\n v13[v17] = *((uint64_t *)v19 + v16);\n }\n --v7;\n } while ((int)v7 >= 0);\n return v20 - __readfsqword(40u);\n}" + }, + { + "index": "HumanEval-C-106", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int* func0(int n) {\n int* out = (int*)malloc(n * sizeof(int));\n int sum = 0, prod = 1;\n for (int i = 1; i <= n; i++) {\n sum += i;\n prod *= i;\n if (i % 2 == 0)\n out[i - 1] = prod;\n else\n out[i - 1] = sum;\n }\n return out;\n}", + "test": "#include \n#include \n#include \n\nint issame(int* a, int a_size, int* b, int b_size) {\n if (a_size != b_size) return 0;\n for (int i = 0; i < a_size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int *result;\n int expected1[] = {1, 2, 6, 24, 15};\n result = func0(5);\n assert(issame(result, 5, expected1, 5));\n free(result);\n\n int expected2[] = {1, 2, 6, 24, 15, 720, 28};\n result = func0(7);\n assert(issame(result, 7, expected2, 7));\n free(result);\n\n int expected3[] = {1};\n result = func0(1);\n assert(issame(result, 1, expected3, 1));\n free(result);\n\n int expected4[] = {1, 2, 6};\n result = func0(3);\n assert(issame(result, 3, expected4, 3));\n free(result);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_24], edi\nmov eax, [rbp+var_24]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_14], 0\nmov [rbp+var_10], 1\nmov [rbp+var_C], 1\njmp short loc_1236\nloc_11E4:\nmov eax, [rbp+var_C]\nadd [rbp+var_14], eax\nmov eax, [rbp+var_10]\nimul eax, [rbp+var_C]\nmov [rbp+var_10], eax\nmov eax, [rbp+var_C]\nand eax, 1\ntest eax, eax\njnz short loc_1219\nmov eax, [rbp+var_C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_10]\nmov [rdx], eax\njmp short loc_1232\nloc_1219:\nmov eax, [rbp+var_C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_14]\nmov [rdx], eax\nloc_1232:\nadd [rbp+var_C], 1\nloc_1236:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_24]\njle short loc_11E4\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int a1)\n{\n int v2; // [rsp+1Ch] [rbp-14h]\n int v3; // [rsp+20h] [rbp-10h]\n int i; // [rsp+24h] [rbp-Ch]\n _DWORD *v5; // [rsp+28h] [rbp-8h]\n\n v5 = malloc(4LL * a1);\n v2 = 0;\n v3 = 1;\n for ( i = 1; i <= a1; ++i )\n {\n v2 += i;\n v3 *= i;\n if ( (i & 1) != 0 )\n v5[i - 1] = v2;\n else\n v5[i - 1] = v3;\n }\n return v5;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_24], edi\nmov eax, [rbp+var_24]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_14], 0\nmov [rbp+var_10], 1\nmov [rbp+var_C], 1\njmp short loc_1236\nloc_11E4:\nmov eax, [rbp+var_C]\nadd [rbp+var_14], eax\nmov eax, [rbp+var_10]\nimul eax, [rbp+var_C]\nmov [rbp+var_10], eax\nmov eax, [rbp+var_C]\nand eax, 1\ntest eax, eax\njnz short loc_1219\nmov eax, [rbp+var_C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_10]\nmov [rdx], eax\njmp short loc_1232\nloc_1219:\nmov eax, [rbp+var_C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_14]\nmov [rdx], eax\nloc_1232:\nadd [rbp+var_C], 1\nloc_1236:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_24]\njle short loc_11E4\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(int a1)\n{\n int v2; // [rsp+1Ch] [rbp-14h]\n int v3; // [rsp+20h] [rbp-10h]\n int i; // [rsp+24h] [rbp-Ch]\n _DWORD *v5; // [rsp+28h] [rbp-8h]\n\n v5 = malloc(4LL * a1);\n v2 = 0;\n v3 = 1;\n for ( i = 1; i <= a1; ++i )\n {\n v2 += i;\n v3 *= i;\n if ( (i & 1) != 0 )\n v5[i - 1] = v2;\n else\n v5[i - 1] = v3;\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(int a1) {\n int v2;\n int v3;\n int i;\n uint32_t *v5;\n v5 = malloc(4LL * a1);\n v2 = 0;\n v3 = 1;\n for (i = 1; i <= a1; ++i) {\n v2 += i;\n v3 *= i;\n if ((i & 1) != 0)\n v5[i - 1] = v2;\n else\n v5[i - 1] = v3;\n }\n return v5;\n}", + "ida_pseudo_norm": "uint32_t *func0(int a1) {\n int v2;\n int v3;\n int i;\n uint32_t *v5;\n v5 = malloc(4LL * a1);\n v2 = 0;\n v3 = 1;\n for (i = 1; i <= a1; ++i) {\n v2 += i;\n v3 *= i;\n if ((i & 1) != 0)\n v5[i - 1] = v2;\n else\n v5[i - 1] = v3;\n }\n return v5;\n}" + }, + { + "index": "HumanEval-C-106", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int* func0(int n) {\n int* out = (int*)malloc(n * sizeof(int));\n int sum = 0, prod = 1;\n for (int i = 1; i <= n; i++) {\n sum += i;\n prod *= i;\n if (i % 2 == 0)\n out[i - 1] = prod;\n else\n out[i - 1] = sum;\n }\n return out;\n}", + "test": "#include \n#include \n#include \n\nint issame(int* a, int a_size, int* b, int b_size) {\n if (a_size != b_size) return 0;\n for (int i = 0; i < a_size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int *result;\n int expected1[] = {1, 2, 6, 24, 15};\n result = func0(5);\n assert(issame(result, 5, expected1, 5));\n free(result);\n\n int expected2[] = {1, 2, 6, 24, 15, 720, 28};\n result = func0(7);\n assert(issame(result, 7, expected2, 7));\n free(result);\n\n int expected3[] = {1};\n result = func0(1);\n assert(issame(result, 1, expected3, 1));\n free(result);\n\n int expected4[] = {1, 2, 6};\n result = func0(3);\n assert(issame(result, 3, expected4, 3));\n free(result);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbx\nmov ebx, edi\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\ntest ebx, ebx\njle short loc_11ED\nlea r8d, [rbx+1]\nmov edx, 1\nmov esi, 1\nmov ecx, 0\nloc_11D3:\nadd ecx, edx\nimul esi, edx\ntest dl, 1\nmov edi, esi\ncmovnz edi, ecx\nmov [rax+rdx*4-4], edi\nadd rdx, 1\ncmp rdx, r8\njnz short loc_11D3\nloc_11ED:\npop rbx\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int a1)\n{\n _DWORD *result; // rax\n __int64 v3; // rdx\n int v4; // esi\n int v5; // ecx\n int v6; // edi\n\n result = malloc(4LL * a1);\n if ( a1 > 0 )\n {\n v3 = 1LL;\n v4 = 1;\n v5 = 0;\n do\n {\n v5 += v3;\n v4 *= (_DWORD)v3;\n v6 = v4;\n if ( (v3 & 1) != 0 )\n v6 = v5;\n result[v3++ - 1] = v6;\n }\n while ( v3 != a1 + 1 );\n }\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbx\nmov ebx, edi\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\ntest ebx, ebx\njle short loc_11ED\nlea r8d, [rbx+1]\nmov edx, 1\nmov esi, 1\nmov ecx, 0\nloc_11D3:\nadd ecx, edx\nimul esi, edx\ntest dl, 1\nmov edi, esi\ncmovnz edi, ecx\nmov [rax+rdx*4-4], edi\nadd rdx, 1\ncmp rdx, r8\njnz short loc_11D3\nloc_11ED:\npop rbx\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(int a1)\n{\n _DWORD *result; // rax\n __int64 v3; // rdx\n int v4; // esi\n int v5; // ecx\n int v6; // edi\n\n result = malloc(4LL * a1);\n if ( a1 > 0 )\n {\n v3 = 1LL;\n v4 = 1;\n v5 = 0;\n do\n {\n v5 += v3;\n v4 *= (_DWORD)v3;\n v6 = v4;\n if ( (v3 & 1) != 0 )\n v6 = v5;\n result[v3++ - 1] = v6;\n }\n while ( v3 != a1 + 1 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(int a1) {\n uint32_t *result;\n long long v3;\n int v4;\n int v5;\n int v6;\n result = malloc(4LL * a1);\n if (a1 > 0) {\n v3 = 1LL;\n v4 = 1;\n v5 = 0;\n do {\n v5 += v3;\n v4 *= (uint32_t)v3;\n v6 = v4;\n if ((v3 & 1) != 0) v6 = v5;\n result[v3++ - 1] = v6;\n } while (v3 != a1 + 1);\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(int a1) {\n uint32_t *result;\n long long v3;\n int v4;\n int v5;\n int v6;\n result = malloc(4LL * a1);\n if (a1 > 0) {\n v3 = 1LL;\n v4 = 1;\n v5 = 0;\n do {\n v5 += v3;\n v4 *= (uint32_t)v3;\n v6 = v4;\n if ((v3 & 1) != 0) v6 = v5;\n result[v3++ - 1] = v6;\n } while (v3 != a1 + 1);\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-106", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int* func0(int n) {\n int* out = (int*)malloc(n * sizeof(int));\n int sum = 0, prod = 1;\n for (int i = 1; i <= n; i++) {\n sum += i;\n prod *= i;\n if (i % 2 == 0)\n out[i - 1] = prod;\n else\n out[i - 1] = sum;\n }\n return out;\n}", + "test": "#include \n#include \n#include \n\nint issame(int* a, int a_size, int* b, int b_size) {\n if (a_size != b_size) return 0;\n for (int i = 0; i < a_size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int *result;\n int expected1[] = {1, 2, 6, 24, 15};\n result = func0(5);\n assert(issame(result, 5, expected1, 5));\n free(result);\n\n int expected2[] = {1, 2, 6, 24, 15, 720, 28};\n result = func0(7);\n assert(issame(result, 7, expected2, 7));\n free(result);\n\n int expected3[] = {1};\n result = func0(1);\n assert(issame(result, 1, expected3, 1));\n free(result);\n\n int expected4[] = {1, 2, 6};\n result = func0(3);\n assert(issame(result, 3, expected4, 3));\n free(result);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbx\nmovsxd rdi, edi\nmov rbx, rdi\nshl rdi, 2; size\ncall _malloc\ntest ebx, ebx\njle short loc_13EA\nlea r8d, [rbx+1]\nmov edx, 1\nmov esi, 1\nxor ecx, ecx\nnop dword ptr [rax+rax+00000000h]\nloc_13D0:\nimul esi, edx\nadd ecx, edx\ntest dl, 1\nmov edi, ecx\ncmovz edi, esi\nmov [rax+rdx*4-4], edi\nadd rdx, 1\ncmp r8, rdx\njnz short loc_13D0\nloc_13EA:\npop rbx\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int a1)\n{\n _DWORD *result; // rax\n __int64 v3; // rdx\n int v4; // esi\n int v5; // ecx\n int v6; // edi\n\n result = malloc(4LL * a1);\n if ( a1 > 0 )\n {\n v3 = 1LL;\n v4 = 1;\n v5 = 0;\n do\n {\n v4 *= (_DWORD)v3;\n v5 += v3;\n v6 = v5;\n if ( (v3 & 1) == 0 )\n v6 = v4;\n result[v3++ - 1] = v6;\n }\n while ( a1 + 1 != v3 );\n }\n return result;\n}", + "ida_strip_asm": "sub_13A0:\nendbr64\npush rbx\nmovsxd rdi, edi\nmov rbx, rdi\nshl rdi, 2; size\ncall _malloc\ntest ebx, ebx\njle short loc_13EA\nlea r8d, [rbx+1]\nmov edx, 1\nmov esi, 1\nxor ecx, ecx\nnop dword ptr [rax+rax+00000000h]\nloc_13D0:\nimul esi, edx\nadd ecx, edx\ntest dl, 1\nmov edi, ecx\ncmovz edi, esi\nmov [rax+rdx*4-4], edi\nadd rdx, 1\ncmp r8, rdx\njnz short loc_13D0\nloc_13EA:\npop rbx\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_13A0(int a1)\n{\n _DWORD *result; // rax\n __int64 v3; // rdx\n int v4; // esi\n int v5; // ecx\n int v6; // edi\n\n result = malloc(4LL * a1);\n if ( a1 > 0 )\n {\n v3 = 1LL;\n v4 = 1;\n v5 = 0;\n do\n {\n v4 *= (_DWORD)v3;\n v5 += v3;\n v6 = v5;\n if ( (v3 & 1) == 0 )\n v6 = v4;\n result[v3++ - 1] = v6;\n }\n while ( a1 + 1 != v3 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_13A0(int a1) {\n uint32_t *result;\n long long v3;\n int v4;\n int v5;\n int v6;\n result = malloc(4LL * a1);\n if (a1 > 0) {\n v3 = 1LL;\n v4 = 1;\n v5 = 0;\n do {\n v4 *= (uint32_t)v3;\n v5 += v3;\n v6 = v5;\n if ((v3 & 1) == 0) v6 = v4;\n result[v3++ - 1] = v6;\n } while (a1 + 1 != v3);\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(int a1) {\n uint32_t *result;\n long long v3;\n int v4;\n int v5;\n int v6;\n result = malloc(4LL * a1);\n if (a1 > 0) {\n v3 = 1LL;\n v4 = 1;\n v5 = 0;\n do {\n v4 *= (uint32_t)v3;\n v5 += v3;\n v6 = v5;\n if ((v3 & 1) == 0) v6 = v4;\n result[v3++ - 1] = v6;\n } while (a1 + 1 != v3);\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-106", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int* func0(int n) {\n int* out = (int*)malloc(n * sizeof(int));\n int sum = 0, prod = 1;\n for (int i = 1; i <= n; i++) {\n sum += i;\n prod *= i;\n if (i % 2 == 0)\n out[i - 1] = prod;\n else\n out[i - 1] = sum;\n }\n return out;\n}", + "test": "#include \n#include \n#include \n\nint issame(int* a, int a_size, int* b, int b_size) {\n if (a_size != b_size) return 0;\n for (int i = 0; i < a_size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int *result;\n int expected1[] = {1, 2, 6, 24, 15};\n result = func0(5);\n assert(issame(result, 5, expected1, 5));\n free(result);\n\n int expected2[] = {1, 2, 6, 24, 15, 720, 28};\n result = func0(7);\n assert(issame(result, 7, expected2, 7));\n free(result);\n\n int expected3[] = {1};\n result = func0(1);\n assert(issame(result, 1, expected3, 1));\n free(result);\n\n int expected4[] = {1, 2, 6};\n result = func0(3);\n assert(issame(result, 3, expected4, 3));\n free(result);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbx\nmovsxd rdi, edi\nmov rbx, rdi\nshl rdi, 2; size\ncall _malloc\ntest ebx, ebx\njle short loc_13E7\nlea edi, [rbx+1]\nmov edx, 1\nmov esi, 1\nxor ecx, ecx\nnop word ptr [rax+rax+00000000h]\nloc_13D0:\nimul esi, edx\nadd ecx, edx\ntest dl, 1\njz short loc_13F0\nmov [rax+rdx*4-4], ecx\nadd rdx, 1\ncmp rdx, rdi\njnz short loc_13D0\nloc_13E7:\npop rbx\nretn\nloc_13F0:\nmov [rax+rdx*4-4], esi\nadd rdx, 1\ncmp rdi, rdx\njnz short loc_13D0\npop rbx\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int a1)\n{\n _DWORD *result; // rax\n __int64 v2; // rdi\n __int64 v3; // rdx\n int v4; // esi\n int v5; // ecx\n\n result = malloc(4LL * a1);\n if ( a1 > 0 )\n {\n v2 = (unsigned int)(a1 + 1);\n v3 = 1LL;\n v4 = 1;\n v5 = 0;\n do\n {\n while ( 1 )\n {\n v4 *= (_DWORD)v3;\n v5 += v3;\n if ( (v3 & 1) == 0 )\n break;\n result[v3++ - 1] = v5;\n if ( v3 == v2 )\n return result;\n }\n result[v3++ - 1] = v4;\n }\n while ( v2 != v3 );\n }\n return result;\n}", + "ida_strip_asm": "sub_13A0:\nendbr64\npush rbx\nmovsxd rdi, edi\nmov rbx, rdi\nshl rdi, 2; size\ncall _malloc\ntest ebx, ebx\njle short loc_13E7\nlea edi, [rbx+1]\nmov edx, 1\nmov esi, 1\nxor ecx, ecx\nnop word ptr [rax+rax+00000000h]\nloc_13D0:\nimul esi, edx\nadd ecx, edx\ntest dl, 1\njz short loc_13F0\nmov [rax+rdx*4-4], ecx\nadd rdx, 1\ncmp rdx, rdi\njnz short loc_13D0\nloc_13E7:\npop rbx\nretn\nloc_13F0:\nmov [rax+rdx*4-4], esi\nadd rdx, 1\ncmp rdi, rdx\njnz short loc_13D0\npop rbx\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_13A0(int a1)\n{\n _DWORD *result; // rax\n __int64 v2; // rdi\n __int64 v3; // rdx\n int v4; // esi\n int v5; // ecx\n\n result = malloc(4LL * a1);\n if ( a1 > 0 )\n {\n v2 = (unsigned int)(a1 + 1);\n v3 = 1LL;\n v4 = 1;\n v5 = 0;\n do\n {\n while ( 1 )\n {\n v4 *= (_DWORD)v3;\n v5 += v3;\n if ( (v3 & 1) == 0 )\n break;\n result[v3++ - 1] = v5;\n if ( v3 == v2 )\n return result;\n }\n result[v3++ - 1] = v4;\n }\n while ( v2 != v3 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_13A0(int a1) {\n uint32_t *result;\n long long v2;\n long long v3;\n int v4;\n int v5;\n result = malloc(4LL * a1);\n if (a1 > 0) {\n v2 = (unsigned int)(a1 + 1);\n v3 = 1LL;\n v4 = 1;\n v5 = 0;\n do {\n while (1) {\n v4 *= (uint32_t)v3;\n v5 += v3;\n if ((v3 & 1) == 0) break;\n result[v3++ - 1] = v5;\n if (v3 == v2) return result;\n }\n result[v3++ - 1] = v4;\n } while (v2 != v3);\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(int a1) {\n uint32_t *result;\n long long v2;\n long long v3;\n int v4;\n int v5;\n result = malloc(4LL * a1);\n if (a1 > 0) {\n v2 = (unsigned int)(a1 + 1);\n v3 = 1LL;\n v4 = 1;\n v5 = 0;\n do {\n while (1) {\n v4 *= (uint32_t)v3;\n v5 += v3;\n if ((v3 & 1) == 0) break;\n result[v3++ - 1] = v5;\n if (v3 == v2) return result;\n }\n result[v3++ - 1] = v4;\n } while (v2 != v3);\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-107", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int* func0(int n) {\n int* counts = (int*)malloc(2 * sizeof(int));\n counts[0] = 0;\n counts[1] = 0;\n for (int i = 1; i <= n; i++) {\n int reversed = 0, original = i;\n int number = i;\n while (number != 0) {\n reversed = reversed * 10 + number % 10;\n number /= 10;\n }\n if (original == reversed) {\n if (original % 2 == 0)\n counts[0]++;\n else\n counts[1]++;\n }\n }\n return counts;\n}", + "test": "#include \n#include \n#include \n\nint issame(int* a, int* b, int size) {\n for (int i = 0; i < size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int* result;\n\n result = func0(123);\n int expected1[] = {8, 13};\n assert(issame(result, expected1, 2));\n free(result);\n\n result = func0(12);\n int expected2[] = {4, 6};\n assert(issame(result, expected2, 2));\n free(result);\n\n result = func0(3);\n int expected3[] = {1, 2};\n assert(issame(result, expected3, 2));\n free(result);\n\n result = func0(63);\n int expected4[] = {6, 8};\n assert(issame(result, expected4, 2));\n free(result);\n\n result = func0(25);\n int expected5[] = {5, 6};\n assert(issame(result, expected5, 2));\n free(result);\n\n result = func0(19);\n int expected6[] = {4, 6};\n assert(issame(result, expected6, 2));\n free(result);\n\n result = func0(9);\n int expected7[] = {4, 5};\n assert(issame(result, expected7, 2));\n free(result);\n\n result = func0(1);\n int expected8[] = {0, 1};\n assert(issame(result, expected8, 2));\n free(result);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_24], edi\nmov edi, 8; size\ncall _malloc\nmov [rbp+var_8], rax\nmov rax, [rbp+var_8]\nmov dword ptr [rax], 0\nmov rax, [rbp+var_8]\nadd rax, 4\nmov dword ptr [rax], 0\nmov [rbp+var_18], 1\njmp loc_1297\nloc_11EA:\nmov [rbp+var_14], 0\nmov eax, [rbp+var_18]\nmov [rbp+var_C], eax\nmov eax, [rbp+var_18]\nmov [rbp+var_10], eax\njmp short loc_125B\nloc_11FF:\nmov edx, [rbp+var_14]\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nmov esi, eax\nmov ecx, [rbp+var_10]\nmovsxd rax, ecx\nimul rax, 66666667h\nshr rax, 20h\nmov edx, eax\nsar edx, 2\nmov eax, ecx\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nsub ecx, eax\nmov edx, ecx\nlea eax, [rsi+rdx]\nmov [rbp+var_14], eax\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_10], eax\nloc_125B:\ncmp [rbp+var_10], 0\njnz short loc_11FF\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_14]\njnz short loc_1293\nmov eax, [rbp+var_C]\nand eax, 1\ntest eax, eax\njnz short loc_1284\nmov rax, [rbp+var_8]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_8]\nmov [rax], edx\njmp short loc_1293\nloc_1284:\nmov rax, [rbp+var_8]\nadd rax, 4\nmov edx, [rax]\nadd edx, 1\nmov [rax], edx\nloc_1293:\nadd [rbp+var_18], 1\nloc_1297:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_24]\njle loc_11EA\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int a1)\n{\n int i; // [rsp+18h] [rbp-18h]\n int v3; // [rsp+1Ch] [rbp-14h]\n int j; // [rsp+20h] [rbp-10h]\n _DWORD *v5; // [rsp+28h] [rbp-8h]\n\n v5 = malloc(8uLL);\n *v5 = 0;\n v5[1] = 0;\n for ( i = 1; i <= a1; ++i )\n {\n v3 = 0;\n for ( j = i; j; j /= 10 )\n v3 = 10 * v3 + j % 10;\n if ( i == v3 )\n {\n if ( (i & 1) != 0 )\n ++v5[1];\n else\n ++*v5;\n }\n }\n return v5;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_24], edi\nmov edi, 8; size\ncall _malloc\nmov [rbp+var_8], rax\nmov rax, [rbp+var_8]\nmov dword ptr [rax], 0\nmov rax, [rbp+var_8]\nadd rax, 4\nmov dword ptr [rax], 0\nmov [rbp+var_18], 1\njmp loc_1297\nloc_11EA:\nmov [rbp+var_14], 0\nmov eax, [rbp+var_18]\nmov [rbp+var_C], eax\nmov eax, [rbp+var_18]\nmov [rbp+var_10], eax\njmp short loc_125B\nloc_11FF:\nmov edx, [rbp+var_14]\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nmov esi, eax\nmov ecx, [rbp+var_10]\nmovsxd rax, ecx\nimul rax, 66666667h\nshr rax, 20h\nmov edx, eax\nsar edx, 2\nmov eax, ecx\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nsub ecx, eax\nmov edx, ecx\nlea eax, [rsi+rdx]\nmov [rbp+var_14], eax\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_10], eax\nloc_125B:\ncmp [rbp+var_10], 0\njnz short loc_11FF\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_14]\njnz short loc_1293\nmov eax, [rbp+var_C]\nand eax, 1\ntest eax, eax\njnz short loc_1284\nmov rax, [rbp+var_8]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_8]\nmov [rax], edx\njmp short loc_1293\nloc_1284:\nmov rax, [rbp+var_8]\nadd rax, 4\nmov edx, [rax]\nadd edx, 1\nmov [rax], edx\nloc_1293:\nadd [rbp+var_18], 1\nloc_1297:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_24]\njle loc_11EA\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(int a1)\n{\n int i; // [rsp+18h] [rbp-18h]\n int v3; // [rsp+1Ch] [rbp-14h]\n int j; // [rsp+20h] [rbp-10h]\n _DWORD *v5; // [rsp+28h] [rbp-8h]\n\n v5 = malloc(8uLL);\n *v5 = 0;\n v5[1] = 0;\n for ( i = 1; i <= a1; ++i )\n {\n v3 = 0;\n for ( j = i; j; j /= 10 )\n v3 = 10 * v3 + j % 10;\n if ( i == v3 )\n {\n if ( (i & 1) != 0 )\n ++v5[1];\n else\n ++*v5;\n }\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(int a1) {\n int i;\n int v3;\n int j;\n uint32_t *v5;\n v5 = malloc(8uLL);\n *v5 = 0;\n v5[1] = 0;\n for (i = 1; i <= a1; ++i) {\n v3 = 0;\n for (j = i; j; j /= 10) v3 = 10 * v3 + j % 10;\n if (i == v3) {\n if ((i & 1) != 0)\n ++v5[1];\n else\n ++*v5;\n }\n }\n return v5;\n}", + "ida_pseudo_norm": "uint32_t *func0(int a1) {\n int i;\n int v3;\n int j;\n uint32_t *v5;\n v5 = malloc(8uLL);\n *v5 = 0;\n v5[1] = 0;\n for (i = 1; i <= a1; ++i) {\n v3 = 0;\n for (j = i; j; j /= 10) v3 = 10 * v3 + j % 10;\n if (i == v3) {\n if ((i & 1) != 0)\n ++v5[1];\n else\n ++*v5;\n }\n }\n return v5;\n}" + }, + { + "index": "HumanEval-C-107", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int* func0(int n) {\n int* counts = (int*)malloc(2 * sizeof(int));\n counts[0] = 0;\n counts[1] = 0;\n for (int i = 1; i <= n; i++) {\n int reversed = 0, original = i;\n int number = i;\n while (number != 0) {\n reversed = reversed * 10 + number % 10;\n number /= 10;\n }\n if (original == reversed) {\n if (original % 2 == 0)\n counts[0]++;\n else\n counts[1]++;\n }\n }\n return counts;\n}", + "test": "#include \n#include \n#include \n\nint issame(int* a, int* b, int size) {\n for (int i = 0; i < size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int* result;\n\n result = func0(123);\n int expected1[] = {8, 13};\n assert(issame(result, expected1, 2));\n free(result);\n\n result = func0(12);\n int expected2[] = {4, 6};\n assert(issame(result, expected2, 2));\n free(result);\n\n result = func0(3);\n int expected3[] = {1, 2};\n assert(issame(result, expected3, 2));\n free(result);\n\n result = func0(63);\n int expected4[] = {6, 8};\n assert(issame(result, expected4, 2));\n free(result);\n\n result = func0(25);\n int expected5[] = {5, 6};\n assert(issame(result, expected5, 2));\n free(result);\n\n result = func0(19);\n int expected6[] = {4, 6};\n assert(issame(result, expected6, 2));\n free(result);\n\n result = func0(9);\n int expected7[] = {4, 5};\n assert(issame(result, expected7, 2));\n free(result);\n\n result = func0(1);\n int expected8[] = {0, 1};\n assert(issame(result, expected8, 2));\n free(result);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbx\nmov ebx, edi\nmov edi, 8; size\ncall _malloc\nmov r9, rax\nmov dword ptr [rax], 0\nmov dword ptr [rax+4], 0\ntest ebx, ebx\njle short loc_122D\nlea r8d, [rbx+1]\nmov edi, 1\nmov r10d, 0\njmp short loc_11EB\nloc_11DF:\nadd dword ptr [r9], 1\nloc_11E3:\nadd edi, 1\ncmp r8d, edi\njz short loc_122D\nloc_11EB:\nmov edx, edi\nmov ecx, r10d\ntest edi, edi\njz short loc_11DF\nloc_11F4:\nlea esi, [rcx+rcx*4]\nmovsxd rax, edx\nimul rax, 66666667h\nsar rax, 22h\nmov ecx, edx\nsar ecx, 1Fh\nsub eax, ecx\nlea ecx, [rax+rax*4]\nadd ecx, ecx\nsub edx, ecx\nlea ecx, [rdx+rsi*2]\nmov edx, eax\ntest eax, eax\njnz short loc_11F4\ncmp ecx, edi\njnz short loc_11E3\ntest dil, 1\njz short loc_11DF\nadd dword ptr [r9+4], 1\njmp short loc_11E3\nloc_122D:\nmov rax, r9\npop rbx\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int a1)\n{\n _DWORD *v1; // r9\n int v2; // r8d\n int i; // edi\n int v4; // edx\n int v5; // ecx\n\n v1 = malloc(8uLL);\n *v1 = 0;\n v1[1] = 0;\n if ( a1 > 0 )\n {\n v2 = a1 + 1;\n for ( i = 1; v2 != i; ++i )\n {\n v4 = i;\n v5 = 0;\n if ( !i )\n goto LABEL_3;\n do\n {\n v5 = v4 % 10 + 10 * v5;\n v4 /= 10;\n }\n while ( v4 );\n if ( v5 != i )\n continue;\n if ( (i & 1) != 0 )\n ++v1[1];\n else\nLABEL_3:\n ++*v1;\n }\n }\n return v1;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbx\nmov ebx, edi\nmov edi, 8; size\ncall _malloc\nmov r9, rax\nmov dword ptr [rax], 0\nmov dword ptr [rax+4], 0\ntest ebx, ebx\njle short loc_122D\nlea r8d, [rbx+1]\nmov edi, 1\nmov r10d, 0\njmp short loc_11EB\nloc_11DF:\nadd dword ptr [r9], 1\nloc_11E3:\nadd edi, 1\ncmp r8d, edi\njz short loc_122D\nloc_11EB:\nmov edx, edi\nmov ecx, r10d\ntest edi, edi\njz short loc_11DF\nloc_11F4:\nlea esi, [rcx+rcx*4]\nmovsxd rax, edx\nimul rax, 66666667h\nsar rax, 22h\nmov ecx, edx\nsar ecx, 1Fh\nsub eax, ecx\nlea ecx, [rax+rax*4]\nadd ecx, ecx\nsub edx, ecx\nlea ecx, [rdx+rsi*2]\nmov edx, eax\ntest eax, eax\njnz short loc_11F4\ncmp ecx, edi\njnz short loc_11E3\ntest dil, 1\njz short loc_11DF\nadd dword ptr [r9+4], 1\njmp short loc_11E3\nloc_122D:\nmov rax, r9\npop rbx\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(int a1)\n{\n _DWORD *v1; // r9\n int v2; // r8d\n int i; // edi\n int v4; // edx\n int v5; // ecx\n\n v1 = malloc(8uLL);\n *v1 = 0;\n v1[1] = 0;\n if ( a1 > 0 )\n {\n v2 = a1 + 1;\n for ( i = 1; v2 != i; ++i )\n {\n v4 = i;\n v5 = 0;\n if ( !i )\n goto LABEL_3;\n do\n {\n v5 = v4 % 10 + 10 * v5;\n v4 /= 10;\n }\n while ( v4 );\n if ( v5 != i )\n continue;\n if ( (i & 1) != 0 )\n ++v1[1];\n else\nLABEL_3:\n ++*v1;\n }\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(int a1) {\n uint32_t *v1;\n int v2;\n int i;\n int v4;\n int v5;\n v1 = malloc(8uLL);\n *v1 = 0;\n v1[1] = 0;\n if (a1 > 0) {\n v2 = a1 + 1;\n for (i = 1; v2 != i; ++i) {\n v4 = i;\n v5 = 0;\n if (!i) goto LABEL_3;\n do {\n v5 = v4 % 10 + 10 * v5;\n v4 /= 10;\n } while (v4);\n if (v5 != i) continue;\n if ((i & 1) != 0)\n ++v1[1];\n else\n LABEL_3:\n ++*v1;\n }\n }\n return v1;\n}", + "ida_pseudo_norm": "uint32_t *func0(int a1) {\n uint32_t *v1;\n int v2;\n int i;\n int v4;\n int v5;\n v1 = malloc(8uLL);\n *v1 = 0;\n v1[1] = 0;\n if (a1 > 0) {\n v2 = a1 + 1;\n for (i = 1; v2 != i; ++i) {\n v4 = i;\n v5 = 0;\n if (!i) goto LABEL_3;\n do {\n v5 = v4 % 10 + 10 * v5;\n v4 /= 10;\n } while (v4);\n if (v5 != i) continue;\n if ((i & 1) != 0)\n ++v1[1];\n else\n LABEL_3:\n ++*v1;\n }\n }\n return v1;\n}" + }, + { + "index": "HumanEval-C-107", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int* func0(int n) {\n int* counts = (int*)malloc(2 * sizeof(int));\n counts[0] = 0;\n counts[1] = 0;\n for (int i = 1; i <= n; i++) {\n int reversed = 0, original = i;\n int number = i;\n while (number != 0) {\n reversed = reversed * 10 + number % 10;\n number /= 10;\n }\n if (original == reversed) {\n if (original % 2 == 0)\n counts[0]++;\n else\n counts[1]++;\n }\n }\n return counts;\n}", + "test": "#include \n#include \n#include \n\nint issame(int* a, int* b, int size) {\n for (int i = 0; i < size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int* result;\n\n result = func0(123);\n int expected1[] = {8, 13};\n assert(issame(result, expected1, 2));\n free(result);\n\n result = func0(12);\n int expected2[] = {4, 6};\n assert(issame(result, expected2, 2));\n free(result);\n\n result = func0(3);\n int expected3[] = {1, 2};\n assert(issame(result, expected3, 2));\n free(result);\n\n result = func0(63);\n int expected4[] = {6, 8};\n assert(issame(result, expected4, 2));\n free(result);\n\n result = func0(25);\n int expected5[] = {5, 6};\n assert(issame(result, expected5, 2));\n free(result);\n\n result = func0(19);\n int expected6[] = {4, 6};\n assert(issame(result, expected6, 2));\n free(result);\n\n result = func0(9);\n int expected7[] = {4, 5};\n assert(issame(result, expected7, 2));\n free(result);\n\n result = func0(1);\n int expected8[] = {0, 1};\n assert(issame(result, expected8, 2));\n free(result);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbx\nmov ebx, edi\nmov edi, 8; size\ncall _malloc\nmov qword ptr [rax], 0\ntest ebx, ebx\njle short loc_141E\nlea r9d, [rbx+1]\nmov r8d, 1\nnop word ptr [rax+rax+00000000h]\nloc_13E0:\nmov ecx, r8d\nxor esi, esi\nnop dword ptr [rax]\nloc_13E8:\nmovsxd rdx, ecx\nlea edi, [rsi+rsi*4]\nmov esi, ecx\nimul rdx, 66666667h\nsar esi, 1Fh\nsar rdx, 22h\nsub edx, esi\nlea esi, [rdx+rdx*4]\nadd esi, esi\nsub ecx, esi\nlea esi, [rcx+rdi*2]\nmov ecx, edx\ntest edx, edx\njnz short loc_13E8\ncmp esi, r8d\njz short loc_1420\nloc_1415:\nadd r8d, 1\ncmp r8d, r9d\njnz short loc_13E0\nloc_141E:\npop rbx\nretn\nloc_1420:\ntest r8b, 1\njnz short loc_1430\nadd dword ptr [rax], 1\njmp short loc_1415\nloc_1430:\nadd dword ptr [rax+4], 1\njmp short loc_1415", + "ida_pseudo": "_DWORD *__fastcall func0(int a1)\n{\n _DWORD *result; // rax\n int v2; // r8d\n int v3; // ecx\n int v4; // esi\n\n result = malloc(8uLL);\n *(_QWORD *)result = 0LL;\n if ( a1 > 0 )\n {\n v2 = 1;\n do\n {\n v3 = v2;\n v4 = 0;\n do\n {\n v4 = v3 % 10 + 10 * v4;\n v3 /= 10;\n }\n while ( v3 );\n if ( v4 == v2 )\n {\n if ( (v2 & 1) != 0 )\n ++result[1];\n else\n ++*result;\n }\n ++v2;\n }\n while ( v2 != a1 + 1 );\n }\n return result;\n}", + "ida_strip_asm": "sub_13B0:\nendbr64\npush rbx\nmov ebx, edi\nmov edi, 8; size\ncall _malloc\nmov qword ptr [rax], 0\ntest ebx, ebx\njle short loc_141E\nlea r9d, [rbx+1]\nmov r8d, 1\nnop word ptr [rax+rax+00000000h]\nloc_13E0:\nmov ecx, r8d\nxor esi, esi\nnop dword ptr [rax]\nloc_13E8:\nmovsxd rdx, ecx\nlea edi, [rsi+rsi*4]\nmov esi, ecx\nimul rdx, 66666667h\nsar esi, 1Fh\nsar rdx, 22h\nsub edx, esi\nlea esi, [rdx+rdx*4]\nadd esi, esi\nsub ecx, esi\nlea esi, [rcx+rdi*2]\nmov ecx, edx\ntest edx, edx\njnz short loc_13E8\ncmp esi, r8d\njz short loc_1420\nloc_1415:\nadd r8d, 1\ncmp r8d, r9d\njnz short loc_13E0\nloc_141E:\npop rbx\nretn\nloc_1420:\ntest r8b, 1\njnz short loc_1430\nadd dword ptr [rax], 1\njmp short loc_1415\nloc_1430:\nadd dword ptr [rax+4], 1\njmp short loc_1415", + "ida_strip_pseudo": "_DWORD *__fastcall sub_13B0(int a1)\n{\n _DWORD *result; // rax\n int v2; // r8d\n int v3; // ecx\n int v4; // esi\n\n result = malloc(8uLL);\n *(_QWORD *)result = 0LL;\n if ( a1 > 0 )\n {\n v2 = 1;\n do\n {\n v3 = v2;\n v4 = 0;\n do\n {\n v4 = v3 % 10 + 10 * v4;\n v3 /= 10;\n }\n while ( v3 );\n if ( v4 == v2 )\n {\n if ( (v2 & 1) != 0 )\n ++result[1];\n else\n ++*result;\n }\n ++v2;\n }\n while ( v2 != a1 + 1 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_13B0(int a1) {\n uint32_t *result;\n int v2;\n int v3;\n int v4;\n result = malloc(8uLL);\n *(uint64_t *)result = 0LL;\n if (a1 > 0) {\n v2 = 1;\n do {\n v3 = v2;\n v4 = 0;\n do {\n v4 = v3 % 10 + 10 * v4;\n v3 /= 10;\n } while (v3);\n if (v4 == v2) {\n if ((v2 & 1) != 0)\n ++result[1];\n else\n ++*result;\n }\n ++v2;\n } while (v2 != a1 + 1);\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(int a1) {\n uint32_t *result;\n int v2;\n int v3;\n int v4;\n result = malloc(8uLL);\n *(uint64_t *)result = 0LL;\n if (a1 > 0) {\n v2 = 1;\n do {\n v3 = v2;\n v4 = 0;\n do {\n v4 = v3 % 10 + 10 * v4;\n v3 /= 10;\n } while (v3);\n if (v4 == v2) {\n if ((v2 & 1) != 0)\n ++result[1];\n else\n ++*result;\n }\n ++v2;\n } while (v2 != a1 + 1);\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-107", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int* func0(int n) {\n int* counts = (int*)malloc(2 * sizeof(int));\n counts[0] = 0;\n counts[1] = 0;\n for (int i = 1; i <= n; i++) {\n int reversed = 0, original = i;\n int number = i;\n while (number != 0) {\n reversed = reversed * 10 + number % 10;\n number /= 10;\n }\n if (original == reversed) {\n if (original % 2 == 0)\n counts[0]++;\n else\n counts[1]++;\n }\n }\n return counts;\n}", + "test": "#include \n#include \n#include \n\nint issame(int* a, int* b, int size) {\n for (int i = 0; i < size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int* result;\n\n result = func0(123);\n int expected1[] = {8, 13};\n assert(issame(result, expected1, 2));\n free(result);\n\n result = func0(12);\n int expected2[] = {4, 6};\n assert(issame(result, expected2, 2));\n free(result);\n\n result = func0(3);\n int expected3[] = {1, 2};\n assert(issame(result, expected3, 2));\n free(result);\n\n result = func0(63);\n int expected4[] = {6, 8};\n assert(issame(result, expected4, 2));\n free(result);\n\n result = func0(25);\n int expected5[] = {5, 6};\n assert(issame(result, expected5, 2));\n free(result);\n\n result = func0(19);\n int expected6[] = {4, 6};\n assert(issame(result, expected6, 2));\n free(result);\n\n result = func0(9);\n int expected7[] = {4, 5};\n assert(issame(result, expected7, 2));\n free(result);\n\n result = func0(1);\n int expected8[] = {0, 1};\n assert(issame(result, expected8, 2));\n free(result);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbx\nmov ebx, edi\nmov edi, 8; size\ncall _malloc\nmov qword ptr [rax], 0\ntest ebx, ebx\njle short loc_141E\nlea r9d, [rbx+1]\nmov r8d, 1\nnop word ptr [rax+rax+00000000h]\nloc_13E0:\nmov ecx, r8d\nxor esi, esi\nnop dword ptr [rax]\nloc_13E8:\nmovsxd rdx, ecx\nlea edi, [rsi+rsi*4]\nmov esi, ecx\nimul rdx, 66666667h\nsar esi, 1Fh\nsar rdx, 22h\nsub edx, esi\nlea esi, [rdx+rdx*4]\nadd esi, esi\nsub ecx, esi\nlea esi, [rcx+rdi*2]\nmov ecx, edx\ntest edx, edx\njnz short loc_13E8\ncmp esi, r8d\njz short loc_1420\nloc_1415:\nadd r8d, 1\ncmp r8d, r9d\njnz short loc_13E0\nloc_141E:\npop rbx\nretn\nloc_1420:\ntest r8b, 1\njnz short loc_1430\nadd dword ptr [rax], 1\njmp short loc_1415\nloc_1430:\nadd dword ptr [rax+4], 1\njmp short loc_1415", + "ida_pseudo": "_DWORD *__fastcall func0(int a1)\n{\n _DWORD *result; // rax\n int v2; // r8d\n int v3; // ecx\n int v4; // esi\n\n result = malloc(8uLL);\n *(_QWORD *)result = 0LL;\n if ( a1 > 0 )\n {\n v2 = 1;\n do\n {\n v3 = v2;\n v4 = 0;\n do\n {\n v4 = v3 % 10 + 10 * v4;\n v3 /= 10;\n }\n while ( v3 );\n if ( v4 == v2 )\n {\n if ( (v2 & 1) != 0 )\n ++result[1];\n else\n ++*result;\n }\n ++v2;\n }\n while ( v2 != a1 + 1 );\n }\n return result;\n}", + "ida_strip_asm": "sub_13B0:\nendbr64\npush rbx\nmov ebx, edi\nmov edi, 8; size\ncall _malloc\nmov qword ptr [rax], 0\ntest ebx, ebx\njle short loc_141E\nlea r9d, [rbx+1]\nmov r8d, 1\nnop word ptr [rax+rax+00000000h]\nloc_13E0:\nmov ecx, r8d\nxor esi, esi\nnop dword ptr [rax]\nloc_13E8:\nmovsxd rdx, ecx\nlea edi, [rsi+rsi*4]\nmov esi, ecx\nimul rdx, 66666667h\nsar esi, 1Fh\nsar rdx, 22h\nsub edx, esi\nlea esi, [rdx+rdx*4]\nadd esi, esi\nsub ecx, esi\nlea esi, [rcx+rdi*2]\nmov ecx, edx\ntest edx, edx\njnz short loc_13E8\ncmp esi, r8d\njz short loc_1420\nloc_1415:\nadd r8d, 1\ncmp r8d, r9d\njnz short loc_13E0\nloc_141E:\npop rbx\nretn\nloc_1420:\ntest r8b, 1\njnz short loc_1430\nadd dword ptr [rax], 1\njmp short loc_1415\nloc_1430:\nadd dword ptr [rax+4], 1\njmp short loc_1415", + "ida_strip_pseudo": "_DWORD *__fastcall sub_13B0(int a1)\n{\n _DWORD *result; // rax\n int v2; // r8d\n int v3; // ecx\n int v4; // esi\n\n result = malloc(8uLL);\n *(_QWORD *)result = 0LL;\n if ( a1 > 0 )\n {\n v2 = 1;\n do\n {\n v3 = v2;\n v4 = 0;\n do\n {\n v4 = v3 % 10 + 10 * v4;\n v3 /= 10;\n }\n while ( v3 );\n if ( v4 == v2 )\n {\n if ( (v2 & 1) != 0 )\n ++result[1];\n else\n ++*result;\n }\n ++v2;\n }\n while ( v2 != a1 + 1 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_13B0(int a1) {\n uint32_t *result;\n int v2;\n int v3;\n int v4;\n result = malloc(8uLL);\n *(uint64_t *)result = 0LL;\n if (a1 > 0) {\n v2 = 1;\n do {\n v3 = v2;\n v4 = 0;\n do {\n v4 = v3 % 10 + 10 * v4;\n v3 /= 10;\n } while (v3);\n if (v4 == v2) {\n if ((v2 & 1) != 0)\n ++result[1];\n else\n ++*result;\n }\n ++v2;\n } while (v2 != a1 + 1);\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(int a1) {\n uint32_t *result;\n int v2;\n int v3;\n int v4;\n result = malloc(8uLL);\n *(uint64_t *)result = 0LL;\n if (a1 > 0) {\n v2 = 1;\n do {\n v3 = v2;\n v4 = 0;\n do {\n v4 = v3 % 10 + 10 * v4;\n v3 /= 10;\n } while (v3);\n if (v4 == v2) {\n if ((v2 & 1) != 0)\n ++result[1];\n else\n ++*result;\n }\n ++v2;\n } while (v2 != a1 + 1);\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-108", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(int *n, int size) {\n int num = 0;\n for (int i = 0; i < size; i++) {\n if (n[i] > 0) {\n num += 1;\n } else {\n int sum = 0;\n int w = abs(n[i]);\n while (w >= 10) {\n sum += w % 10;\n w = w / 10;\n }\n sum -= w;\n if (sum > 0) num += 1;\n }\n }\n return num;\n}", + "test": "#include \n\nint main() {\n assert(func0((const int[]){}, 0) == 0);\n assert(func0((const int[]){-1, -2, 0}, 3) == 0);\n assert(func0((const int[]){1, 1, 2, -2, 3, 4, 5}, 7) == 6);\n assert(func0((const int[]){1, 6, 9, -6, 0, 1, 5}, 7) == 5);\n assert(func0((const int[]){1, 100, 98, -7, 1, -1}, 6) == 4);\n assert(func0((const int[]){12, 23, 34, -45, -56, 0}, 6) == 5);\n assert(func0((const int[]){-0, 1}, 2) == 1);\n assert(func0((const int[]){1}, 1) == 1);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp loc_123C\nloc_118B:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njle short loc_11AE\nadd [rbp+var_10], 1\njmp loc_1238\nloc_11AE:\nmov [rbp+var_8], 0\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov edx, eax\nneg edx\ncmovns eax, edx\nmov [rbp+var_4], eax\njmp short loc_1222\nloc_11D7:\nmov ecx, [rbp+var_4]\nmovsxd rax, ecx\nimul rax, 66666667h\nshr rax, 20h\nmov edx, eax\nsar edx, 2\nmov eax, ecx\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nsub ecx, eax\nmov edx, ecx\nadd [rbp+var_8], edx\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_4], eax\nloc_1222:\ncmp [rbp+var_4], 9\njg short loc_11D7\nmov eax, [rbp+var_4]\nsub [rbp+var_8], eax\ncmp [rbp+var_8], 0\njle short loc_1238\nadd [rbp+var_10], 1\nloc_1238:\nadd [rbp+var_C], 1\nloc_123C:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl loc_118B\nmov eax, [rbp+var_10]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+Ch] [rbp-10h]\n int i; // [rsp+10h] [rbp-Ch]\n int v5; // [rsp+14h] [rbp-8h]\n int j; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(int *)(4LL * i + a1) <= 0 )\n {\n v5 = 0;\n for ( j = -*(_DWORD *)(4LL * i + a1); j > 9; j /= 10 )\n v5 += j % 10;\n if ( v5 - j > 0 )\n ++v3;\n }\n else\n {\n ++v3;\n }\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp loc_123C\nloc_118B:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njle short loc_11AE\nadd [rbp+var_10], 1\njmp loc_1238\nloc_11AE:\nmov [rbp+var_8], 0\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov edx, eax\nneg edx\ncmovns eax, edx\nmov [rbp+var_4], eax\njmp short loc_1222\nloc_11D7:\nmov ecx, [rbp+var_4]\nmovsxd rax, ecx\nimul rax, 66666667h\nshr rax, 20h\nmov edx, eax\nsar edx, 2\nmov eax, ecx\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nsub ecx, eax\nmov edx, ecx\nadd [rbp+var_8], edx\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_4], eax\nloc_1222:\ncmp [rbp+var_4], 9\njg short loc_11D7\nmov eax, [rbp+var_4]\nsub [rbp+var_8], eax\ncmp [rbp+var_8], 0\njle short loc_1238\nadd [rbp+var_10], 1\nloc_1238:\nadd [rbp+var_C], 1\nloc_123C:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl loc_118B\nmov eax, [rbp+var_10]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+Ch] [rbp-10h]\n int i; // [rsp+10h] [rbp-Ch]\n int v5; // [rsp+14h] [rbp-8h]\n int j; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(int *)(4LL * i + a1) <= 0 )\n {\n v5 = 0;\n for ( j = -*(_DWORD *)(4LL * i + a1); j > 9; j /= 10 )\n v5 += j % 10;\n if ( v5 - j > 0 )\n ++v3;\n }\n else\n {\n ++v3;\n }\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n unsigned int v3;\n int i;\n int v5;\n int j;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(int *)(4LL * i + a1) <= 0) {\n v5 = 0;\n for (j = -*(uint32_t *)(4LL * i + a1); j > 9; j /= 10) v5 += j % 10;\n if (v5 - j > 0) ++v3;\n } else {\n ++v3;\n }\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n int v5;\n int j;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(int *)(4LL * i + a1) <= 0) {\n v5 = 0;\n for (j = -*(uint32_t *)(4LL * i + a1); j > 9; j /= 10) v5 += j % 10;\n if (v5 - j > 0) ++v3;\n } else {\n ++v3;\n }\n }\n return v3;\n}" + }, + { + "index": "HumanEval-C-108", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(int *n, int size) {\n int num = 0;\n for (int i = 0; i < size; i++) {\n if (n[i] > 0) {\n num += 1;\n } else {\n int sum = 0;\n int w = abs(n[i]);\n while (w >= 10) {\n sum += w % 10;\n w = w / 10;\n }\n sum -= w;\n if (sum > 0) num += 1;\n }\n }\n return num;\n}", + "test": "#include \n\nint main() {\n assert(func0((const int[]){}, 0) == 0);\n assert(func0((const int[]){-1, -2, 0}, 3) == 0);\n assert(func0((const int[]){1, 1, 2, -2, 3, 4, 5}, 7) == 6);\n assert(func0((const int[]){1, 6, 9, -6, 0, 1, 5}, 7) == 5);\n assert(func0((const int[]){1, 100, 98, -7, 1, -1}, 6) == 4);\n assert(func0((const int[]){12, 23, 34, -45, -56, 0}, 6) == 5);\n assert(func0((const int[]){-0, 1}, 2) == 1);\n assert(func0((const int[]){1}, 1) == 1);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11DE\nmov r8, rdi\nmovsxd rsi, esi\nlea r10, [rdi+rsi*4]\nmov r9d, 0\njmp short loc_11D1\nloc_1183:\nmov edx, eax\nneg edx\ncmovs edx, eax\ncmp edx, 9\njle short loc_11C8\nmov esi, 0\nloc_1194:\nmovsxd rax, edx\nimul rax, 66666667h\nsar rax, 22h\nmov ecx, edx\nsar ecx, 1Fh\nsub eax, ecx\nlea ecx, [rax+rax*4]\nadd ecx, ecx\nmov edi, edx\nsub edi, ecx\nadd esi, edi\nmov ecx, edx\nmov edx, eax\ncmp ecx, 63h ; 'c'\njg short loc_1194\ncmp esi, eax\nsetnle al\nmovzx eax, al\nadd r9d, eax\nloc_11C8:\nadd r8, 4\ncmp r8, r10\njz short loc_11E4\nloc_11D1:\nmov eax, [r8]\ntest eax, eax\njle short loc_1183\nadd r9d, 1\njmp short loc_11C8\nloc_11DE:\nmov r9d, 0\nloc_11E4:\nmov eax, r9d\nretn", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int *v2; // r8\n int *v3; // r10\n unsigned int v4; // r9d\n int v5; // edx\n int v6; // esi\n int v7; // eax\n int v8; // ecx\n int v9; // eax\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n {\n v9 = *v2;\n if ( *v2 <= 0 )\n {\n v5 = -v9;\n if ( -v9 > 9 )\n {\n v6 = 0;\n do\n {\n v7 = v5 / 10;\n v6 += v5 % 10;\n v8 = v5;\n v5 /= 10;\n }\n while ( v8 > 99 );\n v4 += v6 > v7;\n }\n }\n else\n {\n ++v4;\n }\n ++v2;\n }\n while ( v2 != v3 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11DE\nmov r8, rdi\nmovsxd rsi, esi\nlea r10, [rdi+rsi*4]\nmov r9d, 0\njmp short loc_11D1\nloc_1183:\nmov edx, eax\nneg edx\ncmovs edx, eax\ncmp edx, 9\njle short loc_11C8\nmov esi, 0\nloc_1194:\nmovsxd rax, edx\nimul rax, 66666667h\nsar rax, 22h\nmov ecx, edx\nsar ecx, 1Fh\nsub eax, ecx\nlea ecx, [rax+rax*4]\nadd ecx, ecx\nmov edi, edx\nsub edi, ecx\nadd esi, edi\nmov ecx, edx\nmov edx, eax\ncmp ecx, 63h ; 'c'\njg short loc_1194\ncmp esi, eax\nsetnle al\nmovzx eax, al\nadd r9d, eax\nloc_11C8:\nadd r8, 4\ncmp r8, r10\njz short loc_11E4\nloc_11D1:\nmov eax, [r8]\ntest eax, eax\njle short loc_1183\nadd r9d, 1\njmp short loc_11C8\nloc_11DE:\nmov r9d, 0\nloc_11E4:\nmov eax, r9d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int *a1, int a2)\n{\n int *v2; // r8\n int *v3; // r10\n unsigned int v4; // r9d\n int v5; // edx\n int v6; // esi\n int v7; // eax\n int v8; // ecx\n int v9; // eax\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n {\n v9 = *v2;\n if ( *v2 <= 0 )\n {\n v5 = -v9;\n if ( -v9 > 9 )\n {\n v6 = 0;\n do\n {\n v7 = v5 / 10;\n v6 += v5 % 10;\n v8 = v5;\n v5 /= 10;\n }\n while ( v8 > 99 );\n v4 += v6 > v7;\n }\n }\n else\n {\n ++v4;\n }\n ++v2;\n }\n while ( v2 != v3 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int *a1, int a2) {\n int *v2;\n int *v3;\n unsigned int v4;\n int v5;\n int v6;\n int v7;\n int v8;\n int v9;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do {\n v9 = *v2;\n if (*v2 <= 0) {\n v5 = -v9;\n if (-v9 > 9) {\n v6 = 0;\n do {\n v7 = v5 / 10;\n v6 += v5 % 10;\n v8 = v5;\n v5 /= 10;\n } while (v8 > 99);\n v4 += v6 > v7;\n }\n } else {\n ++v4;\n }\n ++v2;\n } while (v2 != v3);\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int *v2;\n int *v3;\n unsigned int v4;\n int v5;\n int v6;\n int v7;\n int v8;\n int v9;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do {\n v9 = *v2;\n if (*v2 <= 0) {\n v5 = -v9;\n if (-v9 > 9) {\n v6 = 0;\n do {\n v7 = v5 / 10;\n v6 += v5 % 10;\n v8 = v5;\n v5 /= 10;\n } while (v8 > 99);\n v4 += v6 > v7;\n }\n } else {\n ++v4;\n }\n ++v2;\n } while (v2 != v3);\n }\n return v4;\n}" + }, + { + "index": "HumanEval-C-108", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(int *n, int size) {\n int num = 0;\n for (int i = 0; i < size; i++) {\n if (n[i] > 0) {\n num += 1;\n } else {\n int sum = 0;\n int w = abs(n[i]);\n while (w >= 10) {\n sum += w % 10;\n w = w / 10;\n }\n sum -= w;\n if (sum > 0) num += 1;\n }\n }\n return num;\n}", + "test": "#include \n\nint main() {\n assert(func0((const int[]){}, 0) == 0);\n assert(func0((const int[]){-1, -2, 0}, 3) == 0);\n assert(func0((const int[]){1, 1, 2, -2, 3, 4, 5}, 7) == 6);\n assert(func0((const int[]){1, 6, 9, -6, 0, 1, 5}, 7) == 5);\n assert(func0((const int[]){1, 100, 98, -7, 1, -1}, 6) == 4);\n assert(func0((const int[]){12, 23, 34, -45, -56, 0}, 6) == 5);\n assert(func0((const int[]){-0, 1}, 2) == 1);\n assert(func0((const int[]){1}, 1) == 1);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1448\nmovsxd rsi, esi\nxor r9d, r9d\nmov r10d, 0CCCCCCCDh\nlea r11, [rdi+rsi*4]\njmp short loc_13FD\nloc_13F0:\nadd r9d, 1\nloc_13F4:\nadd rdi, 4\ncmp rdi, r11\njz short loc_1444\nloc_13FD:\nmov eax, [rdi]\ntest eax, eax\njg short loc_13F0\nmov edx, eax\nneg edx\ncmp eax, 0FFFFFFF7h\njge short loc_13F4\nxor esi, esi\nxchg ax, ax\nloc_1410:\nmov eax, edx\nmov r8d, edx\nimul rax, r10\nshr rax, 23h\nlea ecx, [rax+rax*4]\nadd ecx, ecx\nsub r8d, ecx\nmov ecx, edx\nmov edx, eax\nadd esi, r8d\ncmp ecx, 63h ; 'c'\njg short loc_1410\nxor eax, eax\ncmp esi, edx\nsetnle al\nadd rdi, 4\nadd r9d, eax\ncmp rdi, r11\njnz short loc_13FD\nloc_1444:\nmov eax, r9d\nretn\nloc_1448:\nxor r9d, r9d\nmov eax, r9d\nretn", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n unsigned int v2; // r9d\n int *v3; // r11\n int v4; // eax\n unsigned int v5; // edx\n int v6; // esi\n unsigned int v7; // r8d\n int v8; // ecx\n\n if ( a2 > 0 )\n {\n v2 = 0;\n v3 = &a1[a2];\n while ( 1 )\n {\n while ( 1 )\n {\n v4 = *a1;\n if ( *a1 <= 0 )\n break;\n ++v2;\nLABEL_4:\n if ( ++a1 == v3 )\n return v2;\n }\n v5 = -v4;\n if ( v4 >= -9 )\n goto LABEL_4;\n v6 = 0;\n do\n {\n v7 = v5 % 0xA;\n v8 = v5;\n v5 /= 0xAu;\n v6 += v7;\n }\n while ( v8 > 99 );\n ++a1;\n v2 += v6 > (int)v5;\n if ( a1 == v3 )\n return v2;\n }\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_13D0:\nendbr64\ntest esi, esi\njle short loc_1448\nmovsxd rsi, esi\nxor r9d, r9d\nmov r10d, 0CCCCCCCDh\nlea r11, [rdi+rsi*4]\njmp short loc_13FD\nloc_13F0:\nadd r9d, 1\nloc_13F4:\nadd rdi, 4\ncmp rdi, r11\njz short loc_1444\nloc_13FD:\nmov eax, [rdi]\ntest eax, eax\njg short loc_13F0\nmov edx, eax\nneg edx\ncmp eax, 0FFFFFFF7h\njge short loc_13F4\nxor esi, esi\nxchg ax, ax\nloc_1410:\nmov eax, edx\nmov r8d, edx\nimul rax, r10\nshr rax, 23h\nlea ecx, [rax+rax*4]\nadd ecx, ecx\nsub r8d, ecx\nmov ecx, edx\nmov edx, eax\nadd esi, r8d\ncmp ecx, 63h ; 'c'\njg short loc_1410\nxor eax, eax\ncmp esi, edx\nsetnle al\nadd rdi, 4\nadd r9d, eax\ncmp rdi, r11\njnz short loc_13FD\nloc_1444:\nmov eax, r9d\nretn\nloc_1448:\nxor r9d, r9d\nmov eax, r9d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_13D0(int *a1, int a2)\n{\n unsigned int v2; // r9d\n int *v3; // r11\n int v4; // eax\n unsigned int v5; // edx\n int v6; // esi\n unsigned int v7; // r8d\n int v8; // ecx\n\n if ( a2 > 0 )\n {\n v2 = 0;\n v3 = &a1[a2];\n while ( 1 )\n {\n while ( 1 )\n {\n v4 = *a1;\n if ( *a1 <= 0 )\n break;\n ++v2;\nLABEL_4:\n if ( ++a1 == v3 )\n return v2;\n }\n v5 = -v4;\n if ( v4 >= -9 )\n goto LABEL_4;\n v6 = 0;\n do\n {\n v7 = v5 % 0xA;\n v8 = v5;\n v5 /= 0xAu;\n v6 += v7;\n }\n while ( v8 > 99 );\n ++a1;\n v2 += v6 > (int)v5;\n if ( a1 == v3 )\n return v2;\n }\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_13D0(int *a1, int a2) {\n unsigned int v2;\n int *v3;\n int v4;\n unsigned int v5;\n int v6;\n unsigned int v7;\n int v8;\n if (a2 > 0) {\n v2 = 0;\n v3 = &a1[a2];\n while (1) {\n while (1) {\n v4 = *a1;\n if (*a1 <= 0) break;\n ++v2;\n LABEL_4:\n if (++a1 == v3) return v2;\n }\n v5 = -v4;\n if (v4 >= -9) goto LABEL_4;\n v6 = 0;\n do {\n v7 = v5 % 10;\n v8 = v5;\n v5 /= 10u;\n v6 += v7;\n } while (v8 > 99);\n ++a1;\n v2 += v6 > (int)v5;\n if (a1 == v3) return v2;\n }\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n unsigned int v2;\n int *v3;\n int v4;\n unsigned int v5;\n int v6;\n unsigned int v7;\n int v8;\n if (a2 > 0) {\n v2 = 0;\n v3 = &a1[a2];\n while (1) {\n while (1) {\n v4 = *a1;\n if (*a1 <= 0) break;\n ++v2;\n LABEL_4:\n if (++a1 == v3) return v2;\n }\n v5 = -v4;\n if (v4 >= -9) goto LABEL_4;\n v6 = 0;\n do {\n v7 = v5 % 10;\n v8 = v5;\n v5 /= 10u;\n v6 += v7;\n } while (v8 > 99);\n ++a1;\n v2 += v6 > (int)v5;\n if (a1 == v3) return v2;\n }\n }\n return 0LL;\n}" + }, + { + "index": "HumanEval-C-108", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(int *n, int size) {\n int num = 0;\n for (int i = 0; i < size; i++) {\n if (n[i] > 0) {\n num += 1;\n } else {\n int sum = 0;\n int w = abs(n[i]);\n while (w >= 10) {\n sum += w % 10;\n w = w / 10;\n }\n sum -= w;\n if (sum > 0) num += 1;\n }\n }\n return num;\n}", + "test": "#include \n\nint main() {\n assert(func0((const int[]){}, 0) == 0);\n assert(func0((const int[]){-1, -2, 0}, 3) == 0);\n assert(func0((const int[]){1, 1, 2, -2, 3, 4, 5}, 7) == 6);\n assert(func0((const int[]){1, 6, 9, -6, 0, 1, 5}, 7) == 5);\n assert(func0((const int[]){1, 100, 98, -7, 1, -1}, 6) == 4);\n assert(func0((const int[]){12, 23, 34, -45, -56, 0}, 6) == 5);\n assert(func0((const int[]){-0, 1}, 2) == 1);\n assert(func0((const int[]){1}, 1) == 1);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1448\nmovsxd rsi, esi\nxor r9d, r9d\nmov r10d, 0CCCCCCCDh\nlea r11, [rdi+rsi*4]\njmp short loc_13FD\nloc_13F0:\nadd r9d, 1\nloc_13F4:\nadd rdi, 4\ncmp r11, rdi\njz short loc_1444\nloc_13FD:\nmov eax, [rdi]\ntest eax, eax\njg short loc_13F0\nmov edx, eax\nneg edx\ncmp eax, 0FFFFFFF7h\njge short loc_13F4\nxor esi, esi\nxchg ax, ax\nloc_1410:\nmov eax, edx\nmov r8d, edx\nimul rax, r10\nshr rax, 23h\nlea ecx, [rax+rax*4]\nadd ecx, ecx\nsub r8d, ecx\nmov ecx, edx\nmov edx, eax\nadd esi, r8d\ncmp ecx, 63h ; 'c'\njg short loc_1410\nxor eax, eax\ncmp esi, edx\nsetnle al\nadd rdi, 4\nadd r9d, eax\ncmp r11, rdi\njnz short loc_13FD\nloc_1444:\nmov eax, r9d\nretn\nloc_1448:\nxor r9d, r9d\nmov eax, r9d\nretn", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n unsigned int v2; // r9d\n int *v3; // r11\n int v4; // eax\n unsigned int v5; // edx\n int v6; // esi\n unsigned int v7; // r8d\n int v8; // ecx\n\n if ( a2 > 0 )\n {\n v2 = 0;\n v3 = &a1[a2];\n while ( 1 )\n {\n while ( 1 )\n {\n v4 = *a1;\n if ( *a1 <= 0 )\n break;\n ++v2;\nLABEL_4:\n if ( v3 == ++a1 )\n return v2;\n }\n v5 = -v4;\n if ( v4 >= -9 )\n goto LABEL_4;\n v6 = 0;\n do\n {\n v7 = v5 % 0xA;\n v8 = v5;\n v5 /= 0xAu;\n v6 += v7;\n }\n while ( v8 > 99 );\n ++a1;\n v2 += v6 > (int)v5;\n if ( v3 == a1 )\n return v2;\n }\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_13D0:\nendbr64\ntest esi, esi\njle short loc_1448\nmovsxd rsi, esi\nxor r9d, r9d\nmov r10d, 0CCCCCCCDh\nlea r11, [rdi+rsi*4]\njmp short loc_13FD\nloc_13F0:\nadd r9d, 1\nloc_13F4:\nadd rdi, 4\ncmp r11, rdi\njz short loc_1444\nloc_13FD:\nmov eax, [rdi]\ntest eax, eax\njg short loc_13F0\nmov edx, eax\nneg edx\ncmp eax, 0FFFFFFF7h\njge short loc_13F4\nxor esi, esi\nxchg ax, ax\nloc_1410:\nmov eax, edx\nmov r8d, edx\nimul rax, r10\nshr rax, 23h\nlea ecx, [rax+rax*4]\nadd ecx, ecx\nsub r8d, ecx\nmov ecx, edx\nmov edx, eax\nadd esi, r8d\ncmp ecx, 63h ; 'c'\njg short loc_1410\nxor eax, eax\ncmp esi, edx\nsetnle al\nadd rdi, 4\nadd r9d, eax\ncmp r11, rdi\njnz short loc_13FD\nloc_1444:\nmov eax, r9d\nretn\nloc_1448:\nxor r9d, r9d\nmov eax, r9d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_13D0(int *a1, int a2)\n{\n unsigned int v2; // r9d\n int *v3; // r11\n int v4; // eax\n unsigned int v5; // edx\n int v6; // esi\n unsigned int v7; // r8d\n int v8; // ecx\n\n if ( a2 > 0 )\n {\n v2 = 0;\n v3 = &a1[a2];\n while ( 1 )\n {\n while ( 1 )\n {\n v4 = *a1;\n if ( *a1 <= 0 )\n break;\n ++v2;\nLABEL_4:\n if ( v3 == ++a1 )\n return v2;\n }\n v5 = -v4;\n if ( v4 >= -9 )\n goto LABEL_4;\n v6 = 0;\n do\n {\n v7 = v5 % 0xA;\n v8 = v5;\n v5 /= 0xAu;\n v6 += v7;\n }\n while ( v8 > 99 );\n ++a1;\n v2 += v6 > (int)v5;\n if ( v3 == a1 )\n return v2;\n }\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_13D0(int *a1, int a2) {\n unsigned int v2;\n int *v3;\n int v4;\n unsigned int v5;\n int v6;\n unsigned int v7;\n int v8;\n if (a2 > 0) {\n v2 = 0;\n v3 = &a1[a2];\n while (1) {\n while (1) {\n v4 = *a1;\n if (*a1 <= 0) break;\n ++v2;\n LABEL_4:\n if (v3 == ++a1) return v2;\n }\n v5 = -v4;\n if (v4 >= -9) goto LABEL_4;\n v6 = 0;\n do {\n v7 = v5 % 10;\n v8 = v5;\n v5 /= 10u;\n v6 += v7;\n } while (v8 > 99);\n ++a1;\n v2 += v6 > (int)v5;\n if (v3 == a1) return v2;\n }\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n unsigned int v2;\n int *v3;\n int v4;\n unsigned int v5;\n int v6;\n unsigned int v7;\n int v8;\n if (a2 > 0) {\n v2 = 0;\n v3 = &a1[a2];\n while (1) {\n while (1) {\n v4 = *a1;\n if (*a1 <= 0) break;\n ++v2;\n LABEL_4:\n if (v3 == ++a1) return v2;\n }\n v5 = -v4;\n if (v4 >= -9) goto LABEL_4;\n v6 = 0;\n do {\n v7 = v5 % 10;\n v8 = v5;\n v5 /= 10u;\n v6 += v7;\n } while (v8 > 99);\n ++a1;\n v2 += v6 > (int)v5;\n if (v3 == a1) return v2;\n }\n }\n return 0LL;\n}" + }, + { + "index": "HumanEval-C-109", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "bool func0(int *arr, int size) {\n int num = 0;\n if (size == 0) return true;\n for (int i = 1; i < size; i++)\n if (arr[i] < arr[i - 1]) num += 1;\n if (arr[size - 1] > arr[0]) num += 1;\n if (num < 2) return true;\n return false;\n}", + "test": "#include \n#include \n\nint main() {\n assert(func0((const int[]){3, 4, 5, 1, 2}, 5) == true);\n assert(func0((const int[]){3, 5, 10, 1, 2}, 5) == true);\n assert(func0((const int[]){4, 3, 1, 2}, 4) == false);\n assert(func0((const int[]){3, 5, 4, 1, 2}, 5) == false);\n assert(func0((const int[]){}, 0) == true);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\ncmp [rbp+var_1C], 0\njnz short loc_118C\nmov eax, 1\njmp short loc_120B\nloc_118C:\nmov [rbp+var_4], 1\njmp short loc_11CD\nloc_1195:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nshl rax, 2\nlea rcx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njge short loc_11C9\nadd [rbp+var_8], 1\nloc_11C9:\nadd [rbp+var_4], 1\nloc_11CD:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1195\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_18]\nmov eax, [rax]\ncmp edx, eax\njle short loc_11F9\nadd [rbp+var_8], 1\nloc_11F9:\ncmp [rbp+var_8], 1\njg short loc_1206\nmov eax, 1\njmp short loc_120B\nloc_1206:\nmov eax, 0\nloc_120B:\npop rbp\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(_DWORD *a1, int a2)\n{\n int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n if ( !a2 )\n return 1LL;\n for ( i = 1; i < a2; ++i )\n {\n if ( a1[i] < a1[i - 1] )\n ++v3;\n }\n if ( a1[a2 - 1] > *a1 )\n ++v3;\n return v3 <= 1;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\ncmp [rbp+var_1C], 0\njnz short loc_118C\nmov eax, 1\njmp short loc_120B\nloc_118C:\nmov [rbp+var_4], 1\njmp short loc_11CD\nloc_1195:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nshl rax, 2\nlea rcx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njge short loc_11C9\nadd [rbp+var_8], 1\nloc_11C9:\nadd [rbp+var_4], 1\nloc_11CD:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1195\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_18]\nmov eax, [rax]\ncmp edx, eax\njle short loc_11F9\nadd [rbp+var_8], 1\nloc_11F9:\ncmp [rbp+var_8], 1\njg short loc_1206\nmov eax, 1\njmp short loc_120B\nloc_1206:\nmov eax, 0\nloc_120B:\npop rbp\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1169(_DWORD *a1, int a2)\n{\n int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n if ( !a2 )\n return 1LL;\n for ( i = 1; i < a2; ++i )\n {\n if ( a1[i] < a1[i - 1] )\n ++v3;\n }\n if ( a1[a2 - 1] > *a1 )\n ++v3;\n return v3 <= 1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1169(uint32_t *a1, int a2) {\n int v3;\n int i;\n v3 = 0;\n if (!a2) return 1LL;\n for (i = 1; i < a2; ++i) {\n if (a1[i] < a1[i - 1]) ++v3;\n }\n if (a1[a2 - 1] > *a1) ++v3;\n return v3 <= 1;\n}", + "ida_pseudo_norm": "uint8_t func0(uint32_t *a1, int a2) {\n int v3;\n int i;\n v3 = 0;\n if (!a2) return 1LL;\n for (i = 1; i < a2; ++i) {\n if (a1[i] < a1[i - 1]) ++v3;\n }\n if (a1[a2 - 1] > *a1) ++v3;\n return v3 <= 1;\n}" + }, + { + "index": "HumanEval-C-109", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "bool func0(int *arr, int size) {\n int num = 0;\n if (size == 0) return true;\n for (int i = 1; i < size; i++)\n if (arr[i] < arr[i - 1]) num += 1;\n if (arr[size - 1] > arr[0]) num += 1;\n if (num < 2) return true;\n return false;\n}", + "test": "#include \n#include \n\nint main() {\n assert(func0((const int[]){3, 4, 5, 1, 2}, 5) == true);\n assert(func0((const int[]){3, 5, 10, 1, 2}, 5) == true);\n assert(func0((const int[]){4, 3, 1, 2}, 4) == false);\n assert(func0((const int[]){3, 5, 4, 1, 2}, 5) == false);\n assert(func0((const int[]){}, 0) == true);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmov eax, 1\ntest esi, esi\njz short locret_11B8\ncmp esi, 1\njle short loc_11B9\nmov rax, rdi\nlea edx, [rsi-2]\nlea r8, [rdi+rdx*4+4]\nmov edx, 0\nloc_118B:\nmov ecx, [rax]\ncmp [rax+4], ecx\nsetl cl\nmovzx ecx, cl\nadd edx, ecx\nadd rax, 4\ncmp rax, r8\njnz short loc_118B\nloc_11A1:\nmovsxd rsi, esi\nmov eax, [rdi]\ncmp [rdi+rsi*4-4], eax\nsetnle al\nmovzx eax, al\nadd edx, eax\ncmp edx, 1\nsetle al\nlocret_11B8:\nretn\nloc_11B9:\nmov edx, 0\njmp short loc_11A1", + "ida_pseudo": "bool __fastcall func0(_DWORD *a1, int a2)\n{\n bool result; // al\n _DWORD *v3; // rax\n int v4; // edx\n\n result = 1;\n if ( a2 )\n {\n if ( a2 <= 1 )\n {\n v4 = 0;\n }\n else\n {\n v3 = a1;\n v4 = 0;\n do\n {\n v4 += v3[1] < *v3;\n ++v3;\n }\n while ( v3 != &a1[a2 - 2 + 1] );\n }\n return (a1[a2 - 1] > *a1) + v4 <= 1;\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov eax, 1\ntest esi, esi\njz short locret_11B8\ncmp esi, 1\njle short loc_11B9\nmov rax, rdi\nlea edx, [rsi-2]\nlea r8, [rdi+rdx*4+4]\nmov edx, 0\nloc_118B:\nmov ecx, [rax]\ncmp [rax+4], ecx\nsetl cl\nmovzx ecx, cl\nadd edx, ecx\nadd rax, 4\ncmp rax, r8\njnz short loc_118B\nloc_11A1:\nmovsxd rsi, esi\nmov eax, [rdi]\ncmp [rdi+rsi*4-4], eax\nsetnle al\nmovzx eax, al\nadd edx, eax\ncmp edx, 1\nsetle al\nlocret_11B8:\nretn\nloc_11B9:\nmov edx, 0\njmp short loc_11A1", + "ida_strip_pseudo": "bool __fastcall sub_1169(_DWORD *a1, int a2)\n{\n bool result; // al\n _DWORD *v3; // rax\n int v4; // edx\n\n result = 1;\n if ( a2 )\n {\n if ( a2 <= 1 )\n {\n v4 = 0;\n }\n else\n {\n v3 = a1;\n v4 = 0;\n do\n {\n v4 += v3[1] < *v3;\n ++v3;\n }\n while ( v3 != &a1[a2 - 2 + 1] );\n }\n return (a1[a2 - 1] > *a1) + v4 <= 1;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_1169(uint32_t *a1, int a2) {\n bool result;\n uint32_t *v3;\n int v4;\n result = 1;\n if (a2) {\n if (a2 <= 1) {\n v4 = 0;\n } else {\n v3 = a1;\n v4 = 0;\n do {\n v4 += v3[1] < *v3;\n ++v3;\n } while (v3 != &a1[a2 - 2 + 1]);\n }\n return (a1[a2 - 1] > *a1) + v4 <= 1;\n }\n return result;\n}", + "ida_pseudo_norm": "bool func0(uint32_t *a1, int a2) {\n bool result;\n uint32_t *v3;\n int v4;\n result = 1;\n if (a2) {\n if (a2 <= 1) {\n v4 = 0;\n } else {\n v3 = a1;\n v4 = 0;\n do {\n v4 += v3[1] < *v3;\n ++v3;\n } while (v3 != &a1[a2 - 2 + 1]);\n }\n return (a1[a2 - 1] > *a1) + v4 <= 1;\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-109", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "bool func0(int *arr, int size) {\n int num = 0;\n if (size == 0) return true;\n for (int i = 1; i < size; i++)\n if (arr[i] < arr[i - 1]) num += 1;\n if (arr[size - 1] > arr[0]) num += 1;\n if (num < 2) return true;\n return false;\n}", + "test": "#include \n#include \n\nint main() {\n assert(func0((const int[]){3, 4, 5, 1, 2}, 5) == true);\n assert(func0((const int[]){3, 5, 10, 1, 2}, 5) == true);\n assert(func0((const int[]){4, 3, 1, 2}, 4) == false);\n assert(func0((const int[]){3, 5, 4, 1, 2}, 5) == false);\n assert(func0((const int[]){}, 0) == true);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0_part_0:\ncmp esi, 1\njle short loc_12F0\nlea ecx, [rsi-2]\nmov edx, [rdi]\nlea rax, [rdi+4]\nlea r9, [rdi+rcx*4+8]\nxor ecx, ecx\nnop dword ptr [rax]\nloc_12B8:\nmov r8d, edx\nmov edx, [rax]\ncmp r8d, edx\nsetnle r8b\nadd rax, 4\nmovzx r8d, r8b\nadd ecx, r8d\ncmp rax, r9\njnz short loc_12B8\nloc_12D4:\nmovsxd rsi, esi\nmov eax, [rdi]\ncmp [rdi+rsi*4-4], eax\nsetnle al\nmovzx eax, al\nadd ecx, eax\ncmp ecx, 1\nsetle al\nretn\nloc_12F0:\nxor ecx, ecx\njmp short loc_12D4", + "ida_pseudo": "bool __fastcall func0_part_0(int *a1, int a2)\n{\n int v2; // edx\n int *v3; // rax\n int v4; // ecx\n int v5; // r8d\n\n if ( a2 <= 1 )\n {\n v4 = 0;\n }\n else\n {\n v2 = *a1;\n v3 = a1 + 1;\n v4 = 0;\n do\n {\n v5 = v2;\n v2 = *v3++;\n v4 += v5 > v2;\n }\n while ( v3 != &a1[a2 - 2 + 2] );\n }\n return (a1[a2 - 1] > *a1) + v4 <= 1;\n}", + "ida_strip_asm": "sub_12A0:\ncmp esi, 1\njle short loc_12F0\nlea ecx, [rsi-2]\nmov edx, [rdi]\nlea rax, [rdi+4]\nlea r9, [rdi+rcx*4+8]\nxor ecx, ecx\nnop dword ptr [rax]\nloc_12B8:\nmov r8d, edx\nmov edx, [rax]\ncmp r8d, edx\nsetnle r8b\nadd rax, 4\nmovzx r8d, r8b\nadd ecx, r8d\ncmp rax, r9\njnz short loc_12B8\nloc_12D4:\nmovsxd rsi, esi\nmov eax, [rdi]\ncmp [rdi+rsi*4-4], eax\nsetnle al\nmovzx eax, al\nadd ecx, eax\ncmp ecx, 1\nsetle al\nretn\nloc_12F0:\nxor ecx, ecx\njmp short loc_12D4", + "ida_strip_pseudo": "bool __fastcall sub_12A0(int *a1, int a2)\n{\n int v2; // edx\n int *v3; // rax\n int v4; // ecx\n int v5; // r8d\n\n if ( a2 <= 1 )\n {\n v4 = 0;\n }\n else\n {\n v2 = *a1;\n v3 = a1 + 1;\n v4 = 0;\n do\n {\n v5 = v2;\n v2 = *v3++;\n v4 += v5 > v2;\n }\n while ( v3 != &a1[a2 - 2 + 2] );\n }\n return (a1[a2 - 1] > *a1) + v4 <= 1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_12A0(int *a1, int a2) {\n int v2;\n int *v3;\n int v4;\n int v5;\n if (a2 <= 1) {\n v4 = 0;\n } else {\n v2 = *a1;\n v3 = a1 + 1;\n v4 = 0;\n do {\n v5 = v2;\n v2 = *v3++;\n v4 += v5 > v2;\n } while (v3 != &a1[a2 - 2 + 2]);\n }\n return (a1[a2 - 1] > *a1) + v4 <= 1;\n}", + "ida_pseudo_norm": "bool func0_part_0(int *a1, int a2) {\n int v2;\n int *v3;\n int v4;\n int v5;\n if (a2 <= 1) {\n v4 = 0;\n } else {\n v2 = *a1;\n v3 = a1 + 1;\n v4 = 0;\n do {\n v5 = v2;\n v2 = *v3++;\n v4 += v5 > v2;\n } while (v3 != &a1[a2 - 2 + 2]);\n }\n return (a1[a2 - 1] > *a1) + v4 <= 1;\n}" + }, + { + "index": "HumanEval-C-109", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "bool func0(int *arr, int size) {\n int num = 0;\n if (size == 0) return true;\n for (int i = 1; i < size; i++)\n if (arr[i] < arr[i - 1]) num += 1;\n if (arr[size - 1] > arr[0]) num += 1;\n if (num < 2) return true;\n return false;\n}", + "test": "#include \n#include \n\nint main() {\n assert(func0((const int[]){3, 4, 5, 1, 2}, 5) == true);\n assert(func0((const int[]){3, 5, 10, 1, 2}, 5) == true);\n assert(func0((const int[]){4, 3, 1, 2}, 4) == false);\n assert(func0((const int[]){3, 5, 4, 1, 2}, 5) == false);\n assert(func0((const int[]){}, 0) == true);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0_part_0:\nmov rdx, rdi\ncmp esi, 1\njle loc_1460\nlea eax, [rsi-2]\nlea edi, [rsi-1]\ncmp eax, 2\njbe loc_1467\nmov ecx, edi\nmov rax, rdx\npxor xmm1, xmm1\nshr ecx, 2\nshl rcx, 4\nadd rcx, rdx\nxchg ax, ax\nloc_12E0:\nmovdqu xmm0, xmmword ptr [rax]\nmovdqu xmm2, xmmword ptr [rax+4]\nadd rax, 10h\npcmpgtd xmm0, xmm2\npsubd xmm1, xmm0\ncmp rax, rcx\njnz short loc_12E0\nmovdqa xmm0, xmm1\nmov ecx, edi\npsrldq xmm0, 8\nand ecx, 0FFFFFFFCh\npaddd xmm1, xmm0\nadd ecx, 1\nmovdqa xmm0, xmm1\npsrldq xmm0, 4\npaddd xmm1, xmm0\nmovd eax, xmm1\ntest dil, 3\njz loc_13B3\nloc_132A:\nmovsxd r8, ecx\nlea r10d, [rcx+1]\nlea r9, ds:0[r8*4]\nlea r11, [rdx+r9]\ncmp r10d, edi\njge short loc_1378\ncmp esi, ecx\njle short loc_1378\nmov r8d, [r11]\ncmp [r11-4], r8d\njle short loc_1352\nadd eax, 1\nloc_1352:\nmov r10d, [rdx+r9+4]\ncmp r8d, r10d\nsetnle r8b\nmovzx r8d, r8b\nadd eax, r8d\nlea r8d, [rcx+3]\ncmp edi, r8d\njg short loc_13D0\nadd ecx, 2\nmovsxd r8, ecx\nlea r10d, [rcx+1]\nloc_1378:\nmov r9d, [rdx+r8*4]\nlea rdi, ds:0[r8*4]\ncmp r9d, [rdx+r8*4-4]\njl loc_1430\nloc_138F:\ncmp esi, r10d\njle short loc_13B3\ncmp r9d, [rdx+rdi+4]\njg loc_1440\nloc_139F:\nadd ecx, 2\ncmp esi, ecx\njle short loc_13B3\nmov ecx, [rdx+rdi+8]\ncmp [rdx+rdi+4], ecx\njle short loc_13B3\nadd eax, 1\nloc_13B3:\nmovsxd rsi, esi\nmov edi, [rdx]\ncmp [rdx+rsi*4-4], edi\nsetnle dl\nmovzx edx, dl\nadd eax, edx\ncmp eax, 1\nsetle al\nretn\nloc_13D0:\nmov r8d, [rdx+r9+8]\ncmp r10d, r8d\nsetnle r10b\nmovzx r10d, r10b\nadd eax, r10d\nmov r10d, [rdx+r9+0Ch]\ncmp r8d, r10d\nsetnle r8b\nmovzx r8d, r8b\nadd eax, r8d\nlea r8d, [rcx+5]\ncmp edi, r8d\njle short loc_1450\nmov edi, [rdx+r9+10h]\nxor r8d, r8d\ncmp edi, r10d\nsetl r8b\nadd eax, r8d\ncmp [rdx+r9+14h], edi\njge short loc_141B\nadd eax, 1\nloc_141B:\nadd ecx, 6\nmovsxd r8, ecx\nlea r10d, [rcx+1]\njmp loc_1378\nloc_1430:\nadd eax, 1\njmp loc_138F\nloc_1440:\nadd eax, 1\njmp loc_139F\nloc_1450:\nadd ecx, 4\nmovsxd r8, ecx\nlea r10d, [rcx+1]\njmp loc_1378\nloc_1460:\nxor eax, eax\njmp loc_13B3\nloc_1467:\nxor eax, eax\nmov ecx, 1\njmp loc_132A", + "ida_pseudo": "bool __fastcall func0_part_0(_DWORD *a1, int a2)\n{\n int v3; // edi\n _DWORD *v4; // rax\n __m128i v5; // xmm1\n __m128i v6; // xmm0\n __m128i v7; // xmm2\n __m128i v8; // xmm1\n signed int v9; // ecx\n int v10; // eax\n __int64 v11; // r8\n int v12; // r10d\n __int64 v13; // r9\n _DWORD *v14; // r11\n int v15; // r10d\n int v16; // r9d\n __int64 v17; // rdi\n int v19; // r8d\n int v20; // eax\n int v21; // r10d\n int v22; // edi\n\n if ( a2 <= 1 )\n {\n v10 = 0;\n return (a1[a2 - 1] > *a1) + v10 <= 1;\n }\n v3 = a2 - 1;\n if ( (unsigned int)(a2 - 2) <= 2 )\n {\n v10 = 0;\n v9 = 1;\n }\n else\n {\n v4 = a1;\n v5 = 0LL;\n do\n {\n v6 = _mm_loadu_si128((const __m128i *)v4);\n v7 = _mm_loadu_si128((const __m128i *)(v4 + 1));\n v4 += 4;\n v5 = _mm_sub_epi32(v5, _mm_cmpgt_epi32(v6, v7));\n }\n while ( v4 != &a1[4 * ((unsigned int)v3 >> 2)] );\n v8 = _mm_add_epi32(v5, _mm_srli_si128(v5, 8));\n v9 = (v3 & 0xFFFFFFFC) + 1;\n v10 = _mm_cvtsi128_si32(_mm_add_epi32(v8, _mm_srli_si128(v8, 4)));\n if ( (v3 & 3) == 0 )\n return (a1[a2 - 1] > *a1) + v10 <= 1;\n }\n v11 = v9;\n v12 = v9 + 1;\n v13 = v9;\n v14 = &a1[v13];\n if ( v9 + 1 < v3 && a2 > v9 )\n {\n if ( *(v14 - 1) > *v14 )\n ++v10;\n v15 = a1[v13 + 1];\n v10 += *v14 > v15;\n if ( v3 > v9 + 3 )\n {\n v19 = a1[v13 + 2];\n v20 = (v15 > v19) + v10;\n v21 = a1[v13 + 3];\n v10 = (v19 > v21) + v20;\n if ( v3 <= v9 + 5 )\n {\n v9 += 4;\n v11 = v9;\n v12 = v9 + 1;\n }\n else\n {\n v22 = a1[v13 + 4];\n v10 += v22 < v21;\n if ( a1[v13 + 5] < v22 )\n ++v10;\n v9 += 6;\n v11 = v9;\n v12 = v9 + 1;\n }\n }\n else\n {\n v9 += 2;\n v11 = v9;\n v12 = v9 + 1;\n }\n }\n v16 = a1[v11];\n v17 = v11;\n if ( v16 < a1[v11 - 1] )\n ++v10;\n if ( a2 > v12 )\n {\n if ( v16 > a1[v17 + 1] )\n ++v10;\n if ( a2 > v9 + 2 && a1[v17 + 1] > a1[v17 + 2] )\n ++v10;\n }\n return (a1[a2 - 1] > *a1) + v10 <= 1;\n}", + "ida_strip_asm": "sub_12B0:\nmov rdx, rdi\ncmp esi, 1\njle loc_1460\nlea eax, [rsi-2]\nlea edi, [rsi-1]\ncmp eax, 2\njbe loc_1467\nmov ecx, edi\nmov rax, rdx\npxor xmm1, xmm1\nshr ecx, 2\nshl rcx, 4\nadd rcx, rdx\nxchg ax, ax\nloc_12E0:\nmovdqu xmm0, xmmword ptr [rax]\nmovdqu xmm2, xmmword ptr [rax+4]\nadd rax, 10h\npcmpgtd xmm0, xmm2\npsubd xmm1, xmm0\ncmp rax, rcx\njnz short loc_12E0\nmovdqa xmm0, xmm1\nmov ecx, edi\npsrldq xmm0, 8\nand ecx, 0FFFFFFFCh\npaddd xmm1, xmm0\nadd ecx, 1\nmovdqa xmm0, xmm1\npsrldq xmm0, 4\npaddd xmm1, xmm0\nmovd eax, xmm1\ntest dil, 3\njz loc_13B3\nloc_132A:\nmovsxd r8, ecx\nlea r10d, [rcx+1]\nlea r9, ds:0[r8*4]\nlea r11, [rdx+r9]\ncmp r10d, edi\njge short loc_1378\ncmp esi, ecx\njle short loc_1378\nmov r8d, [r11]\ncmp [r11-4], r8d\njle short loc_1352\nadd eax, 1\nloc_1352:\nmov r10d, [rdx+r9+4]\ncmp r8d, r10d\nsetnle r8b\nmovzx r8d, r8b\nadd eax, r8d\nlea r8d, [rcx+3]\ncmp edi, r8d\njg short loc_13D0\nadd ecx, 2\nmovsxd r8, ecx\nlea r10d, [rcx+1]\nloc_1378:\nmov r9d, [rdx+r8*4]\nlea rdi, ds:0[r8*4]\ncmp r9d, [rdx+r8*4-4]\njl loc_1430\nloc_138F:\ncmp esi, r10d\njle short loc_13B3\ncmp r9d, [rdx+rdi+4]\njg loc_1440\nloc_139F:\nadd ecx, 2\ncmp esi, ecx\njle short loc_13B3\nmov ecx, [rdx+rdi+8]\ncmp [rdx+rdi+4], ecx\njle short loc_13B3\nadd eax, 1\nloc_13B3:\nmovsxd rsi, esi\nmov edi, [rdx]\ncmp [rdx+rsi*4-4], edi\nsetnle dl\nmovzx edx, dl\nadd eax, edx\ncmp eax, 1\nsetle al\nretn\nloc_13D0:\nmov r8d, [rdx+r9+8]\ncmp r10d, r8d\nsetnle r10b\nmovzx r10d, r10b\nadd eax, r10d\nmov r10d, [rdx+r9+0Ch]\ncmp r8d, r10d\nsetnle r8b\nmovzx r8d, r8b\nadd eax, r8d\nlea r8d, [rcx+5]\ncmp edi, r8d\njle short loc_1450\nmov edi, [rdx+r9+10h]\nxor r8d, r8d\ncmp edi, r10d\nsetl r8b\nadd eax, r8d\ncmp [rdx+r9+14h], edi\njge short loc_141B\nadd eax, 1\nloc_141B:\nadd ecx, 6\nmovsxd r8, ecx\nlea r10d, [rcx+1]\njmp loc_1378\nloc_1430:\nadd eax, 1\njmp loc_138F\nloc_1440:\nadd eax, 1\njmp loc_139F\nloc_1450:\nadd ecx, 4\nmovsxd r8, ecx\nlea r10d, [rcx+1]\njmp loc_1378\nloc_1460:\nxor eax, eax\njmp loc_13B3\nloc_1467:\nxor eax, eax\nmov ecx, 1\njmp loc_132A", + "ida_strip_pseudo": "bool __fastcall sub_12B0(_DWORD *a1, int a2)\n{\n int v3; // edi\n _DWORD *v4; // rax\n __m128i v5; // xmm1\n __m128i v6; // xmm0\n __m128i v7; // xmm2\n __m128i v8; // xmm1\n signed int v9; // ecx\n int v10; // eax\n __int64 v11; // r8\n int v12; // r10d\n __int64 v13; // r9\n _DWORD *v14; // r11\n int v15; // r10d\n int v16; // r9d\n __int64 v17; // rdi\n int v19; // r8d\n int v20; // eax\n int v21; // r10d\n int v22; // edi\n\n if ( a2 <= 1 )\n {\n v10 = 0;\n return (a1[a2 - 1] > *a1) + v10 <= 1;\n }\n v3 = a2 - 1;\n if ( (unsigned int)(a2 - 2) <= 2 )\n {\n v10 = 0;\n v9 = 1;\n }\n else\n {\n v4 = a1;\n v5 = 0LL;\n do\n {\n v6 = _mm_loadu_si128((const __m128i *)v4);\n v7 = _mm_loadu_si128((const __m128i *)(v4 + 1));\n v4 += 4;\n v5 = _mm_sub_epi32(v5, _mm_cmpgt_epi32(v6, v7));\n }\n while ( v4 != &a1[4 * ((unsigned int)v3 >> 2)] );\n v8 = _mm_add_epi32(v5, _mm_srli_si128(v5, 8));\n v9 = (v3 & 0xFFFFFFFC) + 1;\n v10 = _mm_cvtsi128_si32(_mm_add_epi32(v8, _mm_srli_si128(v8, 4)));\n if ( (v3 & 3) == 0 )\n return (a1[a2 - 1] > *a1) + v10 <= 1;\n }\n v11 = v9;\n v12 = v9 + 1;\n v13 = v9;\n v14 = &a1[v13];\n if ( v9 + 1 < v3 && a2 > v9 )\n {\n if ( *(v14 - 1) > *v14 )\n ++v10;\n v15 = a1[v13 + 1];\n v10 += *v14 > v15;\n if ( v3 > v9 + 3 )\n {\n v19 = a1[v13 + 2];\n v20 = (v15 > v19) + v10;\n v21 = a1[v13 + 3];\n v10 = (v19 > v21) + v20;\n if ( v3 <= v9 + 5 )\n {\n v9 += 4;\n v11 = v9;\n v12 = v9 + 1;\n }\n else\n {\n v22 = a1[v13 + 4];\n v10 += v22 < v21;\n if ( a1[v13 + 5] < v22 )\n ++v10;\n v9 += 6;\n v11 = v9;\n v12 = v9 + 1;\n }\n }\n else\n {\n v9 += 2;\n v11 = v9;\n v12 = v9 + 1;\n }\n }\n v16 = a1[v11];\n v17 = v11;\n if ( v16 < a1[v11 - 1] )\n ++v10;\n if ( a2 > v12 )\n {\n if ( v16 > a1[v17 + 1] )\n ++v10;\n if ( a2 > v9 + 2 && a1[v17 + 1] > a1[v17 + 2] )\n ++v10;\n }\n return (a1[a2 - 1] > *a1) + v10 <= 1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_12B0(uint32_t *a1, int a2) {\n int v3;\n uint32_t *v4;\n __m128i v5;\n __m128i v6;\n __m128i v7;\n __m128i v8;\n signed int v9;\n int v10;\n long long v11;\n int v12;\n long long v13;\n uint32_t *v14;\n int v15;\n int v16;\n long long v17;\n int v19;\n int v20;\n int v21;\n int v22;\n if (a2 <= 1) {\n v10 = 0;\n return (a1[a2 - 1] > *a1) + v10 <= 1;\n }\n v3 = a2 - 1;\n if ((unsigned int)(a2 - 2) <= 2) {\n v10 = 0;\n v9 = 1;\n } else {\n v4 = a1;\n v5 = 0LL;\n do {\n v6 = _mm_loadu_si128((const __m128i *)v4);\n v7 = _mm_loadu_si128((const __m128i *)(v4 + 1));\n v4 += 4;\n v5 = _mm_sub_epi32(v5, _mm_cmpgt_epi32(v6, v7));\n } while (v4 != &a1[4 * ((unsigned int)v3 >> 2)]);\n v8 = _mm_add_epi32(v5, _mm_srli_si128(v5, 8));\n v9 = (v3 & 4294967292) + 1;\n v10 = _mm_cvtsi128_si32(_mm_add_epi32(v8, _mm_srli_si128(v8, 4)));\n if ((v3 & 3) == 0) return (a1[a2 - 1] > *a1) + v10 <= 1;\n }\n v11 = v9;\n v12 = v9 + 1;\n v13 = v9;\n v14 = &a1[v13];\n if (v9 + 1 < v3 && a2 > v9) {\n if (*(v14 - 1) > *v14) ++v10;\n v15 = a1[v13 + 1];\n v10 += *v14 > v15;\n if (v3 > v9 + 3) {\n v19 = a1[v13 + 2];\n v20 = (v15 > v19) + v10;\n v21 = a1[v13 + 3];\n v10 = (v19 > v21) + v20;\n if (v3 <= v9 + 5) {\n v9 += 4;\n v11 = v9;\n v12 = v9 + 1;\n } else {\n v22 = a1[v13 + 4];\n v10 += v22 < v21;\n if (a1[v13 + 5] < v22) ++v10;\n v9 += 6;\n v11 = v9;\n v12 = v9 + 1;\n }\n } else {\n v9 += 2;\n v11 = v9;\n v12 = v9 + 1;\n }\n }\n v16 = a1[v11];\n v17 = v11;\n if (v16 < a1[v11 - 1]) ++v10;\n if (a2 > v12) {\n if (v16 > a1[v17 + 1]) ++v10;\n if (a2 > v9 + 2 && a1[v17 + 1] > a1[v17 + 2]) ++v10;\n }\n return (a1[a2 - 1] > *a1) + v10 <= 1;\n}", + "ida_pseudo_norm": "bool func0_part_0(uint32_t *a1, int a2) {\n int v3;\n uint32_t *v4;\n __m128i v5;\n __m128i v6;\n __m128i v7;\n __m128i v8;\n signed int v9;\n int v10;\n long long v11;\n int v12;\n long long v13;\n uint32_t *v14;\n int v15;\n int v16;\n long long v17;\n int v19;\n int v20;\n int v21;\n int v22;\n if (a2 <= 1) {\n v10 = 0;\n return (a1[a2 - 1] > *a1) + v10 <= 1;\n }\n v3 = a2 - 1;\n if ((unsigned int)(a2 - 2) <= 2) {\n v10 = 0;\n v9 = 1;\n } else {\n v4 = a1;\n v5 = 0LL;\n do {\n v6 = _mm_loadu_si128((const __m128i *)v4);\n v7 = _mm_loadu_si128((const __m128i *)(v4 + 1));\n v4 += 4;\n v5 = _mm_sub_epi32(v5, _mm_cmpgt_epi32(v6, v7));\n } while (v4 != &a1[4 * ((unsigned int)v3 >> 2)]);\n v8 = _mm_add_epi32(v5, _mm_srli_si128(v5, 8));\n v9 = (v3 & 4294967292) + 1;\n v10 = _mm_cvtsi128_si32(_mm_add_epi32(v8, _mm_srli_si128(v8, 4)));\n if ((v3 & 3) == 0) return (a1[a2 - 1] > *a1) + v10 <= 1;\n }\n v11 = v9;\n v12 = v9 + 1;\n v13 = v9;\n v14 = &a1[v13];\n if (v9 + 1 < v3 && a2 > v9) {\n if (*(v14 - 1) > *v14) ++v10;\n v15 = a1[v13 + 1];\n v10 += *v14 > v15;\n if (v3 > v9 + 3) {\n v19 = a1[v13 + 2];\n v20 = (v15 > v19) + v10;\n v21 = a1[v13 + 3];\n v10 = (v19 > v21) + v20;\n if (v3 <= v9 + 5) {\n v9 += 4;\n v11 = v9;\n v12 = v9 + 1;\n } else {\n v22 = a1[v13 + 4];\n v10 += v22 < v21;\n if (a1[v13 + 5] < v22) ++v10;\n v9 += 6;\n v11 = v9;\n v12 = v9 + 1;\n }\n } else {\n v9 += 2;\n v11 = v9;\n v12 = v9 + 1;\n }\n }\n v16 = a1[v11];\n v17 = v11;\n if (v16 < a1[v11 - 1]) ++v10;\n if (a2 > v12) {\n if (v16 > a1[v17 + 1]) ++v10;\n if (a2 > v9 + 2 && a1[v17 + 1] > a1[v17 + 2]) ++v10;\n }\n return (a1[a2 - 1] > *a1) + v10 <= 1;\n}" + }, + { + "index": "HumanEval-C-110", + "func_name": "func0", + "func_dep": "#include \n", + "func": "const char *func0(int *lst1, int size1, int *lst2, int size2) {\n int num = 0;\n for (int i = 0; i < size1; i++)\n if (lst1[i] % 2 == 0) num += 1;\n for (int i = 0; i < size2; i++)\n if (lst2[i] % 2 == 0) num += 1;\n if (num >= size1) return \"YES\";\n return \"NO\";\n}", + "test": "#include \n#include \n\nint main() {\n assert(strcmp(func0((const int[]){1, 2, 3, 4}, 4, (const int[]){1, 2, 3, 4}, 4), \"YES\") == 0);\n assert(strcmp(func0((const int[]){1, 2, 3, 4}, 4, (const int[]){1, 5, 3, 4}, 4), \"NO\") == 0);\n assert(strcmp(func0((const int[]){1, 2, 3, 4}, 4, (const int[]){2, 1, 4, 3}, 4), \"YES\") == 0);\n assert(strcmp(func0((const int[]){5, 7, 3}, 3, (const int[]){2, 6, 4}, 3), \"YES\") == 0);\n assert(strcmp(func0((const int[]){5, 7, 3}, 3, (const int[]){2, 6, 3}, 3), \"NO\") == 0);\n assert(strcmp(func0((const int[]){3, 2, 6, 1, 8, 9}, 6, (const int[]){3, 5, 5, 1, 1, 1}, 6), \"NO\") == 0);\n assert(strcmp(func0((const int[]){100, 200}, 2, (const int[]){200, 200}, 2), \"YES\") == 0);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_11D4\nloc_11AF:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njnz short loc_11D0\nadd [rbp+var_C], 1\nloc_11D0:\nadd [rbp+var_8], 1\nloc_11D4:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_11AF\nmov [rbp+var_4], 0\njmp short loc_120A\nloc_11E5:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njnz short loc_1206\nadd [rbp+var_C], 1\nloc_1206:\nadd [rbp+var_4], 1\nloc_120A:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_20]\njl short loc_11E5\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_1223\nlea rax, s2; \"YES\"\njmp short loc_122A\nloc_1223:\nlea rax, aNo; \"NO\"\nloc_122A:\npop rbp\nretn", + "ida_pseudo": "const char *__fastcall func0(__int64 a1, int a2, __int64 a3, int a4)\n{\n int v5; // [rsp+1Ch] [rbp-Ch]\n int i; // [rsp+20h] [rbp-8h]\n int j; // [rsp+24h] [rbp-4h]\n\n v5 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( (*(_DWORD *)(4LL * i + a1) & 1) == 0 )\n ++v5;\n }\n for ( j = 0; j < a4; ++j )\n {\n if ( (*(_DWORD *)(4LL * j + a3) & 1) == 0 )\n ++v5;\n }\n if ( v5 < a2 )\n return \"NO\";\n else\n return \"YES\";\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_11D4\nloc_11AF:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njnz short loc_11D0\nadd [rbp+var_C], 1\nloc_11D0:\nadd [rbp+var_8], 1\nloc_11D4:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_11AF\nmov [rbp+var_4], 0\njmp short loc_120A\nloc_11E5:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njnz short loc_1206\nadd [rbp+var_C], 1\nloc_1206:\nadd [rbp+var_4], 1\nloc_120A:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_20]\njl short loc_11E5\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_1223\nlea rax, s2; \"YES\"\njmp short loc_122A\nloc_1223:\nlea rax, aNo; \"NO\"\nloc_122A:\npop rbp\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1189(__int64 a1, int a2, __int64 a3, int a4)\n{\n int v5; // [rsp+1Ch] [rbp-Ch]\n int i; // [rsp+20h] [rbp-8h]\n int j; // [rsp+24h] [rbp-4h]\n\n v5 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( (*(_DWORD *)(4LL * i + a1) & 1) == 0 )\n ++v5;\n }\n for ( j = 0; j < a4; ++j )\n {\n if ( (*(_DWORD *)(4LL * j + a3) & 1) == 0 )\n ++v5;\n }\n if ( v5 < a2 )\n return \"NO\";\n else\n return \"YES\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1189(long long a1, int a2, long long a3, int a4) {\n int v5;\n int i;\n int j;\n v5 = 0;\n for (i = 0; i < a2; ++i) {\n if ((*(uint32_t *)(4LL * i + a1) & 1) == 0) ++v5;\n }\n for (j = 0; j < a4; ++j) {\n if ((*(uint32_t *)(4LL * j + a3) & 1) == 0) ++v5;\n }\n if (v5 < a2)\n return \"NO\";\n else\n return \"YES\";\n}", + "ida_pseudo_norm": "const char *func0(long long a1, int a2, long long a3, int a4) {\n int v5;\n int i;\n int j;\n v5 = 0;\n for (i = 0; i < a2; ++i) {\n if ((*(uint32_t *)(4LL * i + a1) & 1) == 0) ++v5;\n }\n for (j = 0; j < a4; ++j) {\n if ((*(uint32_t *)(4LL * j + a3) & 1) == 0) ++v5;\n }\n if (v5 < a2)\n return \"NO\";\n else\n return \"YES\";\n}" + }, + { + "index": "HumanEval-C-110", + "func_name": "func0", + "func_dep": "#include \n", + "func": "const char *func0(int *lst1, int size1, int *lst2, int size2) {\n int num = 0;\n for (int i = 0; i < size1; i++)\n if (lst1[i] % 2 == 0) num += 1;\n for (int i = 0; i < size2; i++)\n if (lst2[i] % 2 == 0) num += 1;\n if (num >= size1) return \"YES\";\n return \"NO\";\n}", + "test": "#include \n#include \n\nint main() {\n assert(strcmp(func0((const int[]){1, 2, 3, 4}, 4, (const int[]){1, 2, 3, 4}, 4), \"YES\") == 0);\n assert(strcmp(func0((const int[]){1, 2, 3, 4}, 4, (const int[]){1, 5, 3, 4}, 4), \"NO\") == 0);\n assert(strcmp(func0((const int[]){1, 2, 3, 4}, 4, (const int[]){2, 1, 4, 3}, 4), \"YES\") == 0);\n assert(strcmp(func0((const int[]){5, 7, 3}, 3, (const int[]){2, 6, 4}, 3), \"YES\") == 0);\n assert(strcmp(func0((const int[]){5, 7, 3}, 3, (const int[]){2, 6, 3}, 3), \"NO\") == 0);\n assert(strcmp(func0((const int[]){3, 2, 6, 1, 8, 9}, 6, (const int[]){3, 5, 5, 1, 1, 1}, 6), \"NO\") == 0);\n assert(strcmp(func0((const int[]){100, 200}, 2, (const int[]){200, 200}, 2), \"YES\") == 0);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11EA\nmov r8, rdi\nmovsxd rax, esi\nlea r9, [rdi+rax*4]\nmov eax, 0\nloc_11A0:\nmov edi, [r8]\nand edi, 1\ncmp edi, 1\nadc eax, 0\nadd r8, 4\ncmp r8, r9\njnz short loc_11A0\ntest ecx, ecx\njle short loc_11D5\nloc_11B9:\nmov edi, 0\nloc_11BE:\nmov r8d, [rdx+rdi*4]\nand r8d, 1\ncmp r8d, 1\nadc eax, 0\nadd rdi, 1\ncmp ecx, edi\njg short loc_11BE\nloc_11D5:\ncmp esi, eax\nlea rax, s2; \"YES\"\nlea rdx, aNo; \"NO\"\ncmovg rax, rdx\nretn\nloc_11EA:\nmov eax, 0\ntest ecx, ecx\njg short loc_11B9\nlea rax, s2; \"YES\"\nretn", + "ida_pseudo": "const char *__fastcall func0(_DWORD *a1, int a2, __int64 a3, int a4)\n{\n _DWORD *v4; // r8\n int v5; // eax\n __int64 v6; // rdi\n bool v7; // cc\n const char *result; // rax\n\n if ( a2 <= 0 )\n {\n v5 = 0;\n if ( a4 <= 0 )\n return \"YES\";\n }\n else\n {\n v4 = a1;\n v5 = 0;\n do\n v5 += (*v4++ & 1) == 0;\n while ( v4 != &a1[a2] );\n if ( a4 <= 0 )\n goto LABEL_7;\n }\n v6 = 0LL;\n do\n v5 += (*(_DWORD *)(a3 + 4 * v6++) & 1) == 0;\n while ( a4 > (int)v6 );\nLABEL_7:\n v7 = a2 <= v5;\n result = \"YES\";\n if ( !v7 )\n return \"NO\";\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\ntest esi, esi\njle short loc_11EA\nmov r8, rdi\nmovsxd rax, esi\nlea r9, [rdi+rax*4]\nmov eax, 0\nloc_11A0:\nmov edi, [r8]\nand edi, 1\ncmp edi, 1\nadc eax, 0\nadd r8, 4\ncmp r8, r9\njnz short loc_11A0\ntest ecx, ecx\njle short loc_11D5\nloc_11B9:\nmov edi, 0\nloc_11BE:\nmov r8d, [rdx+rdi*4]\nand r8d, 1\ncmp r8d, 1\nadc eax, 0\nadd rdi, 1\ncmp ecx, edi\njg short loc_11BE\nloc_11D5:\ncmp esi, eax\nlea rax, s2; \"YES\"\nlea rdx, aNo; \"NO\"\ncmovg rax, rdx\nretn\nloc_11EA:\nmov eax, 0\ntest ecx, ecx\njg short loc_11B9\nlea rax, s2; \"YES\"\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1189(_DWORD *a1, int a2, __int64 a3, int a4)\n{\n _DWORD *v4; // r8\n int v5; // eax\n __int64 v6; // rdi\n bool v7; // cc\n const char *result; // rax\n\n if ( a2 <= 0 )\n {\n v5 = 0;\n if ( a4 <= 0 )\n return \"YES\";\n }\n else\n {\n v4 = a1;\n v5 = 0;\n do\n v5 += (*v4++ & 1) == 0;\n while ( v4 != &a1[a2] );\n if ( a4 <= 0 )\n goto LABEL_7;\n }\n v6 = 0LL;\n do\n v5 += (*(_DWORD *)(a3 + 4 * v6++) & 1) == 0;\n while ( a4 > (int)v6 );\nLABEL_7:\n v7 = a2 <= v5;\n result = \"YES\";\n if ( !v7 )\n return \"NO\";\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1189(uint32_t *a1, int a2, long long a3, int a4) {\n uint32_t *v4;\n int v5;\n long long v6;\n bool v7;\n const char *result;\n if (a2 <= 0) {\n v5 = 0;\n if (a4 <= 0) return \"YES\";\n } else {\n v4 = a1;\n v5 = 0;\n do\n v5 += (*v4++ & 1) == 0;\n while (v4 != &a1[a2]);\n if (a4 <= 0) goto LABEL_7;\n }\n v6 = 0LL;\n do\n v5 += (*(uint32_t *)(a3 + 4 * v6++) & 1) == 0;\n while (a4 > (int)v6);\nLABEL_7:\n v7 = a2 <= v5;\n result = \"YES\";\n if (!v7) return \"NO\";\n return result;\n}", + "ida_pseudo_norm": "const char *func0(uint32_t *a1, int a2, long long a3, int a4) {\n uint32_t *v4;\n int v5;\n long long v6;\n bool v7;\n const char *result;\n if (a2 <= 0) {\n v5 = 0;\n if (a4 <= 0) return \"YES\";\n } else {\n v4 = a1;\n v5 = 0;\n do\n v5 += (*v4++ & 1) == 0;\n while (v4 != &a1[a2]);\n if (a4 <= 0) goto LABEL_7;\n }\n v6 = 0LL;\n do\n v5 += (*(uint32_t *)(a3 + 4 * v6++) & 1) == 0;\n while (a4 > (int)v6);\nLABEL_7:\n v7 = a2 <= v5;\n result = \"YES\";\n if (!v7) return \"NO\";\n return result;\n}" + }, + { + "index": "HumanEval-C-110", + "func_name": "func0", + "func_dep": "#include \n", + "func": "const char *func0(int *lst1, int size1, int *lst2, int size2) {\n int num = 0;\n for (int i = 0; i < size1; i++)\n if (lst1[i] % 2 == 0) num += 1;\n for (int i = 0; i < size2; i++)\n if (lst2[i] % 2 == 0) num += 1;\n if (num >= size1) return \"YES\";\n return \"NO\";\n}", + "test": "#include \n#include \n\nint main() {\n assert(strcmp(func0((const int[]){1, 2, 3, 4}, 4, (const int[]){1, 2, 3, 4}, 4), \"YES\") == 0);\n assert(strcmp(func0((const int[]){1, 2, 3, 4}, 4, (const int[]){1, 5, 3, 4}, 4), \"NO\") == 0);\n assert(strcmp(func0((const int[]){1, 2, 3, 4}, 4, (const int[]){2, 1, 4, 3}, 4), \"YES\") == 0);\n assert(strcmp(func0((const int[]){5, 7, 3}, 3, (const int[]){2, 6, 4}, 3), \"YES\") == 0);\n assert(strcmp(func0((const int[]){5, 7, 3}, 3, (const int[]){2, 6, 3}, 3), \"NO\") == 0);\n assert(strcmp(func0((const int[]){3, 2, 6, 1, 8, 9}, 6, (const int[]){3, 5, 5, 1, 1, 1}, 6), \"NO\") == 0);\n assert(strcmp(func0((const int[]){100, 200}, 2, (const int[]){200, 200}, 2), \"YES\") == 0);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_14D8\nmovsxd rax, esi\nlea r9, [rdi+rax*4]\nxor eax, eax\nnop dword ptr [rax+00000000h]\nloc_1488:\nmov r8d, [rdi]\nand r8d, 1\ncmp r8d, 1\nadc eax, 0\nadd rdi, 4\ncmp rdi, r9\njnz short loc_1488\ntest ecx, ecx\njle short loc_14BF\nloc_14A3:\nxor edi, edi\nnop dword ptr [rax]\nloc_14A8:\nmov r8d, [rdx+rdi*4]\nand r8d, 1\ncmp r8d, 1\nadc eax, 0\nadd rdi, 1\ncmp ecx, edi\njg short loc_14A8\nloc_14BF:\ncmp esi, eax\nlea rdx, aNo; \"NO\"\nlea rax, s2; \"YES\"\ncmovg rax, rdx\nretn\nloc_14D8:\nxor eax, eax\ntest ecx, ecx\njg short loc_14A3\nlea rax, s2; \"YES\"\nretn", + "ida_pseudo": "const char *__fastcall func0(_DWORD *a1, int a2, __int64 a3, int a4)\n{\n _DWORD *v4; // r9\n int v5; // eax\n __int64 v6; // rdi\n bool v7; // cc\n const char *result; // rax\n\n if ( a2 <= 0 )\n {\n v5 = 0;\n if ( a4 <= 0 )\n return \"YES\";\n }\n else\n {\n v4 = &a1[a2];\n v5 = 0;\n do\n v5 += (*a1++ & 1) == 0;\n while ( a1 != v4 );\n if ( a4 <= 0 )\n goto LABEL_7;\n }\n v6 = 0LL;\n do\n v5 += (*(_DWORD *)(a3 + 4 * v6++) & 1) == 0;\n while ( a4 > (int)v6 );\nLABEL_7:\n v7 = a2 <= v5;\n result = \"YES\";\n if ( !v7 )\n return \"NO\";\n return result;\n}", + "ida_strip_asm": "sub_1470:\nendbr64\ntest esi, esi\njle short loc_14D8\nmovsxd rax, esi\nlea r9, [rdi+rax*4]\nxor eax, eax\nnop dword ptr [rax+00000000h]\nloc_1488:\nmov r8d, [rdi]\nand r8d, 1\ncmp r8d, 1\nadc eax, 0\nadd rdi, 4\ncmp rdi, r9\njnz short loc_1488\ntest ecx, ecx\njle short loc_14BF\nloc_14A3:\nxor edi, edi\nnop dword ptr [rax]\nloc_14A8:\nmov r8d, [rdx+rdi*4]\nand r8d, 1\ncmp r8d, 1\nadc eax, 0\nadd rdi, 1\ncmp ecx, edi\njg short loc_14A8\nloc_14BF:\ncmp esi, eax\nlea rdx, aNo; \"NO\"\nlea rax, s2; \"YES\"\ncmovg rax, rdx\nretn\nloc_14D8:\nxor eax, eax\ntest ecx, ecx\njg short loc_14A3\nlea rax, s2; \"YES\"\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1470(_DWORD *a1, int a2, __int64 a3, int a4)\n{\n _DWORD *v4; // r9\n int v5; // eax\n __int64 v6; // rdi\n bool v7; // cc\n const char *result; // rax\n\n if ( a2 <= 0 )\n {\n v5 = 0;\n if ( a4 <= 0 )\n return \"YES\";\n }\n else\n {\n v4 = &a1[a2];\n v5 = 0;\n do\n v5 += (*a1++ & 1) == 0;\n while ( a1 != v4 );\n if ( a4 <= 0 )\n goto LABEL_7;\n }\n v6 = 0LL;\n do\n v5 += (*(_DWORD *)(a3 + 4 * v6++) & 1) == 0;\n while ( a4 > (int)v6 );\nLABEL_7:\n v7 = a2 <= v5;\n result = \"YES\";\n if ( !v7 )\n return \"NO\";\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1470(uint32_t *a1, int a2, long long a3, int a4) {\n uint32_t *v4;\n int v5;\n long long v6;\n bool v7;\n const char *result;\n if (a2 <= 0) {\n v5 = 0;\n if (a4 <= 0) return \"YES\";\n } else {\n v4 = &a1[a2];\n v5 = 0;\n do\n v5 += (*a1++ & 1) == 0;\n while (a1 != v4);\n if (a4 <= 0) goto LABEL_7;\n }\n v6 = 0LL;\n do\n v5 += (*(uint32_t *)(a3 + 4 * v6++) & 1) == 0;\n while (a4 > (int)v6);\nLABEL_7:\n v7 = a2 <= v5;\n result = \"YES\";\n if (!v7) return \"NO\";\n return result;\n}", + "ida_pseudo_norm": "const char *func0(uint32_t *a1, int a2, long long a3, int a4) {\n uint32_t *v4;\n int v5;\n long long v6;\n bool v7;\n const char *result;\n if (a2 <= 0) {\n v5 = 0;\n if (a4 <= 0) return \"YES\";\n } else {\n v4 = &a1[a2];\n v5 = 0;\n do\n v5 += (*a1++ & 1) == 0;\n while (a1 != v4);\n if (a4 <= 0) goto LABEL_7;\n }\n v6 = 0LL;\n do\n v5 += (*(uint32_t *)(a3 + 4 * v6++) & 1) == 0;\n while (a4 > (int)v6);\nLABEL_7:\n v7 = a2 <= v5;\n result = \"YES\";\n if (!v7) return \"NO\";\n return result;\n}" + }, + { + "index": "HumanEval-C-110", + "func_name": "func0", + "func_dep": "#include \n", + "func": "const char *func0(int *lst1, int size1, int *lst2, int size2) {\n int num = 0;\n for (int i = 0; i < size1; i++)\n if (lst1[i] % 2 == 0) num += 1;\n for (int i = 0; i < size2; i++)\n if (lst2[i] % 2 == 0) num += 1;\n if (num >= size1) return \"YES\";\n return \"NO\";\n}", + "test": "#include \n#include \n\nint main() {\n assert(strcmp(func0((const int[]){1, 2, 3, 4}, 4, (const int[]){1, 2, 3, 4}, 4), \"YES\") == 0);\n assert(strcmp(func0((const int[]){1, 2, 3, 4}, 4, (const int[]){1, 5, 3, 4}, 4), \"NO\") == 0);\n assert(strcmp(func0((const int[]){1, 2, 3, 4}, 4, (const int[]){2, 1, 4, 3}, 4), \"YES\") == 0);\n assert(strcmp(func0((const int[]){5, 7, 3}, 3, (const int[]){2, 6, 4}, 3), \"YES\") == 0);\n assert(strcmp(func0((const int[]){5, 7, 3}, 3, (const int[]){2, 6, 3}, 3), \"NO\") == 0);\n assert(strcmp(func0((const int[]){3, 2, 6, 1, 8, 9}, 6, (const int[]){3, 5, 5, 1, 1, 1}, 6), \"NO\") == 0);\n assert(strcmp(func0((const int[]){100, 200}, 2, (const int[]){200, 200}, 2), \"YES\") == 0);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmov r9, rdi\nmov r8d, ecx\nmov rdi, rdx\ntest esi, esi\njle loc_1610\nlea eax, [rsi-1]\ncmp eax, 2\njbe loc_1622\nmov edx, esi\npxor xmm1, xmm1\nmovdqa xmm2, cs:xmmword_22A0\nmov rax, r9\nshr edx, 2\nmovdqa xmm3, xmm1\nshl rdx, 4\nadd rdx, r9\nloc_14B0:\nmovdqu xmm0, xmmword ptr [rax]\nadd rax, 10h\npand xmm0, xmm2\npcmpeqd xmm0, xmm3\npsubd xmm1, xmm0\ncmp rax, rdx\njnz short loc_14B0\nmovdqa xmm0, xmm1\nmov eax, esi\npsrldq xmm0, 8\nand eax, 0FFFFFFFCh\npaddd xmm1, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm0, 4\npaddd xmm1, xmm0\nmovd edx, xmm1\ntest sil, 3\njz short loc_1534\nloc_14F2:\nmovsxd rcx, eax\nlea r10, ds:0[rcx*4]\nmov ecx, [r9+rcx*4]\nand ecx, 1\ncmp ecx, 1\nlea ecx, [rax+1]\nadc edx, 0\ncmp esi, ecx\njle short loc_1534\nmov ecx, [r9+r10+4]\nand ecx, 1\ncmp ecx, 1\nadc edx, 0\nadd eax, 2\ncmp esi, eax\njle short loc_1534\nmov eax, [r9+r10+8]\nand eax, 1\ncmp eax, 1\nadc edx, 0\nloc_1534:\ntest r8d, r8d\njle loc_15F8\nloc_153D:\ncmp r8d, 3\njle loc_162B\nmov ecx, r8d\npxor xmm1, xmm1\nmovdqa xmm2, cs:xmmword_22A0\nmov rax, rdi\nshr ecx, 2\nmovdqa xmm3, xmm1\nshl rcx, 4\nadd rcx, rdi\nnop word ptr [rax+rax+00000000h]\nloc_1570:\nmovdqu xmm0, xmmword ptr [rax]\nadd rax, 10h\npand xmm0, xmm2\npcmpeqd xmm0, xmm3\npsubd xmm1, xmm0\ncmp rax, rcx\njnz short loc_1570\nmovdqa xmm0, xmm1\npsrldq xmm0, 8\npaddd xmm1, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm0, 4\npaddd xmm1, xmm0\nmovd eax, xmm1\nadd edx, eax\nmov eax, r8d\nand eax, 0FFFFFFFCh\ntest r8b, 3\njz short loc_15F8\nloc_15B5:\nmovsxd rcx, eax\nlea r9, ds:0[rcx*4]\nmov ecx, [rdi+rcx*4]\nand ecx, 1\ncmp ecx, 1\nlea ecx, [rax+1]\nadc edx, 0\ncmp r8d, ecx\njle short loc_15F8\nmov ecx, [rdi+r9+4]\nand ecx, 1\ncmp ecx, 1\nadc edx, 0\nadd eax, 2\ncmp eax, r8d\njge short loc_15F8\nmov eax, [rdi+r9+8]\nand eax, 1\ncmp eax, 1\nadc edx, 0\nloc_15F8:\ncmp esi, edx\nlea rax, s2; \"YES\"\nlea rdx, aNo; \"NO\"\ncmovg rax, rdx\nretn\nloc_1610:\nxor edx, edx\ntest ecx, ecx\njg loc_153D\nlea rax, s2; \"YES\"\nretn\nloc_1622:\nxor eax, eax\nxor edx, edx\njmp loc_14F2\nloc_162B:\nxor eax, eax\njmp short loc_15B5", + "ida_pseudo": "const char *__fastcall func0(const __m128i *a1, int a2, const __m128i *a3, int a4)\n{\n __m128i v6; // xmm1\n __m128i si128; // xmm2\n const __m128i *v8; // rax\n __m128i v9; // xmm0\n int v10; // eax\n __m128i v11; // xmm1\n int v12; // edx\n __int64 v13; // r10\n __m128i v14; // xmm1\n __m128i v15; // xmm2\n const __m128i *v16; // rax\n __m128i v17; // xmm0\n __m128i v18; // xmm1\n signed int v19; // eax\n __int64 v20; // r9\n const char *result; // rax\n\n if ( a2 > 0 )\n {\n if ( (unsigned int)(a2 - 1) <= 2 )\n {\n v10 = 0;\n v12 = 0;\n }\n else\n {\n v6 = 0LL;\n si128 = _mm_load_si128((const __m128i *)&xmmword_22A0);\n v8 = a1;\n do\n {\n v9 = _mm_loadu_si128(v8++);\n v6 = _mm_sub_epi32(v6, _mm_cmpeq_epi32(_mm_and_si128(v9, si128), (__m128i)0LL));\n }\n while ( v8 != &a1[(unsigned int)a2 >> 2] );\n v10 = a2 & 0x7FFFFFFC;\n v11 = _mm_add_epi32(v6, _mm_srli_si128(v6, 8));\n v12 = _mm_cvtsi128_si32(_mm_add_epi32(v11, _mm_srli_si128(v11, 4)));\n if ( (a2 & 3) == 0 )\n goto LABEL_9;\n }\n v13 = v10;\n v12 += (a1->m128i_i32[v13] & 1) == 0;\n if ( a2 > v10 + 1 )\n {\n v12 += (a1->m128i_i32[v13 + 1] & 1) == 0;\n if ( a2 > v10 + 2 )\n v12 += (a1->m128i_i32[v13 + 2] & 1) == 0;\n }\nLABEL_9:\n if ( a4 <= 0 )\n goto LABEL_17;\n goto LABEL_10;\n }\n v12 = 0;\n if ( a4 <= 0 )\n return \"YES\";\nLABEL_10:\n if ( a4 <= 3 )\n {\n v19 = 0;\n goto LABEL_14;\n }\n v14 = 0LL;\n v15 = _mm_load_si128((const __m128i *)&xmmword_22A0);\n v16 = a3;\n do\n {\n v17 = _mm_loadu_si128(v16++);\n v14 = _mm_sub_epi32(v14, _mm_cmpeq_epi32(_mm_and_si128(v17, v15), (__m128i)0LL));\n }\n while ( v16 != &a3[(unsigned int)a4 >> 2] );\n v18 = _mm_add_epi32(v14, _mm_srli_si128(v14, 8));\n v12 += _mm_cvtsi128_si32(_mm_add_epi32(v18, _mm_srli_si128(v18, 4)));\n v19 = a4 & 0xFFFFFFFC;\n if ( (a4 & 3) != 0 )\n {\nLABEL_14:\n v20 = v19;\n v12 += (a3->m128i_i32[v20] & 1) == 0;\n if ( a4 > v19 + 1 )\n {\n v12 += (a3->m128i_i32[v20 + 1] & 1) == 0;\n if ( v19 + 2 < a4 )\n v12 += (a3->m128i_i32[v20 + 2] & 1) == 0;\n }\n }\nLABEL_17:\n result = \"YES\";\n if ( a2 > v12 )\n return \"NO\";\n return result;\n}", + "ida_strip_asm": "sub_1470:\nendbr64\nmov r9, rdi\nmov r8d, ecx\nmov rdi, rdx\ntest esi, esi\njle loc_1610\nlea eax, [rsi-1]\ncmp eax, 2\njbe loc_1622\nmov edx, esi\npxor xmm1, xmm1\nmovdqa xmm2, cs:xmmword_22A0\nmov rax, r9\nshr edx, 2\nmovdqa xmm3, xmm1\nshl rdx, 4\nadd rdx, r9\nloc_14B0:\nmovdqu xmm0, xmmword ptr [rax]\nadd rax, 10h\npand xmm0, xmm2\npcmpeqd xmm0, xmm3\npsubd xmm1, xmm0\ncmp rax, rdx\njnz short loc_14B0\nmovdqa xmm0, xmm1\nmov eax, esi\npsrldq xmm0, 8\nand eax, 0FFFFFFFCh\npaddd xmm1, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm0, 4\npaddd xmm1, xmm0\nmovd edx, xmm1\ntest sil, 3\njz short loc_1534\nloc_14F2:\nmovsxd rcx, eax\nlea r10, ds:0[rcx*4]\nmov ecx, [r9+rcx*4]\nand ecx, 1\ncmp ecx, 1\nlea ecx, [rax+1]\nadc edx, 0\ncmp esi, ecx\njle short loc_1534\nmov ecx, [r9+r10+4]\nand ecx, 1\ncmp ecx, 1\nadc edx, 0\nadd eax, 2\ncmp esi, eax\njle short loc_1534\nmov eax, [r9+r10+8]\nand eax, 1\ncmp eax, 1\nadc edx, 0\nloc_1534:\ntest r8d, r8d\njle loc_15F8\nloc_153D:\ncmp r8d, 3\njle loc_162B\nmov ecx, r8d\npxor xmm1, xmm1\nmovdqa xmm2, cs:xmmword_22A0\nmov rax, rdi\nshr ecx, 2\nmovdqa xmm3, xmm1\nshl rcx, 4\nadd rcx, rdi\nnop word ptr [rax+rax+00000000h]\nloc_1570:\nmovdqu xmm0, xmmword ptr [rax]\nadd rax, 10h\npand xmm0, xmm2\npcmpeqd xmm0, xmm3\npsubd xmm1, xmm0\ncmp rax, rcx\njnz short loc_1570\nmovdqa xmm0, xmm1\npsrldq xmm0, 8\npaddd xmm1, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm0, 4\npaddd xmm1, xmm0\nmovd eax, xmm1\nadd edx, eax\nmov eax, r8d\nand eax, 0FFFFFFFCh\ntest r8b, 3\njz short loc_15F8\nloc_15B5:\nmovsxd rcx, eax\nlea r9, ds:0[rcx*4]\nmov ecx, [rdi+rcx*4]\nand ecx, 1\ncmp ecx, 1\nlea ecx, [rax+1]\nadc edx, 0\ncmp r8d, ecx\njle short loc_15F8\nmov ecx, [rdi+r9+4]\nand ecx, 1\ncmp ecx, 1\nadc edx, 0\nadd eax, 2\ncmp eax, r8d\njge short loc_15F8\nmov eax, [rdi+r9+8]\nand eax, 1\ncmp eax, 1\nadc edx, 0\nloc_15F8:\ncmp esi, edx\nlea rax, s2; \"YES\"\nlea rdx, aNo; \"NO\"\ncmovg rax, rdx\nretn\nloc_1610:\nxor edx, edx\ntest ecx, ecx\njg loc_153D\nlea rax, s2; \"YES\"\nretn\nloc_1622:\nxor eax, eax\nxor edx, edx\njmp loc_14F2\nloc_162B:\nxor eax, eax\njmp short loc_15B5", + "ida_strip_pseudo": "const char *__fastcall sub_1470(const __m128i *a1, int a2, const __m128i *a3, int a4)\n{\n __m128i v6; // xmm1\n __m128i si128; // xmm2\n const __m128i *v8; // rax\n __m128i v9; // xmm0\n int v10; // eax\n __m128i v11; // xmm1\n int v12; // edx\n __int64 v13; // r10\n __m128i v14; // xmm1\n __m128i v15; // xmm2\n const __m128i *v16; // rax\n __m128i v17; // xmm0\n __m128i v18; // xmm1\n signed int v19; // eax\n __int64 v20; // r9\n const char *result; // rax\n\n if ( a2 > 0 )\n {\n if ( (unsigned int)(a2 - 1) <= 2 )\n {\n v10 = 0;\n v12 = 0;\n }\n else\n {\n v6 = 0LL;\n si128 = _mm_load_si128((const __m128i *)&xmmword_22A0);\n v8 = a1;\n do\n {\n v9 = _mm_loadu_si128(v8++);\n v6 = _mm_sub_epi32(v6, _mm_cmpeq_epi32(_mm_and_si128(v9, si128), (__m128i)0LL));\n }\n while ( v8 != &a1[(unsigned int)a2 >> 2] );\n v10 = a2 & 0x7FFFFFFC;\n v11 = _mm_add_epi32(v6, _mm_srli_si128(v6, 8));\n v12 = _mm_cvtsi128_si32(_mm_add_epi32(v11, _mm_srli_si128(v11, 4)));\n if ( (a2 & 3) == 0 )\n goto LABEL_9;\n }\n v13 = v10;\n v12 += (a1->m128i_i32[v13] & 1) == 0;\n if ( a2 > v10 + 1 )\n {\n v12 += (a1->m128i_i32[v13 + 1] & 1) == 0;\n if ( a2 > v10 + 2 )\n v12 += (a1->m128i_i32[v13 + 2] & 1) == 0;\n }\nLABEL_9:\n if ( a4 <= 0 )\n goto LABEL_17;\n goto LABEL_10;\n }\n v12 = 0;\n if ( a4 <= 0 )\n return \"YES\";\nLABEL_10:\n if ( a4 <= 3 )\n {\n v19 = 0;\n goto LABEL_14;\n }\n v14 = 0LL;\n v15 = _mm_load_si128((const __m128i *)&xmmword_22A0);\n v16 = a3;\n do\n {\n v17 = _mm_loadu_si128(v16++);\n v14 = _mm_sub_epi32(v14, _mm_cmpeq_epi32(_mm_and_si128(v17, v15), (__m128i)0LL));\n }\n while ( v16 != &a3[(unsigned int)a4 >> 2] );\n v18 = _mm_add_epi32(v14, _mm_srli_si128(v14, 8));\n v12 += _mm_cvtsi128_si32(_mm_add_epi32(v18, _mm_srli_si128(v18, 4)));\n v19 = a4 & 0xFFFFFFFC;\n if ( (a4 & 3) != 0 )\n {\nLABEL_14:\n v20 = v19;\n v12 += (a3->m128i_i32[v20] & 1) == 0;\n if ( a4 > v19 + 1 )\n {\n v12 += (a3->m128i_i32[v20 + 1] & 1) == 0;\n if ( v19 + 2 < a4 )\n v12 += (a3->m128i_i32[v20 + 2] & 1) == 0;\n }\n }\nLABEL_17:\n result = \"YES\";\n if ( a2 > v12 )\n return \"NO\";\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1470(const __m128i *a1, int a2, const __m128i *a3, int a4) {\n __m128i v6;\n __m128i si128;\n const __m128i *v8;\n __m128i v9;\n int v10;\n __m128i v11;\n int v12;\n long long v13;\n __m128i v14;\n __m128i v15;\n const __m128i *v16;\n __m128i v17;\n __m128i v18;\n signed int v19;\n long long v20;\n const char *result;\n if (a2 > 0) {\n if ((unsigned int)(a2 - 1) <= 2) {\n v10 = 0;\n v12 = 0;\n } else {\n v6 = 0LL;\n si128 = _mm_load_si128((const __m128i *)&xmmword_22A0);\n v8 = a1;\n do {\n v9 = _mm_loadu_si128(v8++);\n v6 = _mm_sub_epi32(\n v6, _mm_cmpeq_epi32(_mm_and_si128(v9, si128), (__m128i)0LL));\n } while (v8 != &a1[(unsigned int)a2 >> 2]);\n v10 = a2 & 2147483644;\n v11 = _mm_add_epi32(v6, _mm_srli_si128(v6, 8));\n v12 = _mm_cvtsi128_si32(_mm_add_epi32(v11, _mm_srli_si128(v11, 4)));\n if ((a2 & 3) == 0) goto LABEL_9;\n }\n v13 = v10;\n v12 += (a1->m128i_i32[v13] & 1) == 0;\n if (a2 > v10 + 1) {\n v12 += (a1->m128i_i32[v13 + 1] & 1) == 0;\n if (a2 > v10 + 2) v12 += (a1->m128i_i32[v13 + 2] & 1) == 0;\n }\n LABEL_9:\n if (a4 <= 0) goto LABEL_17;\n goto LABEL_10;\n }\n v12 = 0;\n if (a4 <= 0) return \"YES\";\nLABEL_10:\n if (a4 <= 3) {\n v19 = 0;\n goto LABEL_14;\n }\n v14 = 0LL;\n v15 = _mm_load_si128((const __m128i *)&xmmword_22A0);\n v16 = a3;\n do {\n v17 = _mm_loadu_si128(v16++);\n v14 = _mm_sub_epi32(v14,\n _mm_cmpeq_epi32(_mm_and_si128(v17, v15), (__m128i)0LL));\n } while (v16 != &a3[(unsigned int)a4 >> 2]);\n v18 = _mm_add_epi32(v14, _mm_srli_si128(v14, 8));\n v12 += _mm_cvtsi128_si32(_mm_add_epi32(v18, _mm_srli_si128(v18, 4)));\n v19 = a4 & 4294967292;\n if ((a4 & 3) != 0) {\n LABEL_14:\n v20 = v19;\n v12 += (a3->m128i_i32[v20] & 1) == 0;\n if (a4 > v19 + 1) {\n v12 += (a3->m128i_i32[v20 + 1] & 1) == 0;\n if (v19 + 2 < a4) v12 += (a3->m128i_i32[v20 + 2] & 1) == 0;\n }\n }\nLABEL_17:\n result = \"YES\";\n if (a2 > v12) return \"NO\";\n return result;\n}", + "ida_pseudo_norm": "const char *func0(const __m128i *a1, int a2, const __m128i *a3, int a4) {\n __m128i v6;\n __m128i si128;\n const __m128i *v8;\n __m128i v9;\n int v10;\n __m128i v11;\n int v12;\n long long v13;\n __m128i v14;\n __m128i v15;\n const __m128i *v16;\n __m128i v17;\n __m128i v18;\n signed int v19;\n long long v20;\n const char *result;\n if (a2 > 0) {\n if ((unsigned int)(a2 - 1) <= 2) {\n v10 = 0;\n v12 = 0;\n } else {\n v6 = 0LL;\n si128 = _mm_load_si128((const __m128i *)&xmmword_22A0);\n v8 = a1;\n do {\n v9 = _mm_loadu_si128(v8++);\n v6 = _mm_sub_epi32(\n v6, _mm_cmpeq_epi32(_mm_and_si128(v9, si128), (__m128i)0LL));\n } while (v8 != &a1[(unsigned int)a2 >> 2]);\n v10 = a2 & 2147483644;\n v11 = _mm_add_epi32(v6, _mm_srli_si128(v6, 8));\n v12 = _mm_cvtsi128_si32(_mm_add_epi32(v11, _mm_srli_si128(v11, 4)));\n if ((a2 & 3) == 0) goto LABEL_9;\n }\n v13 = v10;\n v12 += (a1->m128i_i32[v13] & 1) == 0;\n if (a2 > v10 + 1) {\n v12 += (a1->m128i_i32[v13 + 1] & 1) == 0;\n if (a2 > v10 + 2) v12 += (a1->m128i_i32[v13 + 2] & 1) == 0;\n }\n LABEL_9:\n if (a4 <= 0) goto LABEL_17;\n goto LABEL_10;\n }\n v12 = 0;\n if (a4 <= 0) return \"YES\";\nLABEL_10:\n if (a4 <= 3) {\n v19 = 0;\n goto LABEL_14;\n }\n v14 = 0LL;\n v15 = _mm_load_si128((const __m128i *)&xmmword_22A0);\n v16 = a3;\n do {\n v17 = _mm_loadu_si128(v16++);\n v14 = _mm_sub_epi32(v14,\n _mm_cmpeq_epi32(_mm_and_si128(v17, v15), (__m128i)0LL));\n } while (v16 != &a3[(unsigned int)a4 >> 2]);\n v18 = _mm_add_epi32(v14, _mm_srli_si128(v14, 8));\n v12 += _mm_cvtsi128_si32(_mm_add_epi32(v18, _mm_srli_si128(v18, 4)));\n v19 = a4 & 4294967292;\n if ((a4 & 3) != 0) {\n LABEL_14:\n v20 = v19;\n v12 += (a3->m128i_i32[v20] & 1) == 0;\n if (a4 > v19 + 1) {\n v12 += (a3->m128i_i32[v20 + 1] & 1) == 0;\n if (v19 + 2 < a4) v12 += (a3->m128i_i32[v20 + 2] & 1) == 0;\n }\n }\nLABEL_17:\n result = \"YES\";\n if (a2 > v12) return \"NO\";\n return result;\n}" + }, + { + "index": "HumanEval-C-111", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(const char* test, int* freq, int* max_count, char* letters) {\n int local_freq[26] = {0};\n int local_max = 0;\n const char* ptr = test;\n int idx = 0;\n while (*ptr) {\n if (*ptr != ' ') {\n int letter_index = *ptr - 'a';\n local_freq[letter_index]++;\n if (local_freq[letter_index] > local_max) {\n local_max = local_freq[letter_index];\n }\n }\n ptr++;\n }\n for (int i = 0; i < 26; i++) {\n freq[i] = local_freq[i];\n if (local_freq[i] == local_max) {\n letters[idx++] = 'a' + i;\n }\n }\n *max_count = local_max;\n letters[idx] = '\\0';\n}", + "test": "#include \n#include \n#include \n#include \n\nbool issame(int* freq1, const char* letters1, int max_count1, int* freq2, const char* letters2, int max_count2) {\n if (max_count1 != max_count2) return false;\n for (int i = 0; letters1[i] != '\\0'; i++) {\n if (freq1[letters1[i] - 'a'] != freq2[letters1[i] - 'a']) return false;\n }\n for (int i = 0; letters2[i] != '\\0'; i++) {\n if (freq2[letters2[i] - 'a'] != freq1[letters2[i] - 'a']) return false;\n }\n return true;\n}\n\nint main() {\n int counts1[26], counts2[26];\n int max_count1, max_count2;\n char letters1[27], letters2[27];\n\n func0(\"a b b a\", counts1, &max_count1, letters1);\n memset(counts2, 0, sizeof(counts2));\n counts2['a' - 'a'] = 2;\n counts2['b' - 'a'] = 2;\n assert(issame(counts1, letters1, max_count1, counts2, \"ab\", 2));\n\n func0(\"a b c a b\", counts1, &max_count1, letters1);\n memset(counts2, 0, sizeof(counts2));\n counts2['a' - 'a'] = 2;\n counts2['b' - 'a'] = 2;\n assert(issame(counts1, letters1, max_count1, counts2, \"ab\", 2));\n\n func0(\"a b c d g\", counts1, &max_count1, letters1);\n memset(counts2, 0, sizeof(counts2));\n counts2['a' - 'a'] = counts2['b' - 'a'] = counts2['c' - 'a'] = counts2['d' - 'a'] = counts2['g' - 'a'] = 1;\n assert(issame(counts1, letters1, max_count1, counts2, \"abcdg\", 1));\n\n func0(\"r t g\", counts1, &max_count1, letters1);\n memset(counts2, 0, sizeof(counts2));\n counts2['r' - 'a'] = counts2['t' - 'a'] = counts2['g' - 'a'] = 1;\n assert(issame(counts1, letters1, max_count1, counts2, \"rtg\", 1));\n\n func0(\"b b b b a\", counts1, &max_count1, letters1);\n memset(counts2, 0, sizeof(counts2));\n counts2['b' - 'a'] = 4;\n assert(issame(counts1, letters1, max_count1, counts2, \"b\", 4));\n\n func0(\"r t g\", counts1, &max_count1, letters1);\n memset(counts2, 0, sizeof(counts2));\n counts2['r' - 'a'] = counts2['t' - 'a'] = counts2['g' - 'a'] = 1;\n assert(issame(counts1, letters1, max_count1, counts2, \"rtg\", 1));\n\n func0(\"a\", counts1, &max_count1, letters1);\n memset(counts2, 0, sizeof(counts2));\n counts2['a' - 'a'] = 1;\n assert(issame(counts1, letters1, max_count1, counts2, \"a\", 1));\n \n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0B0h\nmov [rbp+var_98], rdi\nmov [rbp+var_A0], rsi\nmov [rbp+var_A8], rdx\nmov [rbp+var_B0], rcx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rdx, [rbp+var_70]\nmov eax, 0\nmov ecx, 0Dh\nmov rdi, rdx\nrep stosq\nmov [rbp+var_88], 0\nmov rax, [rbp+var_98]\nmov [rbp+var_78], rax\nmov [rbp+var_84], 0\njmp short loc_124D\nloc_11F8:\nmov rax, [rbp+var_78]\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njz short loc_1248\nmov rax, [rbp+var_78]\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nsub eax, 61h ; 'a'\nmov [rbp+var_7C], eax\nmov eax, [rbp+var_7C]\ncdqe\nmov eax, [rbp+rax*4+var_70]\nlea edx, [rax+1]\nmov eax, [rbp+var_7C]\ncdqe\nmov [rbp+rax*4+var_70], edx\nmov eax, [rbp+var_7C]\ncdqe\nmov eax, [rbp+rax*4+var_70]\ncmp [rbp+var_88], eax\njge short loc_1248\nmov eax, [rbp+var_7C]\ncdqe\nmov eax, [rbp+rax*4+var_70]\nmov [rbp+var_88], eax\nloc_1248:\nadd [rbp+var_78], 1\nloc_124D:\nmov rax, [rbp+var_78]\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_11F8\nmov [rbp+var_80], 0\njmp short loc_12BE\nloc_1261:\nmov eax, [rbp+var_80]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_A0]\nadd rdx, rax\nmov eax, [rbp+var_80]\ncdqe\nmov eax, [rbp+rax*4+var_70]\nmov [rdx], eax\nmov eax, [rbp+var_80]\ncdqe\nmov eax, [rbp+rax*4+var_70]\ncmp [rbp+var_88], eax\njnz short loc_12BA\nmov eax, [rbp+var_80]\nlea ecx, [rax+61h]\nmov eax, [rbp+var_84]\nlea edx, [rax+1]\nmov [rbp+var_84], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_B0]\nadd rax, rdx\nmov edx, ecx\nmov [rax], dl\nloc_12BA:\nadd [rbp+var_80], 1\nloc_12BE:\ncmp [rbp+var_80], 19h\njle short loc_1261\nmov rax, [rbp+var_A8]\nmov edx, [rbp+var_88]\nmov [rax], edx\nmov eax, [rbp+var_84]\nmovsxd rdx, eax\nmov rax, [rbp+var_B0]\nadd rax, rdx\nmov byte ptr [rax], 0\nnop\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njz short locret_12FE\ncall ___stack_chk_fail\nlocret_12FE:\nleave\nretn", + "ida_pseudo": "unsigned __int64 __fastcall func0(_BYTE *a1, __int64 a2, _DWORD *a3, __int64 a4)\n{\n int v4; // eax\n int v6; // [rsp+28h] [rbp-88h]\n int v7; // [rsp+2Ch] [rbp-84h]\n int i; // [rsp+30h] [rbp-80h]\n int v9; // [rsp+34h] [rbp-7Ch]\n _DWORD v11[26]; // [rsp+40h] [rbp-70h] BYREF\n unsigned __int64 v12; // [rsp+A8h] [rbp-8h]\n\n v12 = __readfsqword(0x28u);\n memset(v11, 0, sizeof(v11));\n v6 = 0;\n v7 = 0;\n while ( *a1 )\n {\n if ( *a1 != 32 )\n {\n v9 = (char)*a1 - 97;\n if ( v6 < ++v11[v9] )\n v6 = v11[v9];\n }\n ++a1;\n }\n for ( i = 0; i <= 25; ++i )\n {\n *(_DWORD *)(a2 + 4LL * i) = v11[i];\n if ( v6 == v11[i] )\n {\n v4 = v7++;\n *(_BYTE *)(v4 + a4) = i + 97;\n }\n }\n *a3 = v6;\n *(_BYTE *)(v7 + a4) = 0;\n return v12 - __readfsqword(0x28u);\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0B0h\nmov [rbp+var_98], rdi\nmov [rbp+var_A0], rsi\nmov [rbp+var_A8], rdx\nmov [rbp+var_B0], rcx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rdx, [rbp+var_70]\nmov eax, 0\nmov ecx, 0Dh\nmov rdi, rdx\nrep stosq\nmov [rbp+var_88], 0\nmov rax, [rbp+var_98]\nmov [rbp+var_78], rax\nmov [rbp+var_84], 0\njmp short loc_124D\nloc_11F8:\nmov rax, [rbp+var_78]\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njz short loc_1248\nmov rax, [rbp+var_78]\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nsub eax, 61h ; 'a'\nmov [rbp+var_7C], eax\nmov eax, [rbp+var_7C]\ncdqe\nmov eax, [rbp+rax*4+var_70]\nlea edx, [rax+1]\nmov eax, [rbp+var_7C]\ncdqe\nmov [rbp+rax*4+var_70], edx\nmov eax, [rbp+var_7C]\ncdqe\nmov eax, [rbp+rax*4+var_70]\ncmp [rbp+var_88], eax\njge short loc_1248\nmov eax, [rbp+var_7C]\ncdqe\nmov eax, [rbp+rax*4+var_70]\nmov [rbp+var_88], eax\nloc_1248:\nadd [rbp+var_78], 1\nloc_124D:\nmov rax, [rbp+var_78]\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_11F8\nmov [rbp+var_80], 0\njmp short loc_12BE\nloc_1261:\nmov eax, [rbp+var_80]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_A0]\nadd rdx, rax\nmov eax, [rbp+var_80]\ncdqe\nmov eax, [rbp+rax*4+var_70]\nmov [rdx], eax\nmov eax, [rbp+var_80]\ncdqe\nmov eax, [rbp+rax*4+var_70]\ncmp [rbp+var_88], eax\njnz short loc_12BA\nmov eax, [rbp+var_80]\nlea ecx, [rax+61h]\nmov eax, [rbp+var_84]\nlea edx, [rax+1]\nmov [rbp+var_84], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_B0]\nadd rax, rdx\nmov edx, ecx\nmov [rax], dl\nloc_12BA:\nadd [rbp+var_80], 1\nloc_12BE:\ncmp [rbp+var_80], 19h\njle short loc_1261\nmov rax, [rbp+var_A8]\nmov edx, [rbp+var_88]\nmov [rax], edx\nmov eax, [rbp+var_84]\nmovsxd rdx, eax\nmov rax, [rbp+var_B0]\nadd rax, rdx\nmov byte ptr [rax], 0\nnop\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njz short locret_12FE\ncall ___stack_chk_fail\nlocret_12FE:\nleave\nretn", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_1189(_BYTE *a1, __int64 a2, _DWORD *a3, __int64 a4)\n{\n int v4; // eax\n int v6; // [rsp+28h] [rbp-88h]\n int v7; // [rsp+2Ch] [rbp-84h]\n int i; // [rsp+30h] [rbp-80h]\n int v9; // [rsp+34h] [rbp-7Ch]\n _DWORD v11[26]; // [rsp+40h] [rbp-70h] BYREF\n unsigned __int64 v12; // [rsp+A8h] [rbp-8h]\n\n v12 = __readfsqword(0x28u);\n memset(v11, 0, sizeof(v11));\n v6 = 0;\n v7 = 0;\n while ( *a1 )\n {\n if ( *a1 != 32 )\n {\n v9 = (char)*a1 - 97;\n if ( v6 < ++v11[v9] )\n v6 = v11[v9];\n }\n ++a1;\n }\n for ( i = 0; i <= 25; ++i )\n {\n *(_DWORD *)(a2 + 4LL * i) = v11[i];\n if ( v6 == v11[i] )\n {\n v4 = v7++;\n *(_BYTE *)(v4 + a4) = i + 97;\n }\n }\n *a3 = v6;\n *(_BYTE *)(v7 + a4) = 0;\n return v12 - __readfsqword(0x28u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_1189(uint8_t *a1, long long a2, uint32_t *a3,\n long long a4) {\n int v4;\n int v6;\n int v7;\n int i;\n int v9;\n uint32_t v11[26];\n unsigned long long v12;\n v12 = __readfsqword(40u);\n memset(v11, 0, sizeof(v11));\n v6 = 0;\n v7 = 0;\n while (*a1) {\n if (*a1 != 32) {\n v9 = (char)*a1 - 97;\n if (v6 < ++v11[v9]) v6 = v11[v9];\n }\n ++a1;\n }\n for (i = 0; i <= 25; ++i) {\n *(uint32_t *)(a2 + 4LL * i) = v11[i];\n if (v6 == v11[i]) {\n v4 = v7++;\n *(uint8_t *)(v4 + a4) = i + 97;\n }\n }\n *a3 = v6;\n *(uint8_t *)(v7 + a4) = 0;\n return v12 - __readfsqword(40u);\n}", + "ida_pseudo_norm": "unsigned long long func0(uint8_t *a1, long long a2, uint32_t *a3,\n long long a4) {\n int v4;\n int v6;\n int v7;\n int i;\n int v9;\n uint32_t v11[26];\n unsigned long long v12;\n v12 = __readfsqword(40u);\n memset(v11, 0, sizeof(v11));\n v6 = 0;\n v7 = 0;\n while (*a1) {\n if (*a1 != 32) {\n v9 = (char)*a1 - 97;\n if (v6 < ++v11[v9]) v6 = v11[v9];\n }\n ++a1;\n }\n for (i = 0; i <= 25; ++i) {\n *(uint32_t *)(a2 + 4LL * i) = v11[i];\n if (v6 == v11[i]) {\n v4 = v7++;\n *(uint8_t *)(v4 + a4) = i + 97;\n }\n }\n *a3 = v6;\n *(uint8_t *)(v7 + a4) = 0;\n return v12 - __readfsqword(40u);\n}" + }, + { + "index": "HumanEval-C-111", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(const char* test, int* freq, int* max_count, char* letters) {\n int local_freq[26] = {0};\n int local_max = 0;\n const char* ptr = test;\n int idx = 0;\n while (*ptr) {\n if (*ptr != ' ') {\n int letter_index = *ptr - 'a';\n local_freq[letter_index]++;\n if (local_freq[letter_index] > local_max) {\n local_max = local_freq[letter_index];\n }\n }\n ptr++;\n }\n for (int i = 0; i < 26; i++) {\n freq[i] = local_freq[i];\n if (local_freq[i] == local_max) {\n letters[idx++] = 'a' + i;\n }\n }\n *max_count = local_max;\n letters[idx] = '\\0';\n}", + "test": "#include \n#include \n#include \n#include \n\nbool issame(int* freq1, const char* letters1, int max_count1, int* freq2, const char* letters2, int max_count2) {\n if (max_count1 != max_count2) return false;\n for (int i = 0; letters1[i] != '\\0'; i++) {\n if (freq1[letters1[i] - 'a'] != freq2[letters1[i] - 'a']) return false;\n }\n for (int i = 0; letters2[i] != '\\0'; i++) {\n if (freq2[letters2[i] - 'a'] != freq1[letters2[i] - 'a']) return false;\n }\n return true;\n}\n\nint main() {\n int counts1[26], counts2[26];\n int max_count1, max_count2;\n char letters1[27], letters2[27];\n\n func0(\"a b b a\", counts1, &max_count1, letters1);\n memset(counts2, 0, sizeof(counts2));\n counts2['a' - 'a'] = 2;\n counts2['b' - 'a'] = 2;\n assert(issame(counts1, letters1, max_count1, counts2, \"ab\", 2));\n\n func0(\"a b c a b\", counts1, &max_count1, letters1);\n memset(counts2, 0, sizeof(counts2));\n counts2['a' - 'a'] = 2;\n counts2['b' - 'a'] = 2;\n assert(issame(counts1, letters1, max_count1, counts2, \"ab\", 2));\n\n func0(\"a b c d g\", counts1, &max_count1, letters1);\n memset(counts2, 0, sizeof(counts2));\n counts2['a' - 'a'] = counts2['b' - 'a'] = counts2['c' - 'a'] = counts2['d' - 'a'] = counts2['g' - 'a'] = 1;\n assert(issame(counts1, letters1, max_count1, counts2, \"abcdg\", 1));\n\n func0(\"r t g\", counts1, &max_count1, letters1);\n memset(counts2, 0, sizeof(counts2));\n counts2['r' - 'a'] = counts2['t' - 'a'] = counts2['g' - 'a'] = 1;\n assert(issame(counts1, letters1, max_count1, counts2, \"rtg\", 1));\n\n func0(\"b b b b a\", counts1, &max_count1, letters1);\n memset(counts2, 0, sizeof(counts2));\n counts2['b' - 'a'] = 4;\n assert(issame(counts1, letters1, max_count1, counts2, \"b\", 4));\n\n func0(\"r t g\", counts1, &max_count1, letters1);\n memset(counts2, 0, sizeof(counts2));\n counts2['r' - 'a'] = counts2['t' - 'a'] = counts2['g' - 'a'] = 1;\n assert(issame(counts1, letters1, max_count1, counts2, \"rtg\", 1));\n\n func0(\"a\", counts1, &max_count1, letters1);\n memset(counts2, 0, sizeof(counts2));\n counts2['a' - 'a'] = 1;\n assert(issame(counts1, letters1, max_count1, counts2, \"a\", 1));\n \n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nsub rsp, 78h\nmov r11, rdi\nmov r8, rsi\nmov r10, rdx\nmov r9, rcx\nmov rax, fs:28h\nmov [rsp+78h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nmov ecx, 0Dh\nrep stosq\nmovzx eax, byte ptr [r11]\ntest al, al\njnz short loc_11D3\nmov ecx, 0\nloc_11A5:\nmov eax, 0\nmov esi, 0\njmp short loc_11E3\nloc_11B1:\nmovsx eax, al\nsub eax, 61h ; 'a'\ncdqe\nmov edi, [rsp+rax*4+78h+var_78]\nlea edx, [rdi+1]\nmov [rsp+rax*4+78h+var_78], edx\ncmp ecx, edx\ncmovl ecx, edx\nloc_11C7:\nadd r11, 1\nmovzx eax, byte ptr [r11]\ntest al, al\njz short loc_11A5\nloc_11D3:\ncmp al, 20h ; ' '\njnz short loc_11B1\njmp short loc_11C7\nloc_11D9:\nadd rax, 1\ncmp rax, 1Ah\njz short loc_11FD\nloc_11E3:\nmov edx, [rsp+rax*4+78h+var_78]\nmov [r8+rax*4], edx\ncmp edx, ecx\njnz short loc_11D9\nmovsxd rdx, esi\nlea edi, [rax+61h]\nmov [r9+rdx], dil\nlea esi, [rsi+1]\njmp short loc_11D9\nloc_11FD:\nmov [r10], ecx\nmovsxd rsi, esi\nmov byte ptr [r9+rsi], 0\nmov rax, [rsp+78h+var_10]\nsub rax, fs:28h\njnz short loc_121D\nadd rsp, 78h\nretn\nloc_121D:\ncall ___stack_chk_fail", + "ida_pseudo": "unsigned __int64 __fastcall func0(_BYTE *a1, __int64 a2, int *a3, __int64 a4)\n{\n _BYTE *v4; // r11\n int v8; // ecx\n char v9; // al\n __int64 v10; // rax\n int v11; // esi\n __int64 v12; // rax\n int v13; // edx\n int v14; // edx\n _DWORD v16[26]; // [rsp+0h] [rbp-78h] BYREF\n unsigned __int64 v17; // [rsp+68h] [rbp-10h]\n\n v4 = a1;\n v17 = __readfsqword(0x28u);\n memset(v16, 0, sizeof(v16));\n v8 = 0;\n v9 = *a1;\n if ( *a1 )\n {\n do\n {\n if ( v9 != 32 )\n {\n v12 = v9 - 97;\n v13 = v16[v12] + 1;\n v16[v12] = v13;\n if ( v8 < v13 )\n v8 = v13;\n }\n v9 = *++v4;\n }\n while ( *v4 );\n }\n else\n {\n v8 = 0;\n }\n v10 = 0LL;\n v11 = 0;\n do\n {\n v14 = v16[v10];\n *(_DWORD *)(a2 + 4 * v10) = v14;\n if ( v14 == v8 )\n *(_BYTE *)(a4 + v11++) = v10 + 97;\n ++v10;\n }\n while ( v10 != 26 );\n *a3 = v8;\n *(_BYTE *)(a4 + v11) = 0;\n return v17 - __readfsqword(0x28u);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nsub rsp, 78h\nmov r11, rdi\nmov r8, rsi\nmov r10, rdx\nmov r9, rcx\nmov rax, fs:28h\nmov [rsp+78h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nmov ecx, 0Dh\nrep stosq\nmovzx eax, byte ptr [r11]\ntest al, al\njnz short loc_11D3\nmov ecx, 0\nloc_11A5:\nmov eax, 0\nmov esi, 0\njmp short loc_11E3\nloc_11B1:\nmovsx eax, al\nsub eax, 61h ; 'a'\ncdqe\nmov edi, [rsp+rax*4+78h+var_78]\nlea edx, [rdi+1]\nmov [rsp+rax*4+78h+var_78], edx\ncmp ecx, edx\ncmovl ecx, edx\nloc_11C7:\nadd r11, 1\nmovzx eax, byte ptr [r11]\ntest al, al\njz short loc_11A5\nloc_11D3:\ncmp al, 20h ; ' '\njnz short loc_11B1\njmp short loc_11C7\nloc_11D9:\nadd rax, 1\ncmp rax, 1Ah\njz short loc_11FD\nloc_11E3:\nmov edx, [rsp+rax*4+78h+var_78]\nmov [r8+rax*4], edx\ncmp edx, ecx\njnz short loc_11D9\nmovsxd rdx, esi\nlea edi, [rax+61h]\nmov [r9+rdx], dil\nlea esi, [rsi+1]\njmp short loc_11D9\nloc_11FD:\nmov [r10], ecx\nmovsxd rsi, esi\nmov byte ptr [r9+rsi], 0\nmov rax, [rsp+78h+var_10]\nsub rax, fs:28h\njnz short loc_121D\nadd rsp, 78h\nretn\nloc_121D:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_1169(_BYTE *a1, __int64 a2, int *a3, __int64 a4)\n{\n _BYTE *v4; // r11\n int v8; // ecx\n char v9; // al\n __int64 v10; // rax\n int v11; // esi\n __int64 v12; // rax\n int v13; // edx\n int v14; // edx\n _DWORD v16[26]; // [rsp+0h] [rbp-78h] BYREF\n unsigned __int64 v17; // [rsp+68h] [rbp-10h]\n\n v4 = a1;\n v17 = __readfsqword(0x28u);\n memset(v16, 0, sizeof(v16));\n v8 = 0;\n v9 = *a1;\n if ( *a1 )\n {\n do\n {\n if ( v9 != 32 )\n {\n v12 = v9 - 97;\n v13 = v16[v12] + 1;\n v16[v12] = v13;\n if ( v8 < v13 )\n v8 = v13;\n }\n v9 = *++v4;\n }\n while ( *v4 );\n }\n else\n {\n v8 = 0;\n }\n v10 = 0LL;\n v11 = 0;\n do\n {\n v14 = v16[v10];\n *(_DWORD *)(a2 + 4 * v10) = v14;\n if ( v14 == v8 )\n *(_BYTE *)(a4 + v11++) = v10 + 97;\n ++v10;\n }\n while ( v10 != 26 );\n *a3 = v8;\n *(_BYTE *)(a4 + v11) = 0;\n return v17 - __readfsqword(0x28u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_1169(uint8_t *a1, long long a2, int *a3, long long a4) {\n uint8_t *v4;\n int v8;\n char v9;\n long long v10;\n int v11;\n long long v12;\n int v13;\n int v14;\n uint32_t v16[26];\n unsigned long long v17;\n v4 = a1;\n v17 = __readfsqword(40u);\n memset(v16, 0, sizeof(v16));\n v8 = 0;\n v9 = *a1;\n if (*a1) {\n do {\n if (v9 != 32) {\n v12 = v9 - 97;\n v13 = v16[v12] + 1;\n v16[v12] = v13;\n if (v8 < v13) v8 = v13;\n }\n v9 = *++v4;\n } while (*v4);\n } else {\n v8 = 0;\n }\n v10 = 0LL;\n v11 = 0;\n do {\n v14 = v16[v10];\n *(uint32_t *)(a2 + 4 * v10) = v14;\n if (v14 == v8) *(uint8_t *)(a4 + v11++) = v10 + 97;\n ++v10;\n } while (v10 != 26);\n *a3 = v8;\n *(uint8_t *)(a4 + v11) = 0;\n return v17 - __readfsqword(40u);\n}", + "ida_pseudo_norm": "unsigned long long func0(uint8_t *a1, long long a2, int *a3, long long a4) {\n uint8_t *v4;\n int v8;\n char v9;\n long long v10;\n int v11;\n long long v12;\n int v13;\n int v14;\n uint32_t v16[26];\n unsigned long long v17;\n v4 = a1;\n v17 = __readfsqword(40u);\n memset(v16, 0, sizeof(v16));\n v8 = 0;\n v9 = *a1;\n if (*a1) {\n do {\n if (v9 != 32) {\n v12 = v9 - 97;\n v13 = v16[v12] + 1;\n v16[v12] = v13;\n if (v8 < v13) v8 = v13;\n }\n v9 = *++v4;\n } while (*v4);\n } else {\n v8 = 0;\n }\n v10 = 0LL;\n v11 = 0;\n do {\n v14 = v16[v10];\n *(uint32_t *)(a2 + 4 * v10) = v14;\n if (v14 == v8) *(uint8_t *)(a4 + v11++) = v10 + 97;\n ++v10;\n } while (v10 != 26);\n *a3 = v8;\n *(uint8_t *)(a4 + v11) = 0;\n return v17 - __readfsqword(40u);\n}" + }, + { + "index": "HumanEval-C-111", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(const char* test, int* freq, int* max_count, char* letters) {\n int local_freq[26] = {0};\n int local_max = 0;\n const char* ptr = test;\n int idx = 0;\n while (*ptr) {\n if (*ptr != ' ') {\n int letter_index = *ptr - 'a';\n local_freq[letter_index]++;\n if (local_freq[letter_index] > local_max) {\n local_max = local_freq[letter_index];\n }\n }\n ptr++;\n }\n for (int i = 0; i < 26; i++) {\n freq[i] = local_freq[i];\n if (local_freq[i] == local_max) {\n letters[idx++] = 'a' + i;\n }\n }\n *max_count = local_max;\n letters[idx] = '\\0';\n}", + "test": "#include \n#include \n#include \n#include \n\nbool issame(int* freq1, const char* letters1, int max_count1, int* freq2, const char* letters2, int max_count2) {\n if (max_count1 != max_count2) return false;\n for (int i = 0; letters1[i] != '\\0'; i++) {\n if (freq1[letters1[i] - 'a'] != freq2[letters1[i] - 'a']) return false;\n }\n for (int i = 0; letters2[i] != '\\0'; i++) {\n if (freq2[letters2[i] - 'a'] != freq1[letters2[i] - 'a']) return false;\n }\n return true;\n}\n\nint main() {\n int counts1[26], counts2[26];\n int max_count1, max_count2;\n char letters1[27], letters2[27];\n\n func0(\"a b b a\", counts1, &max_count1, letters1);\n memset(counts2, 0, sizeof(counts2));\n counts2['a' - 'a'] = 2;\n counts2['b' - 'a'] = 2;\n assert(issame(counts1, letters1, max_count1, counts2, \"ab\", 2));\n\n func0(\"a b c a b\", counts1, &max_count1, letters1);\n memset(counts2, 0, sizeof(counts2));\n counts2['a' - 'a'] = 2;\n counts2['b' - 'a'] = 2;\n assert(issame(counts1, letters1, max_count1, counts2, \"ab\", 2));\n\n func0(\"a b c d g\", counts1, &max_count1, letters1);\n memset(counts2, 0, sizeof(counts2));\n counts2['a' - 'a'] = counts2['b' - 'a'] = counts2['c' - 'a'] = counts2['d' - 'a'] = counts2['g' - 'a'] = 1;\n assert(issame(counts1, letters1, max_count1, counts2, \"abcdg\", 1));\n\n func0(\"r t g\", counts1, &max_count1, letters1);\n memset(counts2, 0, sizeof(counts2));\n counts2['r' - 'a'] = counts2['t' - 'a'] = counts2['g' - 'a'] = 1;\n assert(issame(counts1, letters1, max_count1, counts2, \"rtg\", 1));\n\n func0(\"b b b b a\", counts1, &max_count1, letters1);\n memset(counts2, 0, sizeof(counts2));\n counts2['b' - 'a'] = 4;\n assert(issame(counts1, letters1, max_count1, counts2, \"b\", 4));\n\n func0(\"r t g\", counts1, &max_count1, letters1);\n memset(counts2, 0, sizeof(counts2));\n counts2['r' - 'a'] = counts2['t' - 'a'] = counts2['g' - 'a'] = 1;\n assert(issame(counts1, letters1, max_count1, counts2, \"rtg\", 1));\n\n func0(\"a\", counts1, &max_count1, letters1);\n memset(counts2, 0, sizeof(counts2));\n counts2['a' - 'a'] = 1;\n assert(issame(counts1, letters1, max_count1, counts2, \"a\", 1));\n \n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nsub rsp, 78h\nmov r9, rdi\nmov r10, rcx\nmov ecx, 0Dh\nmov rax, fs:28h\nmov [rsp+78h+var_10], rax\nxor eax, eax\nmov r8, rsp\nmov r11, rdx\nmov rdi, r8\nrep stosq\nmovsx eax, byte ptr [r9]\ntest al, al\njz short loc_1623\nnop word ptr [rax+rax+00000000h]\nloc_15B0:\ncmp al, 20h ; ' '\njz short loc_15C7\nsub eax, 61h ; 'a'\ncdqe\nmov edi, [rsp+rax*4+78h+var_78]\nlea edx, [rdi+1]\ncmp ecx, edx\nmov [rsp+rax*4+78h+var_78], edx\ncmovl ecx, edx\nloc_15C7:\nmovsx eax, byte ptr [r9+1]\nadd r9, 1\ntest al, al\njnz short loc_15B0\nloc_15D4:\nxor eax, eax\nxor edi, edi\nnop dword ptr [rax+rax+00000000h]\nloc_15E0:\nmov edx, [r8+rax*4]\nmov [rsi+rax*4], edx\ncmp edx, ecx\njnz short loc_15F9\nmovsxd rdx, edi\nlea r9d, [rax+61h]\nadd edi, 1\nmov [r10+rdx], r9b\nloc_15F9:\nadd rax, 1\ncmp rax, 1Ah\njnz short loc_15E0\nmovsxd rdi, edi\nmov [r11], ecx\nmov byte ptr [r10+rdi], 0\nmov rax, [rsp+78h+var_10]\nsub rax, fs:28h\njnz short loc_1627\nadd rsp, 78h\nretn\nloc_1623:\nxor ecx, ecx\njmp short loc_15D4\nloc_1627:\ncall ___stack_chk_fail", + "ida_pseudo": "unsigned __int64 __fastcall func0(_BYTE *a1, __int64 a2, int *a3, __int64 a4)\n{\n _BYTE *v4; // r9\n int v7; // ecx\n int v8; // eax\n __int64 v9; // rax\n int v10; // edx\n __int64 v11; // rax\n int v12; // edi\n int v13; // edx\n __int64 v14; // rdx\n _DWORD v16[26]; // [rsp+0h] [rbp-78h] BYREF\n unsigned __int64 v17; // [rsp+68h] [rbp-10h]\n\n v4 = a1;\n v17 = __readfsqword(0x28u);\n memset(v16, 0, sizeof(v16));\n v7 = 0;\n v8 = (char)*a1;\n if ( *a1 )\n {\n do\n {\n if ( (_BYTE)v8 != 32 )\n {\n v9 = v8 - 97;\n v10 = v16[v9] + 1;\n v16[v9] = v10;\n if ( v7 < v10 )\n v7 = v10;\n }\n v8 = (char)*++v4;\n }\n while ( (_BYTE)v8 );\n }\n else\n {\n v7 = 0;\n }\n v11 = 0LL;\n v12 = 0;\n do\n {\n v13 = v16[v11];\n *(_DWORD *)(a2 + 4 * v11) = v13;\n if ( v13 == v7 )\n {\n v14 = v12++;\n *(_BYTE *)(a4 + v14) = v11 + 97;\n }\n ++v11;\n }\n while ( v11 != 26 );\n *a3 = v7;\n *(_BYTE *)(a4 + v12) = 0;\n return v17 - __readfsqword(0x28u);\n}", + "ida_strip_asm": "sub_1570:\nendbr64\nsub rsp, 78h\nmov r9, rdi\nmov r10, rcx\nmov ecx, 0Dh\nmov rax, fs:28h\nmov [rsp+78h+var_10], rax\nxor eax, eax\nmov r8, rsp\nmov r11, rdx\nmov rdi, r8\nrep stosq\nmovsx eax, byte ptr [r9]\ntest al, al\njz short loc_1623\nnop word ptr [rax+rax+00000000h]\nloc_15B0:\ncmp al, 20h ; ' '\njz short loc_15C7\nsub eax, 61h ; 'a'\ncdqe\nmov edi, [rsp+rax*4+78h+var_78]\nlea edx, [rdi+1]\ncmp ecx, edx\nmov [rsp+rax*4+78h+var_78], edx\ncmovl ecx, edx\nloc_15C7:\nmovsx eax, byte ptr [r9+1]\nadd r9, 1\ntest al, al\njnz short loc_15B0\nloc_15D4:\nxor eax, eax\nxor edi, edi\nnop dword ptr [rax+rax+00000000h]\nloc_15E0:\nmov edx, [r8+rax*4]\nmov [rsi+rax*4], edx\ncmp edx, ecx\njnz short loc_15F9\nmovsxd rdx, edi\nlea r9d, [rax+61h]\nadd edi, 1\nmov [r10+rdx], r9b\nloc_15F9:\nadd rax, 1\ncmp rax, 1Ah\njnz short loc_15E0\nmovsxd rdi, edi\nmov [r11], ecx\nmov byte ptr [r10+rdi], 0\nmov rax, [rsp+78h+var_10]\nsub rax, fs:28h\njnz short loc_1627\nadd rsp, 78h\nretn\nloc_1623:\nxor ecx, ecx\njmp short loc_15D4\nloc_1627:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_1570(_BYTE *a1, __int64 a2, int *a3, __int64 a4)\n{\n _BYTE *v4; // r9\n int v7; // ecx\n int v8; // eax\n __int64 v9; // rax\n int v10; // edx\n __int64 v11; // rax\n int v12; // edi\n int v13; // edx\n __int64 v14; // rdx\n _DWORD v16[26]; // [rsp+0h] [rbp-78h] BYREF\n unsigned __int64 v17; // [rsp+68h] [rbp-10h]\n\n v4 = a1;\n v17 = __readfsqword(0x28u);\n memset(v16, 0, sizeof(v16));\n v7 = 0;\n v8 = (char)*a1;\n if ( *a1 )\n {\n do\n {\n if ( (_BYTE)v8 != 32 )\n {\n v9 = v8 - 97;\n v10 = v16[v9] + 1;\n v16[v9] = v10;\n if ( v7 < v10 )\n v7 = v10;\n }\n v8 = (char)*++v4;\n }\n while ( (_BYTE)v8 );\n }\n else\n {\n v7 = 0;\n }\n v11 = 0LL;\n v12 = 0;\n do\n {\n v13 = v16[v11];\n *(_DWORD *)(a2 + 4 * v11) = v13;\n if ( v13 == v7 )\n {\n v14 = v12++;\n *(_BYTE *)(a4 + v14) = v11 + 97;\n }\n ++v11;\n }\n while ( v11 != 26 );\n *a3 = v7;\n *(_BYTE *)(a4 + v12) = 0;\n return v17 - __readfsqword(0x28u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_1570(uint8_t *a1, long long a2, int *a3, long long a4) {\n uint8_t *v4;\n int v7;\n int v8;\n long long v9;\n int v10;\n long long v11;\n int v12;\n int v13;\n long long v14;\n uint32_t v16[26];\n unsigned long long v17;\n v4 = a1;\n v17 = __readfsqword(40u);\n memset(v16, 0, sizeof(v16));\n v7 = 0;\n v8 = (char)*a1;\n if (*a1) {\n do {\n if ((uint8_t)v8 != 32) {\n v9 = v8 - 97;\n v10 = v16[v9] + 1;\n v16[v9] = v10;\n if (v7 < v10) v7 = v10;\n }\n v8 = (char)*++v4;\n } while ((uint8_t)v8);\n } else {\n v7 = 0;\n }\n v11 = 0LL;\n v12 = 0;\n do {\n v13 = v16[v11];\n *(uint32_t *)(a2 + 4 * v11) = v13;\n if (v13 == v7) {\n v14 = v12++;\n *(uint8_t *)(a4 + v14) = v11 + 97;\n }\n ++v11;\n } while (v11 != 26);\n *a3 = v7;\n *(uint8_t *)(a4 + v12) = 0;\n return v17 - __readfsqword(40u);\n}", + "ida_pseudo_norm": "unsigned long long func0(uint8_t *a1, long long a2, int *a3, long long a4) {\n uint8_t *v4;\n int v7;\n int v8;\n long long v9;\n int v10;\n long long v11;\n int v12;\n int v13;\n long long v14;\n uint32_t v16[26];\n unsigned long long v17;\n v4 = a1;\n v17 = __readfsqword(40u);\n memset(v16, 0, sizeof(v16));\n v7 = 0;\n v8 = (char)*a1;\n if (*a1) {\n do {\n if ((uint8_t)v8 != 32) {\n v9 = v8 - 97;\n v10 = v16[v9] + 1;\n v16[v9] = v10;\n if (v7 < v10) v7 = v10;\n }\n v8 = (char)*++v4;\n } while ((uint8_t)v8);\n } else {\n v7 = 0;\n }\n v11 = 0LL;\n v12 = 0;\n do {\n v13 = v16[v11];\n *(uint32_t *)(a2 + 4 * v11) = v13;\n if (v13 == v7) {\n v14 = v12++;\n *(uint8_t *)(a4 + v14) = v11 + 97;\n }\n ++v11;\n } while (v11 != 26);\n *a3 = v7;\n *(uint8_t *)(a4 + v12) = 0;\n return v17 - __readfsqword(40u);\n}" + }, + { + "index": "HumanEval-C-111", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(const char* test, int* freq, int* max_count, char* letters) {\n int local_freq[26] = {0};\n int local_max = 0;\n const char* ptr = test;\n int idx = 0;\n while (*ptr) {\n if (*ptr != ' ') {\n int letter_index = *ptr - 'a';\n local_freq[letter_index]++;\n if (local_freq[letter_index] > local_max) {\n local_max = local_freq[letter_index];\n }\n }\n ptr++;\n }\n for (int i = 0; i < 26; i++) {\n freq[i] = local_freq[i];\n if (local_freq[i] == local_max) {\n letters[idx++] = 'a' + i;\n }\n }\n *max_count = local_max;\n letters[idx] = '\\0';\n}", + "test": "#include \n#include \n#include \n#include \n\nbool issame(int* freq1, const char* letters1, int max_count1, int* freq2, const char* letters2, int max_count2) {\n if (max_count1 != max_count2) return false;\n for (int i = 0; letters1[i] != '\\0'; i++) {\n if (freq1[letters1[i] - 'a'] != freq2[letters1[i] - 'a']) return false;\n }\n for (int i = 0; letters2[i] != '\\0'; i++) {\n if (freq2[letters2[i] - 'a'] != freq1[letters2[i] - 'a']) return false;\n }\n return true;\n}\n\nint main() {\n int counts1[26], counts2[26];\n int max_count1, max_count2;\n char letters1[27], letters2[27];\n\n func0(\"a b b a\", counts1, &max_count1, letters1);\n memset(counts2, 0, sizeof(counts2));\n counts2['a' - 'a'] = 2;\n counts2['b' - 'a'] = 2;\n assert(issame(counts1, letters1, max_count1, counts2, \"ab\", 2));\n\n func0(\"a b c a b\", counts1, &max_count1, letters1);\n memset(counts2, 0, sizeof(counts2));\n counts2['a' - 'a'] = 2;\n counts2['b' - 'a'] = 2;\n assert(issame(counts1, letters1, max_count1, counts2, \"ab\", 2));\n\n func0(\"a b c d g\", counts1, &max_count1, letters1);\n memset(counts2, 0, sizeof(counts2));\n counts2['a' - 'a'] = counts2['b' - 'a'] = counts2['c' - 'a'] = counts2['d' - 'a'] = counts2['g' - 'a'] = 1;\n assert(issame(counts1, letters1, max_count1, counts2, \"abcdg\", 1));\n\n func0(\"r t g\", counts1, &max_count1, letters1);\n memset(counts2, 0, sizeof(counts2));\n counts2['r' - 'a'] = counts2['t' - 'a'] = counts2['g' - 'a'] = 1;\n assert(issame(counts1, letters1, max_count1, counts2, \"rtg\", 1));\n\n func0(\"b b b b a\", counts1, &max_count1, letters1);\n memset(counts2, 0, sizeof(counts2));\n counts2['b' - 'a'] = 4;\n assert(issame(counts1, letters1, max_count1, counts2, \"b\", 4));\n\n func0(\"r t g\", counts1, &max_count1, letters1);\n memset(counts2, 0, sizeof(counts2));\n counts2['r' - 'a'] = counts2['t' - 'a'] = counts2['g' - 'a'] = 1;\n assert(issame(counts1, letters1, max_count1, counts2, \"rtg\", 1));\n\n func0(\"a\", counts1, &max_count1, letters1);\n memset(counts2, 0, sizeof(counts2));\n counts2['a' - 'a'] = 1;\n assert(issame(counts1, letters1, max_count1, counts2, \"a\", 1));\n \n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nsub rsp, 78h\nmov r9, rdi\nmov r10, rcx\nmov ecx, 0Dh\nmov rax, fs:28h\nmov [rsp+78h+var_10], rax\nxor eax, eax\nmov r8, rsp\nmov r11, rdx\nmov rdi, r8\nrep stosq\nmovsx eax, byte ptr [r9]\ntest al, al\njz loc_163B\nnop dword ptr [rax+rax+00h]\nloc_15B0:\ncmp al, 20h ; ' '\njz short loc_1628\nsub eax, 61h ; 'a'\ncdqe\nmov edi, [rsp+rax*4+78h+var_78]\nlea edx, [rdi+1]\ncmp ecx, edx\nmov [rsp+rax*4+78h+var_78], edx\ncmovl ecx, edx\nmovsx eax, byte ptr [r9+1]\nadd r9, 1\ntest al, al\njnz short loc_15B0\nloc_15D4:\nxor eax, eax\nxor edi, edi\nnop dword ptr [rax+rax+00000000h]\nloc_15E0:\nmov edx, [r8+rax*4]\nmov [rsi+rax*4], edx\ncmp edx, ecx\njnz short loc_15F9\nmovsxd rdx, edi\nlea r9d, [rax+61h]\nadd edi, 1\nmov [r10+rdx], r9b\nloc_15F9:\nadd rax, 1\ncmp rax, 1Ah\njnz short loc_15E0\nmovsxd rdi, edi\nmov [r11], ecx\nmov byte ptr [r10+rdi], 0\nmov rax, [rsp+78h+var_10]\nsub rax, fs:28h\njnz short loc_163F\nadd rsp, 78h\nretn\nloc_1628:\nmovsx eax, byte ptr [r9+1]\nadd r9, 1\ntest al, al\njnz loc_15B0\njmp short loc_15D4\nloc_163B:\nxor ecx, ecx\njmp short loc_15D4\nloc_163F:\ncall ___stack_chk_fail", + "ida_pseudo": "unsigned __int64 __fastcall func0(_BYTE *a1, __int64 a2, int *a3, __int64 a4)\n{\n _BYTE *v4; // r9\n int v7; // ecx\n int v8; // eax\n __int64 v9; // rax\n int v10; // edx\n __int64 v11; // rax\n int v12; // edi\n int v13; // edx\n __int64 v14; // rdx\n _DWORD v16[26]; // [rsp+0h] [rbp-78h] BYREF\n unsigned __int64 v17; // [rsp+68h] [rbp-10h]\n\n v4 = a1;\n v17 = __readfsqword(0x28u);\n memset(v16, 0, sizeof(v16));\n v7 = 0;\n v8 = (char)*a1;\n if ( *a1 )\n {\n do\n {\n while ( (_BYTE)v8 == 32 )\n {\n v8 = (char)*++v4;\n if ( !(_BYTE)v8 )\n goto LABEL_6;\n }\n v9 = v8 - 97;\n v10 = v16[v9] + 1;\n v16[v9] = v10;\n if ( v7 < v10 )\n v7 = v10;\n v8 = (char)*++v4;\n }\n while ( (_BYTE)v8 );\n }\n else\n {\n v7 = 0;\n }\nLABEL_6:\n v11 = 0LL;\n v12 = 0;\n do\n {\n v13 = v16[v11];\n *(_DWORD *)(a2 + 4 * v11) = v13;\n if ( v13 == v7 )\n {\n v14 = v12++;\n *(_BYTE *)(a4 + v14) = v11 + 97;\n }\n ++v11;\n }\n while ( v11 != 26 );\n *a3 = v7;\n *(_BYTE *)(a4 + v12) = 0;\n return v17 - __readfsqword(0x28u);\n}", + "ida_strip_asm": "sub_1570:\nendbr64\nsub rsp, 78h\nmov r9, rdi\nmov r10, rcx\nmov ecx, 0Dh\nmov rax, fs:28h\nmov [rsp+78h+var_10], rax\nxor eax, eax\nmov r8, rsp\nmov r11, rdx\nmov rdi, r8\nrep stosq\nmovsx eax, byte ptr [r9]\ntest al, al\njz loc_163B\nnop dword ptr [rax+rax+00h]\nloc_15B0:\ncmp al, 20h ; ' '\njz short loc_1628\nsub eax, 61h ; 'a'\ncdqe\nmov edi, [rsp+rax*4+78h+var_78]\nlea edx, [rdi+1]\ncmp ecx, edx\nmov [rsp+rax*4+78h+var_78], edx\ncmovl ecx, edx\nmovsx eax, byte ptr [r9+1]\nadd r9, 1\ntest al, al\njnz short loc_15B0\nloc_15D4:\nxor eax, eax\nxor edi, edi\nnop dword ptr [rax+rax+00000000h]\nloc_15E0:\nmov edx, [r8+rax*4]\nmov [rsi+rax*4], edx\ncmp edx, ecx\njnz short loc_15F9\nmovsxd rdx, edi\nlea r9d, [rax+61h]\nadd edi, 1\nmov [r10+rdx], r9b\nloc_15F9:\nadd rax, 1\ncmp rax, 1Ah\njnz short loc_15E0\nmovsxd rdi, edi\nmov [r11], ecx\nmov byte ptr [r10+rdi], 0\nmov rax, [rsp+78h+var_10]\nsub rax, fs:28h\njnz short loc_163F\nadd rsp, 78h\nretn\nloc_1628:\nmovsx eax, byte ptr [r9+1]\nadd r9, 1\ntest al, al\njnz loc_15B0\njmp short loc_15D4\nloc_163B:\nxor ecx, ecx\njmp short loc_15D4\nloc_163F:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_1570(_BYTE *a1, __int64 a2, int *a3, __int64 a4)\n{\n _BYTE *v4; // r9\n int v7; // ecx\n int v8; // eax\n __int64 v9; // rax\n int v10; // edx\n __int64 v11; // rax\n int v12; // edi\n int v13; // edx\n __int64 v14; // rdx\n _DWORD v16[26]; // [rsp+0h] [rbp-78h] BYREF\n unsigned __int64 v17; // [rsp+68h] [rbp-10h]\n\n v4 = a1;\n v17 = __readfsqword(0x28u);\n memset(v16, 0, sizeof(v16));\n v7 = 0;\n v8 = (char)*a1;\n if ( *a1 )\n {\n do\n {\n while ( (_BYTE)v8 == 32 )\n {\n v8 = (char)*++v4;\n if ( !(_BYTE)v8 )\n goto LABEL_6;\n }\n v9 = v8 - 97;\n v10 = v16[v9] + 1;\n v16[v9] = v10;\n if ( v7 < v10 )\n v7 = v10;\n v8 = (char)*++v4;\n }\n while ( (_BYTE)v8 );\n }\n else\n {\n v7 = 0;\n }\nLABEL_6:\n v11 = 0LL;\n v12 = 0;\n do\n {\n v13 = v16[v11];\n *(_DWORD *)(a2 + 4 * v11) = v13;\n if ( v13 == v7 )\n {\n v14 = v12++;\n *(_BYTE *)(a4 + v14) = v11 + 97;\n }\n ++v11;\n }\n while ( v11 != 26 );\n *a3 = v7;\n *(_BYTE *)(a4 + v12) = 0;\n return v17 - __readfsqword(0x28u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_1570(uint8_t *a1, long long a2, int *a3, long long a4) {\n uint8_t *v4;\n int v7;\n int v8;\n long long v9;\n int v10;\n long long v11;\n int v12;\n int v13;\n long long v14;\n uint32_t v16[26];\n unsigned long long v17;\n v4 = a1;\n v17 = __readfsqword(40u);\n memset(v16, 0, sizeof(v16));\n v7 = 0;\n v8 = (char)*a1;\n if (*a1) {\n do {\n while ((uint8_t)v8 == 32) {\n v8 = (char)*++v4;\n if (!(uint8_t)v8) goto LABEL_6;\n }\n v9 = v8 - 97;\n v10 = v16[v9] + 1;\n v16[v9] = v10;\n if (v7 < v10) v7 = v10;\n v8 = (char)*++v4;\n } while ((uint8_t)v8);\n } else {\n v7 = 0;\n }\nLABEL_6:\n v11 = 0LL;\n v12 = 0;\n do {\n v13 = v16[v11];\n *(uint32_t *)(a2 + 4 * v11) = v13;\n if (v13 == v7) {\n v14 = v12++;\n *(uint8_t *)(a4 + v14) = v11 + 97;\n }\n ++v11;\n } while (v11 != 26);\n *a3 = v7;\n *(uint8_t *)(a4 + v12) = 0;\n return v17 - __readfsqword(40u);\n}", + "ida_pseudo_norm": "unsigned long long func0(uint8_t *a1, long long a2, int *a3, long long a4) {\n uint8_t *v4;\n int v7;\n int v8;\n long long v9;\n int v10;\n long long v11;\n int v12;\n int v13;\n long long v14;\n uint32_t v16[26];\n unsigned long long v17;\n v4 = a1;\n v17 = __readfsqword(40u);\n memset(v16, 0, sizeof(v16));\n v7 = 0;\n v8 = (char)*a1;\n if (*a1) {\n do {\n while ((uint8_t)v8 == 32) {\n v8 = (char)*++v4;\n if (!(uint8_t)v8) goto LABEL_6;\n }\n v9 = v8 - 97;\n v10 = v16[v9] + 1;\n v16[v9] = v10;\n if (v7 < v10) v7 = v10;\n v8 = (char)*++v4;\n } while ((uint8_t)v8);\n } else {\n v7 = 0;\n }\nLABEL_6:\n v11 = 0LL;\n v12 = 0;\n do {\n v13 = v16[v11];\n *(uint32_t *)(a2 + 4 * v11) = v13;\n if (v13 == v7) {\n v14 = v12++;\n *(uint8_t *)(a4 + v14) = v11 + 97;\n }\n ++v11;\n } while (v11 != 26);\n *a3 = v7;\n *(uint8_t *)(a4 + v12) = 0;\n return v17 - __readfsqword(40u);\n}" + }, + { + "index": "HumanEval-C-112", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n#include \n", + "func": "void func0(const char *s, const char *c, char *result, char *palindrome) {\n int len = strlen(s);\n char *n = malloc((len + 1) * sizeof(char));\n int ni = 0;\n for (int i = 0; s[i] != '\\0'; i++) {\n const char *temp = c;\n bool found = false;\n while (*temp != '\\0') {\n if (s[i] == *temp) {\n found = true;\n break;\n }\n temp++;\n }\n if (!found) {\n n[ni++] = s[i];\n }\n }\n n[ni] = '\\0';\n int n_len = strlen(n);\n bool is_palindrome = true;\n for (int i = 0; i < n_len / 2; i++) {\n if (n[i] != n[n_len - 1 - i]) {\n is_palindrome = false;\n break;\n }\n }\n strcpy(result, n);\n strcpy(palindrome, is_palindrome ? \"True\" : \"False\");\n free(n);\n}", + "test": "#include \n#include \n\nint main() {\n char result[100];\n char palindrome[6];\n\n func0(\"abcde\", \"ae\", result, palindrome);\n assert(strcmp(result, \"bcd\") == 0 && strcmp(palindrome, \"False\") == 0);\n\n func0(\"abcdef\", \"b\", result, palindrome);\n assert(strcmp(result, \"acdef\") == 0 && strcmp(palindrome, \"False\") == 0);\n\n func0(\"abcdedcba\", \"ab\", result, palindrome);\n assert(strcmp(result, \"cdedc\") == 0 && strcmp(palindrome, \"True\") == 0);\n\n func0(\"dwik\", \"w\", result, palindrome);\n assert(strcmp(result, \"dik\") == 0 && strcmp(palindrome, \"False\") == 0);\n\n func0(\"a\", \"a\", result, palindrome);\n assert(strcmp(result, \"\") == 0 && strcmp(palindrome, \"True\") == 0);\n\n func0(\"abcdedcba\", \"\", result, palindrome);\n assert(strcmp(result, \"abcdedcba\") == 0 && strcmp(palindrome, \"True\") == 0);\n\n func0(\"abcdedcba\", \"v\", result, palindrome);\n assert(strcmp(result, \"abcdedcba\") == 0 && strcmp(palindrome, \"True\") == 0);\n\n func0(\"vabba\", \"v\", result, palindrome);\n assert(strcmp(result, \"abba\") == 0 && strcmp(palindrome, \"True\") == 0);\n\n func0(\"mamma\", \"mia\", result, palindrome);\n assert(strcmp(result, \"\") == 0 && strcmp(palindrome, \"True\") == 0);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+s], rdi\nmov [rbp+var_40], rsi\nmov [rbp+dest], rdx\nmov [rbp+var_50], rcx\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_18], eax\nmov eax, [rbp+var_18]\nadd eax, 1\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+src], rax\nmov [rbp+var_24], 0\nmov [rbp+var_20], 0\njmp short loc_12CC\nloc_1258:\nmov rax, [rbp+var_40]\nmov [rbp+var_10], rax\nmov [rbp+var_26], 0\njmp short loc_128C\nloc_1266:\nmov eax, [rbp+var_20]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov rax, [rbp+var_10]\nmovzx eax, byte ptr [rax]\ncmp dl, al\njnz short loc_1287\nmov [rbp+var_26], 1\njmp short loc_1297\nloc_1287:\nadd [rbp+var_10], 1\nloc_128C:\nmov rax, [rbp+var_10]\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1266\nloc_1297:\nmovzx eax, [rbp+var_26]\nxor eax, 1\ntest al, al\njz short loc_12C8\nmov eax, [rbp+var_20]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_24]\nlea edx, [rax+1]\nmov [rbp+var_24], edx\nmovsxd rdx, eax\nmov rax, [rbp+src]\nadd rdx, rax\nmovzx eax, byte ptr [rcx]\nmov [rdx], al\nloc_12C8:\nadd [rbp+var_20], 1\nloc_12CC:\nmov eax, [rbp+var_20]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_1258\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, [rbp+src]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+src]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_14], eax\nmov [rbp+var_25], 1\nmov [rbp+var_1C], 0\njmp short loc_1344\nloc_1310:\nmov eax, [rbp+var_1C]\nmovsxd rdx, eax\nmov rax, [rbp+src]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_14]\nsub eax, 1\nsub eax, [rbp+var_1C]\nmovsxd rcx, eax\nmov rax, [rbp+src]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njz short loc_1340\nmov [rbp+var_25], 0\njmp short loc_1355\nloc_1340:\nadd [rbp+var_1C], 1\nloc_1344:\nmov eax, [rbp+var_14]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\ncmp [rbp+var_1C], eax\njl short loc_1310\nloc_1355:\nmov rdx, [rbp+src]\nmov rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\ncmp [rbp+var_25], 0\njz short loc_1377\nlea rax, src; \"True\"\njmp short loc_137E\nloc_1377:\nlea rax, aFalse; \"False\"\nloc_137E:\nmov rdx, [rbp+var_50]\nmov rsi, rax; src\nmov rdi, rdx; dest\ncall _strcpy\nmov rax, [rbp+src]\nmov rdi, rax; ptr\ncall _free\nnop\nleave\nretn", + "ida_pseudo": "void __fastcall func0(const char *a1, _BYTE *a2, char *a3, char *a4)\n{\n int v4; // eax\n const char *v5; // rax\n char v8; // [rsp+2Ah] [rbp-26h]\n char v9; // [rsp+2Bh] [rbp-25h]\n int v10; // [rsp+2Ch] [rbp-24h]\n int i; // [rsp+30h] [rbp-20h]\n int j; // [rsp+34h] [rbp-1Ch]\n int v13; // [rsp+38h] [rbp-18h]\n int v14; // [rsp+3Ch] [rbp-14h]\n _BYTE *v15; // [rsp+40h] [rbp-10h]\n char *src; // [rsp+48h] [rbp-8h]\n\n v13 = strlen(a1);\n src = (char *)malloc(v13 + 1);\n v10 = 0;\n for ( i = 0; a1[i]; ++i )\n {\n v15 = a2;\n v8 = 0;\n while ( *v15 )\n {\n if ( a1[i] == *v15 )\n {\n v8 = 1;\n break;\n }\n ++v15;\n }\n if ( v8 != 1 )\n {\n v4 = v10++;\n src[v4] = a1[i];\n }\n }\n src[v10] = 0;\n v14 = strlen(src);\n v9 = 1;\n for ( j = 0; j < v14 / 2; ++j )\n {\n if ( src[j] != src[v14 - 1 - j] )\n {\n v9 = 0;\n break;\n }\n }\n strcpy(a3, src);\n if ( v9 )\n v5 = \"True\";\n else\n v5 = \"False\";\n strcpy(a4, v5);\n free(src);\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+s], rdi\nmov [rbp+var_40], rsi\nmov [rbp+dest], rdx\nmov [rbp+var_50], rcx\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_18], eax\nmov eax, [rbp+var_18]\nadd eax, 1\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+src], rax\nmov [rbp+var_24], 0\nmov [rbp+var_20], 0\njmp short loc_12CC\nloc_1258:\nmov rax, [rbp+var_40]\nmov [rbp+var_10], rax\nmov [rbp+var_26], 0\njmp short loc_128C\nloc_1266:\nmov eax, [rbp+var_20]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov rax, [rbp+var_10]\nmovzx eax, byte ptr [rax]\ncmp dl, al\njnz short loc_1287\nmov [rbp+var_26], 1\njmp short loc_1297\nloc_1287:\nadd [rbp+var_10], 1\nloc_128C:\nmov rax, [rbp+var_10]\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1266\nloc_1297:\nmovzx eax, [rbp+var_26]\nxor eax, 1\ntest al, al\njz short loc_12C8\nmov eax, [rbp+var_20]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_24]\nlea edx, [rax+1]\nmov [rbp+var_24], edx\nmovsxd rdx, eax\nmov rax, [rbp+src]\nadd rdx, rax\nmovzx eax, byte ptr [rcx]\nmov [rdx], al\nloc_12C8:\nadd [rbp+var_20], 1\nloc_12CC:\nmov eax, [rbp+var_20]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_1258\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, [rbp+src]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+src]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_14], eax\nmov [rbp+var_25], 1\nmov [rbp+var_1C], 0\njmp short loc_1344\nloc_1310:\nmov eax, [rbp+var_1C]\nmovsxd rdx, eax\nmov rax, [rbp+src]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_14]\nsub eax, 1\nsub eax, [rbp+var_1C]\nmovsxd rcx, eax\nmov rax, [rbp+src]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njz short loc_1340\nmov [rbp+var_25], 0\njmp short loc_1355\nloc_1340:\nadd [rbp+var_1C], 1\nloc_1344:\nmov eax, [rbp+var_14]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\ncmp [rbp+var_1C], eax\njl short loc_1310\nloc_1355:\nmov rdx, [rbp+src]\nmov rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\ncmp [rbp+var_25], 0\njz short loc_1377\nlea rax, src; \"True\"\njmp short loc_137E\nloc_1377:\nlea rax, aFalse; \"False\"\nloc_137E:\nmov rdx, [rbp+var_50]\nmov rsi, rax; src\nmov rdi, rdx; dest\ncall _strcpy\nmov rax, [rbp+src]\nmov rdi, rax; ptr\ncall _free\nnop\nleave\nretn", + "ida_strip_pseudo": "void __fastcall sub_1209(const char *a1, _BYTE *a2, char *a3, char *a4)\n{\n int v4; // eax\n const char *v5; // rax\n char v8; // [rsp+2Ah] [rbp-26h]\n char v9; // [rsp+2Bh] [rbp-25h]\n int v10; // [rsp+2Ch] [rbp-24h]\n int i; // [rsp+30h] [rbp-20h]\n int j; // [rsp+34h] [rbp-1Ch]\n int v13; // [rsp+38h] [rbp-18h]\n int v14; // [rsp+3Ch] [rbp-14h]\n _BYTE *v15; // [rsp+40h] [rbp-10h]\n char *src; // [rsp+48h] [rbp-8h]\n\n v13 = strlen(a1);\n src = (char *)malloc(v13 + 1);\n v10 = 0;\n for ( i = 0; a1[i]; ++i )\n {\n v15 = a2;\n v8 = 0;\n while ( *v15 )\n {\n if ( a1[i] == *v15 )\n {\n v8 = 1;\n break;\n }\n ++v15;\n }\n if ( v8 != 1 )\n {\n v4 = v10++;\n src[v4] = a1[i];\n }\n }\n src[v10] = 0;\n v14 = strlen(src);\n v9 = 1;\n for ( j = 0; j < v14 / 2; ++j )\n {\n if ( src[j] != src[v14 - 1 - j] )\n {\n v9 = 0;\n break;\n }\n }\n strcpy(a3, src);\n if ( v9 )\n v5 = \"True\";\n else\n v5 = \"False\";\n strcpy(a4, v5);\n free(src);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1209(const char *a1, uint8_t *a2, char *a3, char *a4) {\n int v4;\n const char *v5;\n char v8;\n char v9;\n int v10;\n int i;\n int j;\n int v13;\n int v14;\n uint8_t *v15;\n char *src;\n v13 = strlen(a1);\n src = (char *)malloc(v13 + 1);\n v10 = 0;\n for (i = 0; a1[i]; ++i) {\n v15 = a2;\n v8 = 0;\n while (*v15) {\n if (a1[i] == *v15) {\n v8 = 1;\n break;\n }\n ++v15;\n }\n if (v8 != 1) {\n v4 = v10++;\n src[v4] = a1[i];\n }\n }\n src[v10] = 0;\n v14 = strlen(src);\n v9 = 1;\n for (j = 0; j < v14 / 2; ++j) {\n if (src[j] != src[v14 - 1 - j]) {\n v9 = 0;\n break;\n }\n }\n strcpy(a3, src);\n if (v9)\n v5 = \"True\";\n else\n v5 = \"False\";\n strcpy(a4, v5);\n free(src);\n}", + "ida_pseudo_norm": "void func0(const char *a1, uint8_t *a2, char *a3, char *a4) {\n int v4;\n const char *v5;\n char v8;\n char v9;\n int v10;\n int i;\n int j;\n int v13;\n int v14;\n uint8_t *v15;\n char *src;\n v13 = strlen(a1);\n src = (char *)malloc(v13 + 1);\n v10 = 0;\n for (i = 0; a1[i]; ++i) {\n v15 = a2;\n v8 = 0;\n while (*v15) {\n if (a1[i] == *v15) {\n v8 = 1;\n break;\n }\n ++v15;\n }\n if (v8 != 1) {\n v4 = v10++;\n src[v4] = a1[i];\n }\n }\n src[v10] = 0;\n v14 = strlen(src);\n v9 = 1;\n for (j = 0; j < v14 / 2; ++j) {\n if (src[j] != src[v14 - 1 - j]) {\n v9 = 0;\n break;\n }\n }\n strcpy(a3, src);\n if (v9)\n v5 = \"True\";\n else\n v5 = \"False\";\n strcpy(a4, v5);\n free(src);\n}" + }, + { + "index": "HumanEval-C-112", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n#include \n", + "func": "void func0(const char *s, const char *c, char *result, char *palindrome) {\n int len = strlen(s);\n char *n = malloc((len + 1) * sizeof(char));\n int ni = 0;\n for (int i = 0; s[i] != '\\0'; i++) {\n const char *temp = c;\n bool found = false;\n while (*temp != '\\0') {\n if (s[i] == *temp) {\n found = true;\n break;\n }\n temp++;\n }\n if (!found) {\n n[ni++] = s[i];\n }\n }\n n[ni] = '\\0';\n int n_len = strlen(n);\n bool is_palindrome = true;\n for (int i = 0; i < n_len / 2; i++) {\n if (n[i] != n[n_len - 1 - i]) {\n is_palindrome = false;\n break;\n }\n }\n strcpy(result, n);\n strcpy(palindrome, is_palindrome ? \"True\" : \"False\");\n free(n);\n}", + "test": "#include \n#include \n\nint main() {\n char result[100];\n char palindrome[6];\n\n func0(\"abcde\", \"ae\", result, palindrome);\n assert(strcmp(result, \"bcd\") == 0 && strcmp(palindrome, \"False\") == 0);\n\n func0(\"abcdef\", \"b\", result, palindrome);\n assert(strcmp(result, \"acdef\") == 0 && strcmp(palindrome, \"False\") == 0);\n\n func0(\"abcdedcba\", \"ab\", result, palindrome);\n assert(strcmp(result, \"cdedc\") == 0 && strcmp(palindrome, \"True\") == 0);\n\n func0(\"dwik\", \"w\", result, palindrome);\n assert(strcmp(result, \"dik\") == 0 && strcmp(palindrome, \"False\") == 0);\n\n func0(\"a\", \"a\", result, palindrome);\n assert(strcmp(result, \"\") == 0 && strcmp(palindrome, \"True\") == 0);\n\n func0(\"abcdedcba\", \"\", result, palindrome);\n assert(strcmp(result, \"abcdedcba\") == 0 && strcmp(palindrome, \"True\") == 0);\n\n func0(\"abcdedcba\", \"v\", result, palindrome);\n assert(strcmp(result, \"abcdedcba\") == 0 && strcmp(palindrome, \"True\") == 0);\n\n func0(\"vabba\", \"v\", result, palindrome);\n assert(strcmp(result, \"abba\") == 0 && strcmp(palindrome, \"True\") == 0);\n\n func0(\"mamma\", \"mia\", result, palindrome);\n assert(strcmp(result, \"\") == 0 && strcmp(palindrome, \"True\") == 0);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r14, rdi\nmov rbp, rsi\nmov r13, rdx\nmov r12, rcx\ncall _strlen\nlea edi, [rax+1]\nmovsxd rdi, edi; size\ncall _malloc\nmov rbx, rax\nmovzx ecx, byte ptr [r14]\ntest cl, cl\njz short loc_127D\nmovzx edi, byte ptr [rbp+0]\nlea rsi, [r14+1]\nmov r8d, 0\njmp short loc_1262\nloc_124C:\nmovsxd rax, r8d\nmov [rbx+rax], cl\nlea r8d, [r8+1]\nloc_1256:\nadd rsi, 1\nmovzx ecx, byte ptr [rsi-1]\ntest cl, cl\njz short loc_1283\nloc_1262:\nmov rdx, rbp\nmov eax, edi\ntest dil, dil\njz short loc_124C\nloc_126C:\ncmp al, cl\njz short loc_1256\nadd rdx, 1\nmovzx eax, byte ptr [rdx]\ntest al, al\njnz short loc_126C\njmp short loc_124C\nloc_127D:\nmov r8d, 0\nloc_1283:\nmovsxd r8, r8d\nmov byte ptr [rbx+r8], 0\nmov rdi, rbx; s\ncall _strlen\nmov ecx, eax\nshr ecx, 1Fh\nadd ecx, eax\nsar ecx, 1\ncmp eax, 1\njle short loc_12D6\ncdqe\nlea rdx, [rbx+rax-1]\nmov eax, 0\nloc_12AD:\nmovzx esi, byte ptr [rdx]\ncmp [rbx+rax], sil\njnz short loc_12EA\nadd rax, 1\nsub rdx, 1\ncmp ecx, eax\njg short loc_12AD\nmov rsi, rbx; src\nmov rdi, r13; dest\ncall _strcpy\nlea rsi, aTrue; \"True\"\njmp short loc_12FC\nloc_12D6:\nmov rsi, rbx; src\nmov rdi, r13; dest\ncall _strcpy\nlea rsi, aTrue; \"True\"\njmp short loc_12FC\nloc_12EA:\nmov rsi, rbx; src\nmov rdi, r13; dest\ncall _strcpy\nlea rsi, src; \"False\"\nloc_12FC:\nmov rdi, r12; dest\ncall _strcpy\nmov rdi, rbx; ptr\ncall _free\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "void __fastcall func0(const char *a1, _BYTE *a2, char *a3, char *a4)\n{\n int v8; // eax\n char *v9; // rbx\n char v10; // cl\n char v11; // di\n char *v12; // rsi\n int v13; // r8d\n _BYTE *v14; // rdx\n char v15; // al\n int v16; // eax\n int v17; // ecx\n char *v18; // rdx\n __int64 v19; // rax\n const char *v20; // rsi\n\n v8 = strlen(a1);\n v9 = (char *)malloc(v8 + 1);\n v10 = *a1;\n if ( *a1 )\n {\n v11 = *a2;\n v12 = (char *)(a1 + 1);\n v13 = 0;\n do\n {\n v14 = a2;\n v15 = v11;\n if ( v11 )\n {\n while ( v15 != v10 )\n {\n v15 = *++v14;\n if ( !*v14 )\n goto LABEL_3;\n }\n }\n else\n {\nLABEL_3:\n v9[v13++] = v10;\n }\n v10 = *v12++;\n }\n while ( v10 );\n }\n else\n {\n v13 = 0;\n }\n v9[v13] = 0;\n v16 = strlen(v9);\n v17 = v16 / 2;\n if ( v16 <= 1 )\n {\nLABEL_14:\n strcpy(a3, v9);\n v20 = \"True\";\n }\n else\n {\n v18 = &v9[v16 - 1];\n v19 = 0LL;\n while ( v9[v19] == *v18 )\n {\n ++v19;\n --v18;\n if ( v17 <= (int)v19 )\n goto LABEL_14;\n }\n strcpy(a3, v9);\n v20 = \"False\";\n }\n strcpy(a4, v20);\n free(v9);\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r14, rdi\nmov rbp, rsi\nmov r13, rdx\nmov r12, rcx\ncall _strlen\nlea edi, [rax+1]\nmovsxd rdi, edi; size\ncall _malloc\nmov rbx, rax\nmovzx ecx, byte ptr [r14]\ntest cl, cl\njz short loc_127D\nmovzx edi, byte ptr [rbp+0]\nlea rsi, [r14+1]\nmov r8d, 0\njmp short loc_1262\nloc_124C:\nmovsxd rax, r8d\nmov [rbx+rax], cl\nlea r8d, [r8+1]\nloc_1256:\nadd rsi, 1\nmovzx ecx, byte ptr [rsi-1]\ntest cl, cl\njz short loc_1283\nloc_1262:\nmov rdx, rbp\nmov eax, edi\ntest dil, dil\njz short loc_124C\nloc_126C:\ncmp al, cl\njz short loc_1256\nadd rdx, 1\nmovzx eax, byte ptr [rdx]\ntest al, al\njnz short loc_126C\njmp short loc_124C\nloc_127D:\nmov r8d, 0\nloc_1283:\nmovsxd r8, r8d\nmov byte ptr [rbx+r8], 0\nmov rdi, rbx; s\ncall _strlen\nmov ecx, eax\nshr ecx, 1Fh\nadd ecx, eax\nsar ecx, 1\ncmp eax, 1\njle short loc_12D6\ncdqe\nlea rdx, [rbx+rax-1]\nmov eax, 0\nloc_12AD:\nmovzx esi, byte ptr [rdx]\ncmp [rbx+rax], sil\njnz short loc_12EA\nadd rax, 1\nsub rdx, 1\ncmp ecx, eax\njg short loc_12AD\nmov rsi, rbx; src\nmov rdi, r13; dest\ncall _strcpy\nlea rsi, aTrue; \"True\"\njmp short loc_12FC\nloc_12D6:\nmov rsi, rbx; src\nmov rdi, r13; dest\ncall _strcpy\nlea rsi, aTrue; \"True\"\njmp short loc_12FC\nloc_12EA:\nmov rsi, rbx; src\nmov rdi, r13; dest\ncall _strcpy\nlea rsi, src; \"False\"\nloc_12FC:\nmov rdi, r12; dest\ncall _strcpy\nmov rdi, rbx; ptr\ncall _free\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "void __fastcall sub_1209(const char *a1, _BYTE *a2, char *a3, char *a4)\n{\n int v8; // eax\n char *v9; // rbx\n char v10; // cl\n char v11; // di\n char *v12; // rsi\n int v13; // r8d\n _BYTE *v14; // rdx\n char v15; // al\n int v16; // eax\n int v17; // ecx\n char *v18; // rdx\n __int64 v19; // rax\n const char *v20; // rsi\n\n v8 = strlen(a1);\n v9 = (char *)malloc(v8 + 1);\n v10 = *a1;\n if ( *a1 )\n {\n v11 = *a2;\n v12 = (char *)(a1 + 1);\n v13 = 0;\n do\n {\n v14 = a2;\n v15 = v11;\n if ( v11 )\n {\n while ( v15 != v10 )\n {\n v15 = *++v14;\n if ( !*v14 )\n goto LABEL_3;\n }\n }\n else\n {\nLABEL_3:\n v9[v13++] = v10;\n }\n v10 = *v12++;\n }\n while ( v10 );\n }\n else\n {\n v13 = 0;\n }\n v9[v13] = 0;\n v16 = strlen(v9);\n v17 = v16 / 2;\n if ( v16 <= 1 )\n {\nLABEL_14:\n strcpy(a3, v9);\n v20 = \"True\";\n }\n else\n {\n v18 = &v9[v16 - 1];\n v19 = 0LL;\n while ( v9[v19] == *v18 )\n {\n ++v19;\n --v18;\n if ( v17 <= (int)v19 )\n goto LABEL_14;\n }\n strcpy(a3, v9);\n v20 = \"False\";\n }\n strcpy(a4, v20);\n free(v9);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1209(const char *a1, uint8_t *a2, char *a3, char *a4) {\n int v8;\n char *v9;\n char v10;\n char v11;\n char *v12;\n int v13;\n uint8_t *v14;\n char v15;\n int v16;\n int v17;\n char *v18;\n long long v19;\n const char *v20;\n v8 = strlen(a1);\n v9 = (char *)malloc(v8 + 1);\n v10 = *a1;\n if (*a1) {\n v11 = *a2;\n v12 = (char *)(a1 + 1);\n v13 = 0;\n do {\n v14 = a2;\n v15 = v11;\n if (v11) {\n while (v15 != v10) {\n v15 = *++v14;\n if (!*v14) goto LABEL_3;\n }\n } else {\n LABEL_3:\n v9[v13++] = v10;\n }\n v10 = *v12++;\n } while (v10);\n } else {\n v13 = 0;\n }\n v9[v13] = 0;\n v16 = strlen(v9);\n v17 = v16 / 2;\n if (v16 <= 1) {\n LABEL_14:\n strcpy(a3, v9);\n v20 = \"True\";\n } else {\n v18 = &v9[v16 - 1];\n v19 = 0LL;\n while (v9[v19] == *v18) {\n ++v19;\n --v18;\n if (v17 <= (int)v19) goto LABEL_14;\n }\n strcpy(a3, v9);\n v20 = \"False\";\n }\n strcpy(a4, v20);\n free(v9);\n}", + "ida_pseudo_norm": "void func0(const char *a1, uint8_t *a2, char *a3, char *a4) {\n int v8;\n char *v9;\n char v10;\n char v11;\n char *v12;\n int v13;\n uint8_t *v14;\n char v15;\n int v16;\n int v17;\n char *v18;\n long long v19;\n const char *v20;\n v8 = strlen(a1);\n v9 = (char *)malloc(v8 + 1);\n v10 = *a1;\n if (*a1) {\n v11 = *a2;\n v12 = (char *)(a1 + 1);\n v13 = 0;\n do {\n v14 = a2;\n v15 = v11;\n if (v11) {\n while (v15 != v10) {\n v15 = *++v14;\n if (!*v14) goto LABEL_3;\n }\n } else {\n LABEL_3:\n v9[v13++] = v10;\n }\n v10 = *v12++;\n } while (v10);\n } else {\n v13 = 0;\n }\n v9[v13] = 0;\n v16 = strlen(v9);\n v17 = v16 / 2;\n if (v16 <= 1) {\n LABEL_14:\n strcpy(a3, v9);\n v20 = \"True\";\n } else {\n v18 = &v9[v16 - 1];\n v19 = 0LL;\n while (v9[v19] == *v18) {\n ++v19;\n --v18;\n if (v17 <= (int)v19) goto LABEL_14;\n }\n strcpy(a3, v9);\n v20 = \"False\";\n }\n strcpy(a4, v20);\n free(v9);\n}" + }, + { + "index": "HumanEval-C-112", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n#include \n", + "func": "void func0(const char *s, const char *c, char *result, char *palindrome) {\n int len = strlen(s);\n char *n = malloc((len + 1) * sizeof(char));\n int ni = 0;\n for (int i = 0; s[i] != '\\0'; i++) {\n const char *temp = c;\n bool found = false;\n while (*temp != '\\0') {\n if (s[i] == *temp) {\n found = true;\n break;\n }\n temp++;\n }\n if (!found) {\n n[ni++] = s[i];\n }\n }\n n[ni] = '\\0';\n int n_len = strlen(n);\n bool is_palindrome = true;\n for (int i = 0; i < n_len / 2; i++) {\n if (n[i] != n[n_len - 1 - i]) {\n is_palindrome = false;\n break;\n }\n }\n strcpy(result, n);\n strcpy(palindrome, is_palindrome ? \"True\" : \"False\");\n free(n);\n}", + "test": "#include \n#include \n\nint main() {\n char result[100];\n char palindrome[6];\n\n func0(\"abcde\", \"ae\", result, palindrome);\n assert(strcmp(result, \"bcd\") == 0 && strcmp(palindrome, \"False\") == 0);\n\n func0(\"abcdef\", \"b\", result, palindrome);\n assert(strcmp(result, \"acdef\") == 0 && strcmp(palindrome, \"False\") == 0);\n\n func0(\"abcdedcba\", \"ab\", result, palindrome);\n assert(strcmp(result, \"cdedc\") == 0 && strcmp(palindrome, \"True\") == 0);\n\n func0(\"dwik\", \"w\", result, palindrome);\n assert(strcmp(result, \"dik\") == 0 && strcmp(palindrome, \"False\") == 0);\n\n func0(\"a\", \"a\", result, palindrome);\n assert(strcmp(result, \"\") == 0 && strcmp(palindrome, \"True\") == 0);\n\n func0(\"abcdedcba\", \"\", result, palindrome);\n assert(strcmp(result, \"abcdedcba\") == 0 && strcmp(palindrome, \"True\") == 0);\n\n func0(\"abcdedcba\", \"v\", result, palindrome);\n assert(strcmp(result, \"abcdedcba\") == 0 && strcmp(palindrome, \"True\") == 0);\n\n func0(\"vabba\", \"v\", result, palindrome);\n assert(strcmp(result, \"abba\") == 0 && strcmp(palindrome, \"True\") == 0);\n\n func0(\"mamma\", \"mia\", result, palindrome);\n assert(strcmp(result, \"\") == 0 && strcmp(palindrome, \"True\") == 0);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r14\nmov r14, rsi\npush r13\nmov r13, rdi\npush r12\npush rbp\nmov rbp, rdx\npush rbx\nmov rbx, rcx\ncall _strlen\nlea edi, [rax+1]\nmovsxd rdi, edi; size\ncall _malloc\nmovzx ecx, byte ptr [r13+0]\nmov r12, rax\ntest cl, cl\njz short loc_1605\nmovzx r8d, byte ptr [r14]\nlea rsi, [r13+1]\nxor edi, edi\nxchg ax, ax\nloc_15D0:\nmov rdx, r14\nmov eax, r8d\ntest r8b, r8b\njnz short loc_15F0\njmp loc_1678\nloc_15E0:\nmovzx eax, byte ptr [rdx+1]\nadd rdx, 1\ntest al, al\njz loc_1678\nloc_15F0:\ncmp al, cl\njnz short loc_15E0\nmovzx ecx, byte ptr [rsi]\nadd rsi, 1\ntest cl, cl\njnz short loc_15D0\nloc_15FF:\nmovsxd rax, edi\nadd rax, r12\nloc_1605:\nmov byte ptr [rax], 0\nmov rdi, r12; s\ncall _strlen\nmov esi, eax\nshr esi, 1Fh\nadd esi, eax\nsar esi, 1\ncmp eax, 1\njle short loc_1697\nlea ecx, [rax-1]\nxor edx, edx\nmovsxd rcx, ecx\nadd rcx, r12\njmp short loc_163C\nloc_1630:\nadd rdx, 1\nsub rcx, 1\ncmp esi, edx\njle short loc_1697\nloc_163C:\nmovzx edi, byte ptr [rcx]\ncmp [r12+rdx], dil\njz short loc_1630\nmov rsi, r12; src\nlea rdx, [rax+1]; n\nmov rdi, rbp; dest\ncall _memcpy\nlea rsi, src; \"False\"\nloc_165B:\nmov rdi, rbx; dest\ncall _strcpy\npop rbx\nmov rdi, r12; ptr\npop rbp\npop r12\npop r13\npop r14\njmp _free\nloc_1678:\nmovsxd rax, edi\nadd rsi, 1\nadd edi, 1\nmov [r12+rax], cl\nmovzx ecx, byte ptr [rsi-1]\ntest cl, cl\njnz loc_15D0\njmp loc_15FF\nloc_1697:\nmov rsi, r12; src\nlea rdx, [rax+1]; n\nmov rdi, rbp; dest\ncall _memcpy\nlea rsi, aTrue; \"True\"\njmp short loc_165B", + "ida_pseudo": "void __fastcall func0(const char *a1, _BYTE *a2, void *a3, char *a4)\n{\n int v7; // eax\n char *v8; // rax\n char v9; // cl\n char *v10; // r12\n char v11; // r8\n char *v12; // rsi\n int v13; // edi\n _BYTE *v14; // rdx\n char v15; // al\n size_t v16; // rax\n __int64 v17; // rdx\n char *v18; // rcx\n const char *v19; // rsi\n __int64 v20; // rax\n\n v7 = strlen(a1);\n v8 = (char *)malloc(v7 + 1);\n v9 = *a1;\n v10 = v8;\n if ( *a1 )\n {\n v11 = *a2;\n v12 = (char *)(a1 + 1);\n v13 = 0;\n do\n {\n while ( 1 )\n {\n v14 = a2;\n v15 = v11;\n if ( v11 )\n break;\nLABEL_15:\n v20 = v13;\n ++v12;\n ++v13;\n v10[v20] = v9;\n v9 = *(v12 - 1);\n if ( !v9 )\n goto LABEL_8;\n }\n while ( v15 != v9 )\n {\n v15 = *++v14;\n if ( !v15 )\n goto LABEL_15;\n }\n v9 = *v12++;\n }\n while ( v9 );\nLABEL_8:\n v8 = &v10[v13];\n }\n *v8 = 0;\n v16 = strlen(v10);\n if ( (int)v16 <= 1 )\n {\nLABEL_17:\n memcpy(a3, v10, v16 + 1);\n v19 = \"True\";\n }\n else\n {\n v17 = 0LL;\n v18 = &v10[(int)v16 - 1];\n while ( v10[v17] == *v18 )\n {\n ++v17;\n --v18;\n if ( (int)v16 / 2 <= (int)v17 )\n goto LABEL_17;\n }\n memcpy(a3, v10, v16 + 1);\n v19 = \"False\";\n }\n strcpy(a4, v19);\n free(v10);\n}", + "ida_strip_asm": "sub_1590:\nendbr64\npush r14\nmov r14, rsi\npush r13\nmov r13, rdi\npush r12\npush rbp\nmov rbp, rdx\npush rbx\nmov rbx, rcx\ncall _strlen\nlea edi, [rax+1]\nmovsxd rdi, edi; size\ncall _malloc\nmovzx ecx, byte ptr [r13+0]\nmov r12, rax\ntest cl, cl\njz short loc_1605\nmovzx r8d, byte ptr [r14]\nlea rsi, [r13+1]\nxor edi, edi\nxchg ax, ax\nloc_15D0:\nmov rdx, r14\nmov eax, r8d\ntest r8b, r8b\njnz short loc_15F0\njmp loc_1678\nloc_15E0:\nmovzx eax, byte ptr [rdx+1]\nadd rdx, 1\ntest al, al\njz loc_1678\nloc_15F0:\ncmp al, cl\njnz short loc_15E0\nmovzx ecx, byte ptr [rsi]\nadd rsi, 1\ntest cl, cl\njnz short loc_15D0\nloc_15FF:\nmovsxd rax, edi\nadd rax, r12\nloc_1605:\nmov byte ptr [rax], 0\nmov rdi, r12; s\ncall _strlen\nmov esi, eax\nshr esi, 1Fh\nadd esi, eax\nsar esi, 1\ncmp eax, 1\njle short loc_1697\nlea ecx, [rax-1]\nxor edx, edx\nmovsxd rcx, ecx\nadd rcx, r12\njmp short loc_163C\nloc_1630:\nadd rdx, 1\nsub rcx, 1\ncmp esi, edx\njle short loc_1697\nloc_163C:\nmovzx edi, byte ptr [rcx]\ncmp [r12+rdx], dil\njz short loc_1630\nmov rsi, r12; src\nlea rdx, [rax+1]; n\nmov rdi, rbp; dest\ncall _memcpy\nlea rsi, src; \"False\"\nloc_165B:\nmov rdi, rbx; dest\ncall _strcpy\npop rbx\nmov rdi, r12; ptr\npop rbp\npop r12\npop r13\npop r14\njmp _free\nloc_1678:\nmovsxd rax, edi\nadd rsi, 1\nadd edi, 1\nmov [r12+rax], cl\nmovzx ecx, byte ptr [rsi-1]\ntest cl, cl\njnz loc_15D0\njmp loc_15FF\nloc_1697:\nmov rsi, r12; src\nlea rdx, [rax+1]; n\nmov rdi, rbp; dest\ncall _memcpy\nlea rsi, aTrue; \"True\"\njmp short loc_165B", + "ida_strip_pseudo": "void __fastcall sub_1590(const char *a1, _BYTE *a2, void *a3, char *a4)\n{\n int v7; // eax\n char *v8; // rax\n char v9; // cl\n char *v10; // r12\n char v11; // r8\n char *v12; // rsi\n int v13; // edi\n _BYTE *v14; // rdx\n char v15; // al\n size_t v16; // rax\n __int64 v17; // rdx\n char *v18; // rcx\n const char *v19; // rsi\n __int64 v20; // rax\n\n v7 = strlen(a1);\n v8 = (char *)malloc(v7 + 1);\n v9 = *a1;\n v10 = v8;\n if ( *a1 )\n {\n v11 = *a2;\n v12 = (char *)(a1 + 1);\n v13 = 0;\n do\n {\n while ( 1 )\n {\n v14 = a2;\n v15 = v11;\n if ( v11 )\n break;\nLABEL_15:\n v20 = v13;\n ++v12;\n ++v13;\n v10[v20] = v9;\n v9 = *(v12 - 1);\n if ( !v9 )\n goto LABEL_8;\n }\n while ( v15 != v9 )\n {\n v15 = *++v14;\n if ( !v15 )\n goto LABEL_15;\n }\n v9 = *v12++;\n }\n while ( v9 );\nLABEL_8:\n v8 = &v10[v13];\n }\n *v8 = 0;\n v16 = strlen(v10);\n if ( (int)v16 <= 1 )\n {\nLABEL_17:\n memcpy(a3, v10, v16 + 1);\n v19 = \"True\";\n }\n else\n {\n v17 = 0LL;\n v18 = &v10[(int)v16 - 1];\n while ( v10[v17] == *v18 )\n {\n ++v17;\n --v18;\n if ( (int)v16 / 2 <= (int)v17 )\n goto LABEL_17;\n }\n memcpy(a3, v10, v16 + 1);\n v19 = \"False\";\n }\n strcpy(a4, v19);\n free(v10);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1590(const char *a1, uint8_t *a2, void *a3, char *a4) {\n int v7;\n char *v8;\n char v9;\n char *v10;\n char v11;\n char *v12;\n int v13;\n uint8_t *v14;\n char v15;\n unsigned int v16;\n long long v17;\n char *v18;\n const char *v19;\n long long v20;\n v7 = strlen(a1);\n v8 = (char *)malloc(v7 + 1);\n v9 = *a1;\n v10 = v8;\n if (*a1) {\n v11 = *a2;\n v12 = (char *)(a1 + 1);\n v13 = 0;\n do {\n while (1) {\n v14 = a2;\n v15 = v11;\n if (v11) break;\n LABEL_15:\n v20 = v13;\n ++v12;\n ++v13;\n v10[v20] = v9;\n v9 = *(v12 - 1);\n if (!v9) goto LABEL_8;\n }\n while (v15 != v9) {\n v15 = *++v14;\n if (!v15) goto LABEL_15;\n }\n v9 = *v12++;\n } while (v9);\n LABEL_8:\n v8 = &v10[v13];\n }\n *v8 = 0;\n v16 = strlen(v10);\n if ((int)v16 <= 1) {\n LABEL_17:\n memcpy(a3, v10, v16 + 1);\n v19 = \"True\";\n } else {\n v17 = 0LL;\n v18 = &v10[(int)v16 - 1];\n while (v10[v17] == *v18) {\n ++v17;\n --v18;\n if ((int)v16 / 2 <= (int)v17) goto LABEL_17;\n }\n memcpy(a3, v10, v16 + 1);\n v19 = \"False\";\n }\n strcpy(a4, v19);\n free(v10);\n}", + "ida_pseudo_norm": "void func0(const char *a1, uint8_t *a2, void *a3, char *a4) {\n int v7;\n char *v8;\n char v9;\n char *v10;\n char v11;\n char *v12;\n int v13;\n uint8_t *v14;\n char v15;\n unsigned int v16;\n long long v17;\n char *v18;\n const char *v19;\n long long v20;\n v7 = strlen(a1);\n v8 = (char *)malloc(v7 + 1);\n v9 = *a1;\n v10 = v8;\n if (*a1) {\n v11 = *a2;\n v12 = (char *)(a1 + 1);\n v13 = 0;\n do {\n while (1) {\n v14 = a2;\n v15 = v11;\n if (v11) break;\n LABEL_15:\n v20 = v13;\n ++v12;\n ++v13;\n v10[v20] = v9;\n v9 = *(v12 - 1);\n if (!v9) goto LABEL_8;\n }\n while (v15 != v9) {\n v15 = *++v14;\n if (!v15) goto LABEL_15;\n }\n v9 = *v12++;\n } while (v9);\n LABEL_8:\n v8 = &v10[v13];\n }\n *v8 = 0;\n v16 = strlen(v10);\n if ((int)v16 <= 1) {\n LABEL_17:\n memcpy(a3, v10, v16 + 1);\n v19 = \"True\";\n } else {\n v17 = 0LL;\n v18 = &v10[(int)v16 - 1];\n while (v10[v17] == *v18) {\n ++v17;\n --v18;\n if ((int)v16 / 2 <= (int)v17) goto LABEL_17;\n }\n memcpy(a3, v10, v16 + 1);\n v19 = \"False\";\n }\n strcpy(a4, v19);\n free(v10);\n}" + }, + { + "index": "HumanEval-C-112", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n#include \n", + "func": "void func0(const char *s, const char *c, char *result, char *palindrome) {\n int len = strlen(s);\n char *n = malloc((len + 1) * sizeof(char));\n int ni = 0;\n for (int i = 0; s[i] != '\\0'; i++) {\n const char *temp = c;\n bool found = false;\n while (*temp != '\\0') {\n if (s[i] == *temp) {\n found = true;\n break;\n }\n temp++;\n }\n if (!found) {\n n[ni++] = s[i];\n }\n }\n n[ni] = '\\0';\n int n_len = strlen(n);\n bool is_palindrome = true;\n for (int i = 0; i < n_len / 2; i++) {\n if (n[i] != n[n_len - 1 - i]) {\n is_palindrome = false;\n break;\n }\n }\n strcpy(result, n);\n strcpy(palindrome, is_palindrome ? \"True\" : \"False\");\n free(n);\n}", + "test": "#include \n#include \n\nint main() {\n char result[100];\n char palindrome[6];\n\n func0(\"abcde\", \"ae\", result, palindrome);\n assert(strcmp(result, \"bcd\") == 0 && strcmp(palindrome, \"False\") == 0);\n\n func0(\"abcdef\", \"b\", result, palindrome);\n assert(strcmp(result, \"acdef\") == 0 && strcmp(palindrome, \"False\") == 0);\n\n func0(\"abcdedcba\", \"ab\", result, palindrome);\n assert(strcmp(result, \"cdedc\") == 0 && strcmp(palindrome, \"True\") == 0);\n\n func0(\"dwik\", \"w\", result, palindrome);\n assert(strcmp(result, \"dik\") == 0 && strcmp(palindrome, \"False\") == 0);\n\n func0(\"a\", \"a\", result, palindrome);\n assert(strcmp(result, \"\") == 0 && strcmp(palindrome, \"True\") == 0);\n\n func0(\"abcdedcba\", \"\", result, palindrome);\n assert(strcmp(result, \"abcdedcba\") == 0 && strcmp(palindrome, \"True\") == 0);\n\n func0(\"abcdedcba\", \"v\", result, palindrome);\n assert(strcmp(result, \"abcdedcba\") == 0 && strcmp(palindrome, \"True\") == 0);\n\n func0(\"vabba\", \"v\", result, palindrome);\n assert(strcmp(result, \"abba\") == 0 && strcmp(palindrome, \"True\") == 0);\n\n func0(\"mamma\", \"mia\", result, palindrome);\n assert(strcmp(result, \"\") == 0 && strcmp(palindrome, \"True\") == 0);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r14\nmov r14, rsi\npush r13\nmov r13, rdi\npush r12\npush rbp\nmov rbp, rdx\npush rbx\nmov rbx, rcx\ncall _strlen\nlea edi, [rax+1]\nmovsxd rdi, edi; size\ncall _malloc\nmovzx ecx, byte ptr [r13+0]\nmov r12, rax\ntest cl, cl\njz short loc_1605\nmovzx r8d, byte ptr [r14]\nlea rsi, [r13+1]\nxor edi, edi\nxchg ax, ax\nloc_15D0:\nmov rdx, r14\nmov eax, r8d\ntest r8b, r8b\njnz short loc_15F0\njmp loc_1678\nloc_15E0:\nmovzx eax, byte ptr [rdx+1]\nadd rdx, 1\ntest al, al\njz loc_1678\nloc_15F0:\ncmp al, cl\njnz short loc_15E0\nmovzx ecx, byte ptr [rsi]\nadd rsi, 1\ntest cl, cl\njnz short loc_15D0\nloc_15FF:\nmovsxd rax, edi\nadd rax, r12\nloc_1605:\nmov byte ptr [rax], 0\nmov rdi, r12; s\ncall _strlen\nmov esi, eax\nshr esi, 1Fh\nadd esi, eax\nsar esi, 1\ncmp eax, 1\njle short loc_1697\nlea ecx, [rax-1]\nxor edx, edx\nmovsxd rcx, ecx\nadd rcx, r12\njmp short loc_163C\nloc_1630:\nadd rdx, 1\nsub rcx, 1\ncmp esi, edx\njle short loc_1697\nloc_163C:\nmovzx edi, byte ptr [rcx]\ncmp [r12+rdx], dil\njz short loc_1630\nmov rsi, r12; src\nlea rdx, [rax+1]; n\nmov rdi, rbp; dest\ncall _memcpy\nlea rsi, src; \"False\"\nloc_165B:\nmov rdi, rbx; dest\ncall _strcpy\npop rbx\nmov rdi, r12; ptr\npop rbp\npop r12\npop r13\npop r14\njmp _free\nloc_1678:\nmovsxd rax, edi\nadd rsi, 1\nadd edi, 1\nmov [r12+rax], cl\nmovzx ecx, byte ptr [rsi-1]\ntest cl, cl\njnz loc_15D0\njmp loc_15FF\nloc_1697:\nmov rsi, r12; src\nlea rdx, [rax+1]; n\nmov rdi, rbp; dest\ncall _memcpy\nlea rsi, aTrue; \"True\"\njmp short loc_165B", + "ida_pseudo": "void __fastcall func0(const char *a1, _BYTE *a2, void *a3, char *a4)\n{\n int v7; // eax\n char *v8; // rax\n char v9; // cl\n char *v10; // r12\n char v11; // r8\n char *v12; // rsi\n int v13; // edi\n _BYTE *v14; // rdx\n char v15; // al\n size_t v16; // rax\n __int64 v17; // rdx\n char *v18; // rcx\n const char *v19; // rsi\n __int64 v20; // rax\n\n v7 = strlen(a1);\n v8 = (char *)malloc(v7 + 1);\n v9 = *a1;\n v10 = v8;\n if ( *a1 )\n {\n v11 = *a2;\n v12 = (char *)(a1 + 1);\n v13 = 0;\n do\n {\n while ( 1 )\n {\n v14 = a2;\n v15 = v11;\n if ( v11 )\n break;\nLABEL_15:\n v20 = v13;\n ++v12;\n ++v13;\n v10[v20] = v9;\n v9 = *(v12 - 1);\n if ( !v9 )\n goto LABEL_8;\n }\n while ( v15 != v9 )\n {\n v15 = *++v14;\n if ( !v15 )\n goto LABEL_15;\n }\n v9 = *v12++;\n }\n while ( v9 );\nLABEL_8:\n v8 = &v10[v13];\n }\n *v8 = 0;\n v16 = strlen(v10);\n if ( (int)v16 <= 1 )\n {\nLABEL_17:\n memcpy(a3, v10, v16 + 1);\n v19 = \"True\";\n }\n else\n {\n v17 = 0LL;\n v18 = &v10[(int)v16 - 1];\n while ( v10[v17] == *v18 )\n {\n ++v17;\n --v18;\n if ( (int)v16 / 2 <= (int)v17 )\n goto LABEL_17;\n }\n memcpy(a3, v10, v16 + 1);\n v19 = \"False\";\n }\n strcpy(a4, v19);\n free(v10);\n}", + "ida_strip_asm": "sub_1590:\nendbr64\npush r14\nmov r14, rsi\npush r13\nmov r13, rdi\npush r12\npush rbp\nmov rbp, rdx\npush rbx\nmov rbx, rcx\ncall _strlen\nlea edi, [rax+1]\nmovsxd rdi, edi; size\ncall _malloc\nmovzx ecx, byte ptr [r13+0]\nmov r12, rax\ntest cl, cl\njz short loc_1605\nmovzx r8d, byte ptr [r14]\nlea rsi, [r13+1]\nxor edi, edi\nxchg ax, ax\nloc_15D0:\nmov rdx, r14\nmov eax, r8d\ntest r8b, r8b\njnz short loc_15F0\njmp loc_1678\nloc_15E0:\nmovzx eax, byte ptr [rdx+1]\nadd rdx, 1\ntest al, al\njz loc_1678\nloc_15F0:\ncmp al, cl\njnz short loc_15E0\nmovzx ecx, byte ptr [rsi]\nadd rsi, 1\ntest cl, cl\njnz short loc_15D0\nloc_15FF:\nmovsxd rax, edi\nadd rax, r12\nloc_1605:\nmov byte ptr [rax], 0\nmov rdi, r12; s\ncall _strlen\nmov esi, eax\nshr esi, 1Fh\nadd esi, eax\nsar esi, 1\ncmp eax, 1\njle short loc_1697\nlea ecx, [rax-1]\nxor edx, edx\nmovsxd rcx, ecx\nadd rcx, r12\njmp short loc_163C\nloc_1630:\nadd rdx, 1\nsub rcx, 1\ncmp esi, edx\njle short loc_1697\nloc_163C:\nmovzx edi, byte ptr [rcx]\ncmp [r12+rdx], dil\njz short loc_1630\nmov rsi, r12; src\nlea rdx, [rax+1]; n\nmov rdi, rbp; dest\ncall _memcpy\nlea rsi, src; \"False\"\nloc_165B:\nmov rdi, rbx; dest\ncall _strcpy\npop rbx\nmov rdi, r12; ptr\npop rbp\npop r12\npop r13\npop r14\njmp _free\nloc_1678:\nmovsxd rax, edi\nadd rsi, 1\nadd edi, 1\nmov [r12+rax], cl\nmovzx ecx, byte ptr [rsi-1]\ntest cl, cl\njnz loc_15D0\njmp loc_15FF\nloc_1697:\nmov rsi, r12; src\nlea rdx, [rax+1]; n\nmov rdi, rbp; dest\ncall _memcpy\nlea rsi, aTrue; \"True\"\njmp short loc_165B", + "ida_strip_pseudo": "void __fastcall sub_1590(const char *a1, _BYTE *a2, void *a3, char *a4)\n{\n int v7; // eax\n char *v8; // rax\n char v9; // cl\n char *v10; // r12\n char v11; // r8\n char *v12; // rsi\n int v13; // edi\n _BYTE *v14; // rdx\n char v15; // al\n size_t v16; // rax\n __int64 v17; // rdx\n char *v18; // rcx\n const char *v19; // rsi\n __int64 v20; // rax\n\n v7 = strlen(a1);\n v8 = (char *)malloc(v7 + 1);\n v9 = *a1;\n v10 = v8;\n if ( *a1 )\n {\n v11 = *a2;\n v12 = (char *)(a1 + 1);\n v13 = 0;\n do\n {\n while ( 1 )\n {\n v14 = a2;\n v15 = v11;\n if ( v11 )\n break;\nLABEL_15:\n v20 = v13;\n ++v12;\n ++v13;\n v10[v20] = v9;\n v9 = *(v12 - 1);\n if ( !v9 )\n goto LABEL_8;\n }\n while ( v15 != v9 )\n {\n v15 = *++v14;\n if ( !v15 )\n goto LABEL_15;\n }\n v9 = *v12++;\n }\n while ( v9 );\nLABEL_8:\n v8 = &v10[v13];\n }\n *v8 = 0;\n v16 = strlen(v10);\n if ( (int)v16 <= 1 )\n {\nLABEL_17:\n memcpy(a3, v10, v16 + 1);\n v19 = \"True\";\n }\n else\n {\n v17 = 0LL;\n v18 = &v10[(int)v16 - 1];\n while ( v10[v17] == *v18 )\n {\n ++v17;\n --v18;\n if ( (int)v16 / 2 <= (int)v17 )\n goto LABEL_17;\n }\n memcpy(a3, v10, v16 + 1);\n v19 = \"False\";\n }\n strcpy(a4, v19);\n free(v10);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1590(const char *a1, uint8_t *a2, void *a3, char *a4) {\n int v7;\n char *v8;\n char v9;\n char *v10;\n char v11;\n char *v12;\n int v13;\n uint8_t *v14;\n char v15;\n unsigned int v16;\n long long v17;\n char *v18;\n const char *v19;\n long long v20;\n v7 = strlen(a1);\n v8 = (char *)malloc(v7 + 1);\n v9 = *a1;\n v10 = v8;\n if (*a1) {\n v11 = *a2;\n v12 = (char *)(a1 + 1);\n v13 = 0;\n do {\n while (1) {\n v14 = a2;\n v15 = v11;\n if (v11) break;\n LABEL_15:\n v20 = v13;\n ++v12;\n ++v13;\n v10[v20] = v9;\n v9 = *(v12 - 1);\n if (!v9) goto LABEL_8;\n }\n while (v15 != v9) {\n v15 = *++v14;\n if (!v15) goto LABEL_15;\n }\n v9 = *v12++;\n } while (v9);\n LABEL_8:\n v8 = &v10[v13];\n }\n *v8 = 0;\n v16 = strlen(v10);\n if ((int)v16 <= 1) {\n LABEL_17:\n memcpy(a3, v10, v16 + 1);\n v19 = \"True\";\n } else {\n v17 = 0LL;\n v18 = &v10[(int)v16 - 1];\n while (v10[v17] == *v18) {\n ++v17;\n --v18;\n if ((int)v16 / 2 <= (int)v17) goto LABEL_17;\n }\n memcpy(a3, v10, v16 + 1);\n v19 = \"False\";\n }\n strcpy(a4, v19);\n free(v10);\n}", + "ida_pseudo_norm": "void func0(const char *a1, uint8_t *a2, void *a3, char *a4) {\n int v7;\n char *v8;\n char v9;\n char *v10;\n char v11;\n char *v12;\n int v13;\n uint8_t *v14;\n char v15;\n unsigned int v16;\n long long v17;\n char *v18;\n const char *v19;\n long long v20;\n v7 = strlen(a1);\n v8 = (char *)malloc(v7 + 1);\n v9 = *a1;\n v10 = v8;\n if (*a1) {\n v11 = *a2;\n v12 = (char *)(a1 + 1);\n v13 = 0;\n do {\n while (1) {\n v14 = a2;\n v15 = v11;\n if (v11) break;\n LABEL_15:\n v20 = v13;\n ++v12;\n ++v13;\n v10[v20] = v9;\n v9 = *(v12 - 1);\n if (!v9) goto LABEL_8;\n }\n while (v15 != v9) {\n v15 = *++v14;\n if (!v15) goto LABEL_15;\n }\n v9 = *v12++;\n } while (v9);\n LABEL_8:\n v8 = &v10[v13];\n }\n *v8 = 0;\n v16 = strlen(v10);\n if ((int)v16 <= 1) {\n LABEL_17:\n memcpy(a3, v10, v16 + 1);\n v19 = \"True\";\n } else {\n v17 = 0LL;\n v18 = &v10[(int)v16 - 1];\n while (v10[v17] == *v18) {\n ++v17;\n --v18;\n if ((int)v16 / 2 <= (int)v17) goto LABEL_17;\n }\n memcpy(a3, v10, v16 + 1);\n v19 = \"False\";\n }\n strcpy(a4, v19);\n free(v10);\n}" + }, + { + "index": "HumanEval-C-113", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char **func0(char *lst[], int size) {\n char **out = malloc(size * sizeof(char *));\n for (int i = 0; i < size; i++) {\n int sum = 0;\n for (int j = 0; lst[i][j] != '\\0'; j++) {\n if (lst[i][j] >= '0' && lst[i][j] <= '9' && (lst[i][j] - '0') % 2 == 1)\n sum += 1;\n }\n out[i] = malloc(100);\n sprintf(out[i],\n \"the number of odd elements %d in the string %d of the %d input.\",\n sum, sum, sum);\n }\n return out;\n}", + "test": "#include \n#include \n#include \n\nint issame(char **a, char **b, int size) {\n for (int i = 0; i < size; i++) {\n if (strcmp(a[i], b[i]) != 0) {\n return 0;\n }\n }\n return 1;\n}\n\nint main() {\n char *input1[] = {\"1234567\"};\n char *expected1[] = {\"the number of odd elements 4 in the string 4 of the 4 input.\"};\n char **result1 = func0(input1, 1);\n assert(issame(result1, expected1, 1));\n\n char *input2[] = {\"3\", \"11111111\"};\n char *expected2[] = {\n \"the number of odd elements 1 in the string 1 of the 1 input.\",\n \"the number of odd elements 8 in the string 8 of the 8 input.\"\n };\n char **result2 = func0(input2, 2);\n assert(issame(result2, expected2, 2));\n\n char *input3[] = {\"271\", \"137\", \"314\"};\n char *expected3[] = {\n \"the number of odd elements 2 in the string 2 of the 2 input.\",\n \"the number of odd elements 3 in the string 3 of the 3 input.\",\n \"the number of odd elements 2 in the string 2 of the 2 input.\"\n };\n char **result3 = func0(input3, 3);\n assert(issame(result3, expected3, 3));\n\n // Free the allocated memory\n for (int i = 0; i < 1; i++) free(result1[i]);\n free(result1);\n for (int i = 0; i < 2; i++) free(result2[i]);\n free(result2);\n for (int i = 0; i < 3; i++) free(result3[i]);\n free(result3);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov eax, [rbp+var_3C]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_24], 0\njmp loc_134A\nloc_121E:\nmov [rbp+var_20], 0\nmov [rbp+var_1C], 0\njmp loc_12C3\nloc_1231:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_1C]\ncdqe\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 2Fh ; '/'\njle short loc_12BF\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_1C]\ncdqe\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 39h ; '9'\njg short loc_12BF\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_1C]\ncdqe\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nlea edx, [rax-30h]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\ncmp eax, 1\njnz short loc_12BF\nadd [rbp+var_20], 1\nloc_12BF:\nadd [rbp+var_1C], 1\nloc_12C3:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_1C]\ncdqe\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_1231\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nlea rbx, [rdx+rax]\nmov edi, 64h ; 'd'; size\ncall _malloc\nmov [rbx], rax\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov esi, [rbp+var_20]\nmov ecx, [rbp+var_20]\nmov edx, [rbp+var_20]\nmov r8d, esi\nlea rsi, format; \"the number of odd elements %d in the st\"...\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nadd [rbp+var_24], 1\nloc_134A:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_3C]\njl loc_121E\nmov rax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+1Ch] [rbp-24h]\n int v4; // [rsp+20h] [rbp-20h]\n int j; // [rsp+24h] [rbp-1Ch]\n _QWORD *v6; // [rsp+28h] [rbp-18h]\n\n v6 = malloc(8LL * a2);\n for ( i = 0; i < a2; ++i )\n {\n v4 = 0;\n for ( j = 0; *(_BYTE *)(*(_QWORD *)(8LL * i + a1) + j); ++j )\n {\n if ( *(char *)(*(_QWORD *)(8LL * i + a1) + j) > 47\n && *(char *)(*(_QWORD *)(8LL * i + a1) + j) <= 57\n && (*(char *)(*(_QWORD *)(8LL * i + a1) + j) - 48) % 2 == 1 )\n {\n ++v4;\n }\n }\n v6[i] = malloc(0x64uLL);\n sprintf((char *)v6[i], \"the number of odd elements %d in the string %d of the %d input.\", v4, v4, v4);\n }\n return v6;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov eax, [rbp+var_3C]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_24], 0\njmp loc_134A\nloc_121E:\nmov [rbp+var_20], 0\nmov [rbp+var_1C], 0\njmp loc_12C3\nloc_1231:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_1C]\ncdqe\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 2Fh ; '/'\njle short loc_12BF\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_1C]\ncdqe\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 39h ; '9'\njg short loc_12BF\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_1C]\ncdqe\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nlea edx, [rax-30h]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\ncmp eax, 1\njnz short loc_12BF\nadd [rbp+var_20], 1\nloc_12BF:\nadd [rbp+var_1C], 1\nloc_12C3:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_1C]\ncdqe\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_1231\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nlea rbx, [rdx+rax]\nmov edi, 64h ; 'd'; size\ncall _malloc\nmov [rbx], rax\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov esi, [rbp+var_20]\nmov ecx, [rbp+var_20]\nmov edx, [rbp+var_20]\nmov r8d, esi\nlea rsi, format; \"the number of odd elements %d in the st\"...\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nadd [rbp+var_24], 1\nloc_134A:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_3C]\njl loc_121E\nmov rax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11E9(__int64 a1, int a2)\n{\n int i; // [rsp+1Ch] [rbp-24h]\n int v4; // [rsp+20h] [rbp-20h]\n int j; // [rsp+24h] [rbp-1Ch]\n _QWORD *v6; // [rsp+28h] [rbp-18h]\n\n v6 = malloc(8LL * a2);\n for ( i = 0; i < a2; ++i )\n {\n v4 = 0;\n for ( j = 0; *(_BYTE *)(*(_QWORD *)(8LL * i + a1) + j); ++j )\n {\n if ( *(char *)(*(_QWORD *)(8LL * i + a1) + j) > 47\n && *(char *)(*(_QWORD *)(8LL * i + a1) + j) <= 57\n && (*(char *)(*(_QWORD *)(8LL * i + a1) + j) - 48) % 2 == 1 )\n {\n ++v4;\n }\n }\n v6[i] = malloc(0x64uLL);\n sprintf((char *)v6[i], \"the number of odd elements %d in the string %d of the %d input.\", v4, v4, v4);\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11E9(long long a1, int a2) {\n int i;\n int v4;\n int j;\n uint64_t *v6;\n v6 = malloc(8LL * a2);\n for (i = 0; i < a2; ++i) {\n v4 = 0;\n for (j = 0; *(uint8_t *)(*(uint64_t *)(8LL * i + a1) + j); ++j) {\n if (*(char *)(*(uint64_t *)(8LL * i + a1) + j) > 47 &&\n *(char *)(*(uint64_t *)(8LL * i + a1) + j) <= 57 &&\n (*(char *)(*(uint64_t *)(8LL * i + a1) + j) - 48) % 2 == 1) {\n ++v4;\n }\n }\n v6[i] = malloc(100uLL);\n sprintf((char *)v6[i],\n \"the number of odd elements %d in the string %d of the %d input.\",\n v4, v4, v4);\n }\n return v6;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, int a2) {\n int i;\n int v4;\n int j;\n uint64_t *v6;\n v6 = malloc(8LL * a2);\n for (i = 0; i < a2; ++i) {\n v4 = 0;\n for (j = 0; *(uint8_t *)(*(uint64_t *)(8LL * i + a1) + j); ++j) {\n if (*(char *)(*(uint64_t *)(8LL * i + a1) + j) > 47 &&\n *(char *)(*(uint64_t *)(8LL * i + a1) + j) <= 57 &&\n (*(char *)(*(uint64_t *)(8LL * i + a1) + j) - 48) % 2 == 1) {\n ++v4;\n }\n }\n v6[i] = malloc(100uLL);\n sprintf((char *)v6[i],\n \"the number of odd elements %d in the string %d of the %d input.\",\n v4, v4, v4);\n }\n return v6;\n}" + }, + { + "index": "HumanEval-C-113", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char **func0(char *lst[], int size) {\n char **out = malloc(size * sizeof(char *));\n for (int i = 0; i < size; i++) {\n int sum = 0;\n for (int j = 0; lst[i][j] != '\\0'; j++) {\n if (lst[i][j] >= '0' && lst[i][j] <= '9' && (lst[i][j] - '0') % 2 == 1)\n sum += 1;\n }\n out[i] = malloc(100);\n sprintf(out[i],\n \"the number of odd elements %d in the string %d of the %d input.\",\n sum, sum, sum);\n }\n return out;\n}", + "test": "#include \n#include \n#include \n\nint issame(char **a, char **b, int size) {\n for (int i = 0; i < size; i++) {\n if (strcmp(a[i], b[i]) != 0) {\n return 0;\n }\n }\n return 1;\n}\n\nint main() {\n char *input1[] = {\"1234567\"};\n char *expected1[] = {\"the number of odd elements 4 in the string 4 of the 4 input.\"};\n char **result1 = func0(input1, 1);\n assert(issame(result1, expected1, 1));\n\n char *input2[] = {\"3\", \"11111111\"};\n char *expected2[] = {\n \"the number of odd elements 1 in the string 1 of the 1 input.\",\n \"the number of odd elements 8 in the string 8 of the 8 input.\"\n };\n char **result2 = func0(input2, 2);\n assert(issame(result2, expected2, 2));\n\n char *input3[] = {\"271\", \"137\", \"314\"};\n char *expected3[] = {\n \"the number of odd elements 2 in the string 2 of the 2 input.\",\n \"the number of odd elements 3 in the string 3 of the 3 input.\",\n \"the number of odd elements 2 in the string 2 of the 2 input.\"\n };\n char **result3 = func0(input3, 3);\n assert(issame(result3, expected3, 3));\n\n // Free the allocated memory\n for (int i = 0; i < 1; i++) free(result1[i]);\n free(result1);\n for (int i = 0; i < 2; i++) free(result2[i]);\n free(result2);\n for (int i = 0; i < 3; i++) free(result3[i]);\n free(result3);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r13, rdi\nmov ebx, esi\nmovsxd r14, esi\nshl r14, 3\nmov rdi, r14; size\ncall _malloc\nmov r15, rax\ntest ebx, ebx\njle loc_12B9\nmov rbp, r13\nmov r12, rax\nadd r13, r14\nlea r14, aTheNumberOfOdd; \"the number of odd elements %d in the st\"...\njmp short loc_12A3\nloc_122C:\nadd rdx, 1\nmovzx eax, byte ptr [rdx-1]\ntest al, al\njz short loc_125F\nloc_1238:\nlea ecx, [rax-30h]\ncmp cl, 9\nja short loc_122C\nmovsx eax, al\nsub eax, 30h ; '0'\nmov ecx, eax\nshr ecx, 1Fh\nadd eax, ecx\nand eax, 1\nsub eax, ecx\ncmp eax, 1\nsetz al\nmovzx eax, al\nadd ebx, eax\njmp short loc_122C\nloc_125F:\nmov edi, 64h ; 'd'; size\ncall _malloc\nmov rdi, rax\nmov [r12], rax\nsub rsp, 8\npush rbx\nmov r9d, ebx\nmov r8d, ebx\nmov rcx, r14\nmov edx, 64h ; 'd'\nmov esi, 2\nmov eax, 0\ncall ___sprintf_chk\nadd rbp, 8\nadd r12, 8\nadd rsp, 10h\ncmp rbp, r13\njz short loc_12B9\nloc_12A3:\nmov rdx, [rbp+0]\nmovzx eax, byte ptr [rdx]\nadd rdx, 1\nmov ebx, 0\ntest al, al\njnz short loc_1238\njmp short loc_125F\nloc_12B9:\nmov rax, r15\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(char **a1, int a2)\n{\n _QWORD *v2; // rax\n _QWORD *v3; // r15\n char **v4; // rbp\n _QWORD *v5; // r12\n __int64 v6; // rdx\n char v7; // al\n int i; // ebx\n void *v9; // rax\n\n v2 = malloc(8LL * a2);\n v3 = v2;\n if ( a2 > 0 )\n {\n v4 = a1;\n v5 = v2;\n do\n {\n v7 = **v4;\n v6 = (__int64)(*v4 + 1);\n for ( i = 0; v7; v7 = *(_BYTE *)(v6 - 1) )\n {\n if ( (unsigned __int8)(v7 - 48) <= 9u )\n i += (v7 - 48) % 2 == 1;\n ++v6;\n }\n v9 = malloc(0x64uLL);\n *v5 = v9;\n __sprintf_chk(v9, 2LL, 100LL, \"the number of odd elements %d in the string %d of the %d input.\", i, i, i);\n ++v4;\n ++v5;\n }\n while ( v4 != &a1[a2] );\n }\n return v3;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r13, rdi\nmov ebx, esi\nmovsxd r14, esi\nshl r14, 3\nmov rdi, r14; size\ncall _malloc\nmov r15, rax\ntest ebx, ebx\njle loc_12B9\nmov rbp, r13\nmov r12, rax\nadd r13, r14\nlea r14, aTheNumberOfOdd; \"the number of odd elements %d in the st\"...\njmp short loc_12A3\nloc_122C:\nadd rdx, 1\nmovzx eax, byte ptr [rdx-1]\ntest al, al\njz short loc_125F\nloc_1238:\nlea ecx, [rax-30h]\ncmp cl, 9\nja short loc_122C\nmovsx eax, al\nsub eax, 30h ; '0'\nmov ecx, eax\nshr ecx, 1Fh\nadd eax, ecx\nand eax, 1\nsub eax, ecx\ncmp eax, 1\nsetz al\nmovzx eax, al\nadd ebx, eax\njmp short loc_122C\nloc_125F:\nmov edi, 64h ; 'd'; size\ncall _malloc\nmov rdi, rax\nmov [r12], rax\nsub rsp, 8\npush rbx\nmov r9d, ebx\nmov r8d, ebx\nmov rcx, r14\nmov edx, 64h ; 'd'\nmov esi, 2\nmov eax, 0\ncall ___sprintf_chk\nadd rbp, 8\nadd r12, 8\nadd rsp, 10h\ncmp rbp, r13\njz short loc_12B9\nloc_12A3:\nmov rdx, [rbp+0]\nmovzx eax, byte ptr [rdx]\nadd rdx, 1\nmov ebx, 0\ntest al, al\njnz short loc_1238\njmp short loc_125F\nloc_12B9:\nmov rax, r15\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11E9(char **a1, int a2)\n{\n _QWORD *v2; // rax\n _QWORD *v3; // r15\n char **v4; // rbp\n _QWORD *v5; // r12\n __int64 v6; // rdx\n char v7; // al\n int i; // ebx\n void *v9; // rax\n\n v2 = malloc(8LL * a2);\n v3 = v2;\n if ( a2 > 0 )\n {\n v4 = a1;\n v5 = v2;\n do\n {\n v7 = **v4;\n v6 = (__int64)(*v4 + 1);\n for ( i = 0; v7; v7 = *(_BYTE *)(v6 - 1) )\n {\n if ( (unsigned __int8)(v7 - 48) <= 9u )\n i += (v7 - 48) % 2 == 1;\n ++v6;\n }\n v9 = malloc(0x64uLL);\n *v5 = v9;\n __sprintf_chk(v9, 2LL, 100LL, \"the number of odd elements %d in the string %d of the %d input.\", i, i, i);\n ++v4;\n ++v5;\n }\n while ( v4 != &a1[a2] );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11E9(char **a1, int a2) {\n uint64_t *v2;\n uint64_t *v3;\n char **v4;\n uint64_t *v5;\n long long v6;\n char v7;\n int i;\n void *v9;\n v2 = malloc(8LL * a2);\n v3 = v2;\n if (a2 > 0) {\n v4 = a1;\n v5 = v2;\n do {\n v7 = **v4;\n v6 = (long long)(*v4 + 1);\n for (i = 0; v7; v7 = *(uint8_t *)(v6 - 1)) {\n if ((unsigned char)(v7 - 48) <= 9u) i += (v7 - 48) % 2 == 1;\n ++v6;\n }\n v9 = malloc(100uLL);\n *v5 = v9;\n __sprintf_chk(\n v9, 2LL, 100LL,\n \"the number of odd elements %d in the string %d of the %d input.\", i,\n i, i);\n ++v4;\n ++v5;\n } while (v4 != &a1[a2]);\n }\n return v3;\n}", + "ida_pseudo_norm": "uint64_t *func0(char **a1, int a2) {\n uint64_t *v2;\n uint64_t *v3;\n char **v4;\n uint64_t *v5;\n long long v6;\n char v7;\n int i;\n void *v9;\n v2 = malloc(8LL * a2);\n v3 = v2;\n if (a2 > 0) {\n v4 = a1;\n v5 = v2;\n do {\n v7 = **v4;\n v6 = (long long)(*v4 + 1);\n for (i = 0; v7; v7 = *(uint8_t *)(v6 - 1)) {\n if ((unsigned char)(v7 - 48) <= 9u) i += (v7 - 48) % 2 == 1;\n ++v6;\n }\n v9 = malloc(100uLL);\n *v5 = v9;\n __sprintf_chk(\n v9, 2LL, 100LL,\n \"the number of odd elements %d in the string %d of the %d input.\", i,\n i, i);\n ++v4;\n ++v5;\n } while (v4 != &a1[a2]);\n }\n return v3;\n}" + }, + { + "index": "HumanEval-C-113", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char **func0(char *lst[], int size) {\n char **out = malloc(size * sizeof(char *));\n for (int i = 0; i < size; i++) {\n int sum = 0;\n for (int j = 0; lst[i][j] != '\\0'; j++) {\n if (lst[i][j] >= '0' && lst[i][j] <= '9' && (lst[i][j] - '0') % 2 == 1)\n sum += 1;\n }\n out[i] = malloc(100);\n sprintf(out[i],\n \"the number of odd elements %d in the string %d of the %d input.\",\n sum, sum, sum);\n }\n return out;\n}", + "test": "#include \n#include \n#include \n\nint issame(char **a, char **b, int size) {\n for (int i = 0; i < size; i++) {\n if (strcmp(a[i], b[i]) != 0) {\n return 0;\n }\n }\n return 1;\n}\n\nint main() {\n char *input1[] = {\"1234567\"};\n char *expected1[] = {\"the number of odd elements 4 in the string 4 of the 4 input.\"};\n char **result1 = func0(input1, 1);\n assert(issame(result1, expected1, 1));\n\n char *input2[] = {\"3\", \"11111111\"};\n char *expected2[] = {\n \"the number of odd elements 1 in the string 1 of the 1 input.\",\n \"the number of odd elements 8 in the string 8 of the 8 input.\"\n };\n char **result2 = func0(input2, 2);\n assert(issame(result2, expected2, 2));\n\n char *input3[] = {\"271\", \"137\", \"314\"};\n char *expected3[] = {\n \"the number of odd elements 2 in the string 2 of the 2 input.\",\n \"the number of odd elements 3 in the string 3 of the 3 input.\",\n \"the number of odd elements 2 in the string 2 of the 2 input.\"\n };\n char **result3 = func0(input3, 3);\n assert(issame(result3, expected3, 3));\n\n // Free the allocated memory\n for (int i = 0; i < 1; i++) free(result1[i]);\n free(result1);\n for (int i = 0; i < 2; i++) free(result2[i]);\n free(result2);\n for (int i = 0; i < 3; i++) free(result3[i]);\n free(result3);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14, rdi\npush r13\npush r12\npush rbp\nmovsxd rbp, esi\npush rbx\nmov rbx, rbp\nshl rbp, 3\nmov rdi, rbp; size\nsub rsp, 8\ncall _malloc\nmov r13, rax\ntest ebx, ebx\njle loc_14C4\nmov rbx, rax\nadd rbp, r14\nlea r12, aTheNumberOfOdd_4; \"the number of odd elements %d in the st\"...\nnop\nloc_1450:\nmov rdx, [r14]\nxor r15d, r15d\nmovzx eax, byte ptr [rdx]\nadd rdx, 1\ntest al, al\njz short loc_1484\nnop dword ptr [rax+00000000h]\nloc_1468:\nlea ecx, [rax-30h]\ncmp cl, 9\nja short loc_1479\nand eax, 1\ncmp al, 1\nsbb r15d, 0FFFFFFFFh\nloc_1479:\nmovzx eax, byte ptr [rdx]\nadd rdx, 1\ntest al, al\njnz short loc_1468\nloc_1484:\nmov edi, 64h ; 'd'; size\nadd r14, 8\nadd rbx, 8\ncall _malloc\nsub rsp, 8\nmov r9d, r15d\nmov r8d, r15d\nmov [rbx-8], rax\nmov rdi, rax\nmov edx, 64h ; 'd'\nmov rcx, r12\npush r15\nmov esi, 2\nxor eax, eax\ncall ___sprintf_chk\npop rax\npop rdx\ncmp r14, rbp\njnz short loc_1450\nloc_14C4:\nadd rsp, 8\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "void *__fastcall func0(char **a1, int a2)\n{\n char **v2; // r14\n void *v3; // rax\n void *v4; // r13\n _QWORD *v5; // rbx\n int v6; // r15d\n char v7; // al\n char *i; // rdx\n void *v9; // rax\n\n v2 = a1;\n v3 = malloc(8LL * a2);\n v4 = v3;\n if ( a2 > 0 )\n {\n v5 = v3;\n do\n {\n v6 = 0;\n v7 = **v2;\n for ( i = *v2 + 1; v7; ++i )\n {\n if ( (unsigned __int8)(v7 - 48) <= 9u )\n v6 -= ((v7 & 1) == 0) - 1;\n v7 = *i;\n }\n ++v2;\n ++v5;\n v9 = malloc(0x64uLL);\n *(v5 - 1) = v9;\n __sprintf_chk(v9, 2LL, 100LL, \"the number of odd elements %d in the string %d of the %d input.\", v6, v6, v6);\n }\n while ( v2 != &a1[a2] );\n }\n return v4;\n}", + "ida_strip_asm": "sub_1410:\nendbr64\npush r15\npush r14\nmov r14, rdi\npush r13\npush r12\npush rbp\nmovsxd rbp, esi\npush rbx\nmov rbx, rbp\nshl rbp, 3\nmov rdi, rbp; size\nsub rsp, 8\ncall _malloc\nmov r13, rax\ntest ebx, ebx\njle loc_14C4\nmov rbx, rax\nadd rbp, r14\nlea r12, aTheNumberOfOdd_4; \"the number of odd elements %d in the st\"...\nnop\nloc_1450:\nmov rdx, [r14]\nxor r15d, r15d\nmovzx eax, byte ptr [rdx]\nadd rdx, 1\ntest al, al\njz short loc_1484\nnop dword ptr [rax+00000000h]\nloc_1468:\nlea ecx, [rax-30h]\ncmp cl, 9\nja short loc_1479\nand eax, 1\ncmp al, 1\nsbb r15d, 0FFFFFFFFh\nloc_1479:\nmovzx eax, byte ptr [rdx]\nadd rdx, 1\ntest al, al\njnz short loc_1468\nloc_1484:\nmov edi, 64h ; 'd'; size\nadd r14, 8\nadd rbx, 8\ncall _malloc\nsub rsp, 8\nmov r9d, r15d\nmov r8d, r15d\nmov [rbx-8], rax\nmov rdi, rax\nmov edx, 64h ; 'd'\nmov rcx, r12\npush r15\nmov esi, 2\nxor eax, eax\ncall ___sprintf_chk\npop rax\npop rdx\ncmp r14, rbp\njnz short loc_1450\nloc_14C4:\nadd rsp, 8\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "void *__fastcall sub_1410(char **a1, int a2)\n{\n char **v2; // r14\n void *v3; // rax\n void *v4; // r13\n _QWORD *v5; // rbx\n int v6; // r15d\n char v7; // al\n char *i; // rdx\n void *v9; // rax\n\n v2 = a1;\n v3 = malloc(8LL * a2);\n v4 = v3;\n if ( a2 > 0 )\n {\n v5 = v3;\n do\n {\n v6 = 0;\n v7 = **v2;\n for ( i = *v2 + 1; v7; ++i )\n {\n if ( (unsigned __int8)(v7 - 48) <= 9u )\n v6 -= ((v7 & 1) == 0) - 1;\n v7 = *i;\n }\n ++v2;\n ++v5;\n v9 = malloc(0x64uLL);\n *(v5 - 1) = v9;\n __sprintf_chk(v9, 2LL, 100LL, \"the number of odd elements %d in the string %d of the %d input.\", v6, v6, v6);\n }\n while ( v2 != &a1[a2] );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1410(char **a1, int a2) {\n char **v2;\n void *v3;\n void *v4;\n uint64_t *v5;\n int v6;\n char v7;\n char *i;\n void *v9;\n v2 = a1;\n v3 = malloc(8LL * a2);\n v4 = v3;\n if (a2 > 0) {\n v5 = v3;\n do {\n v6 = 0;\n v7 = **v2;\n for (i = *v2 + 1; v7; ++i) {\n if ((unsigned char)(v7 - 48) <= 9u) v6 -= ((v7 & 1) == 0) - 1;\n v7 = *i;\n }\n ++v2;\n ++v5;\n v9 = malloc(100uLL);\n *(v5 - 1) = v9;\n __sprintf_chk(\n v9, 2LL, 100LL,\n \"the number of odd elements %d in the string %d of the %d input.\", v6,\n v6, v6);\n } while (v2 != &a1[a2]);\n }\n return v4;\n}", + "ida_pseudo_norm": "void *func0(char **a1, int a2) {\n char **v2;\n void *v3;\n void *v4;\n uint64_t *v5;\n int v6;\n char v7;\n char *i;\n void *v9;\n v2 = a1;\n v3 = malloc(8LL * a2);\n v4 = v3;\n if (a2 > 0) {\n v5 = v3;\n do {\n v6 = 0;\n v7 = **v2;\n for (i = *v2 + 1; v7; ++i) {\n if ((unsigned char)(v7 - 48) <= 9u) v6 -= ((v7 & 1) == 0) - 1;\n v7 = *i;\n }\n ++v2;\n ++v5;\n v9 = malloc(100uLL);\n *(v5 - 1) = v9;\n __sprintf_chk(\n v9, 2LL, 100LL,\n \"the number of odd elements %d in the string %d of the %d input.\", v6,\n v6, v6);\n } while (v2 != &a1[a2]);\n }\n return v4;\n}" + }, + { + "index": "HumanEval-C-113", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char **func0(char *lst[], int size) {\n char **out = malloc(size * sizeof(char *));\n for (int i = 0; i < size; i++) {\n int sum = 0;\n for (int j = 0; lst[i][j] != '\\0'; j++) {\n if (lst[i][j] >= '0' && lst[i][j] <= '9' && (lst[i][j] - '0') % 2 == 1)\n sum += 1;\n }\n out[i] = malloc(100);\n sprintf(out[i],\n \"the number of odd elements %d in the string %d of the %d input.\",\n sum, sum, sum);\n }\n return out;\n}", + "test": "#include \n#include \n#include \n\nint issame(char **a, char **b, int size) {\n for (int i = 0; i < size; i++) {\n if (strcmp(a[i], b[i]) != 0) {\n return 0;\n }\n }\n return 1;\n}\n\nint main() {\n char *input1[] = {\"1234567\"};\n char *expected1[] = {\"the number of odd elements 4 in the string 4 of the 4 input.\"};\n char **result1 = func0(input1, 1);\n assert(issame(result1, expected1, 1));\n\n char *input2[] = {\"3\", \"11111111\"};\n char *expected2[] = {\n \"the number of odd elements 1 in the string 1 of the 1 input.\",\n \"the number of odd elements 8 in the string 8 of the 8 input.\"\n };\n char **result2 = func0(input2, 2);\n assert(issame(result2, expected2, 2));\n\n char *input3[] = {\"271\", \"137\", \"314\"};\n char *expected3[] = {\n \"the number of odd elements 2 in the string 2 of the 2 input.\",\n \"the number of odd elements 3 in the string 3 of the 3 input.\",\n \"the number of odd elements 2 in the string 2 of the 2 input.\"\n };\n char **result3 = func0(input3, 3);\n assert(issame(result3, expected3, 3));\n\n // Free the allocated memory\n for (int i = 0; i < 1; i++) free(result1[i]);\n free(result1);\n for (int i = 0; i < 2; i++) free(result2[i]);\n free(result2);\n for (int i = 0; i < 3; i++) free(result3[i]);\n free(result3);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14, rdi\npush r13\npush r12\npush rbp\nmovsxd rbp, esi\npush rbx\nmov rbx, rbp\nshl rbp, 3\nmov rdi, rbp; size\nsub rsp, 8\ncall _malloc\nmov r13, rax\ntest ebx, ebx\njle loc_14C4\nmov rbx, rax\nadd rbp, r14\nlea r12, aTheNumberOfOdd_4; \"the number of odd elements %d in the st\"...\nnop\nloc_1450:\nmov rdx, [r14]\nxor r15d, r15d\nmovzx eax, byte ptr [rdx]\nadd rdx, 1\ntest al, al\njz short loc_1484\nnop dword ptr [rax+00000000h]\nloc_1468:\nlea ecx, [rax-30h]\ncmp cl, 9\nja short loc_1479\nand eax, 1\ncmp al, 1\nsbb r15d, 0FFFFFFFFh\nloc_1479:\nmovzx eax, byte ptr [rdx]\nadd rdx, 1\ntest al, al\njnz short loc_1468\nloc_1484:\nmov edi, 64h ; 'd'; size\nadd r14, 8\nadd rbx, 8\ncall _malloc\nsub rsp, 8\nmov r9d, r15d\nmov r8d, r15d\nmov [rbx-8], rax\nmov rdi, rax\nmov edx, 64h ; 'd'\nmov rcx, r12\npush r15\nmov esi, 2\nxor eax, eax\ncall ___sprintf_chk\npop rax\npop rdx\ncmp r14, rbp\njnz short loc_1450\nloc_14C4:\nadd rsp, 8\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "void *__fastcall func0(char **a1, int a2)\n{\n char **v2; // r14\n void *v3; // rax\n void *v4; // r13\n _QWORD *v5; // rbx\n int v6; // r15d\n char v7; // al\n char *i; // rdx\n void *v9; // rax\n\n v2 = a1;\n v3 = malloc(8LL * a2);\n v4 = v3;\n if ( a2 > 0 )\n {\n v5 = v3;\n do\n {\n v6 = 0;\n v7 = **v2;\n for ( i = *v2 + 1; v7; ++i )\n {\n if ( (unsigned __int8)(v7 - 48) <= 9u )\n v6 -= ((v7 & 1) == 0) - 1;\n v7 = *i;\n }\n ++v2;\n ++v5;\n v9 = malloc(0x64uLL);\n *(v5 - 1) = v9;\n __sprintf_chk(v9, 2LL, 100LL, \"the number of odd elements %d in the string %d of the %d input.\", v6, v6, v6);\n }\n while ( v2 != &a1[a2] );\n }\n return v4;\n}", + "ida_strip_asm": "sub_1410:\nendbr64\npush r15\npush r14\nmov r14, rdi\npush r13\npush r12\npush rbp\nmovsxd rbp, esi\npush rbx\nmov rbx, rbp\nshl rbp, 3\nmov rdi, rbp; size\nsub rsp, 8\ncall _malloc\nmov r13, rax\ntest ebx, ebx\njle loc_14C4\nmov rbx, rax\nadd rbp, r14\nlea r12, aTheNumberOfOdd_4; \"the number of odd elements %d in the st\"...\nnop\nloc_1450:\nmov rdx, [r14]\nxor r15d, r15d\nmovzx eax, byte ptr [rdx]\nadd rdx, 1\ntest al, al\njz short loc_1484\nnop dword ptr [rax+00000000h]\nloc_1468:\nlea ecx, [rax-30h]\ncmp cl, 9\nja short loc_1479\nand eax, 1\ncmp al, 1\nsbb r15d, 0FFFFFFFFh\nloc_1479:\nmovzx eax, byte ptr [rdx]\nadd rdx, 1\ntest al, al\njnz short loc_1468\nloc_1484:\nmov edi, 64h ; 'd'; size\nadd r14, 8\nadd rbx, 8\ncall _malloc\nsub rsp, 8\nmov r9d, r15d\nmov r8d, r15d\nmov [rbx-8], rax\nmov rdi, rax\nmov edx, 64h ; 'd'\nmov rcx, r12\npush r15\nmov esi, 2\nxor eax, eax\ncall ___sprintf_chk\npop rax\npop rdx\ncmp r14, rbp\njnz short loc_1450\nloc_14C4:\nadd rsp, 8\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "void *__fastcall sub_1410(char **a1, int a2)\n{\n char **v2; // r14\n void *v3; // rax\n void *v4; // r13\n _QWORD *v5; // rbx\n int v6; // r15d\n char v7; // al\n char *i; // rdx\n void *v9; // rax\n\n v2 = a1;\n v3 = malloc(8LL * a2);\n v4 = v3;\n if ( a2 > 0 )\n {\n v5 = v3;\n do\n {\n v6 = 0;\n v7 = **v2;\n for ( i = *v2 + 1; v7; ++i )\n {\n if ( (unsigned __int8)(v7 - 48) <= 9u )\n v6 -= ((v7 & 1) == 0) - 1;\n v7 = *i;\n }\n ++v2;\n ++v5;\n v9 = malloc(0x64uLL);\n *(v5 - 1) = v9;\n __sprintf_chk(v9, 2LL, 100LL, \"the number of odd elements %d in the string %d of the %d input.\", v6, v6, v6);\n }\n while ( v2 != &a1[a2] );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1410(char **a1, int a2) {\n char **v2;\n void *v3;\n void *v4;\n uint64_t *v5;\n int v6;\n char v7;\n char *i;\n void *v9;\n v2 = a1;\n v3 = malloc(8LL * a2);\n v4 = v3;\n if (a2 > 0) {\n v5 = v3;\n do {\n v6 = 0;\n v7 = **v2;\n for (i = *v2 + 1; v7; ++i) {\n if ((unsigned char)(v7 - 48) <= 9u) v6 -= ((v7 & 1) == 0) - 1;\n v7 = *i;\n }\n ++v2;\n ++v5;\n v9 = malloc(100uLL);\n *(v5 - 1) = v9;\n __sprintf_chk(\n v9, 2LL, 100LL,\n \"the number of odd elements %d in the string %d of the %d input.\", v6,\n v6, v6);\n } while (v2 != &a1[a2]);\n }\n return v4;\n}", + "ida_pseudo_norm": "void *func0(char **a1, int a2) {\n char **v2;\n void *v3;\n void *v4;\n uint64_t *v5;\n int v6;\n char v7;\n char *i;\n void *v9;\n v2 = a1;\n v3 = malloc(8LL * a2);\n v4 = v3;\n if (a2 > 0) {\n v5 = v3;\n do {\n v6 = 0;\n v7 = **v2;\n for (i = *v2 + 1; v7; ++i) {\n if ((unsigned char)(v7 - 48) <= 9u) v6 -= ((v7 & 1) == 0) - 1;\n v7 = *i;\n }\n ++v2;\n ++v5;\n v9 = malloc(100uLL);\n *(v5 - 1) = v9;\n __sprintf_chk(\n v9, 2LL, 100LL,\n \"the number of odd elements %d in the string %d of the %d input.\", v6,\n v6, v6);\n } while (v2 != &a1[a2]);\n }\n return v4;\n}" + }, + { + "index": "HumanEval-C-114", + "func_name": "func0", + "func_dep": "#include \n", + "func": "long long func0(long long *nums, int size) {\n long long current = nums[0];\n long long min = nums[0];\n for (int i = 1; i < size; i++) {\n current = current < 0 ? current + nums[i] : nums[i];\n if (current < min) min = current;\n }\n return min;\n}", + "test": "#include \n\nint main() {\n long long nums1[] = {2, 3, 4, 1, 2, 4};\n assert(func0(nums1, 6) == 1);\n\n long long nums2[] = {-1, -2, -3};\n assert(func0(nums2, 3) == -6);\n\n long long nums3[] = {-1, -2, -3, 2, -10};\n assert(func0(nums3, 5) == -14);\n\n long long nums4[] = {-9999999999999999};\n assert(func0(nums4, 1) == -9999999999999999);\n\n long long nums5[] = {0, 10, 20, 1000000};\n assert(func0(nums5, 4) == 0);\n\n long long nums6[] = {-1, -2, -3, 10, -5};\n assert(func0(nums6, 5) == -6);\n\n long long nums7[] = {100, -1, -2, -3, 10, -5};\n assert(func0(nums7, 6) == -6);\n\n long long nums8[] = {10, 11, 13, 8, 3, 4};\n assert(func0(nums8, 6) == 3);\n\n long long nums9[] = {100, -33, 32, -1, 0, -2};\n assert(func0(nums9, 6) == -33);\n\n long long nums10[] = {-10};\n assert(func0(nums10, 1) == -10);\n\n long long nums11[] = {7};\n assert(func0(nums11, 1) == 7);\n\n long long nums12[] = {1, -1};\n assert(func0(nums12, 2) == -1);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov rax, [rbp+var_28]\nmov rax, [rax]\nmov [rbp+var_10], rax\nmov rax, [rbp+var_28]\nmov rax, [rax]\nmov [rbp+var_8], rax\nmov [rbp+var_14], 1\njmp short loc_11EF\nloc_1197:\ncmp [rbp+var_10], 0\njns short loc_11BE\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rdx, [rax]\nmov rax, [rbp+var_10]\nadd rax, rdx\njmp short loc_11D5\nloc_11BE:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nloc_11D5:\nmov [rbp+var_10], rax\nmov rax, [rbp+var_10]\ncmp rax, [rbp+var_8]\njge short loc_11EB\nmov rax, [rbp+var_10]\nmov [rbp+var_8], rax\nloc_11EB:\nadd [rbp+var_14], 1\nloc_11EF:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl short loc_1197\nmov rax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 *a1, int a2)\n{\n __int64 v2; // rax\n int i; // [rsp+18h] [rbp-14h]\n __int64 v5; // [rsp+1Ch] [rbp-10h]\n __int64 v6; // [rsp+24h] [rbp-8h]\n\n v5 = *a1;\n v6 = *a1;\n for ( i = 1; i < a2; ++i )\n {\n if ( v5 >= 0 )\n v2 = a1[i];\n else\n v2 = a1[i] + v5;\n v5 = v2;\n if ( v2 < v6 )\n v6 = v2;\n }\n return v6;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov rax, [rbp+var_28]\nmov rax, [rax]\nmov [rbp+var_10], rax\nmov rax, [rbp+var_28]\nmov rax, [rax]\nmov [rbp+var_8], rax\nmov [rbp+var_14], 1\njmp short loc_11EF\nloc_1197:\ncmp [rbp+var_10], 0\njns short loc_11BE\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rdx, [rax]\nmov rax, [rbp+var_10]\nadd rax, rdx\njmp short loc_11D5\nloc_11BE:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nloc_11D5:\nmov [rbp+var_10], rax\nmov rax, [rbp+var_10]\ncmp rax, [rbp+var_8]\njge short loc_11EB\nmov rax, [rbp+var_10]\nmov [rbp+var_8], rax\nloc_11EB:\nadd [rbp+var_14], 1\nloc_11EF:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl short loc_1197\nmov rax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 *a1, int a2)\n{\n __int64 v2; // rax\n int i; // [rsp+18h] [rbp-14h]\n __int64 v5; // [rsp+1Ch] [rbp-10h]\n __int64 v6; // [rsp+24h] [rbp-8h]\n\n v5 = *a1;\n v6 = *a1;\n for ( i = 1; i < a2; ++i )\n {\n if ( v5 >= 0 )\n v2 = a1[i];\n else\n v2 = a1[i] + v5;\n v5 = v2;\n if ( v2 < v6 )\n v6 = v2;\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long *a1, int a2) {\n long long v2;\n int i;\n long long v5;\n long long v6;\n v5 = *a1;\n v6 = *a1;\n for (i = 1; i < a2; ++i) {\n if (v5 >= 0)\n v2 = a1[i];\n else\n v2 = a1[i] + v5;\n v5 = v2;\n if (v2 < v6) v6 = v2;\n }\n return v6;\n}", + "ida_pseudo_norm": "long long func0(long long *a1, int a2) {\n long long v2;\n int i;\n long long v5;\n long long v6;\n v5 = *a1;\n v6 = *a1;\n for (i = 1; i < a2; ++i) {\n if (v5 >= 0)\n v2 = a1[i];\n else\n v2 = a1[i] + v5;\n v5 = v2;\n if (v2 < v6) v6 = v2;\n }\n return v6;\n}" + }, + { + "index": "HumanEval-C-114", + "func_name": "func0", + "func_dep": "#include \n", + "func": "long long func0(long long *nums, int size) {\n long long current = nums[0];\n long long min = nums[0];\n for (int i = 1; i < size; i++) {\n current = current < 0 ? current + nums[i] : nums[i];\n if (current < min) min = current;\n }\n return min;\n}", + "test": "#include \n\nint main() {\n long long nums1[] = {2, 3, 4, 1, 2, 4};\n assert(func0(nums1, 6) == 1);\n\n long long nums2[] = {-1, -2, -3};\n assert(func0(nums2, 3) == -6);\n\n long long nums3[] = {-1, -2, -3, 2, -10};\n assert(func0(nums3, 5) == -14);\n\n long long nums4[] = {-9999999999999999};\n assert(func0(nums4, 1) == -9999999999999999);\n\n long long nums5[] = {0, 10, 20, 1000000};\n assert(func0(nums5, 4) == 0);\n\n long long nums6[] = {-1, -2, -3, 10, -5};\n assert(func0(nums6, 5) == -6);\n\n long long nums7[] = {100, -1, -2, -3, 10, -5};\n assert(func0(nums7, 6) == -6);\n\n long long nums8[] = {10, 11, 13, 8, 3, 4};\n assert(func0(nums8, 6) == 3);\n\n long long nums9[] = {100, -33, 32, -1, 0, -2};\n assert(func0(nums9, 6) == -33);\n\n long long nums10[] = {-10};\n assert(func0(nums10, 1) == -10);\n\n long long nums11[] = {7};\n assert(func0(nums11, 1) == 7);\n\n long long nums12[] = {1, -1};\n assert(func0(nums12, 2) == -1);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmov rax, [rdi]\ncmp esi, 1\njle short loc_11A3\nlea rdx, [rdi+8]\nlea ecx, [rsi-2]\nlea rsi, [rdi+rcx*8+10h]\nmov rcx, rax\njmp short loc_1199\nloc_1186:\nmov rax, [rdx]\nloc_1189:\ncmp rcx, rax\ncmovg rcx, rax\nadd rdx, 8\ncmp rdx, rsi\njz short loc_11A6\nloc_1199:\ntest rax, rax\njns short loc_1186\nadd rax, [rdx]\njmp short loc_1189\nloc_11A3:\nmov rcx, rax\nloc_11A6:\nmov rax, rcx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 *a1, int a2)\n{\n __int64 v2; // rax\n __int64 *v3; // rdx\n __int64 v4; // rsi\n __int64 v5; // rcx\n\n v2 = *a1;\n if ( a2 <= 1 )\n return *a1;\n v3 = a1 + 1;\n v4 = (__int64)&a1[(unsigned int)(a2 - 2) + 2];\n v5 = *a1;\n do\n {\n if ( v2 >= 0 )\n v2 = *v3;\n else\n v2 += *v3;\n if ( v5 > v2 )\n v5 = v2;\n ++v3;\n }\n while ( v3 != (__int64 *)v4 );\n return v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov rax, [rdi]\ncmp esi, 1\njle short loc_11A3\nlea rdx, [rdi+8]\nlea ecx, [rsi-2]\nlea rsi, [rdi+rcx*8+10h]\nmov rcx, rax\njmp short loc_1199\nloc_1186:\nmov rax, [rdx]\nloc_1189:\ncmp rcx, rax\ncmovg rcx, rax\nadd rdx, 8\ncmp rdx, rsi\njz short loc_11A6\nloc_1199:\ntest rax, rax\njns short loc_1186\nadd rax, [rdx]\njmp short loc_1189\nloc_11A3:\nmov rcx, rax\nloc_11A6:\nmov rax, rcx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 *a1, int a2)\n{\n __int64 v2; // rax\n __int64 *v3; // rdx\n __int64 v4; // rsi\n __int64 v5; // rcx\n\n v2 = *a1;\n if ( a2 <= 1 )\n return *a1;\n v3 = a1 + 1;\n v4 = (__int64)&a1[(unsigned int)(a2 - 2) + 2];\n v5 = *a1;\n do\n {\n if ( v2 >= 0 )\n v2 = *v3;\n else\n v2 += *v3;\n if ( v5 > v2 )\n v5 = v2;\n ++v3;\n }\n while ( v3 != (__int64 *)v4 );\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long *a1, int a2) {\n long long v2;\n long long *v3;\n long long v4;\n long long v5;\n v2 = *a1;\n if (a2 <= 1) return *a1;\n v3 = a1 + 1;\n v4 = (long long)&a1[(unsigned int)(a2 - 2) + 2];\n v5 = *a1;\n do {\n if (v2 >= 0)\n v2 = *v3;\n else\n v2 += *v3;\n if (v5 > v2) v5 = v2;\n ++v3;\n } while (v3 != (long long *)v4);\n return v5;\n}", + "ida_pseudo_norm": "long long func0(long long *a1, int a2) {\n long long v2;\n long long *v3;\n long long v4;\n long long v5;\n v2 = *a1;\n if (a2 <= 1) return *a1;\n v3 = a1 + 1;\n v4 = (long long)&a1[(unsigned int)(a2 - 2) + 2];\n v5 = *a1;\n do {\n if (v2 >= 0)\n v2 = *v3;\n else\n v2 += *v3;\n if (v5 > v2) v5 = v2;\n ++v3;\n } while (v3 != (long long *)v4);\n return v5;\n}" + }, + { + "index": "HumanEval-C-114", + "func_name": "func0", + "func_dep": "#include \n", + "func": "long long func0(long long *nums, int size) {\n long long current = nums[0];\n long long min = nums[0];\n for (int i = 1; i < size; i++) {\n current = current < 0 ? current + nums[i] : nums[i];\n if (current < min) min = current;\n }\n return min;\n}", + "test": "#include \n\nint main() {\n long long nums1[] = {2, 3, 4, 1, 2, 4};\n assert(func0(nums1, 6) == 1);\n\n long long nums2[] = {-1, -2, -3};\n assert(func0(nums2, 3) == -6);\n\n long long nums3[] = {-1, -2, -3, 2, -10};\n assert(func0(nums3, 5) == -14);\n\n long long nums4[] = {-9999999999999999};\n assert(func0(nums4, 1) == -9999999999999999);\n\n long long nums5[] = {0, 10, 20, 1000000};\n assert(func0(nums5, 4) == 0);\n\n long long nums6[] = {-1, -2, -3, 10, -5};\n assert(func0(nums6, 5) == -6);\n\n long long nums7[] = {100, -1, -2, -3, 10, -5};\n assert(func0(nums7, 6) == -6);\n\n long long nums8[] = {10, 11, 13, 8, 3, 4};\n assert(func0(nums8, 6) == 3);\n\n long long nums9[] = {100, -33, 32, -1, 0, -2};\n assert(func0(nums9, 6) == -33);\n\n long long nums10[] = {-10};\n assert(func0(nums10, 1) == -10);\n\n long long nums11[] = {7};\n assert(func0(nums11, 1) == 7);\n\n long long nums12[] = {1, -1};\n assert(func0(nums12, 2) == -1);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmov rax, [rdi]\ncmp esi, 1\njle short loc_1608\nlea ecx, [rsi-2]\nlea rdx, [rdi+8]\nlea r8, [rdi+rcx*8+10h]\nmov rcx, rax\nnop dword ptr [rax+rax+00h]\nloc_15E0:\nmov rsi, [rdx]\ntest rax, rax\nlea rdi, [rax+rsi]\nmov rax, rsi\ncmovs rax, rdi\ncmp rcx, rax\ncmovg rcx, rax\nadd rdx, 8\ncmp r8, rdx\njnz short loc_15E0\nmov rax, rcx\nretn\nloc_1608:\nmov rcx, rax\nmov rax, rcx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 *a1, int a2)\n{\n __int64 result; // rax\n __int64 *v3; // rdx\n __int64 v4; // r8\n __int64 v5; // rcx\n bool v6; // sf\n __int64 v7; // rdi\n\n result = *a1;\n if ( a2 > 1 )\n {\n v3 = a1 + 1;\n v4 = (__int64)&a1[(unsigned int)(a2 - 2) + 2];\n v5 = *a1;\n do\n {\n v6 = result < 0;\n v7 = result + *v3;\n result = *v3;\n if ( v6 )\n result = v7;\n if ( v5 > result )\n v5 = result;\n ++v3;\n }\n while ( (__int64 *)v4 != v3 );\n return v5;\n }\n return result;\n}", + "ida_strip_asm": "sub_15C0:\nendbr64\nmov rax, [rdi]\ncmp esi, 1\njle short loc_1608\nlea ecx, [rsi-2]\nlea rdx, [rdi+8]\nlea r8, [rdi+rcx*8+10h]\nmov rcx, rax\nnop dword ptr [rax+rax+00h]\nloc_15E0:\nmov rsi, [rdx]\ntest rax, rax\nlea rdi, [rax+rsi]\nmov rax, rsi\ncmovs rax, rdi\ncmp rcx, rax\ncmovg rcx, rax\nadd rdx, 8\ncmp r8, rdx\njnz short loc_15E0\nmov rax, rcx\nretn\nloc_1608:\nmov rcx, rax\nmov rax, rcx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_15C0(__int64 *a1, int a2)\n{\n __int64 result; // rax\n __int64 *v3; // rdx\n __int64 v4; // r8\n __int64 v5; // rcx\n bool v6; // sf\n __int64 v7; // rdi\n\n result = *a1;\n if ( a2 > 1 )\n {\n v3 = a1 + 1;\n v4 = (__int64)&a1[(unsigned int)(a2 - 2) + 2];\n v5 = *a1;\n do\n {\n v6 = result < 0;\n v7 = result + *v3;\n result = *v3;\n if ( v6 )\n result = v7;\n if ( v5 > result )\n v5 = result;\n ++v3;\n }\n while ( (__int64 *)v4 != v3 );\n return v5;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_15C0(long long *a1, int a2) {\n long long result;\n long long *v3;\n long long v4;\n long long v5;\n bool v6;\n long long v7;\n result = *a1;\n if (a2 > 1) {\n v3 = a1 + 1;\n v4 = (long long)&a1[(unsigned int)(a2 - 2) + 2];\n v5 = *a1;\n do {\n v6 = result < 0;\n v7 = result + *v3;\n result = *v3;\n if (v6) result = v7;\n if (v5 > result) v5 = result;\n ++v3;\n } while ((long long *)v4 != v3);\n return v5;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long *a1, int a2) {\n long long result;\n long long *v3;\n long long v4;\n long long v5;\n bool v6;\n long long v7;\n result = *a1;\n if (a2 > 1) {\n v3 = a1 + 1;\n v4 = (long long)&a1[(unsigned int)(a2 - 2) + 2];\n v5 = *a1;\n do {\n v6 = result < 0;\n v7 = result + *v3;\n result = *v3;\n if (v6) result = v7;\n if (v5 > result) v5 = result;\n ++v3;\n } while ((long long *)v4 != v3);\n return v5;\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-115", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int **grid, int rows, int cols, int capacity) {\n int out = 0;\n for (int i = 0; i < rows; i++) {\n int sum = 0;\n for (int j = 0; j < cols; j++) sum += grid[i][j];\n if (sum > 0) out += (sum + capacity - 1) / capacity;\n }\n return out;\n}", + "test": "#include \n#include \n#include \n\nint main() {\n int rows, cols, capacity;\n int **grid;\n \n // Test case 1\n rows = 3; cols = 4; capacity = 1;\n grid = (int **)malloc(rows * sizeof(int *));\n int grid1_data[3][4] = {{0,0,1,0}, {0,1,0,0}, {1,1,1,1}};\n for (int i = 0; i < rows; i++) {\n grid[i] = (int *)malloc(cols * sizeof(int));\n for (int j = 0; j < cols; j++) {\n grid[i][j] = grid1_data[i][j];\n }\n }\n assert(func0(grid, rows, cols, capacity) == 6);\n for (int i = 0; i < rows; i++) free(grid[i]);\n free(grid);\n\n // Test case 2\n rows = 4; cols = 4; capacity = 2;\n grid = (int **)malloc(rows * sizeof(int *));\n int grid2_data[4][4] = {{0,0,1,1}, {0,0,0,0}, {1,1,1,1}, {0,1,1,1}};\n for (int i = 0; i < rows; i++) {\n grid[i] = (int *)malloc(cols * sizeof(int));\n for (int j = 0; j < cols; j++) {\n grid[i][j] = grid2_data[i][j];\n }\n }\n assert(func0(grid, rows, cols, capacity) == 5);\n for (int i = 0; i < rows; i++) free(grid[i]);\n free(grid);\n\n // Test case 3\n rows = 2; cols = 3; capacity = 5;\n grid = (int **)malloc(rows * sizeof(int *));\n int grid3_data[2][3] = {{0,0,0}, {0,0,0}};\n for (int i = 0; i < rows; i++) {\n grid[i] = (int *)malloc(cols * sizeof(int));\n for (int j = 0; j < cols; j++) {\n grid[i][j] = grid3_data[i][j];\n }\n }\n assert(func0(grid, rows, cols, capacity) == 0);\n for (int i = 0; i < rows; i++) free(grid[i]);\n free(grid);\n\n // Test case 4\n rows = 2; cols = 4; capacity = 2;\n grid = (int **)malloc(rows * sizeof(int *));\n int grid4_data[2][4] = {{1,1,1,1}, {1,1,1,1}};\n for (int i = 0; i < rows; i++) {\n grid[i] = (int *)malloc(cols * sizeof(int));\n for (int j = 0; j < cols; j++) {\n grid[i][j] = grid4_data[i][j];\n }\n }\n assert(func0(grid, rows, cols, capacity) == 4);\n for (int i = 0; i < rows; i++) free(grid[i]);\n free(grid);\n\n // Test case 5\n rows = 2; cols = 4; capacity = 9;\n grid = (int **)malloc(rows * sizeof(int *));\n int grid5_data[2][4] = {{1,1,1,1}, {1,1,1,1}};\n for (int i = 0; i < rows; i++) {\n grid[i] = (int *)malloc(cols * sizeof(int));\n for (int j = 0; j < cols; j++) {\n grid[i][j] = grid5_data[i][j];\n }\n }\n assert(func0(grid, rows, cols, capacity) == 2);\nfor (int i = 0; i < rows; i++) free(grid[i]);\n free(grid);\n\n printf(\"All tests passed!\\n\");\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_24], ecx\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp short loc_124F\nloc_11EE:\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_122B\nloc_11FE:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_122B:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_20]\njl short loc_11FE\ncmp [rbp+var_8], 0\njle short loc_124B\nmov edx, [rbp+var_8]\nmov eax, [rbp+var_24]\nadd eax, edx\nsub eax, 1\ncdq\nidiv [rbp+var_24]\nadd [rbp+var_10], eax\nloc_124B:\nadd [rbp+var_C], 1\nloc_124F:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_11EE\nmov eax, [rbp+var_10]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3, int a4)\n{\n unsigned int v5; // [rsp+14h] [rbp-10h]\n int i; // [rsp+18h] [rbp-Ch]\n int v7; // [rsp+1Ch] [rbp-8h]\n int j; // [rsp+20h] [rbp-4h]\n\n v5 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v7 = 0;\n for ( j = 0; j < a3; ++j )\n v7 += *(_DWORD *)(4LL * j + *(_QWORD *)(8LL * i + a1));\n if ( v7 > 0 )\n v5 += (v7 + a4 - 1) / a4;\n }\n return v5;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_24], ecx\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp short loc_124F\nloc_11EE:\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_122B\nloc_11FE:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_122B:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_20]\njl short loc_11FE\ncmp [rbp+var_8], 0\njle short loc_124B\nmov edx, [rbp+var_8]\nmov eax, [rbp+var_24]\nadd eax, edx\nsub eax, 1\ncdq\nidiv [rbp+var_24]\nadd [rbp+var_10], eax\nloc_124B:\nadd [rbp+var_C], 1\nloc_124F:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_11EE\nmov eax, [rbp+var_10]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11C9(__int64 a1, int a2, int a3, int a4)\n{\n unsigned int v5; // [rsp+14h] [rbp-10h]\n int i; // [rsp+18h] [rbp-Ch]\n int v7; // [rsp+1Ch] [rbp-8h]\n int j; // [rsp+20h] [rbp-4h]\n\n v5 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v7 = 0;\n for ( j = 0; j < a3; ++j )\n v7 += *(_DWORD *)(4LL * j + *(_QWORD *)(8LL * i + a1));\n if ( v7 > 0 )\n v5 += (v7 + a4 - 1) / a4;\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11C9(long long a1, int a2, int a3, int a4) {\n unsigned int v5;\n int i;\n int v7;\n int j;\n v5 = 0;\n for (i = 0; i < a2; ++i) {\n v7 = 0;\n for (j = 0; j < a3; ++j)\n v7 += *(uint32_t *)(4LL * j + *(uint64_t *)(8LL * i + a1));\n if (v7 > 0) v5 += (v7 + a4 - 1) / a4;\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3, int a4) {\n unsigned int v5;\n int i;\n int v7;\n int j;\n v5 = 0;\n for (i = 0; i < a2; ++i) {\n v7 = 0;\n for (j = 0; j < a3; ++j)\n v7 += *(uint32_t *)(4LL * j + *(uint64_t *)(8LL * i + a1));\n if (v7 > 0) v5 += (v7 + a4 - 1) / a4;\n }\n return v5;\n}" + }, + { + "index": "HumanEval-C-115", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int **grid, int rows, int cols, int capacity) {\n int out = 0;\n for (int i = 0; i < rows; i++) {\n int sum = 0;\n for (int j = 0; j < cols; j++) sum += grid[i][j];\n if (sum > 0) out += (sum + capacity - 1) / capacity;\n }\n return out;\n}", + "test": "#include \n#include \n#include \n\nint main() {\n int rows, cols, capacity;\n int **grid;\n \n // Test case 1\n rows = 3; cols = 4; capacity = 1;\n grid = (int **)malloc(rows * sizeof(int *));\n int grid1_data[3][4] = {{0,0,1,0}, {0,1,0,0}, {1,1,1,1}};\n for (int i = 0; i < rows; i++) {\n grid[i] = (int *)malloc(cols * sizeof(int));\n for (int j = 0; j < cols; j++) {\n grid[i][j] = grid1_data[i][j];\n }\n }\n assert(func0(grid, rows, cols, capacity) == 6);\n for (int i = 0; i < rows; i++) free(grid[i]);\n free(grid);\n\n // Test case 2\n rows = 4; cols = 4; capacity = 2;\n grid = (int **)malloc(rows * sizeof(int *));\n int grid2_data[4][4] = {{0,0,1,1}, {0,0,0,0}, {1,1,1,1}, {0,1,1,1}};\n for (int i = 0; i < rows; i++) {\n grid[i] = (int *)malloc(cols * sizeof(int));\n for (int j = 0; j < cols; j++) {\n grid[i][j] = grid2_data[i][j];\n }\n }\n assert(func0(grid, rows, cols, capacity) == 5);\n for (int i = 0; i < rows; i++) free(grid[i]);\n free(grid);\n\n // Test case 3\n rows = 2; cols = 3; capacity = 5;\n grid = (int **)malloc(rows * sizeof(int *));\n int grid3_data[2][3] = {{0,0,0}, {0,0,0}};\n for (int i = 0; i < rows; i++) {\n grid[i] = (int *)malloc(cols * sizeof(int));\n for (int j = 0; j < cols; j++) {\n grid[i][j] = grid3_data[i][j];\n }\n }\n assert(func0(grid, rows, cols, capacity) == 0);\n for (int i = 0; i < rows; i++) free(grid[i]);\n free(grid);\n\n // Test case 4\n rows = 2; cols = 4; capacity = 2;\n grid = (int **)malloc(rows * sizeof(int *));\n int grid4_data[2][4] = {{1,1,1,1}, {1,1,1,1}};\n for (int i = 0; i < rows; i++) {\n grid[i] = (int *)malloc(cols * sizeof(int));\n for (int j = 0; j < cols; j++) {\n grid[i][j] = grid4_data[i][j];\n }\n }\n assert(func0(grid, rows, cols, capacity) == 4);\n for (int i = 0; i < rows; i++) free(grid[i]);\n free(grid);\n\n // Test case 5\n rows = 2; cols = 4; capacity = 9;\n grid = (int **)malloc(rows * sizeof(int *));\n int grid5_data[2][4] = {{1,1,1,1}, {1,1,1,1}};\n for (int i = 0; i < rows; i++) {\n grid[i] = (int *)malloc(cols * sizeof(int));\n for (int j = 0; j < cols; j++) {\n grid[i][j] = grid5_data[i][j];\n }\n }\n assert(func0(grid, rows, cols, capacity) == 2);\nfor (int i = 0; i < rows; i++) free(grid[i]);\n free(grid);\n\n printf(\"All tests passed!\\n\");\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1229\npush rbp\npush rbx\nmov r10d, edx\nmov r9d, ecx\nmov r8, rdi\nmovsxd rsi, esi\nlea rbx, [rdi+rsi*8]\nmovsxd r11, edx\nshl r11, 2\nmov edi, 0\nmov ebp, 0\njmp short loc_11FF\nloc_11F6:\nadd r8, 8\ncmp r8, rbx\njz short loc_1231\nloc_11FF:\ntest r10d, r10d\njle short loc_11F6\nmov rax, [r8]\nlea rsi, [rax+r11]\nmov ecx, ebp\nloc_120D:\nadd ecx, [rax]\nadd rax, 4\ncmp rax, rsi\njnz short loc_120D\ntest ecx, ecx\njle short loc_11F6\nlea eax, [r9+rcx-1]\ncdq\nidiv r9d\nadd edi, eax\njmp short loc_11F6\nloc_1229:\nmov edi, 0\nmov eax, edi\nretn\nloc_1231:\nmov eax, edi\npop rbx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD **a1, int a2, int a3, int a4)\n{\n _DWORD **v5; // r8\n _DWORD **v6; // rbx\n unsigned int v7; // edi\n _DWORD *v8; // rax\n int v9; // ecx\n\n if ( a2 <= 0 )\n return 0LL;\n v5 = a1;\n v6 = &a1[a2];\n v7 = 0;\n do\n {\n if ( a3 > 0 )\n {\n v8 = *v5;\n v9 = 0;\n do\n v9 += *v8++;\n while ( v8 != &(*v5)[a3] );\n if ( v9 > 0 )\n v7 += (a4 + v9 - 1) / a4;\n }\n ++v5;\n }\n while ( v5 != v6 );\n return v7;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\ntest esi, esi\njle short loc_1229\npush rbp\npush rbx\nmov r10d, edx\nmov r9d, ecx\nmov r8, rdi\nmovsxd rsi, esi\nlea rbx, [rdi+rsi*8]\nmovsxd r11, edx\nshl r11, 2\nmov edi, 0\nmov ebp, 0\njmp short loc_11FF\nloc_11F6:\nadd r8, 8\ncmp r8, rbx\njz short loc_1231\nloc_11FF:\ntest r10d, r10d\njle short loc_11F6\nmov rax, [r8]\nlea rsi, [rax+r11]\nmov ecx, ebp\nloc_120D:\nadd ecx, [rax]\nadd rax, 4\ncmp rax, rsi\njnz short loc_120D\ntest ecx, ecx\njle short loc_11F6\nlea eax, [r9+rcx-1]\ncdq\nidiv r9d\nadd edi, eax\njmp short loc_11F6\nloc_1229:\nmov edi, 0\nmov eax, edi\nretn\nloc_1231:\nmov eax, edi\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11C9(_DWORD **a1, int a2, int a3, int a4)\n{\n _DWORD **v5; // r8\n _DWORD **v6; // rbx\n unsigned int v7; // edi\n _DWORD *v8; // rax\n int v9; // ecx\n\n if ( a2 <= 0 )\n return 0LL;\n v5 = a1;\n v6 = &a1[a2];\n v7 = 0;\n do\n {\n if ( a3 > 0 )\n {\n v8 = *v5;\n v9 = 0;\n do\n v9 += *v8++;\n while ( v8 != &(*v5)[a3] );\n if ( v9 > 0 )\n v7 += (a4 + v9 - 1) / a4;\n }\n ++v5;\n }\n while ( v5 != v6 );\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11C9(uint32_t **a1, int a2, int a3, int a4) {\n uint32_t **v5;\n uint32_t **v6;\n unsigned int v7;\n uint32_t *v8;\n int v9;\n if (a2 <= 0) return 0LL;\n v5 = a1;\n v6 = &a1[a2];\n v7 = 0;\n do {\n if (a3 > 0) {\n v8 = *v5;\n v9 = 0;\n do\n v9 += *v8++;\n while (v8 != &(*v5)[a3]);\n if (v9 > 0) v7 += (a4 + v9 - 1) / a4;\n }\n ++v5;\n } while (v5 != v6);\n return v7;\n}", + "ida_pseudo_norm": "long long func0(uint32_t **a1, int a2, int a3, int a4) {\n uint32_t **v5;\n uint32_t **v6;\n unsigned int v7;\n uint32_t *v8;\n int v9;\n if (a2 <= 0) return 0LL;\n v5 = a1;\n v6 = &a1[a2];\n v7 = 0;\n do {\n if (a3 > 0) {\n v8 = *v5;\n v9 = 0;\n do\n v9 += *v8++;\n while (v8 != &(*v5)[a3]);\n if (v9 > 0) v7 += (a4 + v9 - 1) / a4;\n }\n ++v5;\n } while (v5 != v6);\n return v7;\n}" + }, + { + "index": "HumanEval-C-115", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int **grid, int rows, int cols, int capacity) {\n int out = 0;\n for (int i = 0; i < rows; i++) {\n int sum = 0;\n for (int j = 0; j < cols; j++) sum += grid[i][j];\n if (sum > 0) out += (sum + capacity - 1) / capacity;\n }\n return out;\n}", + "test": "#include \n#include \n#include \n\nint main() {\n int rows, cols, capacity;\n int **grid;\n \n // Test case 1\n rows = 3; cols = 4; capacity = 1;\n grid = (int **)malloc(rows * sizeof(int *));\n int grid1_data[3][4] = {{0,0,1,0}, {0,1,0,0}, {1,1,1,1}};\n for (int i = 0; i < rows; i++) {\n grid[i] = (int *)malloc(cols * sizeof(int));\n for (int j = 0; j < cols; j++) {\n grid[i][j] = grid1_data[i][j];\n }\n }\n assert(func0(grid, rows, cols, capacity) == 6);\n for (int i = 0; i < rows; i++) free(grid[i]);\n free(grid);\n\n // Test case 2\n rows = 4; cols = 4; capacity = 2;\n grid = (int **)malloc(rows * sizeof(int *));\n int grid2_data[4][4] = {{0,0,1,1}, {0,0,0,0}, {1,1,1,1}, {0,1,1,1}};\n for (int i = 0; i < rows; i++) {\n grid[i] = (int *)malloc(cols * sizeof(int));\n for (int j = 0; j < cols; j++) {\n grid[i][j] = grid2_data[i][j];\n }\n }\n assert(func0(grid, rows, cols, capacity) == 5);\n for (int i = 0; i < rows; i++) free(grid[i]);\n free(grid);\n\n // Test case 3\n rows = 2; cols = 3; capacity = 5;\n grid = (int **)malloc(rows * sizeof(int *));\n int grid3_data[2][3] = {{0,0,0}, {0,0,0}};\n for (int i = 0; i < rows; i++) {\n grid[i] = (int *)malloc(cols * sizeof(int));\n for (int j = 0; j < cols; j++) {\n grid[i][j] = grid3_data[i][j];\n }\n }\n assert(func0(grid, rows, cols, capacity) == 0);\n for (int i = 0; i < rows; i++) free(grid[i]);\n free(grid);\n\n // Test case 4\n rows = 2; cols = 4; capacity = 2;\n grid = (int **)malloc(rows * sizeof(int *));\n int grid4_data[2][4] = {{1,1,1,1}, {1,1,1,1}};\n for (int i = 0; i < rows; i++) {\n grid[i] = (int *)malloc(cols * sizeof(int));\n for (int j = 0; j < cols; j++) {\n grid[i][j] = grid4_data[i][j];\n }\n }\n assert(func0(grid, rows, cols, capacity) == 4);\n for (int i = 0; i < rows; i++) free(grid[i]);\n free(grid);\n\n // Test case 5\n rows = 2; cols = 4; capacity = 9;\n grid = (int **)malloc(rows * sizeof(int *));\n int grid5_data[2][4] = {{1,1,1,1}, {1,1,1,1}};\n for (int i = 0; i < rows; i++) {\n grid[i] = (int *)malloc(cols * sizeof(int));\n for (int j = 0; j < cols; j++) {\n grid[i][j] = grid5_data[i][j];\n }\n }\n assert(func0(grid, rows, cols, capacity) == 2);\nfor (int i = 0; i < rows; i++) free(grid[i]);\n free(grid);\n\n printf(\"All tests passed!\\n\");\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmov r8d, ecx\ntest esi, esi\njle short loc_159F\nmovsxd rsi, esi\nlea r10, [rdi+rsi*8]\nloc_1592:\ntest edx, edx\njg short loc_15A6\nadd rdi, 8\ncmp rdi, r10\njnz short loc_1592\nloc_159F:\nxor r9d, r9d\nmov eax, r9d\nretn\nloc_15A6:\nmovsxd rdx, edx\nxor r9d, r9d\nlea rsi, ds:0[rdx*4]\nnop dword ptr [rax+00h]\nloc_15B8:\nmov rax, [rdi]\nxor edx, edx\nlea rcx, [rax+rsi]\nnop dword ptr [rax+00000000h]\nloc_15C8:\nadd edx, [rax]\nadd rax, 4\ncmp rax, rcx\njnz short loc_15C8\ntest edx, edx\njle short loc_15F0\nlea eax, [rdx+r8-1]\nadd rdi, 8\ncdq\nidiv r8d\nadd r9d, eax\ncmp rdi, r10\njnz short loc_15B8\nmov eax, r9d\nretn\nloc_15F0:\nadd rdi, 8\ncmp rdi, r10\njnz short loc_15B8\nmov eax, r9d\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD **a1, int a2, int a3, int a4)\n{\n _DWORD **v4; // r10\n unsigned int v6; // r9d\n __int64 v7; // rsi\n _DWORD *v8; // rax\n int v9; // edx\n\n if ( a2 <= 0 )\n return 0LL;\n v4 = &a1[a2];\n while ( a3 <= 0 )\n {\n if ( ++a1 == v4 )\n return 0LL;\n }\n v6 = 0;\n v7 = a3;\n do\n {\n while ( 1 )\n {\n v8 = *a1;\n v9 = 0;\n do\n v9 += *v8++;\n while ( v8 != &(*a1)[v7] );\n if ( v9 <= 0 )\n break;\n ++a1;\n v6 += (v9 + a4 - 1) / a4;\n if ( a1 == v4 )\n return v6;\n }\n ++a1;\n }\n while ( a1 != v4 );\n return v6;\n}", + "ida_strip_asm": "sub_1580:\nendbr64\nmov r8d, ecx\ntest esi, esi\njle short loc_159F\nmovsxd rsi, esi\nlea r10, [rdi+rsi*8]\nloc_1592:\ntest edx, edx\njg short loc_15A6\nadd rdi, 8\ncmp rdi, r10\njnz short loc_1592\nloc_159F:\nxor r9d, r9d\nmov eax, r9d\nretn\nloc_15A6:\nmovsxd rdx, edx\nxor r9d, r9d\nlea rsi, ds:0[rdx*4]\nnop dword ptr [rax+00h]\nloc_15B8:\nmov rax, [rdi]\nxor edx, edx\nlea rcx, [rax+rsi]\nnop dword ptr [rax+00000000h]\nloc_15C8:\nadd edx, [rax]\nadd rax, 4\ncmp rax, rcx\njnz short loc_15C8\ntest edx, edx\njle short loc_15F0\nlea eax, [rdx+r8-1]\nadd rdi, 8\ncdq\nidiv r8d\nadd r9d, eax\ncmp rdi, r10\njnz short loc_15B8\nmov eax, r9d\nretn\nloc_15F0:\nadd rdi, 8\ncmp rdi, r10\njnz short loc_15B8\nmov eax, r9d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1580(_DWORD **a1, int a2, int a3, int a4)\n{\n _DWORD **v4; // r10\n unsigned int v6; // r9d\n __int64 v7; // rsi\n _DWORD *v8; // rax\n int v9; // edx\n\n if ( a2 <= 0 )\n return 0LL;\n v4 = &a1[a2];\n while ( a3 <= 0 )\n {\n if ( ++a1 == v4 )\n return 0LL;\n }\n v6 = 0;\n v7 = a3;\n do\n {\n while ( 1 )\n {\n v8 = *a1;\n v9 = 0;\n do\n v9 += *v8++;\n while ( v8 != &(*a1)[v7] );\n if ( v9 <= 0 )\n break;\n ++a1;\n v6 += (v9 + a4 - 1) / a4;\n if ( a1 == v4 )\n return v6;\n }\n ++a1;\n }\n while ( a1 != v4 );\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1580(uint32_t **a1, int a2, int a3, int a4) {\n uint32_t **v4;\n unsigned int v6;\n long long v7;\n uint32_t *v8;\n int v9;\n if (a2 <= 0) return 0LL;\n v4 = &a1[a2];\n while (a3 <= 0) {\n if (++a1 == v4) return 0LL;\n }\n v6 = 0;\n v7 = a3;\n do {\n while (1) {\n v8 = *a1;\n v9 = 0;\n do\n v9 += *v8++;\n while (v8 != &(*a1)[v7]);\n if (v9 <= 0) break;\n ++a1;\n v6 += (v9 + a4 - 1) / a4;\n if (a1 == v4) return v6;\n }\n ++a1;\n } while (a1 != v4);\n return v6;\n}", + "ida_pseudo_norm": "long long func0(uint32_t **a1, int a2, int a3, int a4) {\n uint32_t **v4;\n unsigned int v6;\n long long v7;\n uint32_t *v8;\n int v9;\n if (a2 <= 0) return 0LL;\n v4 = &a1[a2];\n while (a3 <= 0) {\n if (++a1 == v4) return 0LL;\n }\n v6 = 0;\n v7 = a3;\n do {\n while (1) {\n v8 = *a1;\n v9 = 0;\n do\n v9 += *v8++;\n while (v8 != &(*a1)[v7]);\n if (v9 <= 0) break;\n ++a1;\n v6 += (v9 + a4 - 1) / a4;\n if (a1 == v4) return v6;\n }\n ++a1;\n } while (a1 != v4);\n return v6;\n}" + }, + { + "index": "HumanEval-C-116", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(int *arr, int size) {\n int count_ones, x, y, temp;\n for (int i = 0; i < size; i++) {\n for (int j = i + 1; j < size; j++) {\n count_ones = 0;\n x = arr[i];\n y = arr[j];\n while (x > 0) {\n count_ones += x & 1;\n x >>= 1;\n }\n x = count_ones;\n count_ones = 0;\n while (y > 0) {\n count_ones += y & 1;\n y >>= 1;\n }\n y = count_ones;\n if (y < x || (y == x && arr[j] < arr[i])) {\n temp = arr[i];\n arr[i] = arr[j];\n arr[j] = temp;\n }\n }\n }\n}", + "test": "#include \n#include \n\nint issame(int *a, int size_a, int *b, int size_b) {\n if (size_a != size_b) return 0;\n for (int i = 0; i < size_a; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int test1[] = {1, 5, 2, 3, 4};\n int expected1[] = {1, 2, 4, 3, 5};\n func0(test1, 5);\n assert(issame(test1, 5, expected1, 5));\n\n int test3[] = {1, 0, 2, 3, 4};\n int expected3[] = {0, 1, 2, 4, 3};\n func0(test3, 5);\n assert(issame(test3, 5, expected3, 5));\n\n int test4[] = {2, 5, 77, 4, 5, 3, 5, 7, 2, 3, 4};\n int expected4[] = {2, 2, 4, 4, 3, 3, 5, 5, 5, 7, 77};\n func0(test4, 11);\n assert(issame(test4, 11, expected4, 11));\n\n int test5[] = {3, 6, 44, 12, 32, 5};\n int expected5[] = {32, 3, 5, 6, 12, 44};\n func0(test5, 6);\n assert(issame(test5, 6, expected5, 6));\n\n int test6[] = {2, 4, 8, 16, 32};\n int expected6[] = {2, 4, 8, 16, 32};\n func0(test6, 5);\n assert(issame(test6, 5, expected6, 5));\n\n printf(\"All tests passed!\\n\");\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_C], 0\njmp loc_12DD\nloc_11A4:\nmov eax, [rbp+var_C]\nadd eax, 1\nmov [rbp+var_8], eax\njmp loc_12CD\nloc_11B2:\nmov [rbp+var_18], 0\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_14], eax\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_10], eax\njmp short loc_11F9\nloc_11ED:\nmov eax, [rbp+var_14]\nand eax, 1\nadd [rbp+var_18], eax\nsar [rbp+var_14], 1\nloc_11F9:\ncmp [rbp+var_14], 0\njg short loc_11ED\nmov eax, [rbp+var_18]\nmov [rbp+var_14], eax\nmov [rbp+var_18], 0\njmp short loc_121A\nloc_120E:\nmov eax, [rbp+var_10]\nand eax, 1\nadd [rbp+var_18], eax\nsar [rbp+var_10], 1\nloc_121A:\ncmp [rbp+var_10], 0\njg short loc_120E\nmov eax, [rbp+var_18]\nmov [rbp+var_10], eax\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_14]\njl short loc_126A\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_14]\njnz loc_12C9\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njge short loc_12C9\nloc_126A:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nloc_12C9:\nadd [rbp+var_8], 1\nloc_12CD:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_2C]\njl loc_11B2\nadd [rbp+var_C], 1\nloc_12DD:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_2C]\njl loc_11A4\nnop\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 result; // rax\n int v3; // [rsp+14h] [rbp-18h]\n int v4; // [rsp+14h] [rbp-18h]\n int v5; // [rsp+18h] [rbp-14h]\n int v6; // [rsp+18h] [rbp-14h]\n int v7; // [rsp+1Ch] [rbp-10h]\n unsigned int i; // [rsp+20h] [rbp-Ch]\n int j; // [rsp+24h] [rbp-8h]\n int v10; // [rsp+28h] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a2 )\n break;\n for ( j = i + 1; j < a2; ++j )\n {\n v3 = 0;\n v5 = *(_DWORD *)(4LL * (int)i + a1);\n v7 = *(_DWORD *)(4LL * j + a1);\n while ( v5 > 0 )\n {\n v3 += v5 & 1;\n v5 >>= 1;\n }\n v6 = v3;\n v4 = 0;\n while ( v7 > 0 )\n {\n v4 += v7 & 1;\n v7 >>= 1;\n }\n if ( v4 < v6 || v4 == v6 && *(_DWORD *)(4LL * j + a1) < *(_DWORD *)(4LL * (int)i + a1) )\n {\n v10 = *(_DWORD *)(4LL * (int)i + a1);\n *(_DWORD *)(4LL * (int)i + a1) = *(_DWORD *)(4LL * j + a1);\n *(_DWORD *)(a1 + 4LL * j) = v10;\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_C], 0\njmp loc_12DD\nloc_11A4:\nmov eax, [rbp+var_C]\nadd eax, 1\nmov [rbp+var_8], eax\njmp loc_12CD\nloc_11B2:\nmov [rbp+var_18], 0\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_14], eax\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_10], eax\njmp short loc_11F9\nloc_11ED:\nmov eax, [rbp+var_14]\nand eax, 1\nadd [rbp+var_18], eax\nsar [rbp+var_14], 1\nloc_11F9:\ncmp [rbp+var_14], 0\njg short loc_11ED\nmov eax, [rbp+var_18]\nmov [rbp+var_14], eax\nmov [rbp+var_18], 0\njmp short loc_121A\nloc_120E:\nmov eax, [rbp+var_10]\nand eax, 1\nadd [rbp+var_18], eax\nsar [rbp+var_10], 1\nloc_121A:\ncmp [rbp+var_10], 0\njg short loc_120E\nmov eax, [rbp+var_18]\nmov [rbp+var_10], eax\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_14]\njl short loc_126A\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_14]\njnz loc_12C9\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njge short loc_12C9\nloc_126A:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nloc_12C9:\nadd [rbp+var_8], 1\nloc_12CD:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_2C]\njl loc_11B2\nadd [rbp+var_C], 1\nloc_12DD:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_2C]\njl loc_11A4\nnop\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2)\n{\n __int64 result; // rax\n int v3; // [rsp+14h] [rbp-18h]\n int v4; // [rsp+14h] [rbp-18h]\n int v5; // [rsp+18h] [rbp-14h]\n int v6; // [rsp+18h] [rbp-14h]\n int v7; // [rsp+1Ch] [rbp-10h]\n unsigned int i; // [rsp+20h] [rbp-Ch]\n int j; // [rsp+24h] [rbp-8h]\n int v10; // [rsp+28h] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a2 )\n break;\n for ( j = i + 1; j < a2; ++j )\n {\n v3 = 0;\n v5 = *(_DWORD *)(4LL * (int)i + a1);\n v7 = *(_DWORD *)(4LL * j + a1);\n while ( v5 > 0 )\n {\n v3 += v5 & 1;\n v5 >>= 1;\n }\n v6 = v3;\n v4 = 0;\n while ( v7 > 0 )\n {\n v4 += v7 & 1;\n v7 >>= 1;\n }\n if ( v4 < v6 || v4 == v6 && *(_DWORD *)(4LL * j + a1) < *(_DWORD *)(4LL * (int)i + a1) )\n {\n v10 = *(_DWORD *)(4LL * (int)i + a1);\n *(_DWORD *)(4LL * (int)i + a1) = *(_DWORD *)(4LL * j + a1);\n *(_DWORD *)(a1 + 4LL * j) = v10;\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2) {\n long long result;\n int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n unsigned int i;\n int j;\n int v10;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a2) break;\n for (j = i + 1; j < a2; ++j) {\n v3 = 0;\n v5 = *(uint32_t *)(4LL * (int)i + a1);\n v7 = *(uint32_t *)(4LL * j + a1);\n while (v5 > 0) {\n v3 += v5 & 1;\n v5 >>= 1;\n }\n v6 = v3;\n v4 = 0;\n while (v7 > 0) {\n v4 += v7 & 1;\n v7 >>= 1;\n }\n if (v4 < v6 || v4 == v6 && *(uint32_t *)(4LL * j + a1) <\n *(uint32_t *)(4LL * (int)i + a1)) {\n v10 = *(uint32_t *)(4LL * (int)i + a1);\n *(uint32_t *)(4LL * (int)i + a1) = *(uint32_t *)(4LL * j + a1);\n *(uint32_t *)(a1 + 4LL * j) = v10;\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long result;\n int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n unsigned int i;\n int j;\n int v10;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a2) break;\n for (j = i + 1; j < a2; ++j) {\n v3 = 0;\n v5 = *(uint32_t *)(4LL * (int)i + a1);\n v7 = *(uint32_t *)(4LL * j + a1);\n while (v5 > 0) {\n v3 += v5 & 1;\n v5 >>= 1;\n }\n v6 = v3;\n v4 = 0;\n while (v7 > 0) {\n v4 += v7 & 1;\n v7 >>= 1;\n }\n if (v4 < v6 || v4 == v6 && *(uint32_t *)(4LL * j + a1) <\n *(uint32_t *)(4LL * (int)i + a1)) {\n v10 = *(uint32_t *)(4LL * (int)i + a1);\n *(uint32_t *)(4LL * (int)i + a1) = *(uint32_t *)(4LL * j + a1);\n *(uint32_t *)(a1 + 4LL * j) = v10;\n }\n }\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-116", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(int *arr, int size) {\n int count_ones, x, y, temp;\n for (int i = 0; i < size; i++) {\n for (int j = i + 1; j < size; j++) {\n count_ones = 0;\n x = arr[i];\n y = arr[j];\n while (x > 0) {\n count_ones += x & 1;\n x >>= 1;\n }\n x = count_ones;\n count_ones = 0;\n while (y > 0) {\n count_ones += y & 1;\n y >>= 1;\n }\n y = count_ones;\n if (y < x || (y == x && arr[j] < arr[i])) {\n temp = arr[i];\n arr[i] = arr[j];\n arr[j] = temp;\n }\n }\n }\n}", + "test": "#include \n#include \n\nint issame(int *a, int size_a, int *b, int size_b) {\n if (size_a != size_b) return 0;\n for (int i = 0; i < size_a; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int test1[] = {1, 5, 2, 3, 4};\n int expected1[] = {1, 2, 4, 3, 5};\n func0(test1, 5);\n assert(issame(test1, 5, expected1, 5));\n\n int test3[] = {1, 0, 2, 3, 4};\n int expected3[] = {0, 1, 2, 4, 3};\n func0(test3, 5);\n assert(issame(test3, 5, expected3, 5));\n\n int test4[] = {2, 5, 77, 4, 5, 3, 5, 7, 2, 3, 4};\n int expected4[] = {2, 2, 4, 4, 3, 3, 5, 5, 5, 7, 77};\n func0(test4, 11);\n assert(issame(test4, 11, expected4, 11));\n\n int test5[] = {3, 6, 44, 12, 32, 5};\n int expected5[] = {32, 3, 5, 6, 12, 44};\n func0(test5, 6);\n assert(issame(test5, 6, expected5, 6));\n\n int test6[] = {2, 4, 8, 16, 32};\n int expected6[] = {2, 4, 8, 16, 32};\n func0(test6, 5);\n assert(issame(test6, 5, expected6, 5));\n\n printf(\"All tests passed!\\n\");\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle locret_128D\nmov edx, esi\nlea r10, [rdi+4]\nlea r8d, [rsi-1]\nmov esi, esi\nmovsxd rdx, edx\nmov eax, 1\nlea r9, [rdi+8]\nmov edi, r8d\nmov rcx, rsi\ncmp rax, rsi\njz locret_128D\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\njmp loc_1255\nloc_11CB:\nmov r11d, 0\njmp short loc_122A\nloc_11D3:\nmov [r15-4], r13d\nmov [r14], r12d\nloc_11DA:\nadd rbx, 4\ncmp rbx, rsi\njz short loc_123B\nloc_11E3:\nmov r15, r10\nmov r12d, [r10-4]\nmov r14, rbx\nmov r13d, [rbx]\ntest r12d, r12d\njle short loc_126F\nmov eax, r12d\nmov r8d, 0\nloc_11FE:\nmov r11d, eax\nand r11d, 1\nadd r8d, r11d\nsar eax, 1\ntest eax, eax\njg short loc_11FE\ntest r13d, r13d\njle short loc_11CB\nloc_1213:\nmov eax, r13d\nmov r11d, 0\nloc_121C:\nmov ebp, eax\nand ebp, 1\nadd r11d, ebp\nsar eax, 1\ntest eax, eax\njg short loc_121C\nloc_122A:\ncmp r8d, r11d\njg short loc_11D3\nloc_122F:\ncmp r12d, r13d\njle short loc_11DA\ncmp r11d, r8d\njnz short loc_11DA\njmp short loc_11D3\nloc_123B:\nmov rax, [rsp+30h+var_38]\nlea rsi, [rax+1]\nadd r10, 4\ncmp rax, rdx\njz short loc_1282\nmov rax, rsi\ncmp rsi, rcx\njz short loc_1282\nloc_1255:\nmov esi, edi\nsub esi, eax\nlea rsi, [rax+rsi-1]\nlea rsi, [r9+rsi*4]\nmov rbx, r10\nmov [rsp+30h+var_38], rax\njmp loc_11E3\nloc_126F:\nmov r8d, 0\nmov r11d, 0\ntest r13d, r13d\njg short loc_1213\njmp short loc_122F\nloc_1282:\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nlocret_128D:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2)\n{\n int *v2; // r10\n __int64 v3; // rdx\n __int64 v4; // rax\n __int64 v5; // r9\n int v6; // edi\n __int64 v7; // rcx\n int v8; // r11d\n int *v9; // rbx\n int v10; // r12d\n int v11; // r13d\n int v12; // eax\n int v13; // r8d\n int v14; // eax\n int *v15; // rsi\n __int64 v16; // [rsp+0h] [rbp-38h]\n\n if ( a2 <= 0 )\n return;\n v2 = (int *)(a1 + 4);\n v3 = a2;\n v4 = 1LL;\n v5 = a1 + 8;\n v6 = a2 - 1;\n v7 = (unsigned int)a2;\n if ( a2 == 1LL )\n return;\n while ( 2 )\n {\n v15 = (int *)(v5 + 4 * (v4 + (unsigned int)(v6 - v4) - 1));\n v9 = v2;\n v16 = v4;\n do\n {\n v10 = *(v2 - 1);\n v11 = *v9;\n if ( v10 <= 0 )\n {\n v13 = 0;\n v8 = 0;\n if ( v11 <= 0 )\n goto LABEL_14;\n }\n else\n {\n v12 = *(v2 - 1);\n v13 = 0;\n do\n {\n v13 += v12 & 1;\n v12 >>= 1;\n }\n while ( v12 > 0 );\n if ( v11 <= 0 )\n {\n v8 = 0;\n goto LABEL_13;\n }\n }\n v14 = *v9;\n v8 = 0;\n do\n {\n v8 += v14 & 1;\n v14 >>= 1;\n }\n while ( v14 > 0 );\nLABEL_13:\n if ( v13 > v8 )\n goto LABEL_5;\nLABEL_14:\n if ( v10 > v11 && v8 == v13 )\n {\nLABEL_5:\n *(v2 - 1) = v11;\n *v9 = v10;\n }\n ++v9;\n }\n while ( v9 != v15 );\n ++v2;\n if ( v16 != v3 )\n {\n v4 = v16 + 1;\n if ( v16 + 1 != v7 )\n continue;\n }\n break;\n }\n}", + "ida_strip_asm": "sub_1189:\nendbr64\ntest esi, esi\njle locret_128D\nmov edx, esi\nlea r10, [rdi+4]\nlea r8d, [rsi-1]\nmov esi, esi\nmovsxd rdx, edx\nmov eax, 1\nlea r9, [rdi+8]\nmov edi, r8d\nmov rcx, rsi\ncmp rax, rsi\njz locret_128D\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\njmp loc_1255\nloc_11CB:\nmov r11d, 0\njmp short loc_122A\nloc_11D3:\nmov [r15-4], r13d\nmov [r14], r12d\nloc_11DA:\nadd rbx, 4\ncmp rbx, rsi\njz short loc_123B\nloc_11E3:\nmov r15, r10\nmov r12d, [r10-4]\nmov r14, rbx\nmov r13d, [rbx]\ntest r12d, r12d\njle short loc_126F\nmov eax, r12d\nmov r8d, 0\nloc_11FE:\nmov r11d, eax\nand r11d, 1\nadd r8d, r11d\nsar eax, 1\ntest eax, eax\njg short loc_11FE\ntest r13d, r13d\njle short loc_11CB\nloc_1213:\nmov eax, r13d\nmov r11d, 0\nloc_121C:\nmov ebp, eax\nand ebp, 1\nadd r11d, ebp\nsar eax, 1\ntest eax, eax\njg short loc_121C\nloc_122A:\ncmp r8d, r11d\njg short loc_11D3\nloc_122F:\ncmp r12d, r13d\njle short loc_11DA\ncmp r11d, r8d\njnz short loc_11DA\njmp short loc_11D3\nloc_123B:\nmov rax, [rsp+30h+var_38]\nlea rsi, [rax+1]\nadd r10, 4\ncmp rax, rdx\njz short loc_1282\nmov rax, rsi\ncmp rsi, rcx\njz short loc_1282\nloc_1255:\nmov esi, edi\nsub esi, eax\nlea rsi, [rax+rsi-1]\nlea rsi, [r9+rsi*4]\nmov rbx, r10\nmov [rsp+30h+var_38], rax\njmp loc_11E3\nloc_126F:\nmov r8d, 0\nmov r11d, 0\ntest r13d, r13d\njg short loc_1213\njmp short loc_122F\nloc_1282:\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nlocret_128D:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1189(__int64 a1, int a2)\n{\n int *v2; // r10\n __int64 v3; // rdx\n __int64 v4; // rax\n __int64 v5; // r9\n int v6; // edi\n __int64 v7; // rcx\n int v8; // r11d\n int *v9; // rbx\n int v10; // r12d\n int v11; // r13d\n int v12; // eax\n int v13; // r8d\n int v14; // eax\n int *v15; // rsi\n __int64 v16; // [rsp+0h] [rbp-38h]\n\n if ( a2 <= 0 )\n return;\n v2 = (int *)(a1 + 4);\n v3 = a2;\n v4 = 1LL;\n v5 = a1 + 8;\n v6 = a2 - 1;\n v7 = (unsigned int)a2;\n if ( a2 == 1LL )\n return;\n while ( 2 )\n {\n v15 = (int *)(v5 + 4 * (v4 + (unsigned int)(v6 - v4) - 1));\n v9 = v2;\n v16 = v4;\n do\n {\n v10 = *(v2 - 1);\n v11 = *v9;\n if ( v10 <= 0 )\n {\n v13 = 0;\n v8 = 0;\n if ( v11 <= 0 )\n goto LABEL_14;\n }\n else\n {\n v12 = *(v2 - 1);\n v13 = 0;\n do\n {\n v13 += v12 & 1;\n v12 >>= 1;\n }\n while ( v12 > 0 );\n if ( v11 <= 0 )\n {\n v8 = 0;\n goto LABEL_13;\n }\n }\n v14 = *v9;\n v8 = 0;\n do\n {\n v8 += v14 & 1;\n v14 >>= 1;\n }\n while ( v14 > 0 );\nLABEL_13:\n if ( v13 > v8 )\n goto LABEL_5;\nLABEL_14:\n if ( v10 > v11 && v8 == v13 )\n {\nLABEL_5:\n *(v2 - 1) = v11;\n *v9 = v10;\n }\n ++v9;\n }\n while ( v9 != v15 );\n ++v2;\n if ( v16 != v3 )\n {\n v4 = v16 + 1;\n if ( v16 + 1 != v7 )\n continue;\n }\n break;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1189(long long a1, int a2) {\n int *v2;\n long long v3;\n long long v4;\n long long v5;\n int v6;\n long long v7;\n int v8;\n int *v9;\n int v10;\n int v11;\n int v12;\n int v13;\n int v14;\n int *v15;\n long long v16;\n if (a2 <= 0) return;\n v2 = (int *)(a1 + 4);\n v3 = a2;\n v4 = 1LL;\n v5 = a1 + 8;\n v6 = a2 - 1;\n v7 = (unsigned int)a2;\n if (a2 == 1LL) return;\n while (2) {\n v15 = (int *)(v5 + 4 * (v4 + (unsigned int)(v6 - v4) - 1));\n v9 = v2;\n v16 = v4;\n do {\n v10 = *(v2 - 1);\n v11 = *v9;\n if (v10 <= 0) {\n v13 = 0;\n v8 = 0;\n if (v11 <= 0) goto LABEL_14;\n } else {\n v12 = *(v2 - 1);\n v13 = 0;\n do {\n v13 += v12 & 1;\n v12 >>= 1;\n } while (v12 > 0);\n if (v11 <= 0) {\n v8 = 0;\n goto LABEL_13;\n }\n }\n v14 = *v9;\n v8 = 0;\n do {\n v8 += v14 & 1;\n v14 >>= 1;\n } while (v14 > 0);\n LABEL_13:\n if (v13 > v8) goto LABEL_5;\n LABEL_14:\n if (v10 > v11 && v8 == v13) {\n LABEL_5:\n *(v2 - 1) = v11;\n *v9 = v10;\n }\n ++v9;\n } while (v9 != v15);\n ++v2;\n if (v16 != v3) {\n v4 = v16 + 1;\n if (v16 + 1 != v7) continue;\n }\n break;\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2) {\n int *v2;\n long long v3;\n long long v4;\n long long v5;\n int v6;\n long long v7;\n int v8;\n int *v9;\n int v10;\n int v11;\n int v12;\n int v13;\n int v14;\n int *v15;\n long long v16;\n if (a2 <= 0) return;\n v2 = (int *)(a1 + 4);\n v3 = a2;\n v4 = 1LL;\n v5 = a1 + 8;\n v6 = a2 - 1;\n v7 = (unsigned int)a2;\n if (a2 == 1LL) return;\n while (2) {\n v15 = (int *)(v5 + 4 * (v4 + (unsigned int)(v6 - v4) - 1));\n v9 = v2;\n v16 = v4;\n do {\n v10 = *(v2 - 1);\n v11 = *v9;\n if (v10 <= 0) {\n v13 = 0;\n v8 = 0;\n if (v11 <= 0) goto LABEL_14;\n } else {\n v12 = *(v2 - 1);\n v13 = 0;\n do {\n v13 += v12 & 1;\n v12 >>= 1;\n } while (v12 > 0);\n if (v11 <= 0) {\n v8 = 0;\n goto LABEL_13;\n }\n }\n v14 = *v9;\n v8 = 0;\n do {\n v8 += v14 & 1;\n v14 >>= 1;\n } while (v14 > 0);\n LABEL_13:\n if (v13 > v8) goto LABEL_5;\n LABEL_14:\n if (v10 > v11 && v8 == v13) {\n LABEL_5:\n *(v2 - 1) = v11;\n *v9 = v10;\n }\n ++v9;\n } while (v9 != v15);\n ++v2;\n if (v16 != v3) {\n v4 = v16 + 1;\n if (v16 + 1 != v7) continue;\n }\n break;\n }\n}" + }, + { + "index": "HumanEval-C-116", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(int *arr, int size) {\n int count_ones, x, y, temp;\n for (int i = 0; i < size; i++) {\n for (int j = i + 1; j < size; j++) {\n count_ones = 0;\n x = arr[i];\n y = arr[j];\n while (x > 0) {\n count_ones += x & 1;\n x >>= 1;\n }\n x = count_ones;\n count_ones = 0;\n while (y > 0) {\n count_ones += y & 1;\n y >>= 1;\n }\n y = count_ones;\n if (y < x || (y == x && arr[j] < arr[i])) {\n temp = arr[i];\n arr[i] = arr[j];\n arr[j] = temp;\n }\n }\n }\n}", + "test": "#include \n#include \n\nint issame(int *a, int size_a, int *b, int size_b) {\n if (size_a != size_b) return 0;\n for (int i = 0; i < size_a; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int test1[] = {1, 5, 2, 3, 4};\n int expected1[] = {1, 2, 4, 3, 5};\n func0(test1, 5);\n assert(issame(test1, 5, expected1, 5));\n\n int test3[] = {1, 0, 2, 3, 4};\n int expected3[] = {0, 1, 2, 4, 3};\n func0(test3, 5);\n assert(issame(test3, 5, expected3, 5));\n\n int test4[] = {2, 5, 77, 4, 5, 3, 5, 7, 2, 3, 4};\n int expected4[] = {2, 2, 4, 4, 3, 3, 5, 5, 5, 7, 77};\n func0(test4, 11);\n assert(issame(test4, 11, expected4, 11));\n\n int test5[] = {3, 6, 44, 12, 32, 5};\n int expected5[] = {32, 3, 5, 6, 12, 44};\n func0(test5, 6);\n assert(issame(test5, 6, expected5, 6));\n\n int test6[] = {2, 4, 8, 16, 32};\n int expected6[] = {2, 4, 8, 16, 32};\n func0(test6, 5);\n assert(issame(test6, 5, expected6, 5));\n\n printf(\"All tests passed!\\n\");\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle locret_158E\npush rbp\nmov r10, rdi\nmov ebp, esi\nmov r11d, 1\npush rbx\nmov ebx, esi\ncmp esi, 1\njz short loc_1564\nloc_1500:\nmov rdi, r11\nnop dword ptr [rax+rax+00h]\nloc_1508:\nmov r8d, [r10+r11*4-4]\nmov r9d, [r10+rdi*4]\ntest r8d, r8d\njle short loc_1580\nmov eax, r8d\nxor ecx, ecx\nnop dword ptr [rax+rax+00h]\nloc_1520:\nmov edx, eax\nand edx, 1\nadd ecx, edx\nsar eax, 1\njnz short loc_1520\ntest r9d, r9d\njle short loc_1543\nloc_1530:\nmov edx, r9d\nxor eax, eax\nnop dword ptr [rax]\nloc_1538:\nmov esi, edx\nand esi, 1\nadd eax, esi\nsar edx, 1\njnz short loc_1538\nloc_1543:\ncmp ecx, eax\njg short loc_1570\nsetz al\nloc_154A:\ncmp r8d, r9d\njle short loc_1553\ntest al, al\njnz short loc_1570\nloc_1553:\nadd rdi, 1\ncmp ebx, edi\njg short loc_1508\nadd r11, 1\ncmp r11, rbp\njnz short loc_1500\nloc_1564:\npop rbx\npop rbp\nretn\nloc_1570:\nmov [r10+r11*4-4], r9d\nmov [r10+rdi*4], r8d\njmp short loc_1553\nloc_1580:\nxor ecx, ecx\nmov eax, 1\ntest r9d, r9d\njg short loc_1530\njmp short loc_154A\nlocret_158E:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2)\n{\n __int64 v3; // r11\n __int64 v4; // rdi\n int v5; // r8d\n int v6; // r9d\n int v7; // eax\n int v8; // ecx\n int v9; // edx\n bool v10; // al\n\n if ( a2 > 0 )\n {\n v3 = 1LL;\n if ( a2 != 1 )\n {\n do\n {\n v4 = v3;\n do\n {\n v5 = *(_DWORD *)(a1 + 4 * v3 - 4);\n v6 = *(_DWORD *)(a1 + 4 * v4);\n if ( v5 > 0 )\n {\n v7 = *(_DWORD *)(a1 + 4 * v3 - 4);\n v8 = 0;\n do\n {\n v8 += v7 & 1;\n v7 >>= 1;\n }\n while ( v7 );\n if ( v6 > 0 )\n {\nLABEL_8:\n v9 = *(_DWORD *)(a1 + 4 * v4);\n v7 = 0;\n do\n {\n v7 += v9 & 1;\n v9 >>= 1;\n }\n while ( v9 );\n }\n if ( v8 > v7 )\n goto LABEL_17;\n v10 = v8 == v7;\n goto LABEL_12;\n }\n v8 = 0;\n v10 = 1;\n if ( v6 > 0 )\n goto LABEL_8;\nLABEL_12:\n if ( v5 > v6 && v10 )\n {\nLABEL_17:\n *(_DWORD *)(a1 + 4 * v3 - 4) = v6;\n *(_DWORD *)(a1 + 4 * v4) = v5;\n }\n ++v4;\n }\n while ( a2 > (int)v4 );\n ++v3;\n }\n while ( v3 != a2 );\n }\n }\n}", + "ida_strip_asm": "sub_14E0:\nendbr64\ntest esi, esi\njle locret_158E\npush rbp\nmov r10, rdi\nmov ebp, esi\nmov r11d, 1\npush rbx\nmov ebx, esi\ncmp esi, 1\njz short loc_1564\nloc_1500:\nmov rdi, r11\nnop dword ptr [rax+rax+00h]\nloc_1508:\nmov r8d, [r10+r11*4-4]\nmov r9d, [r10+rdi*4]\ntest r8d, r8d\njle short loc_1580\nmov eax, r8d\nxor ecx, ecx\nnop dword ptr [rax+rax+00h]\nloc_1520:\nmov edx, eax\nand edx, 1\nadd ecx, edx\nsar eax, 1\njnz short loc_1520\ntest r9d, r9d\njle short loc_1543\nloc_1530:\nmov edx, r9d\nxor eax, eax\nnop dword ptr [rax]\nloc_1538:\nmov esi, edx\nand esi, 1\nadd eax, esi\nsar edx, 1\njnz short loc_1538\nloc_1543:\ncmp ecx, eax\njg short loc_1570\nsetz al\nloc_154A:\ncmp r8d, r9d\njle short loc_1553\ntest al, al\njnz short loc_1570\nloc_1553:\nadd rdi, 1\ncmp ebx, edi\njg short loc_1508\nadd r11, 1\ncmp r11, rbp\njnz short loc_1500\nloc_1564:\npop rbx\npop rbp\nretn\nloc_1570:\nmov [r10+r11*4-4], r9d\nmov [r10+rdi*4], r8d\njmp short loc_1553\nloc_1580:\nxor ecx, ecx\nmov eax, 1\ntest r9d, r9d\njg short loc_1530\njmp short loc_154A\nlocret_158E:\nretn", + "ida_strip_pseudo": "void __fastcall sub_14E0(__int64 a1, int a2)\n{\n __int64 v3; // r11\n __int64 v4; // rdi\n int v5; // r8d\n int v6; // r9d\n int v7; // eax\n int v8; // ecx\n int v9; // edx\n bool v10; // al\n\n if ( a2 > 0 )\n {\n v3 = 1LL;\n if ( a2 != 1 )\n {\n do\n {\n v4 = v3;\n do\n {\n v5 = *(_DWORD *)(a1 + 4 * v3 - 4);\n v6 = *(_DWORD *)(a1 + 4 * v4);\n if ( v5 > 0 )\n {\n v7 = *(_DWORD *)(a1 + 4 * v3 - 4);\n v8 = 0;\n do\n {\n v8 += v7 & 1;\n v7 >>= 1;\n }\n while ( v7 );\n if ( v6 > 0 )\n {\nLABEL_8:\n v9 = *(_DWORD *)(a1 + 4 * v4);\n v7 = 0;\n do\n {\n v7 += v9 & 1;\n v9 >>= 1;\n }\n while ( v9 );\n }\n if ( v8 > v7 )\n goto LABEL_17;\n v10 = v8 == v7;\n goto LABEL_12;\n }\n v8 = 0;\n v10 = 1;\n if ( v6 > 0 )\n goto LABEL_8;\nLABEL_12:\n if ( v5 > v6 && v10 )\n {\nLABEL_17:\n *(_DWORD *)(a1 + 4 * v3 - 4) = v6;\n *(_DWORD *)(a1 + 4 * v4) = v5;\n }\n ++v4;\n }\n while ( a2 > (int)v4 );\n ++v3;\n }\n while ( v3 != a2 );\n }\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_14E0(long long a1, int a2) {\n long long v3;\n long long v4;\n int v5;\n int v6;\n int v7;\n int v8;\n int v9;\n bool v10;\n if (a2 > 0) {\n v3 = 1LL;\n if (a2 != 1) {\n do {\n v4 = v3;\n do {\n v5 = *(uint32_t *)(a1 + 4 * v3 - 4);\n v6 = *(uint32_t *)(a1 + 4 * v4);\n if (v5 > 0) {\n v7 = *(uint32_t *)(a1 + 4 * v3 - 4);\n v8 = 0;\n do {\n v8 += v7 & 1;\n v7 >>= 1;\n } while (v7);\n if (v6 > 0) {\n LABEL_8:\n v9 = *(uint32_t *)(a1 + 4 * v4);\n v7 = 0;\n do {\n v7 += v9 & 1;\n v9 >>= 1;\n } while (v9);\n }\n if (v8 > v7) goto LABEL_17;\n v10 = v8 == v7;\n goto LABEL_12;\n }\n v8 = 0;\n v10 = 1;\n if (v6 > 0) goto LABEL_8;\n LABEL_12:\n if (v5 > v6 && v10) {\n LABEL_17:\n *(uint32_t *)(a1 + 4 * v3 - 4) = v6;\n *(uint32_t *)(a1 + 4 * v4) = v5;\n }\n ++v4;\n } while (a2 > (int)v4);\n ++v3;\n } while (v3 != a2);\n }\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2) {\n long long v3;\n long long v4;\n int v5;\n int v6;\n int v7;\n int v8;\n int v9;\n bool v10;\n if (a2 > 0) {\n v3 = 1LL;\n if (a2 != 1) {\n do {\n v4 = v3;\n do {\n v5 = *(uint32_t *)(a1 + 4 * v3 - 4);\n v6 = *(uint32_t *)(a1 + 4 * v4);\n if (v5 > 0) {\n v7 = *(uint32_t *)(a1 + 4 * v3 - 4);\n v8 = 0;\n do {\n v8 += v7 & 1;\n v7 >>= 1;\n } while (v7);\n if (v6 > 0) {\n LABEL_8:\n v9 = *(uint32_t *)(a1 + 4 * v4);\n v7 = 0;\n do {\n v7 += v9 & 1;\n v9 >>= 1;\n } while (v9);\n }\n if (v8 > v7) goto LABEL_17;\n v10 = v8 == v7;\n goto LABEL_12;\n }\n v8 = 0;\n v10 = 1;\n if (v6 > 0) goto LABEL_8;\n LABEL_12:\n if (v5 > v6 && v10) {\n LABEL_17:\n *(uint32_t *)(a1 + 4 * v3 - 4) = v6;\n *(uint32_t *)(a1 + 4 * v4) = v5;\n }\n ++v4;\n } while (a2 > (int)v4);\n ++v3;\n } while (v3 != a2);\n }\n }\n}" + }, + { + "index": "HumanEval-C-116", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(int *arr, int size) {\n int count_ones, x, y, temp;\n for (int i = 0; i < size; i++) {\n for (int j = i + 1; j < size; j++) {\n count_ones = 0;\n x = arr[i];\n y = arr[j];\n while (x > 0) {\n count_ones += x & 1;\n x >>= 1;\n }\n x = count_ones;\n count_ones = 0;\n while (y > 0) {\n count_ones += y & 1;\n y >>= 1;\n }\n y = count_ones;\n if (y < x || (y == x && arr[j] < arr[i])) {\n temp = arr[i];\n arr[i] = arr[j];\n arr[j] = temp;\n }\n }\n }\n}", + "test": "#include \n#include \n\nint issame(int *a, int size_a, int *b, int size_b) {\n if (size_a != size_b) return 0;\n for (int i = 0; i < size_a; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int test1[] = {1, 5, 2, 3, 4};\n int expected1[] = {1, 2, 4, 3, 5};\n func0(test1, 5);\n assert(issame(test1, 5, expected1, 5));\n\n int test3[] = {1, 0, 2, 3, 4};\n int expected3[] = {0, 1, 2, 4, 3};\n func0(test3, 5);\n assert(issame(test3, 5, expected3, 5));\n\n int test4[] = {2, 5, 77, 4, 5, 3, 5, 7, 2, 3, 4};\n int expected4[] = {2, 2, 4, 4, 3, 3, 5, 5, 5, 7, 77};\n func0(test4, 11);\n assert(issame(test4, 11, expected4, 11));\n\n int test5[] = {3, 6, 44, 12, 32, 5};\n int expected5[] = {32, 3, 5, 6, 12, 44};\n func0(test5, 6);\n assert(issame(test5, 6, expected5, 6));\n\n int test6[] = {2, 4, 8, 16, 32};\n int expected6[] = {2, 4, 8, 16, 32};\n func0(test6, 5);\n assert(issame(test6, 5, expected6, 5));\n\n printf(\"All tests passed!\\n\");\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle locret_158E\npush rbp\nmov r10, rdi\nmov ebp, esi\nmov r11d, 1\npush rbx\nmov ebx, esi\ncmp esi, 1\njz short loc_1564\nloc_1500:\nmov rdi, r11\nnop dword ptr [rax+rax+00h]\nloc_1508:\nmov r8d, [r10+r11*4-4]\nmov r9d, [r10+rdi*4]\ntest r8d, r8d\njle short loc_1580\nmov eax, r8d\nxor ecx, ecx\nnop dword ptr [rax+rax+00h]\nloc_1520:\nmov edx, eax\nand edx, 1\nadd ecx, edx\nsar eax, 1\njnz short loc_1520\ntest r9d, r9d\njle short loc_1543\nloc_1530:\nmov edx, r9d\nxor eax, eax\nnop dword ptr [rax]\nloc_1538:\nmov esi, edx\nand esi, 1\nadd eax, esi\nsar edx, 1\njnz short loc_1538\nloc_1543:\ncmp ecx, eax\njg short loc_1570\nsetz al\nloc_154A:\ncmp r8d, r9d\njle short loc_1553\ntest al, al\njnz short loc_1570\nloc_1553:\nadd rdi, 1\ncmp ebx, edi\njg short loc_1508\nadd r11, 1\ncmp rbp, r11\njnz short loc_1500\nloc_1564:\npop rbx\npop rbp\nretn\nloc_1570:\nmov [r10+r11*4-4], r9d\nmov [r10+rdi*4], r8d\njmp short loc_1553\nloc_1580:\nxor ecx, ecx\nmov eax, 1\ntest r9d, r9d\njg short loc_1530\njmp short loc_154A\nlocret_158E:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2)\n{\n __int64 v3; // r11\n __int64 v4; // rdi\n int v5; // r8d\n int v6; // r9d\n int v7; // eax\n int v8; // ecx\n int v9; // edx\n bool v10; // al\n\n if ( a2 > 0 )\n {\n v3 = 1LL;\n if ( a2 != 1 )\n {\n do\n {\n v4 = v3;\n do\n {\n v5 = *(_DWORD *)(a1 + 4 * v3 - 4);\n v6 = *(_DWORD *)(a1 + 4 * v4);\n if ( v5 > 0 )\n {\n v7 = *(_DWORD *)(a1 + 4 * v3 - 4);\n v8 = 0;\n do\n {\n v8 += v7 & 1;\n v7 >>= 1;\n }\n while ( v7 );\n if ( v6 > 0 )\n {\nLABEL_8:\n v9 = *(_DWORD *)(a1 + 4 * v4);\n v7 = 0;\n do\n {\n v7 += v9 & 1;\n v9 >>= 1;\n }\n while ( v9 );\n }\n if ( v8 > v7 )\n goto LABEL_17;\n v10 = v8 == v7;\n goto LABEL_12;\n }\n v8 = 0;\n v10 = 1;\n if ( v6 > 0 )\n goto LABEL_8;\nLABEL_12:\n if ( v5 > v6 && v10 )\n {\nLABEL_17:\n *(_DWORD *)(a1 + 4 * v3 - 4) = v6;\n *(_DWORD *)(a1 + 4 * v4) = v5;\n }\n ++v4;\n }\n while ( a2 > (int)v4 );\n ++v3;\n }\n while ( a2 != v3 );\n }\n }\n}", + "ida_strip_asm": "sub_14E0:\nendbr64\ntest esi, esi\njle locret_158E\npush rbp\nmov r10, rdi\nmov ebp, esi\nmov r11d, 1\npush rbx\nmov ebx, esi\ncmp esi, 1\njz short loc_1564\nloc_1500:\nmov rdi, r11\nnop dword ptr [rax+rax+00h]\nloc_1508:\nmov r8d, [r10+r11*4-4]\nmov r9d, [r10+rdi*4]\ntest r8d, r8d\njle short loc_1580\nmov eax, r8d\nxor ecx, ecx\nnop dword ptr [rax+rax+00h]\nloc_1520:\nmov edx, eax\nand edx, 1\nadd ecx, edx\nsar eax, 1\njnz short loc_1520\ntest r9d, r9d\njle short loc_1543\nloc_1530:\nmov edx, r9d\nxor eax, eax\nnop dword ptr [rax]\nloc_1538:\nmov esi, edx\nand esi, 1\nadd eax, esi\nsar edx, 1\njnz short loc_1538\nloc_1543:\ncmp ecx, eax\njg short loc_1570\nsetz al\nloc_154A:\ncmp r8d, r9d\njle short loc_1553\ntest al, al\njnz short loc_1570\nloc_1553:\nadd rdi, 1\ncmp ebx, edi\njg short loc_1508\nadd r11, 1\ncmp rbp, r11\njnz short loc_1500\nloc_1564:\npop rbx\npop rbp\nretn\nloc_1570:\nmov [r10+r11*4-4], r9d\nmov [r10+rdi*4], r8d\njmp short loc_1553\nloc_1580:\nxor ecx, ecx\nmov eax, 1\ntest r9d, r9d\njg short loc_1530\njmp short loc_154A\nlocret_158E:\nretn", + "ida_strip_pseudo": "void __fastcall sub_14E0(__int64 a1, int a2)\n{\n __int64 v3; // r11\n __int64 v4; // rdi\n int v5; // r8d\n int v6; // r9d\n int v7; // eax\n int v8; // ecx\n int v9; // edx\n bool v10; // al\n\n if ( a2 > 0 )\n {\n v3 = 1LL;\n if ( a2 != 1 )\n {\n do\n {\n v4 = v3;\n do\n {\n v5 = *(_DWORD *)(a1 + 4 * v3 - 4);\n v6 = *(_DWORD *)(a1 + 4 * v4);\n if ( v5 > 0 )\n {\n v7 = *(_DWORD *)(a1 + 4 * v3 - 4);\n v8 = 0;\n do\n {\n v8 += v7 & 1;\n v7 >>= 1;\n }\n while ( v7 );\n if ( v6 > 0 )\n {\nLABEL_8:\n v9 = *(_DWORD *)(a1 + 4 * v4);\n v7 = 0;\n do\n {\n v7 += v9 & 1;\n v9 >>= 1;\n }\n while ( v9 );\n }\n if ( v8 > v7 )\n goto LABEL_17;\n v10 = v8 == v7;\n goto LABEL_12;\n }\n v8 = 0;\n v10 = 1;\n if ( v6 > 0 )\n goto LABEL_8;\nLABEL_12:\n if ( v5 > v6 && v10 )\n {\nLABEL_17:\n *(_DWORD *)(a1 + 4 * v3 - 4) = v6;\n *(_DWORD *)(a1 + 4 * v4) = v5;\n }\n ++v4;\n }\n while ( a2 > (int)v4 );\n ++v3;\n }\n while ( a2 != v3 );\n }\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_14E0(long long a1, int a2) {\n long long v3;\n long long v4;\n int v5;\n int v6;\n int v7;\n int v8;\n int v9;\n bool v10;\n if (a2 > 0) {\n v3 = 1LL;\n if (a2 != 1) {\n do {\n v4 = v3;\n do {\n v5 = *(uint32_t *)(a1 + 4 * v3 - 4);\n v6 = *(uint32_t *)(a1 + 4 * v4);\n if (v5 > 0) {\n v7 = *(uint32_t *)(a1 + 4 * v3 - 4);\n v8 = 0;\n do {\n v8 += v7 & 1;\n v7 >>= 1;\n } while (v7);\n if (v6 > 0) {\n LABEL_8:\n v9 = *(uint32_t *)(a1 + 4 * v4);\n v7 = 0;\n do {\n v7 += v9 & 1;\n v9 >>= 1;\n } while (v9);\n }\n if (v8 > v7) goto LABEL_17;\n v10 = v8 == v7;\n goto LABEL_12;\n }\n v8 = 0;\n v10 = 1;\n if (v6 > 0) goto LABEL_8;\n LABEL_12:\n if (v5 > v6 && v10) {\n LABEL_17:\n *(uint32_t *)(a1 + 4 * v3 - 4) = v6;\n *(uint32_t *)(a1 + 4 * v4) = v5;\n }\n ++v4;\n } while (a2 > (int)v4);\n ++v3;\n } while (a2 != v3);\n }\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2) {\n long long v3;\n long long v4;\n int v5;\n int v6;\n int v7;\n int v8;\n int v9;\n bool v10;\n if (a2 > 0) {\n v3 = 1LL;\n if (a2 != 1) {\n do {\n v4 = v3;\n do {\n v5 = *(uint32_t *)(a1 + 4 * v3 - 4);\n v6 = *(uint32_t *)(a1 + 4 * v4);\n if (v5 > 0) {\n v7 = *(uint32_t *)(a1 + 4 * v3 - 4);\n v8 = 0;\n do {\n v8 += v7 & 1;\n v7 >>= 1;\n } while (v7);\n if (v6 > 0) {\n LABEL_8:\n v9 = *(uint32_t *)(a1 + 4 * v4);\n v7 = 0;\n do {\n v7 += v9 & 1;\n v9 >>= 1;\n } while (v9);\n }\n if (v8 > v7) goto LABEL_17;\n v10 = v8 == v7;\n goto LABEL_12;\n }\n v8 = 0;\n v10 = 1;\n if (v6 > 0) goto LABEL_8;\n LABEL_12:\n if (v5 > v6 && v10) {\n LABEL_17:\n *(uint32_t *)(a1 + 4 * v3 - 4) = v6;\n *(uint32_t *)(a1 + 4 * v4) = v5;\n }\n ++v4;\n } while (a2 > (int)v4);\n ++v3;\n } while (a2 != v3);\n }\n }\n}" + }, + { + "index": "HumanEval-C-117", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n#include \n", + "func": "char **func0(const char *s, int n, int *returnSize) {\n const char *vowels = \"aeiouAEIOU\";\n char **out = NULL;\n int numc = 0, word_count = 0, begin = 0;\n size_t length = strlen(s);\n char *current = (char *)malloc(length + 1);\n for (int i = 0; i <= length; i++) {\n if (isspace(s[i]) || s[i] == '\\0') {\n if (numc == n) {\n current[i - begin] = '\\0';\n out = (char **)realloc(out, sizeof(char *) * (word_count + 1));\n out[word_count] = (char *)malloc(strlen(current) + 1);\n strcpy(out[word_count], current);\n word_count++;\n }\n begin = i + 1;\n numc = 0;\n } else {\n current[i - begin] = s[i];\n if (strchr(vowels, s[i]) == NULL && isalpha((unsigned char)s[i])) {\n numc++;\n }\n }\n }\n free(current);\n *returnSize = word_count;\n return out;\n}", + "test": "#include \n#include \n#include \n#include \n\nint issame(char **a, int aSize, char **b, int bSize) {\n if (aSize != bSize) return 0;\n for (int i = 0; i < aSize; i++) {\n if (strcmp(a[i], b[i]) != 0) return 0;\n }\n return 1;\n}\n\nvoid free_words(char **words, int count) {\n for (int i = 0; i < count; i++) {\n free(words[i]);\n }\n free(words);\n}\n\nint main() {\n int size;\n char **words;\n \n words = func0(\"Mary had a little lamb\", 4, &size);\n char *expected1[] = {\"little\"};\n assert(issame(words, size, expected1, 1));\n free_words(words, size);\n\n words = func0(\"Mary had a little lamb\", 3, &size);\n char *expected2[] = {\"Mary\", \"lamb\"};\n assert(issame(words, size, expected2, 2));\n free_words(words, size);\n\n words = func0(\"simple white space\", 2, &size);\n assert(size == 0);\n free_words(words, size);\n\n words = func0(\"Hello world\", 4, &size);\n char *expected3[] = {\"world\"};\n assert(issame(words, size, expected3, 1));\n free_words(words, size);\n\n words = func0(\"Uncle sam\", 3, &size);\n char *expected4[] = {\"Uncle\"};\n assert(issame(words, size, expected4, 1));\n free_words(words, size);\n\n words = func0(\"\", 4, &size);\n assert(size == 0);\n free_words(words, size);\n\n words = func0(\"a b c d e f\", 1, &size);\n char *expected5[] = {\"b\", \"c\", \"d\", \"f\"};\n assert(issame(words, size, expected5, 4));\n free_words(words, size);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 58h\nmov [rbp+s], rdi\nmov [rbp+var_4C], esi\nmov [rbp+var_58], rdx\nlea rax, aAeiouaeiou; \"aeiouAEIOU\"\nmov [rbp+var_28], rax\nmov [rbp+ptr], 0\nmov [rbp+var_40], 0\nmov [rbp+var_3C], 0\nmov [rbp+var_38], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_20], rax\nmov rax, [rbp+var_20]\nadd rax, 1\nmov rdi, rax; size\ncall _malloc\nmov [rbp+src], rax\nmov [rbp+var_34], 0\njmp loc_1452\nloc_12D9:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_34]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 2000h\ntest eax, eax\njnz short loc_1322\nmov eax, [rbp+var_34]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_13D1\nloc_1322:\nmov eax, [rbp+var_40]\ncmp eax, [rbp+var_4C]\njnz loc_13BF\nmov eax, [rbp+var_34]\nsub eax, [rbp+var_38]\nmovsxd rdx, eax\nmov rax, [rbp+src]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov eax, [rbp+var_3C]\nadd eax, 1\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nmov rsi, rdx; size\nmov rdi, rax; ptr\ncall _realloc\nmov [rbp+ptr], rax\nmov rax, [rbp+src]\nmov rdi, rax; s\ncall _strlen\nadd rax, 1\nmov edx, [rbp+var_3C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+ptr]\nlea rbx, [rcx+rdx]\nmov rdi, rax; size\ncall _malloc\nmov [rbx], rax\nmov eax, [rbp+var_3C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rax, [rax]\nmov rdx, [rbp+src]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\nadd [rbp+var_3C], 1\nloc_13BF:\nmov eax, [rbp+var_34]\nadd eax, 1\nmov [rbp+var_38], eax\nmov [rbp+var_40], 0\njmp short loc_144E\nloc_13D1:\nmov eax, [rbp+var_34]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_34]\nsub eax, [rbp+var_38]\nmovsxd rdx, eax\nmov rax, [rbp+src]\nadd rdx, rax\nmovzx eax, byte ptr [rcx]\nmov [rdx], al\nmov eax, [rbp+var_34]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx edx, al\nmov rax, [rbp+var_28]\nmov esi, edx; c\nmov rdi, rax; s\ncall _strchr\ntest rax, rax\njnz short loc_144E\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_34]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovzx edx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 400h\ntest eax, eax\njz short loc_144E\nadd [rbp+var_40], 1\nloc_144E:\nadd [rbp+var_34], 1\nloc_1452:\nmov eax, [rbp+var_34]\ncdqe\ncmp [rbp+var_20], rax\njnb loc_12D9\nmov rax, [rbp+src]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_58]\nmov edx, [rbp+var_3C]\nmov [rax], edx\nmov rax, [rbp+ptr]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "void *__fastcall func0(const char *a1, int a2, _DWORD *a3)\n{\n size_t v3; // rax\n int v6; // [rsp+20h] [rbp-40h]\n int v7; // [rsp+24h] [rbp-3Ch]\n int v8; // [rsp+28h] [rbp-38h]\n int i; // [rsp+2Ch] [rbp-34h]\n void *ptr; // [rsp+30h] [rbp-30h]\n size_t v11; // [rsp+40h] [rbp-20h]\n char *src; // [rsp+48h] [rbp-18h]\n\n ptr = 0LL;\n v6 = 0;\n v7 = 0;\n v8 = 0;\n v11 = strlen(a1);\n src = (char *)malloc(v11 + 1);\n for ( i = 0; v11 >= i; ++i )\n {\n if ( ((*__ctype_b_loc())[a1[i]] & 0x2000) == 0 && a1[i] )\n {\n src[i - v8] = a1[i];\n if ( !strchr(\"aeiouAEIOU\", a1[i]) && ((*__ctype_b_loc())[(unsigned __int8)a1[i]] & 0x400) != 0 )\n ++v6;\n }\n else\n {\n if ( v6 == a2 )\n {\n src[i - v8] = 0;\n ptr = realloc(ptr, 8LL * (v7 + 1));\n v3 = strlen(src);\n *((_QWORD *)ptr + v7) = malloc(v3 + 1);\n strcpy(*((char **)ptr + v7++), src);\n }\n v8 = i + 1;\n v6 = 0;\n }\n }\n free(src);\n *a3 = v7;\n return ptr;\n}", + "ida_strip_asm": "sub_1269:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 58h\nmov [rbp+s], rdi\nmov [rbp+var_4C], esi\nmov [rbp+var_58], rdx\nlea rax, aAeiouaeiou; \"aeiouAEIOU\"\nmov [rbp+var_28], rax\nmov [rbp+ptr], 0\nmov [rbp+var_40], 0\nmov [rbp+var_3C], 0\nmov [rbp+var_38], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_20], rax\nmov rax, [rbp+var_20]\nadd rax, 1\nmov rdi, rax; size\ncall _malloc\nmov [rbp+src], rax\nmov [rbp+var_34], 0\njmp loc_1452\nloc_12D9:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_34]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 2000h\ntest eax, eax\njnz short loc_1322\nmov eax, [rbp+var_34]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_13D1\nloc_1322:\nmov eax, [rbp+var_40]\ncmp eax, [rbp+var_4C]\njnz loc_13BF\nmov eax, [rbp+var_34]\nsub eax, [rbp+var_38]\nmovsxd rdx, eax\nmov rax, [rbp+src]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov eax, [rbp+var_3C]\nadd eax, 1\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nmov rsi, rdx; size\nmov rdi, rax; ptr\ncall _realloc\nmov [rbp+ptr], rax\nmov rax, [rbp+src]\nmov rdi, rax; s\ncall _strlen\nadd rax, 1\nmov edx, [rbp+var_3C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+ptr]\nlea rbx, [rcx+rdx]\nmov rdi, rax; size\ncall _malloc\nmov [rbx], rax\nmov eax, [rbp+var_3C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rax, [rax]\nmov rdx, [rbp+src]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\nadd [rbp+var_3C], 1\nloc_13BF:\nmov eax, [rbp+var_34]\nadd eax, 1\nmov [rbp+var_38], eax\nmov [rbp+var_40], 0\njmp short loc_144E\nloc_13D1:\nmov eax, [rbp+var_34]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_34]\nsub eax, [rbp+var_38]\nmovsxd rdx, eax\nmov rax, [rbp+src]\nadd rdx, rax\nmovzx eax, byte ptr [rcx]\nmov [rdx], al\nmov eax, [rbp+var_34]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx edx, al\nmov rax, [rbp+var_28]\nmov esi, edx; c\nmov rdi, rax; s\ncall _strchr\ntest rax, rax\njnz short loc_144E\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_34]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovzx edx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 400h\ntest eax, eax\njz short loc_144E\nadd [rbp+var_40], 1\nloc_144E:\nadd [rbp+var_34], 1\nloc_1452:\nmov eax, [rbp+var_34]\ncdqe\ncmp [rbp+var_20], rax\njnb loc_12D9\nmov rax, [rbp+src]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_58]\nmov edx, [rbp+var_3C]\nmov [rax], edx\nmov rax, [rbp+ptr]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "void *__fastcall sub_1269(const char *a1, int a2, _DWORD *a3)\n{\n size_t v3; // rax\n int v6; // [rsp+20h] [rbp-40h]\n int v7; // [rsp+24h] [rbp-3Ch]\n int v8; // [rsp+28h] [rbp-38h]\n int i; // [rsp+2Ch] [rbp-34h]\n void *ptr; // [rsp+30h] [rbp-30h]\n size_t v11; // [rsp+40h] [rbp-20h]\n char *src; // [rsp+48h] [rbp-18h]\n\n ptr = 0LL;\n v6 = 0;\n v7 = 0;\n v8 = 0;\n v11 = strlen(a1);\n src = (char *)malloc(v11 + 1);\n for ( i = 0; v11 >= i; ++i )\n {\n if ( ((*__ctype_b_loc())[a1[i]] & 0x2000) == 0 && a1[i] )\n {\n src[i - v8] = a1[i];\n if ( !strchr(\"aeiouAEIOU\", a1[i]) && ((*__ctype_b_loc())[(unsigned __int8)a1[i]] & 0x400) != 0 )\n ++v6;\n }\n else\n {\n if ( v6 == a2 )\n {\n src[i - v8] = 0;\n ptr = realloc(ptr, 8LL * (v7 + 1));\n v3 = strlen(src);\n *((_QWORD *)ptr + v7) = malloc(v3 + 1);\n strcpy(*((char **)ptr + v7++), src);\n }\n v8 = i + 1;\n v6 = 0;\n }\n }\n free(src);\n *a3 = v7;\n return ptr;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1269(const char *a1, int a2, uint32_t *a3) {\n unsigned int v3;\n int v6;\n int v7;\n int v8;\n int i;\n void *ptr;\n unsigned int v11;\n char *src;\n ptr = 0LL;\n v6 = 0;\n v7 = 0;\n v8 = 0;\n v11 = strlen(a1);\n src = (char *)malloc(v11 + 1);\n for (i = 0; v11 >= i; ++i) {\n if (((*__ctype_b_loc())[a1[i]] & 8192) == 0 && a1[i]) {\n src[i - v8] = a1[i];\n if (!strchr(\"aeiouAEIOU\", a1[i]) &&\n ((*__ctype_b_loc())[(unsigned char)a1[i]] & 1024) != 0)\n ++v6;\n } else {\n if (v6 == a2) {\n src[i - v8] = 0;\n ptr = realloc(ptr, 8LL * (v7 + 1));\n v3 = strlen(src);\n *((uint64_t *)ptr + v7) = malloc(v3 + 1);\n strcpy(*((char **)ptr + v7++), src);\n }\n v8 = i + 1;\n v6 = 0;\n }\n }\n free(src);\n *a3 = v7;\n return ptr;\n}", + "ida_pseudo_norm": "void *func0(const char *a1, int a2, uint32_t *a3) {\n unsigned int v3;\n int v6;\n int v7;\n int v8;\n int i;\n void *ptr;\n unsigned int v11;\n char *src;\n ptr = 0LL;\n v6 = 0;\n v7 = 0;\n v8 = 0;\n v11 = strlen(a1);\n src = (char *)malloc(v11 + 1);\n for (i = 0; v11 >= i; ++i) {\n if (((*__ctype_b_loc())[a1[i]] & 8192) == 0 && a1[i]) {\n src[i - v8] = a1[i];\n if (!strchr(\"aeiouAEIOU\", a1[i]) &&\n ((*__ctype_b_loc())[(unsigned char)a1[i]] & 1024) != 0)\n ++v6;\n } else {\n if (v6 == a2) {\n src[i - v8] = 0;\n ptr = realloc(ptr, 8LL * (v7 + 1));\n v3 = strlen(src);\n *((uint64_t *)ptr + v7) = malloc(v3 + 1);\n strcpy(*((char **)ptr + v7++), src);\n }\n v8 = i + 1;\n v6 = 0;\n }\n }\n free(src);\n *a3 = v7;\n return ptr;\n}" + }, + { + "index": "HumanEval-C-117", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n#include \n", + "func": "char **func0(const char *s, int n, int *returnSize) {\n const char *vowels = \"aeiouAEIOU\";\n char **out = NULL;\n int numc = 0, word_count = 0, begin = 0;\n size_t length = strlen(s);\n char *current = (char *)malloc(length + 1);\n for (int i = 0; i <= length; i++) {\n if (isspace(s[i]) || s[i] == '\\0') {\n if (numc == n) {\n current[i - begin] = '\\0';\n out = (char **)realloc(out, sizeof(char *) * (word_count + 1));\n out[word_count] = (char *)malloc(strlen(current) + 1);\n strcpy(out[word_count], current);\n word_count++;\n }\n begin = i + 1;\n numc = 0;\n } else {\n current[i - begin] = s[i];\n if (strchr(vowels, s[i]) == NULL && isalpha((unsigned char)s[i])) {\n numc++;\n }\n }\n }\n free(current);\n *returnSize = word_count;\n return out;\n}", + "test": "#include \n#include \n#include \n#include \n\nint issame(char **a, int aSize, char **b, int bSize) {\n if (aSize != bSize) return 0;\n for (int i = 0; i < aSize; i++) {\n if (strcmp(a[i], b[i]) != 0) return 0;\n }\n return 1;\n}\n\nvoid free_words(char **words, int count) {\n for (int i = 0; i < count; i++) {\n free(words[i]);\n }\n free(words);\n}\n\nint main() {\n int size;\n char **words;\n \n words = func0(\"Mary had a little lamb\", 4, &size);\n char *expected1[] = {\"little\"};\n assert(issame(words, size, expected1, 1));\n free_words(words, size);\n\n words = func0(\"Mary had a little lamb\", 3, &size);\n char *expected2[] = {\"Mary\", \"lamb\"};\n assert(issame(words, size, expected2, 2));\n free_words(words, size);\n\n words = func0(\"simple white space\", 2, &size);\n assert(size == 0);\n free_words(words, size);\n\n words = func0(\"Hello world\", 4, &size);\n char *expected3[] = {\"world\"};\n assert(issame(words, size, expected3, 1));\n free_words(words, size);\n\n words = func0(\"Uncle sam\", 3, &size);\n char *expected4[] = {\"Uncle\"};\n assert(issame(words, size, expected4, 1));\n free_words(words, size);\n\n words = func0(\"\", 4, &size);\n assert(size == 0);\n free_words(words, size);\n\n words = func0(\"a b c d e f\", 1, &size);\n char *expected5[] = {\"b\", \"c\", \"d\", \"f\"};\n assert(issame(words, size, expected5, 4));\n free_words(words, size);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 38h\nmov r15, rdi\nmov [rsp+68h+var_58], esi\nmov rbp, rdx\ncall _strlen\nmov r14, rax\nlea rdi, [rax+1]; size\ncall _malloc\nmov [rsp+68h+s], rax\ncall ___ctype_b_loc\nmov [rsp+68h+var_60], rax\nmov ebx, 0\nmov r13d, 0\nmov [rsp+68h+var_54], 0\nmov [rsp+68h+var_64], 0\nmov [rsp+68h+ptr], 0\nmov [rsp+68h+var_40], rbp\njmp short loc_12FA\nloc_12D0:\nmov ecx, [rsp+68h+var_64]\ncmp [rsp+68h+var_58], ecx\njz short loc_1358\nloc_12DA:\nmov r13d, [rsp+68h+var_68]\nadd r13d, 1\nmov [rsp+68h+var_64], 0\nloc_12EA:\nlea rax, [rbx+1]\ncmp rbx, r14\njz loc_13BB\nmov rbx, rax\nloc_12FA:\nmov [rsp+68h+var_68], ebx\nmov eax, ebx\nmov rcx, [rsp+68h+var_60]\nmov r12, [rcx]\nmovzx ebp, byte ptr [r15+rbx]\nmovsx rdx, bpl\ntest byte ptr [r12+rdx*2+1], 20h\njnz short loc_12D0\ntest bpl, bpl\njz short loc_12D0\nsub eax, r13d\ncdqe\nmov rdi, [rsp+68h+s]\nmov [rdi+rax], bpl\nmovsx esi, bpl; c\nlea rdi, s; \"aeiouAEIOU\"\ncall _strchr\ntest rax, rax\njnz short loc_12EA\nmovzx ebp, bpl\nmovzx eax, word ptr [r12+rbp*2]\nand ax, 400h\ncmp ax, 1\nsbb [rsp+68h+var_64], 0FFFFFFFFh\njmp short loc_12EA\nloc_1358:\nsub eax, r13d\ncdqe\nmov r13, [rsp+68h+s]\nmov byte ptr [r13+rax+0], 0\nadd [rsp+68h+var_54], 1\nmov eax, [rsp+68h+var_54]\nmovsxd r12, eax\nshl r12, 3\nmov rsi, r12; size\nmov rdi, [rsp+68h+ptr]; ptr\ncall _realloc\nmov [rsp+68h+ptr], rax\nmov rdi, r13; s\ncall _strlen\nlea rbp, [rax+1]\nmov rdi, rbp; size\ncall _malloc\nmov rdi, rax\nmov rax, [rsp+68h+ptr]\nmov [rax+r12-8], rdi\nmov rdx, rbp\nmov rsi, r13\ncall ___strcpy_chk\njmp loc_12DA\nloc_13BB:\nmov rbp, [rsp+68h+var_40]\nmov rdi, [rsp+68h+s]; ptr\ncall _free\nmov eax, [rsp+68h+var_54]\nmov [rbp+0], eax\nmov rax, [rsp+68h+ptr]\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "void *__fastcall func0(const char *a1, int a2, _DWORD *a3)\n{\n size_t v4; // r14\n __int64 v5; // rbx\n int v6; // r13d\n const unsigned __int16 *v7; // r12\n char v8; // bp\n size_t v9; // rbp\n void *v10; // rax\n int v12; // [rsp+4h] [rbp-64h]\n const unsigned __int16 **v13; // [rsp+8h] [rbp-60h]\n int v14; // [rsp+14h] [rbp-54h]\n void *ptr; // [rsp+18h] [rbp-50h]\n char *s; // [rsp+20h] [rbp-48h]\n _DWORD *v17; // [rsp+28h] [rbp-40h]\n\n v4 = strlen(a1);\n s = (char *)malloc(v4 + 1);\n v13 = __ctype_b_loc();\n v5 = 0LL;\n v6 = 0;\n v14 = 0;\n v12 = 0;\n ptr = 0LL;\n v17 = a3;\n while ( 1 )\n {\n v7 = *v13;\n v8 = a1[v5];\n if ( ((*v13)[v8] & 0x2000) != 0 || !v8 )\n {\n if ( a2 == v12 )\n {\n s[(int)v5 - v6] = 0;\n ptr = realloc(ptr, 8LL * ++v14);\n v9 = strlen(s) + 1;\n v10 = malloc(v9);\n *((_QWORD *)ptr + v14 - 1) = v10;\n __strcpy_chk(v10, s, v9);\n }\n v6 = v5 + 1;\n v12 = 0;\n }\n else\n {\n s[(int)v5 - v6] = v8;\n if ( !strchr(\"aeiouAEIOU\", v8) )\n v12 -= ((v7[(unsigned __int8)v8] & 0x400) == 0) - 1;\n }\n if ( v5 == v4 )\n break;\n ++v5;\n }\n free(s);\n *v17 = v14;\n return ptr;\n}", + "ida_strip_asm": "sub_1269:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 38h\nmov r15, rdi\nmov [rsp+68h+var_58], esi\nmov rbp, rdx\ncall _strlen\nmov r14, rax\nlea rdi, [rax+1]; size\ncall _malloc\nmov [rsp+68h+s], rax\ncall ___ctype_b_loc\nmov [rsp+68h+var_60], rax\nmov ebx, 0\nmov r13d, 0\nmov [rsp+68h+var_54], 0\nmov [rsp+68h+var_64], 0\nmov [rsp+68h+ptr], 0\nmov [rsp+68h+var_40], rbp\njmp short loc_12FA\nloc_12D0:\nmov ecx, [rsp+68h+var_64]\ncmp [rsp+68h+var_58], ecx\njz short loc_1358\nloc_12DA:\nmov r13d, [rsp+68h+var_68]\nadd r13d, 1\nmov [rsp+68h+var_64], 0\nloc_12EA:\nlea rax, [rbx+1]\ncmp rbx, r14\njz loc_13BB\nmov rbx, rax\nloc_12FA:\nmov [rsp+68h+var_68], ebx\nmov eax, ebx\nmov rcx, [rsp+68h+var_60]\nmov r12, [rcx]\nmovzx ebp, byte ptr [r15+rbx]\nmovsx rdx, bpl\ntest byte ptr [r12+rdx*2+1], 20h\njnz short loc_12D0\ntest bpl, bpl\njz short loc_12D0\nsub eax, r13d\ncdqe\nmov rdi, [rsp+68h+s]\nmov [rdi+rax], bpl\nmovsx esi, bpl; c\nlea rdi, s; \"aeiouAEIOU\"\ncall _strchr\ntest rax, rax\njnz short loc_12EA\nmovzx ebp, bpl\nmovzx eax, word ptr [r12+rbp*2]\nand ax, 400h\ncmp ax, 1\nsbb [rsp+68h+var_64], 0FFFFFFFFh\njmp short loc_12EA\nloc_1358:\nsub eax, r13d\ncdqe\nmov r13, [rsp+68h+s]\nmov byte ptr [r13+rax+0], 0\nadd [rsp+68h+var_54], 1\nmov eax, [rsp+68h+var_54]\nmovsxd r12, eax\nshl r12, 3\nmov rsi, r12; size\nmov rdi, [rsp+68h+ptr]; ptr\ncall _realloc\nmov [rsp+68h+ptr], rax\nmov rdi, r13; s\ncall _strlen\nlea rbp, [rax+1]\nmov rdi, rbp; size\ncall _malloc\nmov rdi, rax\nmov rax, [rsp+68h+ptr]\nmov [rax+r12-8], rdi\nmov rdx, rbp\nmov rsi, r13\ncall ___strcpy_chk\njmp loc_12DA\nloc_13BB:\nmov rbp, [rsp+68h+var_40]\nmov rdi, [rsp+68h+s]; ptr\ncall _free\nmov eax, [rsp+68h+var_54]\nmov [rbp+0], eax\nmov rax, [rsp+68h+ptr]\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "void *__fastcall sub_1269(const char *a1, int a2, _DWORD *a3)\n{\n size_t v4; // r14\n __int64 v5; // rbx\n int v6; // r13d\n const unsigned __int16 *v7; // r12\n char v8; // bp\n size_t v9; // rbp\n void *v10; // rax\n int v12; // [rsp+4h] [rbp-64h]\n const unsigned __int16 **v13; // [rsp+8h] [rbp-60h]\n int v14; // [rsp+14h] [rbp-54h]\n void *ptr; // [rsp+18h] [rbp-50h]\n char *s; // [rsp+20h] [rbp-48h]\n _DWORD *v17; // [rsp+28h] [rbp-40h]\n\n v4 = strlen(a1);\n s = (char *)malloc(v4 + 1);\n v13 = __ctype_b_loc();\n v5 = 0LL;\n v6 = 0;\n v14 = 0;\n v12 = 0;\n ptr = 0LL;\n v17 = a3;\n while ( 1 )\n {\n v7 = *v13;\n v8 = a1[v5];\n if ( ((*v13)[v8] & 0x2000) != 0 || !v8 )\n {\n if ( a2 == v12 )\n {\n s[(int)v5 - v6] = 0;\n ptr = realloc(ptr, 8LL * ++v14);\n v9 = strlen(s) + 1;\n v10 = malloc(v9);\n *((_QWORD *)ptr + v14 - 1) = v10;\n __strcpy_chk(v10, s, v9);\n }\n v6 = v5 + 1;\n v12 = 0;\n }\n else\n {\n s[(int)v5 - v6] = v8;\n if ( !strchr(\"aeiouAEIOU\", v8) )\n v12 -= ((v7[(unsigned __int8)v8] & 0x400) == 0) - 1;\n }\n if ( v5 == v4 )\n break;\n ++v5;\n }\n free(s);\n *v17 = v14;\n return ptr;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1269(const char *a1, int a2, uint32_t *a3) {\n unsigned int v4;\n long long v5;\n int v6;\n const unsigned short *v7;\n char v8;\n unsigned int v9;\n void *v10;\n int v12;\n const unsigned short **v13;\n int v14;\n void *ptr;\n char *s;\n uint32_t *v17;\n v4 = strlen(a1);\n s = (char *)malloc(v4 + 1);\n v13 = __ctype_b_loc();\n v5 = 0LL;\n v6 = 0;\n v14 = 0;\n v12 = 0;\n ptr = 0LL;\n v17 = a3;\n while (1) {\n v7 = *v13;\n v8 = a1[v5];\n if (((*v13)[v8] & 8192) != 0 || !v8) {\n if (a2 == v12) {\n s[(int)v5 - v6] = 0;\n ptr = realloc(ptr, 8LL * ++v14);\n v9 = strlen(s) + 1;\n v10 = malloc(v9);\n *((uint64_t *)ptr + v14 - 1) = v10;\n __strcpy_chk(v10, s, v9);\n }\n v6 = v5 + 1;\n v12 = 0;\n } else {\n s[(int)v5 - v6] = v8;\n if (!strchr(\"aeiouAEIOU\", v8))\n v12 -= ((v7[(unsigned char)v8] & 1024) == 0) - 1;\n }\n if (v5 == v4) break;\n ++v5;\n }\n free(s);\n *v17 = v14;\n return ptr;\n}", + "ida_pseudo_norm": "void *func0(const char *a1, int a2, uint32_t *a3) {\n unsigned int v4;\n long long v5;\n int v6;\n const unsigned short *v7;\n char v8;\n unsigned int v9;\n void *v10;\n int v12;\n const unsigned short **v13;\n int v14;\n void *ptr;\n char *s;\n uint32_t *v17;\n v4 = strlen(a1);\n s = (char *)malloc(v4 + 1);\n v13 = __ctype_b_loc();\n v5 = 0LL;\n v6 = 0;\n v14 = 0;\n v12 = 0;\n ptr = 0LL;\n v17 = a3;\n while (1) {\n v7 = *v13;\n v8 = a1[v5];\n if (((*v13)[v8] & 8192) != 0 || !v8) {\n if (a2 == v12) {\n s[(int)v5 - v6] = 0;\n ptr = realloc(ptr, 8LL * ++v14);\n v9 = strlen(s) + 1;\n v10 = malloc(v9);\n *((uint64_t *)ptr + v14 - 1) = v10;\n __strcpy_chk(v10, s, v9);\n }\n v6 = v5 + 1;\n v12 = 0;\n } else {\n s[(int)v5 - v6] = v8;\n if (!strchr(\"aeiouAEIOU\", v8))\n v12 -= ((v7[(unsigned char)v8] & 1024) == 0) - 1;\n }\n if (v5 == v4) break;\n ++v5;\n }\n free(s);\n *v17 = v14;\n return ptr;\n}" + }, + { + "index": "HumanEval-C-117", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n#include \n", + "func": "char **func0(const char *s, int n, int *returnSize) {\n const char *vowels = \"aeiouAEIOU\";\n char **out = NULL;\n int numc = 0, word_count = 0, begin = 0;\n size_t length = strlen(s);\n char *current = (char *)malloc(length + 1);\n for (int i = 0; i <= length; i++) {\n if (isspace(s[i]) || s[i] == '\\0') {\n if (numc == n) {\n current[i - begin] = '\\0';\n out = (char **)realloc(out, sizeof(char *) * (word_count + 1));\n out[word_count] = (char *)malloc(strlen(current) + 1);\n strcpy(out[word_count], current);\n word_count++;\n }\n begin = i + 1;\n numc = 0;\n } else {\n current[i - begin] = s[i];\n if (strchr(vowels, s[i]) == NULL && isalpha((unsigned char)s[i])) {\n numc++;\n }\n }\n }\n free(current);\n *returnSize = word_count;\n return out;\n}", + "test": "#include \n#include \n#include \n#include \n\nint issame(char **a, int aSize, char **b, int bSize) {\n if (aSize != bSize) return 0;\n for (int i = 0; i < aSize; i++) {\n if (strcmp(a[i], b[i]) != 0) return 0;\n }\n return 1;\n}\n\nvoid free_words(char **words, int count) {\n for (int i = 0; i < count; i++) {\n free(words[i]);\n }\n free(words);\n}\n\nint main() {\n int size;\n char **words;\n \n words = func0(\"Mary had a little lamb\", 4, &size);\n char *expected1[] = {\"little\"};\n assert(issame(words, size, expected1, 1));\n free_words(words, size);\n\n words = func0(\"Mary had a little lamb\", 3, &size);\n char *expected2[] = {\"Mary\", \"lamb\"};\n assert(issame(words, size, expected2, 2));\n free_words(words, size);\n\n words = func0(\"simple white space\", 2, &size);\n assert(size == 0);\n free_words(words, size);\n\n words = func0(\"Hello world\", 4, &size);\n char *expected3[] = {\"world\"};\n assert(issame(words, size, expected3, 1));\n free_words(words, size);\n\n words = func0(\"Uncle sam\", 3, &size);\n char *expected4[] = {\"Uncle\"};\n assert(issame(words, size, expected4, 1));\n free_words(words, size);\n\n words = func0(\"\", 4, &size);\n assert(size == 0);\n free_words(words, size);\n\n words = func0(\"a b c d e f\", 1, &size);\n char *expected5[] = {\"b\", \"c\", \"d\", \"f\"};\n assert(issame(words, size, expected5, 4));\n free_words(words, size);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\nxor r15d, r15d\npush r14\nmov r14, rdi\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 38h\nmov [rsp+68h+var_5C], esi\nmov [rsp+68h+var_40], rdx\ncall _strlen\nlea rdi, [rax+1]; size\nmov rbx, rax\ncall _malloc\nlea r13d, [rbx+1]\nxor ebx, ebx\nmov rbp, rax\ncall ___ctype_b_loc\nmov [rsp+68h+var_48], 0\nxor r11d, r11d\nmov [rsp+68h+ptr], 0\nmov r12, [rax]\njmp short loc_16BA\nloc_16A0:\ncmp [rsp+68h+var_5C], r15d\njz loc_1750\nloc_16AB:\nmov r11d, ebx\nxor r15d, r15d\nloc_16B1:\nadd r14, 1\ncmp r13d, ebx\njz short loc_171F\nloc_16BA:\nmovsx rsi, byte ptr [r14]\nmov eax, ebx\nadd ebx, 1\nmov rdx, rsi\ntest byte ptr [r12+rsi*2+1], 20h\njnz short loc_16A0\ntest sil, sil\njz short loc_16A0\nsub eax, r11d\nlea rdi, s; \"aeiouAEIOU\"\nmov [rsp+68h+var_44], r11d\ncdqe\nmov byte ptr [rsp+68h+var_50], dl\nmov [rbp+rax+0], sil\nmovsx esi, sil; c\ncall _strchr\nmovzx edx, byte ptr [rsp+68h+var_50]\nmov r11d, [rsp+68h+var_44]\ntest rax, rax\njnz short loc_16B1\nmovzx eax, word ptr [r12+rdx*2]\nand ax, 400h\ncmp ax, 1\nsbb r15d, 0FFFFFFFFh\nadd r14, 1\ncmp r13d, ebx\njnz short loc_16BA\nloc_171F:\nmov rdi, rbp; ptr\ncall _free\nmov rax, [rsp+68h+var_40]\nmov edi, [rsp+68h+var_48]\nmov [rax], edi\nmov rax, [rsp+68h+ptr]\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1750:\nsub eax, r11d\nadd [rsp+68h+var_48], 1\nmovsxd rcx, [rsp+68h+var_48]\ncdqe\nmov rdi, [rsp+68h+ptr]; ptr\nmov byte ptr [rbp+rax+0], 0\nshl rcx, 3\nmov rsi, rcx; size\nmov [rsp+68h+var_50], rcx\ncall _realloc\nmov rdi, rbp; s\nmov [rsp+68h+ptr], rax\ncall _strlen\nlea r15, [rax+1]\nmov rdi, r15; size\ncall _malloc\nmov rcx, [rsp+68h+var_50]\nmov rdx, r15\nmov rsi, rbp\nmov rdi, rax\nmov rax, [rsp+68h+ptr]\nmov [rax+rcx-8], rdi\nmov rcx, r15\ncall ___memcpy_chk\njmp loc_16AB", + "ida_pseudo": "char *__fastcall func0(const char *a1, int a2, _DWORD *a3)\n{\n int v3; // r15d\n const char *v4; // r14\n size_t v5; // rax\n int v6; // r13d\n int v7; // ebx\n char *v8; // rbp\n const unsigned __int16 **v9; // rax\n int v10; // r11d\n const unsigned __int16 *v11; // r12\n __int64 v12; // rsi\n int v13; // eax\n char *v14; // rax\n size_t v16; // r15\n void *v17; // rax\n char *ptr; // [rsp+10h] [rbp-58h]\n size_t v20; // [rsp+18h] [rbp-50h]\n int v21; // [rsp+20h] [rbp-48h]\n int v22; // [rsp+24h] [rbp-44h]\n\n v3 = 0;\n v4 = a1;\n v5 = strlen(a1);\n v6 = v5 + 1;\n v7 = 0;\n v8 = (char *)malloc(v5 + 1);\n v9 = __ctype_b_loc();\n v21 = 0;\n v10 = 0;\n ptr = 0LL;\n v11 = *v9;\n do\n {\n while ( 1 )\n {\n v12 = *v4;\n v13 = v7++;\n if ( (v11[v12] & 0x2000) != 0 || !(_BYTE)v12 )\n {\n if ( a2 == v3 )\n {\n ++v21;\n v8[v13 - v10] = 0;\n v20 = 8LL * v21;\n ptr = (char *)realloc(ptr, v20);\n v16 = strlen(v8) + 1;\n v17 = malloc(v16);\n *(_QWORD *)&ptr[v20 - 8] = v17;\n __memcpy_chk(v17, v8, v16, v16);\n }\n v10 = v7;\n v3 = 0;\n goto LABEL_5;\n }\n v22 = v10;\n v8[v13 - v10] = v12;\n v14 = strchr(\"aeiouAEIOU\", (char)v12);\n v10 = v22;\n if ( !v14 )\n break;\nLABEL_5:\n ++v4;\n if ( v6 == v7 )\n goto LABEL_10;\n }\n v3 -= ((v11[(unsigned __int8)v12] & 0x400) == 0) - 1;\n ++v4;\n }\n while ( v6 != v7 );\nLABEL_10:\n free(v8);\n *a3 = v21;\n return ptr;\n}", + "ida_strip_asm": "sub_1640:\nendbr64\npush r15\nxor r15d, r15d\npush r14\nmov r14, rdi\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 38h\nmov [rsp+68h+var_5C], esi\nmov [rsp+68h+var_40], rdx\ncall _strlen\nlea rdi, [rax+1]; size\nmov rbx, rax\ncall _malloc\nlea r13d, [rbx+1]\nxor ebx, ebx\nmov rbp, rax\ncall ___ctype_b_loc\nmov [rsp+68h+var_48], 0\nxor r11d, r11d\nmov [rsp+68h+ptr], 0\nmov r12, [rax]\njmp short loc_16BA\nloc_16A0:\ncmp [rsp+68h+var_5C], r15d\njz loc_1750\nloc_16AB:\nmov r11d, ebx\nxor r15d, r15d\nloc_16B1:\nadd r14, 1\ncmp r13d, ebx\njz short loc_171F\nloc_16BA:\nmovsx rsi, byte ptr [r14]\nmov eax, ebx\nadd ebx, 1\nmov rdx, rsi\ntest byte ptr [r12+rsi*2+1], 20h\njnz short loc_16A0\ntest sil, sil\njz short loc_16A0\nsub eax, r11d\nlea rdi, s; \"aeiouAEIOU\"\nmov [rsp+68h+var_44], r11d\ncdqe\nmov byte ptr [rsp+68h+var_50], dl\nmov [rbp+rax+0], sil\nmovsx esi, sil; c\ncall _strchr\nmovzx edx, byte ptr [rsp+68h+var_50]\nmov r11d, [rsp+68h+var_44]\ntest rax, rax\njnz short loc_16B1\nmovzx eax, word ptr [r12+rdx*2]\nand ax, 400h\ncmp ax, 1\nsbb r15d, 0FFFFFFFFh\nadd r14, 1\ncmp r13d, ebx\njnz short loc_16BA\nloc_171F:\nmov rdi, rbp; ptr\ncall _free\nmov rax, [rsp+68h+var_40]\nmov edi, [rsp+68h+var_48]\nmov [rax], edi\nmov rax, [rsp+68h+ptr]\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1750:\nsub eax, r11d\nadd [rsp+68h+var_48], 1\nmovsxd rcx, [rsp+68h+var_48]\ncdqe\nmov rdi, [rsp+68h+ptr]; ptr\nmov byte ptr [rbp+rax+0], 0\nshl rcx, 3\nmov rsi, rcx; size\nmov [rsp+68h+var_50], rcx\ncall _realloc\nmov rdi, rbp; s\nmov [rsp+68h+ptr], rax\ncall _strlen\nlea r15, [rax+1]\nmov rdi, r15; size\ncall _malloc\nmov rcx, [rsp+68h+var_50]\nmov rdx, r15\nmov rsi, rbp\nmov rdi, rax\nmov rax, [rsp+68h+ptr]\nmov [rax+rcx-8], rdi\nmov rcx, r15\ncall ___memcpy_chk\njmp loc_16AB", + "ida_strip_pseudo": "char *__fastcall sub_1640(const char *a1, int a2, _DWORD *a3)\n{\n int v3; // r15d\n const char *v4; // r14\n size_t v5; // rax\n int v6; // r13d\n int v7; // ebx\n char *v8; // rbp\n const unsigned __int16 **v9; // rax\n int v10; // r11d\n const unsigned __int16 *v11; // r12\n __int64 v12; // rsi\n int v13; // eax\n char *v14; // rax\n size_t v16; // r15\n void *v17; // rax\n char *ptr; // [rsp+10h] [rbp-58h]\n size_t v20; // [rsp+18h] [rbp-50h]\n int v21; // [rsp+20h] [rbp-48h]\n int v22; // [rsp+24h] [rbp-44h]\n\n v3 = 0;\n v4 = a1;\n v5 = strlen(a1);\n v6 = v5 + 1;\n v7 = 0;\n v8 = (char *)malloc(v5 + 1);\n v9 = __ctype_b_loc();\n v21 = 0;\n v10 = 0;\n ptr = 0LL;\n v11 = *v9;\n do\n {\n while ( 1 )\n {\n v12 = *v4;\n v13 = v7++;\n if ( (v11[v12] & 0x2000) != 0 || !(_BYTE)v12 )\n {\n if ( a2 == v3 )\n {\n ++v21;\n v8[v13 - v10] = 0;\n v20 = 8LL * v21;\n ptr = (char *)realloc(ptr, v20);\n v16 = strlen(v8) + 1;\n v17 = malloc(v16);\n *(_QWORD *)&ptr[v20 - 8] = v17;\n __memcpy_chk(v17, v8, v16, v16);\n }\n v10 = v7;\n v3 = 0;\n goto LABEL_5;\n }\n v22 = v10;\n v8[v13 - v10] = v12;\n v14 = strchr(\"aeiouAEIOU\", (char)v12);\n v10 = v22;\n if ( !v14 )\n break;\nLABEL_5:\n ++v4;\n if ( v6 == v7 )\n goto LABEL_10;\n }\n v3 -= ((v11[(unsigned __int8)v12] & 0x400) == 0) - 1;\n ++v4;\n }\n while ( v6 != v7 );\nLABEL_10:\n free(v8);\n *a3 = v21;\n return ptr;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1640(const char *a1, int a2, uint32_t *a3) {\n int v3;\n const char *v4;\n unsigned int v5;\n int v6;\n int v7;\n char *v8;\n const unsigned short **v9;\n int v10;\n const unsigned short *v11;\n long long v12;\n int v13;\n char *v14;\n unsigned int v16;\n void *v17;\n char *ptr;\n unsigned int v20;\n int v21;\n int v22;\n v3 = 0;\n v4 = a1;\n v5 = strlen(a1);\n v6 = v5 + 1;\n v7 = 0;\n v8 = (char *)malloc(v5 + 1);\n v9 = __ctype_b_loc();\n v21 = 0;\n v10 = 0;\n ptr = 0LL;\n v11 = *v9;\n do {\n while (1) {\n v12 = *v4;\n v13 = v7++;\n if ((v11[v12] & 8192) != 0 || !(uint8_t)v12) {\n if (a2 == v3) {\n ++v21;\n v8[v13 - v10] = 0;\n v20 = 8LL * v21;\n ptr = (char *)realloc(ptr, v20);\n v16 = strlen(v8) + 1;\n v17 = malloc(v16);\n *(uint64_t *)&ptr[v20 - 8] = v17;\n __memcpy_chk(v17, v8, v16, v16);\n }\n v10 = v7;\n v3 = 0;\n goto LABEL_5;\n }\n v22 = v10;\n v8[v13 - v10] = v12;\n v14 = strchr(\"aeiouAEIOU\", (char)v12);\n v10 = v22;\n if (!v14) break;\n LABEL_5:\n ++v4;\n if (v6 == v7) goto LABEL_10;\n }\n v3 -= ((v11[(unsigned char)v12] & 1024) == 0) - 1;\n ++v4;\n } while (v6 != v7);\nLABEL_10:\n free(v8);\n *a3 = v21;\n return ptr;\n}", + "ida_pseudo_norm": "char *func0(const char *a1, int a2, uint32_t *a3) {\n int v3;\n const char *v4;\n unsigned int v5;\n int v6;\n int v7;\n char *v8;\n const unsigned short **v9;\n int v10;\n const unsigned short *v11;\n long long v12;\n int v13;\n char *v14;\n unsigned int v16;\n void *v17;\n char *ptr;\n unsigned int v20;\n int v21;\n int v22;\n v3 = 0;\n v4 = a1;\n v5 = strlen(a1);\n v6 = v5 + 1;\n v7 = 0;\n v8 = (char *)malloc(v5 + 1);\n v9 = __ctype_b_loc();\n v21 = 0;\n v10 = 0;\n ptr = 0LL;\n v11 = *v9;\n do {\n while (1) {\n v12 = *v4;\n v13 = v7++;\n if ((v11[v12] & 8192) != 0 || !(uint8_t)v12) {\n if (a2 == v3) {\n ++v21;\n v8[v13 - v10] = 0;\n v20 = 8LL * v21;\n ptr = (char *)realloc(ptr, v20);\n v16 = strlen(v8) + 1;\n v17 = malloc(v16);\n *(uint64_t *)&ptr[v20 - 8] = v17;\n __memcpy_chk(v17, v8, v16, v16);\n }\n v10 = v7;\n v3 = 0;\n goto LABEL_5;\n }\n v22 = v10;\n v8[v13 - v10] = v12;\n v14 = strchr(\"aeiouAEIOU\", (char)v12);\n v10 = v22;\n if (!v14) break;\n LABEL_5:\n ++v4;\n if (v6 == v7) goto LABEL_10;\n }\n v3 -= ((v11[(unsigned char)v12] & 1024) == 0) - 1;\n ++v4;\n } while (v6 != v7);\nLABEL_10:\n free(v8);\n *a3 = v21;\n return ptr;\n}" + }, + { + "index": "HumanEval-C-117", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n#include \n", + "func": "char **func0(const char *s, int n, int *returnSize) {\n const char *vowels = \"aeiouAEIOU\";\n char **out = NULL;\n int numc = 0, word_count = 0, begin = 0;\n size_t length = strlen(s);\n char *current = (char *)malloc(length + 1);\n for (int i = 0; i <= length; i++) {\n if (isspace(s[i]) || s[i] == '\\0') {\n if (numc == n) {\n current[i - begin] = '\\0';\n out = (char **)realloc(out, sizeof(char *) * (word_count + 1));\n out[word_count] = (char *)malloc(strlen(current) + 1);\n strcpy(out[word_count], current);\n word_count++;\n }\n begin = i + 1;\n numc = 0;\n } else {\n current[i - begin] = s[i];\n if (strchr(vowels, s[i]) == NULL && isalpha((unsigned char)s[i])) {\n numc++;\n }\n }\n }\n free(current);\n *returnSize = word_count;\n return out;\n}", + "test": "#include \n#include \n#include \n#include \n\nint issame(char **a, int aSize, char **b, int bSize) {\n if (aSize != bSize) return 0;\n for (int i = 0; i < aSize; i++) {\n if (strcmp(a[i], b[i]) != 0) return 0;\n }\n return 1;\n}\n\nvoid free_words(char **words, int count) {\n for (int i = 0; i < count; i++) {\n free(words[i]);\n }\n free(words);\n}\n\nint main() {\n int size;\n char **words;\n \n words = func0(\"Mary had a little lamb\", 4, &size);\n char *expected1[] = {\"little\"};\n assert(issame(words, size, expected1, 1));\n free_words(words, size);\n\n words = func0(\"Mary had a little lamb\", 3, &size);\n char *expected2[] = {\"Mary\", \"lamb\"};\n assert(issame(words, size, expected2, 2));\n free_words(words, size);\n\n words = func0(\"simple white space\", 2, &size);\n assert(size == 0);\n free_words(words, size);\n\n words = func0(\"Hello world\", 4, &size);\n char *expected3[] = {\"world\"};\n assert(issame(words, size, expected3, 1));\n free_words(words, size);\n\n words = func0(\"Uncle sam\", 3, &size);\n char *expected4[] = {\"Uncle\"};\n assert(issame(words, size, expected4, 1));\n free_words(words, size);\n\n words = func0(\"\", 4, &size);\n assert(size == 0);\n free_words(words, size);\n\n words = func0(\"a b c d e f\", 1, &size);\n char *expected5[] = {\"b\", \"c\", \"d\", \"f\"};\n assert(issame(words, size, expected5, 4));\n free_words(words, size);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\nxor r15d, r15d\npush r14\nmov r14, rdi\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 38h\nmov [rsp+68h+var_5C], esi\nmov [rsp+68h+var_40], rdx\ncall _strlen\nlea rdi, [rax+1]; size\nmov rbx, rax\ncall _malloc\nlea r13d, [rbx+1]\nxor ebx, ebx\nmov rbp, rax\ncall ___ctype_b_loc\nmov [rsp+68h+var_48], 0\nxor r11d, r11d\nmov [rsp+68h+ptr], 0\nmov r12, [rax]\njmp short loc_16BA\nloc_16A0:\ncmp [rsp+68h+var_5C], r15d\njz loc_1750\nloc_16AB:\nmov r11d, ebx\nxor r15d, r15d\nloc_16B1:\nadd r14, 1\ncmp r13d, ebx\njz short loc_171F\nloc_16BA:\nmovsx rsi, byte ptr [r14]\nmov eax, ebx\nadd ebx, 1\nmov rdx, rsi\ntest byte ptr [r12+rsi*2+1], 20h\njnz short loc_16A0\ntest sil, sil\njz short loc_16A0\nsub eax, r11d\nlea rdi, s; \"aeiouAEIOU\"\nmov [rsp+68h+var_44], r11d\ncdqe\nmov byte ptr [rsp+68h+var_50], dl\nmov [rbp+rax+0], sil\nmovsx esi, sil; c\ncall _strchr\nmovzx edx, byte ptr [rsp+68h+var_50]\nmov r11d, [rsp+68h+var_44]\ntest rax, rax\njnz short loc_16B1\nmovzx eax, word ptr [r12+rdx*2]\nand ax, 400h\ncmp ax, 1\nsbb r15d, 0FFFFFFFFh\nadd r14, 1\ncmp r13d, ebx\njnz short loc_16BA\nloc_171F:\nmov rdi, rbp; ptr\ncall _free\nmov rax, [rsp+68h+var_40]\nmov edi, [rsp+68h+var_48]\nmov [rax], edi\nmov rax, [rsp+68h+ptr]\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1750:\nsub eax, r11d\nadd [rsp+68h+var_48], 1\nmovsxd rcx, [rsp+68h+var_48]\ncdqe\nmov rdi, [rsp+68h+ptr]; ptr\nmov byte ptr [rbp+rax+0], 0\nshl rcx, 3\nmov rsi, rcx; size\nmov [rsp+68h+var_50], rcx\ncall _realloc\nmov rdi, rbp; s\nmov [rsp+68h+ptr], rax\ncall _strlen\nlea r15, [rax+1]\nmov rdi, r15; size\ncall _malloc\nmov rcx, [rsp+68h+var_50]\nmov rdx, r15\nmov rsi, rbp\nmov rdi, rax\nmov rax, [rsp+68h+ptr]\nmov [rax+rcx-8], rdi\nmov rcx, r15\ncall ___memcpy_chk\njmp loc_16AB", + "ida_pseudo": "char *__fastcall func0(const char *a1, int a2, _DWORD *a3)\n{\n int v3; // r15d\n const char *v4; // r14\n size_t v5; // rax\n int v6; // r13d\n int v7; // ebx\n char *v8; // rbp\n const unsigned __int16 **v9; // rax\n int v10; // r11d\n const unsigned __int16 *v11; // r12\n __int64 v12; // rsi\n int v13; // eax\n char *v14; // rax\n size_t v16; // r15\n void *v17; // rax\n char *ptr; // [rsp+10h] [rbp-58h]\n size_t v20; // [rsp+18h] [rbp-50h]\n int v21; // [rsp+20h] [rbp-48h]\n int v22; // [rsp+24h] [rbp-44h]\n\n v3 = 0;\n v4 = a1;\n v5 = strlen(a1);\n v6 = v5 + 1;\n v7 = 0;\n v8 = (char *)malloc(v5 + 1);\n v9 = __ctype_b_loc();\n v21 = 0;\n v10 = 0;\n ptr = 0LL;\n v11 = *v9;\n do\n {\n while ( 1 )\n {\n v12 = *v4;\n v13 = v7++;\n if ( (v11[v12] & 0x2000) != 0 || !(_BYTE)v12 )\n {\n if ( a2 == v3 )\n {\n ++v21;\n v8[v13 - v10] = 0;\n v20 = 8LL * v21;\n ptr = (char *)realloc(ptr, v20);\n v16 = strlen(v8) + 1;\n v17 = malloc(v16);\n *(_QWORD *)&ptr[v20 - 8] = v17;\n __memcpy_chk(v17, v8, v16, v16);\n }\n v10 = v7;\n v3 = 0;\n goto LABEL_5;\n }\n v22 = v10;\n v8[v13 - v10] = v12;\n v14 = strchr(\"aeiouAEIOU\", (char)v12);\n v10 = v22;\n if ( !v14 )\n break;\nLABEL_5:\n ++v4;\n if ( v6 == v7 )\n goto LABEL_10;\n }\n v3 -= ((v11[(unsigned __int8)v12] & 0x400) == 0) - 1;\n ++v4;\n }\n while ( v6 != v7 );\nLABEL_10:\n free(v8);\n *a3 = v21;\n return ptr;\n}", + "ida_strip_asm": "sub_1640:\nendbr64\npush r15\nxor r15d, r15d\npush r14\nmov r14, rdi\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 38h\nmov [rsp+68h+var_5C], esi\nmov [rsp+68h+var_40], rdx\ncall _strlen\nlea rdi, [rax+1]; size\nmov rbx, rax\ncall _malloc\nlea r13d, [rbx+1]\nxor ebx, ebx\nmov rbp, rax\ncall ___ctype_b_loc\nmov [rsp+68h+var_48], 0\nxor r11d, r11d\nmov [rsp+68h+ptr], 0\nmov r12, [rax]\njmp short loc_16BA\nloc_16A0:\ncmp [rsp+68h+var_5C], r15d\njz loc_1750\nloc_16AB:\nmov r11d, ebx\nxor r15d, r15d\nloc_16B1:\nadd r14, 1\ncmp r13d, ebx\njz short loc_171F\nloc_16BA:\nmovsx rsi, byte ptr [r14]\nmov eax, ebx\nadd ebx, 1\nmov rdx, rsi\ntest byte ptr [r12+rsi*2+1], 20h\njnz short loc_16A0\ntest sil, sil\njz short loc_16A0\nsub eax, r11d\nlea rdi, s; \"aeiouAEIOU\"\nmov [rsp+68h+var_44], r11d\ncdqe\nmov byte ptr [rsp+68h+var_50], dl\nmov [rbp+rax+0], sil\nmovsx esi, sil; c\ncall _strchr\nmovzx edx, byte ptr [rsp+68h+var_50]\nmov r11d, [rsp+68h+var_44]\ntest rax, rax\njnz short loc_16B1\nmovzx eax, word ptr [r12+rdx*2]\nand ax, 400h\ncmp ax, 1\nsbb r15d, 0FFFFFFFFh\nadd r14, 1\ncmp r13d, ebx\njnz short loc_16BA\nloc_171F:\nmov rdi, rbp; ptr\ncall _free\nmov rax, [rsp+68h+var_40]\nmov edi, [rsp+68h+var_48]\nmov [rax], edi\nmov rax, [rsp+68h+ptr]\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1750:\nsub eax, r11d\nadd [rsp+68h+var_48], 1\nmovsxd rcx, [rsp+68h+var_48]\ncdqe\nmov rdi, [rsp+68h+ptr]; ptr\nmov byte ptr [rbp+rax+0], 0\nshl rcx, 3\nmov rsi, rcx; size\nmov [rsp+68h+var_50], rcx\ncall _realloc\nmov rdi, rbp; s\nmov [rsp+68h+ptr], rax\ncall _strlen\nlea r15, [rax+1]\nmov rdi, r15; size\ncall _malloc\nmov rcx, [rsp+68h+var_50]\nmov rdx, r15\nmov rsi, rbp\nmov rdi, rax\nmov rax, [rsp+68h+ptr]\nmov [rax+rcx-8], rdi\nmov rcx, r15\ncall ___memcpy_chk\njmp loc_16AB", + "ida_strip_pseudo": "char *__fastcall sub_1640(const char *a1, int a2, _DWORD *a3)\n{\n int v3; // r15d\n const char *v4; // r14\n size_t v5; // rax\n int v6; // r13d\n int v7; // ebx\n char *v8; // rbp\n const unsigned __int16 **v9; // rax\n int v10; // r11d\n const unsigned __int16 *v11; // r12\n __int64 v12; // rsi\n int v13; // eax\n char *v14; // rax\n size_t v16; // r15\n void *v17; // rax\n char *ptr; // [rsp+10h] [rbp-58h]\n size_t v20; // [rsp+18h] [rbp-50h]\n int v21; // [rsp+20h] [rbp-48h]\n int v22; // [rsp+24h] [rbp-44h]\n\n v3 = 0;\n v4 = a1;\n v5 = strlen(a1);\n v6 = v5 + 1;\n v7 = 0;\n v8 = (char *)malloc(v5 + 1);\n v9 = __ctype_b_loc();\n v21 = 0;\n v10 = 0;\n ptr = 0LL;\n v11 = *v9;\n do\n {\n while ( 1 )\n {\n v12 = *v4;\n v13 = v7++;\n if ( (v11[v12] & 0x2000) != 0 || !(_BYTE)v12 )\n {\n if ( a2 == v3 )\n {\n ++v21;\n v8[v13 - v10] = 0;\n v20 = 8LL * v21;\n ptr = (char *)realloc(ptr, v20);\n v16 = strlen(v8) + 1;\n v17 = malloc(v16);\n *(_QWORD *)&ptr[v20 - 8] = v17;\n __memcpy_chk(v17, v8, v16, v16);\n }\n v10 = v7;\n v3 = 0;\n goto LABEL_5;\n }\n v22 = v10;\n v8[v13 - v10] = v12;\n v14 = strchr(\"aeiouAEIOU\", (char)v12);\n v10 = v22;\n if ( !v14 )\n break;\nLABEL_5:\n ++v4;\n if ( v6 == v7 )\n goto LABEL_10;\n }\n v3 -= ((v11[(unsigned __int8)v12] & 0x400) == 0) - 1;\n ++v4;\n }\n while ( v6 != v7 );\nLABEL_10:\n free(v8);\n *a3 = v21;\n return ptr;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1640(const char *a1, int a2, uint32_t *a3) {\n int v3;\n const char *v4;\n unsigned int v5;\n int v6;\n int v7;\n char *v8;\n const unsigned short **v9;\n int v10;\n const unsigned short *v11;\n long long v12;\n int v13;\n char *v14;\n unsigned int v16;\n void *v17;\n char *ptr;\n unsigned int v20;\n int v21;\n int v22;\n v3 = 0;\n v4 = a1;\n v5 = strlen(a1);\n v6 = v5 + 1;\n v7 = 0;\n v8 = (char *)malloc(v5 + 1);\n v9 = __ctype_b_loc();\n v21 = 0;\n v10 = 0;\n ptr = 0LL;\n v11 = *v9;\n do {\n while (1) {\n v12 = *v4;\n v13 = v7++;\n if ((v11[v12] & 8192) != 0 || !(uint8_t)v12) {\n if (a2 == v3) {\n ++v21;\n v8[v13 - v10] = 0;\n v20 = 8LL * v21;\n ptr = (char *)realloc(ptr, v20);\n v16 = strlen(v8) + 1;\n v17 = malloc(v16);\n *(uint64_t *)&ptr[v20 - 8] = v17;\n __memcpy_chk(v17, v8, v16, v16);\n }\n v10 = v7;\n v3 = 0;\n goto LABEL_5;\n }\n v22 = v10;\n v8[v13 - v10] = v12;\n v14 = strchr(\"aeiouAEIOU\", (char)v12);\n v10 = v22;\n if (!v14) break;\n LABEL_5:\n ++v4;\n if (v6 == v7) goto LABEL_10;\n }\n v3 -= ((v11[(unsigned char)v12] & 1024) == 0) - 1;\n ++v4;\n } while (v6 != v7);\nLABEL_10:\n free(v8);\n *a3 = v21;\n return ptr;\n}", + "ida_pseudo_norm": "char *func0(const char *a1, int a2, uint32_t *a3) {\n int v3;\n const char *v4;\n unsigned int v5;\n int v6;\n int v7;\n char *v8;\n const unsigned short **v9;\n int v10;\n const unsigned short *v11;\n long long v12;\n int v13;\n char *v14;\n unsigned int v16;\n void *v17;\n char *ptr;\n unsigned int v20;\n int v21;\n int v22;\n v3 = 0;\n v4 = a1;\n v5 = strlen(a1);\n v6 = v5 + 1;\n v7 = 0;\n v8 = (char *)malloc(v5 + 1);\n v9 = __ctype_b_loc();\n v21 = 0;\n v10 = 0;\n ptr = 0LL;\n v11 = *v9;\n do {\n while (1) {\n v12 = *v4;\n v13 = v7++;\n if ((v11[v12] & 8192) != 0 || !(uint8_t)v12) {\n if (a2 == v3) {\n ++v21;\n v8[v13 - v10] = 0;\n v20 = 8LL * v21;\n ptr = (char *)realloc(ptr, v20);\n v16 = strlen(v8) + 1;\n v17 = malloc(v16);\n *(uint64_t *)&ptr[v20 - 8] = v17;\n __memcpy_chk(v17, v8, v16, v16);\n }\n v10 = v7;\n v3 = 0;\n goto LABEL_5;\n }\n v22 = v10;\n v8[v13 - v10] = v12;\n v14 = strchr(\"aeiouAEIOU\", (char)v12);\n v10 = v22;\n if (!v14) break;\n LABEL_5:\n ++v4;\n if (v6 == v7) goto LABEL_10;\n }\n v3 -= ((v11[(unsigned char)v12] & 1024) == 0) - 1;\n ++v4;\n } while (v6 != v7);\nLABEL_10:\n free(v8);\n *a3 = v21;\n return ptr;\n}" + }, + { + "index": "HumanEval-C-118", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "char *func0(const char *word) {\n static char out[2] = {0};\n const char *vowels = \"AEIOUaeiou\";\n size_t len = strlen(word);\n for (int i = len - 2; i >= 1; i--) {\n if (strchr(vowels, word[i]) && !strchr(vowels, word[i + 1]) &&\n !strchr(vowels, word[i - 1])) {\n out[0] = word[i];\n return out;\n }\n }\n out[0] = '\\0';\n return out;\n}", + "test": "#include \n#include \n#include \n\nint main() {\n assert(strcmp(func0(\"yogurt\"), \"u\") == 0);\n assert(strcmp(func0(\"full\"), \"u\") == 0);\n assert(strcmp(func0(\"easy\"), \"\") == 0);\n assert(strcmp(func0(\"eAsy\"), \"\") == 0);\n assert(strcmp(func0(\"ali\"), \"\") == 0);\n assert(strcmp(func0(\"bad\"), \"a\") == 0);\n assert(strcmp(func0(\"most\"), \"o\") == 0);\n assert(strcmp(func0(\"ab\"), \"\") == 0);\n assert(strcmp(func0(\"ba\"), \"\") == 0);\n assert(strcmp(func0(\"quick\"), \"\") == 0);\n assert(strcmp(func0(\"anime\"), \"i\") == 0);\n assert(strcmp(func0(\"Asia\"), \"\") == 0);\n assert(strcmp(func0(\"Above\"), \"o\") == 0);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nlea rax, aAeiouaeiou; \"AEIOUaeiou\"\nmov [rbp+var_10], rax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_8], rax\nmov rax, [rbp+var_8]\nsub eax, 2\nmov [rbp+var_14], eax\njmp loc_127E\nloc_11E3:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx edx, al\nmov rax, [rbp+var_10]\nmov esi, edx; c\nmov rdi, rax; s\ncall _strchr\ntest rax, rax\njz short loc_127A\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, [rax+1]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx edx, al\nmov rax, [rbp+var_10]\nmov esi, edx; c\nmov rdi, rax; s\ncall _strchr\ntest rax, rax\njnz short loc_127A\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx edx, al\nmov rax, [rbp+var_10]\nmov esi, edx; c\nmov rdi, rax; s\ncall _strchr\ntest rax, rax\njnz short loc_127A\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov cs:out_1, al\nlea rax, out_1\njmp short locret_1296\nloc_127A:\nsub [rbp+var_14], 1\nloc_127E:\ncmp [rbp+var_14], 0\njg loc_11E3\nmov cs:out_1, 0\nlea rax, out_1\nlocret_1296:\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(const char *a1)\n{\n int i; // [rsp+1Ch] [rbp-14h]\n\n for ( i = strlen(a1) - 2; i > 0; --i )\n {\n if ( strchr(\"AEIOUaeiou\", a1[i]) && !strchr(\"AEIOUaeiou\", a1[i + 1]) && !strchr(\"AEIOUaeiou\", a1[i - 1]) )\n {\n out_1 = a1[i];\n return &out_1;\n }\n }\n out_1 = 0;\n return &out_1;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nlea rax, aAeiouaeiou; \"AEIOUaeiou\"\nmov [rbp+var_10], rax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_8], rax\nmov rax, [rbp+var_8]\nsub eax, 2\nmov [rbp+var_14], eax\njmp loc_127E\nloc_11E3:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx edx, al\nmov rax, [rbp+var_10]\nmov esi, edx; c\nmov rdi, rax; s\ncall _strchr\ntest rax, rax\njz short loc_127A\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, [rax+1]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx edx, al\nmov rax, [rbp+var_10]\nmov esi, edx; c\nmov rdi, rax; s\ncall _strchr\ntest rax, rax\njnz short loc_127A\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx edx, al\nmov rax, [rbp+var_10]\nmov esi, edx; c\nmov rdi, rax; s\ncall _strchr\ntest rax, rax\njnz short loc_127A\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov cs:byte_4011, al\nlea rax, byte_4011\njmp short locret_1296\nloc_127A:\nsub [rbp+var_14], 1\nloc_127E:\ncmp [rbp+var_14], 0\njg loc_11E3\nmov cs:byte_4011, 0\nlea rax, byte_4011\nlocret_1296:\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11A9(const char *a1)\n{\n int i; // [rsp+1Ch] [rbp-14h]\n\n for ( i = strlen(a1) - 2; i > 0; --i )\n {\n if ( strchr(\"AEIOUaeiou\", a1[i]) && !strchr(\"AEIOUaeiou\", a1[i + 1]) && !strchr(\"AEIOUaeiou\", a1[i - 1]) )\n {\n byte_4011 = a1[i];\n return &byte_4011;\n }\n }\n byte_4011 = 0;\n return &byte_4011;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11A9(const char *a1) {\n int i;\n for (i = strlen(a1) - 2; i > 0; --i) {\n if (strchr(\"AEIOUaeiou\", a1[i]) && !strchr(\"AEIOUaeiou\", a1[i + 1]) &&\n !strchr(\"AEIOUaeiou\", a1[i - 1])) {\n byte_4011 = a1[i];\n return &byte_4011;\n }\n }\n byte_4011 = 0;\n return &byte_4011;\n}", + "ida_pseudo_norm": "char *func0(const char *a1) {\n int i;\n for (i = strlen(a1) - 2; i > 0; --i) {\n if (strchr(\"AEIOUaeiou\", a1[i]) && !strchr(\"AEIOUaeiou\", a1[i + 1]) &&\n !strchr(\"AEIOUaeiou\", a1[i - 1])) {\n out_1 = a1[i];\n return &out_1;\n }\n }\n out_1 = 0;\n return &out_1;\n}" + }, + { + "index": "HumanEval-C-118", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "char *func0(const char *word) {\n static char out[2] = {0};\n const char *vowels = \"AEIOUaeiou\";\n size_t len = strlen(word);\n for (int i = len - 2; i >= 1; i--) {\n if (strchr(vowels, word[i]) && !strchr(vowels, word[i + 1]) &&\n !strchr(vowels, word[i - 1])) {\n out[0] = word[i];\n return out;\n }\n }\n out[0] = '\\0';\n return out;\n}", + "test": "#include \n#include \n#include \n\nint main() {\n assert(strcmp(func0(\"yogurt\"), \"u\") == 0);\n assert(strcmp(func0(\"full\"), \"u\") == 0);\n assert(strcmp(func0(\"easy\"), \"\") == 0);\n assert(strcmp(func0(\"eAsy\"), \"\") == 0);\n assert(strcmp(func0(\"ali\"), \"\") == 0);\n assert(strcmp(func0(\"bad\"), \"a\") == 0);\n assert(strcmp(func0(\"most\"), \"o\") == 0);\n assert(strcmp(func0(\"ab\"), \"\") == 0);\n assert(strcmp(func0(\"ba\"), \"\") == 0);\n assert(strcmp(func0(\"quick\"), \"\") == 0);\n assert(strcmp(func0(\"anime\"), \"i\") == 0);\n assert(strcmp(func0(\"Asia\"), \"\") == 0);\n assert(strcmp(func0(\"Above\"), \"o\") == 0);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbp, rdi\ncall _strlen\nlea edx, [rax-2]\ntest edx, edx\njle short loc_123D\nmovsxd rdx, edx\nlea rbx, [rbp+rdx+0]\nlea r14, [rbp+rdx-1]\nlea eax, [rax-3]\nsub r14, rax\nlea r12, s; \"AEIOUaeiou\"\njmp short loc_11E9\nloc_11E0:\nsub rbx, 1\ncmp rbx, r14\njz short loc_1221\nloc_11E9:\nmovzx ebp, byte ptr [rbx]\nmovsx esi, bpl; c\nmov rdi, r12; s\ncall _strchr\ntest rax, rax\njz short loc_11E0\nmovsx esi, byte ptr [rbx+1]; c\nmov rdi, r12; s\ncall _strchr\ntest rax, rax\njnz short loc_11E0\nmovsx esi, byte ptr [rbx-1]; c\nmov rdi, r12; s\ncall _strchr\ntest rax, rax\njnz short loc_11E0\njmp short loc_1226\nloc_1221:\nmov ebp, 0\nloc_1226:\nmov cs:out_1, bpl\nlea rax, out_1\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_123D:\nmov ebp, 0\njmp short loc_1226", + "ida_pseudo": "char *__fastcall func0(const char *a1)\n{\n int v1; // eax\n char *v2; // rbx\n __int64 v3; // r14\n char v4; // bp\n\n v1 = strlen(a1);\n if ( v1 - 2 <= 0 )\n {\n v4 = 0;\n }\n else\n {\n v2 = (char *)&a1[v1 - 2];\n v3 = (__int64)&v2[-(v1 - 3) - 1];\n while ( 1 )\n {\n v4 = *v2;\n if ( strchr(\"AEIOUaeiou\", *v2) )\n {\n if ( !strchr(\"AEIOUaeiou\", v2[1]) && !strchr(\"AEIOUaeiou\", *(v2 - 1)) )\n break;\n }\n if ( --v2 == (char *)v3 )\n {\n v4 = 0;\n break;\n }\n }\n }\n out_1 = v4;\n return &out_1;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbp, rdi\ncall _strlen\nlea edx, [rax-2]\ntest edx, edx\njle short loc_123D\nmovsxd rdx, edx\nlea rbx, [rbp+rdx+0]\nlea r14, [rbp+rdx-1]\nlea eax, [rax-3]\nsub r14, rax\nlea r12, s; \"AEIOUaeiou\"\njmp short loc_11E9\nloc_11E0:\nsub rbx, 1\ncmp rbx, r14\njz short loc_1221\nloc_11E9:\nmovzx ebp, byte ptr [rbx]\nmovsx esi, bpl; c\nmov rdi, r12; s\ncall _strchr\ntest rax, rax\njz short loc_11E0\nmovsx esi, byte ptr [rbx+1]; c\nmov rdi, r12; s\ncall _strchr\ntest rax, rax\njnz short loc_11E0\nmovsx esi, byte ptr [rbx-1]; c\nmov rdi, r12; s\ncall _strchr\ntest rax, rax\njnz short loc_11E0\njmp short loc_1226\nloc_1221:\nmov ebp, 0\nloc_1226:\nmov cs:byte_4011, bpl\nlea rax, byte_4011\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_123D:\nmov ebp, 0\njmp short loc_1226", + "ida_strip_pseudo": "char *__fastcall sub_11A9(const char *a1)\n{\n int v1; // eax\n char *v2; // rbx\n __int64 v3; // r14\n char v4; // bp\n\n v1 = strlen(a1);\n if ( v1 - 2 <= 0 )\n {\n v4 = 0;\n }\n else\n {\n v2 = (char *)&a1[v1 - 2];\n v3 = (__int64)&v2[-(v1 - 3) - 1];\n while ( 1 )\n {\n v4 = *v2;\n if ( strchr(\"AEIOUaeiou\", *v2) )\n {\n if ( !strchr(\"AEIOUaeiou\", v2[1]) && !strchr(\"AEIOUaeiou\", *(v2 - 1)) )\n break;\n }\n if ( --v2 == (char *)v3 )\n {\n v4 = 0;\n break;\n }\n }\n }\n byte_4011 = v4;\n return &byte_4011;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11A9(const char *a1) {\n int v1;\n char *v2;\n long long v3;\n char v4;\n v1 = strlen(a1);\n if (v1 - 2 <= 0) {\n v4 = 0;\n } else {\n v2 = (char *)&a1[v1 - 2];\n v3 = (long long)&v2[-(v1 - 3) - 1];\n while (1) {\n v4 = *v2;\n if (strchr(\"AEIOUaeiou\", *v2)) {\n if (!strchr(\"AEIOUaeiou\", v2[1]) && !strchr(\"AEIOUaeiou\", *(v2 - 1)))\n break;\n }\n if (--v2 == (char *)v3) {\n v4 = 0;\n break;\n }\n }\n }\n byte_4011 = v4;\n return &byte_4011;\n}", + "ida_pseudo_norm": "char *func0(const char *a1) {\n int v1;\n char *v2;\n long long v3;\n char v4;\n v1 = strlen(a1);\n if (v1 - 2 <= 0) {\n v4 = 0;\n } else {\n v2 = (char *)&a1[v1 - 2];\n v3 = (long long)&v2[-(v1 - 3) - 1];\n while (1) {\n v4 = *v2;\n if (strchr(\"AEIOUaeiou\", *v2)) {\n if (!strchr(\"AEIOUaeiou\", v2[1]) && !strchr(\"AEIOUaeiou\", *(v2 - 1)))\n break;\n }\n if (--v2 == (char *)v3) {\n v4 = 0;\n break;\n }\n }\n }\n out_1 = v4;\n return &out_1;\n}" + }, + { + "index": "HumanEval-C-118", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "char *func0(const char *word) {\n static char out[2] = {0};\n const char *vowels = \"AEIOUaeiou\";\n size_t len = strlen(word);\n for (int i = len - 2; i >= 1; i--) {\n if (strchr(vowels, word[i]) && !strchr(vowels, word[i + 1]) &&\n !strchr(vowels, word[i - 1])) {\n out[0] = word[i];\n return out;\n }\n }\n out[0] = '\\0';\n return out;\n}", + "test": "#include \n#include \n#include \n\nint main() {\n assert(strcmp(func0(\"yogurt\"), \"u\") == 0);\n assert(strcmp(func0(\"full\"), \"u\") == 0);\n assert(strcmp(func0(\"easy\"), \"\") == 0);\n assert(strcmp(func0(\"eAsy\"), \"\") == 0);\n assert(strcmp(func0(\"ali\"), \"\") == 0);\n assert(strcmp(func0(\"bad\"), \"a\") == 0);\n assert(strcmp(func0(\"most\"), \"o\") == 0);\n assert(strcmp(func0(\"ab\"), \"\") == 0);\n assert(strcmp(func0(\"ba\"), \"\") == 0);\n assert(strcmp(func0(\"quick\"), \"\") == 0);\n assert(strcmp(func0(\"anime\"), \"i\") == 0);\n assert(strcmp(func0(\"Asia\"), \"\") == 0);\n assert(strcmp(func0(\"Above\"), \"o\") == 0);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 8\ncall _strlen\nlea edx, [rax-2]\ntest edx, edx\njle loc_1500\nlea r13, [rbp+rdx-1]\nsub eax, 3\nlea rbx, [rbp+rdx+0]\nsub r13, rax\nlea r12, s; \"AEIOUaeiou\"\njmp short loc_14A9\nloc_14A0:\nsub rbx, 1\ncmp rbx, r13\njz short loc_1500\nloc_14A9:\nmovsx esi, byte ptr [rbx]; c\nmov rdi, r12; s\nmov ebp, esi\ncall _strchr\ntest rax, rax\njz short loc_14A0\nmovsx esi, byte ptr [rbx+1]; c\nmov rdi, r12; s\ncall _strchr\ntest rax, rax\njnz short loc_14A0\nmovsx esi, byte ptr [rbx-1]; c\nmov rdi, r12; s\ncall _strchr\ntest rax, rax\njnz short loc_14A0\nloc_14DD:\nmov cs:out_1, bpl\nadd rsp, 8\nlea rax, out_1\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1500:\nxor ebp, ebp\njmp short loc_14DD", + "ida_pseudo": "char *__fastcall func0(const char *a1)\n{\n int v1; // eax\n __int64 v2; // rdx\n char *v3; // rbx\n __int64 v4; // r13\n char v5; // bp\n\n v1 = strlen(a1);\n v2 = (unsigned int)(v1 - 2);\n if ( v1 - 2 <= 0 )\n {\nLABEL_8:\n v5 = 0;\n }\n else\n {\n v3 = (char *)&a1[v2];\n v4 = (__int64)&a1[v2 - 1 - (unsigned int)(v1 - 3)];\n while ( 1 )\n {\n v5 = *v3;\n if ( strchr(\"AEIOUaeiou\", *v3) )\n {\n if ( !strchr(\"AEIOUaeiou\", v3[1]) && !strchr(\"AEIOUaeiou\", *(v3 - 1)) )\n break;\n }\n if ( --v3 == (char *)v4 )\n goto LABEL_8;\n }\n }\n out_1 = v5;\n return &out_1;\n}", + "ida_strip_asm": "sub_1460:\nendbr64\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 8\ncall _strlen\nlea edx, [rax-2]\ntest edx, edx\njle loc_1500\nlea r13, [rbp+rdx-1]\nsub eax, 3\nlea rbx, [rbp+rdx+0]\nsub r13, rax\nlea r12, s; \"AEIOUaeiou\"\njmp short loc_14A9\nloc_14A0:\nsub rbx, 1\ncmp rbx, r13\njz short loc_1500\nloc_14A9:\nmovsx esi, byte ptr [rbx]; c\nmov rdi, r12; s\nmov ebp, esi\ncall _strchr\ntest rax, rax\njz short loc_14A0\nmovsx esi, byte ptr [rbx+1]; c\nmov rdi, r12; s\ncall _strchr\ntest rax, rax\njnz short loc_14A0\nmovsx esi, byte ptr [rbx-1]; c\nmov rdi, r12; s\ncall _strchr\ntest rax, rax\njnz short loc_14A0\nloc_14DD:\nmov cs:byte_4011, bpl\nadd rsp, 8\nlea rax, byte_4011\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1500:\nxor ebp, ebp\njmp short loc_14DD", + "ida_strip_pseudo": "char *__fastcall sub_1460(const char *a1)\n{\n int v1; // eax\n __int64 v2; // rdx\n char *v3; // rbx\n __int64 v4; // r13\n char v5; // bp\n\n v1 = strlen(a1);\n v2 = (unsigned int)(v1 - 2);\n if ( v1 - 2 <= 0 )\n {\nLABEL_8:\n v5 = 0;\n }\n else\n {\n v3 = (char *)&a1[v2];\n v4 = (__int64)&a1[v2 - 1 - (unsigned int)(v1 - 3)];\n while ( 1 )\n {\n v5 = *v3;\n if ( strchr(\"AEIOUaeiou\", *v3) )\n {\n if ( !strchr(\"AEIOUaeiou\", v3[1]) && !strchr(\"AEIOUaeiou\", *(v3 - 1)) )\n break;\n }\n if ( --v3 == (char *)v4 )\n goto LABEL_8;\n }\n }\n byte_4011 = v5;\n return &byte_4011;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1460(const char *a1) {\n int v1;\n long long v2;\n char *v3;\n long long v4;\n char v5;\n v1 = strlen(a1);\n v2 = (unsigned int)(v1 - 2);\n if (v1 - 2 <= 0) {\n LABEL_8:\n v5 = 0;\n } else {\n v3 = (char *)&a1[v2];\n v4 = (long long)&a1[v2 - 1 - (unsigned int)(v1 - 3)];\n while (1) {\n v5 = *v3;\n if (strchr(\"AEIOUaeiou\", *v3)) {\n if (!strchr(\"AEIOUaeiou\", v3[1]) && !strchr(\"AEIOUaeiou\", *(v3 - 1)))\n break;\n }\n if (--v3 == (char *)v4) goto LABEL_8;\n }\n }\n byte_4011 = v5;\n return &byte_4011;\n}", + "ida_pseudo_norm": "char *func0(const char *a1) {\n int v1;\n long long v2;\n char *v3;\n long long v4;\n char v5;\n v1 = strlen(a1);\n v2 = (unsigned int)(v1 - 2);\n if (v1 - 2 <= 0) {\n LABEL_8:\n v5 = 0;\n } else {\n v3 = (char *)&a1[v2];\n v4 = (long long)&a1[v2 - 1 - (unsigned int)(v1 - 3)];\n while (1) {\n v5 = *v3;\n if (strchr(\"AEIOUaeiou\", *v3)) {\n if (!strchr(\"AEIOUaeiou\", v3[1]) && !strchr(\"AEIOUaeiou\", *(v3 - 1)))\n break;\n }\n if (--v3 == (char *)v4) goto LABEL_8;\n }\n }\n out_1 = v5;\n return &out_1;\n}" + }, + { + "index": "HumanEval-C-118", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "char *func0(const char *word) {\n static char out[2] = {0};\n const char *vowels = \"AEIOUaeiou\";\n size_t len = strlen(word);\n for (int i = len - 2; i >= 1; i--) {\n if (strchr(vowels, word[i]) && !strchr(vowels, word[i + 1]) &&\n !strchr(vowels, word[i - 1])) {\n out[0] = word[i];\n return out;\n }\n }\n out[0] = '\\0';\n return out;\n}", + "test": "#include \n#include \n#include \n\nint main() {\n assert(strcmp(func0(\"yogurt\"), \"u\") == 0);\n assert(strcmp(func0(\"full\"), \"u\") == 0);\n assert(strcmp(func0(\"easy\"), \"\") == 0);\n assert(strcmp(func0(\"eAsy\"), \"\") == 0);\n assert(strcmp(func0(\"ali\"), \"\") == 0);\n assert(strcmp(func0(\"bad\"), \"a\") == 0);\n assert(strcmp(func0(\"most\"), \"o\") == 0);\n assert(strcmp(func0(\"ab\"), \"\") == 0);\n assert(strcmp(func0(\"ba\"), \"\") == 0);\n assert(strcmp(func0(\"quick\"), \"\") == 0);\n assert(strcmp(func0(\"anime\"), \"i\") == 0);\n assert(strcmp(func0(\"Asia\"), \"\") == 0);\n assert(strcmp(func0(\"Above\"), \"o\") == 0);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 8\ncall _strlen\nlea edx, [rax-2]\ntest edx, edx\njle loc_1500\nlea r13, [rbp+rdx-1]\nsub eax, 3\nlea rbx, [rbp+rdx+0]\nsub r13, rax\nlea r12, s; \"AEIOUaeiou\"\njmp short loc_14A9\nloc_14A0:\nsub rbx, 1\ncmp rbx, r13\njz short loc_1500\nloc_14A9:\nmovsx esi, byte ptr [rbx]; c\nmov rdi, r12; s\nmov ebp, esi\ncall _strchr\ntest rax, rax\njz short loc_14A0\nmovsx esi, byte ptr [rbx+1]; c\nmov rdi, r12; s\ncall _strchr\ntest rax, rax\njnz short loc_14A0\nmovsx esi, byte ptr [rbx-1]; c\nmov rdi, r12; s\ncall _strchr\ntest rax, rax\njnz short loc_14A0\nloc_14DD:\nmov cs:out_1, bpl\nadd rsp, 8\nlea rax, out_1\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1500:\nxor ebp, ebp\njmp short loc_14DD", + "ida_pseudo": "char *__fastcall func0(const char *a1)\n{\n int v1; // eax\n __int64 v2; // rdx\n char *v3; // rbx\n __int64 v4; // r13\n char v5; // bp\n\n v1 = strlen(a1);\n v2 = (unsigned int)(v1 - 2);\n if ( v1 - 2 <= 0 )\n {\nLABEL_8:\n v5 = 0;\n }\n else\n {\n v3 = (char *)&a1[v2];\n v4 = (__int64)&a1[v2 - 1 - (unsigned int)(v1 - 3)];\n while ( 1 )\n {\n v5 = *v3;\n if ( strchr(\"AEIOUaeiou\", *v3) )\n {\n if ( !strchr(\"AEIOUaeiou\", v3[1]) && !strchr(\"AEIOUaeiou\", *(v3 - 1)) )\n break;\n }\n if ( --v3 == (char *)v4 )\n goto LABEL_8;\n }\n }\n out_1 = v5;\n return &out_1;\n}", + "ida_strip_asm": "sub_1460:\nendbr64\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 8\ncall _strlen\nlea edx, [rax-2]\ntest edx, edx\njle loc_1500\nlea r13, [rbp+rdx-1]\nsub eax, 3\nlea rbx, [rbp+rdx+0]\nsub r13, rax\nlea r12, s; \"AEIOUaeiou\"\njmp short loc_14A9\nloc_14A0:\nsub rbx, 1\ncmp rbx, r13\njz short loc_1500\nloc_14A9:\nmovsx esi, byte ptr [rbx]; c\nmov rdi, r12; s\nmov ebp, esi\ncall _strchr\ntest rax, rax\njz short loc_14A0\nmovsx esi, byte ptr [rbx+1]; c\nmov rdi, r12; s\ncall _strchr\ntest rax, rax\njnz short loc_14A0\nmovsx esi, byte ptr [rbx-1]; c\nmov rdi, r12; s\ncall _strchr\ntest rax, rax\njnz short loc_14A0\nloc_14DD:\nmov cs:byte_4011, bpl\nadd rsp, 8\nlea rax, byte_4011\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1500:\nxor ebp, ebp\njmp short loc_14DD", + "ida_strip_pseudo": "char *__fastcall sub_1460(const char *a1)\n{\n int v1; // eax\n __int64 v2; // rdx\n char *v3; // rbx\n __int64 v4; // r13\n char v5; // bp\n\n v1 = strlen(a1);\n v2 = (unsigned int)(v1 - 2);\n if ( v1 - 2 <= 0 )\n {\nLABEL_8:\n v5 = 0;\n }\n else\n {\n v3 = (char *)&a1[v2];\n v4 = (__int64)&a1[v2 - 1 - (unsigned int)(v1 - 3)];\n while ( 1 )\n {\n v5 = *v3;\n if ( strchr(\"AEIOUaeiou\", *v3) )\n {\n if ( !strchr(\"AEIOUaeiou\", v3[1]) && !strchr(\"AEIOUaeiou\", *(v3 - 1)) )\n break;\n }\n if ( --v3 == (char *)v4 )\n goto LABEL_8;\n }\n }\n byte_4011 = v5;\n return &byte_4011;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1460(const char *a1) {\n int v1;\n long long v2;\n char *v3;\n long long v4;\n char v5;\n v1 = strlen(a1);\n v2 = (unsigned int)(v1 - 2);\n if (v1 - 2 <= 0) {\n LABEL_8:\n v5 = 0;\n } else {\n v3 = (char *)&a1[v2];\n v4 = (long long)&a1[v2 - 1 - (unsigned int)(v1 - 3)];\n while (1) {\n v5 = *v3;\n if (strchr(\"AEIOUaeiou\", *v3)) {\n if (!strchr(\"AEIOUaeiou\", v3[1]) && !strchr(\"AEIOUaeiou\", *(v3 - 1)))\n break;\n }\n if (--v3 == (char *)v4) goto LABEL_8;\n }\n }\n byte_4011 = v5;\n return &byte_4011;\n}", + "ida_pseudo_norm": "char *func0(const char *a1) {\n int v1;\n long long v2;\n char *v3;\n long long v4;\n char v5;\n v1 = strlen(a1);\n v2 = (unsigned int)(v1 - 2);\n if (v1 - 2 <= 0) {\n LABEL_8:\n v5 = 0;\n } else {\n v3 = (char *)&a1[v2];\n v4 = (long long)&a1[v2 - 1 - (unsigned int)(v1 - 3)];\n while (1) {\n v5 = *v3;\n if (strchr(\"AEIOUaeiou\", *v3)) {\n if (!strchr(\"AEIOUaeiou\", v3[1]) && !strchr(\"AEIOUaeiou\", *(v3 - 1)))\n break;\n }\n if (--v3 == (char *)v4) goto LABEL_8;\n }\n }\n out_1 = v5;\n return &out_1;\n}" + }, + { + "index": "HumanEval-C-119", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "const char *func0(const char *s1, const char *s2) {\n int count = 0;\n int len1 = strlen(s1);\n int len2 = strlen(s2);\n int i;\n int can = 1;\n for (i = 0; i < len1; i++) {\n if (s1[i] == '(') count++;\n if (s1[i] == ')') count--;\n if (count < 0) can = 0;\n }\n for (i = 0; i < len2; i++) {\n if (s2[i] == '(') count++;\n if (s2[i] == ')') count--;\n if (count < 0) can = 0;\n }\n if (count == 0 && can) return \"Yes\";\n count = 0;\n can = 1;\n for (i = 0; i < len2; i++) {\n if (s2[i] == '(') count++;\n if (s2[i] == ')') count--;\n if (count < 0) can = 0;\n }\n for (i = 0; i < len1; i++) {\n if (s1[i] == '(') count++;\n if (s1[i] == ')') count--;\n if (count < 0) can = 0;\n }\n if (count == 0 && can) return \"Yes\";\n return \"No\";\n}", + "test": "#include \n#include \n\nint main() {\n assert(strcmp(func0(\"()(\", \")\"), \"Yes\") == 0);\n assert(strcmp(func0(\")\", \")\"), \"No\") == 0);\n assert(strcmp(func0(\"(()(())\", \"())())\"), \"No\") == 0);\n assert(strcmp(func0(\")())\", \"(()()(\"), \"Yes\") == 0);\n assert(strcmp(func0(\"(())))\", \"(()())((\"), \"Yes\") == 0);\n assert(strcmp(func0(\"()\", \"())\"), \"No\") == 0);\n assert(strcmp(func0(\"(()(\", \"()))()\"), \"Yes\") == 0);\n assert(strcmp(func0(\"((((\", \"((())\"), \"No\") == 0);\n assert(strcmp(func0(\")(()\", \"(()(\"), \"No\") == 0);\n assert(strcmp(func0(\")(\", \")(\"), \"No\") == 0);\n assert(strcmp(func0(\"(\", \")\"), \"Yes\") == 0);\n assert(strcmp(func0(\")\", \"(\"), \"Yes\") == 0);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov [rbp+var_30], rsi\nmov [rbp+var_14], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_8], eax\nmov rax, [rbp+var_30]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_C], 1\nmov [rbp+var_10], 0\njmp short loc_1213\nloc_11D2:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 28h ; '('\njnz short loc_11EA\nadd [rbp+var_14], 1\nloc_11EA:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 29h ; ')'\njnz short loc_1202\nsub [rbp+var_14], 1\nloc_1202:\ncmp [rbp+var_14], 0\njns short loc_120F\nmov [rbp+var_C], 0\nloc_120F:\nadd [rbp+var_10], 1\nloc_1213:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_8]\njl short loc_11D2\nmov [rbp+var_10], 0\njmp short loc_1265\nloc_1224:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 28h ; '('\njnz short loc_123C\nadd [rbp+var_14], 1\nloc_123C:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 29h ; ')'\njnz short loc_1254\nsub [rbp+var_14], 1\nloc_1254:\ncmp [rbp+var_14], 0\njns short loc_1261\nmov [rbp+var_C], 0\nloc_1261:\nadd [rbp+var_10], 1\nloc_1265:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_4]\njl short loc_1224\ncmp [rbp+var_14], 0\njnz short loc_1285\ncmp [rbp+var_C], 0\njz short loc_1285\nlea rax, s2; \"Yes\"\njmp locret_1353\nloc_1285:\nmov [rbp+var_14], 0\nmov [rbp+var_C], 1\nmov [rbp+var_10], 0\njmp short loc_12DD\nloc_129C:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 28h ; '('\njnz short loc_12B4\nadd [rbp+var_14], 1\nloc_12B4:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 29h ; ')'\njnz short loc_12CC\nsub [rbp+var_14], 1\nloc_12CC:\ncmp [rbp+var_14], 0\njns short loc_12D9\nmov [rbp+var_C], 0\nloc_12D9:\nadd [rbp+var_10], 1\nloc_12DD:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_4]\njl short loc_129C\nmov [rbp+var_10], 0\njmp short loc_132F\nloc_12EE:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 28h ; '('\njnz short loc_1306\nadd [rbp+var_14], 1\nloc_1306:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 29h ; ')'\njnz short loc_131E\nsub [rbp+var_14], 1\nloc_131E:\ncmp [rbp+var_14], 0\njns short loc_132B\nmov [rbp+var_C], 0\nloc_132B:\nadd [rbp+var_10], 1\nloc_132F:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_8]\njl short loc_12EE\ncmp [rbp+var_14], 0\njnz short loc_134C\ncmp [rbp+var_C], 0\njz short loc_134C\nlea rax, s2; \"Yes\"\njmp short locret_1353\nloc_134C:\nlea rax, aNo; \"No\"\nlocret_1353:\nleave\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1, const char *a2)\n{\n int v3; // [rsp+1Ch] [rbp-14h]\n int v4; // [rsp+1Ch] [rbp-14h]\n int i; // [rsp+20h] [rbp-10h]\n int j; // [rsp+20h] [rbp-10h]\n int k; // [rsp+20h] [rbp-10h]\n int m; // [rsp+20h] [rbp-10h]\n int v9; // [rsp+24h] [rbp-Ch]\n int v10; // [rsp+24h] [rbp-Ch]\n int v11; // [rsp+28h] [rbp-8h]\n int v12; // [rsp+2Ch] [rbp-4h]\n\n v3 = 0;\n v11 = strlen(a1);\n v12 = strlen(a2);\n v9 = 1;\n for ( i = 0; i < v11; ++i )\n {\n if ( a1[i] == 40 )\n ++v3;\n if ( a1[i] == 41 )\n --v3;\n if ( v3 < 0 )\n v9 = 0;\n }\n for ( j = 0; j < v12; ++j )\n {\n if ( a2[j] == 40 )\n ++v3;\n if ( a2[j] == 41 )\n --v3;\n if ( v3 < 0 )\n v9 = 0;\n }\n if ( !v3 && v9 )\n return \"Yes\";\n v4 = 0;\n v10 = 1;\n for ( k = 0; k < v12; ++k )\n {\n if ( a2[k] == 40 )\n ++v4;\n if ( a2[k] == 41 )\n --v4;\n if ( v4 < 0 )\n v10 = 0;\n }\n for ( m = 0; m < v11; ++m )\n {\n if ( a1[m] == 40 )\n ++v4;\n if ( a1[m] == 41 )\n --v4;\n if ( v4 < 0 )\n v10 = 0;\n }\n if ( v4 || !v10 )\n return \"No\";\n else\n return \"Yes\";\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov [rbp+var_30], rsi\nmov [rbp+var_14], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_8], eax\nmov rax, [rbp+var_30]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_C], 1\nmov [rbp+var_10], 0\njmp short loc_1213\nloc_11D2:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 28h ; '('\njnz short loc_11EA\nadd [rbp+var_14], 1\nloc_11EA:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 29h ; ')'\njnz short loc_1202\nsub [rbp+var_14], 1\nloc_1202:\ncmp [rbp+var_14], 0\njns short loc_120F\nmov [rbp+var_C], 0\nloc_120F:\nadd [rbp+var_10], 1\nloc_1213:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_8]\njl short loc_11D2\nmov [rbp+var_10], 0\njmp short loc_1265\nloc_1224:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 28h ; '('\njnz short loc_123C\nadd [rbp+var_14], 1\nloc_123C:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 29h ; ')'\njnz short loc_1254\nsub [rbp+var_14], 1\nloc_1254:\ncmp [rbp+var_14], 0\njns short loc_1261\nmov [rbp+var_C], 0\nloc_1261:\nadd [rbp+var_10], 1\nloc_1265:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_4]\njl short loc_1224\ncmp [rbp+var_14], 0\njnz short loc_1285\ncmp [rbp+var_C], 0\njz short loc_1285\nlea rax, s2; \"Yes\"\njmp locret_1353\nloc_1285:\nmov [rbp+var_14], 0\nmov [rbp+var_C], 1\nmov [rbp+var_10], 0\njmp short loc_12DD\nloc_129C:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 28h ; '('\njnz short loc_12B4\nadd [rbp+var_14], 1\nloc_12B4:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 29h ; ')'\njnz short loc_12CC\nsub [rbp+var_14], 1\nloc_12CC:\ncmp [rbp+var_14], 0\njns short loc_12D9\nmov [rbp+var_C], 0\nloc_12D9:\nadd [rbp+var_10], 1\nloc_12DD:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_4]\njl short loc_129C\nmov [rbp+var_10], 0\njmp short loc_132F\nloc_12EE:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 28h ; '('\njnz short loc_1306\nadd [rbp+var_14], 1\nloc_1306:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 29h ; ')'\njnz short loc_131E\nsub [rbp+var_14], 1\nloc_131E:\ncmp [rbp+var_14], 0\njns short loc_132B\nmov [rbp+var_C], 0\nloc_132B:\nadd [rbp+var_10], 1\nloc_132F:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_8]\njl short loc_12EE\ncmp [rbp+var_14], 0\njnz short loc_134C\ncmp [rbp+var_C], 0\njz short loc_134C\nlea rax, s2; \"Yes\"\njmp short locret_1353\nloc_134C:\nlea rax, aNo; \"No\"\nlocret_1353:\nleave\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1189(const char *a1, const char *a2)\n{\n int v3; // [rsp+1Ch] [rbp-14h]\n int v4; // [rsp+1Ch] [rbp-14h]\n int i; // [rsp+20h] [rbp-10h]\n int j; // [rsp+20h] [rbp-10h]\n int k; // [rsp+20h] [rbp-10h]\n int m; // [rsp+20h] [rbp-10h]\n int v9; // [rsp+24h] [rbp-Ch]\n int v10; // [rsp+24h] [rbp-Ch]\n int v11; // [rsp+28h] [rbp-8h]\n int v12; // [rsp+2Ch] [rbp-4h]\n\n v3 = 0;\n v11 = strlen(a1);\n v12 = strlen(a2);\n v9 = 1;\n for ( i = 0; i < v11; ++i )\n {\n if ( a1[i] == 40 )\n ++v3;\n if ( a1[i] == 41 )\n --v3;\n if ( v3 < 0 )\n v9 = 0;\n }\n for ( j = 0; j < v12; ++j )\n {\n if ( a2[j] == 40 )\n ++v3;\n if ( a2[j] == 41 )\n --v3;\n if ( v3 < 0 )\n v9 = 0;\n }\n if ( !v3 && v9 )\n return \"Yes\";\n v4 = 0;\n v10 = 1;\n for ( k = 0; k < v12; ++k )\n {\n if ( a2[k] == 40 )\n ++v4;\n if ( a2[k] == 41 )\n --v4;\n if ( v4 < 0 )\n v10 = 0;\n }\n for ( m = 0; m < v11; ++m )\n {\n if ( a1[m] == 40 )\n ++v4;\n if ( a1[m] == 41 )\n --v4;\n if ( v4 < 0 )\n v10 = 0;\n }\n if ( v4 || !v10 )\n return \"No\";\n else\n return \"Yes\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1189(const char *a1, const char *a2) {\n int v3;\n int v4;\n int i;\n int j;\n int k;\n int m;\n int v9;\n int v10;\n int v11;\n int v12;\n v3 = 0;\n v11 = strlen(a1);\n v12 = strlen(a2);\n v9 = 1;\n for (i = 0; i < v11; ++i) {\n if (a1[i] == 40) ++v3;\n if (a1[i] == 41) --v3;\n if (v3 < 0) v9 = 0;\n }\n for (j = 0; j < v12; ++j) {\n if (a2[j] == 40) ++v3;\n if (a2[j] == 41) --v3;\n if (v3 < 0) v9 = 0;\n }\n if (!v3 && v9) return \"Yes\";\n v4 = 0;\n v10 = 1;\n for (k = 0; k < v12; ++k) {\n if (a2[k] == 40) ++v4;\n if (a2[k] == 41) --v4;\n if (v4 < 0) v10 = 0;\n }\n for (m = 0; m < v11; ++m) {\n if (a1[m] == 40) ++v4;\n if (a1[m] == 41) --v4;\n if (v4 < 0) v10 = 0;\n }\n if (v4 || !v10)\n return \"No\";\n else\n return \"Yes\";\n}", + "ida_pseudo_norm": "const char *func0(const char *a1, const char *a2) {\n int v3;\n int v4;\n int i;\n int j;\n int k;\n int m;\n int v9;\n int v10;\n int v11;\n int v12;\n v3 = 0;\n v11 = strlen(a1);\n v12 = strlen(a2);\n v9 = 1;\n for (i = 0; i < v11; ++i) {\n if (a1[i] == 40) ++v3;\n if (a1[i] == 41) --v3;\n if (v3 < 0) v9 = 0;\n }\n for (j = 0; j < v12; ++j) {\n if (a2[j] == 40) ++v3;\n if (a2[j] == 41) --v3;\n if (v3 < 0) v9 = 0;\n }\n if (!v3 && v9) return \"Yes\";\n v4 = 0;\n v10 = 1;\n for (k = 0; k < v12; ++k) {\n if (a2[k] == 40) ++v4;\n if (a2[k] == 41) --v4;\n if (v4 < 0) v10 = 0;\n }\n for (m = 0; m < v11; ++m) {\n if (a1[m] == 40) ++v4;\n if (a1[m] == 41) --v4;\n if (v4 < 0) v10 = 0;\n }\n if (v4 || !v10)\n return \"No\";\n else\n return \"Yes\";\n}" + }, + { + "index": "HumanEval-C-119", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "const char *func0(const char *s1, const char *s2) {\n int count = 0;\n int len1 = strlen(s1);\n int len2 = strlen(s2);\n int i;\n int can = 1;\n for (i = 0; i < len1; i++) {\n if (s1[i] == '(') count++;\n if (s1[i] == ')') count--;\n if (count < 0) can = 0;\n }\n for (i = 0; i < len2; i++) {\n if (s2[i] == '(') count++;\n if (s2[i] == ')') count--;\n if (count < 0) can = 0;\n }\n if (count == 0 && can) return \"Yes\";\n count = 0;\n can = 1;\n for (i = 0; i < len2; i++) {\n if (s2[i] == '(') count++;\n if (s2[i] == ')') count--;\n if (count < 0) can = 0;\n }\n for (i = 0; i < len1; i++) {\n if (s1[i] == '(') count++;\n if (s1[i] == ')') count--;\n if (count < 0) can = 0;\n }\n if (count == 0 && can) return \"Yes\";\n return \"No\";\n}", + "test": "#include \n#include \n\nint main() {\n assert(strcmp(func0(\"()(\", \")\"), \"Yes\") == 0);\n assert(strcmp(func0(\")\", \")\"), \"No\") == 0);\n assert(strcmp(func0(\"(()(())\", \"())())\"), \"No\") == 0);\n assert(strcmp(func0(\")())\", \"(()()(\"), \"Yes\") == 0);\n assert(strcmp(func0(\"(())))\", \"(()())((\"), \"Yes\") == 0);\n assert(strcmp(func0(\"()\", \"())\"), \"No\") == 0);\n assert(strcmp(func0(\"(()(\", \"()))()\"), \"Yes\") == 0);\n assert(strcmp(func0(\"((((\", \"((())\"), \"No\") == 0);\n assert(strcmp(func0(\")(()\", \"(()(\"), \"No\") == 0);\n assert(strcmp(func0(\")(\", \")(\"), \"No\") == 0);\n assert(strcmp(func0(\"(\", \")\"), \"Yes\") == 0);\n assert(strcmp(func0(\")\", \"(\"), \"Yes\") == 0);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov r13, rsi\ncall _strlen\nmov rbp, rax\nmov r12d, eax\nmov rdi, r13; s\ncall _strlen\nmov r8, rax\nmov edi, eax\ntest ebp, ebp\njle loc_12D5\nmov rcx, rbx\nlea eax, [rbp-1]\nlea r10, [rbx+rax+1]\nmov edx, 1\nmov eax, 0\nmov r9d, 0\njmp short loc_11F7\nloc_11DA:\ncmp sil, 29h ; ')'\nsetz sil\nmovzx esi, sil\nsub eax, esi\nloc_11E8:\ntest eax, eax\ncmovs edx, r9d\nadd rcx, 1\ncmp rcx, r10\njz short loc_1205\nloc_11F7:\nmovzx esi, byte ptr [rcx]\ncmp sil, 28h ; '('\njnz short loc_11DA\nadd eax, 1\njmp short loc_11E8\nloc_1205:\ntest r8d, r8d\njle loc_1320\nloc_120E:\nmov ecx, 0\nmov r9d, 0\njmp short loc_1230\nloc_121B:\nadd eax, 1\nloc_121E:\ntest eax, eax\ncmovs edx, r9d\nadd rcx, 1\ncmp edi, ecx\njle loc_12F1\nloc_1230:\nmovzx esi, byte ptr [r13+rcx+0]\ncmp sil, 28h ; '('\njz short loc_121B\ncmp sil, 29h ; ')'\nsetz sil\nmovzx esi, sil\nsub eax, esi\njmp short loc_121E\nloc_124C:\nadd eax, 1\nloc_124F:\ntest eax, eax\ncmovs edx, edi\nadd rcx, 1\ncmp rcx, r8\njz short loc_1276\nloc_125D:\nmovzx esi, byte ptr [rcx]\ncmp sil, 28h ; '('\njz short loc_124C\ncmp sil, 29h ; ')'\nsetz sil\nmovzx esi, sil\nsub eax, esi\njmp short loc_124F\nloc_1276:\ntest ebp, ebp\njle short loc_12B1\nloc_127A:\nmov ecx, 0\nmov edi, 0\njmp short loc_1297\nloc_1286:\nadd eax, 1\nloc_1289:\ntest eax, eax\ncmovs edx, edi\nadd rcx, 1\ncmp r12d, ecx\njle short loc_12B1\nloc_1297:\nmovzx esi, byte ptr [rbx+rcx]\ncmp sil, 28h ; '('\njz short loc_1286\ncmp sil, 29h ; ')'\nsetz sil\nmovzx esi, sil\nsub eax, esi\njmp short loc_1289\nloc_12B1:\ntest eax, eax\njnz short loc_12C0\nlea rcx, s2; \"Yes\"\ntest edx, edx\njnz short loc_12C7\nloc_12C0:\nlea rcx, aNo; \"No\"\nloc_12C7:\nmov rax, rcx\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_12D5:\nmov edx, 1\nmov eax, 0\nlea rcx, s2; \"Yes\"\ntest r8d, r8d\njg loc_120E\njmp short loc_12C7\nloc_12F1:\ntest edx, edx\njz short loc_1300\nlea rcx, s2; \"Yes\"\ntest eax, eax\njz short loc_12C7\nloc_1300:\nmov rcx, r13\nlea eax, [r8-1]\nlea r8, [r13+rax+1]\nmov edx, 1\nmov eax, 0\nmov edi, 0\njmp loc_125D\nloc_1320:\ntest eax, eax\njnz short loc_132F\nlea rcx, s2; \"Yes\"\ntest edx, edx\njnz short loc_12C7\nloc_132F:\nmov edx, 1\nmov eax, 0\njmp loc_127A", + "ida_pseudo": "const char *__fastcall func0(const char *a1, const char *a2)\n{\n int v3; // ebp\n int v4; // r8d\n const char *v5; // rcx\n int v6; // edx\n int v7; // eax\n __int64 v8; // rcx\n char v9; // si\n int v10; // eax\n int v11; // edx\n const char *v12; // rcx\n __int64 v13; // rcx\n char v14; // si\n const char *v15; // rcx\n __int64 v17; // r8\n\n v3 = strlen(a1);\n v4 = strlen(a2);\n if ( v3 <= 0 )\n {\n v6 = 1;\n v7 = 0;\n v15 = \"Yes\";\n if ( v4 <= 0 )\n return v15;\n }\n else\n {\n v5 = a1;\n v6 = 1;\n v7 = 0;\n do\n {\n if ( *v5 == 40 )\n ++v7;\n else\n v7 -= *v5 == 41;\n if ( v7 < 0 )\n v6 = 0;\n ++v5;\n }\n while ( v5 != &a1[v3 - 1 + 1] );\n if ( v4 <= 0 )\n {\n if ( !v7 )\n {\n v15 = \"Yes\";\n if ( v6 )\n return v15;\n }\n v11 = 1;\n v10 = 0;\nLABEL_24:\n v13 = 0LL;\n do\n {\n v14 = a1[v13];\n if ( v14 == 40 )\n ++v10;\n else\n v10 -= v14 == 41;\n if ( v10 < 0 )\n v11 = 0;\n ++v13;\n }\n while ( v3 > (int)v13 );\nLABEL_31:\n if ( v10 )\n return \"No\";\n v15 = \"Yes\";\n if ( !v11 )\n return \"No\";\n return v15;\n }\n }\n v8 = 0LL;\n do\n {\n v9 = a2[v8];\n if ( v9 == 40 )\n ++v7;\n else\n v7 -= v9 == 41;\n if ( v7 < 0 )\n v6 = 0;\n ++v8;\n }\n while ( v4 > (int)v8 );\n if ( !v6 || (v15 = \"Yes\", v7) )\n {\n v12 = a2;\n v17 = (__int64)&a2[v4 - 1 + 1];\n v11 = 1;\n v10 = 0;\n do\n {\n if ( *v12 == 40 )\n ++v10;\n else\n v10 -= *v12 == 41;\n if ( v10 < 0 )\n v11 = 0;\n ++v12;\n }\n while ( v12 != (const char *)v17 );\n if ( v3 <= 0 )\n goto LABEL_31;\n goto LABEL_24;\n }\n return v15;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov r13, rsi\ncall _strlen\nmov rbp, rax\nmov r12d, eax\nmov rdi, r13; s\ncall _strlen\nmov r8, rax\nmov edi, eax\ntest ebp, ebp\njle loc_12D5\nmov rcx, rbx\nlea eax, [rbp-1]\nlea r10, [rbx+rax+1]\nmov edx, 1\nmov eax, 0\nmov r9d, 0\njmp short loc_11F7\nloc_11DA:\ncmp sil, 29h ; ')'\nsetz sil\nmovzx esi, sil\nsub eax, esi\nloc_11E8:\ntest eax, eax\ncmovs edx, r9d\nadd rcx, 1\ncmp rcx, r10\njz short loc_1205\nloc_11F7:\nmovzx esi, byte ptr [rcx]\ncmp sil, 28h ; '('\njnz short loc_11DA\nadd eax, 1\njmp short loc_11E8\nloc_1205:\ntest r8d, r8d\njle loc_1320\nloc_120E:\nmov ecx, 0\nmov r9d, 0\njmp short loc_1230\nloc_121B:\nadd eax, 1\nloc_121E:\ntest eax, eax\ncmovs edx, r9d\nadd rcx, 1\ncmp edi, ecx\njle loc_12F1\nloc_1230:\nmovzx esi, byte ptr [r13+rcx+0]\ncmp sil, 28h ; '('\njz short loc_121B\ncmp sil, 29h ; ')'\nsetz sil\nmovzx esi, sil\nsub eax, esi\njmp short loc_121E\nloc_124C:\nadd eax, 1\nloc_124F:\ntest eax, eax\ncmovs edx, edi\nadd rcx, 1\ncmp rcx, r8\njz short loc_1276\nloc_125D:\nmovzx esi, byte ptr [rcx]\ncmp sil, 28h ; '('\njz short loc_124C\ncmp sil, 29h ; ')'\nsetz sil\nmovzx esi, sil\nsub eax, esi\njmp short loc_124F\nloc_1276:\ntest ebp, ebp\njle short loc_12B1\nloc_127A:\nmov ecx, 0\nmov edi, 0\njmp short loc_1297\nloc_1286:\nadd eax, 1\nloc_1289:\ntest eax, eax\ncmovs edx, edi\nadd rcx, 1\ncmp r12d, ecx\njle short loc_12B1\nloc_1297:\nmovzx esi, byte ptr [rbx+rcx]\ncmp sil, 28h ; '('\njz short loc_1286\ncmp sil, 29h ; ')'\nsetz sil\nmovzx esi, sil\nsub eax, esi\njmp short loc_1289\nloc_12B1:\ntest eax, eax\njnz short loc_12C0\nlea rcx, s2; \"Yes\"\ntest edx, edx\njnz short loc_12C7\nloc_12C0:\nlea rcx, aNo; \"No\"\nloc_12C7:\nmov rax, rcx\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_12D5:\nmov edx, 1\nmov eax, 0\nlea rcx, s2; \"Yes\"\ntest r8d, r8d\njg loc_120E\njmp short loc_12C7\nloc_12F1:\ntest edx, edx\njz short loc_1300\nlea rcx, s2; \"Yes\"\ntest eax, eax\njz short loc_12C7\nloc_1300:\nmov rcx, r13\nlea eax, [r8-1]\nlea r8, [r13+rax+1]\nmov edx, 1\nmov eax, 0\nmov edi, 0\njmp loc_125D\nloc_1320:\ntest eax, eax\njnz short loc_132F\nlea rcx, s2; \"Yes\"\ntest edx, edx\njnz short loc_12C7\nloc_132F:\nmov edx, 1\nmov eax, 0\njmp loc_127A", + "ida_strip_pseudo": "const char *__fastcall sub_1189(const char *a1, const char *a2)\n{\n int v3; // ebp\n int v4; // r8d\n const char *v5; // rcx\n int v6; // edx\n int v7; // eax\n __int64 v8; // rcx\n char v9; // si\n int v10; // eax\n int v11; // edx\n const char *v12; // rcx\n __int64 v13; // rcx\n char v14; // si\n const char *v15; // rcx\n __int64 v17; // r8\n\n v3 = strlen(a1);\n v4 = strlen(a2);\n if ( v3 <= 0 )\n {\n v6 = 1;\n v7 = 0;\n v15 = \"Yes\";\n if ( v4 <= 0 )\n return v15;\n }\n else\n {\n v5 = a1;\n v6 = 1;\n v7 = 0;\n do\n {\n if ( *v5 == 40 )\n ++v7;\n else\n v7 -= *v5 == 41;\n if ( v7 < 0 )\n v6 = 0;\n ++v5;\n }\n while ( v5 != &a1[v3 - 1 + 1] );\n if ( v4 <= 0 )\n {\n if ( !v7 )\n {\n v15 = \"Yes\";\n if ( v6 )\n return v15;\n }\n v11 = 1;\n v10 = 0;\nLABEL_24:\n v13 = 0LL;\n do\n {\n v14 = a1[v13];\n if ( v14 == 40 )\n ++v10;\n else\n v10 -= v14 == 41;\n if ( v10 < 0 )\n v11 = 0;\n ++v13;\n }\n while ( v3 > (int)v13 );\nLABEL_31:\n if ( v10 )\n return \"No\";\n v15 = \"Yes\";\n if ( !v11 )\n return \"No\";\n return v15;\n }\n }\n v8 = 0LL;\n do\n {\n v9 = a2[v8];\n if ( v9 == 40 )\n ++v7;\n else\n v7 -= v9 == 41;\n if ( v7 < 0 )\n v6 = 0;\n ++v8;\n }\n while ( v4 > (int)v8 );\n if ( !v6 || (v15 = \"Yes\", v7) )\n {\n v12 = a2;\n v17 = (__int64)&a2[v4 - 1 + 1];\n v11 = 1;\n v10 = 0;\n do\n {\n if ( *v12 == 40 )\n ++v10;\n else\n v10 -= *v12 == 41;\n if ( v10 < 0 )\n v11 = 0;\n ++v12;\n }\n while ( v12 != (const char *)v17 );\n if ( v3 <= 0 )\n goto LABEL_31;\n goto LABEL_24;\n }\n return v15;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1189(const char *a1, const char *a2) {\n int v3;\n int v4;\n const char *v5;\n int v6;\n int v7;\n long long v8;\n char v9;\n int v10;\n int v11;\n const char *v12;\n long long v13;\n char v14;\n const char *v15;\n long long v17;\n v3 = strlen(a1);\n v4 = strlen(a2);\n if (v3 <= 0) {\n v6 = 1;\n v7 = 0;\n v15 = \"Yes\";\n if (v4 <= 0) return v15;\n } else {\n v5 = a1;\n v6 = 1;\n v7 = 0;\n do {\n if (*v5 == 40)\n ++v7;\n else\n v7 -= *v5 == 41;\n if (v7 < 0) v6 = 0;\n ++v5;\n } while (v5 != &a1[v3 - 1 + 1]);\n if (v4 <= 0) {\n if (!v7) {\n v15 = \"Yes\";\n if (v6) return v15;\n }\n v11 = 1;\n v10 = 0;\n LABEL_24:\n v13 = 0LL;\n do {\n v14 = a1[v13];\n if (v14 == 40)\n ++v10;\n else\n v10 -= v14 == 41;\n if (v10 < 0) v11 = 0;\n ++v13;\n } while (v3 > (int)v13);\n LABEL_31:\n if (v10) return \"No\";\n v15 = \"Yes\";\n if (!v11) return \"No\";\n return v15;\n }\n }\n v8 = 0LL;\n do {\n v9 = a2[v8];\n if (v9 == 40)\n ++v7;\n else\n v7 -= v9 == 41;\n if (v7 < 0) v6 = 0;\n ++v8;\n } while (v4 > (int)v8);\n if (!v6 || (v15 = \"Yes\", v7)) {\n v12 = a2;\n v17 = (long long)&a2[v4 - 1 + 1];\n v11 = 1;\n v10 = 0;\n do {\n if (*v12 == 40)\n ++v10;\n else\n v10 -= *v12 == 41;\n if (v10 < 0) v11 = 0;\n ++v12;\n } while (v12 != (const char *)v17);\n if (v3 <= 0) goto LABEL_31;\n goto LABEL_24;\n }\n return v15;\n}", + "ida_pseudo_norm": "const char *func0(const char *a1, const char *a2) {\n int v3;\n int v4;\n const char *v5;\n int v6;\n int v7;\n long long v8;\n char v9;\n int v10;\n int v11;\n const char *v12;\n long long v13;\n char v14;\n const char *v15;\n long long v17;\n v3 = strlen(a1);\n v4 = strlen(a2);\n if (v3 <= 0) {\n v6 = 1;\n v7 = 0;\n v15 = \"Yes\";\n if (v4 <= 0) return v15;\n } else {\n v5 = a1;\n v6 = 1;\n v7 = 0;\n do {\n if (*v5 == 40)\n ++v7;\n else\n v7 -= *v5 == 41;\n if (v7 < 0) v6 = 0;\n ++v5;\n } while (v5 != &a1[v3 - 1 + 1]);\n if (v4 <= 0) {\n if (!v7) {\n v15 = \"Yes\";\n if (v6) return v15;\n }\n v11 = 1;\n v10 = 0;\n LABEL_24:\n v13 = 0LL;\n do {\n v14 = a1[v13];\n if (v14 == 40)\n ++v10;\n else\n v10 -= v14 == 41;\n if (v10 < 0) v11 = 0;\n ++v13;\n } while (v3 > (int)v13);\n LABEL_31:\n if (v10) return \"No\";\n v15 = \"Yes\";\n if (!v11) return \"No\";\n return v15;\n }\n }\n v8 = 0LL;\n do {\n v9 = a2[v8];\n if (v9 == 40)\n ++v7;\n else\n v7 -= v9 == 41;\n if (v7 < 0) v6 = 0;\n ++v8;\n } while (v4 > (int)v8);\n if (!v6 || (v15 = \"Yes\", v7)) {\n v12 = a2;\n v17 = (long long)&a2[v4 - 1 + 1];\n v11 = 1;\n v10 = 0;\n do {\n if (*v12 == 40)\n ++v10;\n else\n v10 -= *v12 == 41;\n if (v10 < 0) v11 = 0;\n ++v12;\n } while (v12 != (const char *)v17);\n if (v3 <= 0) goto LABEL_31;\n goto LABEL_24;\n }\n return v15;\n}" + }, + { + "index": "HumanEval-C-119", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "const char *func0(const char *s1, const char *s2) {\n int count = 0;\n int len1 = strlen(s1);\n int len2 = strlen(s2);\n int i;\n int can = 1;\n for (i = 0; i < len1; i++) {\n if (s1[i] == '(') count++;\n if (s1[i] == ')') count--;\n if (count < 0) can = 0;\n }\n for (i = 0; i < len2; i++) {\n if (s2[i] == '(') count++;\n if (s2[i] == ')') count--;\n if (count < 0) can = 0;\n }\n if (count == 0 && can) return \"Yes\";\n count = 0;\n can = 1;\n for (i = 0; i < len2; i++) {\n if (s2[i] == '(') count++;\n if (s2[i] == ')') count--;\n if (count < 0) can = 0;\n }\n for (i = 0; i < len1; i++) {\n if (s1[i] == '(') count++;\n if (s1[i] == ')') count--;\n if (count < 0) can = 0;\n }\n if (count == 0 && can) return \"Yes\";\n return \"No\";\n}", + "test": "#include \n#include \n\nint main() {\n assert(strcmp(func0(\"()(\", \")\"), \"Yes\") == 0);\n assert(strcmp(func0(\")\", \")\"), \"No\") == 0);\n assert(strcmp(func0(\"(()(())\", \"())())\"), \"No\") == 0);\n assert(strcmp(func0(\")())\", \"(()()(\"), \"Yes\") == 0);\n assert(strcmp(func0(\"(())))\", \"(()())((\"), \"Yes\") == 0);\n assert(strcmp(func0(\"()\", \"())\"), \"No\") == 0);\n assert(strcmp(func0(\"(()(\", \"()))()\"), \"Yes\") == 0);\n assert(strcmp(func0(\"((((\", \"((())\"), \"No\") == 0);\n assert(strcmp(func0(\")(()\", \"(()(\"), \"No\") == 0);\n assert(strcmp(func0(\")(\", \")(\"), \"No\") == 0);\n assert(strcmp(func0(\"(\", \")\"), \"Yes\") == 0);\n assert(strcmp(func0(\")\", \"(\"), \"Yes\") == 0);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nmov rbx, rsi\nsub rsp, 8\ncall _strlen\nmov rdi, rbx; s\nmov r13, rax\nmov r12d, eax\ncall _strlen\nmov r8d, eax\ntest r13d, r13d\njle loc_1680\nlea edx, [r13-1]\nmov rsi, rbp\nmov ecx, 1\nxor r9d, r9d\nlea r10, [rbp+rdx+1]\nxor edx, edx\njmp short loc_153D\nloc_1520:\ncmp dil, 29h ; ')'\nsetz dil\nmovzx edi, dil\nsub edx, edi\ntest edx, edx\ncmovs ecx, r9d\nadd rsi, 1\ncmp r10, rsi\njz short loc_1558\nloc_153D:\nmovzx edi, byte ptr [rsi]\ncmp dil, 28h ; '('\njnz short loc_1520\nadd edx, 1\ntest edx, edx\ncmovs ecx, r9d\nadd rsi, 1\ncmp r10, rsi\njnz short loc_153D\nloc_1558:\ntest eax, eax\njle loc_16A0\nloc_1560:\nxor eax, eax\nxor edi, edi\njmp short loc_158C\nloc_1570:\ncmp sil, 29h ; ')'\nsetz sil\nmovzx esi, sil\nsub edx, esi\ntest edx, edx\ncmovs ecx, edi\nadd rax, 1\ncmp r8d, eax\njle short loc_15A7\nloc_158C:\nmovzx esi, byte ptr [rbx+rax]\ncmp sil, 28h ; '('\njnz short loc_1570\nadd edx, 1\ntest edx, edx\ncmovs ecx, edi\nadd rax, 1\ncmp r8d, eax\njg short loc_158C\nloc_15A7:\ntest edx, edx\njnz short loc_15C8\nand ecx, 1\nlea rax, s2; \"Yes\"\njz short loc_15C8\nloc_15B7:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_15C8:\nxor ecx, ecx\nmov edx, 1\nxor eax, eax\nxor edi, edi\njmp short loc_15F4\nloc_15D8:\ncmp sil, 29h ; ')'\nsetz sil\nmovzx esi, sil\nsub eax, esi\ntest eax, eax\ncmovs edx, edi\nadd rcx, 1\ncmp r8d, ecx\njle short loc_160F\nloc_15F4:\nmovzx esi, byte ptr [rbx+rcx]\ncmp sil, 28h ; '('\njnz short loc_15D8\nadd eax, 1\ntest eax, eax\ncmovs edx, edi\nadd rcx, 1\ncmp r8d, ecx\njg short loc_15F4\nloc_160F:\ntest r13d, r13d\njle short loc_1658\nloc_1614:\nxor ecx, ecx\nxor edi, edi\njmp short loc_163C\nloc_1620:\ncmp sil, 29h ; ')'\nsetz sil\nmovzx esi, sil\nsub eax, esi\ntest eax, eax\ncmovs edx, edi\nadd rcx, 1\ncmp r12d, ecx\njle short loc_1658\nloc_163C:\nmovzx esi, byte ptr [rbp+rcx+0]\ncmp sil, 28h ; '('\njnz short loc_1620\nadd eax, 1\ntest eax, eax\ncmovs edx, edi\nadd rcx, 1\ncmp r12d, ecx\njg short loc_163C\nloc_1658:\ntest eax, eax\njnz short loc_166C\nand edx, 1\nlea rax, s2; \"Yes\"\njnz loc_15B7\nloc_166C:\nadd rsp, 8\nlea rax, aNo; \"No\"\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1680:\nmov ecx, 1\nxor edx, edx\ntest eax, eax\njg loc_1560\nlea rax, s2; \"Yes\"\njmp loc_15B7\nloc_16A0:\ntest edx, edx\njnz short loc_16B4\nand ecx, 1\nlea rax, s2; \"Yes\"\njnz loc_15B7\nloc_16B4:\nmov edx, 1\nxor eax, eax\njmp loc_1614", + "ida_pseudo": "const char *__fastcall func0(const char *a1, const char *a2)\n{\n int v3; // r13d\n int v4; // eax\n int v5; // r8d\n const char *v6; // rsi\n char v7; // cl\n __int64 v8; // r10\n int v9; // edx\n __int64 v10; // rax\n char v11; // si\n const char *result; // rax\n __int64 v13; // rcx\n char v14; // dl\n int v15; // eax\n char v16; // si\n __int64 v17; // rcx\n char v18; // si\n\n v3 = strlen(a1);\n v4 = strlen(a2);\n v5 = v4;\n if ( v3 <= 0 )\n {\n v7 = 1;\n v9 = 0;\n if ( v4 <= 0 )\n return \"Yes\";\n }\n else\n {\n v6 = a1;\n v7 = 1;\n v8 = (__int64)&a1[v3 - 1 + 1];\n v9 = 0;\n do\n {\n while ( *v6 == 40 )\n {\n if ( ++v9 < 0 )\n v7 = 0;\n if ( (const char *)v8 == ++v6 )\n goto LABEL_10;\n }\n v9 -= *v6 == 41;\n if ( v9 < 0 )\n v7 = 0;\n ++v6;\n }\n while ( (const char *)v8 != v6 );\nLABEL_10:\n if ( v4 <= 0 )\n {\n if ( !v9 )\n {\n result = \"Yes\";\n if ( (v7 & 1) != 0 )\n return result;\n }\n v14 = 1;\n v15 = 0;\nLABEL_31:\n v17 = 0LL;\n do\n {\n while ( 1 )\n {\n v18 = a1[v17];\n if ( v18 != 40 )\n break;\n if ( ++v15 < 0 )\n v14 = 0;\n if ( v3 <= (int)++v17 )\n goto LABEL_39;\n }\n v15 -= v18 == 41;\n if ( v15 < 0 )\n v14 = 0;\n ++v17;\n }\n while ( v3 > (int)v17 );\nLABEL_39:\n if ( v15 )\n return \"No\";\n result = \"Yes\";\n if ( (v14 & 1) == 0 )\n return \"No\";\n return result;\n }\n }\n v10 = 0LL;\n do\n {\n while ( 1 )\n {\n v11 = a2[v10];\n if ( v11 != 40 )\n break;\n if ( ++v9 < 0 )\n v7 = 0;\n if ( v5 <= (int)++v10 )\n goto LABEL_19;\n }\n v9 -= v11 == 41;\n if ( v9 < 0 )\n v7 = 0;\n ++v10;\n }\n while ( v5 > (int)v10 );\nLABEL_19:\n if ( v9 || (result = \"Yes\", (v7 & 1) == 0) )\n {\n v13 = 0LL;\n v14 = 1;\n v15 = 0;\n do\n {\n while ( 1 )\n {\n v16 = a2[v13];\n if ( v16 != 40 )\n break;\n if ( ++v15 < 0 )\n v14 = 0;\n if ( v5 <= (int)++v13 )\n goto LABEL_30;\n }\n v15 -= v16 == 41;\n if ( v15 < 0 )\n v14 = 0;\n ++v13;\n }\n while ( v5 > (int)v13 );\nLABEL_30:\n if ( v3 <= 0 )\n goto LABEL_39;\n goto LABEL_31;\n }\n return result;\n}", + "ida_strip_asm": "sub_14D0:\nendbr64\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nmov rbx, rsi\nsub rsp, 8\ncall _strlen\nmov rdi, rbx; s\nmov r13, rax\nmov r12d, eax\ncall _strlen\nmov r8d, eax\ntest r13d, r13d\njle loc_1680\nlea edx, [r13-1]\nmov rsi, rbp\nmov ecx, 1\nxor r9d, r9d\nlea r10, [rbp+rdx+1]\nxor edx, edx\njmp short loc_153D\nloc_1520:\ncmp dil, 29h ; ')'\nsetz dil\nmovzx edi, dil\nsub edx, edi\ntest edx, edx\ncmovs ecx, r9d\nadd rsi, 1\ncmp r10, rsi\njz short loc_1558\nloc_153D:\nmovzx edi, byte ptr [rsi]\ncmp dil, 28h ; '('\njnz short loc_1520\nadd edx, 1\ntest edx, edx\ncmovs ecx, r9d\nadd rsi, 1\ncmp r10, rsi\njnz short loc_153D\nloc_1558:\ntest eax, eax\njle loc_16A0\nloc_1560:\nxor eax, eax\nxor edi, edi\njmp short loc_158C\nloc_1570:\ncmp sil, 29h ; ')'\nsetz sil\nmovzx esi, sil\nsub edx, esi\ntest edx, edx\ncmovs ecx, edi\nadd rax, 1\ncmp r8d, eax\njle short loc_15A7\nloc_158C:\nmovzx esi, byte ptr [rbx+rax]\ncmp sil, 28h ; '('\njnz short loc_1570\nadd edx, 1\ntest edx, edx\ncmovs ecx, edi\nadd rax, 1\ncmp r8d, eax\njg short loc_158C\nloc_15A7:\ntest edx, edx\njnz short loc_15C8\nand ecx, 1\nlea rax, s2; \"Yes\"\njz short loc_15C8\nloc_15B7:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_15C8:\nxor ecx, ecx\nmov edx, 1\nxor eax, eax\nxor edi, edi\njmp short loc_15F4\nloc_15D8:\ncmp sil, 29h ; ')'\nsetz sil\nmovzx esi, sil\nsub eax, esi\ntest eax, eax\ncmovs edx, edi\nadd rcx, 1\ncmp r8d, ecx\njle short loc_160F\nloc_15F4:\nmovzx esi, byte ptr [rbx+rcx]\ncmp sil, 28h ; '('\njnz short loc_15D8\nadd eax, 1\ntest eax, eax\ncmovs edx, edi\nadd rcx, 1\ncmp r8d, ecx\njg short loc_15F4\nloc_160F:\ntest r13d, r13d\njle short loc_1658\nloc_1614:\nxor ecx, ecx\nxor edi, edi\njmp short loc_163C\nloc_1620:\ncmp sil, 29h ; ')'\nsetz sil\nmovzx esi, sil\nsub eax, esi\ntest eax, eax\ncmovs edx, edi\nadd rcx, 1\ncmp r12d, ecx\njle short loc_1658\nloc_163C:\nmovzx esi, byte ptr [rbp+rcx+0]\ncmp sil, 28h ; '('\njnz short loc_1620\nadd eax, 1\ntest eax, eax\ncmovs edx, edi\nadd rcx, 1\ncmp r12d, ecx\njg short loc_163C\nloc_1658:\ntest eax, eax\njnz short loc_166C\nand edx, 1\nlea rax, s2; \"Yes\"\njnz loc_15B7\nloc_166C:\nadd rsp, 8\nlea rax, aNo; \"No\"\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1680:\nmov ecx, 1\nxor edx, edx\ntest eax, eax\njg loc_1560\nlea rax, s2; \"Yes\"\njmp loc_15B7\nloc_16A0:\ntest edx, edx\njnz short loc_16B4\nand ecx, 1\nlea rax, s2; \"Yes\"\njnz loc_15B7\nloc_16B4:\nmov edx, 1\nxor eax, eax\njmp loc_1614", + "ida_strip_pseudo": "const char *__fastcall sub_14D0(const char *a1, const char *a2)\n{\n int v3; // r13d\n int v4; // eax\n int v5; // r8d\n const char *v6; // rsi\n char v7; // cl\n __int64 v8; // r10\n int v9; // edx\n __int64 v10; // rax\n char v11; // si\n const char *result; // rax\n __int64 v13; // rcx\n char v14; // dl\n int v15; // eax\n char v16; // si\n __int64 v17; // rcx\n char v18; // si\n\n v3 = strlen(a1);\n v4 = strlen(a2);\n v5 = v4;\n if ( v3 <= 0 )\n {\n v7 = 1;\n v9 = 0;\n if ( v4 <= 0 )\n return \"Yes\";\n }\n else\n {\n v6 = a1;\n v7 = 1;\n v8 = (__int64)&a1[v3 - 1 + 1];\n v9 = 0;\n do\n {\n while ( *v6 == 40 )\n {\n if ( ++v9 < 0 )\n v7 = 0;\n if ( (const char *)v8 == ++v6 )\n goto LABEL_10;\n }\n v9 -= *v6 == 41;\n if ( v9 < 0 )\n v7 = 0;\n ++v6;\n }\n while ( (const char *)v8 != v6 );\nLABEL_10:\n if ( v4 <= 0 )\n {\n if ( !v9 )\n {\n result = \"Yes\";\n if ( (v7 & 1) != 0 )\n return result;\n }\n v14 = 1;\n v15 = 0;\nLABEL_31:\n v17 = 0LL;\n do\n {\n while ( 1 )\n {\n v18 = a1[v17];\n if ( v18 != 40 )\n break;\n if ( ++v15 < 0 )\n v14 = 0;\n if ( v3 <= (int)++v17 )\n goto LABEL_39;\n }\n v15 -= v18 == 41;\n if ( v15 < 0 )\n v14 = 0;\n ++v17;\n }\n while ( v3 > (int)v17 );\nLABEL_39:\n if ( v15 )\n return \"No\";\n result = \"Yes\";\n if ( (v14 & 1) == 0 )\n return \"No\";\n return result;\n }\n }\n v10 = 0LL;\n do\n {\n while ( 1 )\n {\n v11 = a2[v10];\n if ( v11 != 40 )\n break;\n if ( ++v9 < 0 )\n v7 = 0;\n if ( v5 <= (int)++v10 )\n goto LABEL_19;\n }\n v9 -= v11 == 41;\n if ( v9 < 0 )\n v7 = 0;\n ++v10;\n }\n while ( v5 > (int)v10 );\nLABEL_19:\n if ( v9 || (result = \"Yes\", (v7 & 1) == 0) )\n {\n v13 = 0LL;\n v14 = 1;\n v15 = 0;\n do\n {\n while ( 1 )\n {\n v16 = a2[v13];\n if ( v16 != 40 )\n break;\n if ( ++v15 < 0 )\n v14 = 0;\n if ( v5 <= (int)++v13 )\n goto LABEL_30;\n }\n v15 -= v16 == 41;\n if ( v15 < 0 )\n v14 = 0;\n ++v13;\n }\n while ( v5 > (int)v13 );\nLABEL_30:\n if ( v3 <= 0 )\n goto LABEL_39;\n goto LABEL_31;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_14D0(const char *a1, const char *a2) {\n int v3;\n int v4;\n int v5;\n const char *v6;\n char v7;\n long long v8;\n int v9;\n long long v10;\n char v11;\n const char *result;\n long long v13;\n char v14;\n int v15;\n char v16;\n long long v17;\n char v18;\n v3 = strlen(a1);\n v4 = strlen(a2);\n v5 = v4;\n if (v3 <= 0) {\n v7 = 1;\n v9 = 0;\n if (v4 <= 0) return \"Yes\";\n } else {\n v6 = a1;\n v7 = 1;\n v8 = (long long)&a1[v3 - 1 + 1];\n v9 = 0;\n do {\n while (*v6 == 40) {\n if (++v9 < 0) v7 = 0;\n if ((const char *)v8 == ++v6) goto LABEL_10;\n }\n v9 -= *v6 == 41;\n if (v9 < 0) v7 = 0;\n ++v6;\n } while ((const char *)v8 != v6);\n LABEL_10:\n if (v4 <= 0) {\n if (!v9) {\n result = \"Yes\";\n if ((v7 & 1) != 0) return result;\n }\n v14 = 1;\n v15 = 0;\n LABEL_31:\n v17 = 0LL;\n do {\n while (1) {\n v18 = a1[v17];\n if (v18 != 40) break;\n if (++v15 < 0) v14 = 0;\n if (v3 <= (int)++v17) goto LABEL_39;\n }\n v15 -= v18 == 41;\n if (v15 < 0) v14 = 0;\n ++v17;\n } while (v3 > (int)v17);\n LABEL_39:\n if (v15) return \"No\";\n result = \"Yes\";\n if ((v14 & 1) == 0) return \"No\";\n return result;\n }\n }\n v10 = 0LL;\n do {\n while (1) {\n v11 = a2[v10];\n if (v11 != 40) break;\n if (++v9 < 0) v7 = 0;\n if (v5 <= (int)++v10) goto LABEL_19;\n }\n v9 -= v11 == 41;\n if (v9 < 0) v7 = 0;\n ++v10;\n } while (v5 > (int)v10);\nLABEL_19:\n if (v9 || (result = \"Yes\", (v7 & 1) == 0)) {\n v13 = 0LL;\n v14 = 1;\n v15 = 0;\n do {\n while (1) {\n v16 = a2[v13];\n if (v16 != 40) break;\n if (++v15 < 0) v14 = 0;\n if (v5 <= (int)++v13) goto LABEL_30;\n }\n v15 -= v16 == 41;\n if (v15 < 0) v14 = 0;\n ++v13;\n } while (v5 > (int)v13);\n LABEL_30:\n if (v3 <= 0) goto LABEL_39;\n goto LABEL_31;\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(const char *a1, const char *a2) {\n int v3;\n int v4;\n int v5;\n const char *v6;\n char v7;\n long long v8;\n int v9;\n long long v10;\n char v11;\n const char *result;\n long long v13;\n char v14;\n int v15;\n char v16;\n long long v17;\n char v18;\n v3 = strlen(a1);\n v4 = strlen(a2);\n v5 = v4;\n if (v3 <= 0) {\n v7 = 1;\n v9 = 0;\n if (v4 <= 0) return \"Yes\";\n } else {\n v6 = a1;\n v7 = 1;\n v8 = (long long)&a1[v3 - 1 + 1];\n v9 = 0;\n do {\n while (*v6 == 40) {\n if (++v9 < 0) v7 = 0;\n if ((const char *)v8 == ++v6) goto LABEL_10;\n }\n v9 -= *v6 == 41;\n if (v9 < 0) v7 = 0;\n ++v6;\n } while ((const char *)v8 != v6);\n LABEL_10:\n if (v4 <= 0) {\n if (!v9) {\n result = \"Yes\";\n if ((v7 & 1) != 0) return result;\n }\n v14 = 1;\n v15 = 0;\n LABEL_31:\n v17 = 0LL;\n do {\n while (1) {\n v18 = a1[v17];\n if (v18 != 40) break;\n if (++v15 < 0) v14 = 0;\n if (v3 <= (int)++v17) goto LABEL_39;\n }\n v15 -= v18 == 41;\n if (v15 < 0) v14 = 0;\n ++v17;\n } while (v3 > (int)v17);\n LABEL_39:\n if (v15) return \"No\";\n result = \"Yes\";\n if ((v14 & 1) == 0) return \"No\";\n return result;\n }\n }\n v10 = 0LL;\n do {\n while (1) {\n v11 = a2[v10];\n if (v11 != 40) break;\n if (++v9 < 0) v7 = 0;\n if (v5 <= (int)++v10) goto LABEL_19;\n }\n v9 -= v11 == 41;\n if (v9 < 0) v7 = 0;\n ++v10;\n } while (v5 > (int)v10);\nLABEL_19:\n if (v9 || (result = \"Yes\", (v7 & 1) == 0)) {\n v13 = 0LL;\n v14 = 1;\n v15 = 0;\n do {\n while (1) {\n v16 = a2[v13];\n if (v16 != 40) break;\n if (++v15 < 0) v14 = 0;\n if (v5 <= (int)++v13) goto LABEL_30;\n }\n v15 -= v16 == 41;\n if (v15 < 0) v14 = 0;\n ++v13;\n } while (v5 > (int)v13);\n LABEL_30:\n if (v3 <= 0) goto LABEL_39;\n goto LABEL_31;\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-119", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "const char *func0(const char *s1, const char *s2) {\n int count = 0;\n int len1 = strlen(s1);\n int len2 = strlen(s2);\n int i;\n int can = 1;\n for (i = 0; i < len1; i++) {\n if (s1[i] == '(') count++;\n if (s1[i] == ')') count--;\n if (count < 0) can = 0;\n }\n for (i = 0; i < len2; i++) {\n if (s2[i] == '(') count++;\n if (s2[i] == ')') count--;\n if (count < 0) can = 0;\n }\n if (count == 0 && can) return \"Yes\";\n count = 0;\n can = 1;\n for (i = 0; i < len2; i++) {\n if (s2[i] == '(') count++;\n if (s2[i] == ')') count--;\n if (count < 0) can = 0;\n }\n for (i = 0; i < len1; i++) {\n if (s1[i] == '(') count++;\n if (s1[i] == ')') count--;\n if (count < 0) can = 0;\n }\n if (count == 0 && can) return \"Yes\";\n return \"No\";\n}", + "test": "#include \n#include \n\nint main() {\n assert(strcmp(func0(\"()(\", \")\"), \"Yes\") == 0);\n assert(strcmp(func0(\")\", \")\"), \"No\") == 0);\n assert(strcmp(func0(\"(()(())\", \"())())\"), \"No\") == 0);\n assert(strcmp(func0(\")())\", \"(()()(\"), \"Yes\") == 0);\n assert(strcmp(func0(\"(())))\", \"(()())((\"), \"Yes\") == 0);\n assert(strcmp(func0(\"()\", \"())\"), \"No\") == 0);\n assert(strcmp(func0(\"(()(\", \"()))()\"), \"Yes\") == 0);\n assert(strcmp(func0(\"((((\", \"((())\"), \"No\") == 0);\n assert(strcmp(func0(\")(()\", \"(()(\"), \"No\") == 0);\n assert(strcmp(func0(\")(\", \")(\"), \"No\") == 0);\n assert(strcmp(func0(\"(\", \")\"), \"Yes\") == 0);\n assert(strcmp(func0(\")\", \"(\"), \"Yes\") == 0);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nmov rbx, rsi\nsub rsp, 8\ncall _strlen\nmov rdi, rbx; s\nmov r13, rax\nmov r12d, eax\ncall _strlen\nmov r8d, eax\ntest r13d, r13d\njle loc_1680\nlea edx, [r13-1]\nmov rsi, rbp\nmov ecx, 1\nxor r9d, r9d\nlea r10, [rbp+rdx+1]\nxor edx, edx\njmp short loc_153D\nloc_1520:\ncmp dil, 29h ; ')'\nsetz dil\nmovzx edi, dil\nsub edx, edi\ntest edx, edx\ncmovs ecx, r9d\nadd rsi, 1\ncmp rsi, r10\njz short loc_1558\nloc_153D:\nmovzx edi, byte ptr [rsi]\ncmp dil, 28h ; '('\njnz short loc_1520\nadd edx, 1\ntest edx, edx\ncmovs ecx, r9d\nadd rsi, 1\ncmp rsi, r10\njnz short loc_153D\nloc_1558:\ntest eax, eax\njle loc_16A0\nloc_1560:\nxor eax, eax\nxor edi, edi\njmp short loc_158C\nloc_1570:\ncmp sil, 29h ; ')'\nsetz sil\nmovzx esi, sil\nsub edx, esi\ntest edx, edx\ncmovs ecx, edi\nadd rax, 1\ncmp r8d, eax\njle short loc_15A7\nloc_158C:\nmovzx esi, byte ptr [rbx+rax]\ncmp sil, 28h ; '('\njnz short loc_1570\nadd edx, 1\ntest edx, edx\ncmovs ecx, edi\nadd rax, 1\ncmp r8d, eax\njg short loc_158C\nloc_15A7:\ntest edx, edx\njnz short loc_15C8\nand ecx, 1\nlea rax, s2; \"Yes\"\njz short loc_15C8\nloc_15B7:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_15C8:\nxor ecx, ecx\nmov edx, 1\nxor eax, eax\nxor edi, edi\njmp short loc_15F4\nloc_15D8:\ncmp sil, 29h ; ')'\nsetz sil\nmovzx esi, sil\nsub eax, esi\ntest eax, eax\ncmovs edx, edi\nadd rcx, 1\ncmp r8d, ecx\njle short loc_160F\nloc_15F4:\nmovzx esi, byte ptr [rbx+rcx]\ncmp sil, 28h ; '('\njnz short loc_15D8\nadd eax, 1\ntest eax, eax\ncmovs edx, edi\nadd rcx, 1\ncmp r8d, ecx\njg short loc_15F4\nloc_160F:\ntest r13d, r13d\njle short loc_1658\nloc_1614:\nxor ecx, ecx\nxor edi, edi\njmp short loc_163C\nloc_1620:\ncmp sil, 29h ; ')'\nsetz sil\nmovzx esi, sil\nsub eax, esi\ntest eax, eax\ncmovs edx, edi\nadd rcx, 1\ncmp r12d, ecx\njle short loc_1658\nloc_163C:\nmovzx esi, byte ptr [rbp+rcx+0]\ncmp sil, 28h ; '('\njnz short loc_1620\nadd eax, 1\ntest eax, eax\ncmovs edx, edi\nadd rcx, 1\ncmp r12d, ecx\njg short loc_163C\nloc_1658:\ntest eax, eax\njnz short loc_166C\nand edx, 1\nlea rax, s2; \"Yes\"\njnz loc_15B7\nloc_166C:\nadd rsp, 8\nlea rax, aNo; \"No\"\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1680:\nmov ecx, 1\nxor edx, edx\ntest eax, eax\njg loc_1560\nlea rax, s2; \"Yes\"\njmp loc_15B7\nloc_16A0:\ntest edx, edx\njnz short loc_16B4\nand ecx, 1\nlea rax, s2; \"Yes\"\njnz loc_15B7\nloc_16B4:\nmov edx, 1\nxor eax, eax\njmp loc_1614", + "ida_pseudo": "const char *__fastcall func0(const char *a1, const char *a2)\n{\n int v3; // r13d\n int v4; // eax\n int v5; // r8d\n const char *v6; // rsi\n char v7; // cl\n __int64 v8; // r10\n int v9; // edx\n __int64 v10; // rax\n char v11; // si\n const char *result; // rax\n __int64 v13; // rcx\n char v14; // dl\n int v15; // eax\n char v16; // si\n __int64 v17; // rcx\n char v18; // si\n\n v3 = strlen(a1);\n v4 = strlen(a2);\n v5 = v4;\n if ( v3 <= 0 )\n {\n v7 = 1;\n v9 = 0;\n if ( v4 <= 0 )\n return \"Yes\";\n }\n else\n {\n v6 = a1;\n v7 = 1;\n v8 = (__int64)&a1[v3 - 1 + 1];\n v9 = 0;\n do\n {\n while ( *v6 == 40 )\n {\n if ( ++v9 < 0 )\n v7 = 0;\n if ( ++v6 == (const char *)v8 )\n goto LABEL_10;\n }\n v9 -= *v6 == 41;\n if ( v9 < 0 )\n v7 = 0;\n ++v6;\n }\n while ( v6 != (const char *)v8 );\nLABEL_10:\n if ( v4 <= 0 )\n {\n if ( !v9 )\n {\n result = \"Yes\";\n if ( (v7 & 1) != 0 )\n return result;\n }\n v14 = 1;\n v15 = 0;\nLABEL_31:\n v17 = 0LL;\n do\n {\n while ( 1 )\n {\n v18 = a1[v17];\n if ( v18 != 40 )\n break;\n if ( ++v15 < 0 )\n v14 = 0;\n if ( v3 <= (int)++v17 )\n goto LABEL_39;\n }\n v15 -= v18 == 41;\n if ( v15 < 0 )\n v14 = 0;\n ++v17;\n }\n while ( v3 > (int)v17 );\nLABEL_39:\n if ( v15 )\n return \"No\";\n result = \"Yes\";\n if ( (v14 & 1) == 0 )\n return \"No\";\n return result;\n }\n }\n v10 = 0LL;\n do\n {\n while ( 1 )\n {\n v11 = a2[v10];\n if ( v11 != 40 )\n break;\n if ( ++v9 < 0 )\n v7 = 0;\n if ( v5 <= (int)++v10 )\n goto LABEL_19;\n }\n v9 -= v11 == 41;\n if ( v9 < 0 )\n v7 = 0;\n ++v10;\n }\n while ( v5 > (int)v10 );\nLABEL_19:\n if ( v9 || (result = \"Yes\", (v7 & 1) == 0) )\n {\n v13 = 0LL;\n v14 = 1;\n v15 = 0;\n do\n {\n while ( 1 )\n {\n v16 = a2[v13];\n if ( v16 != 40 )\n break;\n if ( ++v15 < 0 )\n v14 = 0;\n if ( v5 <= (int)++v13 )\n goto LABEL_30;\n }\n v15 -= v16 == 41;\n if ( v15 < 0 )\n v14 = 0;\n ++v13;\n }\n while ( v5 > (int)v13 );\nLABEL_30:\n if ( v3 <= 0 )\n goto LABEL_39;\n goto LABEL_31;\n }\n return result;\n}", + "ida_strip_asm": "sub_14D0:\nendbr64\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nmov rbx, rsi\nsub rsp, 8\ncall _strlen\nmov rdi, rbx; s\nmov r13, rax\nmov r12d, eax\ncall _strlen\nmov r8d, eax\ntest r13d, r13d\njle loc_1680\nlea edx, [r13-1]\nmov rsi, rbp\nmov ecx, 1\nxor r9d, r9d\nlea r10, [rbp+rdx+1]\nxor edx, edx\njmp short loc_153D\nloc_1520:\ncmp dil, 29h ; ')'\nsetz dil\nmovzx edi, dil\nsub edx, edi\ntest edx, edx\ncmovs ecx, r9d\nadd rsi, 1\ncmp rsi, r10\njz short loc_1558\nloc_153D:\nmovzx edi, byte ptr [rsi]\ncmp dil, 28h ; '('\njnz short loc_1520\nadd edx, 1\ntest edx, edx\ncmovs ecx, r9d\nadd rsi, 1\ncmp rsi, r10\njnz short loc_153D\nloc_1558:\ntest eax, eax\njle loc_16A0\nloc_1560:\nxor eax, eax\nxor edi, edi\njmp short loc_158C\nloc_1570:\ncmp sil, 29h ; ')'\nsetz sil\nmovzx esi, sil\nsub edx, esi\ntest edx, edx\ncmovs ecx, edi\nadd rax, 1\ncmp r8d, eax\njle short loc_15A7\nloc_158C:\nmovzx esi, byte ptr [rbx+rax]\ncmp sil, 28h ; '('\njnz short loc_1570\nadd edx, 1\ntest edx, edx\ncmovs ecx, edi\nadd rax, 1\ncmp r8d, eax\njg short loc_158C\nloc_15A7:\ntest edx, edx\njnz short loc_15C8\nand ecx, 1\nlea rax, s2; \"Yes\"\njz short loc_15C8\nloc_15B7:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_15C8:\nxor ecx, ecx\nmov edx, 1\nxor eax, eax\nxor edi, edi\njmp short loc_15F4\nloc_15D8:\ncmp sil, 29h ; ')'\nsetz sil\nmovzx esi, sil\nsub eax, esi\ntest eax, eax\ncmovs edx, edi\nadd rcx, 1\ncmp r8d, ecx\njle short loc_160F\nloc_15F4:\nmovzx esi, byte ptr [rbx+rcx]\ncmp sil, 28h ; '('\njnz short loc_15D8\nadd eax, 1\ntest eax, eax\ncmovs edx, edi\nadd rcx, 1\ncmp r8d, ecx\njg short loc_15F4\nloc_160F:\ntest r13d, r13d\njle short loc_1658\nloc_1614:\nxor ecx, ecx\nxor edi, edi\njmp short loc_163C\nloc_1620:\ncmp sil, 29h ; ')'\nsetz sil\nmovzx esi, sil\nsub eax, esi\ntest eax, eax\ncmovs edx, edi\nadd rcx, 1\ncmp r12d, ecx\njle short loc_1658\nloc_163C:\nmovzx esi, byte ptr [rbp+rcx+0]\ncmp sil, 28h ; '('\njnz short loc_1620\nadd eax, 1\ntest eax, eax\ncmovs edx, edi\nadd rcx, 1\ncmp r12d, ecx\njg short loc_163C\nloc_1658:\ntest eax, eax\njnz short loc_166C\nand edx, 1\nlea rax, s2; \"Yes\"\njnz loc_15B7\nloc_166C:\nadd rsp, 8\nlea rax, aNo; \"No\"\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1680:\nmov ecx, 1\nxor edx, edx\ntest eax, eax\njg loc_1560\nlea rax, s2; \"Yes\"\njmp loc_15B7\nloc_16A0:\ntest edx, edx\njnz short loc_16B4\nand ecx, 1\nlea rax, s2; \"Yes\"\njnz loc_15B7\nloc_16B4:\nmov edx, 1\nxor eax, eax\njmp loc_1614", + "ida_strip_pseudo": "const char *__fastcall sub_14D0(const char *a1, const char *a2)\n{\n int v3; // r13d\n int v4; // eax\n int v5; // r8d\n const char *v6; // rsi\n char v7; // cl\n __int64 v8; // r10\n int v9; // edx\n __int64 v10; // rax\n char v11; // si\n const char *result; // rax\n __int64 v13; // rcx\n char v14; // dl\n int v15; // eax\n char v16; // si\n __int64 v17; // rcx\n char v18; // si\n\n v3 = strlen(a1);\n v4 = strlen(a2);\n v5 = v4;\n if ( v3 <= 0 )\n {\n v7 = 1;\n v9 = 0;\n if ( v4 <= 0 )\n return \"Yes\";\n }\n else\n {\n v6 = a1;\n v7 = 1;\n v8 = (__int64)&a1[v3 - 1 + 1];\n v9 = 0;\n do\n {\n while ( *v6 == 40 )\n {\n if ( ++v9 < 0 )\n v7 = 0;\n if ( ++v6 == (const char *)v8 )\n goto LABEL_10;\n }\n v9 -= *v6 == 41;\n if ( v9 < 0 )\n v7 = 0;\n ++v6;\n }\n while ( v6 != (const char *)v8 );\nLABEL_10:\n if ( v4 <= 0 )\n {\n if ( !v9 )\n {\n result = \"Yes\";\n if ( (v7 & 1) != 0 )\n return result;\n }\n v14 = 1;\n v15 = 0;\nLABEL_31:\n v17 = 0LL;\n do\n {\n while ( 1 )\n {\n v18 = a1[v17];\n if ( v18 != 40 )\n break;\n if ( ++v15 < 0 )\n v14 = 0;\n if ( v3 <= (int)++v17 )\n goto LABEL_39;\n }\n v15 -= v18 == 41;\n if ( v15 < 0 )\n v14 = 0;\n ++v17;\n }\n while ( v3 > (int)v17 );\nLABEL_39:\n if ( v15 )\n return \"No\";\n result = \"Yes\";\n if ( (v14 & 1) == 0 )\n return \"No\";\n return result;\n }\n }\n v10 = 0LL;\n do\n {\n while ( 1 )\n {\n v11 = a2[v10];\n if ( v11 != 40 )\n break;\n if ( ++v9 < 0 )\n v7 = 0;\n if ( v5 <= (int)++v10 )\n goto LABEL_19;\n }\n v9 -= v11 == 41;\n if ( v9 < 0 )\n v7 = 0;\n ++v10;\n }\n while ( v5 > (int)v10 );\nLABEL_19:\n if ( v9 || (result = \"Yes\", (v7 & 1) == 0) )\n {\n v13 = 0LL;\n v14 = 1;\n v15 = 0;\n do\n {\n while ( 1 )\n {\n v16 = a2[v13];\n if ( v16 != 40 )\n break;\n if ( ++v15 < 0 )\n v14 = 0;\n if ( v5 <= (int)++v13 )\n goto LABEL_30;\n }\n v15 -= v16 == 41;\n if ( v15 < 0 )\n v14 = 0;\n ++v13;\n }\n while ( v5 > (int)v13 );\nLABEL_30:\n if ( v3 <= 0 )\n goto LABEL_39;\n goto LABEL_31;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_14D0(const char *a1, const char *a2) {\n int v3;\n int v4;\n int v5;\n const char *v6;\n char v7;\n long long v8;\n int v9;\n long long v10;\n char v11;\n const char *result;\n long long v13;\n char v14;\n int v15;\n char v16;\n long long v17;\n char v18;\n v3 = strlen(a1);\n v4 = strlen(a2);\n v5 = v4;\n if (v3 <= 0) {\n v7 = 1;\n v9 = 0;\n if (v4 <= 0) return \"Yes\";\n } else {\n v6 = a1;\n v7 = 1;\n v8 = (long long)&a1[v3 - 1 + 1];\n v9 = 0;\n do {\n while (*v6 == 40) {\n if (++v9 < 0) v7 = 0;\n if (++v6 == (const char *)v8) goto LABEL_10;\n }\n v9 -= *v6 == 41;\n if (v9 < 0) v7 = 0;\n ++v6;\n } while (v6 != (const char *)v8);\n LABEL_10:\n if (v4 <= 0) {\n if (!v9) {\n result = \"Yes\";\n if ((v7 & 1) != 0) return result;\n }\n v14 = 1;\n v15 = 0;\n LABEL_31:\n v17 = 0LL;\n do {\n while (1) {\n v18 = a1[v17];\n if (v18 != 40) break;\n if (++v15 < 0) v14 = 0;\n if (v3 <= (int)++v17) goto LABEL_39;\n }\n v15 -= v18 == 41;\n if (v15 < 0) v14 = 0;\n ++v17;\n } while (v3 > (int)v17);\n LABEL_39:\n if (v15) return \"No\";\n result = \"Yes\";\n if ((v14 & 1) == 0) return \"No\";\n return result;\n }\n }\n v10 = 0LL;\n do {\n while (1) {\n v11 = a2[v10];\n if (v11 != 40) break;\n if (++v9 < 0) v7 = 0;\n if (v5 <= (int)++v10) goto LABEL_19;\n }\n v9 -= v11 == 41;\n if (v9 < 0) v7 = 0;\n ++v10;\n } while (v5 > (int)v10);\nLABEL_19:\n if (v9 || (result = \"Yes\", (v7 & 1) == 0)) {\n v13 = 0LL;\n v14 = 1;\n v15 = 0;\n do {\n while (1) {\n v16 = a2[v13];\n if (v16 != 40) break;\n if (++v15 < 0) v14 = 0;\n if (v5 <= (int)++v13) goto LABEL_30;\n }\n v15 -= v16 == 41;\n if (v15 < 0) v14 = 0;\n ++v13;\n } while (v5 > (int)v13);\n LABEL_30:\n if (v3 <= 0) goto LABEL_39;\n goto LABEL_31;\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(const char *a1, const char *a2) {\n int v3;\n int v4;\n int v5;\n const char *v6;\n char v7;\n long long v8;\n int v9;\n long long v10;\n char v11;\n const char *result;\n long long v13;\n char v14;\n int v15;\n char v16;\n long long v17;\n char v18;\n v3 = strlen(a1);\n v4 = strlen(a2);\n v5 = v4;\n if (v3 <= 0) {\n v7 = 1;\n v9 = 0;\n if (v4 <= 0) return \"Yes\";\n } else {\n v6 = a1;\n v7 = 1;\n v8 = (long long)&a1[v3 - 1 + 1];\n v9 = 0;\n do {\n while (*v6 == 40) {\n if (++v9 < 0) v7 = 0;\n if (++v6 == (const char *)v8) goto LABEL_10;\n }\n v9 -= *v6 == 41;\n if (v9 < 0) v7 = 0;\n ++v6;\n } while (v6 != (const char *)v8);\n LABEL_10:\n if (v4 <= 0) {\n if (!v9) {\n result = \"Yes\";\n if ((v7 & 1) != 0) return result;\n }\n v14 = 1;\n v15 = 0;\n LABEL_31:\n v17 = 0LL;\n do {\n while (1) {\n v18 = a1[v17];\n if (v18 != 40) break;\n if (++v15 < 0) v14 = 0;\n if (v3 <= (int)++v17) goto LABEL_39;\n }\n v15 -= v18 == 41;\n if (v15 < 0) v14 = 0;\n ++v17;\n } while (v3 > (int)v17);\n LABEL_39:\n if (v15) return \"No\";\n result = \"Yes\";\n if ((v14 & 1) == 0) return \"No\";\n return result;\n }\n }\n v10 = 0LL;\n do {\n while (1) {\n v11 = a2[v10];\n if (v11 != 40) break;\n if (++v9 < 0) v7 = 0;\n if (v5 <= (int)++v10) goto LABEL_19;\n }\n v9 -= v11 == 41;\n if (v9 < 0) v7 = 0;\n ++v10;\n } while (v5 > (int)v10);\nLABEL_19:\n if (v9 || (result = \"Yes\", (v7 & 1) == 0)) {\n v13 = 0LL;\n v14 = 1;\n v15 = 0;\n do {\n while (1) {\n v16 = a2[v13];\n if (v16 != 40) break;\n if (++v15 < 0) v14 = 0;\n if (v5 <= (int)++v13) goto LABEL_30;\n }\n v15 -= v16 == 41;\n if (v15 < 0) v14 = 0;\n ++v13;\n } while (v5 > (int)v13);\n LABEL_30:\n if (v3 <= 0) goto LABEL_39;\n goto LABEL_31;\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-120", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(int* arr, int arr_size, int k, int* out) {\n for (int i = 0; i < arr_size - 1; i++) {\n for (int j = 0; j < arr_size - i - 1; j++) {\n if (arr[j] > arr[j + 1]) {\n int temp = arr[j];\n arr[j] = arr[j + 1];\n arr[j + 1] = temp;\n }\n }\n }\n for (int i = 0; i < k; i++) {\n out[i] = arr[arr_size - k + i];\n }\n}", + "test": "#include \n#include \n#include \n\nint issame(int* a, int* b, int size) {\n for (int i = 0; i < size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int arr1[] = {-3, -4, 5};\n int out1[3];\n func0(arr1, 3, 3, out1);\n int expected1[] = {-4, -3, 5};\n assert(issame(out1, expected1, 3));\n\n int arr2[] = {4, -4, 4};\n int out2[2];\n func0(arr2, 3, 2, out2);\n int expected2[] = {4, 4};\n assert(issame(out2, expected2, 2));\n\n int arr3[] = {-3, 2, 1, 2, -1, -2, 1};\n int out3[1];\n func0(arr3, 7, 1, out3);\n int expected3[] = {2};\n assert(issame(out3, expected3, 1));\n\n int arr4[] = {123, -123, 20, 0, 1, 2, -3};\n int out4[3];\n func0(arr4, 7, 3, out4);\n int expected4[] = {2, 20, 123};\n assert(issame(out4, expected4, 3));\n\n int arr5[] = {-123, 20, 0, 1, 2, -3};\n int out5[4];\n func0(arr5, 6, 4, out5);\n int expected5[] = {0, 1, 2, 20};\n assert(issame(out5, expected5, 4));\n\n int arr6[] = {5, 15, 0, 3, -13, -8, 0};\n int out6[7];\n func0(arr6, 7, 7, out6);\n int expected6[] = {-13, -8, 0, 0, 3, 5, 15};\n assert(issame(out6, expected6, 7));\n\n int arr7[] = {-1, 0, 2, 5, 3, -10};\n int out7[2];\n func0(arr7, 6, 2, out7);\n int expected7[] = {3, 5};\n assert(issame(out7, expected7, 2));\n\n int arr8[] = {1, 0, 5, -7};\n int out8[1];\n func0(arr8, 4, 1, out8);\n int expected8[] = {5};\n assert(issame(out8, expected8, 1));\n\n int arr9[] = {4, -4};\n int out9[2];\n func0(arr9, 2, 2, out9);\n int expected9[] = {-4, 4};\n assert(issame(out9, expected9, 2));\n\n int arr10[] = {-10, 10};\n int out10[2];\n func0(arr10, 2, 2, out10);\n int expected10[] = {-10, 10};\n assert(issame(out10, expected10, 2));\n\n int arr11[] = {1, 2, 3, -23, 243, -400, 0};\n int out11[0];\n func0(arr11, 7, 0, out11); // Empty output expected\n int expected11[] = {}; // Empty array\n assert(issame(out11, expected11, 0));\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_28], rcx\nmov [rbp+var_10], 0\njmp loc_124C\nloc_118B:\nmov [rbp+var_C], 0\njmp loc_1236\nloc_1197:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_1232\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_C]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_C]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nloc_1232:\nadd [rbp+var_C], 1\nloc_1236:\nmov eax, [rbp+var_1C]\nsub eax, [rbp+var_10]\nsub eax, 1\ncmp [rbp+var_C], eax\njl loc_1197\nadd [rbp+var_10], 1\nloc_124C:\nmov eax, [rbp+var_1C]\nsub eax, 1\ncmp [rbp+var_10], eax\njl loc_118B\nmov [rbp+var_8], 0\njmp short loc_129F\nloc_1264:\nmov eax, [rbp+var_1C]\nsub eax, [rbp+var_20]\nmov edx, eax\nmov eax, [rbp+var_8]\nadd eax, edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_8], 1\nloc_129F:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_20]\njl short loc_1264\nnop\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3, __int64 a4)\n{\n __int64 result; // rax\n int i; // [rsp+18h] [rbp-10h]\n int j; // [rsp+1Ch] [rbp-Ch]\n unsigned int k; // [rsp+20h] [rbp-8h]\n int v8; // [rsp+24h] [rbp-4h]\n\n for ( i = 0; i < a2 - 1; ++i )\n {\n for ( j = 0; j < a2 - i - 1; ++j )\n {\n if ( *(_DWORD *)(4LL * j + a1) > *(_DWORD *)(4 * (j + 1LL) + a1) )\n {\n v8 = *(_DWORD *)(4LL * j + a1);\n *(_DWORD *)(4LL * j + a1) = *(_DWORD *)(4 * (j + 1LL) + a1);\n *(_DWORD *)(a1 + 4 * (j + 1LL)) = v8;\n }\n }\n }\n for ( k = 0; ; ++k )\n {\n result = k;\n if ( (int)k >= a3 )\n break;\n *(_DWORD *)(4LL * (int)k + a4) = *(_DWORD *)(4LL * (int)(a2 - a3 + k) + a1);\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_28], rcx\nmov [rbp+var_10], 0\njmp loc_124C\nloc_118B:\nmov [rbp+var_C], 0\njmp loc_1236\nloc_1197:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_1232\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_C]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_C]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nloc_1232:\nadd [rbp+var_C], 1\nloc_1236:\nmov eax, [rbp+var_1C]\nsub eax, [rbp+var_10]\nsub eax, 1\ncmp [rbp+var_C], eax\njl loc_1197\nadd [rbp+var_10], 1\nloc_124C:\nmov eax, [rbp+var_1C]\nsub eax, 1\ncmp [rbp+var_10], eax\njl loc_118B\nmov [rbp+var_8], 0\njmp short loc_129F\nloc_1264:\nmov eax, [rbp+var_1C]\nsub eax, [rbp+var_20]\nmov edx, eax\nmov eax, [rbp+var_8]\nadd eax, edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_8], 1\nloc_129F:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_20]\njl short loc_1264\nnop\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3, __int64 a4)\n{\n __int64 result; // rax\n int i; // [rsp+18h] [rbp-10h]\n int j; // [rsp+1Ch] [rbp-Ch]\n unsigned int k; // [rsp+20h] [rbp-8h]\n int v8; // [rsp+24h] [rbp-4h]\n\n for ( i = 0; i < a2 - 1; ++i )\n {\n for ( j = 0; j < a2 - i - 1; ++j )\n {\n if ( *(_DWORD *)(4LL * j + a1) > *(_DWORD *)(4 * (j + 1LL) + a1) )\n {\n v8 = *(_DWORD *)(4LL * j + a1);\n *(_DWORD *)(4LL * j + a1) = *(_DWORD *)(4 * (j + 1LL) + a1);\n *(_DWORD *)(a1 + 4 * (j + 1LL)) = v8;\n }\n }\n }\n for ( k = 0; ; ++k )\n {\n result = k;\n if ( (int)k >= a3 )\n break;\n *(_DWORD *)(4LL * (int)k + a4) = *(_DWORD *)(4LL * (int)(a2 - a3 + k) + a1);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3, long long a4) {\n long long result;\n int i;\n int j;\n unsigned int k;\n int v8;\n for (i = 0; i < a2 - 1; ++i) {\n for (j = 0; j < a2 - i - 1; ++j) {\n if (*(uint32_t *)(4LL * j + a1) > *(uint32_t *)(4 * (j + 1LL) + a1)) {\n v8 = *(uint32_t *)(4LL * j + a1);\n *(uint32_t *)(4LL * j + a1) = *(uint32_t *)(4 * (j + 1LL) + a1);\n *(uint32_t *)(a1 + 4 * (j + 1LL)) = v8;\n }\n }\n }\n for (k = 0;; ++k) {\n result = k;\n if ((int)k >= a3) break;\n *(uint32_t *)(4LL * (int)k + a4) =\n *(uint32_t *)(4LL * (int)(a2 - a3 + k) + a1);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3, long long a4) {\n long long result;\n int i;\n int j;\n unsigned int k;\n int v8;\n for (i = 0; i < a2 - 1; ++i) {\n for (j = 0; j < a2 - i - 1; ++j) {\n if (*(uint32_t *)(4LL * j + a1) > *(uint32_t *)(4 * (j + 1LL) + a1)) {\n v8 = *(uint32_t *)(4LL * j + a1);\n *(uint32_t *)(4LL * j + a1) = *(uint32_t *)(4 * (j + 1LL) + a1);\n *(uint32_t *)(a1 + 4 * (j + 1LL)) = v8;\n }\n }\n }\n for (k = 0;; ++k) {\n result = k;\n if ((int)k >= a3) break;\n *(uint32_t *)(4LL * (int)k + a4) =\n *(uint32_t *)(4LL * (int)(a2 - a3 + k) + a1);\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-120", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(int* arr, int arr_size, int k, int* out) {\n for (int i = 0; i < arr_size - 1; i++) {\n for (int j = 0; j < arr_size - i - 1; j++) {\n if (arr[j] > arr[j + 1]) {\n int temp = arr[j];\n arr[j] = arr[j + 1];\n arr[j + 1] = temp;\n }\n }\n }\n for (int i = 0; i < k; i++) {\n out[i] = arr[arr_size - k + i];\n }\n}", + "test": "#include \n#include \n#include \n\nint issame(int* a, int* b, int size) {\n for (int i = 0; i < size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int arr1[] = {-3, -4, 5};\n int out1[3];\n func0(arr1, 3, 3, out1);\n int expected1[] = {-4, -3, 5};\n assert(issame(out1, expected1, 3));\n\n int arr2[] = {4, -4, 4};\n int out2[2];\n func0(arr2, 3, 2, out2);\n int expected2[] = {4, 4};\n assert(issame(out2, expected2, 2));\n\n int arr3[] = {-3, 2, 1, 2, -1, -2, 1};\n int out3[1];\n func0(arr3, 7, 1, out3);\n int expected3[] = {2};\n assert(issame(out3, expected3, 1));\n\n int arr4[] = {123, -123, 20, 0, 1, 2, -3};\n int out4[3];\n func0(arr4, 7, 3, out4);\n int expected4[] = {2, 20, 123};\n assert(issame(out4, expected4, 3));\n\n int arr5[] = {-123, 20, 0, 1, 2, -3};\n int out5[4];\n func0(arr5, 6, 4, out5);\n int expected5[] = {0, 1, 2, 20};\n assert(issame(out5, expected5, 4));\n\n int arr6[] = {5, 15, 0, 3, -13, -8, 0};\n int out6[7];\n func0(arr6, 7, 7, out6);\n int expected6[] = {-13, -8, 0, 0, 3, 5, 15};\n assert(issame(out6, expected6, 7));\n\n int arr7[] = {-1, 0, 2, 5, 3, -10};\n int out7[2];\n func0(arr7, 6, 2, out7);\n int expected7[] = {3, 5};\n assert(issame(out7, expected7, 2));\n\n int arr8[] = {1, 0, 5, -7};\n int out8[1];\n func0(arr8, 4, 1, out8);\n int expected8[] = {5};\n assert(issame(out8, expected8, 1));\n\n int arr9[] = {4, -4};\n int out9[2];\n func0(arr9, 2, 2, out9);\n int expected9[] = {-4, 4};\n assert(issame(out9, expected9, 2));\n\n int arr10[] = {-10, 10};\n int out10[2];\n func0(arr10, 2, 2, out10);\n int expected10[] = {-10, 10};\n assert(issame(out10, expected10, 2));\n\n int arr11[] = {1, 2, 3, -23, 243, -400, 0};\n int out11[0];\n func0(arr11, 7, 0, out11); // Empty output expected\n int expected11[] = {}; // Empty array\n assert(issame(out11, expected11, 0));\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbx\nmov r9, rdi\nmov r11d, esi\nmov ebx, edx\nmov r10, rcx\ncmp esi, 1\njle short loc_11BD\nmov r8d, esi\nlea rdx, [rdi+4]\njmp short loc_11AA\nloc_1187:\nadd rax, 4\ncmp rax, rdi\njz short loc_11A0\nloc_1190:\nmov ecx, [rax]\nmov esi, [rax+4]\ncmp ecx, esi\njle short loc_1187\nmov [rax], esi\nmov [rax+4], ecx\njmp short loc_1187\nloc_11A0:\nsub r8d, 1\ncmp r8d, 1\njz short loc_11BD\nloc_11AA:\ncmp r8d, 1\njle short loc_11ED\nmov rax, r9\nlea ecx, [r8-2]\nlea rdi, [rdx+rcx*4]\njmp short loc_1190\nloc_11BD:\ntest ebx, ebx\njle short loc_11EB\nmovsxd rbx, ebx\nlea rsi, ds:0[rbx*4]\nmovsxd r11, r11d\nsub r11, rbx\nlea rcx, [r9+r11*4]\nmov eax, 0\nloc_11DB:\nmov edx, [rcx+rax]\nmov [r10+rax], edx\nadd rax, 4\ncmp rax, rsi\njnz short loc_11DB\nloc_11EB:\npop rbx\nretn\nloc_11ED:\nsub r8d, 1\njmp short loc_11AA", + "ida_pseudo": "void __fastcall func0(int *a1, int a2, int a3, __int64 a4)\n{\n int i; // r8d\n int *v7; // rax\n int v8; // ecx\n int v9; // esi\n __int64 v10; // r11\n __int64 j; // rax\n\n if ( a2 > 1 )\n {\n for ( i = a2; i != 1; --i )\n {\n while ( i <= 1 )\n --i;\n v7 = a1;\n do\n {\n v8 = *v7;\n v9 = v7[1];\n if ( *v7 > v9 )\n {\n *v7 = v9;\n v7[1] = v8;\n }\n ++v7;\n }\n while ( v7 != &a1[i - 2 + 1] );\n }\n }\n if ( a3 > 0 )\n {\n v10 = a2 - (__int64)a3;\n for ( j = 0LL; j != a3; ++j )\n *(_DWORD *)(a4 + j * 4) = a1[v10 + j];\n }\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbx\nmov r9, rdi\nmov r11d, esi\nmov ebx, edx\nmov r10, rcx\ncmp esi, 1\njle short loc_11BD\nmov r8d, esi\nlea rdx, [rdi+4]\njmp short loc_11AA\nloc_1187:\nadd rax, 4\ncmp rax, rdi\njz short loc_11A0\nloc_1190:\nmov ecx, [rax]\nmov esi, [rax+4]\ncmp ecx, esi\njle short loc_1187\nmov [rax], esi\nmov [rax+4], ecx\njmp short loc_1187\nloc_11A0:\nsub r8d, 1\ncmp r8d, 1\njz short loc_11BD\nloc_11AA:\ncmp r8d, 1\njle short loc_11ED\nmov rax, r9\nlea ecx, [r8-2]\nlea rdi, [rdx+rcx*4]\njmp short loc_1190\nloc_11BD:\ntest ebx, ebx\njle short loc_11EB\nmovsxd rbx, ebx\nlea rsi, ds:0[rbx*4]\nmovsxd r11, r11d\nsub r11, rbx\nlea rcx, [r9+r11*4]\nmov eax, 0\nloc_11DB:\nmov edx, [rcx+rax]\nmov [r10+rax], edx\nadd rax, 4\ncmp rax, rsi\njnz short loc_11DB\nloc_11EB:\npop rbx\nretn\nloc_11ED:\nsub r8d, 1\njmp short loc_11AA", + "ida_strip_pseudo": "void __fastcall sub_1169(int *a1, int a2, int a3, __int64 a4)\n{\n int i; // r8d\n int *v7; // rax\n int v8; // ecx\n int v9; // esi\n __int64 v10; // r11\n __int64 j; // rax\n\n if ( a2 > 1 )\n {\n for ( i = a2; i != 1; --i )\n {\n while ( i <= 1 )\n --i;\n v7 = a1;\n do\n {\n v8 = *v7;\n v9 = v7[1];\n if ( *v7 > v9 )\n {\n *v7 = v9;\n v7[1] = v8;\n }\n ++v7;\n }\n while ( v7 != &a1[i - 2 + 1] );\n }\n }\n if ( a3 > 0 )\n {\n v10 = a2 - (__int64)a3;\n for ( j = 0LL; j != a3; ++j )\n *(_DWORD *)(a4 + j * 4) = a1[v10 + j];\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1169(int *a1, int a2, int a3, long long a4) {\n int i;\n int *v7;\n int v8;\n int v9;\n long long v10;\n long long j;\n if (a2 > 1) {\n for (i = a2; i != 1; --i) {\n while (i <= 1) --i;\n v7 = a1;\n do {\n v8 = *v7;\n v9 = v7[1];\n if (*v7 > v9) {\n *v7 = v9;\n v7[1] = v8;\n }\n ++v7;\n } while (v7 != &a1[i - 2 + 1]);\n }\n }\n if (a3 > 0) {\n v10 = a2 - (long long)a3;\n for (j = 0LL; j != a3; ++j) *(uint32_t *)(a4 + j * 4) = a1[v10 + j];\n }\n}", + "ida_pseudo_norm": "void func0(int *a1, int a2, int a3, long long a4) {\n int i;\n int *v7;\n int v8;\n int v9;\n long long v10;\n long long j;\n if (a2 > 1) {\n for (i = a2; i != 1; --i) {\n while (i <= 1) --i;\n v7 = a1;\n do {\n v8 = *v7;\n v9 = v7[1];\n if (*v7 > v9) {\n *v7 = v9;\n v7[1] = v8;\n }\n ++v7;\n } while (v7 != &a1[i - 2 + 1]);\n }\n }\n if (a3 > 0) {\n v10 = a2 - (long long)a3;\n for (j = 0LL; j != a3; ++j) *(uint32_t *)(a4 + j * 4) = a1[v10 + j];\n }\n}" + }, + { + "index": "HumanEval-C-120", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(int* arr, int arr_size, int k, int* out) {\n for (int i = 0; i < arr_size - 1; i++) {\n for (int j = 0; j < arr_size - i - 1; j++) {\n if (arr[j] > arr[j + 1]) {\n int temp = arr[j];\n arr[j] = arr[j + 1];\n arr[j + 1] = temp;\n }\n }\n }\n for (int i = 0; i < k; i++) {\n out[i] = arr[arr_size - k + i];\n }\n}", + "test": "#include \n#include \n#include \n\nint issame(int* a, int* b, int size) {\n for (int i = 0; i < size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int arr1[] = {-3, -4, 5};\n int out1[3];\n func0(arr1, 3, 3, out1);\n int expected1[] = {-4, -3, 5};\n assert(issame(out1, expected1, 3));\n\n int arr2[] = {4, -4, 4};\n int out2[2];\n func0(arr2, 3, 2, out2);\n int expected2[] = {4, 4};\n assert(issame(out2, expected2, 2));\n\n int arr3[] = {-3, 2, 1, 2, -1, -2, 1};\n int out3[1];\n func0(arr3, 7, 1, out3);\n int expected3[] = {2};\n assert(issame(out3, expected3, 1));\n\n int arr4[] = {123, -123, 20, 0, 1, 2, -3};\n int out4[3];\n func0(arr4, 7, 3, out4);\n int expected4[] = {2, 20, 123};\n assert(issame(out4, expected4, 3));\n\n int arr5[] = {-123, 20, 0, 1, 2, -3};\n int out5[4];\n func0(arr5, 6, 4, out5);\n int expected5[] = {0, 1, 2, 20};\n assert(issame(out5, expected5, 4));\n\n int arr6[] = {5, 15, 0, 3, -13, -8, 0};\n int out6[7];\n func0(arr6, 7, 7, out6);\n int expected6[] = {-13, -8, 0, 0, 3, 5, 15};\n assert(issame(out6, expected6, 7));\n\n int arr7[] = {-1, 0, 2, 5, 3, -10};\n int out7[2];\n func0(arr7, 6, 2, out7);\n int expected7[] = {3, 5};\n assert(issame(out7, expected7, 2));\n\n int arr8[] = {1, 0, 5, -7};\n int out8[1];\n func0(arr8, 4, 1, out8);\n int expected8[] = {5};\n assert(issame(out8, expected8, 1));\n\n int arr9[] = {4, -4};\n int out9[2];\n func0(arr9, 2, 2, out9);\n int expected9[] = {-4, 4};\n assert(issame(out9, expected9, 2));\n\n int arr10[] = {-10, 10};\n int out10[2];\n func0(arr10, 2, 2, out10);\n int expected10[] = {-10, 10};\n assert(issame(out10, expected10, 2));\n\n int arr11[] = {1, 2, 3, -23, 243, -400, 0};\n int out11[0];\n func0(arr11, 7, 0, out11); // Empty output expected\n int expected11[] = {}; // Empty array\n assert(issame(out11, expected11, 0));\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbx\nmov r8, rdi\nmov r10d, esi\nmov ebx, edx\nmov r9, rcx\ncmp esi, 1\njle short loc_172F\nmov edi, esi\nlea r11, [r8+4]\nnop dword ptr [rax+rax+00h]\nloc_16F0:\ncmp edi, 1\njle short loc_1768\nlea edx, [rdi-2]\nmov rax, r8\nlea rsi, [r11+rdx*4]\nnop\nloc_1700:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd edx, xmm0\nmovd ecx, xmm1\ncmp ecx, edx\njge short loc_171E\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_171E:\nadd rax, 4\ncmp rax, rsi\njnz short loc_1700\nsub edi, 1\ncmp edi, 1\njnz short loc_16F0\nloc_172F:\ntest ebx, ebx\njle short loc_1760\nsub r10d, ebx\nmovsxd rcx, ebx\nmovsxd rax, r10d\nshl rcx, 2\nlea rsi, [r8+rax*4]\nxor eax, eax\nnop word ptr [rax+rax+00000000h]\nloc_1750:\nmov edx, [rsi+rax]\nmov [r9+rax], edx\nadd rax, 4\ncmp rcx, rax\njnz short loc_1750\nloc_1760:\npop rbx\nretn\nloc_1768:\nsub edi, 1\njmp short loc_16F0", + "ida_pseudo": "void __fastcall func0(__m128i *a1, int a2, int a3, __int64 a4)\n{\n int i; // edi\n __m128i *v6; // rax\n __m128i v7; // xmm0\n __int64 j; // rax\n\n if ( a2 > 1 )\n {\n for ( i = a2; i != 1; --i )\n {\n while ( i <= 1 )\n --i;\n v6 = a1;\n do\n {\n v7 = _mm_loadl_epi64(v6);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v7, 229)) < _mm_cvtsi128_si32(v7) )\n v6->m128i_i64[0] = _mm_shuffle_epi32(v7, 225).m128i_u64[0];\n v6 = (__m128i *)((char *)v6 + 4);\n }\n while ( v6 != (__m128i *)((char *)a1->m128i_i64 + 4 * (unsigned int)(i - 2) + 4) );\n }\n }\n if ( a3 > 0 )\n {\n for ( j = 0LL; j != a3; ++j )\n *(_DWORD *)(a4 + j * 4) = a1->m128i_i32[a2 - a3 + j];\n }\n}", + "ida_strip_asm": "sub_16D0:\nendbr64\npush rbx\nmov r8, rdi\nmov r10d, esi\nmov ebx, edx\nmov r9, rcx\ncmp esi, 1\njle short loc_172F\nmov edi, esi\nlea r11, [r8+4]\nnop dword ptr [rax+rax+00h]\nloc_16F0:\ncmp edi, 1\njle short loc_1768\nlea edx, [rdi-2]\nmov rax, r8\nlea rsi, [r11+rdx*4]\nnop\nloc_1700:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd edx, xmm0\nmovd ecx, xmm1\ncmp ecx, edx\njge short loc_171E\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_171E:\nadd rax, 4\ncmp rax, rsi\njnz short loc_1700\nsub edi, 1\ncmp edi, 1\njnz short loc_16F0\nloc_172F:\ntest ebx, ebx\njle short loc_1760\nsub r10d, ebx\nmovsxd rcx, ebx\nmovsxd rax, r10d\nshl rcx, 2\nlea rsi, [r8+rax*4]\nxor eax, eax\nnop word ptr [rax+rax+00000000h]\nloc_1750:\nmov edx, [rsi+rax]\nmov [r9+rax], edx\nadd rax, 4\ncmp rcx, rax\njnz short loc_1750\nloc_1760:\npop rbx\nretn\nloc_1768:\nsub edi, 1\njmp short loc_16F0", + "ida_strip_pseudo": "void __fastcall sub_16D0(__m128i *a1, int a2, int a3, __int64 a4)\n{\n int i; // edi\n __m128i *v6; // rax\n __m128i v7; // xmm0\n __int64 j; // rax\n\n if ( a2 > 1 )\n {\n for ( i = a2; i != 1; --i )\n {\n while ( i <= 1 )\n --i;\n v6 = a1;\n do\n {\n v7 = _mm_loadl_epi64(v6);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v7, 229)) < _mm_cvtsi128_si32(v7) )\n v6->m128i_i64[0] = _mm_shuffle_epi32(v7, 225).m128i_u64[0];\n v6 = (__m128i *)((char *)v6 + 4);\n }\n while ( v6 != (__m128i *)((char *)a1->m128i_i64 + 4 * (unsigned int)(i - 2) + 4) );\n }\n }\n if ( a3 > 0 )\n {\n for ( j = 0LL; j != a3; ++j )\n *(_DWORD *)(a4 + j * 4) = a1->m128i_i32[a2 - a3 + j];\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_16D0(__m128i *a1, int a2, int a3, long long a4) {\n int i;\n __m128i *v6;\n __m128i v7;\n long long j;\n if (a2 > 1) {\n for (i = a2; i != 1; --i) {\n while (i <= 1) --i;\n v6 = a1;\n do {\n v7 = _mm_loadl_epi64(v6);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v7, 229)) <\n _mm_cvtsi128_si32(v7))\n v6->m128i_i64[0] = _mm_shuffle_epi32(v7, 225).m128i_u64[0];\n v6 = (__m128i *)((char *)v6 + 4);\n } while (v6 != (__m128i *)((char *)a1->m128i_i64 +\n 4 * (unsigned int)(i - 2) + 4));\n }\n }\n if (a3 > 0) {\n for (j = 0LL; j != a3; ++j)\n *(uint32_t *)(a4 + j * 4) = a1->m128i_i32[a2 - a3 + j];\n }\n}", + "ida_pseudo_norm": "void func0(__m128i *a1, int a2, int a3, long long a4) {\n int i;\n __m128i *v6;\n __m128i v7;\n long long j;\n if (a2 > 1) {\n for (i = a2; i != 1; --i) {\n while (i <= 1) --i;\n v6 = a1;\n do {\n v7 = _mm_loadl_epi64(v6);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v7, 229)) <\n _mm_cvtsi128_si32(v7))\n v6->m128i_i64[0] = _mm_shuffle_epi32(v7, 225).m128i_u64[0];\n v6 = (__m128i *)((char *)v6 + 4);\n } while (v6 != (__m128i *)((char *)a1->m128i_i64 +\n 4 * (unsigned int)(i - 2) + 4));\n }\n }\n if (a3 > 0) {\n for (j = 0LL; j != a3; ++j)\n *(uint32_t *)(a4 + j * 4) = a1->m128i_i32[a2 - a3 + j];\n }\n}" + }, + { + "index": "HumanEval-C-120", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(int* arr, int arr_size, int k, int* out) {\n for (int i = 0; i < arr_size - 1; i++) {\n for (int j = 0; j < arr_size - i - 1; j++) {\n if (arr[j] > arr[j + 1]) {\n int temp = arr[j];\n arr[j] = arr[j + 1];\n arr[j + 1] = temp;\n }\n }\n }\n for (int i = 0; i < k; i++) {\n out[i] = arr[arr_size - k + i];\n }\n}", + "test": "#include \n#include \n#include \n\nint issame(int* a, int* b, int size) {\n for (int i = 0; i < size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int arr1[] = {-3, -4, 5};\n int out1[3];\n func0(arr1, 3, 3, out1);\n int expected1[] = {-4, -3, 5};\n assert(issame(out1, expected1, 3));\n\n int arr2[] = {4, -4, 4};\n int out2[2];\n func0(arr2, 3, 2, out2);\n int expected2[] = {4, 4};\n assert(issame(out2, expected2, 2));\n\n int arr3[] = {-3, 2, 1, 2, -1, -2, 1};\n int out3[1];\n func0(arr3, 7, 1, out3);\n int expected3[] = {2};\n assert(issame(out3, expected3, 1));\n\n int arr4[] = {123, -123, 20, 0, 1, 2, -3};\n int out4[3];\n func0(arr4, 7, 3, out4);\n int expected4[] = {2, 20, 123};\n assert(issame(out4, expected4, 3));\n\n int arr5[] = {-123, 20, 0, 1, 2, -3};\n int out5[4];\n func0(arr5, 6, 4, out5);\n int expected5[] = {0, 1, 2, 20};\n assert(issame(out5, expected5, 4));\n\n int arr6[] = {5, 15, 0, 3, -13, -8, 0};\n int out6[7];\n func0(arr6, 7, 7, out6);\n int expected6[] = {-13, -8, 0, 0, 3, 5, 15};\n assert(issame(out6, expected6, 7));\n\n int arr7[] = {-1, 0, 2, 5, 3, -10};\n int out7[2];\n func0(arr7, 6, 2, out7);\n int expected7[] = {3, 5};\n assert(issame(out7, expected7, 2));\n\n int arr8[] = {1, 0, 5, -7};\n int out8[1];\n func0(arr8, 4, 1, out8);\n int expected8[] = {5};\n assert(issame(out8, expected8, 1));\n\n int arr9[] = {4, -4};\n int out9[2];\n func0(arr9, 2, 2, out9);\n int expected9[] = {-4, 4};\n assert(issame(out9, expected9, 2));\n\n int arr10[] = {-10, 10};\n int out10[2];\n func0(arr10, 2, 2, out10);\n int expected10[] = {-10, 10};\n assert(issame(out10, expected10, 2));\n\n int arr11[] = {1, 2, 3, -23, 243, -400, 0};\n int out11[0];\n func0(arr11, 7, 0, out11); // Empty output expected\n int expected11[] = {}; // Empty array\n assert(issame(out11, expected11, 0));\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmovsxd r10, esi\npush rbx\nmov r8, rdi\nmov r11d, edx\nmov r9, rcx\ncmp r10d, 1\njle short loc_16F7\nmov edi, r10d\nlea rbx, [r8+4]\nxchg ax, ax\nloc_16B0:\ncmp edi, 1\njle loc_1758\nlea edx, [rdi-2]\nmov rax, r8\nlea rsi, [rbx+rdx*4]\nnop dword ptr [rax+rax+00h]\nloc_16C8:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd ecx, xmm0\nmovd edx, xmm1\ncmp ecx, edx\njle short loc_16E6\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_16E6:\nadd rax, 4\ncmp rax, rsi\njnz short loc_16C8\nsub edi, 1\ncmp edi, 1\njnz short loc_16B0\nloc_16F7:\ntest r11d, r11d\njle short loc_1750\nmov esi, r10d\nlea eax, [r11-1]\nmovsxd rcx, r11d\nsub esi, r11d\ncmp eax, 2\njbe short loc_1729\nsub r10, rcx\nmov rdx, r9\nlea rax, ds:4[r10*4]\nlea rdi, [r8+rax]\nsub rdx, rdi\ncmp rdx, 8\nja short loc_1760\nloc_1729:\nmovsxd rsi, esi\nshl rcx, 2\nxor eax, eax\nlea rsi, [r8+rsi*4]\nnop word ptr [rax+rax+00000000h]\nloc_1740:\nmov edx, [rsi+rax]\nmov [r9+rax], edx\nadd rax, 4\ncmp rcx, rax\njnz short loc_1740\nloc_1750:\npop rbx\nretn\nloc_1758:\nsub edi, 1\njmp loc_16B0\nloc_1760:\nmov edx, r11d\nlea rcx, [r8+rax-4]\nxor eax, eax\nshr edx, 2\nshl rdx, 4\nnop dword ptr [rax+00000000h]\nloc_1778:\nmovdqu xmm2, xmmword ptr [rcx+rax]\nmovups xmmword ptr [r9+rax], xmm2\nadd rax, 10h\ncmp rax, rdx\njnz short loc_1778\nmov eax, r11d\nand eax, 0FFFFFFFCh\ntest r11b, 3\njz short loc_1750\nlea edx, [rsi+rax]\nmov ecx, eax\nmovsxd rdx, edx\nlea rdi, ds:0[rcx*4]\nmov edx, [r8+rdx*4]\nmov [r9+rcx*4], edx\nlea edx, [rax+1]\ncmp r11d, edx\njle short loc_1750\nadd edx, esi\nadd eax, 2\nmovsxd rdx, edx\nmov edx, [r8+rdx*4]\nmov [r9+rdi+4], edx\ncmp r11d, eax\njle short loc_1750\nadd eax, esi\ncdqe\nmov eax, [r8+rax*4]\nmov [r9+rdi+8], eax\npop rbx\nretn", + "ida_pseudo": "void __fastcall func0(__m128i *a1, int a2, int a3, __int64 a4)\n{\n __int64 v4; // r10\n int i; // edi\n __m128i *v8; // rax\n __m128i v9; // xmm0\n int v10; // esi\n __int64 v11; // r10\n __int64 v12; // rax\n __int8 *v13; // rsi\n __int64 v14; // rax\n unsigned int v15; // eax\n __int64 v16; // rdi\n unsigned int v17; // edx\n int v18; // eax\n\n v4 = a2;\n if ( a2 > 1 )\n {\n for ( i = a2; i != 1; --i )\n {\n while ( i <= 1 )\n --i;\n v8 = a1;\n do\n {\n v9 = _mm_loadl_epi64(v8);\n if ( _mm_cvtsi128_si32(v9) > _mm_cvtsi128_si32(_mm_shuffle_epi32(v9, 229)) )\n v8->m128i_i64[0] = _mm_shuffle_epi32(v9, 225).m128i_u64[0];\n v8 = (__m128i *)((char *)v8 + 4);\n }\n while ( v8 != (__m128i *)((char *)a1->m128i_i64 + 4 * (unsigned int)(i - 2) + 4) );\n }\n }\n if ( a3 > 0 )\n {\n v10 = a2 - a3;\n if ( (unsigned int)(a3 - 1) > 2\n && (v11 = v4 - a3, (unsigned __int64)(a4 - ((_QWORD)a1->m128i_i64 + 4 * v11 + 4)) > 8) )\n {\n v14 = 0LL;\n do\n {\n *(__m128i *)(a4 + v14) = _mm_loadu_si128((__m128i *)((char *)a1 + 4 * v11 + v14));\n v14 += 16LL;\n }\n while ( v14 != 16LL * ((unsigned int)a3 >> 2) );\n v15 = a3 & 0xFFFFFFFC;\n if ( (a3 & 3) != 0 )\n {\n v16 = 4LL * v15;\n *(_DWORD *)(a4 + v16) = a1->m128i_i32[v10 + v15];\n v17 = v15 + 1;\n if ( a3 > (int)(v15 + 1) )\n {\n v18 = v15 + 2;\n *(_DWORD *)(a4 + v16 + 4) = a1->m128i_i32[v10 + v17];\n if ( a3 > v18 )\n *(_DWORD *)(a4 + v16 + 8) = a1->m128i_i32[v10 + v18];\n }\n }\n }\n else\n {\n v12 = 0LL;\n v13 = &a1->m128i_i8[4 * v10];\n do\n {\n *(_DWORD *)(a4 + v12) = *(_DWORD *)&v13[v12];\n v12 += 4LL;\n }\n while ( 4LL * a3 != v12 );\n }\n }\n}", + "ida_strip_asm": "sub_1690:\nendbr64\nmovsxd r10, esi\npush rbx\nmov r8, rdi\nmov r11d, edx\nmov r9, rcx\ncmp r10d, 1\njle short loc_16F7\nmov edi, r10d\nlea rbx, [r8+4]\nxchg ax, ax\nloc_16B0:\ncmp edi, 1\njle loc_1758\nlea edx, [rdi-2]\nmov rax, r8\nlea rsi, [rbx+rdx*4]\nnop dword ptr [rax+rax+00h]\nloc_16C8:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd ecx, xmm0\nmovd edx, xmm1\ncmp ecx, edx\njle short loc_16E6\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_16E6:\nadd rax, 4\ncmp rax, rsi\njnz short loc_16C8\nsub edi, 1\ncmp edi, 1\njnz short loc_16B0\nloc_16F7:\ntest r11d, r11d\njle short loc_1750\nmov esi, r10d\nlea eax, [r11-1]\nmovsxd rcx, r11d\nsub esi, r11d\ncmp eax, 2\njbe short loc_1729\nsub r10, rcx\nmov rdx, r9\nlea rax, ds:4[r10*4]\nlea rdi, [r8+rax]\nsub rdx, rdi\ncmp rdx, 8\nja short loc_1760\nloc_1729:\nmovsxd rsi, esi\nshl rcx, 2\nxor eax, eax\nlea rsi, [r8+rsi*4]\nnop word ptr [rax+rax+00000000h]\nloc_1740:\nmov edx, [rsi+rax]\nmov [r9+rax], edx\nadd rax, 4\ncmp rcx, rax\njnz short loc_1740\nloc_1750:\npop rbx\nretn\nloc_1758:\nsub edi, 1\njmp loc_16B0\nloc_1760:\nmov edx, r11d\nlea rcx, [r8+rax-4]\nxor eax, eax\nshr edx, 2\nshl rdx, 4\nnop dword ptr [rax+00000000h]\nloc_1778:\nmovdqu xmm2, xmmword ptr [rcx+rax]\nmovups xmmword ptr [r9+rax], xmm2\nadd rax, 10h\ncmp rax, rdx\njnz short loc_1778\nmov eax, r11d\nand eax, 0FFFFFFFCh\ntest r11b, 3\njz short loc_1750\nlea edx, [rsi+rax]\nmov ecx, eax\nmovsxd rdx, edx\nlea rdi, ds:0[rcx*4]\nmov edx, [r8+rdx*4]\nmov [r9+rcx*4], edx\nlea edx, [rax+1]\ncmp r11d, edx\njle short loc_1750\nadd edx, esi\nadd eax, 2\nmovsxd rdx, edx\nmov edx, [r8+rdx*4]\nmov [r9+rdi+4], edx\ncmp r11d, eax\njle short loc_1750\nadd eax, esi\ncdqe\nmov eax, [r8+rax*4]\nmov [r9+rdi+8], eax\npop rbx\nretn", + "ida_strip_pseudo": "void __fastcall sub_1690(__m128i *a1, int a2, int a3, __int64 a4)\n{\n __int64 v4; // r10\n int i; // edi\n __m128i *v8; // rax\n __m128i v9; // xmm0\n int v10; // esi\n __int64 v11; // r10\n __int64 v12; // rax\n __int8 *v13; // rsi\n __int64 v14; // rax\n unsigned int v15; // eax\n __int64 v16; // rdi\n unsigned int v17; // edx\n int v18; // eax\n\n v4 = a2;\n if ( a2 > 1 )\n {\n for ( i = a2; i != 1; --i )\n {\n while ( i <= 1 )\n --i;\n v8 = a1;\n do\n {\n v9 = _mm_loadl_epi64(v8);\n if ( _mm_cvtsi128_si32(v9) > _mm_cvtsi128_si32(_mm_shuffle_epi32(v9, 229)) )\n v8->m128i_i64[0] = _mm_shuffle_epi32(v9, 225).m128i_u64[0];\n v8 = (__m128i *)((char *)v8 + 4);\n }\n while ( v8 != (__m128i *)((char *)a1->m128i_i64 + 4 * (unsigned int)(i - 2) + 4) );\n }\n }\n if ( a3 > 0 )\n {\n v10 = a2 - a3;\n if ( (unsigned int)(a3 - 1) > 2\n && (v11 = v4 - a3, (unsigned __int64)(a4 - ((_QWORD)a1->m128i_i64 + 4 * v11 + 4)) > 8) )\n {\n v14 = 0LL;\n do\n {\n *(__m128i *)(a4 + v14) = _mm_loadu_si128((__m128i *)((char *)a1 + 4 * v11 + v14));\n v14 += 16LL;\n }\n while ( v14 != 16LL * ((unsigned int)a3 >> 2) );\n v15 = a3 & 0xFFFFFFFC;\n if ( (a3 & 3) != 0 )\n {\n v16 = 4LL * v15;\n *(_DWORD *)(a4 + v16) = a1->m128i_i32[v10 + v15];\n v17 = v15 + 1;\n if ( a3 > (int)(v15 + 1) )\n {\n v18 = v15 + 2;\n *(_DWORD *)(a4 + v16 + 4) = a1->m128i_i32[v10 + v17];\n if ( a3 > v18 )\n *(_DWORD *)(a4 + v16 + 8) = a1->m128i_i32[v10 + v18];\n }\n }\n }\n else\n {\n v12 = 0LL;\n v13 = &a1->m128i_i8[4 * v10];\n do\n {\n *(_DWORD *)(a4 + v12) = *(_DWORD *)&v13[v12];\n v12 += 4LL;\n }\n while ( 4LL * a3 != v12 );\n }\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1690(__m128i *a1, int a2, int a3, long long a4) {\n long long v4;\n int i;\n __m128i *v8;\n __m128i v9;\n int v10;\n long long v11;\n long long v12;\n char *v13;\n long long v14;\n unsigned int v15;\n long long v16;\n unsigned int v17;\n int v18;\n v4 = a2;\n if (a2 > 1) {\n for (i = a2; i != 1; --i) {\n while (i <= 1) --i;\n v8 = a1;\n do {\n v9 = _mm_loadl_epi64(v8);\n if (_mm_cvtsi128_si32(v9) >\n _mm_cvtsi128_si32(_mm_shuffle_epi32(v9, 229)))\n v8->m128i_i64[0] = _mm_shuffle_epi32(v9, 225).m128i_u64[0];\n v8 = (__m128i *)((char *)v8 + 4);\n } while (v8 != (__m128i *)((char *)a1->m128i_i64 +\n 4 * (unsigned int)(i - 2) + 4));\n }\n }\n if (a3 > 0) {\n v10 = a2 - a3;\n if ((unsigned int)(a3 - 1) > 2 &&\n (v11 = v4 - a3, (unsigned long long)(a4 - ((uint64_t)a1->m128i_i64 +\n 4 * v11 + 4)) > 8)) {\n v14 = 0LL;\n do {\n *(__m128i *)(a4 + v14) =\n _mm_loadu_si128((__m128i *)((char *)a1 + 4 * v11 + v14));\n v14 += 16LL;\n } while (v14 != 16LL * ((unsigned int)a3 >> 2));\n v15 = a3 & 4294967292;\n if ((a3 & 3) != 0) {\n v16 = 4LL * v15;\n *(uint32_t *)(a4 + v16) = a1->m128i_i32[v10 + v15];\n v17 = v15 + 1;\n if (a3 > (int)(v15 + 1)) {\n v18 = v15 + 2;\n *(uint32_t *)(a4 + v16 + 4) = a1->m128i_i32[v10 + v17];\n if (a3 > v18) *(uint32_t *)(a4 + v16 + 8) = a1->m128i_i32[v10 + v18];\n }\n }\n } else {\n v12 = 0LL;\n v13 = &a1->m128i_i8[4 * v10];\n do {\n *(uint32_t *)(a4 + v12) = *(uint32_t *)&v13[v12];\n v12 += 4LL;\n } while (4LL * a3 != v12);\n }\n }\n}", + "ida_pseudo_norm": "void func0(__m128i *a1, int a2, int a3, long long a4) {\n long long v4;\n int i;\n __m128i *v8;\n __m128i v9;\n int v10;\n long long v11;\n long long v12;\n char *v13;\n long long v14;\n unsigned int v15;\n long long v16;\n unsigned int v17;\n int v18;\n v4 = a2;\n if (a2 > 1) {\n for (i = a2; i != 1; --i) {\n while (i <= 1) --i;\n v8 = a1;\n do {\n v9 = _mm_loadl_epi64(v8);\n if (_mm_cvtsi128_si32(v9) >\n _mm_cvtsi128_si32(_mm_shuffle_epi32(v9, 229)))\n v8->m128i_i64[0] = _mm_shuffle_epi32(v9, 225).m128i_u64[0];\n v8 = (__m128i *)((char *)v8 + 4);\n } while (v8 != (__m128i *)((char *)a1->m128i_i64 +\n 4 * (unsigned int)(i - 2) + 4));\n }\n }\n if (a3 > 0) {\n v10 = a2 - a3;\n if ((unsigned int)(a3 - 1) > 2 &&\n (v11 = v4 - a3, (unsigned long long)(a4 - ((uint64_t)a1->m128i_i64 +\n 4 * v11 + 4)) > 8)) {\n v14 = 0LL;\n do {\n *(__m128i *)(a4 + v14) =\n _mm_loadu_si128((__m128i *)((char *)a1 + 4 * v11 + v14));\n v14 += 16LL;\n } while (v14 != 16LL * ((unsigned int)a3 >> 2));\n v15 = a3 & 4294967292;\n if ((a3 & 3) != 0) {\n v16 = 4LL * v15;\n *(uint32_t *)(a4 + v16) = a1->m128i_i32[v10 + v15];\n v17 = v15 + 1;\n if (a3 > (int)(v15 + 1)) {\n v18 = v15 + 2;\n *(uint32_t *)(a4 + v16 + 4) = a1->m128i_i32[v10 + v17];\n if (a3 > v18) *(uint32_t *)(a4 + v16 + 8) = a1->m128i_i32[v10 + v18];\n }\n }\n } else {\n v12 = 0LL;\n v13 = &a1->m128i_i8[4 * v10];\n do {\n *(uint32_t *)(a4 + v12) = *(uint32_t *)&v13[v12];\n v12 += 4LL;\n } while (4LL * a3 != v12);\n }\n }\n}" + }, + { + "index": "HumanEval-C-121", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int* lst, int size) {\n int sum = 0;\n for (int i = 0; i * 2 < size; i++)\n if (lst[i * 2] % 2 == 1) sum += lst[i * 2];\n return sum;\n}", + "test": "#include \n\nint main() {\n int test1[] = {5, 8, 7, 1};\n assert(func0(test1, 4) == 12);\n\n int test2[] = {3, 3, 3, 3, 3};\n assert(func0(test2, 5) == 9);\n\n int test3[] = {30, 13, 24, 321};\n assert(func0(test3, 4) == 0);\n\n int test4[] = {5, 9};\n assert(func0(test4, 2) == 5);\n\n int test5[] = {2, 4, 8};\n assert(func0(test5, 3) == 0);\n\n int test6[] = {30, 13, 23, 32};\n assert(func0(test6, 4) == 23);\n\n int test7[] = {3, 13, 2, 9};\n assert(func0(test7, 4) == 3);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11D5\nloc_1188:\nmov eax, [rbp+var_4]\nadd eax, eax\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\ncmp eax, 1\njnz short loc_11D1\nmov eax, [rbp+var_4]\nadd eax, eax\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nloc_11D1:\nadd [rbp+var_4], 1\nloc_11D5:\nmov eax, [rbp+var_4]\nadd eax, eax\ncmp [rbp+var_1C], eax\njg short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; a2 > 2 * i; ++i )\n {\n if ( *(_DWORD *)(8LL * i + a1) % 2 == 1 )\n v3 += *(_DWORD *)(8LL * i + a1);\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11D5\nloc_1188:\nmov eax, [rbp+var_4]\nadd eax, eax\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\ncmp eax, 1\njnz short loc_11D1\nmov eax, [rbp+var_4]\nadd eax, eax\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nloc_11D1:\nadd [rbp+var_4], 1\nloc_11D5:\nmov eax, [rbp+var_4]\nadd eax, eax\ncmp [rbp+var_1C], eax\njg short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; a2 > 2 * i; ++i )\n {\n if ( *(_DWORD *)(8LL * i + a1) % 2 == 1 )\n v3 += *(_DWORD *)(8LL * i + a1);\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; a2 > 2 * i; ++i) {\n if (*(uint32_t *)(8LL * i + a1) % 2 == 1) v3 += *(uint32_t *)(8LL * i + a1);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; a2 > 2 * i; ++i) {\n if (*(uint32_t *)(8LL * i + a1) % 2 == 1) v3 += *(uint32_t *)(8LL * i + a1);\n }\n return v3;\n}" + }, + { + "index": "HumanEval-C-121", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int* lst, int size) {\n int sum = 0;\n for (int i = 0; i * 2 < size; i++)\n if (lst[i * 2] % 2 == 1) sum += lst[i * 2];\n return sum;\n}", + "test": "#include \n\nint main() {\n int test1[] = {5, 8, 7, 1};\n assert(func0(test1, 4) == 12);\n\n int test2[] = {3, 3, 3, 3, 3};\n assert(func0(test2, 5) == 9);\n\n int test3[] = {30, 13, 24, 321};\n assert(func0(test3, 4) == 0);\n\n int test4[] = {5, 9};\n assert(func0(test4, 2) == 5);\n\n int test5[] = {2, 4, 8};\n assert(func0(test5, 3) == 0);\n\n int test6[] = {30, 13, 23, 32};\n assert(func0(test6, 4) == 23);\n\n int test7[] = {3, 13, 2, 9};\n assert(func0(test7, 4) == 3);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11A8\nmov rcx, rdi\nsub esi, 1\nshr esi, 1\nmov esi, esi\nlea r8, [rdi+rsi*8+8]\nmov esi, 0\nloc_1185:\nmov eax, [rcx]\nmov edi, eax\nshr edi, 1Fh\nlea edx, [rax+rdi]\nand edx, 1\nsub edx, edi\nadd eax, esi\ncmp edx, 1\ncmovz esi, eax\nadd rcx, 8\ncmp rcx, r8\njnz short loc_1185\nloc_11A5:\nmov eax, esi\nretn\nloc_11A8:\nmov esi, 0\njmp short loc_11A5", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rcx\n __int64 v3; // r8\n unsigned int v4; // esi\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = (__int64)&a1[2 * ((unsigned int)(a2 - 1) >> 1) + 2];\n v4 = 0;\n do\n {\n if ( *v2 % 2 == 1 )\n v4 += *v2;\n v2 += 2;\n }\n while ( v2 != (_DWORD *)v3 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11A8\nmov rcx, rdi\nsub esi, 1\nshr esi, 1\nmov esi, esi\nlea r8, [rdi+rsi*8+8]\nmov esi, 0\nloc_1185:\nmov eax, [rcx]\nmov edi, eax\nshr edi, 1Fh\nlea edx, [rax+rdi]\nand edx, 1\nsub edx, edi\nadd eax, esi\ncmp edx, 1\ncmovz esi, eax\nadd rcx, 8\ncmp rcx, r8\njnz short loc_1185\nloc_11A5:\nmov eax, esi\nretn\nloc_11A8:\nmov esi, 0\njmp short loc_11A5", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rcx\n __int64 v3; // r8\n unsigned int v4; // esi\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = (__int64)&a1[2 * ((unsigned int)(a2 - 1) >> 1) + 2];\n v4 = 0;\n do\n {\n if ( *v2 % 2 == 1 )\n v4 += *v2;\n v2 += 2;\n }\n while ( v2 != (_DWORD *)v3 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2) {\n uint32_t *v2;\n long long v3;\n unsigned int v4;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = (long long)&a1[2 * ((unsigned int)(a2 - 1) >> 1) + 2];\n v4 = 0;\n do {\n if (*v2 % 2 == 1) v4 += *v2;\n v2 += 2;\n } while (v2 != (uint32_t *)v3);\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n long long v3;\n unsigned int v4;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = (long long)&a1[2 * ((unsigned int)(a2 - 1) >> 1) + 2];\n v4 = 0;\n do {\n if (*v2 % 2 == 1) v4 += *v2;\n v2 += 2;\n } while (v2 != (uint32_t *)v3);\n }\n return v4;\n}" + }, + { + "index": "HumanEval-C-121", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int* lst, int size) {\n int sum = 0;\n for (int i = 0; i * 2 < size; i++)\n if (lst[i * 2] % 2 == 1) sum += lst[i * 2];\n return sum;\n}", + "test": "#include \n\nint main() {\n int test1[] = {5, 8, 7, 1};\n assert(func0(test1, 4) == 12);\n\n int test2[] = {3, 3, 3, 3, 3};\n assert(func0(test2, 5) == 9);\n\n int test3[] = {30, 13, 24, 321};\n assert(func0(test3, 4) == 0);\n\n int test4[] = {5, 9};\n assert(func0(test4, 2) == 5);\n\n int test5[] = {2, 4, 8};\n assert(func0(test5, 3) == 0);\n\n int test6[] = {30, 13, 23, 32};\n assert(func0(test6, 4) == 23);\n\n int test7[] = {3, 13, 2, 9};\n assert(func0(test7, 4) == 3);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_13D0\nsub esi, 1\nxor ecx, ecx\nshr esi, 1\nlea r8, [rdi+rsi*8+8]\nnop dword ptr [rax+00h]\nloc_13A8:\nmov eax, [rdi]\nmov esi, eax\nshr esi, 1Fh\nlea edx, [rax+rsi]\nadd eax, ecx\nand edx, 1\nsub edx, esi\ncmp edx, 1\ncmovz ecx, eax\nadd rdi, 8\ncmp rdi, r8\njnz short loc_13A8\nmov eax, ecx\nretn\nloc_13D0:\nxor ecx, ecx\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n unsigned int v2; // ecx\n __int64 v3; // r8\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 0;\n v3 = (__int64)&a1[2 * ((unsigned int)(a2 - 1) >> 1) + 2];\n do\n {\n if ( *a1 % 2 == 1 )\n v2 += *a1;\n a1 += 2;\n }\n while ( a1 != (_DWORD *)v3 );\n return v2;\n}", + "ida_strip_asm": "sub_1390:\nendbr64\ntest esi, esi\njle short loc_13D0\nsub esi, 1\nxor ecx, ecx\nshr esi, 1\nlea r8, [rdi+rsi*8+8]\nnop dword ptr [rax+00h]\nloc_13A8:\nmov eax, [rdi]\nmov esi, eax\nshr esi, 1Fh\nlea edx, [rax+rsi]\nadd eax, ecx\nand edx, 1\nsub edx, esi\ncmp edx, 1\ncmovz ecx, eax\nadd rdi, 8\ncmp rdi, r8\njnz short loc_13A8\nmov eax, ecx\nretn\nloc_13D0:\nxor ecx, ecx\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1390(_DWORD *a1, int a2)\n{\n unsigned int v2; // ecx\n __int64 v3; // r8\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 0;\n v3 = (__int64)&a1[2 * ((unsigned int)(a2 - 1) >> 1) + 2];\n do\n {\n if ( *a1 % 2 == 1 )\n v2 += *a1;\n a1 += 2;\n }\n while ( a1 != (_DWORD *)v3 );\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1390(uint32_t *a1, int a2) {\n unsigned int v2;\n long long v3;\n if (a2 <= 0) return 0LL;\n v2 = 0;\n v3 = (long long)&a1[2 * ((unsigned int)(a2 - 1) >> 1) + 2];\n do {\n if (*a1 % 2 == 1) v2 += *a1;\n a1 += 2;\n } while (a1 != (uint32_t *)v3);\n return v2;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n unsigned int v2;\n long long v3;\n if (a2 <= 0) return 0LL;\n v2 = 0;\n v3 = (long long)&a1[2 * ((unsigned int)(a2 - 1) >> 1) + 2];\n do {\n if (*a1 % 2 == 1) v2 += *a1;\n a1 += 2;\n } while (a1 != (uint32_t *)v3);\n return v2;\n}" + }, + { + "index": "HumanEval-C-122", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int arr[], int k) {\n int sum = 0;\n for (int i = 0; i < k; i++)\n if (arr[i] >= -99 && arr[i] <= 99) sum += arr[i];\n return sum;\n}", + "test": "#include \n\nint main() {\n int test1[] = {1, -2, -3, 41, 57, 76, 87, 88, 99};\n assert(func0(test1, 3) == -4);\n\n int test2[] = {111, 121, 3, 4000, 5, 6};\n assert(func0(test2, 2) == 0);\n\n int test3[] = {11, 21, 3, 90, 5, 6, 7, 8, 9};\n assert(func0(test3, 4) == 125);\n\n int test4[] = {111, 21, 3, 4000, 5, 6, 7, 8, 9};\n assert(func0(test4, 4) == 24);\n \n int test5[] = {1};\n assert(func0(test5, 1) == 1);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11DB\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp eax, 0FFFFFF9Dh\njl short loc_11D7\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp eax, 63h ; 'c'\njg short loc_11D7\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nloc_11D7:\nadd [rbp+var_4], 1\nloc_11DB:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(int *)(4LL * i + a1) >= -99 && *(int *)(4LL * i + a1) <= 99 )\n v3 += *(_DWORD *)(4LL * i + a1);\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11DB\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp eax, 0FFFFFF9Dh\njl short loc_11D7\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp eax, 63h ; 'c'\njg short loc_11D7\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nloc_11D7:\nadd [rbp+var_4], 1\nloc_11DB:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(int *)(4LL * i + a1) >= -99 && *(int *)(4LL * i + a1) <= 99 )\n v3 += *(_DWORD *)(4LL * i + a1);\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(int *)(4LL * i + a1) >= -99 && *(int *)(4LL * i + a1) <= 99)\n v3 += *(uint32_t *)(4LL * i + a1);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(int *)(4LL * i + a1) >= -99 && *(int *)(4LL * i + a1) <= 99)\n v3 += *(uint32_t *)(4LL * i + a1);\n }\n return v3;\n}" + }, + { + "index": "HumanEval-C-122", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int arr[], int k) {\n int sum = 0;\n for (int i = 0; i < k; i++)\n if (arr[i] >= -99 && arr[i] <= 99) sum += arr[i];\n return sum;\n}", + "test": "#include \n\nint main() {\n int test1[] = {1, -2, -3, 41, 57, 76, 87, 88, 99};\n assert(func0(test1, 3) == -4);\n\n int test2[] = {111, 121, 3, 4000, 5, 6};\n assert(func0(test2, 2) == 0);\n\n int test3[] = {11, 21, 3, 90, 5, 6, 7, 8, 9};\n assert(func0(test3, 4) == 125);\n\n int test4[] = {111, 21, 3, 4000, 5, 6, 7, 8, 9};\n assert(func0(test4, 4) == 24);\n \n int test5[] = {1};\n assert(func0(test5, 1) == 1);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_119C\nmov rdx, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*4]\nmov ecx, 0\nloc_1180:\nmov eax, [rdx]\nlea esi, [rax+63h]\nadd eax, ecx\ncmp esi, 0C7h\ncmovb ecx, eax\nadd rdx, 4\ncmp rdx, rdi\njnz short loc_1180\nloc_1199:\nmov eax, ecx\nretn\nloc_119C:\nmov ecx, 0\njmp short loc_1199", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rdx\n _DWORD *v3; // rdi\n unsigned int v4; // ecx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n {\n if ( (unsigned int)(*v2 + 99) < 0xC7 )\n v4 += *v2;\n ++v2;\n }\n while ( v2 != v3 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_119C\nmov rdx, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*4]\nmov ecx, 0\nloc_1180:\nmov eax, [rdx]\nlea esi, [rax+63h]\nadd eax, ecx\ncmp esi, 0C7h\ncmovb ecx, eax\nadd rdx, 4\ncmp rdx, rdi\njnz short loc_1180\nloc_1199:\nmov eax, ecx\nretn\nloc_119C:\nmov ecx, 0\njmp short loc_1199", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rdx\n _DWORD *v3; // rdi\n unsigned int v4; // ecx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n {\n if ( (unsigned int)(*v2 + 99) < 0xC7 )\n v4 += *v2;\n ++v2;\n }\n while ( v2 != v3 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2) {\n uint32_t *v2;\n uint32_t *v3;\n unsigned int v4;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do {\n if ((unsigned int)(*v2 + 99) < 199) v4 += *v2;\n ++v2;\n } while (v2 != v3);\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n uint32_t *v3;\n unsigned int v4;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do {\n if ((unsigned int)(*v2 + 99) < 199) v4 += *v2;\n ++v2;\n } while (v2 != v3);\n }\n return v4;\n}" + }, + { + "index": "HumanEval-C-123", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(int n, int *out, int *size) {\n int capacity = 10;\n *size = 1;\n out[0] = 1;\n while (n != 1) {\n if (n % 2 == 1) {\n if (*size >= capacity) {\n capacity *= 2;\n out = (int *)realloc(out, capacity * sizeof(int));\n }\n out[(*size)++] = n;\n n = n * 3 + 1;\n } else {\n n = n / 2;\n }\n }\n for (int i = 1; i < *size; i++) {\n int key = out[i];\n int j = i - 1;\n while (j >= 0 && out[j] > key) {\n out[j + 1] = out[j];\n j = j - 1;\n }\n out[j + 1] = key;\n }\n}", + "test": "#include \n#include \n\nint issame(int *a, int size_a, int *b, int size_b) {\n if (size_a != size_b) return 0;\n for (int i = 0; i < size_a; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int size;\n int *result;\n\n // Test 1\n int expected1[] = {1, 5, 7, 11, 13, 17};\n result = (int*)malloc(100 * sizeof(int));\n func0(14, result, &size);\n assert(issame(result, size, expected1, 6));\n free(result);\n\n // Test 2\n int expected2[] = {1, 5};\n result = (int*)malloc(100 * sizeof(int));\n func0(5, result, &size);\n assert(issame(result, size, expected2, 2));\n free(result);\n\n // Test 3\n int expected3[] = {1, 3, 5};\n result = (int*)malloc(100 * sizeof(int));\n func0(12, result, &size);\n assert(issame(result, size, expected3, 3));\n free(result);\n\n // Test 4\n int expected4[] = {1};\n result = (int*)malloc(100 * sizeof(int));\n func0(1, result, &size);\n assert(issame(result, size, expected4, 1));\n free(result);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_14], edi\nmov [rbp+ptr], rsi\nmov [rbp+var_28], rdx\nmov [rbp+var_10], 0Ah\nmov rax, [rbp+var_28]\nmov dword ptr [rax], 1\nmov rax, [rbp+ptr]\nmov dword ptr [rax], 1\njmp loc_128C\nloc_1200:\nmov edx, [rbp+var_14]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\ncmp eax, 1\njnz short loc_127D\nmov rax, [rbp+var_28]\nmov eax, [rax]\ncmp [rbp+var_10], eax\njg short loc_1247\nshl [rbp+var_10], 1\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nmov rsi, rdx; size\nmov rdi, rax; ptr\ncall _realloc\nmov [rbp+ptr], rax\nloc_1247:\nmov rax, [rbp+var_28]\nmov eax, [rax]\nlea ecx, [rax+1]\nmov rdx, [rbp+var_28]\nmov [rdx], ecx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov eax, [rbp+var_14]\nmov [rdx], eax\nmov edx, [rbp+var_14]\nmov eax, edx\nadd eax, eax\nadd eax, edx\nadd eax, 1\nmov [rbp+var_14], eax\njmp short loc_128C\nloc_127D:\nmov eax, [rbp+var_14]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_14], eax\nloc_128C:\ncmp [rbp+var_14], 1\njnz loc_1200\nmov [rbp+var_C], 1\njmp loc_133D\nloc_12A2:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_C]\nsub eax, 1\nmov [rbp+var_8], eax\njmp short loc_12FB\nloc_12C6:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nadd rdx, 1\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+ptr]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nsub [rbp+var_8], 1\nloc_12FB:\ncmp [rbp+var_8], 0\njs short loc_131C\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_4], eax\njl short loc_12C6\nloc_131C:\nmov eax, [rbp+var_8]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nadd [rbp+var_C], 1\nloc_133D:\nmov rax, [rbp+var_28]\nmov eax, [rax]\ncmp [rbp+var_C], eax\njl loc_12A2\nnop\nnop\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, _DWORD *a2, int *a3)\n{\n int v3; // eax\n __int64 result; // rax\n void *ptr; // [rsp+10h] [rbp-20h]\n int v8; // [rsp+20h] [rbp-10h]\n int i; // [rsp+24h] [rbp-Ch]\n int j; // [rsp+28h] [rbp-8h]\n int v11; // [rsp+2Ch] [rbp-4h]\n\n ptr = a2;\n v8 = 10;\n *a3 = 1;\n *a2 = 1;\n while ( a1 != 1 )\n {\n if ( a1 % 2 == 1 )\n {\n if ( v8 <= *a3 )\n {\n v8 *= 2;\n ptr = realloc(ptr, 4LL * v8);\n }\n v3 = (*a3)++;\n *((_DWORD *)ptr + v3) = a1;\n a1 = 3 * a1 + 1;\n }\n else\n {\n a1 /= 2;\n }\n }\n for ( i = 1; ; ++i )\n {\n result = (unsigned int)*a3;\n if ( i >= (int)result )\n break;\n v11 = *((_DWORD *)ptr + i);\n for ( j = i - 1; j >= 0 && v11 < *((_DWORD *)ptr + j); --j )\n *((_DWORD *)ptr + j + 1) = *((_DWORD *)ptr + j);\n *((_DWORD *)ptr + j + 1) = v11;\n }\n return result;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_14], edi\nmov [rbp+ptr], rsi\nmov [rbp+var_28], rdx\nmov [rbp+var_10], 0Ah\nmov rax, [rbp+var_28]\nmov dword ptr [rax], 1\nmov rax, [rbp+ptr]\nmov dword ptr [rax], 1\njmp loc_128C\nloc_1200:\nmov edx, [rbp+var_14]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\ncmp eax, 1\njnz short loc_127D\nmov rax, [rbp+var_28]\nmov eax, [rax]\ncmp [rbp+var_10], eax\njg short loc_1247\nshl [rbp+var_10], 1\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nmov rsi, rdx; size\nmov rdi, rax; ptr\ncall _realloc\nmov [rbp+ptr], rax\nloc_1247:\nmov rax, [rbp+var_28]\nmov eax, [rax]\nlea ecx, [rax+1]\nmov rdx, [rbp+var_28]\nmov [rdx], ecx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov eax, [rbp+var_14]\nmov [rdx], eax\nmov edx, [rbp+var_14]\nmov eax, edx\nadd eax, eax\nadd eax, edx\nadd eax, 1\nmov [rbp+var_14], eax\njmp short loc_128C\nloc_127D:\nmov eax, [rbp+var_14]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_14], eax\nloc_128C:\ncmp [rbp+var_14], 1\njnz loc_1200\nmov [rbp+var_C], 1\njmp loc_133D\nloc_12A2:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_C]\nsub eax, 1\nmov [rbp+var_8], eax\njmp short loc_12FB\nloc_12C6:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nadd rdx, 1\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+ptr]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nsub [rbp+var_8], 1\nloc_12FB:\ncmp [rbp+var_8], 0\njs short loc_131C\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_4], eax\njl short loc_12C6\nloc_131C:\nmov eax, [rbp+var_8]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nadd [rbp+var_C], 1\nloc_133D:\nmov rax, [rbp+var_28]\nmov eax, [rax]\ncmp [rbp+var_C], eax\njl loc_12A2\nnop\nnop\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11C9(int a1, _DWORD *a2, int *a3)\n{\n int v3; // eax\n __int64 result; // rax\n void *ptr; // [rsp+10h] [rbp-20h]\n int v8; // [rsp+20h] [rbp-10h]\n int i; // [rsp+24h] [rbp-Ch]\n int j; // [rsp+28h] [rbp-8h]\n int v11; // [rsp+2Ch] [rbp-4h]\n\n ptr = a2;\n v8 = 10;\n *a3 = 1;\n *a2 = 1;\n while ( a1 != 1 )\n {\n if ( a1 % 2 == 1 )\n {\n if ( v8 <= *a3 )\n {\n v8 *= 2;\n ptr = realloc(ptr, 4LL * v8);\n }\n v3 = (*a3)++;\n *((_DWORD *)ptr + v3) = a1;\n a1 = 3 * a1 + 1;\n }\n else\n {\n a1 /= 2;\n }\n }\n for ( i = 1; ; ++i )\n {\n result = (unsigned int)*a3;\n if ( i >= (int)result )\n break;\n v11 = *((_DWORD *)ptr + i);\n for ( j = i - 1; j >= 0 && v11 < *((_DWORD *)ptr + j); --j )\n *((_DWORD *)ptr + j + 1) = *((_DWORD *)ptr + j);\n *((_DWORD *)ptr + j + 1) = v11;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11C9(int a1, uint32_t *a2, int *a3) {\n int v3;\n long long result;\n void *ptr;\n int v8;\n int i;\n int j;\n int v11;\n ptr = a2;\n v8 = 10;\n *a3 = 1;\n *a2 = 1;\n while (a1 != 1) {\n if (a1 % 2 == 1) {\n if (v8 <= *a3) {\n v8 *= 2;\n ptr = realloc(ptr, 4LL * v8);\n }\n v3 = (*a3)++;\n *((uint32_t *)ptr + v3) = a1;\n a1 = 3 * a1 + 1;\n } else {\n a1 /= 2;\n }\n }\n for (i = 1;; ++i) {\n result = (unsigned int)*a3;\n if (i >= (int)result) break;\n v11 = *((uint32_t *)ptr + i);\n for (j = i - 1; j >= 0 && v11 < *((uint32_t *)ptr + j); --j)\n *((uint32_t *)ptr + j + 1) = *((uint32_t *)ptr + j);\n *((uint32_t *)ptr + j + 1) = v11;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(int a1, uint32_t *a2, int *a3) {\n int v3;\n long long result;\n void *ptr;\n int v8;\n int i;\n int j;\n int v11;\n ptr = a2;\n v8 = 10;\n *a3 = 1;\n *a2 = 1;\n while (a1 != 1) {\n if (a1 % 2 == 1) {\n if (v8 <= *a3) {\n v8 *= 2;\n ptr = realloc(ptr, 4LL * v8);\n }\n v3 = (*a3)++;\n *((uint32_t *)ptr + v3) = a1;\n a1 = 3 * a1 + 1;\n } else {\n a1 /= 2;\n }\n }\n for (i = 1;; ++i) {\n result = (unsigned int)*a3;\n if (i >= (int)result) break;\n v11 = *((uint32_t *)ptr + i);\n for (j = i - 1; j >= 0 && v11 < *((uint32_t *)ptr + j); --j)\n *((uint32_t *)ptr + j + 1) = *((uint32_t *)ptr + j);\n *((uint32_t *)ptr + j + 1) = v11;\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-123", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(int n, int *out, int *size) {\n int capacity = 10;\n *size = 1;\n out[0] = 1;\n while (n != 1) {\n if (n % 2 == 1) {\n if (*size >= capacity) {\n capacity *= 2;\n out = (int *)realloc(out, capacity * sizeof(int));\n }\n out[(*size)++] = n;\n n = n * 3 + 1;\n } else {\n n = n / 2;\n }\n }\n for (int i = 1; i < *size; i++) {\n int key = out[i];\n int j = i - 1;\n while (j >= 0 && out[j] > key) {\n out[j + 1] = out[j];\n j = j - 1;\n }\n out[j + 1] = key;\n }\n}", + "test": "#include \n#include \n\nint issame(int *a, int size_a, int *b, int size_b) {\n if (size_a != size_b) return 0;\n for (int i = 0; i < size_a; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int size;\n int *result;\n\n // Test 1\n int expected1[] = {1, 5, 7, 11, 13, 17};\n result = (int*)malloc(100 * sizeof(int));\n func0(14, result, &size);\n assert(issame(result, size, expected1, 6));\n free(result);\n\n // Test 2\n int expected2[] = {1, 5};\n result = (int*)malloc(100 * sizeof(int));\n func0(5, result, &size);\n assert(issame(result, size, expected2, 2));\n free(result);\n\n // Test 3\n int expected3[] = {1, 3, 5};\n result = (int*)malloc(100 * sizeof(int));\n func0(12, result, &size);\n assert(issame(result, size, expected3, 3));\n free(result);\n\n // Test 4\n int expected4[] = {1};\n result = (int*)malloc(100 * sizeof(int));\n func0(1, result, &size);\n assert(issame(result, size, expected4, 1));\n free(result);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov ebp, edi\nmov rdi, rsi; ptr\nmov rbx, rdx\nmov dword ptr [rdx], 1\nmov dword ptr [rsi], 1\ncmp ebp, 1\njz short loc_122A\nmov r12d, 0Ah\njmp short loc_1207\nloc_11F2:\ncmp [rbx], r12d\njge short loc_123A\nloc_11F7:\nmov eax, [rbx]\nlea edx, [rax+1]\nmov [rbx], edx\ncdqe\nmov [rdi+rax*4], ebp\nlea ebp, [rbp+rbp*2+1]\nloc_1207:\nmov edx, ebp\nshr edx, 1Fh\nlea eax, [rbp+rdx+0]\nand eax, 1\nsub eax, edx\ncmp eax, 1\njz short loc_11F2\nmov eax, ebp\nshr eax, 1Fh\nadd eax, ebp\nsar eax, 1\nmov ebp, eax\ncmp eax, 1\njnz short loc_1207\nloc_122A:\ncmp dword ptr [rbx], 1\njle short loc_128D\nmov r9, rdi\nmov r8d, 0\njmp short loc_1267\nloc_123A:\nadd r12d, r12d\nmovsxd rsi, r12d\nshl rsi, 2; size\ncall _realloc\nmov rdi, rax\njmp short loc_11F7\nloc_124E:\nadd edx, 1\nmovsxd rdx, edx\nmov [rdi+rdx*4], esi\nadd r8, 1\nadd r9, 4\nlea eax, [r8+1]\ncmp [rbx], eax\njle short loc_128D\nloc_1267:\nmov esi, [r9+4]\nmov edx, r8d\nmov rax, r9\ntest r8d, r8d\njs short loc_124E\nloc_1276:\nmov ecx, [rax]\ncmp ecx, esi\njle short loc_124E\nmov [rax+4], ecx\nsub edx, 1\nsub rax, 4\ncmp edx, 0FFFFFFFFh\njnz short loc_1276\njmp short loc_124E\nloc_128D:\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "void __fastcall func0(int a1, _DWORD *a2, int *a3)\n{\n void *v4; // rdi\n int v6; // r12d\n int v7; // eax\n _DWORD *v8; // r9\n int v9; // r8d\n int v10; // esi\n int v11; // edx\n _DWORD *v12; // rax\n\n v4 = a2;\n *a3 = 1;\n *a2 = 1;\n if ( a1 != 1 )\n {\n v6 = 10;\n do\n {\n while ( a1 % 2 == 1 )\n {\n if ( *a3 >= v6 )\n {\n v6 *= 2;\n v4 = realloc(v4, 4LL * v6);\n }\n v7 = (*a3)++;\n *((_DWORD *)v4 + v7) = a1;\n a1 = 3 * a1 + 1;\n }\n a1 /= 2;\n }\n while ( a1 != 1 );\n }\n if ( *a3 > 1 )\n {\n v8 = v4;\n v9 = 0;\n do\n {\n v10 = v8[1];\n v11 = v9;\n v12 = v8;\n if ( v9 >= 0 )\n {\n do\n {\n if ( *v12 <= v10 )\n break;\n v12[1] = *v12;\n --v11;\n --v12;\n }\n while ( v11 != -1 );\n }\n *((_DWORD *)v4 + v11 + 1) = v10;\n ++v9;\n ++v8;\n }\n while ( *a3 > v9 + 1 );\n }\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r12\npush rbp\npush rbx\nmov ebp, edi\nmov rdi, rsi; ptr\nmov rbx, rdx\nmov dword ptr [rdx], 1\nmov dword ptr [rsi], 1\ncmp ebp, 1\njz short loc_122A\nmov r12d, 0Ah\njmp short loc_1207\nloc_11F2:\ncmp [rbx], r12d\njge short loc_123A\nloc_11F7:\nmov eax, [rbx]\nlea edx, [rax+1]\nmov [rbx], edx\ncdqe\nmov [rdi+rax*4], ebp\nlea ebp, [rbp+rbp*2+1]\nloc_1207:\nmov edx, ebp\nshr edx, 1Fh\nlea eax, [rbp+rdx+0]\nand eax, 1\nsub eax, edx\ncmp eax, 1\njz short loc_11F2\nmov eax, ebp\nshr eax, 1Fh\nadd eax, ebp\nsar eax, 1\nmov ebp, eax\ncmp eax, 1\njnz short loc_1207\nloc_122A:\ncmp dword ptr [rbx], 1\njle short loc_128D\nmov r9, rdi\nmov r8d, 0\njmp short loc_1267\nloc_123A:\nadd r12d, r12d\nmovsxd rsi, r12d\nshl rsi, 2; size\ncall _realloc\nmov rdi, rax\njmp short loc_11F7\nloc_124E:\nadd edx, 1\nmovsxd rdx, edx\nmov [rdi+rdx*4], esi\nadd r8, 1\nadd r9, 4\nlea eax, [r8+1]\ncmp [rbx], eax\njle short loc_128D\nloc_1267:\nmov esi, [r9+4]\nmov edx, r8d\nmov rax, r9\ntest r8d, r8d\njs short loc_124E\nloc_1276:\nmov ecx, [rax]\ncmp ecx, esi\njle short loc_124E\nmov [rax+4], ecx\nsub edx, 1\nsub rax, 4\ncmp edx, 0FFFFFFFFh\njnz short loc_1276\njmp short loc_124E\nloc_128D:\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "void __fastcall sub_11C9(int a1, _DWORD *a2, int *a3)\n{\n void *v4; // rdi\n int v6; // r12d\n int v7; // eax\n _DWORD *v8; // r9\n int v9; // r8d\n int v10; // esi\n int v11; // edx\n _DWORD *v12; // rax\n\n v4 = a2;\n *a3 = 1;\n *a2 = 1;\n if ( a1 != 1 )\n {\n v6 = 10;\n do\n {\n while ( a1 % 2 == 1 )\n {\n if ( *a3 >= v6 )\n {\n v6 *= 2;\n v4 = realloc(v4, 4LL * v6);\n }\n v7 = (*a3)++;\n *((_DWORD *)v4 + v7) = a1;\n a1 = 3 * a1 + 1;\n }\n a1 /= 2;\n }\n while ( a1 != 1 );\n }\n if ( *a3 > 1 )\n {\n v8 = v4;\n v9 = 0;\n do\n {\n v10 = v8[1];\n v11 = v9;\n v12 = v8;\n if ( v9 >= 0 )\n {\n do\n {\n if ( *v12 <= v10 )\n break;\n v12[1] = *v12;\n --v11;\n --v12;\n }\n while ( v11 != -1 );\n }\n *((_DWORD *)v4 + v11 + 1) = v10;\n ++v9;\n ++v8;\n }\n while ( *a3 > v9 + 1 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_11C9(int a1, uint32_t *a2, int *a3) {\n void *v4;\n int v6;\n int v7;\n uint32_t *v8;\n int v9;\n int v10;\n int v11;\n uint32_t *v12;\n v4 = a2;\n *a3 = 1;\n *a2 = 1;\n if (a1 != 1) {\n v6 = 10;\n do {\n while (a1 % 2 == 1) {\n if (*a3 >= v6) {\n v6 *= 2;\n v4 = realloc(v4, 4LL * v6);\n }\n v7 = (*a3)++;\n *((uint32_t *)v4 + v7) = a1;\n a1 = 3 * a1 + 1;\n }\n a1 /= 2;\n } while (a1 != 1);\n }\n if (*a3 > 1) {\n v8 = v4;\n v9 = 0;\n do {\n v10 = v8[1];\n v11 = v9;\n v12 = v8;\n if (v9 >= 0) {\n do {\n if (*v12 <= v10) break;\n v12[1] = *v12;\n --v11;\n --v12;\n } while (v11 != -1);\n }\n *((uint32_t *)v4 + v11 + 1) = v10;\n ++v9;\n ++v8;\n } while (*a3 > v9 + 1);\n }\n}", + "ida_pseudo_norm": "void func0(int a1, uint32_t *a2, int *a3) {\n void *v4;\n int v6;\n int v7;\n uint32_t *v8;\n int v9;\n int v10;\n int v11;\n uint32_t *v12;\n v4 = a2;\n *a3 = 1;\n *a2 = 1;\n if (a1 != 1) {\n v6 = 10;\n do {\n while (a1 % 2 == 1) {\n if (*a3 >= v6) {\n v6 *= 2;\n v4 = realloc(v4, 4LL * v6);\n }\n v7 = (*a3)++;\n *((uint32_t *)v4 + v7) = a1;\n a1 = 3 * a1 + 1;\n }\n a1 /= 2;\n } while (a1 != 1);\n }\n if (*a3 > 1) {\n v8 = v4;\n v9 = 0;\n do {\n v10 = v8[1];\n v11 = v9;\n v12 = v8;\n if (v9 >= 0) {\n do {\n if (*v12 <= v10) break;\n v12[1] = *v12;\n --v11;\n --v12;\n } while (v11 != -1);\n }\n *((uint32_t *)v4 + v11 + 1) = v10;\n ++v9;\n ++v8;\n } while (*a3 > v9 + 1);\n }\n}" + }, + { + "index": "HumanEval-C-123", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(int n, int *out, int *size) {\n int capacity = 10;\n *size = 1;\n out[0] = 1;\n while (n != 1) {\n if (n % 2 == 1) {\n if (*size >= capacity) {\n capacity *= 2;\n out = (int *)realloc(out, capacity * sizeof(int));\n }\n out[(*size)++] = n;\n n = n * 3 + 1;\n } else {\n n = n / 2;\n }\n }\n for (int i = 1; i < *size; i++) {\n int key = out[i];\n int j = i - 1;\n while (j >= 0 && out[j] > key) {\n out[j + 1] = out[j];\n j = j - 1;\n }\n out[j + 1] = key;\n }\n}", + "test": "#include \n#include \n\nint issame(int *a, int size_a, int *b, int size_b) {\n if (size_a != size_b) return 0;\n for (int i = 0; i < size_a; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int size;\n int *result;\n\n // Test 1\n int expected1[] = {1, 5, 7, 11, 13, 17};\n result = (int*)malloc(100 * sizeof(int));\n func0(14, result, &size);\n assert(issame(result, size, expected1, 6));\n free(result);\n\n // Test 2\n int expected2[] = {1, 5};\n result = (int*)malloc(100 * sizeof(int));\n func0(5, result, &size);\n assert(issame(result, size, expected2, 2));\n free(result);\n\n // Test 3\n int expected3[] = {1, 3, 5};\n result = (int*)malloc(100 * sizeof(int));\n func0(12, result, &size);\n assert(issame(result, size, expected3, 3));\n free(result);\n\n // Test 4\n int expected4[] = {1};\n result = (int*)malloc(100 * sizeof(int));\n func0(1, result, &size);\n assert(issame(result, size, expected4, 1));\n free(result);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\nmov rbp, rdx\npush rbx\nmov ebx, edi\nmov rdi, rsi; ptr\nmov dword ptr [rdx], 1\nmov dword ptr [rsi], 1\ncmp ebx, 1\njz short loc_1472\nmov r12d, 0Ah\nnop word ptr [rax+rax+00000000h]\nloc_1450:\nmov edx, ebx\nshr edx, 1Fh\nlea eax, [rbx+rdx]\nand eax, 1\nsub eax, edx\ncmp eax, 1\njz short loc_14C0\nmov eax, ebx\nshr eax, 1Fh\nadd eax, ebx\nsar eax, 1\nmov ebx, eax\ncmp eax, 1\njnz short loc_1450\nloc_1472:\ncmp dword ptr [rbp+0], 1\nmov esi, 1\njle short loc_14B8\nnop dword ptr [rax]\nloc_1480:\nmov ecx, [rdi+rsi*4]\nlea rax, [rsi-1]\njmp short loc_149D\nloc_1490:\nmov [rdi+rax*4+4], edx\nsub rax, 1\ncmp eax, 0FFFFFFFFh\njz short loc_14E8\nloc_149D:\nmov edx, [rdi+rax*4]\ncmp edx, ecx\njg short loc_1490\nadd eax, 1\ncdqe\nlea rax, [rdi+rax*4]\nloc_14AD:\nmov [rax], ecx\nadd rsi, 1\ncmp [rbp+0], esi\njg short loc_1480\nloc_14B8:\npop rbx\npop rbp\npop r12\nretn\nloc_14C0:\nmovsxd rax, dword ptr [rbp+0]\ncmp r12d, eax\njle short loc_14F0\nloc_14C9:\nlea edx, [rax+1]\nmov [rbp+0], edx\nmov [rdi+rax*4], ebx\nlea ebx, [rbx+rbx*2+1]\ntest bl, 1\njnz short loc_14C0\nsar ebx, 1\njmp loc_1450\nloc_14E8:\nmov rax, rdi\njmp short loc_14AD\nloc_14F0:\nadd r12d, r12d\nmovsxd rsi, r12d\nshl rsi, 2; size\ncall _realloc\nmov rdi, rax\nmovsxd rax, dword ptr [rbp+0]\njmp short loc_14C9", + "ida_pseudo": "void __fastcall func0(int a1, char *a2, int *a3)\n{\n char *v5; // rdi\n int v6; // r12d\n __int64 v7; // rsi\n int v8; // ecx\n __int64 v9; // rax\n int v10; // edx\n char *v11; // rax\n __int64 v12; // rax\n\n v5 = a2;\n *a3 = 1;\n *(_DWORD *)a2 = 1;\n if ( a1 != 1 )\n {\n v6 = 10;\n do\n {\n while ( a1 % 2 == 1 )\n {\n do\n {\n v12 = *a3;\n if ( v6 <= (int)v12 )\n {\n v6 *= 2;\n v5 = (char *)realloc(v5, 4LL * v6);\n v12 = *a3;\n }\n *a3 = v12 + 1;\n *(_DWORD *)&v5[4 * v12] = a1;\n a1 = 3 * a1 + 1;\n }\n while ( (a1 & 1) != 0 );\n a1 >>= 1;\n }\n a1 /= 2;\n }\n while ( a1 != 1 );\n }\n v7 = 1LL;\n if ( *a3 > 1 )\n {\n do\n {\n v8 = *(_DWORD *)&v5[4 * v7];\n v9 = v7 - 1;\n do\n {\n v10 = *(_DWORD *)&v5[4 * v9];\n if ( v10 <= v8 )\n {\n v11 = &v5[4 * (int)v9 + 4];\n goto LABEL_10;\n }\n *(_DWORD *)&v5[4 * v9-- + 4] = v10;\n }\n while ( (_DWORD)v9 != -1 );\n v11 = v5;\nLABEL_10:\n *(_DWORD *)v11 = v8;\n ++v7;\n }\n while ( *a3 > (int)v7 );\n }\n}", + "ida_strip_asm": "sub_1420:\nendbr64\npush r12\npush rbp\nmov rbp, rdx\npush rbx\nmov ebx, edi\nmov rdi, rsi; ptr\nmov dword ptr [rdx], 1\nmov dword ptr [rsi], 1\ncmp ebx, 1\njz short loc_1472\nmov r12d, 0Ah\nnop word ptr [rax+rax+00000000h]\nloc_1450:\nmov edx, ebx\nshr edx, 1Fh\nlea eax, [rbx+rdx]\nand eax, 1\nsub eax, edx\ncmp eax, 1\njz short loc_14C0\nmov eax, ebx\nshr eax, 1Fh\nadd eax, ebx\nsar eax, 1\nmov ebx, eax\ncmp eax, 1\njnz short loc_1450\nloc_1472:\ncmp dword ptr [rbp+0], 1\nmov esi, 1\njle short loc_14B8\nnop dword ptr [rax]\nloc_1480:\nmov ecx, [rdi+rsi*4]\nlea rax, [rsi-1]\njmp short loc_149D\nloc_1490:\nmov [rdi+rax*4+4], edx\nsub rax, 1\ncmp eax, 0FFFFFFFFh\njz short loc_14E8\nloc_149D:\nmov edx, [rdi+rax*4]\ncmp edx, ecx\njg short loc_1490\nadd eax, 1\ncdqe\nlea rax, [rdi+rax*4]\nloc_14AD:\nmov [rax], ecx\nadd rsi, 1\ncmp [rbp+0], esi\njg short loc_1480\nloc_14B8:\npop rbx\npop rbp\npop r12\nretn\nloc_14C0:\nmovsxd rax, dword ptr [rbp+0]\ncmp r12d, eax\njle short loc_14F0\nloc_14C9:\nlea edx, [rax+1]\nmov [rbp+0], edx\nmov [rdi+rax*4], ebx\nlea ebx, [rbx+rbx*2+1]\ntest bl, 1\njnz short loc_14C0\nsar ebx, 1\njmp loc_1450\nloc_14E8:\nmov rax, rdi\njmp short loc_14AD\nloc_14F0:\nadd r12d, r12d\nmovsxd rsi, r12d\nshl rsi, 2; size\ncall _realloc\nmov rdi, rax\nmovsxd rax, dword ptr [rbp+0]\njmp short loc_14C9", + "ida_strip_pseudo": "void __fastcall sub_1420(int a1, char *a2, int *a3)\n{\n char *v5; // rdi\n int v6; // r12d\n __int64 v7; // rsi\n int v8; // ecx\n __int64 v9; // rax\n int v10; // edx\n char *v11; // rax\n __int64 v12; // rax\n\n v5 = a2;\n *a3 = 1;\n *(_DWORD *)a2 = 1;\n if ( a1 != 1 )\n {\n v6 = 10;\n do\n {\n while ( a1 % 2 == 1 )\n {\n do\n {\n v12 = *a3;\n if ( v6 <= (int)v12 )\n {\n v6 *= 2;\n v5 = (char *)realloc(v5, 4LL * v6);\n v12 = *a3;\n }\n *a3 = v12 + 1;\n *(_DWORD *)&v5[4 * v12] = a1;\n a1 = 3 * a1 + 1;\n }\n while ( (a1 & 1) != 0 );\n a1 >>= 1;\n }\n a1 /= 2;\n }\n while ( a1 != 1 );\n }\n v7 = 1LL;\n if ( *a3 > 1 )\n {\n do\n {\n v8 = *(_DWORD *)&v5[4 * v7];\n v9 = v7 - 1;\n do\n {\n v10 = *(_DWORD *)&v5[4 * v9];\n if ( v10 <= v8 )\n {\n v11 = &v5[4 * (int)v9 + 4];\n goto LABEL_10;\n }\n *(_DWORD *)&v5[4 * v9-- + 4] = v10;\n }\n while ( (_DWORD)v9 != -1 );\n v11 = v5;\nLABEL_10:\n *(_DWORD *)v11 = v8;\n ++v7;\n }\n while ( *a3 > (int)v7 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1420(int a1, char *a2, int *a3) {\n char *v5;\n int v6;\n long long v7;\n int v8;\n long long v9;\n int v10;\n char *v11;\n long long v12;\n v5 = a2;\n *a3 = 1;\n *(uint32_t *)a2 = 1;\n if (a1 != 1) {\n v6 = 10;\n do {\n while (a1 % 2 == 1) {\n do {\n v12 = *a3;\n if (v6 <= (int)v12) {\n v6 *= 2;\n v5 = (char *)realloc(v5, 4LL * v6);\n v12 = *a3;\n }\n *a3 = v12 + 1;\n *(uint32_t *)&v5[4 * v12] = a1;\n a1 = 3 * a1 + 1;\n } while ((a1 & 1) != 0);\n a1 >>= 1;\n }\n a1 /= 2;\n } while (a1 != 1);\n }\n v7 = 1LL;\n if (*a3 > 1) {\n do {\n v8 = *(uint32_t *)&v5[4 * v7];\n v9 = v7 - 1;\n do {\n v10 = *(uint32_t *)&v5[4 * v9];\n if (v10 <= v8) {\n v11 = &v5[4 * (int)v9 + 4];\n goto LABEL_10;\n }\n *(uint32_t *)&v5[4 * v9-- + 4] = v10;\n } while ((uint32_t)v9 != -1);\n v11 = v5;\n LABEL_10:\n *(uint32_t *)v11 = v8;\n ++v7;\n } while (*a3 > (int)v7);\n }\n}", + "ida_pseudo_norm": "void func0(int a1, char *a2, int *a3) {\n char *v5;\n int v6;\n long long v7;\n int v8;\n long long v9;\n int v10;\n char *v11;\n long long v12;\n v5 = a2;\n *a3 = 1;\n *(uint32_t *)a2 = 1;\n if (a1 != 1) {\n v6 = 10;\n do {\n while (a1 % 2 == 1) {\n do {\n v12 = *a3;\n if (v6 <= (int)v12) {\n v6 *= 2;\n v5 = (char *)realloc(v5, 4LL * v6);\n v12 = *a3;\n }\n *a3 = v12 + 1;\n *(uint32_t *)&v5[4 * v12] = a1;\n a1 = 3 * a1 + 1;\n } while ((a1 & 1) != 0);\n a1 >>= 1;\n }\n a1 /= 2;\n } while (a1 != 1);\n }\n v7 = 1LL;\n if (*a3 > 1) {\n do {\n v8 = *(uint32_t *)&v5[4 * v7];\n v9 = v7 - 1;\n do {\n v10 = *(uint32_t *)&v5[4 * v9];\n if (v10 <= v8) {\n v11 = &v5[4 * (int)v9 + 4];\n goto LABEL_10;\n }\n *(uint32_t *)&v5[4 * v9-- + 4] = v10;\n } while ((uint32_t)v9 != -1);\n v11 = v5;\n LABEL_10:\n *(uint32_t *)v11 = v8;\n ++v7;\n } while (*a3 > (int)v7);\n }\n}" + }, + { + "index": "HumanEval-C-123", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(int n, int *out, int *size) {\n int capacity = 10;\n *size = 1;\n out[0] = 1;\n while (n != 1) {\n if (n % 2 == 1) {\n if (*size >= capacity) {\n capacity *= 2;\n out = (int *)realloc(out, capacity * sizeof(int));\n }\n out[(*size)++] = n;\n n = n * 3 + 1;\n } else {\n n = n / 2;\n }\n }\n for (int i = 1; i < *size; i++) {\n int key = out[i];\n int j = i - 1;\n while (j >= 0 && out[j] > key) {\n out[j + 1] = out[j];\n j = j - 1;\n }\n out[j + 1] = key;\n }\n}", + "test": "#include \n#include \n\nint issame(int *a, int size_a, int *b, int size_b) {\n if (size_a != size_b) return 0;\n for (int i = 0; i < size_a; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int size;\n int *result;\n\n // Test 1\n int expected1[] = {1, 5, 7, 11, 13, 17};\n result = (int*)malloc(100 * sizeof(int));\n func0(14, result, &size);\n assert(issame(result, size, expected1, 6));\n free(result);\n\n // Test 2\n int expected2[] = {1, 5};\n result = (int*)malloc(100 * sizeof(int));\n func0(5, result, &size);\n assert(issame(result, size, expected2, 2));\n free(result);\n\n // Test 3\n int expected3[] = {1, 3, 5};\n result = (int*)malloc(100 * sizeof(int));\n func0(12, result, &size);\n assert(issame(result, size, expected3, 3));\n free(result);\n\n // Test 4\n int expected4[] = {1};\n result = (int*)malloc(100 * sizeof(int));\n func0(1, result, &size);\n assert(issame(result, size, expected4, 1));\n free(result);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\nmov rbp, rdx\npush rbx\nmov ebx, edi\nmov rdi, rsi; ptr\nmov dword ptr [rdx], 1\nmov dword ptr [rsi], 1\ncmp ebx, 1\njz short loc_1472\nmov r12d, 0Ah\nnop word ptr [rax+rax+00000000h]\nloc_1450:\nmov edx, ebx\nshr edx, 1Fh\nlea eax, [rbx+rdx]\nand eax, 1\nsub eax, edx\ncmp eax, 1\njz short loc_14C0\nmov eax, ebx\nshr eax, 1Fh\nadd eax, ebx\nsar eax, 1\nmov ebx, eax\ncmp eax, 1\njnz short loc_1450\nloc_1472:\ncmp dword ptr [rbp+0], 1\nmov esi, 1\njle short loc_14B8\nnop dword ptr [rax]\nloc_1480:\nmov ecx, [rdi+rsi*4]\nlea rax, [rsi-1]\njmp short loc_149D\nloc_1490:\nmov [rdi+rax*4+4], edx\nsub rax, 1\ncmp eax, 0FFFFFFFFh\njz short loc_14E8\nloc_149D:\nmov edx, [rdi+rax*4]\ncmp edx, ecx\njg short loc_1490\nadd eax, 1\ncdqe\nlea rax, [rdi+rax*4]\nloc_14AD:\nmov [rax], ecx\nadd rsi, 1\ncmp [rbp+0], esi\njg short loc_1480\nloc_14B8:\npop rbx\npop rbp\npop r12\nretn\nloc_14C0:\nmovsxd rax, dword ptr [rbp+0]\ncmp r12d, eax\njle short loc_14F0\nloc_14C9:\nlea edx, [rax+1]\nmov [rbp+0], edx\nmov [rdi+rax*4], ebx\nlea ebx, [rbx+rbx*2+1]\ntest bl, 1\njnz short loc_14C0\nsar ebx, 1\njmp loc_1450\nloc_14E8:\nmov rax, rdi\njmp short loc_14AD\nloc_14F0:\nadd r12d, r12d\nmovsxd rsi, r12d\nshl rsi, 2; size\ncall _realloc\nmov rdi, rax\nmovsxd rax, dword ptr [rbp+0]\njmp short loc_14C9", + "ida_pseudo": "void __fastcall func0(int a1, char *a2, int *a3)\n{\n char *v5; // rdi\n int v6; // r12d\n __int64 v7; // rsi\n int v8; // ecx\n __int64 v9; // rax\n int v10; // edx\n char *v11; // rax\n __int64 v12; // rax\n\n v5 = a2;\n *a3 = 1;\n *(_DWORD *)a2 = 1;\n if ( a1 != 1 )\n {\n v6 = 10;\n do\n {\n while ( a1 % 2 == 1 )\n {\n do\n {\n v12 = *a3;\n if ( v6 <= (int)v12 )\n {\n v6 *= 2;\n v5 = (char *)realloc(v5, 4LL * v6);\n v12 = *a3;\n }\n *a3 = v12 + 1;\n *(_DWORD *)&v5[4 * v12] = a1;\n a1 = 3 * a1 + 1;\n }\n while ( (a1 & 1) != 0 );\n a1 >>= 1;\n }\n a1 /= 2;\n }\n while ( a1 != 1 );\n }\n v7 = 1LL;\n if ( *a3 > 1 )\n {\n do\n {\n v8 = *(_DWORD *)&v5[4 * v7];\n v9 = v7 - 1;\n do\n {\n v10 = *(_DWORD *)&v5[4 * v9];\n if ( v10 <= v8 )\n {\n v11 = &v5[4 * (int)v9 + 4];\n goto LABEL_10;\n }\n *(_DWORD *)&v5[4 * v9-- + 4] = v10;\n }\n while ( (_DWORD)v9 != -1 );\n v11 = v5;\nLABEL_10:\n *(_DWORD *)v11 = v8;\n ++v7;\n }\n while ( *a3 > (int)v7 );\n }\n}", + "ida_strip_asm": "sub_1420:\nendbr64\npush r12\npush rbp\nmov rbp, rdx\npush rbx\nmov ebx, edi\nmov rdi, rsi; ptr\nmov dword ptr [rdx], 1\nmov dword ptr [rsi], 1\ncmp ebx, 1\njz short loc_1472\nmov r12d, 0Ah\nnop word ptr [rax+rax+00000000h]\nloc_1450:\nmov edx, ebx\nshr edx, 1Fh\nlea eax, [rbx+rdx]\nand eax, 1\nsub eax, edx\ncmp eax, 1\njz short loc_14C0\nmov eax, ebx\nshr eax, 1Fh\nadd eax, ebx\nsar eax, 1\nmov ebx, eax\ncmp eax, 1\njnz short loc_1450\nloc_1472:\ncmp dword ptr [rbp+0], 1\nmov esi, 1\njle short loc_14B8\nnop dword ptr [rax]\nloc_1480:\nmov ecx, [rdi+rsi*4]\nlea rax, [rsi-1]\njmp short loc_149D\nloc_1490:\nmov [rdi+rax*4+4], edx\nsub rax, 1\ncmp eax, 0FFFFFFFFh\njz short loc_14E8\nloc_149D:\nmov edx, [rdi+rax*4]\ncmp edx, ecx\njg short loc_1490\nadd eax, 1\ncdqe\nlea rax, [rdi+rax*4]\nloc_14AD:\nmov [rax], ecx\nadd rsi, 1\ncmp [rbp+0], esi\njg short loc_1480\nloc_14B8:\npop rbx\npop rbp\npop r12\nretn\nloc_14C0:\nmovsxd rax, dword ptr [rbp+0]\ncmp r12d, eax\njle short loc_14F0\nloc_14C9:\nlea edx, [rax+1]\nmov [rbp+0], edx\nmov [rdi+rax*4], ebx\nlea ebx, [rbx+rbx*2+1]\ntest bl, 1\njnz short loc_14C0\nsar ebx, 1\njmp loc_1450\nloc_14E8:\nmov rax, rdi\njmp short loc_14AD\nloc_14F0:\nadd r12d, r12d\nmovsxd rsi, r12d\nshl rsi, 2; size\ncall _realloc\nmov rdi, rax\nmovsxd rax, dword ptr [rbp+0]\njmp short loc_14C9", + "ida_strip_pseudo": "void __fastcall sub_1420(int a1, char *a2, int *a3)\n{\n char *v5; // rdi\n int v6; // r12d\n __int64 v7; // rsi\n int v8; // ecx\n __int64 v9; // rax\n int v10; // edx\n char *v11; // rax\n __int64 v12; // rax\n\n v5 = a2;\n *a3 = 1;\n *(_DWORD *)a2 = 1;\n if ( a1 != 1 )\n {\n v6 = 10;\n do\n {\n while ( a1 % 2 == 1 )\n {\n do\n {\n v12 = *a3;\n if ( v6 <= (int)v12 )\n {\n v6 *= 2;\n v5 = (char *)realloc(v5, 4LL * v6);\n v12 = *a3;\n }\n *a3 = v12 + 1;\n *(_DWORD *)&v5[4 * v12] = a1;\n a1 = 3 * a1 + 1;\n }\n while ( (a1 & 1) != 0 );\n a1 >>= 1;\n }\n a1 /= 2;\n }\n while ( a1 != 1 );\n }\n v7 = 1LL;\n if ( *a3 > 1 )\n {\n do\n {\n v8 = *(_DWORD *)&v5[4 * v7];\n v9 = v7 - 1;\n do\n {\n v10 = *(_DWORD *)&v5[4 * v9];\n if ( v10 <= v8 )\n {\n v11 = &v5[4 * (int)v9 + 4];\n goto LABEL_10;\n }\n *(_DWORD *)&v5[4 * v9-- + 4] = v10;\n }\n while ( (_DWORD)v9 != -1 );\n v11 = v5;\nLABEL_10:\n *(_DWORD *)v11 = v8;\n ++v7;\n }\n while ( *a3 > (int)v7 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1420(int a1, char *a2, int *a3) {\n char *v5;\n int v6;\n long long v7;\n int v8;\n long long v9;\n int v10;\n char *v11;\n long long v12;\n v5 = a2;\n *a3 = 1;\n *(uint32_t *)a2 = 1;\n if (a1 != 1) {\n v6 = 10;\n do {\n while (a1 % 2 == 1) {\n do {\n v12 = *a3;\n if (v6 <= (int)v12) {\n v6 *= 2;\n v5 = (char *)realloc(v5, 4LL * v6);\n v12 = *a3;\n }\n *a3 = v12 + 1;\n *(uint32_t *)&v5[4 * v12] = a1;\n a1 = 3 * a1 + 1;\n } while ((a1 & 1) != 0);\n a1 >>= 1;\n }\n a1 /= 2;\n } while (a1 != 1);\n }\n v7 = 1LL;\n if (*a3 > 1) {\n do {\n v8 = *(uint32_t *)&v5[4 * v7];\n v9 = v7 - 1;\n do {\n v10 = *(uint32_t *)&v5[4 * v9];\n if (v10 <= v8) {\n v11 = &v5[4 * (int)v9 + 4];\n goto LABEL_10;\n }\n *(uint32_t *)&v5[4 * v9-- + 4] = v10;\n } while ((uint32_t)v9 != -1);\n v11 = v5;\n LABEL_10:\n *(uint32_t *)v11 = v8;\n ++v7;\n } while (*a3 > (int)v7);\n }\n}", + "ida_pseudo_norm": "void func0(int a1, char *a2, int *a3) {\n char *v5;\n int v6;\n long long v7;\n int v8;\n long long v9;\n int v10;\n char *v11;\n long long v12;\n v5 = a2;\n *a3 = 1;\n *(uint32_t *)a2 = 1;\n if (a1 != 1) {\n v6 = 10;\n do {\n while (a1 % 2 == 1) {\n do {\n v12 = *a3;\n if (v6 <= (int)v12) {\n v6 *= 2;\n v5 = (char *)realloc(v5, 4LL * v6);\n v12 = *a3;\n }\n *a3 = v12 + 1;\n *(uint32_t *)&v5[4 * v12] = a1;\n a1 = 3 * a1 + 1;\n } while ((a1 & 1) != 0);\n a1 >>= 1;\n }\n a1 /= 2;\n } while (a1 != 1);\n }\n v7 = 1LL;\n if (*a3 > 1) {\n do {\n v8 = *(uint32_t *)&v5[4 * v7];\n v9 = v7 - 1;\n do {\n v10 = *(uint32_t *)&v5[4 * v9];\n if (v10 <= v8) {\n v11 = &v5[4 * (int)v9 + 4];\n goto LABEL_10;\n }\n *(uint32_t *)&v5[4 * v9-- + 4] = v10;\n } while ((uint32_t)v9 != -1);\n v11 = v5;\n LABEL_10:\n *(uint32_t *)v11 = v8;\n ++v7;\n } while (*a3 > (int)v7);\n }\n}" + }, + { + "index": "HumanEval-C-124", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int func0(const char *date) {\n int mm, dd, yy;\n if (strlen(date) != 10) return 0;\n for (int i = 0; i < 10; i++) {\n if (i == 2 || i == 5) {\n if (date[i] != '-') return 0;\n } else {\n if (date[i] < '0' || date[i] > '9') return 0;\n }\n }\n char str_month[3] = {date[0], date[1], '\\0'};\n char str_day[3] = {date[3], date[4], '\\0'};\n char str_year[5] = {date[6], date[7], date[8], date[9], '\\0'};\n mm = atoi(str_month);\n dd = atoi(str_day);\n yy = atoi(str_year);\n if (mm < 1 || mm > 12) return 0;\n if (dd < 1 || dd > 31) return 0;\n if ((mm == 4 || mm == 6 || mm == 9 || mm == 11) && dd == 31) return 0;\n if (mm == 2 && dd > 29) return 0;\n return 1;\n}", + "test": "#include \n\n\nint main() {\n assert(func0(\"03-11-2000\") == 1);\n assert(func0(\"15-01-2012\") == 0);\n assert(func0(\"04-0-2040\") == 0);\n assert(func0(\"06-04-2020\") == 1);\n assert(func0(\"01-01-2007\") == 1);\n assert(func0(\"03-32-2011\") == 0);\n assert(func0(\"\") == 0);\n assert(func0(\"04-31-3000\") == 0);\n assert(func0(\"06-06-2005\") == 1);\n assert(func0(\"21-31-2000\") == 0);\n assert(func0(\"04-12-2003\") == 1);\n assert(func0(\"04122003\") == 0);\n assert(func0(\"20030412\") == 0);\n assert(func0(\"2003-04\") == 0);\n assert(func0(\"2003-04-12\") == 0);\n assert(func0(\"04-2003\") == 0);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+s], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rax, 0Ah\njz short loc_11E4\nmov eax, 0\njmp loc_135B\nloc_11E4:\nmov [rbp+var_24], 0\njmp short loc_124D\nloc_11ED:\ncmp [rbp+var_24], 2\njz short loc_11F9\ncmp [rbp+var_24], 5\njnz short loc_1217\nloc_11F9:\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 2Dh ; '-'\njz short loc_1249\nmov eax, 0\njmp loc_135B\nloc_1217:\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 2Fh ; '/'\njle short loc_123F\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 39h ; '9'\njle short loc_1249\nloc_123F:\nmov eax, 0\njmp loc_135B\nloc_1249:\nadd [rbp+var_24], 1\nloc_124D:\ncmp [rbp+var_24], 9\njle short loc_11ED\nmov rax, [rbp+s]\nmovzx eax, byte ptr [rax]\nmov [rbp+nptr], al\nmov rax, [rbp+s]\nadd rax, 1\nmovzx eax, byte ptr [rax]\nmov [rbp+var_12], al\nmov [rbp+var_11], 0\nmov rax, [rbp+s]\nadd rax, 3\nmovzx eax, byte ptr [rax]\nmov [rbp+var_10], al\nmov rax, [rbp+s]\nadd rax, 4\nmovzx eax, byte ptr [rax]\nmov [rbp+var_F], al\nmov [rbp+var_E], 0\nmov rax, [rbp+s]\nadd rax, 6\nmovzx eax, byte ptr [rax]\nmov [rbp+var_D], al\nmov rax, [rbp+s]\nadd rax, 7\nmovzx eax, byte ptr [rax]\nmov [rbp+var_C], al\nmov rax, [rbp+s]\nadd rax, 8\nmovzx eax, byte ptr [rax]\nmov [rbp+var_B], al\nmov rax, [rbp+s]\nadd rax, 9\nmovzx eax, byte ptr [rax]\nmov [rbp+var_A], al\nmov [rbp+var_9], 0\nlea rax, [rbp+nptr]\nmov rdi, rax; nptr\ncall _atoi\nmov [rbp+var_20], eax\nlea rax, [rbp+var_10]\nmov rdi, rax; nptr\ncall _atoi\nmov [rbp+var_1C], eax\nlea rax, [rbp+var_D]\nmov rdi, rax; nptr\ncall _atoi\nmov [rbp+var_18], eax\ncmp [rbp+var_20], 0\njle short loc_1304\ncmp [rbp+var_20], 0Ch\njle short loc_130B\nloc_1304:\nmov eax, 0\njmp short loc_135B\nloc_130B:\ncmp [rbp+var_1C], 0\njle short loc_1317\ncmp [rbp+var_1C], 1Fh\njle short loc_131E\nloc_1317:\nmov eax, 0\njmp short loc_135B\nloc_131E:\ncmp [rbp+var_20], 4\njz short loc_1336\ncmp [rbp+var_20], 6\njz short loc_1336\ncmp [rbp+var_20], 9\njz short loc_1336\ncmp [rbp+var_20], 0Bh\njnz short loc_1343\nloc_1336:\ncmp [rbp+var_1C], 1Fh\njnz short loc_1343\nmov eax, 0\njmp short loc_135B\nloc_1343:\ncmp [rbp+var_20], 2\njnz short loc_1356\ncmp [rbp+var_1C], 1Dh\njle short loc_1356\nmov eax, 0\njmp short loc_135B\nloc_1356:\nmov eax, 1\nloc_135B:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_136F\ncall ___stack_chk_fail\nlocret_136F:\nleave\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(__int64 a1)\n{\n int i; // [rsp+1Ch] [rbp-24h]\n int v3; // [rsp+20h] [rbp-20h]\n int v4; // [rsp+24h] [rbp-1Ch]\n char nptr[3]; // [rsp+2Dh] [rbp-13h] BYREF\n char v6[3]; // [rsp+30h] [rbp-10h] BYREF\n char v7[5]; // [rsp+33h] [rbp-Dh] BYREF\n unsigned __int64 v8; // [rsp+38h] [rbp-8h]\n\n v8 = __readfsqword(0x28u);\n if ( strlen((const char *)a1) != 10 )\n return 0LL;\n for ( i = 0; i <= 9; ++i )\n {\n if ( i == 2 || i == 5 )\n {\n if ( *(_BYTE *)(i + a1) != 45 )\n return 0LL;\n }\n else if ( *(char *)(i + a1) <= 47 || *(char *)(i + a1) > 57 )\n {\n return 0LL;\n }\n }\n nptr[0] = *(_BYTE *)a1;\n nptr[1] = *(_BYTE *)(a1 + 1);\n nptr[2] = 0;\n v6[0] = *(_BYTE *)(a1 + 3);\n v6[1] = *(_BYTE *)(a1 + 4);\n v6[2] = 0;\n v7[0] = *(_BYTE *)(a1 + 6);\n v7[1] = *(_BYTE *)(a1 + 7);\n v7[2] = *(_BYTE *)(a1 + 8);\n v7[3] = *(_BYTE *)(a1 + 9);\n v7[4] = 0;\n v3 = atoi(nptr);\n v4 = atoi(v6);\n atoi(v7);\n if ( v3 <= 0 || v3 > 12 )\n return 0LL;\n if ( v4 <= 0 || v4 > 31 )\n return 0LL;\n if ( (v3 == 4 || v3 == 6 || v3 == 9 || v3 == 11) && v4 == 31 )\n return 0LL;\n return v3 != 2 || v4 <= 29;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+s], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rax, 0Ah\njz short loc_11E4\nmov eax, 0\njmp loc_135B\nloc_11E4:\nmov [rbp+var_24], 0\njmp short loc_124D\nloc_11ED:\ncmp [rbp+var_24], 2\njz short loc_11F9\ncmp [rbp+var_24], 5\njnz short loc_1217\nloc_11F9:\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 2Dh ; '-'\njz short loc_1249\nmov eax, 0\njmp loc_135B\nloc_1217:\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 2Fh ; '/'\njle short loc_123F\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 39h ; '9'\njle short loc_1249\nloc_123F:\nmov eax, 0\njmp loc_135B\nloc_1249:\nadd [rbp+var_24], 1\nloc_124D:\ncmp [rbp+var_24], 9\njle short loc_11ED\nmov rax, [rbp+s]\nmovzx eax, byte ptr [rax]\nmov [rbp+nptr], al\nmov rax, [rbp+s]\nadd rax, 1\nmovzx eax, byte ptr [rax]\nmov [rbp+var_12], al\nmov [rbp+var_11], 0\nmov rax, [rbp+s]\nadd rax, 3\nmovzx eax, byte ptr [rax]\nmov [rbp+var_10], al\nmov rax, [rbp+s]\nadd rax, 4\nmovzx eax, byte ptr [rax]\nmov [rbp+var_F], al\nmov [rbp+var_E], 0\nmov rax, [rbp+s]\nadd rax, 6\nmovzx eax, byte ptr [rax]\nmov [rbp+var_D], al\nmov rax, [rbp+s]\nadd rax, 7\nmovzx eax, byte ptr [rax]\nmov [rbp+var_C], al\nmov rax, [rbp+s]\nadd rax, 8\nmovzx eax, byte ptr [rax]\nmov [rbp+var_B], al\nmov rax, [rbp+s]\nadd rax, 9\nmovzx eax, byte ptr [rax]\nmov [rbp+var_A], al\nmov [rbp+var_9], 0\nlea rax, [rbp+nptr]\nmov rdi, rax; nptr\ncall _atoi\nmov [rbp+var_20], eax\nlea rax, [rbp+var_10]\nmov rdi, rax; nptr\ncall _atoi\nmov [rbp+var_1C], eax\nlea rax, [rbp+var_D]\nmov rdi, rax; nptr\ncall _atoi\nmov [rbp+var_18], eax\ncmp [rbp+var_20], 0\njle short loc_1304\ncmp [rbp+var_20], 0Ch\njle short loc_130B\nloc_1304:\nmov eax, 0\njmp short loc_135B\nloc_130B:\ncmp [rbp+var_1C], 0\njle short loc_1317\ncmp [rbp+var_1C], 1Fh\njle short loc_131E\nloc_1317:\nmov eax, 0\njmp short loc_135B\nloc_131E:\ncmp [rbp+var_20], 4\njz short loc_1336\ncmp [rbp+var_20], 6\njz short loc_1336\ncmp [rbp+var_20], 9\njz short loc_1336\ncmp [rbp+var_20], 0Bh\njnz short loc_1343\nloc_1336:\ncmp [rbp+var_1C], 1Fh\njnz short loc_1343\nmov eax, 0\njmp short loc_135B\nloc_1343:\ncmp [rbp+var_20], 2\njnz short loc_1356\ncmp [rbp+var_1C], 1Dh\njle short loc_1356\nmov eax, 0\njmp short loc_135B\nloc_1356:\nmov eax, 1\nloc_135B:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_136F\ncall ___stack_chk_fail\nlocret_136F:\nleave\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_11A9(__int64 a1)\n{\n int i; // [rsp+1Ch] [rbp-24h]\n int v3; // [rsp+20h] [rbp-20h]\n int v4; // [rsp+24h] [rbp-1Ch]\n char nptr[3]; // [rsp+2Dh] [rbp-13h] BYREF\n char v6[3]; // [rsp+30h] [rbp-10h] BYREF\n char v7[5]; // [rsp+33h] [rbp-Dh] BYREF\n unsigned __int64 v8; // [rsp+38h] [rbp-8h]\n\n v8 = __readfsqword(0x28u);\n if ( strlen((const char *)a1) != 10 )\n return 0LL;\n for ( i = 0; i <= 9; ++i )\n {\n if ( i == 2 || i == 5 )\n {\n if ( *(_BYTE *)(i + a1) != 45 )\n return 0LL;\n }\n else if ( *(char *)(i + a1) <= 47 || *(char *)(i + a1) > 57 )\n {\n return 0LL;\n }\n }\n nptr[0] = *(_BYTE *)a1;\n nptr[1] = *(_BYTE *)(a1 + 1);\n nptr[2] = 0;\n v6[0] = *(_BYTE *)(a1 + 3);\n v6[1] = *(_BYTE *)(a1 + 4);\n v6[2] = 0;\n v7[0] = *(_BYTE *)(a1 + 6);\n v7[1] = *(_BYTE *)(a1 + 7);\n v7[2] = *(_BYTE *)(a1 + 8);\n v7[3] = *(_BYTE *)(a1 + 9);\n v7[4] = 0;\n v3 = atoi(nptr);\n v4 = atoi(v6);\n atoi(v7);\n if ( v3 <= 0 || v3 > 12 )\n return 0LL;\n if ( v4 <= 0 || v4 > 31 )\n return 0LL;\n if ( (v3 == 4 || v3 == 6 || v3 == 9 || v3 == 11) && v4 == 31 )\n return 0LL;\n return v3 != 2 || v4 <= 29;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_11A9(long long a1) {\n int i;\n int v3;\n int v4;\n char nptr[3];\n char v6[3];\n char v7[5];\n unsigned long long v8;\n v8 = __readfsqword(40u);\n if (strlen((const char *)a1) != 10) return 0LL;\n for (i = 0; i <= 9; ++i) {\n if (i == 2 || i == 5) {\n if (*(uint8_t *)(i + a1) != 45) return 0LL;\n } else if (*(char *)(i + a1) <= 47 || *(char *)(i + a1) > 57) {\n return 0LL;\n }\n }\n nptr[0] = *(uint8_t *)a1;\n nptr[1] = *(uint8_t *)(a1 + 1);\n nptr[2] = 0;\n v6[0] = *(uint8_t *)(a1 + 3);\n v6[1] = *(uint8_t *)(a1 + 4);\n v6[2] = 0;\n v7[0] = *(uint8_t *)(a1 + 6);\n v7[1] = *(uint8_t *)(a1 + 7);\n v7[2] = *(uint8_t *)(a1 + 8);\n v7[3] = *(uint8_t *)(a1 + 9);\n v7[4] = 0;\n v3 = atoi(nptr);\n v4 = atoi(v6);\n atoi(v7);\n if (v3 <= 0 || v3 > 12) return 0LL;\n if (v4 <= 0 || v4 > 31) return 0LL;\n if ((v3 == 4 || v3 == 6 || v3 == 9 || v3 == 11) && v4 == 31) return 0LL;\n return v3 != 2 || v4 <= 29;\n}", + "ida_pseudo_norm": "uint8_t func0(long long a1) {\n int i;\n int v3;\n int v4;\n char nptr[3];\n char v6[3];\n char v7[5];\n unsigned long long v8;\n v8 = __readfsqword(40u);\n if (strlen((const char *)a1) != 10) return 0LL;\n for (i = 0; i <= 9; ++i) {\n if (i == 2 || i == 5) {\n if (*(uint8_t *)(i + a1) != 45) return 0LL;\n } else if (*(char *)(i + a1) <= 47 || *(char *)(i + a1) > 57) {\n return 0LL;\n }\n }\n nptr[0] = *(uint8_t *)a1;\n nptr[1] = *(uint8_t *)(a1 + 1);\n nptr[2] = 0;\n v6[0] = *(uint8_t *)(a1 + 3);\n v6[1] = *(uint8_t *)(a1 + 4);\n v6[2] = 0;\n v7[0] = *(uint8_t *)(a1 + 6);\n v7[1] = *(uint8_t *)(a1 + 7);\n v7[2] = *(uint8_t *)(a1 + 8);\n v7[3] = *(uint8_t *)(a1 + 9);\n v7[4] = 0;\n v3 = atoi(nptr);\n v4 = atoi(v6);\n atoi(v7);\n if (v3 <= 0 || v3 > 12) return 0LL;\n if (v4 <= 0 || v4 > 31) return 0LL;\n if ((v3 == 4 || v3 == 6 || v3 == 9 || v3 == 11) && v4 == 31) return 0LL;\n return v3 != 2 || v4 <= 29;\n}" + }, + { + "index": "HumanEval-C-124", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int func0(const char *date) {\n int mm, dd, yy;\n if (strlen(date) != 10) return 0;\n for (int i = 0; i < 10; i++) {\n if (i == 2 || i == 5) {\n if (date[i] != '-') return 0;\n } else {\n if (date[i] < '0' || date[i] > '9') return 0;\n }\n }\n char str_month[3] = {date[0], date[1], '\\0'};\n char str_day[3] = {date[3], date[4], '\\0'};\n char str_year[5] = {date[6], date[7], date[8], date[9], '\\0'};\n mm = atoi(str_month);\n dd = atoi(str_day);\n yy = atoi(str_year);\n if (mm < 1 || mm > 12) return 0;\n if (dd < 1 || dd > 31) return 0;\n if ((mm == 4 || mm == 6 || mm == 9 || mm == 11) && dd == 31) return 0;\n if (mm == 2 && dd > 29) return 0;\n return 1;\n}", + "test": "#include \n\n\nint main() {\n assert(func0(\"03-11-2000\") == 1);\n assert(func0(\"15-01-2012\") == 0);\n assert(func0(\"04-0-2040\") == 0);\n assert(func0(\"06-04-2020\") == 1);\n assert(func0(\"01-01-2007\") == 1);\n assert(func0(\"03-32-2011\") == 0);\n assert(func0(\"\") == 0);\n assert(func0(\"04-31-3000\") == 0);\n assert(func0(\"06-06-2005\") == 1);\n assert(func0(\"21-31-2000\") == 0);\n assert(func0(\"04-12-2003\") == 1);\n assert(func0(\"04122003\") == 0);\n assert(func0(\"20030412\") == 0);\n assert(func0(\"2003-04\") == 0);\n assert(func0(\"2003-04-12\") == 0);\n assert(func0(\"04-2003\") == 0);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 28h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+38h+var_20], rax\nxor eax, eax\ncall _strlen\nmov rdx, rax\nmov eax, 0\ncmp rdx, 0Ah\njnz loc_12E9\nmov eax, 0\njmp short loc_11F2\nloc_11E4:\ncmp byte ptr [rbx+rax], 2Dh ; '-'\njnz loc_1300\nadd rax, 1\nloc_11F2:\ncmp eax, 2\njz short loc_11E4\ncmp eax, 5\njz short loc_11E4\nmovzx ecx, byte ptr [rbx+rax]\nlea edx, [rcx-30h]\ncmp dl, 9\nja loc_1307\nadd rax, 1\ncmp rax, 0Ah\njnz short loc_11F2\nmovzx eax, byte ptr [rbx]\nmov [rsp+38h+nptr], al\nmovzx eax, byte ptr [rbx+1]\nmov [rsp+38h+var_2A], al\nmov [rsp+38h+var_29], 0\nmovzx eax, byte ptr [rbx+3]\nmov [rsp+38h+var_28], al\nmovzx eax, byte ptr [rbx+4]\nmov [rsp+38h+var_27], al\nmov [rsp+38h+var_26], 0\nmovzx eax, byte ptr [rbx+6]\nmov [rsp+38h+var_25], al\nmovzx eax, byte ptr [rbx+7]\nmov [rsp+38h+var_24], al\nmovzx eax, byte ptr [rbx+8]\nmov [rsp+38h+var_23], al\nmovzx eax, byte ptr [rbx+9]\nmov [rsp+38h+var_22], al\nmov [rsp+38h+var_21], 0\nlea rdi, [rsp+38h+nptr]; nptr\nmov edx, 0Ah; base\nmov esi, 0; endptr\ncall _strtol\nmov rbx, rax\nlea rdi, [rsp+38h+var_28]; nptr\nmov edx, 0Ah; base\nmov esi, 0; endptr\ncall _strtol\nmov rbp, rax\nlea rdi, [rsp+38h+var_25]; nptr\nmov edx, 0Ah; base\nmov esi, 0; endptr\ncall _strtol\nlea edx, [rbx-1]\nmov eax, 0\ncmp edx, 0Bh\nja short loc_12E9\nlea edx, [rbp-1]\ncmp edx, 1Eh\nja short loc_12E9\ncmp ebx, 0Bh\nja short loc_12D5\nmov eax, 0A50h\nbt rax, rbx\njnb short loc_12D5\nmov eax, 0\ncmp ebp, 1Fh\njz short loc_12E9\nloc_12D5:\ncmp ebx, 2\nsetz al\ncmp ebp, 1Dh\nsetnle dl\nand eax, edx\nxor eax, 1\nmovzx eax, al\nloc_12E9:\nmov rdx, [rsp+38h+var_20]\nsub rdx, fs:28h\njnz short loc_130E\nadd rsp, 28h\npop rbx\npop rbp\nretn\nloc_1300:\nmov eax, 0\njmp short loc_12E9\nloc_1307:\nmov eax, 0\njmp short loc_12E9\nloc_130E:\ncall ___stack_chk_fail", + "ida_pseudo": "_BOOL8 __fastcall func0(__int64 a1)\n{\n size_t v1; // rdx\n _BOOL8 result; // rax\n __int64 i; // rax\n unsigned __int64 v4; // rbx\n int v5; // ebp\n __int64 v6; // rax\n char nptr[3]; // [rsp+Dh] [rbp-2Bh] BYREF\n char v8[3]; // [rsp+10h] [rbp-28h] BYREF\n char v9[5]; // [rsp+13h] [rbp-25h] BYREF\n unsigned __int64 v10; // [rsp+18h] [rbp-20h]\n\n v10 = __readfsqword(0x28u);\n v1 = strlen((const char *)a1);\n result = 0LL;\n if ( v1 == 10 )\n {\n for ( i = 0LL; i != 10; ++i )\n {\n while ( (_DWORD)i == 2 || (_DWORD)i == 5 )\n {\n if ( *(_BYTE *)(a1 + i) != 45 )\n return 0LL;\n ++i;\n }\n if ( (unsigned __int8)(*(_BYTE *)(a1 + i) - 48) > 9u )\n return 0LL;\n }\n nptr[0] = *(_BYTE *)a1;\n nptr[1] = *(_BYTE *)(a1 + 1);\n nptr[2] = 0;\n v8[0] = *(_BYTE *)(a1 + 3);\n v8[1] = *(_BYTE *)(a1 + 4);\n v8[2] = 0;\n v9[0] = *(_BYTE *)(a1 + 6);\n v9[1] = *(_BYTE *)(a1 + 7);\n v9[2] = *(_BYTE *)(a1 + 8);\n v9[3] = *(_BYTE *)(a1 + 9);\n v9[4] = 0;\n v4 = strtol(nptr, 0LL, 10);\n v5 = strtol(v8, 0LL, 10);\n strtol(v9, 0LL, 10);\n result = 0LL;\n if ( (unsigned int)(v4 - 1) <= 0xB && (unsigned int)(v5 - 1) <= 0x1E )\n {\n if ( (unsigned int)v4 > 0xB )\n return v5 <= 29 || (_DWORD)v4 != 2;\n v6 = 2640LL;\n if ( !_bittest64(&v6, v4) )\n return v5 <= 29 || (_DWORD)v4 != 2;\n result = 0LL;\n if ( v5 != 31 )\n return v5 <= 29 || (_DWORD)v4 != 2;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\npush rbx\nsub rsp, 28h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+38h+var_20], rax\nxor eax, eax\ncall _strlen\nmov rdx, rax\nmov eax, 0\ncmp rdx, 0Ah\njnz loc_12E9\nmov eax, 0\njmp short loc_11F2\nloc_11E4:\ncmp byte ptr [rbx+rax], 2Dh ; '-'\njnz loc_1300\nadd rax, 1\nloc_11F2:\ncmp eax, 2\njz short loc_11E4\ncmp eax, 5\njz short loc_11E4\nmovzx ecx, byte ptr [rbx+rax]\nlea edx, [rcx-30h]\ncmp dl, 9\nja loc_1307\nadd rax, 1\ncmp rax, 0Ah\njnz short loc_11F2\nmovzx eax, byte ptr [rbx]\nmov [rsp+38h+nptr], al\nmovzx eax, byte ptr [rbx+1]\nmov [rsp+38h+var_2A], al\nmov [rsp+38h+var_29], 0\nmovzx eax, byte ptr [rbx+3]\nmov [rsp+38h+var_28], al\nmovzx eax, byte ptr [rbx+4]\nmov [rsp+38h+var_27], al\nmov [rsp+38h+var_26], 0\nmovzx eax, byte ptr [rbx+6]\nmov [rsp+38h+var_25], al\nmovzx eax, byte ptr [rbx+7]\nmov [rsp+38h+var_24], al\nmovzx eax, byte ptr [rbx+8]\nmov [rsp+38h+var_23], al\nmovzx eax, byte ptr [rbx+9]\nmov [rsp+38h+var_22], al\nmov [rsp+38h+var_21], 0\nlea rdi, [rsp+38h+nptr]; nptr\nmov edx, 0Ah; base\nmov esi, 0; endptr\ncall _strtol\nmov rbx, rax\nlea rdi, [rsp+38h+var_28]; nptr\nmov edx, 0Ah; base\nmov esi, 0; endptr\ncall _strtol\nmov rbp, rax\nlea rdi, [rsp+38h+var_25]; nptr\nmov edx, 0Ah; base\nmov esi, 0; endptr\ncall _strtol\nlea edx, [rbx-1]\nmov eax, 0\ncmp edx, 0Bh\nja short loc_12E9\nlea edx, [rbp-1]\ncmp edx, 1Eh\nja short loc_12E9\ncmp ebx, 0Bh\nja short loc_12D5\nmov eax, 0A50h\nbt rax, rbx\njnb short loc_12D5\nmov eax, 0\ncmp ebp, 1Fh\njz short loc_12E9\nloc_12D5:\ncmp ebx, 2\nsetz al\ncmp ebp, 1Dh\nsetnle dl\nand eax, edx\nxor eax, 1\nmovzx eax, al\nloc_12E9:\nmov rdx, [rsp+38h+var_20]\nsub rdx, fs:28h\njnz short loc_130E\nadd rsp, 28h\npop rbx\npop rbp\nretn\nloc_1300:\nmov eax, 0\njmp short loc_12E9\nloc_1307:\nmov eax, 0\njmp short loc_12E9\nloc_130E:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_11A9(__int64 a1)\n{\n size_t v1; // rdx\n _BOOL8 result; // rax\n __int64 i; // rax\n unsigned __int64 v4; // rbx\n int v5; // ebp\n __int64 v6; // rax\n char nptr[3]; // [rsp+Dh] [rbp-2Bh] BYREF\n char v8[3]; // [rsp+10h] [rbp-28h] BYREF\n char v9[5]; // [rsp+13h] [rbp-25h] BYREF\n unsigned __int64 v10; // [rsp+18h] [rbp-20h]\n\n v10 = __readfsqword(0x28u);\n v1 = strlen((const char *)a1);\n result = 0LL;\n if ( v1 == 10 )\n {\n for ( i = 0LL; i != 10; ++i )\n {\n while ( (_DWORD)i == 2 || (_DWORD)i == 5 )\n {\n if ( *(_BYTE *)(a1 + i) != 45 )\n return 0LL;\n ++i;\n }\n if ( (unsigned __int8)(*(_BYTE *)(a1 + i) - 48) > 9u )\n return 0LL;\n }\n nptr[0] = *(_BYTE *)a1;\n nptr[1] = *(_BYTE *)(a1 + 1);\n nptr[2] = 0;\n v8[0] = *(_BYTE *)(a1 + 3);\n v8[1] = *(_BYTE *)(a1 + 4);\n v8[2] = 0;\n v9[0] = *(_BYTE *)(a1 + 6);\n v9[1] = *(_BYTE *)(a1 + 7);\n v9[2] = *(_BYTE *)(a1 + 8);\n v9[3] = *(_BYTE *)(a1 + 9);\n v9[4] = 0;\n v4 = strtol(nptr, 0LL, 10);\n v5 = strtol(v8, 0LL, 10);\n strtol(v9, 0LL, 10);\n result = 0LL;\n if ( (unsigned int)(v4 - 1) <= 0xB && (unsigned int)(v5 - 1) <= 0x1E )\n {\n if ( (unsigned int)v4 > 0xB )\n return v5 <= 29 || (_DWORD)v4 != 2;\n v6 = 2640LL;\n if ( !_bittest64(&v6, v4) )\n return v5 <= 29 || (_DWORD)v4 != 2;\n result = 0LL;\n if ( v5 != 31 )\n return v5 <= 29 || (_DWORD)v4 != 2;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_11A9(long long a1) {\n unsigned int v1;\n uint8_t result;\n long long i;\n unsigned long long v4;\n int v5;\n long long v6;\n char nptr[3];\n char v8[3];\n char v9[5];\n unsigned long long v10;\n v10 = __readfsqword(40u);\n v1 = strlen((const char *)a1);\n result = 0LL;\n if (v1 == 10) {\n for (i = 0LL; i != 10; ++i) {\n while ((uint32_t)i == 2 || (uint32_t)i == 5) {\n if (*(uint8_t *)(a1 + i) != 45) return 0LL;\n ++i;\n }\n if ((unsigned char)(*(uint8_t *)(a1 + i) - 48) > 9u) return 0LL;\n }\n nptr[0] = *(uint8_t *)a1;\n nptr[1] = *(uint8_t *)(a1 + 1);\n nptr[2] = 0;\n v8[0] = *(uint8_t *)(a1 + 3);\n v8[1] = *(uint8_t *)(a1 + 4);\n v8[2] = 0;\n v9[0] = *(uint8_t *)(a1 + 6);\n v9[1] = *(uint8_t *)(a1 + 7);\n v9[2] = *(uint8_t *)(a1 + 8);\n v9[3] = *(uint8_t *)(a1 + 9);\n v9[4] = 0;\n v4 = strtol(nptr, 0LL, 10);\n v5 = strtol(v8, 0LL, 10);\n strtol(v9, 0LL, 10);\n result = 0LL;\n if ((unsigned int)(v4 - 1) <= 11 && (unsigned int)(v5 - 1) <= 30) {\n if ((unsigned int)v4 > 11) return v5 <= 29 || (uint32_t)v4 != 2;\n v6 = 2640LL;\n if (!_bittest64(&v6, v4)) return v5 <= 29 || (uint32_t)v4 != 2;\n result = 0LL;\n if (v5 != 31) return v5 <= 29 || (uint32_t)v4 != 2;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "uint8_t func0(long long a1) {\n unsigned int v1;\n uint8_t result;\n long long i;\n unsigned long long v4;\n int v5;\n long long v6;\n char nptr[3];\n char v8[3];\n char v9[5];\n unsigned long long v10;\n v10 = __readfsqword(40u);\n v1 = strlen((const char *)a1);\n result = 0LL;\n if (v1 == 10) {\n for (i = 0LL; i != 10; ++i) {\n while ((uint32_t)i == 2 || (uint32_t)i == 5) {\n if (*(uint8_t *)(a1 + i) != 45) return 0LL;\n ++i;\n }\n if ((unsigned char)(*(uint8_t *)(a1 + i) - 48) > 9u) return 0LL;\n }\n nptr[0] = *(uint8_t *)a1;\n nptr[1] = *(uint8_t *)(a1 + 1);\n nptr[2] = 0;\n v8[0] = *(uint8_t *)(a1 + 3);\n v8[1] = *(uint8_t *)(a1 + 4);\n v8[2] = 0;\n v9[0] = *(uint8_t *)(a1 + 6);\n v9[1] = *(uint8_t *)(a1 + 7);\n v9[2] = *(uint8_t *)(a1 + 8);\n v9[3] = *(uint8_t *)(a1 + 9);\n v9[4] = 0;\n v4 = strtol(nptr, 0LL, 10);\n v5 = strtol(v8, 0LL, 10);\n strtol(v9, 0LL, 10);\n result = 0LL;\n if ((unsigned int)(v4 - 1) <= 11 && (unsigned int)(v5 - 1) <= 30) {\n if ((unsigned int)v4 > 11) return v5 <= 29 || (uint32_t)v4 != 2;\n v6 = 2640LL;\n if (!_bittest64(&v6, v4)) return v5 <= 29 || (uint32_t)v4 != 2;\n result = 0LL;\n if (v5 != 31) return v5 <= 29 || (uint32_t)v4 != 2;\n }\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-124", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int func0(const char *date) {\n int mm, dd, yy;\n if (strlen(date) != 10) return 0;\n for (int i = 0; i < 10; i++) {\n if (i == 2 || i == 5) {\n if (date[i] != '-') return 0;\n } else {\n if (date[i] < '0' || date[i] > '9') return 0;\n }\n }\n char str_month[3] = {date[0], date[1], '\\0'};\n char str_day[3] = {date[3], date[4], '\\0'};\n char str_year[5] = {date[6], date[7], date[8], date[9], '\\0'};\n mm = atoi(str_month);\n dd = atoi(str_day);\n yy = atoi(str_year);\n if (mm < 1 || mm > 12) return 0;\n if (dd < 1 || dd > 31) return 0;\n if ((mm == 4 || mm == 6 || mm == 9 || mm == 11) && dd == 31) return 0;\n if (mm == 2 && dd > 29) return 0;\n return 1;\n}", + "test": "#include \n\n\nint main() {\n assert(func0(\"03-11-2000\") == 1);\n assert(func0(\"15-01-2012\") == 0);\n assert(func0(\"04-0-2040\") == 0);\n assert(func0(\"06-04-2020\") == 1);\n assert(func0(\"01-01-2007\") == 1);\n assert(func0(\"03-32-2011\") == 0);\n assert(func0(\"\") == 0);\n assert(func0(\"04-31-3000\") == 0);\n assert(func0(\"06-06-2005\") == 1);\n assert(func0(\"21-31-2000\") == 0);\n assert(func0(\"04-12-2003\") == 1);\n assert(func0(\"04122003\") == 0);\n assert(func0(\"20030412\") == 0);\n assert(func0(\"2003-04\") == 0);\n assert(func0(\"2003-04-12\") == 0);\n assert(func0(\"04-2003\") == 0);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 28h\nmov rax, fs:28h\nmov [rsp+38h+var_20], rax\nxor eax, eax\ncall _strlen\ncmp rax, 0Ah\njnz short loc_1550\nxor eax, eax\nmov ecx, 24h ; '$'\njmp short loc_1537\nloc_1528:\ncmp dl, 2Dh ; '-'\njnz short loc_1550\nloc_152D:\nadd rax, 1\ncmp rax, 0Ah\njz short loc_1570\nloc_1537:\nbt rcx, rax\nmovzx edx, byte ptr [rbx+rax]\njb short loc_1528\nsub edx, 30h ; '0'\ncmp dl, 9\njbe short loc_152D\nnop dword ptr [rax+00000000h]\nloc_1550:\nxor eax, eax\nloc_1552:\nmov rdx, [rsp+38h+var_20]\nsub rdx, fs:28h\njnz loc_1621\nadd rsp, 28h\npop rbx\npop rbp\nretn\nloc_1570:\nmovzx eax, word ptr [rbx]\nlea rdi, [rsp+38h+nptr]; nptr\nmov edx, 0Ah; base\nxor esi, esi; endptr\nmov [rsp+38h+var_2E], 0\nmov word ptr [rsp+38h+nptr], ax\nmovzx eax, word ptr [rbx+3]\nmov [rsp+38h+var_2A], 0\nmov word ptr [rsp+38h+var_2C], ax\nmov eax, [rbx+6]\nmov [rsp+38h+var_24], 0\nmov dword ptr [rsp+38h+var_28], eax\ncall _strtol\nlea rdi, [rsp+38h+var_2C]; nptr\nmov edx, 0Ah; base\nxor esi, esi; endptr\nmov rbx, rax\ncall _strtol\nlea rdi, [rsp+38h+var_28]; nptr\nmov edx, 0Ah; base\nxor esi, esi; endptr\nmov rbp, rax\ncall _strtol\nlea eax, [rbx-1]\ncmp eax, 0Bh\nja loc_1550\nlea eax, [rbp-1]\ncmp eax, 1Eh\nja loc_1550\ncmp ebx, 0Bh\nja short loc_1608\nmov eax, 0A50h\nbt rax, rbx\njnb short loc_1608\nxor eax, eax\ncmp ebp, 1Fh\nsetnz al\njmp loc_1552\nloc_1608:\ncmp ebx, 2\nsetz al\ncmp ebp, 1Dh\nsetnle dl\nand eax, edx\nxor eax, 1\nmovzx eax, al\njmp loc_1552\nloc_1621:\ncall ___stack_chk_fail", + "ida_pseudo": "_BOOL8 __fastcall func0(__int16 *a1)\n{\n unsigned __int64 v1; // rax\n __int64 v2; // rcx\n char v3; // dl\n __int16 v5; // ax\n __int16 v6; // ax\n int v7; // eax\n unsigned __int64 v8; // rbx\n int v9; // ebp\n __int64 v10; // rax\n char nptr[2]; // [rsp+8h] [rbp-30h] BYREF\n char v12; // [rsp+Ah] [rbp-2Eh]\n char v13[2]; // [rsp+Ch] [rbp-2Ch] BYREF\n char v14; // [rsp+Eh] [rbp-2Ah]\n char v15[4]; // [rsp+10h] [rbp-28h] BYREF\n char v16; // [rsp+14h] [rbp-24h]\n unsigned __int64 v17; // [rsp+18h] [rbp-20h]\n\n v17 = __readfsqword(0x28u);\n if ( strlen((const char *)a1) != 10 )\n return 0LL;\n v1 = 0LL;\n v2 = 36LL;\n do\n {\n v3 = *((_BYTE *)a1 + v1);\n if ( _bittest64(&v2, v1) )\n {\n if ( v3 != 45 )\n return 0LL;\n }\n else if ( (unsigned __int8)(v3 - 48) > 9u )\n {\n return 0LL;\n }\n ++v1;\n }\n while ( v1 != 10 );\n v5 = *a1;\n v12 = 0;\n *(_WORD *)nptr = v5;\n v6 = *(__int16 *)((char *)a1 + 3);\n v14 = 0;\n *(_WORD *)v13 = v6;\n v7 = *(_DWORD *)(a1 + 3);\n v16 = 0;\n *(_DWORD *)v15 = v7;\n v8 = strtol(nptr, 0LL, 10);\n v9 = strtol(v13, 0LL, 10);\n strtol(v15, 0LL, 10);\n if ( (unsigned int)(v8 - 1) > 0xB || (unsigned int)(v9 - 1) > 0x1E )\n return 0LL;\n if ( (unsigned int)v8 <= 0xB )\n {\n v10 = 2640LL;\n if ( _bittest64(&v10, v8) )\n return v9 != 31;\n }\n return v9 <= 29 || (_DWORD)v8 != 2;\n}", + "ida_strip_asm": "sub_14F0:\nendbr64\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 28h\nmov rax, fs:28h\nmov [rsp+38h+var_20], rax\nxor eax, eax\ncall _strlen\ncmp rax, 0Ah\njnz short loc_1550\nxor eax, eax\nmov ecx, 24h ; '$'\njmp short loc_1537\nloc_1528:\ncmp dl, 2Dh ; '-'\njnz short loc_1550\nloc_152D:\nadd rax, 1\ncmp rax, 0Ah\njz short loc_1570\nloc_1537:\nbt rcx, rax\nmovzx edx, byte ptr [rbx+rax]\njb short loc_1528\nsub edx, 30h ; '0'\ncmp dl, 9\njbe short loc_152D\nnop dword ptr [rax+00000000h]\nloc_1550:\nxor eax, eax\nloc_1552:\nmov rdx, [rsp+38h+var_20]\nsub rdx, fs:28h\njnz loc_1621\nadd rsp, 28h\npop rbx\npop rbp\nretn\nloc_1570:\nmovzx eax, word ptr [rbx]\nlea rdi, [rsp+38h+nptr]; nptr\nmov edx, 0Ah; base\nxor esi, esi; endptr\nmov [rsp+38h+var_2E], 0\nmov word ptr [rsp+38h+nptr], ax\nmovzx eax, word ptr [rbx+3]\nmov [rsp+38h+var_2A], 0\nmov word ptr [rsp+38h+var_2C], ax\nmov eax, [rbx+6]\nmov [rsp+38h+var_24], 0\nmov dword ptr [rsp+38h+var_28], eax\ncall _strtol\nlea rdi, [rsp+38h+var_2C]; nptr\nmov edx, 0Ah; base\nxor esi, esi; endptr\nmov rbx, rax\ncall _strtol\nlea rdi, [rsp+38h+var_28]; nptr\nmov edx, 0Ah; base\nxor esi, esi; endptr\nmov rbp, rax\ncall _strtol\nlea eax, [rbx-1]\ncmp eax, 0Bh\nja loc_1550\nlea eax, [rbp-1]\ncmp eax, 1Eh\nja loc_1550\ncmp ebx, 0Bh\nja short loc_1608\nmov eax, 0A50h\nbt rax, rbx\njnb short loc_1608\nxor eax, eax\ncmp ebp, 1Fh\nsetnz al\njmp loc_1552\nloc_1608:\ncmp ebx, 2\nsetz al\ncmp ebp, 1Dh\nsetnle dl\nand eax, edx\nxor eax, 1\nmovzx eax, al\njmp loc_1552\nloc_1621:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_14F0(__int16 *a1)\n{\n unsigned __int64 v1; // rax\n __int64 v2; // rcx\n char v3; // dl\n __int16 v5; // ax\n __int16 v6; // ax\n int v7; // eax\n unsigned __int64 v8; // rbx\n int v9; // ebp\n __int64 v10; // rax\n char nptr[2]; // [rsp+8h] [rbp-30h] BYREF\n char v12; // [rsp+Ah] [rbp-2Eh]\n char v13[2]; // [rsp+Ch] [rbp-2Ch] BYREF\n char v14; // [rsp+Eh] [rbp-2Ah]\n char v15[4]; // [rsp+10h] [rbp-28h] BYREF\n char v16; // [rsp+14h] [rbp-24h]\n unsigned __int64 v17; // [rsp+18h] [rbp-20h]\n\n v17 = __readfsqword(0x28u);\n if ( strlen((const char *)a1) != 10 )\n return 0LL;\n v1 = 0LL;\n v2 = 36LL;\n do\n {\n v3 = *((_BYTE *)a1 + v1);\n if ( _bittest64(&v2, v1) )\n {\n if ( v3 != 45 )\n return 0LL;\n }\n else if ( (unsigned __int8)(v3 - 48) > 9u )\n {\n return 0LL;\n }\n ++v1;\n }\n while ( v1 != 10 );\n v5 = *a1;\n v12 = 0;\n *(_WORD *)nptr = v5;\n v6 = *(__int16 *)((char *)a1 + 3);\n v14 = 0;\n *(_WORD *)v13 = v6;\n v7 = *(_DWORD *)(a1 + 3);\n v16 = 0;\n *(_DWORD *)v15 = v7;\n v8 = strtol(nptr, 0LL, 10);\n v9 = strtol(v13, 0LL, 10);\n strtol(v15, 0LL, 10);\n if ( (unsigned int)(v8 - 1) > 0xB || (unsigned int)(v9 - 1) > 0x1E )\n return 0LL;\n if ( (unsigned int)v8 <= 0xB )\n {\n v10 = 2640LL;\n if ( _bittest64(&v10, v8) )\n return v9 != 31;\n }\n return v9 <= 29 || (_DWORD)v8 != 2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_14F0(short *a1) {\n unsigned long long v1;\n long long v2;\n char v3;\n short v5;\n short v6;\n int v7;\n unsigned long long v8;\n int v9;\n long long v10;\n char nptr[2];\n char v12;\n char v13[2];\n char v14;\n char v15[4];\n char v16;\n unsigned long long v17;\n v17 = __readfsqword(40u);\n if (strlen((const char *)a1) != 10) return 0LL;\n v1 = 0LL;\n v2 = 36LL;\n do {\n v3 = *((uint8_t *)a1 + v1);\n if (_bittest64(&v2, v1)) {\n if (v3 != 45) return 0LL;\n } else if ((unsigned char)(v3 - 48) > 9u) {\n return 0LL;\n }\n ++v1;\n } while (v1 != 10);\n v5 = *a1;\n v12 = 0;\n *(unsigned short *)nptr = v5;\n v6 = *(short *)((char *)a1 + 3);\n v14 = 0;\n *(unsigned short *)v13 = v6;\n v7 = *(uint32_t *)(a1 + 3);\n v16 = 0;\n *(uint32_t *)v15 = v7;\n v8 = strtol(nptr, 0LL, 10);\n v9 = strtol(v13, 0LL, 10);\n strtol(v15, 0LL, 10);\n if ((unsigned int)(v8 - 1) > 11 || (unsigned int)(v9 - 1) > 30) return 0LL;\n if ((unsigned int)v8 <= 11) {\n v10 = 2640LL;\n if (_bittest64(&v10, v8)) return v9 != 31;\n }\n return v9 <= 29 || (uint32_t)v8 != 2;\n}", + "ida_pseudo_norm": "uint8_t func0(short *a1) {\n unsigned long long v1;\n long long v2;\n char v3;\n short v5;\n short v6;\n int v7;\n unsigned long long v8;\n int v9;\n long long v10;\n char nptr[2];\n char v12;\n char v13[2];\n char v14;\n char v15[4];\n char v16;\n unsigned long long v17;\n v17 = __readfsqword(40u);\n if (strlen((const char *)a1) != 10) return 0LL;\n v1 = 0LL;\n v2 = 36LL;\n do {\n v3 = *((uint8_t *)a1 + v1);\n if (_bittest64(&v2, v1)) {\n if (v3 != 45) return 0LL;\n } else if ((unsigned char)(v3 - 48) > 9u) {\n return 0LL;\n }\n ++v1;\n } while (v1 != 10);\n v5 = *a1;\n v12 = 0;\n *(unsigned short *)nptr = v5;\n v6 = *(short *)((char *)a1 + 3);\n v14 = 0;\n *(unsigned short *)v13 = v6;\n v7 = *(uint32_t *)(a1 + 3);\n v16 = 0;\n *(uint32_t *)v15 = v7;\n v8 = strtol(nptr, 0LL, 10);\n v9 = strtol(v13, 0LL, 10);\n strtol(v15, 0LL, 10);\n if ((unsigned int)(v8 - 1) > 11 || (unsigned int)(v9 - 1) > 30) return 0LL;\n if ((unsigned int)v8 <= 11) {\n v10 = 2640LL;\n if (_bittest64(&v10, v8)) return v9 != 31;\n }\n return v9 <= 29 || (uint32_t)v8 != 2;\n}" + }, + { + "index": "HumanEval-C-124", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int func0(const char *date) {\n int mm, dd, yy;\n if (strlen(date) != 10) return 0;\n for (int i = 0; i < 10; i++) {\n if (i == 2 || i == 5) {\n if (date[i] != '-') return 0;\n } else {\n if (date[i] < '0' || date[i] > '9') return 0;\n }\n }\n char str_month[3] = {date[0], date[1], '\\0'};\n char str_day[3] = {date[3], date[4], '\\0'};\n char str_year[5] = {date[6], date[7], date[8], date[9], '\\0'};\n mm = atoi(str_month);\n dd = atoi(str_day);\n yy = atoi(str_year);\n if (mm < 1 || mm > 12) return 0;\n if (dd < 1 || dd > 31) return 0;\n if ((mm == 4 || mm == 6 || mm == 9 || mm == 11) && dd == 31) return 0;\n if (mm == 2 && dd > 29) return 0;\n return 1;\n}", + "test": "#include \n\n\nint main() {\n assert(func0(\"03-11-2000\") == 1);\n assert(func0(\"15-01-2012\") == 0);\n assert(func0(\"04-0-2040\") == 0);\n assert(func0(\"06-04-2020\") == 1);\n assert(func0(\"01-01-2007\") == 1);\n assert(func0(\"03-32-2011\") == 0);\n assert(func0(\"\") == 0);\n assert(func0(\"04-31-3000\") == 0);\n assert(func0(\"06-06-2005\") == 1);\n assert(func0(\"21-31-2000\") == 0);\n assert(func0(\"04-12-2003\") == 1);\n assert(func0(\"04122003\") == 0);\n assert(func0(\"20030412\") == 0);\n assert(func0(\"2003-04\") == 0);\n assert(func0(\"2003-04-12\") == 0);\n assert(func0(\"04-2003\") == 0);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 28h\nmov rax, fs:28h\nmov [rsp+38h+var_20], rax\nxor eax, eax\ncall _strlen\ncmp rax, 0Ah\njnz loc_1638\nmovzx eax, byte ptr [rbx]\nsub eax, 30h ; '0'\ncmp al, 9\nja loc_1638\nmovzx eax, byte ptr [rbx+1]\nmovzx edx, word ptr [rbx]\nsub eax, 30h ; '0'\ncmp al, 9\nja loc_1638\ncmp byte ptr [rbx+2], 2Dh ; '-'\njnz loc_1638\nmovzx eax, byte ptr [rbx+3]\nsub eax, 30h ; '0'\ncmp al, 9\nja loc_1638\nmovzx eax, byte ptr [rbx+4]\nmovzx ecx, word ptr [rbx+3]\nsub eax, 30h ; '0'\ncmp al, 9\nja loc_1638\ncmp byte ptr [rbx+5], 2Dh ; '-'\njnz loc_1638\nmovzx eax, byte ptr [rbx+6]\nsub eax, 30h ; '0'\ncmp al, 9\nja loc_1638\nmovzx eax, byte ptr [rbx+7]\nsub eax, 30h ; '0'\ncmp al, 9\nja loc_1638\nmovzx eax, byte ptr [rbx+8]\nsub eax, 30h ; '0'\ncmp al, 9\nja loc_1638\nmovzx eax, byte ptr [rbx+9]\nmov esi, [rbx+6]\nsub eax, 30h ; '0'\ncmp al, 9\nja loc_1638\nmov word ptr [rsp+38h+nptr], dx\nlea rdi, [rsp+38h+nptr]; nptr\nmov edx, 0Ah; base\nmov dword ptr [rsp+38h+var_28], esi\nxor esi, esi; endptr\nmov word ptr [rsp+38h+var_2C], cx\nmov [rsp+38h+var_2E], 0\nmov [rsp+38h+var_2A], 0\nmov [rsp+38h+var_24], 0\ncall _strtol\nlea rdi, [rsp+38h+var_2C]; nptr\nmov edx, 0Ah; base\nxor esi, esi; endptr\nmov rbx, rax\ncall _strtol\nlea rdi, [rsp+38h+var_28]; nptr\nmov edx, 0Ah; base\nxor esi, esi; endptr\nmov rbp, rax\ncall _strtol\nlea eax, [rbx-1]\ncmp eax, 0Bh\nja short loc_1638\nlea eax, [rbp-1]\ncmp eax, 1Eh\nja short loc_1638\ncmp ebx, 0Bh\nja short loc_1658\nmov eax, 0A50h\nbt rax, rbx\njnb short loc_1658\nxor eax, eax\ncmp ebp, 1Fh\nsetnz al\njmp short loc_163A\nloc_1638:\nxor eax, eax\nloc_163A:\nmov rdx, [rsp+38h+var_20]\nsub rdx, fs:28h\njnz short loc_166E\nadd rsp, 28h\npop rbx\npop rbp\nretn\nloc_1658:\ncmp ebx, 2\nsetz al\ncmp ebp, 1Dh\nsetnle dl\nand eax, edx\nxor eax, 1\nmovzx eax, al\njmp short loc_163A\nloc_166E:\ncall ___stack_chk_fail", + "ida_pseudo": "_BOOL8 __fastcall func0(__int64 a1)\n{\n __int16 v1; // cx\n int v2; // esi\n unsigned __int64 v3; // rbx\n int v4; // ebp\n __int64 v5; // rax\n char nptr[2]; // [rsp+8h] [rbp-30h] BYREF\n char v8; // [rsp+Ah] [rbp-2Eh]\n char v9[2]; // [rsp+Ch] [rbp-2Ch] BYREF\n char v10; // [rsp+Eh] [rbp-2Ah]\n char v11[4]; // [rsp+10h] [rbp-28h] BYREF\n char v12; // [rsp+14h] [rbp-24h]\n unsigned __int64 v13; // [rsp+18h] [rbp-20h]\n\n v13 = __readfsqword(0x28u);\n if ( strlen((const char *)a1) != 10 )\n return 0LL;\n if ( (unsigned __int8)(*(_BYTE *)a1 - 48) > 9u )\n return 0LL;\n if ( (unsigned __int8)(*(_BYTE *)(a1 + 1) - 48) > 9u )\n return 0LL;\n if ( *(_BYTE *)(a1 + 2) != 45 )\n return 0LL;\n if ( (unsigned __int8)(*(_BYTE *)(a1 + 3) - 48) > 9u )\n return 0LL;\n v1 = *(_WORD *)(a1 + 3);\n if ( (unsigned __int8)(*(_BYTE *)(a1 + 4) - 48) > 9u )\n return 0LL;\n if ( *(_BYTE *)(a1 + 5) != 45 )\n return 0LL;\n if ( (unsigned __int8)(*(_BYTE *)(a1 + 6) - 48) > 9u )\n return 0LL;\n if ( (unsigned __int8)(*(_BYTE *)(a1 + 7) - 48) > 9u )\n return 0LL;\n if ( (unsigned __int8)(*(_BYTE *)(a1 + 8) - 48) > 9u )\n return 0LL;\n v2 = *(_DWORD *)(a1 + 6);\n if ( (unsigned __int8)(*(_BYTE *)(a1 + 9) - 48) > 9u )\n return 0LL;\n *(_WORD *)nptr = *(_WORD *)a1;\n *(_DWORD *)v11 = v2;\n *(_WORD *)v9 = v1;\n v8 = 0;\n v10 = 0;\n v12 = 0;\n v3 = strtol(nptr, 0LL, 10);\n v4 = strtol(v9, 0LL, 10);\n strtol(v11, 0LL, 10);\n if ( (unsigned int)(v3 - 1) > 0xB || (unsigned int)(v4 - 1) > 0x1E )\n return 0LL;\n if ( (unsigned int)v3 <= 0xB )\n {\n v5 = 2640LL;\n if ( _bittest64(&v5, v3) )\n return v4 != 31;\n }\n return v4 <= 29 || (_DWORD)v3 != 2;\n}", + "ida_strip_asm": "sub_14F0:\nendbr64\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 28h\nmov rax, fs:28h\nmov [rsp+38h+var_20], rax\nxor eax, eax\ncall _strlen\ncmp rax, 0Ah\njnz loc_1638\nmovzx eax, byte ptr [rbx]\nsub eax, 30h ; '0'\ncmp al, 9\nja loc_1638\nmovzx eax, byte ptr [rbx+1]\nmovzx edx, word ptr [rbx]\nsub eax, 30h ; '0'\ncmp al, 9\nja loc_1638\ncmp byte ptr [rbx+2], 2Dh ; '-'\njnz loc_1638\nmovzx eax, byte ptr [rbx+3]\nsub eax, 30h ; '0'\ncmp al, 9\nja loc_1638\nmovzx eax, byte ptr [rbx+4]\nmovzx ecx, word ptr [rbx+3]\nsub eax, 30h ; '0'\ncmp al, 9\nja loc_1638\ncmp byte ptr [rbx+5], 2Dh ; '-'\njnz loc_1638\nmovzx eax, byte ptr [rbx+6]\nsub eax, 30h ; '0'\ncmp al, 9\nja loc_1638\nmovzx eax, byte ptr [rbx+7]\nsub eax, 30h ; '0'\ncmp al, 9\nja loc_1638\nmovzx eax, byte ptr [rbx+8]\nsub eax, 30h ; '0'\ncmp al, 9\nja loc_1638\nmovzx eax, byte ptr [rbx+9]\nmov esi, [rbx+6]\nsub eax, 30h ; '0'\ncmp al, 9\nja loc_1638\nmov word ptr [rsp+38h+nptr], dx\nlea rdi, [rsp+38h+nptr]; nptr\nmov edx, 0Ah; base\nmov dword ptr [rsp+38h+var_28], esi\nxor esi, esi; endptr\nmov word ptr [rsp+38h+var_2C], cx\nmov [rsp+38h+var_2E], 0\nmov [rsp+38h+var_2A], 0\nmov [rsp+38h+var_24], 0\ncall _strtol\nlea rdi, [rsp+38h+var_2C]; nptr\nmov edx, 0Ah; base\nxor esi, esi; endptr\nmov rbx, rax\ncall _strtol\nlea rdi, [rsp+38h+var_28]; nptr\nmov edx, 0Ah; base\nxor esi, esi; endptr\nmov rbp, rax\ncall _strtol\nlea eax, [rbx-1]\ncmp eax, 0Bh\nja short loc_1638\nlea eax, [rbp-1]\ncmp eax, 1Eh\nja short loc_1638\ncmp ebx, 0Bh\nja short loc_1658\nmov eax, 0A50h\nbt rax, rbx\njnb short loc_1658\nxor eax, eax\ncmp ebp, 1Fh\nsetnz al\njmp short loc_163A\nloc_1638:\nxor eax, eax\nloc_163A:\nmov rdx, [rsp+38h+var_20]\nsub rdx, fs:28h\njnz short loc_166E\nadd rsp, 28h\npop rbx\npop rbp\nretn\nloc_1658:\ncmp ebx, 2\nsetz al\ncmp ebp, 1Dh\nsetnle dl\nand eax, edx\nxor eax, 1\nmovzx eax, al\njmp short loc_163A\nloc_166E:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_14F0(__int64 a1)\n{\n __int16 v1; // cx\n int v2; // esi\n unsigned __int64 v3; // rbx\n int v4; // ebp\n __int64 v5; // rax\n char nptr[2]; // [rsp+8h] [rbp-30h] BYREF\n char v8; // [rsp+Ah] [rbp-2Eh]\n char v9[2]; // [rsp+Ch] [rbp-2Ch] BYREF\n char v10; // [rsp+Eh] [rbp-2Ah]\n char v11[4]; // [rsp+10h] [rbp-28h] BYREF\n char v12; // [rsp+14h] [rbp-24h]\n unsigned __int64 v13; // [rsp+18h] [rbp-20h]\n\n v13 = __readfsqword(0x28u);\n if ( strlen((const char *)a1) != 10 )\n return 0LL;\n if ( (unsigned __int8)(*(_BYTE *)a1 - 48) > 9u )\n return 0LL;\n if ( (unsigned __int8)(*(_BYTE *)(a1 + 1) - 48) > 9u )\n return 0LL;\n if ( *(_BYTE *)(a1 + 2) != 45 )\n return 0LL;\n if ( (unsigned __int8)(*(_BYTE *)(a1 + 3) - 48) > 9u )\n return 0LL;\n v1 = *(_WORD *)(a1 + 3);\n if ( (unsigned __int8)(*(_BYTE *)(a1 + 4) - 48) > 9u )\n return 0LL;\n if ( *(_BYTE *)(a1 + 5) != 45 )\n return 0LL;\n if ( (unsigned __int8)(*(_BYTE *)(a1 + 6) - 48) > 9u )\n return 0LL;\n if ( (unsigned __int8)(*(_BYTE *)(a1 + 7) - 48) > 9u )\n return 0LL;\n if ( (unsigned __int8)(*(_BYTE *)(a1 + 8) - 48) > 9u )\n return 0LL;\n v2 = *(_DWORD *)(a1 + 6);\n if ( (unsigned __int8)(*(_BYTE *)(a1 + 9) - 48) > 9u )\n return 0LL;\n *(_WORD *)nptr = *(_WORD *)a1;\n *(_DWORD *)v11 = v2;\n *(_WORD *)v9 = v1;\n v8 = 0;\n v10 = 0;\n v12 = 0;\n v3 = strtol(nptr, 0LL, 10);\n v4 = strtol(v9, 0LL, 10);\n strtol(v11, 0LL, 10);\n if ( (unsigned int)(v3 - 1) > 0xB || (unsigned int)(v4 - 1) > 0x1E )\n return 0LL;\n if ( (unsigned int)v3 <= 0xB )\n {\n v5 = 2640LL;\n if ( _bittest64(&v5, v3) )\n return v4 != 31;\n }\n return v4 <= 29 || (_DWORD)v3 != 2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_14F0(long long a1) {\n short v1;\n int v2;\n unsigned long long v3;\n int v4;\n long long v5;\n char nptr[2];\n char v8;\n char v9[2];\n char v10;\n char v11[4];\n char v12;\n unsigned long long v13;\n v13 = __readfsqword(40u);\n if (strlen((const char *)a1) != 10) return 0LL;\n if ((unsigned char)(*(uint8_t *)a1 - 48) > 9u) return 0LL;\n if ((unsigned char)(*(uint8_t *)(a1 + 1) - 48) > 9u) return 0LL;\n if (*(uint8_t *)(a1 + 2) != 45) return 0LL;\n if ((unsigned char)(*(uint8_t *)(a1 + 3) - 48) > 9u) return 0LL;\n v1 = *(unsigned short *)(a1 + 3);\n if ((unsigned char)(*(uint8_t *)(a1 + 4) - 48) > 9u) return 0LL;\n if (*(uint8_t *)(a1 + 5) != 45) return 0LL;\n if ((unsigned char)(*(uint8_t *)(a1 + 6) - 48) > 9u) return 0LL;\n if ((unsigned char)(*(uint8_t *)(a1 + 7) - 48) > 9u) return 0LL;\n if ((unsigned char)(*(uint8_t *)(a1 + 8) - 48) > 9u) return 0LL;\n v2 = *(uint32_t *)(a1 + 6);\n if ((unsigned char)(*(uint8_t *)(a1 + 9) - 48) > 9u) return 0LL;\n *(unsigned short *)nptr = *(unsigned short *)a1;\n *(uint32_t *)v11 = v2;\n *(unsigned short *)v9 = v1;\n v8 = 0;\n v10 = 0;\n v12 = 0;\n v3 = strtol(nptr, 0LL, 10);\n v4 = strtol(v9, 0LL, 10);\n strtol(v11, 0LL, 10);\n if ((unsigned int)(v3 - 1) > 11 || (unsigned int)(v4 - 1) > 30) return 0LL;\n if ((unsigned int)v3 <= 11) {\n v5 = 2640LL;\n if (_bittest64(&v5, v3)) return v4 != 31;\n }\n return v4 <= 29 || (uint32_t)v3 != 2;\n}", + "ida_pseudo_norm": "uint8_t func0(long long a1) {\n short v1;\n int v2;\n unsigned long long v3;\n int v4;\n long long v5;\n char nptr[2];\n char v8;\n char v9[2];\n char v10;\n char v11[4];\n char v12;\n unsigned long long v13;\n v13 = __readfsqword(40u);\n if (strlen((const char *)a1) != 10) return 0LL;\n if ((unsigned char)(*(uint8_t *)a1 - 48) > 9u) return 0LL;\n if ((unsigned char)(*(uint8_t *)(a1 + 1) - 48) > 9u) return 0LL;\n if (*(uint8_t *)(a1 + 2) != 45) return 0LL;\n if ((unsigned char)(*(uint8_t *)(a1 + 3) - 48) > 9u) return 0LL;\n v1 = *(unsigned short *)(a1 + 3);\n if ((unsigned char)(*(uint8_t *)(a1 + 4) - 48) > 9u) return 0LL;\n if (*(uint8_t *)(a1 + 5) != 45) return 0LL;\n if ((unsigned char)(*(uint8_t *)(a1 + 6) - 48) > 9u) return 0LL;\n if ((unsigned char)(*(uint8_t *)(a1 + 7) - 48) > 9u) return 0LL;\n if ((unsigned char)(*(uint8_t *)(a1 + 8) - 48) > 9u) return 0LL;\n v2 = *(uint32_t *)(a1 + 6);\n if ((unsigned char)(*(uint8_t *)(a1 + 9) - 48) > 9u) return 0LL;\n *(unsigned short *)nptr = *(unsigned short *)a1;\n *(uint32_t *)v11 = v2;\n *(unsigned short *)v9 = v1;\n v8 = 0;\n v10 = 0;\n v12 = 0;\n v3 = strtol(nptr, 0LL, 10);\n v4 = strtol(v9, 0LL, 10);\n strtol(v11, 0LL, 10);\n if ((unsigned int)(v3 - 1) > 11 || (unsigned int)(v4 - 1) > 30) return 0LL;\n if ((unsigned int)v3 <= 11) {\n v5 = 2640LL;\n if (_bittest64(&v5, v3)) return v4 != 31;\n }\n return v4 <= 29 || (uint32_t)v3 != 2;\n}" + }, + { + "index": "HumanEval-C-125", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n#include \n", + "func": "char **func0(const char *txt, int *returnSize) {\n int i, j = 0, num = 0, count = 0;\n int len = strlen(txt);\n char **out = NULL;\n char current[101] = {0};\n if (strchr(txt, ' ') || strchr(txt, ',')) {\n out = malloc(sizeof(char *) * (len + 1));\n for (i = 0; i <= len; ++i) {\n if (txt[i] == ' ' || txt[i] == ',' || txt[i] == '\\0') {\n if (j > 0) {\n current[j] = '\\0';\n out[count] = strdup(current);\n count++;\n j = 0;\n }\n } else {\n current[j++] = txt[i];\n }\n }\n } else {\n for (i = 0; i < len; ++i) {\n if (islower(txt[i]) && ((txt[i] - 'a') % 2 == 1)) {\n num++;\n }\n }\n out = malloc(sizeof(char *));\n out[0] = malloc(sizeof(char) * 12);\n sprintf(out[0], \"%d\", num);\n count = 1;\n }\n *returnSize = count;\n return out;\n}", + "test": "#include \n#include \n#include \n#include \n\nint issame(char **a, int aSize, char **b, int bSize) {\n if (aSize != bSize) return 0;\n for (int i = 0; i < aSize; i++) {\n if (strcmp(a[i], b[i]) != 0) return 0;\n }\n return 1;\n}\n\nvoid free_words(char **words, int size) {\n for (int i = 0; i < size; i++) free(words[i]);\n free(words);\n}\n\nint main() {\n int size;\n char *expected[3];\n char **result;\n\n result = func0(\"Hello world!\", &size);\n expected[0] = \"Hello\";\n expected[1] = \"world!\";\n assert(issame(expected, 2,result, size)); \n free_words(result, size);\n\n result = func0(\"Hello,world!\", &size);\n expected[0] = \"Hello\";\n expected[1] = \"world!\";\n assert(issame(expected, 2,result, size));\n free_words(result, size);\n\n result = func0(\"abcdef\", &size);\n expected[0] = \"3\";\n assert(issame(expected, 1,result, size));\n free_words(result, size);\n\n result = func0(\"aaabb\", &size);\n expected[0] = \"2\";\n assert(issame(expected, 1,result, size));\n free_words(result, size);\n\n result = func0(\"aaaBb\", &size);\n expected[0] = \"1\";\n assert(issame(expected, 1,result, size));\n free_words(result, size);\n\n result = func0(\"\", &size);\n expected[0] = \"0\";\n assert(issame(expected, 1,result, size));\n free_words(result, size);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 0A8h\nmov [rbp+s], rdi\nmov [rbp+var_B0], rsi\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov [rbp+var_98], 0\nmov [rbp+var_94], 0\nmov [rbp+var_90], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_8C], eax\nmov [rbp+var_88], 0\nmov qword ptr [rbp+var_80], 0\nmov [rbp+var_78], 0\nmov [rbp+var_70], 0\nmov [rbp+var_68], 0\nmov [rbp+var_60], 0\nmov [rbp+var_58], 0\nmov [rbp+var_50], 0\nmov [rbp+var_48], 0\nmov [rbp+var_40], 0\nmov [rbp+var_38], 0\nmov [rbp+var_30], 0\nmov [rbp+var_28], 0\nmov [rbp+var_28+5], 0\nmov rax, [rbp+s]\nmov esi, 20h ; ' '; c\nmov rdi, rax; s\ncall _strchr\ntest rax, rax\njnz short loc_1372\nmov rax, [rbp+s]\nmov esi, 2Ch ; ','; c\nmov rdi, rax; s\ncall _strchr\ntest rax, rax\njz loc_148A\nloc_1372:\nmov eax, [rbp+var_8C]\nadd eax, 1\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_88], rax\nmov [rbp+var_9C], 0\njmp loc_1473\nloc_139F:\nmov eax, [rbp+var_9C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njz short loc_13ED\nmov eax, [rbp+var_9C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 2Ch ; ','\njz short loc_13ED\nmov eax, [rbp+var_9C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1440\nloc_13ED:\ncmp [rbp+var_98], 0\njle short loc_146C\nmov eax, [rbp+var_98]\ncdqe\nmov [rbp+rax+var_80], 0\nmov eax, [rbp+var_90]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_88]\nlea rbx, [rdx+rax]\nlea rax, [rbp+var_80]\nmov rdi, rax; s\ncall _strdup\nmov [rbx], rax\nadd [rbp+var_90], 1\nmov [rbp+var_98], 0\njmp short loc_146C\nloc_1440:\nmov eax, [rbp+var_9C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_98]\nlea edx, [rax+1]\nmov [rbp+var_98], edx\nmovzx edx, byte ptr [rcx]\ncdqe\nmov [rbp+rax+var_80], dl\nloc_146C:\nadd [rbp+var_9C], 1\nloc_1473:\nmov eax, [rbp+var_9C]\ncmp eax, [rbp+var_8C]\njle loc_139F\njmp loc_1578\nloc_148A:\nmov [rbp+var_9C], 0\njmp short loc_150D\nloc_1496:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_9C]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 200h\ntest eax, eax\njz short loc_1506\nmov eax, [rbp+var_9C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nlea edx, [rax-61h]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\ncmp eax, 1\njnz short loc_1506\nadd [rbp+var_94], 1\nloc_1506:\nadd [rbp+var_9C], 1\nloc_150D:\nmov eax, [rbp+var_9C]\ncmp eax, [rbp+var_8C]\njl loc_1496\nmov edi, 8; size\ncall _malloc\nmov [rbp+var_88], rax\nmov edi, 0Ch; size\ncall _malloc\nmov rdx, rax\nmov rax, [rbp+var_88]\nmov [rax], rdx\nmov rax, [rbp+var_88]\nmov rax, [rax]\nmov edx, [rbp+var_94]\nlea rcx, format; \"%d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nmov [rbp+var_90], 1\nloc_1578:\nmov rax, [rbp+var_B0]\nmov edx, [rbp+var_90]\nmov [rax], edx\nmov rax, [rbp+var_88]\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njz short loc_15A2\ncall ___stack_chk_fail\nloc_15A2:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "char **__fastcall func0(const char *a1, int *a2)\n{\n int v2; // eax\n int i; // [rsp+14h] [rbp-9Ch]\n int j; // [rsp+14h] [rbp-9Ch]\n int v6; // [rsp+18h] [rbp-98h]\n int v7; // [rsp+1Ch] [rbp-94h]\n int v8; // [rsp+20h] [rbp-90h]\n int v9; // [rsp+24h] [rbp-8Ch]\n char **v10; // [rsp+28h] [rbp-88h]\n char v11[8]; // [rsp+30h] [rbp-80h] BYREF\n __int64 v12; // [rsp+38h] [rbp-78h]\n __int64 v13; // [rsp+40h] [rbp-70h]\n __int64 v14; // [rsp+48h] [rbp-68h]\n __int64 v15; // [rsp+50h] [rbp-60h]\n __int64 v16; // [rsp+58h] [rbp-58h]\n __int64 v17; // [rsp+60h] [rbp-50h]\n __int64 v18; // [rsp+68h] [rbp-48h]\n __int64 v19; // [rsp+70h] [rbp-40h]\n __int64 v20; // [rsp+78h] [rbp-38h]\n __int64 v21; // [rsp+80h] [rbp-30h]\n _QWORD v22[4]; // [rsp+88h] [rbp-28h]\n\n v22[2] = __readfsqword(0x28u);\n v6 = 0;\n v7 = 0;\n v8 = 0;\n v9 = strlen(a1);\n *(_QWORD *)v11 = 0LL;\n v12 = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0LL;\n v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n v22[0] = 0LL;\n *(_QWORD *)((char *)v22 + 5) = 0LL;\n if ( strchr(a1, 32) || strchr(a1, 44) )\n {\n v10 = (char **)malloc(8LL * (v9 + 1));\n for ( i = 0; i <= v9; ++i )\n {\n if ( a1[i] == 32 || a1[i] == 44 || !a1[i] )\n {\n if ( v6 > 0 )\n {\n v11[v6] = 0;\n v10[v8++] = strdup(v11);\n v6 = 0;\n }\n }\n else\n {\n v2 = v6++;\n v11[v2] = a1[i];\n }\n }\n }\n else\n {\n for ( j = 0; j < v9; ++j )\n {\n if ( ((*__ctype_b_loc())[a1[j]] & 0x200) != 0 && (a1[j] - 97) % 2 == 1 )\n ++v7;\n }\n v10 = (char **)malloc(8uLL);\n *v10 = (char *)malloc(0xCuLL);\n sprintf(*v10, \"%d\", v7);\n v8 = 1;\n }\n *a2 = v8;\n return v10;\n}", + "ida_strip_asm": "sub_1269:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 0A8h\nmov [rbp+s], rdi\nmov [rbp+var_B0], rsi\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov [rbp+var_98], 0\nmov [rbp+var_94], 0\nmov [rbp+var_90], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_8C], eax\nmov [rbp+var_88], 0\nmov qword ptr [rbp+var_80], 0\nmov [rbp+var_78], 0\nmov [rbp+var_70], 0\nmov [rbp+var_68], 0\nmov [rbp+var_60], 0\nmov [rbp+var_58], 0\nmov [rbp+var_50], 0\nmov [rbp+var_48], 0\nmov [rbp+var_40], 0\nmov [rbp+var_38], 0\nmov [rbp+var_30], 0\nmov [rbp+var_28], 0\nmov [rbp+var_28+5], 0\nmov rax, [rbp+s]\nmov esi, 20h ; ' '; c\nmov rdi, rax; s\ncall _strchr\ntest rax, rax\njnz short loc_1372\nmov rax, [rbp+s]\nmov esi, 2Ch ; ','; c\nmov rdi, rax; s\ncall _strchr\ntest rax, rax\njz loc_148A\nloc_1372:\nmov eax, [rbp+var_8C]\nadd eax, 1\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_88], rax\nmov [rbp+var_9C], 0\njmp loc_1473\nloc_139F:\nmov eax, [rbp+var_9C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njz short loc_13ED\nmov eax, [rbp+var_9C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 2Ch ; ','\njz short loc_13ED\nmov eax, [rbp+var_9C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1440\nloc_13ED:\ncmp [rbp+var_98], 0\njle short loc_146C\nmov eax, [rbp+var_98]\ncdqe\nmov [rbp+rax+var_80], 0\nmov eax, [rbp+var_90]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_88]\nlea rbx, [rdx+rax]\nlea rax, [rbp+var_80]\nmov rdi, rax; s\ncall _strdup\nmov [rbx], rax\nadd [rbp+var_90], 1\nmov [rbp+var_98], 0\njmp short loc_146C\nloc_1440:\nmov eax, [rbp+var_9C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_98]\nlea edx, [rax+1]\nmov [rbp+var_98], edx\nmovzx edx, byte ptr [rcx]\ncdqe\nmov [rbp+rax+var_80], dl\nloc_146C:\nadd [rbp+var_9C], 1\nloc_1473:\nmov eax, [rbp+var_9C]\ncmp eax, [rbp+var_8C]\njle loc_139F\njmp loc_1578\nloc_148A:\nmov [rbp+var_9C], 0\njmp short loc_150D\nloc_1496:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_9C]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 200h\ntest eax, eax\njz short loc_1506\nmov eax, [rbp+var_9C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nlea edx, [rax-61h]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\ncmp eax, 1\njnz short loc_1506\nadd [rbp+var_94], 1\nloc_1506:\nadd [rbp+var_9C], 1\nloc_150D:\nmov eax, [rbp+var_9C]\ncmp eax, [rbp+var_8C]\njl loc_1496\nmov edi, 8; size\ncall _malloc\nmov [rbp+var_88], rax\nmov edi, 0Ch; size\ncall _malloc\nmov rdx, rax\nmov rax, [rbp+var_88]\nmov [rax], rdx\nmov rax, [rbp+var_88]\nmov rax, [rax]\nmov edx, [rbp+var_94]\nlea rcx, format; \"%d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nmov [rbp+var_90], 1\nloc_1578:\nmov rax, [rbp+var_B0]\nmov edx, [rbp+var_90]\nmov [rax], edx\nmov rax, [rbp+var_88]\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njz short loc_15A2\ncall ___stack_chk_fail\nloc_15A2:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "char **__fastcall sub_1269(const char *a1, int *a2)\n{\n int v2; // eax\n int i; // [rsp+14h] [rbp-9Ch]\n int j; // [rsp+14h] [rbp-9Ch]\n int v6; // [rsp+18h] [rbp-98h]\n int v7; // [rsp+1Ch] [rbp-94h]\n int v8; // [rsp+20h] [rbp-90h]\n int v9; // [rsp+24h] [rbp-8Ch]\n char **v10; // [rsp+28h] [rbp-88h]\n char v11[8]; // [rsp+30h] [rbp-80h] BYREF\n __int64 v12; // [rsp+38h] [rbp-78h]\n __int64 v13; // [rsp+40h] [rbp-70h]\n __int64 v14; // [rsp+48h] [rbp-68h]\n __int64 v15; // [rsp+50h] [rbp-60h]\n __int64 v16; // [rsp+58h] [rbp-58h]\n __int64 v17; // [rsp+60h] [rbp-50h]\n __int64 v18; // [rsp+68h] [rbp-48h]\n __int64 v19; // [rsp+70h] [rbp-40h]\n __int64 v20; // [rsp+78h] [rbp-38h]\n __int64 v21; // [rsp+80h] [rbp-30h]\n _QWORD v22[4]; // [rsp+88h] [rbp-28h]\n\n v22[2] = __readfsqword(0x28u);\n v6 = 0;\n v7 = 0;\n v8 = 0;\n v9 = strlen(a1);\n *(_QWORD *)v11 = 0LL;\n v12 = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0LL;\n v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n v22[0] = 0LL;\n *(_QWORD *)((char *)v22 + 5) = 0LL;\n if ( strchr(a1, 32) || strchr(a1, 44) )\n {\n v10 = (char **)malloc(8LL * (v9 + 1));\n for ( i = 0; i <= v9; ++i )\n {\n if ( a1[i] == 32 || a1[i] == 44 || !a1[i] )\n {\n if ( v6 > 0 )\n {\n v11[v6] = 0;\n v10[v8++] = strdup(v11);\n v6 = 0;\n }\n }\n else\n {\n v2 = v6++;\n v11[v2] = a1[i];\n }\n }\n }\n else\n {\n for ( j = 0; j < v9; ++j )\n {\n if ( ((*__ctype_b_loc())[a1[j]] & 0x200) != 0 && (a1[j] - 97) % 2 == 1 )\n ++v7;\n }\n v10 = (char **)malloc(8uLL);\n *v10 = (char *)malloc(0xCuLL);\n sprintf(*v10, \"%d\", v7);\n v8 = 1;\n }\n *a2 = v8;\n return v10;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char **sub_1269(const char *a1, int *a2) {\n int v2;\n int i;\n int j;\n int v6;\n int v7;\n int v8;\n int v9;\n char **v10;\n char v11[8];\n long long v12;\n long long v13;\n long long v14;\n long long v15;\n long long v16;\n long long v17;\n long long v18;\n long long v19;\n long long v20;\n long long v21;\n uint64_t v22[4];\n v22[2] = __readfsqword(40u);\n v6 = 0;\n v7 = 0;\n v8 = 0;\n v9 = strlen(a1);\n *(uint64_t *)v11 = 0LL;\n v12 = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0LL;\n v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n v22[0] = 0LL;\n *(uint64_t *)((char *)v22 + 5) = 0LL;\n if (strchr(a1, 32) || strchr(a1, 44)) {\n v10 = (char **)malloc(8LL * (v9 + 1));\n for (i = 0; i <= v9; ++i) {\n if (a1[i] == 32 || a1[i] == 44 || !a1[i]) {\n if (v6 > 0) {\n v11[v6] = 0;\n v10[v8++] = strdup(v11);\n v6 = 0;\n }\n } else {\n v2 = v6++;\n v11[v2] = a1[i];\n }\n }\n } else {\n for (j = 0; j < v9; ++j) {\n if (((*__ctype_b_loc())[a1[j]] & 512) != 0 && (a1[j] - 97) % 2 == 1) ++v7;\n }\n v10 = (char **)malloc(8uLL);\n *v10 = (char *)malloc(12uLL);\n sprintf(*v10, \"%d\", v7);\n v8 = 1;\n }\n *a2 = v8;\n return v10;\n}", + "ida_pseudo_norm": "char **func0(const char *a1, int *a2) {\n int v2;\n int i;\n int j;\n int v6;\n int v7;\n int v8;\n int v9;\n char **v10;\n char v11[8];\n long long v12;\n long long v13;\n long long v14;\n long long v15;\n long long v16;\n long long v17;\n long long v18;\n long long v19;\n long long v20;\n long long v21;\n uint64_t v22[4];\n v22[2] = __readfsqword(40u);\n v6 = 0;\n v7 = 0;\n v8 = 0;\n v9 = strlen(a1);\n *(uint64_t *)v11 = 0LL;\n v12 = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0LL;\n v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n v22[0] = 0LL;\n *(uint64_t *)((char *)v22 + 5) = 0LL;\n if (strchr(a1, 32) || strchr(a1, 44)) {\n v10 = (char **)malloc(8LL * (v9 + 1));\n for (i = 0; i <= v9; ++i) {\n if (a1[i] == 32 || a1[i] == 44 || !a1[i]) {\n if (v6 > 0) {\n v11[v6] = 0;\n v10[v8++] = strdup(v11);\n v6 = 0;\n }\n } else {\n v2 = v6++;\n v11[v2] = a1[i];\n }\n }\n } else {\n for (j = 0; j < v9; ++j) {\n if (((*__ctype_b_loc())[a1[j]] & 512) != 0 && (a1[j] - 97) % 2 == 1) ++v7;\n }\n v10 = (char **)malloc(8uLL);\n *v10 = (char *)malloc(12uLL);\n sprintf(*v10, \"%d\", v7);\n v8 = 1;\n }\n *a2 = v8;\n return v10;\n}" + }, + { + "index": "HumanEval-C-125", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n#include \n", + "func": "char **func0(const char *txt, int *returnSize) {\n int i, j = 0, num = 0, count = 0;\n int len = strlen(txt);\n char **out = NULL;\n char current[101] = {0};\n if (strchr(txt, ' ') || strchr(txt, ',')) {\n out = malloc(sizeof(char *) * (len + 1));\n for (i = 0; i <= len; ++i) {\n if (txt[i] == ' ' || txt[i] == ',' || txt[i] == '\\0') {\n if (j > 0) {\n current[j] = '\\0';\n out[count] = strdup(current);\n count++;\n j = 0;\n }\n } else {\n current[j++] = txt[i];\n }\n }\n } else {\n for (i = 0; i < len; ++i) {\n if (islower(txt[i]) && ((txt[i] - 'a') % 2 == 1)) {\n num++;\n }\n }\n out = malloc(sizeof(char *));\n out[0] = malloc(sizeof(char) * 12);\n sprintf(out[0], \"%d\", num);\n count = 1;\n }\n *returnSize = count;\n return out;\n}", + "test": "#include \n#include \n#include \n#include \n\nint issame(char **a, int aSize, char **b, int bSize) {\n if (aSize != bSize) return 0;\n for (int i = 0; i < aSize; i++) {\n if (strcmp(a[i], b[i]) != 0) return 0;\n }\n return 1;\n}\n\nvoid free_words(char **words, int size) {\n for (int i = 0; i < size; i++) free(words[i]);\n free(words);\n}\n\nint main() {\n int size;\n char *expected[3];\n char **result;\n\n result = func0(\"Hello world!\", &size);\n expected[0] = \"Hello\";\n expected[1] = \"world!\";\n assert(issame(expected, 2,result, size)); \n free_words(result, size);\n\n result = func0(\"Hello,world!\", &size);\n expected[0] = \"Hello\";\n expected[1] = \"world!\";\n assert(issame(expected, 2,result, size));\n free_words(result, size);\n\n result = func0(\"abcdef\", &size);\n expected[0] = \"3\";\n assert(issame(expected, 1,result, size));\n free_words(result, size);\n\n result = func0(\"aaabb\", &size);\n expected[0] = \"2\";\n assert(issame(expected, 1,result, size));\n free_words(result, size);\n\n result = func0(\"aaaBb\", &size);\n expected[0] = \"1\";\n assert(issame(expected, 1,result, size));\n free_words(result, size);\n\n result = func0(\"\", &size);\n expected[0] = \"0\";\n assert(issame(expected, 1,result, size));\n free_words(result, size);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 78h\nmov r12, rdi\nmov r15, rsi\nmov rax, fs:28h\nmov [rsp+0A8h+var_40], rax\nxor eax, eax\ncall _strlen\nmov rbp, rax\nmov [rsp+0A8h+var_A8], 0\nmov [rsp+0A8h+var_A0], 0\nmov [rsp+0A8h+var_98], 0\nmov [rsp+0A8h+var_90], 0\nmov [rsp+0A8h+var_88], 0\nmov [rsp+0A8h+var_80], 0\nmov [rsp+0A8h+var_78], 0\nmov [rsp+0A8h+var_70], 0\nmov [rsp+0A8h+var_68], 0\nmov [rsp+0A8h+var_60], 0\nmov [rsp+0A8h+var_58], 0\nmov [rsp+0A8h+var_50], 0\nmov [rsp+0A8h+var_50+5], 0\nmov esi, 20h ; ' '; c\nmov rdi, r12; s\ncall _strchr\ntest rax, rax\njz short loc_135A\nloc_131F:\nlea edi, [rbp+1]\nmovsxd rdi, edi\nshl rdi, 3; size\ncall _malloc\nmov r14, rax\ntest ebp, ebp\njs loc_147A\nmov rbx, r12\nmov ebp, ebp\nlea rbp, [r12+rbp+1]\nmov r12d, 0\nmov edx, 0\nmov r13, 100100000001h\njmp short loc_13A9\nloc_135A:\nmov esi, 2Ch ; ','; c\nmov rdi, r12; s\ncall _strchr\ntest rax, rax\njnz short loc_131F\nmov ebx, 0\ntest ebp, ebp\njle loc_1414\ncall ___ctype_b_loc\nmov rdi, [rax]\nmov rdx, r12\nlea eax, [rbp-1]\nlea rsi, [r12+rax+1]\nmov ebx, 0\njmp short loc_13E7\nloc_1393:\nmovsxd rcx, edx\nmov byte ptr [rsp+rcx+0A8h+var_A8], al\nlea edx, [rdx+1]\nloc_139C:\nadd rbx, 1\ncmp rbp, rbx\njz loc_1455\nloc_13A9:\nmovzx eax, byte ptr [rbx]\ncmp al, 2Ch ; ','\nja short loc_1393\nbt r13, rax\njnb short loc_1393\ntest edx, edx\njle short loc_139C\nmovsxd rdx, edx\nmov byte ptr [rsp+rdx+0A8h+var_A8], 0\nmov rdi, rsp; s\ncall _strdup\nmov rdx, rax\nmovsxd rax, r12d\nmov [r14+rax*8], rdx\nadd r12d, 1\nmov edx, 0\njmp short loc_139C\nloc_13DE:\nadd rdx, 1\ncmp rdx, rsi\njz short loc_1414\nloc_13E7:\nmovzx eax, byte ptr [rdx]\nmovsx rcx, al\ntest byte ptr [rdi+rcx*2+1], 2\njz short loc_13DE\nmovsx eax, al\nsub eax, 61h ; 'a'\nmov ecx, eax\nshr ecx, 1Fh\nadd eax, ecx\nand eax, 1\nsub eax, ecx\ncmp eax, 1\nsetz al\nmovzx eax, al\nadd ebx, eax\njmp short loc_13DE\nloc_1414:\nmov edi, 8; size\ncall _malloc\nmov r14, rax\nmov edi, 0Ch; size\ncall _malloc\nmov rdi, rax\nmov [r14], rax\nmov r8d, ebx\nlea rcx, unk_2004\nmov edx, 0Ch\nmov esi, 2\nmov eax, 0\ncall ___sprintf_chk\nmov r12d, 1\nloc_1455:\nmov [r15], r12d\nmov rax, [rsp+0A8h+var_40]\nsub rax, fs:28h\njnz short loc_1482\nmov rax, r14\nadd rsp, 78h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_147A:\nmov r12d, 0\njmp short loc_1455\nloc_1482:\ncall ___stack_chk_fail", + "ida_pseudo": "_QWORD *__fastcall func0(char *s, int *a2)\n{\n int v3; // ebp\n _QWORD *v4; // r14\n char *v5; // rbx\n char *v6; // rbp\n int v7; // r12d\n int v8; // edx\n __int64 v9; // r13\n unsigned int v10; // ebx\n const unsigned __int16 *v11; // rdi\n char *v12; // rdx\n unsigned __int64 v13; // rax\n void *v14; // rax\n __int64 v15; // r9\n __int64 v17; // [rsp+0h] [rbp-A8h] BYREF\n __int64 v18; // [rsp+8h] [rbp-A0h]\n __int64 v19; // [rsp+10h] [rbp-98h]\n __int64 v20; // [rsp+18h] [rbp-90h]\n __int64 v21; // [rsp+20h] [rbp-88h]\n __int64 v22; // [rsp+28h] [rbp-80h]\n __int64 v23; // [rsp+30h] [rbp-78h]\n __int64 v24; // [rsp+38h] [rbp-70h]\n __int64 v25; // [rsp+40h] [rbp-68h]\n __int64 v26; // [rsp+48h] [rbp-60h]\n __int64 v27; // [rsp+50h] [rbp-58h]\n __int128 v28; // [rsp+58h] [rbp-50h]\n unsigned __int64 v29; // [rsp+68h] [rbp-40h]\n\n v29 = __readfsqword(0x28u);\n v3 = strlen(s);\n v17 = 0LL;\n v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n v22 = 0LL;\n v23 = 0LL;\n v24 = 0LL;\n v25 = 0LL;\n v26 = 0LL;\n v27 = 0LL;\n *(_QWORD *)&v28 = 0LL;\n *(_QWORD *)((char *)&v28 + 5) = 0LL;\n if ( strchr(s, 32) || strchr(s, 44) )\n {\n v4 = malloc(8LL * (v3 + 1));\n if ( v3 < 0 )\n {\n v7 = 0;\n }\n else\n {\n v5 = s;\n v6 = &s[v3 + 1];\n v7 = 0;\n v8 = 0;\n v9 = 0x100100000001LL;\n do\n {\n v13 = (unsigned __int8)*v5;\n if ( (unsigned __int8)v13 <= 0x2Cu && _bittest64(&v9, v13) )\n {\n if ( v8 > 0 )\n {\n *((_BYTE *)&v17 + v8) = 0;\n v4[v7++] = strdup((const char *)&v17);\n v8 = 0;\n }\n }\n else\n {\n *((_BYTE *)&v17 + v8++) = v13;\n }\n ++v5;\n }\n while ( v6 != v5 );\n }\n }\n else\n {\n v10 = 0;\n if ( v3 > 0 )\n {\n v11 = *__ctype_b_loc();\n v12 = s;\n v10 = 0;\n do\n {\n if ( (v11[*v12] & 0x200) != 0 )\n v10 += (*v12 - 97) % 2 == 1;\n ++v12;\n }\n while ( v12 != &s[v3 - 1 + 1] );\n }\n v4 = malloc(8uLL);\n v14 = malloc(0xCuLL);\n *v4 = v14;\n __sprintf_chk(\n v14,\n 2LL,\n 12LL,\n &unk_2004,\n v10,\n v15,\n v17,\n v18,\n v19,\n v20,\n v21,\n v22,\n v23,\n v24,\n v25,\n v26,\n v27,\n v28,\n *((_QWORD *)&v28 + 1),\n v29);\n v7 = 1;\n }\n *a2 = v7;\n return v4;\n}", + "ida_strip_asm": "sub_1269:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 78h\nmov r12, rdi\nmov r15, rsi\nmov rax, fs:28h\nmov [rsp+0A8h+var_40], rax\nxor eax, eax\ncall _strlen\nmov rbp, rax\nmov [rsp+0A8h+var_A8], 0\nmov [rsp+0A8h+var_A0], 0\nmov [rsp+0A8h+var_98], 0\nmov [rsp+0A8h+var_90], 0\nmov [rsp+0A8h+var_88], 0\nmov [rsp+0A8h+var_80], 0\nmov [rsp+0A8h+var_78], 0\nmov [rsp+0A8h+var_70], 0\nmov [rsp+0A8h+var_68], 0\nmov [rsp+0A8h+var_60], 0\nmov [rsp+0A8h+var_58], 0\nmov [rsp+0A8h+var_50], 0\nmov [rsp+0A8h+var_50+5], 0\nmov esi, 20h ; ' '; c\nmov rdi, r12; s\ncall _strchr\ntest rax, rax\njz short loc_135A\nloc_131F:\nlea edi, [rbp+1]\nmovsxd rdi, edi\nshl rdi, 3; size\ncall _malloc\nmov r14, rax\ntest ebp, ebp\njs loc_147A\nmov rbx, r12\nmov ebp, ebp\nlea rbp, [r12+rbp+1]\nmov r12d, 0\nmov edx, 0\nmov r13, 100100000001h\njmp short loc_13A9\nloc_135A:\nmov esi, 2Ch ; ','; c\nmov rdi, r12; s\ncall _strchr\ntest rax, rax\njnz short loc_131F\nmov ebx, 0\ntest ebp, ebp\njle loc_1414\ncall ___ctype_b_loc\nmov rdi, [rax]\nmov rdx, r12\nlea eax, [rbp-1]\nlea rsi, [r12+rax+1]\nmov ebx, 0\njmp short loc_13E7\nloc_1393:\nmovsxd rcx, edx\nmov byte ptr [rsp+rcx+0A8h+var_A8], al\nlea edx, [rdx+1]\nloc_139C:\nadd rbx, 1\ncmp rbp, rbx\njz loc_1455\nloc_13A9:\nmovzx eax, byte ptr [rbx]\ncmp al, 2Ch ; ','\nja short loc_1393\nbt r13, rax\njnb short loc_1393\ntest edx, edx\njle short loc_139C\nmovsxd rdx, edx\nmov byte ptr [rsp+rdx+0A8h+var_A8], 0\nmov rdi, rsp; s\ncall _strdup\nmov rdx, rax\nmovsxd rax, r12d\nmov [r14+rax*8], rdx\nadd r12d, 1\nmov edx, 0\njmp short loc_139C\nloc_13DE:\nadd rdx, 1\ncmp rdx, rsi\njz short loc_1414\nloc_13E7:\nmovzx eax, byte ptr [rdx]\nmovsx rcx, al\ntest byte ptr [rdi+rcx*2+1], 2\njz short loc_13DE\nmovsx eax, al\nsub eax, 61h ; 'a'\nmov ecx, eax\nshr ecx, 1Fh\nadd eax, ecx\nand eax, 1\nsub eax, ecx\ncmp eax, 1\nsetz al\nmovzx eax, al\nadd ebx, eax\njmp short loc_13DE\nloc_1414:\nmov edi, 8; size\ncall _malloc\nmov r14, rax\nmov edi, 0Ch; size\ncall _malloc\nmov rdi, rax\nmov [r14], rax\nmov r8d, ebx\nlea rcx, unk_2004\nmov edx, 0Ch\nmov esi, 2\nmov eax, 0\ncall ___sprintf_chk\nmov r12d, 1\nloc_1455:\nmov [r15], r12d\nmov rax, [rsp+0A8h+var_40]\nsub rax, fs:28h\njnz short loc_1482\nmov rax, r14\nadd rsp, 78h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_147A:\nmov r12d, 0\njmp short loc_1455\nloc_1482:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1269(char *s, int *a2)\n{\n int v3; // ebp\n _QWORD *v4; // r14\n char *v5; // rbx\n char *v6; // rbp\n int v7; // r12d\n int v8; // edx\n __int64 v9; // r13\n unsigned int v10; // ebx\n const unsigned __int16 *v11; // rdi\n char *v12; // rdx\n unsigned __int64 v13; // rax\n void *v14; // rax\n __int64 v15; // r9\n __int64 v17; // [rsp+0h] [rbp-A8h] BYREF\n __int64 v18; // [rsp+8h] [rbp-A0h]\n __int64 v19; // [rsp+10h] [rbp-98h]\n __int64 v20; // [rsp+18h] [rbp-90h]\n __int64 v21; // [rsp+20h] [rbp-88h]\n __int64 v22; // [rsp+28h] [rbp-80h]\n __int64 v23; // [rsp+30h] [rbp-78h]\n __int64 v24; // [rsp+38h] [rbp-70h]\n __int64 v25; // [rsp+40h] [rbp-68h]\n __int64 v26; // [rsp+48h] [rbp-60h]\n __int64 v27; // [rsp+50h] [rbp-58h]\n __int128 v28; // [rsp+58h] [rbp-50h]\n unsigned __int64 v29; // [rsp+68h] [rbp-40h]\n\n v29 = __readfsqword(0x28u);\n v3 = strlen(s);\n v17 = 0LL;\n v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n v22 = 0LL;\n v23 = 0LL;\n v24 = 0LL;\n v25 = 0LL;\n v26 = 0LL;\n v27 = 0LL;\n *(_QWORD *)&v28 = 0LL;\n *(_QWORD *)((char *)&v28 + 5) = 0LL;\n if ( strchr(s, 32) || strchr(s, 44) )\n {\n v4 = malloc(8LL * (v3 + 1));\n if ( v3 < 0 )\n {\n v7 = 0;\n }\n else\n {\n v5 = s;\n v6 = &s[v3 + 1];\n v7 = 0;\n v8 = 0;\n v9 = 0x100100000001LL;\n do\n {\n v13 = (unsigned __int8)*v5;\n if ( (unsigned __int8)v13 <= 0x2Cu && _bittest64(&v9, v13) )\n {\n if ( v8 > 0 )\n {\n *((_BYTE *)&v17 + v8) = 0;\n v4[v7++] = strdup((const char *)&v17);\n v8 = 0;\n }\n }\n else\n {\n *((_BYTE *)&v17 + v8++) = v13;\n }\n ++v5;\n }\n while ( v6 != v5 );\n }\n }\n else\n {\n v10 = 0;\n if ( v3 > 0 )\n {\n v11 = *__ctype_b_loc();\n v12 = s;\n v10 = 0;\n do\n {\n if ( (v11[*v12] & 0x200) != 0 )\n v10 += (*v12 - 97) % 2 == 1;\n ++v12;\n }\n while ( v12 != &s[v3 - 1 + 1] );\n }\n v4 = malloc(8uLL);\n v14 = malloc(0xCuLL);\n *v4 = v14;\n __sprintf_chk(\n v14,\n 2LL,\n 12LL,\n &unk_2004,\n v10,\n v15,\n v17,\n v18,\n v19,\n v20,\n v21,\n v22,\n v23,\n v24,\n v25,\n v26,\n v27,\n v28,\n *((_QWORD *)&v28 + 1),\n v29);\n v7 = 1;\n }\n *a2 = v7;\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1269(char *s, int *a2) {\n int v3;\n uint64_t *v4;\n char *v5;\n char *v6;\n int v7;\n int v8;\n long long v9;\n unsigned int v10;\n const unsigned short *v11;\n char *v12;\n unsigned long long v13;\n void *v14;\n long long v15;\n long long v17;\n long long v18;\n long long v19;\n long long v20;\n long long v21;\n long long v22;\n long long v23;\n long long v24;\n long long v25;\n long long v26;\n long long v27;\n __int128 v28;\n unsigned long long v29;\n v29 = __readfsqword(40u);\n v3 = strlen(s);\n v17 = 0LL;\n v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n v22 = 0LL;\n v23 = 0LL;\n v24 = 0LL;\n v25 = 0LL;\n v26 = 0LL;\n v27 = 0LL;\n *(uint64_t *)&v28 = 0LL;\n *(uint64_t *)((char *)&v28 + 5) = 0LL;\n if (strchr(s, 32) || strchr(s, 44)) {\n v4 = malloc(8LL * (v3 + 1));\n if (v3 < 0) {\n v7 = 0;\n } else {\n v5 = s;\n v6 = &s[v3 + 1];\n v7 = 0;\n v8 = 0;\n v9 = 17596481011713LL;\n do {\n v13 = (unsigned char)*v5;\n if ((unsigned char)v13 <= 44u && _bittest64(&v9, v13)) {\n if (v8 > 0) {\n *((uint8_t *)&v17 + v8) = 0;\n v4[v7++] = strdup((const char *)&v17);\n v8 = 0;\n }\n } else {\n *((uint8_t *)&v17 + v8++) = v13;\n }\n ++v5;\n } while (v6 != v5);\n }\n } else {\n v10 = 0;\n if (v3 > 0) {\n v11 = *__ctype_b_loc();\n v12 = s;\n v10 = 0;\n do {\n if ((v11[*v12] & 512) != 0) v10 += (*v12 - 97) % 2 == 1;\n ++v12;\n } while (v12 != &s[v3 - 1 + 1]);\n }\n v4 = malloc(8uLL);\n v14 = malloc(12uLL);\n *v4 = v14;\n __sprintf_chk(v14, 2LL, 12LL, &unk_2004, v10, v15, v17, v18, v19, v20, v21,\n v22, v23, v24, v25, v26, v27, v28, *((uint64_t *)&v28 + 1),\n v29);\n v7 = 1;\n }\n *a2 = v7;\n return v4;\n}", + "ida_pseudo_norm": "uint64_t *func0(char *s, int *a2) {\n int v3;\n uint64_t *v4;\n char *v5;\n char *v6;\n int v7;\n int v8;\n long long v9;\n unsigned int v10;\n const unsigned short *v11;\n char *v12;\n unsigned long long v13;\n void *v14;\n long long v15;\n long long v17;\n long long v18;\n long long v19;\n long long v20;\n long long v21;\n long long v22;\n long long v23;\n long long v24;\n long long v25;\n long long v26;\n long long v27;\n __int128 v28;\n unsigned long long v29;\n v29 = __readfsqword(40u);\n v3 = strlen(s);\n v17 = 0LL;\n v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n v22 = 0LL;\n v23 = 0LL;\n v24 = 0LL;\n v25 = 0LL;\n v26 = 0LL;\n v27 = 0LL;\n *(uint64_t *)&v28 = 0LL;\n *(uint64_t *)((char *)&v28 + 5) = 0LL;\n if (strchr(s, 32) || strchr(s, 44)) {\n v4 = malloc(8LL * (v3 + 1));\n if (v3 < 0) {\n v7 = 0;\n } else {\n v5 = s;\n v6 = &s[v3 + 1];\n v7 = 0;\n v8 = 0;\n v9 = 17596481011713LL;\n do {\n v13 = (unsigned char)*v5;\n if ((unsigned char)v13 <= 44u && _bittest64(&v9, v13)) {\n if (v8 > 0) {\n *((uint8_t *)&v17 + v8) = 0;\n v4[v7++] = strdup((const char *)&v17);\n v8 = 0;\n }\n } else {\n *((uint8_t *)&v17 + v8++) = v13;\n }\n ++v5;\n } while (v6 != v5);\n }\n } else {\n v10 = 0;\n if (v3 > 0) {\n v11 = *__ctype_b_loc();\n v12 = s;\n v10 = 0;\n do {\n if ((v11[*v12] & 512) != 0) v10 += (*v12 - 97) % 2 == 1;\n ++v12;\n } while (v12 != &s[v3 - 1 + 1]);\n }\n v4 = malloc(8uLL);\n v14 = malloc(12uLL);\n *v4 = v14;\n __sprintf_chk(v14, 2LL, 12LL, &unk_2004, v10, v15, v17, v18, v19, v20, v21,\n v22, v23, v24, v25, v26, v27, v28, *((uint64_t *)&v28 + 1),\n v29);\n v7 = 1;\n }\n *a2 = v7;\n return v4;\n}" + }, + { + "index": "HumanEval-C-125", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n#include \n", + "func": "char **func0(const char *txt, int *returnSize) {\n int i, j = 0, num = 0, count = 0;\n int len = strlen(txt);\n char **out = NULL;\n char current[101] = {0};\n if (strchr(txt, ' ') || strchr(txt, ',')) {\n out = malloc(sizeof(char *) * (len + 1));\n for (i = 0; i <= len; ++i) {\n if (txt[i] == ' ' || txt[i] == ',' || txt[i] == '\\0') {\n if (j > 0) {\n current[j] = '\\0';\n out[count] = strdup(current);\n count++;\n j = 0;\n }\n } else {\n current[j++] = txt[i];\n }\n }\n } else {\n for (i = 0; i < len; ++i) {\n if (islower(txt[i]) && ((txt[i] - 'a') % 2 == 1)) {\n num++;\n }\n }\n out = malloc(sizeof(char *));\n out[0] = malloc(sizeof(char) * 12);\n sprintf(out[0], \"%d\", num);\n count = 1;\n }\n *returnSize = count;\n return out;\n}", + "test": "#include \n#include \n#include \n#include \n\nint issame(char **a, int aSize, char **b, int bSize) {\n if (aSize != bSize) return 0;\n for (int i = 0; i < aSize; i++) {\n if (strcmp(a[i], b[i]) != 0) return 0;\n }\n return 1;\n}\n\nvoid free_words(char **words, int size) {\n for (int i = 0; i < size; i++) free(words[i]);\n free(words);\n}\n\nint main() {\n int size;\n char *expected[3];\n char **result;\n\n result = func0(\"Hello world!\", &size);\n expected[0] = \"Hello\";\n expected[1] = \"world!\";\n assert(issame(expected, 2,result, size)); \n free_words(result, size);\n\n result = func0(\"Hello,world!\", &size);\n expected[0] = \"Hello\";\n expected[1] = \"world!\";\n assert(issame(expected, 2,result, size));\n free_words(result, size);\n\n result = func0(\"abcdef\", &size);\n expected[0] = \"3\";\n assert(issame(expected, 1,result, size));\n free_words(result, size);\n\n result = func0(\"aaabb\", &size);\n expected[0] = \"2\";\n assert(issame(expected, 1,result, size));\n free_words(result, size);\n\n result = func0(\"aaaBb\", &size);\n expected[0] = \"1\";\n assert(issame(expected, 1,result, size));\n free_words(result, size);\n\n result = func0(\"\", &size);\n expected[0] = \"0\";\n assert(issame(expected, 1,result, size));\n free_words(result, size);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12, rsi\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 78h\nmov rax, fs:28h\nmov [rsp+0A8h+var_40], rax\nxor eax, eax\ncall _strlen\npxor xmm0, xmm0\nmov esi, 20h ; ' '; c\nmov rdi, rbx; s\nmovaps [rsp+0A8h+var_58], xmm0\nmov r13, rax\nmov qword ptr [rsp+0A8h+var_58+0Dh], 0\nmovaps [rsp+0A8h+var_A8], xmm0\nmovaps [rsp+0A8h+var_98], xmm0\nmovaps [rsp+0A8h+var_88], xmm0\nmovaps [rsp+0A8h+var_78], xmm0\nmovaps [rsp+0A8h+var_68], xmm0\ncall _strchr\ntest rax, rax\njz loc_16E0\nloc_1630:\nlea edi, [r13+1]\nmovsxd rdi, edi\nshl rdi, 3; size\ncall _malloc\nmov rbp, rax\ntest r13d, r13d\njs loc_1790\nmov r13d, r13d\nxor r14d, r14d\nxor edx, edx\nmov r15, 100100000001h\nlea r13, [rbx+r13+1]\njmp short loc_169B\nloc_1668:\nbt r15, rax\njnb short loc_16A2\ntest edx, edx\njle short loc_1692\nmovsxd rdx, edx\nmov rdi, rsp; s\nmov byte ptr [rsp+rdx+0A8h+var_A8], 0\ncall _strdup\nmov rdx, rax\nmovsxd rax, r14d\nadd r14d, 1\nmov [rbp+rax*8+0], rdx\nxor edx, edx\nloc_1692:\nadd rbx, 1\ncmp r13, rbx\njz short loc_16B4\nloc_169B:\nmovzx eax, byte ptr [rbx]\ncmp al, 2Ch ; ','\njbe short loc_1668\nloc_16A2:\nmovsxd rcx, edx\nadd rbx, 1\nadd edx, 1\nmov byte ptr [rsp+rcx+0A8h+var_A8], al\ncmp r13, rbx\njnz short loc_169B\nloc_16B4:\nmov [r12], r14d\nmov rax, [rsp+0A8h+var_40]\nsub rax, fs:28h\njnz loc_179D\nadd rsp, 78h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_16E0:\nmov esi, 2Ch ; ','; c\nmov rdi, rbx; s\ncall _strchr\ntest rax, rax\njnz loc_1630\ntest r13d, r13d\njle loc_1798\ncall ___ctype_b_loc\nmov rsi, [rax]\nlea eax, [r13-1]\nxor r13d, r13d\nlea rcx, [rbx+rax+1]\nnop dword ptr [rax+rax+00h]\nloc_1718:\nmovsx rdx, byte ptr [rbx]\nmov rax, rdx\ntest byte ptr [rsi+rdx*2+1], 2\njz short loc_1741\nsub eax, 61h ; 'a'\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nand eax, 1\nsub eax, edx\ncmp eax, 1\nsetz al\nmovzx eax, al\nadd r13d, eax\nloc_1741:\nadd rbx, 1\ncmp rcx, rbx\njnz short loc_1718\nloc_174A:\nmov edi, 8; size\nmov r14d, 1\ncall _malloc\nmov edi, 0Ch; size\nmov rbp, rax\ncall _malloc\nmov r8d, r13d\nmov edx, 0Ch\nlea rcx, unk_2004\nmov [rbp+0], rax\nmov rdi, rax\nmov esi, 2\nxor eax, eax\ncall ___sprintf_chk\njmp loc_16B4\nloc_1790:\nxor r14d, r14d\njmp loc_16B4\nloc_1798:\nxor r13d, r13d\njmp short loc_174A\nloc_179D:\ncall ___stack_chk_fail", + "ida_pseudo": "_QWORD *__fastcall func0(char *s, int *a2)\n{\n char *v3; // rbx\n int v4; // r13d\n _QWORD *v5; // rbp\n int v6; // r14d\n int v7; // edx\n __int64 v8; // r15\n char *v9; // r13\n char *v10; // rdx\n __int64 v11; // rax\n unsigned __int64 v12; // rax\n __int64 v13; // rcx\n const unsigned __int16 *v15; // rsi\n __int64 v16; // rax\n unsigned int v17; // r13d\n __int64 v18; // rdx\n void *v19; // rax\n __int64 v20; // r9\n __int128 v21; // [rsp+0h] [rbp-A8h] BYREF\n __int128 v22; // [rsp+10h] [rbp-98h]\n __int128 v23; // [rsp+20h] [rbp-88h]\n __int128 v24; // [rsp+30h] [rbp-78h]\n __int128 v25; // [rsp+40h] [rbp-68h]\n _QWORD v26[3]; // [rsp+50h] [rbp-58h] BYREF\n unsigned __int64 v27; // [rsp+68h] [rbp-40h]\n\n v3 = s;\n v27 = __readfsqword(0x28u);\n memset(v26, 0, 21);\n v4 = strlen(s);\n v21 = 0LL;\n v22 = 0LL;\n v23 = 0LL;\n v24 = 0LL;\n v25 = 0LL;\n if ( strchr(s, 32) || strchr(s, 44) )\n {\n v5 = malloc(8LL * (v4 + 1));\n if ( v4 < 0 )\n {\n v6 = 0;\n }\n else\n {\n v6 = 0;\n v7 = 0;\n v8 = 0x100100000001LL;\n v9 = &s[v4 + 1];\n do\n {\n while ( 1 )\n {\n v12 = (unsigned __int8)*v3;\n if ( (unsigned __int8)v12 <= 0x2Cu )\n {\n if ( _bittest64(&v8, v12) )\n break;\n }\n v13 = v7;\n ++v3;\n ++v7;\n *((_BYTE *)&v21 + v13) = v12;\n if ( v9 == v3 )\n goto LABEL_10;\n }\n if ( v7 > 0 )\n {\n *((_BYTE *)&v21 + v7) = 0;\n v10 = strdup((const char *)&v21);\n v11 = v6++;\n v5[v11] = v10;\n v7 = 0;\n }\n ++v3;\n }\n while ( v9 != v3 );\n }\n }\n else\n {\n if ( v4 <= 0 )\n {\n v17 = 0;\n }\n else\n {\n v15 = *__ctype_b_loc();\n v16 = (unsigned int)(v4 - 1);\n v17 = 0;\n do\n {\n v18 = *v3;\n if ( (v15[v18] & 0x200) != 0 )\n v17 += ((int)v18 - 97) % 2 == 1;\n ++v3;\n }\n while ( &s[v16 + 1] != v3 );\n }\n v6 = 1;\n v5 = malloc(8uLL);\n v19 = malloc(0xCuLL);\n *v5 = v19;\n __sprintf_chk(\n v19,\n 2LL,\n 12LL,\n &unk_2004,\n v17,\n v20,\n v21,\n *((_QWORD *)&v21 + 1),\n v22,\n *((_QWORD *)&v22 + 1),\n v23,\n *((_QWORD *)&v23 + 1),\n v24,\n *((_QWORD *)&v24 + 1),\n v25,\n *((_QWORD *)&v25 + 1),\n v26[0],\n v26[1],\n v26[2],\n v27);\n }\nLABEL_10:\n *a2 = v6;\n return v5;\n}", + "ida_strip_asm": "sub_15C0:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12, rsi\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 78h\nmov rax, fs:28h\nmov [rsp+0A8h+var_40], rax\nxor eax, eax\ncall _strlen\npxor xmm0, xmm0\nmov esi, 20h ; ' '; c\nmov rdi, rbx; s\nmovaps [rsp+0A8h+var_58], xmm0\nmov r13, rax\nmov qword ptr [rsp+0A8h+var_58+0Dh], 0\nmovaps [rsp+0A8h+var_A8], xmm0\nmovaps [rsp+0A8h+var_98], xmm0\nmovaps [rsp+0A8h+var_88], xmm0\nmovaps [rsp+0A8h+var_78], xmm0\nmovaps [rsp+0A8h+var_68], xmm0\ncall _strchr\ntest rax, rax\njz loc_16E0\nloc_1630:\nlea edi, [r13+1]\nmovsxd rdi, edi\nshl rdi, 3; size\ncall _malloc\nmov rbp, rax\ntest r13d, r13d\njs loc_1790\nmov r13d, r13d\nxor r14d, r14d\nxor edx, edx\nmov r15, 100100000001h\nlea r13, [rbx+r13+1]\njmp short loc_169B\nloc_1668:\nbt r15, rax\njnb short loc_16A2\ntest edx, edx\njle short loc_1692\nmovsxd rdx, edx\nmov rdi, rsp; s\nmov byte ptr [rsp+rdx+0A8h+var_A8], 0\ncall _strdup\nmov rdx, rax\nmovsxd rax, r14d\nadd r14d, 1\nmov [rbp+rax*8+0], rdx\nxor edx, edx\nloc_1692:\nadd rbx, 1\ncmp r13, rbx\njz short loc_16B4\nloc_169B:\nmovzx eax, byte ptr [rbx]\ncmp al, 2Ch ; ','\njbe short loc_1668\nloc_16A2:\nmovsxd rcx, edx\nadd rbx, 1\nadd edx, 1\nmov byte ptr [rsp+rcx+0A8h+var_A8], al\ncmp r13, rbx\njnz short loc_169B\nloc_16B4:\nmov [r12], r14d\nmov rax, [rsp+0A8h+var_40]\nsub rax, fs:28h\njnz loc_179D\nadd rsp, 78h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_16E0:\nmov esi, 2Ch ; ','; c\nmov rdi, rbx; s\ncall _strchr\ntest rax, rax\njnz loc_1630\ntest r13d, r13d\njle loc_1798\ncall ___ctype_b_loc\nmov rsi, [rax]\nlea eax, [r13-1]\nxor r13d, r13d\nlea rcx, [rbx+rax+1]\nnop dword ptr [rax+rax+00h]\nloc_1718:\nmovsx rdx, byte ptr [rbx]\nmov rax, rdx\ntest byte ptr [rsi+rdx*2+1], 2\njz short loc_1741\nsub eax, 61h ; 'a'\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nand eax, 1\nsub eax, edx\ncmp eax, 1\nsetz al\nmovzx eax, al\nadd r13d, eax\nloc_1741:\nadd rbx, 1\ncmp rcx, rbx\njnz short loc_1718\nloc_174A:\nmov edi, 8; size\nmov r14d, 1\ncall _malloc\nmov edi, 0Ch; size\nmov rbp, rax\ncall _malloc\nmov r8d, r13d\nmov edx, 0Ch\nlea rcx, unk_2004\nmov [rbp+0], rax\nmov rdi, rax\nmov esi, 2\nxor eax, eax\ncall ___sprintf_chk\njmp loc_16B4\nloc_1790:\nxor r14d, r14d\njmp loc_16B4\nloc_1798:\nxor r13d, r13d\njmp short loc_174A\nloc_179D:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_QWORD *__fastcall sub_15C0(char *s, int *a2)\n{\n char *v3; // rbx\n int v4; // r13d\n _QWORD *v5; // rbp\n int v6; // r14d\n int v7; // edx\n __int64 v8; // r15\n char *v9; // r13\n char *v10; // rdx\n __int64 v11; // rax\n unsigned __int64 v12; // rax\n __int64 v13; // rcx\n const unsigned __int16 *v15; // rsi\n __int64 v16; // rax\n unsigned int v17; // r13d\n __int64 v18; // rdx\n void *v19; // rax\n __int64 v20; // r9\n __int128 v21; // [rsp+0h] [rbp-A8h] BYREF\n __int128 v22; // [rsp+10h] [rbp-98h]\n __int128 v23; // [rsp+20h] [rbp-88h]\n __int128 v24; // [rsp+30h] [rbp-78h]\n __int128 v25; // [rsp+40h] [rbp-68h]\n _QWORD v26[3]; // [rsp+50h] [rbp-58h] BYREF\n unsigned __int64 v27; // [rsp+68h] [rbp-40h]\n\n v3 = s;\n v27 = __readfsqword(0x28u);\n memset(v26, 0, 21);\n v4 = strlen(s);\n v21 = 0LL;\n v22 = 0LL;\n v23 = 0LL;\n v24 = 0LL;\n v25 = 0LL;\n if ( strchr(s, 32) || strchr(s, 44) )\n {\n v5 = malloc(8LL * (v4 + 1));\n if ( v4 < 0 )\n {\n v6 = 0;\n }\n else\n {\n v6 = 0;\n v7 = 0;\n v8 = 0x100100000001LL;\n v9 = &s[v4 + 1];\n do\n {\n while ( 1 )\n {\n v12 = (unsigned __int8)*v3;\n if ( (unsigned __int8)v12 <= 0x2Cu )\n {\n if ( _bittest64(&v8, v12) )\n break;\n }\n v13 = v7;\n ++v3;\n ++v7;\n *((_BYTE *)&v21 + v13) = v12;\n if ( v9 == v3 )\n goto LABEL_10;\n }\n if ( v7 > 0 )\n {\n *((_BYTE *)&v21 + v7) = 0;\n v10 = strdup((const char *)&v21);\n v11 = v6++;\n v5[v11] = v10;\n v7 = 0;\n }\n ++v3;\n }\n while ( v9 != v3 );\n }\n }\n else\n {\n if ( v4 <= 0 )\n {\n v17 = 0;\n }\n else\n {\n v15 = *__ctype_b_loc();\n v16 = (unsigned int)(v4 - 1);\n v17 = 0;\n do\n {\n v18 = *v3;\n if ( (v15[v18] & 0x200) != 0 )\n v17 += ((int)v18 - 97) % 2 == 1;\n ++v3;\n }\n while ( &s[v16 + 1] != v3 );\n }\n v6 = 1;\n v5 = malloc(8uLL);\n v19 = malloc(0xCuLL);\n *v5 = v19;\n __sprintf_chk(\n v19,\n 2LL,\n 12LL,\n &unk_2004,\n v17,\n v20,\n v21,\n *((_QWORD *)&v21 + 1),\n v22,\n *((_QWORD *)&v22 + 1),\n v23,\n *((_QWORD *)&v23 + 1),\n v24,\n *((_QWORD *)&v24 + 1),\n v25,\n *((_QWORD *)&v25 + 1),\n v26[0],\n v26[1],\n v26[2],\n v27);\n }\nLABEL_10:\n *a2 = v6;\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_15C0(char *s, int *a2) {\n char *v3;\n int v4;\n uint64_t *v5;\n int v6;\n int v7;\n long long v8;\n char *v9;\n char *v10;\n long long v11;\n unsigned long long v12;\n long long v13;\n const unsigned short *v15;\n long long v16;\n unsigned int v17;\n long long v18;\n void *v19;\n long long v20;\n __int128 v21;\n __int128 v22;\n __int128 v23;\n __int128 v24;\n __int128 v25;\n uint64_t v26[3];\n unsigned long long v27;\n v3 = s;\n v27 = __readfsqword(40u);\n memset(v26, 0, 21);\n v4 = strlen(s);\n v21 = 0LL;\n v22 = 0LL;\n v23 = 0LL;\n v24 = 0LL;\n v25 = 0LL;\n if (strchr(s, 32) || strchr(s, 44)) {\n v5 = malloc(8LL * (v4 + 1));\n if (v4 < 0) {\n v6 = 0;\n } else {\n v6 = 0;\n v7 = 0;\n v8 = 17596481011713LL;\n v9 = &s[v4 + 1];\n do {\n while (1) {\n v12 = (unsigned char)*v3;\n if ((unsigned char)v12 <= 44u) {\n if (_bittest64(&v8, v12)) break;\n }\n v13 = v7;\n ++v3;\n ++v7;\n *((uint8_t *)&v21 + v13) = v12;\n if (v9 == v3) goto LABEL_10;\n }\n if (v7 > 0) {\n *((uint8_t *)&v21 + v7) = 0;\n v10 = strdup((const char *)&v21);\n v11 = v6++;\n v5[v11] = v10;\n v7 = 0;\n }\n ++v3;\n } while (v9 != v3);\n }\n } else {\n if (v4 <= 0) {\n v17 = 0;\n } else {\n v15 = *__ctype_b_loc();\n v16 = (unsigned int)(v4 - 1);\n v17 = 0;\n do {\n v18 = *v3;\n if ((v15[v18] & 512) != 0) v17 += ((int)v18 - 97) % 2 == 1;\n ++v3;\n } while (&s[v16 + 1] != v3);\n }\n v6 = 1;\n v5 = malloc(8uLL);\n v19 = malloc(12uLL);\n *v5 = v19;\n __sprintf_chk(v19, 2LL, 12LL, &unk_2004, v17, v20, v21,\n *((uint64_t *)&v21 + 1), v22, *((uint64_t *)&v22 + 1), v23,\n *((uint64_t *)&v23 + 1), v24, *((uint64_t *)&v24 + 1), v25,\n *((uint64_t *)&v25 + 1), v26[0], v26[1], v26[2], v27);\n }\nLABEL_10:\n *a2 = v6;\n return v5;\n}", + "ida_pseudo_norm": "uint64_t *func0(char *s, int *a2) {\n char *v3;\n int v4;\n uint64_t *v5;\n int v6;\n int v7;\n long long v8;\n char *v9;\n char *v10;\n long long v11;\n unsigned long long v12;\n long long v13;\n const unsigned short *v15;\n long long v16;\n unsigned int v17;\n long long v18;\n void *v19;\n long long v20;\n __int128 v21;\n __int128 v22;\n __int128 v23;\n __int128 v24;\n __int128 v25;\n uint64_t v26[3];\n unsigned long long v27;\n v3 = s;\n v27 = __readfsqword(40u);\n memset(v26, 0, 21);\n v4 = strlen(s);\n v21 = 0LL;\n v22 = 0LL;\n v23 = 0LL;\n v24 = 0LL;\n v25 = 0LL;\n if (strchr(s, 32) || strchr(s, 44)) {\n v5 = malloc(8LL * (v4 + 1));\n if (v4 < 0) {\n v6 = 0;\n } else {\n v6 = 0;\n v7 = 0;\n v8 = 17596481011713LL;\n v9 = &s[v4 + 1];\n do {\n while (1) {\n v12 = (unsigned char)*v3;\n if ((unsigned char)v12 <= 44u) {\n if (_bittest64(&v8, v12)) break;\n }\n v13 = v7;\n ++v3;\n ++v7;\n *((uint8_t *)&v21 + v13) = v12;\n if (v9 == v3) goto LABEL_10;\n }\n if (v7 > 0) {\n *((uint8_t *)&v21 + v7) = 0;\n v10 = strdup((const char *)&v21);\n v11 = v6++;\n v5[v11] = v10;\n v7 = 0;\n }\n ++v3;\n } while (v9 != v3);\n }\n } else {\n if (v4 <= 0) {\n v17 = 0;\n } else {\n v15 = *__ctype_b_loc();\n v16 = (unsigned int)(v4 - 1);\n v17 = 0;\n do {\n v18 = *v3;\n if ((v15[v18] & 512) != 0) v17 += ((int)v18 - 97) % 2 == 1;\n ++v3;\n } while (&s[v16 + 1] != v3);\n }\n v6 = 1;\n v5 = malloc(8uLL);\n v19 = malloc(12uLL);\n *v5 = v19;\n __sprintf_chk(v19, 2LL, 12LL, &unk_2004, v17, v20, v21,\n *((uint64_t *)&v21 + 1), v22, *((uint64_t *)&v22 + 1), v23,\n *((uint64_t *)&v23 + 1), v24, *((uint64_t *)&v24 + 1), v25,\n *((uint64_t *)&v25 + 1), v26[0], v26[1], v26[2], v27);\n }\nLABEL_10:\n *a2 = v6;\n return v5;\n}" + }, + { + "index": "HumanEval-C-125", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n#include \n", + "func": "char **func0(const char *txt, int *returnSize) {\n int i, j = 0, num = 0, count = 0;\n int len = strlen(txt);\n char **out = NULL;\n char current[101] = {0};\n if (strchr(txt, ' ') || strchr(txt, ',')) {\n out = malloc(sizeof(char *) * (len + 1));\n for (i = 0; i <= len; ++i) {\n if (txt[i] == ' ' || txt[i] == ',' || txt[i] == '\\0') {\n if (j > 0) {\n current[j] = '\\0';\n out[count] = strdup(current);\n count++;\n j = 0;\n }\n } else {\n current[j++] = txt[i];\n }\n }\n } else {\n for (i = 0; i < len; ++i) {\n if (islower(txt[i]) && ((txt[i] - 'a') % 2 == 1)) {\n num++;\n }\n }\n out = malloc(sizeof(char *));\n out[0] = malloc(sizeof(char) * 12);\n sprintf(out[0], \"%d\", num);\n count = 1;\n }\n *returnSize = count;\n return out;\n}", + "test": "#include \n#include \n#include \n#include \n\nint issame(char **a, int aSize, char **b, int bSize) {\n if (aSize != bSize) return 0;\n for (int i = 0; i < aSize; i++) {\n if (strcmp(a[i], b[i]) != 0) return 0;\n }\n return 1;\n}\n\nvoid free_words(char **words, int size) {\n for (int i = 0; i < size; i++) free(words[i]);\n free(words);\n}\n\nint main() {\n int size;\n char *expected[3];\n char **result;\n\n result = func0(\"Hello world!\", &size);\n expected[0] = \"Hello\";\n expected[1] = \"world!\";\n assert(issame(expected, 2,result, size)); \n free_words(result, size);\n\n result = func0(\"Hello,world!\", &size);\n expected[0] = \"Hello\";\n expected[1] = \"world!\";\n assert(issame(expected, 2,result, size));\n free_words(result, size);\n\n result = func0(\"abcdef\", &size);\n expected[0] = \"3\";\n assert(issame(expected, 1,result, size));\n free_words(result, size);\n\n result = func0(\"aaabb\", &size);\n expected[0] = \"2\";\n assert(issame(expected, 1,result, size));\n free_words(result, size);\n\n result = func0(\"aaaBb\", &size);\n expected[0] = \"1\";\n assert(issame(expected, 1,result, size));\n free_words(result, size);\n\n result = func0(\"\", &size);\n expected[0] = \"0\";\n assert(issame(expected, 1,result, size));\n free_words(result, size);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12, rsi\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 168h\nmov rax, fs:28h\nmov [rsp+198h+var_40], rax\nxor eax, eax\ncall _strlen\npxor xmm0, xmm0\nmov esi, 20h ; ' '; c\nmov rdi, rbx; s\nmovaps [rsp+198h+var_58], xmm0\nmov r13, rax\nmov qword ptr [rsp+198h+var_58+0Dh], 0\nmovaps xmmword ptr [rsp+198h+s], xmm0\nmovaps [rsp+198h+var_98], xmm0\nmovaps [rsp+198h+var_88], xmm0\nmovaps [rsp+198h+var_78], xmm0\nmovaps [rsp+198h+var_68], xmm0\ncall _strchr\ntest rax, rax\njz loc_1718\nloc_164C:\nlea edi, [r13+1]\nmovsxd rdi, edi\nshl rdi, 3; size\ncall _malloc\nmov rbp, rax\ntest r13d, r13d\njs loc_1E98\nmov r13d, r13d\nxor r14d, r14d\nxor edx, edx\nmov r15, 100100000001h\nlea r13, [rbx+r13+1]\njmp short loc_16C4\nloc_1688:\nbt r15, rax\njnb short loc_16CB\ntest edx, edx\njle short loc_16BB\nmovsxd rdx, edx\nlea rdi, [rsp+198h+s]; s\nmov [rsp+rdx+198h+s], 0\ncall _strdup\nmov rdx, rax\nmovsxd rax, r14d\nadd r14d, 1\nmov [rbp+rax*8+0], rdx\nxor edx, edx\nloc_16BB:\nadd rbx, 1\ncmp r13, rbx\njz short loc_16E1\nloc_16C4:\nmovzx eax, byte ptr [rbx]\ncmp al, 2Ch ; ','\njbe short loc_1688\nloc_16CB:\nmovsxd rcx, edx\nadd rbx, 1\nadd edx, 1\nmov [rsp+rcx+198h+s], al\ncmp r13, rbx\njnz short loc_16C4\nloc_16E1:\nmov [r12], r14d\nmov rax, [rsp+198h+var_40]\nsub rax, fs:28h\njnz loc_1F50\nadd rsp, 168h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1718:\nmov esi, 2Ch ; ','; c\nmov rdi, rbx; s\ncall _strchr\ntest rax, rax\njnz loc_164C\nxor r14d, r14d\ntest r13d, r13d\njle loc_1E50\ncall ___ctype_b_loc\nlea edx, [r13-1]\nmov rax, [rax]\ncmp edx, 0Eh\njbe loc_1F40\nmov esi, r13d\nmov rcx, rbx\npxor xmm3, xmm3\nmovdqa xmm7, cs:xmmword_30C0\nshr esi, 4\npxor xmm8, xmm8\npxor xmm4, xmm4\nmovdqa xmm6, cs:xmmword_30D0\nshl rsi, 4\nmovdqa xmm5, cs:xmmword_30E0\nadd rsi, rbx\nnop dword ptr [rax+00h]\nloc_1788:\nmovdqu xmm0, xmmword ptr [rcx]\nadd rcx, 10h\nmovd edx, xmm0\nmovaps [rsp+198h+var_B8], xmm0\nmovsx r14, byte ptr [rsp+198h+var_B8+1]\nmovdqa xmm13, xmm0\nmovsx rdx, dl\nmovaps [rsp+198h+var_C8], xmm0\nmovsx rbp, byte ptr [rsp+198h+var_C8+2]\nmovaps [rsp+198h+var_D8], xmm0\nmovsx r11, byte ptr [rsp+198h+var_D8+3]\nmovaps [rsp+198h+var_E8], xmm0\nmovsx r10, byte ptr [rsp+198h+var_E8+4]\nmovaps [rsp+198h+var_F8], xmm0\nmovsx r9, byte ptr [rsp+198h+var_F8+5]\nmovaps [rsp+198h+var_108], xmm0\nmovsx r8, byte ptr [rsp+198h+var_108+6]\nmovaps [rsp+198h+var_118], xmm0\nmovzx edx, word ptr [rax+rdx*2]\nmovsx rdi, byte ptr [rsp+198h+var_118+7]\nmovd xmm14, edx\nmovzx edx, word ptr [rax+rbp*2]\npinsrw xmm14, word ptr [rax+r14*2], 1\nmovd xmm9, edx\nmovzx edx, word ptr [rax+r10*2]\npinsrw xmm9, word ptr [rax+r11*2], 1\nmovd xmm1, edx\nmovzx edx, word ptr [rax+r8*2]\npinsrw xmm1, word ptr [rax+r9*2], 1\npunpckldq xmm14, xmm9\nmovd xmm2, edx\npinsrw xmm2, word ptr [rax+rdi*2], 1\nmovaps [rsp+198h+var_128], xmm0\nmovsx r14, byte ptr [rsp+198h+var_128+8]\nmovaps [rsp+198h+var_138], xmm0\nmovsx rbp, byte ptr [rsp+198h+var_138+9]\nmovaps [rsp+198h+var_148], xmm0\nmovsx r11, byte ptr [rsp+198h+var_148+0Ah]\npunpckldq xmm1, xmm2\nmovaps [rsp+198h+var_158], xmm0\nmovsx r10, byte ptr [rsp+198h+var_158+0Bh]\npunpcklqdq xmm14, xmm1\nmovaps [rsp+198h+var_168], xmm0\nmovsx r9, byte ptr [rsp+198h+var_168+0Ch]\npand xmm14, xmm7\nmovaps [rsp+198h+var_188], xmm0\nmovsx rdi, byte ptr [rsp+198h+var_188+0Eh]\npcmpeqw xmm14, xmm4\nmovaps [rsp+198h+var_178], xmm0\nmovsx r8, byte ptr [rsp+198h+var_178+0Dh]\nmovaps [rsp+198h+var_198], xmm0\nmovsx rdx, byte ptr [rsp+198h+var_198+0Fh]\nmovzx r14d, word ptr [rax+r14*2]\nmovzx r11d, word ptr [rax+r11*2]\nmovzx r9d, word ptr [rax+r9*2]\npcmpeqw xmm14, xmm4\nmovzx edi, word ptr [rax+rdi*2]\nmovd xmm9, r14d\npinsrw xmm9, word ptr [rax+rbp*2], 1\nmovd xmm10, r11d\nmovd xmm1, r9d\npinsrw xmm10, word ptr [rax+r10*2], 1\npinsrw xmm1, word ptr [rax+r8*2], 1\nmovd xmm2, edi\npinsrw xmm2, word ptr [rax+rdx*2], 1\npunpckldq xmm9, xmm10\nmovdqa xmm10, xmm4\npunpckldq xmm1, xmm2\npunpcklqdq xmm9, xmm1\nmovdqa xmm1, xmm8\npcmpgtb xmm1, xmm0\npand xmm9, xmm7\npcmpeqw xmm9, xmm4\npunpcklbw xmm13, xmm1\npunpckhbw xmm0, xmm1\nmovdqa xmm1, xmm4\npcmpgtw xmm1, xmm13\npcmpgtw xmm10, xmm0\nmovdqa xmm2, xmm13\npcmpeqw xmm9, xmm4\npunpcklwd xmm2, xmm1\npunpckhwd xmm13, xmm1\nmovdqa xmm1, xmm0\npaddd xmm2, xmm6\npunpckhwd xmm0, xmm10\npunpcklwd xmm1, xmm10\nmovdqa xmm10, xmm0\nmovdqa xmm0, xmm2\npaddd xmm13, xmm6\npsrld xmm0, 1Fh\nmovdqa xmm15, xmm13\npaddd xmm1, xmm6\npaddd xmm2, xmm0\npsrld xmm15, 1Fh\nmovdqa xmm12, xmm1\npand xmm2, xmm5\npsrld xmm12, 1Fh\npaddd xmm10, xmm6\npsubd xmm2, xmm0\nmovdqa xmm0, xmm13\nmovdqa xmm11, xmm10\npaddd xmm0, xmm15\npcmpeqd xmm2, xmm5\npaddd xmm1, xmm12\npand xmm0, xmm5\npsrld xmm11, 1Fh\npsubd xmm0, xmm15\npcmpeqd xmm0, xmm5\nmovdqa xmm13, xmm2\npunpcklwd xmm2, xmm0\npunpckhwd xmm13, xmm0\nmovdqa xmm0, xmm2\npunpcklwd xmm2, xmm13\npunpckhwd xmm0, xmm13\npunpcklwd xmm2, xmm0\nmovdqa xmm0, xmm1\nmovdqa xmm1, xmm10\npaddd xmm1, xmm11\npand xmm0, xmm5\npand xmm2, xmm14\npand xmm1, xmm5\npsubd xmm0, xmm12\npsubd xmm1, xmm11\npcmpeqd xmm0, xmm5\npcmpeqd xmm1, xmm5\nmovdqa xmm10, xmm0\npunpcklwd xmm0, xmm1\npunpckhwd xmm10, xmm1\nmovdqa xmm1, xmm0\npunpcklwd xmm0, xmm10\npunpckhwd xmm1, xmm10\npunpcklwd xmm0, xmm1\nmovdqa xmm1, xmm4\npcmpgtw xmm1, xmm2\npand xmm0, xmm9\nmovdqa xmm9, xmm2\npunpcklwd xmm9, xmm1\npunpckhwd xmm2, xmm1\nmovdqa xmm1, xmm4\npcmpgtw xmm1, xmm0\npsubd xmm3, xmm9\npsubd xmm3, xmm2\nmovdqa xmm2, xmm0\npunpcklwd xmm2, xmm1\npunpckhwd xmm0, xmm1\npsubd xmm3, xmm2\npsubd xmm3, xmm0\ncmp rsi, rcx\njnz loc_1788\nmovdqa xmm0, xmm3\nmov esi, r13d\npsrldq xmm0, 8\nand esi, 0FFFFFFF0h\npaddd xmm0, xmm3\nmov edx, esi\nmovdqa xmm1, xmm0\npsrldq xmm1, 4\npaddd xmm0, xmm1\nmovdqa xmm1, xmm3\npsrldq xmm3, 8\npaddd xmm3, xmm1\nmovd r14d, xmm0\ntest r13b, 0Fh\njz loc_1E50\nloc_1AC7:\nmov ecx, r13d\nsub ecx, esi\nlea edi, [rcx-1]\ncmp edi, 6\njbe loc_1D47\nmov rsi, [rbx+rsi]\npxor xmm0, xmm0\npxor xmm5, xmm5\nmovq xmm7, qword ptr cs:xmmword_30C0\nmovq xmm8, qword ptr cs:xmmword_30D0\nmovdqa xmm9, xmm5\nmov rdi, rsi\nmov r10d, esi\nmov r9d, esi\nmovsx r8, sil\nshl r10d, 8\nsar edi, 18h\nmovzx r8d, word ptr [rax+r8*2]\nmovq xmm2, rsi\nsar r10d, 18h\nmovsx rdi, dil\nsar r9w, 8\nmovzx edi, word ptr [rax+rdi*2]\nmovsx r10, r10b\nmovsx r9, r9b\nmovzx r10d, word ptr [rax+r10*2]\nmovzx r9d, word ptr [rax+r9*2]\nshl rdi, 10h\nor rdi, r10\nmov r10, rsi\nshl rdi, 10h\nshl r10, 8\nor rdi, r9\nsar r10, 38h\nmov r9, rsi\nshl rdi, 10h\nshl r9, 10h\nmovzx r10d, word ptr [rax+r10*2]\nor rdi, r8\nsar r9, 38h\nmov r8, rsi\nmovq xmm4, rdi\nmov rdi, rsi\nshl r8, 18h\nmovzx r9d, word ptr [rax+r9*2]\nsar rdi, 38h\nsar r8, 38h\npand xmm4, xmm7\nmovzx edi, word ptr [rax+rdi*2]\nmovzx r8d, word ptr [rax+r8*2]\npcmpeqw xmm4, xmm5\nshl rdi, 10h\nor rdi, r10\npcmpeqw xmm4, xmm5\nshl rdi, 10h\nor rdi, r9\nshl rdi, 10h\nor rdi, r8\nmovq xmm6, rdi\npand xmm7, xmm6\nmovq xmm6, rsi\npcmpgtb xmm0, xmm6\npcmpeqw xmm7, xmm5\npunpcklbw xmm6, xmm0\npcmpeqw xmm7, xmm5\npunpcklbw xmm2, xmm0\nmovdqa xmm0, xmm5\npshufd xmm2, xmm2, 4Eh ; 'N'\nmovdqa xmm1, xmm6\npcmpgtw xmm0, xmm6\npcmpgtw xmm9, xmm2\npunpcklwd xmm1, xmm0\npunpcklwd xmm6, xmm0\nmovdqa xmm0, xmm2\npaddd xmm1, xmm8\npshufd xmm6, xmm6, 4Eh ; 'N'\npunpcklwd xmm0, xmm9\npaddd xmm6, xmm8\npunpcklwd xmm2, xmm9\npxor xmm9, xmm9\nmovdqa xmm12, xmm9\nmovdqa xmm11, xmm9\npshufd xmm2, xmm2, 4Eh ; 'N'\npcmpgtd xmm12, xmm1\npaddd xmm0, xmm8\npaddd xmm2, xmm8\nmovq xmm8, qword ptr cs:xmmword_30E0\npcmpgtd xmm11, xmm6\nmovdqa xmm10, xmm9\npcmpgtd xmm10, xmm0\npcmpgtd xmm9, xmm2\npand xmm12, xmm8\npand xmm11, xmm8\npaddd xmm1, xmm12\npaddd xmm6, xmm11\npand xmm10, xmm8\npand xmm9, xmm8\npand xmm1, xmm8\npaddd xmm0, xmm10\npaddd xmm2, xmm9\npsubd xmm1, xmm12\npand xmm6, xmm8\npsubd xmm6, xmm11\npand xmm0, xmm8\npand xmm2, xmm8\npcmpeqd xmm1, xmm8\npsubd xmm0, xmm10\npsubd xmm2, xmm9\npcmpeqd xmm6, xmm8\npcmpeqd xmm0, xmm8\npcmpeqd xmm2, xmm8\nmovdqa xmm11, xmm1\npunpcklwd xmm11, xmm6\npunpcklwd xmm1, xmm6\npshufd xmm11, xmm11, 4Eh ; 'N'\npunpcklwd xmm1, xmm11\npand xmm1, xmm4\nmovdqa xmm4, xmm0\npunpcklwd xmm0, xmm2\npunpcklwd xmm4, xmm2\nmovdqa xmm2, xmm5\npcmpgtw xmm2, xmm1\npshufd xmm4, xmm4, 4Eh ; 'N'\npunpcklwd xmm0, xmm4\nmovdqa xmm4, xmm1\npand xmm0, xmm7\npunpcklwd xmm4, xmm2\npcmpgtw xmm5, xmm0\npunpcklwd xmm1, xmm2\npsubd xmm3, xmm4\npshufd xmm1, xmm1, 4Eh ; 'N'\nmovdqa xmm2, xmm0\npunpcklwd xmm2, xmm5\npunpcklwd xmm0, xmm5\npsubd xmm3, xmm1\npshufd xmm0, xmm0, 4Eh ; 'N'\npsubd xmm3, xmm2\npsubd xmm3, xmm0\nmovd r14d, xmm3\npshufd xmm7, xmm3, 0E5h\nmovd esi, xmm7\nadd r14d, esi\nmov esi, ecx\nand esi, 0FFFFFFF8h\nadd edx, esi\nand ecx, 7\njz loc_1E50\nloc_1D47:\nmovsxd rcx, edx\nmovsx rsi, byte ptr [rbx+rcx]\nmov rcx, rsi\ntest byte ptr [rax+rsi*2+1], 2\njz short loc_1D74\nsub ecx, 61h ; 'a'\nmov esi, ecx\nshr esi, 1Fh\nadd ecx, esi\nand ecx, 1\nsub ecx, esi\ncmp ecx, 1\nsetz cl\nmovzx ecx, cl\nadd r14d, ecx\nloc_1D74:\nlea ecx, [rdx+1]\ncmp ecx, r13d\njge loc_1E50\nmovsxd rcx, ecx\nmovsx rsi, byte ptr [rbx+rcx]\nmov rcx, rsi\ntest byte ptr [rax+rsi*2+1], 2\njnz loc_1EA0\nloc_1D96:\nlea ecx, [rdx+2]\ncmp r13d, ecx\njle loc_1E50\nmovsxd rcx, ecx\nmovsx rsi, byte ptr [rbx+rcx]\nmov rcx, rsi\ntest byte ptr [rax+rsi*2+1], 2\njnz loc_1EC0\nloc_1DB8:\nlea ecx, [rdx+3]\ncmp r13d, ecx\njle loc_1E50\nmovsxd rcx, ecx\nmovsx rsi, byte ptr [rbx+rcx]\nmov rcx, rsi\ntest byte ptr [rax+rsi*2+1], 2\njnz loc_1EE0\nloc_1DDA:\nlea ecx, [rdx+4]\ncmp r13d, ecx\njle short loc_1E50\nmovsxd rcx, ecx\nmovsx rsi, byte ptr [rbx+rcx]\nmov rcx, rsi\ntest byte ptr [rax+rsi*2+1], 2\njnz loc_1F00\nloc_1DF8:\nlea ecx, [rdx+5]\ncmp r13d, ecx\njle short loc_1E50\nmovsxd rcx, ecx\nmovsx rsi, byte ptr [rbx+rcx]\nmov rcx, rsi\ntest byte ptr [rax+rsi*2+1], 2\njnz loc_1F20\nloc_1E16:\nadd edx, 6\ncmp r13d, edx\njle short loc_1E50\nmovsxd rdx, edx\nmovsx rcx, byte ptr [rbx+rdx]\ntest byte ptr [rax+rcx*2+1], 2\njz short loc_1E50\nmovsx eax, cl\nsub eax, 61h ; 'a'\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nand eax, 1\nsub eax, edx\ncmp eax, 1\nsetz al\nmovzx eax, al\nadd r14d, eax\nnop dword ptr [rax+rax+00h]\nloc_1E50:\nmov edi, 8; size\ncall _malloc\nmov edi, 0Ch; size\nmov rbp, rax\ncall _malloc\nmov r8d, r14d\nmov edx, 0Ch\nlea rcx, unk_3004\nmov [rbp+0], rax\nmov rdi, rax\nxor eax, eax\nmov esi, 2\nmov r14d, 1\ncall ___sprintf_chk\njmp loc_16E1\nloc_1E98:\nxor r14d, r14d\njmp loc_16E1\nloc_1EA0:\nsub ecx, 61h ; 'a'\nmov esi, ecx\nshr esi, 1Fh\nadd ecx, esi\nand ecx, 1\nsub ecx, esi\ncmp ecx, 1\nsetz cl\nmovzx ecx, cl\nadd r14d, ecx\njmp loc_1D96\nloc_1EC0:\nsub ecx, 61h ; 'a'\nmov esi, ecx\nshr esi, 1Fh\nadd ecx, esi\nand ecx, 1\nsub ecx, esi\ncmp ecx, 1\nsetz cl\nmovzx ecx, cl\nadd r14d, ecx\njmp loc_1DB8\nloc_1EE0:\nsub ecx, 61h ; 'a'\nmov esi, ecx\nshr esi, 1Fh\nadd ecx, esi\nand ecx, 1\nsub ecx, esi\ncmp ecx, 1\nsetz cl\nmovzx ecx, cl\nadd r14d, ecx\njmp loc_1DDA\nloc_1F00:\nsub ecx, 61h ; 'a'\nmov esi, ecx\nshr esi, 1Fh\nadd ecx, esi\nand ecx, 1\nsub ecx, esi\ncmp ecx, 1\nsetz cl\nmovzx ecx, cl\nadd r14d, ecx\njmp loc_1DF8\nloc_1F20:\nsub ecx, 61h ; 'a'\nmov esi, ecx\nshr esi, 1Fh\nadd ecx, esi\nand ecx, 1\nsub ecx, esi\ncmp ecx, 1\nsetz cl\nmovzx ecx, cl\nadd r14d, ecx\njmp loc_1E16\nloc_1F40:\npxor xmm3, xmm3\nxor esi, esi\nxor r14d, r14d\nxor edx, edx\njmp loc_1AC7\nloc_1F50:\ncall ___stack_chk_fail", + "ida_pseudo": "_QWORD *__fastcall func0(__m128i *s, int *a2)\n{\n char *v3; // rbx\n int v4; // r13d\n _QWORD *v5; // rbp\n int v6; // r14d\n int v7; // edx\n __int64 v8; // r15\n char *v9; // r13\n char *v10; // rdx\n __int64 v11; // rax\n unsigned __int64 v12; // rax\n __int64 v13; // rcx\n unsigned int v15; // r14d\n const unsigned __int16 *v16; // rax\n const __m128i *v17; // rcx\n __m128i v18; // xmm3\n __m128i si128; // xmm7\n __m128i v20; // xmm6\n __m128i v21; // xmm5\n __m128i v22; // xmm0\n __m128i v23; // xmm14\n __m128i v24; // xmm1\n __m128i v25; // xmm9\n __m128i v26; // xmm13\n __m128i v27; // xmm0\n __m128i v28; // xmm1\n __m128i v29; // xmm10\n __m128i v30; // xmm2\n __m128i v31; // xmm13\n __m128i v32; // xmm2\n __m128i v33; // xmm1\n __m128i v34; // xmm10\n __m128i v35; // xmm13\n __m128i v36; // xmm0\n __m128i v37; // xmm1\n __m128i v38; // xmm15\n __m128i v39; // xmm12\n __m128i v40; // xmm10\n __m128i v41; // xmm2\n __m128i v42; // xmm11\n __m128i v43; // xmm0\n __m128i v44; // xmm13\n __m128i v45; // xmm2\n __m128i v46; // xmm13\n __m128i v47; // xmm0\n __m128i v48; // xmm2\n __m128i v49; // xmm1\n __m128i v50; // xmm10\n __m128i v51; // xmm0\n __m128i v52; // xmm10\n __m128i v53; // xmm1\n __m128i v54; // xmm0\n __m128i v55; // xmm9\n __m128i v56; // xmm2\n __m128i v57; // xmm1\n __int64 v58; // rsi\n __m128i v59; // xmm0\n unsigned int v60; // edx\n __m128i v61; // xmm3\n int v62; // ecx\n __int64 v63; // rsi\n __m128i v64; // xmm7\n __m128i v65; // xmm8\n __m128i v66; // xmm6\n __m128i v67; // xmm2\n __m128i v68; // xmm6\n __m128i v69; // xmm1\n __m128i v70; // xmm0\n __m128i v71; // xmm6\n __m128i v72; // xmm2\n __m128i v73; // xmm0\n __m128i v74; // xmm2\n __m128i v75; // xmm8\n __m128i v76; // xmm12\n __m128i v77; // xmm11\n __m128i v78; // xmm10\n __m128i v79; // xmm9\n __m128i v80; // xmm1\n __m128i v81; // xmm1\n __m128i v82; // xmm0\n __m128i v83; // xmm0\n __m128i v84; // xmm1\n __m128i v85; // xmm2\n __m128i v86; // xmm3\n __int64 v87; // rsi\n __int64 v88; // rsi\n __int64 v89; // rsi\n __int64 v90; // rsi\n __int64 v91; // rsi\n __int64 v92; // rsi\n int v93; // edx\n __int64 v94; // rcx\n void *v95; // rax\n __int64 v96; // r8\n __int64 v97; // r9\n __m128i v98; // [rsp+0h] [rbp-198h]\n __m128i v99; // [rsp+10h] [rbp-188h]\n __m128i v100; // [rsp+20h] [rbp-178h]\n __m128i v101; // [rsp+30h] [rbp-168h]\n __m128i v102; // [rsp+40h] [rbp-158h]\n __m128i v103; // [rsp+50h] [rbp-148h]\n __m128i v104; // [rsp+60h] [rbp-138h]\n __m128i v105; // [rsp+70h] [rbp-128h]\n __m128i v106; // [rsp+80h] [rbp-118h]\n __m128i v107; // [rsp+90h] [rbp-108h]\n __m128i v108; // [rsp+A0h] [rbp-F8h]\n __m128i v109; // [rsp+B0h] [rbp-E8h]\n __m128i v110; // [rsp+C0h] [rbp-D8h]\n __m128i v111; // [rsp+D0h] [rbp-C8h]\n __m128i v112; // [rsp+E0h] [rbp-B8h]\n char sa[16]; // [rsp+F0h] [rbp-A8h] BYREF\n __int128 v114; // [rsp+100h] [rbp-98h]\n __int128 v115; // [rsp+110h] [rbp-88h]\n __int128 v116; // [rsp+120h] [rbp-78h]\n __int128 v117; // [rsp+130h] [rbp-68h]\n _QWORD v118[3]; // [rsp+140h] [rbp-58h] BYREF\n unsigned __int64 v119; // [rsp+158h] [rbp-40h]\n\n v3 = (char *)s;\n v119 = __readfsqword(0x28u);\n memset(v118, 0, 21);\n v4 = strlen(s->m128i_i8);\n *(_OWORD *)sa = 0LL;\n v114 = 0LL;\n v115 = 0LL;\n v116 = 0LL;\n v117 = 0LL;\n if ( !strchr(s->m128i_i8, 32) && !strchr(s->m128i_i8, 44) )\n {\n v15 = 0;\n if ( v4 > 0 )\n {\n v16 = *__ctype_b_loc();\n if ( (unsigned int)(v4 - 1) <= 0xE )\n {\n v61 = 0LL;\n v58 = 0LL;\n v15 = 0;\n v60 = 0;\n goto LABEL_17;\n }\n v17 = s;\n v18 = 0LL;\n si128 = _mm_load_si128((const __m128i *)&xmmword_30C0);\n v20 = _mm_load_si128((const __m128i *)&xmmword_30D0);\n v21 = _mm_load_si128((const __m128i *)&xmmword_30E0);\n do\n {\n v22 = _mm_loadu_si128(v17++);\n v112 = v22;\n v111 = v22;\n v110 = v22;\n v109 = v22;\n v108 = v22;\n v107 = v22;\n v106 = v22;\n v105 = v22;\n v104 = v22;\n v103 = v22;\n v102 = v22;\n v101 = v22;\n v99 = v22;\n v100 = v22;\n v98 = v22;\n v23 = _mm_cmpeq_epi16(\n _mm_cmpeq_epi16(\n _mm_and_si128(\n _mm_unpacklo_epi64(\n _mm_unpacklo_epi32(\n _mm_insert_epi16(_mm_cvtsi32_si128(v16[(char)_mm_cvtsi128_si32(v22)]), v16[v22.m128i_i8[1]], 1),\n _mm_insert_epi16(_mm_cvtsi32_si128(v16[v22.m128i_i8[2]]), v16[v22.m128i_i8[3]], 1)),\n _mm_unpacklo_epi32(\n _mm_insert_epi16(_mm_cvtsi32_si128(v16[v22.m128i_i8[4]]), v16[v22.m128i_i8[5]], 1),\n _mm_insert_epi16(_mm_cvtsi32_si128(v16[v22.m128i_i8[6]]), v16[v22.m128i_i8[7]], 1))),\n si128),\n (__m128i)0LL),\n (__m128i)0LL);\n v24 = _mm_cmpgt_epi8((__m128i)0LL, v22);\n v25 = _mm_cmpeq_epi16(\n _mm_and_si128(\n _mm_unpacklo_epi64(\n _mm_unpacklo_epi32(\n _mm_insert_epi16(_mm_cvtsi32_si128(v16[v22.m128i_i8[8]]), v16[v22.m128i_i8[9]], 1),\n _mm_insert_epi16(_mm_cvtsi32_si128(v16[v22.m128i_i8[10]]), v16[v22.m128i_i8[11]], 1)),\n _mm_unpacklo_epi32(\n _mm_insert_epi16(_mm_cvtsi32_si128(v16[v22.m128i_i8[12]]), v16[v22.m128i_i8[13]], 1),\n _mm_insert_epi16(_mm_cvtsi32_si128(v16[v22.m128i_i8[14]]), v16[v22.m128i_i8[15]], 1))),\n si128),\n (__m128i)0LL);\n v26 = _mm_unpacklo_epi8(v22, v24);\n v27 = _mm_unpackhi_epi8(v22, v24);\n v28 = _mm_cmpgt_epi16((__m128i)0LL, v26);\n v29 = _mm_cmpgt_epi16((__m128i)0LL, v27);\n v30 = _mm_unpacklo_epi16(v26, v28);\n v31 = _mm_unpackhi_epi16(v26, v28);\n v32 = _mm_add_epi32(v30, v20);\n v33 = _mm_unpacklo_epi16(v27, v29);\n v34 = _mm_unpackhi_epi16(v27, v29);\n v35 = _mm_add_epi32(v31, v20);\n v36 = _mm_srli_epi32(v32, 0x1Fu);\n v37 = _mm_add_epi32(v33, v20);\n v38 = _mm_srli_epi32(v35, 0x1Fu);\n v39 = _mm_srli_epi32(v37, 0x1Fu);\n v40 = _mm_add_epi32(v34, v20);\n v41 = _mm_sub_epi32(_mm_and_si128(_mm_add_epi32(v32, v36), v21), v36);\n v42 = _mm_srli_epi32(v40, 0x1Fu);\n v43 = _mm_cmpeq_epi32(_mm_sub_epi32(_mm_and_si128(_mm_add_epi32(v35, v38), v21), v38), v21);\n v44 = _mm_cmpeq_epi32(v41, v21);\n v45 = _mm_unpacklo_epi16(v44, v43);\n v46 = _mm_unpackhi_epi16(v44, v43);\n v47 = _mm_add_epi32(v37, v39);\n v48 = _mm_and_si128(_mm_unpacklo_epi16(_mm_unpacklo_epi16(v45, v46), _mm_unpackhi_epi16(v45, v46)), v23);\n v49 = _mm_cmpeq_epi32(_mm_sub_epi32(_mm_and_si128(_mm_add_epi32(v40, v42), v21), v42), v21);\n v50 = _mm_cmpeq_epi32(_mm_sub_epi32(_mm_and_si128(v47, v21), v39), v21);\n v51 = _mm_unpacklo_epi16(v50, v49);\n v52 = _mm_unpackhi_epi16(v50, v49);\n v53 = _mm_cmpgt_epi16((__m128i)0LL, v48);\n v54 = _mm_and_si128(\n _mm_unpacklo_epi16(_mm_unpacklo_epi16(v51, v52), _mm_unpackhi_epi16(v51, v52)),\n _mm_cmpeq_epi16(v25, (__m128i)0LL));\n v55 = _mm_unpacklo_epi16(v48, v53);\n v56 = _mm_unpackhi_epi16(v48, v53);\n v57 = _mm_cmpgt_epi16((__m128i)0LL, v54);\n v18 = _mm_sub_epi32(\n _mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(v18, v55), v56), _mm_unpacklo_epi16(v54, v57)),\n _mm_unpackhi_epi16(v54, v57));\n }\n while ( &s[(unsigned int)v4 >> 4] != v17 );\n v58 = v4 & 0xFFFFFFF0;\n v59 = _mm_add_epi32(_mm_srli_si128(v18, 8), v18);\n v60 = v4 & 0xFFFFFFF0;\n v61 = v59;\n v15 = _mm_cvtsi128_si32(_mm_add_epi32(v59, _mm_srli_si128(v59, 4)));\n if ( (v4 & 0xF) != 0 )\n {\nLABEL_17:\n v62 = v4 - v58;\n if ( (unsigned int)(v4 - v58 - 1) <= 6 )\n goto LABEL_19;\n v63 = *(__int64 *)((char *)s->m128i_i64 + v58);\n v64 = _mm_loadl_epi64((const __m128i *)&xmmword_30C0);\n v65 = _mm_loadl_epi64((const __m128i *)&xmmword_30D0);\n v66 = _mm_unpacklo_epi8(\n (__m128i)(unsigned __int64)v63,\n _mm_cmpgt_epi8((__m128i)0LL, (__m128i)(unsigned __int64)v63));\n v67 = _mm_shuffle_epi32(v66, 78);\n v68 = _mm_unpacklo_epi16(v66, _mm_cmpgt_epi16((__m128i)0LL, v66));\n v69 = _mm_add_epi32(v68, v65);\n v70 = _mm_unpacklo_epi16(v67, _mm_cmpgt_epi16((__m128i)0LL, v67));\n v71 = _mm_add_epi32(_mm_shuffle_epi32(v68, 78), v65);\n v72 = _mm_shuffle_epi32(v70, 78);\n v73 = _mm_add_epi32(v70, v65);\n v74 = _mm_add_epi32(v72, v65);\n v75 = _mm_loadl_epi64((const __m128i *)&xmmword_30E0);\n v76 = _mm_and_si128(_mm_cmpgt_epi32((__m128i)0LL, v69), v75);\n v77 = _mm_and_si128(_mm_cmpgt_epi32((__m128i)0LL, v71), v75);\n v78 = _mm_and_si128(_mm_cmpgt_epi32((__m128i)0LL, v73), v75);\n v79 = _mm_and_si128(_mm_cmpgt_epi32((__m128i)0LL, v74), v75);\n v80 = _mm_unpacklo_epi16(\n _mm_cmpeq_epi32(_mm_sub_epi32(_mm_and_si128(_mm_add_epi32(v69, v76), v75), v76), v75),\n _mm_cmpeq_epi32(_mm_sub_epi32(_mm_and_si128(_mm_add_epi32(v71, v77), v75), v77), v75));\n v81 = _mm_and_si128(\n _mm_unpacklo_epi16(v80, _mm_shuffle_epi32(v80, 78)),\n _mm_cmpeq_epi16(\n _mm_cmpeq_epi16(\n _mm_and_si128(\n (__m128i)(v16[(char)v63] | ((v16[SBYTE1(v63)] | ((v16[(char)((_DWORD)v63 << 8 >> 24)] | ((unsigned __int64)v16[SBYTE3(v63)] << 16)) << 16)) << 16)),\n v64),\n (__m128i)0LL),\n (__m128i)0LL));\n v82 = _mm_unpacklo_epi16(\n _mm_cmpeq_epi32(_mm_sub_epi32(_mm_and_si128(_mm_add_epi32(v73, v78), v75), v78), v75),\n _mm_cmpeq_epi32(_mm_sub_epi32(_mm_and_si128(_mm_add_epi32(v74, v79), v75), v79), v75));\n v83 = _mm_and_si128(\n _mm_unpacklo_epi16(v82, _mm_shuffle_epi32(v82, 78)),\n _mm_cmpeq_epi16(\n _mm_cmpeq_epi16(\n _mm_and_si128(\n v64,\n (__m128i)(v16[v63 << 24 >> 56] | ((v16[v63 << 16 >> 56] | ((v16[v63 << 8 >> 56] | ((unsigned __int64)v16[v63 >> 56] << 16)) << 16)) << 16))),\n (__m128i)0LL),\n (__m128i)0LL));\n v84 = _mm_unpacklo_epi16(v81, _mm_cmpgt_epi16((__m128i)0LL, v81));\n v85 = _mm_unpacklo_epi16(v83, _mm_cmpgt_epi16((__m128i)0LL, v83));\n v86 = _mm_sub_epi32(\n _mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(v61, v84), _mm_shuffle_epi32(v84, 78)), v85),\n _mm_shuffle_epi32(v85, 78));\n v15 = _mm_cvtsi128_si32(_mm_shuffle_epi32(v86, 229)) + _mm_cvtsi128_si32(v86);\n v60 += v62 & 0xFFFFFFF8;\n if ( (v62 & 7) != 0 )\n {\nLABEL_19:\n v87 = s->m128i_i8[v60];\n if ( (v16[v87] & 0x200) != 0 )\n v15 += ((int)v87 - 97) % 2 == 1;\n if ( (int)(v60 + 1) < v4 )\n {\n v88 = s->m128i_i8[v60 + 1];\n if ( (v16[v88] & 0x200) != 0 )\n v15 += ((int)v88 - 97) % 2 == 1;\n if ( v4 > (int)(v60 + 2) )\n {\n v89 = s->m128i_i8[v60 + 2];\n if ( (v16[v89] & 0x200) != 0 )\n v15 += ((int)v89 - 97) % 2 == 1;\n if ( v4 > (int)(v60 + 3) )\n {\n v90 = s->m128i_i8[v60 + 3];\n if ( (v16[v90] & 0x200) != 0 )\n v15 += ((int)v90 - 97) % 2 == 1;\n if ( v4 > (int)(v60 + 4) )\n {\n v91 = s->m128i_i8[v60 + 4];\n if ( (v16[v91] & 0x200) != 0 )\n v15 += ((int)v91 - 97) % 2 == 1;\n if ( v4 > (int)(v60 + 5) )\n {\n v92 = s->m128i_i8[v60 + 5];\n if ( (v16[v92] & 0x200) != 0 )\n v15 += ((int)v92 - 97) % 2 == 1;\n v93 = v60 + 6;\n if ( v4 > v93 )\n {\n v94 = s->m128i_i8[v93];\n if ( (v16[v94] & 0x200) != 0 )\n v15 += ((char)v94 - 97) % 2 == 1;\n }\n }\n }\n }\n }\n }\n }\n }\n }\n v5 = malloc(8uLL);\n v95 = malloc(0xCuLL);\n v96 = v15;\n *v5 = v95;\n v6 = 1;\n __sprintf_chk(\n v95,\n 2LL,\n 12LL,\n &unk_3004,\n v96,\n v97,\n v98.m128i_i64[0],\n v98.m128i_i64[1],\n v99.m128i_i64[0],\n v99.m128i_i64[1],\n v100.m128i_i64[0],\n v100.m128i_i64[1],\n v101.m128i_i64[0],\n v101.m128i_i64[1],\n v102.m128i_i64[0],\n v102.m128i_i64[1],\n v103.m128i_i64[0],\n v103.m128i_i64[1],\n v104.m128i_i64[0],\n v104.m128i_i64[1],\n v105.m128i_i64[0],\n v105.m128i_i64[1],\n v106.m128i_i64[0],\n v106.m128i_i64[1],\n v107.m128i_i64[0],\n v107.m128i_i64[1],\n v108.m128i_i64[0],\n v108.m128i_i64[1],\n v109.m128i_i64[0],\n v109.m128i_i64[1],\n v110.m128i_i64[0],\n v110.m128i_i64[1],\n v111.m128i_i64[0],\n v111.m128i_i64[1],\n v112.m128i_i64[0],\n v112.m128i_i64[1],\n *(_QWORD *)sa,\n *(_QWORD *)&sa[8],\n v114,\n *((_QWORD *)&v114 + 1),\n v115,\n *((_QWORD *)&v115 + 1),\n v116,\n *((_QWORD *)&v116 + 1),\n v117,\n *((_QWORD *)&v117 + 1),\n v118[0],\n v118[1],\n v118[2],\n v119);\n goto LABEL_10;\n }\n v5 = malloc(8LL * (v4 + 1));\n if ( v4 < 0 )\n {\n v6 = 0;\n }\n else\n {\n v6 = 0;\n v7 = 0;\n v8 = 0x100100000001LL;\n v9 = &s->m128i_i8[v4 + 1];\n do\n {\n while ( 1 )\n {\n v12 = (unsigned __int8)*v3;\n if ( (unsigned __int8)v12 <= 0x2Cu )\n {\n if ( _bittest64(&v8, v12) )\n break;\n }\n v13 = v7;\n ++v3;\n ++v7;\n sa[v13] = v12;\n if ( v9 == v3 )\n goto LABEL_10;\n }\n if ( v7 > 0 )\n {\n sa[v7] = 0;\n v10 = strdup(sa);\n v11 = v6++;\n v5[v11] = v10;\n v7 = 0;\n }\n ++v3;\n }\n while ( v9 != v3 );\n }\nLABEL_10:\n *a2 = v6;\n return v5;\n}", + "ida_strip_asm": "sub_15C0:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12, rsi\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 168h\nmov rax, fs:28h\nmov [rsp+198h+var_40], rax\nxor eax, eax\ncall _strlen\npxor xmm0, xmm0\nmov esi, 20h ; ' '; c\nmov rdi, rbx; s\nmovaps [rsp+198h+var_58], xmm0\nmov r13, rax\nmov qword ptr [rsp+198h+var_58+0Dh], 0\nmovaps xmmword ptr [rsp+198h+s], xmm0\nmovaps [rsp+198h+var_98], xmm0\nmovaps [rsp+198h+var_88], xmm0\nmovaps [rsp+198h+var_78], xmm0\nmovaps [rsp+198h+var_68], xmm0\ncall _strchr\ntest rax, rax\njz loc_1718\nloc_164C:\nlea edi, [r13+1]\nmovsxd rdi, edi\nshl rdi, 3; size\ncall _malloc\nmov rbp, rax\ntest r13d, r13d\njs loc_1E98\nmov r13d, r13d\nxor r14d, r14d\nxor edx, edx\nmov r15, 100100000001h\nlea r13, [rbx+r13+1]\njmp short loc_16C4\nloc_1688:\nbt r15, rax\njnb short loc_16CB\ntest edx, edx\njle short loc_16BB\nmovsxd rdx, edx\nlea rdi, [rsp+198h+s]; s\nmov [rsp+rdx+198h+s], 0\ncall _strdup\nmov rdx, rax\nmovsxd rax, r14d\nadd r14d, 1\nmov [rbp+rax*8+0], rdx\nxor edx, edx\nloc_16BB:\nadd rbx, 1\ncmp r13, rbx\njz short loc_16E1\nloc_16C4:\nmovzx eax, byte ptr [rbx]\ncmp al, 2Ch ; ','\njbe short loc_1688\nloc_16CB:\nmovsxd rcx, edx\nadd rbx, 1\nadd edx, 1\nmov [rsp+rcx+198h+s], al\ncmp r13, rbx\njnz short loc_16C4\nloc_16E1:\nmov [r12], r14d\nmov rax, [rsp+198h+var_40]\nsub rax, fs:28h\njnz loc_1F50\nadd rsp, 168h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1718:\nmov esi, 2Ch ; ','; c\nmov rdi, rbx; s\ncall _strchr\ntest rax, rax\njnz loc_164C\nxor r14d, r14d\ntest r13d, r13d\njle loc_1E50\ncall ___ctype_b_loc\nlea edx, [r13-1]\nmov rax, [rax]\ncmp edx, 0Eh\njbe loc_1F40\nmov esi, r13d\nmov rcx, rbx\npxor xmm3, xmm3\nmovdqa xmm7, cs:xmmword_30C0\nshr esi, 4\npxor xmm8, xmm8\npxor xmm4, xmm4\nmovdqa xmm6, cs:xmmword_30D0\nshl rsi, 4\nmovdqa xmm5, cs:xmmword_30E0\nadd rsi, rbx\nnop dword ptr [rax+00h]\nloc_1788:\nmovdqu xmm0, xmmword ptr [rcx]\nadd rcx, 10h\nmovd edx, xmm0\nmovaps [rsp+198h+var_B8], xmm0\nmovsx r14, byte ptr [rsp+198h+var_B8+1]\nmovdqa xmm13, xmm0\nmovsx rdx, dl\nmovaps [rsp+198h+var_C8], xmm0\nmovsx rbp, byte ptr [rsp+198h+var_C8+2]\nmovaps [rsp+198h+var_D8], xmm0\nmovsx r11, byte ptr [rsp+198h+var_D8+3]\nmovaps [rsp+198h+var_E8], xmm0\nmovsx r10, byte ptr [rsp+198h+var_E8+4]\nmovaps [rsp+198h+var_F8], xmm0\nmovsx r9, byte ptr [rsp+198h+var_F8+5]\nmovaps [rsp+198h+var_108], xmm0\nmovsx r8, byte ptr [rsp+198h+var_108+6]\nmovaps [rsp+198h+var_118], xmm0\nmovzx edx, word ptr [rax+rdx*2]\nmovsx rdi, byte ptr [rsp+198h+var_118+7]\nmovd xmm14, edx\nmovzx edx, word ptr [rax+rbp*2]\npinsrw xmm14, word ptr [rax+r14*2], 1\nmovd xmm9, edx\nmovzx edx, word ptr [rax+r10*2]\npinsrw xmm9, word ptr [rax+r11*2], 1\nmovd xmm1, edx\nmovzx edx, word ptr [rax+r8*2]\npinsrw xmm1, word ptr [rax+r9*2], 1\npunpckldq xmm14, xmm9\nmovd xmm2, edx\npinsrw xmm2, word ptr [rax+rdi*2], 1\nmovaps [rsp+198h+var_128], xmm0\nmovsx r14, byte ptr [rsp+198h+var_128+8]\nmovaps [rsp+198h+var_138], xmm0\nmovsx rbp, byte ptr [rsp+198h+var_138+9]\nmovaps [rsp+198h+var_148], xmm0\nmovsx r11, byte ptr [rsp+198h+var_148+0Ah]\npunpckldq xmm1, xmm2\nmovaps [rsp+198h+var_158], xmm0\nmovsx r10, byte ptr [rsp+198h+var_158+0Bh]\npunpcklqdq xmm14, xmm1\nmovaps [rsp+198h+var_168], xmm0\nmovsx r9, byte ptr [rsp+198h+var_168+0Ch]\npand xmm14, xmm7\nmovaps [rsp+198h+var_188], xmm0\nmovsx rdi, byte ptr [rsp+198h+var_188+0Eh]\npcmpeqw xmm14, xmm4\nmovaps [rsp+198h+var_178], xmm0\nmovsx r8, byte ptr [rsp+198h+var_178+0Dh]\nmovaps [rsp+198h+var_198], xmm0\nmovsx rdx, byte ptr [rsp+198h+var_198+0Fh]\nmovzx r14d, word ptr [rax+r14*2]\nmovzx r11d, word ptr [rax+r11*2]\nmovzx r9d, word ptr [rax+r9*2]\npcmpeqw xmm14, xmm4\nmovzx edi, word ptr [rax+rdi*2]\nmovd xmm9, r14d\npinsrw xmm9, word ptr [rax+rbp*2], 1\nmovd xmm10, r11d\nmovd xmm1, r9d\npinsrw xmm10, word ptr [rax+r10*2], 1\npinsrw xmm1, word ptr [rax+r8*2], 1\nmovd xmm2, edi\npinsrw xmm2, word ptr [rax+rdx*2], 1\npunpckldq xmm9, xmm10\nmovdqa xmm10, xmm4\npunpckldq xmm1, xmm2\npunpcklqdq xmm9, xmm1\nmovdqa xmm1, xmm8\npcmpgtb xmm1, xmm0\npand xmm9, xmm7\npcmpeqw xmm9, xmm4\npunpcklbw xmm13, xmm1\npunpckhbw xmm0, xmm1\nmovdqa xmm1, xmm4\npcmpgtw xmm1, xmm13\npcmpgtw xmm10, xmm0\nmovdqa xmm2, xmm13\npcmpeqw xmm9, xmm4\npunpcklwd xmm2, xmm1\npunpckhwd xmm13, xmm1\nmovdqa xmm1, xmm0\npaddd xmm2, xmm6\npunpckhwd xmm0, xmm10\npunpcklwd xmm1, xmm10\nmovdqa xmm10, xmm0\nmovdqa xmm0, xmm2\npaddd xmm13, xmm6\npsrld xmm0, 1Fh\nmovdqa xmm15, xmm13\npaddd xmm1, xmm6\npaddd xmm2, xmm0\npsrld xmm15, 1Fh\nmovdqa xmm12, xmm1\npand xmm2, xmm5\npsrld xmm12, 1Fh\npaddd xmm10, xmm6\npsubd xmm2, xmm0\nmovdqa xmm0, xmm13\nmovdqa xmm11, xmm10\npaddd xmm0, xmm15\npcmpeqd xmm2, xmm5\npaddd xmm1, xmm12\npand xmm0, xmm5\npsrld xmm11, 1Fh\npsubd xmm0, xmm15\npcmpeqd xmm0, xmm5\nmovdqa xmm13, xmm2\npunpcklwd xmm2, xmm0\npunpckhwd xmm13, xmm0\nmovdqa xmm0, xmm2\npunpcklwd xmm2, xmm13\npunpckhwd xmm0, xmm13\npunpcklwd xmm2, xmm0\nmovdqa xmm0, xmm1\nmovdqa xmm1, xmm10\npaddd xmm1, xmm11\npand xmm0, xmm5\npand xmm2, xmm14\npand xmm1, xmm5\npsubd xmm0, xmm12\npsubd xmm1, xmm11\npcmpeqd xmm0, xmm5\npcmpeqd xmm1, xmm5\nmovdqa xmm10, xmm0\npunpcklwd xmm0, xmm1\npunpckhwd xmm10, xmm1\nmovdqa xmm1, xmm0\npunpcklwd xmm0, xmm10\npunpckhwd xmm1, xmm10\npunpcklwd xmm0, xmm1\nmovdqa xmm1, xmm4\npcmpgtw xmm1, xmm2\npand xmm0, xmm9\nmovdqa xmm9, xmm2\npunpcklwd xmm9, xmm1\npunpckhwd xmm2, xmm1\nmovdqa xmm1, xmm4\npcmpgtw xmm1, xmm0\npsubd xmm3, xmm9\npsubd xmm3, xmm2\nmovdqa xmm2, xmm0\npunpcklwd xmm2, xmm1\npunpckhwd xmm0, xmm1\npsubd xmm3, xmm2\npsubd xmm3, xmm0\ncmp rsi, rcx\njnz loc_1788\nmovdqa xmm0, xmm3\nmov esi, r13d\npsrldq xmm0, 8\nand esi, 0FFFFFFF0h\npaddd xmm0, xmm3\nmov edx, esi\nmovdqa xmm1, xmm0\npsrldq xmm1, 4\npaddd xmm0, xmm1\nmovdqa xmm1, xmm3\npsrldq xmm3, 8\npaddd xmm3, xmm1\nmovd r14d, xmm0\ntest r13b, 0Fh\njz loc_1E50\nloc_1AC7:\nmov ecx, r13d\nsub ecx, esi\nlea edi, [rcx-1]\ncmp edi, 6\njbe loc_1D47\nmov rsi, [rbx+rsi]\npxor xmm0, xmm0\npxor xmm5, xmm5\nmovq xmm7, qword ptr cs:xmmword_30C0\nmovq xmm8, qword ptr cs:xmmword_30D0\nmovdqa xmm9, xmm5\nmov rdi, rsi\nmov r10d, esi\nmov r9d, esi\nmovsx r8, sil\nshl r10d, 8\nsar edi, 18h\nmovzx r8d, word ptr [rax+r8*2]\nmovq xmm2, rsi\nsar r10d, 18h\nmovsx rdi, dil\nsar r9w, 8\nmovzx edi, word ptr [rax+rdi*2]\nmovsx r10, r10b\nmovsx r9, r9b\nmovzx r10d, word ptr [rax+r10*2]\nmovzx r9d, word ptr [rax+r9*2]\nshl rdi, 10h\nor rdi, r10\nmov r10, rsi\nshl rdi, 10h\nshl r10, 8\nor rdi, r9\nsar r10, 38h\nmov r9, rsi\nshl rdi, 10h\nshl r9, 10h\nmovzx r10d, word ptr [rax+r10*2]\nor rdi, r8\nsar r9, 38h\nmov r8, rsi\nmovq xmm4, rdi\nmov rdi, rsi\nshl r8, 18h\nmovzx r9d, word ptr [rax+r9*2]\nsar rdi, 38h\nsar r8, 38h\npand xmm4, xmm7\nmovzx edi, word ptr [rax+rdi*2]\nmovzx r8d, word ptr [rax+r8*2]\npcmpeqw xmm4, xmm5\nshl rdi, 10h\nor rdi, r10\npcmpeqw xmm4, xmm5\nshl rdi, 10h\nor rdi, r9\nshl rdi, 10h\nor rdi, r8\nmovq xmm6, rdi\npand xmm7, xmm6\nmovq xmm6, rsi\npcmpgtb xmm0, xmm6\npcmpeqw xmm7, xmm5\npunpcklbw xmm6, xmm0\npcmpeqw xmm7, xmm5\npunpcklbw xmm2, xmm0\nmovdqa xmm0, xmm5\npshufd xmm2, xmm2, 4Eh ; 'N'\nmovdqa xmm1, xmm6\npcmpgtw xmm0, xmm6\npcmpgtw xmm9, xmm2\npunpcklwd xmm1, xmm0\npunpcklwd xmm6, xmm0\nmovdqa xmm0, xmm2\npaddd xmm1, xmm8\npshufd xmm6, xmm6, 4Eh ; 'N'\npunpcklwd xmm0, xmm9\npaddd xmm6, xmm8\npunpcklwd xmm2, xmm9\npxor xmm9, xmm9\nmovdqa xmm12, xmm9\nmovdqa xmm11, xmm9\npshufd xmm2, xmm2, 4Eh ; 'N'\npcmpgtd xmm12, xmm1\npaddd xmm0, xmm8\npaddd xmm2, xmm8\nmovq xmm8, qword ptr cs:xmmword_30E0\npcmpgtd xmm11, xmm6\nmovdqa xmm10, xmm9\npcmpgtd xmm10, xmm0\npcmpgtd xmm9, xmm2\npand xmm12, xmm8\npand xmm11, xmm8\npaddd xmm1, xmm12\npaddd xmm6, xmm11\npand xmm10, xmm8\npand xmm9, xmm8\npand xmm1, xmm8\npaddd xmm0, xmm10\npaddd xmm2, xmm9\npsubd xmm1, xmm12\npand xmm6, xmm8\npsubd xmm6, xmm11\npand xmm0, xmm8\npand xmm2, xmm8\npcmpeqd xmm1, xmm8\npsubd xmm0, xmm10\npsubd xmm2, xmm9\npcmpeqd xmm6, xmm8\npcmpeqd xmm0, xmm8\npcmpeqd xmm2, xmm8\nmovdqa xmm11, xmm1\npunpcklwd xmm11, xmm6\npunpcklwd xmm1, xmm6\npshufd xmm11, xmm11, 4Eh ; 'N'\npunpcklwd xmm1, xmm11\npand xmm1, xmm4\nmovdqa xmm4, xmm0\npunpcklwd xmm0, xmm2\npunpcklwd xmm4, xmm2\nmovdqa xmm2, xmm5\npcmpgtw xmm2, xmm1\npshufd xmm4, xmm4, 4Eh ; 'N'\npunpcklwd xmm0, xmm4\nmovdqa xmm4, xmm1\npand xmm0, xmm7\npunpcklwd xmm4, xmm2\npcmpgtw xmm5, xmm0\npunpcklwd xmm1, xmm2\npsubd xmm3, xmm4\npshufd xmm1, xmm1, 4Eh ; 'N'\nmovdqa xmm2, xmm0\npunpcklwd xmm2, xmm5\npunpcklwd xmm0, xmm5\npsubd xmm3, xmm1\npshufd xmm0, xmm0, 4Eh ; 'N'\npsubd xmm3, xmm2\npsubd xmm3, xmm0\nmovd r14d, xmm3\npshufd xmm7, xmm3, 0E5h\nmovd esi, xmm7\nadd r14d, esi\nmov esi, ecx\nand esi, 0FFFFFFF8h\nadd edx, esi\nand ecx, 7\njz loc_1E50\nloc_1D47:\nmovsxd rcx, edx\nmovsx rsi, byte ptr [rbx+rcx]\nmov rcx, rsi\ntest byte ptr [rax+rsi*2+1], 2\njz short loc_1D74\nsub ecx, 61h ; 'a'\nmov esi, ecx\nshr esi, 1Fh\nadd ecx, esi\nand ecx, 1\nsub ecx, esi\ncmp ecx, 1\nsetz cl\nmovzx ecx, cl\nadd r14d, ecx\nloc_1D74:\nlea ecx, [rdx+1]\ncmp ecx, r13d\njge loc_1E50\nmovsxd rcx, ecx\nmovsx rsi, byte ptr [rbx+rcx]\nmov rcx, rsi\ntest byte ptr [rax+rsi*2+1], 2\njnz loc_1EA0\nloc_1D96:\nlea ecx, [rdx+2]\ncmp r13d, ecx\njle loc_1E50\nmovsxd rcx, ecx\nmovsx rsi, byte ptr [rbx+rcx]\nmov rcx, rsi\ntest byte ptr [rax+rsi*2+1], 2\njnz loc_1EC0\nloc_1DB8:\nlea ecx, [rdx+3]\ncmp r13d, ecx\njle loc_1E50\nmovsxd rcx, ecx\nmovsx rsi, byte ptr [rbx+rcx]\nmov rcx, rsi\ntest byte ptr [rax+rsi*2+1], 2\njnz loc_1EE0\nloc_1DDA:\nlea ecx, [rdx+4]\ncmp r13d, ecx\njle short loc_1E50\nmovsxd rcx, ecx\nmovsx rsi, byte ptr [rbx+rcx]\nmov rcx, rsi\ntest byte ptr [rax+rsi*2+1], 2\njnz loc_1F00\nloc_1DF8:\nlea ecx, [rdx+5]\ncmp r13d, ecx\njle short loc_1E50\nmovsxd rcx, ecx\nmovsx rsi, byte ptr [rbx+rcx]\nmov rcx, rsi\ntest byte ptr [rax+rsi*2+1], 2\njnz loc_1F20\nloc_1E16:\nadd edx, 6\ncmp r13d, edx\njle short loc_1E50\nmovsxd rdx, edx\nmovsx rcx, byte ptr [rbx+rdx]\ntest byte ptr [rax+rcx*2+1], 2\njz short loc_1E50\nmovsx eax, cl\nsub eax, 61h ; 'a'\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nand eax, 1\nsub eax, edx\ncmp eax, 1\nsetz al\nmovzx eax, al\nadd r14d, eax\nnop dword ptr [rax+rax+00h]\nloc_1E50:\nmov edi, 8; size\ncall _malloc\nmov edi, 0Ch; size\nmov rbp, rax\ncall _malloc\nmov r8d, r14d\nmov edx, 0Ch\nlea rcx, unk_3004\nmov [rbp+0], rax\nmov rdi, rax\nxor eax, eax\nmov esi, 2\nmov r14d, 1\ncall ___sprintf_chk\njmp loc_16E1\nloc_1E98:\nxor r14d, r14d\njmp loc_16E1\nloc_1EA0:\nsub ecx, 61h ; 'a'\nmov esi, ecx\nshr esi, 1Fh\nadd ecx, esi\nand ecx, 1\nsub ecx, esi\ncmp ecx, 1\nsetz cl\nmovzx ecx, cl\nadd r14d, ecx\njmp loc_1D96\nloc_1EC0:\nsub ecx, 61h ; 'a'\nmov esi, ecx\nshr esi, 1Fh\nadd ecx, esi\nand ecx, 1\nsub ecx, esi\ncmp ecx, 1\nsetz cl\nmovzx ecx, cl\nadd r14d, ecx\njmp loc_1DB8\nloc_1EE0:\nsub ecx, 61h ; 'a'\nmov esi, ecx\nshr esi, 1Fh\nadd ecx, esi\nand ecx, 1\nsub ecx, esi\ncmp ecx, 1\nsetz cl\nmovzx ecx, cl\nadd r14d, ecx\njmp loc_1DDA\nloc_1F00:\nsub ecx, 61h ; 'a'\nmov esi, ecx\nshr esi, 1Fh\nadd ecx, esi\nand ecx, 1\nsub ecx, esi\ncmp ecx, 1\nsetz cl\nmovzx ecx, cl\nadd r14d, ecx\njmp loc_1DF8\nloc_1F20:\nsub ecx, 61h ; 'a'\nmov esi, ecx\nshr esi, 1Fh\nadd ecx, esi\nand ecx, 1\nsub ecx, esi\ncmp ecx, 1\nsetz cl\nmovzx ecx, cl\nadd r14d, ecx\njmp loc_1E16\nloc_1F40:\npxor xmm3, xmm3\nxor esi, esi\nxor r14d, r14d\nxor edx, edx\njmp loc_1AC7\nloc_1F50:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_QWORD *__fastcall sub_15C0(__m128i *s, int *a2)\n{\n char *v3; // rbx\n int v4; // r13d\n _QWORD *v5; // rbp\n int v6; // r14d\n int v7; // edx\n __int64 v8; // r15\n char *v9; // r13\n char *v10; // rdx\n __int64 v11; // rax\n unsigned __int64 v12; // rax\n __int64 v13; // rcx\n unsigned int v15; // r14d\n const unsigned __int16 *v16; // rax\n const __m128i *v17; // rcx\n __m128i v18; // xmm3\n __m128i si128; // xmm7\n __m128i v20; // xmm6\n __m128i v21; // xmm5\n __m128i v22; // xmm0\n __m128i v23; // xmm14\n __m128i v24; // xmm1\n __m128i v25; // xmm9\n __m128i v26; // xmm13\n __m128i v27; // xmm0\n __m128i v28; // xmm1\n __m128i v29; // xmm10\n __m128i v30; // xmm2\n __m128i v31; // xmm13\n __m128i v32; // xmm2\n __m128i v33; // xmm1\n __m128i v34; // xmm10\n __m128i v35; // xmm13\n __m128i v36; // xmm0\n __m128i v37; // xmm1\n __m128i v38; // xmm15\n __m128i v39; // xmm12\n __m128i v40; // xmm10\n __m128i v41; // xmm2\n __m128i v42; // xmm11\n __m128i v43; // xmm0\n __m128i v44; // xmm13\n __m128i v45; // xmm2\n __m128i v46; // xmm13\n __m128i v47; // xmm0\n __m128i v48; // xmm2\n __m128i v49; // xmm1\n __m128i v50; // xmm10\n __m128i v51; // xmm0\n __m128i v52; // xmm10\n __m128i v53; // xmm1\n __m128i v54; // xmm0\n __m128i v55; // xmm9\n __m128i v56; // xmm2\n __m128i v57; // xmm1\n __int64 v58; // rsi\n __m128i v59; // xmm0\n unsigned int v60; // edx\n __m128i v61; // xmm3\n int v62; // ecx\n __int64 v63; // rsi\n __m128i v64; // xmm7\n __m128i v65; // xmm8\n __m128i v66; // xmm6\n __m128i v67; // xmm2\n __m128i v68; // xmm6\n __m128i v69; // xmm1\n __m128i v70; // xmm0\n __m128i v71; // xmm6\n __m128i v72; // xmm2\n __m128i v73; // xmm0\n __m128i v74; // xmm2\n __m128i v75; // xmm8\n __m128i v76; // xmm12\n __m128i v77; // xmm11\n __m128i v78; // xmm10\n __m128i v79; // xmm9\n __m128i v80; // xmm1\n __m128i v81; // xmm1\n __m128i v82; // xmm0\n __m128i v83; // xmm0\n __m128i v84; // xmm1\n __m128i v85; // xmm2\n __m128i v86; // xmm3\n __int64 v87; // rsi\n __int64 v88; // rsi\n __int64 v89; // rsi\n __int64 v90; // rsi\n __int64 v91; // rsi\n __int64 v92; // rsi\n int v93; // edx\n __int64 v94; // rcx\n void *v95; // rax\n __int64 v96; // r8\n __int64 v97; // r9\n __m128i v98; // [rsp+0h] [rbp-198h]\n __m128i v99; // [rsp+10h] [rbp-188h]\n __m128i v100; // [rsp+20h] [rbp-178h]\n __m128i v101; // [rsp+30h] [rbp-168h]\n __m128i v102; // [rsp+40h] [rbp-158h]\n __m128i v103; // [rsp+50h] [rbp-148h]\n __m128i v104; // [rsp+60h] [rbp-138h]\n __m128i v105; // [rsp+70h] [rbp-128h]\n __m128i v106; // [rsp+80h] [rbp-118h]\n __m128i v107; // [rsp+90h] [rbp-108h]\n __m128i v108; // [rsp+A0h] [rbp-F8h]\n __m128i v109; // [rsp+B0h] [rbp-E8h]\n __m128i v110; // [rsp+C0h] [rbp-D8h]\n __m128i v111; // [rsp+D0h] [rbp-C8h]\n __m128i v112; // [rsp+E0h] [rbp-B8h]\n char sa[16]; // [rsp+F0h] [rbp-A8h] BYREF\n __int128 v114; // [rsp+100h] [rbp-98h]\n __int128 v115; // [rsp+110h] [rbp-88h]\n __int128 v116; // [rsp+120h] [rbp-78h]\n __int128 v117; // [rsp+130h] [rbp-68h]\n _QWORD v118[3]; // [rsp+140h] [rbp-58h] BYREF\n unsigned __int64 v119; // [rsp+158h] [rbp-40h]\n\n v3 = (char *)s;\n v119 = __readfsqword(0x28u);\n memset(v118, 0, 21);\n v4 = strlen(s->m128i_i8);\n *(_OWORD *)sa = 0LL;\n v114 = 0LL;\n v115 = 0LL;\n v116 = 0LL;\n v117 = 0LL;\n if ( !strchr(s->m128i_i8, 32) && !strchr(s->m128i_i8, 44) )\n {\n v15 = 0;\n if ( v4 > 0 )\n {\n v16 = *__ctype_b_loc();\n if ( (unsigned int)(v4 - 1) <= 0xE )\n {\n v61 = 0LL;\n v58 = 0LL;\n v15 = 0;\n v60 = 0;\n goto LABEL_17;\n }\n v17 = s;\n v18 = 0LL;\n si128 = _mm_load_si128((const __m128i *)&xmmword_30C0);\n v20 = _mm_load_si128((const __m128i *)&xmmword_30D0);\n v21 = _mm_load_si128((const __m128i *)&xmmword_30E0);\n do\n {\n v22 = _mm_loadu_si128(v17++);\n v112 = v22;\n v111 = v22;\n v110 = v22;\n v109 = v22;\n v108 = v22;\n v107 = v22;\n v106 = v22;\n v105 = v22;\n v104 = v22;\n v103 = v22;\n v102 = v22;\n v101 = v22;\n v99 = v22;\n v100 = v22;\n v98 = v22;\n v23 = _mm_cmpeq_epi16(\n _mm_cmpeq_epi16(\n _mm_and_si128(\n _mm_unpacklo_epi64(\n _mm_unpacklo_epi32(\n _mm_insert_epi16(_mm_cvtsi32_si128(v16[(char)_mm_cvtsi128_si32(v22)]), v16[v22.m128i_i8[1]], 1),\n _mm_insert_epi16(_mm_cvtsi32_si128(v16[v22.m128i_i8[2]]), v16[v22.m128i_i8[3]], 1)),\n _mm_unpacklo_epi32(\n _mm_insert_epi16(_mm_cvtsi32_si128(v16[v22.m128i_i8[4]]), v16[v22.m128i_i8[5]], 1),\n _mm_insert_epi16(_mm_cvtsi32_si128(v16[v22.m128i_i8[6]]), v16[v22.m128i_i8[7]], 1))),\n si128),\n (__m128i)0LL),\n (__m128i)0LL);\n v24 = _mm_cmpgt_epi8((__m128i)0LL, v22);\n v25 = _mm_cmpeq_epi16(\n _mm_and_si128(\n _mm_unpacklo_epi64(\n _mm_unpacklo_epi32(\n _mm_insert_epi16(_mm_cvtsi32_si128(v16[v22.m128i_i8[8]]), v16[v22.m128i_i8[9]], 1),\n _mm_insert_epi16(_mm_cvtsi32_si128(v16[v22.m128i_i8[10]]), v16[v22.m128i_i8[11]], 1)),\n _mm_unpacklo_epi32(\n _mm_insert_epi16(_mm_cvtsi32_si128(v16[v22.m128i_i8[12]]), v16[v22.m128i_i8[13]], 1),\n _mm_insert_epi16(_mm_cvtsi32_si128(v16[v22.m128i_i8[14]]), v16[v22.m128i_i8[15]], 1))),\n si128),\n (__m128i)0LL);\n v26 = _mm_unpacklo_epi8(v22, v24);\n v27 = _mm_unpackhi_epi8(v22, v24);\n v28 = _mm_cmpgt_epi16((__m128i)0LL, v26);\n v29 = _mm_cmpgt_epi16((__m128i)0LL, v27);\n v30 = _mm_unpacklo_epi16(v26, v28);\n v31 = _mm_unpackhi_epi16(v26, v28);\n v32 = _mm_add_epi32(v30, v20);\n v33 = _mm_unpacklo_epi16(v27, v29);\n v34 = _mm_unpackhi_epi16(v27, v29);\n v35 = _mm_add_epi32(v31, v20);\n v36 = _mm_srli_epi32(v32, 0x1Fu);\n v37 = _mm_add_epi32(v33, v20);\n v38 = _mm_srli_epi32(v35, 0x1Fu);\n v39 = _mm_srli_epi32(v37, 0x1Fu);\n v40 = _mm_add_epi32(v34, v20);\n v41 = _mm_sub_epi32(_mm_and_si128(_mm_add_epi32(v32, v36), v21), v36);\n v42 = _mm_srli_epi32(v40, 0x1Fu);\n v43 = _mm_cmpeq_epi32(_mm_sub_epi32(_mm_and_si128(_mm_add_epi32(v35, v38), v21), v38), v21);\n v44 = _mm_cmpeq_epi32(v41, v21);\n v45 = _mm_unpacklo_epi16(v44, v43);\n v46 = _mm_unpackhi_epi16(v44, v43);\n v47 = _mm_add_epi32(v37, v39);\n v48 = _mm_and_si128(_mm_unpacklo_epi16(_mm_unpacklo_epi16(v45, v46), _mm_unpackhi_epi16(v45, v46)), v23);\n v49 = _mm_cmpeq_epi32(_mm_sub_epi32(_mm_and_si128(_mm_add_epi32(v40, v42), v21), v42), v21);\n v50 = _mm_cmpeq_epi32(_mm_sub_epi32(_mm_and_si128(v47, v21), v39), v21);\n v51 = _mm_unpacklo_epi16(v50, v49);\n v52 = _mm_unpackhi_epi16(v50, v49);\n v53 = _mm_cmpgt_epi16((__m128i)0LL, v48);\n v54 = _mm_and_si128(\n _mm_unpacklo_epi16(_mm_unpacklo_epi16(v51, v52), _mm_unpackhi_epi16(v51, v52)),\n _mm_cmpeq_epi16(v25, (__m128i)0LL));\n v55 = _mm_unpacklo_epi16(v48, v53);\n v56 = _mm_unpackhi_epi16(v48, v53);\n v57 = _mm_cmpgt_epi16((__m128i)0LL, v54);\n v18 = _mm_sub_epi32(\n _mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(v18, v55), v56), _mm_unpacklo_epi16(v54, v57)),\n _mm_unpackhi_epi16(v54, v57));\n }\n while ( &s[(unsigned int)v4 >> 4] != v17 );\n v58 = v4 & 0xFFFFFFF0;\n v59 = _mm_add_epi32(_mm_srli_si128(v18, 8), v18);\n v60 = v4 & 0xFFFFFFF0;\n v61 = v59;\n v15 = _mm_cvtsi128_si32(_mm_add_epi32(v59, _mm_srli_si128(v59, 4)));\n if ( (v4 & 0xF) != 0 )\n {\nLABEL_17:\n v62 = v4 - v58;\n if ( (unsigned int)(v4 - v58 - 1) <= 6 )\n goto LABEL_19;\n v63 = *(__int64 *)((char *)s->m128i_i64 + v58);\n v64 = _mm_loadl_epi64((const __m128i *)&xmmword_30C0);\n v65 = _mm_loadl_epi64((const __m128i *)&xmmword_30D0);\n v66 = _mm_unpacklo_epi8(\n (__m128i)(unsigned __int64)v63,\n _mm_cmpgt_epi8((__m128i)0LL, (__m128i)(unsigned __int64)v63));\n v67 = _mm_shuffle_epi32(v66, 78);\n v68 = _mm_unpacklo_epi16(v66, _mm_cmpgt_epi16((__m128i)0LL, v66));\n v69 = _mm_add_epi32(v68, v65);\n v70 = _mm_unpacklo_epi16(v67, _mm_cmpgt_epi16((__m128i)0LL, v67));\n v71 = _mm_add_epi32(_mm_shuffle_epi32(v68, 78), v65);\n v72 = _mm_shuffle_epi32(v70, 78);\n v73 = _mm_add_epi32(v70, v65);\n v74 = _mm_add_epi32(v72, v65);\n v75 = _mm_loadl_epi64((const __m128i *)&xmmword_30E0);\n v76 = _mm_and_si128(_mm_cmpgt_epi32((__m128i)0LL, v69), v75);\n v77 = _mm_and_si128(_mm_cmpgt_epi32((__m128i)0LL, v71), v75);\n v78 = _mm_and_si128(_mm_cmpgt_epi32((__m128i)0LL, v73), v75);\n v79 = _mm_and_si128(_mm_cmpgt_epi32((__m128i)0LL, v74), v75);\n v80 = _mm_unpacklo_epi16(\n _mm_cmpeq_epi32(_mm_sub_epi32(_mm_and_si128(_mm_add_epi32(v69, v76), v75), v76), v75),\n _mm_cmpeq_epi32(_mm_sub_epi32(_mm_and_si128(_mm_add_epi32(v71, v77), v75), v77), v75));\n v81 = _mm_and_si128(\n _mm_unpacklo_epi16(v80, _mm_shuffle_epi32(v80, 78)),\n _mm_cmpeq_epi16(\n _mm_cmpeq_epi16(\n _mm_and_si128(\n (__m128i)(v16[(char)v63] | ((v16[SBYTE1(v63)] | ((v16[(char)((_DWORD)v63 << 8 >> 24)] | ((unsigned __int64)v16[SBYTE3(v63)] << 16)) << 16)) << 16)),\n v64),\n (__m128i)0LL),\n (__m128i)0LL));\n v82 = _mm_unpacklo_epi16(\n _mm_cmpeq_epi32(_mm_sub_epi32(_mm_and_si128(_mm_add_epi32(v73, v78), v75), v78), v75),\n _mm_cmpeq_epi32(_mm_sub_epi32(_mm_and_si128(_mm_add_epi32(v74, v79), v75), v79), v75));\n v83 = _mm_and_si128(\n _mm_unpacklo_epi16(v82, _mm_shuffle_epi32(v82, 78)),\n _mm_cmpeq_epi16(\n _mm_cmpeq_epi16(\n _mm_and_si128(\n v64,\n (__m128i)(v16[v63 << 24 >> 56] | ((v16[v63 << 16 >> 56] | ((v16[v63 << 8 >> 56] | ((unsigned __int64)v16[v63 >> 56] << 16)) << 16)) << 16))),\n (__m128i)0LL),\n (__m128i)0LL));\n v84 = _mm_unpacklo_epi16(v81, _mm_cmpgt_epi16((__m128i)0LL, v81));\n v85 = _mm_unpacklo_epi16(v83, _mm_cmpgt_epi16((__m128i)0LL, v83));\n v86 = _mm_sub_epi32(\n _mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(v61, v84), _mm_shuffle_epi32(v84, 78)), v85),\n _mm_shuffle_epi32(v85, 78));\n v15 = _mm_cvtsi128_si32(_mm_shuffle_epi32(v86, 229)) + _mm_cvtsi128_si32(v86);\n v60 += v62 & 0xFFFFFFF8;\n if ( (v62 & 7) != 0 )\n {\nLABEL_19:\n v87 = s->m128i_i8[v60];\n if ( (v16[v87] & 0x200) != 0 )\n v15 += ((int)v87 - 97) % 2 == 1;\n if ( (int)(v60 + 1) < v4 )\n {\n v88 = s->m128i_i8[v60 + 1];\n if ( (v16[v88] & 0x200) != 0 )\n v15 += ((int)v88 - 97) % 2 == 1;\n if ( v4 > (int)(v60 + 2) )\n {\n v89 = s->m128i_i8[v60 + 2];\n if ( (v16[v89] & 0x200) != 0 )\n v15 += ((int)v89 - 97) % 2 == 1;\n if ( v4 > (int)(v60 + 3) )\n {\n v90 = s->m128i_i8[v60 + 3];\n if ( (v16[v90] & 0x200) != 0 )\n v15 += ((int)v90 - 97) % 2 == 1;\n if ( v4 > (int)(v60 + 4) )\n {\n v91 = s->m128i_i8[v60 + 4];\n if ( (v16[v91] & 0x200) != 0 )\n v15 += ((int)v91 - 97) % 2 == 1;\n if ( v4 > (int)(v60 + 5) )\n {\n v92 = s->m128i_i8[v60 + 5];\n if ( (v16[v92] & 0x200) != 0 )\n v15 += ((int)v92 - 97) % 2 == 1;\n v93 = v60 + 6;\n if ( v4 > v93 )\n {\n v94 = s->m128i_i8[v93];\n if ( (v16[v94] & 0x200) != 0 )\n v15 += ((char)v94 - 97) % 2 == 1;\n }\n }\n }\n }\n }\n }\n }\n }\n }\n v5 = malloc(8uLL);\n v95 = malloc(0xCuLL);\n v96 = v15;\n *v5 = v95;\n v6 = 1;\n __sprintf_chk(\n v95,\n 2LL,\n 12LL,\n &unk_3004,\n v96,\n v97,\n v98.m128i_i64[0],\n v98.m128i_i64[1],\n v99.m128i_i64[0],\n v99.m128i_i64[1],\n v100.m128i_i64[0],\n v100.m128i_i64[1],\n v101.m128i_i64[0],\n v101.m128i_i64[1],\n v102.m128i_i64[0],\n v102.m128i_i64[1],\n v103.m128i_i64[0],\n v103.m128i_i64[1],\n v104.m128i_i64[0],\n v104.m128i_i64[1],\n v105.m128i_i64[0],\n v105.m128i_i64[1],\n v106.m128i_i64[0],\n v106.m128i_i64[1],\n v107.m128i_i64[0],\n v107.m128i_i64[1],\n v108.m128i_i64[0],\n v108.m128i_i64[1],\n v109.m128i_i64[0],\n v109.m128i_i64[1],\n v110.m128i_i64[0],\n v110.m128i_i64[1],\n v111.m128i_i64[0],\n v111.m128i_i64[1],\n v112.m128i_i64[0],\n v112.m128i_i64[1],\n *(_QWORD *)sa,\n *(_QWORD *)&sa[8],\n v114,\n *((_QWORD *)&v114 + 1),\n v115,\n *((_QWORD *)&v115 + 1),\n v116,\n *((_QWORD *)&v116 + 1),\n v117,\n *((_QWORD *)&v117 + 1),\n v118[0],\n v118[1],\n v118[2],\n v119);\n goto LABEL_10;\n }\n v5 = malloc(8LL * (v4 + 1));\n if ( v4 < 0 )\n {\n v6 = 0;\n }\n else\n {\n v6 = 0;\n v7 = 0;\n v8 = 0x100100000001LL;\n v9 = &s->m128i_i8[v4 + 1];\n do\n {\n while ( 1 )\n {\n v12 = (unsigned __int8)*v3;\n if ( (unsigned __int8)v12 <= 0x2Cu )\n {\n if ( _bittest64(&v8, v12) )\n break;\n }\n v13 = v7;\n ++v3;\n ++v7;\n sa[v13] = v12;\n if ( v9 == v3 )\n goto LABEL_10;\n }\n if ( v7 > 0 )\n {\n sa[v7] = 0;\n v10 = strdup(sa);\n v11 = v6++;\n v5[v11] = v10;\n v7 = 0;\n }\n ++v3;\n }\n while ( v9 != v3 );\n }\nLABEL_10:\n *a2 = v6;\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_15C0(__m128i *s, int *a2) {\n char *v3;\n int v4;\n uint64_t *v5;\n int v6;\n int v7;\n long long v8;\n char *v9;\n char *v10;\n long long v11;\n unsigned long long v12;\n long long v13;\n unsigned int v15;\n const unsigned short *v16;\n const __m128i *v17;\n __m128i v18;\n __m128i si128;\n __m128i v20;\n __m128i v21;\n __m128i v22;\n __m128i v23;\n __m128i v24;\n __m128i v25;\n __m128i v26;\n __m128i v27;\n __m128i v28;\n __m128i v29;\n __m128i v30;\n __m128i v31;\n __m128i v32;\n __m128i v33;\n __m128i v34;\n __m128i v35;\n __m128i v36;\n __m128i v37;\n __m128i v38;\n __m128i v39;\n __m128i v40;\n __m128i v41;\n __m128i v42;\n __m128i v43;\n __m128i v44;\n __m128i v45;\n __m128i v46;\n __m128i v47;\n __m128i v48;\n __m128i v49;\n __m128i v50;\n __m128i v51;\n __m128i v52;\n __m128i v53;\n __m128i v54;\n __m128i v55;\n __m128i v56;\n __m128i v57;\n long long v58;\n __m128i v59;\n unsigned int v60;\n __m128i v61;\n int v62;\n long long v63;\n __m128i v64;\n __m128i v65;\n __m128i v66;\n __m128i v67;\n __m128i v68;\n __m128i v69;\n __m128i v70;\n __m128i v71;\n __m128i v72;\n __m128i v73;\n __m128i v74;\n __m128i v75;\n __m128i v76;\n __m128i v77;\n __m128i v78;\n __m128i v79;\n __m128i v80;\n __m128i v81;\n __m128i v82;\n __m128i v83;\n __m128i v84;\n __m128i v85;\n __m128i v86;\n long long v87;\n long long v88;\n long long v89;\n long long v90;\n long long v91;\n long long v92;\n int v93;\n long long v94;\n void *v95;\n long long v96;\n long long v97;\n __m128i v98;\n __m128i v99;\n __m128i v100;\n __m128i v101;\n __m128i v102;\n __m128i v103;\n __m128i v104;\n __m128i v105;\n __m128i v106;\n __m128i v107;\n __m128i v108;\n __m128i v109;\n __m128i v110;\n __m128i v111;\n __m128i v112;\n char sa[16];\n __int128 v114;\n __int128 v115;\n __int128 v116;\n __int128 v117;\n uint64_t v118[3];\n unsigned long long v119;\n v3 = (char *)s;\n v119 = __readfsqword(40u);\n memset(v118, 0, 21);\n v4 = strlen(s->m128i_i8);\n *(long double *)sa = 0LL;\n v114 = 0LL;\n v115 = 0LL;\n v116 = 0LL;\n v117 = 0LL;\n if (!strchr(s->m128i_i8, 32) && !strchr(s->m128i_i8, 44)) {\n v15 = 0;\n if (v4 > 0) {\n v16 = *__ctype_b_loc();\n if ((unsigned int)(v4 - 1) <= 14) {\n v61 = 0LL;\n v58 = 0LL;\n v15 = 0;\n v60 = 0;\n goto LABEL_17;\n }\n v17 = s;\n v18 = 0LL;\n si128 = _mm_load_si128((const __m128i *)&xmmword_30C0);\n v20 = _mm_load_si128((const __m128i *)&xmmword_30D0);\n v21 = _mm_load_si128((const __m128i *)&xmmword_30E0);\n do {\n v22 = _mm_loadu_si128(v17++);\n v112 = v22;\n v111 = v22;\n v110 = v22;\n v109 = v22;\n v108 = v22;\n v107 = v22;\n v106 = v22;\n v105 = v22;\n v104 = v22;\n v103 = v22;\n v102 = v22;\n v101 = v22;\n v99 = v22;\n v100 = v22;\n v98 = v22;\n v23 = _mm_cmpeq_epi16(\n _mm_cmpeq_epi16(\n _mm_and_si128(\n _mm_unpacklo_epi64(\n _mm_unpacklo_epi32(\n _mm_insert_epi16(\n _mm_cvtsi32_si128(\n v16[(char)_mm_cvtsi128_si32(v22)]),\n v16[v22.m128i_i8[1]], 1),\n _mm_insert_epi16(\n _mm_cvtsi32_si128(v16[v22.m128i_i8[2]]),\n v16[v22.m128i_i8[3]], 1)),\n _mm_unpacklo_epi32(\n _mm_insert_epi16(\n _mm_cvtsi32_si128(v16[v22.m128i_i8[4]]),\n v16[v22.m128i_i8[5]], 1),\n _mm_insert_epi16(\n _mm_cvtsi32_si128(v16[v22.m128i_i8[6]]),\n v16[v22.m128i_i8[7]], 1))),\n si128),\n (__m128i)0LL),\n (__m128i)0LL);\n v24 = _mm_cmpgt_epi8((__m128i)0LL, v22);\n v25 = _mm_cmpeq_epi16(\n _mm_and_si128(_mm_unpacklo_epi64(\n _mm_unpacklo_epi32(\n _mm_insert_epi16(\n _mm_cvtsi32_si128(v16[v22.m128i_i8[8]]),\n v16[v22.m128i_i8[9]], 1),\n _mm_insert_epi16(\n _mm_cvtsi32_si128(v16[v22.m128i_i8[10]]),\n v16[v22.m128i_i8[11]], 1)),\n _mm_unpacklo_epi32(\n _mm_insert_epi16(\n _mm_cvtsi32_si128(v16[v22.m128i_i8[12]]),\n v16[v22.m128i_i8[13]], 1),\n _mm_insert_epi16(\n _mm_cvtsi32_si128(v16[v22.m128i_i8[14]]),\n v16[v22.m128i_i8[15]], 1))),\n si128),\n (__m128i)0LL);\n v26 = _mm_unpacklo_epi8(v22, v24);\n v27 = _mm_unpackhi_epi8(v22, v24);\n v28 = _mm_cmpgt_epi16((__m128i)0LL, v26);\n v29 = _mm_cmpgt_epi16((__m128i)0LL, v27);\n v30 = _mm_unpacklo_epi16(v26, v28);\n v31 = _mm_unpackhi_epi16(v26, v28);\n v32 = _mm_add_epi32(v30, v20);\n v33 = _mm_unpacklo_epi16(v27, v29);\n v34 = _mm_unpackhi_epi16(v27, v29);\n v35 = _mm_add_epi32(v31, v20);\n v36 = _mm_srli_epi32(v32, 31u);\n v37 = _mm_add_epi32(v33, v20);\n v38 = _mm_srli_epi32(v35, 31u);\n v39 = _mm_srli_epi32(v37, 31u);\n v40 = _mm_add_epi32(v34, v20);\n v41 = _mm_sub_epi32(_mm_and_si128(_mm_add_epi32(v32, v36), v21), v36);\n v42 = _mm_srli_epi32(v40, 31u);\n v43 = _mm_cmpeq_epi32(\n _mm_sub_epi32(_mm_and_si128(_mm_add_epi32(v35, v38), v21), v38),\n v21);\n v44 = _mm_cmpeq_epi32(v41, v21);\n v45 = _mm_unpacklo_epi16(v44, v43);\n v46 = _mm_unpackhi_epi16(v44, v43);\n v47 = _mm_add_epi32(v37, v39);\n v48 = _mm_and_si128(_mm_unpacklo_epi16(_mm_unpacklo_epi16(v45, v46),\n _mm_unpackhi_epi16(v45, v46)),\n v23);\n v49 = _mm_cmpeq_epi32(\n _mm_sub_epi32(_mm_and_si128(_mm_add_epi32(v40, v42), v21), v42),\n v21);\n v50 = _mm_cmpeq_epi32(_mm_sub_epi32(_mm_and_si128(v47, v21), v39), v21);\n v51 = _mm_unpacklo_epi16(v50, v49);\n v52 = _mm_unpackhi_epi16(v50, v49);\n v53 = _mm_cmpgt_epi16((__m128i)0LL, v48);\n v54 = _mm_and_si128(_mm_unpacklo_epi16(_mm_unpacklo_epi16(v51, v52),\n _mm_unpackhi_epi16(v51, v52)),\n _mm_cmpeq_epi16(v25, (__m128i)0LL));\n v55 = _mm_unpacklo_epi16(v48, v53);\n v56 = _mm_unpackhi_epi16(v48, v53);\n v57 = _mm_cmpgt_epi16((__m128i)0LL, v54);\n v18 = _mm_sub_epi32(\n _mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(v18, v55), v56),\n _mm_unpacklo_epi16(v54, v57)),\n _mm_unpackhi_epi16(v54, v57));\n } while (&s[(unsigned int)v4 >> 4] != v17);\n v58 = v4 & 4294967280;\n v59 = _mm_add_epi32(_mm_srli_si128(v18, 8), v18);\n v60 = v4 & 4294967280;\n v61 = v59;\n v15 = _mm_cvtsi128_si32(_mm_add_epi32(v59, _mm_srli_si128(v59, 4)));\n if ((v4 & 15) != 0) {\n LABEL_17:\n v62 = v4 - v58;\n if ((unsigned int)(v4 - v58 - 1) <= 6) goto LABEL_19;\n v63 = *(long long *)((char *)s->m128i_i64 + v58);\n v64 = _mm_loadl_epi64((const __m128i *)&xmmword_30C0);\n v65 = _mm_loadl_epi64((const __m128i *)&xmmword_30D0);\n v66 = _mm_unpacklo_epi8(\n (__m128i)(unsigned long long)v63,\n _mm_cmpgt_epi8((__m128i)0LL, (__m128i)(unsigned long long)v63));\n v67 = _mm_shuffle_epi32(v66, 78);\n v68 = _mm_unpacklo_epi16(v66, _mm_cmpgt_epi16((__m128i)0LL, v66));\n v69 = _mm_add_epi32(v68, v65);\n v70 = _mm_unpacklo_epi16(v67, _mm_cmpgt_epi16((__m128i)0LL, v67));\n v71 = _mm_add_epi32(_mm_shuffle_epi32(v68, 78), v65);\n v72 = _mm_shuffle_epi32(v70, 78);\n v73 = _mm_add_epi32(v70, v65);\n v74 = _mm_add_epi32(v72, v65);\n v75 = _mm_loadl_epi64((const __m128i *)&xmmword_30E0);\n v76 = _mm_and_si128(_mm_cmpgt_epi32((__m128i)0LL, v69), v75);\n v77 = _mm_and_si128(_mm_cmpgt_epi32((__m128i)0LL, v71), v75);\n v78 = _mm_and_si128(_mm_cmpgt_epi32((__m128i)0LL, v73), v75);\n v79 = _mm_and_si128(_mm_cmpgt_epi32((__m128i)0LL, v74), v75);\n v80 = _mm_unpacklo_epi16(\n _mm_cmpeq_epi32(\n _mm_sub_epi32(_mm_and_si128(_mm_add_epi32(v69, v76), v75), v76),\n v75),\n _mm_cmpeq_epi32(\n _mm_sub_epi32(_mm_and_si128(_mm_add_epi32(v71, v77), v75), v77),\n v75));\n v81 = _mm_and_si128(\n _mm_unpacklo_epi16(v80, _mm_shuffle_epi32(v80, 78)),\n _mm_cmpeq_epi16(\n _mm_cmpeq_epi16(\n _mm_and_si128(\n (__m128i)(\n v16[(char)v63] |\n ((v16[SBYTE1(v63)] |\n ((v16[(char)((uint32_t)v63 << 8 >> 24)] |\n ((unsigned long long)v16[SBYTE3(v63)] << 16))\n << 16))\n << 16)),\n v64),\n (__m128i)0LL),\n (__m128i)0LL));\n v82 = _mm_unpacklo_epi16(\n _mm_cmpeq_epi32(\n _mm_sub_epi32(_mm_and_si128(_mm_add_epi32(v73, v78), v75), v78),\n v75),\n _mm_cmpeq_epi32(\n _mm_sub_epi32(_mm_and_si128(_mm_add_epi32(v74, v79), v75), v79),\n v75));\n v83 = _mm_and_si128(\n _mm_unpacklo_epi16(v82, _mm_shuffle_epi32(v82, 78)),\n _mm_cmpeq_epi16(\n _mm_cmpeq_epi16(\n _mm_and_si128(\n v64, (__m128i)(\n v16[v63 << 24 >> 56] |\n ((v16[v63 << 16 >> 56] |\n ((v16[v63 << 8 >> 56] |\n ((unsigned long long)v16[v63 >> 56] << 16))\n << 16))\n << 16))),\n (__m128i)0LL),\n (__m128i)0LL));\n v84 = _mm_unpacklo_epi16(v81, _mm_cmpgt_epi16((__m128i)0LL, v81));\n v85 = _mm_unpacklo_epi16(v83, _mm_cmpgt_epi16((__m128i)0LL, v83));\n v86 = _mm_sub_epi32(\n _mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(v61, v84),\n _mm_shuffle_epi32(v84, 78)),\n v85),\n _mm_shuffle_epi32(v85, 78));\n v15 = _mm_cvtsi128_si32(_mm_shuffle_epi32(v86, 229)) +\n _mm_cvtsi128_si32(v86);\n v60 += v62 & 4294967288;\n if ((v62 & 7) != 0) {\n LABEL_19:\n v87 = s->m128i_i8[v60];\n if ((v16[v87] & 512) != 0) v15 += ((int)v87 - 97) % 2 == 1;\n if ((int)(v60 + 1) < v4) {\n v88 = s->m128i_i8[v60 + 1];\n if ((v16[v88] & 512) != 0) v15 += ((int)v88 - 97) % 2 == 1;\n if (v4 > (int)(v60 + 2)) {\n v89 = s->m128i_i8[v60 + 2];\n if ((v16[v89] & 512) != 0) v15 += ((int)v89 - 97) % 2 == 1;\n if (v4 > (int)(v60 + 3)) {\n v90 = s->m128i_i8[v60 + 3];\n if ((v16[v90] & 512) != 0) v15 += ((int)v90 - 97) % 2 == 1;\n if (v4 > (int)(v60 + 4)) {\n v91 = s->m128i_i8[v60 + 4];\n if ((v16[v91] & 512) != 0) v15 += ((int)v91 - 97) % 2 == 1;\n if (v4 > (int)(v60 + 5)) {\n v92 = s->m128i_i8[v60 + 5];\n if ((v16[v92] & 512) != 0) v15 += ((int)v92 - 97) % 2 == 1;\n v93 = v60 + 6;\n if (v4 > v93) {\n v94 = s->m128i_i8[v93];\n if ((v16[v94] & 512) != 0)\n v15 += ((char)v94 - 97) % 2 == 1;\n }\n }\n }\n }\n }\n }\n }\n }\n }\n v5 = malloc(8uLL);\n v95 = malloc(12uLL);\n v96 = v15;\n *v5 = v95;\n v6 = 1;\n __sprintf_chk(v95, 2LL, 12LL, &unk_3004, v96, v97, v98.m128i_i64[0],\n v98.m128i_i64[1], v99.m128i_i64[0], v99.m128i_i64[1],\n v100.m128i_i64[0], v100.m128i_i64[1], v101.m128i_i64[0],\n v101.m128i_i64[1], v102.m128i_i64[0], v102.m128i_i64[1],\n v103.m128i_i64[0], v103.m128i_i64[1], v104.m128i_i64[0],\n v104.m128i_i64[1], v105.m128i_i64[0], v105.m128i_i64[1],\n v106.m128i_i64[0], v106.m128i_i64[1], v107.m128i_i64[0],\n v107.m128i_i64[1], v108.m128i_i64[0], v108.m128i_i64[1],\n v109.m128i_i64[0], v109.m128i_i64[1], v110.m128i_i64[0],\n v110.m128i_i64[1], v111.m128i_i64[0], v111.m128i_i64[1],\n v112.m128i_i64[0], v112.m128i_i64[1], *(uint64_t *)sa,\n *(uint64_t *)&sa[8], v114, *((uint64_t *)&v114 + 1), v115,\n *((uint64_t *)&v115 + 1), v116, *((uint64_t *)&v116 + 1),\n v117, *((uint64_t *)&v117 + 1), v118[0], v118[1], v118[2],\n v119);\n goto LABEL_10;\n }\n v5 = malloc(8LL * (v4 + 1));\n if (v4 < 0) {\n v6 = 0;\n } else {\n v6 = 0;\n v7 = 0;\n v8 = 17596481011713LL;\n v9 = &s->m128i_i8[v4 + 1];\n do {\n while (1) {\n v12 = (unsigned char)*v3;\n if ((unsigned char)v12 <= 44u) {\n if (_bittest64(&v8, v12)) break;\n }\n v13 = v7;\n ++v3;\n ++v7;\n sa[v13] = v12;\n if (v9 == v3) goto LABEL_10;\n }\n if (v7 > 0) {\n sa[v7] = 0;\n v10 = strdup(sa);\n v11 = v6++;\n v5[v11] = v10;\n v7 = 0;\n }\n ++v3;\n } while (v9 != v3);\n }\nLABEL_10:\n *a2 = v6;\n return v5;\n}", + "ida_pseudo_norm": "uint64_t *func0(__m128i *s, int *a2) {\n char *v3;\n int v4;\n uint64_t *v5;\n int v6;\n int v7;\n long long v8;\n char *v9;\n char *v10;\n long long v11;\n unsigned long long v12;\n long long v13;\n unsigned int v15;\n const unsigned short *v16;\n const __m128i *v17;\n __m128i v18;\n __m128i si128;\n __m128i v20;\n __m128i v21;\n __m128i v22;\n __m128i v23;\n __m128i v24;\n __m128i v25;\n __m128i v26;\n __m128i v27;\n __m128i v28;\n __m128i v29;\n __m128i v30;\n __m128i v31;\n __m128i v32;\n __m128i v33;\n __m128i v34;\n __m128i v35;\n __m128i v36;\n __m128i v37;\n __m128i v38;\n __m128i v39;\n __m128i v40;\n __m128i v41;\n __m128i v42;\n __m128i v43;\n __m128i v44;\n __m128i v45;\n __m128i v46;\n __m128i v47;\n __m128i v48;\n __m128i v49;\n __m128i v50;\n __m128i v51;\n __m128i v52;\n __m128i v53;\n __m128i v54;\n __m128i v55;\n __m128i v56;\n __m128i v57;\n long long v58;\n __m128i v59;\n unsigned int v60;\n __m128i v61;\n int v62;\n long long v63;\n __m128i v64;\n __m128i v65;\n __m128i v66;\n __m128i v67;\n __m128i v68;\n __m128i v69;\n __m128i v70;\n __m128i v71;\n __m128i v72;\n __m128i v73;\n __m128i v74;\n __m128i v75;\n __m128i v76;\n __m128i v77;\n __m128i v78;\n __m128i v79;\n __m128i v80;\n __m128i v81;\n __m128i v82;\n __m128i v83;\n __m128i v84;\n __m128i v85;\n __m128i v86;\n long long v87;\n long long v88;\n long long v89;\n long long v90;\n long long v91;\n long long v92;\n int v93;\n long long v94;\n void *v95;\n long long v96;\n long long v97;\n __m128i v98;\n __m128i v99;\n __m128i v100;\n __m128i v101;\n __m128i v102;\n __m128i v103;\n __m128i v104;\n __m128i v105;\n __m128i v106;\n __m128i v107;\n __m128i v108;\n __m128i v109;\n __m128i v110;\n __m128i v111;\n __m128i v112;\n char sa[16];\n __int128 v114;\n __int128 v115;\n __int128 v116;\n __int128 v117;\n uint64_t v118[3];\n unsigned long long v119;\n v3 = (char *)s;\n v119 = __readfsqword(40u);\n memset(v118, 0, 21);\n v4 = strlen(s->m128i_i8);\n *(long double *)sa = 0LL;\n v114 = 0LL;\n v115 = 0LL;\n v116 = 0LL;\n v117 = 0LL;\n if (!strchr(s->m128i_i8, 32) && !strchr(s->m128i_i8, 44)) {\n v15 = 0;\n if (v4 > 0) {\n v16 = *__ctype_b_loc();\n if ((unsigned int)(v4 - 1) <= 14) {\n v61 = 0LL;\n v58 = 0LL;\n v15 = 0;\n v60 = 0;\n goto LABEL_17;\n }\n v17 = s;\n v18 = 0LL;\n si128 = _mm_load_si128((const __m128i *)&xmmword_30C0);\n v20 = _mm_load_si128((const __m128i *)&xmmword_30D0);\n v21 = _mm_load_si128((const __m128i *)&xmmword_30E0);\n do {\n v22 = _mm_loadu_si128(v17++);\n v112 = v22;\n v111 = v22;\n v110 = v22;\n v109 = v22;\n v108 = v22;\n v107 = v22;\n v106 = v22;\n v105 = v22;\n v104 = v22;\n v103 = v22;\n v102 = v22;\n v101 = v22;\n v99 = v22;\n v100 = v22;\n v98 = v22;\n v23 = _mm_cmpeq_epi16(\n _mm_cmpeq_epi16(\n _mm_and_si128(\n _mm_unpacklo_epi64(\n _mm_unpacklo_epi32(\n _mm_insert_epi16(\n _mm_cvtsi32_si128(\n v16[(char)_mm_cvtsi128_si32(v22)]),\n v16[v22.m128i_i8[1]], 1),\n _mm_insert_epi16(\n _mm_cvtsi32_si128(v16[v22.m128i_i8[2]]),\n v16[v22.m128i_i8[3]], 1)),\n _mm_unpacklo_epi32(\n _mm_insert_epi16(\n _mm_cvtsi32_si128(v16[v22.m128i_i8[4]]),\n v16[v22.m128i_i8[5]], 1),\n _mm_insert_epi16(\n _mm_cvtsi32_si128(v16[v22.m128i_i8[6]]),\n v16[v22.m128i_i8[7]], 1))),\n si128),\n (__m128i)0LL),\n (__m128i)0LL);\n v24 = _mm_cmpgt_epi8((__m128i)0LL, v22);\n v25 = _mm_cmpeq_epi16(\n _mm_and_si128(_mm_unpacklo_epi64(\n _mm_unpacklo_epi32(\n _mm_insert_epi16(\n _mm_cvtsi32_si128(v16[v22.m128i_i8[8]]),\n v16[v22.m128i_i8[9]], 1),\n _mm_insert_epi16(\n _mm_cvtsi32_si128(v16[v22.m128i_i8[10]]),\n v16[v22.m128i_i8[11]], 1)),\n _mm_unpacklo_epi32(\n _mm_insert_epi16(\n _mm_cvtsi32_si128(v16[v22.m128i_i8[12]]),\n v16[v22.m128i_i8[13]], 1),\n _mm_insert_epi16(\n _mm_cvtsi32_si128(v16[v22.m128i_i8[14]]),\n v16[v22.m128i_i8[15]], 1))),\n si128),\n (__m128i)0LL);\n v26 = _mm_unpacklo_epi8(v22, v24);\n v27 = _mm_unpackhi_epi8(v22, v24);\n v28 = _mm_cmpgt_epi16((__m128i)0LL, v26);\n v29 = _mm_cmpgt_epi16((__m128i)0LL, v27);\n v30 = _mm_unpacklo_epi16(v26, v28);\n v31 = _mm_unpackhi_epi16(v26, v28);\n v32 = _mm_add_epi32(v30, v20);\n v33 = _mm_unpacklo_epi16(v27, v29);\n v34 = _mm_unpackhi_epi16(v27, v29);\n v35 = _mm_add_epi32(v31, v20);\n v36 = _mm_srli_epi32(v32, 31u);\n v37 = _mm_add_epi32(v33, v20);\n v38 = _mm_srli_epi32(v35, 31u);\n v39 = _mm_srli_epi32(v37, 31u);\n v40 = _mm_add_epi32(v34, v20);\n v41 = _mm_sub_epi32(_mm_and_si128(_mm_add_epi32(v32, v36), v21), v36);\n v42 = _mm_srli_epi32(v40, 31u);\n v43 = _mm_cmpeq_epi32(\n _mm_sub_epi32(_mm_and_si128(_mm_add_epi32(v35, v38), v21), v38),\n v21);\n v44 = _mm_cmpeq_epi32(v41, v21);\n v45 = _mm_unpacklo_epi16(v44, v43);\n v46 = _mm_unpackhi_epi16(v44, v43);\n v47 = _mm_add_epi32(v37, v39);\n v48 = _mm_and_si128(_mm_unpacklo_epi16(_mm_unpacklo_epi16(v45, v46),\n _mm_unpackhi_epi16(v45, v46)),\n v23);\n v49 = _mm_cmpeq_epi32(\n _mm_sub_epi32(_mm_and_si128(_mm_add_epi32(v40, v42), v21), v42),\n v21);\n v50 = _mm_cmpeq_epi32(_mm_sub_epi32(_mm_and_si128(v47, v21), v39), v21);\n v51 = _mm_unpacklo_epi16(v50, v49);\n v52 = _mm_unpackhi_epi16(v50, v49);\n v53 = _mm_cmpgt_epi16((__m128i)0LL, v48);\n v54 = _mm_and_si128(_mm_unpacklo_epi16(_mm_unpacklo_epi16(v51, v52),\n _mm_unpackhi_epi16(v51, v52)),\n _mm_cmpeq_epi16(v25, (__m128i)0LL));\n v55 = _mm_unpacklo_epi16(v48, v53);\n v56 = _mm_unpackhi_epi16(v48, v53);\n v57 = _mm_cmpgt_epi16((__m128i)0LL, v54);\n v18 = _mm_sub_epi32(\n _mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(v18, v55), v56),\n _mm_unpacklo_epi16(v54, v57)),\n _mm_unpackhi_epi16(v54, v57));\n } while (&s[(unsigned int)v4 >> 4] != v17);\n v58 = v4 & 4294967280;\n v59 = _mm_add_epi32(_mm_srli_si128(v18, 8), v18);\n v60 = v4 & 4294967280;\n v61 = v59;\n v15 = _mm_cvtsi128_si32(_mm_add_epi32(v59, _mm_srli_si128(v59, 4)));\n if ((v4 & 15) != 0) {\n LABEL_17:\n v62 = v4 - v58;\n if ((unsigned int)(v4 - v58 - 1) <= 6) goto LABEL_19;\n v63 = *(long long *)((char *)s->m128i_i64 + v58);\n v64 = _mm_loadl_epi64((const __m128i *)&xmmword_30C0);\n v65 = _mm_loadl_epi64((const __m128i *)&xmmword_30D0);\n v66 = _mm_unpacklo_epi8(\n (__m128i)(unsigned long long)v63,\n _mm_cmpgt_epi8((__m128i)0LL, (__m128i)(unsigned long long)v63));\n v67 = _mm_shuffle_epi32(v66, 78);\n v68 = _mm_unpacklo_epi16(v66, _mm_cmpgt_epi16((__m128i)0LL, v66));\n v69 = _mm_add_epi32(v68, v65);\n v70 = _mm_unpacklo_epi16(v67, _mm_cmpgt_epi16((__m128i)0LL, v67));\n v71 = _mm_add_epi32(_mm_shuffle_epi32(v68, 78), v65);\n v72 = _mm_shuffle_epi32(v70, 78);\n v73 = _mm_add_epi32(v70, v65);\n v74 = _mm_add_epi32(v72, v65);\n v75 = _mm_loadl_epi64((const __m128i *)&xmmword_30E0);\n v76 = _mm_and_si128(_mm_cmpgt_epi32((__m128i)0LL, v69), v75);\n v77 = _mm_and_si128(_mm_cmpgt_epi32((__m128i)0LL, v71), v75);\n v78 = _mm_and_si128(_mm_cmpgt_epi32((__m128i)0LL, v73), v75);\n v79 = _mm_and_si128(_mm_cmpgt_epi32((__m128i)0LL, v74), v75);\n v80 = _mm_unpacklo_epi16(\n _mm_cmpeq_epi32(\n _mm_sub_epi32(_mm_and_si128(_mm_add_epi32(v69, v76), v75), v76),\n v75),\n _mm_cmpeq_epi32(\n _mm_sub_epi32(_mm_and_si128(_mm_add_epi32(v71, v77), v75), v77),\n v75));\n v81 = _mm_and_si128(\n _mm_unpacklo_epi16(v80, _mm_shuffle_epi32(v80, 78)),\n _mm_cmpeq_epi16(\n _mm_cmpeq_epi16(\n _mm_and_si128(\n (__m128i)(\n v16[(char)v63] |\n ((v16[SBYTE1(v63)] |\n ((v16[(char)((uint32_t)v63 << 8 >> 24)] |\n ((unsigned long long)v16[SBYTE3(v63)] << 16))\n << 16))\n << 16)),\n v64),\n (__m128i)0LL),\n (__m128i)0LL));\n v82 = _mm_unpacklo_epi16(\n _mm_cmpeq_epi32(\n _mm_sub_epi32(_mm_and_si128(_mm_add_epi32(v73, v78), v75), v78),\n v75),\n _mm_cmpeq_epi32(\n _mm_sub_epi32(_mm_and_si128(_mm_add_epi32(v74, v79), v75), v79),\n v75));\n v83 = _mm_and_si128(\n _mm_unpacklo_epi16(v82, _mm_shuffle_epi32(v82, 78)),\n _mm_cmpeq_epi16(\n _mm_cmpeq_epi16(\n _mm_and_si128(\n v64, (__m128i)(\n v16[v63 << 24 >> 56] |\n ((v16[v63 << 16 >> 56] |\n ((v16[v63 << 8 >> 56] |\n ((unsigned long long)v16[v63 >> 56] << 16))\n << 16))\n << 16))),\n (__m128i)0LL),\n (__m128i)0LL));\n v84 = _mm_unpacklo_epi16(v81, _mm_cmpgt_epi16((__m128i)0LL, v81));\n v85 = _mm_unpacklo_epi16(v83, _mm_cmpgt_epi16((__m128i)0LL, v83));\n v86 = _mm_sub_epi32(\n _mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(v61, v84),\n _mm_shuffle_epi32(v84, 78)),\n v85),\n _mm_shuffle_epi32(v85, 78));\n v15 = _mm_cvtsi128_si32(_mm_shuffle_epi32(v86, 229)) +\n _mm_cvtsi128_si32(v86);\n v60 += v62 & 4294967288;\n if ((v62 & 7) != 0) {\n LABEL_19:\n v87 = s->m128i_i8[v60];\n if ((v16[v87] & 512) != 0) v15 += ((int)v87 - 97) % 2 == 1;\n if ((int)(v60 + 1) < v4) {\n v88 = s->m128i_i8[v60 + 1];\n if ((v16[v88] & 512) != 0) v15 += ((int)v88 - 97) % 2 == 1;\n if (v4 > (int)(v60 + 2)) {\n v89 = s->m128i_i8[v60 + 2];\n if ((v16[v89] & 512) != 0) v15 += ((int)v89 - 97) % 2 == 1;\n if (v4 > (int)(v60 + 3)) {\n v90 = s->m128i_i8[v60 + 3];\n if ((v16[v90] & 512) != 0) v15 += ((int)v90 - 97) % 2 == 1;\n if (v4 > (int)(v60 + 4)) {\n v91 = s->m128i_i8[v60 + 4];\n if ((v16[v91] & 512) != 0) v15 += ((int)v91 - 97) % 2 == 1;\n if (v4 > (int)(v60 + 5)) {\n v92 = s->m128i_i8[v60 + 5];\n if ((v16[v92] & 512) != 0) v15 += ((int)v92 - 97) % 2 == 1;\n v93 = v60 + 6;\n if (v4 > v93) {\n v94 = s->m128i_i8[v93];\n if ((v16[v94] & 512) != 0)\n v15 += ((char)v94 - 97) % 2 == 1;\n }\n }\n }\n }\n }\n }\n }\n }\n }\n v5 = malloc(8uLL);\n v95 = malloc(12uLL);\n v96 = v15;\n *v5 = v95;\n v6 = 1;\n __sprintf_chk(v95, 2LL, 12LL, &unk_3004, v96, v97, v98.m128i_i64[0],\n v98.m128i_i64[1], v99.m128i_i64[0], v99.m128i_i64[1],\n v100.m128i_i64[0], v100.m128i_i64[1], v101.m128i_i64[0],\n v101.m128i_i64[1], v102.m128i_i64[0], v102.m128i_i64[1],\n v103.m128i_i64[0], v103.m128i_i64[1], v104.m128i_i64[0],\n v104.m128i_i64[1], v105.m128i_i64[0], v105.m128i_i64[1],\n v106.m128i_i64[0], v106.m128i_i64[1], v107.m128i_i64[0],\n v107.m128i_i64[1], v108.m128i_i64[0], v108.m128i_i64[1],\n v109.m128i_i64[0], v109.m128i_i64[1], v110.m128i_i64[0],\n v110.m128i_i64[1], v111.m128i_i64[0], v111.m128i_i64[1],\n v112.m128i_i64[0], v112.m128i_i64[1], *(uint64_t *)sa,\n *(uint64_t *)&sa[8], v114, *((uint64_t *)&v114 + 1), v115,\n *((uint64_t *)&v115 + 1), v116, *((uint64_t *)&v116 + 1),\n v117, *((uint64_t *)&v117 + 1), v118[0], v118[1], v118[2],\n v119);\n goto LABEL_10;\n }\n v5 = malloc(8LL * (v4 + 1));\n if (v4 < 0) {\n v6 = 0;\n } else {\n v6 = 0;\n v7 = 0;\n v8 = 17596481011713LL;\n v9 = &s->m128i_i8[v4 + 1];\n do {\n while (1) {\n v12 = (unsigned char)*v3;\n if ((unsigned char)v12 <= 44u) {\n if (_bittest64(&v8, v12)) break;\n }\n v13 = v7;\n ++v3;\n ++v7;\n sa[v13] = v12;\n if (v9 == v3) goto LABEL_10;\n }\n if (v7 > 0) {\n sa[v7] = 0;\n v10 = strdup(sa);\n v11 = v6++;\n v5[v11] = v10;\n v7 = 0;\n }\n ++v3;\n } while (v9 != v3);\n }\nLABEL_10:\n *a2 = v6;\n return v5;\n}" + }, + { + "index": "HumanEval-C-126", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "bool func0(const int *lst, int lst_size) {\n if (lst_size == 0) return true;\n for (int i = 1; i < lst_size; i++) {\n if (lst[i] < lst[i - 1]) return false;\n if (i >= 2 && lst[i] == lst[i - 1] && lst[i] == lst[i - 2]) return false;\n }\n return true;\n}", + "test": "#include \n#include \n#include \n\nint main() {\n int list1[] = {5};\n assert(func0(list1, 1) == true);\n\n int list2[] = {1, 2, 3, 4, 5};\n assert(func0(list2, 5) == true);\n\n int list3[] = {1, 3, 2, 4, 5};\n assert(func0(list3, 5) == false);\n\n int list4[] = {1, 2, 3, 4, 5, 6};\n assert(func0(list4, 6) == true);\n\n int list5[] = {1, 2, 3, 4, 5, 6, 7};\n assert(func0(list5, 7) == true);\n\n int list6[] = {1, 3, 2, 4, 5, 6, 7};\n assert(func0(list6, 7) == false);\n\n assert(func0(NULL, 0) == true);\n\n int list7[] = {1};\n assert(func0(list7, 1) == true);\n\n int list8[] = {3, 2, 1};\n assert(func0(list8, 3) == false);\n\n int list9[] = {1, 2, 2, 2, 3, 4};\n assert(func0(list9, 6) == false);\n\n int list10[] = {1, 2, 3, 3, 3, 4};\n assert(func0(list10, 6) == false);\n\n int list11[] = {1, 2, 2, 3, 3, 4};\n assert(func0(list11, 6) == true);\n\n int list12[] = {1, 2, 3, 4};\n assert(func0(list12, 4) == true);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\ncmp [rbp+var_1C], 0\njnz short loc_1188\nmov eax, 1\njmp loc_1250\nloc_1188:\nmov [rbp+var_4], 1\njmp loc_123F\nloc_1194:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nshl rax, 2\nlea rcx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njge short loc_11CE\nmov eax, 0\njmp loc_1250\nloc_11CE:\ncmp [rbp+var_4], 1\njle short loc_123B\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nshl rax, 2\nlea rcx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_123B\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nshl rax, 2\nlea rcx, [rax-8]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_123B\nmov eax, 0\njmp short loc_1250\nloc_123B:\nadd [rbp+var_4], 1\nloc_123F:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl loc_1194\nmov eax, 1\nloc_1250:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-4h]\n\n if ( !a2 )\n return 1LL;\n for ( i = 1; i < a2; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) < *(_DWORD *)(4LL * i - 4 + a1) )\n return 0LL;\n if ( i > 1\n && *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4LL * i - 4 + a1)\n && *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4LL * i - 8 + a1) )\n {\n return 0LL;\n }\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\ncmp [rbp+var_1C], 0\njnz short loc_1188\nmov eax, 1\njmp loc_1250\nloc_1188:\nmov [rbp+var_4], 1\njmp loc_123F\nloc_1194:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nshl rax, 2\nlea rcx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njge short loc_11CE\nmov eax, 0\njmp loc_1250\nloc_11CE:\ncmp [rbp+var_4], 1\njle short loc_123B\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nshl rax, 2\nlea rcx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_123B\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nshl rax, 2\nlea rcx, [rax-8]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_123B\nmov eax, 0\njmp short loc_1250\nloc_123B:\nadd [rbp+var_4], 1\nloc_123F:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl loc_1194\nmov eax, 1\nloc_1250:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-4h]\n\n if ( !a2 )\n return 1LL;\n for ( i = 1; i < a2; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) < *(_DWORD *)(4LL * i - 4 + a1) )\n return 0LL;\n if ( i > 1\n && *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4LL * i - 4 + a1)\n && *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4LL * i - 8 + a1) )\n {\n return 0LL;\n }\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int i;\n if (!a2) return 1LL;\n for (i = 1; i < a2; ++i) {\n if (*(uint32_t *)(4LL * i + a1) < *(uint32_t *)(4LL * i - 4 + a1))\n return 0LL;\n if (i > 1 &&\n *(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4LL * i - 4 + a1) &&\n *(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4LL * i - 8 + a1)) {\n return 0LL;\n }\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int i;\n if (!a2) return 1LL;\n for (i = 1; i < a2; ++i) {\n if (*(uint32_t *)(4LL * i + a1) < *(uint32_t *)(4LL * i - 4 + a1))\n return 0LL;\n if (i > 1 &&\n *(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4LL * i - 4 + a1) &&\n *(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4LL * i - 8 + a1)) {\n return 0LL;\n }\n }\n return 1LL;\n}" + }, + { + "index": "HumanEval-C-126", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "bool func0(const int *lst, int lst_size) {\n if (lst_size == 0) return true;\n for (int i = 1; i < lst_size; i++) {\n if (lst[i] < lst[i - 1]) return false;\n if (i >= 2 && lst[i] == lst[i - 1] && lst[i] == lst[i - 2]) return false;\n }\n return true;\n}", + "test": "#include \n#include \n#include \n\nint main() {\n int list1[] = {5};\n assert(func0(list1, 1) == true);\n\n int list2[] = {1, 2, 3, 4, 5};\n assert(func0(list2, 5) == true);\n\n int list3[] = {1, 3, 2, 4, 5};\n assert(func0(list3, 5) == false);\n\n int list4[] = {1, 2, 3, 4, 5, 6};\n assert(func0(list4, 6) == true);\n\n int list5[] = {1, 2, 3, 4, 5, 6, 7};\n assert(func0(list5, 7) == true);\n\n int list6[] = {1, 3, 2, 4, 5, 6, 7};\n assert(func0(list6, 7) == false);\n\n assert(func0(NULL, 0) == true);\n\n int list7[] = {1};\n assert(func0(list7, 1) == true);\n\n int list8[] = {3, 2, 1};\n assert(func0(list8, 3) == false);\n\n int list9[] = {1, 2, 2, 2, 3, 4};\n assert(func0(list9, 6) == false);\n\n int list10[] = {1, 2, 3, 3, 3, 4};\n assert(func0(list10, 6) == false);\n\n int list11[] = {1, 2, 2, 3, 3, 4};\n assert(func0(list11, 6) == true);\n\n int list12[] = {1, 2, 3, 4};\n assert(func0(list12, 4) == true);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmov eax, 1\ncmp esi, 1\njle short locret_11A6\nmov esi, esi\nmov eax, 1\njmp short loc_1189\nloc_1180:\nadd rax, 1\ncmp rax, rsi\njz short loc_11A7\nloc_1189:\nmov edx, [rdi+rax*4]\nmov ecx, [rdi+rax*4-4]\ncmp edx, ecx\njl short loc_11AD\njnz short loc_1180\ncmp eax, 1\njle short loc_1180\ncmp edx, [rdi+rax*4-8]\njnz short loc_1180\nmov eax, 0\nlocret_11A6:\nretn\nloc_11A7:\nmov eax, 1\nretn\nloc_11AD:\nmov eax, 0\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 result; // rax\n __int64 v3; // rax\n int v4; // edx\n int v5; // ecx\n\n result = 1LL;\n if ( a2 > 1 )\n {\n v3 = 1LL;\n while ( 1 )\n {\n v4 = *(_DWORD *)(a1 + 4 * v3);\n v5 = *(_DWORD *)(a1 + 4 * v3 - 4);\n if ( v4 < v5 )\n break;\n if ( v4 == v5 && (int)v3 > 1 && v4 == *(_DWORD *)(a1 + 4 * v3 - 8) )\n return 0LL;\n if ( ++v3 == a2 )\n return 1LL;\n }\n return 0LL;\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov eax, 1\ncmp esi, 1\njle short locret_11A6\nmov esi, esi\nmov eax, 1\njmp short loc_1189\nloc_1180:\nadd rax, 1\ncmp rax, rsi\njz short loc_11A7\nloc_1189:\nmov edx, [rdi+rax*4]\nmov ecx, [rdi+rax*4-4]\ncmp edx, ecx\njl short loc_11AD\njnz short loc_1180\ncmp eax, 1\njle short loc_1180\ncmp edx, [rdi+rax*4-8]\njnz short loc_1180\nmov eax, 0\nlocret_11A6:\nretn\nloc_11A7:\nmov eax, 1\nretn\nloc_11AD:\nmov eax, 0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n __int64 result; // rax\n __int64 v3; // rax\n int v4; // edx\n int v5; // ecx\n\n result = 1LL;\n if ( a2 > 1 )\n {\n v3 = 1LL;\n while ( 1 )\n {\n v4 = *(_DWORD *)(a1 + 4 * v3);\n v5 = *(_DWORD *)(a1 + 4 * v3 - 4);\n if ( v4 < v5 )\n break;\n if ( v4 == v5 && (int)v3 > 1 && v4 == *(_DWORD *)(a1 + 4 * v3 - 8) )\n return 0LL;\n if ( ++v3 == a2 )\n return 1LL;\n }\n return 0LL;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n long long result;\n long long v3;\n int v4;\n int v5;\n result = 1LL;\n if (a2 > 1) {\n v3 = 1LL;\n while (1) {\n v4 = *(uint32_t *)(a1 + 4 * v3);\n v5 = *(uint32_t *)(a1 + 4 * v3 - 4);\n if (v4 < v5) break;\n if (v4 == v5 && (int)v3 > 1 && v4 == *(uint32_t *)(a1 + 4 * v3 - 8))\n return 0LL;\n if (++v3 == a2) return 1LL;\n }\n return 0LL;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long result;\n long long v3;\n int v4;\n int v5;\n result = 1LL;\n if (a2 > 1) {\n v3 = 1LL;\n while (1) {\n v4 = *(uint32_t *)(a1 + 4 * v3);\n v5 = *(uint32_t *)(a1 + 4 * v3 - 4);\n if (v4 < v5) break;\n if (v4 == v5 && (int)v3 > 1 && v4 == *(uint32_t *)(a1 + 4 * v3 - 8))\n return 0LL;\n if (++v3 == a2) return 1LL;\n }\n return 0LL;\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-126", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "bool func0(const int *lst, int lst_size) {\n if (lst_size == 0) return true;\n for (int i = 1; i < lst_size; i++) {\n if (lst[i] < lst[i - 1]) return false;\n if (i >= 2 && lst[i] == lst[i - 1] && lst[i] == lst[i - 2]) return false;\n }\n return true;\n}", + "test": "#include \n#include \n#include \n\nint main() {\n int list1[] = {5};\n assert(func0(list1, 1) == true);\n\n int list2[] = {1, 2, 3, 4, 5};\n assert(func0(list2, 5) == true);\n\n int list3[] = {1, 3, 2, 4, 5};\n assert(func0(list3, 5) == false);\n\n int list4[] = {1, 2, 3, 4, 5, 6};\n assert(func0(list4, 6) == true);\n\n int list5[] = {1, 2, 3, 4, 5, 6, 7};\n assert(func0(list5, 7) == true);\n\n int list6[] = {1, 3, 2, 4, 5, 6, 7};\n assert(func0(list6, 7) == false);\n\n assert(func0(NULL, 0) == true);\n\n int list7[] = {1};\n assert(func0(list7, 1) == true);\n\n int list8[] = {3, 2, 1};\n assert(func0(list8, 3) == false);\n\n int list9[] = {1, 2, 2, 2, 3, 4};\n assert(func0(list9, 6) == false);\n\n int list10[] = {1, 2, 3, 3, 3, 4};\n assert(func0(list10, 6) == false);\n\n int list11[] = {1, 2, 2, 3, 3, 4};\n assert(func0(list11, 6) == true);\n\n int list12[] = {1, 2, 3, 4};\n assert(func0(list12, 4) == true);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0_part_0:\ncmp esi, 1\njle short loc_1568\nmov esi, esi\nmov eax, 1\njmp short loc_1549\nloc_1540:\nadd rax, 1\ncmp rsi, rax\njz short loc_1568\nloc_1549:\nmov edx, [rdi+rax*4]\ncmp edx, [rdi+rax*4-4]\njl short loc_155F\njnz short loc_1540\ncmp eax, 1\njz short loc_1540\ncmp edx, [rdi+rax*4-8]\njnz short loc_1540\nloc_155F:\nxor eax, eax\nretn\nloc_1568:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0_part_0(__int64 a1, int a2)\n{\n __int64 v2; // rax\n int v3; // edx\n\n if ( a2 <= 1 )\n return 1LL;\n v2 = 1LL;\n while ( 1 )\n {\n v3 = *(_DWORD *)(a1 + 4 * v2);\n if ( v3 < *(_DWORD *)(a1 + 4 * v2 - 4)\n || v3 == *(_DWORD *)(a1 + 4 * v2 - 4) && (_DWORD)v2 != 1 && v3 == *(_DWORD *)(a1 + 4 * v2 - 8) )\n {\n break;\n }\n if ( a2 == ++v2 )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1530:\ncmp esi, 1\njle short loc_1568\nmov esi, esi\nmov eax, 1\njmp short loc_1549\nloc_1540:\nadd rax, 1\ncmp rsi, rax\njz short loc_1568\nloc_1549:\nmov edx, [rdi+rax*4]\ncmp edx, [rdi+rax*4-4]\njl short loc_155F\njnz short loc_1540\ncmp eax, 1\njz short loc_1540\ncmp edx, [rdi+rax*4-8]\njnz short loc_1540\nloc_155F:\nxor eax, eax\nretn\nloc_1568:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1530(__int64 a1, int a2)\n{\n __int64 v2; // rax\n int v3; // edx\n\n if ( a2 <= 1 )\n return 1LL;\n v2 = 1LL;\n while ( 1 )\n {\n v3 = *(_DWORD *)(a1 + 4 * v2);\n if ( v3 < *(_DWORD *)(a1 + 4 * v2 - 4)\n || v3 == *(_DWORD *)(a1 + 4 * v2 - 4) && (_DWORD)v2 != 1 && v3 == *(_DWORD *)(a1 + 4 * v2 - 8) )\n {\n break;\n }\n if ( a2 == ++v2 )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1530(long long a1, int a2) {\n long long v2;\n int v3;\n if (a2 <= 1) return 1LL;\n v2 = 1LL;\n while (1) {\n v3 = *(uint32_t *)(a1 + 4 * v2);\n if (v3 < *(uint32_t *)(a1 + 4 * v2 - 4) ||\n v3 == *(uint32_t *)(a1 + 4 * v2 - 4) && (uint32_t)v2 != 1 &&\n v3 == *(uint32_t *)(a1 + 4 * v2 - 8)) {\n break;\n }\n if (a2 == ++v2) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0_part_0(long long a1, int a2) {\n long long v2;\n int v3;\n if (a2 <= 1) return 1LL;\n v2 = 1LL;\n while (1) {\n v3 = *(uint32_t *)(a1 + 4 * v2);\n if (v3 < *(uint32_t *)(a1 + 4 * v2 - 4) ||\n v3 == *(uint32_t *)(a1 + 4 * v2 - 4) && (uint32_t)v2 != 1 &&\n v3 == *(uint32_t *)(a1 + 4 * v2 - 8)) {\n break;\n }\n if (a2 == ++v2) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": "HumanEval-C-126", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "bool func0(const int *lst, int lst_size) {\n if (lst_size == 0) return true;\n for (int i = 1; i < lst_size; i++) {\n if (lst[i] < lst[i - 1]) return false;\n if (i >= 2 && lst[i] == lst[i - 1] && lst[i] == lst[i - 2]) return false;\n }\n return true;\n}", + "test": "#include \n#include \n#include \n\nint main() {\n int list1[] = {5};\n assert(func0(list1, 1) == true);\n\n int list2[] = {1, 2, 3, 4, 5};\n assert(func0(list2, 5) == true);\n\n int list3[] = {1, 3, 2, 4, 5};\n assert(func0(list3, 5) == false);\n\n int list4[] = {1, 2, 3, 4, 5, 6};\n assert(func0(list4, 6) == true);\n\n int list5[] = {1, 2, 3, 4, 5, 6, 7};\n assert(func0(list5, 7) == true);\n\n int list6[] = {1, 3, 2, 4, 5, 6, 7};\n assert(func0(list6, 7) == false);\n\n assert(func0(NULL, 0) == true);\n\n int list7[] = {1};\n assert(func0(list7, 1) == true);\n\n int list8[] = {3, 2, 1};\n assert(func0(list8, 3) == false);\n\n int list9[] = {1, 2, 2, 2, 3, 4};\n assert(func0(list9, 6) == false);\n\n int list10[] = {1, 2, 3, 3, 3, 4};\n assert(func0(list10, 6) == false);\n\n int list11[] = {1, 2, 2, 3, 3, 4};\n assert(func0(list11, 6) == true);\n\n int list12[] = {1, 2, 3, 4};\n assert(func0(list12, 4) == true);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0_part_0:\ncmp esi, 1\njle short loc_1568\nmov esi, esi\nmov eax, 1\njmp short loc_1549\nloc_1540:\nadd rax, 1\ncmp rsi, rax\njz short loc_1568\nloc_1549:\nmov edx, [rdi+rax*4]\ncmp edx, [rdi+rax*4-4]\njl short loc_155F\njnz short loc_1540\ncmp eax, 1\njz short loc_1540\ncmp edx, [rdi+rax*4-8]\njnz short loc_1540\nloc_155F:\nxor eax, eax\nretn\nloc_1568:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0_part_0(__int64 a1, int a2)\n{\n __int64 v2; // rax\n int v3; // edx\n\n if ( a2 <= 1 )\n return 1LL;\n v2 = 1LL;\n while ( 1 )\n {\n v3 = *(_DWORD *)(a1 + 4 * v2);\n if ( v3 < *(_DWORD *)(a1 + 4 * v2 - 4)\n || v3 == *(_DWORD *)(a1 + 4 * v2 - 4) && (_DWORD)v2 != 1 && v3 == *(_DWORD *)(a1 + 4 * v2 - 8) )\n {\n break;\n }\n if ( a2 == ++v2 )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1530:\ncmp esi, 1\njle short loc_1568\nmov esi, esi\nmov eax, 1\njmp short loc_1549\nloc_1540:\nadd rax, 1\ncmp rsi, rax\njz short loc_1568\nloc_1549:\nmov edx, [rdi+rax*4]\ncmp edx, [rdi+rax*4-4]\njl short loc_155F\njnz short loc_1540\ncmp eax, 1\njz short loc_1540\ncmp edx, [rdi+rax*4-8]\njnz short loc_1540\nloc_155F:\nxor eax, eax\nretn\nloc_1568:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1530(__int64 a1, int a2)\n{\n __int64 v2; // rax\n int v3; // edx\n\n if ( a2 <= 1 )\n return 1LL;\n v2 = 1LL;\n while ( 1 )\n {\n v3 = *(_DWORD *)(a1 + 4 * v2);\n if ( v3 < *(_DWORD *)(a1 + 4 * v2 - 4)\n || v3 == *(_DWORD *)(a1 + 4 * v2 - 4) && (_DWORD)v2 != 1 && v3 == *(_DWORD *)(a1 + 4 * v2 - 8) )\n {\n break;\n }\n if ( a2 == ++v2 )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1530(long long a1, int a2) {\n long long v2;\n int v3;\n if (a2 <= 1) return 1LL;\n v2 = 1LL;\n while (1) {\n v3 = *(uint32_t *)(a1 + 4 * v2);\n if (v3 < *(uint32_t *)(a1 + 4 * v2 - 4) ||\n v3 == *(uint32_t *)(a1 + 4 * v2 - 4) && (uint32_t)v2 != 1 &&\n v3 == *(uint32_t *)(a1 + 4 * v2 - 8)) {\n break;\n }\n if (a2 == ++v2) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0_part_0(long long a1, int a2) {\n long long v2;\n int v3;\n if (a2 <= 1) return 1LL;\n v2 = 1LL;\n while (1) {\n v3 = *(uint32_t *)(a1 + 4 * v2);\n if (v3 < *(uint32_t *)(a1 + 4 * v2 - 4) ||\n v3 == *(uint32_t *)(a1 + 4 * v2 - 4) && (uint32_t)v2 != 1 &&\n v3 == *(uint32_t *)(a1 + 4 * v2 - 8)) {\n break;\n }\n if (a2 == ++v2) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": "HumanEval-C-127", + "func_name": "func0", + "func_dep": "#include \n", + "func": "const char* func0(int interval1_start, int interval1_end, int interval2_start,\n int interval2_end) {\n int inter1, inter2, l, i;\n inter1 =\n interval1_start > interval2_start ? interval1_start : interval2_start;\n inter2 = interval1_end < interval2_end ? interval1_end : interval2_end;\n l = inter2 - inter1;\n if (l < 2) return \"NO\";\n for (i = 2; i * i <= l; i++)\n if (l % i == 0) return \"NO\";\n return \"YES\";\n}", + "test": "#include \n#include \n#include \n\nint main() {\n assert(strcmp(func0(1, 2, 2, 3), \"NO\") == 0);\n assert(strcmp(func0(-1, 1, 0, 4), \"NO\") == 0);\n assert(strcmp(func0(-3, -1, -5, 5), \"YES\") == 0);\n assert(strcmp(func0(-2, 2, -4, 0), \"YES\") == 0);\n assert(strcmp(func0(-11, 2, -1, -1), \"NO\") == 0);\n assert(strcmp(func0(1, 2, 3, 5), \"NO\") == 0);\n assert(strcmp(func0(1, 2, 1, 2), \"NO\") == 0);\n assert(strcmp(func0(-2, -2, -3, -2), \"NO\") == 0);\n \n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov [rbp+var_20], ecx\nmov edx, [rbp+var_1C]\nmov eax, [rbp+var_14]\ncmp edx, eax\ncmovge eax, edx\nmov [rbp+var_C], eax\nmov edx, [rbp+var_20]\nmov eax, [rbp+var_18]\ncmp edx, eax\ncmovle eax, edx\nmov [rbp+var_8], eax\nmov eax, [rbp+var_8]\nsub eax, [rbp+var_C]\nmov [rbp+var_4], eax\ncmp [rbp+var_4], 1\njg short loc_11B1\nlea rax, s2; \"NO\"\njmp short loc_11E6\nloc_11B1:\nmov [rbp+var_10], 2\njmp short loc_11D4\nloc_11BA:\nmov eax, [rbp+var_4]\ncdq\nidiv [rbp+var_10]\nmov eax, edx\ntest eax, eax\njnz short loc_11D0\nlea rax, s2; \"NO\"\njmp short loc_11E6\nloc_11D0:\nadd [rbp+var_10], 1\nloc_11D4:\nmov eax, [rbp+var_10]\nimul eax, eax\ncmp [rbp+var_4], eax\njge short loc_11BA\nlea rax, aYes; \"YES\"\nloc_11E6:\npop rbp\nretn", + "ida_pseudo": "const char *__fastcall func0(int a1, int a2, int a3, int a4)\n{\n int v4; // eax\n int v5; // eax\n int i; // [rsp+10h] [rbp-10h]\n int v8; // [rsp+14h] [rbp-Ch]\n int v9; // [rsp+1Ch] [rbp-4h]\n\n v4 = a1;\n if ( a3 >= a1 )\n v4 = a3;\n v8 = v4;\n v5 = a2;\n if ( a4 <= a2 )\n v5 = a4;\n v9 = v5 - v8;\n if ( v5 - v8 <= 1 )\n return \"NO\";\n for ( i = 2; v9 >= i * i; ++i )\n {\n if ( !(v9 % i) )\n return \"NO\";\n }\n return \"YES\";\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov [rbp+var_20], ecx\nmov edx, [rbp+var_1C]\nmov eax, [rbp+var_14]\ncmp edx, eax\ncmovge eax, edx\nmov [rbp+var_C], eax\nmov edx, [rbp+var_20]\nmov eax, [rbp+var_18]\ncmp edx, eax\ncmovle eax, edx\nmov [rbp+var_8], eax\nmov eax, [rbp+var_8]\nsub eax, [rbp+var_C]\nmov [rbp+var_4], eax\ncmp [rbp+var_4], 1\njg short loc_11B1\nlea rax, s2; \"NO\"\njmp short loc_11E6\nloc_11B1:\nmov [rbp+var_10], 2\njmp short loc_11D4\nloc_11BA:\nmov eax, [rbp+var_4]\ncdq\nidiv [rbp+var_10]\nmov eax, edx\ntest eax, eax\njnz short loc_11D0\nlea rax, s2; \"NO\"\njmp short loc_11E6\nloc_11D0:\nadd [rbp+var_10], 1\nloc_11D4:\nmov eax, [rbp+var_10]\nimul eax, eax\ncmp [rbp+var_4], eax\njge short loc_11BA\nlea rax, aYes; \"YES\"\nloc_11E6:\npop rbp\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1169(int a1, int a2, int a3, int a4)\n{\n int v4; // eax\n int v5; // eax\n int i; // [rsp+10h] [rbp-10h]\n int v8; // [rsp+14h] [rbp-Ch]\n int v9; // [rsp+1Ch] [rbp-4h]\n\n v4 = a1;\n if ( a3 >= a1 )\n v4 = a3;\n v8 = v4;\n v5 = a2;\n if ( a4 <= a2 )\n v5 = a4;\n v9 = v5 - v8;\n if ( v5 - v8 <= 1 )\n return \"NO\";\n for ( i = 2; v9 >= i * i; ++i )\n {\n if ( !(v9 % i) )\n return \"NO\";\n }\n return \"YES\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char* sub_1169(int a1, int a2, int a3, int a4) {\n int v4;\n int v5;\n int i;\n int v8;\n int v9;\n v4 = a1;\n if (a3 >= a1) v4 = a3;\n v8 = v4;\n v5 = a2;\n if (a4 <= a2) v5 = a4;\n v9 = v5 - v8;\n if (v5 - v8 <= 1) return \"NO\";\n for (i = 2; v9 >= i * i; ++i) {\n if (!(v9 % i)) return \"NO\";\n }\n return \"YES\";\n}", + "ida_pseudo_norm": "const char* func0(int a1, int a2, int a3, int a4) {\n int v4;\n int v5;\n int i;\n int v8;\n int v9;\n v4 = a1;\n if (a3 >= a1) v4 = a3;\n v8 = v4;\n v5 = a2;\n if (a4 <= a2) v5 = a4;\n v9 = v5 - v8;\n if (v5 - v8 <= 1) return \"NO\";\n for (i = 2; v9 >= i * i; ++i) {\n if (!(v9 % i)) return \"NO\";\n }\n return \"YES\";\n}" + }, + { + "index": "HumanEval-C-127", + "func_name": "func0", + "func_dep": "#include \n", + "func": "const char* func0(int interval1_start, int interval1_end, int interval2_start,\n int interval2_end) {\n int inter1, inter2, l, i;\n inter1 =\n interval1_start > interval2_start ? interval1_start : interval2_start;\n inter2 = interval1_end < interval2_end ? interval1_end : interval2_end;\n l = inter2 - inter1;\n if (l < 2) return \"NO\";\n for (i = 2; i * i <= l; i++)\n if (l % i == 0) return \"NO\";\n return \"YES\";\n}", + "test": "#include \n#include \n#include \n\nint main() {\n assert(strcmp(func0(1, 2, 2, 3), \"NO\") == 0);\n assert(strcmp(func0(-1, 1, 0, 4), \"NO\") == 0);\n assert(strcmp(func0(-3, -1, -5, 5), \"YES\") == 0);\n assert(strcmp(func0(-2, 2, -4, 0), \"YES\") == 0);\n assert(strcmp(func0(-11, 2, -1, -1), \"NO\") == 0);\n assert(strcmp(func0(1, 2, 3, 5), \"NO\") == 0);\n assert(strcmp(func0(1, 2, 1, 2), \"NO\") == 0);\n assert(strcmp(func0(-2, -2, -3, -2), \"NO\") == 0);\n \n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ncmp ecx, esi\ncmovg ecx, esi\ncmp edx, edi\ncmovl edx, edi\nsub ecx, edx\nlea rax, s2; \"NO\"\ncmp ecx, 1\njle short locret_11BE\nlea rax, aYes; \"YES\"\ncmp ecx, 3\njle short locret_11BE\nlea rax, s2; \"NO\"\ntest cl, 1\njz short locret_11BE\nmov esi, 2\nloc_11A2:\nadd esi, 1\nmov eax, esi\nimul eax, esi\ncmp eax, ecx\njg short loc_11BF\nmov eax, ecx\ncdq\nidiv esi\ntest edx, edx\njnz short loc_11A2\nlea rax, s2; \"NO\"\nlocret_11BE:\nretn\nloc_11BF:\nlea rax, aYes; \"YES\"\nretn", + "ida_pseudo": "const char *__fastcall func0(int a1, int a2, int a3, int a4)\n{\n int v4; // ecx\n const char *result; // rax\n int v6; // esi\n\n if ( a4 > a2 )\n a4 = a2;\n if ( a3 < a1 )\n a3 = a1;\n v4 = a4 - a3;\n result = \"NO\";\n if ( v4 > 1 )\n {\n result = \"YES\";\n if ( v4 > 3 )\n {\n result = \"NO\";\n if ( (v4 & 1) != 0 )\n {\n v6 = 2;\n while ( 1 )\n {\n ++v6;\n if ( v6 * v6 > v4 )\n break;\n if ( !(v4 % v6) )\n return \"NO\";\n }\n return \"YES\";\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ncmp ecx, esi\ncmovg ecx, esi\ncmp edx, edi\ncmovl edx, edi\nsub ecx, edx\nlea rax, s2; \"NO\"\ncmp ecx, 1\njle short locret_11BE\nlea rax, aYes; \"YES\"\ncmp ecx, 3\njle short locret_11BE\nlea rax, s2; \"NO\"\ntest cl, 1\njz short locret_11BE\nmov esi, 2\nloc_11A2:\nadd esi, 1\nmov eax, esi\nimul eax, esi\ncmp eax, ecx\njg short loc_11BF\nmov eax, ecx\ncdq\nidiv esi\ntest edx, edx\njnz short loc_11A2\nlea rax, s2; \"NO\"\nlocret_11BE:\nretn\nloc_11BF:\nlea rax, aYes; \"YES\"\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1169(int a1, int a2, int a3, int a4)\n{\n int v4; // ecx\n const char *result; // rax\n int v6; // esi\n\n if ( a4 > a2 )\n a4 = a2;\n if ( a3 < a1 )\n a3 = a1;\n v4 = a4 - a3;\n result = \"NO\";\n if ( v4 > 1 )\n {\n result = \"YES\";\n if ( v4 > 3 )\n {\n result = \"NO\";\n if ( (v4 & 1) != 0 )\n {\n v6 = 2;\n while ( 1 )\n {\n ++v6;\n if ( v6 * v6 > v4 )\n break;\n if ( !(v4 % v6) )\n return \"NO\";\n }\n return \"YES\";\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1169(int a1, int a2, int a3, int a4) {\n int v4;\n const char *result;\n int v6;\n if (a4 > a2) a4 = a2;\n if (a3 < a1) a3 = a1;\n v4 = a4 - a3;\n result = \"NO\";\n if (v4 > 1) {\n result = \"YES\";\n if (v4 > 3) {\n result = \"NO\";\n if ((v4 & 1) != 0) {\n v6 = 2;\n while (1) {\n ++v6;\n if (v6 * v6 > v4) break;\n if (!(v4 % v6)) return \"NO\";\n }\n return \"YES\";\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(int a1, int a2, int a3, int a4) {\n int v4;\n const char *result;\n int v6;\n if (a4 > a2) a4 = a2;\n if (a3 < a1) a3 = a1;\n v4 = a4 - a3;\n result = \"NO\";\n if (v4 > 1) {\n result = \"YES\";\n if (v4 > 3) {\n result = \"NO\";\n if ((v4 & 1) != 0) {\n v6 = 2;\n while (1) {\n ++v6;\n if (v6 * v6 > v4) break;\n if (!(v4 % v6)) return \"NO\";\n }\n return \"YES\";\n }\n }\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-128", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(int *arr, int arr_size) {\n if (arr_size == 0) return -32768;\n int sum = 0, prods = 1, i;\n for (i = 0; i < arr_size; i++) {\n sum += abs(arr[i]);\n if (arr[i] == 0) prods = 0;\n if (arr[i] < 0) prods = -prods;\n }\n return sum * prods;\n}", + "test": "#include \n#include \n\nint main() {\n int arr1[] = {1, 2, 2, -4};\n assert(func0(arr1, 4) == -9);\n\n int arr2[] = {0, 1};\n assert(func0(arr2, 2) == 0);\n\n int arr3[] = {1, 1, 1, 2, 3, -1, 1};\n assert(func0(arr3, 7) == -10);\n\n assert(func0(NULL, 0) == -32768);\n\n int arr5[] = {2, 4, 1, 2, -1, -1, 9};\n assert(func0(arr5, 7) == 20);\n\n int arr6[] = {-1, 1, -1, 1};\n assert(func0(arr6, 4) == 4);\n\n int arr7[] = {-1, 1, 1, 1};\n assert(func0(arr7, 4) == -4);\n\n int arr8[] = {-1, 1, 1, 0};\n assert(func0(arr8, 4) == 0);\n \n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\ncmp [rbp+var_1C], 0\njnz short loc_1188\nmov eax, 0FFFF8000h\njmp loc_1210\nloc_1188:\nmov [rbp+var_C], 0\nmov [rbp+var_8], 1\nmov [rbp+var_4], 0\njmp short loc_1201\nloc_119F:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov edx, eax\nneg edx\ncmovns eax, edx\nadd [rbp+var_C], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njnz short loc_11E0\nmov [rbp+var_8], 0\nloc_11E0:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njns short loc_11FD\nneg [rbp+var_8]\nloc_11FD:\nadd [rbp+var_4], 1\nloc_1201:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_119F\nmov eax, [rbp+var_C]\nimul eax, [rbp+var_8]\nloc_1210:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int v3; // eax\n int v4; // [rsp+10h] [rbp-Ch]\n int v5; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n if ( !a2 )\n return 4294934528LL;\n v4 = 0;\n v5 = 1;\n for ( i = 0; i < a2; ++i )\n {\n v3 = *(_DWORD *)(4LL * i + a1);\n if ( v3 <= 0 )\n v3 = -*(_DWORD *)(4LL * i + a1);\n v4 += v3;\n if ( !*(_DWORD *)(4LL * i + a1) )\n v5 = 0;\n if ( *(int *)(4LL * i + a1) < 0 )\n v5 = -v5;\n }\n return (unsigned int)(v5 * v4);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\ncmp [rbp+var_1C], 0\njnz short loc_1188\nmov eax, 0FFFF8000h\njmp loc_1210\nloc_1188:\nmov [rbp+var_C], 0\nmov [rbp+var_8], 1\nmov [rbp+var_4], 0\njmp short loc_1201\nloc_119F:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov edx, eax\nneg edx\ncmovns eax, edx\nadd [rbp+var_C], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njnz short loc_11E0\nmov [rbp+var_8], 0\nloc_11E0:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njns short loc_11FD\nneg [rbp+var_8]\nloc_11FD:\nadd [rbp+var_4], 1\nloc_1201:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_119F\nmov eax, [rbp+var_C]\nimul eax, [rbp+var_8]\nloc_1210:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int v3; // eax\n int v4; // [rsp+10h] [rbp-Ch]\n int v5; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n if ( !a2 )\n return 4294934528LL;\n v4 = 0;\n v5 = 1;\n for ( i = 0; i < a2; ++i )\n {\n v3 = *(_DWORD *)(4LL * i + a1);\n if ( v3 <= 0 )\n v3 = -*(_DWORD *)(4LL * i + a1);\n v4 += v3;\n if ( !*(_DWORD *)(4LL * i + a1) )\n v5 = 0;\n if ( *(int *)(4LL * i + a1) < 0 )\n v5 = -v5;\n }\n return (unsigned int)(v5 * v4);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int v3;\n int v4;\n int v5;\n int i;\n if (!a2) return 4294934528LL;\n v4 = 0;\n v5 = 1;\n for (i = 0; i < a2; ++i) {\n v3 = *(uint32_t *)(4LL * i + a1);\n if (v3 <= 0) v3 = -*(uint32_t *)(4LL * i + a1);\n v4 += v3;\n if (!*(uint32_t *)(4LL * i + a1)) v5 = 0;\n if (*(int *)(4LL * i + a1) < 0) v5 = -v5;\n }\n return (unsigned int)(v5 * v4);\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int v3;\n int v4;\n int v5;\n int i;\n if (!a2) return 4294934528LL;\n v4 = 0;\n v5 = 1;\n for (i = 0; i < a2; ++i) {\n v3 = *(uint32_t *)(4LL * i + a1);\n if (v3 <= 0) v3 = -*(uint32_t *)(4LL * i + a1);\n v4 += v3;\n if (!*(uint32_t *)(4LL * i + a1)) v5 = 0;\n if (*(int *)(4LL * i + a1) < 0) v5 = -v5;\n }\n return (unsigned int)(v5 * v4);\n}" + }, + { + "index": "HumanEval-C-128", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(int *arr, int arr_size) {\n if (arr_size == 0) return -32768;\n int sum = 0, prods = 1, i;\n for (i = 0; i < arr_size; i++) {\n sum += abs(arr[i]);\n if (arr[i] == 0) prods = 0;\n if (arr[i] < 0) prods = -prods;\n }\n return sum * prods;\n}", + "test": "#include \n#include \n\nint main() {\n int arr1[] = {1, 2, 2, -4};\n assert(func0(arr1, 4) == -9);\n\n int arr2[] = {0, 1};\n assert(func0(arr2, 2) == 0);\n\n int arr3[] = {1, 1, 1, 2, 3, -1, 1};\n assert(func0(arr3, 7) == -10);\n\n assert(func0(NULL, 0) == -32768);\n\n int arr5[] = {2, 4, 1, 2, -1, -1, 9};\n assert(func0(arr5, 7) == 20);\n\n int arr6[] = {-1, 1, -1, 1};\n assert(func0(arr6, 4) == 4);\n\n int arr7[] = {-1, 1, 1, 1};\n assert(func0(arr7, 4) == -4);\n\n int arr8[] = {-1, 1, 1, 0};\n assert(func0(arr8, 4) == 0);\n \n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njz short loc_11BC\njle short loc_11AE\nmov rcx, rdi\nmovsxd rsi, esi\nlea r8, [rdi+rsi*4]\nmov edi, 1\nmov eax, 0\njmp short loc_1194\nloc_1189:\nmov edi, edx\nloc_118B:\nadd rcx, 4\ncmp rcx, r8\njz short loc_11B8\nloc_1194:\nmov edx, [rcx]\nmov esi, edx\nneg esi\ncmovs esi, edx\nadd eax, esi\ntest edx, edx\njz short loc_1189\nmov esi, edi\nneg esi\ntest edx, edx\ncmovs edi, esi\njmp short loc_118B\nloc_11AE:\nmov edi, 1\nmov eax, 0\nloc_11B8:\nimul eax, edi\nretn\nloc_11BC:\nmov eax, 0FFFF8000h\nretn", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int *v2; // rcx\n int *v3; // r8\n int v4; // edi\n int v5; // eax\n int v6; // edx\n int v7; // esi\n\n if ( !a2 )\n return 4294934528LL;\n if ( a2 <= 0 )\n {\n v4 = 1;\n v5 = 0;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 1;\n v5 = 0;\n do\n {\n v6 = *v2;\n v7 = -*v2;\n if ( *v2 > 0 )\n v7 = *v2;\n v5 += v7;\n if ( v6 )\n {\n if ( v6 < 0 )\n v4 = -v4;\n }\n else\n {\n v4 = 0;\n }\n ++v2;\n }\n while ( v2 != v3 );\n }\n return (unsigned int)(v4 * v5);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njz short loc_11BC\njle short loc_11AE\nmov rcx, rdi\nmovsxd rsi, esi\nlea r8, [rdi+rsi*4]\nmov edi, 1\nmov eax, 0\njmp short loc_1194\nloc_1189:\nmov edi, edx\nloc_118B:\nadd rcx, 4\ncmp rcx, r8\njz short loc_11B8\nloc_1194:\nmov edx, [rcx]\nmov esi, edx\nneg esi\ncmovs esi, edx\nadd eax, esi\ntest edx, edx\njz short loc_1189\nmov esi, edi\nneg esi\ntest edx, edx\ncmovs edi, esi\njmp short loc_118B\nloc_11AE:\nmov edi, 1\nmov eax, 0\nloc_11B8:\nimul eax, edi\nretn\nloc_11BC:\nmov eax, 0FFFF8000h\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int *a1, int a2)\n{\n int *v2; // rcx\n int *v3; // r8\n int v4; // edi\n int v5; // eax\n int v6; // edx\n int v7; // esi\n\n if ( !a2 )\n return 4294934528LL;\n if ( a2 <= 0 )\n {\n v4 = 1;\n v5 = 0;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 1;\n v5 = 0;\n do\n {\n v6 = *v2;\n v7 = -*v2;\n if ( *v2 > 0 )\n v7 = *v2;\n v5 += v7;\n if ( v6 )\n {\n if ( v6 < 0 )\n v4 = -v4;\n }\n else\n {\n v4 = 0;\n }\n ++v2;\n }\n while ( v2 != v3 );\n }\n return (unsigned int)(v4 * v5);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int *a1, int a2) {\n int *v2;\n int *v3;\n int v4;\n int v5;\n int v6;\n int v7;\n if (!a2) return 4294934528LL;\n if (a2 <= 0) {\n v4 = 1;\n v5 = 0;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 1;\n v5 = 0;\n do {\n v6 = *v2;\n v7 = -*v2;\n if (*v2 > 0) v7 = *v2;\n v5 += v7;\n if (v6) {\n if (v6 < 0) v4 = -v4;\n } else {\n v4 = 0;\n }\n ++v2;\n } while (v2 != v3);\n }\n return (unsigned int)(v4 * v5);\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int *v2;\n int *v3;\n int v4;\n int v5;\n int v6;\n int v7;\n if (!a2) return 4294934528LL;\n if (a2 <= 0) {\n v4 = 1;\n v5 = 0;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 1;\n v5 = 0;\n do {\n v6 = *v2;\n v7 = -*v2;\n if (*v2 > 0) v7 = *v2;\n v5 += v7;\n if (v6) {\n if (v6 < 0) v4 = -v4;\n } else {\n v4 = 0;\n }\n ++v2;\n } while (v2 != v3);\n }\n return (unsigned int)(v4 * v5);\n}" + }, + { + "index": "HumanEval-C-128", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(int *arr, int arr_size) {\n if (arr_size == 0) return -32768;\n int sum = 0, prods = 1, i;\n for (i = 0; i < arr_size; i++) {\n sum += abs(arr[i]);\n if (arr[i] == 0) prods = 0;\n if (arr[i] < 0) prods = -prods;\n }\n return sum * prods;\n}", + "test": "#include \n#include \n\nint main() {\n int arr1[] = {1, 2, 2, -4};\n assert(func0(arr1, 4) == -9);\n\n int arr2[] = {0, 1};\n assert(func0(arr2, 2) == 0);\n\n int arr3[] = {1, 1, 1, 2, 3, -1, 1};\n assert(func0(arr3, 7) == -10);\n\n assert(func0(NULL, 0) == -32768);\n\n int arr5[] = {2, 4, 1, 2, -1, -1, 9};\n assert(func0(arr5, 7) == 20);\n\n int arr6[] = {-1, 1, -1, 1};\n assert(func0(arr6, 4) == 4);\n\n int arr7[] = {-1, 1, 1, 1};\n assert(func0(arr7, 4) == -4);\n\n int arr8[] = {-1, 1, 1, 0};\n assert(func0(arr8, 4) == 0);\n \n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0_part_0:\ntest esi, esi\njle short loc_1400\nmovsxd rsi, esi\nxor eax, eax\nlea r8, [rdi+rsi*4]\nmov esi, 1\njmp short loc_13DA\nloc_13C8:\nmov ecx, esi\nneg ecx\ntest edx, edx\ncmovs esi, ecx\nadd rdi, 4\ncmp r8, rdi\njz short loc_13F4\nloc_13DA:\nmov edx, [rdi]\nmov ecx, edx\nneg ecx\ncmovs ecx, edx\nadd eax, ecx\ntest edx, edx\njnz short loc_13C8\nadd rdi, 4\nxor esi, esi\ncmp r8, rdi\njnz short loc_13DA\nloc_13F4:\nimul eax, esi\nretn\nloc_1400:\nxor eax, eax\nretn", + "ida_pseudo": "__int64 __fastcall func0_part_0(int *a1, int a2)\n{\n int v2; // eax\n int *v3; // r8\n int v4; // esi\n int v5; // edx\n int v6; // ecx\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 0;\n v3 = &a1[a2];\n v4 = 1;\n do\n {\n while ( 1 )\n {\n v5 = *a1;\n v6 = -*a1;\n if ( *a1 > 0 )\n v6 = *a1;\n v2 += v6;\n if ( v5 )\n break;\n ++a1;\n v4 = 0;\n if ( v3 == a1 )\n return (unsigned int)(v4 * v2);\n }\n if ( v5 < 0 )\n v4 = -v4;\n ++a1;\n }\n while ( v3 != a1 );\n return (unsigned int)(v4 * v2);\n}", + "ida_strip_asm": "sub_13B0:\ntest esi, esi\njle short loc_1400\nmovsxd rsi, esi\nxor eax, eax\nlea r8, [rdi+rsi*4]\nmov esi, 1\njmp short loc_13DA\nloc_13C8:\nmov ecx, esi\nneg ecx\ntest edx, edx\ncmovs esi, ecx\nadd rdi, 4\ncmp r8, rdi\njz short loc_13F4\nloc_13DA:\nmov edx, [rdi]\nmov ecx, edx\nneg ecx\ncmovs ecx, edx\nadd eax, ecx\ntest edx, edx\njnz short loc_13C8\nadd rdi, 4\nxor esi, esi\ncmp r8, rdi\njnz short loc_13DA\nloc_13F4:\nimul eax, esi\nretn\nloc_1400:\nxor eax, eax\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_13B0(int *a1, int a2)\n{\n int v2; // eax\n int *v3; // r8\n int v4; // esi\n int v5; // edx\n int v6; // ecx\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 0;\n v3 = &a1[a2];\n v4 = 1;\n do\n {\n while ( 1 )\n {\n v5 = *a1;\n v6 = -*a1;\n if ( *a1 > 0 )\n v6 = *a1;\n v2 += v6;\n if ( v5 )\n break;\n ++a1;\n v4 = 0;\n if ( v3 == a1 )\n return (unsigned int)(v4 * v2);\n }\n if ( v5 < 0 )\n v4 = -v4;\n ++a1;\n }\n while ( v3 != a1 );\n return (unsigned int)(v4 * v2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_13B0(int *a1, int a2) {\n int v2;\n int *v3;\n int v4;\n int v5;\n int v6;\n if (a2 <= 0) return 0LL;\n v2 = 0;\n v3 = &a1[a2];\n v4 = 1;\n do {\n while (1) {\n v5 = *a1;\n v6 = -*a1;\n if (*a1 > 0) v6 = *a1;\n v2 += v6;\n if (v5) break;\n ++a1;\n v4 = 0;\n if (v3 == a1) return (unsigned int)(v4 * v2);\n }\n if (v5 < 0) v4 = -v4;\n ++a1;\n } while (v3 != a1);\n return (unsigned int)(v4 * v2);\n}", + "ida_pseudo_norm": "long long func0_part_0(int *a1, int a2) {\n int v2;\n int *v3;\n int v4;\n int v5;\n int v6;\n if (a2 <= 0) return 0LL;\n v2 = 0;\n v3 = &a1[a2];\n v4 = 1;\n do {\n while (1) {\n v5 = *a1;\n v6 = -*a1;\n if (*a1 > 0) v6 = *a1;\n v2 += v6;\n if (v5) break;\n ++a1;\n v4 = 0;\n if (v3 == a1) return (unsigned int)(v4 * v2);\n }\n if (v5 < 0) v4 = -v4;\n ++a1;\n } while (v3 != a1);\n return (unsigned int)(v4 * v2);\n}" + }, + { + "index": "HumanEval-C-128", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(int *arr, int arr_size) {\n if (arr_size == 0) return -32768;\n int sum = 0, prods = 1, i;\n for (i = 0; i < arr_size; i++) {\n sum += abs(arr[i]);\n if (arr[i] == 0) prods = 0;\n if (arr[i] < 0) prods = -prods;\n }\n return sum * prods;\n}", + "test": "#include \n#include \n\nint main() {\n int arr1[] = {1, 2, 2, -4};\n assert(func0(arr1, 4) == -9);\n\n int arr2[] = {0, 1};\n assert(func0(arr2, 2) == 0);\n\n int arr3[] = {1, 1, 1, 2, 3, -1, 1};\n assert(func0(arr3, 7) == -10);\n\n assert(func0(NULL, 0) == -32768);\n\n int arr5[] = {2, 4, 1, 2, -1, -1, 9};\n assert(func0(arr5, 7) == 20);\n\n int arr6[] = {-1, 1, -1, 1};\n assert(func0(arr6, 4) == 4);\n\n int arr7[] = {-1, 1, 1, 1};\n assert(func0(arr7, 4) == -4);\n\n int arr8[] = {-1, 1, 1, 0};\n assert(func0(arr8, 4) == 0);\n \n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0_part_0:\ntest esi, esi\njle short loc_1400\nmovsxd rsi, esi\nxor eax, eax\nlea r8, [rdi+rsi*4]\nmov esi, 1\njmp short loc_13DA\nloc_13C8:\nmov ecx, esi\nneg ecx\ntest edx, edx\ncmovs esi, ecx\nadd rdi, 4\ncmp r8, rdi\njz short loc_13F4\nloc_13DA:\nmov edx, [rdi]\nmov ecx, edx\nneg ecx\ncmovs ecx, edx\nadd eax, ecx\ntest edx, edx\njnz short loc_13C8\nadd rdi, 4\nxor esi, esi\ncmp r8, rdi\njnz short loc_13DA\nloc_13F4:\nimul eax, esi\nretn\nloc_1400:\nxor eax, eax\nretn", + "ida_pseudo": "__int64 __fastcall func0_part_0(int *a1, int a2)\n{\n int v2; // eax\n int *v3; // r8\n int v4; // esi\n int v5; // edx\n int v6; // ecx\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 0;\n v3 = &a1[a2];\n v4 = 1;\n do\n {\n while ( 1 )\n {\n v5 = *a1;\n v6 = -*a1;\n if ( *a1 > 0 )\n v6 = *a1;\n v2 += v6;\n if ( v5 )\n break;\n ++a1;\n v4 = 0;\n if ( v3 == a1 )\n return (unsigned int)(v4 * v2);\n }\n if ( v5 < 0 )\n v4 = -v4;\n ++a1;\n }\n while ( v3 != a1 );\n return (unsigned int)(v4 * v2);\n}", + "ida_strip_asm": "sub_13B0:\ntest esi, esi\njle short loc_1400\nmovsxd rsi, esi\nxor eax, eax\nlea r8, [rdi+rsi*4]\nmov esi, 1\njmp short loc_13DA\nloc_13C8:\nmov ecx, esi\nneg ecx\ntest edx, edx\ncmovs esi, ecx\nadd rdi, 4\ncmp r8, rdi\njz short loc_13F4\nloc_13DA:\nmov edx, [rdi]\nmov ecx, edx\nneg ecx\ncmovs ecx, edx\nadd eax, ecx\ntest edx, edx\njnz short loc_13C8\nadd rdi, 4\nxor esi, esi\ncmp r8, rdi\njnz short loc_13DA\nloc_13F4:\nimul eax, esi\nretn\nloc_1400:\nxor eax, eax\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_13B0(int *a1, int a2)\n{\n int v2; // eax\n int *v3; // r8\n int v4; // esi\n int v5; // edx\n int v6; // ecx\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 0;\n v3 = &a1[a2];\n v4 = 1;\n do\n {\n while ( 1 )\n {\n v5 = *a1;\n v6 = -*a1;\n if ( *a1 > 0 )\n v6 = *a1;\n v2 += v6;\n if ( v5 )\n break;\n ++a1;\n v4 = 0;\n if ( v3 == a1 )\n return (unsigned int)(v4 * v2);\n }\n if ( v5 < 0 )\n v4 = -v4;\n ++a1;\n }\n while ( v3 != a1 );\n return (unsigned int)(v4 * v2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_13B0(int *a1, int a2) {\n int v2;\n int *v3;\n int v4;\n int v5;\n int v6;\n if (a2 <= 0) return 0LL;\n v2 = 0;\n v3 = &a1[a2];\n v4 = 1;\n do {\n while (1) {\n v5 = *a1;\n v6 = -*a1;\n if (*a1 > 0) v6 = *a1;\n v2 += v6;\n if (v5) break;\n ++a1;\n v4 = 0;\n if (v3 == a1) return (unsigned int)(v4 * v2);\n }\n if (v5 < 0) v4 = -v4;\n ++a1;\n } while (v3 != a1);\n return (unsigned int)(v4 * v2);\n}", + "ida_pseudo_norm": "long long func0_part_0(int *a1, int a2) {\n int v2;\n int *v3;\n int v4;\n int v5;\n int v6;\n if (a2 <= 0) return 0LL;\n v2 = 0;\n v3 = &a1[a2];\n v4 = 1;\n do {\n while (1) {\n v5 = *a1;\n v6 = -*a1;\n if (*a1 > 0) v6 = *a1;\n v2 += v6;\n if (v5) break;\n ++a1;\n v4 = 0;\n if (v3 == a1) return (unsigned int)(v4 * v2);\n }\n if (v5 < 0) v4 = -v4;\n ++a1;\n } while (v3 != a1);\n return (unsigned int)(v4 * v2);\n}" + }, + { + "index": "HumanEval-C-129", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int *func0(int **grid, int N, int k, int *returnSize) {\n int i, j, x, y, min;\n for (i = 0; i < N; i++)\n for (j = 0; j < N; j++)\n if (grid[i][j] == 1) {\n x = i;\n y = j;\n }\n min = N * N;\n if (x > 0 && grid[x - 1][y] < min) min = grid[x - 1][y];\n if (x < N - 1 && grid[x + 1][y] < min) min = grid[x + 1][y];\n if (y > 0 && grid[x][y - 1] < min) min = grid[x][y - 1];\n if (y < N - 1 && grid[x][y + 1] < min) min = grid[x][y + 1];\n *returnSize = k;\n int *out = (int *)malloc(k * sizeof(int));\n for (i = 0; i < k; i++)\n if (i % 2 == 0)\n out[i] = 1;\n else\n out[i] = min;\n return out;\n}", + "test": "#include \n#include \n\nint issame(int *a, int *b, int size) {\n for (int i = 0; i < size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int size;\n\n // Test case 1\n int grid1[3][3] = {{1, 2, 3}, {4, 5, 6}, {7, 8, 9}};\n int *grid1_ptrs[] = {grid1[0], grid1[1], grid1[2]};\n int result1[] = {1, 2, 1};\n int *out1 = func0(grid1_ptrs, 3, 3, &size);\n assert(issame(out1, result1, size));\n free(out1);\n\n // Test case 2\n int grid2[3][3] = {{5, 9, 3}, {4, 1, 6}, {7, 8, 2}};\n int *grid2_ptrs[] = {grid2[0], grid2[1], grid2[2]};\n int result2[] = {1};\n int *out2 = func0(grid2_ptrs, 3, 1, &size);\n assert(issame(out2, result2, size));\n free(out2);\n\n // Test case 3\n int grid3[4][4] = {{1, 2, 3, 4}, {5, 6, 7, 8}, {9, 10, 11, 12}, {13, 14, 15, 16}};\n int *grid3_ptrs[] = {grid3[0], grid3[1], grid3[2], grid3[3]};\n int result3[] = {1, 2, 1, 2};\n int *out3 = func0(grid3_ptrs, 4, 4, &size);\n assert(issame(out3, result3, size));\n free(out3);\n\n // Test case 4\n int grid4[4][4] = {{6, 4, 13, 10}, {5, 7, 12, 1}, {3, 16, 11, 15}, {8, 14, 9, 2}};\n int *grid4_ptrs[] = {grid4[0], grid4[1], grid4[2], grid4[3]};\n int result4[] = {1, 10, 1, 10, 1, 10, 1};\n int *out4 = func0(grid4_ptrs, 4, 7, &size);\n assert(issame(out4, result4, size));\n free(out4);\n \n // Test case 5\n int grid5[4][4] = {{8, 14, 9, 2}, {6, 4, 13, 15}, {5, 7, 1, 12}, {3, 10, 11, 16}};\n int *grid5_ptrs[] = {grid5[0], grid5[1], grid5[2], grid5[3]};\n int result5[] = {1, 7, 1, 7, 1};\n int *out5 = func0(grid5_ptrs, 4, 5, &size);\n assert(issame(out5, result5, size));\n free(out5);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_30], edx\nmov [rbp+var_38], rcx\nmov [rbp+var_1C], 0\njmp short loc_121C\nloc_11CC:\nmov [rbp+var_18], 0\njmp short loc_1210\nloc_11D5:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_18]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\ncmp eax, 1\njnz short loc_120C\nmov eax, [rbp+var_1C]\nmov [rbp+var_14], eax\nmov eax, [rbp+var_18]\nmov [rbp+var_10], eax\nloc_120C:\nadd [rbp+var_18], 1\nloc_1210:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_2C]\njl short loc_11D5\nadd [rbp+var_1C], 1\nloc_121C:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_2C]\njl short loc_11CC\nmov eax, [rbp+var_2C]\nimul eax, eax\nmov [rbp+var_C], eax\ncmp [rbp+var_14], 0\njle short loc_1287\nmov eax, [rbp+var_14]\ncdqe\nshl rax, 3\nlea rdx, [rax-8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_C], eax\njle short loc_1287\nmov eax, [rbp+var_14]\ncdqe\nshl rax, 3\nlea rdx, [rax-8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nloc_1287:\nmov eax, [rbp+var_2C]\nsub eax, 1\ncmp [rbp+var_14], eax\njge short loc_12EE\nmov eax, [rbp+var_14]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_C], eax\njle short loc_12EE\nmov eax, [rbp+var_14]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nloc_12EE:\ncmp [rbp+var_10], 0\njle short loc_1350\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nshl rdx, 2\nsub rdx, 4\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_C], eax\njle short loc_1350\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nshl rdx, 2\nsub rdx, 4\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nloc_1350:\nmov eax, [rbp+var_2C]\nsub eax, 1\ncmp [rbp+var_10], eax\njge short loc_13B7\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nadd rdx, 1\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_C], eax\njle short loc_13B7\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nadd rdx, 1\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nloc_13B7:\nmov rax, [rbp+var_38]\nmov edx, [rbp+var_30]\nmov [rax], edx\nmov eax, [rbp+var_30]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_1C], 0\njmp short loc_1421\nloc_13DE:\nmov eax, [rbp+var_1C]\nand eax, 1\ntest eax, eax\njnz short loc_1404\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov dword ptr [rax], 1\njmp short loc_141D\nloc_1404:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_C]\nmov [rdx], eax\nloc_141D:\nadd [rbp+var_1C], 1\nloc_1421:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_30]\njl short loc_13DE\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, int a3, _DWORD *a4)\n{\n int i; // [rsp+24h] [rbp-1Ch]\n int k; // [rsp+24h] [rbp-1Ch]\n int j; // [rsp+28h] [rbp-18h]\n int v9; // [rsp+2Ch] [rbp-14h]\n int v10; // [rsp+30h] [rbp-10h]\n int v11; // [rsp+34h] [rbp-Ch]\n _DWORD *v12; // [rsp+38h] [rbp-8h]\n\n for ( i = 0; i < a2; ++i )\n {\n for ( j = 0; j < a2; ++j )\n {\n if ( *(_DWORD *)(4LL * j + *(_QWORD *)(8LL * i + a1)) == 1 )\n {\n v9 = i;\n v10 = j;\n }\n }\n }\n v11 = a2 * a2;\n if ( v9 > 0 && v11 > *(_DWORD *)(4LL * v10 + *(_QWORD *)(8LL * v9 - 8 + a1)) )\n v11 = *(_DWORD *)(4LL * v10 + *(_QWORD *)(8LL * v9 - 8 + a1));\n if ( v9 < a2 - 1 && v11 > *(_DWORD *)(4LL * v10 + *(_QWORD *)(8 * (v9 + 1LL) + a1)) )\n v11 = *(_DWORD *)(4LL * v10 + *(_QWORD *)(8 * (v9 + 1LL) + a1));\n if ( v10 > 0 && v11 > *(_DWORD *)(4LL * v10 - 4 + *(_QWORD *)(8LL * v9 + a1)) )\n v11 = *(_DWORD *)(4LL * v10 - 4 + *(_QWORD *)(8LL * v9 + a1));\n if ( v10 < a2 - 1 && v11 > *(_DWORD *)(4 * (v10 + 1LL) + *(_QWORD *)(8LL * v9 + a1)) )\n v11 = *(_DWORD *)(4 * (v10 + 1LL) + *(_QWORD *)(8LL * v9 + a1));\n *a4 = a3;\n v12 = malloc(4LL * a3);\n for ( k = 0; k < a3; ++k )\n {\n if ( (k & 1) != 0 )\n v12[k] = v11;\n else\n v12[k] = 1;\n }\n return v12;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_30], edx\nmov [rbp+var_38], rcx\nmov [rbp+var_1C], 0\njmp short loc_121C\nloc_11CC:\nmov [rbp+var_18], 0\njmp short loc_1210\nloc_11D5:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_18]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\ncmp eax, 1\njnz short loc_120C\nmov eax, [rbp+var_1C]\nmov [rbp+var_14], eax\nmov eax, [rbp+var_18]\nmov [rbp+var_10], eax\nloc_120C:\nadd [rbp+var_18], 1\nloc_1210:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_2C]\njl short loc_11D5\nadd [rbp+var_1C], 1\nloc_121C:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_2C]\njl short loc_11CC\nmov eax, [rbp+var_2C]\nimul eax, eax\nmov [rbp+var_C], eax\ncmp [rbp+var_14], 0\njle short loc_1287\nmov eax, [rbp+var_14]\ncdqe\nshl rax, 3\nlea rdx, [rax-8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_C], eax\njle short loc_1287\nmov eax, [rbp+var_14]\ncdqe\nshl rax, 3\nlea rdx, [rax-8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nloc_1287:\nmov eax, [rbp+var_2C]\nsub eax, 1\ncmp [rbp+var_14], eax\njge short loc_12EE\nmov eax, [rbp+var_14]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_C], eax\njle short loc_12EE\nmov eax, [rbp+var_14]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nloc_12EE:\ncmp [rbp+var_10], 0\njle short loc_1350\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nshl rdx, 2\nsub rdx, 4\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_C], eax\njle short loc_1350\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nshl rdx, 2\nsub rdx, 4\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nloc_1350:\nmov eax, [rbp+var_2C]\nsub eax, 1\ncmp [rbp+var_10], eax\njge short loc_13B7\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nadd rdx, 1\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_C], eax\njle short loc_13B7\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nadd rdx, 1\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nloc_13B7:\nmov rax, [rbp+var_38]\nmov edx, [rbp+var_30]\nmov [rax], edx\nmov eax, [rbp+var_30]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_1C], 0\njmp short loc_1421\nloc_13DE:\nmov eax, [rbp+var_1C]\nand eax, 1\ntest eax, eax\njnz short loc_1404\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov dword ptr [rax], 1\njmp short loc_141D\nloc_1404:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_C]\nmov [rdx], eax\nloc_141D:\nadd [rbp+var_1C], 1\nloc_1421:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_30]\njl short loc_13DE\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(__int64 a1, int a2, int a3, _DWORD *a4)\n{\n int i; // [rsp+24h] [rbp-1Ch]\n int k; // [rsp+24h] [rbp-1Ch]\n int j; // [rsp+28h] [rbp-18h]\n int v9; // [rsp+2Ch] [rbp-14h]\n int v10; // [rsp+30h] [rbp-10h]\n int v11; // [rsp+34h] [rbp-Ch]\n _DWORD *v12; // [rsp+38h] [rbp-8h]\n\n for ( i = 0; i < a2; ++i )\n {\n for ( j = 0; j < a2; ++j )\n {\n if ( *(_DWORD *)(4LL * j + *(_QWORD *)(8LL * i + a1)) == 1 )\n {\n v9 = i;\n v10 = j;\n }\n }\n }\n v11 = a2 * a2;\n if ( v9 > 0 && v11 > *(_DWORD *)(4LL * v10 + *(_QWORD *)(8LL * v9 - 8 + a1)) )\n v11 = *(_DWORD *)(4LL * v10 + *(_QWORD *)(8LL * v9 - 8 + a1));\n if ( v9 < a2 - 1 && v11 > *(_DWORD *)(4LL * v10 + *(_QWORD *)(8 * (v9 + 1LL) + a1)) )\n v11 = *(_DWORD *)(4LL * v10 + *(_QWORD *)(8 * (v9 + 1LL) + a1));\n if ( v10 > 0 && v11 > *(_DWORD *)(4LL * v10 - 4 + *(_QWORD *)(8LL * v9 + a1)) )\n v11 = *(_DWORD *)(4LL * v10 - 4 + *(_QWORD *)(8LL * v9 + a1));\n if ( v10 < a2 - 1 && v11 > *(_DWORD *)(4 * (v10 + 1LL) + *(_QWORD *)(8LL * v9 + a1)) )\n v11 = *(_DWORD *)(4 * (v10 + 1LL) + *(_QWORD *)(8LL * v9 + a1));\n *a4 = a3;\n v12 = malloc(4LL * a3);\n for ( k = 0; k < a3; ++k )\n {\n if ( (k & 1) != 0 )\n v12[k] = v11;\n else\n v12[k] = 1;\n }\n return v12;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(long long a1, int a2, int a3, uint32_t *a4) {\n int i;\n int k;\n int j;\n int v9;\n int v10;\n int v11;\n uint32_t *v12;\n for (i = 0; i < a2; ++i) {\n for (j = 0; j < a2; ++j) {\n if (*(uint32_t *)(4LL * j + *(uint64_t *)(8LL * i + a1)) == 1) {\n v9 = i;\n v10 = j;\n }\n }\n }\n v11 = a2 * a2;\n if (v9 > 0 &&\n v11 > *(uint32_t *)(4LL * v10 + *(uint64_t *)(8LL * v9 - 8 + a1)))\n v11 = *(uint32_t *)(4LL * v10 + *(uint64_t *)(8LL * v9 - 8 + a1));\n if (v9 < a2 - 1 &&\n v11 > *(uint32_t *)(4LL * v10 + *(uint64_t *)(8 * (v9 + 1LL) + a1)))\n v11 = *(uint32_t *)(4LL * v10 + *(uint64_t *)(8 * (v9 + 1LL) + a1));\n if (v10 > 0 &&\n v11 > *(uint32_t *)(4LL * v10 - 4 + *(uint64_t *)(8LL * v9 + a1)))\n v11 = *(uint32_t *)(4LL * v10 - 4 + *(uint64_t *)(8LL * v9 + a1));\n if (v10 < a2 - 1 &&\n v11 > *(uint32_t *)(4 * (v10 + 1LL) + *(uint64_t *)(8LL * v9 + a1)))\n v11 = *(uint32_t *)(4 * (v10 + 1LL) + *(uint64_t *)(8LL * v9 + a1));\n *a4 = a3;\n v12 = malloc(4LL * a3);\n for (k = 0; k < a3; ++k) {\n if ((k & 1) != 0)\n v12[k] = v11;\n else\n v12[k] = 1;\n }\n return v12;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, int a3, uint32_t *a4) {\n int i;\n int k;\n int j;\n int v9;\n int v10;\n int v11;\n uint32_t *v12;\n for (i = 0; i < a2; ++i) {\n for (j = 0; j < a2; ++j) {\n if (*(uint32_t *)(4LL * j + *(uint64_t *)(8LL * i + a1)) == 1) {\n v9 = i;\n v10 = j;\n }\n }\n }\n v11 = a2 * a2;\n if (v9 > 0 &&\n v11 > *(uint32_t *)(4LL * v10 + *(uint64_t *)(8LL * v9 - 8 + a1)))\n v11 = *(uint32_t *)(4LL * v10 + *(uint64_t *)(8LL * v9 - 8 + a1));\n if (v9 < a2 - 1 &&\n v11 > *(uint32_t *)(4LL * v10 + *(uint64_t *)(8 * (v9 + 1LL) + a1)))\n v11 = *(uint32_t *)(4LL * v10 + *(uint64_t *)(8 * (v9 + 1LL) + a1));\n if (v10 > 0 &&\n v11 > *(uint32_t *)(4LL * v10 - 4 + *(uint64_t *)(8LL * v9 + a1)))\n v11 = *(uint32_t *)(4LL * v10 - 4 + *(uint64_t *)(8LL * v9 + a1));\n if (v10 < a2 - 1 &&\n v11 > *(uint32_t *)(4 * (v10 + 1LL) + *(uint64_t *)(8LL * v9 + a1)))\n v11 = *(uint32_t *)(4 * (v10 + 1LL) + *(uint64_t *)(8LL * v9 + a1));\n *a4 = a3;\n v12 = malloc(4LL * a3);\n for (k = 0; k < a3; ++k) {\n if ((k & 1) != 0)\n v12[k] = v11;\n else\n v12[k] = 1;\n }\n return v12;\n}" + }, + { + "index": "HumanEval-C-129", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int *func0(int **grid, int N, int k, int *returnSize) {\n int i, j, x, y, min;\n for (i = 0; i < N; i++)\n for (j = 0; j < N; j++)\n if (grid[i][j] == 1) {\n x = i;\n y = j;\n }\n min = N * N;\n if (x > 0 && grid[x - 1][y] < min) min = grid[x - 1][y];\n if (x < N - 1 && grid[x + 1][y] < min) min = grid[x + 1][y];\n if (y > 0 && grid[x][y - 1] < min) min = grid[x][y - 1];\n if (y < N - 1 && grid[x][y + 1] < min) min = grid[x][y + 1];\n *returnSize = k;\n int *out = (int *)malloc(k * sizeof(int));\n for (i = 0; i < k; i++)\n if (i % 2 == 0)\n out[i] = 1;\n else\n out[i] = min;\n return out;\n}", + "test": "#include \n#include \n\nint issame(int *a, int *b, int size) {\n for (int i = 0; i < size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int size;\n\n // Test case 1\n int grid1[3][3] = {{1, 2, 3}, {4, 5, 6}, {7, 8, 9}};\n int *grid1_ptrs[] = {grid1[0], grid1[1], grid1[2]};\n int result1[] = {1, 2, 1};\n int *out1 = func0(grid1_ptrs, 3, 3, &size);\n assert(issame(out1, result1, size));\n free(out1);\n\n // Test case 2\n int grid2[3][3] = {{5, 9, 3}, {4, 1, 6}, {7, 8, 2}};\n int *grid2_ptrs[] = {grid2[0], grid2[1], grid2[2]};\n int result2[] = {1};\n int *out2 = func0(grid2_ptrs, 3, 1, &size);\n assert(issame(out2, result2, size));\n free(out2);\n\n // Test case 3\n int grid3[4][4] = {{1, 2, 3, 4}, {5, 6, 7, 8}, {9, 10, 11, 12}, {13, 14, 15, 16}};\n int *grid3_ptrs[] = {grid3[0], grid3[1], grid3[2], grid3[3]};\n int result3[] = {1, 2, 1, 2};\n int *out3 = func0(grid3_ptrs, 4, 4, &size);\n assert(issame(out3, result3, size));\n free(out3);\n\n // Test case 4\n int grid4[4][4] = {{6, 4, 13, 10}, {5, 7, 12, 1}, {3, 16, 11, 15}, {8, 14, 9, 2}};\n int *grid4_ptrs[] = {grid4[0], grid4[1], grid4[2], grid4[3]};\n int result4[] = {1, 10, 1, 10, 1, 10, 1};\n int *out4 = func0(grid4_ptrs, 4, 7, &size);\n assert(issame(out4, result4, size));\n free(out4);\n \n // Test case 5\n int grid5[4][4] = {{8, 14, 9, 2}, {6, 4, 13, 15}, {5, 7, 1, 12}, {3, 10, 11, 16}};\n int *grid5_ptrs[] = {grid5[0], grid5[1], grid5[2], grid5[3]};\n int result5[] = {1, 7, 1, 7, 1};\n int *out5 = func0(grid5_ptrs, 4, 5, &size);\n assert(issame(out5, result5, size));\n free(out5);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov r10, rdi\nmov r11d, esi\nmov ebx, edx\nmov r12, rcx\ntest esi, esi\njle short loc_11F1\nmovsxd rdx, esi\nmov edi, 0\nloc_11C8:\nmov esi, edi\nmov rcx, [r10+rdi*8]\nmov eax, 0\nloc_11D3:\ncmp dword ptr [rcx+rax*4], 1\ncmovz r8d, eax\ncmovz r9d, esi\nadd rax, 1\ncmp rax, rdx\njnz short loc_11D3\nadd rdi, 1\ncmp rdi, rdx\njnz short loc_11C8\nloc_11F1:\nmov ebp, r11d\nimul ebp, r11d\ntest r9d, r9d\njle short loc_1210\nmovsxd rdx, r9d\nmovsxd rax, r8d\nmov rdx, [r10+rdx*8-8]\nmov eax, [rdx+rax*4]\ncmp ebp, eax\ncmovg ebp, eax\nloc_1210:\nsub r11d, 1\ncmp r11d, r9d\njle short loc_122C\nmovsxd rdx, r9d\nmovsxd rax, r8d\nmov rdx, [r10+rdx*8+8]\nmov eax, [rdx+rax*4]\ncmp ebp, eax\ncmovg ebp, eax\nloc_122C:\ntest r8d, r8d\njle short loc_1244\nmovsxd rdx, r9d\nmovsxd rax, r8d\nmov rdx, [r10+rdx*8]\nmov eax, [rdx+rax*4-4]\ncmp ebp, eax\ncmovg ebp, eax\nloc_1244:\ncmp r11d, r8d\njle short loc_125D\nmovsxd r9, r9d\nmovsxd r8, r8d\nmov rax, [r10+r9*8]\nmov eax, [rax+r8*4+4]\ncmp ebp, eax\ncmovg ebp, eax\nloc_125D:\nmov [r12], ebx\nmovsxd r12, ebx\nlea rdi, ds:0[r12*4]; size\ncall _malloc\ntest ebx, ebx\njle short loc_1296\nmov edx, 0\njmp short loc_1288\nloc_127C:\nmov [rax+rdx*4], ebp\nloc_127F:\nadd rdx, 1\ncmp r12, rdx\njz short loc_1296\nloc_1288:\ntest dl, 1\njnz short loc_127C\nmov dword ptr [rax+rdx*4], 1\njmp short loc_127F\nloc_1296:\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, int a3, int *a4, int a5, int a6)\n{\n __int64 i; // rdi\n __int64 j; // rax\n int v10; // ebp\n _DWORD *result; // rax\n __int64 v12; // rdx\n\n if ( a2 > 0 )\n {\n for ( i = 0LL; i != a2; ++i )\n {\n for ( j = 0LL; j != a2; ++j )\n {\n if ( *(_DWORD *)(*(_QWORD *)(a1 + 8 * i) + 4 * j) == 1 )\n {\n a5 = j;\n a6 = i;\n }\n }\n }\n }\n v10 = a2 * a2;\n if ( a6 > 0 && v10 > *(_DWORD *)(*(_QWORD *)(a1 + 8LL * a6 - 8) + 4LL * a5) )\n v10 = *(_DWORD *)(*(_QWORD *)(a1 + 8LL * a6 - 8) + 4LL * a5);\n if ( a2 - 1 > a6 && v10 > *(_DWORD *)(*(_QWORD *)(a1 + 8LL * a6 + 8) + 4LL * a5) )\n v10 = *(_DWORD *)(*(_QWORD *)(a1 + 8LL * a6 + 8) + 4LL * a5);\n if ( a5 > 0 && v10 > *(_DWORD *)(*(_QWORD *)(a1 + 8LL * a6) + 4LL * a5 - 4) )\n v10 = *(_DWORD *)(*(_QWORD *)(a1 + 8LL * a6) + 4LL * a5 - 4);\n if ( a2 - 1 > a5 && v10 > *(_DWORD *)(*(_QWORD *)(a1 + 8LL * a6) + 4LL * a5 + 4) )\n v10 = *(_DWORD *)(*(_QWORD *)(a1 + 8LL * a6) + 4LL * a5 + 4);\n *a4 = a3;\n result = malloc(4LL * a3);\n if ( a3 > 0 )\n {\n v12 = 0LL;\n do\n {\n if ( (v12 & 1) != 0 )\n result[v12] = v10;\n else\n result[v12] = 1;\n ++v12;\n }\n while ( a3 != v12 );\n }\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r12\npush rbp\npush rbx\nmov r10, rdi\nmov r11d, esi\nmov ebx, edx\nmov r12, rcx\ntest esi, esi\njle short loc_11F1\nmovsxd rdx, esi\nmov edi, 0\nloc_11C8:\nmov esi, edi\nmov rcx, [r10+rdi*8]\nmov eax, 0\nloc_11D3:\ncmp dword ptr [rcx+rax*4], 1\ncmovz r8d, eax\ncmovz r9d, esi\nadd rax, 1\ncmp rax, rdx\njnz short loc_11D3\nadd rdi, 1\ncmp rdi, rdx\njnz short loc_11C8\nloc_11F1:\nmov ebp, r11d\nimul ebp, r11d\ntest r9d, r9d\njle short loc_1210\nmovsxd rdx, r9d\nmovsxd rax, r8d\nmov rdx, [r10+rdx*8-8]\nmov eax, [rdx+rax*4]\ncmp ebp, eax\ncmovg ebp, eax\nloc_1210:\nsub r11d, 1\ncmp r11d, r9d\njle short loc_122C\nmovsxd rdx, r9d\nmovsxd rax, r8d\nmov rdx, [r10+rdx*8+8]\nmov eax, [rdx+rax*4]\ncmp ebp, eax\ncmovg ebp, eax\nloc_122C:\ntest r8d, r8d\njle short loc_1244\nmovsxd rdx, r9d\nmovsxd rax, r8d\nmov rdx, [r10+rdx*8]\nmov eax, [rdx+rax*4-4]\ncmp ebp, eax\ncmovg ebp, eax\nloc_1244:\ncmp r11d, r8d\njle short loc_125D\nmovsxd r9, r9d\nmovsxd r8, r8d\nmov rax, [r10+r9*8]\nmov eax, [rax+r8*4+4]\ncmp ebp, eax\ncmovg ebp, eax\nloc_125D:\nmov [r12], ebx\nmovsxd r12, ebx\nlea rdi, ds:0[r12*4]; size\ncall _malloc\ntest ebx, ebx\njle short loc_1296\nmov edx, 0\njmp short loc_1288\nloc_127C:\nmov [rax+rdx*4], ebp\nloc_127F:\nadd rdx, 1\ncmp r12, rdx\njz short loc_1296\nloc_1288:\ntest dl, 1\njnz short loc_127C\nmov dword ptr [rax+rdx*4], 1\njmp short loc_127F\nloc_1296:\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(__int64 a1, int a2, int a3, int *a4, int a5, int a6)\n{\n __int64 i; // rdi\n __int64 j; // rax\n int v10; // ebp\n _DWORD *result; // rax\n __int64 v12; // rdx\n\n if ( a2 > 0 )\n {\n for ( i = 0LL; i != a2; ++i )\n {\n for ( j = 0LL; j != a2; ++j )\n {\n if ( *(_DWORD *)(*(_QWORD *)(a1 + 8 * i) + 4 * j) == 1 )\n {\n a5 = j;\n a6 = i;\n }\n }\n }\n }\n v10 = a2 * a2;\n if ( a6 > 0 && v10 > *(_DWORD *)(*(_QWORD *)(a1 + 8LL * a6 - 8) + 4LL * a5) )\n v10 = *(_DWORD *)(*(_QWORD *)(a1 + 8LL * a6 - 8) + 4LL * a5);\n if ( a2 - 1 > a6 && v10 > *(_DWORD *)(*(_QWORD *)(a1 + 8LL * a6 + 8) + 4LL * a5) )\n v10 = *(_DWORD *)(*(_QWORD *)(a1 + 8LL * a6 + 8) + 4LL * a5);\n if ( a5 > 0 && v10 > *(_DWORD *)(*(_QWORD *)(a1 + 8LL * a6) + 4LL * a5 - 4) )\n v10 = *(_DWORD *)(*(_QWORD *)(a1 + 8LL * a6) + 4LL * a5 - 4);\n if ( a2 - 1 > a5 && v10 > *(_DWORD *)(*(_QWORD *)(a1 + 8LL * a6) + 4LL * a5 + 4) )\n v10 = *(_DWORD *)(*(_QWORD *)(a1 + 8LL * a6) + 4LL * a5 + 4);\n *a4 = a3;\n result = malloc(4LL * a3);\n if ( a3 > 0 )\n {\n v12 = 0LL;\n do\n {\n if ( (v12 & 1) != 0 )\n result[v12] = v10;\n else\n result[v12] = 1;\n ++v12;\n }\n while ( a3 != v12 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(long long a1, int a2, int a3, int *a4, int a5, int a6) {\n long long i;\n long long j;\n int v10;\n uint32_t *result;\n long long v12;\n if (a2 > 0) {\n for (i = 0LL; i != a2; ++i) {\n for (j = 0LL; j != a2; ++j) {\n if (*(uint32_t *)(*(uint64_t *)(a1 + 8 * i) + 4 * j) == 1) {\n a5 = j;\n a6 = i;\n }\n }\n }\n }\n v10 = a2 * a2;\n if (a6 > 0 &&\n v10 > *(uint32_t *)(*(uint64_t *)(a1 + 8LL * a6 - 8) + 4LL * a5))\n v10 = *(uint32_t *)(*(uint64_t *)(a1 + 8LL * a6 - 8) + 4LL * a5);\n if (a2 - 1 > a6 &&\n v10 > *(uint32_t *)(*(uint64_t *)(a1 + 8LL * a6 + 8) + 4LL * a5))\n v10 = *(uint32_t *)(*(uint64_t *)(a1 + 8LL * a6 + 8) + 4LL * a5);\n if (a5 > 0 &&\n v10 > *(uint32_t *)(*(uint64_t *)(a1 + 8LL * a6) + 4LL * a5 - 4))\n v10 = *(uint32_t *)(*(uint64_t *)(a1 + 8LL * a6) + 4LL * a5 - 4);\n if (a2 - 1 > a5 &&\n v10 > *(uint32_t *)(*(uint64_t *)(a1 + 8LL * a6) + 4LL * a5 + 4))\n v10 = *(uint32_t *)(*(uint64_t *)(a1 + 8LL * a6) + 4LL * a5 + 4);\n *a4 = a3;\n result = malloc(4LL * a3);\n if (a3 > 0) {\n v12 = 0LL;\n do {\n if ((v12 & 1) != 0)\n result[v12] = v10;\n else\n result[v12] = 1;\n ++v12;\n } while (a3 != v12);\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, int a3, int *a4, int a5, int a6) {\n long long i;\n long long j;\n int v10;\n uint32_t *result;\n long long v12;\n if (a2 > 0) {\n for (i = 0LL; i != a2; ++i) {\n for (j = 0LL; j != a2; ++j) {\n if (*(uint32_t *)(*(uint64_t *)(a1 + 8 * i) + 4 * j) == 1) {\n a5 = j;\n a6 = i;\n }\n }\n }\n }\n v10 = a2 * a2;\n if (a6 > 0 &&\n v10 > *(uint32_t *)(*(uint64_t *)(a1 + 8LL * a6 - 8) + 4LL * a5))\n v10 = *(uint32_t *)(*(uint64_t *)(a1 + 8LL * a6 - 8) + 4LL * a5);\n if (a2 - 1 > a6 &&\n v10 > *(uint32_t *)(*(uint64_t *)(a1 + 8LL * a6 + 8) + 4LL * a5))\n v10 = *(uint32_t *)(*(uint64_t *)(a1 + 8LL * a6 + 8) + 4LL * a5);\n if (a5 > 0 &&\n v10 > *(uint32_t *)(*(uint64_t *)(a1 + 8LL * a6) + 4LL * a5 - 4))\n v10 = *(uint32_t *)(*(uint64_t *)(a1 + 8LL * a6) + 4LL * a5 - 4);\n if (a2 - 1 > a5 &&\n v10 > *(uint32_t *)(*(uint64_t *)(a1 + 8LL * a6) + 4LL * a5 + 4))\n v10 = *(uint32_t *)(*(uint64_t *)(a1 + 8LL * a6) + 4LL * a5 + 4);\n *a4 = a3;\n result = malloc(4LL * a3);\n if (a3 > 0) {\n v12 = 0LL;\n do {\n if ((v12 & 1) != 0)\n result[v12] = v10;\n else\n result[v12] = 1;\n ++v12;\n } while (a3 != v12);\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-129", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int *func0(int **grid, int N, int k, int *returnSize) {\n int i, j, x, y, min;\n for (i = 0; i < N; i++)\n for (j = 0; j < N; j++)\n if (grid[i][j] == 1) {\n x = i;\n y = j;\n }\n min = N * N;\n if (x > 0 && grid[x - 1][y] < min) min = grid[x - 1][y];\n if (x < N - 1 && grid[x + 1][y] < min) min = grid[x + 1][y];\n if (y > 0 && grid[x][y - 1] < min) min = grid[x][y - 1];\n if (y < N - 1 && grid[x][y + 1] < min) min = grid[x][y + 1];\n *returnSize = k;\n int *out = (int *)malloc(k * sizeof(int));\n for (i = 0; i < k; i++)\n if (i % 2 == 0)\n out[i] = 1;\n else\n out[i] = min;\n return out;\n}", + "test": "#include \n#include \n\nint issame(int *a, int *b, int size) {\n for (int i = 0; i < size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int size;\n\n // Test case 1\n int grid1[3][3] = {{1, 2, 3}, {4, 5, 6}, {7, 8, 9}};\n int *grid1_ptrs[] = {grid1[0], grid1[1], grid1[2]};\n int result1[] = {1, 2, 1};\n int *out1 = func0(grid1_ptrs, 3, 3, &size);\n assert(issame(out1, result1, size));\n free(out1);\n\n // Test case 2\n int grid2[3][3] = {{5, 9, 3}, {4, 1, 6}, {7, 8, 2}};\n int *grid2_ptrs[] = {grid2[0], grid2[1], grid2[2]};\n int result2[] = {1};\n int *out2 = func0(grid2_ptrs, 3, 1, &size);\n assert(issame(out2, result2, size));\n free(out2);\n\n // Test case 3\n int grid3[4][4] = {{1, 2, 3, 4}, {5, 6, 7, 8}, {9, 10, 11, 12}, {13, 14, 15, 16}};\n int *grid3_ptrs[] = {grid3[0], grid3[1], grid3[2], grid3[3]};\n int result3[] = {1, 2, 1, 2};\n int *out3 = func0(grid3_ptrs, 4, 4, &size);\n assert(issame(out3, result3, size));\n free(out3);\n\n // Test case 4\n int grid4[4][4] = {{6, 4, 13, 10}, {5, 7, 12, 1}, {3, 16, 11, 15}, {8, 14, 9, 2}};\n int *grid4_ptrs[] = {grid4[0], grid4[1], grid4[2], grid4[3]};\n int result4[] = {1, 10, 1, 10, 1, 10, 1};\n int *out4 = func0(grid4_ptrs, 4, 7, &size);\n assert(issame(out4, result4, size));\n free(out4);\n \n // Test case 5\n int grid5[4][4] = {{8, 14, 9, 2}, {6, 4, 13, 15}, {5, 7, 1, 12}, {3, 10, 11, 16}};\n int *grid5_ptrs[] = {grid5[0], grid5[1], grid5[2], grid5[3]};\n int result5[] = {1, 7, 1, 7, 1};\n int *out5 = func0(grid5_ptrs, 4, 5, &size);\n assert(issame(out5, result5, size));\n free(out5);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r12\nmov r10, rdi\nmov r11d, esi\nmov r12, rcx\npush rbp\nmov ebp, edx\npush rbx\ntest esi, esi\njle short loc_17AE\nmovsxd rsi, esi\nxor edi, edi\nnop dword ptr [rax+00h]\nloc_1780:\nmov rdx, [r10+rdi*8]\nmov ecx, edi\nxor eax, eax\nnop dword ptr [rax+rax+00000000h]\nloc_1790:\ncmp dword ptr [rdx+rax*4], 1\ncmovz r8d, eax\ncmovz r9d, ecx\nadd rax, 1\ncmp rax, rsi\njnz short loc_1790\nadd rdi, 1\ncmp rdi, rsi\njnz short loc_1780\nloc_17AE:\nmov ebx, r11d\nimul ebx, r11d\ntest r9d, r9d\njle short loc_17CD\nmovsxd rdx, r9d\nmovsxd rax, r8d\nmov rdx, [r10+rdx*8-8]\nmov eax, [rdx+rax*4]\ncmp ebx, eax\ncmovg ebx, eax\nloc_17CD:\nsub r11d, 1\ncmp r11d, r9d\njle short loc_17E9\nmovsxd rdx, r9d\nmovsxd rax, r8d\nmov rdx, [r10+rdx*8+8]\nmov eax, [rdx+rax*4]\ncmp ebx, eax\ncmovg ebx, eax\nloc_17E9:\ntest r8d, r8d\njle short loc_1801\nmovsxd rdx, r9d\nmovsxd rax, r8d\nmov rdx, [r10+rdx*8]\nmov eax, [rdx+rax*4-4]\ncmp ebx, eax\ncmovg ebx, eax\nloc_1801:\ncmp r11d, r8d\njle short loc_181A\nmovsxd r9, r9d\nmovsxd r8, r8d\nmov rax, [r10+r9*8]\nmov eax, [rax+r8*4+4]\ncmp ebx, eax\ncmovg ebx, eax\nloc_181A:\nmov [r12], ebp\nmovsxd r12, ebp\nlea rdi, ds:0[r12*4]; size\ncall _malloc\nxor edx, edx\nmov esi, 1\ntest ebp, ebp\njle short loc_1854\nnop dword ptr [rax+00000000h]\nloc_1840:\ntest dl, 1\nmov ecx, esi\ncmovnz ecx, ebx\nmov [rax+rdx*4], ecx\nadd rdx, 1\ncmp r12, rdx\njnz short loc_1840\nloc_1854:\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, int a3, int *a4, int a5, int a6)\n{\n __int64 i; // rdi\n __int64 j; // rax\n int v10; // ebx\n _DWORD *result; // rax\n __int64 v12; // rdx\n int v13; // ecx\n\n if ( a2 > 0 )\n {\n for ( i = 0LL; i != a2; ++i )\n {\n for ( j = 0LL; j != a2; ++j )\n {\n if ( *(_DWORD *)(*(_QWORD *)(a1 + 8 * i) + 4 * j) == 1 )\n {\n a5 = j;\n a6 = i;\n }\n }\n }\n }\n v10 = a2 * a2;\n if ( a6 > 0 && v10 > *(_DWORD *)(*(_QWORD *)(a1 + 8LL * a6 - 8) + 4LL * a5) )\n v10 = *(_DWORD *)(*(_QWORD *)(a1 + 8LL * a6 - 8) + 4LL * a5);\n if ( a2 - 1 > a6 && v10 > *(_DWORD *)(*(_QWORD *)(a1 + 8LL * a6 + 8) + 4LL * a5) )\n v10 = *(_DWORD *)(*(_QWORD *)(a1 + 8LL * a6 + 8) + 4LL * a5);\n if ( a5 > 0 && v10 > *(_DWORD *)(*(_QWORD *)(a1 + 8LL * a6) + 4LL * a5 - 4) )\n v10 = *(_DWORD *)(*(_QWORD *)(a1 + 8LL * a6) + 4LL * a5 - 4);\n if ( a2 - 1 > a5 && v10 > *(_DWORD *)(*(_QWORD *)(a1 + 8LL * a6) + 4LL * a5 + 4) )\n v10 = *(_DWORD *)(*(_QWORD *)(a1 + 8LL * a6) + 4LL * a5 + 4);\n *a4 = a3;\n result = malloc(4LL * a3);\n v12 = 0LL;\n if ( a3 > 0 )\n {\n do\n {\n v13 = 1;\n if ( (v12 & 1) != 0 )\n v13 = v10;\n result[v12++] = v13;\n }\n while ( a3 != v12 );\n }\n return result;\n}", + "ida_strip_asm": "sub_1760:\nendbr64\npush r12\nmov r10, rdi\nmov r11d, esi\nmov r12, rcx\npush rbp\nmov ebp, edx\npush rbx\ntest esi, esi\njle short loc_17AE\nmovsxd rsi, esi\nxor edi, edi\nnop dword ptr [rax+00h]\nloc_1780:\nmov rdx, [r10+rdi*8]\nmov ecx, edi\nxor eax, eax\nnop dword ptr [rax+rax+00000000h]\nloc_1790:\ncmp dword ptr [rdx+rax*4], 1\ncmovz r8d, eax\ncmovz r9d, ecx\nadd rax, 1\ncmp rax, rsi\njnz short loc_1790\nadd rdi, 1\ncmp rdi, rsi\njnz short loc_1780\nloc_17AE:\nmov ebx, r11d\nimul ebx, r11d\ntest r9d, r9d\njle short loc_17CD\nmovsxd rdx, r9d\nmovsxd rax, r8d\nmov rdx, [r10+rdx*8-8]\nmov eax, [rdx+rax*4]\ncmp ebx, eax\ncmovg ebx, eax\nloc_17CD:\nsub r11d, 1\ncmp r11d, r9d\njle short loc_17E9\nmovsxd rdx, r9d\nmovsxd rax, r8d\nmov rdx, [r10+rdx*8+8]\nmov eax, [rdx+rax*4]\ncmp ebx, eax\ncmovg ebx, eax\nloc_17E9:\ntest r8d, r8d\njle short loc_1801\nmovsxd rdx, r9d\nmovsxd rax, r8d\nmov rdx, [r10+rdx*8]\nmov eax, [rdx+rax*4-4]\ncmp ebx, eax\ncmovg ebx, eax\nloc_1801:\ncmp r11d, r8d\njle short loc_181A\nmovsxd r9, r9d\nmovsxd r8, r8d\nmov rax, [r10+r9*8]\nmov eax, [rax+r8*4+4]\ncmp ebx, eax\ncmovg ebx, eax\nloc_181A:\nmov [r12], ebp\nmovsxd r12, ebp\nlea rdi, ds:0[r12*4]; size\ncall _malloc\nxor edx, edx\nmov esi, 1\ntest ebp, ebp\njle short loc_1854\nnop dword ptr [rax+00000000h]\nloc_1840:\ntest dl, 1\nmov ecx, esi\ncmovnz ecx, ebx\nmov [rax+rdx*4], ecx\nadd rdx, 1\ncmp r12, rdx\njnz short loc_1840\nloc_1854:\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1760(__int64 a1, int a2, int a3, int *a4, int a5, int a6)\n{\n __int64 i; // rdi\n __int64 j; // rax\n int v10; // ebx\n _DWORD *result; // rax\n __int64 v12; // rdx\n int v13; // ecx\n\n if ( a2 > 0 )\n {\n for ( i = 0LL; i != a2; ++i )\n {\n for ( j = 0LL; j != a2; ++j )\n {\n if ( *(_DWORD *)(*(_QWORD *)(a1 + 8 * i) + 4 * j) == 1 )\n {\n a5 = j;\n a6 = i;\n }\n }\n }\n }\n v10 = a2 * a2;\n if ( a6 > 0 && v10 > *(_DWORD *)(*(_QWORD *)(a1 + 8LL * a6 - 8) + 4LL * a5) )\n v10 = *(_DWORD *)(*(_QWORD *)(a1 + 8LL * a6 - 8) + 4LL * a5);\n if ( a2 - 1 > a6 && v10 > *(_DWORD *)(*(_QWORD *)(a1 + 8LL * a6 + 8) + 4LL * a5) )\n v10 = *(_DWORD *)(*(_QWORD *)(a1 + 8LL * a6 + 8) + 4LL * a5);\n if ( a5 > 0 && v10 > *(_DWORD *)(*(_QWORD *)(a1 + 8LL * a6) + 4LL * a5 - 4) )\n v10 = *(_DWORD *)(*(_QWORD *)(a1 + 8LL * a6) + 4LL * a5 - 4);\n if ( a2 - 1 > a5 && v10 > *(_DWORD *)(*(_QWORD *)(a1 + 8LL * a6) + 4LL * a5 + 4) )\n v10 = *(_DWORD *)(*(_QWORD *)(a1 + 8LL * a6) + 4LL * a5 + 4);\n *a4 = a3;\n result = malloc(4LL * a3);\n v12 = 0LL;\n if ( a3 > 0 )\n {\n do\n {\n v13 = 1;\n if ( (v12 & 1) != 0 )\n v13 = v10;\n result[v12++] = v13;\n }\n while ( a3 != v12 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1760(long long a1, int a2, int a3, int *a4, int a5, int a6) {\n long long i;\n long long j;\n int v10;\n uint32_t *result;\n long long v12;\n int v13;\n if (a2 > 0) {\n for (i = 0LL; i != a2; ++i) {\n for (j = 0LL; j != a2; ++j) {\n if (*(uint32_t *)(*(uint64_t *)(a1 + 8 * i) + 4 * j) == 1) {\n a5 = j;\n a6 = i;\n }\n }\n }\n }\n v10 = a2 * a2;\n if (a6 > 0 &&\n v10 > *(uint32_t *)(*(uint64_t *)(a1 + 8LL * a6 - 8) + 4LL * a5))\n v10 = *(uint32_t *)(*(uint64_t *)(a1 + 8LL * a6 - 8) + 4LL * a5);\n if (a2 - 1 > a6 &&\n v10 > *(uint32_t *)(*(uint64_t *)(a1 + 8LL * a6 + 8) + 4LL * a5))\n v10 = *(uint32_t *)(*(uint64_t *)(a1 + 8LL * a6 + 8) + 4LL * a5);\n if (a5 > 0 &&\n v10 > *(uint32_t *)(*(uint64_t *)(a1 + 8LL * a6) + 4LL * a5 - 4))\n v10 = *(uint32_t *)(*(uint64_t *)(a1 + 8LL * a6) + 4LL * a5 - 4);\n if (a2 - 1 > a5 &&\n v10 > *(uint32_t *)(*(uint64_t *)(a1 + 8LL * a6) + 4LL * a5 + 4))\n v10 = *(uint32_t *)(*(uint64_t *)(a1 + 8LL * a6) + 4LL * a5 + 4);\n *a4 = a3;\n result = malloc(4LL * a3);\n v12 = 0LL;\n if (a3 > 0) {\n do {\n v13 = 1;\n if ((v12 & 1) != 0) v13 = v10;\n result[v12++] = v13;\n } while (a3 != v12);\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, int a3, int *a4, int a5, int a6) {\n long long i;\n long long j;\n int v10;\n uint32_t *result;\n long long v12;\n int v13;\n if (a2 > 0) {\n for (i = 0LL; i != a2; ++i) {\n for (j = 0LL; j != a2; ++j) {\n if (*(uint32_t *)(*(uint64_t *)(a1 + 8 * i) + 4 * j) == 1) {\n a5 = j;\n a6 = i;\n }\n }\n }\n }\n v10 = a2 * a2;\n if (a6 > 0 &&\n v10 > *(uint32_t *)(*(uint64_t *)(a1 + 8LL * a6 - 8) + 4LL * a5))\n v10 = *(uint32_t *)(*(uint64_t *)(a1 + 8LL * a6 - 8) + 4LL * a5);\n if (a2 - 1 > a6 &&\n v10 > *(uint32_t *)(*(uint64_t *)(a1 + 8LL * a6 + 8) + 4LL * a5))\n v10 = *(uint32_t *)(*(uint64_t *)(a1 + 8LL * a6 + 8) + 4LL * a5);\n if (a5 > 0 &&\n v10 > *(uint32_t *)(*(uint64_t *)(a1 + 8LL * a6) + 4LL * a5 - 4))\n v10 = *(uint32_t *)(*(uint64_t *)(a1 + 8LL * a6) + 4LL * a5 - 4);\n if (a2 - 1 > a5 &&\n v10 > *(uint32_t *)(*(uint64_t *)(a1 + 8LL * a6) + 4LL * a5 + 4))\n v10 = *(uint32_t *)(*(uint64_t *)(a1 + 8LL * a6) + 4LL * a5 + 4);\n *a4 = a3;\n result = malloc(4LL * a3);\n v12 = 0LL;\n if (a3 > 0) {\n do {\n v13 = 1;\n if ((v12 & 1) != 0) v13 = v10;\n result[v12++] = v13;\n } while (a3 != v12);\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-129", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int *func0(int **grid, int N, int k, int *returnSize) {\n int i, j, x, y, min;\n for (i = 0; i < N; i++)\n for (j = 0; j < N; j++)\n if (grid[i][j] == 1) {\n x = i;\n y = j;\n }\n min = N * N;\n if (x > 0 && grid[x - 1][y] < min) min = grid[x - 1][y];\n if (x < N - 1 && grid[x + 1][y] < min) min = grid[x + 1][y];\n if (y > 0 && grid[x][y - 1] < min) min = grid[x][y - 1];\n if (y < N - 1 && grid[x][y + 1] < min) min = grid[x][y + 1];\n *returnSize = k;\n int *out = (int *)malloc(k * sizeof(int));\n for (i = 0; i < k; i++)\n if (i % 2 == 0)\n out[i] = 1;\n else\n out[i] = min;\n return out;\n}", + "test": "#include \n#include \n\nint issame(int *a, int *b, int size) {\n for (int i = 0; i < size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int size;\n\n // Test case 1\n int grid1[3][3] = {{1, 2, 3}, {4, 5, 6}, {7, 8, 9}};\n int *grid1_ptrs[] = {grid1[0], grid1[1], grid1[2]};\n int result1[] = {1, 2, 1};\n int *out1 = func0(grid1_ptrs, 3, 3, &size);\n assert(issame(out1, result1, size));\n free(out1);\n\n // Test case 2\n int grid2[3][3] = {{5, 9, 3}, {4, 1, 6}, {7, 8, 2}};\n int *grid2_ptrs[] = {grid2[0], grid2[1], grid2[2]};\n int result2[] = {1};\n int *out2 = func0(grid2_ptrs, 3, 1, &size);\n assert(issame(out2, result2, size));\n free(out2);\n\n // Test case 3\n int grid3[4][4] = {{1, 2, 3, 4}, {5, 6, 7, 8}, {9, 10, 11, 12}, {13, 14, 15, 16}};\n int *grid3_ptrs[] = {grid3[0], grid3[1], grid3[2], grid3[3]};\n int result3[] = {1, 2, 1, 2};\n int *out3 = func0(grid3_ptrs, 4, 4, &size);\n assert(issame(out3, result3, size));\n free(out3);\n\n // Test case 4\n int grid4[4][4] = {{6, 4, 13, 10}, {5, 7, 12, 1}, {3, 16, 11, 15}, {8, 14, 9, 2}};\n int *grid4_ptrs[] = {grid4[0], grid4[1], grid4[2], grid4[3]};\n int result4[] = {1, 10, 1, 10, 1, 10, 1};\n int *out4 = func0(grid4_ptrs, 4, 7, &size);\n assert(issame(out4, result4, size));\n free(out4);\n \n // Test case 5\n int grid5[4][4] = {{8, 14, 9, 2}, {6, 4, 13, 15}, {5, 7, 1, 12}, {3, 10, 11, 16}};\n int *grid5_ptrs[] = {grid5[0], grid5[1], grid5[2], grid5[3]};\n int result5[] = {1, 7, 1, 7, 1};\n int *out5 = func0(grid5_ptrs, 4, 5, &size);\n assert(issame(out5, result5, size));\n free(out5);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\nlea r15d, [rsi-1]\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nmov ebx, edx\nmov rdx, rcx\nsub rsp, 28h\ntest esi, esi\njle loc_19CA\nmovsxd rdi, esi\nmov ecx, esi\nmov [rsp+58h+var_44], ebx\nmov r14d, esi\nshr ecx, 2\nmov [rsp+58h+var_50], rdi\nlea r15d, [rsi-1]\nand r14d, 0FFFFFFFCh\nmov [rsp+58h+var_40], rdx\nshl rcx, 4\nmovdqa xmm7, cs:xmmword_20E0\nxor r9d, r9d\nmovdqa xmm9, cs:xmmword_20F0\nmov r13, rcx\npcmpeqd xmm10, xmm10\nnop word ptr [rax+rax+00000000h]\nloc_17D0:\nmov rdx, [r12+r9*8]\nmov r11d, r9d\ncmp r15d, 5\njbe loc_1B30\nmovd xmm4, eax\nlea rcx, [rdx+r13]\npxor xmm2, xmm2\nmov rax, rdx\npshufd xmm5, xmm4, 0\nmovd xmm4, r9d\nmovdqa xmm6, xmm10\nmovdqa xmm3, cs:xmmword_20D0\npshufd xmm11, xmm4, 0\nmovdqa xmm4, cs:xmmword_20C0\nnop dword ptr [rax]\nloc_1818:\nmovdqu xmm0, xmmword ptr [rax]\nmovdqa xmm8, xmm11\nmovdqa xmm1, xmm3\nadd rax, 10h\npaddd xmm3, xmm7\npcmpeqd xmm0, xmm9\nmovdqa xmm12, xmm0\npand xmm8, xmm0\npand xmm1, xmm0\npandn xmm12, xmm5\nmovdqa xmm5, xmm12\npor xmm5, xmm8\nmovdqa xmm8, xmm0\npandn xmm8, xmm6\nmovdqa xmm6, xmm8\npor xmm6, xmm1\nmovdqa xmm1, xmm4\npaddd xmm4, xmm7\npand xmm1, xmm0\npandn xmm0, xmm2\nmovdqa xmm2, xmm0\npor xmm2, xmm1\ncmp rax, rcx\njnz short loc_1818\nmovdqa xmm0, xmm6\nmovd ebp, xmm2\npsrldq xmm0, 8\nmovdqa xmm1, xmm0\npcmpgtd xmm1, xmm6\npand xmm0, xmm1\npandn xmm1, xmm6\npor xmm1, xmm0\nmovdqa xmm3, xmm1\npsrldq xmm3, 4\nmovdqa xmm0, xmm3\npcmpgtd xmm0, xmm1\npand xmm3, xmm0\npandn xmm0, xmm1\npor xmm0, xmm3\nmovd eax, xmm0\npshufd xmm0, xmm2, 55h ; 'U'\nmovd r10d, xmm0\ncmp eax, 0FFFFFFFFh\nmovdqa xmm0, xmm2\ncmovnz r8d, eax\nmov ecx, r10d\npunpckhdq xmm0, xmm2\ncmp ebp, r10d\ncmovnb ecx, ebp\nmovd edi, xmm0\npshufd xmm0, xmm5, 0FFh\nmovd ebx, xmm0\ncmp ecx, edi\njnb loc_1B00\npunpckhdq xmm5, xmm5\nmovd eax, xmm5\nloc_1900:\ncmp ecx, edi\npshufd xmm2, xmm2, 0FFh\ncmovb ecx, edi\nmovd edi, xmm2\ncmp ecx, edi\nmov ecx, r14d\ncmovb eax, ebx\ncmp esi, r14d\njz loc_19AF\nloc_191F:\nmovsxd r10, ecx\ncmp dword ptr [rdx+r10*4], 1\nlea rdi, ds:0[r10*4]\nlea r10d, [rcx+1]\ncmovz r8d, ecx\ncmovz eax, r11d\ncmp esi, r10d\njle short loc_19AF\ncmp dword ptr [rdx+rdi+4], 1\ncmovnz r10d, r8d\nlea r8d, [rcx+2]\ncmovz eax, r11d\ncmp esi, r8d\njle loc_1B20\ncmp dword ptr [rdx+rdi+8], 1\ncmovnz r8d, r10d\nlea r10d, [rcx+3]\ncmovz eax, r11d\ncmp esi, r10d\njle short loc_19AF\ncmp dword ptr [rdx+rdi+0Ch], 1\nlea ebx, [rcx+4]\ncmovnz r10d, r8d\ncmovz eax, r11d\ncmp ebx, esi\njge loc_1B20\nlea r8d, [rcx+5]\ncmp dword ptr [rdx+rdi+10h], 1\ncmovnz ebx, r10d\ncmovz eax, r11d\ncmp r8d, esi\njge loc_1B37\ncmp dword ptr [rdx+rdi+14h], 1\ncmovnz r8d, ebx\ncmovz eax, r11d\nloc_19AF:\nmov rbx, [rsp+58h+var_50]\nadd r9, 1\ncmp r9, rbx\njnz loc_17D0\nmov ebx, [rsp+58h+var_44]\nmov rdx, [rsp+58h+var_40]\nloc_19CA:\nimul esi, esi\nmov ebp, esi\ntest eax, eax\njle short loc_19E6\nmovsxd rsi, eax\nmovsxd rcx, r8d\nmov rsi, [r12+rsi*8-8]\nmov ecx, [rsi+rcx*4]\ncmp ebp, ecx\ncmovg ebp, ecx\nloc_19E6:\ncmp r15d, eax\njle short loc_19FE\nmovsxd rsi, eax\nmovsxd rcx, r8d\nmov rsi, [r12+rsi*8+8]\nmov ecx, [rsi+rcx*4]\ncmp ebp, ecx\ncmovg ebp, ecx\nloc_19FE:\ntest r8d, r8d\njle short loc_1A16\nmovsxd rsi, eax\nmovsxd rcx, r8d\nmov rsi, [r12+rsi*8]\nmov ecx, [rsi+rcx*4-4]\ncmp ebp, ecx\ncmovg ebp, ecx\nloc_1A16:\ncmp r15d, r8d\njle short loc_1A2E\ncdqe\nmovsxd r8, r8d\nmov rax, [r12+rax*8]\nmov eax, [rax+r8*4+4]\ncmp ebp, eax\ncmovg ebp, eax\nloc_1A2E:\nmov [rdx], ebx\nmovsxd rdi, ebx\nshl rdi, 2; size\ncall _malloc\ntest ebx, ebx\njle loc_1AEC\nlea edx, [rbx-1]\ncmp edx, 2\njbe loc_1B3F\nmov ecx, ebx\nmovd xmm7, ebp\nmovdqa xmm1, cs:xmmword_20D0\nmovdqa xmm5, cs:xmmword_20E0\nshr ecx, 2\npshufd xmm6, xmm7, 0\npxor xmm4, xmm4\nmov rdx, rax\nshl rcx, 4\nmovdqa xmm2, cs:xmmword_20F0\nadd rcx, rax\nnop dword ptr [rax+00h]\nloc_1A88:\nmovdqa xmm0, xmm1\nmovdqa xmm3, xmm2\npaddd xmm1, xmm5\nadd rdx, 10h\npand xmm0, xmm2\npcmpeqd xmm0, xmm4\npand xmm3, xmm0\npandn xmm0, xmm6\npor xmm0, xmm3\nmovups xmmword ptr [rdx-10h], xmm0\ncmp rcx, rdx\njnz short loc_1A88\nmov edx, ebx\nand edx, 0FFFFFFFCh\ntest bl, 3\njz short loc_1AEC\nmov ecx, edx\nlea edi, [rdx+1]\nmov dword ptr [rax+rcx*4], 1\nlea rcx, ds:4[rcx*4]\nlea rsi, [rax+rcx]\ncmp ebx, edi\njle short loc_1AEC\nloc_1ADB:\nadd edx, 2\nmov [rsi], ebp\ncmp edx, ebx\njge short loc_1AEC\nmov dword ptr [rax+rcx+4], 1\nloc_1AEC:\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1B00:\npshufd xmm0, xmm5, 55h ; 'U'\nmovd eax, xmm5\ncmp ebp, r10d\nmovd [rsp+58h+var_48], xmm0\ncmovb eax, [rsp+58h+var_48]\njmp loc_1900\nloc_1B20:\nmov r8d, r10d\njmp loc_19AF\nloc_1B30:\nxor ecx, ecx\njmp loc_191F\nloc_1B37:\nmov r8d, ebx\njmp loc_19AF\nloc_1B3F:\nmov dword ptr [rax], 1\nlea rsi, [rax+4]\nmov ecx, 4\nxor edx, edx\ncmp ebx, 1\njnz short loc_1ADB\njmp short loc_1AEC", + "ida_pseudo": "__m128i *__fastcall func0(__int64 a1, int a2, int a3, int *a4, int a5)\n{\n signed int v5; // eax\n signed int v6; // r15d\n int *v9; // rdx\n __m128i si128; // xmm7\n __int64 v11; // r9\n __m128i v12; // xmm9\n __int64 v13; // rdx\n __m128i v14; // xmm4\n __m128i v15; // xmm2\n const __m128i *v16; // rax\n __m128i v17; // xmm5\n __m128i v18; // xmm6\n __m128i v19; // xmm3\n __m128i v20; // xmm11\n __m128i v21; // xmm4\n __m128i v22; // xmm0\n __m128i v23; // xmm1\n __m128i v24; // xmm0\n __m128i v25; // xmm1\n unsigned int v26; // ebp\n __m128i v27; // xmm0\n __m128i v28; // xmm1\n __m128i v29; // xmm1\n __m128i v30; // xmm3\n __m128i v31; // xmm0\n int v32; // eax\n unsigned int v33; // r10d\n unsigned int v34; // ecx\n __m128i v35; // xmm0\n unsigned int v36; // edi\n int v37; // ebx\n __m128i v38; // xmm2\n bool v39; // cf\n signed int v40; // ecx\n __int64 v41; // rdi\n int v42; // r10d\n int v43; // ebx\n signed int v44; // ebp\n signed int v45; // eax\n __m128i *result; // rax\n __m128i v47; // xmm1\n __m128i v48; // xmm5\n __m128i v49; // xmm6\n __m128i *v50; // rdx\n __m128i v51; // xmm2\n __m128i v52; // xmm0\n __m128i v53; // xmm0\n unsigned int v54; // edx\n __int64 v55; // rcx\n signed int *v56; // rsi\n int v57; // [rsp+10h] [rbp-48h]\n int v58; // [rsp+14h] [rbp-44h]\n\n v6 = a2 - 1;\n v9 = a4;\n if ( a2 > 0 )\n {\n v58 = a3;\n v6 = a2 - 1;\n si128 = _mm_load_si128((const __m128i *)&xmmword_20E0);\n v11 = 0LL;\n v12 = _mm_load_si128((const __m128i *)&xmmword_20F0);\n while ( 1 )\n {\n v13 = *(_QWORD *)(a1 + 8 * v11);\n if ( (unsigned int)v6 <= 5 )\n {\n v40 = 0;\n }\n else\n {\n v14 = _mm_cvtsi32_si128(v5);\n v15 = 0LL;\n v16 = *(const __m128i **)(a1 + 8 * v11);\n v17 = _mm_shuffle_epi32(v14, 0);\n v18 = (__m128i)-1LL;\n v19 = _mm_load_si128((const __m128i *)&xmmword_20D0);\n v20 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v11), 0);\n v21 = _mm_load_si128((const __m128i *)&xmmword_20C0);\n do\n {\n v22 = _mm_loadu_si128(v16);\n v23 = v19;\n ++v16;\n v19 = _mm_add_epi32(v19, si128);\n v24 = _mm_cmpeq_epi32(v22, v12);\n v17 = _mm_or_si128(_mm_andnot_si128(v24, v17), _mm_and_si128(v20, v24));\n v18 = _mm_or_si128(_mm_andnot_si128(v24, v18), _mm_and_si128(v23, v24));\n v25 = v21;\n v21 = _mm_add_epi32(v21, si128);\n v15 = _mm_or_si128(_mm_andnot_si128(v24, v15), _mm_and_si128(v25, v24));\n }\n while ( v16 != (const __m128i *)(v13 + 16LL * ((unsigned int)a2 >> 2)) );\n v26 = _mm_cvtsi128_si32(v15);\n v27 = _mm_srli_si128(v18, 8);\n v28 = _mm_cmpgt_epi32(v27, v18);\n v29 = _mm_or_si128(_mm_andnot_si128(v28, v18), _mm_and_si128(v27, v28));\n v30 = _mm_srli_si128(v29, 4);\n v31 = _mm_cmpgt_epi32(v30, v29);\n v32 = _mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v31, v29), _mm_and_si128(v30, v31)));\n v33 = _mm_cvtsi128_si32(_mm_shuffle_epi32(v15, 85));\n if ( v32 != -1 )\n a5 = v32;\n v34 = v33;\n v35 = _mm_unpackhi_epi32(v15, v15);\n if ( v26 >= v33 )\n v34 = v26;\n v36 = _mm_cvtsi128_si32(v35);\n v37 = _mm_cvtsi128_si32(_mm_shuffle_epi32(v17, 255));\n if ( v34 >= v36 )\n {\n v5 = _mm_cvtsi128_si32(v17);\n v57 = _mm_cvtsi128_si32(_mm_shuffle_epi32(v17, 85));\n if ( v26 < v33 )\n v5 = v57;\n }\n else\n {\n v5 = _mm_cvtsi128_si32(_mm_unpackhi_epi32(v17, v17));\n }\n v38 = _mm_shuffle_epi32(v15, 255);\n if ( v34 < v36 )\n v34 = v36;\n v39 = v34 < _mm_cvtsi128_si32(v38);\n v40 = a2 & 0xFFFFFFFC;\n if ( v39 )\n v5 = v37;\n if ( a2 == (a2 & 0xFFFFFFFC) )\n goto LABEL_41;\n }\n v41 = 4LL * v40;\n v42 = v40 + 1;\n if ( *(_DWORD *)(v13 + v41) == 1 )\n {\n a5 = v40;\n v5 = v11;\n }\n if ( a2 > v42 )\n {\n if ( *(_DWORD *)(v13 + v41 + 4) != 1 )\n v42 = a5;\n a5 = v40 + 2;\n if ( *(_DWORD *)(v13 + v41 + 4) == 1 )\n v5 = v11;\n if ( a2 <= a5 )\n goto LABEL_67;\n if ( *(_DWORD *)(v13 + v41 + 8) != 1 )\n a5 = v42;\n v42 = v40 + 3;\n if ( *(_DWORD *)(v13 + v41 + 8) == 1 )\n v5 = v11;\n if ( a2 <= v42 )\n goto LABEL_41;\n v43 = v40 + 4;\n if ( *(_DWORD *)(v13 + v41 + 12) == 1 )\n v5 = v11;\n else\n v42 = a5;\n if ( v43 >= a2 )\n {\nLABEL_67:\n a5 = v42;\n }\n else\n {\n a5 = v40 + 5;\n if ( *(_DWORD *)(v13 + v41 + 16) == 1 )\n v5 = v11;\n else\n v43 = v42;\n if ( a5 >= a2 )\n {\n a5 = v43;\n }\n else if ( *(_DWORD *)(v13 + v41 + 20) == 1 )\n {\n v5 = v11;\n }\n else\n {\n a5 = v43;\n }\n }\n }\nLABEL_41:\n if ( ++v11 == a2 )\n {\n a3 = v58;\n v9 = a4;\n break;\n }\n }\n }\n v44 = a2 * a2;\n if ( v5 > 0 && v44 > *(_DWORD *)(*(_QWORD *)(a1 + 8LL * v5 - 8) + 4LL * a5) )\n v44 = *(_DWORD *)(*(_QWORD *)(a1 + 8LL * v5 - 8) + 4LL * a5);\n if ( v6 > v5 && v44 > *(_DWORD *)(*(_QWORD *)(a1 + 8LL * v5 + 8) + 4LL * a5) )\n v44 = *(_DWORD *)(*(_QWORD *)(a1 + 8LL * v5 + 8) + 4LL * a5);\n if ( a5 > 0 && v44 > *(_DWORD *)(*(_QWORD *)(a1 + 8LL * v5) + 4LL * a5 - 4) )\n v44 = *(_DWORD *)(*(_QWORD *)(a1 + 8LL * v5) + 4LL * a5 - 4);\n if ( v6 > a5 )\n {\n v45 = *(_DWORD *)(*(_QWORD *)(a1 + 8LL * v5) + 4LL * a5 + 4);\n if ( v44 > v45 )\n v44 = v45;\n }\n *v9 = a3;\n result = (__m128i *)malloc(4LL * a3);\n if ( a3 > 0 )\n {\n if ( (unsigned int)(a3 - 1) <= 2 )\n {\n result->m128i_i32[0] = 1;\n v56 = &result->m128i_i32[1];\n v55 = 4LL;\n v54 = 0;\n if ( a3 == 1 )\n return result;\n goto LABEL_61;\n }\n v47 = _mm_load_si128((const __m128i *)&xmmword_20D0);\n v48 = _mm_load_si128((const __m128i *)&xmmword_20E0);\n v49 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v44), 0);\n v50 = result;\n v51 = _mm_load_si128((const __m128i *)&xmmword_20F0);\n do\n {\n v52 = v47;\n v47 = _mm_add_epi32(v47, v48);\n ++v50;\n v53 = _mm_cmpeq_epi32(_mm_and_si128(v52, v51), (__m128i)0LL);\n v50[-1] = _mm_or_si128(_mm_andnot_si128(v53, v49), _mm_and_si128(v51, v53));\n }\n while ( &result[(unsigned int)a3 >> 2] != v50 );\n v54 = a3 & 0x7FFFFFFC;\n if ( (a3 & 3) != 0 )\n {\n result->m128i_i32[v54] = 1;\n v55 = 4LL * v54 + 4;\n v56 = (__int32 *)((char *)result->m128i_i32 + v55);\n if ( a3 > (int)(v54 + 1) )\n {\nLABEL_61:\n *v56 = v44;\n if ( (int)(v54 + 2) < a3 )\n *(__int32 *)((char *)&result->m128i_i32[1] + v55) = 1;\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1760:\nendbr64\npush r15\nlea r15d, [rsi-1]\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nmov ebx, edx\nmov rdx, rcx\nsub rsp, 28h\ntest esi, esi\njle loc_19CA\nmovsxd rdi, esi\nmov ecx, esi\nmov [rsp+58h+var_44], ebx\nmov r14d, esi\nshr ecx, 2\nmov [rsp+58h+var_50], rdi\nlea r15d, [rsi-1]\nand r14d, 0FFFFFFFCh\nmov [rsp+58h+var_40], rdx\nshl rcx, 4\nmovdqa xmm7, cs:xmmword_20E0\nxor r9d, r9d\nmovdqa xmm9, cs:xmmword_20F0\nmov r13, rcx\npcmpeqd xmm10, xmm10\nnop word ptr [rax+rax+00000000h]\nloc_17D0:\nmov rdx, [r12+r9*8]\nmov r11d, r9d\ncmp r15d, 5\njbe loc_1B30\nmovd xmm4, eax\nlea rcx, [rdx+r13]\npxor xmm2, xmm2\nmov rax, rdx\npshufd xmm5, xmm4, 0\nmovd xmm4, r9d\nmovdqa xmm6, xmm10\nmovdqa xmm3, cs:xmmword_20D0\npshufd xmm11, xmm4, 0\nmovdqa xmm4, cs:xmmword_20C0\nnop dword ptr [rax]\nloc_1818:\nmovdqu xmm0, xmmword ptr [rax]\nmovdqa xmm8, xmm11\nmovdqa xmm1, xmm3\nadd rax, 10h\npaddd xmm3, xmm7\npcmpeqd xmm0, xmm9\nmovdqa xmm12, xmm0\npand xmm8, xmm0\npand xmm1, xmm0\npandn xmm12, xmm5\nmovdqa xmm5, xmm12\npor xmm5, xmm8\nmovdqa xmm8, xmm0\npandn xmm8, xmm6\nmovdqa xmm6, xmm8\npor xmm6, xmm1\nmovdqa xmm1, xmm4\npaddd xmm4, xmm7\npand xmm1, xmm0\npandn xmm0, xmm2\nmovdqa xmm2, xmm0\npor xmm2, xmm1\ncmp rax, rcx\njnz short loc_1818\nmovdqa xmm0, xmm6\nmovd ebp, xmm2\npsrldq xmm0, 8\nmovdqa xmm1, xmm0\npcmpgtd xmm1, xmm6\npand xmm0, xmm1\npandn xmm1, xmm6\npor xmm1, xmm0\nmovdqa xmm3, xmm1\npsrldq xmm3, 4\nmovdqa xmm0, xmm3\npcmpgtd xmm0, xmm1\npand xmm3, xmm0\npandn xmm0, xmm1\npor xmm0, xmm3\nmovd eax, xmm0\npshufd xmm0, xmm2, 55h ; 'U'\nmovd r10d, xmm0\ncmp eax, 0FFFFFFFFh\nmovdqa xmm0, xmm2\ncmovnz r8d, eax\nmov ecx, r10d\npunpckhdq xmm0, xmm2\ncmp ebp, r10d\ncmovnb ecx, ebp\nmovd edi, xmm0\npshufd xmm0, xmm5, 0FFh\nmovd ebx, xmm0\ncmp ecx, edi\njnb loc_1B00\npunpckhdq xmm5, xmm5\nmovd eax, xmm5\nloc_1900:\ncmp ecx, edi\npshufd xmm2, xmm2, 0FFh\ncmovb ecx, edi\nmovd edi, xmm2\ncmp ecx, edi\nmov ecx, r14d\ncmovb eax, ebx\ncmp esi, r14d\njz loc_19AF\nloc_191F:\nmovsxd r10, ecx\ncmp dword ptr [rdx+r10*4], 1\nlea rdi, ds:0[r10*4]\nlea r10d, [rcx+1]\ncmovz r8d, ecx\ncmovz eax, r11d\ncmp esi, r10d\njle short loc_19AF\ncmp dword ptr [rdx+rdi+4], 1\ncmovnz r10d, r8d\nlea r8d, [rcx+2]\ncmovz eax, r11d\ncmp esi, r8d\njle loc_1B20\ncmp dword ptr [rdx+rdi+8], 1\ncmovnz r8d, r10d\nlea r10d, [rcx+3]\ncmovz eax, r11d\ncmp esi, r10d\njle short loc_19AF\ncmp dword ptr [rdx+rdi+0Ch], 1\nlea ebx, [rcx+4]\ncmovnz r10d, r8d\ncmovz eax, r11d\ncmp ebx, esi\njge loc_1B20\nlea r8d, [rcx+5]\ncmp dword ptr [rdx+rdi+10h], 1\ncmovnz ebx, r10d\ncmovz eax, r11d\ncmp r8d, esi\njge loc_1B37\ncmp dword ptr [rdx+rdi+14h], 1\ncmovnz r8d, ebx\ncmovz eax, r11d\nloc_19AF:\nmov rbx, [rsp+58h+var_50]\nadd r9, 1\ncmp r9, rbx\njnz loc_17D0\nmov ebx, [rsp+58h+var_44]\nmov rdx, [rsp+58h+var_40]\nloc_19CA:\nimul esi, esi\nmov ebp, esi\ntest eax, eax\njle short loc_19E6\nmovsxd rsi, eax\nmovsxd rcx, r8d\nmov rsi, [r12+rsi*8-8]\nmov ecx, [rsi+rcx*4]\ncmp ebp, ecx\ncmovg ebp, ecx\nloc_19E6:\ncmp r15d, eax\njle short loc_19FE\nmovsxd rsi, eax\nmovsxd rcx, r8d\nmov rsi, [r12+rsi*8+8]\nmov ecx, [rsi+rcx*4]\ncmp ebp, ecx\ncmovg ebp, ecx\nloc_19FE:\ntest r8d, r8d\njle short loc_1A16\nmovsxd rsi, eax\nmovsxd rcx, r8d\nmov rsi, [r12+rsi*8]\nmov ecx, [rsi+rcx*4-4]\ncmp ebp, ecx\ncmovg ebp, ecx\nloc_1A16:\ncmp r15d, r8d\njle short loc_1A2E\ncdqe\nmovsxd r8, r8d\nmov rax, [r12+rax*8]\nmov eax, [rax+r8*4+4]\ncmp ebp, eax\ncmovg ebp, eax\nloc_1A2E:\nmov [rdx], ebx\nmovsxd rdi, ebx\nshl rdi, 2; size\ncall _malloc\ntest ebx, ebx\njle loc_1AEC\nlea edx, [rbx-1]\ncmp edx, 2\njbe loc_1B3F\nmov ecx, ebx\nmovd xmm7, ebp\nmovdqa xmm1, cs:xmmword_20D0\nmovdqa xmm5, cs:xmmword_20E0\nshr ecx, 2\npshufd xmm6, xmm7, 0\npxor xmm4, xmm4\nmov rdx, rax\nshl rcx, 4\nmovdqa xmm2, cs:xmmword_20F0\nadd rcx, rax\nnop dword ptr [rax+00h]\nloc_1A88:\nmovdqa xmm0, xmm1\nmovdqa xmm3, xmm2\npaddd xmm1, xmm5\nadd rdx, 10h\npand xmm0, xmm2\npcmpeqd xmm0, xmm4\npand xmm3, xmm0\npandn xmm0, xmm6\npor xmm0, xmm3\nmovups xmmword ptr [rdx-10h], xmm0\ncmp rcx, rdx\njnz short loc_1A88\nmov edx, ebx\nand edx, 0FFFFFFFCh\ntest bl, 3\njz short loc_1AEC\nmov ecx, edx\nlea edi, [rdx+1]\nmov dword ptr [rax+rcx*4], 1\nlea rcx, ds:4[rcx*4]\nlea rsi, [rax+rcx]\ncmp ebx, edi\njle short loc_1AEC\nloc_1ADB:\nadd edx, 2\nmov [rsi], ebp\ncmp edx, ebx\njge short loc_1AEC\nmov dword ptr [rax+rcx+4], 1\nloc_1AEC:\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1B00:\npshufd xmm0, xmm5, 55h ; 'U'\nmovd eax, xmm5\ncmp ebp, r10d\nmovd [rsp+58h+var_48], xmm0\ncmovb eax, [rsp+58h+var_48]\njmp loc_1900\nloc_1B20:\nmov r8d, r10d\njmp loc_19AF\nloc_1B30:\nxor ecx, ecx\njmp loc_191F\nloc_1B37:\nmov r8d, ebx\njmp loc_19AF\nloc_1B3F:\nmov dword ptr [rax], 1\nlea rsi, [rax+4]\nmov ecx, 4\nxor edx, edx\ncmp ebx, 1\njnz short loc_1ADB\njmp short loc_1AEC", + "ida_strip_pseudo": "__m128i *__fastcall sub_1760(__int64 a1, int a2, int a3, int *a4, int a5)\n{\n signed int v5; // eax\n signed int v6; // r15d\n int *v9; // rdx\n __m128i si128; // xmm7\n __int64 v11; // r9\n __m128i v12; // xmm9\n __int64 v13; // rdx\n __m128i v14; // xmm4\n __m128i v15; // xmm2\n const __m128i *v16; // rax\n __m128i v17; // xmm5\n __m128i v18; // xmm6\n __m128i v19; // xmm3\n __m128i v20; // xmm11\n __m128i v21; // xmm4\n __m128i v22; // xmm0\n __m128i v23; // xmm1\n __m128i v24; // xmm0\n __m128i v25; // xmm1\n unsigned int v26; // ebp\n __m128i v27; // xmm0\n __m128i v28; // xmm1\n __m128i v29; // xmm1\n __m128i v30; // xmm3\n __m128i v31; // xmm0\n int v32; // eax\n unsigned int v33; // r10d\n unsigned int v34; // ecx\n __m128i v35; // xmm0\n unsigned int v36; // edi\n int v37; // ebx\n __m128i v38; // xmm2\n bool v39; // cf\n signed int v40; // ecx\n __int64 v41; // rdi\n int v42; // r10d\n int v43; // ebx\n signed int v44; // ebp\n signed int v45; // eax\n __m128i *result; // rax\n __m128i v47; // xmm1\n __m128i v48; // xmm5\n __m128i v49; // xmm6\n __m128i *v50; // rdx\n __m128i v51; // xmm2\n __m128i v52; // xmm0\n __m128i v53; // xmm0\n unsigned int v54; // edx\n __int64 v55; // rcx\n signed int *v56; // rsi\n int v57; // [rsp+10h] [rbp-48h]\n int v58; // [rsp+14h] [rbp-44h]\n\n v6 = a2 - 1;\n v9 = a4;\n if ( a2 > 0 )\n {\n v58 = a3;\n v6 = a2 - 1;\n si128 = _mm_load_si128((const __m128i *)&xmmword_20E0);\n v11 = 0LL;\n v12 = _mm_load_si128((const __m128i *)&xmmword_20F0);\n while ( 1 )\n {\n v13 = *(_QWORD *)(a1 + 8 * v11);\n if ( (unsigned int)v6 <= 5 )\n {\n v40 = 0;\n }\n else\n {\n v14 = _mm_cvtsi32_si128(v5);\n v15 = 0LL;\n v16 = *(const __m128i **)(a1 + 8 * v11);\n v17 = _mm_shuffle_epi32(v14, 0);\n v18 = (__m128i)-1LL;\n v19 = _mm_load_si128((const __m128i *)&xmmword_20D0);\n v20 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v11), 0);\n v21 = _mm_load_si128((const __m128i *)&xmmword_20C0);\n do\n {\n v22 = _mm_loadu_si128(v16);\n v23 = v19;\n ++v16;\n v19 = _mm_add_epi32(v19, si128);\n v24 = _mm_cmpeq_epi32(v22, v12);\n v17 = _mm_or_si128(_mm_andnot_si128(v24, v17), _mm_and_si128(v20, v24));\n v18 = _mm_or_si128(_mm_andnot_si128(v24, v18), _mm_and_si128(v23, v24));\n v25 = v21;\n v21 = _mm_add_epi32(v21, si128);\n v15 = _mm_or_si128(_mm_andnot_si128(v24, v15), _mm_and_si128(v25, v24));\n }\n while ( v16 != (const __m128i *)(v13 + 16LL * ((unsigned int)a2 >> 2)) );\n v26 = _mm_cvtsi128_si32(v15);\n v27 = _mm_srli_si128(v18, 8);\n v28 = _mm_cmpgt_epi32(v27, v18);\n v29 = _mm_or_si128(_mm_andnot_si128(v28, v18), _mm_and_si128(v27, v28));\n v30 = _mm_srli_si128(v29, 4);\n v31 = _mm_cmpgt_epi32(v30, v29);\n v32 = _mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v31, v29), _mm_and_si128(v30, v31)));\n v33 = _mm_cvtsi128_si32(_mm_shuffle_epi32(v15, 85));\n if ( v32 != -1 )\n a5 = v32;\n v34 = v33;\n v35 = _mm_unpackhi_epi32(v15, v15);\n if ( v26 >= v33 )\n v34 = v26;\n v36 = _mm_cvtsi128_si32(v35);\n v37 = _mm_cvtsi128_si32(_mm_shuffle_epi32(v17, 255));\n if ( v34 >= v36 )\n {\n v5 = _mm_cvtsi128_si32(v17);\n v57 = _mm_cvtsi128_si32(_mm_shuffle_epi32(v17, 85));\n if ( v26 < v33 )\n v5 = v57;\n }\n else\n {\n v5 = _mm_cvtsi128_si32(_mm_unpackhi_epi32(v17, v17));\n }\n v38 = _mm_shuffle_epi32(v15, 255);\n if ( v34 < v36 )\n v34 = v36;\n v39 = v34 < _mm_cvtsi128_si32(v38);\n v40 = a2 & 0xFFFFFFFC;\n if ( v39 )\n v5 = v37;\n if ( a2 == (a2 & 0xFFFFFFFC) )\n goto LABEL_41;\n }\n v41 = 4LL * v40;\n v42 = v40 + 1;\n if ( *(_DWORD *)(v13 + v41) == 1 )\n {\n a5 = v40;\n v5 = v11;\n }\n if ( a2 > v42 )\n {\n if ( *(_DWORD *)(v13 + v41 + 4) != 1 )\n v42 = a5;\n a5 = v40 + 2;\n if ( *(_DWORD *)(v13 + v41 + 4) == 1 )\n v5 = v11;\n if ( a2 <= a5 )\n goto LABEL_67;\n if ( *(_DWORD *)(v13 + v41 + 8) != 1 )\n a5 = v42;\n v42 = v40 + 3;\n if ( *(_DWORD *)(v13 + v41 + 8) == 1 )\n v5 = v11;\n if ( a2 <= v42 )\n goto LABEL_41;\n v43 = v40 + 4;\n if ( *(_DWORD *)(v13 + v41 + 12) == 1 )\n v5 = v11;\n else\n v42 = a5;\n if ( v43 >= a2 )\n {\nLABEL_67:\n a5 = v42;\n }\n else\n {\n a5 = v40 + 5;\n if ( *(_DWORD *)(v13 + v41 + 16) == 1 )\n v5 = v11;\n else\n v43 = v42;\n if ( a5 >= a2 )\n {\n a5 = v43;\n }\n else if ( *(_DWORD *)(v13 + v41 + 20) == 1 )\n {\n v5 = v11;\n }\n else\n {\n a5 = v43;\n }\n }\n }\nLABEL_41:\n if ( ++v11 == a2 )\n {\n a3 = v58;\n v9 = a4;\n break;\n }\n }\n }\n v44 = a2 * a2;\n if ( v5 > 0 && v44 > *(_DWORD *)(*(_QWORD *)(a1 + 8LL * v5 - 8) + 4LL * a5) )\n v44 = *(_DWORD *)(*(_QWORD *)(a1 + 8LL * v5 - 8) + 4LL * a5);\n if ( v6 > v5 && v44 > *(_DWORD *)(*(_QWORD *)(a1 + 8LL * v5 + 8) + 4LL * a5) )\n v44 = *(_DWORD *)(*(_QWORD *)(a1 + 8LL * v5 + 8) + 4LL * a5);\n if ( a5 > 0 && v44 > *(_DWORD *)(*(_QWORD *)(a1 + 8LL * v5) + 4LL * a5 - 4) )\n v44 = *(_DWORD *)(*(_QWORD *)(a1 + 8LL * v5) + 4LL * a5 - 4);\n if ( v6 > a5 )\n {\n v45 = *(_DWORD *)(*(_QWORD *)(a1 + 8LL * v5) + 4LL * a5 + 4);\n if ( v44 > v45 )\n v44 = v45;\n }\n *v9 = a3;\n result = (__m128i *)malloc(4LL * a3);\n if ( a3 > 0 )\n {\n if ( (unsigned int)(a3 - 1) <= 2 )\n {\n result->m128i_i32[0] = 1;\n v56 = &result->m128i_i32[1];\n v55 = 4LL;\n v54 = 0;\n if ( a3 == 1 )\n return result;\n goto LABEL_61;\n }\n v47 = _mm_load_si128((const __m128i *)&xmmword_20D0);\n v48 = _mm_load_si128((const __m128i *)&xmmword_20E0);\n v49 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v44), 0);\n v50 = result;\n v51 = _mm_load_si128((const __m128i *)&xmmword_20F0);\n do\n {\n v52 = v47;\n v47 = _mm_add_epi32(v47, v48);\n ++v50;\n v53 = _mm_cmpeq_epi32(_mm_and_si128(v52, v51), (__m128i)0LL);\n v50[-1] = _mm_or_si128(_mm_andnot_si128(v53, v49), _mm_and_si128(v51, v53));\n }\n while ( &result[(unsigned int)a3 >> 2] != v50 );\n v54 = a3 & 0x7FFFFFFC;\n if ( (a3 & 3) != 0 )\n {\n result->m128i_i32[v54] = 1;\n v55 = 4LL * v54 + 4;\n v56 = (__int32 *)((char *)result->m128i_i32 + v55);\n if ( a3 > (int)(v54 + 1) )\n {\nLABEL_61:\n *v56 = v44;\n if ( (int)(v54 + 2) < a3 )\n *(__int32 *)((char *)&result->m128i_i32[1] + v55) = 1;\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__m128i *sub_1760(long long a1, int a2, int a3, int *a4, int a5) {\n signed int v5;\n signed int v6;\n int *v9;\n __m128i si128;\n long long v11;\n __m128i v12;\n long long v13;\n __m128i v14;\n __m128i v15;\n const __m128i *v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n __m128i v20;\n __m128i v21;\n __m128i v22;\n __m128i v23;\n __m128i v24;\n __m128i v25;\n unsigned int v26;\n __m128i v27;\n __m128i v28;\n __m128i v29;\n __m128i v30;\n __m128i v31;\n int v32;\n unsigned int v33;\n unsigned int v34;\n __m128i v35;\n unsigned int v36;\n int v37;\n __m128i v38;\n bool v39;\n signed int v40;\n long long v41;\n int v42;\n int v43;\n signed int v44;\n signed int v45;\n __m128i *result;\n __m128i v47;\n __m128i v48;\n __m128i v49;\n __m128i *v50;\n __m128i v51;\n __m128i v52;\n __m128i v53;\n unsigned int v54;\n long long v55;\n signed int *v56;\n int v57;\n int v58;\n v6 = a2 - 1;\n v9 = a4;\n if (a2 > 0) {\n v58 = a3;\n v6 = a2 - 1;\n si128 = _mm_load_si128((const __m128i *)&xmmword_20E0);\n v11 = 0LL;\n v12 = _mm_load_si128((const __m128i *)&xmmword_20F0);\n while (1) {\n v13 = *(uint64_t *)(a1 + 8 * v11);\n if ((unsigned int)v6 <= 5) {\n v40 = 0;\n } else {\n v14 = _mm_cvtsi32_si128(v5);\n v15 = 0LL;\n v16 = *(const __m128i **)(a1 + 8 * v11);\n v17 = _mm_shuffle_epi32(v14, 0);\n v18 = (__m128i)-1LL;\n v19 = _mm_load_si128((const __m128i *)&xmmword_20D0);\n v20 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v11), 0);\n v21 = _mm_load_si128((const __m128i *)&xmmword_20C0);\n do {\n v22 = _mm_loadu_si128(v16);\n v23 = v19;\n ++v16;\n v19 = _mm_add_epi32(v19, si128);\n v24 = _mm_cmpeq_epi32(v22, v12);\n v17 =\n _mm_or_si128(_mm_andnot_si128(v24, v17), _mm_and_si128(v20, v24));\n v18 =\n _mm_or_si128(_mm_andnot_si128(v24, v18), _mm_and_si128(v23, v24));\n v25 = v21;\n v21 = _mm_add_epi32(v21, si128);\n v15 =\n _mm_or_si128(_mm_andnot_si128(v24, v15), _mm_and_si128(v25, v24));\n } while (v16 !=\n (const __m128i *)(v13 + 16LL * ((unsigned int)a2 >> 2)));\n v26 = _mm_cvtsi128_si32(v15);\n v27 = _mm_srli_si128(v18, 8);\n v28 = _mm_cmpgt_epi32(v27, v18);\n v29 = _mm_or_si128(_mm_andnot_si128(v28, v18), _mm_and_si128(v27, v28));\n v30 = _mm_srli_si128(v29, 4);\n v31 = _mm_cmpgt_epi32(v30, v29);\n v32 = _mm_cvtsi128_si32(\n _mm_or_si128(_mm_andnot_si128(v31, v29), _mm_and_si128(v30, v31)));\n v33 = _mm_cvtsi128_si32(_mm_shuffle_epi32(v15, 85));\n if (v32 != -1) a5 = v32;\n v34 = v33;\n v35 = _mm_unpackhi_epi32(v15, v15);\n if (v26 >= v33) v34 = v26;\n v36 = _mm_cvtsi128_si32(v35);\n v37 = _mm_cvtsi128_si32(_mm_shuffle_epi32(v17, 255));\n if (v34 >= v36) {\n v5 = _mm_cvtsi128_si32(v17);\n v57 = _mm_cvtsi128_si32(_mm_shuffle_epi32(v17, 85));\n if (v26 < v33) v5 = v57;\n } else {\n v5 = _mm_cvtsi128_si32(_mm_unpackhi_epi32(v17, v17));\n }\n v38 = _mm_shuffle_epi32(v15, 255);\n if (v34 < v36) v34 = v36;\n v39 = v34 < _mm_cvtsi128_si32(v38);\n v40 = a2 & 4294967292;\n if (v39) v5 = v37;\n if (a2 == (a2 & 4294967292)) goto LABEL_41;\n }\n v41 = 4LL * v40;\n v42 = v40 + 1;\n if (*(uint32_t *)(v13 + v41) == 1) {\n a5 = v40;\n v5 = v11;\n }\n if (a2 > v42) {\n if (*(uint32_t *)(v13 + v41 + 4) != 1) v42 = a5;\n a5 = v40 + 2;\n if (*(uint32_t *)(v13 + v41 + 4) == 1) v5 = v11;\n if (a2 <= a5) goto LABEL_67;\n if (*(uint32_t *)(v13 + v41 + 8) != 1) a5 = v42;\n v42 = v40 + 3;\n if (*(uint32_t *)(v13 + v41 + 8) == 1) v5 = v11;\n if (a2 <= v42) goto LABEL_41;\n v43 = v40 + 4;\n if (*(uint32_t *)(v13 + v41 + 12) == 1)\n v5 = v11;\n else\n v42 = a5;\n if (v43 >= a2) {\n LABEL_67:\n a5 = v42;\n } else {\n a5 = v40 + 5;\n if (*(uint32_t *)(v13 + v41 + 16) == 1)\n v5 = v11;\n else\n v43 = v42;\n if (a5 >= a2) {\n a5 = v43;\n } else if (*(uint32_t *)(v13 + v41 + 20) == 1) {\n v5 = v11;\n } else {\n a5 = v43;\n }\n }\n }\n LABEL_41:\n if (++v11 == a2) {\n a3 = v58;\n v9 = a4;\n break;\n }\n }\n }\n v44 = a2 * a2;\n if (v5 > 0 &&\n v44 > *(uint32_t *)(*(uint64_t *)(a1 + 8LL * v5 - 8) + 4LL * a5))\n v44 = *(uint32_t *)(*(uint64_t *)(a1 + 8LL * v5 - 8) + 4LL * a5);\n if (v6 > v5 &&\n v44 > *(uint32_t *)(*(uint64_t *)(a1 + 8LL * v5 + 8) + 4LL * a5))\n v44 = *(uint32_t *)(*(uint64_t *)(a1 + 8LL * v5 + 8) + 4LL * a5);\n if (a5 > 0 &&\n v44 > *(uint32_t *)(*(uint64_t *)(a1 + 8LL * v5) + 4LL * a5 - 4))\n v44 = *(uint32_t *)(*(uint64_t *)(a1 + 8LL * v5) + 4LL * a5 - 4);\n if (v6 > a5) {\n v45 = *(uint32_t *)(*(uint64_t *)(a1 + 8LL * v5) + 4LL * a5 + 4);\n if (v44 > v45) v44 = v45;\n }\n *v9 = a3;\n result = (__m128i *)malloc(4LL * a3);\n if (a3 > 0) {\n if ((unsigned int)(a3 - 1) <= 2) {\n result->m128i_i32[0] = 1;\n v56 = &result->m128i_i32[1];\n v55 = 4LL;\n v54 = 0;\n if (a3 == 1) return result;\n goto LABEL_61;\n }\n v47 = _mm_load_si128((const __m128i *)&xmmword_20D0);\n v48 = _mm_load_si128((const __m128i *)&xmmword_20E0);\n v49 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v44), 0);\n v50 = result;\n v51 = _mm_load_si128((const __m128i *)&xmmword_20F0);\n do {\n v52 = v47;\n v47 = _mm_add_epi32(v47, v48);\n ++v50;\n v53 = _mm_cmpeq_epi32(_mm_and_si128(v52, v51), (__m128i)0LL);\n v50[-1] =\n _mm_or_si128(_mm_andnot_si128(v53, v49), _mm_and_si128(v51, v53));\n } while (&result[(unsigned int)a3 >> 2] != v50);\n v54 = a3 & 2147483644;\n if ((a3 & 3) != 0) {\n result->m128i_i32[v54] = 1;\n v55 = 4LL * v54 + 4;\n v56 = (int *)((char *)result->m128i_i32 + v55);\n if (a3 > (int)(v54 + 1)) {\n LABEL_61:\n *v56 = v44;\n if ((int)(v54 + 2) < a3)\n *(int *)((char *)&result->m128i_i32[1] + v55) = 1;\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "__m128i *func0(long long a1, int a2, int a3, int *a4, int a5) {\n signed int v5;\n signed int v6;\n int *v9;\n __m128i si128;\n long long v11;\n __m128i v12;\n long long v13;\n __m128i v14;\n __m128i v15;\n const __m128i *v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n __m128i v20;\n __m128i v21;\n __m128i v22;\n __m128i v23;\n __m128i v24;\n __m128i v25;\n unsigned int v26;\n __m128i v27;\n __m128i v28;\n __m128i v29;\n __m128i v30;\n __m128i v31;\n int v32;\n unsigned int v33;\n unsigned int v34;\n __m128i v35;\n unsigned int v36;\n int v37;\n __m128i v38;\n bool v39;\n signed int v40;\n long long v41;\n int v42;\n int v43;\n signed int v44;\n signed int v45;\n __m128i *result;\n __m128i v47;\n __m128i v48;\n __m128i v49;\n __m128i *v50;\n __m128i v51;\n __m128i v52;\n __m128i v53;\n unsigned int v54;\n long long v55;\n signed int *v56;\n int v57;\n int v58;\n v6 = a2 - 1;\n v9 = a4;\n if (a2 > 0) {\n v58 = a3;\n v6 = a2 - 1;\n si128 = _mm_load_si128((const __m128i *)&xmmword_20E0);\n v11 = 0LL;\n v12 = _mm_load_si128((const __m128i *)&xmmword_20F0);\n while (1) {\n v13 = *(uint64_t *)(a1 + 8 * v11);\n if ((unsigned int)v6 <= 5) {\n v40 = 0;\n } else {\n v14 = _mm_cvtsi32_si128(v5);\n v15 = 0LL;\n v16 = *(const __m128i **)(a1 + 8 * v11);\n v17 = _mm_shuffle_epi32(v14, 0);\n v18 = (__m128i)-1LL;\n v19 = _mm_load_si128((const __m128i *)&xmmword_20D0);\n v20 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v11), 0);\n v21 = _mm_load_si128((const __m128i *)&xmmword_20C0);\n do {\n v22 = _mm_loadu_si128(v16);\n v23 = v19;\n ++v16;\n v19 = _mm_add_epi32(v19, si128);\n v24 = _mm_cmpeq_epi32(v22, v12);\n v17 =\n _mm_or_si128(_mm_andnot_si128(v24, v17), _mm_and_si128(v20, v24));\n v18 =\n _mm_or_si128(_mm_andnot_si128(v24, v18), _mm_and_si128(v23, v24));\n v25 = v21;\n v21 = _mm_add_epi32(v21, si128);\n v15 =\n _mm_or_si128(_mm_andnot_si128(v24, v15), _mm_and_si128(v25, v24));\n } while (v16 !=\n (const __m128i *)(v13 + 16LL * ((unsigned int)a2 >> 2)));\n v26 = _mm_cvtsi128_si32(v15);\n v27 = _mm_srli_si128(v18, 8);\n v28 = _mm_cmpgt_epi32(v27, v18);\n v29 = _mm_or_si128(_mm_andnot_si128(v28, v18), _mm_and_si128(v27, v28));\n v30 = _mm_srli_si128(v29, 4);\n v31 = _mm_cmpgt_epi32(v30, v29);\n v32 = _mm_cvtsi128_si32(\n _mm_or_si128(_mm_andnot_si128(v31, v29), _mm_and_si128(v30, v31)));\n v33 = _mm_cvtsi128_si32(_mm_shuffle_epi32(v15, 85));\n if (v32 != -1) a5 = v32;\n v34 = v33;\n v35 = _mm_unpackhi_epi32(v15, v15);\n if (v26 >= v33) v34 = v26;\n v36 = _mm_cvtsi128_si32(v35);\n v37 = _mm_cvtsi128_si32(_mm_shuffle_epi32(v17, 255));\n if (v34 >= v36) {\n v5 = _mm_cvtsi128_si32(v17);\n v57 = _mm_cvtsi128_si32(_mm_shuffle_epi32(v17, 85));\n if (v26 < v33) v5 = v57;\n } else {\n v5 = _mm_cvtsi128_si32(_mm_unpackhi_epi32(v17, v17));\n }\n v38 = _mm_shuffle_epi32(v15, 255);\n if (v34 < v36) v34 = v36;\n v39 = v34 < _mm_cvtsi128_si32(v38);\n v40 = a2 & 4294967292;\n if (v39) v5 = v37;\n if (a2 == (a2 & 4294967292)) goto LABEL_41;\n }\n v41 = 4LL * v40;\n v42 = v40 + 1;\n if (*(uint32_t *)(v13 + v41) == 1) {\n a5 = v40;\n v5 = v11;\n }\n if (a2 > v42) {\n if (*(uint32_t *)(v13 + v41 + 4) != 1) v42 = a5;\n a5 = v40 + 2;\n if (*(uint32_t *)(v13 + v41 + 4) == 1) v5 = v11;\n if (a2 <= a5) goto LABEL_67;\n if (*(uint32_t *)(v13 + v41 + 8) != 1) a5 = v42;\n v42 = v40 + 3;\n if (*(uint32_t *)(v13 + v41 + 8) == 1) v5 = v11;\n if (a2 <= v42) goto LABEL_41;\n v43 = v40 + 4;\n if (*(uint32_t *)(v13 + v41 + 12) == 1)\n v5 = v11;\n else\n v42 = a5;\n if (v43 >= a2) {\n LABEL_67:\n a5 = v42;\n } else {\n a5 = v40 + 5;\n if (*(uint32_t *)(v13 + v41 + 16) == 1)\n v5 = v11;\n else\n v43 = v42;\n if (a5 >= a2) {\n a5 = v43;\n } else if (*(uint32_t *)(v13 + v41 + 20) == 1) {\n v5 = v11;\n } else {\n a5 = v43;\n }\n }\n }\n LABEL_41:\n if (++v11 == a2) {\n a3 = v58;\n v9 = a4;\n break;\n }\n }\n }\n v44 = a2 * a2;\n if (v5 > 0 &&\n v44 > *(uint32_t *)(*(uint64_t *)(a1 + 8LL * v5 - 8) + 4LL * a5))\n v44 = *(uint32_t *)(*(uint64_t *)(a1 + 8LL * v5 - 8) + 4LL * a5);\n if (v6 > v5 &&\n v44 > *(uint32_t *)(*(uint64_t *)(a1 + 8LL * v5 + 8) + 4LL * a5))\n v44 = *(uint32_t *)(*(uint64_t *)(a1 + 8LL * v5 + 8) + 4LL * a5);\n if (a5 > 0 &&\n v44 > *(uint32_t *)(*(uint64_t *)(a1 + 8LL * v5) + 4LL * a5 - 4))\n v44 = *(uint32_t *)(*(uint64_t *)(a1 + 8LL * v5) + 4LL * a5 - 4);\n if (v6 > a5) {\n v45 = *(uint32_t *)(*(uint64_t *)(a1 + 8LL * v5) + 4LL * a5 + 4);\n if (v44 > v45) v44 = v45;\n }\n *v9 = a3;\n result = (__m128i *)malloc(4LL * a3);\n if (a3 > 0) {\n if ((unsigned int)(a3 - 1) <= 2) {\n result->m128i_i32[0] = 1;\n v56 = &result->m128i_i32[1];\n v55 = 4LL;\n v54 = 0;\n if (a3 == 1) return result;\n goto LABEL_61;\n }\n v47 = _mm_load_si128((const __m128i *)&xmmword_20D0);\n v48 = _mm_load_si128((const __m128i *)&xmmword_20E0);\n v49 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v44), 0);\n v50 = result;\n v51 = _mm_load_si128((const __m128i *)&xmmword_20F0);\n do {\n v52 = v47;\n v47 = _mm_add_epi32(v47, v48);\n ++v50;\n v53 = _mm_cmpeq_epi32(_mm_and_si128(v52, v51), (__m128i)0LL);\n v50[-1] =\n _mm_or_si128(_mm_andnot_si128(v53, v49), _mm_and_si128(v51, v53));\n } while (&result[(unsigned int)a3 >> 2] != v50);\n v54 = a3 & 2147483644;\n if ((a3 & 3) != 0) {\n result->m128i_i32[v54] = 1;\n v55 = 4LL * v54 + 4;\n v56 = (int *)((char *)result->m128i_i32 + v55);\n if (a3 > (int)(v54 + 1)) {\n LABEL_61:\n *v56 = v44;\n if ((int)(v54 + 2) < a3)\n *(int *)((char *)&result->m128i_i32[1] + v55) = 1;\n }\n }\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-130", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int* func0(int n) {\n int* out = (int*)malloc((n + 1) * sizeof(int));\n out[0] = 1;\n if (n == 0) return out;\n out[1] = 3;\n for (int i = 2; i <= n; i++) {\n if (i % 2 == 0)\n out[i] = 1 + i / 2;\n else\n out[i] = out[i - 1] + out[i - 2] + 1 + (i + 1) / 2;\n }\n return out;\n}", + "test": "#include \n#include \n#include \n\n\nint issame(int* a, int* b, int size) {\n for (int i = 0; i < size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int size;\n\n int tri_3[] = {1, 3, 2, 8};\n size = 4;\n int* out3 = func0(3);\n assert(issame(out3, tri_3, size));\n free(out3);\n\n int tri_4[] = {1, 3, 2, 8, 3};\n size = 5;\n int* out4 = func0(4);\n assert(issame(out4, tri_4, size));\n free(out4);\n\n int tri_5[] = {1, 3, 2, 8, 3, 15};\n size = 6;\n int* out5 = func0(5);\n assert(issame(out5, tri_5, size));\n free(out5);\n\n int tri_6[] = {1, 3, 2, 8, 3, 15, 4};\n size = 7;\n int* out6 = func0(6);\n assert(issame(out6, tri_6, size));\n free(out6);\n\n int tri_7[] = {1, 3, 2, 8, 3, 15, 4, 24};\n size = 8;\n int* out7 = func0(7);\n assert(issame(out7, tri_7, size));\n free(out7);\n\n int tri_8[] = {1, 3, 2, 8, 3, 15, 4, 24, 5};\n size = 9;\n int* out8 = func0(8);\n assert(issame(out8, tri_8, size));\n free(out8);\n\n int tri_9[] = {1, 3, 2, 8, 3, 15, 4, 24, 5, 35};\n size = 10;\n int* out9 = func0(9);\n assert(issame(out9, tri_9, size));\n free(out9);\n\n int tri_20[] = {1, 3, 2, 8, 3, 15, 4, 24, 5, 35, 6, 48, 7, 63, 8, 80, 9, 99, 10, 120, 11};\n size = 21;\n int* out20 = func0(20);\n assert(issame(out20, tri_20, size));\n free(out20);\n\n int tri_0[] = {1};\n size = 1;\n int* out0 = func0(0);\n assert(issame(out0, tri_0, size));\n free(out0);\n\n int tri_1[] = {1, 3};\n size = 2;\n int* out1 = func0(1);\n assert(issame(out1, tri_1, size));\n free(out1);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov eax, [rbp+var_14]\nadd eax, 1\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov rax, [rbp+var_8]\nmov dword ptr [rax], 1\ncmp [rbp+var_14], 0\njnz short loc_11E9\nmov rax, [rbp+var_8]\njmp locret_12A4\nloc_11E9:\nmov rax, [rbp+var_8]\nadd rax, 4\nmov dword ptr [rax], 3\nmov [rbp+var_C], 2\njmp loc_1294\nloc_1203:\nmov eax, [rbp+var_C]\nand eax, 1\ntest eax, eax\njnz short loc_1236\nmov eax, [rbp+var_C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov ecx, eax\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nlea edx, [rcx+1]\nmov [rax], edx\njmp short loc_1290\nloc_1236:\nmov eax, [rbp+var_C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nshl rax, 2\nlea rcx, [rax-8]\nmov rax, [rbp+var_8]\nadd rax, rcx\nmov eax, [rax]\nadd eax, edx\nlea edx, [rax+1]\nmov eax, [rbp+var_C]\nadd eax, 1\nmov ecx, eax\nshr ecx, 1Fh\nadd eax, ecx\nsar eax, 1\nmov esi, eax\nmov eax, [rbp+var_C]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rcx\nadd edx, esi\nmov [rax], edx\nloc_1290:\nadd [rbp+var_C], 1\nloc_1294:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_14]\njle loc_1203\nmov rax, [rbp+var_8]\nlocret_12A4:\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int a1)\n{\n int i; // [rsp+14h] [rbp-Ch]\n _DWORD *v3; // [rsp+18h] [rbp-8h]\n\n v3 = malloc(4LL * (a1 + 1));\n *v3 = 1;\n if ( !a1 )\n return v3;\n v3[1] = 3;\n for ( i = 2; i <= a1; ++i )\n {\n if ( (i & 1) != 0 )\n v3[i] = (i + 1) / 2 + v3[i - 1] + v3[i - 2] + 1;\n else\n v3[i] = i / 2 + 1;\n }\n return v3;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov eax, [rbp+var_14]\nadd eax, 1\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov rax, [rbp+var_8]\nmov dword ptr [rax], 1\ncmp [rbp+var_14], 0\njnz short loc_11E9\nmov rax, [rbp+var_8]\njmp locret_12A4\nloc_11E9:\nmov rax, [rbp+var_8]\nadd rax, 4\nmov dword ptr [rax], 3\nmov [rbp+var_C], 2\njmp loc_1294\nloc_1203:\nmov eax, [rbp+var_C]\nand eax, 1\ntest eax, eax\njnz short loc_1236\nmov eax, [rbp+var_C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov ecx, eax\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nlea edx, [rcx+1]\nmov [rax], edx\njmp short loc_1290\nloc_1236:\nmov eax, [rbp+var_C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nshl rax, 2\nlea rcx, [rax-8]\nmov rax, [rbp+var_8]\nadd rax, rcx\nmov eax, [rax]\nadd eax, edx\nlea edx, [rax+1]\nmov eax, [rbp+var_C]\nadd eax, 1\nmov ecx, eax\nshr ecx, 1Fh\nadd eax, ecx\nsar eax, 1\nmov esi, eax\nmov eax, [rbp+var_C]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rcx\nadd edx, esi\nmov [rax], edx\nloc_1290:\nadd [rbp+var_C], 1\nloc_1294:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_14]\njle loc_1203\nmov rax, [rbp+var_8]\nlocret_12A4:\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(int a1)\n{\n int i; // [rsp+14h] [rbp-Ch]\n _DWORD *v3; // [rsp+18h] [rbp-8h]\n\n v3 = malloc(4LL * (a1 + 1));\n *v3 = 1;\n if ( !a1 )\n return v3;\n v3[1] = 3;\n for ( i = 2; i <= a1; ++i )\n {\n if ( (i & 1) != 0 )\n v3[i] = (i + 1) / 2 + v3[i - 1] + v3[i - 2] + 1;\n else\n v3[i] = i / 2 + 1;\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(int a1) {\n int i;\n uint32_t *v3;\n v3 = malloc(4LL * (a1 + 1));\n *v3 = 1;\n if (!a1) return v3;\n v3[1] = 3;\n for (i = 2; i <= a1; ++i) {\n if ((i & 1) != 0)\n v3[i] = (i + 1) / 2 + v3[i - 1] + v3[i - 2] + 1;\n else\n v3[i] = i / 2 + 1;\n }\n return v3;\n}", + "ida_pseudo_norm": "uint32_t *func0(int a1) {\n int i;\n uint32_t *v3;\n v3 = malloc(4LL * (a1 + 1));\n *v3 = 1;\n if (!a1) return v3;\n v3[1] = 3;\n for (i = 2; i <= a1; ++i) {\n if ((i & 1) != 0)\n v3[i] = (i + 1) / 2 + v3[i - 1] + v3[i - 2] + 1;\n else\n v3[i] = i / 2 + 1;\n }\n return v3;\n}" + }, + { + "index": "HumanEval-C-130", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int* func0(int n) {\n int* out = (int*)malloc((n + 1) * sizeof(int));\n out[0] = 1;\n if (n == 0) return out;\n out[1] = 3;\n for (int i = 2; i <= n; i++) {\n if (i % 2 == 0)\n out[i] = 1 + i / 2;\n else\n out[i] = out[i - 1] + out[i - 2] + 1 + (i + 1) / 2;\n }\n return out;\n}", + "test": "#include \n#include \n#include \n\n\nint issame(int* a, int* b, int size) {\n for (int i = 0; i < size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int size;\n\n int tri_3[] = {1, 3, 2, 8};\n size = 4;\n int* out3 = func0(3);\n assert(issame(out3, tri_3, size));\n free(out3);\n\n int tri_4[] = {1, 3, 2, 8, 3};\n size = 5;\n int* out4 = func0(4);\n assert(issame(out4, tri_4, size));\n free(out4);\n\n int tri_5[] = {1, 3, 2, 8, 3, 15};\n size = 6;\n int* out5 = func0(5);\n assert(issame(out5, tri_5, size));\n free(out5);\n\n int tri_6[] = {1, 3, 2, 8, 3, 15, 4};\n size = 7;\n int* out6 = func0(6);\n assert(issame(out6, tri_6, size));\n free(out6);\n\n int tri_7[] = {1, 3, 2, 8, 3, 15, 4, 24};\n size = 8;\n int* out7 = func0(7);\n assert(issame(out7, tri_7, size));\n free(out7);\n\n int tri_8[] = {1, 3, 2, 8, 3, 15, 4, 24, 5};\n size = 9;\n int* out8 = func0(8);\n assert(issame(out8, tri_8, size));\n free(out8);\n\n int tri_9[] = {1, 3, 2, 8, 3, 15, 4, 24, 5, 35};\n size = 10;\n int* out9 = func0(9);\n assert(issame(out9, tri_9, size));\n free(out9);\n\n int tri_20[] = {1, 3, 2, 8, 3, 15, 4, 24, 5, 35, 6, 48, 7, 63, 8, 80, 9, 99, 10, 120, 11};\n size = 21;\n int* out20 = func0(20);\n assert(issame(out20, tri_20, size));\n free(out20);\n\n int tri_0[] = {1};\n size = 1;\n int* out0 = func0(0);\n assert(issame(out0, tri_0, size));\n free(out0);\n\n int tri_1[] = {1, 3};\n size = 2;\n int* out1 = func0(1);\n assert(issame(out1, tri_1, size));\n free(out1);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbx\nmov ebx, edi\nlea edi, [rdi+1]\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov dword ptr [rax], 1\ntest ebx, ebx\njz short loc_121A\nmov dword ptr [rax+4], 3\ncmp ebx, 1\njle short loc_121A\nlea r8d, [rbx+1]\nmov edx, 2\njmp short loc_1204\nloc_11E0:\nmov esi, [rax+rdx*4-8]\nadd esi, [rax+rdx*4-4]\nlea edi, [rdx+1]\nmov ecx, edi\nshr ecx, 1Fh\nadd ecx, edi\nsar ecx, 1\nlea ecx, [rsi+rcx+1]\nmov [rax+rdx*4], ecx\nloc_11FB:\nadd rdx, 1\ncmp rdx, r8\njz short loc_121A\nloc_1204:\ntest dl, 1\njnz short loc_11E0\nmov ecx, edx\nshr ecx, 1Fh\nadd ecx, edx\nsar ecx, 1\nadd ecx, 1\nmov [rax+rdx*4], ecx\njmp short loc_11FB\nloc_121A:\npop rbx\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int a1)\n{\n _DWORD *result; // rax\n __int64 v2; // rdx\n int v3; // ecx\n\n result = malloc(4LL * (a1 + 1));\n *result = 1;\n if ( a1 )\n {\n result[1] = 3;\n if ( a1 > 1 )\n {\n v2 = 2LL;\n do\n {\n if ( (v2 & 1) != 0 )\n v3 = result[v2 - 1] + result[v2 - 2] + ((int)v2 + 1) / 2 + 1;\n else\n v3 = (int)v2 / 2 + 1;\n result[v2++] = v3;\n }\n while ( v2 != a1 + 1 );\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbx\nmov ebx, edi\nlea edi, [rdi+1]\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov dword ptr [rax], 1\ntest ebx, ebx\njz short loc_121A\nmov dword ptr [rax+4], 3\ncmp ebx, 1\njle short loc_121A\nlea r8d, [rbx+1]\nmov edx, 2\njmp short loc_1204\nloc_11E0:\nmov esi, [rax+rdx*4-8]\nadd esi, [rax+rdx*4-4]\nlea edi, [rdx+1]\nmov ecx, edi\nshr ecx, 1Fh\nadd ecx, edi\nsar ecx, 1\nlea ecx, [rsi+rcx+1]\nmov [rax+rdx*4], ecx\nloc_11FB:\nadd rdx, 1\ncmp rdx, r8\njz short loc_121A\nloc_1204:\ntest dl, 1\njnz short loc_11E0\nmov ecx, edx\nshr ecx, 1Fh\nadd ecx, edx\nsar ecx, 1\nadd ecx, 1\nmov [rax+rdx*4], ecx\njmp short loc_11FB\nloc_121A:\npop rbx\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(int a1)\n{\n _DWORD *result; // rax\n __int64 v2; // rdx\n int v3; // ecx\n\n result = malloc(4LL * (a1 + 1));\n *result = 1;\n if ( a1 )\n {\n result[1] = 3;\n if ( a1 > 1 )\n {\n v2 = 2LL;\n do\n {\n if ( (v2 & 1) != 0 )\n v3 = result[v2 - 1] + result[v2 - 2] + ((int)v2 + 1) / 2 + 1;\n else\n v3 = (int)v2 / 2 + 1;\n result[v2++] = v3;\n }\n while ( v2 != a1 + 1 );\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(int a1) {\n uint32_t *result;\n long long v2;\n int v3;\n result = malloc(4LL * (a1 + 1));\n *result = 1;\n if (a1) {\n result[1] = 3;\n if (a1 > 1) {\n v2 = 2LL;\n do {\n if ((v2 & 1) != 0)\n v3 = result[v2 - 1] + result[v2 - 2] + ((int)v2 + 1) / 2 + 1;\n else\n v3 = (int)v2 / 2 + 1;\n result[v2++] = v3;\n } while (v2 != a1 + 1);\n }\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(int a1) {\n uint32_t *result;\n long long v2;\n int v3;\n result = malloc(4LL * (a1 + 1));\n *result = 1;\n if (a1) {\n result[1] = 3;\n if (a1 > 1) {\n v2 = 2LL;\n do {\n if ((v2 & 1) != 0)\n v3 = result[v2 - 1] + result[v2 - 2] + ((int)v2 + 1) / 2 + 1;\n else\n v3 = (int)v2 / 2 + 1;\n result[v2++] = v3;\n } while (v2 != a1 + 1);\n }\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-130", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int* func0(int n) {\n int* out = (int*)malloc((n + 1) * sizeof(int));\n out[0] = 1;\n if (n == 0) return out;\n out[1] = 3;\n for (int i = 2; i <= n; i++) {\n if (i % 2 == 0)\n out[i] = 1 + i / 2;\n else\n out[i] = out[i - 1] + out[i - 2] + 1 + (i + 1) / 2;\n }\n return out;\n}", + "test": "#include \n#include \n#include \n\n\nint issame(int* a, int* b, int size) {\n for (int i = 0; i < size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int size;\n\n int tri_3[] = {1, 3, 2, 8};\n size = 4;\n int* out3 = func0(3);\n assert(issame(out3, tri_3, size));\n free(out3);\n\n int tri_4[] = {1, 3, 2, 8, 3};\n size = 5;\n int* out4 = func0(4);\n assert(issame(out4, tri_4, size));\n free(out4);\n\n int tri_5[] = {1, 3, 2, 8, 3, 15};\n size = 6;\n int* out5 = func0(5);\n assert(issame(out5, tri_5, size));\n free(out5);\n\n int tri_6[] = {1, 3, 2, 8, 3, 15, 4};\n size = 7;\n int* out6 = func0(6);\n assert(issame(out6, tri_6, size));\n free(out6);\n\n int tri_7[] = {1, 3, 2, 8, 3, 15, 4, 24};\n size = 8;\n int* out7 = func0(7);\n assert(issame(out7, tri_7, size));\n free(out7);\n\n int tri_8[] = {1, 3, 2, 8, 3, 15, 4, 24, 5};\n size = 9;\n int* out8 = func0(8);\n assert(issame(out8, tri_8, size));\n free(out8);\n\n int tri_9[] = {1, 3, 2, 8, 3, 15, 4, 24, 5, 35};\n size = 10;\n int* out9 = func0(9);\n assert(issame(out9, tri_9, size));\n free(out9);\n\n int tri_20[] = {1, 3, 2, 8, 3, 15, 4, 24, 5, 35, 6, 48, 7, 63, 8, 80, 9, 99, 10, 120, 11};\n size = 21;\n int* out20 = func0(20);\n assert(issame(out20, tri_20, size));\n free(out20);\n\n int tri_0[] = {1};\n size = 1;\n int* out0 = func0(0);\n assert(issame(out0, tri_0, size));\n free(out0);\n\n int tri_1[] = {1, 3};\n size = 2;\n int* out1 = func0(1);\n assert(issame(out1, tri_1, size));\n free(out1);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbx\nmov ebx, edi\nadd edi, 1\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov dword ptr [rax], 1\ntest ebx, ebx\njz short loc_169B\nmov dword ptr [rax+4], 3\ncmp ebx, 1\njle short loc_169B\nmov rcx, rax\nmov edx, 2\njmp short loc_1672\nloc_1660:\nmov edi, esi\nadd rcx, 4\nsar edi, 1\nadd edi, 1\nmov [rcx+4], edi\ncmp ebx, esi\njz short loc_169B\nloc_1672:\nmov edi, edx\nmov esi, edx\nadd edx, 1\nand edi, 1\ntest edi, edi\njz short loc_1660\nmov r8d, edx\nmov edi, [rcx]\nadd edi, [rcx+4]\nadd rcx, 4\nsar r8d, 1\nlea edi, [rdi+r8+1]\nmov [rcx+4], edi\ncmp ebx, esi\njnz short loc_1672\nloc_169B:\npop rbx\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int a1)\n{\n _DWORD *result; // rax\n _DWORD *v3; // rcx\n int v4; // edx\n char v5; // di\n int v6; // esi\n int v7; // edi\n\n result = malloc(4LL * (a1 + 1));\n *result = 1;\n if ( a1 )\n {\n result[1] = 3;\n if ( a1 > 1 )\n {\n v3 = result;\n v4 = 2;\n do\n {\n while ( 1 )\n {\n v5 = v4;\n v6 = v4++;\n if ( (v5 & 1) != 0 )\n break;\n ++v3;\n v3[1] = (v6 >> 1) + 1;\n if ( a1 == v6 )\n return result;\n }\n v7 = v3[1] + *v3;\n ++v3;\n v3[1] = v7 + (v4 >> 1) + 1;\n }\n while ( a1 != v6 );\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1620:\nendbr64\npush rbx\nmov ebx, edi\nadd edi, 1\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov dword ptr [rax], 1\ntest ebx, ebx\njz short loc_169B\nmov dword ptr [rax+4], 3\ncmp ebx, 1\njle short loc_169B\nmov rcx, rax\nmov edx, 2\njmp short loc_1672\nloc_1660:\nmov edi, esi\nadd rcx, 4\nsar edi, 1\nadd edi, 1\nmov [rcx+4], edi\ncmp ebx, esi\njz short loc_169B\nloc_1672:\nmov edi, edx\nmov esi, edx\nadd edx, 1\nand edi, 1\ntest edi, edi\njz short loc_1660\nmov r8d, edx\nmov edi, [rcx]\nadd edi, [rcx+4]\nadd rcx, 4\nsar r8d, 1\nlea edi, [rdi+r8+1]\nmov [rcx+4], edi\ncmp ebx, esi\njnz short loc_1672\nloc_169B:\npop rbx\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1620(int a1)\n{\n _DWORD *result; // rax\n _DWORD *v3; // rcx\n int v4; // edx\n char v5; // di\n int v6; // esi\n int v7; // edi\n\n result = malloc(4LL * (a1 + 1));\n *result = 1;\n if ( a1 )\n {\n result[1] = 3;\n if ( a1 > 1 )\n {\n v3 = result;\n v4 = 2;\n do\n {\n while ( 1 )\n {\n v5 = v4;\n v6 = v4++;\n if ( (v5 & 1) != 0 )\n break;\n ++v3;\n v3[1] = (v6 >> 1) + 1;\n if ( a1 == v6 )\n return result;\n }\n v7 = v3[1] + *v3;\n ++v3;\n v3[1] = v7 + (v4 >> 1) + 1;\n }\n while ( a1 != v6 );\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1620(int a1) {\n uint32_t *result;\n uint32_t *v3;\n int v4;\n char v5;\n int v6;\n int v7;\n result = malloc(4LL * (a1 + 1));\n *result = 1;\n if (a1) {\n result[1] = 3;\n if (a1 > 1) {\n v3 = result;\n v4 = 2;\n do {\n while (1) {\n v5 = v4;\n v6 = v4++;\n if ((v5 & 1) != 0) break;\n ++v3;\n v3[1] = (v6 >> 1) + 1;\n if (a1 == v6) return result;\n }\n v7 = v3[1] + *v3;\n ++v3;\n v3[1] = v7 + (v4 >> 1) + 1;\n } while (a1 != v6);\n }\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(int a1) {\n uint32_t *result;\n uint32_t *v3;\n int v4;\n char v5;\n int v6;\n int v7;\n result = malloc(4LL * (a1 + 1));\n *result = 1;\n if (a1) {\n result[1] = 3;\n if (a1 > 1) {\n v3 = result;\n v4 = 2;\n do {\n while (1) {\n v5 = v4;\n v6 = v4++;\n if ((v5 & 1) != 0) break;\n ++v3;\n v3[1] = (v6 >> 1) + 1;\n if (a1 == v6) return result;\n }\n v7 = v3[1] + *v3;\n ++v3;\n v3[1] = v7 + (v4 >> 1) + 1;\n } while (a1 != v6);\n }\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-130", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int* func0(int n) {\n int* out = (int*)malloc((n + 1) * sizeof(int));\n out[0] = 1;\n if (n == 0) return out;\n out[1] = 3;\n for (int i = 2; i <= n; i++) {\n if (i % 2 == 0)\n out[i] = 1 + i / 2;\n else\n out[i] = out[i - 1] + out[i - 2] + 1 + (i + 1) / 2;\n }\n return out;\n}", + "test": "#include \n#include \n#include \n\n\nint issame(int* a, int* b, int size) {\n for (int i = 0; i < size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int size;\n\n int tri_3[] = {1, 3, 2, 8};\n size = 4;\n int* out3 = func0(3);\n assert(issame(out3, tri_3, size));\n free(out3);\n\n int tri_4[] = {1, 3, 2, 8, 3};\n size = 5;\n int* out4 = func0(4);\n assert(issame(out4, tri_4, size));\n free(out4);\n\n int tri_5[] = {1, 3, 2, 8, 3, 15};\n size = 6;\n int* out5 = func0(5);\n assert(issame(out5, tri_5, size));\n free(out5);\n\n int tri_6[] = {1, 3, 2, 8, 3, 15, 4};\n size = 7;\n int* out6 = func0(6);\n assert(issame(out6, tri_6, size));\n free(out6);\n\n int tri_7[] = {1, 3, 2, 8, 3, 15, 4, 24};\n size = 8;\n int* out7 = func0(7);\n assert(issame(out7, tri_7, size));\n free(out7);\n\n int tri_8[] = {1, 3, 2, 8, 3, 15, 4, 24, 5};\n size = 9;\n int* out8 = func0(8);\n assert(issame(out8, tri_8, size));\n free(out8);\n\n int tri_9[] = {1, 3, 2, 8, 3, 15, 4, 24, 5, 35};\n size = 10;\n int* out9 = func0(9);\n assert(issame(out9, tri_9, size));\n free(out9);\n\n int tri_20[] = {1, 3, 2, 8, 3, 15, 4, 24, 5, 35, 6, 48, 7, 63, 8, 80, 9, 99, 10, 120, 11};\n size = 21;\n int* out20 = func0(20);\n assert(issame(out20, tri_20, size));\n free(out20);\n\n int tri_0[] = {1};\n size = 1;\n int* out0 = func0(0);\n assert(issame(out0, tri_0, size));\n free(out0);\n\n int tri_1[] = {1, 3};\n size = 2;\n int* out1 = func0(1);\n assert(issame(out1, tri_1, size));\n free(out1);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbx\nmov ebx, edi\nadd edi, 1\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov dword ptr [rax], 1\ntest ebx, ebx\njz short loc_168B\nmov dword ptr [rax+4], 3\ncmp ebx, 1\njle short loc_168B\nmov rcx, rax\nmov edx, 2\njmp short loc_1662\nloc_1650:\nmov edi, esi\nadd rcx, 4\nsar edi, 1\nadd edi, 1\nmov [rcx+4], edi\ncmp ebx, esi\njz short loc_168B\nloc_1662:\nmov edi, edx\nmov esi, edx\nadd edx, 1\nand edi, 1\ntest edi, edi\njz short loc_1650\nmov r8d, edx\nmov edi, [rcx]\nadd edi, [rcx+4]\nadd rcx, 4\nsar r8d, 1\nlea edi, [rdi+r8+1]\nmov [rcx+4], edi\ncmp ebx, esi\njnz short loc_1662\nloc_168B:\npop rbx\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int a1)\n{\n _DWORD *result; // rax\n _DWORD *v3; // rcx\n int v4; // edx\n char v5; // di\n int v6; // esi\n int v7; // edi\n\n result = malloc(4LL * (a1 + 1));\n *result = 1;\n if ( a1 )\n {\n result[1] = 3;\n if ( a1 > 1 )\n {\n v3 = result;\n v4 = 2;\n do\n {\n while ( 1 )\n {\n v5 = v4;\n v6 = v4++;\n if ( (v5 & 1) != 0 )\n break;\n ++v3;\n v3[1] = (v6 >> 1) + 1;\n if ( a1 == v6 )\n return result;\n }\n v7 = v3[1] + *v3;\n ++v3;\n v3[1] = v7 + (v4 >> 1) + 1;\n }\n while ( a1 != v6 );\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1610:\nendbr64\npush rbx\nmov ebx, edi\nadd edi, 1\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov dword ptr [rax], 1\ntest ebx, ebx\njz short loc_168B\nmov dword ptr [rax+4], 3\ncmp ebx, 1\njle short loc_168B\nmov rcx, rax\nmov edx, 2\njmp short loc_1662\nloc_1650:\nmov edi, esi\nadd rcx, 4\nsar edi, 1\nadd edi, 1\nmov [rcx+4], edi\ncmp ebx, esi\njz short loc_168B\nloc_1662:\nmov edi, edx\nmov esi, edx\nadd edx, 1\nand edi, 1\ntest edi, edi\njz short loc_1650\nmov r8d, edx\nmov edi, [rcx]\nadd edi, [rcx+4]\nadd rcx, 4\nsar r8d, 1\nlea edi, [rdi+r8+1]\nmov [rcx+4], edi\ncmp ebx, esi\njnz short loc_1662\nloc_168B:\npop rbx\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1610(int a1)\n{\n _DWORD *result; // rax\n _DWORD *v3; // rcx\n int v4; // edx\n char v5; // di\n int v6; // esi\n int v7; // edi\n\n result = malloc(4LL * (a1 + 1));\n *result = 1;\n if ( a1 )\n {\n result[1] = 3;\n if ( a1 > 1 )\n {\n v3 = result;\n v4 = 2;\n do\n {\n while ( 1 )\n {\n v5 = v4;\n v6 = v4++;\n if ( (v5 & 1) != 0 )\n break;\n ++v3;\n v3[1] = (v6 >> 1) + 1;\n if ( a1 == v6 )\n return result;\n }\n v7 = v3[1] + *v3;\n ++v3;\n v3[1] = v7 + (v4 >> 1) + 1;\n }\n while ( a1 != v6 );\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1610(int a1) {\n uint32_t *result;\n uint32_t *v3;\n int v4;\n char v5;\n int v6;\n int v7;\n result = malloc(4LL * (a1 + 1));\n *result = 1;\n if (a1) {\n result[1] = 3;\n if (a1 > 1) {\n v3 = result;\n v4 = 2;\n do {\n while (1) {\n v5 = v4;\n v6 = v4++;\n if ((v5 & 1) != 0) break;\n ++v3;\n v3[1] = (v6 >> 1) + 1;\n if (a1 == v6) return result;\n }\n v7 = v3[1] + *v3;\n ++v3;\n v3[1] = v7 + (v4 >> 1) + 1;\n } while (a1 != v6);\n }\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(int a1) {\n uint32_t *result;\n uint32_t *v3;\n int v4;\n char v5;\n int v6;\n int v7;\n result = malloc(4LL * (a1 + 1));\n *result = 1;\n if (a1) {\n result[1] = 3;\n if (a1 > 1) {\n v3 = result;\n v4 = 2;\n do {\n while (1) {\n v5 = v4;\n v6 = v4++;\n if ((v5 & 1) != 0) break;\n ++v3;\n v3[1] = (v6 >> 1) + 1;\n if (a1 == v6) return result;\n }\n v7 = v3[1] + *v3;\n ++v3;\n v3[1] = v7 + (v4 >> 1) + 1;\n } while (a1 != v6);\n }\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-131", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int n) {\n int prod = 1, has_odd = 0, digit;\n while (n > 0) {\n digit = n % 10;\n if (digit % 2 == 1) {\n has_odd = 1;\n prod *= digit;\n }\n n /= 10;\n }\n return has_odd ? prod : 0;\n}", + "test": "#include \n\nint main(){\n assert(func0(5) == 5);\n assert(func0(54) == 5);\n assert(func0(120) == 1);\n assert(func0(5014) == 5);\n assert(func0(98765) == 315);\n assert(func0(5576543) == 2625);\n assert(func0(2468) == 0);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_C], 1\nmov [rbp+var_8], 0\njmp short loc_11D7\nloc_1164:\nmov edx, [rbp+var_14]\nmovsxd rax, edx\nimul rax, 66666667h\nshr rax, 20h\nmov ecx, eax\nsar ecx, 2\nmov eax, edx\nsar eax, 1Fh\nsub ecx, eax\nmov eax, ecx\nshl eax, 2\nadd eax, ecx\nadd eax, eax\nsub edx, eax\nmov [rbp+var_4], edx\nmov edx, [rbp+var_4]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\ncmp eax, 1\njnz short loc_11B9\nmov [rbp+var_8], 1\nmov eax, [rbp+var_C]\nimul eax, [rbp+var_4]\nmov [rbp+var_C], eax\nloc_11B9:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_14], eax\nloc_11D7:\ncmp [rbp+var_14], 0\njg short loc_1164\ncmp [rbp+var_8], 0\njz short loc_11E8\nmov eax, [rbp+var_C]\njmp short loc_11ED\nloc_11E8:\nmov eax, 0\nloc_11ED:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v3; // [rsp+8h] [rbp-Ch]\n int v4; // [rsp+Ch] [rbp-8h]\n\n v3 = 1;\n v4 = 0;\n while ( a1 > 0 )\n {\n if ( a1 % 10 % 2 == 1 )\n {\n v4 = 1;\n v3 *= a1 % 10;\n }\n a1 /= 10;\n }\n if ( v4 )\n return v3;\n else\n return 0LL;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_C], 1\nmov [rbp+var_8], 0\njmp short loc_11D7\nloc_1164:\nmov edx, [rbp+var_14]\nmovsxd rax, edx\nimul rax, 66666667h\nshr rax, 20h\nmov ecx, eax\nsar ecx, 2\nmov eax, edx\nsar eax, 1Fh\nsub ecx, eax\nmov eax, ecx\nshl eax, 2\nadd eax, ecx\nadd eax, eax\nsub edx, eax\nmov [rbp+var_4], edx\nmov edx, [rbp+var_4]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\ncmp eax, 1\njnz short loc_11B9\nmov [rbp+var_8], 1\nmov eax, [rbp+var_C]\nimul eax, [rbp+var_4]\nmov [rbp+var_C], eax\nloc_11B9:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_14], eax\nloc_11D7:\ncmp [rbp+var_14], 0\njg short loc_1164\ncmp [rbp+var_8], 0\njz short loc_11E8\nmov eax, [rbp+var_C]\njmp short loc_11ED\nloc_11E8:\nmov eax, 0\nloc_11ED:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n unsigned int v3; // [rsp+8h] [rbp-Ch]\n int v4; // [rsp+Ch] [rbp-8h]\n\n v3 = 1;\n v4 = 0;\n while ( a1 > 0 )\n {\n if ( a1 % 10 % 2 == 1 )\n {\n v4 = 1;\n v3 *= a1 % 10;\n }\n a1 /= 10;\n }\n if ( v4 )\n return v3;\n else\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n unsigned int v3;\n int v4;\n v3 = 1;\n v4 = 0;\n while (a1 > 0) {\n if (a1 % 10 % 2 == 1) {\n v4 = 1;\n v3 *= a1 % 10;\n }\n a1 /= 10;\n }\n if (v4)\n return v3;\n else\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v3;\n int v4;\n v3 = 1;\n v4 = 0;\n while (a1 > 0) {\n if (a1 % 10 % 2 == 1) {\n v4 = 1;\n v3 *= a1 % 10;\n }\n a1 /= 10;\n }\n if (v4)\n return v3;\n else\n return 0LL;\n}" + }, + { + "index": "HumanEval-C-131", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int n) {\n int prod = 1, has_odd = 0, digit;\n while (n > 0) {\n digit = n % 10;\n if (digit % 2 == 1) {\n has_odd = 1;\n prod *= digit;\n }\n n /= 10;\n }\n return has_odd ? prod : 0;\n}", + "test": "#include \n\nint main(){\n assert(func0(5) == 5);\n assert(func0(54) == 5);\n assert(func0(120) == 1);\n assert(func0(5014) == 5);\n assert(func0(98765) == 315);\n assert(func0(5576543) == 2625);\n assert(func0(2468) == 0);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmov edx, edi\ntest edi, edi\njle short loc_11BE\nmov esi, 0\nmov edi, 1\njmp short loc_117B\nloc_115F:\nmovsxd rax, edx\nimul rax, 66666667h\nsar rax, 22h\nmov ecx, edx\nsar ecx, 1Fh\nsub eax, ecx\ncmp edx, 9\njle short loc_11B6\nmov edx, eax\nloc_117B:\nmovsxd rax, edx\nimul rax, 66666667h\nsar rax, 22h\nmov ecx, edx\nsar ecx, 1Fh\nsub eax, ecx\nlea ecx, [rax+rax*4]\nadd ecx, ecx\nmov eax, edx\nsub eax, ecx\nmov r8d, eax\nshr r8d, 1Fh\nlea ecx, [rax+r8]\nand ecx, 1\nsub ecx, r8d\ncmp ecx, 1\njnz short loc_115F\nimul edi, eax\nmov esi, ecx\njmp short loc_115F\nloc_11B6:\ntest esi, esi\ncmovnz esi, edi\nloc_11BB:\nmov eax, esi\nretn\nloc_11BE:\nmov esi, 0\njmp short loc_11BB", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // edx\n unsigned int v2; // esi\n unsigned int v3; // edi\n\n v1 = a1;\n if ( a1 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = 0;\n v3 = 1;\n while ( 1 )\n {\n if ( v1 % 10 % 2 == 1 )\n {\n v3 *= v1 % 10;\n v2 = 1;\n }\n if ( v1 <= 9 )\n break;\n v1 /= 10;\n }\n if ( v2 )\n return v3;\n }\n return v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmov edx, edi\ntest edi, edi\njle short loc_11BE\nmov esi, 0\nmov edi, 1\njmp short loc_117B\nloc_115F:\nmovsxd rax, edx\nimul rax, 66666667h\nsar rax, 22h\nmov ecx, edx\nsar ecx, 1Fh\nsub eax, ecx\ncmp edx, 9\njle short loc_11B6\nmov edx, eax\nloc_117B:\nmovsxd rax, edx\nimul rax, 66666667h\nsar rax, 22h\nmov ecx, edx\nsar ecx, 1Fh\nsub eax, ecx\nlea ecx, [rax+rax*4]\nadd ecx, ecx\nmov eax, edx\nsub eax, ecx\nmov r8d, eax\nshr r8d, 1Fh\nlea ecx, [rax+r8]\nand ecx, 1\nsub ecx, r8d\ncmp ecx, 1\njnz short loc_115F\nimul edi, eax\nmov esi, ecx\njmp short loc_115F\nloc_11B6:\ntest esi, esi\ncmovnz esi, edi\nloc_11BB:\nmov eax, esi\nretn\nloc_11BE:\nmov esi, 0\njmp short loc_11BB", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v1; // edx\n unsigned int v2; // esi\n unsigned int v3; // edi\n\n v1 = a1;\n if ( a1 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = 0;\n v3 = 1;\n while ( 1 )\n {\n if ( v1 % 10 % 2 == 1 )\n {\n v3 *= v1 % 10;\n v2 = 1;\n }\n if ( v1 <= 9 )\n break;\n v1 /= 10;\n }\n if ( v2 )\n return v3;\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v1;\n unsigned int v2;\n unsigned int v3;\n v1 = a1;\n if (a1 <= 0) {\n return 0;\n } else {\n v2 = 0;\n v3 = 1;\n while (1) {\n if (v1 % 10 % 2 == 1) {\n v3 *= v1 % 10;\n v2 = 1;\n }\n if (v1 <= 9) break;\n v1 /= 10;\n }\n if (v2) return v3;\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n unsigned int v2;\n unsigned int v3;\n v1 = a1;\n if (a1 <= 0) {\n return 0;\n } else {\n v2 = 0;\n v3 = 1;\n while (1) {\n if (v1 % 10 % 2 == 1) {\n v3 *= v1 % 10;\n v2 = 1;\n }\n if (v1 <= 9) break;\n v1 /= 10;\n }\n if (v2) return v3;\n }\n return v2;\n}" + }, + { + "index": "HumanEval-C-131", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int n) {\n int prod = 1, has_odd = 0, digit;\n while (n > 0) {\n digit = n % 10;\n if (digit % 2 == 1) {\n has_odd = 1;\n prod *= digit;\n }\n n /= 10;\n }\n return has_odd ? prod : 0;\n}", + "test": "#include \n\nint main(){\n assert(func0(5) == 5);\n assert(func0(54) == 5);\n assert(func0(120) == 1);\n assert(func0(5014) == 5);\n assert(func0(98765) == 315);\n assert(func0(5576543) == 2625);\n assert(func0(2468) == 0);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njle short loc_1320\nxor r9d, r9d\nmov r8d, 1\nmov esi, 0CCCCCCCDh\njmp short loc_12E2\nloc_12E0:\nmov edi, eax\nloc_12E2:\nmov eax, edi\nmov rdx, rax\nimul rdx, rsi\nshr rdx, 23h\nlea ecx, [rdx+rdx*4]\nmov edx, edi\nadd ecx, ecx\nsub edx, ecx\nmov ecx, edi\nand ecx, 1\njz short loc_1306\nimul r8d, edx\nmov r9d, ecx\nloc_1306:\nimul rax, rsi\nshr rax, 23h\ncmp edi, 9\njg short loc_12E0\nxor eax, eax\ntest r9d, r9d\ncmovz r8d, eax\nmov eax, r8d\nretn\nloc_1320:\nxor r8d, r8d\nmov eax, r8d\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // r9d\n unsigned int v2; // r8d\n\n if ( a1 <= 0 )\n return 0LL;\n v1 = 0;\n v2 = 1;\n while ( 1 )\n {\n if ( (a1 & 1) != 0 )\n {\n v2 *= a1 % 0xAu;\n v1 = a1 & 1;\n }\n if ( a1 <= 9 )\n break;\n a1 /= 0xAu;\n }\n if ( !v1 )\n return 0;\n return v2;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\ntest edi, edi\njle short loc_1320\nxor r9d, r9d\nmov r8d, 1\nmov esi, 0CCCCCCCDh\njmp short loc_12E2\nloc_12E0:\nmov edi, eax\nloc_12E2:\nmov eax, edi\nmov rdx, rax\nimul rdx, rsi\nshr rdx, 23h\nlea ecx, [rdx+rdx*4]\nmov edx, edi\nadd ecx, ecx\nsub edx, ecx\nmov ecx, edi\nand ecx, 1\njz short loc_1306\nimul r8d, edx\nmov r9d, ecx\nloc_1306:\nimul rax, rsi\nshr rax, 23h\ncmp edi, 9\njg short loc_12E0\nxor eax, eax\ntest r9d, r9d\ncmovz r8d, eax\nmov eax, r8d\nretn\nloc_1320:\nxor r8d, r8d\nmov eax, r8d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12C0(int a1)\n{\n int v1; // r9d\n unsigned int v2; // r8d\n\n if ( a1 <= 0 )\n return 0LL;\n v1 = 0;\n v2 = 1;\n while ( 1 )\n {\n if ( (a1 & 1) != 0 )\n {\n v2 *= a1 % 0xAu;\n v1 = a1 & 1;\n }\n if ( a1 <= 9 )\n break;\n a1 /= 0xAu;\n }\n if ( !v1 )\n return 0;\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12C0(int a1) {\n int v1;\n unsigned int v2;\n if (a1 <= 0) return 0LL;\n v1 = 0;\n v2 = 1;\n while (1) {\n if ((a1 & 1) != 0) {\n v2 *= a1 % 10u;\n v1 = a1 & 1;\n }\n if (a1 <= 9) break;\n a1 /= 10u;\n }\n if (!v1) return 0;\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n unsigned int v2;\n if (a1 <= 0) return 0LL;\n v1 = 0;\n v2 = 1;\n while (1) {\n if ((a1 & 1) != 0) {\n v2 *= a1 % 10u;\n v1 = a1 & 1;\n }\n if (a1 <= 9) break;\n a1 /= 10u;\n }\n if (!v1) return 0;\n return v2;\n}" + }, + { + "index": "HumanEval-C-132", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(const char *str) {\n int count = 0, maxcount = 0;\n for (int i = 0; i < strlen(str); i++) {\n if (str[i] == '[') count += 1;\n if (str[i] == ']') count -= 1;\n if (count < 0) count = 0;\n if (count > maxcount) maxcount = count;\n if (count <= maxcount - 2) return 1;\n }\n return 0;\n}", + "test": "#include \n\nint func0(const char *str);\n\nint main() {\n assert(func0(\"[[]]\") == 1);\n assert(func0(\"[]]]]]]][[[[[]\") == 0);\n assert(func0(\"[][]\") == 0);\n assert(func0(\"[]\") == 0);\n assert(func0(\"[[[[]]]]\") == 1);\n assert(func0(\"[]]]]]]]]]]\") == 0);\n assert(func0(\"[][][[]]\") == 1);\n assert(func0(\"[[]\") == 0);\n assert(func0(\"[]]\") == 0);\n assert(func0(\"[[]][[\") == 1);\n assert(func0(\"[[][]]\") == 1);\n assert(func0(\"\") == 0);\n assert(func0(\"[[[[[[[[\") == 0);\n assert(func0(\"]]]]]]]]\") == 0);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+s], rdi\nmov [rbp+var_1C], 0\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp short loc_11F2\nloc_1191:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 5Bh ; '['\njnz short loc_11A9\nadd [rbp+var_1C], 1\nloc_11A9:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 5Dh ; ']'\njnz short loc_11C1\nsub [rbp+var_1C], 1\nloc_11C1:\ncmp [rbp+var_1C], 0\njns short loc_11CE\nmov [rbp+var_1C], 0\nloc_11CE:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_18]\njle short loc_11DC\nmov eax, [rbp+var_1C]\nmov [rbp+var_18], eax\nloc_11DC:\nmov eax, [rbp+var_18]\nsub eax, 1\ncmp [rbp+var_1C], eax\njge short loc_11EE\nmov eax, 1\njmp short loc_120E\nloc_11EE:\nadd [rbp+var_14], 1\nloc_11F2:\nmov eax, [rbp+var_14]\nmovsxd rbx, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rbx, rax\njb short loc_1191\nmov eax, 0\nloc_120E:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v2; // [rsp+14h] [rbp-1Ch]\n int v3; // [rsp+18h] [rbp-18h]\n int i; // [rsp+1Ch] [rbp-14h]\n\n v2 = 0;\n v3 = 0;\n for ( i = 0; i < strlen(a1); ++i )\n {\n if ( a1[i] == 91 )\n ++v2;\n if ( a1[i] == 93 )\n --v2;\n if ( v2 < 0 )\n v2 = 0;\n if ( v2 > v3 )\n v3 = v2;\n if ( v2 < v3 - 1 )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+s], rdi\nmov [rbp+var_1C], 0\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp short loc_11F2\nloc_1191:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 5Bh ; '['\njnz short loc_11A9\nadd [rbp+var_1C], 1\nloc_11A9:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 5Dh ; ']'\njnz short loc_11C1\nsub [rbp+var_1C], 1\nloc_11C1:\ncmp [rbp+var_1C], 0\njns short loc_11CE\nmov [rbp+var_1C], 0\nloc_11CE:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_18]\njle short loc_11DC\nmov eax, [rbp+var_1C]\nmov [rbp+var_18], eax\nloc_11DC:\nmov eax, [rbp+var_18]\nsub eax, 1\ncmp [rbp+var_1C], eax\njge short loc_11EE\nmov eax, 1\njmp short loc_120E\nloc_11EE:\nadd [rbp+var_14], 1\nloc_11F2:\nmov eax, [rbp+var_14]\nmovsxd rbx, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rbx, rax\njb short loc_1191\nmov eax, 0\nloc_120E:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1)\n{\n int v2; // [rsp+14h] [rbp-1Ch]\n int v3; // [rsp+18h] [rbp-18h]\n int i; // [rsp+1Ch] [rbp-14h]\n\n v2 = 0;\n v3 = 0;\n for ( i = 0; i < strlen(a1); ++i )\n {\n if ( a1[i] == 91 )\n ++v2;\n if ( a1[i] == 93 )\n --v2;\n if ( v2 < 0 )\n v2 = 0;\n if ( v2 > v3 )\n v3 = v2;\n if ( v2 < v3 - 1 )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1) {\n int v2;\n int v3;\n int i;\n v2 = 0;\n v3 = 0;\n for (i = 0; i < strlen(a1); ++i) {\n if (a1[i] == 91) ++v2;\n if (a1[i] == 93) --v2;\n if (v2 < 0) v2 = 0;\n if (v2 > v3) v3 = v2;\n if (v2 < v3 - 1) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v2;\n int v3;\n int i;\n v2 = 0;\n v3 = 0;\n for (i = 0; i < strlen(a1); ++i) {\n if (a1[i] == 91) ++v2;\n if (a1[i] == 93) --v2;\n if (v2 < 0) v2 = 0;\n if (v2 > v3) v3 = v2;\n if (v2 < v3 - 1) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": "HumanEval-C-132", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(const char *str) {\n int count = 0, maxcount = 0;\n for (int i = 0; i < strlen(str); i++) {\n if (str[i] == '[') count += 1;\n if (str[i] == ']') count -= 1;\n if (count < 0) count = 0;\n if (count > maxcount) maxcount = count;\n if (count <= maxcount - 2) return 1;\n }\n return 0;\n}", + "test": "#include \n\nint func0(const char *str);\n\nint main() {\n assert(func0(\"[[]]\") == 1);\n assert(func0(\"[]]]]]]][[[[[]\") == 0);\n assert(func0(\"[][]\") == 0);\n assert(func0(\"[]\") == 0);\n assert(func0(\"[[[[]]]]\") == 1);\n assert(func0(\"[]]]]]]]]]]\") == 0);\n assert(func0(\"[][][[]]\") == 1);\n assert(func0(\"[[]\") == 0);\n assert(func0(\"[]]\") == 0);\n assert(func0(\"[[]][[\") == 1);\n assert(func0(\"[[][]]\") == 1);\n assert(func0(\"\") == 0);\n assert(func0(\"[[[[[[[[\") == 0);\n assert(func0(\"]]]]]]]]\") == 0);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmov rdx, rbx\nlea rdi, [rbx+rax]\nmov ecx, 0\nmov eax, 0\njmp short loc_11A6\nloc_1189:\nadd eax, 1\nloc_118C:\ntest eax, eax\nmov esi, 0\ncmovs eax, esi\ncmp ecx, eax\ncmovl ecx, eax\nadd rdx, 1\nlea esi, [rcx-1]\ncmp eax, esi\njl short loc_11CB\nloc_11A6:\ncmp rdx, rdi\njz short loc_11C4\nmovzx esi, byte ptr [rdx]\ncmp sil, 5Bh ; '['\njz short loc_1189\ncmp sil, 5Dh ; ']'\nsetz sil\nmovzx esi, sil\nsub eax, esi\njmp short loc_118C\nloc_11C4:\nmov eax, 0\nloc_11C9:\npop rbx\nretn\nloc_11CB:\nmov eax, 1\njmp short loc_11C9", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n size_t v1; // rax\n const char *v2; // rdx\n const char *v3; // rdi\n int v4; // ecx\n int v5; // eax\n\n v1 = strlen(a1);\n v2 = a1;\n v3 = &a1[v1];\n v4 = 0;\n v5 = 0;\n do\n {\n if ( v2 == v3 )\n return 0LL;\n if ( *v2 == 91 )\n ++v5;\n else\n v5 -= *v2 == 93;\n if ( v5 < 0 )\n v5 = 0;\n if ( v4 < v5 )\n v4 = v5;\n ++v2;\n }\n while ( v5 >= v4 - 1 );\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmov rdx, rbx\nlea rdi, [rbx+rax]\nmov ecx, 0\nmov eax, 0\njmp short loc_11A6\nloc_1189:\nadd eax, 1\nloc_118C:\ntest eax, eax\nmov esi, 0\ncmovs eax, esi\ncmp ecx, eax\ncmovl ecx, eax\nadd rdx, 1\nlea esi, [rcx-1]\ncmp eax, esi\njl short loc_11CB\nloc_11A6:\ncmp rdx, rdi\njz short loc_11C4\nmovzx esi, byte ptr [rdx]\ncmp sil, 5Bh ; '['\njz short loc_1189\ncmp sil, 5Dh ; ']'\nsetz sil\nmovzx esi, sil\nsub eax, esi\njmp short loc_118C\nloc_11C4:\nmov eax, 0\nloc_11C9:\npop rbx\nretn\nloc_11CB:\nmov eax, 1\njmp short loc_11C9", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1)\n{\n size_t v1; // rax\n const char *v2; // rdx\n const char *v3; // rdi\n int v4; // ecx\n int v5; // eax\n\n v1 = strlen(a1);\n v2 = a1;\n v3 = &a1[v1];\n v4 = 0;\n v5 = 0;\n do\n {\n if ( v2 == v3 )\n return 0LL;\n if ( *v2 == 91 )\n ++v5;\n else\n v5 -= *v2 == 93;\n if ( v5 < 0 )\n v5 = 0;\n if ( v4 < v5 )\n v4 = v5;\n ++v2;\n }\n while ( v5 >= v4 - 1 );\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1) {\n unsigned int v1;\n const char *v2;\n const char *v3;\n int v4;\n int v5;\n v1 = strlen(a1);\n v2 = a1;\n v3 = &a1[v1];\n v4 = 0;\n v5 = 0;\n do {\n if (v2 == v3) return 0LL;\n if (*v2 == 91)\n ++v5;\n else\n v5 -= *v2 == 93;\n if (v5 < 0) v5 = 0;\n if (v4 < v5) v4 = v5;\n ++v2;\n } while (v5 >= v4 - 1);\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n unsigned int v1;\n const char *v2;\n const char *v3;\n int v4;\n int v5;\n v1 = strlen(a1);\n v2 = a1;\n v3 = &a1[v1];\n v4 = 0;\n v5 = 0;\n do {\n if (v2 == v3) return 0LL;\n if (*v2 == 91)\n ++v5;\n else\n v5 -= *v2 == 93;\n if (v5 < 0) v5 = 0;\n if (v4 < v5) v4 = v5;\n ++v2;\n } while (v5 >= v4 - 1);\n return 1LL;\n}" + }, + { + "index": "HumanEval-C-132", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(const char *str) {\n int count = 0, maxcount = 0;\n for (int i = 0; i < strlen(str); i++) {\n if (str[i] == '[') count += 1;\n if (str[i] == ']') count -= 1;\n if (count < 0) count = 0;\n if (count > maxcount) maxcount = count;\n if (count <= maxcount - 2) return 1;\n }\n return 0;\n}", + "test": "#include \n\nint func0(const char *str);\n\nint main() {\n assert(func0(\"[[]]\") == 1);\n assert(func0(\"[]]]]]]][[[[[]\") == 0);\n assert(func0(\"[][]\") == 0);\n assert(func0(\"[]\") == 0);\n assert(func0(\"[[[[]]]]\") == 1);\n assert(func0(\"[]]]]]]]]]]\") == 0);\n assert(func0(\"[][][[]]\") == 1);\n assert(func0(\"[[]\") == 0);\n assert(func0(\"[]]\") == 0);\n assert(func0(\"[[]][[\") == 1);\n assert(func0(\"[[][]]\") == 1);\n assert(func0(\"\") == 0);\n assert(func0(\"[[[[[[[[\") == 0);\n assert(func0(\"]]]]]]]]\") == 0);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmov rdi, rbx\nxor ecx, ecx\nxor edx, edx\nadd rax, rbx\nxor r8d, r8d\njmp short loc_1490\nloc_1470:\ncmp sil, 5Dh ; ']'\njnz short loc_1480\nsub edx, 1\ncmp edx, 0FFFFFFFFh\ncmovz edx, r8d\nloc_1480:\ncmp ecx, edx\ncmovl ecx, edx\nadd rdi, 1\nlea esi, [rcx-1]\ncmp esi, edx\njg short loc_14B1\nloc_1490:\ncmp rdi, rax\njz short loc_14C0\nmovzx esi, byte ptr [rdi]\ncmp sil, 5Bh ; '['\njnz short loc_1470\nadd edx, 1\ncmp ecx, edx\ncmovl ecx, edx\nadd rdi, 1\nlea esi, [rcx-1]\ncmp esi, edx\njle short loc_1490\nloc_14B1:\nmov eax, 1\npop rbx\nretn\nloc_14C0:\nxor eax, eax\npop rbx\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n size_t v1; // rax\n int v2; // ecx\n int v3; // edx\n const char *v4; // rax\n\n v1 = strlen(a1);\n v2 = 0;\n v3 = 0;\n v4 = &a1[v1];\n while ( a1 != v4 )\n {\n if ( *a1 == 91 )\n {\n if ( v2 < ++v3 )\n v2 = v3;\n ++a1;\n if ( v2 - 1 > v3 )\n return 1LL;\n }\n else\n {\n if ( *a1 == 93 && --v3 == -1 )\n v3 = 0;\n if ( v2 < v3 )\n v2 = v3;\n ++a1;\n if ( v2 - 1 > v3 )\n return 1LL;\n }\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1450:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmov rdi, rbx\nxor ecx, ecx\nxor edx, edx\nadd rax, rbx\nxor r8d, r8d\njmp short loc_1490\nloc_1470:\ncmp sil, 5Dh ; ']'\njnz short loc_1480\nsub edx, 1\ncmp edx, 0FFFFFFFFh\ncmovz edx, r8d\nloc_1480:\ncmp ecx, edx\ncmovl ecx, edx\nadd rdi, 1\nlea esi, [rcx-1]\ncmp esi, edx\njg short loc_14B1\nloc_1490:\ncmp rdi, rax\njz short loc_14C0\nmovzx esi, byte ptr [rdi]\ncmp sil, 5Bh ; '['\njnz short loc_1470\nadd edx, 1\ncmp ecx, edx\ncmovl ecx, edx\nadd rdi, 1\nlea esi, [rcx-1]\ncmp esi, edx\njle short loc_1490\nloc_14B1:\nmov eax, 1\npop rbx\nretn\nloc_14C0:\nxor eax, eax\npop rbx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1450(const char *a1)\n{\n size_t v1; // rax\n int v2; // ecx\n int v3; // edx\n const char *v4; // rax\n\n v1 = strlen(a1);\n v2 = 0;\n v3 = 0;\n v4 = &a1[v1];\n while ( a1 != v4 )\n {\n if ( *a1 == 91 )\n {\n if ( v2 < ++v3 )\n v2 = v3;\n ++a1;\n if ( v2 - 1 > v3 )\n return 1LL;\n }\n else\n {\n if ( *a1 == 93 && --v3 == -1 )\n v3 = 0;\n if ( v2 < v3 )\n v2 = v3;\n ++a1;\n if ( v2 - 1 > v3 )\n return 1LL;\n }\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1450(const char *a1) {\n unsigned int v1;\n int v2;\n int v3;\n const char *v4;\n v1 = strlen(a1);\n v2 = 0;\n v3 = 0;\n v4 = &a1[v1];\n while (a1 != v4) {\n if (*a1 == 91) {\n if (v2 < ++v3) v2 = v3;\n ++a1;\n if (v2 - 1 > v3) return 1LL;\n } else {\n if (*a1 == 93 && --v3 == -1) v3 = 0;\n if (v2 < v3) v2 = v3;\n ++a1;\n if (v2 - 1 > v3) return 1LL;\n }\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n unsigned int v1;\n int v2;\n int v3;\n const char *v4;\n v1 = strlen(a1);\n v2 = 0;\n v3 = 0;\n v4 = &a1[v1];\n while (a1 != v4) {\n if (*a1 == 91) {\n if (v2 < ++v3) v2 = v3;\n ++a1;\n if (v2 - 1 > v3) return 1LL;\n } else {\n if (*a1 == 93 && --v3 == -1) v3 = 0;\n if (v2 < v3) v2 = v3;\n ++a1;\n if (v2 - 1 > v3) return 1LL;\n }\n }\n return 0LL;\n}" + }, + { + "index": "HumanEval-C-132", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(const char *str) {\n int count = 0, maxcount = 0;\n for (int i = 0; i < strlen(str); i++) {\n if (str[i] == '[') count += 1;\n if (str[i] == ']') count -= 1;\n if (count < 0) count = 0;\n if (count > maxcount) maxcount = count;\n if (count <= maxcount - 2) return 1;\n }\n return 0;\n}", + "test": "#include \n\nint func0(const char *str);\n\nint main() {\n assert(func0(\"[[]]\") == 1);\n assert(func0(\"[]]]]]]][[[[[]\") == 0);\n assert(func0(\"[][]\") == 0);\n assert(func0(\"[]\") == 0);\n assert(func0(\"[[[[]]]]\") == 1);\n assert(func0(\"[]]]]]]]]]]\") == 0);\n assert(func0(\"[][][[]]\") == 1);\n assert(func0(\"[[]\") == 0);\n assert(func0(\"[]]\") == 0);\n assert(func0(\"[[]][[\") == 1);\n assert(func0(\"[[][]]\") == 1);\n assert(func0(\"\") == 0);\n assert(func0(\"[[[[[[[[\") == 0);\n assert(func0(\"]]]]]]]]\") == 0);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmov rdi, rbx\nxor ecx, ecx\nxor edx, edx\nadd rax, rbx\nxor r8d, r8d\njmp short loc_1490\nloc_1470:\ncmp sil, 5Dh ; ']'\njnz short loc_1480\nsub edx, 1\ncmp edx, 0FFFFFFFFh\ncmovz edx, r8d\nloc_1480:\ncmp ecx, edx\ncmovl ecx, edx\nadd rdi, 1\nlea esi, [rcx-1]\ncmp esi, edx\njg short loc_14B1\nloc_1490:\ncmp rax, rdi\njz short loc_14C0\nmovzx esi, byte ptr [rdi]\ncmp sil, 5Bh ; '['\njnz short loc_1470\nadd edx, 1\ncmp ecx, edx\ncmovl ecx, edx\nadd rdi, 1\nlea esi, [rcx-1]\ncmp esi, edx\njle short loc_1490\nloc_14B1:\nmov eax, 1\npop rbx\nretn\nloc_14C0:\nxor eax, eax\npop rbx\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n size_t v1; // rax\n int v2; // ecx\n int v3; // edx\n const char *v4; // rax\n\n v1 = strlen(a1);\n v2 = 0;\n v3 = 0;\n v4 = &a1[v1];\n while ( v4 != a1 )\n {\n if ( *a1 == 91 )\n {\n if ( v2 < ++v3 )\n v2 = v3;\n ++a1;\n if ( v2 - 1 > v3 )\n return 1LL;\n }\n else\n {\n if ( *a1 == 93 && --v3 == -1 )\n v3 = 0;\n if ( v2 < v3 )\n v2 = v3;\n ++a1;\n if ( v2 - 1 > v3 )\n return 1LL;\n }\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1450:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmov rdi, rbx\nxor ecx, ecx\nxor edx, edx\nadd rax, rbx\nxor r8d, r8d\njmp short loc_1490\nloc_1470:\ncmp sil, 5Dh ; ']'\njnz short loc_1480\nsub edx, 1\ncmp edx, 0FFFFFFFFh\ncmovz edx, r8d\nloc_1480:\ncmp ecx, edx\ncmovl ecx, edx\nadd rdi, 1\nlea esi, [rcx-1]\ncmp esi, edx\njg short loc_14B1\nloc_1490:\ncmp rax, rdi\njz short loc_14C0\nmovzx esi, byte ptr [rdi]\ncmp sil, 5Bh ; '['\njnz short loc_1470\nadd edx, 1\ncmp ecx, edx\ncmovl ecx, edx\nadd rdi, 1\nlea esi, [rcx-1]\ncmp esi, edx\njle short loc_1490\nloc_14B1:\nmov eax, 1\npop rbx\nretn\nloc_14C0:\nxor eax, eax\npop rbx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1450(const char *a1)\n{\n size_t v1; // rax\n int v2; // ecx\n int v3; // edx\n const char *v4; // rax\n\n v1 = strlen(a1);\n v2 = 0;\n v3 = 0;\n v4 = &a1[v1];\n while ( v4 != a1 )\n {\n if ( *a1 == 91 )\n {\n if ( v2 < ++v3 )\n v2 = v3;\n ++a1;\n if ( v2 - 1 > v3 )\n return 1LL;\n }\n else\n {\n if ( *a1 == 93 && --v3 == -1 )\n v3 = 0;\n if ( v2 < v3 )\n v2 = v3;\n ++a1;\n if ( v2 - 1 > v3 )\n return 1LL;\n }\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1450(const char *a1) {\n unsigned int v1;\n int v2;\n int v3;\n const char *v4;\n v1 = strlen(a1);\n v2 = 0;\n v3 = 0;\n v4 = &a1[v1];\n while (v4 != a1) {\n if (*a1 == 91) {\n if (v2 < ++v3) v2 = v3;\n ++a1;\n if (v2 - 1 > v3) return 1LL;\n } else {\n if (*a1 == 93 && --v3 == -1) v3 = 0;\n if (v2 < v3) v2 = v3;\n ++a1;\n if (v2 - 1 > v3) return 1LL;\n }\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n unsigned int v1;\n int v2;\n int v3;\n const char *v4;\n v1 = strlen(a1);\n v2 = 0;\n v3 = 0;\n v4 = &a1[v1];\n while (v4 != a1) {\n if (*a1 == 91) {\n if (v2 < ++v3) v2 = v3;\n ++a1;\n if (v2 - 1 > v3) return 1LL;\n } else {\n if (*a1 == 93 && --v3 == -1) v3 = 0;\n if (v2 < v3) v2 = v3;\n ++a1;\n if (v2 - 1 > v3) return 1LL;\n }\n }\n return 0LL;\n}" + }, + { + "index": "HumanEval-C-133", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(float *lst, int size) {\n int sum = 0;\n for (int i = 0; i < size; i++) {\n sum += (int)ceil(lst[i]) * (int)ceil(lst[i]);\n }\n return sum;\n}", + "test": "#include \n\n\nint main() {\n float lst1[] = {1, 2, 3};\n assert(func0(lst1, 3) == 14);\n\n float lst2[] = {1.0, 2, 3};\n assert(func0(lst2, 3) == 14);\n\n float lst3[] = {1, 3, 5, 7};\n assert(func0(lst3, 4) == 84);\n\n float lst4[] = {1.4, 4.2, 0};\n assert(func0(lst4, 3) == 29);\n\n float lst5[] = {-2.4, 1, 1};\n assert(func0(lst5, 3) == 6);\n\n float lst6[] = {100, 1, 15, 2};\n assert(func0(lst6, 4) == 10230);\n\n float lst7[] = {10000, 10000};\n assert(func0(lst7, 2) == 200000000);\n\n float lst8[] = {-1.4, 4.6, 6.3};\n assert(func0(lst8, 3) == 75);\n\n float lst9[] = {-1.4, 17.9, 18.9, 19.9};\n assert(func0(lst9, 4) == 1086);\n\n float lst10[] = {0};\n assert(func0(lst10, 1) == 0);\n\n float lst11[] = {-1};\n assert(func0(lst11, 1) == 1);\n\n float lst12[] = {-1, 1, 0};\n assert(func0(lst12, 3) == 2);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp short loc_121D\nloc_11AD:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\npxor xmm1, xmm1\ncvtss2sd xmm1, xmm0\nmovq rax, xmm1\nmovq xmm0, rax; x\ncall _ceil\ncvttsd2si ebx, xmm0\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\npxor xmm2, xmm2\ncvtss2sd xmm2, xmm0\nmovq rax, xmm2\nmovq xmm0, rax; x\ncall _ceil\ncvttsd2si eax, xmm0\nimul eax, ebx\nadd [rbp+var_18], eax\nadd [rbp+var_14], 1\nloc_121D:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl short loc_11AD\nmov eax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int v2; // ebx\n unsigned int v4; // [rsp+18h] [rbp-18h]\n int i; // [rsp+1Ch] [rbp-14h]\n\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v2 = (int)ceil(*(float *)(4LL * i + a1));\n v4 += v2 * (int)ceil(*(float *)(4LL * i + a1));\n }\n return v4;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp short loc_121D\nloc_11AD:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\npxor xmm1, xmm1\ncvtss2sd xmm1, xmm0\nmovq rax, xmm1\nmovq xmm0, rax; x\ncall _ceil\ncvttsd2si ebx, xmm0\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\npxor xmm2, xmm2\ncvtss2sd xmm2, xmm0\nmovq rax, xmm2\nmovq xmm0, rax; x\ncall _ceil\ncvttsd2si eax, xmm0\nimul eax, ebx\nadd [rbp+var_18], eax\nadd [rbp+var_14], 1\nloc_121D:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl short loc_11AD\nmov eax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2)\n{\n int v2; // ebx\n unsigned int v4; // [rsp+18h] [rbp-18h]\n int i; // [rsp+1Ch] [rbp-14h]\n\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v2 = (int)ceil(*(float *)(4LL * i + a1));\n v4 += v2 * (int)ceil(*(float *)(4LL * i + a1));\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2) {\n int v2;\n unsigned int v4;\n int i;\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n v2 = (int)ceil(*(float *)(4LL * i + a1));\n v4 += v2 * (int)ceil(*(float *)(4LL * i + a1));\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int v2;\n unsigned int v4;\n int i;\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n v2 = (int)ceil(*(float *)(4LL * i + a1));\n v4 += v2 * (int)ceil(*(float *)(4LL * i + a1));\n }\n return v4;\n}" + }, + { + "index": "HumanEval-C-133", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(float *lst, int size) {\n int sum = 0;\n for (int i = 0; i < size; i++) {\n sum += (int)ceil(lst[i]) * (int)ceil(lst[i]);\n }\n return sum;\n}", + "test": "#include \n\n\nint main() {\n float lst1[] = {1, 2, 3};\n assert(func0(lst1, 3) == 14);\n\n float lst2[] = {1.0, 2, 3};\n assert(func0(lst2, 3) == 14);\n\n float lst3[] = {1, 3, 5, 7};\n assert(func0(lst3, 4) == 84);\n\n float lst4[] = {1.4, 4.2, 0};\n assert(func0(lst4, 3) == 29);\n\n float lst5[] = {-2.4, 1, 1};\n assert(func0(lst5, 3) == 6);\n\n float lst6[] = {100, 1, 15, 2};\n assert(func0(lst6, 4) == 10230);\n\n float lst7[] = {10000, 10000};\n assert(func0(lst7, 2) == 200000000);\n\n float lst8[] = {-1.4, 4.6, 6.3};\n assert(func0(lst8, 3) == 75);\n\n float lst9[] = {-1.4, 17.9, 18.9, 19.9};\n assert(func0(lst9, 4) == 1086);\n\n float lst10[] = {0};\n assert(func0(lst10, 1) == 0);\n\n float lst11[] = {-1};\n assert(func0(lst11, 1) == 1);\n\n float lst12[] = {-1, 1, 0};\n assert(func0(lst12, 3) == 2);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11E1\nmov rdx, rdi\nmovsxd rsi, esi\nlea rsi, [rdi+rsi*4]\nmov ecx, 0\nmovss xmm4, cs:dword_2004\nmovss xmm3, cs:dword_200C\nmovss xmm5, cs:dword_2008\njmp short loc_11AC\nloc_119A:\ncvttss2si eax, xmm2\nimul eax, eax\nadd ecx, eax\nadd rdx, 4\ncmp rdx, rsi\njz short loc_11E6\nloc_11AC:\nmovss xmm1, dword ptr [rdx]\nmovaps xmm2, xmm1\nmovaps xmm0, xmm1\nandps xmm0, xmm3\nucomiss xmm4, xmm0\njbe short loc_119A\ncvttss2si eax, xmm1\npxor xmm0, xmm0\ncvtsi2ss xmm0, eax\ncmpnless xmm2, xmm0\nandps xmm2, xmm5\naddss xmm0, xmm2\nmovaps xmm2, xmm3\nandnps xmm2, xmm1\norps xmm2, xmm0\njmp short loc_119A\nloc_11E1:\nmov ecx, 0\nloc_11E6:\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(float *a1, int a2)\n{\n float *v2; // rdx\n float *v3; // rsi\n unsigned int v4; // ecx\n __m128 v5; // xmm1\n float v6; // xmm2_4\n __m128 v7; // xmm0\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n {\n v5 = (__m128)*(unsigned int *)v2;\n v6 = v5.m128_f32[0];\n if ( fabs(*v2) < 8388608.0 )\n {\n v7.m128_f32[0] = (float)(int)v5.m128_f32[0];\n LODWORD(v6) = _mm_andnot_ps((__m128)0x7FFFFFFFu, v5).m128_u32[0] | COERCE_UNSIGNED_INT(\n v7.m128_f32[0]\n + COERCE_FLOAT(_mm_cmpgt_ss(v5, v7).m128_u32[0] & 0x3F800000));\n }\n v4 += (int)v6 * (int)v6;\n ++v2;\n }\n while ( v2 != v3 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11E1\nmov rdx, rdi\nmovsxd rsi, esi\nlea rsi, [rdi+rsi*4]\nmov ecx, 0\nmovss xmm4, cs:dword_2004\nmovss xmm3, cs:dword_200C\nmovss xmm5, cs:dword_2008\njmp short loc_11AC\nloc_119A:\ncvttss2si eax, xmm2\nimul eax, eax\nadd ecx, eax\nadd rdx, 4\ncmp rdx, rsi\njz short loc_11E6\nloc_11AC:\nmovss xmm1, dword ptr [rdx]\nmovaps xmm2, xmm1\nmovaps xmm0, xmm1\nandps xmm0, xmm3\nucomiss xmm4, xmm0\njbe short loc_119A\ncvttss2si eax, xmm1\npxor xmm0, xmm0\ncvtsi2ss xmm0, eax\ncmpnless xmm2, xmm0\nandps xmm2, xmm5\naddss xmm0, xmm2\nmovaps xmm2, xmm3\nandnps xmm2, xmm1\norps xmm2, xmm0\njmp short loc_119A\nloc_11E1:\nmov ecx, 0\nloc_11E6:\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(float *a1, int a2)\n{\n float *v2; // rdx\n float *v3; // rsi\n unsigned int v4; // ecx\n __m128 v5; // xmm1\n float v6; // xmm2_4\n __m128 v7; // xmm0\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n {\n v5 = (__m128)*(unsigned int *)v2;\n v6 = v5.m128_f32[0];\n if ( fabs(*v2) < 8388608.0 )\n {\n v7.m128_f32[0] = (float)(int)v5.m128_f32[0];\n LODWORD(v6) = _mm_andnot_ps((__m128)0x7FFFFFFFu, v5).m128_u32[0] | COERCE_UNSIGNED_INT(\n v7.m128_f32[0]\n + COERCE_FLOAT(_mm_cmpgt_ss(v5, v7).m128_u32[0] & 0x3F800000));\n }\n v4 += (int)v6 * (int)v6;\n ++v2;\n }\n while ( v2 != v3 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(float *a1, int a2) {\n float *v2;\n float *v3;\n unsigned int v4;\n __m128 v5;\n float v6;\n __m128 v7;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do {\n v5 = (__m128) * (unsigned int *)v2;\n v6 = v5.m128_f32[0];\n if (fabs(*v2) < 8388608.0) {\n v7.m128_f32[0] = (float)(int)v5.m128_f32[0];\n LODWORD(v6) =\n _mm_andnot_ps((__m128)2147483647u, v5).m128_u32[0] |\n COERCE_UNSIGNED_INT(\n v7.m128_f32[0] +\n COERCE_FLOAT(_mm_cmpgt_ss(v5, v7).m128_u32[0] & 1065353216));\n }\n v4 += (int)v6 * (int)v6;\n ++v2;\n } while (v2 != v3);\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(float *a1, int a2) {\n float *v2;\n float *v3;\n unsigned int v4;\n __m128 v5;\n float v6;\n __m128 v7;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do {\n v5 = (__m128) * (unsigned int *)v2;\n v6 = v5.m128_f32[0];\n if (fabs(*v2) < 8388608.0) {\n v7.m128_f32[0] = (float)(int)v5.m128_f32[0];\n LODWORD(v6) =\n _mm_andnot_ps((__m128)2147483647u, v5).m128_u32[0] |\n COERCE_UNSIGNED_INT(\n v7.m128_f32[0] +\n COERCE_FLOAT(_mm_cmpgt_ss(v5, v7).m128_u32[0] & 1065353216));\n }\n v4 += (int)v6 * (int)v6;\n ++v2;\n } while (v2 != v3);\n }\n return v4;\n}" + }, + { + "index": "HumanEval-C-133", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(float *lst, int size) {\n int sum = 0;\n for (int i = 0; i < size; i++) {\n sum += (int)ceil(lst[i]) * (int)ceil(lst[i]);\n }\n return sum;\n}", + "test": "#include \n\n\nint main() {\n float lst1[] = {1, 2, 3};\n assert(func0(lst1, 3) == 14);\n\n float lst2[] = {1.0, 2, 3};\n assert(func0(lst2, 3) == 14);\n\n float lst3[] = {1, 3, 5, 7};\n assert(func0(lst3, 4) == 84);\n\n float lst4[] = {1.4, 4.2, 0};\n assert(func0(lst4, 3) == 29);\n\n float lst5[] = {-2.4, 1, 1};\n assert(func0(lst5, 3) == 6);\n\n float lst6[] = {100, 1, 15, 2};\n assert(func0(lst6, 4) == 10230);\n\n float lst7[] = {10000, 10000};\n assert(func0(lst7, 2) == 200000000);\n\n float lst8[] = {-1.4, 4.6, 6.3};\n assert(func0(lst8, 3) == 75);\n\n float lst9[] = {-1.4, 17.9, 18.9, 19.9};\n assert(func0(lst9, 4) == 1086);\n\n float lst10[] = {0};\n assert(func0(lst10, 1) == 0);\n\n float lst11[] = {-1};\n assert(func0(lst11, 1) == 1);\n\n float lst12[] = {-1, 1, 0};\n assert(func0(lst12, 3) == 2);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1590\nmovsxd rsi, esi\nmovss xmm4, cs:dword_2004\nxor edx, edx\nmovss xmm3, cs:dword_2008\nmovss xmm5, dword ptr cs:xmmword_2170\nlea rcx, [rdi+rsi*4]\nnop dword ptr [rax+00000000h]\nloc_1540:\nmovss xmm0, dword ptr [rdi]\nmovaps xmm1, xmm0\nandps xmm1, xmm3\nucomiss xmm4, xmm1\njbe short loc_1576\ncvttss2si eax, xmm0\npxor xmm1, xmm1\nmovaps xmm2, xmm0\ncvtsi2ss xmm1, eax\ncmpnless xmm2, xmm1\nandps xmm2, xmm5\naddss xmm1, xmm2\nmovaps xmm2, xmm3\nandnps xmm2, xmm0\nmovaps xmm0, xmm1\norps xmm0, xmm2\nloc_1576:\ncvttss2si eax, xmm0\nadd rdi, 4\nimul eax, eax\nadd edx, eax\ncmp rcx, rdi\njnz short loc_1540\nmov eax, edx\nretn\nloc_1590:\nxor edx, edx\nmov eax, edx\nretn", + "ida_pseudo": "__int64 __fastcall func0(float *a1, int a2)\n{\n unsigned int v2; // edx\n float *v3; // rcx\n __m128 v4; // xmm0\n __m128 v5; // xmm1\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 0;\n v3 = &a1[a2];\n do\n {\n v4 = (__m128)*(unsigned int *)a1;\n if ( fabs(*a1) < 8388608.0 )\n {\n v5.m128_f32[0] = (float)(int)v4.m128_f32[0];\n v4.m128_i32[0] = COERCE_UNSIGNED_INT(v5.m128_f32[0] + COERCE_FLOAT(_mm_cmpgt_ss(v4, v5).m128_u32[0] & 0x3F800000)) | _mm_andnot_ps((__m128)0x7FFFFFFFu, v4).m128_u32[0];\n }\n ++a1;\n v2 += (int)v4.m128_f32[0] * (int)v4.m128_f32[0];\n }\n while ( v3 != a1 );\n return v2;\n}", + "ida_strip_asm": "sub_1510:\nendbr64\ntest esi, esi\njle short loc_1590\nmovsxd rsi, esi\nmovss xmm4, cs:dword_2004\nxor edx, edx\nmovss xmm3, cs:dword_2008\nmovss xmm5, dword ptr cs:xmmword_2170\nlea rcx, [rdi+rsi*4]\nnop dword ptr [rax+00000000h]\nloc_1540:\nmovss xmm0, dword ptr [rdi]\nmovaps xmm1, xmm0\nandps xmm1, xmm3\nucomiss xmm4, xmm1\njbe short loc_1576\ncvttss2si eax, xmm0\npxor xmm1, xmm1\nmovaps xmm2, xmm0\ncvtsi2ss xmm1, eax\ncmpnless xmm2, xmm1\nandps xmm2, xmm5\naddss xmm1, xmm2\nmovaps xmm2, xmm3\nandnps xmm2, xmm0\nmovaps xmm0, xmm1\norps xmm0, xmm2\nloc_1576:\ncvttss2si eax, xmm0\nadd rdi, 4\nimul eax, eax\nadd edx, eax\ncmp rcx, rdi\njnz short loc_1540\nmov eax, edx\nretn\nloc_1590:\nxor edx, edx\nmov eax, edx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1510(float *a1, int a2)\n{\n unsigned int v2; // edx\n float *v3; // rcx\n __m128 v4; // xmm0\n __m128 v5; // xmm1\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 0;\n v3 = &a1[a2];\n do\n {\n v4 = (__m128)*(unsigned int *)a1;\n if ( fabs(*a1) < 8388608.0 )\n {\n v5.m128_f32[0] = (float)(int)v4.m128_f32[0];\n v4.m128_i32[0] = COERCE_UNSIGNED_INT(v5.m128_f32[0] + COERCE_FLOAT(_mm_cmpgt_ss(v4, v5).m128_u32[0] & 0x3F800000)) | _mm_andnot_ps((__m128)0x7FFFFFFFu, v4).m128_u32[0];\n }\n ++a1;\n v2 += (int)v4.m128_f32[0] * (int)v4.m128_f32[0];\n }\n while ( v3 != a1 );\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1510(float *a1, int a2) {\n unsigned int v2;\n float *v3;\n __m128 v4;\n __m128 v5;\n if (a2 <= 0) return 0LL;\n v2 = 0;\n v3 = &a1[a2];\n do {\n v4 = (__m128) * (unsigned int *)a1;\n if (fabs(*a1) < 8388608.0) {\n v5.m128_f32[0] = (float)(int)v4.m128_f32[0];\n v4.m128_i32[0] =\n COERCE_UNSIGNED_INT(\n v5.m128_f32[0] +\n COERCE_FLOAT(_mm_cmpgt_ss(v4, v5).m128_u32[0] & 1065353216)) |\n _mm_andnot_ps((__m128)2147483647u, v4).m128_u32[0];\n }\n ++a1;\n v2 += (int)v4.m128_f32[0] * (int)v4.m128_f32[0];\n } while (v3 != a1);\n return v2;\n}", + "ida_pseudo_norm": "long long func0(float *a1, int a2) {\n unsigned int v2;\n float *v3;\n __m128 v4;\n __m128 v5;\n if (a2 <= 0) return 0LL;\n v2 = 0;\n v3 = &a1[a2];\n do {\n v4 = (__m128) * (unsigned int *)a1;\n if (fabs(*a1) < 8388608.0) {\n v5.m128_f32[0] = (float)(int)v4.m128_f32[0];\n v4.m128_i32[0] =\n COERCE_UNSIGNED_INT(\n v5.m128_f32[0] +\n COERCE_FLOAT(_mm_cmpgt_ss(v4, v5).m128_u32[0] & 1065353216)) |\n _mm_andnot_ps((__m128)2147483647u, v4).m128_u32[0];\n }\n ++a1;\n v2 += (int)v4.m128_f32[0] * (int)v4.m128_f32[0];\n } while (v3 != a1);\n return v2;\n}" + }, + { + "index": "HumanEval-C-133", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(float *lst, int size) {\n int sum = 0;\n for (int i = 0; i < size; i++) {\n sum += (int)ceil(lst[i]) * (int)ceil(lst[i]);\n }\n return sum;\n}", + "test": "#include \n\n\nint main() {\n float lst1[] = {1, 2, 3};\n assert(func0(lst1, 3) == 14);\n\n float lst2[] = {1.0, 2, 3};\n assert(func0(lst2, 3) == 14);\n\n float lst3[] = {1, 3, 5, 7};\n assert(func0(lst3, 4) == 84);\n\n float lst4[] = {1.4, 4.2, 0};\n assert(func0(lst4, 3) == 29);\n\n float lst5[] = {-2.4, 1, 1};\n assert(func0(lst5, 3) == 6);\n\n float lst6[] = {100, 1, 15, 2};\n assert(func0(lst6, 4) == 10230);\n\n float lst7[] = {10000, 10000};\n assert(func0(lst7, 2) == 200000000);\n\n float lst8[] = {-1.4, 4.6, 6.3};\n assert(func0(lst8, 3) == 75);\n\n float lst9[] = {-1.4, 17.9, 18.9, 19.9};\n assert(func0(lst9, 4) == 1086);\n\n float lst10[] = {0};\n assert(func0(lst10, 1) == 0);\n\n float lst11[] = {-1};\n assert(func0(lst11, 1) == 1);\n\n float lst12[] = {-1, 1, 0};\n assert(func0(lst12, 3) == 2);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1590\nmovsxd rsi, esi\nmovss xmm4, cs:dword_2004\nxor edx, edx\nmovss xmm3, cs:dword_2008\nmovss xmm5, dword ptr cs:xmmword_2170\nlea rcx, [rdi+rsi*4]\nnop dword ptr [rax+00000000h]\nloc_1540:\nmovss xmm0, dword ptr [rdi]\nmovaps xmm1, xmm0\nandps xmm1, xmm3\nucomiss xmm4, xmm1\njbe short loc_1576\ncvttss2si eax, xmm0\npxor xmm1, xmm1\nmovaps xmm2, xmm0\ncvtsi2ss xmm1, eax\ncmpnless xmm2, xmm1\nandps xmm2, xmm5\naddss xmm1, xmm2\nmovaps xmm2, xmm3\nandnps xmm2, xmm0\nmovaps xmm0, xmm1\norps xmm0, xmm2\nloc_1576:\ncvttss2si eax, xmm0\nadd rdi, 4\nimul eax, eax\nadd edx, eax\ncmp rcx, rdi\njnz short loc_1540\nmov eax, edx\nretn\nloc_1590:\nxor edx, edx\nmov eax, edx\nretn", + "ida_pseudo": "__int64 __fastcall func0(float *a1, int a2)\n{\n unsigned int v2; // edx\n float *v3; // rcx\n __m128 v4; // xmm0\n __m128 v5; // xmm1\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 0;\n v3 = &a1[a2];\n do\n {\n v4 = (__m128)*(unsigned int *)a1;\n if ( fabs(*a1) < 8388608.0 )\n {\n v5.m128_f32[0] = (float)(int)v4.m128_f32[0];\n v4.m128_i32[0] = COERCE_UNSIGNED_INT(v5.m128_f32[0] + COERCE_FLOAT(_mm_cmpgt_ss(v4, v5).m128_u32[0] & 0x3F800000)) | _mm_andnot_ps((__m128)0x7FFFFFFFu, v4).m128_u32[0];\n }\n ++a1;\n v2 += (int)v4.m128_f32[0] * (int)v4.m128_f32[0];\n }\n while ( v3 != a1 );\n return v2;\n}", + "ida_strip_asm": "sub_1510:\nendbr64\ntest esi, esi\njle short loc_1590\nmovsxd rsi, esi\nmovss xmm4, cs:dword_2004\nxor edx, edx\nmovss xmm3, cs:dword_2008\nmovss xmm5, dword ptr cs:xmmword_2170\nlea rcx, [rdi+rsi*4]\nnop dword ptr [rax+00000000h]\nloc_1540:\nmovss xmm0, dword ptr [rdi]\nmovaps xmm1, xmm0\nandps xmm1, xmm3\nucomiss xmm4, xmm1\njbe short loc_1576\ncvttss2si eax, xmm0\npxor xmm1, xmm1\nmovaps xmm2, xmm0\ncvtsi2ss xmm1, eax\ncmpnless xmm2, xmm1\nandps xmm2, xmm5\naddss xmm1, xmm2\nmovaps xmm2, xmm3\nandnps xmm2, xmm0\nmovaps xmm0, xmm1\norps xmm0, xmm2\nloc_1576:\ncvttss2si eax, xmm0\nadd rdi, 4\nimul eax, eax\nadd edx, eax\ncmp rcx, rdi\njnz short loc_1540\nmov eax, edx\nretn\nloc_1590:\nxor edx, edx\nmov eax, edx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1510(float *a1, int a2)\n{\n unsigned int v2; // edx\n float *v3; // rcx\n __m128 v4; // xmm0\n __m128 v5; // xmm1\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 0;\n v3 = &a1[a2];\n do\n {\n v4 = (__m128)*(unsigned int *)a1;\n if ( fabs(*a1) < 8388608.0 )\n {\n v5.m128_f32[0] = (float)(int)v4.m128_f32[0];\n v4.m128_i32[0] = COERCE_UNSIGNED_INT(v5.m128_f32[0] + COERCE_FLOAT(_mm_cmpgt_ss(v4, v5).m128_u32[0] & 0x3F800000)) | _mm_andnot_ps((__m128)0x7FFFFFFFu, v4).m128_u32[0];\n }\n ++a1;\n v2 += (int)v4.m128_f32[0] * (int)v4.m128_f32[0];\n }\n while ( v3 != a1 );\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1510(float *a1, int a2) {\n unsigned int v2;\n float *v3;\n __m128 v4;\n __m128 v5;\n if (a2 <= 0) return 0LL;\n v2 = 0;\n v3 = &a1[a2];\n do {\n v4 = (__m128) * (unsigned int *)a1;\n if (fabs(*a1) < 8388608.0) {\n v5.m128_f32[0] = (float)(int)v4.m128_f32[0];\n v4.m128_i32[0] =\n COERCE_UNSIGNED_INT(\n v5.m128_f32[0] +\n COERCE_FLOAT(_mm_cmpgt_ss(v4, v5).m128_u32[0] & 1065353216)) |\n _mm_andnot_ps((__m128)2147483647u, v4).m128_u32[0];\n }\n ++a1;\n v2 += (int)v4.m128_f32[0] * (int)v4.m128_f32[0];\n } while (v3 != a1);\n return v2;\n}", + "ida_pseudo_norm": "long long func0(float *a1, int a2) {\n unsigned int v2;\n float *v3;\n __m128 v4;\n __m128 v5;\n if (a2 <= 0) return 0LL;\n v2 = 0;\n v3 = &a1[a2];\n do {\n v4 = (__m128) * (unsigned int *)a1;\n if (fabs(*a1) < 8388608.0) {\n v5.m128_f32[0] = (float)(int)v4.m128_f32[0];\n v4.m128_i32[0] =\n COERCE_UNSIGNED_INT(\n v5.m128_f32[0] +\n COERCE_FLOAT(_mm_cmpgt_ss(v4, v5).m128_u32[0] & 1065353216)) |\n _mm_andnot_ps((__m128)2147483647u, v4).m128_u32[0];\n }\n ++a1;\n v2 += (int)v4.m128_f32[0] * (int)v4.m128_f32[0];\n } while (v3 != a1);\n return v2;\n}" + }, + { + "index": "HumanEval-C-134", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int func0(const char *txt) {\n int len = strlen(txt);\n if (len == 0) return 0;\n char last_char = txt[len - 1];\n if (!isalpha((unsigned char)last_char)) return 0;\n if (len == 1) return 1;\n char second_last_char = txt[len - 2];\n if (isalpha((unsigned char)second_last_char)) return 0;\n return 1;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"apple\") == 0);\n assert(func0(\"apple pi e\") == 1);\n assert(func0(\"eeeee\") == 0);\n assert(func0(\"A\") == 1);\n assert(func0(\"Pumpkin pie \") == 0);\n assert(func0(\"Pumpkin pie 1\") == 0);\n assert(func0(\"\") == 0);\n assert(func0(\"eeeee e \") == 0);\n assert(func0(\"apple pie\") == 0);\n assert(func0(\"apple pi e \") == 0);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\ncmp [rbp+var_4], 0\njnz short loc_11B8\nmov eax, 0\njmp locret_124C\nloc_11B8:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_6], al\ncall ___ctype_b_loc\nmov rax, [rax]\nmovzx edx, [rbp+var_6]\nmovzx edx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 400h\ntest eax, eax\njnz short loc_11F9\nmov eax, 0\njmp short locret_124C\nloc_11F9:\ncmp [rbp+var_4], 1\njnz short loc_1206\nmov eax, 1\njmp short locret_124C\nloc_1206:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, [rax-2]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_5], al\ncall ___ctype_b_loc\nmov rax, [rax]\nmovzx edx, [rbp+var_5]\nmovzx edx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 400h\ntest eax, eax\njz short loc_1247\nmov eax, 0\njmp short locret_124C\nloc_1247:\nmov eax, 1\nlocret_124C:\nleave\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(const char *a1)\n{\n unsigned __int8 v2; // [rsp+1Ah] [rbp-6h]\n unsigned __int8 v3; // [rsp+1Bh] [rbp-5h]\n int v4; // [rsp+1Ch] [rbp-4h]\n\n v4 = strlen(a1);\n if ( !v4 )\n return 0LL;\n v2 = a1[v4 - 1];\n if ( ((*__ctype_b_loc())[v2] & 0x400) == 0 )\n return 0LL;\n if ( v4 == 1 )\n return 1LL;\n v3 = a1[v4 - 2];\n return ((*__ctype_b_loc())[v3] & 0x400) == 0;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\ncmp [rbp+var_4], 0\njnz short loc_11B8\nmov eax, 0\njmp locret_124C\nloc_11B8:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_6], al\ncall ___ctype_b_loc\nmov rax, [rax]\nmovzx edx, [rbp+var_6]\nmovzx edx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 400h\ntest eax, eax\njnz short loc_11F9\nmov eax, 0\njmp short locret_124C\nloc_11F9:\ncmp [rbp+var_4], 1\njnz short loc_1206\nmov eax, 1\njmp short locret_124C\nloc_1206:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, [rax-2]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_5], al\ncall ___ctype_b_loc\nmov rax, [rax]\nmovzx edx, [rbp+var_5]\nmovzx edx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 400h\ntest eax, eax\njz short loc_1247\nmov eax, 0\njmp short locret_124C\nloc_1247:\nmov eax, 1\nlocret_124C:\nleave\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1189(const char *a1)\n{\n unsigned __int8 v2; // [rsp+1Ah] [rbp-6h]\n unsigned __int8 v3; // [rsp+1Bh] [rbp-5h]\n int v4; // [rsp+1Ch] [rbp-4h]\n\n v4 = strlen(a1);\n if ( !v4 )\n return 0LL;\n v2 = a1[v4 - 1];\n if ( ((*__ctype_b_loc())[v2] & 0x400) == 0 )\n return 0LL;\n if ( v4 == 1 )\n return 1LL;\n v3 = a1[v4 - 2];\n return ((*__ctype_b_loc())[v3] & 0x400) == 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1189(const char *a1) {\n unsigned char v2;\n unsigned char v3;\n int v4;\n v4 = strlen(a1);\n if (!v4) return 0LL;\n v2 = a1[v4 - 1];\n if (((*__ctype_b_loc())[v2] & 1024) == 0) return 0LL;\n if (v4 == 1) return 1LL;\n v3 = a1[v4 - 2];\n return ((*__ctype_b_loc())[v3] & 1024) == 0;\n}", + "ida_pseudo_norm": "uint8_t func0(const char *a1) {\n unsigned char v2;\n unsigned char v3;\n int v4;\n v4 = strlen(a1);\n if (!v4) return 0LL;\n v2 = a1[v4 - 1];\n if (((*__ctype_b_loc())[v2] & 1024) == 0) return 0LL;\n if (v4 == 1) return 1LL;\n v3 = a1[v4 - 2];\n return ((*__ctype_b_loc())[v3] & 1024) == 0;\n}" + }, + { + "index": "HumanEval-C-134", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int func0(const char *txt) {\n int len = strlen(txt);\n if (len == 0) return 0;\n char last_char = txt[len - 1];\n if (!isalpha((unsigned char)last_char)) return 0;\n if (len == 1) return 1;\n char second_last_char = txt[len - 2];\n if (isalpha((unsigned char)second_last_char)) return 0;\n return 1;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"apple\") == 0);\n assert(func0(\"apple pi e\") == 1);\n assert(func0(\"eeeee\") == 0);\n assert(func0(\"A\") == 1);\n assert(func0(\"Pumpkin pie \") == 0);\n assert(func0(\"Pumpkin pie 1\") == 0);\n assert(func0(\"\") == 0);\n assert(func0(\"eeeee e \") == 0);\n assert(func0(\"apple pie\") == 0);\n assert(func0(\"apple pi e \") == 0);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r13, rdi\ncall _strlen\nmov ebp, eax\ntest eax, eax\njz short loc_11D9\nmovsxd r14, eax\nmovzx r12d, byte ptr [r13+r14-1]\ncall ___ctype_b_loc\nmov rax, [rax]\nmovzx r12d, r12b\ntest byte ptr [rax+r12*2+1], 4\njz short loc_11E4\ncmp ebp, 1\njz short loc_11D9\nmovzx edx, byte ptr [r13+r14-2]\nmovzx ebp, word ptr [rax+rdx*2]\nshr bp, 0Ah\nxor ebp, 1\nand ebp, 1\nloc_11D9:\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_11E4:\nmov ebp, 0\njmp short loc_11D9", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n unsigned int v1; // eax\n unsigned int v2; // ebp\n __int64 v3; // r14\n unsigned __int8 v4; // r12\n const unsigned __int16 *v5; // rax\n\n v1 = strlen(a1);\n v2 = v1;\n if ( v1 )\n {\n v3 = (int)v1;\n v4 = a1[v1 - 1];\n v5 = *__ctype_b_loc();\n if ( (v5[v4] & 0x400) != 0 )\n {\n if ( v2 != 1 )\n return ((v5[(unsigned __int8)a1[v3 - 2]] >> 10) ^ 1) & 1;\n }\n else\n {\n return 0;\n }\n }\n return v2;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r13, rdi\ncall _strlen\nmov ebp, eax\ntest eax, eax\njz short loc_11D9\nmovsxd r14, eax\nmovzx r12d, byte ptr [r13+r14-1]\ncall ___ctype_b_loc\nmov rax, [rax]\nmovzx r12d, r12b\ntest byte ptr [rax+r12*2+1], 4\njz short loc_11E4\ncmp ebp, 1\njz short loc_11D9\nmovzx edx, byte ptr [r13+r14-2]\nmovzx ebp, word ptr [rax+rdx*2]\nshr bp, 0Ah\nxor ebp, 1\nand ebp, 1\nloc_11D9:\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_11E4:\nmov ebp, 0\njmp short loc_11D9", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(const char *a1)\n{\n unsigned int v1; // eax\n unsigned int v2; // ebp\n __int64 v3; // r14\n unsigned __int8 v4; // r12\n const unsigned __int16 *v5; // rax\n\n v1 = strlen(a1);\n v2 = v1;\n if ( v1 )\n {\n v3 = (int)v1;\n v4 = a1[v1 - 1];\n v5 = *__ctype_b_loc();\n if ( (v5[v4] & 0x400) != 0 )\n {\n if ( v2 != 1 )\n return ((v5[(unsigned __int8)a1[v3 - 2]] >> 10) ^ 1) & 1;\n }\n else\n {\n return 0;\n }\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(const char *a1) {\n unsigned int v1;\n unsigned int v2;\n long long v3;\n unsigned char v4;\n const unsigned short *v5;\n v1 = strlen(a1);\n v2 = v1;\n if (v1) {\n v3 = (int)v1;\n v4 = a1[v1 - 1];\n v5 = *__ctype_b_loc();\n if ((v5[v4] & 1024) != 0) {\n if (v2 != 1) return ((v5[(unsigned char)a1[v3 - 2]] >> 10) ^ 1) & 1;\n } else {\n return 0;\n }\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n unsigned int v1;\n unsigned int v2;\n long long v3;\n unsigned char v4;\n const unsigned short *v5;\n v1 = strlen(a1);\n v2 = v1;\n if (v1) {\n v3 = (int)v1;\n v4 = a1[v1 - 1];\n v5 = *__ctype_b_loc();\n if ((v5[v4] & 1024) != 0) {\n if (v2 != 1) return ((v5[(unsigned char)a1[v3 - 2]] >> 10) ^ 1) & 1;\n } else {\n return 0;\n }\n }\n return v2;\n}" + }, + { + "index": "HumanEval-C-134", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int func0(const char *txt) {\n int len = strlen(txt);\n if (len == 0) return 0;\n char last_char = txt[len - 1];\n if (!isalpha((unsigned char)last_char)) return 0;\n if (len == 1) return 1;\n char second_last_char = txt[len - 2];\n if (isalpha((unsigned char)second_last_char)) return 0;\n return 1;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"apple\") == 0);\n assert(func0(\"apple pi e\") == 1);\n assert(func0(\"eeeee\") == 0);\n assert(func0(\"A\") == 1);\n assert(func0(\"Pumpkin pie \") == 0);\n assert(func0(\"Pumpkin pie 1\") == 0);\n assert(func0(\"\") == 0);\n assert(func0(\"eeeee e \") == 0);\n assert(func0(\"apple pie\") == 0);\n assert(func0(\"apple pi e \") == 0);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\ncall _strlen\nmov r12d, eax\ntest eax, eax\njz short loc_13F2\nmovsxd r14, eax\ncall ___ctype_b_loc\nmovzx r13d, byte ptr [rbp+r14-1]\nmov rax, [rax]\ntest byte ptr [rax+r13*2+1], 4\njz short loc_1400\ncmp r12d, 1\njz short loc_13F2\nmovzx edx, byte ptr [rbp+r14-2]\nmovzx r12d, word ptr [rax+rdx*2]\nshr r12w, 0Ah\nxor r12d, 1\nand r12d, 1\nloc_13F2:\npop rbx\nmov eax, r12d\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1400:\nxor r12d, r12d\npop rbx\npop rbp\nmov eax, r12d\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n unsigned int v1; // eax\n unsigned int v2; // r12d\n __int64 v3; // r14\n const unsigned __int16 *v4; // rax\n\n v1 = strlen(a1);\n v2 = v1;\n if ( !v1 )\n return v2;\n v3 = (int)v1;\n v4 = *__ctype_b_loc();\n if ( (v4[(unsigned __int8)a1[v3 - 1]] & 0x400) != 0 )\n {\n if ( v2 != 1 )\n return ((v4[(unsigned __int8)a1[v3 - 2]] >> 10) ^ 1) & 1;\n return v2;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_13A0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\ncall _strlen\nmov r12d, eax\ntest eax, eax\njz short loc_13F2\nmovsxd r14, eax\ncall ___ctype_b_loc\nmovzx r13d, byte ptr [rbp+r14-1]\nmov rax, [rax]\ntest byte ptr [rax+r13*2+1], 4\njz short loc_1400\ncmp r12d, 1\njz short loc_13F2\nmovzx edx, byte ptr [rbp+r14-2]\nmovzx r12d, word ptr [rax+rdx*2]\nshr r12w, 0Ah\nxor r12d, 1\nand r12d, 1\nloc_13F2:\npop rbx\nmov eax, r12d\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1400:\nxor r12d, r12d\npop rbx\npop rbp\nmov eax, r12d\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_13A0(const char *a1)\n{\n unsigned int v1; // eax\n unsigned int v2; // r12d\n __int64 v3; // r14\n const unsigned __int16 *v4; // rax\n\n v1 = strlen(a1);\n v2 = v1;\n if ( !v1 )\n return v2;\n v3 = (int)v1;\n v4 = *__ctype_b_loc();\n if ( (v4[(unsigned __int8)a1[v3 - 1]] & 0x400) != 0 )\n {\n if ( v2 != 1 )\n return ((v4[(unsigned __int8)a1[v3 - 2]] >> 10) ^ 1) & 1;\n return v2;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_13A0(const char *a1) {\n unsigned int v1;\n unsigned int v2;\n long long v3;\n const unsigned short *v4;\n v1 = strlen(a1);\n v2 = v1;\n if (!v1) return v2;\n v3 = (int)v1;\n v4 = *__ctype_b_loc();\n if ((v4[(unsigned char)a1[v3 - 1]] & 1024) != 0) {\n if (v2 != 1) return ((v4[(unsigned char)a1[v3 - 2]] >> 10) ^ 1) & 1;\n return v2;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n unsigned int v1;\n unsigned int v2;\n long long v3;\n const unsigned short *v4;\n v1 = strlen(a1);\n v2 = v1;\n if (!v1) return v2;\n v3 = (int)v1;\n v4 = *__ctype_b_loc();\n if ((v4[(unsigned char)a1[v3 - 1]] & 1024) != 0) {\n if (v2 != 1) return ((v4[(unsigned char)a1[v3 - 2]] >> 10) ^ 1) & 1;\n return v2;\n }\n return 0LL;\n}" + }, + { + "index": "HumanEval-C-134", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int func0(const char *txt) {\n int len = strlen(txt);\n if (len == 0) return 0;\n char last_char = txt[len - 1];\n if (!isalpha((unsigned char)last_char)) return 0;\n if (len == 1) return 1;\n char second_last_char = txt[len - 2];\n if (isalpha((unsigned char)second_last_char)) return 0;\n return 1;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"apple\") == 0);\n assert(func0(\"apple pi e\") == 1);\n assert(func0(\"eeeee\") == 0);\n assert(func0(\"A\") == 1);\n assert(func0(\"Pumpkin pie \") == 0);\n assert(func0(\"Pumpkin pie 1\") == 0);\n assert(func0(\"\") == 0);\n assert(func0(\"eeeee e \") == 0);\n assert(func0(\"apple pie\") == 0);\n assert(func0(\"apple pi e \") == 0);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\ncall _strlen\nmov r12d, eax\ntest eax, eax\njz short loc_13F2\nmovsxd r14, eax\ncall ___ctype_b_loc\nmovzx r13d, byte ptr [rbp+r14-1]\nmov rax, [rax]\ntest byte ptr [rax+r13*2+1], 4\njz short loc_1400\ncmp r12d, 1\njz short loc_13F2\nmovzx edx, byte ptr [rbp+r14-2]\nmovzx r12d, word ptr [rax+rdx*2]\nshr r12w, 0Ah\nxor r12d, 1\nand r12d, 1\nloc_13F2:\npop rbx\nmov eax, r12d\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1400:\nxor r12d, r12d\npop rbx\npop rbp\nmov eax, r12d\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n unsigned int v1; // eax\n unsigned int v2; // r12d\n __int64 v3; // r14\n const unsigned __int16 *v4; // rax\n\n v1 = strlen(a1);\n v2 = v1;\n if ( !v1 )\n return v2;\n v3 = (int)v1;\n v4 = *__ctype_b_loc();\n if ( (v4[(unsigned __int8)a1[v3 - 1]] & 0x400) != 0 )\n {\n if ( v2 != 1 )\n return ((v4[(unsigned __int8)a1[v3 - 2]] >> 10) ^ 1) & 1;\n return v2;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_13A0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\ncall _strlen\nmov r12d, eax\ntest eax, eax\njz short loc_13F2\nmovsxd r14, eax\ncall ___ctype_b_loc\nmovzx r13d, byte ptr [rbp+r14-1]\nmov rax, [rax]\ntest byte ptr [rax+r13*2+1], 4\njz short loc_1400\ncmp r12d, 1\njz short loc_13F2\nmovzx edx, byte ptr [rbp+r14-2]\nmovzx r12d, word ptr [rax+rdx*2]\nshr r12w, 0Ah\nxor r12d, 1\nand r12d, 1\nloc_13F2:\npop rbx\nmov eax, r12d\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1400:\nxor r12d, r12d\npop rbx\npop rbp\nmov eax, r12d\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_13A0(const char *a1)\n{\n unsigned int v1; // eax\n unsigned int v2; // r12d\n __int64 v3; // r14\n const unsigned __int16 *v4; // rax\n\n v1 = strlen(a1);\n v2 = v1;\n if ( !v1 )\n return v2;\n v3 = (int)v1;\n v4 = *__ctype_b_loc();\n if ( (v4[(unsigned __int8)a1[v3 - 1]] & 0x400) != 0 )\n {\n if ( v2 != 1 )\n return ((v4[(unsigned __int8)a1[v3 - 2]] >> 10) ^ 1) & 1;\n return v2;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_13A0(const char *a1) {\n unsigned int v1;\n unsigned int v2;\n long long v3;\n const unsigned short *v4;\n v1 = strlen(a1);\n v2 = v1;\n if (!v1) return v2;\n v3 = (int)v1;\n v4 = *__ctype_b_loc();\n if ((v4[(unsigned char)a1[v3 - 1]] & 1024) != 0) {\n if (v2 != 1) return ((v4[(unsigned char)a1[v3 - 2]] >> 10) ^ 1) & 1;\n return v2;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n unsigned int v1;\n unsigned int v2;\n long long v3;\n const unsigned short *v4;\n v1 = strlen(a1);\n v2 = v1;\n if (!v1) return v2;\n v3 = (int)v1;\n v4 = *__ctype_b_loc();\n if ((v4[(unsigned char)a1[v3 - 1]] & 1024) != 0) {\n if (v2 != 1) return ((v4[(unsigned char)a1[v3 - 2]] >> 10) ^ 1) & 1;\n return v2;\n }\n return 0LL;\n}" + }, + { + "index": "HumanEval-C-135", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int *arr, int size) {\n int max = -1;\n for (int i = 1; i < size; ++i) {\n if (arr[i] < arr[i - 1]) max = i;\n }\n return max;\n}", + "test": "#include \n\nint main() {\n int arr1[] = {1, 2, 4, 3, 5};\n assert(func0(arr1, 5) == 3);\n\n int arr2[] = {1, 2, 4, 5};\n assert(func0(arr2, 4) == -1);\n\n int arr3[] = {1, 4, 2, 5, 6, 7, 8, 9, 10};\n assert(func0(arr3, 9) == 2);\n\n int arr4[] = {4, 8, 5, 7, 3};\n assert(func0(arr4, 5) == 4);\n\n assert(func0(NULL, 0) == -1);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0FFFFFFFFh\nmov [rbp+var_4], 1\njmp short loc_11C2\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nshl rax, 2\nlea rcx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njge short loc_11BE\nmov eax, [rbp+var_4]\nmov [rbp+var_8], eax\nloc_11BE:\nadd [rbp+var_4], 1\nloc_11C2:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = -1;\n for ( i = 1; i < a2; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) < *(_DWORD *)(4LL * i - 4 + a1) )\n v3 = i;\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0FFFFFFFFh\nmov [rbp+var_4], 1\njmp short loc_11C2\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nshl rax, 2\nlea rcx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njge short loc_11BE\nmov eax, [rbp+var_4]\nmov [rbp+var_8], eax\nloc_11BE:\nadd [rbp+var_4], 1\nloc_11C2:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = -1;\n for ( i = 1; i < a2; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) < *(_DWORD *)(4LL * i - 4 + a1) )\n v3 = i;\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = -1;\n for (i = 1; i < a2; ++i) {\n if (*(uint32_t *)(4LL * i + a1) < *(uint32_t *)(4LL * i - 4 + a1)) v3 = i;\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = -1;\n for (i = 1; i < a2; ++i) {\n if (*(uint32_t *)(4LL * i + a1) < *(uint32_t *)(4LL * i - 4 + a1)) v3 = i;\n }\n return v3;\n}" + }, + { + "index": "HumanEval-C-135", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int *arr, int size) {\n int max = -1;\n for (int i = 1; i < size; ++i) {\n if (arr[i] < arr[i - 1]) max = i;\n }\n return max;\n}", + "test": "#include \n\nint main() {\n int arr1[] = {1, 2, 4, 3, 5};\n assert(func0(arr1, 5) == 3);\n\n int arr2[] = {1, 2, 4, 5};\n assert(func0(arr2, 4) == -1);\n\n int arr3[] = {1, 4, 2, 5, 6, 7, 8, 9, 10};\n assert(func0(arr3, 9) == 2);\n\n int arr4[] = {4, 8, 5, 7, 3};\n assert(func0(arr4, 5) == 4);\n\n assert(func0(NULL, 0) == -1);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ncmp esi, 1\njle short loc_1194\nmov esi, esi\nmov eax, 1\nmov edx, 0FFFFFFFFh\nloc_117E:\nmov ecx, [rdi+rax*4-4]\ncmp [rdi+rax*4], ecx\ncmovl edx, eax\nadd rax, 1\ncmp rax, rsi\njnz short loc_117E\nloc_1191:\nmov eax, edx\nretn\nloc_1194:\nmov edx, 0FFFFFFFFh\njmp short loc_1191", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // rax\n unsigned int v3; // edx\n\n if ( a2 <= 1 )\n {\n return (unsigned int)-1;\n }\n else\n {\n v2 = 1LL;\n v3 = -1;\n do\n {\n if ( *(_DWORD *)(a1 + 4 * v2) < *(_DWORD *)(a1 + 4 * v2 - 4) )\n v3 = v2;\n ++v2;\n }\n while ( v2 != a2 );\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ncmp esi, 1\njle short loc_1194\nmov esi, esi\nmov eax, 1\nmov edx, 0FFFFFFFFh\nloc_117E:\nmov ecx, [rdi+rax*4-4]\ncmp [rdi+rax*4], ecx\ncmovl edx, eax\nadd rax, 1\ncmp rax, rsi\njnz short loc_117E\nloc_1191:\nmov eax, edx\nretn\nloc_1194:\nmov edx, 0FFFFFFFFh\njmp short loc_1191", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n __int64 v2; // rax\n unsigned int v3; // edx\n\n if ( a2 <= 1 )\n {\n return (unsigned int)-1;\n }\n else\n {\n v2 = 1LL;\n v3 = -1;\n do\n {\n if ( *(_DWORD *)(a1 + 4 * v2) < *(_DWORD *)(a1 + 4 * v2 - 4) )\n v3 = v2;\n ++v2;\n }\n while ( v2 != a2 );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n if (a2 <= 1) {\n return (unsigned int)-1;\n } else {\n v2 = 1LL;\n v3 = -1;\n do {\n if (*(uint32_t *)(a1 + 4 * v2) < *(uint32_t *)(a1 + 4 * v2 - 4)) v3 = v2;\n ++v2;\n } while (v2 != a2);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n if (a2 <= 1) {\n return (unsigned int)-1;\n } else {\n v2 = 1LL;\n v3 = -1;\n do {\n if (*(uint32_t *)(a1 + 4 * v2) < *(uint32_t *)(a1 + 4 * v2 - 4)) v3 = v2;\n ++v2;\n } while (v2 != a2);\n }\n return v3;\n}" + }, + { + "index": "HumanEval-C-135", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int *arr, int size) {\n int max = -1;\n for (int i = 1; i < size; ++i) {\n if (arr[i] < arr[i - 1]) max = i;\n }\n return max;\n}", + "test": "#include \n\nint main() {\n int arr1[] = {1, 2, 4, 3, 5};\n assert(func0(arr1, 5) == 3);\n\n int arr2[] = {1, 2, 4, 5};\n assert(func0(arr2, 4) == -1);\n\n int arr3[] = {1, 4, 2, 5, 6, 7, 8, 9, 10};\n assert(func0(arr3, 9) == 2);\n\n int arr4[] = {4, 8, 5, 7, 3};\n assert(func0(arr4, 5) == 4);\n\n assert(func0(NULL, 0) == -1);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ncmp esi, 1\njle short loc_1350\nmov edx, [rdi]\nmov esi, esi\nmov eax, 1\nmov ecx, 0FFFFFFFFh\nnop word ptr [rax+rax+00000000h]\nloc_1330:\nmov r8d, edx\nmov edx, [rdi+rax*4]\ncmp r8d, edx\ncmovg ecx, eax\nadd rax, 1\ncmp rax, rsi\njnz short loc_1330\nmov eax, ecx\nretn\nloc_1350:\nmov ecx, 0FFFFFFFFh\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int v2; // edx\n __int64 v3; // rax\n unsigned int v4; // ecx\n int v5; // r8d\n\n if ( a2 <= 1 )\n return 0xFFFFFFFFLL;\n v2 = *a1;\n v3 = 1LL;\n v4 = -1;\n do\n {\n v5 = v2;\n v2 = a1[v3];\n if ( v5 > v2 )\n v4 = v3;\n ++v3;\n }\n while ( v3 != a2 );\n return v4;\n}", + "ida_strip_asm": "sub_1310:\nendbr64\ncmp esi, 1\njle short loc_1350\nmov edx, [rdi]\nmov esi, esi\nmov eax, 1\nmov ecx, 0FFFFFFFFh\nnop word ptr [rax+rax+00000000h]\nloc_1330:\nmov r8d, edx\nmov edx, [rdi+rax*4]\ncmp r8d, edx\ncmovg ecx, eax\nadd rax, 1\ncmp rax, rsi\njnz short loc_1330\nmov eax, ecx\nretn\nloc_1350:\nmov ecx, 0FFFFFFFFh\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1310(int *a1, int a2)\n{\n int v2; // edx\n __int64 v3; // rax\n unsigned int v4; // ecx\n int v5; // r8d\n\n if ( a2 <= 1 )\n return 0xFFFFFFFFLL;\n v2 = *a1;\n v3 = 1LL;\n v4 = -1;\n do\n {\n v5 = v2;\n v2 = a1[v3];\n if ( v5 > v2 )\n v4 = v3;\n ++v3;\n }\n while ( v3 != a2 );\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1310(int *a1, int a2) {\n int v2;\n long long v3;\n unsigned int v4;\n int v5;\n if (a2 <= 1) return 4294967295LL;\n v2 = *a1;\n v3 = 1LL;\n v4 = -1;\n do {\n v5 = v2;\n v2 = a1[v3];\n if (v5 > v2) v4 = v3;\n ++v3;\n } while (v3 != a2);\n return v4;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int v2;\n long long v3;\n unsigned int v4;\n int v5;\n if (a2 <= 1) return 4294967295LL;\n v2 = *a1;\n v3 = 1LL;\n v4 = -1;\n do {\n v5 = v2;\n v2 = a1[v3];\n if (v5 > v2) v4 = v3;\n ++v3;\n } while (v3 != a2);\n return v4;\n}" + }, + { + "index": "HumanEval-C-136", + "func_name": "func0", + "func_dep": "#include \n", + "func": "void func0(const int *lst, int size, int result[2]) {\n int maxneg = 0;\n int minpos = 0;\n for (int i = 0; i < size; i++) {\n if (lst[i] < 0 && (maxneg == 0 || lst[i] > maxneg)) maxneg = lst[i];\n if (lst[i] > 0 && (minpos == 0 || lst[i] < minpos)) minpos = lst[i];\n }\n result[0] = maxneg;\n result[1] = minpos;\n}", + "test": "#include \n\nint issame(const int a[2], const int b[2]) {\n return a[0] == b[0] && a[1] == b[1];\n}\n\nint main() {\n int result[2];\n \n func0((const int[]){2, 4, 1, 3, 5, 7}, 6, result);\n assert(issame(result, (const int[]){0, 1}));\n\n func0((const int[]){2, 4, 1, 3, 5, 7, 0}, 7, result);\n assert(issame(result, (const int[]){0, 1}));\n\n func0((const int[]){1, 3, 2, 4, 5, 6, -2}, 7, result);\n assert(issame(result, (const int[]){-2, 1}));\n\n func0((const int[]){4, 5, 3, 6, 2, 7, -7}, 7, result);\n assert(issame(result, (const int[]){-7, 2}));\n\n func0((const int[]){7, 3, 8, 4, 9, 2, 5, -9}, 8, result);\n assert(issame(result, (const int[]){-9, 2}));\n\n func0((const int[]){}, 0, result);\n assert(issame(result, (const int[]){0, 0}));\n\n func0((const int[]){0}, 1, result);\n assert(issame(result, (const int[]){0, 0}));\n\n func0((const int[]){-1, -3, -5, -6}, 4, result);\n assert(issame(result, (const int[]){-1, 0}));\n\n func0((const int[]){-1, -3, -5, -6, 0}, 5, result);\n assert(issame(result, (const int[]){-1, 0}));\n\n func0((const int[]){-6, -4, -4, -3, 1}, 5, result);\n assert(issame(result, (const int[]){-3, 1}));\n\n func0((const int[]){-6, -4, -4, -3, -100, 1}, 6, result);\n assert(issame(result, (const int[]){-3, 1}));\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp loc_1242\nloc_1196:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njns short loc_11EA\ncmp [rbp+var_C], 0\njz short loc_11D1\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_C], eax\njge short loc_11EA\nloc_11D1:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nloc_11EA:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njle short loc_123E\ncmp [rbp+var_8], 0\njz short loc_1225\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_8], eax\njle short loc_123E\nloc_1225:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_8], eax\nloc_123E:\nadd [rbp+var_4], 1\nloc_1242:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl loc_1196\nmov rax, [rbp+var_28]\nmov edx, [rbp+var_C]\nmov [rax], edx\nmov rax, [rbp+var_28]\nlea rdx, [rax+4]\nmov eax, [rbp+var_8]\nmov [rdx], eax\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, _DWORD *a3)\n{\n __int64 result; // rax\n int v4; // [rsp+1Ch] [rbp-Ch]\n unsigned int v5; // [rsp+20h] [rbp-8h]\n int i; // [rsp+24h] [rbp-4h]\n\n v4 = 0;\n v5 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(int *)(4LL * i + a1) < 0 && (!v4 || v4 < *(_DWORD *)(4LL * i + a1)) )\n v4 = *(_DWORD *)(4LL * i + a1);\n if ( *(int *)(4LL * i + a1) > 0 && (!v5 || (signed int)v5 > *(_DWORD *)(4LL * i + a1)) )\n v5 = *(_DWORD *)(4LL * i + a1);\n }\n *a3 = v4;\n result = v5;\n a3[1] = v5;\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp loc_1242\nloc_1196:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njns short loc_11EA\ncmp [rbp+var_C], 0\njz short loc_11D1\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_C], eax\njge short loc_11EA\nloc_11D1:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nloc_11EA:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njle short loc_123E\ncmp [rbp+var_8], 0\njz short loc_1225\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_8], eax\njle short loc_123E\nloc_1225:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_8], eax\nloc_123E:\nadd [rbp+var_4], 1\nloc_1242:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl loc_1196\nmov rax, [rbp+var_28]\nmov edx, [rbp+var_C]\nmov [rax], edx\nmov rax, [rbp+var_28]\nlea rdx, [rax+4]\nmov eax, [rbp+var_8]\nmov [rdx], eax\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, _DWORD *a3)\n{\n __int64 result; // rax\n int v4; // [rsp+1Ch] [rbp-Ch]\n unsigned int v5; // [rsp+20h] [rbp-8h]\n int i; // [rsp+24h] [rbp-4h]\n\n v4 = 0;\n v5 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(int *)(4LL * i + a1) < 0 && (!v4 || v4 < *(_DWORD *)(4LL * i + a1)) )\n v4 = *(_DWORD *)(4LL * i + a1);\n if ( *(int *)(4LL * i + a1) > 0 && (!v5 || (signed int)v5 > *(_DWORD *)(4LL * i + a1)) )\n v5 = *(_DWORD *)(4LL * i + a1);\n }\n *a3 = v4;\n result = v5;\n a3[1] = v5;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, uint32_t *a3) {\n long long result;\n int v4;\n unsigned int v5;\n int i;\n v4 = 0;\n v5 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(int *)(4LL * i + a1) < 0 && (!v4 || v4 < *(uint32_t *)(4LL * i + a1)))\n v4 = *(uint32_t *)(4LL * i + a1);\n if (*(int *)(4LL * i + a1) > 0 &&\n (!v5 || (signed int)v5 > *(uint32_t *)(4LL * i + a1)))\n v5 = *(uint32_t *)(4LL * i + a1);\n }\n *a3 = v4;\n result = v5;\n a3[1] = v5;\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, uint32_t *a3) {\n long long result;\n int v4;\n unsigned int v5;\n int i;\n v4 = 0;\n v5 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(int *)(4LL * i + a1) < 0 && (!v4 || v4 < *(uint32_t *)(4LL * i + a1)))\n v4 = *(uint32_t *)(4LL * i + a1);\n if (*(int *)(4LL * i + a1) > 0 &&\n (!v5 || (signed int)v5 > *(uint32_t *)(4LL * i + a1)))\n v5 = *(uint32_t *)(4LL * i + a1);\n }\n *a3 = v4;\n result = v5;\n a3[1] = v5;\n return result;\n}" + }, + { + "index": "HumanEval-C-136", + "func_name": "func0", + "func_dep": "#include \n", + "func": "void func0(const int *lst, int size, int result[2]) {\n int maxneg = 0;\n int minpos = 0;\n for (int i = 0; i < size; i++) {\n if (lst[i] < 0 && (maxneg == 0 || lst[i] > maxneg)) maxneg = lst[i];\n if (lst[i] > 0 && (minpos == 0 || lst[i] < minpos)) minpos = lst[i];\n }\n result[0] = maxneg;\n result[1] = minpos;\n}", + "test": "#include \n\nint issame(const int a[2], const int b[2]) {\n return a[0] == b[0] && a[1] == b[1];\n}\n\nint main() {\n int result[2];\n \n func0((const int[]){2, 4, 1, 3, 5, 7}, 6, result);\n assert(issame(result, (const int[]){0, 1}));\n\n func0((const int[]){2, 4, 1, 3, 5, 7, 0}, 7, result);\n assert(issame(result, (const int[]){0, 1}));\n\n func0((const int[]){1, 3, 2, 4, 5, 6, -2}, 7, result);\n assert(issame(result, (const int[]){-2, 1}));\n\n func0((const int[]){4, 5, 3, 6, 2, 7, -7}, 7, result);\n assert(issame(result, (const int[]){-7, 2}));\n\n func0((const int[]){7, 3, 8, 4, 9, 2, 5, -9}, 8, result);\n assert(issame(result, (const int[]){-9, 2}));\n\n func0((const int[]){}, 0, result);\n assert(issame(result, (const int[]){0, 0}));\n\n func0((const int[]){0}, 1, result);\n assert(issame(result, (const int[]){0, 0}));\n\n func0((const int[]){-1, -3, -5, -6}, 4, result);\n assert(issame(result, (const int[]){-1, 0}));\n\n func0((const int[]){-1, -3, -5, -6, 0}, 5, result);\n assert(issame(result, (const int[]){-1, 0}));\n\n func0((const int[]){-6, -4, -4, -3, 1}, 5, result);\n assert(issame(result, (const int[]){-3, 1}));\n\n func0((const int[]){-6, -4, -4, -3, -100, 1}, 6, result);\n assert(issame(result, (const int[]){-3, 1}));\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11BE\nmov rcx, rdi\nmovsxd rsi, esi\nlea r9, [rdi+rsi*4]\nmov esi, 0\nmov edi, 0\njmp short loc_11B4\nloc_1187:\ncmp edi, eax\nmov r8d, eax\ncmovge r8d, edi\ntest edi, edi\ncmovnz eax, r8d\nmov edi, eax\njmp short loc_11AB\nloc_119A:\ncmp esi, eax\nmov r8d, eax\ncmovle r8d, esi\ntest esi, esi\ncmovnz eax, r8d\nmov esi, eax\nloc_11AB:\nadd rcx, 4\ncmp rcx, r9\njz short loc_11C8\nloc_11B4:\nmov eax, [rcx]\ntest eax, eax\njs short loc_1187\njg short loc_119A\njmp short loc_11AB\nloc_11BE:\nmov esi, 0\nmov edi, 0\nloc_11C8:\nmov [rdx], edi\nmov [rdx+4], esi\nretn", + "ida_pseudo": "void __fastcall func0(int *a1, int a2, int *a3)\n{\n int *v3; // rcx\n int *v4; // r9\n int v5; // esi\n int v6; // edi\n int v7; // r8d\n int v8; // eax\n int v9; // r8d\n\n if ( a2 <= 0 )\n {\n v5 = 0;\n v6 = 0;\n }\n else\n {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n v6 = 0;\n do\n {\n v8 = *v3;\n if ( *v3 < 0 )\n {\n v7 = *v3;\n if ( v6 >= v8 )\n v7 = v6;\n if ( v6 )\n v8 = v7;\n v6 = v8;\n }\n else if ( v8 > 0 )\n {\n v9 = *v3;\n if ( v5 <= v8 )\n v9 = v5;\n if ( v5 )\n v8 = v9;\n v5 = v8;\n }\n ++v3;\n }\n while ( v3 != v4 );\n }\n *a3 = v6;\n a3[1] = v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11BE\nmov rcx, rdi\nmovsxd rsi, esi\nlea r9, [rdi+rsi*4]\nmov esi, 0\nmov edi, 0\njmp short loc_11B4\nloc_1187:\ncmp edi, eax\nmov r8d, eax\ncmovge r8d, edi\ntest edi, edi\ncmovnz eax, r8d\nmov edi, eax\njmp short loc_11AB\nloc_119A:\ncmp esi, eax\nmov r8d, eax\ncmovle r8d, esi\ntest esi, esi\ncmovnz eax, r8d\nmov esi, eax\nloc_11AB:\nadd rcx, 4\ncmp rcx, r9\njz short loc_11C8\nloc_11B4:\nmov eax, [rcx]\ntest eax, eax\njs short loc_1187\njg short loc_119A\njmp short loc_11AB\nloc_11BE:\nmov esi, 0\nmov edi, 0\nloc_11C8:\nmov [rdx], edi\nmov [rdx+4], esi\nretn", + "ida_strip_pseudo": "void __fastcall sub_1169(int *a1, int a2, int *a3)\n{\n int *v3; // rcx\n int *v4; // r9\n int v5; // esi\n int v6; // edi\n int v7; // r8d\n int v8; // eax\n int v9; // r8d\n\n if ( a2 <= 0 )\n {\n v5 = 0;\n v6 = 0;\n }\n else\n {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n v6 = 0;\n do\n {\n v8 = *v3;\n if ( *v3 < 0 )\n {\n v7 = *v3;\n if ( v6 >= v8 )\n v7 = v6;\n if ( v6 )\n v8 = v7;\n v6 = v8;\n }\n else if ( v8 > 0 )\n {\n v9 = *v3;\n if ( v5 <= v8 )\n v9 = v5;\n if ( v5 )\n v8 = v9;\n v5 = v8;\n }\n ++v3;\n }\n while ( v3 != v4 );\n }\n *a3 = v6;\n a3[1] = v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1169(int *a1, int a2, int *a3) {\n int *v3;\n int *v4;\n int v5;\n int v6;\n int v7;\n int v8;\n int v9;\n if (a2 <= 0) {\n v5 = 0;\n v6 = 0;\n } else {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n v6 = 0;\n do {\n v8 = *v3;\n if (*v3 < 0) {\n v7 = *v3;\n if (v6 >= v8) v7 = v6;\n if (v6) v8 = v7;\n v6 = v8;\n } else if (v8 > 0) {\n v9 = *v3;\n if (v5 <= v8) v9 = v5;\n if (v5) v8 = v9;\n v5 = v8;\n }\n ++v3;\n } while (v3 != v4);\n }\n *a3 = v6;\n a3[1] = v5;\n}", + "ida_pseudo_norm": "void func0(int *a1, int a2, int *a3) {\n int *v3;\n int *v4;\n int v5;\n int v6;\n int v7;\n int v8;\n int v9;\n if (a2 <= 0) {\n v5 = 0;\n v6 = 0;\n } else {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n v6 = 0;\n do {\n v8 = *v3;\n if (*v3 < 0) {\n v7 = *v3;\n if (v6 >= v8) v7 = v6;\n if (v6) v8 = v7;\n v6 = v8;\n } else if (v8 > 0) {\n v9 = *v3;\n if (v5 <= v8) v9 = v5;\n if (v5) v8 = v9;\n v5 = v8;\n }\n ++v3;\n } while (v3 != v4);\n }\n *a3 = v6;\n a3[1] = v5;\n}" + }, + { + "index": "HumanEval-C-136", + "func_name": "func0", + "func_dep": "#include \n", + "func": "void func0(const int *lst, int size, int result[2]) {\n int maxneg = 0;\n int minpos = 0;\n for (int i = 0; i < size; i++) {\n if (lst[i] < 0 && (maxneg == 0 || lst[i] > maxneg)) maxneg = lst[i];\n if (lst[i] > 0 && (minpos == 0 || lst[i] < minpos)) minpos = lst[i];\n }\n result[0] = maxneg;\n result[1] = minpos;\n}", + "test": "#include \n\nint issame(const int a[2], const int b[2]) {\n return a[0] == b[0] && a[1] == b[1];\n}\n\nint main() {\n int result[2];\n \n func0((const int[]){2, 4, 1, 3, 5, 7}, 6, result);\n assert(issame(result, (const int[]){0, 1}));\n\n func0((const int[]){2, 4, 1, 3, 5, 7, 0}, 7, result);\n assert(issame(result, (const int[]){0, 1}));\n\n func0((const int[]){1, 3, 2, 4, 5, 6, -2}, 7, result);\n assert(issame(result, (const int[]){-2, 1}));\n\n func0((const int[]){4, 5, 3, 6, 2, 7, -7}, 7, result);\n assert(issame(result, (const int[]){-7, 2}));\n\n func0((const int[]){7, 3, 8, 4, 9, 2, 5, -9}, 8, result);\n assert(issame(result, (const int[]){-9, 2}));\n\n func0((const int[]){}, 0, result);\n assert(issame(result, (const int[]){0, 0}));\n\n func0((const int[]){0}, 1, result);\n assert(issame(result, (const int[]){0, 0}));\n\n func0((const int[]){-1, -3, -5, -6}, 4, result);\n assert(issame(result, (const int[]){-1, 0}));\n\n func0((const int[]){-1, -3, -5, -6, 0}, 5, result);\n assert(issame(result, (const int[]){-1, 0}));\n\n func0((const int[]){-6, -4, -4, -3, 1}, 5, result);\n assert(issame(result, (const int[]){-3, 1}));\n\n func0((const int[]){-6, -4, -4, -3, -100, 1}, 6, result);\n assert(issame(result, (const int[]){-3, 1}));\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_15A0\nmovsxd rsi, esi\nxor ecx, ecx\nlea r9, [rdi+rsi*4]\nxor esi, esi\njmp short loc_1574\nloc_1558:\njz short loc_156B\ncmp ecx, eax\nmov r8d, eax\ncmovle r8d, ecx\ntest ecx, ecx\ncmovnz eax, r8d\nmov ecx, eax\nloc_156B:\nadd rdi, 4\ncmp rdi, r9\njz short loc_1594\nloc_1574:\nmov eax, [rdi]\ntest eax, eax\njns short loc_1558\ncmp esi, eax\nmov r8d, eax\ncmovge r8d, esi\ntest esi, esi\ncmovnz eax, r8d\nadd rdi, 4\nmov esi, eax\ncmp rdi, r9\njnz short loc_1574\nloc_1594:\nmov [rdx], esi\nmov [rdx+4], ecx\nretn\nloc_15A0:\nxor ecx, ecx\nxor esi, esi\nmov [rdx], esi\nmov [rdx+4], ecx\nretn", + "ida_pseudo": "void __fastcall func0(int *a1, int a2, int *a3)\n{\n int v3; // ecx\n int *v4; // r9\n int v5; // esi\n int v6; // r8d\n int v7; // eax\n int v8; // r8d\n\n if ( a2 <= 0 )\n {\n *a3 = 0;\n a3[1] = 0;\n }\n else\n {\n v3 = 0;\n v4 = &a1[a2];\n v5 = 0;\n do\n {\n while ( 1 )\n {\n v7 = *a1;\n if ( *a1 >= 0 )\n break;\n v8 = *a1;\n if ( v5 >= v7 )\n v8 = v5;\n if ( v5 )\n v7 = v8;\n ++a1;\n v5 = v7;\n if ( a1 == v4 )\n goto LABEL_16;\n }\n if ( v7 )\n {\n v6 = *a1;\n if ( v3 <= v7 )\n v6 = v3;\n if ( v3 )\n v7 = v6;\n v3 = v7;\n }\n ++a1;\n }\n while ( a1 != v4 );\nLABEL_16:\n *a3 = v5;\n a3[1] = v3;\n }\n}", + "ida_strip_asm": "sub_1540:\nendbr64\ntest esi, esi\njle short loc_15A0\nmovsxd rsi, esi\nxor ecx, ecx\nlea r9, [rdi+rsi*4]\nxor esi, esi\njmp short loc_1574\nloc_1558:\njz short loc_156B\ncmp ecx, eax\nmov r8d, eax\ncmovle r8d, ecx\ntest ecx, ecx\ncmovnz eax, r8d\nmov ecx, eax\nloc_156B:\nadd rdi, 4\ncmp rdi, r9\njz short loc_1594\nloc_1574:\nmov eax, [rdi]\ntest eax, eax\njns short loc_1558\ncmp esi, eax\nmov r8d, eax\ncmovge r8d, esi\ntest esi, esi\ncmovnz eax, r8d\nadd rdi, 4\nmov esi, eax\ncmp rdi, r9\njnz short loc_1574\nloc_1594:\nmov [rdx], esi\nmov [rdx+4], ecx\nretn\nloc_15A0:\nxor ecx, ecx\nxor esi, esi\nmov [rdx], esi\nmov [rdx+4], ecx\nretn", + "ida_strip_pseudo": "void __fastcall sub_1540(int *a1, int a2, int *a3)\n{\n int v3; // ecx\n int *v4; // r9\n int v5; // esi\n int v6; // r8d\n int v7; // eax\n int v8; // r8d\n\n if ( a2 <= 0 )\n {\n *a3 = 0;\n a3[1] = 0;\n }\n else\n {\n v3 = 0;\n v4 = &a1[a2];\n v5 = 0;\n do\n {\n while ( 1 )\n {\n v7 = *a1;\n if ( *a1 >= 0 )\n break;\n v8 = *a1;\n if ( v5 >= v7 )\n v8 = v5;\n if ( v5 )\n v7 = v8;\n ++a1;\n v5 = v7;\n if ( a1 == v4 )\n goto LABEL_16;\n }\n if ( v7 )\n {\n v6 = *a1;\n if ( v3 <= v7 )\n v6 = v3;\n if ( v3 )\n v7 = v6;\n v3 = v7;\n }\n ++a1;\n }\n while ( a1 != v4 );\nLABEL_16:\n *a3 = v5;\n a3[1] = v3;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1540(int *a1, int a2, int *a3) {\n int v3;\n int *v4;\n int v5;\n int v6;\n int v7;\n int v8;\n if (a2 <= 0) {\n *a3 = 0;\n a3[1] = 0;\n } else {\n v3 = 0;\n v4 = &a1[a2];\n v5 = 0;\n do {\n while (1) {\n v7 = *a1;\n if (*a1 >= 0) break;\n v8 = *a1;\n if (v5 >= v7) v8 = v5;\n if (v5) v7 = v8;\n ++a1;\n v5 = v7;\n if (a1 == v4) goto LABEL_16;\n }\n if (v7) {\n v6 = *a1;\n if (v3 <= v7) v6 = v3;\n if (v3) v7 = v6;\n v3 = v7;\n }\n ++a1;\n } while (a1 != v4);\n LABEL_16:\n *a3 = v5;\n a3[1] = v3;\n }\n}", + "ida_pseudo_norm": "void func0(int *a1, int a2, int *a3) {\n int v3;\n int *v4;\n int v5;\n int v6;\n int v7;\n int v8;\n if (a2 <= 0) {\n *a3 = 0;\n a3[1] = 0;\n } else {\n v3 = 0;\n v4 = &a1[a2];\n v5 = 0;\n do {\n while (1) {\n v7 = *a1;\n if (*a1 >= 0) break;\n v8 = *a1;\n if (v5 >= v7) v8 = v5;\n if (v5) v7 = v8;\n ++a1;\n v5 = v7;\n if (a1 == v4) goto LABEL_16;\n }\n if (v7) {\n v6 = *a1;\n if (v3 <= v7) v6 = v3;\n if (v3) v7 = v6;\n v3 = v7;\n }\n ++a1;\n } while (a1 != v4);\n LABEL_16:\n *a3 = v5;\n a3[1] = v3;\n }\n}" + }, + { + "index": "HumanEval-C-137", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char* func0(const char* a, const char* b) {\n char* end;\n char* a_modified = strdup(a);\n char* b_modified = strdup(b);\n for (int i = 0; a_modified[i]; ++i)\n if (a_modified[i] == ',') a_modified[i] = '.';\n for (int i = 0; b_modified[i]; ++i)\n if (b_modified[i] == ',') b_modified[i] = '.';\n double numa = strtod(a_modified, &end);\n if (*end) {\n free(a_modified);\n free(b_modified);\n return \"Invalid input\";\n }\n double numb = strtod(b_modified, &end);\n if (*end) {\n free(a_modified);\n free(b_modified);\n return \"Invalid input\";\n }\n free(a_modified);\n free(b_modified);\n if (numa == numb) return \"None\";\n return numa > numb ? (char*)a : (char*)b;\n}", + "test": "#include \n#include \n#include \n#include \n\nint main() {\n assert(strcmp(func0(\"1\", \"2\"), \"2\") == 0);\n assert(strcmp(func0(\"1\", \"2.5\"), \"2.5\") == 0);\n assert(strcmp(func0(\"2\", \"3\"), \"3\") == 0);\n assert(strcmp(func0(\"5\", \"6\"), \"6\") == 0);\n assert(strcmp(func0(\"1\", \"2,3\"), \"2,3\") == 0);\n assert(strcmp(func0(\"5,1\", \"6\"), \"6\") == 0);\n assert(strcmp(func0(\"1\", \"2\"), \"2\") == 0);\n assert(strcmp(func0(\"1\", \"1\"), \"None\") == 0);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+s], rdi\nmov [rbp+var_50], rsi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strdup\nmov [rbp+nptr], rax\nmov rax, [rbp+var_50]\nmov rdi, rax; s\ncall _strdup\nmov [rbp+ptr], rax\nmov [rbp+var_38], 0\njmp short loc_125D\nloc_1235:\nmov eax, [rbp+var_38]\nmovsxd rdx, eax\nmov rax, [rbp+nptr]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 2Ch ; ','\njnz short loc_1259\nmov eax, [rbp+var_38]\nmovsxd rdx, eax\nmov rax, [rbp+nptr]\nadd rax, rdx\nmov byte ptr [rax], 2Eh ; '.'\nloc_1259:\nadd [rbp+var_38], 1\nloc_125D:\nmov eax, [rbp+var_38]\nmovsxd rdx, eax\nmov rax, [rbp+nptr]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1235\nmov [rbp+var_34], 0\njmp short loc_12A2\nloc_127A:\nmov eax, [rbp+var_34]\nmovsxd rdx, eax\nmov rax, [rbp+ptr]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 2Ch ; ','\njnz short loc_129E\nmov eax, [rbp+var_34]\nmovsxd rdx, eax\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov byte ptr [rax], 2Eh ; '.'\nloc_129E:\nadd [rbp+var_34], 1\nloc_12A2:\nmov eax, [rbp+var_34]\nmovsxd rdx, eax\nmov rax, [rbp+ptr]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_127A\nlea rdx, [rbp+endptr]\nmov rax, [rbp+nptr]\nmov rsi, rdx; endptr\nmov rdi, rax; nptr\ncall _strtod\nmovq rax, xmm0\nmov [rbp+var_18], rax\nmov rax, [rbp+endptr]\nmovzx eax, byte ptr [rax]\ntest al, al\njz short loc_1301\nmov rax, [rbp+nptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nlea rax, aInvalidInput; \"Invalid input\"\njmp loc_1398\nloc_1301:\nlea rdx, [rbp+endptr]\nmov rax, [rbp+ptr]\nmov rsi, rdx; endptr\nmov rdi, rax; nptr\ncall _strtod\nmovq rax, xmm0\nmov [rbp+var_10], rax\nmov rax, [rbp+endptr]\nmovzx eax, byte ptr [rax]\ntest al, al\njz short loc_1349\nmov rax, [rbp+nptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nlea rax, aInvalidInput; \"Invalid input\"\njmp short loc_1398\nloc_1349:\nmov rax, [rbp+nptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmovsd xmm0, [rbp+var_18]\nucomisd xmm0, [rbp+var_10]\njp short loc_1382\nmovsd xmm0, [rbp+var_18]\nucomisd xmm0, [rbp+var_10]\njnz short loc_1382\nlea rax, aNone; \"None\"\njmp short loc_1398\nloc_1382:\nmovsd xmm0, [rbp+var_18]\ncomisd xmm0, [rbp+var_10]\njbe short loc_1394\nmov rax, [rbp+s]\njmp short loc_1398\nloc_1394:\nmov rax, [rbp+var_50]\nloc_1398:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_13AC\ncall ___stack_chk_fail\nlocret_13AC:\nleave\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1, const char *a2)\n{\n int i; // [rsp+18h] [rbp-38h]\n int j; // [rsp+1Ch] [rbp-34h]\n char *endptr; // [rsp+20h] [rbp-30h] BYREF\n char *nptr; // [rsp+28h] [rbp-28h]\n void *ptr; // [rsp+30h] [rbp-20h]\n double v8; // [rsp+38h] [rbp-18h]\n double v9; // [rsp+40h] [rbp-10h]\n unsigned __int64 v10; // [rsp+48h] [rbp-8h]\n\n v10 = __readfsqword(0x28u);\n nptr = strdup(a1);\n ptr = strdup(a2);\n for ( i = 0; nptr[i]; ++i )\n {\n if ( nptr[i] == 44 )\n nptr[i] = 46;\n }\n for ( j = 0; *((_BYTE *)ptr + j); ++j )\n {\n if ( *((_BYTE *)ptr + j) == 44 )\n *((_BYTE *)ptr + j) = 46;\n }\n v8 = strtod(nptr, &endptr);\n if ( *endptr || (v9 = strtod((const char *)ptr, &endptr), *endptr) )\n {\n free(nptr);\n free(ptr);\n return \"Invalid input\";\n }\n else\n {\n free(nptr);\n free(ptr);\n if ( v8 == v9 )\n {\n return \"None\";\n }\n else if ( v8 <= v9 )\n {\n return a2;\n }\n else\n {\n return a1;\n }\n }\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+s], rdi\nmov [rbp+var_50], rsi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strdup\nmov [rbp+nptr], rax\nmov rax, [rbp+var_50]\nmov rdi, rax; s\ncall _strdup\nmov [rbp+ptr], rax\nmov [rbp+var_38], 0\njmp short loc_125D\nloc_1235:\nmov eax, [rbp+var_38]\nmovsxd rdx, eax\nmov rax, [rbp+nptr]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 2Ch ; ','\njnz short loc_1259\nmov eax, [rbp+var_38]\nmovsxd rdx, eax\nmov rax, [rbp+nptr]\nadd rax, rdx\nmov byte ptr [rax], 2Eh ; '.'\nloc_1259:\nadd [rbp+var_38], 1\nloc_125D:\nmov eax, [rbp+var_38]\nmovsxd rdx, eax\nmov rax, [rbp+nptr]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1235\nmov [rbp+var_34], 0\njmp short loc_12A2\nloc_127A:\nmov eax, [rbp+var_34]\nmovsxd rdx, eax\nmov rax, [rbp+ptr]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 2Ch ; ','\njnz short loc_129E\nmov eax, [rbp+var_34]\nmovsxd rdx, eax\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov byte ptr [rax], 2Eh ; '.'\nloc_129E:\nadd [rbp+var_34], 1\nloc_12A2:\nmov eax, [rbp+var_34]\nmovsxd rdx, eax\nmov rax, [rbp+ptr]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_127A\nlea rdx, [rbp+endptr]\nmov rax, [rbp+nptr]\nmov rsi, rdx; endptr\nmov rdi, rax; nptr\ncall _strtod\nmovq rax, xmm0\nmov [rbp+var_18], rax\nmov rax, [rbp+endptr]\nmovzx eax, byte ptr [rax]\ntest al, al\njz short loc_1301\nmov rax, [rbp+nptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nlea rax, aInvalidInput; \"Invalid input\"\njmp loc_1398\nloc_1301:\nlea rdx, [rbp+endptr]\nmov rax, [rbp+ptr]\nmov rsi, rdx; endptr\nmov rdi, rax; nptr\ncall _strtod\nmovq rax, xmm0\nmov [rbp+var_10], rax\nmov rax, [rbp+endptr]\nmovzx eax, byte ptr [rax]\ntest al, al\njz short loc_1349\nmov rax, [rbp+nptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nlea rax, aInvalidInput; \"Invalid input\"\njmp short loc_1398\nloc_1349:\nmov rax, [rbp+nptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmovsd xmm0, [rbp+var_18]\nucomisd xmm0, [rbp+var_10]\njp short loc_1382\nmovsd xmm0, [rbp+var_18]\nucomisd xmm0, [rbp+var_10]\njnz short loc_1382\nlea rax, aNone; \"None\"\njmp short loc_1398\nloc_1382:\nmovsd xmm0, [rbp+var_18]\ncomisd xmm0, [rbp+var_10]\njbe short loc_1394\nmov rax, [rbp+s]\njmp short loc_1398\nloc_1394:\nmov rax, [rbp+var_50]\nloc_1398:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_13AC\ncall ___stack_chk_fail\nlocret_13AC:\nleave\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_11E9(const char *a1, const char *a2)\n{\n int i; // [rsp+18h] [rbp-38h]\n int j; // [rsp+1Ch] [rbp-34h]\n char *endptr; // [rsp+20h] [rbp-30h] BYREF\n char *nptr; // [rsp+28h] [rbp-28h]\n void *ptr; // [rsp+30h] [rbp-20h]\n double v8; // [rsp+38h] [rbp-18h]\n double v9; // [rsp+40h] [rbp-10h]\n unsigned __int64 v10; // [rsp+48h] [rbp-8h]\n\n v10 = __readfsqword(0x28u);\n nptr = strdup(a1);\n ptr = strdup(a2);\n for ( i = 0; nptr[i]; ++i )\n {\n if ( nptr[i] == 44 )\n nptr[i] = 46;\n }\n for ( j = 0; *((_BYTE *)ptr + j); ++j )\n {\n if ( *((_BYTE *)ptr + j) == 44 )\n *((_BYTE *)ptr + j) = 46;\n }\n v8 = strtod(nptr, &endptr);\n if ( *endptr || (v9 = strtod((const char *)ptr, &endptr), *endptr) )\n {\n free(nptr);\n free(ptr);\n return \"Invalid input\";\n }\n else\n {\n free(nptr);\n free(ptr);\n if ( v8 == v9 )\n {\n return \"None\";\n }\n else if ( v8 <= v9 )\n {\n return a2;\n }\n else\n {\n return a1;\n }\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_11E9(const char *a1, const char *a2) {\n int i;\n int j;\n char *endptr;\n char *nptr;\n void *ptr;\n double v8;\n double v9;\n unsigned long long v10;\n v10 = __readfsqword(40u);\n nptr = strdup(a1);\n ptr = strdup(a2);\n for (i = 0; nptr[i]; ++i) {\n if (nptr[i] == 44) nptr[i] = 46;\n }\n for (j = 0; *((uint8_t *)ptr + j); ++j) {\n if (*((uint8_t *)ptr + j) == 44) *((uint8_t *)ptr + j) = 46;\n }\n v8 = strtod(nptr, &endptr);\n if (*endptr || (v9 = strtod((const char *)ptr, &endptr), *endptr)) {\n free(nptr);\n free(ptr);\n return \"Invalid input\";\n } else {\n free(nptr);\n free(ptr);\n if (v8 == v9) {\n return \"None\";\n } else if (v8 <= v9) {\n return a2;\n } else {\n return a1;\n }\n }\n}", + "ida_pseudo_norm": "const char *func0(const char *a1, const char *a2) {\n int i;\n int j;\n char *endptr;\n char *nptr;\n void *ptr;\n double v8;\n double v9;\n unsigned long long v10;\n v10 = __readfsqword(40u);\n nptr = strdup(a1);\n ptr = strdup(a2);\n for (i = 0; nptr[i]; ++i) {\n if (nptr[i] == 44) nptr[i] = 46;\n }\n for (j = 0; *((uint8_t *)ptr + j); ++j) {\n if (*((uint8_t *)ptr + j) == 44) *((uint8_t *)ptr + j) = 46;\n }\n v8 = strtod(nptr, &endptr);\n if (*endptr || (v9 = strtod((const char *)ptr, &endptr), *endptr)) {\n free(nptr);\n free(ptr);\n return \"Invalid input\";\n } else {\n free(nptr);\n free(ptr);\n if (v8 == v9) {\n return \"None\";\n } else if (v8 <= v9) {\n return a2;\n } else {\n return a1;\n }\n }\n}" + }, + { + "index": "HumanEval-C-137", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char* func0(const char* a, const char* b) {\n char* end;\n char* a_modified = strdup(a);\n char* b_modified = strdup(b);\n for (int i = 0; a_modified[i]; ++i)\n if (a_modified[i] == ',') a_modified[i] = '.';\n for (int i = 0; b_modified[i]; ++i)\n if (b_modified[i] == ',') b_modified[i] = '.';\n double numa = strtod(a_modified, &end);\n if (*end) {\n free(a_modified);\n free(b_modified);\n return \"Invalid input\";\n }\n double numb = strtod(b_modified, &end);\n if (*end) {\n free(a_modified);\n free(b_modified);\n return \"Invalid input\";\n }\n free(a_modified);\n free(b_modified);\n if (numa == numb) return \"None\";\n return numa > numb ? (char*)a : (char*)b;\n}", + "test": "#include \n#include \n#include \n#include \n\nint main() {\n assert(strcmp(func0(\"1\", \"2\"), \"2\") == 0);\n assert(strcmp(func0(\"1\", \"2.5\"), \"2.5\") == 0);\n assert(strcmp(func0(\"2\", \"3\"), \"3\") == 0);\n assert(strcmp(func0(\"5\", \"6\"), \"6\") == 0);\n assert(strcmp(func0(\"1\", \"2,3\"), \"2,3\") == 0);\n assert(strcmp(func0(\"5,1\", \"6\"), \"6\") == 0);\n assert(strcmp(func0(\"1\", \"2\"), \"2\") == 0);\n assert(strcmp(func0(\"1\", \"1\"), \"None\") == 0);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov r13, rdi\nmov r12, rsi\nmov rax, fs:28h\nmov [rsp+48h+var_30], rax\nxor eax, eax\ncall _strdup\nmov rbx, rax\nmov rdi, r12; s\ncall _strdup\nmov rbp, rax\nmovzx edx, byte ptr [rbx]\ntest dl, dl\njz short loc_1241\nmov rax, rbx\njmp short loc_1237\nloc_122C:\nadd rax, 1\nmovzx edx, byte ptr [rax]\ntest dl, dl\njz short loc_1241\nloc_1237:\ncmp dl, 2Ch ; ','\njnz short loc_122C\nmov byte ptr [rax], 2Eh ; '.'\njmp short loc_122C\nloc_1241:\nmovzx edx, byte ptr [rbp+0]\ntest dl, dl\njz short loc_1263\nmov rax, rbp\njmp short loc_1259\nloc_124E:\nadd rax, 1\nmovzx edx, byte ptr [rax]\ntest dl, dl\njz short loc_1263\nloc_1259:\ncmp dl, 2Ch ; ','\njnz short loc_124E\nmov byte ptr [rax], 2Eh ; '.'\njmp short loc_124E\nloc_1263:\nlea rsi, [rsp+48h+endptr]; endptr\nmov rdi, rbx; nptr\ncall _strtod\nmovsd [rsp+48h+var_48], xmm0\nmov rax, [rsp+48h+endptr]\ncmp byte ptr [rax], 0\njnz short loc_12DA\nlea rsi, [rsp+48h+endptr]; endptr\nmov rdi, rbp; nptr\ncall _strtod\nmovsd [rsp+48h+var_40], xmm0\nmov rax, [rsp+48h+endptr]\ncmp byte ptr [rax], 0\njnz short loc_130C\nmov rdi, rbx; ptr\ncall _free\nmov rdi, rbp; ptr\ncall _free\nmovsd xmm1, [rsp+48h+var_48]\nmovsd xmm2, [rsp+48h+var_40]\nucomisd xmm1, xmm2\njp short loc_12C6\nlea rax, aNone; \"None\"\njz short loc_12F1\nloc_12C6:\nmovsd xmm3, [rsp+48h+var_48]\ncomisd xmm3, [rsp+48h+var_40]\nmov rax, r12\ncmova rax, r13\njmp short loc_12F1\nloc_12DA:\nmov rdi, rbx; ptr\ncall _free\nmov rdi, rbp; ptr\ncall _free\nlea rax, aInvalidInput; \"Invalid input\"\nloc_12F1:\nmov rdx, [rsp+48h+var_30]\nsub rdx, fs:28h\njnz short loc_1325\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_130C:\nmov rdi, rbx; ptr\ncall _free\nmov rdi, rbp; ptr\ncall _free\nlea rax, aInvalidInput; \"Invalid input\"\njmp short loc_12F1\nloc_1325:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(const char *a1, const char *a2)\n{\n char *v2; // rbx\n char *v3; // rbp\n char v4; // dl\n char *v5; // rax\n char v6; // dl\n char *v7; // rax\n const char *result; // rax\n double v9; // [rsp+0h] [rbp-48h]\n double v10; // [rsp+8h] [rbp-40h]\n char *endptr[7]; // [rsp+10h] [rbp-38h] BYREF\n\n endptr[1] = (char *)__readfsqword(0x28u);\n v2 = strdup(a1);\n v3 = strdup(a2);\n v4 = *v2;\n if ( *v2 )\n {\n v5 = v2;\n do\n {\n if ( v4 == 44 )\n *v5 = 46;\n v4 = *++v5;\n }\n while ( *v5 );\n }\n v6 = *v3;\n if ( *v3 )\n {\n v7 = v3;\n do\n {\n if ( v6 == 44 )\n *v7 = 46;\n v6 = *++v7;\n }\n while ( *v7 );\n }\n v9 = strtod(v2, endptr);\n if ( *endptr[0] || (v10 = strtod(v3, endptr), *endptr[0]) )\n {\n free(v2);\n free(v3);\n return \"Invalid input\";\n }\n else\n {\n free(v2);\n free(v3);\n result = \"None\";\n if ( v9 != v10 )\n {\n result = a2;\n if ( v9 > v10 )\n return a1;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov r13, rdi\nmov r12, rsi\nmov rax, fs:28h\nmov [rsp+48h+var_30], rax\nxor eax, eax\ncall _strdup\nmov rbx, rax\nmov rdi, r12; s\ncall _strdup\nmov rbp, rax\nmovzx edx, byte ptr [rbx]\ntest dl, dl\njz short loc_1241\nmov rax, rbx\njmp short loc_1237\nloc_122C:\nadd rax, 1\nmovzx edx, byte ptr [rax]\ntest dl, dl\njz short loc_1241\nloc_1237:\ncmp dl, 2Ch ; ','\njnz short loc_122C\nmov byte ptr [rax], 2Eh ; '.'\njmp short loc_122C\nloc_1241:\nmovzx edx, byte ptr [rbp+0]\ntest dl, dl\njz short loc_1263\nmov rax, rbp\njmp short loc_1259\nloc_124E:\nadd rax, 1\nmovzx edx, byte ptr [rax]\ntest dl, dl\njz short loc_1263\nloc_1259:\ncmp dl, 2Ch ; ','\njnz short loc_124E\nmov byte ptr [rax], 2Eh ; '.'\njmp short loc_124E\nloc_1263:\nlea rsi, [rsp+48h+endptr]; endptr\nmov rdi, rbx; nptr\ncall _strtod\nmovsd [rsp+48h+var_48], xmm0\nmov rax, [rsp+48h+endptr]\ncmp byte ptr [rax], 0\njnz short loc_12DA\nlea rsi, [rsp+48h+endptr]; endptr\nmov rdi, rbp; nptr\ncall _strtod\nmovsd [rsp+48h+var_40], xmm0\nmov rax, [rsp+48h+endptr]\ncmp byte ptr [rax], 0\njnz short loc_130C\nmov rdi, rbx; ptr\ncall _free\nmov rdi, rbp; ptr\ncall _free\nmovsd xmm1, [rsp+48h+var_48]\nmovsd xmm2, [rsp+48h+var_40]\nucomisd xmm1, xmm2\njp short loc_12C6\nlea rax, aNone; \"None\"\njz short loc_12F1\nloc_12C6:\nmovsd xmm3, [rsp+48h+var_48]\ncomisd xmm3, [rsp+48h+var_40]\nmov rax, r12\ncmova rax, r13\njmp short loc_12F1\nloc_12DA:\nmov rdi, rbx; ptr\ncall _free\nmov rdi, rbp; ptr\ncall _free\nlea rax, aInvalidInput; \"Invalid input\"\nloc_12F1:\nmov rdx, [rsp+48h+var_30]\nsub rdx, fs:28h\njnz short loc_1325\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_130C:\nmov rdi, rbx; ptr\ncall _free\nmov rdi, rbp; ptr\ncall _free\nlea rax, aInvalidInput; \"Invalid input\"\njmp short loc_12F1\nloc_1325:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_11E9(const char *a1, const char *a2)\n{\n char *v2; // rbx\n char *v3; // rbp\n char v4; // dl\n char *v5; // rax\n char v6; // dl\n char *v7; // rax\n const char *result; // rax\n double v9; // [rsp+0h] [rbp-48h]\n double v10; // [rsp+8h] [rbp-40h]\n char *endptr[7]; // [rsp+10h] [rbp-38h] BYREF\n\n endptr[1] = (char *)__readfsqword(0x28u);\n v2 = strdup(a1);\n v3 = strdup(a2);\n v4 = *v2;\n if ( *v2 )\n {\n v5 = v2;\n do\n {\n if ( v4 == 44 )\n *v5 = 46;\n v4 = *++v5;\n }\n while ( *v5 );\n }\n v6 = *v3;\n if ( *v3 )\n {\n v7 = v3;\n do\n {\n if ( v6 == 44 )\n *v7 = 46;\n v6 = *++v7;\n }\n while ( *v7 );\n }\n v9 = strtod(v2, endptr);\n if ( *endptr[0] || (v10 = strtod(v3, endptr), *endptr[0]) )\n {\n free(v2);\n free(v3);\n return \"Invalid input\";\n }\n else\n {\n free(v2);\n free(v3);\n result = \"None\";\n if ( v9 != v10 )\n {\n result = a2;\n if ( v9 > v10 )\n return a1;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_11E9(const char *a1, const char *a2) {\n char *v2;\n char *v3;\n char v4;\n char *v5;\n char v6;\n char *v7;\n const char *result;\n double v9;\n double v10;\n char *endptr[7];\n endptr[1] = (char *)__readfsqword(40u);\n v2 = strdup(a1);\n v3 = strdup(a2);\n v4 = *v2;\n if (*v2) {\n v5 = v2;\n do {\n if (v4 == 44) *v5 = 46;\n v4 = *++v5;\n } while (*v5);\n }\n v6 = *v3;\n if (*v3) {\n v7 = v3;\n do {\n if (v6 == 44) *v7 = 46;\n v6 = *++v7;\n } while (*v7);\n }\n v9 = strtod(v2, endptr);\n if (*endptr[0] || (v10 = strtod(v3, endptr), *endptr[0])) {\n free(v2);\n free(v3);\n return \"Invalid input\";\n } else {\n free(v2);\n free(v3);\n result = \"None\";\n if (v9 != v10) {\n result = a2;\n if (v9 > v10) return a1;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(const char *a1, const char *a2) {\n char *v2;\n char *v3;\n char v4;\n char *v5;\n char v6;\n char *v7;\n const char *result;\n double v9;\n double v10;\n char *endptr[7];\n endptr[1] = (char *)__readfsqword(40u);\n v2 = strdup(a1);\n v3 = strdup(a2);\n v4 = *v2;\n if (*v2) {\n v5 = v2;\n do {\n if (v4 == 44) *v5 = 46;\n v4 = *++v5;\n } while (*v5);\n }\n v6 = *v3;\n if (*v3) {\n v7 = v3;\n do {\n if (v6 == 44) *v7 = 46;\n v6 = *++v7;\n } while (*v7);\n }\n v9 = strtod(v2, endptr);\n if (*endptr[0] || (v10 = strtod(v3, endptr), *endptr[0])) {\n free(v2);\n free(v3);\n return \"Invalid input\";\n } else {\n free(v2);\n free(v3);\n result = \"None\";\n if (v9 != v10) {\n result = a2;\n if (v9 > v10) return a1;\n }\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-137", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char* func0(const char* a, const char* b) {\n char* end;\n char* a_modified = strdup(a);\n char* b_modified = strdup(b);\n for (int i = 0; a_modified[i]; ++i)\n if (a_modified[i] == ',') a_modified[i] = '.';\n for (int i = 0; b_modified[i]; ++i)\n if (b_modified[i] == ',') b_modified[i] = '.';\n double numa = strtod(a_modified, &end);\n if (*end) {\n free(a_modified);\n free(b_modified);\n return \"Invalid input\";\n }\n double numb = strtod(b_modified, &end);\n if (*end) {\n free(a_modified);\n free(b_modified);\n return \"Invalid input\";\n }\n free(a_modified);\n free(b_modified);\n if (numa == numb) return \"None\";\n return numa > numb ? (char*)a : (char*)b;\n}", + "test": "#include \n#include \n#include \n#include \n\nint main() {\n assert(strcmp(func0(\"1\", \"2\"), \"2\") == 0);\n assert(strcmp(func0(\"1\", \"2.5\"), \"2.5\") == 0);\n assert(strcmp(func0(\"2\", \"3\"), \"3\") == 0);\n assert(strcmp(func0(\"5\", \"6\"), \"6\") == 0);\n assert(strcmp(func0(\"1\", \"2,3\"), \"2,3\") == 0);\n assert(strcmp(func0(\"5,1\", \"6\"), \"6\") == 0);\n assert(strcmp(func0(\"1\", \"2\"), \"2\") == 0);\n assert(strcmp(func0(\"1\", \"1\"), \"None\") == 0);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\nmov r13, rsi\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 28h\nmov rax, fs:28h\nmov [rsp+58h+var_40], rax\nxor eax, eax\ncall _strdup\nmov rdi, r13; s\nmov rbx, rax\ncall _strdup\nmovzx edx, byte ptr [rbx]\nmov rbp, rax\ntest dl, dl\njz short loc_146C\nmov rax, rbx\nnop dword ptr [rax]\nloc_1458:\ncmp dl, 2Ch ; ','\njnz short loc_1460\nmov byte ptr [rax], 2Eh ; '.'\nloc_1460:\nmovzx edx, byte ptr [rax+1]\nadd rax, 1\ntest dl, dl\njnz short loc_1458\nloc_146C:\nmovzx edx, byte ptr [rbp+0]\ntest dl, dl\njz short loc_1494\nmov rax, rbp\nnop word ptr [rax+rax+00000000h]\nloc_1480:\ncmp dl, 2Ch ; ','\njnz short loc_1488\nmov byte ptr [rax], 2Eh ; '.'\nloc_1488:\nmovzx edx, byte ptr [rax+1]\nadd rax, 1\ntest dl, dl\njnz short loc_1480\nloc_1494:\nlea r14, [rsp+58h+endptr]\nmov rdi, rbx; nptr\nmov rsi, r14; endptr\ncall _strtod\nmov rax, [rsp+58h+endptr]\nmovq r15, xmm0\ncmp byte ptr [rax], 0\njnz short loc_1508\nmov rsi, r14; endptr\nmov rdi, rbp; nptr\ncall _strtod\nmov rax, [rsp+58h+endptr]\ncmp byte ptr [rax], 0\njnz short loc_1508\nmov rdi, rbx; ptr\nmovsd [rsp+58h+var_50], xmm0\ncall _free\nmov rdi, rbp; ptr\ncall _free\nmovsd xmm0, [rsp+58h+var_50]\nmovq xmm1, r15\ncomisd xmm1, xmm0\njp short loc_14FD\nlea rax, aNone; \"None\"\njz short loc_151F\nmov rax, r12\nja short loc_151F\nloc_14FD:\nmov rax, r13\njmp short loc_151F\nloc_1508:\nmov rdi, rbx; ptr\ncall _free\nmov rdi, rbp; ptr\ncall _free\nlea rax, aInvalidInput; \"Invalid input\"\nloc_151F:\nmov rdx, [rsp+58h+var_40]\nsub rdx, fs:28h\njnz short loc_153E\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_153E:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(const char *a1, const char *a2)\n{\n char *v2; // rbx\n char *v3; // rax\n char v4; // dl\n char *v5; // rbp\n char *v6; // rax\n char v7; // dl\n char *v8; // rax\n double v9; // r15\n double v10; // xmm0_8\n const char *result; // rax\n char *endptr[9]; // [rsp+10h] [rbp-48h] BYREF\n\n endptr[1] = (char *)__readfsqword(0x28u);\n v2 = strdup(a1);\n v3 = strdup(a2);\n v4 = *v2;\n v5 = v3;\n if ( *v2 )\n {\n v6 = v2;\n do\n {\n if ( v4 == 44 )\n *v6 = 46;\n v4 = *++v6;\n }\n while ( v4 );\n }\n v7 = *v5;\n if ( *v5 )\n {\n v8 = v5;\n do\n {\n if ( v7 == 44 )\n *v8 = 46;\n v7 = *++v8;\n }\n while ( v7 );\n }\n v9 = strtod(v2, endptr);\n if ( *endptr[0] || (v10 = strtod(v5, endptr), *endptr[0]) )\n {\n free(v2);\n free(v5);\n return \"Invalid input\";\n }\n else\n {\n free(v2);\n free(v5);\n result = \"None\";\n if ( v9 != v10 )\n {\n result = a1;\n if ( v9 <= v10 )\n return a2;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1410:\nendbr64\npush r15\npush r14\npush r13\nmov r13, rsi\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 28h\nmov rax, fs:28h\nmov [rsp+58h+var_40], rax\nxor eax, eax\ncall _strdup\nmov rdi, r13; s\nmov rbx, rax\ncall _strdup\nmovzx edx, byte ptr [rbx]\nmov rbp, rax\ntest dl, dl\njz short loc_146C\nmov rax, rbx\nnop dword ptr [rax]\nloc_1458:\ncmp dl, 2Ch ; ','\njnz short loc_1460\nmov byte ptr [rax], 2Eh ; '.'\nloc_1460:\nmovzx edx, byte ptr [rax+1]\nadd rax, 1\ntest dl, dl\njnz short loc_1458\nloc_146C:\nmovzx edx, byte ptr [rbp+0]\ntest dl, dl\njz short loc_1494\nmov rax, rbp\nnop word ptr [rax+rax+00000000h]\nloc_1480:\ncmp dl, 2Ch ; ','\njnz short loc_1488\nmov byte ptr [rax], 2Eh ; '.'\nloc_1488:\nmovzx edx, byte ptr [rax+1]\nadd rax, 1\ntest dl, dl\njnz short loc_1480\nloc_1494:\nlea r14, [rsp+58h+endptr]\nmov rdi, rbx; nptr\nmov rsi, r14; endptr\ncall _strtod\nmov rax, [rsp+58h+endptr]\nmovq r15, xmm0\ncmp byte ptr [rax], 0\njnz short loc_1508\nmov rsi, r14; endptr\nmov rdi, rbp; nptr\ncall _strtod\nmov rax, [rsp+58h+endptr]\ncmp byte ptr [rax], 0\njnz short loc_1508\nmov rdi, rbx; ptr\nmovsd [rsp+58h+var_50], xmm0\ncall _free\nmov rdi, rbp; ptr\ncall _free\nmovsd xmm0, [rsp+58h+var_50]\nmovq xmm1, r15\ncomisd xmm1, xmm0\njp short loc_14FD\nlea rax, aNone; \"None\"\njz short loc_151F\nmov rax, r12\nja short loc_151F\nloc_14FD:\nmov rax, r13\njmp short loc_151F\nloc_1508:\nmov rdi, rbx; ptr\ncall _free\nmov rdi, rbp; ptr\ncall _free\nlea rax, aInvalidInput; \"Invalid input\"\nloc_151F:\nmov rdx, [rsp+58h+var_40]\nsub rdx, fs:28h\njnz short loc_153E\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_153E:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_1410(const char *a1, const char *a2)\n{\n char *v2; // rbx\n char *v3; // rax\n char v4; // dl\n char *v5; // rbp\n char *v6; // rax\n char v7; // dl\n char *v8; // rax\n double v9; // r15\n double v10; // xmm0_8\n const char *result; // rax\n char *endptr[9]; // [rsp+10h] [rbp-48h] BYREF\n\n endptr[1] = (char *)__readfsqword(0x28u);\n v2 = strdup(a1);\n v3 = strdup(a2);\n v4 = *v2;\n v5 = v3;\n if ( *v2 )\n {\n v6 = v2;\n do\n {\n if ( v4 == 44 )\n *v6 = 46;\n v4 = *++v6;\n }\n while ( v4 );\n }\n v7 = *v5;\n if ( *v5 )\n {\n v8 = v5;\n do\n {\n if ( v7 == 44 )\n *v8 = 46;\n v7 = *++v8;\n }\n while ( v7 );\n }\n v9 = strtod(v2, endptr);\n if ( *endptr[0] || (v10 = strtod(v5, endptr), *endptr[0]) )\n {\n free(v2);\n free(v5);\n return \"Invalid input\";\n }\n else\n {\n free(v2);\n free(v5);\n result = \"None\";\n if ( v9 != v10 )\n {\n result = a1;\n if ( v9 <= v10 )\n return a2;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1410(const char *a1, const char *a2) {\n char *v2;\n char *v3;\n char v4;\n char *v5;\n char *v6;\n char v7;\n char *v8;\n double v9;\n double v10;\n const char *result;\n char *endptr[9];\n endptr[1] = (char *)__readfsqword(40u);\n v2 = strdup(a1);\n v3 = strdup(a2);\n v4 = *v2;\n v5 = v3;\n if (*v2) {\n v6 = v2;\n do {\n if (v4 == 44) *v6 = 46;\n v4 = *++v6;\n } while (v4);\n }\n v7 = *v5;\n if (*v5) {\n v8 = v5;\n do {\n if (v7 == 44) *v8 = 46;\n v7 = *++v8;\n } while (v7);\n }\n v9 = strtod(v2, endptr);\n if (*endptr[0] || (v10 = strtod(v5, endptr), *endptr[0])) {\n free(v2);\n free(v5);\n return \"Invalid input\";\n } else {\n free(v2);\n free(v5);\n result = \"None\";\n if (v9 != v10) {\n result = a1;\n if (v9 <= v10) return a2;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(const char *a1, const char *a2) {\n char *v2;\n char *v3;\n char v4;\n char *v5;\n char *v6;\n char v7;\n char *v8;\n double v9;\n double v10;\n const char *result;\n char *endptr[9];\n endptr[1] = (char *)__readfsqword(40u);\n v2 = strdup(a1);\n v3 = strdup(a2);\n v4 = *v2;\n v5 = v3;\n if (*v2) {\n v6 = v2;\n do {\n if (v4 == 44) *v6 = 46;\n v4 = *++v6;\n } while (v4);\n }\n v7 = *v5;\n if (*v5) {\n v8 = v5;\n do {\n if (v7 == 44) *v8 = 46;\n v7 = *++v8;\n } while (v7);\n }\n v9 = strtod(v2, endptr);\n if (*endptr[0] || (v10 = strtod(v5, endptr), *endptr[0])) {\n free(v2);\n free(v5);\n return \"Invalid input\";\n } else {\n free(v2);\n free(v5);\n result = \"None\";\n if (v9 != v10) {\n result = a1;\n if (v9 <= v10) return a2;\n }\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-137", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char* func0(const char* a, const char* b) {\n char* end;\n char* a_modified = strdup(a);\n char* b_modified = strdup(b);\n for (int i = 0; a_modified[i]; ++i)\n if (a_modified[i] == ',') a_modified[i] = '.';\n for (int i = 0; b_modified[i]; ++i)\n if (b_modified[i] == ',') b_modified[i] = '.';\n double numa = strtod(a_modified, &end);\n if (*end) {\n free(a_modified);\n free(b_modified);\n return \"Invalid input\";\n }\n double numb = strtod(b_modified, &end);\n if (*end) {\n free(a_modified);\n free(b_modified);\n return \"Invalid input\";\n }\n free(a_modified);\n free(b_modified);\n if (numa == numb) return \"None\";\n return numa > numb ? (char*)a : (char*)b;\n}", + "test": "#include \n#include \n#include \n#include \n\nint main() {\n assert(strcmp(func0(\"1\", \"2\"), \"2\") == 0);\n assert(strcmp(func0(\"1\", \"2.5\"), \"2.5\") == 0);\n assert(strcmp(func0(\"2\", \"3\"), \"3\") == 0);\n assert(strcmp(func0(\"5\", \"6\"), \"6\") == 0);\n assert(strcmp(func0(\"1\", \"2,3\"), \"2,3\") == 0);\n assert(strcmp(func0(\"5,1\", \"6\"), \"6\") == 0);\n assert(strcmp(func0(\"1\", \"2\"), \"2\") == 0);\n assert(strcmp(func0(\"1\", \"1\"), \"None\") == 0);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\nmov r13, rsi\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 28h\nmov rax, fs:28h\nmov [rsp+58h+var_40], rax\nxor eax, eax\ncall _strdup\nmov rdi, r13; s\nmov rbx, rax\ncall _strdup\nmovzx edx, byte ptr [rbx]\nmov rbp, rax\ntest dl, dl\njz short loc_146D\nmov rax, rbx\nnop dword ptr [rax]\nloc_1458:\ncmp dl, 2Ch ; ','\njz loc_1540\nmovzx edx, byte ptr [rax+1]\nadd rax, 1\ntest dl, dl\njnz short loc_1458\nloc_146D:\nmovzx edx, byte ptr [rbp+0]\ntest dl, dl\njz short loc_1495\nmov rax, rbp\nnop dword ptr [rax+rax+00000000h]\nloc_1480:\ncmp dl, 2Ch ; ','\njz loc_1560\nmovzx edx, byte ptr [rax+1]\nadd rax, 1\ntest dl, dl\njnz short loc_1480\nloc_1495:\nlea r14, [rsp+58h+endptr]\nmov rdi, rbx; nptr\nmov rsi, r14; endptr\ncall _strtod\nmov rax, [rsp+58h+endptr]\nmovq r15, xmm0\ncmp byte ptr [rax], 0\njnz short loc_1508\nmov rsi, r14; endptr\nmov rdi, rbp; nptr\ncall _strtod\nmov rax, [rsp+58h+endptr]\ncmp byte ptr [rax], 0\njnz short loc_1508\nmov rdi, rbx; ptr\nmovsd [rsp+58h+var_50], xmm0\ncall _free\nmov rdi, rbp; ptr\ncall _free\nmovsd xmm0, [rsp+58h+var_50]\nmovq xmm1, r15\ncomisd xmm1, xmm0\njp short loc_14FE\nlea rax, aNone; \"None\"\njz short loc_151F\nmov rax, r12\nja short loc_151F\nloc_14FE:\nmov rax, r13\njmp short loc_151F\nloc_1508:\nmov rdi, rbx; ptr\ncall _free\nmov rdi, rbp; ptr\ncall _free\nlea rax, aInvalidInput; \"Invalid input\"\nloc_151F:\nmov rdx, [rsp+58h+var_40]\nsub rdx, fs:28h\njnz short loc_1578\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1540:\nmov byte ptr [rax], 2Eh ; '.'\nmovzx edx, byte ptr [rax+1]\nadd rax, 1\ntest dl, dl\njnz loc_1458\njmp loc_146D\nloc_1560:\nmov byte ptr [rax], 2Eh ; '.'\nmovzx edx, byte ptr [rax+1]\nadd rax, 1\ntest dl, dl\njnz loc_1480\njmp loc_1495\nloc_1578:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(const char *a1, const char *a2)\n{\n char *v2; // rbx\n char *v3; // rax\n char v4; // dl\n char *v5; // rbp\n char *v6; // rax\n char v7; // dl\n char *v8; // rax\n double v9; // r15\n double v10; // xmm0_8\n const char *result; // rax\n char *endptr[9]; // [rsp+10h] [rbp-48h] BYREF\n\n endptr[1] = (char *)__readfsqword(0x28u);\n v2 = strdup(a1);\n v3 = strdup(a2);\n v4 = *v2;\n v5 = v3;\n if ( *v2 )\n {\n v6 = v2;\n do\n {\n while ( v4 != 44 )\n {\n v4 = *++v6;\n if ( !v4 )\n goto LABEL_5;\n }\n *v6 = 46;\n v4 = *++v6;\n }\n while ( v4 );\n }\nLABEL_5:\n v7 = *v5;\n if ( *v5 )\n {\n v8 = v5;\n do\n {\n while ( v7 != 44 )\n {\n v7 = *++v8;\n if ( !v7 )\n goto LABEL_9;\n }\n *v8 = 46;\n v7 = *++v8;\n }\n while ( v7 );\n }\nLABEL_9:\n v9 = strtod(v2, endptr);\n if ( *endptr[0] || (v10 = strtod(v5, endptr), *endptr[0]) )\n {\n free(v2);\n free(v5);\n return \"Invalid input\";\n }\n else\n {\n free(v2);\n free(v5);\n result = \"None\";\n if ( v9 != v10 )\n {\n result = a1;\n if ( v9 <= v10 )\n return a2;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1410:\nendbr64\npush r15\npush r14\npush r13\nmov r13, rsi\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 28h\nmov rax, fs:28h\nmov [rsp+58h+var_40], rax\nxor eax, eax\ncall _strdup\nmov rdi, r13; s\nmov rbx, rax\ncall _strdup\nmovzx edx, byte ptr [rbx]\nmov rbp, rax\ntest dl, dl\njz short loc_146D\nmov rax, rbx\nnop dword ptr [rax]\nloc_1458:\ncmp dl, 2Ch ; ','\njz loc_1540\nmovzx edx, byte ptr [rax+1]\nadd rax, 1\ntest dl, dl\njnz short loc_1458\nloc_146D:\nmovzx edx, byte ptr [rbp+0]\ntest dl, dl\njz short loc_1495\nmov rax, rbp\nnop dword ptr [rax+rax+00000000h]\nloc_1480:\ncmp dl, 2Ch ; ','\njz loc_1560\nmovzx edx, byte ptr [rax+1]\nadd rax, 1\ntest dl, dl\njnz short loc_1480\nloc_1495:\nlea r14, [rsp+58h+endptr]\nmov rdi, rbx; nptr\nmov rsi, r14; endptr\ncall _strtod\nmov rax, [rsp+58h+endptr]\nmovq r15, xmm0\ncmp byte ptr [rax], 0\njnz short loc_1508\nmov rsi, r14; endptr\nmov rdi, rbp; nptr\ncall _strtod\nmov rax, [rsp+58h+endptr]\ncmp byte ptr [rax], 0\njnz short loc_1508\nmov rdi, rbx; ptr\nmovsd [rsp+58h+var_50], xmm0\ncall _free\nmov rdi, rbp; ptr\ncall _free\nmovsd xmm0, [rsp+58h+var_50]\nmovq xmm1, r15\ncomisd xmm1, xmm0\njp short loc_14FE\nlea rax, aNone; \"None\"\njz short loc_151F\nmov rax, r12\nja short loc_151F\nloc_14FE:\nmov rax, r13\njmp short loc_151F\nloc_1508:\nmov rdi, rbx; ptr\ncall _free\nmov rdi, rbp; ptr\ncall _free\nlea rax, aInvalidInput; \"Invalid input\"\nloc_151F:\nmov rdx, [rsp+58h+var_40]\nsub rdx, fs:28h\njnz short loc_1578\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1540:\nmov byte ptr [rax], 2Eh ; '.'\nmovzx edx, byte ptr [rax+1]\nadd rax, 1\ntest dl, dl\njnz loc_1458\njmp loc_146D\nloc_1560:\nmov byte ptr [rax], 2Eh ; '.'\nmovzx edx, byte ptr [rax+1]\nadd rax, 1\ntest dl, dl\njnz loc_1480\njmp loc_1495\nloc_1578:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_1410(const char *a1, const char *a2)\n{\n char *v2; // rbx\n char *v3; // rax\n char v4; // dl\n char *v5; // rbp\n char *v6; // rax\n char v7; // dl\n char *v8; // rax\n double v9; // r15\n double v10; // xmm0_8\n const char *result; // rax\n char *endptr[9]; // [rsp+10h] [rbp-48h] BYREF\n\n endptr[1] = (char *)__readfsqword(0x28u);\n v2 = strdup(a1);\n v3 = strdup(a2);\n v4 = *v2;\n v5 = v3;\n if ( *v2 )\n {\n v6 = v2;\n do\n {\n while ( v4 != 44 )\n {\n v4 = *++v6;\n if ( !v4 )\n goto LABEL_5;\n }\n *v6 = 46;\n v4 = *++v6;\n }\n while ( v4 );\n }\nLABEL_5:\n v7 = *v5;\n if ( *v5 )\n {\n v8 = v5;\n do\n {\n while ( v7 != 44 )\n {\n v7 = *++v8;\n if ( !v7 )\n goto LABEL_9;\n }\n *v8 = 46;\n v7 = *++v8;\n }\n while ( v7 );\n }\nLABEL_9:\n v9 = strtod(v2, endptr);\n if ( *endptr[0] || (v10 = strtod(v5, endptr), *endptr[0]) )\n {\n free(v2);\n free(v5);\n return \"Invalid input\";\n }\n else\n {\n free(v2);\n free(v5);\n result = \"None\";\n if ( v9 != v10 )\n {\n result = a1;\n if ( v9 <= v10 )\n return a2;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1410(const char *a1, const char *a2) {\n char *v2;\n char *v3;\n char v4;\n char *v5;\n char *v6;\n char v7;\n char *v8;\n double v9;\n double v10;\n const char *result;\n char *endptr[9];\n endptr[1] = (char *)__readfsqword(40u);\n v2 = strdup(a1);\n v3 = strdup(a2);\n v4 = *v2;\n v5 = v3;\n if (*v2) {\n v6 = v2;\n do {\n while (v4 != 44) {\n v4 = *++v6;\n if (!v4) goto LABEL_5;\n }\n *v6 = 46;\n v4 = *++v6;\n } while (v4);\n }\nLABEL_5:\n v7 = *v5;\n if (*v5) {\n v8 = v5;\n do {\n while (v7 != 44) {\n v7 = *++v8;\n if (!v7) goto LABEL_9;\n }\n *v8 = 46;\n v7 = *++v8;\n } while (v7);\n }\nLABEL_9:\n v9 = strtod(v2, endptr);\n if (*endptr[0] || (v10 = strtod(v5, endptr), *endptr[0])) {\n free(v2);\n free(v5);\n return \"Invalid input\";\n } else {\n free(v2);\n free(v5);\n result = \"None\";\n if (v9 != v10) {\n result = a1;\n if (v9 <= v10) return a2;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(const char *a1, const char *a2) {\n char *v2;\n char *v3;\n char v4;\n char *v5;\n char *v6;\n char v7;\n char *v8;\n double v9;\n double v10;\n const char *result;\n char *endptr[9];\n endptr[1] = (char *)__readfsqword(40u);\n v2 = strdup(a1);\n v3 = strdup(a2);\n v4 = *v2;\n v5 = v3;\n if (*v2) {\n v6 = v2;\n do {\n while (v4 != 44) {\n v4 = *++v6;\n if (!v4) goto LABEL_5;\n }\n *v6 = 46;\n v4 = *++v6;\n } while (v4);\n }\nLABEL_5:\n v7 = *v5;\n if (*v5) {\n v8 = v5;\n do {\n while (v7 != 44) {\n v7 = *++v8;\n if (!v7) goto LABEL_9;\n }\n *v8 = 46;\n v7 = *++v8;\n } while (v7);\n }\nLABEL_9:\n v9 = strtod(v2, endptr);\n if (*endptr[0] || (v10 = strtod(v5, endptr), *endptr[0])) {\n free(v2);\n free(v5);\n return \"Invalid input\";\n } else {\n free(v2);\n free(v5);\n result = \"None\";\n if (v9 != v10) {\n result = a1;\n if (v9 <= v10) return a2;\n }\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-138", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int n) {\n if (n % 2 == 0 && n >= 8) return 1;\n return 0;\n}", + "test": "#include \n\nint main() {\n assert(func0(4) == 0);\n assert(func0(6) == 0);\n assert(func0(8) == 1);\n assert(func0(10) == 1);\n assert(func0(11) == 0);\n assert(func0(12) == 1);\n assert(func0(13) == 0);\n assert(func0(16) == 1);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov eax, [rbp+var_4]\nand eax, 1\ntest eax, eax\njnz short loc_116B\ncmp [rbp+var_4], 7\njle short loc_116B\nmov eax, 1\njmp short loc_1170\nloc_116B:\nmov eax, 0\nloc_1170:\npop rbp\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(int a1)\n{\n return (a1 & 1) == 0 && a1 > 7;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov eax, [rbp+var_4]\nand eax, 1\ntest eax, eax\njnz short loc_116B\ncmp [rbp+var_4], 7\njle short loc_116B\nmov eax, 1\njmp short loc_1170\nloc_116B:\nmov eax, 0\nloc_1170:\npop rbp\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1149(int a1)\n{\n return (a1 & 1) == 0 && a1 > 7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1149(int a1) { return (a1 & 1) == 0 && a1 > 7; }", + "ida_pseudo_norm": "uint8_t func0(int a1) { return (a1 & 1) == 0 && a1 > 7; }" + }, + { + "index": "HumanEval-C-139", + "func_name": "func0", + "func_dep": "#include \n", + "func": "long long func0(int n) {\n long long fact = 1, bfact = 1;\n for (int i = 1; i <= n; i++) {\n fact = fact * i;\n bfact = bfact * fact;\n }\n return bfact;\n}", + "test": "#include \n\nint main() {\n assert(func0(4) == 288);\n assert(func0(5) == 34560);\n assert(func0(7) == 125411328000);\n assert(func0(1) == 1);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_24], edi\nmov [rbp+var_10], 1\nmov [rbp+var_8], 1\nmov [rbp+var_14], 1\njmp short loc_118F\nloc_116D:\nmov eax, [rbp+var_14]\ncdqe\nmov rdx, [rbp+var_10]\nimul rax, rdx\nmov [rbp+var_10], rax\nmov rax, [rbp+var_8]\nimul rax, [rbp+var_10]\nmov [rbp+var_8], rax\nadd [rbp+var_14], 1\nloc_118F:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_24]\njle short loc_116D\nmov rax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int i; // [rsp+10h] [rbp-14h]\n __int64 v3; // [rsp+14h] [rbp-10h]\n __int64 v4; // [rsp+1Ch] [rbp-8h]\n\n v3 = 1LL;\n v4 = 1LL;\n for ( i = 1; i <= a1; ++i )\n {\n v3 *= i;\n v4 *= v3;\n }\n return v4;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_24], edi\nmov [rbp+var_10], 1\nmov [rbp+var_8], 1\nmov [rbp+var_14], 1\njmp short loc_118F\nloc_116D:\nmov eax, [rbp+var_14]\ncdqe\nmov rdx, [rbp+var_10]\nimul rax, rdx\nmov [rbp+var_10], rax\nmov rax, [rbp+var_8]\nimul rax, [rbp+var_10]\nmov [rbp+var_8], rax\nadd [rbp+var_14], 1\nloc_118F:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_24]\njle short loc_116D\nmov rax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int i; // [rsp+10h] [rbp-14h]\n __int64 v3; // [rsp+14h] [rbp-10h]\n __int64 v4; // [rsp+1Ch] [rbp-8h]\n\n v3 = 1LL;\n v4 = 1LL;\n for ( i = 1; i <= a1; ++i )\n {\n v3 *= i;\n v4 *= v3;\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int i;\n long long v3;\n long long v4;\n v3 = 1LL;\n v4 = 1LL;\n for (i = 1; i <= a1; ++i) {\n v3 *= i;\n v4 *= v3;\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int i;\n long long v3;\n long long v4;\n v3 = 1LL;\n v4 = 1LL;\n for (i = 1; i <= a1; ++i) {\n v3 *= i;\n v4 *= v3;\n }\n return v4;\n}" + }, + { + "index": "HumanEval-C-139", + "func_name": "func0", + "func_dep": "#include \n", + "func": "long long func0(int n) {\n long long fact = 1, bfact = 1;\n for (int i = 1; i <= n; i++) {\n fact = fact * i;\n bfact = bfact * fact;\n }\n return bfact;\n}", + "test": "#include \n\nint main() {\n assert(func0(4) == 288);\n assert(func0(5) == 34560);\n assert(func0(7) == 125411328000);\n assert(func0(1) == 1);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njle short loc_1178\nlea esi, [rdi+1]\nmov eax, 1\nmov ecx, 1\nmov edx, 1\nloc_1163:\nimul rdx, rax\nimul rcx, rdx\nadd rax, 1\ncmp rax, rsi\njnz short loc_1163\nloc_1174:\nmov rax, rcx\nretn\nloc_1178:\nmov ecx, 1\njmp short loc_1174", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n __int64 v1; // rax\n __int64 v2; // rcx\n __int64 v3; // rdx\n\n if ( a1 <= 0 )\n return 1LL;\n v1 = 1LL;\n v2 = 1LL;\n v3 = 1LL;\n do\n {\n v3 *= v1;\n v2 *= v3;\n ++v1;\n }\n while ( v1 != a1 + 1 );\n return v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ntest edi, edi\njle short loc_1178\nlea esi, [rdi+1]\nmov eax, 1\nmov ecx, 1\nmov edx, 1\nloc_1163:\nimul rdx, rax\nimul rcx, rdx\nadd rax, 1\ncmp rax, rsi\njnz short loc_1163\nloc_1174:\nmov rax, rcx\nretn\nloc_1178:\nmov ecx, 1\njmp short loc_1174", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n __int64 v1; // rax\n __int64 v2; // rcx\n __int64 v3; // rdx\n\n if ( a1 <= 0 )\n return 1LL;\n v1 = 1LL;\n v2 = 1LL;\n v3 = 1LL;\n do\n {\n v3 *= v1;\n v2 *= v3;\n ++v1;\n }\n while ( v1 != a1 + 1 );\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n long long v1;\n long long v2;\n long long v3;\n if (a1 <= 0) return 1LL;\n v1 = 1LL;\n v2 = 1LL;\n v3 = 1LL;\n do {\n v3 *= v1;\n v2 *= v3;\n ++v1;\n } while (v1 != a1 + 1);\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n long long v1;\n long long v2;\n long long v3;\n if (a1 <= 0) return 1LL;\n v1 = 1LL;\n v2 = 1LL;\n v3 = 1LL;\n do {\n v3 *= v1;\n v2 *= v3;\n ++v1;\n } while (v1 != a1 + 1);\n return v2;\n}" + }, + { + "index": "HumanEval-C-140", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(const char *text, char *out) {\n int space_len = 0;\n int j = 0;\n for (int i = 0; i < strlen(text); i++) {\n if (text[i] == ' ') {\n space_len++;\n } else {\n if (space_len == 1) out[j++] = '_';\n if (space_len == 2) out[j++] = '_', out[j++] = '_';\n if (space_len > 2) out[j++] = '-';\n space_len = 0;\n out[j++] = text[i];\n }\n }\n if (space_len == 1) out[j++] = '_';\n if (space_len == 2) out[j++] = '_', out[j++] = '_';\n if (space_len > 2) out[j++] = '-';\n out[j] = '\\0';\n}", + "test": "#include \n#include \n\nint main() {\n char output[100];\n\n func0(\"Example\", output);\n assert(strcmp(output, \"Example\") == 0);\n\n func0(\"Mudasir Hanif \", output);\n assert(strcmp(output, \"Mudasir_Hanif_\") == 0);\n\n func0(\"Yellow Yellow Dirty Fellow\", output);\n assert(strcmp(output, \"Yellow_Yellow__Dirty__Fellow\") == 0);\n\n func0(\"Exa mple\", output);\n assert(strcmp(output, \"Exa-mple\") == 0);\n\n func0(\" Exa 1 2 2 mple\", output);\n assert(strcmp(output, \"-Exa_1_2_2_mple\") == 0);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+s], rdi\nmov [rbp+var_30], rsi\nmov [rbp+var_1C], 0\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp loc_1290\nloc_11D8:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njnz short loc_11F5\nadd [rbp+var_1C], 1\njmp loc_128C\nloc_11F5:\ncmp [rbp+var_1C], 1\njnz short loc_1211\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov byte ptr [rax], 5Fh ; '_'\nloc_1211:\ncmp [rbp+var_1C], 2\njnz short loc_1243\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov byte ptr [rax], 5Fh ; '_'\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov byte ptr [rax], 5Fh ; '_'\nloc_1243:\ncmp [rbp+var_1C], 2\njle short loc_125F\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov byte ptr [rax], 2Dh ; '-'\nloc_125F:\nmov [rbp+var_1C], 0\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rdx, rax\nmovzx eax, byte ptr [rcx]\nmov [rdx], al\nloc_128C:\nadd [rbp+var_14], 1\nloc_1290:\nmov eax, [rbp+var_14]\nmovsxd rbx, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rbx, rax\njb loc_11D8\ncmp [rbp+var_1C], 1\njnz short loc_12C7\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov byte ptr [rax], 5Fh ; '_'\nloc_12C7:\ncmp [rbp+var_1C], 2\njnz short loc_12F9\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov byte ptr [rax], 5Fh ; '_'\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov byte ptr [rax], 5Fh ; '_'\nloc_12F9:\ncmp [rbp+var_1C], 2\njle short loc_1315\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov byte ptr [rax], 2Dh ; '-'\nloc_1315:\nmov eax, [rbp+var_18]\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov byte ptr [rax], 0\nnop\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1, __int64 a2)\n{\n int v2; // eax\n int v3; // eax\n int v4; // eax\n int v5; // eax\n int v6; // eax\n int v7; // eax\n int v8; // eax\n _BYTE *result; // rax\n int v10; // [rsp+14h] [rbp-1Ch]\n int v11; // [rsp+18h] [rbp-18h]\n int i; // [rsp+1Ch] [rbp-14h]\n\n v10 = 0;\n v11 = 0;\n for ( i = 0; i < strlen(a1); ++i )\n {\n if ( a1[i] == 32 )\n {\n ++v10;\n }\n else\n {\n if ( v10 == 1 )\n {\n v2 = v11++;\n *(_BYTE *)(v2 + a2) = 95;\n }\n if ( v10 == 2 )\n {\n *(_BYTE *)(v11 + a2) = 95;\n v3 = v11 + 1;\n v11 += 2;\n *(_BYTE *)(v3 + a2) = 95;\n }\n if ( v10 > 2 )\n {\n v4 = v11++;\n *(_BYTE *)(v4 + a2) = 45;\n }\n v10 = 0;\n v5 = v11++;\n *(_BYTE *)(a2 + v5) = a1[i];\n }\n }\n if ( v10 == 1 )\n {\n v6 = v11++;\n *(_BYTE *)(v6 + a2) = 95;\n }\n if ( v10 == 2 )\n {\n *(_BYTE *)(v11 + a2) = 95;\n v7 = v11 + 1;\n v11 += 2;\n *(_BYTE *)(v7 + a2) = 95;\n }\n if ( v10 > 2 )\n {\n v8 = v11++;\n *(_BYTE *)(v8 + a2) = 45;\n }\n result = (_BYTE *)(v11 + a2);\n *result = 0;\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+s], rdi\nmov [rbp+var_30], rsi\nmov [rbp+var_1C], 0\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp loc_1290\nloc_11D8:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njnz short loc_11F5\nadd [rbp+var_1C], 1\njmp loc_128C\nloc_11F5:\ncmp [rbp+var_1C], 1\njnz short loc_1211\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov byte ptr [rax], 5Fh ; '_'\nloc_1211:\ncmp [rbp+var_1C], 2\njnz short loc_1243\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov byte ptr [rax], 5Fh ; '_'\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov byte ptr [rax], 5Fh ; '_'\nloc_1243:\ncmp [rbp+var_1C], 2\njle short loc_125F\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov byte ptr [rax], 2Dh ; '-'\nloc_125F:\nmov [rbp+var_1C], 0\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rdx, rax\nmovzx eax, byte ptr [rcx]\nmov [rdx], al\nloc_128C:\nadd [rbp+var_14], 1\nloc_1290:\nmov eax, [rbp+var_14]\nmovsxd rbx, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rbx, rax\njb loc_11D8\ncmp [rbp+var_1C], 1\njnz short loc_12C7\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov byte ptr [rax], 5Fh ; '_'\nloc_12C7:\ncmp [rbp+var_1C], 2\njnz short loc_12F9\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov byte ptr [rax], 5Fh ; '_'\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov byte ptr [rax], 5Fh ; '_'\nloc_12F9:\ncmp [rbp+var_1C], 2\njle short loc_1315\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov byte ptr [rax], 2Dh ; '-'\nloc_1315:\nmov eax, [rbp+var_18]\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov byte ptr [rax], 0\nnop\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_11A9(const char *a1, __int64 a2)\n{\n int v2; // eax\n int v3; // eax\n int v4; // eax\n int v5; // eax\n int v6; // eax\n int v7; // eax\n int v8; // eax\n _BYTE *result; // rax\n int v10; // [rsp+14h] [rbp-1Ch]\n int v11; // [rsp+18h] [rbp-18h]\n int i; // [rsp+1Ch] [rbp-14h]\n\n v10 = 0;\n v11 = 0;\n for ( i = 0; i < strlen(a1); ++i )\n {\n if ( a1[i] == 32 )\n {\n ++v10;\n }\n else\n {\n if ( v10 == 1 )\n {\n v2 = v11++;\n *(_BYTE *)(v2 + a2) = 95;\n }\n if ( v10 == 2 )\n {\n *(_BYTE *)(v11 + a2) = 95;\n v3 = v11 + 1;\n v11 += 2;\n *(_BYTE *)(v3 + a2) = 95;\n }\n if ( v10 > 2 )\n {\n v4 = v11++;\n *(_BYTE *)(v4 + a2) = 45;\n }\n v10 = 0;\n v5 = v11++;\n *(_BYTE *)(a2 + v5) = a1[i];\n }\n }\n if ( v10 == 1 )\n {\n v6 = v11++;\n *(_BYTE *)(v6 + a2) = 95;\n }\n if ( v10 == 2 )\n {\n *(_BYTE *)(v11 + a2) = 95;\n v7 = v11 + 1;\n v11 += 2;\n *(_BYTE *)(v7 + a2) = 95;\n }\n if ( v10 > 2 )\n {\n v8 = v11++;\n *(_BYTE *)(v8 + a2) = 45;\n }\n result = (_BYTE *)(v11 + a2);\n *result = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_11A9(const char *a1, long long a2) {\n int v2;\n int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n int v8;\n uint8_t *result;\n int v10;\n int v11;\n int i;\n v10 = 0;\n v11 = 0;\n for (i = 0; i < strlen(a1); ++i) {\n if (a1[i] == 32) {\n ++v10;\n } else {\n if (v10 == 1) {\n v2 = v11++;\n *(uint8_t *)(v2 + a2) = 95;\n }\n if (v10 == 2) {\n *(uint8_t *)(v11 + a2) = 95;\n v3 = v11 + 1;\n v11 += 2;\n *(uint8_t *)(v3 + a2) = 95;\n }\n if (v10 > 2) {\n v4 = v11++;\n *(uint8_t *)(v4 + a2) = 45;\n }\n v10 = 0;\n v5 = v11++;\n *(uint8_t *)(a2 + v5) = a1[i];\n }\n }\n if (v10 == 1) {\n v6 = v11++;\n *(uint8_t *)(v6 + a2) = 95;\n }\n if (v10 == 2) {\n *(uint8_t *)(v11 + a2) = 95;\n v7 = v11 + 1;\n v11 += 2;\n *(uint8_t *)(v7 + a2) = 95;\n }\n if (v10 > 2) {\n v8 = v11++;\n *(uint8_t *)(v8 + a2) = 45;\n }\n result = (uint8_t *)(v11 + a2);\n *result = 0;\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1, long long a2) {\n int v2;\n int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n int v8;\n uint8_t *result;\n int v10;\n int v11;\n int i;\n v10 = 0;\n v11 = 0;\n for (i = 0; i < strlen(a1); ++i) {\n if (a1[i] == 32) {\n ++v10;\n } else {\n if (v10 == 1) {\n v2 = v11++;\n *(uint8_t *)(v2 + a2) = 95;\n }\n if (v10 == 2) {\n *(uint8_t *)(v11 + a2) = 95;\n v3 = v11 + 1;\n v11 += 2;\n *(uint8_t *)(v3 + a2) = 95;\n }\n if (v10 > 2) {\n v4 = v11++;\n *(uint8_t *)(v4 + a2) = 45;\n }\n v10 = 0;\n v5 = v11++;\n *(uint8_t *)(a2 + v5) = a1[i];\n }\n }\n if (v10 == 1) {\n v6 = v11++;\n *(uint8_t *)(v6 + a2) = 95;\n }\n if (v10 == 2) {\n *(uint8_t *)(v11 + a2) = 95;\n v7 = v11 + 1;\n v11 += 2;\n *(uint8_t *)(v7 + a2) = 95;\n }\n if (v10 > 2) {\n v8 = v11++;\n *(uint8_t *)(v8 + a2) = 45;\n }\n result = (uint8_t *)(v11 + a2);\n *result = 0;\n return result;\n}" + }, + { + "index": "HumanEval-C-140", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(const char *text, char *out) {\n int space_len = 0;\n int j = 0;\n for (int i = 0; i < strlen(text); i++) {\n if (text[i] == ' ') {\n space_len++;\n } else {\n if (space_len == 1) out[j++] = '_';\n if (space_len == 2) out[j++] = '_', out[j++] = '_';\n if (space_len > 2) out[j++] = '-';\n space_len = 0;\n out[j++] = text[i];\n }\n }\n if (space_len == 1) out[j++] = '_';\n if (space_len == 2) out[j++] = '_', out[j++] = '_';\n if (space_len > 2) out[j++] = '-';\n out[j] = '\\0';\n}", + "test": "#include \n#include \n\nint main() {\n char output[100];\n\n func0(\"Example\", output);\n assert(strcmp(output, \"Example\") == 0);\n\n func0(\"Mudasir Hanif \", output);\n assert(strcmp(output, \"Mudasir_Hanif_\") == 0);\n\n func0(\"Yellow Yellow Dirty Fellow\", output);\n assert(strcmp(output, \"Yellow_Yellow__Dirty__Fellow\") == 0);\n\n func0(\"Exa mple\", output);\n assert(strcmp(output, \"Exa-mple\") == 0);\n\n func0(\" Exa 1 2 2 mple\", output);\n assert(strcmp(output, \"-Exa_1_2_2_mple\") == 0);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r12, rdi\nmov r13, rsi\nmov ebp, 0\nmov ebx, 0\nmov r14d, 0\njmp short loc_1208\nloc_11CD:\nadd r14d, 1\njmp short loc_1204\nloc_11D3:\nlea eax, [rbx+1]\nmovsxd rbx, ebx\nmov byte ptr [r13+rbx+0], 5Fh ; '_'\njmp short loc_11EF\nloc_11E1:\njle short loc_1242\nlea eax, [rbx+1]\nmovsxd rbx, ebx\nmov byte ptr [r13+rbx+0], 2Dh ; '-'\nloc_11EF:\nlea ebx, [rax+1]\nmovzx edx, byte ptr [r12+rbp]\ncdqe\nmov [r13+rax+0], dl\nmov r14d, 0\nloc_1204:\nadd rbp, 1\nloc_1208:\nmov rdi, r12; s\ncall _strlen\ncmp rbp, rax\njnb short loc_1246\ncmp byte ptr [r12+rbp], 20h ; ' '\njz short loc_11CD\ncmp r14d, 1\njz short loc_11D3\ncmp r14d, 2\njnz short loc_11E1\nmovsxd rax, ebx\nmov byte ptr [r13+rax+0], 5Fh ; '_'\nlea eax, [rbx+2]\nadd ebx, 1\nmovsxd rbx, ebx\nmov byte ptr [r13+rbx+0], 5Fh ; '_'\njmp short loc_11EF\nloc_1242:\nmov eax, ebx\njmp short loc_11EF\nloc_1246:\ncmp r14d, 1\njz short loc_126C\ncmp r14d, 2\njnz short loc_127A\nmovsxd rax, ebx\nmov byte ptr [r13+rax+0], 5Fh ; '_'\nlea eax, [rbx+2]\nadd ebx, 1\nmovsxd rbx, ebx\nmov byte ptr [r13+rbx+0], 5Fh ; '_'\njmp short loc_1288\nloc_126C:\nlea eax, [rbx+1]\nmovsxd rbx, ebx\nmov byte ptr [r13+rbx+0], 5Fh ; '_'\njmp short loc_1288\nloc_127A:\njle short loc_1299\nlea eax, [rbx+1]\nmovsxd rbx, ebx\nmov byte ptr [r13+rbx+0], 2Dh ; '-'\nloc_1288:\ncdqe\nmov byte ptr [r13+rax+0], 0\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1299:\nmov eax, ebx\njmp short loc_1288", + "ida_pseudo": "__int64 __fastcall func0(char *s, __int64 a2)\n{\n size_t v2; // rbp\n int v3; // ebx\n int v4; // r14d\n int v5; // eax\n __int64 result; // rax\n\n v2 = 0LL;\n v3 = 0;\n v4 = 0;\n while ( v2 < strlen(s) )\n {\n if ( s[v2] == 32 )\n {\n ++v4;\n }\n else\n {\n if ( v4 == 1 )\n {\n v5 = v3 + 1;\n *(_BYTE *)(a2 + v3) = 95;\n }\n else if ( v4 == 2 )\n {\n *(_BYTE *)(a2 + v3) = 95;\n v5 = v3 + 2;\n *(_BYTE *)(a2 + v3 + 1) = 95;\n }\n else if ( v4 <= 2 )\n {\n v5 = v3;\n }\n else\n {\n v5 = v3 + 1;\n *(_BYTE *)(a2 + v3) = 45;\n }\n v3 = v5 + 1;\n *(_BYTE *)(a2 + v5) = s[v2];\n v4 = 0;\n }\n ++v2;\n }\n if ( v4 == 1 )\n {\n LODWORD(result) = v3 + 1;\n *(_BYTE *)(a2 + v3) = 95;\n }\n else if ( v4 == 2 )\n {\n *(_BYTE *)(a2 + v3) = 95;\n LODWORD(result) = v3 + 2;\n *(_BYTE *)(a2 + v3 + 1) = 95;\n }\n else if ( v4 <= 2 )\n {\n LODWORD(result) = v3;\n }\n else\n {\n LODWORD(result) = v3 + 1;\n *(_BYTE *)(a2 + v3) = 45;\n }\n result = (int)result;\n *(_BYTE *)(a2 + (int)result) = 0;\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r12, rdi\nmov r13, rsi\nmov ebp, 0\nmov ebx, 0\nmov r14d, 0\njmp short loc_1208\nloc_11CD:\nadd r14d, 1\njmp short loc_1204\nloc_11D3:\nlea eax, [rbx+1]\nmovsxd rbx, ebx\nmov byte ptr [r13+rbx+0], 5Fh ; '_'\njmp short loc_11EF\nloc_11E1:\njle short loc_1242\nlea eax, [rbx+1]\nmovsxd rbx, ebx\nmov byte ptr [r13+rbx+0], 2Dh ; '-'\nloc_11EF:\nlea ebx, [rax+1]\nmovzx edx, byte ptr [r12+rbp]\ncdqe\nmov [r13+rax+0], dl\nmov r14d, 0\nloc_1204:\nadd rbp, 1\nloc_1208:\nmov rdi, r12; s\ncall _strlen\ncmp rbp, rax\njnb short loc_1246\ncmp byte ptr [r12+rbp], 20h ; ' '\njz short loc_11CD\ncmp r14d, 1\njz short loc_11D3\ncmp r14d, 2\njnz short loc_11E1\nmovsxd rax, ebx\nmov byte ptr [r13+rax+0], 5Fh ; '_'\nlea eax, [rbx+2]\nadd ebx, 1\nmovsxd rbx, ebx\nmov byte ptr [r13+rbx+0], 5Fh ; '_'\njmp short loc_11EF\nloc_1242:\nmov eax, ebx\njmp short loc_11EF\nloc_1246:\ncmp r14d, 1\njz short loc_126C\ncmp r14d, 2\njnz short loc_127A\nmovsxd rax, ebx\nmov byte ptr [r13+rax+0], 5Fh ; '_'\nlea eax, [rbx+2]\nadd ebx, 1\nmovsxd rbx, ebx\nmov byte ptr [r13+rbx+0], 5Fh ; '_'\njmp short loc_1288\nloc_126C:\nlea eax, [rbx+1]\nmovsxd rbx, ebx\nmov byte ptr [r13+rbx+0], 5Fh ; '_'\njmp short loc_1288\nloc_127A:\njle short loc_1299\nlea eax, [rbx+1]\nmovsxd rbx, ebx\nmov byte ptr [r13+rbx+0], 2Dh ; '-'\nloc_1288:\ncdqe\nmov byte ptr [r13+rax+0], 0\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1299:\nmov eax, ebx\njmp short loc_1288", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(char *s, __int64 a2)\n{\n size_t v2; // rbp\n int v3; // ebx\n int v4; // r14d\n int v5; // eax\n __int64 result; // rax\n\n v2 = 0LL;\n v3 = 0;\n v4 = 0;\n while ( v2 < strlen(s) )\n {\n if ( s[v2] == 32 )\n {\n ++v4;\n }\n else\n {\n if ( v4 == 1 )\n {\n v5 = v3 + 1;\n *(_BYTE *)(a2 + v3) = 95;\n }\n else if ( v4 == 2 )\n {\n *(_BYTE *)(a2 + v3) = 95;\n v5 = v3 + 2;\n *(_BYTE *)(a2 + v3 + 1) = 95;\n }\n else if ( v4 <= 2 )\n {\n v5 = v3;\n }\n else\n {\n v5 = v3 + 1;\n *(_BYTE *)(a2 + v3) = 45;\n }\n v3 = v5 + 1;\n *(_BYTE *)(a2 + v5) = s[v2];\n v4 = 0;\n }\n ++v2;\n }\n if ( v4 == 1 )\n {\n LODWORD(result) = v3 + 1;\n *(_BYTE *)(a2 + v3) = 95;\n }\n else if ( v4 == 2 )\n {\n *(_BYTE *)(a2 + v3) = 95;\n LODWORD(result) = v3 + 2;\n *(_BYTE *)(a2 + v3 + 1) = 95;\n }\n else if ( v4 <= 2 )\n {\n LODWORD(result) = v3;\n }\n else\n {\n LODWORD(result) = v3 + 1;\n *(_BYTE *)(a2 + v3) = 45;\n }\n result = (int)result;\n *(_BYTE *)(a2 + (int)result) = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(char *s, long long a2) {\n unsigned int v2;\n int v3;\n int v4;\n int v5;\n long long result;\n v2 = 0LL;\n v3 = 0;\n v4 = 0;\n while (v2 < strlen(s)) {\n if (s[v2] == 32) {\n ++v4;\n } else {\n if (v4 == 1) {\n v5 = v3 + 1;\n *(uint8_t *)(a2 + v3) = 95;\n } else if (v4 == 2) {\n *(uint8_t *)(a2 + v3) = 95;\n v5 = v3 + 2;\n *(uint8_t *)(a2 + v3 + 1) = 95;\n } else if (v4 <= 2) {\n v5 = v3;\n } else {\n v5 = v3 + 1;\n *(uint8_t *)(a2 + v3) = 45;\n }\n v3 = v5 + 1;\n *(uint8_t *)(a2 + v5) = s[v2];\n v4 = 0;\n }\n ++v2;\n }\n if (v4 == 1) {\n LODWORD(result) = v3 + 1;\n *(uint8_t *)(a2 + v3) = 95;\n } else if (v4 == 2) {\n *(uint8_t *)(a2 + v3) = 95;\n LODWORD(result) = v3 + 2;\n *(uint8_t *)(a2 + v3 + 1) = 95;\n } else if (v4 <= 2) {\n LODWORD(result) = v3;\n } else {\n LODWORD(result) = v3 + 1;\n *(uint8_t *)(a2 + v3) = 45;\n }\n result = (int)result;\n *(uint8_t *)(a2 + (int)result) = 0;\n return result;\n}", + "ida_pseudo_norm": "long long func0(char *s, long long a2) {\n unsigned int v2;\n int v3;\n int v4;\n int v5;\n long long result;\n v2 = 0LL;\n v3 = 0;\n v4 = 0;\n while (v2 < strlen(s)) {\n if (s[v2] == 32) {\n ++v4;\n } else {\n if (v4 == 1) {\n v5 = v3 + 1;\n *(uint8_t *)(a2 + v3) = 95;\n } else if (v4 == 2) {\n *(uint8_t *)(a2 + v3) = 95;\n v5 = v3 + 2;\n *(uint8_t *)(a2 + v3 + 1) = 95;\n } else if (v4 <= 2) {\n v5 = v3;\n } else {\n v5 = v3 + 1;\n *(uint8_t *)(a2 + v3) = 45;\n }\n v3 = v5 + 1;\n *(uint8_t *)(a2 + v5) = s[v2];\n v4 = 0;\n }\n ++v2;\n }\n if (v4 == 1) {\n LODWORD(result) = v3 + 1;\n *(uint8_t *)(a2 + v3) = 95;\n } else if (v4 == 2) {\n *(uint8_t *)(a2 + v3) = 95;\n LODWORD(result) = v3 + 2;\n *(uint8_t *)(a2 + v3 + 1) = 95;\n } else if (v4 <= 2) {\n LODWORD(result) = v3;\n } else {\n LODWORD(result) = v3 + 1;\n *(uint8_t *)(a2 + v3) = 45;\n }\n result = (int)result;\n *(uint8_t *)(a2 + (int)result) = 0;\n return result;\n}" + }, + { + "index": "HumanEval-C-140", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(const char *text, char *out) {\n int space_len = 0;\n int j = 0;\n for (int i = 0; i < strlen(text); i++) {\n if (text[i] == ' ') {\n space_len++;\n } else {\n if (space_len == 1) out[j++] = '_';\n if (space_len == 2) out[j++] = '_', out[j++] = '_';\n if (space_len > 2) out[j++] = '-';\n space_len = 0;\n out[j++] = text[i];\n }\n }\n if (space_len == 1) out[j++] = '_';\n if (space_len == 2) out[j++] = '_', out[j++] = '_';\n if (space_len > 2) out[j++] = '-';\n out[j] = '\\0';\n}", + "test": "#include \n#include \n\nint main() {\n char output[100];\n\n func0(\"Example\", output);\n assert(strcmp(output, \"Example\") == 0);\n\n func0(\"Mudasir Hanif \", output);\n assert(strcmp(output, \"Mudasir_Hanif_\") == 0);\n\n func0(\"Yellow Yellow Dirty Fellow\", output);\n assert(strcmp(output, \"Yellow_Yellow__Dirty__Fellow\") == 0);\n\n func0(\"Exa mple\", output);\n assert(strcmp(output, \"Exa-mple\") == 0);\n\n func0(\" Exa 1 2 2 mple\", output);\n assert(strcmp(output, \"-Exa_1_2_2_mple\") == 0);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\nxor r15d, r15d\npush r14\nxor r14d, r14d\npush r13\nmov r13, rdi\npush r12\nxor r12d, r12d\npush rbp\nmov rbp, rsi\npush rbx\nxor ebx, ebx\nsub rsp, 8\njmp short loc_13C0\nloc_1388:\nlea eax, [r15+1]\ncmp r12d, 1\njz short loc_13E8\ncmp r12d, 2\njnz short loc_13F8\nmovzx ecx, cs:word_2194\nlea eax, [r15+2]\nmov [rsi], cx\nmovzx edx, byte ptr [r13+rbx+0]\nloc_13AC:\nlea r15d, [rax+1]\ncdqe\nxor r12d, r12d\nmov [rbp+rax+0], dl\nmovsxd r14, r15d\nloc_13BC:\nadd rbx, 1\nloc_13C0:\nmov rdi, r13; s\ncall _strlen\nlea rsi, [rbp+r14+0]\ncmp rbx, rax\njnb short loc_1408\nmovzx edx, byte ptr [r13+rbx+0]\ncmp dl, 20h ; ' '\njnz short loc_1388\nadd r12d, 1\njmp short loc_13BC\nloc_13E8:\nmov byte ptr [rsi], 5Fh ; '_'\nmovzx edx, byte ptr [r13+rbx+0]\njmp short loc_13AC\nloc_13F8:\njle short loc_1460\nmov byte ptr [rsi], 2Dh ; '-'\nmovzx edx, byte ptr [r13+rbx+0]\njmp short loc_13AC\nloc_1408:\ncmp r12d, 1\njz short loc_1450\ncmp r12d, 2\njz short loc_1438\njle short loc_1420\nmov byte ptr [rsi], 2Dh ; '-'\nadd r15d, 1\nmovsxd r14, r15d\nloc_1420:\nmov byte ptr [rbp+r14+0], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1438:\nlea eax, [r15+1]\nadd r15d, 2\nmov byte ptr [rsi], 5Fh ; '_'\ncdqe\nmovsxd r14, r15d\nmov byte ptr [rbp+rax+0], 5Fh ; '_'\njmp short loc_1420\nloc_1450:\nadd r15d, 1\nmov byte ptr [rsi], 5Fh ; '_'\nmovsxd r14, r15d\njmp short loc_1420\nloc_1460:\nmov eax, r15d\njmp loc_13AC", + "ida_pseudo": "size_t __fastcall func0(char *s, __int64 a2)\n{\n int v2; // r15d\n __int64 v3; // r14\n int v4; // r12d\n unsigned __int64 i; // rbx\n int v7; // eax\n char v8; // dl\n size_t result; // rax\n _BYTE *v10; // rsi\n\n v2 = 0;\n v3 = 0LL;\n v4 = 0;\n for ( i = 0LL; ; ++i )\n {\n result = strlen(s);\n v10 = (_BYTE *)(a2 + v3);\n if ( i >= result )\n break;\n v8 = s[i];\n if ( v8 == 32 )\n {\n ++v4;\n }\n else\n {\n v7 = v2 + 1;\n if ( v4 == 1 )\n {\n *v10 = 95;\n v8 = s[i];\n }\n else if ( v4 == 2 )\n {\n v7 = v2 + 2;\n *(_WORD *)v10 = 24415;\n v8 = s[i];\n }\n else if ( v4 <= 2 )\n {\n v7 = v2;\n }\n else\n {\n *v10 = 45;\n v8 = s[i];\n }\n v2 = v7 + 1;\n v4 = 0;\n *(_BYTE *)(a2 + v7) = v8;\n v3 = v7 + 1;\n }\n }\n if ( v4 == 1 )\n {\n *v10 = 95;\n v3 = v2 + 1;\n }\n else if ( v4 == 2 )\n {\n *v10 = 95;\n result = v2 + 1;\n v3 = v2 + 2;\n *(_BYTE *)(a2 + (int)result) = 95;\n }\n else if ( v4 > 2 )\n {\n *v10 = 45;\n v3 = v2 + 1;\n }\n *(_BYTE *)(a2 + v3) = 0;\n return result;\n}", + "ida_strip_asm": "sub_1360:\nendbr64\npush r15\nxor r15d, r15d\npush r14\nxor r14d, r14d\npush r13\nmov r13, rdi\npush r12\nxor r12d, r12d\npush rbp\nmov rbp, rsi\npush rbx\nxor ebx, ebx\nsub rsp, 8\njmp short loc_13C0\nloc_1388:\nlea eax, [r15+1]\ncmp r12d, 1\njz short loc_13E8\ncmp r12d, 2\njnz short loc_13F8\nmovzx ecx, cs:word_2194\nlea eax, [r15+2]\nmov [rsi], cx\nmovzx edx, byte ptr [r13+rbx+0]\nloc_13AC:\nlea r15d, [rax+1]\ncdqe\nxor r12d, r12d\nmov [rbp+rax+0], dl\nmovsxd r14, r15d\nloc_13BC:\nadd rbx, 1\nloc_13C0:\nmov rdi, r13; s\ncall _strlen\nlea rsi, [rbp+r14+0]\ncmp rbx, rax\njnb short loc_1408\nmovzx edx, byte ptr [r13+rbx+0]\ncmp dl, 20h ; ' '\njnz short loc_1388\nadd r12d, 1\njmp short loc_13BC\nloc_13E8:\nmov byte ptr [rsi], 5Fh ; '_'\nmovzx edx, byte ptr [r13+rbx+0]\njmp short loc_13AC\nloc_13F8:\njle short loc_1460\nmov byte ptr [rsi], 2Dh ; '-'\nmovzx edx, byte ptr [r13+rbx+0]\njmp short loc_13AC\nloc_1408:\ncmp r12d, 1\njz short loc_1450\ncmp r12d, 2\njz short loc_1438\njle short loc_1420\nmov byte ptr [rsi], 2Dh ; '-'\nadd r15d, 1\nmovsxd r14, r15d\nloc_1420:\nmov byte ptr [rbp+r14+0], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1438:\nlea eax, [r15+1]\nadd r15d, 2\nmov byte ptr [rsi], 5Fh ; '_'\ncdqe\nmovsxd r14, r15d\nmov byte ptr [rbp+rax+0], 5Fh ; '_'\njmp short loc_1420\nloc_1450:\nadd r15d, 1\nmov byte ptr [rsi], 5Fh ; '_'\nmovsxd r14, r15d\njmp short loc_1420\nloc_1460:\nmov eax, r15d\njmp loc_13AC", + "ida_strip_pseudo": "size_t __fastcall sub_1360(char *s, __int64 a2)\n{\n int v2; // r15d\n __int64 v3; // r14\n int v4; // r12d\n unsigned __int64 i; // rbx\n int v7; // eax\n char v8; // dl\n size_t result; // rax\n _BYTE *v10; // rsi\n\n v2 = 0;\n v3 = 0LL;\n v4 = 0;\n for ( i = 0LL; ; ++i )\n {\n result = strlen(s);\n v10 = (_BYTE *)(a2 + v3);\n if ( i >= result )\n break;\n v8 = s[i];\n if ( v8 == 32 )\n {\n ++v4;\n }\n else\n {\n v7 = v2 + 1;\n if ( v4 == 1 )\n {\n *v10 = 95;\n v8 = s[i];\n }\n else if ( v4 == 2 )\n {\n v7 = v2 + 2;\n *(_WORD *)v10 = 24415;\n v8 = s[i];\n }\n else if ( v4 <= 2 )\n {\n v7 = v2;\n }\n else\n {\n *v10 = 45;\n v8 = s[i];\n }\n v2 = v7 + 1;\n v4 = 0;\n *(_BYTE *)(a2 + v7) = v8;\n v3 = v7 + 1;\n }\n }\n if ( v4 == 1 )\n {\n *v10 = 95;\n v3 = v2 + 1;\n }\n else if ( v4 == 2 )\n {\n *v10 = 95;\n result = v2 + 1;\n v3 = v2 + 2;\n *(_BYTE *)(a2 + (int)result) = 95;\n }\n else if ( v4 > 2 )\n {\n *v10 = 45;\n v3 = v2 + 1;\n }\n *(_BYTE *)(a2 + v3) = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned int sub_1360(char *s, long long a2) {\n int v2;\n long long v3;\n int v4;\n unsigned long long i;\n int v7;\n char v8;\n unsigned int result;\n uint8_t *v10;\n v2 = 0;\n v3 = 0LL;\n v4 = 0;\n for (i = 0LL;; ++i) {\n result = strlen(s);\n v10 = (uint8_t *)(a2 + v3);\n if (i >= result) break;\n v8 = s[i];\n if (v8 == 32) {\n ++v4;\n } else {\n v7 = v2 + 1;\n if (v4 == 1) {\n *v10 = 95;\n v8 = s[i];\n } else if (v4 == 2) {\n v7 = v2 + 2;\n *(unsigned short *)v10 = 24415;\n v8 = s[i];\n } else if (v4 <= 2) {\n v7 = v2;\n } else {\n *v10 = 45;\n v8 = s[i];\n }\n v2 = v7 + 1;\n v4 = 0;\n *(uint8_t *)(a2 + v7) = v8;\n v3 = v7 + 1;\n }\n }\n if (v4 == 1) {\n *v10 = 95;\n v3 = v2 + 1;\n } else if (v4 == 2) {\n *v10 = 95;\n result = v2 + 1;\n v3 = v2 + 2;\n *(uint8_t *)(a2 + (int)result) = 95;\n } else if (v4 > 2) {\n *v10 = 45;\n v3 = v2 + 1;\n }\n *(uint8_t *)(a2 + v3) = 0;\n return result;\n}", + "ida_pseudo_norm": "unsigned int func0(char *s, long long a2) {\n int v2;\n long long v3;\n int v4;\n unsigned long long i;\n int v7;\n char v8;\n unsigned int result;\n uint8_t *v10;\n v2 = 0;\n v3 = 0LL;\n v4 = 0;\n for (i = 0LL;; ++i) {\n result = strlen(s);\n v10 = (uint8_t *)(a2 + v3);\n if (i >= result) break;\n v8 = s[i];\n if (v8 == 32) {\n ++v4;\n } else {\n v7 = v2 + 1;\n if (v4 == 1) {\n *v10 = 95;\n v8 = s[i];\n } else if (v4 == 2) {\n v7 = v2 + 2;\n *(unsigned short *)v10 = 24415;\n v8 = s[i];\n } else if (v4 <= 2) {\n v7 = v2;\n } else {\n *v10 = 45;\n v8 = s[i];\n }\n v2 = v7 + 1;\n v4 = 0;\n *(uint8_t *)(a2 + v7) = v8;\n v3 = v7 + 1;\n }\n }\n if (v4 == 1) {\n *v10 = 95;\n v3 = v2 + 1;\n } else if (v4 == 2) {\n *v10 = 95;\n result = v2 + 1;\n v3 = v2 + 2;\n *(uint8_t *)(a2 + (int)result) = 95;\n } else if (v4 > 2) {\n *v10 = 45;\n v3 = v2 + 1;\n }\n *(uint8_t *)(a2 + v3) = 0;\n return result;\n}" + }, + { + "index": "HumanEval-C-140", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(const char *text, char *out) {\n int space_len = 0;\n int j = 0;\n for (int i = 0; i < strlen(text); i++) {\n if (text[i] == ' ') {\n space_len++;\n } else {\n if (space_len == 1) out[j++] = '_';\n if (space_len == 2) out[j++] = '_', out[j++] = '_';\n if (space_len > 2) out[j++] = '-';\n space_len = 0;\n out[j++] = text[i];\n }\n }\n if (space_len == 1) out[j++] = '_';\n if (space_len == 2) out[j++] = '_', out[j++] = '_';\n if (space_len > 2) out[j++] = '-';\n out[j] = '\\0';\n}", + "test": "#include \n#include \n\nint main() {\n char output[100];\n\n func0(\"Example\", output);\n assert(strcmp(output, \"Example\") == 0);\n\n func0(\"Mudasir Hanif \", output);\n assert(strcmp(output, \"Mudasir_Hanif_\") == 0);\n\n func0(\"Yellow Yellow Dirty Fellow\", output);\n assert(strcmp(output, \"Yellow_Yellow__Dirty__Fellow\") == 0);\n\n func0(\"Exa mple\", output);\n assert(strcmp(output, \"Exa-mple\") == 0);\n\n func0(\" Exa 1 2 2 mple\", output);\n assert(strcmp(output, \"-Exa_1_2_2_mple\") == 0);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\nxor r15d, r15d\npush r14\nxor r14d, r14d\npush r13\nmov r13, rdi\npush r12\nxor r12d, r12d\npush rbp\nmov rbp, rsi\npush rbx\nxor ebx, ebx\nsub rsp, 8\njmp short loc_13C0\nloc_1388:\nlea eax, [r15+1]\ncmp r12d, 1\njz short loc_13E8\ncmp r12d, 2\njnz short loc_13F8\nmovzx ecx, cs:word_2194\nlea eax, [r15+2]\nmov [rsi], cx\nmovzx edx, byte ptr [r13+rbx+0]\nloc_13AC:\nlea r15d, [rax+1]\ncdqe\nxor r12d, r12d\nmov [rbp+rax+0], dl\nmovsxd r14, r15d\nloc_13BC:\nadd rbx, 1\nloc_13C0:\nmov rdi, r13; s\ncall _strlen\nlea rsi, [rbp+r14+0]\ncmp rbx, rax\njnb short loc_1408\nmovzx edx, byte ptr [r13+rbx+0]\ncmp dl, 20h ; ' '\njnz short loc_1388\nadd r12d, 1\njmp short loc_13BC\nloc_13E8:\nmov byte ptr [rsi], 5Fh ; '_'\nmovzx edx, byte ptr [r13+rbx+0]\njmp short loc_13AC\nloc_13F8:\njle short loc_1460\nmov byte ptr [rsi], 2Dh ; '-'\nmovzx edx, byte ptr [r13+rbx+0]\njmp short loc_13AC\nloc_1408:\ncmp r12d, 1\njz short loc_1450\ncmp r12d, 2\njz short loc_1438\njle short loc_1420\nmov byte ptr [rsi], 2Dh ; '-'\nadd r15d, 1\nmovsxd r14, r15d\nloc_1420:\nmov byte ptr [rbp+r14+0], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1438:\nlea eax, [r15+1]\nadd r15d, 2\nmov byte ptr [rsi], 5Fh ; '_'\ncdqe\nmovsxd r14, r15d\nmov byte ptr [rbp+rax+0], 5Fh ; '_'\njmp short loc_1420\nloc_1450:\nadd r15d, 1\nmov byte ptr [rsi], 5Fh ; '_'\nmovsxd r14, r15d\njmp short loc_1420\nloc_1460:\nmov eax, r15d\njmp loc_13AC", + "ida_pseudo": "size_t __fastcall func0(char *s, __int64 a2)\n{\n int v2; // r15d\n __int64 v3; // r14\n int v4; // r12d\n unsigned __int64 i; // rbx\n int v7; // eax\n char v8; // dl\n size_t result; // rax\n _BYTE *v10; // rsi\n\n v2 = 0;\n v3 = 0LL;\n v4 = 0;\n for ( i = 0LL; ; ++i )\n {\n result = strlen(s);\n v10 = (_BYTE *)(a2 + v3);\n if ( i >= result )\n break;\n v8 = s[i];\n if ( v8 == 32 )\n {\n ++v4;\n }\n else\n {\n v7 = v2 + 1;\n if ( v4 == 1 )\n {\n *v10 = 95;\n v8 = s[i];\n }\n else if ( v4 == 2 )\n {\n v7 = v2 + 2;\n *(_WORD *)v10 = 24415;\n v8 = s[i];\n }\n else if ( v4 <= 2 )\n {\n v7 = v2;\n }\n else\n {\n *v10 = 45;\n v8 = s[i];\n }\n v2 = v7 + 1;\n v4 = 0;\n *(_BYTE *)(a2 + v7) = v8;\n v3 = v7 + 1;\n }\n }\n if ( v4 == 1 )\n {\n *v10 = 95;\n v3 = v2 + 1;\n }\n else if ( v4 == 2 )\n {\n *v10 = 95;\n result = v2 + 1;\n v3 = v2 + 2;\n *(_BYTE *)(a2 + (int)result) = 95;\n }\n else if ( v4 > 2 )\n {\n *v10 = 45;\n v3 = v2 + 1;\n }\n *(_BYTE *)(a2 + v3) = 0;\n return result;\n}", + "ida_strip_asm": "sub_1360:\nendbr64\npush r15\nxor r15d, r15d\npush r14\nxor r14d, r14d\npush r13\nmov r13, rdi\npush r12\nxor r12d, r12d\npush rbp\nmov rbp, rsi\npush rbx\nxor ebx, ebx\nsub rsp, 8\njmp short loc_13C0\nloc_1388:\nlea eax, [r15+1]\ncmp r12d, 1\njz short loc_13E8\ncmp r12d, 2\njnz short loc_13F8\nmovzx ecx, cs:word_2194\nlea eax, [r15+2]\nmov [rsi], cx\nmovzx edx, byte ptr [r13+rbx+0]\nloc_13AC:\nlea r15d, [rax+1]\ncdqe\nxor r12d, r12d\nmov [rbp+rax+0], dl\nmovsxd r14, r15d\nloc_13BC:\nadd rbx, 1\nloc_13C0:\nmov rdi, r13; s\ncall _strlen\nlea rsi, [rbp+r14+0]\ncmp rbx, rax\njnb short loc_1408\nmovzx edx, byte ptr [r13+rbx+0]\ncmp dl, 20h ; ' '\njnz short loc_1388\nadd r12d, 1\njmp short loc_13BC\nloc_13E8:\nmov byte ptr [rsi], 5Fh ; '_'\nmovzx edx, byte ptr [r13+rbx+0]\njmp short loc_13AC\nloc_13F8:\njle short loc_1460\nmov byte ptr [rsi], 2Dh ; '-'\nmovzx edx, byte ptr [r13+rbx+0]\njmp short loc_13AC\nloc_1408:\ncmp r12d, 1\njz short loc_1450\ncmp r12d, 2\njz short loc_1438\njle short loc_1420\nmov byte ptr [rsi], 2Dh ; '-'\nadd r15d, 1\nmovsxd r14, r15d\nloc_1420:\nmov byte ptr [rbp+r14+0], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1438:\nlea eax, [r15+1]\nadd r15d, 2\nmov byte ptr [rsi], 5Fh ; '_'\ncdqe\nmovsxd r14, r15d\nmov byte ptr [rbp+rax+0], 5Fh ; '_'\njmp short loc_1420\nloc_1450:\nadd r15d, 1\nmov byte ptr [rsi], 5Fh ; '_'\nmovsxd r14, r15d\njmp short loc_1420\nloc_1460:\nmov eax, r15d\njmp loc_13AC", + "ida_strip_pseudo": "size_t __fastcall sub_1360(char *s, __int64 a2)\n{\n int v2; // r15d\n __int64 v3; // r14\n int v4; // r12d\n unsigned __int64 i; // rbx\n int v7; // eax\n char v8; // dl\n size_t result; // rax\n _BYTE *v10; // rsi\n\n v2 = 0;\n v3 = 0LL;\n v4 = 0;\n for ( i = 0LL; ; ++i )\n {\n result = strlen(s);\n v10 = (_BYTE *)(a2 + v3);\n if ( i >= result )\n break;\n v8 = s[i];\n if ( v8 == 32 )\n {\n ++v4;\n }\n else\n {\n v7 = v2 + 1;\n if ( v4 == 1 )\n {\n *v10 = 95;\n v8 = s[i];\n }\n else if ( v4 == 2 )\n {\n v7 = v2 + 2;\n *(_WORD *)v10 = 24415;\n v8 = s[i];\n }\n else if ( v4 <= 2 )\n {\n v7 = v2;\n }\n else\n {\n *v10 = 45;\n v8 = s[i];\n }\n v2 = v7 + 1;\n v4 = 0;\n *(_BYTE *)(a2 + v7) = v8;\n v3 = v7 + 1;\n }\n }\n if ( v4 == 1 )\n {\n *v10 = 95;\n v3 = v2 + 1;\n }\n else if ( v4 == 2 )\n {\n *v10 = 95;\n result = v2 + 1;\n v3 = v2 + 2;\n *(_BYTE *)(a2 + (int)result) = 95;\n }\n else if ( v4 > 2 )\n {\n *v10 = 45;\n v3 = v2 + 1;\n }\n *(_BYTE *)(a2 + v3) = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned int sub_1360(char *s, long long a2) {\n int v2;\n long long v3;\n int v4;\n unsigned long long i;\n int v7;\n char v8;\n unsigned int result;\n uint8_t *v10;\n v2 = 0;\n v3 = 0LL;\n v4 = 0;\n for (i = 0LL;; ++i) {\n result = strlen(s);\n v10 = (uint8_t *)(a2 + v3);\n if (i >= result) break;\n v8 = s[i];\n if (v8 == 32) {\n ++v4;\n } else {\n v7 = v2 + 1;\n if (v4 == 1) {\n *v10 = 95;\n v8 = s[i];\n } else if (v4 == 2) {\n v7 = v2 + 2;\n *(unsigned short *)v10 = 24415;\n v8 = s[i];\n } else if (v4 <= 2) {\n v7 = v2;\n } else {\n *v10 = 45;\n v8 = s[i];\n }\n v2 = v7 + 1;\n v4 = 0;\n *(uint8_t *)(a2 + v7) = v8;\n v3 = v7 + 1;\n }\n }\n if (v4 == 1) {\n *v10 = 95;\n v3 = v2 + 1;\n } else if (v4 == 2) {\n *v10 = 95;\n result = v2 + 1;\n v3 = v2 + 2;\n *(uint8_t *)(a2 + (int)result) = 95;\n } else if (v4 > 2) {\n *v10 = 45;\n v3 = v2 + 1;\n }\n *(uint8_t *)(a2 + v3) = 0;\n return result;\n}", + "ida_pseudo_norm": "unsigned int func0(char *s, long long a2) {\n int v2;\n long long v3;\n int v4;\n unsigned long long i;\n int v7;\n char v8;\n unsigned int result;\n uint8_t *v10;\n v2 = 0;\n v3 = 0LL;\n v4 = 0;\n for (i = 0LL;; ++i) {\n result = strlen(s);\n v10 = (uint8_t *)(a2 + v3);\n if (i >= result) break;\n v8 = s[i];\n if (v8 == 32) {\n ++v4;\n } else {\n v7 = v2 + 1;\n if (v4 == 1) {\n *v10 = 95;\n v8 = s[i];\n } else if (v4 == 2) {\n v7 = v2 + 2;\n *(unsigned short *)v10 = 24415;\n v8 = s[i];\n } else if (v4 <= 2) {\n v7 = v2;\n } else {\n *v10 = 45;\n v8 = s[i];\n }\n v2 = v7 + 1;\n v4 = 0;\n *(uint8_t *)(a2 + v7) = v8;\n v3 = v7 + 1;\n }\n }\n if (v4 == 1) {\n *v10 = 95;\n v3 = v2 + 1;\n } else if (v4 == 2) {\n *v10 = 95;\n result = v2 + 1;\n v3 = v2 + 2;\n *(uint8_t *)(a2 + (int)result) = 95;\n } else if (v4 > 2) {\n *v10 = 45;\n v3 = v2 + 1;\n }\n *(uint8_t *)(a2 + v3) = 0;\n return result;\n}" + }, + { + "index": "HumanEval-C-141", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "const char* func0(const char* file_name) {\n int num_digit = 0, num_dot = 0;\n int length = strlen(file_name);\n if (length < 5) return \"No\";\n char w = file_name[0];\n if (w < 'A' || (w > 'Z' && w < 'a') || w > 'z') return \"No\";\n const char* last = file_name + length - 4;\n if (strcmp(last, \".txt\") != 0 && strcmp(last, \".exe\") != 0 &&\n strcmp(last, \".dll\") != 0)\n return \"No\";\n for (int i = 0; i < length; i++) {\n if (file_name[i] >= '0' && file_name[i] <= '9') num_digit++;\n if (file_name[i] == '.') num_dot++;\n }\n if (num_digit > 3 || num_dot != 1) return \"No\";\n return \"Yes\";\n}", + "test": "#include \n#include \n\nint main() {\n assert(strcmp(func0(\"example.txt\"), \"Yes\") == 0);\n assert(strcmp(func0(\"1example.dll\"), \"No\") == 0);\n assert(strcmp(func0(\"s1sdf3.asd\"), \"No\") == 0);\n assert(strcmp(func0(\"K.dll\"), \"Yes\") == 0);\n assert(strcmp(func0(\"MY16FILE3.exe\"), \"Yes\") == 0);\n assert(strcmp(func0(\"His12FILE94.exe\"), \"No\") == 0);\n assert(strcmp(func0(\"_Y.txt\"), \"No\") == 0);\n assert(strcmp(func0(\"?aREYA.exe\"), \"No\") == 0);\n assert(strcmp(func0(\"/this_is_valid.dll\"), \"No\") == 0);\n assert(strcmp(func0(\"this_is_valid.wow\"), \"No\") == 0);\n assert(strcmp(func0(\"this_is_valid.txt\"), \"Yes\") == 0);\n assert(strcmp(func0(\"this_is_valid.txtexe\"), \"No\") == 0);\n assert(strcmp(func0(\"#this2_i4s_5valid.ten\"), \"No\") == 0);\n assert(strcmp(func0(\"@this1_is6_valid.exe\"), \"No\") == 0);\n assert(strcmp(func0(\"this_is_12valid.6exe4.txt\"), \"No\") == 0);\n assert(strcmp(func0(\"all.exe.txt\"), \"No\") == 0);\n assert(strcmp(func0(\"I563_No.exe\"), \"Yes\") == 0);\n assert(strcmp(func0(\"Is3youfault.txt\"), \"Yes\") == 0);\n assert(strcmp(func0(\"no_one#knows.dll\"), \"Yes\") == 0);\n assert(strcmp(func0(\"1I563_Yes3.exe\"), \"No\") == 0);\n assert(strcmp(func0(\"I563_Yes3.txtt\"), \"No\") == 0);\n assert(strcmp(func0(\"final..txt\"), \"No\") == 0);\n assert(strcmp(func0(\"final132\"), \"No\") == 0);\n assert(strcmp(func0(\"_f4indsartal132.\"), \"No\") == 0);\n assert(strcmp(func0(\".txt\"), \"No\") == 0);\n assert(strcmp(func0(\"s.\"), \"No\") == 0);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_C], eax\ncmp [rbp+var_C], 4\njg short loc_11C8\nlea rax, aNo; \"No\"\njmp locret_12D6\nloc_11C8:\nmov rax, [rbp+s]\nmovzx eax, byte ptr [rax]\nmov [rbp+var_19], al\ncmp [rbp+var_19], 40h ; '@'\njle short loc_11EA\ncmp [rbp+var_19], 5Ah ; 'Z'\njle short loc_11E4\ncmp [rbp+var_19], 60h ; '`'\njle short loc_11EA\nloc_11E4:\ncmp [rbp+var_19], 7Ah ; 'z'\njle short loc_11F6\nloc_11EA:\nlea rax, aNo; \"No\"\njmp locret_12D6\nloc_11F6:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, [rax-4]\nmov rax, [rbp+s]\nadd rax, rdx\nmov [rbp+s1], rax\nmov rax, [rbp+s1]\nlea rdx, s2; \".txt\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_1261\nmov rax, [rbp+s1]\nlea rdx, aExe; \".exe\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_1261\nmov rax, [rbp+s1]\nlea rdx, aDll; \".dll\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_1261\nlea rax, aNo; \"No\"\njmp short locret_12D6\nloc_1261:\nmov [rbp+var_10], 0\njmp short loc_12B2\nloc_126A:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 2Fh ; '/'\njle short loc_1296\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 39h ; '9'\njg short loc_1296\nadd [rbp+var_18], 1\nloc_1296:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 2Eh ; '.'\njnz short loc_12AE\nadd [rbp+var_14], 1\nloc_12AE:\nadd [rbp+var_10], 1\nloc_12B2:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_C]\njl short loc_126A\ncmp [rbp+var_18], 3\njg short loc_12C6\ncmp [rbp+var_14], 1\njz short loc_12CF\nloc_12C6:\nlea rax, aNo; \"No\"\njmp short locret_12D6\nloc_12CF:\nlea rax, aYes; \"Yes\"\nlocret_12D6:\nleave\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n char v2; // [rsp+17h] [rbp-19h]\n int v3; // [rsp+18h] [rbp-18h]\n int v4; // [rsp+1Ch] [rbp-14h]\n int i; // [rsp+20h] [rbp-10h]\n int v6; // [rsp+24h] [rbp-Ch]\n char *s1; // [rsp+28h] [rbp-8h]\n\n v3 = 0;\n v4 = 0;\n v6 = strlen(a1);\n if ( v6 <= 4 )\n return \"No\";\n v2 = *a1;\n if ( *a1 <= 64 || v2 > 90 && v2 <= 96 || v2 > 122 )\n return \"No\";\n s1 = (char *)&a1[v6 - 4];\n if ( strcmp(s1, \".txt\") && strcmp(s1, \".exe\") && strcmp(s1, \".dll\") )\n return \"No\";\n for ( i = 0; i < v6; ++i )\n {\n if ( a1[i] > 47 && a1[i] <= 57 )\n ++v3;\n if ( a1[i] == 46 )\n ++v4;\n }\n if ( v3 <= 3 && v4 == 1 )\n return \"Yes\";\n else\n return \"No\";\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_C], eax\ncmp [rbp+var_C], 4\njg short loc_11C8\nlea rax, aNo; \"No\"\njmp locret_12D6\nloc_11C8:\nmov rax, [rbp+s]\nmovzx eax, byte ptr [rax]\nmov [rbp+var_19], al\ncmp [rbp+var_19], 40h ; '@'\njle short loc_11EA\ncmp [rbp+var_19], 5Ah ; 'Z'\njle short loc_11E4\ncmp [rbp+var_19], 60h ; '`'\njle short loc_11EA\nloc_11E4:\ncmp [rbp+var_19], 7Ah ; 'z'\njle short loc_11F6\nloc_11EA:\nlea rax, aNo; \"No\"\njmp locret_12D6\nloc_11F6:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, [rax-4]\nmov rax, [rbp+s]\nadd rax, rdx\nmov [rbp+s1], rax\nmov rax, [rbp+s1]\nlea rdx, s2; \".txt\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_1261\nmov rax, [rbp+s1]\nlea rdx, aExe; \".exe\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_1261\nmov rax, [rbp+s1]\nlea rdx, aDll; \".dll\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_1261\nlea rax, aNo; \"No\"\njmp short locret_12D6\nloc_1261:\nmov [rbp+var_10], 0\njmp short loc_12B2\nloc_126A:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 2Fh ; '/'\njle short loc_1296\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 39h ; '9'\njg short loc_1296\nadd [rbp+var_18], 1\nloc_1296:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 2Eh ; '.'\njnz short loc_12AE\nadd [rbp+var_14], 1\nloc_12AE:\nadd [rbp+var_10], 1\nloc_12B2:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_C]\njl short loc_126A\ncmp [rbp+var_18], 3\njg short loc_12C6\ncmp [rbp+var_14], 1\njz short loc_12CF\nloc_12C6:\nlea rax, aNo; \"No\"\njmp short locret_12D6\nloc_12CF:\nlea rax, aYes; \"Yes\"\nlocret_12D6:\nleave\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1189(const char *a1)\n{\n char v2; // [rsp+17h] [rbp-19h]\n int v3; // [rsp+18h] [rbp-18h]\n int v4; // [rsp+1Ch] [rbp-14h]\n int i; // [rsp+20h] [rbp-10h]\n int v6; // [rsp+24h] [rbp-Ch]\n char *s1; // [rsp+28h] [rbp-8h]\n\n v3 = 0;\n v4 = 0;\n v6 = strlen(a1);\n if ( v6 <= 4 )\n return \"No\";\n v2 = *a1;\n if ( *a1 <= 64 || v2 > 90 && v2 <= 96 || v2 > 122 )\n return \"No\";\n s1 = (char *)&a1[v6 - 4];\n if ( strcmp(s1, \".txt\") && strcmp(s1, \".exe\") && strcmp(s1, \".dll\") )\n return \"No\";\n for ( i = 0; i < v6; ++i )\n {\n if ( a1[i] > 47 && a1[i] <= 57 )\n ++v3;\n if ( a1[i] == 46 )\n ++v4;\n }\n if ( v3 <= 3 && v4 == 1 )\n return \"Yes\";\n else\n return \"No\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1189(const char *a1) {\n char v2;\n int v3;\n int v4;\n int i;\n int v6;\n char *s1;\n v3 = 0;\n v4 = 0;\n v6 = strlen(a1);\n if (v6 <= 4) return \"No\";\n v2 = *a1;\n if (*a1 <= 64 || v2 > 90 && v2 <= 96 || v2 > 122) return \"No\";\n s1 = (char *)&a1[v6 - 4];\n if (strcmp(s1, \".txt\") && strcmp(s1, \".exe\") && strcmp(s1, \".dll\"))\n return \"No\";\n for (i = 0; i < v6; ++i) {\n if (a1[i] > 47 && a1[i] <= 57) ++v3;\n if (a1[i] == 46) ++v4;\n }\n if (v3 <= 3 && v4 == 1)\n return \"Yes\";\n else\n return \"No\";\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n char v2;\n int v3;\n int v4;\n int i;\n int v6;\n char *s1;\n v3 = 0;\n v4 = 0;\n v6 = strlen(a1);\n if (v6 <= 4) return \"No\";\n v2 = *a1;\n if (*a1 <= 64 || v2 > 90 && v2 <= 96 || v2 > 122) return \"No\";\n s1 = (char *)&a1[v6 - 4];\n if (strcmp(s1, \".txt\") && strcmp(s1, \".exe\") && strcmp(s1, \".dll\"))\n return \"No\";\n for (i = 0; i < v6; ++i) {\n if (a1[i] > 47 && a1[i] <= 57) ++v3;\n if (a1[i] == 46) ++v4;\n }\n if (v3 <= 3 && v4 == 1)\n return \"Yes\";\n else\n return \"No\";\n}" + }, + { + "index": "HumanEval-C-141", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "const char* func0(const char* file_name) {\n int num_digit = 0, num_dot = 0;\n int length = strlen(file_name);\n if (length < 5) return \"No\";\n char w = file_name[0];\n if (w < 'A' || (w > 'Z' && w < 'a') || w > 'z') return \"No\";\n const char* last = file_name + length - 4;\n if (strcmp(last, \".txt\") != 0 && strcmp(last, \".exe\") != 0 &&\n strcmp(last, \".dll\") != 0)\n return \"No\";\n for (int i = 0; i < length; i++) {\n if (file_name[i] >= '0' && file_name[i] <= '9') num_digit++;\n if (file_name[i] == '.') num_dot++;\n }\n if (num_digit > 3 || num_dot != 1) return \"No\";\n return \"Yes\";\n}", + "test": "#include \n#include \n\nint main() {\n assert(strcmp(func0(\"example.txt\"), \"Yes\") == 0);\n assert(strcmp(func0(\"1example.dll\"), \"No\") == 0);\n assert(strcmp(func0(\"s1sdf3.asd\"), \"No\") == 0);\n assert(strcmp(func0(\"K.dll\"), \"Yes\") == 0);\n assert(strcmp(func0(\"MY16FILE3.exe\"), \"Yes\") == 0);\n assert(strcmp(func0(\"His12FILE94.exe\"), \"No\") == 0);\n assert(strcmp(func0(\"_Y.txt\"), \"No\") == 0);\n assert(strcmp(func0(\"?aREYA.exe\"), \"No\") == 0);\n assert(strcmp(func0(\"/this_is_valid.dll\"), \"No\") == 0);\n assert(strcmp(func0(\"this_is_valid.wow\"), \"No\") == 0);\n assert(strcmp(func0(\"this_is_valid.txt\"), \"Yes\") == 0);\n assert(strcmp(func0(\"this_is_valid.txtexe\"), \"No\") == 0);\n assert(strcmp(func0(\"#this2_i4s_5valid.ten\"), \"No\") == 0);\n assert(strcmp(func0(\"@this1_is6_valid.exe\"), \"No\") == 0);\n assert(strcmp(func0(\"this_is_12valid.6exe4.txt\"), \"No\") == 0);\n assert(strcmp(func0(\"all.exe.txt\"), \"No\") == 0);\n assert(strcmp(func0(\"I563_No.exe\"), \"Yes\") == 0);\n assert(strcmp(func0(\"Is3youfault.txt\"), \"Yes\") == 0);\n assert(strcmp(func0(\"no_one#knows.dll\"), \"Yes\") == 0);\n assert(strcmp(func0(\"1I563_Yes3.exe\"), \"No\") == 0);\n assert(strcmp(func0(\"I563_Yes3.txtt\"), \"No\") == 0);\n assert(strcmp(func0(\"final..txt\"), \"No\") == 0);\n assert(strcmp(func0(\"final132\"), \"No\") == 0);\n assert(strcmp(func0(\"_f4indsartal132.\"), \"No\") == 0);\n assert(strcmp(func0(\".txt\"), \"No\") == 0);\n assert(strcmp(func0(\"s.\"), \"No\") == 0);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbx, rdi\ncall _strlen\nmov rbp, rax\nlea rax, aNo; \"No\"\ncmp ebp, 4\njle loc_126C\nmovzx eax, byte ptr [rbx]\nlea edx, [rax-5Bh]\ncmp dl, 5\njbe loc_1265\nsub eax, 41h ; 'A'\ncmp al, 39h ; '9'\nja loc_1265\nmovsxd rax, ebp\nlea r12, [rbx+rax-4]\nlea rsi, aFinalTxt+6; s2\nmov rdi, r12; s1\ncall _strcmp\ntest eax, eax\njz short loc_1210\nlea rsi, aMy16file3Exe+9; s2\nmov rdi, r12; s1\ncall _strcmp\ntest eax, eax\njz short loc_1210\nlea rsi, aKDll+1; s2\nmov rdi, r12; s1\ncall _strcmp\nmov edx, eax\nlea rax, aNo; \"No\"\ntest edx, edx\njnz short loc_126C\nloc_1210:\nmov rax, rbx\nlea edx, [rbp-1]\nlea r8, [rbx+rdx+1]\nmov edi, 0\nmov esi, 0\njmp short loc_123B\nloc_1227:\ncmp dl, 2Eh ; '.'\nsetz dl\nmovzx edx, dl\nadd edi, edx\nloc_1232:\nadd rax, 1\ncmp rax, r8\njz short loc_124B\nloc_123B:\nmovzx edx, byte ptr [rax]\nlea ecx, [rdx-30h]\ncmp cl, 9\nja short loc_1227\nadd esi, 1\njmp short loc_1232\nloc_124B:\ncmp esi, 3\njg short loc_125C\nlea rax, s2; \"Yes\"\ncmp edi, 1\njz short loc_126C\nloc_125C:\nlea rax, aNo; \"No\"\njmp short loc_126C\nloc_1265:\nlea rax, aNo; \"No\"\nloc_126C:\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n int v2; // ebp\n const char *result; // rax\n int v4; // edx\n const char *v5; // rax\n int v6; // edi\n int v7; // esi\n\n v2 = strlen(a1);\n result = \"No\";\n if ( v2 > 4 )\n {\n if ( (unsigned __int8)(*a1 - 91) <= 5u || (unsigned __int8)(*a1 - 65) > 0x39u )\n {\n return \"No\";\n }\n else if ( !strcmp(&a1[v2 - 4], \".txt\")\n || !strcmp(&a1[v2 - 4], \".exe\")\n || (v4 = strcmp(&a1[v2 - 4], \".dll\"), result = \"No\", !v4) )\n {\n v5 = a1;\n v6 = 0;\n v7 = 0;\n do\n {\n if ( (unsigned __int8)(*v5 - 48) > 9u )\n v6 += *v5 == 46;\n else\n ++v7;\n ++v5;\n }\n while ( v5 != &a1[v2 - 1 + 1] );\n if ( v7 > 3 )\n return \"No\";\n result = \"Yes\";\n if ( v6 != 1 )\n return \"No\";\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbx, rdi\ncall _strlen\nmov rbp, rax\nlea rax, aNo; \"No\"\ncmp ebp, 4\njle loc_126C\nmovzx eax, byte ptr [rbx]\nlea edx, [rax-5Bh]\ncmp dl, 5\njbe loc_1265\nsub eax, 41h ; 'A'\ncmp al, 39h ; '9'\nja loc_1265\nmovsxd rax, ebp\nlea r12, [rbx+rax-4]\nlea rsi, aFinalTxt+6; s2\nmov rdi, r12; s1\ncall _strcmp\ntest eax, eax\njz short loc_1210\nlea rsi, aMy16file3Exe+9; s2\nmov rdi, r12; s1\ncall _strcmp\ntest eax, eax\njz short loc_1210\nlea rsi, aKDll+1; s2\nmov rdi, r12; s1\ncall _strcmp\nmov edx, eax\nlea rax, aNo; \"No\"\ntest edx, edx\njnz short loc_126C\nloc_1210:\nmov rax, rbx\nlea edx, [rbp-1]\nlea r8, [rbx+rdx+1]\nmov edi, 0\nmov esi, 0\njmp short loc_123B\nloc_1227:\ncmp dl, 2Eh ; '.'\nsetz dl\nmovzx edx, dl\nadd edi, edx\nloc_1232:\nadd rax, 1\ncmp rax, r8\njz short loc_124B\nloc_123B:\nmovzx edx, byte ptr [rax]\nlea ecx, [rdx-30h]\ncmp cl, 9\nja short loc_1227\nadd esi, 1\njmp short loc_1232\nloc_124B:\ncmp esi, 3\njg short loc_125C\nlea rax, s2; \"Yes\"\ncmp edi, 1\njz short loc_126C\nloc_125C:\nlea rax, aNo; \"No\"\njmp short loc_126C\nloc_1265:\nlea rax, aNo; \"No\"\nloc_126C:\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1189(const char *a1)\n{\n int v2; // ebp\n const char *result; // rax\n int v4; // edx\n const char *v5; // rax\n int v6; // edi\n int v7; // esi\n\n v2 = strlen(a1);\n result = \"No\";\n if ( v2 > 4 )\n {\n if ( (unsigned __int8)(*a1 - 91) <= 5u || (unsigned __int8)(*a1 - 65) > 0x39u )\n {\n return \"No\";\n }\n else if ( !strcmp(&a1[v2 - 4], \".txt\")\n || !strcmp(&a1[v2 - 4], \".exe\")\n || (v4 = strcmp(&a1[v2 - 4], \".dll\"), result = \"No\", !v4) )\n {\n v5 = a1;\n v6 = 0;\n v7 = 0;\n do\n {\n if ( (unsigned __int8)(*v5 - 48) > 9u )\n v6 += *v5 == 46;\n else\n ++v7;\n ++v5;\n }\n while ( v5 != &a1[v2 - 1 + 1] );\n if ( v7 > 3 )\n return \"No\";\n result = \"Yes\";\n if ( v6 != 1 )\n return \"No\";\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1189(const char *a1) {\n int v2;\n const char *result;\n int v4;\n const char *v5;\n int v6;\n int v7;\n v2 = strlen(a1);\n result = \"No\";\n if (v2 > 4) {\n if ((unsigned char)(*a1 - 91) <= 5u || (unsigned char)(*a1 - 65) > 57u) {\n return \"No\";\n } else if (!strcmp(&a1[v2 - 4], \".txt\") || !strcmp(&a1[v2 - 4], \".exe\") ||\n (v4 = strcmp(&a1[v2 - 4], \".dll\"), result = \"No\", !v4)) {\n v5 = a1;\n v6 = 0;\n v7 = 0;\n do {\n if ((unsigned char)(*v5 - 48) > 9u)\n v6 += *v5 == 46;\n else\n ++v7;\n ++v5;\n } while (v5 != &a1[v2 - 1 + 1]);\n if (v7 > 3) return \"No\";\n result = \"Yes\";\n if (v6 != 1) return \"No\";\n }\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n int v2;\n const char *result;\n int v4;\n const char *v5;\n int v6;\n int v7;\n v2 = strlen(a1);\n result = \"No\";\n if (v2 > 4) {\n if ((unsigned char)(*a1 - 91) <= 5u || (unsigned char)(*a1 - 65) > 57u) {\n return \"No\";\n } else if (!strcmp(&a1[v2 - 4], \".txt\") || !strcmp(&a1[v2 - 4], \".exe\") ||\n (v4 = strcmp(&a1[v2 - 4], \".dll\"), result = \"No\", !v4)) {\n v5 = a1;\n v6 = 0;\n v7 = 0;\n do {\n if ((unsigned char)(*v5 - 48) > 9u)\n v6 += *v5 == 46;\n else\n ++v7;\n ++v5;\n } while (v5 != &a1[v2 - 1 + 1]);\n if (v7 > 3) return \"No\";\n result = \"Yes\";\n if (v6 != 1) return \"No\";\n }\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-141", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "const char* func0(const char* file_name) {\n int num_digit = 0, num_dot = 0;\n int length = strlen(file_name);\n if (length < 5) return \"No\";\n char w = file_name[0];\n if (w < 'A' || (w > 'Z' && w < 'a') || w > 'z') return \"No\";\n const char* last = file_name + length - 4;\n if (strcmp(last, \".txt\") != 0 && strcmp(last, \".exe\") != 0 &&\n strcmp(last, \".dll\") != 0)\n return \"No\";\n for (int i = 0; i < length; i++) {\n if (file_name[i] >= '0' && file_name[i] <= '9') num_digit++;\n if (file_name[i] == '.') num_dot++;\n }\n if (num_digit > 3 || num_dot != 1) return \"No\";\n return \"Yes\";\n}", + "test": "#include \n#include \n\nint main() {\n assert(strcmp(func0(\"example.txt\"), \"Yes\") == 0);\n assert(strcmp(func0(\"1example.dll\"), \"No\") == 0);\n assert(strcmp(func0(\"s1sdf3.asd\"), \"No\") == 0);\n assert(strcmp(func0(\"K.dll\"), \"Yes\") == 0);\n assert(strcmp(func0(\"MY16FILE3.exe\"), \"Yes\") == 0);\n assert(strcmp(func0(\"His12FILE94.exe\"), \"No\") == 0);\n assert(strcmp(func0(\"_Y.txt\"), \"No\") == 0);\n assert(strcmp(func0(\"?aREYA.exe\"), \"No\") == 0);\n assert(strcmp(func0(\"/this_is_valid.dll\"), \"No\") == 0);\n assert(strcmp(func0(\"this_is_valid.wow\"), \"No\") == 0);\n assert(strcmp(func0(\"this_is_valid.txt\"), \"Yes\") == 0);\n assert(strcmp(func0(\"this_is_valid.txtexe\"), \"No\") == 0);\n assert(strcmp(func0(\"#this2_i4s_5valid.ten\"), \"No\") == 0);\n assert(strcmp(func0(\"@this1_is6_valid.exe\"), \"No\") == 0);\n assert(strcmp(func0(\"this_is_12valid.6exe4.txt\"), \"No\") == 0);\n assert(strcmp(func0(\"all.exe.txt\"), \"No\") == 0);\n assert(strcmp(func0(\"I563_No.exe\"), \"Yes\") == 0);\n assert(strcmp(func0(\"Is3youfault.txt\"), \"Yes\") == 0);\n assert(strcmp(func0(\"no_one#knows.dll\"), \"Yes\") == 0);\n assert(strcmp(func0(\"1I563_Yes3.exe\"), \"No\") == 0);\n assert(strcmp(func0(\"I563_Yes3.txtt\"), \"No\") == 0);\n assert(strcmp(func0(\"final..txt\"), \"No\") == 0);\n assert(strcmp(func0(\"final132\"), \"No\") == 0);\n assert(strcmp(func0(\"_f4indsartal132.\"), \"No\") == 0);\n assert(strcmp(func0(\".txt\"), \"No\") == 0);\n assert(strcmp(func0(\"s.\"), \"No\") == 0);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\nlea r12, unk_2004\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\ncmp eax, 4\njle loc_187C\nmov rbp, rax\nmovzx eax, byte ptr [rbx]\nlea edx, [rax-5Bh]\ncmp dl, 5\njbe loc_1890\nsub eax, 41h ; 'A'\ncmp al, 39h ; '9'\nja loc_1890\nmovsxd rax, ebp\nlea rsi, aFinalTxt+6; s2\nlea r13, [rbx+rax-4]\nmov rdi, r13; s1\ncall _strcmp\ntest eax, eax\njnz short loc_18A8\nloc_182E:\nlea edx, [rbp-1]\nmov rax, rbx\nxor edi, edi\nxor esi, esi\nlea r8, [rbx+rdx+1]\njmp short loc_1854\nloc_1840:\ncmp dl, 2Eh ; '.'\nsetz dl\nadd rax, 1\nmovzx edx, dl\nadd edi, edx\ncmp r8, rax\njz short loc_186B\nloc_1854:\nmovzx edx, byte ptr [rax]\nlea ecx, [rdx-30h]\ncmp cl, 9\nja short loc_1840\nadd rax, 1\nadd esi, 1\ncmp r8, rax\njnz short loc_1854\nloc_186B:\ncmp esi, 3\njg short loc_1890\nlea r12, s2; \"Yes\"\ncmp edi, 1\njnz short loc_1890\nloc_187C:\nadd rsp, 8\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1890:\nadd rsp, 8\nlea r12, unk_2004\npop rbx\nmov rax, r12\npop rbp\npop r12\npop r13\nretn\nloc_18A8:\nlea rsi, aMy16file3Exe+9; s2\nmov rdi, r13; s1\ncall _strcmp\ntest eax, eax\njz loc_182E\nlea rsi, aKDll+1; s2\nmov rdi, r13; s1\ncall _strcmp\ntest eax, eax\njz loc_182E\njmp short loc_187C", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n const char *v1; // r12\n int v3; // eax\n int v4; // ebp\n const char *v5; // rax\n int v6; // edi\n int v7; // esi\n __int64 v8; // r8\n char v9; // dl\n\n v1 = (const char *)&unk_2004;\n v3 = strlen(a1);\n if ( v3 <= 4 )\n return v1;\n v4 = v3;\n if ( (unsigned __int8)(*a1 - 91) <= 5u || (unsigned __int8)(*a1 - 65) > 0x39u )\n return (const char *)&unk_2004;\n if ( strcmp(&a1[v3 - 4], \".txt\") && strcmp(&a1[v4 - 4], \".exe\") && strcmp(&a1[v4 - 4], \".dll\") )\n return v1;\n v5 = a1;\n v6 = 0;\n v7 = 0;\n v8 = (__int64)&a1[v4 - 1 + 1];\n do\n {\n while ( 1 )\n {\n v9 = *v5;\n if ( (unsigned __int8)(*v5 - 48) <= 9u )\n break;\n ++v5;\n v6 += v9 == 46;\n if ( (const char *)v8 == v5 )\n goto LABEL_9;\n }\n ++v5;\n ++v7;\n }\n while ( (const char *)v8 != v5 );\nLABEL_9:\n if ( v7 > 3 )\n return (const char *)&unk_2004;\n v1 = \"Yes\";\n if ( v6 != 1 )\n return (const char *)&unk_2004;\n else\n return v1;\n}", + "ida_strip_asm": "sub_17D0:\nendbr64\npush r13\npush r12\nlea r12, unk_2004\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\ncmp eax, 4\njle loc_187C\nmov rbp, rax\nmovzx eax, byte ptr [rbx]\nlea edx, [rax-5Bh]\ncmp dl, 5\njbe loc_1890\nsub eax, 41h ; 'A'\ncmp al, 39h ; '9'\nja loc_1890\nmovsxd rax, ebp\nlea rsi, aFinalTxt+6; s2\nlea r13, [rbx+rax-4]\nmov rdi, r13; s1\ncall _strcmp\ntest eax, eax\njnz short loc_18A8\nloc_182E:\nlea edx, [rbp-1]\nmov rax, rbx\nxor edi, edi\nxor esi, esi\nlea r8, [rbx+rdx+1]\njmp short loc_1854\nloc_1840:\ncmp dl, 2Eh ; '.'\nsetz dl\nadd rax, 1\nmovzx edx, dl\nadd edi, edx\ncmp r8, rax\njz short loc_186B\nloc_1854:\nmovzx edx, byte ptr [rax]\nlea ecx, [rdx-30h]\ncmp cl, 9\nja short loc_1840\nadd rax, 1\nadd esi, 1\ncmp r8, rax\njnz short loc_1854\nloc_186B:\ncmp esi, 3\njg short loc_1890\nlea r12, s2; \"Yes\"\ncmp edi, 1\njnz short loc_1890\nloc_187C:\nadd rsp, 8\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1890:\nadd rsp, 8\nlea r12, unk_2004\npop rbx\nmov rax, r12\npop rbp\npop r12\npop r13\nretn\nloc_18A8:\nlea rsi, aMy16file3Exe+9; s2\nmov rdi, r13; s1\ncall _strcmp\ntest eax, eax\njz loc_182E\nlea rsi, aKDll+1; s2\nmov rdi, r13; s1\ncall _strcmp\ntest eax, eax\njz loc_182E\njmp short loc_187C", + "ida_strip_pseudo": "const char *__fastcall sub_17D0(const char *a1)\n{\n const char *v1; // r12\n int v3; // eax\n int v4; // ebp\n const char *v5; // rax\n int v6; // edi\n int v7; // esi\n __int64 v8; // r8\n char v9; // dl\n\n v1 = (const char *)&unk_2004;\n v3 = strlen(a1);\n if ( v3 <= 4 )\n return v1;\n v4 = v3;\n if ( (unsigned __int8)(*a1 - 91) <= 5u || (unsigned __int8)(*a1 - 65) > 0x39u )\n return (const char *)&unk_2004;\n if ( strcmp(&a1[v3 - 4], \".txt\") && strcmp(&a1[v4 - 4], \".exe\") && strcmp(&a1[v4 - 4], \".dll\") )\n return v1;\n v5 = a1;\n v6 = 0;\n v7 = 0;\n v8 = (__int64)&a1[v4 - 1 + 1];\n do\n {\n while ( 1 )\n {\n v9 = *v5;\n if ( (unsigned __int8)(*v5 - 48) <= 9u )\n break;\n ++v5;\n v6 += v9 == 46;\n if ( (const char *)v8 == v5 )\n goto LABEL_9;\n }\n ++v5;\n ++v7;\n }\n while ( (const char *)v8 != v5 );\nLABEL_9:\n if ( v7 > 3 )\n return (const char *)&unk_2004;\n v1 = \"Yes\";\n if ( v6 != 1 )\n return (const char *)&unk_2004;\n else\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_17D0(const char *a1) {\n const char *v1;\n int v3;\n int v4;\n const char *v5;\n int v6;\n int v7;\n long long v8;\n char v9;\n v1 = (const char *)&unk_2004;\n v3 = strlen(a1);\n if (v3 <= 4) return v1;\n v4 = v3;\n if ((unsigned char)(*a1 - 91) <= 5u || (unsigned char)(*a1 - 65) > 57u)\n return (const char *)&unk_2004;\n if (strcmp(&a1[v3 - 4], \".txt\") && strcmp(&a1[v4 - 4], \".exe\") &&\n strcmp(&a1[v4 - 4], \".dll\"))\n return v1;\n v5 = a1;\n v6 = 0;\n v7 = 0;\n v8 = (long long)&a1[v4 - 1 + 1];\n do {\n while (1) {\n v9 = *v5;\n if ((unsigned char)(*v5 - 48) <= 9u) break;\n ++v5;\n v6 += v9 == 46;\n if ((const char *)v8 == v5) goto LABEL_9;\n }\n ++v5;\n ++v7;\n } while ((const char *)v8 != v5);\nLABEL_9:\n if (v7 > 3) return (const char *)&unk_2004;\n v1 = \"Yes\";\n if (v6 != 1)\n return (const char *)&unk_2004;\n else\n return v1;\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n const char *v1;\n int v3;\n int v4;\n const char *v5;\n int v6;\n int v7;\n long long v8;\n char v9;\n v1 = (const char *)&unk_2004;\n v3 = strlen(a1);\n if (v3 <= 4) return v1;\n v4 = v3;\n if ((unsigned char)(*a1 - 91) <= 5u || (unsigned char)(*a1 - 65) > 57u)\n return (const char *)&unk_2004;\n if (strcmp(&a1[v3 - 4], \".txt\") && strcmp(&a1[v4 - 4], \".exe\") &&\n strcmp(&a1[v4 - 4], \".dll\"))\n return v1;\n v5 = a1;\n v6 = 0;\n v7 = 0;\n v8 = (long long)&a1[v4 - 1 + 1];\n do {\n while (1) {\n v9 = *v5;\n if ((unsigned char)(*v5 - 48) <= 9u) break;\n ++v5;\n v6 += v9 == 46;\n if ((const char *)v8 == v5) goto LABEL_9;\n }\n ++v5;\n ++v7;\n } while ((const char *)v8 != v5);\nLABEL_9:\n if (v7 > 3) return (const char *)&unk_2004;\n v1 = \"Yes\";\n if (v6 != 1)\n return (const char *)&unk_2004;\n else\n return v1;\n}" + }, + { + "index": "HumanEval-C-141", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "const char* func0(const char* file_name) {\n int num_digit = 0, num_dot = 0;\n int length = strlen(file_name);\n if (length < 5) return \"No\";\n char w = file_name[0];\n if (w < 'A' || (w > 'Z' && w < 'a') || w > 'z') return \"No\";\n const char* last = file_name + length - 4;\n if (strcmp(last, \".txt\") != 0 && strcmp(last, \".exe\") != 0 &&\n strcmp(last, \".dll\") != 0)\n return \"No\";\n for (int i = 0; i < length; i++) {\n if (file_name[i] >= '0' && file_name[i] <= '9') num_digit++;\n if (file_name[i] == '.') num_dot++;\n }\n if (num_digit > 3 || num_dot != 1) return \"No\";\n return \"Yes\";\n}", + "test": "#include \n#include \n\nint main() {\n assert(strcmp(func0(\"example.txt\"), \"Yes\") == 0);\n assert(strcmp(func0(\"1example.dll\"), \"No\") == 0);\n assert(strcmp(func0(\"s1sdf3.asd\"), \"No\") == 0);\n assert(strcmp(func0(\"K.dll\"), \"Yes\") == 0);\n assert(strcmp(func0(\"MY16FILE3.exe\"), \"Yes\") == 0);\n assert(strcmp(func0(\"His12FILE94.exe\"), \"No\") == 0);\n assert(strcmp(func0(\"_Y.txt\"), \"No\") == 0);\n assert(strcmp(func0(\"?aREYA.exe\"), \"No\") == 0);\n assert(strcmp(func0(\"/this_is_valid.dll\"), \"No\") == 0);\n assert(strcmp(func0(\"this_is_valid.wow\"), \"No\") == 0);\n assert(strcmp(func0(\"this_is_valid.txt\"), \"Yes\") == 0);\n assert(strcmp(func0(\"this_is_valid.txtexe\"), \"No\") == 0);\n assert(strcmp(func0(\"#this2_i4s_5valid.ten\"), \"No\") == 0);\n assert(strcmp(func0(\"@this1_is6_valid.exe\"), \"No\") == 0);\n assert(strcmp(func0(\"this_is_12valid.6exe4.txt\"), \"No\") == 0);\n assert(strcmp(func0(\"all.exe.txt\"), \"No\") == 0);\n assert(strcmp(func0(\"I563_No.exe\"), \"Yes\") == 0);\n assert(strcmp(func0(\"Is3youfault.txt\"), \"Yes\") == 0);\n assert(strcmp(func0(\"no_one#knows.dll\"), \"Yes\") == 0);\n assert(strcmp(func0(\"1I563_Yes3.exe\"), \"No\") == 0);\n assert(strcmp(func0(\"I563_Yes3.txtt\"), \"No\") == 0);\n assert(strcmp(func0(\"final..txt\"), \"No\") == 0);\n assert(strcmp(func0(\"final132\"), \"No\") == 0);\n assert(strcmp(func0(\"_f4indsartal132.\"), \"No\") == 0);\n assert(strcmp(func0(\".txt\"), \"No\") == 0);\n assert(strcmp(func0(\"s.\"), \"No\") == 0);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\nlea r12, unk_2004\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\ncmp eax, 4\njle loc_1C31\nmov rbp, rax\nmovzx eax, byte ptr [rbx]\nlea edx, [rax-5Bh]\ncmp dl, 5\njbe loc_1C40\nsub eax, 41h ; 'A'\ncmp al, 39h ; '9'\nja loc_1C40\nmovsxd rax, ebp\nlea rsi, aFinalTxt+6; s2\nlea r13, [rbx+rax-4]\nmov rdi, r13; s1\ncall _strcmp\ntest eax, eax\njnz loc_1C58\nloc_1832:\nlea eax, [rbp-1]\ncmp eax, 0Eh\njbe loc_1D00\nmov edx, ebp\npxor xmm2, xmm2\npxor xmm4, xmm4\nmov rax, rbx\nshr edx, 4\nmovdqa xmm3, xmm2\npxor xmm5, xmm5\nmovdqa xmm9, cs:xmmword_2650\nshl rdx, 4\nmovdqa xmm7, cs:xmmword_2670\nmovdqa xmm8, cs:xmmword_2660\nmovdqa xmm6, cs:xmmword_2680\nadd rdx, rbx\nnop\nloc_1880:\nmovdqu xmm0, xmmword ptr [rax]\nmovdqa xmm1, xmm8\nmovdqu xmm10, xmmword ptr [rax]\nmovdqa xmm11, xmm4\nadd rax, 10h\npaddb xmm0, xmm9\npcmpeqb xmm10, xmm6\npsubusb xmm1, xmm0\npsubusb xmm0, xmm7\npcmpeqb xmm0, xmm4\npcmpeqb xmm1, xmm4\npcmpeqb xmm0, xmm4\npcmpeqb xmm1, xmm4\npand xmm0, xmm10\npcmpgtb xmm11, xmm0\nmovdqa xmm10, xmm0\npunpcklbw xmm10, xmm11\npunpckhbw xmm0, xmm11\nmovdqa xmm11, xmm5\npcmpgtw xmm11, xmm10\nmovdqa xmm12, xmm10\npunpcklwd xmm12, xmm11\npunpckhwd xmm10, xmm11\nmovdqa xmm11, xmm0\npsubd xmm2, xmm12\npsubd xmm2, xmm10\nmovdqa xmm10, xmm5\npcmpgtw xmm10, xmm0\npunpcklwd xmm11, xmm10\npunpckhwd xmm0, xmm10\nmovdqa xmm10, xmm4\npcmpgtb xmm10, xmm1\npsubd xmm2, xmm11\npsubd xmm2, xmm0\nmovdqa xmm0, xmm1\npunpcklbw xmm0, xmm10\npunpckhbw xmm1, xmm10\nmovdqa xmm10, xmm5\npcmpgtw xmm10, xmm0\nmovdqa xmm11, xmm0\npunpcklwd xmm11, xmm10\npunpckhwd xmm0, xmm10\nmovdqa xmm10, xmm1\npsubd xmm3, xmm11\npsubd xmm3, xmm0\nmovdqa xmm0, xmm5\npcmpgtw xmm0, xmm1\npunpcklwd xmm10, xmm0\npunpckhwd xmm1, xmm0\npsubd xmm3, xmm10\npsubd xmm3, xmm1\ncmp rax, rdx\njnz loc_1880\nmovdqa xmm0, xmm3\nmov edi, ebp\nmovhlps xmm6, xmm3\npsrldq xmm0, 8\nand edi, 0FFFFFFF0h\npaddd xmm6, xmm3\npaddd xmm0, xmm3\nmov edx, edi\nmovdqa xmm1, xmm0\npsrldq xmm1, 4\npaddd xmm0, xmm1\nmovd eax, xmm0\nmovdqa xmm0, xmm2\npsrldq xmm0, 8\npaddd xmm0, xmm2\nmovdqa xmm1, xmm0\npsrldq xmm1, 4\npaddd xmm0, xmm1\nmovdqa xmm1, xmm2\npsrldq xmm2, 8\npaddd xmm1, xmm2\nmovd esi, xmm0\ntest bpl, 0Fh\njz loc_1C20\nloc_19DA:\nmov ecx, ebp\nsub ecx, edi\nlea r8d, [rcx-1]\ncmp r8d, 6\njbe loc_1B18\nmovq xmm0, qword ptr cs:xmmword_2650\nmovq xmm3, qword ptr [rbx+rdi]\nmovq xmm4, qword ptr cs:xmmword_2670\nmovq xmm5, qword ptr cs:xmmword_2680\npaddb xmm0, xmm3\npcmpeqb xmm3, xmm5\nmovdqa xmm2, xmm0\npminub xmm2, xmm4\npcmpeqb xmm2, xmm0\npsubusb xmm0, xmm4\npxor xmm4, xmm4\npcmpeqb xmm0, xmm4\npcmpeqb xmm0, xmm4\npand xmm0, xmm3\nmovdqa xmm3, xmm4\npcmpgtb xmm3, xmm0\npcmpgtb xmm4, xmm2\nmovdqa xmm5, xmm0\npunpcklbw xmm5, xmm3\npunpcklbw xmm0, xmm3\npxor xmm3, xmm3\nmovdqa xmm7, xmm3\nmovdqa xmm8, xmm5\npshufd xmm0, xmm0, 4Eh ; 'N'\npcmpgtw xmm7, xmm5\npunpcklwd xmm8, xmm7\npunpcklwd xmm5, xmm7\nmovdqa xmm7, xmm0\npsubd xmm1, xmm8\npshufd xmm5, xmm5, 4Eh ; 'N'\npsubd xmm1, xmm5\nmovdqa xmm5, xmm3\npcmpgtw xmm5, xmm0\npunpcklwd xmm7, xmm5\npunpcklwd xmm0, xmm5\nmovdqa xmm5, xmm2\npunpcklbw xmm5, xmm4\npunpcklbw xmm2, xmm4\nmovdqa xmm4, xmm3\npcmpgtw xmm4, xmm5\npsubd xmm1, xmm7\nmovdqa xmm7, xmm5\npshufd xmm2, xmm2, 4Eh ; 'N'\npshufd xmm0, xmm0, 4Eh ; 'N'\npcmpgtw xmm3, xmm2\npunpcklwd xmm7, xmm4\npunpcklwd xmm5, xmm4\npsubd xmm1, xmm0\npsubd xmm6, xmm7\npshufd xmm5, xmm5, 4Eh ; 'N'\nmovdqa xmm4, xmm2\npunpcklwd xmm4, xmm3\npunpcklwd xmm2, xmm3\npshufd xmm2, xmm2, 4Eh ; 'N'\nmovdqa xmm0, xmm6\npsubd xmm0, xmm5\npsubd xmm0, xmm4\npsubd xmm0, xmm2\nmovd esi, xmm0\npshufd xmm6, xmm0, 0E5h\nmovd eax, xmm6\npshufd xmm6, xmm1, 0E5h\nadd eax, esi\nmovd edi, xmm6\nmovd esi, xmm1\nadd esi, edi\nmov edi, ecx\nand edi, 0FFFFFFF8h\nadd edx, edi\nand ecx, 7\njz loc_1C20\nloc_1B18:\nmovsxd rcx, edx\nmovzx ecx, byte ptr [rbx+rcx]\nlea edi, [rcx-30h]\ncmp dil, 9\njbe loc_1C90\ncmp cl, 2Eh ; '.'\nsetz cl\nmovzx ecx, cl\nadd esi, ecx\nloc_1B37:\nlea ecx, [rdx+1]\ncmp ebp, ecx\njle loc_1C20\nmovsxd rcx, ecx\nmovzx ecx, byte ptr [rbx+rcx]\nlea edi, [rcx-30h]\ncmp dil, 9\njbe loc_1CA0\ncmp cl, 2Eh ; '.'\nsetz cl\nmovzx ecx, cl\nadd esi, ecx\nloc_1B61:\nlea ecx, [rdx+2]\ncmp ebp, ecx\njle loc_1C20\nmovsxd rcx, ecx\nmovzx ecx, byte ptr [rbx+rcx]\nlea edi, [rcx-30h]\ncmp dil, 9\njbe loc_1CB0\ncmp cl, 2Eh ; '.'\nsetz cl\nmovzx ecx, cl\nadd esi, ecx\nloc_1B8B:\nlea ecx, [rdx+3]\ncmp ebp, ecx\njle loc_1C20\nmovsxd rcx, ecx\nmovzx ecx, byte ptr [rbx+rcx]\nlea edi, [rcx-30h]\ncmp dil, 9\njbe loc_1CC0\ncmp cl, 2Eh ; '.'\nsetz cl\nmovzx ecx, cl\nadd esi, ecx\nloc_1BB5:\nlea ecx, [rdx+4]\ncmp ecx, ebp\njge short loc_1C20\nmovsxd rcx, ecx\nmovzx ecx, byte ptr [rbx+rcx]\nlea edi, [rcx-30h]\ncmp dil, 9\njbe loc_1CD0\ncmp cl, 2Eh ; '.'\nsetz cl\nmovzx ecx, cl\nadd esi, ecx\nloc_1BDB:\nlea ecx, [rdx+5]\ncmp ebp, ecx\njle short loc_1C20\nmovsxd rcx, ecx\nmovzx ecx, byte ptr [rbx+rcx]\nlea edi, [rcx-30h]\ncmp dil, 9\njbe loc_1CE0\ncmp cl, 2Eh ; '.'\nsetz cl\nmovzx ecx, cl\nadd esi, ecx\nloc_1C01:\nadd edx, 6\ncmp ebp, edx\njle short loc_1C20\nmovsxd rdx, edx\nmovzx edx, byte ptr [rbx+rdx]\nlea ecx, [rdx-30h]\ncmp cl, 9\nja loc_1CF0\nadd eax, 1\nxchg ax, ax\nloc_1C20:\ncmp eax, 3\njg short loc_1C40\nlea r12, s2; \"Yes\"\ncmp esi, 1\njnz short loc_1C40\nloc_1C31:\nadd rsp, 8\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1C40:\nadd rsp, 8\nlea r12, unk_2004\npop rbx\nmov rax, r12\npop rbp\npop r12\npop r13\nretn\nloc_1C58:\nlea rsi, aMy16file3Exe+9; s2\nmov rdi, r13; s1\ncall _strcmp\ntest eax, eax\njz loc_1832\nlea rsi, aKDll+1; s2\nmov rdi, r13; s1\ncall _strcmp\ntest eax, eax\njz loc_1832\njmp short loc_1C31\nloc_1C90:\nadd eax, 1\njmp loc_1B37\nloc_1CA0:\nadd eax, 1\njmp loc_1B61\nloc_1CB0:\nadd eax, 1\njmp loc_1B8B\nloc_1CC0:\nadd eax, 1\njmp loc_1BB5\nloc_1CD0:\nadd eax, 1\njmp loc_1BDB\nloc_1CE0:\nadd eax, 1\njmp loc_1C01\nloc_1CF0:\ncmp dl, 2Eh ; '.'\nsetz dl\nmovzx edx, dl\nadd esi, edx\njmp loc_1C20\nloc_1D00:\npxor xmm1, xmm1\nxor edi, edi\nxor edx, edx\nxor esi, esi\nmovdqa xmm6, xmm1\nxor eax, eax\njmp loc_19DA", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n const char *v1; // r12\n int v3; // eax\n int v4; // ebp\n __m128i v5; // xmm2\n const __m128i *v6; // rax\n __m128 v7; // xmm3\n __m128i si128; // xmm9\n __m128i v9; // xmm7\n __m128i v10; // xmm8\n __m128 v11; // xmm6\n __m128i v12; // xmm0\n __m128i v13; // xmm10\n __m128i v14; // xmm0\n __m128i v15; // xmm1\n __m128i v16; // xmm0\n __m128i v17; // xmm11\n __m128i v18; // xmm10\n __m128i v19; // xmm0\n __m128i v20; // xmm11\n __m128i v21; // xmm2\n __m128i v22; // xmm10\n __m128i v23; // xmm11\n __m128i v24; // xmm0\n __m128i v25; // xmm10\n __m128i v26; // xmm0\n __m128i v27; // xmm1\n __m128i v28; // xmm10\n __m128i v29; // xmm3\n __m128i v30; // xmm0\n __int64 v31; // rdi\n __m128i v32; // xmm6\n __m128i v33; // xmm0\n signed int v34; // edx\n int v35; // eax\n __m128i v36; // xmm0\n __m128i v37; // xmm1\n int v38; // esi\n int v39; // ecx\n __m128i v40; // xmm3\n __m128i v41; // xmm4\n __m128i v42; // xmm0\n __m128i v43; // xmm2\n __m128i v44; // xmm0\n __m128i v45; // xmm5\n __m128i v46; // xmm0\n __m128i v47; // xmm5\n __m128i v48; // xmm1\n __m128i v49; // xmm0\n __m128i v50; // xmm5\n __m128i v51; // xmm2\n __m128i v52; // xmm5\n __m128i v53; // xmm1\n __m128i v54; // xmm4\n __m128i v55; // xmm0\n char v56; // cl\n char v57; // cl\n char v58; // cl\n char v59; // cl\n char v60; // cl\n char v61; // cl\n int v62; // edx\n char v63; // dl\n\n v1 = (const char *)&unk_2004;\n v3 = strlen(a1);\n if ( v3 <= 4 )\n return v1;\n v4 = v3;\n if ( (unsigned __int8)(*a1 - 91) <= 5u || (unsigned __int8)(*a1 - 65) > 0x39u )\n return (const char *)&unk_2004;\n if ( strcmp(&a1[v3 - 4], \".txt\") && strcmp(&a1[v4 - 4], \".exe\") && strcmp(&a1[v4 - 4], \".dll\") )\n return v1;\n if ( (unsigned int)(v4 - 1) <= 0xE )\n {\n v37 = 0LL;\n v31 = 0LL;\n v34 = 0;\n v38 = 0;\n v32 = 0LL;\n v35 = 0;\n }\n else\n {\n v5 = 0LL;\n v6 = (const __m128i *)a1;\n v7 = 0LL;\n si128 = _mm_load_si128((const __m128i *)&xmmword_2650);\n v9 = _mm_load_si128((const __m128i *)&xmmword_2670);\n v10 = _mm_load_si128((const __m128i *)&xmmword_2660);\n v11 = (__m128)_mm_load_si128((const __m128i *)&xmmword_2680);\n do\n {\n v12 = _mm_loadu_si128(v6);\n v13 = v12;\n ++v6;\n v14 = _mm_add_epi8(v12, si128);\n v15 = _mm_cmpeq_epi8(_mm_cmpeq_epi8(_mm_subs_epu8(v10, v14), (__m128i)0LL), (__m128i)0LL);\n v16 = _mm_and_si128(\n _mm_cmpeq_epi8(_mm_cmpeq_epi8(_mm_subs_epu8(v14, v9), (__m128i)0LL), (__m128i)0LL),\n _mm_cmpeq_epi8(v13, (__m128i)v11));\n v17 = _mm_cmpgt_epi8((__m128i)0LL, v16);\n v18 = _mm_unpacklo_epi8(v16, v17);\n v19 = _mm_unpackhi_epi8(v16, v17);\n v20 = _mm_cmpgt_epi16((__m128i)0LL, v18);\n v21 = _mm_sub_epi32(_mm_sub_epi32(v5, _mm_unpacklo_epi16(v18, v20)), _mm_unpackhi_epi16(v18, v20));\n v22 = _mm_cmpgt_epi16((__m128i)0LL, v19);\n v23 = _mm_unpacklo_epi16(v19, v22);\n v24 = _mm_unpackhi_epi16(v19, v22);\n v25 = _mm_cmpgt_epi8((__m128i)0LL, v15);\n v5 = _mm_sub_epi32(_mm_sub_epi32(v21, v23), v24);\n v26 = _mm_unpacklo_epi8(v15, v25);\n v27 = _mm_unpackhi_epi8(v15, v25);\n v28 = _mm_cmpgt_epi16((__m128i)0LL, v26);\n v29 = _mm_sub_epi32(_mm_sub_epi32((__m128i)v7, _mm_unpacklo_epi16(v26, v28)), _mm_unpackhi_epi16(v26, v28));\n v30 = _mm_cmpgt_epi16((__m128i)0LL, v27);\n v7 = (__m128)_mm_sub_epi32(_mm_sub_epi32(v29, _mm_unpacklo_epi16(v27, v30)), _mm_unpackhi_epi16(v27, v30));\n }\n while ( v6 != (const __m128i *)&a1[16 * ((unsigned int)v4 >> 4)] );\n v31 = v4 & 0xFFFFFFF0;\n v32 = _mm_add_epi32((__m128i)_mm_movehl_ps(v11, v7), (__m128i)v7);\n v33 = _mm_add_epi32(_mm_srli_si128((__m128i)v7, 8), (__m128i)v7);\n v34 = v4 & 0xFFFFFFF0;\n v35 = _mm_cvtsi128_si32(_mm_add_epi32(v33, _mm_srli_si128(v33, 4)));\n v36 = _mm_add_epi32(_mm_srli_si128(v5, 8), v5);\n v37 = _mm_add_epi32(v5, _mm_srli_si128(v5, 8));\n v38 = _mm_cvtsi128_si32(_mm_add_epi32(v36, _mm_srli_si128(v36, 4)));\n if ( (v4 & 0xF) == 0 )\n goto LABEL_31;\n }\n v39 = v4 - v31;\n if ( (unsigned int)(v4 - v31 - 1) <= 6 )\n goto LABEL_25;\n v40 = _mm_loadl_epi64((const __m128i *)&a1[v31]);\n v41 = _mm_loadl_epi64((const __m128i *)&xmmword_2670);\n v42 = _mm_add_epi8(_mm_loadl_epi64((const __m128i *)&xmmword_2650), v40);\n v43 = _mm_cmpeq_epi8(_mm_min_epu8(v42, v41), v42);\n v44 = _mm_and_si128(\n _mm_cmpeq_epi8(_mm_cmpeq_epi8(_mm_subs_epu8(v42, v41), (__m128i)0LL), (__m128i)0LL),\n _mm_cmpeq_epi8(v40, _mm_loadl_epi64((const __m128i *)&xmmword_2680)));\n v45 = _mm_unpacklo_epi8(v44, _mm_cmpgt_epi8((__m128i)0LL, v44));\n v46 = _mm_shuffle_epi32(v45, 78);\n v47 = _mm_unpacklo_epi16(v45, _mm_cmpgt_epi16((__m128i)0LL, v45));\n v48 = _mm_sub_epi32(_mm_sub_epi32(v37, v47), _mm_shuffle_epi32(v47, 78));\n v49 = _mm_unpacklo_epi16(v46, _mm_cmpgt_epi16((__m128i)0LL, v46));\n v50 = _mm_unpacklo_epi8(v43, _mm_cmpgt_epi8((__m128i)0LL, v43));\n v51 = _mm_shuffle_epi32(v50, 78);\n v52 = _mm_unpacklo_epi16(v50, _mm_cmpgt_epi16((__m128i)0LL, v50));\n v53 = _mm_sub_epi32(_mm_sub_epi32(v48, v49), _mm_shuffle_epi32(v49, 78));\n v54 = _mm_unpacklo_epi16(v51, _mm_cmpgt_epi16((__m128i)0LL, v51));\n v55 = _mm_sub_epi32(\n _mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(v32, v52), _mm_shuffle_epi32(v52, 78)), v54),\n _mm_shuffle_epi32(v54, 78));\n v35 = _mm_cvtsi128_si32(v55) + _mm_cvtsi128_si32(_mm_shuffle_epi32(v55, 229));\n v38 = _mm_cvtsi128_si32(_mm_shuffle_epi32(v53, 229)) + _mm_cvtsi128_si32(v53);\n v34 += v39 & 0xFFFFFFF8;\n if ( (v39 & 7) != 0 )\n {\nLABEL_25:\n v56 = a1[v34];\n if ( (unsigned __int8)(v56 - 48) <= 9u )\n ++v35;\n else\n v38 += v56 == 46;\n if ( v4 > v34 + 1 )\n {\n v57 = a1[v34 + 1];\n if ( (unsigned __int8)(v57 - 48) <= 9u )\n ++v35;\n else\n v38 += v57 == 46;\n if ( v4 > v34 + 2 )\n {\n v58 = a1[v34 + 2];\n if ( (unsigned __int8)(v58 - 48) <= 9u )\n ++v35;\n else\n v38 += v58 == 46;\n if ( v4 > v34 + 3 )\n {\n v59 = a1[v34 + 3];\n if ( (unsigned __int8)(v59 - 48) <= 9u )\n ++v35;\n else\n v38 += v59 == 46;\n if ( v34 + 4 < v4 )\n {\n v60 = a1[v34 + 4];\n if ( (unsigned __int8)(v60 - 48) <= 9u )\n ++v35;\n else\n v38 += v60 == 46;\n if ( v4 > v34 + 5 )\n {\n v61 = a1[v34 + 5];\n if ( (unsigned __int8)(v61 - 48) <= 9u )\n ++v35;\n else\n v38 += v61 == 46;\n v62 = v34 + 6;\n if ( v4 > v62 )\n {\n v63 = a1[v62];\n if ( (unsigned __int8)(v63 - 48) > 9u )\n v38 += v63 == 46;\n else\n ++v35;\n }\n }\n }\n }\n }\n }\n }\nLABEL_31:\n if ( v35 <= 3 )\n {\n v1 = \"Yes\";\n if ( v38 == 1 )\n return v1;\n }\n return (const char *)&unk_2004;\n}", + "ida_strip_asm": "sub_17D0:\nendbr64\npush r13\npush r12\nlea r12, unk_2004\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\ncmp eax, 4\njle loc_1C31\nmov rbp, rax\nmovzx eax, byte ptr [rbx]\nlea edx, [rax-5Bh]\ncmp dl, 5\njbe loc_1C40\nsub eax, 41h ; 'A'\ncmp al, 39h ; '9'\nja loc_1C40\nmovsxd rax, ebp\nlea rsi, aFinalTxt+6; s2\nlea r13, [rbx+rax-4]\nmov rdi, r13; s1\ncall _strcmp\ntest eax, eax\njnz loc_1C58\nloc_1832:\nlea eax, [rbp-1]\ncmp eax, 0Eh\njbe loc_1D00\nmov edx, ebp\npxor xmm2, xmm2\npxor xmm4, xmm4\nmov rax, rbx\nshr edx, 4\nmovdqa xmm3, xmm2\npxor xmm5, xmm5\nmovdqa xmm9, cs:xmmword_2650\nshl rdx, 4\nmovdqa xmm7, cs:xmmword_2670\nmovdqa xmm8, cs:xmmword_2660\nmovdqa xmm6, cs:xmmword_2680\nadd rdx, rbx\nnop\nloc_1880:\nmovdqu xmm0, xmmword ptr [rax]\nmovdqa xmm1, xmm8\nmovdqu xmm10, xmmword ptr [rax]\nmovdqa xmm11, xmm4\nadd rax, 10h\npaddb xmm0, xmm9\npcmpeqb xmm10, xmm6\npsubusb xmm1, xmm0\npsubusb xmm0, xmm7\npcmpeqb xmm0, xmm4\npcmpeqb xmm1, xmm4\npcmpeqb xmm0, xmm4\npcmpeqb xmm1, xmm4\npand xmm0, xmm10\npcmpgtb xmm11, xmm0\nmovdqa xmm10, xmm0\npunpcklbw xmm10, xmm11\npunpckhbw xmm0, xmm11\nmovdqa xmm11, xmm5\npcmpgtw xmm11, xmm10\nmovdqa xmm12, xmm10\npunpcklwd xmm12, xmm11\npunpckhwd xmm10, xmm11\nmovdqa xmm11, xmm0\npsubd xmm2, xmm12\npsubd xmm2, xmm10\nmovdqa xmm10, xmm5\npcmpgtw xmm10, xmm0\npunpcklwd xmm11, xmm10\npunpckhwd xmm0, xmm10\nmovdqa xmm10, xmm4\npcmpgtb xmm10, xmm1\npsubd xmm2, xmm11\npsubd xmm2, xmm0\nmovdqa xmm0, xmm1\npunpcklbw xmm0, xmm10\npunpckhbw xmm1, xmm10\nmovdqa xmm10, xmm5\npcmpgtw xmm10, xmm0\nmovdqa xmm11, xmm0\npunpcklwd xmm11, xmm10\npunpckhwd xmm0, xmm10\nmovdqa xmm10, xmm1\npsubd xmm3, xmm11\npsubd xmm3, xmm0\nmovdqa xmm0, xmm5\npcmpgtw xmm0, xmm1\npunpcklwd xmm10, xmm0\npunpckhwd xmm1, xmm0\npsubd xmm3, xmm10\npsubd xmm3, xmm1\ncmp rax, rdx\njnz loc_1880\nmovdqa xmm0, xmm3\nmov edi, ebp\nmovhlps xmm6, xmm3\npsrldq xmm0, 8\nand edi, 0FFFFFFF0h\npaddd xmm6, xmm3\npaddd xmm0, xmm3\nmov edx, edi\nmovdqa xmm1, xmm0\npsrldq xmm1, 4\npaddd xmm0, xmm1\nmovd eax, xmm0\nmovdqa xmm0, xmm2\npsrldq xmm0, 8\npaddd xmm0, xmm2\nmovdqa xmm1, xmm0\npsrldq xmm1, 4\npaddd xmm0, xmm1\nmovdqa xmm1, xmm2\npsrldq xmm2, 8\npaddd xmm1, xmm2\nmovd esi, xmm0\ntest bpl, 0Fh\njz loc_1C20\nloc_19DA:\nmov ecx, ebp\nsub ecx, edi\nlea r8d, [rcx-1]\ncmp r8d, 6\njbe loc_1B18\nmovq xmm0, qword ptr cs:xmmword_2650\nmovq xmm3, qword ptr [rbx+rdi]\nmovq xmm4, qword ptr cs:xmmword_2670\nmovq xmm5, qword ptr cs:xmmword_2680\npaddb xmm0, xmm3\npcmpeqb xmm3, xmm5\nmovdqa xmm2, xmm0\npminub xmm2, xmm4\npcmpeqb xmm2, xmm0\npsubusb xmm0, xmm4\npxor xmm4, xmm4\npcmpeqb xmm0, xmm4\npcmpeqb xmm0, xmm4\npand xmm0, xmm3\nmovdqa xmm3, xmm4\npcmpgtb xmm3, xmm0\npcmpgtb xmm4, xmm2\nmovdqa xmm5, xmm0\npunpcklbw xmm5, xmm3\npunpcklbw xmm0, xmm3\npxor xmm3, xmm3\nmovdqa xmm7, xmm3\nmovdqa xmm8, xmm5\npshufd xmm0, xmm0, 4Eh ; 'N'\npcmpgtw xmm7, xmm5\npunpcklwd xmm8, xmm7\npunpcklwd xmm5, xmm7\nmovdqa xmm7, xmm0\npsubd xmm1, xmm8\npshufd xmm5, xmm5, 4Eh ; 'N'\npsubd xmm1, xmm5\nmovdqa xmm5, xmm3\npcmpgtw xmm5, xmm0\npunpcklwd xmm7, xmm5\npunpcklwd xmm0, xmm5\nmovdqa xmm5, xmm2\npunpcklbw xmm5, xmm4\npunpcklbw xmm2, xmm4\nmovdqa xmm4, xmm3\npcmpgtw xmm4, xmm5\npsubd xmm1, xmm7\nmovdqa xmm7, xmm5\npshufd xmm2, xmm2, 4Eh ; 'N'\npshufd xmm0, xmm0, 4Eh ; 'N'\npcmpgtw xmm3, xmm2\npunpcklwd xmm7, xmm4\npunpcklwd xmm5, xmm4\npsubd xmm1, xmm0\npsubd xmm6, xmm7\npshufd xmm5, xmm5, 4Eh ; 'N'\nmovdqa xmm4, xmm2\npunpcklwd xmm4, xmm3\npunpcklwd xmm2, xmm3\npshufd xmm2, xmm2, 4Eh ; 'N'\nmovdqa xmm0, xmm6\npsubd xmm0, xmm5\npsubd xmm0, xmm4\npsubd xmm0, xmm2\nmovd esi, xmm0\npshufd xmm6, xmm0, 0E5h\nmovd eax, xmm6\npshufd xmm6, xmm1, 0E5h\nadd eax, esi\nmovd edi, xmm6\nmovd esi, xmm1\nadd esi, edi\nmov edi, ecx\nand edi, 0FFFFFFF8h\nadd edx, edi\nand ecx, 7\njz loc_1C20\nloc_1B18:\nmovsxd rcx, edx\nmovzx ecx, byte ptr [rbx+rcx]\nlea edi, [rcx-30h]\ncmp dil, 9\njbe loc_1C90\ncmp cl, 2Eh ; '.'\nsetz cl\nmovzx ecx, cl\nadd esi, ecx\nloc_1B37:\nlea ecx, [rdx+1]\ncmp ebp, ecx\njle loc_1C20\nmovsxd rcx, ecx\nmovzx ecx, byte ptr [rbx+rcx]\nlea edi, [rcx-30h]\ncmp dil, 9\njbe loc_1CA0\ncmp cl, 2Eh ; '.'\nsetz cl\nmovzx ecx, cl\nadd esi, ecx\nloc_1B61:\nlea ecx, [rdx+2]\ncmp ebp, ecx\njle loc_1C20\nmovsxd rcx, ecx\nmovzx ecx, byte ptr [rbx+rcx]\nlea edi, [rcx-30h]\ncmp dil, 9\njbe loc_1CB0\ncmp cl, 2Eh ; '.'\nsetz cl\nmovzx ecx, cl\nadd esi, ecx\nloc_1B8B:\nlea ecx, [rdx+3]\ncmp ebp, ecx\njle loc_1C20\nmovsxd rcx, ecx\nmovzx ecx, byte ptr [rbx+rcx]\nlea edi, [rcx-30h]\ncmp dil, 9\njbe loc_1CC0\ncmp cl, 2Eh ; '.'\nsetz cl\nmovzx ecx, cl\nadd esi, ecx\nloc_1BB5:\nlea ecx, [rdx+4]\ncmp ecx, ebp\njge short loc_1C20\nmovsxd rcx, ecx\nmovzx ecx, byte ptr [rbx+rcx]\nlea edi, [rcx-30h]\ncmp dil, 9\njbe loc_1CD0\ncmp cl, 2Eh ; '.'\nsetz cl\nmovzx ecx, cl\nadd esi, ecx\nloc_1BDB:\nlea ecx, [rdx+5]\ncmp ebp, ecx\njle short loc_1C20\nmovsxd rcx, ecx\nmovzx ecx, byte ptr [rbx+rcx]\nlea edi, [rcx-30h]\ncmp dil, 9\njbe loc_1CE0\ncmp cl, 2Eh ; '.'\nsetz cl\nmovzx ecx, cl\nadd esi, ecx\nloc_1C01:\nadd edx, 6\ncmp ebp, edx\njle short loc_1C20\nmovsxd rdx, edx\nmovzx edx, byte ptr [rbx+rdx]\nlea ecx, [rdx-30h]\ncmp cl, 9\nja loc_1CF0\nadd eax, 1\nxchg ax, ax\nloc_1C20:\ncmp eax, 3\njg short loc_1C40\nlea r12, s2; \"Yes\"\ncmp esi, 1\njnz short loc_1C40\nloc_1C31:\nadd rsp, 8\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1C40:\nadd rsp, 8\nlea r12, unk_2004\npop rbx\nmov rax, r12\npop rbp\npop r12\npop r13\nretn\nloc_1C58:\nlea rsi, aMy16file3Exe+9; s2\nmov rdi, r13; s1\ncall _strcmp\ntest eax, eax\njz loc_1832\nlea rsi, aKDll+1; s2\nmov rdi, r13; s1\ncall _strcmp\ntest eax, eax\njz loc_1832\njmp short loc_1C31\nloc_1C90:\nadd eax, 1\njmp loc_1B37\nloc_1CA0:\nadd eax, 1\njmp loc_1B61\nloc_1CB0:\nadd eax, 1\njmp loc_1B8B\nloc_1CC0:\nadd eax, 1\njmp loc_1BB5\nloc_1CD0:\nadd eax, 1\njmp loc_1BDB\nloc_1CE0:\nadd eax, 1\njmp loc_1C01\nloc_1CF0:\ncmp dl, 2Eh ; '.'\nsetz dl\nmovzx edx, dl\nadd esi, edx\njmp loc_1C20\nloc_1D00:\npxor xmm1, xmm1\nxor edi, edi\nxor edx, edx\nxor esi, esi\nmovdqa xmm6, xmm1\nxor eax, eax\njmp loc_19DA", + "ida_strip_pseudo": "const char *__fastcall sub_17D0(const char *a1)\n{\n const char *v1; // r12\n int v3; // eax\n int v4; // ebp\n __m128i v5; // xmm2\n const __m128i *v6; // rax\n __m128 v7; // xmm3\n __m128i si128; // xmm9\n __m128i v9; // xmm7\n __m128i v10; // xmm8\n __m128 v11; // xmm6\n __m128i v12; // xmm0\n __m128i v13; // xmm10\n __m128i v14; // xmm0\n __m128i v15; // xmm1\n __m128i v16; // xmm0\n __m128i v17; // xmm11\n __m128i v18; // xmm10\n __m128i v19; // xmm0\n __m128i v20; // xmm11\n __m128i v21; // xmm2\n __m128i v22; // xmm10\n __m128i v23; // xmm11\n __m128i v24; // xmm0\n __m128i v25; // xmm10\n __m128i v26; // xmm0\n __m128i v27; // xmm1\n __m128i v28; // xmm10\n __m128i v29; // xmm3\n __m128i v30; // xmm0\n __int64 v31; // rdi\n __m128i v32; // xmm6\n __m128i v33; // xmm0\n signed int v34; // edx\n int v35; // eax\n __m128i v36; // xmm0\n __m128i v37; // xmm1\n int v38; // esi\n int v39; // ecx\n __m128i v40; // xmm3\n __m128i v41; // xmm4\n __m128i v42; // xmm0\n __m128i v43; // xmm2\n __m128i v44; // xmm0\n __m128i v45; // xmm5\n __m128i v46; // xmm0\n __m128i v47; // xmm5\n __m128i v48; // xmm1\n __m128i v49; // xmm0\n __m128i v50; // xmm5\n __m128i v51; // xmm2\n __m128i v52; // xmm5\n __m128i v53; // xmm1\n __m128i v54; // xmm4\n __m128i v55; // xmm0\n char v56; // cl\n char v57; // cl\n char v58; // cl\n char v59; // cl\n char v60; // cl\n char v61; // cl\n int v62; // edx\n char v63; // dl\n\n v1 = (const char *)&unk_2004;\n v3 = strlen(a1);\n if ( v3 <= 4 )\n return v1;\n v4 = v3;\n if ( (unsigned __int8)(*a1 - 91) <= 5u || (unsigned __int8)(*a1 - 65) > 0x39u )\n return (const char *)&unk_2004;\n if ( strcmp(&a1[v3 - 4], \".txt\") && strcmp(&a1[v4 - 4], \".exe\") && strcmp(&a1[v4 - 4], \".dll\") )\n return v1;\n if ( (unsigned int)(v4 - 1) <= 0xE )\n {\n v37 = 0LL;\n v31 = 0LL;\n v34 = 0;\n v38 = 0;\n v32 = 0LL;\n v35 = 0;\n }\n else\n {\n v5 = 0LL;\n v6 = (const __m128i *)a1;\n v7 = 0LL;\n si128 = _mm_load_si128((const __m128i *)&xmmword_2650);\n v9 = _mm_load_si128((const __m128i *)&xmmword_2670);\n v10 = _mm_load_si128((const __m128i *)&xmmword_2660);\n v11 = (__m128)_mm_load_si128((const __m128i *)&xmmword_2680);\n do\n {\n v12 = _mm_loadu_si128(v6);\n v13 = v12;\n ++v6;\n v14 = _mm_add_epi8(v12, si128);\n v15 = _mm_cmpeq_epi8(_mm_cmpeq_epi8(_mm_subs_epu8(v10, v14), (__m128i)0LL), (__m128i)0LL);\n v16 = _mm_and_si128(\n _mm_cmpeq_epi8(_mm_cmpeq_epi8(_mm_subs_epu8(v14, v9), (__m128i)0LL), (__m128i)0LL),\n _mm_cmpeq_epi8(v13, (__m128i)v11));\n v17 = _mm_cmpgt_epi8((__m128i)0LL, v16);\n v18 = _mm_unpacklo_epi8(v16, v17);\n v19 = _mm_unpackhi_epi8(v16, v17);\n v20 = _mm_cmpgt_epi16((__m128i)0LL, v18);\n v21 = _mm_sub_epi32(_mm_sub_epi32(v5, _mm_unpacklo_epi16(v18, v20)), _mm_unpackhi_epi16(v18, v20));\n v22 = _mm_cmpgt_epi16((__m128i)0LL, v19);\n v23 = _mm_unpacklo_epi16(v19, v22);\n v24 = _mm_unpackhi_epi16(v19, v22);\n v25 = _mm_cmpgt_epi8((__m128i)0LL, v15);\n v5 = _mm_sub_epi32(_mm_sub_epi32(v21, v23), v24);\n v26 = _mm_unpacklo_epi8(v15, v25);\n v27 = _mm_unpackhi_epi8(v15, v25);\n v28 = _mm_cmpgt_epi16((__m128i)0LL, v26);\n v29 = _mm_sub_epi32(_mm_sub_epi32((__m128i)v7, _mm_unpacklo_epi16(v26, v28)), _mm_unpackhi_epi16(v26, v28));\n v30 = _mm_cmpgt_epi16((__m128i)0LL, v27);\n v7 = (__m128)_mm_sub_epi32(_mm_sub_epi32(v29, _mm_unpacklo_epi16(v27, v30)), _mm_unpackhi_epi16(v27, v30));\n }\n while ( v6 != (const __m128i *)&a1[16 * ((unsigned int)v4 >> 4)] );\n v31 = v4 & 0xFFFFFFF0;\n v32 = _mm_add_epi32((__m128i)_mm_movehl_ps(v11, v7), (__m128i)v7);\n v33 = _mm_add_epi32(_mm_srli_si128((__m128i)v7, 8), (__m128i)v7);\n v34 = v4 & 0xFFFFFFF0;\n v35 = _mm_cvtsi128_si32(_mm_add_epi32(v33, _mm_srli_si128(v33, 4)));\n v36 = _mm_add_epi32(_mm_srli_si128(v5, 8), v5);\n v37 = _mm_add_epi32(v5, _mm_srli_si128(v5, 8));\n v38 = _mm_cvtsi128_si32(_mm_add_epi32(v36, _mm_srli_si128(v36, 4)));\n if ( (v4 & 0xF) == 0 )\n goto LABEL_31;\n }\n v39 = v4 - v31;\n if ( (unsigned int)(v4 - v31 - 1) <= 6 )\n goto LABEL_25;\n v40 = _mm_loadl_epi64((const __m128i *)&a1[v31]);\n v41 = _mm_loadl_epi64((const __m128i *)&xmmword_2670);\n v42 = _mm_add_epi8(_mm_loadl_epi64((const __m128i *)&xmmword_2650), v40);\n v43 = _mm_cmpeq_epi8(_mm_min_epu8(v42, v41), v42);\n v44 = _mm_and_si128(\n _mm_cmpeq_epi8(_mm_cmpeq_epi8(_mm_subs_epu8(v42, v41), (__m128i)0LL), (__m128i)0LL),\n _mm_cmpeq_epi8(v40, _mm_loadl_epi64((const __m128i *)&xmmword_2680)));\n v45 = _mm_unpacklo_epi8(v44, _mm_cmpgt_epi8((__m128i)0LL, v44));\n v46 = _mm_shuffle_epi32(v45, 78);\n v47 = _mm_unpacklo_epi16(v45, _mm_cmpgt_epi16((__m128i)0LL, v45));\n v48 = _mm_sub_epi32(_mm_sub_epi32(v37, v47), _mm_shuffle_epi32(v47, 78));\n v49 = _mm_unpacklo_epi16(v46, _mm_cmpgt_epi16((__m128i)0LL, v46));\n v50 = _mm_unpacklo_epi8(v43, _mm_cmpgt_epi8((__m128i)0LL, v43));\n v51 = _mm_shuffle_epi32(v50, 78);\n v52 = _mm_unpacklo_epi16(v50, _mm_cmpgt_epi16((__m128i)0LL, v50));\n v53 = _mm_sub_epi32(_mm_sub_epi32(v48, v49), _mm_shuffle_epi32(v49, 78));\n v54 = _mm_unpacklo_epi16(v51, _mm_cmpgt_epi16((__m128i)0LL, v51));\n v55 = _mm_sub_epi32(\n _mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(v32, v52), _mm_shuffle_epi32(v52, 78)), v54),\n _mm_shuffle_epi32(v54, 78));\n v35 = _mm_cvtsi128_si32(v55) + _mm_cvtsi128_si32(_mm_shuffle_epi32(v55, 229));\n v38 = _mm_cvtsi128_si32(_mm_shuffle_epi32(v53, 229)) + _mm_cvtsi128_si32(v53);\n v34 += v39 & 0xFFFFFFF8;\n if ( (v39 & 7) != 0 )\n {\nLABEL_25:\n v56 = a1[v34];\n if ( (unsigned __int8)(v56 - 48) <= 9u )\n ++v35;\n else\n v38 += v56 == 46;\n if ( v4 > v34 + 1 )\n {\n v57 = a1[v34 + 1];\n if ( (unsigned __int8)(v57 - 48) <= 9u )\n ++v35;\n else\n v38 += v57 == 46;\n if ( v4 > v34 + 2 )\n {\n v58 = a1[v34 + 2];\n if ( (unsigned __int8)(v58 - 48) <= 9u )\n ++v35;\n else\n v38 += v58 == 46;\n if ( v4 > v34 + 3 )\n {\n v59 = a1[v34 + 3];\n if ( (unsigned __int8)(v59 - 48) <= 9u )\n ++v35;\n else\n v38 += v59 == 46;\n if ( v34 + 4 < v4 )\n {\n v60 = a1[v34 + 4];\n if ( (unsigned __int8)(v60 - 48) <= 9u )\n ++v35;\n else\n v38 += v60 == 46;\n if ( v4 > v34 + 5 )\n {\n v61 = a1[v34 + 5];\n if ( (unsigned __int8)(v61 - 48) <= 9u )\n ++v35;\n else\n v38 += v61 == 46;\n v62 = v34 + 6;\n if ( v4 > v62 )\n {\n v63 = a1[v62];\n if ( (unsigned __int8)(v63 - 48) > 9u )\n v38 += v63 == 46;\n else\n ++v35;\n }\n }\n }\n }\n }\n }\n }\nLABEL_31:\n if ( v35 <= 3 )\n {\n v1 = \"Yes\";\n if ( v38 == 1 )\n return v1;\n }\n return (const char *)&unk_2004;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_17D0(const char *a1) {\n const char *v1;\n int v3;\n int v4;\n __m128i v5;\n const __m128i *v6;\n __m128 v7;\n __m128i si128;\n __m128i v9;\n __m128i v10;\n __m128 v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n __m128i v15;\n __m128i v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n __m128i v20;\n __m128i v21;\n __m128i v22;\n __m128i v23;\n __m128i v24;\n __m128i v25;\n __m128i v26;\n __m128i v27;\n __m128i v28;\n __m128i v29;\n __m128i v30;\n long long v31;\n __m128i v32;\n __m128i v33;\n signed int v34;\n int v35;\n __m128i v36;\n __m128i v37;\n int v38;\n int v39;\n __m128i v40;\n __m128i v41;\n __m128i v42;\n __m128i v43;\n __m128i v44;\n __m128i v45;\n __m128i v46;\n __m128i v47;\n __m128i v48;\n __m128i v49;\n __m128i v50;\n __m128i v51;\n __m128i v52;\n __m128i v53;\n __m128i v54;\n __m128i v55;\n char v56;\n char v57;\n char v58;\n char v59;\n char v60;\n char v61;\n int v62;\n char v63;\n v1 = (const char *)&unk_2004;\n v3 = strlen(a1);\n if (v3 <= 4) return v1;\n v4 = v3;\n if ((unsigned char)(*a1 - 91) <= 5u || (unsigned char)(*a1 - 65) > 57u)\n return (const char *)&unk_2004;\n if (strcmp(&a1[v3 - 4], \".txt\") && strcmp(&a1[v4 - 4], \".exe\") &&\n strcmp(&a1[v4 - 4], \".dll\"))\n return v1;\n if ((unsigned int)(v4 - 1) <= 14) {\n v37 = 0LL;\n v31 = 0LL;\n v34 = 0;\n v38 = 0;\n v32 = 0LL;\n v35 = 0;\n } else {\n v5 = 0LL;\n v6 = (const __m128i *)a1;\n v7 = 0LL;\n si128 = _mm_load_si128((const __m128i *)&xmmword_2650);\n v9 = _mm_load_si128((const __m128i *)&xmmword_2670);\n v10 = _mm_load_si128((const __m128i *)&xmmword_2660);\n v11 = (__m128)_mm_load_si128((const __m128i *)&xmmword_2680);\n do {\n v12 = _mm_loadu_si128(v6);\n v13 = v12;\n ++v6;\n v14 = _mm_add_epi8(v12, si128);\n v15 = _mm_cmpeq_epi8(\n _mm_cmpeq_epi8(_mm_subs_epu8(v10, v14), (__m128i)0LL), (__m128i)0LL);\n v16 = _mm_and_si128(\n _mm_cmpeq_epi8(_mm_cmpeq_epi8(_mm_subs_epu8(v14, v9), (__m128i)0LL),\n (__m128i)0LL),\n _mm_cmpeq_epi8(v13, (__m128i)v11));\n v17 = _mm_cmpgt_epi8((__m128i)0LL, v16);\n v18 = _mm_unpacklo_epi8(v16, v17);\n v19 = _mm_unpackhi_epi8(v16, v17);\n v20 = _mm_cmpgt_epi16((__m128i)0LL, v18);\n v21 = _mm_sub_epi32(_mm_sub_epi32(v5, _mm_unpacklo_epi16(v18, v20)),\n _mm_unpackhi_epi16(v18, v20));\n v22 = _mm_cmpgt_epi16((__m128i)0LL, v19);\n v23 = _mm_unpacklo_epi16(v19, v22);\n v24 = _mm_unpackhi_epi16(v19, v22);\n v25 = _mm_cmpgt_epi8((__m128i)0LL, v15);\n v5 = _mm_sub_epi32(_mm_sub_epi32(v21, v23), v24);\n v26 = _mm_unpacklo_epi8(v15, v25);\n v27 = _mm_unpackhi_epi8(v15, v25);\n v28 = _mm_cmpgt_epi16((__m128i)0LL, v26);\n v29 = _mm_sub_epi32(\n _mm_sub_epi32((__m128i)v7, _mm_unpacklo_epi16(v26, v28)),\n _mm_unpackhi_epi16(v26, v28));\n v30 = _mm_cmpgt_epi16((__m128i)0LL, v27);\n v7 = (__m128)_mm_sub_epi32(\n _mm_sub_epi32(v29, _mm_unpacklo_epi16(v27, v30)),\n _mm_unpackhi_epi16(v27, v30));\n } while (v6 != (const __m128i *)&a1[16 * ((unsigned int)v4 >> 4)]);\n v31 = v4 & 4294967280;\n v32 = _mm_add_epi32((__m128i)_mm_movehl_ps(v11, v7), (__m128i)v7);\n v33 = _mm_add_epi32(_mm_srli_si128((__m128i)v7, 8), (__m128i)v7);\n v34 = v4 & 4294967280;\n v35 = _mm_cvtsi128_si32(_mm_add_epi32(v33, _mm_srli_si128(v33, 4)));\n v36 = _mm_add_epi32(_mm_srli_si128(v5, 8), v5);\n v37 = _mm_add_epi32(v5, _mm_srli_si128(v5, 8));\n v38 = _mm_cvtsi128_si32(_mm_add_epi32(v36, _mm_srli_si128(v36, 4)));\n if ((v4 & 15) == 0) goto LABEL_31;\n }\n v39 = v4 - v31;\n if ((unsigned int)(v4 - v31 - 1) <= 6) goto LABEL_25;\n v40 = _mm_loadl_epi64((const __m128i *)&a1[v31]);\n v41 = _mm_loadl_epi64((const __m128i *)&xmmword_2670);\n v42 = _mm_add_epi8(_mm_loadl_epi64((const __m128i *)&xmmword_2650), v40);\n v43 = _mm_cmpeq_epi8(_mm_min_epu8(v42, v41), v42);\n v44 = _mm_and_si128(\n _mm_cmpeq_epi8(_mm_cmpeq_epi8(_mm_subs_epu8(v42, v41), (__m128i)0LL),\n (__m128i)0LL),\n _mm_cmpeq_epi8(v40, _mm_loadl_epi64((const __m128i *)&xmmword_2680)));\n v45 = _mm_unpacklo_epi8(v44, _mm_cmpgt_epi8((__m128i)0LL, v44));\n v46 = _mm_shuffle_epi32(v45, 78);\n v47 = _mm_unpacklo_epi16(v45, _mm_cmpgt_epi16((__m128i)0LL, v45));\n v48 = _mm_sub_epi32(_mm_sub_epi32(v37, v47), _mm_shuffle_epi32(v47, 78));\n v49 = _mm_unpacklo_epi16(v46, _mm_cmpgt_epi16((__m128i)0LL, v46));\n v50 = _mm_unpacklo_epi8(v43, _mm_cmpgt_epi8((__m128i)0LL, v43));\n v51 = _mm_shuffle_epi32(v50, 78);\n v52 = _mm_unpacklo_epi16(v50, _mm_cmpgt_epi16((__m128i)0LL, v50));\n v53 = _mm_sub_epi32(_mm_sub_epi32(v48, v49), _mm_shuffle_epi32(v49, 78));\n v54 = _mm_unpacklo_epi16(v51, _mm_cmpgt_epi16((__m128i)0LL, v51));\n v55 = _mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(v32, v52),\n _mm_shuffle_epi32(v52, 78)),\n v54),\n _mm_shuffle_epi32(v54, 78));\n v35 = _mm_cvtsi128_si32(v55) + _mm_cvtsi128_si32(_mm_shuffle_epi32(v55, 229));\n v38 = _mm_cvtsi128_si32(_mm_shuffle_epi32(v53, 229)) + _mm_cvtsi128_si32(v53);\n v34 += v39 & 4294967288;\n if ((v39 & 7) != 0) {\n LABEL_25:\n v56 = a1[v34];\n if ((unsigned char)(v56 - 48) <= 9u)\n ++v35;\n else\n v38 += v56 == 46;\n if (v4 > v34 + 1) {\n v57 = a1[v34 + 1];\n if ((unsigned char)(v57 - 48) <= 9u)\n ++v35;\n else\n v38 += v57 == 46;\n if (v4 > v34 + 2) {\n v58 = a1[v34 + 2];\n if ((unsigned char)(v58 - 48) <= 9u)\n ++v35;\n else\n v38 += v58 == 46;\n if (v4 > v34 + 3) {\n v59 = a1[v34 + 3];\n if ((unsigned char)(v59 - 48) <= 9u)\n ++v35;\n else\n v38 += v59 == 46;\n if (v34 + 4 < v4) {\n v60 = a1[v34 + 4];\n if ((unsigned char)(v60 - 48) <= 9u)\n ++v35;\n else\n v38 += v60 == 46;\n if (v4 > v34 + 5) {\n v61 = a1[v34 + 5];\n if ((unsigned char)(v61 - 48) <= 9u)\n ++v35;\n else\n v38 += v61 == 46;\n v62 = v34 + 6;\n if (v4 > v62) {\n v63 = a1[v62];\n if ((unsigned char)(v63 - 48) > 9u)\n v38 += v63 == 46;\n else\n ++v35;\n }\n }\n }\n }\n }\n }\n }\nLABEL_31:\n if (v35 <= 3) {\n v1 = \"Yes\";\n if (v38 == 1) return v1;\n }\n return (const char *)&unk_2004;\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n const char *v1;\n int v3;\n int v4;\n __m128i v5;\n const __m128i *v6;\n __m128 v7;\n __m128i si128;\n __m128i v9;\n __m128i v10;\n __m128 v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n __m128i v15;\n __m128i v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n __m128i v20;\n __m128i v21;\n __m128i v22;\n __m128i v23;\n __m128i v24;\n __m128i v25;\n __m128i v26;\n __m128i v27;\n __m128i v28;\n __m128i v29;\n __m128i v30;\n long long v31;\n __m128i v32;\n __m128i v33;\n signed int v34;\n int v35;\n __m128i v36;\n __m128i v37;\n int v38;\n int v39;\n __m128i v40;\n __m128i v41;\n __m128i v42;\n __m128i v43;\n __m128i v44;\n __m128i v45;\n __m128i v46;\n __m128i v47;\n __m128i v48;\n __m128i v49;\n __m128i v50;\n __m128i v51;\n __m128i v52;\n __m128i v53;\n __m128i v54;\n __m128i v55;\n char v56;\n char v57;\n char v58;\n char v59;\n char v60;\n char v61;\n int v62;\n char v63;\n v1 = (const char *)&unk_2004;\n v3 = strlen(a1);\n if (v3 <= 4) return v1;\n v4 = v3;\n if ((unsigned char)(*a1 - 91) <= 5u || (unsigned char)(*a1 - 65) > 57u)\n return (const char *)&unk_2004;\n if (strcmp(&a1[v3 - 4], \".txt\") && strcmp(&a1[v4 - 4], \".exe\") &&\n strcmp(&a1[v4 - 4], \".dll\"))\n return v1;\n if ((unsigned int)(v4 - 1) <= 14) {\n v37 = 0LL;\n v31 = 0LL;\n v34 = 0;\n v38 = 0;\n v32 = 0LL;\n v35 = 0;\n } else {\n v5 = 0LL;\n v6 = (const __m128i *)a1;\n v7 = 0LL;\n si128 = _mm_load_si128((const __m128i *)&xmmword_2650);\n v9 = _mm_load_si128((const __m128i *)&xmmword_2670);\n v10 = _mm_load_si128((const __m128i *)&xmmword_2660);\n v11 = (__m128)_mm_load_si128((const __m128i *)&xmmword_2680);\n do {\n v12 = _mm_loadu_si128(v6);\n v13 = v12;\n ++v6;\n v14 = _mm_add_epi8(v12, si128);\n v15 = _mm_cmpeq_epi8(\n _mm_cmpeq_epi8(_mm_subs_epu8(v10, v14), (__m128i)0LL), (__m128i)0LL);\n v16 = _mm_and_si128(\n _mm_cmpeq_epi8(_mm_cmpeq_epi8(_mm_subs_epu8(v14, v9), (__m128i)0LL),\n (__m128i)0LL),\n _mm_cmpeq_epi8(v13, (__m128i)v11));\n v17 = _mm_cmpgt_epi8((__m128i)0LL, v16);\n v18 = _mm_unpacklo_epi8(v16, v17);\n v19 = _mm_unpackhi_epi8(v16, v17);\n v20 = _mm_cmpgt_epi16((__m128i)0LL, v18);\n v21 = _mm_sub_epi32(_mm_sub_epi32(v5, _mm_unpacklo_epi16(v18, v20)),\n _mm_unpackhi_epi16(v18, v20));\n v22 = _mm_cmpgt_epi16((__m128i)0LL, v19);\n v23 = _mm_unpacklo_epi16(v19, v22);\n v24 = _mm_unpackhi_epi16(v19, v22);\n v25 = _mm_cmpgt_epi8((__m128i)0LL, v15);\n v5 = _mm_sub_epi32(_mm_sub_epi32(v21, v23), v24);\n v26 = _mm_unpacklo_epi8(v15, v25);\n v27 = _mm_unpackhi_epi8(v15, v25);\n v28 = _mm_cmpgt_epi16((__m128i)0LL, v26);\n v29 = _mm_sub_epi32(\n _mm_sub_epi32((__m128i)v7, _mm_unpacklo_epi16(v26, v28)),\n _mm_unpackhi_epi16(v26, v28));\n v30 = _mm_cmpgt_epi16((__m128i)0LL, v27);\n v7 = (__m128)_mm_sub_epi32(\n _mm_sub_epi32(v29, _mm_unpacklo_epi16(v27, v30)),\n _mm_unpackhi_epi16(v27, v30));\n } while (v6 != (const __m128i *)&a1[16 * ((unsigned int)v4 >> 4)]);\n v31 = v4 & 4294967280;\n v32 = _mm_add_epi32((__m128i)_mm_movehl_ps(v11, v7), (__m128i)v7);\n v33 = _mm_add_epi32(_mm_srli_si128((__m128i)v7, 8), (__m128i)v7);\n v34 = v4 & 4294967280;\n v35 = _mm_cvtsi128_si32(_mm_add_epi32(v33, _mm_srli_si128(v33, 4)));\n v36 = _mm_add_epi32(_mm_srli_si128(v5, 8), v5);\n v37 = _mm_add_epi32(v5, _mm_srli_si128(v5, 8));\n v38 = _mm_cvtsi128_si32(_mm_add_epi32(v36, _mm_srli_si128(v36, 4)));\n if ((v4 & 15) == 0) goto LABEL_31;\n }\n v39 = v4 - v31;\n if ((unsigned int)(v4 - v31 - 1) <= 6) goto LABEL_25;\n v40 = _mm_loadl_epi64((const __m128i *)&a1[v31]);\n v41 = _mm_loadl_epi64((const __m128i *)&xmmword_2670);\n v42 = _mm_add_epi8(_mm_loadl_epi64((const __m128i *)&xmmword_2650), v40);\n v43 = _mm_cmpeq_epi8(_mm_min_epu8(v42, v41), v42);\n v44 = _mm_and_si128(\n _mm_cmpeq_epi8(_mm_cmpeq_epi8(_mm_subs_epu8(v42, v41), (__m128i)0LL),\n (__m128i)0LL),\n _mm_cmpeq_epi8(v40, _mm_loadl_epi64((const __m128i *)&xmmword_2680)));\n v45 = _mm_unpacklo_epi8(v44, _mm_cmpgt_epi8((__m128i)0LL, v44));\n v46 = _mm_shuffle_epi32(v45, 78);\n v47 = _mm_unpacklo_epi16(v45, _mm_cmpgt_epi16((__m128i)0LL, v45));\n v48 = _mm_sub_epi32(_mm_sub_epi32(v37, v47), _mm_shuffle_epi32(v47, 78));\n v49 = _mm_unpacklo_epi16(v46, _mm_cmpgt_epi16((__m128i)0LL, v46));\n v50 = _mm_unpacklo_epi8(v43, _mm_cmpgt_epi8((__m128i)0LL, v43));\n v51 = _mm_shuffle_epi32(v50, 78);\n v52 = _mm_unpacklo_epi16(v50, _mm_cmpgt_epi16((__m128i)0LL, v50));\n v53 = _mm_sub_epi32(_mm_sub_epi32(v48, v49), _mm_shuffle_epi32(v49, 78));\n v54 = _mm_unpacklo_epi16(v51, _mm_cmpgt_epi16((__m128i)0LL, v51));\n v55 = _mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(v32, v52),\n _mm_shuffle_epi32(v52, 78)),\n v54),\n _mm_shuffle_epi32(v54, 78));\n v35 = _mm_cvtsi128_si32(v55) + _mm_cvtsi128_si32(_mm_shuffle_epi32(v55, 229));\n v38 = _mm_cvtsi128_si32(_mm_shuffle_epi32(v53, 229)) + _mm_cvtsi128_si32(v53);\n v34 += v39 & 4294967288;\n if ((v39 & 7) != 0) {\n LABEL_25:\n v56 = a1[v34];\n if ((unsigned char)(v56 - 48) <= 9u)\n ++v35;\n else\n v38 += v56 == 46;\n if (v4 > v34 + 1) {\n v57 = a1[v34 + 1];\n if ((unsigned char)(v57 - 48) <= 9u)\n ++v35;\n else\n v38 += v57 == 46;\n if (v4 > v34 + 2) {\n v58 = a1[v34 + 2];\n if ((unsigned char)(v58 - 48) <= 9u)\n ++v35;\n else\n v38 += v58 == 46;\n if (v4 > v34 + 3) {\n v59 = a1[v34 + 3];\n if ((unsigned char)(v59 - 48) <= 9u)\n ++v35;\n else\n v38 += v59 == 46;\n if (v34 + 4 < v4) {\n v60 = a1[v34 + 4];\n if ((unsigned char)(v60 - 48) <= 9u)\n ++v35;\n else\n v38 += v60 == 46;\n if (v4 > v34 + 5) {\n v61 = a1[v34 + 5];\n if ((unsigned char)(v61 - 48) <= 9u)\n ++v35;\n else\n v38 += v61 == 46;\n v62 = v34 + 6;\n if (v4 > v62) {\n v63 = a1[v62];\n if ((unsigned char)(v63 - 48) > 9u)\n v38 += v63 == 46;\n else\n ++v35;\n }\n }\n }\n }\n }\n }\n }\nLABEL_31:\n if (v35 <= 3) {\n v1 = \"Yes\";\n if (v38 == 1) return v1;\n }\n return (const char *)&unk_2004;\n}" + }, + { + "index": "HumanEval-C-142", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int* lst, int size) {\n int sum = 0;\n for (int i = 0; i < size; i++) {\n if (i % 3 == 0)\n sum += lst[i] * lst[i];\n else if (i % 4 == 0)\n sum += lst[i] * lst[i] * lst[i];\n else\n sum += lst[i];\n }\n return sum;\n}", + "test": "#include \n\nint main() {\n {\n int lst[] = {1, 2, 3};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == 6);\n }\n {\n int lst[] = {1, 4, 9};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == 14);\n }\n {\n int lst[] = {};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == 0);\n }\n {\n int lst[] = {1, 1, 1, 1, 1, 1, 1, 1, 1};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == 9);\n }\n {\n int lst[] = {-1, -1, -1, -1, -1, -1, -1, -1, -1};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == -3);\n }\n {\n int lst[] = {0};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == 0);\n }\n {\n int lst[] = {-1, -5, 2, -1, -5};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == -126);\n }\n {\n int lst[] = {-56, -99, 1, 0, -2};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == 3030);\n }\n {\n int lst[] = {-1, 0, 0, 0, 0, 0, 0, 0, -1};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == 0);\n }\n {\n int lst[] = {-16, -9, -2, 36, 36, 26, -20, 25, -40, 20, -4, 12, -26, 35, 37};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == -14196);\n }\n {\n int lst[] = {-1, -3, 17, -1, -15, 13, -1, 14, -14, -12, -5, 14, -14, 6, 13, 11, 16, 16, 4, 10};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == -1448);\n }\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp loc_125C\nloc_118B:\nmov ecx, [rbp+var_4]\nmovsxd rax, ecx\nimul rax, 55555556h\nshr rax, 20h\nmov rdx, rax\nmov eax, ecx\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\nadd eax, eax\nadd eax, edx\nsub ecx, eax\nmov edx, ecx\ntest edx, edx\njnz short loc_11E8\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nimul eax, edx\nadd [rbp+var_8], eax\njmp short loc_1258\nloc_11E8:\nmov eax, [rbp+var_4]\nand eax, 3\ntest eax, eax\njnz short loc_123F\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nimul edx, eax\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nimul eax, edx\nadd [rbp+var_8], eax\njmp short loc_1258\nloc_123F:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nloc_1258:\nadd [rbp+var_4], 1\nloc_125C:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl loc_118B\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int v2; // eax\n unsigned int v4; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( i % 3 )\n {\n if ( (i & 3) != 0 )\n v2 = *(_DWORD *)(4LL * i + a1);\n else\n v2 = *(_DWORD *)(4LL * i + a1) * *(_DWORD *)(4LL * i + a1) * *(_DWORD *)(4LL * i + a1);\n v4 += v2;\n }\n else\n {\n v4 += *(_DWORD *)(4LL * i + a1) * *(_DWORD *)(4LL * i + a1);\n }\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp loc_125C\nloc_118B:\nmov ecx, [rbp+var_4]\nmovsxd rax, ecx\nimul rax, 55555556h\nshr rax, 20h\nmov rdx, rax\nmov eax, ecx\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\nadd eax, eax\nadd eax, edx\nsub ecx, eax\nmov edx, ecx\ntest edx, edx\njnz short loc_11E8\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nimul eax, edx\nadd [rbp+var_8], eax\njmp short loc_1258\nloc_11E8:\nmov eax, [rbp+var_4]\nand eax, 3\ntest eax, eax\njnz short loc_123F\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nimul edx, eax\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nimul eax, edx\nadd [rbp+var_8], eax\njmp short loc_1258\nloc_123F:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nloc_1258:\nadd [rbp+var_4], 1\nloc_125C:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl loc_118B\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int v2; // eax\n unsigned int v4; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( i % 3 )\n {\n if ( (i & 3) != 0 )\n v2 = *(_DWORD *)(4LL * i + a1);\n else\n v2 = *(_DWORD *)(4LL * i + a1) * *(_DWORD *)(4LL * i + a1) * *(_DWORD *)(4LL * i + a1);\n v4 += v2;\n }\n else\n {\n v4 += *(_DWORD *)(4LL * i + a1) * *(_DWORD *)(4LL * i + a1);\n }\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int v2;\n unsigned int v4;\n int i;\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n if (i % 3) {\n if ((i & 3) != 0)\n v2 = *(uint32_t *)(4LL * i + a1);\n else\n v2 = *(uint32_t *)(4LL * i + a1) * *(uint32_t *)(4LL * i + a1) *\n *(uint32_t *)(4LL * i + a1);\n v4 += v2;\n } else {\n v4 += *(uint32_t *)(4LL * i + a1) * *(uint32_t *)(4LL * i + a1);\n }\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int v2;\n unsigned int v4;\n int i;\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n if (i % 3) {\n if ((i & 3) != 0)\n v2 = *(uint32_t *)(4LL * i + a1);\n else\n v2 = *(uint32_t *)(4LL * i + a1) * *(uint32_t *)(4LL * i + a1) *\n *(uint32_t *)(4LL * i + a1);\n v4 += v2;\n } else {\n v4 += *(uint32_t *)(4LL * i + a1) * *(uint32_t *)(4LL * i + a1);\n }\n }\n return v4;\n}" + }, + { + "index": "HumanEval-C-142", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int* lst, int size) {\n int sum = 0;\n for (int i = 0; i < size; i++) {\n if (i % 3 == 0)\n sum += lst[i] * lst[i];\n else if (i % 4 == 0)\n sum += lst[i] * lst[i] * lst[i];\n else\n sum += lst[i];\n }\n return sum;\n}", + "test": "#include \n\nint main() {\n {\n int lst[] = {1, 2, 3};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == 6);\n }\n {\n int lst[] = {1, 4, 9};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == 14);\n }\n {\n int lst[] = {};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == 0);\n }\n {\n int lst[] = {1, 1, 1, 1, 1, 1, 1, 1, 1};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == 9);\n }\n {\n int lst[] = {-1, -1, -1, -1, -1, -1, -1, -1, -1};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == -3);\n }\n {\n int lst[] = {0};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == 0);\n }\n {\n int lst[] = {-1, -5, 2, -1, -5};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == -126);\n }\n {\n int lst[] = {-56, -99, 1, 0, -2};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == 3030);\n }\n {\n int lst[] = {-1, 0, 0, 0, 0, 0, 0, 0, -1};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == 0);\n }\n {\n int lst[] = {-16, -9, -2, 36, 36, 26, -20, 25, -40, 20, -4, 12, -26, 35, 37};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == -14196);\n }\n {\n int lst[] = {-1, -3, 17, -1, -15, 13, -1, 14, -14, -12, -5, 14, -14, 6, 13, 11, 16, 16, 4, 10};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == -1448);\n }\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmov r8, rdi\ntest esi, esi\njle short loc_11CC\nmovsxd rsi, esi\nmov edx, 0\nmov ecx, 0\njmp short loc_119F\nloc_1183:\ntest dl, 3\njnz short loc_11C6\nmov edi, [r8+rdx*4]\nmov eax, edi\nimul eax, edi\nimul eax, edi\nadd ecx, eax\nloc_1196:\nadd rdx, 1\ncmp rdx, rsi\njz short loc_11D1\nloc_119F:\nmovsxd rax, edx\nimul rax, 55555556h\nshr rax, 20h\nmov edi, edx\nsar edi, 1Fh\nsub eax, edi\nlea eax, [rax+rax*2]\ncmp eax, edx\njnz short loc_1183\nmov eax, [r8+rdx*4]\nimul eax, eax\nadd ecx, eax\njmp short loc_1196\nloc_11C6:\nadd ecx, [r8+rdx*4]\njmp short loc_1196\nloc_11CC:\nmov ecx, 0\nloc_11D1:\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // rdx\n unsigned int v3; // ecx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = 0LL;\n v3 = 0;\n do\n {\n if ( 3 * ((int)v2 / 3) == (_DWORD)v2 )\n {\n v3 += *(_DWORD *)(a1 + 4 * v2) * *(_DWORD *)(a1 + 4 * v2);\n }\n else if ( (v2 & 3) != 0 )\n {\n v3 += *(_DWORD *)(a1 + 4 * v2);\n }\n else\n {\n v3 += *(_DWORD *)(a1 + 4 * v2) * *(_DWORD *)(a1 + 4 * v2) * *(_DWORD *)(a1 + 4 * v2);\n }\n ++v2;\n }\n while ( v2 != a2 );\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov r8, rdi\ntest esi, esi\njle short loc_11CC\nmovsxd rsi, esi\nmov edx, 0\nmov ecx, 0\njmp short loc_119F\nloc_1183:\ntest dl, 3\njnz short loc_11C6\nmov edi, [r8+rdx*4]\nmov eax, edi\nimul eax, edi\nimul eax, edi\nadd ecx, eax\nloc_1196:\nadd rdx, 1\ncmp rdx, rsi\njz short loc_11D1\nloc_119F:\nmovsxd rax, edx\nimul rax, 55555556h\nshr rax, 20h\nmov edi, edx\nsar edi, 1Fh\nsub eax, edi\nlea eax, [rax+rax*2]\ncmp eax, edx\njnz short loc_1183\nmov eax, [r8+rdx*4]\nimul eax, eax\nadd ecx, eax\njmp short loc_1196\nloc_11C6:\nadd ecx, [r8+rdx*4]\njmp short loc_1196\nloc_11CC:\nmov ecx, 0\nloc_11D1:\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n __int64 v2; // rdx\n unsigned int v3; // ecx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = 0LL;\n v3 = 0;\n do\n {\n if ( 3 * ((int)v2 / 3) == (_DWORD)v2 )\n {\n v3 += *(_DWORD *)(a1 + 4 * v2) * *(_DWORD *)(a1 + 4 * v2);\n }\n else if ( (v2 & 3) != 0 )\n {\n v3 += *(_DWORD *)(a1 + 4 * v2);\n }\n else\n {\n v3 += *(_DWORD *)(a1 + 4 * v2) * *(_DWORD *)(a1 + 4 * v2) * *(_DWORD *)(a1 + 4 * v2);\n }\n ++v2;\n }\n while ( v2 != a2 );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = 0LL;\n v3 = 0;\n do {\n if (3 * ((int)v2 / 3) == (uint32_t)v2) {\n v3 += *(uint32_t *)(a1 + 4 * v2) * *(uint32_t *)(a1 + 4 * v2);\n } else if ((v2 & 3) != 0) {\n v3 += *(uint32_t *)(a1 + 4 * v2);\n } else {\n v3 += *(uint32_t *)(a1 + 4 * v2) * *(uint32_t *)(a1 + 4 * v2) *\n *(uint32_t *)(a1 + 4 * v2);\n }\n ++v2;\n } while (v2 != a2);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = 0LL;\n v3 = 0;\n do {\n if (3 * ((int)v2 / 3) == (uint32_t)v2) {\n v3 += *(uint32_t *)(a1 + 4 * v2) * *(uint32_t *)(a1 + 4 * v2);\n } else if ((v2 & 3) != 0) {\n v3 += *(uint32_t *)(a1 + 4 * v2);\n } else {\n v3 += *(uint32_t *)(a1 + 4 * v2) * *(uint32_t *)(a1 + 4 * v2) *\n *(uint32_t *)(a1 + 4 * v2);\n }\n ++v2;\n } while (v2 != a2);\n }\n return v3;\n}" + }, + { + "index": "HumanEval-C-142", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int* lst, int size) {\n int sum = 0;\n for (int i = 0; i < size; i++) {\n if (i % 3 == 0)\n sum += lst[i] * lst[i];\n else if (i % 4 == 0)\n sum += lst[i] * lst[i] * lst[i];\n else\n sum += lst[i];\n }\n return sum;\n}", + "test": "#include \n\nint main() {\n {\n int lst[] = {1, 2, 3};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == 6);\n }\n {\n int lst[] = {1, 4, 9};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == 14);\n }\n {\n int lst[] = {};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == 0);\n }\n {\n int lst[] = {1, 1, 1, 1, 1, 1, 1, 1, 1};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == 9);\n }\n {\n int lst[] = {-1, -1, -1, -1, -1, -1, -1, -1, -1};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == -3);\n }\n {\n int lst[] = {0};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == 0);\n }\n {\n int lst[] = {-1, -5, 2, -1, -5};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == -126);\n }\n {\n int lst[] = {-56, -99, 1, 0, -2};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == 3030);\n }\n {\n int lst[] = {-1, 0, 0, 0, 0, 0, 0, 0, -1};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == 0);\n }\n {\n int lst[] = {-16, -9, -2, 36, 36, 26, -20, 25, -40, 20, -4, 12, -26, 35, 37};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == -14196);\n }\n {\n int lst[] = {-1, -3, 17, -1, -15, 13, -1, 14, -14, -12, -5, 14, -14, 6, 13, 11, 16, 16, 4, 10};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == -1448);\n }\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1540\nmovsxd rsi, esi\nxor eax, eax\nxor ecx, ecx\njmp short loc_1506\nloc_14F8:\nimul edx, edx\nadd ecx, edx\nloc_14FD:\nadd rax, 1\ncmp rax, rsi\njz short loc_1531\nloc_1506:\nimul edx, eax, 0AAAAAAABh\ncmp edx, 55555555h\nmov edx, [rdi+rax*4]\njbe short loc_14F8\ntest al, 3\njnz short loc_1538\nmov r8d, edx\nadd rax, 1\nimul r8d, edx\nimul edx, r8d\nadd ecx, edx\ncmp rax, rsi\njnz short loc_1506\nloc_1531:\nmov eax, ecx\nretn\nloc_1538:\nadd ecx, edx\njmp short loc_14FD\nloc_1540:\nxor ecx, ecx\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // rax\n unsigned int v3; // ecx\n int v4; // edx\n\n if ( a2 > 0 )\n {\n v2 = 0LL;\n v3 = 0;\n while ( 1 )\n {\n while ( 1 )\n {\n v4 = *(_DWORD *)(a1 + 4 * v2);\n if ( (unsigned int)(-1431655765 * v2) > 0x55555555 )\n break;\n v3 += v4 * v4;\nLABEL_4:\n if ( ++v2 == a2 )\n return v3;\n }\n if ( (v2 & 3) != 0 )\n {\n v3 += v4;\n goto LABEL_4;\n }\n ++v2;\n v3 += v4 * v4 * v4;\n if ( v2 == a2 )\n return v3;\n }\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_14E0:\nendbr64\ntest esi, esi\njle short loc_1540\nmovsxd rsi, esi\nxor eax, eax\nxor ecx, ecx\njmp short loc_1506\nloc_14F8:\nimul edx, edx\nadd ecx, edx\nloc_14FD:\nadd rax, 1\ncmp rax, rsi\njz short loc_1531\nloc_1506:\nimul edx, eax, 0AAAAAAABh\ncmp edx, 55555555h\nmov edx, [rdi+rax*4]\njbe short loc_14F8\ntest al, 3\njnz short loc_1538\nmov r8d, edx\nadd rax, 1\nimul r8d, edx\nimul edx, r8d\nadd ecx, edx\ncmp rax, rsi\njnz short loc_1506\nloc_1531:\nmov eax, ecx\nretn\nloc_1538:\nadd ecx, edx\njmp short loc_14FD\nloc_1540:\nxor ecx, ecx\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_14E0(__int64 a1, int a2)\n{\n __int64 v2; // rax\n unsigned int v3; // ecx\n int v4; // edx\n\n if ( a2 > 0 )\n {\n v2 = 0LL;\n v3 = 0;\n while ( 1 )\n {\n while ( 1 )\n {\n v4 = *(_DWORD *)(a1 + 4 * v2);\n if ( (unsigned int)(-1431655765 * v2) > 0x55555555 )\n break;\n v3 += v4 * v4;\nLABEL_4:\n if ( ++v2 == a2 )\n return v3;\n }\n if ( (v2 & 3) != 0 )\n {\n v3 += v4;\n goto LABEL_4;\n }\n ++v2;\n v3 += v4 * v4 * v4;\n if ( v2 == a2 )\n return v3;\n }\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_14E0(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n int v4;\n if (a2 > 0) {\n v2 = 0LL;\n v3 = 0;\n while (1) {\n while (1) {\n v4 = *(uint32_t *)(a1 + 4 * v2);\n if ((unsigned int)(-1431655765 * v2) > 1431655765) break;\n v3 += v4 * v4;\n LABEL_4:\n if (++v2 == a2) return v3;\n }\n if ((v2 & 3) != 0) {\n v3 += v4;\n goto LABEL_4;\n }\n ++v2;\n v3 += v4 * v4 * v4;\n if (v2 == a2) return v3;\n }\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n int v4;\n if (a2 > 0) {\n v2 = 0LL;\n v3 = 0;\n while (1) {\n while (1) {\n v4 = *(uint32_t *)(a1 + 4 * v2);\n if ((unsigned int)(-1431655765 * v2) > 1431655765) break;\n v3 += v4 * v4;\n LABEL_4:\n if (++v2 == a2) return v3;\n }\n if ((v2 & 3) != 0) {\n v3 += v4;\n goto LABEL_4;\n }\n ++v2;\n v3 += v4 * v4 * v4;\n if (v2 == a2) return v3;\n }\n }\n return 0LL;\n}" + }, + { + "index": "HumanEval-C-142", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int* lst, int size) {\n int sum = 0;\n for (int i = 0; i < size; i++) {\n if (i % 3 == 0)\n sum += lst[i] * lst[i];\n else if (i % 4 == 0)\n sum += lst[i] * lst[i] * lst[i];\n else\n sum += lst[i];\n }\n return sum;\n}", + "test": "#include \n\nint main() {\n {\n int lst[] = {1, 2, 3};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == 6);\n }\n {\n int lst[] = {1, 4, 9};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == 14);\n }\n {\n int lst[] = {};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == 0);\n }\n {\n int lst[] = {1, 1, 1, 1, 1, 1, 1, 1, 1};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == 9);\n }\n {\n int lst[] = {-1, -1, -1, -1, -1, -1, -1, -1, -1};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == -3);\n }\n {\n int lst[] = {0};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == 0);\n }\n {\n int lst[] = {-1, -5, 2, -1, -5};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == -126);\n }\n {\n int lst[] = {-56, -99, 1, 0, -2};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == 3030);\n }\n {\n int lst[] = {-1, 0, 0, 0, 0, 0, 0, 0, -1};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == 0);\n }\n {\n int lst[] = {-16, -9, -2, 36, 36, 26, -20, 25, -40, 20, -4, 12, -26, 35, 37};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == -14196);\n }\n {\n int lst[] = {-1, -3, 17, -1, -15, 13, -1, 14, -14, -12, -5, 14, -14, 6, 13, 11, 16, 16, 4, 10};\n assert(func0(lst, sizeof(lst)/sizeof(lst[0])) == -1448);\n }\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1540\nmovsxd rsi, esi\nxor eax, eax\nxor ecx, ecx\njmp short loc_1506\nloc_14F8:\nimul edx, edx\nadd ecx, edx\nloc_14FD:\nadd rax, 1\ncmp rsi, rax\njz short loc_1531\nloc_1506:\nimul edx, eax, 0AAAAAAABh\ncmp edx, 55555555h\nmov edx, [rdi+rax*4]\njbe short loc_14F8\ntest al, 3\njnz short loc_1538\nmov r8d, edx\nadd rax, 1\nimul r8d, edx\nimul edx, r8d\nadd ecx, edx\ncmp rsi, rax\njnz short loc_1506\nloc_1531:\nmov eax, ecx\nretn\nloc_1538:\nadd ecx, edx\njmp short loc_14FD\nloc_1540:\nxor ecx, ecx\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // rax\n unsigned int v3; // ecx\n int v4; // edx\n\n if ( a2 > 0 )\n {\n v2 = 0LL;\n v3 = 0;\n while ( 1 )\n {\n while ( 1 )\n {\n v4 = *(_DWORD *)(a1 + 4 * v2);\n if ( (unsigned int)(-1431655765 * v2) > 0x55555555 )\n break;\n v3 += v4 * v4;\nLABEL_4:\n if ( a2 == ++v2 )\n return v3;\n }\n if ( (v2 & 3) != 0 )\n {\n v3 += v4;\n goto LABEL_4;\n }\n ++v2;\n v3 += v4 * v4 * v4;\n if ( a2 == v2 )\n return v3;\n }\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_14E0:\nendbr64\ntest esi, esi\njle short loc_1540\nmovsxd rsi, esi\nxor eax, eax\nxor ecx, ecx\njmp short loc_1506\nloc_14F8:\nimul edx, edx\nadd ecx, edx\nloc_14FD:\nadd rax, 1\ncmp rsi, rax\njz short loc_1531\nloc_1506:\nimul edx, eax, 0AAAAAAABh\ncmp edx, 55555555h\nmov edx, [rdi+rax*4]\njbe short loc_14F8\ntest al, 3\njnz short loc_1538\nmov r8d, edx\nadd rax, 1\nimul r8d, edx\nimul edx, r8d\nadd ecx, edx\ncmp rsi, rax\njnz short loc_1506\nloc_1531:\nmov eax, ecx\nretn\nloc_1538:\nadd ecx, edx\njmp short loc_14FD\nloc_1540:\nxor ecx, ecx\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_14E0(__int64 a1, int a2)\n{\n __int64 v2; // rax\n unsigned int v3; // ecx\n int v4; // edx\n\n if ( a2 > 0 )\n {\n v2 = 0LL;\n v3 = 0;\n while ( 1 )\n {\n while ( 1 )\n {\n v4 = *(_DWORD *)(a1 + 4 * v2);\n if ( (unsigned int)(-1431655765 * v2) > 0x55555555 )\n break;\n v3 += v4 * v4;\nLABEL_4:\n if ( a2 == ++v2 )\n return v3;\n }\n if ( (v2 & 3) != 0 )\n {\n v3 += v4;\n goto LABEL_4;\n }\n ++v2;\n v3 += v4 * v4 * v4;\n if ( a2 == v2 )\n return v3;\n }\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_14E0(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n int v4;\n if (a2 > 0) {\n v2 = 0LL;\n v3 = 0;\n while (1) {\n while (1) {\n v4 = *(uint32_t *)(a1 + 4 * v2);\n if ((unsigned int)(-1431655765 * v2) > 1431655765) break;\n v3 += v4 * v4;\n LABEL_4:\n if (a2 == ++v2) return v3;\n }\n if ((v2 & 3) != 0) {\n v3 += v4;\n goto LABEL_4;\n }\n ++v2;\n v3 += v4 * v4 * v4;\n if (a2 == v2) return v3;\n }\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n int v4;\n if (a2 > 0) {\n v2 = 0LL;\n v3 = 0;\n while (1) {\n while (1) {\n v4 = *(uint32_t *)(a1 + 4 * v2);\n if ((unsigned int)(-1431655765 * v2) > 1431655765) break;\n v3 += v4 * v4;\n LABEL_4:\n if (a2 == ++v2) return v3;\n }\n if ((v2 & 3) != 0) {\n v3 += v4;\n goto LABEL_4;\n }\n ++v2;\n v3 += v4 * v4 * v4;\n if (a2 == v2) return v3;\n }\n }\n return 0LL;\n}" + }, + { + "index": "HumanEval-C-143", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "void func0(const char* sentence, char* out) {\n int index = 0, word_len = 0;\n int out_index = 0;\n bool is_prime;\n int i, j;\n for (i = 0; sentence[i] != '\\0'; ++i) {\n if (sentence[i] != ' ') {\n word_len++;\n } else {\n if (word_len > 1) {\n is_prime = true;\n for (j = 2; j * j <= word_len; ++j) {\n if (word_len % j == 0) {\n is_prime = false;\n break;\n }\n }\n } else {\n is_prime = false;\n }\n if (is_prime) {\n if (out_index > 0) {\n out[out_index++] = ' ';\n }\n memcpy(out + out_index, sentence + i - word_len, word_len);\n out_index += word_len;\n }\n word_len = 0;\n }\n }\n if (word_len > 1) {\n is_prime = true;\n for (j = 2; j * j <= word_len; ++j) {\n if (word_len % j == 0) {\n is_prime = false;\n break;\n }\n }\n } else {\n is_prime = false;\n }\n if (is_prime) {\n if (out_index > 0) {\n out[out_index++] = ' ';\n }\n memcpy(out + out_index, sentence + i - word_len, word_len);\n out_index += word_len;\n }\n out[out_index] = '\\0';\n}", + "test": "#include \n#include \n\nint main() {\n char output[101];\n\n func0(\"This is a test\", output);\n assert(strcmp(output, \"is\") == 0);\n\n func0(\"lets go for swimming\", output);\n assert(strcmp(output, \"go for\") == 0);\n\n func0(\"there is no place available here\", output);\n assert(strcmp(output, \"there is no place\") == 0);\n\n func0(\"Hi I am Hussein\", output);\n assert(strcmp(output, \"Hi am Hussein\") == 0);\n\n func0(\"go for it\", output);\n assert(strcmp(output, \"go for it\") == 0);\n\n func0(\"here\", output);\n assert(strcmp(output, \"\") == 0);\n\n func0(\"here is\", output);\n assert(strcmp(output, \"is\") == 0);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_30], rsi\nmov [rbp+var_4], 0\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp loc_129D\nloc_11DE:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njz short loc_11FB\nadd [rbp+var_14], 1\njmp loc_1299\nloc_11FB:\ncmp [rbp+var_14], 1\njle short loc_1232\nmov [rbp+var_15], 1\nmov [rbp+var_8], 2\njmp short loc_1225\nloc_120E:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_8]\nmov eax, edx\ntest eax, eax\njnz short loc_1221\nmov [rbp+var_15], 0\njmp short loc_1236\nloc_1221:\nadd [rbp+var_8], 1\nloc_1225:\nmov eax, [rbp+var_8]\nimul eax, eax\ncmp [rbp+var_14], eax\njge short loc_120E\njmp short loc_1236\nloc_1232:\nmov [rbp+var_15], 0\nloc_1236:\ncmp [rbp+var_15], 0\njz short loc_1292\ncmp [rbp+var_10], 0\njle short loc_1258\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov byte ptr [rax], 20h ; ' '\nloc_1258:\nmov eax, [rbp+var_14]\ncdqe\nmov edx, [rbp+var_C]\nmovsxd rcx, edx\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nsub rcx, rdx\nmov rdx, [rbp+var_28]\nlea rsi, [rcx+rdx]; src\nmov edx, [rbp+var_10]\nmovsxd rcx, edx\nmov rdx, [rbp+var_30]\nadd rcx, rdx\nmov rdx, rax; n\nmov rdi, rcx; dest\ncall _memcpy\nmov eax, [rbp+var_14]\nadd [rbp+var_10], eax\nloc_1292:\nmov [rbp+var_14], 0\nloc_1299:\nadd [rbp+var_C], 1\nloc_129D:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_11DE\ncmp [rbp+var_14], 1\njle short loc_12EC\nmov [rbp+var_15], 1\nmov [rbp+var_8], 2\njmp short loc_12DF\nloc_12C8:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_8]\nmov eax, edx\ntest eax, eax\njnz short loc_12DB\nmov [rbp+var_15], 0\njmp short loc_12F0\nloc_12DB:\nadd [rbp+var_8], 1\nloc_12DF:\nmov eax, [rbp+var_8]\nimul eax, eax\ncmp [rbp+var_14], eax\njge short loc_12C8\njmp short loc_12F0\nloc_12EC:\nmov [rbp+var_15], 0\nloc_12F0:\ncmp [rbp+var_15], 0\njz short loc_134C\ncmp [rbp+var_10], 0\njle short loc_1312\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov byte ptr [rax], 20h ; ' '\nloc_1312:\nmov eax, [rbp+var_14]\ncdqe\nmov edx, [rbp+var_C]\nmovsxd rcx, edx\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nsub rcx, rdx\nmov rdx, [rbp+var_28]\nlea rsi, [rcx+rdx]; src\nmov edx, [rbp+var_10]\nmovsxd rcx, edx\nmov rdx, [rbp+var_30]\nadd rcx, rdx\nmov rdx, rax; n\nmov rdi, rcx; dest\ncall _memcpy\nmov eax, [rbp+var_14]\nadd [rbp+var_10], eax\nloc_134C:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov byte ptr [rax], 0\nnop\nleave\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(__int64 a1, __int64 a2)\n{\n int v2; // eax\n int v3; // eax\n _BYTE *result; // rax\n char v5; // [rsp+1Bh] [rbp-15h]\n char v6; // [rsp+1Bh] [rbp-15h]\n int v7; // [rsp+1Ch] [rbp-14h]\n int v8; // [rsp+20h] [rbp-10h]\n int i; // [rsp+24h] [rbp-Ch]\n int j; // [rsp+28h] [rbp-8h]\n int k; // [rsp+28h] [rbp-8h]\n\n v7 = 0;\n v8 = 0;\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n {\n if ( *(_BYTE *)(i + a1) == 32 )\n {\n if ( v7 <= 1 )\n {\n v5 = 0;\n }\n else\n {\n v5 = 1;\n for ( j = 2; v7 >= j * j; ++j )\n {\n if ( !(v7 % j) )\n {\n v5 = 0;\n break;\n }\n }\n }\n if ( v5 )\n {\n if ( v8 > 0 )\n {\n v2 = v8++;\n *(_BYTE *)(v2 + a2) = 32;\n }\n memcpy((void *)(a2 + v8), (const void *)(i - (__int64)v7 + a1), v7);\n v8 += v7;\n }\n v7 = 0;\n }\n else\n {\n ++v7;\n }\n }\n if ( v7 <= 1 )\n {\n v6 = 0;\n }\n else\n {\n v6 = 1;\n for ( k = 2; v7 >= k * k; ++k )\n {\n if ( !(v7 % k) )\n {\n v6 = 0;\n break;\n }\n }\n }\n if ( v6 )\n {\n if ( v8 > 0 )\n {\n v3 = v8++;\n *(_BYTE *)(v3 + a2) = 32;\n }\n memcpy((void *)(a2 + v8), (const void *)(i - (__int64)v7 + a1), v7);\n v8 += v7;\n }\n result = (_BYTE *)(v8 + a2);\n *result = 0;\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_30], rsi\nmov [rbp+var_4], 0\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp loc_129D\nloc_11DE:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njz short loc_11FB\nadd [rbp+var_14], 1\njmp loc_1299\nloc_11FB:\ncmp [rbp+var_14], 1\njle short loc_1232\nmov [rbp+var_15], 1\nmov [rbp+var_8], 2\njmp short loc_1225\nloc_120E:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_8]\nmov eax, edx\ntest eax, eax\njnz short loc_1221\nmov [rbp+var_15], 0\njmp short loc_1236\nloc_1221:\nadd [rbp+var_8], 1\nloc_1225:\nmov eax, [rbp+var_8]\nimul eax, eax\ncmp [rbp+var_14], eax\njge short loc_120E\njmp short loc_1236\nloc_1232:\nmov [rbp+var_15], 0\nloc_1236:\ncmp [rbp+var_15], 0\njz short loc_1292\ncmp [rbp+var_10], 0\njle short loc_1258\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov byte ptr [rax], 20h ; ' '\nloc_1258:\nmov eax, [rbp+var_14]\ncdqe\nmov edx, [rbp+var_C]\nmovsxd rcx, edx\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nsub rcx, rdx\nmov rdx, [rbp+var_28]\nlea rsi, [rcx+rdx]; src\nmov edx, [rbp+var_10]\nmovsxd rcx, edx\nmov rdx, [rbp+var_30]\nadd rcx, rdx\nmov rdx, rax; n\nmov rdi, rcx; dest\ncall _memcpy\nmov eax, [rbp+var_14]\nadd [rbp+var_10], eax\nloc_1292:\nmov [rbp+var_14], 0\nloc_1299:\nadd [rbp+var_C], 1\nloc_129D:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_11DE\ncmp [rbp+var_14], 1\njle short loc_12EC\nmov [rbp+var_15], 1\nmov [rbp+var_8], 2\njmp short loc_12DF\nloc_12C8:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_8]\nmov eax, edx\ntest eax, eax\njnz short loc_12DB\nmov [rbp+var_15], 0\njmp short loc_12F0\nloc_12DB:\nadd [rbp+var_8], 1\nloc_12DF:\nmov eax, [rbp+var_8]\nimul eax, eax\ncmp [rbp+var_14], eax\njge short loc_12C8\njmp short loc_12F0\nloc_12EC:\nmov [rbp+var_15], 0\nloc_12F0:\ncmp [rbp+var_15], 0\njz short loc_134C\ncmp [rbp+var_10], 0\njle short loc_1312\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov byte ptr [rax], 20h ; ' '\nloc_1312:\nmov eax, [rbp+var_14]\ncdqe\nmov edx, [rbp+var_C]\nmovsxd rcx, edx\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nsub rcx, rdx\nmov rdx, [rbp+var_28]\nlea rsi, [rcx+rdx]; src\nmov edx, [rbp+var_10]\nmovsxd rcx, edx\nmov rdx, [rbp+var_30]\nadd rcx, rdx\nmov rdx, rax; n\nmov rdi, rcx; dest\ncall _memcpy\nmov eax, [rbp+var_14]\nadd [rbp+var_10], eax\nloc_134C:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov byte ptr [rax], 0\nnop\nleave\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_11A9(__int64 a1, __int64 a2)\n{\n int v2; // eax\n int v3; // eax\n _BYTE *result; // rax\n char v5; // [rsp+1Bh] [rbp-15h]\n char v6; // [rsp+1Bh] [rbp-15h]\n int v7; // [rsp+1Ch] [rbp-14h]\n int v8; // [rsp+20h] [rbp-10h]\n int i; // [rsp+24h] [rbp-Ch]\n int j; // [rsp+28h] [rbp-8h]\n int k; // [rsp+28h] [rbp-8h]\n\n v7 = 0;\n v8 = 0;\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n {\n if ( *(_BYTE *)(i + a1) == 32 )\n {\n if ( v7 <= 1 )\n {\n v5 = 0;\n }\n else\n {\n v5 = 1;\n for ( j = 2; v7 >= j * j; ++j )\n {\n if ( !(v7 % j) )\n {\n v5 = 0;\n break;\n }\n }\n }\n if ( v5 )\n {\n if ( v8 > 0 )\n {\n v2 = v8++;\n *(_BYTE *)(v2 + a2) = 32;\n }\n memcpy((void *)(a2 + v8), (const void *)(i - (__int64)v7 + a1), v7);\n v8 += v7;\n }\n v7 = 0;\n }\n else\n {\n ++v7;\n }\n }\n if ( v7 <= 1 )\n {\n v6 = 0;\n }\n else\n {\n v6 = 1;\n for ( k = 2; v7 >= k * k; ++k )\n {\n if ( !(v7 % k) )\n {\n v6 = 0;\n break;\n }\n }\n }\n if ( v6 )\n {\n if ( v8 > 0 )\n {\n v3 = v8++;\n *(_BYTE *)(v3 + a2) = 32;\n }\n memcpy((void *)(a2 + v8), (const void *)(i - (__int64)v7 + a1), v7);\n v8 += v7;\n }\n result = (_BYTE *)(v8 + a2);\n *result = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_11A9(long long a1, long long a2) {\n int v2;\n int v3;\n uint8_t *result;\n char v5;\n char v6;\n int v7;\n int v8;\n int i;\n int j;\n int k;\n v7 = 0;\n v8 = 0;\n for (i = 0; *(uint8_t *)(i + a1); ++i) {\n if (*(uint8_t *)(i + a1) == 32) {\n if (v7 <= 1) {\n v5 = 0;\n } else {\n v5 = 1;\n for (j = 2; v7 >= j * j; ++j) {\n if (!(v7 % j)) {\n v5 = 0;\n break;\n }\n }\n }\n if (v5) {\n if (v8 > 0) {\n v2 = v8++;\n *(uint8_t *)(v2 + a2) = 32;\n }\n memcpy((void *)(a2 + v8), (const void *)(i - (long long)v7 + a1), v7);\n v8 += v7;\n }\n v7 = 0;\n } else {\n ++v7;\n }\n }\n if (v7 <= 1) {\n v6 = 0;\n } else {\n v6 = 1;\n for (k = 2; v7 >= k * k; ++k) {\n if (!(v7 % k)) {\n v6 = 0;\n break;\n }\n }\n }\n if (v6) {\n if (v8 > 0) {\n v3 = v8++;\n *(uint8_t *)(v3 + a2) = 32;\n }\n memcpy((void *)(a2 + v8), (const void *)(i - (long long)v7 + a1), v7);\n v8 += v7;\n }\n result = (uint8_t *)(v8 + a2);\n *result = 0;\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(long long a1, long long a2) {\n int v2;\n int v3;\n uint8_t *result;\n char v5;\n char v6;\n int v7;\n int v8;\n int i;\n int j;\n int k;\n v7 = 0;\n v8 = 0;\n for (i = 0; *(uint8_t *)(i + a1); ++i) {\n if (*(uint8_t *)(i + a1) == 32) {\n if (v7 <= 1) {\n v5 = 0;\n } else {\n v5 = 1;\n for (j = 2; v7 >= j * j; ++j) {\n if (!(v7 % j)) {\n v5 = 0;\n break;\n }\n }\n }\n if (v5) {\n if (v8 > 0) {\n v2 = v8++;\n *(uint8_t *)(v2 + a2) = 32;\n }\n memcpy((void *)(a2 + v8), (const void *)(i - (long long)v7 + a1), v7);\n v8 += v7;\n }\n v7 = 0;\n } else {\n ++v7;\n }\n }\n if (v7 <= 1) {\n v6 = 0;\n } else {\n v6 = 1;\n for (k = 2; v7 >= k * k; ++k) {\n if (!(v7 % k)) {\n v6 = 0;\n break;\n }\n }\n }\n if (v6) {\n if (v8 > 0) {\n v3 = v8++;\n *(uint8_t *)(v3 + a2) = 32;\n }\n memcpy((void *)(a2 + v8), (const void *)(i - (long long)v7 + a1), v7);\n v8 += v7;\n }\n result = (uint8_t *)(v8 + a2);\n *result = 0;\n return result;\n}" + }, + { + "index": "HumanEval-C-143", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "void func0(const char* sentence, char* out) {\n int index = 0, word_len = 0;\n int out_index = 0;\n bool is_prime;\n int i, j;\n for (i = 0; sentence[i] != '\\0'; ++i) {\n if (sentence[i] != ' ') {\n word_len++;\n } else {\n if (word_len > 1) {\n is_prime = true;\n for (j = 2; j * j <= word_len; ++j) {\n if (word_len % j == 0) {\n is_prime = false;\n break;\n }\n }\n } else {\n is_prime = false;\n }\n if (is_prime) {\n if (out_index > 0) {\n out[out_index++] = ' ';\n }\n memcpy(out + out_index, sentence + i - word_len, word_len);\n out_index += word_len;\n }\n word_len = 0;\n }\n }\n if (word_len > 1) {\n is_prime = true;\n for (j = 2; j * j <= word_len; ++j) {\n if (word_len % j == 0) {\n is_prime = false;\n break;\n }\n }\n } else {\n is_prime = false;\n }\n if (is_prime) {\n if (out_index > 0) {\n out[out_index++] = ' ';\n }\n memcpy(out + out_index, sentence + i - word_len, word_len);\n out_index += word_len;\n }\n out[out_index] = '\\0';\n}", + "test": "#include \n#include \n\nint main() {\n char output[101];\n\n func0(\"This is a test\", output);\n assert(strcmp(output, \"is\") == 0);\n\n func0(\"lets go for swimming\", output);\n assert(strcmp(output, \"go for\") == 0);\n\n func0(\"there is no place available here\", output);\n assert(strcmp(output, \"there is no place\") == 0);\n\n func0(\"Hi I am Hussein\", output);\n assert(strcmp(output, \"Hi am Hussein\") == 0);\n\n func0(\"go for it\", output);\n assert(strcmp(output, \"go for it\") == 0);\n\n func0(\"here\", output);\n assert(strcmp(output, \"\") == 0);\n\n func0(\"here is\", output);\n assert(strcmp(output, \"is\") == 0);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r14, rsi\nmovzx eax, byte ptr [rdi]\ntest al, al\njz loc_12BD\nmov r12, rdi\nmov r13d, 0\nmov ebx, 0\nmov ebp, 0\njmp short loc_11EF\nloc_11D8:\ncmp ebx, 1\njg short loc_11F8\nmov ebx, 0\nloc_11E2:\nadd rbp, 1\nmovzx eax, byte ptr [r12+rbp]\ntest al, al\njz short loc_1258\nloc_11EF:\ncmp al, 20h ; ' '\njz short loc_11D8\nadd ebx, 1\njmp short loc_11E2\nloc_11F8:\ncmp ebx, 3\njle short loc_1222\nmov eax, ebx\nand eax, 1\njz short loc_1254\nmov ecx, 2\nloc_1209:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, ebx\njg short loc_1222\nmov eax, ebx\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_1209\nmov ebx, edx\njmp short loc_11E2\nloc_1222:\ntest r13d, r13d\njle short loc_1233\nmovsxd rax, r13d\nmov byte ptr [r14+rax], 20h ; ' '\nlea r13d, [r13+1]\nloc_1233:\nmovsxd rdx, ebx; n\nmovsxd rdi, r13d\nadd rdi, r14; dest\nmov rsi, rbp\nsub rsi, rdx\nadd rsi, r12; src\ncall _memcpy\nadd r13d, ebx\nmov ebx, 0\njmp short loc_11E2\nloc_1254:\nmov ebx, eax\njmp short loc_11E2\nloc_1258:\ncmp ebx, 1\njle short loc_12AC\ncmp ebx, 3\njle short loc_1283\ntest bl, 1\njz short loc_12AC\nmov ecx, 2\nloc_126C:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, ebx\njg short loc_1283\nmov eax, ebx\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_126C\njmp short loc_12AC\nloc_1283:\ntest r13d, r13d\njle short loc_1294\nmovsxd rax, r13d\nmov byte ptr [r14+rax], 20h ; ' '\nlea r13d, [r13+1]\nloc_1294:\nmovsxd rdx, ebx; n\nmovsxd rdi, r13d\nadd rdi, r14; dest\nsub rbp, rdx\nlea rsi, [r12+rbp]; src\ncall _memcpy\nadd r13d, ebx\nloc_12AC:\nmovsxd r13, r13d\nmov byte ptr [r14+r13], 0\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_12BD:\nmov r13d, 0\njmp short loc_12AC", + "ida_pseudo": "unsigned __int64 __fastcall func0(unsigned __int8 *a1, __int64 a2)\n{\n unsigned __int64 result; // rax\n int v3; // r13d\n int v4; // ebx\n __int64 v5; // rbp\n int v6; // ecx\n int v7; // ecx\n\n result = *a1;\n if ( !(_BYTE)result )\n {\n v3 = 0;\n goto LABEL_28;\n }\n v3 = 0;\n v4 = 0;\n v5 = 0LL;\n do\n {\n if ( (_BYTE)result != 32 )\n {\n ++v4;\n goto LABEL_5;\n }\n if ( v4 <= 1 )\n {\n v4 = 0;\n goto LABEL_5;\n }\n if ( v4 > 3 )\n {\n if ( (v4 & 1) == 0 )\n {\n v4 &= 1u;\n goto LABEL_5;\n }\n v6 = 2;\n while ( 1 )\n {\n ++v6;\n if ( v6 * v6 > v4 )\n break;\n if ( !(v4 % v6) )\n {\n v4 = 0;\n goto LABEL_5;\n }\n }\n }\n if ( v3 > 0 )\n *(_BYTE *)(a2 + v3++) = 32;\n memcpy((void *)(a2 + v3), &a1[v5 - v4], v4);\n v3 += v4;\n v4 = 0;\nLABEL_5:\n result = a1[++v5];\n }\n while ( (_BYTE)result );\n if ( v4 > 1 )\n {\n if ( v4 <= 3 )\n goto LABEL_25;\n if ( (v4 & 1) != 0 )\n {\n v7 = 2;\n while ( 1 )\n {\n ++v7;\n if ( v7 * v7 > v4 )\n break;\n result = (unsigned int)(v4 / v7);\n if ( !(v4 % v7) )\n goto LABEL_28;\n }\nLABEL_25:\n if ( v3 > 0 )\n *(_BYTE *)(a2 + v3++) = 32;\n result = (unsigned __int64)memcpy((void *)(a2 + v3), &a1[v5 - v4], v4);\n v3 += v4;\n }\n }\nLABEL_28:\n *(_BYTE *)(a2 + v3) = 0;\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r14, rsi\nmovzx eax, byte ptr [rdi]\ntest al, al\njz loc_12BD\nmov r12, rdi\nmov r13d, 0\nmov ebx, 0\nmov ebp, 0\njmp short loc_11EF\nloc_11D8:\ncmp ebx, 1\njg short loc_11F8\nmov ebx, 0\nloc_11E2:\nadd rbp, 1\nmovzx eax, byte ptr [r12+rbp]\ntest al, al\njz short loc_1258\nloc_11EF:\ncmp al, 20h ; ' '\njz short loc_11D8\nadd ebx, 1\njmp short loc_11E2\nloc_11F8:\ncmp ebx, 3\njle short loc_1222\nmov eax, ebx\nand eax, 1\njz short loc_1254\nmov ecx, 2\nloc_1209:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, ebx\njg short loc_1222\nmov eax, ebx\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_1209\nmov ebx, edx\njmp short loc_11E2\nloc_1222:\ntest r13d, r13d\njle short loc_1233\nmovsxd rax, r13d\nmov byte ptr [r14+rax], 20h ; ' '\nlea r13d, [r13+1]\nloc_1233:\nmovsxd rdx, ebx; n\nmovsxd rdi, r13d\nadd rdi, r14; dest\nmov rsi, rbp\nsub rsi, rdx\nadd rsi, r12; src\ncall _memcpy\nadd r13d, ebx\nmov ebx, 0\njmp short loc_11E2\nloc_1254:\nmov ebx, eax\njmp short loc_11E2\nloc_1258:\ncmp ebx, 1\njle short loc_12AC\ncmp ebx, 3\njle short loc_1283\ntest bl, 1\njz short loc_12AC\nmov ecx, 2\nloc_126C:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, ebx\njg short loc_1283\nmov eax, ebx\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_126C\njmp short loc_12AC\nloc_1283:\ntest r13d, r13d\njle short loc_1294\nmovsxd rax, r13d\nmov byte ptr [r14+rax], 20h ; ' '\nlea r13d, [r13+1]\nloc_1294:\nmovsxd rdx, ebx; n\nmovsxd rdi, r13d\nadd rdi, r14; dest\nsub rbp, rdx\nlea rsi, [r12+rbp]; src\ncall _memcpy\nadd r13d, ebx\nloc_12AC:\nmovsxd r13, r13d\nmov byte ptr [r14+r13], 0\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_12BD:\nmov r13d, 0\njmp short loc_12AC", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_11A9(unsigned __int8 *a1, __int64 a2)\n{\n unsigned __int64 result; // rax\n int v3; // r13d\n int v4; // ebx\n __int64 v5; // rbp\n int v6; // ecx\n int v7; // ecx\n\n result = *a1;\n if ( !(_BYTE)result )\n {\n v3 = 0;\n goto LABEL_28;\n }\n v3 = 0;\n v4 = 0;\n v5 = 0LL;\n do\n {\n if ( (_BYTE)result != 32 )\n {\n ++v4;\n goto LABEL_5;\n }\n if ( v4 <= 1 )\n {\n v4 = 0;\n goto LABEL_5;\n }\n if ( v4 > 3 )\n {\n if ( (v4 & 1) == 0 )\n {\n v4 &= 1u;\n goto LABEL_5;\n }\n v6 = 2;\n while ( 1 )\n {\n ++v6;\n if ( v6 * v6 > v4 )\n break;\n if ( !(v4 % v6) )\n {\n v4 = 0;\n goto LABEL_5;\n }\n }\n }\n if ( v3 > 0 )\n *(_BYTE *)(a2 + v3++) = 32;\n memcpy((void *)(a2 + v3), &a1[v5 - v4], v4);\n v3 += v4;\n v4 = 0;\nLABEL_5:\n result = a1[++v5];\n }\n while ( (_BYTE)result );\n if ( v4 > 1 )\n {\n if ( v4 <= 3 )\n goto LABEL_25;\n if ( (v4 & 1) != 0 )\n {\n v7 = 2;\n while ( 1 )\n {\n ++v7;\n if ( v7 * v7 > v4 )\n break;\n result = (unsigned int)(v4 / v7);\n if ( !(v4 % v7) )\n goto LABEL_28;\n }\nLABEL_25:\n if ( v3 > 0 )\n *(_BYTE *)(a2 + v3++) = 32;\n result = (unsigned __int64)memcpy((void *)(a2 + v3), &a1[v5 - v4], v4);\n v3 += v4;\n }\n }\nLABEL_28:\n *(_BYTE *)(a2 + v3) = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_11A9(unsigned char *a1, long long a2) {\n unsigned long long result;\n int v3;\n int v4;\n long long v5;\n int v6;\n int v7;\n result = *a1;\n if (!(uint8_t)result) {\n v3 = 0;\n goto LABEL_28;\n }\n v3 = 0;\n v4 = 0;\n v5 = 0LL;\n do {\n if ((uint8_t)result != 32) {\n ++v4;\n goto LABEL_5;\n }\n if (v4 <= 1) {\n v4 = 0;\n goto LABEL_5;\n }\n if (v4 > 3) {\n if ((v4 & 1) == 0) {\n v4 &= 1u;\n goto LABEL_5;\n }\n v6 = 2;\n while (1) {\n ++v6;\n if (v6 * v6 > v4) break;\n if (!(v4 % v6)) {\n v4 = 0;\n goto LABEL_5;\n }\n }\n }\n if (v3 > 0) *(uint8_t *)(a2 + v3++) = 32;\n memcpy((void *)(a2 + v3), &a1[v5 - v4], v4);\n v3 += v4;\n v4 = 0;\n LABEL_5:\n result = a1[++v5];\n } while ((uint8_t)result);\n if (v4 > 1) {\n if (v4 <= 3) goto LABEL_25;\n if ((v4 & 1) != 0) {\n v7 = 2;\n while (1) {\n ++v7;\n if (v7 * v7 > v4) break;\n result = (unsigned int)(v4 / v7);\n if (!(v4 % v7)) goto LABEL_28;\n }\n LABEL_25:\n if (v3 > 0) *(uint8_t *)(a2 + v3++) = 32;\n result = (unsigned long long)memcpy((void *)(a2 + v3), &a1[v5 - v4], v4);\n v3 += v4;\n }\n }\nLABEL_28:\n *(uint8_t *)(a2 + v3) = 0;\n return result;\n}", + "ida_pseudo_norm": "unsigned long long func0(unsigned char *a1, long long a2) {\n unsigned long long result;\n int v3;\n int v4;\n long long v5;\n int v6;\n int v7;\n result = *a1;\n if (!(uint8_t)result) {\n v3 = 0;\n goto LABEL_28;\n }\n v3 = 0;\n v4 = 0;\n v5 = 0LL;\n do {\n if ((uint8_t)result != 32) {\n ++v4;\n goto LABEL_5;\n }\n if (v4 <= 1) {\n v4 = 0;\n goto LABEL_5;\n }\n if (v4 > 3) {\n if ((v4 & 1) == 0) {\n v4 &= 1u;\n goto LABEL_5;\n }\n v6 = 2;\n while (1) {\n ++v6;\n if (v6 * v6 > v4) break;\n if (!(v4 % v6)) {\n v4 = 0;\n goto LABEL_5;\n }\n }\n }\n if (v3 > 0) *(uint8_t *)(a2 + v3++) = 32;\n memcpy((void *)(a2 + v3), &a1[v5 - v4], v4);\n v3 += v4;\n v4 = 0;\n LABEL_5:\n result = a1[++v5];\n } while ((uint8_t)result);\n if (v4 > 1) {\n if (v4 <= 3) goto LABEL_25;\n if ((v4 & 1) != 0) {\n v7 = 2;\n while (1) {\n ++v7;\n if (v7 * v7 > v4) break;\n result = (unsigned int)(v4 / v7);\n if (!(v4 % v7)) goto LABEL_28;\n }\n LABEL_25:\n if (v3 > 0) *(uint8_t *)(a2 + v3++) = 32;\n result = (unsigned long long)memcpy((void *)(a2 + v3), &a1[v5 - v4], v4);\n v3 += v4;\n }\n }\nLABEL_28:\n *(uint8_t *)(a2 + v3) = 0;\n return result;\n}" + }, + { + "index": "HumanEval-C-143", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "void func0(const char* sentence, char* out) {\n int index = 0, word_len = 0;\n int out_index = 0;\n bool is_prime;\n int i, j;\n for (i = 0; sentence[i] != '\\0'; ++i) {\n if (sentence[i] != ' ') {\n word_len++;\n } else {\n if (word_len > 1) {\n is_prime = true;\n for (j = 2; j * j <= word_len; ++j) {\n if (word_len % j == 0) {\n is_prime = false;\n break;\n }\n }\n } else {\n is_prime = false;\n }\n if (is_prime) {\n if (out_index > 0) {\n out[out_index++] = ' ';\n }\n memcpy(out + out_index, sentence + i - word_len, word_len);\n out_index += word_len;\n }\n word_len = 0;\n }\n }\n if (word_len > 1) {\n is_prime = true;\n for (j = 2; j * j <= word_len; ++j) {\n if (word_len % j == 0) {\n is_prime = false;\n break;\n }\n }\n } else {\n is_prime = false;\n }\n if (is_prime) {\n if (out_index > 0) {\n out[out_index++] = ' ';\n }\n memcpy(out + out_index, sentence + i - word_len, word_len);\n out_index += word_len;\n }\n out[out_index] = '\\0';\n}", + "test": "#include \n#include \n\nint main() {\n char output[101];\n\n func0(\"This is a test\", output);\n assert(strcmp(output, \"is\") == 0);\n\n func0(\"lets go for swimming\", output);\n assert(strcmp(output, \"go for\") == 0);\n\n func0(\"there is no place available here\", output);\n assert(strcmp(output, \"there is no place\") == 0);\n\n func0(\"Hi I am Hussein\", output);\n assert(strcmp(output, \"Hi am Hussein\") == 0);\n\n func0(\"go for it\", output);\n assert(strcmp(output, \"go for it\") == 0);\n\n func0(\"here\", output);\n assert(strcmp(output, \"\") == 0);\n\n func0(\"here is\", output);\n assert(strcmp(output, \"is\") == 0);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\nmov r12, rsi\npush rbp\npush rbx\nmovzx eax, byte ptr [rdi]\ntest al, al\njz loc_1471\nmov r13, rdi\nxor r14d, r14d\nxor ebx, ebx\nxor ebp, ebp\njmp short loc_13F1\nloc_13E0:\nadd ebx, 1\nloc_13E3:\nadd rbp, 1\nmovzx eax, byte ptr [r13+rbp+0]\ntest al, al\njz short loc_140E\nloc_13F1:\ncmp al, 20h ; ' '\njnz short loc_13E0\ncmp ebx, 1\njg loc_1480\nloc_13FE:\nadd rbp, 1\nxor ebx, ebx\nmovzx eax, byte ptr [r13+rbp+0]\ntest al, al\njnz short loc_13F1\nloc_140E:\nmovsxd rdi, r14d\nlea rsi, [r12+rdi]\ncmp ebx, 1\njle short loc_1471\ncmp ebx, 3\njle short loc_1445\ntest bl, 1\njz short loc_1471\nmov ecx, 2\njmp short loc_1439\nloc_1430:\nmov eax, ebx\ncdq\nidiv ecx\ntest edx, edx\njz short loc_1471\nloc_1439:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, ebx\njle short loc_1430\nloc_1445:\ntest r14d, r14d\njle short loc_1454\nmov byte ptr [rsi], 20h ; ' '\nadd r14d, 1\nmovsxd rdi, r14d\nloc_1454:\nmovsxd rdx, ebx; n\nadd ebx, r14d\nadd rdi, r12; dest\nsub rbp, rdx\nmovsxd rbx, ebx\nlea rsi, [r13+rbp+0]; src\ncall _memcpy\nlea rsi, [r12+rbx]\nloc_1471:\nmov byte ptr [rsi], 0\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1480:\ncmp ebx, 3\njle short loc_14B1\ntest bl, 1\njz loc_13FE\nmov ecx, 2\njmp short loc_14A5\nloc_1498:\nmov eax, ebx\ncdq\nidiv ecx\ntest edx, edx\njz loc_13FE\nloc_14A5:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, ebx\njle short loc_1498\nloc_14B1:\ntest r14d, r14d\njle short loc_14C2\nmovsxd rax, r14d\nadd r14d, 1\nmov byte ptr [r12+rax], 20h ; ' '\nloc_14C2:\nmovsxd rdx, ebx; n\nmov rsi, rbp\nmovsxd rdi, r14d\nadd r14d, ebx\nsub rsi, rdx\nadd rdi, r12; dest\nxor ebx, ebx\nadd rsi, r13; src\ncall _memcpy\njmp loc_13E3", + "ida_pseudo": "unsigned __int64 __fastcall func0(unsigned __int8 *a1, _BYTE *a2)\n{\n _BYTE *v2; // r12\n unsigned __int64 result; // rax\n int v5; // r14d\n int v6; // ebx\n __int64 v7; // rbp\n __int64 v8; // rdi\n int v9; // ecx\n int v10; // ecx\n __int64 v11; // rax\n size_t v12; // rdx\n __int64 v13; // rdi\n __int64 v14; // rsi\n\n v2 = a2;\n result = *a1;\n if ( !(_BYTE)result )\n goto LABEL_17;\n v5 = 0;\n v6 = 0;\n v7 = 0LL;\n do\n {\n while ( (_BYTE)result != 32 )\n {\n ++v6;\nLABEL_4:\n result = a1[++v7];\n if ( !(_BYTE)result )\n goto LABEL_8;\n }\n if ( v6 <= 1 )\n goto LABEL_7;\n if ( v6 <= 3 )\n goto LABEL_23;\n if ( (v6 & 1) != 0 )\n {\n v10 = 2;\n while ( 1 )\n {\n ++v10;\n if ( v10 * v10 > v6 )\n break;\n if ( !(v6 % v10) )\n goto LABEL_7;\n }\nLABEL_23:\n if ( v5 > 0 )\n {\n v11 = v5++;\n v2[v11] = 32;\n }\n v12 = v6;\n v13 = v5;\n v5 += v6;\n v14 = v7 - v6;\n v6 = 0;\n memcpy(&v2[v13], &a1[v14], v12);\n goto LABEL_4;\n }\nLABEL_7:\n ++v7;\n v6 = 0;\n result = a1[v7];\n }\n while ( (_BYTE)result );\nLABEL_8:\n v8 = v5;\n a2 = &v2[v5];\n if ( v6 > 1 )\n {\n if ( v6 <= 3 )\n goto LABEL_14;\n if ( (v6 & 1) != 0 )\n {\n v9 = 2;\n while ( 1 )\n {\n ++v9;\n if ( v9 * v9 > v6 )\n break;\n result = (unsigned int)(v6 / v9);\n if ( !(v6 % v9) )\n goto LABEL_17;\n }\nLABEL_14:\n if ( v5 > 0 )\n {\n *a2 = 32;\n v8 = ++v5;\n }\n result = (unsigned __int64)memcpy(&v2[v8], &a1[v7 - v6], v6);\n a2 = &v2[v5 + v6];\n }\n }\nLABEL_17:\n *a2 = 0;\n return result;\n}", + "ida_strip_asm": "sub_13B0:\nendbr64\npush r14\npush r13\npush r12\nmov r12, rsi\npush rbp\npush rbx\nmovzx eax, byte ptr [rdi]\ntest al, al\njz loc_1471\nmov r13, rdi\nxor r14d, r14d\nxor ebx, ebx\nxor ebp, ebp\njmp short loc_13F1\nloc_13E0:\nadd ebx, 1\nloc_13E3:\nadd rbp, 1\nmovzx eax, byte ptr [r13+rbp+0]\ntest al, al\njz short loc_140E\nloc_13F1:\ncmp al, 20h ; ' '\njnz short loc_13E0\ncmp ebx, 1\njg loc_1480\nloc_13FE:\nadd rbp, 1\nxor ebx, ebx\nmovzx eax, byte ptr [r13+rbp+0]\ntest al, al\njnz short loc_13F1\nloc_140E:\nmovsxd rdi, r14d\nlea rsi, [r12+rdi]\ncmp ebx, 1\njle short loc_1471\ncmp ebx, 3\njle short loc_1445\ntest bl, 1\njz short loc_1471\nmov ecx, 2\njmp short loc_1439\nloc_1430:\nmov eax, ebx\ncdq\nidiv ecx\ntest edx, edx\njz short loc_1471\nloc_1439:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, ebx\njle short loc_1430\nloc_1445:\ntest r14d, r14d\njle short loc_1454\nmov byte ptr [rsi], 20h ; ' '\nadd r14d, 1\nmovsxd rdi, r14d\nloc_1454:\nmovsxd rdx, ebx; n\nadd ebx, r14d\nadd rdi, r12; dest\nsub rbp, rdx\nmovsxd rbx, ebx\nlea rsi, [r13+rbp+0]; src\ncall _memcpy\nlea rsi, [r12+rbx]\nloc_1471:\nmov byte ptr [rsi], 0\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1480:\ncmp ebx, 3\njle short loc_14B1\ntest bl, 1\njz loc_13FE\nmov ecx, 2\njmp short loc_14A5\nloc_1498:\nmov eax, ebx\ncdq\nidiv ecx\ntest edx, edx\njz loc_13FE\nloc_14A5:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, ebx\njle short loc_1498\nloc_14B1:\ntest r14d, r14d\njle short loc_14C2\nmovsxd rax, r14d\nadd r14d, 1\nmov byte ptr [r12+rax], 20h ; ' '\nloc_14C2:\nmovsxd rdx, ebx; n\nmov rsi, rbp\nmovsxd rdi, r14d\nadd r14d, ebx\nsub rsi, rdx\nadd rdi, r12; dest\nxor ebx, ebx\nadd rsi, r13; src\ncall _memcpy\njmp loc_13E3", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_13B0(unsigned __int8 *a1, _BYTE *a2)\n{\n _BYTE *v2; // r12\n unsigned __int64 result; // rax\n int v5; // r14d\n int v6; // ebx\n __int64 v7; // rbp\n __int64 v8; // rdi\n int v9; // ecx\n int v10; // ecx\n __int64 v11; // rax\n size_t v12; // rdx\n __int64 v13; // rdi\n __int64 v14; // rsi\n\n v2 = a2;\n result = *a1;\n if ( !(_BYTE)result )\n goto LABEL_17;\n v5 = 0;\n v6 = 0;\n v7 = 0LL;\n do\n {\n while ( (_BYTE)result != 32 )\n {\n ++v6;\nLABEL_4:\n result = a1[++v7];\n if ( !(_BYTE)result )\n goto LABEL_8;\n }\n if ( v6 <= 1 )\n goto LABEL_7;\n if ( v6 <= 3 )\n goto LABEL_23;\n if ( (v6 & 1) != 0 )\n {\n v10 = 2;\n while ( 1 )\n {\n ++v10;\n if ( v10 * v10 > v6 )\n break;\n if ( !(v6 % v10) )\n goto LABEL_7;\n }\nLABEL_23:\n if ( v5 > 0 )\n {\n v11 = v5++;\n v2[v11] = 32;\n }\n v12 = v6;\n v13 = v5;\n v5 += v6;\n v14 = v7 - v6;\n v6 = 0;\n memcpy(&v2[v13], &a1[v14], v12);\n goto LABEL_4;\n }\nLABEL_7:\n ++v7;\n v6 = 0;\n result = a1[v7];\n }\n while ( (_BYTE)result );\nLABEL_8:\n v8 = v5;\n a2 = &v2[v5];\n if ( v6 > 1 )\n {\n if ( v6 <= 3 )\n goto LABEL_14;\n if ( (v6 & 1) != 0 )\n {\n v9 = 2;\n while ( 1 )\n {\n ++v9;\n if ( v9 * v9 > v6 )\n break;\n result = (unsigned int)(v6 / v9);\n if ( !(v6 % v9) )\n goto LABEL_17;\n }\nLABEL_14:\n if ( v5 > 0 )\n {\n *a2 = 32;\n v8 = ++v5;\n }\n result = (unsigned __int64)memcpy(&v2[v8], &a1[v7 - v6], v6);\n a2 = &v2[v5 + v6];\n }\n }\nLABEL_17:\n *a2 = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_13B0(unsigned char *a1, uint8_t *a2) {\n uint8_t *v2;\n unsigned long long result;\n int v5;\n int v6;\n long long v7;\n long long v8;\n int v9;\n int v10;\n long long v11;\n unsigned int v12;\n long long v13;\n long long v14;\n v2 = a2;\n result = *a1;\n if (!(uint8_t)result) goto LABEL_17;\n v5 = 0;\n v6 = 0;\n v7 = 0LL;\n do {\n while ((uint8_t)result != 32) {\n ++v6;\n LABEL_4:\n result = a1[++v7];\n if (!(uint8_t)result) goto LABEL_8;\n }\n if (v6 <= 1) goto LABEL_7;\n if (v6 <= 3) goto LABEL_23;\n if ((v6 & 1) != 0) {\n v10 = 2;\n while (1) {\n ++v10;\n if (v10 * v10 > v6) break;\n if (!(v6 % v10)) goto LABEL_7;\n }\n LABEL_23:\n if (v5 > 0) {\n v11 = v5++;\n v2[v11] = 32;\n }\n v12 = v6;\n v13 = v5;\n v5 += v6;\n v14 = v7 - v6;\n v6 = 0;\n memcpy(&v2[v13], &a1[v14], v12);\n goto LABEL_4;\n }\n LABEL_7:\n ++v7;\n v6 = 0;\n result = a1[v7];\n } while ((uint8_t)result);\nLABEL_8:\n v8 = v5;\n a2 = &v2[v5];\n if (v6 > 1) {\n if (v6 <= 3) goto LABEL_14;\n if ((v6 & 1) != 0) {\n v9 = 2;\n while (1) {\n ++v9;\n if (v9 * v9 > v6) break;\n result = (unsigned int)(v6 / v9);\n if (!(v6 % v9)) goto LABEL_17;\n }\n LABEL_14:\n if (v5 > 0) {\n *a2 = 32;\n v8 = ++v5;\n }\n result = (unsigned long long)memcpy(&v2[v8], &a1[v7 - v6], v6);\n a2 = &v2[v5 + v6];\n }\n }\nLABEL_17:\n *a2 = 0;\n return result;\n}", + "ida_pseudo_norm": "unsigned long long func0(unsigned char *a1, uint8_t *a2) {\n uint8_t *v2;\n unsigned long long result;\n int v5;\n int v6;\n long long v7;\n long long v8;\n int v9;\n int v10;\n long long v11;\n unsigned int v12;\n long long v13;\n long long v14;\n v2 = a2;\n result = *a1;\n if (!(uint8_t)result) goto LABEL_17;\n v5 = 0;\n v6 = 0;\n v7 = 0LL;\n do {\n while ((uint8_t)result != 32) {\n ++v6;\n LABEL_4:\n result = a1[++v7];\n if (!(uint8_t)result) goto LABEL_8;\n }\n if (v6 <= 1) goto LABEL_7;\n if (v6 <= 3) goto LABEL_23;\n if ((v6 & 1) != 0) {\n v10 = 2;\n while (1) {\n ++v10;\n if (v10 * v10 > v6) break;\n if (!(v6 % v10)) goto LABEL_7;\n }\n LABEL_23:\n if (v5 > 0) {\n v11 = v5++;\n v2[v11] = 32;\n }\n v12 = v6;\n v13 = v5;\n v5 += v6;\n v14 = v7 - v6;\n v6 = 0;\n memcpy(&v2[v13], &a1[v14], v12);\n goto LABEL_4;\n }\n LABEL_7:\n ++v7;\n v6 = 0;\n result = a1[v7];\n } while ((uint8_t)result);\nLABEL_8:\n v8 = v5;\n a2 = &v2[v5];\n if (v6 > 1) {\n if (v6 <= 3) goto LABEL_14;\n if ((v6 & 1) != 0) {\n v9 = 2;\n while (1) {\n ++v9;\n if (v9 * v9 > v6) break;\n result = (unsigned int)(v6 / v9);\n if (!(v6 % v9)) goto LABEL_17;\n }\n LABEL_14:\n if (v5 > 0) {\n *a2 = 32;\n v8 = ++v5;\n }\n result = (unsigned long long)memcpy(&v2[v8], &a1[v7 - v6], v6);\n a2 = &v2[v5 + v6];\n }\n }\nLABEL_17:\n *a2 = 0;\n return result;\n}" + }, + { + "index": "HumanEval-C-143", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "void func0(const char* sentence, char* out) {\n int index = 0, word_len = 0;\n int out_index = 0;\n bool is_prime;\n int i, j;\n for (i = 0; sentence[i] != '\\0'; ++i) {\n if (sentence[i] != ' ') {\n word_len++;\n } else {\n if (word_len > 1) {\n is_prime = true;\n for (j = 2; j * j <= word_len; ++j) {\n if (word_len % j == 0) {\n is_prime = false;\n break;\n }\n }\n } else {\n is_prime = false;\n }\n if (is_prime) {\n if (out_index > 0) {\n out[out_index++] = ' ';\n }\n memcpy(out + out_index, sentence + i - word_len, word_len);\n out_index += word_len;\n }\n word_len = 0;\n }\n }\n if (word_len > 1) {\n is_prime = true;\n for (j = 2; j * j <= word_len; ++j) {\n if (word_len % j == 0) {\n is_prime = false;\n break;\n }\n }\n } else {\n is_prime = false;\n }\n if (is_prime) {\n if (out_index > 0) {\n out[out_index++] = ' ';\n }\n memcpy(out + out_index, sentence + i - word_len, word_len);\n out_index += word_len;\n }\n out[out_index] = '\\0';\n}", + "test": "#include \n#include \n\nint main() {\n char output[101];\n\n func0(\"This is a test\", output);\n assert(strcmp(output, \"is\") == 0);\n\n func0(\"lets go for swimming\", output);\n assert(strcmp(output, \"go for\") == 0);\n\n func0(\"there is no place available here\", output);\n assert(strcmp(output, \"there is no place\") == 0);\n\n func0(\"Hi I am Hussein\", output);\n assert(strcmp(output, \"Hi am Hussein\") == 0);\n\n func0(\"go for it\", output);\n assert(strcmp(output, \"go for it\") == 0);\n\n func0(\"here\", output);\n assert(strcmp(output, \"\") == 0);\n\n func0(\"here is\", output);\n assert(strcmp(output, \"is\") == 0);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\nmov r12, rsi\npush rbp\npush rbx\nmovzx eax, byte ptr [rdi]\ntest al, al\njz loc_1471\nmov r13, rdi\nxor r14d, r14d\nxor ebx, ebx\nxor ebp, ebp\njmp short loc_13F1\nloc_13E0:\nadd ebx, 1\nloc_13E3:\nadd rbp, 1\nmovzx eax, byte ptr [r13+rbp+0]\ntest al, al\njz short loc_140E\nloc_13F1:\ncmp al, 20h ; ' '\njnz short loc_13E0\ncmp ebx, 1\njg loc_1480\nloc_13FE:\nadd rbp, 1\nxor ebx, ebx\nmovzx eax, byte ptr [r13+rbp+0]\ntest al, al\njnz short loc_13F1\nloc_140E:\nmovsxd rdi, r14d\nlea rsi, [r12+rdi]\ncmp ebx, 1\njle short loc_1471\ncmp ebx, 3\njle short loc_1445\ntest bl, 1\njz short loc_1471\nmov ecx, 2\njmp short loc_1439\nloc_1430:\nmov eax, ebx\ncdq\nidiv ecx\ntest edx, edx\njz short loc_1471\nloc_1439:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, ebx\njle short loc_1430\nloc_1445:\ntest r14d, r14d\njle short loc_1454\nmov byte ptr [rsi], 20h ; ' '\nadd r14d, 1\nmovsxd rdi, r14d\nloc_1454:\nmovsxd rdx, ebx; n\nadd ebx, r14d\nadd rdi, r12; dest\nsub rbp, rdx\nmovsxd rbx, ebx\nlea rsi, [r13+rbp+0]; src\ncall _memcpy\nlea rsi, [r12+rbx]\nloc_1471:\nmov byte ptr [rsi], 0\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1480:\ncmp ebx, 3\njle short loc_14B1\ntest bl, 1\njz loc_13FE\nmov ecx, 2\njmp short loc_14A5\nloc_1498:\nmov eax, ebx\ncdq\nidiv ecx\ntest edx, edx\njz loc_13FE\nloc_14A5:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, ebx\njle short loc_1498\nloc_14B1:\ntest r14d, r14d\njle short loc_14C2\nmovsxd rax, r14d\nadd r14d, 1\nmov byte ptr [r12+rax], 20h ; ' '\nloc_14C2:\nmovsxd rdx, ebx; n\nmov rsi, rbp\nmovsxd rdi, r14d\nadd r14d, ebx\nsub rsi, rdx\nadd rdi, r12; dest\nxor ebx, ebx\nadd rsi, r13; src\ncall _memcpy\njmp loc_13E3", + "ida_pseudo": "unsigned __int64 __fastcall func0(unsigned __int8 *a1, _BYTE *a2)\n{\n _BYTE *v2; // r12\n unsigned __int64 result; // rax\n int v5; // r14d\n int v6; // ebx\n __int64 v7; // rbp\n __int64 v8; // rdi\n int v9; // ecx\n int v10; // ecx\n __int64 v11; // rax\n size_t v12; // rdx\n __int64 v13; // rdi\n __int64 v14; // rsi\n\n v2 = a2;\n result = *a1;\n if ( !(_BYTE)result )\n goto LABEL_17;\n v5 = 0;\n v6 = 0;\n v7 = 0LL;\n do\n {\n while ( (_BYTE)result != 32 )\n {\n ++v6;\nLABEL_4:\n result = a1[++v7];\n if ( !(_BYTE)result )\n goto LABEL_8;\n }\n if ( v6 <= 1 )\n goto LABEL_7;\n if ( v6 <= 3 )\n goto LABEL_23;\n if ( (v6 & 1) != 0 )\n {\n v10 = 2;\n while ( 1 )\n {\n ++v10;\n if ( v10 * v10 > v6 )\n break;\n if ( !(v6 % v10) )\n goto LABEL_7;\n }\nLABEL_23:\n if ( v5 > 0 )\n {\n v11 = v5++;\n v2[v11] = 32;\n }\n v12 = v6;\n v13 = v5;\n v5 += v6;\n v14 = v7 - v6;\n v6 = 0;\n memcpy(&v2[v13], &a1[v14], v12);\n goto LABEL_4;\n }\nLABEL_7:\n ++v7;\n v6 = 0;\n result = a1[v7];\n }\n while ( (_BYTE)result );\nLABEL_8:\n v8 = v5;\n a2 = &v2[v5];\n if ( v6 > 1 )\n {\n if ( v6 <= 3 )\n goto LABEL_14;\n if ( (v6 & 1) != 0 )\n {\n v9 = 2;\n while ( 1 )\n {\n ++v9;\n if ( v9 * v9 > v6 )\n break;\n result = (unsigned int)(v6 / v9);\n if ( !(v6 % v9) )\n goto LABEL_17;\n }\nLABEL_14:\n if ( v5 > 0 )\n {\n *a2 = 32;\n v8 = ++v5;\n }\n result = (unsigned __int64)memcpy(&v2[v8], &a1[v7 - v6], v6);\n a2 = &v2[v5 + v6];\n }\n }\nLABEL_17:\n *a2 = 0;\n return result;\n}", + "ida_strip_asm": "sub_13B0:\nendbr64\npush r14\npush r13\npush r12\nmov r12, rsi\npush rbp\npush rbx\nmovzx eax, byte ptr [rdi]\ntest al, al\njz loc_1471\nmov r13, rdi\nxor r14d, r14d\nxor ebx, ebx\nxor ebp, ebp\njmp short loc_13F1\nloc_13E0:\nadd ebx, 1\nloc_13E3:\nadd rbp, 1\nmovzx eax, byte ptr [r13+rbp+0]\ntest al, al\njz short loc_140E\nloc_13F1:\ncmp al, 20h ; ' '\njnz short loc_13E0\ncmp ebx, 1\njg loc_1480\nloc_13FE:\nadd rbp, 1\nxor ebx, ebx\nmovzx eax, byte ptr [r13+rbp+0]\ntest al, al\njnz short loc_13F1\nloc_140E:\nmovsxd rdi, r14d\nlea rsi, [r12+rdi]\ncmp ebx, 1\njle short loc_1471\ncmp ebx, 3\njle short loc_1445\ntest bl, 1\njz short loc_1471\nmov ecx, 2\njmp short loc_1439\nloc_1430:\nmov eax, ebx\ncdq\nidiv ecx\ntest edx, edx\njz short loc_1471\nloc_1439:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, ebx\njle short loc_1430\nloc_1445:\ntest r14d, r14d\njle short loc_1454\nmov byte ptr [rsi], 20h ; ' '\nadd r14d, 1\nmovsxd rdi, r14d\nloc_1454:\nmovsxd rdx, ebx; n\nadd ebx, r14d\nadd rdi, r12; dest\nsub rbp, rdx\nmovsxd rbx, ebx\nlea rsi, [r13+rbp+0]; src\ncall _memcpy\nlea rsi, [r12+rbx]\nloc_1471:\nmov byte ptr [rsi], 0\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1480:\ncmp ebx, 3\njle short loc_14B1\ntest bl, 1\njz loc_13FE\nmov ecx, 2\njmp short loc_14A5\nloc_1498:\nmov eax, ebx\ncdq\nidiv ecx\ntest edx, edx\njz loc_13FE\nloc_14A5:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, ebx\njle short loc_1498\nloc_14B1:\ntest r14d, r14d\njle short loc_14C2\nmovsxd rax, r14d\nadd r14d, 1\nmov byte ptr [r12+rax], 20h ; ' '\nloc_14C2:\nmovsxd rdx, ebx; n\nmov rsi, rbp\nmovsxd rdi, r14d\nadd r14d, ebx\nsub rsi, rdx\nadd rdi, r12; dest\nxor ebx, ebx\nadd rsi, r13; src\ncall _memcpy\njmp loc_13E3", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_13B0(unsigned __int8 *a1, _BYTE *a2)\n{\n _BYTE *v2; // r12\n unsigned __int64 result; // rax\n int v5; // r14d\n int v6; // ebx\n __int64 v7; // rbp\n __int64 v8; // rdi\n int v9; // ecx\n int v10; // ecx\n __int64 v11; // rax\n size_t v12; // rdx\n __int64 v13; // rdi\n __int64 v14; // rsi\n\n v2 = a2;\n result = *a1;\n if ( !(_BYTE)result )\n goto LABEL_17;\n v5 = 0;\n v6 = 0;\n v7 = 0LL;\n do\n {\n while ( (_BYTE)result != 32 )\n {\n ++v6;\nLABEL_4:\n result = a1[++v7];\n if ( !(_BYTE)result )\n goto LABEL_8;\n }\n if ( v6 <= 1 )\n goto LABEL_7;\n if ( v6 <= 3 )\n goto LABEL_23;\n if ( (v6 & 1) != 0 )\n {\n v10 = 2;\n while ( 1 )\n {\n ++v10;\n if ( v10 * v10 > v6 )\n break;\n if ( !(v6 % v10) )\n goto LABEL_7;\n }\nLABEL_23:\n if ( v5 > 0 )\n {\n v11 = v5++;\n v2[v11] = 32;\n }\n v12 = v6;\n v13 = v5;\n v5 += v6;\n v14 = v7 - v6;\n v6 = 0;\n memcpy(&v2[v13], &a1[v14], v12);\n goto LABEL_4;\n }\nLABEL_7:\n ++v7;\n v6 = 0;\n result = a1[v7];\n }\n while ( (_BYTE)result );\nLABEL_8:\n v8 = v5;\n a2 = &v2[v5];\n if ( v6 > 1 )\n {\n if ( v6 <= 3 )\n goto LABEL_14;\n if ( (v6 & 1) != 0 )\n {\n v9 = 2;\n while ( 1 )\n {\n ++v9;\n if ( v9 * v9 > v6 )\n break;\n result = (unsigned int)(v6 / v9);\n if ( !(v6 % v9) )\n goto LABEL_17;\n }\nLABEL_14:\n if ( v5 > 0 )\n {\n *a2 = 32;\n v8 = ++v5;\n }\n result = (unsigned __int64)memcpy(&v2[v8], &a1[v7 - v6], v6);\n a2 = &v2[v5 + v6];\n }\n }\nLABEL_17:\n *a2 = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_13B0(unsigned char *a1, uint8_t *a2) {\n uint8_t *v2;\n unsigned long long result;\n int v5;\n int v6;\n long long v7;\n long long v8;\n int v9;\n int v10;\n long long v11;\n unsigned int v12;\n long long v13;\n long long v14;\n v2 = a2;\n result = *a1;\n if (!(uint8_t)result) goto LABEL_17;\n v5 = 0;\n v6 = 0;\n v7 = 0LL;\n do {\n while ((uint8_t)result != 32) {\n ++v6;\n LABEL_4:\n result = a1[++v7];\n if (!(uint8_t)result) goto LABEL_8;\n }\n if (v6 <= 1) goto LABEL_7;\n if (v6 <= 3) goto LABEL_23;\n if ((v6 & 1) != 0) {\n v10 = 2;\n while (1) {\n ++v10;\n if (v10 * v10 > v6) break;\n if (!(v6 % v10)) goto LABEL_7;\n }\n LABEL_23:\n if (v5 > 0) {\n v11 = v5++;\n v2[v11] = 32;\n }\n v12 = v6;\n v13 = v5;\n v5 += v6;\n v14 = v7 - v6;\n v6 = 0;\n memcpy(&v2[v13], &a1[v14], v12);\n goto LABEL_4;\n }\n LABEL_7:\n ++v7;\n v6 = 0;\n result = a1[v7];\n } while ((uint8_t)result);\nLABEL_8:\n v8 = v5;\n a2 = &v2[v5];\n if (v6 > 1) {\n if (v6 <= 3) goto LABEL_14;\n if ((v6 & 1) != 0) {\n v9 = 2;\n while (1) {\n ++v9;\n if (v9 * v9 > v6) break;\n result = (unsigned int)(v6 / v9);\n if (!(v6 % v9)) goto LABEL_17;\n }\n LABEL_14:\n if (v5 > 0) {\n *a2 = 32;\n v8 = ++v5;\n }\n result = (unsigned long long)memcpy(&v2[v8], &a1[v7 - v6], v6);\n a2 = &v2[v5 + v6];\n }\n }\nLABEL_17:\n *a2 = 0;\n return result;\n}", + "ida_pseudo_norm": "unsigned long long func0(unsigned char *a1, uint8_t *a2) {\n uint8_t *v2;\n unsigned long long result;\n int v5;\n int v6;\n long long v7;\n long long v8;\n int v9;\n int v10;\n long long v11;\n unsigned int v12;\n long long v13;\n long long v14;\n v2 = a2;\n result = *a1;\n if (!(uint8_t)result) goto LABEL_17;\n v5 = 0;\n v6 = 0;\n v7 = 0LL;\n do {\n while ((uint8_t)result != 32) {\n ++v6;\n LABEL_4:\n result = a1[++v7];\n if (!(uint8_t)result) goto LABEL_8;\n }\n if (v6 <= 1) goto LABEL_7;\n if (v6 <= 3) goto LABEL_23;\n if ((v6 & 1) != 0) {\n v10 = 2;\n while (1) {\n ++v10;\n if (v10 * v10 > v6) break;\n if (!(v6 % v10)) goto LABEL_7;\n }\n LABEL_23:\n if (v5 > 0) {\n v11 = v5++;\n v2[v11] = 32;\n }\n v12 = v6;\n v13 = v5;\n v5 += v6;\n v14 = v7 - v6;\n v6 = 0;\n memcpy(&v2[v13], &a1[v14], v12);\n goto LABEL_4;\n }\n LABEL_7:\n ++v7;\n v6 = 0;\n result = a1[v7];\n } while ((uint8_t)result);\nLABEL_8:\n v8 = v5;\n a2 = &v2[v5];\n if (v6 > 1) {\n if (v6 <= 3) goto LABEL_14;\n if ((v6 & 1) != 0) {\n v9 = 2;\n while (1) {\n ++v9;\n if (v9 * v9 > v6) break;\n result = (unsigned int)(v6 / v9);\n if (!(v6 % v9)) goto LABEL_17;\n }\n LABEL_14:\n if (v5 > 0) {\n *a2 = 32;\n v8 = ++v5;\n }\n result = (unsigned long long)memcpy(&v2[v8], &a1[v7 - v6], v6);\n a2 = &v2[v5 + v6];\n }\n }\nLABEL_17:\n *a2 = 0;\n return result;\n}" + }, + { + "index": "HumanEval-C-144", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(const char* x, const char* n) {\n int a, b, c, d, i, j;\n char num[101], den[101];\n for (i = 0; x[i] != '/'; i++) {\n num[i] = x[i];\n }\n num[i] = '\\0';\n a = atoi(num);\n for (j = 0, i = i + 1; x[i] != '\\0'; i++, j++) {\n den[j] = x[i];\n }\n den[j] = '\\0';\n b = atoi(den);\n for (i = 0; n[i] != '/'; i++) {\n num[i] = n[i];\n }\n num[i] = '\\0';\n c = atoi(num);\n for (j = 0, i = i + 1; n[i] != '\\0'; i++, j++) {\n den[j] = n[i];\n }\n den[j] = '\\0';\n d = atoi(den);\n if ((a * c) % (b * d) == 0) return 1;\n return 0;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"1/5\", \"5/1\") == 1);\n assert(func0(\"1/6\", \"2/1\") == 0);\n assert(func0(\"5/1\", \"3/1\") == 1);\n assert(func0(\"7/10\", \"10/2\") == 0);\n assert(func0(\"2/10\", \"50/10\") == 1);\n assert(func0(\"7/2\", \"4/2\") == 1);\n assert(func0(\"11/6\", \"6/1\") == 1);\n assert(func0(\"2/3\", \"5/2\") == 0);\n assert(func0(\"5/2\", \"3/5\") == 0);\n assert(func0(\"2/4\", \"8/4\") == 1);\n assert(func0(\"2/4\", \"4/2\") == 1);\n assert(func0(\"1/5\", \"5/1\") == 1);\n assert(func0(\"1/5\", \"1/5\") == 0);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 110h\nmov [rbp+var_108], rdi\nmov [rbp+var_110], rsi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_F8], 0\njmp short loc_11ED\nloc_11C1:\nmov eax, [rbp+var_F8]\nmovsxd rdx, eax\nmov rax, [rbp+var_108]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_F8]\ncdqe\nmov [rbp+rax+nptr], dl\nadd [rbp+var_F8], 1\nloc_11ED:\nmov eax, [rbp+var_F8]\nmovsxd rdx, eax\nmov rax, [rbp+var_108]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 2Fh ; '/'\njnz short loc_11C1\nmov eax, [rbp+var_F8]\ncdqe\nmov [rbp+rax+nptr], 0\nlea rax, [rbp+nptr]\nmov rdi, rax; nptr\ncall _atoi\nmov [rbp+var_F0], eax\nmov [rbp+var_F4], 0\nadd [rbp+var_F8], 1\njmp short loc_126F\nloc_123F:\nmov eax, [rbp+var_F8]\nmovsxd rdx, eax\nmov rax, [rbp+var_108]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_F4]\ncdqe\nmov [rbp+rax+var_70], dl\nadd [rbp+var_F8], 1\nadd [rbp+var_F4], 1\nloc_126F:\nmov eax, [rbp+var_F8]\nmovsxd rdx, eax\nmov rax, [rbp+var_108]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_123F\nmov eax, [rbp+var_F4]\ncdqe\nmov [rbp+rax+var_70], 0\nlea rax, [rbp+var_70]\nmov rdi, rax; nptr\ncall _atoi\nmov [rbp+var_EC], eax\nmov [rbp+var_F8], 0\njmp short loc_12E0\nloc_12B4:\nmov eax, [rbp+var_F8]\nmovsxd rdx, eax\nmov rax, [rbp+var_110]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_F8]\ncdqe\nmov [rbp+rax+nptr], dl\nadd [rbp+var_F8], 1\nloc_12E0:\nmov eax, [rbp+var_F8]\nmovsxd rdx, eax\nmov rax, [rbp+var_110]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 2Fh ; '/'\njnz short loc_12B4\nmov eax, [rbp+var_F8]\ncdqe\nmov [rbp+rax+nptr], 0\nlea rax, [rbp+nptr]\nmov rdi, rax; nptr\ncall _atoi\nmov [rbp+var_E8], eax\nmov [rbp+var_F4], 0\nadd [rbp+var_F8], 1\njmp short loc_1362\nloc_1332:\nmov eax, [rbp+var_F8]\nmovsxd rdx, eax\nmov rax, [rbp+var_110]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_F4]\ncdqe\nmov [rbp+rax+var_70], dl\nadd [rbp+var_F8], 1\nadd [rbp+var_F4], 1\nloc_1362:\nmov eax, [rbp+var_F8]\nmovsxd rdx, eax\nmov rax, [rbp+var_110]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1332\nmov eax, [rbp+var_F4]\ncdqe\nmov [rbp+rax+var_70], 0\nlea rax, [rbp+var_70]\nmov rdi, rax; nptr\ncall _atoi\nmov [rbp+var_E4], eax\nmov eax, [rbp+var_F0]\nimul eax, [rbp+var_E8]\nmov edx, [rbp+var_EC]\nmov esi, edx\nimul esi, [rbp+var_E4]\ncdq\nidiv esi\nmov ecx, edx\nmov eax, ecx\ntest eax, eax\njnz short loc_13C9\nmov eax, 1\njmp short loc_13CE\nloc_13C9:\nmov eax, 0\nloc_13CE:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_13E2\ncall ___stack_chk_fail\nlocret_13E2:\nleave\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(__int64 a1, __int64 a2)\n{\n int i; // [rsp+18h] [rbp-F8h]\n int j; // [rsp+18h] [rbp-F8h]\n int k; // [rsp+18h] [rbp-F8h]\n int m; // [rsp+18h] [rbp-F8h]\n int v7; // [rsp+1Ch] [rbp-F4h]\n int v8; // [rsp+1Ch] [rbp-F4h]\n int v9; // [rsp+20h] [rbp-F0h]\n int v10; // [rsp+24h] [rbp-ECh]\n int v11; // [rsp+28h] [rbp-E8h]\n char nptr[112]; // [rsp+30h] [rbp-E0h] BYREF\n char v13[104]; // [rsp+A0h] [rbp-70h] BYREF\n unsigned __int64 v14; // [rsp+108h] [rbp-8h]\n\n v14 = __readfsqword(0x28u);\n for ( i = 0; *(_BYTE *)(i + a1) != 47; ++i )\n nptr[i] = *(_BYTE *)(i + a1);\n nptr[i] = 0;\n v9 = atoi(nptr);\n v7 = 0;\n for ( j = i + 1; *(_BYTE *)(j + a1); ++j )\n v13[v7++] = *(_BYTE *)(j + a1);\n v13[v7] = 0;\n v10 = atoi(v13);\n for ( k = 0; *(_BYTE *)(k + a2) != 47; ++k )\n nptr[k] = *(_BYTE *)(k + a2);\n nptr[k] = 0;\n v11 = atoi(nptr);\n v8 = 0;\n for ( m = k + 1; *(_BYTE *)(m + a2); ++m )\n v13[v8++] = *(_BYTE *)(m + a2);\n v13[v8] = 0;\n return v11 * v9 % (atoi(v13) * v10) == 0;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 110h\nmov [rbp+var_108], rdi\nmov [rbp+var_110], rsi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_F8], 0\njmp short loc_11ED\nloc_11C1:\nmov eax, [rbp+var_F8]\nmovsxd rdx, eax\nmov rax, [rbp+var_108]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_F8]\ncdqe\nmov [rbp+rax+nptr], dl\nadd [rbp+var_F8], 1\nloc_11ED:\nmov eax, [rbp+var_F8]\nmovsxd rdx, eax\nmov rax, [rbp+var_108]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 2Fh ; '/'\njnz short loc_11C1\nmov eax, [rbp+var_F8]\ncdqe\nmov [rbp+rax+nptr], 0\nlea rax, [rbp+nptr]\nmov rdi, rax; nptr\ncall _atoi\nmov [rbp+var_F0], eax\nmov [rbp+var_F4], 0\nadd [rbp+var_F8], 1\njmp short loc_126F\nloc_123F:\nmov eax, [rbp+var_F8]\nmovsxd rdx, eax\nmov rax, [rbp+var_108]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_F4]\ncdqe\nmov [rbp+rax+var_70], dl\nadd [rbp+var_F8], 1\nadd [rbp+var_F4], 1\nloc_126F:\nmov eax, [rbp+var_F8]\nmovsxd rdx, eax\nmov rax, [rbp+var_108]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_123F\nmov eax, [rbp+var_F4]\ncdqe\nmov [rbp+rax+var_70], 0\nlea rax, [rbp+var_70]\nmov rdi, rax; nptr\ncall _atoi\nmov [rbp+var_EC], eax\nmov [rbp+var_F8], 0\njmp short loc_12E0\nloc_12B4:\nmov eax, [rbp+var_F8]\nmovsxd rdx, eax\nmov rax, [rbp+var_110]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_F8]\ncdqe\nmov [rbp+rax+nptr], dl\nadd [rbp+var_F8], 1\nloc_12E0:\nmov eax, [rbp+var_F8]\nmovsxd rdx, eax\nmov rax, [rbp+var_110]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 2Fh ; '/'\njnz short loc_12B4\nmov eax, [rbp+var_F8]\ncdqe\nmov [rbp+rax+nptr], 0\nlea rax, [rbp+nptr]\nmov rdi, rax; nptr\ncall _atoi\nmov [rbp+var_E8], eax\nmov [rbp+var_F4], 0\nadd [rbp+var_F8], 1\njmp short loc_1362\nloc_1332:\nmov eax, [rbp+var_F8]\nmovsxd rdx, eax\nmov rax, [rbp+var_110]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_F4]\ncdqe\nmov [rbp+rax+var_70], dl\nadd [rbp+var_F8], 1\nadd [rbp+var_F4], 1\nloc_1362:\nmov eax, [rbp+var_F8]\nmovsxd rdx, eax\nmov rax, [rbp+var_110]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1332\nmov eax, [rbp+var_F4]\ncdqe\nmov [rbp+rax+var_70], 0\nlea rax, [rbp+var_70]\nmov rdi, rax; nptr\ncall _atoi\nmov [rbp+var_E4], eax\nmov eax, [rbp+var_F0]\nimul eax, [rbp+var_E8]\nmov edx, [rbp+var_EC]\nmov esi, edx\nimul esi, [rbp+var_E4]\ncdq\nidiv esi\nmov ecx, edx\nmov eax, ecx\ntest eax, eax\njnz short loc_13C9\nmov eax, 1\njmp short loc_13CE\nloc_13C9:\nmov eax, 0\nloc_13CE:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_13E2\ncall ___stack_chk_fail\nlocret_13E2:\nleave\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1189(__int64 a1, __int64 a2)\n{\n int i; // [rsp+18h] [rbp-F8h]\n int j; // [rsp+18h] [rbp-F8h]\n int k; // [rsp+18h] [rbp-F8h]\n int m; // [rsp+18h] [rbp-F8h]\n int v7; // [rsp+1Ch] [rbp-F4h]\n int v8; // [rsp+1Ch] [rbp-F4h]\n int v9; // [rsp+20h] [rbp-F0h]\n int v10; // [rsp+24h] [rbp-ECh]\n int v11; // [rsp+28h] [rbp-E8h]\n char nptr[112]; // [rsp+30h] [rbp-E0h] BYREF\n char v13[104]; // [rsp+A0h] [rbp-70h] BYREF\n unsigned __int64 v14; // [rsp+108h] [rbp-8h]\n\n v14 = __readfsqword(0x28u);\n for ( i = 0; *(_BYTE *)(i + a1) != 47; ++i )\n nptr[i] = *(_BYTE *)(i + a1);\n nptr[i] = 0;\n v9 = atoi(nptr);\n v7 = 0;\n for ( j = i + 1; *(_BYTE *)(j + a1); ++j )\n v13[v7++] = *(_BYTE *)(j + a1);\n v13[v7] = 0;\n v10 = atoi(v13);\n for ( k = 0; *(_BYTE *)(k + a2) != 47; ++k )\n nptr[k] = *(_BYTE *)(k + a2);\n nptr[k] = 0;\n v11 = atoi(nptr);\n v8 = 0;\n for ( m = k + 1; *(_BYTE *)(m + a2); ++m )\n v13[v8++] = *(_BYTE *)(m + a2);\n v13[v8] = 0;\n return v11 * v9 % (atoi(v13) * v10) == 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1189(long long a1, long long a2) {\n int i;\n int j;\n int k;\n int m;\n int v7;\n int v8;\n int v9;\n int v10;\n int v11;\n char nptr[112];\n char v13[104];\n unsigned long long v14;\n v14 = __readfsqword(40u);\n for (i = 0; *(uint8_t *)(i + a1) != 47; ++i) nptr[i] = *(uint8_t *)(i + a1);\n nptr[i] = 0;\n v9 = atoi(nptr);\n v7 = 0;\n for (j = i + 1; *(uint8_t *)(j + a1); ++j) v13[v7++] = *(uint8_t *)(j + a1);\n v13[v7] = 0;\n v10 = atoi(v13);\n for (k = 0; *(uint8_t *)(k + a2) != 47; ++k) nptr[k] = *(uint8_t *)(k + a2);\n nptr[k] = 0;\n v11 = atoi(nptr);\n v8 = 0;\n for (m = k + 1; *(uint8_t *)(m + a2); ++m) v13[v8++] = *(uint8_t *)(m + a2);\n v13[v8] = 0;\n return v11 * v9 % (atoi(v13) * v10) == 0;\n}", + "ida_pseudo_norm": "uint8_t func0(long long a1, long long a2) {\n int i;\n int j;\n int k;\n int m;\n int v7;\n int v8;\n int v9;\n int v10;\n int v11;\n char nptr[112];\n char v13[104];\n unsigned long long v14;\n v14 = __readfsqword(40u);\n for (i = 0; *(uint8_t *)(i + a1) != 47; ++i) nptr[i] = *(uint8_t *)(i + a1);\n nptr[i] = 0;\n v9 = atoi(nptr);\n v7 = 0;\n for (j = i + 1; *(uint8_t *)(j + a1); ++j) v13[v7++] = *(uint8_t *)(j + a1);\n v13[v7] = 0;\n v10 = atoi(v13);\n for (k = 0; *(uint8_t *)(k + a2) != 47; ++k) nptr[k] = *(uint8_t *)(k + a2);\n nptr[k] = 0;\n v11 = atoi(nptr);\n v8 = 0;\n for (m = k + 1; *(uint8_t *)(m + a2); ++m) v13[v8++] = *(uint8_t *)(m + a2);\n v13[v8] = 0;\n return v11 * v9 % (atoi(v13) * v10) == 0;\n}" + }, + { + "index": "HumanEval-C-144", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(const char* x, const char* n) {\n int a, b, c, d, i, j;\n char num[101], den[101];\n for (i = 0; x[i] != '/'; i++) {\n num[i] = x[i];\n }\n num[i] = '\\0';\n a = atoi(num);\n for (j = 0, i = i + 1; x[i] != '\\0'; i++, j++) {\n den[j] = x[i];\n }\n den[j] = '\\0';\n b = atoi(den);\n for (i = 0; n[i] != '/'; i++) {\n num[i] = n[i];\n }\n num[i] = '\\0';\n c = atoi(num);\n for (j = 0, i = i + 1; n[i] != '\\0'; i++, j++) {\n den[j] = n[i];\n }\n den[j] = '\\0';\n d = atoi(den);\n if ((a * c) % (b * d) == 0) return 1;\n return 0;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"1/5\", \"5/1\") == 1);\n assert(func0(\"1/6\", \"2/1\") == 0);\n assert(func0(\"5/1\", \"3/1\") == 1);\n assert(func0(\"7/10\", \"10/2\") == 0);\n assert(func0(\"2/10\", \"50/10\") == 1);\n assert(func0(\"7/2\", \"4/2\") == 1);\n assert(func0(\"11/6\", \"6/1\") == 1);\n assert(func0(\"2/3\", \"5/2\") == 0);\n assert(func0(\"5/2\", \"3/5\") == 0);\n assert(func0(\"2/4\", \"8/4\") == 1);\n assert(func0(\"2/4\", \"4/2\") == 1);\n assert(func0(\"1/5\", \"5/1\") == 1);\n assert(func0(\"1/5\", \"1/5\") == 0);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 0E0h\nmov rbp, rdi\nmov rbx, rsi\nmov rax, fs:28h\nmov [rsp+108h+var_30], rax\nxor eax, eax\nmovzx edx, byte ptr [rdi]\ncmp dl, 2Fh ; '/'\njz loc_1320\nmov eax, 1\nlea rcx, [rsp+108h+var_109]\nloc_11CB:\nmov [rcx+rax], dl\nmov r13, rax\nadd rax, 1\nmovzx edx, byte ptr [rbp+rax-1]\ncmp dl, 2Fh ; '/'\njnz short loc_11CB\nloc_11DF:\nmovsxd rax, r13d\nmov [rsp+rax+108h+var_108], 0\nmov rdi, rsp; nptr\nmov edx, 0Ah; base\nmov esi, 0; endptr\ncall _strtol\nmov r12, rax\nlea eax, [r13+1]\ncdqe\nmovzx eax, byte ptr [rbp+rax+0]\ntest al, al\njz loc_132B\nmov edx, 1\nlea rsi, [rsp+108h+var_99]\nmovsxd r13, r13d\nadd rbp, r13\nloc_121E:\nmov [rsi+rdx], al\nmov rcx, rdx\nadd rdx, 1\nmovzx eax, byte ptr [rbp+rdx+0]\ntest al, al\njnz short loc_121E\nloc_1231:\nmovsxd rcx, ecx\nmov [rsp+rcx+108h+nptr], 0\nlea rdi, [rsp+108h+nptr]; nptr\nmov edx, 0Ah; base\nmov esi, 0; endptr\ncall _strtol\nmov r13, rax\nmovzx eax, byte ptr [rbx]\ncmp al, 2Fh ; '/'\njz loc_1335\nmov edx, 1\nlea rcx, [rsp+108h+var_109]\nloc_1265:\nmov [rcx+rdx], al\nmov rbp, rdx\nadd rdx, 1\nmovzx eax, byte ptr [rbx+rdx-1]\ncmp al, 2Fh ; '/'\njnz short loc_1265\nloc_1278:\nmovsxd rax, ebp\nmov [rsp+rax+108h+var_108], 0\nmov rdi, rsp; nptr\nmov edx, 0Ah; base\nmov esi, 0; endptr\ncall _strtol\nmov r14, rax\nlea eax, [rbp+1]\ncdqe\nmovzx eax, byte ptr [rbx+rax]\ntest al, al\njz loc_133F\nmov edx, 1\nlea rsi, [rsp+108h+var_99]\nmovsxd rbp, ebp\nadd rbx, rbp\nloc_12B5:\nmov [rsi+rdx], al\nmov rcx, rdx\nadd rdx, 1\nmovzx eax, byte ptr [rbx+rdx]\ntest al, al\njnz short loc_12B5\nloc_12C7:\nmovsxd rcx, ecx\nmov [rsp+rcx+108h+nptr], 0\nlea rdi, [rsp+108h+nptr]; nptr\nmov edx, 0Ah; base\nmov esi, 0; endptr\ncall _strtol\nmov rdx, rax\nmov eax, r14d\nimul eax, r12d\nimul r13d, edx\ncdq\nidiv r13d\ntest edx, edx\nsetz al\nmovzx eax, al\nmov rdx, [rsp+108h+var_30]\nsub rdx, fs:28h\njnz short loc_1346\nadd rsp, 0E0h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1320:\nmov r13d, 0\njmp loc_11DF\nloc_132B:\nmov ecx, 0\njmp loc_1231\nloc_1335:\nmov ebp, 0\njmp loc_1278\nloc_133F:\nmov ecx, 0\njmp short loc_12C7\nloc_1346:\ncall ___stack_chk_fail", + "ida_pseudo": "_BOOL8 __fastcall func0(char *a1, char *a2)\n{\n char v2; // dl\n __int64 v3; // rax\n int v4; // r13d\n int v5; // r12d\n char v6; // al\n __int64 v7; // rdx\n int v8; // ecx\n int v9; // r13d\n char v10; // al\n __int64 v11; // rdx\n int v12; // ebp\n int v13; // r14d\n char v14; // al\n __int64 v15; // rdx\n int v16; // ecx\n char v19[112]; // [rsp+2h] [rbp-108h] BYREF\n char nptr[104]; // [rsp+72h] [rbp-98h] BYREF\n unsigned __int64 v21; // [rsp+DAh] [rbp-30h]\n\n v21 = __readfsqword(0x28u);\n v2 = *a1;\n if ( *a1 == 47 )\n {\n v4 = 0;\n }\n else\n {\n v3 = 1LL;\n do\n {\n v19[v3 - 1] = v2;\n v4 = v3++;\n v2 = a1[v3 - 1];\n }\n while ( v2 != 47 );\n }\n v19[v4] = 0;\n v5 = strtol(v19, 0LL, 10);\n v6 = a1[v4 + 1];\n if ( v6 )\n {\n v7 = 1LL;\n do\n {\n v19[v7 + 111] = v6;\n v8 = v7++;\n v6 = a1[v4 + v7];\n }\n while ( v6 );\n }\n else\n {\n v8 = 0;\n }\n nptr[v8] = 0;\n v9 = strtol(nptr, 0LL, 10);\n v10 = *a2;\n if ( *a2 == 47 )\n {\n v12 = 0;\n }\n else\n {\n v11 = 1LL;\n do\n {\n v19[v11 - 1] = v10;\n v12 = v11++;\n v10 = a2[v11 - 1];\n }\n while ( v10 != 47 );\n }\n v19[v12] = 0;\n v13 = strtol(v19, 0LL, 10);\n v14 = a2[v12 + 1];\n if ( v14 )\n {\n v15 = 1LL;\n do\n {\n v19[v15 + 111] = v14;\n v16 = v15++;\n v14 = a2[v12 + v15];\n }\n while ( v14 );\n }\n else\n {\n v16 = 0;\n }\n nptr[v16] = 0;\n return v5 * v13 % (int)(strtol(nptr, 0LL, 10) * v9) == 0;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 0E0h\nmov rbp, rdi\nmov rbx, rsi\nmov rax, fs:28h\nmov [rsp+108h+var_30], rax\nxor eax, eax\nmovzx edx, byte ptr [rdi]\ncmp dl, 2Fh ; '/'\njz loc_1320\nmov eax, 1\nlea rcx, [rsp+108h+var_109]\nloc_11CB:\nmov [rcx+rax], dl\nmov r13, rax\nadd rax, 1\nmovzx edx, byte ptr [rbp+rax-1]\ncmp dl, 2Fh ; '/'\njnz short loc_11CB\nloc_11DF:\nmovsxd rax, r13d\nmov [rsp+rax+108h+var_108], 0\nmov rdi, rsp; nptr\nmov edx, 0Ah; base\nmov esi, 0; endptr\ncall _strtol\nmov r12, rax\nlea eax, [r13+1]\ncdqe\nmovzx eax, byte ptr [rbp+rax+0]\ntest al, al\njz loc_132B\nmov edx, 1\nlea rsi, [rsp+108h+var_99]\nmovsxd r13, r13d\nadd rbp, r13\nloc_121E:\nmov [rsi+rdx], al\nmov rcx, rdx\nadd rdx, 1\nmovzx eax, byte ptr [rbp+rdx+0]\ntest al, al\njnz short loc_121E\nloc_1231:\nmovsxd rcx, ecx\nmov [rsp+rcx+108h+nptr], 0\nlea rdi, [rsp+108h+nptr]; nptr\nmov edx, 0Ah; base\nmov esi, 0; endptr\ncall _strtol\nmov r13, rax\nmovzx eax, byte ptr [rbx]\ncmp al, 2Fh ; '/'\njz loc_1335\nmov edx, 1\nlea rcx, [rsp+108h+var_109]\nloc_1265:\nmov [rcx+rdx], al\nmov rbp, rdx\nadd rdx, 1\nmovzx eax, byte ptr [rbx+rdx-1]\ncmp al, 2Fh ; '/'\njnz short loc_1265\nloc_1278:\nmovsxd rax, ebp\nmov [rsp+rax+108h+var_108], 0\nmov rdi, rsp; nptr\nmov edx, 0Ah; base\nmov esi, 0; endptr\ncall _strtol\nmov r14, rax\nlea eax, [rbp+1]\ncdqe\nmovzx eax, byte ptr [rbx+rax]\ntest al, al\njz loc_133F\nmov edx, 1\nlea rsi, [rsp+108h+var_99]\nmovsxd rbp, ebp\nadd rbx, rbp\nloc_12B5:\nmov [rsi+rdx], al\nmov rcx, rdx\nadd rdx, 1\nmovzx eax, byte ptr [rbx+rdx]\ntest al, al\njnz short loc_12B5\nloc_12C7:\nmovsxd rcx, ecx\nmov [rsp+rcx+108h+nptr], 0\nlea rdi, [rsp+108h+nptr]; nptr\nmov edx, 0Ah; base\nmov esi, 0; endptr\ncall _strtol\nmov rdx, rax\nmov eax, r14d\nimul eax, r12d\nimul r13d, edx\ncdq\nidiv r13d\ntest edx, edx\nsetz al\nmovzx eax, al\nmov rdx, [rsp+108h+var_30]\nsub rdx, fs:28h\njnz short loc_1346\nadd rsp, 0E0h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1320:\nmov r13d, 0\njmp loc_11DF\nloc_132B:\nmov ecx, 0\njmp loc_1231\nloc_1335:\nmov ebp, 0\njmp loc_1278\nloc_133F:\nmov ecx, 0\njmp short loc_12C7\nloc_1346:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1189(char *a1, char *a2)\n{\n char v2; // dl\n __int64 v3; // rax\n int v4; // r13d\n int v5; // r12d\n char v6; // al\n __int64 v7; // rdx\n int v8; // ecx\n int v9; // r13d\n char v10; // al\n __int64 v11; // rdx\n int v12; // ebp\n int v13; // r14d\n char v14; // al\n __int64 v15; // rdx\n int v16; // ecx\n char v19[112]; // [rsp+2h] [rbp-108h] BYREF\n char nptr[104]; // [rsp+72h] [rbp-98h] BYREF\n unsigned __int64 v21; // [rsp+DAh] [rbp-30h]\n\n v21 = __readfsqword(0x28u);\n v2 = *a1;\n if ( *a1 == 47 )\n {\n v4 = 0;\n }\n else\n {\n v3 = 1LL;\n do\n {\n v19[v3 - 1] = v2;\n v4 = v3++;\n v2 = a1[v3 - 1];\n }\n while ( v2 != 47 );\n }\n v19[v4] = 0;\n v5 = strtol(v19, 0LL, 10);\n v6 = a1[v4 + 1];\n if ( v6 )\n {\n v7 = 1LL;\n do\n {\n v19[v7 + 111] = v6;\n v8 = v7++;\n v6 = a1[v4 + v7];\n }\n while ( v6 );\n }\n else\n {\n v8 = 0;\n }\n nptr[v8] = 0;\n v9 = strtol(nptr, 0LL, 10);\n v10 = *a2;\n if ( *a2 == 47 )\n {\n v12 = 0;\n }\n else\n {\n v11 = 1LL;\n do\n {\n v19[v11 - 1] = v10;\n v12 = v11++;\n v10 = a2[v11 - 1];\n }\n while ( v10 != 47 );\n }\n v19[v12] = 0;\n v13 = strtol(v19, 0LL, 10);\n v14 = a2[v12 + 1];\n if ( v14 )\n {\n v15 = 1LL;\n do\n {\n v19[v15 + 111] = v14;\n v16 = v15++;\n v14 = a2[v12 + v15];\n }\n while ( v14 );\n }\n else\n {\n v16 = 0;\n }\n nptr[v16] = 0;\n return v5 * v13 % (int)(strtol(nptr, 0LL, 10) * v9) == 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1189(char *a1, char *a2) {\n char v2;\n long long v3;\n int v4;\n int v5;\n char v6;\n long long v7;\n int v8;\n int v9;\n char v10;\n long long v11;\n int v12;\n int v13;\n char v14;\n long long v15;\n int v16;\n char v19[112];\n char nptr[104];\n unsigned long long v21;\n v21 = __readfsqword(40u);\n v2 = *a1;\n if (*a1 == 47) {\n v4 = 0;\n } else {\n v3 = 1LL;\n do {\n v19[v3 - 1] = v2;\n v4 = v3++;\n v2 = a1[v3 - 1];\n } while (v2 != 47);\n }\n v19[v4] = 0;\n v5 = strtol(v19, 0LL, 10);\n v6 = a1[v4 + 1];\n if (v6) {\n v7 = 1LL;\n do {\n v19[v7 + 111] = v6;\n v8 = v7++;\n v6 = a1[v4 + v7];\n } while (v6);\n } else {\n v8 = 0;\n }\n nptr[v8] = 0;\n v9 = strtol(nptr, 0LL, 10);\n v10 = *a2;\n if (*a2 == 47) {\n v12 = 0;\n } else {\n v11 = 1LL;\n do {\n v19[v11 - 1] = v10;\n v12 = v11++;\n v10 = a2[v11 - 1];\n } while (v10 != 47);\n }\n v19[v12] = 0;\n v13 = strtol(v19, 0LL, 10);\n v14 = a2[v12 + 1];\n if (v14) {\n v15 = 1LL;\n do {\n v19[v15 + 111] = v14;\n v16 = v15++;\n v14 = a2[v12 + v15];\n } while (v14);\n } else {\n v16 = 0;\n }\n nptr[v16] = 0;\n return v5 * v13 % (int)(strtol(nptr, 0LL, 10) * v9) == 0;\n}", + "ida_pseudo_norm": "uint8_t func0(char *a1, char *a2) {\n char v2;\n long long v3;\n int v4;\n int v5;\n char v6;\n long long v7;\n int v8;\n int v9;\n char v10;\n long long v11;\n int v12;\n int v13;\n char v14;\n long long v15;\n int v16;\n char v19[112];\n char nptr[104];\n unsigned long long v21;\n v21 = __readfsqword(40u);\n v2 = *a1;\n if (*a1 == 47) {\n v4 = 0;\n } else {\n v3 = 1LL;\n do {\n v19[v3 - 1] = v2;\n v4 = v3++;\n v2 = a1[v3 - 1];\n } while (v2 != 47);\n }\n v19[v4] = 0;\n v5 = strtol(v19, 0LL, 10);\n v6 = a1[v4 + 1];\n if (v6) {\n v7 = 1LL;\n do {\n v19[v7 + 111] = v6;\n v8 = v7++;\n v6 = a1[v4 + v7];\n } while (v6);\n } else {\n v8 = 0;\n }\n nptr[v8] = 0;\n v9 = strtol(nptr, 0LL, 10);\n v10 = *a2;\n if (*a2 == 47) {\n v12 = 0;\n } else {\n v11 = 1LL;\n do {\n v19[v11 - 1] = v10;\n v12 = v11++;\n v10 = a2[v11 - 1];\n } while (v10 != 47);\n }\n v19[v12] = 0;\n v13 = strtol(v19, 0LL, 10);\n v14 = a2[v12 + 1];\n if (v14) {\n v15 = 1LL;\n do {\n v19[v15 + 111] = v14;\n v16 = v15++;\n v14 = a2[v12 + v15];\n } while (v14);\n } else {\n v16 = 0;\n }\n nptr[v16] = 0;\n return v5 * v13 % (int)(strtol(nptr, 0LL, 10) * v9) == 0;\n}" + }, + { + "index": "HumanEval-C-144", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(const char* x, const char* n) {\n int a, b, c, d, i, j;\n char num[101], den[101];\n for (i = 0; x[i] != '/'; i++) {\n num[i] = x[i];\n }\n num[i] = '\\0';\n a = atoi(num);\n for (j = 0, i = i + 1; x[i] != '\\0'; i++, j++) {\n den[j] = x[i];\n }\n den[j] = '\\0';\n b = atoi(den);\n for (i = 0; n[i] != '/'; i++) {\n num[i] = n[i];\n }\n num[i] = '\\0';\n c = atoi(num);\n for (j = 0, i = i + 1; n[i] != '\\0'; i++, j++) {\n den[j] = n[i];\n }\n den[j] = '\\0';\n d = atoi(den);\n if ((a * c) % (b * d) == 0) return 1;\n return 0;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"1/5\", \"5/1\") == 1);\n assert(func0(\"1/6\", \"2/1\") == 0);\n assert(func0(\"5/1\", \"3/1\") == 1);\n assert(func0(\"7/10\", \"10/2\") == 0);\n assert(func0(\"2/10\", \"50/10\") == 1);\n assert(func0(\"7/2\", \"4/2\") == 1);\n assert(func0(\"11/6\", \"6/1\") == 1);\n assert(func0(\"2/3\", \"5/2\") == 0);\n assert(func0(\"5/2\", \"3/5\") == 0);\n assert(func0(\"2/4\", \"8/4\") == 1);\n assert(func0(\"2/4\", \"4/2\") == 1);\n assert(func0(\"1/5\", \"5/1\") == 1);\n assert(func0(\"1/5\", \"1/5\") == 0);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14, rsi\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 0F8h\nmovzx edx, byte ptr [rdi]\nmov rax, fs:28h\nmov [rsp+128h+var_40], rax\nxor eax, eax\ncmp dl, 2Fh ; '/'\njz loc_1650\nmov eax, 1\nlea rcx, [rsp+128h+var_119]\nnop dword ptr [rax+00h]\nloc_14D8:\nmov [rcx+rax], dl\nmov rsi, rax\nadd rax, 1\nmovzx edx, byte ptr [rbx+rax-1]\ncmp dl, 2Fh ; '/'\njnz short loc_14D8\nlea r12d, [rsi+1]\nmovsxd rax, esi\nmovsxd r15, r12d\nloc_14F6:\nlea r13, [rsp+128h+nptr]\nmov edx, 0Ah; base\nxor esi, esi; endptr\nmov [rsp+rax+128h+nptr], 0\nmov rdi, r13; nptr\ncall _strtol\nmov rbp, rax\nmovzx eax, byte ptr [rbx+r15]\ntest al, al\njz loc_1668\nmovsxd r12, r12d\nmov edx, 1\nlea rsi, [rsp+128h+var_A9]\nadd rbx, r12\nnop\nloc_1530:\nmov [rsi+rdx], al\nmov rcx, rdx\nadd rdx, 1\nmovzx eax, byte ptr [rbx+rdx-1]\ntest al, al\njnz short loc_1530\nloc_1543:\nlea r12, [rsp+128h+var_A8]\nmovsxd rcx, ecx\nmov edx, 0Ah; base\nxor esi, esi; endptr\nmov rdi, r12; nptr\nmov [rsp+rcx+128h+var_A8], 0\ncall _strtol\nmov rbx, rax\nmovzx eax, byte ptr [r14]\ncmp al, 2Fh ; '/'\njz loc_1670\nmov edx, 1\nlea rcx, [rsp+128h+var_119]\nxchg ax, ax\nloc_1580:\nmov [rcx+rdx], al\nmov rsi, rdx\nadd rdx, 1\nmovzx eax, byte ptr [r14+rdx-1]\ncmp al, 2Fh ; '/'\njnz short loc_1580\nlea r8d, [rsi+1]\nmovsxd rax, esi\nmovsxd r15, r8d\nloc_159E:\nmov rdi, r13; nptr\nmov edx, 0Ah; base\nxor esi, esi; endptr\nmov [rsp+0Ch], r8d\nmov [rsp+rax+128h+nptr], 0\ncall _strtol\nmovzx ecx, byte ptr [r14+r15]\nmov r13, rax\ntest cl, cl\njz loc_1688\nmovsxd r8, dword ptr [rsp+0Ch]\nmov edx, 1\nlea rsi, [rsp+128h+var_A9]\nadd r14, r8\nnop dword ptr [rax+00000000h]\nloc_15E0:\nmov [rsi+rdx], cl\nmov rdi, rdx\nadd rdx, 1\nmovzx ecx, byte ptr [r14+rdx-1]\ntest cl, cl\njnz short loc_15E0\nloc_15F4:\nmovsxd rdi, edi\nmov edx, 0Ah; base\nxor esi, esi; endptr\nmov [rsp+rdi+128h+var_A8], 0\nmov rdi, r12; nptr\ncall _strtol\nmov rdx, rax\nmov eax, r13d\nimul eax, ebp\nimul ebx, edx\ncdq\nidiv ebx\nxor eax, eax\ntest edx, edx\nsetz al\nmov rdx, [rsp+128h+var_40]\nsub rdx, fs:28h\njnz short loc_168F\nadd rsp, 0F8h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1650:\nmov r15d, 1\nmov r12d, 1\nxor eax, eax\njmp loc_14F6\nloc_1668:\nxor ecx, ecx\njmp loc_1543\nloc_1670:\nmov r15d, 1\nmov r8d, 1\nxor eax, eax\njmp loc_159E\nloc_1688:\nxor edi, edi\njmp loc_15F4\nloc_168F:\ncall ___stack_chk_fail", + "ida_pseudo": "_BOOL8 __fastcall func0(char *a1, char *a2)\n{\n char v3; // dl\n __int64 v4; // rax\n int v5; // esi\n int v6; // r12d\n __int64 v7; // rax\n __int64 v8; // r15\n int v9; // ebp\n char v10; // al\n __int64 v11; // rdx\n int v12; // ecx\n int v13; // ebx\n char v14; // al\n __int64 v15; // rdx\n int v16; // esi\n int v17; // r8d\n __int64 v18; // rax\n __int64 v19; // r15\n int v20; // eax\n char v21; // cl\n __int64 v22; // rdx\n char *v23; // r14\n int v24; // edi\n int v26; // [rsp+Ch] [rbp-11Ch]\n char nptr[112]; // [rsp+10h] [rbp-118h] BYREF\n char v28[104]; // [rsp+80h] [rbp-A8h] BYREF\n unsigned __int64 v29; // [rsp+E8h] [rbp-40h]\n\n v3 = *a1;\n v29 = __readfsqword(0x28u);\n if ( v3 == 47 )\n {\n v8 = 1LL;\n v6 = 1;\n v7 = 0LL;\n }\n else\n {\n v4 = 1LL;\n do\n {\n nptr[v4 - 1] = v3;\n v5 = v4++;\n v3 = a1[v4 - 1];\n }\n while ( v3 != 47 );\n v6 = v5 + 1;\n v7 = v5;\n v8 = v5 + 1;\n }\n nptr[v7] = 0;\n v9 = strtol(nptr, 0LL, 10);\n v10 = a1[v8];\n if ( v10 )\n {\n v11 = 1LL;\n do\n {\n nptr[v11 + 111] = v10;\n v12 = v11++;\n v10 = a1[v6 - 1 + v11];\n }\n while ( v10 );\n }\n else\n {\n v12 = 0;\n }\n v28[v12] = 0;\n v13 = strtol(v28, 0LL, 10);\n v14 = *a2;\n if ( *a2 == 47 )\n {\n v19 = 1LL;\n v17 = 1;\n v18 = 0LL;\n }\n else\n {\n v15 = 1LL;\n do\n {\n nptr[v15 - 1] = v14;\n v16 = v15++;\n v14 = a2[v15 - 1];\n }\n while ( v14 != 47 );\n v17 = v16 + 1;\n v18 = v16;\n v19 = v16 + 1;\n }\n v26 = v17;\n nptr[v18] = 0;\n v20 = strtol(nptr, 0LL, 10);\n v21 = a2[v19];\n if ( v21 )\n {\n v22 = 1LL;\n v23 = &a2[v26];\n do\n {\n nptr[v22 + 111] = v21;\n v24 = v22++;\n v21 = v23[v22 - 1];\n }\n while ( v21 );\n }\n else\n {\n v24 = 0;\n }\n v28[v24] = 0;\n return v9 * v20 % (int)(strtol(v28, 0LL, 10) * v13) == 0;\n}", + "ida_strip_asm": "sub_1490:\nendbr64\npush r15\npush r14\nmov r14, rsi\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 0F8h\nmovzx edx, byte ptr [rdi]\nmov rax, fs:28h\nmov [rsp+128h+var_40], rax\nxor eax, eax\ncmp dl, 2Fh ; '/'\njz loc_1650\nmov eax, 1\nlea rcx, [rsp+128h+var_119]\nnop dword ptr [rax+00h]\nloc_14D8:\nmov [rcx+rax], dl\nmov rsi, rax\nadd rax, 1\nmovzx edx, byte ptr [rbx+rax-1]\ncmp dl, 2Fh ; '/'\njnz short loc_14D8\nlea r12d, [rsi+1]\nmovsxd rax, esi\nmovsxd r15, r12d\nloc_14F6:\nlea r13, [rsp+128h+nptr]\nmov edx, 0Ah; base\nxor esi, esi; endptr\nmov [rsp+rax+128h+nptr], 0\nmov rdi, r13; nptr\ncall _strtol\nmov rbp, rax\nmovzx eax, byte ptr [rbx+r15]\ntest al, al\njz loc_1668\nmovsxd r12, r12d\nmov edx, 1\nlea rsi, [rsp+128h+var_A9]\nadd rbx, r12\nnop\nloc_1530:\nmov [rsi+rdx], al\nmov rcx, rdx\nadd rdx, 1\nmovzx eax, byte ptr [rbx+rdx-1]\ntest al, al\njnz short loc_1530\nloc_1543:\nlea r12, [rsp+128h+var_A8]\nmovsxd rcx, ecx\nmov edx, 0Ah; base\nxor esi, esi; endptr\nmov rdi, r12; nptr\nmov [rsp+rcx+128h+var_A8], 0\ncall _strtol\nmov rbx, rax\nmovzx eax, byte ptr [r14]\ncmp al, 2Fh ; '/'\njz loc_1670\nmov edx, 1\nlea rcx, [rsp+128h+var_119]\nxchg ax, ax\nloc_1580:\nmov [rcx+rdx], al\nmov rsi, rdx\nadd rdx, 1\nmovzx eax, byte ptr [r14+rdx-1]\ncmp al, 2Fh ; '/'\njnz short loc_1580\nlea r8d, [rsi+1]\nmovsxd rax, esi\nmovsxd r15, r8d\nloc_159E:\nmov rdi, r13; nptr\nmov edx, 0Ah; base\nxor esi, esi; endptr\nmov [rsp+0Ch], r8d\nmov [rsp+rax+128h+nptr], 0\ncall _strtol\nmovzx ecx, byte ptr [r14+r15]\nmov r13, rax\ntest cl, cl\njz loc_1688\nmovsxd r8, dword ptr [rsp+0Ch]\nmov edx, 1\nlea rsi, [rsp+128h+var_A9]\nadd r14, r8\nnop dword ptr [rax+00000000h]\nloc_15E0:\nmov [rsi+rdx], cl\nmov rdi, rdx\nadd rdx, 1\nmovzx ecx, byte ptr [r14+rdx-1]\ntest cl, cl\njnz short loc_15E0\nloc_15F4:\nmovsxd rdi, edi\nmov edx, 0Ah; base\nxor esi, esi; endptr\nmov [rsp+rdi+128h+var_A8], 0\nmov rdi, r12; nptr\ncall _strtol\nmov rdx, rax\nmov eax, r13d\nimul eax, ebp\nimul ebx, edx\ncdq\nidiv ebx\nxor eax, eax\ntest edx, edx\nsetz al\nmov rdx, [rsp+128h+var_40]\nsub rdx, fs:28h\njnz short loc_168F\nadd rsp, 0F8h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1650:\nmov r15d, 1\nmov r12d, 1\nxor eax, eax\njmp loc_14F6\nloc_1668:\nxor ecx, ecx\njmp loc_1543\nloc_1670:\nmov r15d, 1\nmov r8d, 1\nxor eax, eax\njmp loc_159E\nloc_1688:\nxor edi, edi\njmp loc_15F4\nloc_168F:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1490(char *a1, char *a2)\n{\n char v3; // dl\n __int64 v4; // rax\n int v5; // esi\n int v6; // r12d\n __int64 v7; // rax\n __int64 v8; // r15\n int v9; // ebp\n char v10; // al\n __int64 v11; // rdx\n int v12; // ecx\n int v13; // ebx\n char v14; // al\n __int64 v15; // rdx\n int v16; // esi\n int v17; // r8d\n __int64 v18; // rax\n __int64 v19; // r15\n int v20; // eax\n char v21; // cl\n __int64 v22; // rdx\n char *v23; // r14\n int v24; // edi\n int v26; // [rsp+Ch] [rbp-11Ch]\n char nptr[112]; // [rsp+10h] [rbp-118h] BYREF\n char v28[104]; // [rsp+80h] [rbp-A8h] BYREF\n unsigned __int64 v29; // [rsp+E8h] [rbp-40h]\n\n v3 = *a1;\n v29 = __readfsqword(0x28u);\n if ( v3 == 47 )\n {\n v8 = 1LL;\n v6 = 1;\n v7 = 0LL;\n }\n else\n {\n v4 = 1LL;\n do\n {\n nptr[v4 - 1] = v3;\n v5 = v4++;\n v3 = a1[v4 - 1];\n }\n while ( v3 != 47 );\n v6 = v5 + 1;\n v7 = v5;\n v8 = v5 + 1;\n }\n nptr[v7] = 0;\n v9 = strtol(nptr, 0LL, 10);\n v10 = a1[v8];\n if ( v10 )\n {\n v11 = 1LL;\n do\n {\n nptr[v11 + 111] = v10;\n v12 = v11++;\n v10 = a1[v6 - 1 + v11];\n }\n while ( v10 );\n }\n else\n {\n v12 = 0;\n }\n v28[v12] = 0;\n v13 = strtol(v28, 0LL, 10);\n v14 = *a2;\n if ( *a2 == 47 )\n {\n v19 = 1LL;\n v17 = 1;\n v18 = 0LL;\n }\n else\n {\n v15 = 1LL;\n do\n {\n nptr[v15 - 1] = v14;\n v16 = v15++;\n v14 = a2[v15 - 1];\n }\n while ( v14 != 47 );\n v17 = v16 + 1;\n v18 = v16;\n v19 = v16 + 1;\n }\n v26 = v17;\n nptr[v18] = 0;\n v20 = strtol(nptr, 0LL, 10);\n v21 = a2[v19];\n if ( v21 )\n {\n v22 = 1LL;\n v23 = &a2[v26];\n do\n {\n nptr[v22 + 111] = v21;\n v24 = v22++;\n v21 = v23[v22 - 1];\n }\n while ( v21 );\n }\n else\n {\n v24 = 0;\n }\n v28[v24] = 0;\n return v9 * v20 % (int)(strtol(v28, 0LL, 10) * v13) == 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1490(char *a1, char *a2) {\n char v3;\n long long v4;\n int v5;\n int v6;\n long long v7;\n long long v8;\n int v9;\n char v10;\n long long v11;\n int v12;\n int v13;\n char v14;\n long long v15;\n int v16;\n int v17;\n long long v18;\n long long v19;\n int v20;\n char v21;\n long long v22;\n char *v23;\n int v24;\n int v26;\n char nptr[112];\n char v28[104];\n unsigned long long v29;\n v3 = *a1;\n v29 = __readfsqword(40u);\n if (v3 == 47) {\n v8 = 1LL;\n v6 = 1;\n v7 = 0LL;\n } else {\n v4 = 1LL;\n do {\n nptr[v4 - 1] = v3;\n v5 = v4++;\n v3 = a1[v4 - 1];\n } while (v3 != 47);\n v6 = v5 + 1;\n v7 = v5;\n v8 = v5 + 1;\n }\n nptr[v7] = 0;\n v9 = strtol(nptr, 0LL, 10);\n v10 = a1[v8];\n if (v10) {\n v11 = 1LL;\n do {\n nptr[v11 + 111] = v10;\n v12 = v11++;\n v10 = a1[v6 - 1 + v11];\n } while (v10);\n } else {\n v12 = 0;\n }\n v28[v12] = 0;\n v13 = strtol(v28, 0LL, 10);\n v14 = *a2;\n if (*a2 == 47) {\n v19 = 1LL;\n v17 = 1;\n v18 = 0LL;\n } else {\n v15 = 1LL;\n do {\n nptr[v15 - 1] = v14;\n v16 = v15++;\n v14 = a2[v15 - 1];\n } while (v14 != 47);\n v17 = v16 + 1;\n v18 = v16;\n v19 = v16 + 1;\n }\n v26 = v17;\n nptr[v18] = 0;\n v20 = strtol(nptr, 0LL, 10);\n v21 = a2[v19];\n if (v21) {\n v22 = 1LL;\n v23 = &a2[v26];\n do {\n nptr[v22 + 111] = v21;\n v24 = v22++;\n v21 = v23[v22 - 1];\n } while (v21);\n } else {\n v24 = 0;\n }\n v28[v24] = 0;\n return v9 * v20 % (int)(strtol(v28, 0LL, 10) * v13) == 0;\n}", + "ida_pseudo_norm": "uint8_t func0(char *a1, char *a2) {\n char v3;\n long long v4;\n int v5;\n int v6;\n long long v7;\n long long v8;\n int v9;\n char v10;\n long long v11;\n int v12;\n int v13;\n char v14;\n long long v15;\n int v16;\n int v17;\n long long v18;\n long long v19;\n int v20;\n char v21;\n long long v22;\n char *v23;\n int v24;\n int v26;\n char nptr[112];\n char v28[104];\n unsigned long long v29;\n v3 = *a1;\n v29 = __readfsqword(40u);\n if (v3 == 47) {\n v8 = 1LL;\n v6 = 1;\n v7 = 0LL;\n } else {\n v4 = 1LL;\n do {\n nptr[v4 - 1] = v3;\n v5 = v4++;\n v3 = a1[v4 - 1];\n } while (v3 != 47);\n v6 = v5 + 1;\n v7 = v5;\n v8 = v5 + 1;\n }\n nptr[v7] = 0;\n v9 = strtol(nptr, 0LL, 10);\n v10 = a1[v8];\n if (v10) {\n v11 = 1LL;\n do {\n nptr[v11 + 111] = v10;\n v12 = v11++;\n v10 = a1[v6 - 1 + v11];\n } while (v10);\n } else {\n v12 = 0;\n }\n v28[v12] = 0;\n v13 = strtol(v28, 0LL, 10);\n v14 = *a2;\n if (*a2 == 47) {\n v19 = 1LL;\n v17 = 1;\n v18 = 0LL;\n } else {\n v15 = 1LL;\n do {\n nptr[v15 - 1] = v14;\n v16 = v15++;\n v14 = a2[v15 - 1];\n } while (v14 != 47);\n v17 = v16 + 1;\n v18 = v16;\n v19 = v16 + 1;\n }\n v26 = v17;\n nptr[v18] = 0;\n v20 = strtol(nptr, 0LL, 10);\n v21 = a2[v19];\n if (v21) {\n v22 = 1LL;\n v23 = &a2[v26];\n do {\n nptr[v22 + 111] = v21;\n v24 = v22++;\n v21 = v23[v22 - 1];\n } while (v21);\n } else {\n v24 = 0;\n }\n v28[v24] = 0;\n return v9 * v20 % (int)(strtol(v28, 0LL, 10) * v13) == 0;\n}" + }, + { + "index": "HumanEval-C-144", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(const char* x, const char* n) {\n int a, b, c, d, i, j;\n char num[101], den[101];\n for (i = 0; x[i] != '/'; i++) {\n num[i] = x[i];\n }\n num[i] = '\\0';\n a = atoi(num);\n for (j = 0, i = i + 1; x[i] != '\\0'; i++, j++) {\n den[j] = x[i];\n }\n den[j] = '\\0';\n b = atoi(den);\n for (i = 0; n[i] != '/'; i++) {\n num[i] = n[i];\n }\n num[i] = '\\0';\n c = atoi(num);\n for (j = 0, i = i + 1; n[i] != '\\0'; i++, j++) {\n den[j] = n[i];\n }\n den[j] = '\\0';\n d = atoi(den);\n if ((a * c) % (b * d) == 0) return 1;\n return 0;\n}", + "test": "#include \n\nint main() {\n assert(func0(\"1/5\", \"5/1\") == 1);\n assert(func0(\"1/6\", \"2/1\") == 0);\n assert(func0(\"5/1\", \"3/1\") == 1);\n assert(func0(\"7/10\", \"10/2\") == 0);\n assert(func0(\"2/10\", \"50/10\") == 1);\n assert(func0(\"7/2\", \"4/2\") == 1);\n assert(func0(\"11/6\", \"6/1\") == 1);\n assert(func0(\"2/3\", \"5/2\") == 0);\n assert(func0(\"5/2\", \"3/5\") == 0);\n assert(func0(\"2/4\", \"8/4\") == 1);\n assert(func0(\"2/4\", \"4/2\") == 1);\n assert(func0(\"1/5\", \"5/1\") == 1);\n assert(func0(\"1/5\", \"1/5\") == 0);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14, rsi\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 0F8h\nmovzx edx, byte ptr [rdi]\nmov rax, fs:28h\nmov [rsp+128h+var_40], rax\nxor eax, eax\ncmp dl, 2Fh ; '/'\njz loc_1650\nmov eax, 1\nlea rcx, [rsp+128h+var_119]\nnop dword ptr [rax+00h]\nloc_14D8:\nmov [rcx+rax], dl\nmov rsi, rax\nadd rax, 1\nmovzx edx, byte ptr [rbx+rax-1]\ncmp dl, 2Fh ; '/'\njnz short loc_14D8\nlea r12d, [rsi+1]\nmovsxd rax, esi\nmovsxd r15, r12d\nloc_14F6:\nlea r13, [rsp+128h+nptr]\nmov edx, 0Ah; base\nxor esi, esi; endptr\nmov [rsp+rax+128h+nptr], 0\nmov rdi, r13; nptr\ncall _strtol\nmov rbp, rax\nmovzx eax, byte ptr [rbx+r15]\ntest al, al\njz loc_1668\nmovsxd r12, r12d\nmov edx, 1\nlea rsi, [rsp+128h+var_A9]\nadd rbx, r12\nnop\nloc_1530:\nmov [rsi+rdx], al\nmov rcx, rdx\nadd rdx, 1\nmovzx eax, byte ptr [rbx+rdx-1]\ntest al, al\njnz short loc_1530\nloc_1543:\nlea r12, [rsp+128h+var_A8]\nmovsxd rcx, ecx\nmov edx, 0Ah; base\nxor esi, esi; endptr\nmov rdi, r12; nptr\nmov [rsp+rcx+128h+var_A8], 0\ncall _strtol\nmov rbx, rax\nmovzx eax, byte ptr [r14]\ncmp al, 2Fh ; '/'\njz loc_1670\nmov edx, 1\nlea rcx, [rsp+128h+var_119]\nxchg ax, ax\nloc_1580:\nmov [rcx+rdx], al\nmov rsi, rdx\nadd rdx, 1\nmovzx eax, byte ptr [r14+rdx-1]\ncmp al, 2Fh ; '/'\njnz short loc_1580\nlea r8d, [rsi+1]\nmovsxd rax, esi\nmovsxd r15, r8d\nloc_159E:\nmov rdi, r13; nptr\nmov edx, 0Ah; base\nxor esi, esi; endptr\nmov [rsp+0Ch], r8d\nmov [rsp+rax+128h+nptr], 0\ncall _strtol\nmovzx ecx, byte ptr [r14+r15]\nmov r13, rax\ntest cl, cl\njz loc_1688\nmovsxd r8, dword ptr [rsp+0Ch]\nmov edx, 1\nlea rsi, [rsp+128h+var_A9]\nadd r14, r8\nnop dword ptr [rax+00000000h]\nloc_15E0:\nmov [rsi+rdx], cl\nmov rdi, rdx\nadd rdx, 1\nmovzx ecx, byte ptr [r14+rdx-1]\ntest cl, cl\njnz short loc_15E0\nloc_15F4:\nmovsxd rdi, edi\nmov edx, 0Ah; base\nxor esi, esi; endptr\nmov [rsp+rdi+128h+var_A8], 0\nmov rdi, r12; nptr\ncall _strtol\nmov rdx, rax\nmov eax, r13d\nimul eax, ebp\nimul ebx, edx\ncdq\nidiv ebx\nxor eax, eax\ntest edx, edx\nsetz al\nmov rdx, [rsp+128h+var_40]\nsub rdx, fs:28h\njnz short loc_168F\nadd rsp, 0F8h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1650:\nmov r15d, 1\nmov r12d, 1\nxor eax, eax\njmp loc_14F6\nloc_1668:\nxor ecx, ecx\njmp loc_1543\nloc_1670:\nmov r15d, 1\nmov r8d, 1\nxor eax, eax\njmp loc_159E\nloc_1688:\nxor edi, edi\njmp loc_15F4\nloc_168F:\ncall ___stack_chk_fail", + "ida_pseudo": "_BOOL8 __fastcall func0(char *a1, char *a2)\n{\n char v3; // dl\n __int64 v4; // rax\n int v5; // esi\n int v6; // r12d\n __int64 v7; // rax\n __int64 v8; // r15\n int v9; // ebp\n char v10; // al\n __int64 v11; // rdx\n int v12; // ecx\n int v13; // ebx\n char v14; // al\n __int64 v15; // rdx\n int v16; // esi\n int v17; // r8d\n __int64 v18; // rax\n __int64 v19; // r15\n int v20; // eax\n char v21; // cl\n __int64 v22; // rdx\n char *v23; // r14\n int v24; // edi\n int v26; // [rsp+Ch] [rbp-11Ch]\n char nptr[112]; // [rsp+10h] [rbp-118h] BYREF\n char v28[104]; // [rsp+80h] [rbp-A8h] BYREF\n unsigned __int64 v29; // [rsp+E8h] [rbp-40h]\n\n v3 = *a1;\n v29 = __readfsqword(0x28u);\n if ( v3 == 47 )\n {\n v8 = 1LL;\n v6 = 1;\n v7 = 0LL;\n }\n else\n {\n v4 = 1LL;\n do\n {\n nptr[v4 - 1] = v3;\n v5 = v4++;\n v3 = a1[v4 - 1];\n }\n while ( v3 != 47 );\n v6 = v5 + 1;\n v7 = v5;\n v8 = v5 + 1;\n }\n nptr[v7] = 0;\n v9 = strtol(nptr, 0LL, 10);\n v10 = a1[v8];\n if ( v10 )\n {\n v11 = 1LL;\n do\n {\n nptr[v11 + 111] = v10;\n v12 = v11++;\n v10 = a1[v6 - 1 + v11];\n }\n while ( v10 );\n }\n else\n {\n v12 = 0;\n }\n v28[v12] = 0;\n v13 = strtol(v28, 0LL, 10);\n v14 = *a2;\n if ( *a2 == 47 )\n {\n v19 = 1LL;\n v17 = 1;\n v18 = 0LL;\n }\n else\n {\n v15 = 1LL;\n do\n {\n nptr[v15 - 1] = v14;\n v16 = v15++;\n v14 = a2[v15 - 1];\n }\n while ( v14 != 47 );\n v17 = v16 + 1;\n v18 = v16;\n v19 = v16 + 1;\n }\n v26 = v17;\n nptr[v18] = 0;\n v20 = strtol(nptr, 0LL, 10);\n v21 = a2[v19];\n if ( v21 )\n {\n v22 = 1LL;\n v23 = &a2[v26];\n do\n {\n nptr[v22 + 111] = v21;\n v24 = v22++;\n v21 = v23[v22 - 1];\n }\n while ( v21 );\n }\n else\n {\n v24 = 0;\n }\n v28[v24] = 0;\n return v9 * v20 % (int)(strtol(v28, 0LL, 10) * v13) == 0;\n}", + "ida_strip_asm": "sub_1490:\nendbr64\npush r15\npush r14\nmov r14, rsi\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 0F8h\nmovzx edx, byte ptr [rdi]\nmov rax, fs:28h\nmov [rsp+128h+var_40], rax\nxor eax, eax\ncmp dl, 2Fh ; '/'\njz loc_1650\nmov eax, 1\nlea rcx, [rsp+128h+var_119]\nnop dword ptr [rax+00h]\nloc_14D8:\nmov [rcx+rax], dl\nmov rsi, rax\nadd rax, 1\nmovzx edx, byte ptr [rbx+rax-1]\ncmp dl, 2Fh ; '/'\njnz short loc_14D8\nlea r12d, [rsi+1]\nmovsxd rax, esi\nmovsxd r15, r12d\nloc_14F6:\nlea r13, [rsp+128h+nptr]\nmov edx, 0Ah; base\nxor esi, esi; endptr\nmov [rsp+rax+128h+nptr], 0\nmov rdi, r13; nptr\ncall _strtol\nmov rbp, rax\nmovzx eax, byte ptr [rbx+r15]\ntest al, al\njz loc_1668\nmovsxd r12, r12d\nmov edx, 1\nlea rsi, [rsp+128h+var_A9]\nadd rbx, r12\nnop\nloc_1530:\nmov [rsi+rdx], al\nmov rcx, rdx\nadd rdx, 1\nmovzx eax, byte ptr [rbx+rdx-1]\ntest al, al\njnz short loc_1530\nloc_1543:\nlea r12, [rsp+128h+var_A8]\nmovsxd rcx, ecx\nmov edx, 0Ah; base\nxor esi, esi; endptr\nmov rdi, r12; nptr\nmov [rsp+rcx+128h+var_A8], 0\ncall _strtol\nmov rbx, rax\nmovzx eax, byte ptr [r14]\ncmp al, 2Fh ; '/'\njz loc_1670\nmov edx, 1\nlea rcx, [rsp+128h+var_119]\nxchg ax, ax\nloc_1580:\nmov [rcx+rdx], al\nmov rsi, rdx\nadd rdx, 1\nmovzx eax, byte ptr [r14+rdx-1]\ncmp al, 2Fh ; '/'\njnz short loc_1580\nlea r8d, [rsi+1]\nmovsxd rax, esi\nmovsxd r15, r8d\nloc_159E:\nmov rdi, r13; nptr\nmov edx, 0Ah; base\nxor esi, esi; endptr\nmov [rsp+0Ch], r8d\nmov [rsp+rax+128h+nptr], 0\ncall _strtol\nmovzx ecx, byte ptr [r14+r15]\nmov r13, rax\ntest cl, cl\njz loc_1688\nmovsxd r8, dword ptr [rsp+0Ch]\nmov edx, 1\nlea rsi, [rsp+128h+var_A9]\nadd r14, r8\nnop dword ptr [rax+00000000h]\nloc_15E0:\nmov [rsi+rdx], cl\nmov rdi, rdx\nadd rdx, 1\nmovzx ecx, byte ptr [r14+rdx-1]\ntest cl, cl\njnz short loc_15E0\nloc_15F4:\nmovsxd rdi, edi\nmov edx, 0Ah; base\nxor esi, esi; endptr\nmov [rsp+rdi+128h+var_A8], 0\nmov rdi, r12; nptr\ncall _strtol\nmov rdx, rax\nmov eax, r13d\nimul eax, ebp\nimul ebx, edx\ncdq\nidiv ebx\nxor eax, eax\ntest edx, edx\nsetz al\nmov rdx, [rsp+128h+var_40]\nsub rdx, fs:28h\njnz short loc_168F\nadd rsp, 0F8h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1650:\nmov r15d, 1\nmov r12d, 1\nxor eax, eax\njmp loc_14F6\nloc_1668:\nxor ecx, ecx\njmp loc_1543\nloc_1670:\nmov r15d, 1\nmov r8d, 1\nxor eax, eax\njmp loc_159E\nloc_1688:\nxor edi, edi\njmp loc_15F4\nloc_168F:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1490(char *a1, char *a2)\n{\n char v3; // dl\n __int64 v4; // rax\n int v5; // esi\n int v6; // r12d\n __int64 v7; // rax\n __int64 v8; // r15\n int v9; // ebp\n char v10; // al\n __int64 v11; // rdx\n int v12; // ecx\n int v13; // ebx\n char v14; // al\n __int64 v15; // rdx\n int v16; // esi\n int v17; // r8d\n __int64 v18; // rax\n __int64 v19; // r15\n int v20; // eax\n char v21; // cl\n __int64 v22; // rdx\n char *v23; // r14\n int v24; // edi\n int v26; // [rsp+Ch] [rbp-11Ch]\n char nptr[112]; // [rsp+10h] [rbp-118h] BYREF\n char v28[104]; // [rsp+80h] [rbp-A8h] BYREF\n unsigned __int64 v29; // [rsp+E8h] [rbp-40h]\n\n v3 = *a1;\n v29 = __readfsqword(0x28u);\n if ( v3 == 47 )\n {\n v8 = 1LL;\n v6 = 1;\n v7 = 0LL;\n }\n else\n {\n v4 = 1LL;\n do\n {\n nptr[v4 - 1] = v3;\n v5 = v4++;\n v3 = a1[v4 - 1];\n }\n while ( v3 != 47 );\n v6 = v5 + 1;\n v7 = v5;\n v8 = v5 + 1;\n }\n nptr[v7] = 0;\n v9 = strtol(nptr, 0LL, 10);\n v10 = a1[v8];\n if ( v10 )\n {\n v11 = 1LL;\n do\n {\n nptr[v11 + 111] = v10;\n v12 = v11++;\n v10 = a1[v6 - 1 + v11];\n }\n while ( v10 );\n }\n else\n {\n v12 = 0;\n }\n v28[v12] = 0;\n v13 = strtol(v28, 0LL, 10);\n v14 = *a2;\n if ( *a2 == 47 )\n {\n v19 = 1LL;\n v17 = 1;\n v18 = 0LL;\n }\n else\n {\n v15 = 1LL;\n do\n {\n nptr[v15 - 1] = v14;\n v16 = v15++;\n v14 = a2[v15 - 1];\n }\n while ( v14 != 47 );\n v17 = v16 + 1;\n v18 = v16;\n v19 = v16 + 1;\n }\n v26 = v17;\n nptr[v18] = 0;\n v20 = strtol(nptr, 0LL, 10);\n v21 = a2[v19];\n if ( v21 )\n {\n v22 = 1LL;\n v23 = &a2[v26];\n do\n {\n nptr[v22 + 111] = v21;\n v24 = v22++;\n v21 = v23[v22 - 1];\n }\n while ( v21 );\n }\n else\n {\n v24 = 0;\n }\n v28[v24] = 0;\n return v9 * v20 % (int)(strtol(v28, 0LL, 10) * v13) == 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1490(char *a1, char *a2) {\n char v3;\n long long v4;\n int v5;\n int v6;\n long long v7;\n long long v8;\n int v9;\n char v10;\n long long v11;\n int v12;\n int v13;\n char v14;\n long long v15;\n int v16;\n int v17;\n long long v18;\n long long v19;\n int v20;\n char v21;\n long long v22;\n char *v23;\n int v24;\n int v26;\n char nptr[112];\n char v28[104];\n unsigned long long v29;\n v3 = *a1;\n v29 = __readfsqword(40u);\n if (v3 == 47) {\n v8 = 1LL;\n v6 = 1;\n v7 = 0LL;\n } else {\n v4 = 1LL;\n do {\n nptr[v4 - 1] = v3;\n v5 = v4++;\n v3 = a1[v4 - 1];\n } while (v3 != 47);\n v6 = v5 + 1;\n v7 = v5;\n v8 = v5 + 1;\n }\n nptr[v7] = 0;\n v9 = strtol(nptr, 0LL, 10);\n v10 = a1[v8];\n if (v10) {\n v11 = 1LL;\n do {\n nptr[v11 + 111] = v10;\n v12 = v11++;\n v10 = a1[v6 - 1 + v11];\n } while (v10);\n } else {\n v12 = 0;\n }\n v28[v12] = 0;\n v13 = strtol(v28, 0LL, 10);\n v14 = *a2;\n if (*a2 == 47) {\n v19 = 1LL;\n v17 = 1;\n v18 = 0LL;\n } else {\n v15 = 1LL;\n do {\n nptr[v15 - 1] = v14;\n v16 = v15++;\n v14 = a2[v15 - 1];\n } while (v14 != 47);\n v17 = v16 + 1;\n v18 = v16;\n v19 = v16 + 1;\n }\n v26 = v17;\n nptr[v18] = 0;\n v20 = strtol(nptr, 0LL, 10);\n v21 = a2[v19];\n if (v21) {\n v22 = 1LL;\n v23 = &a2[v26];\n do {\n nptr[v22 + 111] = v21;\n v24 = v22++;\n v21 = v23[v22 - 1];\n } while (v21);\n } else {\n v24 = 0;\n }\n v28[v24] = 0;\n return v9 * v20 % (int)(strtol(v28, 0LL, 10) * v13) == 0;\n}", + "ida_pseudo_norm": "uint8_t func0(char *a1, char *a2) {\n char v3;\n long long v4;\n int v5;\n int v6;\n long long v7;\n long long v8;\n int v9;\n char v10;\n long long v11;\n int v12;\n int v13;\n char v14;\n long long v15;\n int v16;\n int v17;\n long long v18;\n long long v19;\n int v20;\n char v21;\n long long v22;\n char *v23;\n int v24;\n int v26;\n char nptr[112];\n char v28[104];\n unsigned long long v29;\n v3 = *a1;\n v29 = __readfsqword(40u);\n if (v3 == 47) {\n v8 = 1LL;\n v6 = 1;\n v7 = 0LL;\n } else {\n v4 = 1LL;\n do {\n nptr[v4 - 1] = v3;\n v5 = v4++;\n v3 = a1[v4 - 1];\n } while (v3 != 47);\n v6 = v5 + 1;\n v7 = v5;\n v8 = v5 + 1;\n }\n nptr[v7] = 0;\n v9 = strtol(nptr, 0LL, 10);\n v10 = a1[v8];\n if (v10) {\n v11 = 1LL;\n do {\n nptr[v11 + 111] = v10;\n v12 = v11++;\n v10 = a1[v6 - 1 + v11];\n } while (v10);\n } else {\n v12 = 0;\n }\n v28[v12] = 0;\n v13 = strtol(v28, 0LL, 10);\n v14 = *a2;\n if (*a2 == 47) {\n v19 = 1LL;\n v17 = 1;\n v18 = 0LL;\n } else {\n v15 = 1LL;\n do {\n nptr[v15 - 1] = v14;\n v16 = v15++;\n v14 = a2[v15 - 1];\n } while (v14 != 47);\n v17 = v16 + 1;\n v18 = v16;\n v19 = v16 + 1;\n }\n v26 = v17;\n nptr[v18] = 0;\n v20 = strtol(nptr, 0LL, 10);\n v21 = a2[v19];\n if (v21) {\n v22 = 1LL;\n v23 = &a2[v26];\n do {\n nptr[v22 + 111] = v21;\n v24 = v22++;\n v21 = v23[v22 - 1];\n } while (v21);\n } else {\n v24 = 0;\n }\n v28[v24] = 0;\n return v9 * v20 % (int)(strtol(v28, 0LL, 10) * v13) == 0;\n}" + }, + { + "index": "HumanEval-C-145", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int* func0(int nums[], int size) {\n int* sumdigit = (int*)malloc(size * sizeof(int));\n for (int i = 0; i < size; i++) {\n char w[12];\n sprintf(w, \"%d\", abs(nums[i]));\n int sum = 0, length = strlen(w);\n for (int j = 1; j < length; j++) sum += w[j] - '0';\n if (nums[i] > 0)\n sum += w[0] - '0';\n else\n sum -= w[0] - '0';\n sumdigit[i] = sum;\n }\n int m;\n for (int i = 0; i < size; i++)\n for (int j = 1; j < size; j++)\n if (sumdigit[j - 1] > sumdigit[j]) {\n m = sumdigit[j];\n sumdigit[j] = sumdigit[j - 1];\n sumdigit[j - 1] = m;\n m = nums[j];\n nums[j] = nums[j - 1];\n nums[j - 1] = m;\n }\n free(sumdigit);\n return nums;\n}", + "test": "#include \n#include \n\nint issame(int* a, int* b, int size_a, int size_b) {\n if (size_a != size_b) return 0;\n for (int i = 0; i < size_a; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int test1[] = {1, 11, -1, -11, -12};\n int expected1[] = {-1, -11, 1, -12, 11};\n assert(issame(func0(test1, 5), expected1, 5, 5));\n\n int test2[] = {1234, 423, 463, 145, 2, 423, 423, 53, 6, 37, 3457, 3, 56, 0, 46};\n int expected2[] = {0, 2, 3, 6, 53, 423, 423, 423, 1234, 145, 37, 46, 56, 463, 3457};\n assert(issame(func0(test2, 15), expected2, 15, 15));\n\n int test3[] = {};\n int expected3[] = {};\n assert(issame(func0(test3, 0), expected3, 0, 0));\n\n int test4[] = {1, -11, -32, 43, 54, -98, 2, -3};\n int expected4[] = {-3, -32, -98, -11, 1, 2, 43, 54};\n assert(issame(func0(test4, 8), expected4, 8, 8));\n\n int test5[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11};\n int expected5[] = {1, 10, 2, 11, 3, 4, 5, 6, 7, 8, 9};\n assert(issame(func0(test5, 11), expected5, 11, 11));\n\n int test6[] = {0, 6, 6, -76, -21, 23, 4};\n int expected6[] = {-76, -21, 0, 4, 23, 6, 6};\n assert(issame(func0(test6, 7), expected6, 7, 7));\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+var_48], rdi\nmov [rbp+var_4C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov eax, [rbp+var_4C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov [rbp+var_3C], 0\njmp loc_1315\nloc_124C:\nmov eax, [rbp+var_3C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax]\nmov edx, eax\nneg edx\ncmovs edx, eax\nlea rax, [rbp+s]\nlea rcx, format; \"%d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nmov [rbp+var_38], 0\nlea rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_24], eax\nmov [rbp+var_34], 1\njmp short loc_12BA\nloc_12A3:\nmov eax, [rbp+var_34]\ncdqe\nmovzx eax, [rbp+rax+s]\nmovsx eax, al\nsub eax, 30h ; '0'\nadd [rbp+var_38], eax\nadd [rbp+var_34], 1\nloc_12BA:\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_24]\njl short loc_12A3\nmov eax, [rbp+var_3C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njle short loc_12EB\nmovzx eax, [rbp+s]\nmovsx eax, al\nsub eax, 30h ; '0'\nadd [rbp+var_38], eax\njmp short loc_12F8\nloc_12EB:\nmovzx eax, [rbp+s]\nmovsx eax, al\nsub eax, 30h ; '0'\nsub [rbp+var_38], eax\nloc_12F8:\nmov eax, [rbp+var_3C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov eax, [rbp+var_38]\nmov [rdx], eax\nadd [rbp+var_3C], 1\nloc_1315:\nmov eax, [rbp+var_3C]\ncmp eax, [rbp+var_4C]\njl loc_124C\nmov [rbp+var_30], 0\njmp loc_143F\nloc_132D:\nmov [rbp+var_2C], 1\njmp loc_142F\nloc_1339:\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_2C]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle loc_142B\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_28], eax\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rbp+var_2C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+ptr]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov eax, [rbp+var_28]\nmov [rdx], eax\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_28], eax\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov edx, [rbp+var_2C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_48]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_48]\nadd rdx, rax\nmov eax, [rbp+var_28]\nmov [rdx], eax\nloc_142B:\nadd [rbp+var_2C], 1\nloc_142F:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_4C]\njl loc_1339\nadd [rbp+var_30], 1\nloc_143F:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_4C]\njl loc_132D\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_48]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_146F\ncall ___stack_chk_fail\nlocret_146F:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int v2; // edx\n int i; // [rsp+14h] [rbp-3Ch]\n int v5; // [rsp+18h] [rbp-38h]\n int v6; // [rsp+18h] [rbp-38h]\n int j; // [rsp+1Ch] [rbp-34h]\n int k; // [rsp+20h] [rbp-30h]\n int m; // [rsp+24h] [rbp-2Ch]\n int v10; // [rsp+28h] [rbp-28h]\n int v11; // [rsp+28h] [rbp-28h]\n int v12; // [rsp+2Ch] [rbp-24h]\n _DWORD *ptr; // [rsp+30h] [rbp-20h]\n char s[12]; // [rsp+3Ch] [rbp-14h] BYREF\n unsigned __int64 v15; // [rsp+48h] [rbp-8h]\n\n v15 = __readfsqword(0x28u);\n ptr = malloc(4LL * a2);\n for ( i = 0; i < a2; ++i )\n {\n v2 = -*(_DWORD *)(4LL * i + a1);\n if ( *(int *)(4LL * i + a1) > 0 )\n v2 = *(_DWORD *)(4LL * i + a1);\n sprintf(s, \"%d\", v2);\n v5 = 0;\n v12 = strlen(s);\n for ( j = 1; j < v12; ++j )\n v5 += s[j] - 48;\n if ( *(int *)(4LL * i + a1) <= 0 )\n v6 = v5 - (s[0] - 48);\n else\n v6 = s[0] - 48 + v5;\n ptr[i] = v6;\n }\n for ( k = 0; k < a2; ++k )\n {\n for ( m = 1; m < a2; ++m )\n {\n if ( ptr[m - 1] > ptr[m] )\n {\n v10 = ptr[m];\n ptr[m] = ptr[m - 1];\n ptr[m - 1] = v10;\n v11 = *(_DWORD *)(4LL * m + a1);\n *(_DWORD *)(4LL * m + a1) = *(_DWORD *)(4LL * m - 4 + a1);\n *(_DWORD *)(a1 + 4LL * m - 4) = v11;\n }\n }\n }\n free(ptr);\n return a1;\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+var_48], rdi\nmov [rbp+var_4C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov eax, [rbp+var_4C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov [rbp+var_3C], 0\njmp loc_1315\nloc_124C:\nmov eax, [rbp+var_3C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax]\nmov edx, eax\nneg edx\ncmovs edx, eax\nlea rax, [rbp+s]\nlea rcx, format; \"%d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nmov [rbp+var_38], 0\nlea rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_24], eax\nmov [rbp+var_34], 1\njmp short loc_12BA\nloc_12A3:\nmov eax, [rbp+var_34]\ncdqe\nmovzx eax, [rbp+rax+s]\nmovsx eax, al\nsub eax, 30h ; '0'\nadd [rbp+var_38], eax\nadd [rbp+var_34], 1\nloc_12BA:\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_24]\njl short loc_12A3\nmov eax, [rbp+var_3C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njle short loc_12EB\nmovzx eax, [rbp+s]\nmovsx eax, al\nsub eax, 30h ; '0'\nadd [rbp+var_38], eax\njmp short loc_12F8\nloc_12EB:\nmovzx eax, [rbp+s]\nmovsx eax, al\nsub eax, 30h ; '0'\nsub [rbp+var_38], eax\nloc_12F8:\nmov eax, [rbp+var_3C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov eax, [rbp+var_38]\nmov [rdx], eax\nadd [rbp+var_3C], 1\nloc_1315:\nmov eax, [rbp+var_3C]\ncmp eax, [rbp+var_4C]\njl loc_124C\nmov [rbp+var_30], 0\njmp loc_143F\nloc_132D:\nmov [rbp+var_2C], 1\njmp loc_142F\nloc_1339:\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_2C]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle loc_142B\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_28], eax\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rbp+var_2C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+ptr]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov eax, [rbp+var_28]\nmov [rdx], eax\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_28], eax\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov edx, [rbp+var_2C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_48]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_48]\nadd rdx, rax\nmov eax, [rbp+var_28]\nmov [rdx], eax\nloc_142B:\nadd [rbp+var_2C], 1\nloc_142F:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_4C]\njl loc_1339\nadd [rbp+var_30], 1\nloc_143F:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_4C]\njl loc_132D\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_48]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_146F\ncall ___stack_chk_fail\nlocret_146F:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1209(__int64 a1, int a2)\n{\n int v2; // edx\n int i; // [rsp+14h] [rbp-3Ch]\n int v5; // [rsp+18h] [rbp-38h]\n int v6; // [rsp+18h] [rbp-38h]\n int j; // [rsp+1Ch] [rbp-34h]\n int k; // [rsp+20h] [rbp-30h]\n int m; // [rsp+24h] [rbp-2Ch]\n int v10; // [rsp+28h] [rbp-28h]\n int v11; // [rsp+28h] [rbp-28h]\n int v12; // [rsp+2Ch] [rbp-24h]\n _DWORD *ptr; // [rsp+30h] [rbp-20h]\n char s[12]; // [rsp+3Ch] [rbp-14h] BYREF\n unsigned __int64 v15; // [rsp+48h] [rbp-8h]\n\n v15 = __readfsqword(0x28u);\n ptr = malloc(4LL * a2);\n for ( i = 0; i < a2; ++i )\n {\n v2 = -*(_DWORD *)(4LL * i + a1);\n if ( *(int *)(4LL * i + a1) > 0 )\n v2 = *(_DWORD *)(4LL * i + a1);\n sprintf(s, \"%d\", v2);\n v5 = 0;\n v12 = strlen(s);\n for ( j = 1; j < v12; ++j )\n v5 += s[j] - 48;\n if ( *(int *)(4LL * i + a1) <= 0 )\n v6 = v5 - (s[0] - 48);\n else\n v6 = s[0] - 48 + v5;\n ptr[i] = v6;\n }\n for ( k = 0; k < a2; ++k )\n {\n for ( m = 1; m < a2; ++m )\n {\n if ( ptr[m - 1] > ptr[m] )\n {\n v10 = ptr[m];\n ptr[m] = ptr[m - 1];\n ptr[m - 1] = v10;\n v11 = *(_DWORD *)(4LL * m + a1);\n *(_DWORD *)(4LL * m + a1) = *(_DWORD *)(4LL * m - 4 + a1);\n *(_DWORD *)(a1 + 4LL * m - 4) = v11;\n }\n }\n }\n free(ptr);\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1209(long long a1, int a2) {\n int v2;\n int i;\n int v5;\n int v6;\n int j;\n int k;\n int m;\n int v10;\n int v11;\n int v12;\n uint32_t *ptr;\n char s[12];\n unsigned long long v15;\n v15 = __readfsqword(40u);\n ptr = malloc(4LL * a2);\n for (i = 0; i < a2; ++i) {\n v2 = -*(uint32_t *)(4LL * i + a1);\n if (*(int *)(4LL * i + a1) > 0) v2 = *(uint32_t *)(4LL * i + a1);\n sprintf(s, \"%d\", v2);\n v5 = 0;\n v12 = strlen(s);\n for (j = 1; j < v12; ++j) v5 += s[j] - 48;\n if (*(int *)(4LL * i + a1) <= 0)\n v6 = v5 - (s[0] - 48);\n else\n v6 = s[0] - 48 + v5;\n ptr[i] = v6;\n }\n for (k = 0; k < a2; ++k) {\n for (m = 1; m < a2; ++m) {\n if (ptr[m - 1] > ptr[m]) {\n v10 = ptr[m];\n ptr[m] = ptr[m - 1];\n ptr[m - 1] = v10;\n v11 = *(uint32_t *)(4LL * m + a1);\n *(uint32_t *)(4LL * m + a1) = *(uint32_t *)(4LL * m - 4 + a1);\n *(uint32_t *)(a1 + 4LL * m - 4) = v11;\n }\n }\n }\n free(ptr);\n return a1;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int v2;\n int i;\n int v5;\n int v6;\n int j;\n int k;\n int m;\n int v10;\n int v11;\n int v12;\n uint32_t *ptr;\n char s[12];\n unsigned long long v15;\n v15 = __readfsqword(40u);\n ptr = malloc(4LL * a2);\n for (i = 0; i < a2; ++i) {\n v2 = -*(uint32_t *)(4LL * i + a1);\n if (*(int *)(4LL * i + a1) > 0) v2 = *(uint32_t *)(4LL * i + a1);\n sprintf(s, \"%d\", v2);\n v5 = 0;\n v12 = strlen(s);\n for (j = 1; j < v12; ++j) v5 += s[j] - 48;\n if (*(int *)(4LL * i + a1) <= 0)\n v6 = v5 - (s[0] - 48);\n else\n v6 = s[0] - 48 + v5;\n ptr[i] = v6;\n }\n for (k = 0; k < a2; ++k) {\n for (m = 1; m < a2; ++m) {\n if (ptr[m - 1] > ptr[m]) {\n v10 = ptr[m];\n ptr[m] = ptr[m - 1];\n ptr[m - 1] = v10;\n v11 = *(uint32_t *)(4LL * m + a1);\n *(uint32_t *)(4LL * m + a1) = *(uint32_t *)(4LL * m - 4 + a1);\n *(uint32_t *)(a1 + 4LL * m - 4) = v11;\n }\n }\n }\n free(ptr);\n return a1;\n}" + }, + { + "index": "HumanEval-C-145", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int* func0(int nums[], int size) {\n int* sumdigit = (int*)malloc(size * sizeof(int));\n for (int i = 0; i < size; i++) {\n char w[12];\n sprintf(w, \"%d\", abs(nums[i]));\n int sum = 0, length = strlen(w);\n for (int j = 1; j < length; j++) sum += w[j] - '0';\n if (nums[i] > 0)\n sum += w[0] - '0';\n else\n sum -= w[0] - '0';\n sumdigit[i] = sum;\n }\n int m;\n for (int i = 0; i < size; i++)\n for (int j = 1; j < size; j++)\n if (sumdigit[j - 1] > sumdigit[j]) {\n m = sumdigit[j];\n sumdigit[j] = sumdigit[j - 1];\n sumdigit[j - 1] = m;\n m = nums[j];\n nums[j] = nums[j - 1];\n nums[j - 1] = m;\n }\n free(sumdigit);\n return nums;\n}", + "test": "#include \n#include \n\nint issame(int* a, int* b, int size_a, int size_b) {\n if (size_a != size_b) return 0;\n for (int i = 0; i < size_a; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int test1[] = {1, 11, -1, -11, -12};\n int expected1[] = {-1, -11, 1, -12, 11};\n assert(issame(func0(test1, 5), expected1, 5, 5));\n\n int test2[] = {1234, 423, 463, 145, 2, 423, 423, 53, 6, 37, 3457, 3, 56, 0, 46};\n int expected2[] = {0, 2, 3, 6, 53, 423, 423, 423, 1234, 145, 37, 46, 56, 463, 3457};\n assert(issame(func0(test2, 15), expected2, 15, 15));\n\n int test3[] = {};\n int expected3[] = {};\n assert(issame(func0(test3, 0), expected3, 0, 0));\n\n int test4[] = {1, -11, -32, 43, 54, -98, 2, -3};\n int expected4[] = {-3, -32, -98, -11, 1, 2, 43, 54};\n assert(issame(func0(test4, 8), expected4, 8, 8));\n\n int test5[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11};\n int expected5[] = {1, 10, 2, 11, 3, 4, 5, 6, 7, 8, 9};\n assert(issame(func0(test5, 11), expected5, 11, 11));\n\n int test6[] = {0, 6, 6, -76, -21, 23, 4};\n int expected6[] = {-76, -21, 0, 4, 23, 6, 6};\n assert(issame(func0(test6, 7), expected6, 7, 7));\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 38h\nmov r14, rdi\nmov r13d, esi\nmov rax, fs:28h\nmov [rsp+68h+var_40], rax\nxor eax, eax\nmovsxd rbp, esi\nshl rbp, 2\nmov rdi, rbp; size\ncall _malloc\nmov r15, rax\ntest r13d, r13d\njle loc_1355\nmov rbx, r14\nlea rax, [rbp+r14+0]\nmov [rsp+68h+var_60], rax\nmov rbp, r15\njmp short loc_1287\nloc_125E:\nmov eax, 0\njmp loc_12E9\nloc_1268:\nmovsx edx, [rsp+68h+s]\nsub edx, 30h ; '0'\nsub eax, edx\nloc_1272:\nmov [rbp+0], eax\nadd rbx, 4\nadd rbp, 4\nmov rax, [rsp+68h+var_60]\ncmp rbx, rax\njz short loc_1304\nloc_1287:\nmov [rsp+68h+var_68], rbx\nlea r12, [rsp+68h+s]\nmov eax, [rbx]\nmov r8d, eax\nneg r8d\ncmovs r8d, eax\nlea rcx, unk_2004\nmov edx, 0Ch\nmov esi, 2\nmov rdi, r12\nmov eax, 0\ncall ___sprintf_chk\nmov rdi, r12; s\ncall _strlen\ncmp eax, 1\njle short loc_125E\nlea rdx, [rsp+68h+var_4B]\nlea eax, [rax-2]\nlea rsi, [rsp+rax+68h+var_4A]\nmov eax, 0\nloc_12D9:\nmovsx ecx, byte ptr [rdx]\nlea eax, [rax+rcx-30h]\nadd rdx, 1\ncmp rdx, rsi\njnz short loc_12D9\nloc_12E9:\nmov rdi, [rsp+68h+var_68]\ncmp dword ptr [rdi], 0\njle loc_1268\nmovsx edx, [rsp+68h+s]\nlea eax, [rax+rdx-30h]\njmp loc_1272\nloc_1304:\nlea eax, [r13-2]\nlea rdi, [r15+rax*4+8]\nmov r8d, 0\njmp short loc_1345\nloc_1315:\nadd rax, 4\nadd rdx, 4\ncmp rax, rdi\njz short loc_133C\nloc_1322:\nmov esi, [rax-4]\nmov ecx, [rax]\ncmp esi, ecx\njle short loc_1315\nmov [rax], esi\nmov [rax-4], ecx\nmov ecx, [rdx]\nmov esi, [rdx-4]\nmov [rdx], esi\nmov [rdx-4], ecx\njmp short loc_1315\nloc_133C:\nadd r8d, 1\ncmp r13d, r8d\njz short loc_1355\nloc_1345:\nlea rax, [r15+4]\nlea rdx, [r14+4]\ncmp r13d, 1\njg short loc_1322\njmp short loc_133C\nloc_1355:\nmov rdi, r15; ptr\ncall _free\nmov rax, [rsp+68h+var_40]\nsub rax, fs:28h\njnz short loc_137F\nmov rax, r14\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_137F:\ncall ___stack_chk_fail", + "ida_pseudo": "int *__fastcall func0(int *a1, int a2)\n{\n int *v3; // r15\n int *v4; // rbx\n int *v5; // rbp\n int v6; // eax\n int v7; // eax\n __int64 v8; // r8\n int v9; // eax\n char *v10; // rdx\n char *v11; // rsi\n int v12; // r8d\n int *v13; // rax\n int *v14; // rdx\n int v15; // esi\n int v16; // ecx\n int v17; // ecx\n int *v19; // [rsp+8h] [rbp-60h]\n char s; // [rsp+1Ch] [rbp-4Ch] BYREF\n _BYTE v21[11]; // [rsp+1Dh] [rbp-4Bh] BYREF\n unsigned __int64 v22; // [rsp+28h] [rbp-40h]\n\n v22 = __readfsqword(0x28u);\n v3 = (int *)malloc(4LL * a2);\n if ( a2 > 0 )\n {\n v4 = a1;\n v19 = &a1[a2];\n v5 = v3;\n do\n {\n v8 = (unsigned int)-*v4;\n if ( *v4 > 0 )\n v8 = (unsigned int)*v4;\n __sprintf_chk(&s, 2LL, 12LL, &unk_2004, v8);\n v9 = strlen(&s);\n if ( v9 <= 1 )\n {\n v6 = 0;\n }\n else\n {\n v10 = v21;\n v11 = &v21[v9 - 2 + 1];\n v6 = 0;\n do\n v6 = v6 + *v10++ - 48;\n while ( v10 != v11 );\n }\n if ( *v4 <= 0 )\n v7 = v6 - (s - 48);\n else\n v7 = v6 + s - 48;\n *v5 = v7;\n ++v4;\n ++v5;\n }\n while ( v4 != v19 );\n v12 = 0;\n do\n {\n v13 = v3 + 1;\n v14 = a1 + 1;\n if ( a2 > 1 )\n {\n do\n {\n v15 = *(v13 - 1);\n v16 = *v13;\n if ( v15 > *v13 )\n {\n *v13 = v15;\n *(v13 - 1) = v16;\n v17 = *v14;\n *v14 = *(v14 - 1);\n *(v14 - 1) = v17;\n }\n ++v13;\n ++v14;\n }\n while ( v13 != &v3[a2 - 2 + 2] );\n }\n ++v12;\n }\n while ( a2 != v12 );\n }\n free(v3);\n return a1;\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 38h\nmov r14, rdi\nmov r13d, esi\nmov rax, fs:28h\nmov [rsp+68h+var_40], rax\nxor eax, eax\nmovsxd rbp, esi\nshl rbp, 2\nmov rdi, rbp; size\ncall _malloc\nmov r15, rax\ntest r13d, r13d\njle loc_1355\nmov rbx, r14\nlea rax, [rbp+r14+0]\nmov [rsp+68h+var_60], rax\nmov rbp, r15\njmp short loc_1287\nloc_125E:\nmov eax, 0\njmp loc_12E9\nloc_1268:\nmovsx edx, [rsp+68h+s]\nsub edx, 30h ; '0'\nsub eax, edx\nloc_1272:\nmov [rbp+0], eax\nadd rbx, 4\nadd rbp, 4\nmov rax, [rsp+68h+var_60]\ncmp rbx, rax\njz short loc_1304\nloc_1287:\nmov [rsp+68h+var_68], rbx\nlea r12, [rsp+68h+s]\nmov eax, [rbx]\nmov r8d, eax\nneg r8d\ncmovs r8d, eax\nlea rcx, unk_2004\nmov edx, 0Ch\nmov esi, 2\nmov rdi, r12\nmov eax, 0\ncall ___sprintf_chk\nmov rdi, r12; s\ncall _strlen\ncmp eax, 1\njle short loc_125E\nlea rdx, [rsp+68h+var_4B]\nlea eax, [rax-2]\nlea rsi, [rsp+rax+68h+var_4A]\nmov eax, 0\nloc_12D9:\nmovsx ecx, byte ptr [rdx]\nlea eax, [rax+rcx-30h]\nadd rdx, 1\ncmp rdx, rsi\njnz short loc_12D9\nloc_12E9:\nmov rdi, [rsp+68h+var_68]\ncmp dword ptr [rdi], 0\njle loc_1268\nmovsx edx, [rsp+68h+s]\nlea eax, [rax+rdx-30h]\njmp loc_1272\nloc_1304:\nlea eax, [r13-2]\nlea rdi, [r15+rax*4+8]\nmov r8d, 0\njmp short loc_1345\nloc_1315:\nadd rax, 4\nadd rdx, 4\ncmp rax, rdi\njz short loc_133C\nloc_1322:\nmov esi, [rax-4]\nmov ecx, [rax]\ncmp esi, ecx\njle short loc_1315\nmov [rax], esi\nmov [rax-4], ecx\nmov ecx, [rdx]\nmov esi, [rdx-4]\nmov [rdx], esi\nmov [rdx-4], ecx\njmp short loc_1315\nloc_133C:\nadd r8d, 1\ncmp r13d, r8d\njz short loc_1355\nloc_1345:\nlea rax, [r15+4]\nlea rdx, [r14+4]\ncmp r13d, 1\njg short loc_1322\njmp short loc_133C\nloc_1355:\nmov rdi, r15; ptr\ncall _free\nmov rax, [rsp+68h+var_40]\nsub rax, fs:28h\njnz short loc_137F\nmov rax, r14\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_137F:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "int *__fastcall sub_1209(int *a1, int a2)\n{\n int *v3; // r15\n int *v4; // rbx\n int *v5; // rbp\n int v6; // eax\n int v7; // eax\n __int64 v8; // r8\n int v9; // eax\n char *v10; // rdx\n char *v11; // rsi\n int v12; // r8d\n int *v13; // rax\n int *v14; // rdx\n int v15; // esi\n int v16; // ecx\n int v17; // ecx\n int *v19; // [rsp+8h] [rbp-60h]\n char s; // [rsp+1Ch] [rbp-4Ch] BYREF\n _BYTE v21[11]; // [rsp+1Dh] [rbp-4Bh] BYREF\n unsigned __int64 v22; // [rsp+28h] [rbp-40h]\n\n v22 = __readfsqword(0x28u);\n v3 = (int *)malloc(4LL * a2);\n if ( a2 > 0 )\n {\n v4 = a1;\n v19 = &a1[a2];\n v5 = v3;\n do\n {\n v8 = (unsigned int)-*v4;\n if ( *v4 > 0 )\n v8 = (unsigned int)*v4;\n __sprintf_chk(&s, 2LL, 12LL, &unk_2004, v8);\n v9 = strlen(&s);\n if ( v9 <= 1 )\n {\n v6 = 0;\n }\n else\n {\n v10 = v21;\n v11 = &v21[v9 - 2 + 1];\n v6 = 0;\n do\n v6 = v6 + *v10++ - 48;\n while ( v10 != v11 );\n }\n if ( *v4 <= 0 )\n v7 = v6 - (s - 48);\n else\n v7 = v6 + s - 48;\n *v5 = v7;\n ++v4;\n ++v5;\n }\n while ( v4 != v19 );\n v12 = 0;\n do\n {\n v13 = v3 + 1;\n v14 = a1 + 1;\n if ( a2 > 1 )\n {\n do\n {\n v15 = *(v13 - 1);\n v16 = *v13;\n if ( v15 > *v13 )\n {\n *v13 = v15;\n *(v13 - 1) = v16;\n v17 = *v14;\n *v14 = *(v14 - 1);\n *(v14 - 1) = v17;\n }\n ++v13;\n ++v14;\n }\n while ( v13 != &v3[a2 - 2 + 2] );\n }\n ++v12;\n }\n while ( a2 != v12 );\n }\n free(v3);\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "int *sub_1209(int *a1, int a2) {\n int *v3;\n int *v4;\n int *v5;\n int v6;\n int v7;\n long long v8;\n int v9;\n char *v10;\n char *v11;\n int v12;\n int *v13;\n int *v14;\n int v15;\n int v16;\n int v17;\n int *v19;\n char s;\n uint8_t v21[11];\n unsigned long long v22;\n v22 = __readfsqword(40u);\n v3 = (int *)malloc(4LL * a2);\n if (a2 > 0) {\n v4 = a1;\n v19 = &a1[a2];\n v5 = v3;\n do {\n v8 = (unsigned int)-*v4;\n if (*v4 > 0) v8 = (unsigned int)*v4;\n __sprintf_chk(&s, 2LL, 12LL, &unk_2004, v8);\n v9 = strlen(&s);\n if (v9 <= 1) {\n v6 = 0;\n } else {\n v10 = v21;\n v11 = &v21[v9 - 2 + 1];\n v6 = 0;\n do\n v6 = v6 + *v10++ - 48;\n while (v10 != v11);\n }\n if (*v4 <= 0)\n v7 = v6 - (s - 48);\n else\n v7 = v6 + s - 48;\n *v5 = v7;\n ++v4;\n ++v5;\n } while (v4 != v19);\n v12 = 0;\n do {\n v13 = v3 + 1;\n v14 = a1 + 1;\n if (a2 > 1) {\n do {\n v15 = *(v13 - 1);\n v16 = *v13;\n if (v15 > *v13) {\n *v13 = v15;\n *(v13 - 1) = v16;\n v17 = *v14;\n *v14 = *(v14 - 1);\n *(v14 - 1) = v17;\n }\n ++v13;\n ++v14;\n } while (v13 != &v3[a2 - 2 + 2]);\n }\n ++v12;\n } while (a2 != v12);\n }\n free(v3);\n return a1;\n}", + "ida_pseudo_norm": "int *func0(int *a1, int a2) {\n int *v3;\n int *v4;\n int *v5;\n int v6;\n int v7;\n long long v8;\n int v9;\n char *v10;\n char *v11;\n int v12;\n int *v13;\n int *v14;\n int v15;\n int v16;\n int v17;\n int *v19;\n char s;\n uint8_t v21[11];\n unsigned long long v22;\n v22 = __readfsqword(40u);\n v3 = (int *)malloc(4LL * a2);\n if (a2 > 0) {\n v4 = a1;\n v19 = &a1[a2];\n v5 = v3;\n do {\n v8 = (unsigned int)-*v4;\n if (*v4 > 0) v8 = (unsigned int)*v4;\n __sprintf_chk(&s, 2LL, 12LL, &unk_2004, v8);\n v9 = strlen(&s);\n if (v9 <= 1) {\n v6 = 0;\n } else {\n v10 = v21;\n v11 = &v21[v9 - 2 + 1];\n v6 = 0;\n do\n v6 = v6 + *v10++ - 48;\n while (v10 != v11);\n }\n if (*v4 <= 0)\n v7 = v6 - (s - 48);\n else\n v7 = v6 + s - 48;\n *v5 = v7;\n ++v4;\n ++v5;\n } while (v4 != v19);\n v12 = 0;\n do {\n v13 = v3 + 1;\n v14 = a1 + 1;\n if (a2 > 1) {\n do {\n v15 = *(v13 - 1);\n v16 = *v13;\n if (v15 > *v13) {\n *v13 = v15;\n *(v13 - 1) = v16;\n v17 = *v14;\n *v14 = *(v14 - 1);\n *(v14 - 1) = v17;\n }\n ++v13;\n ++v14;\n } while (v13 != &v3[a2 - 2 + 2]);\n }\n ++v12;\n } while (a2 != v12);\n }\n free(v3);\n return a1;\n}" + }, + { + "index": "HumanEval-C-145", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int* func0(int nums[], int size) {\n int* sumdigit = (int*)malloc(size * sizeof(int));\n for (int i = 0; i < size; i++) {\n char w[12];\n sprintf(w, \"%d\", abs(nums[i]));\n int sum = 0, length = strlen(w);\n for (int j = 1; j < length; j++) sum += w[j] - '0';\n if (nums[i] > 0)\n sum += w[0] - '0';\n else\n sum -= w[0] - '0';\n sumdigit[i] = sum;\n }\n int m;\n for (int i = 0; i < size; i++)\n for (int j = 1; j < size; j++)\n if (sumdigit[j - 1] > sumdigit[j]) {\n m = sumdigit[j];\n sumdigit[j] = sumdigit[j - 1];\n sumdigit[j - 1] = m;\n m = nums[j];\n nums[j] = nums[j - 1];\n nums[j - 1] = m;\n }\n free(sumdigit);\n return nums;\n}", + "test": "#include \n#include \n\nint issame(int* a, int* b, int size_a, int size_b) {\n if (size_a != size_b) return 0;\n for (int i = 0; i < size_a; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int test1[] = {1, 11, -1, -11, -12};\n int expected1[] = {-1, -11, 1, -12, 11};\n assert(issame(func0(test1, 5), expected1, 5, 5));\n\n int test2[] = {1234, 423, 463, 145, 2, 423, 423, 53, 6, 37, 3457, 3, 56, 0, 46};\n int expected2[] = {0, 2, 3, 6, 53, 423, 423, 423, 1234, 145, 37, 46, 56, 463, 3457};\n assert(issame(func0(test2, 15), expected2, 15, 15));\n\n int test3[] = {};\n int expected3[] = {};\n assert(issame(func0(test3, 0), expected3, 0, 0));\n\n int test4[] = {1, -11, -32, 43, 54, -98, 2, -3};\n int expected4[] = {-3, -32, -98, -11, 1, 2, 43, 54};\n assert(issame(func0(test4, 8), expected4, 8, 8));\n\n int test5[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11};\n int expected5[] = {1, 10, 2, 11, 3, 4, 5, 6, 7, 8, 9};\n assert(issame(func0(test5, 11), expected5, 11, 11));\n\n int test6[] = {0, 6, 6, -76, -21, 23, 4};\n int expected6[] = {-76, -21, 0, 4, 23, 6, 6};\n assert(issame(func0(test6, 7), expected6, 7, 7));\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\nmov r13, rdi\npush r12\npush rbp\nmovsxd rbp, esi\npush rbx\nmov r12, rbp\nshl rbp, 2\nmov rdi, rbp; size\nsub rsp, 38h\nmov rax, fs:28h\nmov [rsp+68h+var_40], rax\nxor eax, eax\ncall _malloc\nmov r14, rax\ntest r12d, r12d\njle loc_1758\nlea rax, [rbp+r13+0]\nmov r15, r13\nlea rbx, [rsp+68h+s]\nmov rbp, r14\nmov [rsp+68h+var_68], rax\nlea rax, [rsp+68h+var_4A]\nmov [rsp+68h+var_60], rax\nnop dword ptr [rax+00000000h]\nloc_1668:\nmov eax, [r15]\nmov rdi, rbx\nmov edx, 0Ch\nmov esi, 2\nlea rcx, unk_2004\nmov r8d, eax\nneg r8d\ncmovs r8d, eax\nxor eax, eax\ncall ___sprintf_chk\nmov rdi, rbx; s\ncall _strlen\ncmp rax, 1\njbe loc_1788\nlea esi, [rax-2]\nmov rax, [rsp+68h+var_60]\nlea rdx, [rsp+68h+var_4B]\nadd rsi, rax\nxor eax, eax\nnop dword ptr [rax+00h]\nloc_16B8:\nmovsx ecx, byte ptr [rdx]\nadd rdx, 1\nlea eax, [rax+rcx-30h]\ncmp rdx, rsi\njnz short loc_16B8\nloc_16C8:\nmovsx edx, [rsp+68h+s]\nmov esi, [r15]\nmov ecx, eax\nsub edx, 30h ; '0'\nsub ecx, edx\ntest esi, esi\njle short loc_16DE\nlea ecx, [rax+rdx]\nloc_16DE:\nmov rax, [rsp+68h+var_68]\nadd r15, 4\nmov [rbp+0], ecx\nadd rbp, 4\ncmp r15, rax\njnz loc_1668\ncmp r12d, 1\njz short loc_1758\nlea eax, [r12-2]\nxor r8d, r8d\nlea rdi, [r14+rax*4+4]\nnop dword ptr [rax+00000000h]\nloc_1710:\nmov rdx, r13\nmov rax, r14\nnop word ptr [rax+rax+00000000h]\nloc_1720:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd esi, xmm0\nmovd ecx, xmm1\ncmp esi, ecx\njle short loc_1742\npshufd xmm0, xmm0, 0E1h\nrol qword ptr [rdx], 20h\nmovq qword ptr [rax], xmm0\nloc_1742:\nadd rax, 4\nadd rdx, 4\ncmp rax, rdi\njnz short loc_1720\nadd r8d, 1\ncmp r12d, r8d\njnz short loc_1710\nloc_1758:\nmov rdi, r14; ptr\ncall _free\nmov rax, [rsp+68h+var_40]\nsub rax, fs:28h\njnz short loc_178F\nadd rsp, 38h\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1788:\nxor eax, eax\njmp loc_16C8\nloc_178F:\ncall ___stack_chk_fail", + "ida_pseudo": "int *__fastcall func0(int *a1, int a2)\n{\n __m128i *v3; // r14\n int *v4; // r15\n __m128i *v5; // rbp\n __int64 v6; // r8\n size_t v7; // rax\n char *v8; // rdx\n char *v9; // rsi\n int v10; // eax\n int v11; // ecx\n int v12; // edx\n int v13; // ecx\n int v14; // r8d\n int *v15; // rdx\n __m128i *v16; // rax\n __m128i v17; // xmm0\n int *v19; // [rsp+0h] [rbp-68h]\n char s; // [rsp+1Ch] [rbp-4Ch] BYREF\n _BYTE v21[11]; // [rsp+1Dh] [rbp-4Bh] BYREF\n unsigned __int64 v22; // [rsp+28h] [rbp-40h]\n\n v22 = __readfsqword(0x28u);\n v3 = (__m128i *)malloc(4LL * a2);\n if ( a2 > 0 )\n {\n v4 = a1;\n v5 = v3;\n v19 = &a1[a2];\n do\n {\n v6 = (unsigned int)-*v4;\n if ( *v4 > 0 )\n v6 = (unsigned int)*v4;\n __sprintf_chk(&s, 2LL, 12LL, &unk_2004, v6);\n v7 = strlen(&s);\n if ( v7 <= 1 )\n {\n v10 = 0;\n }\n else\n {\n v8 = v21;\n v9 = &v21[(unsigned int)(v7 - 2) + 1];\n v10 = 0;\n do\n {\n v11 = *v8++;\n v10 = v10 + v11 - 48;\n }\n while ( v8 != v9 );\n }\n v12 = s - 48;\n v13 = v10 - v12;\n if ( *v4 > 0 )\n v13 = v10 + v12;\n ++v4;\n v5->m128i_i32[0] = v13;\n v5 = (__m128i *)((char *)v5 + 4);\n }\n while ( v4 != v19 );\n if ( a2 != 1 )\n {\n v14 = 0;\n do\n {\n v15 = a1;\n v16 = v3;\n do\n {\n v17 = _mm_loadl_epi64(v16);\n if ( _mm_cvtsi128_si32(v17) > _mm_cvtsi128_si32(_mm_shuffle_epi32(v17, 229)) )\n {\n *(_QWORD *)v15 = __ROL8__(*(_QWORD *)v15, 32);\n v16->m128i_i64[0] = _mm_shuffle_epi32(v17, 225).m128i_u64[0];\n }\n v16 = (__m128i *)((char *)v16 + 4);\n ++v15;\n }\n while ( v16 != (__m128i *)((char *)v3->m128i_i64 + 4 * (unsigned int)(a2 - 2) + 4) );\n ++v14;\n }\n while ( a2 != v14 );\n }\n }\n free(v3);\n return a1;\n}", + "ida_strip_asm": "sub_1600:\nendbr64\npush r15\npush r14\npush r13\nmov r13, rdi\npush r12\npush rbp\nmovsxd rbp, esi\npush rbx\nmov r12, rbp\nshl rbp, 2\nmov rdi, rbp; size\nsub rsp, 38h\nmov rax, fs:28h\nmov [rsp+68h+var_40], rax\nxor eax, eax\ncall _malloc\nmov r14, rax\ntest r12d, r12d\njle loc_1758\nlea rax, [rbp+r13+0]\nmov r15, r13\nlea rbx, [rsp+68h+s]\nmov rbp, r14\nmov [rsp+68h+var_68], rax\nlea rax, [rsp+68h+var_4A]\nmov [rsp+68h+var_60], rax\nnop dword ptr [rax+00000000h]\nloc_1668:\nmov eax, [r15]\nmov rdi, rbx\nmov edx, 0Ch\nmov esi, 2\nlea rcx, unk_2004\nmov r8d, eax\nneg r8d\ncmovs r8d, eax\nxor eax, eax\ncall ___sprintf_chk\nmov rdi, rbx; s\ncall _strlen\ncmp rax, 1\njbe loc_1788\nlea esi, [rax-2]\nmov rax, [rsp+68h+var_60]\nlea rdx, [rsp+68h+var_4B]\nadd rsi, rax\nxor eax, eax\nnop dword ptr [rax+00h]\nloc_16B8:\nmovsx ecx, byte ptr [rdx]\nadd rdx, 1\nlea eax, [rax+rcx-30h]\ncmp rdx, rsi\njnz short loc_16B8\nloc_16C8:\nmovsx edx, [rsp+68h+s]\nmov esi, [r15]\nmov ecx, eax\nsub edx, 30h ; '0'\nsub ecx, edx\ntest esi, esi\njle short loc_16DE\nlea ecx, [rax+rdx]\nloc_16DE:\nmov rax, [rsp+68h+var_68]\nadd r15, 4\nmov [rbp+0], ecx\nadd rbp, 4\ncmp r15, rax\njnz loc_1668\ncmp r12d, 1\njz short loc_1758\nlea eax, [r12-2]\nxor r8d, r8d\nlea rdi, [r14+rax*4+4]\nnop dword ptr [rax+00000000h]\nloc_1710:\nmov rdx, r13\nmov rax, r14\nnop word ptr [rax+rax+00000000h]\nloc_1720:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd esi, xmm0\nmovd ecx, xmm1\ncmp esi, ecx\njle short loc_1742\npshufd xmm0, xmm0, 0E1h\nrol qword ptr [rdx], 20h\nmovq qword ptr [rax], xmm0\nloc_1742:\nadd rax, 4\nadd rdx, 4\ncmp rax, rdi\njnz short loc_1720\nadd r8d, 1\ncmp r12d, r8d\njnz short loc_1710\nloc_1758:\nmov rdi, r14; ptr\ncall _free\nmov rax, [rsp+68h+var_40]\nsub rax, fs:28h\njnz short loc_178F\nadd rsp, 38h\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1788:\nxor eax, eax\njmp loc_16C8\nloc_178F:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "int *__fastcall sub_1600(int *a1, int a2)\n{\n __m128i *v3; // r14\n int *v4; // r15\n __m128i *v5; // rbp\n __int64 v6; // r8\n size_t v7; // rax\n char *v8; // rdx\n char *v9; // rsi\n int v10; // eax\n int v11; // ecx\n int v12; // edx\n int v13; // ecx\n int v14; // r8d\n int *v15; // rdx\n __m128i *v16; // rax\n __m128i v17; // xmm0\n int *v19; // [rsp+0h] [rbp-68h]\n char s; // [rsp+1Ch] [rbp-4Ch] BYREF\n _BYTE v21[11]; // [rsp+1Dh] [rbp-4Bh] BYREF\n unsigned __int64 v22; // [rsp+28h] [rbp-40h]\n\n v22 = __readfsqword(0x28u);\n v3 = (__m128i *)malloc(4LL * a2);\n if ( a2 > 0 )\n {\n v4 = a1;\n v5 = v3;\n v19 = &a1[a2];\n do\n {\n v6 = (unsigned int)-*v4;\n if ( *v4 > 0 )\n v6 = (unsigned int)*v4;\n __sprintf_chk(&s, 2LL, 12LL, &unk_2004, v6);\n v7 = strlen(&s);\n if ( v7 <= 1 )\n {\n v10 = 0;\n }\n else\n {\n v8 = v21;\n v9 = &v21[(unsigned int)(v7 - 2) + 1];\n v10 = 0;\n do\n {\n v11 = *v8++;\n v10 = v10 + v11 - 48;\n }\n while ( v8 != v9 );\n }\n v12 = s - 48;\n v13 = v10 - v12;\n if ( *v4 > 0 )\n v13 = v10 + v12;\n ++v4;\n v5->m128i_i32[0] = v13;\n v5 = (__m128i *)((char *)v5 + 4);\n }\n while ( v4 != v19 );\n if ( a2 != 1 )\n {\n v14 = 0;\n do\n {\n v15 = a1;\n v16 = v3;\n do\n {\n v17 = _mm_loadl_epi64(v16);\n if ( _mm_cvtsi128_si32(v17) > _mm_cvtsi128_si32(_mm_shuffle_epi32(v17, 229)) )\n {\n *(_QWORD *)v15 = __ROL8__(*(_QWORD *)v15, 32);\n v16->m128i_i64[0] = _mm_shuffle_epi32(v17, 225).m128i_u64[0];\n }\n v16 = (__m128i *)((char *)v16 + 4);\n ++v15;\n }\n while ( v16 != (__m128i *)((char *)v3->m128i_i64 + 4 * (unsigned int)(a2 - 2) + 4) );\n ++v14;\n }\n while ( a2 != v14 );\n }\n }\n free(v3);\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "int *sub_1600(int *a1, int a2) {\n __m128i *v3;\n int *v4;\n __m128i *v5;\n long long v6;\n unsigned int v7;\n char *v8;\n char *v9;\n int v10;\n int v11;\n int v12;\n int v13;\n int v14;\n int *v15;\n __m128i *v16;\n __m128i v17;\n int *v19;\n char s;\n uint8_t v21[11];\n unsigned long long v22;\n v22 = __readfsqword(40u);\n v3 = (__m128i *)malloc(4LL * a2);\n if (a2 > 0) {\n v4 = a1;\n v5 = v3;\n v19 = &a1[a2];\n do {\n v6 = (unsigned int)-*v4;\n if (*v4 > 0) v6 = (unsigned int)*v4;\n __sprintf_chk(&s, 2LL, 12LL, &unk_2004, v6);\n v7 = strlen(&s);\n if (v7 <= 1) {\n v10 = 0;\n } else {\n v8 = v21;\n v9 = &v21[(unsigned int)(v7 - 2) + 1];\n v10 = 0;\n do {\n v11 = *v8++;\n v10 = v10 + v11 - 48;\n } while (v8 != v9);\n }\n v12 = s - 48;\n v13 = v10 - v12;\n if (*v4 > 0) v13 = v10 + v12;\n ++v4;\n v5->m128i_i32[0] = v13;\n v5 = (__m128i *)((char *)v5 + 4);\n } while (v4 != v19);\n if (a2 != 1) {\n v14 = 0;\n do {\n v15 = a1;\n v16 = v3;\n do {\n v17 = _mm_loadl_epi64(v16);\n if (_mm_cvtsi128_si32(v17) >\n _mm_cvtsi128_si32(_mm_shuffle_epi32(v17, 229))) {\n *(uint64_t *)v15 = __ROL8__(*(uint64_t *)v15, 32);\n v16->m128i_i64[0] = _mm_shuffle_epi32(v17, 225).m128i_u64[0];\n }\n v16 = (__m128i *)((char *)v16 + 4);\n ++v15;\n } while (v16 != (__m128i *)((char *)v3->m128i_i64 +\n 4 * (unsigned int)(a2 - 2) + 4));\n ++v14;\n } while (a2 != v14);\n }\n }\n free(v3);\n return a1;\n}", + "ida_pseudo_norm": "int *func0(int *a1, int a2) {\n __m128i *v3;\n int *v4;\n __m128i *v5;\n long long v6;\n unsigned int v7;\n char *v8;\n char *v9;\n int v10;\n int v11;\n int v12;\n int v13;\n int v14;\n int *v15;\n __m128i *v16;\n __m128i v17;\n int *v19;\n char s;\n uint8_t v21[11];\n unsigned long long v22;\n v22 = __readfsqword(40u);\n v3 = (__m128i *)malloc(4LL * a2);\n if (a2 > 0) {\n v4 = a1;\n v5 = v3;\n v19 = &a1[a2];\n do {\n v6 = (unsigned int)-*v4;\n if (*v4 > 0) v6 = (unsigned int)*v4;\n __sprintf_chk(&s, 2LL, 12LL, &unk_2004, v6);\n v7 = strlen(&s);\n if (v7 <= 1) {\n v10 = 0;\n } else {\n v8 = v21;\n v9 = &v21[(unsigned int)(v7 - 2) + 1];\n v10 = 0;\n do {\n v11 = *v8++;\n v10 = v10 + v11 - 48;\n } while (v8 != v9);\n }\n v12 = s - 48;\n v13 = v10 - v12;\n if (*v4 > 0) v13 = v10 + v12;\n ++v4;\n v5->m128i_i32[0] = v13;\n v5 = (__m128i *)((char *)v5 + 4);\n } while (v4 != v19);\n if (a2 != 1) {\n v14 = 0;\n do {\n v15 = a1;\n v16 = v3;\n do {\n v17 = _mm_loadl_epi64(v16);\n if (_mm_cvtsi128_si32(v17) >\n _mm_cvtsi128_si32(_mm_shuffle_epi32(v17, 229))) {\n *(uint64_t *)v15 = __ROL8__(*(uint64_t *)v15, 32);\n v16->m128i_i64[0] = _mm_shuffle_epi32(v17, 225).m128i_u64[0];\n }\n v16 = (__m128i *)((char *)v16 + 4);\n ++v15;\n } while (v16 != (__m128i *)((char *)v3->m128i_i64 +\n 4 * (unsigned int)(a2 - 2) + 4));\n ++v14;\n } while (a2 != v14);\n }\n }\n free(v3);\n return a1;\n}" + }, + { + "index": "HumanEval-C-145", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "int* func0(int nums[], int size) {\n int* sumdigit = (int*)malloc(size * sizeof(int));\n for (int i = 0; i < size; i++) {\n char w[12];\n sprintf(w, \"%d\", abs(nums[i]));\n int sum = 0, length = strlen(w);\n for (int j = 1; j < length; j++) sum += w[j] - '0';\n if (nums[i] > 0)\n sum += w[0] - '0';\n else\n sum -= w[0] - '0';\n sumdigit[i] = sum;\n }\n int m;\n for (int i = 0; i < size; i++)\n for (int j = 1; j < size; j++)\n if (sumdigit[j - 1] > sumdigit[j]) {\n m = sumdigit[j];\n sumdigit[j] = sumdigit[j - 1];\n sumdigit[j - 1] = m;\n m = nums[j];\n nums[j] = nums[j - 1];\n nums[j - 1] = m;\n }\n free(sumdigit);\n return nums;\n}", + "test": "#include \n#include \n\nint issame(int* a, int* b, int size_a, int size_b) {\n if (size_a != size_b) return 0;\n for (int i = 0; i < size_a; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int test1[] = {1, 11, -1, -11, -12};\n int expected1[] = {-1, -11, 1, -12, 11};\n assert(issame(func0(test1, 5), expected1, 5, 5));\n\n int test2[] = {1234, 423, 463, 145, 2, 423, 423, 53, 6, 37, 3457, 3, 56, 0, 46};\n int expected2[] = {0, 2, 3, 6, 53, 423, 423, 423, 1234, 145, 37, 46, 56, 463, 3457};\n assert(issame(func0(test2, 15), expected2, 15, 15));\n\n int test3[] = {};\n int expected3[] = {};\n assert(issame(func0(test3, 0), expected3, 0, 0));\n\n int test4[] = {1, -11, -32, 43, 54, -98, 2, -3};\n int expected4[] = {-3, -32, -98, -11, 1, 2, 43, 54};\n assert(issame(func0(test4, 8), expected4, 8, 8));\n\n int test5[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11};\n int expected5[] = {1, 10, 2, 11, 3, 4, 5, 6, 7, 8, 9};\n assert(issame(func0(test5, 11), expected5, 11, 11));\n\n int test6[] = {0, 6, 6, -76, -21, 23, 4};\n int expected6[] = {-76, -21, 0, 4, 23, 6, 6};\n assert(issame(func0(test6, 7), expected6, 7, 7));\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmovsxd r14, esi\npush r13\npush r12\nmov r12, rdi\npush rbp\nmov rbp, r14\nshl r14, 2\npush rbx\nmov rdi, r14; size\nsub rsp, 38h\nmov rax, fs:28h\nmov [rsp+68h+var_40], rax\nxor eax, eax\ncall _malloc\nmov r13, rax\ntest ebp, ebp\njle loc_1828\nlea rax, [r14+r12]\nmov r15, r12\nlea rbx, [rsp+68h+s]\nmov r14, r13\nmov [rsp+68h+var_60], rax\njmp loc_1779\nloc_1660:\nlea eax, [rax-2]\ncmp eax, 6\njbe loc_1852\nmovq xmm1, [rsp+68h+var_4F]\npxor xmm2, xmm2\npcmpgtb xmm2, xmm1\nmovdqa xmm0, xmm1\npunpcklbw xmm0, xmm2\npunpcklbw xmm1, xmm2\npxor xmm2, xmm2\npaddw xmm0, xmm4\nmovdqa xmm3, xmm2\npshufd xmm1, xmm1, 4Eh ; 'N'\npaddw xmm1, xmm4\npcmpgtw xmm3, xmm0\nmovdqa xmm5, xmm0\npcmpgtw xmm2, xmm1\npunpcklwd xmm0, xmm3\npunpcklwd xmm5, xmm3\nmovdqa xmm3, xmm1\npshufd xmm0, xmm0, 4Eh ; 'N'\npunpcklwd xmm3, xmm2\npunpcklwd xmm1, xmm2\npaddd xmm0, xmm5\npshufd xmm1, xmm1, 4Eh ; 'N'\npaddd xmm0, xmm3\npaddd xmm0, xmm1\nmovd ecx, xmm0\npshufd xmm7, xmm0, 0E5h\nmovd eax, xmm7\nadd eax, ecx\nmov ecx, 9\ncmp edx, 9\njz short loc_1751\nloc_16EA:\nmovsxd rsi, ecx\nmovsx esi, [rsp+rsi+68h+s]\nlea eax, [rax+rsi-30h]\nlea esi, [rcx+1]\ncmp edx, esi\njle short loc_1751\nmovsxd rsi, esi\nadd ecx, 2\nmovsx esi, [rsp+rsi+68h+s]\nlea eax, [rax+rsi-30h]\ncmp edx, ecx\njle short loc_1751\nmovsx ecx, byte ptr [rsp+68h+var_4F+2]\nlea eax, [rax+rcx-30h]\ncmp edx, 4\njz short loc_1751\nmovsx ecx, byte ptr [rsp+68h+var_4F+3]\nlea eax, [rax+rcx-30h]\ncmp edx, 5\njz short loc_1751\nmovsx ecx, byte ptr [rsp+68h+var_4F+4]\nlea eax, [rax+rcx-30h]\ncmp edx, 6\njz short loc_1751\nmovsx ecx, byte ptr [rsp+68h+var_4F+5]\nlea eax, [rax+rcx-30h]\ncmp edx, 7\njz short loc_1751\nmovsx edx, byte ptr [rsp+68h+var_4F+6]\nlea eax, [rax+rdx-30h]\nloc_1751:\nmovsx edx, [rsp+68h+s]\nmov esi, [r15]\nmov ecx, eax\nsub edx, 30h ; '0'\nsub ecx, edx\ntest esi, esi\njle short loc_1767\nlea ecx, [rax+rdx]\nloc_1767:\nmov [r14], ecx\nadd r15, 4\nadd r14, 4\ncmp [rsp+68h+var_60], r15\njz short loc_17C8\nloc_1779:\nmov eax, [r15]\nmov edx, 0Ch\nmov esi, 2\nmov rdi, rbx\nlea rcx, unk_2004\nmov r8d, eax\nneg r8d\ncmovs r8d, eax\nxor eax, eax\ncall ___sprintf_chk\nmov rdi, rbx; s\ncall _strlen\nmovq xmm4, cs:qword_2160\ncmp rax, 1\nmov rdx, rax\nja loc_1660\nxor eax, eax\njmp short loc_1751\nloc_17C8:\ncmp ebp, 1\njz short loc_1828\nlea eax, [rbp-2]\nxor r8d, r8d\nlea rdi, [r13+rax*4+4]\nnop dword ptr [rax+rax+00000000h]\nloc_17E0:\nmov rdx, r12\nmov rax, r13\nnop word ptr [rax+rax+00000000h]\nloc_17F0:\nmovq xmm0, qword ptr [rax]\npshufd xmm6, xmm0, 0E5h\nmovd esi, xmm0\nmovd ecx, xmm6\ncmp esi, ecx\njle short loc_1812\npshufd xmm0, xmm0, 0E1h\nrol qword ptr [rdx], 20h\nmovq qword ptr [rax], xmm0\nloc_1812:\nadd rax, 4\nadd rdx, 4\ncmp rdi, rax\njnz short loc_17F0\nadd r8d, 1\ncmp ebp, r8d\njnz short loc_17E0\nloc_1828:\nmov rdi, r13; ptr\ncall _free\nmov rax, [rsp+68h+var_40]\nsub rax, fs:28h\njnz short loc_185E\nadd rsp, 38h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1852:\nmov ecx, 1\nxor eax, eax\njmp loc_16EA\nloc_185E:\ncall ___stack_chk_fail", + "ida_pseudo": "int *__fastcall func0(int *a1, int a2)\n{\n __m128i *v2; // r13\n int *v3; // r15\n __m128i *v4; // r14\n __m128i v5; // xmm1\n __m128i v6; // xmm1\n __m128i v7; // xmm0\n __m128i v8; // xmm1\n __m128i v9; // xmm5\n __m128i v10; // xmm3\n __m128i v11; // xmm0\n int v12; // eax\n int v13; // ecx\n int v14; // edx\n int v15; // ecx\n __int64 v16; // r8\n size_t v17; // rax\n __m128i v18; // xmm4\n int v19; // edx\n int i; // r8d\n int *v21; // rdx\n __m128i *v22; // rax\n __m128i v23; // xmm0\n char s; // [rsp+18h] [rbp-50h] BYREF\n _BYTE v26[15]; // [rsp+19h] [rbp-4Fh] BYREF\n unsigned __int64 v27; // [rsp+28h] [rbp-40h]\n\n v27 = __readfsqword(0x28u);\n v2 = (__m128i *)malloc(4LL * a2);\n if ( a2 <= 0 )\n goto LABEL_26;\n v3 = a1;\n v4 = v2;\n do\n {\n v16 = (unsigned int)-*v3;\n if ( *v3 > 0 )\n v16 = (unsigned int)*v3;\n __sprintf_chk(&s, 2LL, 12LL, &unk_2004, v16);\n v17 = strlen(&s);\n v18 = _mm_loadl_epi64((const __m128i *)&qword_2160);\n v19 = v17;\n if ( v17 > 1 )\n {\n if ( (unsigned int)(v17 - 2) <= 6 )\n {\n v13 = 1;\n v12 = 0;\n }\n else\n {\n v5 = _mm_loadl_epi64((const __m128i *)v26);\n v6 = _mm_unpacklo_epi8(v5, _mm_cmpgt_epi8((__m128i)0LL, v5));\n v7 = _mm_add_epi16(v6, v18);\n v8 = _mm_add_epi16(_mm_shuffle_epi32(v6, 78), v18);\n v9 = _mm_unpacklo_epi16(v7, _mm_cmpgt_epi16((__m128i)0LL, v7));\n v10 = _mm_unpacklo_epi16(v8, _mm_cmpgt_epi16((__m128i)0LL, v8));\n v11 = _mm_add_epi32(\n _mm_add_epi32(_mm_add_epi32(_mm_shuffle_epi32(v9, 78), v9), v10),\n _mm_shuffle_epi32(v10, 78));\n v12 = _mm_cvtsi128_si32(v11) + _mm_cvtsi128_si32(_mm_shuffle_epi32(v11, 229));\n v13 = 9;\n if ( v19 == 9 )\n goto LABEL_12;\n }\n v12 = v12 + v26[v13 - 1] - 48;\n if ( v19 > v13 + 1 )\n {\n v12 = v12 + v26[v13] - 48;\n if ( v19 > v13 + 2 )\n {\n v12 = v12 + v26[2] - 48;\n if ( v19 != 4 )\n {\n v12 = v12 + v26[3] - 48;\n if ( v19 != 5 )\n {\n v12 = v12 + v26[4] - 48;\n if ( v19 != 6 )\n {\n v12 = v12 + v26[5] - 48;\n if ( v19 != 7 )\n v12 = v12 + v26[6] - 48;\n }\n }\n }\n }\n }\n }\n else\n {\n v12 = 0;\n }\nLABEL_12:\n v14 = s - 48;\n v15 = v12 - v14;\n if ( *v3 > 0 )\n v15 = v12 + v14;\n v4->m128i_i32[0] = v15;\n ++v3;\n v4 = (__m128i *)((char *)v4 + 4);\n }\n while ( &a1[a2] != v3 );\n if ( a2 != 1 )\n {\n for ( i = 0; i != a2; ++i )\n {\n v21 = a1;\n v22 = v2;\n do\n {\n v23 = _mm_loadl_epi64(v22);\n if ( _mm_cvtsi128_si32(v23) > _mm_cvtsi128_si32(_mm_shuffle_epi32(v23, 229)) )\n {\n *(_QWORD *)v21 = __ROL8__(*(_QWORD *)v21, 32);\n v22->m128i_i64[0] = _mm_shuffle_epi32(v23, 225).m128i_u64[0];\n }\n v22 = (__m128i *)((char *)v22 + 4);\n ++v21;\n }\n while ( (__m128i *)((char *)v2->m128i_i64 + 4 * (unsigned int)(a2 - 2) + 4) != v22 );\n }\n }\nLABEL_26:\n free(v2);\n return a1;\n}", + "ida_strip_asm": "sub_1600:\nendbr64\npush r15\npush r14\nmovsxd r14, esi\npush r13\npush r12\nmov r12, rdi\npush rbp\nmov rbp, r14\nshl r14, 2\npush rbx\nmov rdi, r14; size\nsub rsp, 38h\nmov rax, fs:28h\nmov [rsp+68h+var_40], rax\nxor eax, eax\ncall _malloc\nmov r13, rax\ntest ebp, ebp\njle loc_1828\nlea rax, [r14+r12]\nmov r15, r12\nlea rbx, [rsp+68h+s]\nmov r14, r13\nmov [rsp+68h+var_60], rax\njmp loc_1779\nloc_1660:\nlea eax, [rax-2]\ncmp eax, 6\njbe loc_1852\nmovq xmm1, [rsp+68h+var_4F]\npxor xmm2, xmm2\npcmpgtb xmm2, xmm1\nmovdqa xmm0, xmm1\npunpcklbw xmm0, xmm2\npunpcklbw xmm1, xmm2\npxor xmm2, xmm2\npaddw xmm0, xmm4\nmovdqa xmm3, xmm2\npshufd xmm1, xmm1, 4Eh ; 'N'\npaddw xmm1, xmm4\npcmpgtw xmm3, xmm0\nmovdqa xmm5, xmm0\npcmpgtw xmm2, xmm1\npunpcklwd xmm0, xmm3\npunpcklwd xmm5, xmm3\nmovdqa xmm3, xmm1\npshufd xmm0, xmm0, 4Eh ; 'N'\npunpcklwd xmm3, xmm2\npunpcklwd xmm1, xmm2\npaddd xmm0, xmm5\npshufd xmm1, xmm1, 4Eh ; 'N'\npaddd xmm0, xmm3\npaddd xmm0, xmm1\nmovd ecx, xmm0\npshufd xmm7, xmm0, 0E5h\nmovd eax, xmm7\nadd eax, ecx\nmov ecx, 9\ncmp edx, 9\njz short loc_1751\nloc_16EA:\nmovsxd rsi, ecx\nmovsx esi, [rsp+rsi+68h+s]\nlea eax, [rax+rsi-30h]\nlea esi, [rcx+1]\ncmp edx, esi\njle short loc_1751\nmovsxd rsi, esi\nadd ecx, 2\nmovsx esi, [rsp+rsi+68h+s]\nlea eax, [rax+rsi-30h]\ncmp edx, ecx\njle short loc_1751\nmovsx ecx, byte ptr [rsp+68h+var_4F+2]\nlea eax, [rax+rcx-30h]\ncmp edx, 4\njz short loc_1751\nmovsx ecx, byte ptr [rsp+68h+var_4F+3]\nlea eax, [rax+rcx-30h]\ncmp edx, 5\njz short loc_1751\nmovsx ecx, byte ptr [rsp+68h+var_4F+4]\nlea eax, [rax+rcx-30h]\ncmp edx, 6\njz short loc_1751\nmovsx ecx, byte ptr [rsp+68h+var_4F+5]\nlea eax, [rax+rcx-30h]\ncmp edx, 7\njz short loc_1751\nmovsx edx, byte ptr [rsp+68h+var_4F+6]\nlea eax, [rax+rdx-30h]\nloc_1751:\nmovsx edx, [rsp+68h+s]\nmov esi, [r15]\nmov ecx, eax\nsub edx, 30h ; '0'\nsub ecx, edx\ntest esi, esi\njle short loc_1767\nlea ecx, [rax+rdx]\nloc_1767:\nmov [r14], ecx\nadd r15, 4\nadd r14, 4\ncmp [rsp+68h+var_60], r15\njz short loc_17C8\nloc_1779:\nmov eax, [r15]\nmov edx, 0Ch\nmov esi, 2\nmov rdi, rbx\nlea rcx, unk_2004\nmov r8d, eax\nneg r8d\ncmovs r8d, eax\nxor eax, eax\ncall ___sprintf_chk\nmov rdi, rbx; s\ncall _strlen\nmovq xmm4, cs:qword_2160\ncmp rax, 1\nmov rdx, rax\nja loc_1660\nxor eax, eax\njmp short loc_1751\nloc_17C8:\ncmp ebp, 1\njz short loc_1828\nlea eax, [rbp-2]\nxor r8d, r8d\nlea rdi, [r13+rax*4+4]\nnop dword ptr [rax+rax+00000000h]\nloc_17E0:\nmov rdx, r12\nmov rax, r13\nnop word ptr [rax+rax+00000000h]\nloc_17F0:\nmovq xmm0, qword ptr [rax]\npshufd xmm6, xmm0, 0E5h\nmovd esi, xmm0\nmovd ecx, xmm6\ncmp esi, ecx\njle short loc_1812\npshufd xmm0, xmm0, 0E1h\nrol qword ptr [rdx], 20h\nmovq qword ptr [rax], xmm0\nloc_1812:\nadd rax, 4\nadd rdx, 4\ncmp rdi, rax\njnz short loc_17F0\nadd r8d, 1\ncmp ebp, r8d\njnz short loc_17E0\nloc_1828:\nmov rdi, r13; ptr\ncall _free\nmov rax, [rsp+68h+var_40]\nsub rax, fs:28h\njnz short loc_185E\nadd rsp, 38h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1852:\nmov ecx, 1\nxor eax, eax\njmp loc_16EA\nloc_185E:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "int *__fastcall sub_1600(int *a1, int a2)\n{\n __m128i *v2; // r13\n int *v3; // r15\n __m128i *v4; // r14\n __m128i v5; // xmm1\n __m128i v6; // xmm1\n __m128i v7; // xmm0\n __m128i v8; // xmm1\n __m128i v9; // xmm5\n __m128i v10; // xmm3\n __m128i v11; // xmm0\n int v12; // eax\n int v13; // ecx\n int v14; // edx\n int v15; // ecx\n __int64 v16; // r8\n size_t v17; // rax\n __m128i v18; // xmm4\n int v19; // edx\n int i; // r8d\n int *v21; // rdx\n __m128i *v22; // rax\n __m128i v23; // xmm0\n char s; // [rsp+18h] [rbp-50h] BYREF\n _BYTE v26[15]; // [rsp+19h] [rbp-4Fh] BYREF\n unsigned __int64 v27; // [rsp+28h] [rbp-40h]\n\n v27 = __readfsqword(0x28u);\n v2 = (__m128i *)malloc(4LL * a2);\n if ( a2 <= 0 )\n goto LABEL_26;\n v3 = a1;\n v4 = v2;\n do\n {\n v16 = (unsigned int)-*v3;\n if ( *v3 > 0 )\n v16 = (unsigned int)*v3;\n __sprintf_chk(&s, 2LL, 12LL, &unk_2004, v16);\n v17 = strlen(&s);\n v18 = _mm_loadl_epi64((const __m128i *)&qword_2160);\n v19 = v17;\n if ( v17 > 1 )\n {\n if ( (unsigned int)(v17 - 2) <= 6 )\n {\n v13 = 1;\n v12 = 0;\n }\n else\n {\n v5 = _mm_loadl_epi64((const __m128i *)v26);\n v6 = _mm_unpacklo_epi8(v5, _mm_cmpgt_epi8((__m128i)0LL, v5));\n v7 = _mm_add_epi16(v6, v18);\n v8 = _mm_add_epi16(_mm_shuffle_epi32(v6, 78), v18);\n v9 = _mm_unpacklo_epi16(v7, _mm_cmpgt_epi16((__m128i)0LL, v7));\n v10 = _mm_unpacklo_epi16(v8, _mm_cmpgt_epi16((__m128i)0LL, v8));\n v11 = _mm_add_epi32(\n _mm_add_epi32(_mm_add_epi32(_mm_shuffle_epi32(v9, 78), v9), v10),\n _mm_shuffle_epi32(v10, 78));\n v12 = _mm_cvtsi128_si32(v11) + _mm_cvtsi128_si32(_mm_shuffle_epi32(v11, 229));\n v13 = 9;\n if ( v19 == 9 )\n goto LABEL_12;\n }\n v12 = v12 + v26[v13 - 1] - 48;\n if ( v19 > v13 + 1 )\n {\n v12 = v12 + v26[v13] - 48;\n if ( v19 > v13 + 2 )\n {\n v12 = v12 + v26[2] - 48;\n if ( v19 != 4 )\n {\n v12 = v12 + v26[3] - 48;\n if ( v19 != 5 )\n {\n v12 = v12 + v26[4] - 48;\n if ( v19 != 6 )\n {\n v12 = v12 + v26[5] - 48;\n if ( v19 != 7 )\n v12 = v12 + v26[6] - 48;\n }\n }\n }\n }\n }\n }\n else\n {\n v12 = 0;\n }\nLABEL_12:\n v14 = s - 48;\n v15 = v12 - v14;\n if ( *v3 > 0 )\n v15 = v12 + v14;\n v4->m128i_i32[0] = v15;\n ++v3;\n v4 = (__m128i *)((char *)v4 + 4);\n }\n while ( &a1[a2] != v3 );\n if ( a2 != 1 )\n {\n for ( i = 0; i != a2; ++i )\n {\n v21 = a1;\n v22 = v2;\n do\n {\n v23 = _mm_loadl_epi64(v22);\n if ( _mm_cvtsi128_si32(v23) > _mm_cvtsi128_si32(_mm_shuffle_epi32(v23, 229)) )\n {\n *(_QWORD *)v21 = __ROL8__(*(_QWORD *)v21, 32);\n v22->m128i_i64[0] = _mm_shuffle_epi32(v23, 225).m128i_u64[0];\n }\n v22 = (__m128i *)((char *)v22 + 4);\n ++v21;\n }\n while ( (__m128i *)((char *)v2->m128i_i64 + 4 * (unsigned int)(a2 - 2) + 4) != v22 );\n }\n }\nLABEL_26:\n free(v2);\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "int *sub_1600(int *a1, int a2) {\n __m128i *v2;\n int *v3;\n __m128i *v4;\n __m128i v5;\n __m128i v6;\n __m128i v7;\n __m128i v8;\n __m128i v9;\n __m128i v10;\n __m128i v11;\n int v12;\n int v13;\n int v14;\n int v15;\n long long v16;\n unsigned int v17;\n __m128i v18;\n int v19;\n int i;\n int *v21;\n __m128i *v22;\n __m128i v23;\n char s;\n uint8_t v26[15];\n unsigned long long v27;\n v27 = __readfsqword(40u);\n v2 = (__m128i *)malloc(4LL * a2);\n if (a2 <= 0) goto LABEL_26;\n v3 = a1;\n v4 = v2;\n do {\n v16 = (unsigned int)-*v3;\n if (*v3 > 0) v16 = (unsigned int)*v3;\n __sprintf_chk(&s, 2LL, 12LL, &unk_2004, v16);\n v17 = strlen(&s);\n v18 = _mm_loadl_epi64((const __m128i *)&qword_2160);\n v19 = v17;\n if (v17 > 1) {\n if ((unsigned int)(v17 - 2) <= 6) {\n v13 = 1;\n v12 = 0;\n } else {\n v5 = _mm_loadl_epi64((const __m128i *)v26);\n v6 = _mm_unpacklo_epi8(v5, _mm_cmpgt_epi8((__m128i)0LL, v5));\n v7 = _mm_add_epi16(v6, v18);\n v8 = _mm_add_epi16(_mm_shuffle_epi32(v6, 78), v18);\n v9 = _mm_unpacklo_epi16(v7, _mm_cmpgt_epi16((__m128i)0LL, v7));\n v10 = _mm_unpacklo_epi16(v8, _mm_cmpgt_epi16((__m128i)0LL, v8));\n v11 = _mm_add_epi32(\n _mm_add_epi32(_mm_add_epi32(_mm_shuffle_epi32(v9, 78), v9), v10),\n _mm_shuffle_epi32(v10, 78));\n v12 = _mm_cvtsi128_si32(v11) +\n _mm_cvtsi128_si32(_mm_shuffle_epi32(v11, 229));\n v13 = 9;\n if (v19 == 9) goto LABEL_12;\n }\n v12 = v12 + v26[v13 - 1] - 48;\n if (v19 > v13 + 1) {\n v12 = v12 + v26[v13] - 48;\n if (v19 > v13 + 2) {\n v12 = v12 + v26[2] - 48;\n if (v19 != 4) {\n v12 = v12 + v26[3] - 48;\n if (v19 != 5) {\n v12 = v12 + v26[4] - 48;\n if (v19 != 6) {\n v12 = v12 + v26[5] - 48;\n if (v19 != 7) v12 = v12 + v26[6] - 48;\n }\n }\n }\n }\n }\n } else {\n v12 = 0;\n }\n LABEL_12:\n v14 = s - 48;\n v15 = v12 - v14;\n if (*v3 > 0) v15 = v12 + v14;\n v4->m128i_i32[0] = v15;\n ++v3;\n v4 = (__m128i *)((char *)v4 + 4);\n } while (&a1[a2] != v3);\n if (a2 != 1) {\n for (i = 0; i != a2; ++i) {\n v21 = a1;\n v22 = v2;\n do {\n v23 = _mm_loadl_epi64(v22);\n if (_mm_cvtsi128_si32(v23) >\n _mm_cvtsi128_si32(_mm_shuffle_epi32(v23, 229))) {\n *(uint64_t *)v21 = __ROL8__(*(uint64_t *)v21, 32);\n v22->m128i_i64[0] = _mm_shuffle_epi32(v23, 225).m128i_u64[0];\n }\n v22 = (__m128i *)((char *)v22 + 4);\n ++v21;\n } while ((__m128i *)((char *)v2->m128i_i64 + 4 * (unsigned int)(a2 - 2) +\n 4) != v22);\n }\n }\nLABEL_26:\n free(v2);\n return a1;\n}", + "ida_pseudo_norm": "int *func0(int *a1, int a2) {\n __m128i *v2;\n int *v3;\n __m128i *v4;\n __m128i v5;\n __m128i v6;\n __m128i v7;\n __m128i v8;\n __m128i v9;\n __m128i v10;\n __m128i v11;\n int v12;\n int v13;\n int v14;\n int v15;\n long long v16;\n unsigned int v17;\n __m128i v18;\n int v19;\n int i;\n int *v21;\n __m128i *v22;\n __m128i v23;\n char s;\n uint8_t v26[15];\n unsigned long long v27;\n v27 = __readfsqword(40u);\n v2 = (__m128i *)malloc(4LL * a2);\n if (a2 <= 0) goto LABEL_26;\n v3 = a1;\n v4 = v2;\n do {\n v16 = (unsigned int)-*v3;\n if (*v3 > 0) v16 = (unsigned int)*v3;\n __sprintf_chk(&s, 2LL, 12LL, &unk_2004, v16);\n v17 = strlen(&s);\n v18 = _mm_loadl_epi64((const __m128i *)&qword_2160);\n v19 = v17;\n if (v17 > 1) {\n if ((unsigned int)(v17 - 2) <= 6) {\n v13 = 1;\n v12 = 0;\n } else {\n v5 = _mm_loadl_epi64((const __m128i *)v26);\n v6 = _mm_unpacklo_epi8(v5, _mm_cmpgt_epi8((__m128i)0LL, v5));\n v7 = _mm_add_epi16(v6, v18);\n v8 = _mm_add_epi16(_mm_shuffle_epi32(v6, 78), v18);\n v9 = _mm_unpacklo_epi16(v7, _mm_cmpgt_epi16((__m128i)0LL, v7));\n v10 = _mm_unpacklo_epi16(v8, _mm_cmpgt_epi16((__m128i)0LL, v8));\n v11 = _mm_add_epi32(\n _mm_add_epi32(_mm_add_epi32(_mm_shuffle_epi32(v9, 78), v9), v10),\n _mm_shuffle_epi32(v10, 78));\n v12 = _mm_cvtsi128_si32(v11) +\n _mm_cvtsi128_si32(_mm_shuffle_epi32(v11, 229));\n v13 = 9;\n if (v19 == 9) goto LABEL_12;\n }\n v12 = v12 + v26[v13 - 1] - 48;\n if (v19 > v13 + 1) {\n v12 = v12 + v26[v13] - 48;\n if (v19 > v13 + 2) {\n v12 = v12 + v26[2] - 48;\n if (v19 != 4) {\n v12 = v12 + v26[3] - 48;\n if (v19 != 5) {\n v12 = v12 + v26[4] - 48;\n if (v19 != 6) {\n v12 = v12 + v26[5] - 48;\n if (v19 != 7) v12 = v12 + v26[6] - 48;\n }\n }\n }\n }\n }\n } else {\n v12 = 0;\n }\n LABEL_12:\n v14 = s - 48;\n v15 = v12 - v14;\n if (*v3 > 0) v15 = v12 + v14;\n v4->m128i_i32[0] = v15;\n ++v3;\n v4 = (__m128i *)((char *)v4 + 4);\n } while (&a1[a2] != v3);\n if (a2 != 1) {\n for (i = 0; i != a2; ++i) {\n v21 = a1;\n v22 = v2;\n do {\n v23 = _mm_loadl_epi64(v22);\n if (_mm_cvtsi128_si32(v23) >\n _mm_cvtsi128_si32(_mm_shuffle_epi32(v23, 229))) {\n *(uint64_t *)v21 = __ROL8__(*(uint64_t *)v21, 32);\n v22->m128i_i64[0] = _mm_shuffle_epi32(v23, 225).m128i_u64[0];\n }\n v22 = (__m128i *)((char *)v22 + 4);\n ++v21;\n } while ((__m128i *)((char *)v2->m128i_i64 + 4 * (unsigned int)(a2 - 2) +\n 4) != v22);\n }\n }\nLABEL_26:\n free(v2);\n return a1;\n}" + }, + { + "index": "HumanEval-C-146", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(int nums[], int size) {\n int num = 0;\n for (int i = 0; i < size; i++) {\n if (nums[i] > 10) {\n int first, last;\n last = nums[i] % 10;\n int n = nums[i];\n while (n >= 10) {\n n /= 10;\n }\n first = n;\n if (first % 2 == 1 && last % 2 == 1) {\n num += 1;\n }\n }\n }\n return num;\n}", + "test": "#include \n\nint main() {\n {\n int nums[] = {5, -2, 1, -5};\n assert(func0(nums, sizeof(nums) / sizeof(nums[0])) == 0);\n }\n\n {\n int nums[] = {15, -73, 14, -15};\n assert(func0(nums, sizeof(nums) / sizeof(nums[0])) == 1);\n }\n\n {\n int nums[] = {33, -2, -3, 45, 21, 109};\n assert(func0(nums, sizeof(nums) / sizeof(nums[0])) == 2);\n }\n\n {\n int nums[] = {43, -12, 93, 125, 121, 109};\n assert(func0(nums, sizeof(nums) / sizeof(nums[0])) == 4);\n }\n\n {\n int nums[] = {71, -2, -33, 75, 21, 19};\n assert(func0(nums, sizeof(nums) / sizeof(nums[0])) == 3);\n }\n\n {\n int nums[] = {1};\n assert(func0(nums, sizeof(nums) / sizeof(nums[0])) == 0);\n }\n\n {\n int nums[] = {};\n assert(func0(nums, sizeof(nums) / sizeof(nums[0])) == 0);\n }\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\njmp loc_126B\nloc_118B:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\ncmp eax, 0Ah\njle loc_1267\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmovsxd rax, edx\nimul rax, 66666667h\nshr rax, 20h\nsar eax, 2\nmov ecx, edx\nsar ecx, 1Fh\nsub eax, ecx\nmov [rbp+var_8], eax\nmov ecx, [rbp+var_8]\nmov eax, ecx\nshl eax, 2\nadd eax, ecx\nadd eax, eax\nsub edx, eax\nmov [rbp+var_8], edx\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\njmp short loc_1225\nloc_1207:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_C], eax\nloc_1225:\ncmp [rbp+var_C], 9\njg short loc_1207\nmov eax, [rbp+var_C]\nmov [rbp+var_4], eax\nmov edx, [rbp+var_4]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\ncmp eax, 1\njnz short loc_1267\nmov edx, [rbp+var_8]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\ncmp eax, 1\njnz short loc_1267\nadd [rbp+var_14], 1\nloc_1267:\nadd [rbp+var_10], 1\nloc_126B:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_2C]\njl loc_118B\nmov eax, [rbp+var_14]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+18h] [rbp-14h]\n int i; // [rsp+1Ch] [rbp-10h]\n int j; // [rsp+20h] [rbp-Ch]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(int *)(4LL * i + a1) > 10 )\n {\n for ( j = *(_DWORD *)(4LL * i + a1); j > 9; j /= 10 )\n ;\n if ( j % 2 == 1 && *(_DWORD *)(4LL * i + a1) % 10 % 2 == 1 )\n ++v3;\n }\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\njmp loc_126B\nloc_118B:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\ncmp eax, 0Ah\njle loc_1267\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmovsxd rax, edx\nimul rax, 66666667h\nshr rax, 20h\nsar eax, 2\nmov ecx, edx\nsar ecx, 1Fh\nsub eax, ecx\nmov [rbp+var_8], eax\nmov ecx, [rbp+var_8]\nmov eax, ecx\nshl eax, 2\nadd eax, ecx\nadd eax, eax\nsub edx, eax\nmov [rbp+var_8], edx\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\njmp short loc_1225\nloc_1207:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_C], eax\nloc_1225:\ncmp [rbp+var_C], 9\njg short loc_1207\nmov eax, [rbp+var_C]\nmov [rbp+var_4], eax\nmov edx, [rbp+var_4]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\ncmp eax, 1\njnz short loc_1267\nmov edx, [rbp+var_8]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\ncmp eax, 1\njnz short loc_1267\nadd [rbp+var_14], 1\nloc_1267:\nadd [rbp+var_10], 1\nloc_126B:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_2C]\njl loc_118B\nmov eax, [rbp+var_14]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+18h] [rbp-14h]\n int i; // [rsp+1Ch] [rbp-10h]\n int j; // [rsp+20h] [rbp-Ch]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(int *)(4LL * i + a1) > 10 )\n {\n for ( j = *(_DWORD *)(4LL * i + a1); j > 9; j /= 10 )\n ;\n if ( j % 2 == 1 && *(_DWORD *)(4LL * i + a1) % 10 % 2 == 1 )\n ++v3;\n }\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n unsigned int v3;\n int i;\n int j;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(int *)(4LL * i + a1) > 10) {\n for (j = *(uint32_t *)(4LL * i + a1); j > 9; j /= 10)\n ;\n if (j % 2 == 1 && *(uint32_t *)(4LL * i + a1) % 10 % 2 == 1) ++v3;\n }\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n int j;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(int *)(4LL * i + a1) > 10) {\n for (j = *(uint32_t *)(4LL * i + a1); j > 9; j /= 10)\n ;\n if (j % 2 == 1 && *(uint32_t *)(4LL * i + a1) % 10 % 2 == 1) ++v3;\n }\n }\n return v3;\n}" + }, + { + "index": "HumanEval-C-146", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(int nums[], int size) {\n int num = 0;\n for (int i = 0; i < size; i++) {\n if (nums[i] > 10) {\n int first, last;\n last = nums[i] % 10;\n int n = nums[i];\n while (n >= 10) {\n n /= 10;\n }\n first = n;\n if (first % 2 == 1 && last % 2 == 1) {\n num += 1;\n }\n }\n }\n return num;\n}", + "test": "#include \n\nint main() {\n {\n int nums[] = {5, -2, 1, -5};\n assert(func0(nums, sizeof(nums) / sizeof(nums[0])) == 0);\n }\n\n {\n int nums[] = {15, -73, 14, -15};\n assert(func0(nums, sizeof(nums) / sizeof(nums[0])) == 1);\n }\n\n {\n int nums[] = {33, -2, -3, 45, 21, 109};\n assert(func0(nums, sizeof(nums) / sizeof(nums[0])) == 2);\n }\n\n {\n int nums[] = {43, -12, 93, 125, 121, 109};\n assert(func0(nums, sizeof(nums) / sizeof(nums[0])) == 4);\n }\n\n {\n int nums[] = {71, -2, -33, 75, 21, 19};\n assert(func0(nums, sizeof(nums) / sizeof(nums[0])) == 3);\n }\n\n {\n int nums[] = {1};\n assert(func0(nums, sizeof(nums) / sizeof(nums[0])) == 0);\n }\n\n {\n int nums[] = {};\n assert(func0(nums, sizeof(nums) / sizeof(nums[0])) == 0);\n }\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle loc_11FB\nmov r8, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*4]\nmov r9d, 0\njmp short loc_1190\nloc_1187:\nadd r8, 4\ncmp r8, rdi\njz short loc_1201\nloc_1190:\nmov esi, [r8]\ncmp esi, 0Ah\njle short loc_1187\nmov edx, esi\nloc_119A:\nmov ecx, edx\nmovsxd rax, edx\nimul rax, 66666667h\nsar rax, 22h\nsar edx, 1Fh\nsub eax, edx\nmov edx, eax\ncmp ecx, 63h ; 'c'\njg short loc_119A\nshr edx, 1Fh\nadd eax, edx\nand eax, 1\nsub eax, edx\ncmp eax, 1\njnz short loc_1187\nmovsxd rax, esi\nimul rax, 66666667h\nsar rax, 22h\nmov edx, esi\nsar edx, 1Fh\nsub eax, edx\nlea eax, [rax+rax*4]\nadd eax, eax\nsub esi, eax\nmov eax, esi\nshr eax, 1Fh\nadd esi, eax\nand esi, 1\nsub esi, eax\ncmp esi, 1\nsetz al\nmovzx eax, al\nadd r9d, eax\njmp short loc_1187\nloc_11FB:\nmov r9d, 0\nloc_1201:\nmov eax, r9d\nretn", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int *v2; // r8\n int *v3; // rdi\n unsigned int v4; // r9d\n int v5; // edx\n int v6; // ecx\n int v7; // eax\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n {\n if ( *v2 > 10 )\n {\n v5 = *v2;\n do\n {\n v6 = v5;\n v7 = v5 / 10;\n v5 /= 10;\n }\n while ( v6 > 99 );\n if ( (((v5 < 0) + (_BYTE)v7) & 1) - ((unsigned int)v5 >> 31) == 1 )\n v4 += *v2 % 10 % 2 == 1;\n }\n ++v2;\n }\n while ( v2 != v3 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle loc_11FB\nmov r8, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*4]\nmov r9d, 0\njmp short loc_1190\nloc_1187:\nadd r8, 4\ncmp r8, rdi\njz short loc_1201\nloc_1190:\nmov esi, [r8]\ncmp esi, 0Ah\njle short loc_1187\nmov edx, esi\nloc_119A:\nmov ecx, edx\nmovsxd rax, edx\nimul rax, 66666667h\nsar rax, 22h\nsar edx, 1Fh\nsub eax, edx\nmov edx, eax\ncmp ecx, 63h ; 'c'\njg short loc_119A\nshr edx, 1Fh\nadd eax, edx\nand eax, 1\nsub eax, edx\ncmp eax, 1\njnz short loc_1187\nmovsxd rax, esi\nimul rax, 66666667h\nsar rax, 22h\nmov edx, esi\nsar edx, 1Fh\nsub eax, edx\nlea eax, [rax+rax*4]\nadd eax, eax\nsub esi, eax\nmov eax, esi\nshr eax, 1Fh\nadd esi, eax\nand esi, 1\nsub esi, eax\ncmp esi, 1\nsetz al\nmovzx eax, al\nadd r9d, eax\njmp short loc_1187\nloc_11FB:\nmov r9d, 0\nloc_1201:\nmov eax, r9d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int *a1, int a2)\n{\n int *v2; // r8\n int *v3; // rdi\n unsigned int v4; // r9d\n int v5; // edx\n int v6; // ecx\n int v7; // eax\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n {\n if ( *v2 > 10 )\n {\n v5 = *v2;\n do\n {\n v6 = v5;\n v7 = v5 / 10;\n v5 /= 10;\n }\n while ( v6 > 99 );\n if ( (((v5 < 0) + (_BYTE)v7) & 1) - ((unsigned int)v5 >> 31) == 1 )\n v4 += *v2 % 10 % 2 == 1;\n }\n ++v2;\n }\n while ( v2 != v3 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int *a1, int a2) {\n int *v2;\n int *v3;\n unsigned int v4;\n int v5;\n int v6;\n int v7;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do {\n if (*v2 > 10) {\n v5 = *v2;\n do {\n v6 = v5;\n v7 = v5 / 10;\n v5 /= 10;\n } while (v6 > 99);\n if ((((v5 < 0) + (uint8_t)v7) & 1) - ((unsigned int)v5 >> 31) == 1)\n v4 += *v2 % 10 % 2 == 1;\n }\n ++v2;\n } while (v2 != v3);\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int *v2;\n int *v3;\n unsigned int v4;\n int v5;\n int v6;\n int v7;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do {\n if (*v2 > 10) {\n v5 = *v2;\n do {\n v6 = v5;\n v7 = v5 / 10;\n v5 /= 10;\n } while (v6 > 99);\n if ((((v5 < 0) + (uint8_t)v7) & 1) - ((unsigned int)v5 >> 31) == 1)\n v4 += *v2 % 10 % 2 == 1;\n }\n ++v2;\n } while (v2 != v3);\n }\n return v4;\n}" + }, + { + "index": "HumanEval-C-146", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(int nums[], int size) {\n int num = 0;\n for (int i = 0; i < size; i++) {\n if (nums[i] > 10) {\n int first, last;\n last = nums[i] % 10;\n int n = nums[i];\n while (n >= 10) {\n n /= 10;\n }\n first = n;\n if (first % 2 == 1 && last % 2 == 1) {\n num += 1;\n }\n }\n }\n return num;\n}", + "test": "#include \n\nint main() {\n {\n int nums[] = {5, -2, 1, -5};\n assert(func0(nums, sizeof(nums) / sizeof(nums[0])) == 0);\n }\n\n {\n int nums[] = {15, -73, 14, -15};\n assert(func0(nums, sizeof(nums) / sizeof(nums[0])) == 1);\n }\n\n {\n int nums[] = {33, -2, -3, 45, 21, 109};\n assert(func0(nums, sizeof(nums) / sizeof(nums[0])) == 2);\n }\n\n {\n int nums[] = {43, -12, 93, 125, 121, 109};\n assert(func0(nums, sizeof(nums) / sizeof(nums[0])) == 4);\n }\n\n {\n int nums[] = {71, -2, -33, 75, 21, 19};\n assert(func0(nums, sizeof(nums) / sizeof(nums[0])) == 3);\n }\n\n {\n int nums[] = {1};\n assert(func0(nums, sizeof(nums) / sizeof(nums[0])) == 0);\n }\n\n {\n int nums[] = {};\n assert(func0(nums, sizeof(nums) / sizeof(nums[0])) == 0);\n }\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_13E5\nmovsxd rsi, esi\nxor r9d, r9d\nlea r8, [rdi+rsi*4]\nmov esi, 0CCCCCCCDh\njmp short loc_13A9\nloc_13A0:\nadd rdi, 4\ncmp rdi, r8\njz short loc_13E1\nloc_13A9:\nmov ecx, [rdi]\ncmp ecx, 0Ah\njle short loc_13A0\nmov eax, ecx\nnop word ptr [rax+rax+00h]\nloc_13B8:\nmov eax, eax\nmov rdx, rax\nimul rax, rsi\nshr rax, 23h\ncmp edx, 63h ; 'c'\njg short loc_13B8\ntest al, 1\njz short loc_13A0\nand ecx, 1\ncmp ecx, 1\nsbb r9d, 0FFFFFFFFh\nadd rdi, 4\ncmp rdi, r8\njnz short loc_13A9\nloc_13E1:\nmov eax, r9d\nretn\nloc_13E5:\nxor r9d, r9d\nmov eax, r9d\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n unsigned int v2; // r9d\n unsigned int *v3; // r8\n unsigned int v4; // eax\n int v5; // edx\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 0;\n v3 = &a1[a2];\n do\n {\n while ( 1 )\n {\n if ( (int)*a1 > 10 )\n {\n v4 = *a1;\n do\n {\n v5 = v4;\n v4 /= 0xAu;\n }\n while ( v5 > 99 );\n if ( (v4 & 1) != 0 )\n break;\n }\n if ( ++a1 == v3 )\n return v2;\n }\n v2 -= ((*a1++ & 1) == 0) - 1;\n }\n while ( a1 != v3 );\n return v2;\n}", + "ida_strip_asm": "sub_1380:\nendbr64\ntest esi, esi\njle short loc_13E5\nmovsxd rsi, esi\nxor r9d, r9d\nlea r8, [rdi+rsi*4]\nmov esi, 0CCCCCCCDh\njmp short loc_13A9\nloc_13A0:\nadd rdi, 4\ncmp rdi, r8\njz short loc_13E1\nloc_13A9:\nmov ecx, [rdi]\ncmp ecx, 0Ah\njle short loc_13A0\nmov eax, ecx\nnop word ptr [rax+rax+00h]\nloc_13B8:\nmov eax, eax\nmov rdx, rax\nimul rax, rsi\nshr rax, 23h\ncmp edx, 63h ; 'c'\njg short loc_13B8\ntest al, 1\njz short loc_13A0\nand ecx, 1\ncmp ecx, 1\nsbb r9d, 0FFFFFFFFh\nadd rdi, 4\ncmp rdi, r8\njnz short loc_13A9\nloc_13E1:\nmov eax, r9d\nretn\nloc_13E5:\nxor r9d, r9d\nmov eax, r9d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1380(unsigned int *a1, int a2)\n{\n unsigned int v2; // r9d\n unsigned int *v3; // r8\n unsigned int v4; // eax\n int v5; // edx\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 0;\n v3 = &a1[a2];\n do\n {\n while ( 1 )\n {\n if ( (int)*a1 > 10 )\n {\n v4 = *a1;\n do\n {\n v5 = v4;\n v4 /= 0xAu;\n }\n while ( v5 > 99 );\n if ( (v4 & 1) != 0 )\n break;\n }\n if ( ++a1 == v3 )\n return v2;\n }\n v2 -= ((*a1++ & 1) == 0) - 1;\n }\n while ( a1 != v3 );\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1380(unsigned int *a1, int a2) {\n unsigned int v2;\n unsigned int *v3;\n unsigned int v4;\n int v5;\n if (a2 <= 0) return 0LL;\n v2 = 0;\n v3 = &a1[a2];\n do {\n while (1) {\n if ((int)*a1 > 10) {\n v4 = *a1;\n do {\n v5 = v4;\n v4 /= 10u;\n } while (v5 > 99);\n if ((v4 & 1) != 0) break;\n }\n if (++a1 == v3) return v2;\n }\n v2 -= ((*a1++ & 1) == 0) - 1;\n } while (a1 != v3);\n return v2;\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n unsigned int v2;\n unsigned int *v3;\n unsigned int v4;\n int v5;\n if (a2 <= 0) return 0LL;\n v2 = 0;\n v3 = &a1[a2];\n do {\n while (1) {\n if ((int)*a1 > 10) {\n v4 = *a1;\n do {\n v5 = v4;\n v4 /= 10u;\n } while (v5 > 99);\n if ((v4 & 1) != 0) break;\n }\n if (++a1 == v3) return v2;\n }\n v2 -= ((*a1++ & 1) == 0) - 1;\n } while (a1 != v3);\n return v2;\n}" + }, + { + "index": "HumanEval-C-146", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(int nums[], int size) {\n int num = 0;\n for (int i = 0; i < size; i++) {\n if (nums[i] > 10) {\n int first, last;\n last = nums[i] % 10;\n int n = nums[i];\n while (n >= 10) {\n n /= 10;\n }\n first = n;\n if (first % 2 == 1 && last % 2 == 1) {\n num += 1;\n }\n }\n }\n return num;\n}", + "test": "#include \n\nint main() {\n {\n int nums[] = {5, -2, 1, -5};\n assert(func0(nums, sizeof(nums) / sizeof(nums[0])) == 0);\n }\n\n {\n int nums[] = {15, -73, 14, -15};\n assert(func0(nums, sizeof(nums) / sizeof(nums[0])) == 1);\n }\n\n {\n int nums[] = {33, -2, -3, 45, 21, 109};\n assert(func0(nums, sizeof(nums) / sizeof(nums[0])) == 2);\n }\n\n {\n int nums[] = {43, -12, 93, 125, 121, 109};\n assert(func0(nums, sizeof(nums) / sizeof(nums[0])) == 4);\n }\n\n {\n int nums[] = {71, -2, -33, 75, 21, 19};\n assert(func0(nums, sizeof(nums) / sizeof(nums[0])) == 3);\n }\n\n {\n int nums[] = {1};\n assert(func0(nums, sizeof(nums) / sizeof(nums[0])) == 0);\n }\n\n {\n int nums[] = {};\n assert(func0(nums, sizeof(nums) / sizeof(nums[0])) == 0);\n }\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_13E5\nmovsxd rsi, esi\nxor r9d, r9d\nlea r8, [rdi+rsi*4]\nmov esi, 0CCCCCCCDh\njmp short loc_13A9\nloc_13A0:\nadd rdi, 4\ncmp rdi, r8\njz short loc_13E1\nloc_13A9:\nmov ecx, [rdi]\ncmp ecx, 0Ah\njle short loc_13A0\nmov eax, ecx\nnop word ptr [rax+rax+00h]\nloc_13B8:\nmov eax, eax\nmov rdx, rax\nimul rax, rsi\nshr rax, 23h\ncmp edx, 63h ; 'c'\njg short loc_13B8\ntest al, 1\njz short loc_13A0\nand ecx, 1\ncmp ecx, 1\nsbb r9d, 0FFFFFFFFh\nadd rdi, 4\ncmp rdi, r8\njnz short loc_13A9\nloc_13E1:\nmov eax, r9d\nretn\nloc_13E5:\nxor r9d, r9d\nmov eax, r9d\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n unsigned int v2; // r9d\n unsigned int *v3; // r8\n unsigned int v4; // eax\n int v5; // edx\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 0;\n v3 = &a1[a2];\n do\n {\n while ( 1 )\n {\n if ( (int)*a1 > 10 )\n {\n v4 = *a1;\n do\n {\n v5 = v4;\n v4 /= 0xAu;\n }\n while ( v5 > 99 );\n if ( (v4 & 1) != 0 )\n break;\n }\n if ( ++a1 == v3 )\n return v2;\n }\n v2 -= ((*a1++ & 1) == 0) - 1;\n }\n while ( a1 != v3 );\n return v2;\n}", + "ida_strip_asm": "sub_1380:\nendbr64\ntest esi, esi\njle short loc_13E5\nmovsxd rsi, esi\nxor r9d, r9d\nlea r8, [rdi+rsi*4]\nmov esi, 0CCCCCCCDh\njmp short loc_13A9\nloc_13A0:\nadd rdi, 4\ncmp rdi, r8\njz short loc_13E1\nloc_13A9:\nmov ecx, [rdi]\ncmp ecx, 0Ah\njle short loc_13A0\nmov eax, ecx\nnop word ptr [rax+rax+00h]\nloc_13B8:\nmov eax, eax\nmov rdx, rax\nimul rax, rsi\nshr rax, 23h\ncmp edx, 63h ; 'c'\njg short loc_13B8\ntest al, 1\njz short loc_13A0\nand ecx, 1\ncmp ecx, 1\nsbb r9d, 0FFFFFFFFh\nadd rdi, 4\ncmp rdi, r8\njnz short loc_13A9\nloc_13E1:\nmov eax, r9d\nretn\nloc_13E5:\nxor r9d, r9d\nmov eax, r9d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1380(unsigned int *a1, int a2)\n{\n unsigned int v2; // r9d\n unsigned int *v3; // r8\n unsigned int v4; // eax\n int v5; // edx\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 0;\n v3 = &a1[a2];\n do\n {\n while ( 1 )\n {\n if ( (int)*a1 > 10 )\n {\n v4 = *a1;\n do\n {\n v5 = v4;\n v4 /= 0xAu;\n }\n while ( v5 > 99 );\n if ( (v4 & 1) != 0 )\n break;\n }\n if ( ++a1 == v3 )\n return v2;\n }\n v2 -= ((*a1++ & 1) == 0) - 1;\n }\n while ( a1 != v3 );\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1380(unsigned int *a1, int a2) {\n unsigned int v2;\n unsigned int *v3;\n unsigned int v4;\n int v5;\n if (a2 <= 0) return 0LL;\n v2 = 0;\n v3 = &a1[a2];\n do {\n while (1) {\n if ((int)*a1 > 10) {\n v4 = *a1;\n do {\n v5 = v4;\n v4 /= 10u;\n } while (v5 > 99);\n if ((v4 & 1) != 0) break;\n }\n if (++a1 == v3) return v2;\n }\n v2 -= ((*a1++ & 1) == 0) - 1;\n } while (a1 != v3);\n return v2;\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n unsigned int v2;\n unsigned int *v3;\n unsigned int v4;\n int v5;\n if (a2 <= 0) return 0LL;\n v2 = 0;\n v3 = &a1[a2];\n do {\n while (1) {\n if ((int)*a1 > 10) {\n v4 = *a1;\n do {\n v5 = v4;\n v4 /= 10u;\n } while (v5 > 99);\n if ((v4 & 1) != 0) break;\n }\n if (++a1 == v3) return v2;\n }\n v2 -= ((*a1++ & 1) == 0) - 1;\n } while (a1 != v3);\n return v2;\n}" + }, + { + "index": "HumanEval-C-147", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(int n) {\n int *a = (int *)malloc(n * sizeof(int));\n int **sum = (int **)malloc((n + 1) * sizeof(int *));\n int **sum2 = (int **)malloc((n + 1) * sizeof(int *));\n for (int i = 0; i <= n; i++) {\n sum[i] = (int *)calloc(3, sizeof(int));\n sum2[i] = (int *)calloc(3, sizeof(int));\n }\n sum[0][0] = sum[0][1] = sum[0][2] = 0;\n sum2[0][0] = sum2[0][1] = sum2[0][2] = 0;\n for (int i = 1; i <= n; i++) {\n a[i - 1] = (i * i - i + 1) % 3;\n for (int j = 0; j < 3; j++) {\n sum[i][j] = sum[i - 1][j];\n }\n sum[i][a[i - 1]] += 1;\n }\n for (int times = 1; times < 3; times++) {\n for (int i = 1; i <= n; i++) {\n for (int j = 0; j < 3; j++) {\n sum2[i][j] = sum2[i - 1][j];\n }\n if (i >= 1) {\n for (int j = 0; j <= 2; j++) {\n sum2[i][(a[i - 1] + j) % 3] += sum[i - 1][j];\n }\n }\n }\n for (int i = 0; i <= n; i++) {\n for (int j = 0; j < 3; j++) {\n sum[i][j] = sum2[i][j];\n sum2[i][j] = 0;\n }\n }\n }\n int result = sum[n][0];\n for (int i = 0; i <= n; ++i) {\n free(sum[i]);\n free(sum2[i]);\n }\n free(sum);\n free(sum2);\n free(a);\n return result;\n}", + "test": "#include \n\nint main() {\n assert(func0(5) == 1);\n assert(func0(6) == 4);\n assert(func0(10) == 36);\n assert(func0(100) == 53361);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 68h\nmov [rbp+var_64], edi\nmov eax, [rbp+var_64]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_28], rax\nmov eax, [rbp+var_64]\nadd eax, 1\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov eax, [rbp+var_64]\nadd eax, 1\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_54], 0\njmp short loc_1259\nloc_1207:\nmov eax, [rbp+var_54]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nlea rbx, [rdx+rax]\nmov esi, 4; size\nmov edi, 3; nmemb\ncall _calloc\nmov [rbx], rax\nmov eax, [rbp+var_54]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nlea rbx, [rdx+rax]\nmov esi, 4; size\nmov edi, 3; nmemb\ncall _calloc\nmov [rbx], rax\nadd [rbp+var_54], 1\nloc_1259:\nmov eax, [rbp+var_54]\ncmp eax, [rbp+var_64]\njle short loc_1207\nmov rax, [rbp+ptr]\nmov rax, [rax]\nlea rdx, [rax+8]\nmov dword ptr [rdx], 0\nmov rax, [rbp+ptr]\nmov rax, [rax]\nadd rax, 4\nmov edx, [rdx]\nmov [rax], edx\nmov rdx, [rbp+ptr]\nmov rdx, [rdx]\nmov eax, [rax]\nmov [rdx], eax\nmov rax, [rbp+var_18]\nmov rax, [rax]\nlea rdx, [rax+8]\nmov dword ptr [rdx], 0\nmov rax, [rbp+var_18]\nmov rax, [rax]\nadd rax, 4\nmov edx, [rdx]\nmov [rax], edx\nmov rdx, [rbp+var_18]\nmov rdx, [rdx]\nmov eax, [rax]\nmov [rdx], eax\nmov [rbp+var_50], 1\njmp loc_13E3\nloc_12C3:\nmov eax, [rbp+var_50]\nimul eax, eax\nsub eax, [rbp+var_50]\nlea ecx, [rax+1]\nmov eax, [rbp+var_50]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_28]\nlea rsi, [rdx+rax]\nmovsxd rax, ecx\nimul rax, 55555556h\nshr rax, 20h\nmov rdx, rax\nmov eax, ecx\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\nadd eax, eax\nadd eax, edx\nsub ecx, eax\nmov edx, ecx\nmov [rsi], edx\nmov [rbp+var_4C], 0\njmp short loc_1362\nloc_1311:\nmov eax, [rbp+var_50]\ncdqe\nshl rax, 3\nlea rdx, [rax-8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_4C]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov edx, [rbp+var_50]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+ptr]\nadd rdx, rcx\nmov rdx, [rdx]\nmov ecx, [rbp+var_4C]\nmovsxd rcx, ecx\nshl rcx, 2\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_4C], 1\nloc_1362:\ncmp [rbp+var_4C], 2\njle short loc_1311\nmov eax, [rbp+var_50]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_50]\nmovsxd rdx, edx\nshl rdx, 2\nlea rcx, [rdx-4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov edx, [rdx]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_50]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rcx\nmov rax, [rax]\nmov ecx, [rbp+var_50]\nmovsxd rcx, ecx\nshl rcx, 2\nlea rsi, [rcx-4]\nmov rcx, [rbp+var_28]\nadd rcx, rsi\nmov ecx, [rcx]\nmovsxd rcx, ecx\nshl rcx, 2\nadd rax, rcx\nadd edx, 1\nmov [rax], edx\nadd [rbp+var_50], 1\nloc_13E3:\nmov eax, [rbp+var_50]\ncmp eax, [rbp+var_64]\njle loc_12C3\nmov [rbp+var_48], 1\njmp loc_15F3\nloc_13FB:\nmov [rbp+var_44], 1\njmp loc_1539\nloc_1407:\nmov [rbp+var_40], 0\njmp short loc_1461\nloc_1410:\nmov eax, [rbp+var_44]\ncdqe\nshl rax, 3\nlea rdx, [rax-8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_40]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov edx, [rbp+var_44]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov rdx, [rdx]\nmov ecx, [rbp+var_40]\nmovsxd rcx, ecx\nshl rcx, 2\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_40], 1\nloc_1461:\ncmp [rbp+var_40], 2\njle short loc_1410\ncmp [rbp+var_44], 0\njle loc_1535\nmov [rbp+var_3C], 0\njmp loc_152B\nloc_147D:\nmov eax, [rbp+var_44]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rsi, [rax]\nmov eax, [rbp+var_44]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_3C]\nlea ecx, [rdx+rax]\nmovsxd rax, ecx\nimul rax, 55555556h\nshr rax, 20h\nmov edx, ecx\nsar edx, 1Fh\nsub eax, edx\nmov edx, eax\nadd edx, edx\nadd edx, eax\nmov eax, ecx\nsub eax, edx\nmovsxd rdx, eax\nshl rdx, 2\nadd rdx, rsi\nmov ecx, [rdx]\nmov edx, [rbp+var_44]\nmovsxd rdx, edx\nshl rdx, 3\nlea rsi, [rdx-8]\nmov rdx, [rbp+ptr]\nadd rdx, rsi\nmov rdx, [rdx]\nmov esi, [rbp+var_3C]\nmovsxd rsi, esi\nshl rsi, 2\nadd rdx, rsi\nmov edx, [rdx]\nmov esi, [rbp+var_44]\nmovsxd rsi, esi\nlea rdi, ds:0[rsi*8]\nmov rsi, [rbp+var_18]\nadd rsi, rdi\nmov rsi, [rsi]\ncdqe\nshl rax, 2\nadd rax, rsi\nadd edx, ecx\nmov [rax], edx\nadd [rbp+var_3C], 1\nloc_152B:\ncmp [rbp+var_3C], 2\njle loc_147D\nloc_1535:\nadd [rbp+var_44], 1\nloc_1539:\nmov eax, [rbp+var_44]\ncmp eax, [rbp+var_64]\njle loc_1407\nmov [rbp+var_38], 0\njmp loc_15E3\nloc_1551:\nmov [rbp+var_34], 0\njmp short loc_15D5\nloc_155A:\nmov eax, [rbp+var_38]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_34]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+ptr]\nadd rdx, rcx\nmov rdx, [rdx]\nmov ecx, [rbp+var_34]\nmovsxd rcx, ecx\nshl rcx, 2\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_38]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_34]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov dword ptr [rax], 0\nadd [rbp+var_34], 1\nloc_15D5:\ncmp [rbp+var_34], 2\njle loc_155A\nadd [rbp+var_38], 1\nloc_15E3:\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_64]\njle loc_1551\nadd [rbp+var_48], 1\nloc_15F3:\ncmp [rbp+var_48], 2\njle loc_13FB\nmov eax, [rbp+var_64]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rax, [rax]\nmov eax, [rax]\nmov [rbp+var_2C], eax\nmov [rbp+var_30], 0\njmp short loc_1664\nloc_1622:\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; ptr\ncall _free\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; ptr\ncall _free\nadd [rbp+var_30], 1\nloc_1664:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_64]\njle short loc_1622\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_18]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_28]\nmov rdi, rax; ptr\ncall _free\nmov eax, [rbp+var_2C]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n _DWORD *v1; // rdx\n _DWORD *v2; // rax\n _DWORD *v3; // rdx\n _DWORD *v4; // rax\n int v5; // eax\n int i; // [rsp+1Ch] [rbp-54h]\n int j; // [rsp+20h] [rbp-50h]\n int k; // [rsp+24h] [rbp-4Ch]\n int m; // [rsp+28h] [rbp-48h]\n int n; // [rsp+2Ch] [rbp-44h]\n int ii; // [rsp+30h] [rbp-40h]\n int jj; // [rsp+34h] [rbp-3Ch]\n int kk; // [rsp+38h] [rbp-38h]\n int mm; // [rsp+3Ch] [rbp-34h]\n int nn; // [rsp+40h] [rbp-30h]\n unsigned int v17; // [rsp+44h] [rbp-2Ch]\n int *v18; // [rsp+48h] [rbp-28h]\n _QWORD *ptr; // [rsp+50h] [rbp-20h]\n _QWORD *v20; // [rsp+58h] [rbp-18h]\n\n v18 = (int *)malloc(4LL * a1);\n ptr = malloc(8LL * (a1 + 1));\n v20 = malloc(8LL * (a1 + 1));\n for ( i = 0; i <= a1; ++i )\n {\n ptr[i] = calloc(3uLL, 4uLL);\n v20[i] = calloc(3uLL, 4uLL);\n }\n v1 = (_DWORD *)(*ptr + 8LL);\n *v1 = 0;\n v2 = (_DWORD *)(*ptr + 4LL);\n *v2 = *v1;\n *(_DWORD *)*ptr = *v2;\n v3 = (_DWORD *)(*v20 + 8LL);\n *v3 = 0;\n v4 = (_DWORD *)(*v20 + 4LL);\n *v4 = *v3;\n *(_DWORD *)*v20 = *v4;\n for ( j = 1; j <= a1; ++j )\n {\n v18[j - 1] = (j * j - j + 1) % 3;\n for ( k = 0; k <= 2; ++k )\n *(_DWORD *)(4LL * k + ptr[j]) = *(_DWORD *)(4LL * k + ptr[j - 1]);\n ++*(_DWORD *)(4LL * v18[j - 1] + ptr[j]);\n }\n for ( m = 1; m <= 2; ++m )\n {\n for ( n = 1; n <= a1; ++n )\n {\n for ( ii = 0; ii <= 2; ++ii )\n *(_DWORD *)(4LL * ii + v20[n]) = *(_DWORD *)(4LL * ii + v20[n - 1]);\n if ( n > 0 )\n {\n for ( jj = 0; jj <= 2; ++jj )\n {\n v5 = (v18[n - 1] + jj) % 3;\n *(_DWORD *)(v20[n] + 4LL * v5) += *(_DWORD *)(4LL * jj + ptr[n - 1]);\n }\n }\n }\n for ( kk = 0; kk <= a1; ++kk )\n {\n for ( mm = 0; mm <= 2; ++mm )\n {\n *(_DWORD *)(4LL * mm + ptr[kk]) = *(_DWORD *)(4LL * mm + v20[kk]);\n *(_DWORD *)(4LL * mm + v20[kk]) = 0;\n }\n }\n }\n v17 = *(_DWORD *)ptr[a1];\n for ( nn = 0; nn <= a1; ++nn )\n {\n free((void *)ptr[nn]);\n free((void *)v20[nn]);\n }\n free(ptr);\n free(v20);\n free(v18);\n return v17;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 68h\nmov [rbp+var_64], edi\nmov eax, [rbp+var_64]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_28], rax\nmov eax, [rbp+var_64]\nadd eax, 1\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov eax, [rbp+var_64]\nadd eax, 1\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_54], 0\njmp short loc_1259\nloc_1207:\nmov eax, [rbp+var_54]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nlea rbx, [rdx+rax]\nmov esi, 4; size\nmov edi, 3; nmemb\ncall _calloc\nmov [rbx], rax\nmov eax, [rbp+var_54]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nlea rbx, [rdx+rax]\nmov esi, 4; size\nmov edi, 3; nmemb\ncall _calloc\nmov [rbx], rax\nadd [rbp+var_54], 1\nloc_1259:\nmov eax, [rbp+var_54]\ncmp eax, [rbp+var_64]\njle short loc_1207\nmov rax, [rbp+ptr]\nmov rax, [rax]\nlea rdx, [rax+8]\nmov dword ptr [rdx], 0\nmov rax, [rbp+ptr]\nmov rax, [rax]\nadd rax, 4\nmov edx, [rdx]\nmov [rax], edx\nmov rdx, [rbp+ptr]\nmov rdx, [rdx]\nmov eax, [rax]\nmov [rdx], eax\nmov rax, [rbp+var_18]\nmov rax, [rax]\nlea rdx, [rax+8]\nmov dword ptr [rdx], 0\nmov rax, [rbp+var_18]\nmov rax, [rax]\nadd rax, 4\nmov edx, [rdx]\nmov [rax], edx\nmov rdx, [rbp+var_18]\nmov rdx, [rdx]\nmov eax, [rax]\nmov [rdx], eax\nmov [rbp+var_50], 1\njmp loc_13E3\nloc_12C3:\nmov eax, [rbp+var_50]\nimul eax, eax\nsub eax, [rbp+var_50]\nlea ecx, [rax+1]\nmov eax, [rbp+var_50]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_28]\nlea rsi, [rdx+rax]\nmovsxd rax, ecx\nimul rax, 55555556h\nshr rax, 20h\nmov rdx, rax\nmov eax, ecx\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\nadd eax, eax\nadd eax, edx\nsub ecx, eax\nmov edx, ecx\nmov [rsi], edx\nmov [rbp+var_4C], 0\njmp short loc_1362\nloc_1311:\nmov eax, [rbp+var_50]\ncdqe\nshl rax, 3\nlea rdx, [rax-8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_4C]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov edx, [rbp+var_50]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+ptr]\nadd rdx, rcx\nmov rdx, [rdx]\nmov ecx, [rbp+var_4C]\nmovsxd rcx, ecx\nshl rcx, 2\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_4C], 1\nloc_1362:\ncmp [rbp+var_4C], 2\njle short loc_1311\nmov eax, [rbp+var_50]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_50]\nmovsxd rdx, edx\nshl rdx, 2\nlea rcx, [rdx-4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov edx, [rdx]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_50]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rcx\nmov rax, [rax]\nmov ecx, [rbp+var_50]\nmovsxd rcx, ecx\nshl rcx, 2\nlea rsi, [rcx-4]\nmov rcx, [rbp+var_28]\nadd rcx, rsi\nmov ecx, [rcx]\nmovsxd rcx, ecx\nshl rcx, 2\nadd rax, rcx\nadd edx, 1\nmov [rax], edx\nadd [rbp+var_50], 1\nloc_13E3:\nmov eax, [rbp+var_50]\ncmp eax, [rbp+var_64]\njle loc_12C3\nmov [rbp+var_48], 1\njmp loc_15F3\nloc_13FB:\nmov [rbp+var_44], 1\njmp loc_1539\nloc_1407:\nmov [rbp+var_40], 0\njmp short loc_1461\nloc_1410:\nmov eax, [rbp+var_44]\ncdqe\nshl rax, 3\nlea rdx, [rax-8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_40]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov edx, [rbp+var_44]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov rdx, [rdx]\nmov ecx, [rbp+var_40]\nmovsxd rcx, ecx\nshl rcx, 2\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_40], 1\nloc_1461:\ncmp [rbp+var_40], 2\njle short loc_1410\ncmp [rbp+var_44], 0\njle loc_1535\nmov [rbp+var_3C], 0\njmp loc_152B\nloc_147D:\nmov eax, [rbp+var_44]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rsi, [rax]\nmov eax, [rbp+var_44]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_3C]\nlea ecx, [rdx+rax]\nmovsxd rax, ecx\nimul rax, 55555556h\nshr rax, 20h\nmov edx, ecx\nsar edx, 1Fh\nsub eax, edx\nmov edx, eax\nadd edx, edx\nadd edx, eax\nmov eax, ecx\nsub eax, edx\nmovsxd rdx, eax\nshl rdx, 2\nadd rdx, rsi\nmov ecx, [rdx]\nmov edx, [rbp+var_44]\nmovsxd rdx, edx\nshl rdx, 3\nlea rsi, [rdx-8]\nmov rdx, [rbp+ptr]\nadd rdx, rsi\nmov rdx, [rdx]\nmov esi, [rbp+var_3C]\nmovsxd rsi, esi\nshl rsi, 2\nadd rdx, rsi\nmov edx, [rdx]\nmov esi, [rbp+var_44]\nmovsxd rsi, esi\nlea rdi, ds:0[rsi*8]\nmov rsi, [rbp+var_18]\nadd rsi, rdi\nmov rsi, [rsi]\ncdqe\nshl rax, 2\nadd rax, rsi\nadd edx, ecx\nmov [rax], edx\nadd [rbp+var_3C], 1\nloc_152B:\ncmp [rbp+var_3C], 2\njle loc_147D\nloc_1535:\nadd [rbp+var_44], 1\nloc_1539:\nmov eax, [rbp+var_44]\ncmp eax, [rbp+var_64]\njle loc_1407\nmov [rbp+var_38], 0\njmp loc_15E3\nloc_1551:\nmov [rbp+var_34], 0\njmp short loc_15D5\nloc_155A:\nmov eax, [rbp+var_38]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_34]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+ptr]\nadd rdx, rcx\nmov rdx, [rdx]\nmov ecx, [rbp+var_34]\nmovsxd rcx, ecx\nshl rcx, 2\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_38]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_34]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov dword ptr [rax], 0\nadd [rbp+var_34], 1\nloc_15D5:\ncmp [rbp+var_34], 2\njle loc_155A\nadd [rbp+var_38], 1\nloc_15E3:\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_64]\njle loc_1551\nadd [rbp+var_48], 1\nloc_15F3:\ncmp [rbp+var_48], 2\njle loc_13FB\nmov eax, [rbp+var_64]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rax, [rax]\nmov eax, [rax]\nmov [rbp+var_2C], eax\nmov [rbp+var_30], 0\njmp short loc_1664\nloc_1622:\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; ptr\ncall _free\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; ptr\ncall _free\nadd [rbp+var_30], 1\nloc_1664:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_64]\njle short loc_1622\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_18]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_28]\nmov rdi, rax; ptr\ncall _free\nmov eax, [rbp+var_2C]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(int a1)\n{\n _DWORD *v1; // rdx\n _DWORD *v2; // rax\n _DWORD *v3; // rdx\n _DWORD *v4; // rax\n int v5; // eax\n int i; // [rsp+1Ch] [rbp-54h]\n int j; // [rsp+20h] [rbp-50h]\n int k; // [rsp+24h] [rbp-4Ch]\n int m; // [rsp+28h] [rbp-48h]\n int n; // [rsp+2Ch] [rbp-44h]\n int ii; // [rsp+30h] [rbp-40h]\n int jj; // [rsp+34h] [rbp-3Ch]\n int kk; // [rsp+38h] [rbp-38h]\n int mm; // [rsp+3Ch] [rbp-34h]\n int nn; // [rsp+40h] [rbp-30h]\n unsigned int v17; // [rsp+44h] [rbp-2Ch]\n int *v18; // [rsp+48h] [rbp-28h]\n _QWORD *ptr; // [rsp+50h] [rbp-20h]\n _QWORD *v20; // [rsp+58h] [rbp-18h]\n\n v18 = (int *)malloc(4LL * a1);\n ptr = malloc(8LL * (a1 + 1));\n v20 = malloc(8LL * (a1 + 1));\n for ( i = 0; i <= a1; ++i )\n {\n ptr[i] = calloc(3uLL, 4uLL);\n v20[i] = calloc(3uLL, 4uLL);\n }\n v1 = (_DWORD *)(*ptr + 8LL);\n *v1 = 0;\n v2 = (_DWORD *)(*ptr + 4LL);\n *v2 = *v1;\n *(_DWORD *)*ptr = *v2;\n v3 = (_DWORD *)(*v20 + 8LL);\n *v3 = 0;\n v4 = (_DWORD *)(*v20 + 4LL);\n *v4 = *v3;\n *(_DWORD *)*v20 = *v4;\n for ( j = 1; j <= a1; ++j )\n {\n v18[j - 1] = (j * j - j + 1) % 3;\n for ( k = 0; k <= 2; ++k )\n *(_DWORD *)(4LL * k + ptr[j]) = *(_DWORD *)(4LL * k + ptr[j - 1]);\n ++*(_DWORD *)(4LL * v18[j - 1] + ptr[j]);\n }\n for ( m = 1; m <= 2; ++m )\n {\n for ( n = 1; n <= a1; ++n )\n {\n for ( ii = 0; ii <= 2; ++ii )\n *(_DWORD *)(4LL * ii + v20[n]) = *(_DWORD *)(4LL * ii + v20[n - 1]);\n if ( n > 0 )\n {\n for ( jj = 0; jj <= 2; ++jj )\n {\n v5 = (v18[n - 1] + jj) % 3;\n *(_DWORD *)(v20[n] + 4LL * v5) += *(_DWORD *)(4LL * jj + ptr[n - 1]);\n }\n }\n }\n for ( kk = 0; kk <= a1; ++kk )\n {\n for ( mm = 0; mm <= 2; ++mm )\n {\n *(_DWORD *)(4LL * mm + ptr[kk]) = *(_DWORD *)(4LL * mm + v20[kk]);\n *(_DWORD *)(4LL * mm + v20[kk]) = 0;\n }\n }\n }\n v17 = *(_DWORD *)ptr[a1];\n for ( nn = 0; nn <= a1; ++nn )\n {\n free((void *)ptr[nn]);\n free((void *)v20[nn]);\n }\n free(ptr);\n free(v20);\n free(v18);\n return v17;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(int a1) {\n uint32_t *v1;\n uint32_t *v2;\n uint32_t *v3;\n uint32_t *v4;\n int v5;\n int i;\n int j;\n int k;\n int m;\n int n;\n int ii;\n int jj;\n int kk;\n int mm;\n int nn;\n unsigned int v17;\n int *v18;\n uint64_t *ptr;\n uint64_t *v20;\n v18 = (int *)malloc(4LL * a1);\n ptr = malloc(8LL * (a1 + 1));\n v20 = malloc(8LL * (a1 + 1));\n for (i = 0; i <= a1; ++i) {\n ptr[i] = calloc(3uLL, 4uLL);\n v20[i] = calloc(3uLL, 4uLL);\n }\n v1 = (uint32_t *)(*ptr + 8LL);\n *v1 = 0;\n v2 = (uint32_t *)(*ptr + 4LL);\n *v2 = *v1;\n *(uint32_t *)*ptr = *v2;\n v3 = (uint32_t *)(*v20 + 8LL);\n *v3 = 0;\n v4 = (uint32_t *)(*v20 + 4LL);\n *v4 = *v3;\n *(uint32_t *)*v20 = *v4;\n for (j = 1; j <= a1; ++j) {\n v18[j - 1] = (j * j - j + 1) % 3;\n for (k = 0; k <= 2; ++k)\n *(uint32_t *)(4LL * k + ptr[j]) = *(uint32_t *)(4LL * k + ptr[j - 1]);\n ++*(uint32_t *)(4LL * v18[j - 1] + ptr[j]);\n }\n for (m = 1; m <= 2; ++m) {\n for (n = 1; n <= a1; ++n) {\n for (ii = 0; ii <= 2; ++ii)\n *(uint32_t *)(4LL * ii + v20[n]) = *(uint32_t *)(4LL * ii + v20[n - 1]);\n if (n > 0) {\n for (jj = 0; jj <= 2; ++jj) {\n v5 = (v18[n - 1] + jj) % 3;\n *(uint32_t *)(v20[n] + 4LL * v5) +=\n *(uint32_t *)(4LL * jj + ptr[n - 1]);\n }\n }\n }\n for (kk = 0; kk <= a1; ++kk) {\n for (mm = 0; mm <= 2; ++mm) {\n *(uint32_t *)(4LL * mm + ptr[kk]) = *(uint32_t *)(4LL * mm + v20[kk]);\n *(uint32_t *)(4LL * mm + v20[kk]) = 0;\n }\n }\n }\n v17 = *(uint32_t *)ptr[a1];\n for (nn = 0; nn <= a1; ++nn) {\n free((void *)ptr[nn]);\n free((void *)v20[nn]);\n }\n free(ptr);\n free(v20);\n free(v18);\n return v17;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n uint32_t *v1;\n uint32_t *v2;\n uint32_t *v3;\n uint32_t *v4;\n int v5;\n int i;\n int j;\n int k;\n int m;\n int n;\n int ii;\n int jj;\n int kk;\n int mm;\n int nn;\n unsigned int v17;\n int *v18;\n uint64_t *ptr;\n uint64_t *v20;\n v18 = (int *)malloc(4LL * a1);\n ptr = malloc(8LL * (a1 + 1));\n v20 = malloc(8LL * (a1 + 1));\n for (i = 0; i <= a1; ++i) {\n ptr[i] = calloc(3uLL, 4uLL);\n v20[i] = calloc(3uLL, 4uLL);\n }\n v1 = (uint32_t *)(*ptr + 8LL);\n *v1 = 0;\n v2 = (uint32_t *)(*ptr + 4LL);\n *v2 = *v1;\n *(uint32_t *)*ptr = *v2;\n v3 = (uint32_t *)(*v20 + 8LL);\n *v3 = 0;\n v4 = (uint32_t *)(*v20 + 4LL);\n *v4 = *v3;\n *(uint32_t *)*v20 = *v4;\n for (j = 1; j <= a1; ++j) {\n v18[j - 1] = (j * j - j + 1) % 3;\n for (k = 0; k <= 2; ++k)\n *(uint32_t *)(4LL * k + ptr[j]) = *(uint32_t *)(4LL * k + ptr[j - 1]);\n ++*(uint32_t *)(4LL * v18[j - 1] + ptr[j]);\n }\n for (m = 1; m <= 2; ++m) {\n for (n = 1; n <= a1; ++n) {\n for (ii = 0; ii <= 2; ++ii)\n *(uint32_t *)(4LL * ii + v20[n]) = *(uint32_t *)(4LL * ii + v20[n - 1]);\n if (n > 0) {\n for (jj = 0; jj <= 2; ++jj) {\n v5 = (v18[n - 1] + jj) % 3;\n *(uint32_t *)(v20[n] + 4LL * v5) +=\n *(uint32_t *)(4LL * jj + ptr[n - 1]);\n }\n }\n }\n for (kk = 0; kk <= a1; ++kk) {\n for (mm = 0; mm <= 2; ++mm) {\n *(uint32_t *)(4LL * mm + ptr[kk]) = *(uint32_t *)(4LL * mm + v20[kk]);\n *(uint32_t *)(4LL * mm + v20[kk]) = 0;\n }\n }\n }\n v17 = *(uint32_t *)ptr[a1];\n for (nn = 0; nn <= a1; ++nn) {\n free((void *)ptr[nn]);\n free((void *)v20[nn]);\n }\n free(ptr);\n free(v20);\n free(v18);\n return v17;\n}" + }, + { + "index": "HumanEval-C-147", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(int n) {\n int *a = (int *)malloc(n * sizeof(int));\n int **sum = (int **)malloc((n + 1) * sizeof(int *));\n int **sum2 = (int **)malloc((n + 1) * sizeof(int *));\n for (int i = 0; i <= n; i++) {\n sum[i] = (int *)calloc(3, sizeof(int));\n sum2[i] = (int *)calloc(3, sizeof(int));\n }\n sum[0][0] = sum[0][1] = sum[0][2] = 0;\n sum2[0][0] = sum2[0][1] = sum2[0][2] = 0;\n for (int i = 1; i <= n; i++) {\n a[i - 1] = (i * i - i + 1) % 3;\n for (int j = 0; j < 3; j++) {\n sum[i][j] = sum[i - 1][j];\n }\n sum[i][a[i - 1]] += 1;\n }\n for (int times = 1; times < 3; times++) {\n for (int i = 1; i <= n; i++) {\n for (int j = 0; j < 3; j++) {\n sum2[i][j] = sum2[i - 1][j];\n }\n if (i >= 1) {\n for (int j = 0; j <= 2; j++) {\n sum2[i][(a[i - 1] + j) % 3] += sum[i - 1][j];\n }\n }\n }\n for (int i = 0; i <= n; i++) {\n for (int j = 0; j < 3; j++) {\n sum[i][j] = sum2[i][j];\n sum2[i][j] = 0;\n }\n }\n }\n int result = sum[n][0];\n for (int i = 0; i <= n; ++i) {\n free(sum[i]);\n free(sum2[i]);\n }\n free(sum);\n free(sum2);\n free(a);\n return result;\n}", + "test": "#include \n\nint main() {\n assert(func0(5) == 1);\n assert(func0(6) == 4);\n assert(func0(10) == 36);\n assert(func0(100) == 53361);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov r13d, edi\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov r12, rax\nlea eax, [r13+1]\ncdqe\nlea rbx, ds:0[rax*8]\nmov [rsp+48h+var_40], rbx\nmov rdi, rbx; size\ncall _malloc\nmov rbp, rax\nmov rdi, rbx; size\ncall _malloc\nmov rbx, rax\ntest r13d, r13d\njs loc_1406\nlea r15d, [r13+1]\nshl r15, 3\nmov r14d, 0\nloc_120D:\nmov esi, 4; size\nmov edi, 3; nmemb\ncall _calloc\nmov [rbp+r14+0], rax\nmov esi, 4; size\nmov edi, 3; nmemb\ncall _calloc\nmov [rbx+r14], rax\nadd r14, 8\ncmp r14, r15\njnz short loc_120D\nmov rax, [rbp+0]\nmov dword ptr [rax+8], 0\nmov dword ptr [rax+4], 0\nmov dword ptr [rax], 0\nmov rax, [rbx]\nmov dword ptr [rax+8], 0\nmov dword ptr [rax+4], 0\nmov dword ptr [rax], 0\ntest r13d, r13d\njle short loc_12CF\nmov esi, r13d\nmov ecx, 0\nloc_1279:\nlea edx, [rcx+1]\nimul edx, ecx\nadd edx, 1\nmovsxd rax, edx\nimul rax, 55555556h\nshr rax, 20h\nmov edi, edx\nsar edi, 1Fh\nsub eax, edi\nlea edi, [rax+rax*2]\nmov eax, edx\nsub eax, edi\nmov [r12+rcx*4], eax\nmov rdi, [rbp+rcx*8+0]\nmov rdx, [rbp+rcx*8+8]\nmov r8d, [rdi]\nmov [rdx], r8d\nmov r8d, [rdi+4]\nmov [rdx+4], r8d\nmov edi, [rdi+8]\nmov [rdx+8], edi\ncdqe\nadd dword ptr [rdx+rax*4], 1\nadd rcx, 1\ncmp rsi, rcx\njnz short loc_1279\nloc_12CF:\nmov eax, r13d\nlea r14, ds:8[rax*8]\nmov ecx, 2\nlea r8d, [r13+1]\njmp loc_139C\nloc_12E8:\nmov r10d, [r12+rdi*4-4]\nmov r9, [rbp+rdi*8-8]\nmov edx, 0\nloc_12F7:\nlea eax, [r10+rdx]\nmovsxd r11, eax\nimul r11, 55555556h\nshr r11, 20h\nmov r15d, eax\nsar r15d, 1Fh\nsub r11d, r15d\nlea r11d, [r11+r11*2]\nsub eax, r11d\ncdqe\nmov r11d, [r9+rdx*4]\nadd [rsi+rax*4], r11d\nadd rdx, 1\ncmp rdx, 3\njnz short loc_12F7\nadd rdi, 1\ncmp r8, rdi\njz short loc_135C\nloc_1337:\nmov rax, [rbx+rdi*8-8]\nmov rsi, [rbx+rdi*8]\nmov edx, [rax]\nmov [rsi], edx\nmov edx, [rax+4]\nmov [rsi+4], edx\nmov eax, [rax+8]\nmov [rsi+8], eax\ntest edi, edi\njg short loc_12E8\nadd rdi, 1\njmp short loc_1337\nloc_135A:\njs short loc_1397\nloc_135C:\nmov edx, 0\nloc_1361:\nmov rax, [rbx+rdx]\nmov rsi, [rbp+rdx+0]\nmov edi, [rax]\nmov [rsi], edi\nmov dword ptr [rax], 0\nmov edi, [rax+4]\nmov [rsi+4], edi\nmov dword ptr [rax+4], 0\nmov edi, [rax+8]\nmov [rsi+8], edi\nmov dword ptr [rax+8], 0\nadd rdx, 8\ncmp rdx, r14\njnz short loc_1361\nloc_1397:\nsub ecx, 1\njz short loc_13A8\nloc_139C:\ntest r13d, r13d\njle short loc_135A\nmov edi, 1\njmp short loc_1337\nloc_13A8:\nmov rax, [rsp+48h+var_40]\nmov rax, [rbp+rax-8]\nmov r15d, [rax]\ntest r13d, r13d\njs short loc_13DC\nmov r13d, 0\nloc_13C0:\nmov rdi, [rbp+r13+0]; ptr\ncall _free\nmov rdi, [rbx+r13]; ptr\ncall _free\nadd r13, 8\ncmp r13, r14\njnz short loc_13C0\nloc_13DC:\nmov rdi, rbp; ptr\ncall _free\nmov rdi, rbx; ptr\ncall _free\nmov rdi, r12; ptr\ncall _free\nmov eax, r15d\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1406:\nmov rax, [rbp+0]\nmov dword ptr [rax+8], 0\nmov dword ptr [rax+4], 0\nmov dword ptr [rax], 0\nmov rax, [rbx]\nmov dword ptr [rax+8], 0\nmov dword ptr [rax+4], 0\nmov dword ptr [rax], 0\njmp loc_12CF", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n _DWORD *v2; // r12\n _QWORD *v3; // rbp\n _QWORD *v4; // rbx\n __int64 v5; // r14\n _DWORD *v6; // rax\n _DWORD *v7; // rax\n __int64 i; // rcx\n int v9; // eax\n _DWORD *v10; // rdi\n _DWORD *v11; // rdx\n __int64 v12; // r14\n int v13; // ecx\n int v14; // r10d\n __int64 v15; // r9\n __int64 j; // rdx\n __int64 v17; // rdi\n _DWORD *v18; // rax\n _DWORD *v19; // rsi\n unsigned __int64 v20; // rdx\n _DWORD *v21; // rax\n _DWORD *v22; // rsi\n unsigned int v23; // r15d\n unsigned __int64 v24; // r13\n _DWORD *v26; // rax\n _DWORD *v27; // rax\n size_t v28; // [rsp+8h] [rbp-40h]\n\n v2 = malloc(4LL * a1);\n v28 = 8LL * (a1 + 1);\n v3 = malloc(v28);\n v4 = malloc(v28);\n if ( a1 < 0 )\n {\n v26 = (_DWORD *)*v3;\n v26[2] = 0;\n v26[1] = 0;\n *v26 = 0;\n v27 = (_DWORD *)*v4;\n v27[2] = 0;\n v27[1] = 0;\n *v27 = 0;\n }\n else\n {\n v5 = 0LL;\n do\n {\n v3[v5] = calloc(3uLL, 4uLL);\n v4[v5++] = calloc(3uLL, 4uLL);\n }\n while ( v5 != a1 + 1 );\n v6 = (_DWORD *)*v3;\n v6[2] = 0;\n v6[1] = 0;\n *v6 = 0;\n v7 = (_DWORD *)*v4;\n v7[2] = 0;\n v7[1] = 0;\n *v7 = 0;\n if ( a1 > 0 )\n {\n for ( i = 0LL; i != a1; ++i )\n {\n v9 = ((int)i * ((int)i + 1) + 1) % 3;\n v2[i] = v9;\n v10 = (_DWORD *)v3[i];\n v11 = (_DWORD *)v3[i + 1];\n *v11 = *v10;\n v11[1] = v10[1];\n v11[2] = v10[2];\n ++v11[v9];\n }\n }\n }\n v12 = 8LL * (unsigned int)a1 + 8;\n v13 = 2;\n do\n {\n if ( a1 <= 0 )\n {\n if ( a1 < 0 )\n goto LABEL_16;\n }\n else\n {\n v17 = 1LL;\n do\n {\n while ( 1 )\n {\n v18 = (_DWORD *)v4[v17 - 1];\n v19 = (_DWORD *)v4[v17];\n *v19 = *v18;\n v19[1] = v18[1];\n v19[2] = v18[2];\n if ( (int)v17 > 0 )\n break;\n ++v17;\n }\n v14 = v2[v17 - 1];\n v15 = v3[v17 - 1];\n for ( j = 0LL; j != 3; ++j )\n v19[(v14 + (int)j) % 3] += *(_DWORD *)(v15 + 4 * j);\n ++v17;\n }\n while ( a1 + 1 != v17 );\n }\n v20 = 0LL;\n do\n {\n v21 = (_DWORD *)v4[v20 / 8];\n v22 = (_DWORD *)v3[v20 / 8];\n *v22 = *v21;\n *v21 = 0;\n v22[1] = v21[1];\n v21[1] = 0;\n v22[2] = v21[2];\n v21[2] = 0;\n v20 += 8LL;\n }\n while ( v20 != v12 );\nLABEL_16:\n --v13;\n }\n while ( v13 );\n v23 = *(_DWORD *)v3[v28 / 8 - 1];\n if ( a1 >= 0 )\n {\n v24 = 0LL;\n do\n {\n free((void *)v3[v24 / 8]);\n free((void *)v4[v24 / 8]);\n v24 += 8LL;\n }\n while ( v24 != v12 );\n }\n free(v3);\n free(v4);\n free(v2);\n return v23;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov r13d, edi\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov r12, rax\nlea eax, [r13+1]\ncdqe\nlea rbx, ds:0[rax*8]\nmov [rsp+48h+var_40], rbx\nmov rdi, rbx; size\ncall _malloc\nmov rbp, rax\nmov rdi, rbx; size\ncall _malloc\nmov rbx, rax\ntest r13d, r13d\njs loc_1406\nlea r15d, [r13+1]\nshl r15, 3\nmov r14d, 0\nloc_120D:\nmov esi, 4; size\nmov edi, 3; nmemb\ncall _calloc\nmov [rbp+r14+0], rax\nmov esi, 4; size\nmov edi, 3; nmemb\ncall _calloc\nmov [rbx+r14], rax\nadd r14, 8\ncmp r14, r15\njnz short loc_120D\nmov rax, [rbp+0]\nmov dword ptr [rax+8], 0\nmov dword ptr [rax+4], 0\nmov dword ptr [rax], 0\nmov rax, [rbx]\nmov dword ptr [rax+8], 0\nmov dword ptr [rax+4], 0\nmov dword ptr [rax], 0\ntest r13d, r13d\njle short loc_12CF\nmov esi, r13d\nmov ecx, 0\nloc_1279:\nlea edx, [rcx+1]\nimul edx, ecx\nadd edx, 1\nmovsxd rax, edx\nimul rax, 55555556h\nshr rax, 20h\nmov edi, edx\nsar edi, 1Fh\nsub eax, edi\nlea edi, [rax+rax*2]\nmov eax, edx\nsub eax, edi\nmov [r12+rcx*4], eax\nmov rdi, [rbp+rcx*8+0]\nmov rdx, [rbp+rcx*8+8]\nmov r8d, [rdi]\nmov [rdx], r8d\nmov r8d, [rdi+4]\nmov [rdx+4], r8d\nmov edi, [rdi+8]\nmov [rdx+8], edi\ncdqe\nadd dword ptr [rdx+rax*4], 1\nadd rcx, 1\ncmp rsi, rcx\njnz short loc_1279\nloc_12CF:\nmov eax, r13d\nlea r14, ds:8[rax*8]\nmov ecx, 2\nlea r8d, [r13+1]\njmp loc_139C\nloc_12E8:\nmov r10d, [r12+rdi*4-4]\nmov r9, [rbp+rdi*8-8]\nmov edx, 0\nloc_12F7:\nlea eax, [r10+rdx]\nmovsxd r11, eax\nimul r11, 55555556h\nshr r11, 20h\nmov r15d, eax\nsar r15d, 1Fh\nsub r11d, r15d\nlea r11d, [r11+r11*2]\nsub eax, r11d\ncdqe\nmov r11d, [r9+rdx*4]\nadd [rsi+rax*4], r11d\nadd rdx, 1\ncmp rdx, 3\njnz short loc_12F7\nadd rdi, 1\ncmp r8, rdi\njz short loc_135C\nloc_1337:\nmov rax, [rbx+rdi*8-8]\nmov rsi, [rbx+rdi*8]\nmov edx, [rax]\nmov [rsi], edx\nmov edx, [rax+4]\nmov [rsi+4], edx\nmov eax, [rax+8]\nmov [rsi+8], eax\ntest edi, edi\njg short loc_12E8\nadd rdi, 1\njmp short loc_1337\nloc_135A:\njs short loc_1397\nloc_135C:\nmov edx, 0\nloc_1361:\nmov rax, [rbx+rdx]\nmov rsi, [rbp+rdx+0]\nmov edi, [rax]\nmov [rsi], edi\nmov dword ptr [rax], 0\nmov edi, [rax+4]\nmov [rsi+4], edi\nmov dword ptr [rax+4], 0\nmov edi, [rax+8]\nmov [rsi+8], edi\nmov dword ptr [rax+8], 0\nadd rdx, 8\ncmp rdx, r14\njnz short loc_1361\nloc_1397:\nsub ecx, 1\njz short loc_13A8\nloc_139C:\ntest r13d, r13d\njle short loc_135A\nmov edi, 1\njmp short loc_1337\nloc_13A8:\nmov rax, [rsp+48h+var_40]\nmov rax, [rbp+rax-8]\nmov r15d, [rax]\ntest r13d, r13d\njs short loc_13DC\nmov r13d, 0\nloc_13C0:\nmov rdi, [rbp+r13+0]; ptr\ncall _free\nmov rdi, [rbx+r13]; ptr\ncall _free\nadd r13, 8\ncmp r13, r14\njnz short loc_13C0\nloc_13DC:\nmov rdi, rbp; ptr\ncall _free\nmov rdi, rbx; ptr\ncall _free\nmov rdi, r12; ptr\ncall _free\nmov eax, r15d\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1406:\nmov rax, [rbp+0]\nmov dword ptr [rax+8], 0\nmov dword ptr [rax+4], 0\nmov dword ptr [rax], 0\nmov rax, [rbx]\nmov dword ptr [rax+8], 0\nmov dword ptr [rax+4], 0\nmov dword ptr [rax], 0\njmp loc_12CF", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(int a1)\n{\n _DWORD *v2; // r12\n _QWORD *v3; // rbp\n _QWORD *v4; // rbx\n __int64 v5; // r14\n _DWORD *v6; // rax\n _DWORD *v7; // rax\n __int64 i; // rcx\n int v9; // eax\n _DWORD *v10; // rdi\n _DWORD *v11; // rdx\n __int64 v12; // r14\n int v13; // ecx\n int v14; // r10d\n __int64 v15; // r9\n __int64 j; // rdx\n __int64 v17; // rdi\n _DWORD *v18; // rax\n _DWORD *v19; // rsi\n unsigned __int64 v20; // rdx\n _DWORD *v21; // rax\n _DWORD *v22; // rsi\n unsigned int v23; // r15d\n unsigned __int64 v24; // r13\n _DWORD *v26; // rax\n _DWORD *v27; // rax\n size_t v28; // [rsp+8h] [rbp-40h]\n\n v2 = malloc(4LL * a1);\n v28 = 8LL * (a1 + 1);\n v3 = malloc(v28);\n v4 = malloc(v28);\n if ( a1 < 0 )\n {\n v26 = (_DWORD *)*v3;\n v26[2] = 0;\n v26[1] = 0;\n *v26 = 0;\n v27 = (_DWORD *)*v4;\n v27[2] = 0;\n v27[1] = 0;\n *v27 = 0;\n }\n else\n {\n v5 = 0LL;\n do\n {\n v3[v5] = calloc(3uLL, 4uLL);\n v4[v5++] = calloc(3uLL, 4uLL);\n }\n while ( v5 != a1 + 1 );\n v6 = (_DWORD *)*v3;\n v6[2] = 0;\n v6[1] = 0;\n *v6 = 0;\n v7 = (_DWORD *)*v4;\n v7[2] = 0;\n v7[1] = 0;\n *v7 = 0;\n if ( a1 > 0 )\n {\n for ( i = 0LL; i != a1; ++i )\n {\n v9 = ((int)i * ((int)i + 1) + 1) % 3;\n v2[i] = v9;\n v10 = (_DWORD *)v3[i];\n v11 = (_DWORD *)v3[i + 1];\n *v11 = *v10;\n v11[1] = v10[1];\n v11[2] = v10[2];\n ++v11[v9];\n }\n }\n }\n v12 = 8LL * (unsigned int)a1 + 8;\n v13 = 2;\n do\n {\n if ( a1 <= 0 )\n {\n if ( a1 < 0 )\n goto LABEL_16;\n }\n else\n {\n v17 = 1LL;\n do\n {\n while ( 1 )\n {\n v18 = (_DWORD *)v4[v17 - 1];\n v19 = (_DWORD *)v4[v17];\n *v19 = *v18;\n v19[1] = v18[1];\n v19[2] = v18[2];\n if ( (int)v17 > 0 )\n break;\n ++v17;\n }\n v14 = v2[v17 - 1];\n v15 = v3[v17 - 1];\n for ( j = 0LL; j != 3; ++j )\n v19[(v14 + (int)j) % 3] += *(_DWORD *)(v15 + 4 * j);\n ++v17;\n }\n while ( a1 + 1 != v17 );\n }\n v20 = 0LL;\n do\n {\n v21 = (_DWORD *)v4[v20 / 8];\n v22 = (_DWORD *)v3[v20 / 8];\n *v22 = *v21;\n *v21 = 0;\n v22[1] = v21[1];\n v21[1] = 0;\n v22[2] = v21[2];\n v21[2] = 0;\n v20 += 8LL;\n }\n while ( v20 != v12 );\nLABEL_16:\n --v13;\n }\n while ( v13 );\n v23 = *(_DWORD *)v3[v28 / 8 - 1];\n if ( a1 >= 0 )\n {\n v24 = 0LL;\n do\n {\n free((void *)v3[v24 / 8]);\n free((void *)v4[v24 / 8]);\n v24 += 8LL;\n }\n while ( v24 != v12 );\n }\n free(v3);\n free(v4);\n free(v2);\n return v23;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(int a1) {\n uint32_t *v2;\n uint64_t *v3;\n uint64_t *v4;\n long long v5;\n uint32_t *v6;\n uint32_t *v7;\n long long i;\n int v9;\n uint32_t *v10;\n uint32_t *v11;\n long long v12;\n int v13;\n int v14;\n long long v15;\n long long j;\n long long v17;\n uint32_t *v18;\n uint32_t *v19;\n unsigned long long v20;\n uint32_t *v21;\n uint32_t *v22;\n unsigned int v23;\n unsigned long long v24;\n uint32_t *v26;\n uint32_t *v27;\n unsigned int v28;\n v2 = malloc(4LL * a1);\n v28 = 8LL * (a1 + 1);\n v3 = malloc(v28);\n v4 = malloc(v28);\n if (a1 < 0) {\n v26 = (uint32_t *)*v3;\n v26[2] = 0;\n v26[1] = 0;\n *v26 = 0;\n v27 = (uint32_t *)*v4;\n v27[2] = 0;\n v27[1] = 0;\n *v27 = 0;\n } else {\n v5 = 0LL;\n do {\n v3[v5] = calloc(3uLL, 4uLL);\n v4[v5++] = calloc(3uLL, 4uLL);\n } while (v5 != a1 + 1);\n v6 = (uint32_t *)*v3;\n v6[2] = 0;\n v6[1] = 0;\n *v6 = 0;\n v7 = (uint32_t *)*v4;\n v7[2] = 0;\n v7[1] = 0;\n *v7 = 0;\n if (a1 > 0) {\n for (i = 0LL; i != a1; ++i) {\n v9 = ((int)i * ((int)i + 1) + 1) % 3;\n v2[i] = v9;\n v10 = (uint32_t *)v3[i];\n v11 = (uint32_t *)v3[i + 1];\n *v11 = *v10;\n v11[1] = v10[1];\n v11[2] = v10[2];\n ++v11[v9];\n }\n }\n }\n v12 = 8LL * (unsigned int)a1 + 8;\n v13 = 2;\n do {\n if (a1 <= 0) {\n if (a1 < 0) goto LABEL_16;\n } else {\n v17 = 1LL;\n do {\n while (1) {\n v18 = (uint32_t *)v4[v17 - 1];\n v19 = (uint32_t *)v4[v17];\n *v19 = *v18;\n v19[1] = v18[1];\n v19[2] = v18[2];\n if ((int)v17 > 0) break;\n ++v17;\n }\n v14 = v2[v17 - 1];\n v15 = v3[v17 - 1];\n for (j = 0LL; j != 3; ++j)\n v19[(v14 + (int)j) % 3] += *(uint32_t *)(v15 + 4 * j);\n ++v17;\n } while (a1 + 1 != v17);\n }\n v20 = 0LL;\n do {\n v21 = (uint32_t *)v4[v20 / 8];\n v22 = (uint32_t *)v3[v20 / 8];\n *v22 = *v21;\n *v21 = 0;\n v22[1] = v21[1];\n v21[1] = 0;\n v22[2] = v21[2];\n v21[2] = 0;\n v20 += 8LL;\n } while (v20 != v12);\n LABEL_16:\n --v13;\n } while (v13);\n v23 = *(uint32_t *)v3[v28 / 8 - 1];\n if (a1 >= 0) {\n v24 = 0LL;\n do {\n free((void *)v3[v24 / 8]);\n free((void *)v4[v24 / 8]);\n v24 += 8LL;\n } while (v24 != v12);\n }\n free(v3);\n free(v4);\n free(v2);\n return v23;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n uint32_t *v2;\n uint64_t *v3;\n uint64_t *v4;\n long long v5;\n uint32_t *v6;\n uint32_t *v7;\n long long i;\n int v9;\n uint32_t *v10;\n uint32_t *v11;\n long long v12;\n int v13;\n int v14;\n long long v15;\n long long j;\n long long v17;\n uint32_t *v18;\n uint32_t *v19;\n unsigned long long v20;\n uint32_t *v21;\n uint32_t *v22;\n unsigned int v23;\n unsigned long long v24;\n uint32_t *v26;\n uint32_t *v27;\n unsigned int v28;\n v2 = malloc(4LL * a1);\n v28 = 8LL * (a1 + 1);\n v3 = malloc(v28);\n v4 = malloc(v28);\n if (a1 < 0) {\n v26 = (uint32_t *)*v3;\n v26[2] = 0;\n v26[1] = 0;\n *v26 = 0;\n v27 = (uint32_t *)*v4;\n v27[2] = 0;\n v27[1] = 0;\n *v27 = 0;\n } else {\n v5 = 0LL;\n do {\n v3[v5] = calloc(3uLL, 4uLL);\n v4[v5++] = calloc(3uLL, 4uLL);\n } while (v5 != a1 + 1);\n v6 = (uint32_t *)*v3;\n v6[2] = 0;\n v6[1] = 0;\n *v6 = 0;\n v7 = (uint32_t *)*v4;\n v7[2] = 0;\n v7[1] = 0;\n *v7 = 0;\n if (a1 > 0) {\n for (i = 0LL; i != a1; ++i) {\n v9 = ((int)i * ((int)i + 1) + 1) % 3;\n v2[i] = v9;\n v10 = (uint32_t *)v3[i];\n v11 = (uint32_t *)v3[i + 1];\n *v11 = *v10;\n v11[1] = v10[1];\n v11[2] = v10[2];\n ++v11[v9];\n }\n }\n }\n v12 = 8LL * (unsigned int)a1 + 8;\n v13 = 2;\n do {\n if (a1 <= 0) {\n if (a1 < 0) goto LABEL_16;\n } else {\n v17 = 1LL;\n do {\n while (1) {\n v18 = (uint32_t *)v4[v17 - 1];\n v19 = (uint32_t *)v4[v17];\n *v19 = *v18;\n v19[1] = v18[1];\n v19[2] = v18[2];\n if ((int)v17 > 0) break;\n ++v17;\n }\n v14 = v2[v17 - 1];\n v15 = v3[v17 - 1];\n for (j = 0LL; j != 3; ++j)\n v19[(v14 + (int)j) % 3] += *(uint32_t *)(v15 + 4 * j);\n ++v17;\n } while (a1 + 1 != v17);\n }\n v20 = 0LL;\n do {\n v21 = (uint32_t *)v4[v20 / 8];\n v22 = (uint32_t *)v3[v20 / 8];\n *v22 = *v21;\n *v21 = 0;\n v22[1] = v21[1];\n v21[1] = 0;\n v22[2] = v21[2];\n v21[2] = 0;\n v20 += 8LL;\n } while (v20 != v12);\n LABEL_16:\n --v13;\n } while (v13);\n v23 = *(uint32_t *)v3[v28 / 8 - 1];\n if (a1 >= 0) {\n v24 = 0LL;\n do {\n free((void *)v3[v24 / 8]);\n free((void *)v4[v24 / 8]);\n v24 += 8LL;\n } while (v24 != v12);\n }\n free(v3);\n free(v4);\n free(v2);\n return v23;\n}" + }, + { + "index": "HumanEval-C-147", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(int n) {\n int *a = (int *)malloc(n * sizeof(int));\n int **sum = (int **)malloc((n + 1) * sizeof(int *));\n int **sum2 = (int **)malloc((n + 1) * sizeof(int *));\n for (int i = 0; i <= n; i++) {\n sum[i] = (int *)calloc(3, sizeof(int));\n sum2[i] = (int *)calloc(3, sizeof(int));\n }\n sum[0][0] = sum[0][1] = sum[0][2] = 0;\n sum2[0][0] = sum2[0][1] = sum2[0][2] = 0;\n for (int i = 1; i <= n; i++) {\n a[i - 1] = (i * i - i + 1) % 3;\n for (int j = 0; j < 3; j++) {\n sum[i][j] = sum[i - 1][j];\n }\n sum[i][a[i - 1]] += 1;\n }\n for (int times = 1; times < 3; times++) {\n for (int i = 1; i <= n; i++) {\n for (int j = 0; j < 3; j++) {\n sum2[i][j] = sum2[i - 1][j];\n }\n if (i >= 1) {\n for (int j = 0; j <= 2; j++) {\n sum2[i][(a[i - 1] + j) % 3] += sum[i - 1][j];\n }\n }\n }\n for (int i = 0; i <= n; i++) {\n for (int j = 0; j < 3; j++) {\n sum[i][j] = sum2[i][j];\n sum2[i][j] = 0;\n }\n }\n }\n int result = sum[n][0];\n for (int i = 0; i <= n; ++i) {\n free(sum[i]);\n free(sum2[i]);\n }\n free(sum);\n free(sum2);\n free(a);\n return result;\n}", + "test": "#include \n\nint main() {\n assert(func0(5) == 1);\n assert(func0(6) == 4);\n assert(func0(10) == 36);\n assert(func0(100) == 53361);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmovsxd r14, edi\npush r13\nlea rdi, ds:0[r14*4]; size\nmov r13, r14\npush r12\npush rbp\npush rbx\nsub rsp, 18h\ncall _malloc\nmov r12, rax\nlea eax, [r14+1]\ncdqe\nlea r15, ds:0[rax*8]\nmov rdi, r15; size\nmov [rsp+48h+var_40], r15\ncall _malloc\nmov rdi, r15; size\nmov rbx, rax\ncall _malloc\nmov rbp, rax\ntest r14d, r14d\njs loc_14B6\nlea r14, ds:8[r14*8]\nxor r15d, r15d\nnop dword ptr [rax]\nloc_12E8:\nmov esi, 4; size\nmov edi, 3; nmemb\ncall _calloc\nmov esi, 4; size\nmov edi, 3; nmemb\nmov [rbx+r15], rax\ncall _calloc\nmov [rbp+r15+0], rax\nadd r15, 8\ncmp r15, r14\njnz short loc_12E8\nmov rax, [rbx]\nmov dword ptr [rax+8], 0\nmov qword ptr [rax], 0\nmov rax, [rbp+0]\nmov dword ptr [rax+8], 0\nmov qword ptr [rax], 0\ntest r13d, r13d\njz loc_14F6\nmov r8d, r13d\nxor edx, edx\nmov edi, 0AAAAAAABh\nxchg ax, ax\nloc_1350:\nlea ecx, [rdx+1]\nimul ecx, edx\nlea eax, [rcx+1]\nmov rcx, rax\nimul rax, rdi\nshr rax, 21h\nlea esi, [rax+rax*2]\nmov eax, ecx\nmov rcx, [rbx+rdx*8+8]\nsub eax, esi\nmov rsi, [rbx+rdx*8]\nmov [r12+rdx*4], eax\ncdqe\nadd rdx, 1\nmov r9d, [rsi]\nmov [rcx], r9d\nmov r9d, [rsi+4]\nmov [rcx+4], r9d\nmov esi, [rsi+8]\nmov [rcx+8], esi\nadd dword ptr [rcx+rax*4], 1\ncmp rdx, r8\njnz short loc_1350\nloc_139B:\nlea r14, ds:8[r8*8]\nmov esi, 2\nloc_13A8:\ntest r13d, r13d\njle loc_14E1\nxor edi, edi\nnop dword ptr [rax+rax+00h]\nloc_13B8:\nmov rax, [rbp+rdi*8+0]\nmov rcx, [rbp+rdi*8+8]\nmov r10d, [r12+rdi*4]\nmov r9, [rbx+rdi*8]\nmov edx, [rax]\nmov [rcx], edx\nmov edx, [rax+4]\nmov [rcx+4], edx\nmov eax, [rax+8]\nxor edx, edx\nmov [rcx+8], eax\nloc_13DC:\nlea eax, [r10+rdx]\nmovsxd r11, eax\nmov r15d, eax\nimul r11, 55555556h\nsar r15d, 1Fh\nshr r11, 20h\nsub r11d, r15d\nlea r11d, [r11+r11*2]\nsub eax, r11d\nmov r11d, [r9+rdx*4]\nadd rdx, 1\ncdqe\nadd [rcx+rax*4], r11d\ncmp rdx, 3\njnz short loc_13DC\nadd rdi, 1\ncmp r8, rdi\njnz short loc_13B8\nloc_141C:\nxor eax, eax\nxchg ax, ax\nloc_1420:\nmov rdx, [rbp+rax+0]\nmov rcx, [rbx+rax]\nadd rax, 8\nmov rdi, [rdx]\nmov qword ptr [rdx], 0\nmov [rcx], rdi\nmov edi, [rdx+8]\nmov dword ptr [rdx+8], 0\nmov [rcx+8], edi\ncmp r14, rax\njnz short loc_1420\ncmp esi, 1\njz short loc_145B\nmov esi, 1\njmp loc_13A8\nloc_145B:\nmov rax, [rsp+48h+var_40]\nxor r13d, r13d\nmov rax, [rbx+rax-8]\nmov r15d, [rax]\nnop dword ptr [rax+rax+00h]\nloc_1470:\nmov rdi, [rbx+r13]; ptr\ncall _free\nmov rdi, [rbp+r13+0]; ptr\nadd r13, 8\ncall _free\ncmp r13, r14\njnz short loc_1470\nloc_148C:\nmov rdi, rbx; ptr\ncall _free\nmov rdi, rbp; ptr\ncall _free\nmov rdi, r12; ptr\ncall _free\nadd rsp, 18h\nmov eax, r15d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14B6:\nmov rax, [rbx]\nmov r8d, r14d\nmov dword ptr [rax+8], 0\nmov qword ptr [rax], 0\nmov rax, [rbp+0]\nmov dword ptr [rax+8], 0\nmov qword ptr [rax], 0\njmp loc_139B\nloc_14E1:\njz loc_141C\nmov rax, [rsp+48h+var_40]\nmov rax, [rbx+rax-8]\nmov r15d, [rax]\njmp short loc_148C\nloc_14F6:\nxor r8d, r8d\njmp loc_139B", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n _DWORD *v2; // r12\n size_t v3; // r15\n __int64 *v4; // rbx\n __int64 *v5; // rbp\n unsigned __int64 v6; // r15\n __int64 v7; // rax\n __int64 v8; // rax\n __int64 v9; // r8\n __int64 v10; // rdx\n _DWORD *v11; // rcx\n signed int v12; // eax\n _DWORD *v13; // rsi\n __int64 v14; // r14\n int i; // esi\n __int64 v16; // rdi\n _DWORD *v17; // rax\n _DWORD *v18; // rcx\n int v19; // r10d\n __int64 v20; // r9\n __int64 v21; // rdx\n int v22; // eax\n int v23; // r11d\n unsigned __int64 v24; // rax\n __int64 *v25; // rdx\n __int64 v26; // rcx\n __int64 v27; // rdi\n unsigned __int64 v28; // r13\n unsigned int v29; // r15d\n void *v30; // rdi\n __int64 v32; // rax\n __int64 v33; // rax\n size_t v34; // [rsp+8h] [rbp-40h]\n\n v2 = malloc(4LL * a1);\n v3 = 8LL * (a1 + 1);\n v34 = v3;\n v4 = (__int64 *)malloc(v3);\n v5 = (__int64 *)malloc(v3);\n if ( a1 < 0 )\n {\n v32 = *v4;\n v9 = (unsigned int)a1;\n *(_DWORD *)(v32 + 8) = 0;\n *(_QWORD *)v32 = 0LL;\n v33 = *v5;\n *(_DWORD *)(v33 + 8) = 0;\n *(_QWORD *)v33 = 0LL;\n }\n else\n {\n v6 = 0LL;\n do\n {\n v4[v6 / 8] = (__int64)calloc(3uLL, 4uLL);\n v5[v6 / 8] = (__int64)calloc(3uLL, 4uLL);\n v6 += 8LL;\n }\n while ( v6 != 8LL * a1 + 8 );\n v7 = *v4;\n *(_DWORD *)(v7 + 8) = 0;\n *(_QWORD *)v7 = 0LL;\n v8 = *v5;\n *(_DWORD *)(v8 + 8) = 0;\n *(_QWORD *)v8 = 0LL;\n if ( a1 )\n {\n v9 = (unsigned int)a1;\n v10 = 0LL;\n do\n {\n v11 = (_DWORD *)v4[v10 + 1];\n v12 = ((int)v10 * ((int)v10 + 1) + 1) % 3u;\n v13 = (_DWORD *)v4[v10];\n v2[v10++] = v12;\n *v11 = *v13;\n v11[1] = v13[1];\n v11[2] = v13[2];\n ++v11[v12];\n }\n while ( v10 != a1 );\n }\n else\n {\n v9 = 0LL;\n }\n }\n v14 = 8 * v9 + 8;\n for ( i = 2; ; i = 1 )\n {\n if ( a1 <= 0 )\n {\n if ( a1 )\n {\n v29 = **(_DWORD **)((char *)v4 + v34 - 8);\n goto LABEL_19;\n }\n }\n else\n {\n v16 = 0LL;\n do\n {\n v17 = (_DWORD *)v5[v16];\n v18 = (_DWORD *)v5[v16 + 1];\n v19 = v2[v16];\n v20 = v4[v16];\n *v18 = *v17;\n v18[1] = v17[1];\n v21 = 0LL;\n v18[2] = v17[2];\n do\n {\n v22 = (v19 + (int)v21) % 3;\n v23 = *(_DWORD *)(v20 + 4 * v21++);\n v18[v22] += v23;\n }\n while ( v21 != 3 );\n ++v16;\n }\n while ( v9 != v16 );\n }\n v24 = 0LL;\n do\n {\n v25 = (__int64 *)v5[v24 / 8];\n v26 = v4[v24 / 8];\n v24 += 8LL;\n v27 = *v25;\n *v25 = 0LL;\n *(_QWORD *)v26 = v27;\n LODWORD(v27) = *((_DWORD *)v25 + 2);\n *((_DWORD *)v25 + 2) = 0;\n *(_DWORD *)(v26 + 8) = v27;\n }\n while ( v14 != v24 );\n if ( i == 1 )\n break;\n }\n v28 = 0LL;\n v29 = **(_DWORD **)((char *)v4 + v34 - 8);\n do\n {\n free((void *)v4[v28 / 8]);\n v30 = (void *)v5[v28 / 8];\n v28 += 8LL;\n free(v30);\n }\n while ( v28 != v14 );\nLABEL_19:\n free(v4);\n free(v5);\n free(v2);\n return v29;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\npush r15\npush r14\nmovsxd r14, edi\npush r13\nlea rdi, ds:0[r14*4]; size\nmov r13, r14\npush r12\npush rbp\npush rbx\nsub rsp, 18h\ncall _malloc\nmov r12, rax\nlea eax, [r14+1]\ncdqe\nlea r15, ds:0[rax*8]\nmov rdi, r15; size\nmov [rsp+48h+var_40], r15\ncall _malloc\nmov rdi, r15; size\nmov rbx, rax\ncall _malloc\nmov rbp, rax\ntest r14d, r14d\njs loc_14B6\nlea r14, ds:8[r14*8]\nxor r15d, r15d\nnop dword ptr [rax]\nloc_12E8:\nmov esi, 4; size\nmov edi, 3; nmemb\ncall _calloc\nmov esi, 4; size\nmov edi, 3; nmemb\nmov [rbx+r15], rax\ncall _calloc\nmov [rbp+r15+0], rax\nadd r15, 8\ncmp r15, r14\njnz short loc_12E8\nmov rax, [rbx]\nmov dword ptr [rax+8], 0\nmov qword ptr [rax], 0\nmov rax, [rbp+0]\nmov dword ptr [rax+8], 0\nmov qword ptr [rax], 0\ntest r13d, r13d\njz loc_14F6\nmov r8d, r13d\nxor edx, edx\nmov edi, 0AAAAAAABh\nxchg ax, ax\nloc_1350:\nlea ecx, [rdx+1]\nimul ecx, edx\nlea eax, [rcx+1]\nmov rcx, rax\nimul rax, rdi\nshr rax, 21h\nlea esi, [rax+rax*2]\nmov eax, ecx\nmov rcx, [rbx+rdx*8+8]\nsub eax, esi\nmov rsi, [rbx+rdx*8]\nmov [r12+rdx*4], eax\ncdqe\nadd rdx, 1\nmov r9d, [rsi]\nmov [rcx], r9d\nmov r9d, [rsi+4]\nmov [rcx+4], r9d\nmov esi, [rsi+8]\nmov [rcx+8], esi\nadd dword ptr [rcx+rax*4], 1\ncmp rdx, r8\njnz short loc_1350\nloc_139B:\nlea r14, ds:8[r8*8]\nmov esi, 2\nloc_13A8:\ntest r13d, r13d\njle loc_14E1\nxor edi, edi\nnop dword ptr [rax+rax+00h]\nloc_13B8:\nmov rax, [rbp+rdi*8+0]\nmov rcx, [rbp+rdi*8+8]\nmov r10d, [r12+rdi*4]\nmov r9, [rbx+rdi*8]\nmov edx, [rax]\nmov [rcx], edx\nmov edx, [rax+4]\nmov [rcx+4], edx\nmov eax, [rax+8]\nxor edx, edx\nmov [rcx+8], eax\nloc_13DC:\nlea eax, [r10+rdx]\nmovsxd r11, eax\nmov r15d, eax\nimul r11, 55555556h\nsar r15d, 1Fh\nshr r11, 20h\nsub r11d, r15d\nlea r11d, [r11+r11*2]\nsub eax, r11d\nmov r11d, [r9+rdx*4]\nadd rdx, 1\ncdqe\nadd [rcx+rax*4], r11d\ncmp rdx, 3\njnz short loc_13DC\nadd rdi, 1\ncmp r8, rdi\njnz short loc_13B8\nloc_141C:\nxor eax, eax\nxchg ax, ax\nloc_1420:\nmov rdx, [rbp+rax+0]\nmov rcx, [rbx+rax]\nadd rax, 8\nmov rdi, [rdx]\nmov qword ptr [rdx], 0\nmov [rcx], rdi\nmov edi, [rdx+8]\nmov dword ptr [rdx+8], 0\nmov [rcx+8], edi\ncmp r14, rax\njnz short loc_1420\ncmp esi, 1\njz short loc_145B\nmov esi, 1\njmp loc_13A8\nloc_145B:\nmov rax, [rsp+48h+var_40]\nxor r13d, r13d\nmov rax, [rbx+rax-8]\nmov r15d, [rax]\nnop dword ptr [rax+rax+00h]\nloc_1470:\nmov rdi, [rbx+r13]; ptr\ncall _free\nmov rdi, [rbp+r13+0]; ptr\nadd r13, 8\ncall _free\ncmp r13, r14\njnz short loc_1470\nloc_148C:\nmov rdi, rbx; ptr\ncall _free\nmov rdi, rbp; ptr\ncall _free\nmov rdi, r12; ptr\ncall _free\nadd rsp, 18h\nmov eax, r15d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14B6:\nmov rax, [rbx]\nmov r8d, r14d\nmov dword ptr [rax+8], 0\nmov qword ptr [rax], 0\nmov rax, [rbp+0]\nmov dword ptr [rax+8], 0\nmov qword ptr [rax], 0\njmp loc_139B\nloc_14E1:\njz loc_141C\nmov rax, [rsp+48h+var_40]\nmov rax, [rbx+rax-8]\nmov r15d, [rax]\njmp short loc_148C\nloc_14F6:\nxor r8d, r8d\njmp loc_139B", + "ida_strip_pseudo": "__int64 __fastcall sub_1280(int a1)\n{\n _DWORD *v2; // r12\n size_t v3; // r15\n __int64 *v4; // rbx\n __int64 *v5; // rbp\n unsigned __int64 v6; // r15\n __int64 v7; // rax\n __int64 v8; // rax\n __int64 v9; // r8\n __int64 v10; // rdx\n _DWORD *v11; // rcx\n signed int v12; // eax\n _DWORD *v13; // rsi\n __int64 v14; // r14\n int i; // esi\n __int64 v16; // rdi\n _DWORD *v17; // rax\n _DWORD *v18; // rcx\n int v19; // r10d\n __int64 v20; // r9\n __int64 v21; // rdx\n int v22; // eax\n int v23; // r11d\n unsigned __int64 v24; // rax\n __int64 *v25; // rdx\n __int64 v26; // rcx\n __int64 v27; // rdi\n unsigned __int64 v28; // r13\n unsigned int v29; // r15d\n void *v30; // rdi\n __int64 v32; // rax\n __int64 v33; // rax\n size_t v34; // [rsp+8h] [rbp-40h]\n\n v2 = malloc(4LL * a1);\n v3 = 8LL * (a1 + 1);\n v34 = v3;\n v4 = (__int64 *)malloc(v3);\n v5 = (__int64 *)malloc(v3);\n if ( a1 < 0 )\n {\n v32 = *v4;\n v9 = (unsigned int)a1;\n *(_DWORD *)(v32 + 8) = 0;\n *(_QWORD *)v32 = 0LL;\n v33 = *v5;\n *(_DWORD *)(v33 + 8) = 0;\n *(_QWORD *)v33 = 0LL;\n }\n else\n {\n v6 = 0LL;\n do\n {\n v4[v6 / 8] = (__int64)calloc(3uLL, 4uLL);\n v5[v6 / 8] = (__int64)calloc(3uLL, 4uLL);\n v6 += 8LL;\n }\n while ( v6 != 8LL * a1 + 8 );\n v7 = *v4;\n *(_DWORD *)(v7 + 8) = 0;\n *(_QWORD *)v7 = 0LL;\n v8 = *v5;\n *(_DWORD *)(v8 + 8) = 0;\n *(_QWORD *)v8 = 0LL;\n if ( a1 )\n {\n v9 = (unsigned int)a1;\n v10 = 0LL;\n do\n {\n v11 = (_DWORD *)v4[v10 + 1];\n v12 = ((int)v10 * ((int)v10 + 1) + 1) % 3u;\n v13 = (_DWORD *)v4[v10];\n v2[v10++] = v12;\n *v11 = *v13;\n v11[1] = v13[1];\n v11[2] = v13[2];\n ++v11[v12];\n }\n while ( v10 != a1 );\n }\n else\n {\n v9 = 0LL;\n }\n }\n v14 = 8 * v9 + 8;\n for ( i = 2; ; i = 1 )\n {\n if ( a1 <= 0 )\n {\n if ( a1 )\n {\n v29 = **(_DWORD **)((char *)v4 + v34 - 8);\n goto LABEL_19;\n }\n }\n else\n {\n v16 = 0LL;\n do\n {\n v17 = (_DWORD *)v5[v16];\n v18 = (_DWORD *)v5[v16 + 1];\n v19 = v2[v16];\n v20 = v4[v16];\n *v18 = *v17;\n v18[1] = v17[1];\n v21 = 0LL;\n v18[2] = v17[2];\n do\n {\n v22 = (v19 + (int)v21) % 3;\n v23 = *(_DWORD *)(v20 + 4 * v21++);\n v18[v22] += v23;\n }\n while ( v21 != 3 );\n ++v16;\n }\n while ( v9 != v16 );\n }\n v24 = 0LL;\n do\n {\n v25 = (__int64 *)v5[v24 / 8];\n v26 = v4[v24 / 8];\n v24 += 8LL;\n v27 = *v25;\n *v25 = 0LL;\n *(_QWORD *)v26 = v27;\n LODWORD(v27) = *((_DWORD *)v25 + 2);\n *((_DWORD *)v25 + 2) = 0;\n *(_DWORD *)(v26 + 8) = v27;\n }\n while ( v14 != v24 );\n if ( i == 1 )\n break;\n }\n v28 = 0LL;\n v29 = **(_DWORD **)((char *)v4 + v34 - 8);\n do\n {\n free((void *)v4[v28 / 8]);\n v30 = (void *)v5[v28 / 8];\n v28 += 8LL;\n free(v30);\n }\n while ( v28 != v14 );\nLABEL_19:\n free(v4);\n free(v5);\n free(v2);\n return v29;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1280(int a1) {\n uint32_t *v2;\n unsigned int v3;\n long long *v4;\n long long *v5;\n unsigned long long v6;\n long long v7;\n long long v8;\n long long v9;\n long long v10;\n uint32_t *v11;\n signed int v12;\n uint32_t *v13;\n long long v14;\n int i;\n long long v16;\n uint32_t *v17;\n uint32_t *v18;\n int v19;\n long long v20;\n long long v21;\n int v22;\n int v23;\n unsigned long long v24;\n long long *v25;\n long long v26;\n long long v27;\n unsigned long long v28;\n unsigned int v29;\n void *v30;\n long long v32;\n long long v33;\n unsigned int v34;\n v2 = malloc(4LL * a1);\n v3 = 8LL * (a1 + 1);\n v34 = v3;\n v4 = (long long *)malloc(v3);\n v5 = (long long *)malloc(v3);\n if (a1 < 0) {\n v32 = *v4;\n v9 = (unsigned int)a1;\n *(uint32_t *)(v32 + 8) = 0;\n *(uint64_t *)v32 = 0LL;\n v33 = *v5;\n *(uint32_t *)(v33 + 8) = 0;\n *(uint64_t *)v33 = 0LL;\n } else {\n v6 = 0LL;\n do {\n v4[v6 / 8] = (long long)calloc(3uLL, 4uLL);\n v5[v6 / 8] = (long long)calloc(3uLL, 4uLL);\n v6 += 8LL;\n } while (v6 != 8LL * a1 + 8);\n v7 = *v4;\n *(uint32_t *)(v7 + 8) = 0;\n *(uint64_t *)v7 = 0LL;\n v8 = *v5;\n *(uint32_t *)(v8 + 8) = 0;\n *(uint64_t *)v8 = 0LL;\n if (a1) {\n v9 = (unsigned int)a1;\n v10 = 0LL;\n do {\n v11 = (uint32_t *)v4[v10 + 1];\n v12 = ((int)v10 * ((int)v10 + 1) + 1) % 3u;\n v13 = (uint32_t *)v4[v10];\n v2[v10++] = v12;\n *v11 = *v13;\n v11[1] = v13[1];\n v11[2] = v13[2];\n ++v11[v12];\n } while (v10 != a1);\n } else {\n v9 = 0LL;\n }\n }\n v14 = 8 * v9 + 8;\n for (i = 2;; i = 1) {\n if (a1 <= 0) {\n if (a1) {\n v29 = **(uint32_t **)((char *)v4 + v34 - 8);\n goto LABEL_19;\n }\n } else {\n v16 = 0LL;\n do {\n v17 = (uint32_t *)v5[v16];\n v18 = (uint32_t *)v5[v16 + 1];\n v19 = v2[v16];\n v20 = v4[v16];\n *v18 = *v17;\n v18[1] = v17[1];\n v21 = 0LL;\n v18[2] = v17[2];\n do {\n v22 = (v19 + (int)v21) % 3;\n v23 = *(uint32_t *)(v20 + 4 * v21++);\n v18[v22] += v23;\n } while (v21 != 3);\n ++v16;\n } while (v9 != v16);\n }\n v24 = 0LL;\n do {\n v25 = (long long *)v5[v24 / 8];\n v26 = v4[v24 / 8];\n v24 += 8LL;\n v27 = *v25;\n *v25 = 0LL;\n *(uint64_t *)v26 = v27;\n LODWORD(v27) = *((uint32_t *)v25 + 2);\n *((uint32_t *)v25 + 2) = 0;\n *(uint32_t *)(v26 + 8) = v27;\n } while (v14 != v24);\n if (i == 1) break;\n }\n v28 = 0LL;\n v29 = **(uint32_t **)((char *)v4 + v34 - 8);\n do {\n free((void *)v4[v28 / 8]);\n v30 = (void *)v5[v28 / 8];\n v28 += 8LL;\n free(v30);\n } while (v28 != v14);\nLABEL_19:\n free(v4);\n free(v5);\n free(v2);\n return v29;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n uint32_t *v2;\n unsigned int v3;\n long long *v4;\n long long *v5;\n unsigned long long v6;\n long long v7;\n long long v8;\n long long v9;\n long long v10;\n uint32_t *v11;\n signed int v12;\n uint32_t *v13;\n long long v14;\n int i;\n long long v16;\n uint32_t *v17;\n uint32_t *v18;\n int v19;\n long long v20;\n long long v21;\n int v22;\n int v23;\n unsigned long long v24;\n long long *v25;\n long long v26;\n long long v27;\n unsigned long long v28;\n unsigned int v29;\n void *v30;\n long long v32;\n long long v33;\n unsigned int v34;\n v2 = malloc(4LL * a1);\n v3 = 8LL * (a1 + 1);\n v34 = v3;\n v4 = (long long *)malloc(v3);\n v5 = (long long *)malloc(v3);\n if (a1 < 0) {\n v32 = *v4;\n v9 = (unsigned int)a1;\n *(uint32_t *)(v32 + 8) = 0;\n *(uint64_t *)v32 = 0LL;\n v33 = *v5;\n *(uint32_t *)(v33 + 8) = 0;\n *(uint64_t *)v33 = 0LL;\n } else {\n v6 = 0LL;\n do {\n v4[v6 / 8] = (long long)calloc(3uLL, 4uLL);\n v5[v6 / 8] = (long long)calloc(3uLL, 4uLL);\n v6 += 8LL;\n } while (v6 != 8LL * a1 + 8);\n v7 = *v4;\n *(uint32_t *)(v7 + 8) = 0;\n *(uint64_t *)v7 = 0LL;\n v8 = *v5;\n *(uint32_t *)(v8 + 8) = 0;\n *(uint64_t *)v8 = 0LL;\n if (a1) {\n v9 = (unsigned int)a1;\n v10 = 0LL;\n do {\n v11 = (uint32_t *)v4[v10 + 1];\n v12 = ((int)v10 * ((int)v10 + 1) + 1) % 3u;\n v13 = (uint32_t *)v4[v10];\n v2[v10++] = v12;\n *v11 = *v13;\n v11[1] = v13[1];\n v11[2] = v13[2];\n ++v11[v12];\n } while (v10 != a1);\n } else {\n v9 = 0LL;\n }\n }\n v14 = 8 * v9 + 8;\n for (i = 2;; i = 1) {\n if (a1 <= 0) {\n if (a1) {\n v29 = **(uint32_t **)((char *)v4 + v34 - 8);\n goto LABEL_19;\n }\n } else {\n v16 = 0LL;\n do {\n v17 = (uint32_t *)v5[v16];\n v18 = (uint32_t *)v5[v16 + 1];\n v19 = v2[v16];\n v20 = v4[v16];\n *v18 = *v17;\n v18[1] = v17[1];\n v21 = 0LL;\n v18[2] = v17[2];\n do {\n v22 = (v19 + (int)v21) % 3;\n v23 = *(uint32_t *)(v20 + 4 * v21++);\n v18[v22] += v23;\n } while (v21 != 3);\n ++v16;\n } while (v9 != v16);\n }\n v24 = 0LL;\n do {\n v25 = (long long *)v5[v24 / 8];\n v26 = v4[v24 / 8];\n v24 += 8LL;\n v27 = *v25;\n *v25 = 0LL;\n *(uint64_t *)v26 = v27;\n LODWORD(v27) = *((uint32_t *)v25 + 2);\n *((uint32_t *)v25 + 2) = 0;\n *(uint32_t *)(v26 + 8) = v27;\n } while (v14 != v24);\n if (i == 1) break;\n }\n v28 = 0LL;\n v29 = **(uint32_t **)((char *)v4 + v34 - 8);\n do {\n free((void *)v4[v28 / 8]);\n v30 = (void *)v5[v28 / 8];\n v28 += 8LL;\n free(v30);\n } while (v28 != v14);\nLABEL_19:\n free(v4);\n free(v5);\n free(v2);\n return v29;\n}" + }, + { + "index": "HumanEval-C-147", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(int n) {\n int *a = (int *)malloc(n * sizeof(int));\n int **sum = (int **)malloc((n + 1) * sizeof(int *));\n int **sum2 = (int **)malloc((n + 1) * sizeof(int *));\n for (int i = 0; i <= n; i++) {\n sum[i] = (int *)calloc(3, sizeof(int));\n sum2[i] = (int *)calloc(3, sizeof(int));\n }\n sum[0][0] = sum[0][1] = sum[0][2] = 0;\n sum2[0][0] = sum2[0][1] = sum2[0][2] = 0;\n for (int i = 1; i <= n; i++) {\n a[i - 1] = (i * i - i + 1) % 3;\n for (int j = 0; j < 3; j++) {\n sum[i][j] = sum[i - 1][j];\n }\n sum[i][a[i - 1]] += 1;\n }\n for (int times = 1; times < 3; times++) {\n for (int i = 1; i <= n; i++) {\n for (int j = 0; j < 3; j++) {\n sum2[i][j] = sum2[i - 1][j];\n }\n if (i >= 1) {\n for (int j = 0; j <= 2; j++) {\n sum2[i][(a[i - 1] + j) % 3] += sum[i - 1][j];\n }\n }\n }\n for (int i = 0; i <= n; i++) {\n for (int j = 0; j < 3; j++) {\n sum[i][j] = sum2[i][j];\n sum2[i][j] = 0;\n }\n }\n }\n int result = sum[n][0];\n for (int i = 0; i <= n; ++i) {\n free(sum[i]);\n free(sum2[i]);\n }\n free(sum);\n free(sum2);\n free(a);\n return result;\n}", + "test": "#include \n\nint main() {\n assert(func0(5) == 1);\n assert(func0(6) == 4);\n assert(func0(10) == 36);\n assert(func0(100) == 53361);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\nmovsxd r13, edi\npush r12\nlea rdi, ds:0[r13*4]; size\nmov r14, r13\npush rbp\npush rbx\nsub rsp, 18h\ncall _malloc\nmov r12, rax\nlea eax, [r13+1]\ncdqe\nlea r15, ds:0[rax*8]\nmov rdi, r15; size\nmov [rsp+48h+var_40], r15\ncall _malloc\nmov rdi, r15; size\nmov rbx, rax\ncall _malloc\nmov rbp, rax\ntest r13d, r13d\njs loc_150E\nlea r13, ds:8[r13*8]\nxor r15d, r15d\nnop dword ptr [rax]\nloc_12E8:\nmov esi, 4; size\nmov edi, 3; nmemb\ncall _calloc\nmov esi, 4; size\nmov edi, 3; nmemb\nmov [rbx+r15], rax\ncall _calloc\nmov [rbp+r15+0], rax\nadd r15, 8\ncmp r15, r13\njnz short loc_12E8\nmov rax, [rbx]\nmov r9, [rbp+0]\nmov dword ptr [rax+8], 0\nmov qword ptr [rax], 0\nmov dword ptr [r9+8], 0\nmov qword ptr [r9], 0\ntest r14d, r14d\njz loc_154F\nmov r10d, r14d\nxor edx, edx\nxor edi, edi\nmov esi, 0AAAAAAABh\njmp short loc_135E\nloc_1358:\nmov rax, [rbx+rdx*8]\nmov edi, [rax]\nloc_135E:\nlea ecx, [rdx+1]\nimul ecx, edx\nlea eax, [rcx+1]\nmov rcx, rax\nimul rax, rsi\nshr rax, 21h\nlea r8d, [rax+rax*2]\nmov eax, ecx\nmov rcx, [rbx+rdx*8+8]\nsub eax, r8d\nmov r8, [rbx+rdx*8]\nmov [rcx], edi\nmov edi, [r8+4]\nmov [r12+rdx*4], eax\ncdqe\nadd rdx, 1\nmov [rcx+4], edi\nmov edi, [r8+8]\nmov [rcx+8], edi\nadd dword ptr [rcx+rax*4], 1\ncmp rdx, r10\njnz short loc_1358\nloc_13A7:\nlea r13, ds:8[r10*8]\nmov r11d, 2\nloc_13B5:\nmov rdx, r9\nxor esi, esi\ntest r14d, r14d\njle loc_153A\nnop dword ptr [rax+rax+00h]\nloc_13C8:\nmov rax, rdx\nmov rdx, [rbp+rsi*8+8]\nmov ecx, [rax]\nmov [rdx], ecx\nmov ecx, [rax+4]\nmov [rdx+4], ecx\nmovsxd rcx, dword ptr [r12+rsi*4]\nmov eax, [rax+8]\nmov [rdx+8], eax\nmov rax, rcx\nimul rcx, 55555556h\nmov edi, eax\nsar edi, 1Fh\nshr rcx, 20h\nsub ecx, edi\nlea edi, [rcx+rcx*2]\nmov ecx, eax\nsub ecx, edi\nmov rdi, [rbx+rsi*8]\nadd rsi, 1\nmovsxd rcx, ecx\nmov r8d, [rdi]\nadd [rdx+rcx*4], r8d\nlea ecx, [rax+1]\nadd eax, 2\nmovsxd r8, ecx\nmov r15d, ecx\nimul r8, 55555556h\nsar r15d, 1Fh\nshr r8, 20h\nsub r8d, r15d\nlea r8d, [r8+r8*2]\nsub ecx, r8d\nmov r8d, [rdi+4]\nmovsxd rcx, ecx\nadd [rdx+rcx*4], r8d\nmovsxd rcx, eax\nmov r8d, eax\nimul rcx, 55555556h\nsar r8d, 1Fh\nshr rcx, 20h\nsub ecx, r8d\nlea ecx, [rcx+rcx*2]\nsub eax, ecx\nmov ecx, [rdi+8]\ncdqe\nadd [rdx+rax*4], ecx\ncmp rsi, r10\njnz loc_13C8\nloc_1470:\nxor eax, eax\nnop word ptr [rax+rax+00h]\nloc_1478:\nmov rdx, [rbp+rax+0]\nmov rcx, [rbx+rax]\nadd rax, 8\nmov rsi, [rdx]\nmov qword ptr [rdx], 0\nmov [rcx], rsi\nmov esi, [rdx+8]\nmov dword ptr [rdx+8], 0\nmov [rcx+8], esi\ncmp rax, r13\njnz short loc_1478\ncmp r11d, 1\njz short loc_14B5\nmov r11d, 1\njmp loc_13B5\nloc_14B5:\nmov rax, [rsp+48h+var_40]\nxor r14d, r14d\nmov rax, [rbx+rax-8]\nmov r15d, [rax]\nnop dword ptr [rax]\nloc_14C8:\nmov rdi, [rbx+r14]; ptr\ncall _free\nmov rdi, [rbp+r14+0]; ptr\nadd r14, 8\ncall _free\ncmp r14, r13\njnz short loc_14C8\nloc_14E4:\nmov rdi, rbx; ptr\ncall _free\nmov rdi, rbp; ptr\ncall _free\nmov rdi, r12; ptr\ncall _free\nadd rsp, 18h\nmov eax, r15d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_150E:\nmov rax, [rbx]\nmov r9, [rbp+0]\nmov r10d, r13d\nmov dword ptr [rax+8], 0\nmov qword ptr [rax], 0\nmov dword ptr [r9+8], 0\nmov qword ptr [r9], 0\njmp loc_13A7\nloc_153A:\njz loc_1470\nmov rax, [rsp+48h+var_40]\nmov rax, [rbx+rax-8]\nmov r15d, [rax]\njmp short loc_14E4\nloc_154F:\nxor r10d, r10d\njmp loc_13A7", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n _DWORD *v2; // r12\n size_t v3; // r15\n __int64 *v4; // rbx\n _QWORD *v5; // rbp\n unsigned __int64 v6; // r15\n __int64 v7; // rax\n _DWORD *v8; // r9\n __int64 v9; // r10\n __int64 v10; // rdx\n int i; // edi\n _DWORD *v12; // rcx\n signed int v13; // eax\n __int64 v14; // r8\n int v15; // edi\n __int64 v16; // r13\n int j; // r11d\n _DWORD *v18; // rdx\n __int64 v19; // rsi\n _DWORD *v20; // rax\n int v21; // ecx\n _DWORD *v22; // rdi\n unsigned __int64 v23; // rax\n __int64 *v24; // rdx\n __int64 v25; // rcx\n __int64 v26; // rsi\n unsigned __int64 v27; // r14\n unsigned int v28; // r15d\n void *v29; // rdi\n __int64 v31; // rax\n size_t v32; // [rsp+8h] [rbp-40h]\n\n v2 = malloc(4LL * a1);\n v3 = 8LL * (a1 + 1);\n v32 = v3;\n v4 = (__int64 *)malloc(v3);\n v5 = malloc(v3);\n if ( a1 < 0 )\n {\n v31 = *v4;\n v8 = (_DWORD *)*v5;\n v9 = (unsigned int)a1;\n *(_DWORD *)(v31 + 8) = 0;\n *(_QWORD *)v31 = 0LL;\n v8[2] = 0;\n *(_QWORD *)v8 = 0LL;\n }\n else\n {\n v6 = 0LL;\n do\n {\n v4[v6 / 8] = (__int64)calloc(3uLL, 4uLL);\n v5[v6 / 8] = calloc(3uLL, 4uLL);\n v6 += 8LL;\n }\n while ( v6 != 8LL * a1 + 8 );\n v7 = *v4;\n v8 = (_DWORD *)*v5;\n *(_DWORD *)(v7 + 8) = 0;\n *(_QWORD *)v7 = 0LL;\n v8[2] = 0;\n *(_QWORD *)v8 = 0LL;\n if ( a1 )\n {\n v9 = (unsigned int)a1;\n v10 = 0LL;\n for ( i = 0; ; i = *(_DWORD *)v4[v10] )\n {\n v12 = (_DWORD *)v4[v10 + 1];\n v13 = ((int)v10 * ((int)v10 + 1) + 1) % 3u;\n v14 = v4[v10];\n *v12 = i;\n v15 = *(_DWORD *)(v14 + 4);\n v2[v10++] = v13;\n v12[1] = v15;\n v12[2] = *(_DWORD *)(v14 + 8);\n ++v12[v13];\n if ( v10 == a1 )\n break;\n }\n }\n else\n {\n v9 = 0LL;\n }\n }\n v16 = 8 * v9 + 8;\n for ( j = 2; ; j = 1 )\n {\n v18 = v8;\n v19 = 0LL;\n if ( a1 <= 0 )\n {\n if ( a1 )\n {\n v28 = **(_DWORD **)((char *)v4 + v32 - 8);\n goto LABEL_17;\n }\n }\n else\n {\n do\n {\n v20 = v18;\n v18 = (_DWORD *)v5[v19 + 1];\n *v18 = *v20;\n v18[1] = v20[1];\n v21 = v2[v19];\n v18[2] = v20[2];\n v22 = (_DWORD *)v4[v19++];\n v18[v21 % 3] += *v22;\n v18[(v21 + 1) % 3] += v22[1];\n v18[(v21 + 2) % 3] += v22[2];\n }\n while ( v19 != v9 );\n }\n v23 = 0LL;\n do\n {\n v24 = (__int64 *)v5[v23 / 8];\n v25 = v4[v23 / 8];\n v23 += 8LL;\n v26 = *v24;\n *v24 = 0LL;\n *(_QWORD *)v25 = v26;\n LODWORD(v26) = *((_DWORD *)v24 + 2);\n *((_DWORD *)v24 + 2) = 0;\n *(_DWORD *)(v25 + 8) = v26;\n }\n while ( v23 != v16 );\n if ( j == 1 )\n break;\n }\n v27 = 0LL;\n v28 = **(_DWORD **)((char *)v4 + v32 - 8);\n do\n {\n free((void *)v4[v27 / 8]);\n v29 = (void *)v5[v27 / 8];\n v27 += 8LL;\n free(v29);\n }\n while ( v27 != v16 );\nLABEL_17:\n free(v4);\n free(v5);\n free(v2);\n return v28;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\npush r15\npush r14\npush r13\nmovsxd r13, edi\npush r12\nlea rdi, ds:0[r13*4]; size\nmov r14, r13\npush rbp\npush rbx\nsub rsp, 18h\ncall _malloc\nmov r12, rax\nlea eax, [r13+1]\ncdqe\nlea r15, ds:0[rax*8]\nmov rdi, r15; size\nmov [rsp+48h+var_40], r15\ncall _malloc\nmov rdi, r15; size\nmov rbx, rax\ncall _malloc\nmov rbp, rax\ntest r13d, r13d\njs loc_150E\nlea r13, ds:8[r13*8]\nxor r15d, r15d\nnop dword ptr [rax]\nloc_12E8:\nmov esi, 4; size\nmov edi, 3; nmemb\ncall _calloc\nmov esi, 4; size\nmov edi, 3; nmemb\nmov [rbx+r15], rax\ncall _calloc\nmov [rbp+r15+0], rax\nadd r15, 8\ncmp r15, r13\njnz short loc_12E8\nmov rax, [rbx]\nmov r9, [rbp+0]\nmov dword ptr [rax+8], 0\nmov qword ptr [rax], 0\nmov dword ptr [r9+8], 0\nmov qword ptr [r9], 0\ntest r14d, r14d\njz loc_154F\nmov r10d, r14d\nxor edx, edx\nxor edi, edi\nmov esi, 0AAAAAAABh\njmp short loc_135E\nloc_1358:\nmov rax, [rbx+rdx*8]\nmov edi, [rax]\nloc_135E:\nlea ecx, [rdx+1]\nimul ecx, edx\nlea eax, [rcx+1]\nmov rcx, rax\nimul rax, rsi\nshr rax, 21h\nlea r8d, [rax+rax*2]\nmov eax, ecx\nmov rcx, [rbx+rdx*8+8]\nsub eax, r8d\nmov r8, [rbx+rdx*8]\nmov [rcx], edi\nmov edi, [r8+4]\nmov [r12+rdx*4], eax\ncdqe\nadd rdx, 1\nmov [rcx+4], edi\nmov edi, [r8+8]\nmov [rcx+8], edi\nadd dword ptr [rcx+rax*4], 1\ncmp rdx, r10\njnz short loc_1358\nloc_13A7:\nlea r13, ds:8[r10*8]\nmov r11d, 2\nloc_13B5:\nmov rdx, r9\nxor esi, esi\ntest r14d, r14d\njle loc_153A\nnop dword ptr [rax+rax+00h]\nloc_13C8:\nmov rax, rdx\nmov rdx, [rbp+rsi*8+8]\nmov ecx, [rax]\nmov [rdx], ecx\nmov ecx, [rax+4]\nmov [rdx+4], ecx\nmovsxd rcx, dword ptr [r12+rsi*4]\nmov eax, [rax+8]\nmov [rdx+8], eax\nmov rax, rcx\nimul rcx, 55555556h\nmov edi, eax\nsar edi, 1Fh\nshr rcx, 20h\nsub ecx, edi\nlea edi, [rcx+rcx*2]\nmov ecx, eax\nsub ecx, edi\nmov rdi, [rbx+rsi*8]\nadd rsi, 1\nmovsxd rcx, ecx\nmov r8d, [rdi]\nadd [rdx+rcx*4], r8d\nlea ecx, [rax+1]\nadd eax, 2\nmovsxd r8, ecx\nmov r15d, ecx\nimul r8, 55555556h\nsar r15d, 1Fh\nshr r8, 20h\nsub r8d, r15d\nlea r8d, [r8+r8*2]\nsub ecx, r8d\nmov r8d, [rdi+4]\nmovsxd rcx, ecx\nadd [rdx+rcx*4], r8d\nmovsxd rcx, eax\nmov r8d, eax\nimul rcx, 55555556h\nsar r8d, 1Fh\nshr rcx, 20h\nsub ecx, r8d\nlea ecx, [rcx+rcx*2]\nsub eax, ecx\nmov ecx, [rdi+8]\ncdqe\nadd [rdx+rax*4], ecx\ncmp rsi, r10\njnz loc_13C8\nloc_1470:\nxor eax, eax\nnop word ptr [rax+rax+00h]\nloc_1478:\nmov rdx, [rbp+rax+0]\nmov rcx, [rbx+rax]\nadd rax, 8\nmov rsi, [rdx]\nmov qword ptr [rdx], 0\nmov [rcx], rsi\nmov esi, [rdx+8]\nmov dword ptr [rdx+8], 0\nmov [rcx+8], esi\ncmp rax, r13\njnz short loc_1478\ncmp r11d, 1\njz short loc_14B5\nmov r11d, 1\njmp loc_13B5\nloc_14B5:\nmov rax, [rsp+48h+var_40]\nxor r14d, r14d\nmov rax, [rbx+rax-8]\nmov r15d, [rax]\nnop dword ptr [rax]\nloc_14C8:\nmov rdi, [rbx+r14]; ptr\ncall _free\nmov rdi, [rbp+r14+0]; ptr\nadd r14, 8\ncall _free\ncmp r14, r13\njnz short loc_14C8\nloc_14E4:\nmov rdi, rbx; ptr\ncall _free\nmov rdi, rbp; ptr\ncall _free\nmov rdi, r12; ptr\ncall _free\nadd rsp, 18h\nmov eax, r15d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_150E:\nmov rax, [rbx]\nmov r9, [rbp+0]\nmov r10d, r13d\nmov dword ptr [rax+8], 0\nmov qword ptr [rax], 0\nmov dword ptr [r9+8], 0\nmov qword ptr [r9], 0\njmp loc_13A7\nloc_153A:\njz loc_1470\nmov rax, [rsp+48h+var_40]\nmov rax, [rbx+rax-8]\nmov r15d, [rax]\njmp short loc_14E4\nloc_154F:\nxor r10d, r10d\njmp loc_13A7", + "ida_strip_pseudo": "__int64 __fastcall sub_1280(int a1)\n{\n _DWORD *v2; // r12\n size_t v3; // r15\n __int64 *v4; // rbx\n _QWORD *v5; // rbp\n unsigned __int64 v6; // r15\n __int64 v7; // rax\n _DWORD *v8; // r9\n __int64 v9; // r10\n __int64 v10; // rdx\n int i; // edi\n _DWORD *v12; // rcx\n signed int v13; // eax\n __int64 v14; // r8\n int v15; // edi\n __int64 v16; // r13\n int j; // r11d\n _DWORD *v18; // rdx\n __int64 v19; // rsi\n _DWORD *v20; // rax\n int v21; // ecx\n _DWORD *v22; // rdi\n unsigned __int64 v23; // rax\n __int64 *v24; // rdx\n __int64 v25; // rcx\n __int64 v26; // rsi\n unsigned __int64 v27; // r14\n unsigned int v28; // r15d\n void *v29; // rdi\n __int64 v31; // rax\n size_t v32; // [rsp+8h] [rbp-40h]\n\n v2 = malloc(4LL * a1);\n v3 = 8LL * (a1 + 1);\n v32 = v3;\n v4 = (__int64 *)malloc(v3);\n v5 = malloc(v3);\n if ( a1 < 0 )\n {\n v31 = *v4;\n v8 = (_DWORD *)*v5;\n v9 = (unsigned int)a1;\n *(_DWORD *)(v31 + 8) = 0;\n *(_QWORD *)v31 = 0LL;\n v8[2] = 0;\n *(_QWORD *)v8 = 0LL;\n }\n else\n {\n v6 = 0LL;\n do\n {\n v4[v6 / 8] = (__int64)calloc(3uLL, 4uLL);\n v5[v6 / 8] = calloc(3uLL, 4uLL);\n v6 += 8LL;\n }\n while ( v6 != 8LL * a1 + 8 );\n v7 = *v4;\n v8 = (_DWORD *)*v5;\n *(_DWORD *)(v7 + 8) = 0;\n *(_QWORD *)v7 = 0LL;\n v8[2] = 0;\n *(_QWORD *)v8 = 0LL;\n if ( a1 )\n {\n v9 = (unsigned int)a1;\n v10 = 0LL;\n for ( i = 0; ; i = *(_DWORD *)v4[v10] )\n {\n v12 = (_DWORD *)v4[v10 + 1];\n v13 = ((int)v10 * ((int)v10 + 1) + 1) % 3u;\n v14 = v4[v10];\n *v12 = i;\n v15 = *(_DWORD *)(v14 + 4);\n v2[v10++] = v13;\n v12[1] = v15;\n v12[2] = *(_DWORD *)(v14 + 8);\n ++v12[v13];\n if ( v10 == a1 )\n break;\n }\n }\n else\n {\n v9 = 0LL;\n }\n }\n v16 = 8 * v9 + 8;\n for ( j = 2; ; j = 1 )\n {\n v18 = v8;\n v19 = 0LL;\n if ( a1 <= 0 )\n {\n if ( a1 )\n {\n v28 = **(_DWORD **)((char *)v4 + v32 - 8);\n goto LABEL_17;\n }\n }\n else\n {\n do\n {\n v20 = v18;\n v18 = (_DWORD *)v5[v19 + 1];\n *v18 = *v20;\n v18[1] = v20[1];\n v21 = v2[v19];\n v18[2] = v20[2];\n v22 = (_DWORD *)v4[v19++];\n v18[v21 % 3] += *v22;\n v18[(v21 + 1) % 3] += v22[1];\n v18[(v21 + 2) % 3] += v22[2];\n }\n while ( v19 != v9 );\n }\n v23 = 0LL;\n do\n {\n v24 = (__int64 *)v5[v23 / 8];\n v25 = v4[v23 / 8];\n v23 += 8LL;\n v26 = *v24;\n *v24 = 0LL;\n *(_QWORD *)v25 = v26;\n LODWORD(v26) = *((_DWORD *)v24 + 2);\n *((_DWORD *)v24 + 2) = 0;\n *(_DWORD *)(v25 + 8) = v26;\n }\n while ( v23 != v16 );\n if ( j == 1 )\n break;\n }\n v27 = 0LL;\n v28 = **(_DWORD **)((char *)v4 + v32 - 8);\n do\n {\n free((void *)v4[v27 / 8]);\n v29 = (void *)v5[v27 / 8];\n v27 += 8LL;\n free(v29);\n }\n while ( v27 != v16 );\nLABEL_17:\n free(v4);\n free(v5);\n free(v2);\n return v28;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1280(int a1) {\n uint32_t *v2;\n unsigned int v3;\n long long *v4;\n uint64_t *v5;\n unsigned long long v6;\n long long v7;\n uint32_t *v8;\n long long v9;\n long long v10;\n int i;\n uint32_t *v12;\n signed int v13;\n long long v14;\n int v15;\n long long v16;\n int j;\n uint32_t *v18;\n long long v19;\n uint32_t *v20;\n int v21;\n uint32_t *v22;\n unsigned long long v23;\n long long *v24;\n long long v25;\n long long v26;\n unsigned long long v27;\n unsigned int v28;\n void *v29;\n long long v31;\n unsigned int v32;\n v2 = malloc(4LL * a1);\n v3 = 8LL * (a1 + 1);\n v32 = v3;\n v4 = (long long *)malloc(v3);\n v5 = malloc(v3);\n if (a1 < 0) {\n v31 = *v4;\n v8 = (uint32_t *)*v5;\n v9 = (unsigned int)a1;\n *(uint32_t *)(v31 + 8) = 0;\n *(uint64_t *)v31 = 0LL;\n v8[2] = 0;\n *(uint64_t *)v8 = 0LL;\n } else {\n v6 = 0LL;\n do {\n v4[v6 / 8] = (long long)calloc(3uLL, 4uLL);\n v5[v6 / 8] = calloc(3uLL, 4uLL);\n v6 += 8LL;\n } while (v6 != 8LL * a1 + 8);\n v7 = *v4;\n v8 = (uint32_t *)*v5;\n *(uint32_t *)(v7 + 8) = 0;\n *(uint64_t *)v7 = 0LL;\n v8[2] = 0;\n *(uint64_t *)v8 = 0LL;\n if (a1) {\n v9 = (unsigned int)a1;\n v10 = 0LL;\n for (i = 0;; i = *(uint32_t *)v4[v10]) {\n v12 = (uint32_t *)v4[v10 + 1];\n v13 = ((int)v10 * ((int)v10 + 1) + 1) % 3u;\n v14 = v4[v10];\n *v12 = i;\n v15 = *(uint32_t *)(v14 + 4);\n v2[v10++] = v13;\n v12[1] = v15;\n v12[2] = *(uint32_t *)(v14 + 8);\n ++v12[v13];\n if (v10 == a1) break;\n }\n } else {\n v9 = 0LL;\n }\n }\n v16 = 8 * v9 + 8;\n for (j = 2;; j = 1) {\n v18 = v8;\n v19 = 0LL;\n if (a1 <= 0) {\n if (a1) {\n v28 = **(uint32_t **)((char *)v4 + v32 - 8);\n goto LABEL_17;\n }\n } else {\n do {\n v20 = v18;\n v18 = (uint32_t *)v5[v19 + 1];\n *v18 = *v20;\n v18[1] = v20[1];\n v21 = v2[v19];\n v18[2] = v20[2];\n v22 = (uint32_t *)v4[v19++];\n v18[v21 % 3] += *v22;\n v18[(v21 + 1) % 3] += v22[1];\n v18[(v21 + 2) % 3] += v22[2];\n } while (v19 != v9);\n }\n v23 = 0LL;\n do {\n v24 = (long long *)v5[v23 / 8];\n v25 = v4[v23 / 8];\n v23 += 8LL;\n v26 = *v24;\n *v24 = 0LL;\n *(uint64_t *)v25 = v26;\n LODWORD(v26) = *((uint32_t *)v24 + 2);\n *((uint32_t *)v24 + 2) = 0;\n *(uint32_t *)(v25 + 8) = v26;\n } while (v23 != v16);\n if (j == 1) break;\n }\n v27 = 0LL;\n v28 = **(uint32_t **)((char *)v4 + v32 - 8);\n do {\n free((void *)v4[v27 / 8]);\n v29 = (void *)v5[v27 / 8];\n v27 += 8LL;\n free(v29);\n } while (v27 != v16);\nLABEL_17:\n free(v4);\n free(v5);\n free(v2);\n return v28;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n uint32_t *v2;\n unsigned int v3;\n long long *v4;\n uint64_t *v5;\n unsigned long long v6;\n long long v7;\n uint32_t *v8;\n long long v9;\n long long v10;\n int i;\n uint32_t *v12;\n signed int v13;\n long long v14;\n int v15;\n long long v16;\n int j;\n uint32_t *v18;\n long long v19;\n uint32_t *v20;\n int v21;\n uint32_t *v22;\n unsigned long long v23;\n long long *v24;\n long long v25;\n long long v26;\n unsigned long long v27;\n unsigned int v28;\n void *v29;\n long long v31;\n unsigned int v32;\n v2 = malloc(4LL * a1);\n v3 = 8LL * (a1 + 1);\n v32 = v3;\n v4 = (long long *)malloc(v3);\n v5 = malloc(v3);\n if (a1 < 0) {\n v31 = *v4;\n v8 = (uint32_t *)*v5;\n v9 = (unsigned int)a1;\n *(uint32_t *)(v31 + 8) = 0;\n *(uint64_t *)v31 = 0LL;\n v8[2] = 0;\n *(uint64_t *)v8 = 0LL;\n } else {\n v6 = 0LL;\n do {\n v4[v6 / 8] = (long long)calloc(3uLL, 4uLL);\n v5[v6 / 8] = calloc(3uLL, 4uLL);\n v6 += 8LL;\n } while (v6 != 8LL * a1 + 8);\n v7 = *v4;\n v8 = (uint32_t *)*v5;\n *(uint32_t *)(v7 + 8) = 0;\n *(uint64_t *)v7 = 0LL;\n v8[2] = 0;\n *(uint64_t *)v8 = 0LL;\n if (a1) {\n v9 = (unsigned int)a1;\n v10 = 0LL;\n for (i = 0;; i = *(uint32_t *)v4[v10]) {\n v12 = (uint32_t *)v4[v10 + 1];\n v13 = ((int)v10 * ((int)v10 + 1) + 1) % 3u;\n v14 = v4[v10];\n *v12 = i;\n v15 = *(uint32_t *)(v14 + 4);\n v2[v10++] = v13;\n v12[1] = v15;\n v12[2] = *(uint32_t *)(v14 + 8);\n ++v12[v13];\n if (v10 == a1) break;\n }\n } else {\n v9 = 0LL;\n }\n }\n v16 = 8 * v9 + 8;\n for (j = 2;; j = 1) {\n v18 = v8;\n v19 = 0LL;\n if (a1 <= 0) {\n if (a1) {\n v28 = **(uint32_t **)((char *)v4 + v32 - 8);\n goto LABEL_17;\n }\n } else {\n do {\n v20 = v18;\n v18 = (uint32_t *)v5[v19 + 1];\n *v18 = *v20;\n v18[1] = v20[1];\n v21 = v2[v19];\n v18[2] = v20[2];\n v22 = (uint32_t *)v4[v19++];\n v18[v21 % 3] += *v22;\n v18[(v21 + 1) % 3] += v22[1];\n v18[(v21 + 2) % 3] += v22[2];\n } while (v19 != v9);\n }\n v23 = 0LL;\n do {\n v24 = (long long *)v5[v23 / 8];\n v25 = v4[v23 / 8];\n v23 += 8LL;\n v26 = *v24;\n *v24 = 0LL;\n *(uint64_t *)v25 = v26;\n LODWORD(v26) = *((uint32_t *)v24 + 2);\n *((uint32_t *)v24 + 2) = 0;\n *(uint32_t *)(v25 + 8) = v26;\n } while (v23 != v16);\n if (j == 1) break;\n }\n v27 = 0LL;\n v28 = **(uint32_t **)((char *)v4 + v32 - 8);\n do {\n free((void *)v4[v27 / 8]);\n v29 = (void *)v5[v27 / 8];\n v27 += 8LL;\n free(v29);\n } while (v27 != v16);\nLABEL_17:\n free(v4);\n free(v5);\n free(v2);\n return v28;\n}" + }, + { + "index": "HumanEval-C-148", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char** func0(const char* planet1, const char* planet2, int* returnSize) {\n const char* planets[] = {\"Mercury\", \"Venus\", \"Earth\", \"Mars\",\n \"Jupiter\", \"Saturn\", \"Uranus\", \"Neptune\"};\n int pos1 = -1, pos2 = -1, m;\n for (m = 0; m < 8; m++) {\n if (strcmp(planets[m], planet1) == 0) pos1 = m;\n if (strcmp(planets[m], planet2) == 0) pos2 = m;\n }\n if (pos1 == -1 || pos2 == -1 || pos1 == pos2) {\n *returnSize = 0;\n return NULL;\n }\n if (pos1 > pos2) {\n int temp = pos1;\n pos1 = pos2;\n pos2 = temp;\n }\n *returnSize = pos2 - pos1 - 1;\n if (*returnSize <= 0) {\n *returnSize = 0;\n return NULL;\n }\n char** out = malloc(*returnSize * sizeof(char*));\n for (m = pos1 + 1; m < pos2; m++) {\n out[m - pos1 - 1] = (char*)planets[m];\n }\n return out;\n}", + "test": "#include \n#include \n#include \n#include \n\nint issame(char** a, const char** b, int a_size, int b_size) {\n if (a_size != b_size) return 0;\n for (int i = 0; i < a_size; i++) {\n if (strcmp(a[i], b[i]) != 0) return 0;\n }\n return 1;\n}\n\nint main() {\n int size;\n char** result;\n\n const char* test1[] = {\"Saturn\", \"Uranus\"};\n result = func0(\"Jupiter\", \"Neptune\", &size);\n assert(issame(result, test1, size, 2));\n free(result);\n\n const char* test2[] = {\"Venus\"};\n result = func0(\"Earth\", \"Mercury\", &size);\n assert(issame(result, test2, size, 1));\n free(result);\n\n const char* test3[] = {\"Venus\", \"Earth\", \"Mars\", \"Jupiter\", \"Saturn\"};\n result = func0(\"Mercury\", \"Uranus\", &size);\n assert(issame(result, test3, size, 5));\n free(result);\n\n const char* test4[] = {\"Earth\", \"Mars\", \"Jupiter\", \"Saturn\", \"Uranus\"};\n result = func0(\"Neptune\", \"Venus\", &size);\n assert(issame(result, test4, size, 5));\n free(result);\n\n result = func0(\"Earth\", \"Earth\", &size);\n assert(size == 0 && result == NULL);\n\n result = func0(\"Mars\", \"Earth\", &size);\n assert(size == 0 && result == NULL);\n\n result = func0(\"Jupiter\", \"Makemake\", &size);\n assert(size == 0 && result == NULL);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 90h\nmov [rbp+s2], rdi\nmov [rbp+var_80], rsi\nmov [rbp+var_88], rdx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aMercury; \"Mercury\"\nmov [rbp+s1], rax\nlea rax, aVenus; \"Venus\"\nmov [rbp+var_48], rax\nlea rax, aEarth; \"Earth\"\nmov [rbp+var_40], rax\nlea rax, aMars; \"Mars\"\nmov [rbp+var_38], rax\nlea rax, aJupiter; \"Jupiter\"\nmov [rbp+var_30], rax\nlea rax, aSaturn; \"Saturn\"\nmov [rbp+var_28], rax\nlea rax, aUranus; \"Uranus\"\nmov [rbp+var_20], rax\nlea rax, aNeptune; \"Neptune\"\nmov [rbp+var_18], rax\nmov [rbp+var_68], 0FFFFFFFFh\nmov [rbp+var_64], 0FFFFFFFFh\nmov [rbp+var_60], 0\njmp short loc_12AF\nloc_1265:\nmov eax, [rbp+var_60]\ncdqe\nmov rax, [rbp+rax*8+s1]\nmov rdx, [rbp+s2]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1288\nmov eax, [rbp+var_60]\nmov [rbp+var_68], eax\nloc_1288:\nmov eax, [rbp+var_60]\ncdqe\nmov rax, [rbp+rax*8+s1]\nmov rdx, [rbp+var_80]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_12AB\nmov eax, [rbp+var_60]\nmov [rbp+var_64], eax\nloc_12AB:\nadd [rbp+var_60], 1\nloc_12AF:\ncmp [rbp+var_60], 7\njle short loc_1265\ncmp [rbp+var_68], 0FFFFFFFFh\njz short loc_12C9\ncmp [rbp+var_64], 0FFFFFFFFh\njz short loc_12C9\nmov eax, [rbp+var_68]\ncmp eax, [rbp+var_64]\njnz short loc_12E0\nloc_12C9:\nmov rax, [rbp+var_88]\nmov dword ptr [rax], 0\nmov eax, 0\njmp loc_1387\nloc_12E0:\nmov eax, [rbp+var_68]\ncmp eax, [rbp+var_64]\njle short loc_12FA\nmov eax, [rbp+var_68]\nmov [rbp+var_5C], eax\nmov eax, [rbp+var_64]\nmov [rbp+var_68], eax\nmov eax, [rbp+var_5C]\nmov [rbp+var_64], eax\nloc_12FA:\nmov eax, [rbp+var_64]\nsub eax, [rbp+var_68]\nlea edx, [rax-1]\nmov rax, [rbp+var_88]\nmov [rax], edx\nmov rax, [rbp+var_88]\nmov eax, [rax]\ntest eax, eax\njg short loc_132D\nmov rax, [rbp+var_88]\nmov dword ptr [rax], 0\nmov eax, 0\njmp short loc_1387\nloc_132D:\nmov rax, [rbp+var_88]\nmov eax, [rax]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_58], rax\nmov eax, [rbp+var_68]\nadd eax, 1\nmov [rbp+var_60], eax\njmp short loc_137B\nloc_1353:\nmov eax, [rbp+var_60]\nsub eax, [rbp+var_68]\ncdqe\nshl rax, 3\nlea rdx, [rax-8]\nmov rax, [rbp+var_58]\nadd rdx, rax\nmov eax, [rbp+var_60]\ncdqe\nmov rax, [rbp+rax*8+s1]\nmov [rdx], rax\nadd [rbp+var_60], 1\nloc_137B:\nmov eax, [rbp+var_60]\ncmp eax, [rbp+var_64]\njl short loc_1353\nmov rax, [rbp+var_58]\nloc_1387:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_139B\ncall ___stack_chk_fail\nlocret_139B:\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(const char *a1, const char *a2, int *a3)\n{\n int v5; // [rsp+28h] [rbp-68h]\n int v6; // [rsp+2Ch] [rbp-64h]\n int i; // [rsp+30h] [rbp-60h]\n int j; // [rsp+30h] [rbp-60h]\n int v9; // [rsp+34h] [rbp-5Ch]\n _QWORD *v10; // [rsp+38h] [rbp-58h]\n char *s1[10]; // [rsp+40h] [rbp-50h]\n\n s1[9] = (char *)__readfsqword(0x28u);\n s1[0] = \"Mercury\";\n s1[1] = \"Venus\";\n s1[2] = \"Earth\";\n s1[3] = \"Mars\";\n s1[4] = \"Jupiter\";\n s1[5] = \"Saturn\";\n s1[6] = \"Uranus\";\n s1[7] = \"Neptune\";\n v5 = -1;\n v6 = -1;\n for ( i = 0; i <= 7; ++i )\n {\n if ( !strcmp(s1[i], a1) )\n v5 = i;\n if ( !strcmp(s1[i], a2) )\n v6 = i;\n }\n if ( v5 == -1 || v6 == -1 || v5 == v6 )\n {\n *a3 = 0;\n return 0LL;\n }\n else\n {\n if ( v5 > v6 )\n {\n v9 = v5;\n v5 = v6;\n v6 = v9;\n }\n *a3 = v6 - v5 - 1;\n if ( *a3 > 0 )\n {\n v10 = malloc(8LL * *a3);\n for ( j = v5 + 1; j < v6; ++j )\n v10[j - v5 - 1] = s1[j];\n return v10;\n }\n else\n {\n *a3 = 0;\n return 0LL;\n }\n }\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 90h\nmov [rbp+s2], rdi\nmov [rbp+var_80], rsi\nmov [rbp+var_88], rdx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aMercury; \"Mercury\"\nmov [rbp+s1], rax\nlea rax, aVenus; \"Venus\"\nmov [rbp+var_48], rax\nlea rax, aEarth; \"Earth\"\nmov [rbp+var_40], rax\nlea rax, aMars; \"Mars\"\nmov [rbp+var_38], rax\nlea rax, aJupiter; \"Jupiter\"\nmov [rbp+var_30], rax\nlea rax, aSaturn; \"Saturn\"\nmov [rbp+var_28], rax\nlea rax, aUranus; \"Uranus\"\nmov [rbp+var_20], rax\nlea rax, aNeptune; \"Neptune\"\nmov [rbp+var_18], rax\nmov [rbp+var_68], 0FFFFFFFFh\nmov [rbp+var_64], 0FFFFFFFFh\nmov [rbp+var_60], 0\njmp short loc_12AF\nloc_1265:\nmov eax, [rbp+var_60]\ncdqe\nmov rax, [rbp+rax*8+s1]\nmov rdx, [rbp+s2]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1288\nmov eax, [rbp+var_60]\nmov [rbp+var_68], eax\nloc_1288:\nmov eax, [rbp+var_60]\ncdqe\nmov rax, [rbp+rax*8+s1]\nmov rdx, [rbp+var_80]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_12AB\nmov eax, [rbp+var_60]\nmov [rbp+var_64], eax\nloc_12AB:\nadd [rbp+var_60], 1\nloc_12AF:\ncmp [rbp+var_60], 7\njle short loc_1265\ncmp [rbp+var_68], 0FFFFFFFFh\njz short loc_12C9\ncmp [rbp+var_64], 0FFFFFFFFh\njz short loc_12C9\nmov eax, [rbp+var_68]\ncmp eax, [rbp+var_64]\njnz short loc_12E0\nloc_12C9:\nmov rax, [rbp+var_88]\nmov dword ptr [rax], 0\nmov eax, 0\njmp loc_1387\nloc_12E0:\nmov eax, [rbp+var_68]\ncmp eax, [rbp+var_64]\njle short loc_12FA\nmov eax, [rbp+var_68]\nmov [rbp+var_5C], eax\nmov eax, [rbp+var_64]\nmov [rbp+var_68], eax\nmov eax, [rbp+var_5C]\nmov [rbp+var_64], eax\nloc_12FA:\nmov eax, [rbp+var_64]\nsub eax, [rbp+var_68]\nlea edx, [rax-1]\nmov rax, [rbp+var_88]\nmov [rax], edx\nmov rax, [rbp+var_88]\nmov eax, [rax]\ntest eax, eax\njg short loc_132D\nmov rax, [rbp+var_88]\nmov dword ptr [rax], 0\nmov eax, 0\njmp short loc_1387\nloc_132D:\nmov rax, [rbp+var_88]\nmov eax, [rax]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_58], rax\nmov eax, [rbp+var_68]\nadd eax, 1\nmov [rbp+var_60], eax\njmp short loc_137B\nloc_1353:\nmov eax, [rbp+var_60]\nsub eax, [rbp+var_68]\ncdqe\nshl rax, 3\nlea rdx, [rax-8]\nmov rax, [rbp+var_58]\nadd rdx, rax\nmov eax, [rbp+var_60]\ncdqe\nmov rax, [rbp+rax*8+s1]\nmov [rdx], rax\nadd [rbp+var_60], 1\nloc_137B:\nmov eax, [rbp+var_60]\ncmp eax, [rbp+var_64]\njl short loc_1353\nmov rax, [rbp+var_58]\nloc_1387:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_139B\ncall ___stack_chk_fail\nlocret_139B:\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11C9(const char *a1, const char *a2, int *a3)\n{\n int v5; // [rsp+28h] [rbp-68h]\n int v6; // [rsp+2Ch] [rbp-64h]\n int i; // [rsp+30h] [rbp-60h]\n int j; // [rsp+30h] [rbp-60h]\n int v9; // [rsp+34h] [rbp-5Ch]\n _QWORD *v10; // [rsp+38h] [rbp-58h]\n char *s1[10]; // [rsp+40h] [rbp-50h]\n\n s1[9] = (char *)__readfsqword(0x28u);\n s1[0] = \"Mercury\";\n s1[1] = \"Venus\";\n s1[2] = \"Earth\";\n s1[3] = \"Mars\";\n s1[4] = \"Jupiter\";\n s1[5] = \"Saturn\";\n s1[6] = \"Uranus\";\n s1[7] = \"Neptune\";\n v5 = -1;\n v6 = -1;\n for ( i = 0; i <= 7; ++i )\n {\n if ( !strcmp(s1[i], a1) )\n v5 = i;\n if ( !strcmp(s1[i], a2) )\n v6 = i;\n }\n if ( v5 == -1 || v6 == -1 || v5 == v6 )\n {\n *a3 = 0;\n return 0LL;\n }\n else\n {\n if ( v5 > v6 )\n {\n v9 = v5;\n v5 = v6;\n v6 = v9;\n }\n *a3 = v6 - v5 - 1;\n if ( *a3 > 0 )\n {\n v10 = malloc(8LL * *a3);\n for ( j = v5 + 1; j < v6; ++j )\n v10[j - v5 - 1] = s1[j];\n return v10;\n }\n else\n {\n *a3 = 0;\n return 0LL;\n }\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11C9(const char *a1, const char *a2, int *a3) {\n int v5;\n int v6;\n int i;\n int j;\n int v9;\n uint64_t *v10;\n char *s1[10];\n s1[9] = (char *)__readfsqword(40u);\n s1[0] = \"Mercury\";\n s1[1] = \"Venus\";\n s1[2] = \"Earth\";\n s1[3] = \"Mars\";\n s1[4] = \"Jupiter\";\n s1[5] = \"Saturn\";\n s1[6] = \"Uranus\";\n s1[7] = \"Neptune\";\n v5 = -1;\n v6 = -1;\n for (i = 0; i <= 7; ++i) {\n if (!strcmp(s1[i], a1)) v5 = i;\n if (!strcmp(s1[i], a2)) v6 = i;\n }\n if (v5 == -1 || v6 == -1 || v5 == v6) {\n *a3 = 0;\n return 0LL;\n } else {\n if (v5 > v6) {\n v9 = v5;\n v5 = v6;\n v6 = v9;\n }\n *a3 = v6 - v5 - 1;\n if (*a3 > 0) {\n v10 = malloc(8LL * *a3);\n for (j = v5 + 1; j < v6; ++j) v10[j - v5 - 1] = s1[j];\n return v10;\n } else {\n *a3 = 0;\n return 0LL;\n }\n }\n}", + "ida_pseudo_norm": "uint64_t *func0(const char *a1, const char *a2, int *a3) {\n int v5;\n int v6;\n int i;\n int j;\n int v9;\n uint64_t *v10;\n char *s1[10];\n s1[9] = (char *)__readfsqword(40u);\n s1[0] = \"Mercury\";\n s1[1] = \"Venus\";\n s1[2] = \"Earth\";\n s1[3] = \"Mars\";\n s1[4] = \"Jupiter\";\n s1[5] = \"Saturn\";\n s1[6] = \"Uranus\";\n s1[7] = \"Neptune\";\n v5 = -1;\n v6 = -1;\n for (i = 0; i <= 7; ++i) {\n if (!strcmp(s1[i], a1)) v5 = i;\n if (!strcmp(s1[i], a2)) v6 = i;\n }\n if (v5 == -1 || v6 == -1 || v5 == v6) {\n *a3 = 0;\n return 0LL;\n } else {\n if (v5 > v6) {\n v9 = v5;\n v5 = v6;\n v6 = v9;\n }\n *a3 = v6 - v5 - 1;\n if (*a3 > 0) {\n v10 = malloc(8LL * *a3);\n for (j = v5 + 1; j < v6; ++j) v10[j - v5 - 1] = s1[j];\n return v10;\n } else {\n *a3 = 0;\n return 0LL;\n }\n }\n}" + }, + { + "index": "HumanEval-C-148", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char** func0(const char* planet1, const char* planet2, int* returnSize) {\n const char* planets[] = {\"Mercury\", \"Venus\", \"Earth\", \"Mars\",\n \"Jupiter\", \"Saturn\", \"Uranus\", \"Neptune\"};\n int pos1 = -1, pos2 = -1, m;\n for (m = 0; m < 8; m++) {\n if (strcmp(planets[m], planet1) == 0) pos1 = m;\n if (strcmp(planets[m], planet2) == 0) pos2 = m;\n }\n if (pos1 == -1 || pos2 == -1 || pos1 == pos2) {\n *returnSize = 0;\n return NULL;\n }\n if (pos1 > pos2) {\n int temp = pos1;\n pos1 = pos2;\n pos2 = temp;\n }\n *returnSize = pos2 - pos1 - 1;\n if (*returnSize <= 0) {\n *returnSize = 0;\n return NULL;\n }\n char** out = malloc(*returnSize * sizeof(char*));\n for (m = pos1 + 1; m < pos2; m++) {\n out[m - pos1 - 1] = (char*)planets[m];\n }\n return out;\n}", + "test": "#include \n#include \n#include \n#include \n\nint issame(char** a, const char** b, int a_size, int b_size) {\n if (a_size != b_size) return 0;\n for (int i = 0; i < a_size; i++) {\n if (strcmp(a[i], b[i]) != 0) return 0;\n }\n return 1;\n}\n\nint main() {\n int size;\n char** result;\n\n const char* test1[] = {\"Saturn\", \"Uranus\"};\n result = func0(\"Jupiter\", \"Neptune\", &size);\n assert(issame(result, test1, size, 2));\n free(result);\n\n const char* test2[] = {\"Venus\"};\n result = func0(\"Earth\", \"Mercury\", &size);\n assert(issame(result, test2, size, 1));\n free(result);\n\n const char* test3[] = {\"Venus\", \"Earth\", \"Mars\", \"Jupiter\", \"Saturn\"};\n result = func0(\"Mercury\", \"Uranus\", &size);\n assert(issame(result, test3, size, 5));\n free(result);\n\n const char* test4[] = {\"Earth\", \"Mars\", \"Jupiter\", \"Saturn\", \"Uranus\"};\n result = func0(\"Neptune\", \"Venus\", &size);\n assert(issame(result, test4, size, 5));\n free(result);\n\n result = func0(\"Earth\", \"Earth\", &size);\n assert(size == 0 && result == NULL);\n\n result = func0(\"Mars\", \"Earth\", &size);\n assert(size == 0 && result == NULL);\n\n result = func0(\"Jupiter\", \"Makemake\", &size);\n assert(size == 0 && result == NULL);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 68h\nmov r15, rdi\nmov [rsp+98h+s2], rsi\nmov [rsp+98h+var_90], rdx\nmov rax, fs:28h\nmov [rsp+98h+var_40], rax\nxor eax, eax\nlea rax, aMercury; \"Mercury\"\nmov [rsp+98h+s1], rax\nlea rax, aVenus; \"Venus\"\nmov [rsp+98h+var_80], rax\nlea rax, aEarth; \"Earth\"\nmov [rsp+98h+var_78], rax\nlea rax, aMars; \"Mars\"\nmov [rsp+98h+var_70], rax\nlea rax, s2; \"Jupiter\"\nmov [rsp+98h+var_68], rax\nlea rax, aSaturn; \"Saturn\"\nmov [rsp+98h+var_60], rax\nlea rax, aUranus; \"Uranus\"\nmov [rsp+98h+var_58], rax\nlea rax, aNeptune; \"Neptune\"\nmov [rsp+98h+var_50], rax\nmov ebx, 0\nmov r13d, 0FFFFFFFFh\nmov ebp, 0FFFFFFFFh\nloc_1267:\nmov r12, [rsp+rbx*8+98h+s1]\nmov rsi, r15; s2\nmov rdi, r12; s1\ncall _strcmp\ntest eax, eax\ncmovz ebp, ebx\nmov rsi, [rsp+98h+s2]; s2\nmov rdi, r12; s1\ncall _strcmp\ntest eax, eax\ncmovz r13d, ebx\nadd rbx, 1\ncmp rbx, 8\njnz short loc_1267\ncmp r13d, 0FFFFFFFFh\nsetz al\ncmp ebp, r13d\nsetz dl\nor al, dl\njnz loc_1330\ncmp ebp, 0FFFFFFFFh\njz short loc_1330\ncmp ebp, r13d\njg short loc_12BF\nmov eax, r13d\nmov r13d, ebp\nmov ebp, eax\nloc_12BF:\nmov eax, ebp\nsub eax, r13d\nsub eax, 1\nmov rcx, [rsp+98h+var_90]\nmov [rcx], eax\ntest eax, eax\njle short loc_1342\ncdqe\nlea rdi, ds:0[rax*8]; size\ncall _malloc\nlea edx, [r13+1]\ncmp ebp, edx\njle short loc_1311\nsub ebp, 2\nsub ebp, r13d\nmovsxd r13, r13d\nlea rsi, [rsp+r13*8+98h+s1]\nmov edx, 0\nloc_12FC:\nmov rcx, [rsi+rdx*8+8]\nmov [rax+rdx*8], rcx\nmov rcx, rdx\nadd rdx, 1\ncmp rcx, rbp\njnz short loc_12FC\nloc_1311:\nmov rdx, [rsp+98h+var_40]\nsub rdx, fs:28h\njnz short loc_134F\nadd rsp, 68h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1330:\nmov rax, [rsp+98h+var_90]\nmov dword ptr [rax], 0\nmov eax, 0\njmp short loc_1311\nloc_1342:\nmov dword ptr [rcx], 0\nmov eax, 0\njmp short loc_1311\nloc_134F:\ncall ___stack_chk_fail", + "ida_pseudo": "_QWORD *__fastcall func0(char *s2, const char *a2, int *a3)\n{\n __int64 v3; // rbx\n int v4; // r13d\n int v5; // ebp\n const char *v6; // r12\n int v7; // eax\n int v8; // eax\n _QWORD *result; // rax\n int v10; // ebp\n __int64 v11; // rdx\n __int64 v12; // rcx\n char *s1[17]; // [rsp+10h] [rbp-88h] BYREF\n\n s1[9] = (char *)__readfsqword(0x28u);\n s1[0] = \"Mercury\";\n s1[1] = \"Venus\";\n s1[2] = \"Earth\";\n s1[3] = \"Mars\";\n s1[4] = \"Jupiter\";\n s1[5] = \"Saturn\";\n s1[6] = \"Uranus\";\n s1[7] = \"Neptune\";\n v3 = 0LL;\n v4 = -1;\n v5 = -1;\n do\n {\n v6 = s1[v3];\n if ( !strcmp(v6, s2) )\n v5 = v3;\n if ( !strcmp(v6, a2) )\n v4 = v3;\n ++v3;\n }\n while ( v3 != 8 );\n if ( v5 == v4 || v4 == -1 || v5 == -1 )\n {\n *a3 = 0;\n return 0LL;\n }\n else\n {\n if ( v5 <= v4 )\n {\n v7 = v4;\n v4 = v5;\n v5 = v7;\n }\n v8 = v5 - v4 - 1;\n *a3 = v8;\n if ( v8 <= 0 )\n {\n *a3 = 0;\n return 0LL;\n }\n else\n {\n result = malloc(8LL * v8);\n if ( v5 > v4 + 1 )\n {\n v10 = v5 - 2 - v4;\n v11 = 0LL;\n do\n {\n result[v11] = (&s1[v4])[v11 + 1];\n v12 = v11++;\n }\n while ( v12 != v10 );\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 68h\nmov r15, rdi\nmov [rsp+98h+s2], rsi\nmov [rsp+98h+var_90], rdx\nmov rax, fs:28h\nmov [rsp+98h+var_40], rax\nxor eax, eax\nlea rax, aMercury; \"Mercury\"\nmov [rsp+98h+s1], rax\nlea rax, aVenus; \"Venus\"\nmov [rsp+98h+var_80], rax\nlea rax, aEarth; \"Earth\"\nmov [rsp+98h+var_78], rax\nlea rax, aMars; \"Mars\"\nmov [rsp+98h+var_70], rax\nlea rax, s2; \"Jupiter\"\nmov [rsp+98h+var_68], rax\nlea rax, aSaturn; \"Saturn\"\nmov [rsp+98h+var_60], rax\nlea rax, aUranus; \"Uranus\"\nmov [rsp+98h+var_58], rax\nlea rax, aNeptune; \"Neptune\"\nmov [rsp+98h+var_50], rax\nmov ebx, 0\nmov r13d, 0FFFFFFFFh\nmov ebp, 0FFFFFFFFh\nloc_1267:\nmov r12, [rsp+rbx*8+98h+s1]\nmov rsi, r15; s2\nmov rdi, r12; s1\ncall _strcmp\ntest eax, eax\ncmovz ebp, ebx\nmov rsi, [rsp+98h+s2]; s2\nmov rdi, r12; s1\ncall _strcmp\ntest eax, eax\ncmovz r13d, ebx\nadd rbx, 1\ncmp rbx, 8\njnz short loc_1267\ncmp r13d, 0FFFFFFFFh\nsetz al\ncmp ebp, r13d\nsetz dl\nor al, dl\njnz loc_1330\ncmp ebp, 0FFFFFFFFh\njz short loc_1330\ncmp ebp, r13d\njg short loc_12BF\nmov eax, r13d\nmov r13d, ebp\nmov ebp, eax\nloc_12BF:\nmov eax, ebp\nsub eax, r13d\nsub eax, 1\nmov rcx, [rsp+98h+var_90]\nmov [rcx], eax\ntest eax, eax\njle short loc_1342\ncdqe\nlea rdi, ds:0[rax*8]; size\ncall _malloc\nlea edx, [r13+1]\ncmp ebp, edx\njle short loc_1311\nsub ebp, 2\nsub ebp, r13d\nmovsxd r13, r13d\nlea rsi, [rsp+r13*8+98h+s1]\nmov edx, 0\nloc_12FC:\nmov rcx, [rsi+rdx*8+8]\nmov [rax+rdx*8], rcx\nmov rcx, rdx\nadd rdx, 1\ncmp rcx, rbp\njnz short loc_12FC\nloc_1311:\nmov rdx, [rsp+98h+var_40]\nsub rdx, fs:28h\njnz short loc_134F\nadd rsp, 68h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1330:\nmov rax, [rsp+98h+var_90]\nmov dword ptr [rax], 0\nmov eax, 0\njmp short loc_1311\nloc_1342:\nmov dword ptr [rcx], 0\nmov eax, 0\njmp short loc_1311\nloc_134F:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11C9(char *s2, const char *a2, int *a3)\n{\n __int64 v3; // rbx\n int v4; // r13d\n int v5; // ebp\n const char *v6; // r12\n int v7; // eax\n int v8; // eax\n _QWORD *result; // rax\n int v10; // ebp\n __int64 v11; // rdx\n __int64 v12; // rcx\n char *s1[17]; // [rsp+10h] [rbp-88h] BYREF\n\n s1[9] = (char *)__readfsqword(0x28u);\n s1[0] = \"Mercury\";\n s1[1] = \"Venus\";\n s1[2] = \"Earth\";\n s1[3] = \"Mars\";\n s1[4] = \"Jupiter\";\n s1[5] = \"Saturn\";\n s1[6] = \"Uranus\";\n s1[7] = \"Neptune\";\n v3 = 0LL;\n v4 = -1;\n v5 = -1;\n do\n {\n v6 = s1[v3];\n if ( !strcmp(v6, s2) )\n v5 = v3;\n if ( !strcmp(v6, a2) )\n v4 = v3;\n ++v3;\n }\n while ( v3 != 8 );\n if ( v5 == v4 || v4 == -1 || v5 == -1 )\n {\n *a3 = 0;\n return 0LL;\n }\n else\n {\n if ( v5 <= v4 )\n {\n v7 = v4;\n v4 = v5;\n v5 = v7;\n }\n v8 = v5 - v4 - 1;\n *a3 = v8;\n if ( v8 <= 0 )\n {\n *a3 = 0;\n return 0LL;\n }\n else\n {\n result = malloc(8LL * v8);\n if ( v5 > v4 + 1 )\n {\n v10 = v5 - 2 - v4;\n v11 = 0LL;\n do\n {\n result[v11] = (&s1[v4])[v11 + 1];\n v12 = v11++;\n }\n while ( v12 != v10 );\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11C9(char *s2, const char *a2, int *a3) {\n long long v3;\n int v4;\n int v5;\n const char *v6;\n int v7;\n int v8;\n uint64_t *result;\n int v10;\n long long v11;\n long long v12;\n char *s1[17];\n s1[9] = (char *)__readfsqword(40u);\n s1[0] = \"Mercury\";\n s1[1] = \"Venus\";\n s1[2] = \"Earth\";\n s1[3] = \"Mars\";\n s1[4] = \"Jupiter\";\n s1[5] = \"Saturn\";\n s1[6] = \"Uranus\";\n s1[7] = \"Neptune\";\n v3 = 0LL;\n v4 = -1;\n v5 = -1;\n do {\n v6 = s1[v3];\n if (!strcmp(v6, s2)) v5 = v3;\n if (!strcmp(v6, a2)) v4 = v3;\n ++v3;\n } while (v3 != 8);\n if (v5 == v4 || v4 == -1 || v5 == -1) {\n *a3 = 0;\n return 0LL;\n } else {\n if (v5 <= v4) {\n v7 = v4;\n v4 = v5;\n v5 = v7;\n }\n v8 = v5 - v4 - 1;\n *a3 = v8;\n if (v8 <= 0) {\n *a3 = 0;\n return 0LL;\n } else {\n result = malloc(8LL * v8);\n if (v5 > v4 + 1) {\n v10 = v5 - 2 - v4;\n v11 = 0LL;\n do {\n result[v11] = (&s1[v4])[v11 + 1];\n v12 = v11++;\n } while (v12 != v10);\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "uint64_t *func0(char *s2, const char *a2, int *a3) {\n long long v3;\n int v4;\n int v5;\n const char *v6;\n int v7;\n int v8;\n uint64_t *result;\n int v10;\n long long v11;\n long long v12;\n char *s1[17];\n s1[9] = (char *)__readfsqword(40u);\n s1[0] = \"Mercury\";\n s1[1] = \"Venus\";\n s1[2] = \"Earth\";\n s1[3] = \"Mars\";\n s1[4] = \"Jupiter\";\n s1[5] = \"Saturn\";\n s1[6] = \"Uranus\";\n s1[7] = \"Neptune\";\n v3 = 0LL;\n v4 = -1;\n v5 = -1;\n do {\n v6 = s1[v3];\n if (!strcmp(v6, s2)) v5 = v3;\n if (!strcmp(v6, a2)) v4 = v3;\n ++v3;\n } while (v3 != 8);\n if (v5 == v4 || v4 == -1 || v5 == -1) {\n *a3 = 0;\n return 0LL;\n } else {\n if (v5 <= v4) {\n v7 = v4;\n v4 = v5;\n v5 = v7;\n }\n v8 = v5 - v4 - 1;\n *a3 = v8;\n if (v8 <= 0) {\n *a3 = 0;\n return 0LL;\n } else {\n result = malloc(8LL * v8);\n if (v5 > v4 + 1) {\n v10 = v5 - 2 - v4;\n v11 = 0LL;\n do {\n result[v11] = (&s1[v4])[v11 + 1];\n v12 = v11++;\n } while (v12 != v10);\n }\n }\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-148", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char** func0(const char* planet1, const char* planet2, int* returnSize) {\n const char* planets[] = {\"Mercury\", \"Venus\", \"Earth\", \"Mars\",\n \"Jupiter\", \"Saturn\", \"Uranus\", \"Neptune\"};\n int pos1 = -1, pos2 = -1, m;\n for (m = 0; m < 8; m++) {\n if (strcmp(planets[m], planet1) == 0) pos1 = m;\n if (strcmp(planets[m], planet2) == 0) pos2 = m;\n }\n if (pos1 == -1 || pos2 == -1 || pos1 == pos2) {\n *returnSize = 0;\n return NULL;\n }\n if (pos1 > pos2) {\n int temp = pos1;\n pos1 = pos2;\n pos2 = temp;\n }\n *returnSize = pos2 - pos1 - 1;\n if (*returnSize <= 0) {\n *returnSize = 0;\n return NULL;\n }\n char** out = malloc(*returnSize * sizeof(char*));\n for (m = pos1 + 1; m < pos2; m++) {\n out[m - pos1 - 1] = (char*)planets[m];\n }\n return out;\n}", + "test": "#include \n#include \n#include \n#include \n\nint issame(char** a, const char** b, int a_size, int b_size) {\n if (a_size != b_size) return 0;\n for (int i = 0; i < a_size; i++) {\n if (strcmp(a[i], b[i]) != 0) return 0;\n }\n return 1;\n}\n\nint main() {\n int size;\n char** result;\n\n const char* test1[] = {\"Saturn\", \"Uranus\"};\n result = func0(\"Jupiter\", \"Neptune\", &size);\n assert(issame(result, test1, size, 2));\n free(result);\n\n const char* test2[] = {\"Venus\"};\n result = func0(\"Earth\", \"Mercury\", &size);\n assert(issame(result, test2, size, 1));\n free(result);\n\n const char* test3[] = {\"Venus\", \"Earth\", \"Mars\", \"Jupiter\", \"Saturn\"};\n result = func0(\"Mercury\", \"Uranus\", &size);\n assert(issame(result, test3, size, 5));\n free(result);\n\n const char* test4[] = {\"Earth\", \"Mars\", \"Jupiter\", \"Saturn\", \"Uranus\"};\n result = func0(\"Neptune\", \"Venus\", &size);\n assert(issame(result, test4, size, 5));\n free(result);\n\n result = func0(\"Earth\", \"Earth\", &size);\n assert(size == 0 && result == NULL);\n\n result = func0(\"Mars\", \"Earth\", &size);\n assert(size == 0 && result == NULL);\n\n result = func0(\"Jupiter\", \"Makemake\", &size);\n assert(size == 0 && result == NULL);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\nlea rcx, aMercury; \"Mercury\"\nmov r15d, 0FFFFFFFFh\npush r14\nmovq xmm0, rcx\nlea rcx, aEarth; \"Earth\"\npush r13\npush r12\nxor r12d, r12d\npush rbp\npush rbx\nmov ebx, 0FFFFFFFFh\nsub rsp, 78h\nmov [rsp+0A8h+s2], rdi\nlea r14, [rsp+0A8h+var_88]\nmov [rsp+0A8h+var_98], rsi\nmov [rsp+0A8h+var_90], rdx\nmov rax, fs:28h\nmov [rsp+0A8h+var_40], rax\nlea rax, aVenus; \"Venus\"\nmovq xmm1, rax\nlea rax, aMars; \"Mars\"\npunpcklqdq xmm0, xmm1\nmovq xmm2, rax\nlea rax, aSaturn; \"Saturn\"\nmovaps [rsp+0A8h+var_88], xmm0\nmovq xmm0, rcx\nmovq xmm3, rax\nlea rcx, aJupiter; \"Jupiter\"\npunpcklqdq xmm0, xmm2\nlea rax, aNeptune; \"Neptune\"\nmovaps [rsp+0A8h+var_78], xmm0\nmovq xmm0, rcx\nmovq xmm4, rax\nlea rcx, aUranus; \"Uranus\"\npunpcklqdq xmm0, xmm3\nmovaps [rsp+0A8h+var_68], xmm0\nmovq xmm0, rcx\npunpcklqdq xmm0, xmm4\nmovaps [rsp+0A8h+var_58], xmm0\nnop word ptr [rax+rax+00000000h]\nloc_1670:\nmov r13, [r14+r12*8]\nmov rsi, [rsp+0A8h+s2]; s2\nmov rdi, r13; s1\ncall _strcmp\nmov rsi, [rsp+0A8h+var_98]; s2\nmov rdi, r13; s1\ntest eax, eax\ncmovz ebx, r12d\ncall _strcmp\ntest eax, eax\ncmovz r15d, r12d\nadd r12, 1\ncmp r12, 8\njnz short loc_1670\ncmp ebx, r15d\nsetz al\ncmp r15d, 0FFFFFFFFh\nsetz dl\nor al, dl\njnz loc_1748\ncmp ebx, 0FFFFFFFFh\njz loc_1748\ncmp ebx, r15d\njle short loc_1738\nloc_16C7:\nmov eax, ebx\nmov rdx, [rsp+0A8h+var_90]\nsub eax, r15d\nsub eax, 1\nmov [rdx], eax\ntest eax, eax\njle short loc_1748\ncdqe\nlea rdi, ds:0[rax*8]; size\ncall _malloc\nmov rdi, rax; dest\nlea eax, [r15+1]\ncmp ebx, eax\njle short loc_1710\nsub ebx, 2\ncdqe\nsub ebx, r15d\nlea rsi, [r14+rax*8]; src\nlea rdx, ds:8[rbx*8]; n\ncall _memcpy\nmov rdi, rax\nloc_1710:\nmov rax, [rsp+0A8h+var_40]\nsub rax, fs:28h\njnz short loc_1757\nadd rsp, 78h\nmov rax, rdi\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1738:\nmov eax, r15d\nmov r15d, ebx\nmov ebx, eax\njmp short loc_16C7\nloc_1748:\nmov rax, [rsp+0A8h+var_90]\nxor edi, edi\nmov dword ptr [rax], 0\njmp short loc_1710\nloc_1757:\ncall ___stack_chk_fail", + "ida_pseudo": "void *__fastcall func0(const char *a1, const char *a2, int *a3)\n{\n int v3; // r15d\n __int64 v4; // r12\n int v5; // ebx\n const char *v6; // rdi\n int v7; // eax\n void *v8; // rdi\n int v10; // eax\n _OWORD v13[4]; // [rsp+18h] [rbp-88h] BYREF\n unsigned __int64 v14; // [rsp+60h] [rbp-40h]\n\n v3 = -1;\n v4 = 0LL;\n v5 = -1;\n v14 = __readfsqword(0x28u);\n v13[0] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)\"Mercury\", (__m128i)(unsigned __int64)\"Venus\");\n v13[1] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)\"Earth\", (__m128i)(unsigned __int64)\"Mars\");\n v13[2] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)\"Jupiter\", (__m128i)(unsigned __int64)\"Saturn\");\n v13[3] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)\"Uranus\", (__m128i)(unsigned __int64)\"Neptune\");\n do\n {\n v6 = (const char *)*((_QWORD *)v13 + v4);\n if ( !strcmp(v6, a1) )\n v5 = v4;\n if ( !strcmp(v6, a2) )\n v3 = v4;\n ++v4;\n }\n while ( v4 != 8 );\n if ( v3 == -1 || v5 == v3 || v5 == -1 )\n goto LABEL_15;\n if ( v5 <= v3 )\n {\n v10 = v3;\n v3 = v5;\n v5 = v10;\n }\n v7 = v5 - v3 - 1;\n *a3 = v7;\n if ( v7 <= 0 )\n {\nLABEL_15:\n v8 = 0LL;\n *a3 = 0;\n }\n else\n {\n v8 = malloc(8LL * v7);\n if ( v5 > v3 + 1 )\n return memcpy(v8, (char *)v13 + 8 * v3 + 8, 8LL * (unsigned int)(v5 - 2 - v3) + 8);\n }\n return v8;\n}", + "ida_strip_asm": "sub_15A0:\nendbr64\npush r15\nlea rcx, aMercury; \"Mercury\"\nmov r15d, 0FFFFFFFFh\npush r14\nmovq xmm0, rcx\nlea rcx, aEarth; \"Earth\"\npush r13\npush r12\nxor r12d, r12d\npush rbp\npush rbx\nmov ebx, 0FFFFFFFFh\nsub rsp, 78h\nmov [rsp+0A8h+s2], rdi\nlea r14, [rsp+0A8h+var_88]\nmov [rsp+0A8h+var_98], rsi\nmov [rsp+0A8h+var_90], rdx\nmov rax, fs:28h\nmov [rsp+0A8h+var_40], rax\nlea rax, aVenus; \"Venus\"\nmovq xmm1, rax\nlea rax, aMars; \"Mars\"\npunpcklqdq xmm0, xmm1\nmovq xmm2, rax\nlea rax, aSaturn; \"Saturn\"\nmovaps [rsp+0A8h+var_88], xmm0\nmovq xmm0, rcx\nmovq xmm3, rax\nlea rcx, aJupiter; \"Jupiter\"\npunpcklqdq xmm0, xmm2\nlea rax, aNeptune; \"Neptune\"\nmovaps [rsp+0A8h+var_78], xmm0\nmovq xmm0, rcx\nmovq xmm4, rax\nlea rcx, aUranus; \"Uranus\"\npunpcklqdq xmm0, xmm3\nmovaps [rsp+0A8h+var_68], xmm0\nmovq xmm0, rcx\npunpcklqdq xmm0, xmm4\nmovaps [rsp+0A8h+var_58], xmm0\nnop word ptr [rax+rax+00000000h]\nloc_1670:\nmov r13, [r14+r12*8]\nmov rsi, [rsp+0A8h+s2]; s2\nmov rdi, r13; s1\ncall _strcmp\nmov rsi, [rsp+0A8h+var_98]; s2\nmov rdi, r13; s1\ntest eax, eax\ncmovz ebx, r12d\ncall _strcmp\ntest eax, eax\ncmovz r15d, r12d\nadd r12, 1\ncmp r12, 8\njnz short loc_1670\ncmp ebx, r15d\nsetz al\ncmp r15d, 0FFFFFFFFh\nsetz dl\nor al, dl\njnz loc_1748\ncmp ebx, 0FFFFFFFFh\njz loc_1748\ncmp ebx, r15d\njle short loc_1738\nloc_16C7:\nmov eax, ebx\nmov rdx, [rsp+0A8h+var_90]\nsub eax, r15d\nsub eax, 1\nmov [rdx], eax\ntest eax, eax\njle short loc_1748\ncdqe\nlea rdi, ds:0[rax*8]; size\ncall _malloc\nmov rdi, rax; dest\nlea eax, [r15+1]\ncmp ebx, eax\njle short loc_1710\nsub ebx, 2\ncdqe\nsub ebx, r15d\nlea rsi, [r14+rax*8]; src\nlea rdx, ds:8[rbx*8]; n\ncall _memcpy\nmov rdi, rax\nloc_1710:\nmov rax, [rsp+0A8h+var_40]\nsub rax, fs:28h\njnz short loc_1757\nadd rsp, 78h\nmov rax, rdi\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1738:\nmov eax, r15d\nmov r15d, ebx\nmov ebx, eax\njmp short loc_16C7\nloc_1748:\nmov rax, [rsp+0A8h+var_90]\nxor edi, edi\nmov dword ptr [rax], 0\njmp short loc_1710\nloc_1757:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "void *__fastcall sub_15A0(const char *a1, const char *a2, int *a3)\n{\n int v3; // r15d\n __int64 v4; // r12\n int v5; // ebx\n const char *v6; // rdi\n int v7; // eax\n void *v8; // rdi\n int v10; // eax\n _OWORD v13[4]; // [rsp+18h] [rbp-88h] BYREF\n unsigned __int64 v14; // [rsp+60h] [rbp-40h]\n\n v3 = -1;\n v4 = 0LL;\n v5 = -1;\n v14 = __readfsqword(0x28u);\n v13[0] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)\"Mercury\", (__m128i)(unsigned __int64)\"Venus\");\n v13[1] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)\"Earth\", (__m128i)(unsigned __int64)\"Mars\");\n v13[2] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)\"Jupiter\", (__m128i)(unsigned __int64)\"Saturn\");\n v13[3] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)\"Uranus\", (__m128i)(unsigned __int64)\"Neptune\");\n do\n {\n v6 = (const char *)*((_QWORD *)v13 + v4);\n if ( !strcmp(v6, a1) )\n v5 = v4;\n if ( !strcmp(v6, a2) )\n v3 = v4;\n ++v4;\n }\n while ( v4 != 8 );\n if ( v3 == -1 || v5 == v3 || v5 == -1 )\n goto LABEL_15;\n if ( v5 <= v3 )\n {\n v10 = v3;\n v3 = v5;\n v5 = v10;\n }\n v7 = v5 - v3 - 1;\n *a3 = v7;\n if ( v7 <= 0 )\n {\nLABEL_15:\n v8 = 0LL;\n *a3 = 0;\n }\n else\n {\n v8 = malloc(8LL * v7);\n if ( v5 > v3 + 1 )\n return memcpy(v8, (char *)v13 + 8 * v3 + 8, 8LL * (unsigned int)(v5 - 2 - v3) + 8);\n }\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_15A0(const char *a1, const char *a2, int *a3) {\n int v3;\n long long v4;\n int v5;\n const char *v6;\n int v7;\n void *v8;\n int v10;\n long double v13[4];\n unsigned long long v14;\n v3 = -1;\n v4 = 0LL;\n v5 = -1;\n v14 = __readfsqword(40u);\n v13[0] = _mm_unpacklo_epi64((__m128i)(unsigned long long)\"Mercury\",\n (__m128i)(unsigned long long)\"Venus\");\n v13[1] = _mm_unpacklo_epi64((__m128i)(unsigned long long)\"Earth\",\n (__m128i)(unsigned long long)\"Mars\");\n v13[2] = _mm_unpacklo_epi64((__m128i)(unsigned long long)\"Jupiter\",\n (__m128i)(unsigned long long)\"Saturn\");\n v13[3] = _mm_unpacklo_epi64((__m128i)(unsigned long long)\"Uranus\",\n (__m128i)(unsigned long long)\"Neptune\");\n do {\n v6 = (const char *)*((uint64_t *)v13 + v4);\n if (!strcmp(v6, a1)) v5 = v4;\n if (!strcmp(v6, a2)) v3 = v4;\n ++v4;\n } while (v4 != 8);\n if (v3 == -1 || v5 == v3 || v5 == -1) goto LABEL_15;\n if (v5 <= v3) {\n v10 = v3;\n v3 = v5;\n v5 = v10;\n }\n v7 = v5 - v3 - 1;\n *a3 = v7;\n if (v7 <= 0) {\n LABEL_15:\n v8 = 0LL;\n *a3 = 0;\n } else {\n v8 = malloc(8LL * v7);\n if (v5 > v3 + 1)\n return memcpy(v8, (char *)v13 + 8 * v3 + 8,\n 8LL * (unsigned int)(v5 - 2 - v3) + 8);\n }\n return v8;\n}", + "ida_pseudo_norm": "void *func0(const char *a1, const char *a2, int *a3) {\n int v3;\n long long v4;\n int v5;\n const char *v6;\n int v7;\n void *v8;\n int v10;\n long double v13[4];\n unsigned long long v14;\n v3 = -1;\n v4 = 0LL;\n v5 = -1;\n v14 = __readfsqword(40u);\n v13[0] = _mm_unpacklo_epi64((__m128i)(unsigned long long)\"Mercury\",\n (__m128i)(unsigned long long)\"Venus\");\n v13[1] = _mm_unpacklo_epi64((__m128i)(unsigned long long)\"Earth\",\n (__m128i)(unsigned long long)\"Mars\");\n v13[2] = _mm_unpacklo_epi64((__m128i)(unsigned long long)\"Jupiter\",\n (__m128i)(unsigned long long)\"Saturn\");\n v13[3] = _mm_unpacklo_epi64((__m128i)(unsigned long long)\"Uranus\",\n (__m128i)(unsigned long long)\"Neptune\");\n do {\n v6 = (const char *)*((uint64_t *)v13 + v4);\n if (!strcmp(v6, a1)) v5 = v4;\n if (!strcmp(v6, a2)) v3 = v4;\n ++v4;\n } while (v4 != 8);\n if (v3 == -1 || v5 == v3 || v5 == -1) goto LABEL_15;\n if (v5 <= v3) {\n v10 = v3;\n v3 = v5;\n v5 = v10;\n }\n v7 = v5 - v3 - 1;\n *a3 = v7;\n if (v7 <= 0) {\n LABEL_15:\n v8 = 0LL;\n *a3 = 0;\n } else {\n v8 = malloc(8LL * v7);\n if (v5 > v3 + 1)\n return memcpy(v8, (char *)v13 + 8 * v3 + 8,\n 8LL * (unsigned int)(v5 - 2 - v3) + 8);\n }\n return v8;\n}" + }, + { + "index": "HumanEval-C-148", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char** func0(const char* planet1, const char* planet2, int* returnSize) {\n const char* planets[] = {\"Mercury\", \"Venus\", \"Earth\", \"Mars\",\n \"Jupiter\", \"Saturn\", \"Uranus\", \"Neptune\"};\n int pos1 = -1, pos2 = -1, m;\n for (m = 0; m < 8; m++) {\n if (strcmp(planets[m], planet1) == 0) pos1 = m;\n if (strcmp(planets[m], planet2) == 0) pos2 = m;\n }\n if (pos1 == -1 || pos2 == -1 || pos1 == pos2) {\n *returnSize = 0;\n return NULL;\n }\n if (pos1 > pos2) {\n int temp = pos1;\n pos1 = pos2;\n pos2 = temp;\n }\n *returnSize = pos2 - pos1 - 1;\n if (*returnSize <= 0) {\n *returnSize = 0;\n return NULL;\n }\n char** out = malloc(*returnSize * sizeof(char*));\n for (m = pos1 + 1; m < pos2; m++) {\n out[m - pos1 - 1] = (char*)planets[m];\n }\n return out;\n}", + "test": "#include \n#include \n#include \n#include \n\nint issame(char** a, const char** b, int a_size, int b_size) {\n if (a_size != b_size) return 0;\n for (int i = 0; i < a_size; i++) {\n if (strcmp(a[i], b[i]) != 0) return 0;\n }\n return 1;\n}\n\nint main() {\n int size;\n char** result;\n\n const char* test1[] = {\"Saturn\", \"Uranus\"};\n result = func0(\"Jupiter\", \"Neptune\", &size);\n assert(issame(result, test1, size, 2));\n free(result);\n\n const char* test2[] = {\"Venus\"};\n result = func0(\"Earth\", \"Mercury\", &size);\n assert(issame(result, test2, size, 1));\n free(result);\n\n const char* test3[] = {\"Venus\", \"Earth\", \"Mars\", \"Jupiter\", \"Saturn\"};\n result = func0(\"Mercury\", \"Uranus\", &size);\n assert(issame(result, test3, size, 5));\n free(result);\n\n const char* test4[] = {\"Earth\", \"Mars\", \"Jupiter\", \"Saturn\", \"Uranus\"};\n result = func0(\"Neptune\", \"Venus\", &size);\n assert(issame(result, test4, size, 5));\n free(result);\n\n result = func0(\"Earth\", \"Earth\", &size);\n assert(size == 0 && result == NULL);\n\n result = func0(\"Mars\", \"Earth\", &size);\n assert(size == 0 && result == NULL);\n\n result = func0(\"Jupiter\", \"Makemake\", &size);\n assert(size == 0 && result == NULL);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\nlea r15, aEarth; \"Earth\"\npush r14\nlea r14, s2; \"Jupiter\"\npush r13\nlea r13, s1; \"Mercury\"\npush r12\nmovq xmm0, r13\nmov r12, rdi\npush rbp\nmov rbp, rsi\nmov rsi, rdi; s2\nmov rdi, r13; s1\npush rbx\nxor ebx, ebx\nsub rsp, 68h\nmov [rsp+98h+var_90], rdx\nmovhps xmm0, cs:off_3D70; \"Venus\"\nmov rax, fs:28h\nmov [rsp+98h+var_40], rax\nxor eax, eax\nmovaps [rsp+98h+src], xmm0\nmovq xmm0, r15\nmovhps xmm0, cs:off_3D78; \"Mars\"\nmovaps [rsp+98h+var_78], xmm0\nmovq xmm0, r14\nmovhps xmm0, cs:off_3D80; \"Saturn\"\nmovaps [rsp+98h+var_68], xmm0\nmovq xmm0, cs:off_3D88; \"Uranus\"\nmovhps xmm0, cs:off_3D90; \"Neptune\"\nmovaps [rsp+98h+var_58], xmm0\ncall _strcmp\nmov rdi, r13; s1\nmov rsi, rbp; s2\nmov r13d, 1\ntest eax, eax\nsetnz bl\ncall _strcmp\nmov rsi, r12; s2\nlea rdi, aVenus; \"Venus\"\ntest eax, eax\nsetnz al\nneg ebx\nmovzx eax, al\nmov [rsp+98h+var_94], eax\ncall _strcmp\nmov rsi, rbp; s2\nlea rdi, aVenus; \"Venus\"\ntest eax, eax\ncmovz ebx, r13d\ncall _strcmp\nmov edx, [rsp+98h+var_94]\nmov rdi, r15; s1\nmov rsi, r12; s2\nneg edx\ntest eax, eax\ncmovnz r13d, edx\ncall _strcmp\nmov r8d, 2\nmov rdi, r15; s1\nmov rsi, rbp; s2\ntest eax, eax\nmov r15d, 3\ncmovz ebx, r8d\ncall _strcmp\nmov r8d, 2\nmov rsi, r12; s2\ntest eax, eax\nlea rdi, aMars; \"Mars\"\ncmovz r13d, r8d\ncall _strcmp\nmov rsi, rbp; s2\nlea rdi, aMars; \"Mars\"\ntest eax, eax\ncmovz ebx, r15d\ncall _strcmp\nmov rdi, r14; s1\nmov rsi, r12; s2\ntest eax, eax\ncmovz r13d, r15d\nmov r15d, 4\ncall _strcmp\nmov rdi, r14; s1\nmov rsi, rbp; s2\nmov r14d, 5\ntest eax, eax\ncmovz ebx, r15d\ncall _strcmp\nmov rsi, r12; s2\nlea rdi, aSaturn; \"Saturn\"\ntest eax, eax\ncmovz r13d, r15d\ncall _strcmp\nmov rsi, rbp; s2\nlea rdi, aSaturn; \"Saturn\"\ntest eax, eax\ncmovz ebx, r14d\ncall _strcmp\nmov rsi, r12; s2\nlea rdi, aUranus; \"Uranus\"\ntest eax, eax\ncmovz r13d, r14d\nmov r14d, 6\ncall _strcmp\nmov rsi, rbp; s2\nlea rdi, aUranus; \"Uranus\"\ntest eax, eax\ncmovz ebx, r14d\ncall _strcmp\nmov rsi, r12; s2\nlea rdi, aNeptune; \"Neptune\"\ntest eax, eax\ncmovz r13d, r14d\ncall _strcmp\nmov rsi, rbp; s2\nlea rdi, aNeptune; \"Neptune\"\ntest eax, eax\nmov eax, 7\ncmovz ebx, eax\ncall _strcmp\nmov rcx, [rsp+98h+var_90]\ntest eax, eax\njz short loc_17E0\ncmp ebx, r13d\nsetz al\ncmp r13d, 0FFFFFFFFh\nsetz sil\nor al, sil\njnz short loc_17D4\ncmp ebx, 0FFFFFFFFh\njz short loc_17D4\ncmp ebx, r13d\njle short loc_17F0\nmov eax, ebx\nmov ebx, r13d\nmov r13d, eax\nmov eax, r13d\nsub eax, ebx\nsub eax, 1\nmov [rcx], eax\ntest eax, eax\njg short loc_17FE\nloc_17D4:\nmov dword ptr [rcx], 0\nxor ecx, ecx\njmp short loc_1838\nloc_17E0:\ncmp ebx, 0FFFFFFFFh\njz short loc_17D4\ncmp ebx, 7\njz short loc_17D4\nmov r13d, 7\nloc_17F0:\nmov eax, r13d\nsub eax, ebx\nsub eax, 1\nmov [rcx], eax\ntest eax, eax\njle short loc_17D4\nloc_17FE:\ncdqe\nlea rdi, ds:0[rax*8]; size\ncall _malloc\nmov rcx, rax\nlea eax, [rbx+1]\ncmp r13d, eax\njle short loc_1838\nlea edx, [r13-2]\ncdqe\nmov rdi, rcx; dest\nsub edx, ebx\nlea rsi, [rsp+rax*8+98h+src]; src\nlea rdx, ds:8[rdx*8]; n\ncall _memcpy\nmov rcx, rax\nloc_1838:\nmov rax, [rsp+98h+var_40]\nsub rax, fs:28h\njnz short loc_185A\nadd rsp, 68h\nmov rax, rcx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_185A:\ncall ___stack_chk_fail", + "ida_pseudo": "void *__fastcall func0(char *s2, char *a2, int *a3)\n{\n int v3; // r13d\n int v4; // ebx\n int v5; // eax\n int v6; // eax\n void *v7; // rcx\n int v9; // [rsp+0h] [rbp-94h]\n _OWORD src[4]; // [rsp+Ch] [rbp-88h] BYREF\n unsigned __int64 v12; // [rsp+54h] [rbp-40h]\n\n v12 = __readfsqword(0x28u);\n src[0] = _mm_loadh_ps((const double *)&off_3D70);\n src[1] = _mm_loadh_ps((const double *)&off_3D78);\n src[2] = _mm_loadh_ps((const double *)&off_3D80);\n src[3] = _mm_loadh_ps((const double *)&off_3D90);\n v3 = 1;\n v4 = -(strcmp(\"Mercury\", s2) != 0);\n v9 = strcmp(\"Mercury\", a2) != 0;\n if ( !strcmp(\"Venus\", s2) )\n v4 = 1;\n if ( strcmp(\"Venus\", a2) )\n v3 = -v9;\n if ( !strcmp(\"Earth\", s2) )\n v4 = 2;\n if ( !strcmp(\"Earth\", a2) )\n v3 = 2;\n if ( !strcmp(\"Mars\", s2) )\n v4 = 3;\n if ( !strcmp(\"Mars\", a2) )\n v3 = 3;\n if ( !strcmp(\"Jupiter\", s2) )\n v4 = 4;\n if ( !strcmp(\"Jupiter\", a2) )\n v3 = 4;\n if ( !strcmp(\"Saturn\", s2) )\n v4 = 5;\n if ( !strcmp(\"Saturn\", a2) )\n v3 = 5;\n if ( !strcmp(\"Uranus\", s2) )\n v4 = 6;\n if ( !strcmp(\"Uranus\", a2) )\n v3 = 6;\n if ( !strcmp(\"Neptune\", s2) )\n v4 = 7;\n if ( !strcmp(\"Neptune\", a2) )\n {\n if ( v4 == -1 || v4 == 7 )\n goto LABEL_32;\n v3 = 7;\n goto LABEL_36;\n }\n if ( v3 == -1 || v4 == v3 || v4 == -1 )\n goto LABEL_32;\n if ( v4 <= v3 )\n {\nLABEL_36:\n v6 = v3 - v4 - 1;\n *a3 = v6;\n if ( v6 <= 0 )\n goto LABEL_32;\n goto LABEL_37;\n }\n v5 = v4;\n v4 = v3;\n v3 = v5;\n v6 = v5 - v4 - 1;\n *a3 = v6;\n if ( v6 <= 0 )\n {\nLABEL_32:\n *a3 = 0;\n return 0LL;\n }\nLABEL_37:\n v7 = malloc(8LL * v6);\n if ( v3 > v4 + 1 )\n return memcpy(v7, (char *)src + 8 * v4 + 8, 8LL * (unsigned int)(v3 - 2 - v4) + 8);\n return v7;\n}", + "ida_strip_asm": "sub_15A0:\nendbr64\npush r15\nlea r15, aEarth; \"Earth\"\npush r14\nlea r14, s2; \"Jupiter\"\npush r13\nlea r13, s1; \"Mercury\"\npush r12\nmovq xmm0, r13\nmov r12, rdi\npush rbp\nmov rbp, rsi\nmov rsi, rdi; s2\nmov rdi, r13; s1\npush rbx\nxor ebx, ebx\nsub rsp, 68h\nmov [rsp+98h+var_90], rdx\nmovhps xmm0, cs:off_3D70; \"Venus\"\nmov rax, fs:28h\nmov [rsp+98h+var_40], rax\nxor eax, eax\nmovaps [rsp+98h+src], xmm0\nmovq xmm0, r15\nmovhps xmm0, cs:off_3D78; \"Mars\"\nmovaps [rsp+98h+var_78], xmm0\nmovq xmm0, r14\nmovhps xmm0, cs:off_3D80; \"Saturn\"\nmovaps [rsp+98h+var_68], xmm0\nmovq xmm0, cs:off_3D88; \"Uranus\"\nmovhps xmm0, cs:off_3D90; \"Neptune\"\nmovaps [rsp+98h+var_58], xmm0\ncall _strcmp\nmov rdi, r13; s1\nmov rsi, rbp; s2\nmov r13d, 1\ntest eax, eax\nsetnz bl\ncall _strcmp\nmov rsi, r12; s2\nlea rdi, aVenus; \"Venus\"\ntest eax, eax\nsetnz al\nneg ebx\nmovzx eax, al\nmov [rsp+98h+var_94], eax\ncall _strcmp\nmov rsi, rbp; s2\nlea rdi, aVenus; \"Venus\"\ntest eax, eax\ncmovz ebx, r13d\ncall _strcmp\nmov edx, [rsp+98h+var_94]\nmov rdi, r15; s1\nmov rsi, r12; s2\nneg edx\ntest eax, eax\ncmovnz r13d, edx\ncall _strcmp\nmov r8d, 2\nmov rdi, r15; s1\nmov rsi, rbp; s2\ntest eax, eax\nmov r15d, 3\ncmovz ebx, r8d\ncall _strcmp\nmov r8d, 2\nmov rsi, r12; s2\ntest eax, eax\nlea rdi, aMars; \"Mars\"\ncmovz r13d, r8d\ncall _strcmp\nmov rsi, rbp; s2\nlea rdi, aMars; \"Mars\"\ntest eax, eax\ncmovz ebx, r15d\ncall _strcmp\nmov rdi, r14; s1\nmov rsi, r12; s2\ntest eax, eax\ncmovz r13d, r15d\nmov r15d, 4\ncall _strcmp\nmov rdi, r14; s1\nmov rsi, rbp; s2\nmov r14d, 5\ntest eax, eax\ncmovz ebx, r15d\ncall _strcmp\nmov rsi, r12; s2\nlea rdi, aSaturn; \"Saturn\"\ntest eax, eax\ncmovz r13d, r15d\ncall _strcmp\nmov rsi, rbp; s2\nlea rdi, aSaturn; \"Saturn\"\ntest eax, eax\ncmovz ebx, r14d\ncall _strcmp\nmov rsi, r12; s2\nlea rdi, aUranus; \"Uranus\"\ntest eax, eax\ncmovz r13d, r14d\nmov r14d, 6\ncall _strcmp\nmov rsi, rbp; s2\nlea rdi, aUranus; \"Uranus\"\ntest eax, eax\ncmovz ebx, r14d\ncall _strcmp\nmov rsi, r12; s2\nlea rdi, aNeptune; \"Neptune\"\ntest eax, eax\ncmovz r13d, r14d\ncall _strcmp\nmov rsi, rbp; s2\nlea rdi, aNeptune; \"Neptune\"\ntest eax, eax\nmov eax, 7\ncmovz ebx, eax\ncall _strcmp\nmov rcx, [rsp+98h+var_90]\ntest eax, eax\njz short loc_17E0\ncmp ebx, r13d\nsetz al\ncmp r13d, 0FFFFFFFFh\nsetz sil\nor al, sil\njnz short loc_17D4\ncmp ebx, 0FFFFFFFFh\njz short loc_17D4\ncmp ebx, r13d\njle short loc_17F0\nmov eax, ebx\nmov ebx, r13d\nmov r13d, eax\nmov eax, r13d\nsub eax, ebx\nsub eax, 1\nmov [rcx], eax\ntest eax, eax\njg short loc_17FE\nloc_17D4:\nmov dword ptr [rcx], 0\nxor ecx, ecx\njmp short loc_1838\nloc_17E0:\ncmp ebx, 0FFFFFFFFh\njz short loc_17D4\ncmp ebx, 7\njz short loc_17D4\nmov r13d, 7\nloc_17F0:\nmov eax, r13d\nsub eax, ebx\nsub eax, 1\nmov [rcx], eax\ntest eax, eax\njle short loc_17D4\nloc_17FE:\ncdqe\nlea rdi, ds:0[rax*8]; size\ncall _malloc\nmov rcx, rax\nlea eax, [rbx+1]\ncmp r13d, eax\njle short loc_1838\nlea edx, [r13-2]\ncdqe\nmov rdi, rcx; dest\nsub edx, ebx\nlea rsi, [rsp+rax*8+98h+src]; src\nlea rdx, ds:8[rdx*8]; n\ncall _memcpy\nmov rcx, rax\nloc_1838:\nmov rax, [rsp+98h+var_40]\nsub rax, fs:28h\njnz short loc_185A\nadd rsp, 68h\nmov rax, rcx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_185A:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "void *__fastcall sub_15A0(char *s2, char *a2, int *a3)\n{\n int v3; // r13d\n int v4; // ebx\n int v5; // eax\n int v6; // eax\n void *v7; // rcx\n int v9; // [rsp+0h] [rbp-94h]\n _OWORD src[4]; // [rsp+Ch] [rbp-88h] BYREF\n unsigned __int64 v12; // [rsp+54h] [rbp-40h]\n\n v12 = __readfsqword(0x28u);\n src[0] = _mm_loadh_ps((const double *)&off_3D70);\n src[1] = _mm_loadh_ps((const double *)&off_3D78);\n src[2] = _mm_loadh_ps((const double *)&off_3D80);\n src[3] = _mm_loadh_ps((const double *)&off_3D90);\n v3 = 1;\n v4 = -(strcmp(\"Mercury\", s2) != 0);\n v9 = strcmp(\"Mercury\", a2) != 0;\n if ( !strcmp(\"Venus\", s2) )\n v4 = 1;\n if ( strcmp(\"Venus\", a2) )\n v3 = -v9;\n if ( !strcmp(\"Earth\", s2) )\n v4 = 2;\n if ( !strcmp(\"Earth\", a2) )\n v3 = 2;\n if ( !strcmp(\"Mars\", s2) )\n v4 = 3;\n if ( !strcmp(\"Mars\", a2) )\n v3 = 3;\n if ( !strcmp(\"Jupiter\", s2) )\n v4 = 4;\n if ( !strcmp(\"Jupiter\", a2) )\n v3 = 4;\n if ( !strcmp(\"Saturn\", s2) )\n v4 = 5;\n if ( !strcmp(\"Saturn\", a2) )\n v3 = 5;\n if ( !strcmp(\"Uranus\", s2) )\n v4 = 6;\n if ( !strcmp(\"Uranus\", a2) )\n v3 = 6;\n if ( !strcmp(\"Neptune\", s2) )\n v4 = 7;\n if ( !strcmp(\"Neptune\", a2) )\n {\n if ( v4 == -1 || v4 == 7 )\n goto LABEL_32;\n v3 = 7;\n goto LABEL_36;\n }\n if ( v3 == -1 || v4 == v3 || v4 == -1 )\n goto LABEL_32;\n if ( v4 <= v3 )\n {\nLABEL_36:\n v6 = v3 - v4 - 1;\n *a3 = v6;\n if ( v6 <= 0 )\n goto LABEL_32;\n goto LABEL_37;\n }\n v5 = v4;\n v4 = v3;\n v3 = v5;\n v6 = v5 - v4 - 1;\n *a3 = v6;\n if ( v6 <= 0 )\n {\nLABEL_32:\n *a3 = 0;\n return 0LL;\n }\nLABEL_37:\n v7 = malloc(8LL * v6);\n if ( v3 > v4 + 1 )\n return memcpy(v7, (char *)src + 8 * v4 + 8, 8LL * (unsigned int)(v3 - 2 - v4) + 8);\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_15A0(char *s2, char *a2, int *a3) {\n int v3;\n int v4;\n int v5;\n int v6;\n void *v7;\n int v9;\n long double src[4];\n unsigned long long v12;\n v12 = __readfsqword(40u);\n src[0] = _mm_loadh_ps((const double *)&off_3D70);\n src[1] = _mm_loadh_ps((const double *)&off_3D78);\n src[2] = _mm_loadh_ps((const double *)&off_3D80);\n src[3] = _mm_loadh_ps((const double *)&off_3D90);\n v3 = 1;\n v4 = -(strcmp(\"Mercury\", s2) != 0);\n v9 = strcmp(\"Mercury\", a2) != 0;\n if (!strcmp(\"Venus\", s2)) v4 = 1;\n if (strcmp(\"Venus\", a2)) v3 = -v9;\n if (!strcmp(\"Earth\", s2)) v4 = 2;\n if (!strcmp(\"Earth\", a2)) v3 = 2;\n if (!strcmp(\"Mars\", s2)) v4 = 3;\n if (!strcmp(\"Mars\", a2)) v3 = 3;\n if (!strcmp(\"Jupiter\", s2)) v4 = 4;\n if (!strcmp(\"Jupiter\", a2)) v3 = 4;\n if (!strcmp(\"Saturn\", s2)) v4 = 5;\n if (!strcmp(\"Saturn\", a2)) v3 = 5;\n if (!strcmp(\"Uranus\", s2)) v4 = 6;\n if (!strcmp(\"Uranus\", a2)) v3 = 6;\n if (!strcmp(\"Neptune\", s2)) v4 = 7;\n if (!strcmp(\"Neptune\", a2)) {\n if (v4 == -1 || v4 == 7) goto LABEL_32;\n v3 = 7;\n goto LABEL_36;\n }\n if (v3 == -1 || v4 == v3 || v4 == -1) goto LABEL_32;\n if (v4 <= v3) {\n LABEL_36:\n v6 = v3 - v4 - 1;\n *a3 = v6;\n if (v6 <= 0) goto LABEL_32;\n goto LABEL_37;\n }\n v5 = v4;\n v4 = v3;\n v3 = v5;\n v6 = v5 - v4 - 1;\n *a3 = v6;\n if (v6 <= 0) {\n LABEL_32:\n *a3 = 0;\n return 0LL;\n }\nLABEL_37:\n v7 = malloc(8LL * v6);\n if (v3 > v4 + 1)\n return memcpy(v7, (char *)src + 8 * v4 + 8,\n 8LL * (unsigned int)(v3 - 2 - v4) + 8);\n return v7;\n}", + "ida_pseudo_norm": "void *func0(char *s2, char *a2, int *a3) {\n int v3;\n int v4;\n int v5;\n int v6;\n void *v7;\n int v9;\n long double src[4];\n unsigned long long v12;\n v12 = __readfsqword(40u);\n src[0] = _mm_loadh_ps((const double *)&off_3D70);\n src[1] = _mm_loadh_ps((const double *)&off_3D78);\n src[2] = _mm_loadh_ps((const double *)&off_3D80);\n src[3] = _mm_loadh_ps((const double *)&off_3D90);\n v3 = 1;\n v4 = -(strcmp(\"Mercury\", s2) != 0);\n v9 = strcmp(\"Mercury\", a2) != 0;\n if (!strcmp(\"Venus\", s2)) v4 = 1;\n if (strcmp(\"Venus\", a2)) v3 = -v9;\n if (!strcmp(\"Earth\", s2)) v4 = 2;\n if (!strcmp(\"Earth\", a2)) v3 = 2;\n if (!strcmp(\"Mars\", s2)) v4 = 3;\n if (!strcmp(\"Mars\", a2)) v3 = 3;\n if (!strcmp(\"Jupiter\", s2)) v4 = 4;\n if (!strcmp(\"Jupiter\", a2)) v3 = 4;\n if (!strcmp(\"Saturn\", s2)) v4 = 5;\n if (!strcmp(\"Saturn\", a2)) v3 = 5;\n if (!strcmp(\"Uranus\", s2)) v4 = 6;\n if (!strcmp(\"Uranus\", a2)) v3 = 6;\n if (!strcmp(\"Neptune\", s2)) v4 = 7;\n if (!strcmp(\"Neptune\", a2)) {\n if (v4 == -1 || v4 == 7) goto LABEL_32;\n v3 = 7;\n goto LABEL_36;\n }\n if (v3 == -1 || v4 == v3 || v4 == -1) goto LABEL_32;\n if (v4 <= v3) {\n LABEL_36:\n v6 = v3 - v4 - 1;\n *a3 = v6;\n if (v6 <= 0) goto LABEL_32;\n goto LABEL_37;\n }\n v5 = v4;\n v4 = v3;\n v3 = v5;\n v6 = v5 - v4 - 1;\n *a3 = v6;\n if (v6 <= 0) {\n LABEL_32:\n *a3 = 0;\n return 0LL;\n }\nLABEL_37:\n v7 = malloc(8LL * v6);\n if (v3 > v4 + 1)\n return memcpy(v7, (char *)src + 8 * v4 + 8,\n 8LL * (unsigned int)(v3 - 2 - v4) + 8);\n return v7;\n}" + }, + { + "index": "HumanEval-C-149", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char **func0(char **lst, int lst_size, int *return_size) {\n int i, j;\n char *temp;\n *return_size = 0;\n for (i = 0; i < lst_size; ++i) {\n if (strlen(lst[i]) % 2 == 0) {\n lst[*return_size] = lst[i];\n (*return_size)++;\n }\n }\n for (i = 0; i < *return_size - 1; ++i) {\n for (j = 0; j < *return_size - i - 1; ++j) {\n size_t len_j = strlen(lst[j]);\n size_t len_j1 = strlen(lst[j + 1]);\n if (len_j > len_j1 ||\n (len_j == len_j1 && strcmp(lst[j], lst[j + 1]) > 0)) {\n temp = lst[j];\n lst[j] = lst[j + 1];\n lst[j + 1] = temp;\n }\n }\n }\n char **out = malloc(*return_size * sizeof(char *));\n for (i = 0; i < *return_size; ++i) {\n out[i] = lst[i];\n }\n return out;\n}", + "test": "#include \n#include \n#include \n#include \n\nint issame(char **a, char **b, int a_size, int b_size) {\n if (a_size != b_size) return 0;\n for (int i = 0; i < a_size; i++) {\n if (strcmp(a[i], b[i]) != 0) return 0;\n }\n return 1;\n}\n\nint main() {\n int size;\n char **result;\n\n char *test1[] = {\"aa\", \"a\", \"aaa\"};\n char *expected1[] = {\"aa\"};\n result = func0(test1, 3, &size);\n assert(issame(result, expected1, size, 1));\n free(result);\n\n char *test2[] = {\"school\", \"AI\", \"asdf\", \"b\"};\n char *expected2[] = {\"AI\", \"asdf\", \"school\"};\n result = func0(test2, 4, &size);\n assert(issame(result, expected2, size, 3));\n free(result);\n\n char *test3[] = {\"d\", \"b\", \"c\", \"a\"};\n result = func0(test3, 4, &size);\n assert(size == 0);\n free(result);\n\n char *test4[] = {\"d\", \"dcba\", \"abcd\", \"a\"};\n char *expected4[] = {\"abcd\", \"dcba\"};\n result = func0(test4, 4, &size);\n assert(issame(result, expected4, size, 2));\n free(result);\n\n char *test5[] = {\"AI\", \"ai\", \"au\"};\n char *expected5[] = {\"AI\", \"ai\", \"au\"};\n result = func0(test5, 3, &size);\n assert(issame(result, expected5, size, 3));\n free(result);\n\n char *test6[] = {\"a\", \"b\", \"b\", \"c\", \"c\", \"a\"};\n result = func0(test6, 6, &size);\n assert(size == 0);\n free(result);\n\n char *test7[] = {\"aaaa\", \"bbbb\", \"dd\", \"cc\"};\n char *expected7[] = {\"cc\", \"dd\", \"aaaa\", \"bbbb\"};\n result = func0(test7, 4, &size);\n assert(issame(result, expected7, size, 4));\n free(result);\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov [rbp+var_48], rdx\nmov rax, [rbp+var_48]\nmov dword ptr [rax], 0\nmov [rbp+var_28], 0\njmp short loc_129F\nloc_1233:\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; s\ncall _strlen\nand eax, 1\ntest rax, rax\njnz short loc_129B\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nlea rcx, [rdx+rax]\nmov rax, [rbp+var_48]\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rdx, rax\nmov rax, [rcx]\nmov [rdx], rax\nmov rax, [rbp+var_48]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_48]\nmov [rax], edx\nloc_129B:\nadd [rbp+var_28], 1\nloc_129F:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_3C]\njl short loc_1233\nmov [rbp+var_28], 0\njmp loc_13EC\nloc_12B3:\nmov [rbp+var_24], 0\njmp loc_13D3\nloc_12BF:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_18], rax\nmov eax, [rbp+var_24]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_10], rax\nmov rax, [rbp+var_18]\ncmp [rbp+var_10], rax\njb short loc_1362\nmov rax, [rbp+var_18]\ncmp rax, [rbp+var_10]\njnz loc_13CF\nmov eax, [rbp+var_24]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_24]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njle short loc_13CF\nloc_1362:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nmov [rbp+var_8], rax\nmov eax, [rbp+var_24]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_38]\nadd rdx, rcx\nmov rax, [rax]\nmov [rdx], rax\nmov eax, [rbp+var_24]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rdx, rax\nmov rax, [rbp+var_8]\nmov [rdx], rax\nloc_13CF:\nadd [rbp+var_24], 1\nloc_13D3:\nmov rax, [rbp+var_48]\nmov eax, [rax]\nsub eax, [rbp+var_28]\nsub eax, 1\ncmp [rbp+var_24], eax\njl loc_12BF\nadd [rbp+var_28], 1\nloc_13EC:\nmov rax, [rbp+var_48]\nmov eax, [rax]\nsub eax, 1\ncmp [rbp+var_28], eax\njl loc_12B3\nmov rax, [rbp+var_48]\nmov eax, [rax]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_20], rax\nmov [rbp+var_28], 0\njmp short loc_1452\nloc_141F:\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_20]\nadd rdx, rcx\nmov rax, [rax]\nmov [rdx], rax\nadd [rbp+var_28], 1\nloc_1452:\nmov rax, [rbp+var_48]\nmov eax, [rax]\ncmp [rbp+var_28], eax\njl short loc_141F\nmov rax, [rbp+var_20]\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, int a2, int *a3)\n{\n int i; // [rsp+28h] [rbp-28h]\n int j; // [rsp+28h] [rbp-28h]\n int m; // [rsp+28h] [rbp-28h]\n int k; // [rsp+2Ch] [rbp-24h]\n _QWORD *v9; // [rsp+30h] [rbp-20h]\n size_t v10; // [rsp+38h] [rbp-18h]\n size_t v11; // [rsp+40h] [rbp-10h]\n __int64 v12; // [rsp+48h] [rbp-8h]\n\n *a3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( (strlen(*(const char **)(8LL * i + a1)) & 1) == 0 )\n *(_QWORD *)(a1 + 8LL * (*a3)++) = *(_QWORD *)(8LL * i + a1);\n }\n for ( j = 0; j < *a3 - 1; ++j )\n {\n for ( k = 0; k < *a3 - j - 1; ++k )\n {\n v10 = strlen(*(const char **)(8LL * k + a1));\n v11 = strlen(*(const char **)(8 * (k + 1LL) + a1));\n if ( v11 < v10 || v10 == v11 && strcmp(*(const char **)(8LL * k + a1), *(const char **)(8 * (k + 1LL) + a1)) > 0 )\n {\n v12 = *(_QWORD *)(8LL * k + a1);\n *(_QWORD *)(8LL * k + a1) = *(_QWORD *)(8 * (k + 1LL) + a1);\n *(_QWORD *)(a1 + 8 * (k + 1LL)) = v12;\n }\n }\n }\n v9 = malloc(8LL * *a3);\n for ( m = 0; m < *a3; ++m )\n v9[m] = *(_QWORD *)(8LL * m + a1);\n return v9;\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov [rbp+var_48], rdx\nmov rax, [rbp+var_48]\nmov dword ptr [rax], 0\nmov [rbp+var_28], 0\njmp short loc_129F\nloc_1233:\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; s\ncall _strlen\nand eax, 1\ntest rax, rax\njnz short loc_129B\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nlea rcx, [rdx+rax]\nmov rax, [rbp+var_48]\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rdx, rax\nmov rax, [rcx]\nmov [rdx], rax\nmov rax, [rbp+var_48]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_48]\nmov [rax], edx\nloc_129B:\nadd [rbp+var_28], 1\nloc_129F:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_3C]\njl short loc_1233\nmov [rbp+var_28], 0\njmp loc_13EC\nloc_12B3:\nmov [rbp+var_24], 0\njmp loc_13D3\nloc_12BF:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_18], rax\nmov eax, [rbp+var_24]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_10], rax\nmov rax, [rbp+var_18]\ncmp [rbp+var_10], rax\njb short loc_1362\nmov rax, [rbp+var_18]\ncmp rax, [rbp+var_10]\njnz loc_13CF\nmov eax, [rbp+var_24]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_24]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njle short loc_13CF\nloc_1362:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nmov [rbp+var_8], rax\nmov eax, [rbp+var_24]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_38]\nadd rdx, rcx\nmov rax, [rax]\nmov [rdx], rax\nmov eax, [rbp+var_24]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rdx, rax\nmov rax, [rbp+var_8]\nmov [rdx], rax\nloc_13CF:\nadd [rbp+var_24], 1\nloc_13D3:\nmov rax, [rbp+var_48]\nmov eax, [rax]\nsub eax, [rbp+var_28]\nsub eax, 1\ncmp [rbp+var_24], eax\njl loc_12BF\nadd [rbp+var_28], 1\nloc_13EC:\nmov rax, [rbp+var_48]\nmov eax, [rax]\nsub eax, 1\ncmp [rbp+var_28], eax\njl loc_12B3\nmov rax, [rbp+var_48]\nmov eax, [rax]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_20], rax\nmov [rbp+var_28], 0\njmp short loc_1452\nloc_141F:\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_20]\nadd rdx, rcx\nmov rax, [rax]\nmov [rdx], rax\nadd [rbp+var_28], 1\nloc_1452:\nmov rax, [rbp+var_48]\nmov eax, [rax]\ncmp [rbp+var_28], eax\njl short loc_141F\nmov rax, [rbp+var_20]\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1209(__int64 a1, int a2, int *a3)\n{\n int i; // [rsp+28h] [rbp-28h]\n int j; // [rsp+28h] [rbp-28h]\n int m; // [rsp+28h] [rbp-28h]\n int k; // [rsp+2Ch] [rbp-24h]\n _QWORD *v9; // [rsp+30h] [rbp-20h]\n size_t v10; // [rsp+38h] [rbp-18h]\n size_t v11; // [rsp+40h] [rbp-10h]\n __int64 v12; // [rsp+48h] [rbp-8h]\n\n *a3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( (strlen(*(const char **)(8LL * i + a1)) & 1) == 0 )\n *(_QWORD *)(a1 + 8LL * (*a3)++) = *(_QWORD *)(8LL * i + a1);\n }\n for ( j = 0; j < *a3 - 1; ++j )\n {\n for ( k = 0; k < *a3 - j - 1; ++k )\n {\n v10 = strlen(*(const char **)(8LL * k + a1));\n v11 = strlen(*(const char **)(8 * (k + 1LL) + a1));\n if ( v11 < v10 || v10 == v11 && strcmp(*(const char **)(8LL * k + a1), *(const char **)(8 * (k + 1LL) + a1)) > 0 )\n {\n v12 = *(_QWORD *)(8LL * k + a1);\n *(_QWORD *)(8LL * k + a1) = *(_QWORD *)(8 * (k + 1LL) + a1);\n *(_QWORD *)(a1 + 8 * (k + 1LL)) = v12;\n }\n }\n }\n v9 = malloc(8LL * *a3);\n for ( m = 0; m < *a3; ++m )\n v9[m] = *(_QWORD *)(8LL * m + a1);\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1209(long long a1, int a2, int *a3) {\n int i;\n int j;\n int m;\n int k;\n uint64_t *v9;\n unsigned int v10;\n unsigned int v11;\n long long v12;\n *a3 = 0;\n for (i = 0; i < a2; ++i) {\n if ((strlen(*(const char **)(8LL * i + a1)) & 1) == 0)\n *(uint64_t *)(a1 + 8LL * (*a3)++) = *(uint64_t *)(8LL * i + a1);\n }\n for (j = 0; j < *a3 - 1; ++j) {\n for (k = 0; k < *a3 - j - 1; ++k) {\n v10 = strlen(*(const char **)(8LL * k + a1));\n v11 = strlen(*(const char **)(8 * (k + 1LL) + a1));\n if (v11 < v10 ||\n v10 == v11 && strcmp(*(const char **)(8LL * k + a1),\n *(const char **)(8 * (k + 1LL) + a1)) > 0) {\n v12 = *(uint64_t *)(8LL * k + a1);\n *(uint64_t *)(8LL * k + a1) = *(uint64_t *)(8 * (k + 1LL) + a1);\n *(uint64_t *)(a1 + 8 * (k + 1LL)) = v12;\n }\n }\n }\n v9 = malloc(8LL * *a3);\n for (m = 0; m < *a3; ++m) v9[m] = *(uint64_t *)(8LL * m + a1);\n return v9;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, int a2, int *a3) {\n int i;\n int j;\n int m;\n int k;\n uint64_t *v9;\n unsigned int v10;\n unsigned int v11;\n long long v12;\n *a3 = 0;\n for (i = 0; i < a2; ++i) {\n if ((strlen(*(const char **)(8LL * i + a1)) & 1) == 0)\n *(uint64_t *)(a1 + 8LL * (*a3)++) = *(uint64_t *)(8LL * i + a1);\n }\n for (j = 0; j < *a3 - 1; ++j) {\n for (k = 0; k < *a3 - j - 1; ++k) {\n v10 = strlen(*(const char **)(8LL * k + a1));\n v11 = strlen(*(const char **)(8 * (k + 1LL) + a1));\n if (v11 < v10 ||\n v10 == v11 && strcmp(*(const char **)(8LL * k + a1),\n *(const char **)(8 * (k + 1LL) + a1)) > 0) {\n v12 = *(uint64_t *)(8LL * k + a1);\n *(uint64_t *)(8LL * k + a1) = *(uint64_t *)(8 * (k + 1LL) + a1);\n *(uint64_t *)(a1 + 8 * (k + 1LL)) = v12;\n }\n }\n }\n v9 = malloc(8LL * *a3);\n for (m = 0; m < *a3; ++m) v9[m] = *(uint64_t *)(8LL * m + a1);\n return v9;\n}" + }, + { + "index": "HumanEval-C-149", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char **func0(char **lst, int lst_size, int *return_size) {\n int i, j;\n char *temp;\n *return_size = 0;\n for (i = 0; i < lst_size; ++i) {\n if (strlen(lst[i]) % 2 == 0) {\n lst[*return_size] = lst[i];\n (*return_size)++;\n }\n }\n for (i = 0; i < *return_size - 1; ++i) {\n for (j = 0; j < *return_size - i - 1; ++j) {\n size_t len_j = strlen(lst[j]);\n size_t len_j1 = strlen(lst[j + 1]);\n if (len_j > len_j1 ||\n (len_j == len_j1 && strcmp(lst[j], lst[j + 1]) > 0)) {\n temp = lst[j];\n lst[j] = lst[j + 1];\n lst[j + 1] = temp;\n }\n }\n }\n char **out = malloc(*return_size * sizeof(char *));\n for (i = 0; i < *return_size; ++i) {\n out[i] = lst[i];\n }\n return out;\n}", + "test": "#include \n#include \n#include \n#include \n\nint issame(char **a, char **b, int a_size, int b_size) {\n if (a_size != b_size) return 0;\n for (int i = 0; i < a_size; i++) {\n if (strcmp(a[i], b[i]) != 0) return 0;\n }\n return 1;\n}\n\nint main() {\n int size;\n char **result;\n\n char *test1[] = {\"aa\", \"a\", \"aaa\"};\n char *expected1[] = {\"aa\"};\n result = func0(test1, 3, &size);\n assert(issame(result, expected1, size, 1));\n free(result);\n\n char *test2[] = {\"school\", \"AI\", \"asdf\", \"b\"};\n char *expected2[] = {\"AI\", \"asdf\", \"school\"};\n result = func0(test2, 4, &size);\n assert(issame(result, expected2, size, 3));\n free(result);\n\n char *test3[] = {\"d\", \"b\", \"c\", \"a\"};\n result = func0(test3, 4, &size);\n assert(size == 0);\n free(result);\n\n char *test4[] = {\"d\", \"dcba\", \"abcd\", \"a\"};\n char *expected4[] = {\"abcd\", \"dcba\"};\n result = func0(test4, 4, &size);\n assert(issame(result, expected4, size, 2));\n free(result);\n\n char *test5[] = {\"AI\", \"ai\", \"au\"};\n char *expected5[] = {\"AI\", \"ai\", \"au\"};\n result = func0(test5, 3, &size);\n assert(issame(result, expected5, size, 3));\n free(result);\n\n char *test6[] = {\"a\", \"b\", \"b\", \"c\", \"c\", \"a\"};\n result = func0(test6, 6, &size);\n assert(size == 0);\n free(result);\n\n char *test7[] = {\"aaaa\", \"bbbb\", \"dd\", \"cc\"};\n char *expected7[] = {\"cc\", \"dd\", \"aaaa\", \"bbbb\"};\n result = func0(test7, 4, &size);\n assert(issame(result, expected7, size, 4));\n free(result);\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov r12, rdi\nmov r15, rdx\nmov dword ptr [rdx], 0\ntest esi, esi\njle loc_12EF\nmov rbx, rdi\nmovsxd rsi, esi\nlea r13, [rdi+rsi*8]\njmp short loc_1244\nloc_123B:\nadd rbx, 8\ncmp rbx, r13\njz short loc_1260\nloc_1244:\nmov rbp, [rbx]\nmov rdi, rbp; s\ncall _strlen\ntest al, 1\njnz short loc_123B\nmovsxd rax, dword ptr [r15]\nmov [r12+rax*8], rbp\nadd dword ptr [r15], 1\njmp short loc_123B\nloc_1260:\nmov eax, [r15]\ncmp eax, 1\njle loc_12F4\nmov [rsp+48h+var_3C], 0\njmp short loc_12DA\nloc_1276:\nmov [r12+rbx*8], r14\nmov [r12+rbx*8+8], r13\nloc_127F:\nadd rbx, 1\nmov eax, [rsp+48h+var_3C]\nnot eax\nadd eax, [r15]\ncmp eax, ebx\njle short loc_12C7\nloc_1290:\nmov r13, [r12+rbx*8]\nmov rdi, r13; s\ncall _strlen\nmov rbp, rax\nmov r14, [r12+rbx*8+8]\nmov rdi, r14; s\ncall _strlen\ncmp rax, rbp\njb short loc_1276\ncmp rbp, rax\njnz short loc_127F\nmov rsi, r14; s2\nmov rdi, r13; s1\ncall _strcmp\ntest eax, eax\njg short loc_1276\njmp short loc_127F\nloc_12C7:\nadd [rsp+48h+var_3C], 1\nmov ecx, [rsp+48h+var_3C]\nmov eax, [r15]\nlea edx, [rax-1]\ncmp edx, ecx\njle short loc_12F4\nloc_12DA:\nmov eax, [r15]\nmov esi, [rsp+48h+var_3C]\nsub eax, esi\nmov ebx, 0\ncmp eax, 1\njg short loc_1290\njmp short loc_12C7\nloc_12EF:\nmov eax, 0\nloc_12F4:\ncdqe\nlea rdi, ds:0[rax*8]; size\ncall _malloc\nmov edx, [r15]\ntest edx, edx\njle short loc_132B\nmovsxd rdx, edx\nlea rsi, ds:0[rdx*8]\nmov edx, 0\nloc_131A:\nmov rcx, [r12+rdx]\nmov [rax+rdx], rcx\nadd rdx, 8\ncmp rdx, rsi\njnz short loc_131A\nloc_132B:\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "char *__fastcall func0(const char **a1, int a2, int *a3)\n{\n const char **v4; // rbx\n const char *v5; // rbp\n int v6; // eax\n __int64 v7; // rbx\n const char *v8; // r13\n size_t v9; // rbp\n const char *v10; // r14\n size_t v11; // rax\n char *result; // rax\n __int64 v13; // rsi\n unsigned __int64 v14; // rdx\n int v15; // [rsp+Ch] [rbp-3Ch]\n\n *a3 = 0;\n if ( a2 <= 0 )\n {\n v6 = 0;\n }\n else\n {\n v4 = a1;\n do\n {\n v5 = *v4;\n if ( (strlen(*v4) & 1) == 0 )\n a1[(*a3)++] = v5;\n ++v4;\n }\n while ( v4 != &a1[a2] );\n v6 = *a3;\n if ( *a3 > 1 )\n {\n v15 = 0;\n do\n {\n v7 = 0LL;\n if ( *a3 - v15 > 1 )\n {\n do\n {\n v8 = a1[v7];\n v9 = strlen(v8);\n v10 = a1[v7 + 1];\n v11 = strlen(v10);\n if ( v11 < v9 || v9 == v11 && strcmp(v8, v10) > 0 )\n {\n a1[v7] = v10;\n a1[v7 + 1] = v8;\n }\n ++v7;\n }\n while ( *a3 + ~v15 > (int)v7 );\n }\n ++v15;\n v6 = *a3;\n }\n while ( *a3 - 1 > v15 );\n }\n }\n result = (char *)malloc(8LL * v6);\n if ( *a3 > 0 )\n {\n v13 = 8LL * *a3;\n v14 = 0LL;\n do\n {\n *(_QWORD *)&result[v14] = a1[v14 / 8];\n v14 += 8LL;\n }\n while ( v14 != v13 );\n }\n return result;\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov r12, rdi\nmov r15, rdx\nmov dword ptr [rdx], 0\ntest esi, esi\njle loc_12EF\nmov rbx, rdi\nmovsxd rsi, esi\nlea r13, [rdi+rsi*8]\njmp short loc_1244\nloc_123B:\nadd rbx, 8\ncmp rbx, r13\njz short loc_1260\nloc_1244:\nmov rbp, [rbx]\nmov rdi, rbp; s\ncall _strlen\ntest al, 1\njnz short loc_123B\nmovsxd rax, dword ptr [r15]\nmov [r12+rax*8], rbp\nadd dword ptr [r15], 1\njmp short loc_123B\nloc_1260:\nmov eax, [r15]\ncmp eax, 1\njle loc_12F4\nmov [rsp+48h+var_3C], 0\njmp short loc_12DA\nloc_1276:\nmov [r12+rbx*8], r14\nmov [r12+rbx*8+8], r13\nloc_127F:\nadd rbx, 1\nmov eax, [rsp+48h+var_3C]\nnot eax\nadd eax, [r15]\ncmp eax, ebx\njle short loc_12C7\nloc_1290:\nmov r13, [r12+rbx*8]\nmov rdi, r13; s\ncall _strlen\nmov rbp, rax\nmov r14, [r12+rbx*8+8]\nmov rdi, r14; s\ncall _strlen\ncmp rax, rbp\njb short loc_1276\ncmp rbp, rax\njnz short loc_127F\nmov rsi, r14; s2\nmov rdi, r13; s1\ncall _strcmp\ntest eax, eax\njg short loc_1276\njmp short loc_127F\nloc_12C7:\nadd [rsp+48h+var_3C], 1\nmov ecx, [rsp+48h+var_3C]\nmov eax, [r15]\nlea edx, [rax-1]\ncmp edx, ecx\njle short loc_12F4\nloc_12DA:\nmov eax, [r15]\nmov esi, [rsp+48h+var_3C]\nsub eax, esi\nmov ebx, 0\ncmp eax, 1\njg short loc_1290\njmp short loc_12C7\nloc_12EF:\nmov eax, 0\nloc_12F4:\ncdqe\nlea rdi, ds:0[rax*8]; size\ncall _malloc\nmov edx, [r15]\ntest edx, edx\njle short loc_132B\nmovsxd rdx, edx\nlea rsi, ds:0[rdx*8]\nmov edx, 0\nloc_131A:\nmov rcx, [r12+rdx]\nmov [rax+rdx], rcx\nadd rdx, 8\ncmp rdx, rsi\njnz short loc_131A\nloc_132B:\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1209(const char **a1, int a2, int *a3)\n{\n const char **v4; // rbx\n const char *v5; // rbp\n int v6; // eax\n __int64 v7; // rbx\n const char *v8; // r13\n size_t v9; // rbp\n const char *v10; // r14\n size_t v11; // rax\n char *result; // rax\n __int64 v13; // rsi\n unsigned __int64 v14; // rdx\n int v15; // [rsp+Ch] [rbp-3Ch]\n\n *a3 = 0;\n if ( a2 <= 0 )\n {\n v6 = 0;\n }\n else\n {\n v4 = a1;\n do\n {\n v5 = *v4;\n if ( (strlen(*v4) & 1) == 0 )\n a1[(*a3)++] = v5;\n ++v4;\n }\n while ( v4 != &a1[a2] );\n v6 = *a3;\n if ( *a3 > 1 )\n {\n v15 = 0;\n do\n {\n v7 = 0LL;\n if ( *a3 - v15 > 1 )\n {\n do\n {\n v8 = a1[v7];\n v9 = strlen(v8);\n v10 = a1[v7 + 1];\n v11 = strlen(v10);\n if ( v11 < v9 || v9 == v11 && strcmp(v8, v10) > 0 )\n {\n a1[v7] = v10;\n a1[v7 + 1] = v8;\n }\n ++v7;\n }\n while ( *a3 + ~v15 > (int)v7 );\n }\n ++v15;\n v6 = *a3;\n }\n while ( *a3 - 1 > v15 );\n }\n }\n result = (char *)malloc(8LL * v6);\n if ( *a3 > 0 )\n {\n v13 = 8LL * *a3;\n v14 = 0LL;\n do\n {\n *(_QWORD *)&result[v14] = a1[v14 / 8];\n v14 += 8LL;\n }\n while ( v14 != v13 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1209(const char **a1, int a2, int *a3) {\n const char **v4;\n const char *v5;\n int v6;\n long long v7;\n const char *v8;\n unsigned int v9;\n const char *v10;\n unsigned int v11;\n char *result;\n long long v13;\n unsigned long long v14;\n int v15;\n *a3 = 0;\n if (a2 <= 0) {\n v6 = 0;\n } else {\n v4 = a1;\n do {\n v5 = *v4;\n if ((strlen(*v4) & 1) == 0) a1[(*a3)++] = v5;\n ++v4;\n } while (v4 != &a1[a2]);\n v6 = *a3;\n if (*a3 > 1) {\n v15 = 0;\n do {\n v7 = 0LL;\n if (*a3 - v15 > 1) {\n do {\n v8 = a1[v7];\n v9 = strlen(v8);\n v10 = a1[v7 + 1];\n v11 = strlen(v10);\n if (v11 < v9 || v9 == v11 && strcmp(v8, v10) > 0) {\n a1[v7] = v10;\n a1[v7 + 1] = v8;\n }\n ++v7;\n } while (*a3 + ~v15 > (int)v7);\n }\n ++v15;\n v6 = *a3;\n } while (*a3 - 1 > v15);\n }\n }\n result = (char *)malloc(8LL * v6);\n if (*a3 > 0) {\n v13 = 8LL * *a3;\n v14 = 0LL;\n do {\n *(uint64_t *)&result[v14] = a1[v14 / 8];\n v14 += 8LL;\n } while (v14 != v13);\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(const char **a1, int a2, int *a3) {\n const char **v4;\n const char *v5;\n int v6;\n long long v7;\n const char *v8;\n unsigned int v9;\n const char *v10;\n unsigned int v11;\n char *result;\n long long v13;\n unsigned long long v14;\n int v15;\n *a3 = 0;\n if (a2 <= 0) {\n v6 = 0;\n } else {\n v4 = a1;\n do {\n v5 = *v4;\n if ((strlen(*v4) & 1) == 0) a1[(*a3)++] = v5;\n ++v4;\n } while (v4 != &a1[a2]);\n v6 = *a3;\n if (*a3 > 1) {\n v15 = 0;\n do {\n v7 = 0LL;\n if (*a3 - v15 > 1) {\n do {\n v8 = a1[v7];\n v9 = strlen(v8);\n v10 = a1[v7 + 1];\n v11 = strlen(v10);\n if (v11 < v9 || v9 == v11 && strcmp(v8, v10) > 0) {\n a1[v7] = v10;\n a1[v7 + 1] = v8;\n }\n ++v7;\n } while (*a3 + ~v15 > (int)v7);\n }\n ++v15;\n v6 = *a3;\n } while (*a3 - 1 > v15);\n }\n }\n result = (char *)malloc(8LL * v6);\n if (*a3 > 0) {\n v13 = 8LL * *a3;\n v14 = 0LL;\n do {\n *(uint64_t *)&result[v14] = a1[v14 / 8];\n v14 += 8LL;\n } while (v14 != v13);\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-149", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char **func0(char **lst, int lst_size, int *return_size) {\n int i, j;\n char *temp;\n *return_size = 0;\n for (i = 0; i < lst_size; ++i) {\n if (strlen(lst[i]) % 2 == 0) {\n lst[*return_size] = lst[i];\n (*return_size)++;\n }\n }\n for (i = 0; i < *return_size - 1; ++i) {\n for (j = 0; j < *return_size - i - 1; ++j) {\n size_t len_j = strlen(lst[j]);\n size_t len_j1 = strlen(lst[j + 1]);\n if (len_j > len_j1 ||\n (len_j == len_j1 && strcmp(lst[j], lst[j + 1]) > 0)) {\n temp = lst[j];\n lst[j] = lst[j + 1];\n lst[j + 1] = temp;\n }\n }\n }\n char **out = malloc(*return_size * sizeof(char *));\n for (i = 0; i < *return_size; ++i) {\n out[i] = lst[i];\n }\n return out;\n}", + "test": "#include \n#include \n#include \n#include \n\nint issame(char **a, char **b, int a_size, int b_size) {\n if (a_size != b_size) return 0;\n for (int i = 0; i < a_size; i++) {\n if (strcmp(a[i], b[i]) != 0) return 0;\n }\n return 1;\n}\n\nint main() {\n int size;\n char **result;\n\n char *test1[] = {\"aa\", \"a\", \"aaa\"};\n char *expected1[] = {\"aa\"};\n result = func0(test1, 3, &size);\n assert(issame(result, expected1, size, 1));\n free(result);\n\n char *test2[] = {\"school\", \"AI\", \"asdf\", \"b\"};\n char *expected2[] = {\"AI\", \"asdf\", \"school\"};\n result = func0(test2, 4, &size);\n assert(issame(result, expected2, size, 3));\n free(result);\n\n char *test3[] = {\"d\", \"b\", \"c\", \"a\"};\n result = func0(test3, 4, &size);\n assert(size == 0);\n free(result);\n\n char *test4[] = {\"d\", \"dcba\", \"abcd\", \"a\"};\n char *expected4[] = {\"abcd\", \"dcba\"};\n result = func0(test4, 4, &size);\n assert(issame(result, expected4, size, 2));\n free(result);\n\n char *test5[] = {\"AI\", \"ai\", \"au\"};\n char *expected5[] = {\"AI\", \"ai\", \"au\"};\n result = func0(test5, 3, &size);\n assert(issame(result, expected5, size, 3));\n free(result);\n\n char *test6[] = {\"a\", \"b\", \"b\", \"c\", \"c\", \"a\"};\n result = func0(test6, 6, &size);\n assert(size == 0);\n free(result);\n\n char *test7[] = {\"aaaa\", \"bbbb\", \"dd\", \"cc\"};\n char *expected7[] = {\"cc\", \"dd\", \"aaaa\", \"bbbb\"};\n result = func0(test7, 4, &size);\n assert(issame(result, expected7, size, 4));\n free(result);\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov dword ptr [rdx], 0\nmov [rsp+58h+src], rdi\nmov [rsp+58h+var_48], rdx\ntest esi, esi\njle loc_1901\nmovsxd rsi, esi\nmov rbx, rdi\nxor r13d, r13d\nlea r12, [rdi+rsi*8]\nnop word ptr [rax+rax+00000000h]\nloc_17D0:\nmov rbp, [rbx]\nmov rdi, rbp; s\ncall _strlen\ntest al, 1\njnz short loc_17F6\nmov rdx, [rsp+58h+src]\nmovsxd rax, r13d\nadd r13d, 1\nmov [rdx+rax*8], rbp\nmov rax, [rsp+58h+var_48]\nmov [rax], r13d\nloc_17F6:\nadd rbx, 8\ncmp r12, rbx\njnz short loc_17D0\nmovsxd rax, r13d\nshl rax, 3\nmov [rsp+58h+size], rax\ncmp r13d, 1\njle loc_189F\nmov rax, [rsp+58h+src]\nadd rax, 8\nmov [rsp+58h+var_50], rax\nnop word ptr [rax+rax+00h]\nloc_1828:\ncmp r13d, 1\njle loc_18F8\nmov rcx, [rsp+58h+var_50]\nlea eax, [r13-2]\nmov r15, [rsp+58h+src]\nlea r12, [rcx+rax*8]\njmp short loc_185A\nloc_1848:\ncmp r14, rax\njz loc_18E0\nloc_1851:\nadd r15, 8\ncmp r15, r12\njz short loc_1895\nloc_185A:\nmov rbp, [r15]\nmov rdi, rbp; s\ncall _strlen\nmov rbx, [r15+8]\nmov r14, rax\nmov rdi, rbx; s\ncall _strlen\ncmp rax, r14\njnb short loc_1848\nloc_1879:\nmovq xmm0, rbx\nmovq xmm1, rbp\nadd r15, 8\npunpcklqdq xmm0, xmm1\nmovups xmmword ptr [r15-8], xmm0\ncmp r15, r12\njnz short loc_185A\nloc_1895:\nsub r13d, 1\ncmp r13d, 1\njnz short loc_1828\nloc_189F:\nmov rdi, [rsp+58h+size]; size\ncall _malloc\nmov rcx, rax\nmov rax, [rsp+58h+var_48]\nmov eax, [rax]\ntest eax, eax\njle short loc_18CE\nmov rsi, [rsp+58h+src]; src\nmov rdi, rcx; dest\nlea rdx, ds:0[rax*8]; n\ncall _memcpy\nmov rcx, rax\nloc_18CE:\nadd rsp, 28h\nmov rax, rcx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_18E0:\nmov rsi, rbx; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njg short loc_1879\njmp loc_1851\nloc_18F8:\nsub r13d, 1\njmp loc_1828\nloc_1901:\nmov [rsp+58h+size], 0\njmp short loc_189F", + "ida_pseudo": "void *__fastcall func0(const char **a1, int a2, int *a3)\n{\n const char **v3; // rbx\n int v4; // r13d\n const char *v5; // rbp\n __int64 v6; // rax\n const char **v7; // r15\n __int64 v8; // r12\n const char *v9; // rbp\n size_t v10; // rax\n const char *v11; // rbx\n size_t v12; // r14\n size_t v13; // rax\n void *v14; // rax\n void *v15; // rcx\n __int64 v16; // rax\n __int64 size; // [rsp+18h] [rbp-40h]\n\n *a3 = 0;\n if ( a2 <= 0 )\n {\n v14 = malloc(0LL);\n }\n else\n {\n v3 = a1;\n v4 = 0;\n do\n {\n v5 = *v3;\n if ( (strlen(*v3) & 1) == 0 )\n {\n v6 = v4++;\n a1[v6] = v5;\n *a3 = v4;\n }\n ++v3;\n }\n while ( &a1[a2] != v3 );\n size = 8LL * v4;\n if ( v4 > 1 )\n {\n do\n {\n while ( v4 <= 1 )\n --v4;\n v7 = a1;\n v8 = (__int64)&a1[(unsigned int)(v4 - 2) + 1];\n do\n {\n while ( 1 )\n {\n v9 = *v7;\n v10 = strlen(*v7);\n v11 = v7[1];\n v12 = v10;\n v13 = strlen(v11);\n if ( v13 < v12 || v12 == v13 && strcmp(v9, v11) > 0 )\n break;\n if ( ++v7 == (const char **)v8 )\n goto LABEL_13;\n }\n *(__m128i *)v7++ = _mm_unpacklo_epi64((__m128i)(unsigned __int64)v11, (__m128i)(unsigned __int64)v9);\n }\n while ( v7 != (const char **)v8 );\nLABEL_13:\n --v4;\n }\n while ( v4 != 1 );\n }\n v14 = malloc(size);\n }\n v15 = v14;\n v16 = (unsigned int)*a3;\n if ( (int)v16 > 0 )\n return memcpy(v15, a1, 8 * v16);\n return v15;\n}", + "ida_strip_asm": "sub_1790:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov dword ptr [rdx], 0\nmov [rsp+58h+src], rdi\nmov [rsp+58h+var_48], rdx\ntest esi, esi\njle loc_1901\nmovsxd rsi, esi\nmov rbx, rdi\nxor r13d, r13d\nlea r12, [rdi+rsi*8]\nnop word ptr [rax+rax+00000000h]\nloc_17D0:\nmov rbp, [rbx]\nmov rdi, rbp; s\ncall _strlen\ntest al, 1\njnz short loc_17F6\nmov rdx, [rsp+58h+src]\nmovsxd rax, r13d\nadd r13d, 1\nmov [rdx+rax*8], rbp\nmov rax, [rsp+58h+var_48]\nmov [rax], r13d\nloc_17F6:\nadd rbx, 8\ncmp r12, rbx\njnz short loc_17D0\nmovsxd rax, r13d\nshl rax, 3\nmov [rsp+58h+size], rax\ncmp r13d, 1\njle loc_189F\nmov rax, [rsp+58h+src]\nadd rax, 8\nmov [rsp+58h+var_50], rax\nnop word ptr [rax+rax+00h]\nloc_1828:\ncmp r13d, 1\njle loc_18F8\nmov rcx, [rsp+58h+var_50]\nlea eax, [r13-2]\nmov r15, [rsp+58h+src]\nlea r12, [rcx+rax*8]\njmp short loc_185A\nloc_1848:\ncmp r14, rax\njz loc_18E0\nloc_1851:\nadd r15, 8\ncmp r15, r12\njz short loc_1895\nloc_185A:\nmov rbp, [r15]\nmov rdi, rbp; s\ncall _strlen\nmov rbx, [r15+8]\nmov r14, rax\nmov rdi, rbx; s\ncall _strlen\ncmp rax, r14\njnb short loc_1848\nloc_1879:\nmovq xmm0, rbx\nmovq xmm1, rbp\nadd r15, 8\npunpcklqdq xmm0, xmm1\nmovups xmmword ptr [r15-8], xmm0\ncmp r15, r12\njnz short loc_185A\nloc_1895:\nsub r13d, 1\ncmp r13d, 1\njnz short loc_1828\nloc_189F:\nmov rdi, [rsp+58h+size]; size\ncall _malloc\nmov rcx, rax\nmov rax, [rsp+58h+var_48]\nmov eax, [rax]\ntest eax, eax\njle short loc_18CE\nmov rsi, [rsp+58h+src]; src\nmov rdi, rcx; dest\nlea rdx, ds:0[rax*8]; n\ncall _memcpy\nmov rcx, rax\nloc_18CE:\nadd rsp, 28h\nmov rax, rcx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_18E0:\nmov rsi, rbx; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njg short loc_1879\njmp loc_1851\nloc_18F8:\nsub r13d, 1\njmp loc_1828\nloc_1901:\nmov [rsp+58h+size], 0\njmp short loc_189F", + "ida_strip_pseudo": "void *__fastcall sub_1790(const char **a1, int a2, int *a3)\n{\n const char **v3; // rbx\n int v4; // r13d\n const char *v5; // rbp\n __int64 v6; // rax\n const char **v7; // r15\n __int64 v8; // r12\n const char *v9; // rbp\n size_t v10; // rax\n const char *v11; // rbx\n size_t v12; // r14\n size_t v13; // rax\n void *v14; // rax\n void *v15; // rcx\n __int64 v16; // rax\n __int64 size; // [rsp+18h] [rbp-40h]\n\n *a3 = 0;\n if ( a2 <= 0 )\n {\n v14 = malloc(0LL);\n }\n else\n {\n v3 = a1;\n v4 = 0;\n do\n {\n v5 = *v3;\n if ( (strlen(*v3) & 1) == 0 )\n {\n v6 = v4++;\n a1[v6] = v5;\n *a3 = v4;\n }\n ++v3;\n }\n while ( &a1[a2] != v3 );\n size = 8LL * v4;\n if ( v4 > 1 )\n {\n do\n {\n while ( v4 <= 1 )\n --v4;\n v7 = a1;\n v8 = (__int64)&a1[(unsigned int)(v4 - 2) + 1];\n do\n {\n while ( 1 )\n {\n v9 = *v7;\n v10 = strlen(*v7);\n v11 = v7[1];\n v12 = v10;\n v13 = strlen(v11);\n if ( v13 < v12 || v12 == v13 && strcmp(v9, v11) > 0 )\n break;\n if ( ++v7 == (const char **)v8 )\n goto LABEL_13;\n }\n *(__m128i *)v7++ = _mm_unpacklo_epi64((__m128i)(unsigned __int64)v11, (__m128i)(unsigned __int64)v9);\n }\n while ( v7 != (const char **)v8 );\nLABEL_13:\n --v4;\n }\n while ( v4 != 1 );\n }\n v14 = malloc(size);\n }\n v15 = v14;\n v16 = (unsigned int)*a3;\n if ( (int)v16 > 0 )\n return memcpy(v15, a1, 8 * v16);\n return v15;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1790(const char **a1, int a2, int *a3) {\n const char **v3;\n int v4;\n const char *v5;\n long long v6;\n const char **v7;\n long long v8;\n const char *v9;\n unsigned int v10;\n const char *v11;\n unsigned int v12;\n unsigned int v13;\n void *v14;\n void *v15;\n long long v16;\n long long size;\n *a3 = 0;\n if (a2 <= 0) {\n v14 = malloc(0LL);\n } else {\n v3 = a1;\n v4 = 0;\n do {\n v5 = *v3;\n if ((strlen(*v3) & 1) == 0) {\n v6 = v4++;\n a1[v6] = v5;\n *a3 = v4;\n }\n ++v3;\n } while (&a1[a2] != v3);\n size = 8LL * v4;\n if (v4 > 1) {\n do {\n while (v4 <= 1) --v4;\n v7 = a1;\n v8 = (long long)&a1[(unsigned int)(v4 - 2) + 1];\n do {\n while (1) {\n v9 = *v7;\n v10 = strlen(*v7);\n v11 = v7[1];\n v12 = v10;\n v13 = strlen(v11);\n if (v13 < v12 || v12 == v13 && strcmp(v9, v11) > 0) break;\n if (++v7 == (const char **)v8) goto LABEL_13;\n }\n *(__m128i *)v7++ =\n _mm_unpacklo_epi64((__m128i)(unsigned long long)v11,\n (__m128i)(unsigned long long)v9);\n } while (v7 != (const char **)v8);\n LABEL_13:\n --v4;\n } while (v4 != 1);\n }\n v14 = malloc(size);\n }\n v15 = v14;\n v16 = (unsigned int)*a3;\n if ((int)v16 > 0) return memcpy(v15, a1, 8 * v16);\n return v15;\n}", + "ida_pseudo_norm": "void *func0(const char **a1, int a2, int *a3) {\n const char **v3;\n int v4;\n const char *v5;\n long long v6;\n const char **v7;\n long long v8;\n const char *v9;\n unsigned int v10;\n const char *v11;\n unsigned int v12;\n unsigned int v13;\n void *v14;\n void *v15;\n long long v16;\n long long size;\n *a3 = 0;\n if (a2 <= 0) {\n v14 = malloc(0LL);\n } else {\n v3 = a1;\n v4 = 0;\n do {\n v5 = *v3;\n if ((strlen(*v3) & 1) == 0) {\n v6 = v4++;\n a1[v6] = v5;\n *a3 = v4;\n }\n ++v3;\n } while (&a1[a2] != v3);\n size = 8LL * v4;\n if (v4 > 1) {\n do {\n while (v4 <= 1) --v4;\n v7 = a1;\n v8 = (long long)&a1[(unsigned int)(v4 - 2) + 1];\n do {\n while (1) {\n v9 = *v7;\n v10 = strlen(*v7);\n v11 = v7[1];\n v12 = v10;\n v13 = strlen(v11);\n if (v13 < v12 || v12 == v13 && strcmp(v9, v11) > 0) break;\n if (++v7 == (const char **)v8) goto LABEL_13;\n }\n *(__m128i *)v7++ =\n _mm_unpacklo_epi64((__m128i)(unsigned long long)v11,\n (__m128i)(unsigned long long)v9);\n } while (v7 != (const char **)v8);\n LABEL_13:\n --v4;\n } while (v4 != 1);\n }\n v14 = malloc(size);\n }\n v15 = v14;\n v16 = (unsigned int)*a3;\n if ((int)v16 > 0) return memcpy(v15, a1, 8 * v16);\n return v15;\n}" + }, + { + "index": "HumanEval-C-149", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char **func0(char **lst, int lst_size, int *return_size) {\n int i, j;\n char *temp;\n *return_size = 0;\n for (i = 0; i < lst_size; ++i) {\n if (strlen(lst[i]) % 2 == 0) {\n lst[*return_size] = lst[i];\n (*return_size)++;\n }\n }\n for (i = 0; i < *return_size - 1; ++i) {\n for (j = 0; j < *return_size - i - 1; ++j) {\n size_t len_j = strlen(lst[j]);\n size_t len_j1 = strlen(lst[j + 1]);\n if (len_j > len_j1 ||\n (len_j == len_j1 && strcmp(lst[j], lst[j + 1]) > 0)) {\n temp = lst[j];\n lst[j] = lst[j + 1];\n lst[j + 1] = temp;\n }\n }\n }\n char **out = malloc(*return_size * sizeof(char *));\n for (i = 0; i < *return_size; ++i) {\n out[i] = lst[i];\n }\n return out;\n}", + "test": "#include \n#include \n#include \n#include \n\nint issame(char **a, char **b, int a_size, int b_size) {\n if (a_size != b_size) return 0;\n for (int i = 0; i < a_size; i++) {\n if (strcmp(a[i], b[i]) != 0) return 0;\n }\n return 1;\n}\n\nint main() {\n int size;\n char **result;\n\n char *test1[] = {\"aa\", \"a\", \"aaa\"};\n char *expected1[] = {\"aa\"};\n result = func0(test1, 3, &size);\n assert(issame(result, expected1, size, 1));\n free(result);\n\n char *test2[] = {\"school\", \"AI\", \"asdf\", \"b\"};\n char *expected2[] = {\"AI\", \"asdf\", \"school\"};\n result = func0(test2, 4, &size);\n assert(issame(result, expected2, size, 3));\n free(result);\n\n char *test3[] = {\"d\", \"b\", \"c\", \"a\"};\n result = func0(test3, 4, &size);\n assert(size == 0);\n free(result);\n\n char *test4[] = {\"d\", \"dcba\", \"abcd\", \"a\"};\n char *expected4[] = {\"abcd\", \"dcba\"};\n result = func0(test4, 4, &size);\n assert(issame(result, expected4, size, 2));\n free(result);\n\n char *test5[] = {\"AI\", \"ai\", \"au\"};\n char *expected5[] = {\"AI\", \"ai\", \"au\"};\n result = func0(test5, 3, &size);\n assert(issame(result, expected5, size, 3));\n free(result);\n\n char *test6[] = {\"a\", \"b\", \"b\", \"c\", \"c\", \"a\"};\n result = func0(test6, 6, &size);\n assert(size == 0);\n free(result);\n\n char *test7[] = {\"aaaa\", \"bbbb\", \"dd\", \"cc\"};\n char *expected7[] = {\"cc\", \"dd\", \"aaaa\", \"bbbb\"};\n result = func0(test7, 4, &size);\n assert(issame(result, expected7, size, 4));\n free(result);\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov dword ptr [rdx], 0\nmov [rsp+58h+src], rdi\nmov [rsp+58h+var_48], rdx\ntest esi, esi\njle loc_1901\nmovsxd rsi, esi\nmov rbx, rdi\nxor r13d, r13d\nlea r12, [rdi+rsi*8]\nnop word ptr [rax+rax+00000000h]\nloc_17D0:\nmov rbp, [rbx]\nmov rdi, rbp; s\ncall _strlen\ntest al, 1\njnz short loc_17F6\nmov rdx, [rsp+58h+src]\nmovsxd rax, r13d\nadd r13d, 1\nmov [rdx+rax*8], rbp\nmov rax, [rsp+58h+var_48]\nmov [rax], r13d\nloc_17F6:\nadd rbx, 8\ncmp r12, rbx\njnz short loc_17D0\nmovsxd rax, r13d\nshl rax, 3\nmov [rsp+58h+size], rax\ncmp r13d, 1\njle loc_189F\nmov rax, [rsp+58h+src]\nadd rax, 8\nmov [rsp+58h+var_50], rax\nnop word ptr [rax+rax+00h]\nloc_1828:\ncmp r13d, 1\njle loc_18F8\nmov rcx, [rsp+58h+var_50]\nlea eax, [r13-2]\nmov r15, [rsp+58h+src]\nlea r12, [rcx+rax*8]\njmp short loc_185A\nloc_1848:\ncmp r14, rax\njz loc_18E0\nloc_1851:\nadd r15, 8\ncmp r15, r12\njz short loc_1895\nloc_185A:\nmov rbp, [r15]\nmov rdi, rbp; s\ncall _strlen\nmov rbx, [r15+8]\nmov r14, rax\nmov rdi, rbx; s\ncall _strlen\ncmp rax, r14\njnb short loc_1848\nloc_1879:\nmovq xmm0, rbx\nmovq xmm1, rbp\nadd r15, 8\npunpcklqdq xmm0, xmm1\nmovups xmmword ptr [r15-8], xmm0\ncmp r15, r12\njnz short loc_185A\nloc_1895:\nsub r13d, 1\ncmp r13d, 1\njnz short loc_1828\nloc_189F:\nmov rdi, [rsp+58h+size]; size\ncall _malloc\nmov rcx, rax\nmov rax, [rsp+58h+var_48]\nmov eax, [rax]\ntest eax, eax\njle short loc_18CE\nmov rsi, [rsp+58h+src]; src\nmov rdi, rcx; dest\nlea rdx, ds:0[rax*8]; n\ncall _memcpy\nmov rcx, rax\nloc_18CE:\nadd rsp, 28h\nmov rax, rcx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_18E0:\nmov rsi, rbx; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njg short loc_1879\njmp loc_1851\nloc_18F8:\nsub r13d, 1\njmp loc_1828\nloc_1901:\nmov [rsp+58h+size], 0\njmp short loc_189F", + "ida_pseudo": "void *__fastcall func0(const char **a1, int a2, int *a3)\n{\n const char **v3; // rbx\n int v4; // r13d\n const char *v5; // rbp\n __int64 v6; // rax\n const char **v7; // r15\n __int64 v8; // r12\n const char *v9; // rbp\n size_t v10; // rax\n const char *v11; // rbx\n size_t v12; // r14\n size_t v13; // rax\n void *v14; // rax\n void *v15; // rcx\n __int64 v16; // rax\n __int64 size; // [rsp+18h] [rbp-40h]\n\n *a3 = 0;\n if ( a2 <= 0 )\n {\n v14 = malloc(0LL);\n }\n else\n {\n v3 = a1;\n v4 = 0;\n do\n {\n v5 = *v3;\n if ( (strlen(*v3) & 1) == 0 )\n {\n v6 = v4++;\n a1[v6] = v5;\n *a3 = v4;\n }\n ++v3;\n }\n while ( &a1[a2] != v3 );\n size = 8LL * v4;\n if ( v4 > 1 )\n {\n do\n {\n while ( v4 <= 1 )\n --v4;\n v7 = a1;\n v8 = (__int64)&a1[(unsigned int)(v4 - 2) + 1];\n do\n {\n while ( 1 )\n {\n v9 = *v7;\n v10 = strlen(*v7);\n v11 = v7[1];\n v12 = v10;\n v13 = strlen(v11);\n if ( v13 < v12 || v12 == v13 && strcmp(v9, v11) > 0 )\n break;\n if ( ++v7 == (const char **)v8 )\n goto LABEL_13;\n }\n *(__m128i *)v7++ = _mm_unpacklo_epi64((__m128i)(unsigned __int64)v11, (__m128i)(unsigned __int64)v9);\n }\n while ( v7 != (const char **)v8 );\nLABEL_13:\n --v4;\n }\n while ( v4 != 1 );\n }\n v14 = malloc(size);\n }\n v15 = v14;\n v16 = (unsigned int)*a3;\n if ( (int)v16 > 0 )\n return memcpy(v15, a1, 8 * v16);\n return v15;\n}", + "ida_strip_asm": "sub_1790:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov dword ptr [rdx], 0\nmov [rsp+58h+src], rdi\nmov [rsp+58h+var_48], rdx\ntest esi, esi\njle loc_1901\nmovsxd rsi, esi\nmov rbx, rdi\nxor r13d, r13d\nlea r12, [rdi+rsi*8]\nnop word ptr [rax+rax+00000000h]\nloc_17D0:\nmov rbp, [rbx]\nmov rdi, rbp; s\ncall _strlen\ntest al, 1\njnz short loc_17F6\nmov rdx, [rsp+58h+src]\nmovsxd rax, r13d\nadd r13d, 1\nmov [rdx+rax*8], rbp\nmov rax, [rsp+58h+var_48]\nmov [rax], r13d\nloc_17F6:\nadd rbx, 8\ncmp r12, rbx\njnz short loc_17D0\nmovsxd rax, r13d\nshl rax, 3\nmov [rsp+58h+size], rax\ncmp r13d, 1\njle loc_189F\nmov rax, [rsp+58h+src]\nadd rax, 8\nmov [rsp+58h+var_50], rax\nnop word ptr [rax+rax+00h]\nloc_1828:\ncmp r13d, 1\njle loc_18F8\nmov rcx, [rsp+58h+var_50]\nlea eax, [r13-2]\nmov r15, [rsp+58h+src]\nlea r12, [rcx+rax*8]\njmp short loc_185A\nloc_1848:\ncmp r14, rax\njz loc_18E0\nloc_1851:\nadd r15, 8\ncmp r15, r12\njz short loc_1895\nloc_185A:\nmov rbp, [r15]\nmov rdi, rbp; s\ncall _strlen\nmov rbx, [r15+8]\nmov r14, rax\nmov rdi, rbx; s\ncall _strlen\ncmp rax, r14\njnb short loc_1848\nloc_1879:\nmovq xmm0, rbx\nmovq xmm1, rbp\nadd r15, 8\npunpcklqdq xmm0, xmm1\nmovups xmmword ptr [r15-8], xmm0\ncmp r15, r12\njnz short loc_185A\nloc_1895:\nsub r13d, 1\ncmp r13d, 1\njnz short loc_1828\nloc_189F:\nmov rdi, [rsp+58h+size]; size\ncall _malloc\nmov rcx, rax\nmov rax, [rsp+58h+var_48]\nmov eax, [rax]\ntest eax, eax\njle short loc_18CE\nmov rsi, [rsp+58h+src]; src\nmov rdi, rcx; dest\nlea rdx, ds:0[rax*8]; n\ncall _memcpy\nmov rcx, rax\nloc_18CE:\nadd rsp, 28h\nmov rax, rcx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_18E0:\nmov rsi, rbx; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njg short loc_1879\njmp loc_1851\nloc_18F8:\nsub r13d, 1\njmp loc_1828\nloc_1901:\nmov [rsp+58h+size], 0\njmp short loc_189F", + "ida_strip_pseudo": "void *__fastcall sub_1790(const char **a1, int a2, int *a3)\n{\n const char **v3; // rbx\n int v4; // r13d\n const char *v5; // rbp\n __int64 v6; // rax\n const char **v7; // r15\n __int64 v8; // r12\n const char *v9; // rbp\n size_t v10; // rax\n const char *v11; // rbx\n size_t v12; // r14\n size_t v13; // rax\n void *v14; // rax\n void *v15; // rcx\n __int64 v16; // rax\n __int64 size; // [rsp+18h] [rbp-40h]\n\n *a3 = 0;\n if ( a2 <= 0 )\n {\n v14 = malloc(0LL);\n }\n else\n {\n v3 = a1;\n v4 = 0;\n do\n {\n v5 = *v3;\n if ( (strlen(*v3) & 1) == 0 )\n {\n v6 = v4++;\n a1[v6] = v5;\n *a3 = v4;\n }\n ++v3;\n }\n while ( &a1[a2] != v3 );\n size = 8LL * v4;\n if ( v4 > 1 )\n {\n do\n {\n while ( v4 <= 1 )\n --v4;\n v7 = a1;\n v8 = (__int64)&a1[(unsigned int)(v4 - 2) + 1];\n do\n {\n while ( 1 )\n {\n v9 = *v7;\n v10 = strlen(*v7);\n v11 = v7[1];\n v12 = v10;\n v13 = strlen(v11);\n if ( v13 < v12 || v12 == v13 && strcmp(v9, v11) > 0 )\n break;\n if ( ++v7 == (const char **)v8 )\n goto LABEL_13;\n }\n *(__m128i *)v7++ = _mm_unpacklo_epi64((__m128i)(unsigned __int64)v11, (__m128i)(unsigned __int64)v9);\n }\n while ( v7 != (const char **)v8 );\nLABEL_13:\n --v4;\n }\n while ( v4 != 1 );\n }\n v14 = malloc(size);\n }\n v15 = v14;\n v16 = (unsigned int)*a3;\n if ( (int)v16 > 0 )\n return memcpy(v15, a1, 8 * v16);\n return v15;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1790(const char **a1, int a2, int *a3) {\n const char **v3;\n int v4;\n const char *v5;\n long long v6;\n const char **v7;\n long long v8;\n const char *v9;\n unsigned int v10;\n const char *v11;\n unsigned int v12;\n unsigned int v13;\n void *v14;\n void *v15;\n long long v16;\n long long size;\n *a3 = 0;\n if (a2 <= 0) {\n v14 = malloc(0LL);\n } else {\n v3 = a1;\n v4 = 0;\n do {\n v5 = *v3;\n if ((strlen(*v3) & 1) == 0) {\n v6 = v4++;\n a1[v6] = v5;\n *a3 = v4;\n }\n ++v3;\n } while (&a1[a2] != v3);\n size = 8LL * v4;\n if (v4 > 1) {\n do {\n while (v4 <= 1) --v4;\n v7 = a1;\n v8 = (long long)&a1[(unsigned int)(v4 - 2) + 1];\n do {\n while (1) {\n v9 = *v7;\n v10 = strlen(*v7);\n v11 = v7[1];\n v12 = v10;\n v13 = strlen(v11);\n if (v13 < v12 || v12 == v13 && strcmp(v9, v11) > 0) break;\n if (++v7 == (const char **)v8) goto LABEL_13;\n }\n *(__m128i *)v7++ =\n _mm_unpacklo_epi64((__m128i)(unsigned long long)v11,\n (__m128i)(unsigned long long)v9);\n } while (v7 != (const char **)v8);\n LABEL_13:\n --v4;\n } while (v4 != 1);\n }\n v14 = malloc(size);\n }\n v15 = v14;\n v16 = (unsigned int)*a3;\n if ((int)v16 > 0) return memcpy(v15, a1, 8 * v16);\n return v15;\n}", + "ida_pseudo_norm": "void *func0(const char **a1, int a2, int *a3) {\n const char **v3;\n int v4;\n const char *v5;\n long long v6;\n const char **v7;\n long long v8;\n const char *v9;\n unsigned int v10;\n const char *v11;\n unsigned int v12;\n unsigned int v13;\n void *v14;\n void *v15;\n long long v16;\n long long size;\n *a3 = 0;\n if (a2 <= 0) {\n v14 = malloc(0LL);\n } else {\n v3 = a1;\n v4 = 0;\n do {\n v5 = *v3;\n if ((strlen(*v3) & 1) == 0) {\n v6 = v4++;\n a1[v6] = v5;\n *a3 = v4;\n }\n ++v3;\n } while (&a1[a2] != v3);\n size = 8LL * v4;\n if (v4 > 1) {\n do {\n while (v4 <= 1) --v4;\n v7 = a1;\n v8 = (long long)&a1[(unsigned int)(v4 - 2) + 1];\n do {\n while (1) {\n v9 = *v7;\n v10 = strlen(*v7);\n v11 = v7[1];\n v12 = v10;\n v13 = strlen(v11);\n if (v13 < v12 || v12 == v13 && strcmp(v9, v11) > 0) break;\n if (++v7 == (const char **)v8) goto LABEL_13;\n }\n *(__m128i *)v7++ =\n _mm_unpacklo_epi64((__m128i)(unsigned long long)v11,\n (__m128i)(unsigned long long)v9);\n } while (v7 != (const char **)v8);\n LABEL_13:\n --v4;\n } while (v4 != 1);\n }\n v14 = malloc(size);\n }\n v15 = v14;\n v16 = (unsigned int)*a3;\n if ((int)v16 > 0) return memcpy(v15, a1, 8 * v16);\n return v15;\n}" + }, + { + "index": "HumanEval-C-150", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int n, int x, int y) {\n int isp = 1;\n if (n < 2) isp = 0;\n for (int i = 2; i * i <= n; i++) {\n if (n % i == 0) isp = 0;\n }\n if (isp) return x;\n return y;\n}", + "test": "#include \n\nint main() {\n assert(func0(7, 34, 12) == 34);\n assert(func0(15, 8, 5) == 5);\n assert(func0(3, 33, 5212) == 33);\n assert(func0(1259, 3, 52) == 3);\n assert(func0(7919, -1, 12) == -1);\n assert(func0(3609, 1245, 583) == 583);\n assert(func0(91, 56, 129) == 129);\n assert(func0(6, 34, 1234) == 1234);\n assert(func0(1, 2, 0) == 0);\n assert(func0(2, 2, 0) == 2);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov [rbp+var_8], 1\ncmp [rbp+var_14], 1\njg short loc_116E\nmov [rbp+var_8], 0\nloc_116E:\nmov [rbp+var_4], 2\njmp short loc_118F\nloc_1177:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njnz short loc_118B\nmov [rbp+var_8], 0\nloc_118B:\nadd [rbp+var_4], 1\nloc_118F:\nmov eax, [rbp+var_4]\nimul eax, eax\ncmp [rbp+var_14], eax\njge short loc_1177\ncmp [rbp+var_8], 0\njz short loc_11A5\nmov eax, [rbp+var_18]\njmp short loc_11A8\nloc_11A5:\nmov eax, [rbp+var_1C]\nloc_11A8:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, unsigned int a2, unsigned int a3)\n{\n _BOOL4 v4; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v4 = a1 > 1;\n for ( i = 2; a1 >= i * i; ++i )\n {\n if ( !(a1 % i) )\n v4 = 0;\n }\n if ( v4 )\n return a2;\n else\n return a3;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov [rbp+var_8], 1\ncmp [rbp+var_14], 1\njg short loc_116E\nmov [rbp+var_8], 0\nloc_116E:\nmov [rbp+var_4], 2\njmp short loc_118F\nloc_1177:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njnz short loc_118B\nmov [rbp+var_8], 0\nloc_118B:\nadd [rbp+var_4], 1\nloc_118F:\nmov eax, [rbp+var_4]\nimul eax, eax\ncmp [rbp+var_14], eax\njge short loc_1177\ncmp [rbp+var_8], 0\njz short loc_11A5\nmov eax, [rbp+var_18]\njmp short loc_11A8\nloc_11A5:\nmov eax, [rbp+var_1C]\nloc_11A8:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, unsigned int a2, unsigned int a3)\n{\n _BOOL4 v4; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v4 = a1 > 1;\n for ( i = 2; a1 >= i * i; ++i )\n {\n if ( !(a1 % i) )\n v4 = 0;\n }\n if ( v4 )\n return a2;\n else\n return a3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, unsigned int a2, unsigned int a3) {\n int v4;\n int i;\n v4 = a1 > 1;\n for (i = 2; a1 >= i * i; ++i) {\n if (!(a1 % i)) v4 = 0;\n }\n if (v4)\n return a2;\n else\n return a3;\n}", + "ida_pseudo_norm": "long long func0(int a1, unsigned int a2, unsigned int a3) {\n int v4;\n int i;\n v4 = a1 > 1;\n for (i = 2; a1 >= i * i; ++i) {\n if (!(a1 % i)) v4 = 0;\n }\n if (v4)\n return a2;\n else\n return a3;\n}" + }, + { + "index": "HumanEval-C-150", + "func_name": "func0", + "func_dep": "#include \n", + "func": "int func0(int n, int x, int y) {\n int isp = 1;\n if (n < 2) isp = 0;\n for (int i = 2; i * i <= n; i++) {\n if (n % i == 0) isp = 0;\n }\n if (isp) return x;\n return y;\n}", + "test": "#include \n\nint main() {\n assert(func0(7, 34, 12) == 34);\n assert(func0(15, 8, 5) == 5);\n assert(func0(3, 33, 5212) == 33);\n assert(func0(1259, 3, 52) == 3);\n assert(func0(7919, -1, 12) == -1);\n assert(func0(3609, 1245, 583) == 583);\n assert(func0(91, 56, 129) == 129);\n assert(func0(6, 34, 1234) == 1234);\n assert(func0(1, 2, 0) == 0);\n assert(func0(2, 2, 0) == 2);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmov r10d, edx\ncmp edi, 1\nsetnle r8b\nmovzx r8d, r8b\ncmp edi, 3\njle short loc_117F\nmov ecx, 2\nloc_1165:\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\ncmovz r8d, edx\nadd ecx, 1\nmov r9d, ecx\nimul r9d, ecx\ncmp r9d, edi\njle short loc_1165\nloc_117F:\ntest r8d, r8d\nmov eax, r10d\ncmovnz eax, esi\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, unsigned int a2, unsigned int a3)\n{\n _BOOL4 v3; // r8d\n int v4; // ecx\n __int64 result; // rax\n\n v3 = a1 > 1;\n if ( a1 > 3 )\n {\n v4 = 2;\n do\n {\n if ( !(a1 % v4) )\n v3 = 0;\n ++v4;\n }\n while ( v4 * v4 <= a1 );\n }\n result = a3;\n if ( v3 )\n return a2;\n return result;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmov r10d, edx\ncmp edi, 1\nsetnle r8b\nmovzx r8d, r8b\ncmp edi, 3\njle short loc_117F\nmov ecx, 2\nloc_1165:\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\ncmovz r8d, edx\nadd ecx, 1\nmov r9d, ecx\nimul r9d, ecx\ncmp r9d, edi\njle short loc_1165\nloc_117F:\ntest r8d, r8d\nmov eax, r10d\ncmovnz eax, esi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, unsigned int a2, unsigned int a3)\n{\n _BOOL4 v3; // r8d\n int v4; // ecx\n __int64 result; // rax\n\n v3 = a1 > 1;\n if ( a1 > 3 )\n {\n v4 = 2;\n do\n {\n if ( !(a1 % v4) )\n v3 = 0;\n ++v4;\n }\n while ( v4 * v4 <= a1 );\n }\n result = a3;\n if ( v3 )\n return a2;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, unsigned int a2, unsigned int a3) {\n int v3;\n int v4;\n long long result;\n v3 = a1 > 1;\n if (a1 > 3) {\n v4 = 2;\n do {\n if (!(a1 % v4)) v3 = 0;\n ++v4;\n } while (v4 * v4 <= a1);\n }\n result = a3;\n if (v3) return a2;\n return result;\n}", + "ida_pseudo_norm": "long long func0(int a1, unsigned int a2, unsigned int a3) {\n int v3;\n int v4;\n long long result;\n v3 = a1 > 1;\n if (a1 > 3) {\n v4 = 2;\n do {\n if (!(a1 % v4)) v3 = 0;\n ++v4;\n } while (v4 * v4 <= a1);\n }\n result = a3;\n if (v3) return a2;\n return result;\n}" + }, + { + "index": "HumanEval-C-151", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "long long func0(float lst[], int lst_size) {\n long long sum = 0;\n for (int i = 0; i < lst_size; i++) {\n if (fabs(lst[i] - round(lst[i])) < 1e-4) {\n if (lst[i] > 0 && (int)(round(lst[i])) % 2 == 1) {\n sum += (int)(round(lst[i])) * (int)(round(lst[i]));\n }\n }\n }\n return sum;\n}", + "test": "#include \n\nint main() {\n assert(func0((const float[]){}, 0) == 0);\n assert(func0((const float[]){5, 4}, 2) == 25);\n assert(func0((const float[]){0.1, 0.2, 0.3}, 3) == 0);\n assert(func0((const float[]){-10, -20, -30}, 3) == 0);\n assert(func0((const float[]){-1, -2, 8}, 3) == 0);\n assert(func0((const float[]){0.2, 3, 5}, 3) == 34);\n \n long long odd_sum = 0;\n float lst[200];\n int lst_size = 0;\n\n for (int i = -99; i < 100; i += 2) {\n lst[lst_size++] = i + 0.0f;\n if (i > 0 && i % 2 == 1) odd_sum += i * i;\n }\n\n assert(func0(lst, lst_size) == odd_sum);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_18], 0\nmov [rbp+var_1C], 0\njmp loc_1311\nloc_11B1:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\npxor xmm2, xmm2\ncvtss2sd xmm2, xmm0\nmovsd [rbp+var_38], xmm2\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\npxor xmm3, xmm3\ncvtss2sd xmm3, xmm0\nmovq rax, xmm3\nmovq xmm0, rax; x\ncall _round\nmovapd xmm1, xmm0\nmovsd xmm0, [rbp+var_38]\nsubsd xmm0, xmm1\nmovq xmm1, cs:qword_2170\nandpd xmm1, xmm0\nmovsd xmm0, cs:qword_2180\ncomisd xmm0, xmm1\njbe loc_130D\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\npxor xmm1, xmm1\ncomiss xmm0, xmm1\njbe loc_130D\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\npxor xmm4, xmm4\ncvtss2sd xmm4, xmm0\nmovq rax, xmm4\nmovq xmm0, rax; x\ncall _round\ncvttsd2si edx, xmm0\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\ncmp eax, 1\njnz short loc_130D\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\npxor xmm5, xmm5\ncvtss2sd xmm5, xmm0\nmovq rax, xmm5\nmovq xmm0, rax; x\ncall _round\ncvttsd2si ebx, xmm0\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\npxor xmm6, xmm6\ncvtss2sd xmm6, xmm0\nmovq rax, xmm6\nmovq xmm0, rax; x\ncall _round\ncvttsd2si eax, xmm0\nimul eax, ebx\ncdqe\nadd [rbp+var_18], rax\nloc_130D:\nadd [rbp+var_1C], 1\nloc_1311:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_2C]\njl loc_11B1\nmov rax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int v2; // ebx\n int i; // [rsp+24h] [rbp-1Ch]\n __int64 v5; // [rsp+28h] [rbp-18h]\n\n v5 = 0LL;\n for ( i = 0; i < a2; ++i )\n {\n if ( fabs(*(float *)(4LL * i + a1) - round(*(float *)(4LL * i + a1))) < 0.0001\n && *(float *)(4LL * i + a1) > 0.0\n && (int)round(*(float *)(4LL * i + a1)) % 2 == 1 )\n {\n v2 = (int)round(*(float *)(4LL * i + a1));\n v5 += v2 * (int)round(*(float *)(4LL * i + a1));\n }\n }\n return v5;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_18], 0\nmov [rbp+var_1C], 0\njmp loc_1311\nloc_11B1:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\npxor xmm2, xmm2\ncvtss2sd xmm2, xmm0\nmovsd [rbp+var_38], xmm2\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\npxor xmm3, xmm3\ncvtss2sd xmm3, xmm0\nmovq rax, xmm3\nmovq xmm0, rax; x\ncall _round\nmovapd xmm1, xmm0\nmovsd xmm0, [rbp+var_38]\nsubsd xmm0, xmm1\nmovq xmm1, cs:qword_2170\nandpd xmm1, xmm0\nmovsd xmm0, cs:qword_2180\ncomisd xmm0, xmm1\njbe loc_130D\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\npxor xmm1, xmm1\ncomiss xmm0, xmm1\njbe loc_130D\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\npxor xmm4, xmm4\ncvtss2sd xmm4, xmm0\nmovq rax, xmm4\nmovq xmm0, rax; x\ncall _round\ncvttsd2si edx, xmm0\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\ncmp eax, 1\njnz short loc_130D\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\npxor xmm5, xmm5\ncvtss2sd xmm5, xmm0\nmovq rax, xmm5\nmovq xmm0, rax; x\ncall _round\ncvttsd2si ebx, xmm0\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovss xmm0, dword ptr [rax]\npxor xmm6, xmm6\ncvtss2sd xmm6, xmm0\nmovq rax, xmm6\nmovq xmm0, rax; x\ncall _round\ncvttsd2si eax, xmm0\nimul eax, ebx\ncdqe\nadd [rbp+var_18], rax\nloc_130D:\nadd [rbp+var_1C], 1\nloc_1311:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_2C]\njl loc_11B1\nmov rax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2)\n{\n int v2; // ebx\n int i; // [rsp+24h] [rbp-1Ch]\n __int64 v5; // [rsp+28h] [rbp-18h]\n\n v5 = 0LL;\n for ( i = 0; i < a2; ++i )\n {\n if ( fabs(*(float *)(4LL * i + a1) - round(*(float *)(4LL * i + a1))) < 0.0001\n && *(float *)(4LL * i + a1) > 0.0\n && (int)round(*(float *)(4LL * i + a1)) % 2 == 1 )\n {\n v2 = (int)round(*(float *)(4LL * i + a1));\n v5 += v2 * (int)round(*(float *)(4LL * i + a1));\n }\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2) {\n int v2;\n int i;\n long long v5;\n v5 = 0LL;\n for (i = 0; i < a2; ++i) {\n if (fabs(*(float *)(4LL * i + a1) - round(*(float *)(4LL * i + a1))) <\n 0.0001 &&\n *(float *)(4LL * i + a1) > 0.0 &&\n (int)round(*(float *)(4LL * i + a1)) % 2 == 1) {\n v2 = (int)round(*(float *)(4LL * i + a1));\n v5 += v2 * (int)round(*(float *)(4LL * i + a1));\n }\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int v2;\n int i;\n long long v5;\n v5 = 0LL;\n for (i = 0; i < a2; ++i) {\n if (fabs(*(float *)(4LL * i + a1) - round(*(float *)(4LL * i + a1))) <\n 0.0001 &&\n *(float *)(4LL * i + a1) > 0.0 &&\n (int)round(*(float *)(4LL * i + a1)) % 2 == 1) {\n v2 = (int)round(*(float *)(4LL * i + a1));\n v5 += v2 * (int)round(*(float *)(4LL * i + a1));\n }\n }\n return v5;\n}" + }, + { + "index": "HumanEval-C-151", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "long long func0(float lst[], int lst_size) {\n long long sum = 0;\n for (int i = 0; i < lst_size; i++) {\n if (fabs(lst[i] - round(lst[i])) < 1e-4) {\n if (lst[i] > 0 && (int)(round(lst[i])) % 2 == 1) {\n sum += (int)(round(lst[i])) * (int)(round(lst[i]));\n }\n }\n }\n return sum;\n}", + "test": "#include \n\nint main() {\n assert(func0((const float[]){}, 0) == 0);\n assert(func0((const float[]){5, 4}, 2) == 25);\n assert(func0((const float[]){0.1, 0.2, 0.3}, 3) == 0);\n assert(func0((const float[]){-10, -20, -30}, 3) == 0);\n assert(func0((const float[]){-1, -2, 8}, 3) == 0);\n assert(func0((const float[]){0.2, 3, 5}, 3) == 34);\n \n long long odd_sum = 0;\n float lst[200];\n int lst_size = 0;\n\n for (int i = -99; i < 100; i += 2) {\n lst[lst_size++] = i + 0.0f;\n if (i > 0 && i % 2 == 1) odd_sum += i * i;\n }\n\n assert(func0(lst, lst_size) == odd_sum);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 10h\ntest esi, esi\njle loc_1224\nmov rbx, rdi\nmovsxd rsi, esi\nlea rbp, [rdi+rsi*4]\nmov r12d, 0\njmp short loc_11B8\nloc_11AF:\nadd rbx, 4\ncmp rbx, rbp\njz short loc_122A\nloc_11B8:\nmovss xmm3, dword ptr [rbx]\nmovss [rsp+28h+var_1C], xmm3\nmovaps xmm0, xmm3; x\ncall _roundf\nmovss xmm3, [rsp+28h+var_1C]\npxor xmm1, xmm1\ncvtss2sd xmm1, xmm3\npxor xmm2, xmm2\ncvtss2sd xmm2, xmm0\nsubsd xmm1, xmm2\nandpd xmm1, cs:xmmword_2160\nmovsd xmm4, cs:qword_2170\ncomisd xmm4, xmm1\njbe short loc_11AF\npxor xmm5, xmm5\ncomiss xmm3, xmm5\njbe short loc_11AF\ncvttss2si edx, xmm0\nmov ecx, edx\nshr ecx, 1Fh\nlea eax, [rdx+rcx]\nand eax, 1\nsub eax, ecx\ncmp eax, 1\njnz short loc_11AF\nimul edx, edx\nmovsxd rdx, edx\nadd r12, rdx\njmp short loc_11AF\nloc_1224:\nmov r12d, 0\nloc_122A:\nmov rax, r12\nadd rsp, 10h\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "__int64 __fastcall func0(float *a1, int a2)\n{\n float *v2; // rbx\n __int64 v3; // r12\n float v4; // xmm0_4\n float v6; // [rsp+Ch] [rbp-1Ch]\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = a1;\n v3 = 0LL;\n do\n {\n v6 = *v2;\n v4 = roundf(*v2);\n if ( fabs(v6 - v4) < 0.0001 && v6 > 0.0 && (int)v4 % 2 == 1 )\n v3 += (int)v4 * (int)v4;\n ++v2;\n }\n while ( v2 != &a1[a2] );\n return v3;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 10h\ntest esi, esi\njle loc_1224\nmov rbx, rdi\nmovsxd rsi, esi\nlea rbp, [rdi+rsi*4]\nmov r12d, 0\njmp short loc_11B8\nloc_11AF:\nadd rbx, 4\ncmp rbx, rbp\njz short loc_122A\nloc_11B8:\nmovss xmm3, dword ptr [rbx]\nmovss [rsp+28h+var_1C], xmm3\nmovaps xmm0, xmm3; x\ncall _roundf\nmovss xmm3, [rsp+28h+var_1C]\npxor xmm1, xmm1\ncvtss2sd xmm1, xmm3\npxor xmm2, xmm2\ncvtss2sd xmm2, xmm0\nsubsd xmm1, xmm2\nandpd xmm1, cs:xmmword_2160\nmovsd xmm4, cs:qword_2170\ncomisd xmm4, xmm1\njbe short loc_11AF\npxor xmm5, xmm5\ncomiss xmm3, xmm5\njbe short loc_11AF\ncvttss2si edx, xmm0\nmov ecx, edx\nshr ecx, 1Fh\nlea eax, [rdx+rcx]\nand eax, 1\nsub eax, ecx\ncmp eax, 1\njnz short loc_11AF\nimul edx, edx\nmovsxd rdx, edx\nadd r12, rdx\njmp short loc_11AF\nloc_1224:\nmov r12d, 0\nloc_122A:\nmov rax, r12\nadd rsp, 10h\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(float *a1, int a2)\n{\n float *v2; // rbx\n __int64 v3; // r12\n float v4; // xmm0_4\n float v6; // [rsp+Ch] [rbp-1Ch]\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = a1;\n v3 = 0LL;\n do\n {\n v6 = *v2;\n v4 = roundf(*v2);\n if ( fabs(v6 - v4) < 0.0001 && v6 > 0.0 && (int)v4 % 2 == 1 )\n v3 += (int)v4 * (int)v4;\n ++v2;\n }\n while ( v2 != &a1[a2] );\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(float *a1, int a2) {\n float *v2;\n long long v3;\n float v4;\n float v6;\n if (a2 <= 0) return 0LL;\n v2 = a1;\n v3 = 0LL;\n do {\n v6 = *v2;\n v4 = roundf(*v2);\n if (fabs(v6 - v4) < 0.0001 && v6 > 0.0 && (int)v4 % 2 == 1)\n v3 += (int)v4 * (int)v4;\n ++v2;\n } while (v2 != &a1[a2]);\n return v3;\n}", + "ida_pseudo_norm": "long long func0(float *a1, int a2) {\n float *v2;\n long long v3;\n float v4;\n float v6;\n if (a2 <= 0) return 0LL;\n v2 = a1;\n v3 = 0LL;\n do {\n v6 = *v2;\n v4 = roundf(*v2);\n if (fabs(v6 - v4) < 0.0001 && v6 > 0.0 && (int)v4 % 2 == 1)\n v3 += (int)v4 * (int)v4;\n ++v2;\n } while (v2 != &a1[a2]);\n return v3;\n}" + }, + { + "index": "HumanEval-C-151", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "long long func0(float lst[], int lst_size) {\n long long sum = 0;\n for (int i = 0; i < lst_size; i++) {\n if (fabs(lst[i] - round(lst[i])) < 1e-4) {\n if (lst[i] > 0 && (int)(round(lst[i])) % 2 == 1) {\n sum += (int)(round(lst[i])) * (int)(round(lst[i]));\n }\n }\n }\n return sum;\n}", + "test": "#include \n\nint main() {\n assert(func0((const float[]){}, 0) == 0);\n assert(func0((const float[]){5, 4}, 2) == 25);\n assert(func0((const float[]){0.1, 0.2, 0.3}, 3) == 0);\n assert(func0((const float[]){-10, -20, -30}, 3) == 0);\n assert(func0((const float[]){-1, -2, 8}, 3) == 0);\n assert(func0((const float[]){0.2, 3, 5}, 3) == 34);\n \n long long odd_sum = 0;\n float lst[200];\n int lst_size = 0;\n\n for (int i = -99; i < 100; i += 2) {\n lst[lst_size++] = i + 0.0f;\n if (i > 0 && i % 2 == 1) odd_sum += i * i;\n }\n\n assert(func0(lst, lst_size) == odd_sum);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 10h\ntest esi, esi\njle loc_1530\nmovsxd rsi, esi\nmov rbx, rdi\nxor r12d, r12d\nlea rbp, [rdi+rsi*4]\nnop dword ptr [rax+00000000h]\nloc_14A8:\nmovss xmm2, dword ptr [rbx]\nmovaps xmm0, xmm2; x\nmovss [rsp+28h+var_1C], xmm2\ncall _roundf\nmovss xmm2, [rsp+28h+var_1C]\npxor xmm1, xmm1\npxor xmm3, xmm3\nmovsd xmm4, cs:qword_2190\ncvtss2sd xmm3, xmm0\ncvtss2sd xmm1, xmm2\nsubsd xmm1, xmm3\nandpd xmm1, cs:xmmword_2160\ncomisd xmm4, xmm1\njbe short loc_1518\npxor xmm5, xmm5\ncomiss xmm2, xmm5\njbe short loc_1518\ncvttss2si edx, xmm0\nmov ecx, edx\nshr ecx, 1Fh\nlea eax, [rdx+rcx]\nand eax, 1\nsub eax, ecx\ncmp eax, 1\njnz short loc_1518\nimul edx, edx\nmovsxd rdx, edx\nadd r12, rdx\nnop word ptr [rax+rax+00h]\nloc_1518:\nadd rbx, 4\ncmp rbp, rbx\njnz short loc_14A8\nadd rsp, 10h\nmov rax, r12\npop rbx\npop rbp\npop r12\nretn\nloc_1530:\nadd rsp, 10h\nxor r12d, r12d\nmov rax, r12\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "__int64 __fastcall func0(float *a1, int a2)\n{\n float *v2; // rbx\n __int64 v3; // r12\n float v4; // xmm0_4\n float v6; // [rsp+Ch] [rbp-1Ch]\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = a1;\n v3 = 0LL;\n do\n {\n v6 = *v2;\n v4 = roundf(*v2);\n if ( fabs(v6 - v4) < 0.0001 && v6 > 0.0 && (int)v4 % 2 == 1 )\n v3 += (int)v4 * (int)v4;\n ++v2;\n }\n while ( &a1[a2] != v2 );\n return v3;\n}", + "ida_strip_asm": "sub_1480:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 10h\ntest esi, esi\njle loc_1530\nmovsxd rsi, esi\nmov rbx, rdi\nxor r12d, r12d\nlea rbp, [rdi+rsi*4]\nnop dword ptr [rax+00000000h]\nloc_14A8:\nmovss xmm2, dword ptr [rbx]\nmovaps xmm0, xmm2; x\nmovss [rsp+28h+var_1C], xmm2\ncall _roundf\nmovss xmm2, [rsp+28h+var_1C]\npxor xmm1, xmm1\npxor xmm3, xmm3\nmovsd xmm4, cs:qword_2190\ncvtss2sd xmm3, xmm0\ncvtss2sd xmm1, xmm2\nsubsd xmm1, xmm3\nandpd xmm1, cs:xmmword_2160\ncomisd xmm4, xmm1\njbe short loc_1518\npxor xmm5, xmm5\ncomiss xmm2, xmm5\njbe short loc_1518\ncvttss2si edx, xmm0\nmov ecx, edx\nshr ecx, 1Fh\nlea eax, [rdx+rcx]\nand eax, 1\nsub eax, ecx\ncmp eax, 1\njnz short loc_1518\nimul edx, edx\nmovsxd rdx, edx\nadd r12, rdx\nnop word ptr [rax+rax+00h]\nloc_1518:\nadd rbx, 4\ncmp rbp, rbx\njnz short loc_14A8\nadd rsp, 10h\nmov rax, r12\npop rbx\npop rbp\npop r12\nretn\nloc_1530:\nadd rsp, 10h\nxor r12d, r12d\nmov rax, r12\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1480(float *a1, int a2)\n{\n float *v2; // rbx\n __int64 v3; // r12\n float v4; // xmm0_4\n float v6; // [rsp+Ch] [rbp-1Ch]\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = a1;\n v3 = 0LL;\n do\n {\n v6 = *v2;\n v4 = roundf(*v2);\n if ( fabs(v6 - v4) < 0.0001 && v6 > 0.0 && (int)v4 % 2 == 1 )\n v3 += (int)v4 * (int)v4;\n ++v2;\n }\n while ( &a1[a2] != v2 );\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1480(float *a1, int a2) {\n float *v2;\n long long v3;\n float v4;\n float v6;\n if (a2 <= 0) return 0LL;\n v2 = a1;\n v3 = 0LL;\n do {\n v6 = *v2;\n v4 = roundf(*v2);\n if (fabs(v6 - v4) < 0.0001 && v6 > 0.0 && (int)v4 % 2 == 1)\n v3 += (int)v4 * (int)v4;\n ++v2;\n } while (&a1[a2] != v2);\n return v3;\n}", + "ida_pseudo_norm": "long long func0(float *a1, int a2) {\n float *v2;\n long long v3;\n float v4;\n float v6;\n if (a2 <= 0) return 0LL;\n v2 = a1;\n v3 = 0LL;\n do {\n v6 = *v2;\n v4 = roundf(*v2);\n if (fabs(v6 - v4) < 0.0001 && v6 > 0.0 && (int)v4 % 2 == 1)\n v3 += (int)v4 * (int)v4;\n ++v2;\n } while (&a1[a2] != v2);\n return v3;\n}" + }, + { + "index": "HumanEval-C-151", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "long long func0(float lst[], int lst_size) {\n long long sum = 0;\n for (int i = 0; i < lst_size; i++) {\n if (fabs(lst[i] - round(lst[i])) < 1e-4) {\n if (lst[i] > 0 && (int)(round(lst[i])) % 2 == 1) {\n sum += (int)(round(lst[i])) * (int)(round(lst[i]));\n }\n }\n }\n return sum;\n}", + "test": "#include \n\nint main() {\n assert(func0((const float[]){}, 0) == 0);\n assert(func0((const float[]){5, 4}, 2) == 25);\n assert(func0((const float[]){0.1, 0.2, 0.3}, 3) == 0);\n assert(func0((const float[]){-10, -20, -30}, 3) == 0);\n assert(func0((const float[]){-1, -2, 8}, 3) == 0);\n assert(func0((const float[]){0.2, 3, 5}, 3) == 34);\n \n long long odd_sum = 0;\n float lst[200];\n int lst_size = 0;\n\n for (int i = -99; i < 100; i += 2) {\n lst[lst_size++] = i + 0.0f;\n if (i > 0 && i % 2 == 1) odd_sum += i * i;\n }\n\n assert(func0(lst, lst_size) == odd_sum);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 10h\ntest esi, esi\njle loc_1530\nmovsxd rsi, esi\nmov rbx, rdi\nxor r12d, r12d\nlea rbp, [rdi+rsi*4]\nnop dword ptr [rax+00000000h]\nloc_14A8:\nmovss xmm2, dword ptr [rbx]\nmovaps xmm0, xmm2; x\nmovss [rsp+28h+var_1C], xmm2\ncall _roundf\nmovss xmm2, [rsp+28h+var_1C]\npxor xmm1, xmm1\npxor xmm3, xmm3\nmovsd xmm4, cs:qword_2190\ncvtss2sd xmm3, xmm0\ncvtss2sd xmm1, xmm2\nsubsd xmm1, xmm3\nandpd xmm1, cs:xmmword_2160\ncomisd xmm4, xmm1\njbe short loc_1518\npxor xmm5, xmm5\ncomiss xmm2, xmm5\njbe short loc_1518\ncvttss2si edx, xmm0\nmov ecx, edx\nshr ecx, 1Fh\nlea eax, [rdx+rcx]\nand eax, 1\nsub eax, ecx\ncmp eax, 1\njnz short loc_1518\nimul edx, edx\nmovsxd rdx, edx\nadd r12, rdx\nnop word ptr [rax+rax+00h]\nloc_1518:\nadd rbx, 4\ncmp rbp, rbx\njnz short loc_14A8\nadd rsp, 10h\nmov rax, r12\npop rbx\npop rbp\npop r12\nretn\nloc_1530:\nadd rsp, 10h\nxor r12d, r12d\nmov rax, r12\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "__int64 __fastcall func0(float *a1, int a2)\n{\n float *v2; // rbx\n __int64 v3; // r12\n float v4; // xmm0_4\n float v6; // [rsp+Ch] [rbp-1Ch]\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = a1;\n v3 = 0LL;\n do\n {\n v6 = *v2;\n v4 = roundf(*v2);\n if ( fabs(v6 - v4) < 0.0001 && v6 > 0.0 && (int)v4 % 2 == 1 )\n v3 += (int)v4 * (int)v4;\n ++v2;\n }\n while ( &a1[a2] != v2 );\n return v3;\n}", + "ida_strip_asm": "sub_1480:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 10h\ntest esi, esi\njle loc_1530\nmovsxd rsi, esi\nmov rbx, rdi\nxor r12d, r12d\nlea rbp, [rdi+rsi*4]\nnop dword ptr [rax+00000000h]\nloc_14A8:\nmovss xmm2, dword ptr [rbx]\nmovaps xmm0, xmm2; x\nmovss [rsp+28h+var_1C], xmm2\ncall _roundf\nmovss xmm2, [rsp+28h+var_1C]\npxor xmm1, xmm1\npxor xmm3, xmm3\nmovsd xmm4, cs:qword_2190\ncvtss2sd xmm3, xmm0\ncvtss2sd xmm1, xmm2\nsubsd xmm1, xmm3\nandpd xmm1, cs:xmmword_2160\ncomisd xmm4, xmm1\njbe short loc_1518\npxor xmm5, xmm5\ncomiss xmm2, xmm5\njbe short loc_1518\ncvttss2si edx, xmm0\nmov ecx, edx\nshr ecx, 1Fh\nlea eax, [rdx+rcx]\nand eax, 1\nsub eax, ecx\ncmp eax, 1\njnz short loc_1518\nimul edx, edx\nmovsxd rdx, edx\nadd r12, rdx\nnop word ptr [rax+rax+00h]\nloc_1518:\nadd rbx, 4\ncmp rbp, rbx\njnz short loc_14A8\nadd rsp, 10h\nmov rax, r12\npop rbx\npop rbp\npop r12\nretn\nloc_1530:\nadd rsp, 10h\nxor r12d, r12d\nmov rax, r12\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1480(float *a1, int a2)\n{\n float *v2; // rbx\n __int64 v3; // r12\n float v4; // xmm0_4\n float v6; // [rsp+Ch] [rbp-1Ch]\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = a1;\n v3 = 0LL;\n do\n {\n v6 = *v2;\n v4 = roundf(*v2);\n if ( fabs(v6 - v4) < 0.0001 && v6 > 0.0 && (int)v4 % 2 == 1 )\n v3 += (int)v4 * (int)v4;\n ++v2;\n }\n while ( &a1[a2] != v2 );\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1480(float *a1, int a2) {\n float *v2;\n long long v3;\n float v4;\n float v6;\n if (a2 <= 0) return 0LL;\n v2 = a1;\n v3 = 0LL;\n do {\n v6 = *v2;\n v4 = roundf(*v2);\n if (fabs(v6 - v4) < 0.0001 && v6 > 0.0 && (int)v4 % 2 == 1)\n v3 += (int)v4 * (int)v4;\n ++v2;\n } while (&a1[a2] != v2);\n return v3;\n}", + "ida_pseudo_norm": "long long func0(float *a1, int a2) {\n float *v2;\n long long v3;\n float v4;\n float v6;\n if (a2 <= 0) return 0LL;\n v2 = a1;\n v3 = 0LL;\n do {\n v6 = *v2;\n v4 = roundf(*v2);\n if (fabs(v6 - v4) < 0.0001 && v6 > 0.0 && (int)v4 % 2 == 1)\n v3 += (int)v4 * (int)v4;\n ++v2;\n } while (&a1[a2] != v2);\n return v3;\n}" + }, + { + "index": "HumanEval-C-152", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(int* game, int* guess, int* out, int length) {\n for (int i = 0; i < length; i++) {\n out[i] = abs(game[i] - guess[i]);\n }\n}", + "test": "#include \n#include \n\nint issame(int* a, int* b, int length) {\n for (int i = 0; i < length; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int result[6];\n\n func0((const int[]){1,2,3,4,5,1}, (const int[]){1,2,3,4,2,-2}, result, 6);\n assert(issame(result, (const int[]){0,0,0,0,3,3}, 6));\n\n func0((const int[]){0,5,0,0,0,4}, (const int[]){4,1,1,0,0,-2}, result, 6);\n assert(issame(result, (const int[]){4,4,1,0,0,6}, 6));\n\n func0((const int[]){1,2,3,4,5,1}, (const int[]){1,2,3,4,2,-2}, result, 6);\n assert(issame(result, (const int[]){0,0,0,0,3,3}, 6));\n\n func0((const int[]){0,0,0,0,0,0}, (const int[]){0,0,0,0,0,0}, result, 6);\n assert(issame(result, (const int[]){0,0,0,0,0,0}, 6));\n\n func0((const int[]){1,2,3}, (const int[]){-1,-2,-3}, result, 3);\n assert(issame(result, (const int[]){2,4,6}, 3));\n\n func0((const int[]){1,2,3,5}, (const int[]){-1,2,3,4}, result, 4);\n assert(issame(result, (const int[]){2,0,0,1}, 4));\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_28], rdx\nmov [rbp+var_2C], ecx\nmov [rbp+var_4], 0\njmp short loc_11DA\nloc_1189:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_20]\nadd rdx, rcx\nmov edx, [rdx]\nsub eax, edx\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov ecx, eax\nneg ecx\ncmovns eax, ecx\nmov [rdx], eax\nadd [rbp+var_4], 1\nloc_11DA:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_2C]\njl short loc_1189\nnop\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n int v4; // eax\n __int64 result; // rax\n unsigned int i; // [rsp+28h] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a4 )\n break;\n v4 = *(_DWORD *)(4LL * (int)i + a1) - *(_DWORD *)(4LL * (int)i + a2);\n if ( *(_DWORD *)(4LL * (int)i + a2) - *(_DWORD *)(4LL * (int)i + a1) >= 0 )\n v4 = *(_DWORD *)(4LL * (int)i + a2) - *(_DWORD *)(4LL * (int)i + a1);\n *(_DWORD *)(4LL * (int)i + a3) = v4;\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_28], rdx\nmov [rbp+var_2C], ecx\nmov [rbp+var_4], 0\njmp short loc_11DA\nloc_1189:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_20]\nadd rdx, rcx\nmov edx, [rdx]\nsub eax, edx\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov ecx, eax\nneg ecx\ncmovns eax, ecx\nmov [rdx], eax\nadd [rbp+var_4], 1\nloc_11DA:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_2C]\njl short loc_1189\nnop\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n int v4; // eax\n __int64 result; // rax\n unsigned int i; // [rsp+28h] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a4 )\n break;\n v4 = *(_DWORD *)(4LL * (int)i + a1) - *(_DWORD *)(4LL * (int)i + a2);\n if ( *(_DWORD *)(4LL * (int)i + a2) - *(_DWORD *)(4LL * (int)i + a1) >= 0 )\n v4 = *(_DWORD *)(4LL * (int)i + a2) - *(_DWORD *)(4LL * (int)i + a1);\n *(_DWORD *)(4LL * (int)i + a3) = v4;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, long long a3, int a4) {\n int v4;\n long long result;\n unsigned int i;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a4) break;\n v4 = *(uint32_t *)(4LL * (int)i + a1) - *(uint32_t *)(4LL * (int)i + a2);\n if (*(uint32_t *)(4LL * (int)i + a2) - *(uint32_t *)(4LL * (int)i + a1) >=\n 0)\n v4 = *(uint32_t *)(4LL * (int)i + a2) - *(uint32_t *)(4LL * (int)i + a1);\n *(uint32_t *)(4LL * (int)i + a3) = v4;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, long long a3, int a4) {\n int v4;\n long long result;\n unsigned int i;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a4) break;\n v4 = *(uint32_t *)(4LL * (int)i + a1) - *(uint32_t *)(4LL * (int)i + a2);\n if (*(uint32_t *)(4LL * (int)i + a2) - *(uint32_t *)(4LL * (int)i + a1) >=\n 0)\n v4 = *(uint32_t *)(4LL * (int)i + a2) - *(uint32_t *)(4LL * (int)i + a1);\n *(uint32_t *)(4LL * (int)i + a3) = v4;\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-152", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(int* game, int* guess, int* out, int length) {\n for (int i = 0; i < length; i++) {\n out[i] = abs(game[i] - guess[i]);\n }\n}", + "test": "#include \n#include \n\nint issame(int* a, int* b, int length) {\n for (int i = 0; i < length; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int result[6];\n\n func0((const int[]){1,2,3,4,5,1}, (const int[]){1,2,3,4,2,-2}, result, 6);\n assert(issame(result, (const int[]){0,0,0,0,3,3}, 6));\n\n func0((const int[]){0,5,0,0,0,4}, (const int[]){4,1,1,0,0,-2}, result, 6);\n assert(issame(result, (const int[]){4,4,1,0,0,6}, 6));\n\n func0((const int[]){1,2,3,4,5,1}, (const int[]){1,2,3,4,2,-2}, result, 6);\n assert(issame(result, (const int[]){0,0,0,0,3,3}, 6));\n\n func0((const int[]){0,0,0,0,0,0}, (const int[]){0,0,0,0,0,0}, result, 6);\n assert(issame(result, (const int[]){0,0,0,0,0,0}, 6));\n\n func0((const int[]){1,2,3}, (const int[]){-1,-2,-3}, result, 3);\n assert(issame(result, (const int[]){2,4,6}, 3));\n\n func0((const int[]){1,2,3,5}, (const int[]){-1,2,3,4}, result, 4);\n assert(issame(result, (const int[]){2,0,0,1}, 4));\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmov r9, rdi\ntest ecx, ecx\njle short locret_119E\nmovsxd rcx, ecx\nlea r8, ds:0[rcx*4]\nmov eax, 0\nloc_1184:\nmov ecx, [r9+rax]\nsub ecx, [rsi+rax]\nmov edi, ecx\nneg edi\ncmovns ecx, edi\nmov [rdx+rax], ecx\nadd rax, 4\ncmp rax, r8\njnz short loc_1184\nlocret_119E:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 v4; // r8\n __int64 v5; // rax\n int v6; // ecx\n\n if ( a4 > 0 )\n {\n v4 = 4LL * a4;\n v5 = 0LL;\n do\n {\n v6 = *(_DWORD *)(a1 + v5) - *(_DWORD *)(a2 + v5);\n if ( *(_DWORD *)(a2 + v5) - *(_DWORD *)(a1 + v5) >= 0 )\n v6 = *(_DWORD *)(a2 + v5) - *(_DWORD *)(a1 + v5);\n *(_DWORD *)(a3 + v5) = v6;\n v5 += 4LL;\n }\n while ( v5 != v4 );\n }\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov r9, rdi\ntest ecx, ecx\njle short locret_119E\nmovsxd rcx, ecx\nlea r8, ds:0[rcx*4]\nmov eax, 0\nloc_1184:\nmov ecx, [r9+rax]\nsub ecx, [rsi+rax]\nmov edi, ecx\nneg edi\ncmovns ecx, edi\nmov [rdx+rax], ecx\nadd rax, 4\ncmp rax, r8\njnz short loc_1184\nlocret_119E:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1169(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 v4; // r8\n __int64 v5; // rax\n int v6; // ecx\n\n if ( a4 > 0 )\n {\n v4 = 4LL * a4;\n v5 = 0LL;\n do\n {\n v6 = *(_DWORD *)(a1 + v5) - *(_DWORD *)(a2 + v5);\n if ( *(_DWORD *)(a2 + v5) - *(_DWORD *)(a1 + v5) >= 0 )\n v6 = *(_DWORD *)(a2 + v5) - *(_DWORD *)(a1 + v5);\n *(_DWORD *)(a3 + v5) = v6;\n v5 += 4LL;\n }\n while ( v5 != v4 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1169(long long a1, long long a2, long long a3, int a4) {\n long long v4;\n long long v5;\n int v6;\n if (a4 > 0) {\n v4 = 4LL * a4;\n v5 = 0LL;\n do {\n v6 = *(uint32_t *)(a1 + v5) - *(uint32_t *)(a2 + v5);\n if (*(uint32_t *)(a2 + v5) - *(uint32_t *)(a1 + v5) >= 0)\n v6 = *(uint32_t *)(a2 + v5) - *(uint32_t *)(a1 + v5);\n *(uint32_t *)(a3 + v5) = v6;\n v5 += 4LL;\n } while (v5 != v4);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, long long a2, long long a3, int a4) {\n long long v4;\n long long v5;\n int v6;\n if (a4 > 0) {\n v4 = 4LL * a4;\n v5 = 0LL;\n do {\n v6 = *(uint32_t *)(a1 + v5) - *(uint32_t *)(a2 + v5);\n if (*(uint32_t *)(a2 + v5) - *(uint32_t *)(a1 + v5) >= 0)\n v6 = *(uint32_t *)(a2 + v5) - *(uint32_t *)(a1 + v5);\n *(uint32_t *)(a3 + v5) = v6;\n v5 += 4LL;\n } while (v5 != v4);\n }\n}" + }, + { + "index": "HumanEval-C-152", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(int* game, int* guess, int* out, int length) {\n for (int i = 0; i < length; i++) {\n out[i] = abs(game[i] - guess[i]);\n }\n}", + "test": "#include \n#include \n\nint issame(int* a, int* b, int length) {\n for (int i = 0; i < length; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int result[6];\n\n func0((const int[]){1,2,3,4,5,1}, (const int[]){1,2,3,4,2,-2}, result, 6);\n assert(issame(result, (const int[]){0,0,0,0,3,3}, 6));\n\n func0((const int[]){0,5,0,0,0,4}, (const int[]){4,1,1,0,0,-2}, result, 6);\n assert(issame(result, (const int[]){4,4,1,0,0,6}, 6));\n\n func0((const int[]){1,2,3,4,5,1}, (const int[]){1,2,3,4,2,-2}, result, 6);\n assert(issame(result, (const int[]){0,0,0,0,3,3}, 6));\n\n func0((const int[]){0,0,0,0,0,0}, (const int[]){0,0,0,0,0,0}, result, 6);\n assert(issame(result, (const int[]){0,0,0,0,0,0}, 6));\n\n func0((const int[]){1,2,3}, (const int[]){-1,-2,-3}, result, 3);\n assert(issame(result, (const int[]){2,4,6}, 3));\n\n func0((const int[]){1,2,3,5}, (const int[]){-1,2,3,4}, result, 4);\n assert(issame(result, (const int[]){2,0,0,1}, 4));\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmov r9, rdi\ntest ecx, ecx\njle short locret_159A\nmovsxd rcx, ecx\nxor eax, eax\nlea r8, ds:0[rcx*4]\nnop dword ptr [rax+rax+00000000h]\nloc_1580:\nmov ecx, [r9+rax]\nsub ecx, [rsi+rax]\nmov edi, ecx\nneg edi\ncmovns ecx, edi\nmov [rdx+rax], ecx\nadd rax, 4\ncmp r8, rax\njnz short loc_1580\nlocret_159A:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 v4; // rax\n __int64 v5; // r8\n int v6; // ecx\n\n if ( a4 > 0 )\n {\n v4 = 0LL;\n v5 = 4LL * a4;\n do\n {\n v6 = *(_DWORD *)(a1 + v4) - *(_DWORD *)(a2 + v4);\n if ( *(_DWORD *)(a2 + v4) - *(_DWORD *)(a1 + v4) >= 0 )\n v6 = *(_DWORD *)(a2 + v4) - *(_DWORD *)(a1 + v4);\n *(_DWORD *)(a3 + v4) = v6;\n v4 += 4LL;\n }\n while ( v5 != v4 );\n }\n}", + "ida_strip_asm": "sub_1560:\nendbr64\nmov r9, rdi\ntest ecx, ecx\njle short locret_159A\nmovsxd rcx, ecx\nxor eax, eax\nlea r8, ds:0[rcx*4]\nnop dword ptr [rax+rax+00000000h]\nloc_1580:\nmov ecx, [r9+rax]\nsub ecx, [rsi+rax]\nmov edi, ecx\nneg edi\ncmovns ecx, edi\nmov [rdx+rax], ecx\nadd rax, 4\ncmp r8, rax\njnz short loc_1580\nlocret_159A:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1560(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 v4; // rax\n __int64 v5; // r8\n int v6; // ecx\n\n if ( a4 > 0 )\n {\n v4 = 0LL;\n v5 = 4LL * a4;\n do\n {\n v6 = *(_DWORD *)(a1 + v4) - *(_DWORD *)(a2 + v4);\n if ( *(_DWORD *)(a2 + v4) - *(_DWORD *)(a1 + v4) >= 0 )\n v6 = *(_DWORD *)(a2 + v4) - *(_DWORD *)(a1 + v4);\n *(_DWORD *)(a3 + v4) = v6;\n v4 += 4LL;\n }\n while ( v5 != v4 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1560(long long a1, long long a2, long long a3, int a4) {\n long long v4;\n long long v5;\n int v6;\n if (a4 > 0) {\n v4 = 0LL;\n v5 = 4LL * a4;\n do {\n v6 = *(uint32_t *)(a1 + v4) - *(uint32_t *)(a2 + v4);\n if (*(uint32_t *)(a2 + v4) - *(uint32_t *)(a1 + v4) >= 0)\n v6 = *(uint32_t *)(a2 + v4) - *(uint32_t *)(a1 + v4);\n *(uint32_t *)(a3 + v4) = v6;\n v4 += 4LL;\n } while (v5 != v4);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, long long a2, long long a3, int a4) {\n long long v4;\n long long v5;\n int v6;\n if (a4 > 0) {\n v4 = 0LL;\n v5 = 4LL * a4;\n do {\n v6 = *(uint32_t *)(a1 + v4) - *(uint32_t *)(a2 + v4);\n if (*(uint32_t *)(a2 + v4) - *(uint32_t *)(a1 + v4) >= 0)\n v6 = *(uint32_t *)(a2 + v4) - *(uint32_t *)(a1 + v4);\n *(uint32_t *)(a3 + v4) = v6;\n v4 += 4LL;\n } while (v5 != v4);\n }\n}" + }, + { + "index": "HumanEval-C-153", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(const char* class_name, const char** extensions, int ext_count,\n char* output) {\n int max_strength = -1000;\n const char* strongest = NULL;\n for (int i = 0; i < ext_count; i++) {\n const char* extension = extensions[i];\n int strength = 0;\n for (int j = 0; extension[j] != '\\0'; j++) {\n char chr = extension[j];\n if (chr >= 'A' && chr <= 'Z') strength++;\n if (chr >= 'a' && chr <= 'z') strength--;\n }\n if (strength > max_strength) {\n max_strength = strength;\n strongest = extension;\n }\n }\n sprintf(output, \"%s.%s\", class_name, strongest);\n}", + "test": "#include \n#include \n\nint main() {\n char result[50];\n\n const char* tmp1[] = {\"tEN\", \"niNE\", \"eIGHt8OKe\"};\n func0(\"Watashi\", tmp1, 3, result);\n assert(strcmp(result, \"Watashi.eIGHt8OKe\") == 0);\n\n const char* tmp2[] = {\"nani\", \"NazeDa\", \"YEs.WeCaNe\", \"32145tggg\"};\n func0(\"Boku123\", tmp2, 4, result);\n assert(strcmp(result, \"Boku123.YEs.WeCaNe\") == 0);\n\n const char* tmp3[] = {\"t\", \"eMptY\", \"(nothing\", \"zeR00\", \"NuLl__\", \"123NoooneB321\"};\n func0(\"__YESIMHERE\", tmp3, 6, result);\n assert(strcmp(result, \"__YESIMHERE.NuLl__\") == 0);\n\n const char* tmp4[] = {\"Ta\", \"TAR\", \"t234An\", \"cosSo\"};\n func0(\"K\", tmp4, 4, result);\n assert(strcmp(result, \"K.TAR\") == 0);\n\n const char* tmp5[] = {\"Tab\", \"123\", \"781345\", \"-_-\"};\n func0(\"__HAHA\", tmp5, 4, result);\n assert(strcmp(result, \"__HAHA.123\") == 0);\n\n const char* tmp[] = {\"HhAas\", \"okIWILL123\", \"WorkOut\", \"Fails\", \"-_-\"};\n func0(\"YameRore\", tmp, 5, result);\n assert(strcmp(result, \"YameRore.okIWILL123\") == 0);\n\n const char* tmp6[] = {\"Die\", \"NowW\", \"Wow\", \"WoW\"};\n func0(\"finNNalLLly\", tmp6, 4, result);\n assert(strcmp(result, \"finNNalLLly.WoW\") == 0);\n\n const char* tmp7[] = {\"Bb\", \"91245\"};\n func0(\"_\", tmp7, 2, result);\n assert(strcmp(result, \"_.Bb\") == 0);\n\n const char* tmp8[] = {\"671235\", \"Bb\"};\n func0(\"Sp\", tmp8, 2, result);\n assert(strcmp(result, \"Sp.671235\") == 0);\n \n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+var_38], rdi\nmov [rbp+var_40], rsi\nmov [rbp+var_44], edx\nmov [rbp+s], rcx\nmov [rbp+var_20], 0FFFFFC18h\nmov [rbp+var_10], 0\nmov [rbp+var_1C], 0\njmp loc_126F\nloc_11DF:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_40]\nadd rax, rdx\nmov rax, [rax]\nmov [rbp+var_8], rax\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp short loc_1241\nloc_120A:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_21], al\ncmp [rbp+var_21], 40h ; '@'\njle short loc_122D\ncmp [rbp+var_21], 5Ah ; 'Z'\njg short loc_122D\nadd [rbp+var_18], 1\nloc_122D:\ncmp [rbp+var_21], 60h ; '`'\njle short loc_123D\ncmp [rbp+var_21], 7Ah ; 'z'\njg short loc_123D\nsub [rbp+var_18], 1\nloc_123D:\nadd [rbp+var_14], 1\nloc_1241:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_120A\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_20]\njle short loc_126B\nmov eax, [rbp+var_18]\nmov [rbp+var_20], eax\nmov rax, [rbp+var_8]\nmov [rbp+var_10], rax\nloc_126B:\nadd [rbp+var_1C], 1\nloc_126F:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_44]\njl loc_11DF\nmov rcx, [rbp+var_10]\nmov rdx, [rbp+var_38]\nmov rax, [rbp+s]\nlea rsi, format; \"%s.%s\"\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nnop\nleave\nretn", + "ida_pseudo": "int __fastcall func0(const char *a1, __int64 a2, int a3, char *a4)\n{\n char v5; // [rsp+2Fh] [rbp-21h]\n int v6; // [rsp+30h] [rbp-20h]\n int i; // [rsp+34h] [rbp-1Ch]\n int v8; // [rsp+38h] [rbp-18h]\n int j; // [rsp+3Ch] [rbp-14h]\n const char *v10; // [rsp+40h] [rbp-10h]\n __int64 v11; // [rsp+48h] [rbp-8h]\n\n v6 = -1000;\n v10 = 0LL;\n for ( i = 0; i < a3; ++i )\n {\n v11 = *(_QWORD *)(8LL * i + a2);\n v8 = 0;\n for ( j = 0; *(_BYTE *)(j + v11); ++j )\n {\n v5 = *(_BYTE *)(j + v11);\n if ( v5 > 64 && v5 <= 90 )\n ++v8;\n if ( v5 > 96 && v5 <= 122 )\n --v8;\n }\n if ( v8 > v6 )\n {\n v6 = v8;\n v10 = *(const char **)(8LL * i + a2);\n }\n }\n return sprintf(a4, \"%s.%s\", a1, v10);\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+var_38], rdi\nmov [rbp+var_40], rsi\nmov [rbp+var_44], edx\nmov [rbp+s], rcx\nmov [rbp+var_20], 0FFFFFC18h\nmov [rbp+var_10], 0\nmov [rbp+var_1C], 0\njmp loc_126F\nloc_11DF:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_40]\nadd rax, rdx\nmov rax, [rax]\nmov [rbp+var_8], rax\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp short loc_1241\nloc_120A:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_21], al\ncmp [rbp+var_21], 40h ; '@'\njle short loc_122D\ncmp [rbp+var_21], 5Ah ; 'Z'\njg short loc_122D\nadd [rbp+var_18], 1\nloc_122D:\ncmp [rbp+var_21], 60h ; '`'\njle short loc_123D\ncmp [rbp+var_21], 7Ah ; 'z'\njg short loc_123D\nsub [rbp+var_18], 1\nloc_123D:\nadd [rbp+var_14], 1\nloc_1241:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_120A\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_20]\njle short loc_126B\nmov eax, [rbp+var_18]\nmov [rbp+var_20], eax\nmov rax, [rbp+var_8]\nmov [rbp+var_10], rax\nloc_126B:\nadd [rbp+var_1C], 1\nloc_126F:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_44]\njl loc_11DF\nmov rcx, [rbp+var_10]\nmov rdx, [rbp+var_38]\nmov rax, [rbp+s]\nlea rsi, format; \"%s.%s\"\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nnop\nleave\nretn", + "ida_strip_pseudo": "int __fastcall sub_11A9(const char *a1, __int64 a2, int a3, char *a4)\n{\n char v5; // [rsp+2Fh] [rbp-21h]\n int v6; // [rsp+30h] [rbp-20h]\n int i; // [rsp+34h] [rbp-1Ch]\n int v8; // [rsp+38h] [rbp-18h]\n int j; // [rsp+3Ch] [rbp-14h]\n const char *v10; // [rsp+40h] [rbp-10h]\n __int64 v11; // [rsp+48h] [rbp-8h]\n\n v6 = -1000;\n v10 = 0LL;\n for ( i = 0; i < a3; ++i )\n {\n v11 = *(_QWORD *)(8LL * i + a2);\n v8 = 0;\n for ( j = 0; *(_BYTE *)(j + v11); ++j )\n {\n v5 = *(_BYTE *)(j + v11);\n if ( v5 > 64 && v5 <= 90 )\n ++v8;\n if ( v5 > 96 && v5 <= 122 )\n --v8;\n }\n if ( v8 > v6 )\n {\n v6 = v8;\n v10 = *(const char **)(8LL * i + a2);\n }\n }\n return sprintf(a4, \"%s.%s\", a1, v10);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "int sub_11A9(const char *a1, long long a2, int a3, char *a4) {\n char v5;\n int v6;\n int i;\n int v8;\n int j;\n const char *v10;\n long long v11;\n v6 = -1000;\n v10 = 0LL;\n for (i = 0; i < a3; ++i) {\n v11 = *(uint64_t *)(8LL * i + a2);\n v8 = 0;\n for (j = 0; *(uint8_t *)(j + v11); ++j) {\n v5 = *(uint8_t *)(j + v11);\n if (v5 > 64 && v5 <= 90) ++v8;\n if (v5 > 96 && v5 <= 122) --v8;\n }\n if (v8 > v6) {\n v6 = v8;\n v10 = *(const char **)(8LL * i + a2);\n }\n }\n return sprintf(a4, \"%s.%s\", a1, v10);\n}", + "ida_pseudo_norm": "int func0(const char *a1, long long a2, int a3, char *a4) {\n char v5;\n int v6;\n int i;\n int v8;\n int j;\n const char *v10;\n long long v11;\n v6 = -1000;\n v10 = 0LL;\n for (i = 0; i < a3; ++i) {\n v11 = *(uint64_t *)(8LL * i + a2);\n v8 = 0;\n for (j = 0; *(uint8_t *)(j + v11); ++j) {\n v5 = *(uint8_t *)(j + v11);\n if (v5 > 64 && v5 <= 90) ++v8;\n if (v5 > 96 && v5 <= 122) --v8;\n }\n if (v8 > v6) {\n v6 = v8;\n v10 = *(const char **)(8LL * i + a2);\n }\n }\n return sprintf(a4, \"%s.%s\", a1, v10);\n}" + }, + { + "index": "HumanEval-C-153", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(const char* class_name, const char** extensions, int ext_count,\n char* output) {\n int max_strength = -1000;\n const char* strongest = NULL;\n for (int i = 0; i < ext_count; i++) {\n const char* extension = extensions[i];\n int strength = 0;\n for (int j = 0; extension[j] != '\\0'; j++) {\n char chr = extension[j];\n if (chr >= 'A' && chr <= 'Z') strength++;\n if (chr >= 'a' && chr <= 'z') strength--;\n }\n if (strength > max_strength) {\n max_strength = strength;\n strongest = extension;\n }\n }\n sprintf(output, \"%s.%s\", class_name, strongest);\n}", + "test": "#include \n#include \n\nint main() {\n char result[50];\n\n const char* tmp1[] = {\"tEN\", \"niNE\", \"eIGHt8OKe\"};\n func0(\"Watashi\", tmp1, 3, result);\n assert(strcmp(result, \"Watashi.eIGHt8OKe\") == 0);\n\n const char* tmp2[] = {\"nani\", \"NazeDa\", \"YEs.WeCaNe\", \"32145tggg\"};\n func0(\"Boku123\", tmp2, 4, result);\n assert(strcmp(result, \"Boku123.YEs.WeCaNe\") == 0);\n\n const char* tmp3[] = {\"t\", \"eMptY\", \"(nothing\", \"zeR00\", \"NuLl__\", \"123NoooneB321\"};\n func0(\"__YESIMHERE\", tmp3, 6, result);\n assert(strcmp(result, \"__YESIMHERE.NuLl__\") == 0);\n\n const char* tmp4[] = {\"Ta\", \"TAR\", \"t234An\", \"cosSo\"};\n func0(\"K\", tmp4, 4, result);\n assert(strcmp(result, \"K.TAR\") == 0);\n\n const char* tmp5[] = {\"Tab\", \"123\", \"781345\", \"-_-\"};\n func0(\"__HAHA\", tmp5, 4, result);\n assert(strcmp(result, \"__HAHA.123\") == 0);\n\n const char* tmp[] = {\"HhAas\", \"okIWILL123\", \"WorkOut\", \"Fails\", \"-_-\"};\n func0(\"YameRore\", tmp, 5, result);\n assert(strcmp(result, \"YameRore.okIWILL123\") == 0);\n\n const char* tmp6[] = {\"Die\", \"NowW\", \"Wow\", \"WoW\"};\n func0(\"finNNalLLly\", tmp6, 4, result);\n assert(strcmp(result, \"finNNalLLly.WoW\") == 0);\n\n const char* tmp7[] = {\"Bb\", \"91245\"};\n func0(\"_\", tmp7, 2, result);\n assert(strcmp(result, \"_.Bb\") == 0);\n\n const char* tmp8[] = {\"671235\", \"Bb\"};\n func0(\"Sp\", tmp8, 2, result);\n assert(strcmp(result, \"Sp.671235\") == 0);\n \n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov r8, rdi\nmov rbp, rcx\ntest edx, edx\njle short loc_1226\nmov rdi, rsi\nmovsxd rdx, edx\nlea rbx, [rsi+rdx*8]\nmov r9d, 0\nmov r11d, 0FFFFFC18h\njmp short loc_1210\nloc_11D5:\nsub eax, 61h ; 'a'\ncmp al, 1Ah\nsbb ecx, 0\nloc_11DD:\nadd rdx, 1\nmovzx eax, byte ptr [rdx-1]\ntest al, al\njz short loc_11FC\nloc_11E9:\nlea esi, [rax-41h]\ncmp sil, 19h\nja short loc_11D5\nadd ecx, 1\njmp short loc_11DD\nloc_11F7:\nmov ecx, 0\nloc_11FC:\ncmp r11d, ecx\njge short loc_1207\nmov r9, r10\nmov r11d, ecx\nloc_1207:\nadd rdi, 8\ncmp rdi, rbx\njz short loc_122C\nloc_1210:\nmov r10, [rdi]\nmovzx eax, byte ptr [r10]\ntest al, al\njz short loc_11F7\nlea rdx, [r10+1]\nmov ecx, 0\njmp short loc_11E9\nloc_1226:\nmov r9d, 0\nloc_122C:\nlea rcx, aSS; \"%s.%s\"\nmov rdx, 0FFFFFFFFFFFFFFFFh\nmov esi, 2\nmov rdi, rbp\nmov eax, 0\ncall ___sprintf_chk\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, const char **a2, int a3, __int64 a4)\n{\n const char **v6; // rdi\n const char **v7; // rbx\n const char *v8; // r9\n int v9; // r11d\n int v10; // ecx\n char *v11; // rdx\n char v12; // al\n\n if ( a3 <= 0 )\n {\n v8 = 0LL;\n }\n else\n {\n v6 = a2;\n v7 = &a2[a3];\n v8 = 0LL;\n v9 = -1000;\n do\n {\n v12 = **v6;\n if ( v12 )\n {\n v11 = (char *)(*v6 + 1);\n v10 = 0;\n do\n {\n if ( (unsigned __int8)(v12 - 65) > 0x19u )\n v10 -= (unsigned __int8)(v12 - 97) < 0x1Au;\n else\n ++v10;\n v12 = *v11++;\n }\n while ( v12 );\n }\n else\n {\n v10 = 0;\n }\n if ( v9 < v10 )\n {\n v8 = *v6;\n v9 = v10;\n }\n ++v6;\n }\n while ( v6 != v7 );\n }\n return __sprintf_chk(a4, 2LL, -1LL, \"%s.%s\", a1, v8);\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov r8, rdi\nmov rbp, rcx\ntest edx, edx\njle short loc_1226\nmov rdi, rsi\nmovsxd rdx, edx\nlea rbx, [rsi+rdx*8]\nmov r9d, 0\nmov r11d, 0FFFFFC18h\njmp short loc_1210\nloc_11D5:\nsub eax, 61h ; 'a'\ncmp al, 1Ah\nsbb ecx, 0\nloc_11DD:\nadd rdx, 1\nmovzx eax, byte ptr [rdx-1]\ntest al, al\njz short loc_11FC\nloc_11E9:\nlea esi, [rax-41h]\ncmp sil, 19h\nja short loc_11D5\nadd ecx, 1\njmp short loc_11DD\nloc_11F7:\nmov ecx, 0\nloc_11FC:\ncmp r11d, ecx\njge short loc_1207\nmov r9, r10\nmov r11d, ecx\nloc_1207:\nadd rdi, 8\ncmp rdi, rbx\njz short loc_122C\nloc_1210:\nmov r10, [rdi]\nmovzx eax, byte ptr [r10]\ntest al, al\njz short loc_11F7\nlea rdx, [r10+1]\nmov ecx, 0\njmp short loc_11E9\nloc_1226:\nmov r9d, 0\nloc_122C:\nlea rcx, aSS; \"%s.%s\"\nmov rdx, 0FFFFFFFFFFFFFFFFh\nmov esi, 2\nmov rdi, rbp\nmov eax, 0\ncall ___sprintf_chk\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(const char *a1, const char **a2, int a3, __int64 a4)\n{\n const char **v6; // rdi\n const char **v7; // rbx\n const char *v8; // r9\n int v9; // r11d\n int v10; // ecx\n char *v11; // rdx\n char v12; // al\n\n if ( a3 <= 0 )\n {\n v8 = 0LL;\n }\n else\n {\n v6 = a2;\n v7 = &a2[a3];\n v8 = 0LL;\n v9 = -1000;\n do\n {\n v12 = **v6;\n if ( v12 )\n {\n v11 = (char *)(*v6 + 1);\n v10 = 0;\n do\n {\n if ( (unsigned __int8)(v12 - 65) > 0x19u )\n v10 -= (unsigned __int8)(v12 - 97) < 0x1Au;\n else\n ++v10;\n v12 = *v11++;\n }\n while ( v12 );\n }\n else\n {\n v10 = 0;\n }\n if ( v9 < v10 )\n {\n v8 = *v6;\n v9 = v10;\n }\n ++v6;\n }\n while ( v6 != v7 );\n }\n return __sprintf_chk(a4, 2LL, -1LL, \"%s.%s\", a1, v8);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(const char *a1, const char **a2, int a3, long long a4) {\n const char **v6;\n const char **v7;\n const char *v8;\n int v9;\n int v10;\n char *v11;\n char v12;\n if (a3 <= 0) {\n v8 = 0LL;\n } else {\n v6 = a2;\n v7 = &a2[a3];\n v8 = 0LL;\n v9 = -1000;\n do {\n v12 = **v6;\n if (v12) {\n v11 = (char *)(*v6 + 1);\n v10 = 0;\n do {\n if ((unsigned char)(v12 - 65) > 25u)\n v10 -= (unsigned char)(v12 - 97) < 26u;\n else\n ++v10;\n v12 = *v11++;\n } while (v12);\n } else {\n v10 = 0;\n }\n if (v9 < v10) {\n v8 = *v6;\n v9 = v10;\n }\n ++v6;\n } while (v6 != v7);\n }\n return __sprintf_chk(a4, 2LL, -1LL, \"%s.%s\", a1, v8);\n}", + "ida_pseudo_norm": "long long func0(const char *a1, const char **a2, int a3, long long a4) {\n const char **v6;\n const char **v7;\n const char *v8;\n int v9;\n int v10;\n char *v11;\n char v12;\n if (a3 <= 0) {\n v8 = 0LL;\n } else {\n v6 = a2;\n v7 = &a2[a3];\n v8 = 0LL;\n v9 = -1000;\n do {\n v12 = **v6;\n if (v12) {\n v11 = (char *)(*v6 + 1);\n v10 = 0;\n do {\n if ((unsigned char)(v12 - 65) > 25u)\n v10 -= (unsigned char)(v12 - 97) < 26u;\n else\n ++v10;\n v12 = *v11++;\n } while (v12);\n } else {\n v10 = 0;\n }\n if (v9 < v10) {\n v8 = *v6;\n v9 = v10;\n }\n ++v6;\n } while (v6 != v7);\n }\n return __sprintf_chk(a4, 2LL, -1LL, \"%s.%s\", a1, v8);\n}" + }, + { + "index": "HumanEval-C-153", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(const char* class_name, const char** extensions, int ext_count,\n char* output) {\n int max_strength = -1000;\n const char* strongest = NULL;\n for (int i = 0; i < ext_count; i++) {\n const char* extension = extensions[i];\n int strength = 0;\n for (int j = 0; extension[j] != '\\0'; j++) {\n char chr = extension[j];\n if (chr >= 'A' && chr <= 'Z') strength++;\n if (chr >= 'a' && chr <= 'z') strength--;\n }\n if (strength > max_strength) {\n max_strength = strength;\n strongest = extension;\n }\n }\n sprintf(output, \"%s.%s\", class_name, strongest);\n}", + "test": "#include \n#include \n\nint main() {\n char result[50];\n\n const char* tmp1[] = {\"tEN\", \"niNE\", \"eIGHt8OKe\"};\n func0(\"Watashi\", tmp1, 3, result);\n assert(strcmp(result, \"Watashi.eIGHt8OKe\") == 0);\n\n const char* tmp2[] = {\"nani\", \"NazeDa\", \"YEs.WeCaNe\", \"32145tggg\"};\n func0(\"Boku123\", tmp2, 4, result);\n assert(strcmp(result, \"Boku123.YEs.WeCaNe\") == 0);\n\n const char* tmp3[] = {\"t\", \"eMptY\", \"(nothing\", \"zeR00\", \"NuLl__\", \"123NoooneB321\"};\n func0(\"__YESIMHERE\", tmp3, 6, result);\n assert(strcmp(result, \"__YESIMHERE.NuLl__\") == 0);\n\n const char* tmp4[] = {\"Ta\", \"TAR\", \"t234An\", \"cosSo\"};\n func0(\"K\", tmp4, 4, result);\n assert(strcmp(result, \"K.TAR\") == 0);\n\n const char* tmp5[] = {\"Tab\", \"123\", \"781345\", \"-_-\"};\n func0(\"__HAHA\", tmp5, 4, result);\n assert(strcmp(result, \"__HAHA.123\") == 0);\n\n const char* tmp[] = {\"HhAas\", \"okIWILL123\", \"WorkOut\", \"Fails\", \"-_-\"};\n func0(\"YameRore\", tmp, 5, result);\n assert(strcmp(result, \"YameRore.okIWILL123\") == 0);\n\n const char* tmp6[] = {\"Die\", \"NowW\", \"Wow\", \"WoW\"};\n func0(\"finNNalLLly\", tmp6, 4, result);\n assert(strcmp(result, \"finNNalLLly.WoW\") == 0);\n\n const char* tmp7[] = {\"Bb\", \"91245\"};\n func0(\"_\", tmp7, 2, result);\n assert(strcmp(result, \"_.Bb\") == 0);\n\n const char* tmp8[] = {\"671235\", \"Bb\"};\n func0(\"Sp\", tmp8, 2, result);\n assert(strcmp(result, \"Sp.671235\") == 0);\n \n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov r8, rdi\nmov r11, rcx\npush rbx\ntest edx, edx\njle loc_1854\nmovsxd rdx, edx\nxor r9d, r9d\nmov ebx, 0FFFFFC18h\nlea rbp, [rsi+rdx*8]\nnop dword ptr [rax+rax+00h]\nloc_17D8:\nmov r10, [rsi]\nmovzx eax, byte ptr [r10]\ntest al, al\njz short loc_1850\nlea rdx, [r10+1]\nxor ecx, ecx\njmp short loc_17FE\nloc_17F0:\nmovzx eax, byte ptr [rdx]\nadd rdx, 1\nadd ecx, 1\ntest al, al\njz short loc_181A\nloc_17FE:\nlea edi, [rax-41h]\ncmp dil, 19h\njbe short loc_17F0\nsub eax, 61h ; 'a'\ncmp al, 1Ah\nsbb ecx, 0\nmovzx eax, byte ptr [rdx]\nadd rdx, 1\ntest al, al\njnz short loc_17FE\nloc_181A:\ncmp ebx, ecx\njge short loc_1823\nmov r9, r10\nmov ebx, ecx\nloc_1823:\nadd rsi, 8\ncmp rbp, rsi\njnz short loc_17D8\nloc_182C:\npop rbx\nlea rcx, aSS; \"%s.%s\"\nmov rdx, 0FFFFFFFFFFFFFFFFh\npop rbp\nmov esi, 2\nmov rdi, r11\nxor eax, eax\njmp ___sprintf_chk\nloc_1850:\nxor ecx, ecx\njmp short loc_181A\nloc_1854:\nxor r9d, r9d\njmp short loc_182C", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, const char **a2, int a3, __int64 a4)\n{\n const char *v6; // r9\n int v7; // ebx\n const char **v8; // rbp\n char v9; // al\n char *v10; // rdx\n int v11; // ecx\n\n if ( a3 <= 0 )\n {\n v6 = 0LL;\n }\n else\n {\n v6 = 0LL;\n v7 = -1000;\n v8 = &a2[a3];\n do\n {\n v9 = **a2;\n if ( v9 )\n {\n v10 = (char *)(*a2 + 1);\n v11 = 0;\n do\n {\n while ( (unsigned __int8)(v9 - 65) <= 0x19u )\n {\n v9 = *v10++;\n ++v11;\n if ( !v9 )\n goto LABEL_8;\n }\n v11 -= (unsigned __int8)(v9 - 97) < 0x1Au;\n v9 = *v10++;\n }\n while ( v9 );\n }\n else\n {\n v11 = 0;\n }\nLABEL_8:\n if ( v7 < v11 )\n {\n v6 = *a2;\n v7 = v11;\n }\n ++a2;\n }\n while ( v8 != a2 );\n }\n return _sprintf_chk(a4, 2LL, -1LL, \"%s.%s\", a1, v6);\n}", + "ida_strip_asm": "sub_17B0:\nendbr64\npush rbp\nmov r8, rdi\nmov r11, rcx\npush rbx\ntest edx, edx\njle loc_1854\nmovsxd rdx, edx\nxor r9d, r9d\nmov ebx, 0FFFFFC18h\nlea rbp, [rsi+rdx*8]\nnop dword ptr [rax+rax+00h]\nloc_17D8:\nmov r10, [rsi]\nmovzx eax, byte ptr [r10]\ntest al, al\njz short loc_1850\nlea rdx, [r10+1]\nxor ecx, ecx\njmp short loc_17FE\nloc_17F0:\nmovzx eax, byte ptr [rdx]\nadd rdx, 1\nadd ecx, 1\ntest al, al\njz short loc_181A\nloc_17FE:\nlea edi, [rax-41h]\ncmp dil, 19h\njbe short loc_17F0\nsub eax, 61h ; 'a'\ncmp al, 1Ah\nsbb ecx, 0\nmovzx eax, byte ptr [rdx]\nadd rdx, 1\ntest al, al\njnz short loc_17FE\nloc_181A:\ncmp ebx, ecx\njge short loc_1823\nmov r9, r10\nmov ebx, ecx\nloc_1823:\nadd rsi, 8\ncmp rbp, rsi\njnz short loc_17D8\nloc_182C:\npop rbx\nlea rcx, aSS; \"%s.%s\"\nmov rdx, 0FFFFFFFFFFFFFFFFh\npop rbp\nmov esi, 2\nmov rdi, r11\nxor eax, eax\njmp ___sprintf_chk\nloc_1850:\nxor ecx, ecx\njmp short loc_181A\nloc_1854:\nxor r9d, r9d\njmp short loc_182C", + "ida_strip_pseudo": "__int64 __fastcall sub_17B0(const char *a1, const char **a2, int a3, __int64 a4)\n{\n const char *v6; // r9\n int v7; // ebx\n const char **v8; // rbp\n char v9; // al\n char *v10; // rdx\n int v11; // ecx\n\n if ( a3 <= 0 )\n {\n v6 = 0LL;\n }\n else\n {\n v6 = 0LL;\n v7 = -1000;\n v8 = &a2[a3];\n do\n {\n v9 = **a2;\n if ( v9 )\n {\n v10 = (char *)(*a2 + 1);\n v11 = 0;\n do\n {\n while ( (unsigned __int8)(v9 - 65) <= 0x19u )\n {\n v9 = *v10++;\n ++v11;\n if ( !v9 )\n goto LABEL_8;\n }\n v11 -= (unsigned __int8)(v9 - 97) < 0x1Au;\n v9 = *v10++;\n }\n while ( v9 );\n }\n else\n {\n v11 = 0;\n }\nLABEL_8:\n if ( v7 < v11 )\n {\n v6 = *a2;\n v7 = v11;\n }\n ++a2;\n }\n while ( v8 != a2 );\n }\n return _sprintf_chk(a4, 2LL, -1LL, \"%s.%s\", a1, v6);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_17B0(const char *a1, const char **a2, int a3, long long a4) {\n const char *v6;\n int v7;\n const char **v8;\n char v9;\n char *v10;\n int v11;\n if (a3 <= 0) {\n v6 = 0LL;\n } else {\n v6 = 0LL;\n v7 = -1000;\n v8 = &a2[a3];\n do {\n v9 = **a2;\n if (v9) {\n v10 = (char *)(*a2 + 1);\n v11 = 0;\n do {\n while ((unsigned char)(v9 - 65) <= 25u) {\n v9 = *v10++;\n ++v11;\n if (!v9) goto LABEL_8;\n }\n v11 -= (unsigned char)(v9 - 97) < 26u;\n v9 = *v10++;\n } while (v9);\n } else {\n v11 = 0;\n }\n LABEL_8:\n if (v7 < v11) {\n v6 = *a2;\n v7 = v11;\n }\n ++a2;\n } while (v8 != a2);\n }\n return _sprintf_chk(a4, 2LL, -1LL, \"%s.%s\", a1, v6);\n}", + "ida_pseudo_norm": "long long func0(const char *a1, const char **a2, int a3, long long a4) {\n const char *v6;\n int v7;\n const char **v8;\n char v9;\n char *v10;\n int v11;\n if (a3 <= 0) {\n v6 = 0LL;\n } else {\n v6 = 0LL;\n v7 = -1000;\n v8 = &a2[a3];\n do {\n v9 = **a2;\n if (v9) {\n v10 = (char *)(*a2 + 1);\n v11 = 0;\n do {\n while ((unsigned char)(v9 - 65) <= 25u) {\n v9 = *v10++;\n ++v11;\n if (!v9) goto LABEL_8;\n }\n v11 -= (unsigned char)(v9 - 97) < 26u;\n v9 = *v10++;\n } while (v9);\n } else {\n v11 = 0;\n }\n LABEL_8:\n if (v7 < v11) {\n v6 = *a2;\n v7 = v11;\n }\n ++a2;\n } while (v8 != a2);\n }\n return _sprintf_chk(a4, 2LL, -1LL, \"%s.%s\", a1, v6);\n}" + }, + { + "index": "HumanEval-C-153", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(const char* class_name, const char** extensions, int ext_count,\n char* output) {\n int max_strength = -1000;\n const char* strongest = NULL;\n for (int i = 0; i < ext_count; i++) {\n const char* extension = extensions[i];\n int strength = 0;\n for (int j = 0; extension[j] != '\\0'; j++) {\n char chr = extension[j];\n if (chr >= 'A' && chr <= 'Z') strength++;\n if (chr >= 'a' && chr <= 'z') strength--;\n }\n if (strength > max_strength) {\n max_strength = strength;\n strongest = extension;\n }\n }\n sprintf(output, \"%s.%s\", class_name, strongest);\n}", + "test": "#include \n#include \n\nint main() {\n char result[50];\n\n const char* tmp1[] = {\"tEN\", \"niNE\", \"eIGHt8OKe\"};\n func0(\"Watashi\", tmp1, 3, result);\n assert(strcmp(result, \"Watashi.eIGHt8OKe\") == 0);\n\n const char* tmp2[] = {\"nani\", \"NazeDa\", \"YEs.WeCaNe\", \"32145tggg\"};\n func0(\"Boku123\", tmp2, 4, result);\n assert(strcmp(result, \"Boku123.YEs.WeCaNe\") == 0);\n\n const char* tmp3[] = {\"t\", \"eMptY\", \"(nothing\", \"zeR00\", \"NuLl__\", \"123NoooneB321\"};\n func0(\"__YESIMHERE\", tmp3, 6, result);\n assert(strcmp(result, \"__YESIMHERE.NuLl__\") == 0);\n\n const char* tmp4[] = {\"Ta\", \"TAR\", \"t234An\", \"cosSo\"};\n func0(\"K\", tmp4, 4, result);\n assert(strcmp(result, \"K.TAR\") == 0);\n\n const char* tmp5[] = {\"Tab\", \"123\", \"781345\", \"-_-\"};\n func0(\"__HAHA\", tmp5, 4, result);\n assert(strcmp(result, \"__HAHA.123\") == 0);\n\n const char* tmp[] = {\"HhAas\", \"okIWILL123\", \"WorkOut\", \"Fails\", \"-_-\"};\n func0(\"YameRore\", tmp, 5, result);\n assert(strcmp(result, \"YameRore.okIWILL123\") == 0);\n\n const char* tmp6[] = {\"Die\", \"NowW\", \"Wow\", \"WoW\"};\n func0(\"finNNalLLly\", tmp6, 4, result);\n assert(strcmp(result, \"finNNalLLly.WoW\") == 0);\n\n const char* tmp7[] = {\"Bb\", \"91245\"};\n func0(\"_\", tmp7, 2, result);\n assert(strcmp(result, \"_.Bb\") == 0);\n\n const char* tmp8[] = {\"671235\", \"Bb\"};\n func0(\"Sp\", tmp8, 2, result);\n assert(strcmp(result, \"Sp.671235\") == 0);\n \n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov r8, rdi\nmov r11, rcx\npush rbx\ntest edx, edx\njle loc_1854\nmovsxd rdx, edx\nxor r9d, r9d\nmov ebx, 0FFFFFC18h\nlea rbp, [rsi+rdx*8]\nnop dword ptr [rax+rax+00h]\nloc_17D8:\nmov r10, [rsi]\nmovzx eax, byte ptr [r10]\ntest al, al\njz short loc_1850\nlea rdx, [r10+1]\nxor ecx, ecx\njmp short loc_17FE\nloc_17F0:\nmovzx eax, byte ptr [rdx]\nadd rdx, 1\nadd ecx, 1\ntest al, al\njz short loc_181A\nloc_17FE:\nlea edi, [rax-41h]\ncmp dil, 19h\njbe short loc_17F0\nsub eax, 61h ; 'a'\ncmp al, 1Ah\nsbb ecx, 0\nmovzx eax, byte ptr [rdx]\nadd rdx, 1\ntest al, al\njnz short loc_17FE\nloc_181A:\ncmp ebx, ecx\njge short loc_1823\nmov r9, r10\nmov ebx, ecx\nloc_1823:\nadd rsi, 8\ncmp rbp, rsi\njnz short loc_17D8\nloc_182C:\npop rbx\nlea rcx, aSS; \"%s.%s\"\nmov rdx, 0FFFFFFFFFFFFFFFFh\npop rbp\nmov esi, 2\nmov rdi, r11\nxor eax, eax\njmp ___sprintf_chk\nloc_1850:\nxor ecx, ecx\njmp short loc_181A\nloc_1854:\nxor r9d, r9d\njmp short loc_182C", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, const char **a2, int a3, __int64 a4)\n{\n const char *v6; // r9\n int v7; // ebx\n const char **v8; // rbp\n char v9; // al\n char *v10; // rdx\n int v11; // ecx\n\n if ( a3 <= 0 )\n {\n v6 = 0LL;\n }\n else\n {\n v6 = 0LL;\n v7 = -1000;\n v8 = &a2[a3];\n do\n {\n v9 = **a2;\n if ( v9 )\n {\n v10 = (char *)(*a2 + 1);\n v11 = 0;\n do\n {\n while ( (unsigned __int8)(v9 - 65) <= 0x19u )\n {\n v9 = *v10++;\n ++v11;\n if ( !v9 )\n goto LABEL_8;\n }\n v11 -= (unsigned __int8)(v9 - 97) < 0x1Au;\n v9 = *v10++;\n }\n while ( v9 );\n }\n else\n {\n v11 = 0;\n }\nLABEL_8:\n if ( v7 < v11 )\n {\n v6 = *a2;\n v7 = v11;\n }\n ++a2;\n }\n while ( v8 != a2 );\n }\n return _sprintf_chk(a4, 2LL, -1LL, \"%s.%s\", a1, v6);\n}", + "ida_strip_asm": "sub_17B0:\nendbr64\npush rbp\nmov r8, rdi\nmov r11, rcx\npush rbx\ntest edx, edx\njle loc_1854\nmovsxd rdx, edx\nxor r9d, r9d\nmov ebx, 0FFFFFC18h\nlea rbp, [rsi+rdx*8]\nnop dword ptr [rax+rax+00h]\nloc_17D8:\nmov r10, [rsi]\nmovzx eax, byte ptr [r10]\ntest al, al\njz short loc_1850\nlea rdx, [r10+1]\nxor ecx, ecx\njmp short loc_17FE\nloc_17F0:\nmovzx eax, byte ptr [rdx]\nadd rdx, 1\nadd ecx, 1\ntest al, al\njz short loc_181A\nloc_17FE:\nlea edi, [rax-41h]\ncmp dil, 19h\njbe short loc_17F0\nsub eax, 61h ; 'a'\ncmp al, 1Ah\nsbb ecx, 0\nmovzx eax, byte ptr [rdx]\nadd rdx, 1\ntest al, al\njnz short loc_17FE\nloc_181A:\ncmp ebx, ecx\njge short loc_1823\nmov r9, r10\nmov ebx, ecx\nloc_1823:\nadd rsi, 8\ncmp rbp, rsi\njnz short loc_17D8\nloc_182C:\npop rbx\nlea rcx, aSS; \"%s.%s\"\nmov rdx, 0FFFFFFFFFFFFFFFFh\npop rbp\nmov esi, 2\nmov rdi, r11\nxor eax, eax\njmp ___sprintf_chk\nloc_1850:\nxor ecx, ecx\njmp short loc_181A\nloc_1854:\nxor r9d, r9d\njmp short loc_182C", + "ida_strip_pseudo": "__int64 __fastcall sub_17B0(const char *a1, const char **a2, int a3, __int64 a4)\n{\n const char *v6; // r9\n int v7; // ebx\n const char **v8; // rbp\n char v9; // al\n char *v10; // rdx\n int v11; // ecx\n\n if ( a3 <= 0 )\n {\n v6 = 0LL;\n }\n else\n {\n v6 = 0LL;\n v7 = -1000;\n v8 = &a2[a3];\n do\n {\n v9 = **a2;\n if ( v9 )\n {\n v10 = (char *)(*a2 + 1);\n v11 = 0;\n do\n {\n while ( (unsigned __int8)(v9 - 65) <= 0x19u )\n {\n v9 = *v10++;\n ++v11;\n if ( !v9 )\n goto LABEL_8;\n }\n v11 -= (unsigned __int8)(v9 - 97) < 0x1Au;\n v9 = *v10++;\n }\n while ( v9 );\n }\n else\n {\n v11 = 0;\n }\nLABEL_8:\n if ( v7 < v11 )\n {\n v6 = *a2;\n v7 = v11;\n }\n ++a2;\n }\n while ( v8 != a2 );\n }\n return _sprintf_chk(a4, 2LL, -1LL, \"%s.%s\", a1, v6);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_17B0(const char *a1, const char **a2, int a3, long long a4) {\n const char *v6;\n int v7;\n const char **v8;\n char v9;\n char *v10;\n int v11;\n if (a3 <= 0) {\n v6 = 0LL;\n } else {\n v6 = 0LL;\n v7 = -1000;\n v8 = &a2[a3];\n do {\n v9 = **a2;\n if (v9) {\n v10 = (char *)(*a2 + 1);\n v11 = 0;\n do {\n while ((unsigned char)(v9 - 65) <= 25u) {\n v9 = *v10++;\n ++v11;\n if (!v9) goto LABEL_8;\n }\n v11 -= (unsigned char)(v9 - 97) < 26u;\n v9 = *v10++;\n } while (v9);\n } else {\n v11 = 0;\n }\n LABEL_8:\n if (v7 < v11) {\n v6 = *a2;\n v7 = v11;\n }\n ++a2;\n } while (v8 != a2);\n }\n return _sprintf_chk(a4, 2LL, -1LL, \"%s.%s\", a1, v6);\n}", + "ida_pseudo_norm": "long long func0(const char *a1, const char **a2, int a3, long long a4) {\n const char *v6;\n int v7;\n const char **v8;\n char v9;\n char *v10;\n int v11;\n if (a3 <= 0) {\n v6 = 0LL;\n } else {\n v6 = 0LL;\n v7 = -1000;\n v8 = &a2[a3];\n do {\n v9 = **a2;\n if (v9) {\n v10 = (char *)(*a2 + 1);\n v11 = 0;\n do {\n while ((unsigned char)(v9 - 65) <= 25u) {\n v9 = *v10++;\n ++v11;\n if (!v9) goto LABEL_8;\n }\n v11 -= (unsigned char)(v9 - 97) < 26u;\n v9 = *v10++;\n } while (v9);\n } else {\n v11 = 0;\n }\n LABEL_8:\n if (v7 < v11) {\n v6 = *a2;\n v7 = v11;\n }\n ++a2;\n } while (v8 != a2);\n }\n return _sprintf_chk(a4, 2LL, -1LL, \"%s.%s\", a1, v6);\n}" + }, + { + "index": "HumanEval-C-154", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n#include \n", + "func": "bool func0(const char *a, const char *b) {\n int len_a = strlen(a);\n int len_b = strlen(b);\n char *temp = (char *)malloc(2 * len_b + 1);\n for (int i = 0; i < len_b; i++) {\n strncpy(temp, b + i, len_b - i);\n strncpy(temp + len_b - i, b, i);\n temp[len_b] = '\\0';\n if (strstr(a, temp)) {\n free(temp);\n return true;\n }\n }\n free(temp);\n return false;\n}", + "test": "#include \n#include \n\nint main() {\n assert(func0(\"xyzw\", \"xyw\") == false);\n assert(func0(\"yello\", \"ell\") == true);\n assert(func0(\"whattup\", \"ptut\") == false);\n assert(func0(\"efef\", \"fee\") == true);\n assert(func0(\"abab\", \"aabb\") == false);\n assert(func0(\"winemtt\", \"tinem\") == true);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov [rbp+src], rsi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_10], eax\nmov rax, [rbp+src]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_C], eax\nmov eax, [rbp+var_C]\nadd eax, eax\nadd eax, 1\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+dest], rax\nmov [rbp+var_14], 0\njmp loc_12CB\nloc_123D:\nmov eax, [rbp+var_C]\nsub eax, [rbp+var_14]\nmovsxd rdx, eax; n\nmov eax, [rbp+var_14]\nmovsxd rcx, eax\nmov rax, [rbp+src]\nadd rcx, rax\nmov rax, [rbp+dest]\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strncpy\nmov eax, [rbp+var_14]\nmovsxd rdx, eax; n\nmov eax, [rbp+var_C]\nmovsxd rcx, eax\nmov eax, [rbp+var_14]\ncdqe\nsub rcx, rax\nmov rax, [rbp+dest]\nadd rcx, rax\nmov rax, [rbp+src]\nmov rsi, rax; src\nmov rdi, rcx; dest\ncall _strncpy\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+dest]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rdx, [rbp+dest]\nmov rax, [rbp+s]\nmov rsi, rdx; needle\nmov rdi, rax; haystack\ncall _strstr\ntest rax, rax\njz short loc_12C7\nmov rax, [rbp+dest]\nmov rdi, rax; ptr\ncall _free\nmov eax, 1\njmp short locret_12E8\nloc_12C7:\nadd [rbp+var_14], 1\nloc_12CB:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_C]\njl loc_123D\nmov rax, [rbp+dest]\nmov rdi, rax; ptr\ncall _free\nmov eax, 0\nlocret_12E8:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, const char *a2)\n{\n int i; // [rsp+1Ch] [rbp-14h]\n int v4; // [rsp+24h] [rbp-Ch]\n char *dest; // [rsp+28h] [rbp-8h]\n\n strlen(a1);\n v4 = strlen(a2);\n dest = (char *)malloc(2 * v4 + 1);\n for ( i = 0; i < v4; ++i )\n {\n strncpy(dest, &a2[i], v4 - i);\n strncpy(&dest[v4 - (__int64)i], a2, i);\n dest[v4] = 0;\n if ( strstr(a1, dest) )\n {\n free(dest);\n return 1LL;\n }\n }\n free(dest);\n return 0LL;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov [rbp+src], rsi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_10], eax\nmov rax, [rbp+src]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_C], eax\nmov eax, [rbp+var_C]\nadd eax, eax\nadd eax, 1\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+dest], rax\nmov [rbp+var_14], 0\njmp loc_12CB\nloc_123D:\nmov eax, [rbp+var_C]\nsub eax, [rbp+var_14]\nmovsxd rdx, eax; n\nmov eax, [rbp+var_14]\nmovsxd rcx, eax\nmov rax, [rbp+src]\nadd rcx, rax\nmov rax, [rbp+dest]\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strncpy\nmov eax, [rbp+var_14]\nmovsxd rdx, eax; n\nmov eax, [rbp+var_C]\nmovsxd rcx, eax\nmov eax, [rbp+var_14]\ncdqe\nsub rcx, rax\nmov rax, [rbp+dest]\nadd rcx, rax\nmov rax, [rbp+src]\nmov rsi, rax; src\nmov rdi, rcx; dest\ncall _strncpy\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+dest]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rdx, [rbp+dest]\nmov rax, [rbp+s]\nmov rsi, rdx; needle\nmov rdi, rax; haystack\ncall _strstr\ntest rax, rax\njz short loc_12C7\nmov rax, [rbp+dest]\nmov rdi, rax; ptr\ncall _free\nmov eax, 1\njmp short locret_12E8\nloc_12C7:\nadd [rbp+var_14], 1\nloc_12CB:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_C]\njl loc_123D\nmov rax, [rbp+dest]\nmov rdi, rax; ptr\ncall _free\nmov eax, 0\nlocret_12E8:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11E9(const char *a1, const char *a2)\n{\n int i; // [rsp+1Ch] [rbp-14h]\n int v4; // [rsp+24h] [rbp-Ch]\n char *dest; // [rsp+28h] [rbp-8h]\n\n strlen(a1);\n v4 = strlen(a2);\n dest = (char *)malloc(2 * v4 + 1);\n for ( i = 0; i < v4; ++i )\n {\n strncpy(dest, &a2[i], v4 - i);\n strncpy(&dest[v4 - (__int64)i], a2, i);\n dest[v4] = 0;\n if ( strstr(a1, dest) )\n {\n free(dest);\n return 1LL;\n }\n }\n free(dest);\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11E9(const char *a1, const char *a2) {\n int i;\n int v4;\n char *dest;\n strlen(a1);\n v4 = strlen(a2);\n dest = (char *)malloc(2 * v4 + 1);\n for (i = 0; i < v4; ++i) {\n strncpy(dest, &a2[i], v4 - i);\n strncpy(&dest[v4 - (long long)i], a2, i);\n dest[v4] = 0;\n if (strstr(a1, dest)) {\n free(dest);\n return 1LL;\n }\n }\n free(dest);\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, const char *a2) {\n int i;\n int v4;\n char *dest;\n strlen(a1);\n v4 = strlen(a2);\n dest = (char *)malloc(2 * v4 + 1);\n for (i = 0; i < v4; ++i) {\n strncpy(dest, &a2[i], v4 - i);\n strncpy(&dest[v4 - (long long)i], a2, i);\n dest[v4] = 0;\n if (strstr(a1, dest)) {\n free(dest);\n return 1LL;\n }\n }\n free(dest);\n return 0LL;\n}" + }, + { + "index": "HumanEval-C-154", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n#include \n", + "func": "bool func0(const char *a, const char *b) {\n int len_a = strlen(a);\n int len_b = strlen(b);\n char *temp = (char *)malloc(2 * len_b + 1);\n for (int i = 0; i < len_b; i++) {\n strncpy(temp, b + i, len_b - i);\n strncpy(temp + len_b - i, b, i);\n temp[len_b] = '\\0';\n if (strstr(a, temp)) {\n free(temp);\n return true;\n }\n }\n free(temp);\n return false;\n}", + "test": "#include \n#include \n\nint main() {\n assert(func0(\"xyzw\", \"xyw\") == false);\n assert(func0(\"yello\", \"ell\") == true);\n assert(func0(\"whattup\", \"ptut\") == false);\n assert(func0(\"efef\", \"fee\") == true);\n assert(func0(\"abab\", \"aabb\") == false);\n assert(func0(\"winemtt\", \"tinem\") == true);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+haystack], rdi\nmov r14, rsi\nmov rdi, rsi; s\ncall _strlen\nmov rbx, rax\nlea r13d, [rax+rax+1]\nmovsxd r13, r13d\nmov rdi, r13; size\ncall _malloc\nmov r12, rax\ntest ebx, ebx\njle short loc_1292\nmovsxd r15, ebx\nlea eax, [rbx-1]\nmov [rsp+48h+var_40], rax\nmov rbx, r15\nmov ebp, 0\njmp short loc_123C\nloc_1239:\nmov rbp, rax\nloc_123C:\nlea rsi, [r14+rbp]\nmov rcx, r13\nmov rdx, rbx\nmov rdi, r12\ncall ___strncpy_chk\ncmp r13, rbx\nmov rcx, rbx\ncmovnb rcx, r13\nsub rcx, rbx\nlea rdi, [r12+rbx]\nmov rdx, rbp\nmov rsi, r14\ncall ___strncpy_chk\nmov byte ptr [r12+r15], 0\nmov rsi, r12; needle\nmov rdi, [rsp+48h+haystack]; haystack\ncall _strstr\ntest rax, rax\njnz short loc_12AE\nlea rax, [rbp+1]\nsub rbx, 1\nmov rdx, [rsp+48h+var_40]\ncmp rbp, rdx\njnz short loc_1239\nloc_1292:\nmov rdi, r12; ptr\ncall _free\nmov eax, 0\nloc_129F:\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_12AE:\nmov rdi, r12; ptr\ncall _free\nmov eax, 1\njmp short loc_129F", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, const char *a2)\n{\n size_t v2; // rbx\n size_t v3; // r13\n char *v4; // r12\n __int64 v5; // r15\n __int64 i; // rbp\n size_t v7; // rcx\n __int64 v9; // [rsp+8h] [rbp-40h]\n\n LODWORD(v2) = strlen(a2);\n v3 = 2 * (int)v2 + 1;\n v4 = (char *)malloc(v3);\n if ( (int)v2 <= 0 )\n {\nLABEL_8:\n free(v4);\n return 0LL;\n }\n else\n {\n v5 = (int)v2;\n v9 = (unsigned int)(v2 - 1);\n v2 = (int)v2;\n for ( i = 0LL; ; ++i )\n {\n __strncpy_chk(v4, &a2[i], v2, v3);\n v7 = v2;\n if ( v3 >= v2 )\n v7 = v3;\n __strncpy_chk(&v4[v2], a2, i, v7 - v2);\n v4[v5] = 0;\n if ( strstr(a1, v4) )\n break;\n --v2;\n if ( i == v9 )\n goto LABEL_8;\n }\n free(v4);\n return 1LL;\n }\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+haystack], rdi\nmov r14, rsi\nmov rdi, rsi; s\ncall _strlen\nmov rbx, rax\nlea r13d, [rax+rax+1]\nmovsxd r13, r13d\nmov rdi, r13; size\ncall _malloc\nmov r12, rax\ntest ebx, ebx\njle short loc_1292\nmovsxd r15, ebx\nlea eax, [rbx-1]\nmov [rsp+48h+var_40], rax\nmov rbx, r15\nmov ebp, 0\njmp short loc_123C\nloc_1239:\nmov rbp, rax\nloc_123C:\nlea rsi, [r14+rbp]\nmov rcx, r13\nmov rdx, rbx\nmov rdi, r12\ncall ___strncpy_chk\ncmp r13, rbx\nmov rcx, rbx\ncmovnb rcx, r13\nsub rcx, rbx\nlea rdi, [r12+rbx]\nmov rdx, rbp\nmov rsi, r14\ncall ___strncpy_chk\nmov byte ptr [r12+r15], 0\nmov rsi, r12; needle\nmov rdi, [rsp+48h+haystack]; haystack\ncall _strstr\ntest rax, rax\njnz short loc_12AE\nlea rax, [rbp+1]\nsub rbx, 1\nmov rdx, [rsp+48h+var_40]\ncmp rbp, rdx\njnz short loc_1239\nloc_1292:\nmov rdi, r12; ptr\ncall _free\nmov eax, 0\nloc_129F:\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_12AE:\nmov rdi, r12; ptr\ncall _free\nmov eax, 1\njmp short loc_129F", + "ida_strip_pseudo": "__int64 __fastcall sub_11E9(const char *a1, const char *a2)\n{\n size_t v2; // rbx\n size_t v3; // r13\n char *v4; // r12\n __int64 v5; // r15\n __int64 i; // rbp\n size_t v7; // rcx\n __int64 v9; // [rsp+8h] [rbp-40h]\n\n LODWORD(v2) = strlen(a2);\n v3 = 2 * (int)v2 + 1;\n v4 = (char *)malloc(v3);\n if ( (int)v2 <= 0 )\n {\nLABEL_8:\n free(v4);\n return 0LL;\n }\n else\n {\n v5 = (int)v2;\n v9 = (unsigned int)(v2 - 1);\n v2 = (int)v2;\n for ( i = 0LL; ; ++i )\n {\n __strncpy_chk(v4, &a2[i], v2, v3);\n v7 = v2;\n if ( v3 >= v2 )\n v7 = v3;\n __strncpy_chk(&v4[v2], a2, i, v7 - v2);\n v4[v5] = 0;\n if ( strstr(a1, v4) )\n break;\n --v2;\n if ( i == v9 )\n goto LABEL_8;\n }\n free(v4);\n return 1LL;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11E9(const char *a1, const char *a2) {\n unsigned int v2;\n unsigned int v3;\n char *v4;\n long long v5;\n long long i;\n unsigned int v7;\n long long v9;\n LODWORD(v2) = strlen(a2);\n v3 = 2 * (int)v2 + 1;\n v4 = (char *)malloc(v3);\n if ((int)v2 <= 0) {\n LABEL_8:\n free(v4);\n return 0LL;\n } else {\n v5 = (int)v2;\n v9 = (unsigned int)(v2 - 1);\n v2 = (int)v2;\n for (i = 0LL;; ++i) {\n __strncpy_chk(v4, &a2[i], v2, v3);\n v7 = v2;\n if (v3 >= v2) v7 = v3;\n __strncpy_chk(&v4[v2], a2, i, v7 - v2);\n v4[v5] = 0;\n if (strstr(a1, v4)) break;\n --v2;\n if (i == v9) goto LABEL_8;\n }\n free(v4);\n return 1LL;\n }\n}", + "ida_pseudo_norm": "long long func0(const char *a1, const char *a2) {\n unsigned int v2;\n unsigned int v3;\n char *v4;\n long long v5;\n long long i;\n unsigned int v7;\n long long v9;\n LODWORD(v2) = strlen(a2);\n v3 = 2 * (int)v2 + 1;\n v4 = (char *)malloc(v3);\n if ((int)v2 <= 0) {\n LABEL_8:\n free(v4);\n return 0LL;\n } else {\n v5 = (int)v2;\n v9 = (unsigned int)(v2 - 1);\n v2 = (int)v2;\n for (i = 0LL;; ++i) {\n __strncpy_chk(v4, &a2[i], v2, v3);\n v7 = v2;\n if (v3 >= v2) v7 = v3;\n __strncpy_chk(&v4[v2], a2, i, v7 - v2);\n v4[v5] = 0;\n if (strstr(a1, v4)) break;\n --v2;\n if (i == v9) goto LABEL_8;\n }\n free(v4);\n return 1LL;\n }\n}" + }, + { + "index": "HumanEval-C-154", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n#include \n", + "func": "bool func0(const char *a, const char *b) {\n int len_a = strlen(a);\n int len_b = strlen(b);\n char *temp = (char *)malloc(2 * len_b + 1);\n for (int i = 0; i < len_b; i++) {\n strncpy(temp, b + i, len_b - i);\n strncpy(temp + len_b - i, b, i);\n temp[len_b] = '\\0';\n if (strstr(a, temp)) {\n free(temp);\n return true;\n }\n }\n free(temp);\n return false;\n}", + "test": "#include \n#include \n\nint main() {\n assert(func0(\"xyzw\", \"xyw\") == false);\n assert(func0(\"yello\", \"ell\") == true);\n assert(func0(\"whattup\", \"ptut\") == false);\n assert(func0(\"efef\", \"fee\") == true);\n assert(func0(\"abab\", \"aabb\") == false);\n assert(func0(\"winemtt\", \"tinem\") == true);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12, rsi\npush rbp\npush rbx\nsub rsp, 28h\nmov [rsp+58h+haystack], rdi\nmov rdi, rsi; s\ncall _strlen\nlea ebx, [rax+rax+1]\nmov r15, rax\nmovsxd rbx, ebx\nmov rdi, rbx; size\ncall _malloc\nmov rbp, rax\ntest r15d, r15d\njle loc_1440\nmovsxd r14, r15d\nlea r13, [rax+r14]\nlea eax, [r15-1]\nxor r15d, r15d\nmov [rsp+58h+var_48], r13\nmov [rsp+58h+var_40], rax\njmp short loc_13DA\nloc_13C0:\nmov rdx, [rsp+58h+var_40]\nlea rax, [r15+1]\nsub r14, 1\ncmp r15, rdx\njz short loc_1440\nmov r15, rax\nlea r13, [rbp+r14+0]\nloc_13DA:\nlea rsi, [r12+r15]\nmov rcx, rbx\nmov rdx, r14\nmov rdi, rbp\ncall ___strncpy_chk\ncmp rbx, r14\nmov rcx, r14\nmov rsi, r12\ncmovnb rcx, rbx\nmov rdi, r13\nmov rdx, r15\nsub rcx, r14\ncall ___strncpy_chk\nmov rax, [rsp+58h+var_48]\nmov rdi, [rsp+58h+haystack]; haystack\nmov rsi, rbp; needle\nmov byte ptr [rax], 0\ncall _strstr\ntest rax, rax\njz short loc_13C0\nmov rdi, rbp; ptr\ncall _free\nadd rsp, 28h\nmov eax, 1\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1440:\nmov rdi, rbp; ptr\ncall _free\nadd rsp, 28h\nxor eax, eax\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, const char *a2)\n{\n int v2; // r15d\n size_t v3; // rbx\n char *v4; // rax\n char *v5; // rbp\n size_t v6; // r14\n char *v7; // r13\n __int64 v8; // rax\n __int64 v9; // r15\n size_t v10; // rcx\n char *v12; // [rsp+10h] [rbp-48h]\n __int64 v13; // [rsp+18h] [rbp-40h]\n\n v2 = strlen(a2);\n v3 = 2 * v2 + 1;\n v4 = (char *)malloc(v3);\n v5 = v4;\n if ( v2 <= 0 )\n {\nLABEL_9:\n free(v5);\n return 0LL;\n }\n else\n {\n v6 = v2;\n v7 = &v4[v2];\n v8 = (unsigned int)(v2 - 1);\n v9 = 0LL;\n v12 = v7;\n v13 = v8;\n while ( 1 )\n {\n __strncpy_chk(v5, &a2[v9], v6, v3);\n v10 = v6;\n if ( v3 >= v6 )\n v10 = v3;\n __strncpy_chk(v7, a2, v9, v10 - v6);\n *v12 = 0;\n if ( strstr(a1, v5) )\n break;\n --v6;\n if ( v9 == v13 )\n goto LABEL_9;\n ++v9;\n v7 = &v5[v6];\n }\n free(v5);\n return 1LL;\n }\n}", + "ida_strip_asm": "sub_1360:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12, rsi\npush rbp\npush rbx\nsub rsp, 28h\nmov [rsp+58h+haystack], rdi\nmov rdi, rsi; s\ncall _strlen\nlea ebx, [rax+rax+1]\nmov r15, rax\nmovsxd rbx, ebx\nmov rdi, rbx; size\ncall _malloc\nmov rbp, rax\ntest r15d, r15d\njle loc_1440\nmovsxd r14, r15d\nlea r13, [rax+r14]\nlea eax, [r15-1]\nxor r15d, r15d\nmov [rsp+58h+var_48], r13\nmov [rsp+58h+var_40], rax\njmp short loc_13DA\nloc_13C0:\nmov rdx, [rsp+58h+var_40]\nlea rax, [r15+1]\nsub r14, 1\ncmp r15, rdx\njz short loc_1440\nmov r15, rax\nlea r13, [rbp+r14+0]\nloc_13DA:\nlea rsi, [r12+r15]\nmov rcx, rbx\nmov rdx, r14\nmov rdi, rbp\ncall ___strncpy_chk\ncmp rbx, r14\nmov rcx, r14\nmov rsi, r12\ncmovnb rcx, rbx\nmov rdi, r13\nmov rdx, r15\nsub rcx, r14\ncall ___strncpy_chk\nmov rax, [rsp+58h+var_48]\nmov rdi, [rsp+58h+haystack]; haystack\nmov rsi, rbp; needle\nmov byte ptr [rax], 0\ncall _strstr\ntest rax, rax\njz short loc_13C0\nmov rdi, rbp; ptr\ncall _free\nadd rsp, 28h\nmov eax, 1\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1440:\nmov rdi, rbp; ptr\ncall _free\nadd rsp, 28h\nxor eax, eax\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1360(const char *a1, const char *a2)\n{\n int v2; // r15d\n size_t v3; // rbx\n char *v4; // rax\n char *v5; // rbp\n size_t v6; // r14\n char *v7; // r13\n __int64 v8; // rax\n __int64 v9; // r15\n size_t v10; // rcx\n char *v12; // [rsp+10h] [rbp-48h]\n __int64 v13; // [rsp+18h] [rbp-40h]\n\n v2 = strlen(a2);\n v3 = 2 * v2 + 1;\n v4 = (char *)malloc(v3);\n v5 = v4;\n if ( v2 <= 0 )\n {\nLABEL_9:\n free(v5);\n return 0LL;\n }\n else\n {\n v6 = v2;\n v7 = &v4[v2];\n v8 = (unsigned int)(v2 - 1);\n v9 = 0LL;\n v12 = v7;\n v13 = v8;\n while ( 1 )\n {\n __strncpy_chk(v5, &a2[v9], v6, v3);\n v10 = v6;\n if ( v3 >= v6 )\n v10 = v3;\n __strncpy_chk(v7, a2, v9, v10 - v6);\n *v12 = 0;\n if ( strstr(a1, v5) )\n break;\n --v6;\n if ( v9 == v13 )\n goto LABEL_9;\n ++v9;\n v7 = &v5[v6];\n }\n free(v5);\n return 1LL;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1360(const char *a1, const char *a2) {\n int v2;\n unsigned int v3;\n char *v4;\n char *v5;\n unsigned int v6;\n char *v7;\n long long v8;\n long long v9;\n unsigned int v10;\n char *v12;\n long long v13;\n v2 = strlen(a2);\n v3 = 2 * v2 + 1;\n v4 = (char *)malloc(v3);\n v5 = v4;\n if (v2 <= 0) {\n LABEL_9:\n free(v5);\n return 0LL;\n } else {\n v6 = v2;\n v7 = &v4[v2];\n v8 = (unsigned int)(v2 - 1);\n v9 = 0LL;\n v12 = v7;\n v13 = v8;\n while (1) {\n __strncpy_chk(v5, &a2[v9], v6, v3);\n v10 = v6;\n if (v3 >= v6) v10 = v3;\n __strncpy_chk(v7, a2, v9, v10 - v6);\n *v12 = 0;\n if (strstr(a1, v5)) break;\n --v6;\n if (v9 == v13) goto LABEL_9;\n ++v9;\n v7 = &v5[v6];\n }\n free(v5);\n return 1LL;\n }\n}", + "ida_pseudo_norm": "long long func0(const char *a1, const char *a2) {\n int v2;\n unsigned int v3;\n char *v4;\n char *v5;\n unsigned int v6;\n char *v7;\n long long v8;\n long long v9;\n unsigned int v10;\n char *v12;\n long long v13;\n v2 = strlen(a2);\n v3 = 2 * v2 + 1;\n v4 = (char *)malloc(v3);\n v5 = v4;\n if (v2 <= 0) {\n LABEL_9:\n free(v5);\n return 0LL;\n } else {\n v6 = v2;\n v7 = &v4[v2];\n v8 = (unsigned int)(v2 - 1);\n v9 = 0LL;\n v12 = v7;\n v13 = v8;\n while (1) {\n __strncpy_chk(v5, &a2[v9], v6, v3);\n v10 = v6;\n if (v3 >= v6) v10 = v3;\n __strncpy_chk(v7, a2, v9, v10 - v6);\n *v12 = 0;\n if (strstr(a1, v5)) break;\n --v6;\n if (v9 == v13) goto LABEL_9;\n ++v9;\n v7 = &v5[v6];\n }\n free(v5);\n return 1LL;\n }\n}" + }, + { + "index": "HumanEval-C-154", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n#include \n", + "func": "bool func0(const char *a, const char *b) {\n int len_a = strlen(a);\n int len_b = strlen(b);\n char *temp = (char *)malloc(2 * len_b + 1);\n for (int i = 0; i < len_b; i++) {\n strncpy(temp, b + i, len_b - i);\n strncpy(temp + len_b - i, b, i);\n temp[len_b] = '\\0';\n if (strstr(a, temp)) {\n free(temp);\n return true;\n }\n }\n free(temp);\n return false;\n}", + "test": "#include \n#include \n\nint main() {\n assert(func0(\"xyzw\", \"xyw\") == false);\n assert(func0(\"yello\", \"ell\") == true);\n assert(func0(\"whattup\", \"ptut\") == false);\n assert(func0(\"efef\", \"fee\") == true);\n assert(func0(\"abab\", \"aabb\") == false);\n assert(func0(\"winemtt\", \"tinem\") == true);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12, rsi\npush rbp\npush rbx\nsub rsp, 28h\nmov [rsp+58h+haystack], rdi\nmov rdi, rsi; s\ncall _strlen\nlea ebx, [rax+rax+1]\nmov r15, rax\nmovsxd rbx, ebx\nmov rdi, rbx; size\ncall _malloc\nmov rbp, rax\ntest r15d, r15d\njle loc_1440\nmovsxd r14, r15d\nlea r13, [rax+r14]\nlea eax, [r15-1]\nxor r15d, r15d\nmov [rsp+58h+var_48], r13\nmov [rsp+58h+var_40], rax\njmp short loc_13DA\nloc_13C0:\nmov rdx, [rsp+58h+var_40]\nlea rax, [r15+1]\nsub r14, 1\ncmp r15, rdx\njz short loc_1440\nmov r15, rax\nlea r13, [rbp+r14+0]\nloc_13DA:\nlea rsi, [r12+r15]\nmov rcx, rbx\nmov rdx, r14\nmov rdi, rbp\ncall ___strncpy_chk\ncmp rbx, r14\nmov rcx, r14\nmov rsi, r12\ncmovnb rcx, rbx\nmov rdi, r13\nmov rdx, r15\nsub rcx, r14\ncall ___strncpy_chk\nmov rax, [rsp+58h+var_48]\nmov rdi, [rsp+58h+haystack]; haystack\nmov rsi, rbp; needle\nmov byte ptr [rax], 0\ncall _strstr\ntest rax, rax\njz short loc_13C0\nmov rdi, rbp; ptr\ncall _free\nadd rsp, 28h\nmov eax, 1\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1440:\nmov rdi, rbp; ptr\ncall _free\nadd rsp, 28h\nxor eax, eax\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, const char *a2)\n{\n int v2; // r15d\n size_t v3; // rbx\n char *v4; // rax\n char *v5; // rbp\n size_t v6; // r14\n char *v7; // r13\n __int64 v8; // rax\n __int64 v9; // r15\n size_t v10; // rcx\n char *v12; // [rsp+10h] [rbp-48h]\n __int64 v13; // [rsp+18h] [rbp-40h]\n\n v2 = strlen(a2);\n v3 = 2 * v2 + 1;\n v4 = (char *)malloc(v3);\n v5 = v4;\n if ( v2 <= 0 )\n {\nLABEL_9:\n free(v5);\n return 0LL;\n }\n else\n {\n v6 = v2;\n v7 = &v4[v2];\n v8 = (unsigned int)(v2 - 1);\n v9 = 0LL;\n v12 = v7;\n v13 = v8;\n while ( 1 )\n {\n __strncpy_chk(v5, &a2[v9], v6, v3);\n v10 = v6;\n if ( v3 >= v6 )\n v10 = v3;\n __strncpy_chk(v7, a2, v9, v10 - v6);\n *v12 = 0;\n if ( strstr(a1, v5) )\n break;\n --v6;\n if ( v9 == v13 )\n goto LABEL_9;\n ++v9;\n v7 = &v5[v6];\n }\n free(v5);\n return 1LL;\n }\n}", + "ida_strip_asm": "sub_1360:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12, rsi\npush rbp\npush rbx\nsub rsp, 28h\nmov [rsp+58h+haystack], rdi\nmov rdi, rsi; s\ncall _strlen\nlea ebx, [rax+rax+1]\nmov r15, rax\nmovsxd rbx, ebx\nmov rdi, rbx; size\ncall _malloc\nmov rbp, rax\ntest r15d, r15d\njle loc_1440\nmovsxd r14, r15d\nlea r13, [rax+r14]\nlea eax, [r15-1]\nxor r15d, r15d\nmov [rsp+58h+var_48], r13\nmov [rsp+58h+var_40], rax\njmp short loc_13DA\nloc_13C0:\nmov rdx, [rsp+58h+var_40]\nlea rax, [r15+1]\nsub r14, 1\ncmp r15, rdx\njz short loc_1440\nmov r15, rax\nlea r13, [rbp+r14+0]\nloc_13DA:\nlea rsi, [r12+r15]\nmov rcx, rbx\nmov rdx, r14\nmov rdi, rbp\ncall ___strncpy_chk\ncmp rbx, r14\nmov rcx, r14\nmov rsi, r12\ncmovnb rcx, rbx\nmov rdi, r13\nmov rdx, r15\nsub rcx, r14\ncall ___strncpy_chk\nmov rax, [rsp+58h+var_48]\nmov rdi, [rsp+58h+haystack]; haystack\nmov rsi, rbp; needle\nmov byte ptr [rax], 0\ncall _strstr\ntest rax, rax\njz short loc_13C0\nmov rdi, rbp; ptr\ncall _free\nadd rsp, 28h\nmov eax, 1\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1440:\nmov rdi, rbp; ptr\ncall _free\nadd rsp, 28h\nxor eax, eax\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1360(const char *a1, const char *a2)\n{\n int v2; // r15d\n size_t v3; // rbx\n char *v4; // rax\n char *v5; // rbp\n size_t v6; // r14\n char *v7; // r13\n __int64 v8; // rax\n __int64 v9; // r15\n size_t v10; // rcx\n char *v12; // [rsp+10h] [rbp-48h]\n __int64 v13; // [rsp+18h] [rbp-40h]\n\n v2 = strlen(a2);\n v3 = 2 * v2 + 1;\n v4 = (char *)malloc(v3);\n v5 = v4;\n if ( v2 <= 0 )\n {\nLABEL_9:\n free(v5);\n return 0LL;\n }\n else\n {\n v6 = v2;\n v7 = &v4[v2];\n v8 = (unsigned int)(v2 - 1);\n v9 = 0LL;\n v12 = v7;\n v13 = v8;\n while ( 1 )\n {\n __strncpy_chk(v5, &a2[v9], v6, v3);\n v10 = v6;\n if ( v3 >= v6 )\n v10 = v3;\n __strncpy_chk(v7, a2, v9, v10 - v6);\n *v12 = 0;\n if ( strstr(a1, v5) )\n break;\n --v6;\n if ( v9 == v13 )\n goto LABEL_9;\n ++v9;\n v7 = &v5[v6];\n }\n free(v5);\n return 1LL;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1360(const char *a1, const char *a2) {\n int v2;\n unsigned int v3;\n char *v4;\n char *v5;\n unsigned int v6;\n char *v7;\n long long v8;\n long long v9;\n unsigned int v10;\n char *v12;\n long long v13;\n v2 = strlen(a2);\n v3 = 2 * v2 + 1;\n v4 = (char *)malloc(v3);\n v5 = v4;\n if (v2 <= 0) {\n LABEL_9:\n free(v5);\n return 0LL;\n } else {\n v6 = v2;\n v7 = &v4[v2];\n v8 = (unsigned int)(v2 - 1);\n v9 = 0LL;\n v12 = v7;\n v13 = v8;\n while (1) {\n __strncpy_chk(v5, &a2[v9], v6, v3);\n v10 = v6;\n if (v3 >= v6) v10 = v3;\n __strncpy_chk(v7, a2, v9, v10 - v6);\n *v12 = 0;\n if (strstr(a1, v5)) break;\n --v6;\n if (v9 == v13) goto LABEL_9;\n ++v9;\n v7 = &v5[v6];\n }\n free(v5);\n return 1LL;\n }\n}", + "ida_pseudo_norm": "long long func0(const char *a1, const char *a2) {\n int v2;\n unsigned int v3;\n char *v4;\n char *v5;\n unsigned int v6;\n char *v7;\n long long v8;\n long long v9;\n unsigned int v10;\n char *v12;\n long long v13;\n v2 = strlen(a2);\n v3 = 2 * v2 + 1;\n v4 = (char *)malloc(v3);\n v5 = v4;\n if (v2 <= 0) {\n LABEL_9:\n free(v5);\n return 0LL;\n } else {\n v6 = v2;\n v7 = &v4[v2];\n v8 = (unsigned int)(v2 - 1);\n v9 = 0LL;\n v12 = v7;\n v13 = v8;\n while (1) {\n __strncpy_chk(v5, &a2[v9], v6, v3);\n v10 = v6;\n if (v3 >= v6) v10 = v3;\n __strncpy_chk(v7, a2, v9, v10 - v6);\n *v12 = 0;\n if (strstr(a1, v5)) break;\n --v6;\n if (v9 == v13) goto LABEL_9;\n ++v9;\n v7 = &v5[v6];\n }\n free(v5);\n return 1LL;\n }\n}" + }, + { + "index": "HumanEval-C-155", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(int num, int *result) {\n int even_count = 0, odd_count = 0;\n num = abs(num);\n do {\n int digit = num % 10;\n if (digit % 2 == 0) {\n even_count++;\n } else {\n odd_count++;\n }\n num /= 10;\n } while (num > 0);\n result[0] = even_count;\n result[1] = odd_count;\n}", + "test": "#include \n#include \n\nint issame(const int *a, const int *b, int size) {\n return memcmp(a, b, size * sizeof(int)) == 0;\n}\n\nint main() {\n int result[2];\n\n func0(7, result);\n assert(issame(result, (const int[]){0, 1}, 2));\n\n func0(-78, result);\n assert(issame(result, (const int[]){1, 1}, 2));\n\n func0(3452, result);\n assert(issame(result, (const int[]){2, 2}, 2));\n\n func0(346211, result);\n assert(issame(result, (const int[]){3, 3}, 2));\n\n func0(-345821, result);\n assert(issame(result, (const int[]){3, 3}, 2));\n\n func0(-2, result);\n assert(issame(result, (const int[]){1, 0}, 2));\n\n func0(-45347, result);\n assert(issame(result, (const int[]){2, 3}, 2));\n\n func0(0, result);\n assert(issame(result, (const int[]){1, 0}, 2));\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_20], rsi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\nmov eax, [rbp+var_14]\nmov edx, eax\nneg edx\ncmovns eax, edx\nmov [rbp+var_14], eax\nloc_11B3:\nmov edx, [rbp+var_14]\nmovsxd rax, edx\nimul rax, 66666667h\nshr rax, 20h\nmov ecx, eax\nsar ecx, 2\nmov eax, edx\nsar eax, 1Fh\nsub ecx, eax\nmov eax, ecx\nshl eax, 2\nadd eax, ecx\nadd eax, eax\nsub edx, eax\nmov [rbp+var_4], edx\nmov eax, [rbp+var_4]\nand eax, 1\ntest eax, eax\njnz short loc_11EE\nadd [rbp+var_C], 1\njmp short loc_11F2\nloc_11EE:\nadd [rbp+var_8], 1\nloc_11F2:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_14], eax\ncmp [rbp+var_14], 0\njg short loc_11B3\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_C]\nmov [rax], edx\nmov rax, [rbp+var_20]\nlea rdx, [rax+4]\nmov eax, [rbp+var_8]\nmov [rdx], eax\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, _DWORD *a2)\n{\n int v2; // eax\n __int64 result; // rax\n int v4; // [rsp+Ch] [rbp-14h]\n int v5; // [rsp+14h] [rbp-Ch]\n unsigned int v6; // [rsp+18h] [rbp-8h]\n\n v5 = 0;\n v6 = 0;\n v2 = a1;\n if ( a1 <= 0 )\n v2 = -a1;\n v4 = v2;\n do\n {\n if ( ((v4 % 10) & 1) != 0 )\n ++v6;\n else\n ++v5;\n v4 /= 10;\n }\n while ( v4 > 0 );\n *a2 = v5;\n result = v6;\n a2[1] = v6;\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_20], rsi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\nmov eax, [rbp+var_14]\nmov edx, eax\nneg edx\ncmovns eax, edx\nmov [rbp+var_14], eax\nloc_11B3:\nmov edx, [rbp+var_14]\nmovsxd rax, edx\nimul rax, 66666667h\nshr rax, 20h\nmov ecx, eax\nsar ecx, 2\nmov eax, edx\nsar eax, 1Fh\nsub ecx, eax\nmov eax, ecx\nshl eax, 2\nadd eax, ecx\nadd eax, eax\nsub edx, eax\nmov [rbp+var_4], edx\nmov eax, [rbp+var_4]\nand eax, 1\ntest eax, eax\njnz short loc_11EE\nadd [rbp+var_C], 1\njmp short loc_11F2\nloc_11EE:\nadd [rbp+var_8], 1\nloc_11F2:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_14], eax\ncmp [rbp+var_14], 0\njg short loc_11B3\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_C]\nmov [rax], edx\nmov rax, [rbp+var_20]\nlea rdx, [rax+4]\nmov eax, [rbp+var_8]\nmov [rdx], eax\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(int a1, _DWORD *a2)\n{\n int v2; // eax\n __int64 result; // rax\n int v4; // [rsp+Ch] [rbp-14h]\n int v5; // [rsp+14h] [rbp-Ch]\n unsigned int v6; // [rsp+18h] [rbp-8h]\n\n v5 = 0;\n v6 = 0;\n v2 = a1;\n if ( a1 <= 0 )\n v2 = -a1;\n v4 = v2;\n do\n {\n if ( ((v4 % 10) & 1) != 0 )\n ++v6;\n else\n ++v5;\n v4 /= 10;\n }\n while ( v4 > 0 );\n *a2 = v5;\n result = v6;\n a2[1] = v6;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(int a1, uint32_t *a2) {\n int v2;\n long long result;\n int v4;\n int v5;\n unsigned int v6;\n v5 = 0;\n v6 = 0;\n v2 = a1;\n if (a1 <= 0) v2 = -a1;\n v4 = v2;\n do {\n if (((v4 % 10) & 1) != 0)\n ++v6;\n else\n ++v5;\n v4 /= 10;\n } while (v4 > 0);\n *a2 = v5;\n result = v6;\n a2[1] = v6;\n return result;\n}", + "ida_pseudo_norm": "long long func0(int a1, uint32_t *a2) {\n int v2;\n long long result;\n int v4;\n int v5;\n unsigned int v6;\n v5 = 0;\n v6 = 0;\n v2 = a1;\n if (a1 <= 0) v2 = -a1;\n v4 = v2;\n do {\n if (((v4 % 10) & 1) != 0)\n ++v6;\n else\n ++v5;\n v4 /= 10;\n } while (v4 > 0);\n *a2 = v5;\n result = v6;\n a2[1] = v6;\n return result;\n}" + }, + { + "index": "HumanEval-C-155", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(int num, int *result) {\n int even_count = 0, odd_count = 0;\n num = abs(num);\n do {\n int digit = num % 10;\n if (digit % 2 == 0) {\n even_count++;\n } else {\n odd_count++;\n }\n num /= 10;\n } while (num > 0);\n result[0] = even_count;\n result[1] = odd_count;\n}", + "test": "#include \n#include \n\nint issame(const int *a, const int *b, int size) {\n return memcmp(a, b, size * sizeof(int)) == 0;\n}\n\nint main() {\n int result[2];\n\n func0(7, result);\n assert(issame(result, (const int[]){0, 1}, 2));\n\n func0(-78, result);\n assert(issame(result, (const int[]){1, 1}, 2));\n\n func0(3452, result);\n assert(issame(result, (const int[]){2, 2}, 2));\n\n func0(346211, result);\n assert(issame(result, (const int[]){3, 3}, 2));\n\n func0(-345821, result);\n assert(issame(result, (const int[]){3, 3}, 2));\n\n func0(-2, result);\n assert(issame(result, (const int[]){1, 0}, 2));\n\n func0(-45347, result);\n assert(issame(result, (const int[]){2, 3}, 2));\n\n func0(0, result);\n assert(issame(result, (const int[]){1, 0}, 2));\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmov edx, edi\nneg edx\ncmovs edx, edi\nmov edi, 0\nmov r8d, 0\njmp short loc_11C1\nloc_11A1:\nadd r8d, 1\nloc_11A5:\nmovsxd rax, edx\nimul rax, 66666667h\nsar rax, 22h\nmov ecx, edx\nsar ecx, 1Fh\nsub eax, ecx\ncmp edx, 9\njle short loc_11CB\nmov edx, eax\nloc_11C1:\ntest dl, 1\njz short loc_11A1\nadd edi, 1\njmp short loc_11A5\nloc_11CB:\nmov [rsi], r8d\nmov [rsi+4], edi\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, _DWORD *a2)\n{\n int v2; // edx\n int v3; // edi\n int v4; // r8d\n __int64 result; // rax\n\n v2 = -a1;\n if ( a1 > 0 )\n v2 = a1;\n v3 = 0;\n v4 = 0;\n while ( 1 )\n {\n if ( (v2 & 1) != 0 )\n ++v3;\n else\n ++v4;\n result = (unsigned int)(v2 / 10);\n if ( v2 <= 9 )\n break;\n v2 /= 10;\n }\n *a2 = v4;\n a2[1] = v3;\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\nmov edx, edi\nneg edx\ncmovs edx, edi\nmov edi, 0\nmov r8d, 0\njmp short loc_11C1\nloc_11A1:\nadd r8d, 1\nloc_11A5:\nmovsxd rax, edx\nimul rax, 66666667h\nsar rax, 22h\nmov ecx, edx\nsar ecx, 1Fh\nsub eax, ecx\ncmp edx, 9\njle short loc_11CB\nmov edx, eax\nloc_11C1:\ntest dl, 1\njz short loc_11A1\nadd edi, 1\njmp short loc_11A5\nloc_11CB:\nmov [rsi], r8d\nmov [rsi+4], edi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(int a1, _DWORD *a2)\n{\n int v2; // edx\n int v3; // edi\n int v4; // r8d\n __int64 result; // rax\n\n v2 = -a1;\n if ( a1 > 0 )\n v2 = a1;\n v3 = 0;\n v4 = 0;\n while ( 1 )\n {\n if ( (v2 & 1) != 0 )\n ++v3;\n else\n ++v4;\n result = (unsigned int)(v2 / 10);\n if ( v2 <= 9 )\n break;\n v2 /= 10;\n }\n *a2 = v4;\n a2[1] = v3;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(int a1, uint32_t *a2) {\n int v2;\n int v3;\n int v4;\n long long result;\n v2 = -a1;\n if (a1 > 0) v2 = a1;\n v3 = 0;\n v4 = 0;\n while (1) {\n if ((v2 & 1) != 0)\n ++v3;\n else\n ++v4;\n result = (unsigned int)(v2 / 10);\n if (v2 <= 9) break;\n v2 /= 10;\n }\n *a2 = v4;\n a2[1] = v3;\n return result;\n}", + "ida_pseudo_norm": "long long func0(int a1, uint32_t *a2) {\n int v2;\n int v3;\n int v4;\n long long result;\n v2 = -a1;\n if (a1 > 0) v2 = a1;\n v3 = 0;\n v4 = 0;\n while (1) {\n if ((v2 & 1) != 0)\n ++v3;\n else\n ++v4;\n result = (unsigned int)(v2 / 10);\n if (v2 <= 9) break;\n v2 /= 10;\n }\n *a2 = v4;\n a2[1] = v3;\n return result;\n}" + }, + { + "index": "HumanEval-C-155", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(int num, int *result) {\n int even_count = 0, odd_count = 0;\n num = abs(num);\n do {\n int digit = num % 10;\n if (digit % 2 == 0) {\n even_count++;\n } else {\n odd_count++;\n }\n num /= 10;\n } while (num > 0);\n result[0] = even_count;\n result[1] = odd_count;\n}", + "test": "#include \n#include \n\nint issame(const int *a, const int *b, int size) {\n return memcmp(a, b, size * sizeof(int)) == 0;\n}\n\nint main() {\n int result[2];\n\n func0(7, result);\n assert(issame(result, (const int[]){0, 1}, 2));\n\n func0(-78, result);\n assert(issame(result, (const int[]){1, 1}, 2));\n\n func0(3452, result);\n assert(issame(result, (const int[]){2, 2}, 2));\n\n func0(346211, result);\n assert(issame(result, (const int[]){3, 3}, 2));\n\n func0(-345821, result);\n assert(issame(result, (const int[]){3, 3}, 2));\n\n func0(-2, result);\n assert(issame(result, (const int[]){1, 0}, 2));\n\n func0(-45347, result);\n assert(issame(result, (const int[]){2, 3}, 2));\n\n func0(0, result);\n assert(issame(result, (const int[]){1, 0}, 2));\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmov edx, edi\nmov r8d, 0CCCCCCCDh\nneg edx\ncmovs edx, edi\nxor ecx, ecx\nxor edi, edi\njmp short loc_1422\nloc_1410:\nimul rax, r8\nadd edi, 1\nshr rax, 23h\ncmp edx, 9\njle short loc_1439\nloc_1420:\nmov edx, eax\nloc_1422:\nmov eax, edx\ntest dl, 1\njz short loc_1410\nimul rax, r8\nadd ecx, 1\nshr rax, 23h\ncmp edx, 9\njg short loc_1420\nloc_1439:\nmov [rsi], edi\nmov [rsi+4], ecx\nretn", + "ida_pseudo": "unsigned __int64 __fastcall func0(int a1, _DWORD *a2)\n{\n int v2; // edx\n int v3; // ecx\n int v4; // edi\n unsigned __int64 result; // rax\n\n v2 = -a1;\n if ( a1 > 0 )\n v2 = a1;\n v3 = 0;\n v4 = 0;\n while ( (v2 & 1) == 0 )\n {\n ++v4;\n result = (unsigned int)v2 / 0xAuLL;\n if ( v2 <= 9 )\n goto LABEL_8;\nLABEL_5:\n v2 = result;\n }\n ++v3;\n result = (unsigned int)v2 / 0xAuLL;\n if ( v2 > 9 )\n goto LABEL_5;\nLABEL_8:\n *a2 = v4;\n a2[1] = v3;\n return result;\n}", + "ida_strip_asm": "sub_13F0:\nendbr64\nmov edx, edi\nmov r8d, 0CCCCCCCDh\nneg edx\ncmovs edx, edi\nxor ecx, ecx\nxor edi, edi\njmp short loc_1422\nloc_1410:\nimul rax, r8\nadd edi, 1\nshr rax, 23h\ncmp edx, 9\njle short loc_1439\nloc_1420:\nmov edx, eax\nloc_1422:\nmov eax, edx\ntest dl, 1\njz short loc_1410\nimul rax, r8\nadd ecx, 1\nshr rax, 23h\ncmp edx, 9\njg short loc_1420\nloc_1439:\nmov [rsi], edi\nmov [rsi+4], ecx\nretn", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_13F0(int a1, _DWORD *a2)\n{\n int v2; // edx\n int v3; // ecx\n int v4; // edi\n unsigned __int64 result; // rax\n\n v2 = -a1;\n if ( a1 > 0 )\n v2 = a1;\n v3 = 0;\n v4 = 0;\n while ( (v2 & 1) == 0 )\n {\n ++v4;\n result = (unsigned int)v2 / 0xAuLL;\n if ( v2 <= 9 )\n goto LABEL_8;\nLABEL_5:\n v2 = result;\n }\n ++v3;\n result = (unsigned int)v2 / 0xAuLL;\n if ( v2 > 9 )\n goto LABEL_5;\nLABEL_8:\n *a2 = v4;\n a2[1] = v3;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_13F0(int a1, uint32_t *a2) {\n int v2;\n int v3;\n int v4;\n unsigned long long result;\n v2 = -a1;\n if (a1 > 0) v2 = a1;\n v3 = 0;\n v4 = 0;\n while ((v2 & 1) == 0) {\n ++v4;\n result = (unsigned int)v2 / 10uLL;\n if (v2 <= 9) goto LABEL_8;\n LABEL_5:\n v2 = result;\n }\n ++v3;\n result = (unsigned int)v2 / 10uLL;\n if (v2 > 9) goto LABEL_5;\nLABEL_8:\n *a2 = v4;\n a2[1] = v3;\n return result;\n}", + "ida_pseudo_norm": "unsigned long long func0(int a1, uint32_t *a2) {\n int v2;\n int v3;\n int v4;\n unsigned long long result;\n v2 = -a1;\n if (a1 > 0) v2 = a1;\n v3 = 0;\n v4 = 0;\n while ((v2 & 1) == 0) {\n ++v4;\n result = (unsigned int)v2 / 10uLL;\n if (v2 <= 9) goto LABEL_8;\n LABEL_5:\n v2 = result;\n }\n ++v3;\n result = (unsigned int)v2 / 10uLL;\n if (v2 > 9) goto LABEL_5;\nLABEL_8:\n *a2 = v4;\n a2[1] = v3;\n return result;\n}" + }, + { + "index": "HumanEval-C-156", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(int number, char *result) {\n const char *rep[] = {\"m\", \"cm\", \"d\", \"cd\", \"c\", \"xc\", \"l\",\n \"xl\", \"x\", \"ix\", \"v\", \"iv\", \"i\"};\n const int num[] = {1000, 900, 500, 400, 100, 90, 50, 40, 10, 9, 5, 4, 1};\n int pos = 0;\n result[0] = '\\0';\n while (number > 0) {\n while (number >= num[pos]) {\n strcat(result, rep[pos]);\n number -= num[pos];\n }\n if (number > 0) pos++;\n }\n}", + "test": "#include \n#include \n\nint main() {\n char result[64]; // Buffer large enough for all Roman numeral representations of numbers 1-1000\n\n func0(19, result);\n assert(strcmp(result, \"xix\") == 0);\n\n func0(152, result);\n assert(strcmp(result, \"clii\") == 0);\n\n func0(251, result);\n assert(strcmp(result, \"ccli\") == 0);\n\n func0(426, result);\n assert(strcmp(result, \"cdxxvi\") == 0);\n\n func0(500, result);\n assert(strcmp(result, \"d\") == 0);\n\n func0(1, result);\n assert(strcmp(result, \"i\") == 0);\n\n func0(4, result);\n assert(strcmp(result, \"iv\") == 0);\n\n func0(43, result);\n assert(strcmp(result, \"xliii\") == 0);\n\n func0(90, result);\n assert(strcmp(result, \"xc\") == 0);\n\n func0(94, result);\n assert(strcmp(result, \"xciv\") == 0);\n\n func0(532, result);\n assert(strcmp(result, \"dxxxii\") == 0);\n\n func0(900, result);\n assert(strcmp(result, \"cm\") == 0);\n\n func0(994, result);\n assert(strcmp(result, \"cmxciv\") == 0);\n\n func0(1000, result);\n assert(strcmp(result, \"m\") == 0);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0D0h\nmov [rbp+var_C4], edi\nmov [rbp+dest], rsi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aM; \"m\"\nmov [rbp+src], rax\nlea rax, aCm; \"cm\"\nmov [rbp+var_68], rax\nlea rax, aD; \"d\"\nmov [rbp+var_60], rax\nlea rax, aCd; \"cd\"\nmov [rbp+var_58], rax\nlea rax, aC; \"c\"\nmov [rbp+var_50], rax\nlea rax, aXc; \"xc\"\nmov [rbp+var_48], rax\nlea rax, asc_2017; \"l\"\nmov [rbp+var_40], rax\nlea rax, aXl; \"xl\"\nmov [rbp+var_38], rax\nlea rax, asc_201C; \"x\"\nmov [rbp+var_30], rax\nlea rax, aIx; \"ix\"\nmov [rbp+var_28], rax\nlea rax, aV; \"v\"\nmov [rbp+var_20], rax\nlea rax, aIv; \"iv\"\nmov [rbp+var_18], rax\nlea rax, aI; \"i\"\nmov [rbp+var_10], rax\nmov [rbp+var_B0], 3E8h\nmov [rbp+var_AC], 384h\nmov [rbp+var_A8], 1F4h\nmov [rbp+var_A4], 190h\nmov [rbp+var_A0], 64h ; 'd'\nmov [rbp+var_9C], 5Ah ; 'Z'\nmov [rbp+var_98], 32h ; '2'\nmov [rbp+var_94], 28h ; '('\nmov [rbp+var_90], 0Ah\nmov [rbp+var_8C], 9\nmov [rbp+var_88], 5\nmov [rbp+var_84], 4\nmov [rbp+var_80], 1\nmov [rbp+var_B4], 0\nmov rax, [rbp+dest]\nmov byte ptr [rax], 0\njmp short loc_1353\nloc_12F8:\nmov eax, [rbp+var_B4]\ncdqe\nmov rdx, [rbp+rax*8+src]\nmov rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\nmov eax, [rbp+var_B4]\ncdqe\nmov eax, [rbp+rax*4+var_B0]\nsub [rbp+var_C4], eax\nloc_132C:\nmov eax, [rbp+var_B4]\ncdqe\nmov eax, [rbp+rax*4+var_B0]\ncmp [rbp+var_C4], eax\njge short loc_12F8\ncmp [rbp+var_C4], 0\njle short loc_1353\nadd [rbp+var_B4], 1\nloc_1353:\ncmp [rbp+var_C4], 0\njg short loc_132C\nnop\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njz short locret_1371\ncall ___stack_chk_fail\nlocret_1371:\nleave\nretn", + "ida_pseudo": "unsigned __int64 __fastcall func0(int a1, char *a2)\n{\n int v4; // [rsp+1Ch] [rbp-B4h]\n _DWORD v5[16]; // [rsp+20h] [rbp-B0h]\n char *src[13]; // [rsp+60h] [rbp-70h]\n unsigned __int64 v7; // [rsp+C8h] [rbp-8h]\n\n v7 = __readfsqword(0x28u);\n src[0] = \"m\";\n src[1] = \"cm\";\n src[2] = \"d\";\n src[3] = \"cd\";\n src[4] = \"c\";\n src[5] = \"xc\";\n src[6] = \"l\";\n src[7] = \"xl\";\n src[8] = \"x\";\n src[9] = \"ix\";\n src[10] = \"v\";\n src[11] = \"iv\";\n src[12] = \"i\";\n v5[0] = 1000;\n v5[1] = 900;\n v5[2] = 500;\n v5[3] = 400;\n v5[4] = 100;\n v5[5] = 90;\n v5[6] = 50;\n v5[7] = 40;\n v5[8] = 10;\n v5[9] = 9;\n v5[10] = 5;\n v5[11] = 4;\n v5[12] = 1;\n v4 = 0;\n *a2 = 0;\n while ( a1 > 0 )\n {\n while ( a1 >= v5[v4] )\n {\n strcat(a2, src[v4]);\n a1 -= v5[v4];\n }\n if ( a1 > 0 )\n ++v4;\n }\n return v7 - __readfsqword(0x28u);\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0D0h\nmov [rbp+var_C4], edi\nmov [rbp+dest], rsi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aM; \"m\"\nmov [rbp+src], rax\nlea rax, aCm; \"cm\"\nmov [rbp+var_68], rax\nlea rax, aD; \"d\"\nmov [rbp+var_60], rax\nlea rax, aCd; \"cd\"\nmov [rbp+var_58], rax\nlea rax, aC; \"c\"\nmov [rbp+var_50], rax\nlea rax, aXc; \"xc\"\nmov [rbp+var_48], rax\nlea rax, asc_2017; \"l\"\nmov [rbp+var_40], rax\nlea rax, aXl; \"xl\"\nmov [rbp+var_38], rax\nlea rax, asc_201C; \"x\"\nmov [rbp+var_30], rax\nlea rax, aIx; \"ix\"\nmov [rbp+var_28], rax\nlea rax, aV; \"v\"\nmov [rbp+var_20], rax\nlea rax, aIv; \"iv\"\nmov [rbp+var_18], rax\nlea rax, aI; \"i\"\nmov [rbp+var_10], rax\nmov [rbp+var_B0], 3E8h\nmov [rbp+var_AC], 384h\nmov [rbp+var_A8], 1F4h\nmov [rbp+var_A4], 190h\nmov [rbp+var_A0], 64h ; 'd'\nmov [rbp+var_9C], 5Ah ; 'Z'\nmov [rbp+var_98], 32h ; '2'\nmov [rbp+var_94], 28h ; '('\nmov [rbp+var_90], 0Ah\nmov [rbp+var_8C], 9\nmov [rbp+var_88], 5\nmov [rbp+var_84], 4\nmov [rbp+var_80], 1\nmov [rbp+var_B4], 0\nmov rax, [rbp+dest]\nmov byte ptr [rax], 0\njmp short loc_1353\nloc_12F8:\nmov eax, [rbp+var_B4]\ncdqe\nmov rdx, [rbp+rax*8+src]\nmov rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\nmov eax, [rbp+var_B4]\ncdqe\nmov eax, [rbp+rax*4+var_B0]\nsub [rbp+var_C4], eax\nloc_132C:\nmov eax, [rbp+var_B4]\ncdqe\nmov eax, [rbp+rax*4+var_B0]\ncmp [rbp+var_C4], eax\njge short loc_12F8\ncmp [rbp+var_C4], 0\njle short loc_1353\nadd [rbp+var_B4], 1\nloc_1353:\ncmp [rbp+var_C4], 0\njg short loc_132C\nnop\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njz short locret_1371\ncall ___stack_chk_fail\nlocret_1371:\nleave\nretn", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_11A9(int a1, char *a2)\n{\n int v4; // [rsp+1Ch] [rbp-B4h]\n _DWORD v5[16]; // [rsp+20h] [rbp-B0h]\n char *src[13]; // [rsp+60h] [rbp-70h]\n unsigned __int64 v7; // [rsp+C8h] [rbp-8h]\n\n v7 = __readfsqword(0x28u);\n src[0] = \"m\";\n src[1] = \"cm\";\n src[2] = \"d\";\n src[3] = \"cd\";\n src[4] = \"c\";\n src[5] = \"xc\";\n src[6] = \"l\";\n src[7] = \"xl\";\n src[8] = \"x\";\n src[9] = \"ix\";\n src[10] = \"v\";\n src[11] = \"iv\";\n src[12] = \"i\";\n v5[0] = 1000;\n v5[1] = 900;\n v5[2] = 500;\n v5[3] = 400;\n v5[4] = 100;\n v5[5] = 90;\n v5[6] = 50;\n v5[7] = 40;\n v5[8] = 10;\n v5[9] = 9;\n v5[10] = 5;\n v5[11] = 4;\n v5[12] = 1;\n v4 = 0;\n *a2 = 0;\n while ( a1 > 0 )\n {\n while ( a1 >= v5[v4] )\n {\n strcat(a2, src[v4]);\n a1 -= v5[v4];\n }\n if ( a1 > 0 )\n ++v4;\n }\n return v7 - __readfsqword(0x28u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_11A9(int a1, char *a2) {\n int v4;\n uint32_t v5[16];\n char *src[13];\n unsigned long long v7;\n v7 = __readfsqword(40u);\n src[0] = \"m\";\n src[1] = \"cm\";\n src[2] = \"d\";\n src[3] = \"cd\";\n src[4] = \"c\";\n src[5] = \"xc\";\n src[6] = \"l\";\n src[7] = \"xl\";\n src[8] = \"x\";\n src[9] = \"ix\";\n src[10] = \"v\";\n src[11] = \"iv\";\n src[12] = \"i\";\n v5[0] = 1000;\n v5[1] = 900;\n v5[2] = 500;\n v5[3] = 400;\n v5[4] = 100;\n v5[5] = 90;\n v5[6] = 50;\n v5[7] = 40;\n v5[8] = 10;\n v5[9] = 9;\n v5[10] = 5;\n v5[11] = 4;\n v5[12] = 1;\n v4 = 0;\n *a2 = 0;\n while (a1 > 0) {\n while (a1 >= v5[v4]) {\n strcat(a2, src[v4]);\n a1 -= v5[v4];\n }\n if (a1 > 0) ++v4;\n }\n return v7 - __readfsqword(40u);\n}", + "ida_pseudo_norm": "unsigned long long func0(int a1, char *a2) {\n int v4;\n uint32_t v5[16];\n char *src[13];\n unsigned long long v7;\n v7 = __readfsqword(40u);\n src[0] = \"m\";\n src[1] = \"cm\";\n src[2] = \"d\";\n src[3] = \"cd\";\n src[4] = \"c\";\n src[5] = \"xc\";\n src[6] = \"l\";\n src[7] = \"xl\";\n src[8] = \"x\";\n src[9] = \"ix\";\n src[10] = \"v\";\n src[11] = \"iv\";\n src[12] = \"i\";\n v5[0] = 1000;\n v5[1] = 900;\n v5[2] = 500;\n v5[3] = 400;\n v5[4] = 100;\n v5[5] = 90;\n v5[6] = 50;\n v5[7] = 40;\n v5[8] = 10;\n v5[9] = 9;\n v5[10] = 5;\n v5[11] = 4;\n v5[12] = 1;\n v4 = 0;\n *a2 = 0;\n while (a1 > 0) {\n while (a1 >= v5[v4]) {\n strcat(a2, src[v4]);\n a1 -= v5[v4];\n }\n if (a1 > 0) ++v4;\n }\n return v7 - __readfsqword(40u);\n}" + }, + { + "index": "HumanEval-C-156", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(int number, char *result) {\n const char *rep[] = {\"m\", \"cm\", \"d\", \"cd\", \"c\", \"xc\", \"l\",\n \"xl\", \"x\", \"ix\", \"v\", \"iv\", \"i\"};\n const int num[] = {1000, 900, 500, 400, 100, 90, 50, 40, 10, 9, 5, 4, 1};\n int pos = 0;\n result[0] = '\\0';\n while (number > 0) {\n while (number >= num[pos]) {\n strcat(result, rep[pos]);\n number -= num[pos];\n }\n if (number > 0) pos++;\n }\n}", + "test": "#include \n#include \n\nint main() {\n char result[64]; // Buffer large enough for all Roman numeral representations of numbers 1-1000\n\n func0(19, result);\n assert(strcmp(result, \"xix\") == 0);\n\n func0(152, result);\n assert(strcmp(result, \"clii\") == 0);\n\n func0(251, result);\n assert(strcmp(result, \"ccli\") == 0);\n\n func0(426, result);\n assert(strcmp(result, \"cdxxvi\") == 0);\n\n func0(500, result);\n assert(strcmp(result, \"d\") == 0);\n\n func0(1, result);\n assert(strcmp(result, \"i\") == 0);\n\n func0(4, result);\n assert(strcmp(result, \"iv\") == 0);\n\n func0(43, result);\n assert(strcmp(result, \"xliii\") == 0);\n\n func0(90, result);\n assert(strcmp(result, \"xc\") == 0);\n\n func0(94, result);\n assert(strcmp(result, \"xciv\") == 0);\n\n func0(532, result);\n assert(strcmp(result, \"dxxxii\") == 0);\n\n func0(900, result);\n assert(strcmp(result, \"cm\") == 0);\n\n func0(994, result);\n assert(strcmp(result, \"cmxciv\") == 0);\n\n func0(1000, result);\n assert(strcmp(result, \"m\") == 0);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 0B0h\nmov rax, fs:28h\nmov [rsp+0D8h+var_30], rax\nxor eax, eax\nlea rax, aCm+1; \"m\"\nmov [rsp+0D8h+var_98], rax\nlea rax, aCm; \"cm\"\nmov [rsp+0D8h+var_90], rax\nlea rax, aCd+1; \"d\"\nmov [rsp+0D8h+var_88], rax\nlea rax, aCd; \"cd\"\nmov [rsp+0D8h+var_80], rax\nlea rax, aXc+1; \"c\"\nmov [rsp+0D8h+var_78], rax\nlea rax, aXc; \"xc\"\nmov [rsp+0D8h+var_70], rax\nlea rax, aXl+1; \"l\"\nmov [rsp+0D8h+var_68], rax\nlea rax, aXl; \"xl\"\nmov [rsp+0D8h+var_60], rax\nlea rax, s2+2; \"x\"\nmov [rsp+0D8h+var_58], rax\nlea rax, s2+1; \"ix\"\nmov [rsp+0D8h+var_50], rax\nlea rax, aCmxciv+5; \"v\"\nmov [rsp+0D8h+var_48], rax\nlea rax, aCmxciv+4; \"iv\"\nmov [rsp+0D8h+var_40], rax\nlea rax, aXliii+4; \"i\"\nmov [rsp+0D8h+var_38], rax\nmov [rsp+0D8h+var_D8], 3E8h\nmov [rsp+0D8h+var_D4], 384h\nmov [rsp+0D8h+var_D0], 1F4h\nmov [rsp+0D8h+var_CC], 190h\nmov [rsp+0D8h+var_C8], 64h ; 'd'\nmov [rsp+0D8h+var_C4], 5Ah ; 'Z'\nmov [rsp+0D8h+var_C0], 32h ; '2'\nmov [rsp+0D8h+var_BC], 28h ; '('\nmov [rsp+0D8h+var_B8], 0Ah\nmov [rsp+0D8h+var_B4], 9\nmov [rsp+0D8h+var_B0], 5\nmov [rsp+0D8h+var_AC], 4\nmov [rsp+0D8h+var_A8], 1\nmov byte ptr [rsi], 0\ntest edi, edi\njle short loc_131C\nmov ebx, edi\nmov r13, rsi\nmov r14, rsp\nlea r12, [rsp+0D8h+var_98]\njmp short loc_12FF\nloc_12F7:\nadd r14, 4\nadd r12, 8\nloc_12FF:\nmov ebp, [r14]\ncmp ebp, ebx\njg short loc_12F7\nloc_1306:\nmov rsi, [r12]; src\nmov rdi, r13; dest\ncall _strcat\nsub ebx, ebp\ncmp ebx, ebp\njge short loc_1306\ntest ebx, ebx\njg short loc_12F7\nloc_131C:\nmov rax, [rsp+0D8h+var_30]\nsub rax, fs:28h\njnz short loc_133F\nadd rsp, 0B0h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_133F:\ncall ___stack_chk_fail", + "ida_pseudo": "unsigned __int64 __fastcall func0(int a1, char *a2)\n{\n int v2; // ebx\n int *v3; // r14\n const char **i; // r12\n int v5; // ebp\n _DWORD v7[16]; // [rsp+0h] [rbp-D8h] BYREF\n _QWORD v8[13]; // [rsp+40h] [rbp-98h] BYREF\n unsigned __int64 v9; // [rsp+A8h] [rbp-30h]\n\n v9 = __readfsqword(0x28u);\n v8[0] = \"m\";\n v8[1] = \"cm\";\n v8[2] = \"d\";\n v8[3] = \"cd\";\n v8[4] = \"c\";\n v8[5] = \"xc\";\n v8[6] = \"l\";\n v8[7] = \"xl\";\n v8[8] = \"x\";\n v8[9] = \"ix\";\n v8[10] = \"v\";\n v8[11] = \"iv\";\n v8[12] = \"i\";\n v7[0] = 1000;\n v7[1] = 900;\n v7[2] = 500;\n v7[3] = 400;\n v7[4] = 100;\n v7[5] = 90;\n v7[6] = 50;\n v7[7] = 40;\n v7[8] = 10;\n v7[9] = 9;\n v7[10] = 5;\n v7[11] = 4;\n v7[12] = 1;\n *a2 = 0;\n if ( a1 > 0 )\n {\n v2 = a1;\n v3 = v7;\n for ( i = (const char **)v8; ; ++i )\n {\n v5 = *v3;\n if ( *v3 <= v2 )\n {\n do\n {\n strcat(a2, *i);\n v2 -= v5;\n }\n while ( v2 >= v5 );\n if ( v2 <= 0 )\n break;\n }\n ++v3;\n }\n }\n return v9 - __readfsqword(0x28u);\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 0B0h\nmov rax, fs:28h\nmov [rsp+0D8h+var_30], rax\nxor eax, eax\nlea rax, aCm+1; \"m\"\nmov [rsp+0D8h+var_98], rax\nlea rax, aCm; \"cm\"\nmov [rsp+0D8h+var_90], rax\nlea rax, aCd+1; \"d\"\nmov [rsp+0D8h+var_88], rax\nlea rax, aCd; \"cd\"\nmov [rsp+0D8h+var_80], rax\nlea rax, aXc+1; \"c\"\nmov [rsp+0D8h+var_78], rax\nlea rax, aXc; \"xc\"\nmov [rsp+0D8h+var_70], rax\nlea rax, aXl+1; \"l\"\nmov [rsp+0D8h+var_68], rax\nlea rax, aXl; \"xl\"\nmov [rsp+0D8h+var_60], rax\nlea rax, s2+2; \"x\"\nmov [rsp+0D8h+var_58], rax\nlea rax, s2+1; \"ix\"\nmov [rsp+0D8h+var_50], rax\nlea rax, aCmxciv+5; \"v\"\nmov [rsp+0D8h+var_48], rax\nlea rax, aCmxciv+4; \"iv\"\nmov [rsp+0D8h+var_40], rax\nlea rax, aXliii+4; \"i\"\nmov [rsp+0D8h+var_38], rax\nmov [rsp+0D8h+var_D8], 3E8h\nmov [rsp+0D8h+var_D4], 384h\nmov [rsp+0D8h+var_D0], 1F4h\nmov [rsp+0D8h+var_CC], 190h\nmov [rsp+0D8h+var_C8], 64h ; 'd'\nmov [rsp+0D8h+var_C4], 5Ah ; 'Z'\nmov [rsp+0D8h+var_C0], 32h ; '2'\nmov [rsp+0D8h+var_BC], 28h ; '('\nmov [rsp+0D8h+var_B8], 0Ah\nmov [rsp+0D8h+var_B4], 9\nmov [rsp+0D8h+var_B0], 5\nmov [rsp+0D8h+var_AC], 4\nmov [rsp+0D8h+var_A8], 1\nmov byte ptr [rsi], 0\ntest edi, edi\njle short loc_131C\nmov ebx, edi\nmov r13, rsi\nmov r14, rsp\nlea r12, [rsp+0D8h+var_98]\njmp short loc_12FF\nloc_12F7:\nadd r14, 4\nadd r12, 8\nloc_12FF:\nmov ebp, [r14]\ncmp ebp, ebx\njg short loc_12F7\nloc_1306:\nmov rsi, [r12]; src\nmov rdi, r13; dest\ncall _strcat\nsub ebx, ebp\ncmp ebx, ebp\njge short loc_1306\ntest ebx, ebx\njg short loc_12F7\nloc_131C:\nmov rax, [rsp+0D8h+var_30]\nsub rax, fs:28h\njnz short loc_133F\nadd rsp, 0B0h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_133F:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_11A9(int a1, char *a2)\n{\n int v2; // ebx\n int *v3; // r14\n const char **i; // r12\n int v5; // ebp\n _DWORD v7[16]; // [rsp+0h] [rbp-D8h] BYREF\n _QWORD v8[13]; // [rsp+40h] [rbp-98h] BYREF\n unsigned __int64 v9; // [rsp+A8h] [rbp-30h]\n\n v9 = __readfsqword(0x28u);\n v8[0] = \"m\";\n v8[1] = \"cm\";\n v8[2] = \"d\";\n v8[3] = \"cd\";\n v8[4] = \"c\";\n v8[5] = \"xc\";\n v8[6] = \"l\";\n v8[7] = \"xl\";\n v8[8] = \"x\";\n v8[9] = \"ix\";\n v8[10] = \"v\";\n v8[11] = \"iv\";\n v8[12] = \"i\";\n v7[0] = 1000;\n v7[1] = 900;\n v7[2] = 500;\n v7[3] = 400;\n v7[4] = 100;\n v7[5] = 90;\n v7[6] = 50;\n v7[7] = 40;\n v7[8] = 10;\n v7[9] = 9;\n v7[10] = 5;\n v7[11] = 4;\n v7[12] = 1;\n *a2 = 0;\n if ( a1 > 0 )\n {\n v2 = a1;\n v3 = v7;\n for ( i = (const char **)v8; ; ++i )\n {\n v5 = *v3;\n if ( *v3 <= v2 )\n {\n do\n {\n strcat(a2, *i);\n v2 -= v5;\n }\n while ( v2 >= v5 );\n if ( v2 <= 0 )\n break;\n }\n ++v3;\n }\n }\n return v9 - __readfsqword(0x28u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_11A9(int a1, char *a2) {\n int v2;\n int *v3;\n const char **i;\n int v5;\n uint32_t v7[16];\n uint64_t v8[13];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n v8[0] = \"m\";\n v8[1] = \"cm\";\n v8[2] = \"d\";\n v8[3] = \"cd\";\n v8[4] = \"c\";\n v8[5] = \"xc\";\n v8[6] = \"l\";\n v8[7] = \"xl\";\n v8[8] = \"x\";\n v8[9] = \"ix\";\n v8[10] = \"v\";\n v8[11] = \"iv\";\n v8[12] = \"i\";\n v7[0] = 1000;\n v7[1] = 900;\n v7[2] = 500;\n v7[3] = 400;\n v7[4] = 100;\n v7[5] = 90;\n v7[6] = 50;\n v7[7] = 40;\n v7[8] = 10;\n v7[9] = 9;\n v7[10] = 5;\n v7[11] = 4;\n v7[12] = 1;\n *a2 = 0;\n if (a1 > 0) {\n v2 = a1;\n v3 = v7;\n for (i = (const char **)v8;; ++i) {\n v5 = *v3;\n if (*v3 <= v2) {\n do {\n strcat(a2, *i);\n v2 -= v5;\n } while (v2 >= v5);\n if (v2 <= 0) break;\n }\n ++v3;\n }\n }\n return v9 - __readfsqword(40u);\n}", + "ida_pseudo_norm": "unsigned long long func0(int a1, char *a2) {\n int v2;\n int *v3;\n const char **i;\n int v5;\n uint32_t v7[16];\n uint64_t v8[13];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n v8[0] = \"m\";\n v8[1] = \"cm\";\n v8[2] = \"d\";\n v8[3] = \"cd\";\n v8[4] = \"c\";\n v8[5] = \"xc\";\n v8[6] = \"l\";\n v8[7] = \"xl\";\n v8[8] = \"x\";\n v8[9] = \"ix\";\n v8[10] = \"v\";\n v8[11] = \"iv\";\n v8[12] = \"i\";\n v7[0] = 1000;\n v7[1] = 900;\n v7[2] = 500;\n v7[3] = 400;\n v7[4] = 100;\n v7[5] = 90;\n v7[6] = 50;\n v7[7] = 40;\n v7[8] = 10;\n v7[9] = 9;\n v7[10] = 5;\n v7[11] = 4;\n v7[12] = 1;\n *a2 = 0;\n if (a1 > 0) {\n v2 = a1;\n v3 = v7;\n for (i = (const char **)v8;; ++i) {\n v5 = *v3;\n if (*v3 <= v2) {\n do {\n strcat(a2, *i);\n v2 -= v5;\n } while (v2 >= v5);\n if (v2 <= 0) break;\n }\n ++v3;\n }\n }\n return v9 - __readfsqword(40u);\n}" + }, + { + "index": "HumanEval-C-156", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(int number, char *result) {\n const char *rep[] = {\"m\", \"cm\", \"d\", \"cd\", \"c\", \"xc\", \"l\",\n \"xl\", \"x\", \"ix\", \"v\", \"iv\", \"i\"};\n const int num[] = {1000, 900, 500, 400, 100, 90, 50, 40, 10, 9, 5, 4, 1};\n int pos = 0;\n result[0] = '\\0';\n while (number > 0) {\n while (number >= num[pos]) {\n strcat(result, rep[pos]);\n number -= num[pos];\n }\n if (number > 0) pos++;\n }\n}", + "test": "#include \n#include \n\nint main() {\n char result[64]; // Buffer large enough for all Roman numeral representations of numbers 1-1000\n\n func0(19, result);\n assert(strcmp(result, \"xix\") == 0);\n\n func0(152, result);\n assert(strcmp(result, \"clii\") == 0);\n\n func0(251, result);\n assert(strcmp(result, \"ccli\") == 0);\n\n func0(426, result);\n assert(strcmp(result, \"cdxxvi\") == 0);\n\n func0(500, result);\n assert(strcmp(result, \"d\") == 0);\n\n func0(1, result);\n assert(strcmp(result, \"i\") == 0);\n\n func0(4, result);\n assert(strcmp(result, \"iv\") == 0);\n\n func0(43, result);\n assert(strcmp(result, \"xliii\") == 0);\n\n func0(90, result);\n assert(strcmp(result, \"xc\") == 0);\n\n func0(94, result);\n assert(strcmp(result, \"xciv\") == 0);\n\n func0(532, result);\n assert(strcmp(result, \"dxxxii\") == 0);\n\n func0(900, result);\n assert(strcmp(result, \"cm\") == 0);\n\n func0(994, result);\n assert(strcmp(result, \"cmxciv\") == 0);\n\n func0(1000, result);\n assert(strcmp(result, \"m\") == 0);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\nlea rcx, unk_2005\npush r14\nmovq xmm0, rcx\nlea rcx, unk_2008\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 0B8h\nmov rax, fs:28h\nmov [rsp+0E8h+var_40], rax\nlea rax, unk_2004\nmov [rsp+0E8h+var_B8], 1\nmov byte ptr [rsi], 0\nmovq xmm1, rax\nlea rax, unk_2007\npunpcklqdq xmm0, xmm1\nmovq xmm2, rax\nlea rax, unk_200A\nmovaps [rsp+0E8h+var_A8], xmm0\nmovq xmm0, rcx\nmovq xmm3, rax\nlea rcx, unk_200B\npunpcklqdq xmm0, xmm2\nlea rax, unk_200D\nmovaps [rsp+0E8h+var_98], xmm0\nmovq xmm0, rcx\nmovq xmm4, rax\nlea rcx, unk_200E\npunpcklqdq xmm0, xmm3\nlea rax, unk_2011\nmovaps [rsp+0E8h+var_88], xmm0\nmovq xmm0, rcx\nmovq xmm5, rax\nlea rcx, unk_2012\npunpcklqdq xmm0, xmm4\nlea rax, aCmxciv+4; \"iv\"\nmovaps [rsp+0E8h+var_78], xmm0\nmovq xmm0, rcx\nmovq xmm6, rax\nlea rcx, aCmxciv+5; \"v\"\npunpcklqdq xmm0, xmm5\nlea rax, aXliii+4; \"i\"\nmovaps [rsp+0E8h+var_68], xmm0\nmovq xmm0, rcx\npunpcklqdq xmm0, xmm6\nmov [rsp+0E8h+var_48], rax\nmovaps [rsp+0E8h+var_58], xmm0\nmovdqa xmm0, cs:xmmword_21E0\nmovaps [rsp+0E8h+var_E8], xmm0\nmovdqa xmm0, cs:xmmword_21F0\nmovaps [rsp+0E8h+var_D8], xmm0\nmovdqa xmm0, cs:xmmword_2200\nmovaps [rsp+0E8h+var_C8], xmm0\ntest edi, edi\njle short loc_167E\nmov ebx, edi\nmov rdx, rsi\nxor r13d, r13d\nmov r14, rsp\nlea r15, [rsp+0E8h+var_A8]\nnop word ptr [rax+rax+00000000h]\nloc_1650:\nmov ebp, [r14+r13*4]\ncmp ebp, ebx\njg short loc_1678\nmov r12, [r15+r13*8]\nnop dword ptr [rax+00h]\nloc_1660:\nmov rdi, rdx; dest\nmov rsi, r12; src\nsub ebx, ebp\ncall _strcat\nmov rdx, rax\ncmp ebx, ebp\njge short loc_1660\ntest ebx, ebx\njz short loc_167E\nloc_1678:\nadd r13, 1\njmp short loc_1650\nloc_167E:\nmov rax, [rsp+0E8h+var_40]\nsub rax, fs:28h\njnz short loc_16A3\nadd rsp, 0B8h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_16A3:\ncall ___stack_chk_fail", + "ida_pseudo": "unsigned __int64 __fastcall func0(int a1, char *a2)\n{\n int v2; // ebx\n char *v3; // rdx\n __int64 i; // r13\n int v5; // ebp\n const char *v6; // r12\n _OWORD v8[3]; // [rsp+0h] [rbp-E8h]\n int v9; // [rsp+30h] [rbp-B8h]\n _OWORD v10[6]; // [rsp+40h] [rbp-A8h]\n char *v11; // [rsp+A0h] [rbp-48h]\n unsigned __int64 v12; // [rsp+A8h] [rbp-40h]\n\n v12 = __readfsqword(0x28u);\n v9 = 1;\n *a2 = 0;\n v10[0] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_2005, (__m128i)(unsigned __int64)&unk_2004);\n v10[1] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_2008, (__m128i)(unsigned __int64)&unk_2007);\n v10[2] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_200B, (__m128i)(unsigned __int64)&unk_200A);\n v10[3] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_200E, (__m128i)(unsigned __int64)&unk_200D);\n v10[4] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_2012, (__m128i)(unsigned __int64)&unk_2011);\n v11 = \"i\";\n v10[5] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)\"v\", (__m128i)(unsigned __int64)\"iv\");\n v8[0] = _mm_load_si128((const __m128i *)&xmmword_21E0);\n v8[1] = _mm_load_si128((const __m128i *)&xmmword_21F0);\n v8[2] = _mm_load_si128((const __m128i *)&xmmword_2200);\n if ( a1 > 0 )\n {\n v2 = a1;\n v3 = a2;\n for ( i = 0LL; ; ++i )\n {\n v5 = *((_DWORD *)v8 + i);\n if ( v5 <= v2 )\n {\n v6 = (const char *)*((_QWORD *)v10 + i);\n do\n {\n v2 -= v5;\n v3 = strcat(v3, v6);\n }\n while ( v2 >= v5 );\n if ( !v2 )\n break;\n }\n }\n }\n return v12 - __readfsqword(0x28u);\n}", + "ida_strip_asm": "sub_1500:\nendbr64\npush r15\nlea rcx, unk_2005\npush r14\nmovq xmm0, rcx\nlea rcx, unk_2008\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 0B8h\nmov rax, fs:28h\nmov [rsp+0E8h+var_40], rax\nlea rax, unk_2004\nmov [rsp+0E8h+var_B8], 1\nmov byte ptr [rsi], 0\nmovq xmm1, rax\nlea rax, unk_2007\npunpcklqdq xmm0, xmm1\nmovq xmm2, rax\nlea rax, unk_200A\nmovaps [rsp+0E8h+var_A8], xmm0\nmovq xmm0, rcx\nmovq xmm3, rax\nlea rcx, unk_200B\npunpcklqdq xmm0, xmm2\nlea rax, unk_200D\nmovaps [rsp+0E8h+var_98], xmm0\nmovq xmm0, rcx\nmovq xmm4, rax\nlea rcx, unk_200E\npunpcklqdq xmm0, xmm3\nlea rax, unk_2011\nmovaps [rsp+0E8h+var_88], xmm0\nmovq xmm0, rcx\nmovq xmm5, rax\nlea rcx, unk_2012\npunpcklqdq xmm0, xmm4\nlea rax, aCmxciv+4; \"iv\"\nmovaps [rsp+0E8h+var_78], xmm0\nmovq xmm0, rcx\nmovq xmm6, rax\nlea rcx, aCmxciv+5; \"v\"\npunpcklqdq xmm0, xmm5\nlea rax, aXliii+4; \"i\"\nmovaps [rsp+0E8h+var_68], xmm0\nmovq xmm0, rcx\npunpcklqdq xmm0, xmm6\nmov [rsp+0E8h+var_48], rax\nmovaps [rsp+0E8h+var_58], xmm0\nmovdqa xmm0, cs:xmmword_21E0\nmovaps [rsp+0E8h+var_E8], xmm0\nmovdqa xmm0, cs:xmmword_21F0\nmovaps [rsp+0E8h+var_D8], xmm0\nmovdqa xmm0, cs:xmmword_2200\nmovaps [rsp+0E8h+var_C8], xmm0\ntest edi, edi\njle short loc_167E\nmov ebx, edi\nmov rdx, rsi\nxor r13d, r13d\nmov r14, rsp\nlea r15, [rsp+0E8h+var_A8]\nnop word ptr [rax+rax+00000000h]\nloc_1650:\nmov ebp, [r14+r13*4]\ncmp ebp, ebx\njg short loc_1678\nmov r12, [r15+r13*8]\nnop dword ptr [rax+00h]\nloc_1660:\nmov rdi, rdx; dest\nmov rsi, r12; src\nsub ebx, ebp\ncall _strcat\nmov rdx, rax\ncmp ebx, ebp\njge short loc_1660\ntest ebx, ebx\njz short loc_167E\nloc_1678:\nadd r13, 1\njmp short loc_1650\nloc_167E:\nmov rax, [rsp+0E8h+var_40]\nsub rax, fs:28h\njnz short loc_16A3\nadd rsp, 0B8h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_16A3:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_1500(int a1, char *a2)\n{\n int v2; // ebx\n char *v3; // rdx\n __int64 i; // r13\n int v5; // ebp\n const char *v6; // r12\n _OWORD v8[3]; // [rsp+0h] [rbp-E8h]\n int v9; // [rsp+30h] [rbp-B8h]\n _OWORD v10[6]; // [rsp+40h] [rbp-A8h]\n char *v11; // [rsp+A0h] [rbp-48h]\n unsigned __int64 v12; // [rsp+A8h] [rbp-40h]\n\n v12 = __readfsqword(0x28u);\n v9 = 1;\n *a2 = 0;\n v10[0] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_2005, (__m128i)(unsigned __int64)&unk_2004);\n v10[1] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_2008, (__m128i)(unsigned __int64)&unk_2007);\n v10[2] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_200B, (__m128i)(unsigned __int64)&unk_200A);\n v10[3] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_200E, (__m128i)(unsigned __int64)&unk_200D);\n v10[4] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_2012, (__m128i)(unsigned __int64)&unk_2011);\n v11 = \"i\";\n v10[5] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)\"v\", (__m128i)(unsigned __int64)\"iv\");\n v8[0] = _mm_load_si128((const __m128i *)&xmmword_21E0);\n v8[1] = _mm_load_si128((const __m128i *)&xmmword_21F0);\n v8[2] = _mm_load_si128((const __m128i *)&xmmword_2200);\n if ( a1 > 0 )\n {\n v2 = a1;\n v3 = a2;\n for ( i = 0LL; ; ++i )\n {\n v5 = *((_DWORD *)v8 + i);\n if ( v5 <= v2 )\n {\n v6 = (const char *)*((_QWORD *)v10 + i);\n do\n {\n v2 -= v5;\n v3 = strcat(v3, v6);\n }\n while ( v2 >= v5 );\n if ( !v2 )\n break;\n }\n }\n }\n return v12 - __readfsqword(0x28u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_1500(int a1, char *a2) {\n int v2;\n char *v3;\n long long i;\n int v5;\n const char *v6;\n long double v8[3];\n int v9;\n long double v10[6];\n char *v11;\n unsigned long long v12;\n v12 = __readfsqword(40u);\n v9 = 1;\n *a2 = 0;\n v10[0] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_2005,\n (__m128i)(unsigned long long)&unk_2004);\n v10[1] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_2008,\n (__m128i)(unsigned long long)&unk_2007);\n v10[2] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_200B,\n (__m128i)(unsigned long long)&unk_200A);\n v10[3] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_200E,\n (__m128i)(unsigned long long)&unk_200D);\n v10[4] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_2012,\n (__m128i)(unsigned long long)&unk_2011);\n v11 = \"i\";\n v10[5] = _mm_unpacklo_epi64((__m128i)(unsigned long long)\"v\",\n (__m128i)(unsigned long long)\"iv\");\n v8[0] = _mm_load_si128((const __m128i *)&xmmword_21E0);\n v8[1] = _mm_load_si128((const __m128i *)&xmmword_21F0);\n v8[2] = _mm_load_si128((const __m128i *)&xmmword_2200);\n if (a1 > 0) {\n v2 = a1;\n v3 = a2;\n for (i = 0LL;; ++i) {\n v5 = *((uint32_t *)v8 + i);\n if (v5 <= v2) {\n v6 = (const char *)*((uint64_t *)v10 + i);\n do {\n v2 -= v5;\n v3 = strcat(v3, v6);\n } while (v2 >= v5);\n if (!v2) break;\n }\n }\n }\n return v12 - __readfsqword(40u);\n}", + "ida_pseudo_norm": "unsigned long long func0(int a1, char *a2) {\n int v2;\n char *v3;\n long long i;\n int v5;\n const char *v6;\n long double v8[3];\n int v9;\n long double v10[6];\n char *v11;\n unsigned long long v12;\n v12 = __readfsqword(40u);\n v9 = 1;\n *a2 = 0;\n v10[0] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_2005,\n (__m128i)(unsigned long long)&unk_2004);\n v10[1] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_2008,\n (__m128i)(unsigned long long)&unk_2007);\n v10[2] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_200B,\n (__m128i)(unsigned long long)&unk_200A);\n v10[3] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_200E,\n (__m128i)(unsigned long long)&unk_200D);\n v10[4] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_2012,\n (__m128i)(unsigned long long)&unk_2011);\n v11 = \"i\";\n v10[5] = _mm_unpacklo_epi64((__m128i)(unsigned long long)\"v\",\n (__m128i)(unsigned long long)\"iv\");\n v8[0] = _mm_load_si128((const __m128i *)&xmmword_21E0);\n v8[1] = _mm_load_si128((const __m128i *)&xmmword_21F0);\n v8[2] = _mm_load_si128((const __m128i *)&xmmword_2200);\n if (a1 > 0) {\n v2 = a1;\n v3 = a2;\n for (i = 0LL;; ++i) {\n v5 = *((uint32_t *)v8 + i);\n if (v5 <= v2) {\n v6 = (const char *)*((uint64_t *)v10 + i);\n do {\n v2 -= v5;\n v3 = strcat(v3, v6);\n } while (v2 >= v5);\n if (!v2) break;\n }\n }\n }\n return v12 - __readfsqword(40u);\n}" + }, + { + "index": "HumanEval-C-156", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "void func0(int number, char *result) {\n const char *rep[] = {\"m\", \"cm\", \"d\", \"cd\", \"c\", \"xc\", \"l\",\n \"xl\", \"x\", \"ix\", \"v\", \"iv\", \"i\"};\n const int num[] = {1000, 900, 500, 400, 100, 90, 50, 40, 10, 9, 5, 4, 1};\n int pos = 0;\n result[0] = '\\0';\n while (number > 0) {\n while (number >= num[pos]) {\n strcat(result, rep[pos]);\n number -= num[pos];\n }\n if (number > 0) pos++;\n }\n}", + "test": "#include \n#include \n\nint main() {\n char result[64]; // Buffer large enough for all Roman numeral representations of numbers 1-1000\n\n func0(19, result);\n assert(strcmp(result, \"xix\") == 0);\n\n func0(152, result);\n assert(strcmp(result, \"clii\") == 0);\n\n func0(251, result);\n assert(strcmp(result, \"ccli\") == 0);\n\n func0(426, result);\n assert(strcmp(result, \"cdxxvi\") == 0);\n\n func0(500, result);\n assert(strcmp(result, \"d\") == 0);\n\n func0(1, result);\n assert(strcmp(result, \"i\") == 0);\n\n func0(4, result);\n assert(strcmp(result, \"iv\") == 0);\n\n func0(43, result);\n assert(strcmp(result, \"xliii\") == 0);\n\n func0(90, result);\n assert(strcmp(result, \"xc\") == 0);\n\n func0(94, result);\n assert(strcmp(result, \"xciv\") == 0);\n\n func0(532, result);\n assert(strcmp(result, \"dxxxii\") == 0);\n\n func0(900, result);\n assert(strcmp(result, \"cm\") == 0);\n\n func0(994, result);\n assert(strcmp(result, \"cmxciv\") == 0);\n\n func0(1000, result);\n assert(strcmp(result, \"m\") == 0);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\nlea rcx, unk_2005\npush r14\nmovq xmm0, rcx\nlea rcx, unk_2008\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 0B8h\nmov rax, fs:28h\nmov [rsp+0E8h+var_40], rax\nlea rax, unk_2004\nmov [rsp+0E8h+var_B8], 1\nmov byte ptr [rsi], 0\nmovq xmm1, rax\nlea rax, unk_2007\npunpcklqdq xmm0, xmm1\nmovq xmm2, rax\nlea rax, unk_200A\nmovaps [rsp+0E8h+var_A8], xmm0\nmovq xmm0, rcx\nmovq xmm3, rax\nlea rcx, unk_200B\npunpcklqdq xmm0, xmm2\nlea rax, unk_200D\nmovaps [rsp+0E8h+var_98], xmm0\nmovq xmm0, rcx\nmovq xmm4, rax\nlea rcx, unk_200E\npunpcklqdq xmm0, xmm3\nlea rax, unk_2011\nmovaps [rsp+0E8h+var_88], xmm0\nmovq xmm0, rcx\nmovq xmm5, rax\nlea rcx, unk_2012\npunpcklqdq xmm0, xmm4\nlea rax, aCmxciv+4; \"iv\"\nmovaps [rsp+0E8h+var_78], xmm0\nmovq xmm0, rcx\nmovq xmm6, rax\nlea rcx, aCmxciv+5; \"v\"\npunpcklqdq xmm0, xmm5\nlea rax, aXliii+4; \"i\"\nmovaps [rsp+0E8h+var_68], xmm0\nmovq xmm0, rcx\npunpcklqdq xmm0, xmm6\nmov [rsp+0E8h+var_48], rax\nmovaps [rsp+0E8h+var_58], xmm0\nmovdqa xmm0, cs:xmmword_21E0\nmovaps [rsp+0E8h+var_E8], xmm0\nmovdqa xmm0, cs:xmmword_21F0\nmovaps [rsp+0E8h+var_D8], xmm0\nmovdqa xmm0, cs:xmmword_2200\nmovaps [rsp+0E8h+var_C8], xmm0\ntest edi, edi\njle short loc_167E\nmov ebx, edi\nmov rdx, rsi\nxor r13d, r13d\nmov r14, rsp\nlea r15, [rsp+0E8h+var_A8]\nnop word ptr [rax+rax+00000000h]\nloc_1650:\nmov ebp, [r14+r13*4]\ncmp ebp, ebx\njg short loc_1678\nmov r12, [r15+r13*8]\nnop dword ptr [rax+00h]\nloc_1660:\nmov rdi, rdx; dest\nmov rsi, r12; src\nsub ebx, ebp\ncall _strcat\nmov rdx, rax\ncmp ebx, ebp\njge short loc_1660\ntest ebx, ebx\njz short loc_167E\nloc_1678:\nadd r13, 1\njmp short loc_1650\nloc_167E:\nmov rax, [rsp+0E8h+var_40]\nsub rax, fs:28h\njnz short loc_16A3\nadd rsp, 0B8h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_16A3:\ncall ___stack_chk_fail", + "ida_pseudo": "unsigned __int64 __fastcall func0(int a1, char *a2)\n{\n int v2; // ebx\n char *v3; // rdx\n __int64 i; // r13\n int v5; // ebp\n const char *v6; // r12\n _OWORD v8[3]; // [rsp+0h] [rbp-E8h]\n int v9; // [rsp+30h] [rbp-B8h]\n _OWORD v10[6]; // [rsp+40h] [rbp-A8h]\n char *v11; // [rsp+A0h] [rbp-48h]\n unsigned __int64 v12; // [rsp+A8h] [rbp-40h]\n\n v12 = __readfsqword(0x28u);\n v9 = 1;\n *a2 = 0;\n v10[0] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_2005, (__m128i)(unsigned __int64)&unk_2004);\n v10[1] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_2008, (__m128i)(unsigned __int64)&unk_2007);\n v10[2] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_200B, (__m128i)(unsigned __int64)&unk_200A);\n v10[3] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_200E, (__m128i)(unsigned __int64)&unk_200D);\n v10[4] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_2012, (__m128i)(unsigned __int64)&unk_2011);\n v11 = \"i\";\n v10[5] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)\"v\", (__m128i)(unsigned __int64)\"iv\");\n v8[0] = _mm_load_si128((const __m128i *)&xmmword_21E0);\n v8[1] = _mm_load_si128((const __m128i *)&xmmword_21F0);\n v8[2] = _mm_load_si128((const __m128i *)&xmmword_2200);\n if ( a1 > 0 )\n {\n v2 = a1;\n v3 = a2;\n for ( i = 0LL; ; ++i )\n {\n v5 = *((_DWORD *)v8 + i);\n if ( v5 <= v2 )\n {\n v6 = (const char *)*((_QWORD *)v10 + i);\n do\n {\n v2 -= v5;\n v3 = strcat(v3, v6);\n }\n while ( v2 >= v5 );\n if ( !v2 )\n break;\n }\n }\n }\n return v12 - __readfsqword(0x28u);\n}", + "ida_strip_asm": "sub_1500:\nendbr64\npush r15\nlea rcx, unk_2005\npush r14\nmovq xmm0, rcx\nlea rcx, unk_2008\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 0B8h\nmov rax, fs:28h\nmov [rsp+0E8h+var_40], rax\nlea rax, unk_2004\nmov [rsp+0E8h+var_B8], 1\nmov byte ptr [rsi], 0\nmovq xmm1, rax\nlea rax, unk_2007\npunpcklqdq xmm0, xmm1\nmovq xmm2, rax\nlea rax, unk_200A\nmovaps [rsp+0E8h+var_A8], xmm0\nmovq xmm0, rcx\nmovq xmm3, rax\nlea rcx, unk_200B\npunpcklqdq xmm0, xmm2\nlea rax, unk_200D\nmovaps [rsp+0E8h+var_98], xmm0\nmovq xmm0, rcx\nmovq xmm4, rax\nlea rcx, unk_200E\npunpcklqdq xmm0, xmm3\nlea rax, unk_2011\nmovaps [rsp+0E8h+var_88], xmm0\nmovq xmm0, rcx\nmovq xmm5, rax\nlea rcx, unk_2012\npunpcklqdq xmm0, xmm4\nlea rax, aCmxciv+4; \"iv\"\nmovaps [rsp+0E8h+var_78], xmm0\nmovq xmm0, rcx\nmovq xmm6, rax\nlea rcx, aCmxciv+5; \"v\"\npunpcklqdq xmm0, xmm5\nlea rax, aXliii+4; \"i\"\nmovaps [rsp+0E8h+var_68], xmm0\nmovq xmm0, rcx\npunpcklqdq xmm0, xmm6\nmov [rsp+0E8h+var_48], rax\nmovaps [rsp+0E8h+var_58], xmm0\nmovdqa xmm0, cs:xmmword_21E0\nmovaps [rsp+0E8h+var_E8], xmm0\nmovdqa xmm0, cs:xmmword_21F0\nmovaps [rsp+0E8h+var_D8], xmm0\nmovdqa xmm0, cs:xmmword_2200\nmovaps [rsp+0E8h+var_C8], xmm0\ntest edi, edi\njle short loc_167E\nmov ebx, edi\nmov rdx, rsi\nxor r13d, r13d\nmov r14, rsp\nlea r15, [rsp+0E8h+var_A8]\nnop word ptr [rax+rax+00000000h]\nloc_1650:\nmov ebp, [r14+r13*4]\ncmp ebp, ebx\njg short loc_1678\nmov r12, [r15+r13*8]\nnop dword ptr [rax+00h]\nloc_1660:\nmov rdi, rdx; dest\nmov rsi, r12; src\nsub ebx, ebp\ncall _strcat\nmov rdx, rax\ncmp ebx, ebp\njge short loc_1660\ntest ebx, ebx\njz short loc_167E\nloc_1678:\nadd r13, 1\njmp short loc_1650\nloc_167E:\nmov rax, [rsp+0E8h+var_40]\nsub rax, fs:28h\njnz short loc_16A3\nadd rsp, 0B8h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_16A3:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_1500(int a1, char *a2)\n{\n int v2; // ebx\n char *v3; // rdx\n __int64 i; // r13\n int v5; // ebp\n const char *v6; // r12\n _OWORD v8[3]; // [rsp+0h] [rbp-E8h]\n int v9; // [rsp+30h] [rbp-B8h]\n _OWORD v10[6]; // [rsp+40h] [rbp-A8h]\n char *v11; // [rsp+A0h] [rbp-48h]\n unsigned __int64 v12; // [rsp+A8h] [rbp-40h]\n\n v12 = __readfsqword(0x28u);\n v9 = 1;\n *a2 = 0;\n v10[0] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_2005, (__m128i)(unsigned __int64)&unk_2004);\n v10[1] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_2008, (__m128i)(unsigned __int64)&unk_2007);\n v10[2] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_200B, (__m128i)(unsigned __int64)&unk_200A);\n v10[3] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_200E, (__m128i)(unsigned __int64)&unk_200D);\n v10[4] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_2012, (__m128i)(unsigned __int64)&unk_2011);\n v11 = \"i\";\n v10[5] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)\"v\", (__m128i)(unsigned __int64)\"iv\");\n v8[0] = _mm_load_si128((const __m128i *)&xmmword_21E0);\n v8[1] = _mm_load_si128((const __m128i *)&xmmword_21F0);\n v8[2] = _mm_load_si128((const __m128i *)&xmmword_2200);\n if ( a1 > 0 )\n {\n v2 = a1;\n v3 = a2;\n for ( i = 0LL; ; ++i )\n {\n v5 = *((_DWORD *)v8 + i);\n if ( v5 <= v2 )\n {\n v6 = (const char *)*((_QWORD *)v10 + i);\n do\n {\n v2 -= v5;\n v3 = strcat(v3, v6);\n }\n while ( v2 >= v5 );\n if ( !v2 )\n break;\n }\n }\n }\n return v12 - __readfsqword(0x28u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_1500(int a1, char *a2) {\n int v2;\n char *v3;\n long long i;\n int v5;\n const char *v6;\n long double v8[3];\n int v9;\n long double v10[6];\n char *v11;\n unsigned long long v12;\n v12 = __readfsqword(40u);\n v9 = 1;\n *a2 = 0;\n v10[0] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_2005,\n (__m128i)(unsigned long long)&unk_2004);\n v10[1] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_2008,\n (__m128i)(unsigned long long)&unk_2007);\n v10[2] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_200B,\n (__m128i)(unsigned long long)&unk_200A);\n v10[3] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_200E,\n (__m128i)(unsigned long long)&unk_200D);\n v10[4] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_2012,\n (__m128i)(unsigned long long)&unk_2011);\n v11 = \"i\";\n v10[5] = _mm_unpacklo_epi64((__m128i)(unsigned long long)\"v\",\n (__m128i)(unsigned long long)\"iv\");\n v8[0] = _mm_load_si128((const __m128i *)&xmmword_21E0);\n v8[1] = _mm_load_si128((const __m128i *)&xmmword_21F0);\n v8[2] = _mm_load_si128((const __m128i *)&xmmword_2200);\n if (a1 > 0) {\n v2 = a1;\n v3 = a2;\n for (i = 0LL;; ++i) {\n v5 = *((uint32_t *)v8 + i);\n if (v5 <= v2) {\n v6 = (const char *)*((uint64_t *)v10 + i);\n do {\n v2 -= v5;\n v3 = strcat(v3, v6);\n } while (v2 >= v5);\n if (!v2) break;\n }\n }\n }\n return v12 - __readfsqword(40u);\n}", + "ida_pseudo_norm": "unsigned long long func0(int a1, char *a2) {\n int v2;\n char *v3;\n long long i;\n int v5;\n const char *v6;\n long double v8[3];\n int v9;\n long double v10[6];\n char *v11;\n unsigned long long v12;\n v12 = __readfsqword(40u);\n v9 = 1;\n *a2 = 0;\n v10[0] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_2005,\n (__m128i)(unsigned long long)&unk_2004);\n v10[1] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_2008,\n (__m128i)(unsigned long long)&unk_2007);\n v10[2] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_200B,\n (__m128i)(unsigned long long)&unk_200A);\n v10[3] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_200E,\n (__m128i)(unsigned long long)&unk_200D);\n v10[4] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_2012,\n (__m128i)(unsigned long long)&unk_2011);\n v11 = \"i\";\n v10[5] = _mm_unpacklo_epi64((__m128i)(unsigned long long)\"v\",\n (__m128i)(unsigned long long)\"iv\");\n v8[0] = _mm_load_si128((const __m128i *)&xmmword_21E0);\n v8[1] = _mm_load_si128((const __m128i *)&xmmword_21F0);\n v8[2] = _mm_load_si128((const __m128i *)&xmmword_2200);\n if (a1 > 0) {\n v2 = a1;\n v3 = a2;\n for (i = 0LL;; ++i) {\n v5 = *((uint32_t *)v8 + i);\n if (v5 <= v2) {\n v6 = (const char *)*((uint64_t *)v10 + i);\n do {\n v2 -= v5;\n v3 = strcat(v3, v6);\n } while (v2 >= v5);\n if (!v2) break;\n }\n }\n }\n return v12 - __readfsqword(40u);\n}" + }, + { + "index": "HumanEval-C-157", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "int func0(float a, float b, float c) {\n if (fabs(a * a + b * b - c * c) < 1e-4 ||\n fabs(a * a + c * c - b * b) < 1e-4 || fabs(b * b + c * c - a * a) < 1e-4)\n return 1;\n return 0;\n}", + "test": "#include \n\nint main() {\n assert(func0(3, 4, 5) == 1);\n assert(func0(1, 2, 3) == 0);\n assert(func0(10, 6, 8) == 1);\n assert(func0(2, 2, 2) == 0);\n assert(func0(7, 24, 25) == 1);\n assert(func0(10, 5, 7) == 0);\n assert(func0(5, 12, 13) == 1);\n assert(func0(15, 8, 17) == 1);\n assert(func0(48, 55, 73) == 1);\n assert(func0(1, 1, 1) == 0);\n assert(func0(2, 2, 10) == 0);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmovss [rbp+var_4], xmm0\nmovss [rbp+var_8], xmm1\nmovss [rbp+var_C], xmm2\nmovss xmm0, [rbp+var_4]\nmovaps xmm1, xmm0\nmulss xmm1, xmm0\nmovss xmm0, [rbp+var_8]\nmulss xmm0, xmm0\naddss xmm1, xmm0\nmovss xmm0, [rbp+var_C]\nmovaps xmm2, xmm0\nmulss xmm2, xmm0\nsubss xmm1, xmm2\nmovaps xmm0, xmm1\nmovss xmm1, cs:dword_2120\nandps xmm0, xmm1\npxor xmm1, xmm1\ncvtss2sd xmm1, xmm0\nmovsd xmm0, cs:qword_2130\ncomisd xmm0, xmm1\nja loc_124B\nmovss xmm0, [rbp+var_4]\nmovaps xmm1, xmm0\nmulss xmm1, xmm0\nmovss xmm0, [rbp+var_C]\nmulss xmm0, xmm0\naddss xmm1, xmm0\nmovss xmm0, [rbp+var_8]\nmovaps xmm2, xmm0\nmulss xmm2, xmm0\nsubss xmm1, xmm2\nmovaps xmm0, xmm1\nmovss xmm1, cs:dword_2120\nandps xmm0, xmm1\npxor xmm1, xmm1\ncvtss2sd xmm1, xmm0\nmovsd xmm0, cs:qword_2130\ncomisd xmm0, xmm1\nja short loc_124B\nmovss xmm0, [rbp+var_8]\nmovaps xmm1, xmm0\nmulss xmm1, xmm0\nmovss xmm0, [rbp+var_C]\nmulss xmm0, xmm0\naddss xmm1, xmm0\nmovss xmm0, [rbp+var_4]\nmovaps xmm2, xmm0\nmulss xmm2, xmm0\nsubss xmm1, xmm2\nmovaps xmm0, xmm1\nmovss xmm1, cs:dword_2120\nandps xmm0, xmm1\npxor xmm1, xmm1\ncvtss2sd xmm1, xmm0\nmovsd xmm0, cs:qword_2130\ncomisd xmm0, xmm1\njbe short loc_1252\nloc_124B:\nmov eax, 1\njmp short loc_1257\nloc_1252:\nmov eax, 0\nloc_1257:\npop rbp\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(float a1, float a2, float a3)\n{\n return fabs((float)((float)(a1 * a1) + (float)(a2 * a2)) - (float)(a3 * a3)) < 0.0001\n || fabs((float)((float)(a1 * a1) + (float)(a3 * a3)) - (float)(a2 * a2)) < 0.0001\n || fabs((float)((float)(a2 * a2) + (float)(a3 * a3)) - (float)(a1 * a1)) < 0.0001;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmovss [rbp+var_4], xmm0\nmovss [rbp+var_8], xmm1\nmovss [rbp+var_C], xmm2\nmovss xmm0, [rbp+var_4]\nmovaps xmm1, xmm0\nmulss xmm1, xmm0\nmovss xmm0, [rbp+var_8]\nmulss xmm0, xmm0\naddss xmm1, xmm0\nmovss xmm0, [rbp+var_C]\nmovaps xmm2, xmm0\nmulss xmm2, xmm0\nsubss xmm1, xmm2\nmovaps xmm0, xmm1\nmovss xmm1, cs:dword_2120\nandps xmm0, xmm1\npxor xmm1, xmm1\ncvtss2sd xmm1, xmm0\nmovsd xmm0, cs:qword_2130\ncomisd xmm0, xmm1\nja loc_124B\nmovss xmm0, [rbp+var_4]\nmovaps xmm1, xmm0\nmulss xmm1, xmm0\nmovss xmm0, [rbp+var_C]\nmulss xmm0, xmm0\naddss xmm1, xmm0\nmovss xmm0, [rbp+var_8]\nmovaps xmm2, xmm0\nmulss xmm2, xmm0\nsubss xmm1, xmm2\nmovaps xmm0, xmm1\nmovss xmm1, cs:dword_2120\nandps xmm0, xmm1\npxor xmm1, xmm1\ncvtss2sd xmm1, xmm0\nmovsd xmm0, cs:qword_2130\ncomisd xmm0, xmm1\nja short loc_124B\nmovss xmm0, [rbp+var_8]\nmovaps xmm1, xmm0\nmulss xmm1, xmm0\nmovss xmm0, [rbp+var_C]\nmulss xmm0, xmm0\naddss xmm1, xmm0\nmovss xmm0, [rbp+var_4]\nmovaps xmm2, xmm0\nmulss xmm2, xmm0\nsubss xmm1, xmm2\nmovaps xmm0, xmm1\nmovss xmm1, cs:dword_2120\nandps xmm0, xmm1\npxor xmm1, xmm1\ncvtss2sd xmm1, xmm0\nmovsd xmm0, cs:qword_2130\ncomisd xmm0, xmm1\njbe short loc_1252\nloc_124B:\nmov eax, 1\njmp short loc_1257\nloc_1252:\nmov eax, 0\nloc_1257:\npop rbp\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1149(float a1, float a2, float a3)\n{\n return fabs((float)((float)(a1 * a1) + (float)(a2 * a2)) - (float)(a3 * a3)) < 0.0001\n || fabs((float)((float)(a1 * a1) + (float)(a3 * a3)) - (float)(a2 * a2)) < 0.0001\n || fabs((float)((float)(a2 * a2) + (float)(a3 * a3)) - (float)(a1 * a1)) < 0.0001;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1149(float a1, float a2, float a3) {\n return fabs((float)((float)(a1 * a1) + (float)(a2 * a2)) - (float)(a3 * a3)) <\n 0.0001 ||\n fabs((float)((float)(a1 * a1) + (float)(a3 * a3)) - (float)(a2 * a2)) <\n 0.0001 ||\n fabs((float)((float)(a2 * a2) + (float)(a3 * a3)) - (float)(a1 * a1)) <\n 0.0001;\n}", + "ida_pseudo_norm": "uint8_t func0(float a1, float a2, float a3) {\n return fabs((float)((float)(a1 * a1) + (float)(a2 * a2)) - (float)(a3 * a3)) <\n 0.0001 ||\n fabs((float)((float)(a1 * a1) + (float)(a3 * a3)) - (float)(a2 * a2)) <\n 0.0001 ||\n fabs((float)((float)(a2 * a2) + (float)(a3 * a3)) - (float)(a1 * a1)) <\n 0.0001;\n}" + }, + { + "index": "HumanEval-C-158", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "char *func0(char *words[], int count) {\n char *max = \"\";\n int maxu = 0;\n for (int i = 0; i < count; i++) {\n char unique[256] = {0};\n int unique_count = 0;\n for (int j = 0; words[i][j] != '\\0'; j++) {\n if (!strchr(unique, words[i][j])) {\n int len = strlen(unique);\n unique[len] = words[i][j];\n unique[len + 1] = '\\0';\n unique_count++;\n }\n }\n if (unique_count > maxu ||\n (unique_count == maxu && strcmp(words[i], max) < 0)) {\n max = words[i];\n maxu = unique_count;\n }\n }\n return max;\n}", + "test": "#include \n#include \n\nint main() {\n char *words1[] = {\"name\", \"of\", \"string\"};\n assert(strcmp(func0(words1, 3), \"string\") == 0);\n\n char *words2[] = {\"name\", \"enam\", \"game\"};\n assert(strcmp(func0(words2, 3), \"enam\") == 0);\n\n char *words3[] = {\"aaaaaaa\", \"bb\", \"cc\"};\n assert(strcmp(func0(words3, 3), \"aaaaaaa\") == 0);\n\n char *words4[] = {\"abc\", \"cba\"};\n assert(strcmp(func0(words4, 2), \"abc\") == 0);\n\n char *words5[] = {\"play\", \"this\", \"game\", \"of\", \"footbott\"};\n assert(strcmp(func0(words5, 5), \"footbott\") == 0);\n\n char *words6[] = {\"we\", \"are\", \"gonna\", \"rock\"};\n assert(strcmp(func0(words6, 4), \"gonna\") == 0);\n\n char *words7[] = {\"we\", \"are\", \"a\", \"mad\", \"nation\"};\n assert(strcmp(func0(words7, 5), \"nation\") == 0);\n\n char *words8[] = {\"this\", \"is\", \"a\", \"prrk\"};\n assert(strcmp(func0(words8, 4), \"this\") == 0);\n\n char *words9[] = {\"b\"};\n assert(strcmp(func0(words9, 1), \"b\") == 0);\n\n char *words10[] = {\"play\", \"play\", \"play\"};\n assert(strcmp(func0(words10, 3), \"play\") == 0);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 140h\nmov [rbp+var_138], rdi\nmov [rbp+var_13C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, unk_2008\nmov [rbp+s2], rax\nmov [rbp+var_12C], 0\nmov [rbp+var_128], 0\njmp loc_14D7\nloc_121B:\nmov qword ptr [rbp+s], 0\nmov [rbp+var_108], 0\nmov [rbp+var_100], 0\nmov [rbp+var_F8], 0\nmov [rbp+var_F0], 0\nmov [rbp+var_E8], 0\nmov [rbp+var_E0], 0\nmov [rbp+var_D8], 0\nmov [rbp+var_D0], 0\nmov [rbp+var_C8], 0\nmov [rbp+var_C0], 0\nmov [rbp+var_B8], 0\nmov [rbp+var_B0], 0\nmov [rbp+var_A8], 0\nmov [rbp+var_A0], 0\nmov [rbp+var_98], 0\nmov [rbp+var_90], 0\nmov [rbp+var_88], 0\nmov [rbp+var_80], 0\nmov [rbp+var_78], 0\nmov [rbp+var_70], 0\nmov [rbp+var_68], 0\nmov [rbp+var_60], 0\nmov [rbp+var_58], 0\nmov [rbp+var_50], 0\nmov [rbp+var_48], 0\nmov [rbp+var_40], 0\nmov [rbp+var_38], 0\nmov [rbp+var_30], 0\nmov [rbp+var_28], 0\nmov [rbp+var_20], 0\nmov [rbp+var_18], 0\nmov [rbp+var_124], 0\nmov [rbp+var_120], 0\njmp loc_141E\nloc_136A:\nmov eax, [rbp+var_128]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_138]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_120]\ncdqe\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx edx, al\nlea rax, [rbp+s]\nmov esi, edx; c\nmov rdi, rax; s\ncall _strchr\ntest rax, rax\njnz short loc_1417\nlea rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_11C], eax\nmov eax, [rbp+var_128]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_138]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_120]\ncdqe\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_11C]\ncdqe\nmov [rbp+rax+s], dl\nmov eax, [rbp+var_11C]\nadd eax, 1\ncdqe\nmov [rbp+rax+s], 0\nadd [rbp+var_124], 1\nloc_1417:\nadd [rbp+var_120], 1\nloc_141E:\nmov eax, [rbp+var_128]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_138]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_120]\ncdqe\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_136A\nmov eax, [rbp+var_124]\ncmp eax, [rbp+var_12C]\njg short loc_14A0\nmov eax, [rbp+var_124]\ncmp eax, [rbp+var_12C]\njnz short loc_14D0\nmov eax, [rbp+var_128]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_138]\nadd rax, rdx\nmov rax, [rax]\nmov rdx, [rbp+s2]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njns short loc_14D0\nloc_14A0:\nmov eax, [rbp+var_128]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_138]\nadd rax, rdx\nmov rax, [rax]\nmov [rbp+s2], rax\nmov eax, [rbp+var_124]\nmov [rbp+var_12C], eax\nloc_14D0:\nadd [rbp+var_128], 1\nloc_14D7:\nmov eax, [rbp+var_128]\ncmp eax, [rbp+var_13C]\njl loc_121B\nmov rax, [rbp+s2]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1504\ncall ___stack_chk_fail\nlocret_1504:\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2)\n{\n int v3; // [rsp+14h] [rbp-12Ch]\n int i; // [rsp+18h] [rbp-128h]\n int v5; // [rsp+1Ch] [rbp-124h]\n int j; // [rsp+20h] [rbp-120h]\n int v7; // [rsp+24h] [rbp-11Ch]\n char *s2; // [rsp+28h] [rbp-118h]\n char s[8]; // [rsp+30h] [rbp-110h] BYREF\n __int64 v10; // [rsp+38h] [rbp-108h]\n __int64 v11; // [rsp+40h] [rbp-100h]\n __int64 v12; // [rsp+48h] [rbp-F8h]\n __int64 v13; // [rsp+50h] [rbp-F0h]\n __int64 v14; // [rsp+58h] [rbp-E8h]\n __int64 v15; // [rsp+60h] [rbp-E0h]\n __int64 v16; // [rsp+68h] [rbp-D8h]\n __int64 v17; // [rsp+70h] [rbp-D0h]\n __int64 v18; // [rsp+78h] [rbp-C8h]\n __int64 v19; // [rsp+80h] [rbp-C0h]\n __int64 v20; // [rsp+88h] [rbp-B8h]\n __int64 v21; // [rsp+90h] [rbp-B0h]\n __int64 v22; // [rsp+98h] [rbp-A8h]\n __int64 v23; // [rsp+A0h] [rbp-A0h]\n __int64 v24; // [rsp+A8h] [rbp-98h]\n __int64 v25; // [rsp+B0h] [rbp-90h]\n __int64 v26; // [rsp+B8h] [rbp-88h]\n __int64 v27; // [rsp+C0h] [rbp-80h]\n __int64 v28; // [rsp+C8h] [rbp-78h]\n __int64 v29; // [rsp+D0h] [rbp-70h]\n __int64 v30; // [rsp+D8h] [rbp-68h]\n __int64 v31; // [rsp+E0h] [rbp-60h]\n __int64 v32; // [rsp+E8h] [rbp-58h]\n __int64 v33; // [rsp+F0h] [rbp-50h]\n __int64 v34; // [rsp+F8h] [rbp-48h]\n __int64 v35; // [rsp+100h] [rbp-40h]\n __int64 v36; // [rsp+108h] [rbp-38h]\n __int64 v37; // [rsp+110h] [rbp-30h]\n __int64 v38; // [rsp+118h] [rbp-28h]\n __int64 v39; // [rsp+120h] [rbp-20h]\n __int64 v40; // [rsp+128h] [rbp-18h]\n unsigned __int64 v41; // [rsp+138h] [rbp-8h]\n\n v41 = __readfsqword(0x28u);\n s2 = (char *)&unk_2008;\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n *(_QWORD *)s = 0LL;\n v10 = 0LL;\n v11 = 0LL;\n v12 = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0LL;\n v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n v22 = 0LL;\n v23 = 0LL;\n v24 = 0LL;\n v25 = 0LL;\n v26 = 0LL;\n v27 = 0LL;\n v28 = 0LL;\n v29 = 0LL;\n v30 = 0LL;\n v31 = 0LL;\n v32 = 0LL;\n v33 = 0LL;\n v34 = 0LL;\n v35 = 0LL;\n v36 = 0LL;\n v37 = 0LL;\n v38 = 0LL;\n v39 = 0LL;\n v40 = 0LL;\n v5 = 0;\n for ( j = 0; *(_BYTE *)(*(_QWORD *)(8LL * i + a1) + j); ++j )\n {\n if ( !strchr(s, *(char *)(*(_QWORD *)(8LL * i + a1) + j)) )\n {\n v7 = strlen(s);\n s[v7] = *(_BYTE *)(*(_QWORD *)(8LL * i + a1) + j);\n s[v7 + 1] = 0;\n ++v5;\n }\n }\n if ( v5 > v3 || v5 == v3 && strcmp(*(const char **)(8LL * i + a1), s2) < 0 )\n {\n s2 = *(char **)(8LL * i + a1);\n v3 = v5;\n }\n }\n return s2;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 140h\nmov [rbp+var_138], rdi\nmov [rbp+var_13C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, unk_2008\nmov [rbp+s2], rax\nmov [rbp+var_12C], 0\nmov [rbp+var_128], 0\njmp loc_14D7\nloc_121B:\nmov qword ptr [rbp+s], 0\nmov [rbp+var_108], 0\nmov [rbp+var_100], 0\nmov [rbp+var_F8], 0\nmov [rbp+var_F0], 0\nmov [rbp+var_E8], 0\nmov [rbp+var_E0], 0\nmov [rbp+var_D8], 0\nmov [rbp+var_D0], 0\nmov [rbp+var_C8], 0\nmov [rbp+var_C0], 0\nmov [rbp+var_B8], 0\nmov [rbp+var_B0], 0\nmov [rbp+var_A8], 0\nmov [rbp+var_A0], 0\nmov [rbp+var_98], 0\nmov [rbp+var_90], 0\nmov [rbp+var_88], 0\nmov [rbp+var_80], 0\nmov [rbp+var_78], 0\nmov [rbp+var_70], 0\nmov [rbp+var_68], 0\nmov [rbp+var_60], 0\nmov [rbp+var_58], 0\nmov [rbp+var_50], 0\nmov [rbp+var_48], 0\nmov [rbp+var_40], 0\nmov [rbp+var_38], 0\nmov [rbp+var_30], 0\nmov [rbp+var_28], 0\nmov [rbp+var_20], 0\nmov [rbp+var_18], 0\nmov [rbp+var_124], 0\nmov [rbp+var_120], 0\njmp loc_141E\nloc_136A:\nmov eax, [rbp+var_128]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_138]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_120]\ncdqe\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx edx, al\nlea rax, [rbp+s]\nmov esi, edx; c\nmov rdi, rax; s\ncall _strchr\ntest rax, rax\njnz short loc_1417\nlea rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_11C], eax\nmov eax, [rbp+var_128]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_138]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_120]\ncdqe\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_11C]\ncdqe\nmov [rbp+rax+s], dl\nmov eax, [rbp+var_11C]\nadd eax, 1\ncdqe\nmov [rbp+rax+s], 0\nadd [rbp+var_124], 1\nloc_1417:\nadd [rbp+var_120], 1\nloc_141E:\nmov eax, [rbp+var_128]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_138]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_120]\ncdqe\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_136A\nmov eax, [rbp+var_124]\ncmp eax, [rbp+var_12C]\njg short loc_14A0\nmov eax, [rbp+var_124]\ncmp eax, [rbp+var_12C]\njnz short loc_14D0\nmov eax, [rbp+var_128]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_138]\nadd rax, rdx\nmov rax, [rax]\nmov rdx, [rbp+s2]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njns short loc_14D0\nloc_14A0:\nmov eax, [rbp+var_128]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_138]\nadd rax, rdx\nmov rax, [rax]\nmov [rbp+s2], rax\nmov eax, [rbp+var_124]\nmov [rbp+var_12C], eax\nloc_14D0:\nadd [rbp+var_128], 1\nloc_14D7:\nmov eax, [rbp+var_128]\ncmp eax, [rbp+var_13C]\njl loc_121B\nmov rax, [rbp+s2]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1504\ncall ___stack_chk_fail\nlocret_1504:\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11C9(__int64 a1, int a2)\n{\n int v3; // [rsp+14h] [rbp-12Ch]\n int i; // [rsp+18h] [rbp-128h]\n int v5; // [rsp+1Ch] [rbp-124h]\n int j; // [rsp+20h] [rbp-120h]\n int v7; // [rsp+24h] [rbp-11Ch]\n char *s2; // [rsp+28h] [rbp-118h]\n char s[8]; // [rsp+30h] [rbp-110h] BYREF\n __int64 v10; // [rsp+38h] [rbp-108h]\n __int64 v11; // [rsp+40h] [rbp-100h]\n __int64 v12; // [rsp+48h] [rbp-F8h]\n __int64 v13; // [rsp+50h] [rbp-F0h]\n __int64 v14; // [rsp+58h] [rbp-E8h]\n __int64 v15; // [rsp+60h] [rbp-E0h]\n __int64 v16; // [rsp+68h] [rbp-D8h]\n __int64 v17; // [rsp+70h] [rbp-D0h]\n __int64 v18; // [rsp+78h] [rbp-C8h]\n __int64 v19; // [rsp+80h] [rbp-C0h]\n __int64 v20; // [rsp+88h] [rbp-B8h]\n __int64 v21; // [rsp+90h] [rbp-B0h]\n __int64 v22; // [rsp+98h] [rbp-A8h]\n __int64 v23; // [rsp+A0h] [rbp-A0h]\n __int64 v24; // [rsp+A8h] [rbp-98h]\n __int64 v25; // [rsp+B0h] [rbp-90h]\n __int64 v26; // [rsp+B8h] [rbp-88h]\n __int64 v27; // [rsp+C0h] [rbp-80h]\n __int64 v28; // [rsp+C8h] [rbp-78h]\n __int64 v29; // [rsp+D0h] [rbp-70h]\n __int64 v30; // [rsp+D8h] [rbp-68h]\n __int64 v31; // [rsp+E0h] [rbp-60h]\n __int64 v32; // [rsp+E8h] [rbp-58h]\n __int64 v33; // [rsp+F0h] [rbp-50h]\n __int64 v34; // [rsp+F8h] [rbp-48h]\n __int64 v35; // [rsp+100h] [rbp-40h]\n __int64 v36; // [rsp+108h] [rbp-38h]\n __int64 v37; // [rsp+110h] [rbp-30h]\n __int64 v38; // [rsp+118h] [rbp-28h]\n __int64 v39; // [rsp+120h] [rbp-20h]\n __int64 v40; // [rsp+128h] [rbp-18h]\n unsigned __int64 v41; // [rsp+138h] [rbp-8h]\n\n v41 = __readfsqword(0x28u);\n s2 = (char *)&unk_2008;\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n *(_QWORD *)s = 0LL;\n v10 = 0LL;\n v11 = 0LL;\n v12 = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0LL;\n v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n v22 = 0LL;\n v23 = 0LL;\n v24 = 0LL;\n v25 = 0LL;\n v26 = 0LL;\n v27 = 0LL;\n v28 = 0LL;\n v29 = 0LL;\n v30 = 0LL;\n v31 = 0LL;\n v32 = 0LL;\n v33 = 0LL;\n v34 = 0LL;\n v35 = 0LL;\n v36 = 0LL;\n v37 = 0LL;\n v38 = 0LL;\n v39 = 0LL;\n v40 = 0LL;\n v5 = 0;\n for ( j = 0; *(_BYTE *)(*(_QWORD *)(8LL * i + a1) + j); ++j )\n {\n if ( !strchr(s, *(char *)(*(_QWORD *)(8LL * i + a1) + j)) )\n {\n v7 = strlen(s);\n s[v7] = *(_BYTE *)(*(_QWORD *)(8LL * i + a1) + j);\n s[v7 + 1] = 0;\n ++v5;\n }\n }\n if ( v5 > v3 || v5 == v3 && strcmp(*(const char **)(8LL * i + a1), s2) < 0 )\n {\n s2 = *(char **)(8LL * i + a1);\n v3 = v5;\n }\n }\n return s2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11C9(long long a1, int a2) {\n int v3;\n int i;\n int v5;\n int j;\n int v7;\n char *s2;\n char s[8];\n long long v10;\n long long v11;\n long long v12;\n long long v13;\n long long v14;\n long long v15;\n long long v16;\n long long v17;\n long long v18;\n long long v19;\n long long v20;\n long long v21;\n long long v22;\n long long v23;\n long long v24;\n long long v25;\n long long v26;\n long long v27;\n long long v28;\n long long v29;\n long long v30;\n long long v31;\n long long v32;\n long long v33;\n long long v34;\n long long v35;\n long long v36;\n long long v37;\n long long v38;\n long long v39;\n long long v40;\n unsigned long long v41;\n v41 = __readfsqword(40u);\n s2 = (char *)&unk_2008;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n *(uint64_t *)s = 0LL;\n v10 = 0LL;\n v11 = 0LL;\n v12 = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0LL;\n v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n v22 = 0LL;\n v23 = 0LL;\n v24 = 0LL;\n v25 = 0LL;\n v26 = 0LL;\n v27 = 0LL;\n v28 = 0LL;\n v29 = 0LL;\n v30 = 0LL;\n v31 = 0LL;\n v32 = 0LL;\n v33 = 0LL;\n v34 = 0LL;\n v35 = 0LL;\n v36 = 0LL;\n v37 = 0LL;\n v38 = 0LL;\n v39 = 0LL;\n v40 = 0LL;\n v5 = 0;\n for (j = 0; *(uint8_t *)(*(uint64_t *)(8LL * i + a1) + j); ++j) {\n if (!strchr(s, *(char *)(*(uint64_t *)(8LL * i + a1) + j))) {\n v7 = strlen(s);\n s[v7] = *(uint8_t *)(*(uint64_t *)(8LL * i + a1) + j);\n s[v7 + 1] = 0;\n ++v5;\n }\n }\n if (v5 > v3 || v5 == v3 && strcmp(*(const char **)(8LL * i + a1), s2) < 0) {\n s2 = *(char **)(8LL * i + a1);\n v3 = v5;\n }\n }\n return s2;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2) {\n int v3;\n int i;\n int v5;\n int j;\n int v7;\n char *s2;\n char s[8];\n long long v10;\n long long v11;\n long long v12;\n long long v13;\n long long v14;\n long long v15;\n long long v16;\n long long v17;\n long long v18;\n long long v19;\n long long v20;\n long long v21;\n long long v22;\n long long v23;\n long long v24;\n long long v25;\n long long v26;\n long long v27;\n long long v28;\n long long v29;\n long long v30;\n long long v31;\n long long v32;\n long long v33;\n long long v34;\n long long v35;\n long long v36;\n long long v37;\n long long v38;\n long long v39;\n long long v40;\n unsigned long long v41;\n v41 = __readfsqword(40u);\n s2 = (char *)&unk_2008;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n *(uint64_t *)s = 0LL;\n v10 = 0LL;\n v11 = 0LL;\n v12 = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0LL;\n v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n v22 = 0LL;\n v23 = 0LL;\n v24 = 0LL;\n v25 = 0LL;\n v26 = 0LL;\n v27 = 0LL;\n v28 = 0LL;\n v29 = 0LL;\n v30 = 0LL;\n v31 = 0LL;\n v32 = 0LL;\n v33 = 0LL;\n v34 = 0LL;\n v35 = 0LL;\n v36 = 0LL;\n v37 = 0LL;\n v38 = 0LL;\n v39 = 0LL;\n v40 = 0LL;\n v5 = 0;\n for (j = 0; *(uint8_t *)(*(uint64_t *)(8LL * i + a1) + j); ++j) {\n if (!strchr(s, *(char *)(*(uint64_t *)(8LL * i + a1) + j))) {\n v7 = strlen(s);\n s[v7] = *(uint8_t *)(*(uint64_t *)(8LL * i + a1) + j);\n s[v7 + 1] = 0;\n ++v5;\n }\n }\n if (v5 > v3 || v5 == v3 && strcmp(*(const char **)(8LL * i + a1), s2) < 0) {\n s2 = *(char **)(8LL * i + a1);\n v3 = v5;\n }\n }\n return s2;\n}" + }, + { + "index": "HumanEval-C-158", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "char *func0(char *words[], int count) {\n char *max = \"\";\n int maxu = 0;\n for (int i = 0; i < count; i++) {\n char unique[256] = {0};\n int unique_count = 0;\n for (int j = 0; words[i][j] != '\\0'; j++) {\n if (!strchr(unique, words[i][j])) {\n int len = strlen(unique);\n unique[len] = words[i][j];\n unique[len + 1] = '\\0';\n unique_count++;\n }\n }\n if (unique_count > maxu ||\n (unique_count == maxu && strcmp(words[i], max) < 0)) {\n max = words[i];\n maxu = unique_count;\n }\n }\n return max;\n}", + "test": "#include \n#include \n\nint main() {\n char *words1[] = {\"name\", \"of\", \"string\"};\n assert(strcmp(func0(words1, 3), \"string\") == 0);\n\n char *words2[] = {\"name\", \"enam\", \"game\"};\n assert(strcmp(func0(words2, 3), \"enam\") == 0);\n\n char *words3[] = {\"aaaaaaa\", \"bb\", \"cc\"};\n assert(strcmp(func0(words3, 3), \"aaaaaaa\") == 0);\n\n char *words4[] = {\"abc\", \"cba\"};\n assert(strcmp(func0(words4, 2), \"abc\") == 0);\n\n char *words5[] = {\"play\", \"this\", \"game\", \"of\", \"footbott\"};\n assert(strcmp(func0(words5, 5), \"footbott\") == 0);\n\n char *words6[] = {\"we\", \"are\", \"gonna\", \"rock\"};\n assert(strcmp(func0(words6, 4), \"gonna\") == 0);\n\n char *words7[] = {\"we\", \"are\", \"a\", \"mad\", \"nation\"};\n assert(strcmp(func0(words7, 5), \"nation\") == 0);\n\n char *words8[] = {\"this\", \"is\", \"a\", \"prrk\"};\n assert(strcmp(func0(words8, 4), \"this\") == 0);\n\n char *words9[] = {\"b\"};\n assert(strcmp(func0(words9, 1), \"b\") == 0);\n\n char *words10[] = {\"play\", \"play\", \"play\"};\n assert(strcmp(func0(words10, 3), \"play\") == 0);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 138h\nmov rax, fs:28h\nmov [rsp+168h+var_40], rax\nxor eax, eax\nlea rax, aAaaaaaa+7; \"\"\nmov [rsp+168h+s2], rax\ntest esi, esi\njle loc_1430\nmov r14, rdi\nmovsxd rsi, esi\nlea rax, [rdi+rsi*8]\nmov [rsp+168h+var_150], rax\nmov [rsp+168h+var_15C], 0\nlea r12, [rsp+168h+var_148]\njmp loc_12B6\nloc_1226:\nmov rdi, r12; s\ncall _strlen\nmovsxd rdx, eax\nmov byte ptr [rsp+rdx+168h+var_148], bl\nadd eax, 1\ncdqe\nmov byte ptr [rsp+rax+168h+var_148], 0\nadd r13d, 1\nloc_1243:\nadd rbp, 1\nmovzx ebx, byte ptr [rbp-1]\ntest bl, bl\njz short loc_1267\nloc_124F:\nmovsx esi, bl; c\nmov rdi, r12; s\ncall _strchr\ntest rax, rax\njnz short loc_1243\njmp short loc_1226\nloc_1261:\nmov r13d, 0\nloc_1267:\nmov eax, [rsp+168h+var_15C]\ncmp eax, r13d\njl short loc_129A\njnz short loc_12A4\nmov rbx, [rsp+168h+s2]\nmov rsi, rbx; s2\nmov rdi, r15; s1\ncall _strcmp\ntest eax, eax\ncmovns r13d, [rsp+168h+var_15C]\nmov [rsp+168h+var_15C], r13d\ncmovns r15, rbx\nmov [rsp+168h+s2], r15\njmp short loc_12A4\nloc_129A:\nmov [rsp+168h+var_15C], r13d\nmov [rsp+168h+s2], r15\nloc_12A4:\nadd r14, 8\nmov rax, [rsp+168h+var_150]\ncmp r14, rax\njz loc_1430\nloc_12B6:\nmov [rsp+168h+var_148], 0\nmov [rsp+168h+var_140], 0\nmov [rsp+168h+var_138], 0\nmov [rsp+168h+var_130], 0\nmov [rsp+168h+var_128], 0\nmov [rsp+168h+var_120], 0\nmov [rsp+168h+var_118], 0\nmov [rsp+168h+var_110], 0\nmov [rsp+168h+var_108], 0\nmov [rsp+168h+var_100], 0\nmov [rsp+168h+var_F8], 0\nmov [rsp+168h+var_F0], 0\nmov [rsp+168h+var_E8], 0\nmov [rsp+168h+var_E0], 0\nmov [rsp+168h+var_D8], 0\nmov [rsp+168h+var_D0], 0\nmov [rsp+168h+var_C8], 0\nmov [rsp+168h+var_C0], 0\nmov [rsp+168h+var_B8], 0\nmov [rsp+168h+var_B0], 0\nmov [rsp+168h+var_A8], 0\nmov [rsp+168h+var_A0], 0\nmov [rsp+168h+var_98], 0\nmov [rsp+168h+var_90], 0\nmov [rsp+168h+var_88], 0\nmov [rsp+168h+var_80], 0\nmov [rsp+168h+var_78], 0\nmov [rsp+168h+var_70], 0\nmov [rsp+168h+var_68], 0\nmov [rsp+168h+var_60], 0\nmov [rsp+168h+var_58], 0\nmov [rsp+168h+var_50], 0\nmov r15, [r14]\nmovzx ebx, byte ptr [r15]\ntest bl, bl\njz loc_1261\nlea rbp, [r15+1]\nmov r13d, 0\njmp loc_124F\nloc_1430:\nmov rax, [rsp+168h+var_40]\nsub rax, fs:28h\njnz short loc_145A\nmov rax, [rsp+168h+s2]\nadd rsp, 138h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_145A:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(const char **a1, int a2)\n{\n const char **v2; // r14\n int v3; // eax\n int v4; // r13d\n char *v5; // rbp\n char v6; // bl\n int v7; // eax\n const char *v8; // r15\n int v10; // [rsp+Ch] [rbp-15Ch]\n char *s2; // [rsp+10h] [rbp-158h]\n _QWORD v12[41]; // [rsp+20h] [rbp-148h] BYREF\n\n v12[33] = __readfsqword(0x28u);\n s2 = (char *)\"\";\n if ( a2 > 0 )\n {\n v2 = a1;\n v10 = 0;\n do\n {\n memset(v12, 0, 256);\n v8 = *v2;\n v6 = **v2;\n if ( v6 )\n {\n v5 = (char *)(v8 + 1);\n v4 = 0;\n do\n {\n if ( !strchr((const char *)v12, v6) )\n {\n v3 = strlen((const char *)v12);\n *((_BYTE *)v12 + v3) = v6;\n *((_BYTE *)v12 + v3 + 1) = 0;\n ++v4;\n }\n v6 = *v5++;\n }\n while ( v6 );\n }\n else\n {\n v4 = 0;\n }\n if ( v10 < v4 )\n {\n v10 = v4;\n s2 = (char *)v8;\n }\n else if ( v10 == v4 )\n {\n v7 = strcmp(v8, s2);\n if ( v7 >= 0 )\n v4 = v10;\n v10 = v4;\n if ( v7 >= 0 )\n v8 = s2;\n s2 = (char *)v8;\n }\n ++v2;\n }\n while ( v2 != &a1[a2] );\n }\n return s2;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 138h\nmov rax, fs:28h\nmov [rsp+168h+var_40], rax\nxor eax, eax\nlea rax, aAaaaaaa+7; \"\"\nmov [rsp+168h+s2], rax\ntest esi, esi\njle loc_1430\nmov r14, rdi\nmovsxd rsi, esi\nlea rax, [rdi+rsi*8]\nmov [rsp+168h+var_150], rax\nmov [rsp+168h+var_15C], 0\nlea r12, [rsp+168h+var_148]\njmp loc_12B6\nloc_1226:\nmov rdi, r12; s\ncall _strlen\nmovsxd rdx, eax\nmov byte ptr [rsp+rdx+168h+var_148], bl\nadd eax, 1\ncdqe\nmov byte ptr [rsp+rax+168h+var_148], 0\nadd r13d, 1\nloc_1243:\nadd rbp, 1\nmovzx ebx, byte ptr [rbp-1]\ntest bl, bl\njz short loc_1267\nloc_124F:\nmovsx esi, bl; c\nmov rdi, r12; s\ncall _strchr\ntest rax, rax\njnz short loc_1243\njmp short loc_1226\nloc_1261:\nmov r13d, 0\nloc_1267:\nmov eax, [rsp+168h+var_15C]\ncmp eax, r13d\njl short loc_129A\njnz short loc_12A4\nmov rbx, [rsp+168h+s2]\nmov rsi, rbx; s2\nmov rdi, r15; s1\ncall _strcmp\ntest eax, eax\ncmovns r13d, [rsp+168h+var_15C]\nmov [rsp+168h+var_15C], r13d\ncmovns r15, rbx\nmov [rsp+168h+s2], r15\njmp short loc_12A4\nloc_129A:\nmov [rsp+168h+var_15C], r13d\nmov [rsp+168h+s2], r15\nloc_12A4:\nadd r14, 8\nmov rax, [rsp+168h+var_150]\ncmp r14, rax\njz loc_1430\nloc_12B6:\nmov [rsp+168h+var_148], 0\nmov [rsp+168h+var_140], 0\nmov [rsp+168h+var_138], 0\nmov [rsp+168h+var_130], 0\nmov [rsp+168h+var_128], 0\nmov [rsp+168h+var_120], 0\nmov [rsp+168h+var_118], 0\nmov [rsp+168h+var_110], 0\nmov [rsp+168h+var_108], 0\nmov [rsp+168h+var_100], 0\nmov [rsp+168h+var_F8], 0\nmov [rsp+168h+var_F0], 0\nmov [rsp+168h+var_E8], 0\nmov [rsp+168h+var_E0], 0\nmov [rsp+168h+var_D8], 0\nmov [rsp+168h+var_D0], 0\nmov [rsp+168h+var_C8], 0\nmov [rsp+168h+var_C0], 0\nmov [rsp+168h+var_B8], 0\nmov [rsp+168h+var_B0], 0\nmov [rsp+168h+var_A8], 0\nmov [rsp+168h+var_A0], 0\nmov [rsp+168h+var_98], 0\nmov [rsp+168h+var_90], 0\nmov [rsp+168h+var_88], 0\nmov [rsp+168h+var_80], 0\nmov [rsp+168h+var_78], 0\nmov [rsp+168h+var_70], 0\nmov [rsp+168h+var_68], 0\nmov [rsp+168h+var_60], 0\nmov [rsp+168h+var_58], 0\nmov [rsp+168h+var_50], 0\nmov r15, [r14]\nmovzx ebx, byte ptr [r15]\ntest bl, bl\njz loc_1261\nlea rbp, [r15+1]\nmov r13d, 0\njmp loc_124F\nloc_1430:\nmov rax, [rsp+168h+var_40]\nsub rax, fs:28h\njnz short loc_145A\nmov rax, [rsp+168h+s2]\nadd rsp, 138h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_145A:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_11C9(const char **a1, int a2)\n{\n const char **v2; // r14\n int v3; // eax\n int v4; // r13d\n char *v5; // rbp\n char v6; // bl\n int v7; // eax\n const char *v8; // r15\n int v10; // [rsp+Ch] [rbp-15Ch]\n char *s2; // [rsp+10h] [rbp-158h]\n _QWORD v12[41]; // [rsp+20h] [rbp-148h] BYREF\n\n v12[33] = __readfsqword(0x28u);\n s2 = (char *)\"\";\n if ( a2 > 0 )\n {\n v2 = a1;\n v10 = 0;\n do\n {\n memset(v12, 0, 256);\n v8 = *v2;\n v6 = **v2;\n if ( v6 )\n {\n v5 = (char *)(v8 + 1);\n v4 = 0;\n do\n {\n if ( !strchr((const char *)v12, v6) )\n {\n v3 = strlen((const char *)v12);\n *((_BYTE *)v12 + v3) = v6;\n *((_BYTE *)v12 + v3 + 1) = 0;\n ++v4;\n }\n v6 = *v5++;\n }\n while ( v6 );\n }\n else\n {\n v4 = 0;\n }\n if ( v10 < v4 )\n {\n v10 = v4;\n s2 = (char *)v8;\n }\n else if ( v10 == v4 )\n {\n v7 = strcmp(v8, s2);\n if ( v7 >= 0 )\n v4 = v10;\n v10 = v4;\n if ( v7 >= 0 )\n v8 = s2;\n s2 = (char *)v8;\n }\n ++v2;\n }\n while ( v2 != &a1[a2] );\n }\n return s2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11C9(const char **a1, int a2) {\n const char **v2;\n int v3;\n int v4;\n char *v5;\n char v6;\n int v7;\n const char *v8;\n int v10;\n char *s2;\n uint64_t v12[41];\n v12[33] = __readfsqword(40u);\n s2 = (char *)\"\";\n if (a2 > 0) {\n v2 = a1;\n v10 = 0;\n do {\n memset(v12, 0, 256);\n v8 = *v2;\n v6 = **v2;\n if (v6) {\n v5 = (char *)(v8 + 1);\n v4 = 0;\n do {\n if (!strchr((const char *)v12, v6)) {\n v3 = strlen((const char *)v12);\n *((uint8_t *)v12 + v3) = v6;\n *((uint8_t *)v12 + v3 + 1) = 0;\n ++v4;\n }\n v6 = *v5++;\n } while (v6);\n } else {\n v4 = 0;\n }\n if (v10 < v4) {\n v10 = v4;\n s2 = (char *)v8;\n } else if (v10 == v4) {\n v7 = strcmp(v8, s2);\n if (v7 >= 0) v4 = v10;\n v10 = v4;\n if (v7 >= 0) v8 = s2;\n s2 = (char *)v8;\n }\n ++v2;\n } while (v2 != &a1[a2]);\n }\n return s2;\n}", + "ida_pseudo_norm": "char *func0(const char **a1, int a2) {\n const char **v2;\n int v3;\n int v4;\n char *v5;\n char v6;\n int v7;\n const char *v8;\n int v10;\n char *s2;\n uint64_t v12[41];\n v12[33] = __readfsqword(40u);\n s2 = (char *)\"\";\n if (a2 > 0) {\n v2 = a1;\n v10 = 0;\n do {\n memset(v12, 0, 256);\n v8 = *v2;\n v6 = **v2;\n if (v6) {\n v5 = (char *)(v8 + 1);\n v4 = 0;\n do {\n if (!strchr((const char *)v12, v6)) {\n v3 = strlen((const char *)v12);\n *((uint8_t *)v12 + v3) = v6;\n *((uint8_t *)v12 + v3 + 1) = 0;\n ++v4;\n }\n v6 = *v5++;\n } while (v6);\n } else {\n v4 = 0;\n }\n if (v10 < v4) {\n v10 = v4;\n s2 = (char *)v8;\n } else if (v10 == v4) {\n v7 = strcmp(v8, s2);\n if (v7 >= 0) v4 = v10;\n v10 = v4;\n if (v7 >= 0) v8 = s2;\n s2 = (char *)v8;\n }\n ++v2;\n } while (v2 != &a1[a2]);\n }\n return s2;\n}" + }, + { + "index": "HumanEval-C-158", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "char *func0(char *words[], int count) {\n char *max = \"\";\n int maxu = 0;\n for (int i = 0; i < count; i++) {\n char unique[256] = {0};\n int unique_count = 0;\n for (int j = 0; words[i][j] != '\\0'; j++) {\n if (!strchr(unique, words[i][j])) {\n int len = strlen(unique);\n unique[len] = words[i][j];\n unique[len + 1] = '\\0';\n unique_count++;\n }\n }\n if (unique_count > maxu ||\n (unique_count == maxu && strcmp(words[i], max) < 0)) {\n max = words[i];\n maxu = unique_count;\n }\n }\n return max;\n}", + "test": "#include \n#include \n\nint main() {\n char *words1[] = {\"name\", \"of\", \"string\"};\n assert(strcmp(func0(words1, 3), \"string\") == 0);\n\n char *words2[] = {\"name\", \"enam\", \"game\"};\n assert(strcmp(func0(words2, 3), \"enam\") == 0);\n\n char *words3[] = {\"aaaaaaa\", \"bb\", \"cc\"};\n assert(strcmp(func0(words3, 3), \"aaaaaaa\") == 0);\n\n char *words4[] = {\"abc\", \"cba\"};\n assert(strcmp(func0(words4, 2), \"abc\") == 0);\n\n char *words5[] = {\"play\", \"this\", \"game\", \"of\", \"footbott\"};\n assert(strcmp(func0(words5, 5), \"footbott\") == 0);\n\n char *words6[] = {\"we\", \"are\", \"gonna\", \"rock\"};\n assert(strcmp(func0(words6, 4), \"gonna\") == 0);\n\n char *words7[] = {\"we\", \"are\", \"a\", \"mad\", \"nation\"};\n assert(strcmp(func0(words7, 5), \"nation\") == 0);\n\n char *words8[] = {\"this\", \"is\", \"a\", \"prrk\"};\n assert(strcmp(func0(words8, 4), \"this\") == 0);\n\n char *words9[] = {\"b\"};\n assert(strcmp(func0(words9, 1), \"b\") == 0);\n\n char *words10[] = {\"play\", \"play\", \"play\"};\n assert(strcmp(func0(words10, 3), \"play\") == 0);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 138h\nmov rax, fs:28h\nmov [rsp+168h+var_40], rax\nlea rax, aAaaaaaa+7; \"\"\nmov [rsp+168h+s2], rax\ntest esi, esi\njle loc_18A2\nmovsxd rsi, esi\nmov [rsp+168h+var_15C], 0\nmov r12, rdi\nlea rbx, [rsp+168h+s]\nlea rax, [rdi+rsi*8]\nmov [rsp+168h+var_158], rax\nnop word ptr [rax+rax+00000000h]\nloc_1790:\nmov r13, [r12]\npxor xmm0, xmm0\nmovaps xmmword ptr [rsp+168h+s], xmm0\nmovzx r14d, byte ptr [r13+0]\nmovaps [rsp+168h+var_138], xmm0\nmovaps [rsp+168h+var_128], xmm0\nmovaps [rsp+168h+var_118], xmm0\nmovaps [rsp+168h+var_108], xmm0\nmovaps [rsp+168h+var_F8], xmm0\nmovaps [rsp+168h+var_E8], xmm0\nmovaps [rsp+168h+var_D8], xmm0\nmovaps [rsp+168h+var_C8], xmm0\nmovaps [rsp+168h+var_B8], xmm0\nmovaps [rsp+168h+var_A8], xmm0\nmovaps [rsp+168h+var_98], xmm0\nmovaps [rsp+168h+var_88], xmm0\nmovaps [rsp+168h+var_78], xmm0\nmovaps [rsp+168h+var_68], xmm0\nmovaps [rsp+168h+var_58], xmm0\ntest r14b, r14b\njz loc_18E0\nlea r15, [r13+1]\nxor ebp, ebp\njmp short loc_182D\nloc_1820:\nmovzx r14d, byte ptr [r15]\nadd r15, 1\ntest r14b, r14b\njz short loc_1869\nloc_182D:\nmovsx esi, r14b; c\nmov rdi, rbx; s\ncall _strchr\ntest rax, rax\njnz short loc_1820\nmov rdi, rbx; s\nadd r15, 1\nadd ebp, 1\ncall _strlen\nmovsxd rsi, eax\nadd eax, 1\nmov [rsp+rsi+168h+s], r14b\nmovzx r14d, byte ptr [r15-1]\ncdqe\nmov [rsp+rax+168h+s], 0\ntest r14b, r14b\njnz short loc_182D\nloc_1869:\ncmp [rsp+168h+var_15C], ebp\njl short loc_18D0\njnz short loc_1890\nmov r15, [rsp+168h+s2]\nmov rdi, r13; s1\nmov rsi, r15; s2\ncall _strcmp\ntest eax, eax\ncmovns r13, r15\nmov [rsp+168h+s2], r13\nnop dword ptr [rax+00h]\nloc_1890:\nmov rax, [rsp+168h+var_158]\nadd r12, 8\ncmp r12, rax\njnz loc_1790\nloc_18A2:\nmov rax, [rsp+168h+var_40]\nsub rax, fs:28h\njnz short loc_18E4\nmov rax, [rsp+168h+s2]\nadd rsp, 138h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_18D0:\nmov [rsp+168h+var_15C], ebp\nmov [rsp+168h+s2], r13\njmp short loc_1890\nloc_18E0:\nxor ebp, ebp\njmp short loc_1869\nloc_18E4:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(const char **a1, int a2)\n{\n const char **v2; // r12\n const char *v3; // r13\n char v4; // r14\n char *v5; // r15\n int v6; // ebp\n int v7; // eax\n int v9; // [rsp+Ch] [rbp-15Ch]\n char *s2; // [rsp+18h] [rbp-150h]\n char s[16]; // [rsp+20h] [rbp-148h] BYREF\n __int128 v12; // [rsp+30h] [rbp-138h]\n __int128 v13; // [rsp+40h] [rbp-128h]\n __int128 v14; // [rsp+50h] [rbp-118h]\n __int128 v15; // [rsp+60h] [rbp-108h]\n __int128 v16; // [rsp+70h] [rbp-F8h]\n __int128 v17; // [rsp+80h] [rbp-E8h]\n __int128 v18; // [rsp+90h] [rbp-D8h]\n __int128 v19; // [rsp+A0h] [rbp-C8h]\n __int128 v20; // [rsp+B0h] [rbp-B8h]\n __int128 v21; // [rsp+C0h] [rbp-A8h]\n __int128 v22; // [rsp+D0h] [rbp-98h]\n __int128 v23; // [rsp+E0h] [rbp-88h]\n __int128 v24; // [rsp+F0h] [rbp-78h]\n __int128 v25; // [rsp+100h] [rbp-68h]\n __int128 v26; // [rsp+110h] [rbp-58h]\n unsigned __int64 v27; // [rsp+128h] [rbp-40h]\n\n v27 = __readfsqword(0x28u);\n s2 = (char *)\"\";\n if ( a2 > 0 )\n {\n v9 = 0;\n v2 = a1;\n do\n {\n v3 = *v2;\n *(_OWORD *)s = 0LL;\n v4 = *v3;\n v12 = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0LL;\n v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n v22 = 0LL;\n v23 = 0LL;\n v24 = 0LL;\n v25 = 0LL;\n v26 = 0LL;\n if ( v4 )\n {\n v5 = (char *)(v3 + 1);\n v6 = 0;\n do\n {\n while ( strchr(s, v4) )\n {\n v4 = *v5++;\n if ( !v4 )\n goto LABEL_8;\n }\n ++v5;\n ++v6;\n v7 = strlen(s);\n s[v7] = v4;\n v4 = *(v5 - 1);\n s[v7 + 1] = 0;\n }\n while ( v4 );\n }\n else\n {\n v6 = 0;\n }\nLABEL_8:\n if ( v9 < v6 )\n {\n v9 = v6;\n s2 = (char *)v3;\n }\n else if ( v9 == v6 )\n {\n if ( strcmp(v3, s2) >= 0 )\n v3 = s2;\n s2 = (char *)v3;\n }\n ++v2;\n }\n while ( v2 != &a1[a2] );\n }\n return s2;\n}", + "ida_strip_asm": "sub_1730:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 138h\nmov rax, fs:28h\nmov [rsp+168h+var_40], rax\nlea rax, aAaaaaaa+7; \"\"\nmov [rsp+168h+s2], rax\ntest esi, esi\njle loc_18A2\nmovsxd rsi, esi\nmov [rsp+168h+var_15C], 0\nmov r12, rdi\nlea rbx, [rsp+168h+s]\nlea rax, [rdi+rsi*8]\nmov [rsp+168h+var_158], rax\nnop word ptr [rax+rax+00000000h]\nloc_1790:\nmov r13, [r12]\npxor xmm0, xmm0\nmovaps xmmword ptr [rsp+168h+s], xmm0\nmovzx r14d, byte ptr [r13+0]\nmovaps [rsp+168h+var_138], xmm0\nmovaps [rsp+168h+var_128], xmm0\nmovaps [rsp+168h+var_118], xmm0\nmovaps [rsp+168h+var_108], xmm0\nmovaps [rsp+168h+var_F8], xmm0\nmovaps [rsp+168h+var_E8], xmm0\nmovaps [rsp+168h+var_D8], xmm0\nmovaps [rsp+168h+var_C8], xmm0\nmovaps [rsp+168h+var_B8], xmm0\nmovaps [rsp+168h+var_A8], xmm0\nmovaps [rsp+168h+var_98], xmm0\nmovaps [rsp+168h+var_88], xmm0\nmovaps [rsp+168h+var_78], xmm0\nmovaps [rsp+168h+var_68], xmm0\nmovaps [rsp+168h+var_58], xmm0\ntest r14b, r14b\njz loc_18E0\nlea r15, [r13+1]\nxor ebp, ebp\njmp short loc_182D\nloc_1820:\nmovzx r14d, byte ptr [r15]\nadd r15, 1\ntest r14b, r14b\njz short loc_1869\nloc_182D:\nmovsx esi, r14b; c\nmov rdi, rbx; s\ncall _strchr\ntest rax, rax\njnz short loc_1820\nmov rdi, rbx; s\nadd r15, 1\nadd ebp, 1\ncall _strlen\nmovsxd rsi, eax\nadd eax, 1\nmov [rsp+rsi+168h+s], r14b\nmovzx r14d, byte ptr [r15-1]\ncdqe\nmov [rsp+rax+168h+s], 0\ntest r14b, r14b\njnz short loc_182D\nloc_1869:\ncmp [rsp+168h+var_15C], ebp\njl short loc_18D0\njnz short loc_1890\nmov r15, [rsp+168h+s2]\nmov rdi, r13; s1\nmov rsi, r15; s2\ncall _strcmp\ntest eax, eax\ncmovns r13, r15\nmov [rsp+168h+s2], r13\nnop dword ptr [rax+00h]\nloc_1890:\nmov rax, [rsp+168h+var_158]\nadd r12, 8\ncmp r12, rax\njnz loc_1790\nloc_18A2:\nmov rax, [rsp+168h+var_40]\nsub rax, fs:28h\njnz short loc_18E4\nmov rax, [rsp+168h+s2]\nadd rsp, 138h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_18D0:\nmov [rsp+168h+var_15C], ebp\nmov [rsp+168h+s2], r13\njmp short loc_1890\nloc_18E0:\nxor ebp, ebp\njmp short loc_1869\nloc_18E4:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_1730(const char **a1, int a2)\n{\n const char **v2; // r12\n const char *v3; // r13\n char v4; // r14\n char *v5; // r15\n int v6; // ebp\n int v7; // eax\n int v9; // [rsp+Ch] [rbp-15Ch]\n char *s2; // [rsp+18h] [rbp-150h]\n char s[16]; // [rsp+20h] [rbp-148h] BYREF\n __int128 v12; // [rsp+30h] [rbp-138h]\n __int128 v13; // [rsp+40h] [rbp-128h]\n __int128 v14; // [rsp+50h] [rbp-118h]\n __int128 v15; // [rsp+60h] [rbp-108h]\n __int128 v16; // [rsp+70h] [rbp-F8h]\n __int128 v17; // [rsp+80h] [rbp-E8h]\n __int128 v18; // [rsp+90h] [rbp-D8h]\n __int128 v19; // [rsp+A0h] [rbp-C8h]\n __int128 v20; // [rsp+B0h] [rbp-B8h]\n __int128 v21; // [rsp+C0h] [rbp-A8h]\n __int128 v22; // [rsp+D0h] [rbp-98h]\n __int128 v23; // [rsp+E0h] [rbp-88h]\n __int128 v24; // [rsp+F0h] [rbp-78h]\n __int128 v25; // [rsp+100h] [rbp-68h]\n __int128 v26; // [rsp+110h] [rbp-58h]\n unsigned __int64 v27; // [rsp+128h] [rbp-40h]\n\n v27 = __readfsqword(0x28u);\n s2 = (char *)\"\";\n if ( a2 > 0 )\n {\n v9 = 0;\n v2 = a1;\n do\n {\n v3 = *v2;\n *(_OWORD *)s = 0LL;\n v4 = *v3;\n v12 = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0LL;\n v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n v22 = 0LL;\n v23 = 0LL;\n v24 = 0LL;\n v25 = 0LL;\n v26 = 0LL;\n if ( v4 )\n {\n v5 = (char *)(v3 + 1);\n v6 = 0;\n do\n {\n while ( strchr(s, v4) )\n {\n v4 = *v5++;\n if ( !v4 )\n goto LABEL_8;\n }\n ++v5;\n ++v6;\n v7 = strlen(s);\n s[v7] = v4;\n v4 = *(v5 - 1);\n s[v7 + 1] = 0;\n }\n while ( v4 );\n }\n else\n {\n v6 = 0;\n }\nLABEL_8:\n if ( v9 < v6 )\n {\n v9 = v6;\n s2 = (char *)v3;\n }\n else if ( v9 == v6 )\n {\n if ( strcmp(v3, s2) >= 0 )\n v3 = s2;\n s2 = (char *)v3;\n }\n ++v2;\n }\n while ( v2 != &a1[a2] );\n }\n return s2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1730(const char **a1, int a2) {\n const char **v2;\n const char *v3;\n char v4;\n char *v5;\n int v6;\n int v7;\n int v9;\n char *s2;\n char s[16];\n __int128 v12;\n __int128 v13;\n __int128 v14;\n __int128 v15;\n __int128 v16;\n __int128 v17;\n __int128 v18;\n __int128 v19;\n __int128 v20;\n __int128 v21;\n __int128 v22;\n __int128 v23;\n __int128 v24;\n __int128 v25;\n __int128 v26;\n unsigned long long v27;\n v27 = __readfsqword(40u);\n s2 = (char *)\"\";\n if (a2 > 0) {\n v9 = 0;\n v2 = a1;\n do {\n v3 = *v2;\n *(long double *)s = 0LL;\n v4 = *v3;\n v12 = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0LL;\n v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n v22 = 0LL;\n v23 = 0LL;\n v24 = 0LL;\n v25 = 0LL;\n v26 = 0LL;\n if (v4) {\n v5 = (char *)(v3 + 1);\n v6 = 0;\n do {\n while (strchr(s, v4)) {\n v4 = *v5++;\n if (!v4) goto LABEL_8;\n }\n ++v5;\n ++v6;\n v7 = strlen(s);\n s[v7] = v4;\n v4 = *(v5 - 1);\n s[v7 + 1] = 0;\n } while (v4);\n } else {\n v6 = 0;\n }\n LABEL_8:\n if (v9 < v6) {\n v9 = v6;\n s2 = (char *)v3;\n } else if (v9 == v6) {\n if (strcmp(v3, s2) >= 0) v3 = s2;\n s2 = (char *)v3;\n }\n ++v2;\n } while (v2 != &a1[a2]);\n }\n return s2;\n}", + "ida_pseudo_norm": "char *func0(const char **a1, int a2) {\n const char **v2;\n const char *v3;\n char v4;\n char *v5;\n int v6;\n int v7;\n int v9;\n char *s2;\n char s[16];\n __int128 v12;\n __int128 v13;\n __int128 v14;\n __int128 v15;\n __int128 v16;\n __int128 v17;\n __int128 v18;\n __int128 v19;\n __int128 v20;\n __int128 v21;\n __int128 v22;\n __int128 v23;\n __int128 v24;\n __int128 v25;\n __int128 v26;\n unsigned long long v27;\n v27 = __readfsqword(40u);\n s2 = (char *)\"\";\n if (a2 > 0) {\n v9 = 0;\n v2 = a1;\n do {\n v3 = *v2;\n *(long double *)s = 0LL;\n v4 = *v3;\n v12 = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0LL;\n v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n v22 = 0LL;\n v23 = 0LL;\n v24 = 0LL;\n v25 = 0LL;\n v26 = 0LL;\n if (v4) {\n v5 = (char *)(v3 + 1);\n v6 = 0;\n do {\n while (strchr(s, v4)) {\n v4 = *v5++;\n if (!v4) goto LABEL_8;\n }\n ++v5;\n ++v6;\n v7 = strlen(s);\n s[v7] = v4;\n v4 = *(v5 - 1);\n s[v7 + 1] = 0;\n } while (v4);\n } else {\n v6 = 0;\n }\n LABEL_8:\n if (v9 < v6) {\n v9 = v6;\n s2 = (char *)v3;\n } else if (v9 == v6) {\n if (strcmp(v3, s2) >= 0) v3 = s2;\n s2 = (char *)v3;\n }\n ++v2;\n } while (v2 != &a1[a2]);\n }\n return s2;\n}" + }, + { + "index": "HumanEval-C-158", + "func_name": "func0", + "func_dep": "#include \n#include \n", + "func": "char *func0(char *words[], int count) {\n char *max = \"\";\n int maxu = 0;\n for (int i = 0; i < count; i++) {\n char unique[256] = {0};\n int unique_count = 0;\n for (int j = 0; words[i][j] != '\\0'; j++) {\n if (!strchr(unique, words[i][j])) {\n int len = strlen(unique);\n unique[len] = words[i][j];\n unique[len + 1] = '\\0';\n unique_count++;\n }\n }\n if (unique_count > maxu ||\n (unique_count == maxu && strcmp(words[i], max) < 0)) {\n max = words[i];\n maxu = unique_count;\n }\n }\n return max;\n}", + "test": "#include \n#include \n\nint main() {\n char *words1[] = {\"name\", \"of\", \"string\"};\n assert(strcmp(func0(words1, 3), \"string\") == 0);\n\n char *words2[] = {\"name\", \"enam\", \"game\"};\n assert(strcmp(func0(words2, 3), \"enam\") == 0);\n\n char *words3[] = {\"aaaaaaa\", \"bb\", \"cc\"};\n assert(strcmp(func0(words3, 3), \"aaaaaaa\") == 0);\n\n char *words4[] = {\"abc\", \"cba\"};\n assert(strcmp(func0(words4, 2), \"abc\") == 0);\n\n char *words5[] = {\"play\", \"this\", \"game\", \"of\", \"footbott\"};\n assert(strcmp(func0(words5, 5), \"footbott\") == 0);\n\n char *words6[] = {\"we\", \"are\", \"gonna\", \"rock\"};\n assert(strcmp(func0(words6, 4), \"gonna\") == 0);\n\n char *words7[] = {\"we\", \"are\", \"a\", \"mad\", \"nation\"};\n assert(strcmp(func0(words7, 5), \"nation\") == 0);\n\n char *words8[] = {\"this\", \"is\", \"a\", \"prrk\"};\n assert(strcmp(func0(words8, 4), \"this\") == 0);\n\n char *words9[] = {\"b\"};\n assert(strcmp(func0(words9, 1), \"b\") == 0);\n\n char *words10[] = {\"play\", \"play\", \"play\"};\n assert(strcmp(func0(words10, 3), \"play\") == 0);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 138h\nmov rax, fs:28h\nmov [rsp+168h+var_40], rax\nlea rax, aAaaaaaa+7; \"\"\nmov [rsp+168h+s2], rax\ntest esi, esi\njle loc_1877\nmovsxd rsi, esi\nmov [rsp+168h+var_15C], 0\nmov r12, rdi\nlea rbx, [rsp+168h+s]\nlea rax, [rdi+rsi*8]\nmov [rsp+168h+var_158], rax\nnop word ptr [rax+rax+00000000h]\nloc_1790:\nmov r13, [r12]\npxor xmm0, xmm0\nmovaps xmmword ptr [rsp+168h+s], xmm0\nmovzx r14d, byte ptr [r13+0]\nmovaps [rsp+168h+var_138], xmm0\nmovaps [rsp+168h+var_128], xmm0\nmovaps [rsp+168h+var_118], xmm0\nmovaps [rsp+168h+var_108], xmm0\nmovaps [rsp+168h+var_F8], xmm0\nmovaps [rsp+168h+var_E8], xmm0\nmovaps [rsp+168h+var_D8], xmm0\nmovaps [rsp+168h+var_C8], xmm0\nmovaps [rsp+168h+var_B8], xmm0\nmovaps [rsp+168h+var_A8], xmm0\nmovaps [rsp+168h+var_98], xmm0\nmovaps [rsp+168h+var_88], xmm0\nmovaps [rsp+168h+var_78], xmm0\nmovaps [rsp+168h+var_68], xmm0\nmovaps [rsp+168h+var_58], xmm0\ntest r14b, r14b\njz loc_18F0\nlea r15, [r13+1]\nxor ebp, ebp\nnop word ptr [rax+rax+00h]\nloc_1820:\nmovsx esi, r14b; c\nmov rdi, rbx; s\ncall _strchr\ntest rax, rax\njz short loc_18A8\nmovzx r14d, byte ptr [r15]\nadd r15, 1\ntest r14b, r14b\njnz short loc_1820\nloc_183E:\ncmp [rsp+168h+var_15C], ebp\njl loc_18E1\nloc_1848:\njnz short loc_1868\nmov r15, [rsp+168h+s2]\nmov rdi, r13; s1\nmov rsi, r15; s2\ncall _strcmp\ntest eax, eax\ncmovns r13, r15\nmov [rsp+168h+s2], r13\nnop dword ptr [rax]\nloc_1868:\nadd r12, 8\ncmp [rsp+168h+var_158], r12\njnz loc_1790\nloc_1877:\nmov rax, [rsp+168h+var_40]\nsub rax, fs:28h\njnz short loc_18F7\nmov rax, [rsp+168h+s2]\nadd rsp, 138h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_18A8:\nmov rdi, rbx; s\nadd r15, 1\nadd ebp, 1\ncall _strlen\nmovsxd rsi, eax\nadd eax, 1\ncdqe\nmov [rsp+rsi+168h+s], r14b\nmov [rsp+rax+168h+s], 0\nmovzx r14d, byte ptr [r15-1]\ntest r14b, r14b\njnz loc_1820\ncmp [rsp+168h+var_15C], ebp\njge loc_1848\nloc_18E1:\nmov [rsp+168h+var_15C], ebp\nmov [rsp+168h+s2], r13\njmp loc_1868\nloc_18F0:\nxor ebp, ebp\njmp loc_183E\nloc_18F7:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(const char **a1, int a2)\n{\n const char **i; // r12\n const char *v3; // r13\n char v4; // r14\n char *v5; // r15\n int v6; // ebp\n bool v7; // zf\n int v9; // eax\n int v10; // [rsp+Ch] [rbp-15Ch]\n char *s2; // [rsp+18h] [rbp-150h]\n char s[16]; // [rsp+20h] [rbp-148h] BYREF\n __int128 v13; // [rsp+30h] [rbp-138h]\n __int128 v14; // [rsp+40h] [rbp-128h]\n __int128 v15; // [rsp+50h] [rbp-118h]\n __int128 v16; // [rsp+60h] [rbp-108h]\n __int128 v17; // [rsp+70h] [rbp-F8h]\n __int128 v18; // [rsp+80h] [rbp-E8h]\n __int128 v19; // [rsp+90h] [rbp-D8h]\n __int128 v20; // [rsp+A0h] [rbp-C8h]\n __int128 v21; // [rsp+B0h] [rbp-B8h]\n __int128 v22; // [rsp+C0h] [rbp-A8h]\n __int128 v23; // [rsp+D0h] [rbp-98h]\n __int128 v24; // [rsp+E0h] [rbp-88h]\n __int128 v25; // [rsp+F0h] [rbp-78h]\n __int128 v26; // [rsp+100h] [rbp-68h]\n __int128 v27; // [rsp+110h] [rbp-58h]\n unsigned __int64 v28; // [rsp+128h] [rbp-40h]\n\n v28 = __readfsqword(0x28u);\n s2 = (char *)\"\";\n if ( a2 > 0 )\n {\n v10 = 0;\n for ( i = a1; &a1[a2] != i; ++i )\n {\n v3 = *i;\n *(_OWORD *)s = 0LL;\n v4 = *v3;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0LL;\n v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n v22 = 0LL;\n v23 = 0LL;\n v24 = 0LL;\n v25 = 0LL;\n v26 = 0LL;\n v27 = 0LL;\n if ( v4 )\n {\n v5 = (char *)(v3 + 1);\n v6 = 0;\n do\n {\n while ( strchr(s, v4) )\n {\n v4 = *v5++;\n if ( !v4 )\n goto LABEL_7;\n }\n ++v5;\n ++v6;\n v9 = strlen(s);\n s[v9] = v4;\n s[v9 + 1] = 0;\n v4 = *(v5 - 1);\n }\n while ( v4 );\n v7 = v10 == v6;\n if ( v10 >= v6 )\n {\nLABEL_8:\n if ( v7 )\n {\n if ( strcmp(v3, s2) >= 0 )\n v3 = s2;\n s2 = (char *)v3;\n }\n continue;\n }\n }\n else\n {\n v6 = 0;\nLABEL_7:\n v7 = v10 == v6;\n if ( v10 >= v6 )\n goto LABEL_8;\n }\n v10 = v6;\n s2 = (char *)v3;\n }\n }\n return s2;\n}", + "ida_strip_asm": "sub_1730:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 138h\nmov rax, fs:28h\nmov [rsp+168h+var_40], rax\nlea rax, aAaaaaaa+7; \"\"\nmov [rsp+168h+s2], rax\ntest esi, esi\njle loc_1877\nmovsxd rsi, esi\nmov [rsp+168h+var_15C], 0\nmov r12, rdi\nlea rbx, [rsp+168h+s]\nlea rax, [rdi+rsi*8]\nmov [rsp+168h+var_158], rax\nnop word ptr [rax+rax+00000000h]\nloc_1790:\nmov r13, [r12]\npxor xmm0, xmm0\nmovaps xmmword ptr [rsp+168h+s], xmm0\nmovzx r14d, byte ptr [r13+0]\nmovaps [rsp+168h+var_138], xmm0\nmovaps [rsp+168h+var_128], xmm0\nmovaps [rsp+168h+var_118], xmm0\nmovaps [rsp+168h+var_108], xmm0\nmovaps [rsp+168h+var_F8], xmm0\nmovaps [rsp+168h+var_E8], xmm0\nmovaps [rsp+168h+var_D8], xmm0\nmovaps [rsp+168h+var_C8], xmm0\nmovaps [rsp+168h+var_B8], xmm0\nmovaps [rsp+168h+var_A8], xmm0\nmovaps [rsp+168h+var_98], xmm0\nmovaps [rsp+168h+var_88], xmm0\nmovaps [rsp+168h+var_78], xmm0\nmovaps [rsp+168h+var_68], xmm0\nmovaps [rsp+168h+var_58], xmm0\ntest r14b, r14b\njz loc_18F0\nlea r15, [r13+1]\nxor ebp, ebp\nnop word ptr [rax+rax+00h]\nloc_1820:\nmovsx esi, r14b; c\nmov rdi, rbx; s\ncall _strchr\ntest rax, rax\njz short loc_18A8\nmovzx r14d, byte ptr [r15]\nadd r15, 1\ntest r14b, r14b\njnz short loc_1820\nloc_183E:\ncmp [rsp+168h+var_15C], ebp\njl loc_18E1\nloc_1848:\njnz short loc_1868\nmov r15, [rsp+168h+s2]\nmov rdi, r13; s1\nmov rsi, r15; s2\ncall _strcmp\ntest eax, eax\ncmovns r13, r15\nmov [rsp+168h+s2], r13\nnop dword ptr [rax]\nloc_1868:\nadd r12, 8\ncmp [rsp+168h+var_158], r12\njnz loc_1790\nloc_1877:\nmov rax, [rsp+168h+var_40]\nsub rax, fs:28h\njnz short loc_18F7\nmov rax, [rsp+168h+s2]\nadd rsp, 138h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_18A8:\nmov rdi, rbx; s\nadd r15, 1\nadd ebp, 1\ncall _strlen\nmovsxd rsi, eax\nadd eax, 1\ncdqe\nmov [rsp+rsi+168h+s], r14b\nmov [rsp+rax+168h+s], 0\nmovzx r14d, byte ptr [r15-1]\ntest r14b, r14b\njnz loc_1820\ncmp [rsp+168h+var_15C], ebp\njge loc_1848\nloc_18E1:\nmov [rsp+168h+var_15C], ebp\nmov [rsp+168h+s2], r13\njmp loc_1868\nloc_18F0:\nxor ebp, ebp\njmp loc_183E\nloc_18F7:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_1730(const char **a1, int a2)\n{\n const char **i; // r12\n const char *v3; // r13\n char v4; // r14\n char *v5; // r15\n int v6; // ebp\n bool v7; // zf\n int v9; // eax\n int v10; // [rsp+Ch] [rbp-15Ch]\n char *s2; // [rsp+18h] [rbp-150h]\n char s[16]; // [rsp+20h] [rbp-148h] BYREF\n __int128 v13; // [rsp+30h] [rbp-138h]\n __int128 v14; // [rsp+40h] [rbp-128h]\n __int128 v15; // [rsp+50h] [rbp-118h]\n __int128 v16; // [rsp+60h] [rbp-108h]\n __int128 v17; // [rsp+70h] [rbp-F8h]\n __int128 v18; // [rsp+80h] [rbp-E8h]\n __int128 v19; // [rsp+90h] [rbp-D8h]\n __int128 v20; // [rsp+A0h] [rbp-C8h]\n __int128 v21; // [rsp+B0h] [rbp-B8h]\n __int128 v22; // [rsp+C0h] [rbp-A8h]\n __int128 v23; // [rsp+D0h] [rbp-98h]\n __int128 v24; // [rsp+E0h] [rbp-88h]\n __int128 v25; // [rsp+F0h] [rbp-78h]\n __int128 v26; // [rsp+100h] [rbp-68h]\n __int128 v27; // [rsp+110h] [rbp-58h]\n unsigned __int64 v28; // [rsp+128h] [rbp-40h]\n\n v28 = __readfsqword(0x28u);\n s2 = (char *)\"\";\n if ( a2 > 0 )\n {\n v10 = 0;\n for ( i = a1; &a1[a2] != i; ++i )\n {\n v3 = *i;\n *(_OWORD *)s = 0LL;\n v4 = *v3;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0LL;\n v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n v22 = 0LL;\n v23 = 0LL;\n v24 = 0LL;\n v25 = 0LL;\n v26 = 0LL;\n v27 = 0LL;\n if ( v4 )\n {\n v5 = (char *)(v3 + 1);\n v6 = 0;\n do\n {\n while ( strchr(s, v4) )\n {\n v4 = *v5++;\n if ( !v4 )\n goto LABEL_7;\n }\n ++v5;\n ++v6;\n v9 = strlen(s);\n s[v9] = v4;\n s[v9 + 1] = 0;\n v4 = *(v5 - 1);\n }\n while ( v4 );\n v7 = v10 == v6;\n if ( v10 >= v6 )\n {\nLABEL_8:\n if ( v7 )\n {\n if ( strcmp(v3, s2) >= 0 )\n v3 = s2;\n s2 = (char *)v3;\n }\n continue;\n }\n }\n else\n {\n v6 = 0;\nLABEL_7:\n v7 = v10 == v6;\n if ( v10 >= v6 )\n goto LABEL_8;\n }\n v10 = v6;\n s2 = (char *)v3;\n }\n }\n return s2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1730(const char **a1, int a2) {\n const char **i;\n const char *v3;\n char v4;\n char *v5;\n int v6;\n bool v7;\n int v9;\n int v10;\n char *s2;\n char s[16];\n __int128 v13;\n __int128 v14;\n __int128 v15;\n __int128 v16;\n __int128 v17;\n __int128 v18;\n __int128 v19;\n __int128 v20;\n __int128 v21;\n __int128 v22;\n __int128 v23;\n __int128 v24;\n __int128 v25;\n __int128 v26;\n __int128 v27;\n unsigned long long v28;\n v28 = __readfsqword(40u);\n s2 = (char *)\"\";\n if (a2 > 0) {\n v10 = 0;\n for (i = a1; &a1[a2] != i; ++i) {\n v3 = *i;\n *(long double *)s = 0LL;\n v4 = *v3;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0LL;\n v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n v22 = 0LL;\n v23 = 0LL;\n v24 = 0LL;\n v25 = 0LL;\n v26 = 0LL;\n v27 = 0LL;\n if (v4) {\n v5 = (char *)(v3 + 1);\n v6 = 0;\n do {\n while (strchr(s, v4)) {\n v4 = *v5++;\n if (!v4) goto LABEL_7;\n }\n ++v5;\n ++v6;\n v9 = strlen(s);\n s[v9] = v4;\n s[v9 + 1] = 0;\n v4 = *(v5 - 1);\n } while (v4);\n v7 = v10 == v6;\n if (v10 >= v6) {\n LABEL_8:\n if (v7) {\n if (strcmp(v3, s2) >= 0) v3 = s2;\n s2 = (char *)v3;\n }\n continue;\n }\n } else {\n v6 = 0;\n LABEL_7:\n v7 = v10 == v6;\n if (v10 >= v6) goto LABEL_8;\n }\n v10 = v6;\n s2 = (char *)v3;\n }\n }\n return s2;\n}", + "ida_pseudo_norm": "char *func0(const char **a1, int a2) {\n const char **i;\n const char *v3;\n char v4;\n char *v5;\n int v6;\n bool v7;\n int v9;\n int v10;\n char *s2;\n char s[16];\n __int128 v13;\n __int128 v14;\n __int128 v15;\n __int128 v16;\n __int128 v17;\n __int128 v18;\n __int128 v19;\n __int128 v20;\n __int128 v21;\n __int128 v22;\n __int128 v23;\n __int128 v24;\n __int128 v25;\n __int128 v26;\n __int128 v27;\n unsigned long long v28;\n v28 = __readfsqword(40u);\n s2 = (char *)\"\";\n if (a2 > 0) {\n v10 = 0;\n for (i = a1; &a1[a2] != i; ++i) {\n v3 = *i;\n *(long double *)s = 0LL;\n v4 = *v3;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0LL;\n v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n v22 = 0LL;\n v23 = 0LL;\n v24 = 0LL;\n v25 = 0LL;\n v26 = 0LL;\n v27 = 0LL;\n if (v4) {\n v5 = (char *)(v3 + 1);\n v6 = 0;\n do {\n while (strchr(s, v4)) {\n v4 = *v5++;\n if (!v4) goto LABEL_7;\n }\n ++v5;\n ++v6;\n v9 = strlen(s);\n s[v9] = v4;\n s[v9 + 1] = 0;\n v4 = *(v5 - 1);\n } while (v4);\n v7 = v10 == v6;\n if (v10 >= v6) {\n LABEL_8:\n if (v7) {\n if (strcmp(v3, s2) >= 0) v3 = s2;\n s2 = (char *)v3;\n }\n continue;\n }\n } else {\n v6 = 0;\n LABEL_7:\n v7 = v10 == v6;\n if (v10 >= v6) goto LABEL_8;\n }\n v10 = v6;\n s2 = (char *)v3;\n }\n }\n return s2;\n}" + }, + { + "index": "HumanEval-C-159", + "func_name": "func0", + "func_dep": "#include \n", + "func": "void func0(int number, int need, int remaining, int result[2]) {\n if (need > remaining) {\n result[0] = number + remaining;\n result[1] = 0;\n } else {\n result[0] = number + need;\n result[1] = remaining - need;\n }\n}", + "test": "#include \n\nint issame(int a[2], int b[2]) {\n return a[0] == b[0] && a[1] == b[1];\n}\n\nint main() {\n int result[2];\n\n func0(5, 6, 10, result);\n assert(issame(result, (const int[]){11, 4}));\n\n func0(4, 8, 9, result);\n assert(issame(result, (const int[]){12, 1}));\n\n func0(1, 10, 10, result);\n assert(issame(result, (const int[]){11, 0}));\n\n func0(2, 11, 5, result);\n assert(issame(result, (const int[]){7, 0}));\n\n func0(4, 5, 7, result);\n assert(issame(result, (const int[]){9, 2}));\n\n func0(4, 5, 1, result);\n assert(issame(result, (const int[]){5, 0}));\n \n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov [rbp+var_C], edx\nmov [rbp+var_18], rcx\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_C]\njle short loc_11A4\nmov edx, [rbp+var_4]\nmov eax, [rbp+var_C]\nadd edx, eax\nmov rax, [rbp+var_18]\nmov [rax], edx\nmov rax, [rbp+var_18]\nadd rax, 4\nmov dword ptr [rax], 0\njmp short loc_11C2\nloc_11A4:\nmov edx, [rbp+var_4]\nmov eax, [rbp+var_8]\nadd edx, eax\nmov rax, [rbp+var_18]\nmov [rax], edx\nmov rax, [rbp+var_18]\nlea rdx, [rax+4]\nmov eax, [rbp+var_C]\nsub eax, [rbp+var_8]\nmov [rdx], eax\nloc_11C2:\nnop\npop rbp\nretn", + "ida_pseudo": "unsigned __int64 __fastcall func0(int a1, int a2, int a3, _DWORD *a4)\n{\n unsigned __int64 result; // rax\n\n if ( a2 <= a3 )\n {\n *a4 = a2 + a1;\n result = (unsigned int)(a3 - a2);\n a4[1] = result;\n }\n else\n {\n *a4 = a3 + a1;\n result = (unsigned __int64)(a4 + 1);\n a4[1] = 0;\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov [rbp+var_C], edx\nmov [rbp+var_18], rcx\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_C]\njle short loc_11A4\nmov edx, [rbp+var_4]\nmov eax, [rbp+var_C]\nadd edx, eax\nmov rax, [rbp+var_18]\nmov [rax], edx\nmov rax, [rbp+var_18]\nadd rax, 4\nmov dword ptr [rax], 0\njmp short loc_11C2\nloc_11A4:\nmov edx, [rbp+var_4]\nmov eax, [rbp+var_8]\nadd edx, eax\nmov rax, [rbp+var_18]\nmov [rax], edx\nmov rax, [rbp+var_18]\nlea rdx, [rax+4]\nmov eax, [rbp+var_C]\nsub eax, [rbp+var_8]\nmov [rdx], eax\nloc_11C2:\nnop\npop rbp\nretn", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_1169(int a1, int a2, int a3, _DWORD *a4)\n{\n unsigned __int64 result; // rax\n\n if ( a2 <= a3 )\n {\n *a4 = a2 + a1;\n result = (unsigned int)(a3 - a2);\n a4[1] = result;\n }\n else\n {\n *a4 = a3 + a1;\n result = (unsigned __int64)(a4 + 1);\n a4[1] = 0;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_1169(int a1, int a2, int a3, uint32_t *a4) {\n unsigned long long result;\n if (a2 <= a3) {\n *a4 = a2 + a1;\n result = (unsigned int)(a3 - a2);\n a4[1] = result;\n } else {\n *a4 = a3 + a1;\n result = (unsigned long long)(a4 + 1);\n a4[1] = 0;\n }\n return result;\n}", + "ida_pseudo_norm": "unsigned long long func0(int a1, int a2, int a3, uint32_t *a4) {\n unsigned long long result;\n if (a2 <= a3) {\n *a4 = a2 + a1;\n result = (unsigned int)(a3 - a2);\n a4[1] = result;\n } else {\n *a4 = a3 + a1;\n result = (unsigned long long)(a4 + 1);\n a4[1] = 0;\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-160", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n#include \n", + "func": "int func0(const char **operato, const int *operand, int operato_size,\n int operand_size) {\n int *num = (int *)malloc(operand_size * sizeof(int));\n int *posto = (int *)malloc(operand_size * sizeof(int));\n for (int i = 0; i < operand_size; i++) {\n num[i] = operand[i];\n posto[i] = i;\n }\n for (int i = 0; i < operato_size; i++) {\n if (strcmp(operato[i], \"**\") == 0) {\n while (posto[posto[i]] != posto[i]) posto[i] = posto[posto[i]];\n while (posto[posto[i + 1]] != posto[i + 1])\n posto[i + 1] = posto[posto[i + 1]];\n num[posto[i]] = pow(num[posto[i]], num[posto[i + 1]]);\n posto[i + 1] = posto[i];\n }\n }\n for (int i = 0; i < operato_size; i++) {\n if (strcmp(operato[i], \"*\") == 0 || strcmp(operato[i], \"//\") == 0) {\n while (posto[posto[i]] != posto[i]) posto[i] = posto[posto[i]];\n while (posto[posto[i + 1]] != posto[i + 1])\n posto[i + 1] = posto[posto[i + 1]];\n if (strcmp(operato[i], \"*\") == 0)\n num[posto[i]] *= num[posto[i + 1]];\n else\n num[posto[i]] /= num[posto[i + 1]];\n posto[i + 1] = posto[i];\n }\n }\n for (int i = 0; i < operato_size; i++) {\n if (strcmp(operato[i], \"+\") == 0 || strcmp(operato[i], \"-\") == 0) {\n while (posto[posto[i]] != posto[i]) posto[i] = posto[posto[i]];\n while (posto[posto[i + 1]] != posto[i + 1])\n posto[i + 1] = posto[posto[i + 1]];\n if (strcmp(operato[i], \"+\") == 0)\n num[posto[i]] += num[posto[i + 1]];\n else\n num[posto[i]] -= num[posto[i + 1]];\n posto[i + 1] = posto[i];\n }\n }\n int result = num[0];\n free(num);\n free(posto);\n return result;\n}", + "test": "#include \n\nint main() {\n const char *operators1[] = {\"**\", \"*\", \"+\"};\n int operands1[] = {2, 3, 4, 5};\n assert(func0(operators1, operands1, 3, 4) == 37);\n\n const char *operators2[] = {\"+\", \"*\", \"-\"};\n int operands2[] = {2, 3, 4, 5};\n assert(func0(operators2, operands2, 3, 4) == 9);\n\n const char *operators3[] = {\"//\", \"*\"};\n int operands3[] = {7, 3, 4};\n assert(func0(operators3, operands3, 2, 3) == 8);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+var_38], rdi\nmov [rbp+var_40], rsi\nmov [rbp+var_44], edx\nmov [rbp+var_48], ecx\nmov eax, [rbp+var_48]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov eax, [rbp+var_48]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_24], 0\njmp short loc_1280\nloc_1236:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nadd rax, rdx\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+ptr]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_24]\nmov [rdx], eax\nadd [rbp+var_24], 1\nloc_1280:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_48]\njl short loc_1236\nmov [rbp+var_20], 0\njmp loc_14C2\nloc_1294:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nlea rdx, s2; \"**\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz loc_14BE\njmp short loc_1307\nloc_12C7:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nloc_1307:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_20]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz loc_12C7\njmp short loc_1398\nloc_1350:\nmov eax, [rbp+var_20]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nadd rdx, 1\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nloc_1398:\nmov eax, [rbp+var_20]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_20]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz loc_1350\nmov eax, [rbp+var_20]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\npxor xmm2, xmm2\ncvtsi2sd xmm2, eax\nmovq rax, xmm2\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rdx, rax\ncvttsd2si eax, xmm0\nmov [rdx], eax\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nadd rdx, 1\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nloc_14BE:\nadd [rbp+var_20], 1\nloc_14C2:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_44]\njl loc_1294\nmov [rbp+var_1C], 0\njmp loc_17CF\nloc_14DA:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nlea rdx, asc_200B; \"*\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_157A\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nlea rdx, asc_200D; \"//\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz loc_17CB\njmp short loc_157A\nloc_153A:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nloc_157A:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_1C]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz loc_153A\njmp short loc_160B\nloc_15C3:\nmov eax, [rbp+var_1C]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nadd rdx, 1\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nloc_160B:\nmov eax, [rbp+var_1C]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_1C]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz loc_15C3\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nlea rdx, asc_200B; \"*\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz loc_1714\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_1C]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rcx\nmov eax, [rax]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rcx\nmov eax, [rax]\nmov ecx, [rbp+var_1C]\nmovsxd rcx, ecx\nlea rsi, ds:0[rcx*4]\nmov rcx, [rbp+var_8]\nadd rcx, rsi\nmov ecx, [rcx]\nmovsxd rcx, ecx\nlea rsi, ds:0[rcx*4]\nmov rcx, [rbp+ptr]\nadd rcx, rsi\nimul eax, edx\nmov [rcx], eax\njmp loc_179A\nloc_1714:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nadd rdx, 1\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov edx, [rdx]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+ptr]\nadd rdx, rcx\nmov edi, [rdx]\nmov ecx, [rbp+var_1C]\nmovsxd rcx, ecx\nlea rsi, ds:0[rcx*4]\nmov rcx, [rbp+var_8]\nadd rcx, rsi\nmov ecx, [rcx]\nmovsxd rcx, ecx\nlea rsi, ds:0[rcx*4]\nmov rcx, [rbp+ptr]\nadd rcx, rsi\ncdq\nidiv edi\nmov [rcx], eax\nloc_179A:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nadd rdx, 1\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nloc_17CB:\nadd [rbp+var_1C], 1\nloc_17CF:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_44]\njl loc_14DA\nmov [rbp+var_18], 0\njmp loc_1AD6\nloc_17E7:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nlea rdx, asc_2010; \"+-\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_1887\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nlea rdx, asc_2010+2; \"-\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz loc_1AD2\njmp short loc_1887\nloc_1847:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rbp+var_18]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nloc_1887:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_18]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz loc_1847\njmp short loc_1918\nloc_18D0:\nmov eax, [rbp+var_18]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rbp+var_18]\nmovsxd rdx, edx\nadd rdx, 1\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nloc_1918:\nmov eax, [rbp+var_18]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_18]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz loc_18D0\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nlea rdx, asc_2010; \"+-\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz loc_1A1E\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov ecx, [rax]\nmov eax, [rbp+var_18]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_18]\ncdqe\nlea rsi, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rsi\nmov eax, [rax]\ncdqe\nlea rsi, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rsi\nadd edx, ecx\nmov [rax], edx\njmp loc_1AA1\nloc_1A1E:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov ecx, [rax]\nmov eax, [rbp+var_18]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_18]\nmovsxd rdx, edx\nlea rsi, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rsi\nmov edx, [rdx]\nmovsxd rdx, edx\nlea rsi, ds:0[rdx*4]\nmov rdx, [rbp+ptr]\nadd rdx, rsi\nsub ecx, eax\nmov [rdx], ecx\nloc_1AA1:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rbp+var_18]\nmovsxd rdx, edx\nadd rdx, 1\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nloc_1AD2:\nadd [rbp+var_18], 1\nloc_1AD6:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_44]\njl loc_17E7\nmov rax, [rbp+ptr]\nmov eax, [rax]\nmov [rbp+var_14], eax\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_8]\nmov rdi, rax; ptr\ncall _free\nmov eax, [rbp+var_14]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3, int a4)\n{\n __int64 v4; // rsi\n int v5; // eax\n int i; // [rsp+2Ch] [rbp-24h]\n int j; // [rsp+30h] [rbp-20h]\n int k; // [rsp+34h] [rbp-1Ch]\n int m; // [rsp+38h] [rbp-18h]\n unsigned int v13; // [rsp+3Ch] [rbp-14h]\n unsigned int *ptr; // [rsp+40h] [rbp-10h]\n int *v15; // [rsp+48h] [rbp-8h]\n\n ptr = (unsigned int *)malloc(4LL * a4);\n v15 = (int *)malloc(4LL * a4);\n for ( i = 0; i < a4; ++i )\n {\n ptr[i] = *(_DWORD *)(4LL * i + a2);\n v15[i] = i;\n }\n for ( j = 0; j < a3; ++j )\n {\n if ( !strcmp(*(const char **)(8LL * j + a1), \"**\") )\n {\n while ( v15[v15[j]] != v15[j] )\n v15[j] = v15[v15[j]];\n while ( v15[v15[j + 1]] != v15[j + 1] )\n v15[j + 1] = v15[v15[j + 1]];\n ptr[v15[j]] = (int)pow((double)(int)ptr[v15[j]], (double)(int)ptr[v15[j + 1]]);\n v15[j + 1] = v15[j];\n }\n }\n for ( k = 0; k < a3; ++k )\n {\n if ( !strcmp(*(const char **)(8LL * k + a1), \"*\") || !strcmp(*(const char **)(8LL * k + a1), \"//\") )\n {\n while ( v15[v15[k]] != v15[k] )\n v15[k] = v15[v15[k]];\n while ( v15[v15[k + 1]] != v15[k + 1] )\n v15[k + 1] = v15[v15[k + 1]];\n if ( !strcmp(*(const char **)(8LL * k + a1), \"*\") )\n {\n v4 = v15[k];\n v5 = ptr[v4] * ptr[v15[k + 1]];\n }\n else\n {\n v4 = v15[k];\n v5 = (int)ptr[v4] / (int)ptr[v15[k + 1]];\n }\n ptr[v4] = v5;\n v15[k + 1] = v15[k];\n }\n }\n for ( m = 0; m < a3; ++m )\n {\n if ( !strcmp(*(const char **)(8LL * m + a1), L\"+-\") || !strcmp(*(const char **)(8LL * m + a1), L\"-\") )\n {\n while ( v15[v15[m]] != v15[m] )\n v15[m] = v15[v15[m]];\n while ( v15[v15[m + 1]] != v15[m + 1] )\n v15[m + 1] = v15[v15[m + 1]];\n if ( !strcmp(*(const char **)(8LL * m + a1), L\"+-\") )\n ptr[v15[m]] += ptr[v15[m + 1]];\n else\n ptr[v15[m]] -= ptr[v15[m + 1]];\n v15[m + 1] = v15[m];\n }\n }\n v13 = *ptr;\n free(ptr);\n free(v15);\n return v13;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+var_38], rdi\nmov [rbp+var_40], rsi\nmov [rbp+var_44], edx\nmov [rbp+var_48], ecx\nmov eax, [rbp+var_48]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov eax, [rbp+var_48]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_24], 0\njmp short loc_1280\nloc_1236:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nadd rax, rdx\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+ptr]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_24]\nmov [rdx], eax\nadd [rbp+var_24], 1\nloc_1280:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_48]\njl short loc_1236\nmov [rbp+var_20], 0\njmp loc_14C2\nloc_1294:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nlea rdx, s2; \"**\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz loc_14BE\njmp short loc_1307\nloc_12C7:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nloc_1307:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_20]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz loc_12C7\njmp short loc_1398\nloc_1350:\nmov eax, [rbp+var_20]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nadd rdx, 1\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nloc_1398:\nmov eax, [rbp+var_20]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_20]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz loc_1350\nmov eax, [rbp+var_20]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\npxor xmm2, xmm2\ncvtsi2sd xmm2, eax\nmovq rax, xmm2\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rdx, rax\ncvttsd2si eax, xmm0\nmov [rdx], eax\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nadd rdx, 1\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nloc_14BE:\nadd [rbp+var_20], 1\nloc_14C2:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_44]\njl loc_1294\nmov [rbp+var_1C], 0\njmp loc_17CF\nloc_14DA:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nlea rdx, asc_200B; \"*\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_157A\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nlea rdx, asc_200D; \"//\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz loc_17CB\njmp short loc_157A\nloc_153A:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nloc_157A:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_1C]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz loc_153A\njmp short loc_160B\nloc_15C3:\nmov eax, [rbp+var_1C]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nadd rdx, 1\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nloc_160B:\nmov eax, [rbp+var_1C]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_1C]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz loc_15C3\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nlea rdx, asc_200B; \"*\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz loc_1714\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_1C]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rcx\nmov eax, [rax]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rcx\nmov eax, [rax]\nmov ecx, [rbp+var_1C]\nmovsxd rcx, ecx\nlea rsi, ds:0[rcx*4]\nmov rcx, [rbp+var_8]\nadd rcx, rsi\nmov ecx, [rcx]\nmovsxd rcx, ecx\nlea rsi, ds:0[rcx*4]\nmov rcx, [rbp+ptr]\nadd rcx, rsi\nimul eax, edx\nmov [rcx], eax\njmp loc_179A\nloc_1714:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nadd rdx, 1\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov edx, [rdx]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+ptr]\nadd rdx, rcx\nmov edi, [rdx]\nmov ecx, [rbp+var_1C]\nmovsxd rcx, ecx\nlea rsi, ds:0[rcx*4]\nmov rcx, [rbp+var_8]\nadd rcx, rsi\nmov ecx, [rcx]\nmovsxd rcx, ecx\nlea rsi, ds:0[rcx*4]\nmov rcx, [rbp+ptr]\nadd rcx, rsi\ncdq\nidiv edi\nmov [rcx], eax\nloc_179A:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nadd rdx, 1\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nloc_17CB:\nadd [rbp+var_1C], 1\nloc_17CF:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_44]\njl loc_14DA\nmov [rbp+var_18], 0\njmp loc_1AD6\nloc_17E7:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nlea rdx, asc_2010; \"+-\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_1887\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nlea rdx, asc_2010+2; \"-\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz loc_1AD2\njmp short loc_1887\nloc_1847:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rbp+var_18]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nloc_1887:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_18]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz loc_1847\njmp short loc_1918\nloc_18D0:\nmov eax, [rbp+var_18]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rbp+var_18]\nmovsxd rdx, edx\nadd rdx, 1\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nloc_1918:\nmov eax, [rbp+var_18]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_18]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz loc_18D0\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nlea rdx, asc_2010; \"+-\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz loc_1A1E\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov ecx, [rax]\nmov eax, [rbp+var_18]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_18]\ncdqe\nlea rsi, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rsi\nmov eax, [rax]\ncdqe\nlea rsi, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rsi\nadd edx, ecx\nmov [rax], edx\njmp loc_1AA1\nloc_1A1E:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov ecx, [rax]\nmov eax, [rbp+var_18]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_18]\nmovsxd rdx, edx\nlea rsi, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rsi\nmov edx, [rdx]\nmovsxd rdx, edx\nlea rsi, ds:0[rdx*4]\nmov rdx, [rbp+ptr]\nadd rdx, rsi\nsub ecx, eax\nmov [rdx], ecx\nloc_1AA1:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rbp+var_18]\nmovsxd rdx, edx\nadd rdx, 1\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nloc_1AD2:\nadd [rbp+var_18], 1\nloc_1AD6:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_44]\njl loc_17E7\nmov rax, [rbp+ptr]\nmov eax, [rax]\nmov [rbp+var_14], eax\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_8]\nmov rdi, rax; ptr\ncall _free\nmov eax, [rbp+var_14]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11E9(__int64 a1, __int64 a2, int a3, int a4)\n{\n __int64 v4; // rsi\n int v5; // eax\n int i; // [rsp+2Ch] [rbp-24h]\n int j; // [rsp+30h] [rbp-20h]\n int k; // [rsp+34h] [rbp-1Ch]\n int m; // [rsp+38h] [rbp-18h]\n unsigned int v13; // [rsp+3Ch] [rbp-14h]\n unsigned int *ptr; // [rsp+40h] [rbp-10h]\n int *v15; // [rsp+48h] [rbp-8h]\n\n ptr = (unsigned int *)malloc(4LL * a4);\n v15 = (int *)malloc(4LL * a4);\n for ( i = 0; i < a4; ++i )\n {\n ptr[i] = *(_DWORD *)(4LL * i + a2);\n v15[i] = i;\n }\n for ( j = 0; j < a3; ++j )\n {\n if ( !strcmp(*(const char **)(8LL * j + a1), \"**\") )\n {\n while ( v15[v15[j]] != v15[j] )\n v15[j] = v15[v15[j]];\n while ( v15[v15[j + 1]] != v15[j + 1] )\n v15[j + 1] = v15[v15[j + 1]];\n ptr[v15[j]] = (int)pow((double)(int)ptr[v15[j]], (double)(int)ptr[v15[j + 1]]);\n v15[j + 1] = v15[j];\n }\n }\n for ( k = 0; k < a3; ++k )\n {\n if ( !strcmp(*(const char **)(8LL * k + a1), \"*\") || !strcmp(*(const char **)(8LL * k + a1), \"//\") )\n {\n while ( v15[v15[k]] != v15[k] )\n v15[k] = v15[v15[k]];\n while ( v15[v15[k + 1]] != v15[k + 1] )\n v15[k + 1] = v15[v15[k + 1]];\n if ( !strcmp(*(const char **)(8LL * k + a1), \"*\") )\n {\n v4 = v15[k];\n v5 = ptr[v4] * ptr[v15[k + 1]];\n }\n else\n {\n v4 = v15[k];\n v5 = (int)ptr[v4] / (int)ptr[v15[k + 1]];\n }\n ptr[v4] = v5;\n v15[k + 1] = v15[k];\n }\n }\n for ( m = 0; m < a3; ++m )\n {\n if ( !strcmp(*(const char **)(8LL * m + a1), L\"+-\") || !strcmp(*(const char **)(8LL * m + a1), L\"-\") )\n {\n while ( v15[v15[m]] != v15[m] )\n v15[m] = v15[v15[m]];\n while ( v15[v15[m + 1]] != v15[m + 1] )\n v15[m + 1] = v15[v15[m + 1]];\n if ( !strcmp(*(const char **)(8LL * m + a1), L\"+-\") )\n ptr[v15[m]] += ptr[v15[m + 1]];\n else\n ptr[v15[m]] -= ptr[v15[m + 1]];\n v15[m + 1] = v15[m];\n }\n }\n v13 = *ptr;\n free(ptr);\n free(v15);\n return v13;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11E9(long long a1, long long a2, int a3, int a4) {\n long long v4;\n int v5;\n int i;\n int j;\n int k;\n int m;\n unsigned int v13;\n unsigned int *ptr;\n int *v15;\n ptr = (unsigned int *)malloc(4LL * a4);\n v15 = (int *)malloc(4LL * a4);\n for (i = 0; i < a4; ++i) {\n ptr[i] = *(uint32_t *)(4LL * i + a2);\n v15[i] = i;\n }\n for (j = 0; j < a3; ++j) {\n if (!strcmp(*(const char **)(8LL * j + a1), \"**\")) {\n while (v15[v15[j]] != v15[j]) v15[j] = v15[v15[j]];\n while (v15[v15[j + 1]] != v15[j + 1]) v15[j + 1] = v15[v15[j + 1]];\n ptr[v15[j]] =\n (int)pow((double)(int)ptr[v15[j]], (double)(int)ptr[v15[j + 1]]);\n v15[j + 1] = v15[j];\n }\n }\n for (k = 0; k < a3; ++k) {\n if ( !strcmp(*(const char **)(8LL * k + a1), \"*\") || !strcmp(*(const char **)(8LL * k + a1), \"\n {\n while (v15[v15[k]] != v15[k]) v15[k] = v15[v15[k]];\n while (v15[v15[k + 1]] != v15[k + 1]) v15[k + 1] = v15[v15[k + 1]];\n if (!strcmp(*(const char **)(8LL * k + a1), \"*\")) {\n v4 = v15[k];\n v5 = ptr[v4] * ptr[v15[k + 1]];\n } else {\n v4 = v15[k];\n v5 = (int)ptr[v4] / (int)ptr[v15[k + 1]];\n }\n ptr[v4] = v5;\n v15[k + 1] = v15[k];\n }\n }\n for (m = 0; m < a3; ++m) {\n if (!strcmp(*(const char **)(8LL * m + a1), L\"+-\") ||\n !strcmp(*(const char **)(8LL * m + a1), L\"-\")) {\n while (v15[v15[m]] != v15[m]) v15[m] = v15[v15[m]];\n while (v15[v15[m + 1]] != v15[m + 1]) v15[m + 1] = v15[v15[m + 1]];\n if (!strcmp(*(const char **)(8LL * m + a1), L\"+-\"))\n ptr[v15[m]] += ptr[v15[m + 1]];\n else\n ptr[v15[m]] -= ptr[v15[m + 1]];\n v15[m + 1] = v15[m];\n }\n }\n v13 = *ptr;\n free(ptr);\n free(v15);\n return v13;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3, int a4) {\n long long v4;\n int v5;\n int i;\n int j;\n int k;\n int m;\n unsigned int v13;\n unsigned int *ptr;\n int *v15;\n ptr = (unsigned int *)malloc(4LL * a4);\n v15 = (int *)malloc(4LL * a4);\n for (i = 0; i < a4; ++i) {\n ptr[i] = *(uint32_t *)(4LL * i + a2);\n v15[i] = i;\n }\n for (j = 0; j < a3; ++j) {\n if (!strcmp(*(const char **)(8LL * j + a1), \"**\")) {\n while (v15[v15[j]] != v15[j]) v15[j] = v15[v15[j]];\n while (v15[v15[j + 1]] != v15[j + 1]) v15[j + 1] = v15[v15[j + 1]];\n ptr[v15[j]] =\n (int)pow((double)(int)ptr[v15[j]], (double)(int)ptr[v15[j + 1]]);\n v15[j + 1] = v15[j];\n }\n }\n for (k = 0; k < a3; ++k) {\n if ( !strcmp(*(const char **)(8LL * k + a1), \"*\") || !strcmp(*(const char **)(8LL * k + a1), \"\n {\n while (v15[v15[k]] != v15[k]) v15[k] = v15[v15[k]];\n while (v15[v15[k + 1]] != v15[k + 1]) v15[k + 1] = v15[v15[k + 1]];\n if (!strcmp(*(const char **)(8LL * k + a1), \"*\")) {\n v4 = v15[k];\n v5 = ptr[v4] * ptr[v15[k + 1]];\n } else {\n v4 = v15[k];\n v5 = (int)ptr[v4] / (int)ptr[v15[k + 1]];\n }\n ptr[v4] = v5;\n v15[k + 1] = v15[k];\n }\n }\n for (m = 0; m < a3; ++m) {\n if (!strcmp(*(const char **)(8LL * m + a1), L\"+-\") ||\n !strcmp(*(const char **)(8LL * m + a1), L\"-\")) {\n while (v15[v15[m]] != v15[m]) v15[m] = v15[v15[m]];\n while (v15[v15[m + 1]] != v15[m + 1]) v15[m + 1] = v15[v15[m + 1]];\n if (!strcmp(*(const char **)(8LL * m + a1), L\"+-\"))\n ptr[v15[m]] += ptr[v15[m + 1]];\n else\n ptr[v15[m]] -= ptr[v15[m + 1]];\n v15[m + 1] = v15[m];\n }\n }\n v13 = *ptr;\n free(ptr);\n free(v15);\n return v13;\n}" + }, + { + "index": "HumanEval-C-160", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n#include \n", + "func": "int func0(const char **operato, const int *operand, int operato_size,\n int operand_size) {\n int *num = (int *)malloc(operand_size * sizeof(int));\n int *posto = (int *)malloc(operand_size * sizeof(int));\n for (int i = 0; i < operand_size; i++) {\n num[i] = operand[i];\n posto[i] = i;\n }\n for (int i = 0; i < operato_size; i++) {\n if (strcmp(operato[i], \"**\") == 0) {\n while (posto[posto[i]] != posto[i]) posto[i] = posto[posto[i]];\n while (posto[posto[i + 1]] != posto[i + 1])\n posto[i + 1] = posto[posto[i + 1]];\n num[posto[i]] = pow(num[posto[i]], num[posto[i + 1]]);\n posto[i + 1] = posto[i];\n }\n }\n for (int i = 0; i < operato_size; i++) {\n if (strcmp(operato[i], \"*\") == 0 || strcmp(operato[i], \"//\") == 0) {\n while (posto[posto[i]] != posto[i]) posto[i] = posto[posto[i]];\n while (posto[posto[i + 1]] != posto[i + 1])\n posto[i + 1] = posto[posto[i + 1]];\n if (strcmp(operato[i], \"*\") == 0)\n num[posto[i]] *= num[posto[i + 1]];\n else\n num[posto[i]] /= num[posto[i + 1]];\n posto[i + 1] = posto[i];\n }\n }\n for (int i = 0; i < operato_size; i++) {\n if (strcmp(operato[i], \"+\") == 0 || strcmp(operato[i], \"-\") == 0) {\n while (posto[posto[i]] != posto[i]) posto[i] = posto[posto[i]];\n while (posto[posto[i + 1]] != posto[i + 1])\n posto[i + 1] = posto[posto[i + 1]];\n if (strcmp(operato[i], \"+\") == 0)\n num[posto[i]] += num[posto[i + 1]];\n else\n num[posto[i]] -= num[posto[i + 1]];\n posto[i + 1] = posto[i];\n }\n }\n int result = num[0];\n free(num);\n free(posto);\n return result;\n}", + "test": "#include \n\nint main() {\n const char *operators1[] = {\"**\", \"*\", \"+\"};\n int operands1[] = {2, 3, 4, 5};\n assert(func0(operators1, operands1, 3, 4) == 37);\n\n const char *operators2[] = {\"+\", \"*\", \"-\"};\n int operands2[] = {2, 3, 4, 5};\n assert(func0(operators2, operands2, 3, 4) == 9);\n\n const char *operators3[] = {\"//\", \"*\"};\n int operands3[] = {7, 3, 4};\n assert(func0(operators3, operands3, 2, 3) == 8);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 38h\nmov [rsp+68h+var_40], rdi\nmov rbp, rsi\nmov r12d, edx\nmov r15d, ecx\nmovsxd r14, ecx\nlea rbx, ds:0[r14*4]\nmov rdi, rbx; size\ncall _malloc\nmov r13, rax\nmov rdi, rbx; size\ncall _malloc\nmov rbx, rax\ntest r15d, r15d\njle short loc_1249\nmov eax, 0\nloc_1234:\nmov edx, [rbp+rax*4+0]\nmov [r13+rax*4+0], edx\nmov [rbx+rax*4], eax\nadd rax, 1\ncmp r14, rax\njnz short loc_1234\nloc_1249:\ntest r12d, r12d\njle loc_14E7\nmov r15, [rsp+68h+var_40]\nmov [rsp+68h+var_50], r15\nmov r14, rbx\nmovsxd r12, r12d\nlea rax, [rbx+r12*4]\nmov [rsp+68h+var_60], rax\nmov r12, rbx\njmp short loc_12BF\nloc_1270:\nmov eax, [rbp+0]\nmov dword ptr [rsp+68h+s1], eax\ncdqe\nlea rdi, [r13+rax*4+0]\nmov [rsp+68h+var_48], rdi\npxor xmm0, xmm0\ncvtsi2sd xmm0, dword ptr [rdi]; x\npxor xmm1, xmm1\ncvtsi2sd xmm1, dword ptr [r13+rsi+0]; y\ncall _pow\ncvttsd2si eax, xmm0\nmov rdi, [rsp+68h+var_48]\nmov [rdi], eax\nmov eax, dword ptr [rsp+68h+s1]\nmov [rbp+4], eax\nloc_12AD:\nadd r15, 8\nadd r12, 4\nmov rax, [rsp+68h+var_60]\ncmp r12, rax\njz short loc_1326\nloc_12BF:\nmov rdi, [r15]; s1\nlea rsi, s2; \"**\"\ncall _strcmp\ntest eax, eax\njnz short loc_12AD\nmov rbp, r12\nmov edx, [r12]\nmovsxd rax, edx\nmov eax, [rbx+rax*4]\ncmp edx, eax\njz short loc_12F1\nloc_12E3:\nmov [rbp+0], eax\nmov edx, eax\ncdqe\nmov eax, [rbx+rax*4]\ncmp eax, edx\njnz short loc_12E3\nloc_12F1:\nmov edx, [rbp+4]\nmovsxd rax, edx\nlea rsi, ds:0[rax*4]\nmov eax, [rbx+rax*4]\ncmp edx, eax\njz loc_1270\nloc_130A:\nmov [rbp+4], eax\nmovsxd rdx, eax\nlea rsi, ds:0[rdx*4]\nmov ecx, eax\nmov eax, [rbx+rdx*4]\ncmp eax, ecx\njnz short loc_130A\njmp loc_1270\nloc_1326:\nmov r15, rbx\nmov rax, [rsp+68h+var_40]\nmov [rsp+68h+var_48], rax\njmp loc_13C8\nloc_1338:\nmov rbp, r15\nmov edx, [r15]\nmovsxd rax, edx\nmov eax, [rbx+rax*4]\ncmp edx, eax\njz short loc_1356\nloc_1348:\nmov [rbp+0], eax\nmov edx, eax\ncdqe\nmov eax, [rbx+rax*4]\ncmp eax, edx\njnz short loc_1348\nloc_1356:\nmov edx, [rbp+4]\nmovsxd rax, edx\nlea r12, ds:0[rax*4]\nmov eax, [rbx+rax*4]\ncmp edx, eax\njz short loc_1382\nloc_136B:\nmov [rbp+4], eax\nmovsxd rdx, eax\nlea r12, ds:0[rdx*4]\nmov ecx, eax\nmov eax, [rbx+rdx*4]\ncmp eax, ecx\njnz short loc_136B\nloc_1382:\nlea rsi, s2+1; s2\nmov rdi, [rsp+68h+s1]; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1406\nmovsxd rax, dword ptr [rbp+0]\nlea rdx, [r13+rax*4+0]\nmov eax, [rdx]\nimul eax, [r13+r12+0]\nmov [rdx], eax\nloc_13AA:\nmov eax, [rbp+0]\nmov [rbp+4], eax\nloc_13B0:\nadd [rsp+68h+var_48], 8\nadd r15, 4\nmov rax, [rsp+68h+var_60]\ncmp r15, rax\njz loc_14A0\nloc_13C8:\nmov rax, [rsp+68h+var_48]\nmov rax, [rax]\nmov [rsp+68h+s1], rax\nlea rsi, s2+1; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz loc_1338\nlea rsi, asc_2007; \"//\"\nmov rdi, [rsp+68h+s1]; s1\ncall _strcmp\ntest eax, eax\njnz short loc_13B0\njmp loc_1338\nloc_1406:\nmovsxd rax, dword ptr [rbp+0]\nlea rcx, [r13+rax*4+0]\nmov eax, [rcx]\ncdq\nidiv dword ptr [r13+r12+0]\nmov [rcx], eax\njmp short loc_13AA\nloc_141B:\nmov rbp, r14\nmov edx, [r14]\nmovsxd rax, edx\nmov eax, [rbx+rax*4]\ncmp edx, eax\njz short loc_1439\nloc_142B:\nmov [rbp+0], eax\nmov edx, eax\ncdqe\nmov eax, [rbx+rax*4]\ncmp eax, edx\njnz short loc_142B\nloc_1439:\nmov edx, [rbp+4]\nmovsxd rax, edx\nlea r12, ds:0[rax*4]\nmov eax, [rbx+rax*4]\ncmp edx, eax\njz short loc_1465\nloc_144E:\nmov [rbp+4], eax\nmovsxd rdx, eax\nlea r12, ds:0[rdx*4]\nmov ecx, eax\nmov eax, [rbx+rdx*4]\ncmp eax, ecx\njnz short loc_144E\nloc_1465:\nlea rsi, asc_200A; \"+\"\nmov rdi, r15; s1\ncall _strcmp\ntest eax, eax\njnz short loc_14D7\nmovsxd rax, dword ptr [rbp+0]\nmov edx, [r13+r12+0]\nadd [r13+rax*4+0], edx\nloc_1486:\nmov eax, [rbp+0]\nmov [rbp+4], eax\nloc_148C:\nadd [rsp+68h+var_50], 8\nadd r14, 4\nmov rax, [rsp+68h+var_60]\ncmp r14, rax\njz short loc_14E7\nloc_14A0:\nmov rax, [rsp+68h+var_50]\nmov r15, [rax]\nlea rsi, asc_200A; \"+\"\nmov rdi, r15; s1\ncall _strcmp\ntest eax, eax\njz loc_141B\nlea rsi, asc_200C; \"-\"\nmov rdi, r15; s1\ncall _strcmp\ntest eax, eax\njnz short loc_148C\njmp loc_141B\nloc_14D7:\nmovsxd rax, dword ptr [rbp+0]\nmov edx, [r13+r12+0]\nsub [r13+rax*4+0], edx\njmp short loc_1486\nloc_14E7:\nmov ebp, [r13+0]\nmov rdi, r13; ptr\ncall _free\nmov rdi, rbx; ptr\ncall _free\nmov eax, ebp\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char **a1, __int64 a2, int a3, int a4)\n{\n __int64 v6; // r14\n size_t v7; // rbx\n unsigned int *v8; // r13\n int *v9; // rbx\n __int64 v10; // rax\n const char **v11; // r15\n int *v12; // r14\n int *v13; // r12\n int *v14; // rdi\n int v15; // eax\n int v16; // edx\n int v17; // edx\n __int64 v18; // rsi\n int v19; // eax\n int v20; // ecx\n int *v21; // r15\n int v22; // eax\n int v23; // edx\n int v24; // edx\n __int64 v25; // r12\n int v26; // eax\n int v27; // ecx\n int v28; // eax\n int v29; // edx\n int v30; // edx\n __int64 v31; // r12\n int v32; // eax\n int v33; // ecx\n const char *v34; // r15\n unsigned int v35; // ebp\n int *v37; // [rsp+8h] [rbp-60h]\n int s1a; // [rsp+10h] [rbp-58h]\n char *s1; // [rsp+10h] [rbp-58h]\n const char **v40; // [rsp+18h] [rbp-50h]\n const char **v41; // [rsp+20h] [rbp-48h]\n\n v6 = a4;\n v7 = 4LL * a4;\n v8 = (unsigned int *)malloc(v7);\n v9 = (int *)malloc(v7);\n if ( a4 > 0 )\n {\n v10 = 0LL;\n do\n {\n v8[v10] = *(_DWORD *)(a2 + 4 * v10);\n v9[v10] = v10;\n ++v10;\n }\n while ( v6 != v10 );\n }\n if ( a3 > 0 )\n {\n v11 = a1;\n v40 = a1;\n v12 = v9;\n v37 = &v9[a3];\n v13 = v9;\n do\n {\n if ( !strcmp(*v11, \"**\") )\n {\n v15 = v9[*v13];\n if ( *v13 != v15 )\n {\n do\n {\n *v13 = v15;\n v16 = v15;\n v15 = v9[v15];\n }\n while ( v15 != v16 );\n }\n v17 = v13[1];\n v18 = v17;\n v19 = v9[v18];\n if ( v17 != v19 )\n {\n do\n {\n v13[1] = v19;\n v18 = v19;\n v20 = v19;\n v19 = v9[v18];\n }\n while ( v19 != v20 );\n }\n s1a = *v13;\n v14 = (int *)&v8[*v13];\n *v14 = (int)pow((double)*v14, (double)(int)v8[v18]);\n v13[1] = s1a;\n }\n ++v11;\n ++v13;\n }\n while ( v13 != v37 );\n v21 = v9;\n v41 = a1;\n do\n {\n s1 = (char *)*v41;\n if ( !strcmp(*v41, \"*\") || !strcmp(s1, \"//\") )\n {\n v22 = v9[*v21];\n if ( *v21 != v22 )\n {\n do\n {\n *v21 = v22;\n v23 = v22;\n v22 = v9[v22];\n }\n while ( v22 != v23 );\n }\n v24 = v21[1];\n v25 = v24;\n v26 = v9[v25];\n if ( v24 != v26 )\n {\n do\n {\n v21[1] = v26;\n v25 = v26;\n v27 = v26;\n v26 = v9[v25];\n }\n while ( v26 != v27 );\n }\n if ( !strcmp(s1, \"*\") )\n v8[*v21] *= v8[v25];\n else\n v8[*v21] = (int)v8[*v21] / (int)v8[v25];\n v21[1] = *v21;\n }\n ++v41;\n ++v21;\n }\n while ( v21 != v37 );\n do\n {\n v34 = *v40;\n if ( !strcmp(*v40, \"+\") || !strcmp(v34, \"-\") )\n {\n v28 = v9[*v12];\n if ( *v12 != v28 )\n {\n do\n {\n *v12 = v28;\n v29 = v28;\n v28 = v9[v28];\n }\n while ( v28 != v29 );\n }\n v30 = v12[1];\n v31 = v30;\n v32 = v9[v31];\n if ( v30 != v32 )\n {\n do\n {\n v12[1] = v32;\n v31 = v32;\n v33 = v32;\n v32 = v9[v31];\n }\n while ( v32 != v33 );\n }\n if ( !strcmp(v34, \"+\") )\n v8[*v12] += v8[v31];\n else\n v8[*v12] -= v8[v31];\n v12[1] = *v12;\n }\n ++v40;\n ++v12;\n }\n while ( v12 != v37 );\n }\n v35 = *v8;\n free(v8);\n free(v9);\n return v35;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 38h\nmov [rsp+68h+var_40], rdi\nmov rbp, rsi\nmov r12d, edx\nmov r15d, ecx\nmovsxd r14, ecx\nlea rbx, ds:0[r14*4]\nmov rdi, rbx; size\ncall _malloc\nmov r13, rax\nmov rdi, rbx; size\ncall _malloc\nmov rbx, rax\ntest r15d, r15d\njle short loc_1249\nmov eax, 0\nloc_1234:\nmov edx, [rbp+rax*4+0]\nmov [r13+rax*4+0], edx\nmov [rbx+rax*4], eax\nadd rax, 1\ncmp r14, rax\njnz short loc_1234\nloc_1249:\ntest r12d, r12d\njle loc_14E7\nmov r15, [rsp+68h+var_40]\nmov [rsp+68h+var_50], r15\nmov r14, rbx\nmovsxd r12, r12d\nlea rax, [rbx+r12*4]\nmov [rsp+68h+var_60], rax\nmov r12, rbx\njmp short loc_12BF\nloc_1270:\nmov eax, [rbp+0]\nmov dword ptr [rsp+68h+s1], eax\ncdqe\nlea rdi, [r13+rax*4+0]\nmov [rsp+68h+var_48], rdi\npxor xmm0, xmm0\ncvtsi2sd xmm0, dword ptr [rdi]; x\npxor xmm1, xmm1\ncvtsi2sd xmm1, dword ptr [r13+rsi+0]; y\ncall _pow\ncvttsd2si eax, xmm0\nmov rdi, [rsp+68h+var_48]\nmov [rdi], eax\nmov eax, dword ptr [rsp+68h+s1]\nmov [rbp+4], eax\nloc_12AD:\nadd r15, 8\nadd r12, 4\nmov rax, [rsp+68h+var_60]\ncmp r12, rax\njz short loc_1326\nloc_12BF:\nmov rdi, [r15]; s1\nlea rsi, s2; \"**\"\ncall _strcmp\ntest eax, eax\njnz short loc_12AD\nmov rbp, r12\nmov edx, [r12]\nmovsxd rax, edx\nmov eax, [rbx+rax*4]\ncmp edx, eax\njz short loc_12F1\nloc_12E3:\nmov [rbp+0], eax\nmov edx, eax\ncdqe\nmov eax, [rbx+rax*4]\ncmp eax, edx\njnz short loc_12E3\nloc_12F1:\nmov edx, [rbp+4]\nmovsxd rax, edx\nlea rsi, ds:0[rax*4]\nmov eax, [rbx+rax*4]\ncmp edx, eax\njz loc_1270\nloc_130A:\nmov [rbp+4], eax\nmovsxd rdx, eax\nlea rsi, ds:0[rdx*4]\nmov ecx, eax\nmov eax, [rbx+rdx*4]\ncmp eax, ecx\njnz short loc_130A\njmp loc_1270\nloc_1326:\nmov r15, rbx\nmov rax, [rsp+68h+var_40]\nmov [rsp+68h+var_48], rax\njmp loc_13C8\nloc_1338:\nmov rbp, r15\nmov edx, [r15]\nmovsxd rax, edx\nmov eax, [rbx+rax*4]\ncmp edx, eax\njz short loc_1356\nloc_1348:\nmov [rbp+0], eax\nmov edx, eax\ncdqe\nmov eax, [rbx+rax*4]\ncmp eax, edx\njnz short loc_1348\nloc_1356:\nmov edx, [rbp+4]\nmovsxd rax, edx\nlea r12, ds:0[rax*4]\nmov eax, [rbx+rax*4]\ncmp edx, eax\njz short loc_1382\nloc_136B:\nmov [rbp+4], eax\nmovsxd rdx, eax\nlea r12, ds:0[rdx*4]\nmov ecx, eax\nmov eax, [rbx+rdx*4]\ncmp eax, ecx\njnz short loc_136B\nloc_1382:\nlea rsi, s2+1; s2\nmov rdi, [rsp+68h+s1]; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1406\nmovsxd rax, dword ptr [rbp+0]\nlea rdx, [r13+rax*4+0]\nmov eax, [rdx]\nimul eax, [r13+r12+0]\nmov [rdx], eax\nloc_13AA:\nmov eax, [rbp+0]\nmov [rbp+4], eax\nloc_13B0:\nadd [rsp+68h+var_48], 8\nadd r15, 4\nmov rax, [rsp+68h+var_60]\ncmp r15, rax\njz loc_14A0\nloc_13C8:\nmov rax, [rsp+68h+var_48]\nmov rax, [rax]\nmov [rsp+68h+s1], rax\nlea rsi, s2+1; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz loc_1338\nlea rsi, asc_2007; \"//\"\nmov rdi, [rsp+68h+s1]; s1\ncall _strcmp\ntest eax, eax\njnz short loc_13B0\njmp loc_1338\nloc_1406:\nmovsxd rax, dword ptr [rbp+0]\nlea rcx, [r13+rax*4+0]\nmov eax, [rcx]\ncdq\nidiv dword ptr [r13+r12+0]\nmov [rcx], eax\njmp short loc_13AA\nloc_141B:\nmov rbp, r14\nmov edx, [r14]\nmovsxd rax, edx\nmov eax, [rbx+rax*4]\ncmp edx, eax\njz short loc_1439\nloc_142B:\nmov [rbp+0], eax\nmov edx, eax\ncdqe\nmov eax, [rbx+rax*4]\ncmp eax, edx\njnz short loc_142B\nloc_1439:\nmov edx, [rbp+4]\nmovsxd rax, edx\nlea r12, ds:0[rax*4]\nmov eax, [rbx+rax*4]\ncmp edx, eax\njz short loc_1465\nloc_144E:\nmov [rbp+4], eax\nmovsxd rdx, eax\nlea r12, ds:0[rdx*4]\nmov ecx, eax\nmov eax, [rbx+rdx*4]\ncmp eax, ecx\njnz short loc_144E\nloc_1465:\nlea rsi, asc_200A; \"+\"\nmov rdi, r15; s1\ncall _strcmp\ntest eax, eax\njnz short loc_14D7\nmovsxd rax, dword ptr [rbp+0]\nmov edx, [r13+r12+0]\nadd [r13+rax*4+0], edx\nloc_1486:\nmov eax, [rbp+0]\nmov [rbp+4], eax\nloc_148C:\nadd [rsp+68h+var_50], 8\nadd r14, 4\nmov rax, [rsp+68h+var_60]\ncmp r14, rax\njz short loc_14E7\nloc_14A0:\nmov rax, [rsp+68h+var_50]\nmov r15, [rax]\nlea rsi, asc_200A; \"+\"\nmov rdi, r15; s1\ncall _strcmp\ntest eax, eax\njz loc_141B\nlea rsi, asc_200C; \"-\"\nmov rdi, r15; s1\ncall _strcmp\ntest eax, eax\njnz short loc_148C\njmp loc_141B\nloc_14D7:\nmovsxd rax, dword ptr [rbp+0]\nmov edx, [r13+r12+0]\nsub [r13+rax*4+0], edx\njmp short loc_1486\nloc_14E7:\nmov ebp, [r13+0]\nmov rdi, r13; ptr\ncall _free\nmov rdi, rbx; ptr\ncall _free\nmov eax, ebp\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11E9(const char **a1, __int64 a2, int a3, int a4)\n{\n __int64 v6; // r14\n size_t v7; // rbx\n unsigned int *v8; // r13\n int *v9; // rbx\n __int64 v10; // rax\n const char **v11; // r15\n int *v12; // r14\n int *v13; // r12\n int *v14; // rdi\n int v15; // eax\n int v16; // edx\n int v17; // edx\n __int64 v18; // rsi\n int v19; // eax\n int v20; // ecx\n int *v21; // r15\n int v22; // eax\n int v23; // edx\n int v24; // edx\n __int64 v25; // r12\n int v26; // eax\n int v27; // ecx\n int v28; // eax\n int v29; // edx\n int v30; // edx\n __int64 v31; // r12\n int v32; // eax\n int v33; // ecx\n const char *v34; // r15\n unsigned int v35; // ebp\n int *v37; // [rsp+8h] [rbp-60h]\n int s1a; // [rsp+10h] [rbp-58h]\n char *s1; // [rsp+10h] [rbp-58h]\n const char **v40; // [rsp+18h] [rbp-50h]\n const char **v41; // [rsp+20h] [rbp-48h]\n\n v6 = a4;\n v7 = 4LL * a4;\n v8 = (unsigned int *)malloc(v7);\n v9 = (int *)malloc(v7);\n if ( a4 > 0 )\n {\n v10 = 0LL;\n do\n {\n v8[v10] = *(_DWORD *)(a2 + 4 * v10);\n v9[v10] = v10;\n ++v10;\n }\n while ( v6 != v10 );\n }\n if ( a3 > 0 )\n {\n v11 = a1;\n v40 = a1;\n v12 = v9;\n v37 = &v9[a3];\n v13 = v9;\n do\n {\n if ( !strcmp(*v11, \"**\") )\n {\n v15 = v9[*v13];\n if ( *v13 != v15 )\n {\n do\n {\n *v13 = v15;\n v16 = v15;\n v15 = v9[v15];\n }\n while ( v15 != v16 );\n }\n v17 = v13[1];\n v18 = v17;\n v19 = v9[v18];\n if ( v17 != v19 )\n {\n do\n {\n v13[1] = v19;\n v18 = v19;\n v20 = v19;\n v19 = v9[v18];\n }\n while ( v19 != v20 );\n }\n s1a = *v13;\n v14 = (int *)&v8[*v13];\n *v14 = (int)pow((double)*v14, (double)(int)v8[v18]);\n v13[1] = s1a;\n }\n ++v11;\n ++v13;\n }\n while ( v13 != v37 );\n v21 = v9;\n v41 = a1;\n do\n {\n s1 = (char *)*v41;\n if ( !strcmp(*v41, \"*\") || !strcmp(s1, \"//\") )\n {\n v22 = v9[*v21];\n if ( *v21 != v22 )\n {\n do\n {\n *v21 = v22;\n v23 = v22;\n v22 = v9[v22];\n }\n while ( v22 != v23 );\n }\n v24 = v21[1];\n v25 = v24;\n v26 = v9[v25];\n if ( v24 != v26 )\n {\n do\n {\n v21[1] = v26;\n v25 = v26;\n v27 = v26;\n v26 = v9[v25];\n }\n while ( v26 != v27 );\n }\n if ( !strcmp(s1, \"*\") )\n v8[*v21] *= v8[v25];\n else\n v8[*v21] = (int)v8[*v21] / (int)v8[v25];\n v21[1] = *v21;\n }\n ++v41;\n ++v21;\n }\n while ( v21 != v37 );\n do\n {\n v34 = *v40;\n if ( !strcmp(*v40, \"+\") || !strcmp(v34, \"-\") )\n {\n v28 = v9[*v12];\n if ( *v12 != v28 )\n {\n do\n {\n *v12 = v28;\n v29 = v28;\n v28 = v9[v28];\n }\n while ( v28 != v29 );\n }\n v30 = v12[1];\n v31 = v30;\n v32 = v9[v31];\n if ( v30 != v32 )\n {\n do\n {\n v12[1] = v32;\n v31 = v32;\n v33 = v32;\n v32 = v9[v31];\n }\n while ( v32 != v33 );\n }\n if ( !strcmp(v34, \"+\") )\n v8[*v12] += v8[v31];\n else\n v8[*v12] -= v8[v31];\n v12[1] = *v12;\n }\n ++v40;\n ++v12;\n }\n while ( v12 != v37 );\n }\n v35 = *v8;\n free(v8);\n free(v9);\n return v35;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11E9(const char **a1, long long a2, int a3, int a4) {\n long long v6;\n unsigned int v7;\n unsigned int *v8;\n int *v9;\n long long v10;\n const char **v11;\n int *v12;\n int *v13;\n int *v14;\n int v15;\n int v16;\n int v17;\n long long v18;\n int v19;\n int v20;\n int *v21;\n int v22;\n int v23;\n int v24;\n long long v25;\n int v26;\n int v27;\n int v28;\n int v29;\n int v30;\n long long v31;\n int v32;\n int v33;\n const char *v34;\n unsigned int v35;\n int *v37;\n int s1a;\n char *s1;\n const char **v40;\n const char **v41;\n v6 = a4;\n v7 = 4LL * a4;\n v8 = (unsigned int *)malloc(v7);\n v9 = (int *)malloc(v7);\n if (a4 > 0) {\n v10 = 0LL;\n do {\n v8[v10] = *(uint32_t *)(a2 + 4 * v10);\n v9[v10] = v10;\n ++v10;\n } while (v6 != v10);\n }\n if (a3 > 0) {\n v11 = a1;\n v40 = a1;\n v12 = v9;\n v37 = &v9[a3];\n v13 = v9;\n do {\n if (!strcmp(*v11, \"**\")) {\n v15 = v9[*v13];\n if (*v13 != v15) {\n do {\n *v13 = v15;\n v16 = v15;\n v15 = v9[v15];\n } while (v15 != v16);\n }\n v17 = v13[1];\n v18 = v17;\n v19 = v9[v18];\n if (v17 != v19) {\n do {\n v13[1] = v19;\n v18 = v19;\n v20 = v19;\n v19 = v9[v18];\n } while (v19 != v20);\n }\n s1a = *v13;\n v14 = (int *)&v8[*v13];\n *v14 = (int)pow((double)*v14, (double)(int)v8[v18]);\n v13[1] = s1a;\n }\n ++v11;\n ++v13;\n } while (v13 != v37);\n v21 = v9;\n v41 = a1;\n do {\n s1 = (char *)*v41;\n if ( !strcmp(*v41, \"*\") || !strcmp(s1, \"\n {\n v22 = v9[*v21];\n if (*v21 != v22) {\n do {\n *v21 = v22;\n v23 = v22;\n v22 = v9[v22];\n } while (v22 != v23);\n }\n v24 = v21[1];\n v25 = v24;\n v26 = v9[v25];\n if (v24 != v26) {\n do {\n v21[1] = v26;\n v25 = v26;\n v27 = v26;\n v26 = v9[v25];\n } while (v26 != v27);\n }\n if (!strcmp(s1, \"*\"))\n v8[*v21] *= v8[v25];\n else\n v8[*v21] = (int)v8[*v21] / (int)v8[v25];\n v21[1] = *v21;\n }\n ++v41;\n ++v21;\n } while (v21 != v37);\n do {\n v34 = *v40;\n if (!strcmp(*v40, \"+\") || !strcmp(v34, \"-\")) {\n v28 = v9[*v12];\n if (*v12 != v28) {\n do {\n *v12 = v28;\n v29 = v28;\n v28 = v9[v28];\n } while (v28 != v29);\n }\n v30 = v12[1];\n v31 = v30;\n v32 = v9[v31];\n if (v30 != v32) {\n do {\n v12[1] = v32;\n v31 = v32;\n v33 = v32;\n v32 = v9[v31];\n } while (v32 != v33);\n }\n if (!strcmp(v34, \"+\"))\n v8[*v12] += v8[v31];\n else\n v8[*v12] -= v8[v31];\n v12[1] = *v12;\n }\n ++v40;\n ++v12;\n } while (v12 != v37);\n }\n v35 = *v8;\n free(v8);\n free(v9);\n return v35;\n}", + "ida_pseudo_norm": "long long func0(const char **a1, long long a2, int a3, int a4) {\n long long v6;\n unsigned int v7;\n unsigned int *v8;\n int *v9;\n long long v10;\n const char **v11;\n int *v12;\n int *v13;\n int *v14;\n int v15;\n int v16;\n int v17;\n long long v18;\n int v19;\n int v20;\n int *v21;\n int v22;\n int v23;\n int v24;\n long long v25;\n int v26;\n int v27;\n int v28;\n int v29;\n int v30;\n long long v31;\n int v32;\n int v33;\n const char *v34;\n unsigned int v35;\n int *v37;\n int s1a;\n char *s1;\n const char **v40;\n const char **v41;\n v6 = a4;\n v7 = 4LL * a4;\n v8 = (unsigned int *)malloc(v7);\n v9 = (int *)malloc(v7);\n if (a4 > 0) {\n v10 = 0LL;\n do {\n v8[v10] = *(uint32_t *)(a2 + 4 * v10);\n v9[v10] = v10;\n ++v10;\n } while (v6 != v10);\n }\n if (a3 > 0) {\n v11 = a1;\n v40 = a1;\n v12 = v9;\n v37 = &v9[a3];\n v13 = v9;\n do {\n if (!strcmp(*v11, \"**\")) {\n v15 = v9[*v13];\n if (*v13 != v15) {\n do {\n *v13 = v15;\n v16 = v15;\n v15 = v9[v15];\n } while (v15 != v16);\n }\n v17 = v13[1];\n v18 = v17;\n v19 = v9[v18];\n if (v17 != v19) {\n do {\n v13[1] = v19;\n v18 = v19;\n v20 = v19;\n v19 = v9[v18];\n } while (v19 != v20);\n }\n s1a = *v13;\n v14 = (int *)&v8[*v13];\n *v14 = (int)pow((double)*v14, (double)(int)v8[v18]);\n v13[1] = s1a;\n }\n ++v11;\n ++v13;\n } while (v13 != v37);\n v21 = v9;\n v41 = a1;\n do {\n s1 = (char *)*v41;\n if ( !strcmp(*v41, \"*\") || !strcmp(s1, \"\n {\n v22 = v9[*v21];\n if (*v21 != v22) {\n do {\n *v21 = v22;\n v23 = v22;\n v22 = v9[v22];\n } while (v22 != v23);\n }\n v24 = v21[1];\n v25 = v24;\n v26 = v9[v25];\n if (v24 != v26) {\n do {\n v21[1] = v26;\n v25 = v26;\n v27 = v26;\n v26 = v9[v25];\n } while (v26 != v27);\n }\n if (!strcmp(s1, \"*\"))\n v8[*v21] *= v8[v25];\n else\n v8[*v21] = (int)v8[*v21] / (int)v8[v25];\n v21[1] = *v21;\n }\n ++v41;\n ++v21;\n } while (v21 != v37);\n do {\n v34 = *v40;\n if (!strcmp(*v40, \"+\") || !strcmp(v34, \"-\")) {\n v28 = v9[*v12];\n if (*v12 != v28) {\n do {\n *v12 = v28;\n v29 = v28;\n v28 = v9[v28];\n } while (v28 != v29);\n }\n v30 = v12[1];\n v31 = v30;\n v32 = v9[v31];\n if (v30 != v32) {\n do {\n v12[1] = v32;\n v31 = v32;\n v33 = v32;\n v32 = v9[v31];\n } while (v32 != v33);\n }\n if (!strcmp(v34, \"+\"))\n v8[*v12] += v8[v31];\n else\n v8[*v12] -= v8[v31];\n v12[1] = *v12;\n }\n ++v40;\n ++v12;\n } while (v12 != v37);\n }\n v35 = *v8;\n free(v8);\n free(v9);\n return v35;\n}" + }, + { + "index": "HumanEval-C-160", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n#include \n", + "func": "int func0(const char **operato, const int *operand, int operato_size,\n int operand_size) {\n int *num = (int *)malloc(operand_size * sizeof(int));\n int *posto = (int *)malloc(operand_size * sizeof(int));\n for (int i = 0; i < operand_size; i++) {\n num[i] = operand[i];\n posto[i] = i;\n }\n for (int i = 0; i < operato_size; i++) {\n if (strcmp(operato[i], \"**\") == 0) {\n while (posto[posto[i]] != posto[i]) posto[i] = posto[posto[i]];\n while (posto[posto[i + 1]] != posto[i + 1])\n posto[i + 1] = posto[posto[i + 1]];\n num[posto[i]] = pow(num[posto[i]], num[posto[i + 1]]);\n posto[i + 1] = posto[i];\n }\n }\n for (int i = 0; i < operato_size; i++) {\n if (strcmp(operato[i], \"*\") == 0 || strcmp(operato[i], \"//\") == 0) {\n while (posto[posto[i]] != posto[i]) posto[i] = posto[posto[i]];\n while (posto[posto[i + 1]] != posto[i + 1])\n posto[i + 1] = posto[posto[i + 1]];\n if (strcmp(operato[i], \"*\") == 0)\n num[posto[i]] *= num[posto[i + 1]];\n else\n num[posto[i]] /= num[posto[i + 1]];\n posto[i + 1] = posto[i];\n }\n }\n for (int i = 0; i < operato_size; i++) {\n if (strcmp(operato[i], \"+\") == 0 || strcmp(operato[i], \"-\") == 0) {\n while (posto[posto[i]] != posto[i]) posto[i] = posto[posto[i]];\n while (posto[posto[i + 1]] != posto[i + 1])\n posto[i + 1] = posto[posto[i + 1]];\n if (strcmp(operato[i], \"+\") == 0)\n num[posto[i]] += num[posto[i + 1]];\n else\n num[posto[i]] -= num[posto[i + 1]];\n posto[i + 1] = posto[i];\n }\n }\n int result = num[0];\n free(num);\n free(posto);\n return result;\n}", + "test": "#include \n\nint main() {\n const char *operators1[] = {\"**\", \"*\", \"+\"};\n int operands1[] = {2, 3, 4, 5};\n assert(func0(operators1, operands1, 3, 4) == 37);\n\n const char *operators2[] = {\"+\", \"*\", \"-\"};\n int operands2[] = {2, 3, 4, 5};\n assert(func0(operators2, operands2, 3, 4) == 9);\n\n const char *operators3[] = {\"//\", \"*\"};\n int operands3[] = {7, 3, 4};\n assert(func0(operators3, operands3, 2, 3) == 8);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\nmovsxd r15, ecx\npush r14\nmov r14d, edx\npush r13\npush r12\npush rbp\nmov rbp, rsi\npush rbx\nlea rbx, ds:0[r15*4]\nsub rsp, 28h\nmov [rsp+58h+var_48], rdi\nmov rdi, rbx; size\ncall _malloc\nmov rdi, rbx; size\nmov r12, rax\ncall _malloc\nmov rbx, rax\ntest r15d, r15d\njle short loc_1423\nmov edx, r15d\nmov rsi, rbp; src\nmov rdi, r12; dest\nshl rdx, 2; n\ncall _memcpy\nxor eax, eax\ntest r15b, 1\njz short loc_1410\nmov dword ptr [rbx], 0\nmov eax, 1\ncmp r15, 1\njz short loc_1423\nxchg ax, ax\nloc_1410:\nmov [rbx+rax*4], eax\nlea rdx, [rax+1]\nadd rax, 2\nmov [rbx+rdx*4], edx\ncmp r15, rax\njnz short loc_1410\nloc_1423:\ntest r14d, r14d\njle loc_1670\nmovsxd rdi, r14d\nmov rax, [rsp+58h+var_48]\nlea rdx, [rbx+4]\nmov [rsp+58h+var_40], rdi\nmov r13, rax\nmov r14, rax\nlea rbp, [rax+rdi*8]\nnop word ptr [rax+rax+00000000h]\nloc_1450:\nmov rax, [r14]\ncmp byte ptr [rax], 2Ah ; '*'\njnz loc_14F7\ncmp byte ptr [rax+1], 2Ah ; '*'\njnz loc_14F7\ncmp byte ptr [rax+2], 0\njnz loc_14F7\nmovsxd rax, dword ptr [rdx-4]\nmov r15, rax\nmov eax, [rbx+rax*4]\ncmp r15d, eax\njz short loc_1490\nnop\nloc_1480:\ncdqe\nmov [rdx-4], eax\nmov r15, rax\nmov eax, [rbx+rax*4]\ncmp eax, r15d\njnz short loc_1480\nloc_1490:\nmovsxd rax, dword ptr [rdx]\nmov rcx, rax\nlea r9, ds:0[rax*4]\nmov eax, [rbx+rax*4]\ncmp ecx, eax\njz short loc_14BE\nnop dword ptr [rax]\nloc_14A8:\nmovsxd rcx, eax\nmov [rdx], eax\nmov esi, eax\nmov eax, [rbx+rcx*4]\nlea r9, ds:0[rcx*4]\ncmp eax, esi\njnz short loc_14A8\nloc_14BE:\nmovsxd rax, r15d\npxor xmm0, xmm0\npxor xmm1, xmm1\nmov [rsp+58h+var_50], rdx\ncvtsi2sd xmm1, dword ptr [r12+r9]; y\nlea rax, [r12+rax*4]\ncvtsi2sd xmm0, dword ptr [rax]; x\nmov [rsp+58h+var_58], rax\ncall _pow\nmov rax, [rsp+58h+var_58]\nmov rdx, [rsp+58h+var_50]\ncvttsd2si ecx, xmm0\nmov [rdx], r15d\nmov [rax], ecx\nloc_14F7:\nadd r14, 8\nadd rdx, 4\ncmp rbp, r14\njnz loc_1450\nmov rax, [rsp+58h+var_40]\nmov rbp, [rsp+58h+var_48]\nmov rdi, rbx\nmov rsi, rbx\nlea r8, [rbx+rax*4]\nnop dword ptr [rax+00h]\nloc_1520:\nmov r11, [rbp+0]\nmovzx r10d, byte ptr [r11]\ncmp r10d, 2Ah ; '*'\njnz loc_16B0\ncmp byte ptr [r11+1], 0\njnz loc_16B0\nloc_153D:\nmovsxd rax, dword ptr [rsi]\nmov rcx, rax\nmov eax, [rbx+rax*4]\ncmp ecx, eax\njz short loc_155E\nnop word ptr [rax+rax+00h]\nloc_1550:\ncdqe\nmov [rsi], eax\nmov rcx, rax\nmov eax, [rbx+rax*4]\ncmp eax, ecx\njnz short loc_1550\nloc_155E:\nmovsxd rax, dword ptr [rsi+4]\nmov rdx, rax\nlea r14, ds:0[rax*4]\nmov eax, [rbx+rax*4]\ncmp edx, eax\njz short loc_1591\nnop dword ptr [rax+00h]\nloc_1578:\nmovsxd rdx, eax\nmov [rsi+4], eax\nmov r9d, eax\nmov eax, [rbx+rdx*4]\nlea r14, ds:0[rdx*4]\ncmp eax, r9d\njnz short loc_1578\nloc_1591:\nsub r10d, 2Ah ; '*'\njnz short loc_159C\nmovzx r10d, byte ptr [r11+1]\nloc_159C:\nmovsxd rax, ecx\nmov r11d, [r12+r14]\nlea r9, [r12+rax*4]\nmov eax, [r9]\ntest r10d, r10d\njnz loc_16D8\nimul eax, r11d\nloc_15B7:\nmov [r9], eax\nmov [rsi+4], ecx\nloc_15BD:\nadd rsi, 4\nadd rbp, 8\ncmp r8, rsi\njnz loc_1520\nxchg ax, ax\nloc_15D0:\nmov rax, [r13+0]\nmovzx r10d, byte ptr [rax]\ncmp r10d, 2Bh ; '+'\njnz loc_1698\ncmp byte ptr [rax+1], 0\njnz loc_1698\nloc_15EC:\nmovsxd rax, dword ptr [rdi]\nmov rdx, rax\nmov eax, [rbx+rax*4]\ncmp edx, eax\njz short loc_160E\nnop dword ptr [rax+00000000h]\nloc_1600:\ncdqe\nmov [rdi], eax\nmov rdx, rax\nmov eax, [rbx+rax*4]\ncmp eax, edx\njnz short loc_1600\nloc_160E:\nmovsxd rax, dword ptr [rdi+4]\nmov rcx, rax\nlea r9, ds:0[rax*4]\nmov eax, [rbx+rax*4]\ncmp ecx, eax\njz short loc_163F\nnop dword ptr [rax+00h]\nloc_1628:\nmovsxd rcx, eax\nmov [rdi+4], eax\nmov esi, eax\nmov eax, [rbx+rcx*4]\nlea r9, ds:0[rcx*4]\ncmp eax, esi\njnz short loc_1628\nloc_163F:\nmovsxd rax, edx\nmov esi, [r12+r9]\nmov [rdi+4], edx\nlea rcx, [r12+rax*4]\nmov eax, [rcx]\nlea r9d, [rax+rsi]\nsub eax, esi\ncmp r10d, 2Bh ; '+'\ncmovz eax, r9d\nmov [rcx], eax\nloc_165F:\nadd rdi, 4\nadd r13, 8\ncmp r8, rdi\njnz loc_15D0\nloc_1670:\nmov rdi, r12; ptr\nmov ebp, [r12]\ncall _free\nmov rdi, rbx; ptr\ncall _free\nadd rsp, 28h\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1698:\ncmp r10d, 2Dh ; '-'\njnz short loc_165F\ncmp byte ptr [rax+1], 0\njz loc_15EC\njmp short loc_165F\nloc_16B0:\ncmp byte ptr [r11], 2Fh ; '/'\njnz loc_15BD\ncmp byte ptr [r11+1], 2Fh ; '/'\njnz loc_15BD\ncmp byte ptr [r11+2], 0\njz loc_153D\njmp loc_15BD\nloc_16D8:\ncdq\nidiv r11d\njmp loc_15B7", + "ida_pseudo": "__int64 __fastcall func0(unsigned __int8 **a1, const void *a2, int a3, int a4)\n{\n __int64 v4; // r15\n size_t v6; // rbx\n _DWORD *v7; // r12\n int *v8; // rbx\n __int64 v9; // rax\n __int64 v10; // rdx\n int *v11; // rdx\n unsigned __int8 **v12; // r13\n unsigned __int8 **v13; // r14\n unsigned __int8 *v14; // rax\n __int64 v15; // r15\n int i; // eax\n __int64 v17; // rcx\n __int64 v18; // r9\n int v19; // eax\n __int64 v20; // rcx\n int v21; // esi\n double v22; // xmm0_8\n unsigned __int8 **v23; // rbp\n int *v24; // rdi\n int *v25; // rsi\n int *v26; // r8\n _BYTE *v27; // r11\n int v28; // r10d\n __int64 v29; // rcx\n int j; // eax\n __int64 v31; // rdx\n __int64 v32; // r14\n int v33; // eax\n __int64 v34; // rdx\n int v35; // r9d\n int v36; // r10d\n int v37; // r11d\n int *v38; // r9\n int v39; // eax\n int v40; // eax\n __int64 v41; // rax\n int v42; // r10d\n __int64 v43; // rdx\n int k; // eax\n __int64 v45; // rcx\n __int64 v46; // r9\n int v47; // eax\n __int64 v48; // rcx\n int v49; // esi\n int v50; // esi\n _DWORD *v51; // rcx\n int v52; // eax\n unsigned int v53; // ebp\n int *v55; // [rsp+8h] [rbp-50h]\n __int64 v56; // [rsp+18h] [rbp-40h]\n\n v4 = a4;\n v6 = 4LL * a4;\n v7 = malloc(v6);\n v8 = (int *)malloc(v6);\n if ( (int)v4 > 0 )\n {\n memcpy(v7, a2, 4LL * (unsigned int)v4);\n v9 = 0LL;\n if ( (v4 & 1) == 0 || (*v8 = 0, v9 = 1LL, v4 != 1) )\n {\n do\n {\n v8[v9] = v9;\n v10 = v9 + 1;\n v9 += 2LL;\n v8[v10] = v10;\n }\n while ( v4 != v9 );\n }\n }\n if ( a3 > 0 )\n {\n v11 = v8 + 1;\n v56 = a3;\n v12 = a1;\n v13 = a1;\n do\n {\n v14 = *v13;\n if ( **v13 == 42 && v14[1] == 42 && !v14[2] )\n {\n v15 = *(v11 - 1);\n for ( i = v8[v15]; i != (_DWORD)v15; i = v8[i] )\n {\n *(v11 - 1) = i;\n LODWORD(v15) = i;\n }\n v17 = *v11;\n v18 = v17;\n v19 = v8[v17];\n if ( (_DWORD)v17 != v19 )\n {\n do\n {\n v20 = v19;\n *v11 = v19;\n v21 = v19;\n v19 = v8[v19];\n v18 = v20;\n }\n while ( v19 != v21 );\n }\n v55 = v11;\n v22 = pow((double)(int)v7[(int)v15], (double)(int)v7[v18]);\n v11 = v55;\n *v55 = v15;\n v7[(int)v15] = (int)v22;\n }\n ++v13;\n ++v11;\n }\n while ( &a1[v56] != v13 );\n v23 = a1;\n v24 = v8;\n v25 = v8;\n v26 = &v8[v56];\n do\n {\n v27 = *v23;\n v28 = **v23;\n if ( v28 == 42 && !v27[1] || *v27 == 47 && v27[1] == 47 && !v27[2] )\n {\n v29 = *v25;\n for ( j = v8[v29]; j != (_DWORD)v29; j = v8[j] )\n {\n *v25 = j;\n LODWORD(v29) = j;\n }\n v31 = v25[1];\n v32 = v31;\n v33 = v8[v31];\n if ( (_DWORD)v31 != v33 )\n {\n do\n {\n v34 = v33;\n v25[1] = v33;\n v35 = v33;\n v33 = v8[v33];\n v32 = v34;\n }\n while ( v33 != v35 );\n }\n v36 = v28 - 42;\n if ( !v36 )\n v36 = (unsigned __int8)v27[1];\n v37 = v7[v32];\n v38 = &v7[(int)v29];\n v39 = *v38;\n if ( v36 )\n v40 = v39 / v37;\n else\n v40 = v37 * v39;\n *v38 = v40;\n v25[1] = v29;\n }\n ++v25;\n ++v23;\n }\n while ( v26 != v25 );\n do\n {\n v41 = (__int64)*v12;\n v42 = **v12;\n if ( v42 == 43 && !*(_BYTE *)(v41 + 1) || v42 == 45 && !*(_BYTE *)(v41 + 1) )\n {\n v43 = *v24;\n for ( k = v8[v43]; k != (_DWORD)v43; k = v8[k] )\n {\n *v24 = k;\n LODWORD(v43) = k;\n }\n v45 = v24[1];\n v46 = v45;\n v47 = v8[v45];\n if ( (_DWORD)v45 != v47 )\n {\n do\n {\n v48 = v47;\n v24[1] = v47;\n v49 = v47;\n v47 = v8[v47];\n v46 = v48;\n }\n while ( v47 != v49 );\n }\n v50 = v7[v46];\n v24[1] = v43;\n v51 = &v7[(int)v43];\n v52 = *v51 - v50;\n if ( v42 == 43 )\n v52 = *v51 + v50;\n *v51 = v52;\n }\n ++v24;\n ++v12;\n }\n while ( v26 != v24 );\n }\n v53 = *v7;\n free(v7);\n free(v8);\n return v53;\n}", + "ida_strip_asm": "sub_13A0:\nendbr64\npush r15\nmovsxd r15, ecx\npush r14\nmov r14d, edx\npush r13\npush r12\npush rbp\nmov rbp, rsi\npush rbx\nlea rbx, ds:0[r15*4]\nsub rsp, 28h\nmov [rsp+58h+var_48], rdi\nmov rdi, rbx; size\ncall _malloc\nmov rdi, rbx; size\nmov r12, rax\ncall _malloc\nmov rbx, rax\ntest r15d, r15d\njle short loc_1423\nmov edx, r15d\nmov rsi, rbp; src\nmov rdi, r12; dest\nshl rdx, 2; n\ncall _memcpy\nxor eax, eax\ntest r15b, 1\njz short loc_1410\nmov dword ptr [rbx], 0\nmov eax, 1\ncmp r15, 1\njz short loc_1423\nxchg ax, ax\nloc_1410:\nmov [rbx+rax*4], eax\nlea rdx, [rax+1]\nadd rax, 2\nmov [rbx+rdx*4], edx\ncmp r15, rax\njnz short loc_1410\nloc_1423:\ntest r14d, r14d\njle loc_1670\nmovsxd rdi, r14d\nmov rax, [rsp+58h+var_48]\nlea rdx, [rbx+4]\nmov [rsp+58h+var_40], rdi\nmov r13, rax\nmov r14, rax\nlea rbp, [rax+rdi*8]\nnop word ptr [rax+rax+00000000h]\nloc_1450:\nmov rax, [r14]\ncmp byte ptr [rax], 2Ah ; '*'\njnz loc_14F7\ncmp byte ptr [rax+1], 2Ah ; '*'\njnz loc_14F7\ncmp byte ptr [rax+2], 0\njnz loc_14F7\nmovsxd rax, dword ptr [rdx-4]\nmov r15, rax\nmov eax, [rbx+rax*4]\ncmp r15d, eax\njz short loc_1490\nnop\nloc_1480:\ncdqe\nmov [rdx-4], eax\nmov r15, rax\nmov eax, [rbx+rax*4]\ncmp eax, r15d\njnz short loc_1480\nloc_1490:\nmovsxd rax, dword ptr [rdx]\nmov rcx, rax\nlea r9, ds:0[rax*4]\nmov eax, [rbx+rax*4]\ncmp ecx, eax\njz short loc_14BE\nnop dword ptr [rax]\nloc_14A8:\nmovsxd rcx, eax\nmov [rdx], eax\nmov esi, eax\nmov eax, [rbx+rcx*4]\nlea r9, ds:0[rcx*4]\ncmp eax, esi\njnz short loc_14A8\nloc_14BE:\nmovsxd rax, r15d\npxor xmm0, xmm0\npxor xmm1, xmm1\nmov [rsp+58h+var_50], rdx\ncvtsi2sd xmm1, dword ptr [r12+r9]; y\nlea rax, [r12+rax*4]\ncvtsi2sd xmm0, dword ptr [rax]; x\nmov [rsp+58h+var_58], rax\ncall _pow\nmov rax, [rsp+58h+var_58]\nmov rdx, [rsp+58h+var_50]\ncvttsd2si ecx, xmm0\nmov [rdx], r15d\nmov [rax], ecx\nloc_14F7:\nadd r14, 8\nadd rdx, 4\ncmp rbp, r14\njnz loc_1450\nmov rax, [rsp+58h+var_40]\nmov rbp, [rsp+58h+var_48]\nmov rdi, rbx\nmov rsi, rbx\nlea r8, [rbx+rax*4]\nnop dword ptr [rax+00h]\nloc_1520:\nmov r11, [rbp+0]\nmovzx r10d, byte ptr [r11]\ncmp r10d, 2Ah ; '*'\njnz loc_16B0\ncmp byte ptr [r11+1], 0\njnz loc_16B0\nloc_153D:\nmovsxd rax, dword ptr [rsi]\nmov rcx, rax\nmov eax, [rbx+rax*4]\ncmp ecx, eax\njz short loc_155E\nnop word ptr [rax+rax+00h]\nloc_1550:\ncdqe\nmov [rsi], eax\nmov rcx, rax\nmov eax, [rbx+rax*4]\ncmp eax, ecx\njnz short loc_1550\nloc_155E:\nmovsxd rax, dword ptr [rsi+4]\nmov rdx, rax\nlea r14, ds:0[rax*4]\nmov eax, [rbx+rax*4]\ncmp edx, eax\njz short loc_1591\nnop dword ptr [rax+00h]\nloc_1578:\nmovsxd rdx, eax\nmov [rsi+4], eax\nmov r9d, eax\nmov eax, [rbx+rdx*4]\nlea r14, ds:0[rdx*4]\ncmp eax, r9d\njnz short loc_1578\nloc_1591:\nsub r10d, 2Ah ; '*'\njnz short loc_159C\nmovzx r10d, byte ptr [r11+1]\nloc_159C:\nmovsxd rax, ecx\nmov r11d, [r12+r14]\nlea r9, [r12+rax*4]\nmov eax, [r9]\ntest r10d, r10d\njnz loc_16D8\nimul eax, r11d\nloc_15B7:\nmov [r9], eax\nmov [rsi+4], ecx\nloc_15BD:\nadd rsi, 4\nadd rbp, 8\ncmp r8, rsi\njnz loc_1520\nxchg ax, ax\nloc_15D0:\nmov rax, [r13+0]\nmovzx r10d, byte ptr [rax]\ncmp r10d, 2Bh ; '+'\njnz loc_1698\ncmp byte ptr [rax+1], 0\njnz loc_1698\nloc_15EC:\nmovsxd rax, dword ptr [rdi]\nmov rdx, rax\nmov eax, [rbx+rax*4]\ncmp edx, eax\njz short loc_160E\nnop dword ptr [rax+00000000h]\nloc_1600:\ncdqe\nmov [rdi], eax\nmov rdx, rax\nmov eax, [rbx+rax*4]\ncmp eax, edx\njnz short loc_1600\nloc_160E:\nmovsxd rax, dword ptr [rdi+4]\nmov rcx, rax\nlea r9, ds:0[rax*4]\nmov eax, [rbx+rax*4]\ncmp ecx, eax\njz short loc_163F\nnop dword ptr [rax+00h]\nloc_1628:\nmovsxd rcx, eax\nmov [rdi+4], eax\nmov esi, eax\nmov eax, [rbx+rcx*4]\nlea r9, ds:0[rcx*4]\ncmp eax, esi\njnz short loc_1628\nloc_163F:\nmovsxd rax, edx\nmov esi, [r12+r9]\nmov [rdi+4], edx\nlea rcx, [r12+rax*4]\nmov eax, [rcx]\nlea r9d, [rax+rsi]\nsub eax, esi\ncmp r10d, 2Bh ; '+'\ncmovz eax, r9d\nmov [rcx], eax\nloc_165F:\nadd rdi, 4\nadd r13, 8\ncmp r8, rdi\njnz loc_15D0\nloc_1670:\nmov rdi, r12; ptr\nmov ebp, [r12]\ncall _free\nmov rdi, rbx; ptr\ncall _free\nadd rsp, 28h\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1698:\ncmp r10d, 2Dh ; '-'\njnz short loc_165F\ncmp byte ptr [rax+1], 0\njz loc_15EC\njmp short loc_165F\nloc_16B0:\ncmp byte ptr [r11], 2Fh ; '/'\njnz loc_15BD\ncmp byte ptr [r11+1], 2Fh ; '/'\njnz loc_15BD\ncmp byte ptr [r11+2], 0\njz loc_153D\njmp loc_15BD\nloc_16D8:\ncdq\nidiv r11d\njmp loc_15B7", + "ida_strip_pseudo": "__int64 __fastcall sub_13A0(unsigned __int8 **a1, const void *a2, int a3, int a4)\n{\n __int64 v4; // r15\n size_t v6; // rbx\n _DWORD *v7; // r12\n int *v8; // rbx\n __int64 v9; // rax\n __int64 v10; // rdx\n int *v11; // rdx\n unsigned __int8 **v12; // r13\n unsigned __int8 **v13; // r14\n unsigned __int8 *v14; // rax\n __int64 v15; // r15\n int i; // eax\n __int64 v17; // rcx\n __int64 v18; // r9\n int v19; // eax\n __int64 v20; // rcx\n int v21; // esi\n double v22; // xmm0_8\n unsigned __int8 **v23; // rbp\n int *v24; // rdi\n int *v25; // rsi\n int *v26; // r8\n _BYTE *v27; // r11\n int v28; // r10d\n __int64 v29; // rcx\n int j; // eax\n __int64 v31; // rdx\n __int64 v32; // r14\n int v33; // eax\n __int64 v34; // rdx\n int v35; // r9d\n int v36; // r10d\n int v37; // r11d\n int *v38; // r9\n int v39; // eax\n int v40; // eax\n __int64 v41; // rax\n int v42; // r10d\n __int64 v43; // rdx\n int k; // eax\n __int64 v45; // rcx\n __int64 v46; // r9\n int v47; // eax\n __int64 v48; // rcx\n int v49; // esi\n int v50; // esi\n _DWORD *v51; // rcx\n int v52; // eax\n unsigned int v53; // ebp\n int *v55; // [rsp+8h] [rbp-50h]\n __int64 v56; // [rsp+18h] [rbp-40h]\n\n v4 = a4;\n v6 = 4LL * a4;\n v7 = malloc(v6);\n v8 = (int *)malloc(v6);\n if ( (int)v4 > 0 )\n {\n memcpy(v7, a2, 4LL * (unsigned int)v4);\n v9 = 0LL;\n if ( (v4 & 1) == 0 || (*v8 = 0, v9 = 1LL, v4 != 1) )\n {\n do\n {\n v8[v9] = v9;\n v10 = v9 + 1;\n v9 += 2LL;\n v8[v10] = v10;\n }\n while ( v4 != v9 );\n }\n }\n if ( a3 > 0 )\n {\n v11 = v8 + 1;\n v56 = a3;\n v12 = a1;\n v13 = a1;\n do\n {\n v14 = *v13;\n if ( **v13 == 42 && v14[1] == 42 && !v14[2] )\n {\n v15 = *(v11 - 1);\n for ( i = v8[v15]; i != (_DWORD)v15; i = v8[i] )\n {\n *(v11 - 1) = i;\n LODWORD(v15) = i;\n }\n v17 = *v11;\n v18 = v17;\n v19 = v8[v17];\n if ( (_DWORD)v17 != v19 )\n {\n do\n {\n v20 = v19;\n *v11 = v19;\n v21 = v19;\n v19 = v8[v19];\n v18 = v20;\n }\n while ( v19 != v21 );\n }\n v55 = v11;\n v22 = pow((double)(int)v7[(int)v15], (double)(int)v7[v18]);\n v11 = v55;\n *v55 = v15;\n v7[(int)v15] = (int)v22;\n }\n ++v13;\n ++v11;\n }\n while ( &a1[v56] != v13 );\n v23 = a1;\n v24 = v8;\n v25 = v8;\n v26 = &v8[v56];\n do\n {\n v27 = *v23;\n v28 = **v23;\n if ( v28 == 42 && !v27[1] || *v27 == 47 && v27[1] == 47 && !v27[2] )\n {\n v29 = *v25;\n for ( j = v8[v29]; j != (_DWORD)v29; j = v8[j] )\n {\n *v25 = j;\n LODWORD(v29) = j;\n }\n v31 = v25[1];\n v32 = v31;\n v33 = v8[v31];\n if ( (_DWORD)v31 != v33 )\n {\n do\n {\n v34 = v33;\n v25[1] = v33;\n v35 = v33;\n v33 = v8[v33];\n v32 = v34;\n }\n while ( v33 != v35 );\n }\n v36 = v28 - 42;\n if ( !v36 )\n v36 = (unsigned __int8)v27[1];\n v37 = v7[v32];\n v38 = &v7[(int)v29];\n v39 = *v38;\n if ( v36 )\n v40 = v39 / v37;\n else\n v40 = v37 * v39;\n *v38 = v40;\n v25[1] = v29;\n }\n ++v25;\n ++v23;\n }\n while ( v26 != v25 );\n do\n {\n v41 = (__int64)*v12;\n v42 = **v12;\n if ( v42 == 43 && !*(_BYTE *)(v41 + 1) || v42 == 45 && !*(_BYTE *)(v41 + 1) )\n {\n v43 = *v24;\n for ( k = v8[v43]; k != (_DWORD)v43; k = v8[k] )\n {\n *v24 = k;\n LODWORD(v43) = k;\n }\n v45 = v24[1];\n v46 = v45;\n v47 = v8[v45];\n if ( (_DWORD)v45 != v47 )\n {\n do\n {\n v48 = v47;\n v24[1] = v47;\n v49 = v47;\n v47 = v8[v47];\n v46 = v48;\n }\n while ( v47 != v49 );\n }\n v50 = v7[v46];\n v24[1] = v43;\n v51 = &v7[(int)v43];\n v52 = *v51 - v50;\n if ( v42 == 43 )\n v52 = *v51 + v50;\n *v51 = v52;\n }\n ++v24;\n ++v12;\n }\n while ( v26 != v24 );\n }\n v53 = *v7;\n free(v7);\n free(v8);\n return v53;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_13A0(unsigned char **a1, const void *a2, int a3, int a4) {\n long long v4;\n unsigned int v6;\n uint32_t *v7;\n int *v8;\n long long v9;\n long long v10;\n int *v11;\n unsigned char **v12;\n unsigned char **v13;\n unsigned char *v14;\n long long v15;\n int i;\n long long v17;\n long long v18;\n int v19;\n long long v20;\n int v21;\n double v22;\n unsigned char **v23;\n int *v24;\n int *v25;\n int *v26;\n uint8_t *v27;\n int v28;\n long long v29;\n int j;\n long long v31;\n long long v32;\n int v33;\n long long v34;\n int v35;\n int v36;\n int v37;\n int *v38;\n int v39;\n int v40;\n long long v41;\n int v42;\n long long v43;\n int k;\n long long v45;\n long long v46;\n int v47;\n long long v48;\n int v49;\n int v50;\n uint32_t *v51;\n int v52;\n unsigned int v53;\n int *v55;\n long long v56;\n v4 = a4;\n v6 = 4LL * a4;\n v7 = malloc(v6);\n v8 = (int *)malloc(v6);\n if ((int)v4 > 0) {\n memcpy(v7, a2, 4LL * (unsigned int)v4);\n v9 = 0LL;\n if ((v4 & 1) == 0 || (*v8 = 0, v9 = 1LL, v4 != 1)) {\n do {\n v8[v9] = v9;\n v10 = v9 + 1;\n v9 += 2LL;\n v8[v10] = v10;\n } while (v4 != v9);\n }\n }\n if (a3 > 0) {\n v11 = v8 + 1;\n v56 = a3;\n v12 = a1;\n v13 = a1;\n do {\n v14 = *v13;\n if (**v13 == 42 && v14[1] == 42 && !v14[2]) {\n v15 = *(v11 - 1);\n for (i = v8[v15]; i != (uint32_t)v15; i = v8[i]) {\n *(v11 - 1) = i;\n LODWORD(v15) = i;\n }\n v17 = *v11;\n v18 = v17;\n v19 = v8[v17];\n if ((uint32_t)v17 != v19) {\n do {\n v20 = v19;\n *v11 = v19;\n v21 = v19;\n v19 = v8[v19];\n v18 = v20;\n } while (v19 != v21);\n }\n v55 = v11;\n v22 = pow((double)(int)v7[(int)v15], (double)(int)v7[v18]);\n v11 = v55;\n *v55 = v15;\n v7[(int)v15] = (int)v22;\n }\n ++v13;\n ++v11;\n } while (&a1[v56] != v13);\n v23 = a1;\n v24 = v8;\n v25 = v8;\n v26 = &v8[v56];\n do {\n v27 = *v23;\n v28 = **v23;\n if (v28 == 42 && !v27[1] || *v27 == 47 && v27[1] == 47 && !v27[2]) {\n v29 = *v25;\n for (j = v8[v29]; j != (uint32_t)v29; j = v8[j]) {\n *v25 = j;\n LODWORD(v29) = j;\n }\n v31 = v25[1];\n v32 = v31;\n v33 = v8[v31];\n if ((uint32_t)v31 != v33) {\n do {\n v34 = v33;\n v25[1] = v33;\n v35 = v33;\n v33 = v8[v33];\n v32 = v34;\n } while (v33 != v35);\n }\n v36 = v28 - 42;\n if (!v36) v36 = (unsigned char)v27[1];\n v37 = v7[v32];\n v38 = &v7[(int)v29];\n v39 = *v38;\n if (v36)\n v40 = v39 / v37;\n else\n v40 = v37 * v39;\n *v38 = v40;\n v25[1] = v29;\n }\n ++v25;\n ++v23;\n } while (v26 != v25);\n do {\n v41 = (long long)*v12;\n v42 = **v12;\n if (v42 == 43 && !*(uint8_t *)(v41 + 1) ||\n v42 == 45 && !*(uint8_t *)(v41 + 1)) {\n v43 = *v24;\n for (k = v8[v43]; k != (uint32_t)v43; k = v8[k]) {\n *v24 = k;\n LODWORD(v43) = k;\n }\n v45 = v24[1];\n v46 = v45;\n v47 = v8[v45];\n if ((uint32_t)v45 != v47) {\n do {\n v48 = v47;\n v24[1] = v47;\n v49 = v47;\n v47 = v8[v47];\n v46 = v48;\n } while (v47 != v49);\n }\n v50 = v7[v46];\n v24[1] = v43;\n v51 = &v7[(int)v43];\n v52 = *v51 - v50;\n if (v42 == 43) v52 = *v51 + v50;\n *v51 = v52;\n }\n ++v24;\n ++v12;\n } while (v26 != v24);\n }\n v53 = *v7;\n free(v7);\n free(v8);\n return v53;\n}", + "ida_pseudo_norm": "long long func0(unsigned char **a1, const void *a2, int a3, int a4) {\n long long v4;\n unsigned int v6;\n uint32_t *v7;\n int *v8;\n long long v9;\n long long v10;\n int *v11;\n unsigned char **v12;\n unsigned char **v13;\n unsigned char *v14;\n long long v15;\n int i;\n long long v17;\n long long v18;\n int v19;\n long long v20;\n int v21;\n double v22;\n unsigned char **v23;\n int *v24;\n int *v25;\n int *v26;\n uint8_t *v27;\n int v28;\n long long v29;\n int j;\n long long v31;\n long long v32;\n int v33;\n long long v34;\n int v35;\n int v36;\n int v37;\n int *v38;\n int v39;\n int v40;\n long long v41;\n int v42;\n long long v43;\n int k;\n long long v45;\n long long v46;\n int v47;\n long long v48;\n int v49;\n int v50;\n uint32_t *v51;\n int v52;\n unsigned int v53;\n int *v55;\n long long v56;\n v4 = a4;\n v6 = 4LL * a4;\n v7 = malloc(v6);\n v8 = (int *)malloc(v6);\n if ((int)v4 > 0) {\n memcpy(v7, a2, 4LL * (unsigned int)v4);\n v9 = 0LL;\n if ((v4 & 1) == 0 || (*v8 = 0, v9 = 1LL, v4 != 1)) {\n do {\n v8[v9] = v9;\n v10 = v9 + 1;\n v9 += 2LL;\n v8[v10] = v10;\n } while (v4 != v9);\n }\n }\n if (a3 > 0) {\n v11 = v8 + 1;\n v56 = a3;\n v12 = a1;\n v13 = a1;\n do {\n v14 = *v13;\n if (**v13 == 42 && v14[1] == 42 && !v14[2]) {\n v15 = *(v11 - 1);\n for (i = v8[v15]; i != (uint32_t)v15; i = v8[i]) {\n *(v11 - 1) = i;\n LODWORD(v15) = i;\n }\n v17 = *v11;\n v18 = v17;\n v19 = v8[v17];\n if ((uint32_t)v17 != v19) {\n do {\n v20 = v19;\n *v11 = v19;\n v21 = v19;\n v19 = v8[v19];\n v18 = v20;\n } while (v19 != v21);\n }\n v55 = v11;\n v22 = pow((double)(int)v7[(int)v15], (double)(int)v7[v18]);\n v11 = v55;\n *v55 = v15;\n v7[(int)v15] = (int)v22;\n }\n ++v13;\n ++v11;\n } while (&a1[v56] != v13);\n v23 = a1;\n v24 = v8;\n v25 = v8;\n v26 = &v8[v56];\n do {\n v27 = *v23;\n v28 = **v23;\n if (v28 == 42 && !v27[1] || *v27 == 47 && v27[1] == 47 && !v27[2]) {\n v29 = *v25;\n for (j = v8[v29]; j != (uint32_t)v29; j = v8[j]) {\n *v25 = j;\n LODWORD(v29) = j;\n }\n v31 = v25[1];\n v32 = v31;\n v33 = v8[v31];\n if ((uint32_t)v31 != v33) {\n do {\n v34 = v33;\n v25[1] = v33;\n v35 = v33;\n v33 = v8[v33];\n v32 = v34;\n } while (v33 != v35);\n }\n v36 = v28 - 42;\n if (!v36) v36 = (unsigned char)v27[1];\n v37 = v7[v32];\n v38 = &v7[(int)v29];\n v39 = *v38;\n if (v36)\n v40 = v39 / v37;\n else\n v40 = v37 * v39;\n *v38 = v40;\n v25[1] = v29;\n }\n ++v25;\n ++v23;\n } while (v26 != v25);\n do {\n v41 = (long long)*v12;\n v42 = **v12;\n if (v42 == 43 && !*(uint8_t *)(v41 + 1) ||\n v42 == 45 && !*(uint8_t *)(v41 + 1)) {\n v43 = *v24;\n for (k = v8[v43]; k != (uint32_t)v43; k = v8[k]) {\n *v24 = k;\n LODWORD(v43) = k;\n }\n v45 = v24[1];\n v46 = v45;\n v47 = v8[v45];\n if ((uint32_t)v45 != v47) {\n do {\n v48 = v47;\n v24[1] = v47;\n v49 = v47;\n v47 = v8[v47];\n v46 = v48;\n } while (v47 != v49);\n }\n v50 = v7[v46];\n v24[1] = v43;\n v51 = &v7[(int)v43];\n v52 = *v51 - v50;\n if (v42 == 43) v52 = *v51 + v50;\n *v51 = v52;\n }\n ++v24;\n ++v12;\n } while (v26 != v24);\n }\n v53 = *v7;\n free(v7);\n free(v8);\n return v53;\n}" + }, + { + "index": "HumanEval-C-160", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n#include \n", + "func": "int func0(const char **operato, const int *operand, int operato_size,\n int operand_size) {\n int *num = (int *)malloc(operand_size * sizeof(int));\n int *posto = (int *)malloc(operand_size * sizeof(int));\n for (int i = 0; i < operand_size; i++) {\n num[i] = operand[i];\n posto[i] = i;\n }\n for (int i = 0; i < operato_size; i++) {\n if (strcmp(operato[i], \"**\") == 0) {\n while (posto[posto[i]] != posto[i]) posto[i] = posto[posto[i]];\n while (posto[posto[i + 1]] != posto[i + 1])\n posto[i + 1] = posto[posto[i + 1]];\n num[posto[i]] = pow(num[posto[i]], num[posto[i + 1]]);\n posto[i + 1] = posto[i];\n }\n }\n for (int i = 0; i < operato_size; i++) {\n if (strcmp(operato[i], \"*\") == 0 || strcmp(operato[i], \"//\") == 0) {\n while (posto[posto[i]] != posto[i]) posto[i] = posto[posto[i]];\n while (posto[posto[i + 1]] != posto[i + 1])\n posto[i + 1] = posto[posto[i + 1]];\n if (strcmp(operato[i], \"*\") == 0)\n num[posto[i]] *= num[posto[i + 1]];\n else\n num[posto[i]] /= num[posto[i + 1]];\n posto[i + 1] = posto[i];\n }\n }\n for (int i = 0; i < operato_size; i++) {\n if (strcmp(operato[i], \"+\") == 0 || strcmp(operato[i], \"-\") == 0) {\n while (posto[posto[i]] != posto[i]) posto[i] = posto[posto[i]];\n while (posto[posto[i + 1]] != posto[i + 1])\n posto[i + 1] = posto[posto[i + 1]];\n if (strcmp(operato[i], \"+\") == 0)\n num[posto[i]] += num[posto[i + 1]];\n else\n num[posto[i]] -= num[posto[i + 1]];\n posto[i + 1] = posto[i];\n }\n }\n int result = num[0];\n free(num);\n free(posto);\n return result;\n}", + "test": "#include \n\nint main() {\n const char *operators1[] = {\"**\", \"*\", \"+\"};\n int operands1[] = {2, 3, 4, 5};\n assert(func0(operators1, operands1, 3, 4) == 37);\n\n const char *operators2[] = {\"+\", \"*\", \"-\"};\n int operands2[] = {2, 3, 4, 5};\n assert(func0(operators2, operands2, 3, 4) == 9);\n\n const char *operators3[] = {\"//\", \"*\"};\n int operands3[] = {7, 3, 4};\n assert(func0(operators3, operands3, 2, 3) == 8);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\nmov r15, rsi\npush r14\npush r13\nmov r13d, edx\npush r12\npush rbp\npush rbx\nmovsxd rbx, ecx\nmov r14, rbx\nshl rbx, 2\nsub rsp, 28h\nmov [rsp+58h+var_48], rdi\nmov rdi, rbx; size\ncall _malloc\nmov rdi, rbx; size\nmov r12, rax\ncall _malloc\nmov rbx, rax\ntest r14d, r14d\njle loc_146F\nmov edx, r14d\nmov rsi, r15; src\nmov rdi, r12; dest\nshl rdx, 2; n\ncall _memcpy\nlea eax, [r14-1]\ncmp eax, 2\njbe loc_1771\nmov edx, r14d\nmovdqa xmm0, cs:xmmword_20C0\nmovdqa xmm2, cs:xmmword_20D0\nmov rax, rbx\nshr edx, 2\nshl rdx, 4\nadd rdx, rbx\nnop dword ptr [rax]\nloc_1428:\nmovdqa xmm1, xmm0\nadd rax, 10h\npaddd xmm0, xmm2\nmovups xmmword ptr [rax-10h], xmm1\ncmp rdx, rax\njnz short loc_1428\ntest r14b, 3\njz short loc_146F\nmov eax, r14d\nand eax, 0FFFFFFFCh\nloc_1449:\nmovsxd rdx, eax\nmov [rbx+rdx*4], eax\nlea rcx, ds:0[rdx*4]\nlea edx, [rax+1]\ncmp r14d, edx\njle short loc_146F\nadd eax, 2\nmov [rbx+rcx+4], edx\ncmp r14d, eax\njle short loc_146F\nmov [rbx+rcx+8], eax\nloc_146F:\ntest r13d, r13d\njle loc_1700\nmovsxd rdi, r13d\nmov rax, [rsp+58h+var_48]\nlea r15, [rbx+4]\nmov [rsp+58h+var_40], rdi\nmov r14, rax\nmov r13, rax\nlea rbp, [rax+rdi*8]\nnop dword ptr [rax+rax+00h]\nloc_1498:\nmov rax, [r13+0]\ncmp byte ptr [rax], 2Ah ; '*'\njnz loc_155B\ncmp byte ptr [rax+1], 2Ah ; '*'\njnz loc_155B\ncmp byte ptr [rax+2], 0\njnz loc_155B\nmovsxd rax, dword ptr [r15-4]\nmov rcx, rax\nlea r8, ds:0[rax*4]\nmov eax, [rbx+rax*4]\ncmp ecx, eax\njz short loc_14E8\nnop\nloc_14D0:\nmovsxd rdx, eax\nmov [r15-4], eax\nmov ecx, eax\nmov eax, [rbx+rdx*4]\nlea r8, ds:0[rdx*4]\ncmp eax, ecx\njnz short loc_14D0\nloc_14E8:\nmovsxd rax, dword ptr [r15]\nmov rdx, rax\nlea r9, ds:0[rax*4]\nmov eax, [rbx+rax*4]\ncmp edx, eax\njz short loc_1526\nnop dword ptr [rax]\nloc_1500:\nmovsxd rdx, eax\nmov [r15], eax\nmov ecx, eax\nmov eax, [rbx+rdx*4]\nlea r9, ds:0[rdx*4]\ncmp eax, ecx\njnz short loc_1500\nmovsxd rax, dword ptr [r15-4]\nmov rcx, rax\nlea r8, ds:0[rax*4]\nloc_1526:\nadd r8, r12\npxor xmm0, xmm0\npxor xmm1, xmm1\nmov [rsp+58h+var_4C], ecx\ncvtsi2sd xmm0, dword ptr [r8]; x\nmov [rsp+58h+var_58], r8\ncvtsi2sd xmm1, dword ptr [r12+r9]; y\ncall _pow\nmov r8, [rsp+58h+var_58]\nmov ecx, [rsp+58h+var_4C]\ncvttsd2si edx, xmm0\nmov [r15], ecx\nmov [r8], edx\nloc_155B:\nadd r13, 8\nadd r15, 4\ncmp rbp, r13\njnz loc_1498\nmov rax, [rsp+58h+var_40]\nmov rbp, [rsp+58h+var_48]\nmov rsi, rbx\nmov rcx, rbx\nlea rdi, [rbx+rax*4]\nloc_1580:\nmov r10, [rbp+0]\nmovzx r9d, byte ptr [r10]\ncmp r9d, 2Ah ; '*'\njnz loc_1740\ncmp byte ptr [r10+1], 0\njnz loc_1740\nloc_159D:\nmovsxd rax, dword ptr [rcx]\nmov r8, rax\nlea r11, ds:0[rax*4]\nmov eax, [rbx+rax*4]\ncmp r8d, eax\njz short loc_15D0\nnop dword ptr [rax+rax+00h]\nloc_15B8:\nmovsxd rdx, eax\nmov [rcx], eax\nmov r8d, eax\nmov eax, [rbx+rdx*4]\nlea r11, ds:0[rdx*4]\ncmp eax, r8d\njnz short loc_15B8\nloc_15D0:\nmovsxd rax, dword ptr [rcx+4]\nmov rdx, rax\nlea r13, ds:0[rax*4]\nmov eax, [rbx+rax*4]\ncmp edx, eax\njz short loc_1613\nnop word ptr [rax+rax+00000000h]\nloc_15F0:\nmovsxd rdx, eax\nmov [rcx+4], eax\nmov r8d, eax\nmov eax, [rbx+rdx*4]\nlea r13, ds:0[rdx*4]\ncmp eax, r8d\njnz short loc_15F0\nmovsxd r11, dword ptr [rcx]\nmov r8, r11\nshl r11, 2\nloc_1613:\nsub r9d, 2Ah ; '*'\njnz short loc_161E\nmovzx r9d, byte ptr [r10+1]\nloc_161E:\nadd r11, r12\nmov r10d, [r12+r13]\nmov eax, [r11]\ntest r9d, r9d\njnz loc_1768\nimul eax, r10d\nloc_1635:\nmov [r11], eax\nmov [rcx+4], r8d\nloc_163C:\nadd rcx, 4\nadd rbp, 8\ncmp rcx, rdi\njnz loc_1580\nnop dword ptr [rax]\nloc_1650:\nmov rax, [r14]\nmovzx r10d, byte ptr [rax]\ncmp r10d, 2Bh ; '+'\njnz loc_1728\ncmp byte ptr [rax+1], 0\njnz loc_1728\nloc_166B:\nmovsxd rax, dword ptr [rsi]\nmov rcx, rax\nlea r8, ds:0[rax*4]\nmov eax, [rbx+rax*4]\ncmp ecx, eax\njz short loc_1696\nloc_1680:\nmovsxd rdx, eax\nmov [rsi], eax\nmov ecx, eax\nmov eax, [rbx+rdx*4]\nlea r8, ds:0[rdx*4]\ncmp eax, ecx\njnz short loc_1680\nloc_1696:\nmovsxd rax, dword ptr [rsi+4]\nmov rdx, rax\nlea r9, ds:0[rax*4]\nmov eax, [rbx+rax*4]\ncmp edx, eax\njz short loc_16D1\nnop dword ptr [rax+00h]\nloc_16B0:\nmovsxd rdx, eax\nmov [rsi+4], eax\nmov ecx, eax\nmov eax, [rbx+rdx*4]\nlea r9, ds:0[rdx*4]\ncmp eax, ecx\njnz short loc_16B0\nmovsxd r8, dword ptr [rsi]\nmov rcx, r8\nshl r8, 2\nloc_16D1:\nadd r8, r12\nmov edx, [r12+r9]\nmov [rsi+4], ecx\nmov eax, [r8]\nlea r9d, [rax+rdx]\nsub eax, edx\ncmp r10d, 2Bh ; '+'\ncmovz eax, r9d\nmov [r8], eax\nloc_16EF:\nadd rsi, 4\nadd r14, 8\ncmp rdi, rsi\njnz loc_1650\nloc_1700:\nmov rdi, r12; ptr\nmov ebp, [r12]\ncall _free\nmov rdi, rbx; ptr\ncall _free\nadd rsp, 28h\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1728:\ncmp r10d, 2Dh ; '-'\njnz short loc_16EF\ncmp byte ptr [rax+1], 0\njz loc_166B\njmp short loc_16EF\nloc_1740:\ncmp byte ptr [r10], 2Fh ; '/'\njnz loc_163C\ncmp byte ptr [r10+1], 2Fh ; '/'\njnz loc_163C\ncmp byte ptr [r10+2], 0\njz loc_159D\njmp loc_163C\nloc_1768:\ncdq\nidiv r10d\njmp loc_1635\nloc_1771:\nxor eax, eax\njmp loc_1449", + "ida_pseudo": "__int64 __fastcall func0(unsigned __int8 **a1, const void *a2, int a3, int a4)\n{\n size_t v6; // rbx\n _DWORD *v7; // r12\n int *v8; // rbx\n __m128i si128; // xmm0\n __m128i v10; // xmm2\n __m128i *v11; // rax\n __m128i v12; // xmm1\n int v13; // eax\n __int64 v14; // rcx\n int v15; // edx\n int v16; // eax\n int *v17; // r15\n unsigned __int8 **v18; // r14\n unsigned __int8 **v19; // r13\n unsigned __int8 *v20; // rax\n __int64 v21; // rcx\n __int64 v22; // r8\n int i; // eax\n __int64 v24; // rdx\n __int64 v25; // rdx\n __int64 v26; // r9\n int v27; // eax\n __int64 v28; // rdx\n int v29; // ecx\n double v30; // xmm0_8\n unsigned __int8 **v31; // rbp\n int *v32; // rsi\n int *v33; // rcx\n int *v34; // rdi\n _BYTE *v35; // r10\n int v36; // r9d\n __int64 v37; // r8\n __int64 v38; // r11\n int j; // eax\n __int64 v40; // rdx\n __int64 v41; // rdx\n __int64 v42; // r13\n int v43; // eax\n __int64 v44; // rdx\n int v45; // r8d\n int v46; // r9d\n int *v47; // r11\n int v48; // r10d\n int v49; // eax\n int v50; // eax\n __int64 v51; // rax\n int v52; // r10d\n __int64 v53; // rcx\n __int64 v54; // r8\n int k; // eax\n __int64 v56; // rdx\n __int64 v57; // rdx\n __int64 v58; // r9\n int v59; // eax\n __int64 v60; // rdx\n int v61; // ecx\n _DWORD *v62; // r8\n int v63; // edx\n int v64; // eax\n unsigned int v65; // ebp\n _DWORD *v67; // [rsp+0h] [rbp-58h]\n int v68; // [rsp+Ch] [rbp-4Ch]\n __int64 v69; // [rsp+18h] [rbp-40h]\n\n v6 = 4LL * a4;\n v7 = malloc(v6);\n v8 = (int *)malloc(v6);\n if ( a4 > 0 )\n {\n memcpy(v7, a2, 4LL * (unsigned int)a4);\n if ( (unsigned int)(a4 - 1) <= 2 )\n {\n v13 = 0;\n }\n else\n {\n si128 = _mm_load_si128((const __m128i *)&xmmword_20C0);\n v10 = _mm_load_si128((const __m128i *)&xmmword_20D0);\n v11 = (__m128i *)v8;\n do\n {\n v12 = si128;\n ++v11;\n si128 = _mm_add_epi32(si128, v10);\n v11[-1] = v12;\n }\n while ( &v8[4 * ((unsigned int)a4 >> 2)] != (int *)v11 );\n if ( (a4 & 3) == 0 )\n goto LABEL_10;\n v13 = a4 & 0x7FFFFFFC;\n }\n v8[v13] = v13;\n v14 = v13;\n v15 = v13 + 1;\n if ( a4 > v13 + 1 )\n {\n v16 = v13 + 2;\n v8[v14 + 1] = v15;\n if ( a4 > v16 )\n v8[v14 + 2] = v16;\n }\n }\nLABEL_10:\n if ( a3 > 0 )\n {\n v17 = v8 + 1;\n v69 = a3;\n v18 = a1;\n v19 = a1;\n do\n {\n v20 = *v19;\n if ( **v19 == 42 && v20[1] == 42 && !v20[2] )\n {\n v21 = *(v17 - 1);\n v22 = v21;\n for ( i = v8[v21]; i != (_DWORD)v21; v22 = v24 )\n {\n v24 = i;\n *(v17 - 1) = i;\n LODWORD(v21) = i;\n i = v8[i];\n }\n v25 = *v17;\n v26 = v25;\n v27 = v8[v25];\n if ( (_DWORD)v25 != v27 )\n {\n do\n {\n v28 = v27;\n *v17 = v27;\n v29 = v27;\n v27 = v8[v27];\n v26 = v28;\n }\n while ( v27 != v29 );\n v21 = *(v17 - 1);\n v22 = v21;\n }\n v68 = v21;\n v67 = &v7[v22];\n v30 = pow((double)(int)v7[v22], (double)(int)v7[v26]);\n *v17 = v68;\n *v67 = (int)v30;\n }\n ++v19;\n ++v17;\n }\n while ( &a1[v69] != v19 );\n v31 = a1;\n v32 = v8;\n v33 = v8;\n v34 = &v8[v69];\n do\n {\n v35 = *v31;\n v36 = **v31;\n if ( v36 == 42 && !v35[1] || *v35 == 47 && v35[1] == 47 && !v35[2] )\n {\n v37 = *v33;\n v38 = v37;\n for ( j = v8[v37]; j != (_DWORD)v37; v38 = v40 )\n {\n v40 = j;\n *v33 = j;\n LODWORD(v37) = j;\n j = v8[j];\n }\n v41 = v33[1];\n v42 = v41;\n v43 = v8[v41];\n if ( (_DWORD)v41 != v43 )\n {\n do\n {\n v44 = v43;\n v33[1] = v43;\n v45 = v43;\n v43 = v8[v43];\n v42 = v44;\n }\n while ( v43 != v45 );\n v37 = *v33;\n v38 = v37;\n }\n v46 = v36 - 42;\n if ( !v46 )\n v46 = (unsigned __int8)v35[1];\n v47 = &v7[v38];\n v48 = v7[v42];\n v49 = *v47;\n if ( v46 )\n v50 = v49 / v48;\n else\n v50 = v48 * v49;\n *v47 = v50;\n v33[1] = v37;\n }\n ++v33;\n ++v31;\n }\n while ( v33 != v34 );\n do\n {\n v51 = (__int64)*v18;\n v52 = **v18;\n if ( v52 == 43 && !*(_BYTE *)(v51 + 1) || v52 == 45 && !*(_BYTE *)(v51 + 1) )\n {\n v53 = *v32;\n v54 = v53;\n for ( k = v8[v53]; k != (_DWORD)v53; v54 = v56 )\n {\n v56 = k;\n *v32 = k;\n LODWORD(v53) = k;\n k = v8[k];\n }\n v57 = v32[1];\n v58 = v57;\n v59 = v8[v57];\n if ( (_DWORD)v57 != v59 )\n {\n do\n {\n v60 = v59;\n v32[1] = v59;\n v61 = v59;\n v59 = v8[v59];\n v58 = v60;\n }\n while ( v59 != v61 );\n v53 = *v32;\n v54 = v53;\n }\n v62 = &v7[v54];\n v63 = v7[v58];\n v32[1] = v53;\n v64 = *v62 - v63;\n if ( v52 == 43 )\n v64 = *v62 + v63;\n *v62 = v64;\n }\n ++v32;\n ++v18;\n }\n while ( v34 != v32 );\n }\n v65 = *v7;\n free(v7);\n free(v8);\n return v65;\n}", + "ida_strip_asm": "sub_13A0:\nendbr64\npush r15\nmov r15, rsi\npush r14\npush r13\nmov r13d, edx\npush r12\npush rbp\npush rbx\nmovsxd rbx, ecx\nmov r14, rbx\nshl rbx, 2\nsub rsp, 28h\nmov [rsp+58h+var_48], rdi\nmov rdi, rbx; size\ncall _malloc\nmov rdi, rbx; size\nmov r12, rax\ncall _malloc\nmov rbx, rax\ntest r14d, r14d\njle loc_146F\nmov edx, r14d\nmov rsi, r15; src\nmov rdi, r12; dest\nshl rdx, 2; n\ncall _memcpy\nlea eax, [r14-1]\ncmp eax, 2\njbe loc_1771\nmov edx, r14d\nmovdqa xmm0, cs:xmmword_20C0\nmovdqa xmm2, cs:xmmword_20D0\nmov rax, rbx\nshr edx, 2\nshl rdx, 4\nadd rdx, rbx\nnop dword ptr [rax]\nloc_1428:\nmovdqa xmm1, xmm0\nadd rax, 10h\npaddd xmm0, xmm2\nmovups xmmword ptr [rax-10h], xmm1\ncmp rdx, rax\njnz short loc_1428\ntest r14b, 3\njz short loc_146F\nmov eax, r14d\nand eax, 0FFFFFFFCh\nloc_1449:\nmovsxd rdx, eax\nmov [rbx+rdx*4], eax\nlea rcx, ds:0[rdx*4]\nlea edx, [rax+1]\ncmp r14d, edx\njle short loc_146F\nadd eax, 2\nmov [rbx+rcx+4], edx\ncmp r14d, eax\njle short loc_146F\nmov [rbx+rcx+8], eax\nloc_146F:\ntest r13d, r13d\njle loc_1700\nmovsxd rdi, r13d\nmov rax, [rsp+58h+var_48]\nlea r15, [rbx+4]\nmov [rsp+58h+var_40], rdi\nmov r14, rax\nmov r13, rax\nlea rbp, [rax+rdi*8]\nnop dword ptr [rax+rax+00h]\nloc_1498:\nmov rax, [r13+0]\ncmp byte ptr [rax], 2Ah ; '*'\njnz loc_155B\ncmp byte ptr [rax+1], 2Ah ; '*'\njnz loc_155B\ncmp byte ptr [rax+2], 0\njnz loc_155B\nmovsxd rax, dword ptr [r15-4]\nmov rcx, rax\nlea r8, ds:0[rax*4]\nmov eax, [rbx+rax*4]\ncmp ecx, eax\njz short loc_14E8\nnop\nloc_14D0:\nmovsxd rdx, eax\nmov [r15-4], eax\nmov ecx, eax\nmov eax, [rbx+rdx*4]\nlea r8, ds:0[rdx*4]\ncmp eax, ecx\njnz short loc_14D0\nloc_14E8:\nmovsxd rax, dword ptr [r15]\nmov rdx, rax\nlea r9, ds:0[rax*4]\nmov eax, [rbx+rax*4]\ncmp edx, eax\njz short loc_1526\nnop dword ptr [rax]\nloc_1500:\nmovsxd rdx, eax\nmov [r15], eax\nmov ecx, eax\nmov eax, [rbx+rdx*4]\nlea r9, ds:0[rdx*4]\ncmp eax, ecx\njnz short loc_1500\nmovsxd rax, dword ptr [r15-4]\nmov rcx, rax\nlea r8, ds:0[rax*4]\nloc_1526:\nadd r8, r12\npxor xmm0, xmm0\npxor xmm1, xmm1\nmov [rsp+58h+var_4C], ecx\ncvtsi2sd xmm0, dword ptr [r8]; x\nmov [rsp+58h+var_58], r8\ncvtsi2sd xmm1, dword ptr [r12+r9]; y\ncall _pow\nmov r8, [rsp+58h+var_58]\nmov ecx, [rsp+58h+var_4C]\ncvttsd2si edx, xmm0\nmov [r15], ecx\nmov [r8], edx\nloc_155B:\nadd r13, 8\nadd r15, 4\ncmp rbp, r13\njnz loc_1498\nmov rax, [rsp+58h+var_40]\nmov rbp, [rsp+58h+var_48]\nmov rsi, rbx\nmov rcx, rbx\nlea rdi, [rbx+rax*4]\nloc_1580:\nmov r10, [rbp+0]\nmovzx r9d, byte ptr [r10]\ncmp r9d, 2Ah ; '*'\njnz loc_1740\ncmp byte ptr [r10+1], 0\njnz loc_1740\nloc_159D:\nmovsxd rax, dword ptr [rcx]\nmov r8, rax\nlea r11, ds:0[rax*4]\nmov eax, [rbx+rax*4]\ncmp r8d, eax\njz short loc_15D0\nnop dword ptr [rax+rax+00h]\nloc_15B8:\nmovsxd rdx, eax\nmov [rcx], eax\nmov r8d, eax\nmov eax, [rbx+rdx*4]\nlea r11, ds:0[rdx*4]\ncmp eax, r8d\njnz short loc_15B8\nloc_15D0:\nmovsxd rax, dword ptr [rcx+4]\nmov rdx, rax\nlea r13, ds:0[rax*4]\nmov eax, [rbx+rax*4]\ncmp edx, eax\njz short loc_1613\nnop word ptr [rax+rax+00000000h]\nloc_15F0:\nmovsxd rdx, eax\nmov [rcx+4], eax\nmov r8d, eax\nmov eax, [rbx+rdx*4]\nlea r13, ds:0[rdx*4]\ncmp eax, r8d\njnz short loc_15F0\nmovsxd r11, dword ptr [rcx]\nmov r8, r11\nshl r11, 2\nloc_1613:\nsub r9d, 2Ah ; '*'\njnz short loc_161E\nmovzx r9d, byte ptr [r10+1]\nloc_161E:\nadd r11, r12\nmov r10d, [r12+r13]\nmov eax, [r11]\ntest r9d, r9d\njnz loc_1768\nimul eax, r10d\nloc_1635:\nmov [r11], eax\nmov [rcx+4], r8d\nloc_163C:\nadd rcx, 4\nadd rbp, 8\ncmp rcx, rdi\njnz loc_1580\nnop dword ptr [rax]\nloc_1650:\nmov rax, [r14]\nmovzx r10d, byte ptr [rax]\ncmp r10d, 2Bh ; '+'\njnz loc_1728\ncmp byte ptr [rax+1], 0\njnz loc_1728\nloc_166B:\nmovsxd rax, dword ptr [rsi]\nmov rcx, rax\nlea r8, ds:0[rax*4]\nmov eax, [rbx+rax*4]\ncmp ecx, eax\njz short loc_1696\nloc_1680:\nmovsxd rdx, eax\nmov [rsi], eax\nmov ecx, eax\nmov eax, [rbx+rdx*4]\nlea r8, ds:0[rdx*4]\ncmp eax, ecx\njnz short loc_1680\nloc_1696:\nmovsxd rax, dword ptr [rsi+4]\nmov rdx, rax\nlea r9, ds:0[rax*4]\nmov eax, [rbx+rax*4]\ncmp edx, eax\njz short loc_16D1\nnop dword ptr [rax+00h]\nloc_16B0:\nmovsxd rdx, eax\nmov [rsi+4], eax\nmov ecx, eax\nmov eax, [rbx+rdx*4]\nlea r9, ds:0[rdx*4]\ncmp eax, ecx\njnz short loc_16B0\nmovsxd r8, dword ptr [rsi]\nmov rcx, r8\nshl r8, 2\nloc_16D1:\nadd r8, r12\nmov edx, [r12+r9]\nmov [rsi+4], ecx\nmov eax, [r8]\nlea r9d, [rax+rdx]\nsub eax, edx\ncmp r10d, 2Bh ; '+'\ncmovz eax, r9d\nmov [r8], eax\nloc_16EF:\nadd rsi, 4\nadd r14, 8\ncmp rdi, rsi\njnz loc_1650\nloc_1700:\nmov rdi, r12; ptr\nmov ebp, [r12]\ncall _free\nmov rdi, rbx; ptr\ncall _free\nadd rsp, 28h\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1728:\ncmp r10d, 2Dh ; '-'\njnz short loc_16EF\ncmp byte ptr [rax+1], 0\njz loc_166B\njmp short loc_16EF\nloc_1740:\ncmp byte ptr [r10], 2Fh ; '/'\njnz loc_163C\ncmp byte ptr [r10+1], 2Fh ; '/'\njnz loc_163C\ncmp byte ptr [r10+2], 0\njz loc_159D\njmp loc_163C\nloc_1768:\ncdq\nidiv r10d\njmp loc_1635\nloc_1771:\nxor eax, eax\njmp loc_1449", + "ida_strip_pseudo": "__int64 __fastcall sub_13A0(unsigned __int8 **a1, const void *a2, int a3, int a4)\n{\n size_t v6; // rbx\n _DWORD *v7; // r12\n int *v8; // rbx\n __m128i si128; // xmm0\n __m128i v10; // xmm2\n __m128i *v11; // rax\n __m128i v12; // xmm1\n int v13; // eax\n __int64 v14; // rcx\n int v15; // edx\n int v16; // eax\n int *v17; // r15\n unsigned __int8 **v18; // r14\n unsigned __int8 **v19; // r13\n unsigned __int8 *v20; // rax\n __int64 v21; // rcx\n __int64 v22; // r8\n int i; // eax\n __int64 v24; // rdx\n __int64 v25; // rdx\n __int64 v26; // r9\n int v27; // eax\n __int64 v28; // rdx\n int v29; // ecx\n double v30; // xmm0_8\n unsigned __int8 **v31; // rbp\n int *v32; // rsi\n int *v33; // rcx\n int *v34; // rdi\n _BYTE *v35; // r10\n int v36; // r9d\n __int64 v37; // r8\n __int64 v38; // r11\n int j; // eax\n __int64 v40; // rdx\n __int64 v41; // rdx\n __int64 v42; // r13\n int v43; // eax\n __int64 v44; // rdx\n int v45; // r8d\n int v46; // r9d\n int *v47; // r11\n int v48; // r10d\n int v49; // eax\n int v50; // eax\n __int64 v51; // rax\n int v52; // r10d\n __int64 v53; // rcx\n __int64 v54; // r8\n int k; // eax\n __int64 v56; // rdx\n __int64 v57; // rdx\n __int64 v58; // r9\n int v59; // eax\n __int64 v60; // rdx\n int v61; // ecx\n _DWORD *v62; // r8\n int v63; // edx\n int v64; // eax\n unsigned int v65; // ebp\n _DWORD *v67; // [rsp+0h] [rbp-58h]\n int v68; // [rsp+Ch] [rbp-4Ch]\n __int64 v69; // [rsp+18h] [rbp-40h]\n\n v6 = 4LL * a4;\n v7 = malloc(v6);\n v8 = (int *)malloc(v6);\n if ( a4 > 0 )\n {\n memcpy(v7, a2, 4LL * (unsigned int)a4);\n if ( (unsigned int)(a4 - 1) <= 2 )\n {\n v13 = 0;\n }\n else\n {\n si128 = _mm_load_si128((const __m128i *)&xmmword_20C0);\n v10 = _mm_load_si128((const __m128i *)&xmmword_20D0);\n v11 = (__m128i *)v8;\n do\n {\n v12 = si128;\n ++v11;\n si128 = _mm_add_epi32(si128, v10);\n v11[-1] = v12;\n }\n while ( &v8[4 * ((unsigned int)a4 >> 2)] != (int *)v11 );\n if ( (a4 & 3) == 0 )\n goto LABEL_10;\n v13 = a4 & 0x7FFFFFFC;\n }\n v8[v13] = v13;\n v14 = v13;\n v15 = v13 + 1;\n if ( a4 > v13 + 1 )\n {\n v16 = v13 + 2;\n v8[v14 + 1] = v15;\n if ( a4 > v16 )\n v8[v14 + 2] = v16;\n }\n }\nLABEL_10:\n if ( a3 > 0 )\n {\n v17 = v8 + 1;\n v69 = a3;\n v18 = a1;\n v19 = a1;\n do\n {\n v20 = *v19;\n if ( **v19 == 42 && v20[1] == 42 && !v20[2] )\n {\n v21 = *(v17 - 1);\n v22 = v21;\n for ( i = v8[v21]; i != (_DWORD)v21; v22 = v24 )\n {\n v24 = i;\n *(v17 - 1) = i;\n LODWORD(v21) = i;\n i = v8[i];\n }\n v25 = *v17;\n v26 = v25;\n v27 = v8[v25];\n if ( (_DWORD)v25 != v27 )\n {\n do\n {\n v28 = v27;\n *v17 = v27;\n v29 = v27;\n v27 = v8[v27];\n v26 = v28;\n }\n while ( v27 != v29 );\n v21 = *(v17 - 1);\n v22 = v21;\n }\n v68 = v21;\n v67 = &v7[v22];\n v30 = pow((double)(int)v7[v22], (double)(int)v7[v26]);\n *v17 = v68;\n *v67 = (int)v30;\n }\n ++v19;\n ++v17;\n }\n while ( &a1[v69] != v19 );\n v31 = a1;\n v32 = v8;\n v33 = v8;\n v34 = &v8[v69];\n do\n {\n v35 = *v31;\n v36 = **v31;\n if ( v36 == 42 && !v35[1] || *v35 == 47 && v35[1] == 47 && !v35[2] )\n {\n v37 = *v33;\n v38 = v37;\n for ( j = v8[v37]; j != (_DWORD)v37; v38 = v40 )\n {\n v40 = j;\n *v33 = j;\n LODWORD(v37) = j;\n j = v8[j];\n }\n v41 = v33[1];\n v42 = v41;\n v43 = v8[v41];\n if ( (_DWORD)v41 != v43 )\n {\n do\n {\n v44 = v43;\n v33[1] = v43;\n v45 = v43;\n v43 = v8[v43];\n v42 = v44;\n }\n while ( v43 != v45 );\n v37 = *v33;\n v38 = v37;\n }\n v46 = v36 - 42;\n if ( !v46 )\n v46 = (unsigned __int8)v35[1];\n v47 = &v7[v38];\n v48 = v7[v42];\n v49 = *v47;\n if ( v46 )\n v50 = v49 / v48;\n else\n v50 = v48 * v49;\n *v47 = v50;\n v33[1] = v37;\n }\n ++v33;\n ++v31;\n }\n while ( v33 != v34 );\n do\n {\n v51 = (__int64)*v18;\n v52 = **v18;\n if ( v52 == 43 && !*(_BYTE *)(v51 + 1) || v52 == 45 && !*(_BYTE *)(v51 + 1) )\n {\n v53 = *v32;\n v54 = v53;\n for ( k = v8[v53]; k != (_DWORD)v53; v54 = v56 )\n {\n v56 = k;\n *v32 = k;\n LODWORD(v53) = k;\n k = v8[k];\n }\n v57 = v32[1];\n v58 = v57;\n v59 = v8[v57];\n if ( (_DWORD)v57 != v59 )\n {\n do\n {\n v60 = v59;\n v32[1] = v59;\n v61 = v59;\n v59 = v8[v59];\n v58 = v60;\n }\n while ( v59 != v61 );\n v53 = *v32;\n v54 = v53;\n }\n v62 = &v7[v54];\n v63 = v7[v58];\n v32[1] = v53;\n v64 = *v62 - v63;\n if ( v52 == 43 )\n v64 = *v62 + v63;\n *v62 = v64;\n }\n ++v32;\n ++v18;\n }\n while ( v34 != v32 );\n }\n v65 = *v7;\n free(v7);\n free(v8);\n return v65;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_13A0(unsigned char **a1, const void *a2, int a3, int a4) {\n unsigned int v6;\n uint32_t *v7;\n int *v8;\n __m128i si128;\n __m128i v10;\n __m128i *v11;\n __m128i v12;\n int v13;\n long long v14;\n int v15;\n int v16;\n int *v17;\n unsigned char **v18;\n unsigned char **v19;\n unsigned char *v20;\n long long v21;\n long long v22;\n int i;\n long long v24;\n long long v25;\n long long v26;\n int v27;\n long long v28;\n int v29;\n double v30;\n unsigned char **v31;\n int *v32;\n int *v33;\n int *v34;\n uint8_t *v35;\n int v36;\n long long v37;\n long long v38;\n int j;\n long long v40;\n long long v41;\n long long v42;\n int v43;\n long long v44;\n int v45;\n int v46;\n int *v47;\n int v48;\n int v49;\n int v50;\n long long v51;\n int v52;\n long long v53;\n long long v54;\n int k;\n long long v56;\n long long v57;\n long long v58;\n int v59;\n long long v60;\n int v61;\n uint32_t *v62;\n int v63;\n int v64;\n unsigned int v65;\n uint32_t *v67;\n int v68;\n long long v69;\n v6 = 4LL * a4;\n v7 = malloc(v6);\n v8 = (int *)malloc(v6);\n if (a4 > 0) {\n memcpy(v7, a2, 4LL * (unsigned int)a4);\n if ((unsigned int)(a4 - 1) <= 2) {\n v13 = 0;\n } else {\n si128 = _mm_load_si128((const __m128i *)&xmmword_20C0);\n v10 = _mm_load_si128((const __m128i *)&xmmword_20D0);\n v11 = (__m128i *)v8;\n do {\n v12 = si128;\n ++v11;\n si128 = _mm_add_epi32(si128, v10);\n v11[-1] = v12;\n } while (&v8[4 * ((unsigned int)a4 >> 2)] != (int *)v11);\n if ((a4 & 3) == 0) goto LABEL_10;\n v13 = a4 & 2147483644;\n }\n v8[v13] = v13;\n v14 = v13;\n v15 = v13 + 1;\n if (a4 > v13 + 1) {\n v16 = v13 + 2;\n v8[v14 + 1] = v15;\n if (a4 > v16) v8[v14 + 2] = v16;\n }\n }\nLABEL_10:\n if (a3 > 0) {\n v17 = v8 + 1;\n v69 = a3;\n v18 = a1;\n v19 = a1;\n do {\n v20 = *v19;\n if (**v19 == 42 && v20[1] == 42 && !v20[2]) {\n v21 = *(v17 - 1);\n v22 = v21;\n for (i = v8[v21]; i != (uint32_t)v21; v22 = v24) {\n v24 = i;\n *(v17 - 1) = i;\n LODWORD(v21) = i;\n i = v8[i];\n }\n v25 = *v17;\n v26 = v25;\n v27 = v8[v25];\n if ((uint32_t)v25 != v27) {\n do {\n v28 = v27;\n *v17 = v27;\n v29 = v27;\n v27 = v8[v27];\n v26 = v28;\n } while (v27 != v29);\n v21 = *(v17 - 1);\n v22 = v21;\n }\n v68 = v21;\n v67 = &v7[v22];\n v30 = pow((double)(int)v7[v22], (double)(int)v7[v26]);\n *v17 = v68;\n *v67 = (int)v30;\n }\n ++v19;\n ++v17;\n } while (&a1[v69] != v19);\n v31 = a1;\n v32 = v8;\n v33 = v8;\n v34 = &v8[v69];\n do {\n v35 = *v31;\n v36 = **v31;\n if (v36 == 42 && !v35[1] || *v35 == 47 && v35[1] == 47 && !v35[2]) {\n v37 = *v33;\n v38 = v37;\n for (j = v8[v37]; j != (uint32_t)v37; v38 = v40) {\n v40 = j;\n *v33 = j;\n LODWORD(v37) = j;\n j = v8[j];\n }\n v41 = v33[1];\n v42 = v41;\n v43 = v8[v41];\n if ((uint32_t)v41 != v43) {\n do {\n v44 = v43;\n v33[1] = v43;\n v45 = v43;\n v43 = v8[v43];\n v42 = v44;\n } while (v43 != v45);\n v37 = *v33;\n v38 = v37;\n }\n v46 = v36 - 42;\n if (!v46) v46 = (unsigned char)v35[1];\n v47 = &v7[v38];\n v48 = v7[v42];\n v49 = *v47;\n if (v46)\n v50 = v49 / v48;\n else\n v50 = v48 * v49;\n *v47 = v50;\n v33[1] = v37;\n }\n ++v33;\n ++v31;\n } while (v33 != v34);\n do {\n v51 = (long long)*v18;\n v52 = **v18;\n if (v52 == 43 && !*(uint8_t *)(v51 + 1) ||\n v52 == 45 && !*(uint8_t *)(v51 + 1)) {\n v53 = *v32;\n v54 = v53;\n for (k = v8[v53]; k != (uint32_t)v53; v54 = v56) {\n v56 = k;\n *v32 = k;\n LODWORD(v53) = k;\n k = v8[k];\n }\n v57 = v32[1];\n v58 = v57;\n v59 = v8[v57];\n if ((uint32_t)v57 != v59) {\n do {\n v60 = v59;\n v32[1] = v59;\n v61 = v59;\n v59 = v8[v59];\n v58 = v60;\n } while (v59 != v61);\n v53 = *v32;\n v54 = v53;\n }\n v62 = &v7[v54];\n v63 = v7[v58];\n v32[1] = v53;\n v64 = *v62 - v63;\n if (v52 == 43) v64 = *v62 + v63;\n *v62 = v64;\n }\n ++v32;\n ++v18;\n } while (v34 != v32);\n }\n v65 = *v7;\n free(v7);\n free(v8);\n return v65;\n}", + "ida_pseudo_norm": "long long func0(unsigned char **a1, const void *a2, int a3, int a4) {\n unsigned int v6;\n uint32_t *v7;\n int *v8;\n __m128i si128;\n __m128i v10;\n __m128i *v11;\n __m128i v12;\n int v13;\n long long v14;\n int v15;\n int v16;\n int *v17;\n unsigned char **v18;\n unsigned char **v19;\n unsigned char *v20;\n long long v21;\n long long v22;\n int i;\n long long v24;\n long long v25;\n long long v26;\n int v27;\n long long v28;\n int v29;\n double v30;\n unsigned char **v31;\n int *v32;\n int *v33;\n int *v34;\n uint8_t *v35;\n int v36;\n long long v37;\n long long v38;\n int j;\n long long v40;\n long long v41;\n long long v42;\n int v43;\n long long v44;\n int v45;\n int v46;\n int *v47;\n int v48;\n int v49;\n int v50;\n long long v51;\n int v52;\n long long v53;\n long long v54;\n int k;\n long long v56;\n long long v57;\n long long v58;\n int v59;\n long long v60;\n int v61;\n uint32_t *v62;\n int v63;\n int v64;\n unsigned int v65;\n uint32_t *v67;\n int v68;\n long long v69;\n v6 = 4LL * a4;\n v7 = malloc(v6);\n v8 = (int *)malloc(v6);\n if (a4 > 0) {\n memcpy(v7, a2, 4LL * (unsigned int)a4);\n if ((unsigned int)(a4 - 1) <= 2) {\n v13 = 0;\n } else {\n si128 = _mm_load_si128((const __m128i *)&xmmword_20C0);\n v10 = _mm_load_si128((const __m128i *)&xmmword_20D0);\n v11 = (__m128i *)v8;\n do {\n v12 = si128;\n ++v11;\n si128 = _mm_add_epi32(si128, v10);\n v11[-1] = v12;\n } while (&v8[4 * ((unsigned int)a4 >> 2)] != (int *)v11);\n if ((a4 & 3) == 0) goto LABEL_10;\n v13 = a4 & 2147483644;\n }\n v8[v13] = v13;\n v14 = v13;\n v15 = v13 + 1;\n if (a4 > v13 + 1) {\n v16 = v13 + 2;\n v8[v14 + 1] = v15;\n if (a4 > v16) v8[v14 + 2] = v16;\n }\n }\nLABEL_10:\n if (a3 > 0) {\n v17 = v8 + 1;\n v69 = a3;\n v18 = a1;\n v19 = a1;\n do {\n v20 = *v19;\n if (**v19 == 42 && v20[1] == 42 && !v20[2]) {\n v21 = *(v17 - 1);\n v22 = v21;\n for (i = v8[v21]; i != (uint32_t)v21; v22 = v24) {\n v24 = i;\n *(v17 - 1) = i;\n LODWORD(v21) = i;\n i = v8[i];\n }\n v25 = *v17;\n v26 = v25;\n v27 = v8[v25];\n if ((uint32_t)v25 != v27) {\n do {\n v28 = v27;\n *v17 = v27;\n v29 = v27;\n v27 = v8[v27];\n v26 = v28;\n } while (v27 != v29);\n v21 = *(v17 - 1);\n v22 = v21;\n }\n v68 = v21;\n v67 = &v7[v22];\n v30 = pow((double)(int)v7[v22], (double)(int)v7[v26]);\n *v17 = v68;\n *v67 = (int)v30;\n }\n ++v19;\n ++v17;\n } while (&a1[v69] != v19);\n v31 = a1;\n v32 = v8;\n v33 = v8;\n v34 = &v8[v69];\n do {\n v35 = *v31;\n v36 = **v31;\n if (v36 == 42 && !v35[1] || *v35 == 47 && v35[1] == 47 && !v35[2]) {\n v37 = *v33;\n v38 = v37;\n for (j = v8[v37]; j != (uint32_t)v37; v38 = v40) {\n v40 = j;\n *v33 = j;\n LODWORD(v37) = j;\n j = v8[j];\n }\n v41 = v33[1];\n v42 = v41;\n v43 = v8[v41];\n if ((uint32_t)v41 != v43) {\n do {\n v44 = v43;\n v33[1] = v43;\n v45 = v43;\n v43 = v8[v43];\n v42 = v44;\n } while (v43 != v45);\n v37 = *v33;\n v38 = v37;\n }\n v46 = v36 - 42;\n if (!v46) v46 = (unsigned char)v35[1];\n v47 = &v7[v38];\n v48 = v7[v42];\n v49 = *v47;\n if (v46)\n v50 = v49 / v48;\n else\n v50 = v48 * v49;\n *v47 = v50;\n v33[1] = v37;\n }\n ++v33;\n ++v31;\n } while (v33 != v34);\n do {\n v51 = (long long)*v18;\n v52 = **v18;\n if (v52 == 43 && !*(uint8_t *)(v51 + 1) ||\n v52 == 45 && !*(uint8_t *)(v51 + 1)) {\n v53 = *v32;\n v54 = v53;\n for (k = v8[v53]; k != (uint32_t)v53; v54 = v56) {\n v56 = k;\n *v32 = k;\n LODWORD(v53) = k;\n k = v8[k];\n }\n v57 = v32[1];\n v58 = v57;\n v59 = v8[v57];\n if ((uint32_t)v57 != v59) {\n do {\n v60 = v59;\n v32[1] = v59;\n v61 = v59;\n v59 = v8[v59];\n v58 = v60;\n } while (v59 != v61);\n v53 = *v32;\n v54 = v53;\n }\n v62 = &v7[v54];\n v63 = v7[v58];\n v32[1] = v53;\n v64 = *v62 - v63;\n if (v52 == 43) v64 = *v62 + v63;\n *v62 = v64;\n }\n ++v32;\n ++v18;\n } while (v34 != v32);\n }\n v65 = *v7;\n free(v7);\n free(v8);\n return v65;\n}" + }, + { + "index": "HumanEval-C-161", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char* func0(char* s) {\n int nletter = 0;\n int length = strlen(s);\n for (int i = 0; i < length; i++) {\n if (isalpha((unsigned char)s[i])) {\n if (isupper((unsigned char)s[i]))\n s[i] = tolower((unsigned char)s[i]);\n else if (islower((unsigned char)s[i]))\n s[i] = toupper((unsigned char)s[i]);\n } else {\n nletter += 1;\n }\n }\n if (nletter == length) {\n for (int i = 0; i < length / 2; i++) {\n char temp = s[i];\n s[i] = s[length - i - 1];\n s[length - i - 1] = temp;\n }\n }\n return s;\n}", + "test": "#include \n#include \n\nint main(){\n char test1[] = \"AsDf\";\n assert(strcmp(func0(test1), \"aSdF\") == 0);\n\n char test2[] = \"1234\";\n assert(strcmp(func0(test2), \"4321\") == 0);\n\n char test3[] = \"ab\";\n assert(strcmp(func0(test3), \"AB\") == 0);\n\n char test4[] = \"#a@C\";\n assert(strcmp(func0(test4), \"#A@c\") == 0);\n\n char test5[] = \"#AsdfW^45\";\n assert(strcmp(func0(test5), \"#aSDFw^45\") == 0);\n\n char test6[] = \"#6@2\";\n assert(strcmp(func0(test6), \"2@6#\") == 0);\n\n char test7[] = \"#$a^D\";\n assert(strcmp(func0(test7), \"#$A^d\") == 0);\n\n char test8[] = \"#ccc\";\n assert(strcmp(func0(test8), \"#CCC\") == 0);\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov [rbp+var_10], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_C], 0\njmp loc_1335\nloc_123B:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_C]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovzx edx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 400h\ntest eax, eax\njz loc_132D\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_C]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovzx edx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 100h\ntest eax, eax\njz short loc_12CE\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovzx eax, al\nmov edi, eax; c\ncall _tolower\nmov ecx, eax\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmov edx, ecx\nmov [rax], dl\njmp short loc_1331\nloc_12CE:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_C]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovzx edx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 200h\ntest eax, eax\njz short loc_1331\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovzx eax, al\nmov edi, eax; c\ncall _toupper\nmov ecx, eax\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmov edx, ecx\nmov [rax], dl\njmp short loc_1331\nloc_132D:\nadd [rbp+var_10], 1\nloc_1331:\nadd [rbp+var_C], 1\nloc_1335:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_4]\njl loc_123B\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_4]\njnz short loc_13B8\nmov [rbp+var_8], 0\njmp short loc_13A7\nloc_1352:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_11], al\nmov eax, [rbp+var_4]\nsub eax, [rbp+var_8]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rdx\nmov edx, [rbp+var_8]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx eax, byte ptr [rax]\nmov [rdx], al\nmov eax, [rbp+var_4]\nsub eax, [rbp+var_8]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nadd rdx, rax\nmovzx eax, [rbp+var_11]\nmov [rdx], al\nadd [rbp+var_8], 1\nloc_13A7:\nmov eax, [rbp+var_4]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\ncmp [rbp+var_8], eax\njl short loc_1352\nloc_13B8:\nmov rax, [rbp+s]\nleave\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n char v2; // [rsp+1Fh] [rbp-11h]\n int v3; // [rsp+20h] [rbp-10h]\n int i; // [rsp+24h] [rbp-Ch]\n int j; // [rsp+28h] [rbp-8h]\n int v6; // [rsp+2Ch] [rbp-4h]\n\n v3 = 0;\n v6 = strlen(a1);\n for ( i = 0; i < v6; ++i )\n {\n if ( ((*__ctype_b_loc())[(unsigned __int8)a1[i]] & 0x400) != 0 )\n {\n if ( ((*__ctype_b_loc())[(unsigned __int8)a1[i]] & 0x100) != 0 )\n {\n a1[i] = tolower((unsigned __int8)a1[i]);\n }\n else if ( ((*__ctype_b_loc())[(unsigned __int8)a1[i]] & 0x200) != 0 )\n {\n a1[i] = toupper((unsigned __int8)a1[i]);\n }\n }\n else\n {\n ++v3;\n }\n }\n if ( v3 == v6 )\n {\n for ( j = 0; j < v6 / 2; ++j )\n {\n v2 = a1[j];\n a1[j] = a1[v6 - j - 1];\n a1[v6 - j - 1] = v2;\n }\n }\n return a1;\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov [rbp+var_10], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_C], 0\njmp loc_1335\nloc_123B:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_C]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovzx edx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 400h\ntest eax, eax\njz loc_132D\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_C]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovzx edx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 100h\ntest eax, eax\njz short loc_12CE\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovzx eax, al\nmov edi, eax; c\ncall _tolower\nmov ecx, eax\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmov edx, ecx\nmov [rax], dl\njmp short loc_1331\nloc_12CE:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_C]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovzx edx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 200h\ntest eax, eax\njz short loc_1331\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovzx eax, al\nmov edi, eax; c\ncall _toupper\nmov ecx, eax\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmov edx, ecx\nmov [rax], dl\njmp short loc_1331\nloc_132D:\nadd [rbp+var_10], 1\nloc_1331:\nadd [rbp+var_C], 1\nloc_1335:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_4]\njl loc_123B\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_4]\njnz short loc_13B8\nmov [rbp+var_8], 0\njmp short loc_13A7\nloc_1352:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_11], al\nmov eax, [rbp+var_4]\nsub eax, [rbp+var_8]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rdx\nmov edx, [rbp+var_8]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx eax, byte ptr [rax]\nmov [rdx], al\nmov eax, [rbp+var_4]\nsub eax, [rbp+var_8]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nadd rdx, rax\nmovzx eax, [rbp+var_11]\nmov [rdx], al\nadd [rbp+var_8], 1\nloc_13A7:\nmov eax, [rbp+var_4]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\ncmp [rbp+var_8], eax\njl short loc_1352\nloc_13B8:\nmov rax, [rbp+s]\nleave\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1209(const char *a1)\n{\n char v2; // [rsp+1Fh] [rbp-11h]\n int v3; // [rsp+20h] [rbp-10h]\n int i; // [rsp+24h] [rbp-Ch]\n int j; // [rsp+28h] [rbp-8h]\n int v6; // [rsp+2Ch] [rbp-4h]\n\n v3 = 0;\n v6 = strlen(a1);\n for ( i = 0; i < v6; ++i )\n {\n if ( ((*__ctype_b_loc())[(unsigned __int8)a1[i]] & 0x400) != 0 )\n {\n if ( ((*__ctype_b_loc())[(unsigned __int8)a1[i]] & 0x100) != 0 )\n {\n a1[i] = tolower((unsigned __int8)a1[i]);\n }\n else if ( ((*__ctype_b_loc())[(unsigned __int8)a1[i]] & 0x200) != 0 )\n {\n a1[i] = toupper((unsigned __int8)a1[i]);\n }\n }\n else\n {\n ++v3;\n }\n }\n if ( v3 == v6 )\n {\n for ( j = 0; j < v6 / 2; ++j )\n {\n v2 = a1[j];\n a1[j] = a1[v6 - j - 1];\n a1[v6 - j - 1] = v2;\n }\n }\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1209(const char *a1) {\n char v2;\n int v3;\n int i;\n int j;\n int v6;\n v3 = 0;\n v6 = strlen(a1);\n for (i = 0; i < v6; ++i) {\n if (((*__ctype_b_loc())[(unsigned char)a1[i]] & 1024) != 0) {\n if (((*__ctype_b_loc())[(unsigned char)a1[i]] & 256) != 0) {\n a1[i] = tolower((unsigned char)a1[i]);\n } else if (((*__ctype_b_loc())[(unsigned char)a1[i]] & 512) != 0) {\n a1[i] = toupper((unsigned char)a1[i]);\n }\n } else {\n ++v3;\n }\n }\n if (v3 == v6) {\n for (j = 0; j < v6 / 2; ++j) {\n v2 = a1[j];\n a1[j] = a1[v6 - j - 1];\n a1[v6 - j - 1] = v2;\n }\n }\n return a1;\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n char v2;\n int v3;\n int i;\n int j;\n int v6;\n v3 = 0;\n v6 = strlen(a1);\n for (i = 0; i < v6; ++i) {\n if (((*__ctype_b_loc())[(unsigned char)a1[i]] & 1024) != 0) {\n if (((*__ctype_b_loc())[(unsigned char)a1[i]] & 256) != 0) {\n a1[i] = tolower((unsigned char)a1[i]);\n } else if (((*__ctype_b_loc())[(unsigned char)a1[i]] & 512) != 0) {\n a1[i] = toupper((unsigned char)a1[i]);\n }\n } else {\n ++v3;\n }\n }\n if (v3 == v6) {\n for (j = 0; j < v6 / 2; ++j) {\n v2 = a1[j];\n a1[j] = a1[v6 - j - 1];\n a1[v6 - j - 1] = v2;\n }\n }\n return a1;\n}" + }, + { + "index": "HumanEval-C-161", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char* func0(char* s) {\n int nletter = 0;\n int length = strlen(s);\n for (int i = 0; i < length; i++) {\n if (isalpha((unsigned char)s[i])) {\n if (isupper((unsigned char)s[i]))\n s[i] = tolower((unsigned char)s[i]);\n else if (islower((unsigned char)s[i]))\n s[i] = toupper((unsigned char)s[i]);\n } else {\n nletter += 1;\n }\n }\n if (nletter == length) {\n for (int i = 0; i < length / 2; i++) {\n char temp = s[i];\n s[i] = s[length - i - 1];\n s[length - i - 1] = temp;\n }\n }\n return s;\n}", + "test": "#include \n#include \n\nint main(){\n char test1[] = \"AsDf\";\n assert(strcmp(func0(test1), \"aSdF\") == 0);\n\n char test2[] = \"1234\";\n assert(strcmp(func0(test2), \"4321\") == 0);\n\n char test3[] = \"ab\";\n assert(strcmp(func0(test3), \"AB\") == 0);\n\n char test4[] = \"#a@C\";\n assert(strcmp(func0(test4), \"#A@c\") == 0);\n\n char test5[] = \"#AsdfW^45\";\n assert(strcmp(func0(test5), \"#aSDFw^45\") == 0);\n\n char test6[] = \"#6@2\";\n assert(strcmp(func0(test6), \"2@6#\") == 0);\n\n char test7[] = \"#$a^D\";\n assert(strcmp(func0(test7), \"#$A^d\") == 0);\n\n char test8[] = \"#ccc\";\n assert(strcmp(func0(test8), \"#CCC\") == 0);\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov r12, rdi\ncall _strlen\nmov [rsp+48h+var_40], rax\ntest eax, eax\njle short loc_129F\nmov r14, rax\ncall ___ctype_b_loc\nmov r13, rax\nmov rbx, r12\nlea eax, [r14-1]\nlea r15, [r12+rax+1]\nmov r14d, 0\njmp short loc_1270\nloc_124B:\ntest ah, 2\njz short loc_1267\ncall ___ctype_toupper_loc\nmov rax, [rax]\nmov eax, [rax+rbp*4]\nmov rsi, [rsp+48h+var_48]\nmov [rsi], al\njmp short loc_1267\nloc_1263:\nadd r14d, 1\nloc_1267:\nadd rbx, 1\ncmp rbx, r15\njz short loc_1298\nloc_1270:\nmov [rsp+48h+var_48], rbx\nmovzx ebp, byte ptr [rbx]\nmov rax, [r13+0]\nmovzx eax, word ptr [rax+rbp*2]\ntest ah, 4\njz short loc_1263\ntest ah, 1\njz short loc_124B\ncall ___ctype_tolower_loc\nmov rax, [rax]\nmov eax, [rax+rbp*4]\nmov [rbx], al\njmp short loc_1267\nloc_1298:\ncmp dword ptr [rsp+48h+var_40], r14d\njz short loc_12B1\nloc_129F:\nmov rax, r12\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_12B1:\nmov rax, [rsp+48h+var_40]\nmov edi, eax\nshr edi, 1Fh\nadd edi, eax\nsar edi, 1\ncmp eax, 1\njle short loc_129F\ncdqe\nlea rdx, [r12+rax-1]\nmov eax, 0\nloc_12D0:\nmovzx ecx, byte ptr [r12+rax]\nmovzx esi, byte ptr [rdx]\nmov [r12+rax], sil\nmov [rdx], cl\nadd rax, 1\nsub rdx, 1\ncmp edi, eax\njg short loc_12D0\njmp short loc_129F", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n int v1; // eax\n int v2; // r14d\n const unsigned __int16 **v3; // r13\n char *v4; // rbx\n __int64 v5; // r15\n int v6; // r14d\n __int64 v7; // rbp\n unsigned __int16 v8; // ax\n char *v10; // rdx\n __int64 v11; // rax\n char v12; // cl\n int v13; // [rsp+8h] [rbp-40h]\n\n v1 = strlen(a1);\n v13 = v1;\n if ( v1 > 0 )\n {\n v2 = v1;\n v3 = __ctype_b_loc();\n v4 = (char *)a1;\n v5 = (__int64)&a1[v2 - 1 + 1];\n v6 = 0;\n do\n {\n v7 = (unsigned __int8)*v4;\n v8 = (*v3)[v7];\n if ( (v8 & 0x400) != 0 )\n {\n if ( (v8 & 0x100) != 0 )\n {\n *v4 = (*__ctype_tolower_loc())[v7];\n }\n else if ( (v8 & 0x200) != 0 )\n {\n *v4 = (*__ctype_toupper_loc())[v7];\n }\n }\n else\n {\n ++v6;\n }\n ++v4;\n }\n while ( v4 != (char *)v5 );\n if ( v13 == v6 && v13 > 1 )\n {\n v10 = (char *)&a1[v13 - 1];\n v11 = 0LL;\n do\n {\n v12 = a1[v11];\n a1[v11] = *v10;\n *v10 = v12;\n ++v11;\n --v10;\n }\n while ( v13 / 2 > (int)v11 );\n }\n }\n return a1;\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov r12, rdi\ncall _strlen\nmov [rsp+48h+var_40], rax\ntest eax, eax\njle short loc_129F\nmov r14, rax\ncall ___ctype_b_loc\nmov r13, rax\nmov rbx, r12\nlea eax, [r14-1]\nlea r15, [r12+rax+1]\nmov r14d, 0\njmp short loc_1270\nloc_124B:\ntest ah, 2\njz short loc_1267\ncall ___ctype_toupper_loc\nmov rax, [rax]\nmov eax, [rax+rbp*4]\nmov rsi, [rsp+48h+var_48]\nmov [rsi], al\njmp short loc_1267\nloc_1263:\nadd r14d, 1\nloc_1267:\nadd rbx, 1\ncmp rbx, r15\njz short loc_1298\nloc_1270:\nmov [rsp+48h+var_48], rbx\nmovzx ebp, byte ptr [rbx]\nmov rax, [r13+0]\nmovzx eax, word ptr [rax+rbp*2]\ntest ah, 4\njz short loc_1263\ntest ah, 1\njz short loc_124B\ncall ___ctype_tolower_loc\nmov rax, [rax]\nmov eax, [rax+rbp*4]\nmov [rbx], al\njmp short loc_1267\nloc_1298:\ncmp dword ptr [rsp+48h+var_40], r14d\njz short loc_12B1\nloc_129F:\nmov rax, r12\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_12B1:\nmov rax, [rsp+48h+var_40]\nmov edi, eax\nshr edi, 1Fh\nadd edi, eax\nsar edi, 1\ncmp eax, 1\njle short loc_129F\ncdqe\nlea rdx, [r12+rax-1]\nmov eax, 0\nloc_12D0:\nmovzx ecx, byte ptr [r12+rax]\nmovzx esi, byte ptr [rdx]\nmov [r12+rax], sil\nmov [rdx], cl\nadd rax, 1\nsub rdx, 1\ncmp edi, eax\njg short loc_12D0\njmp short loc_129F", + "ida_strip_pseudo": "const char *__fastcall sub_1209(const char *a1)\n{\n int v1; // eax\n int v2; // r14d\n const unsigned __int16 **v3; // r13\n char *v4; // rbx\n __int64 v5; // r15\n int v6; // r14d\n __int64 v7; // rbp\n unsigned __int16 v8; // ax\n char *v10; // rdx\n __int64 v11; // rax\n char v12; // cl\n int v13; // [rsp+8h] [rbp-40h]\n\n v1 = strlen(a1);\n v13 = v1;\n if ( v1 > 0 )\n {\n v2 = v1;\n v3 = __ctype_b_loc();\n v4 = (char *)a1;\n v5 = (__int64)&a1[v2 - 1 + 1];\n v6 = 0;\n do\n {\n v7 = (unsigned __int8)*v4;\n v8 = (*v3)[v7];\n if ( (v8 & 0x400) != 0 )\n {\n if ( (v8 & 0x100) != 0 )\n {\n *v4 = (*__ctype_tolower_loc())[v7];\n }\n else if ( (v8 & 0x200) != 0 )\n {\n *v4 = (*__ctype_toupper_loc())[v7];\n }\n }\n else\n {\n ++v6;\n }\n ++v4;\n }\n while ( v4 != (char *)v5 );\n if ( v13 == v6 && v13 > 1 )\n {\n v10 = (char *)&a1[v13 - 1];\n v11 = 0LL;\n do\n {\n v12 = a1[v11];\n a1[v11] = *v10;\n *v10 = v12;\n ++v11;\n --v10;\n }\n while ( v13 / 2 > (int)v11 );\n }\n }\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1209(const char *a1) {\n int v1;\n int v2;\n const unsigned short **v3;\n char *v4;\n long long v5;\n int v6;\n long long v7;\n unsigned short v8;\n char *v10;\n long long v11;\n char v12;\n int v13;\n v1 = strlen(a1);\n v13 = v1;\n if (v1 > 0) {\n v2 = v1;\n v3 = __ctype_b_loc();\n v4 = (char *)a1;\n v5 = (long long)&a1[v2 - 1 + 1];\n v6 = 0;\n do {\n v7 = (unsigned char)*v4;\n v8 = (*v3)[v7];\n if ((v8 & 1024) != 0) {\n if ((v8 & 256) != 0) {\n *v4 = (*__ctype_tolower_loc())[v7];\n } else if ((v8 & 512) != 0) {\n *v4 = (*__ctype_toupper_loc())[v7];\n }\n } else {\n ++v6;\n }\n ++v4;\n } while (v4 != (char *)v5);\n if (v13 == v6 && v13 > 1) {\n v10 = (char *)&a1[v13 - 1];\n v11 = 0LL;\n do {\n v12 = a1[v11];\n a1[v11] = *v10;\n *v10 = v12;\n ++v11;\n --v10;\n } while (v13 / 2 > (int)v11);\n }\n }\n return a1;\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n int v1;\n int v2;\n const unsigned short **v3;\n char *v4;\n long long v5;\n int v6;\n long long v7;\n unsigned short v8;\n char *v10;\n long long v11;\n char v12;\n int v13;\n v1 = strlen(a1);\n v13 = v1;\n if (v1 > 0) {\n v2 = v1;\n v3 = __ctype_b_loc();\n v4 = (char *)a1;\n v5 = (long long)&a1[v2 - 1 + 1];\n v6 = 0;\n do {\n v7 = (unsigned char)*v4;\n v8 = (*v3)[v7];\n if ((v8 & 1024) != 0) {\n if ((v8 & 256) != 0) {\n *v4 = (*__ctype_tolower_loc())[v7];\n } else if ((v8 & 512) != 0) {\n *v4 = (*__ctype_toupper_loc())[v7];\n }\n } else {\n ++v6;\n }\n ++v4;\n } while (v4 != (char *)v5);\n if (v13 == v6 && v13 > 1) {\n v10 = (char *)&a1[v13 - 1];\n v11 = 0LL;\n do {\n v12 = a1[v11];\n a1[v11] = *v10;\n *v10 = v12;\n ++v11;\n --v10;\n } while (v13 / 2 > (int)v11);\n }\n }\n return a1;\n}" + }, + { + "index": "HumanEval-C-161", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char* func0(char* s) {\n int nletter = 0;\n int length = strlen(s);\n for (int i = 0; i < length; i++) {\n if (isalpha((unsigned char)s[i])) {\n if (isupper((unsigned char)s[i]))\n s[i] = tolower((unsigned char)s[i]);\n else if (islower((unsigned char)s[i]))\n s[i] = toupper((unsigned char)s[i]);\n } else {\n nletter += 1;\n }\n }\n if (nletter == length) {\n for (int i = 0; i < length / 2; i++) {\n char temp = s[i];\n s[i] = s[length - i - 1];\n s[length - i - 1] = temp;\n }\n }\n return s;\n}", + "test": "#include \n#include \n\nint main(){\n char test1[] = \"AsDf\";\n assert(strcmp(func0(test1), \"aSdF\") == 0);\n\n char test2[] = \"1234\";\n assert(strcmp(func0(test2), \"4321\") == 0);\n\n char test3[] = \"ab\";\n assert(strcmp(func0(test3), \"AB\") == 0);\n\n char test4[] = \"#a@C\";\n assert(strcmp(func0(test4), \"#A@c\") == 0);\n\n char test5[] = \"#AsdfW^45\";\n assert(strcmp(func0(test5), \"#aSDFw^45\") == 0);\n\n char test6[] = \"#6@2\";\n assert(strcmp(func0(test6), \"2@6#\") == 0);\n\n char test7[] = \"#$a^D\";\n assert(strcmp(func0(test7), \"#$A^d\") == 0);\n\n char test8[] = \"#ccc\";\n assert(strcmp(func0(test8), \"#CCC\") == 0);\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 18h\ncall _strlen\nmov [rsp+48h+var_40], rax\ntest eax, eax\njle short loc_153E\nmov r15, rax\nmov rbx, r12\ncall ___ctype_b_loc\nmov r14, rax\nlea eax, [r15-1]\nxor r15d, r15d\nlea r13, [r12+rax+1]\njmp short loc_151B\nloc_1500:\ntest ah, 1\njz short loc_1550\ncall ___ctype_tolower_loc\nmov rax, [rax]\nmov eax, [rax+rbp*4]\nmov [rbx], al\nloc_1512:\nadd rbx, 1\ncmp rbx, r13\njz short loc_1537\nloc_151B:\nmovzx ebp, byte ptr [rbx]\nmov rax, [r14]\nmovzx eax, word ptr [rax+rbp*2]\ntest ah, 4\njnz short loc_1500\nadd rbx, 1\nadd r15d, 1\ncmp rbx, r13\njnz short loc_151B\nloc_1537:\ncmp dword ptr [rsp+48h+var_40], r15d\njz short loc_1568\nloc_153E:\nadd rsp, 18h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1550:\ntest ah, 2\njz short loc_1512\ncall ___ctype_toupper_loc\nmov rax, [rax]\nmov eax, [rax+rbp*4]\nmov [rbx], al\njmp short loc_1512\nloc_1568:\nmov rax, [rsp+48h+var_40]\nmov edi, eax\nsar edi, 1\ncmp eax, 1\njz short loc_153E\nmovsxd r13, eax\nxor eax, eax\nlea rdx, [r12+r13-1]\nloc_1580:\nmovzx esi, byte ptr [rdx]\nmovzx ecx, byte ptr [r12+rax]\nsub rdx, 1\nmov [r12+rax], sil\nadd rax, 1\nmov [rdx+1], cl\ncmp edi, eax\njg short loc_1580\njmp short loc_153E", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n int v1; // eax\n int v2; // r15d\n char *v3; // rbx\n const unsigned __int16 **v4; // r14\n __int64 v5; // rax\n int v6; // r15d\n __int64 v7; // r13\n __int64 v8; // rbp\n unsigned __int16 v9; // ax\n __int64 v11; // rax\n const char *v12; // rdx\n char v13; // si\n char v14; // cl\n int v15; // [rsp+8h] [rbp-40h]\n\n v1 = strlen(a1);\n v15 = v1;\n if ( v1 > 0 )\n {\n v2 = v1;\n v3 = (char *)a1;\n v4 = __ctype_b_loc();\n v5 = (unsigned int)(v2 - 1);\n v6 = 0;\n v7 = (__int64)&a1[v5 + 1];\n do\n {\n while ( 1 )\n {\n v8 = (unsigned __int8)*v3;\n v9 = (*v4)[v8];\n if ( (v9 & 0x400) != 0 )\n break;\n ++v3;\n ++v6;\n if ( v3 == (char *)v7 )\n goto LABEL_8;\n }\n if ( (v9 & 0x100) != 0 )\n {\n *v3 = (*__ctype_tolower_loc())[v8];\n }\n else if ( (v9 & 0x200) != 0 )\n {\n *v3 = (*__ctype_toupper_loc())[v8];\n }\n ++v3;\n }\n while ( v3 != (char *)v7 );\nLABEL_8:\n if ( v15 == v6 && v15 != 1 )\n {\n v11 = 0LL;\n v12 = &a1[v15 - 1];\n do\n {\n v13 = *v12;\n v14 = a1[v11];\n --v12;\n a1[v11++] = v13;\n *((_BYTE *)v12 + 1) = v14;\n }\n while ( v15 >> 1 > (int)v11 );\n }\n }\n return a1;\n}", + "ida_strip_asm": "sub_14C0:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 18h\ncall _strlen\nmov [rsp+48h+var_40], rax\ntest eax, eax\njle short loc_153E\nmov r15, rax\nmov rbx, r12\ncall ___ctype_b_loc\nmov r14, rax\nlea eax, [r15-1]\nxor r15d, r15d\nlea r13, [r12+rax+1]\njmp short loc_151B\nloc_1500:\ntest ah, 1\njz short loc_1550\ncall ___ctype_tolower_loc\nmov rax, [rax]\nmov eax, [rax+rbp*4]\nmov [rbx], al\nloc_1512:\nadd rbx, 1\ncmp rbx, r13\njz short loc_1537\nloc_151B:\nmovzx ebp, byte ptr [rbx]\nmov rax, [r14]\nmovzx eax, word ptr [rax+rbp*2]\ntest ah, 4\njnz short loc_1500\nadd rbx, 1\nadd r15d, 1\ncmp rbx, r13\njnz short loc_151B\nloc_1537:\ncmp dword ptr [rsp+48h+var_40], r15d\njz short loc_1568\nloc_153E:\nadd rsp, 18h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1550:\ntest ah, 2\njz short loc_1512\ncall ___ctype_toupper_loc\nmov rax, [rax]\nmov eax, [rax+rbp*4]\nmov [rbx], al\njmp short loc_1512\nloc_1568:\nmov rax, [rsp+48h+var_40]\nmov edi, eax\nsar edi, 1\ncmp eax, 1\njz short loc_153E\nmovsxd r13, eax\nxor eax, eax\nlea rdx, [r12+r13-1]\nloc_1580:\nmovzx esi, byte ptr [rdx]\nmovzx ecx, byte ptr [r12+rax]\nsub rdx, 1\nmov [r12+rax], sil\nadd rax, 1\nmov [rdx+1], cl\ncmp edi, eax\njg short loc_1580\njmp short loc_153E", + "ida_strip_pseudo": "const char *__fastcall sub_14C0(const char *a1)\n{\n int v1; // eax\n int v2; // r15d\n char *v3; // rbx\n const unsigned __int16 **v4; // r14\n __int64 v5; // rax\n int v6; // r15d\n __int64 v7; // r13\n __int64 v8; // rbp\n unsigned __int16 v9; // ax\n __int64 v11; // rax\n const char *v12; // rdx\n char v13; // si\n char v14; // cl\n int v15; // [rsp+8h] [rbp-40h]\n\n v1 = strlen(a1);\n v15 = v1;\n if ( v1 > 0 )\n {\n v2 = v1;\n v3 = (char *)a1;\n v4 = __ctype_b_loc();\n v5 = (unsigned int)(v2 - 1);\n v6 = 0;\n v7 = (__int64)&a1[v5 + 1];\n do\n {\n while ( 1 )\n {\n v8 = (unsigned __int8)*v3;\n v9 = (*v4)[v8];\n if ( (v9 & 0x400) != 0 )\n break;\n ++v3;\n ++v6;\n if ( v3 == (char *)v7 )\n goto LABEL_8;\n }\n if ( (v9 & 0x100) != 0 )\n {\n *v3 = (*__ctype_tolower_loc())[v8];\n }\n else if ( (v9 & 0x200) != 0 )\n {\n *v3 = (*__ctype_toupper_loc())[v8];\n }\n ++v3;\n }\n while ( v3 != (char *)v7 );\nLABEL_8:\n if ( v15 == v6 && v15 != 1 )\n {\n v11 = 0LL;\n v12 = &a1[v15 - 1];\n do\n {\n v13 = *v12;\n v14 = a1[v11];\n --v12;\n a1[v11++] = v13;\n *((_BYTE *)v12 + 1) = v14;\n }\n while ( v15 >> 1 > (int)v11 );\n }\n }\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_14C0(const char *a1) {\n int v1;\n int v2;\n char *v3;\n const unsigned short **v4;\n long long v5;\n int v6;\n long long v7;\n long long v8;\n unsigned short v9;\n long long v11;\n const char *v12;\n char v13;\n char v14;\n int v15;\n v1 = strlen(a1);\n v15 = v1;\n if (v1 > 0) {\n v2 = v1;\n v3 = (char *)a1;\n v4 = __ctype_b_loc();\n v5 = (unsigned int)(v2 - 1);\n v6 = 0;\n v7 = (long long)&a1[v5 + 1];\n do {\n while (1) {\n v8 = (unsigned char)*v3;\n v9 = (*v4)[v8];\n if ((v9 & 1024) != 0) break;\n ++v3;\n ++v6;\n if (v3 == (char *)v7) goto LABEL_8;\n }\n if ((v9 & 256) != 0) {\n *v3 = (*__ctype_tolower_loc())[v8];\n } else if ((v9 & 512) != 0) {\n *v3 = (*__ctype_toupper_loc())[v8];\n }\n ++v3;\n } while (v3 != (char *)v7);\n LABEL_8:\n if (v15 == v6 && v15 != 1) {\n v11 = 0LL;\n v12 = &a1[v15 - 1];\n do {\n v13 = *v12;\n v14 = a1[v11];\n --v12;\n a1[v11++] = v13;\n *((uint8_t *)v12 + 1) = v14;\n } while (v15 >> 1 > (int)v11);\n }\n }\n return a1;\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n int v1;\n int v2;\n char *v3;\n const unsigned short **v4;\n long long v5;\n int v6;\n long long v7;\n long long v8;\n unsigned short v9;\n long long v11;\n const char *v12;\n char v13;\n char v14;\n int v15;\n v1 = strlen(a1);\n v15 = v1;\n if (v1 > 0) {\n v2 = v1;\n v3 = (char *)a1;\n v4 = __ctype_b_loc();\n v5 = (unsigned int)(v2 - 1);\n v6 = 0;\n v7 = (long long)&a1[v5 + 1];\n do {\n while (1) {\n v8 = (unsigned char)*v3;\n v9 = (*v4)[v8];\n if ((v9 & 1024) != 0) break;\n ++v3;\n ++v6;\n if (v3 == (char *)v7) goto LABEL_8;\n }\n if ((v9 & 256) != 0) {\n *v3 = (*__ctype_tolower_loc())[v8];\n } else if ((v9 & 512) != 0) {\n *v3 = (*__ctype_toupper_loc())[v8];\n }\n ++v3;\n } while (v3 != (char *)v7);\n LABEL_8:\n if (v15 == v6 && v15 != 1) {\n v11 = 0LL;\n v12 = &a1[v15 - 1];\n do {\n v13 = *v12;\n v14 = a1[v11];\n --v12;\n a1[v11++] = v13;\n *((uint8_t *)v12 + 1) = v14;\n } while (v15 >> 1 > (int)v11);\n }\n }\n return a1;\n}" + }, + { + "index": "HumanEval-C-161", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char* func0(char* s) {\n int nletter = 0;\n int length = strlen(s);\n for (int i = 0; i < length; i++) {\n if (isalpha((unsigned char)s[i])) {\n if (isupper((unsigned char)s[i]))\n s[i] = tolower((unsigned char)s[i]);\n else if (islower((unsigned char)s[i]))\n s[i] = toupper((unsigned char)s[i]);\n } else {\n nletter += 1;\n }\n }\n if (nletter == length) {\n for (int i = 0; i < length / 2; i++) {\n char temp = s[i];\n s[i] = s[length - i - 1];\n s[length - i - 1] = temp;\n }\n }\n return s;\n}", + "test": "#include \n#include \n\nint main(){\n char test1[] = \"AsDf\";\n assert(strcmp(func0(test1), \"aSdF\") == 0);\n\n char test2[] = \"1234\";\n assert(strcmp(func0(test2), \"4321\") == 0);\n\n char test3[] = \"ab\";\n assert(strcmp(func0(test3), \"AB\") == 0);\n\n char test4[] = \"#a@C\";\n assert(strcmp(func0(test4), \"#A@c\") == 0);\n\n char test5[] = \"#AsdfW^45\";\n assert(strcmp(func0(test5), \"#aSDFw^45\") == 0);\n\n char test6[] = \"#6@2\";\n assert(strcmp(func0(test6), \"2@6#\") == 0);\n\n char test7[] = \"#$a^D\";\n assert(strcmp(func0(test7), \"#$A^d\") == 0);\n\n char test8[] = \"#ccc\";\n assert(strcmp(func0(test8), \"#CCC\") == 0);\n\n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 18h\ncall _strlen\nmov [rsp+48h+var_40], rax\ntest eax, eax\njle short loc_153E\nmov r15, rax\nmov rbx, r12\ncall ___ctype_b_loc\nmov r14, rax\nlea eax, [r15-1]\nxor r15d, r15d\nlea r13, [r12+rax+1]\njmp short loc_151B\nloc_1500:\ntest ah, 1\njz short loc_1550\ncall ___ctype_tolower_loc\nmov rax, [rax]\nmov eax, [rax+rbp*4]\nmov [rbx], al\nloc_1512:\nadd rbx, 1\ncmp r13, rbx\njz short loc_1537\nloc_151B:\nmovzx ebp, byte ptr [rbx]\nmov rax, [r14]\nmovzx eax, word ptr [rax+rbp*2]\ntest ah, 4\njnz short loc_1500\nadd rbx, 1\nadd r15d, 1\ncmp r13, rbx\njnz short loc_151B\nloc_1537:\ncmp dword ptr [rsp+48h+var_40], r15d\njz short loc_1568\nloc_153E:\nadd rsp, 18h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1550:\ntest ah, 2\njz short loc_1512\ncall ___ctype_toupper_loc\nmov rax, [rax]\nmov eax, [rax+rbp*4]\nmov [rbx], al\njmp short loc_1512\nloc_1568:\nmov rax, [rsp+48h+var_40]\nmov edi, eax\nsar edi, 1\ncmp eax, 1\njz short loc_153E\nmovsxd r13, eax\nxor eax, eax\nlea rdx, [r12+r13-1]\nloc_1580:\nmovzx esi, byte ptr [rdx]\nmovzx ecx, byte ptr [r12+rax]\nsub rdx, 1\nmov [r12+rax], sil\nadd rax, 1\nmov [rdx+1], cl\ncmp edi, eax\njg short loc_1580\njmp short loc_153E", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n int v1; // eax\n int v2; // r15d\n char *v3; // rbx\n const unsigned __int16 **v4; // r14\n __int64 v5; // rax\n int v6; // r15d\n __int64 v7; // r13\n __int64 v8; // rbp\n unsigned __int16 v9; // ax\n __int64 v11; // rax\n const char *v12; // rdx\n char v13; // si\n char v14; // cl\n int v15; // [rsp+8h] [rbp-40h]\n\n v1 = strlen(a1);\n v15 = v1;\n if ( v1 > 0 )\n {\n v2 = v1;\n v3 = (char *)a1;\n v4 = __ctype_b_loc();\n v5 = (unsigned int)(v2 - 1);\n v6 = 0;\n v7 = (__int64)&a1[v5 + 1];\n do\n {\n while ( 1 )\n {\n v8 = (unsigned __int8)*v3;\n v9 = (*v4)[v8];\n if ( (v9 & 0x400) != 0 )\n break;\n ++v3;\n ++v6;\n if ( (char *)v7 == v3 )\n goto LABEL_8;\n }\n if ( (v9 & 0x100) != 0 )\n {\n *v3 = (*__ctype_tolower_loc())[v8];\n }\n else if ( (v9 & 0x200) != 0 )\n {\n *v3 = (*__ctype_toupper_loc())[v8];\n }\n ++v3;\n }\n while ( (char *)v7 != v3 );\nLABEL_8:\n if ( v15 == v6 && v15 != 1 )\n {\n v11 = 0LL;\n v12 = &a1[v15 - 1];\n do\n {\n v13 = *v12;\n v14 = a1[v11];\n --v12;\n a1[v11++] = v13;\n *((_BYTE *)v12 + 1) = v14;\n }\n while ( v15 >> 1 > (int)v11 );\n }\n }\n return a1;\n}", + "ida_strip_asm": "sub_14C0:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 18h\ncall _strlen\nmov [rsp+48h+var_40], rax\ntest eax, eax\njle short loc_153E\nmov r15, rax\nmov rbx, r12\ncall ___ctype_b_loc\nmov r14, rax\nlea eax, [r15-1]\nxor r15d, r15d\nlea r13, [r12+rax+1]\njmp short loc_151B\nloc_1500:\ntest ah, 1\njz short loc_1550\ncall ___ctype_tolower_loc\nmov rax, [rax]\nmov eax, [rax+rbp*4]\nmov [rbx], al\nloc_1512:\nadd rbx, 1\ncmp r13, rbx\njz short loc_1537\nloc_151B:\nmovzx ebp, byte ptr [rbx]\nmov rax, [r14]\nmovzx eax, word ptr [rax+rbp*2]\ntest ah, 4\njnz short loc_1500\nadd rbx, 1\nadd r15d, 1\ncmp r13, rbx\njnz short loc_151B\nloc_1537:\ncmp dword ptr [rsp+48h+var_40], r15d\njz short loc_1568\nloc_153E:\nadd rsp, 18h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1550:\ntest ah, 2\njz short loc_1512\ncall ___ctype_toupper_loc\nmov rax, [rax]\nmov eax, [rax+rbp*4]\nmov [rbx], al\njmp short loc_1512\nloc_1568:\nmov rax, [rsp+48h+var_40]\nmov edi, eax\nsar edi, 1\ncmp eax, 1\njz short loc_153E\nmovsxd r13, eax\nxor eax, eax\nlea rdx, [r12+r13-1]\nloc_1580:\nmovzx esi, byte ptr [rdx]\nmovzx ecx, byte ptr [r12+rax]\nsub rdx, 1\nmov [r12+rax], sil\nadd rax, 1\nmov [rdx+1], cl\ncmp edi, eax\njg short loc_1580\njmp short loc_153E", + "ida_strip_pseudo": "const char *__fastcall sub_14C0(const char *a1)\n{\n int v1; // eax\n int v2; // r15d\n char *v3; // rbx\n const unsigned __int16 **v4; // r14\n __int64 v5; // rax\n int v6; // r15d\n __int64 v7; // r13\n __int64 v8; // rbp\n unsigned __int16 v9; // ax\n __int64 v11; // rax\n const char *v12; // rdx\n char v13; // si\n char v14; // cl\n int v15; // [rsp+8h] [rbp-40h]\n\n v1 = strlen(a1);\n v15 = v1;\n if ( v1 > 0 )\n {\n v2 = v1;\n v3 = (char *)a1;\n v4 = __ctype_b_loc();\n v5 = (unsigned int)(v2 - 1);\n v6 = 0;\n v7 = (__int64)&a1[v5 + 1];\n do\n {\n while ( 1 )\n {\n v8 = (unsigned __int8)*v3;\n v9 = (*v4)[v8];\n if ( (v9 & 0x400) != 0 )\n break;\n ++v3;\n ++v6;\n if ( (char *)v7 == v3 )\n goto LABEL_8;\n }\n if ( (v9 & 0x100) != 0 )\n {\n *v3 = (*__ctype_tolower_loc())[v8];\n }\n else if ( (v9 & 0x200) != 0 )\n {\n *v3 = (*__ctype_toupper_loc())[v8];\n }\n ++v3;\n }\n while ( (char *)v7 != v3 );\nLABEL_8:\n if ( v15 == v6 && v15 != 1 )\n {\n v11 = 0LL;\n v12 = &a1[v15 - 1];\n do\n {\n v13 = *v12;\n v14 = a1[v11];\n --v12;\n a1[v11++] = v13;\n *((_BYTE *)v12 + 1) = v14;\n }\n while ( v15 >> 1 > (int)v11 );\n }\n }\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_14C0(const char *a1) {\n int v1;\n int v2;\n char *v3;\n const unsigned short **v4;\n long long v5;\n int v6;\n long long v7;\n long long v8;\n unsigned short v9;\n long long v11;\n const char *v12;\n char v13;\n char v14;\n int v15;\n v1 = strlen(a1);\n v15 = v1;\n if (v1 > 0) {\n v2 = v1;\n v3 = (char *)a1;\n v4 = __ctype_b_loc();\n v5 = (unsigned int)(v2 - 1);\n v6 = 0;\n v7 = (long long)&a1[v5 + 1];\n do {\n while (1) {\n v8 = (unsigned char)*v3;\n v9 = (*v4)[v8];\n if ((v9 & 1024) != 0) break;\n ++v3;\n ++v6;\n if ((char *)v7 == v3) goto LABEL_8;\n }\n if ((v9 & 256) != 0) {\n *v3 = (*__ctype_tolower_loc())[v8];\n } else if ((v9 & 512) != 0) {\n *v3 = (*__ctype_toupper_loc())[v8];\n }\n ++v3;\n } while ((char *)v7 != v3);\n LABEL_8:\n if (v15 == v6 && v15 != 1) {\n v11 = 0LL;\n v12 = &a1[v15 - 1];\n do {\n v13 = *v12;\n v14 = a1[v11];\n --v12;\n a1[v11++] = v13;\n *((uint8_t *)v12 + 1) = v14;\n } while (v15 >> 1 > (int)v11);\n }\n }\n return a1;\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n int v1;\n int v2;\n char *v3;\n const unsigned short **v4;\n long long v5;\n int v6;\n long long v7;\n long long v8;\n unsigned short v9;\n long long v11;\n const char *v12;\n char v13;\n char v14;\n int v15;\n v1 = strlen(a1);\n v15 = v1;\n if (v1 > 0) {\n v2 = v1;\n v3 = (char *)a1;\n v4 = __ctype_b_loc();\n v5 = (unsigned int)(v2 - 1);\n v6 = 0;\n v7 = (long long)&a1[v5 + 1];\n do {\n while (1) {\n v8 = (unsigned char)*v3;\n v9 = (*v4)[v8];\n if ((v9 & 1024) != 0) break;\n ++v3;\n ++v6;\n if ((char *)v7 == v3) goto LABEL_8;\n }\n if ((v9 & 256) != 0) {\n *v3 = (*__ctype_tolower_loc())[v8];\n } else if ((v9 & 512) != 0) {\n *v3 = (*__ctype_toupper_loc())[v8];\n }\n ++v3;\n } while ((char *)v7 != v3);\n LABEL_8:\n if (v15 == v6 && v15 != 1) {\n v11 = 0LL;\n v12 = &a1[v15 - 1];\n do {\n v13 = *v12;\n v14 = a1[v11];\n --v12;\n a1[v11++] = v13;\n *((uint8_t *)v12 + 1) = v14;\n } while (v15 >> 1 > (int)v11);\n }\n }\n return a1;\n}" + }, + { + "index": "HumanEval-C-162", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char* func0(const char* text) {\n if (strlen(text) == 0) {\n return strdup(\"None\");\n }\n unsigned int crc = 0xFFFFFFFF;\n unsigned int i, j;\n unsigned char byte;\n for (i = 0; text[i] != '\\0'; i++) {\n byte = text[i];\n crc = crc ^ byte;\n for (j = 0; j < 8; j++) {\n if (crc & 1) {\n crc = (crc >> 1) ^ 0xEDB88320;\n } else {\n crc = crc >> 1;\n }\n }\n }\n crc = ~crc;\n char* result = malloc(9);\n if (result != NULL) {\n sprintf(result, \"%08X\", crc);\n }\n return result;\n}", + "test": "#include \n#include \n#include \n\nint main() {\n char* result;\n\n // Test 1\n result = func0(\"Hello world\");\n assert(strcmp(result, \"8BD69E52\") == 0);\n free(result); // Free the allocated memory\n\n // Test 2\n result = func0(\"\");\n assert(strcmp(result, \"None\") == 0);\n free(result); // Free the allocated memory\n\n // Test 3\n result = func0(\"foobar\");\n assert(strcmp(result, \"9EF61F95\") == 0); \n free(result); // Free the allocated memory\n\n // Test 4\n result = func0(\"abcd1234\");\n assert(strcmp(result, \"3D3FB146\") == 0);\n free(result); // Free the allocated memory\n\n // Test 5\n result = func0(\"test string\");\n assert(strcmp(result, \"13471545\") == 0);\n free(result); // Free the allocated memory\n \n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov rax, [rbp+var_28]\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1218\nlea rax, s; \"None\"\nmov rdi, rax; s\ncall _strdup\njmp locret_12BD\nloc_1218:\nmov [rbp+var_14], 0FFFFFFFFh\nmov [rbp+var_10], 0\njmp short loc_1272\nloc_1228:\nmov edx, [rbp+var_10]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_15], al\nmovzx eax, [rbp+var_15]\nxor [rbp+var_14], eax\nmov [rbp+var_C], 0\njmp short loc_1268\nloc_1248:\nmov eax, [rbp+var_14]\nand eax, 1\ntest eax, eax\njz short loc_1261\nmov eax, [rbp+var_14]\nshr eax, 1\nxor eax, 0EDB88320h\nmov [rbp+var_14], eax\njmp short loc_1264\nloc_1261:\nshr [rbp+var_14], 1\nloc_1264:\nadd [rbp+var_C], 1\nloc_1268:\ncmp [rbp+var_C], 7\njbe short loc_1248\nadd [rbp+var_10], 1\nloc_1272:\nmov edx, [rbp+var_10]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1228\nnot [rbp+var_14]\nmov edi, 9; size\ncall _malloc\nmov [rbp+s], rax\ncmp [rbp+s], 0\njz short loc_12B9\nmov edx, [rbp+var_14]\nmov rax, [rbp+s]\nlea rcx, format; \"%08X\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nloc_12B9:\nmov rax, [rbp+s]\nlocret_12BD:\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(_BYTE *a1)\n{\n unsigned int v2; // [rsp+1Ch] [rbp-14h]\n int v3; // [rsp+1Ch] [rbp-14h]\n int i; // [rsp+20h] [rbp-10h]\n unsigned int j; // [rsp+24h] [rbp-Ch]\n char *s; // [rsp+28h] [rbp-8h]\n\n if ( !*a1 )\n return strdup(\"None\");\n v2 = -1;\n for ( i = 0; a1[i]; ++i )\n {\n v2 ^= (unsigned __int8)a1[i];\n for ( j = 0; j <= 7; ++j )\n {\n if ( (v2 & 1) != 0 )\n v2 = (v2 >> 1) ^ 0xEDB88320;\n else\n v2 >>= 1;\n }\n }\n v3 = ~v2;\n s = (char *)malloc(9uLL);\n if ( s )\n sprintf(s, \"%08X\", v3);\n return s;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov rax, [rbp+var_28]\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1218\nlea rax, s; \"None\"\nmov rdi, rax; s\ncall _strdup\njmp locret_12BD\nloc_1218:\nmov [rbp+var_14], 0FFFFFFFFh\nmov [rbp+var_10], 0\njmp short loc_1272\nloc_1228:\nmov edx, [rbp+var_10]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_15], al\nmovzx eax, [rbp+var_15]\nxor [rbp+var_14], eax\nmov [rbp+var_C], 0\njmp short loc_1268\nloc_1248:\nmov eax, [rbp+var_14]\nand eax, 1\ntest eax, eax\njz short loc_1261\nmov eax, [rbp+var_14]\nshr eax, 1\nxor eax, 0EDB88320h\nmov [rbp+var_14], eax\njmp short loc_1264\nloc_1261:\nshr [rbp+var_14], 1\nloc_1264:\nadd [rbp+var_C], 1\nloc_1268:\ncmp [rbp+var_C], 7\njbe short loc_1248\nadd [rbp+var_10], 1\nloc_1272:\nmov edx, [rbp+var_10]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1228\nnot [rbp+var_14]\nmov edi, 9; size\ncall _malloc\nmov [rbp+s], rax\ncmp [rbp+s], 0\njz short loc_12B9\nmov edx, [rbp+var_14]\nmov rax, [rbp+s]\nlea rcx, format; \"%08X\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nloc_12B9:\nmov rax, [rbp+s]\nlocret_12BD:\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11E9(_BYTE *a1)\n{\n unsigned int v2; // [rsp+1Ch] [rbp-14h]\n int v3; // [rsp+1Ch] [rbp-14h]\n int i; // [rsp+20h] [rbp-10h]\n unsigned int j; // [rsp+24h] [rbp-Ch]\n char *s; // [rsp+28h] [rbp-8h]\n\n if ( !*a1 )\n return strdup(\"None\");\n v2 = -1;\n for ( i = 0; a1[i]; ++i )\n {\n v2 ^= (unsigned __int8)a1[i];\n for ( j = 0; j <= 7; ++j )\n {\n if ( (v2 & 1) != 0 )\n v2 = (v2 >> 1) ^ 0xEDB88320;\n else\n v2 >>= 1;\n }\n }\n v3 = ~v2;\n s = (char *)malloc(9uLL);\n if ( s )\n sprintf(s, \"%08X\", v3);\n return s;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11E9(uint8_t *a1) {\n unsigned int v2;\n int v3;\n int i;\n unsigned int j;\n char *s;\n if (!*a1) return strdup(\"None\");\n v2 = -1;\n for (i = 0; a1[i]; ++i) {\n v2 ^= (unsigned char)a1[i];\n for (j = 0; j <= 7; ++j) {\n if ((v2 & 1) != 0)\n v2 = (v2 >> 1) ^ 3988292384;\n else\n v2 >>= 1;\n }\n }\n v3 = ~v2;\n s = (char *)malloc(9uLL);\n if (s) sprintf(s, \"%08X\", v3);\n return s;\n}", + "ida_pseudo_norm": "char *func0(uint8_t *a1) {\n unsigned int v2;\n int v3;\n int i;\n unsigned int j;\n char *s;\n if (!*a1) return strdup(\"None\");\n v2 = -1;\n for (i = 0; a1[i]; ++i) {\n v2 ^= (unsigned char)a1[i];\n for (j = 0; j <= 7; ++j) {\n if ((v2 & 1) != 0)\n v2 = (v2 >> 1) ^ 3988292384;\n else\n v2 >>= 1;\n }\n }\n v3 = ~v2;\n s = (char *)malloc(9uLL);\n if (s) sprintf(s, \"%08X\", v3);\n return s;\n}" + }, + { + "index": "HumanEval-C-162", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char* func0(const char* text) {\n if (strlen(text) == 0) {\n return strdup(\"None\");\n }\n unsigned int crc = 0xFFFFFFFF;\n unsigned int i, j;\n unsigned char byte;\n for (i = 0; text[i] != '\\0'; i++) {\n byte = text[i];\n crc = crc ^ byte;\n for (j = 0; j < 8; j++) {\n if (crc & 1) {\n crc = (crc >> 1) ^ 0xEDB88320;\n } else {\n crc = crc >> 1;\n }\n }\n }\n crc = ~crc;\n char* result = malloc(9);\n if (result != NULL) {\n sprintf(result, \"%08X\", crc);\n }\n return result;\n}", + "test": "#include \n#include \n#include \n\nint main() {\n char* result;\n\n // Test 1\n result = func0(\"Hello world\");\n assert(strcmp(result, \"8BD69E52\") == 0);\n free(result); // Free the allocated memory\n\n // Test 2\n result = func0(\"\");\n assert(strcmp(result, \"None\") == 0);\n free(result); // Free the allocated memory\n\n // Test 3\n result = func0(\"foobar\");\n assert(strcmp(result, \"9EF61F95\") == 0); \n free(result); // Free the allocated memory\n\n // Test 4\n result = func0(\"abcd1234\");\n assert(strcmp(result, \"3D3FB146\") == 0);\n free(result); // Free the allocated memory\n\n // Test 5\n result = func0(\"test string\");\n assert(strcmp(result, \"13471545\") == 0);\n free(result); // Free the allocated memory\n \n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmovzx eax, byte ptr [rdi]\nmov esi, 0\nmov r8d, 0FFFFFFFFh\ntest al, al\njnz short loc_1223\nlea rdi, s; \"None\"\ncall _strdup\nmov rbp, rax\njmp short loc_1286\nloc_1216:\nadd esi, 1\nmov eax, esi\nmovzx eax, byte ptr [rdi+rax]\ntest al, al\njz short loc_124E\nloc_1223:\nmovzx eax, al\nxor r8d, eax\nmov edx, 8\nloc_122E:\nmov eax, r8d\nshr eax, 1\nxor eax, 0EDB88320h\nmov ecx, r8d\nshr ecx, 1\ntest r8b, 1\ncmovz eax, ecx\nmov r8d, eax\nsub edx, 1\njnz short loc_122E\njmp short loc_1216\nloc_124E:\nmov ebx, r8d\nnot ebx\nmov edi, 9; size\ncall _malloc\nmov rbp, rax\ntest rax, rax\njz short loc_1286\nmov r8d, ebx\nlea rcx, a08x; \"%08X\"\nmov edx, 9\nmov esi, 2\nmov rdi, rax\nmov eax, 0\ncall ___sprintf_chk\nloc_1286:\nmov rax, rbp\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_pseudo": "char *__fastcall func0(unsigned __int8 *a1)\n{\n unsigned __int8 v1; // al\n int v2; // esi\n unsigned int v3; // r8d\n void *v4; // rbp\n int v5; // edx\n unsigned int v6; // eax\n int v7; // ebx\n void *v8; // rax\n\n v1 = *a1;\n v2 = 0;\n v3 = -1;\n if ( !*a1 )\n return strdup(\"None\");\n do\n {\n v3 ^= v1;\n v5 = 8;\n do\n {\n v6 = (v3 >> 1) ^ 0xEDB88320;\n if ( (v3 & 1) == 0 )\n v6 = v3 >> 1;\n v3 = v6;\n --v5;\n }\n while ( v5 );\n v1 = a1[++v2];\n }\n while ( v1 );\n v7 = ~v3;\n v8 = malloc(9uLL);\n v4 = v8;\n if ( v8 )\n __sprintf_chk(v8, 2LL, 9LL, \"%08X\", v7);\n return (char *)v4;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmovzx eax, byte ptr [rdi]\nmov esi, 0\nmov r8d, 0FFFFFFFFh\ntest al, al\njnz short loc_1223\nlea rdi, s; \"None\"\ncall _strdup\nmov rbp, rax\njmp short loc_1286\nloc_1216:\nadd esi, 1\nmov eax, esi\nmovzx eax, byte ptr [rdi+rax]\ntest al, al\njz short loc_124E\nloc_1223:\nmovzx eax, al\nxor r8d, eax\nmov edx, 8\nloc_122E:\nmov eax, r8d\nshr eax, 1\nxor eax, 0EDB88320h\nmov ecx, r8d\nshr ecx, 1\ntest r8b, 1\ncmovz eax, ecx\nmov r8d, eax\nsub edx, 1\njnz short loc_122E\njmp short loc_1216\nloc_124E:\nmov ebx, r8d\nnot ebx\nmov edi, 9; size\ncall _malloc\nmov rbp, rax\ntest rax, rax\njz short loc_1286\nmov r8d, ebx\nlea rcx, a08x; \"%08X\"\nmov edx, 9\nmov esi, 2\nmov rdi, rax\nmov eax, 0\ncall ___sprintf_chk\nloc_1286:\nmov rax, rbp\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11E9(unsigned __int8 *a1)\n{\n unsigned __int8 v1; // al\n int v2; // esi\n unsigned int v3; // r8d\n void *v4; // rbp\n int v5; // edx\n unsigned int v6; // eax\n int v7; // ebx\n void *v8; // rax\n\n v1 = *a1;\n v2 = 0;\n v3 = -1;\n if ( !*a1 )\n return strdup(\"None\");\n do\n {\n v3 ^= v1;\n v5 = 8;\n do\n {\n v6 = (v3 >> 1) ^ 0xEDB88320;\n if ( (v3 & 1) == 0 )\n v6 = v3 >> 1;\n v3 = v6;\n --v5;\n }\n while ( v5 );\n v1 = a1[++v2];\n }\n while ( v1 );\n v7 = ~v3;\n v8 = malloc(9uLL);\n v4 = v8;\n if ( v8 )\n __sprintf_chk(v8, 2LL, 9LL, \"%08X\", v7);\n return (char *)v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11E9(unsigned char *a1) {\n unsigned char v1;\n int v2;\n unsigned int v3;\n void *v4;\n int v5;\n unsigned int v6;\n int v7;\n void *v8;\n v1 = *a1;\n v2 = 0;\n v3 = -1;\n if (!*a1) return strdup(\"None\");\n do {\n v3 ^= v1;\n v5 = 8;\n do {\n v6 = (v3 >> 1) ^ 3988292384;\n if ((v3 & 1) == 0) v6 = v3 >> 1;\n v3 = v6;\n --v5;\n } while (v5);\n v1 = a1[++v2];\n } while (v1);\n v7 = ~v3;\n v8 = malloc(9uLL);\n v4 = v8;\n if (v8) __sprintf_chk(v8, 2LL, 9LL, \"%08X\", v7);\n return (char *)v4;\n}", + "ida_pseudo_norm": "char *func0(unsigned char *a1) {\n unsigned char v1;\n int v2;\n unsigned int v3;\n void *v4;\n int v5;\n unsigned int v6;\n int v7;\n void *v8;\n v1 = *a1;\n v2 = 0;\n v3 = -1;\n if (!*a1) return strdup(\"None\");\n do {\n v3 ^= v1;\n v5 = 8;\n do {\n v6 = (v3 >> 1) ^ 3988292384;\n if ((v3 & 1) == 0) v6 = v3 >> 1;\n v3 = v6;\n --v5;\n } while (v5);\n v1 = a1[++v2];\n } while (v1);\n v7 = ~v3;\n v8 = malloc(9uLL);\n v4 = v8;\n if (v8) __sprintf_chk(v8, 2LL, 9LL, \"%08X\", v7);\n return (char *)v4;\n}" + }, + { + "index": "HumanEval-C-162", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char* func0(const char* text) {\n if (strlen(text) == 0) {\n return strdup(\"None\");\n }\n unsigned int crc = 0xFFFFFFFF;\n unsigned int i, j;\n unsigned char byte;\n for (i = 0; text[i] != '\\0'; i++) {\n byte = text[i];\n crc = crc ^ byte;\n for (j = 0; j < 8; j++) {\n if (crc & 1) {\n crc = (crc >> 1) ^ 0xEDB88320;\n } else {\n crc = crc >> 1;\n }\n }\n }\n crc = ~crc;\n char* result = malloc(9);\n if (result != NULL) {\n sprintf(result, \"%08X\", crc);\n }\n return result;\n}", + "test": "#include \n#include \n#include \n\nint main() {\n char* result;\n\n // Test 1\n result = func0(\"Hello world\");\n assert(strcmp(result, \"8BD69E52\") == 0);\n free(result); // Free the allocated memory\n\n // Test 2\n result = func0(\"\");\n assert(strcmp(result, \"None\") == 0);\n free(result); // Free the allocated memory\n\n // Test 3\n result = func0(\"foobar\");\n assert(strcmp(result, \"9EF61F95\") == 0); \n free(result); // Free the allocated memory\n\n // Test 4\n result = func0(\"abcd1234\");\n assert(strcmp(result, \"3D3FB146\") == 0);\n free(result); // Free the allocated memory\n\n // Test 5\n result = func0(\"test string\");\n assert(strcmp(result, \"13471545\") == 0);\n free(result); // Free the allocated memory\n \n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmovzx eax, byte ptr [rdi]\ntest al, al\njz loc_1415\npush rbp\nxor ecx, ecx\nmov r8d, 0FFFFFFFFh\npush rbx\nsub rsp, 8\nnop dword ptr [rax]\nloc_13A0:\nxor r8d, eax\nmov edx, 8\nnop dword ptr [rax+rax+00000000h]\nloc_13B0:\nmov eax, r8d\nshr r8d, 1\nand eax, 1\nneg eax\nand eax, 0EDB88320h\nxor r8d, eax\nsub edx, 1\njnz short loc_13B0\nlea eax, [rcx+1]\nmov rcx, rax\nmovzx eax, byte ptr [rdi+rax]\ntest al, al\njnz short loc_13A0\nmov edi, 9; size\nmov ebx, r8d\ncall _malloc\nnot ebx\nmov rbp, rax\ntest rax, rax\njz short loc_140B\nmov rdi, rax\nmov r8d, ebx\nlea rcx, a08x; \"%08X\"\nxor eax, eax\nmov edx, 9\nmov esi, 2\ncall ___sprintf_chk\nloc_140B:\nadd rsp, 8\nmov rax, rbp\npop rbx\npop rbp\nretn\nloc_1415:\nlea rdi, s; \"None\"\njmp _strdup", + "ida_pseudo": "char *__fastcall func0(unsigned __int8 *a1)\n{\n int v1; // eax\n __int64 v2; // rcx\n unsigned int v3; // r8d\n int v4; // edx\n unsigned int v5; // ebx\n void *v6; // rax\n int v7; // ebx\n void *v8; // rbp\n\n v1 = *a1;\n if ( !(_BYTE)v1 )\n return strdup(\"None\");\n LODWORD(v2) = 0;\n v3 = -1;\n do\n {\n v3 ^= v1;\n v4 = 8;\n do\n {\n v3 = -(v3 & 1) & 0xEDB88320 ^ (v3 >> 1);\n --v4;\n }\n while ( v4 );\n v2 = (unsigned int)(v2 + 1);\n v1 = a1[v2];\n }\n while ( (_BYTE)v1 );\n v5 = v3;\n v6 = malloc(9uLL);\n v7 = ~v5;\n v8 = v6;\n if ( v6 )\n __sprintf_chk(v6, 2LL, 9LL, \"%08X\", v7);\n return (char *)v8;\n}", + "ida_strip_asm": "sub_1380:\nendbr64\nmovzx eax, byte ptr [rdi]\ntest al, al\njz loc_1415\npush rbp\nxor ecx, ecx\nmov r8d, 0FFFFFFFFh\npush rbx\nsub rsp, 8\nnop dword ptr [rax]\nloc_13A0:\nxor r8d, eax\nmov edx, 8\nnop dword ptr [rax+rax+00000000h]\nloc_13B0:\nmov eax, r8d\nshr r8d, 1\nand eax, 1\nneg eax\nand eax, 0EDB88320h\nxor r8d, eax\nsub edx, 1\njnz short loc_13B0\nlea eax, [rcx+1]\nmov rcx, rax\nmovzx eax, byte ptr [rdi+rax]\ntest al, al\njnz short loc_13A0\nmov edi, 9; size\nmov ebx, r8d\ncall _malloc\nnot ebx\nmov rbp, rax\ntest rax, rax\njz short loc_140B\nmov rdi, rax\nmov r8d, ebx\nlea rcx, a08x; \"%08X\"\nxor eax, eax\nmov edx, 9\nmov esi, 2\ncall ___sprintf_chk\nloc_140B:\nadd rsp, 8\nmov rax, rbp\npop rbx\npop rbp\nretn\nloc_1415:\nlea rdi, s; \"None\"\njmp _strdup", + "ida_strip_pseudo": "char *__fastcall sub_1380(unsigned __int8 *a1)\n{\n int v1; // eax\n __int64 v2; // rcx\n unsigned int v3; // r8d\n int v4; // edx\n unsigned int v5; // ebx\n void *v6; // rax\n int v7; // ebx\n void *v8; // rbp\n\n v1 = *a1;\n if ( !(_BYTE)v1 )\n return strdup(\"None\");\n LODWORD(v2) = 0;\n v3 = -1;\n do\n {\n v3 ^= v1;\n v4 = 8;\n do\n {\n v3 = -(v3 & 1) & 0xEDB88320 ^ (v3 >> 1);\n --v4;\n }\n while ( v4 );\n v2 = (unsigned int)(v2 + 1);\n v1 = a1[v2];\n }\n while ( (_BYTE)v1 );\n v5 = v3;\n v6 = malloc(9uLL);\n v7 = ~v5;\n v8 = v6;\n if ( v6 )\n __sprintf_chk(v6, 2LL, 9LL, \"%08X\", v7);\n return (char *)v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1380(unsigned char *a1) {\n int v1;\n long long v2;\n unsigned int v3;\n int v4;\n unsigned int v5;\n void *v6;\n int v7;\n void *v8;\n v1 = *a1;\n if (!(uint8_t)v1) return strdup(\"None\");\n LODWORD(v2) = 0;\n v3 = -1;\n do {\n v3 ^= v1;\n v4 = 8;\n do {\n v3 = -(v3 & 1) & 3988292384 ^ (v3 >> 1);\n --v4;\n } while (v4);\n v2 = (unsigned int)(v2 + 1);\n v1 = a1[v2];\n } while ((uint8_t)v1);\n v5 = v3;\n v6 = malloc(9uLL);\n v7 = ~v5;\n v8 = v6;\n if (v6) __sprintf_chk(v6, 2LL, 9LL, \"%08X\", v7);\n return (char *)v8;\n}", + "ida_pseudo_norm": "char *func0(unsigned char *a1) {\n int v1;\n long long v2;\n unsigned int v3;\n int v4;\n unsigned int v5;\n void *v6;\n int v7;\n void *v8;\n v1 = *a1;\n if (!(uint8_t)v1) return strdup(\"None\");\n LODWORD(v2) = 0;\n v3 = -1;\n do {\n v3 ^= v1;\n v4 = 8;\n do {\n v3 = -(v3 & 1) & 3988292384 ^ (v3 >> 1);\n --v4;\n } while (v4);\n v2 = (unsigned int)(v2 + 1);\n v1 = a1[v2];\n } while ((uint8_t)v1);\n v5 = v3;\n v6 = malloc(9uLL);\n v7 = ~v5;\n v8 = v6;\n if (v6) __sprintf_chk(v6, 2LL, 9LL, \"%08X\", v7);\n return (char *)v8;\n}" + }, + { + "index": "HumanEval-C-162", + "func_name": "func0", + "func_dep": "#include \n#include \n#include \n", + "func": "char* func0(const char* text) {\n if (strlen(text) == 0) {\n return strdup(\"None\");\n }\n unsigned int crc = 0xFFFFFFFF;\n unsigned int i, j;\n unsigned char byte;\n for (i = 0; text[i] != '\\0'; i++) {\n byte = text[i];\n crc = crc ^ byte;\n for (j = 0; j < 8; j++) {\n if (crc & 1) {\n crc = (crc >> 1) ^ 0xEDB88320;\n } else {\n crc = crc >> 1;\n }\n }\n }\n crc = ~crc;\n char* result = malloc(9);\n if (result != NULL) {\n sprintf(result, \"%08X\", crc);\n }\n return result;\n}", + "test": "#include \n#include \n#include \n\nint main() {\n char* result;\n\n // Test 1\n result = func0(\"Hello world\");\n assert(strcmp(result, \"8BD69E52\") == 0);\n free(result); // Free the allocated memory\n\n // Test 2\n result = func0(\"\");\n assert(strcmp(result, \"None\") == 0);\n free(result); // Free the allocated memory\n\n // Test 3\n result = func0(\"foobar\");\n assert(strcmp(result, \"9EF61F95\") == 0); \n free(result); // Free the allocated memory\n\n // Test 4\n result = func0(\"abcd1234\");\n assert(strcmp(result, \"3D3FB146\") == 0);\n free(result); // Free the allocated memory\n\n // Test 5\n result = func0(\"test string\");\n assert(strcmp(result, \"13471545\") == 0);\n free(result); // Free the allocated memory\n \n return 0;\n}", + "opt": "O3", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmovzx eax, byte ptr [rdi]\ntest al, al\njz loc_1475\npush rbp\nmov rcx, rdi\nxor edx, edx\nmov r8d, 0FFFFFFFFh\npush rbx\nsub rsp, 8\nloc_13A0:\nmovzx eax, al\nxor eax, r8d\nmov esi, eax\nshr eax, 1\nand esi, 1\nneg esi\nand esi, 0EDB88320h\nxor esi, eax\nand eax, 1\nneg eax\nshr esi, 1\nand eax, 0EDB88320h\nxor eax, esi\nand esi, 1\nneg esi\nshr eax, 1\nand esi, 0EDB88320h\nxor esi, eax\nand eax, 1\nneg eax\nshr esi, 1\nand eax, 0EDB88320h\nxor eax, esi\nand esi, 1\nneg esi\nshr eax, 1\nand esi, 0EDB88320h\nxor esi, eax\nand eax, 1\nneg eax\nshr esi, 1\nand eax, 0EDB88320h\nxor eax, esi\nand esi, 1\nmov r8d, esi\nneg r8d\nshr eax, 1\nand r8d, 0EDB88320h\nxor r8d, eax\nand eax, 1\nneg eax\nshr r8d, 1\nand eax, 0EDB88320h\nxor r8d, eax\nlea eax, [rdx+1]\nmov rdx, rax\nmovzx eax, byte ptr [rcx+rax]\ntest al, al\njnz loc_13A0\nmov edi, 9; size\nmov ebx, r8d\ncall _malloc\nnot ebx\nmov rbp, rax\ntest rax, rax\njz short loc_146B\nmov rdi, rax\nmov r8d, ebx\nlea rcx, a08x; \"%08X\"\nxor eax, eax\nmov edx, 9\nmov esi, 2\ncall ___sprintf_chk\nloc_146B:\nadd rsp, 8\nmov rax, rbp\npop rbx\npop rbp\nretn\nloc_1475:\nlea rdi, s; \"None\"\njmp _strdup", + "ida_pseudo": "char *__fastcall func0(unsigned __int8 *a1)\n{\n unsigned __int8 v1; // al\n __int64 v2; // rdx\n unsigned int v3; // r8d\n unsigned int v4; // eax\n char v5; // si\n unsigned int v6; // esi\n unsigned int v7; // eax\n unsigned int v8; // esi\n unsigned int v9; // eax\n unsigned int v10; // esi\n unsigned int v11; // ebx\n void *v12; // rax\n int v13; // ebx\n void *v14; // rbp\n\n v1 = *a1;\n if ( !*a1 )\n return strdup(\"None\");\n LODWORD(v2) = 0;\n v3 = -1;\n do\n {\n v4 = v3 ^ v1;\n v5 = v4;\n v4 >>= 1;\n v6 = (v4 ^ -(v5 & 1) & 0xEDB88320) >> 1;\n v7 = (v6 ^ -(v4 & 1) & 0xEDB88320) >> 1;\n v8 = (v7 ^ -(v6 & 1) & 0xEDB88320) >> 1;\n v9 = (v8 ^ -(v7 & 1) & 0xEDB88320) >> 1;\n v10 = (v9 ^ -(v8 & 1) & 0xEDB88320) >> 1;\n v3 = -(((v10 ^ -(v9 & 1) & 0xEDB88320) >> 1) & 1) & 0xEDB88320 ^ ((((v10 ^ -(v9 & 1) & 0xEDB88320) >> 1) ^ -(v10 & 1) & 0xEDB88320) >> 1);\n v2 = (unsigned int)(v2 + 1);\n v1 = a1[v2];\n }\n while ( v1 );\n v11 = v3;\n v12 = malloc(9uLL);\n v13 = ~v11;\n v14 = v12;\n if ( v12 )\n __sprintf_chk(v12, 2LL, 9LL, \"%08X\", v13);\n return (char *)v14;\n}", + "ida_strip_asm": "sub_1380:\nendbr64\nmovzx eax, byte ptr [rdi]\ntest al, al\njz loc_1475\npush rbp\nmov rcx, rdi\nxor edx, edx\nmov r8d, 0FFFFFFFFh\npush rbx\nsub rsp, 8\nloc_13A0:\nmovzx eax, al\nxor eax, r8d\nmov esi, eax\nshr eax, 1\nand esi, 1\nneg esi\nand esi, 0EDB88320h\nxor esi, eax\nand eax, 1\nneg eax\nshr esi, 1\nand eax, 0EDB88320h\nxor eax, esi\nand esi, 1\nneg esi\nshr eax, 1\nand esi, 0EDB88320h\nxor esi, eax\nand eax, 1\nneg eax\nshr esi, 1\nand eax, 0EDB88320h\nxor eax, esi\nand esi, 1\nneg esi\nshr eax, 1\nand esi, 0EDB88320h\nxor esi, eax\nand eax, 1\nneg eax\nshr esi, 1\nand eax, 0EDB88320h\nxor eax, esi\nand esi, 1\nmov r8d, esi\nneg r8d\nshr eax, 1\nand r8d, 0EDB88320h\nxor r8d, eax\nand eax, 1\nneg eax\nshr r8d, 1\nand eax, 0EDB88320h\nxor r8d, eax\nlea eax, [rdx+1]\nmov rdx, rax\nmovzx eax, byte ptr [rcx+rax]\ntest al, al\njnz loc_13A0\nmov edi, 9; size\nmov ebx, r8d\ncall _malloc\nnot ebx\nmov rbp, rax\ntest rax, rax\njz short loc_146B\nmov rdi, rax\nmov r8d, ebx\nlea rcx, a08x; \"%08X\"\nxor eax, eax\nmov edx, 9\nmov esi, 2\ncall ___sprintf_chk\nloc_146B:\nadd rsp, 8\nmov rax, rbp\npop rbx\npop rbp\nretn\nloc_1475:\nlea rdi, s; \"None\"\njmp _strdup", + "ida_strip_pseudo": "char *__fastcall sub_1380(unsigned __int8 *a1)\n{\n unsigned __int8 v1; // al\n __int64 v2; // rdx\n unsigned int v3; // r8d\n unsigned int v4; // eax\n char v5; // si\n unsigned int v6; // esi\n unsigned int v7; // eax\n unsigned int v8; // esi\n unsigned int v9; // eax\n unsigned int v10; // esi\n unsigned int v11; // ebx\n void *v12; // rax\n int v13; // ebx\n void *v14; // rbp\n\n v1 = *a1;\n if ( !*a1 )\n return strdup(\"None\");\n LODWORD(v2) = 0;\n v3 = -1;\n do\n {\n v4 = v3 ^ v1;\n v5 = v4;\n v4 >>= 1;\n v6 = (v4 ^ -(v5 & 1) & 0xEDB88320) >> 1;\n v7 = (v6 ^ -(v4 & 1) & 0xEDB88320) >> 1;\n v8 = (v7 ^ -(v6 & 1) & 0xEDB88320) >> 1;\n v9 = (v8 ^ -(v7 & 1) & 0xEDB88320) >> 1;\n v10 = (v9 ^ -(v8 & 1) & 0xEDB88320) >> 1;\n v3 = -(((v10 ^ -(v9 & 1) & 0xEDB88320) >> 1) & 1) & 0xEDB88320 ^ ((((v10 ^ -(v9 & 1) & 0xEDB88320) >> 1) ^ -(v10 & 1) & 0xEDB88320) >> 1);\n v2 = (unsigned int)(v2 + 1);\n v1 = a1[v2];\n }\n while ( v1 );\n v11 = v3;\n v12 = malloc(9uLL);\n v13 = ~v11;\n v14 = v12;\n if ( v12 )\n __sprintf_chk(v12, 2LL, 9LL, \"%08X\", v13);\n return (char *)v14;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1380(unsigned char *a1) {\n unsigned char v1;\n long long v2;\n unsigned int v3;\n unsigned int v4;\n char v5;\n unsigned int v6;\n unsigned int v7;\n unsigned int v8;\n unsigned int v9;\n unsigned int v10;\n unsigned int v11;\n void *v12;\n int v13;\n void *v14;\n v1 = *a1;\n if (!*a1) return strdup(\"None\");\n LODWORD(v2) = 0;\n v3 = -1;\n do {\n v4 = v3 ^ v1;\n v5 = v4;\n v4 >>= 1;\n v6 = (v4 ^ -(v5 & 1) & 3988292384) >> 1;\n v7 = (v6 ^ -(v4 & 1) & 3988292384) >> 1;\n v8 = (v7 ^ -(v6 & 1) & 3988292384) >> 1;\n v9 = (v8 ^ -(v7 & 1) & 3988292384) >> 1;\n v10 = (v9 ^ -(v8 & 1) & 3988292384) >> 1;\n v3 = -(((v10 ^ -(v9 & 1) & 3988292384) >> 1) & 1) & 3988292384 ^\n ((((v10 ^ -(v9 & 1) & 3988292384) >> 1) ^ -(v10 & 1) & 3988292384) >>\n 1);\n v2 = (unsigned int)(v2 + 1);\n v1 = a1[v2];\n } while (v1);\n v11 = v3;\n v12 = malloc(9uLL);\n v13 = ~v11;\n v14 = v12;\n if (v12) __sprintf_chk(v12, 2LL, 9LL, \"%08X\", v13);\n return (char *)v14;\n}", + "ida_pseudo_norm": "char *func0(unsigned char *a1) {\n unsigned char v1;\n long long v2;\n unsigned int v3;\n unsigned int v4;\n char v5;\n unsigned int v6;\n unsigned int v7;\n unsigned int v8;\n unsigned int v9;\n unsigned int v10;\n unsigned int v11;\n void *v12;\n int v13;\n void *v14;\n v1 = *a1;\n if (!*a1) return strdup(\"None\");\n LODWORD(v2) = 0;\n v3 = -1;\n do {\n v4 = v3 ^ v1;\n v5 = v4;\n v4 >>= 1;\n v6 = (v4 ^ -(v5 & 1) & 3988292384) >> 1;\n v7 = (v6 ^ -(v4 & 1) & 3988292384) >> 1;\n v8 = (v7 ^ -(v6 & 1) & 3988292384) >> 1;\n v9 = (v8 ^ -(v7 & 1) & 3988292384) >> 1;\n v10 = (v9 ^ -(v8 & 1) & 3988292384) >> 1;\n v3 = -(((v10 ^ -(v9 & 1) & 3988292384) >> 1) & 1) & 3988292384 ^\n ((((v10 ^ -(v9 & 1) & 3988292384) >> 1) ^ -(v10 & 1) & 3988292384) >>\n 1);\n v2 = (unsigned int)(v2 + 1);\n v1 = a1[v2];\n } while (v1);\n v11 = v3;\n v12 = malloc(9uLL);\n v13 = ~v11;\n v14 = v12;\n if (v12) __sprintf_chk(v12, 2LL, 9LL, \"%08X\", v13);\n return (char *)v14;\n}" + }, + { + "index": "HumanEval-C-163", + "func_name": "func0", + "func_dep": "#include \n", + "func": "void func0(int a, int b, int *out, int *size) {\n int m;\n *size = 0;\n if (b < a) {\n m = a;\n a = b;\n b = m;\n }\n for (int i = a; i <= b; i++) {\n if (i < 10 && i % 2 == 0) {\n out[(*size)++] = i;\n }\n }\n}", + "test": "#include \n#include \n\nint issame(const int *a, int a_size, const int *b, int b_size) {\n if (a_size != b_size) return 0;\n for (int i = 0; i < a_size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int result[10], size;\n\n int expected1[] = {2, 4, 6, 8};\n func0(2, 10, result, &size);\n assert(issame(result, size, expected1, 4));\n\n int expected2[] = {2, 4, 6, 8};\n func0(10, 2, result, &size);\n assert(issame(result, size, expected2, 4));\n\n int expected3[] = {2, 4, 6, 8};\n func0(132, 2, result, &size);\n assert(issame(result, size, expected3, 4));\n\n int expected4[] = {}; // Empty set\n func0(17, 89, result, &size);\n assert(issame(result, size, expected4, 0));\n\n printf(\"All tests passed.\\n\");\n\n return 0;\n}", + "opt": "O0", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_20], rdx\nmov [rbp+var_28], rcx\nmov rax, [rbp+var_28]\nmov dword ptr [rax], 0\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_14]\njge short loc_11C3\nmov eax, [rbp+var_14]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_18]\nmov [rbp+var_14], eax\nmov eax, [rbp+var_4]\nmov [rbp+var_18], eax\nloc_11C3:\nmov eax, [rbp+var_14]\nmov [rbp+var_8], eax\njmp short loc_1204\nloc_11CB:\ncmp [rbp+var_8], 9\njg short loc_1200\nmov eax, [rbp+var_8]\nand eax, 1\ntest eax, eax\njnz short loc_1200\nmov rax, [rbp+var_28]\nmov eax, [rax]\nlea ecx, [rax+1]\nmov rdx, [rbp+var_28]\nmov [rdx], ecx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rdx, rax\nmov eax, [rbp+var_8]\nmov [rdx], eax\nloc_1200:\nadd [rbp+var_8], 1\nloc_1204:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_18]\njle short loc_11CB\nnop\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, __int64 a3, _DWORD *a4)\n{\n int v4; // eax\n __int64 result; // rax\n int v6; // [rsp+10h] [rbp-18h]\n int v7; // [rsp+14h] [rbp-14h]\n int i; // [rsp+20h] [rbp-8h]\n\n v7 = a1;\n v6 = a2;\n *a4 = 0;\n if ( a2 < a1 )\n {\n v7 = a2;\n v6 = a1;\n }\n for ( i = v7; ; ++i )\n {\n result = (unsigned int)i;\n if ( i > v6 )\n break;\n if ( i <= 9 && (i & 1) == 0 )\n {\n v4 = (*a4)++;\n *(_DWORD *)(a3 + 4LL * v4) = i;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_20], rdx\nmov [rbp+var_28], rcx\nmov rax, [rbp+var_28]\nmov dword ptr [rax], 0\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_14]\njge short loc_11C3\nmov eax, [rbp+var_14]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_18]\nmov [rbp+var_14], eax\nmov eax, [rbp+var_4]\nmov [rbp+var_18], eax\nloc_11C3:\nmov eax, [rbp+var_14]\nmov [rbp+var_8], eax\njmp short loc_1204\nloc_11CB:\ncmp [rbp+var_8], 9\njg short loc_1200\nmov eax, [rbp+var_8]\nand eax, 1\ntest eax, eax\njnz short loc_1200\nmov rax, [rbp+var_28]\nmov eax, [rax]\nlea ecx, [rax+1]\nmov rdx, [rbp+var_28]\nmov [rdx], ecx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rdx, rax\nmov eax, [rbp+var_8]\nmov [rdx], eax\nloc_1200:\nadd [rbp+var_8], 1\nloc_1204:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_18]\njle short loc_11CB\nnop\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(int a1, int a2, __int64 a3, _DWORD *a4)\n{\n int v4; // eax\n __int64 result; // rax\n int v6; // [rsp+10h] [rbp-18h]\n int v7; // [rsp+14h] [rbp-14h]\n int i; // [rsp+20h] [rbp-8h]\n\n v7 = a1;\n v6 = a2;\n *a4 = 0;\n if ( a2 < a1 )\n {\n v7 = a2;\n v6 = a1;\n }\n for ( i = v7; ; ++i )\n {\n result = (unsigned int)i;\n if ( i > v6 )\n break;\n if ( i <= 9 && (i & 1) == 0 )\n {\n v4 = (*a4)++;\n *(_DWORD *)(a3 + 4LL * v4) = i;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(int a1, int a2, long long a3, uint32_t *a4) {\n int v4;\n long long result;\n int v6;\n int v7;\n int i;\n v7 = a1;\n v6 = a2;\n *a4 = 0;\n if (a2 < a1) {\n v7 = a2;\n v6 = a1;\n }\n for (i = v7;; ++i) {\n result = (unsigned int)i;\n if (i > v6) break;\n if (i <= 9 && (i & 1) == 0) {\n v4 = (*a4)++;\n *(uint32_t *)(a3 + 4LL * v4) = i;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, long long a3, uint32_t *a4) {\n int v4;\n long long result;\n int v6;\n int v7;\n int i;\n v7 = a1;\n v6 = a2;\n *a4 = 0;\n if (a2 < a1) {\n v7 = a2;\n v6 = a1;\n }\n for (i = v7;; ++i) {\n result = (unsigned int)i;\n if (i > v6) break;\n if (i <= 9 && (i & 1) == 0) {\n v4 = (*a4)++;\n *(uint32_t *)(a3 + 4LL * v4) = i;\n }\n }\n return result;\n}" + }, + { + "index": "HumanEval-C-163", + "func_name": "func0", + "func_dep": "#include \n", + "func": "void func0(int a, int b, int *out, int *size) {\n int m;\n *size = 0;\n if (b < a) {\n m = a;\n a = b;\n b = m;\n }\n for (int i = a; i <= b; i++) {\n if (i < 10 && i % 2 == 0) {\n out[(*size)++] = i;\n }\n }\n}", + "test": "#include \n#include \n\nint issame(const int *a, int a_size, const int *b, int b_size) {\n if (a_size != b_size) return 0;\n for (int i = 0; i < a_size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int result[10], size;\n\n int expected1[] = {2, 4, 6, 8};\n func0(2, 10, result, &size);\n assert(issame(result, size, expected1, 4));\n\n int expected2[] = {2, 4, 6, 8};\n func0(10, 2, result, &size);\n assert(issame(result, size, expected2, 4));\n\n int expected3[] = {2, 4, 6, 8};\n func0(132, 2, result, &size);\n assert(issame(result, size, expected3, 4));\n\n int expected4[] = {}; // Empty set\n func0(17, 89, result, &size);\n assert(issame(result, size, expected4, 0));\n\n printf(\"All tests passed.\\n\");\n\n return 0;\n}", + "opt": "O1", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmov dword ptr [rcx], 0\ncmp esi, edi\njl short loc_119D\nmov eax, esi\nmov esi, edi\nmov edi, eax\nloc_119D:\nadd edi, 1\njmp short loc_11A9\nloc_11A2:\nadd esi, 1\ncmp esi, edi\njz short locret_11C4\nloc_11A9:\ncmp esi, 9\njg short loc_11A2\ntest sil, 1\njnz short loc_11A2\nmov eax, [rcx]\nlea r8d, [rax+1]\nmov [rcx], r8d\ncdqe\nmov [rdx+rax*4], esi\njmp short loc_11A2\nlocret_11C4:\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, __int64 a3, _DWORD *a4)\n{\n __int64 result; // rax\n int v5; // edi\n\n *a4 = 0;\n if ( a2 >= a1 )\n {\n result = (unsigned int)a2;\n a2 = a1;\n a1 = result;\n }\n v5 = a1 + 1;\n do\n {\n if ( a2 <= 9 && (a2 & 1) == 0 )\n {\n LODWORD(result) = (*a4)++;\n result = (int)result;\n *(_DWORD *)(a3 + 4LL * (int)result) = a2;\n }\n ++a2;\n }\n while ( a2 != v5 );\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\nmov dword ptr [rcx], 0\ncmp esi, edi\njl short loc_119D\nmov eax, esi\nmov esi, edi\nmov edi, eax\nloc_119D:\nadd edi, 1\njmp short loc_11A9\nloc_11A2:\nadd esi, 1\ncmp esi, edi\njz short locret_11C4\nloc_11A9:\ncmp esi, 9\njg short loc_11A2\ntest sil, 1\njnz short loc_11A2\nmov eax, [rcx]\nlea r8d, [rax+1]\nmov [rcx], r8d\ncdqe\nmov [rdx+rax*4], esi\njmp short loc_11A2\nlocret_11C4:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(int a1, int a2, __int64 a3, _DWORD *a4)\n{\n __int64 result; // rax\n int v5; // edi\n\n *a4 = 0;\n if ( a2 >= a1 )\n {\n result = (unsigned int)a2;\n a2 = a1;\n a1 = result;\n }\n v5 = a1 + 1;\n do\n {\n if ( a2 <= 9 && (a2 & 1) == 0 )\n {\n LODWORD(result) = (*a4)++;\n result = (int)result;\n *(_DWORD *)(a3 + 4LL * (int)result) = a2;\n }\n ++a2;\n }\n while ( a2 != v5 );\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(int a1, int a2, long long a3, uint32_t *a4) {\n long long result;\n int v5;\n *a4 = 0;\n if (a2 >= a1) {\n result = (unsigned int)a2;\n a2 = a1;\n a1 = result;\n }\n v5 = a1 + 1;\n do {\n if (a2 <= 9 && (a2 & 1) == 0) {\n LODWORD(result) = (*a4)++;\n result = (int)result;\n *(uint32_t *)(a3 + 4LL * (int)result) = a2;\n }\n ++a2;\n } while (a2 != v5);\n return result;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, long long a3, uint32_t *a4) {\n long long result;\n int v5;\n *a4 = 0;\n if (a2 >= a1) {\n result = (unsigned int)a2;\n a2 = a1;\n a1 = result;\n }\n v5 = a1 + 1;\n do {\n if (a2 <= 9 && (a2 & 1) == 0) {\n LODWORD(result) = (*a4)++;\n result = (int)result;\n *(uint32_t *)(a3 + 4LL * (int)result) = a2;\n }\n ++a2;\n } while (a2 != v5);\n return result;\n}" + }, + { + "index": "HumanEval-C-163", + "func_name": "func0", + "func_dep": "#include \n", + "func": "void func0(int a, int b, int *out, int *size) {\n int m;\n *size = 0;\n if (b < a) {\n m = a;\n a = b;\n b = m;\n }\n for (int i = a; i <= b; i++) {\n if (i < 10 && i % 2 == 0) {\n out[(*size)++] = i;\n }\n }\n}", + "test": "#include \n#include \n\nint issame(const int *a, int a_size, const int *b, int b_size) {\n if (a_size != b_size) return 0;\n for (int i = 0; i < a_size; i++) {\n if (a[i] != b[i]) return 0;\n }\n return 1;\n}\n\nint main() {\n int result[10], size;\n\n int expected1[] = {2, 4, 6, 8};\n func0(2, 10, result, &size);\n assert(issame(result, size, expected1, 4));\n\n int expected2[] = {2, 4, 6, 8};\n func0(10, 2, result, &size);\n assert(issame(result, size, expected2, 4));\n\n int expected3[] = {2, 4, 6, 8};\n func0(132, 2, result, &size);\n assert(issame(result, size, expected3, 4));\n\n int expected4[] = {}; // Empty set\n func0(17, 89, result, &size);\n assert(issame(result, size, expected4, 0));\n\n printf(\"All tests passed.\\n\");\n\n return 0;\n}", + "opt": "O2", + "language": "c", + "asm": "", + "ida_asm": "func0:\nendbr64\nmov dword ptr [rcx], 0\ncmp esi, edi\njl short loc_13B4\nmov eax, esi\nmov esi, edi\nmov edi, eax\nloc_13B4:\nadd edi, 1\nnop word ptr [rax+rax+00000000h]\nloc_13C0:\ncmp esi, 9\njg short loc_13D8\ntest sil, 1\njnz short loc_13D8\nmovsxd rax, dword ptr [rcx]\nlea r8d, [rax+1]\nmov [rcx], r8d\nmov [rdx+rax*4], esi\nloc_13D8:\nadd esi, 1\ncmp esi, edi\njnz short loc_13C0\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, __int64 a3, int *a4)\n{\n __int64 result; // rax\n int v5; // edi\n\n *a4 = 0;\n if ( a2 >= a1 )\n {\n result = (unsigned int)a2;\n a2 = a1;\n a1 = result;\n }\n v5 = a1 + 1;\n do\n {\n if ( a2 <= 9 && (a2 & 1) == 0 )\n {\n result = *a4;\n *a4 = result + 1;\n *(_DWORD *)(a3 + 4 * result) = a2;\n }\n ++a2;\n }\n while ( a2 != v5 );\n return result;\n}", + "ida_strip_asm": "sub_13A0:\nendbr64\nmov dword ptr [rcx], 0\ncmp esi, edi\njl short loc_13B4\nmov eax, esi\nmov esi, edi\nmov edi, eax\nloc_13B4:\nadd edi, 1\nnop word ptr [rax+rax+00000000h]\nloc_13C0:\ncmp esi, 9\njg short loc_13D8\ntest sil, 1\njnz short loc_13D8\nmovsxd rax, dword ptr [rcx]\nlea r8d, [rax+1]\nmov [rcx], r8d\nmov [rdx+rax*4], esi\nloc_13D8:\nadd esi, 1\ncmp esi, edi\njnz short loc_13C0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_13A0(int a1, int a2, __int64 a3, int *a4)\n{\n __int64 result; // rax\n int v5; // edi\n\n *a4 = 0;\n if ( a2 >= a1 )\n {\n result = (unsigned int)a2;\n a2 = a1;\n a1 = result;\n }\n v5 = a1 + 1;\n do\n {\n if ( a2 <= 9 && (a2 & 1) == 0 )\n {\n result = *a4;\n *a4 = result + 1;\n *(_DWORD *)(a3 + 4 * result) = a2;\n }\n ++a2;\n }\n while ( a2 != v5 );\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_13A0(int a1, int a2, long long a3, int *a4) {\n long long result;\n int v5;\n *a4 = 0;\n if (a2 >= a1) {\n result = (unsigned int)a2;\n a2 = a1;\n a1 = result;\n }\n v5 = a1 + 1;\n do {\n if (a2 <= 9 && (a2 & 1) == 0) {\n result = *a4;\n *a4 = result + 1;\n *(uint32_t *)(a3 + 4 * result) = a2;\n }\n ++a2;\n } while (a2 != v5);\n return result;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, long long a3, int *a4) {\n long long result;\n int v5;\n *a4 = 0;\n if (a2 >= a1) {\n result = (unsigned int)a2;\n a2 = a1;\n a1 = result;\n }\n v5 = a1 + 1;\n do {\n if (a2 <= 9 && (a2 & 1) == 0) {\n result = *a4;\n *a4 = result + 1;\n *(uint32_t *)(a3 + 4 * result) = a2;\n }\n ++a2;\n } while (a2 != v5);\n return result;\n}" + } +] \ No newline at end of file diff --git a/sk2decompile/evaluation/data/mbpp_normsrcpseudo.json b/sk2decompile/evaluation/data/mbpp_normsrcpseudo.json new file mode 100644 index 0000000..6395cc4 --- /dev/null +++ b/sk2decompile/evaluation/data/mbpp_normsrcpseudo.json @@ -0,0 +1,51138 @@ +[ + { + "index": 1, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n#define R 3\n\n#define C 3\n\n\n\n", + "func": "int func0(int cost[R][C], int m, int n) {\n int tc[R][C];\n tc[0][0] = cost[0][0];\n for (int i = 1; i <= m; ++i) {\n tc[i][0] = tc[i - 1][0] + cost[i][0];\n }\n for (int j = 1; j <= n; ++j) {\n tc[0][j] = tc[0][j - 1] + cost[0][j];\n }\n for (int i = 1; i <= m; ++i) {\n for (int j = 1; j <= n; ++j) {\n int min_val = tc[i - 1][j - 1];\n if (tc[i - 1][j] < min_val) min_val = tc[i - 1][j];\n if (tc[i][j - 1] < min_val) min_val = tc[i][j - 1];\n tc[i][j] = min_val + cost[i][j];\n }\n }\n return tc[m][n];\n}", + "test": "int main() {\n\n int cost1[R][C] = {{1, 2, 3}, {4, 8, 2}, {1, 5, 3}};\n\n int cost2[R][C] = {{2, 3, 4}, {5, 9, 3}, {2, 6, 4}};\n\n int cost3[R][C] = {{3, 4, 5}, {6, 10, 4}, {3, 7, 5}};\n\n\n\n assert(func0(cost1, 2, 2) == 8);\n\n assert(func0(cost2, 2, 2) == 12);\n\n assert(func0(cost3, 2, 2) == 16);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x60,%rsp\nmov %rdi,-0x58(%rbp)\nmov %esi,-0x5c(%rbp)\nmov %edx,-0x60(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmov -0x58(%rbp),%rax\nmov (%rax),%eax\nmov %eax,-0x30(%rbp)\nmovl $0x1,-0x44(%rbp)\njmp 1200 \nmov -0x44(%rbp),%eax\nsub $0x1,%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rbp,%rax\nsub $0x30,%rax\nmov (%rax),%ecx\nmov -0x44(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x58(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nadd %eax,%ecx\nmov -0x44(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rbp,%rax\nsub $0x30,%rax\nmov %ecx,(%rax)\naddl $0x1,-0x44(%rbp)\nmov -0x44(%rbp),%eax\ncmp -0x5c(%rbp),%eax\njle 11a0 \nmovl $0x1,-0x40(%rbp)\njmp 123a \nmov -0x40(%rbp),%eax\nsub $0x1,%eax\ncltq\nmov -0x30(%rbp,%rax,4),%ecx\nmov -0x58(%rbp),%rax\nmov -0x40(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nlea (%rcx,%rax,1),%edx\nmov -0x40(%rbp),%eax\ncltq\nmov %edx,-0x30(%rbp,%rax,4)\naddl $0x1,-0x40(%rbp)\nmov -0x40(%rbp),%eax\ncmp -0x60(%rbp),%eax\njle 1211 \nmovl $0x1,-0x3c(%rbp)\njmpq 1366 \nmovl $0x1,-0x38(%rbp)\njmpq 1356 \nmov -0x3c(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x38(%rbp),%eax\nsub $0x1,%eax\nmovslq %eax,%rcx\nmovslq %edx,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nadd %rcx,%rax\nmov -0x30(%rbp,%rax,4),%eax\nmov %eax,-0x34(%rbp)\nmov -0x3c(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x38(%rbp),%eax\nmovslq %eax,%rcx\nmovslq %edx,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nadd %rcx,%rax\nmov -0x30(%rbp,%rax,4),%eax\ncmp %eax,-0x34(%rbp)\njle 12c5 \nmov -0x3c(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x38(%rbp),%eax\nmovslq %eax,%rcx\nmovslq %edx,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nadd %rcx,%rax\nmov -0x30(%rbp,%rax,4),%eax\nmov %eax,-0x34(%rbp)\nmov -0x38(%rbp),%eax\nsub $0x1,%eax\nmovslq %eax,%rcx\nmov -0x3c(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nadd %rcx,%rax\nmov -0x30(%rbp,%rax,4),%eax\ncmp %eax,-0x34(%rbp)\njle 130b \nmov -0x38(%rbp),%eax\nsub $0x1,%eax\nmovslq %eax,%rcx\nmov -0x3c(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nadd %rcx,%rax\nmov -0x30(%rbp,%rax,4),%eax\nmov %eax,-0x34(%rbp)\nmov -0x3c(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x58(%rbp),%rax\nadd %rax,%rdx\nmov -0x38(%rbp),%eax\ncltq\nmov (%rdx,%rax,4),%edx\nmov -0x34(%rbp),%eax\nlea (%rdx,%rax,1),%ecx\nmov -0x38(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x3c(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nadd %rsi,%rax\nmov %ecx,-0x30(%rbp,%rax,4)\naddl $0x1,-0x38(%rbp)\nmov -0x38(%rbp),%eax\ncmp -0x60(%rbp),%eax\njle 125a \naddl $0x1,-0x3c(%rbp)\nmov -0x3c(%rbp),%eax\ncmp -0x5c(%rbp),%eax\njle 124e \nmov -0x60(%rbp),%eax\nmovslq %eax,%rcx\nmov -0x5c(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nadd %rcx,%rax\nmov -0x30(%rbp,%rax,4),%eax\nmov -0x8(%rbp),%rdi\nxor %fs:0x28,%rdi\nje 13a2 \ncallq 1060 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 60h\nmov [rbp+var_58], rdi\nmov [rbp+var_5C], esi\nmov [rbp+var_60], edx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, [rbp+var_58]\nmov eax, [rax]\nmov [rbp+var_30], eax\nmov [rbp+var_44], 1\njmp short loc_1200\nloc_11A0:\nmov eax, [rbp+var_44]\nsub eax, 1\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rbp\nsub rax, 30h ; '0'\nmov ecx, [rax]\nmov eax, [rbp+var_44]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov eax, [rax]\nadd ecx, eax\nmov eax, [rbp+var_44]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rbp\nsub rax, 30h ; '0'\nmov [rax], ecx\nadd [rbp+var_44], 1\nloc_1200:\nmov eax, [rbp+var_44]\ncmp eax, [rbp+var_5C]\njle short loc_11A0\nmov [rbp+var_40], 1\njmp short loc_123A\nloc_1211:\nmov eax, [rbp+var_40]\nsub eax, 1\ncdqe\nmov ecx, [rbp+rax*4+var_30]\nmov rax, [rbp+var_58]\nmov edx, [rbp+var_40]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nlea edx, [rcx+rax]\nmov eax, [rbp+var_40]\ncdqe\nmov [rbp+rax*4+var_30], edx\nadd [rbp+var_40], 1\nloc_123A:\nmov eax, [rbp+var_40]\ncmp eax, [rbp+var_60]\njle short loc_1211\nmov [rbp+var_3C], 1\njmp loc_1366\nloc_124E:\nmov [rbp+var_38], 1\njmp loc_1356\nloc_125A:\nmov eax, [rbp+var_3C]\nlea edx, [rax-1]\nmov eax, [rbp+var_38]\nsub eax, 1\nmovsxd rcx, eax\nmovsxd rdx, edx\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nadd rax, rcx\nmov eax, [rbp+rax*4+var_30]\nmov [rbp+var_34], eax\nmov eax, [rbp+var_3C]\nlea edx, [rax-1]\nmov eax, [rbp+var_38]\nmovsxd rcx, eax\nmovsxd rdx, edx\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nadd rax, rcx\nmov eax, [rbp+rax*4+var_30]\ncmp [rbp+var_34], eax\njle short loc_12C5\nmov eax, [rbp+var_3C]\nlea edx, [rax-1]\nmov eax, [rbp+var_38]\nmovsxd rcx, eax\nmovsxd rdx, edx\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nadd rax, rcx\nmov eax, [rbp+rax*4+var_30]\nmov [rbp+var_34], eax\nloc_12C5:\nmov eax, [rbp+var_38]\nsub eax, 1\nmovsxd rcx, eax\nmov eax, [rbp+var_3C]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nadd rax, rcx\nmov eax, [rbp+rax*4+var_30]\ncmp [rbp+var_34], eax\njle short loc_130B\nmov eax, [rbp+var_38]\nsub eax, 1\nmovsxd rcx, eax\nmov eax, [rbp+var_3C]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nadd rax, rcx\nmov eax, [rbp+rax*4+var_30]\nmov [rbp+var_34], eax\nloc_130B:\nmov eax, [rbp+var_3C]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_58]\nadd rdx, rax\nmov eax, [rbp+var_38]\ncdqe\nmov edx, [rdx+rax*4]\nmov eax, [rbp+var_34]\nlea ecx, [rdx+rax]\nmov eax, [rbp+var_38]\nmovsxd rsi, eax\nmov eax, [rbp+var_3C]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nadd rax, rsi\nmov [rbp+rax*4+var_30], ecx\nadd [rbp+var_38], 1\nloc_1356:\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_60]\njle loc_125A\nadd [rbp+var_3C], 1\nloc_1366:\nmov eax, [rbp+var_3C]\ncmp eax, [rbp+var_5C]\njle loc_124E\nmov eax, [rbp+var_60]\nmovsxd rcx, eax\nmov eax, [rbp+var_5C]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nadd rax, rcx\nmov eax, [rbp+rax*4+var_30]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_13A2\ncall ___stack_chk_fail\nlocret_13A2:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2, int a3)\n{\n int i; // [rsp+1Ch] [rbp-44h]\n int j; // [rsp+20h] [rbp-40h]\n int k; // [rsp+24h] [rbp-3Ch]\n int m; // [rsp+28h] [rbp-38h]\n int v8; // [rsp+2Ch] [rbp-34h]\n _DWORD v9[10]; // [rsp+30h] [rbp-30h]\n unsigned __int64 v10; // [rsp+58h] [rbp-8h]\n\n v10 = __readfsqword(0x28u);\n v9[0] = *a1;\n for ( i = 1; i <= a2; ++i )\n v9[3 * i] = a1[3 * i] + v9[3 * i - 3];\n for ( j = 1; j <= a3; ++j )\n v9[j] = v9[j - 1] + a1[j];\n for ( k = 1; k <= a2; ++k )\n {\n for ( m = 1; m <= a3; ++m )\n {\n v8 = v9[3 * k - 4 + m];\n if ( v8 > v9[3 * k - 3 + m] )\n v8 = v9[3 * k - 3 + m];\n if ( v8 > v9[3 * k - 1 + m] )\n v8 = v9[3 * k - 1 + m];\n v9[3 * k + m] = a1[3 * k + m] + v8;\n }\n }\n return (unsigned int)v9[3 * a2 + a3];\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 60h\nmov [rbp+var_58], rdi\nmov [rbp+var_5C], esi\nmov [rbp+var_60], edx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, [rbp+var_58]\nmov eax, [rax]\nmov [rbp+var_30], eax\nmov [rbp+var_44], 1\njmp short loc_1200\nloc_11A0:\nmov eax, [rbp+var_44]\nsub eax, 1\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rbp\nsub rax, 30h ; '0'\nmov ecx, [rax]\nmov eax, [rbp+var_44]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov eax, [rax]\nadd ecx, eax\nmov eax, [rbp+var_44]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rbp\nsub rax, 30h ; '0'\nmov [rax], ecx\nadd [rbp+var_44], 1\nloc_1200:\nmov eax, [rbp+var_44]\ncmp eax, [rbp+var_5C]\njle short loc_11A0\nmov [rbp+var_40], 1\njmp short loc_123A\nloc_1211:\nmov eax, [rbp+var_40]\nsub eax, 1\ncdqe\nmov ecx, [rbp+rax*4+var_30]\nmov rax, [rbp+var_58]\nmov edx, [rbp+var_40]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nlea edx, [rcx+rax]\nmov eax, [rbp+var_40]\ncdqe\nmov [rbp+rax*4+var_30], edx\nadd [rbp+var_40], 1\nloc_123A:\nmov eax, [rbp+var_40]\ncmp eax, [rbp+var_60]\njle short loc_1211\nmov [rbp+var_3C], 1\njmp loc_1366\nloc_124E:\nmov [rbp+var_38], 1\njmp loc_1356\nloc_125A:\nmov eax, [rbp+var_3C]\nlea edx, [rax-1]\nmov eax, [rbp+var_38]\nsub eax, 1\nmovsxd rcx, eax\nmovsxd rdx, edx\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nadd rax, rcx\nmov eax, [rbp+rax*4+var_30]\nmov [rbp+var_34], eax\nmov eax, [rbp+var_3C]\nlea edx, [rax-1]\nmov eax, [rbp+var_38]\nmovsxd rcx, eax\nmovsxd rdx, edx\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nadd rax, rcx\nmov eax, [rbp+rax*4+var_30]\ncmp [rbp+var_34], eax\njle short loc_12C5\nmov eax, [rbp+var_3C]\nlea edx, [rax-1]\nmov eax, [rbp+var_38]\nmovsxd rcx, eax\nmovsxd rdx, edx\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nadd rax, rcx\nmov eax, [rbp+rax*4+var_30]\nmov [rbp+var_34], eax\nloc_12C5:\nmov eax, [rbp+var_38]\nsub eax, 1\nmovsxd rcx, eax\nmov eax, [rbp+var_3C]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nadd rax, rcx\nmov eax, [rbp+rax*4+var_30]\ncmp [rbp+var_34], eax\njle short loc_130B\nmov eax, [rbp+var_38]\nsub eax, 1\nmovsxd rcx, eax\nmov eax, [rbp+var_3C]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nadd rax, rcx\nmov eax, [rbp+rax*4+var_30]\nmov [rbp+var_34], eax\nloc_130B:\nmov eax, [rbp+var_3C]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_58]\nadd rdx, rax\nmov eax, [rbp+var_38]\ncdqe\nmov edx, [rdx+rax*4]\nmov eax, [rbp+var_34]\nlea ecx, [rdx+rax]\nmov eax, [rbp+var_38]\nmovsxd rsi, eax\nmov eax, [rbp+var_3C]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nadd rax, rsi\nmov [rbp+rax*4+var_30], ecx\nadd [rbp+var_38], 1\nloc_1356:\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_60]\njle loc_125A\nadd [rbp+var_3C], 1\nloc_1366:\nmov eax, [rbp+var_3C]\ncmp eax, [rbp+var_5C]\njle loc_124E\nmov eax, [rbp+var_60]\nmovsxd rcx, eax\nmov eax, [rbp+var_5C]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nadd rax, rcx\nmov eax, [rbp+rax*4+var_30]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_13A2\ncall ___stack_chk_fail\nlocret_13A2:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2, int a3)\n{\n int i; // [rsp+1Ch] [rbp-44h]\n int j; // [rsp+20h] [rbp-40h]\n int k; // [rsp+24h] [rbp-3Ch]\n int m; // [rsp+28h] [rbp-38h]\n int v8; // [rsp+2Ch] [rbp-34h]\n _DWORD v9[10]; // [rsp+30h] [rbp-30h]\n unsigned __int64 v10; // [rsp+58h] [rbp-8h]\n\n v10 = __readfsqword(0x28u);\n v9[0] = *a1;\n for ( i = 1; i <= a2; ++i )\n v9[3 * i] = a1[3 * i] + v9[3 * i - 3];\n for ( j = 1; j <= a3; ++j )\n v9[j] = v9[j - 1] + a1[j];\n for ( k = 1; k <= a2; ++k )\n {\n for ( m = 1; m <= a3; ++m )\n {\n v8 = v9[3 * k - 4 + m];\n if ( v8 > v9[3 * k - 3 + m] )\n v8 = v9[3 * k - 3 + m];\n if ( v8 > v9[3 * k - 1 + m] )\n v8 = v9[3 * k - 1 + m];\n v9[3 * k + m] = a1[3 * k + m] + v8;\n }\n }\n return (unsigned int)v9[3 * a2 + a3];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2, int a3) {\n int i;\n int j;\n int k;\n int m;\n int v8;\n uint32_t v9[10];\n unsigned long long v10;\n v10 = __readfsqword(40u);\n v9[0] = *a1;\n for (i = 1; i <= a2; ++i) v9[3 * i] = a1[3 * i] + v9[3 * i - 3];\n for (j = 1; j <= a3; ++j) v9[j] = v9[j - 1] + a1[j];\n for (k = 1; k <= a2; ++k) {\n for (m = 1; m <= a3; ++m) {\n v8 = v9[3 * k - 4 + m];\n if (v8 > v9[3 * k - 3 + m]) v8 = v9[3 * k - 3 + m];\n if (v8 > v9[3 * k - 1 + m]) v8 = v9[3 * k - 1 + m];\n v9[3 * k + m] = a1[3 * k + m] + v8;\n }\n }\n return (unsigned int)v9[3 * a2 + a3];\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2, int a3) {\n int i;\n int j;\n int k;\n int m;\n int v8;\n uint32_t v9[10];\n unsigned long long v10;\n v10 = __readfsqword(40u);\n v9[0] = *a1;\n for (i = 1; i <= a2; ++i) v9[3 * i] = a1[3 * i] + v9[3 * i - 3];\n for (j = 1; j <= a3; ++j) v9[j] = v9[j - 1] + a1[j];\n for (k = 1; k <= a2; ++k) {\n for (m = 1; m <= a3; ++m) {\n v8 = v9[3 * k - 4 + m];\n if (v8 > v9[3 * k - 3 + m]) v8 = v9[3 * k - 3 + m];\n if (v8 > v9[3 * k - 1 + m]) v8 = v9[3 * k - 1 + m];\n v9[3 * k + m] = a1[3 * k + m] + v8;\n }\n }\n return (unsigned int)v9[3 * a2 + a3];\n}" + }, + { + "index": 1, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n#define R 3\n\n#define C 3\n\n\n\n", + "func": "int func0(int cost[R][C], int m, int n) {\n int tc[R][C];\n tc[0][0] = cost[0][0];\n for (int i = 1; i <= m; ++i) {\n tc[i][0] = tc[i - 1][0] + cost[i][0];\n }\n for (int j = 1; j <= n; ++j) {\n tc[0][j] = tc[0][j - 1] + cost[0][j];\n }\n for (int i = 1; i <= m; ++i) {\n for (int j = 1; j <= n; ++j) {\n int min_val = tc[i - 1][j - 1];\n if (tc[i - 1][j] < min_val) min_val = tc[i - 1][j];\n if (tc[i][j - 1] < min_val) min_val = tc[i][j - 1];\n tc[i][j] = min_val + cost[i][j];\n }\n }\n return tc[m][n];\n}", + "test": "int main() {\n\n int cost1[R][C] = {{1, 2, 3}, {4, 8, 2}, {1, 5, 3}};\n\n int cost2[R][C] = {{2, 3, 4}, {5, 9, 3}, {2, 6, 4}};\n\n int cost3[R][C] = {{3, 4, 5}, {6, 10, 4}, {3, 7, 5}};\n\n\n\n assert(func0(cost1, 2, 2) == 8);\n\n assert(func0(cost2, 2, 2) == 12);\n\n assert(func0(cost3, 2, 2) == 16);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x38,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x28(%rsp)\nxor %eax,%eax\nmov (%rdi),%eax\nmov %eax,(%rsp)\ntest %esi,%esi\njle 1219 \nmov %eax,%ecx\nadd 0xc(%rdi),%ecx\nmov %ecx,0xc(%rsp)\ncmp $0x1,%esi\njle 11a3 \nadd 0x18(%rdi),%ecx\nmov %ecx,0x18(%rsp)\ntest %edx,%edx\njle 11be \nadd 0x4(%rdi),%eax\nmov %eax,0x4(%rsp)\ncmp $0x1,%edx\njle 11ba \nadd 0x8(%rdi),%eax\nmov %eax,0x8(%rsp)\ntest %esi,%esi\njle 121d \nmov %rsp,%rax\nadd $0x10,%rdi\nmov $0x1,%r9d\njmp 11de \nadd $0x1,%r9d\nadd $0xc,%rax\nadd $0xc,%rdi\ncmp %r9d,%esi\njl 121d \ntest %edx,%edx\njle 11cd \nmov 0x4(%rax),%ecx\ncmp %ecx,(%rax)\nmov %ecx,%r8d\ncmovle (%rax),%r8d\ncmp %r8d,0xc(%rax)\ncmovle 0xc(%rax),%r8d\nadd (%rdi),%r8d\nmov %r8d,0x10(%rax)\ncmp $0x1,%edx\njle 11cd \ncmp %ecx,0x8(%rax)\ncmovle 0x8(%rax),%ecx\ncmp %r8d,%ecx\ncmovg %r8d,%ecx\nadd 0x4(%rdi),%ecx\nmov %ecx,0x14(%rax)\njmp 11cd \ntest %edx,%edx\njg 11a7 \nmovslq %edx,%rdx\nmovslq %esi,%rsi\nlea (%rsi,%rsi,2),%rax\nadd %rax,%rdx\nmov (%rsp,%rdx,4),%eax\nmov 0x28(%rsp),%rsi\nxor %fs:0x28,%rsi\njne 1242 \nadd $0x38,%rsp\nretq\ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 38h\nmov r8d, edx\nmov rax, fs:28h\nmov [rsp+38h+var_10], rax\nxor eax, eax\nmov eax, [rdi]\nmov [rsp+38h+var_38], eax\ntest esi, esi\njle loc_1220\nmov edx, eax\nadd edx, [rdi+0Ch]\nmov [rsp+38h+var_2C], edx\ncmp esi, 1\njle short loc_11A6\nadd edx, [rdi+18h]\nmov [rsp+38h+var_20], edx\nloc_11A6:\ntest r8d, r8d\njle short loc_11C3\nloc_11AB:\nadd eax, [rdi+4]\nmov [rsp+38h+var_34], eax\ncmp r8d, 1\njle short loc_11BF\nadd eax, [rdi+8]\nmov [rsp+38h+var_30], eax\nloc_11BF:\ntest esi, esi\njle short loc_1224\nloc_11C3:\nmov rcx, rsp\nadd rdi, 10h\nmov r9d, 1\njmp short loc_11E3\nloc_11D2:\nadd r9d, 1\nadd rcx, 0Ch\nadd rdi, 0Ch\ncmp esi, r9d\njl short loc_1224\nloc_11E3:\ntest r8d, r8d\njle short loc_11D2\nmov edx, [rcx+4]\nmov eax, [rcx]\ncmp edx, eax\ncmovle eax, edx\nmov r10d, [rcx+0Ch]\ncmp eax, r10d\ncmovg eax, r10d\nadd eax, [rdi]\nmov [rcx+10h], eax\ncmp r8d, 1\njle short loc_11D2\nmov r10d, [rcx+8]\ncmp edx, r10d\ncmovg edx, r10d\ncmp edx, eax\ncmovg edx, eax\nadd edx, [rdi+4]\nmov [rcx+14h], edx\njmp short loc_11D2\nloc_1220:\ntest edx, edx\njg short loc_11AB\nloc_1224:\nmovsxd r8, r8d\nmovsxd rsi, esi\nlea rax, [rsi+rsi*2]\nadd rax, r8\nmov eax, [rsp+rax*4+38h+var_38]\nmov rdx, [rsp+38h+var_10]\nsub rdx, fs:28h\njnz short loc_1249\nadd rsp, 38h\nretn\nloc_1249:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2, int a3)\n{\n int v4; // eax\n int v5; // edx\n int v6; // eax\n int *v7; // rcx\n _DWORD *v8; // rdi\n int i; // r9d\n int v10; // edx\n int v11; // eax\n int v12; // eax\n _DWORD v14[10]; // [rsp+0h] [rbp-38h] BYREF\n unsigned __int64 v15; // [rsp+28h] [rbp-10h]\n\n v15 = __readfsqword(0x28u);\n v4 = *a1;\n v14[0] = *a1;\n if ( a2 <= 0 )\n {\n if ( a3 <= 0 )\n return (unsigned int)v14[3 * a2 + a3];\n }\n else\n {\n v5 = a1[3] + v4;\n v14[3] = v5;\n if ( a2 > 1 )\n v14[6] = a1[6] + v5;\n if ( a3 <= 0 )\n goto LABEL_8;\n }\n v6 = a1[1] + v4;\n v14[1] = v6;\n if ( a3 > 1 )\n v14[2] = a1[2] + v6;\n if ( a2 > 0 )\n {\nLABEL_8:\n v7 = v14;\n v8 = a1 + 4;\n for ( i = 1; i <= a2; ++i )\n {\n if ( a3 > 0 )\n {\n v10 = v7[1];\n v11 = *v7;\n if ( v10 <= *v7 )\n v11 = v7[1];\n if ( v11 > v7[3] )\n v11 = v7[3];\n v12 = *v8 + v11;\n v7[4] = v12;\n if ( a3 > 1 )\n {\n if ( v10 > v7[2] )\n v10 = v7[2];\n if ( v10 > v12 )\n v10 = v12;\n v7[5] = v8[1] + v10;\n }\n }\n v7 += 3;\n v8 += 3;\n }\n }\n return (unsigned int)v14[3 * a2 + a3];\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nsub rsp, 38h\nmov r8d, edx\nmov rax, fs:28h\nmov [rsp+38h+var_10], rax\nxor eax, eax\nmov eax, [rdi]\nmov [rsp+38h+var_38], eax\ntest esi, esi\njle loc_1220\nmov edx, eax\nadd edx, [rdi+0Ch]\nmov [rsp+38h+var_2C], edx\ncmp esi, 1\njle short loc_11A6\nadd edx, [rdi+18h]\nmov [rsp+38h+var_20], edx\nloc_11A6:\ntest r8d, r8d\njle short loc_11C3\nloc_11AB:\nadd eax, [rdi+4]\nmov [rsp+38h+var_34], eax\ncmp r8d, 1\njle short loc_11BF\nadd eax, [rdi+8]\nmov [rsp+38h+var_30], eax\nloc_11BF:\ntest esi, esi\njle short loc_1224\nloc_11C3:\nmov rcx, rsp\nadd rdi, 10h\nmov r9d, 1\njmp short loc_11E3\nloc_11D2:\nadd r9d, 1\nadd rcx, 0Ch\nadd rdi, 0Ch\ncmp esi, r9d\njl short loc_1224\nloc_11E3:\ntest r8d, r8d\njle short loc_11D2\nmov edx, [rcx+4]\nmov eax, [rcx]\ncmp edx, eax\ncmovle eax, edx\nmov r10d, [rcx+0Ch]\ncmp eax, r10d\ncmovg eax, r10d\nadd eax, [rdi]\nmov [rcx+10h], eax\ncmp r8d, 1\njle short loc_11D2\nmov r10d, [rcx+8]\ncmp edx, r10d\ncmovg edx, r10d\ncmp edx, eax\ncmovg edx, eax\nadd edx, [rdi+4]\nmov [rcx+14h], edx\njmp short loc_11D2\nloc_1220:\ntest edx, edx\njg short loc_11AB\nloc_1224:\nmovsxd r8, r8d\nmovsxd rsi, esi\nlea rax, [rsi+rsi*2]\nadd rax, r8\nmov eax, [rsp+rax*4+38h+var_38]\nmov rdx, [rsp+38h+var_10]\nsub rdx, fs:28h\njnz short loc_1249\nadd rsp, 38h\nretn\nloc_1249:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int *a1, int a2, int a3)\n{\n int v4; // eax\n int v5; // edx\n int v6; // eax\n int *v7; // rcx\n _DWORD *v8; // rdi\n int i; // r9d\n int v10; // edx\n int v11; // eax\n int v12; // eax\n _DWORD v14[10]; // [rsp+0h] [rbp-38h] BYREF\n unsigned __int64 v15; // [rsp+28h] [rbp-10h]\n\n v15 = __readfsqword(0x28u);\n v4 = *a1;\n v14[0] = *a1;\n if ( a2 <= 0 )\n {\n if ( a3 <= 0 )\n return (unsigned int)v14[3 * a2 + a3];\n }\n else\n {\n v5 = a1[3] + v4;\n v14[3] = v5;\n if ( a2 > 1 )\n v14[6] = a1[6] + v5;\n if ( a3 <= 0 )\n goto LABEL_8;\n }\n v6 = a1[1] + v4;\n v14[1] = v6;\n if ( a3 > 1 )\n v14[2] = a1[2] + v6;\n if ( a2 > 0 )\n {\nLABEL_8:\n v7 = v14;\n v8 = a1 + 4;\n for ( i = 1; i <= a2; ++i )\n {\n if ( a3 > 0 )\n {\n v10 = v7[1];\n v11 = *v7;\n if ( v10 <= *v7 )\n v11 = v7[1];\n if ( v11 > v7[3] )\n v11 = v7[3];\n v12 = *v8 + v11;\n v7[4] = v12;\n if ( a3 > 1 )\n {\n if ( v10 > v7[2] )\n v10 = v7[2];\n if ( v10 > v12 )\n v10 = v12;\n v7[5] = v8[1] + v10;\n }\n }\n v7 += 3;\n v8 += 3;\n }\n }\n return (unsigned int)v14[3 * a2 + a3];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int *a1, int a2, int a3) {\n int v4;\n int v5;\n int v6;\n int *v7;\n uint32_t *v8;\n int i;\n int v10;\n int v11;\n int v12;\n uint32_t v14[10];\n unsigned long long v15;\n v15 = __readfsqword(40u);\n v4 = *a1;\n v14[0] = *a1;\n if (a2 <= 0) {\n if (a3 <= 0) return (unsigned int)v14[3 * a2 + a3];\n } else {\n v5 = a1[3] + v4;\n v14[3] = v5;\n if (a2 > 1) v14[6] = a1[6] + v5;\n if (a3 <= 0) goto LABEL_8;\n }\n v6 = a1[1] + v4;\n v14[1] = v6;\n if (a3 > 1) v14[2] = a1[2] + v6;\n if (a2 > 0) {\n LABEL_8:\n v7 = v14;\n v8 = a1 + 4;\n for (i = 1; i <= a2; ++i) {\n if (a3 > 0) {\n v10 = v7[1];\n v11 = *v7;\n if (v10 <= *v7) v11 = v7[1];\n if (v11 > v7[3]) v11 = v7[3];\n v12 = *v8 + v11;\n v7[4] = v12;\n if (a3 > 1) {\n if (v10 > v7[2]) v10 = v7[2];\n if (v10 > v12) v10 = v12;\n v7[5] = v8[1] + v10;\n }\n }\n v7 += 3;\n v8 += 3;\n }\n }\n return (unsigned int)v14[3 * a2 + a3];\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2, int a3) {\n int v4;\n int v5;\n int v6;\n int *v7;\n uint32_t *v8;\n int i;\n int v10;\n int v11;\n int v12;\n uint32_t v14[10];\n unsigned long long v15;\n v15 = __readfsqword(40u);\n v4 = *a1;\n v14[0] = *a1;\n if (a2 <= 0) {\n if (a3 <= 0) return (unsigned int)v14[3 * a2 + a3];\n } else {\n v5 = a1[3] + v4;\n v14[3] = v5;\n if (a2 > 1) v14[6] = a1[6] + v5;\n if (a3 <= 0) goto LABEL_8;\n }\n v6 = a1[1] + v4;\n v14[1] = v6;\n if (a3 > 1) v14[2] = a1[2] + v6;\n if (a2 > 0) {\n LABEL_8:\n v7 = v14;\n v8 = a1 + 4;\n for (i = 1; i <= a2; ++i) {\n if (a3 > 0) {\n v10 = v7[1];\n v11 = *v7;\n if (v10 <= *v7) v11 = v7[1];\n if (v11 > v7[3]) v11 = v7[3];\n v12 = *v8 + v11;\n v7[4] = v12;\n if (a3 > 1) {\n if (v10 > v7[2]) v10 = v7[2];\n if (v10 > v12) v10 = v12;\n v7[5] = v8[1] + v10;\n }\n }\n v7 += 3;\n v8 += 3;\n }\n }\n return (unsigned int)v14[3 * a2 + a3];\n}" + }, + { + "index": 1, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n#define R 3\n\n#define C 3\n\n\n\n", + "func": "int func0(int cost[R][C], int m, int n) {\n int tc[R][C];\n tc[0][0] = cost[0][0];\n for (int i = 1; i <= m; ++i) {\n tc[i][0] = tc[i - 1][0] + cost[i][0];\n }\n for (int j = 1; j <= n; ++j) {\n tc[0][j] = tc[0][j - 1] + cost[0][j];\n }\n for (int i = 1; i <= m; ++i) {\n for (int j = 1; j <= n; ++j) {\n int min_val = tc[i - 1][j - 1];\n if (tc[i - 1][j] < min_val) min_val = tc[i - 1][j];\n if (tc[i][j - 1] < min_val) min_val = tc[i][j - 1];\n tc[i][j] = min_val + cost[i][j];\n }\n }\n return tc[m][n];\n}", + "test": "int main() {\n\n int cost1[R][C] = {{1, 2, 3}, {4, 8, 2}, {1, 5, 3}};\n\n int cost2[R][C] = {{2, 3, 4}, {5, 9, 3}, {2, 6, 4}};\n\n int cost3[R][C] = {{3, 4, 5}, {6, 10, 4}, {3, 7, 5}};\n\n\n\n assert(func0(cost1, 2, 2) == 8);\n\n assert(func0(cost2, 2, 2) == 12);\n\n assert(func0(cost3, 2, 2) == 16);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x38,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x28(%rsp)\nxor %eax,%eax\nmov (%rdi),%eax\nmov %eax,(%rsp)\ntest %esi,%esi\njle 1356 \nmov 0xc(%rdi),%ecx\nadd %eax,%ecx\nmov %ecx,0xc(%rsp)\ncmp $0x1,%esi\nje 1356 \nadd 0x18(%rdi),%ecx\nmov %ecx,0x18(%rsp)\ntest %edx,%edx\njle 136d \nadd 0x4(%rdi),%eax\nmov %eax,0x4(%rsp)\ncmp $0x1,%edx\nje 136d \nadd 0x8(%rdi),%eax\nmov %eax,0x8(%rsp)\ntest %esi,%esi\njle 13c8 \nmov %rsp,%rax\nadd $0x10,%rdi\nmov $0x1,%r9d\ntest %edx,%edx\njle 13b7 \nmov 0x4(%rax),%ecx\ncmp %ecx,(%rax)\nmov %ecx,%r8d\ncmovle (%rax),%r8d\ncmp %r8d,0xc(%rax)\ncmovle 0xc(%rax),%r8d\nadd (%rdi),%r8d\nmov %r8d,0x10(%rax)\ncmp $0x1,%edx\nje 13b7 \ncmp %ecx,0x8(%rax)\ncmovle 0x8(%rax),%ecx\ncmp %r8d,%ecx\ncmovg %r8d,%ecx\nadd 0x4(%rdi),%ecx\nmov %ecx,0x14(%rax)\nadd $0x1,%r9d\nadd $0xc,%rax\nadd $0xc,%rdi\ncmp %r9d,%esi\njge 137e \nmovslq %esi,%rsi\nmovslq %edx,%rdx\nlea (%rsi,%rsi,2),%rax\nadd %rax,%rdx\nmov 0x28(%rsp),%rsi\nxor %fs:0x28,%rsi\nmov (%rsp,%rdx,4),%eax\njne 13ed \nadd $0x38,%rsp\nretq\ncallq 1060 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 38h\nmovsxd rcx, edx\nmov rax, fs:28h\nmov [rsp+38h+var_10], rax\nmov eax, [rdi]\nmov [rsp+38h+var_38], eax\ntest esi, esi\njle loc_1398\nmov edx, [rdi+0Ch]\nadd edx, eax\nmov [rsp+38h+var_2C], edx\ncmp esi, 1\njz short loc_12FB\nadd edx, [rdi+18h]\nmov [rsp+38h+var_20], edx\nloc_12FB:\ntest ecx, ecx\njle short loc_1312\nadd eax, [rdi+4]\nmov [rsp+38h+var_34], eax\ncmp ecx, 1\njz short loc_1312\nadd eax, [rdi+8]\nmov [rsp+38h+var_30], eax\nloc_1312:\nmov rdx, rsp\nadd rdi, 10h\nmov r9d, 1\nloc_131F:\ntest ecx, ecx\njle short loc_135F\nmov r10d, [rdx+4]\nmov eax, [rdx+0Ch]\nmov r11d, [rdx]\nmov r8d, [rdx+8]\ncmp r10d, eax\ncmovle eax, r10d\ncmp eax, r11d\ncmovg eax, r11d\nadd eax, [rdi]\nmov [rdx+10h], eax\ncmp ecx, 1\njz short loc_135F\ncmp r8d, r10d\ncmovg r8d, r10d\ncmp r8d, eax\ncmovg r8d, eax\nadd r8d, [rdi+4]\nmov [rdx+14h], r8d\nloc_135F:\nadd r9d, 1\nadd rdx, 0Ch\nadd rdi, 0Ch\ncmp esi, r9d\njge short loc_131F\nloc_1370:\nmovsxd rsi, esi\nlea rax, [rsi+rsi*2]\nadd rax, rcx\nmov eax, [rsp+rax*4+38h+var_38]\nmov rdx, [rsp+38h+var_10]\nsub rdx, fs:28h\njnz short loc_13B1\nadd rsp, 38h\nretn\nloc_1398:\ntest ecx, ecx\njle short loc_1370\nadd eax, [rdi+4]\nmov [rsp+38h+var_34], eax\ncmp ecx, 1\njz short loc_1370\nadd eax, [rdi+8]\nmov [rsp+38h+var_30], eax\njmp short loc_1370\nloc_13B1:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2, int a3)\n{\n __int64 v3; // rcx\n int v4; // eax\n int v5; // edx\n int v6; // eax\n int *v7; // rdx\n _DWORD *v8; // rdi\n int i; // r9d\n int v10; // r10d\n int v11; // eax\n int v12; // r8d\n int v13; // eax\n int v15; // eax\n int v16; // [rsp+0h] [rbp-38h] BYREF\n int v17; // [rsp+4h] [rbp-34h]\n int v18; // [rsp+8h] [rbp-30h]\n int v19; // [rsp+Ch] [rbp-2Ch]\n int v20; // [rsp+18h] [rbp-20h]\n unsigned __int64 v21; // [rsp+28h] [rbp-10h]\n\n v3 = a3;\n v21 = __readfsqword(0x28u);\n v4 = *a1;\n v16 = *a1;\n if ( a2 <= 0 )\n {\n if ( a3 > 0 )\n {\n v15 = a1[1] + v4;\n v17 = v15;\n if ( a3 != 1 )\n v18 = a1[2] + v15;\n }\n }\n else\n {\n v5 = v4 + a1[3];\n v19 = v5;\n if ( a2 != 1 )\n v20 = a1[6] + v5;\n if ( (int)v3 > 0 )\n {\n v6 = a1[1] + v4;\n v17 = v6;\n if ( (_DWORD)v3 != 1 )\n v18 = a1[2] + v6;\n }\n v7 = &v16;\n v8 = a1 + 4;\n for ( i = 1; i <= a2; ++i )\n {\n if ( (int)v3 > 0 )\n {\n v10 = v7[1];\n v11 = v7[3];\n v12 = v7[2];\n if ( v10 <= v11 )\n v11 = v7[1];\n if ( v11 > *v7 )\n v11 = *v7;\n v13 = *v8 + v11;\n v7[4] = v13;\n if ( (_DWORD)v3 != 1 )\n {\n if ( v12 > v10 )\n v12 = v10;\n if ( v12 > v13 )\n v12 = v13;\n v7[5] = v8[1] + v12;\n }\n }\n v7 += 3;\n v8 += 3;\n }\n }\n return (unsigned int)*(&v16 + 3 * a2 + v3);\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\nsub rsp, 38h\nmovsxd rcx, edx\nmov rax, fs:28h\nmov [rsp+38h+var_10], rax\nmov eax, [rdi]\nmov [rsp+38h+var_38], eax\ntest esi, esi\njle loc_1398\nmov edx, [rdi+0Ch]\nadd edx, eax\nmov [rsp+38h+var_2C], edx\ncmp esi, 1\njz short loc_12FB\nadd edx, [rdi+18h]\nmov [rsp+38h+var_20], edx\nloc_12FB:\ntest ecx, ecx\njle short loc_1312\nadd eax, [rdi+4]\nmov [rsp+38h+var_34], eax\ncmp ecx, 1\njz short loc_1312\nadd eax, [rdi+8]\nmov [rsp+38h+var_30], eax\nloc_1312:\nmov rdx, rsp\nadd rdi, 10h\nmov r9d, 1\nloc_131F:\ntest ecx, ecx\njle short loc_135F\nmov r10d, [rdx+4]\nmov eax, [rdx+0Ch]\nmov r11d, [rdx]\nmov r8d, [rdx+8]\ncmp r10d, eax\ncmovle eax, r10d\ncmp eax, r11d\ncmovg eax, r11d\nadd eax, [rdi]\nmov [rdx+10h], eax\ncmp ecx, 1\njz short loc_135F\ncmp r8d, r10d\ncmovg r8d, r10d\ncmp r8d, eax\ncmovg r8d, eax\nadd r8d, [rdi+4]\nmov [rdx+14h], r8d\nloc_135F:\nadd r9d, 1\nadd rdx, 0Ch\nadd rdi, 0Ch\ncmp esi, r9d\njge short loc_131F\nloc_1370:\nmovsxd rsi, esi\nlea rax, [rsi+rsi*2]\nadd rax, rcx\nmov eax, [rsp+rax*4+38h+var_38]\nmov rdx, [rsp+38h+var_10]\nsub rdx, fs:28h\njnz short loc_13B1\nadd rsp, 38h\nretn\nloc_1398:\ntest ecx, ecx\njle short loc_1370\nadd eax, [rdi+4]\nmov [rsp+38h+var_34], eax\ncmp ecx, 1\njz short loc_1370\nadd eax, [rdi+8]\nmov [rsp+38h+var_30], eax\njmp short loc_1370\nloc_13B1:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12C0(int *a1, int a2, int a3)\n{\n __int64 v3; // rcx\n int v4; // eax\n int v5; // edx\n int v6; // eax\n int *v7; // rdx\n _DWORD *v8; // rdi\n int i; // r9d\n int v10; // r10d\n int v11; // eax\n int v12; // r8d\n int v13; // eax\n int v15; // eax\n int v16; // [rsp+0h] [rbp-38h] BYREF\n int v17; // [rsp+4h] [rbp-34h]\n int v18; // [rsp+8h] [rbp-30h]\n int v19; // [rsp+Ch] [rbp-2Ch]\n int v20; // [rsp+18h] [rbp-20h]\n unsigned __int64 v21; // [rsp+28h] [rbp-10h]\n\n v3 = a3;\n v21 = __readfsqword(0x28u);\n v4 = *a1;\n v16 = *a1;\n if ( a2 <= 0 )\n {\n if ( a3 > 0 )\n {\n v15 = a1[1] + v4;\n v17 = v15;\n if ( a3 != 1 )\n v18 = a1[2] + v15;\n }\n }\n else\n {\n v5 = v4 + a1[3];\n v19 = v5;\n if ( a2 != 1 )\n v20 = a1[6] + v5;\n if ( (int)v3 > 0 )\n {\n v6 = a1[1] + v4;\n v17 = v6;\n if ( (_DWORD)v3 != 1 )\n v18 = a1[2] + v6;\n }\n v7 = &v16;\n v8 = a1 + 4;\n for ( i = 1; i <= a2; ++i )\n {\n if ( (int)v3 > 0 )\n {\n v10 = v7[1];\n v11 = v7[3];\n v12 = v7[2];\n if ( v10 <= v11 )\n v11 = v7[1];\n if ( v11 > *v7 )\n v11 = *v7;\n v13 = *v8 + v11;\n v7[4] = v13;\n if ( (_DWORD)v3 != 1 )\n {\n if ( v12 > v10 )\n v12 = v10;\n if ( v12 > v13 )\n v12 = v13;\n v7[5] = v8[1] + v12;\n }\n }\n v7 += 3;\n v8 += 3;\n }\n }\n return (unsigned int)*(&v16 + 3 * a2 + v3);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12C0(int *a1, int a2, int a3) {\n long long v3;\n int v4;\n int v5;\n int v6;\n int *v7;\n uint32_t *v8;\n int i;\n int v10;\n int v11;\n int v12;\n int v13;\n int v15;\n int v16;\n int v17;\n int v18;\n int v19;\n int v20;\n unsigned long long v21;\n v3 = a3;\n v21 = __readfsqword(40u);\n v4 = *a1;\n v16 = *a1;\n if (a2 <= 0) {\n if (a3 > 0) {\n v15 = a1[1] + v4;\n v17 = v15;\n if (a3 != 1) v18 = a1[2] + v15;\n }\n } else {\n v5 = v4 + a1[3];\n v19 = v5;\n if (a2 != 1) v20 = a1[6] + v5;\n if ((int)v3 > 0) {\n v6 = a1[1] + v4;\n v17 = v6;\n if ((uint32_t)v3 != 1) v18 = a1[2] + v6;\n }\n v7 = &v16;\n v8 = a1 + 4;\n for (i = 1; i <= a2; ++i) {\n if ((int)v3 > 0) {\n v10 = v7[1];\n v11 = v7[3];\n v12 = v7[2];\n if (v10 <= v11) v11 = v7[1];\n if (v11 > *v7) v11 = *v7;\n v13 = *v8 + v11;\n v7[4] = v13;\n if ((uint32_t)v3 != 1) {\n if (v12 > v10) v12 = v10;\n if (v12 > v13) v12 = v13;\n v7[5] = v8[1] + v12;\n }\n }\n v7 += 3;\n v8 += 3;\n }\n }\n return (unsigned int)*(&v16 + 3 * a2 + v3);\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2, int a3) {\n long long v3;\n int v4;\n int v5;\n int v6;\n int *v7;\n uint32_t *v8;\n int i;\n int v10;\n int v11;\n int v12;\n int v13;\n int v15;\n int v16;\n int v17;\n int v18;\n int v19;\n int v20;\n unsigned long long v21;\n v3 = a3;\n v21 = __readfsqword(40u);\n v4 = *a1;\n v16 = *a1;\n if (a2 <= 0) {\n if (a3 > 0) {\n v15 = a1[1] + v4;\n v17 = v15;\n if (a3 != 1) v18 = a1[2] + v15;\n }\n } else {\n v5 = v4 + a1[3];\n v19 = v5;\n if (a2 != 1) v20 = a1[6] + v5;\n if ((int)v3 > 0) {\n v6 = a1[1] + v4;\n v17 = v6;\n if ((uint32_t)v3 != 1) v18 = a1[2] + v6;\n }\n v7 = &v16;\n v8 = a1 + 4;\n for (i = 1; i <= a2; ++i) {\n if ((int)v3 > 0) {\n v10 = v7[1];\n v11 = v7[3];\n v12 = v7[2];\n if (v10 <= v11) v11 = v7[1];\n if (v11 > *v7) v11 = *v7;\n v13 = *v8 + v11;\n v7[4] = v13;\n if ((uint32_t)v3 != 1) {\n if (v12 > v10) v12 = v10;\n if (v12 > v13) v12 = v13;\n v7[5] = v8[1] + v12;\n }\n }\n v7 += 3;\n v8 += 3;\n }\n }\n return (unsigned int)*(&v16 + 3 * a2 + v3);\n}" + }, + { + "index": 1, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n#define R 3\n\n#define C 3\n\n\n\n", + "func": "int func0(int cost[R][C], int m, int n) {\n int tc[R][C];\n tc[0][0] = cost[0][0];\n for (int i = 1; i <= m; ++i) {\n tc[i][0] = tc[i - 1][0] + cost[i][0];\n }\n for (int j = 1; j <= n; ++j) {\n tc[0][j] = tc[0][j - 1] + cost[0][j];\n }\n for (int i = 1; i <= m; ++i) {\n for (int j = 1; j <= n; ++j) {\n int min_val = tc[i - 1][j - 1];\n if (tc[i - 1][j] < min_val) min_val = tc[i - 1][j];\n if (tc[i][j - 1] < min_val) min_val = tc[i][j - 1];\n tc[i][j] = min_val + cost[i][j];\n }\n }\n return tc[m][n];\n}", + "test": "int main() {\n\n int cost1[R][C] = {{1, 2, 3}, {4, 8, 2}, {1, 5, 3}};\n\n int cost2[R][C] = {{2, 3, 4}, {5, 9, 3}, {2, 6, 4}};\n\n int cost3[R][C] = {{3, 4, 5}, {6, 10, 4}, {3, 7, 5}};\n\n\n\n assert(func0(cost1, 2, 2) == 8);\n\n assert(func0(cost2, 2, 2) == 12);\n\n assert(func0(cost3, 2, 2) == 16);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x38,%rsp\nmov (%rdi),%r8d\nmov %fs:0x28,%rax\nmov %rax,0x28(%rsp)\nxor %eax,%eax\nmov %r8d,(%rsp)\ntest %esi,%esi\njle 12f9 \nmov 0xc(%rdi),%eax\nadd %r8d,%eax\nmov %eax,0xc(%rsp)\ncmp $0x1,%esi\nje 12f9 \nadd 0x18(%rdi),%eax\nmov %eax,0x18(%rsp)\ntest %edx,%edx\njle 14a8 \nmov 0x4(%rdi),%eax\nadd %r8d,%eax\nmov %eax,0x4(%rsp)\ncmp $0x1,%edx\nje 14a8 \nadd 0x8(%rdi),%eax\nmov %eax,0x8(%rsp)\ntest %esi,%esi\njle 1480 \ncmp $0x3,%edx\njle 14b5 \nmov 0x4(%rsp),%eax\nmov 0xc(%rsp),%r10d\nmov 0x8(%rsp),%ecx\ncmp %r10d,%eax\nmov %r10d,%r9d\ncmovle %eax,%r9d\ncmp %r8d,%r9d\ncmovle %r9d,%r8d\nadd 0x10(%rdi),%r8d\ncmp %ecx,%eax\ncmovg %ecx,%eax\nmov %r8d,0x10(%rsp)\ncmp %r8d,%eax\ncmovg %r8d,%eax\nadd 0x14(%rdi),%eax\ncmp %r10d,%ecx\ncmovg %r10d,%ecx\nmov %eax,0x14(%rsp)\ncmp %eax,%ecx\ncmovg %eax,%ecx\nadd 0x18(%rdi),%ecx\nmov %ecx,0x18(%rsp)\nmov $0x4,%ecx\nlea -0x1(%rcx),%r9d\nmovslq %ecx,%r10\nmovslq %r9d,%r9\nmov (%rsp,%r10,4),%r8d\nmov 0xc(%rsp,%r9,4),%eax\ncmp %eax,(%rsp,%r9,4)\ncmovle (%rsp,%r9,4),%eax\nlea 0xc(%rdi,%r10,4),%r9\ncmp %eax,%r8d\ncmovle %r8d,%eax\nadd $0x1,%ecx\nadd (%r9),%eax\nmov %eax,0xc(%rsp,%r10,4)\ncmp %ecx,%edx\njl 13d1 \nmovslq %ecx,%rcx\ncmp %r8d,(%rsp,%rcx,4)\ncmovle (%rsp,%rcx,4),%r8d\ncmp %eax,%r8d\ncmovg %eax,%r8d\nadd 0x4(%r9),%r8d\nmov %r8d,0xc(%rsp,%rcx,4)\ncmp $0x1,%esi\njle 1480 \nmov $0x1,%ecx\ncmp $0x3,%edx\njle 1425 \nmov 0x10(%rsp),%r8d\nmov 0xc(%rsp),%r9d\ncmp %r8d,0x18(%rsp)\nmov 0x14(%rsp),%eax\nmov %r8d,%ecx\ncmovle 0x18(%rsp),%ecx\ncmp %r9d,%ecx\ncmovg %r9d,%ecx\nadd 0x1c(%rdi),%ecx\ncmp %r8d,%eax\ncmovg %r8d,%eax\nmov %ecx,0x1c(%rsp)\ncmp %ecx,%eax\ncmovg %ecx,%eax\nadd 0x20(%rdi),%eax\nmov $0x4,%ecx\nmov %eax,0x20(%rsp)\nlea -0x1(%rcx),%r9d\nmovslq %ecx,%r10\nmovslq %r9d,%r9\nmov 0xc(%rsp,%r10,4),%r8d\nlea 0x18(%rdi,%r10,4),%rdi\nmov 0xc(%rsp,%r9,4),%eax\ncmp %eax,0x18(%rsp,%r9,4)\ncmovle 0x18(%rsp,%r9,4),%eax\ncmp %r8d,%eax\ncmovg %r8d,%eax\nadd $0x1,%ecx\nadd (%rdi),%eax\nmov %eax,0x18(%rsp,%r10,4)\ncmp %ecx,%edx\njl 1480 \nmovslq %ecx,%rcx\ncmp %r8d,0xc(%rsp,%rcx,4)\ncmovle 0xc(%rsp,%rcx,4),%r8d\ncmp %eax,%r8d\ncmovg %eax,%r8d\nadd 0x4(%rdi),%r8d\nmov %r8d,0x18(%rsp,%rcx,4)\nnopl 0x0(%rax)\nmovslq %esi,%rsi\nmovslq %edx,%rdx\nlea (%rsi,%rsi,2),%rax\nadd %rax,%rdx\nmov 0x28(%rsp),%rsi\nxor %fs:0x28,%rsi\nmov (%rsp,%rdx,4),%eax\njne 14bf \nadd $0x38,%rsp\nretq\nnopl (%rax)\ntest %esi,%esi\njle 1480 \ntest %edx,%edx\njle 1480 \njmpq 1323 \nmov $0x1,%ecx\njmpq 137e \ncallq 1060 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmovsxd rcx, esi\nmovsxd rsi, edx\nsub rsp, 30h\nmov rax, fs:28h\nmov [rsp+38h+var_10], rax\nmov eax, [rdi]\nmov [rsp+38h+var_38], eax\ntest ecx, ecx\njle loc_1438\nmov edx, [rdi+0Ch]\nadd edx, eax\nmov [rsp+38h+var_2C], edx\ncmp ecx, 1\njz short loc_12FF\nadd edx, [rdi+18h]\nmov [rsp+38h+var_20], edx\nloc_12FF:\ntest esi, esi\njle loc_1411\nmov edx, [rdi+4]\nadd edx, eax\nmov [rsp+38h+var_34], edx\ncmp esi, 1\njz loc_1458\nmov r10d, [rdi+8]\nadd r10d, edx\nmov [rsp+38h+var_30], r10d\ncmp esi, 3\njle loc_1495\nmov r8d, [rsp+38h+var_2C]\nmov r11d, 4\nmov ebx, 10h\ncmp edx, r8d\nmov r9d, r8d\ncmovle r9d, edx\ncmp r9d, eax\ncmovg r9d, eax\nadd r9d, [rdi+10h]\ncmp r10d, edx\ncmovle edx, r10d\nmov [rsp+38h+var_28], r9d\ncmp edx, r9d\ncmovg edx, r9d\nadd edx, [rdi+14h]\ncmp r10d, r8d\ncmovg r10d, r8d\ncmp edx, r10d\ncmovg edx, r10d\nadd edx, [rdi+18h]\nlea r10, [rdi+1Ch]\ncmp eax, r8d\ncmovg eax, r8d\nmov [rsp+38h+var_20], edx\nmov edx, r9d\ncmp eax, r9d\ncmovg eax, r9d\nadd eax, [rdi+1Ch]\nmov [rsp+38h+var_1C], eax\nloc_139A:\nmov r9d, [rsp+38h+var_30]\ncmp edx, r9d\ncmovg edx, r9d\ncmp edx, eax\ncmovg edx, eax\nadd edx, [r10+4]\nmov [rsp+38h+var_24], edx\ncmp ecx, 1\njz short loc_1411\ncmp esi, 3\njle short loc_13D8\nmov eax, [rsp+38h+var_28]\nmov edx, [rsp+38h+var_20]\ncmp eax, edx\ncmovg eax, edx\ncmp eax, r8d\ncmovg eax, r8d\nadd eax, [rdi+1Ch]\nmov [rsp+38h+var_1C], eax\nloc_13D8:\nmov edx, [rsp+38h+var_20]\nmov eax, [rsp+r11*4+38h+var_2C]\nlea rdi, [rdi+rbx+18h]\ncmp r8d, edx\ncmovle edx, r8d\nmov r8d, [rsp+38h+var_24]\ncmp edx, eax\ncmovg edx, eax\nadd edx, [rdi]\ncmp eax, r8d\ncmovg eax, r8d\nmov [rsp+r11*4+38h+var_20], edx\ncmp eax, edx\ncmovg eax, edx\nadd eax, [rdi+4]\nmov [rsp+38h+var_18], eax\nloc_1411:\nlea rax, [rcx+rcx*2]\nadd rax, rsi\nmov eax, [rsp+rax*4+38h+var_38]\nmov rdx, [rsp+38h+var_10]\nsub rdx, fs:28h\njnz loc_14C1\nadd rsp, 30h\npop rbx\nretn\nloc_1438:\ntest esi, esi\njle short loc_1411\nadd eax, [rdi+4]\nmov [rsp+38h+var_34], eax\ncmp esi, 1\njz short loc_1411\nadd eax, [rdi+8]\nmov [rsp+38h+var_30], eax\njmp short loc_1411\nloc_1458:\nmov r8d, edx\nmov edx, [rsp+38h+var_2C]\ncmp eax, edx\ncmovg eax, edx\ncmp eax, r8d\ncmovg eax, r8d\nadd eax, [rdi+10h]\nmov [rsp+38h+var_28], eax\ncmp ecx, 1\njz short loc_1411\nmov eax, [rsp+38h+var_20]\ncmp edx, eax\ncmovg edx, eax\nmov eax, [rsp+38h+var_28]\ncmp edx, eax\ncmovg edx, eax\nadd edx, [rdi+1Ch]\nmov [rsp+38h+var_1C], edx\njmp loc_1411\nloc_1495:\nmov r8d, [rsp+38h+var_2C]\nlea r10, [rdi+10h]\nmov r11d, 1\nmov ebx, 4\ncmp eax, r8d\ncmovg eax, r8d\ncmp eax, edx\ncmovg eax, edx\nadd eax, [rdi+10h]\nmov [rsp+38h+var_28], eax\njmp loc_139A\nloc_14C1:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2, int a3)\n{\n __int64 v3; // rcx\n __int64 v4; // rsi\n int v5; // eax\n int v6; // edx\n int v7; // edx\n int v8; // r10d\n int v9; // r8d\n __int64 v10; // r11\n __int64 v11; // rbx\n int v12; // r9d\n int v13; // r9d\n int v14; // edx\n int v15; // edx\n _DWORD *v16; // r10\n int v17; // eax\n int v18; // eax\n int v19; // edx\n int v20; // eax\n int *v21; // rdi\n int v22; // edx\n int v24; // eax\n int v25; // r8d\n int v26; // edx\n int v27; // [rsp+0h] [rbp-38h]\n int v28; // [rsp+4h] [rbp-34h]\n int v29; // [rsp+8h] [rbp-30h]\n int v30; // [rsp+Ch] [rbp-2Ch]\n int v31; // [rsp+10h] [rbp-28h]\n int v32; // [rsp+14h] [rbp-24h]\n int v33; // [rsp+18h] [rbp-20h]\n int v34; // [rsp+1Ch] [rbp-1Ch]\n int v35; // [rsp+20h] [rbp-18h]\n unsigned __int64 v36; // [rsp+28h] [rbp-10h]\n\n v3 = a2;\n v4 = a3;\n v36 = __readfsqword(0x28u);\n v5 = *a1;\n v27 = *a1;\n if ( (int)v3 <= 0 )\n {\n if ( a3 > 0 )\n {\n v24 = a1[1] + v5;\n v28 = v24;\n if ( a3 != 1 )\n v29 = a1[2] + v24;\n }\n }\n else\n {\n v6 = v5 + a1[3];\n v30 = v6;\n if ( (_DWORD)v3 != 1 )\n v33 = a1[6] + v6;\n if ( (int)v4 > 0 )\n {\n v7 = v5 + a1[1];\n v28 = v7;\n if ( (_DWORD)v4 == 1 )\n {\n v25 = v7;\n v26 = v30;\n if ( v5 > v30 )\n v5 = v30;\n if ( v5 > v25 )\n v5 = v25;\n v31 = a1[4] + v5;\n if ( (_DWORD)v3 != 1 )\n {\n if ( v30 > v33 )\n v26 = v33;\n if ( v26 > v31 )\n v26 = v31;\n v34 = a1[7] + v26;\n }\n }\n else\n {\n v8 = v7 + a1[2];\n v29 = v8;\n if ( (int)v4 <= 3 )\n {\n v9 = v30;\n v16 = a1 + 4;\n v10 = 1LL;\n v11 = 1LL;\n if ( v5 > v30 )\n v5 = v30;\n if ( v5 > v7 )\n v5 = v7;\n v17 = a1[4] + v5;\n v31 = v17;\n }\n else\n {\n v9 = v30;\n v10 = 4LL;\n v11 = 4LL;\n v12 = v30;\n if ( v7 <= v30 )\n v12 = v7;\n if ( v12 > v5 )\n v12 = v5;\n v13 = a1[4] + v12;\n if ( v8 <= v7 )\n v7 = v8;\n v31 = v13;\n if ( v7 > v13 )\n v7 = v13;\n v14 = a1[5] + v7;\n if ( v8 > v30 )\n v8 = v30;\n if ( v14 > v8 )\n v14 = v8;\n v15 = a1[6] + v14;\n v16 = a1 + 7;\n if ( v5 > v30 )\n v5 = v30;\n v33 = v15;\n v7 = v13;\n if ( v5 > v13 )\n v5 = v13;\n v17 = a1[7] + v5;\n v34 = v17;\n }\n if ( v7 > v29 )\n v7 = v29;\n if ( v7 > v17 )\n v7 = v17;\n v32 = v16[1] + v7;\n if ( (_DWORD)v3 != 1 )\n {\n if ( (int)v4 > 3 )\n {\n v18 = v31;\n if ( v31 > v33 )\n v18 = v33;\n if ( v18 > v9 )\n v18 = v9;\n v34 = a1[7] + v18;\n }\n v19 = v33;\n v20 = *(&v30 + v10);\n v21 = &a1[v11 + 6];\n if ( v9 <= v33 )\n v19 = v9;\n if ( v19 > v20 )\n v19 = *(&v30 + v10);\n v22 = *v21 + v19;\n if ( v20 > v32 )\n v20 = v32;\n *(&v33 + v10) = v22;\n if ( v20 > v22 )\n v20 = v22;\n v35 = v21[1] + v20;\n }\n }\n }\n }\n return (unsigned int)*(&v27 + 3 * v3 + v4);\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\npush rbx\nmovsxd rcx, esi\nmovsxd rsi, edx\nsub rsp, 30h\nmov rax, fs:28h\nmov [rsp+38h+var_10], rax\nmov eax, [rdi]\nmov [rsp+38h+var_38], eax\ntest ecx, ecx\njle loc_1438\nmov edx, [rdi+0Ch]\nadd edx, eax\nmov [rsp+38h+var_2C], edx\ncmp ecx, 1\njz short loc_12FF\nadd edx, [rdi+18h]\nmov [rsp+38h+var_20], edx\nloc_12FF:\ntest esi, esi\njle loc_1411\nmov edx, [rdi+4]\nadd edx, eax\nmov [rsp+38h+var_34], edx\ncmp esi, 1\njz loc_1458\nmov r10d, [rdi+8]\nadd r10d, edx\nmov [rsp+38h+var_30], r10d\ncmp esi, 3\njle loc_1495\nmov r8d, [rsp+38h+var_2C]\nmov r11d, 4\nmov ebx, 10h\ncmp edx, r8d\nmov r9d, r8d\ncmovle r9d, edx\ncmp r9d, eax\ncmovg r9d, eax\nadd r9d, [rdi+10h]\ncmp r10d, edx\ncmovle edx, r10d\nmov [rsp+38h+var_28], r9d\ncmp edx, r9d\ncmovg edx, r9d\nadd edx, [rdi+14h]\ncmp r10d, r8d\ncmovg r10d, r8d\ncmp edx, r10d\ncmovg edx, r10d\nadd edx, [rdi+18h]\nlea r10, [rdi+1Ch]\ncmp eax, r8d\ncmovg eax, r8d\nmov [rsp+38h+var_20], edx\nmov edx, r9d\ncmp eax, r9d\ncmovg eax, r9d\nadd eax, [rdi+1Ch]\nmov [rsp+38h+var_1C], eax\nloc_139A:\nmov r9d, [rsp+38h+var_30]\ncmp edx, r9d\ncmovg edx, r9d\ncmp edx, eax\ncmovg edx, eax\nadd edx, [r10+4]\nmov [rsp+38h+var_24], edx\ncmp ecx, 1\njz short loc_1411\ncmp esi, 3\njle short loc_13D8\nmov eax, [rsp+38h+var_28]\nmov edx, [rsp+38h+var_20]\ncmp eax, edx\ncmovg eax, edx\ncmp eax, r8d\ncmovg eax, r8d\nadd eax, [rdi+1Ch]\nmov [rsp+38h+var_1C], eax\nloc_13D8:\nmov edx, [rsp+38h+var_20]\nmov eax, [rsp+r11*4+38h+var_2C]\nlea rdi, [rdi+rbx+18h]\ncmp r8d, edx\ncmovle edx, r8d\nmov r8d, [rsp+38h+var_24]\ncmp edx, eax\ncmovg edx, eax\nadd edx, [rdi]\ncmp eax, r8d\ncmovg eax, r8d\nmov [rsp+r11*4+38h+var_20], edx\ncmp eax, edx\ncmovg eax, edx\nadd eax, [rdi+4]\nmov [rsp+38h+var_18], eax\nloc_1411:\nlea rax, [rcx+rcx*2]\nadd rax, rsi\nmov eax, [rsp+rax*4+38h+var_38]\nmov rdx, [rsp+38h+var_10]\nsub rdx, fs:28h\njnz loc_14C1\nadd rsp, 30h\npop rbx\nretn\nloc_1438:\ntest esi, esi\njle short loc_1411\nadd eax, [rdi+4]\nmov [rsp+38h+var_34], eax\ncmp esi, 1\njz short loc_1411\nadd eax, [rdi+8]\nmov [rsp+38h+var_30], eax\njmp short loc_1411\nloc_1458:\nmov r8d, edx\nmov edx, [rsp+38h+var_2C]\ncmp eax, edx\ncmovg eax, edx\ncmp eax, r8d\ncmovg eax, r8d\nadd eax, [rdi+10h]\nmov [rsp+38h+var_28], eax\ncmp ecx, 1\njz short loc_1411\nmov eax, [rsp+38h+var_20]\ncmp edx, eax\ncmovg edx, eax\nmov eax, [rsp+38h+var_28]\ncmp edx, eax\ncmovg edx, eax\nadd edx, [rdi+1Ch]\nmov [rsp+38h+var_1C], edx\njmp loc_1411\nloc_1495:\nmov r8d, [rsp+38h+var_2C]\nlea r10, [rdi+10h]\nmov r11d, 1\nmov ebx, 4\ncmp eax, r8d\ncmovg eax, r8d\ncmp eax, edx\ncmovg eax, edx\nadd eax, [rdi+10h]\nmov [rsp+38h+var_28], eax\njmp loc_139A\nloc_14C1:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12C0(int *a1, int a2, int a3)\n{\n __int64 v3; // rcx\n __int64 v4; // rsi\n int v5; // eax\n int v6; // edx\n int v7; // edx\n int v8; // r10d\n int v9; // r8d\n __int64 v10; // r11\n __int64 v11; // rbx\n int v12; // r9d\n int v13; // r9d\n int v14; // edx\n int v15; // edx\n _DWORD *v16; // r10\n int v17; // eax\n int v18; // eax\n int v19; // edx\n int v20; // eax\n int *v21; // rdi\n int v22; // edx\n int v24; // eax\n int v25; // r8d\n int v26; // edx\n int v27; // [rsp+0h] [rbp-38h]\n int v28; // [rsp+4h] [rbp-34h]\n int v29; // [rsp+8h] [rbp-30h]\n int v30; // [rsp+Ch] [rbp-2Ch]\n int v31; // [rsp+10h] [rbp-28h]\n int v32; // [rsp+14h] [rbp-24h]\n int v33; // [rsp+18h] [rbp-20h]\n int v34; // [rsp+1Ch] [rbp-1Ch]\n int v35; // [rsp+20h] [rbp-18h]\n unsigned __int64 v36; // [rsp+28h] [rbp-10h]\n\n v3 = a2;\n v4 = a3;\n v36 = __readfsqword(0x28u);\n v5 = *a1;\n v27 = *a1;\n if ( (int)v3 <= 0 )\n {\n if ( a3 > 0 )\n {\n v24 = a1[1] + v5;\n v28 = v24;\n if ( a3 != 1 )\n v29 = a1[2] + v24;\n }\n }\n else\n {\n v6 = v5 + a1[3];\n v30 = v6;\n if ( (_DWORD)v3 != 1 )\n v33 = a1[6] + v6;\n if ( (int)v4 > 0 )\n {\n v7 = v5 + a1[1];\n v28 = v7;\n if ( (_DWORD)v4 == 1 )\n {\n v25 = v7;\n v26 = v30;\n if ( v5 > v30 )\n v5 = v30;\n if ( v5 > v25 )\n v5 = v25;\n v31 = a1[4] + v5;\n if ( (_DWORD)v3 != 1 )\n {\n if ( v30 > v33 )\n v26 = v33;\n if ( v26 > v31 )\n v26 = v31;\n v34 = a1[7] + v26;\n }\n }\n else\n {\n v8 = v7 + a1[2];\n v29 = v8;\n if ( (int)v4 <= 3 )\n {\n v9 = v30;\n v16 = a1 + 4;\n v10 = 1LL;\n v11 = 1LL;\n if ( v5 > v30 )\n v5 = v30;\n if ( v5 > v7 )\n v5 = v7;\n v17 = a1[4] + v5;\n v31 = v17;\n }\n else\n {\n v9 = v30;\n v10 = 4LL;\n v11 = 4LL;\n v12 = v30;\n if ( v7 <= v30 )\n v12 = v7;\n if ( v12 > v5 )\n v12 = v5;\n v13 = a1[4] + v12;\n if ( v8 <= v7 )\n v7 = v8;\n v31 = v13;\n if ( v7 > v13 )\n v7 = v13;\n v14 = a1[5] + v7;\n if ( v8 > v30 )\n v8 = v30;\n if ( v14 > v8 )\n v14 = v8;\n v15 = a1[6] + v14;\n v16 = a1 + 7;\n if ( v5 > v30 )\n v5 = v30;\n v33 = v15;\n v7 = v13;\n if ( v5 > v13 )\n v5 = v13;\n v17 = a1[7] + v5;\n v34 = v17;\n }\n if ( v7 > v29 )\n v7 = v29;\n if ( v7 > v17 )\n v7 = v17;\n v32 = v16[1] + v7;\n if ( (_DWORD)v3 != 1 )\n {\n if ( (int)v4 > 3 )\n {\n v18 = v31;\n if ( v31 > v33 )\n v18 = v33;\n if ( v18 > v9 )\n v18 = v9;\n v34 = a1[7] + v18;\n }\n v19 = v33;\n v20 = *(&v30 + v10);\n v21 = &a1[v11 + 6];\n if ( v9 <= v33 )\n v19 = v9;\n if ( v19 > v20 )\n v19 = *(&v30 + v10);\n v22 = *v21 + v19;\n if ( v20 > v32 )\n v20 = v32;\n *(&v33 + v10) = v22;\n if ( v20 > v22 )\n v20 = v22;\n v35 = v21[1] + v20;\n }\n }\n }\n }\n return (unsigned int)*(&v27 + 3 * v3 + v4);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12C0(int *a1, int a2, int a3) {\n long long v3;\n long long v4;\n int v5;\n int v6;\n int v7;\n int v8;\n int v9;\n long long v10;\n long long v11;\n int v12;\n int v13;\n int v14;\n int v15;\n uint32_t *v16;\n int v17;\n int v18;\n int v19;\n int v20;\n int *v21;\n int v22;\n int v24;\n int v25;\n int v26;\n int v27;\n int v28;\n int v29;\n int v30;\n int v31;\n int v32;\n int v33;\n int v34;\n int v35;\n unsigned long long v36;\n v3 = a2;\n v4 = a3;\n v36 = __readfsqword(40u);\n v5 = *a1;\n v27 = *a1;\n if ((int)v3 <= 0) {\n if (a3 > 0) {\n v24 = a1[1] + v5;\n v28 = v24;\n if (a3 != 1) v29 = a1[2] + v24;\n }\n } else {\n v6 = v5 + a1[3];\n v30 = v6;\n if ((uint32_t)v3 != 1) v33 = a1[6] + v6;\n if ((int)v4 > 0) {\n v7 = v5 + a1[1];\n v28 = v7;\n if ((uint32_t)v4 == 1) {\n v25 = v7;\n v26 = v30;\n if (v5 > v30) v5 = v30;\n if (v5 > v25) v5 = v25;\n v31 = a1[4] + v5;\n if ((uint32_t)v3 != 1) {\n if (v30 > v33) v26 = v33;\n if (v26 > v31) v26 = v31;\n v34 = a1[7] + v26;\n }\n } else {\n v8 = v7 + a1[2];\n v29 = v8;\n if ((int)v4 <= 3) {\n v9 = v30;\n v16 = a1 + 4;\n v10 = 1LL;\n v11 = 1LL;\n if (v5 > v30) v5 = v30;\n if (v5 > v7) v5 = v7;\n v17 = a1[4] + v5;\n v31 = v17;\n } else {\n v9 = v30;\n v10 = 4LL;\n v11 = 4LL;\n v12 = v30;\n if (v7 <= v30) v12 = v7;\n if (v12 > v5) v12 = v5;\n v13 = a1[4] + v12;\n if (v8 <= v7) v7 = v8;\n v31 = v13;\n if (v7 > v13) v7 = v13;\n v14 = a1[5] + v7;\n if (v8 > v30) v8 = v30;\n if (v14 > v8) v14 = v8;\n v15 = a1[6] + v14;\n v16 = a1 + 7;\n if (v5 > v30) v5 = v30;\n v33 = v15;\n v7 = v13;\n if (v5 > v13) v5 = v13;\n v17 = a1[7] + v5;\n v34 = v17;\n }\n if (v7 > v29) v7 = v29;\n if (v7 > v17) v7 = v17;\n v32 = v16[1] + v7;\n if ((uint32_t)v3 != 1) {\n if ((int)v4 > 3) {\n v18 = v31;\n if (v31 > v33) v18 = v33;\n if (v18 > v9) v18 = v9;\n v34 = a1[7] + v18;\n }\n v19 = v33;\n v20 = *(&v30 + v10);\n v21 = &a1[v11 + 6];\n if (v9 <= v33) v19 = v9;\n if (v19 > v20) v19 = *(&v30 + v10);\n v22 = *v21 + v19;\n if (v20 > v32) v20 = v32;\n *(&v33 + v10) = v22;\n if (v20 > v22) v20 = v22;\n v35 = v21[1] + v20;\n }\n }\n }\n }\n return (unsigned int)*(&v27 + 3 * v3 + v4);\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2, int a3) {\n long long v3;\n long long v4;\n int v5;\n int v6;\n int v7;\n int v8;\n int v9;\n long long v10;\n long long v11;\n int v12;\n int v13;\n int v14;\n int v15;\n uint32_t *v16;\n int v17;\n int v18;\n int v19;\n int v20;\n int *v21;\n int v22;\n int v24;\n int v25;\n int v26;\n int v27;\n int v28;\n int v29;\n int v30;\n int v31;\n int v32;\n int v33;\n int v34;\n int v35;\n unsigned long long v36;\n v3 = a2;\n v4 = a3;\n v36 = __readfsqword(40u);\n v5 = *a1;\n v27 = *a1;\n if ((int)v3 <= 0) {\n if (a3 > 0) {\n v24 = a1[1] + v5;\n v28 = v24;\n if (a3 != 1) v29 = a1[2] + v24;\n }\n } else {\n v6 = v5 + a1[3];\n v30 = v6;\n if ((uint32_t)v3 != 1) v33 = a1[6] + v6;\n if ((int)v4 > 0) {\n v7 = v5 + a1[1];\n v28 = v7;\n if ((uint32_t)v4 == 1) {\n v25 = v7;\n v26 = v30;\n if (v5 > v30) v5 = v30;\n if (v5 > v25) v5 = v25;\n v31 = a1[4] + v5;\n if ((uint32_t)v3 != 1) {\n if (v30 > v33) v26 = v33;\n if (v26 > v31) v26 = v31;\n v34 = a1[7] + v26;\n }\n } else {\n v8 = v7 + a1[2];\n v29 = v8;\n if ((int)v4 <= 3) {\n v9 = v30;\n v16 = a1 + 4;\n v10 = 1LL;\n v11 = 1LL;\n if (v5 > v30) v5 = v30;\n if (v5 > v7) v5 = v7;\n v17 = a1[4] + v5;\n v31 = v17;\n } else {\n v9 = v30;\n v10 = 4LL;\n v11 = 4LL;\n v12 = v30;\n if (v7 <= v30) v12 = v7;\n if (v12 > v5) v12 = v5;\n v13 = a1[4] + v12;\n if (v8 <= v7) v7 = v8;\n v31 = v13;\n if (v7 > v13) v7 = v13;\n v14 = a1[5] + v7;\n if (v8 > v30) v8 = v30;\n if (v14 > v8) v14 = v8;\n v15 = a1[6] + v14;\n v16 = a1 + 7;\n if (v5 > v30) v5 = v30;\n v33 = v15;\n v7 = v13;\n if (v5 > v13) v5 = v13;\n v17 = a1[7] + v5;\n v34 = v17;\n }\n if (v7 > v29) v7 = v29;\n if (v7 > v17) v7 = v17;\n v32 = v16[1] + v7;\n if ((uint32_t)v3 != 1) {\n if ((int)v4 > 3) {\n v18 = v31;\n if (v31 > v33) v18 = v33;\n if (v18 > v9) v18 = v9;\n v34 = a1[7] + v18;\n }\n v19 = v33;\n v20 = *(&v30 + v10);\n v21 = &a1[v11 + 6];\n if (v9 <= v33) v19 = v9;\n if (v19 > v20) v19 = *(&v30 + v10);\n v22 = *v21 + v19;\n if (v20 > v32) v20 = v32;\n *(&v33 + v10) = v22;\n if (v20 > v22) v20 = v22;\n v35 = v21[1] + v20;\n }\n }\n }\n }\n return (unsigned int)*(&v27 + 3 * v3 + v4);\n}" + }, + { + "index": 2, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n// Function to find similar elements\n\n", + "func": "int* func0(int test_tup1[], int size1, int test_tup2[], int size2,\n int* res_size) {\n int* temp = (int*)malloc((size1 < size2 ? size1 : size2) * sizeof(int));\n if (!temp) {\n *res_size = 0;\n return NULL;\n }\n int count = 0;\n for (int i = 0; i < size1; i++) {\n for (int j = 0; j < size2; j++) {\n if (test_tup1[i] == test_tup2[j]) {\n int exists = 0;\n for (int k = 0; k < count; k++) {\n if (temp[k] == test_tup1[i]) {\n exists = 1;\n break;\n }\n }\n if (!exists) {\n temp[count++] = test_tup1[i];\n }\n break;\n }\n }\n }\n for (int i = 0; i < count - 1; i++) {\n for (int j = i + 1; j < count; j++) {\n if (temp[i] > temp[j]) {\n int swap = temp[i];\n temp[i] = temp[j];\n temp[j] = swap;\n }\n }\n }\n *res_size = count;\n return temp;\n}", + "test": "int main() {\n\n int res_size;\n\n int* res;\n\n\n\n // First assertion\n\n int test1_a[] = {3, 4, 5, 6};\n\n int test1_b[] = {5, 7, 4, 10};\n\n res = func0(test1_a, 4, test1_b, 4, &res_size);\n\n assert(res_size == 2);\n\n assert(res[0] == 4 && res[1] == 5);\n\n free(res);\n\n\n\n // Second assertion\n\n int test2_a[] = {1, 2, 3, 4};\n\n int test2_b[] = {5, 4, 3, 7};\n\n res = func0(test2_a, 4, test2_b, 4, &res_size);\n\n assert(res_size == 2);\n\n assert(res[0] == 3 && res[1] == 4);\n\n free(res);\n\n\n\n // Third assertion\n\n int test3_a[] = {11, 12, 14, 13};\n\n int test3_b[] = {17, 15, 14, 13};\n\n res = func0(test3_a, 4, test3_b, 4, &res_size);\n\n assert(res_size == 2);\n\n assert(res[0] == 13 && res[1] == 14);\n\n free(res);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x50,%rsp\nmov %rdi,-0x38(%rbp)\nmov %esi,-0x3c(%rbp)\nmov %rdx,-0x48(%rbp)\nmov %ecx,-0x40(%rbp)\nmov %r8,-0x50(%rbp)\nmov -0x3c(%rbp),%eax\ncmp %eax,-0x40(%rbp)\ncmovle -0x40(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\ncmpq $0x0,-0x8(%rbp)\njne 11fe \nmov -0x50(%rbp),%rax\nmovl $0x0,(%rax)\nmov $0x0,%eax\njmpq 13dd \nmovl $0x0,-0x28(%rbp)\nmovl $0x0,-0x24(%rbp)\njmpq 12f8 \nmovl $0x0,-0x20(%rbp)\njmpq 12e5 \nmov -0x24(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x20(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x48(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 12e1 \nmovl $0x0,-0x1c(%rbp)\nmovl $0x0,-0x18(%rbp)\njmp 129e \nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x24(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x38(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 129a \nmovl $0x1,-0x1c(%rbp)\njmp 12a6 \naddl $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%eax\ncmp -0x28(%rbp),%eax\njl 1261 \ncmpl $0x0,-0x1c(%rbp)\njne 12f3 \nmov -0x24(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x38(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x28(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x28(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\njmp 12f3 \naddl $0x1,-0x20(%rbp)\nmov -0x20(%rbp),%eax\ncmp -0x40(%rbp),%eax\njl 121d \njmp 12f4 \naddl $0x1,-0x24(%rbp)\nmov -0x24(%rbp),%eax\ncmp -0x3c(%rbp),%eax\njl 1211 \nmovl $0x0,-0x14(%rbp)\njmpq 13c1 \nmov -0x14(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x10(%rbp)\njmpq 13b1 \nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x8(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njle 13ad \nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0xc(%rbp)\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov -0x14(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov -0xc(%rbp),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x10(%rbp)\nmov -0x10(%rbp),%eax\ncmp -0x28(%rbp),%eax\njl 131e \naddl $0x1,-0x14(%rbp)\nmov -0x28(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x14(%rbp)\njl 1310 \nmov -0x50(%rbp),%rax\nmov -0x28(%rbp),%edx\nmov %edx,(%rax)\nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov [rbp+var_48], rdx\nmov [rbp+var_40], ecx\nmov [rbp+var_50], r8\nmov edx, [rbp+var_40]\nmov eax, [rbp+var_3C]\ncmp edx, eax\ncmovle eax, edx\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\ncmp [rbp+var_8], 0\njnz short loc_11FF\nmov rax, [rbp+var_50]\nmov dword ptr [rax], 0\nmov eax, 0\njmp locret_13DE\nloc_11FF:\nmov [rbp+var_28], 0\nmov [rbp+var_24], 0\njmp loc_12F9\nloc_1212:\nmov [rbp+var_20], 0\njmp loc_12E6\nloc_121E:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_20]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz loc_12E2\nmov [rbp+var_1C], 0\nmov [rbp+var_18], 0\njmp short loc_129F\nloc_1262:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_24]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_129B\nmov [rbp+var_1C], 1\njmp short loc_12A7\nloc_129B:\nadd [rbp+var_18], 1\nloc_129F:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_28]\njl short loc_1262\nloc_12A7:\ncmp [rbp+var_1C], 0\njnz short loc_12F4\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_28]\nlea edx, [rax+1]\nmov [rbp+var_28], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\njmp short loc_12F4\nloc_12E2:\nadd [rbp+var_20], 1\nloc_12E6:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_40]\njl loc_121E\njmp short loc_12F5\nloc_12F4:\nnop\nloc_12F5:\nadd [rbp+var_24], 1\nloc_12F9:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_3C]\njl loc_1212\nmov [rbp+var_14], 0\njmp loc_13C2\nloc_1311:\nmov eax, [rbp+var_14]\nadd eax, 1\nmov [rbp+var_10], eax\njmp loc_13B2\nloc_131F:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_13AE\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_C]\nmov [rdx], eax\nloc_13AE:\nadd [rbp+var_10], 1\nloc_13B2:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_28]\njl loc_131F\nadd [rbp+var_14], 1\nloc_13C2:\nmov eax, [rbp+var_28]\nsub eax, 1\ncmp [rbp+var_14], eax\njl loc_1311\nmov rax, [rbp+var_50]\nmov edx, [rbp+var_28]\nmov [rax], edx\nmov rax, [rbp+var_8]\nlocret_13DE:\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, __int64 a3, int a4, _DWORD *a5)\n{\n int v5; // eax\n int v7; // eax\n int v11; // [rsp+28h] [rbp-28h]\n int i; // [rsp+2Ch] [rbp-24h]\n int j; // [rsp+30h] [rbp-20h]\n int v14; // [rsp+34h] [rbp-1Ch]\n int k; // [rsp+38h] [rbp-18h]\n int m; // [rsp+3Ch] [rbp-14h]\n int n; // [rsp+40h] [rbp-10h]\n int v18; // [rsp+44h] [rbp-Ch]\n _DWORD *v19; // [rsp+48h] [rbp-8h]\n\n v5 = a2;\n if ( a4 <= a2 )\n v5 = a4;\n v19 = malloc(4LL * v5);\n if ( v19 )\n {\n v11 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = 0; j < a4; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4LL * j + a3) )\n {\n v14 = 0;\n for ( k = 0; k < v11; ++k )\n {\n if ( v19[k] == *(_DWORD *)(4LL * i + a1) )\n {\n v14 = 1;\n break;\n }\n }\n if ( !v14 )\n {\n v7 = v11++;\n v19[v7] = *(_DWORD *)(4LL * i + a1);\n }\n break;\n }\n }\n }\n for ( m = 0; m < v11 - 1; ++m )\n {\n for ( n = m + 1; n < v11; ++n )\n {\n if ( v19[m] > v19[n] )\n {\n v18 = v19[m];\n v19[m] = v19[n];\n v19[n] = v18;\n }\n }\n }\n *a5 = v11;\n return v19;\n }\n else\n {\n *a5 = 0;\n return 0LL;\n }\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov [rbp+var_48], rdx\nmov [rbp+var_40], ecx\nmov [rbp+var_50], r8\nmov edx, [rbp+var_40]\nmov eax, [rbp+var_3C]\ncmp edx, eax\ncmovle eax, edx\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\ncmp [rbp+var_8], 0\njnz short loc_11FF\nmov rax, [rbp+var_50]\nmov dword ptr [rax], 0\nmov eax, 0\njmp locret_13DE\nloc_11FF:\nmov [rbp+var_28], 0\nmov [rbp+var_24], 0\njmp loc_12F9\nloc_1212:\nmov [rbp+var_20], 0\njmp loc_12E6\nloc_121E:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_20]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz loc_12E2\nmov [rbp+var_1C], 0\nmov [rbp+var_18], 0\njmp short loc_129F\nloc_1262:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_24]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_129B\nmov [rbp+var_1C], 1\njmp short loc_12A7\nloc_129B:\nadd [rbp+var_18], 1\nloc_129F:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_28]\njl short loc_1262\nloc_12A7:\ncmp [rbp+var_1C], 0\njnz short loc_12F4\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_28]\nlea edx, [rax+1]\nmov [rbp+var_28], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\njmp short loc_12F4\nloc_12E2:\nadd [rbp+var_20], 1\nloc_12E6:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_40]\njl loc_121E\njmp short loc_12F5\nloc_12F4:\nnop\nloc_12F5:\nadd [rbp+var_24], 1\nloc_12F9:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_3C]\njl loc_1212\nmov [rbp+var_14], 0\njmp loc_13C2\nloc_1311:\nmov eax, [rbp+var_14]\nadd eax, 1\nmov [rbp+var_10], eax\njmp loc_13B2\nloc_131F:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_13AE\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_C]\nmov [rdx], eax\nloc_13AE:\nadd [rbp+var_10], 1\nloc_13B2:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_28]\njl loc_131F\nadd [rbp+var_14], 1\nloc_13C2:\nmov eax, [rbp+var_28]\nsub eax, 1\ncmp [rbp+var_14], eax\njl loc_1311\nmov rax, [rbp+var_50]\nmov edx, [rbp+var_28]\nmov [rax], edx\nmov rax, [rbp+var_8]\nlocret_13DE:\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(__int64 a1, int a2, __int64 a3, int a4, _DWORD *a5)\n{\n int v5; // eax\n int v7; // eax\n int v11; // [rsp+28h] [rbp-28h]\n int i; // [rsp+2Ch] [rbp-24h]\n int j; // [rsp+30h] [rbp-20h]\n int v14; // [rsp+34h] [rbp-1Ch]\n int k; // [rsp+38h] [rbp-18h]\n int m; // [rsp+3Ch] [rbp-14h]\n int n; // [rsp+40h] [rbp-10h]\n int v18; // [rsp+44h] [rbp-Ch]\n _DWORD *v19; // [rsp+48h] [rbp-8h]\n\n v5 = a2;\n if ( a4 <= a2 )\n v5 = a4;\n v19 = malloc(4LL * v5);\n if ( v19 )\n {\n v11 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = 0; j < a4; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4LL * j + a3) )\n {\n v14 = 0;\n for ( k = 0; k < v11; ++k )\n {\n if ( v19[k] == *(_DWORD *)(4LL * i + a1) )\n {\n v14 = 1;\n break;\n }\n }\n if ( !v14 )\n {\n v7 = v11++;\n v19[v7] = *(_DWORD *)(4LL * i + a1);\n }\n break;\n }\n }\n }\n for ( m = 0; m < v11 - 1; ++m )\n {\n for ( n = m + 1; n < v11; ++n )\n {\n if ( v19[m] > v19[n] )\n {\n v18 = v19[m];\n v19[m] = v19[n];\n v19[n] = v18;\n }\n }\n }\n *a5 = v11;\n return v19;\n }\n else\n {\n *a5 = 0;\n return 0LL;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(long long a1, int a2, long long a3, int a4, uint32_t *a5) {\n int v5;\n int v7;\n int v11;\n int i;\n int j;\n int v14;\n int k;\n int m;\n int n;\n int v18;\n uint32_t *v19;\n v5 = a2;\n if (a4 <= a2) v5 = a4;\n v19 = malloc(4LL * v5);\n if (v19) {\n v11 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = 0; j < a4; ++j) {\n if (*(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4LL * j + a3)) {\n v14 = 0;\n for (k = 0; k < v11; ++k) {\n if (v19[k] == *(uint32_t *)(4LL * i + a1)) {\n v14 = 1;\n break;\n }\n }\n if (!v14) {\n v7 = v11++;\n v19[v7] = *(uint32_t *)(4LL * i + a1);\n }\n break;\n }\n }\n }\n for (m = 0; m < v11 - 1; ++m) {\n for (n = m + 1; n < v11; ++n) {\n if (v19[m] > v19[n]) {\n v18 = v19[m];\n v19[m] = v19[n];\n v19[n] = v18;\n }\n }\n }\n *a5 = v11;\n return v19;\n } else {\n *a5 = 0;\n return 0LL;\n }\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, long long a3, int a4, uint32_t *a5) {\n int v5;\n int v7;\n int v11;\n int i;\n int j;\n int v14;\n int k;\n int m;\n int n;\n int v18;\n uint32_t *v19;\n v5 = a2;\n if (a4 <= a2) v5 = a4;\n v19 = malloc(4LL * v5);\n if (v19) {\n v11 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = 0; j < a4; ++j) {\n if (*(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4LL * j + a3)) {\n v14 = 0;\n for (k = 0; k < v11; ++k) {\n if (v19[k] == *(uint32_t *)(4LL * i + a1)) {\n v14 = 1;\n break;\n }\n }\n if (!v14) {\n v7 = v11++;\n v19[v7] = *(uint32_t *)(4LL * i + a1);\n }\n break;\n }\n }\n }\n for (m = 0; m < v11 - 1; ++m) {\n for (n = m + 1; n < v11; ++n) {\n if (v19[m] > v19[n]) {\n v18 = v19[m];\n v19[m] = v19[n];\n v19[n] = v18;\n }\n }\n }\n *a5 = v11;\n return v19;\n } else {\n *a5 = 0;\n return 0LL;\n }\n}" + }, + { + "index": 2, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n// Function to find similar elements\n\n", + "func": "int* func0(int test_tup1[], int size1, int test_tup2[], int size2,\n int* res_size) {\n int* temp = (int*)malloc((size1 < size2 ? size1 : size2) * sizeof(int));\n if (!temp) {\n *res_size = 0;\n return NULL;\n }\n int count = 0;\n for (int i = 0; i < size1; i++) {\n for (int j = 0; j < size2; j++) {\n if (test_tup1[i] == test_tup2[j]) {\n int exists = 0;\n for (int k = 0; k < count; k++) {\n if (temp[k] == test_tup1[i]) {\n exists = 1;\n break;\n }\n }\n if (!exists) {\n temp[count++] = test_tup1[i];\n }\n break;\n }\n }\n }\n for (int i = 0; i < count - 1; i++) {\n for (int j = i + 1; j < count; j++) {\n if (temp[i] > temp[j]) {\n int swap = temp[i];\n temp[i] = temp[j];\n temp[j] = swap;\n }\n }\n }\n *res_size = count;\n return temp;\n}", + "test": "int main() {\n\n int res_size;\n\n int* res;\n\n\n\n // First assertion\n\n int test1_a[] = {3, 4, 5, 6};\n\n int test1_b[] = {5, 7, 4, 10};\n\n res = func0(test1_a, 4, test1_b, 4, &res_size);\n\n assert(res_size == 2);\n\n assert(res[0] == 4 && res[1] == 5);\n\n free(res);\n\n\n\n // Second assertion\n\n int test2_a[] = {1, 2, 3, 4};\n\n int test2_b[] = {5, 4, 3, 7};\n\n res = func0(test2_a, 4, test2_b, 4, &res_size);\n\n assert(res_size == 2);\n\n assert(res[0] == 3 && res[1] == 4);\n\n free(res);\n\n\n\n // Third assertion\n\n int test3_a[] = {11, 12, 14, 13};\n\n int test3_b[] = {17, 15, 14, 13};\n\n res = func0(test3_a, 4, test3_b, 4, &res_size);\n\n assert(res_size == 2);\n\n assert(res[0] == 13 && res[1] == 14);\n\n free(res);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%r14\nmov %esi,%r12d\nmov %rdx,%r13\nmov %ecx,%ebp\nmov %r8,%rbx\ncmp %esi,%ecx\nmov %esi,%edi\ncmovle %ecx,%edi\nmovslq %edi,%rdi\nshl $0x2,%rdi\ncallq 10b0 \ntest %rax,%rax\nje 1208 \ntest %r12d,%r12d\njle 12a5 \nmov %r14,%r9\nlea -0x1(%r12),%edx\nlea 0x4(%r14,%rdx,4),%r10\nmov %r13,%r11\nlea -0x1(%rbp),%edx\nlea 0x4(%r13,%rdx,4),%rsi\nmov $0x0,%r8d\nlea 0x4(%rax),%r12\njmp 1243 \nmovl $0x0,(%rbx)\njmpq 12ae \ntest %r8d,%r8d\njle 1230 \nmov %rax,%rdx\nlea -0x1(%r8),%edi\nlea (%r12,%rdi,4),%rdi\ncmp (%rdx),%ecx\nje 123a \nadd $0x4,%rdx\ncmp %rdi,%rdx\njne 1223 \nmovslq %r8d,%rdx\nmov %ecx,(%rax,%rdx,4)\nlea 0x1(%r8),%r8d\nadd $0x4,%r9\ncmp %r10,%r9\nje 125c \ntest %ebp,%ebp\njle 123a \nmov (%r9),%ecx\nmov %r11,%rdx\ncmp (%rdx),%ecx\nje 1213 \nadd $0x4,%rdx\ncmp %rsi,%rdx\njne 124d \njmp 123a \ncmp $0x1,%r8d\njle 12ab \nmov %rax,%rdi\nlea -0x2(%r8),%r10d\nadd $0x2,%r10\nmov $0x1,%r9d\njmp 129b \nadd $0x1,%rdx\ncmp %edx,%r8d\njle 128e \nmov (%rdi),%ecx\nmov (%rax,%rdx,4),%esi\ncmp %esi,%ecx\njle 1275 \nmov %esi,(%rdi)\nmov %ecx,(%rax,%rdx,4)\njmp 1275 \nadd $0x1,%r9\nadd $0x4,%rdi\ncmp %r10,%r9\nje 12ab \ncmp %r9d,%r8d\njle 128e \nmov %r9,%rdx\njmp 127e \nmov $0x0,%r8d\nmov %r8d,(%rbx)\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r14, rdi\nmov r13d, esi\nmov r12, rdx\nmov ebp, ecx\nmov rbx, r8\ncmp ecx, esi\nmov edi, esi\ncmovle edi, ecx\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov r10, rax\ntest rax, rax\njz loc_12BE\ntest r13d, r13d\njle loc_12A9\nmov rdi, r14\nmovsxd r13, r13d\nlea r8, [r14+r13*4]\nmovsxd rax, ebp\nlea rcx, [r12+rax*4]\nmov r9d, 0\njmp short loc_1234\nloc_1204:\ntest r9d, r9d\njle short loc_1220\nmov rax, r10\nmovsxd rsi, r9d\nlea rsi, [r10+rsi*4]\nloc_1213:\ncmp edx, [rax]\njz short loc_122B\nadd rax, 4\ncmp rax, rsi\njnz short loc_1213\nloc_1220:\nmovsxd rax, r9d\nmov [r10+rax*4], edx\nlea r9d, [r9+1]\nloc_122B:\nadd rdi, 4\ncmp rdi, r8\njz short loc_124C\nloc_1234:\ntest ebp, ebp\njle short loc_122B\nmov edx, [rdi]\nmov rax, r12\nloc_123D:\ncmp edx, [rax]\njz short loc_1204\nadd rax, 4\ncmp rax, rcx\njnz short loc_123D\njmp short loc_122B\nloc_124C:\ncmp r9d, 1\njle short loc_12AF\nlea rsi, [r10+4]\nmov r11d, r9d\nmov r8d, 1\nlea r12d, [r9-1]\nlea rbp, [r10+8]\njmp short loc_128F\nloc_1269:\nadd rax, 4\ncmp rax, rdi\njz short loc_1282\nloc_1272:\nmov edx, [rsi-4]\nmov ecx, [rax]\ncmp edx, ecx\njle short loc_1269\nmov [rsi-4], ecx\nmov [rax], edx\njmp short loc_1269\nloc_1282:\nadd r8, 1\nadd rsi, 4\ncmp r8, r11\njz short loc_12AF\nloc_128F:\ncmp r9d, r8d\njle short loc_1282\nmov eax, r12d\nsub eax, r8d\nlea rax, [r8+rax-1]\nlea rdi, [rbp+rax*4+0]\nmov rax, rsi\njmp short loc_1272\nloc_12A9:\nmov r9d, 0\nloc_12AF:\nmov [rbx], r9d\nmov rax, r10\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_12BE:\nmov r9d, 0\njmp short loc_12AF", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2, _DWORD *a3, int a4, int *a5)\n{\n int v9; // edi\n _DWORD *v10; // r10\n int *v11; // rdi\n int v12; // r9d\n _DWORD *v13; // rax\n int v14; // edx\n _DWORD *v15; // rax\n _DWORD *v16; // rsi\n __int64 i; // r8\n _DWORD *v18; // rax\n int v19; // edx\n\n v9 = a2;\n if ( a4 <= a2 )\n v9 = a4;\n v10 = malloc(4LL * v9);\n if ( v10 )\n {\n if ( a2 <= 0 )\n {\n v12 = 0;\n }\n else\n {\n v11 = a1;\n v12 = 0;\n do\n {\n if ( a4 > 0 )\n {\n v14 = *v11;\n v15 = a3;\n while ( v14 != *v15 )\n {\n if ( ++v15 == &a3[a4] )\n goto LABEL_11;\n }\n if ( v12 <= 0 )\n {\nLABEL_10:\n v10[v12++] = v14;\n }\n else\n {\n v13 = v10;\n while ( v14 != *v13 )\n {\n if ( ++v13 == &v10[v12] )\n goto LABEL_10;\n }\n }\n }\nLABEL_11:\n ++v11;\n }\n while ( v11 != &a1[a2] );\n if ( v12 > 1 )\n {\n v16 = v10 + 1;\n for ( i = 1LL; i != v12; ++i )\n {\n if ( v12 > (int)i )\n {\n v18 = v16;\n do\n {\n v19 = *(v16 - 1);\n if ( v19 > *v18 )\n {\n *(v16 - 1) = *v18;\n *v18 = v19;\n }\n ++v18;\n }\n while ( v18 != &v10[i + 1 + (unsigned int)(v12 - 1 - i)] );\n }\n ++v16;\n }\n }\n }\n }\n else\n {\n v12 = 0;\n }\n *a5 = v12;\n return v10;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r14, rdi\nmov r13d, esi\nmov r12, rdx\nmov ebp, ecx\nmov rbx, r8\ncmp ecx, esi\nmov edi, esi\ncmovle edi, ecx\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov r10, rax\ntest rax, rax\njz loc_12BE\ntest r13d, r13d\njle loc_12A9\nmov rdi, r14\nmovsxd r13, r13d\nlea r8, [r14+r13*4]\nmovsxd rax, ebp\nlea rcx, [r12+rax*4]\nmov r9d, 0\njmp short loc_1234\nloc_1204:\ntest r9d, r9d\njle short loc_1220\nmov rax, r10\nmovsxd rsi, r9d\nlea rsi, [r10+rsi*4]\nloc_1213:\ncmp edx, [rax]\njz short loc_122B\nadd rax, 4\ncmp rax, rsi\njnz short loc_1213\nloc_1220:\nmovsxd rax, r9d\nmov [r10+rax*4], edx\nlea r9d, [r9+1]\nloc_122B:\nadd rdi, 4\ncmp rdi, r8\njz short loc_124C\nloc_1234:\ntest ebp, ebp\njle short loc_122B\nmov edx, [rdi]\nmov rax, r12\nloc_123D:\ncmp edx, [rax]\njz short loc_1204\nadd rax, 4\ncmp rax, rcx\njnz short loc_123D\njmp short loc_122B\nloc_124C:\ncmp r9d, 1\njle short loc_12AF\nlea rsi, [r10+4]\nmov r11d, r9d\nmov r8d, 1\nlea r12d, [r9-1]\nlea rbp, [r10+8]\njmp short loc_128F\nloc_1269:\nadd rax, 4\ncmp rax, rdi\njz short loc_1282\nloc_1272:\nmov edx, [rsi-4]\nmov ecx, [rax]\ncmp edx, ecx\njle short loc_1269\nmov [rsi-4], ecx\nmov [rax], edx\njmp short loc_1269\nloc_1282:\nadd r8, 1\nadd rsi, 4\ncmp r8, r11\njz short loc_12AF\nloc_128F:\ncmp r9d, r8d\njle short loc_1282\nmov eax, r12d\nsub eax, r8d\nlea rax, [r8+rax-1]\nlea rdi, [rbp+rax*4+0]\nmov rax, rsi\njmp short loc_1272\nloc_12A9:\nmov r9d, 0\nloc_12AF:\nmov [rbx], r9d\nmov rax, r10\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_12BE:\nmov r9d, 0\njmp short loc_12AF", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(int *a1, int a2, _DWORD *a3, int a4, int *a5)\n{\n int v9; // edi\n _DWORD *v10; // r10\n int *v11; // rdi\n int v12; // r9d\n _DWORD *v13; // rax\n int v14; // edx\n _DWORD *v15; // rax\n _DWORD *v16; // rsi\n __int64 i; // r8\n _DWORD *v18; // rax\n int v19; // edx\n\n v9 = a2;\n if ( a4 <= a2 )\n v9 = a4;\n v10 = malloc(4LL * v9);\n if ( v10 )\n {\n if ( a2 <= 0 )\n {\n v12 = 0;\n }\n else\n {\n v11 = a1;\n v12 = 0;\n do\n {\n if ( a4 > 0 )\n {\n v14 = *v11;\n v15 = a3;\n while ( v14 != *v15 )\n {\n if ( ++v15 == &a3[a4] )\n goto LABEL_11;\n }\n if ( v12 <= 0 )\n {\nLABEL_10:\n v10[v12++] = v14;\n }\n else\n {\n v13 = v10;\n while ( v14 != *v13 )\n {\n if ( ++v13 == &v10[v12] )\n goto LABEL_10;\n }\n }\n }\nLABEL_11:\n ++v11;\n }\n while ( v11 != &a1[a2] );\n if ( v12 > 1 )\n {\n v16 = v10 + 1;\n for ( i = 1LL; i != v12; ++i )\n {\n if ( v12 > (int)i )\n {\n v18 = v16;\n do\n {\n v19 = *(v16 - 1);\n if ( v19 > *v18 )\n {\n *(v16 - 1) = *v18;\n *v18 = v19;\n }\n ++v18;\n }\n while ( v18 != &v10[i + 1 + (unsigned int)(v12 - 1 - i)] );\n }\n ++v16;\n }\n }\n }\n }\n else\n {\n v12 = 0;\n }\n *a5 = v12;\n return v10;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(int *a1, int a2, uint32_t *a3, int a4, int *a5) {\n int v9;\n uint32_t *v10;\n int *v11;\n int v12;\n uint32_t *v13;\n int v14;\n uint32_t *v15;\n uint32_t *v16;\n long long i;\n uint32_t *v18;\n int v19;\n v9 = a2;\n if (a4 <= a2) v9 = a4;\n v10 = malloc(4LL * v9);\n if (v10) {\n if (a2 <= 0) {\n v12 = 0;\n } else {\n v11 = a1;\n v12 = 0;\n do {\n if (a4 > 0) {\n v14 = *v11;\n v15 = a3;\n while (v14 != *v15) {\n if (++v15 == &a3[a4]) goto LABEL_11;\n }\n if (v12 <= 0) {\n LABEL_10:\n v10[v12++] = v14;\n } else {\n v13 = v10;\n while (v14 != *v13) {\n if (++v13 == &v10[v12]) goto LABEL_10;\n }\n }\n }\n LABEL_11:\n ++v11;\n } while (v11 != &a1[a2]);\n if (v12 > 1) {\n v16 = v10 + 1;\n for (i = 1LL; i != v12; ++i) {\n if (v12 > (int)i) {\n v18 = v16;\n do {\n v19 = *(v16 - 1);\n if (v19 > *v18) {\n *(v16 - 1) = *v18;\n *v18 = v19;\n }\n ++v18;\n } while (v18 != &v10[i + 1 + (unsigned int)(v12 - 1 - i)]);\n }\n ++v16;\n }\n }\n }\n } else {\n v12 = 0;\n }\n *a5 = v12;\n return v10;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2, uint32_t *a3, int a4, int *a5) {\n int v9;\n uint32_t *v10;\n int *v11;\n int v12;\n uint32_t *v13;\n int v14;\n uint32_t *v15;\n uint32_t *v16;\n long long i;\n uint32_t *v18;\n int v19;\n v9 = a2;\n if (a4 <= a2) v9 = a4;\n v10 = malloc(4LL * v9);\n if (v10) {\n if (a2 <= 0) {\n v12 = 0;\n } else {\n v11 = a1;\n v12 = 0;\n do {\n if (a4 > 0) {\n v14 = *v11;\n v15 = a3;\n while (v14 != *v15) {\n if (++v15 == &a3[a4]) goto LABEL_11;\n }\n if (v12 <= 0) {\n LABEL_10:\n v10[v12++] = v14;\n } else {\n v13 = v10;\n while (v14 != *v13) {\n if (++v13 == &v10[v12]) goto LABEL_10;\n }\n }\n }\n LABEL_11:\n ++v11;\n } while (v11 != &a1[a2]);\n if (v12 > 1) {\n v16 = v10 + 1;\n for (i = 1LL; i != v12; ++i) {\n if (v12 > (int)i) {\n v18 = v16;\n do {\n v19 = *(v16 - 1);\n if (v19 > *v18) {\n *(v16 - 1) = *v18;\n *v18 = v19;\n }\n ++v18;\n } while (v18 != &v10[i + 1 + (unsigned int)(v12 - 1 - i)]);\n }\n ++v16;\n }\n }\n }\n } else {\n v12 = 0;\n }\n *a5 = v12;\n return v10;\n}" + }, + { + "index": 2, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n// Function to find similar elements\n\n", + "func": "int* func0(int test_tup1[], int size1, int test_tup2[], int size2,\n int* res_size) {\n int* temp = (int*)malloc((size1 < size2 ? size1 : size2) * sizeof(int));\n if (!temp) {\n *res_size = 0;\n return NULL;\n }\n int count = 0;\n for (int i = 0; i < size1; i++) {\n for (int j = 0; j < size2; j++) {\n if (test_tup1[i] == test_tup2[j]) {\n int exists = 0;\n for (int k = 0; k < count; k++) {\n if (temp[k] == test_tup1[i]) {\n exists = 1;\n break;\n }\n }\n if (!exists) {\n temp[count++] = test_tup1[i];\n }\n break;\n }\n }\n }\n for (int i = 0; i < count - 1; i++) {\n for (int j = i + 1; j < count; j++) {\n if (temp[i] > temp[j]) {\n int swap = temp[i];\n temp[i] = temp[j];\n temp[j] = swap;\n }\n }\n }\n *res_size = count;\n return temp;\n}", + "test": "int main() {\n\n int res_size;\n\n int* res;\n\n\n\n // First assertion\n\n int test1_a[] = {3, 4, 5, 6};\n\n int test1_b[] = {5, 7, 4, 10};\n\n res = func0(test1_a, 4, test1_b, 4, &res_size);\n\n assert(res_size == 2);\n\n assert(res[0] == 4 && res[1] == 5);\n\n free(res);\n\n\n\n // Second assertion\n\n int test2_a[] = {1, 2, 3, 4};\n\n int test2_b[] = {5, 4, 3, 7};\n\n res = func0(test2_a, 4, test2_b, 4, &res_size);\n\n assert(res_size == 2);\n\n assert(res[0] == 3 && res[1] == 4);\n\n free(res);\n\n\n\n // Third assertion\n\n int test3_a[] = {11, 12, 14, 13};\n\n int test3_b[] = {17, 15, 14, 13};\n\n res = func0(test3_a, 4, test3_b, 4, &res_size);\n\n assert(res_size == 2);\n\n assert(res[0] == 13 && res[1] == 14);\n\n free(res);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\nmov %esi,%r14d\npush %r13\nmovslq %ecx,%r13\npush %r12\ncmp %esi,%r13d\nmov %rdx,%r12\npush %rbp\nmov %rdi,%rbp\nmovslq %esi,%rdi\npush %rbx\ncmovle %r13,%rdi\nmov %r8,%rbx\nshl $0x2,%rdi\ncallq 10b0 \ntest %rax,%rax\nje 152e \ntest %r14d,%r14d\njle 1529 \nlea -0x1(%r14),%edx\nlea -0x1(%r13),%ecx\nmov %rbp,%r8\nxor %r9d,%r9d\nlea 0x4(%rbp,%rdx,4),%rdx\nlea 0x4(%r12,%rcx,4),%r10\nlea 0x4(%rax),%rbp\nnopl 0x0(%rax)\ntest %r13d,%r13d\njle 14ad \nmov (%r8),%edi\nmov %r12,%rsi\njmp 1489 \nnopl (%rax)\nadd $0x4,%rsi\ncmp %r10,%rsi\nje 14ad \ncmp (%rsi),%edi\njne 1480 \ntest %r9d,%r9d\nje 1510 \nlea -0x1(%r9),%ecx\nmov %rax,%rsi\nlea 0x0(%rbp,%rcx,4),%r11\njmp 14a9 \nadd $0x4,%rsi\ncmp %r11,%rsi\nje 1510 \ncmp (%rsi),%edi\njne 14a0 \nadd $0x4,%r8\ncmp %rdx,%r8\njne 1470 \ncmp $0x1,%r9d\njle 1504 \nlea -0x2(%r9),%r8d\nmov %rax,%rdi\nmov $0x1,%r10d\nadd $0x2,%r8\nnopl (%rax)\ncmp %r10d,%r9d\njle 14f7 \nmov %r10,%rdx\nnopl 0x0(%rax,%rax,1)\nmov (%rdi),%ecx\nmov (%rax,%rdx,4),%esi\ncmp %esi,%ecx\njle 14ee \nmov %esi,(%rdi)\nmov %ecx,(%rax,%rdx,4)\nadd $0x1,%rdx\ncmp %edx,%r9d\njg 14e0 \nadd $0x1,%r10\nadd $0x4,%rdi\ncmp %r8,%r10\njne 14d0 \nmov %r9d,(%rbx)\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nmovslq %r9d,%rcx\nadd $0x4,%r8\nadd $0x1,%r9d\nmov %edi,(%rax,%rcx,4)\ncmp %rdx,%r8\njne 1470 \njmp 14b6 \nxor %r9d,%r9d\njmp 1504 \nmovl $0x0,(%rbx)\njmp 1507 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\nmovsxd r14, ecx\npush r13\nmovsxd r13, esi\npush r12\ncmp r14d, r13d\nmov r12, rdx\npush rbp\nmov rbp, rdi\nmovsxd rdi, r13d\npush rbx\ncmovle rdi, r14\nmov rbx, r8\nshl rdi, 2; size\ncall _malloc\nmov r8, rax\ntest rax, rax\njz loc_150F\ntest r13d, r13d\njle loc_150F\nmovsxd rax, r14d\nmov rdi, rbp\nlea r11, [rbp+r13*4+0]\nlea rcx, [r12+rax*4]\nloc_1412:\ntest r14d, r14d\njle loc_1502\nxor r10d, r10d\nxchg ax, ax\nloc_1420:\nmov edx, [rdi]\nmov rax, r12\njmp short loc_1439\nloc_1430:\nadd rax, 4\ncmp rax, rcx\njz short loc_1469\nloc_1439:\ncmp edx, [rax]\njnz short loc_1430\nmovsxd r9, r10d\ntest r10d, r10d\njle loc_14E8\nmovsxd r9, r10d\nmov rax, r8\nlea rsi, [r8+r9*4]\njmp short loc_1465\nloc_1458:\nadd rax, 4\ncmp rax, rsi\njz loc_14E8\nloc_1465:\ncmp edx, [rax]\njnz short loc_1458\nloc_1469:\nadd rdi, 4\ncmp rdi, r11\njnz short loc_1420\nloc_1472:\ncmp r10d, 1\njle short loc_14D4\nlea rsi, [r8+4]\nmov r11d, r10d\nmov r9d, 1\nlea r12d, [r10-1]\nlea rbp, [r8+8]\nnop dword ptr [rax]\nloc_1490:\ncmp r10d, r9d\njle short loc_14C7\nmov eax, r12d\nsub eax, r9d\nlea rax, [r9+rax-1]\nlea rdi, [rbp+rax*4+0]\nmov rax, rsi\nnop dword ptr [rax+rax+00000000h]\nloc_14B0:\nmov edx, [rsi-4]\nmov ecx, [rax]\ncmp edx, ecx\njle short loc_14BE\nmov [rsi-4], ecx\nmov [rax], edx\nloc_14BE:\nadd rax, 4\ncmp rax, rdi\njnz short loc_14B0\nloc_14C7:\nadd r9, 1\nadd rsi, 4\ncmp r9, r11\njnz short loc_1490\nloc_14D4:\nmov [rbx], r10d\nmov rax, r8\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_14E8:\nadd rdi, 4\nmov [r8+r9*4], edx\nadd r10d, 1\ncmp rdi, r11\njnz loc_1420\njmp loc_1472\nloc_1502:\nadd rdi, 4\ncmp rdi, r11\njnz loc_1412\nloc_150F:\nxor r10d, r10d\nmov rax, r8\nmov [rbx], r10d\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2, _DWORD *a3, int a4, int *a5)\n{\n __int64 v8; // rdi\n _DWORD *v10; // r8\n int *v11; // rdi\n int *v12; // r11\n int v13; // r10d\n int v14; // edx\n _DWORD *v15; // rax\n __int64 v16; // r9\n _DWORD *v17; // rax\n _DWORD *v18; // rsi\n __int64 i; // r9\n _DWORD *v20; // rax\n int v21; // edx\n _DWORD *result; // rax\n\n v8 = a2;\n if ( a4 <= a2 )\n v8 = a4;\n v10 = malloc(4 * v8);\n if ( v10 && a2 > 0 )\n {\n v11 = a1;\n v12 = &a1[a2];\n while ( a4 <= 0 )\n {\n if ( ++v11 == v12 )\n goto LABEL_28;\n }\n v13 = 0;\n while ( 2 )\n {\n while ( 2 )\n {\n v14 = *v11;\n v15 = a3;\n while ( v14 != *v15 )\n {\n if ( ++v15 == &a3[a4] )\n goto LABEL_15;\n }\n v16 = v13;\n if ( v13 > 0 )\n {\n v16 = v13;\n v17 = v10;\n while ( v14 != *v17 )\n {\n if ( ++v17 == &v10[v13] )\n goto LABEL_25;\n }\nLABEL_15:\n if ( ++v11 != v12 )\n continue;\n goto LABEL_16;\n }\n break;\n }\nLABEL_25:\n ++v11;\n v10[v16] = v14;\n ++v13;\n if ( v11 != v12 )\n continue;\n break;\n }\nLABEL_16:\n if ( v13 > 1 )\n {\n v18 = v10 + 1;\n for ( i = 1LL; i != v13; ++i )\n {\n if ( v13 > (int)i )\n {\n v20 = v18;\n do\n {\n v21 = *(v18 - 1);\n if ( v21 > *v20 )\n {\n *(v18 - 1) = *v20;\n *v20 = v21;\n }\n ++v20;\n }\n while ( v20 != &v10[i + 1 + (unsigned int)(v13 - 1 - i)] );\n }\n ++v18;\n }\n }\n *a5 = v13;\n return v10;\n }\n else\n {\nLABEL_28:\n result = v10;\n *a5 = 0;\n }\n return result;\n}", + "ida_strip_asm": "sub_13C0:\nendbr64\npush r14\nmovsxd r14, ecx\npush r13\nmovsxd r13, esi\npush r12\ncmp r14d, r13d\nmov r12, rdx\npush rbp\nmov rbp, rdi\nmovsxd rdi, r13d\npush rbx\ncmovle rdi, r14\nmov rbx, r8\nshl rdi, 2; size\ncall _malloc\nmov r8, rax\ntest rax, rax\njz loc_150F\ntest r13d, r13d\njle loc_150F\nmovsxd rax, r14d\nmov rdi, rbp\nlea r11, [rbp+r13*4+0]\nlea rcx, [r12+rax*4]\nloc_1412:\ntest r14d, r14d\njle loc_1502\nxor r10d, r10d\nxchg ax, ax\nloc_1420:\nmov edx, [rdi]\nmov rax, r12\njmp short loc_1439\nloc_1430:\nadd rax, 4\ncmp rax, rcx\njz short loc_1469\nloc_1439:\ncmp edx, [rax]\njnz short loc_1430\nmovsxd r9, r10d\ntest r10d, r10d\njle loc_14E8\nmovsxd r9, r10d\nmov rax, r8\nlea rsi, [r8+r9*4]\njmp short loc_1465\nloc_1458:\nadd rax, 4\ncmp rax, rsi\njz loc_14E8\nloc_1465:\ncmp edx, [rax]\njnz short loc_1458\nloc_1469:\nadd rdi, 4\ncmp rdi, r11\njnz short loc_1420\nloc_1472:\ncmp r10d, 1\njle short loc_14D4\nlea rsi, [r8+4]\nmov r11d, r10d\nmov r9d, 1\nlea r12d, [r10-1]\nlea rbp, [r8+8]\nnop dword ptr [rax]\nloc_1490:\ncmp r10d, r9d\njle short loc_14C7\nmov eax, r12d\nsub eax, r9d\nlea rax, [r9+rax-1]\nlea rdi, [rbp+rax*4+0]\nmov rax, rsi\nnop dword ptr [rax+rax+00000000h]\nloc_14B0:\nmov edx, [rsi-4]\nmov ecx, [rax]\ncmp edx, ecx\njle short loc_14BE\nmov [rsi-4], ecx\nmov [rax], edx\nloc_14BE:\nadd rax, 4\ncmp rax, rdi\njnz short loc_14B0\nloc_14C7:\nadd r9, 1\nadd rsi, 4\ncmp r9, r11\njnz short loc_1490\nloc_14D4:\nmov [rbx], r10d\nmov rax, r8\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_14E8:\nadd rdi, 4\nmov [r8+r9*4], edx\nadd r10d, 1\ncmp rdi, r11\njnz loc_1420\njmp loc_1472\nloc_1502:\nadd rdi, 4\ncmp rdi, r11\njnz loc_1412\nloc_150F:\nxor r10d, r10d\nmov rax, r8\nmov [rbx], r10d\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_13C0(int *a1, int a2, _DWORD *a3, int a4, int *a5)\n{\n __int64 v8; // rdi\n _DWORD *v10; // r8\n int *v11; // rdi\n int *v12; // r11\n int v13; // r10d\n int v14; // edx\n _DWORD *v15; // rax\n __int64 v16; // r9\n _DWORD *v17; // rax\n _DWORD *v18; // rsi\n __int64 i; // r9\n _DWORD *v20; // rax\n int v21; // edx\n _DWORD *result; // rax\n\n v8 = a2;\n if ( a4 <= a2 )\n v8 = a4;\n v10 = malloc(4 * v8);\n if ( v10 && a2 > 0 )\n {\n v11 = a1;\n v12 = &a1[a2];\n while ( a4 <= 0 )\n {\n if ( ++v11 == v12 )\n goto LABEL_28;\n }\n v13 = 0;\n while ( 2 )\n {\n while ( 2 )\n {\n v14 = *v11;\n v15 = a3;\n while ( v14 != *v15 )\n {\n if ( ++v15 == &a3[a4] )\n goto LABEL_15;\n }\n v16 = v13;\n if ( v13 > 0 )\n {\n v16 = v13;\n v17 = v10;\n while ( v14 != *v17 )\n {\n if ( ++v17 == &v10[v13] )\n goto LABEL_25;\n }\nLABEL_15:\n if ( ++v11 != v12 )\n continue;\n goto LABEL_16;\n }\n break;\n }\nLABEL_25:\n ++v11;\n v10[v16] = v14;\n ++v13;\n if ( v11 != v12 )\n continue;\n break;\n }\nLABEL_16:\n if ( v13 > 1 )\n {\n v18 = v10 + 1;\n for ( i = 1LL; i != v13; ++i )\n {\n if ( v13 > (int)i )\n {\n v20 = v18;\n do\n {\n v21 = *(v18 - 1);\n if ( v21 > *v20 )\n {\n *(v18 - 1) = *v20;\n *v20 = v21;\n }\n ++v20;\n }\n while ( v20 != &v10[i + 1 + (unsigned int)(v13 - 1 - i)] );\n }\n ++v18;\n }\n }\n *a5 = v13;\n return v10;\n }\n else\n {\nLABEL_28:\n result = v10;\n *a5 = 0;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_13C0(int *a1, int a2, uint32_t *a3, int a4, int *a5) {\n long long v8;\n uint32_t *v10;\n int *v11;\n int *v12;\n int v13;\n int v14;\n uint32_t *v15;\n long long v16;\n uint32_t *v17;\n uint32_t *v18;\n long long i;\n uint32_t *v20;\n int v21;\n uint32_t *result;\n v8 = a2;\n if (a4 <= a2) v8 = a4;\n v10 = malloc(4 * v8);\n if (v10 && a2 > 0) {\n v11 = a1;\n v12 = &a1[a2];\n while (a4 <= 0) {\n if (++v11 == v12) goto LABEL_28;\n }\n v13 = 0;\n while (2) {\n while (2) {\n v14 = *v11;\n v15 = a3;\n while (v14 != *v15) {\n if (++v15 == &a3[a4]) goto LABEL_15;\n }\n v16 = v13;\n if (v13 > 0) {\n v16 = v13;\n v17 = v10;\n while (v14 != *v17) {\n if (++v17 == &v10[v13]) goto LABEL_25;\n }\n LABEL_15:\n if (++v11 != v12) continue;\n goto LABEL_16;\n }\n break;\n }\n LABEL_25:\n ++v11;\n v10[v16] = v14;\n ++v13;\n if (v11 != v12) continue;\n break;\n }\n LABEL_16:\n if (v13 > 1) {\n v18 = v10 + 1;\n for (i = 1LL; i != v13; ++i) {\n if (v13 > (int)i) {\n v20 = v18;\n do {\n v21 = *(v18 - 1);\n if (v21 > *v20) {\n *(v18 - 1) = *v20;\n *v20 = v21;\n }\n ++v20;\n } while (v20 != &v10[i + 1 + (unsigned int)(v13 - 1 - i)]);\n }\n ++v18;\n }\n }\n *a5 = v13;\n return v10;\n } else {\n LABEL_28:\n result = v10;\n *a5 = 0;\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2, uint32_t *a3, int a4, int *a5) {\n long long v8;\n uint32_t *v10;\n int *v11;\n int *v12;\n int v13;\n int v14;\n uint32_t *v15;\n long long v16;\n uint32_t *v17;\n uint32_t *v18;\n long long i;\n uint32_t *v20;\n int v21;\n uint32_t *result;\n v8 = a2;\n if (a4 <= a2) v8 = a4;\n v10 = malloc(4 * v8);\n if (v10 && a2 > 0) {\n v11 = a1;\n v12 = &a1[a2];\n while (a4 <= 0) {\n if (++v11 == v12) goto LABEL_28;\n }\n v13 = 0;\n while (2) {\n while (2) {\n v14 = *v11;\n v15 = a3;\n while (v14 != *v15) {\n if (++v15 == &a3[a4]) goto LABEL_15;\n }\n v16 = v13;\n if (v13 > 0) {\n v16 = v13;\n v17 = v10;\n while (v14 != *v17) {\n if (++v17 == &v10[v13]) goto LABEL_25;\n }\n LABEL_15:\n if (++v11 != v12) continue;\n goto LABEL_16;\n }\n break;\n }\n LABEL_25:\n ++v11;\n v10[v16] = v14;\n ++v13;\n if (v11 != v12) continue;\n break;\n }\n LABEL_16:\n if (v13 > 1) {\n v18 = v10 + 1;\n for (i = 1LL; i != v13; ++i) {\n if (v13 > (int)i) {\n v20 = v18;\n do {\n v21 = *(v18 - 1);\n if (v21 > *v20) {\n *(v18 - 1) = *v20;\n *v20 = v21;\n }\n ++v20;\n } while (v20 != &v10[i + 1 + (unsigned int)(v13 - 1 - i)]);\n }\n ++v18;\n }\n }\n *a5 = v13;\n return v10;\n } else {\n LABEL_28:\n result = v10;\n *a5 = 0;\n }\n return result;\n}" + }, + { + "index": 2, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n// Function to find similar elements\n\n", + "func": "int* func0(int test_tup1[], int size1, int test_tup2[], int size2,\n int* res_size) {\n int* temp = (int*)malloc((size1 < size2 ? size1 : size2) * sizeof(int));\n if (!temp) {\n *res_size = 0;\n return NULL;\n }\n int count = 0;\n for (int i = 0; i < size1; i++) {\n for (int j = 0; j < size2; j++) {\n if (test_tup1[i] == test_tup2[j]) {\n int exists = 0;\n for (int k = 0; k < count; k++) {\n if (temp[k] == test_tup1[i]) {\n exists = 1;\n break;\n }\n }\n if (!exists) {\n temp[count++] = test_tup1[i];\n }\n break;\n }\n }\n }\n for (int i = 0; i < count - 1; i++) {\n for (int j = i + 1; j < count; j++) {\n if (temp[i] > temp[j]) {\n int swap = temp[i];\n temp[i] = temp[j];\n temp[j] = swap;\n }\n }\n }\n *res_size = count;\n return temp;\n}", + "test": "int main() {\n\n int res_size;\n\n int* res;\n\n\n\n // First assertion\n\n int test1_a[] = {3, 4, 5, 6};\n\n int test1_b[] = {5, 7, 4, 10};\n\n res = func0(test1_a, 4, test1_b, 4, &res_size);\n\n assert(res_size == 2);\n\n assert(res[0] == 4 && res[1] == 5);\n\n free(res);\n\n\n\n // Second assertion\n\n int test2_a[] = {1, 2, 3, 4};\n\n int test2_b[] = {5, 4, 3, 7};\n\n res = func0(test2_a, 4, test2_b, 4, &res_size);\n\n assert(res_size == 2);\n\n assert(res[0] == 3 && res[1] == 4);\n\n free(res);\n\n\n\n // Third assertion\n\n int test3_a[] = {11, 12, 14, 13};\n\n int test3_b[] = {17, 15, 14, 13};\n\n res = func0(test3_a, 4, test3_b, 4, &res_size);\n\n assert(res_size == 2);\n\n assert(res[0] == 13 && res[1] == 14);\n\n free(res);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\nmov %esi,%r14d\npush %r13\nmovslq %ecx,%r13\npush %r12\ncmp %esi,%r13d\nmov %rdx,%r12\npush %rbp\nmov %rdi,%rbp\nmovslq %esi,%rdi\npush %rbx\ncmovle %r13,%rdi\nmov %r8,%rbx\nshl $0x2,%rdi\ncallq 10b0 \ntest %rax,%rax\nje 14de \ntest %r14d,%r14d\njle 14d9 \nlea -0x1(%r14),%edx\nlea -0x1(%r13),%ecx\nmov %rbp,%r8\nxor %r9d,%r9d\nlea 0x4(%rbp,%rdx,4),%rdx\nlea 0x4(%r12,%rcx,4),%r10\nlea 0x4(%rax),%rbp\nnopl 0x0(%rax)\ntest %r13d,%r13d\njle 145d \nmov (%r8),%edi\nmov %r12,%rsi\njmp 1439 \nnopl (%rax)\nadd $0x4,%rsi\ncmp %r10,%rsi\nje 145d \ncmp (%rsi),%edi\njne 1430 \ntest %r9d,%r9d\nje 14c0 \nlea -0x1(%r9),%ecx\nmov %rax,%rsi\nlea 0x0(%rbp,%rcx,4),%r11\njmp 1459 \nadd $0x4,%rsi\ncmp %r11,%rsi\nje 14c0 \ncmp (%rsi),%edi\njne 1450 \nadd $0x4,%r8\ncmp %rdx,%r8\njne 1420 \ncmp $0x1,%r9d\njle 14b4 \nlea -0x2(%r9),%r8d\nmov %rax,%rdi\nmov $0x1,%r10d\nadd $0x2,%r8\nnopl (%rax)\ncmp %r10d,%r9d\njle 14a7 \nmov %r10,%rdx\nnopl 0x0(%rax,%rax,1)\nmov (%rdi),%ecx\nmov (%rax,%rdx,4),%esi\ncmp %esi,%ecx\njle 149e \nmov %esi,(%rdi)\nmov %ecx,(%rax,%rdx,4)\nadd $0x1,%rdx\ncmp %edx,%r9d\njg 1490 \nadd $0x1,%r10\nadd $0x4,%rdi\ncmp %r10,%r8\njne 1480 \nmov %r9d,(%rbx)\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nmovslq %r9d,%rcx\nadd $0x4,%r8\nadd $0x1,%r9d\nmov %edi,(%rax,%rcx,4)\ncmp %rdx,%r8\njne 1420 \njmp 1466 \nxor %r9d,%r9d\njmp 14b4 \nmovl $0x0,(%rbx)\njmp 14b7 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\nmovsxd r14, ecx\npush r13\nmovsxd r13, esi\npush r12\ncmp r14d, r13d\nmov r12, rdx\npush rbp\nmov rbp, rdi\nmovsxd rdi, r13d\npush rbx\ncmovle rdi, r14\nmov rbx, r8\nshl rdi, 2; size\ncall _malloc\nmov r8, rax\ntest rax, rax\njz loc_150F\ntest r13d, r13d\njle loc_150F\nmovsxd rax, r14d\nmov rdi, rbp\nlea r11, [rbp+r13*4+0]\nlea rcx, [r12+rax*4]\nloc_1412:\ntest r14d, r14d\njle loc_1502\nxor r10d, r10d\nxchg ax, ax\nloc_1420:\nmov edx, [rdi]\nmov rax, r12\njmp short loc_1439\nloc_1430:\nadd rax, 4\ncmp rax, rcx\njz short loc_1469\nloc_1439:\ncmp edx, [rax]\njnz short loc_1430\nmovsxd r9, r10d\ntest r10d, r10d\njle loc_14E8\nmovsxd r9, r10d\nmov rax, r8\nlea rsi, [r8+r9*4]\njmp short loc_1465\nloc_1458:\nadd rax, 4\ncmp rax, rsi\njz loc_14E8\nloc_1465:\ncmp edx, [rax]\njnz short loc_1458\nloc_1469:\nadd rdi, 4\ncmp rdi, r11\njnz short loc_1420\nloc_1472:\ncmp r10d, 1\njle short loc_14D4\nlea rsi, [r8+4]\nmov r11d, r10d\nmov r9d, 1\nlea r12d, [r10-1]\nlea rbp, [r8+8]\nnop dword ptr [rax]\nloc_1490:\ncmp r10d, r9d\njle short loc_14C7\nmov eax, r12d\nsub eax, r9d\nlea rax, [r9+rax-1]\nlea rdi, [rbp+rax*4+0]\nmov rax, rsi\nnop dword ptr [rax+rax+00000000h]\nloc_14B0:\nmov edx, [rsi-4]\nmov ecx, [rax]\ncmp edx, ecx\njle short loc_14BE\nmov [rsi-4], ecx\nmov [rax], edx\nloc_14BE:\nadd rax, 4\ncmp rax, rdi\njnz short loc_14B0\nloc_14C7:\nadd r9, 1\nadd rsi, 4\ncmp r9, r11\njnz short loc_1490\nloc_14D4:\nmov [rbx], r10d\nmov rax, r8\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_14E8:\nadd rdi, 4\nmov [r8+r9*4], edx\nadd r10d, 1\ncmp rdi, r11\njnz loc_1420\njmp loc_1472\nloc_1502:\nadd rdi, 4\ncmp rdi, r11\njnz loc_1412\nloc_150F:\nxor r10d, r10d\nmov rax, r8\nmov [rbx], r10d\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2, _DWORD *a3, int a4, int *a5)\n{\n __int64 v8; // rdi\n _DWORD *v10; // r8\n int *v11; // rdi\n int *v12; // r11\n int v13; // r10d\n int v14; // edx\n _DWORD *v15; // rax\n __int64 v16; // r9\n _DWORD *v17; // rax\n _DWORD *v18; // rsi\n __int64 i; // r9\n _DWORD *v20; // rax\n int v21; // edx\n _DWORD *result; // rax\n\n v8 = a2;\n if ( a4 <= a2 )\n v8 = a4;\n v10 = malloc(4 * v8);\n if ( v10 && a2 > 0 )\n {\n v11 = a1;\n v12 = &a1[a2];\n while ( a4 <= 0 )\n {\n if ( ++v11 == v12 )\n goto LABEL_28;\n }\n v13 = 0;\n while ( 2 )\n {\n while ( 2 )\n {\n v14 = *v11;\n v15 = a3;\n while ( v14 != *v15 )\n {\n if ( ++v15 == &a3[a4] )\n goto LABEL_15;\n }\n v16 = v13;\n if ( v13 > 0 )\n {\n v16 = v13;\n v17 = v10;\n while ( v14 != *v17 )\n {\n if ( ++v17 == &v10[v13] )\n goto LABEL_25;\n }\nLABEL_15:\n if ( ++v11 != v12 )\n continue;\n goto LABEL_16;\n }\n break;\n }\nLABEL_25:\n ++v11;\n v10[v16] = v14;\n ++v13;\n if ( v11 != v12 )\n continue;\n break;\n }\nLABEL_16:\n if ( v13 > 1 )\n {\n v18 = v10 + 1;\n for ( i = 1LL; i != v13; ++i )\n {\n if ( v13 > (int)i )\n {\n v20 = v18;\n do\n {\n v21 = *(v18 - 1);\n if ( v21 > *v20 )\n {\n *(v18 - 1) = *v20;\n *v20 = v21;\n }\n ++v20;\n }\n while ( v20 != &v10[i + 1 + (unsigned int)(v13 - 1 - i)] );\n }\n ++v18;\n }\n }\n *a5 = v13;\n return v10;\n }\n else\n {\nLABEL_28:\n result = v10;\n *a5 = 0;\n }\n return result;\n}", + "ida_strip_asm": "sub_13C0:\nendbr64\npush r14\nmovsxd r14, ecx\npush r13\nmovsxd r13, esi\npush r12\ncmp r14d, r13d\nmov r12, rdx\npush rbp\nmov rbp, rdi\nmovsxd rdi, r13d\npush rbx\ncmovle rdi, r14\nmov rbx, r8\nshl rdi, 2; size\ncall _malloc\nmov r8, rax\ntest rax, rax\njz loc_150F\ntest r13d, r13d\njle loc_150F\nmovsxd rax, r14d\nmov rdi, rbp\nlea r11, [rbp+r13*4+0]\nlea rcx, [r12+rax*4]\nloc_1412:\ntest r14d, r14d\njle loc_1502\nxor r10d, r10d\nxchg ax, ax\nloc_1420:\nmov edx, [rdi]\nmov rax, r12\njmp short loc_1439\nloc_1430:\nadd rax, 4\ncmp rax, rcx\njz short loc_1469\nloc_1439:\ncmp edx, [rax]\njnz short loc_1430\nmovsxd r9, r10d\ntest r10d, r10d\njle loc_14E8\nmovsxd r9, r10d\nmov rax, r8\nlea rsi, [r8+r9*4]\njmp short loc_1465\nloc_1458:\nadd rax, 4\ncmp rax, rsi\njz loc_14E8\nloc_1465:\ncmp edx, [rax]\njnz short loc_1458\nloc_1469:\nadd rdi, 4\ncmp rdi, r11\njnz short loc_1420\nloc_1472:\ncmp r10d, 1\njle short loc_14D4\nlea rsi, [r8+4]\nmov r11d, r10d\nmov r9d, 1\nlea r12d, [r10-1]\nlea rbp, [r8+8]\nnop dword ptr [rax]\nloc_1490:\ncmp r10d, r9d\njle short loc_14C7\nmov eax, r12d\nsub eax, r9d\nlea rax, [r9+rax-1]\nlea rdi, [rbp+rax*4+0]\nmov rax, rsi\nnop dword ptr [rax+rax+00000000h]\nloc_14B0:\nmov edx, [rsi-4]\nmov ecx, [rax]\ncmp edx, ecx\njle short loc_14BE\nmov [rsi-4], ecx\nmov [rax], edx\nloc_14BE:\nadd rax, 4\ncmp rax, rdi\njnz short loc_14B0\nloc_14C7:\nadd r9, 1\nadd rsi, 4\ncmp r9, r11\njnz short loc_1490\nloc_14D4:\nmov [rbx], r10d\nmov rax, r8\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_14E8:\nadd rdi, 4\nmov [r8+r9*4], edx\nadd r10d, 1\ncmp rdi, r11\njnz loc_1420\njmp loc_1472\nloc_1502:\nadd rdi, 4\ncmp rdi, r11\njnz loc_1412\nloc_150F:\nxor r10d, r10d\nmov rax, r8\nmov [rbx], r10d\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_13C0(int *a1, int a2, _DWORD *a3, int a4, int *a5)\n{\n __int64 v8; // rdi\n _DWORD *v10; // r8\n int *v11; // rdi\n int *v12; // r11\n int v13; // r10d\n int v14; // edx\n _DWORD *v15; // rax\n __int64 v16; // r9\n _DWORD *v17; // rax\n _DWORD *v18; // rsi\n __int64 i; // r9\n _DWORD *v20; // rax\n int v21; // edx\n _DWORD *result; // rax\n\n v8 = a2;\n if ( a4 <= a2 )\n v8 = a4;\n v10 = malloc(4 * v8);\n if ( v10 && a2 > 0 )\n {\n v11 = a1;\n v12 = &a1[a2];\n while ( a4 <= 0 )\n {\n if ( ++v11 == v12 )\n goto LABEL_28;\n }\n v13 = 0;\n while ( 2 )\n {\n while ( 2 )\n {\n v14 = *v11;\n v15 = a3;\n while ( v14 != *v15 )\n {\n if ( ++v15 == &a3[a4] )\n goto LABEL_15;\n }\n v16 = v13;\n if ( v13 > 0 )\n {\n v16 = v13;\n v17 = v10;\n while ( v14 != *v17 )\n {\n if ( ++v17 == &v10[v13] )\n goto LABEL_25;\n }\nLABEL_15:\n if ( ++v11 != v12 )\n continue;\n goto LABEL_16;\n }\n break;\n }\nLABEL_25:\n ++v11;\n v10[v16] = v14;\n ++v13;\n if ( v11 != v12 )\n continue;\n break;\n }\nLABEL_16:\n if ( v13 > 1 )\n {\n v18 = v10 + 1;\n for ( i = 1LL; i != v13; ++i )\n {\n if ( v13 > (int)i )\n {\n v20 = v18;\n do\n {\n v21 = *(v18 - 1);\n if ( v21 > *v20 )\n {\n *(v18 - 1) = *v20;\n *v20 = v21;\n }\n ++v20;\n }\n while ( v20 != &v10[i + 1 + (unsigned int)(v13 - 1 - i)] );\n }\n ++v18;\n }\n }\n *a5 = v13;\n return v10;\n }\n else\n {\nLABEL_28:\n result = v10;\n *a5 = 0;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_13C0(int *a1, int a2, uint32_t *a3, int a4, int *a5) {\n long long v8;\n uint32_t *v10;\n int *v11;\n int *v12;\n int v13;\n int v14;\n uint32_t *v15;\n long long v16;\n uint32_t *v17;\n uint32_t *v18;\n long long i;\n uint32_t *v20;\n int v21;\n uint32_t *result;\n v8 = a2;\n if (a4 <= a2) v8 = a4;\n v10 = malloc(4 * v8);\n if (v10 && a2 > 0) {\n v11 = a1;\n v12 = &a1[a2];\n while (a4 <= 0) {\n if (++v11 == v12) goto LABEL_28;\n }\n v13 = 0;\n while (2) {\n while (2) {\n v14 = *v11;\n v15 = a3;\n while (v14 != *v15) {\n if (++v15 == &a3[a4]) goto LABEL_15;\n }\n v16 = v13;\n if (v13 > 0) {\n v16 = v13;\n v17 = v10;\n while (v14 != *v17) {\n if (++v17 == &v10[v13]) goto LABEL_25;\n }\n LABEL_15:\n if (++v11 != v12) continue;\n goto LABEL_16;\n }\n break;\n }\n LABEL_25:\n ++v11;\n v10[v16] = v14;\n ++v13;\n if (v11 != v12) continue;\n break;\n }\n LABEL_16:\n if (v13 > 1) {\n v18 = v10 + 1;\n for (i = 1LL; i != v13; ++i) {\n if (v13 > (int)i) {\n v20 = v18;\n do {\n v21 = *(v18 - 1);\n if (v21 > *v20) {\n *(v18 - 1) = *v20;\n *v20 = v21;\n }\n ++v20;\n } while (v20 != &v10[i + 1 + (unsigned int)(v13 - 1 - i)]);\n }\n ++v18;\n }\n }\n *a5 = v13;\n return v10;\n } else {\n LABEL_28:\n result = v10;\n *a5 = 0;\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2, uint32_t *a3, int a4, int *a5) {\n long long v8;\n uint32_t *v10;\n int *v11;\n int *v12;\n int v13;\n int v14;\n uint32_t *v15;\n long long v16;\n uint32_t *v17;\n uint32_t *v18;\n long long i;\n uint32_t *v20;\n int v21;\n uint32_t *result;\n v8 = a2;\n if (a4 <= a2) v8 = a4;\n v10 = malloc(4 * v8);\n if (v10 && a2 > 0) {\n v11 = a1;\n v12 = &a1[a2];\n while (a4 <= 0) {\n if (++v11 == v12) goto LABEL_28;\n }\n v13 = 0;\n while (2) {\n while (2) {\n v14 = *v11;\n v15 = a3;\n while (v14 != *v15) {\n if (++v15 == &a3[a4]) goto LABEL_15;\n }\n v16 = v13;\n if (v13 > 0) {\n v16 = v13;\n v17 = v10;\n while (v14 != *v17) {\n if (++v17 == &v10[v13]) goto LABEL_25;\n }\n LABEL_15:\n if (++v11 != v12) continue;\n goto LABEL_16;\n }\n break;\n }\n LABEL_25:\n ++v11;\n v10[v16] = v14;\n ++v13;\n if (v11 != v12) continue;\n break;\n }\n LABEL_16:\n if (v13 > 1) {\n v18 = v10 + 1;\n for (i = 1LL; i != v13; ++i) {\n if (v13 > (int)i) {\n v20 = v18;\n do {\n v21 = *(v18 - 1);\n if (v21 > *v20) {\n *(v18 - 1) = *v20;\n *v20 = v21;\n }\n ++v20;\n } while (v20 != &v10[i + 1 + (unsigned int)(v13 - 1 - i)]);\n }\n ++v18;\n }\n }\n *a5 = v13;\n return v10;\n } else {\n LABEL_28:\n result = v10;\n *a5 = 0;\n }\n return result;\n}" + }, + { + "index": 3, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int result = 0;\n for (int i = 2; i <= (int)sqrt(n); i++) {\n if (n % i == 0) {\n result = 1;\n }\n }\n return result;\n}", + "test": "int main() {\n\n assert(func0(2) == 0);\n\n assert(func0(10) == 1);\n\n assert(func0(35) == 1);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %edi,-0x14(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x2,-0x4(%rbp)\njmp 11a0 \nmov -0x14(%rbp),%eax\ncltd\nidivl -0x4(%rbp)\nmov %edx,%eax\ntest %eax,%eax\njne 119c \nmovl $0x1,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\ncvtsi2sdl -0x14(%rbp),%xmm0\ncallq 1070 \ncvttsd2si %xmm0,%eax\ncmp %eax,-0x4(%rbp)\njle 1188 \nmov -0x8(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 2\njmp short loc_11A0\nloc_1188:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njnz short loc_119C\nmov [rbp+var_8], 1\nloc_119C:\nadd [rbp+var_4], 1\nloc_11A0:\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_14]\nmovq rax, xmm1\nmovq xmm0, rax; x\ncall _sqrt\ncvttsd2si eax, xmm0\ncmp [rbp+var_4], eax\njle short loc_1188\nmov eax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v2; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v2 = 0;\n for ( i = 2; i <= (int)sqrt((double)a1); ++i )\n {\n if ( !(a1 % i) )\n v2 = 1;\n }\n return v2;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 2\njmp short loc_11A0\nloc_1188:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njnz short loc_119C\nmov [rbp+var_8], 1\nloc_119C:\nadd [rbp+var_4], 1\nloc_11A0:\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_14]\nmovq rax, xmm1\nmovq xmm0, rax; x\ncall _sqrt\ncvttsd2si eax, xmm0\ncmp [rbp+var_4], eax\njle short loc_1188\nmov eax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n unsigned int v2; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v2 = 0;\n for ( i = 2; i <= (int)sqrt((double)a1); ++i )\n {\n if ( !(a1 % i) )\n v2 = 1;\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n unsigned int v2;\n int i;\n v2 = 0;\n for (i = 2; i <= (int)sqrt((double)a1); ++i) {\n if (!(a1 % i)) v2 = 1;\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v2;\n int i;\n v2 = 0;\n for (i = 2; i <= (int)sqrt((double)a1); ++i) {\n if (!(a1 % i)) v2 = 1;\n }\n return v2;\n}" + }, + { + "index": 3, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int result = 0;\n for (int i = 2; i <= (int)sqrt(n); i++) {\n if (n % i == 0) {\n result = 1;\n }\n }\n return result;\n}", + "test": "int main() {\n\n assert(func0(2) == 0);\n\n assert(func0(10) == 1);\n\n assert(func0(35) == 1);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov %edi,%ebp\npxor %xmm3,%xmm3\ncvtsi2sd %edi,%xmm3\nmovsd %xmm3,0x8(%rsp)\nmovapd %xmm3,%xmm0\nsqrtsd %xmm0,%xmm0\ncvttsd2si %xmm0,%r13d\nmov $0x2,%ebx\nmov $0x0,%r12d\npxor %xmm1,%xmm1\nucomisd 0x8(%rsp),%xmm1\nja 11c5 \ncmp %ebx,%r13d\njl 11d2 \nmov %ebp,%eax\ncltd\nidiv %ebx\ntest %edx,%edx\nmov $0x1,%eax\ncmove %eax,%r12d\nadd $0x1,%ebx\njmp 119f \nmovsd 0x8(%rsp),%xmm0\ncallq 1070 \njmp 11ab \nmov %r12d,%eax\nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 10h\nmov ebp, edi\nmov ebx, 2\nmov r12d, 0\npxor xmm2, xmm2\ncvtsi2sd xmm2, edi\nmovsd [rsp+28h+x], xmm2\njmp short loc_11A5\nloc_1192:\nmov eax, ebp\ncdq\nidiv ebx\ntest edx, edx\nmov eax, 1\ncmovz r12d, eax\nadd ebx, 1\nloc_11A5:\npxor xmm0, xmm0\nmovsd xmm1, [rsp+28h+x]\nucomisd xmm0, xmm1\nja short loc_11D1\nmovapd xmm0, xmm1\nsqrtsd xmm0, xmm0\nloc_11BD:\ncvttsd2si eax, xmm0\ncmp eax, ebx\njge short loc_1192\nmov eax, r12d\nadd rsp, 10h\npop rbx\npop rbp\npop r12\nretn\nloc_11D1:\nmovsd xmm0, [rsp+28h+x]; x\ncall _sqrt\njmp short loc_11BD", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // ebx\n unsigned int v2; // r12d\n double v3; // xmm0_8\n double x; // [rsp+8h] [rbp-20h]\n\n v1 = 2;\n v2 = 0;\n x = (double)a1;\n while ( 1 )\n {\n v3 = x < 0.0 ? sqrt(x) : sqrt(x);\n if ( (int)v3 < v1 )\n break;\n if ( !(a1 % v1) )\n v2 = 1;\n ++v1;\n }\n return v2;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 10h\nmov ebp, edi\nmov ebx, 2\nmov r12d, 0\npxor xmm2, xmm2\ncvtsi2sd xmm2, edi\nmovsd [rsp+28h+x], xmm2\njmp short loc_11A5\nloc_1192:\nmov eax, ebp\ncdq\nidiv ebx\ntest edx, edx\nmov eax, 1\ncmovz r12d, eax\nadd ebx, 1\nloc_11A5:\npxor xmm0, xmm0\nmovsd xmm1, [rsp+28h+x]\nucomisd xmm0, xmm1\nja short loc_11D1\nmovapd xmm0, xmm1\nsqrtsd xmm0, xmm0\nloc_11BD:\ncvttsd2si eax, xmm0\ncmp eax, ebx\njge short loc_1192\nmov eax, r12d\nadd rsp, 10h\npop rbx\npop rbp\npop r12\nretn\nloc_11D1:\nmovsd xmm0, [rsp+28h+x]; x\ncall _sqrt\njmp short loc_11BD", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n int v1; // ebx\n unsigned int v2; // r12d\n double v3; // xmm0_8\n double x; // [rsp+8h] [rbp-20h]\n\n v1 = 2;\n v2 = 0;\n x = (double)a1;\n while ( 1 )\n {\n v3 = x < 0.0 ? sqrt(x) : sqrt(x);\n if ( (int)v3 < v1 )\n break;\n if ( !(a1 % v1) )\n v2 = 1;\n ++v1;\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n int v1;\n unsigned int v2;\n double v3;\n double x;\n v1 = 2;\n v2 = 0;\n x = (double)a1;\n while (1) {\n v3 = x < 0.0 ? sqrt(x) : sqrt(x);\n if ((int)v3 < v1) break;\n if (!(a1 % v1)) v2 = 1;\n ++v1;\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n unsigned int v2;\n double v3;\n double x;\n v1 = 2;\n v2 = 0;\n x = (double)a1;\n while (1) {\n v3 = x < 0.0 ? sqrt(x) : sqrt(x);\n if ((int)v3 < v1) break;\n if (!(a1 % v1)) v2 = 1;\n ++v1;\n }\n return v2;\n}" + }, + { + "index": 3, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int result = 0;\n for (int i = 2; i <= (int)sqrt(n); i++) {\n if (n % i == 0) {\n result = 1;\n }\n }\n return result;\n}", + "test": "int main() {\n\n assert(func0(2) == 0);\n\n assert(func0(10) == 1);\n\n assert(func0(35) == 1);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npxor %xmm1,%xmm1\npush %r13\npxor %xmm2,%xmm2\nmov $0x1,%r13d\ncvtsi2sd %edi,%xmm1\npush %r12\nxor %r12d,%r12d\npush %rbp\npush %rbx\nmov $0x2,%ebx\nmovapd %xmm1,%xmm0\nsqrtsd %xmm0,%xmm0\nsub $0x18,%rsp\ncvttsd2si %xmm0,%ebp\njmp 11ae \nnopw %cs:0x0(%rax,%rax,1)\nmov %edi,%eax\ncltd\nidiv %ebx\ntest %edx,%edx\ncmove %r13d,%r12d\nadd $0x1,%ebx\nucomisd %xmm1,%xmm2\nja 11c6 \ncmp %ebx,%ebp\njge 11a0 \nadd $0x18,%rsp\nmov %r12d,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nmovapd %xmm1,%xmm0\nmov %edi,0xc(%rsp)\nmovsd %xmm1,(%rsp)\ncallq 1050 \nmov 0xc(%rsp),%edi\nmovsd (%rsp),%xmm1\npxor %xmm2,%xmm2\njmp 11b4 \nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\npxor xmm1, xmm1\nxor ebp, ebp\npxor xmm2, xmm2\npush rbx\ncvtsi2sd xmm1, edi\nmov ebx, 2\nsub rsp, 18h\njmp short loc_1242\nloc_1230:\nmov eax, edi\ncdq\nidiv ebx\nmov eax, 1\ntest edx, edx\ncmovz ebp, eax\nadd ebx, 1\nloc_1242:\nucomisd xmm2, xmm1\nja short loc_1261\nmovapd xmm0, xmm1\nsqrtsd xmm0, xmm0\nloc_1250:\ncvttsd2si eax, xmm0\ncmp eax, ebx\njge short loc_1230\nadd rsp, 18h\nmov eax, ebp\npop rbx\npop rbp\nretn\nloc_1261:\nmovapd xmm0, xmm1; x\nmov [rsp+28h+var_1C], edi\nmovsd [rsp+28h+var_28], xmm1\ncall _sqrt\nmov edi, [rsp+28h+var_1C]\nmovsd xmm1, [rsp+28h+var_28]\npxor xmm2, xmm2\njmp short loc_1250", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v1; // ebp\n double v2; // xmm1_8\n int i; // ebx\n double v4; // xmm0_8\n\n v1 = 0;\n v2 = (double)a1;\n for ( i = 2; ; ++i )\n {\n v4 = v2 < 0.0 ? sqrt(v2) : sqrt(v2);\n if ( (int)v4 < i )\n break;\n if ( !(a1 % i) )\n v1 = 1;\n }\n return v1;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbp\npxor xmm1, xmm1\nxor ebp, ebp\npxor xmm2, xmm2\npush rbx\ncvtsi2sd xmm1, edi\nmov ebx, 2\nsub rsp, 18h\njmp short loc_1242\nloc_1230:\nmov eax, edi\ncdq\nidiv ebx\nmov eax, 1\ntest edx, edx\ncmovz ebp, eax\nadd ebx, 1\nloc_1242:\nucomisd xmm2, xmm1\nja short loc_1261\nmovapd xmm0, xmm1\nsqrtsd xmm0, xmm0\nloc_1250:\ncvttsd2si eax, xmm0\ncmp eax, ebx\njge short loc_1230\nadd rsp, 18h\nmov eax, ebp\npop rbx\npop rbp\nretn\nloc_1261:\nmovapd xmm0, xmm1; x\nmov [rsp+28h+var_1C], edi\nmovsd [rsp+28h+var_28], xmm1\ncall _sqrt\nmov edi, [rsp+28h+var_1C]\nmovsd xmm1, [rsp+28h+var_28]\npxor xmm2, xmm2\njmp short loc_1250", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(int a1)\n{\n unsigned int v1; // ebp\n double v2; // xmm1_8\n int i; // ebx\n double v4; // xmm0_8\n\n v1 = 0;\n v2 = (double)a1;\n for ( i = 2; ; ++i )\n {\n v4 = v2 < 0.0 ? sqrt(v2) : sqrt(v2);\n if ( (int)v4 < i )\n break;\n if ( !(a1 % i) )\n v1 = 1;\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(int a1) {\n unsigned int v1;\n double v2;\n int i;\n double v4;\n v1 = 0;\n v2 = (double)a1;\n for (i = 2;; ++i) {\n v4 = v2 < 0.0 ? sqrt(v2) : sqrt(v2);\n if ((int)v4 < i) break;\n if (!(a1 % i)) v1 = 1;\n }\n return v1;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v1;\n double v2;\n int i;\n double v4;\n v1 = 0;\n v2 = (double)a1;\n for (i = 2;; ++i) {\n v4 = v2 < 0.0 ? sqrt(v2) : sqrt(v2);\n if ((int)v4 < i) break;\n if (!(a1 % i)) v1 = 1;\n }\n return v1;\n}" + }, + { + "index": 3, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int result = 0;\n for (int i = 2; i <= (int)sqrt(n); i++) {\n if (n % i == 0) {\n result = 1;\n }\n }\n return result;\n}", + "test": "int main() {\n\n assert(func0(2) == 0);\n\n assert(func0(10) == 1);\n\n assert(func0(35) == 1);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npxor %xmm1,%xmm1\npush %r13\ncvtsi2sd %edi,%xmm1\npush %r12\npush %rbp\npush %rbx\nmovapd %xmm1,%xmm0\nsqrtsd %xmm0,%xmm0\nsub $0x18,%rsp\ncvttsd2si %xmm0,%ebx\npxor %xmm0,%xmm0\nucomisd %xmm1,%xmm0\nja 11c9 \nlea 0x1(%rbx),%r8d\nmov $0x2,%ecx\nxor %r12d,%r12d\nmov $0x1,%esi\ncmp $0x1,%ebx\njle 11bb \nnopw 0x0(%rax,%rax,1)\nmov %edi,%eax\ncltd\nidiv %ecx\ntest %edx,%edx\ncmove %esi,%r12d\nadd $0x1,%ecx\ncmp %ecx,%r8d\njne 11a8 \nadd $0x18,%rsp\nmov %r12d,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nmov $0x2,%ebp\nxor %r12d,%r12d\nmov $0x1,%r13d\njmp 11f0 \nmov 0xc(%rsp),%edi\nmovsd (%rsp),%xmm1\nmov %edi,%eax\ncltd\nidiv %ebp\ntest %edx,%edx\ncmove %r13d,%r12d\nadd $0x1,%ebp\nmovapd %xmm1,%xmm0\nmov %edi,0xc(%rsp)\nmovsd %xmm1,(%rsp)\ncallq 1050 \ncmp %ebp,%ebx\njge 11d9 \njmp 11bb \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npxor xmm1, xmm1\npush r13\npxor xmm0, xmm0\ncvtsi2sd xmm1, edi\npush r12\npush rbp\npush rbx\nmov ebx, edi\nsub rsp, 18h\nucomisd xmm0, xmm1\nja short loc_11BE\nsqrtsd xmm1, xmm1\nmov ecx, 2\nxor ebp, ebp\nmov edi, 1\ncvttsd2si esi, xmm1\ncmp esi, 1\njle short loc_11B1\nnop dword ptr [rax+rax+00h]\nloc_11A0:\nmov eax, ebx\ncdq\nidiv ecx\ntest edx, edx\ncmovz ebp, edi\nadd ecx, 1\ncmp esi, ecx\njge short loc_11A0\nloc_11B1:\nadd rsp, 18h\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_11BE:\nmov r12d, 2\nxor ebp, ebp\nmov r13d, 1\njmp short loc_11E4\nloc_11CE:\nmov eax, ebx\nmovsd xmm1, [rsp+38h+var_30]\ncdq\nidiv r12d\ntest edx, edx\ncmovz ebp, r13d\nadd r12d, 1\nloc_11E4:\nmovapd xmm0, xmm1; x\nmovsd [rsp+38h+var_30], xmm1\ncall _sqrt\ncvttsd2si eax, xmm0\ncmp r12d, eax\njle short loc_11CE\njmp short loc_11B1", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n double v1; // xmm1_8\n int v2; // ecx\n unsigned int v3; // ebp\n int v4; // esi\n int v6; // r12d\n\n v1 = (double)a1;\n if ( (double)a1 < 0.0 )\n {\n v6 = 2;\n v3 = 0;\n while ( v6 <= (int)sqrt(v1) )\n {\n if ( !(a1 % v6) )\n v3 = 1;\n ++v6;\n }\n }\n else\n {\n v2 = 2;\n v3 = 0;\n v4 = (int)sqrt(v1);\n if ( v4 > 1 )\n {\n do\n {\n if ( !(a1 % v2) )\n v3 = 1;\n ++v2;\n }\n while ( v4 >= v2 );\n }\n }\n return v3;\n}", + "ida_strip_asm": "sub_1160:\nendbr64\npxor xmm1, xmm1\npush r13\npxor xmm0, xmm0\ncvtsi2sd xmm1, edi\npush r12\npush rbp\npush rbx\nmov ebx, edi\nsub rsp, 18h\nucomisd xmm0, xmm1\nja short loc_11BE\nsqrtsd xmm1, xmm1\nmov ecx, 2\nxor ebp, ebp\nmov edi, 1\ncvttsd2si esi, xmm1\ncmp esi, 1\njle short loc_11B1\nnop dword ptr [rax+rax+00h]\nloc_11A0:\nmov eax, ebx\ncdq\nidiv ecx\ntest edx, edx\ncmovz ebp, edi\nadd ecx, 1\ncmp esi, ecx\njge short loc_11A0\nloc_11B1:\nadd rsp, 18h\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_11BE:\nmov r12d, 2\nxor ebp, ebp\nmov r13d, 1\njmp short loc_11E4\nloc_11CE:\nmov eax, ebx\nmovsd xmm1, [rsp+38h+var_30]\ncdq\nidiv r12d\ntest edx, edx\ncmovz ebp, r13d\nadd r12d, 1\nloc_11E4:\nmovapd xmm0, xmm1; x\nmovsd [rsp+38h+var_30], xmm1\ncall _sqrt\ncvttsd2si eax, xmm0\ncmp r12d, eax\njle short loc_11CE\njmp short loc_11B1", + "ida_strip_pseudo": "__int64 __fastcall sub_1160(int a1)\n{\n double v1; // xmm1_8\n int v2; // ecx\n unsigned int v3; // ebp\n int v4; // esi\n int v6; // r12d\n\n v1 = (double)a1;\n if ( (double)a1 < 0.0 )\n {\n v6 = 2;\n v3 = 0;\n while ( v6 <= (int)sqrt(v1) )\n {\n if ( !(a1 % v6) )\n v3 = 1;\n ++v6;\n }\n }\n else\n {\n v2 = 2;\n v3 = 0;\n v4 = (int)sqrt(v1);\n if ( v4 > 1 )\n {\n do\n {\n if ( !(a1 % v2) )\n v3 = 1;\n ++v2;\n }\n while ( v4 >= v2 );\n }\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1160(int a1) {\n double v1;\n int v2;\n unsigned int v3;\n int v4;\n int v6;\n v1 = (double)a1;\n if ((double)a1 < 0.0) {\n v6 = 2;\n v3 = 0;\n while (v6 <= (int)sqrt(v1)) {\n if (!(a1 % v6)) v3 = 1;\n ++v6;\n }\n } else {\n v2 = 2;\n v3 = 0;\n v4 = (int)sqrt(v1);\n if (v4 > 1) {\n do {\n if (!(a1 % v2)) v3 = 1;\n ++v2;\n } while (v4 >= v2);\n }\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n double v1;\n int v2;\n unsigned int v3;\n int v4;\n int v6;\n v1 = (double)a1;\n if ((double)a1 < 0.0) {\n v6 = 2;\n v3 = 0;\n while (v6 <= (int)sqrt(v1)) {\n if (!(a1 % v6)) v3 = 1;\n ++v6;\n }\n } else {\n v2 = 2;\n v3 = 0;\n v4 = (int)sqrt(v1);\n if (v4 > 1) {\n do {\n if (!(a1 % v2)) v3 = 1;\n ++v2;\n } while (v4 >= v2);\n }\n }\n return v3;\n}" + }, + { + "index": 4, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nint compare(const void * a, const void * b) {\n\n return ( *(int*)b - *(int*)a );\n\n}\n\n\n\n", + "func": "void func0(int nums[], int size, int n, int result[]) {\n qsort(nums, size, sizeof(int), compare);\n for (int i = 0; i < n; i++) {\n result[i] = nums[i];\n }\n}", + "test": "int main() {\n\n int test1[9] = {25, 35, 22, 85, 14, 65, 75, 22, 58};\n\n int result1[3];\n\n func0(test1, 9, 3, result1);\n\n assert(result1[0] == 85 && result1[1] == 75 && result1[2] == 65);\n\n \n\n int test2[9] = {25, 35, 22, 85, 14, 65, 75, 22, 58};\n\n int result2[2];\n\n func0(test2, 9, 2, result2);\n\n assert(result2[0] == 85 && result2[1] == 75);\n\n\n\n int test3[9] = {25, 35, 22, 85, 14, 65, 75, 22, 58};\n\n int result3[5];\n\n func0(test3, 9, 5, result3);\n\n assert(result3[0] == 85 && result3[1] == 75 && result3[2] == 65 && result3[3] == 58 && result3[4] == 35);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmov %rcx,-0x28(%rbp)\nmov -0x1c(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x18(%rbp),%rax\nlea -0x4d(%rip),%rcx\nmov $0x4,%edx\nmov %rax,%rdi\ncallq 1070 \nmovl $0x0,-0x4(%rbp)\njmp 121d \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0x4(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x28(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x20(%rbp),%eax\njl 11ec \nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+base], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_28], rcx\nmov eax, [rbp+var_1C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compare\nmov rcx, rdx; compar\nmov edx, 4; size\nmov rdi, rax; base\ncall _qsort\nmov [rbp+var_4], 0\njmp short loc_1220\nloc_11EF:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_4], 1\nloc_1220:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_20]\njl short loc_11EF\nnop\nnop\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(void *a1, int a2, int a3, __int64 a4)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+2Ch] [rbp-4h]\n\n qsort(a1, a2, 4uLL, compare);\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a3 )\n break;\n *(_DWORD *)(4LL * (int)i + a4) = *((_DWORD *)a1 + (int)i);\n }\n return result;\n}", + "ida_strip_asm": "sub_11AB:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+base], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_28], rcx\nmov eax, [rbp+var_1C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 4; size\nmov rdi, rax; base\ncall _qsort\nmov [rbp+var_4], 0\njmp short loc_1220\nloc_11EF:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_4], 1\nloc_1220:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_20]\njl short loc_11EF\nnop\nnop\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11AB(void *a1, int a2, int a3, __int64 a4)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+2Ch] [rbp-4h]\n\n qsort(a1, a2, 4uLL, compar);\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a3 )\n break;\n *(_DWORD *)(4LL * (int)i + a4) = *((_DWORD *)a1 + (int)i);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11AB(void *a1, int a2, int a3, long long a4) {\n long long result;\n unsigned int i;\n qsort(a1, a2, 4uLL, compar);\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a3) break;\n *(uint32_t *)(4LL * (int)i + a4) = *((uint32_t *)a1 + (int)i);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(void *a1, int a2, int a3, long long a4) {\n long long result;\n unsigned int i;\n qsort(a1, a2, 4uLL, compare);\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a3) break;\n *(uint32_t *)(4LL * (int)i + a4) = *((uint32_t *)a1 + (int)i);\n }\n return result;\n}" + }, + { + "index": 4, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nint compare(const void * a, const void * b) {\n\n return ( *(int*)b - *(int*)a );\n\n}\n\n\n\n", + "func": "void func0(int nums[], int size, int n, int result[]) {\n qsort(nums, size, sizeof(int), compare);\n for (int i = 0; i < n; i++) {\n result[i] = nums[i];\n }\n}", + "test": "int main() {\n\n int test1[9] = {25, 35, 22, 85, 14, 65, 75, 22, 58};\n\n int result1[3];\n\n func0(test1, 9, 3, result1);\n\n assert(result1[0] == 85 && result1[1] == 75 && result1[2] == 65);\n\n \n\n int test2[9] = {25, 35, 22, 85, 14, 65, 75, 22, 58};\n\n int result2[2];\n\n func0(test2, 9, 2, result2);\n\n assert(result2[0] == 85 && result2[1] == 75);\n\n\n\n int test3[9] = {25, 35, 22, 85, 14, 65, 75, 22, 58};\n\n int result3[5];\n\n func0(test3, 9, 5, result3);\n\n assert(result3[0] == 85 && result3[1] == 75 && result3[2] == 65 && result3[3] == 58 && result3[4] == 35);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nmov %edx,%r12d\nmov %rcx,%rbp\nmovslq %esi,%rsi\nlea -0x24(%rip),%rcx\nmov $0x4,%edx\ncallq 1070 \ntest %r12d,%r12d\njle 11d9 \nlea -0x1(%r12),%ecx\nmov $0x0,%eax\nmov (%rbx,%rax,4),%edx\nmov %edx,0x0(%rbp,%rax,4)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rcx,%rdx\njne 11c6 \npop %rbx\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbp, rdi\nmov ebx, edx\nmov r12, rcx\nmovsxd rsi, esi; nmemb\nlea rcx, compare; compar\nmov edx, 4; size\ncall _qsort\ntest ebx, ebx\njle short loc_11D7\nmovsxd rcx, ebx\nshl rcx, 2\nmov eax, 0\nloc_11C6:\nmov edx, [rbp+rax+0]\nmov [r12+rax], edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_11C6\nloc_11D7:\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "void __fastcall func0(char *a1, int a2, int a3, __int64 a4)\n{\n __int64 v6; // rax\n\n qsort(a1, a2, 4uLL, compare);\n if ( a3 > 0 )\n {\n v6 = 0LL;\n do\n {\n *(_DWORD *)(a4 + v6) = *(_DWORD *)&a1[v6];\n v6 += 4LL;\n }\n while ( v6 != 4LL * a3 );\n }\n}", + "ida_strip_asm": "sub_1192:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbp, rdi\nmov ebx, edx\nmov r12, rcx\nmovsxd rsi, esi; nmemb\nlea rcx, compar; compar\nmov edx, 4; size\ncall _qsort\ntest ebx, ebx\njle short loc_11D7\nmovsxd rcx, ebx\nshl rcx, 2\nmov eax, 0\nloc_11C6:\nmov edx, [rbp+rax+0]\nmov [r12+rax], edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_11C6\nloc_11D7:\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "void __fastcall sub_1192(char *a1, int a2, int a3, __int64 a4)\n{\n __int64 v6; // rax\n\n qsort(a1, a2, 4uLL, compar);\n if ( a3 > 0 )\n {\n v6 = 0LL;\n do\n {\n *(_DWORD *)(a4 + v6) = *(_DWORD *)&a1[v6];\n v6 += 4LL;\n }\n while ( v6 != 4LL * a3 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1192(char *a1, int a2, int a3, long long a4) {\n long long v6;\n qsort(a1, a2, 4uLL, compar);\n if (a3 > 0) {\n v6 = 0LL;\n do {\n *(uint32_t *)(a4 + v6) = *(uint32_t *)&a1[v6];\n v6 += 4LL;\n } while (v6 != 4LL * a3);\n }\n}", + "ida_pseudo_norm": "void func0(char *a1, int a2, int a3, long long a4) {\n long long v6;\n qsort(a1, a2, 4uLL, compare);\n if (a3 > 0) {\n v6 = 0LL;\n do {\n *(uint32_t *)(a4 + v6) = *(uint32_t *)&a1[v6];\n v6 += 4LL;\n } while (v6 != 4LL * a3);\n }\n}" + }, + { + "index": 4, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nint compare(const void * a, const void * b) {\n\n return ( *(int*)b - *(int*)a );\n\n}\n\n\n\n", + "func": "void func0(int nums[], int size, int n, int result[]) {\n qsort(nums, size, sizeof(int), compare);\n for (int i = 0; i < n; i++) {\n result[i] = nums[i];\n }\n}", + "test": "int main() {\n\n int test1[9] = {25, 35, 22, 85, 14, 65, 75, 22, 58};\n\n int result1[3];\n\n func0(test1, 9, 3, result1);\n\n assert(result1[0] == 85 && result1[1] == 75 && result1[2] == 65);\n\n \n\n int test2[9] = {25, 35, 22, 85, 14, 65, 75, 22, 58};\n\n int result2[2];\n\n func0(test2, 9, 2, result2);\n\n assert(result2[0] == 85 && result2[1] == 75);\n\n\n\n int test3[9] = {25, 35, 22, 85, 14, 65, 75, 22, 58};\n\n int result3[5];\n\n func0(test3, 9, 5, result3);\n\n assert(result3[0] == 85 && result3[1] == 75 && result3[2] == 65 && result3[3] == 58 && result3[4] == 35);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmovslq %esi,%rsi\nmov %edx,%r12d\nmov $0x4,%edx\npush %rbp\nmov %rcx,%rbp\nlea -0x2c(%rip),%rcx\npush %rbx\nmov %rdi,%rbx\ncallq 1070 \ntest %r12d,%r12d\njle 13db \nlea -0x1(%r12),%ecx\nxor %eax,%eax\nnopl 0x0(%rax)\nmov (%rbx,%rax,4),%edx\nmov %edx,0x0(%rbp,%rax,4)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rcx,%rdx\njne 13c8 \npop %rbx\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\npush r12\nmovsxd rsi, esi; nmemb\nmov r12, rcx\nlea rcx, compare; compar\npush rbp\nmov rbp, rdi\npush rbx\nmov ebx, edx\nmov edx, 4; size\ncall _qsort\ntest ebx, ebx\njle short loc_13A9\nmovsxd rcx, ebx\nxor eax, eax\nshl rcx, 2\nnop dword ptr [rax+00000000h]\nloc_1398:\nmov edx, [rbp+rax+0]\nmov [r12+rax], edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_1398\nloc_13A9:\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "void __fastcall func0(char *a1, int a2, int a3, __int64 a4)\n{\n __int64 v6; // rax\n\n qsort(a1, a2, 4uLL, compare);\n if ( a3 > 0 )\n {\n v6 = 0LL;\n do\n {\n *(_DWORD *)(a4 + v6) = *(_DWORD *)&a1[v6];\n v6 += 4LL;\n }\n while ( v6 != 4LL * a3 );\n }\n}", + "ida_strip_asm": "sub_1360:\nendbr64\npush r12\nmovsxd rsi, esi; nmemb\nmov r12, rcx\nlea rcx, compar; compar\npush rbp\nmov rbp, rdi\npush rbx\nmov ebx, edx\nmov edx, 4; size\ncall _qsort\ntest ebx, ebx\njle short loc_13A9\nmovsxd rcx, ebx\nxor eax, eax\nshl rcx, 2\nnop dword ptr [rax+00000000h]\nloc_1398:\nmov edx, [rbp+rax+0]\nmov [r12+rax], edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_1398\nloc_13A9:\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "void __fastcall sub_1360(char *a1, int a2, int a3, __int64 a4)\n{\n __int64 v6; // rax\n\n qsort(a1, a2, 4uLL, compar);\n if ( a3 > 0 )\n {\n v6 = 0LL;\n do\n {\n *(_DWORD *)(a4 + v6) = *(_DWORD *)&a1[v6];\n v6 += 4LL;\n }\n while ( v6 != 4LL * a3 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1360(char *a1, int a2, int a3, long long a4) {\n long long v6;\n qsort(a1, a2, 4uLL, compar);\n if (a3 > 0) {\n v6 = 0LL;\n do {\n *(uint32_t *)(a4 + v6) = *(uint32_t *)&a1[v6];\n v6 += 4LL;\n } while (v6 != 4LL * a3);\n }\n}", + "ida_pseudo_norm": "void func0(char *a1, int a2, int a3, long long a4) {\n long long v6;\n qsort(a1, a2, 4uLL, compare);\n if (a3 > 0) {\n v6 = 0LL;\n do {\n *(uint32_t *)(a4 + v6) = *(uint32_t *)&a1[v6];\n v6 += 4LL;\n } while (v6 != 4LL * a3);\n }\n}" + }, + { + "index": 4, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nint compare(const void * a, const void * b) {\n\n return ( *(int*)b - *(int*)a );\n\n}\n\n\n\n", + "func": "void func0(int nums[], int size, int n, int result[]) {\n qsort(nums, size, sizeof(int), compare);\n for (int i = 0; i < n; i++) {\n result[i] = nums[i];\n }\n}", + "test": "int main() {\n\n int test1[9] = {25, 35, 22, 85, 14, 65, 75, 22, 58};\n\n int result1[3];\n\n func0(test1, 9, 3, result1);\n\n assert(result1[0] == 85 && result1[1] == 75 && result1[2] == 65);\n\n \n\n int test2[9] = {25, 35, 22, 85, 14, 65, 75, 22, 58};\n\n int result2[2];\n\n func0(test2, 9, 2, result2);\n\n assert(result2[0] == 85 && result2[1] == 75);\n\n\n\n int test3[9] = {25, 35, 22, 85, 14, 65, 75, 22, 58};\n\n int result3[5];\n\n func0(test3, 9, 5, result3);\n\n assert(result3[0] == 85 && result3[1] == 75 && result3[2] == 65 && result3[3] == 58 && result3[4] == 35);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmovslq %esi,%rsi\nmov %edx,%r12d\nmov $0x4,%edx\npush %rbp\nmov %rcx,%rbp\nlea -0x2c(%rip),%rcx\npush %rbx\nmov %rdi,%rbx\ncallq 1070 \ntest %r12d,%r12d\njle 13fb \nlea 0xf(%rbx),%rdx\nlea -0x1(%r12),%eax\nsub %rbp,%rdx\ncmp $0x1e,%rdx\njbe 1400 \ncmp $0x3,%eax\njbe 1400 \nmov %r12d,%edx\nxor %eax,%eax\nshr $0x2,%edx\nshl $0x4,%rdx\nnopl (%rax)\nmovdqu (%rbx,%rax,1),%xmm0\nmovups %xmm0,0x0(%rbp,%rax,1)\nadd $0x10,%rax\ncmp %rdx,%rax\njne 13b0 \nmov %r12d,%eax\nand $0xfffffffc,%eax\ntest $0x3,%r12b\nje 13fb \nmov %eax,%edx\nmov (%rbx,%rdx,4),%ecx\nmov %ecx,0x0(%rbp,%rdx,4)\nlea 0x1(%rax),%edx\ncmp %edx,%r12d\njle 13fb \nmovslq %edx,%rdx\nadd $0x2,%eax\nmov (%rbx,%rdx,4),%ecx\nmov %ecx,0x0(%rbp,%rdx,4)\ncmp %eax,%r12d\njle 13fb \ncltq\nmov (%rbx,%rax,4),%edx\nmov %edx,0x0(%rbp,%rax,4)\npop %rbx\npop %rbp\npop %r12\nretq\nmov %eax,%edx\nxor %eax,%eax\nnopl 0x0(%rax)\nmov (%rbx,%rax,4),%ecx\nmov %ecx,0x0(%rbp,%rax,4)\nmov %rax,%rcx\nadd $0x1,%rax\ncmp %rdx,%rcx\njne 1408 \npop %rbx\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\npush r12\nmovsxd rsi, esi; nmemb\nmov r12, rcx\nlea rcx, compare; compar\npush rbp\nmov rbp, rdi\npush rbx\nmovsxd rbx, edx\nmov edx, 4; size\ncall _qsort\ntest ebx, ebx\njle short loc_13C1\nlea eax, [rbx-1]\ncmp eax, 2\njbe short loc_13A1\nlea rdx, [rbp+4]\nmov rax, r12\nsub rax, rdx\ncmp rax, 8\nja short loc_13D0\nloc_13A1:\nshl rbx, 2\nxor eax, eax\nnop word ptr [rax+rax+00000000h]\nloc_13B0:\nmov edx, [rbp+rax+0]\nmov [r12+rax], edx\nadd rax, 4\ncmp rbx, rax\njnz short loc_13B0\nloc_13C1:\npop rbx\npop rbp\npop r12\nretn\nloc_13D0:\nmov edx, ebx\nxor eax, eax\nshr edx, 2\nshl rdx, 4\nnop dword ptr [rax+rax+00h]\nloc_13E0:\nmovdqu xmm0, xmmword ptr [rbp+rax+0]\nmovups xmmword ptr [r12+rax], xmm0\nadd rax, 10h\ncmp rax, rdx\njnz short loc_13E0\nmov eax, ebx\nand eax, 0FFFFFFFCh\ntest bl, 3\njz short loc_13C1\nmov ecx, eax\nmov esi, [rbp+rcx*4+0]\nlea rdx, ds:0[rcx*4]\nmov [r12+rcx*4], esi\nlea ecx, [rax+1]\ncmp ebx, ecx\njle short loc_13C1\nmov ecx, [rbp+rdx+4]\nadd eax, 2\nmov [r12+rdx+4], ecx\ncmp ebx, eax\njle short loc_13C1\nmov eax, [rbp+rdx+8]\nmov [r12+rdx+8], eax\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "void __fastcall func0(char *a1, int a2, int a3, __int64 a4)\n{\n __int64 v5; // rbx\n __int64 v6; // rbx\n __int64 v7; // rax\n __int64 v8; // rax\n unsigned int v9; // eax\n __int64 v10; // rdx\n\n v5 = a3;\n qsort(a1, a2, 4uLL, compare);\n if ( (int)v5 > 0 )\n {\n if ( (unsigned int)(v5 - 1) > 2 && (unsigned __int64)(a4 - (_QWORD)(a1 + 4)) > 8 )\n {\n v8 = 0LL;\n do\n {\n *(__m128i *)(a4 + v8) = _mm_loadu_si128((const __m128i *)&a1[v8]);\n v8 += 16LL;\n }\n while ( v8 != 16LL * ((unsigned int)v5 >> 2) );\n v9 = v5 & 0xFFFFFFFC;\n if ( (v5 & 3) != 0 )\n {\n v10 = 4LL * v9;\n *(_DWORD *)(a4 + v10) = *(_DWORD *)&a1[v10];\n if ( (int)v5 > (int)(v9 + 1) )\n {\n *(_DWORD *)(a4 + v10 + 4) = *(_DWORD *)&a1[v10 + 4];\n if ( (int)v5 > (int)(v9 + 2) )\n *(_DWORD *)(a4 + v10 + 8) = *(_DWORD *)&a1[v10 + 8];\n }\n }\n }\n else\n {\n v6 = 4 * v5;\n v7 = 0LL;\n do\n {\n *(_DWORD *)(a4 + v7) = *(_DWORD *)&a1[v7];\n v7 += 4LL;\n }\n while ( v6 != v7 );\n }\n }\n}", + "ida_strip_asm": "sub_1360:\nendbr64\npush r12\nmovsxd rsi, esi; nmemb\nmov r12, rcx\nlea rcx, compar; compar\npush rbp\nmov rbp, rdi\npush rbx\nmovsxd rbx, edx\nmov edx, 4; size\ncall _qsort\ntest ebx, ebx\njle short loc_13C1\nlea eax, [rbx-1]\ncmp eax, 2\njbe short loc_13A1\nlea rdx, [rbp+4]\nmov rax, r12\nsub rax, rdx\ncmp rax, 8\nja short loc_13D0\nloc_13A1:\nshl rbx, 2\nxor eax, eax\nnop word ptr [rax+rax+00000000h]\nloc_13B0:\nmov edx, [rbp+rax+0]\nmov [r12+rax], edx\nadd rax, 4\ncmp rbx, rax\njnz short loc_13B0\nloc_13C1:\npop rbx\npop rbp\npop r12\nretn\nloc_13D0:\nmov edx, ebx\nxor eax, eax\nshr edx, 2\nshl rdx, 4\nnop dword ptr [rax+rax+00h]\nloc_13E0:\nmovdqu xmm0, xmmword ptr [rbp+rax+0]\nmovups xmmword ptr [r12+rax], xmm0\nadd rax, 10h\ncmp rax, rdx\njnz short loc_13E0\nmov eax, ebx\nand eax, 0FFFFFFFCh\ntest bl, 3\njz short loc_13C1\nmov ecx, eax\nmov esi, [rbp+rcx*4+0]\nlea rdx, ds:0[rcx*4]\nmov [r12+rcx*4], esi\nlea ecx, [rax+1]\ncmp ebx, ecx\njle short loc_13C1\nmov ecx, [rbp+rdx+4]\nadd eax, 2\nmov [r12+rdx+4], ecx\ncmp ebx, eax\njle short loc_13C1\nmov eax, [rbp+rdx+8]\nmov [r12+rdx+8], eax\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "void __fastcall sub_1360(char *a1, int a2, int a3, __int64 a4)\n{\n __int64 v5; // rbx\n __int64 v6; // rbx\n __int64 v7; // rax\n __int64 v8; // rax\n unsigned int v9; // eax\n __int64 v10; // rdx\n\n v5 = a3;\n qsort(a1, a2, 4uLL, compar);\n if ( (int)v5 > 0 )\n {\n if ( (unsigned int)(v5 - 1) > 2 && (unsigned __int64)(a4 - (_QWORD)(a1 + 4)) > 8 )\n {\n v8 = 0LL;\n do\n {\n *(__m128i *)(a4 + v8) = _mm_loadu_si128((const __m128i *)&a1[v8]);\n v8 += 16LL;\n }\n while ( v8 != 16LL * ((unsigned int)v5 >> 2) );\n v9 = v5 & 0xFFFFFFFC;\n if ( (v5 & 3) != 0 )\n {\n v10 = 4LL * v9;\n *(_DWORD *)(a4 + v10) = *(_DWORD *)&a1[v10];\n if ( (int)v5 > (int)(v9 + 1) )\n {\n *(_DWORD *)(a4 + v10 + 4) = *(_DWORD *)&a1[v10 + 4];\n if ( (int)v5 > (int)(v9 + 2) )\n *(_DWORD *)(a4 + v10 + 8) = *(_DWORD *)&a1[v10 + 8];\n }\n }\n }\n else\n {\n v6 = 4 * v5;\n v7 = 0LL;\n do\n {\n *(_DWORD *)(a4 + v7) = *(_DWORD *)&a1[v7];\n v7 += 4LL;\n }\n while ( v6 != v7 );\n }\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1360(char *a1, int a2, int a3, long long a4) {\n long long v5;\n long long v6;\n long long v7;\n long long v8;\n unsigned int v9;\n long long v10;\n v5 = a3;\n qsort(a1, a2, 4uLL, compar);\n if ((int)v5 > 0) {\n if ((unsigned int)(v5 - 1) > 2 &&\n (unsigned long long)(a4 - (uint64_t)(a1 + 4)) > 8) {\n v8 = 0LL;\n do {\n *(__m128i *)(a4 + v8) = _mm_loadu_si128((const __m128i *)&a1[v8]);\n v8 += 16LL;\n } while (v8 != 16LL * ((unsigned int)v5 >> 2));\n v9 = v5 & 4294967292;\n if ((v5 & 3) != 0) {\n v10 = 4LL * v9;\n *(uint32_t *)(a4 + v10) = *(uint32_t *)&a1[v10];\n if ((int)v5 > (int)(v9 + 1)) {\n *(uint32_t *)(a4 + v10 + 4) = *(uint32_t *)&a1[v10 + 4];\n if ((int)v5 > (int)(v9 + 2))\n *(uint32_t *)(a4 + v10 + 8) = *(uint32_t *)&a1[v10 + 8];\n }\n }\n } else {\n v6 = 4 * v5;\n v7 = 0LL;\n do {\n *(uint32_t *)(a4 + v7) = *(uint32_t *)&a1[v7];\n v7 += 4LL;\n } while (v6 != v7);\n }\n }\n}", + "ida_pseudo_norm": "void func0(char *a1, int a2, int a3, long long a4) {\n long long v5;\n long long v6;\n long long v7;\n long long v8;\n unsigned int v9;\n long long v10;\n v5 = a3;\n qsort(a1, a2, 4uLL, compare);\n if ((int)v5 > 0) {\n if ((unsigned int)(v5 - 1) > 2 &&\n (unsigned long long)(a4 - (uint64_t)(a1 + 4)) > 8) {\n v8 = 0LL;\n do {\n *(__m128i *)(a4 + v8) = _mm_loadu_si128((const __m128i *)&a1[v8]);\n v8 += 16LL;\n } while (v8 != 16LL * ((unsigned int)v5 >> 2));\n v9 = v5 & 4294967292;\n if ((v5 & 3) != 0) {\n v10 = 4LL * v9;\n *(uint32_t *)(a4 + v10) = *(uint32_t *)&a1[v10];\n if ((int)v5 > (int)(v9 + 1)) {\n *(uint32_t *)(a4 + v10 + 4) = *(uint32_t *)&a1[v10 + 4];\n if ((int)v5 > (int)(v9 + 2))\n *(uint32_t *)(a4 + v10 + 8) = *(uint32_t *)&a1[v10 + 8];\n }\n }\n } else {\n v6 = 4 * v5;\n v7 = 0LL;\n do {\n *(uint32_t *)(a4 + v7) = *(uint32_t *)&a1[v7];\n v7 += 4LL;\n } while (v6 != v7);\n }\n }\n}" + }, + { + "index": 5, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int *A = (int *)malloc((n + 1) * sizeof(int));\n int *B = (int *)malloc((n + 1) * sizeof(int));\n if (A == NULL || B == NULL) {\n fprintf(stderr, \"Memory allocation failed\\n\");\n exit(EXIT_FAILURE);\n }\n A[0] = 1;\n A[1] = 0;\n B[0] = 0;\n B[1] = 1;\n for (int i = 2; i <= n; i++) {\n A[i] = A[i - 2] + 2 * B[i - 1];\n B[i] = A[i - 1] + B[i - 2];\n }\n int result = A[n];\n free(A);\n free(B);\n return result;\n}", + "test": "int main() {\n\n assert(func0(2) == 3);\n\n assert(func0(8) == 153);\n\n assert(func0(12) == 2131);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %edi,-0x24(%rbp)\nmov -0x24(%rbp),%eax\nadd $0x1,%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x10(%rbp)\nmov -0x24(%rbp),%eax\nadd $0x1,%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\ncmpq $0x0,-0x10(%rbp)\nje 1216 \ncmpq $0x0,-0x8(%rbp)\njne 1240 \nmov 0x2e03(%rip),%rax\nmov %rax,%rcx\nmov $0x19,%edx\nmov $0x1,%esi\nlea 0xdd7(%rip),%rdi\ncallq 10d0 \nmov $0x1,%edi\ncallq 10c0 \nmov -0x10(%rbp),%rax\nmovl $0x1,(%rax)\nmov -0x10(%rbp),%rax\nadd $0x4,%rax\nmovl $0x0,(%rax)\nmov -0x8(%rbp),%rax\nmovl $0x0,(%rax)\nmov -0x8(%rbp),%rax\nadd $0x4,%rax\nmovl $0x1,(%rax)\nmovl $0x2,-0x18(%rbp)\njmpq 130b \nmov -0x18(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x8(%rax),%rdx\nmov -0x10(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x18(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rcx\nmov -0x8(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\nlea (%rax,%rax,1),%ecx\nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rsi\nmov -0x10(%rbp),%rax\nadd %rsi,%rax\nadd %ecx,%edx\nmov %edx,(%rax)\nmov -0x18(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rdx\nmov -0x10(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%ecx\nmov -0x18(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x8(%rax),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rsi\nmov -0x8(%rbp),%rax\nadd %rsi,%rax\nadd %ecx,%edx\nmov %edx,(%rax)\naddl $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%eax\ncmp -0x24(%rbp),%eax\njle 127c \nmov -0x24(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x10(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x14(%rbp)\nmov -0x10(%rbp),%rax\nmov %rax,%rdi\ncallq 1090 \nmov -0x8(%rbp),%rax\nmov %rax,%rdi\ncallq 1090 \nmov -0x14(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_24], edi\nmov eax, [rbp+var_24]\nadd eax, 1\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov eax, [rbp+var_24]\nadd eax, 1\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\ncmp [rbp+ptr], 0\njz short loc_1216\ncmp [rbp+var_8], 0\njnz short loc_1243\nloc_1216:\nmov rax, cs:__bss_start\nmov rcx, rax; s\nmov edx, 19h; n\nmov esi, 1; size\nlea rax, aMemoryAllocati; \"Memory allocation failed\\n\"\nmov rdi, rax; ptr\ncall _fwrite\nmov edi, 1; status\ncall _exit\nloc_1243:\nmov rax, [rbp+ptr]\nmov dword ptr [rax], 1\nmov rax, [rbp+ptr]\nadd rax, 4\nmov dword ptr [rax], 0\nmov rax, [rbp+var_8]\nmov dword ptr [rax], 0\nmov rax, [rbp+var_8]\nadd rax, 4\nmov dword ptr [rax], 1\nmov [rbp+var_18], 2\njmp loc_130E\nloc_127F:\nmov eax, [rbp+var_18]\ncdqe\nshl rax, 2\nlea rdx, [rax-8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_18]\ncdqe\nshl rax, 2\nlea rcx, [rax-4]\nmov rax, [rbp+var_8]\nadd rax, rcx\nmov eax, [rax]\nlea ecx, [rax+rax]\nmov eax, [rbp+var_18]\ncdqe\nlea rsi, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rsi\nadd edx, ecx\nmov [rax], edx\nmov eax, [rbp+var_18]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov ecx, [rax]\nmov eax, [rbp+var_18]\ncdqe\nshl rax, 2\nlea rdx, [rax-8]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_18]\ncdqe\nlea rsi, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rsi\nadd edx, ecx\nmov [rax], edx\nadd [rbp+var_18], 1\nloc_130E:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_24]\njle loc_127F\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_14], eax\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_8]\nmov rdi, rax; ptr\ncall _free\nmov eax, [rbp+var_14]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int i; // [rsp+18h] [rbp-18h]\n unsigned int v3; // [rsp+1Ch] [rbp-14h]\n _DWORD *ptr; // [rsp+20h] [rbp-10h]\n _DWORD *v5; // [rsp+28h] [rbp-8h]\n\n ptr = malloc(4LL * (a1 + 1));\n v5 = malloc(4LL * (a1 + 1));\n if ( !ptr || !v5 )\n {\n fwrite(\"Memory allocation failed\\n\", 1uLL, 0x19uLL, _bss_start);\n exit(1);\n }\n *ptr = 1;\n ptr[1] = 0;\n *v5 = 0;\n v5[1] = 1;\n for ( i = 2; i <= a1; ++i )\n {\n ptr[i] = 2 * v5[i - 1] + ptr[i - 2];\n v5[i] = ptr[i - 1] + v5[i - 2];\n }\n v3 = ptr[a1];\n free(ptr);\n free(v5);\n return v3;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_24], edi\nmov eax, [rbp+var_24]\nadd eax, 1\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov eax, [rbp+var_24]\nadd eax, 1\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\ncmp [rbp+ptr], 0\njz short loc_1216\ncmp [rbp+var_8], 0\njnz short loc_1243\nloc_1216:\nmov rax, cs:stderr\nmov rcx, rax; s\nmov edx, 19h; n\nmov esi, 1; size\nlea rax, aMemoryAllocati; \"Memory allocation failed\\n\"\nmov rdi, rax; ptr\ncall _fwrite\nmov edi, 1; status\ncall _exit\nloc_1243:\nmov rax, [rbp+ptr]\nmov dword ptr [rax], 1\nmov rax, [rbp+ptr]\nadd rax, 4\nmov dword ptr [rax], 0\nmov rax, [rbp+var_8]\nmov dword ptr [rax], 0\nmov rax, [rbp+var_8]\nadd rax, 4\nmov dword ptr [rax], 1\nmov [rbp+var_18], 2\njmp loc_130E\nloc_127F:\nmov eax, [rbp+var_18]\ncdqe\nshl rax, 2\nlea rdx, [rax-8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_18]\ncdqe\nshl rax, 2\nlea rcx, [rax-4]\nmov rax, [rbp+var_8]\nadd rax, rcx\nmov eax, [rax]\nlea ecx, [rax+rax]\nmov eax, [rbp+var_18]\ncdqe\nlea rsi, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rsi\nadd edx, ecx\nmov [rax], edx\nmov eax, [rbp+var_18]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov ecx, [rax]\nmov eax, [rbp+var_18]\ncdqe\nshl rax, 2\nlea rdx, [rax-8]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_18]\ncdqe\nlea rsi, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rsi\nadd edx, ecx\nmov [rax], edx\nadd [rbp+var_18], 1\nloc_130E:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_24]\njle loc_127F\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_14], eax\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_8]\nmov rdi, rax; ptr\ncall _free\nmov eax, [rbp+var_14]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11C9(int a1)\n{\n int i; // [rsp+18h] [rbp-18h]\n unsigned int v3; // [rsp+1Ch] [rbp-14h]\n _DWORD *ptr; // [rsp+20h] [rbp-10h]\n _DWORD *v5; // [rsp+28h] [rbp-8h]\n\n ptr = malloc(4LL * (a1 + 1));\n v5 = malloc(4LL * (a1 + 1));\n if ( !ptr || !v5 )\n {\n fwrite(\"Memory allocation failed\\n\", 1uLL, 0x19uLL, stderr);\n exit(1);\n }\n *ptr = 1;\n ptr[1] = 0;\n *v5 = 0;\n v5[1] = 1;\n for ( i = 2; i <= a1; ++i )\n {\n ptr[i] = 2 * v5[i - 1] + ptr[i - 2];\n v5[i] = ptr[i - 1] + v5[i - 2];\n }\n v3 = ptr[a1];\n free(ptr);\n free(v5);\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11C9(int a1) {\n int i;\n unsigned int v3;\n uint32_t *ptr;\n uint32_t *v5;\n ptr = malloc(4LL * (a1 + 1));\n v5 = malloc(4LL * (a1 + 1));\n if (!ptr || !v5) {\n fwrite(\"Memory allocation failed\\n\", 1uLL, 25uLL, stderr);\n exit(1);\n }\n *ptr = 1;\n ptr[1] = 0;\n *v5 = 0;\n v5[1] = 1;\n for (i = 2; i <= a1; ++i) {\n ptr[i] = 2 * v5[i - 1] + ptr[i - 2];\n v5[i] = ptr[i - 1] + v5[i - 2];\n }\n v3 = ptr[a1];\n free(ptr);\n free(v5);\n return v3;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int i;\n unsigned int v3;\n uint32_t *ptr;\n uint32_t *v5;\n ptr = malloc(4LL * (a1 + 1));\n v5 = malloc(4LL * (a1 + 1));\n if (!ptr || !v5) {\n fwrite(\"Memory allocation failed\\n\", 1uLL, 25uLL, _bss_start);\n exit(1);\n }\n *ptr = 1;\n ptr[1] = 0;\n *v5 = 0;\n v5[1] = 1;\n for (i = 2; i <= a1; ++i) {\n ptr[i] = 2 * v5[i - 1] + ptr[i - 2];\n v5[i] = ptr[i - 1] + v5[i - 2];\n }\n v3 = ptr[a1];\n free(ptr);\n free(v5);\n return v3;\n}" + }, + { + "index": 5, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int *A = (int *)malloc((n + 1) * sizeof(int));\n int *B = (int *)malloc((n + 1) * sizeof(int));\n if (A == NULL || B == NULL) {\n fprintf(stderr, \"Memory allocation failed\\n\");\n exit(EXIT_FAILURE);\n }\n A[0] = 1;\n A[1] = 0;\n B[0] = 0;\n B[1] = 1;\n for (int i = 2; i <= n; i++) {\n A[i] = A[i - 2] + 2 * B[i - 1];\n B[i] = A[i - 1] + B[i - 2];\n }\n int result = A[n];\n free(A);\n free(B);\n return result;\n}", + "test": "int main() {\n\n assert(func0(2) == 3);\n\n assert(func0(8) == 153);\n\n assert(func0(12) == 2131);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %edi,%r13d\nlea 0x1(%rdi),%ebp\nmovslq %ebp,%rbp\nshl $0x2,%rbp\nmov %rbp,%rdi\ncallq 10b0 \nmov %rax,%rbx\nmov %rbp,%rdi\ncallq 10b0 \ntest %rbx,%rbx\nje 1274 \nmov %rax,%r12\ntest %rax,%rax\nje 1274 \nmovl $0x1,(%rbx)\nmovl $0x0,0x4(%rbx)\nmovl $0x0,(%rax)\nmovl $0x1,0x4(%rax)\ncmp $0x1,%r13d\njle 1253 \nmov %rbx,%rax\nmov %r12,%rdx\nlea -0x2(%r13),%ecx\nlea 0x4(%rbx,%rcx,4),%rdi\nmov 0x4(%rdx),%esi\nmov (%rax),%ecx\nlea (%rcx,%rsi,2),%ecx\nmov %ecx,0x8(%rax)\nmov (%rdx),%ecx\nadd 0x4(%rax),%ecx\nmov %ecx,0x8(%rdx)\nadd $0x4,%rax\nadd $0x4,%rdx\ncmp %rdi,%rax\njne 1233 \nmov -0x4(%rbx,%rbp,1),%ebp\nmov %rbx,%rdi\ncallq 1090 \nmov %r12,%rdi\ncallq 1090 \nmov %ebp,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nmov 0x2da5(%rip),%rcx\nmov $0x19,%edx\nmov $0x1,%esi\nlea 0xd78(%rip),%rdi\ncallq 10d0 \nmov $0x1,%edi\ncallq 10c0 \n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r13d, edi\nlea ebp, [rdi+1]\nmovsxd rbp, ebp\nshl rbp, 2\nmov rdi, rbp; size\ncall _malloc\nmov rbx, rax\nmov rdi, rbp; size\ncall _malloc\ntest rbx, rbx\njz short loc_1273\nmov r12, rax\ntest rax, rax\njz short loc_1273\nmov dword ptr [rbx], 1\nmov dword ptr [rbx+4], 0\nmov dword ptr [rax], 0\nmov dword ptr [rax+4], 1\ncmp r13d, 1\njle short loc_1252\nmov rax, rbx\nmov rdx, r12\nlea ecx, [r13-1]\nlea rdi, [rbx+rcx*4]\nloc_1232:\nmov esi, [rdx+4]\nmov ecx, [rax]\nlea ecx, [rcx+rsi*2]\nmov [rax+8], ecx\nmov ecx, [rdx]\nadd ecx, [rax+4]\nmov [rdx+8], ecx\nadd rax, 4\nadd rdx, 4\ncmp rax, rdi\njnz short loc_1232\nloc_1252:\nmov ebp, [rbx+rbp-4]\nmov rdi, rbx; ptr\ncall _free\nmov rdi, r12; ptr\ncall _free\nmov eax, ebp\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1273:\nmov rcx, cs:__bss_start; s\nmov edx, 19h; n\nmov esi, 1; size\nlea rdi, aMemoryAllocati; \"Memory allocation failed\\n\"\ncall _fwrite\nmov edi, 1; status\ncall _exit", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n size_t v1; // rbp\n _DWORD *v2; // rbx\n _DWORD *v3; // rax\n _DWORD *v4; // r12\n _DWORD *v5; // rax\n _DWORD *v6; // rdx\n unsigned int v7; // ebp\n\n v1 = 4LL * (a1 + 1);\n v2 = malloc(v1);\n v3 = malloc(v1);\n if ( !v2 || (v4 = v3) == 0LL )\n {\n fwrite(\"Memory allocation failed\\n\", 1uLL, 0x19uLL, _bss_start);\n exit(1);\n }\n *v2 = 1;\n v2[1] = 0;\n *v3 = 0;\n v3[1] = 1;\n if ( a1 > 1 )\n {\n v5 = v2;\n v6 = v4;\n do\n {\n v5[2] = *v5 + 2 * v6[1];\n v6[2] = v5[1] + *v6;\n ++v5;\n ++v6;\n }\n while ( v5 != &v2[a1 - 1] );\n }\n v7 = v2[v1 / 4 - 1];\n free(v2);\n free(v4);\n return v7;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r13d, edi\nlea ebp, [rdi+1]\nmovsxd rbp, ebp\nshl rbp, 2\nmov rdi, rbp; size\ncall _malloc\nmov rbx, rax\nmov rdi, rbp; size\ncall _malloc\ntest rbx, rbx\njz short loc_1273\nmov r12, rax\ntest rax, rax\njz short loc_1273\nmov dword ptr [rbx], 1\nmov dword ptr [rbx+4], 0\nmov dword ptr [rax], 0\nmov dword ptr [rax+4], 1\ncmp r13d, 1\njle short loc_1252\nmov rax, rbx\nmov rdx, r12\nlea ecx, [r13-1]\nlea rdi, [rbx+rcx*4]\nloc_1232:\nmov esi, [rdx+4]\nmov ecx, [rax]\nlea ecx, [rcx+rsi*2]\nmov [rax+8], ecx\nmov ecx, [rdx]\nadd ecx, [rax+4]\nmov [rdx+8], ecx\nadd rax, 4\nadd rdx, 4\ncmp rax, rdi\njnz short loc_1232\nloc_1252:\nmov ebp, [rbx+rbp-4]\nmov rdi, rbx; ptr\ncall _free\nmov rdi, r12; ptr\ncall _free\nmov eax, ebp\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1273:\nmov rcx, cs:stderr; s\nmov edx, 19h; n\nmov esi, 1; size\nlea rdi, aMemoryAllocati; \"Memory allocation failed\\n\"\ncall _fwrite\nmov edi, 1; status\ncall _exit", + "ida_strip_pseudo": "__int64 __fastcall sub_11C9(int a1)\n{\n size_t v1; // rbp\n _DWORD *v2; // rbx\n _DWORD *v3; // rax\n _DWORD *v4; // r12\n _DWORD *v5; // rax\n _DWORD *v6; // rdx\n unsigned int v7; // ebp\n\n v1 = 4LL * (a1 + 1);\n v2 = malloc(v1);\n v3 = malloc(v1);\n if ( !v2 || (v4 = v3) == 0LL )\n {\n fwrite(\"Memory allocation failed\\n\", 1uLL, 0x19uLL, stderr);\n exit(1);\n }\n *v2 = 1;\n v2[1] = 0;\n *v3 = 0;\n v3[1] = 1;\n if ( a1 > 1 )\n {\n v5 = v2;\n v6 = v4;\n do\n {\n v5[2] = *v5 + 2 * v6[1];\n v6[2] = v5[1] + *v6;\n ++v5;\n ++v6;\n }\n while ( v5 != &v2[a1 - 1] );\n }\n v7 = v2[v1 / 4 - 1];\n free(v2);\n free(v4);\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11C9(int a1) {\n unsigned int v1;\n uint32_t *v2;\n uint32_t *v3;\n uint32_t *v4;\n uint32_t *v5;\n uint32_t *v6;\n unsigned int v7;\n v1 = 4LL * (a1 + 1);\n v2 = malloc(v1);\n v3 = malloc(v1);\n if (!v2 || (v4 = v3) == 0LL) {\n fwrite(\"Memory allocation failed\\n\", 1uLL, 25uLL, stderr);\n exit(1);\n }\n *v2 = 1;\n v2[1] = 0;\n *v3 = 0;\n v3[1] = 1;\n if (a1 > 1) {\n v5 = v2;\n v6 = v4;\n do {\n v5[2] = *v5 + 2 * v6[1];\n v6[2] = v5[1] + *v6;\n ++v5;\n ++v6;\n } while (v5 != &v2[a1 - 1]);\n }\n v7 = v2[v1 / 4 - 1];\n free(v2);\n free(v4);\n return v7;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v1;\n uint32_t *v2;\n uint32_t *v3;\n uint32_t *v4;\n uint32_t *v5;\n uint32_t *v6;\n unsigned int v7;\n v1 = 4LL * (a1 + 1);\n v2 = malloc(v1);\n v3 = malloc(v1);\n if (!v2 || (v4 = v3) == 0LL) {\n fwrite(\"Memory allocation failed\\n\", 1uLL, 25uLL, _bss_start);\n exit(1);\n }\n *v2 = 1;\n v2[1] = 0;\n *v3 = 0;\n v3[1] = 1;\n if (a1 > 1) {\n v5 = v2;\n v6 = v4;\n do {\n v5[2] = *v5 + 2 * v6[1];\n v6[2] = v5[1] + *v6;\n ++v5;\n ++v6;\n } while (v5 != &v2[a1 - 1]);\n }\n v7 = v2[v1 / 4 - 1];\n free(v2);\n free(v4);\n return v7;\n}" + }, + { + "index": 5, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int *A = (int *)malloc((n + 1) * sizeof(int));\n int *B = (int *)malloc((n + 1) * sizeof(int));\n if (A == NULL || B == NULL) {\n fprintf(stderr, \"Memory allocation failed\\n\");\n exit(EXIT_FAILURE);\n }\n A[0] = 1;\n A[1] = 0;\n B[0] = 0;\n B[1] = 1;\n for (int i = 2; i <= n; i++) {\n A[i] = A[i - 2] + 2 * B[i - 1];\n B[i] = A[i - 1] + B[i - 2];\n }\n int result = A[n];\n free(A);\n free(B);\n return result;\n}", + "test": "int main() {\n\n assert(func0(2) == 3);\n\n assert(func0(8) == 153);\n\n assert(func0(12) == 2131);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\nmov %edi,%r12d\npush %rbp\npush %rbx\nlea 0x1(%rdi),%ebx\nmovslq %ebx,%rbx\nshl $0x2,%rbx\nsub $0x8,%rsp\nmov %rbx,%rdi\ncallq 10b0 \nmov %rbx,%rdi\nmov %rax,%r13\ncallq 10b0 \ntest %r13,%r13\nje 1334 \nmov %rax,%rbp\ntest %rax,%rax\nje 1334 \nmovabs $0x100000000,%rax\nmovq $0x1,0x0(%r13)\nmov %rax,0x0(%rbp)\ncmp $0x1,%r12d\njle 1311 \nlea -0x2(%r12),%eax\nlea 0x4(%rbp),%rdx\nxor %ecx,%ecx\nmov $0x1,%edi\nlea 0x4(%r13),%rsi\nlea 0x4(%rbp,%rax,4),%r9\njmp 12fb \nnopw 0x0(%rax,%rax,1)\nadd $0x4,%rdx\nadd $0x4,%rsi\nmov %r8d,%ecx\nmov (%rdx),%r8d\nlea (%rdi,%r8,2),%edi\nmov %edi,0x4(%rsi)\nmov (%rsi),%edi\nadd %edi,%ecx\nmov %ecx,0x4(%rdx)\ncmp %r9,%rdx\njne 12f0 \nmov %r13,%rdi\nmov -0x4(%r13,%rbx,1),%r12d\ncallq 1090 \nmov %rbp,%rdi\ncallq 1090 \nadd $0x8,%rsp\nmov %r12d,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nmov 0x2ce5(%rip),%rcx\nmov $0x19,%edx\nmov $0x1,%esi\nlea 0xcb8(%rip),%rdi\ncallq 10d0 \nmov $0x1,%edi\ncallq 10c0 \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r13\nmov r13d, edi\npush r12\npush rbp\npush rbx\nlea ebx, [rdi+1]\nmovsxd rbx, ebx\nshl rbx, 2\nsub rsp, 8\nmov rdi, rbx; size\ncall _malloc\nmov rdi, rbx; size\nmov rbp, rax\ncall _malloc\ntest rbp, rbp\njz loc_1337\nmov r12, rax\ntest rax, rax\njz loc_1337\nmov rax, cs:qword_2078\nmov qword ptr [rbp+0], 1\nmov [r12], rax\ncmp r13d, 1\njle short loc_1316\nlea eax, [r13-2]\nlea rdx, [rbp+8]\nxor esi, esi\nmov r9d, 1\nlea r10, [rbp+rax*4+0Ch]\nlea rcx, [r12+8]\nmov eax, 1\nxor r8d, r8d\njmp short loc_12F2\nloc_12F0:\nmov esi, edi\nloc_12F2:\nlea edi, [r9+rax*2]\nadd rdx, 4\nmov r9d, eax\nadd rcx, 4\nlea eax, [rsi+r8]\nmov [rdx-4], edi\nmov r8d, r9d\nmov r9d, esi\nmov [rcx-4], eax\ncmp rdx, r10\njnz short loc_12F0\nloc_1316:\nmov rdi, rbp; ptr\nmov ebx, [rbp+rbx-4]\ncall _free\nmov rdi, r12; ptr\ncall _free\nadd rsp, 8\nmov eax, ebx\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1337:\nmov rcx, cs:__bss_start; s\nmov edx, 19h; n\nmov esi, 1; size\nlea rdi, aMemoryAllocati; \"Memory allocation failed\\n\"\ncall _fwrite\nmov edi, 1; status\ncall _exit", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n size_t v2; // rbx\n _QWORD *v3; // rbp\n _QWORD *v4; // rax\n void *v5; // r12\n _QWORD *v6; // rdx\n int v7; // esi\n int v8; // r9d\n _QWORD *v9; // rcx\n int v10; // eax\n int v11; // r8d\n int v12; // edi\n int v13; // r9d\n unsigned int v14; // ebx\n\n v2 = 4LL * (a1 + 1);\n v3 = malloc(v2);\n v4 = malloc(v2);\n if ( !v3 || (v5 = v4) == 0LL )\n {\n fwrite(\"Memory allocation failed\\n\", 1uLL, 0x19uLL, _bss_start);\n exit(1);\n }\n *v3 = 1LL;\n *v4 = 0x100000000LL;\n if ( a1 > 1 )\n {\n v6 = v3 + 1;\n v7 = 0;\n v8 = 1;\n v9 = v4 + 1;\n v10 = 1;\n v11 = 0;\n while ( 1 )\n {\n v12 = v8 + 2 * v10;\n v6 = (_QWORD *)((char *)v6 + 4);\n v13 = v10;\n v9 = (_QWORD *)((char *)v9 + 4);\n v10 = v7 + v11;\n *((_DWORD *)v6 - 1) = v12;\n v11 = v13;\n v8 = v7;\n *((_DWORD *)v9 - 1) = v10;\n if ( v6 == (_QWORD *)((char *)v3 + 4 * (unsigned int)(a1 - 2) + 12) )\n break;\n v7 = v12;\n }\n }\n v14 = *(_DWORD *)((char *)v3 + v2 - 4);\n free(v3);\n free(v5);\n return v14;\n}", + "ida_strip_asm": "sub_1270:\nendbr64\npush r13\nmov r13d, edi\npush r12\npush rbp\npush rbx\nlea ebx, [rdi+1]\nmovsxd rbx, ebx\nshl rbx, 2\nsub rsp, 8\nmov rdi, rbx; size\ncall _malloc\nmov rdi, rbx; size\nmov rbp, rax\ncall _malloc\ntest rbp, rbp\njz loc_1337\nmov r12, rax\ntest rax, rax\njz loc_1337\nmov rax, cs:qword_2078\nmov qword ptr [rbp+0], 1\nmov [r12], rax\ncmp r13d, 1\njle short loc_1316\nlea eax, [r13-2]\nlea rdx, [rbp+8]\nxor esi, esi\nmov r9d, 1\nlea r10, [rbp+rax*4+0Ch]\nlea rcx, [r12+8]\nmov eax, 1\nxor r8d, r8d\njmp short loc_12F2\nloc_12F0:\nmov esi, edi\nloc_12F2:\nlea edi, [r9+rax*2]\nadd rdx, 4\nmov r9d, eax\nadd rcx, 4\nlea eax, [rsi+r8]\nmov [rdx-4], edi\nmov r8d, r9d\nmov r9d, esi\nmov [rcx-4], eax\ncmp rdx, r10\njnz short loc_12F0\nloc_1316:\nmov rdi, rbp; ptr\nmov ebx, [rbp+rbx-4]\ncall _free\nmov rdi, r12; ptr\ncall _free\nadd rsp, 8\nmov eax, ebx\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1337:\nmov rcx, cs:stderr; s\nmov edx, 19h; n\nmov esi, 1; size\nlea rdi, aMemoryAllocati; \"Memory allocation failed\\n\"\ncall _fwrite\nmov edi, 1; status\ncall _exit", + "ida_strip_pseudo": "__int64 __fastcall sub_1270(int a1)\n{\n size_t v2; // rbx\n _QWORD *v3; // rbp\n _QWORD *v4; // rax\n void *v5; // r12\n _QWORD *v6; // rdx\n int v7; // esi\n int v8; // r9d\n _QWORD *v9; // rcx\n int v10; // eax\n int v11; // r8d\n int v12; // edi\n int v13; // r9d\n unsigned int v14; // ebx\n\n v2 = 4LL * (a1 + 1);\n v3 = malloc(v2);\n v4 = malloc(v2);\n if ( !v3 || (v5 = v4) == 0LL )\n {\n fwrite(\"Memory allocation failed\\n\", 1uLL, 0x19uLL, stderr);\n exit(1);\n }\n *v3 = 1LL;\n *v4 = 0x100000000LL;\n if ( a1 > 1 )\n {\n v6 = v3 + 1;\n v7 = 0;\n v8 = 1;\n v9 = v4 + 1;\n v10 = 1;\n v11 = 0;\n while ( 1 )\n {\n v12 = v8 + 2 * v10;\n v6 = (_QWORD *)((char *)v6 + 4);\n v13 = v10;\n v9 = (_QWORD *)((char *)v9 + 4);\n v10 = v7 + v11;\n *((_DWORD *)v6 - 1) = v12;\n v11 = v13;\n v8 = v7;\n *((_DWORD *)v9 - 1) = v10;\n if ( v6 == (_QWORD *)((char *)v3 + 4 * (unsigned int)(a1 - 2) + 12) )\n break;\n v7 = v12;\n }\n }\n v14 = *(_DWORD *)((char *)v3 + v2 - 4);\n free(v3);\n free(v5);\n return v14;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1270(int a1) {\n unsigned int v2;\n uint64_t *v3;\n uint64_t *v4;\n void *v5;\n uint64_t *v6;\n int v7;\n int v8;\n uint64_t *v9;\n int v10;\n int v11;\n int v12;\n int v13;\n unsigned int v14;\n v2 = 4LL * (a1 + 1);\n v3 = malloc(v2);\n v4 = malloc(v2);\n if (!v3 || (v5 = v4) == 0LL) {\n fwrite(\"Memory allocation failed\\n\", 1uLL, 25uLL, stderr);\n exit(1);\n }\n *v3 = 1LL;\n *v4 = 4294967296LL;\n if (a1 > 1) {\n v6 = v3 + 1;\n v7 = 0;\n v8 = 1;\n v9 = v4 + 1;\n v10 = 1;\n v11 = 0;\n while (1) {\n v12 = v8 + 2 * v10;\n v6 = (uint64_t *)((char *)v6 + 4);\n v13 = v10;\n v9 = (uint64_t *)((char *)v9 + 4);\n v10 = v7 + v11;\n *((uint32_t *)v6 - 1) = v12;\n v11 = v13;\n v8 = v7;\n *((uint32_t *)v9 - 1) = v10;\n if (v6 == (uint64_t *)((char *)v3 + 4 * (unsigned int)(a1 - 2) + 12))\n break;\n v7 = v12;\n }\n }\n v14 = *(uint32_t *)((char *)v3 + v2 - 4);\n free(v3);\n free(v5);\n return v14;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v2;\n uint64_t *v3;\n uint64_t *v4;\n void *v5;\n uint64_t *v6;\n int v7;\n int v8;\n uint64_t *v9;\n int v10;\n int v11;\n int v12;\n int v13;\n unsigned int v14;\n v2 = 4LL * (a1 + 1);\n v3 = malloc(v2);\n v4 = malloc(v2);\n if (!v3 || (v5 = v4) == 0LL) {\n fwrite(\"Memory allocation failed\\n\", 1uLL, 25uLL, _bss_start);\n exit(1);\n }\n *v3 = 1LL;\n *v4 = 4294967296LL;\n if (a1 > 1) {\n v6 = v3 + 1;\n v7 = 0;\n v8 = 1;\n v9 = v4 + 1;\n v10 = 1;\n v11 = 0;\n while (1) {\n v12 = v8 + 2 * v10;\n v6 = (uint64_t *)((char *)v6 + 4);\n v13 = v10;\n v9 = (uint64_t *)((char *)v9 + 4);\n v10 = v7 + v11;\n *((uint32_t *)v6 - 1) = v12;\n v11 = v13;\n v8 = v7;\n *((uint32_t *)v9 - 1) = v10;\n if (v6 == (uint64_t *)((char *)v3 + 4 * (unsigned int)(a1 - 2) + 12))\n break;\n v7 = v12;\n }\n }\n v14 = *(uint32_t *)((char *)v3 + v2 - 4);\n free(v3);\n free(v5);\n return v14;\n}" + }, + { + "index": 5, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int *A = (int *)malloc((n + 1) * sizeof(int));\n int *B = (int *)malloc((n + 1) * sizeof(int));\n if (A == NULL || B == NULL) {\n fprintf(stderr, \"Memory allocation failed\\n\");\n exit(EXIT_FAILURE);\n }\n A[0] = 1;\n A[1] = 0;\n B[0] = 0;\n B[1] = 1;\n for (int i = 2; i <= n; i++) {\n A[i] = A[i - 2] + 2 * B[i - 1];\n B[i] = A[i - 1] + B[i - 2];\n }\n int result = A[n];\n free(A);\n free(B);\n return result;\n}", + "test": "int main() {\n\n assert(func0(2) == 3);\n\n assert(func0(8) == 153);\n\n assert(func0(12) == 2131);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nlea 0x1(%rdi),%r13d\npush %r12\nmovslq %r13d,%r13\npush %rbp\nshl $0x2,%r13\npush %rbx\nmov %edi,%ebx\nmov %r13,%rdi\nsub $0x8,%rsp\ncallq 10b0 \nmov %r13,%rdi\nmov %rax,%rbp\ncallq 10b0 \ntest %rbp,%rbp\nje 136f \nmov %rax,%r12\ntest %rax,%rax\nje 136f \nmovabs $0x100000000,%rax\nmovq $0x1,0x0(%rbp)\nmov %rax,(%r12)\ncmp $0x1,%ebx\njle 1345 \ncmp $0x3,%ebx\njle 1368 \nlea -0x4(%rbx),%eax\nmov $0x1,%esi\nmov $0x1,%ecx\nshr %eax\nlea 0x6(%rax,%rax,1),%rdi\nmov $0x4,%eax\nlea (%rsi,%rcx,2),%esi\nmovl $0x0,-0x4(%rbp,%rax,4)\nmovslq %eax,%rdx\nadd %esi,%ecx\nmov %esi,-0x8(%rbp,%rax,4)\nmovl $0x0,-0x8(%r12,%rax,4)\nmov %ecx,-0x4(%r12,%rax,4)\nadd $0x2,%rax\ncmp %rdi,%rax\njne 12f0 \nnopl 0x0(%rax,%rax,1)\nmov -0x4(%r12,%rdx,4),%ecx\nmov -0x8(%rbp,%rdx,4),%eax\nlea (%rax,%rcx,2),%eax\nmov -0x8(%r12,%rdx,4),%ecx\nadd -0x4(%rbp,%rdx,4),%ecx\nmov %eax,0x0(%rbp,%rdx,4)\nmov %ecx,(%r12,%rdx,4)\nadd $0x1,%rdx\ncmp %edx,%ebx\njge 1320 \nmov %rbp,%rdi\nmov -0x4(%rbp,%r13,1),%r13d\ncallq 1090 \nmov %r12,%rdi\ncallq 1090 \nadd $0x8,%rsp\nmov %r13d,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nmov $0x2,%edx\njmp 1320 \nmov 0x2caa(%rip),%rcx\nmov $0x19,%edx\nmov $0x1,%esi\nlea 0xc7d(%rip),%rdi\ncallq 10d0 \nmov $0x1,%edi\ncallq 10c0 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r13\nmov r13d, edi\npush r12\npush rbp\nlea ebp, [rdi+1]\npush rbx\nmovsxd rbp, ebp\nshl rbp, 2\nmov rdi, rbp; size\nsub rsp, 8\ncall _malloc\nmov rdi, rbp; size\nmov rbx, rax\ncall _malloc\ntest rbx, rbx\njz loc_136D\nmov r12, rax\ntest rax, rax\njz loc_136D\nmov rax, cs:qword_2078\nmov qword ptr [rbx], 1\nmov [r12], rax\ncmp r13d, 1\njle short loc_1345\ncmp r13d, 3\njle loc_1366\nlea eax, [r13-4]\nmov edx, 4\nmov esi, 1\nmov ecx, 1\nshr eax, 1\nlea edi, [rax+3]\nadd rdi, rdi\nloc_12F0:\nlea esi, [rsi+rcx*2]\nmov dword ptr [rbx+rdx*4-4], 0\nmov rax, rdx\nadd ecx, esi\nmov [rbx+rdx*4-8], esi\nmov dword ptr [r12+rdx*4-8], 0\nmov [r12+rdx*4-4], ecx\nadd rdx, 2\ncmp rdi, rdx\njnz short loc_12F0\nloc_131B:\ncdqe\nnop dword ptr [rax]\nloc_1320:\nmov ecx, [r12+rax*4-4]\nmov edx, [rbx+rax*4-8]\nlea edx, [rdx+rcx*2]\nmov [rbx+rax*4], edx\nmov edx, [rbx+rax*4-4]\nadd edx, [r12+rax*4-8]\nmov [r12+rax*4], edx\nadd rax, 1\ncmp r13d, eax\njge short loc_1320\nloc_1345:\nmov rdi, rbx; ptr\nmov ebp, [rbx+rbp-4]\ncall _free\nmov rdi, r12; ptr\ncall _free\nadd rsp, 8\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1366:\nmov eax, 2\njmp short loc_131B\nloc_136D:\nmov rcx, cs:__bss_start; s\nmov edx, 19h; n\nmov esi, 1; size\nlea rdi, aMemoryAllocati; \"Memory allocation failed\\n\"\ncall _fwrite\nmov edi, 1; status\ncall _exit", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n size_t v1; // rbp\n _QWORD *v2; // rbx\n _QWORD *v3; // rax\n _DWORD *v4; // r12\n __int64 v5; // rdx\n int v6; // esi\n int v7; // ecx\n __int64 v8; // rax\n unsigned int v9; // ebp\n\n v1 = 4LL * (a1 + 1);\n v2 = malloc(v1);\n v3 = malloc(v1);\n if ( !v2 || (v4 = v3) == 0LL )\n {\n fwrite(\"Memory allocation failed\\n\", 1uLL, 0x19uLL, _bss_start);\n exit(1);\n }\n *v2 = 1LL;\n *v3 = 0x100000000LL;\n if ( a1 > 1 )\n {\n if ( a1 <= 3 )\n {\n LODWORD(v8) = 2;\n }\n else\n {\n v5 = 2LL;\n v6 = 1;\n v7 = 1;\n do\n {\n v6 += 2 * v7;\n HIDWORD(v2[v5 - 1]) = 0;\n LODWORD(v8) = v5 * 2;\n v7 += v6;\n LODWORD(v2[v5 - 1]) = v6;\n v4[v5 * 2 - 2] = 0;\n v4[v5 * 2 - 1] = v7;\n ++v5;\n }\n while ( ((unsigned int)(a1 - 4) >> 1) + 3 != v5 );\n }\n v8 = (int)v8;\n do\n {\n *((_DWORD *)v2 + v8) = *((_DWORD *)v2 + v8 - 2) + 2 * v4[v8 - 1];\n v4[v8] = v4[v8 - 2] + *((_DWORD *)v2 + v8 - 1);\n ++v8;\n }\n while ( a1 >= (int)v8 );\n }\n v9 = *(_DWORD *)((char *)v2 + v1 - 4);\n free(v2);\n free(v4);\n return v9;\n}", + "ida_strip_asm": "sub_1270:\nendbr64\npush r13\nmov r13d, edi\npush r12\npush rbp\nlea ebp, [rdi+1]\npush rbx\nmovsxd rbp, ebp\nshl rbp, 2\nmov rdi, rbp; size\nsub rsp, 8\ncall _malloc\nmov rdi, rbp; size\nmov rbx, rax\ncall _malloc\ntest rbx, rbx\njz loc_136D\nmov r12, rax\ntest rax, rax\njz loc_136D\nmov rax, cs:qword_2078\nmov qword ptr [rbx], 1\nmov [r12], rax\ncmp r13d, 1\njle short loc_1345\ncmp r13d, 3\njle loc_1366\nlea eax, [r13-4]\nmov edx, 4\nmov esi, 1\nmov ecx, 1\nshr eax, 1\nlea edi, [rax+3]\nadd rdi, rdi\nloc_12F0:\nlea esi, [rsi+rcx*2]\nmov dword ptr [rbx+rdx*4-4], 0\nmov rax, rdx\nadd ecx, esi\nmov [rbx+rdx*4-8], esi\nmov dword ptr [r12+rdx*4-8], 0\nmov [r12+rdx*4-4], ecx\nadd rdx, 2\ncmp rdi, rdx\njnz short loc_12F0\nloc_131B:\ncdqe\nnop dword ptr [rax]\nloc_1320:\nmov ecx, [r12+rax*4-4]\nmov edx, [rbx+rax*4-8]\nlea edx, [rdx+rcx*2]\nmov [rbx+rax*4], edx\nmov edx, [rbx+rax*4-4]\nadd edx, [r12+rax*4-8]\nmov [r12+rax*4], edx\nadd rax, 1\ncmp r13d, eax\njge short loc_1320\nloc_1345:\nmov rdi, rbx; ptr\nmov ebp, [rbx+rbp-4]\ncall _free\nmov rdi, r12; ptr\ncall _free\nadd rsp, 8\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1366:\nmov eax, 2\njmp short loc_131B\nloc_136D:\nmov rcx, cs:stderr; s\nmov edx, 19h; n\nmov esi, 1; size\nlea rdi, aMemoryAllocati; \"Memory allocation failed\\n\"\ncall _fwrite\nmov edi, 1; status\ncall _exit", + "ida_strip_pseudo": "__int64 __fastcall sub_1270(int a1)\n{\n size_t v1; // rbp\n _QWORD *v2; // rbx\n _QWORD *v3; // rax\n _DWORD *v4; // r12\n __int64 v5; // rdx\n int v6; // esi\n int v7; // ecx\n __int64 v8; // rax\n unsigned int v9; // ebp\n\n v1 = 4LL * (a1 + 1);\n v2 = malloc(v1);\n v3 = malloc(v1);\n if ( !v2 || (v4 = v3) == 0LL )\n {\n fwrite(\"Memory allocation failed\\n\", 1uLL, 0x19uLL, stderr);\n exit(1);\n }\n *v2 = 1LL;\n *v3 = 0x100000000LL;\n if ( a1 > 1 )\n {\n if ( a1 <= 3 )\n {\n LODWORD(v8) = 2;\n }\n else\n {\n v5 = 2LL;\n v6 = 1;\n v7 = 1;\n do\n {\n v6 += 2 * v7;\n HIDWORD(v2[v5 - 1]) = 0;\n LODWORD(v8) = v5 * 2;\n v7 += v6;\n LODWORD(v2[v5 - 1]) = v6;\n v4[v5 * 2 - 2] = 0;\n v4[v5 * 2 - 1] = v7;\n ++v5;\n }\n while ( ((unsigned int)(a1 - 4) >> 1) + 3 != v5 );\n }\n v8 = (int)v8;\n do\n {\n *((_DWORD *)v2 + v8) = *((_DWORD *)v2 + v8 - 2) + 2 * v4[v8 - 1];\n v4[v8] = v4[v8 - 2] + *((_DWORD *)v2 + v8 - 1);\n ++v8;\n }\n while ( a1 >= (int)v8 );\n }\n v9 = *(_DWORD *)((char *)v2 + v1 - 4);\n free(v2);\n free(v4);\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1270(int a1) {\n unsigned int v1;\n uint64_t *v2;\n uint64_t *v3;\n uint32_t *v4;\n long long v5;\n int v6;\n int v7;\n long long v8;\n unsigned int v9;\n v1 = 4LL * (a1 + 1);\n v2 = malloc(v1);\n v3 = malloc(v1);\n if (!v2 || (v4 = v3) == 0LL) {\n fwrite(\"Memory allocation failed\\n\", 1uLL, 25uLL, stderr);\n exit(1);\n }\n *v2 = 1LL;\n *v3 = 4294967296LL;\n if (a1 > 1) {\n if (a1 <= 3) {\n LODWORD(v8) = 2;\n } else {\n v5 = 2LL;\n v6 = 1;\n v7 = 1;\n do {\n v6 += 2 * v7;\n HIDWORD(v2[v5 - 1]) = 0;\n LODWORD(v8) = v5 * 2;\n v7 += v6;\n LODWORD(v2[v5 - 1]) = v6;\n v4[v5 * 2 - 2] = 0;\n v4[v5 * 2 - 1] = v7;\n ++v5;\n } while (((unsigned int)(a1 - 4) >> 1) + 3 != v5);\n }\n v8 = (int)v8;\n do {\n *((uint32_t *)v2 + v8) = *((uint32_t *)v2 + v8 - 2) + 2 * v4[v8 - 1];\n v4[v8] = v4[v8 - 2] + *((uint32_t *)v2 + v8 - 1);\n ++v8;\n } while (a1 >= (int)v8);\n }\n v9 = *(uint32_t *)((char *)v2 + v1 - 4);\n free(v2);\n free(v4);\n return v9;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v1;\n uint64_t *v2;\n uint64_t *v3;\n uint32_t *v4;\n long long v5;\n int v6;\n int v7;\n long long v8;\n unsigned int v9;\n v1 = 4LL * (a1 + 1);\n v2 = malloc(v1);\n v3 = malloc(v1);\n if (!v2 || (v4 = v3) == 0LL) {\n fwrite(\"Memory allocation failed\\n\", 1uLL, 25uLL, _bss_start);\n exit(1);\n }\n *v2 = 1LL;\n *v3 = 4294967296LL;\n if (a1 > 1) {\n if (a1 <= 3) {\n LODWORD(v8) = 2;\n } else {\n v5 = 2LL;\n v6 = 1;\n v7 = 1;\n do {\n v6 += 2 * v7;\n HIDWORD(v2[v5 - 1]) = 0;\n LODWORD(v8) = v5 * 2;\n v7 += v6;\n LODWORD(v2[v5 - 1]) = v6;\n v4[v5 * 2 - 2] = 0;\n v4[v5 * 2 - 1] = v7;\n ++v5;\n } while (((unsigned int)(a1 - 4) >> 1) + 3 != v5);\n }\n v8 = (int)v8;\n do {\n *((uint32_t *)v2 + v8) = *((uint32_t *)v2 + v8 - 2) + 2 * v4[v8 - 1];\n v4[v8] = v4[v8 - 2] + *((uint32_t *)v2 + v8 - 1);\n ++v8;\n } while (a1 >= (int)v8);\n }\n v9 = *(uint32_t *)((char *)v2 + v1 - 4);\n free(v2);\n free(v4);\n return v9;\n}" + }, + { + "index": 6, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n\n\n", + "func": "bool func0(int a, int b) { return (a ^ b) && !((a ^ b) & ((a ^ b) - 1)); }", + "test": "int main() {\n\n assert(func0(13,9) == true);\n\n assert(func0(15,8) == false);\n\n assert(func0(2,4) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov %esi,-0x8(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x8(%rbp),%eax\nje 117d \nmov -0x4(%rbp),%eax\nxor -0x8(%rbp),%eax\nmov %eax,%edx\nmov -0x4(%rbp),%eax\nxor -0x8(%rbp),%eax\nsub $0x1,%eax\nand %edx,%eax\ntest %eax,%eax\njne 117d \nmov $0x1,%eax\njmp 1182 \nmov $0x0,%eax\nand $0x1,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_8]\njz short loc_117D\nmov eax, [rbp+var_4]\nxor eax, [rbp+var_8]\nmov edx, eax\nmov eax, [rbp+var_4]\nxor eax, [rbp+var_8]\nsub eax, 1\nand eax, edx\ntest eax, eax\njnz short loc_117D\nmov eax, 1\njmp short loc_1182\nloc_117D:\nmov eax, 0\nloc_1182:\nand eax, 1\npop rbp\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(int a1, int a2)\n{\n return a1 != a2 && ((a2 ^ a1) & ((a2 ^ a1) - 1)) == 0;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_8]\njz short loc_117D\nmov eax, [rbp+var_4]\nxor eax, [rbp+var_8]\nmov edx, eax\nmov eax, [rbp+var_4]\nxor eax, [rbp+var_8]\nsub eax, 1\nand eax, edx\ntest eax, eax\njnz short loc_117D\nmov eax, 1\njmp short loc_1182\nloc_117D:\nmov eax, 0\nloc_1182:\nand eax, 1\npop rbp\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1149(int a1, int a2)\n{\n return a1 != a2 && ((a2 ^ a1) & ((a2 ^ a1) - 1)) == 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1149(int a1, int a2) {\n return a1 != a2 && ((a2 ^ a1) & ((a2 ^ a1) - 1)) == 0;\n}", + "ida_pseudo_norm": "uint8_t func0(int a1, int a2) {\n return a1 != a2 && ((a2 ^ a1) & ((a2 ^ a1) - 1)) == 0;\n}" + }, + { + "index": 7, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char **func0(const char *text) {\n char **result = malloc(sizeof(char *) * (strlen(text) / 2 + 1));\n int count = 0;\n char *copy = strdup(text);\n char *token = strtok(copy, \" \");\n while (token != NULL) {\n char *end = token + strlen(token) - 1;\n while (end > token && (*end == '.' || *end == ',' || *end == '!' ||\n *end == '?' || *end == ';' || *end == ':')) {\n *end = '\\0';\n end--;\n }\n if (strlen(token) >= 4) {\n result[count++] = strdup(token);\n }\n token = strtok(NULL, \" \");\n }\n result[count] = NULL;\n free(copy);\n return result;\n}", + "test": "int main() {\n\n // First assert\n\n {\n\n char **result = func0(\"Please move back to stream\");\n\n assert(strcmp(result[0], \"Please\") == 0);\n\n assert(strcmp(result[1], \"move\") == 0);\n\n assert(strcmp(result[2], \"back\") == 0);\n\n assert(strcmp(result[3], \"stream\") == 0);\n\n assert(result[4] == NULL);\n\n // Free allocated memory\n\n for(int i = 0; result[i] != NULL; i++) {\n\n free(result[i]);\n\n }\n\n free(result);\n\n }\n\n \n\n // Second assert\n\n {\n\n char **result = func0(\"Jing Eco and Tech\");\n\n assert(strcmp(result[0], \"Jing\") == 0);\n\n assert(strcmp(result[1], \"Tech\") == 0);\n\n assert(result[2] == NULL);\n\n // Free allocated memory\n\n for(int i = 0; result[i] != NULL; i++) {\n\n free(result[i]);\n\n }\n\n free(result);\n\n }\n\n \n\n // Third assert\n\n {\n\n char **result = func0(\"Jhingai wulu road Zone 3\");\n\n assert(strcmp(result[0], \"Jhingai\") == 0);\n\n assert(strcmp(result[1], \"wulu\") == 0);\n\n assert(strcmp(result[2], \"road\") == 0);\n\n assert(strcmp(result[3], \"Zone\") == 0);\n\n assert(result[4] == NULL);\n\n // Free allocated memory\n\n for(int i = 0; result[i] != NULL; i++) {\n\n free(result[i]);\n\n }\n\n free(result);\n\n }\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x48,%rsp\nmov %rdi,-0x48(%rbp)\nmov -0x48(%rbp),%rax\nmov %rax,%rdi\ncallq 10c0 \nshr %rax\nadd $0x1,%rax\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 10f0 \nmov %rax,-0x20(%rbp)\nmovl $0x0,-0x34(%rbp)\nmov -0x48(%rbp),%rax\nmov %rax,%rdi\ncallq 1110 \nmov %rax,-0x18(%rbp)\nmov -0x18(%rbp),%rax\nlea 0xda9(%rip),%rsi\nmov %rax,%rdi\ncallq 1100 \nmov %rax,-0x30(%rbp)\njmpq 1336 \nmov -0x30(%rbp),%rax\nmov %rax,%rdi\ncallq 10c0 \nlea -0x1(%rax),%rdx\nmov -0x30(%rbp),%rax\nadd %rdx,%rax\nmov %rax,-0x28(%rbp)\njmp 1299 \nmov -0x28(%rbp),%rax\nmovb $0x0,(%rax)\nsubq $0x1,-0x28(%rbp)\nmov -0x28(%rbp),%rax\ncmp -0x30(%rbp),%rax\njbe 12e5 \nmov -0x28(%rbp),%rax\nmovzbl (%rax),%eax\ncmp $0x2e,%al\nje 128d \nmov -0x28(%rbp),%rax\nmovzbl (%rax),%eax\ncmp $0x2c,%al\nje 128d \nmov -0x28(%rbp),%rax\nmovzbl (%rax),%eax\ncmp $0x21,%al\nje 128d \nmov -0x28(%rbp),%rax\nmovzbl (%rax),%eax\ncmp $0x3f,%al\nje 128d \nmov -0x28(%rbp),%rax\nmovzbl (%rax),%eax\ncmp $0x3b,%al\nje 128d \nmov -0x28(%rbp),%rax\nmovzbl (%rax),%eax\ncmp $0x3a,%al\nje 128d \nmov -0x30(%rbp),%rax\nmov %rax,%rdi\ncallq 10c0 \ncmp $0x3,%rax\njbe 1321 \nmov -0x34(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x34(%rbp)\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x20(%rbp),%rax\nlea (%rdx,%rax,1),%rbx\nmov -0x30(%rbp),%rax\nmov %rax,%rdi\ncallq 1110 \nmov %rax,(%rbx)\nlea 0xce0(%rip),%rsi\nmov $0x0,%edi\ncallq 1100 \nmov %rax,-0x30(%rbp)\ncmpq $0x0,-0x30(%rbp)\njne 1270 \nmov -0x34(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmovq $0x0,(%rax)\nmov -0x18(%rbp),%rax\nmov %rax,%rdi\ncallq 10b0 \nmov -0x20(%rbp),%rax\nadd $0x48,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 48h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nshr rax, 1\nadd rax, 1\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_20], rax\nmov [rbp+var_34], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strdup\nmov [rbp+var_18], rax\nmov rax, [rbp+var_18]\nlea rdx, delim; \" \"\nmov rsi, rdx; delim\nmov rdi, rax; s\ncall _strtok\nmov [rbp+var_30], rax\njmp loc_133C\nloc_1273:\nmov rax, [rbp+var_30]\nmov rdi, rax; s\ncall _strlen\nlea rdx, [rax-1]\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov [rbp+var_28], rax\njmp short loc_129C\nloc_1290:\nmov rax, [rbp+var_28]\nmov byte ptr [rax], 0\nsub [rbp+var_28], 1\nloc_129C:\nmov rax, [rbp+var_28]\ncmp [rbp+var_30], rax\njnb short loc_12E8\nmov rax, [rbp+var_28]\nmovzx eax, byte ptr [rax]\ncmp al, 2Eh ; '.'\njz short loc_1290\nmov rax, [rbp+var_28]\nmovzx eax, byte ptr [rax]\ncmp al, 2Ch ; ','\njz short loc_1290\nmov rax, [rbp+var_28]\nmovzx eax, byte ptr [rax]\ncmp al, 21h ; '!'\njz short loc_1290\nmov rax, [rbp+var_28]\nmovzx eax, byte ptr [rax]\ncmp al, 3Fh ; '?'\njz short loc_1290\nmov rax, [rbp+var_28]\nmovzx eax, byte ptr [rax]\ncmp al, 3Bh ; ';'\njz short loc_1290\nmov rax, [rbp+var_28]\nmovzx eax, byte ptr [rax]\ncmp al, 3Ah ; ':'\njz short loc_1290\nloc_12E8:\nmov rax, [rbp+var_30]\nmov rdi, rax; s\ncall _strlen\ncmp rax, 3\njbe short loc_1324\nmov eax, [rbp+var_34]\nlea edx, [rax+1]\nmov [rbp+var_34], edx\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_20]\nlea rbx, [rdx+rax]\nmov rax, [rbp+var_30]\nmov rdi, rax; s\ncall _strdup\nmov [rbx], rax\nloc_1324:\nlea rax, delim; \" \"\nmov rsi, rax; delim\nmov edi, 0; s\ncall _strtok\nmov [rbp+var_30], rax\nloc_133C:\ncmp [rbp+var_30], 0\njnz loc_1273\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov qword ptr [rax], 0\nmov rax, [rbp+var_18]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_20]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(const char *a1)\n{\n size_t v1; // rax\n int v2; // eax\n int v4; // [rsp+1Ch] [rbp-34h]\n const char *i; // [rsp+20h] [rbp-30h]\n const char *j; // [rsp+28h] [rbp-28h]\n _QWORD *v7; // [rsp+30h] [rbp-20h]\n char *v8; // [rsp+38h] [rbp-18h]\n\n v1 = strlen(a1);\n v7 = malloc(8 * ((v1 >> 1) + 1));\n v4 = 0;\n v8 = strdup(a1);\n for ( i = strtok(v8, \" \"); i; i = strtok(0LL, \" \") )\n {\n for ( j = &i[strlen(i) - 1]; i < j && (*j == 46 || *j == 44 || *j == 33 || *j == 63 || *j == 59 || *j == 58); --j )\n *j = 0;\n if ( strlen(i) > 3 )\n {\n v2 = v4++;\n v7[v2] = strdup(i);\n }\n }\n v7[v4] = 0LL;\n free(v8);\n return v7;\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 48h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nshr rax, 1\nadd rax, 1\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_20], rax\nmov [rbp+var_34], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strdup\nmov [rbp+var_18], rax\nmov rax, [rbp+var_18]\nlea rdx, delim; \" \"\nmov rsi, rdx; delim\nmov rdi, rax; s\ncall _strtok\nmov [rbp+var_30], rax\njmp loc_133C\nloc_1273:\nmov rax, [rbp+var_30]\nmov rdi, rax; s\ncall _strlen\nlea rdx, [rax-1]\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov [rbp+var_28], rax\njmp short loc_129C\nloc_1290:\nmov rax, [rbp+var_28]\nmov byte ptr [rax], 0\nsub [rbp+var_28], 1\nloc_129C:\nmov rax, [rbp+var_28]\ncmp [rbp+var_30], rax\njnb short loc_12E8\nmov rax, [rbp+var_28]\nmovzx eax, byte ptr [rax]\ncmp al, 2Eh ; '.'\njz short loc_1290\nmov rax, [rbp+var_28]\nmovzx eax, byte ptr [rax]\ncmp al, 2Ch ; ','\njz short loc_1290\nmov rax, [rbp+var_28]\nmovzx eax, byte ptr [rax]\ncmp al, 21h ; '!'\njz short loc_1290\nmov rax, [rbp+var_28]\nmovzx eax, byte ptr [rax]\ncmp al, 3Fh ; '?'\njz short loc_1290\nmov rax, [rbp+var_28]\nmovzx eax, byte ptr [rax]\ncmp al, 3Bh ; ';'\njz short loc_1290\nmov rax, [rbp+var_28]\nmovzx eax, byte ptr [rax]\ncmp al, 3Ah ; ':'\njz short loc_1290\nloc_12E8:\nmov rax, [rbp+var_30]\nmov rdi, rax; s\ncall _strlen\ncmp rax, 3\njbe short loc_1324\nmov eax, [rbp+var_34]\nlea edx, [rax+1]\nmov [rbp+var_34], edx\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_20]\nlea rbx, [rdx+rax]\nmov rax, [rbp+var_30]\nmov rdi, rax; s\ncall _strdup\nmov [rbx], rax\nloc_1324:\nlea rax, delim; \" \"\nmov rsi, rax; delim\nmov edi, 0; s\ncall _strtok\nmov [rbp+var_30], rax\nloc_133C:\ncmp [rbp+var_30], 0\njnz loc_1273\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov qword ptr [rax], 0\nmov rax, [rbp+var_18]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_20]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1209(const char *a1)\n{\n size_t v1; // rax\n int v2; // eax\n int v4; // [rsp+1Ch] [rbp-34h]\n const char *i; // [rsp+20h] [rbp-30h]\n const char *j; // [rsp+28h] [rbp-28h]\n _QWORD *v7; // [rsp+30h] [rbp-20h]\n char *v8; // [rsp+38h] [rbp-18h]\n\n v1 = strlen(a1);\n v7 = malloc(8 * ((v1 >> 1) + 1));\n v4 = 0;\n v8 = strdup(a1);\n for ( i = strtok(v8, \" \"); i; i = strtok(0LL, \" \") )\n {\n for ( j = &i[strlen(i) - 1]; i < j && (*j == 46 || *j == 44 || *j == 33 || *j == 63 || *j == 59 || *j == 58); --j )\n *j = 0;\n if ( strlen(i) > 3 )\n {\n v2 = v4++;\n v7[v2] = strdup(i);\n }\n }\n v7[v4] = 0LL;\n free(v8);\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1209(const char *a1) {\n unsigned int v1;\n int v2;\n int v4;\n const char *i;\n const char *j;\n uint64_t *v7;\n char *v8;\n v1 = strlen(a1);\n v7 = malloc(8 * ((v1 >> 1) + 1));\n v4 = 0;\n v8 = strdup(a1);\n for (i = strtok(v8, \" \"); i; i = strtok(0LL, \" \")) {\n for (j = &i[strlen(i) - 1]; i < j && (*j == 46 || *j == 44 || *j == 33 ||\n *j == 63 || *j == 59 || *j == 58);\n --j)\n *j = 0;\n if (strlen(i) > 3) {\n v2 = v4++;\n v7[v2] = strdup(i);\n }\n }\n v7[v4] = 0LL;\n free(v8);\n return v7;\n}", + "ida_pseudo_norm": "uint64_t *func0(const char *a1) {\n unsigned int v1;\n int v2;\n int v4;\n const char *i;\n const char *j;\n uint64_t *v7;\n char *v8;\n v1 = strlen(a1);\n v7 = malloc(8 * ((v1 >> 1) + 1));\n v4 = 0;\n v8 = strdup(a1);\n for (i = strtok(v8, \" \"); i; i = strtok(0LL, \" \")) {\n for (j = &i[strlen(i) - 1]; i < j && (*j == 46 || *j == 44 || *j == 33 ||\n *j == 63 || *j == 59 || *j == 58);\n --j)\n *j = 0;\n if (strlen(i) > 3) {\n v2 = v4++;\n v7[v2] = strdup(i);\n }\n }\n v7[v4] = 0LL;\n free(v8);\n return v7;\n}" + }, + { + "index": 7, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char **func0(const char *text) {\n char **result = malloc(sizeof(char *) * (strlen(text) / 2 + 1));\n int count = 0;\n char *copy = strdup(text);\n char *token = strtok(copy, \" \");\n while (token != NULL) {\n char *end = token + strlen(token) - 1;\n while (end > token && (*end == '.' || *end == ',' || *end == '!' ||\n *end == '?' || *end == ';' || *end == ':')) {\n *end = '\\0';\n end--;\n }\n if (strlen(token) >= 4) {\n result[count++] = strdup(token);\n }\n token = strtok(NULL, \" \");\n }\n result[count] = NULL;\n free(copy);\n return result;\n}", + "test": "int main() {\n\n // First assert\n\n {\n\n char **result = func0(\"Please move back to stream\");\n\n assert(strcmp(result[0], \"Please\") == 0);\n\n assert(strcmp(result[1], \"move\") == 0);\n\n assert(strcmp(result[2], \"back\") == 0);\n\n assert(strcmp(result[3], \"stream\") == 0);\n\n assert(result[4] == NULL);\n\n // Free allocated memory\n\n for(int i = 0; result[i] != NULL; i++) {\n\n free(result[i]);\n\n }\n\n free(result);\n\n }\n\n \n\n // Second assert\n\n {\n\n char **result = func0(\"Jing Eco and Tech\");\n\n assert(strcmp(result[0], \"Jing\") == 0);\n\n assert(strcmp(result[1], \"Tech\") == 0);\n\n assert(result[2] == NULL);\n\n // Free allocated memory\n\n for(int i = 0; result[i] != NULL; i++) {\n\n free(result[i]);\n\n }\n\n free(result);\n\n }\n\n \n\n // Third assert\n\n {\n\n char **result = func0(\"Jhingai wulu road Zone 3\");\n\n assert(strcmp(result[0], \"Jhingai\") == 0);\n\n assert(strcmp(result[1], \"wulu\") == 0);\n\n assert(strcmp(result[2], \"road\") == 0);\n\n assert(strcmp(result[3], \"Zone\") == 0);\n\n assert(result[4] == NULL);\n\n // Free allocated memory\n\n for(int i = 0; result[i] != NULL; i++) {\n\n free(result[i]);\n\n }\n\n free(result);\n\n }\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov %rdi,%rbx\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nsub $0x1,%rax\nshr %rax\nlea 0x8(,%rax,8),%rdi\ncallq 10b0 \nmov %rax,%r14\nmov %rbx,%rdi\ncallq 10d0 \nmov %rax,0x8(%rsp)\nlea 0xde7(%rip),%rsi\nmov %rax,%rdi\ncallq 10c0 \ntest %rax,%rax\nje 12ca \nmov %rax,%rsi\nmov $0x0,%r13d\nmov $0xffffffffffffffff,%r12\nmov $0x0,%ebp\nmovabs $0x8c00500200000000,%rbx\njmp 1299 \nbt %rdx,%rbx\njae 1269 \nmovb $0x0,(%rax)\nsub $0x1,%rax\ncmp %rsi,%rax\nje 1269 \nmovzbl (%rax),%edx\ncmp $0x3f,%dl\njbe 124f \nmov %r12,%rcx\nmov %rsi,%rdi\nmov %ebp,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nsub $0x1,%rcx\ncmp $0x3,%rcx\nja 12b2 \nlea 0xd7d(%rip),%rsi\nmov $0x0,%edi\ncallq 10c0 \nmov %rax,%rsi\ntest %rax,%rax\nje 12d0 \nmov %r12,%rcx\nmov %rsi,%rdi\nmov %ebp,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nlea -0x2(%rsi,%rcx,1),%rax\ncmp %rsi,%rax\nja 1261 \njmp 1269 \nlea 0x1(%r13),%r15d\nmov %rsi,%rdi\ncallq 10d0 \nmovslq %r13d,%r13\nmov %rax,(%r14,%r13,8)\nmov %r15d,%r13d\njmp 1280 \nmov $0x0,%r13d\nmovslq %r13d,%r13\nmovq $0x0,(%r14,%r13,8)\nmov 0x8(%rsp),%rdi\ncallq 1090 \nmov %r14,%rax\nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov rbx, rdi\ncall _strlen\nshr rax, 1\nlea rdi, ds:8[rax*8]; size\ncall _malloc\nmov r14, rax\nmov rdi, rbx; s\ncall _strdup\nmov [rsp+48h+ptr], rax\nlea rsi, delim; \" \"\nmov rdi, rax; s\ncall _strtok\ntest rax, rax\njz loc_12E1\nmov rbx, rax\nmov r12d, 0\nmov rbp, 8C00500200000000h\nlea r13, delim; \" \"\njmp short loc_129A\nloc_1277:\nmov rdi, rbx; s\ncall _strlen\ncmp rax, 3\nja short loc_12C8\nloc_1285:\nmov rsi, r13; delim\nmov edi, 0; s\ncall _strtok\nmov rbx, rax\ntest rax, rax\njz short loc_12E7\nloc_129A:\nmov rdi, rbx; s\ncall _strlen\nlea rax, [rbx+rax-1]\ncmp rbx, rax\njnb short loc_1277\nloc_12AC:\nmovzx edx, byte ptr [rax]\ncmp dl, 3Fh ; '?'\nja short loc_1277\nbt rbp, rdx\njnb short loc_1277\nmov byte ptr [rax], 0\nsub rax, 1\ncmp rax, rbx\njnz short loc_12AC\njmp short loc_1277\nloc_12C8:\nlea r15d, [r12+1]\nmov rdi, rbx; s\ncall _strdup\nmovsxd r12, r12d\nmov [r14+r12*8], rax\nmov r12d, r15d\njmp short loc_1285\nloc_12E1:\nmov r12d, 0\nloc_12E7:\nmovsxd r12, r12d\nmov qword ptr [r14+r12*8], 0\nmov rdi, [rsp+48h+ptr]; ptr\ncall _free\nmov rax, r14\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(char *s)\n{\n size_t v1; // rax\n _QWORD *v2; // r14\n char *v3; // rax\n char *v4; // rbx\n int v5; // r12d\n unsigned __int64 v6; // rbp\n char *v7; // rax\n unsigned __int64 v8; // rdx\n char *ptr; // [rsp+8h] [rbp-40h]\n\n v1 = strlen(s);\n v2 = malloc(8 * (v1 >> 1) + 8);\n ptr = strdup(s);\n v3 = strtok(ptr, \" \");\n if ( v3 )\n {\n v4 = v3;\n v5 = 0;\n v6 = 0x8C00500200000000LL;\n do\n {\n v7 = &v4[strlen(v4) - 1];\n if ( v4 < v7 )\n {\n do\n {\n v8 = (unsigned __int8)*v7;\n if ( (unsigned __int8)v8 > 0x3Fu )\n break;\n if ( !_bittest64((const __int64 *)&v6, v8) )\n break;\n *v7-- = 0;\n }\n while ( v7 != v4 );\n }\n if ( strlen(v4) > 3 )\n v2[v5++] = strdup(v4);\n v4 = strtok(0LL, \" \");\n }\n while ( v4 );\n }\n else\n {\n v5 = 0;\n }\n v2[v5] = 0LL;\n free(ptr);\n return v2;\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov rbx, rdi\ncall _strlen\nshr rax, 1\nlea rdi, ds:8[rax*8]; size\ncall _malloc\nmov r14, rax\nmov rdi, rbx; s\ncall _strdup\nmov [rsp+48h+ptr], rax\nlea rsi, delim; \" \"\nmov rdi, rax; s\ncall _strtok\ntest rax, rax\njz loc_12E1\nmov rbx, rax\nmov r12d, 0\nmov rbp, 8C00500200000000h\nlea r13, delim; \" \"\njmp short loc_129A\nloc_1277:\nmov rdi, rbx; s\ncall _strlen\ncmp rax, 3\nja short loc_12C8\nloc_1285:\nmov rsi, r13; delim\nmov edi, 0; s\ncall _strtok\nmov rbx, rax\ntest rax, rax\njz short loc_12E7\nloc_129A:\nmov rdi, rbx; s\ncall _strlen\nlea rax, [rbx+rax-1]\ncmp rbx, rax\njnb short loc_1277\nloc_12AC:\nmovzx edx, byte ptr [rax]\ncmp dl, 3Fh ; '?'\nja short loc_1277\nbt rbp, rdx\njnb short loc_1277\nmov byte ptr [rax], 0\nsub rax, 1\ncmp rax, rbx\njnz short loc_12AC\njmp short loc_1277\nloc_12C8:\nlea r15d, [r12+1]\nmov rdi, rbx; s\ncall _strdup\nmovsxd r12, r12d\nmov [r14+r12*8], rax\nmov r12d, r15d\njmp short loc_1285\nloc_12E1:\nmov r12d, 0\nloc_12E7:\nmovsxd r12, r12d\nmov qword ptr [r14+r12*8], 0\nmov rdi, [rsp+48h+ptr]; ptr\ncall _free\nmov rax, r14\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1209(char *s)\n{\n size_t v1; // rax\n _QWORD *v2; // r14\n char *v3; // rax\n char *v4; // rbx\n int v5; // r12d\n unsigned __int64 v6; // rbp\n char *v7; // rax\n unsigned __int64 v8; // rdx\n char *ptr; // [rsp+8h] [rbp-40h]\n\n v1 = strlen(s);\n v2 = malloc(8 * (v1 >> 1) + 8);\n ptr = strdup(s);\n v3 = strtok(ptr, \" \");\n if ( v3 )\n {\n v4 = v3;\n v5 = 0;\n v6 = 0x8C00500200000000LL;\n do\n {\n v7 = &v4[strlen(v4) - 1];\n if ( v4 < v7 )\n {\n do\n {\n v8 = (unsigned __int8)*v7;\n if ( (unsigned __int8)v8 > 0x3Fu )\n break;\n if ( !_bittest64((const __int64 *)&v6, v8) )\n break;\n *v7-- = 0;\n }\n while ( v7 != v4 );\n }\n if ( strlen(v4) > 3 )\n v2[v5++] = strdup(v4);\n v4 = strtok(0LL, \" \");\n }\n while ( v4 );\n }\n else\n {\n v5 = 0;\n }\n v2[v5] = 0LL;\n free(ptr);\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1209(char *s) {\n unsigned int v1;\n uint64_t *v2;\n char *v3;\n char *v4;\n int v5;\n unsigned long long v6;\n char *v7;\n unsigned long long v8;\n char *ptr;\n v1 = strlen(s);\n v2 = malloc(8 * (v1 >> 1) + 8);\n ptr = strdup(s);\n v3 = strtok(ptr, \" \");\n if (v3) {\n v4 = v3;\n v5 = 0;\n v6 = 10088151134830067712LL;\n do {\n v7 = &v4[strlen(v4) - 1];\n if (v4 < v7) {\n do {\n v8 = (unsigned char)*v7;\n if ((unsigned char)v8 > 63u) break;\n if (!_bittest64((const long long *)&v6, v8)) break;\n *v7-- = 0;\n } while (v7 != v4);\n }\n if (strlen(v4) > 3) v2[v5++] = strdup(v4);\n v4 = strtok(0LL, \" \");\n } while (v4);\n } else {\n v5 = 0;\n }\n v2[v5] = 0LL;\n free(ptr);\n return v2;\n}", + "ida_pseudo_norm": "uint64_t *func0(char *s) {\n unsigned int v1;\n uint64_t *v2;\n char *v3;\n char *v4;\n int v5;\n unsigned long long v6;\n char *v7;\n unsigned long long v8;\n char *ptr;\n v1 = strlen(s);\n v2 = malloc(8 * (v1 >> 1) + 8);\n ptr = strdup(s);\n v3 = strtok(ptr, \" \");\n if (v3) {\n v4 = v3;\n v5 = 0;\n v6 = 10088151134830067712LL;\n do {\n v7 = &v4[strlen(v4) - 1];\n if (v4 < v7) {\n do {\n v8 = (unsigned char)*v7;\n if ((unsigned char)v8 > 63u) break;\n if (!_bittest64((const long long *)&v6, v8)) break;\n *v7-- = 0;\n } while (v7 != v4);\n }\n if (strlen(v4) > 3) v2[v5++] = strdup(v4);\n v4 = strtok(0LL, \" \");\n } while (v4);\n } else {\n v5 = 0;\n }\n v2[v5] = 0LL;\n free(ptr);\n return v2;\n}" + }, + { + "index": 7, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char **func0(const char *text) {\n char **result = malloc(sizeof(char *) * (strlen(text) / 2 + 1));\n int count = 0;\n char *copy = strdup(text);\n char *token = strtok(copy, \" \");\n while (token != NULL) {\n char *end = token + strlen(token) - 1;\n while (end > token && (*end == '.' || *end == ',' || *end == '!' ||\n *end == '?' || *end == ';' || *end == ':')) {\n *end = '\\0';\n end--;\n }\n if (strlen(token) >= 4) {\n result[count++] = strdup(token);\n }\n token = strtok(NULL, \" \");\n }\n result[count] = NULL;\n free(copy);\n return result;\n}", + "test": "int main() {\n\n // First assert\n\n {\n\n char **result = func0(\"Please move back to stream\");\n\n assert(strcmp(result[0], \"Please\") == 0);\n\n assert(strcmp(result[1], \"move\") == 0);\n\n assert(strcmp(result[2], \"back\") == 0);\n\n assert(strcmp(result[3], \"stream\") == 0);\n\n assert(result[4] == NULL);\n\n // Free allocated memory\n\n for(int i = 0; result[i] != NULL; i++) {\n\n free(result[i]);\n\n }\n\n free(result);\n\n }\n\n \n\n // Second assert\n\n {\n\n char **result = func0(\"Jing Eco and Tech\");\n\n assert(strcmp(result[0], \"Jing\") == 0);\n\n assert(strcmp(result[1], \"Tech\") == 0);\n\n assert(result[2] == NULL);\n\n // Free allocated memory\n\n for(int i = 0; result[i] != NULL; i++) {\n\n free(result[i]);\n\n }\n\n free(result);\n\n }\n\n \n\n // Third assert\n\n {\n\n char **result = func0(\"Jhingai wulu road Zone 3\");\n\n assert(strcmp(result[0], \"Jhingai\") == 0);\n\n assert(strcmp(result[1], \"wulu\") == 0);\n\n assert(strcmp(result[2], \"road\") == 0);\n\n assert(strcmp(result[3], \"Zone\") == 0);\n\n assert(result[4] == NULL);\n\n // Free allocated memory\n\n for(int i = 0; result[i] != NULL; i++) {\n\n free(result[i]);\n\n }\n\n free(result);\n\n }\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\nmov %rdi,%rbp\npush %rbx\nsub $0x18,%rsp\ncallq 10b0 \nshr %rax\nlea 0x8(,%rax,8),%rdi\ncallq 10d0 \nmov %rbp,%rdi\nmov %rax,%r12\ncallq 10f0 \nlea 0xa28(%rip),%rsi\nmov %rax,%rdi\nmov %rax,0x8(%rsp)\ncallq 10e0 \ntest %rax,%rax\nje 1685 \nmovabs $0x8c00500200000000,%r15\nmov %rax,%rbp\nxor %ebx,%ebx\njmp 163b \nnopl 0x0(%rax,%rax,1)\nmov %rbp,%rdi\ncallq 10b0 \nmovslq %ebx,%rdx\nlea 0x0(,%rdx,8),%r13\nlea (%r12,%r13,1),%r14\ncmp $0x3,%rax\nja 1670 \nlea 0x9d8(%rip),%rsi\nxor %edi,%edi\ncallq 10e0 \nmov %rax,%rbp\ntest %rax,%rax\nje 1688 \nmov %rbp,%rdi\ncallq 10b0 \nlea -0x1(%rbp,%rax,1),%rdx\ncmp %rbp,%rdx\njbe 1610 \nnopl (%rax)\nmovzbl (%rdx),%eax\ncmp $0x3f,%al\nja 1608 \nbt %rax,%r15\njae 1608 \nmovb $0x0,(%rdx)\nsub $0x1,%rdx\ncmp %rbp,%rdx\njne 1650 \njmp 1608 \nnopl 0x0(%rax,%rax,1)\nmov %rbp,%rdi\nadd $0x1,%ebx\ncallq 10f0 \nmov %rax,(%r14)\nlea 0x8(%r12,%r13,1),%r14\njmp 1625 \nmov %r12,%r14\nmovq $0x0,(%r14)\nmov 0x8(%rsp),%rdi\ncallq 10a0 \nadd $0x18,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\nlea rbp, delim; \" \"\npush rbx\nmov rbx, rdi\nsub rsp, 18h\ncall _strlen\nshr rax, 1\nlea rdi, ds:8[rax*8]; size\ncall _malloc\nmov rdi, rbx; s\nmov r12, rax\ncall _strdup\nmov rsi, rbp; delim\nmov rdi, rax; s\nmov [rsp+48h+ptr], rax\ncall _strtok\ntest rax, rax\njz loc_166D\nmov r13, 8C00500200000000h\nmov r14, rax\nxor ebx, ebx\nnop dword ptr [rax+00h]\nloc_15D8:\nmov rdi, r14; s\ncall _strlen\nlea rdx, [r14+rax-1]\ncmp r14, rdx\njnb short loc_1612\nnop word ptr [rax+rax+00h]\nloc_15F0:\nmovzx ecx, byte ptr [rdx]\ncmp cl, 3Fh ; '?'\nja short loc_160A\nbt r13, rcx\njnb short loc_160A\nmov byte ptr [rdx], 0\nsub rdx, 1\ncmp rdx, r14\njnz short loc_15F0\nloc_160A:\nmov rdi, r14; s\ncall _strlen\nloc_1612:\ncmp rax, 3\nja short loc_1658\nloc_1618:\nmov rsi, rbp; delim\nxor edi, edi; s\ncall _strtok\nmov r14, rax\ntest rax, rax\njnz short loc_15D8\nlea rax, [r12+rbx*8]\nloc_162E:\nmov qword ptr [rax], 0\nmov rdi, [rsp+48h+ptr]; ptr\ncall _free\nadd rsp, 18h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1658:\nmov rdi, r14; s\nlea r15d, [rbx+1]\ncall _strdup\nmov [r12+rbx*8], rax\nmovsxd rbx, r15d\njmp short loc_1618\nloc_166D:\nmov rax, r12\njmp short loc_162E", + "ida_pseudo": "_QWORD *__fastcall func0(char *s)\n{\n size_t v1; // rax\n _QWORD *v2; // r12\n char *v3; // rax\n unsigned __int64 v4; // r13\n char *v5; // r14\n __int64 v6; // rbx\n size_t v7; // rax\n char *v8; // rdx\n unsigned __int64 v9; // rcx\n _QWORD *v10; // rax\n char *ptr; // [rsp+8h] [rbp-40h]\n\n v1 = strlen(s);\n v2 = malloc(8 * (v1 >> 1) + 8);\n ptr = strdup(s);\n v3 = strtok(ptr, \" \");\n if ( v3 )\n {\n v4 = 0x8C00500200000000LL;\n v5 = v3;\n v6 = 0LL;\n do\n {\n v7 = strlen(v5);\n v8 = &v5[v7 - 1];\n if ( v5 < v8 )\n {\n do\n {\n v9 = (unsigned __int8)*v8;\n if ( (unsigned __int8)v9 > 0x3Fu )\n break;\n if ( !_bittest64((const __int64 *)&v4, v9) )\n break;\n *v8-- = 0;\n }\n while ( v8 != v5 );\n v7 = strlen(v5);\n }\n if ( v7 > 3 )\n {\n v2[v6] = strdup(v5);\n v6 = (int)v6 + 1;\n }\n v5 = strtok(0LL, \" \");\n }\n while ( v5 );\n v10 = &v2[v6];\n }\n else\n {\n v10 = v2;\n }\n *v10 = 0LL;\n free(ptr);\n return v2;\n}", + "ida_strip_asm": "sub_1570:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\nlea rbp, delim; \" \"\npush rbx\nmov rbx, rdi\nsub rsp, 18h\ncall _strlen\nshr rax, 1\nlea rdi, ds:8[rax*8]; size\ncall _malloc\nmov rdi, rbx; s\nmov r12, rax\ncall _strdup\nmov rsi, rbp; delim\nmov rdi, rax; s\nmov [rsp+48h+ptr], rax\ncall _strtok\ntest rax, rax\njz loc_166D\nmov r13, 8C00500200000000h\nmov r14, rax\nxor ebx, ebx\nnop dword ptr [rax+00h]\nloc_15D8:\nmov rdi, r14; s\ncall _strlen\nlea rdx, [r14+rax-1]\ncmp r14, rdx\njnb short loc_1612\nnop word ptr [rax+rax+00h]\nloc_15F0:\nmovzx ecx, byte ptr [rdx]\ncmp cl, 3Fh ; '?'\nja short loc_160A\nbt r13, rcx\njnb short loc_160A\nmov byte ptr [rdx], 0\nsub rdx, 1\ncmp rdx, r14\njnz short loc_15F0\nloc_160A:\nmov rdi, r14; s\ncall _strlen\nloc_1612:\ncmp rax, 3\nja short loc_1658\nloc_1618:\nmov rsi, rbp; delim\nxor edi, edi; s\ncall _strtok\nmov r14, rax\ntest rax, rax\njnz short loc_15D8\nlea rax, [r12+rbx*8]\nloc_162E:\nmov qword ptr [rax], 0\nmov rdi, [rsp+48h+ptr]; ptr\ncall _free\nadd rsp, 18h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1658:\nmov rdi, r14; s\nlea r15d, [rbx+1]\ncall _strdup\nmov [r12+rbx*8], rax\nmovsxd rbx, r15d\njmp short loc_1618\nloc_166D:\nmov rax, r12\njmp short loc_162E", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1570(char *s)\n{\n size_t v1; // rax\n _QWORD *v2; // r12\n char *v3; // rax\n unsigned __int64 v4; // r13\n char *v5; // r14\n __int64 v6; // rbx\n size_t v7; // rax\n char *v8; // rdx\n unsigned __int64 v9; // rcx\n _QWORD *v10; // rax\n char *ptr; // [rsp+8h] [rbp-40h]\n\n v1 = strlen(s);\n v2 = malloc(8 * (v1 >> 1) + 8);\n ptr = strdup(s);\n v3 = strtok(ptr, \" \");\n if ( v3 )\n {\n v4 = 0x8C00500200000000LL;\n v5 = v3;\n v6 = 0LL;\n do\n {\n v7 = strlen(v5);\n v8 = &v5[v7 - 1];\n if ( v5 < v8 )\n {\n do\n {\n v9 = (unsigned __int8)*v8;\n if ( (unsigned __int8)v9 > 0x3Fu )\n break;\n if ( !_bittest64((const __int64 *)&v4, v9) )\n break;\n *v8-- = 0;\n }\n while ( v8 != v5 );\n v7 = strlen(v5);\n }\n if ( v7 > 3 )\n {\n v2[v6] = strdup(v5);\n v6 = (int)v6 + 1;\n }\n v5 = strtok(0LL, \" \");\n }\n while ( v5 );\n v10 = &v2[v6];\n }\n else\n {\n v10 = v2;\n }\n *v10 = 0LL;\n free(ptr);\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1570(char *s) {\n unsigned int v1;\n uint64_t *v2;\n char *v3;\n unsigned long long v4;\n char *v5;\n long long v6;\n unsigned int v7;\n char *v8;\n unsigned long long v9;\n uint64_t *v10;\n char *ptr;\n v1 = strlen(s);\n v2 = malloc(8 * (v1 >> 1) + 8);\n ptr = strdup(s);\n v3 = strtok(ptr, \" \");\n if (v3) {\n v4 = 10088151134830067712LL;\n v5 = v3;\n v6 = 0LL;\n do {\n v7 = strlen(v5);\n v8 = &v5[v7 - 1];\n if (v5 < v8) {\n do {\n v9 = (unsigned char)*v8;\n if ((unsigned char)v9 > 63u) break;\n if (!_bittest64((const long long *)&v4, v9)) break;\n *v8-- = 0;\n } while (v8 != v5);\n v7 = strlen(v5);\n }\n if (v7 > 3) {\n v2[v6] = strdup(v5);\n v6 = (int)v6 + 1;\n }\n v5 = strtok(0LL, \" \");\n } while (v5);\n v10 = &v2[v6];\n } else {\n v10 = v2;\n }\n *v10 = 0LL;\n free(ptr);\n return v2;\n}", + "ida_pseudo_norm": "uint64_t *func0(char *s) {\n unsigned int v1;\n uint64_t *v2;\n char *v3;\n unsigned long long v4;\n char *v5;\n long long v6;\n unsigned int v7;\n char *v8;\n unsigned long long v9;\n uint64_t *v10;\n char *ptr;\n v1 = strlen(s);\n v2 = malloc(8 * (v1 >> 1) + 8);\n ptr = strdup(s);\n v3 = strtok(ptr, \" \");\n if (v3) {\n v4 = 10088151134830067712LL;\n v5 = v3;\n v6 = 0LL;\n do {\n v7 = strlen(v5);\n v8 = &v5[v7 - 1];\n if (v5 < v8) {\n do {\n v9 = (unsigned char)*v8;\n if ((unsigned char)v9 > 63u) break;\n if (!_bittest64((const long long *)&v4, v9)) break;\n *v8-- = 0;\n } while (v8 != v5);\n v7 = strlen(v5);\n }\n if (v7 > 3) {\n v2[v6] = strdup(v5);\n v6 = (int)v6 + 1;\n }\n v5 = strtok(0LL, \" \");\n } while (v5);\n v10 = &v2[v6];\n } else {\n v10 = v2;\n }\n *v10 = 0LL;\n free(ptr);\n return v2;\n}" + }, + { + "index": 7, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char **func0(const char *text) {\n char **result = malloc(sizeof(char *) * (strlen(text) / 2 + 1));\n int count = 0;\n char *copy = strdup(text);\n char *token = strtok(copy, \" \");\n while (token != NULL) {\n char *end = token + strlen(token) - 1;\n while (end > token && (*end == '.' || *end == ',' || *end == '!' ||\n *end == '?' || *end == ';' || *end == ':')) {\n *end = '\\0';\n end--;\n }\n if (strlen(token) >= 4) {\n result[count++] = strdup(token);\n }\n token = strtok(NULL, \" \");\n }\n result[count] = NULL;\n free(copy);\n return result;\n}", + "test": "int main() {\n\n // First assert\n\n {\n\n char **result = func0(\"Please move back to stream\");\n\n assert(strcmp(result[0], \"Please\") == 0);\n\n assert(strcmp(result[1], \"move\") == 0);\n\n assert(strcmp(result[2], \"back\") == 0);\n\n assert(strcmp(result[3], \"stream\") == 0);\n\n assert(result[4] == NULL);\n\n // Free allocated memory\n\n for(int i = 0; result[i] != NULL; i++) {\n\n free(result[i]);\n\n }\n\n free(result);\n\n }\n\n \n\n // Second assert\n\n {\n\n char **result = func0(\"Jing Eco and Tech\");\n\n assert(strcmp(result[0], \"Jing\") == 0);\n\n assert(strcmp(result[1], \"Tech\") == 0);\n\n assert(result[2] == NULL);\n\n // Free allocated memory\n\n for(int i = 0; result[i] != NULL; i++) {\n\n free(result[i]);\n\n }\n\n free(result);\n\n }\n\n \n\n // Third assert\n\n {\n\n char **result = func0(\"Jhingai wulu road Zone 3\");\n\n assert(strcmp(result[0], \"Jhingai\") == 0);\n\n assert(strcmp(result[1], \"wulu\") == 0);\n\n assert(strcmp(result[2], \"road\") == 0);\n\n assert(strcmp(result[3], \"Zone\") == 0);\n\n assert(result[4] == NULL);\n\n // Free allocated memory\n\n for(int i = 0; result[i] != NULL; i++) {\n\n free(result[i]);\n\n }\n\n free(result);\n\n }\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\nmov %rdi,%rbp\npush %rbx\nsub $0x18,%rsp\ncallq 10b0 \nshr %rax\nlea 0x8(,%rax,8),%rdi\ncallq 10d0 \nmov %rbp,%rdi\nmov %rax,%r12\ncallq 10f0 \nlea 0xa28(%rip),%rsi\nmov %rax,%rdi\nmov %rax,0x8(%rsp)\ncallq 10e0 \ntest %rax,%rax\nje 16d1 \nmov %rax,%r14\nxor %ebp,%ebp\nxor %ebx,%ebx\nmovabs $0x8c00500200000000,%r13\nnopl 0x0(%rax,%rax,1)\nmov %r14,%rdi\ncallq 10b0 \nlea -0x1(%r14,%rax,1),%rdx\ncmp %r14,%rdx\njbe 162f \nnopw 0x0(%rax,%rax,1)\nmovzbl (%rdx),%eax\ncmp $0x3f,%al\njbe 1680 \nmov %r14,%rdi\ncallq 10b0 \nlea 0x0(,%rbx,8),%rdx\nlea (%r12,%rdx,1),%r15\ncmp $0x3,%rax\nja 1698 \nlea 0x9bc(%rip),%rsi\nxor %edi,%edi\ncallq 10e0 \nmov %rax,%r14\ntest %rax,%rax\njne 1608 \nmovq $0x0,(%r15)\nmov 0x8(%rsp),%rdi\ncallq 10a0 \nadd $0x18,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw 0x0(%rax,%rax,1)\nbt %rax,%r13\njae 1627 \nmovb $0x0,(%rdx)\nsub $0x1,%rdx\ncmp %r14,%rdx\njne 1620 \njmp 1627 \nnopl 0x0(%rax)\nmov %r14,%rdi\nmov %rdx,(%rsp)\nadd $0x1,%ebp\ncallq 10f0 \nmov (%rsp),%rdx\nlea 0x952(%rip),%rsi\nxor %edi,%edi\nmov %rax,(%r15)\nlea 0x8(%r12,%rdx,1),%r15\ncallq 10e0 \nmov %rax,%r14\ntest %rax,%rax\nje 1657 \nmovslq %ebp,%rbx\njmpq 1608 \nmov %r12,%r15\njmp 1657 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\nlea rbp, delim; \" \"\npush rbx\nmov rbx, rdi\nsub rsp, 18h\ncall _strlen\nshr rax, 1\nlea rdi, ds:8[rax*8]; size\ncall _malloc\nmov rdi, rbx; s\nmov r12, rax\ncall _strdup\nmov rsi, rbp; delim\nmov rdi, rax; s\nmov [rsp+48h+ptr], rax\ncall _strtok\ntest rax, rax\njz loc_1683\nmov r13, 8C00500200000000h\nmov r14, rax\nxor ebx, ebx\nnop dword ptr [rax+00h]\nloc_15D8:\nmov rdi, r14; s\ncall _strlen\nlea rdx, [r14+rax-1]\ncmp r14, rdx\njnb short loc_1612\nnop word ptr [rax+rax+00h]\nloc_15F0:\nmovzx ecx, byte ptr [rdx]\ncmp cl, 3Fh ; '?'\nja short loc_160A\nbt r13, rcx\njnb short loc_160A\nmov byte ptr [rdx], 0\nsub rdx, 1\ncmp rdx, r14\njnz short loc_15F0\nloc_160A:\nmov rdi, r14; s\ncall _strlen\nloc_1612:\ncmp rax, 3\nja short loc_1658\nmov rsi, rbp; delim\nxor edi, edi; s\ncall _strtok\nmov r14, rax\ntest rax, rax\njnz short loc_15D8\nloc_162A:\nlea rax, [r12+rbx*8]\nloc_162E:\nmov qword ptr [rax], 0\nmov rdi, [rsp+48h+ptr]; ptr\ncall _free\nadd rsp, 18h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1658:\nmov rdi, r14; s\nlea r15d, [rbx+1]\ncall _strdup\nmov rsi, rbp; delim\nxor edi, edi; s\nmov [r12+rbx*8], rax\nmovsxd rbx, r15d\ncall _strtok\nmov r14, rax\ntest rax, rax\njnz loc_15D8\njmp short loc_162A\nloc_1683:\nmov rax, r12\njmp short loc_162E", + "ida_pseudo": "_QWORD *__fastcall func0(char *s)\n{\n size_t v1; // rax\n _QWORD *v2; // r12\n char *v3; // rax\n unsigned __int64 v4; // r13\n char *v5; // r14\n __int64 v6; // rbx\n size_t v7; // rax\n char *v8; // rdx\n unsigned __int64 v9; // rcx\n _QWORD *v10; // rax\n char *ptr; // [rsp+8h] [rbp-40h]\n\n v1 = strlen(s);\n v2 = malloc(8 * (v1 >> 1) + 8);\n ptr = strdup(s);\n v3 = strtok(ptr, \" \");\n if ( v3 )\n {\n v4 = 0x8C00500200000000LL;\n v5 = v3;\n v6 = 0LL;\n do\n {\n while ( 1 )\n {\n v7 = strlen(v5);\n v8 = &v5[v7 - 1];\n if ( v5 < v8 )\n {\n do\n {\n v9 = (unsigned __int8)*v8;\n if ( (unsigned __int8)v9 > 0x3Fu )\n break;\n if ( !_bittest64((const __int64 *)&v4, v9) )\n break;\n *v8-- = 0;\n }\n while ( v8 != v5 );\n v7 = strlen(v5);\n }\n if ( v7 > 3 )\n break;\n v5 = strtok(0LL, \" \");\n if ( !v5 )\n goto LABEL_10;\n }\n v2[v6] = strdup(v5);\n v6 = (int)v6 + 1;\n v5 = strtok(0LL, \" \");\n }\n while ( v5 );\nLABEL_10:\n v10 = &v2[v6];\n }\n else\n {\n v10 = v2;\n }\n *v10 = 0LL;\n free(ptr);\n return v2;\n}", + "ida_strip_asm": "sub_1570:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\nlea rbp, delim; \" \"\npush rbx\nmov rbx, rdi\nsub rsp, 18h\ncall _strlen\nshr rax, 1\nlea rdi, ds:8[rax*8]; size\ncall _malloc\nmov rdi, rbx; s\nmov r12, rax\ncall _strdup\nmov rsi, rbp; delim\nmov rdi, rax; s\nmov [rsp+48h+ptr], rax\ncall _strtok\ntest rax, rax\njz loc_1683\nmov r13, 8C00500200000000h\nmov r14, rax\nxor ebx, ebx\nnop dword ptr [rax+00h]\nloc_15D8:\nmov rdi, r14; s\ncall _strlen\nlea rdx, [r14+rax-1]\ncmp r14, rdx\njnb short loc_1612\nnop word ptr [rax+rax+00h]\nloc_15F0:\nmovzx ecx, byte ptr [rdx]\ncmp cl, 3Fh ; '?'\nja short loc_160A\nbt r13, rcx\njnb short loc_160A\nmov byte ptr [rdx], 0\nsub rdx, 1\ncmp rdx, r14\njnz short loc_15F0\nloc_160A:\nmov rdi, r14; s\ncall _strlen\nloc_1612:\ncmp rax, 3\nja short loc_1658\nmov rsi, rbp; delim\nxor edi, edi; s\ncall _strtok\nmov r14, rax\ntest rax, rax\njnz short loc_15D8\nloc_162A:\nlea rax, [r12+rbx*8]\nloc_162E:\nmov qword ptr [rax], 0\nmov rdi, [rsp+48h+ptr]; ptr\ncall _free\nadd rsp, 18h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1658:\nmov rdi, r14; s\nlea r15d, [rbx+1]\ncall _strdup\nmov rsi, rbp; delim\nxor edi, edi; s\nmov [r12+rbx*8], rax\nmovsxd rbx, r15d\ncall _strtok\nmov r14, rax\ntest rax, rax\njnz loc_15D8\njmp short loc_162A\nloc_1683:\nmov rax, r12\njmp short loc_162E", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1570(char *s)\n{\n size_t v1; // rax\n _QWORD *v2; // r12\n char *v3; // rax\n unsigned __int64 v4; // r13\n char *v5; // r14\n __int64 v6; // rbx\n size_t v7; // rax\n char *v8; // rdx\n unsigned __int64 v9; // rcx\n _QWORD *v10; // rax\n char *ptr; // [rsp+8h] [rbp-40h]\n\n v1 = strlen(s);\n v2 = malloc(8 * (v1 >> 1) + 8);\n ptr = strdup(s);\n v3 = strtok(ptr, \" \");\n if ( v3 )\n {\n v4 = 0x8C00500200000000LL;\n v5 = v3;\n v6 = 0LL;\n do\n {\n while ( 1 )\n {\n v7 = strlen(v5);\n v8 = &v5[v7 - 1];\n if ( v5 < v8 )\n {\n do\n {\n v9 = (unsigned __int8)*v8;\n if ( (unsigned __int8)v9 > 0x3Fu )\n break;\n if ( !_bittest64((const __int64 *)&v4, v9) )\n break;\n *v8-- = 0;\n }\n while ( v8 != v5 );\n v7 = strlen(v5);\n }\n if ( v7 > 3 )\n break;\n v5 = strtok(0LL, \" \");\n if ( !v5 )\n goto LABEL_10;\n }\n v2[v6] = strdup(v5);\n v6 = (int)v6 + 1;\n v5 = strtok(0LL, \" \");\n }\n while ( v5 );\nLABEL_10:\n v10 = &v2[v6];\n }\n else\n {\n v10 = v2;\n }\n *v10 = 0LL;\n free(ptr);\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1570(char *s) {\n unsigned int v1;\n uint64_t *v2;\n char *v3;\n unsigned long long v4;\n char *v5;\n long long v6;\n unsigned int v7;\n char *v8;\n unsigned long long v9;\n uint64_t *v10;\n char *ptr;\n v1 = strlen(s);\n v2 = malloc(8 * (v1 >> 1) + 8);\n ptr = strdup(s);\n v3 = strtok(ptr, \" \");\n if (v3) {\n v4 = 10088151134830067712LL;\n v5 = v3;\n v6 = 0LL;\n do {\n while (1) {\n v7 = strlen(v5);\n v8 = &v5[v7 - 1];\n if (v5 < v8) {\n do {\n v9 = (unsigned char)*v8;\n if ((unsigned char)v9 > 63u) break;\n if (!_bittest64((const long long *)&v4, v9)) break;\n *v8-- = 0;\n } while (v8 != v5);\n v7 = strlen(v5);\n }\n if (v7 > 3) break;\n v5 = strtok(0LL, \" \");\n if (!v5) goto LABEL_10;\n }\n v2[v6] = strdup(v5);\n v6 = (int)v6 + 1;\n v5 = strtok(0LL, \" \");\n } while (v5);\n LABEL_10:\n v10 = &v2[v6];\n } else {\n v10 = v2;\n }\n *v10 = 0LL;\n free(ptr);\n return v2;\n}", + "ida_pseudo_norm": "uint64_t *func0(char *s) {\n unsigned int v1;\n uint64_t *v2;\n char *v3;\n unsigned long long v4;\n char *v5;\n long long v6;\n unsigned int v7;\n char *v8;\n unsigned long long v9;\n uint64_t *v10;\n char *ptr;\n v1 = strlen(s);\n v2 = malloc(8 * (v1 >> 1) + 8);\n ptr = strdup(s);\n v3 = strtok(ptr, \" \");\n if (v3) {\n v4 = 10088151134830067712LL;\n v5 = v3;\n v6 = 0LL;\n do {\n while (1) {\n v7 = strlen(v5);\n v8 = &v5[v7 - 1];\n if (v5 < v8) {\n do {\n v9 = (unsigned char)*v8;\n if ((unsigned char)v9 > 63u) break;\n if (!_bittest64((const long long *)&v4, v9)) break;\n *v8-- = 0;\n } while (v8 != v5);\n v7 = strlen(v5);\n }\n if (v7 > 3) break;\n v5 = strtok(0LL, \" \");\n if (!v5) goto LABEL_10;\n }\n v2[v6] = strdup(v5);\n v6 = (int)v6 + 1;\n v5 = strtok(0LL, \" \");\n } while (v5);\n LABEL_10:\n v10 = &v2[v6];\n } else {\n v10 = v2;\n }\n *v10 = 0LL;\n free(ptr);\n return v2;\n}" + }, + { + "index": 8, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int nums[], int result[], int size) {\n for (int i = 0; i < size; i++) {\n result[i] = nums[i] * nums[i];\n }\n}", + "test": "int main() {\n\n int nums1[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n int size1 = sizeof(nums1) / sizeof(nums1[0]);\n\n int result1[10];\n\n func0(nums1, result1, size1);\n\n int expected1[] = {1, 4, 9, 16, 25, 36, 49, 64, 81, 100};\n\n for(int i = 0; i < size1; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n\n\n int nums2[] = {10, 20, 30};\n\n int size2 = sizeof(nums2) / sizeof(nums2[0]);\n\n int result2[3];\n\n func0(nums2, result2, size2);\n\n int expected2[] = {100, 400, 900};\n\n for(int i = 0; i < size2; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n\n\n int nums3[] = {12, 15};\n\n int size3 = sizeof(nums3) / sizeof(nums3[0]);\n\n int result3[2];\n\n func0(nums3, result3, size3);\n\n int expected3[] = {144, 225};\n\n for(int i = 0; i < size3; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %edx,-0x24(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11ef \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%ecx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov -0x4(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rsi\nmov -0x20(%rbp),%rdx\nadd %rsi,%rdx\nimul %ecx,%eax\nmov %eax,(%rdx)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x24(%rbp),%eax\njl 11a5 \npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_4], 0\njmp short loc_11EF\nloc_11A5:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nmov ecx, [rbp+var_4]\nmovsxd rcx, ecx\nlea rsi, ds:0[rcx*4]\nmov rcx, [rbp+var_20]\nadd rcx, rsi\nimul eax, edx\nmov [rcx], eax\nadd [rbp+var_4], 1\nloc_11EF:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_24]\njl short loc_11A5\nnop\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+20h] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a3 )\n break;\n *(_DWORD *)(4LL * (int)i + a2) = *(_DWORD *)(4LL * (int)i + a1) * *(_DWORD *)(4LL * (int)i + a1);\n }\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_4], 0\njmp short loc_11EF\nloc_11A5:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nmov ecx, [rbp+var_4]\nmovsxd rcx, ecx\nlea rsi, ds:0[rcx*4]\nmov rcx, [rbp+var_20]\nadd rcx, rsi\nimul eax, edx\nmov [rcx], eax\nadd [rbp+var_4], 1\nloc_11EF:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_24]\njl short loc_11A5\nnop\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, __int64 a2, int a3)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+20h] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a3 )\n break;\n *(_DWORD *)(4LL * (int)i + a2) = *(_DWORD *)(4LL * (int)i + a1) * *(_DWORD *)(4LL * (int)i + a1);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, long long a2, int a3) {\n long long result;\n unsigned int i;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a3) break;\n *(uint32_t *)(4LL * (int)i + a2) =\n *(uint32_t *)(4LL * (int)i + a1) * *(uint32_t *)(4LL * (int)i + a1);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3) {\n long long result;\n unsigned int i;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a3) break;\n *(uint32_t *)(4LL * (int)i + a2) =\n *(uint32_t *)(4LL * (int)i + a1) * *(uint32_t *)(4LL * (int)i + a1);\n }\n return result;\n}" + }, + { + "index": 8, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int nums[], int result[], int size) {\n for (int i = 0; i < size; i++) {\n result[i] = nums[i] * nums[i];\n }\n}", + "test": "int main() {\n\n int nums1[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n int size1 = sizeof(nums1) / sizeof(nums1[0]);\n\n int result1[10];\n\n func0(nums1, result1, size1);\n\n int expected1[] = {1, 4, 9, 16, 25, 36, 49, 64, 81, 100};\n\n for(int i = 0; i < size1; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n\n\n int nums2[] = {10, 20, 30};\n\n int size2 = sizeof(nums2) / sizeof(nums2[0]);\n\n int result2[3];\n\n func0(nums2, result2, size2);\n\n int expected2[] = {100, 400, 900};\n\n for(int i = 0; i < size2; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n\n\n int nums3[] = {12, 15};\n\n int size3 = sizeof(nums3) / sizeof(nums3[0]);\n\n int result3[2];\n\n func0(nums3, result3, size3);\n\n int expected3[] = {144, 225};\n\n for(int i = 0; i < size3; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edx,%edx\njle 11ae \nlea -0x1(%rdx),%ecx\nmov $0x0,%eax\nmov (%rdi,%rax,4),%edx\nimul %edx,%edx\nmov %edx,(%rsi,%rax,4)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rcx,%rdx\njne 1199 \nretq\n", + "ida_asm": "func0:\nendbr64\ntest edx, edx\njle short locret_11B3\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov eax, 0\nloc_11A1:\nmov edx, [rdi+rax]\nimul edx, edx\nmov [rsi+rax], edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_11A1\nlocret_11B3:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n __int64 v3; // rax\n\n if ( a3 > 0 )\n {\n v3 = 0LL;\n do\n {\n *(_DWORD *)(a2 + v3) = *(_DWORD *)(a1 + v3) * *(_DWORD *)(a1 + v3);\n v3 += 4LL;\n }\n while ( v3 != 4LL * a3 );\n }\n}", + "ida_strip_asm": "sub_1189:\nendbr64\ntest edx, edx\njle short locret_11B3\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov eax, 0\nloc_11A1:\nmov edx, [rdi+rax]\nimul edx, edx\nmov [rsi+rax], edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_11A1\nlocret_11B3:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1189(__int64 a1, __int64 a2, int a3)\n{\n __int64 v3; // rax\n\n if ( a3 > 0 )\n {\n v3 = 0LL;\n do\n {\n *(_DWORD *)(a2 + v3) = *(_DWORD *)(a1 + v3) * *(_DWORD *)(a1 + v3);\n v3 += 4LL;\n }\n while ( v3 != 4LL * a3 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1189(long long a1, long long a2, int a3) {\n long long v3;\n if (a3 > 0) {\n v3 = 0LL;\n do {\n *(uint32_t *)(a2 + v3) = *(uint32_t *)(a1 + v3) * *(uint32_t *)(a1 + v3);\n v3 += 4LL;\n } while (v3 != 4LL * a3);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, long long a2, int a3) {\n long long v3;\n if (a3 > 0) {\n v3 = 0LL;\n do {\n *(uint32_t *)(a2 + v3) = *(uint32_t *)(a1 + v3) * *(uint32_t *)(a1 + v3);\n v3 += 4LL;\n } while (v3 != 4LL * a3);\n }\n}" + }, + { + "index": 9, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char* str) {\n int n = strlen(str);\n char tmp[2 * n + 1];\n strcpy(tmp, str);\n strcat(tmp, str);\n for (int i = 1; i <= n; i++) {\n int equal = 1;\n for (int j = 0; j < n; j++) {\n if (str[j] != tmp[i + j]) {\n equal = 0;\n break;\n }\n }\n if (equal) {\n return i;\n }\n }\n return n;\n}", + "test": "int main() {\n\n assert(func0(\"aaaa\") == 1);\n\n assert(func0(\"ab\") == 2);\n\n assert(func0(\"abc\") == 3);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0x48,%rsp\nmov %rdi,-0x68(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nmov %rsp,%rax\nmov %rax,%rbx\nmov -0x68(%rbp),%rax\nmov %rax,%rdi\ncallq 10a0 \nmov %eax,-0x4c(%rbp)\nmov -0x4c(%rbp),%eax\nadd %eax,%eax\nadd $0x1,%eax\nmovslq %eax,%rdx\nsub $0x1,%rdx\nmov %rdx,-0x48(%rbp)\nmovslq %eax,%rdx\nmov %rdx,%r14\nmov $0x0,%r15d\nmovslq %eax,%rdx\nmov %rdx,%r12\nmov $0x0,%r13d\ncltq\nmov $0x10,%edx\nsub $0x1,%rdx\nadd %rdx,%rax\nmov $0x10,%esi\nmov $0x0,%edx\ndiv %rsi\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rcx\nsub %rdx,%rcx\nmov %rcx,%rdx\ncmp %rdx,%rsp\nje 127a \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 1263 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 12a4 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x0,%rax\nmov %rax,-0x40(%rbp)\nmov -0x68(%rbp),%rdx\nmov -0x40(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1090 \nmov -0x68(%rbp),%rdx\nmov -0x40(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10d0 \nmovl $0x1,-0x50(%rbp)\njmp 1338 \nmovl $0x1,-0x54(%rbp)\nmovl $0x0,-0x58(%rbp)\njmp 1321 \nmov -0x58(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x68(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%ecx\nmov -0x50(%rbp),%edx\nmov -0x58(%rbp),%eax\nadd %edx,%eax\nmov -0x40(%rbp),%rdx\ncltq\nmovzbl (%rdx,%rax,1),%eax\ncmp %al,%cl\nje 131d \nmovl $0x0,-0x54(%rbp)\njmp 1329 \naddl $0x1,-0x58(%rbp)\nmov -0x58(%rbp),%eax\ncmp -0x4c(%rbp),%eax\njl 12ee \ncmpl $0x0,-0x54(%rbp)\nje 1334 \nmov -0x50(%rbp),%eax\njmp 1343 \naddl $0x1,-0x50(%rbp)\nmov -0x50(%rbp),%eax\ncmp -0x4c(%rbp),%eax\njle 12de \nmov -0x4c(%rbp),%eax\nmov %rbx,%rsp\nmov -0x38(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 135a \ncallq 10b0 <__stack_chk_fail@plt>\nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 48h\nmov [rbp+s], rdi\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov rax, rsp\nmov rbx, rax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_2C], eax\nmov eax, [rbp+var_2C]\nadd eax, eax\nadd eax, 1\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_28], rdx\ncdqe\nmov edx, 10h\nsub rdx, 1\nadd rax, rdx\nmov esi, 10h\nmov edx, 0\ndiv rsi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_1240:\ncmp rsp, rdx\njz short loc_1257\nsub rsp, 1000h\nor [rsp+1050h+var_58], 0\njmp short loc_1240\nloc_1257:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1281\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1281:\nmov rax, rsp\nadd rax, 0\nmov [rbp+dest], rax\nmov rdx, [rbp+s]\nmov rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\nmov rdx, [rbp+s]\nmov rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\nmov [rbp+var_38], 1\njmp short loc_1315\nloc_12BB:\nmov [rbp+var_34], 1\nmov [rbp+var_30], 0\njmp short loc_12FE\nloc_12CB:\nmov eax, [rbp+var_30]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx ecx, byte ptr [rax]\nmov edx, [rbp+var_38]\nmov eax, [rbp+var_30]\nadd eax, edx\nmov rdx, [rbp+dest]\ncdqe\nmovzx eax, byte ptr [rdx+rax]\ncmp cl, al\njz short loc_12FA\nmov [rbp+var_34], 0\njmp short loc_1306\nloc_12FA:\nadd [rbp+var_30], 1\nloc_12FE:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_2C]\njl short loc_12CB\nloc_1306:\ncmp [rbp+var_34], 0\njz short loc_1311\nmov eax, [rbp+var_38]\njmp short loc_1320\nloc_1311:\nadd [rbp+var_38], 1\nloc_1315:\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_2C]\njle short loc_12BB\nmov eax, [rbp+var_2C]\nloc_1320:\nmov rsp, rbx\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njz short loc_1337\ncall ___stack_chk_fail\nloc_1337:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(char *a1)\n{\n int v1; // eax\n unsigned __int64 v2; // rax\n void *v3; // rsp\n char v5[8]; // [rsp+8h] [rbp-50h] BYREF\n char *s; // [rsp+10h] [rbp-48h]\n int i; // [rsp+20h] [rbp-38h]\n int v8; // [rsp+24h] [rbp-34h]\n int j; // [rsp+28h] [rbp-30h]\n int v10; // [rsp+2Ch] [rbp-2Ch]\n __int64 v11; // [rsp+30h] [rbp-28h]\n char *dest; // [rsp+38h] [rbp-20h]\n unsigned __int64 v13; // [rsp+40h] [rbp-18h]\n\n s = a1;\n v13 = __readfsqword(0x28u);\n v10 = strlen(a1);\n v1 = 2 * v10 + 1;\n v11 = v1 - 1LL;\n v2 = 16 * ((v1 + 15LL) / 0x10uLL);\n while ( v5 != &v5[-(v2 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = alloca(v2 & 0xFFF);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)&v5[(v2 & 0xFFF) - 8] = *(_QWORD *)&v5[(v2 & 0xFFF) - 8];\n dest = v5;\n strcpy(v5, s);\n strcat(dest, s);\n for ( i = 1; i <= v10; ++i )\n {\n v8 = 1;\n for ( j = 0; j < v10; ++j )\n {\n if ( s[j] != dest[i + j] )\n {\n v8 = 0;\n break;\n }\n }\n if ( v8 )\n return (unsigned int)i;\n }\n return (unsigned int)v10;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 48h\nmov [rbp+s], rdi\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov rax, rsp\nmov rbx, rax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_2C], eax\nmov eax, [rbp+var_2C]\nadd eax, eax\nadd eax, 1\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_28], rdx\ncdqe\nmov edx, 10h\nsub rdx, 1\nadd rax, rdx\nmov esi, 10h\nmov edx, 0\ndiv rsi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_1240:\ncmp rsp, rdx\njz short loc_1257\nsub rsp, 1000h\nor [rsp+1050h+var_58], 0\njmp short loc_1240\nloc_1257:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1281\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1281:\nmov rax, rsp\nadd rax, 0\nmov [rbp+dest], rax\nmov rdx, [rbp+s]\nmov rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\nmov rdx, [rbp+s]\nmov rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\nmov [rbp+var_38], 1\njmp short loc_1315\nloc_12BB:\nmov [rbp+var_34], 1\nmov [rbp+var_30], 0\njmp short loc_12FE\nloc_12CB:\nmov eax, [rbp+var_30]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx ecx, byte ptr [rax]\nmov edx, [rbp+var_38]\nmov eax, [rbp+var_30]\nadd eax, edx\nmov rdx, [rbp+dest]\ncdqe\nmovzx eax, byte ptr [rdx+rax]\ncmp cl, al\njz short loc_12FA\nmov [rbp+var_34], 0\njmp short loc_1306\nloc_12FA:\nadd [rbp+var_30], 1\nloc_12FE:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_2C]\njl short loc_12CB\nloc_1306:\ncmp [rbp+var_34], 0\njz short loc_1311\nmov eax, [rbp+var_38]\njmp short loc_1320\nloc_1311:\nadd [rbp+var_38], 1\nloc_1315:\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_2C]\njle short loc_12BB\nmov eax, [rbp+var_2C]\nloc_1320:\nmov rsp, rbx\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njz short loc_1337\ncall ___stack_chk_fail\nloc_1337:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11C9(char *a1)\n{\n int v1; // eax\n unsigned __int64 v2; // rax\n void *v3; // rsp\n char v5[8]; // [rsp+8h] [rbp-50h] BYREF\n char *s; // [rsp+10h] [rbp-48h]\n int i; // [rsp+20h] [rbp-38h]\n int v8; // [rsp+24h] [rbp-34h]\n int j; // [rsp+28h] [rbp-30h]\n int v10; // [rsp+2Ch] [rbp-2Ch]\n __int64 v11; // [rsp+30h] [rbp-28h]\n char *dest; // [rsp+38h] [rbp-20h]\n unsigned __int64 v13; // [rsp+40h] [rbp-18h]\n\n s = a1;\n v13 = __readfsqword(0x28u);\n v10 = strlen(a1);\n v1 = 2 * v10 + 1;\n v11 = v1 - 1LL;\n v2 = 16 * ((v1 + 15LL) / 0x10uLL);\n while ( v5 != &v5[-(v2 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = alloca(v2 & 0xFFF);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)&v5[(v2 & 0xFFF) - 8] = *(_QWORD *)&v5[(v2 & 0xFFF) - 8];\n dest = v5;\n strcpy(v5, s);\n strcat(dest, s);\n for ( i = 1; i <= v10; ++i )\n {\n v8 = 1;\n for ( j = 0; j < v10; ++j )\n {\n if ( s[j] != dest[i + j] )\n {\n v8 = 0;\n break;\n }\n }\n if ( v8 )\n return (unsigned int)i;\n }\n return (unsigned int)v10;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11C9(char *a1) {\n int v1;\n unsigned long long v2;\n void *v3;\n char v5[8];\n char *s;\n int i;\n int v8;\n int j;\n int v10;\n long long v11;\n char *dest;\n unsigned long long v13;\n s = a1;\n v13 = __readfsqword(40u);\n v10 = strlen(a1);\n v1 = 2 * v10 + 1;\n v11 = v1 - 1LL;\n v2 = 16 * ((v1 + 15LL) / 16uLL);\n while (v5 != &v5[-(v2 & 18446744073709547520LL)])\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)&v5[(v2 & 4095) - 8] = *(uint64_t *)&v5[(v2 & 4095) - 8];\n dest = v5;\n strcpy(v5, s);\n strcat(dest, s);\n for (i = 1; i <= v10; ++i) {\n v8 = 1;\n for (j = 0; j < v10; ++j) {\n if (s[j] != dest[i + j]) {\n v8 = 0;\n break;\n }\n }\n if (v8) return (unsigned int)i;\n }\n return (unsigned int)v10;\n}", + "ida_pseudo_norm": "long long func0(char *a1) {\n int v1;\n unsigned long long v2;\n void *v3;\n char v5[8];\n char *s;\n int i;\n int v8;\n int j;\n int v10;\n long long v11;\n char *dest;\n unsigned long long v13;\n s = a1;\n v13 = __readfsqword(40u);\n v10 = strlen(a1);\n v1 = 2 * v10 + 1;\n v11 = v1 - 1LL;\n v2 = 16 * ((v1 + 15LL) / 16uLL);\n while (v5 != &v5[-(v2 & 18446744073709547520LL)])\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)&v5[(v2 & 4095) - 8] = *(uint64_t *)&v5[(v2 & 4095) - 8];\n dest = v5;\n strcpy(v5, s);\n strcat(dest, s);\n for (i = 1; i <= v10; ++i) {\n v8 = 1;\n for (j = 0; j < v10; ++j) {\n if (s[j] != dest[i + j]) {\n v8 = 0;\n break;\n }\n }\n if (v8) return (unsigned int)i;\n }\n return (unsigned int)v10;\n}" + }, + { + "index": 9, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char* str) {\n int n = strlen(str);\n char tmp[2 * n + 1];\n strcpy(tmp, str);\n strcat(tmp, str);\n for (int i = 1; i <= n; i++) {\n int equal = 1;\n for (int j = 0; j < n; j++) {\n if (str[j] != tmp[i + j]) {\n equal = 0;\n break;\n }\n }\n if (equal) {\n return i;\n }\n }\n return n;\n}", + "test": "int main() {\n\n assert(func0(\"aaaa\") == 1);\n\n assert(func0(\"ab\") == 2);\n\n assert(func0(\"abc\") == 3);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0x10,%rsp\nmov %rdi,%rbx\nmov %fs:0x28,%rax\nmov %rax,-0x28(%rbp)\nxor %eax,%eax\nmov $0xffffffffffffffff,%rcx\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%r12\nmov %r12d,%r13d\nlea 0x1(%r12,%r12,1),%eax\ncltq\nadd $0xf,%rax\nmov %rax,%rdx\nand $0xfffffffffffffff0,%rdx\nand $0xfffffffffffff000,%rax\nmov %rsp,%rdi\nsub %rax,%rdi\nmov %rdi,%rax\ncmp %rax,%rsp\nje 121c \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 1205 \nmov %rdx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 1232 \norq $0x0,-0x8(%rsp,%rax,1)\nmov %rsp,%r14\nmov %rbx,%rsi\nmov %rsp,%rdi\ncallq 1080 \nmov %rbx,%rsi\nmov %rsp,%rdi\ncallq 10b0 \nlea 0x1(%r14),%rcx\nmov $0x1,%edi\nlea -0x1(%r12),%esi\nmov $0x0,%r8d\ntest %r12d,%r12d\njg 12a8 \nmov %r12d,%edi\njmp 127e \nmov %rdx,%rax\nmovzbl (%rcx,%rax,1),%edx\ncmp %dl,(%rbx,%rax,1)\njne 129c \nlea 0x1(%rax),%rdx\ncmp %rsi,%rax\njne 1269 \nmov -0x28(%rbp),%rax\nxor %fs:0x28,%rax\njne 12b2 \nmov %edi,%eax\nlea -0x20(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %rbp\nretq\nadd $0x1,%edi\nadd $0x1,%rcx\ncmp %edi,%r13d\njl 12ad \nmov %r8,%rax\njmp 126c \nmov %r12d,%edi\njmp 127e \ncallq 1090 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 18h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\ncall _strlen\nmov r13, rax\nmov r12d, eax\nlea r15d, [rax+rax+1]\nmovsxd r15, r15d\nlea rax, [r15+0Fh]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_121A:\ncmp rsp, rdx\njz short loc_1231\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_121A\nloc_1231:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_1247\nor [rsp+rax+40h+var_48], 0\nloc_1247:\nmov r14, rsp\nmov rdx, r15\nmov rsi, rbx\nmov rdi, rsp\ncall ___strcpy_chk\nmov rdx, r15\nmov rsi, rbx\nmov rdi, rsp\ncall ___strcat_chk\ntest r13d, r13d\njle short loc_12C6\nlea rcx, [r14+1]\nmov edi, 1\nlea esi, [r13-1]\nmov r8d, 0\njmp short loc_12C1\nloc_1280:\nmov rax, rdx\nloc_1283:\nmovzx edx, byte ptr [rcx+rax]\ncmp [rbx+rax], dl\njnz short loc_12B5\nlea rdx, [rax+1]\ncmp rax, rsi\njnz short loc_1280\nloc_1295:\nmov rax, [rbp+var_38]\nsub rax, fs:28h\njnz short loc_12D0\nmov eax, edi\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_12B5:\nadd edi, 1\nadd rcx, 1\ncmp r12d, edi\njl short loc_12CB\nloc_12C1:\nmov rax, r8\njmp short loc_1283\nloc_12C6:\nmov edi, r13d\njmp short loc_1295\nloc_12CB:\nmov edi, r13d\njmp short loc_1295\nloc_12D0:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v2; // r13d\n __int64 v3; // r15\n signed __int64 v4; // rax\n void *v5; // rsp\n _BYTE *v6; // rcx\n int i; // edi\n __int64 j; // rax\n __int64 v10; // [rsp+0h] [rbp-48h]\n char v11; // [rsp+8h] [rbp-40h] BYREF\n _BYTE v12[63]; // [rsp+9h] [rbp-3Fh] BYREF\n\n *(_QWORD *)&v12[7] = __readfsqword(0x28u);\n v2 = strlen(a1);\n v3 = 2 * v2 + 1;\n while ( &v11 != &v12[-((v3 + 15) & 0xFFFFFFFFFFFFF000LL) - 1] )\n ;\n v4 = (2 * (_WORD)v2 + 16) & 0xFF0;\n v5 = alloca(v4);\n if ( ((2 * (_WORD)v2 + 16) & 0xFF0) != 0 )\n *(__int64 *)((char *)&v10 + v4) = *(__int64 *)((char *)&v10 + v4);\n __strcpy_chk(&v11, a1, v3);\n __strcat_chk(&v11, a1, v3);\n if ( v2 <= 0 )\n {\n return (unsigned int)v2;\n }\n else\n {\n v6 = v12;\n for ( i = 1; i <= v2; ++i )\n {\n for ( j = 0LL; a1[j] == v6[j]; ++j )\n {\n if ( j == v2 - 1 )\n return (unsigned int)i;\n }\n ++v6;\n }\n return (unsigned int)v2;\n }\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 18h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\ncall _strlen\nmov r13, rax\nmov r12d, eax\nlea r15d, [rax+rax+1]\nmovsxd r15, r15d\nlea rax, [r15+0Fh]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_121A:\ncmp rsp, rdx\njz short loc_1231\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_121A\nloc_1231:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_1247\nor [rsp+rax+40h+var_48], 0\nloc_1247:\nmov r14, rsp\nmov rdx, r15\nmov rsi, rbx\nmov rdi, rsp\ncall ___strcpy_chk\nmov rdx, r15\nmov rsi, rbx\nmov rdi, rsp\ncall ___strcat_chk\ntest r13d, r13d\njle short loc_12C6\nlea rcx, [r14+1]\nmov edi, 1\nlea esi, [r13-1]\nmov r8d, 0\njmp short loc_12C1\nloc_1280:\nmov rax, rdx\nloc_1283:\nmovzx edx, byte ptr [rcx+rax]\ncmp [rbx+rax], dl\njnz short loc_12B5\nlea rdx, [rax+1]\ncmp rax, rsi\njnz short loc_1280\nloc_1295:\nmov rax, [rbp+var_38]\nsub rax, fs:28h\njnz short loc_12D0\nmov eax, edi\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_12B5:\nadd edi, 1\nadd rcx, 1\ncmp r12d, edi\njl short loc_12CB\nloc_12C1:\nmov rax, r8\njmp short loc_1283\nloc_12C6:\nmov edi, r13d\njmp short loc_1295\nloc_12CB:\nmov edi, r13d\njmp short loc_1295\nloc_12D0:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_11C9(const char *a1)\n{\n int v2; // r13d\n __int64 v3; // r15\n signed __int64 v4; // rax\n void *v5; // rsp\n _BYTE *v6; // rcx\n int i; // edi\n __int64 j; // rax\n __int64 v10; // [rsp+0h] [rbp-48h]\n char v11; // [rsp+8h] [rbp-40h] BYREF\n _BYTE v12[63]; // [rsp+9h] [rbp-3Fh] BYREF\n\n *(_QWORD *)&v12[7] = __readfsqword(0x28u);\n v2 = strlen(a1);\n v3 = 2 * v2 + 1;\n while ( &v11 != &v12[-((v3 + 15) & 0xFFFFFFFFFFFFF000LL) - 1] )\n ;\n v4 = (2 * (_WORD)v2 + 16) & 0xFF0;\n v5 = alloca(v4);\n if ( ((2 * (_WORD)v2 + 16) & 0xFF0) != 0 )\n *(__int64 *)((char *)&v10 + v4) = *(__int64 *)((char *)&v10 + v4);\n __strcpy_chk(&v11, a1, v3);\n __strcat_chk(&v11, a1, v3);\n if ( v2 <= 0 )\n {\n return (unsigned int)v2;\n }\n else\n {\n v6 = v12;\n for ( i = 1; i <= v2; ++i )\n {\n for ( j = 0LL; a1[j] == v6[j]; ++j )\n {\n if ( j == v2 - 1 )\n return (unsigned int)i;\n }\n ++v6;\n }\n return (unsigned int)v2;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11C9(const char *a1) {\n int v2;\n long long v3;\n signed long long v4;\n void *v5;\n uint8_t *v6;\n int i;\n long long j;\n long long v10;\n char v11;\n uint8_t v12[63];\n *(uint64_t *)&v12[7] = __readfsqword(40u);\n v2 = strlen(a1);\n v3 = 2 * v2 + 1;\n while (&v11 != &v12[-((v3 + 15) & 18446744073709547520LL) - 1])\n ;\n v4 = (2 * (unsigned short)v2 + 16) & 4080;\n v5 = alloca(v4);\n if (((2 * (unsigned short)v2 + 16) & 4080) != 0)\n *(long long *)((char *)&v10 + v4) = *(long long *)((char *)&v10 + v4);\n __strcpy_chk(&v11, a1, v3);\n __strcat_chk(&v11, a1, v3);\n if (v2 <= 0) {\n return (unsigned int)v2;\n } else {\n v6 = v12;\n for (i = 1; i <= v2; ++i) {\n for (j = 0LL; a1[j] == v6[j]; ++j) {\n if (j == v2 - 1) return (unsigned int)i;\n }\n ++v6;\n }\n return (unsigned int)v2;\n }\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v2;\n long long v3;\n signed long long v4;\n void *v5;\n uint8_t *v6;\n int i;\n long long j;\n long long v10;\n char v11;\n uint8_t v12[63];\n *(uint64_t *)&v12[7] = __readfsqword(40u);\n v2 = strlen(a1);\n v3 = 2 * v2 + 1;\n while (&v11 != &v12[-((v3 + 15) & 18446744073709547520LL) - 1])\n ;\n v4 = (2 * (unsigned short)v2 + 16) & 4080;\n v5 = alloca(v4);\n if (((2 * (unsigned short)v2 + 16) & 4080) != 0)\n *(long long *)((char *)&v10 + v4) = *(long long *)((char *)&v10 + v4);\n __strcpy_chk(&v11, a1, v3);\n __strcat_chk(&v11, a1, v3);\n if (v2 <= 0) {\n return (unsigned int)v2;\n } else {\n v6 = v12;\n for (i = 1; i <= v2; ++i) {\n for (j = 0LL; a1[j] == v6[j]; ++j) {\n if (j == v2 - 1) return (unsigned int)i;\n }\n ++v6;\n }\n return (unsigned int)v2;\n }\n}" + }, + { + "index": 9, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char* str) {\n int n = strlen(str);\n char tmp[2 * n + 1];\n strcpy(tmp, str);\n strcat(tmp, str);\n for (int i = 1; i <= n; i++) {\n int equal = 1;\n for (int j = 0; j < n; j++) {\n if (str[j] != tmp[i + j]) {\n equal = 0;\n break;\n }\n }\n if (equal) {\n return i;\n }\n }\n return n;\n}", + "test": "int main() {\n\n assert(func0(\"aaaa\") == 1);\n\n assert(func0(\"ab\") == 2);\n\n assert(func0(\"abc\") == 3);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r13\npush %r12\npush %rbx\nmov %rdi,%rbx\nsub $0x18,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x28(%rbp)\nxor %eax,%eax\ncallq 1080 \nmov %rsp,%rsi\nmov %rax,%r13\nmov %eax,%r12d\nlea 0x1(%rax,%rax,1),%eax\ncltq\nadd $0xf,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rsi\nand $0xfffffffffffffff0,%rdx\nmov %rsi,%rax\ncmp %rax,%rsp\nje 12b8 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 12a3 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 134d \nmov %r13,%rdx\nmov %rbx,%rsi\nmov %rsp,%rdi\ncallq 10b0 \nmov %rbx,%rsi\nlea (%rsp,%r13,1),%rdi\nlea 0x1(%r13),%rdx\ncallq 10b0 \nlea 0x1(%rsp),%rcx\nmov $0x1,%r8d\nlea -0x1(%r13),%esi\ntest %r13d,%r13d\njle 132b \nnopl 0x0(%rax)\nxor %eax,%eax\njmp 1314 \nnopl 0x0(%rax)\nlea 0x1(%rax),%rdx\ncmp %rsi,%rax\nje 1330 \nmov %rdx,%rax\nmovzbl (%rcx,%rax,1),%edi\ncmp %dil,(%rbx,%rax,1)\nje 1308 \nadd $0x1,%r8d\nadd $0x1,%rcx\ncmp %r8d,%r12d\njge 1300 \nmov %r13d,%r8d\nxchg %ax,%ax\nmov -0x28(%rbp),%rax\nxor %fs:0x28,%rax\njne 1358 \nlea -0x18(%rbp),%rsp\nmov %r8d,%eax\npop %rbx\npop %r12\npop %r13\npop %rbp\nretq\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 12ca \ncallq 1090 <__stack_chk_fail@plt>\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r14\npush r13\npush r12\npush rbx\nmov rbx, rdi\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\ncall _strlen\nmov rcx, rsp\nlea r14d, [rax+rax+1]\nmov r13, rax\nmov r12d, eax\nmovsxd r14, r14d\nlea rax, [r14+0Fh]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_12B9\nloc_12A4:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rcx\njnz short loc_12A4\nloc_12B9:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1356\nloc_12CB:\nmov rcx, r14\nmov rdx, r13\nmov rsi, rbx\nmov rdi, rsp\ncall ___memcpy_chk\nmov rcx, r14\nlea rdx, [r13+1]\nlea rdi, [rsp+r13+1030h+var_1030]\nsub rcx, r13\nmov rsi, rbx\ncall ___memcpy_chk\ntest r13d, r13d\njle short loc_1331\nlea rcx, [rsp+1030h+var_102F]\nmov edi, 1\nlea esi, [r13-1]\nnop dword ptr [rax]\nloc_1308:\nxor eax, eax\njmp short loc_131C\nloc_1310:\nlea rdx, [rax+1]\ncmp rax, rsi\njz short loc_1338\nmov rax, rdx\nloc_131C:\nmovzx edx, byte ptr [rcx+rax]\ncmp [rbx+rax], dl\njz short loc_1310\nadd edi, 1\nadd rcx, 1\ncmp r12d, edi\njge short loc_1308\nloc_1331:\nmov edi, r13d\nnop dword ptr [rax+00h]\nloc_1338:\nmov rax, [rbp+var_28]\nsub rax, fs:28h\njnz short loc_1361\nlea rsp, [rbp-20h]\nmov eax, edi\npop rbx\npop r12\npop r13\npop r14\npop rbp\nretn\nloc_1356:\nor [rsp+rdx+1030h+var_1038], 0\njmp loc_12CB\nloc_1361:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n size_t v2; // r13\n __int64 v3; // r14\n char *v4; // rcx\n signed __int64 v5; // rdx\n void *v6; // rsp\n char *v7; // rcx\n int v8; // edi\n __int64 i; // rax\n __int64 v11; // [rsp+0h] [rbp-1038h]\n char v12; // [rsp+8h] [rbp-1030h] BYREF\n char v13; // [rsp+9h] [rbp-102Fh] BYREF\n _QWORD v14[6]; // [rsp+1008h] [rbp-30h] BYREF\n\n v14[1] = __readfsqword(0x28u);\n v2 = strlen(a1);\n v3 = 2 * (int)v2 + 1;\n v4 = (char *)v14 - ((v3 + 15) & 0xFFFFFFFFFFFFF000LL);\n if ( v14 != (_QWORD *)v4 )\n {\n while ( &v12 != v4 )\n ;\n }\n v5 = (2 * (_WORD)v2 + 16) & 0xFF0;\n v6 = alloca(v5);\n if ( ((2 * (_WORD)v2 + 16) & 0xFF0) != 0 )\n *(__int64 *)((char *)&v11 + v5) = *(__int64 *)((char *)&v11 + v5);\n __memcpy_chk(&v12, a1, v2, v3);\n __memcpy_chk(&v12 + v2, a1, v2 + 1, v3 - v2);\n if ( (int)v2 > 0 )\n {\n v7 = &v13;\n v8 = 1;\n do\n {\n for ( i = 0LL; a1[i] == v7[i]; ++i )\n {\n if ( i == (_DWORD)v2 - 1 )\n return (unsigned int)v8;\n }\n ++v8;\n ++v7;\n }\n while ( (int)v2 >= v8 );\n }\n return (unsigned int)v2;\n}", + "ida_strip_asm": "sub_1250:\nendbr64\npush rbp\nmov rbp, rsp\npush r14\npush r13\npush r12\npush rbx\nmov rbx, rdi\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\ncall _strlen\nmov rcx, rsp\nlea r14d, [rax+rax+1]\nmov r13, rax\nmov r12d, eax\nmovsxd r14, r14d\nlea rax, [r14+0Fh]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_12B9\nloc_12A4:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rcx\njnz short loc_12A4\nloc_12B9:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1356\nloc_12CB:\nmov rcx, r14\nmov rdx, r13\nmov rsi, rbx\nmov rdi, rsp\ncall ___memcpy_chk\nmov rcx, r14\nlea rdx, [r13+1]\nlea rdi, [rsp+r13+1030h+var_1030]\nsub rcx, r13\nmov rsi, rbx\ncall ___memcpy_chk\ntest r13d, r13d\njle short loc_1331\nlea rcx, [rsp+1030h+var_102F]\nmov edi, 1\nlea esi, [r13-1]\nnop dword ptr [rax]\nloc_1308:\nxor eax, eax\njmp short loc_131C\nloc_1310:\nlea rdx, [rax+1]\ncmp rax, rsi\njz short loc_1338\nmov rax, rdx\nloc_131C:\nmovzx edx, byte ptr [rcx+rax]\ncmp [rbx+rax], dl\njz short loc_1310\nadd edi, 1\nadd rcx, 1\ncmp r12d, edi\njge short loc_1308\nloc_1331:\nmov edi, r13d\nnop dword ptr [rax+00h]\nloc_1338:\nmov rax, [rbp+var_28]\nsub rax, fs:28h\njnz short loc_1361\nlea rsp, [rbp-20h]\nmov eax, edi\npop rbx\npop r12\npop r13\npop r14\npop rbp\nretn\nloc_1356:\nor [rsp+rdx+1030h+var_1038], 0\njmp loc_12CB\nloc_1361:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1250(const char *a1)\n{\n size_t v2; // r13\n __int64 v3; // r14\n char *v4; // rcx\n signed __int64 v5; // rdx\n void *v6; // rsp\n char *v7; // rcx\n int v8; // edi\n __int64 i; // rax\n __int64 v11; // [rsp+0h] [rbp-1038h]\n char v12; // [rsp+8h] [rbp-1030h] BYREF\n char v13; // [rsp+9h] [rbp-102Fh] BYREF\n _QWORD v14[6]; // [rsp+1008h] [rbp-30h] BYREF\n\n v14[1] = __readfsqword(0x28u);\n v2 = strlen(a1);\n v3 = 2 * (int)v2 + 1;\n v4 = (char *)v14 - ((v3 + 15) & 0xFFFFFFFFFFFFF000LL);\n if ( v14 != (_QWORD *)v4 )\n {\n while ( &v12 != v4 )\n ;\n }\n v5 = (2 * (_WORD)v2 + 16) & 0xFF0;\n v6 = alloca(v5);\n if ( ((2 * (_WORD)v2 + 16) & 0xFF0) != 0 )\n *(__int64 *)((char *)&v11 + v5) = *(__int64 *)((char *)&v11 + v5);\n __memcpy_chk(&v12, a1, v2, v3);\n __memcpy_chk(&v12 + v2, a1, v2 + 1, v3 - v2);\n if ( (int)v2 > 0 )\n {\n v7 = &v13;\n v8 = 1;\n do\n {\n for ( i = 0LL; a1[i] == v7[i]; ++i )\n {\n if ( i == (_DWORD)v2 - 1 )\n return (unsigned int)v8;\n }\n ++v8;\n ++v7;\n }\n while ( (int)v2 >= v8 );\n }\n return (unsigned int)v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1250(const char *a1) {\n unsigned int v2;\n long long v3;\n char *v4;\n signed long long v5;\n void *v6;\n char *v7;\n int v8;\n long long i;\n long long v11;\n char v12;\n char v13;\n uint64_t v14[6];\n v14[1] = __readfsqword(40u);\n v2 = strlen(a1);\n v3 = 2 * (int)v2 + 1;\n v4 = (char *)v14 - ((v3 + 15) & 18446744073709547520LL);\n if (v14 != (uint64_t *)v4) {\n while (&v12 != v4)\n ;\n }\n v5 = (2 * (unsigned short)v2 + 16) & 4080;\n v6 = alloca(v5);\n if (((2 * (unsigned short)v2 + 16) & 4080) != 0)\n *(long long *)((char *)&v11 + v5) = *(long long *)((char *)&v11 + v5);\n __memcpy_chk(&v12, a1, v2, v3);\n __memcpy_chk(&v12 + v2, a1, v2 + 1, v3 - v2);\n if ((int)v2 > 0) {\n v7 = &v13;\n v8 = 1;\n do {\n for (i = 0LL; a1[i] == v7[i]; ++i) {\n if (i == (uint32_t)v2 - 1) return (unsigned int)v8;\n }\n ++v8;\n ++v7;\n } while ((int)v2 >= v8);\n }\n return (unsigned int)v2;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n unsigned int v2;\n long long v3;\n char *v4;\n signed long long v5;\n void *v6;\n char *v7;\n int v8;\n long long i;\n long long v11;\n char v12;\n char v13;\n uint64_t v14[6];\n v14[1] = __readfsqword(40u);\n v2 = strlen(a1);\n v3 = 2 * (int)v2 + 1;\n v4 = (char *)v14 - ((v3 + 15) & 18446744073709547520LL);\n if (v14 != (uint64_t *)v4) {\n while (&v12 != v4)\n ;\n }\n v5 = (2 * (unsigned short)v2 + 16) & 4080;\n v6 = alloca(v5);\n if (((2 * (unsigned short)v2 + 16) & 4080) != 0)\n *(long long *)((char *)&v11 + v5) = *(long long *)((char *)&v11 + v5);\n __memcpy_chk(&v12, a1, v2, v3);\n __memcpy_chk(&v12 + v2, a1, v2 + 1, v3 - v2);\n if ((int)v2 > 0) {\n v7 = &v13;\n v8 = 1;\n do {\n for (i = 0LL; a1[i] == v7[i]; ++i) {\n if (i == (uint32_t)v2 - 1) return (unsigned int)v8;\n }\n ++v8;\n ++v7;\n } while ((int)v2 >= v8);\n }\n return (unsigned int)v2;\n}" + }, + { + "index": 9, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char* str) {\n int n = strlen(str);\n char tmp[2 * n + 1];\n strcpy(tmp, str);\n strcat(tmp, str);\n for (int i = 1; i <= n; i++) {\n int equal = 1;\n for (int j = 0; j < n; j++) {\n if (str[j] != tmp[i + j]) {\n equal = 0;\n break;\n }\n }\n if (equal) {\n return i;\n }\n }\n return n;\n}", + "test": "int main() {\n\n assert(func0(\"aaaa\") == 1);\n\n assert(func0(\"ab\") == 2);\n\n assert(func0(\"abc\") == 3);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r13\npush %r12\npush %rbx\nmov %rdi,%rbx\nsub $0x18,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x28(%rbp)\nxor %eax,%eax\ncallq 1080 \nmov %rsp,%rsi\nmov %rax,%r13\nmov %eax,%r12d\nlea 0x1(%rax,%rax,1),%eax\ncltq\nadd $0xf,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rsi\nand $0xfffffffffffffff0,%rdx\nmov %rsi,%rax\ncmp %rax,%rsp\nje 12b8 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 12a3 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 134d \nmov %r13,%rdx\nmov %rbx,%rsi\nmov %rsp,%rdi\ncallq 10b0 \nmov %rbx,%rsi\nlea (%rsp,%r13,1),%rdi\nlea 0x1(%r13),%rdx\ncallq 10b0 \nlea 0x1(%rsp),%rcx\nmov $0x1,%r8d\nlea -0x1(%r13),%esi\ntest %r13d,%r13d\njle 132b \nnopl 0x0(%rax)\nxor %eax,%eax\njmp 1314 \nnopl 0x0(%rax)\nlea 0x1(%rax),%rdx\ncmp %rax,%rsi\nje 1330 \nmov %rdx,%rax\nmovzbl (%rcx,%rax,1),%edi\ncmp %dil,(%rbx,%rax,1)\nje 1308 \nadd $0x1,%r8d\nadd $0x1,%rcx\ncmp %r8d,%r12d\njge 1300 \nmov %r13d,%r8d\nxchg %ax,%ax\nmov -0x28(%rbp),%rax\nxor %fs:0x28,%rax\njne 1358 \nlea -0x18(%rbp),%rsp\nmov %r8d,%eax\npop %rbx\npop %r12\npop %r13\npop %rbp\nretq\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 12ca \ncallq 1090 <__stack_chk_fail@plt>\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r14\npush r13\npush r12\npush rbx\nmov rbx, rdi\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\ncall _strlen\nmov rcx, rsp\nlea r14d, [rax+rax+1]\nmov r13, rax\nmov r12d, eax\nmovsxd r14, r14d\nlea rax, [r14+0Fh]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_12B9\nloc_12A4:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rcx\njnz short loc_12A4\nloc_12B9:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1356\nloc_12CB:\nmov rcx, r14\nmov rdx, r13\nmov rsi, rbx\nmov rdi, rsp\ncall ___memcpy_chk\nmov rcx, r14\nlea rdx, [r13+1]\nlea rdi, [rsp+r13+1030h+var_1030]\nsub rcx, r13\nmov rsi, rbx\ncall ___memcpy_chk\ntest r13d, r13d\njle short loc_1331\nlea rcx, [rsp+1030h+var_102F]\nmov edi, 1\nlea esi, [r13-1]\nnop dword ptr [rax]\nloc_1308:\nxor eax, eax\njmp short loc_131C\nloc_1310:\nlea rdx, [rax+1]\ncmp rax, rsi\njz short loc_1338\nmov rax, rdx\nloc_131C:\nmovzx edx, byte ptr [rcx+rax]\ncmp [rbx+rax], dl\njz short loc_1310\nadd edi, 1\nadd rcx, 1\ncmp r12d, edi\njge short loc_1308\nloc_1331:\nmov edi, r13d\nnop dword ptr [rax+00h]\nloc_1338:\nmov rax, [rbp+var_28]\nsub rax, fs:28h\njnz short loc_1361\nlea rsp, [rbp-20h]\nmov eax, edi\npop rbx\npop r12\npop r13\npop r14\npop rbp\nretn\nloc_1356:\nor [rsp+rdx+1030h+var_1038], 0\njmp loc_12CB\nloc_1361:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n size_t v2; // r13\n __int64 v3; // r14\n char *v4; // rcx\n signed __int64 v5; // rdx\n void *v6; // rsp\n char *v7; // rcx\n int v8; // edi\n __int64 i; // rax\n __int64 v11; // [rsp+0h] [rbp-1038h]\n char v12; // [rsp+8h] [rbp-1030h] BYREF\n char v13; // [rsp+9h] [rbp-102Fh] BYREF\n _QWORD v14[6]; // [rsp+1008h] [rbp-30h] BYREF\n\n v14[1] = __readfsqword(0x28u);\n v2 = strlen(a1);\n v3 = 2 * (int)v2 + 1;\n v4 = (char *)v14 - ((v3 + 15) & 0xFFFFFFFFFFFFF000LL);\n if ( v14 != (_QWORD *)v4 )\n {\n while ( &v12 != v4 )\n ;\n }\n v5 = (2 * (_WORD)v2 + 16) & 0xFF0;\n v6 = alloca(v5);\n if ( ((2 * (_WORD)v2 + 16) & 0xFF0) != 0 )\n *(__int64 *)((char *)&v11 + v5) = *(__int64 *)((char *)&v11 + v5);\n __memcpy_chk(&v12, a1, v2, v3);\n __memcpy_chk(&v12 + v2, a1, v2 + 1, v3 - v2);\n if ( (int)v2 > 0 )\n {\n v7 = &v13;\n v8 = 1;\n do\n {\n for ( i = 0LL; a1[i] == v7[i]; ++i )\n {\n if ( i == (_DWORD)v2 - 1 )\n return (unsigned int)v8;\n }\n ++v8;\n ++v7;\n }\n while ( (int)v2 >= v8 );\n }\n return (unsigned int)v2;\n}", + "ida_strip_asm": "sub_1250:\nendbr64\npush rbp\nmov rbp, rsp\npush r14\npush r13\npush r12\npush rbx\nmov rbx, rdi\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\ncall _strlen\nmov rcx, rsp\nlea r14d, [rax+rax+1]\nmov r13, rax\nmov r12d, eax\nmovsxd r14, r14d\nlea rax, [r14+0Fh]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_12B9\nloc_12A4:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rcx\njnz short loc_12A4\nloc_12B9:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1356\nloc_12CB:\nmov rcx, r14\nmov rdx, r13\nmov rsi, rbx\nmov rdi, rsp\ncall ___memcpy_chk\nmov rcx, r14\nlea rdx, [r13+1]\nlea rdi, [rsp+r13+1030h+var_1030]\nsub rcx, r13\nmov rsi, rbx\ncall ___memcpy_chk\ntest r13d, r13d\njle short loc_1331\nlea rcx, [rsp+1030h+var_102F]\nmov edi, 1\nlea esi, [r13-1]\nnop dword ptr [rax]\nloc_1308:\nxor eax, eax\njmp short loc_131C\nloc_1310:\nlea rdx, [rax+1]\ncmp rax, rsi\njz short loc_1338\nmov rax, rdx\nloc_131C:\nmovzx edx, byte ptr [rcx+rax]\ncmp [rbx+rax], dl\njz short loc_1310\nadd edi, 1\nadd rcx, 1\ncmp r12d, edi\njge short loc_1308\nloc_1331:\nmov edi, r13d\nnop dword ptr [rax+00h]\nloc_1338:\nmov rax, [rbp+var_28]\nsub rax, fs:28h\njnz short loc_1361\nlea rsp, [rbp-20h]\nmov eax, edi\npop rbx\npop r12\npop r13\npop r14\npop rbp\nretn\nloc_1356:\nor [rsp+rdx+1030h+var_1038], 0\njmp loc_12CB\nloc_1361:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1250(const char *a1)\n{\n size_t v2; // r13\n __int64 v3; // r14\n char *v4; // rcx\n signed __int64 v5; // rdx\n void *v6; // rsp\n char *v7; // rcx\n int v8; // edi\n __int64 i; // rax\n __int64 v11; // [rsp+0h] [rbp-1038h]\n char v12; // [rsp+8h] [rbp-1030h] BYREF\n char v13; // [rsp+9h] [rbp-102Fh] BYREF\n _QWORD v14[6]; // [rsp+1008h] [rbp-30h] BYREF\n\n v14[1] = __readfsqword(0x28u);\n v2 = strlen(a1);\n v3 = 2 * (int)v2 + 1;\n v4 = (char *)v14 - ((v3 + 15) & 0xFFFFFFFFFFFFF000LL);\n if ( v14 != (_QWORD *)v4 )\n {\n while ( &v12 != v4 )\n ;\n }\n v5 = (2 * (_WORD)v2 + 16) & 0xFF0;\n v6 = alloca(v5);\n if ( ((2 * (_WORD)v2 + 16) & 0xFF0) != 0 )\n *(__int64 *)((char *)&v11 + v5) = *(__int64 *)((char *)&v11 + v5);\n __memcpy_chk(&v12, a1, v2, v3);\n __memcpy_chk(&v12 + v2, a1, v2 + 1, v3 - v2);\n if ( (int)v2 > 0 )\n {\n v7 = &v13;\n v8 = 1;\n do\n {\n for ( i = 0LL; a1[i] == v7[i]; ++i )\n {\n if ( i == (_DWORD)v2 - 1 )\n return (unsigned int)v8;\n }\n ++v8;\n ++v7;\n }\n while ( (int)v2 >= v8 );\n }\n return (unsigned int)v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1250(const char *a1) {\n unsigned int v2;\n long long v3;\n char *v4;\n signed long long v5;\n void *v6;\n char *v7;\n int v8;\n long long i;\n long long v11;\n char v12;\n char v13;\n uint64_t v14[6];\n v14[1] = __readfsqword(40u);\n v2 = strlen(a1);\n v3 = 2 * (int)v2 + 1;\n v4 = (char *)v14 - ((v3 + 15) & 18446744073709547520LL);\n if (v14 != (uint64_t *)v4) {\n while (&v12 != v4)\n ;\n }\n v5 = (2 * (unsigned short)v2 + 16) & 4080;\n v6 = alloca(v5);\n if (((2 * (unsigned short)v2 + 16) & 4080) != 0)\n *(long long *)((char *)&v11 + v5) = *(long long *)((char *)&v11 + v5);\n __memcpy_chk(&v12, a1, v2, v3);\n __memcpy_chk(&v12 + v2, a1, v2 + 1, v3 - v2);\n if ((int)v2 > 0) {\n v7 = &v13;\n v8 = 1;\n do {\n for (i = 0LL; a1[i] == v7[i]; ++i) {\n if (i == (uint32_t)v2 - 1) return (unsigned int)v8;\n }\n ++v8;\n ++v7;\n } while ((int)v2 >= v8);\n }\n return (unsigned int)v2;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n unsigned int v2;\n long long v3;\n char *v4;\n signed long long v5;\n void *v6;\n char *v7;\n int v8;\n long long i;\n long long v11;\n char v12;\n char v13;\n uint64_t v14[6];\n v14[1] = __readfsqword(40u);\n v2 = strlen(a1);\n v3 = 2 * (int)v2 + 1;\n v4 = (char *)v14 - ((v3 + 15) & 18446744073709547520LL);\n if (v14 != (uint64_t *)v4) {\n while (&v12 != v4)\n ;\n }\n v5 = (2 * (unsigned short)v2 + 16) & 4080;\n v6 = alloca(v5);\n if (((2 * (unsigned short)v2 + 16) & 4080) != 0)\n *(long long *)((char *)&v11 + v5) = *(long long *)((char *)&v11 + v5);\n __memcpy_chk(&v12, a1, v2, v3);\n __memcpy_chk(&v12 + v2, a1, v2 + 1, v3 - v2);\n if ((int)v2 > 0) {\n v7 = &v13;\n v8 = 1;\n do {\n for (i = 0LL; a1[i] == v7[i]; ++i) {\n if (i == (uint32_t)v2 - 1) return (unsigned int)v8;\n }\n ++v8;\n ++v7;\n } while ((int)v2 >= v8);\n }\n return (unsigned int)v2;\n}" + }, + { + "index": 10, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int arr[], int size, int n, int result[]) {\n int i, j, temp;\n for (i = 0; i < n; i++) {\n result[i] = arr[i];\n }\n for (i = 0; i < n; i++) {\n for (j = i + 1; j < n; j++) {\n if (result[i] > result[j]) {\n temp = result[i];\n result[i] = result[j];\n result[j] = temp;\n }\n }\n }\n for (i = n; i < size; i++) {\n if (arr[i] < result[n - 1]) {\n result[n - 1] = arr[i];\n for (j = n - 1; j > 0 && result[j] < result[j - 1]; j--) {\n temp = result[j];\n result[j] = result[j - 1];\n result[j - 1] = temp;\n }\n }\n }\n}", + "test": "int main() {\n\n int arr1[] = {10, 20, 50, 70, 90, 20, 50, 40, 60, 80, 100};\n\n int size1 = sizeof(arr1) / sizeof(arr1[0]);\n\n int result1[2], result2[5], result3[3];\n\n\n\n func0(arr1, size1, 2, result1);\n\n func0(arr1, size1, 5, result2);\n\n func0(arr1, size1, 3, result3);\n\n \n\n assert(result1[0] == 10 && result1[1] == 20);\n\n assert(result2[0] == 10 && result2[1] == 20 && result2[2] == 20 && result2[3] == 40 && result2[4] == 50);\n\n assert(result3[0] == 10 && result3[1] == 20 && result3[2] == 20);\n\n \n\n printf(\"All tests passed!\\n\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmov %rcx,-0x28(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 11d9 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0xc(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x28(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x20(%rbp),%eax\njl 11a8 \nmovl $0x0,-0xc(%rbp)\njmpq 129e \nmov -0xc(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x8(%rbp)\njmpq 128e \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njle 128a \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x4(%rbp)\nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov -0xc(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x28(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rax,%rdx\nmov -0x4(%rbp),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x20(%rbp),%eax\njl 11fb \naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x20(%rbp),%eax\njl 11ed \nmov -0x20(%rbp),%eax\nmov %eax,-0xc(%rbp)\njmpq 13c2 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x20(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njge 13be \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0x20(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x2,%rdx\nlea -0x4(%rdx),%rcx\nmov -0x28(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\nmov -0x20(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0x8(%rbp)\njmp 1384 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x4(%rbp)\nmov -0x8(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov -0x8(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x28(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\nmov -0x8(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rdx\nmov -0x28(%rbp),%rax\nadd %rax,%rdx\nmov -0x4(%rbp),%eax\nmov %eax,(%rdx)\nsubl $0x1,-0x8(%rbp)\ncmpl $0x0,-0x8(%rbp)\njle 13be \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x8(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njl 1321 \naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 12b5 \npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_28], rcx\nmov [rbp+var_C], 0\njmp short loc_11D9\nloc_11A8:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_C], 1\nloc_11D9:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_20]\njl short loc_11A8\nmov [rbp+var_C], 0\njmp loc_129E\nloc_11ED:\nmov eax, [rbp+var_C]\nadd eax, 1\nmov [rbp+var_8], eax\njmp loc_128E\nloc_11FB:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_128A\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nloc_128A:\nadd [rbp+var_8], 1\nloc_128E:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_20]\njl loc_11FB\nadd [rbp+var_C], 1\nloc_129E:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_20]\njl loc_11ED\nmov eax, [rbp+var_20]\nmov [rbp+var_C], eax\njmp loc_13C2\nloc_12B5:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_20]\ncdqe\nshl rax, 2\nlea rcx, [rax-4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njge loc_13BE\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nshl rdx, 2\nlea rcx, [rdx-4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_20]\nsub eax, 1\nmov [rbp+var_8], eax\njmp short loc_1384\nloc_1321:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_8]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_8]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nsub [rbp+var_8], 1\nloc_1384:\ncmp [rbp+var_8], 0\njle short loc_13BE\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nshl rax, 2\nlea rcx, [rax-4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njl loc_1321\nloc_13BE:\nadd [rbp+var_C], 1\nloc_13C2:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl loc_12B5\nnop\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3, __int64 a4)\n{\n __int64 result; // rax\n int i; // [rsp+1Ch] [rbp-Ch]\n int j; // [rsp+1Ch] [rbp-Ch]\n unsigned int m; // [rsp+1Ch] [rbp-Ch]\n int k; // [rsp+20h] [rbp-8h]\n int n; // [rsp+20h] [rbp-8h]\n int v10; // [rsp+24h] [rbp-4h]\n int v11; // [rsp+24h] [rbp-4h]\n\n for ( i = 0; i < a3; ++i )\n *(_DWORD *)(4LL * i + a4) = *(_DWORD *)(4LL * i + a1);\n for ( j = 0; j < a3; ++j )\n {\n for ( k = j + 1; k < a3; ++k )\n {\n if ( *(_DWORD *)(4LL * j + a4) > *(_DWORD *)(4LL * k + a4) )\n {\n v10 = *(_DWORD *)(4LL * j + a4);\n *(_DWORD *)(4LL * j + a4) = *(_DWORD *)(4LL * k + a4);\n *(_DWORD *)(a4 + 4LL * k) = v10;\n }\n }\n }\n for ( m = a3; ; ++m )\n {\n result = m;\n if ( (int)m >= a2 )\n break;\n if ( *(_DWORD *)(4LL * (int)m + a1) < *(_DWORD *)(4LL * a3 - 4 + a4) )\n {\n *(_DWORD *)(4LL * a3 - 4 + a4) = *(_DWORD *)(4LL * (int)m + a1);\n for ( n = a3 - 1; n > 0 && *(_DWORD *)(4LL * n + a4) < *(_DWORD *)(4LL * n - 4 + a4); --n )\n {\n v11 = *(_DWORD *)(4LL * n + a4);\n *(_DWORD *)(4LL * n + a4) = *(_DWORD *)(4LL * n - 4 + a4);\n *(_DWORD *)(a4 + 4LL * n - 4) = v11;\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_28], rcx\nmov [rbp+var_C], 0\njmp short loc_11D9\nloc_11A8:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_C], 1\nloc_11D9:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_20]\njl short loc_11A8\nmov [rbp+var_C], 0\njmp loc_129E\nloc_11ED:\nmov eax, [rbp+var_C]\nadd eax, 1\nmov [rbp+var_8], eax\njmp loc_128E\nloc_11FB:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_128A\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nloc_128A:\nadd [rbp+var_8], 1\nloc_128E:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_20]\njl loc_11FB\nadd [rbp+var_C], 1\nloc_129E:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_20]\njl loc_11ED\nmov eax, [rbp+var_20]\nmov [rbp+var_C], eax\njmp loc_13C2\nloc_12B5:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_20]\ncdqe\nshl rax, 2\nlea rcx, [rax-4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njge loc_13BE\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nshl rdx, 2\nlea rcx, [rdx-4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_20]\nsub eax, 1\nmov [rbp+var_8], eax\njmp short loc_1384\nloc_1321:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_8]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_8]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nsub [rbp+var_8], 1\nloc_1384:\ncmp [rbp+var_8], 0\njle short loc_13BE\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nshl rax, 2\nlea rcx, [rax-4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njl loc_1321\nloc_13BE:\nadd [rbp+var_C], 1\nloc_13C2:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl loc_12B5\nnop\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2, int a3, __int64 a4)\n{\n __int64 result; // rax\n int i; // [rsp+1Ch] [rbp-Ch]\n int j; // [rsp+1Ch] [rbp-Ch]\n unsigned int m; // [rsp+1Ch] [rbp-Ch]\n int k; // [rsp+20h] [rbp-8h]\n int n; // [rsp+20h] [rbp-8h]\n int v10; // [rsp+24h] [rbp-4h]\n int v11; // [rsp+24h] [rbp-4h]\n\n for ( i = 0; i < a3; ++i )\n *(_DWORD *)(4LL * i + a4) = *(_DWORD *)(4LL * i + a1);\n for ( j = 0; j < a3; ++j )\n {\n for ( k = j + 1; k < a3; ++k )\n {\n if ( *(_DWORD *)(4LL * j + a4) > *(_DWORD *)(4LL * k + a4) )\n {\n v10 = *(_DWORD *)(4LL * j + a4);\n *(_DWORD *)(4LL * j + a4) = *(_DWORD *)(4LL * k + a4);\n *(_DWORD *)(a4 + 4LL * k) = v10;\n }\n }\n }\n for ( m = a3; ; ++m )\n {\n result = m;\n if ( (int)m >= a2 )\n break;\n if ( *(_DWORD *)(4LL * (int)m + a1) < *(_DWORD *)(4LL * a3 - 4 + a4) )\n {\n *(_DWORD *)(4LL * a3 - 4 + a4) = *(_DWORD *)(4LL * (int)m + a1);\n for ( n = a3 - 1; n > 0 && *(_DWORD *)(4LL * n + a4) < *(_DWORD *)(4LL * n - 4 + a4); --n )\n {\n v11 = *(_DWORD *)(4LL * n + a4);\n *(_DWORD *)(4LL * n + a4) = *(_DWORD *)(4LL * n - 4 + a4);\n *(_DWORD *)(a4 + 4LL * n - 4) = v11;\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2, int a3, long long a4) {\n long long result;\n int i;\n int j;\n unsigned int m;\n int k;\n int n;\n int v10;\n int v11;\n for (i = 0; i < a3; ++i)\n *(uint32_t *)(4LL * i + a4) = *(uint32_t *)(4LL * i + a1);\n for (j = 0; j < a3; ++j) {\n for (k = j + 1; k < a3; ++k) {\n if (*(uint32_t *)(4LL * j + a4) > *(uint32_t *)(4LL * k + a4)) {\n v10 = *(uint32_t *)(4LL * j + a4);\n *(uint32_t *)(4LL * j + a4) = *(uint32_t *)(4LL * k + a4);\n *(uint32_t *)(a4 + 4LL * k) = v10;\n }\n }\n }\n for (m = a3;; ++m) {\n result = m;\n if ((int)m >= a2) break;\n if (*(uint32_t *)(4LL * (int)m + a1) < *(uint32_t *)(4LL * a3 - 4 + a4)) {\n *(uint32_t *)(4LL * a3 - 4 + a4) = *(uint32_t *)(4LL * (int)m + a1);\n for (n = a3 - 1; n > 0 && *(uint32_t *)(4LL * n + a4) <\n *(uint32_t *)(4LL * n - 4 + a4);\n --n) {\n v11 = *(uint32_t *)(4LL * n + a4);\n *(uint32_t *)(4LL * n + a4) = *(uint32_t *)(4LL * n - 4 + a4);\n *(uint32_t *)(a4 + 4LL * n - 4) = v11;\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3, long long a4) {\n long long result;\n int i;\n int j;\n unsigned int m;\n int k;\n int n;\n int v10;\n int v11;\n for (i = 0; i < a3; ++i)\n *(uint32_t *)(4LL * i + a4) = *(uint32_t *)(4LL * i + a1);\n for (j = 0; j < a3; ++j) {\n for (k = j + 1; k < a3; ++k) {\n if (*(uint32_t *)(4LL * j + a4) > *(uint32_t *)(4LL * k + a4)) {\n v10 = *(uint32_t *)(4LL * j + a4);\n *(uint32_t *)(4LL * j + a4) = *(uint32_t *)(4LL * k + a4);\n *(uint32_t *)(a4 + 4LL * k) = v10;\n }\n }\n }\n for (m = a3;; ++m) {\n result = m;\n if ((int)m >= a2) break;\n if (*(uint32_t *)(4LL * (int)m + a1) < *(uint32_t *)(4LL * a3 - 4 + a4)) {\n *(uint32_t *)(4LL * a3 - 4 + a4) = *(uint32_t *)(4LL * (int)m + a1);\n for (n = a3 - 1; n > 0 && *(uint32_t *)(4LL * n + a4) <\n *(uint32_t *)(4LL * n - 4 + a4);\n --n) {\n v11 = *(uint32_t *)(4LL * n + a4);\n *(uint32_t *)(4LL * n + a4) = *(uint32_t *)(4LL * n - 4 + a4);\n *(uint32_t *)(a4 + 4LL * n - 4) = v11;\n }\n }\n }\n return result;\n}" + }, + { + "index": 10, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int arr[], int size, int n, int result[]) {\n int i, j, temp;\n for (i = 0; i < n; i++) {\n result[i] = arr[i];\n }\n for (i = 0; i < n; i++) {\n for (j = i + 1; j < n; j++) {\n if (result[i] > result[j]) {\n temp = result[i];\n result[i] = result[j];\n result[j] = temp;\n }\n }\n }\n for (i = n; i < size; i++) {\n if (arr[i] < result[n - 1]) {\n result[n - 1] = arr[i];\n for (j = n - 1; j > 0 && result[j] < result[j - 1]; j--) {\n temp = result[j];\n result[j] = result[j - 1];\n result[j - 1] = temp;\n }\n }\n }\n}", + "test": "int main() {\n\n int arr1[] = {10, 20, 50, 70, 90, 20, 50, 40, 60, 80, 100};\n\n int size1 = sizeof(arr1) / sizeof(arr1[0]);\n\n int result1[2], result2[5], result3[3];\n\n\n\n func0(arr1, size1, 2, result1);\n\n func0(arr1, size1, 5, result2);\n\n func0(arr1, size1, 3, result3);\n\n \n\n assert(result1[0] == 10 && result1[1] == 20);\n\n assert(result2[0] == 10 && result2[1] == 20 && result2[2] == 20 && result2[3] == 40 && result2[4] == 50);\n\n assert(result3[0] == 10 && result3[1] == 20 && result3[2] == 20);\n\n \n\n printf(\"All tests passed!\\n\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\ntest %edx,%edx\njle 11ed \nlea -0x1(%rdx),%r9d\nlea 0x1(%r9),%rbx\nmov $0x0,%eax\nmov (%rdi,%rax,4),%r8d\nmov %r8d,(%rcx,%rax,4)\nmov %rax,%r8\nadd $0x1,%rax\ncmp %r9,%r8\njne 119f \nmov %rcx,%r10\nmov $0x1,%r11d\njmp 11e3 \nadd $0x1,%rax\ncmp %eax,%edx\njle 11db \nmov (%r10),%r8d\nmov (%rcx,%rax,4),%r9d\ncmp %r9d,%r8d\njle 11be \nmov %r9d,(%r10)\nmov %r8d,(%rcx,%rax,4)\njmp 11be \nadd $0x1,%r11\nadd $0x4,%r10\ncmp %rbx,%r11\nje 11ed \nmov %r11,%rax\njmp 11c6 \ncmp %esi,%edx\njge 1261 \nmovslq %edx,%rax\nlea 0x0(,%rax,4),%r11\nlea -0x4(%rcx,%r11,1),%r9\nlea (%rdi,%r11,1),%r8\nsub $0x1,%esi\nsub %edx,%esi\nadd %rsi,%rax\nlea 0x4(%rdi,%rax,4),%r10\nlea -0x1(%rdx),%eax\ncltq\nlea (%rcx,%rax,4),%rbx\nlea -0x8(%rcx,%r11,1),%rdi\nlea -0x2(%rdx),%eax\nshl $0x2,%rax\nsub %rax,%rdi\njmp 1235 \nadd $0x4,%r8\ncmp %r10,%r8\nje 1261 \nmov (%r8),%eax\ncmp (%r9),%eax\njge 122c \nmov %eax,(%r9)\nmov %rbx,%rax\ncmp $0x1,%edx\njle 122c \nmov (%rax),%esi\nmov -0x4(%rax),%ecx\ncmp %ecx,%esi\njge 122c \nmov %ecx,(%rax)\nmov %esi,-0x4(%rax)\nsub $0x4,%rax\ncmp %rdi,%rax\njne 1248 \njmp 122c \npop %rbx\nretq\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r11, rdi\nmov ebx, esi\nmov r9d, edx\nmov r10, rcx\ntest edx, edx\njle short loc_121F\nmovsxd r12, edx\nlea rcx, ds:0[r12*4]\nmov eax, 0\nloc_11B4:\nmov edx, [r11+rax]\nmov [r10+rax], edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_11B4\nlea rsi, [r10+4]\nlea r14d, [r9-1]\nmov ebp, r9d\nmov r8d, 1\nlea r13, [r10+8]\njmp short loc_1205\nloc_11DC:\nadd rax, 4\ncmp rax, rdi\njz short loc_11F5\nloc_11E5:\nmov edx, [rsi-4]\nmov ecx, [rax]\ncmp edx, ecx\njle short loc_11DC\nmov [rsi-4], ecx\nmov [rax], edx\njmp short loc_11DC\nloc_11F5:\nlea rax, [r8+1]\nadd rsi, 4\ncmp r8, r12\njz short loc_121F\nmov r8, rax\nloc_1205:\ncmp r8, rbp\njz short loc_121F\nmov eax, r14d\nsub eax, r8d\nlea rax, [r8+rax-1]\nlea rdi, [r13+rax*4+0]\nmov rax, rsi\njmp short loc_11E5\nloc_121F:\ncmp r9d, ebx\njge short loc_1293\nmovsxd rax, r9d\nlea rdx, ds:0[rax*4]\nlea r8, [r10+rdx-4]\nlea rsi, [r11+rdx]\nsub ebx, r9d\nadd rax, rbx\nlea r11, [r11+rax*4]\nlea eax, [r9-1]\ncdqe\nlea rbx, [r10+rax*4]\nlea rdi, [r10+rdx-8]\nlea eax, [r9-2]\nshl rax, 2\nsub rdi, rax\njmp short loc_1267\nloc_125E:\nadd rsi, 4\ncmp rsi, r11\njz short loc_1293\nloc_1267:\nmov eax, [rsi]\ncmp eax, [r8]\njge short loc_125E\nmov [r8], eax\nmov rax, rbx\ncmp r9d, 1\njle short loc_125E\nloc_127A:\nmov ecx, [rax]\nmov edx, [rax-4]\ncmp ecx, edx\njge short loc_125E\nmov [rax], edx\nmov [rax-4], ecx\nsub rax, 4\ncmp rax, rdi\njnz short loc_127A\njmp short loc_125E\nloc_1293:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2, int a3, __int64 a4)\n{\n __int64 v7; // r12\n __int64 v8; // rax\n _DWORD *v9; // rsi\n __int64 i; // r8\n _DWORD *v11; // rax\n int v12; // edx\n __int64 v13; // rdx\n _DWORD *v14; // r8\n _DWORD *v15; // rsi\n _DWORD *v16; // r11\n __int64 v17; // rdi\n int *v18; // rax\n int v19; // ecx\n int v20; // edx\n\n if ( a3 > 0 )\n {\n v7 = a3;\n v8 = 0LL;\n do\n {\n *(_DWORD *)(a4 + v8) = *(_DWORD *)(a1 + v8);\n v8 += 4LL;\n }\n while ( v8 != 4LL * a3 );\n v9 = (_DWORD *)(a4 + 4);\n for ( i = 1LL; i != a3; ++i )\n {\n v11 = v9;\n do\n {\n v12 = *(v9 - 1);\n if ( v12 > *v11 )\n {\n *(v9 - 1) = *v11;\n *v11 = v12;\n }\n ++v11;\n }\n while ( v11 != (_DWORD *)(a4 + 8 + 4 * (i + (unsigned int)(a3 - 1 - i) - 1)) );\n ++v9;\n if ( i == v7 )\n break;\n }\n }\n if ( a3 < a2 )\n {\n v13 = 4LL * a3;\n v14 = (_DWORD *)(a4 + v13 - 4);\n v15 = (_DWORD *)(a1 + v13);\n v16 = (_DWORD *)(a1 + 4 * ((unsigned int)(a2 - a3) + (__int64)a3));\n v17 = a4 + v13 - 8 - 4LL * (unsigned int)(a3 - 2);\n do\n {\n if ( *v15 < *v14 )\n {\n *v14 = *v15;\n v18 = (int *)(a4 + 4LL * (a3 - 1));\n if ( a3 > 1 )\n {\n do\n {\n v19 = *v18;\n v20 = *(v18 - 1);\n if ( *v18 >= v20 )\n break;\n *v18 = v20;\n *--v18 = v19;\n }\n while ( v18 != (int *)v17 );\n }\n }\n ++v15;\n }\n while ( v15 != v16 );\n }\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r11, rdi\nmov ebx, esi\nmov r9d, edx\nmov r10, rcx\ntest edx, edx\njle short loc_121F\nmovsxd r12, edx\nlea rcx, ds:0[r12*4]\nmov eax, 0\nloc_11B4:\nmov edx, [r11+rax]\nmov [r10+rax], edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_11B4\nlea rsi, [r10+4]\nlea r14d, [r9-1]\nmov ebp, r9d\nmov r8d, 1\nlea r13, [r10+8]\njmp short loc_1205\nloc_11DC:\nadd rax, 4\ncmp rax, rdi\njz short loc_11F5\nloc_11E5:\nmov edx, [rsi-4]\nmov ecx, [rax]\ncmp edx, ecx\njle short loc_11DC\nmov [rsi-4], ecx\nmov [rax], edx\njmp short loc_11DC\nloc_11F5:\nlea rax, [r8+1]\nadd rsi, 4\ncmp r8, r12\njz short loc_121F\nmov r8, rax\nloc_1205:\ncmp r8, rbp\njz short loc_121F\nmov eax, r14d\nsub eax, r8d\nlea rax, [r8+rax-1]\nlea rdi, [r13+rax*4+0]\nmov rax, rsi\njmp short loc_11E5\nloc_121F:\ncmp r9d, ebx\njge short loc_1293\nmovsxd rax, r9d\nlea rdx, ds:0[rax*4]\nlea r8, [r10+rdx-4]\nlea rsi, [r11+rdx]\nsub ebx, r9d\nadd rax, rbx\nlea r11, [r11+rax*4]\nlea eax, [r9-1]\ncdqe\nlea rbx, [r10+rax*4]\nlea rdi, [r10+rdx-8]\nlea eax, [r9-2]\nshl rax, 2\nsub rdi, rax\njmp short loc_1267\nloc_125E:\nadd rsi, 4\ncmp rsi, r11\njz short loc_1293\nloc_1267:\nmov eax, [rsi]\ncmp eax, [r8]\njge short loc_125E\nmov [r8], eax\nmov rax, rbx\ncmp r9d, 1\njle short loc_125E\nloc_127A:\nmov ecx, [rax]\nmov edx, [rax-4]\ncmp ecx, edx\njge short loc_125E\nmov [rax], edx\nmov [rax-4], ecx\nsub rax, 4\ncmp rax, rdi\njnz short loc_127A\njmp short loc_125E\nloc_1293:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "void __fastcall sub_1189(__int64 a1, int a2, int a3, __int64 a4)\n{\n __int64 v7; // r12\n __int64 v8; // rax\n _DWORD *v9; // rsi\n __int64 i; // r8\n _DWORD *v11; // rax\n int v12; // edx\n __int64 v13; // rdx\n _DWORD *v14; // r8\n _DWORD *v15; // rsi\n _DWORD *v16; // r11\n __int64 v17; // rdi\n int *v18; // rax\n int v19; // ecx\n int v20; // edx\n\n if ( a3 > 0 )\n {\n v7 = a3;\n v8 = 0LL;\n do\n {\n *(_DWORD *)(a4 + v8) = *(_DWORD *)(a1 + v8);\n v8 += 4LL;\n }\n while ( v8 != 4LL * a3 );\n v9 = (_DWORD *)(a4 + 4);\n for ( i = 1LL; i != a3; ++i )\n {\n v11 = v9;\n do\n {\n v12 = *(v9 - 1);\n if ( v12 > *v11 )\n {\n *(v9 - 1) = *v11;\n *v11 = v12;\n }\n ++v11;\n }\n while ( v11 != (_DWORD *)(a4 + 8 + 4 * (i + (unsigned int)(a3 - 1 - i) - 1)) );\n ++v9;\n if ( i == v7 )\n break;\n }\n }\n if ( a3 < a2 )\n {\n v13 = 4LL * a3;\n v14 = (_DWORD *)(a4 + v13 - 4);\n v15 = (_DWORD *)(a1 + v13);\n v16 = (_DWORD *)(a1 + 4 * ((unsigned int)(a2 - a3) + (__int64)a3));\n v17 = a4 + v13 - 8 - 4LL * (unsigned int)(a3 - 2);\n do\n {\n if ( *v15 < *v14 )\n {\n *v14 = *v15;\n v18 = (int *)(a4 + 4LL * (a3 - 1));\n if ( a3 > 1 )\n {\n do\n {\n v19 = *v18;\n v20 = *(v18 - 1);\n if ( *v18 >= v20 )\n break;\n *v18 = v20;\n *--v18 = v19;\n }\n while ( v18 != (int *)v17 );\n }\n }\n ++v15;\n }\n while ( v15 != v16 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1189(long long a1, int a2, int a3, long long a4) {\n long long v7;\n long long v8;\n uint32_t *v9;\n long long i;\n uint32_t *v11;\n int v12;\n long long v13;\n uint32_t *v14;\n uint32_t *v15;\n uint32_t *v16;\n long long v17;\n int *v18;\n int v19;\n int v20;\n if (a3 > 0) {\n v7 = a3;\n v8 = 0LL;\n do {\n *(uint32_t *)(a4 + v8) = *(uint32_t *)(a1 + v8);\n v8 += 4LL;\n } while (v8 != 4LL * a3);\n v9 = (uint32_t *)(a4 + 4);\n for (i = 1LL; i != a3; ++i) {\n v11 = v9;\n do {\n v12 = *(v9 - 1);\n if (v12 > *v11) {\n *(v9 - 1) = *v11;\n *v11 = v12;\n }\n ++v11;\n } while (v11 !=\n (uint32_t *)(a4 + 8 + 4 * (i + (unsigned int)(a3 - 1 - i) - 1)));\n ++v9;\n if (i == v7) break;\n }\n }\n if (a3 < a2) {\n v13 = 4LL * a3;\n v14 = (uint32_t *)(a4 + v13 - 4);\n v15 = (uint32_t *)(a1 + v13);\n v16 = (uint32_t *)(a1 + 4 * ((unsigned int)(a2 - a3) + (long long)a3));\n v17 = a4 + v13 - 8 - 4LL * (unsigned int)(a3 - 2);\n do {\n if (*v15 < *v14) {\n *v14 = *v15;\n v18 = (int *)(a4 + 4LL * (a3 - 1));\n if (a3 > 1) {\n do {\n v19 = *v18;\n v20 = *(v18 - 1);\n if (*v18 >= v20) break;\n *v18 = v20;\n *--v18 = v19;\n } while (v18 != (int *)v17);\n }\n }\n ++v15;\n } while (v15 != v16);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2, int a3, long long a4) {\n long long v7;\n long long v8;\n uint32_t *v9;\n long long i;\n uint32_t *v11;\n int v12;\n long long v13;\n uint32_t *v14;\n uint32_t *v15;\n uint32_t *v16;\n long long v17;\n int *v18;\n int v19;\n int v20;\n if (a3 > 0) {\n v7 = a3;\n v8 = 0LL;\n do {\n *(uint32_t *)(a4 + v8) = *(uint32_t *)(a1 + v8);\n v8 += 4LL;\n } while (v8 != 4LL * a3);\n v9 = (uint32_t *)(a4 + 4);\n for (i = 1LL; i != a3; ++i) {\n v11 = v9;\n do {\n v12 = *(v9 - 1);\n if (v12 > *v11) {\n *(v9 - 1) = *v11;\n *v11 = v12;\n }\n ++v11;\n } while (v11 !=\n (uint32_t *)(a4 + 8 + 4 * (i + (unsigned int)(a3 - 1 - i) - 1)));\n ++v9;\n if (i == v7) break;\n }\n }\n if (a3 < a2) {\n v13 = 4LL * a3;\n v14 = (uint32_t *)(a4 + v13 - 4);\n v15 = (uint32_t *)(a1 + v13);\n v16 = (uint32_t *)(a1 + 4 * ((unsigned int)(a2 - a3) + (long long)a3));\n v17 = a4 + v13 - 8 - 4LL * (unsigned int)(a3 - 2);\n do {\n if (*v15 < *v14) {\n *v14 = *v15;\n v18 = (int *)(a4 + 4LL * (a3 - 1));\n if (a3 > 1) {\n do {\n v19 = *v18;\n v20 = *(v18 - 1);\n if (*v18 >= v20) break;\n *v18 = v20;\n *--v18 = v19;\n } while (v18 != (int *)v17);\n }\n }\n ++v15;\n } while (v15 != v16);\n }\n}" + }, + { + "index": 10, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int arr[], int size, int n, int result[]) {\n int i, j, temp;\n for (i = 0; i < n; i++) {\n result[i] = arr[i];\n }\n for (i = 0; i < n; i++) {\n for (j = i + 1; j < n; j++) {\n if (result[i] > result[j]) {\n temp = result[i];\n result[i] = result[j];\n result[j] = temp;\n }\n }\n }\n for (i = n; i < size; i++) {\n if (arr[i] < result[n - 1]) {\n result[n - 1] = arr[i];\n for (j = n - 1; j > 0 && result[j] < result[j - 1]; j--) {\n temp = result[j];\n result[j] = result[j - 1];\n result[j - 1] = temp;\n }\n }\n }\n}", + "test": "int main() {\n\n int arr1[] = {10, 20, 50, 70, 90, 20, 50, 40, 60, 80, 100};\n\n int size1 = sizeof(arr1) / sizeof(arr1[0]);\n\n int result1[2], result2[5], result3[3];\n\n\n\n func0(arr1, size1, 2, result1);\n\n func0(arr1, size1, 5, result2);\n\n func0(arr1, size1, 3, result3);\n\n \n\n assert(result1[0] == 10 && result1[1] == 20);\n\n assert(result2[0] == 10 && result2[1] == 20 && result2[2] == 20 && result2[3] == 40 && result2[4] == 50);\n\n assert(result3[0] == 10 && result3[1] == 20 && result3[2] == 20);\n\n \n\n printf(\"All tests passed!\\n\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\ntest %edx,%edx\njle 1390 \nlea -0x1(%rdx),%r9d\nxor %eax,%eax\nlea 0x1(%r9),%rbx\nnopl 0x0(%rax,%rax,1)\nmov (%rdi,%rax,4),%r8d\nmov %r8d,(%rcx,%rax,4)\nmov %rax,%r8\nadd $0x1,%rax\ncmp %r9,%r8\njne 1338 \nmov $0x1,%r11d\nmov %rcx,%r10\ncmp %rbx,%r11\nje 1390 \nnopw 0x0(%rax,%rax,1)\nmov %r11,%rax\nnopl 0x0(%rax,%rax,1)\nmov (%r10),%r8d\nmov (%rcx,%rax,4),%r9d\ncmp %r9d,%r8d\njle 137b \nmov %r9d,(%r10)\nmov %r8d,(%rcx,%rax,4)\nadd $0x1,%rax\ncmp %eax,%edx\njg 1368 \nadd $0x1,%r11\nadd $0x4,%r10\ncmp %rbx,%r11\njne 1360 \ncmp %esi,%edx\njge 140f \nsub $0x1,%esi\nmovslq %edx,%rax\nsub %edx,%esi\nlea 0x0(,%rax,4),%r11\nadd %rsi,%rax\nlea (%rdi,%r11,1),%r8\nlea -0x4(%rcx,%r11,1),%r9\nlea 0x4(%rdi,%rax,4),%r10\nlea -0x1(%rdx),%eax\ncltq\nlea -0x8(%rcx,%r11,1),%rdi\nlea (%rcx,%rax,4),%rbx\nlea -0x2(%rdx),%eax\nshl $0x2,%rax\nsub %rax,%rdi\njmp 13d9 \nadd $0x4,%r8\ncmp %r10,%r8\nje 140f \nmov (%r8),%eax\ncmp (%r9),%eax\njge 13d0 \nmov %eax,(%r9)\nmov %rbx,%rax\ncmp $0x1,%edx\njg 13fd \njmp 13d0 \nxchg %ax,%ax\nmov %ecx,(%rax)\nsub $0x4,%rax\nmov %esi,(%rax)\ncmp %rax,%rdi\nje 13d0 \nmov (%rax),%esi\nmov -0x4(%rax),%ecx\ncmp %ecx,%esi\njl 13f0 \nadd $0x4,%r8\ncmp %r10,%r8\njne 13d9 \npop %rbx\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmov r10, rdi\npush rbx\nmov r11d, esi\nmov r8d, edx\nmov rdi, rcx\ntest edx, edx\njle short loc_1374\nmovsxd rcx, edx\nxor eax, eax\nshl rcx, 2\nxchg ax, ax\nloc_1320:\nmov edx, [r10+rax]\nmov [rdi+rax], edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_1320\nmov rsi, rdi\nmov ebx, r8d\nmov r9d, 1\ncmp r8d, 1\njz short loc_1374\nnop word ptr [rax+rax+00h]\nloc_1348:\nmov rax, r9\nnop dword ptr [rax+rax+00h]\nloc_1350:\nmov edx, [rsi]\nmov ecx, [rdi+rax*4]\ncmp edx, ecx\njle short loc_135E\nmov [rsi], ecx\nmov [rdi+rax*4], edx\nloc_135E:\nadd rax, 1\ncmp r8d, eax\njg short loc_1350\nadd r9, 1\nadd rsi, 4\ncmp r9, rbx\njnz short loc_1348\nloc_1374:\ncmp r8d, r11d\njge loc_1410\nmovsxd rax, r8d\nsub r11d, r8d\nlea rdx, ds:0[rax*4]\nadd rax, r11\nlea rsi, [r10+rdx]\nlea r10, [r10+rax*4]\nlea eax, [r8-1]\nlea r9, [rdi+rdx-4]\ncdqe\nlea r11, [rdi+rax*4-4]\nlea eax, [r8-2]\nlea rdi, [rdi+rdx-0Ch]\nshl rax, 2\nsub rdi, rax\njmp short loc_13C9\nloc_13C0:\nadd rsi, 4\ncmp rsi, r10\njz short loc_1410\nloc_13C9:\nmov eax, [rsi]\ncmp eax, [r9]\njge short loc_13C0\nmov [r9], eax\nmov rdx, r11\ncmp r8d, 1\njg short loc_13ED\njmp short loc_13C0\nloc_13E0:\nmovq qword ptr [rdx], xmm1\nsub rdx, 4\ncmp rdx, rdi\njz short loc_13C0\nloc_13ED:\nmovq xmm0, qword ptr [rdx]\npshufd xmm2, xmm0, 0E5h\nmovd eax, xmm0\nmovd ecx, xmm2\npshufd xmm1, xmm0, 0E1h\ncmp ecx, eax\njl short loc_13E0\nadd rsi, 4\ncmp rsi, r10\njnz short loc_13C9\nloc_1410:\npop rbx\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2, int a3, int *a4)\n{\n __int64 i; // rax\n int *v9; // rsi\n __int64 v10; // r9\n __int64 v11; // rax\n int v12; // edx\n int v13; // ecx\n __int64 v14; // rdx\n int *v15; // rsi\n int *v16; // r10\n int *v17; // r9\n __int64 v18; // r11\n __int64 v19; // rdi\n __m128i *v20; // rdx\n __m128i v21; // xmm0\n unsigned __int64 v22; // xmm1_8\n\n if ( a3 > 0 )\n {\n for ( i = 0LL; i != a3; ++i )\n a4[i] = *(_DWORD *)(a1 + i * 4);\n v9 = a4;\n v10 = 1LL;\n if ( a3 != 1 )\n {\n do\n {\n v11 = v10;\n do\n {\n v12 = *v9;\n v13 = a4[v11];\n if ( *v9 > v13 )\n {\n *v9 = v13;\n a4[v11] = v12;\n }\n ++v11;\n }\n while ( a3 > (int)v11 );\n ++v10;\n ++v9;\n }\n while ( v10 != a3 );\n }\n }\n if ( a3 < a2 )\n {\n v14 = a3;\n v15 = (int *)(a1 + v14 * 4);\n v16 = (int *)(a1 + 4 * ((unsigned int)(a2 - a3) + (__int64)a3));\n v17 = &a4[v14 - 1];\n v18 = (__int64)&a4[a3 - 2];\n v19 = (__int64)&a4[v14 - 3 - (unsigned int)(a3 - 2)];\n do\n {\n while ( 1 )\n {\n if ( *v15 < *v17 )\n {\n *v17 = *v15;\n v20 = (__m128i *)v18;\n if ( a3 > 1 )\n break;\n }\nLABEL_12:\n if ( ++v15 == v16 )\n return;\n }\n while ( 1 )\n {\n v21 = _mm_loadl_epi64(v20);\n v22 = _mm_shuffle_epi32(v21, 225).m128i_u64[0];\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v21, 229)) >= _mm_cvtsi128_si32(v21) )\n break;\n v20->m128i_i64[0] = v22;\n v20 = (__m128i *)((char *)v20 - 4);\n if ( v20 == (__m128i *)v19 )\n goto LABEL_12;\n }\n ++v15;\n }\n while ( v15 != v16 );\n }\n}", + "ida_strip_asm": "sub_1300:\nendbr64\nmov r10, rdi\npush rbx\nmov r11d, esi\nmov r8d, edx\nmov rdi, rcx\ntest edx, edx\njle short loc_1374\nmovsxd rcx, edx\nxor eax, eax\nshl rcx, 2\nxchg ax, ax\nloc_1320:\nmov edx, [r10+rax]\nmov [rdi+rax], edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_1320\nmov rsi, rdi\nmov ebx, r8d\nmov r9d, 1\ncmp r8d, 1\njz short loc_1374\nnop word ptr [rax+rax+00h]\nloc_1348:\nmov rax, r9\nnop dword ptr [rax+rax+00h]\nloc_1350:\nmov edx, [rsi]\nmov ecx, [rdi+rax*4]\ncmp edx, ecx\njle short loc_135E\nmov [rsi], ecx\nmov [rdi+rax*4], edx\nloc_135E:\nadd rax, 1\ncmp r8d, eax\njg short loc_1350\nadd r9, 1\nadd rsi, 4\ncmp r9, rbx\njnz short loc_1348\nloc_1374:\ncmp r8d, r11d\njge loc_1410\nmovsxd rax, r8d\nsub r11d, r8d\nlea rdx, ds:0[rax*4]\nadd rax, r11\nlea rsi, [r10+rdx]\nlea r10, [r10+rax*4]\nlea eax, [r8-1]\nlea r9, [rdi+rdx-4]\ncdqe\nlea r11, [rdi+rax*4-4]\nlea eax, [r8-2]\nlea rdi, [rdi+rdx-0Ch]\nshl rax, 2\nsub rdi, rax\njmp short loc_13C9\nloc_13C0:\nadd rsi, 4\ncmp rsi, r10\njz short loc_1410\nloc_13C9:\nmov eax, [rsi]\ncmp eax, [r9]\njge short loc_13C0\nmov [r9], eax\nmov rdx, r11\ncmp r8d, 1\njg short loc_13ED\njmp short loc_13C0\nloc_13E0:\nmovq qword ptr [rdx], xmm1\nsub rdx, 4\ncmp rdx, rdi\njz short loc_13C0\nloc_13ED:\nmovq xmm0, qword ptr [rdx]\npshufd xmm2, xmm0, 0E5h\nmovd eax, xmm0\nmovd ecx, xmm2\npshufd xmm1, xmm0, 0E1h\ncmp ecx, eax\njl short loc_13E0\nadd rsi, 4\ncmp rsi, r10\njnz short loc_13C9\nloc_1410:\npop rbx\nretn", + "ida_strip_pseudo": "void __fastcall sub_1300(__int64 a1, int a2, int a3, int *a4)\n{\n __int64 i; // rax\n int *v9; // rsi\n __int64 v10; // r9\n __int64 v11; // rax\n int v12; // edx\n int v13; // ecx\n __int64 v14; // rdx\n int *v15; // rsi\n int *v16; // r10\n int *v17; // r9\n __int64 v18; // r11\n __int64 v19; // rdi\n __m128i *v20; // rdx\n __m128i v21; // xmm0\n unsigned __int64 v22; // xmm1_8\n\n if ( a3 > 0 )\n {\n for ( i = 0LL; i != a3; ++i )\n a4[i] = *(_DWORD *)(a1 + i * 4);\n v9 = a4;\n v10 = 1LL;\n if ( a3 != 1 )\n {\n do\n {\n v11 = v10;\n do\n {\n v12 = *v9;\n v13 = a4[v11];\n if ( *v9 > v13 )\n {\n *v9 = v13;\n a4[v11] = v12;\n }\n ++v11;\n }\n while ( a3 > (int)v11 );\n ++v10;\n ++v9;\n }\n while ( v10 != a3 );\n }\n }\n if ( a3 < a2 )\n {\n v14 = a3;\n v15 = (int *)(a1 + v14 * 4);\n v16 = (int *)(a1 + 4 * ((unsigned int)(a2 - a3) + (__int64)a3));\n v17 = &a4[v14 - 1];\n v18 = (__int64)&a4[a3 - 2];\n v19 = (__int64)&a4[v14 - 3 - (unsigned int)(a3 - 2)];\n do\n {\n while ( 1 )\n {\n if ( *v15 < *v17 )\n {\n *v17 = *v15;\n v20 = (__m128i *)v18;\n if ( a3 > 1 )\n break;\n }\nLABEL_12:\n if ( ++v15 == v16 )\n return;\n }\n while ( 1 )\n {\n v21 = _mm_loadl_epi64(v20);\n v22 = _mm_shuffle_epi32(v21, 225).m128i_u64[0];\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v21, 229)) >= _mm_cvtsi128_si32(v21) )\n break;\n v20->m128i_i64[0] = v22;\n v20 = (__m128i *)((char *)v20 - 4);\n if ( v20 == (__m128i *)v19 )\n goto LABEL_12;\n }\n ++v15;\n }\n while ( v15 != v16 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1300(long long a1, int a2, int a3, int *a4) {\n long long i;\n int *v9;\n long long v10;\n long long v11;\n int v12;\n int v13;\n long long v14;\n int *v15;\n int *v16;\n int *v17;\n long long v18;\n long long v19;\n __m128i *v20;\n __m128i v21;\n unsigned long long v22;\n if (a3 > 0) {\n for (i = 0LL; i != a3; ++i) a4[i] = *(uint32_t *)(a1 + i * 4);\n v9 = a4;\n v10 = 1LL;\n if (a3 != 1) {\n do {\n v11 = v10;\n do {\n v12 = *v9;\n v13 = a4[v11];\n if (*v9 > v13) {\n *v9 = v13;\n a4[v11] = v12;\n }\n ++v11;\n } while (a3 > (int)v11);\n ++v10;\n ++v9;\n } while (v10 != a3);\n }\n }\n if (a3 < a2) {\n v14 = a3;\n v15 = (int *)(a1 + v14 * 4);\n v16 = (int *)(a1 + 4 * ((unsigned int)(a2 - a3) + (long long)a3));\n v17 = &a4[v14 - 1];\n v18 = (long long)&a4[a3 - 2];\n v19 = (long long)&a4[v14 - 3 - (unsigned int)(a3 - 2)];\n do {\n while (1) {\n if (*v15 < *v17) {\n *v17 = *v15;\n v20 = (__m128i *)v18;\n if (a3 > 1) break;\n }\n LABEL_12:\n if (++v15 == v16) return;\n }\n while (1) {\n v21 = _mm_loadl_epi64(v20);\n v22 = _mm_shuffle_epi32(v21, 225).m128i_u64[0];\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v21, 229)) >=\n _mm_cvtsi128_si32(v21))\n break;\n v20->m128i_i64[0] = v22;\n v20 = (__m128i *)((char *)v20 - 4);\n if (v20 == (__m128i *)v19) goto LABEL_12;\n }\n ++v15;\n } while (v15 != v16);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2, int a3, int *a4) {\n long long i;\n int *v9;\n long long v10;\n long long v11;\n int v12;\n int v13;\n long long v14;\n int *v15;\n int *v16;\n int *v17;\n long long v18;\n long long v19;\n __m128i *v20;\n __m128i v21;\n unsigned long long v22;\n if (a3 > 0) {\n for (i = 0LL; i != a3; ++i) a4[i] = *(uint32_t *)(a1 + i * 4);\n v9 = a4;\n v10 = 1LL;\n if (a3 != 1) {\n do {\n v11 = v10;\n do {\n v12 = *v9;\n v13 = a4[v11];\n if (*v9 > v13) {\n *v9 = v13;\n a4[v11] = v12;\n }\n ++v11;\n } while (a3 > (int)v11);\n ++v10;\n ++v9;\n } while (v10 != a3);\n }\n }\n if (a3 < a2) {\n v14 = a3;\n v15 = (int *)(a1 + v14 * 4);\n v16 = (int *)(a1 + 4 * ((unsigned int)(a2 - a3) + (long long)a3));\n v17 = &a4[v14 - 1];\n v18 = (long long)&a4[a3 - 2];\n v19 = (long long)&a4[v14 - 3 - (unsigned int)(a3 - 2)];\n do {\n while (1) {\n if (*v15 < *v17) {\n *v17 = *v15;\n v20 = (__m128i *)v18;\n if (a3 > 1) break;\n }\n LABEL_12:\n if (++v15 == v16) return;\n }\n while (1) {\n v21 = _mm_loadl_epi64(v20);\n v22 = _mm_shuffle_epi32(v21, 225).m128i_u64[0];\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v21, 229)) >=\n _mm_cvtsi128_si32(v21))\n break;\n v20->m128i_i64[0] = v22;\n v20 = (__m128i *)((char *)v20 - 4);\n if (v20 == (__m128i *)v19) goto LABEL_12;\n }\n ++v15;\n } while (v15 != v16);\n }\n}" + }, + { + "index": 10, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int arr[], int size, int n, int result[]) {\n int i, j, temp;\n for (i = 0; i < n; i++) {\n result[i] = arr[i];\n }\n for (i = 0; i < n; i++) {\n for (j = i + 1; j < n; j++) {\n if (result[i] > result[j]) {\n temp = result[i];\n result[i] = result[j];\n result[j] = temp;\n }\n }\n }\n for (i = n; i < size; i++) {\n if (arr[i] < result[n - 1]) {\n result[n - 1] = arr[i];\n for (j = n - 1; j > 0 && result[j] < result[j - 1]; j--) {\n temp = result[j];\n result[j] = result[j - 1];\n result[j - 1] = temp;\n }\n }\n }\n}", + "test": "int main() {\n\n int arr1[] = {10, 20, 50, 70, 90, 20, 50, 40, 60, 80, 100};\n\n int size1 = sizeof(arr1) / sizeof(arr1[0]);\n\n int result1[2], result2[5], result3[3];\n\n\n\n func0(arr1, size1, 2, result1);\n\n func0(arr1, size1, 5, result2);\n\n func0(arr1, size1, 3, result3);\n\n \n\n assert(result1[0] == 10 && result1[1] == 20);\n\n assert(result2[0] == 10 && result2[1] == 20 && result2[2] == 20 && result2[3] == 40 && result2[4] == 50);\n\n assert(result3[0] == 10 && result3[1] == 20 && result3[2] == 20);\n\n \n\n printf(\"All tests passed!\\n\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\ntest %edx,%edx\njle 13d0 \nlea 0xf(%rdi),%rax\nlea -0x1(%rdx),%r8d\nsub %rcx,%rax\ncmp $0x1e,%rax\njbe 1461 \ncmp $0x3,%r8d\njbe 1461 \nmov %edx,%r8d\nxor %eax,%eax\nshr $0x2,%r8d\nshl $0x4,%r8\nnopl 0x0(%rax)\nmovdqu (%rdi,%rax,1),%xmm0\nmovups %xmm0,(%rcx,%rax,1)\nadd $0x10,%rax\ncmp %r8,%rax\njne 1340 \nmov %edx,%eax\nand $0xfffffffc,%eax\ntest $0x3,%dl\nje 138c \nmov %eax,%r8d\nmov (%rdi,%r8,4),%r9d\nmov %r9d,(%rcx,%r8,4)\nlea 0x1(%rax),%r8d\ncmp %r8d,%edx\njle 138c \nmovslq %r8d,%r8\nadd $0x2,%eax\nmov (%rdi,%r8,4),%r9d\nmov %r9d,(%rcx,%r8,4)\ncmp %eax,%edx\njle 138c \ncltq\nmov (%rdi,%rax,4),%r8d\nmov %r8d,(%rcx,%rax,4)\nlea -0x2(%rdx),%ebx\nmov %rcx,%r10\nmov $0x1,%r11d\nadd $0x2,%rbx\nnopl 0x0(%rax)\nmov %r11,%rax\nnopl 0x0(%rax,%rax,1)\nmov (%r10),%r8d\nmov (%rcx,%rax,4),%r9d\ncmp %r9d,%r8d\njle 13bb \nmov %r9d,(%r10)\nmov %r8d,(%rcx,%rax,4)\nadd $0x1,%rax\ncmp %eax,%edx\njg 13a8 \nadd $0x1,%r11\nadd $0x4,%r10\ncmp %rbx,%r11\njne 13a0 \ncmp %esi,%edx\njge 145f \nsub $0x1,%esi\nmovslq %edx,%rax\nlea -0x1(%rdx),%r10d\nsub %edx,%esi\nlea 0x0(,%rax,4),%r8\nadd %rsi,%rax\nlea -0x4(%rcx,%r8,1),%r9\nadd %rdi,%r8\nlea 0x4(%rdi,%rax,4),%rdi\nmovslq %r10d,%rax\nshl $0x2,%rax\nlea -0x4(%rcx,%rax,1),%rsi\nlea (%rcx,%rax,1),%r11\nlea -0x2(%rdx),%eax\nshl $0x2,%rax\nsub %rax,%rsi\njmp 1429 \nnopl 0x0(%rax,%rax,1)\nadd $0x4,%r8\ncmp %rdi,%r8\nje 145f \nmov (%r8),%eax\ncmp (%r9),%eax\njge 1420 \nmov %eax,(%r9)\nmov %r11,%rax\ntest %r10d,%r10d\njg 144d \njmp 1420 \nxchg %ax,%ax\nmov %edx,(%rax)\nsub $0x4,%rax\nmov %ecx,(%rax)\ncmp %rsi,%rax\nje 1420 \nmov (%rax),%ecx\nmov -0x4(%rax),%edx\ncmp %edx,%ecx\njl 1440 \nadd $0x4,%r8\ncmp %rdi,%r8\njne 1429 \npop %rbx\nretq\nxor %eax,%eax\nnopl 0x0(%rax,%rax,1)\nmov (%rdi,%rax,4),%r9d\nmov %r9d,(%rcx,%rax,4)\nmov %rax,%r9\nadd $0x1,%rax\ncmp %r8,%r9\njne 1468 \ncmp $0x1,%edx\nje 13d0 \njmpq 138c \nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmov r10, rdi\npush rbx\nmov r11d, esi\nmov r8d, edx\nmov rdi, rcx\ntest edx, edx\njle short loc_1394\nlea eax, [rdx-1]\ncmp eax, 2\njbe short loc_1331\nlea rdx, [r10+4]\nmov rax, rcx\nsub rax, rdx\ncmp rax, 8\nja loc_1432\nloc_1331:\nmovsxd rcx, r8d\nxor eax, eax\nshl rcx, 2\nnop word ptr [rax+rax+00h]\nloc_1340:\nmov edx, [r10+rax]\nmov [rdi+rax], edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_1340\ncmp r8d, 1\njz short loc_1394\nloc_1356:\nmov rsi, rdi\nmov ebx, r8d\nmov r9d, 1\nnop word ptr [rax+rax+00h]\nloc_1368:\nmov rax, r9\nnop dword ptr [rax+rax+00h]\nloc_1370:\nmov edx, [rsi]\nmov ecx, [rdi+rax*4]\ncmp edx, ecx\njle short loc_137E\nmov [rsi], ecx\nmov [rdi+rax*4], edx\nloc_137E:\nadd rax, 1\ncmp r8d, eax\njg short loc_1370\nadd r9, 1\nadd rsi, 4\ncmp r9, rbx\njnz short loc_1368\nloc_1394:\ncmp r8d, r11d\njge loc_1430\nmovsxd rax, r8d\nsub r11d, r8d\nlea ebx, [r8-1]\nlea rsi, ds:0[rax*4]\nadd rax, r11\nlea r9, [rdi+rsi-4]\nadd rsi, r10\nlea r10, [r10+rax*4]\nmovsxd rax, ebx\nshl rax, 2\nlea r11, [rdi+rax-4]\nlea rdi, [rdi+rax-8]\nlea eax, [r8-2]\nshl rax, 2\nsub rdi, rax\njmp short loc_13E9\nloc_13E0:\nadd rsi, 4\ncmp rsi, r10\njz short loc_1430\nloc_13E9:\nmov eax, [rsi]\ncmp eax, [r9]\njge short loc_13E0\nmov [r9], eax\nmov rdx, r11\ntest ebx, ebx\njg short loc_140D\njmp short loc_13E0\nloc_1400:\nmovq qword ptr [rdx], xmm1\nsub rdx, 4\ncmp rdx, rdi\njz short loc_13E0\nloc_140D:\nmovq xmm0, qword ptr [rdx]\npshufd xmm2, xmm0, 0E5h\nmovd ecx, xmm0\nmovd eax, xmm2\npshufd xmm1, xmm0, 0E1h\ncmp ecx, eax\njg short loc_1400\nadd rsi, 4\ncmp rsi, r10\njnz short loc_13E9\nloc_1430:\npop rbx\nretn\nloc_1432:\nmov edx, r8d\nxor eax, eax\nshr edx, 2\nshl rdx, 4\nxchg ax, ax\nloc_1440:\nmovdqu xmm3, xmmword ptr [r10+rax]\nmovups xmmword ptr [rdi+rax], xmm3\nadd rax, 10h\ncmp rax, rdx\njnz short loc_1440\nmov eax, r8d\nand eax, 0FFFFFFFCh\ntest r8b, 3\njz loc_1356\nmov ecx, eax\nmov esi, [r10+rcx*4]\nlea rdx, ds:0[rcx*4]\nmov [rdi+rcx*4], esi\nlea ecx, [rax+1]\ncmp r8d, ecx\njle loc_1356\nmov ecx, [r10+rdx+4]\nadd eax, 2\nmov [rdi+rdx+4], ecx\ncmp r8d, eax\njle loc_1356\nmov eax, [r10+rdx+8]\nmov [rdi+rdx+8], eax\njmp loc_1356", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2, int a3, int *a4)\n{\n __int64 i; // rax\n int *v9; // rsi\n __int64 v10; // r9\n __int64 v11; // rax\n int v12; // edx\n int v13; // ecx\n __int64 v14; // rsi\n int *v15; // r9\n int *v16; // rsi\n int *v17; // r10\n __int64 v18; // rax\n __int64 v19; // r11\n __int64 v20; // rdi\n __m128i *v21; // rdx\n __m128i v22; // xmm0\n unsigned __int64 v23; // xmm1_8\n __int64 v24; // rax\n unsigned int v25; // eax\n __int64 v26; // rdx\n\n if ( a3 > 0 )\n {\n if ( (unsigned int)(a3 - 1) > 2 && (unsigned __int64)a4 - a1 - 4 > 8 )\n {\n v24 = 0LL;\n do\n {\n *(__m128i *)&a4[v24] = _mm_loadu_si128((const __m128i *)(a1 + v24 * 4));\n v24 += 4LL;\n }\n while ( v24 != 4LL * ((unsigned int)a3 >> 2) );\n v25 = a3 & 0xFFFFFFFC;\n if ( (a3 & 3) != 0 )\n {\n v26 = v25;\n a4[v26] = *(_DWORD *)(a1 + v26 * 4);\n if ( a3 > (int)(v25 + 1) )\n {\n a4[v26 + 1] = *(_DWORD *)(a1 + v26 * 4 + 4);\n if ( a3 > (int)(v25 + 2) )\n a4[v26 + 2] = *(_DWORD *)(a1 + v26 * 4 + 8);\n }\n }\n }\n else\n {\n for ( i = 0LL; i != a3; ++i )\n a4[i] = *(_DWORD *)(a1 + i * 4);\n if ( a3 == 1 )\n goto LABEL_13;\n }\n v9 = a4;\n v10 = 1LL;\n do\n {\n v11 = v10;\n do\n {\n v12 = *v9;\n v13 = a4[v11];\n if ( *v9 > v13 )\n {\n *v9 = v13;\n a4[v11] = v12;\n }\n ++v11;\n }\n while ( a3 > (int)v11 );\n ++v10;\n ++v9;\n }\n while ( v10 != a3 );\n }\nLABEL_13:\n if ( a3 < a2 )\n {\n v14 = a3;\n v15 = &a4[v14 - 1];\n v16 = (int *)(a1 + v14 * 4);\n v17 = (int *)(a1 + 4 * ((unsigned int)(a2 - a3) + (__int64)a3));\n v18 = a3 - 1;\n v19 = (__int64)&a4[v18 - 1];\n v20 = (__int64)&a4[v18 - 2 - (unsigned int)(a3 - 2)];\n do\n {\n while ( 1 )\n {\n if ( *v16 < *v15 )\n {\n *v15 = *v16;\n v21 = (__m128i *)v19;\n if ( a3 - 1 > 0 )\n break;\n }\nLABEL_15:\n if ( ++v16 == v17 )\n return;\n }\n while ( 1 )\n {\n v22 = _mm_loadl_epi64(v21);\n v23 = _mm_shuffle_epi32(v22, 225).m128i_u64[0];\n if ( _mm_cvtsi128_si32(v22) <= _mm_cvtsi128_si32(_mm_shuffle_epi32(v22, 229)) )\n break;\n v21->m128i_i64[0] = v23;\n v21 = (__m128i *)((char *)v21 - 4);\n if ( v21 == (__m128i *)v20 )\n goto LABEL_15;\n }\n ++v16;\n }\n while ( v16 != v17 );\n }\n}", + "ida_strip_asm": "sub_1300:\nendbr64\nmov r10, rdi\npush rbx\nmov r11d, esi\nmov r8d, edx\nmov rdi, rcx\ntest edx, edx\njle short loc_1394\nlea eax, [rdx-1]\ncmp eax, 2\njbe short loc_1331\nlea rdx, [r10+4]\nmov rax, rcx\nsub rax, rdx\ncmp rax, 8\nja loc_1432\nloc_1331:\nmovsxd rcx, r8d\nxor eax, eax\nshl rcx, 2\nnop word ptr [rax+rax+00h]\nloc_1340:\nmov edx, [r10+rax]\nmov [rdi+rax], edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_1340\ncmp r8d, 1\njz short loc_1394\nloc_1356:\nmov rsi, rdi\nmov ebx, r8d\nmov r9d, 1\nnop word ptr [rax+rax+00h]\nloc_1368:\nmov rax, r9\nnop dword ptr [rax+rax+00h]\nloc_1370:\nmov edx, [rsi]\nmov ecx, [rdi+rax*4]\ncmp edx, ecx\njle short loc_137E\nmov [rsi], ecx\nmov [rdi+rax*4], edx\nloc_137E:\nadd rax, 1\ncmp r8d, eax\njg short loc_1370\nadd r9, 1\nadd rsi, 4\ncmp r9, rbx\njnz short loc_1368\nloc_1394:\ncmp r8d, r11d\njge loc_1430\nmovsxd rax, r8d\nsub r11d, r8d\nlea ebx, [r8-1]\nlea rsi, ds:0[rax*4]\nadd rax, r11\nlea r9, [rdi+rsi-4]\nadd rsi, r10\nlea r10, [r10+rax*4]\nmovsxd rax, ebx\nshl rax, 2\nlea r11, [rdi+rax-4]\nlea rdi, [rdi+rax-8]\nlea eax, [r8-2]\nshl rax, 2\nsub rdi, rax\njmp short loc_13E9\nloc_13E0:\nadd rsi, 4\ncmp rsi, r10\njz short loc_1430\nloc_13E9:\nmov eax, [rsi]\ncmp eax, [r9]\njge short loc_13E0\nmov [r9], eax\nmov rdx, r11\ntest ebx, ebx\njg short loc_140D\njmp short loc_13E0\nloc_1400:\nmovq qword ptr [rdx], xmm1\nsub rdx, 4\ncmp rdx, rdi\njz short loc_13E0\nloc_140D:\nmovq xmm0, qword ptr [rdx]\npshufd xmm2, xmm0, 0E5h\nmovd ecx, xmm0\nmovd eax, xmm2\npshufd xmm1, xmm0, 0E1h\ncmp ecx, eax\njg short loc_1400\nadd rsi, 4\ncmp rsi, r10\njnz short loc_13E9\nloc_1430:\npop rbx\nretn\nloc_1432:\nmov edx, r8d\nxor eax, eax\nshr edx, 2\nshl rdx, 4\nxchg ax, ax\nloc_1440:\nmovdqu xmm3, xmmword ptr [r10+rax]\nmovups xmmword ptr [rdi+rax], xmm3\nadd rax, 10h\ncmp rax, rdx\njnz short loc_1440\nmov eax, r8d\nand eax, 0FFFFFFFCh\ntest r8b, 3\njz loc_1356\nmov ecx, eax\nmov esi, [r10+rcx*4]\nlea rdx, ds:0[rcx*4]\nmov [rdi+rcx*4], esi\nlea ecx, [rax+1]\ncmp r8d, ecx\njle loc_1356\nmov ecx, [r10+rdx+4]\nadd eax, 2\nmov [rdi+rdx+4], ecx\ncmp r8d, eax\njle loc_1356\nmov eax, [r10+rdx+8]\nmov [rdi+rdx+8], eax\njmp loc_1356", + "ida_strip_pseudo": "void __fastcall sub_1300(__int64 a1, int a2, int a3, int *a4)\n{\n __int64 i; // rax\n int *v9; // rsi\n __int64 v10; // r9\n __int64 v11; // rax\n int v12; // edx\n int v13; // ecx\n __int64 v14; // rsi\n int *v15; // r9\n int *v16; // rsi\n int *v17; // r10\n __int64 v18; // rax\n __int64 v19; // r11\n __int64 v20; // rdi\n __m128i *v21; // rdx\n __m128i v22; // xmm0\n unsigned __int64 v23; // xmm1_8\n __int64 v24; // rax\n unsigned int v25; // eax\n __int64 v26; // rdx\n\n if ( a3 > 0 )\n {\n if ( (unsigned int)(a3 - 1) > 2 && (unsigned __int64)a4 - a1 - 4 > 8 )\n {\n v24 = 0LL;\n do\n {\n *(__m128i *)&a4[v24] = _mm_loadu_si128((const __m128i *)(a1 + v24 * 4));\n v24 += 4LL;\n }\n while ( v24 != 4LL * ((unsigned int)a3 >> 2) );\n v25 = a3 & 0xFFFFFFFC;\n if ( (a3 & 3) != 0 )\n {\n v26 = v25;\n a4[v26] = *(_DWORD *)(a1 + v26 * 4);\n if ( a3 > (int)(v25 + 1) )\n {\n a4[v26 + 1] = *(_DWORD *)(a1 + v26 * 4 + 4);\n if ( a3 > (int)(v25 + 2) )\n a4[v26 + 2] = *(_DWORD *)(a1 + v26 * 4 + 8);\n }\n }\n }\n else\n {\n for ( i = 0LL; i != a3; ++i )\n a4[i] = *(_DWORD *)(a1 + i * 4);\n if ( a3 == 1 )\n goto LABEL_13;\n }\n v9 = a4;\n v10 = 1LL;\n do\n {\n v11 = v10;\n do\n {\n v12 = *v9;\n v13 = a4[v11];\n if ( *v9 > v13 )\n {\n *v9 = v13;\n a4[v11] = v12;\n }\n ++v11;\n }\n while ( a3 > (int)v11 );\n ++v10;\n ++v9;\n }\n while ( v10 != a3 );\n }\nLABEL_13:\n if ( a3 < a2 )\n {\n v14 = a3;\n v15 = &a4[v14 - 1];\n v16 = (int *)(a1 + v14 * 4);\n v17 = (int *)(a1 + 4 * ((unsigned int)(a2 - a3) + (__int64)a3));\n v18 = a3 - 1;\n v19 = (__int64)&a4[v18 - 1];\n v20 = (__int64)&a4[v18 - 2 - (unsigned int)(a3 - 2)];\n do\n {\n while ( 1 )\n {\n if ( *v16 < *v15 )\n {\n *v15 = *v16;\n v21 = (__m128i *)v19;\n if ( a3 - 1 > 0 )\n break;\n }\nLABEL_15:\n if ( ++v16 == v17 )\n return;\n }\n while ( 1 )\n {\n v22 = _mm_loadl_epi64(v21);\n v23 = _mm_shuffle_epi32(v22, 225).m128i_u64[0];\n if ( _mm_cvtsi128_si32(v22) <= _mm_cvtsi128_si32(_mm_shuffle_epi32(v22, 229)) )\n break;\n v21->m128i_i64[0] = v23;\n v21 = (__m128i *)((char *)v21 - 4);\n if ( v21 == (__m128i *)v20 )\n goto LABEL_15;\n }\n ++v16;\n }\n while ( v16 != v17 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1300(long long a1, int a2, int a3, int *a4) {\n long long i;\n int *v9;\n long long v10;\n long long v11;\n int v12;\n int v13;\n long long v14;\n int *v15;\n int *v16;\n int *v17;\n long long v18;\n long long v19;\n long long v20;\n __m128i *v21;\n __m128i v22;\n unsigned long long v23;\n long long v24;\n unsigned int v25;\n long long v26;\n if (a3 > 0) {\n if ((unsigned int)(a3 - 1) > 2 && (unsigned long long)a4 - a1 - 4 > 8) {\n v24 = 0LL;\n do {\n *(__m128i *)&a4[v24] = _mm_loadu_si128((const __m128i *)(a1 + v24 * 4));\n v24 += 4LL;\n } while (v24 != 4LL * ((unsigned int)a3 >> 2));\n v25 = a3 & 4294967292;\n if ((a3 & 3) != 0) {\n v26 = v25;\n a4[v26] = *(uint32_t *)(a1 + v26 * 4);\n if (a3 > (int)(v25 + 1)) {\n a4[v26 + 1] = *(uint32_t *)(a1 + v26 * 4 + 4);\n if (a3 > (int)(v25 + 2))\n a4[v26 + 2] = *(uint32_t *)(a1 + v26 * 4 + 8);\n }\n }\n } else {\n for (i = 0LL; i != a3; ++i) a4[i] = *(uint32_t *)(a1 + i * 4);\n if (a3 == 1) goto LABEL_13;\n }\n v9 = a4;\n v10 = 1LL;\n do {\n v11 = v10;\n do {\n v12 = *v9;\n v13 = a4[v11];\n if (*v9 > v13) {\n *v9 = v13;\n a4[v11] = v12;\n }\n ++v11;\n } while (a3 > (int)v11);\n ++v10;\n ++v9;\n } while (v10 != a3);\n }\nLABEL_13:\n if (a3 < a2) {\n v14 = a3;\n v15 = &a4[v14 - 1];\n v16 = (int *)(a1 + v14 * 4);\n v17 = (int *)(a1 + 4 * ((unsigned int)(a2 - a3) + (long long)a3));\n v18 = a3 - 1;\n v19 = (long long)&a4[v18 - 1];\n v20 = (long long)&a4[v18 - 2 - (unsigned int)(a3 - 2)];\n do {\n while (1) {\n if (*v16 < *v15) {\n *v15 = *v16;\n v21 = (__m128i *)v19;\n if (a3 - 1 > 0) break;\n }\n LABEL_15:\n if (++v16 == v17) return;\n }\n while (1) {\n v22 = _mm_loadl_epi64(v21);\n v23 = _mm_shuffle_epi32(v22, 225).m128i_u64[0];\n if (_mm_cvtsi128_si32(v22) <=\n _mm_cvtsi128_si32(_mm_shuffle_epi32(v22, 229)))\n break;\n v21->m128i_i64[0] = v23;\n v21 = (__m128i *)((char *)v21 - 4);\n if (v21 == (__m128i *)v20) goto LABEL_15;\n }\n ++v16;\n } while (v16 != v17);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2, int a3, int *a4) {\n long long i;\n int *v9;\n long long v10;\n long long v11;\n int v12;\n int v13;\n long long v14;\n int *v15;\n int *v16;\n int *v17;\n long long v18;\n long long v19;\n long long v20;\n __m128i *v21;\n __m128i v22;\n unsigned long long v23;\n long long v24;\n unsigned int v25;\n long long v26;\n if (a3 > 0) {\n if ((unsigned int)(a3 - 1) > 2 && (unsigned long long)a4 - a1 - 4 > 8) {\n v24 = 0LL;\n do {\n *(__m128i *)&a4[v24] = _mm_loadu_si128((const __m128i *)(a1 + v24 * 4));\n v24 += 4LL;\n } while (v24 != 4LL * ((unsigned int)a3 >> 2));\n v25 = a3 & 4294967292;\n if ((a3 & 3) != 0) {\n v26 = v25;\n a4[v26] = *(uint32_t *)(a1 + v26 * 4);\n if (a3 > (int)(v25 + 1)) {\n a4[v26 + 1] = *(uint32_t *)(a1 + v26 * 4 + 4);\n if (a3 > (int)(v25 + 2))\n a4[v26 + 2] = *(uint32_t *)(a1 + v26 * 4 + 8);\n }\n }\n } else {\n for (i = 0LL; i != a3; ++i) a4[i] = *(uint32_t *)(a1 + i * 4);\n if (a3 == 1) goto LABEL_13;\n }\n v9 = a4;\n v10 = 1LL;\n do {\n v11 = v10;\n do {\n v12 = *v9;\n v13 = a4[v11];\n if (*v9 > v13) {\n *v9 = v13;\n a4[v11] = v12;\n }\n ++v11;\n } while (a3 > (int)v11);\n ++v10;\n ++v9;\n } while (v10 != a3);\n }\nLABEL_13:\n if (a3 < a2) {\n v14 = a3;\n v15 = &a4[v14 - 1];\n v16 = (int *)(a1 + v14 * 4);\n v17 = (int *)(a1 + 4 * ((unsigned int)(a2 - a3) + (long long)a3));\n v18 = a3 - 1;\n v19 = (long long)&a4[v18 - 1];\n v20 = (long long)&a4[v18 - 2 - (unsigned int)(a3 - 2)];\n do {\n while (1) {\n if (*v16 < *v15) {\n *v15 = *v16;\n v21 = (__m128i *)v19;\n if (a3 - 1 > 0) break;\n }\n LABEL_15:\n if (++v16 == v17) return;\n }\n while (1) {\n v22 = _mm_loadl_epi64(v21);\n v23 = _mm_shuffle_epi32(v22, 225).m128i_u64[0];\n if (_mm_cvtsi128_si32(v22) <=\n _mm_cvtsi128_si32(_mm_shuffle_epi32(v22, 229)))\n break;\n v21->m128i_i64[0] = v23;\n v21 = (__m128i *)((char *)v21 - 4);\n if (v21 == (__m128i *)v20) goto LABEL_15;\n }\n ++v16;\n } while (v16 != v17);\n }\n}" + }, + { + "index": 11, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char *func0(const char *str, char ch) {\n int len = strlen(str);\n int first = -1, last = -1;\n for (int i = 0; i < len; i++) {\n if (str[i] == ch) {\n if (first == -1) {\n first = i;\n }\n last = i;\n }\n }\n if (first != -1 && last != -1 && first != last) {\n char *new_str = (char *)malloc(len - 2 + 1);\n int new_index = 0;\n for (int i = 0; i < first; i++) {\n new_str[new_index++] = str[i];\n }\n for (int i = first + 1; i < last; i++) {\n new_str[new_index++] = str[i];\n }\n for (int i = last + 1; i < len; i++) {\n new_str[new_index++] = str[i];\n }\n new_str[new_index] = '\\0';\n return new_str;\n }\n char *new_str = (char *)malloc(len + 1);\n strcpy(new_str, str);\n return new_str;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"hello\",'l'), \"heo\") == 0);\n\n assert(strcmp(func0(\"abcda\",'a'), \"bcd\") == 0);\n\n assert(strcmp(func0(\"PHP\",'P'), \"H\") == 0);\n\n assert(strcmp(func0(\"hellolloll\",'l'), \"helollol\") == 0);\n\n assert(strcmp(func0(\"\",'l'), \"\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x40,%rsp\nmov %rdi,-0x38(%rbp)\nmov %esi,%eax\nmov %al,-0x3c(%rbp)\nmov -0x38(%rbp),%rax\nmov %rax,%rdi\ncallq 10a0 \nmov %eax,-0x14(%rbp)\nmovl $0xffffffff,-0x30(%rbp)\nmovl $0xffffffff,-0x2c(%rbp)\nmovl $0x0,-0x28(%rbp)\njmp 122f \nmov -0x28(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp %al,-0x3c(%rbp)\njne 122b \ncmpl $0xffffffff,-0x30(%rbp)\njne 1225 \nmov -0x28(%rbp),%eax\nmov %eax,-0x30(%rbp)\nmov -0x28(%rbp),%eax\nmov %eax,-0x2c(%rbp)\naddl $0x1,-0x28(%rbp)\nmov -0x28(%rbp),%eax\ncmp -0x14(%rbp),%eax\njl 1204 \ncmpl $0xffffffff,-0x30(%rbp)\nje 133d \ncmpl $0xffffffff,-0x2c(%rbp)\nje 133d \nmov -0x30(%rbp),%eax\ncmp -0x2c(%rbp),%eax\nje 133d \nmov -0x14(%rbp),%eax\nsub $0x1,%eax\ncltq\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,-0x10(%rbp)\nmovl $0x0,-0x24(%rbp)\nmovl $0x0,-0x20(%rbp)\njmp 12a5 \nmov -0x20(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x38(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x24(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x24(%rbp)\nmovslq %eax,%rdx\nmov -0x10(%rbp),%rax\nadd %rax,%rdx\nmovzbl (%rcx),%eax\nmov %al,(%rdx)\naddl $0x1,-0x20(%rbp)\nmov -0x20(%rbp),%eax\ncmp -0x30(%rbp),%eax\njl 127b \nmov -0x30(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x1c(%rbp)\njmp 12e2 \nmov -0x1c(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x38(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x24(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x24(%rbp)\nmovslq %eax,%rdx\nmov -0x10(%rbp),%rax\nadd %rax,%rdx\nmovzbl (%rcx),%eax\nmov %al,(%rdx)\naddl $0x1,-0x1c(%rbp)\nmov -0x1c(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 12b8 \nmov -0x2c(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x18(%rbp)\njmp 131f \nmov -0x18(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x38(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x24(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x24(%rbp)\nmovslq %eax,%rdx\nmov -0x10(%rbp),%rax\nadd %rax,%rdx\nmovzbl (%rcx),%eax\nmov %al,(%rdx)\naddl $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%eax\ncmp -0x14(%rbp),%eax\njl 12f5 \nmov -0x24(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x10(%rbp),%rax\nadd %rdx,%rax\nmovb $0x0,(%rax)\nmov -0x10(%rbp),%rax\njmp 1368 \nmov -0x14(%rbp),%eax\nadd $0x1,%eax\ncltq\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,-0x8(%rbp)\nmov -0x38(%rbp),%rdx\nmov -0x8(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1090 \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+s], rdi\nmov eax, esi\nmov [rbp+var_3C], al\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_14], eax\nmov [rbp+var_30], 0FFFFFFFFh\nmov [rbp+var_2C], 0FFFFFFFFh\nmov [rbp+var_28], 0\njmp short loc_122F\nloc_1204:\nmov eax, [rbp+var_28]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp [rbp+var_3C], al\njnz short loc_122B\ncmp [rbp+var_30], 0FFFFFFFFh\njnz short loc_1225\nmov eax, [rbp+var_28]\nmov [rbp+var_30], eax\nloc_1225:\nmov eax, [rbp+var_28]\nmov [rbp+var_2C], eax\nloc_122B:\nadd [rbp+var_28], 1\nloc_122F:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_14]\njl short loc_1204\ncmp [rbp+var_30], 0FFFFFFFFh\njz loc_133D\ncmp [rbp+var_2C], 0FFFFFFFFh\njz loc_133D\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_2C]\njz loc_133D\nmov eax, [rbp+var_14]\nsub eax, 1\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_10], rax\nmov [rbp+var_24], 0\nmov [rbp+var_20], 0\njmp short loc_12A5\nloc_127B:\nmov eax, [rbp+var_20]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_24]\nlea edx, [rax+1]\nmov [rbp+var_24], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_10]\nadd rdx, rax\nmovzx eax, byte ptr [rcx]\nmov [rdx], al\nadd [rbp+var_20], 1\nloc_12A5:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_30]\njl short loc_127B\nmov eax, [rbp+var_30]\nadd eax, 1\nmov [rbp+var_1C], eax\njmp short loc_12E2\nloc_12B8:\nmov eax, [rbp+var_1C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_24]\nlea edx, [rax+1]\nmov [rbp+var_24], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_10]\nadd rdx, rax\nmovzx eax, byte ptr [rcx]\nmov [rdx], al\nadd [rbp+var_1C], 1\nloc_12E2:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_2C]\njl short loc_12B8\nmov eax, [rbp+var_2C]\nadd eax, 1\nmov [rbp+var_18], eax\njmp short loc_131F\nloc_12F5:\nmov eax, [rbp+var_18]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_24]\nlea edx, [rax+1]\nmov [rbp+var_24], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_10]\nadd rdx, rax\nmovzx eax, byte ptr [rcx]\nmov [rdx], al\nadd [rbp+var_18], 1\nloc_131F:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_14]\njl short loc_12F5\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, [rbp+var_10]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+var_10]\njmp short locret_1368\nloc_133D:\nmov eax, [rbp+var_14]\nadd eax, 1\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+dest], rax\nmov rdx, [rbp+s]\nmov rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\nmov rax, [rbp+dest]\nlocret_1368:\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(const char *a1, char a2)\n{\n int v2; // eax\n int v3; // eax\n int v4; // eax\n int v6; // [rsp+10h] [rbp-30h]\n int v7; // [rsp+14h] [rbp-2Ch]\n int i; // [rsp+18h] [rbp-28h]\n int v9; // [rsp+1Ch] [rbp-24h]\n int j; // [rsp+20h] [rbp-20h]\n int k; // [rsp+24h] [rbp-1Ch]\n int m; // [rsp+28h] [rbp-18h]\n int v13; // [rsp+2Ch] [rbp-14h]\n _BYTE *v14; // [rsp+30h] [rbp-10h]\n char *dest; // [rsp+38h] [rbp-8h]\n\n v13 = strlen(a1);\n v6 = -1;\n v7 = -1;\n for ( i = 0; i < v13; ++i )\n {\n if ( a2 == a1[i] )\n {\n if ( v6 == -1 )\n v6 = i;\n v7 = i;\n }\n }\n if ( v6 == -1 || v7 == -1 || v6 == v7 )\n {\n dest = (char *)malloc(v13 + 1);\n strcpy(dest, a1);\n return dest;\n }\n else\n {\n v14 = malloc(v13 - 1);\n v9 = 0;\n for ( j = 0; j < v6; ++j )\n {\n v2 = v9++;\n v14[v2] = a1[j];\n }\n for ( k = v6 + 1; k < v7; ++k )\n {\n v3 = v9++;\n v14[v3] = a1[k];\n }\n for ( m = v7 + 1; m < v13; ++m )\n {\n v4 = v9++;\n v14[v4] = a1[m];\n }\n v14[v9] = 0;\n return v14;\n }\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+s], rdi\nmov eax, esi\nmov [rbp+var_3C], al\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_14], eax\nmov [rbp+var_30], 0FFFFFFFFh\nmov [rbp+var_2C], 0FFFFFFFFh\nmov [rbp+var_28], 0\njmp short loc_122F\nloc_1204:\nmov eax, [rbp+var_28]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp [rbp+var_3C], al\njnz short loc_122B\ncmp [rbp+var_30], 0FFFFFFFFh\njnz short loc_1225\nmov eax, [rbp+var_28]\nmov [rbp+var_30], eax\nloc_1225:\nmov eax, [rbp+var_28]\nmov [rbp+var_2C], eax\nloc_122B:\nadd [rbp+var_28], 1\nloc_122F:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_14]\njl short loc_1204\ncmp [rbp+var_30], 0FFFFFFFFh\njz loc_133D\ncmp [rbp+var_2C], 0FFFFFFFFh\njz loc_133D\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_2C]\njz loc_133D\nmov eax, [rbp+var_14]\nsub eax, 1\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_10], rax\nmov [rbp+var_24], 0\nmov [rbp+var_20], 0\njmp short loc_12A5\nloc_127B:\nmov eax, [rbp+var_20]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_24]\nlea edx, [rax+1]\nmov [rbp+var_24], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_10]\nadd rdx, rax\nmovzx eax, byte ptr [rcx]\nmov [rdx], al\nadd [rbp+var_20], 1\nloc_12A5:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_30]\njl short loc_127B\nmov eax, [rbp+var_30]\nadd eax, 1\nmov [rbp+var_1C], eax\njmp short loc_12E2\nloc_12B8:\nmov eax, [rbp+var_1C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_24]\nlea edx, [rax+1]\nmov [rbp+var_24], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_10]\nadd rdx, rax\nmovzx eax, byte ptr [rcx]\nmov [rdx], al\nadd [rbp+var_1C], 1\nloc_12E2:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_2C]\njl short loc_12B8\nmov eax, [rbp+var_2C]\nadd eax, 1\nmov [rbp+var_18], eax\njmp short loc_131F\nloc_12F5:\nmov eax, [rbp+var_18]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_24]\nlea edx, [rax+1]\nmov [rbp+var_24], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_10]\nadd rdx, rax\nmovzx eax, byte ptr [rcx]\nmov [rdx], al\nadd [rbp+var_18], 1\nloc_131F:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_14]\njl short loc_12F5\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, [rbp+var_10]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+var_10]\njmp short locret_1368\nloc_133D:\nmov eax, [rbp+var_14]\nadd eax, 1\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+dest], rax\nmov rdx, [rbp+s]\nmov rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\nmov rax, [rbp+dest]\nlocret_1368:\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11C9(const char *a1, char a2)\n{\n int v2; // eax\n int v3; // eax\n int v4; // eax\n int v6; // [rsp+10h] [rbp-30h]\n int v7; // [rsp+14h] [rbp-2Ch]\n int i; // [rsp+18h] [rbp-28h]\n int v9; // [rsp+1Ch] [rbp-24h]\n int j; // [rsp+20h] [rbp-20h]\n int k; // [rsp+24h] [rbp-1Ch]\n int m; // [rsp+28h] [rbp-18h]\n int v13; // [rsp+2Ch] [rbp-14h]\n _BYTE *v14; // [rsp+30h] [rbp-10h]\n char *dest; // [rsp+38h] [rbp-8h]\n\n v13 = strlen(a1);\n v6 = -1;\n v7 = -1;\n for ( i = 0; i < v13; ++i )\n {\n if ( a2 == a1[i] )\n {\n if ( v6 == -1 )\n v6 = i;\n v7 = i;\n }\n }\n if ( v6 == -1 || v7 == -1 || v6 == v7 )\n {\n dest = (char *)malloc(v13 + 1);\n strcpy(dest, a1);\n return dest;\n }\n else\n {\n v14 = malloc(v13 - 1);\n v9 = 0;\n for ( j = 0; j < v6; ++j )\n {\n v2 = v9++;\n v14[v2] = a1[j];\n }\n for ( k = v6 + 1; k < v7; ++k )\n {\n v3 = v9++;\n v14[v3] = a1[k];\n }\n for ( m = v7 + 1; m < v13; ++m )\n {\n v4 = v9++;\n v14[v4] = a1[m];\n }\n v14[v9] = 0;\n return v14;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11C9(const char *a1, char a2) {\n int v2;\n int v3;\n int v4;\n int v6;\n int v7;\n int i;\n int v9;\n int j;\n int k;\n int m;\n int v13;\n uint8_t *v14;\n char *dest;\n v13 = strlen(a1);\n v6 = -1;\n v7 = -1;\n for (i = 0; i < v13; ++i) {\n if (a2 == a1[i]) {\n if (v6 == -1) v6 = i;\n v7 = i;\n }\n }\n if (v6 == -1 || v7 == -1 || v6 == v7) {\n dest = (char *)malloc(v13 + 1);\n strcpy(dest, a1);\n return dest;\n } else {\n v14 = malloc(v13 - 1);\n v9 = 0;\n for (j = 0; j < v6; ++j) {\n v2 = v9++;\n v14[v2] = a1[j];\n }\n for (k = v6 + 1; k < v7; ++k) {\n v3 = v9++;\n v14[v3] = a1[k];\n }\n for (m = v7 + 1; m < v13; ++m) {\n v4 = v9++;\n v14[v4] = a1[m];\n }\n v14[v9] = 0;\n return v14;\n }\n}", + "ida_pseudo_norm": "char *func0(const char *a1, char a2) {\n int v2;\n int v3;\n int v4;\n int v6;\n int v7;\n int i;\n int v9;\n int j;\n int k;\n int m;\n int v13;\n uint8_t *v14;\n char *dest;\n v13 = strlen(a1);\n v6 = -1;\n v7 = -1;\n for (i = 0; i < v13; ++i) {\n if (a2 == a1[i]) {\n if (v6 == -1) v6 = i;\n v7 = i;\n }\n }\n if (v6 == -1 || v7 == -1 || v6 == v7) {\n dest = (char *)malloc(v13 + 1);\n strcpy(dest, a1);\n return dest;\n } else {\n v14 = malloc(v13 - 1);\n v9 = 0;\n for (j = 0; j < v6; ++j) {\n v2 = v9++;\n v14[v2] = a1[j];\n }\n for (k = v6 + 1; k < v7; ++k) {\n v3 = v9++;\n v14[v3] = a1[k];\n }\n for (m = v7 + 1; m < v13; ++m) {\n v4 = v9++;\n v14[v4] = a1[m];\n }\n v14[v9] = 0;\n return v14;\n }\n}" + }, + { + "index": 11, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char *func0(const char *str, char ch) {\n int len = strlen(str);\n int first = -1, last = -1;\n for (int i = 0; i < len; i++) {\n if (str[i] == ch) {\n if (first == -1) {\n first = i;\n }\n last = i;\n }\n }\n if (first != -1 && last != -1 && first != last) {\n char *new_str = (char *)malloc(len - 2 + 1);\n int new_index = 0;\n for (int i = 0; i < first; i++) {\n new_str[new_index++] = str[i];\n }\n for (int i = first + 1; i < last; i++) {\n new_str[new_index++] = str[i];\n }\n for (int i = last + 1; i < len; i++) {\n new_str[new_index++] = str[i];\n }\n new_str[new_index] = '\\0';\n return new_str;\n }\n char *new_str = (char *)malloc(len + 1);\n strcpy(new_str, str);\n return new_str;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"hello\",'l'), \"heo\") == 0);\n\n assert(strcmp(func0(\"abcda\",'a'), \"bcd\") == 0);\n\n assert(strcmp(func0(\"PHP\",'P'), \"H\") == 0);\n\n assert(strcmp(func0(\"hellolloll\",'l'), \"helollol\") == 0);\n\n assert(strcmp(func0(\"\",'l'), \"\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov %rdi,%rbx\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nlea -0x1(%rcx),%rbp\ntest %ebp,%ebp\njle 120d \nmov %ebp,%r15d\nlea -0x1(%rbp),%eax\nmov %eax,0xc(%rsp)\nmov %eax,%ecx\nmov $0x0,%eax\nmov $0xffffffff,%r12d\nmov $0xffffffff,%r13d\njmp 11e2 \nlea 0x1(%rax),%rdx\ncmp %rcx,%rax\nje 11f6 \nmov %rdx,%rax\ncmp %sil,(%rbx,%rax,1)\njne 11d6 \nmov %eax,%r12d\ncmp $0xffffffff,%r13d\njne 11d6 \nmov %eax,%r13d\njmp 11d6 \ncmp $0xffffffff,%r13d\nsetne %dl\ncmp $0xffffffff,%r12d\nsetne %al\ntest %al,%dl\nje 120d \ncmp %r12d,%r13d\njne 1238 \nlea 0x1(%rbp),%edi\nmovslq %edi,%rdi\ncallq 1090 \nmov %rax,%r14\nmov %rbx,%rsi\nmov %rax,%rdi\ncallq 1070 \nmov %r14,%rax\nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nlea -0x1(%rbp),%edi\nmovslq %edi,%rdi\ncallq 1090 \nmov %rax,%r14\ntest %r13d,%r13d\njle 12df \nlea -0x1(%r13),%ecx\nmov $0x0,%eax\nmovzbl (%rbx,%rax,1),%edx\nmov %dl,(%r14,%rax,1)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rcx,%rdx\njne 1258 \nmov %r13d,%esi\nlea 0x1(%r13),%eax\ncmp %eax,%r12d\njle 12a1 \ncltq\nmovslq %esi,%rcx\nmovslq %r13d,%rdx\nsub %rdx,%rcx\nadd %r14,%rcx\nmovzbl (%rbx,%rax,1),%edx\nmov %dl,-0x1(%rcx,%rax,1)\nadd $0x1,%rax\ncmp %eax,%r12d\njg 1286 \nlea -0x1(%r12),%eax\nsub %r13d,%eax\nadd %eax,%esi\nlea 0x1(%r12),%eax\ncmp %eax,%ebp\njle 12d2 \ncltq\nmovslq %esi,%rcx\nmovslq %r12d,%rdx\nsub %rdx,%rcx\nadd %r14,%rcx\nmovzbl (%rbx,%rax,1),%edx\nmov %dl,-0x1(%rcx,%rax,1)\nadd $0x1,%rax\ncmp %eax,%r15d\njg 12b8 \nmov 0xc(%rsp),%eax\nsub %r12d,%eax\nadd %eax,%esi\nmovslq %esi,%rsi\nmovb $0x0,(%r14,%rsi,1)\njmpq 1226 \nmov $0x0,%esi\njmp 126f \n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov rbx, rdi\nmov r12d, esi\ncall _strlen\nmov r13, rax\ntest eax, eax\njle short loc_123E\nmov r15d, eax\nlea eax, [rax-1]\nmov [rsp+48h+var_3C], eax\nmov ecx, eax\nmov eax, 0\nmov r14d, 0FFFFFFFFh\nmov ebp, 0FFFFFFFFh\njmp short loc_1217\nloc_120B:\nlea rdx, [rax+1]\ncmp rax, rcx\njz short loc_1228\nmov rax, rdx\nloc_1217:\ncmp [rbx+rax], r12b\njnz short loc_120B\nmov r14d, eax\ncmp ebp, 0FFFFFFFFh\ncmovz ebp, eax\njmp short loc_120B\nloc_1228:\ncmp ebp, 0FFFFFFFFh\nsetnz dl\ncmp r14d, 0FFFFFFFFh\nsetnz al\ntest dl, al\njz short loc_123E\ncmp ebp, r14d\njnz short loc_1270\nloc_123E:\nadd r13d, 1\nmovsxd r13, r13d\nmov rdi, r13; size\ncall _malloc\nmov r12, rax\nmov rdx, r13\nmov rsi, rbx\nmov rdi, rax\ncall ___strcpy_chk\nloc_125E:\nmov rax, r12\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1270:\nlea edi, [r13-1]\nmovsxd rdi, edi; size\ncall _malloc\nmov r12, rax\ntest ebp, ebp\njle loc_130F\nmovsxd rcx, ebp\nmov eax, 0\nloc_128F:\nmovzx edx, byte ptr [rbx+rax]\nmov [r12+rax], dl\nadd rax, 1\ncmp rax, rcx\njnz short loc_128F\nmov esi, ebp\nloc_12A2:\nlea eax, [rbp+1]\ncmp r14d, eax\njle short loc_12D1\ncdqe\nmovsxd rcx, esi\nmovsxd rdx, ebp\nsub rcx, rdx\nadd rcx, r12\nloc_12B8:\nmovzx edx, byte ptr [rbx+rax]\nmov [rcx+rax-1], dl\nadd rax, 1\ncmp r14d, eax\njg short loc_12B8\nlea eax, [r14-1]\nsub eax, ebp\nadd esi, eax\nloc_12D1:\nlea eax, [r14+1]\ncmp r13d, eax\njle short loc_1302\ncdqe\nmovsxd rcx, esi\nmovsxd rdx, r14d\nsub rcx, rdx\nadd rcx, r12\nloc_12E8:\nmovzx edx, byte ptr [rbx+rax]\nmov [rcx+rax-1], dl\nadd rax, 1\ncmp r15d, eax\njg short loc_12E8\nmov eax, [rsp+48h+var_3C]\nsub eax, r14d\nadd esi, eax\nloc_1302:\nmovsxd rsi, esi\nmov byte ptr [r12+rsi], 0\njmp loc_125E\nloc_130F:\nmov esi, 0\njmp short loc_12A2", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1, char a2)\n{\n int v2; // eax\n int v3; // r13d\n int v4; // r15d\n __int64 v5; // rcx\n __int64 v6; // rax\n int v7; // r14d\n int v8; // ebp\n size_t v9; // r13\n _BYTE *v10; // r12\n __int64 i; // rax\n int v13; // esi\n __int64 v14; // rax\n __int64 v15; // rax\n int v16; // [rsp+Ch] [rbp-3Ch]\n\n v2 = strlen(a1);\n v3 = v2;\n if ( v2 <= 0 )\n goto LABEL_11;\n v4 = v2;\n v16 = v2 - 1;\n v5 = (unsigned int)(v2 - 1);\n v6 = 0LL;\n v7 = -1;\n v8 = -1;\n while ( 1 )\n {\n if ( a1[v6] == a2 )\n {\n v7 = v6;\n if ( v8 == -1 )\n v8 = v6;\n }\n if ( v6 == v5 )\n break;\n ++v6;\n }\n if ( v7 != -1 && v8 != -1 && v8 != v7 )\n {\n v10 = malloc(v3 - 1);\n if ( v8 <= 0 )\n {\n v13 = 0;\n }\n else\n {\n for ( i = 0LL; i != v8; ++i )\n v10[i] = a1[i];\n v13 = v8;\n }\n LODWORD(v14) = v8 + 1;\n if ( v7 > v8 + 1 )\n {\n v14 = (int)v14;\n do\n {\n v10[v13 - (__int64)v8 - 1 + v14] = a1[v14];\n ++v14;\n }\n while ( v7 > (int)v14 );\n v13 += v7 - 1 - v8;\n }\n LODWORD(v15) = v7 + 1;\n if ( v3 > v7 + 1 )\n {\n v15 = (int)v15;\n do\n {\n v10[v13 - (__int64)v7 - 1 + v15] = a1[v15];\n ++v15;\n }\n while ( v4 > (int)v15 );\n v13 += v16 - v7;\n }\n v10[v13] = 0;\n }\n else\n {\nLABEL_11:\n v9 = v3 + 1;\n v10 = malloc(v9);\n __strcpy_chk(v10, a1, v9);\n }\n return v10;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov rbx, rdi\nmov r12d, esi\ncall _strlen\nmov r13, rax\ntest eax, eax\njle short loc_123E\nmov r15d, eax\nlea eax, [rax-1]\nmov [rsp+48h+var_3C], eax\nmov ecx, eax\nmov eax, 0\nmov r14d, 0FFFFFFFFh\nmov ebp, 0FFFFFFFFh\njmp short loc_1217\nloc_120B:\nlea rdx, [rax+1]\ncmp rax, rcx\njz short loc_1228\nmov rax, rdx\nloc_1217:\ncmp [rbx+rax], r12b\njnz short loc_120B\nmov r14d, eax\ncmp ebp, 0FFFFFFFFh\ncmovz ebp, eax\njmp short loc_120B\nloc_1228:\ncmp ebp, 0FFFFFFFFh\nsetnz dl\ncmp r14d, 0FFFFFFFFh\nsetnz al\ntest dl, al\njz short loc_123E\ncmp ebp, r14d\njnz short loc_1270\nloc_123E:\nadd r13d, 1\nmovsxd r13, r13d\nmov rdi, r13; size\ncall _malloc\nmov r12, rax\nmov rdx, r13\nmov rsi, rbx\nmov rdi, rax\ncall ___strcpy_chk\nloc_125E:\nmov rax, r12\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1270:\nlea edi, [r13-1]\nmovsxd rdi, edi; size\ncall _malloc\nmov r12, rax\ntest ebp, ebp\njle loc_130F\nmovsxd rcx, ebp\nmov eax, 0\nloc_128F:\nmovzx edx, byte ptr [rbx+rax]\nmov [r12+rax], dl\nadd rax, 1\ncmp rax, rcx\njnz short loc_128F\nmov esi, ebp\nloc_12A2:\nlea eax, [rbp+1]\ncmp r14d, eax\njle short loc_12D1\ncdqe\nmovsxd rcx, esi\nmovsxd rdx, ebp\nsub rcx, rdx\nadd rcx, r12\nloc_12B8:\nmovzx edx, byte ptr [rbx+rax]\nmov [rcx+rax-1], dl\nadd rax, 1\ncmp r14d, eax\njg short loc_12B8\nlea eax, [r14-1]\nsub eax, ebp\nadd esi, eax\nloc_12D1:\nlea eax, [r14+1]\ncmp r13d, eax\njle short loc_1302\ncdqe\nmovsxd rcx, esi\nmovsxd rdx, r14d\nsub rcx, rdx\nadd rcx, r12\nloc_12E8:\nmovzx edx, byte ptr [rbx+rax]\nmov [rcx+rax-1], dl\nadd rax, 1\ncmp r15d, eax\njg short loc_12E8\nmov eax, [rsp+48h+var_3C]\nsub eax, r14d\nadd esi, eax\nloc_1302:\nmovsxd rsi, esi\nmov byte ptr [r12+rsi], 0\njmp loc_125E\nloc_130F:\nmov esi, 0\njmp short loc_12A2", + "ida_strip_pseudo": "_BYTE *__fastcall sub_11C9(const char *a1, char a2)\n{\n int v2; // eax\n int v3; // r13d\n int v4; // r15d\n __int64 v5; // rcx\n __int64 v6; // rax\n int v7; // r14d\n int v8; // ebp\n size_t v9; // r13\n _BYTE *v10; // r12\n __int64 i; // rax\n int v13; // esi\n __int64 v14; // rax\n __int64 v15; // rax\n int v16; // [rsp+Ch] [rbp-3Ch]\n\n v2 = strlen(a1);\n v3 = v2;\n if ( v2 <= 0 )\n goto LABEL_11;\n v4 = v2;\n v16 = v2 - 1;\n v5 = (unsigned int)(v2 - 1);\n v6 = 0LL;\n v7 = -1;\n v8 = -1;\n while ( 1 )\n {\n if ( a1[v6] == a2 )\n {\n v7 = v6;\n if ( v8 == -1 )\n v8 = v6;\n }\n if ( v6 == v5 )\n break;\n ++v6;\n }\n if ( v7 != -1 && v8 != -1 && v8 != v7 )\n {\n v10 = malloc(v3 - 1);\n if ( v8 <= 0 )\n {\n v13 = 0;\n }\n else\n {\n for ( i = 0LL; i != v8; ++i )\n v10[i] = a1[i];\n v13 = v8;\n }\n LODWORD(v14) = v8 + 1;\n if ( v7 > v8 + 1 )\n {\n v14 = (int)v14;\n do\n {\n v10[v13 - (__int64)v8 - 1 + v14] = a1[v14];\n ++v14;\n }\n while ( v7 > (int)v14 );\n v13 += v7 - 1 - v8;\n }\n LODWORD(v15) = v7 + 1;\n if ( v3 > v7 + 1 )\n {\n v15 = (int)v15;\n do\n {\n v10[v13 - (__int64)v7 - 1 + v15] = a1[v15];\n ++v15;\n }\n while ( v4 > (int)v15 );\n v13 += v16 - v7;\n }\n v10[v13] = 0;\n }\n else\n {\nLABEL_11:\n v9 = v3 + 1;\n v10 = malloc(v9);\n __strcpy_chk(v10, a1, v9);\n }\n return v10;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_11C9(const char *a1, char a2) {\n int v2;\n int v3;\n int v4;\n long long v5;\n long long v6;\n int v7;\n int v8;\n unsigned int v9;\n uint8_t *v10;\n long long i;\n int v13;\n long long v14;\n long long v15;\n int v16;\n v2 = strlen(a1);\n v3 = v2;\n if (v2 <= 0) goto LABEL_11;\n v4 = v2;\n v16 = v2 - 1;\n v5 = (unsigned int)(v2 - 1);\n v6 = 0LL;\n v7 = -1;\n v8 = -1;\n while (1) {\n if (a1[v6] == a2) {\n v7 = v6;\n if (v8 == -1) v8 = v6;\n }\n if (v6 == v5) break;\n ++v6;\n }\n if (v7 != -1 && v8 != -1 && v8 != v7) {\n v10 = malloc(v3 - 1);\n if (v8 <= 0) {\n v13 = 0;\n } else {\n for (i = 0LL; i != v8; ++i) v10[i] = a1[i];\n v13 = v8;\n }\n LODWORD(v14) = v8 + 1;\n if (v7 > v8 + 1) {\n v14 = (int)v14;\n do {\n v10[v13 - (long long)v8 - 1 + v14] = a1[v14];\n ++v14;\n } while (v7 > (int)v14);\n v13 += v7 - 1 - v8;\n }\n LODWORD(v15) = v7 + 1;\n if (v3 > v7 + 1) {\n v15 = (int)v15;\n do {\n v10[v13 - (long long)v7 - 1 + v15] = a1[v15];\n ++v15;\n } while (v4 > (int)v15);\n v13 += v16 - v7;\n }\n v10[v13] = 0;\n } else {\n LABEL_11:\n v9 = v3 + 1;\n v10 = malloc(v9);\n __strcpy_chk(v10, a1, v9);\n }\n return v10;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1, char a2) {\n int v2;\n int v3;\n int v4;\n long long v5;\n long long v6;\n int v7;\n int v8;\n unsigned int v9;\n uint8_t *v10;\n long long i;\n int v13;\n long long v14;\n long long v15;\n int v16;\n v2 = strlen(a1);\n v3 = v2;\n if (v2 <= 0) goto LABEL_11;\n v4 = v2;\n v16 = v2 - 1;\n v5 = (unsigned int)(v2 - 1);\n v6 = 0LL;\n v7 = -1;\n v8 = -1;\n while (1) {\n if (a1[v6] == a2) {\n v7 = v6;\n if (v8 == -1) v8 = v6;\n }\n if (v6 == v5) break;\n ++v6;\n }\n if (v7 != -1 && v8 != -1 && v8 != v7) {\n v10 = malloc(v3 - 1);\n if (v8 <= 0) {\n v13 = 0;\n } else {\n for (i = 0LL; i != v8; ++i) v10[i] = a1[i];\n v13 = v8;\n }\n LODWORD(v14) = v8 + 1;\n if (v7 > v8 + 1) {\n v14 = (int)v14;\n do {\n v10[v13 - (long long)v8 - 1 + v14] = a1[v14];\n ++v14;\n } while (v7 > (int)v14);\n v13 += v7 - 1 - v8;\n }\n LODWORD(v15) = v7 + 1;\n if (v3 > v7 + 1) {\n v15 = (int)v15;\n do {\n v10[v13 - (long long)v7 - 1 + v15] = a1[v15];\n ++v15;\n } while (v4 > (int)v15);\n v13 += v16 - v7;\n }\n v10[v13] = 0;\n } else {\n LABEL_11:\n v9 = v3 + 1;\n v10 = malloc(v9);\n __strcpy_chk(v10, a1, v9);\n }\n return v10;\n}" + }, + { + "index": 11, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char *func0(const char *str, char ch) {\n int len = strlen(str);\n int first = -1, last = -1;\n for (int i = 0; i < len; i++) {\n if (str[i] == ch) {\n if (first == -1) {\n first = i;\n }\n last = i;\n }\n }\n if (first != -1 && last != -1 && first != last) {\n char *new_str = (char *)malloc(len - 2 + 1);\n int new_index = 0;\n for (int i = 0; i < first; i++) {\n new_str[new_index++] = str[i];\n }\n for (int i = first + 1; i < last; i++) {\n new_str[new_index++] = str[i];\n }\n for (int i = last + 1; i < len; i++) {\n new_str[new_index++] = str[i];\n }\n new_str[new_index] = '\\0';\n return new_str;\n }\n char *new_str = (char *)malloc(len + 1);\n strcpy(new_str, str);\n return new_str;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"hello\",'l'), \"heo\") == 0);\n\n assert(strcmp(func0(\"abcda\",'a'), \"bcd\") == 0);\n\n assert(strcmp(func0(\"PHP\",'P'), \"H\") == 0);\n\n assert(strcmp(func0(\"hellolloll\",'l'), \"helollol\") == 0);\n\n assert(strcmp(func0(\"\",'l'), \"\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\nmov %esi,%r12d\npush %rbp\nmov %rdi,%rbp\npush %rbx\nsub $0x18,%rsp\ncallq 1080 \nmov %rax,%r13\ntest %eax,%eax\njle 1392 \nlea -0x1(%rax),%esi\nmov %eax,%edx\nmov $0xffffffff,%r14d\nxor %eax,%eax\nmov %rsi,%r15\nmov $0xffffffff,%ebx\njmp 1363 \nnopl 0x0(%rax,%rax,1)\nmov %rcx,%rax\ncmp %r12b,0x0(%rbp,%rax,1)\njne 1373 \ncmp $0xffffffff,%ebx\nmov %eax,%r14d\ncmove %eax,%ebx\nlea 0x1(%rax),%rcx\ncmp %rsi,%rax\njne 1360 \ncmp $0xffffffff,%ebx\nsetne %cl\ncmp $0xffffffff,%r14d\nsetne %al\ntest %al,%cl\nje 1392 \ncmp %r14d,%ebx\njne 13c8 \nlea 0x1(%r13),%edi\nmovslq %edi,%rdi\ncallq 10b0 \nlea 0x1(%r13),%rdx\nmov %rbp,%rsi\nmov %rax,%rdi\ncallq 10a0 \nmov %rax,%r8\nadd $0x18,%rsp\nmov %r8,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw 0x0(%rax,%rax,1)\nmovslq %r15d,%rdi\nmov %edx,0xc(%rsp)\ncallq 10b0 \ntest %ebx,%ebx\nmov 0xc(%rsp),%edx\nmov %rax,%r8\njle 1487 \nlea -0x1(%rbx),%esi\nxor %eax,%eax\nnopl 0x0(%rax,%rax,1)\nmovzbl 0x0(%rbp,%rax,1),%ecx\nmov %cl,(%r8,%rax,1)\nmov %rax,%rcx\nadd $0x1,%rax\ncmp %rcx,%rsi\njne 13f0 \nmovslq %ebx,%rdi\nmov %ebx,%esi\nlea (%r8,%rdi,1),%rcx\nlea 0x1(%rbx),%eax\ncmp %eax,%r14d\njle 1449 \nmovslq %ebx,%rdi\nmovslq %esi,%rcx\ncltq\nsub %rdi,%rcx\nadd %r8,%rcx\nnopl 0x0(%rax)\nmovzbl 0x0(%rbp,%rax,1),%edi\nmov %dil,-0x1(%rcx,%rax,1)\nadd $0x1,%rax\ncmp %eax,%r14d\njg 1428 \nlea -0x1(%r14),%eax\nsub %ebx,%eax\nadd %eax,%esi\nmovslq %esi,%rcx\nadd %r8,%rcx\nlea 0x1(%r14),%eax\ncmp %eax,%r13d\njle 147f \nmovslq %esi,%rcx\nmovslq %r14d,%rdi\ncltq\nsub %rdi,%rcx\nadd %r8,%rcx\nmovzbl 0x0(%rbp,%rax,1),%edi\nmov %dil,-0x1(%rcx,%rax,1)\nadd $0x1,%rax\ncmp %eax,%edx\njg 1460 \nsub %r14d,%r15d\nadd %r15d,%esi\nmovslq %esi,%rsi\nlea (%r8,%rsi,1),%rcx\nmovb $0x0,(%rcx)\njmpq 13b0 \nmov %rax,%rcx\nxor %esi,%esi\njmp 140e \nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12d, esi\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 18h\ncall _strlen\nmov r13, rax\ntest eax, eax\njle short loc_13C1\nlea ecx, [rax-1]\nmov r14d, 0FFFFFFFFh\nxor eax, eax\nmov ebp, 0FFFFFFFFh\nmov r15, rcx\njmp short loc_1393\nloc_1390:\nmov rax, rdx\nloc_1393:\ncmp [rbx+rax], r12b\njnz short loc_13A2\ncmp ebp, 0FFFFFFFFh\nmov r14d, eax\ncmovz ebp, eax\nloc_13A2:\nlea rdx, [rax+1]\ncmp rcx, rax\njnz short loc_1390\ncmp ebp, 0FFFFFFFFh\nsetnz dl\ncmp r14d, 0FFFFFFFFh\nsetnz al\ntest dl, al\njz short loc_13C1\ncmp ebp, r14d\njnz short loc_1400\nloc_13C1:\nlea ebp, [r13+1]\nmovsxd rbp, ebp\nmov rdi, rbp; size\ncall _malloc\nlea rdx, [r13+1]\nmov rcx, rbp\nmov rsi, rbx\nmov rdi, rax\nmov r12, rax\ncall ___memcpy_chk\nloc_13E5:\nadd rsp, 18h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1400:\nmovsxd rdi, r15d; size\ncall _malloc\nmov r12, rax\ntest ebp, ebp\njle loc_14AD\nmov edx, ebp; n\nmov rsi, rbx; src\nmov rdi, rax; dest\ncall _memcpy\nmovsxd rax, ebp\nmov r8d, ebp\nadd rax, r12\nloc_1429:\nlea ecx, [rbp+1]\ncmp ecx, r14d\njge short loc_1466\nlea edx, [r14-2]\nmovsxd rdi, r8d\nmovsxd rcx, ecx\nmov [rsp+48h+var_3C], r8d\nsub edx, ebp\nadd rdi, r12; dest\nlea rsi, [rbx+rcx]; src\nadd rdx, 1; n\ncall _memcpy\nmov r8d, [rsp+48h+var_3C]\nlea eax, [r14-1]\nsub eax, ebp\nadd r8d, eax\nmovsxd rax, r8d\nadd rax, r12\nloc_1466:\nlea ecx, [r14+1]\ncmp r13d, ecx\njle short loc_14A5\nlea edx, [r13-2]\nmovsxd rdi, r8d\nmovsxd rcx, ecx\nmov [rsp+48h+var_3C], r8d\nmov r13d, edx\nadd rdi, r12; dest\nlea rsi, [rbx+rcx]; src\nsub r15d, r14d\nsub r13d, r14d\nlea rdx, [r13+1]; n\ncall _memcpy\nmov r8d, [rsp+48h+var_3C]\nlea eax, [r15+r8]\ncdqe\nadd rax, r12\nloc_14A5:\nmov byte ptr [rax], 0\njmp loc_13E5\nloc_14AD:\nxor r8d, r8d\njmp loc_1429", + "ida_pseudo": "char *__fastcall func0(const char *src, char a2)\n{\n size_t v2; // rax\n size_t v3; // r13\n __int64 v4; // rcx\n int v5; // r14d\n __int64 v6; // rax\n int v7; // ebp\n int v8; // r15d\n char *v9; // r12\n char *v11; // rax\n int v12; // r8d\n int v13; // [rsp+Ch] [rbp-3Ch]\n int v14; // [rsp+Ch] [rbp-3Ch]\n\n v2 = strlen(src);\n v3 = v2;\n if ( (int)v2 <= 0 )\n goto LABEL_10;\n v4 = (unsigned int)(v2 - 1);\n v5 = -1;\n v6 = 0LL;\n v7 = -1;\n v8 = v4;\n while ( 1 )\n {\n if ( src[v6] == a2 )\n {\n v5 = v6;\n if ( v7 == -1 )\n v7 = v6;\n }\n if ( v4 == v6 )\n break;\n ++v6;\n }\n if ( v5 != -1 && v7 != -1 && v7 != v5 )\n {\n v11 = (char *)malloc((int)v4);\n v9 = v11;\n if ( v7 <= 0 )\n {\n v12 = 0;\n }\n else\n {\n memcpy(v11, src, (unsigned int)v7);\n v12 = v7;\n v11 = &v9[v7];\n }\n if ( v7 + 1 < v5 )\n {\n v13 = v12;\n memcpy(&v9[v12], &src[v7 + 1], (unsigned int)(v5 - 2 - v7) + 1LL);\n v12 = v5 - 1 - v7 + v13;\n v11 = &v9[v12];\n }\n if ( (int)v3 > v5 + 1 )\n {\n v14 = v12;\n memcpy(&v9[v12], &src[v5 + 1], (unsigned int)(v3 - 2 - v5) + 1LL);\n v11 = &v9[v8 - v5 + v14];\n }\n *v11 = 0;\n }\n else\n {\nLABEL_10:\n v9 = (char *)malloc((int)v3 + 1);\n __memcpy_chk(v9, src, v3 + 1, (int)v3 + 1);\n }\n return v9;\n}", + "ida_strip_asm": "sub_1350:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12d, esi\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 18h\ncall _strlen\nmov r13, rax\ntest eax, eax\njle short loc_13C1\nlea ecx, [rax-1]\nmov r14d, 0FFFFFFFFh\nxor eax, eax\nmov ebp, 0FFFFFFFFh\nmov r15, rcx\njmp short loc_1393\nloc_1390:\nmov rax, rdx\nloc_1393:\ncmp [rbx+rax], r12b\njnz short loc_13A2\ncmp ebp, 0FFFFFFFFh\nmov r14d, eax\ncmovz ebp, eax\nloc_13A2:\nlea rdx, [rax+1]\ncmp rcx, rax\njnz short loc_1390\ncmp ebp, 0FFFFFFFFh\nsetnz dl\ncmp r14d, 0FFFFFFFFh\nsetnz al\ntest dl, al\njz short loc_13C1\ncmp ebp, r14d\njnz short loc_1400\nloc_13C1:\nlea ebp, [r13+1]\nmovsxd rbp, ebp\nmov rdi, rbp; size\ncall _malloc\nlea rdx, [r13+1]\nmov rcx, rbp\nmov rsi, rbx\nmov rdi, rax\nmov r12, rax\ncall ___memcpy_chk\nloc_13E5:\nadd rsp, 18h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1400:\nmovsxd rdi, r15d; size\ncall _malloc\nmov r12, rax\ntest ebp, ebp\njle loc_14AD\nmov edx, ebp; n\nmov rsi, rbx; src\nmov rdi, rax; dest\ncall _memcpy\nmovsxd rax, ebp\nmov r8d, ebp\nadd rax, r12\nloc_1429:\nlea ecx, [rbp+1]\ncmp ecx, r14d\njge short loc_1466\nlea edx, [r14-2]\nmovsxd rdi, r8d\nmovsxd rcx, ecx\nmov [rsp+48h+var_3C], r8d\nsub edx, ebp\nadd rdi, r12; dest\nlea rsi, [rbx+rcx]; src\nadd rdx, 1; n\ncall _memcpy\nmov r8d, [rsp+48h+var_3C]\nlea eax, [r14-1]\nsub eax, ebp\nadd r8d, eax\nmovsxd rax, r8d\nadd rax, r12\nloc_1466:\nlea ecx, [r14+1]\ncmp r13d, ecx\njle short loc_14A5\nlea edx, [r13-2]\nmovsxd rdi, r8d\nmovsxd rcx, ecx\nmov [rsp+48h+var_3C], r8d\nmov r13d, edx\nadd rdi, r12; dest\nlea rsi, [rbx+rcx]; src\nsub r15d, r14d\nsub r13d, r14d\nlea rdx, [r13+1]; n\ncall _memcpy\nmov r8d, [rsp+48h+var_3C]\nlea eax, [r15+r8]\ncdqe\nadd rax, r12\nloc_14A5:\nmov byte ptr [rax], 0\njmp loc_13E5\nloc_14AD:\nxor r8d, r8d\njmp loc_1429", + "ida_strip_pseudo": "char *__fastcall sub_1350(const char *src, char a2)\n{\n size_t v2; // rax\n size_t v3; // r13\n __int64 v4; // rcx\n int v5; // r14d\n __int64 v6; // rax\n int v7; // ebp\n int v8; // r15d\n char *v9; // r12\n char *v11; // rax\n int v12; // r8d\n int v13; // [rsp+Ch] [rbp-3Ch]\n int v14; // [rsp+Ch] [rbp-3Ch]\n\n v2 = strlen(src);\n v3 = v2;\n if ( (int)v2 <= 0 )\n goto LABEL_10;\n v4 = (unsigned int)(v2 - 1);\n v5 = -1;\n v6 = 0LL;\n v7 = -1;\n v8 = v4;\n while ( 1 )\n {\n if ( src[v6] == a2 )\n {\n v5 = v6;\n if ( v7 == -1 )\n v7 = v6;\n }\n if ( v4 == v6 )\n break;\n ++v6;\n }\n if ( v5 != -1 && v7 != -1 && v7 != v5 )\n {\n v11 = (char *)malloc((int)v4);\n v9 = v11;\n if ( v7 <= 0 )\n {\n v12 = 0;\n }\n else\n {\n memcpy(v11, src, (unsigned int)v7);\n v12 = v7;\n v11 = &v9[v7];\n }\n if ( v7 + 1 < v5 )\n {\n v13 = v12;\n memcpy(&v9[v12], &src[v7 + 1], (unsigned int)(v5 - 2 - v7) + 1LL);\n v12 = v5 - 1 - v7 + v13;\n v11 = &v9[v12];\n }\n if ( (int)v3 > v5 + 1 )\n {\n v14 = v12;\n memcpy(&v9[v12], &src[v5 + 1], (unsigned int)(v3 - 2 - v5) + 1LL);\n v11 = &v9[v8 - v5 + v14];\n }\n *v11 = 0;\n }\n else\n {\nLABEL_10:\n v9 = (char *)malloc((int)v3 + 1);\n __memcpy_chk(v9, src, v3 + 1, (int)v3 + 1);\n }\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1350(const char *src, char a2) {\n unsigned int v2;\n unsigned int v3;\n long long v4;\n int v5;\n long long v6;\n int v7;\n int v8;\n char *v9;\n char *v11;\n int v12;\n int v13;\n int v14;\n v2 = strlen(src);\n v3 = v2;\n if ((int)v2 <= 0) goto LABEL_10;\n v4 = (unsigned int)(v2 - 1);\n v5 = -1;\n v6 = 0LL;\n v7 = -1;\n v8 = v4;\n while (1) {\n if (src[v6] == a2) {\n v5 = v6;\n if (v7 == -1) v7 = v6;\n }\n if (v4 == v6) break;\n ++v6;\n }\n if (v5 != -1 && v7 != -1 && v7 != v5) {\n v11 = (char *)malloc((int)v4);\n v9 = v11;\n if (v7 <= 0) {\n v12 = 0;\n } else {\n memcpy(v11, src, (unsigned int)v7);\n v12 = v7;\n v11 = &v9[v7];\n }\n if (v7 + 1 < v5) {\n v13 = v12;\n memcpy(&v9[v12], &src[v7 + 1], (unsigned int)(v5 - 2 - v7) + 1LL);\n v12 = v5 - 1 - v7 + v13;\n v11 = &v9[v12];\n }\n if ((int)v3 > v5 + 1) {\n v14 = v12;\n memcpy(&v9[v12], &src[v5 + 1], (unsigned int)(v3 - 2 - v5) + 1LL);\n v11 = &v9[v8 - v5 + v14];\n }\n *v11 = 0;\n } else {\n LABEL_10:\n v9 = (char *)malloc((int)v3 + 1);\n __memcpy_chk(v9, src, v3 + 1, (int)v3 + 1);\n }\n return v9;\n}", + "ida_pseudo_norm": "char *func0(const char *src, char a2) {\n unsigned int v2;\n unsigned int v3;\n long long v4;\n int v5;\n long long v6;\n int v7;\n int v8;\n char *v9;\n char *v11;\n int v12;\n int v13;\n int v14;\n v2 = strlen(src);\n v3 = v2;\n if ((int)v2 <= 0) goto LABEL_10;\n v4 = (unsigned int)(v2 - 1);\n v5 = -1;\n v6 = 0LL;\n v7 = -1;\n v8 = v4;\n while (1) {\n if (src[v6] == a2) {\n v5 = v6;\n if (v7 == -1) v7 = v6;\n }\n if (v4 == v6) break;\n ++v6;\n }\n if (v5 != -1 && v7 != -1 && v7 != v5) {\n v11 = (char *)malloc((int)v4);\n v9 = v11;\n if (v7 <= 0) {\n v12 = 0;\n } else {\n memcpy(v11, src, (unsigned int)v7);\n v12 = v7;\n v11 = &v9[v7];\n }\n if (v7 + 1 < v5) {\n v13 = v12;\n memcpy(&v9[v12], &src[v7 + 1], (unsigned int)(v5 - 2 - v7) + 1LL);\n v12 = v5 - 1 - v7 + v13;\n v11 = &v9[v12];\n }\n if ((int)v3 > v5 + 1) {\n v14 = v12;\n memcpy(&v9[v12], &src[v5 + 1], (unsigned int)(v3 - 2 - v5) + 1LL);\n v11 = &v9[v8 - v5 + v14];\n }\n *v11 = 0;\n } else {\n LABEL_10:\n v9 = (char *)malloc((int)v3 + 1);\n __memcpy_chk(v9, src, v3 + 1, (int)v3 + 1);\n }\n return v9;\n}" + }, + { + "index": 11, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char *func0(const char *str, char ch) {\n int len = strlen(str);\n int first = -1, last = -1;\n for (int i = 0; i < len; i++) {\n if (str[i] == ch) {\n if (first == -1) {\n first = i;\n }\n last = i;\n }\n }\n if (first != -1 && last != -1 && first != last) {\n char *new_str = (char *)malloc(len - 2 + 1);\n int new_index = 0;\n for (int i = 0; i < first; i++) {\n new_str[new_index++] = str[i];\n }\n for (int i = first + 1; i < last; i++) {\n new_str[new_index++] = str[i];\n }\n for (int i = last + 1; i < len; i++) {\n new_str[new_index++] = str[i];\n }\n new_str[new_index] = '\\0';\n return new_str;\n }\n char *new_str = (char *)malloc(len + 1);\n strcpy(new_str, str);\n return new_str;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"hello\",'l'), \"heo\") == 0);\n\n assert(strcmp(func0(\"abcda\",'a'), \"bcd\") == 0);\n\n assert(strcmp(func0(\"PHP\",'P'), \"H\") == 0);\n\n assert(strcmp(func0(\"hellolloll\",'l'), \"helollol\") == 0);\n\n assert(strcmp(func0(\"\",'l'), \"\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\nmov %esi,%r12d\npush %rbp\nmov %rdi,%rbp\npush %rbx\nsub $0x18,%rsp\ncallq 1080 \nmov %rax,%r13\ntest %eax,%eax\njle 1392 \nlea -0x1(%rax),%ecx\nmov $0xffffffff,%r14d\nxor %eax,%eax\nmov $0xffffffff,%ebx\nmov %rcx,%r15\njmp 1363 \nnopl 0x0(%rax)\nmov %rdx,%rax\ncmp 0x0(%rbp,%rax,1),%r12b\njne 1373 \ncmp $0xffffffff,%ebx\nmov %eax,%r14d\ncmove %eax,%ebx\nlea 0x1(%rax),%rdx\ncmp %rax,%rcx\njne 1360 \ncmp $0xffffffff,%ebx\nsetne %dl\ncmp $0xffffffff,%r14d\nsetne %al\ntest %al,%dl\nje 1392 \ncmp %ebx,%r14d\njne 13c8 \nlea 0x1(%r13),%edi\nmovslq %edi,%rdi\ncallq 10b0 \nlea 0x1(%r13),%rdx\nmov %rbp,%rsi\nmov %rax,%rdi\nmov %rax,%r12\ncallq 10a0 \nadd $0x18,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw 0x0(%rax,%rax,1)\nmovslq %r15d,%rdi\ncallq 10b0 \nmov %rax,%r12\ntest %ebx,%ebx\njle 1480 \nlea -0x1(%rbx),%edx\nmov %rbp,%rsi\nmov %rax,%rdi\nadd $0x1,%rdx\ncallq 10a0 \nmovslq %ebx,%rax\nmov %ebx,%r8d\nadd %r12,%rax\nlea 0x1(%rbx),%edx\ncmp %edx,%r14d\njle 1438 \nlea -0x2(%r14),%r9d\nmovslq %r8d,%rdi\nmovslq %edx,%rdx\nmov %r8d,0xc(%rsp)\nsub %ebx,%r9d\nlea 0x0(%rbp,%rdx,1),%rsi\nadd %r12,%rdi\nadd $0x1,%r9\nmov %r9,%rdx\ncallq 10a0 \nmov 0xc(%rsp),%r8d\nlea -0x1(%r14),%eax\nsub %ebx,%eax\nadd %eax,%r8d\nmovslq %r8d,%rax\nadd %r12,%rax\nlea 0x1(%r14),%ecx\ncmp %ecx,%r13d\njle 1478 \nlea -0x2(%r13),%edx\nmovslq %r8d,%rdi\nmovslq %ecx,%rcx\nmov %r8d,0xc(%rsp)\nmov %edx,%r13d\nadd %r12,%rdi\nlea 0x0(%rbp,%rcx,1),%rsi\nsub %r14d,%r15d\nsub %r14d,%r13d\nlea 0x1(%r13),%rdx\ncallq 10a0 \nmov 0xc(%rsp),%r8d\nlea (%r15,%r8,1),%eax\ncltq\nadd %r12,%rax\nmovb $0x0,(%rax)\njmpq 13b0 \nxor %r8d,%r8d\njmpq 13f6 \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12d, esi\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 18h\ncall _strlen\nmov r13, rax\ntest eax, eax\njle short loc_13C1\nlea ecx, [rax-1]\nmov r14d, 0FFFFFFFFh\nxor eax, eax\nmov ebp, 0FFFFFFFFh\nmov r15, rcx\njmp short loc_1393\nloc_1390:\nmov rax, rdx\nloc_1393:\ncmp [rbx+rax], r12b\njnz short loc_13A2\ncmp ebp, 0FFFFFFFFh\nmov r14d, eax\ncmovz ebp, eax\nloc_13A2:\nlea rdx, [rax+1]\ncmp rcx, rax\njnz short loc_1390\ncmp ebp, 0FFFFFFFFh\nsetnz dl\ncmp r14d, 0FFFFFFFFh\nsetnz al\ntest dl, al\njz short loc_13C1\ncmp ebp, r14d\njnz short loc_1400\nloc_13C1:\nlea ebp, [r13+1]\nmovsxd rbp, ebp\nmov rdi, rbp; size\ncall _malloc\nlea rdx, [r13+1]\nmov rcx, rbp\nmov rsi, rbx\nmov rdi, rax\nmov r12, rax\ncall ___memcpy_chk\nloc_13E5:\nadd rsp, 18h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1400:\nmovsxd rdi, r15d; size\ncall _malloc\nmov r12, rax\ntest ebp, ebp\njle loc_14AD\nmov edx, ebp; n\nmov rsi, rbx; src\nmov rdi, rax; dest\ncall _memcpy\nmovsxd rax, ebp\nmov r8d, ebp\nadd rax, r12\nloc_1429:\nlea ecx, [rbp+1]\ncmp ecx, r14d\njge short loc_1466\nlea edx, [r14-2]\nmovsxd rdi, r8d\nmovsxd rcx, ecx\nmov [rsp+48h+var_3C], r8d\nsub edx, ebp\nadd rdi, r12; dest\nlea rsi, [rbx+rcx]; src\nadd rdx, 1; n\ncall _memcpy\nmov r8d, [rsp+48h+var_3C]\nlea eax, [r14-1]\nsub eax, ebp\nadd r8d, eax\nmovsxd rax, r8d\nadd rax, r12\nloc_1466:\nlea ecx, [r14+1]\ncmp r13d, ecx\njle short loc_14A5\nlea edx, [r13-2]\nmovsxd rdi, r8d\nmovsxd rcx, ecx\nmov [rsp+48h+var_3C], r8d\nmov r13d, edx\nadd rdi, r12; dest\nlea rsi, [rbx+rcx]; src\nsub r15d, r14d\nsub r13d, r14d\nlea rdx, [r13+1]; n\ncall _memcpy\nmov r8d, [rsp+48h+var_3C]\nlea eax, [r15+r8]\ncdqe\nadd rax, r12\nloc_14A5:\nmov byte ptr [rax], 0\njmp loc_13E5\nloc_14AD:\nxor r8d, r8d\njmp loc_1429", + "ida_pseudo": "char *__fastcall func0(const char *src, char a2)\n{\n size_t v2; // rax\n size_t v3; // r13\n __int64 v4; // rcx\n int v5; // r14d\n __int64 v6; // rax\n int v7; // ebp\n int v8; // r15d\n char *v9; // r12\n char *v11; // rax\n int v12; // r8d\n int v13; // [rsp+Ch] [rbp-3Ch]\n int v14; // [rsp+Ch] [rbp-3Ch]\n\n v2 = strlen(src);\n v3 = v2;\n if ( (int)v2 <= 0 )\n goto LABEL_10;\n v4 = (unsigned int)(v2 - 1);\n v5 = -1;\n v6 = 0LL;\n v7 = -1;\n v8 = v4;\n while ( 1 )\n {\n if ( src[v6] == a2 )\n {\n v5 = v6;\n if ( v7 == -1 )\n v7 = v6;\n }\n if ( v4 == v6 )\n break;\n ++v6;\n }\n if ( v5 != -1 && v7 != -1 && v7 != v5 )\n {\n v11 = (char *)malloc((int)v4);\n v9 = v11;\n if ( v7 <= 0 )\n {\n v12 = 0;\n }\n else\n {\n memcpy(v11, src, (unsigned int)v7);\n v12 = v7;\n v11 = &v9[v7];\n }\n if ( v7 + 1 < v5 )\n {\n v13 = v12;\n memcpy(&v9[v12], &src[v7 + 1], (unsigned int)(v5 - 2 - v7) + 1LL);\n v12 = v5 - 1 - v7 + v13;\n v11 = &v9[v12];\n }\n if ( (int)v3 > v5 + 1 )\n {\n v14 = v12;\n memcpy(&v9[v12], &src[v5 + 1], (unsigned int)(v3 - 2 - v5) + 1LL);\n v11 = &v9[v8 - v5 + v14];\n }\n *v11 = 0;\n }\n else\n {\nLABEL_10:\n v9 = (char *)malloc((int)v3 + 1);\n __memcpy_chk(v9, src, v3 + 1, (int)v3 + 1);\n }\n return v9;\n}", + "ida_strip_asm": "sub_1350:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12d, esi\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 18h\ncall _strlen\nmov r13, rax\ntest eax, eax\njle short loc_13C1\nlea ecx, [rax-1]\nmov r14d, 0FFFFFFFFh\nxor eax, eax\nmov ebp, 0FFFFFFFFh\nmov r15, rcx\njmp short loc_1393\nloc_1390:\nmov rax, rdx\nloc_1393:\ncmp [rbx+rax], r12b\njnz short loc_13A2\ncmp ebp, 0FFFFFFFFh\nmov r14d, eax\ncmovz ebp, eax\nloc_13A2:\nlea rdx, [rax+1]\ncmp rcx, rax\njnz short loc_1390\ncmp ebp, 0FFFFFFFFh\nsetnz dl\ncmp r14d, 0FFFFFFFFh\nsetnz al\ntest dl, al\njz short loc_13C1\ncmp ebp, r14d\njnz short loc_1400\nloc_13C1:\nlea ebp, [r13+1]\nmovsxd rbp, ebp\nmov rdi, rbp; size\ncall _malloc\nlea rdx, [r13+1]\nmov rcx, rbp\nmov rsi, rbx\nmov rdi, rax\nmov r12, rax\ncall ___memcpy_chk\nloc_13E5:\nadd rsp, 18h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1400:\nmovsxd rdi, r15d; size\ncall _malloc\nmov r12, rax\ntest ebp, ebp\njle loc_14AD\nmov edx, ebp; n\nmov rsi, rbx; src\nmov rdi, rax; dest\ncall _memcpy\nmovsxd rax, ebp\nmov r8d, ebp\nadd rax, r12\nloc_1429:\nlea ecx, [rbp+1]\ncmp ecx, r14d\njge short loc_1466\nlea edx, [r14-2]\nmovsxd rdi, r8d\nmovsxd rcx, ecx\nmov [rsp+48h+var_3C], r8d\nsub edx, ebp\nadd rdi, r12; dest\nlea rsi, [rbx+rcx]; src\nadd rdx, 1; n\ncall _memcpy\nmov r8d, [rsp+48h+var_3C]\nlea eax, [r14-1]\nsub eax, ebp\nadd r8d, eax\nmovsxd rax, r8d\nadd rax, r12\nloc_1466:\nlea ecx, [r14+1]\ncmp r13d, ecx\njle short loc_14A5\nlea edx, [r13-2]\nmovsxd rdi, r8d\nmovsxd rcx, ecx\nmov [rsp+48h+var_3C], r8d\nmov r13d, edx\nadd rdi, r12; dest\nlea rsi, [rbx+rcx]; src\nsub r15d, r14d\nsub r13d, r14d\nlea rdx, [r13+1]; n\ncall _memcpy\nmov r8d, [rsp+48h+var_3C]\nlea eax, [r15+r8]\ncdqe\nadd rax, r12\nloc_14A5:\nmov byte ptr [rax], 0\njmp loc_13E5\nloc_14AD:\nxor r8d, r8d\njmp loc_1429", + "ida_strip_pseudo": "char *__fastcall sub_1350(const char *src, char a2)\n{\n size_t v2; // rax\n size_t v3; // r13\n __int64 v4; // rcx\n int v5; // r14d\n __int64 v6; // rax\n int v7; // ebp\n int v8; // r15d\n char *v9; // r12\n char *v11; // rax\n int v12; // r8d\n int v13; // [rsp+Ch] [rbp-3Ch]\n int v14; // [rsp+Ch] [rbp-3Ch]\n\n v2 = strlen(src);\n v3 = v2;\n if ( (int)v2 <= 0 )\n goto LABEL_10;\n v4 = (unsigned int)(v2 - 1);\n v5 = -1;\n v6 = 0LL;\n v7 = -1;\n v8 = v4;\n while ( 1 )\n {\n if ( src[v6] == a2 )\n {\n v5 = v6;\n if ( v7 == -1 )\n v7 = v6;\n }\n if ( v4 == v6 )\n break;\n ++v6;\n }\n if ( v5 != -1 && v7 != -1 && v7 != v5 )\n {\n v11 = (char *)malloc((int)v4);\n v9 = v11;\n if ( v7 <= 0 )\n {\n v12 = 0;\n }\n else\n {\n memcpy(v11, src, (unsigned int)v7);\n v12 = v7;\n v11 = &v9[v7];\n }\n if ( v7 + 1 < v5 )\n {\n v13 = v12;\n memcpy(&v9[v12], &src[v7 + 1], (unsigned int)(v5 - 2 - v7) + 1LL);\n v12 = v5 - 1 - v7 + v13;\n v11 = &v9[v12];\n }\n if ( (int)v3 > v5 + 1 )\n {\n v14 = v12;\n memcpy(&v9[v12], &src[v5 + 1], (unsigned int)(v3 - 2 - v5) + 1LL);\n v11 = &v9[v8 - v5 + v14];\n }\n *v11 = 0;\n }\n else\n {\nLABEL_10:\n v9 = (char *)malloc((int)v3 + 1);\n __memcpy_chk(v9, src, v3 + 1, (int)v3 + 1);\n }\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1350(const char *src, char a2) {\n unsigned int v2;\n unsigned int v3;\n long long v4;\n int v5;\n long long v6;\n int v7;\n int v8;\n char *v9;\n char *v11;\n int v12;\n int v13;\n int v14;\n v2 = strlen(src);\n v3 = v2;\n if ((int)v2 <= 0) goto LABEL_10;\n v4 = (unsigned int)(v2 - 1);\n v5 = -1;\n v6 = 0LL;\n v7 = -1;\n v8 = v4;\n while (1) {\n if (src[v6] == a2) {\n v5 = v6;\n if (v7 == -1) v7 = v6;\n }\n if (v4 == v6) break;\n ++v6;\n }\n if (v5 != -1 && v7 != -1 && v7 != v5) {\n v11 = (char *)malloc((int)v4);\n v9 = v11;\n if (v7 <= 0) {\n v12 = 0;\n } else {\n memcpy(v11, src, (unsigned int)v7);\n v12 = v7;\n v11 = &v9[v7];\n }\n if (v7 + 1 < v5) {\n v13 = v12;\n memcpy(&v9[v12], &src[v7 + 1], (unsigned int)(v5 - 2 - v7) + 1LL);\n v12 = v5 - 1 - v7 + v13;\n v11 = &v9[v12];\n }\n if ((int)v3 > v5 + 1) {\n v14 = v12;\n memcpy(&v9[v12], &src[v5 + 1], (unsigned int)(v3 - 2 - v5) + 1LL);\n v11 = &v9[v8 - v5 + v14];\n }\n *v11 = 0;\n } else {\n LABEL_10:\n v9 = (char *)malloc((int)v3 + 1);\n __memcpy_chk(v9, src, v3 + 1, (int)v3 + 1);\n }\n return v9;\n}", + "ida_pseudo_norm": "char *func0(const char *src, char a2) {\n unsigned int v2;\n unsigned int v3;\n long long v4;\n int v5;\n long long v6;\n int v7;\n int v8;\n char *v9;\n char *v11;\n int v12;\n int v13;\n int v14;\n v2 = strlen(src);\n v3 = v2;\n if ((int)v2 <= 0) goto LABEL_10;\n v4 = (unsigned int)(v2 - 1);\n v5 = -1;\n v6 = 0LL;\n v7 = -1;\n v8 = v4;\n while (1) {\n if (src[v6] == a2) {\n v5 = v6;\n if (v7 == -1) v7 = v6;\n }\n if (v4 == v6) break;\n ++v6;\n }\n if (v5 != -1 && v7 != -1 && v7 != v5) {\n v11 = (char *)malloc((int)v4);\n v9 = v11;\n if (v7 <= 0) {\n v12 = 0;\n } else {\n memcpy(v11, src, (unsigned int)v7);\n v12 = v7;\n v11 = &v9[v7];\n }\n if (v7 + 1 < v5) {\n v13 = v12;\n memcpy(&v9[v12], &src[v7 + 1], (unsigned int)(v5 - 2 - v7) + 1LL);\n v12 = v5 - 1 - v7 + v13;\n v11 = &v9[v12];\n }\n if ((int)v3 > v5 + 1) {\n v14 = v12;\n memcpy(&v9[v12], &src[v5 + 1], (unsigned int)(v3 - 2 - v5) + 1LL);\n v11 = &v9[v8 - v5 + v14];\n }\n *v11 = 0;\n } else {\n LABEL_10:\n v9 = (char *)malloc((int)v3 + 1);\n __memcpy_chk(v9, src, v3 + 1, (int)v3 + 1);\n }\n return v9;\n}" + }, + { + "index": 12, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint sum(const int *row, int cols) {\n\n int total = 0;\n\n for (int i = 0; i < cols; i++) {\n\n total += row[i];\n\n }\n\n return total;\n\n}\n\n\n\nint compare(const void *a, const void *b, void *cols) {\n\n int sum_a = sum(*(const int **)a, *(int *)cols);\n\n int sum_b = sum(*(const int **)b, *(int *)cols);\n\n return (sum_a > sum_b) - (sum_a < sum_b);\n\n}\n\n\n\n", + "func": "void func0(int **M, int rows, int cols) {\n qsort_r(M, rows, sizeof(int *), compare, &cols);\n}", + "test": "int main() {\n\n int rows1 = 3, cols1 =3;\n\n int row1[] = {1, 2, 3}, row2[] = {2, 4, 5}, row3[] = {1, 1, 1};\n\n int *matrix1[] = {row1, row2, row3};\n\n func0(matrix1, rows1, cols1);\n\n assert(matrix1[0][0] == 1 && matrix1[0][1] == 1 && matrix1[0][2] == 1);\n\n assert(matrix1[1][0] == 1 && matrix1[1][1] == 2 && matrix1[1][2] == 3);\n\n assert(matrix1[2][0] == 2 && matrix1[2][1] == 4 && matrix1[2][2] == 5);\n\n\n\n int row4[] = {1, 2, 3}, row5[] = {-2, 4, -5}, row6[] = {1, -1, 1};\n\n int *matrix2[] = {row4, row5, row6};\n\n func0(matrix2, rows1, cols1);\n\n assert(matrix2[0][0] == -2 && matrix2[0][1] == 4 && matrix2[0][2] == -5);\n\n assert(matrix2[1][0] == 1 && matrix2[1][1] == -1 && matrix2[1][2] == 1);\n\n assert(matrix2[2][0] == 1 && matrix2[2][1] == 2 && matrix2[2][2] == 3);\n\n\n\n int row7[] = {5, 8, 9}, row8[] = {6, 4, 3}, row9[] = {2, 1, 4};\n\n int *matrix3[] = {row7, row8, row9};\n\n func0(matrix3, rows1, cols1);\n\n assert(matrix3[0][0] == 2 && matrix3[0][1] == 1 && matrix3[0][2] == 4);\n\n assert(matrix3[1][0] == 6 && matrix3[1][1] == 4 && matrix3[1][2] == 3);\n\n assert(matrix3[2][0] == 5 && matrix3[2][1] == 8 && matrix3[2][2] == 9);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %rdi,-0x8(%rbp)\nmov %esi,-0xc(%rbp)\nmov %edx,-0x10(%rbp)\nlea -0x10(%rbp),%rdx\nmov -0xc(%rbp),%esi\nmov -0x8(%rbp),%rax\nmov %rdx,%r8\nlea -0x95(%rip),%rcx\nmov $0x8,%edx\nmov %rax,%rdi\nmov $0x0,%eax\ncallq 1090 \nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+nmemb+4], rdi\nmov dword ptr [rbp+nmemb], esi\nmov [rbp+arg], edx\nlea rdx, [rbp+arg]\nmov esi, dword ptr [rbp+nmemb]; nmemb\nmov rax, [rbp+nmemb+4]\nmov r8, rdx; arg\nlea rdx, compare\nmov rcx, rdx; compar\nmov edx, 8; size\nmov rdi, rax; base\nmov eax, 0\ncall _qsort_r\nnop\nleave\nretn", + "ida_pseudo": "void __fastcall func0(void *a1, unsigned int a2, int a3)\n{\n _DWORD arg[2]; // [rsp+0h] [rbp-10h] BYREF\n void *nmemb_4; // [rsp+8h] [rbp-8h]\n\n nmemb_4 = a1;\n arg[1] = a2;\n arg[0] = a3;\n qsort_r(a1, a2, 8uLL, compare, arg);\n}", + "ida_strip_asm": "sub_123C:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+nmemb+4], rdi\nmov dword ptr [rbp+nmemb], esi\nmov [rbp+arg], edx\nlea rdx, [rbp+arg]\nmov esi, dword ptr [rbp+nmemb]; nmemb\nmov rax, [rbp+nmemb+4]\nmov r8, rdx; arg\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 8; size\nmov rdi, rax; base\nmov eax, 0\ncall _qsort_r\nnop\nleave\nretn", + "ida_strip_pseudo": "void __fastcall sub_123C(void *a1, unsigned int a2, int a3)\n{\n _DWORD arg[2]; // [rsp+0h] [rbp-10h] BYREF\n void *nmemb_4; // [rsp+8h] [rbp-8h]\n\n nmemb_4 = a1;\n arg[1] = a2;\n arg[0] = a3;\n qsort_r(a1, a2, 8uLL, compar, arg);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_123C(void *a1, unsigned int a2, int a3) {\n uint32_t arg[2];\n void *nmemb_4;\n nmemb_4 = a1;\n arg[1] = a2;\n arg[0] = a3;\n qsort_r(a1, a2, 8uLL, compar, arg);\n}", + "ida_pseudo_norm": "void func0(void *a1, unsigned int a2, int a3) {\n uint32_t arg[2];\n void *nmemb_4;\n nmemb_4 = a1;\n arg[1] = a2;\n arg[0] = a3;\n qsort_r(a1, a2, 8uLL, compare, arg);\n}" + }, + { + "index": 12, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint sum(const int *row, int cols) {\n\n int total = 0;\n\n for (int i = 0; i < cols; i++) {\n\n total += row[i];\n\n }\n\n return total;\n\n}\n\n\n\nint compare(const void *a, const void *b, void *cols) {\n\n int sum_a = sum(*(const int **)a, *(int *)cols);\n\n int sum_b = sum(*(const int **)b, *(int *)cols);\n\n return (sum_a > sum_b) - (sum_a < sum_b);\n\n}\n\n\n\n", + "func": "void func0(int **M, int rows, int cols) {\n qsort_r(M, rows, sizeof(int *), compare, &cols);\n}", + "test": "int main() {\n\n int rows1 = 3, cols1 =3;\n\n int row1[] = {1, 2, 3}, row2[] = {2, 4, 5}, row3[] = {1, 1, 1};\n\n int *matrix1[] = {row1, row2, row3};\n\n func0(matrix1, rows1, cols1);\n\n assert(matrix1[0][0] == 1 && matrix1[0][1] == 1 && matrix1[0][2] == 1);\n\n assert(matrix1[1][0] == 1 && matrix1[1][1] == 2 && matrix1[1][2] == 3);\n\n assert(matrix1[2][0] == 2 && matrix1[2][1] == 4 && matrix1[2][2] == 5);\n\n\n\n int row4[] = {1, 2, 3}, row5[] = {-2, 4, -5}, row6[] = {1, -1, 1};\n\n int *matrix2[] = {row4, row5, row6};\n\n func0(matrix2, rows1, cols1);\n\n assert(matrix2[0][0] == -2 && matrix2[0][1] == 4 && matrix2[0][2] == -5);\n\n assert(matrix2[1][0] == 1 && matrix2[1][1] == -1 && matrix2[1][2] == 1);\n\n assert(matrix2[2][0] == 1 && matrix2[2][1] == 2 && matrix2[2][2] == 3);\n\n\n\n int row7[] = {5, 8, 9}, row8[] = {6, 4, 3}, row9[] = {2, 1, 4};\n\n int *matrix3[] = {row7, row8, row9};\n\n func0(matrix3, rows1, cols1);\n\n assert(matrix3[0][0] == 2 && matrix3[0][1] == 1 && matrix3[0][2] == 4);\n\n assert(matrix3[1][0] == 6 && matrix3[1][1] == 4 && matrix3[1][2] == 3);\n\n assert(matrix3[2][0] == 5 && matrix3[2][1] == 8 && matrix3[2][2] == 9);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x18,%rsp\nmov %edx,0xc(%rsp)\nlea 0xc(%rsp),%r8\nlea -0x56(%rip),%rcx\nmov $0x8,%edx\nmov $0x0,%eax\ncallq 1090 \nadd $0x18,%rsp\nretq\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 18h\nmov [rsp+18h+arg], edx\nlea r8, [rsp+18h+arg]; arg\nlea rcx, compare; compar\nmov edx, 8; size\nmov eax, 0\ncall _qsort_r\nadd rsp, 18h\nretn", + "ida_pseudo": "void __fastcall func0(void *a1, size_t a2, int a3)\n{\n _DWORD arg[3]; // [rsp+Ch] [rbp-Ch] BYREF\n\n arg[0] = a3;\n qsort_r(a1, a2, 8uLL, compare, arg);\n}", + "ida_strip_asm": "sub_11F1:\nendbr64\nsub rsp, 18h\nmov [rsp+18h+arg], edx\nlea r8, [rsp+18h+arg]; arg\nlea rcx, compar; compar\nmov edx, 8; size\nmov eax, 0\ncall _qsort_r\nadd rsp, 18h\nretn", + "ida_strip_pseudo": "void __fastcall sub_11F1(void *a1, size_t a2, int a3)\n{\n _DWORD arg[3]; // [rsp+Ch] [rbp-Ch] BYREF\n\n arg[0] = a3;\n qsort_r(a1, a2, 8uLL, compar, arg);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_11F1(void *a1, unsigned int a2, int a3) {\n uint32_t arg[3];\n arg[0] = a3;\n qsort_r(a1, a2, 8uLL, compar, arg);\n}", + "ida_pseudo_norm": "void func0(void *a1, unsigned int a2, int a3) {\n uint32_t arg[3];\n arg[0] = a3;\n qsort_r(a1, a2, 8uLL, compare, arg);\n}" + }, + { + "index": 12, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint sum(const int *row, int cols) {\n\n int total = 0;\n\n for (int i = 0; i < cols; i++) {\n\n total += row[i];\n\n }\n\n return total;\n\n}\n\n\n\nint compare(const void *a, const void *b, void *cols) {\n\n int sum_a = sum(*(const int **)a, *(int *)cols);\n\n int sum_b = sum(*(const int **)b, *(int *)cols);\n\n return (sum_a > sum_b) - (sum_a < sum_b);\n\n}\n\n\n\n", + "func": "void func0(int **M, int rows, int cols) {\n qsort_r(M, rows, sizeof(int *), compare, &cols);\n}", + "test": "int main() {\n\n int rows1 = 3, cols1 =3;\n\n int row1[] = {1, 2, 3}, row2[] = {2, 4, 5}, row3[] = {1, 1, 1};\n\n int *matrix1[] = {row1, row2, row3};\n\n func0(matrix1, rows1, cols1);\n\n assert(matrix1[0][0] == 1 && matrix1[0][1] == 1 && matrix1[0][2] == 1);\n\n assert(matrix1[1][0] == 1 && matrix1[1][1] == 2 && matrix1[1][2] == 3);\n\n assert(matrix1[2][0] == 2 && matrix1[2][1] == 4 && matrix1[2][2] == 5);\n\n\n\n int row4[] = {1, 2, 3}, row5[] = {-2, 4, -5}, row6[] = {1, -1, 1};\n\n int *matrix2[] = {row4, row5, row6};\n\n func0(matrix2, rows1, cols1);\n\n assert(matrix2[0][0] == -2 && matrix2[0][1] == 4 && matrix2[0][2] == -5);\n\n assert(matrix2[1][0] == 1 && matrix2[1][1] == -1 && matrix2[1][2] == 1);\n\n assert(matrix2[2][0] == 1 && matrix2[2][1] == 2 && matrix2[2][2] == 3);\n\n\n\n int row7[] = {5, 8, 9}, row8[] = {6, 4, 3}, row9[] = {2, 1, 4};\n\n int *matrix3[] = {row7, row8, row9};\n\n func0(matrix3, rows1, cols1);\n\n assert(matrix3[0][0] == 2 && matrix3[0][1] == 1 && matrix3[0][2] == 4);\n\n assert(matrix3[1][0] == 6 && matrix3[1][1] == 4 && matrix3[1][2] == 3);\n\n assert(matrix3[2][0] == 5 && matrix3[2][1] == 8 && matrix3[2][2] == 9);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x18,%rsp\nlea -0xaf(%rip),%rcx\nxor %eax,%eax\nmov %edx,0xc(%rsp)\nlea 0xc(%rsp),%r8\nmov $0x8,%edx\ncallq 1090 \nadd $0x18,%rsp\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 18h\nlea rcx, compare; compar\nxor eax, eax\nmov [rsp+18h+arg], edx\nlea r8, [rsp+18h+arg]; arg\nmov edx, 8; size\ncall _qsort_r\nadd rsp, 18h\nretn", + "ida_pseudo": "void __fastcall func0(void *a1, size_t a2, int a3)\n{\n _DWORD arg[3]; // [rsp+Ch] [rbp-Ch] BYREF\n\n arg[0] = a3;\n qsort_r(a1, a2, 8uLL, compare, arg);\n}", + "ida_strip_asm": "sub_16C0:\nendbr64\nsub rsp, 18h\nlea rcx, compar; compar\nxor eax, eax\nmov [rsp+18h+arg], edx\nlea r8, [rsp+18h+arg]; arg\nmov edx, 8; size\ncall _qsort_r\nadd rsp, 18h\nretn", + "ida_strip_pseudo": "void __fastcall sub_16C0(void *a1, size_t a2, int a3)\n{\n _DWORD arg[3]; // [rsp+Ch] [rbp-Ch] BYREF\n\n arg[0] = a3;\n qsort_r(a1, a2, 8uLL, compar, arg);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_16C0(void *a1, unsigned int a2, int a3) {\n uint32_t arg[3];\n arg[0] = a3;\n qsort_r(a1, a2, 8uLL, compar, arg);\n}", + "ida_pseudo_norm": "void func0(void *a1, unsigned int a2, int a3) {\n uint32_t arg[3];\n arg[0] = a3;\n qsort_r(a1, a2, 8uLL, compare, arg);\n}" + }, + { + "index": 12, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint sum(const int *row, int cols) {\n\n int total = 0;\n\n for (int i = 0; i < cols; i++) {\n\n total += row[i];\n\n }\n\n return total;\n\n}\n\n\n\nint compare(const void *a, const void *b, void *cols) {\n\n int sum_a = sum(*(const int **)a, *(int *)cols);\n\n int sum_b = sum(*(const int **)b, *(int *)cols);\n\n return (sum_a > sum_b) - (sum_a < sum_b);\n\n}\n\n\n\n", + "func": "void func0(int **M, int rows, int cols) {\n qsort_r(M, rows, sizeof(int *), compare, &cols);\n}", + "test": "int main() {\n\n int rows1 = 3, cols1 =3;\n\n int row1[] = {1, 2, 3}, row2[] = {2, 4, 5}, row3[] = {1, 1, 1};\n\n int *matrix1[] = {row1, row2, row3};\n\n func0(matrix1, rows1, cols1);\n\n assert(matrix1[0][0] == 1 && matrix1[0][1] == 1 && matrix1[0][2] == 1);\n\n assert(matrix1[1][0] == 1 && matrix1[1][1] == 2 && matrix1[1][2] == 3);\n\n assert(matrix1[2][0] == 2 && matrix1[2][1] == 4 && matrix1[2][2] == 5);\n\n\n\n int row4[] = {1, 2, 3}, row5[] = {-2, 4, -5}, row6[] = {1, -1, 1};\n\n int *matrix2[] = {row4, row5, row6};\n\n func0(matrix2, rows1, cols1);\n\n assert(matrix2[0][0] == -2 && matrix2[0][1] == 4 && matrix2[0][2] == -5);\n\n assert(matrix2[1][0] == 1 && matrix2[1][1] == -1 && matrix2[1][2] == 1);\n\n assert(matrix2[2][0] == 1 && matrix2[2][1] == 2 && matrix2[2][2] == 3);\n\n\n\n int row7[] = {5, 8, 9}, row8[] = {6, 4, 3}, row9[] = {2, 1, 4};\n\n int *matrix3[] = {row7, row8, row9};\n\n func0(matrix3, rows1, cols1);\n\n assert(matrix3[0][0] == 2 && matrix3[0][1] == 1 && matrix3[0][2] == 4);\n\n assert(matrix3[1][0] == 6 && matrix3[1][1] == 4 && matrix3[1][2] == 3);\n\n assert(matrix3[2][0] == 5 && matrix3[2][1] == 8 && matrix3[2][2] == 9);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x18,%rsp\nlea -0x22f(%rip),%rcx\nxor %eax,%eax\nmov %edx,0xc(%rsp)\nlea 0xc(%rsp),%r8\nmov $0x8,%edx\ncallq 1090 \nadd $0x18,%rsp\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 18h\nlea rcx, compare; compar\nxor eax, eax\nmov [rsp+18h+arg], edx\nlea r8, [rsp+18h+arg]; arg\nmov edx, 8; size\ncall _qsort_r\nadd rsp, 18h\nretn", + "ida_pseudo": "void __fastcall func0(void *a1, size_t a2, int a3)\n{\n _DWORD arg[3]; // [rsp+Ch] [rbp-Ch] BYREF\n\n arg[0] = a3;\n qsort_r(a1, a2, 8uLL, compare, arg);\n}", + "ida_strip_asm": "sub_1850:\nendbr64\nsub rsp, 18h\nlea rcx, compar; compar\nxor eax, eax\nmov [rsp+18h+arg], edx\nlea r8, [rsp+18h+arg]; arg\nmov edx, 8; size\ncall _qsort_r\nadd rsp, 18h\nretn", + "ida_strip_pseudo": "void __fastcall sub_1850(void *a1, size_t a2, int a3)\n{\n _DWORD arg[3]; // [rsp+Ch] [rbp-Ch] BYREF\n\n arg[0] = a3;\n qsort_r(a1, a2, 8uLL, compar, arg);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1850(void *a1, unsigned int a2, int a3) {\n uint32_t arg[3];\n arg[0] = a3;\n qsort_r(a1, a2, 8uLL, compar, arg);\n}", + "ida_pseudo_norm": "void func0(void *a1, unsigned int a2, int a3) {\n uint32_t arg[3];\n arg[0] = a3;\n qsort_r(a1, a2, 8uLL, compare, arg);\n}" + }, + { + "index": 13, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n#define MAX_WORDS 100\n\n#define MAX_WORD_LENGTH 50\n\n\n\ntypedef struct {\n\n char word[MAX_WORD_LENGTH];\n\n int count;\n\n} WordCount;\n\n\n\n", + "func": "void func0(char words[][MAX_WORD_LENGTH], int num_words, WordCount result[],\n int *result_size) {\n WordCount counts[MAX_WORDS] = {0};\n int unique_words = 0;\n for (int i = 0; i < num_words; i++) {\n int found = 0;\n for (int j = 0; j < unique_words; j++) {\n if (strcmp(words[i], counts[j].word) == 0) {\n counts[j].count++;\n found = 1;\n break;\n }\n }\n if (!found) {\n strcpy(counts[unique_words].word, words[i]);\n counts[unique_words].count = 1;\n unique_words++;\n }\n }\n for (int i = 0; i < 4 && i < unique_words; i++) {\n int max_idx = i;\n for (int j = i + 1; j < unique_words; j++) {\n if (counts[j].count > counts[max_idx].count) {\n max_idx = j;\n }\n }\n WordCount tmp = counts[i];\n counts[i] = counts[max_idx];\n counts[max_idx] = tmp;\n strcpy(result[i].word, counts[i].word);\n result[i].count = counts[i].count;\n }\n *result_size = unique_words > 4 ? 4 : unique_words;\n}", + "test": "int main() {\n\n WordCount result[4];\n\n int result_size;\n\n\n\n char data1[][MAX_WORD_LENGTH] = {\"red\",\"green\",\"black\",\"pink\",\"black\",\"white\",\"black\",\"eyes\",\"white\",\"black\",\"orange\",\"pink\",\"pink\",\"red\",\"red\",\"white\",\"orange\",\"white\",\"black\",\"pink\",\"green\",\"green\",\"pink\",\"green\",\"pink\",\"white\",\"orange\",\"orange\",\"red\"};\n\n func0(data1, 29, result, &result_size);\n\n assert(strcmp(result[0].word, \"pink\") == 0 && result[0].count == 6);\n\n assert(strcmp(result[1].word, \"black\") == 0 && result[1].count == 5);\n\n assert(strcmp(result[2].word, \"white\") == 0 && result[2].count == 5);\n\n assert(strcmp(result[3].word, \"red\") == 0 && result[3].count == 4);\n\n \n\n char data2[][MAX_WORD_LENGTH] = {\"one\", \"two\", \"three\", \"four\", \"five\", \"one\", \"two\", \"one\", \"three\", \"one\"};\n\n func0(data2, 10, result, &result_size);\n\n assert(strcmp(result[0].word, \"one\") == 0 && result[0].count == 4);\n\n assert(strcmp(result[1].word, \"two\") == 0 && result[1].count == 2);\n\n assert(strcmp(result[2].word, \"three\") == 0 && result[2].count == 2);\n\n assert(strcmp(result[3].word, \"four\") == 0 && result[3].count == 1);\n\n\n\n char data3[][MAX_WORD_LENGTH] = {\"Facebook\", \"Apple\", \"Amazon\", \"Netflix\", \"Google\", \"Apple\", \"Netflix\", \"Amazon\"};\n\n func0(data3, 8, result, &result_size);\n\n assert(strcmp(result[0].word, \"Apple\") == 0 && result[0].count == 2);\n\n assert(strcmp(result[1].word, \"Amazon\") == 0 && result[1].count == 2);\n\n assert(strcmp(result[2].word, \"Netflix\") == 0 && result[2].count == 2);\n\n assert(strcmp(result[3].word, \"Facebook\") == 0 && result[3].count == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x1000,%rsp\norq $0x0,(%rsp)\nsub $0x678,%rsp\nmov %rdi,-0x1668(%rbp)\nmov %esi,-0x166c(%rbp)\nmov %rdx,-0x1678(%rbp)\nmov %rcx,-0x1680(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nlea -0x1600(%rbp),%rdx\nmov $0x0,%eax\nmov $0x2bc,%ecx\nmov %rdx,%rdi\nrep stos %rax,%es:(%rdi)\nmovl $0x0,-0x165c(%rbp)\nmovl $0x0,-0x1658(%rbp)\njmpq 13aa \nmovl $0x0,-0x1654(%rbp)\nmovl $0x0,-0x1650(%rbp)\njmpq 12f8 \nlea -0x1600(%rbp),%rcx\nmov -0x1650(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x3,%rax\nsub %rdx,%rax\nshl $0x3,%rax\nadd %rax,%rcx\nmov -0x1658(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nadd %rax,%rax\nmov %rax,%rdx\nmov -0x1668(%rbp),%rax\nadd %rdx,%rax\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 10b0 \ntest %eax,%eax\njne 12f1 \nmov -0x1650(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x3,%rax\nsub %rdx,%rax\nshl $0x3,%rax\nlea -0x10(%rbp),%rbx\nadd %rbx,%rax\nsub $0x15bc,%rax\nmov (%rax),%eax\nlea 0x1(%rax),%ecx\nmov -0x1650(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x3,%rax\nsub %rdx,%rax\nshl $0x3,%rax\nlea -0x10(%rbp),%rbx\nadd %rbx,%rax\nsub $0x15bc,%rax\nmov %ecx,(%rax)\nmovl $0x1,-0x1654(%rbp)\njmp 130a \naddl $0x1,-0x1650(%rbp)\nmov -0x1650(%rbp),%eax\ncmp -0x165c(%rbp),%eax\njl 1238 \ncmpl $0x0,-0x1654(%rbp)\njne 13a3 \nmov -0x1658(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nadd %rax,%rax\nmov %rax,%rdx\nmov -0x1668(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nlea -0x1600(%rbp),%rsi\nmov -0x165c(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x3,%rax\nsub %rdx,%rax\nshl $0x3,%rax\nadd %rsi,%rax\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 1080 \nmov -0x165c(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x3,%rax\nsub %rdx,%rax\nshl $0x3,%rax\nlea -0x10(%rbp),%rbx\nadd %rbx,%rax\nsub $0x15bc,%rax\nmovl $0x1,(%rax)\naddl $0x1,-0x165c(%rbp)\naddl $0x1,-0x1658(%rbp)\nmov -0x1658(%rbp),%eax\ncmp -0x166c(%rbp),%eax\njl 121f \nmovl $0x0,-0x164c(%rbp)\njmpq 165d \nmov -0x164c(%rbp),%eax\nmov %eax,-0x1648(%rbp)\nmov -0x164c(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x1644(%rbp)\njmp 144b \nmov -0x1644(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x3,%rax\nsub %rdx,%rax\nshl $0x3,%rax\nlea -0x10(%rbp),%rsi\nadd %rsi,%rax\nsub $0x15bc,%rax\nmov (%rax),%ecx\nmov -0x1648(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x3,%rax\nsub %rdx,%rax\nshl $0x3,%rax\nlea -0x10(%rbp),%rdi\nadd %rdi,%rax\nsub $0x15bc,%rax\nmov (%rax),%eax\ncmp %eax,%ecx\njle 1444 \nmov -0x1644(%rbp),%eax\nmov %eax,-0x1648(%rbp)\naddl $0x1,-0x1644(%rbp)\nmov -0x1644(%rbp),%eax\ncmp -0x165c(%rbp),%eax\njl 13e8 \nmov -0x164c(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x3,%rax\nsub %rdx,%rax\nshl $0x3,%rax\nlea -0x10(%rbp),%rbx\nadd %rbx,%rax\nsub $0x15f0,%rax\nmov (%rax),%rcx\nmov 0x8(%rax),%rbx\nmov %rcx,-0x1640(%rbp)\nmov %rbx,-0x1638(%rbp)\nmov 0x10(%rax),%rcx\nmov 0x18(%rax),%rbx\nmov %rcx,-0x1630(%rbp)\nmov %rbx,-0x1628(%rbp)\nmov 0x20(%rax),%rcx\nmov 0x28(%rax),%rbx\nmov %rcx,-0x1620(%rbp)\nmov %rbx,-0x1618(%rbp)\nmov 0x30(%rax),%rax\nmov %rax,-0x1610(%rbp)\nmov -0x164c(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x3,%rax\nsub %rdx,%rax\nshl $0x3,%rax\nlea -0x10(%rbp),%rsi\nadd %rsi,%rax\nlea -0x15f0(%rax),%rdx\nmov -0x1648(%rbp),%eax\nmovslq %eax,%rcx\nmov %rcx,%rax\nshl $0x3,%rax\nsub %rcx,%rax\nshl $0x3,%rax\nlea -0x10(%rbp),%rdi\nadd %rdi,%rax\nsub $0x15f0,%rax\nmov (%rax),%rcx\nmov 0x8(%rax),%rbx\nmov %rcx,(%rdx)\nmov %rbx,0x8(%rdx)\nmov 0x10(%rax),%rcx\nmov 0x18(%rax),%rbx\nmov %rcx,0x10(%rdx)\nmov %rbx,0x18(%rdx)\nmov 0x20(%rax),%rcx\nmov 0x28(%rax),%rbx\nmov %rcx,0x20(%rdx)\nmov %rbx,0x28(%rdx)\nmov 0x30(%rax),%rax\nmov %rax,0x30(%rdx)\nmov -0x1648(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x3,%rax\nsub %rdx,%rax\nshl $0x3,%rax\nlea -0x10(%rbp),%rbx\nadd %rbx,%rax\nsub $0x15f0,%rax\nmov -0x1640(%rbp),%rcx\nmov -0x1638(%rbp),%rbx\nmov %rcx,(%rax)\nmov %rbx,0x8(%rax)\nmov -0x1630(%rbp),%rcx\nmov -0x1628(%rbp),%rbx\nmov %rcx,0x10(%rax)\nmov %rbx,0x18(%rax)\nmov -0x1620(%rbp),%rcx\nmov -0x1618(%rbp),%rbx\nmov %rcx,0x20(%rax)\nmov %rbx,0x28(%rax)\nmov -0x1610(%rbp),%rdx\nmov %rdx,0x30(%rax)\nlea -0x1600(%rbp),%rcx\nmov -0x164c(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x3,%rax\nsub %rdx,%rax\nshl $0x3,%rax\nadd %rax,%rcx\nmov -0x164c(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x3,%rax\nsub %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nmov -0x1678(%rbp),%rax\nadd %rdx,%rax\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 1080 \nmov -0x164c(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x3,%rax\nsub %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nmov -0x1678(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x164c(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x3,%rax\nsub %rdx,%rax\nshl $0x3,%rax\nlea -0x10(%rbp),%rsi\nadd %rsi,%rax\nsub $0x15bc,%rax\nmov (%rax),%eax\nmov %eax,0x34(%rcx)\naddl $0x1,-0x164c(%rbp)\ncmpl $0x3,-0x164c(%rbp)\njg 1678 \nmov -0x164c(%rbp),%eax\ncmp -0x165c(%rbp),%eax\njl 13cb \nmov $0x4,%eax\ncmpl $0x4,-0x165c(%rbp)\ncmovle -0x165c(%rbp),%eax\nmov %eax,%edx\nmov -0x1680(%rbp),%rax\nmov %edx,(%rax)\nmov -0x18(%rbp),%rax\nxor %fs:0x28,%rax\nje 16ab \ncallq 1090 <__stack_chk_fail@plt>\nadd $0x1678,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 1000h\nor [rsp+1008h+var_1008], 0\nsub rsp, 678h\nmov [rbp+var_1668], rdi\nmov [rbp+var_166C], esi\nmov [rbp+var_1678], rdx\nmov [rbp+var_1680], rcx\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nlea rdx, [rbp+var_1600]\nmov eax, 0\nmov ecx, 2BCh\nmov rdi, rdx\nrep stosq\nmov [rbp+var_165C], 0\nmov [rbp+var_1658], 0\njmp loc_13AA\nloc_121F:\nmov [rbp+var_1654], 0\nmov [rbp+var_1650], 0\njmp loc_12F8\nloc_1238:\nlea rcx, [rbp+var_1600]\nmov eax, [rbp+var_1650]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nadd rcx, rax\nmov eax, [rbp+var_1658]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nadd rax, rax\nmov rdx, rax\nmov rax, [rbp+var_1668]\nadd rax, rdx\nmov rsi, rcx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_12F1\nmov eax, [rbp+var_1650]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nlea rax, [rax-10h]\nadd rax, rbp\nsub rax, 15BCh\nmov eax, [rax]\nlea ecx, [rax+1]\nmov eax, [rbp+var_1650]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nlea rax, [rax-10h]\nadd rax, rbp\nsub rax, 15BCh\nmov [rax], ecx\nmov [rbp+var_1654], 1\njmp short loc_130A\nloc_12F1:\nadd [rbp+var_1650], 1\nloc_12F8:\nmov eax, [rbp+var_1650]\ncmp eax, [rbp+var_165C]\njl loc_1238\nloc_130A:\ncmp [rbp+var_1654], 0\njnz loc_13A3\nmov eax, [rbp+var_1658]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nadd rax, rax\nmov rdx, rax\nmov rax, [rbp+var_1668]\nlea rcx, [rdx+rax]\nlea rsi, [rbp+var_1600]\nmov eax, [rbp+var_165C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nadd rax, rsi\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strcpy\nmov eax, [rbp+var_165C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nlea rax, [rax-10h]\nadd rax, rbp\nsub rax, 15BCh\nmov dword ptr [rax], 1\nadd [rbp+var_165C], 1\nloc_13A3:\nadd [rbp+var_1658], 1\nloc_13AA:\nmov eax, [rbp+var_1658]\ncmp eax, [rbp+var_166C]\njl loc_121F\nmov [rbp+var_164C], 0\njmp loc_165D\nloc_13CB:\nmov eax, [rbp+var_164C]\nmov [rbp+var_1648], eax\nmov eax, [rbp+var_164C]\nadd eax, 1\nmov [rbp+var_1644], eax\njmp short loc_144B\nloc_13E8:\nmov eax, [rbp+var_1644]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nlea rax, [rax-10h]\nadd rax, rbp\nsub rax, 15BCh\nmov ecx, [rax]\nmov eax, [rbp+var_1648]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nlea rax, [rax-10h]\nadd rax, rbp\nsub rax, 15BCh\nmov eax, [rax]\ncmp ecx, eax\njle short loc_1444\nmov eax, [rbp+var_1644]\nmov [rbp+var_1648], eax\nloc_1444:\nadd [rbp+var_1644], 1\nloc_144B:\nmov eax, [rbp+var_1644]\ncmp eax, [rbp+var_165C]\njl short loc_13E8\nmov eax, [rbp+var_164C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nlea rax, [rax-10h]\nadd rax, rbp\nsub rax, 15F0h\nmov rcx, [rax]\nmov rbx, [rax+8]\nmov [rbp+var_1640], rcx\nmov [rbp+var_1638], rbx\nmov rcx, [rax+10h]\nmov rbx, [rax+18h]\nmov [rbp+var_1630], rcx\nmov [rbp+var_1628], rbx\nmov rcx, [rax+20h]\nmov rbx, [rax+28h]\nmov [rbp+var_1620], rcx\nmov [rbp+var_1618], rbx\nmov rax, [rax+30h]\nmov [rbp+var_1610], rax\nmov eax, [rbp+var_164C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nlea rax, [rax-10h]\nadd rax, rbp\nlea rdx, [rax-15F0h]\nmov eax, [rbp+var_1648]\nmovsxd rcx, eax\nmov rax, rcx\nshl rax, 3\nsub rax, rcx\nshl rax, 3\nlea rax, [rax-10h]\nadd rax, rbp\nsub rax, 15F0h\nmov rcx, [rax]\nmov rbx, [rax+8]\nmov [rdx], rcx\nmov [rdx+8], rbx\nmov rcx, [rax+10h]\nmov rbx, [rax+18h]\nmov [rdx+10h], rcx\nmov [rdx+18h], rbx\nmov rcx, [rax+20h]\nmov rbx, [rax+28h]\nmov [rdx+20h], rcx\nmov [rdx+28h], rbx\nmov rax, [rax+30h]\nmov [rdx+30h], rax\nmov eax, [rbp+var_1648]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nlea rax, [rax-10h]\nadd rax, rbp\nsub rax, 15F0h\nmov rcx, [rbp+var_1640]\nmov rbx, [rbp+var_1638]\nmov [rax], rcx\nmov [rax+8], rbx\nmov rcx, [rbp+var_1630]\nmov rbx, [rbp+var_1628]\nmov [rax+10h], rcx\nmov [rax+18h], rbx\nmov rcx, [rbp+var_1620]\nmov rbx, [rbp+var_1618]\nmov [rax+20h], rcx\nmov [rax+28h], rbx\nmov rdx, [rbp+var_1610]\nmov [rax+30h], rdx\nlea rcx, [rbp+var_1600]\nmov eax, [rbp+var_164C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nadd rcx, rax\nmov eax, [rbp+var_164C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_1678]\nadd rax, rdx\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strcpy\nmov eax, [rbp+var_164C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_1678]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_164C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nlea rax, [rax-10h]\nadd rax, rbp\nsub rax, 15BCh\nmov eax, [rax]\nmov [rcx+34h], eax\nadd [rbp+var_164C], 1\nloc_165D:\ncmp [rbp+var_164C], 3\njg short loc_1678\nmov eax, [rbp+var_164C]\ncmp eax, [rbp+var_165C]\njl loc_13CB\nloc_1678:\nmov eax, [rbp+var_165C]\nmov edx, 4\ncmp eax, edx\ncmovle edx, eax\nmov rax, [rbp+var_1680]\nmov [rax], edx\nnop\nmov rax, [rbp+var_18]\nsub rax, fs:28h\njz short loc_16A6\ncall ___stack_chk_fail\nloc_16A6:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "unsigned __int64 __fastcall func0(__int64 a1, int a2, __int64 a3, int *a4)\n{\n _QWORD *v4; // rdx\n _QWORD *v5; // rax\n __int64 v6; // rbx\n __int64 v7; // rbx\n __int64 v8; // rbx\n int v9; // edx\n int v13; // [rsp+24h] [rbp-165Ch]\n int i; // [rsp+28h] [rbp-1658h]\n int v15; // [rsp+2Ch] [rbp-1654h]\n int j; // [rsp+30h] [rbp-1650h]\n int k; // [rsp+34h] [rbp-164Ch]\n int v18; // [rsp+38h] [rbp-1648h]\n int m; // [rsp+3Ch] [rbp-1644h]\n __int64 v20; // [rsp+40h] [rbp-1640h]\n __int64 v21; // [rsp+48h] [rbp-1638h]\n __int64 v22; // [rsp+50h] [rbp-1630h]\n __int64 v23; // [rsp+58h] [rbp-1628h]\n __int64 v24; // [rsp+60h] [rbp-1620h]\n __int64 v25; // [rsp+68h] [rbp-1618h]\n __int64 v26; // [rsp+70h] [rbp-1610h]\n _QWORD v27[701]; // [rsp+80h] [rbp-1600h] BYREF\n unsigned __int64 v28; // [rsp+1668h] [rbp-18h]\n\n v28 = __readfsqword(0x28u);\n memset(v27, 0, 0x15E0uLL);\n v13 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v15 = 0;\n for ( j = 0; j < v13; ++j )\n {\n if ( !strcmp((const char *)(50LL * i + a1), (const char *)&v27[7 * j]) )\n {\n ++HIDWORD(v27[7 * j + 6]);\n v15 = 1;\n break;\n }\n }\n if ( !v15 )\n {\n strcpy((char *)&v27[7 * v13], (const char *)(50LL * i + a1));\n HIDWORD(v27[7 * v13++ + 6]) = 1;\n }\n }\n for ( k = 0; k <= 3 && k < v13; ++k )\n {\n v18 = k;\n for ( m = k + 1; m < v13; ++m )\n {\n if ( SHIDWORD(v27[7 * m + 6]) > SHIDWORD(v27[7 * v18 + 6]) )\n v18 = m;\n }\n v20 = v27[7 * k];\n v21 = v27[7 * k + 1];\n v22 = v27[7 * k + 2];\n v23 = v27[7 * k + 3];\n v24 = v27[7 * k + 4];\n v25 = v27[7 * k + 5];\n v26 = v27[7 * k + 6];\n v4 = &v27[7 * k];\n v5 = &v27[7 * v18];\n v6 = v5[1];\n *v4 = *v5;\n v4[1] = v6;\n v7 = v5[3];\n v4[2] = v27[7 * v18 + 2];\n v4[3] = v7;\n v8 = v5[5];\n v4[4] = v5[4];\n v4[5] = v8;\n v4[6] = v5[6];\n *v5 = v20;\n v5[1] = v21;\n v5[2] = v22;\n v5[3] = v23;\n v5[4] = v24;\n v5[5] = v25;\n v5[6] = v26;\n strcpy((char *)(56LL * k + a3), (const char *)&v27[7 * k]);\n *(_DWORD *)(56LL * k + a3 + 52) = HIDWORD(v27[7 * k + 6]);\n }\n v9 = 4;\n if ( v13 <= 4 )\n v9 = v13;\n *a4 = v9;\n return v28 - __readfsqword(0x28u);\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 1000h\nor [rsp+1008h+var_1008], 0\nsub rsp, 678h\nmov [rbp+var_1668], rdi\nmov [rbp+var_166C], esi\nmov [rbp+var_1678], rdx\nmov [rbp+var_1680], rcx\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nlea rdx, [rbp+var_1600]\nmov eax, 0\nmov ecx, 2BCh\nmov rdi, rdx\nrep stosq\nmov [rbp+var_165C], 0\nmov [rbp+var_1658], 0\njmp loc_13AA\nloc_121F:\nmov [rbp+var_1654], 0\nmov [rbp+var_1650], 0\njmp loc_12F8\nloc_1238:\nlea rcx, [rbp+var_1600]\nmov eax, [rbp+var_1650]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nadd rcx, rax\nmov eax, [rbp+var_1658]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nadd rax, rax\nmov rdx, rax\nmov rax, [rbp+var_1668]\nadd rax, rdx\nmov rsi, rcx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_12F1\nmov eax, [rbp+var_1650]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nlea rax, [rax-10h]\nadd rax, rbp\nsub rax, 15BCh\nmov eax, [rax]\nlea ecx, [rax+1]\nmov eax, [rbp+var_1650]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nlea rax, [rax-10h]\nadd rax, rbp\nsub rax, 15BCh\nmov [rax], ecx\nmov [rbp+var_1654], 1\njmp short loc_130A\nloc_12F1:\nadd [rbp+var_1650], 1\nloc_12F8:\nmov eax, [rbp+var_1650]\ncmp eax, [rbp+var_165C]\njl loc_1238\nloc_130A:\ncmp [rbp+var_1654], 0\njnz loc_13A3\nmov eax, [rbp+var_1658]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nadd rax, rax\nmov rdx, rax\nmov rax, [rbp+var_1668]\nlea rcx, [rdx+rax]\nlea rsi, [rbp+var_1600]\nmov eax, [rbp+var_165C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nadd rax, rsi\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strcpy\nmov eax, [rbp+var_165C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nlea rax, [rax-10h]\nadd rax, rbp\nsub rax, 15BCh\nmov dword ptr [rax], 1\nadd [rbp+var_165C], 1\nloc_13A3:\nadd [rbp+var_1658], 1\nloc_13AA:\nmov eax, [rbp+var_1658]\ncmp eax, [rbp+var_166C]\njl loc_121F\nmov [rbp+var_164C], 0\njmp loc_165D\nloc_13CB:\nmov eax, [rbp+var_164C]\nmov [rbp+var_1648], eax\nmov eax, [rbp+var_164C]\nadd eax, 1\nmov [rbp+var_1644], eax\njmp short loc_144B\nloc_13E8:\nmov eax, [rbp+var_1644]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nlea rax, [rax-10h]\nadd rax, rbp\nsub rax, 15BCh\nmov ecx, [rax]\nmov eax, [rbp+var_1648]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nlea rax, [rax-10h]\nadd rax, rbp\nsub rax, 15BCh\nmov eax, [rax]\ncmp ecx, eax\njle short loc_1444\nmov eax, [rbp+var_1644]\nmov [rbp+var_1648], eax\nloc_1444:\nadd [rbp+var_1644], 1\nloc_144B:\nmov eax, [rbp+var_1644]\ncmp eax, [rbp+var_165C]\njl short loc_13E8\nmov eax, [rbp+var_164C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nlea rax, [rax-10h]\nadd rax, rbp\nsub rax, 15F0h\nmov rcx, [rax]\nmov rbx, [rax+8]\nmov [rbp+var_1640], rcx\nmov [rbp+var_1638], rbx\nmov rcx, [rax+10h]\nmov rbx, [rax+18h]\nmov [rbp+var_1630], rcx\nmov [rbp+var_1628], rbx\nmov rcx, [rax+20h]\nmov rbx, [rax+28h]\nmov [rbp+var_1620], rcx\nmov [rbp+var_1618], rbx\nmov rax, [rax+30h]\nmov [rbp+var_1610], rax\nmov eax, [rbp+var_164C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nlea rax, [rax-10h]\nadd rax, rbp\nlea rdx, [rax-15F0h]\nmov eax, [rbp+var_1648]\nmovsxd rcx, eax\nmov rax, rcx\nshl rax, 3\nsub rax, rcx\nshl rax, 3\nlea rax, [rax-10h]\nadd rax, rbp\nsub rax, 15F0h\nmov rcx, [rax]\nmov rbx, [rax+8]\nmov [rdx], rcx\nmov [rdx+8], rbx\nmov rcx, [rax+10h]\nmov rbx, [rax+18h]\nmov [rdx+10h], rcx\nmov [rdx+18h], rbx\nmov rcx, [rax+20h]\nmov rbx, [rax+28h]\nmov [rdx+20h], rcx\nmov [rdx+28h], rbx\nmov rax, [rax+30h]\nmov [rdx+30h], rax\nmov eax, [rbp+var_1648]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nlea rax, [rax-10h]\nadd rax, rbp\nsub rax, 15F0h\nmov rcx, [rbp+var_1640]\nmov rbx, [rbp+var_1638]\nmov [rax], rcx\nmov [rax+8], rbx\nmov rcx, [rbp+var_1630]\nmov rbx, [rbp+var_1628]\nmov [rax+10h], rcx\nmov [rax+18h], rbx\nmov rcx, [rbp+var_1620]\nmov rbx, [rbp+var_1618]\nmov [rax+20h], rcx\nmov [rax+28h], rbx\nmov rdx, [rbp+var_1610]\nmov [rax+30h], rdx\nlea rcx, [rbp+var_1600]\nmov eax, [rbp+var_164C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nadd rcx, rax\nmov eax, [rbp+var_164C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_1678]\nadd rax, rdx\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strcpy\nmov eax, [rbp+var_164C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_1678]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_164C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nlea rax, [rax-10h]\nadd rax, rbp\nsub rax, 15BCh\nmov eax, [rax]\nmov [rcx+34h], eax\nadd [rbp+var_164C], 1\nloc_165D:\ncmp [rbp+var_164C], 3\njg short loc_1678\nmov eax, [rbp+var_164C]\ncmp eax, [rbp+var_165C]\njl loc_13CB\nloc_1678:\nmov eax, [rbp+var_165C]\nmov edx, 4\ncmp eax, edx\ncmovle edx, eax\nmov rax, [rbp+var_1680]\nmov [rax], edx\nnop\nmov rax, [rbp+var_18]\nsub rax, fs:28h\njz short loc_16A6\ncall ___stack_chk_fail\nloc_16A6:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_11A9(__int64 a1, int a2, __int64 a3, int *a4)\n{\n _QWORD *v4; // rdx\n _QWORD *v5; // rax\n __int64 v6; // rbx\n __int64 v7; // rbx\n __int64 v8; // rbx\n int v9; // edx\n int v13; // [rsp+24h] [rbp-165Ch]\n int i; // [rsp+28h] [rbp-1658h]\n int v15; // [rsp+2Ch] [rbp-1654h]\n int j; // [rsp+30h] [rbp-1650h]\n int k; // [rsp+34h] [rbp-164Ch]\n int v18; // [rsp+38h] [rbp-1648h]\n int m; // [rsp+3Ch] [rbp-1644h]\n __int64 v20; // [rsp+40h] [rbp-1640h]\n __int64 v21; // [rsp+48h] [rbp-1638h]\n __int64 v22; // [rsp+50h] [rbp-1630h]\n __int64 v23; // [rsp+58h] [rbp-1628h]\n __int64 v24; // [rsp+60h] [rbp-1620h]\n __int64 v25; // [rsp+68h] [rbp-1618h]\n __int64 v26; // [rsp+70h] [rbp-1610h]\n _QWORD v27[701]; // [rsp+80h] [rbp-1600h] BYREF\n unsigned __int64 v28; // [rsp+1668h] [rbp-18h]\n\n v28 = __readfsqword(0x28u);\n memset(v27, 0, 0x15E0uLL);\n v13 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v15 = 0;\n for ( j = 0; j < v13; ++j )\n {\n if ( !strcmp((const char *)(50LL * i + a1), (const char *)&v27[7 * j]) )\n {\n ++HIDWORD(v27[7 * j + 6]);\n v15 = 1;\n break;\n }\n }\n if ( !v15 )\n {\n strcpy((char *)&v27[7 * v13], (const char *)(50LL * i + a1));\n HIDWORD(v27[7 * v13++ + 6]) = 1;\n }\n }\n for ( k = 0; k <= 3 && k < v13; ++k )\n {\n v18 = k;\n for ( m = k + 1; m < v13; ++m )\n {\n if ( SHIDWORD(v27[7 * m + 6]) > SHIDWORD(v27[7 * v18 + 6]) )\n v18 = m;\n }\n v20 = v27[7 * k];\n v21 = v27[7 * k + 1];\n v22 = v27[7 * k + 2];\n v23 = v27[7 * k + 3];\n v24 = v27[7 * k + 4];\n v25 = v27[7 * k + 5];\n v26 = v27[7 * k + 6];\n v4 = &v27[7 * k];\n v5 = &v27[7 * v18];\n v6 = v5[1];\n *v4 = *v5;\n v4[1] = v6;\n v7 = v5[3];\n v4[2] = v27[7 * v18 + 2];\n v4[3] = v7;\n v8 = v5[5];\n v4[4] = v5[4];\n v4[5] = v8;\n v4[6] = v5[6];\n *v5 = v20;\n v5[1] = v21;\n v5[2] = v22;\n v5[3] = v23;\n v5[4] = v24;\n v5[5] = v25;\n v5[6] = v26;\n strcpy((char *)(56LL * k + a3), (const char *)&v27[7 * k]);\n *(_DWORD *)(56LL * k + a3 + 52) = HIDWORD(v27[7 * k + 6]);\n }\n v9 = 4;\n if ( v13 <= 4 )\n v9 = v13;\n *a4 = v9;\n return v28 - __readfsqword(0x28u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_11A9(long long a1, int a2, long long a3, int *a4) {\n uint64_t *v4;\n uint64_t *v5;\n long long v6;\n long long v7;\n long long v8;\n int v9;\n int v13;\n int i;\n int v15;\n int j;\n int k;\n int v18;\n int m;\n long long v20;\n long long v21;\n long long v22;\n long long v23;\n long long v24;\n long long v25;\n long long v26;\n uint64_t v27[701];\n unsigned long long v28;\n v28 = __readfsqword(40u);\n memset(v27, 0, 5600uLL);\n v13 = 0;\n for (i = 0; i < a2; ++i) {\n v15 = 0;\n for (j = 0; j < v13; ++j) {\n if (!strcmp((const char *)(50LL * i + a1), (const char *)&v27[7 * j])) {\n ++HIDWORD(v27[7 * j + 6]);\n v15 = 1;\n break;\n }\n }\n if (!v15) {\n strcpy((char *)&v27[7 * v13], (const char *)(50LL * i + a1));\n HIDWORD(v27[7 * v13++ + 6]) = 1;\n }\n }\n for (k = 0; k <= 3 && k < v13; ++k) {\n v18 = k;\n for (m = k + 1; m < v13; ++m) {\n if (SHIDWORD(v27[7 * m + 6]) > SHIDWORD(v27[7 * v18 + 6])) v18 = m;\n }\n v20 = v27[7 * k];\n v21 = v27[7 * k + 1];\n v22 = v27[7 * k + 2];\n v23 = v27[7 * k + 3];\n v24 = v27[7 * k + 4];\n v25 = v27[7 * k + 5];\n v26 = v27[7 * k + 6];\n v4 = &v27[7 * k];\n v5 = &v27[7 * v18];\n v6 = v5[1];\n *v4 = *v5;\n v4[1] = v6;\n v7 = v5[3];\n v4[2] = v27[7 * v18 + 2];\n v4[3] = v7;\n v8 = v5[5];\n v4[4] = v5[4];\n v4[5] = v8;\n v4[6] = v5[6];\n *v5 = v20;\n v5[1] = v21;\n v5[2] = v22;\n v5[3] = v23;\n v5[4] = v24;\n v5[5] = v25;\n v5[6] = v26;\n strcpy((char *)(56LL * k + a3), (const char *)&v27[7 * k]);\n *(uint32_t *)(56LL * k + a3 + 52) = HIDWORD(v27[7 * k + 6]);\n }\n v9 = 4;\n if (v13 <= 4) v9 = v13;\n *a4 = v9;\n return v28 - __readfsqword(40u);\n}", + "ida_pseudo_norm": "unsigned long long func0(long long a1, int a2, long long a3, int *a4) {\n uint64_t *v4;\n uint64_t *v5;\n long long v6;\n long long v7;\n long long v8;\n int v9;\n int v13;\n int i;\n int v15;\n int j;\n int k;\n int v18;\n int m;\n long long v20;\n long long v21;\n long long v22;\n long long v23;\n long long v24;\n long long v25;\n long long v26;\n uint64_t v27[701];\n unsigned long long v28;\n v28 = __readfsqword(40u);\n memset(v27, 0, 5600uLL);\n v13 = 0;\n for (i = 0; i < a2; ++i) {\n v15 = 0;\n for (j = 0; j < v13; ++j) {\n if (!strcmp((const char *)(50LL * i + a1), (const char *)&v27[7 * j])) {\n ++HIDWORD(v27[7 * j + 6]);\n v15 = 1;\n break;\n }\n }\n if (!v15) {\n strcpy((char *)&v27[7 * v13], (const char *)(50LL * i + a1));\n HIDWORD(v27[7 * v13++ + 6]) = 1;\n }\n }\n for (k = 0; k <= 3 && k < v13; ++k) {\n v18 = k;\n for (m = k + 1; m < v13; ++m) {\n if (SHIDWORD(v27[7 * m + 6]) > SHIDWORD(v27[7 * v18 + 6])) v18 = m;\n }\n v20 = v27[7 * k];\n v21 = v27[7 * k + 1];\n v22 = v27[7 * k + 2];\n v23 = v27[7 * k + 3];\n v24 = v27[7 * k + 4];\n v25 = v27[7 * k + 5];\n v26 = v27[7 * k + 6];\n v4 = &v27[7 * k];\n v5 = &v27[7 * v18];\n v6 = v5[1];\n *v4 = *v5;\n v4[1] = v6;\n v7 = v5[3];\n v4[2] = v27[7 * v18 + 2];\n v4[3] = v7;\n v8 = v5[5];\n v4[4] = v5[4];\n v4[5] = v8;\n v4[6] = v5[6];\n *v5 = v20;\n v5[1] = v21;\n v5[2] = v22;\n v5[3] = v23;\n v5[4] = v24;\n v5[5] = v25;\n v5[6] = v26;\n strcpy((char *)(56LL * k + a3), (const char *)&v27[7 * k]);\n *(uint32_t *)(56LL * k + a3 + 52) = HIDWORD(v27[7 * k + 6]);\n }\n v9 = 4;\n if (v13 <= 4) v9 = v13;\n *a4 = v9;\n return v28 - __readfsqword(40u);\n}" + }, + { + "index": 13, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n#define MAX_WORDS 100\n\n#define MAX_WORD_LENGTH 50\n\n\n\ntypedef struct {\n\n char word[MAX_WORD_LENGTH];\n\n int count;\n\n} WordCount;\n\n\n\n", + "func": "void func0(char words[][MAX_WORD_LENGTH], int num_words, WordCount result[],\n int *result_size) {\n WordCount counts[MAX_WORDS] = {0};\n int unique_words = 0;\n for (int i = 0; i < num_words; i++) {\n int found = 0;\n for (int j = 0; j < unique_words; j++) {\n if (strcmp(words[i], counts[j].word) == 0) {\n counts[j].count++;\n found = 1;\n break;\n }\n }\n if (!found) {\n strcpy(counts[unique_words].word, words[i]);\n counts[unique_words].count = 1;\n unique_words++;\n }\n }\n for (int i = 0; i < 4 && i < unique_words; i++) {\n int max_idx = i;\n for (int j = i + 1; j < unique_words; j++) {\n if (counts[j].count > counts[max_idx].count) {\n max_idx = j;\n }\n }\n WordCount tmp = counts[i];\n counts[i] = counts[max_idx];\n counts[max_idx] = tmp;\n strcpy(result[i].word, counts[i].word);\n result[i].count = counts[i].count;\n }\n *result_size = unique_words > 4 ? 4 : unique_words;\n}", + "test": "int main() {\n\n WordCount result[4];\n\n int result_size;\n\n\n\n char data1[][MAX_WORD_LENGTH] = {\"red\",\"green\",\"black\",\"pink\",\"black\",\"white\",\"black\",\"eyes\",\"white\",\"black\",\"orange\",\"pink\",\"pink\",\"red\",\"red\",\"white\",\"orange\",\"white\",\"black\",\"pink\",\"green\",\"green\",\"pink\",\"green\",\"pink\",\"white\",\"orange\",\"orange\",\"red\"};\n\n func0(data1, 29, result, &result_size);\n\n assert(strcmp(result[0].word, \"pink\") == 0 && result[0].count == 6);\n\n assert(strcmp(result[1].word, \"black\") == 0 && result[1].count == 5);\n\n assert(strcmp(result[2].word, \"white\") == 0 && result[2].count == 5);\n\n assert(strcmp(result[3].word, \"red\") == 0 && result[3].count == 4);\n\n \n\n char data2[][MAX_WORD_LENGTH] = {\"one\", \"two\", \"three\", \"four\", \"five\", \"one\", \"two\", \"one\", \"three\", \"one\"};\n\n func0(data2, 10, result, &result_size);\n\n assert(strcmp(result[0].word, \"one\") == 0 && result[0].count == 4);\n\n assert(strcmp(result[1].word, \"two\") == 0 && result[1].count == 2);\n\n assert(strcmp(result[2].word, \"three\") == 0 && result[2].count == 2);\n\n assert(strcmp(result[3].word, \"four\") == 0 && result[3].count == 1);\n\n\n\n char data3[][MAX_WORD_LENGTH] = {\"Facebook\", \"Apple\", \"Amazon\", \"Netflix\", \"Google\", \"Apple\", \"Netflix\", \"Amazon\"};\n\n func0(data3, 8, result, &result_size);\n\n assert(strcmp(result[0].word, \"Apple\") == 0 && result[0].count == 2);\n\n assert(strcmp(result[1].word, \"Amazon\") == 0 && result[1].count == 2);\n\n assert(strcmp(result[2].word, \"Netflix\") == 0 && result[2].count == 2);\n\n assert(strcmp(result[3].word, \"Facebook\") == 0 && result[3].count == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x1000,%rsp\norq $0x0,(%rsp)\nsub $0x658,%rsp\nmov %rdi,%r8\nmov %rdx,0x10(%rsp)\nmov %rcx,0x18(%rsp)\nmov %fs:0x28,%rax\nmov %rax,0x1648(%rsp)\nxor %eax,%eax\nlea 0x60(%rsp),%rdi\nmov $0x2bc,%ecx\nrep stos %rax,%es:(%rdi)\ntest %esi,%esi\njle 13e6 \nmov %r8,%r14\nlea -0x1(%rsi),%eax\nlea (%rax,%rax,4),%rax\nlea (%rax,%rax,4),%rax\nlea 0x32(%r8,%rax,2),%r15\nmov $0x0,%r12d\nlea 0x60(%rsp),%rax\nmov %rax,0x8(%rsp)\njmp 128a \nmovslq %ebx,%rbx\nlea 0x0(,%rbx,8),%rax\nmov %rax,%rdx\nsub %rbx,%rdx\nmov 0x94(%rsp,%rdx,8),%eax\nadd $0x1,%eax\nmov %eax,0x94(%rsp,%rdx,8)\njmp 1281 \nmovslq %r12d,%rbp\nlea 0x0(,%rbp,8),%rbx\nmov %rbx,%rax\nsub %rbp,%rax\nmov 0x8(%rsp),%rcx\nlea (%rcx,%rax,8),%rdi\nmov $0x32,%edx\nmov %r14,%rsi\ncallq 10b0 <__strcpy_chk@plt>\nsub %rbp,%rbx\nmovl $0x1,0x94(%rsp,%rbx,8)\nadd $0x1,%r12d\nadd $0x32,%r14\ncmp %r15,%r14\nje 12bd \nmov %r14,%r13\nlea 0x60(%rsp),%rbp\nmov $0x0,%ebx\ntest %r12d,%r12d\njle 1248 \nmov %rbp,%rsi\nmov %r13,%rdi\ncallq 10a0 \ntest %eax,%eax\nje 1224 \nadd $0x1,%ebx\nadd $0x38,%rbp\ncmp %r12d,%ebx\njne 129c \njmp 1248 \ntest %r12d,%r12d\njle 1490 \nlea 0x60(%rsp),%rbx\nmov 0x10(%rsp),%r13\nmov $0x0,%ebp\njmpq 13ab \nmov (%rbx),%r14\nmov 0x8(%rbx),%r15\nmov %r14,0x20(%rsp)\nmov %r15,0x28(%rsp)\nmov 0x10(%rbx),%r10\nmov 0x18(%rbx),%r11\nmov %r10,0x30(%rsp)\nmov %r11,0x38(%rsp)\nmov 0x20(%rbx),%r8\nmov 0x28(%rbx),%r9\nmov %r8,0x40(%rsp)\nmov %r9,0x48(%rsp)\nmov 0x30(%rbx),%rdi\nmov %rdi,0x50(%rsp)\nmovslq %ecx,%rcx\nlea 0x0(,%rcx,8),%rax\nmov %rax,%rdx\nsub %rcx,%rdx\nshl $0x3,%rdx\nlea 0x60(%rsp,%rdx,1),%rsi\nmovdqu 0x60(%rsp,%rdx,1),%xmm0\nmovups %xmm0,(%rbx)\nmovdqu 0x10(%rsi),%xmm1\nmovups %xmm1,0x10(%rbx)\nmovdqu 0x20(%rsi),%xmm2\nmovups %xmm2,0x20(%rbx)\nmov 0x30(%rsi),%rdx\nmov %rdx,0x30(%rbx)\nsub %rcx,%rax\nshl $0x3,%rax\nmov %r14,0x60(%rsp,%rax,1)\nmov %r15,0x68(%rsp,%rax,1)\nmov %r10,0x10(%rsi)\nmov %r11,0x18(%rsi)\nmov %r8,0x20(%rsi)\nmov %r9,0x28(%rsi)\nmov %rdi,0x30(%rsi)\nmov $0x32,%edx\nmov %rbx,%rsi\nmov %r13,%rdi\ncallq 10b0 <__strcpy_chk@plt>\nmov 0x34(%rbx),%eax\nmov %eax,0x34(%r13)\nadd $0x38,%rbx\nadd $0x38,%r13\ncmp $0x3,%ebp\njg 1490 \ncmp %ebp,%r12d\njle 1490 \nmov %ebp,%ecx\nadd $0x1,%ebp\ncmp %ebp,%r12d\nje 13f1 \nmov %rbx,%rsi\nmov %ebp,%eax\nmovslq %ecx,%rdi\nlea 0x0(,%rdi,8),%rdx\nsub %rdi,%rdx\nmov 0x94(%rsp,%rdx,8),%edi\ncmp %edi,0x6c(%rsi)\ncmovg %eax,%ecx\nadd $0x1,%eax\nadd $0x38,%rsi\ncmp %eax,%r12d\njne 13ba \njmpq 12da \nmov $0x0,%r12d\njmpq 1490 \nmovslq %ecx,%rbp\nlea 0x0(,%rbp,8),%rbx\nmov %rbx,%rax\nsub %rbp,%rax\nshl $0x3,%rax\nlea 0x60(%rsp,%rax,1),%rdx\nmov 0x60(%rsp,%rax,1),%r10\nmov 0x68(%rsp,%rax,1),%r11\nmov %r10,0x20(%rsp)\nmov %r11,0x28(%rsp)\nmov 0x10(%rdx),%r8\nmov 0x18(%rdx),%r9\nmov %r8,0x30(%rsp)\nmov %r9,0x38(%rsp)\nmov 0x20(%rdx),%rsi\nmov 0x28(%rdx),%rdi\nmov %rsi,0x40(%rsp)\nmov %rdi,0x48(%rsp)\nmov 0x30(%rdx),%rcx\nmov %rcx,0x50(%rsp)\nmov %r8,0x10(%rdx)\nmov %r9,0x18(%rdx)\nmov %rsi,0x20(%rdx)\nmov %rdi,0x28(%rdx)\nmov %rcx,0x30(%rdx)\nmov %rbx,%rax\nsub %rbp,%rax\nshl $0x3,%rax\nmov 0x10(%rsp),%r13\nadd %rax,%r13\nmov %rdx,%rsi\nmov $0x32,%edx\nmov %r13,%rdi\ncallq 10b0 <__strcpy_chk@plt>\nsub %rbp,%rbx\nmov 0x94(%rsp,%rbx,8),%eax\nmov %eax,0x34(%r13)\ncmp $0x4,%r12d\nmov $0x4,%eax\ncmovg %eax,%r12d\nmov 0x18(%rsp),%rax\nmov %r12d,(%rax)\nmov 0x1648(%rsp),%rax\nxor %fs:0x28,%rax\njne 14ca \nadd $0x1658,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\ncallq 1080 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 1000h\nor [rsp+1030h+var_1030], 0\nsub rsp, 658h\nmov r8, rdi\nmov [rsp+1688h+var_1678], rdx\nmov [rsp+1688h+var_1670], rcx\nmov rax, fs:28h\nmov [rsp+1688h+var_40], rax\nxor eax, eax\nlea rdi, [rsp+1688h+s2]\nmov ecx, 2BCh\nrep stosq\ntest esi, esi\njle loc_13F5\nmov r13, r8\nmovsxd rsi, esi\nlea rax, [rsi+rsi*4]\nlea rax, [rax+rax*4]\nlea r14, [r8+rax*2]\nmov r15d, 0\nlea rax, [rsp+1688h+s2]\nmov [rsp+1688h+var_1680], rax\njmp short loc_1289\nloc_1223:\nmovsxd rbx, ebx\nlea rax, ds:0[rbx*8]\nmov rdx, rax\nsub rdx, rbx\nmov eax, [rsp+rdx*8+1688h+var_15F4]\nadd eax, 1\nmov [rsp+rdx*8+1688h+var_15F4], eax\njmp short loc_1280\nloc_1247:\nmovsxd rbp, r15d\nlea rbx, ds:0[rbp*8]\nmov rax, rbx\nsub rax, rbp\nmov rdi, [rsp+1688h+var_1680]\nlea rdi, [rdi+rax*8]\nmov edx, 32h ; '2'\nmov rsi, r13\ncall ___strcpy_chk\nsub rbx, rbp\nmov [rsp+rbx*8+1688h+var_15F4], 1\nadd r15d, 1\nloc_1280:\nadd r13, 32h ; '2'\ncmp r13, r14\njz short loc_12BC\nloc_1289:\nmov r12, r13\nlea rbp, [rsp+1688h+s2]\nmov ebx, 0\ntest r15d, r15d\njle short loc_1247\nloc_129B:\nmov rsi, rbp; s2\nmov rdi, r12; s1\ncall _strcmp\ntest eax, eax\njz loc_1223\nadd ebx, 1\nadd rbp, 38h ; '8'\ncmp ebx, r15d\njnz short loc_129B\njmp short loc_1247\nloc_12BC:\ntest r15d, r15d\njle loc_1400\nlea r12, [rsp+1688h+s2]\nmov r14, [rsp+1688h+var_1678]\nmov r13d, 0\njmp loc_13D1\nloc_12DA:\nmov ebx, ebp\nloc_12DC:\nmovsxd rsi, edx\nlea rax, ds:0[rsi*8]\nsub rax, rsi\nmov eax, [rsp+rax*8+1688h+var_15F4]\ncmp [rcx+6Ch], eax\ncmovg edx, ebx\nlea ebp, [rbx+1]\nadd rcx, 38h ; '8'\ncmp r15d, ebp\njnz short loc_12DA\nmovdqu xmm0, xmmword ptr [r12]\nmovaps [rsp+1688h+var_1668], xmm0\nmov r10, [r12+10h]\nmov r11, [r12+18h]\nmov [rsp+1688h+var_1658], r10\nmov [rsp+1688h+var_1650], r11\nmov r8, [r12+20h]\nmov r9, [r12+28h]\nmov [rsp+1688h+var_1648], r8\nmov [rsp+1688h+var_1640], r9\nmov rdi, [r12+30h]\nmov [rsp+1688h+var_1638], rdi\nmovsxd rdx, edx\nlea rax, ds:0[rdx*8]\nmov rcx, rax\nsub rcx, rdx\nshl rcx, 3\nlea rsi, [rsp+rcx+1688h+s2]\nmovdqu xmm1, xmmword ptr [rsp+rcx+1688h+s2]\nmovups xmmword ptr [r12], xmm1\nmovdqu xmm2, xmmword ptr [rsi+10h]\nmovups xmmword ptr [r12+10h], xmm2\nmovdqu xmm3, xmmword ptr [rsi+20h]\nmovups xmmword ptr [r12+20h], xmm3\nmov rcx, [rsi+30h]\nmov [r12+30h], rcx\nsub rax, rdx\nshl rax, 3\nmovups xmmword ptr [rsp+rax+1688h+s2], xmm0\nmov [rsi+10h], r10\nmov [rsi+18h], r11\nmov [rsi+20h], r8\nmov [rsi+28h], r9\nmov [rsi+30h], rdi\nmov edx, 32h ; '2'\nmov rsi, r12\nmov rdi, r14\ncall ___strcpy_chk\nmov eax, [r12+34h]\nmov [r14+34h], eax\nadd r12, 38h ; '8'\nadd r14, 38h ; '8'\ncmp r13d, 3\njg short loc_13ED\ncmp dword ptr [rsp+1688h+var_1680], ebx\njge short loc_13ED\nloc_13D1:\nmov edx, r13d\nmov dword ptr [rsp+1688h+var_1680], r13d\nadd r13d, 1\ncmp r15d, r13d\njz short loc_1408\nmov rcx, r12\nmov ebx, r13d\njmp loc_12DC\nloc_13ED:\nmov r13d, ebp\njmp loc_14AA\nloc_13F5:\nmov r13d, 0\njmp loc_14AA\nloc_1400:\nmov r13d, r15d\njmp loc_14AA\nloc_1408:\nmovsxd r15, dword ptr [rsp+1688h+var_1680]\nlea rbx, ds:0[r15*8]\nmov rax, rbx\nsub rax, r15\nshl rax, 3\nlea rdx, [rsp+rax+1688h+s2]\nmov r10, qword ptr [rsp+rax+1688h+s2]\nmov r11, qword ptr [rsp+rax+1688h+s2+8]\nmov qword ptr [rsp+1688h+var_1668], r10\nmov qword ptr [rsp+1688h+var_1668+8], r11\nmov r8, [rdx+10h]\nmov r9, [rdx+18h]\nmov [rsp+1688h+var_1658], r8\nmov [rsp+1688h+var_1650], r9\nmov rsi, [rdx+20h]\nmov rdi, [rdx+28h]\nmov [rsp+1688h+var_1648], rsi\nmov [rsp+1688h+var_1640], rdi\nmov rcx, [rdx+30h]\nmov [rsp+1688h+var_1638], rcx\nmov [rdx+10h], r8\nmov [rdx+18h], r9\nmov [rdx+20h], rsi\nmov [rdx+28h], rdi\nmov [rdx+30h], rcx\nmov rax, rbx\nsub rax, r15\nshl rax, 3\nmov r12, [rsp+1688h+var_1678]\nadd r12, rax\nmov rsi, rdx\nmov edx, 32h ; '2'\nmov rdi, r12\ncall ___strcpy_chk\nsub rbx, r15\nmov eax, [rsp+rbx*8+1688h+var_15F4]\nmov [r12+34h], eax\nloc_14AA:\nmov eax, 4\ncmp r13d, eax\ncmovle eax, r13d\nmov rdi, [rsp+1688h+var_1670]\nmov [rdi], eax\nmov rax, [rsp+1688h+var_40]\nsub rax, fs:28h\njnz short loc_14E2\nadd rsp, 1658h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14E2:\ncall ___stack_chk_fail", + "ida_pseudo": "unsigned __int64 __fastcall func0(char *s1, int a2, __int64 a3, int *a4)\n{\n const char *v4; // r13\n int v5; // r15d\n const char *v6; // rbp\n int v7; // ebx\n __m128i *v8; // r12\n __int64 v9; // r14\n int v10; // r13d\n int i; // ebx\n int v12; // edx\n __m128i *v13; // rcx\n __int64 v14; // r10\n __int64 v15; // r8\n __int64 v16; // rdi\n __m128i *v17; // rsi\n _QWORD *v18; // rdx\n __int64 v19; // rsi\n __int64 v20; // rcx\n int v21; // eax\n int v23; // [rsp+8h] [rbp-1680h]\n __m128i v26; // [rsp+20h] [rbp-1668h]\n __int64 v27; // [rsp+38h] [rbp-1650h]\n __int64 v28; // [rsp+38h] [rbp-1650h]\n __int64 v29; // [rsp+48h] [rbp-1640h]\n __int64 v30; // [rsp+48h] [rbp-1640h]\n _QWORD s2[701]; // [rsp+60h] [rbp-1628h] BYREF\n unsigned __int64 v32; // [rsp+1648h] [rbp-40h]\n\n v32 = __readfsqword(0x28u);\n memset(s2, 0, 0x15E0uLL);\n if ( a2 <= 0 )\n {\n v10 = 0;\n }\n else\n {\n v4 = s1;\n v5 = 0;\n do\n {\n v6 = (const char *)s2;\n v7 = 0;\n if ( v5 <= 0 )\n {\nLABEL_4:\n __strcpy_chk(&s2[7 * v5], v4, 50LL);\n HIDWORD(s2[7 * v5++ + 6]) = 1;\n }\n else\n {\n while ( strcmp(v4, v6) )\n {\n ++v7;\n v6 += 56;\n if ( v7 == v5 )\n goto LABEL_4;\n }\n ++HIDWORD(s2[7 * v7 + 6]);\n }\n v4 += 50;\n }\n while ( v4 != &s1[50 * a2] );\n if ( v5 <= 0 )\n {\n v10 = v5;\n }\n else\n {\n v8 = (__m128i *)s2;\n v9 = a3;\n v10 = 0;\n while ( 1 )\n {\n v12 = v10;\n v23 = v10++;\n if ( v5 == v10 )\n break;\n v13 = v8;\n for ( i = v10; ; ++i )\n {\n if ( v13[6].m128i_i32[3] > SHIDWORD(s2[7 * v12 + 6]) )\n v12 = i;\n v13 = (__m128i *)((char *)v13 + 56);\n if ( v5 == i + 1 )\n break;\n }\n v26 = _mm_loadu_si128(v8);\n v14 = v8[1].m128i_i64[0];\n v27 = v8[1].m128i_i64[1];\n v15 = v8[2].m128i_i64[0];\n v29 = v8[2].m128i_i64[1];\n v16 = v8[3].m128i_i64[0];\n v17 = (__m128i *)&s2[7 * v12];\n *v8 = _mm_loadu_si128(v17);\n v8[1] = _mm_loadu_si128(v17 + 1);\n v8[2] = _mm_loadu_si128(v17 + 2);\n v8[3].m128i_i64[0] = v17[3].m128i_i64[0];\n *v17 = v26;\n v17[1].m128i_i64[0] = v14;\n v17[1].m128i_i64[1] = v27;\n v17[2].m128i_i64[0] = v15;\n v17[2].m128i_i64[1] = v29;\n v17[3].m128i_i64[0] = v16;\n __strcpy_chk(v9, v8, 50LL);\n *(_DWORD *)(v9 + 52) = v8[3].m128i_i32[1];\n v8 = (__m128i *)((char *)v8 + 56);\n v9 += 56LL;\n if ( v10 > 3 || v23 >= i )\n {\n v10 = i + 1;\n goto LABEL_24;\n }\n }\n v18 = &s2[7 * v23];\n v28 = v18[3];\n v19 = v18[4];\n v30 = v18[5];\n v20 = v18[6];\n v18[2] = v18[2];\n v18[3] = v28;\n v18[4] = v19;\n v18[5] = v30;\n v18[6] = v20;\n __strcpy_chk(56LL * v23 + a3, v18, 50LL);\n *(_DWORD *)(56LL * v23 + a3 + 52) = HIDWORD(s2[7 * v23 + 6]);\n }\n }\nLABEL_24:\n v21 = 4;\n if ( v10 <= 4 )\n v21 = v10;\n *a4 = v21;\n return v32 - __readfsqword(0x28u);\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 1000h\nor [rsp+1030h+var_1030], 0\nsub rsp, 658h\nmov r8, rdi\nmov [rsp+1688h+var_1678], rdx\nmov [rsp+1688h+var_1670], rcx\nmov rax, fs:28h\nmov [rsp+1688h+var_40], rax\nxor eax, eax\nlea rdi, [rsp+1688h+s2]\nmov ecx, 2BCh\nrep stosq\ntest esi, esi\njle loc_13F5\nmov r13, r8\nmovsxd rsi, esi\nlea rax, [rsi+rsi*4]\nlea rax, [rax+rax*4]\nlea r14, [r8+rax*2]\nmov r15d, 0\nlea rax, [rsp+1688h+s2]\nmov [rsp+1688h+var_1680], rax\njmp short loc_1289\nloc_1223:\nmovsxd rbx, ebx\nlea rax, ds:0[rbx*8]\nmov rdx, rax\nsub rdx, rbx\nmov eax, [rsp+rdx*8+1688h+var_15F4]\nadd eax, 1\nmov [rsp+rdx*8+1688h+var_15F4], eax\njmp short loc_1280\nloc_1247:\nmovsxd rbp, r15d\nlea rbx, ds:0[rbp*8]\nmov rax, rbx\nsub rax, rbp\nmov rdi, [rsp+1688h+var_1680]\nlea rdi, [rdi+rax*8]\nmov edx, 32h ; '2'\nmov rsi, r13\ncall ___strcpy_chk\nsub rbx, rbp\nmov [rsp+rbx*8+1688h+var_15F4], 1\nadd r15d, 1\nloc_1280:\nadd r13, 32h ; '2'\ncmp r13, r14\njz short loc_12BC\nloc_1289:\nmov r12, r13\nlea rbp, [rsp+1688h+s2]\nmov ebx, 0\ntest r15d, r15d\njle short loc_1247\nloc_129B:\nmov rsi, rbp; s2\nmov rdi, r12; s1\ncall _strcmp\ntest eax, eax\njz loc_1223\nadd ebx, 1\nadd rbp, 38h ; '8'\ncmp ebx, r15d\njnz short loc_129B\njmp short loc_1247\nloc_12BC:\ntest r15d, r15d\njle loc_1400\nlea r12, [rsp+1688h+s2]\nmov r14, [rsp+1688h+var_1678]\nmov r13d, 0\njmp loc_13D1\nloc_12DA:\nmov ebx, ebp\nloc_12DC:\nmovsxd rsi, edx\nlea rax, ds:0[rsi*8]\nsub rax, rsi\nmov eax, [rsp+rax*8+1688h+var_15F4]\ncmp [rcx+6Ch], eax\ncmovg edx, ebx\nlea ebp, [rbx+1]\nadd rcx, 38h ; '8'\ncmp r15d, ebp\njnz short loc_12DA\nmovdqu xmm0, xmmword ptr [r12]\nmovaps [rsp+1688h+var_1668], xmm0\nmov r10, [r12+10h]\nmov r11, [r12+18h]\nmov [rsp+1688h+var_1658], r10\nmov [rsp+1688h+var_1650], r11\nmov r8, [r12+20h]\nmov r9, [r12+28h]\nmov [rsp+1688h+var_1648], r8\nmov [rsp+1688h+var_1640], r9\nmov rdi, [r12+30h]\nmov [rsp+1688h+var_1638], rdi\nmovsxd rdx, edx\nlea rax, ds:0[rdx*8]\nmov rcx, rax\nsub rcx, rdx\nshl rcx, 3\nlea rsi, [rsp+rcx+1688h+s2]\nmovdqu xmm1, xmmword ptr [rsp+rcx+1688h+s2]\nmovups xmmword ptr [r12], xmm1\nmovdqu xmm2, xmmword ptr [rsi+10h]\nmovups xmmword ptr [r12+10h], xmm2\nmovdqu xmm3, xmmword ptr [rsi+20h]\nmovups xmmword ptr [r12+20h], xmm3\nmov rcx, [rsi+30h]\nmov [r12+30h], rcx\nsub rax, rdx\nshl rax, 3\nmovups xmmword ptr [rsp+rax+1688h+s2], xmm0\nmov [rsi+10h], r10\nmov [rsi+18h], r11\nmov [rsi+20h], r8\nmov [rsi+28h], r9\nmov [rsi+30h], rdi\nmov edx, 32h ; '2'\nmov rsi, r12\nmov rdi, r14\ncall ___strcpy_chk\nmov eax, [r12+34h]\nmov [r14+34h], eax\nadd r12, 38h ; '8'\nadd r14, 38h ; '8'\ncmp r13d, 3\njg short loc_13ED\ncmp dword ptr [rsp+1688h+var_1680], ebx\njge short loc_13ED\nloc_13D1:\nmov edx, r13d\nmov dword ptr [rsp+1688h+var_1680], r13d\nadd r13d, 1\ncmp r15d, r13d\njz short loc_1408\nmov rcx, r12\nmov ebx, r13d\njmp loc_12DC\nloc_13ED:\nmov r13d, ebp\njmp loc_14AA\nloc_13F5:\nmov r13d, 0\njmp loc_14AA\nloc_1400:\nmov r13d, r15d\njmp loc_14AA\nloc_1408:\nmovsxd r15, dword ptr [rsp+1688h+var_1680]\nlea rbx, ds:0[r15*8]\nmov rax, rbx\nsub rax, r15\nshl rax, 3\nlea rdx, [rsp+rax+1688h+s2]\nmov r10, qword ptr [rsp+rax+1688h+s2]\nmov r11, qword ptr [rsp+rax+1688h+s2+8]\nmov qword ptr [rsp+1688h+var_1668], r10\nmov qword ptr [rsp+1688h+var_1668+8], r11\nmov r8, [rdx+10h]\nmov r9, [rdx+18h]\nmov [rsp+1688h+var_1658], r8\nmov [rsp+1688h+var_1650], r9\nmov rsi, [rdx+20h]\nmov rdi, [rdx+28h]\nmov [rsp+1688h+var_1648], rsi\nmov [rsp+1688h+var_1640], rdi\nmov rcx, [rdx+30h]\nmov [rsp+1688h+var_1638], rcx\nmov [rdx+10h], r8\nmov [rdx+18h], r9\nmov [rdx+20h], rsi\nmov [rdx+28h], rdi\nmov [rdx+30h], rcx\nmov rax, rbx\nsub rax, r15\nshl rax, 3\nmov r12, [rsp+1688h+var_1678]\nadd r12, rax\nmov rsi, rdx\nmov edx, 32h ; '2'\nmov rdi, r12\ncall ___strcpy_chk\nsub rbx, r15\nmov eax, [rsp+rbx*8+1688h+var_15F4]\nmov [r12+34h], eax\nloc_14AA:\nmov eax, 4\ncmp r13d, eax\ncmovle eax, r13d\nmov rdi, [rsp+1688h+var_1670]\nmov [rdi], eax\nmov rax, [rsp+1688h+var_40]\nsub rax, fs:28h\njnz short loc_14E2\nadd rsp, 1658h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14E2:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_11A9(char *s1, int a2, __int64 a3, int *a4)\n{\n const char *v4; // r13\n int v5; // r15d\n const char *v6; // rbp\n int v7; // ebx\n __m128i *v8; // r12\n __int64 v9; // r14\n int v10; // r13d\n int i; // ebx\n int v12; // edx\n __m128i *v13; // rcx\n __int64 v14; // r10\n __int64 v15; // r8\n __int64 v16; // rdi\n __m128i *v17; // rsi\n _QWORD *v18; // rdx\n __int64 v19; // rsi\n __int64 v20; // rcx\n int v21; // eax\n int v23; // [rsp+8h] [rbp-1680h]\n __m128i v26; // [rsp+20h] [rbp-1668h]\n __int64 v27; // [rsp+38h] [rbp-1650h]\n __int64 v28; // [rsp+38h] [rbp-1650h]\n __int64 v29; // [rsp+48h] [rbp-1640h]\n __int64 v30; // [rsp+48h] [rbp-1640h]\n _QWORD s2[701]; // [rsp+60h] [rbp-1628h] BYREF\n unsigned __int64 v32; // [rsp+1648h] [rbp-40h]\n\n v32 = __readfsqword(0x28u);\n memset(s2, 0, 0x15E0uLL);\n if ( a2 <= 0 )\n {\n v10 = 0;\n }\n else\n {\n v4 = s1;\n v5 = 0;\n do\n {\n v6 = (const char *)s2;\n v7 = 0;\n if ( v5 <= 0 )\n {\nLABEL_4:\n __strcpy_chk(&s2[7 * v5], v4, 50LL);\n HIDWORD(s2[7 * v5++ + 6]) = 1;\n }\n else\n {\n while ( strcmp(v4, v6) )\n {\n ++v7;\n v6 += 56;\n if ( v7 == v5 )\n goto LABEL_4;\n }\n ++HIDWORD(s2[7 * v7 + 6]);\n }\n v4 += 50;\n }\n while ( v4 != &s1[50 * a2] );\n if ( v5 <= 0 )\n {\n v10 = v5;\n }\n else\n {\n v8 = (__m128i *)s2;\n v9 = a3;\n v10 = 0;\n while ( 1 )\n {\n v12 = v10;\n v23 = v10++;\n if ( v5 == v10 )\n break;\n v13 = v8;\n for ( i = v10; ; ++i )\n {\n if ( v13[6].m128i_i32[3] > SHIDWORD(s2[7 * v12 + 6]) )\n v12 = i;\n v13 = (__m128i *)((char *)v13 + 56);\n if ( v5 == i + 1 )\n break;\n }\n v26 = _mm_loadu_si128(v8);\n v14 = v8[1].m128i_i64[0];\n v27 = v8[1].m128i_i64[1];\n v15 = v8[2].m128i_i64[0];\n v29 = v8[2].m128i_i64[1];\n v16 = v8[3].m128i_i64[0];\n v17 = (__m128i *)&s2[7 * v12];\n *v8 = _mm_loadu_si128(v17);\n v8[1] = _mm_loadu_si128(v17 + 1);\n v8[2] = _mm_loadu_si128(v17 + 2);\n v8[3].m128i_i64[0] = v17[3].m128i_i64[0];\n *v17 = v26;\n v17[1].m128i_i64[0] = v14;\n v17[1].m128i_i64[1] = v27;\n v17[2].m128i_i64[0] = v15;\n v17[2].m128i_i64[1] = v29;\n v17[3].m128i_i64[0] = v16;\n __strcpy_chk(v9, v8, 50LL);\n *(_DWORD *)(v9 + 52) = v8[3].m128i_i32[1];\n v8 = (__m128i *)((char *)v8 + 56);\n v9 += 56LL;\n if ( v10 > 3 || v23 >= i )\n {\n v10 = i + 1;\n goto LABEL_24;\n }\n }\n v18 = &s2[7 * v23];\n v28 = v18[3];\n v19 = v18[4];\n v30 = v18[5];\n v20 = v18[6];\n v18[2] = v18[2];\n v18[3] = v28;\n v18[4] = v19;\n v18[5] = v30;\n v18[6] = v20;\n __strcpy_chk(56LL * v23 + a3, v18, 50LL);\n *(_DWORD *)(56LL * v23 + a3 + 52) = HIDWORD(s2[7 * v23 + 6]);\n }\n }\nLABEL_24:\n v21 = 4;\n if ( v10 <= 4 )\n v21 = v10;\n *a4 = v21;\n return v32 - __readfsqword(0x28u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_11A9(char *s1, int a2, long long a3, int *a4) {\n const char *v4;\n int v5;\n const char *v6;\n int v7;\n __m128i *v8;\n long long v9;\n int v10;\n int i;\n int v12;\n __m128i *v13;\n long long v14;\n long long v15;\n long long v16;\n __m128i *v17;\n uint64_t *v18;\n long long v19;\n long long v20;\n int v21;\n int v23;\n __m128i v26;\n long long v27;\n long long v28;\n long long v29;\n long long v30;\n uint64_t s2[701];\n unsigned long long v32;\n v32 = __readfsqword(40u);\n memset(s2, 0, 5600uLL);\n if (a2 <= 0) {\n v10 = 0;\n } else {\n v4 = s1;\n v5 = 0;\n do {\n v6 = (const char *)s2;\n v7 = 0;\n if (v5 <= 0) {\n LABEL_4:\n __strcpy_chk(&s2[7 * v5], v4, 50LL);\n HIDWORD(s2[7 * v5++ + 6]) = 1;\n } else {\n while (strcmp(v4, v6)) {\n ++v7;\n v6 += 56;\n if (v7 == v5) goto LABEL_4;\n }\n ++HIDWORD(s2[7 * v7 + 6]);\n }\n v4 += 50;\n } while (v4 != &s1[50 * a2]);\n if (v5 <= 0) {\n v10 = v5;\n } else {\n v8 = (__m128i *)s2;\n v9 = a3;\n v10 = 0;\n while (1) {\n v12 = v10;\n v23 = v10++;\n if (v5 == v10) break;\n v13 = v8;\n for (i = v10;; ++i) {\n if (v13[6].m128i_i32[3] > SHIDWORD(s2[7 * v12 + 6])) v12 = i;\n v13 = (__m128i *)((char *)v13 + 56);\n if (v5 == i + 1) break;\n }\n v26 = _mm_loadu_si128(v8);\n v14 = v8[1].m128i_i64[0];\n v27 = v8[1].m128i_i64[1];\n v15 = v8[2].m128i_i64[0];\n v29 = v8[2].m128i_i64[1];\n v16 = v8[3].m128i_i64[0];\n v17 = (__m128i *)&s2[7 * v12];\n *v8 = _mm_loadu_si128(v17);\n v8[1] = _mm_loadu_si128(v17 + 1);\n v8[2] = _mm_loadu_si128(v17 + 2);\n v8[3].m128i_i64[0] = v17[3].m128i_i64[0];\n *v17 = v26;\n v17[1].m128i_i64[0] = v14;\n v17[1].m128i_i64[1] = v27;\n v17[2].m128i_i64[0] = v15;\n v17[2].m128i_i64[1] = v29;\n v17[3].m128i_i64[0] = v16;\n __strcpy_chk(v9, v8, 50LL);\n *(uint32_t *)(v9 + 52) = v8[3].m128i_i32[1];\n v8 = (__m128i *)((char *)v8 + 56);\n v9 += 56LL;\n if (v10 > 3 || v23 >= i) {\n v10 = i + 1;\n goto LABEL_24;\n }\n }\n v18 = &s2[7 * v23];\n v28 = v18[3];\n v19 = v18[4];\n v30 = v18[5];\n v20 = v18[6];\n v18[2] = v18[2];\n v18[3] = v28;\n v18[4] = v19;\n v18[5] = v30;\n v18[6] = v20;\n __strcpy_chk(56LL * v23 + a3, v18, 50LL);\n *(uint32_t *)(56LL * v23 + a3 + 52) = HIDWORD(s2[7 * v23 + 6]);\n }\n }\nLABEL_24:\n v21 = 4;\n if (v10 <= 4) v21 = v10;\n *a4 = v21;\n return v32 - __readfsqword(40u);\n}", + "ida_pseudo_norm": "unsigned long long func0(char *s1, int a2, long long a3, int *a4) {\n const char *v4;\n int v5;\n const char *v6;\n int v7;\n __m128i *v8;\n long long v9;\n int v10;\n int i;\n int v12;\n __m128i *v13;\n long long v14;\n long long v15;\n long long v16;\n __m128i *v17;\n uint64_t *v18;\n long long v19;\n long long v20;\n int v21;\n int v23;\n __m128i v26;\n long long v27;\n long long v28;\n long long v29;\n long long v30;\n uint64_t s2[701];\n unsigned long long v32;\n v32 = __readfsqword(40u);\n memset(s2, 0, 5600uLL);\n if (a2 <= 0) {\n v10 = 0;\n } else {\n v4 = s1;\n v5 = 0;\n do {\n v6 = (const char *)s2;\n v7 = 0;\n if (v5 <= 0) {\n LABEL_4:\n __strcpy_chk(&s2[7 * v5], v4, 50LL);\n HIDWORD(s2[7 * v5++ + 6]) = 1;\n } else {\n while (strcmp(v4, v6)) {\n ++v7;\n v6 += 56;\n if (v7 == v5) goto LABEL_4;\n }\n ++HIDWORD(s2[7 * v7 + 6]);\n }\n v4 += 50;\n } while (v4 != &s1[50 * a2]);\n if (v5 <= 0) {\n v10 = v5;\n } else {\n v8 = (__m128i *)s2;\n v9 = a3;\n v10 = 0;\n while (1) {\n v12 = v10;\n v23 = v10++;\n if (v5 == v10) break;\n v13 = v8;\n for (i = v10;; ++i) {\n if (v13[6].m128i_i32[3] > SHIDWORD(s2[7 * v12 + 6])) v12 = i;\n v13 = (__m128i *)((char *)v13 + 56);\n if (v5 == i + 1) break;\n }\n v26 = _mm_loadu_si128(v8);\n v14 = v8[1].m128i_i64[0];\n v27 = v8[1].m128i_i64[1];\n v15 = v8[2].m128i_i64[0];\n v29 = v8[2].m128i_i64[1];\n v16 = v8[3].m128i_i64[0];\n v17 = (__m128i *)&s2[7 * v12];\n *v8 = _mm_loadu_si128(v17);\n v8[1] = _mm_loadu_si128(v17 + 1);\n v8[2] = _mm_loadu_si128(v17 + 2);\n v8[3].m128i_i64[0] = v17[3].m128i_i64[0];\n *v17 = v26;\n v17[1].m128i_i64[0] = v14;\n v17[1].m128i_i64[1] = v27;\n v17[2].m128i_i64[0] = v15;\n v17[2].m128i_i64[1] = v29;\n v17[3].m128i_i64[0] = v16;\n __strcpy_chk(v9, v8, 50LL);\n *(uint32_t *)(v9 + 52) = v8[3].m128i_i32[1];\n v8 = (__m128i *)((char *)v8 + 56);\n v9 += 56LL;\n if (v10 > 3 || v23 >= i) {\n v10 = i + 1;\n goto LABEL_24;\n }\n }\n v18 = &s2[7 * v23];\n v28 = v18[3];\n v19 = v18[4];\n v30 = v18[5];\n v20 = v18[6];\n v18[2] = v18[2];\n v18[3] = v28;\n v18[4] = v19;\n v18[5] = v30;\n v18[6] = v20;\n __strcpy_chk(56LL * v23 + a3, v18, 50LL);\n *(uint32_t *)(56LL * v23 + a3 + 52) = HIDWORD(s2[7 * v23 + 6]);\n }\n }\nLABEL_24:\n v21 = 4;\n if (v10 <= 4) v21 = v10;\n *a4 = v21;\n return v32 - __readfsqword(40u);\n}" + }, + { + "index": 13, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n#define MAX_WORDS 100\n\n#define MAX_WORD_LENGTH 50\n\n\n\ntypedef struct {\n\n char word[MAX_WORD_LENGTH];\n\n int count;\n\n} WordCount;\n\n\n\n", + "func": "void func0(char words[][MAX_WORD_LENGTH], int num_words, WordCount result[],\n int *result_size) {\n WordCount counts[MAX_WORDS] = {0};\n int unique_words = 0;\n for (int i = 0; i < num_words; i++) {\n int found = 0;\n for (int j = 0; j < unique_words; j++) {\n if (strcmp(words[i], counts[j].word) == 0) {\n counts[j].count++;\n found = 1;\n break;\n }\n }\n if (!found) {\n strcpy(counts[unique_words].word, words[i]);\n counts[unique_words].count = 1;\n unique_words++;\n }\n }\n for (int i = 0; i < 4 && i < unique_words; i++) {\n int max_idx = i;\n for (int j = i + 1; j < unique_words; j++) {\n if (counts[j].count > counts[max_idx].count) {\n max_idx = j;\n }\n }\n WordCount tmp = counts[i];\n counts[i] = counts[max_idx];\n counts[max_idx] = tmp;\n strcpy(result[i].word, counts[i].word);\n result[i].count = counts[i].count;\n }\n *result_size = unique_words > 4 ? 4 : unique_words;\n}", + "test": "int main() {\n\n WordCount result[4];\n\n int result_size;\n\n\n\n char data1[][MAX_WORD_LENGTH] = {\"red\",\"green\",\"black\",\"pink\",\"black\",\"white\",\"black\",\"eyes\",\"white\",\"black\",\"orange\",\"pink\",\"pink\",\"red\",\"red\",\"white\",\"orange\",\"white\",\"black\",\"pink\",\"green\",\"green\",\"pink\",\"green\",\"pink\",\"white\",\"orange\",\"orange\",\"red\"};\n\n func0(data1, 29, result, &result_size);\n\n assert(strcmp(result[0].word, \"pink\") == 0 && result[0].count == 6);\n\n assert(strcmp(result[1].word, \"black\") == 0 && result[1].count == 5);\n\n assert(strcmp(result[2].word, \"white\") == 0 && result[2].count == 5);\n\n assert(strcmp(result[3].word, \"red\") == 0 && result[3].count == 4);\n\n \n\n char data2[][MAX_WORD_LENGTH] = {\"one\", \"two\", \"three\", \"four\", \"five\", \"one\", \"two\", \"one\", \"three\", \"one\"};\n\n func0(data2, 10, result, &result_size);\n\n assert(strcmp(result[0].word, \"one\") == 0 && result[0].count == 4);\n\n assert(strcmp(result[1].word, \"two\") == 0 && result[1].count == 2);\n\n assert(strcmp(result[2].word, \"three\") == 0 && result[2].count == 2);\n\n assert(strcmp(result[3].word, \"four\") == 0 && result[3].count == 1);\n\n\n\n char data3[][MAX_WORD_LENGTH] = {\"Facebook\", \"Apple\", \"Amazon\", \"Netflix\", \"Google\", \"Apple\", \"Netflix\", \"Amazon\"};\n\n func0(data3, 8, result, &result_size);\n\n assert(strcmp(result[0].word, \"Apple\") == 0 && result[0].count == 2);\n\n assert(strcmp(result[1].word, \"Amazon\") == 0 && result[1].count == 2);\n\n assert(strcmp(result[2].word, \"Netflix\") == 0 && result[2].count == 2);\n\n assert(strcmp(result[3].word, \"Facebook\") == 0 && result[3].count == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x1000,%rsp\norq $0x0,(%rsp)\nsub $0x648,%rsp\nmov %rcx,0x8(%rsp)\nlea 0x50(%rsp),%r12\nmov %rdi,%rbp\nmov $0x2bc,%ecx\nmov %rdx,(%rsp)\nmov %r12,%rdi\nmov %fs:0x28,%rax\nmov %rax,0x1638(%rsp)\nxor %eax,%eax\nrep stos %rax,%es:(%rdi)\ntest %esi,%esi\njle 17df \nlea -0x1(%rsi),%eax\nxor %ebx,%ebx\nlea (%rax,%rax,4),%rax\nlea (%rax,%rax,4),%rax\nlea 0x32(%rbp,%rax,2),%r13\nnopw 0x0(%rax,%rax,1)\nmov %r12,%r14\nxor %r15d,%r15d\ntest %ebx,%ebx\njne 15f1 \njmpq 1740 \nadd $0x1,%r15d\nadd $0x38,%r14\ncmp %ebx,%r15d\nje 1740 \nmov %r14,%rsi\nmov %rbp,%rdi\ncallq 10a0 \ntest %eax,%eax\njne 15e0 \nmovslq %r15d,%rdx\nlea 0x0(,%rdx,8),%rax\nsub %rdx,%rax\naddl $0x1,0x84(%rsp,%rax,8)\nadd $0x32,%rbp\ncmp %r13,%rbp\njne 15d0 \nmov (%rsp),%rdi\nmov %r12,%rbp\nxor %r13d,%r13d\nmovslq %r13d,%rax\nadd $0x1,%r13d\ncmp %r13d,%ebx\nje 177b \nmov %rbp,%rsi\nmov %r13d,%edx\nlea 0x0(,%rax,8),%rcx\nmovslq %edx,%r8\nsub %rax,%rcx\nmov 0x84(%rsp,%rcx,8),%ecx\ncmp %ecx,0x6c(%rsi)\ncmovg %r8,%rax\nadd $0x1,%edx\nadd $0x38,%rsi\ncmp %edx,%ebx\njne 1640 \nlea 0x0(,%rax,8),%rdx\nmovdqu 0x0(%rbp),%xmm2\nmovdqu 0x10(%rbp),%xmm1\nsub %rax,%rdx\nmovdqu 0x20(%rbp),%xmm0\nmov 0x30(%rbp),%rcx\nmov %rdx,%rax\nmovaps %xmm2,0x10(%rsp)\nshl $0x3,%rax\nmov %rcx,0x40(%rsp)\nmovdqu 0x50(%rsp,%rax,1),%xmm3\nlea 0x50(%rsp,%rax,1),%rdx\nmovaps %xmm1,0x20(%rsp)\nmovaps %xmm0,0x30(%rsp)\nmovups %xmm3,0x0(%rbp)\nmovdqu 0x10(%rdx),%xmm4\nmovups %xmm4,0x10(%rbp)\nmovdqu 0x20(%rdx),%xmm5\nmovups %xmm5,0x20(%rbp)\nmov 0x30(%rdx),%rsi\nmov %rsi,0x30(%rbp)\nmov %rbp,%rsi\nadd $0x38,%rbp\nmovups %xmm2,0x50(%rsp,%rax,1)\nmov %rcx,0x30(%rdx)\nmovups %xmm1,0x10(%rdx)\nmovups %xmm0,0x20(%rdx)\nmov $0x32,%edx\ncallq 10b0 <__strcpy_chk@plt>\nmov %rax,%rdi\nmov -0x4(%rbp),%eax\nadd $0x38,%rdi\nmov %eax,-0x4(%rdi)\ncmp $0x4,%r13d\njne 1629 \ncmp $0x4,%ebx\ncmovg %r13d,%ebx\nmov 0x8(%rsp),%rax\nmov %ebx,(%rax)\nmov 0x1638(%rsp),%rax\nxor %fs:0x28,%rax\njne 17e6 \nadd $0x1648,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\nmovslq %ebx,%rax\nmov $0x32,%edx\nmov %rbp,%rsi\nadd $0x1,%ebx\nlea 0x0(,%rax,8),%rcx\nsub %rax,%rcx\nlea 0x0(,%rcx,8),%r14\nlea (%r12,%r14,1),%rdi\ncallq 10b0 <__strcpy_chk@plt>\nmovl $0x1,0x84(%rsp,%r14,1)\njmpq 1616 \nlea 0x0(,%rax,8),%rbp\nmov (%rsp),%r14\nmov $0x32,%edx\nsub %rax,%rbp\nshl $0x3,%rbp\nmovdqu 0x50(%rsp,%rbp,1),%xmm6\nlea 0x50(%rsp,%rbp,1),%rax\nadd %rbp,%r14\nlea (%r12,%rbp,1),%rsi\nmovdqu 0x10(%rax),%xmm7\nmov %r14,%rdi\nmovaps %xmm6,0x10(%rsp)\nmovdqu 0x20(%rax),%xmm6\nmov 0x30(%rax),%rax\nmovaps %xmm7,0x20(%rsp)\nmov %rax,0x40(%rsp)\nmovaps %xmm6,0x30(%rsp)\ncallq 10b0 <__strcpy_chk@plt>\nmov 0x84(%rsp,%rbp,1),%eax\nmov %eax,0x34(%r14)\njmpq 1709 \nxor %ebx,%ebx\njmpq 1709 \ncallq 1080 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 1000h\nor [rsp+1030h+var_1030], 0\nsub rsp, 648h\nmov [rsp+1678h+var_1670], rcx\nlea r12, [rsp+1678h+s2]\nmov rbp, rdi\nmov ecx, 2BCh\nmov [rsp+1678h+var_1678], rdx\nmov rdi, r12\nmov rax, fs:28h\nmov [rsp+1678h+var_40], rax\nxor eax, eax\nrep stosq\ntest esi, esi\njle loc_17FC\nmovsxd rsi, esi\nxor ebx, ebx\nlea rax, [rsi+rsi*4]\nlea rax, [rax+rax*4]\nlea r13, [rbp+rax*2+0]\nnop word ptr [rax+rax+00h]\nloc_15D0:\ntest ebx, ebx\njle loc_1750\nloc_15D8:\nmov r15, r12\nxor r14d, r14d\njmp short loc_15F1\nloc_15E0:\nadd r14d, 1\nadd r15, 38h ; '8'\ncmp r14d, ebx\njz loc_1750\nloc_15F1:\nmov rsi, r15; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njnz short loc_15E0\nmovsxd rdx, r14d\nadd rbp, 32h ; '2'\nlea rax, ds:0[rdx*8]\nsub rax, rdx\nadd [rsp+rax*8+1678h+var_15F4], 1\ncmp rbp, r13\njnz short loc_15D8\nloc_161F:\ntest ebx, ebx\njle loc_170D\nmov rdi, [rsp+1678h+var_1678]\nmov rbp, r12\nxor r13d, r13d\nloc_1631:\nmovsxd rsi, r13d\nadd r13d, 1\ncmp r13d, ebx\njz loc_1798\nmov rcx, rbp\nmov edx, r13d\nnop word ptr [rax+rax+00000000h]\nloc_1650:\nlea rax, ds:0[rsi*8]\nsub rax, rsi\nmov eax, [rsp+rax*8+1678h+var_15F4]\ncmp [rcx+6Ch], eax\njle short loc_166A\nmovsxd rsi, edx\nloc_166A:\nadd edx, 1\nadd rcx, 38h ; '8'\ncmp edx, ebx\njnz short loc_1650\nlea rax, ds:0[rsi*8]\nmovdqu xmm2, xmmword ptr [rbp+0]\nmovdqu xmm1, xmmword ptr [rbp+10h]\nsub rax, rsi\nmovdqu xmm0, xmmword ptr [rbp+20h]\nmov rcx, [rbp+30h]\nshl rax, 3\nmovaps [rsp+1678h+var_1668], xmm2\nmovdqu xmm3, xmmword ptr [rsp+rax+1678h+s2]\nlea rdx, [rsp+rax+1678h+s2]\nmov [rsp+1678h+var_1638], rcx\nmovaps [rsp+1678h+var_1658], xmm1\nmovups xmmword ptr [rbp+0], xmm3\nmovdqu xmm4, xmmword ptr [rdx+10h]\nmovaps [rsp+1678h+var_1648], xmm0\nmovups xmmword ptr [rbp+10h], xmm4\nmovdqu xmm5, xmmword ptr [rdx+20h]\nmovups xmmword ptr [rbp+20h], xmm5\nmov rsi, [rdx+30h]\nmov [rbp+30h], rsi\nmov rsi, rbp\nadd rbp, 38h ; '8'\nmovups xmmword ptr [rsp+rax+1678h+s2], xmm2\nmov [rdx+30h], rcx\nmovups xmmword ptr [rdx+10h], xmm1\nmovups xmmword ptr [rdx+20h], xmm0\nmov edx, 32h ; '2'\ncall ___strcpy_chk\nmov rdi, rax\nmov eax, [rbp-4]\nadd rdi, 38h ; '8'\nmov [rdi-4], eax\ncmp r13d, 4\njnz loc_1631\nloc_170D:\nmov eax, 4\ncmp ebx, eax\ncmovle eax, ebx\nloc_1717:\nmov rcx, [rsp+1678h+var_1670]\nmov [rcx], eax\nmov rax, [rsp+1678h+var_40]\nsub rax, fs:28h\njnz loc_1803\nadd rsp, 1648h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1750:\nmovsxd rax, ebx\nmov rsi, rbp\nmov edx, 32h ; '2'\nadd rbp, 32h ; '2'\nlea rcx, ds:0[rax*8]\nadd ebx, 1\nsub rcx, rax\nlea r14, ds:0[rcx*8]\nlea rdi, [r12+r14]\ncall ___strcpy_chk\nmov [rsp+r14+1678h+var_15F4], 1\ncmp rbp, r13\njnz loc_15D0\njmp loc_161F\nloc_1798:\nlea rbp, ds:0[rsi*8]\nmov r14, [rsp+1678h+var_1678]\nmov edx, 32h ; '2'\nsub rbp, rsi\nshl rbp, 3\nmovdqu xmm6, xmmword ptr [rsp+rbp+1678h+s2]\nlea rax, [rsp+rbp+1678h+s2]\nadd r14, rbp\nlea rsi, [r12+rbp]\nmovdqu xmm7, xmmword ptr [rax+10h]\nmov rdi, r14\nmovaps [rsp+1678h+var_1668], xmm6\nmovdqu xmm6, xmmword ptr [rax+20h]\nmov rax, [rax+30h]\nmovaps [rsp+1678h+var_1658], xmm7\nmov [rsp+1678h+var_1638], rax\nmovaps [rsp+1678h+var_1648], xmm6\ncall ___strcpy_chk\nmov eax, [rsp+rbp+1678h+var_15F4]\nmov [r14+34h], eax\njmp loc_170D\nloc_17FC:\nxor eax, eax\njmp loc_1717\nloc_1803:\ncall ___stack_chk_fail", + "ida_pseudo": "unsigned __int64 __fastcall func0(char *s1, int a2, __int64 a3, int *a4)\n{\n const char *v4; // rbp\n int v5; // ebx\n char *v6; // r13\n char *v7; // r15\n int v8; // r14d\n __int64 v9; // rdi\n __m128i *v10; // rbp\n int v11; // r13d\n __int64 v12; // rsi\n __m128i *v13; // rcx\n int v14; // edx\n __m128i v15; // xmm0\n __int64 v16; // rax\n const __m128i *v17; // rdx\n __m128i *v18; // rsi\n __int64 v19; // rax\n int v20; // eax\n __int64 v22; // rax\n const char *v23; // rsi\n __int64 v24; // rcx\n __int64 v25; // r14\n __int64 v26; // r14\n __m128i v29; // [rsp+10h] [rbp-1668h]\n __m128i v30; // [rsp+20h] [rbp-1658h]\n __int64 v31; // [rsp+40h] [rbp-1638h]\n char s2[5608]; // [rsp+50h] [rbp-1628h] BYREF\n unsigned __int64 v33; // [rsp+1638h] [rbp-40h]\n\n v4 = s1;\n v33 = __readfsqword(0x28u);\n memset(s2, 0, 0x15E0uLL);\n if ( a2 <= 0 )\n {\n v20 = 0;\n }\n else\n {\n v5 = 0;\n v6 = &s1[50 * a2];\n while ( v5 <= 0 )\n {\nLABEL_19:\n v22 = v5;\n v23 = v4;\n v4 += 50;\n v24 = 8LL * v5++;\n v25 = 8 * (v24 - v22);\n __strcpy_chk(&s2[v25], v23, 50LL);\n *(_DWORD *)&s2[v25 + 52] = 1;\n if ( v4 == v6 )\n goto LABEL_8;\n }\n do\n {\n v7 = s2;\n v8 = 0;\n while ( strcmp(v4, v7) )\n {\n ++v8;\n v7 += 56;\n if ( v8 == v5 )\n goto LABEL_19;\n }\n v4 += 50;\n ++*(_DWORD *)&s2[56 * v8 + 52];\n }\n while ( v4 != v6 );\nLABEL_8:\n if ( v5 > 0 )\n {\n v9 = a3;\n v10 = (__m128i *)s2;\n v11 = 0;\n while ( 1 )\n {\n v12 = v11++;\n if ( v11 == v5 )\n break;\n v13 = v10;\n v14 = v11;\n do\n {\n if ( v13[6].m128i_i32[3] > *(_DWORD *)&s2[56 * v12 + 52] )\n v12 = v14;\n ++v14;\n v13 = (__m128i *)((char *)v13 + 56);\n }\n while ( v14 != v5 );\n v15 = _mm_loadu_si128(v10 + 2);\n v16 = 56 * v12;\n v29 = _mm_loadu_si128(v10);\n v17 = (const __m128i *)&s2[56 * v12];\n v31 = v10[3].m128i_i64[0];\n v30 = _mm_loadu_si128(v10 + 1);\n *v10 = _mm_loadu_si128(v17);\n v10[1] = _mm_loadu_si128(v17 + 1);\n v10[2] = _mm_loadu_si128(v17 + 2);\n v10[3].m128i_i64[0] = v17[3].m128i_i64[0];\n v18 = v10;\n v10 = (__m128i *)((char *)v10 + 56);\n *(__m128i *)&s2[v16] = v29;\n v17[3].m128i_i64[0] = v31;\n v17[1] = v30;\n v17[2] = v15;\n v19 = __strcpy_chk(v9, v18, 50LL);\n v9 = v19 + 56;\n *(_DWORD *)(v19 + 52) = v10[-1].m128i_i32[3];\n if ( v11 == 4 )\n goto LABEL_16;\n }\n v26 = 56 * v12 + a3;\n __strcpy_chk(v26, &s2[56 * v12], 50LL);\n *(_DWORD *)(v26 + 52) = *(_DWORD *)&s2[56 * v12 + 52];\n }\nLABEL_16:\n v20 = 4;\n if ( v5 <= 4 )\n v20 = v5;\n }\n *a4 = v20;\n return v33 - __readfsqword(0x28u);\n}", + "ida_strip_asm": "sub_1560:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 1000h\nor [rsp+1030h+var_1030], 0\nsub rsp, 648h\nmov [rsp+1678h+var_1670], rcx\nlea r12, [rsp+1678h+s2]\nmov rbp, rdi\nmov ecx, 2BCh\nmov [rsp+1678h+var_1678], rdx\nmov rdi, r12\nmov rax, fs:28h\nmov [rsp+1678h+var_40], rax\nxor eax, eax\nrep stosq\ntest esi, esi\njle loc_17FC\nmovsxd rsi, esi\nxor ebx, ebx\nlea rax, [rsi+rsi*4]\nlea rax, [rax+rax*4]\nlea r13, [rbp+rax*2+0]\nnop word ptr [rax+rax+00h]\nloc_15D0:\ntest ebx, ebx\njle loc_1750\nloc_15D8:\nmov r15, r12\nxor r14d, r14d\njmp short loc_15F1\nloc_15E0:\nadd r14d, 1\nadd r15, 38h ; '8'\ncmp r14d, ebx\njz loc_1750\nloc_15F1:\nmov rsi, r15; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njnz short loc_15E0\nmovsxd rdx, r14d\nadd rbp, 32h ; '2'\nlea rax, ds:0[rdx*8]\nsub rax, rdx\nadd [rsp+rax*8+1678h+var_15F4], 1\ncmp rbp, r13\njnz short loc_15D8\nloc_161F:\ntest ebx, ebx\njle loc_170D\nmov rdi, [rsp+1678h+var_1678]\nmov rbp, r12\nxor r13d, r13d\nloc_1631:\nmovsxd rsi, r13d\nadd r13d, 1\ncmp r13d, ebx\njz loc_1798\nmov rcx, rbp\nmov edx, r13d\nnop word ptr [rax+rax+00000000h]\nloc_1650:\nlea rax, ds:0[rsi*8]\nsub rax, rsi\nmov eax, [rsp+rax*8+1678h+var_15F4]\ncmp [rcx+6Ch], eax\njle short loc_166A\nmovsxd rsi, edx\nloc_166A:\nadd edx, 1\nadd rcx, 38h ; '8'\ncmp edx, ebx\njnz short loc_1650\nlea rax, ds:0[rsi*8]\nmovdqu xmm2, xmmword ptr [rbp+0]\nmovdqu xmm1, xmmword ptr [rbp+10h]\nsub rax, rsi\nmovdqu xmm0, xmmword ptr [rbp+20h]\nmov rcx, [rbp+30h]\nshl rax, 3\nmovaps [rsp+1678h+var_1668], xmm2\nmovdqu xmm3, xmmword ptr [rsp+rax+1678h+s2]\nlea rdx, [rsp+rax+1678h+s2]\nmov [rsp+1678h+var_1638], rcx\nmovaps [rsp+1678h+var_1658], xmm1\nmovups xmmword ptr [rbp+0], xmm3\nmovdqu xmm4, xmmword ptr [rdx+10h]\nmovaps [rsp+1678h+var_1648], xmm0\nmovups xmmword ptr [rbp+10h], xmm4\nmovdqu xmm5, xmmword ptr [rdx+20h]\nmovups xmmword ptr [rbp+20h], xmm5\nmov rsi, [rdx+30h]\nmov [rbp+30h], rsi\nmov rsi, rbp\nadd rbp, 38h ; '8'\nmovups xmmword ptr [rsp+rax+1678h+s2], xmm2\nmov [rdx+30h], rcx\nmovups xmmword ptr [rdx+10h], xmm1\nmovups xmmword ptr [rdx+20h], xmm0\nmov edx, 32h ; '2'\ncall ___strcpy_chk\nmov rdi, rax\nmov eax, [rbp-4]\nadd rdi, 38h ; '8'\nmov [rdi-4], eax\ncmp r13d, 4\njnz loc_1631\nloc_170D:\nmov eax, 4\ncmp ebx, eax\ncmovle eax, ebx\nloc_1717:\nmov rcx, [rsp+1678h+var_1670]\nmov [rcx], eax\nmov rax, [rsp+1678h+var_40]\nsub rax, fs:28h\njnz loc_1803\nadd rsp, 1648h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1750:\nmovsxd rax, ebx\nmov rsi, rbp\nmov edx, 32h ; '2'\nadd rbp, 32h ; '2'\nlea rcx, ds:0[rax*8]\nadd ebx, 1\nsub rcx, rax\nlea r14, ds:0[rcx*8]\nlea rdi, [r12+r14]\ncall ___strcpy_chk\nmov [rsp+r14+1678h+var_15F4], 1\ncmp rbp, r13\njnz loc_15D0\njmp loc_161F\nloc_1798:\nlea rbp, ds:0[rsi*8]\nmov r14, [rsp+1678h+var_1678]\nmov edx, 32h ; '2'\nsub rbp, rsi\nshl rbp, 3\nmovdqu xmm6, xmmword ptr [rsp+rbp+1678h+s2]\nlea rax, [rsp+rbp+1678h+s2]\nadd r14, rbp\nlea rsi, [r12+rbp]\nmovdqu xmm7, xmmword ptr [rax+10h]\nmov rdi, r14\nmovaps [rsp+1678h+var_1668], xmm6\nmovdqu xmm6, xmmword ptr [rax+20h]\nmov rax, [rax+30h]\nmovaps [rsp+1678h+var_1658], xmm7\nmov [rsp+1678h+var_1638], rax\nmovaps [rsp+1678h+var_1648], xmm6\ncall ___strcpy_chk\nmov eax, [rsp+rbp+1678h+var_15F4]\nmov [r14+34h], eax\njmp loc_170D\nloc_17FC:\nxor eax, eax\njmp loc_1717\nloc_1803:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_1560(char *s1, int a2, __int64 a3, int *a4)\n{\n const char *v4; // rbp\n int v5; // ebx\n char *v6; // r13\n char *v7; // r15\n int v8; // r14d\n __int64 v9; // rdi\n __m128i *v10; // rbp\n int v11; // r13d\n __int64 v12; // rsi\n __m128i *v13; // rcx\n int v14; // edx\n __m128i v15; // xmm0\n __int64 v16; // rax\n const __m128i *v17; // rdx\n __m128i *v18; // rsi\n __int64 v19; // rax\n int v20; // eax\n __int64 v22; // rax\n const char *v23; // rsi\n __int64 v24; // rcx\n __int64 v25; // r14\n __int64 v26; // r14\n __m128i v29; // [rsp+10h] [rbp-1668h]\n __m128i v30; // [rsp+20h] [rbp-1658h]\n __int64 v31; // [rsp+40h] [rbp-1638h]\n char s2[5608]; // [rsp+50h] [rbp-1628h] BYREF\n unsigned __int64 v33; // [rsp+1638h] [rbp-40h]\n\n v4 = s1;\n v33 = __readfsqword(0x28u);\n memset(s2, 0, 0x15E0uLL);\n if ( a2 <= 0 )\n {\n v20 = 0;\n }\n else\n {\n v5 = 0;\n v6 = &s1[50 * a2];\n while ( v5 <= 0 )\n {\nLABEL_19:\n v22 = v5;\n v23 = v4;\n v4 += 50;\n v24 = 8LL * v5++;\n v25 = 8 * (v24 - v22);\n __strcpy_chk(&s2[v25], v23, 50LL);\n *(_DWORD *)&s2[v25 + 52] = 1;\n if ( v4 == v6 )\n goto LABEL_8;\n }\n do\n {\n v7 = s2;\n v8 = 0;\n while ( strcmp(v4, v7) )\n {\n ++v8;\n v7 += 56;\n if ( v8 == v5 )\n goto LABEL_19;\n }\n v4 += 50;\n ++*(_DWORD *)&s2[56 * v8 + 52];\n }\n while ( v4 != v6 );\nLABEL_8:\n if ( v5 > 0 )\n {\n v9 = a3;\n v10 = (__m128i *)s2;\n v11 = 0;\n while ( 1 )\n {\n v12 = v11++;\n if ( v11 == v5 )\n break;\n v13 = v10;\n v14 = v11;\n do\n {\n if ( v13[6].m128i_i32[3] > *(_DWORD *)&s2[56 * v12 + 52] )\n v12 = v14;\n ++v14;\n v13 = (__m128i *)((char *)v13 + 56);\n }\n while ( v14 != v5 );\n v15 = _mm_loadu_si128(v10 + 2);\n v16 = 56 * v12;\n v29 = _mm_loadu_si128(v10);\n v17 = (const __m128i *)&s2[56 * v12];\n v31 = v10[3].m128i_i64[0];\n v30 = _mm_loadu_si128(v10 + 1);\n *v10 = _mm_loadu_si128(v17);\n v10[1] = _mm_loadu_si128(v17 + 1);\n v10[2] = _mm_loadu_si128(v17 + 2);\n v10[3].m128i_i64[0] = v17[3].m128i_i64[0];\n v18 = v10;\n v10 = (__m128i *)((char *)v10 + 56);\n *(__m128i *)&s2[v16] = v29;\n v17[3].m128i_i64[0] = v31;\n v17[1] = v30;\n v17[2] = v15;\n v19 = __strcpy_chk(v9, v18, 50LL);\n v9 = v19 + 56;\n *(_DWORD *)(v19 + 52) = v10[-1].m128i_i32[3];\n if ( v11 == 4 )\n goto LABEL_16;\n }\n v26 = 56 * v12 + a3;\n __strcpy_chk(v26, &s2[56 * v12], 50LL);\n *(_DWORD *)(v26 + 52) = *(_DWORD *)&s2[56 * v12 + 52];\n }\nLABEL_16:\n v20 = 4;\n if ( v5 <= 4 )\n v20 = v5;\n }\n *a4 = v20;\n return v33 - __readfsqword(0x28u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_1560(char *s1, int a2, long long a3, int *a4) {\n const char *v4;\n int v5;\n char *v6;\n char *v7;\n int v8;\n long long v9;\n __m128i *v10;\n int v11;\n long long v12;\n __m128i *v13;\n int v14;\n __m128i v15;\n long long v16;\n const __m128i *v17;\n __m128i *v18;\n long long v19;\n int v20;\n long long v22;\n const char *v23;\n long long v24;\n long long v25;\n long long v26;\n __m128i v29;\n __m128i v30;\n long long v31;\n char s2[5608];\n unsigned long long v33;\n v4 = s1;\n v33 = __readfsqword(40u);\n memset(s2, 0, 5600uLL);\n if (a2 <= 0) {\n v20 = 0;\n } else {\n v5 = 0;\n v6 = &s1[50 * a2];\n while (v5 <= 0) {\n LABEL_19:\n v22 = v5;\n v23 = v4;\n v4 += 50;\n v24 = 8LL * v5++;\n v25 = 8 * (v24 - v22);\n __strcpy_chk(&s2[v25], v23, 50LL);\n *(uint32_t *)&s2[v25 + 52] = 1;\n if (v4 == v6) goto LABEL_8;\n }\n do {\n v7 = s2;\n v8 = 0;\n while (strcmp(v4, v7)) {\n ++v8;\n v7 += 56;\n if (v8 == v5) goto LABEL_19;\n }\n v4 += 50;\n ++*(uint32_t *)&s2[56 * v8 + 52];\n } while (v4 != v6);\n LABEL_8:\n if (v5 > 0) {\n v9 = a3;\n v10 = (__m128i *)s2;\n v11 = 0;\n while (1) {\n v12 = v11++;\n if (v11 == v5) break;\n v13 = v10;\n v14 = v11;\n do {\n if (v13[6].m128i_i32[3] > *(uint32_t *)&s2[56 * v12 + 52]) v12 = v14;\n ++v14;\n v13 = (__m128i *)((char *)v13 + 56);\n } while (v14 != v5);\n v15 = _mm_loadu_si128(v10 + 2);\n v16 = 56 * v12;\n v29 = _mm_loadu_si128(v10);\n v17 = (const __m128i *)&s2[56 * v12];\n v31 = v10[3].m128i_i64[0];\n v30 = _mm_loadu_si128(v10 + 1);\n *v10 = _mm_loadu_si128(v17);\n v10[1] = _mm_loadu_si128(v17 + 1);\n v10[2] = _mm_loadu_si128(v17 + 2);\n v10[3].m128i_i64[0] = v17[3].m128i_i64[0];\n v18 = v10;\n v10 = (__m128i *)((char *)v10 + 56);\n *(__m128i *)&s2[v16] = v29;\n v17[3].m128i_i64[0] = v31;\n v17[1] = v30;\n v17[2] = v15;\n v19 = __strcpy_chk(v9, v18, 50LL);\n v9 = v19 + 56;\n *(uint32_t *)(v19 + 52) = v10[-1].m128i_i32[3];\n if (v11 == 4) goto LABEL_16;\n }\n v26 = 56 * v12 + a3;\n __strcpy_chk(v26, &s2[56 * v12], 50LL);\n *(uint32_t *)(v26 + 52) = *(uint32_t *)&s2[56 * v12 + 52];\n }\n LABEL_16:\n v20 = 4;\n if (v5 <= 4) v20 = v5;\n }\n *a4 = v20;\n return v33 - __readfsqword(40u);\n}", + "ida_pseudo_norm": "unsigned long long func0(char *s1, int a2, long long a3, int *a4) {\n const char *v4;\n int v5;\n char *v6;\n char *v7;\n int v8;\n long long v9;\n __m128i *v10;\n int v11;\n long long v12;\n __m128i *v13;\n int v14;\n __m128i v15;\n long long v16;\n const __m128i *v17;\n __m128i *v18;\n long long v19;\n int v20;\n long long v22;\n const char *v23;\n long long v24;\n long long v25;\n long long v26;\n __m128i v29;\n __m128i v30;\n long long v31;\n char s2[5608];\n unsigned long long v33;\n v4 = s1;\n v33 = __readfsqword(40u);\n memset(s2, 0, 5600uLL);\n if (a2 <= 0) {\n v20 = 0;\n } else {\n v5 = 0;\n v6 = &s1[50 * a2];\n while (v5 <= 0) {\n LABEL_19:\n v22 = v5;\n v23 = v4;\n v4 += 50;\n v24 = 8LL * v5++;\n v25 = 8 * (v24 - v22);\n __strcpy_chk(&s2[v25], v23, 50LL);\n *(uint32_t *)&s2[v25 + 52] = 1;\n if (v4 == v6) goto LABEL_8;\n }\n do {\n v7 = s2;\n v8 = 0;\n while (strcmp(v4, v7)) {\n ++v8;\n v7 += 56;\n if (v8 == v5) goto LABEL_19;\n }\n v4 += 50;\n ++*(uint32_t *)&s2[56 * v8 + 52];\n } while (v4 != v6);\n LABEL_8:\n if (v5 > 0) {\n v9 = a3;\n v10 = (__m128i *)s2;\n v11 = 0;\n while (1) {\n v12 = v11++;\n if (v11 == v5) break;\n v13 = v10;\n v14 = v11;\n do {\n if (v13[6].m128i_i32[3] > *(uint32_t *)&s2[56 * v12 + 52]) v12 = v14;\n ++v14;\n v13 = (__m128i *)((char *)v13 + 56);\n } while (v14 != v5);\n v15 = _mm_loadu_si128(v10 + 2);\n v16 = 56 * v12;\n v29 = _mm_loadu_si128(v10);\n v17 = (const __m128i *)&s2[56 * v12];\n v31 = v10[3].m128i_i64[0];\n v30 = _mm_loadu_si128(v10 + 1);\n *v10 = _mm_loadu_si128(v17);\n v10[1] = _mm_loadu_si128(v17 + 1);\n v10[2] = _mm_loadu_si128(v17 + 2);\n v10[3].m128i_i64[0] = v17[3].m128i_i64[0];\n v18 = v10;\n v10 = (__m128i *)((char *)v10 + 56);\n *(__m128i *)&s2[v16] = v29;\n v17[3].m128i_i64[0] = v31;\n v17[1] = v30;\n v17[2] = v15;\n v19 = __strcpy_chk(v9, v18, 50LL);\n v9 = v19 + 56;\n *(uint32_t *)(v19 + 52) = v10[-1].m128i_i32[3];\n if (v11 == 4) goto LABEL_16;\n }\n v26 = 56 * v12 + a3;\n __strcpy_chk(v26, &s2[56 * v12], 50LL);\n *(uint32_t *)(v26 + 52) = *(uint32_t *)&s2[56 * v12 + 52];\n }\n LABEL_16:\n v20 = 4;\n if (v5 <= 4) v20 = v5;\n }\n *a4 = v20;\n return v33 - __readfsqword(40u);\n}" + }, + { + "index": 13, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n#define MAX_WORDS 100\n\n#define MAX_WORD_LENGTH 50\n\n\n\ntypedef struct {\n\n char word[MAX_WORD_LENGTH];\n\n int count;\n\n} WordCount;\n\n\n\n", + "func": "void func0(char words[][MAX_WORD_LENGTH], int num_words, WordCount result[],\n int *result_size) {\n WordCount counts[MAX_WORDS] = {0};\n int unique_words = 0;\n for (int i = 0; i < num_words; i++) {\n int found = 0;\n for (int j = 0; j < unique_words; j++) {\n if (strcmp(words[i], counts[j].word) == 0) {\n counts[j].count++;\n found = 1;\n break;\n }\n }\n if (!found) {\n strcpy(counts[unique_words].word, words[i]);\n counts[unique_words].count = 1;\n unique_words++;\n }\n }\n for (int i = 0; i < 4 && i < unique_words; i++) {\n int max_idx = i;\n for (int j = i + 1; j < unique_words; j++) {\n if (counts[j].count > counts[max_idx].count) {\n max_idx = j;\n }\n }\n WordCount tmp = counts[i];\n counts[i] = counts[max_idx];\n counts[max_idx] = tmp;\n strcpy(result[i].word, counts[i].word);\n result[i].count = counts[i].count;\n }\n *result_size = unique_words > 4 ? 4 : unique_words;\n}", + "test": "int main() {\n\n WordCount result[4];\n\n int result_size;\n\n\n\n char data1[][MAX_WORD_LENGTH] = {\"red\",\"green\",\"black\",\"pink\",\"black\",\"white\",\"black\",\"eyes\",\"white\",\"black\",\"orange\",\"pink\",\"pink\",\"red\",\"red\",\"white\",\"orange\",\"white\",\"black\",\"pink\",\"green\",\"green\",\"pink\",\"green\",\"pink\",\"white\",\"orange\",\"orange\",\"red\"};\n\n func0(data1, 29, result, &result_size);\n\n assert(strcmp(result[0].word, \"pink\") == 0 && result[0].count == 6);\n\n assert(strcmp(result[1].word, \"black\") == 0 && result[1].count == 5);\n\n assert(strcmp(result[2].word, \"white\") == 0 && result[2].count == 5);\n\n assert(strcmp(result[3].word, \"red\") == 0 && result[3].count == 4);\n\n \n\n char data2[][MAX_WORD_LENGTH] = {\"one\", \"two\", \"three\", \"four\", \"five\", \"one\", \"two\", \"one\", \"three\", \"one\"};\n\n func0(data2, 10, result, &result_size);\n\n assert(strcmp(result[0].word, \"one\") == 0 && result[0].count == 4);\n\n assert(strcmp(result[1].word, \"two\") == 0 && result[1].count == 2);\n\n assert(strcmp(result[2].word, \"three\") == 0 && result[2].count == 2);\n\n assert(strcmp(result[3].word, \"four\") == 0 && result[3].count == 1);\n\n\n\n char data3[][MAX_WORD_LENGTH] = {\"Facebook\", \"Apple\", \"Amazon\", \"Netflix\", \"Google\", \"Apple\", \"Netflix\", \"Amazon\"};\n\n func0(data3, 8, result, &result_size);\n\n assert(strcmp(result[0].word, \"Apple\") == 0 && result[0].count == 2);\n\n assert(strcmp(result[1].word, \"Amazon\") == 0 && result[1].count == 2);\n\n assert(strcmp(result[2].word, \"Netflix\") == 0 && result[2].count == 2);\n\n assert(strcmp(result[3].word, \"Facebook\") == 0 && result[3].count == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x1000,%rsp\norq $0x0,(%rsp)\nsub $0x648,%rsp\nmov %rcx,0x8(%rsp)\nlea 0x50(%rsp),%r12\nmov %rdi,%rbp\nmov $0x2bc,%ecx\nmov %rdx,(%rsp)\nmov %r12,%rdi\nmov %fs:0x28,%rax\nmov %rax,0x1638(%rsp)\nxor %eax,%eax\nrep stos %rax,%es:(%rdi)\ntest %esi,%esi\njle 17d7 \nlea -0x1(%rsi),%eax\nxor %ebx,%ebx\nlea (%rax,%rax,4),%rax\nlea (%rax,%rax,4),%rax\nlea 0x32(%rbp,%rax,2),%r13\nnopw 0x0(%rax,%rax,1)\nmov %r12,%r14\nxor %r15d,%r15d\ntest %ebx,%ebx\njne 15f1 \njmpq 1738 \nadd $0x1,%r15d\nadd $0x38,%r14\ncmp %ebx,%r15d\nje 1738 \nmov %r14,%rsi\nmov %rbp,%rdi\ncallq 10a0 \ntest %eax,%eax\njne 15e0 \nmovslq %r15d,%rdx\nlea 0x0(,%rdx,8),%rax\nsub %rdx,%rax\naddl $0x1,0x84(%rsp,%rax,8)\nadd $0x32,%rbp\ncmp %r13,%rbp\njne 15d0 \nmov (%rsp),%r8\nmov %r12,%rbp\nxor %r13d,%r13d\nmovslq %r13d,%rdi\nadd $0x1,%r13d\ncmp %r13d,%ebx\nje 1773 \nmov 0x34(%rbp),%esi\nmov %rbp,%rdx\nmov %r13d,%eax\nnopw 0x0(%rax,%rax,1)\nmov 0x6c(%rdx),%ecx\ncmp %esi,%ecx\njle 1654 \nmov %ecx,%esi\nmovslq %eax,%rdi\nadd $0x1,%eax\nadd $0x38,%rdx\ncmp %eax,%ebx\njne 1648 \nlea 0x0(,%rdi,8),%rax\nmovdqu 0x0(%rbp),%xmm2\nmovdqu 0x10(%rbp),%xmm1\nsub %rdi,%rax\nmovdqu 0x20(%rbp),%xmm0\nmov 0x30(%rbp),%rcx\nmov %r8,%rdi\nshl $0x3,%rax\nmovaps %xmm2,0x10(%rsp)\nmovdqu 0x50(%rsp,%rax,1),%xmm3\nlea 0x50(%rsp,%rax,1),%rdx\nmov %rcx,0x40(%rsp)\nmovaps %xmm1,0x20(%rsp)\nmovups %xmm3,0x0(%rbp)\nmovdqu 0x10(%rdx),%xmm4\nmovaps %xmm0,0x30(%rsp)\nmovups %xmm4,0x10(%rbp)\nmovdqu 0x20(%rdx),%xmm5\nmovups %xmm5,0x20(%rbp)\nmov 0x30(%rdx),%rsi\nmov %rsi,0x30(%rbp)\nmov %rbp,%rsi\nadd $0x38,%rbp\nmovups %xmm2,0x50(%rsp,%rax,1)\nmov %rcx,0x30(%rdx)\nmovups %xmm1,0x10(%rdx)\nmovups %xmm0,0x20(%rdx)\nmov $0x32,%edx\ncallq 10b0 <__strcpy_chk@plt>\nmov %rax,%r8\nmov -0x4(%rbp),%eax\nadd $0x38,%r8\nmov %eax,-0x4(%r8)\ncmp $0x4,%r13d\njne 1629 \ncmp $0x4,%ebx\ncmovg %r13d,%ebx\nmov 0x8(%rsp),%rax\nmov %ebx,(%rax)\nmov 0x1638(%rsp),%rax\nxor %fs:0x28,%rax\njne 17de \nadd $0x1648,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw 0x0(%rax,%rax,1)\nmovslq %ebx,%rax\nmov $0x32,%edx\nmov %rbp,%rsi\nadd $0x1,%ebx\nlea 0x0(,%rax,8),%rcx\nsub %rax,%rcx\nlea 0x0(,%rcx,8),%r14\nlea (%r12,%r14,1),%rdi\ncallq 10b0 <__strcpy_chk@plt>\nmovl $0x1,0x84(%rsp,%r14,1)\njmpq 1616 \nlea 0x0(,%rdi,8),%rbp\nmov (%rsp),%r14\nmov $0x32,%edx\nsub %rdi,%rbp\nshl $0x3,%rbp\nmovdqu 0x50(%rsp,%rbp,1),%xmm6\nlea 0x50(%rsp,%rbp,1),%rax\nadd %rbp,%r14\nlea (%r12,%rbp,1),%rsi\nmovdqu 0x10(%rax),%xmm7\nmov %r14,%rdi\nmovaps %xmm6,0x10(%rsp)\nmovdqu 0x20(%rax),%xmm6\nmov 0x30(%rax),%rax\nmovaps %xmm7,0x20(%rsp)\nmov %rax,0x40(%rsp)\nmovaps %xmm6,0x30(%rsp)\ncallq 10b0 <__strcpy_chk@plt>\nmov 0x84(%rsp,%rbp,1),%eax\nmov %eax,0x34(%r14)\njmpq 1702 \nxor %ebx,%ebx\njmpq 1702 \ncallq 1080 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 1000h\nor [rsp+1030h+var_1030], 0\nsub rsp, 648h\nmov [rsp+1678h+var_1670], rcx\nlea r12, [rsp+1678h+s2]\nmov rbp, rdi\nmov ecx, 2BCh\nmov [rsp+1678h+var_1678], rdx\nmov rdi, r12\nmov rax, fs:28h\nmov [rsp+1678h+var_40], rax\nxor eax, eax\nrep stosq\ntest esi, esi\njle loc_17EC\nmovsxd rsi, esi\nxor ebx, ebx\nlea rax, [rsi+rsi*4]\nlea rax, [rax+rax*4]\nlea r13, [rbp+rax*2+0]\nnop word ptr [rax+rax+00h]\nloc_15D0:\ntest ebx, ebx\njle loc_1740\nloc_15D8:\nmov r15, r12\nxor r14d, r14d\njmp short loc_15F1\nloc_15E0:\nadd r14d, 1\nadd r15, 38h ; '8'\ncmp r14d, ebx\njz loc_1740\nloc_15F1:\nmov rsi, r15; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njnz short loc_15E0\nmovsxd rdx, r14d\nadd rbp, 32h ; '2'\nlea rax, ds:0[rdx*8]\nsub rax, rdx\nadd [rsp+rax*8+1678h+var_15F4], 1\ncmp rbp, r13\njnz short loc_15D8\nloc_161F:\ntest ebx, ebx\njle loc_1703\nmov r8, [rsp+1678h+var_1678]\nmov rbp, r12\nxor r13d, r13d\nloc_1631:\nmovsxd rdi, r13d\nadd r13d, 1\ncmp r13d, ebx\njz loc_1788\nmov esi, [rbp+34h]\nmov rdx, rbp\nmov eax, r13d\nnop word ptr [rax+rax+00h]\nloc_1650:\nmov ecx, [rdx+6Ch]\ncmp ecx, esi\njle short loc_165C\nmov esi, ecx\nmovsxd rdi, eax\nloc_165C:\nadd eax, 1\nadd rdx, 38h ; '8'\ncmp eax, ebx\njnz short loc_1650\nlea rax, ds:0[rdi*8]\nmovdqu xmm2, xmmword ptr [rbp+0]\nmovdqu xmm1, xmmword ptr [rbp+10h]\nsub rax, rdi\nmovdqu xmm0, xmmword ptr [rbp+20h]\nmov rcx, [rbp+30h]\nmov rdi, r8\nshl rax, 3\nmovaps [rsp+1678h+var_1668], xmm2\nmovdqu xmm3, xmmword ptr [rsp+rax+1678h+s2]\nlea rdx, [rsp+rax+1678h+s2]\nmov [rsp+1678h+var_1638], rcx\nmovaps [rsp+1678h+var_1658], xmm1\nmovups xmmword ptr [rbp+0], xmm3\nmovdqu xmm4, xmmword ptr [rdx+10h]\nmovaps [rsp+1678h+var_1648], xmm0\nmovups xmmword ptr [rbp+10h], xmm4\nmovdqu xmm5, xmmword ptr [rdx+20h]\nmovups xmmword ptr [rbp+20h], xmm5\nmov rsi, [rdx+30h]\nmov [rbp+30h], rsi\nmov rsi, rbp\nadd rbp, 38h ; '8'\nmovups xmmword ptr [rsp+rax+1678h+s2], xmm2\nmov [rdx+30h], rcx\nmovups xmmword ptr [rdx+10h], xmm1\nmovups xmmword ptr [rdx+20h], xmm0\nmov edx, 32h ; '2'\ncall ___strcpy_chk\nmov r8, rax\nmov eax, [rbp-4]\nadd r8, 38h ; '8'\nmov [r8-4], eax\ncmp r13d, 4\njnz loc_1631\nloc_1703:\nmov eax, 4\ncmp ebx, eax\ncmovle eax, ebx\nloc_170D:\nmov rcx, [rsp+1678h+var_1670]\nmov [rcx], eax\nmov rax, [rsp+1678h+var_40]\nsub rax, fs:28h\njnz loc_17F3\nadd rsp, 1648h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1740:\nmovsxd rax, ebx\nmov rsi, rbp\nmov edx, 32h ; '2'\nadd rbp, 32h ; '2'\nlea rcx, ds:0[rax*8]\nadd ebx, 1\nsub rcx, rax\nlea r14, ds:0[rcx*8]\nlea rdi, [r12+r14]\ncall ___strcpy_chk\nmov [rsp+r14+1678h+var_15F4], 1\ncmp r13, rbp\njnz loc_15D0\njmp loc_161F\nloc_1788:\nlea rbp, ds:0[rdi*8]\nmov r14, [rsp+1678h+var_1678]\nmov edx, 32h ; '2'\nsub rbp, rdi\nshl rbp, 3\nmovdqu xmm6, xmmword ptr [rsp+rbp+1678h+s2]\nlea rax, [rsp+rbp+1678h+s2]\nadd r14, rbp\nlea rsi, [r12+rbp]\nmovdqu xmm7, xmmword ptr [rax+10h]\nmov rdi, r14\nmovaps [rsp+1678h+var_1668], xmm6\nmovdqu xmm6, xmmword ptr [rax+20h]\nmov rax, [rax+30h]\nmovaps [rsp+1678h+var_1658], xmm7\nmov [rsp+1678h+var_1638], rax\nmovaps [rsp+1678h+var_1648], xmm6\ncall ___strcpy_chk\nmov eax, [rsp+rbp+1678h+var_15F4]\nmov [r14+34h], eax\njmp loc_1703\nloc_17EC:\nxor eax, eax\njmp loc_170D\nloc_17F3:\ncall ___stack_chk_fail", + "ida_pseudo": "unsigned __int64 __fastcall func0(char *s1, int a2, __int64 a3, int *a4)\n{\n const char *v4; // rbp\n int v5; // ebx\n char *v6; // r13\n char *v7; // r15\n int v8; // r14d\n __int64 v9; // r8\n __m128i *v10; // rbp\n int v11; // r13d\n __int64 v12; // rdi\n __int32 v13; // esi\n __m128i *v14; // rdx\n int v15; // eax\n __m128i v16; // xmm0\n __m128i *v17; // rdx\n __m128i *v18; // rsi\n __int64 v19; // rax\n int v20; // eax\n __int64 v22; // rax\n const char *v23; // rsi\n __int64 v24; // rcx\n __int64 v25; // r14\n __m128i v28; // [rsp+10h] [rbp-1668h]\n __m128i v29; // [rsp+20h] [rbp-1658h]\n __int64 v30; // [rsp+40h] [rbp-1638h]\n char s2[5608]; // [rsp+50h] [rbp-1628h] BYREF\n unsigned __int64 v32; // [rsp+1638h] [rbp-40h]\n\n v4 = s1;\n v32 = __readfsqword(0x28u);\n memset(s2, 0, 0x15E0uLL);\n if ( a2 <= 0 )\n {\n v20 = 0;\n }\n else\n {\n v5 = 0;\n v6 = &s1[50 * a2];\n while ( v5 <= 0 )\n {\nLABEL_19:\n v22 = v5;\n v23 = v4;\n v4 += 50;\n v24 = 8LL * v5++;\n v25 = 8 * (v24 - v22);\n __strcpy_chk(&s2[v25], v23, 50LL);\n *(_DWORD *)&s2[v25 + 52] = 1;\n if ( v6 == v4 )\n goto LABEL_8;\n }\n do\n {\n v7 = s2;\n v8 = 0;\n while ( strcmp(v4, v7) )\n {\n ++v8;\n v7 += 56;\n if ( v8 == v5 )\n goto LABEL_19;\n }\n v4 += 50;\n ++*(_DWORD *)&s2[56 * v8 + 52];\n }\n while ( v4 != v6 );\nLABEL_8:\n if ( v5 > 0 )\n {\n v9 = a3;\n v10 = (__m128i *)s2;\n v11 = 0;\n while ( 1 )\n {\n v12 = v11++;\n if ( v11 == v5 )\n break;\n v13 = v10[3].m128i_i32[1];\n v14 = v10;\n v15 = v11;\n do\n {\n if ( v14[6].m128i_i32[3] > v13 )\n {\n v13 = v14[6].m128i_i32[3];\n v12 = v15;\n }\n ++v15;\n v14 = (__m128i *)((char *)v14 + 56);\n }\n while ( v15 != v5 );\n v16 = _mm_loadu_si128(v10 + 2);\n v28 = _mm_loadu_si128(v10);\n v17 = (__m128i *)&s2[56 * v12];\n v30 = v10[3].m128i_i64[0];\n v29 = _mm_loadu_si128(v10 + 1);\n *v10 = _mm_loadu_si128(v17);\n v10[1] = _mm_loadu_si128(v17 + 1);\n v10[2] = _mm_loadu_si128(v17 + 2);\n v10[3].m128i_i64[0] = v17[3].m128i_i64[0];\n v18 = v10;\n v10 = (__m128i *)((char *)v10 + 56);\n *v17 = v28;\n v17[3].m128i_i64[0] = v30;\n v17[1] = v29;\n v17[2] = v16;\n v19 = __strcpy_chk(v9, v18, 50LL);\n v9 = v19 + 56;\n *(_DWORD *)(v19 + 52) = v10[-1].m128i_i32[3];\n if ( v11 == 4 )\n goto LABEL_16;\n }\n __strcpy_chk(56 * v12 + a3, &s2[56 * v12], 50LL);\n *(_DWORD *)(56 * v12 + a3 + 52) = *(_DWORD *)&s2[56 * v12 + 52];\n }\nLABEL_16:\n v20 = 4;\n if ( v5 <= 4 )\n v20 = v5;\n }\n *a4 = v20;\n return v32 - __readfsqword(0x28u);\n}", + "ida_strip_asm": "sub_1560:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 1000h\nor [rsp+1030h+var_1030], 0\nsub rsp, 648h\nmov [rsp+1678h+var_1670], rcx\nlea r12, [rsp+1678h+s2]\nmov rbp, rdi\nmov ecx, 2BCh\nmov [rsp+1678h+var_1678], rdx\nmov rdi, r12\nmov rax, fs:28h\nmov [rsp+1678h+var_40], rax\nxor eax, eax\nrep stosq\ntest esi, esi\njle loc_17EC\nmovsxd rsi, esi\nxor ebx, ebx\nlea rax, [rsi+rsi*4]\nlea rax, [rax+rax*4]\nlea r13, [rbp+rax*2+0]\nnop word ptr [rax+rax+00h]\nloc_15D0:\ntest ebx, ebx\njle loc_1740\nloc_15D8:\nmov r15, r12\nxor r14d, r14d\njmp short loc_15F1\nloc_15E0:\nadd r14d, 1\nadd r15, 38h ; '8'\ncmp r14d, ebx\njz loc_1740\nloc_15F1:\nmov rsi, r15; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njnz short loc_15E0\nmovsxd rdx, r14d\nadd rbp, 32h ; '2'\nlea rax, ds:0[rdx*8]\nsub rax, rdx\nadd [rsp+rax*8+1678h+var_15F4], 1\ncmp rbp, r13\njnz short loc_15D8\nloc_161F:\ntest ebx, ebx\njle loc_1703\nmov r8, [rsp+1678h+var_1678]\nmov rbp, r12\nxor r13d, r13d\nloc_1631:\nmovsxd rdi, r13d\nadd r13d, 1\ncmp r13d, ebx\njz loc_1788\nmov esi, [rbp+34h]\nmov rdx, rbp\nmov eax, r13d\nnop word ptr [rax+rax+00h]\nloc_1650:\nmov ecx, [rdx+6Ch]\ncmp ecx, esi\njle short loc_165C\nmov esi, ecx\nmovsxd rdi, eax\nloc_165C:\nadd eax, 1\nadd rdx, 38h ; '8'\ncmp eax, ebx\njnz short loc_1650\nlea rax, ds:0[rdi*8]\nmovdqu xmm2, xmmword ptr [rbp+0]\nmovdqu xmm1, xmmword ptr [rbp+10h]\nsub rax, rdi\nmovdqu xmm0, xmmword ptr [rbp+20h]\nmov rcx, [rbp+30h]\nmov rdi, r8\nshl rax, 3\nmovaps [rsp+1678h+var_1668], xmm2\nmovdqu xmm3, xmmword ptr [rsp+rax+1678h+s2]\nlea rdx, [rsp+rax+1678h+s2]\nmov [rsp+1678h+var_1638], rcx\nmovaps [rsp+1678h+var_1658], xmm1\nmovups xmmword ptr [rbp+0], xmm3\nmovdqu xmm4, xmmword ptr [rdx+10h]\nmovaps [rsp+1678h+var_1648], xmm0\nmovups xmmword ptr [rbp+10h], xmm4\nmovdqu xmm5, xmmword ptr [rdx+20h]\nmovups xmmword ptr [rbp+20h], xmm5\nmov rsi, [rdx+30h]\nmov [rbp+30h], rsi\nmov rsi, rbp\nadd rbp, 38h ; '8'\nmovups xmmword ptr [rsp+rax+1678h+s2], xmm2\nmov [rdx+30h], rcx\nmovups xmmword ptr [rdx+10h], xmm1\nmovups xmmword ptr [rdx+20h], xmm0\nmov edx, 32h ; '2'\ncall ___strcpy_chk\nmov r8, rax\nmov eax, [rbp-4]\nadd r8, 38h ; '8'\nmov [r8-4], eax\ncmp r13d, 4\njnz loc_1631\nloc_1703:\nmov eax, 4\ncmp ebx, eax\ncmovle eax, ebx\nloc_170D:\nmov rcx, [rsp+1678h+var_1670]\nmov [rcx], eax\nmov rax, [rsp+1678h+var_40]\nsub rax, fs:28h\njnz loc_17F3\nadd rsp, 1648h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1740:\nmovsxd rax, ebx\nmov rsi, rbp\nmov edx, 32h ; '2'\nadd rbp, 32h ; '2'\nlea rcx, ds:0[rax*8]\nadd ebx, 1\nsub rcx, rax\nlea r14, ds:0[rcx*8]\nlea rdi, [r12+r14]\ncall ___strcpy_chk\nmov [rsp+r14+1678h+var_15F4], 1\ncmp r13, rbp\njnz loc_15D0\njmp loc_161F\nloc_1788:\nlea rbp, ds:0[rdi*8]\nmov r14, [rsp+1678h+var_1678]\nmov edx, 32h ; '2'\nsub rbp, rdi\nshl rbp, 3\nmovdqu xmm6, xmmword ptr [rsp+rbp+1678h+s2]\nlea rax, [rsp+rbp+1678h+s2]\nadd r14, rbp\nlea rsi, [r12+rbp]\nmovdqu xmm7, xmmword ptr [rax+10h]\nmov rdi, r14\nmovaps [rsp+1678h+var_1668], xmm6\nmovdqu xmm6, xmmword ptr [rax+20h]\nmov rax, [rax+30h]\nmovaps [rsp+1678h+var_1658], xmm7\nmov [rsp+1678h+var_1638], rax\nmovaps [rsp+1678h+var_1648], xmm6\ncall ___strcpy_chk\nmov eax, [rsp+rbp+1678h+var_15F4]\nmov [r14+34h], eax\njmp loc_1703\nloc_17EC:\nxor eax, eax\njmp loc_170D\nloc_17F3:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_1560(char *s1, int a2, __int64 a3, int *a4)\n{\n const char *v4; // rbp\n int v5; // ebx\n char *v6; // r13\n char *v7; // r15\n int v8; // r14d\n __int64 v9; // r8\n __m128i *v10; // rbp\n int v11; // r13d\n __int64 v12; // rdi\n __int32 v13; // esi\n __m128i *v14; // rdx\n int v15; // eax\n __m128i v16; // xmm0\n __m128i *v17; // rdx\n __m128i *v18; // rsi\n __int64 v19; // rax\n int v20; // eax\n __int64 v22; // rax\n const char *v23; // rsi\n __int64 v24; // rcx\n __int64 v25; // r14\n __m128i v28; // [rsp+10h] [rbp-1668h]\n __m128i v29; // [rsp+20h] [rbp-1658h]\n __int64 v30; // [rsp+40h] [rbp-1638h]\n char s2[5608]; // [rsp+50h] [rbp-1628h] BYREF\n unsigned __int64 v32; // [rsp+1638h] [rbp-40h]\n\n v4 = s1;\n v32 = __readfsqword(0x28u);\n memset(s2, 0, 0x15E0uLL);\n if ( a2 <= 0 )\n {\n v20 = 0;\n }\n else\n {\n v5 = 0;\n v6 = &s1[50 * a2];\n while ( v5 <= 0 )\n {\nLABEL_19:\n v22 = v5;\n v23 = v4;\n v4 += 50;\n v24 = 8LL * v5++;\n v25 = 8 * (v24 - v22);\n __strcpy_chk(&s2[v25], v23, 50LL);\n *(_DWORD *)&s2[v25 + 52] = 1;\n if ( v6 == v4 )\n goto LABEL_8;\n }\n do\n {\n v7 = s2;\n v8 = 0;\n while ( strcmp(v4, v7) )\n {\n ++v8;\n v7 += 56;\n if ( v8 == v5 )\n goto LABEL_19;\n }\n v4 += 50;\n ++*(_DWORD *)&s2[56 * v8 + 52];\n }\n while ( v4 != v6 );\nLABEL_8:\n if ( v5 > 0 )\n {\n v9 = a3;\n v10 = (__m128i *)s2;\n v11 = 0;\n while ( 1 )\n {\n v12 = v11++;\n if ( v11 == v5 )\n break;\n v13 = v10[3].m128i_i32[1];\n v14 = v10;\n v15 = v11;\n do\n {\n if ( v14[6].m128i_i32[3] > v13 )\n {\n v13 = v14[6].m128i_i32[3];\n v12 = v15;\n }\n ++v15;\n v14 = (__m128i *)((char *)v14 + 56);\n }\n while ( v15 != v5 );\n v16 = _mm_loadu_si128(v10 + 2);\n v28 = _mm_loadu_si128(v10);\n v17 = (__m128i *)&s2[56 * v12];\n v30 = v10[3].m128i_i64[0];\n v29 = _mm_loadu_si128(v10 + 1);\n *v10 = _mm_loadu_si128(v17);\n v10[1] = _mm_loadu_si128(v17 + 1);\n v10[2] = _mm_loadu_si128(v17 + 2);\n v10[3].m128i_i64[0] = v17[3].m128i_i64[0];\n v18 = v10;\n v10 = (__m128i *)((char *)v10 + 56);\n *v17 = v28;\n v17[3].m128i_i64[0] = v30;\n v17[1] = v29;\n v17[2] = v16;\n v19 = __strcpy_chk(v9, v18, 50LL);\n v9 = v19 + 56;\n *(_DWORD *)(v19 + 52) = v10[-1].m128i_i32[3];\n if ( v11 == 4 )\n goto LABEL_16;\n }\n __strcpy_chk(56 * v12 + a3, &s2[56 * v12], 50LL);\n *(_DWORD *)(56 * v12 + a3 + 52) = *(_DWORD *)&s2[56 * v12 + 52];\n }\nLABEL_16:\n v20 = 4;\n if ( v5 <= 4 )\n v20 = v5;\n }\n *a4 = v20;\n return v32 - __readfsqword(0x28u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_1560(char *s1, int a2, long long a3, int *a4) {\n const char *v4;\n int v5;\n char *v6;\n char *v7;\n int v8;\n long long v9;\n __m128i *v10;\n int v11;\n long long v12;\n int v13;\n __m128i *v14;\n int v15;\n __m128i v16;\n __m128i *v17;\n __m128i *v18;\n long long v19;\n int v20;\n long long v22;\n const char *v23;\n long long v24;\n long long v25;\n __m128i v28;\n __m128i v29;\n long long v30;\n char s2[5608];\n unsigned long long v32;\n v4 = s1;\n v32 = __readfsqword(40u);\n memset(s2, 0, 5600uLL);\n if (a2 <= 0) {\n v20 = 0;\n } else {\n v5 = 0;\n v6 = &s1[50 * a2];\n while (v5 <= 0) {\n LABEL_19:\n v22 = v5;\n v23 = v4;\n v4 += 50;\n v24 = 8LL * v5++;\n v25 = 8 * (v24 - v22);\n __strcpy_chk(&s2[v25], v23, 50LL);\n *(uint32_t *)&s2[v25 + 52] = 1;\n if (v6 == v4) goto LABEL_8;\n }\n do {\n v7 = s2;\n v8 = 0;\n while (strcmp(v4, v7)) {\n ++v8;\n v7 += 56;\n if (v8 == v5) goto LABEL_19;\n }\n v4 += 50;\n ++*(uint32_t *)&s2[56 * v8 + 52];\n } while (v4 != v6);\n LABEL_8:\n if (v5 > 0) {\n v9 = a3;\n v10 = (__m128i *)s2;\n v11 = 0;\n while (1) {\n v12 = v11++;\n if (v11 == v5) break;\n v13 = v10[3].m128i_i32[1];\n v14 = v10;\n v15 = v11;\n do {\n if (v14[6].m128i_i32[3] > v13) {\n v13 = v14[6].m128i_i32[3];\n v12 = v15;\n }\n ++v15;\n v14 = (__m128i *)((char *)v14 + 56);\n } while (v15 != v5);\n v16 = _mm_loadu_si128(v10 + 2);\n v28 = _mm_loadu_si128(v10);\n v17 = (__m128i *)&s2[56 * v12];\n v30 = v10[3].m128i_i64[0];\n v29 = _mm_loadu_si128(v10 + 1);\n *v10 = _mm_loadu_si128(v17);\n v10[1] = _mm_loadu_si128(v17 + 1);\n v10[2] = _mm_loadu_si128(v17 + 2);\n v10[3].m128i_i64[0] = v17[3].m128i_i64[0];\n v18 = v10;\n v10 = (__m128i *)((char *)v10 + 56);\n *v17 = v28;\n v17[3].m128i_i64[0] = v30;\n v17[1] = v29;\n v17[2] = v16;\n v19 = __strcpy_chk(v9, v18, 50LL);\n v9 = v19 + 56;\n *(uint32_t *)(v19 + 52) = v10[-1].m128i_i32[3];\n if (v11 == 4) goto LABEL_16;\n }\n __strcpy_chk(56 * v12 + a3, &s2[56 * v12], 50LL);\n *(uint32_t *)(56 * v12 + a3 + 52) = *(uint32_t *)&s2[56 * v12 + 52];\n }\n LABEL_16:\n v20 = 4;\n if (v5 <= 4) v20 = v5;\n }\n *a4 = v20;\n return v32 - __readfsqword(40u);\n}", + "ida_pseudo_norm": "unsigned long long func0(char *s1, int a2, long long a3, int *a4) {\n const char *v4;\n int v5;\n char *v6;\n char *v7;\n int v8;\n long long v9;\n __m128i *v10;\n int v11;\n long long v12;\n int v13;\n __m128i *v14;\n int v15;\n __m128i v16;\n __m128i *v17;\n __m128i *v18;\n long long v19;\n int v20;\n long long v22;\n const char *v23;\n long long v24;\n long long v25;\n __m128i v28;\n __m128i v29;\n long long v30;\n char s2[5608];\n unsigned long long v32;\n v4 = s1;\n v32 = __readfsqword(40u);\n memset(s2, 0, 5600uLL);\n if (a2 <= 0) {\n v20 = 0;\n } else {\n v5 = 0;\n v6 = &s1[50 * a2];\n while (v5 <= 0) {\n LABEL_19:\n v22 = v5;\n v23 = v4;\n v4 += 50;\n v24 = 8LL * v5++;\n v25 = 8 * (v24 - v22);\n __strcpy_chk(&s2[v25], v23, 50LL);\n *(uint32_t *)&s2[v25 + 52] = 1;\n if (v6 == v4) goto LABEL_8;\n }\n do {\n v7 = s2;\n v8 = 0;\n while (strcmp(v4, v7)) {\n ++v8;\n v7 += 56;\n if (v8 == v5) goto LABEL_19;\n }\n v4 += 50;\n ++*(uint32_t *)&s2[56 * v8 + 52];\n } while (v4 != v6);\n LABEL_8:\n if (v5 > 0) {\n v9 = a3;\n v10 = (__m128i *)s2;\n v11 = 0;\n while (1) {\n v12 = v11++;\n if (v11 == v5) break;\n v13 = v10[3].m128i_i32[1];\n v14 = v10;\n v15 = v11;\n do {\n if (v14[6].m128i_i32[3] > v13) {\n v13 = v14[6].m128i_i32[3];\n v12 = v15;\n }\n ++v15;\n v14 = (__m128i *)((char *)v14 + 56);\n } while (v15 != v5);\n v16 = _mm_loadu_si128(v10 + 2);\n v28 = _mm_loadu_si128(v10);\n v17 = (__m128i *)&s2[56 * v12];\n v30 = v10[3].m128i_i64[0];\n v29 = _mm_loadu_si128(v10 + 1);\n *v10 = _mm_loadu_si128(v17);\n v10[1] = _mm_loadu_si128(v17 + 1);\n v10[2] = _mm_loadu_si128(v17 + 2);\n v10[3].m128i_i64[0] = v17[3].m128i_i64[0];\n v18 = v10;\n v10 = (__m128i *)((char *)v10 + 56);\n *v17 = v28;\n v17[3].m128i_i64[0] = v30;\n v17[1] = v29;\n v17[2] = v16;\n v19 = __strcpy_chk(v9, v18, 50LL);\n v9 = v19 + 56;\n *(uint32_t *)(v19 + 52) = v10[-1].m128i_i32[3];\n if (v11 == 4) goto LABEL_16;\n }\n __strcpy_chk(56 * v12 + a3, &s2[56 * v12], 50LL);\n *(uint32_t *)(56 * v12 + a3 + 52) = *(uint32_t *)&s2[56 * v12 + 52];\n }\n LABEL_16:\n v20 = 4;\n if (v5 <= 4) v20 = v5;\n }\n *a4 = v20;\n return v32 - __readfsqword(40u);\n}" + }, + { + "index": 14, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "float func0(float l, float b, float h) { return ((l * b * h) / 2); }", + "test": "int main() {\n\n assert(func0(10, 8, 6) == 240);\n\n assert(func0(3, 2, 2) == 6);\n\n assert(func0(1, 2, 1) == 1);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmovss %xmm0,-0x4(%rbp)\nmovss %xmm1,-0x8(%rbp)\nmovss %xmm2,-0xc(%rbp)\nmovss -0x4(%rbp),%xmm0\nmulss -0x8(%rbp),%xmm0\nmulss -0xc(%rbp),%xmm0\nmovss 0xf11(%rip),%xmm1\ndivss %xmm1,%xmm0\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmovss [rbp+var_4], xmm0\nmovss [rbp+var_8], xmm1\nmovss [rbp+var_C], xmm2\nmovss xmm0, [rbp+var_4]\nmulss xmm0, [rbp+var_8]\nmulss xmm0, [rbp+var_C]\nmovss xmm1, cs:dword_206C\ndivss xmm0, xmm1\npop rbp\nretn", + "ida_pseudo": "float __fastcall func0(float a1, float a2, float a3)\n{\n return (float)((float)(a1 * a2) * a3) / 2.0;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmovss [rbp+var_4], xmm0\nmovss [rbp+var_8], xmm1\nmovss [rbp+var_C], xmm2\nmovss xmm0, [rbp+var_4]\nmulss xmm0, [rbp+var_8]\nmulss xmm0, [rbp+var_C]\nmovss xmm1, cs:dword_206C\ndivss xmm0, xmm1\npop rbp\nretn", + "ida_strip_pseudo": "float __fastcall sub_1149(float a1, float a2, float a3)\n{\n return (float)((float)(a1 * a2) * a3) / 2.0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "float sub_1149(float a1, float a2, float a3) {\n return (float)((float)(a1 * a2) * a3) / 2.0;\n}", + "ida_pseudo_norm": "float func0(float a1, float a2, float a3) {\n return (float)((float)(a1 * a2) * a3) / 2.0;\n}" + }, + { + "index": 15, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(const char* text, int* count) {\n char** result = NULL;\n *count = 0;\n int len = strlen(text);\n int i = 0;\n while (i < len) {\n if (islower((unsigned char)text[i])) {\n int start = i;\n i++;\n while (i < len && !islower((unsigned char)text[i])) {\n i++;\n }\n int end = i;\n int substr_len = end - start;\n char* substr = (char*)malloc(substr_len + 1);\n strncpy(substr, text + start, substr_len);\n substr[substr_len] = '\\0';\n result = (char**)realloc(result, sizeof(char*) * (*count + 1));\n result[*count] = substr;\n (*count)++;\n } else {\n i++;\n }\n }\n return result;\n}", + "test": "int main() {\n\n // Test case 1\n\n int count1;\n\n char** res1 = func0(\"AbCd\", &count1);\n\n assert(count1 == 2);\n\n assert(strcmp(res1[0], \"bC\") == 0);\n\n assert(strcmp(res1[1], \"d\") == 0);\n\n for(int i = 0; i < count1; i++) free(res1[i]);\n\n free(res1);\n\n\n\n // Test case 2\n\n int count2;\n\n char** res2 = func0(\"Python\", &count2);\n\n assert(count2 == 5);\n\n assert(strcmp(res2[0], \"y\") == 0);\n\n assert(strcmp(res2[1], \"t\") == 0);\n\n assert(strcmp(res2[2], \"h\") == 0);\n\n assert(strcmp(res2[3], \"o\") == 0);\n\n assert(strcmp(res2[4], \"n\") == 0);\n\n for(int i = 0; i < count2; i++) free(res2[i]);\n\n free(res2);\n\n\n\n // Test case 3\n\n int count3;\n\n char** res3 = func0(\"Programming\", &count3);\n\n assert(count3 == 10);\n\n assert(strcmp(res3[0], \"r\") == 0);\n\n assert(strcmp(res3[1], \"o\") == 0);\n\n assert(strcmp(res3[2], \"g\") == 0);\n\n assert(strcmp(res3[3], \"r\") == 0);\n\n assert(strcmp(res3[4], \"a\") == 0);\n\n assert(strcmp(res3[5], \"m\") == 0);\n\n assert(strcmp(res3[6], \"m\") == 0);\n\n assert(strcmp(res3[7], \"i\") == 0);\n\n assert(strcmp(res3[8], \"n\") == 0);\n\n assert(strcmp(res3[9], \"g\") == 0);\n\n for(int i = 0; i < count3; i++) free(res3[i]);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x40,%rsp\nmov %rdi,-0x38(%rbp)\nmov %rsi,-0x40(%rbp)\nmovq $0x0,-0x10(%rbp)\nmov -0x40(%rbp),%rax\nmovl $0x0,(%rax)\nmov -0x38(%rbp),%rax\nmov %rax,%rdi\ncallq 10f0 \nmov %eax,-0x20(%rbp)\nmovl $0x0,-0x24(%rbp)\njmpq 13b4 \ncallq 1150 <__ctype_b_loc@plt>\nmov (%rax),%rax\nmov -0x24(%rbp),%edx\nmovslq %edx,%rcx\nmov -0x38(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rdx),%edx\nmovzbl %dl,%edx\nadd %rdx,%rdx\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x200,%eax\ntest %eax,%eax\nje 13b0 \nmov -0x24(%rbp),%eax\nmov %eax,-0x1c(%rbp)\naddl $0x1,-0x24(%rbp)\njmp 12ce \naddl $0x1,-0x24(%rbp)\nmov -0x24(%rbp),%eax\ncmp -0x20(%rbp),%eax\njge 1306 \ncallq 1150 <__ctype_b_loc@plt>\nmov (%rax),%rax\nmov -0x24(%rbp),%edx\nmovslq %edx,%rcx\nmov -0x38(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rdx),%edx\nmovzbl %dl,%edx\nadd %rdx,%rdx\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x200,%eax\ntest %eax,%eax\nje 12ca \nmov -0x24(%rbp),%eax\nmov %eax,-0x18(%rbp)\nmov -0x18(%rbp),%eax\nsub -0x1c(%rbp),%eax\nmov %eax,-0x14(%rbp)\nmov -0x14(%rbp),%eax\nadd $0x1,%eax\ncltq\nmov %rax,%rdi\ncallq 1130 \nmov %rax,-0x8(%rbp)\nmov -0x14(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x1c(%rbp),%eax\nmovslq %eax,%rcx\nmov -0x38(%rbp),%rax\nadd %rax,%rcx\nmov -0x8(%rbp),%rax\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 10e0 \nmov -0x14(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmovb $0x0,(%rax)\nmov -0x40(%rbp),%rax\nmov (%rax),%eax\nadd $0x1,%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x10(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1140 \nmov %rax,-0x10(%rbp)\nmov -0x40(%rbp),%rax\nmov (%rax),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x10(%rbp),%rax\nadd %rax,%rdx\nmov -0x8(%rbp),%rax\nmov %rax,(%rdx)\nmov -0x40(%rbp),%rax\nmov (%rax),%eax\nlea 0x1(%rax),%edx\nmov -0x40(%rbp),%rax\nmov %edx,(%rax)\njmp 13b4 \naddl $0x1,-0x24(%rbp)\nmov -0x24(%rbp),%eax\ncmp -0x20(%rbp),%eax\njl 128a \nmov -0x10(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+s], rdi\nmov [rbp+var_40], rsi\nmov [rbp+ptr], 0\nmov rax, [rbp+var_40]\nmov dword ptr [rax], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_20], eax\nmov [rbp+var_24], 0\njmp loc_13B4\nloc_128A:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_24]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovzx edx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 200h\ntest eax, eax\njz loc_13B0\nmov eax, [rbp+var_24]\nmov [rbp+var_1C], eax\nadd [rbp+var_24], 1\njmp short loc_12CE\nloc_12CA:\nadd [rbp+var_24], 1\nloc_12CE:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_20]\njge short loc_1306\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_24]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovzx edx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 200h\ntest eax, eax\njz short loc_12CA\nloc_1306:\nmov eax, [rbp+var_24]\nmov [rbp+var_18], eax\nmov eax, [rbp+var_18]\nsub eax, [rbp+var_1C]\nmov [rbp+var_14], eax\nmov eax, [rbp+var_14]\nadd eax, 1\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+dest], rax\nmov eax, [rbp+var_14]\nmovsxd rdx, eax; n\nmov eax, [rbp+var_1C]\nmovsxd rcx, eax\nmov rax, [rbp+s]\nadd rcx, rax\nmov rax, [rbp+dest]\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strncpy\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+dest]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+var_40]\nmov eax, [rax]\nadd eax, 1\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nmov rsi, rdx; size\nmov rdi, rax; ptr\ncall _realloc\nmov [rbp+ptr], rax\nmov rax, [rbp+var_40]\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov rax, [rbp+dest]\nmov [rdx], rax\nmov rax, [rbp+var_40]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_40]\nmov [rax], edx\njmp short loc_13B4\nloc_13B0:\nadd [rbp+var_24], 1\nloc_13B4:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_20]\njl loc_128A\nmov rax, [rbp+ptr]\nleave\nretn", + "ida_pseudo": "void *__fastcall func0(const char *a1, _DWORD *a2)\n{\n int v3; // [rsp+1Ch] [rbp-24h]\n int v4; // [rsp+20h] [rbp-20h]\n int v5; // [rsp+24h] [rbp-1Ch]\n void *ptr; // [rsp+30h] [rbp-10h]\n char *dest; // [rsp+38h] [rbp-8h]\n\n ptr = 0LL;\n *a2 = 0;\n v4 = strlen(a1);\n v3 = 0;\n while ( v3 < v4 )\n {\n if ( ((*__ctype_b_loc())[(unsigned __int8)a1[v3]] & 0x200) != 0 )\n {\n v5 = v3++;\n while ( v3 < v4 && ((*__ctype_b_loc())[(unsigned __int8)a1[v3]] & 0x200) == 0 )\n ++v3;\n dest = (char *)malloc(v3 - v5 + 1);\n strncpy(dest, &a1[v5], v3 - v5);\n dest[v3 - v5] = 0;\n ptr = realloc(ptr, 8LL * (*a2 + 1));\n *((_QWORD *)ptr + (int)(*a2)++) = dest;\n }\n else\n {\n ++v3;\n }\n }\n return ptr;\n}", + "ida_strip_asm": "sub_1249:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+s], rdi\nmov [rbp+var_40], rsi\nmov [rbp+ptr], 0\nmov rax, [rbp+var_40]\nmov dword ptr [rax], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_20], eax\nmov [rbp+var_24], 0\njmp loc_13B4\nloc_128A:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_24]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovzx edx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 200h\ntest eax, eax\njz loc_13B0\nmov eax, [rbp+var_24]\nmov [rbp+var_1C], eax\nadd [rbp+var_24], 1\njmp short loc_12CE\nloc_12CA:\nadd [rbp+var_24], 1\nloc_12CE:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_20]\njge short loc_1306\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_24]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovzx edx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 200h\ntest eax, eax\njz short loc_12CA\nloc_1306:\nmov eax, [rbp+var_24]\nmov [rbp+var_18], eax\nmov eax, [rbp+var_18]\nsub eax, [rbp+var_1C]\nmov [rbp+var_14], eax\nmov eax, [rbp+var_14]\nadd eax, 1\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+dest], rax\nmov eax, [rbp+var_14]\nmovsxd rdx, eax; n\nmov eax, [rbp+var_1C]\nmovsxd rcx, eax\nmov rax, [rbp+s]\nadd rcx, rax\nmov rax, [rbp+dest]\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strncpy\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+dest]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+var_40]\nmov eax, [rax]\nadd eax, 1\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nmov rsi, rdx; size\nmov rdi, rax; ptr\ncall _realloc\nmov [rbp+ptr], rax\nmov rax, [rbp+var_40]\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov rax, [rbp+dest]\nmov [rdx], rax\nmov rax, [rbp+var_40]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_40]\nmov [rax], edx\njmp short loc_13B4\nloc_13B0:\nadd [rbp+var_24], 1\nloc_13B4:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_20]\njl loc_128A\nmov rax, [rbp+ptr]\nleave\nretn", + "ida_strip_pseudo": "void *__fastcall sub_1249(const char *a1, _DWORD *a2)\n{\n int v3; // [rsp+1Ch] [rbp-24h]\n int v4; // [rsp+20h] [rbp-20h]\n int v5; // [rsp+24h] [rbp-1Ch]\n void *ptr; // [rsp+30h] [rbp-10h]\n char *dest; // [rsp+38h] [rbp-8h]\n\n ptr = 0LL;\n *a2 = 0;\n v4 = strlen(a1);\n v3 = 0;\n while ( v3 < v4 )\n {\n if ( ((*__ctype_b_loc())[(unsigned __int8)a1[v3]] & 0x200) != 0 )\n {\n v5 = v3++;\n while ( v3 < v4 && ((*__ctype_b_loc())[(unsigned __int8)a1[v3]] & 0x200) == 0 )\n ++v3;\n dest = (char *)malloc(v3 - v5 + 1);\n strncpy(dest, &a1[v5], v3 - v5);\n dest[v3 - v5] = 0;\n ptr = realloc(ptr, 8LL * (*a2 + 1));\n *((_QWORD *)ptr + (int)(*a2)++) = dest;\n }\n else\n {\n ++v3;\n }\n }\n return ptr;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1249(const char *a1, uint32_t *a2) {\n int v3;\n int v4;\n int v5;\n void *ptr;\n char *dest;\n ptr = 0LL;\n *a2 = 0;\n v4 = strlen(a1);\n v3 = 0;\n while (v3 < v4) {\n if (((*__ctype_b_loc())[(unsigned char)a1[v3]] & 512) != 0) {\n v5 = v3++;\n while (v3 < v4 && ((*__ctype_b_loc())[(unsigned char)a1[v3]] & 512) == 0)\n ++v3;\n dest = (char *)malloc(v3 - v5 + 1);\n strncpy(dest, &a1[v5], v3 - v5);\n dest[v3 - v5] = 0;\n ptr = realloc(ptr, 8LL * (*a2 + 1));\n *((uint64_t *)ptr + (int)(*a2)++) = dest;\n } else {\n ++v3;\n }\n }\n return ptr;\n}", + "ida_pseudo_norm": "void *func0(const char *a1, uint32_t *a2) {\n int v3;\n int v4;\n int v5;\n void *ptr;\n char *dest;\n ptr = 0LL;\n *a2 = 0;\n v4 = strlen(a1);\n v3 = 0;\n while (v3 < v4) {\n if (((*__ctype_b_loc())[(unsigned char)a1[v3]] & 512) != 0) {\n v5 = v3++;\n while (v3 < v4 && ((*__ctype_b_loc())[(unsigned char)a1[v3]] & 512) == 0)\n ++v3;\n dest = (char *)malloc(v3 - v5 + 1);\n strncpy(dest, &a1[v5], v3 - v5);\n dest[v3 - v5] = 0;\n ptr = realloc(ptr, 8LL * (*a2 + 1));\n *((uint64_t *)ptr + (int)(*a2)++) = dest;\n } else {\n ++v3;\n }\n }\n return ptr;\n}" + }, + { + "index": 15, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(const char* text, int* count) {\n char** result = NULL;\n *count = 0;\n int len = strlen(text);\n int i = 0;\n while (i < len) {\n if (islower((unsigned char)text[i])) {\n int start = i;\n i++;\n while (i < len && !islower((unsigned char)text[i])) {\n i++;\n }\n int end = i;\n int substr_len = end - start;\n char* substr = (char*)malloc(substr_len + 1);\n strncpy(substr, text + start, substr_len);\n substr[substr_len] = '\\0';\n result = (char**)realloc(result, sizeof(char*) * (*count + 1));\n result[*count] = substr;\n (*count)++;\n } else {\n i++;\n }\n }\n return result;\n}", + "test": "int main() {\n\n // Test case 1\n\n int count1;\n\n char** res1 = func0(\"AbCd\", &count1);\n\n assert(count1 == 2);\n\n assert(strcmp(res1[0], \"bC\") == 0);\n\n assert(strcmp(res1[1], \"d\") == 0);\n\n for(int i = 0; i < count1; i++) free(res1[i]);\n\n free(res1);\n\n\n\n // Test case 2\n\n int count2;\n\n char** res2 = func0(\"Python\", &count2);\n\n assert(count2 == 5);\n\n assert(strcmp(res2[0], \"y\") == 0);\n\n assert(strcmp(res2[1], \"t\") == 0);\n\n assert(strcmp(res2[2], \"h\") == 0);\n\n assert(strcmp(res2[3], \"o\") == 0);\n\n assert(strcmp(res2[4], \"n\") == 0);\n\n for(int i = 0; i < count2; i++) free(res2[i]);\n\n free(res2);\n\n\n\n // Test case 3\n\n int count3;\n\n char** res3 = func0(\"Programming\", &count3);\n\n assert(count3 == 10);\n\n assert(strcmp(res3[0], \"r\") == 0);\n\n assert(strcmp(res3[1], \"o\") == 0);\n\n assert(strcmp(res3[2], \"g\") == 0);\n\n assert(strcmp(res3[3], \"r\") == 0);\n\n assert(strcmp(res3[4], \"a\") == 0);\n\n assert(strcmp(res3[5], \"m\") == 0);\n\n assert(strcmp(res3[6], \"m\") == 0);\n\n assert(strcmp(res3[7], \"i\") == 0);\n\n assert(strcmp(res3[8], \"n\") == 0);\n\n assert(strcmp(res3[9], \"g\") == 0);\n\n for(int i = 0; i < count3; i++) free(res3[i]);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov %rdi,%r12\nmovl $0x0,(%rsi)\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nsub $0x1,%rax\ntest %eax,%eax\njle 130e \nmov %rsi,%r15\nmov %eax,%r13d\ncallq 1110 <__ctype_b_loc@plt>\nmov %rax,(%rsp)\nmov $0x0,%esi\nmovq $0x0,0x8(%rsp)\njmp 126f \nadd $0x1,%esi\ncmp %esi,%r13d\njle 1317 \nmov (%rsp),%rax\nmov (%rax),%rcx\nmovslq %esi,%rbp\nadd %r12,%rbp\nmovzbl 0x0(%rbp),%eax\ntestb $0x2,0x1(%rcx,%rax,2)\nje 1263 \nlea 0x1(%rsi),%ebx\ncmp %ebx,%r13d\njle 12ac \nmovslq %ebx,%rax\nmov %eax,%ebx\nmovzbl (%r12,%rax,1),%edx\ntestb $0x2,0x1(%rcx,%rdx,2)\njne 12ac \nlea 0x1(%rax),%ebx\nadd $0x1,%rax\ncmp %eax,%r13d\njg 1292 \nmov %ebx,%r14d\nsub %esi,%r14d\nlea 0x1(%r14),%edi\nmovslq %edi,%rdi\ncallq 10f0 \nmovslq %r14d,%r14\nmov %r14,%rdx\nmov %rbp,%rsi\nmov %rax,%rbp\nmov %rax,%rdi\ncallq 10c0 \nmovb $0x0,0x0(%rbp,%r14,1)\nmov (%r15),%eax\nlea 0x1(%rax),%esi\nmovslq %esi,%rsi\nshl $0x3,%rsi\nmov 0x8(%rsp),%rdi\ncallq 1100 \nmov %rax,%rdi\nmov %rax,0x8(%rsp)\nmov (%r15),%eax\nmovslq %eax,%rdx\nmov %rbp,(%rdi,%rdx,8)\nadd $0x1,%eax\nmov %eax,(%r15)\nmov %ebx,%esi\njmpq 1266 \nmovq $0x0,0x8(%rsp)\nmov 0x8(%rsp),%rax\nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov r13, rdi\nmov r15, rsi\nmov dword ptr [rsi], 0\ncall _strlen\ntest eax, eax\njle loc_1348\nmov r12d, eax\ncall ___ctype_b_loc\nmov [rsp+58h+var_50], rax\nmov esi, 0\nmov [rsp+58h+ptr], 0\njmp loc_1326\nloc_1294:\nlea ebx, [rsi+1]\ncmp r12d, ebx\njle short loc_12B8\nmovsxd rax, ebx\nadd rax, r13\nloc_12A2:\nmovzx edx, byte ptr [rax]\ntest byte ptr [rcx+rdx*2+1], 2\njnz short loc_12B8\nadd ebx, 1\nadd rax, 1\ncmp r12d, ebx\njnz short loc_12A2\nloc_12B8:\nmov r14d, ebx\nsub r14d, esi\nlea eax, [r14+1]\ncdqe\nmov [rsp+58h+var_40], rax\nmov rdi, rax; size\ncall _malloc\nmovsxd r14, r14d\nmov rcx, [rsp+58h+var_40]\nmov rdx, r14\nmov rsi, rbp\nmov rbp, rax\nmov rdi, rax\ncall ___strncpy_chk\nmov byte ptr [rbp+r14+0], 0\nmov eax, [r15]\nlea esi, [rax+1]\nmovsxd rsi, esi\nshl rsi, 3; size\nmov rdi, [rsp+58h+ptr]; ptr\ncall _realloc\nmov rdi, rax\nmov [rsp+58h+ptr], rax\nmov eax, [r15]\nmovsxd rdx, eax\nmov [rdi+rdx*8], rbp\nadd eax, 1\nmov [r15], eax\nmov esi, ebx\nloc_1321:\ncmp esi, r12d\njge short loc_1351\nloc_1326:\nmov rax, [rsp+58h+var_50]\nmov rcx, [rax]\nmovsxd rbp, esi\nadd rbp, r13\nmovzx eax, byte ptr [rbp+0]\ntest byte ptr [rcx+rax*2+1], 2\njnz loc_1294\nadd esi, 1\njmp short loc_1321\nloc_1348:\nmov [rsp+58h+ptr], 0\nloc_1351:\nmov rax, [rsp+58h+ptr]\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "void *__fastcall func0(const char *a1, int *a2)\n{\n int v3; // eax\n int v4; // r12d\n int v5; // esi\n int v6; // ebx\n const char *v7; // rax\n _BYTE *v8; // rbp\n int v9; // eax\n const unsigned __int16 **v11; // [rsp+8h] [rbp-50h]\n void *ptr; // [rsp+10h] [rbp-48h]\n\n *a2 = 0;\n v3 = strlen(a1);\n if ( v3 <= 0 )\n return 0LL;\n v4 = v3;\n v11 = __ctype_b_loc();\n v5 = 0;\n ptr = 0LL;\n do\n {\n if ( ((*v11)[(unsigned __int8)a1[v5]] & 0x200) != 0 )\n {\n v6 = v5 + 1;\n if ( v4 > v5 + 1 )\n {\n v7 = &a1[v6];\n do\n {\n if ( ((*v11)[*(unsigned __int8 *)v7] & 0x200) != 0 )\n break;\n ++v6;\n ++v7;\n }\n while ( v4 != v6 );\n }\n v8 = malloc(v6 - v5 + 1);\n __strncpy_chk(v8, &a1[v5], v6 - v5, v6 - v5 + 1);\n v8[v6 - v5] = 0;\n ptr = realloc(ptr, 8LL * (*a2 + 1));\n v9 = *a2;\n *((_QWORD *)ptr + *a2) = v8;\n *a2 = v9 + 1;\n v5 = v6;\n }\n else\n {\n ++v5;\n }\n }\n while ( v5 < v4 );\n return ptr;\n}", + "ida_strip_asm": "sub_1249:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov r13, rdi\nmov r15, rsi\nmov dword ptr [rsi], 0\ncall _strlen\ntest eax, eax\njle loc_1348\nmov r12d, eax\ncall ___ctype_b_loc\nmov [rsp+58h+var_50], rax\nmov esi, 0\nmov [rsp+58h+ptr], 0\njmp loc_1326\nloc_1294:\nlea ebx, [rsi+1]\ncmp r12d, ebx\njle short loc_12B8\nmovsxd rax, ebx\nadd rax, r13\nloc_12A2:\nmovzx edx, byte ptr [rax]\ntest byte ptr [rcx+rdx*2+1], 2\njnz short loc_12B8\nadd ebx, 1\nadd rax, 1\ncmp r12d, ebx\njnz short loc_12A2\nloc_12B8:\nmov r14d, ebx\nsub r14d, esi\nlea eax, [r14+1]\ncdqe\nmov [rsp+58h+var_40], rax\nmov rdi, rax; size\ncall _malloc\nmovsxd r14, r14d\nmov rcx, [rsp+58h+var_40]\nmov rdx, r14\nmov rsi, rbp\nmov rbp, rax\nmov rdi, rax\ncall ___strncpy_chk\nmov byte ptr [rbp+r14+0], 0\nmov eax, [r15]\nlea esi, [rax+1]\nmovsxd rsi, esi\nshl rsi, 3; size\nmov rdi, [rsp+58h+ptr]; ptr\ncall _realloc\nmov rdi, rax\nmov [rsp+58h+ptr], rax\nmov eax, [r15]\nmovsxd rdx, eax\nmov [rdi+rdx*8], rbp\nadd eax, 1\nmov [r15], eax\nmov esi, ebx\nloc_1321:\ncmp esi, r12d\njge short loc_1351\nloc_1326:\nmov rax, [rsp+58h+var_50]\nmov rcx, [rax]\nmovsxd rbp, esi\nadd rbp, r13\nmovzx eax, byte ptr [rbp+0]\ntest byte ptr [rcx+rax*2+1], 2\njnz loc_1294\nadd esi, 1\njmp short loc_1321\nloc_1348:\nmov [rsp+58h+ptr], 0\nloc_1351:\nmov rax, [rsp+58h+ptr]\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "void *__fastcall sub_1249(const char *a1, int *a2)\n{\n int v3; // eax\n int v4; // r12d\n int v5; // esi\n int v6; // ebx\n const char *v7; // rax\n _BYTE *v8; // rbp\n int v9; // eax\n const unsigned __int16 **v11; // [rsp+8h] [rbp-50h]\n void *ptr; // [rsp+10h] [rbp-48h]\n\n *a2 = 0;\n v3 = strlen(a1);\n if ( v3 <= 0 )\n return 0LL;\n v4 = v3;\n v11 = __ctype_b_loc();\n v5 = 0;\n ptr = 0LL;\n do\n {\n if ( ((*v11)[(unsigned __int8)a1[v5]] & 0x200) != 0 )\n {\n v6 = v5 + 1;\n if ( v4 > v5 + 1 )\n {\n v7 = &a1[v6];\n do\n {\n if ( ((*v11)[*(unsigned __int8 *)v7] & 0x200) != 0 )\n break;\n ++v6;\n ++v7;\n }\n while ( v4 != v6 );\n }\n v8 = malloc(v6 - v5 + 1);\n __strncpy_chk(v8, &a1[v5], v6 - v5, v6 - v5 + 1);\n v8[v6 - v5] = 0;\n ptr = realloc(ptr, 8LL * (*a2 + 1));\n v9 = *a2;\n *((_QWORD *)ptr + *a2) = v8;\n *a2 = v9 + 1;\n v5 = v6;\n }\n else\n {\n ++v5;\n }\n }\n while ( v5 < v4 );\n return ptr;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1249(const char *a1, int *a2) {\n int v3;\n int v4;\n int v5;\n int v6;\n const char *v7;\n uint8_t *v8;\n int v9;\n const unsigned short **v11;\n void *ptr;\n *a2 = 0;\n v3 = strlen(a1);\n if (v3 <= 0) return 0LL;\n v4 = v3;\n v11 = __ctype_b_loc();\n v5 = 0;\n ptr = 0LL;\n do {\n if (((*v11)[(unsigned char)a1[v5]] & 512) != 0) {\n v6 = v5 + 1;\n if (v4 > v5 + 1) {\n v7 = &a1[v6];\n do {\n if (((*v11)[*(unsigned char *)v7] & 512) != 0) break;\n ++v6;\n ++v7;\n } while (v4 != v6);\n }\n v8 = malloc(v6 - v5 + 1);\n __strncpy_chk(v8, &a1[v5], v6 - v5, v6 - v5 + 1);\n v8[v6 - v5] = 0;\n ptr = realloc(ptr, 8LL * (*a2 + 1));\n v9 = *a2;\n *((uint64_t *)ptr + *a2) = v8;\n *a2 = v9 + 1;\n v5 = v6;\n } else {\n ++v5;\n }\n } while (v5 < v4);\n return ptr;\n}", + "ida_pseudo_norm": "void *func0(const char *a1, int *a2) {\n int v3;\n int v4;\n int v5;\n int v6;\n const char *v7;\n uint8_t *v8;\n int v9;\n const unsigned short **v11;\n void *ptr;\n *a2 = 0;\n v3 = strlen(a1);\n if (v3 <= 0) return 0LL;\n v4 = v3;\n v11 = __ctype_b_loc();\n v5 = 0;\n ptr = 0LL;\n do {\n if (((*v11)[(unsigned char)a1[v5]] & 512) != 0) {\n v6 = v5 + 1;\n if (v4 > v5 + 1) {\n v7 = &a1[v6];\n do {\n if (((*v11)[*(unsigned char *)v7] & 512) != 0) break;\n ++v6;\n ++v7;\n } while (v4 != v6);\n }\n v8 = malloc(v6 - v5 + 1);\n __strncpy_chk(v8, &a1[v5], v6 - v5, v6 - v5 + 1);\n v8[v6 - v5] = 0;\n ptr = realloc(ptr, 8LL * (*a2 + 1));\n v9 = *a2;\n *((uint64_t *)ptr + *a2) = v8;\n *a2 = v9 + 1;\n v5 = v6;\n } else {\n ++v5;\n }\n } while (v5 < v4);\n return ptr;\n}" + }, + { + "index": 15, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(const char* text, int* count) {\n char** result = NULL;\n *count = 0;\n int len = strlen(text);\n int i = 0;\n while (i < len) {\n if (islower((unsigned char)text[i])) {\n int start = i;\n i++;\n while (i < len && !islower((unsigned char)text[i])) {\n i++;\n }\n int end = i;\n int substr_len = end - start;\n char* substr = (char*)malloc(substr_len + 1);\n strncpy(substr, text + start, substr_len);\n substr[substr_len] = '\\0';\n result = (char**)realloc(result, sizeof(char*) * (*count + 1));\n result[*count] = substr;\n (*count)++;\n } else {\n i++;\n }\n }\n return result;\n}", + "test": "int main() {\n\n // Test case 1\n\n int count1;\n\n char** res1 = func0(\"AbCd\", &count1);\n\n assert(count1 == 2);\n\n assert(strcmp(res1[0], \"bC\") == 0);\n\n assert(strcmp(res1[1], \"d\") == 0);\n\n for(int i = 0; i < count1; i++) free(res1[i]);\n\n free(res1);\n\n\n\n // Test case 2\n\n int count2;\n\n char** res2 = func0(\"Python\", &count2);\n\n assert(count2 == 5);\n\n assert(strcmp(res2[0], \"y\") == 0);\n\n assert(strcmp(res2[1], \"t\") == 0);\n\n assert(strcmp(res2[2], \"h\") == 0);\n\n assert(strcmp(res2[3], \"o\") == 0);\n\n assert(strcmp(res2[4], \"n\") == 0);\n\n for(int i = 0; i < count2; i++) free(res2[i]);\n\n free(res2);\n\n\n\n // Test case 3\n\n int count3;\n\n char** res3 = func0(\"Programming\", &count3);\n\n assert(count3 == 10);\n\n assert(strcmp(res3[0], \"r\") == 0);\n\n assert(strcmp(res3[1], \"o\") == 0);\n\n assert(strcmp(res3[2], \"g\") == 0);\n\n assert(strcmp(res3[3], \"r\") == 0);\n\n assert(strcmp(res3[4], \"a\") == 0);\n\n assert(strcmp(res3[5], \"m\") == 0);\n\n assert(strcmp(res3[6], \"m\") == 0);\n\n assert(strcmp(res3[7], \"i\") == 0);\n\n assert(strcmp(res3[8], \"n\") == 0);\n\n assert(strcmp(res3[9], \"g\") == 0);\n\n for(int i = 0; i < count3; i++) free(res3[i]);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\nmov %rdi,%r13\npush %r12\npush %rbp\npush %rbx\nsub $0x28,%rsp\nmovl $0x0,(%rsi)\nmov %rsi,0x8(%rsp)\ncallq 10e0 \ntest %eax,%eax\njle 1802 \nmov %eax,%r14d\nxor %ebx,%ebx\ncallq 1130 <__ctype_b_loc@plt>\nmov 0x8(%rsp),%rcx\nxor %r8d,%r8d\nmov (%rax),%r15\njmp 16f3 \nnopl 0x0(%rax)\nmov %edx,%ebx\ncmp %ebx,%r14d\njle 17bd \nmovslq %ebx,%rbp\nlea 0x1(%rbx),%edx\nadd %r13,%rbp\nmovzbl 0x0(%rbp),%eax\ntestb $0x2,0x1(%r15,%rax,2)\nje 16e8 \nmovslq %edx,%rax\ncmp %edx,%r14d\njg 1728 \njmpq 17ed \nnopl (%rax)\nlea 0x1(%rax),%edx\nadd $0x1,%rax\ncmp %eax,%r14d\njle 17d0 \nmovzbl 0x0(%r13,%rax,1),%edx\nmov %eax,%r12d\ntestb $0x2,0x1(%r15,%rdx,2)\nje 1718 \nsub %ebx,%r12d\nmov %eax,%ebx\nmovslq %r12d,%rsi\nlea 0x1(%r12),%edi\nmov %rsi,0x8(%rsp)\nmovslq %edi,%rdi\nmov %rcx,0x18(%rsp)\nmov %r8,0x10(%rsp)\ncallq 1110 \nmov 0x8(%rsp),%rdx\nmov %rbp,%rsi\nmov %rax,%rdi\nmov %rax,%r12\ncallq 10d0 \nmov 0x8(%rsp),%rax\nmov 0x18(%rsp),%rcx\nmov 0x10(%rsp),%r8\nmovb $0x0,(%r12,%rax,1)\nmov (%rcx),%eax\nmov %r8,%rdi\nmov %rcx,0x8(%rsp)\nlea 0x1(%rax),%esi\nmovslq %esi,%rsi\nshl $0x3,%rsi\ncallq 1120 \nmov 0x8(%rsp),%rcx\nmov %rax,%r8\nmovslq (%rcx),%rdx\nmov %rdx,%rax\nmov %r12,(%r8,%rdx,8)\nadd $0x1,%eax\nmov %eax,(%rcx)\ncmp %ebx,%r14d\njg 16f3 \nadd $0x28,%rsp\nmov %r8,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmov %edx,%r12d\nsub %ebx,%r12d\nmov %edx,%ebx\nlea 0x1(%r12),%edi\nmovslq %r12d,%rax\nmov %rax,0x8(%rsp)\nmovslq %edi,%rdi\njmpq 174e \nmovq $0x1,0x8(%rsp)\nmov %edx,%ebx\nmov $0x2,%edi\njmpq 174e \nxor %r8d,%r8d\njmp 17bd \nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov r15, rsi\npush r14\npush r13\nmov r13, rdi\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov dword ptr [rsi], 0\ncall _strlen\ntest eax, eax\njle loc_17EF\nmov ebp, eax\nxor ebx, ebx\ncall ___ctype_b_loc\nxor r8d, r8d\nmov r12, [rax]\njmp short loc_16EA\nloc_16E0:\nmov ebx, eax\ncmp ebx, ebp\njge loc_17AB\nloc_16EA:\nmovsxd rsi, ebx\nlea eax, [rbx+1]\nadd rsi, r13\nmovzx edx, byte ptr [rsi]\ntest byte ptr [r12+rdx*2+1], 2\njz short loc_16E0\nmovsxd rdx, eax\nadd rdx, r13\ncmp ebp, eax\njg short loc_171F\njmp loc_17DB\nloc_1710:\nadd eax, 1\nadd rdx, 1\ncmp ebp, eax\njz loc_17C0\nloc_171F:\nmovzx ecx, byte ptr [rdx]\ntest byte ptr [r12+rcx*2+1], 2\njz short loc_1710\nmov r14d, eax\nsub r14d, ebx\nmov ebx, eax\nmovsxd rdi, r14d\nlea ecx, [r14+1]\nmov [rsp+58h+var_58], rdi\nmovsxd rcx, ecx\nloc_1740:\nmov rdi, rcx; size\nmov [rsp+58h+ptr], r8\nmov [rsp+58h+var_48], rsi\nmov [rsp+58h+var_50], rcx\ncall _malloc\nmov rdx, [rsp+58h+var_58]\nmov rcx, [rsp+58h+var_50]\nmov rsi, [rsp+58h+var_48]\nmov rdi, rax\nmov r14, rax\ncall ___strncpy_chk\nmov rax, [rsp+58h+var_58]\nmov rdi, [rsp+58h+ptr]; ptr\nmov byte ptr [r14+rax], 0\nmov eax, [r15]\nlea esi, [rax+1]\nmovsxd rsi, esi\nshl rsi, 3; size\ncall _realloc\nmovsxd rdx, dword ptr [r15]\nmov r8, rax\nmov rax, rdx\nmov [r8+rdx*8], r14\nadd eax, 1\nmov [r15], eax\ncmp ebx, ebp\njl loc_16EA\nloc_17AB:\nadd rsp, 28h\nmov rax, r8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_17C0:\nmov r14d, ebp\nsub r14d, ebx\nmov ebx, ebp\nlea ecx, [r14+1]\nmovsxd rax, r14d\nmov [rsp+58h+var_58], rax\nmovsxd rcx, ecx\njmp loc_1740\nloc_17DB:\nmov [rsp+58h+var_58], 1\nmov ebx, eax\nmov ecx, 2\njmp loc_1740\nloc_17EF:\nxor r8d, r8d\njmp short loc_17AB", + "ida_pseudo": "void *__fastcall func0(const char *a1, int *a2)\n{\n int v3; // eax\n int v4; // ebp\n int v5; // ebx\n const unsigned __int16 **v6; // rax\n void *v7; // r8\n const unsigned __int16 *v8; // r12\n int v9; // eax\n const char *v10; // rsi\n const char *v11; // rdx\n int v12; // r14d\n _BYTE *v13; // r14\n int v14; // eax\n int v16; // r14d\n size_t v17; // rcx\n __int64 v18; // [rsp+0h] [rbp-58h]\n size_t v19; // [rsp+8h] [rbp-50h]\n void *ptr; // [rsp+18h] [rbp-40h]\n\n *a2 = 0;\n v3 = strlen(a1);\n if ( v3 <= 0 )\n return 0LL;\n v4 = v3;\n v5 = 0;\n v6 = __ctype_b_loc();\n v7 = 0LL;\n v8 = *v6;\n do\n {\n while ( 1 )\n {\n v9 = v5 + 1;\n v10 = &a1[v5];\n if ( (v8[*(unsigned __int8 *)v10] & 0x200) != 0 )\n break;\n ++v5;\n if ( v9 >= v4 )\n return v7;\n }\n v11 = &a1[v9];\n if ( v4 > v9 )\n {\n do\n {\n if ( (v8[*(unsigned __int8 *)v11] & 0x200) != 0 )\n {\n v12 = v9 - v5;\n v5 = v9;\n v18 = v12;\n v17 = v12 + 1;\n goto LABEL_10;\n }\n ++v9;\n ++v11;\n }\n while ( v4 != v9 );\n v16 = v4 - v5;\n v5 = v4;\n v18 = v16;\n v17 = v16 + 1;\n }\n else\n {\n v18 = 1LL;\n ++v5;\n v17 = 2LL;\n }\nLABEL_10:\n ptr = v7;\n v19 = v17;\n v13 = malloc(v17);\n __strncpy_chk(v13, v10, v18, v19);\n v13[v18] = 0;\n v7 = realloc(ptr, 8LL * (*a2 + 1));\n v14 = *a2;\n *((_QWORD *)v7 + *a2) = v13;\n *a2 = v14 + 1;\n }\n while ( v5 < v4 );\n return v7;\n}", + "ida_strip_asm": "sub_16A0:\nendbr64\npush r15\nmov r15, rsi\npush r14\npush r13\nmov r13, rdi\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov dword ptr [rsi], 0\ncall _strlen\ntest eax, eax\njle loc_17EF\nmov ebp, eax\nxor ebx, ebx\ncall ___ctype_b_loc\nxor r8d, r8d\nmov r12, [rax]\njmp short loc_16EA\nloc_16E0:\nmov ebx, eax\ncmp ebx, ebp\njge loc_17AB\nloc_16EA:\nmovsxd rsi, ebx\nlea eax, [rbx+1]\nadd rsi, r13\nmovzx edx, byte ptr [rsi]\ntest byte ptr [r12+rdx*2+1], 2\njz short loc_16E0\nmovsxd rdx, eax\nadd rdx, r13\ncmp ebp, eax\njg short loc_171F\njmp loc_17DB\nloc_1710:\nadd eax, 1\nadd rdx, 1\ncmp ebp, eax\njz loc_17C0\nloc_171F:\nmovzx ecx, byte ptr [rdx]\ntest byte ptr [r12+rcx*2+1], 2\njz short loc_1710\nmov r14d, eax\nsub r14d, ebx\nmov ebx, eax\nmovsxd rdi, r14d\nlea ecx, [r14+1]\nmov [rsp+58h+var_58], rdi\nmovsxd rcx, ecx\nloc_1740:\nmov rdi, rcx; size\nmov [rsp+58h+ptr], r8\nmov [rsp+58h+var_48], rsi\nmov [rsp+58h+var_50], rcx\ncall _malloc\nmov rdx, [rsp+58h+var_58]\nmov rcx, [rsp+58h+var_50]\nmov rsi, [rsp+58h+var_48]\nmov rdi, rax\nmov r14, rax\ncall ___strncpy_chk\nmov rax, [rsp+58h+var_58]\nmov rdi, [rsp+58h+ptr]; ptr\nmov byte ptr [r14+rax], 0\nmov eax, [r15]\nlea esi, [rax+1]\nmovsxd rsi, esi\nshl rsi, 3; size\ncall _realloc\nmovsxd rdx, dword ptr [r15]\nmov r8, rax\nmov rax, rdx\nmov [r8+rdx*8], r14\nadd eax, 1\nmov [r15], eax\ncmp ebx, ebp\njl loc_16EA\nloc_17AB:\nadd rsp, 28h\nmov rax, r8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_17C0:\nmov r14d, ebp\nsub r14d, ebx\nmov ebx, ebp\nlea ecx, [r14+1]\nmovsxd rax, r14d\nmov [rsp+58h+var_58], rax\nmovsxd rcx, ecx\njmp loc_1740\nloc_17DB:\nmov [rsp+58h+var_58], 1\nmov ebx, eax\nmov ecx, 2\njmp loc_1740\nloc_17EF:\nxor r8d, r8d\njmp short loc_17AB", + "ida_strip_pseudo": "void *__fastcall sub_16A0(const char *a1, int *a2)\n{\n int v3; // eax\n int v4; // ebp\n int v5; // ebx\n const unsigned __int16 **v6; // rax\n void *v7; // r8\n const unsigned __int16 *v8; // r12\n int v9; // eax\n const char *v10; // rsi\n const char *v11; // rdx\n int v12; // r14d\n _BYTE *v13; // r14\n int v14; // eax\n int v16; // r14d\n size_t v17; // rcx\n __int64 v18; // [rsp+0h] [rbp-58h]\n size_t v19; // [rsp+8h] [rbp-50h]\n void *ptr; // [rsp+18h] [rbp-40h]\n\n *a2 = 0;\n v3 = strlen(a1);\n if ( v3 <= 0 )\n return 0LL;\n v4 = v3;\n v5 = 0;\n v6 = __ctype_b_loc();\n v7 = 0LL;\n v8 = *v6;\n do\n {\n while ( 1 )\n {\n v9 = v5 + 1;\n v10 = &a1[v5];\n if ( (v8[*(unsigned __int8 *)v10] & 0x200) != 0 )\n break;\n ++v5;\n if ( v9 >= v4 )\n return v7;\n }\n v11 = &a1[v9];\n if ( v4 > v9 )\n {\n do\n {\n if ( (v8[*(unsigned __int8 *)v11] & 0x200) != 0 )\n {\n v12 = v9 - v5;\n v5 = v9;\n v18 = v12;\n v17 = v12 + 1;\n goto LABEL_10;\n }\n ++v9;\n ++v11;\n }\n while ( v4 != v9 );\n v16 = v4 - v5;\n v5 = v4;\n v18 = v16;\n v17 = v16 + 1;\n }\n else\n {\n v18 = 1LL;\n ++v5;\n v17 = 2LL;\n }\nLABEL_10:\n ptr = v7;\n v19 = v17;\n v13 = malloc(v17);\n __strncpy_chk(v13, v10, v18, v19);\n v13[v18] = 0;\n v7 = realloc(ptr, 8LL * (*a2 + 1));\n v14 = *a2;\n *((_QWORD *)v7 + *a2) = v13;\n *a2 = v14 + 1;\n }\n while ( v5 < v4 );\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_16A0(const char *a1, int *a2) {\n int v3;\n int v4;\n int v5;\n const unsigned short **v6;\n void *v7;\n const unsigned short *v8;\n int v9;\n const char *v10;\n const char *v11;\n int v12;\n uint8_t *v13;\n int v14;\n int v16;\n unsigned int v17;\n long long v18;\n unsigned int v19;\n void *ptr;\n *a2 = 0;\n v3 = strlen(a1);\n if (v3 <= 0) return 0LL;\n v4 = v3;\n v5 = 0;\n v6 = __ctype_b_loc();\n v7 = 0LL;\n v8 = *v6;\n do {\n while (1) {\n v9 = v5 + 1;\n v10 = &a1[v5];\n if ((v8[*(unsigned char *)v10] & 512) != 0) break;\n ++v5;\n if (v9 >= v4) return v7;\n }\n v11 = &a1[v9];\n if (v4 > v9) {\n do {\n if ((v8[*(unsigned char *)v11] & 512) != 0) {\n v12 = v9 - v5;\n v5 = v9;\n v18 = v12;\n v17 = v12 + 1;\n goto LABEL_10;\n }\n ++v9;\n ++v11;\n } while (v4 != v9);\n v16 = v4 - v5;\n v5 = v4;\n v18 = v16;\n v17 = v16 + 1;\n } else {\n v18 = 1LL;\n ++v5;\n v17 = 2LL;\n }\n LABEL_10:\n ptr = v7;\n v19 = v17;\n v13 = malloc(v17);\n __strncpy_chk(v13, v10, v18, v19);\n v13[v18] = 0;\n v7 = realloc(ptr, 8LL * (*a2 + 1));\n v14 = *a2;\n *((uint64_t *)v7 + *a2) = v13;\n *a2 = v14 + 1;\n } while (v5 < v4);\n return v7;\n}", + "ida_pseudo_norm": "void *func0(const char *a1, int *a2) {\n int v3;\n int v4;\n int v5;\n const unsigned short **v6;\n void *v7;\n const unsigned short *v8;\n int v9;\n const char *v10;\n const char *v11;\n int v12;\n uint8_t *v13;\n int v14;\n int v16;\n unsigned int v17;\n long long v18;\n unsigned int v19;\n void *ptr;\n *a2 = 0;\n v3 = strlen(a1);\n if (v3 <= 0) return 0LL;\n v4 = v3;\n v5 = 0;\n v6 = __ctype_b_loc();\n v7 = 0LL;\n v8 = *v6;\n do {\n while (1) {\n v9 = v5 + 1;\n v10 = &a1[v5];\n if ((v8[*(unsigned char *)v10] & 512) != 0) break;\n ++v5;\n if (v9 >= v4) return v7;\n }\n v11 = &a1[v9];\n if (v4 > v9) {\n do {\n if ((v8[*(unsigned char *)v11] & 512) != 0) {\n v12 = v9 - v5;\n v5 = v9;\n v18 = v12;\n v17 = v12 + 1;\n goto LABEL_10;\n }\n ++v9;\n ++v11;\n } while (v4 != v9);\n v16 = v4 - v5;\n v5 = v4;\n v18 = v16;\n v17 = v16 + 1;\n } else {\n v18 = 1LL;\n ++v5;\n v17 = 2LL;\n }\n LABEL_10:\n ptr = v7;\n v19 = v17;\n v13 = malloc(v17);\n __strncpy_chk(v13, v10, v18, v19);\n v13[v18] = 0;\n v7 = realloc(ptr, 8LL * (*a2 + 1));\n v14 = *a2;\n *((uint64_t *)v7 + *a2) = v13;\n *a2 = v14 + 1;\n } while (v5 < v4);\n return v7;\n}" + }, + { + "index": 15, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(const char* text, int* count) {\n char** result = NULL;\n *count = 0;\n int len = strlen(text);\n int i = 0;\n while (i < len) {\n if (islower((unsigned char)text[i])) {\n int start = i;\n i++;\n while (i < len && !islower((unsigned char)text[i])) {\n i++;\n }\n int end = i;\n int substr_len = end - start;\n char* substr = (char*)malloc(substr_len + 1);\n strncpy(substr, text + start, substr_len);\n substr[substr_len] = '\\0';\n result = (char**)realloc(result, sizeof(char*) * (*count + 1));\n result[*count] = substr;\n (*count)++;\n } else {\n i++;\n }\n }\n return result;\n}", + "test": "int main() {\n\n // Test case 1\n\n int count1;\n\n char** res1 = func0(\"AbCd\", &count1);\n\n assert(count1 == 2);\n\n assert(strcmp(res1[0], \"bC\") == 0);\n\n assert(strcmp(res1[1], \"d\") == 0);\n\n for(int i = 0; i < count1; i++) free(res1[i]);\n\n free(res1);\n\n\n\n // Test case 2\n\n int count2;\n\n char** res2 = func0(\"Python\", &count2);\n\n assert(count2 == 5);\n\n assert(strcmp(res2[0], \"y\") == 0);\n\n assert(strcmp(res2[1], \"t\") == 0);\n\n assert(strcmp(res2[2], \"h\") == 0);\n\n assert(strcmp(res2[3], \"o\") == 0);\n\n assert(strcmp(res2[4], \"n\") == 0);\n\n for(int i = 0; i < count2; i++) free(res2[i]);\n\n free(res2);\n\n\n\n // Test case 3\n\n int count3;\n\n char** res3 = func0(\"Programming\", &count3);\n\n assert(count3 == 10);\n\n assert(strcmp(res3[0], \"r\") == 0);\n\n assert(strcmp(res3[1], \"o\") == 0);\n\n assert(strcmp(res3[2], \"g\") == 0);\n\n assert(strcmp(res3[3], \"r\") == 0);\n\n assert(strcmp(res3[4], \"a\") == 0);\n\n assert(strcmp(res3[5], \"m\") == 0);\n\n assert(strcmp(res3[6], \"m\") == 0);\n\n assert(strcmp(res3[7], \"i\") == 0);\n\n assert(strcmp(res3[8], \"n\") == 0);\n\n assert(strcmp(res3[9], \"g\") == 0);\n\n for(int i = 0; i < count3; i++) free(res3[i]);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\nmov %rdi,%r13\npush %r12\npush %rbp\npush %rbx\nsub $0x28,%rsp\nmovl $0x0,(%rsi)\nmov %rsi,0x8(%rsp)\ncallq 10e0 \ntest %eax,%eax\njle 1802 \nmov %eax,%r14d\nxor %ebx,%ebx\ncallq 1130 <__ctype_b_loc@plt>\nmov 0x8(%rsp),%rcx\nxor %r8d,%r8d\nmov (%rax),%r15\njmp 16f3 \nnopl 0x0(%rax)\nmov %edx,%ebx\ncmp %ebx,%r14d\njle 17bd \nmovslq %ebx,%rbp\nlea 0x1(%rbx),%edx\nadd %r13,%rbp\nmovzbl 0x0(%rbp),%eax\ntestb $0x2,0x1(%r15,%rax,2)\nje 16e8 \nmovslq %edx,%rax\ncmp %edx,%r14d\njg 1728 \njmpq 17ed \nnopl (%rax)\nlea 0x1(%rax),%edx\nadd $0x1,%rax\ncmp %eax,%r14d\njle 17d0 \nmovzbl 0x0(%r13,%rax,1),%edx\nmov %eax,%r12d\ntestb $0x2,0x1(%r15,%rdx,2)\nje 1718 \nsub %ebx,%r12d\nmov %eax,%ebx\nmovslq %r12d,%rsi\nlea 0x1(%r12),%edi\nmov %rsi,0x8(%rsp)\nmovslq %edi,%rdi\nmov %rcx,0x18(%rsp)\nmov %r8,0x10(%rsp)\ncallq 1110 \nmov 0x8(%rsp),%rdx\nmov %rbp,%rsi\nmov %rax,%rdi\nmov %rax,%r12\ncallq 10d0 \nmov 0x8(%rsp),%rax\nmov 0x18(%rsp),%rcx\nmov 0x10(%rsp),%r8\nmovb $0x0,(%r12,%rax,1)\nmov (%rcx),%eax\nmov %r8,%rdi\nmov %rcx,0x8(%rsp)\nlea 0x1(%rax),%esi\nmovslq %esi,%rsi\nshl $0x3,%rsi\ncallq 1120 \nmov 0x8(%rsp),%rcx\nmov %rax,%r8\nmovslq (%rcx),%rdx\nmov %rdx,%rax\nmov %r12,(%r8,%rdx,8)\nadd $0x1,%eax\nmov %eax,(%rcx)\ncmp %ebx,%r14d\njg 16f3 \nadd $0x28,%rsp\nmov %r8,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmov %edx,%r12d\nsub %ebx,%r12d\nmov %edx,%ebx\nlea 0x1(%r12),%edi\nmovslq %r12d,%rax\nmov %rax,0x8(%rsp)\nmovslq %edi,%rdi\njmpq 174e \nmovq $0x1,0x8(%rsp)\nmov %edx,%ebx\nmov $0x2,%edi\njmpq 174e \nxor %r8d,%r8d\njmp 17bd \nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov r15, rsi\npush r14\npush r13\nmov r13, rdi\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov dword ptr [rsi], 0\ncall _strlen\ntest eax, eax\njle loc_17EF\nmov ebp, eax\nxor ebx, ebx\ncall ___ctype_b_loc\nxor r8d, r8d\nmov r12, [rax]\njmp short loc_16EA\nloc_16E0:\nmov ebx, eax\ncmp ebx, ebp\njge loc_17AB\nloc_16EA:\nmovsxd rsi, ebx\nlea eax, [rbx+1]\nadd rsi, r13\nmovzx edx, byte ptr [rsi]\ntest byte ptr [r12+rdx*2+1], 2\njz short loc_16E0\nmovsxd rdx, eax\nadd rdx, r13\ncmp ebp, eax\njg short loc_171F\njmp loc_17DB\nloc_1710:\nadd eax, 1\nadd rdx, 1\ncmp ebp, eax\njz loc_17C0\nloc_171F:\nmovzx ecx, byte ptr [rdx]\ntest byte ptr [r12+rcx*2+1], 2\njz short loc_1710\nmov r14d, eax\nsub r14d, ebx\nmov ebx, eax\nmovsxd rdi, r14d\nlea ecx, [r14+1]\nmov [rsp+58h+var_58], rdi\nmovsxd rcx, ecx\nloc_1740:\nmov rdi, rcx; size\nmov [rsp+58h+ptr], r8\nmov [rsp+58h+var_48], rsi\nmov [rsp+58h+var_50], rcx\ncall _malloc\nmov rdx, [rsp+58h+var_58]\nmov rcx, [rsp+58h+var_50]\nmov rsi, [rsp+58h+var_48]\nmov rdi, rax\nmov r14, rax\ncall ___strncpy_chk\nmov rax, [rsp+58h+var_58]\nmov rdi, [rsp+58h+ptr]; ptr\nmov byte ptr [r14+rax], 0\nmov eax, [r15]\nlea esi, [rax+1]\nmovsxd rsi, esi\nshl rsi, 3; size\ncall _realloc\nmovsxd rdx, dword ptr [r15]\nmov r8, rax\nmov rax, rdx\nmov [r8+rdx*8], r14\nadd eax, 1\nmov [r15], eax\ncmp ebx, ebp\njl loc_16EA\nloc_17AB:\nadd rsp, 28h\nmov rax, r8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_17C0:\nmov r14d, ebp\nsub r14d, ebx\nmov ebx, ebp\nlea ecx, [r14+1]\nmovsxd rax, r14d\nmov [rsp+58h+var_58], rax\nmovsxd rcx, ecx\njmp loc_1740\nloc_17DB:\nmov [rsp+58h+var_58], 1\nmov ebx, eax\nmov ecx, 2\njmp loc_1740\nloc_17EF:\nxor r8d, r8d\njmp short loc_17AB", + "ida_pseudo": "void *__fastcall func0(const char *a1, int *a2)\n{\n int v3; // eax\n int v4; // ebp\n int v5; // ebx\n const unsigned __int16 **v6; // rax\n void *v7; // r8\n const unsigned __int16 *v8; // r12\n int v9; // eax\n const char *v10; // rsi\n const char *v11; // rdx\n int v12; // r14d\n _BYTE *v13; // r14\n int v14; // eax\n int v16; // r14d\n size_t v17; // rcx\n __int64 v18; // [rsp+0h] [rbp-58h]\n size_t v19; // [rsp+8h] [rbp-50h]\n void *ptr; // [rsp+18h] [rbp-40h]\n\n *a2 = 0;\n v3 = strlen(a1);\n if ( v3 <= 0 )\n return 0LL;\n v4 = v3;\n v5 = 0;\n v6 = __ctype_b_loc();\n v7 = 0LL;\n v8 = *v6;\n do\n {\n while ( 1 )\n {\n v9 = v5 + 1;\n v10 = &a1[v5];\n if ( (v8[*(unsigned __int8 *)v10] & 0x200) != 0 )\n break;\n ++v5;\n if ( v9 >= v4 )\n return v7;\n }\n v11 = &a1[v9];\n if ( v4 > v9 )\n {\n do\n {\n if ( (v8[*(unsigned __int8 *)v11] & 0x200) != 0 )\n {\n v12 = v9 - v5;\n v5 = v9;\n v18 = v12;\n v17 = v12 + 1;\n goto LABEL_10;\n }\n ++v9;\n ++v11;\n }\n while ( v4 != v9 );\n v16 = v4 - v5;\n v5 = v4;\n v18 = v16;\n v17 = v16 + 1;\n }\n else\n {\n v18 = 1LL;\n ++v5;\n v17 = 2LL;\n }\nLABEL_10:\n ptr = v7;\n v19 = v17;\n v13 = malloc(v17);\n __strncpy_chk(v13, v10, v18, v19);\n v13[v18] = 0;\n v7 = realloc(ptr, 8LL * (*a2 + 1));\n v14 = *a2;\n *((_QWORD *)v7 + *a2) = v13;\n *a2 = v14 + 1;\n }\n while ( v5 < v4 );\n return v7;\n}", + "ida_strip_asm": "sub_16A0:\nendbr64\npush r15\nmov r15, rsi\npush r14\npush r13\nmov r13, rdi\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov dword ptr [rsi], 0\ncall _strlen\ntest eax, eax\njle loc_17EF\nmov ebp, eax\nxor ebx, ebx\ncall ___ctype_b_loc\nxor r8d, r8d\nmov r12, [rax]\njmp short loc_16EA\nloc_16E0:\nmov ebx, eax\ncmp ebx, ebp\njge loc_17AB\nloc_16EA:\nmovsxd rsi, ebx\nlea eax, [rbx+1]\nadd rsi, r13\nmovzx edx, byte ptr [rsi]\ntest byte ptr [r12+rdx*2+1], 2\njz short loc_16E0\nmovsxd rdx, eax\nadd rdx, r13\ncmp ebp, eax\njg short loc_171F\njmp loc_17DB\nloc_1710:\nadd eax, 1\nadd rdx, 1\ncmp ebp, eax\njz loc_17C0\nloc_171F:\nmovzx ecx, byte ptr [rdx]\ntest byte ptr [r12+rcx*2+1], 2\njz short loc_1710\nmov r14d, eax\nsub r14d, ebx\nmov ebx, eax\nmovsxd rdi, r14d\nlea ecx, [r14+1]\nmov [rsp+58h+var_58], rdi\nmovsxd rcx, ecx\nloc_1740:\nmov rdi, rcx; size\nmov [rsp+58h+ptr], r8\nmov [rsp+58h+var_48], rsi\nmov [rsp+58h+var_50], rcx\ncall _malloc\nmov rdx, [rsp+58h+var_58]\nmov rcx, [rsp+58h+var_50]\nmov rsi, [rsp+58h+var_48]\nmov rdi, rax\nmov r14, rax\ncall ___strncpy_chk\nmov rax, [rsp+58h+var_58]\nmov rdi, [rsp+58h+ptr]; ptr\nmov byte ptr [r14+rax], 0\nmov eax, [r15]\nlea esi, [rax+1]\nmovsxd rsi, esi\nshl rsi, 3; size\ncall _realloc\nmovsxd rdx, dword ptr [r15]\nmov r8, rax\nmov rax, rdx\nmov [r8+rdx*8], r14\nadd eax, 1\nmov [r15], eax\ncmp ebx, ebp\njl loc_16EA\nloc_17AB:\nadd rsp, 28h\nmov rax, r8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_17C0:\nmov r14d, ebp\nsub r14d, ebx\nmov ebx, ebp\nlea ecx, [r14+1]\nmovsxd rax, r14d\nmov [rsp+58h+var_58], rax\nmovsxd rcx, ecx\njmp loc_1740\nloc_17DB:\nmov [rsp+58h+var_58], 1\nmov ebx, eax\nmov ecx, 2\njmp loc_1740\nloc_17EF:\nxor r8d, r8d\njmp short loc_17AB", + "ida_strip_pseudo": "void *__fastcall sub_16A0(const char *a1, int *a2)\n{\n int v3; // eax\n int v4; // ebp\n int v5; // ebx\n const unsigned __int16 **v6; // rax\n void *v7; // r8\n const unsigned __int16 *v8; // r12\n int v9; // eax\n const char *v10; // rsi\n const char *v11; // rdx\n int v12; // r14d\n _BYTE *v13; // r14\n int v14; // eax\n int v16; // r14d\n size_t v17; // rcx\n __int64 v18; // [rsp+0h] [rbp-58h]\n size_t v19; // [rsp+8h] [rbp-50h]\n void *ptr; // [rsp+18h] [rbp-40h]\n\n *a2 = 0;\n v3 = strlen(a1);\n if ( v3 <= 0 )\n return 0LL;\n v4 = v3;\n v5 = 0;\n v6 = __ctype_b_loc();\n v7 = 0LL;\n v8 = *v6;\n do\n {\n while ( 1 )\n {\n v9 = v5 + 1;\n v10 = &a1[v5];\n if ( (v8[*(unsigned __int8 *)v10] & 0x200) != 0 )\n break;\n ++v5;\n if ( v9 >= v4 )\n return v7;\n }\n v11 = &a1[v9];\n if ( v4 > v9 )\n {\n do\n {\n if ( (v8[*(unsigned __int8 *)v11] & 0x200) != 0 )\n {\n v12 = v9 - v5;\n v5 = v9;\n v18 = v12;\n v17 = v12 + 1;\n goto LABEL_10;\n }\n ++v9;\n ++v11;\n }\n while ( v4 != v9 );\n v16 = v4 - v5;\n v5 = v4;\n v18 = v16;\n v17 = v16 + 1;\n }\n else\n {\n v18 = 1LL;\n ++v5;\n v17 = 2LL;\n }\nLABEL_10:\n ptr = v7;\n v19 = v17;\n v13 = malloc(v17);\n __strncpy_chk(v13, v10, v18, v19);\n v13[v18] = 0;\n v7 = realloc(ptr, 8LL * (*a2 + 1));\n v14 = *a2;\n *((_QWORD *)v7 + *a2) = v13;\n *a2 = v14 + 1;\n }\n while ( v5 < v4 );\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_16A0(const char *a1, int *a2) {\n int v3;\n int v4;\n int v5;\n const unsigned short **v6;\n void *v7;\n const unsigned short *v8;\n int v9;\n const char *v10;\n const char *v11;\n int v12;\n uint8_t *v13;\n int v14;\n int v16;\n unsigned int v17;\n long long v18;\n unsigned int v19;\n void *ptr;\n *a2 = 0;\n v3 = strlen(a1);\n if (v3 <= 0) return 0LL;\n v4 = v3;\n v5 = 0;\n v6 = __ctype_b_loc();\n v7 = 0LL;\n v8 = *v6;\n do {\n while (1) {\n v9 = v5 + 1;\n v10 = &a1[v5];\n if ((v8[*(unsigned char *)v10] & 512) != 0) break;\n ++v5;\n if (v9 >= v4) return v7;\n }\n v11 = &a1[v9];\n if (v4 > v9) {\n do {\n if ((v8[*(unsigned char *)v11] & 512) != 0) {\n v12 = v9 - v5;\n v5 = v9;\n v18 = v12;\n v17 = v12 + 1;\n goto LABEL_10;\n }\n ++v9;\n ++v11;\n } while (v4 != v9);\n v16 = v4 - v5;\n v5 = v4;\n v18 = v16;\n v17 = v16 + 1;\n } else {\n v18 = 1LL;\n ++v5;\n v17 = 2LL;\n }\n LABEL_10:\n ptr = v7;\n v19 = v17;\n v13 = malloc(v17);\n __strncpy_chk(v13, v10, v18, v19);\n v13[v18] = 0;\n v7 = realloc(ptr, 8LL * (*a2 + 1));\n v14 = *a2;\n *((uint64_t *)v7 + *a2) = v13;\n *a2 = v14 + 1;\n } while (v5 < v4);\n return v7;\n}", + "ida_pseudo_norm": "void *func0(const char *a1, int *a2) {\n int v3;\n int v4;\n int v5;\n const unsigned short **v6;\n void *v7;\n const unsigned short *v8;\n int v9;\n const char *v10;\n const char *v11;\n int v12;\n uint8_t *v13;\n int v14;\n int v16;\n unsigned int v17;\n long long v18;\n unsigned int v19;\n void *ptr;\n *a2 = 0;\n v3 = strlen(a1);\n if (v3 <= 0) return 0LL;\n v4 = v3;\n v5 = 0;\n v6 = __ctype_b_loc();\n v7 = 0LL;\n v8 = *v6;\n do {\n while (1) {\n v9 = v5 + 1;\n v10 = &a1[v5];\n if ((v8[*(unsigned char *)v10] & 512) != 0) break;\n ++v5;\n if (v9 >= v4) return v7;\n }\n v11 = &a1[v9];\n if (v4 > v9) {\n do {\n if ((v8[*(unsigned char *)v11] & 512) != 0) {\n v12 = v9 - v5;\n v5 = v9;\n v18 = v12;\n v17 = v12 + 1;\n goto LABEL_10;\n }\n ++v9;\n ++v11;\n } while (v4 != v9);\n v16 = v4 - v5;\n v5 = v4;\n v18 = v16;\n v17 = v16 + 1;\n } else {\n v18 = 1LL;\n ++v5;\n v17 = 2LL;\n }\n LABEL_10:\n ptr = v7;\n v19 = v17;\n v13 = malloc(v17);\n __strncpy_chk(v13, v10, v18, v19);\n v13[v18] = 0;\n v7 = realloc(ptr, 8LL * (*a2 + 1));\n v14 = *a2;\n *((uint64_t *)v7 + *a2) = v13;\n *a2 = v14 + 1;\n } while (v5 < v4);\n return v7;\n}" + }, + { + "index": 16, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n regex_t regex;\n char* pattern = \"^[a-z]+_[a-z]+$\";\n regcomp(®ex, pattern, REG_EXTENDED);\n int reti = regexec(®ex, text, 0, NULL, 0);\n regfree(®ex);\n if (!reti)\n return \"Found a match!\";\n else\n return \"Not matched!\";\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"aab_cbbbc\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\"aab_Abbbc\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"Aaab_abbbc\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"aab-cbbbc\"), \"Not matched!\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x70,%rsp\nmov %rdi,-0x68(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0xdf9(%rip),%rax\nmov %rax,-0x58(%rbp)\nmov -0x58(%rbp),%rcx\nlea -0x50(%rbp),%rax\nmov $0x1,%edx\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 10d0 \nmov -0x68(%rbp),%rsi\nlea -0x50(%rbp),%rax\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rax,%rdi\ncallq 10f0 \nmov %eax,-0x5c(%rbp)\nlea -0x50(%rbp),%rax\nmov %rax,%rdi\ncallq 10a0 \ncmpl $0x0,-0x5c(%rbp)\njne 1269 \nlea 0xdb1(%rip),%rax\njmp 1270 \nlea 0xdb7(%rip),%rax\nmov -0x8(%rbp),%rdx\nxor %fs:0x28,%rdx\nje 1284 \ncallq 10b0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aAZAZ; \"^[a-z]+_[a-z]+$\"\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_5C], eax\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\ncmp [rbp+var_5C], 0\njnz short loc_1269\nlea rax, s2; \"Found a match!\"\njmp short loc_1270\nloc_1269:\nlea rax, aNotMatched; \"Not matched!\"\nloc_1270:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1284\ncall ___stack_chk_fail\nlocret_1284:\nleave\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n int v2; // [rsp+14h] [rbp-5Ch]\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n unsigned __int64 v4; // [rsp+68h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n regcomp(&preg, \"^[a-z]+_[a-z]+$\", 1);\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if ( v2 )\n return \"Not matched!\";\n else\n return \"Found a match!\";\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aAZAZ; \"^[a-z]+_[a-z]+$\"\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_5C], eax\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\ncmp [rbp+var_5C], 0\njnz short loc_1269\nlea rax, s2; \"Found a match!\"\njmp short loc_1270\nloc_1269:\nlea rax, aNotMatched; \"Not matched!\"\nloc_1270:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1284\ncall ___stack_chk_fail\nlocret_1284:\nleave\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_11E9(const char *a1)\n{\n int v2; // [rsp+14h] [rbp-5Ch]\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n unsigned __int64 v4; // [rsp+68h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n regcomp(&preg, \"^[a-z]+_[a-z]+$\", 1);\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if ( v2 )\n return \"Not matched!\";\n else\n return \"Found a match!\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_11E9(const char *a1) {\n int v2;\n regex_t preg;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n regcomp(&preg, \"^[a-z]+_[a-z]+$\", 1);\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if (v2)\n return \"Not matched!\";\n else\n return \"Found a match!\";\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n int v2;\n regex_t preg;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n regcomp(&preg, \"^[a-z]+_[a-z]+$\", 1);\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if (v2)\n return \"Not matched!\";\n else\n return \"Found a match!\";\n}" + }, + { + "index": 16, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n regex_t regex;\n char* pattern = \"^[a-z]+_[a-z]+$\";\n regcomp(®ex, pattern, REG_EXTENDED);\n int reti = regexec(®ex, text, 0, NULL, 0);\n regfree(®ex);\n if (!reti)\n return \"Found a match!\";\n else\n return \"Not matched!\";\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"aab_cbbbc\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\"aab_Abbbc\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"Aaab_abbbc\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"aab-cbbbc\"), \"Not matched!\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x58,%rsp\nmov %rdi,%rbx\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%rbp\nmov $0x1,%edx\nlea 0xe2b(%rip),%rsi\nmov %rbp,%rdi\ncallq 10c0 \nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rbx,%rsi\nmov %rbp,%rdi\ncallq 10d0 \nmov %eax,%ebx\nmov %rbp,%rdi\ncallq 1090 \ntest %ebx,%ebx\nlea 0xdd9(%rip),%rax\nlea 0xde1(%rip),%rdx\ncmovne %rdx,%rax\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 124d \nadd $0x58,%rsp\npop %rbx\npop %rbp\nretq\ncallq 10a0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov edx, 1; cflags\nlea rsi, pattern; \"^[a-z]+_[a-z]+$\"\nmov rdi, rbp; preg\ncall _regcomp\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov ebx, eax\nmov rdi, rbp; preg\ncall _regfree\ntest ebx, ebx\nlea rax, aNotMatched; \"Not matched!\"\nlea rdx, s2; \"Found a match!\"\ncmovz rax, rdx\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_126D\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_126D:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // ebx\n const char *result; // rax\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \"^[a-z]+_[a-z]+$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if ( !v1 )\n return \"Found a match!\";\n return result;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov edx, 1; cflags\nlea rsi, pattern; \"^[a-z]+_[a-z]+$\"\nmov rdi, rbp; preg\ncall _regcomp\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov ebx, eax\nmov rdi, rbp; preg\ncall _regfree\ntest ebx, ebx\nlea rax, aNotMatched; \"Not matched!\"\nlea rdx, s2; \"Found a match!\"\ncmovz rax, rdx\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_126D\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_126D:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_11E9(char *string)\n{\n int v1; // ebx\n const char *result; // rax\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \"^[a-z]+_[a-z]+$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if ( !v1 )\n return \"Found a match!\";\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_11E9(char *string) {\n int v1;\n const char *result;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \"^[a-z]+_[a-z]+$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if (!v1) return \"Found a match!\";\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n const char *result;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \"^[a-z]+_[a-z]+$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if (!v1) return \"Found a match!\";\n return result;\n}" + }, + { + "index": 16, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n regex_t regex;\n char* pattern = \"^[a-z]+_[a-z]+$\";\n regcomp(®ex, pattern, REG_EXTENDED);\n int reti = regexec(®ex, text, 0, NULL, 0);\n regfree(®ex);\n if (!reti)\n return \"Found a match!\";\n else\n return \"Not matched!\";\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"aab_cbbbc\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\"aab_Abbbc\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"Aaab_abbbc\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"aab-cbbbc\"), \"Not matched!\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov $0x1,%edx\nmov %rdi,%r12\nlea 0xd1b(%rip),%rsi\npush %rbp\npush %rbx\nsub $0x50,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%rbp\nmov %rbp,%rdi\ncallq 10c0 \nxor %ecx,%ecx\nxor %edx,%edx\nxor %r8d,%r8d\nmov %r12,%rsi\nmov %rbp,%rdi\ncallq 10d0 \nmov %rbp,%rdi\nmov %eax,%ebx\ncallq 1090 \ntest %ebx,%ebx\nlea 0xcb9(%rip),%rax\nlea 0xcc1(%rip),%rdx\ncmovne %rdx,%rax\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 136f \nadd $0x50,%rsp\npop %rbx\npop %rbp\npop %r12\nretq\ncallq 10a0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"^[a-z]+_[a-z]+$\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, aNotMatched; \"Not matched!\"\nlea rdx, s2; \"Found a match!\"\ncmovz rax, rdx\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_136B\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_136B:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // ebx\n const char *result; // rax\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \"^[a-z]+_[a-z]+$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if ( !v1 )\n return \"Found a match!\";\n return result;\n}", + "ida_strip_asm": "sub_12F0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"^[a-z]+_[a-z]+$\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, aNotMatched; \"Not matched!\"\nlea rdx, s2; \"Found a match!\"\ncmovz rax, rdx\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_136B\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_136B:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_12F0(char *string)\n{\n int v1; // ebx\n const char *result; // rax\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \"^[a-z]+_[a-z]+$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if ( !v1 )\n return \"Found a match!\";\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_12F0(char *string) {\n int v1;\n const char *result;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \"^[a-z]+_[a-z]+$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if (!v1) return \"Found a match!\";\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n const char *result;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \"^[a-z]+_[a-z]+$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if (!v1) return \"Found a match!\";\n return result;\n}" + }, + { + "index": 16, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n regex_t regex;\n char* pattern = \"^[a-z]+_[a-z]+$\";\n regcomp(®ex, pattern, REG_EXTENDED);\n int reti = regexec(®ex, text, 0, NULL, 0);\n regfree(®ex);\n if (!reti)\n return \"Found a match!\";\n else\n return \"Not matched!\";\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"aab_cbbbc\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\"aab_Abbbc\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"Aaab_abbbc\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"aab-cbbbc\"), \"Not matched!\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov $0x1,%edx\nmov %rdi,%r12\nlea 0xd1b(%rip),%rsi\npush %rbp\npush %rbx\nsub $0x50,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%rbp\nmov %rbp,%rdi\ncallq 10c0 \nxor %ecx,%ecx\nxor %edx,%edx\nxor %r8d,%r8d\nmov %r12,%rsi\nmov %rbp,%rdi\ncallq 10d0 \nmov %rbp,%rdi\nmov %eax,%ebx\ncallq 1090 \ntest %ebx,%ebx\nlea 0xcb9(%rip),%rax\nlea 0xcc1(%rip),%rdx\ncmovne %rdx,%rax\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 136f \nadd $0x50,%rsp\npop %rbx\npop %rbp\npop %r12\nretq\ncallq 10a0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"^[a-z]+_[a-z]+$\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, aNotMatched; \"Not matched!\"\nlea rdx, s2; \"Found a match!\"\ncmovz rax, rdx\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_136B\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_136B:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // ebx\n const char *result; // rax\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \"^[a-z]+_[a-z]+$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if ( !v1 )\n return \"Found a match!\";\n return result;\n}", + "ida_strip_asm": "sub_12F0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"^[a-z]+_[a-z]+$\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, aNotMatched; \"Not matched!\"\nlea rdx, s2; \"Found a match!\"\ncmovz rax, rdx\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_136B\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_136B:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_12F0(char *string)\n{\n int v1; // ebx\n const char *result; // rax\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \"^[a-z]+_[a-z]+$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if ( !v1 )\n return \"Found a match!\";\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_12F0(char *string) {\n int v1;\n const char *result;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \"^[a-z]+_[a-z]+$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if (!v1) return \"Found a match!\";\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n const char *result;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \"^[a-z]+_[a-z]+$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if (!v1) return \"Found a match!\";\n return result;\n}" + }, + { + "index": 17, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int a) {\n int perimeter = 4 * a;\n return perimeter;\n}", + "test": "int main() {\n\n assert(func0(10) == 40);\n\n assert(func0(5) == 20);\n\n assert(func0(4) == 16);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov -0x14(%rbp),%eax\nshl $0x2,%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov eax, [rbp+var_14]\nshl eax, 2\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n return (unsigned int)(4 * a1);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov eax, [rbp+var_14]\nshl eax, 2\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n return (unsigned int)(4 * a1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) { return (unsigned int)(4 * a1); }", + "ida_pseudo_norm": "long long func0(int a1) { return (unsigned int)(4 * a1); }" + }, + { + "index": 18, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n#define NO_OF_CHARS 256\n\n\n\nchar *str_to_list(char *string) {\n\n static char temp[256];\n\n int i = 0;\n\n while (*string) {\n\n temp[i++] = *string++;\n\n }\n\n temp[i] = '\\0';\n\n return temp;\n\n}\n\n\n\nchar *lst_to_string(char *list, int res_ind) {\n\n static char result[256];\n\n strncpy(result, list, res_ind);\n\n result[res_ind] = '\\0';\n\n return result;\n\n}\n\n\n\nint *get_char_count_array(char *string) {\n\n static int count[NO_OF_CHARS];\n\n memset(count, 0, sizeof(count));\n\n \n\n while (*string) {\n\n count[(int)(*string)]++;\n\n string++;\n\n }\n\n return count;\n\n}\n\n\n\n", + "func": "char *func0(char *string, char *second_string) {\n int *count = get_char_count_array(second_string);\n int ip_ind = 0, res_ind = 0;\n char *str_list = str_to_list(string);\n while (str_list[ip_ind] != '\\0') {\n char temp = str_list[ip_ind];\n if (count[(int)temp] == 0) {\n str_list[res_ind++] = temp;\n }\n ip_ind++;\n }\n return lst_to_string(str_list, res_ind);\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"probasscurve\", \"pros\"), \"bacuve\") == 0);\n\n assert(strcmp(func0(\"digitalindia\", \"talent\"), \"digiidi\") == 0);\n\n assert(strcmp(func0(\"exoticmiles\", \"toxic\"), \"emles\") == 0);\n\n\n\n printf(\"All tests passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x28(%rbp)\nmov %rsi,-0x30(%rbp)\nmov -0x30(%rbp),%rax\nmov %rax,%rdi\ncallq 126c \nmov %rax,-0x10(%rbp)\nmovl $0x0,-0x18(%rbp)\nmovl $0x0,-0x14(%rbp)\nmov -0x28(%rbp),%rax\nmov %rax,%rdi\ncallq 11c9 \nmov %rax,-0x8(%rbp)\njmp 1371 \nmov -0x18(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmov %al,-0x19(%rbp)\nmovsbq -0x19(%rbp),%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x10(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ntest %eax,%eax\njne 136d \nmov -0x14(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x14(%rbp)\nmovslq %eax,%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmovzbl -0x19(%rbp),%eax\nmov %al,(%rdx)\naddl $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 1327 \nmov -0x14(%rbp),%edx\nmov -0x8(%rbp),%rax\nmov %edx,%esi\nmov %rax,%rdi\ncallq 1227 \nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_30], rsi\nmov rax, [rbp+var_30]\nmov rdi, rax\ncall get_char_count_array\nmov [rbp+var_10], rax\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\nmov rax, [rbp+var_28]\nmov rdi, rax\ncall str_to_list\nmov [rbp+var_8], rax\njmp short loc_1377\nloc_132D:\nmov eax, [rbp+var_18]\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_19], al\nmovsx rax, [rbp+var_19]\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_10]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njnz short loc_1373\nmov eax, [rbp+var_14]\nlea edx, [rax+1]\nmov [rbp+var_14], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rdx, rax\nmovzx eax, [rbp+var_19]\nmov [rdx], al\nloc_1373:\nadd [rbp+var_18], 1\nloc_1377:\nmov eax, [rbp+var_18]\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_132D\nmov edx, [rbp+var_14]\nmov rax, [rbp+var_8]\nmov esi, edx\nmov rdi, rax\ncall lst_to_string\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2)\n{\n int v2; // eax\n char v4; // [rsp+17h] [rbp-19h]\n int v5; // [rsp+18h] [rbp-18h]\n unsigned int v6; // [rsp+1Ch] [rbp-14h]\n __int64 char_count_array; // [rsp+20h] [rbp-10h]\n __int64 v8; // [rsp+28h] [rbp-8h]\n\n char_count_array = get_char_count_array(a2);\n v5 = 0;\n v6 = 0;\n v8 = str_to_list(a1);\n while ( *(_BYTE *)(v5 + v8) )\n {\n v4 = *(_BYTE *)(v5 + v8);\n if ( !*(_DWORD *)(4LL * v4 + char_count_array) )\n {\n v2 = v6++;\n *(_BYTE *)(v8 + v2) = v4;\n }\n ++v5;\n }\n return lst_to_string(v8, v6);\n}", + "ida_strip_asm": "sub_12E9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_30], rsi\nmov rax, [rbp+var_30]\nmov rdi, rax\ncall sub_126F\nmov [rbp+var_10], rax\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\nmov rax, [rbp+var_28]\nmov rdi, rax\ncall sub_11C9\nmov [rbp+var_8], rax\njmp short loc_1377\nloc_132D:\nmov eax, [rbp+var_18]\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_19], al\nmovsx rax, [rbp+var_19]\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_10]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njnz short loc_1373\nmov eax, [rbp+var_14]\nlea edx, [rax+1]\nmov [rbp+var_14], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rdx, rax\nmovzx eax, [rbp+var_19]\nmov [rdx], al\nloc_1373:\nadd [rbp+var_18], 1\nloc_1377:\nmov eax, [rbp+var_18]\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_132D\nmov edx, [rbp+var_14]\nmov rax, [rbp+var_8]\nmov esi, edx\nmov rdi, rax\ncall sub_1227\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12E9(__int64 a1, __int64 a2)\n{\n int v2; // eax\n char v4; // [rsp+17h] [rbp-19h]\n int v5; // [rsp+18h] [rbp-18h]\n unsigned int v6; // [rsp+1Ch] [rbp-14h]\n __int64 v7; // [rsp+20h] [rbp-10h]\n __int64 v8; // [rsp+28h] [rbp-8h]\n\n v7 = sub_126F(a2);\n v5 = 0;\n v6 = 0;\n v8 = sub_11C9(a1);\n while ( *(_BYTE *)(v5 + v8) )\n {\n v4 = *(_BYTE *)(v5 + v8);\n if ( !*(_DWORD *)(4LL * v4 + v7) )\n {\n v2 = v6++;\n *(_BYTE *)(v8 + v2) = v4;\n }\n ++v5;\n }\n return sub_1227(v8, v6);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12E9(long long a1, long long a2) {\n int v2;\n char v4;\n int v5;\n unsigned int v6;\n long long v7;\n long long v8;\n v7 = sub_126F(a2);\n v5 = 0;\n v6 = 0;\n v8 = sub_11C9(a1);\n while (*(uint8_t *)(v5 + v8)) {\n v4 = *(uint8_t *)(v5 + v8);\n if (!*(uint32_t *)(4LL * v4 + v7)) {\n v2 = v6++;\n *(uint8_t *)(v8 + v2) = v4;\n }\n ++v5;\n }\n return sub_1227(v8, v6);\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2) {\n int v2;\n char v4;\n int v5;\n unsigned int v6;\n long long char_count_array;\n long long v8;\n char_count_array = get_char_count_array(a2);\n v5 = 0;\n v6 = 0;\n v8 = str_to_list(a1);\n while (*(uint8_t *)(v5 + v8)) {\n v4 = *(uint8_t *)(v5 + v8);\n if (!*(uint32_t *)(4LL * v4 + char_count_array)) {\n v2 = v6++;\n *(uint8_t *)(v8 + v2) = v4;\n }\n ++v5;\n }\n return lst_to_string(v8, v6);\n}" + }, + { + "index": 18, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n#define NO_OF_CHARS 256\n\n\n\nchar *str_to_list(char *string) {\n\n static char temp[256];\n\n int i = 0;\n\n while (*string) {\n\n temp[i++] = *string++;\n\n }\n\n temp[i] = '\\0';\n\n return temp;\n\n}\n\n\n\nchar *lst_to_string(char *list, int res_ind) {\n\n static char result[256];\n\n strncpy(result, list, res_ind);\n\n result[res_ind] = '\\0';\n\n return result;\n\n}\n\n\n\nint *get_char_count_array(char *string) {\n\n static int count[NO_OF_CHARS];\n\n memset(count, 0, sizeof(count));\n\n \n\n while (*string) {\n\n count[(int)(*string)]++;\n\n string++;\n\n }\n\n return count;\n\n}\n\n\n\n", + "func": "char *func0(char *string, char *second_string) {\n int *count = get_char_count_array(second_string);\n int ip_ind = 0, res_ind = 0;\n char *str_list = str_to_list(string);\n while (str_list[ip_ind] != '\\0') {\n char temp = str_list[ip_ind];\n if (count[(int)temp] == 0) {\n str_list[res_ind++] = temp;\n }\n ip_ind++;\n }\n return lst_to_string(str_list, res_ind);\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"probasscurve\", \"pros\"), \"bacuve\") == 0);\n\n assert(strcmp(func0(\"digitalindia\", \"talent\"), \"digiidi\") == 0);\n\n assert(strcmp(func0(\"exoticmiles\", \"toxic\"), \"emles\") == 0);\n\n\n\n printf(\"All tests passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbp\nmov %rsi,%rdi\ncallq 11f4 \nmov %rax,%rbx\nmov %rbp,%rdi\ncallq 1189 \nmov %rax,%rdi\nmovzbl (%rax),%edx\ntest %dl,%dl\nje 128f \nlea 0x1(%rax),%rcx\nmov $0x0,%r8d\njmp 1279 \nadd $0x1,%rcx\nmovzbl -0x1(%rcx),%edx\ntest %dl,%dl\nje 1295 \nmovsbq %dl,%rsi\ncmpl $0x0,(%rbx,%rsi,4)\njne 126d \nmovslq %r8d,%rax\nmov %dl,(%rdi,%rax,1)\nlea 0x1(%r8),%r8d\njmp 126d \nmov $0x0,%r8d\nmov %r8d,%esi\ncallq 11c8 \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov rdi, rsi\ncall get_char_count_array\nmov rbx, rax\nmov rdi, rbp\ncall str_to_list\nmov rdi, rax\nmovzx edx, byte ptr [rax]\ntest dl, dl\njz short loc_12B7\nlea rcx, [rax+1]\nmov r8d, 0\njmp short loc_12A1\nloc_1295:\nadd rcx, 1\nmovzx edx, byte ptr [rcx-1]\ntest dl, dl\njz short loc_12BD\nloc_12A1:\nmovsx rsi, dl\ncmp dword ptr [rbx+rsi*4], 0\njnz short loc_1295\nmovsxd rax, r8d\nmov [rdi+rax], dl\nlea r8d, [r8+1]\njmp short loc_1295\nloc_12B7:\nmov r8d, 0\nloc_12BD:\nmov esi, r8d\ncall lst_to_string\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2)\n{\n __int64 char_count_array; // rbx\n char *v3; // rax\n char v4; // dl\n char *v5; // rcx\n unsigned int v6; // r8d\n\n char_count_array = get_char_count_array(a2);\n v3 = (char *)str_to_list(a1);\n v4 = *v3;\n if ( *v3 )\n {\n v5 = v3 + 1;\n v6 = 0;\n do\n {\n if ( !*(_DWORD *)(char_count_array + 4LL * v4) )\n v3[v6++] = v4;\n v4 = *v5++;\n }\n while ( v4 );\n }\n else\n {\n v6 = 0;\n }\n return lst_to_string(v3, v6);\n}", + "ida_strip_asm": "sub_125F:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov rdi, rsi\ncall sub_121C\nmov rbx, rax\nmov rdi, rbp\ncall sub_11A9\nmov rdi, rax\nmovzx edx, byte ptr [rax]\ntest dl, dl\njz short loc_12B7\nlea rcx, [rax+1]\nmov r8d, 0\njmp short loc_12A1\nloc_1295:\nadd rcx, 1\nmovzx edx, byte ptr [rcx-1]\ntest dl, dl\njz short loc_12BD\nloc_12A1:\nmovsx rsi, dl\ncmp dword ptr [rbx+rsi*4], 0\njnz short loc_1295\nmovsxd rax, r8d\nmov [rdi+rax], dl\nlea r8d, [r8+1]\njmp short loc_1295\nloc_12B7:\nmov r8d, 0\nloc_12BD:\nmov esi, r8d\ncall sub_11E9\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_125F(__int64 a1, __int64 a2)\n{\n __int64 v2; // rbx\n char *v3; // rax\n char v4; // dl\n char *v5; // rcx\n unsigned int v6; // r8d\n\n v2 = sub_121C(a2);\n v3 = (char *)sub_11A9(a1);\n v4 = *v3;\n if ( *v3 )\n {\n v5 = v3 + 1;\n v6 = 0;\n do\n {\n if ( !*(_DWORD *)(v2 + 4LL * v4) )\n v3[v6++] = v4;\n v4 = *v5++;\n }\n while ( v4 );\n }\n else\n {\n v6 = 0;\n }\n return sub_11E9(v3, v6);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_125F(long long a1, long long a2) {\n long long v2;\n char *v3;\n char v4;\n char *v5;\n unsigned int v6;\n v2 = sub_121C(a2);\n v3 = (char *)sub_11A9(a1);\n v4 = *v3;\n if (*v3) {\n v5 = v3 + 1;\n v6 = 0;\n do {\n if (!*(uint32_t *)(v2 + 4LL * v4)) v3[v6++] = v4;\n v4 = *v5++;\n } while (v4);\n } else {\n v6 = 0;\n }\n return sub_11E9(v3, v6);\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2) {\n long long char_count_array;\n char *v3;\n char v4;\n char *v5;\n unsigned int v6;\n char_count_array = get_char_count_array(a2);\n v3 = (char *)str_to_list(a1);\n v4 = *v3;\n if (*v3) {\n v5 = v3 + 1;\n v6 = 0;\n do {\n if (!*(uint32_t *)(char_count_array + 4LL * v4)) v3[v6++] = v4;\n v4 = *v5++;\n } while (v4);\n } else {\n v6 = 0;\n }\n return lst_to_string(v3, v6);\n}" + }, + { + "index": 18, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n#define NO_OF_CHARS 256\n\n\n\nchar *str_to_list(char *string) {\n\n static char temp[256];\n\n int i = 0;\n\n while (*string) {\n\n temp[i++] = *string++;\n\n }\n\n temp[i] = '\\0';\n\n return temp;\n\n}\n\n\n\nchar *lst_to_string(char *list, int res_ind) {\n\n static char result[256];\n\n strncpy(result, list, res_ind);\n\n result[res_ind] = '\\0';\n\n return result;\n\n}\n\n\n\nint *get_char_count_array(char *string) {\n\n static int count[NO_OF_CHARS];\n\n memset(count, 0, sizeof(count));\n\n \n\n while (*string) {\n\n count[(int)(*string)]++;\n\n string++;\n\n }\n\n return count;\n\n}\n\n\n\n", + "func": "char *func0(char *string, char *second_string) {\n int *count = get_char_count_array(second_string);\n int ip_ind = 0, res_ind = 0;\n char *str_list = str_to_list(string);\n while (str_list[ip_ind] != '\\0') {\n char temp = str_list[ip_ind];\n if (count[(int)temp] == 0) {\n str_list[res_ind++] = temp;\n }\n ip_ind++;\n }\n return lst_to_string(str_list, res_ind);\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"probasscurve\", \"pros\"), \"bacuve\") == 0);\n\n assert(strcmp(func0(\"digitalindia\", \"talent\"), \"digiidi\") == 0);\n\n assert(strcmp(func0(\"exoticmiles\", \"toxic\"), \"emles\") == 0);\n\n\n\n printf(\"All tests passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%r8\nmov %rsi,%rdi\ncallq 1310 \nmovzbl (%r8),%ecx\ntest %cl,%cl\nje 1410 \nmov $0x1,%edx\nlea 0x31c7(%rip),%rdi\nnopl 0x0(%rax,%rax,1)\nmov %cl,(%rdi,%rdx,1)\nmovslq %edx,%rsi\nadd $0x1,%rdx\nmovzbl -0x1(%r8,%rdx,1),%ecx\ntest %cl,%cl\njne 1380 \nlea 0x31a5(%rip),%r9\nmovb $0x0,(%r9,%rsi,1)\nmovzbl 0x3199(%rip),%edx\ntest %dl,%dl\nje 1418 \nlea 0x1(%r9),%rcx\nxor %edi,%edi\nxor %ebx,%ebx\nnopl 0x0(%rax,%rax,1)\nmovsbq %dl,%rsi\nmov %rbx,%r8\nmov (%rax,%rsi,4),%esi\ntest %esi,%esi\njne 13d3 \nadd $0x1,%edi\nmov %dl,(%r9,%rbx,1)\nmovslq %edi,%rbx\nmov %rbx,%r8\nmovzbl (%rcx),%edx\nadd $0x1,%rcx\ntest %dl,%dl\njne 13b8 \nmov $0x100,%ecx\nmov %r8,%rdx\nlea 0x3153(%rip),%rsi\nlea 0x304c(%rip),%rdi\ncallq 1090 <__strncpy_chk@plt>\nlea 0x3040(%rip),%rax\nmovb $0x0,(%rax,%rbx,1)\npop %rbx\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxor %esi,%esi\njmp 1394 \nnopl 0x0(%rax)\nxor %r8d,%r8d\nxor %ebx,%ebx\njmp 13de \n", + "ida_asm": "func0:\nendbr64\nlea rdx, count_1\nxor eax, eax\nmov r8, rdi\npush rbx\nmov ecx, 80h\nmov rdi, rdx\nrep stosq\nmovsx rax, byte ptr [rsi]\ntest al, al\njz short loc_13A8\nnop dword ptr [rax+00h]\nloc_1398:\nadd rsi, 1\nadd dword ptr [rdx+rax*4], 1\nmovsx rax, byte ptr [rsi]\ntest al, al\njnz short loc_1398\nloc_13A8:\nmovzx ecx, byte ptr [r8]\nmov eax, 1\nlea rdi, unk_453F\nxor esi, esi\ntest cl, cl\njz short loc_13D4\nxchg ax, ax\nloc_13C0:\nmov [rdi+rax], cl\nmov rsi, rax\nadd rax, 1\nmovzx ecx, byte ptr [r8+rax-1]\ntest cl, cl\njnz short loc_13C0\nloc_13D4:\nlea r8, temp_3\nmovsxd rsi, esi\nmov byte ptr [r8+rsi], 0\nmovzx eax, cs:temp_3\ntest al, al\njz short loc_1440\nlea rcx, [r8+1]\nxor esi, esi\nnop dword ptr [rax+00h]\nloc_13F8:\nmovsx rdi, al\nmov edi, [rdx+rdi*4]\ntest edi, edi\njnz short loc_140D\nmovsxd rdi, esi\nadd esi, 1\nmov [r8+rdi], al\nloc_140D:\nmovzx eax, byte ptr [rcx]\nadd rcx, 1\ntest al, al\njnz short loc_13F8\nmovsxd rbx, esi\nmov rdx, rbx\nloc_141E:\nmov ecx, 100h\nmov rsi, r8\nlea rdi, result_2\ncall ___strncpy_chk\nmov byte ptr [rax+rbx], 0\npop rbx\nretn\nloc_1440:\nxor edx, edx\nxor ebx, ebx\njmp short loc_141E", + "ida_pseudo": "__int64 __fastcall func0(char *a1, char *a2)\n{\n __int64 i; // rax\n char v3; // cl\n __int64 v4; // rax\n int j; // esi\n char v6; // al\n char *v7; // rcx\n int v8; // esi\n __int64 v9; // rdi\n __int64 v10; // rbx\n __int64 v11; // rdx\n __int64 result; // rax\n\n memset(count_1, 0, sizeof(count_1));\n for ( i = *a2; (_BYTE)i; i = *a2 )\n {\n ++a2;\n ++count_1[i];\n }\n v3 = *a1;\n v4 = 1LL;\n for ( j = 0; v3; v3 = a1[v4 - 1] )\n {\n *((_BYTE *)&unk_453F + v4) = v3;\n j = v4++;\n }\n temp_3[j] = 0;\n v6 = temp_3[0];\n if ( temp_3[0] )\n {\n v7 = &temp_3[1];\n v8 = 0;\n do\n {\n if ( !count_1[v6] )\n {\n v9 = v8++;\n temp_3[v9] = v6;\n }\n v6 = *v7++;\n }\n while ( v6 );\n v10 = v8;\n v11 = v8;\n }\n else\n {\n v11 = 0LL;\n v10 = 0LL;\n }\n result = __strncpy_chk(&result_2, temp_3, v11, 256LL);\n *(_BYTE *)(result + v10) = 0;\n return result;\n}", + "ida_strip_asm": "sub_1370:\nendbr64\nlea rdx, unk_4040\nxor eax, eax\nmov r8, rdi\npush rbx\nmov ecx, 80h\nmov rdi, rdx\nrep stosq\nmovsx rax, byte ptr [rsi]\ntest al, al\njz short loc_13A8\nnop dword ptr [rax+00h]\nloc_1398:\nadd rsi, 1\nadd dword ptr [rdx+rax*4], 1\nmovsx rax, byte ptr [rsi]\ntest al, al\njnz short loc_1398\nloc_13A8:\nmovzx ecx, byte ptr [r8]\nmov eax, 1\nlea rdi, unk_453F\nxor esi, esi\ntest cl, cl\njz short loc_13D4\nxchg ax, ax\nloc_13C0:\nmov [rdi+rax], cl\nmov rsi, rax\nadd rax, 1\nmovzx ecx, byte ptr [r8+rax-1]\ntest cl, cl\njnz short loc_13C0\nloc_13D4:\nlea r8, byte_4540\nmovsxd rsi, esi\nmov byte ptr [r8+rsi], 0\nmovzx eax, cs:byte_4540\ntest al, al\njz short loc_1440\nlea rcx, [r8+1]\nxor esi, esi\nnop dword ptr [rax+00h]\nloc_13F8:\nmovsx rdi, al\nmov edi, [rdx+rdi*4]\ntest edi, edi\njnz short loc_140D\nmovsxd rdi, esi\nadd esi, 1\nmov [r8+rdi], al\nloc_140D:\nmovzx eax, byte ptr [rcx]\nadd rcx, 1\ntest al, al\njnz short loc_13F8\nmovsxd rbx, esi\nmov rdx, rbx\nloc_141E:\nmov ecx, 100h\nmov rsi, r8\nlea rdi, unk_4440\ncall ___strncpy_chk\nmov byte ptr [rax+rbx], 0\npop rbx\nretn\nloc_1440:\nxor edx, edx\nxor ebx, ebx\njmp short loc_141E", + "ida_strip_pseudo": "__int64 __fastcall sub_1370(char *a1, char *a2)\n{\n __int64 i; // rax\n char v3; // cl\n __int64 v4; // rax\n int j; // esi\n char v6; // al\n char *v7; // rcx\n int v8; // esi\n __int64 v9; // rdi\n __int64 v10; // rbx\n __int64 v11; // rdx\n __int64 result; // rax\n\n memset(dword_4040, 0, sizeof(dword_4040));\n for ( i = *a2; (_BYTE)i; i = *a2 )\n {\n ++a2;\n ++dword_4040[i];\n }\n v3 = *a1;\n v4 = 1LL;\n for ( j = 0; v3; v3 = a1[v4 - 1] )\n {\n *((_BYTE *)&unk_453F + v4) = v3;\n j = v4++;\n }\n byte_4540[j] = 0;\n v6 = byte_4540[0];\n if ( byte_4540[0] )\n {\n v7 = &byte_4540[1];\n v8 = 0;\n do\n {\n if ( !dword_4040[v6] )\n {\n v9 = v8++;\n byte_4540[v9] = v6;\n }\n v6 = *v7++;\n }\n while ( v6 );\n v10 = v8;\n v11 = v8;\n }\n else\n {\n v11 = 0LL;\n v10 = 0LL;\n }\n result = __strncpy_chk(&unk_4440, byte_4540, v11, 256LL);\n *(_BYTE *)(result + v10) = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1370(char *a1, char *a2) {\n long long i;\n char v3;\n long long v4;\n int j;\n char v6;\n char *v7;\n int v8;\n long long v9;\n long long v10;\n long long v11;\n long long result;\n memset(dword_4040, 0, sizeof(dword_4040));\n for (i = *a2; (uint8_t)i; i = *a2) {\n ++a2;\n ++dword_4040[i];\n }\n v3 = *a1;\n v4 = 1LL;\n for (j = 0; v3; v3 = a1[v4 - 1]) {\n *((uint8_t *)&unk_453F + v4) = v3;\n j = v4++;\n }\n byte_4540[j] = 0;\n v6 = byte_4540[0];\n if (byte_4540[0]) {\n v7 = &byte_4540[1];\n v8 = 0;\n do {\n if (!dword_4040[v6]) {\n v9 = v8++;\n byte_4540[v9] = v6;\n }\n v6 = *v7++;\n } while (v6);\n v10 = v8;\n v11 = v8;\n } else {\n v11 = 0LL;\n v10 = 0LL;\n }\n result = __strncpy_chk(&unk_4440, byte_4540, v11, 256LL);\n *(uint8_t *)(result + v10) = 0;\n return result;\n}", + "ida_pseudo_norm": "long long func0(char *a1, char *a2) {\n long long i;\n char v3;\n long long v4;\n int j;\n char v6;\n char *v7;\n int v8;\n long long v9;\n long long v10;\n long long v11;\n long long result;\n memset(count_1, 0, sizeof(count_1));\n for (i = *a2; (uint8_t)i; i = *a2) {\n ++a2;\n ++count_1[i];\n }\n v3 = *a1;\n v4 = 1LL;\n for (j = 0; v3; v3 = a1[v4 - 1]) {\n *((uint8_t *)&unk_453F + v4) = v3;\n j = v4++;\n }\n temp_3[j] = 0;\n v6 = temp_3[0];\n if (temp_3[0]) {\n v7 = &temp_3[1];\n v8 = 0;\n do {\n if (!count_1[v6]) {\n v9 = v8++;\n temp_3[v9] = v6;\n }\n v6 = *v7++;\n } while (v6);\n v10 = v8;\n v11 = v8;\n } else {\n v11 = 0LL;\n v10 = 0LL;\n }\n result = __strncpy_chk(&result_2, temp_3, v11, 256LL);\n *(uint8_t *)(result + v10) = 0;\n return result;\n}" + }, + { + "index": 18, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n#define NO_OF_CHARS 256\n\n\n\nchar *str_to_list(char *string) {\n\n static char temp[256];\n\n int i = 0;\n\n while (*string) {\n\n temp[i++] = *string++;\n\n }\n\n temp[i] = '\\0';\n\n return temp;\n\n}\n\n\n\nchar *lst_to_string(char *list, int res_ind) {\n\n static char result[256];\n\n strncpy(result, list, res_ind);\n\n result[res_ind] = '\\0';\n\n return result;\n\n}\n\n\n\nint *get_char_count_array(char *string) {\n\n static int count[NO_OF_CHARS];\n\n memset(count, 0, sizeof(count));\n\n \n\n while (*string) {\n\n count[(int)(*string)]++;\n\n string++;\n\n }\n\n return count;\n\n}\n\n\n\n", + "func": "char *func0(char *string, char *second_string) {\n int *count = get_char_count_array(second_string);\n int ip_ind = 0, res_ind = 0;\n char *str_list = str_to_list(string);\n while (str_list[ip_ind] != '\\0') {\n char temp = str_list[ip_ind];\n if (count[(int)temp] == 0) {\n str_list[res_ind++] = temp;\n }\n ip_ind++;\n }\n return lst_to_string(str_list, res_ind);\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"probasscurve\", \"pros\"), \"bacuve\") == 0);\n\n assert(strcmp(func0(\"digitalindia\", \"talent\"), \"digiidi\") == 0);\n\n assert(strcmp(func0(\"exoticmiles\", \"toxic\"), \"emles\") == 0);\n\n\n\n printf(\"All tests passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nlea 0x2ce5(%rip),%rdx\nxor %eax,%eax\nmov %rdi,%r8\npush %rbx\nmov $0x80,%ecx\nmov %rdx,%rdi\nrep stos %rax,%es:(%rdi)\nmovsbq (%rsi),%rax\ntest %al,%al\nje 1388 \nnopl 0x0(%rax)\nadd $0x1,%rsi\naddl $0x1,(%rdx,%rax,4)\nmovsbq (%rsi),%rax\ntest %al,%al\njne 1378 \nmovzbl (%r8),%ecx\nmov $0x1,%eax\nlea 0x31a7(%rip),%rdi\nxor %esi,%esi\ntest %cl,%cl\nje 13b4 \nxchg %ax,%ax\nmov %cl,(%rdi,%rax,1)\nmovslq %eax,%rsi\nadd $0x1,%rax\nmovzbl -0x1(%r8,%rax,1),%ecx\ntest %cl,%cl\njne 13a0 \nlea 0x3185(%rip),%r9\nmovb $0x0,(%r9,%rsi,1)\nmovzbl 0x3179(%rip),%eax\ntest %al,%al\nje 1440 \nlea 0x1(%r9),%rcx\nxor %edi,%edi\nxor %ebx,%ebx\nnopl 0x0(%rax,%rax,1)\nmovsbq %al,%rsi\nmov %rbx,%r8\nmov (%rdx,%rsi,4),%esi\ntest %esi,%esi\njne 1430 \nadd $0x1,%rcx\nmov %al,(%r9,%rbx,1)\nadd $0x1,%edi\nmovzbl -0x1(%rcx),%eax\nmovslq %edi,%rbx\nmov %rbx,%r8\ntest %al,%al\njne 13d8 \nmov $0x100,%ecx\nmov %r8,%rdx\nlea 0x3132(%rip),%rsi\nlea 0x302b(%rip),%rdi\ncallq 1090 <__strncpy_chk@plt>\nlea 0x301f(%rip),%rax\nmovb $0x0,(%rax,%rbx,1)\npop %rbx\nretq\nnopw 0x0(%rax,%rax,1)\nmovzbl (%rcx),%eax\nadd $0x1,%rcx\ntest %al,%al\njne 13d8 \njmp 13ff \nnopl (%rax)\nxor %r8d,%r8d\nxor %ebx,%ebx\njmp 13ff \nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nlea rdx, count_1\nxor eax, eax\nmov r8, rdi\npush rbx\nmov ecx, 80h\nmov rdi, rdx\nrep stosq\nmovsx rax, byte ptr [rsi]\ntest al, al\njz short loc_13A8\nnop dword ptr [rax+00h]\nloc_1398:\nadd rsi, 1\nadd dword ptr [rdx+rax*4], 1\nmovsx rax, byte ptr [rsi]\ntest al, al\njnz short loc_1398\nloc_13A8:\nmovzx ecx, byte ptr [r8]\nmov eax, 1\nlea rdi, unk_453F\nxor esi, esi\ntest cl, cl\njz short loc_13D4\nxchg ax, ax\nloc_13C0:\nmov [rdi+rax], cl\nmov rsi, rax\nadd rax, 1\nmovzx ecx, byte ptr [r8+rax-1]\ntest cl, cl\njnz short loc_13C0\nloc_13D4:\nlea r8, temp_3\nmovsxd rsi, esi\nmov byte ptr [r8+rsi], 0\nmovzx eax, cs:temp_3\ntest al, al\njz short loc_1458\nlea rcx, [r8+1]\nxor esi, esi\nnop dword ptr [rax+00h]\nloc_13F8:\nmovsx rdi, al\nmov edi, [rdx+rdi*4]\ntest edi, edi\njnz short loc_1424\nloc_1403:\nadd rcx, 1\nmov [r8+rsi], al\nlea edi, [rsi+1]\nmovzx eax, byte ptr [rcx-1]\ntest al, al\njz short loc_1450\nmovsxd rsi, edi\nmovsx rdi, al\nmov edi, [rdx+rdi*4]\ntest edi, edi\njz short loc_1403\nloc_1424:\nmovzx eax, byte ptr [rcx]\nadd rcx, 1\ntest al, al\njnz short loc_13F8\nloc_142F:\nmovsxd rbx, esi\nmov rdx, rbx\nloc_1435:\nmov ecx, 100h\nmov rsi, r8\nlea rdi, result_2\ncall ___strncpy_chk\nmov byte ptr [rax+rbx], 0\npop rbx\nretn\nloc_1450:\nmov esi, edi\njmp short loc_142F\nloc_1458:\nxor edx, edx\nxor ebx, ebx\njmp short loc_1435", + "ida_pseudo": "__int64 __fastcall func0(char *a1, char *a2)\n{\n __int64 i; // rax\n char v3; // cl\n __int64 v4; // rax\n int j; // esi\n char v6; // al\n char *v7; // rcx\n __int64 v8; // rsi\n __int64 v9; // rbx\n __int64 v10; // rdx\n __int64 result; // rax\n\n memset(count_1, 0, sizeof(count_1));\n for ( i = *a2; (_BYTE)i; i = *a2 )\n {\n ++a2;\n ++count_1[i];\n }\n v3 = *a1;\n v4 = 1LL;\n for ( j = 0; v3; v3 = a1[v4 - 1] )\n {\n *((_BYTE *)&unk_453F + v4) = v3;\n j = v4++;\n }\n temp_3[j] = 0;\n v6 = temp_3[0];\n if ( temp_3[0] )\n {\n v7 = &temp_3[1];\n v8 = 0LL;\n while ( count_1[v6] )\n {\nLABEL_10:\n v6 = *v7++;\n if ( !v6 )\n goto LABEL_11;\n }\n while ( 1 )\n {\n ++v7;\n temp_3[v8] = v6;\n v6 = *(v7 - 1);\n if ( !v6 )\n break;\n v8 = (int)v8 + 1;\n if ( count_1[v6] )\n goto LABEL_10;\n }\n LODWORD(v8) = v8 + 1;\nLABEL_11:\n v9 = (int)v8;\n v10 = (int)v8;\n }\n else\n {\n v10 = 0LL;\n v9 = 0LL;\n }\n result = __strncpy_chk(&result_2, temp_3, v10, 256LL);\n *(_BYTE *)(result + v9) = 0;\n return result;\n}", + "ida_strip_asm": "sub_1370:\nendbr64\nlea rdx, unk_4040\nxor eax, eax\nmov r8, rdi\npush rbx\nmov ecx, 80h\nmov rdi, rdx\nrep stosq\nmovsx rax, byte ptr [rsi]\ntest al, al\njz short loc_13A8\nnop dword ptr [rax+00h]\nloc_1398:\nadd rsi, 1\nadd dword ptr [rdx+rax*4], 1\nmovsx rax, byte ptr [rsi]\ntest al, al\njnz short loc_1398\nloc_13A8:\nmovzx ecx, byte ptr [r8]\nmov eax, 1\nlea rdi, unk_453F\nxor esi, esi\ntest cl, cl\njz short loc_13D4\nxchg ax, ax\nloc_13C0:\nmov [rdi+rax], cl\nmov rsi, rax\nadd rax, 1\nmovzx ecx, byte ptr [r8+rax-1]\ntest cl, cl\njnz short loc_13C0\nloc_13D4:\nlea r8, byte_4540\nmovsxd rsi, esi\nmov byte ptr [r8+rsi], 0\nmovzx eax, cs:byte_4540\ntest al, al\njz short loc_1458\nlea rcx, [r8+1]\nxor esi, esi\nnop dword ptr [rax+00h]\nloc_13F8:\nmovsx rdi, al\nmov edi, [rdx+rdi*4]\ntest edi, edi\njnz short loc_1424\nloc_1403:\nadd rcx, 1\nmov [r8+rsi], al\nlea edi, [rsi+1]\nmovzx eax, byte ptr [rcx-1]\ntest al, al\njz short loc_1450\nmovsxd rsi, edi\nmovsx rdi, al\nmov edi, [rdx+rdi*4]\ntest edi, edi\njz short loc_1403\nloc_1424:\nmovzx eax, byte ptr [rcx]\nadd rcx, 1\ntest al, al\njnz short loc_13F8\nloc_142F:\nmovsxd rbx, esi\nmov rdx, rbx\nloc_1435:\nmov ecx, 100h\nmov rsi, r8\nlea rdi, unk_4440\ncall ___strncpy_chk\nmov byte ptr [rax+rbx], 0\npop rbx\nretn\nloc_1450:\nmov esi, edi\njmp short loc_142F\nloc_1458:\nxor edx, edx\nxor ebx, ebx\njmp short loc_1435", + "ida_strip_pseudo": "__int64 __fastcall sub_1370(char *a1, char *a2)\n{\n __int64 i; // rax\n char v3; // cl\n __int64 v4; // rax\n int j; // esi\n char v6; // al\n char *v7; // rcx\n __int64 v8; // rsi\n __int64 v9; // rbx\n __int64 v10; // rdx\n __int64 result; // rax\n\n memset(dword_4040, 0, sizeof(dword_4040));\n for ( i = *a2; (_BYTE)i; i = *a2 )\n {\n ++a2;\n ++dword_4040[i];\n }\n v3 = *a1;\n v4 = 1LL;\n for ( j = 0; v3; v3 = a1[v4 - 1] )\n {\n *((_BYTE *)&unk_453F + v4) = v3;\n j = v4++;\n }\n byte_4540[j] = 0;\n v6 = byte_4540[0];\n if ( byte_4540[0] )\n {\n v7 = &byte_4540[1];\n v8 = 0LL;\n while ( dword_4040[v6] )\n {\nLABEL_10:\n v6 = *v7++;\n if ( !v6 )\n goto LABEL_11;\n }\n while ( 1 )\n {\n ++v7;\n byte_4540[v8] = v6;\n v6 = *(v7 - 1);\n if ( !v6 )\n break;\n v8 = (int)v8 + 1;\n if ( dword_4040[v6] )\n goto LABEL_10;\n }\n LODWORD(v8) = v8 + 1;\nLABEL_11:\n v9 = (int)v8;\n v10 = (int)v8;\n }\n else\n {\n v10 = 0LL;\n v9 = 0LL;\n }\n result = __strncpy_chk(&unk_4440, byte_4540, v10, 256LL);\n *(_BYTE *)(result + v9) = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1370(char *a1, char *a2) {\n long long i;\n char v3;\n long long v4;\n int j;\n char v6;\n char *v7;\n long long v8;\n long long v9;\n long long v10;\n long long result;\n memset(dword_4040, 0, sizeof(dword_4040));\n for (i = *a2; (uint8_t)i; i = *a2) {\n ++a2;\n ++dword_4040[i];\n }\n v3 = *a1;\n v4 = 1LL;\n for (j = 0; v3; v3 = a1[v4 - 1]) {\n *((uint8_t *)&unk_453F + v4) = v3;\n j = v4++;\n }\n byte_4540[j] = 0;\n v6 = byte_4540[0];\n if (byte_4540[0]) {\n v7 = &byte_4540[1];\n v8 = 0LL;\n while (dword_4040[v6]) {\n LABEL_10:\n v6 = *v7++;\n if (!v6) goto LABEL_11;\n }\n while (1) {\n ++v7;\n byte_4540[v8] = v6;\n v6 = *(v7 - 1);\n if (!v6) break;\n v8 = (int)v8 + 1;\n if (dword_4040[v6]) goto LABEL_10;\n }\n LODWORD(v8) = v8 + 1;\n LABEL_11:\n v9 = (int)v8;\n v10 = (int)v8;\n } else {\n v10 = 0LL;\n v9 = 0LL;\n }\n result = __strncpy_chk(&unk_4440, byte_4540, v10, 256LL);\n *(uint8_t *)(result + v9) = 0;\n return result;\n}", + "ida_pseudo_norm": "long long func0(char *a1, char *a2) {\n long long i;\n char v3;\n long long v4;\n int j;\n char v6;\n char *v7;\n long long v8;\n long long v9;\n long long v10;\n long long result;\n memset(count_1, 0, sizeof(count_1));\n for (i = *a2; (uint8_t)i; i = *a2) {\n ++a2;\n ++count_1[i];\n }\n v3 = *a1;\n v4 = 1LL;\n for (j = 0; v3; v3 = a1[v4 - 1]) {\n *((uint8_t *)&unk_453F + v4) = v3;\n j = v4++;\n }\n temp_3[j] = 0;\n v6 = temp_3[0];\n if (temp_3[0]) {\n v7 = &temp_3[1];\n v8 = 0LL;\n while (count_1[v6]) {\n LABEL_10:\n v6 = *v7++;\n if (!v6) goto LABEL_11;\n }\n while (1) {\n ++v7;\n temp_3[v8] = v6;\n v6 = *(v7 - 1);\n if (!v6) break;\n v8 = (int)v8 + 1;\n if (count_1[v6]) goto LABEL_10;\n }\n LODWORD(v8) = v8 + 1;\n LABEL_11:\n v9 = (int)v8;\n v10 = (int)v8;\n } else {\n v10 = 0LL;\n v9 = 0LL;\n }\n result = __strncpy_chk(&result_2, temp_3, v10, 256LL);\n *(uint8_t *)(result + v9) = 0;\n return result;\n}" + }, + { + "index": 19, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "bool func0(int arraynums[], int length) {\n bool found_duplicate = false;\n for (int i = 0; i < length; i++) {\n for (int j = i + 1; j < length; j++) {\n if (arraynums[i] == arraynums[j]) {\n found_duplicate = true;\n break;\n }\n }\n if (found_duplicate) {\n break;\n }\n }\n return found_duplicate;\n}", + "test": "int main() {\n\n int array1[] = {1, 2, 3, 4, 5};\n\n int array2[] = {1, 2, 3, 4, 4};\n\n int array3[] = {1, 1, 2, 2, 3, 3, 4, 4, 5};\n\n\n\n assert(func0(array1, sizeof(array1)/sizeof(array1[0])) == false);\n\n assert(func0(array2, sizeof(array2)/sizeof(array2[0])) == true);\n\n assert(func0(array3, sizeof(array3)/sizeof(array3[0])) == true);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovb $0x0,-0x9(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11dc \nmov -0x8(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x4(%rbp)\njmp 11ca \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 11c6 \nmovb $0x1,-0x9(%rbp)\njmp 11d2 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1190 \ncmpb $0x0,-0x9(%rbp)\njne 11e6 \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1185 \njmp 11e7 \nmovzbl -0x9(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_9], 0\nmov [rbp+var_8], 0\njmp short loc_11DC\nloc_1185:\nmov eax, [rbp+var_8]\nadd eax, 1\nmov [rbp+var_4], eax\njmp short loc_11CA\nloc_1190:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11C6\nmov [rbp+var_9], 1\njmp short loc_11D2\nloc_11C6:\nadd [rbp+var_4], 1\nloc_11CA:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1190\nloc_11D2:\ncmp [rbp+var_9], 0\njnz short loc_11E6\nadd [rbp+var_8], 1\nloc_11DC:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_1185\njmp short loc_11E7\nloc_11E6:\nnop\nloc_11E7:\nmovzx eax, [rbp+var_9]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned __int8 v3; // [rsp+13h] [rbp-9h]\n int i; // [rsp+14h] [rbp-8h]\n int j; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4LL * j + a1) )\n {\n v3 = 1;\n break;\n }\n }\n if ( v3 )\n break;\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_9], 0\nmov [rbp+var_8], 0\njmp short loc_11DC\nloc_1185:\nmov eax, [rbp+var_8]\nadd eax, 1\nmov [rbp+var_4], eax\njmp short loc_11CA\nloc_1190:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11C6\nmov [rbp+var_9], 1\njmp short loc_11D2\nloc_11C6:\nadd [rbp+var_4], 1\nloc_11CA:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1190\nloc_11D2:\ncmp [rbp+var_9], 0\njnz short loc_11E6\nadd [rbp+var_8], 1\nloc_11DC:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_1185\njmp short loc_11E7\nloc_11E6:\nnop\nloc_11E7:\nmovzx eax, [rbp+var_9]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned __int8 v3; // [rsp+13h] [rbp-9h]\n int i; // [rsp+14h] [rbp-8h]\n int j; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4LL * j + a1) )\n {\n v3 = 1;\n break;\n }\n }\n if ( v3 )\n break;\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n unsigned char v3;\n int i;\n int j;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if (*(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4LL * j + a1)) {\n v3 = 1;\n break;\n }\n }\n if (v3) break;\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned char v3;\n int i;\n int j;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if (*(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4LL * j + a1)) {\n v3 = 1;\n break;\n }\n }\n if (v3) break;\n }\n return v3;\n}" + }, + { + "index": 19, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "bool func0(int arraynums[], int length) {\n bool found_duplicate = false;\n for (int i = 0; i < length; i++) {\n for (int j = i + 1; j < length; j++) {\n if (arraynums[i] == arraynums[j]) {\n found_duplicate = true;\n break;\n }\n }\n if (found_duplicate) {\n break;\n }\n }\n return found_duplicate;\n}", + "test": "int main() {\n\n int array1[] = {1, 2, 3, 4, 5};\n\n int array2[] = {1, 2, 3, 4, 4};\n\n int array3[] = {1, 1, 2, 2, 3, 3, 4, 4, 5};\n\n\n\n assert(func0(array1, sizeof(array1)/sizeof(array1[0])) == false);\n\n assert(func0(array2, sizeof(array2)/sizeof(array2[0])) == true);\n\n assert(func0(array3, sizeof(array3)/sizeof(array3[0])) == true);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x1,%ecx\njmp 1178 \nadd $0x1,%rcx\nlea -0x1(%rcx),%eax\ncmp %eax,%esi\njle 1199 \ncmp %ecx,%esi\njle 1174 \nmov -0x4(%rdi,%rcx,4),%edx\nmovslq %ecx,%rax\ncmp (%rdi,%rax,4),%edx\nje 119f \nadd $0x1,%rax\ncmp %eax,%esi\njg 118a \njmp 1174 \nmov $0x0,%eax\nretq\nmov $0x1,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov ecx, 1\njmp short loc_1178\nloc_1174:\nadd rcx, 1\nloc_1178:\nlea eax, [rcx-1]\ncmp esi, eax\njle short loc_1199\ncmp esi, ecx\njle short loc_1174\nmov edx, [rdi+rcx*4-4]\nmovsxd rax, ecx\nloc_118A:\ncmp edx, [rdi+rax*4]\njz short loc_119F\nadd rax, 1\ncmp esi, eax\njg short loc_118A\njmp short loc_1174\nloc_1199:\nmov eax, 0\nretn\nloc_119F:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 i; // rcx\n __int64 v3; // rax\n\n for ( i = 1LL; ; ++i )\n {\n if ( a2 <= (int)i - 1 )\n return 0LL;\n if ( a2 > (int)i )\n break;\nLABEL_2:\n ;\n }\n v3 = (int)i;\n while ( *(_DWORD *)(a1 + 4 * i - 4) != *(_DWORD *)(a1 + 4 * v3) )\n {\n if ( a2 <= (int)++v3 )\n goto LABEL_2;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov ecx, 1\njmp short loc_1178\nloc_1174:\nadd rcx, 1\nloc_1178:\nlea eax, [rcx-1]\ncmp esi, eax\njle short loc_1199\ncmp esi, ecx\njle short loc_1174\nmov edx, [rdi+rcx*4-4]\nmovsxd rax, ecx\nloc_118A:\ncmp edx, [rdi+rax*4]\njz short loc_119F\nadd rax, 1\ncmp esi, eax\njg short loc_118A\njmp short loc_1174\nloc_1199:\nmov eax, 0\nretn\nloc_119F:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n __int64 i; // rcx\n __int64 v3; // rax\n\n for ( i = 1LL; ; ++i )\n {\n if ( a2 <= (int)i - 1 )\n return 0LL;\n if ( a2 > (int)i )\n break;\nLABEL_2:\n ;\n }\n v3 = (int)i;\n while ( *(_DWORD *)(a1 + 4 * i - 4) != *(_DWORD *)(a1 + 4 * v3) )\n {\n if ( a2 <= (int)++v3 )\n goto LABEL_2;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n long long i;\n long long v3;\n for (i = 1LL;; ++i) {\n if (a2 <= (int)i - 1) return 0LL;\n if (a2 > (int)i) break;\n LABEL_2:;\n }\n v3 = (int)i;\n while (*(uint32_t *)(a1 + 4 * i - 4) != *(uint32_t *)(a1 + 4 * v3)) {\n if (a2 <= (int)++v3) goto LABEL_2;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long i;\n long long v3;\n for (i = 1LL;; ++i) {\n if (a2 <= (int)i - 1) return 0LL;\n if (a2 > (int)i) break;\n LABEL_2:;\n }\n v3 = (int)i;\n while (*(uint32_t *)(a1 + 4 * i - 4) != *(uint32_t *)(a1 + 4 * v3)) {\n if (a2 <= (int)++v3) goto LABEL_2;\n }\n return 1LL;\n}" + }, + { + "index": 19, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "bool func0(int arraynums[], int length) {\n bool found_duplicate = false;\n for (int i = 0; i < length; i++) {\n for (int j = i + 1; j < length; j++) {\n if (arraynums[i] == arraynums[j]) {\n found_duplicate = true;\n break;\n }\n }\n if (found_duplicate) {\n break;\n }\n }\n return found_duplicate;\n}", + "test": "int main() {\n\n int array1[] = {1, 2, 3, 4, 5};\n\n int array2[] = {1, 2, 3, 4, 4};\n\n int array3[] = {1, 1, 2, 2, 3, 3, 4, 4, 5};\n\n\n\n assert(func0(array1, sizeof(array1)/sizeof(array1[0])) == false);\n\n assert(func0(array2, sizeof(array2)/sizeof(array2[0])) == true);\n\n assert(func0(array3, sizeof(array3)/sizeof(array3[0])) == true);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 12e1 \nlea -0x1(%rsi),%r8d\nmov $0x1,%ecx\nadd $0x1,%r8\ncmp %r8,%rcx\nje 12e1 \nnopw 0x0(%rax,%rax,1)\nmov -0x4(%rdi,%rcx,4),%edx\nmov %rcx,%rax\njmp 12c8 \nnopl 0x0(%rax)\nadd $0x1,%rax\ncmp %eax,%esi\njle 12d8 \ncmp (%rdi,%rax,4),%edx\njne 12c0 \nmov $0x1,%eax\nretq\nnopl 0x0(%rax,%rax,1)\nadd $0x1,%rcx\ncmp %r8,%rcx\njne 12b0 \nxor %eax,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\nmov ecx, 1\nlea eax, [rcx-1]\ncmp esi, eax\njle short loc_12C3\nloc_1290:\ncmp esi, ecx\njle short loc_12B8\nmov edx, [rdi+rcx*4-4]\nmov rax, rcx\njmp short loc_12A8\nloc_12A0:\nadd rax, 1\ncmp esi, eax\njle short loc_12B8\nloc_12A8:\ncmp edx, [rdi+rax*4]\njnz short loc_12A0\nmov eax, 1\nretn\nloc_12B8:\nadd rcx, 1\nlea eax, [rcx-1]\ncmp esi, eax\njg short loc_1290\nloc_12C3:\nxor eax, eax\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // rcx\n __int64 v3; // rax\n\n v2 = 1LL;\n if ( a2 <= 0 )\n return 0LL;\n while ( a2 <= (int)v2 )\n {\nLABEL_7:\n if ( a2 <= (int)++v2 - 1 )\n return 0LL;\n }\n v3 = v2;\n while ( *(_DWORD *)(a1 + 4 * v2 - 4) != *(_DWORD *)(a1 + 4 * v3) )\n {\n if ( a2 <= (int)++v3 )\n goto LABEL_7;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\nmov ecx, 1\nlea eax, [rcx-1]\ncmp esi, eax\njle short loc_12C3\nloc_1290:\ncmp esi, ecx\njle short loc_12B8\nmov edx, [rdi+rcx*4-4]\nmov rax, rcx\njmp short loc_12A8\nloc_12A0:\nadd rax, 1\ncmp esi, eax\njle short loc_12B8\nloc_12A8:\ncmp edx, [rdi+rax*4]\njnz short loc_12A0\nmov eax, 1\nretn\nloc_12B8:\nadd rcx, 1\nlea eax, [rcx-1]\ncmp esi, eax\njg short loc_1290\nloc_12C3:\nxor eax, eax\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1280(__int64 a1, int a2)\n{\n __int64 v2; // rcx\n __int64 v3; // rax\n\n v2 = 1LL;\n if ( a2 <= 0 )\n return 0LL;\n while ( a2 <= (int)v2 )\n {\nLABEL_7:\n if ( a2 <= (int)++v2 - 1 )\n return 0LL;\n }\n v3 = v2;\n while ( *(_DWORD *)(a1 + 4 * v2 - 4) != *(_DWORD *)(a1 + 4 * v3) )\n {\n if ( a2 <= (int)++v3 )\n goto LABEL_7;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1280(long long a1, int a2) {\n long long v2;\n long long v3;\n v2 = 1LL;\n if (a2 <= 0) return 0LL;\n while (a2 <= (int)v2) {\n LABEL_7:\n if (a2 <= (int)++v2 - 1) return 0LL;\n }\n v3 = v2;\n while (*(uint32_t *)(a1 + 4 * v2 - 4) != *(uint32_t *)(a1 + 4 * v3)) {\n if (a2 <= (int)++v3) goto LABEL_7;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n long long v3;\n v2 = 1LL;\n if (a2 <= 0) return 0LL;\n while (a2 <= (int)v2) {\n LABEL_7:\n if (a2 <= (int)++v2 - 1) return 0LL;\n }\n v3 = v2;\n while (*(uint32_t *)(a1 + 4 * v2 - 4) != *(uint32_t *)(a1 + 4 * v3)) {\n if (a2 <= (int)++v3) goto LABEL_7;\n }\n return 1LL;\n}" + }, + { + "index": 20, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "bool func0(long long x) {\n if (x % 2 == 0) {\n return false;\n }\n if (x == 1) {\n return true;\n }\n x = x + 1;\n long long p = 0;\n while (x % 2 == 0) {\n x = x / 2;\n p = p + 1;\n if (p == x) {\n return true;\n }\n }\n return false;\n}", + "test": "int main() {\n\n assert(func0(383) == true);\n\n assert(func0(254) == false);\n\n assert(func0(200) == false);\n\n assert(func0(32212254719) == true);\n\n assert(func0(32212254718) == false);\n\n assert(func0(159) == true);\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov -0x18(%rbp),%rax\nand $0x1,%eax\ntest %rax,%rax\njne 1168 \nmov $0x0,%eax\njmp 11c1 \ncmpq $0x1,-0x18(%rbp)\njne 1176 \nmov $0x1,%eax\njmp 11c1 \naddq $0x1,-0x18(%rbp)\nmovq $0x0,-0x8(%rbp)\njmp 11b0 \nmov -0x18(%rbp),%rax\nmov %rax,%rdx\nshr $0x3f,%rdx\nadd %rdx,%rax\nsar %rax\nmov %rax,-0x18(%rbp)\naddq $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%rax\ncmp -0x18(%rbp),%rax\njne 11b0 \nmov $0x1,%eax\njmp 11c1 \nmov -0x18(%rbp),%rax\nand $0x1,%eax\ntest %rax,%rax\nje 1185 \nmov $0x0,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov rax, [rbp+var_18]\nand eax, 1\ntest rax, rax\njnz short loc_1168\nmov eax, 0\njmp short loc_11C1\nloc_1168:\ncmp [rbp+var_18], 1\njnz short loc_1176\nmov eax, 1\njmp short loc_11C1\nloc_1176:\nadd [rbp+var_18], 1\nmov [rbp+var_8], 0\njmp short loc_11B0\nloc_1185:\nmov rax, [rbp+var_18]\nmov rdx, rax\nshr rdx, 3Fh\nadd rax, rdx\nsar rax, 1\nmov [rbp+var_18], rax\nadd [rbp+var_8], 1\nmov rax, [rbp+var_8]\ncmp rax, [rbp+var_18]\njnz short loc_11B0\nmov eax, 1\njmp short loc_11C1\nloc_11B0:\nmov rax, [rbp+var_18]\nand eax, 1\ntest rax, rax\njz short loc_1185\nmov eax, 0\nloc_11C1:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1)\n{\n __int64 v2; // [rsp+0h] [rbp-18h]\n __int64 v3; // [rsp+10h] [rbp-8h]\n\n if ( (a1 & 1) == 0 )\n return 0LL;\n if ( a1 == 1 )\n return 1LL;\n v2 = a1 + 1;\n v3 = 0LL;\n while ( (v2 & 1) == 0 )\n {\n v2 /= 2LL;\n if ( ++v3 == v2 )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov rax, [rbp+var_18]\nand eax, 1\ntest rax, rax\njnz short loc_1168\nmov eax, 0\njmp short loc_11C1\nloc_1168:\ncmp [rbp+var_18], 1\njnz short loc_1176\nmov eax, 1\njmp short loc_11C1\nloc_1176:\nadd [rbp+var_18], 1\nmov [rbp+var_8], 0\njmp short loc_11B0\nloc_1185:\nmov rax, [rbp+var_18]\nmov rdx, rax\nshr rdx, 3Fh\nadd rax, rdx\nsar rax, 1\nmov [rbp+var_18], rax\nadd [rbp+var_8], 1\nmov rax, [rbp+var_8]\ncmp rax, [rbp+var_18]\njnz short loc_11B0\nmov eax, 1\njmp short loc_11C1\nloc_11B0:\nmov rax, [rbp+var_18]\nand eax, 1\ntest rax, rax\njz short loc_1185\nmov eax, 0\nloc_11C1:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(__int64 a1)\n{\n __int64 v2; // [rsp+0h] [rbp-18h]\n __int64 v3; // [rsp+10h] [rbp-8h]\n\n if ( (a1 & 1) == 0 )\n return 0LL;\n if ( a1 == 1 )\n return 1LL;\n v2 = a1 + 1;\n v3 = 0LL;\n while ( (v2 & 1) == 0 )\n {\n v2 /= 2LL;\n if ( ++v3 == v2 )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(long long a1) {\n long long v2;\n long long v3;\n if ((a1 & 1) == 0) return 0LL;\n if (a1 == 1) return 1LL;\n v2 = a1 + 1;\n v3 = 0LL;\n while ((v2 & 1) == 0) {\n v2 /= 2LL;\n if (++v3 == v2) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1) {\n long long v2;\n long long v3;\n if ((a1 & 1) == 0) return 0LL;\n if (a1 == 1) return 1LL;\n v2 = a1 + 1;\n v3 = 0LL;\n while ((v2 & 1) == 0) {\n v2 /= 2LL;\n if (++v3 == v2) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 20, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "bool func0(long long x) {\n if (x % 2 == 0) {\n return false;\n }\n if (x == 1) {\n return true;\n }\n x = x + 1;\n long long p = 0;\n while (x % 2 == 0) {\n x = x / 2;\n p = p + 1;\n if (p == x) {\n return true;\n }\n }\n return false;\n}", + "test": "int main() {\n\n assert(func0(383) == true);\n\n assert(func0(254) == false);\n\n assert(func0(200) == false);\n\n assert(func0(32212254719) == true);\n\n assert(func0(32212254718) == false);\n\n assert(func0(159) == true);\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x0,%eax\ntest $0x1,%dil\nje 118e \nmov $0x1,%eax\ncmp $0x1,%rdi\nje 118e \nlea 0x1(%rdi),%rax\nmov $0x0,%edx\ntest $0x1,%al\njne 118f \nmov %rax,%rdi\nshr $0x3f,%rdi\nadd %rax,%rdi\nsar %rdi\nmov %rdi,%rax\nadd $0x1,%rdx\ncmp %rdx,%rdi\njne 116c \nmov $0x1,%eax\nretq\nmov $0x0,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov eax, 0\ntest dil, 1\njz short locret_1190\nmov eax, 1\ncmp rdi, 1\njz short locret_1190\nadd rdi, 1\nmov edx, 0\nloc_116C:\ntest dil, 1\njnz short loc_1191\nmov rax, rdi\nshr rax, 3Fh\nadd rax, rdi\nsar rax, 1\nmov rdi, rax\nadd rdx, 1\ncmp rax, rdx\njnz short loc_116C\nmov eax, 1\nlocret_1190:\nretn\nloc_1191:\nmov eax, 0\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1)\n{\n __int64 result; // rax\n __int64 v2; // rdi\n __int64 v3; // rdx\n\n result = 0LL;\n if ( (a1 & 1) != 0 )\n {\n result = 1LL;\n if ( a1 != 1 )\n {\n v2 = a1 + 1;\n v3 = 0LL;\n while ( (v2 & 1) == 0 )\n {\n v2 /= 2LL;\n if ( v2 == ++v3 )\n return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmov eax, 0\ntest dil, 1\njz short locret_1190\nmov eax, 1\ncmp rdi, 1\njz short locret_1190\nadd rdi, 1\nmov edx, 0\nloc_116C:\ntest dil, 1\njnz short loc_1191\nmov rax, rdi\nshr rax, 3Fh\nadd rax, rdi\nsar rax, 1\nmov rdi, rax\nadd rdx, 1\ncmp rax, rdx\njnz short loc_116C\nmov eax, 1\nlocret_1190:\nretn\nloc_1191:\nmov eax, 0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(__int64 a1)\n{\n __int64 result; // rax\n __int64 v2; // rdi\n __int64 v3; // rdx\n\n result = 0LL;\n if ( (a1 & 1) != 0 )\n {\n result = 1LL;\n if ( a1 != 1 )\n {\n v2 = a1 + 1;\n v3 = 0LL;\n while ( (v2 & 1) == 0 )\n {\n v2 /= 2LL;\n if ( v2 == ++v3 )\n return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(long long a1) {\n long long result;\n long long v2;\n long long v3;\n result = 0LL;\n if ((a1 & 1) != 0) {\n result = 1LL;\n if (a1 != 1) {\n v2 = a1 + 1;\n v3 = 0LL;\n while ((v2 & 1) == 0) {\n v2 /= 2LL;\n if (v2 == ++v3) return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1) {\n long long result;\n long long v2;\n long long v3;\n result = 0LL;\n if ((a1 & 1) != 0) {\n result = 1LL;\n if (a1 != 1) {\n v2 = a1 + 1;\n v3 = 0LL;\n while ((v2 & 1) == 0) {\n v2 /= 2LL;\n if (v2 == ++v3) return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}" + }, + { + "index": 20, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "bool func0(long long x) {\n if (x % 2 == 0) {\n return false;\n }\n if (x == 1) {\n return true;\n }\n x = x + 1;\n long long p = 0;\n while (x % 2 == 0) {\n x = x / 2;\n p = p + 1;\n if (p == x) {\n return true;\n }\n }\n return false;\n}", + "test": "int main() {\n\n assert(func0(383) == true);\n\n assert(func0(254) == false);\n\n assert(func0(200) == false);\n\n assert(func0(32212254719) == true);\n\n assert(func0(32212254718) == false);\n\n assert(func0(159) == true);\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest $0x1,%dil\nje 1248 \ncmp $0x1,%rdi\nje 1250 \njmp 11f0 \nnopw 0x0(%rax,%rax,1)\nxor %eax,%eax\nretq\nnopl 0x0(%rax,%rax,1)\nmov $0x1,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0_part_0:\nadd rdi, 1\nxor eax, eax\njmp short loc_1216\nloc_1200:\nmov rdx, rdi\nadd rax, 1\nshr rdx, 3Fh\nadd rdi, rdx\nsar rdi, 1\ncmp rdi, rax\njz short loc_1220\nloc_1216:\ntest dil, 1\njz short loc_1200\nxor eax, eax\nretn\nloc_1220:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0_part_0(__int64 a1)\n{\n __int64 v1; // rdi\n __int64 v2; // rax\n\n v1 = a1 + 1;\n v2 = 0LL;\n do\n {\n if ( (v1 & 1) != 0 )\n return 0LL;\n ++v2;\n v1 /= 2LL;\n }\n while ( v1 != v2 );\n return 1LL;\n}", + "ida_strip_asm": "sub_11F0:\nadd rdi, 1\nxor eax, eax\njmp short loc_1216\nloc_1200:\nmov rdx, rdi\nadd rax, 1\nshr rdx, 3Fh\nadd rdi, rdx\nsar rdi, 1\ncmp rdi, rax\njz short loc_1220\nloc_1216:\ntest dil, 1\njz short loc_1200\nxor eax, eax\nretn\nloc_1220:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11F0(__int64 a1)\n{\n __int64 v1; // rdi\n __int64 v2; // rax\n\n v1 = a1 + 1;\n v2 = 0LL;\n do\n {\n if ( (v1 & 1) != 0 )\n return 0LL;\n ++v2;\n v1 /= 2LL;\n }\n while ( v1 != v2 );\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11F0(long long a1) {\n long long v1;\n long long v2;\n v1 = a1 + 1;\n v2 = 0LL;\n do {\n if ((v1 & 1) != 0) return 0LL;\n ++v2;\n v1 /= 2LL;\n } while (v1 != v2);\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0_part_0(long long a1) {\n long long v1;\n long long v2;\n v1 = a1 + 1;\n v2 = 0LL;\n do {\n if ((v1 & 1) != 0) return 0LL;\n ++v2;\n v1 /= 2LL;\n } while (v1 != v2);\n return 1LL;\n}" + }, + { + "index": 20, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "bool func0(long long x) {\n if (x % 2 == 0) {\n return false;\n }\n if (x == 1) {\n return true;\n }\n x = x + 1;\n long long p = 0;\n while (x % 2 == 0) {\n x = x / 2;\n p = p + 1;\n if (p == x) {\n return true;\n }\n }\n return false;\n}", + "test": "int main() {\n\n assert(func0(383) == true);\n\n assert(func0(254) == false);\n\n assert(func0(200) == false);\n\n assert(func0(32212254719) == true);\n\n assert(func0(32212254718) == false);\n\n assert(func0(159) == true);\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nxor %eax,%eax\ntest $0x1,%dil\nje 1275 \nmov $0x1,%eax\ncmp $0x1,%rdi\nje 1275 \nadd $0x1,%rdi\nxor %eax,%eax\njmp 1266 \nmov %rdi,%rdx\nadd $0x1,%rax\nshr $0x3f,%rdx\nadd %rdx,%rdi\nsar %rdi\ncmp %rax,%rdi\nje 1270 \ntest $0x1,%dil\nje 1250 \nxor %eax,%eax\nretq\nmov $0x1,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0_part_0:\nadd rdi, 1\nxor eax, eax\njmp short loc_1216\nloc_1200:\nmov rdx, rdi\nadd rax, 1\nshr rdx, 3Fh\nadd rdi, rdx\nsar rdi, 1\ncmp rdi, rax\njz short loc_1220\nloc_1216:\ntest dil, 1\njz short loc_1200\nxor eax, eax\nretn\nloc_1220:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0_part_0(__int64 a1)\n{\n __int64 v1; // rdi\n __int64 v2; // rax\n\n v1 = a1 + 1;\n v2 = 0LL;\n do\n {\n if ( (v1 & 1) != 0 )\n return 0LL;\n ++v2;\n v1 /= 2LL;\n }\n while ( v1 != v2 );\n return 1LL;\n}", + "ida_strip_asm": "sub_11F0:\nadd rdi, 1\nxor eax, eax\njmp short loc_1216\nloc_1200:\nmov rdx, rdi\nadd rax, 1\nshr rdx, 3Fh\nadd rdi, rdx\nsar rdi, 1\ncmp rdi, rax\njz short loc_1220\nloc_1216:\ntest dil, 1\njz short loc_1200\nxor eax, eax\nretn\nloc_1220:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11F0(__int64 a1)\n{\n __int64 v1; // rdi\n __int64 v2; // rax\n\n v1 = a1 + 1;\n v2 = 0LL;\n do\n {\n if ( (v1 & 1) != 0 )\n return 0LL;\n ++v2;\n v1 /= 2LL;\n }\n while ( v1 != v2 );\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11F0(long long a1) {\n long long v1;\n long long v2;\n v1 = a1 + 1;\n v2 = 0LL;\n do {\n if ((v1 & 1) != 0) return 0LL;\n ++v2;\n v1 /= 2LL;\n } while (v1 != v2);\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0_part_0(long long a1) {\n long long v1;\n long long v2;\n v1 = a1 + 1;\n v2 = 0LL;\n do {\n if ((v1 & 1) != 0) return 0LL;\n ++v2;\n v1 /= 2LL;\n } while (v1 != v2);\n return 1LL;\n}" + }, + { + "index": 21, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int m, int n, int* length) {\n *length = m;\n int* results = malloc(sizeof(int) * m);\n if (!results) {\n return NULL;\n }\n for (int i = 0; i < m; i++) {\n results[i] = (i + 1) * n;\n }\n return results;\n}", + "test": "int main() {\n\n int length, *result;\n\n \n\n result = func0(4, 3, &length);\n\n int expected1[] = {3, 6, 9, 12};\n\n for (int i = 0; i < length; i++) {\n\n assert(result[i] == expected1[i]);\n\n }\n\n free(result);\n\n \n\n result = func0(2, 5, &length);\n\n int expected2[] = {5, 10};\n\n for (int i = 0; i < length; i++) {\n\n assert(result[i] == expected2[i]);\n\n }\n\n free(result);\n\n \n\n result = func0(9, 2, &length);\n\n int expected3[] = {2, 4, 6, 8, 10, 12, 14, 16, 18};\n\n for (int i = 0; i < length; i++) {\n\n assert(result[i] == expected3[i]);\n\n }\n\n free(result);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov %rdx,-0x20(%rbp)\nmov -0x20(%rbp),%rax\nmov -0x14(%rbp),%edx\nmov %edx,(%rax)\nmov -0x14(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\ncmpq $0x0,-0x8(%rbp)\njne 11eb \nmov $0x0,%eax\njmp 1225 \nmovl $0x0,-0xc(%rbp)\njmp 1219 \nmov -0xc(%rbp),%eax\nadd $0x1,%eax\nmov -0xc(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nimul -0x18(%rbp),%eax\nmov %eax,(%rdx)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x14(%rbp),%eax\njl 11f4 \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_20], rdx\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_14]\nmov [rax], edx\nmov eax, [rbp+var_14]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\ncmp [rbp+var_8], 0\njnz short loc_11EB\nmov eax, 0\njmp short locret_1225\nloc_11EB:\nmov [rbp+var_C], 0\njmp short loc_1219\nloc_11F4:\nmov eax, [rbp+var_C]\nadd eax, 1\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nimul eax, [rbp+var_18]\nmov [rdx], eax\nadd [rbp+var_C], 1\nloc_1219:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_14]\njl short loc_11F4\nmov rax, [rbp+var_8]\nlocret_1225:\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int a1, int a2, _DWORD *a3)\n{\n int i; // [rsp+14h] [rbp-Ch]\n _DWORD *v5; // [rsp+18h] [rbp-8h]\n\n *a3 = a1;\n v5 = malloc(4LL * a1);\n if ( !v5 )\n return 0LL;\n for ( i = 0; i < a1; ++i )\n v5[i] = a2 * (i + 1);\n return v5;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_20], rdx\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_14]\nmov [rax], edx\nmov eax, [rbp+var_14]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\ncmp [rbp+var_8], 0\njnz short loc_11EB\nmov eax, 0\njmp short locret_1225\nloc_11EB:\nmov [rbp+var_C], 0\njmp short loc_1219\nloc_11F4:\nmov eax, [rbp+var_C]\nadd eax, 1\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nimul eax, [rbp+var_18]\nmov [rdx], eax\nadd [rbp+var_C], 1\nloc_1219:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_14]\njl short loc_11F4\nmov rax, [rbp+var_8]\nlocret_1225:\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(int a1, int a2, _DWORD *a3)\n{\n int i; // [rsp+14h] [rbp-Ch]\n _DWORD *v5; // [rsp+18h] [rbp-8h]\n\n *a3 = a1;\n v5 = malloc(4LL * a1);\n if ( !v5 )\n return 0LL;\n for ( i = 0; i < a1; ++i )\n v5[i] = a2 * (i + 1);\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(int a1, int a2, uint32_t *a3) {\n int i;\n uint32_t *v5;\n *a3 = a1;\n v5 = malloc(4LL * a1);\n if (!v5) return 0LL;\n for (i = 0; i < a1; ++i) v5[i] = a2 * (i + 1);\n return v5;\n}", + "ida_pseudo_norm": "uint32_t *func0(int a1, int a2, uint32_t *a3) {\n int i;\n uint32_t *v5;\n *a3 = a1;\n v5 = malloc(4LL * a1);\n if (!v5) return 0LL;\n for (i = 0; i < a1; ++i) v5[i] = a2 * (i + 1);\n return v5;\n}" + }, + { + "index": 21, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int m, int n, int* length) {\n *length = m;\n int* results = malloc(sizeof(int) * m);\n if (!results) {\n return NULL;\n }\n for (int i = 0; i < m; i++) {\n results[i] = (i + 1) * n;\n }\n return results;\n}", + "test": "int main() {\n\n int length, *result;\n\n \n\n result = func0(4, 3, &length);\n\n int expected1[] = {3, 6, 9, 12};\n\n for (int i = 0; i < length; i++) {\n\n assert(result[i] == expected1[i]);\n\n }\n\n free(result);\n\n \n\n result = func0(2, 5, &length);\n\n int expected2[] = {5, 10};\n\n for (int i = 0; i < length; i++) {\n\n assert(result[i] == expected2[i]);\n\n }\n\n free(result);\n\n \n\n result = func0(9, 2, &length);\n\n int expected3[] = {2, 4, 6, 8, 10, 12, 14, 16, 18};\n\n for (int i = 0; i < length; i++) {\n\n assert(result[i] == expected3[i]);\n\n }\n\n free(result);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %edi,%ebp\nmov %esi,%ebx\nmov %edi,(%rdx)\nmovslq %edi,%rdi\nshl $0x2,%rdi\ncallq 10b0 \ntest %rax,%rax\nje 11ea \ntest %ebp,%ebp\njle 11ea \nmov %ebx,%edi\nmov %rax,%rdx\nlea -0x1(%rbp),%ecx\nlea 0x4(%rax,%rcx,4),%rcx\nmov %ebx,%esi\nmov %esi,(%rdx)\nadd %edi,%esi\nadd $0x4,%rdx\ncmp %rcx,%rdx\njne 11dd \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov r12d, edi\nmov ebp, esi\nmov [rdx], edi\nmovsxd rsi, edi\nlea rbx, ds:0[rsi*4]\nmov rdi, rbx; size\ncall _malloc\ntest rax, rax\njz short loc_11EB\ntest r12d, r12d\njle short loc_11EB\nmov rdx, rax\nlea rsi, [rbx+rax]\nmov ecx, ebp\nloc_11DE:\nmov [rdx], ecx\nadd ecx, ebp\nadd rdx, 4\ncmp rdx, rsi\njnz short loc_11DE\nloc_11EB:\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int a1, int a2, int *a3)\n{\n _DWORD *result; // rax\n _DWORD *v4; // rdx\n int v5; // ecx\n\n *a3 = a1;\n result = malloc(4LL * a1);\n if ( result && a1 > 0 )\n {\n v4 = result;\n v5 = a2;\n do\n {\n *v4 = v5;\n v5 += a2;\n ++v4;\n }\n while ( v4 != &result[a1] );\n }\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r12\npush rbp\npush rbx\nmov r12d, edi\nmov ebp, esi\nmov [rdx], edi\nmovsxd rsi, edi\nlea rbx, ds:0[rsi*4]\nmov rdi, rbx; size\ncall _malloc\ntest rax, rax\njz short loc_11EB\ntest r12d, r12d\njle short loc_11EB\nmov rdx, rax\nlea rsi, [rbx+rax]\nmov ecx, ebp\nloc_11DE:\nmov [rdx], ecx\nadd ecx, ebp\nadd rdx, 4\ncmp rdx, rsi\njnz short loc_11DE\nloc_11EB:\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(int a1, int a2, int *a3)\n{\n _DWORD *result; // rax\n _DWORD *v4; // rdx\n int v5; // ecx\n\n *a3 = a1;\n result = malloc(4LL * a1);\n if ( result && a1 > 0 )\n {\n v4 = result;\n v5 = a2;\n do\n {\n *v4 = v5;\n v5 += a2;\n ++v4;\n }\n while ( v4 != &result[a1] );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(int a1, int a2, int *a3) {\n uint32_t *result;\n uint32_t *v4;\n int v5;\n *a3 = a1;\n result = malloc(4LL * a1);\n if (result && a1 > 0) {\n v4 = result;\n v5 = a2;\n do {\n *v4 = v5;\n v5 += a2;\n ++v4;\n } while (v4 != &result[a1]);\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(int a1, int a2, int *a3) {\n uint32_t *result;\n uint32_t *v4;\n int v5;\n *a3 = a1;\n result = malloc(4LL * a1);\n if (result && a1 > 0) {\n v4 = result;\n v5 = a2;\n do {\n *v4 = v5;\n v5 += a2;\n ++v4;\n } while (v4 != &result[a1]);\n }\n return result;\n}" + }, + { + "index": 21, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int m, int n, int* length) {\n *length = m;\n int* results = malloc(sizeof(int) * m);\n if (!results) {\n return NULL;\n }\n for (int i = 0; i < m; i++) {\n results[i] = (i + 1) * n;\n }\n return results;\n}", + "test": "int main() {\n\n int length, *result;\n\n \n\n result = func0(4, 3, &length);\n\n int expected1[] = {3, 6, 9, 12};\n\n for (int i = 0; i < length; i++) {\n\n assert(result[i] == expected1[i]);\n\n }\n\n free(result);\n\n \n\n result = func0(2, 5, &length);\n\n int expected2[] = {5, 10};\n\n for (int i = 0; i < length; i++) {\n\n assert(result[i] == expected2[i]);\n\n }\n\n free(result);\n\n \n\n result = func0(9, 2, &length);\n\n int expected3[] = {2, 4, 6, 8, 10, 12, 14, 16, 18};\n\n for (int i = 0; i < length; i++) {\n\n assert(result[i] == expected3[i]);\n\n }\n\n free(result);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmovslq %edi,%rdi\npush %rbx\nmov %rdi,%rbp\nmov %esi,%ebx\nsub $0x8,%rsp\nmov %edi,(%rdx)\nshl $0x2,%rdi\ncallq 10b0 \ntest %rax,%rax\nje 13b5 \ntest %ebp,%ebp\njle 13b5 \nlea -0x1(%rbp),%ecx\nmov %rax,%rdx\nlea 0x4(%rax,%rcx,4),%rsi\nmov %ebx,%ecx\nnopl 0x0(%rax,%rax,1)\nmov %ecx,(%rdx)\nadd $0x4,%rdx\nadd %ebx,%ecx\ncmp %rsi,%rdx\njne 13a8 \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\nmovsxd rdi, edi\npush r12\npush rbp\nmov r12, rdi\nmov ebp, esi\npush rbx\nlea rbx, ds:0[rdi*4]\nmov [rdx], edi\nmov rdi, rbx; size\ncall _malloc\ntest rax, rax\njz short loc_1375\ntest r12d, r12d\njle short loc_1375\nmov rdx, rax\nlea rdi, [rbx+rax]\nmov ecx, ebp\nnop dword ptr [rax]\nloc_1368:\nmov [rdx], ecx\nadd rdx, 4\nadd ecx, ebp\ncmp rdx, rdi\njnz short loc_1368\nloc_1375:\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int a1, int a2, int *a3)\n{\n _DWORD *result; // rax\n _DWORD *v4; // rdx\n int v5; // ecx\n\n *a3 = a1;\n result = malloc(4LL * a1);\n if ( result && a1 > 0 )\n {\n v4 = result;\n v5 = a2;\n do\n {\n *v4++ = v5;\n v5 += a2;\n }\n while ( v4 != &result[a1] );\n }\n return result;\n}", + "ida_strip_asm": "sub_1330:\nendbr64\nmovsxd rdi, edi\npush r12\npush rbp\nmov r12, rdi\nmov ebp, esi\npush rbx\nlea rbx, ds:0[rdi*4]\nmov [rdx], edi\nmov rdi, rbx; size\ncall _malloc\ntest rax, rax\njz short loc_1375\ntest r12d, r12d\njle short loc_1375\nmov rdx, rax\nlea rdi, [rbx+rax]\nmov ecx, ebp\nnop dword ptr [rax]\nloc_1368:\nmov [rdx], ecx\nadd rdx, 4\nadd ecx, ebp\ncmp rdx, rdi\njnz short loc_1368\nloc_1375:\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1330(int a1, int a2, int *a3)\n{\n _DWORD *result; // rax\n _DWORD *v4; // rdx\n int v5; // ecx\n\n *a3 = a1;\n result = malloc(4LL * a1);\n if ( result && a1 > 0 )\n {\n v4 = result;\n v5 = a2;\n do\n {\n *v4++ = v5;\n v5 += a2;\n }\n while ( v4 != &result[a1] );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1330(int a1, int a2, int *a3) {\n uint32_t *result;\n uint32_t *v4;\n int v5;\n *a3 = a1;\n result = malloc(4LL * a1);\n if (result && a1 > 0) {\n v4 = result;\n v5 = a2;\n do {\n *v4++ = v5;\n v5 += a2;\n } while (v4 != &result[a1]);\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(int a1, int a2, int *a3) {\n uint32_t *result;\n uint32_t *v4;\n int v5;\n *a3 = a1;\n result = malloc(4LL * a1);\n if (result && a1 > 0) {\n v4 = result;\n v5 = a2;\n do {\n *v4++ = v5;\n v5 += a2;\n } while (v4 != &result[a1]);\n }\n return result;\n}" + }, + { + "index": 21, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int m, int n, int* length) {\n *length = m;\n int* results = malloc(sizeof(int) * m);\n if (!results) {\n return NULL;\n }\n for (int i = 0; i < m; i++) {\n results[i] = (i + 1) * n;\n }\n return results;\n}", + "test": "int main() {\n\n int length, *result;\n\n \n\n result = func0(4, 3, &length);\n\n int expected1[] = {3, 6, 9, 12};\n\n for (int i = 0; i < length; i++) {\n\n assert(result[i] == expected1[i]);\n\n }\n\n free(result);\n\n \n\n result = func0(2, 5, &length);\n\n int expected2[] = {5, 10};\n\n for (int i = 0; i < length; i++) {\n\n assert(result[i] == expected2[i]);\n\n }\n\n free(result);\n\n \n\n result = func0(9, 2, &length);\n\n int expected3[] = {2, 4, 6, 8, 10, 12, 14, 16, 18};\n\n for (int i = 0; i < length; i++) {\n\n assert(result[i] == expected3[i]);\n\n }\n\n free(result);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmovslq %edi,%rdi\nmov %esi,%ebp\npush %rbx\nmov %rdi,%rbx\nsub $0x8,%rsp\nmov %edi,(%rdx)\nshl $0x2,%rdi\ncallq 10b0 \ntest %rax,%rax\nje 1493 \ntest %ebx,%ebx\njle 1493 \nlea -0x1(%rbx),%edx\ncmp $0x2,%edx\njbe 149a \nmovd %ebp,%xmm7\nmov %ebx,%ecx\nmovdqa 0xca8(%rip),%xmm2\nmovdqa 0xcb0(%rip),%xmm6\npshufd $0x0,%xmm7,%xmm3\nshr $0x2,%ecx\nmovdqa 0xcb0(%rip),%xmm5\nmov %rax,%rdx\nshl $0x4,%rcx\nmovdqa %xmm3,%xmm4\nadd %rax,%rcx\npsrlq $0x20,%xmm4\nnopl 0x0(%rax,%rax,1)\nmovdqa %xmm2,%xmm0\nadd $0x10,%rdx\npaddd %xmm6,%xmm2\npaddd %xmm5,%xmm0\nmovdqa %xmm0,%xmm1\npsrlq $0x20,%xmm0\npmuludq %xmm3,%xmm1\npmuludq %xmm4,%xmm0\npshufd $0x8,%xmm1,%xmm1\npshufd $0x8,%xmm0,%xmm0\npunpckldq %xmm0,%xmm1\nmovups %xmm1,-0x10(%rdx)\ncmp %rcx,%rdx\njne 1428 \nmov %ebx,%edx\nand $0xfffffffc,%edx\ntest $0x3,%bl\nje 1493 \nlea 0x1(%rdx),%ecx\nmovslq %edx,%rdi\nmov %ecx,%esi\nimul %ebp,%esi\nmov %esi,(%rax,%rdi,4)\ncmp %ebx,%ecx\njge 1493 \nadd %ebp,%esi\nmovslq %ecx,%rcx\nadd $0x2,%edx\nmov %esi,(%rax,%rcx,4)\ncmp %edx,%ebx\njle 1493 \nmovslq %edx,%rdx\nadd %esi,%ebp\nmov %ebp,(%rax,%rdx,4)\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nxor %edx,%edx\njmp 146a \nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmovsxd rdi, edi\nmov ebp, esi\npush rbx\nmov rbx, rdi\nsub rsp, 8\nmov [rdx], edi\nshl rdi, 2; size\ncall _malloc\nmov rcx, rax\ntest rax, rax\njz loc_1461\ntest ebx, ebx\njle loc_1461\nlea eax, [rbx-1]\ncmp eax, 2\njbe loc_146B\nmovd xmm7, ebp\nmov edx, ebx\nmovdqa xmm2, cs:xmmword_2080\nmovdqa xmm6, cs:xmmword_2090\npshufd xmm3, xmm7, 0\nshr edx, 2\nmovdqa xmm5, cs:xmmword_20A0\nmov rax, rcx\nshl rdx, 4\nmovdqa xmm4, xmm3\nadd rdx, rcx\npsrlq xmm4, 20h ; ' '\nnop word ptr [rax+rax+00000000h]\nloc_13F0:\nmovdqa xmm0, xmm2\nadd rax, 10h\npaddd xmm2, xmm6\npaddd xmm0, xmm5\nmovdqa xmm1, xmm0\npsrlq xmm0, 20h ; ' '\npmuludq xmm1, xmm3\npmuludq xmm0, xmm4\npshufd xmm1, xmm1, 8\npshufd xmm0, xmm0, 8\npunpckldq xmm1, xmm0\nmovups xmmword ptr [rax-10h], xmm1\ncmp rax, rdx\njnz short loc_13F0\nmov eax, ebx\nand eax, 0FFFFFFFCh\ntest bl, 3\njz short loc_1461\nloc_1432:\nlea esi, [rax+1]\nmovsxd rdi, eax\nmov edx, esi\nlea r8, ds:0[rdi*4]\nimul edx, ebp\nmov [rcx+rdi*4], edx\ncmp esi, ebx\njge short loc_1461\nadd edx, ebp\nadd eax, 2\nmov [rcx+r8+4], edx\ncmp ebx, eax\njle short loc_1461\nadd ebp, edx\nmov [rcx+r8+8], ebp\nloc_1461:\nadd rsp, 8\nmov rax, rcx\npop rbx\npop rbp\nretn\nloc_146B:\nxor eax, eax\njmp short loc_1432", + "ida_pseudo": "__m128i *__fastcall func0(int a1, unsigned int a2, int *a3)\n{\n __m128i *v3; // rcx\n __m128i si128; // xmm2\n __m128i v5; // xmm6\n __m128i v6; // xmm3\n __m128i v7; // xmm5\n __m128i *v8; // rax\n __m128i v9; // xmm4\n __m128i v10; // xmm0\n __m128i v11; // xmm1\n int v12; // eax\n __int64 v13; // r8\n int v14; // edx\n unsigned int v15; // edx\n\n *a3 = a1;\n v3 = (__m128i *)malloc(4LL * a1);\n if ( v3 && a1 > 0 )\n {\n if ( (unsigned int)(a1 - 1) <= 2 )\n {\n v12 = 0;\n }\n else\n {\n si128 = _mm_load_si128((const __m128i *)&xmmword_2080);\n v5 = _mm_load_si128((const __m128i *)&xmmword_2090);\n v6 = _mm_shuffle_epi32(_mm_cvtsi32_si128(a2), 0);\n v7 = _mm_load_si128((const __m128i *)&xmmword_20A0);\n v8 = v3;\n v9 = _mm_srli_epi64(v6, 0x20u);\n do\n {\n v10 = si128;\n ++v8;\n si128 = _mm_add_epi32(si128, v5);\n v11 = _mm_add_epi32(v10, v7);\n v8[-1] = _mm_unpacklo_epi32(\n _mm_shuffle_epi32(_mm_mul_epu32(v11, v6), 8),\n _mm_shuffle_epi32(_mm_mul_epu32(_mm_srli_epi64(v11, 0x20u), v9), 8));\n }\n while ( v8 != &v3[(unsigned int)a1 >> 2] );\n v12 = a1 & 0x7FFFFFFC;\n if ( (a1 & 3) == 0 )\n return v3;\n }\n v13 = v12;\n v14 = a2 * (v12 + 1);\n v3->m128i_i32[v13] = v14;\n if ( v12 + 1 < a1 )\n {\n v15 = a2 + v14;\n v3->m128i_i32[v13 + 1] = v15;\n if ( a1 > v12 + 2 )\n v3->m128i_i32[v13 + 2] = v15 + a2;\n }\n }\n return v3;\n}", + "ida_strip_asm": "sub_1370:\nendbr64\npush rbp\nmovsxd rdi, edi\nmov ebp, esi\npush rbx\nmov rbx, rdi\nsub rsp, 8\nmov [rdx], edi\nshl rdi, 2; size\ncall _malloc\nmov rcx, rax\ntest rax, rax\njz loc_1461\ntest ebx, ebx\njle loc_1461\nlea eax, [rbx-1]\ncmp eax, 2\njbe loc_146B\nmovd xmm7, ebp\nmov edx, ebx\nmovdqa xmm2, cs:xmmword_2080\nmovdqa xmm6, cs:xmmword_2090\npshufd xmm3, xmm7, 0\nshr edx, 2\nmovdqa xmm5, cs:xmmword_20A0\nmov rax, rcx\nshl rdx, 4\nmovdqa xmm4, xmm3\nadd rdx, rcx\npsrlq xmm4, 20h ; ' '\nnop word ptr [rax+rax+00000000h]\nloc_13F0:\nmovdqa xmm0, xmm2\nadd rax, 10h\npaddd xmm2, xmm6\npaddd xmm0, xmm5\nmovdqa xmm1, xmm0\npsrlq xmm0, 20h ; ' '\npmuludq xmm1, xmm3\npmuludq xmm0, xmm4\npshufd xmm1, xmm1, 8\npshufd xmm0, xmm0, 8\npunpckldq xmm1, xmm0\nmovups xmmword ptr [rax-10h], xmm1\ncmp rax, rdx\njnz short loc_13F0\nmov eax, ebx\nand eax, 0FFFFFFFCh\ntest bl, 3\njz short loc_1461\nloc_1432:\nlea esi, [rax+1]\nmovsxd rdi, eax\nmov edx, esi\nlea r8, ds:0[rdi*4]\nimul edx, ebp\nmov [rcx+rdi*4], edx\ncmp esi, ebx\njge short loc_1461\nadd edx, ebp\nadd eax, 2\nmov [rcx+r8+4], edx\ncmp ebx, eax\njle short loc_1461\nadd ebp, edx\nmov [rcx+r8+8], ebp\nloc_1461:\nadd rsp, 8\nmov rax, rcx\npop rbx\npop rbp\nretn\nloc_146B:\nxor eax, eax\njmp short loc_1432", + "ida_strip_pseudo": "__m128i *__fastcall sub_1370(int a1, unsigned int a2, int *a3)\n{\n __m128i *v3; // rcx\n __m128i si128; // xmm2\n __m128i v5; // xmm6\n __m128i v6; // xmm3\n __m128i v7; // xmm5\n __m128i *v8; // rax\n __m128i v9; // xmm4\n __m128i v10; // xmm0\n __m128i v11; // xmm1\n int v12; // eax\n __int64 v13; // r8\n int v14; // edx\n unsigned int v15; // edx\n\n *a3 = a1;\n v3 = (__m128i *)malloc(4LL * a1);\n if ( v3 && a1 > 0 )\n {\n if ( (unsigned int)(a1 - 1) <= 2 )\n {\n v12 = 0;\n }\n else\n {\n si128 = _mm_load_si128((const __m128i *)&xmmword_2080);\n v5 = _mm_load_si128((const __m128i *)&xmmword_2090);\n v6 = _mm_shuffle_epi32(_mm_cvtsi32_si128(a2), 0);\n v7 = _mm_load_si128((const __m128i *)&xmmword_20A0);\n v8 = v3;\n v9 = _mm_srli_epi64(v6, 0x20u);\n do\n {\n v10 = si128;\n ++v8;\n si128 = _mm_add_epi32(si128, v5);\n v11 = _mm_add_epi32(v10, v7);\n v8[-1] = _mm_unpacklo_epi32(\n _mm_shuffle_epi32(_mm_mul_epu32(v11, v6), 8),\n _mm_shuffle_epi32(_mm_mul_epu32(_mm_srli_epi64(v11, 0x20u), v9), 8));\n }\n while ( v8 != &v3[(unsigned int)a1 >> 2] );\n v12 = a1 & 0x7FFFFFFC;\n if ( (a1 & 3) == 0 )\n return v3;\n }\n v13 = v12;\n v14 = a2 * (v12 + 1);\n v3->m128i_i32[v13] = v14;\n if ( v12 + 1 < a1 )\n {\n v15 = a2 + v14;\n v3->m128i_i32[v13 + 1] = v15;\n if ( a1 > v12 + 2 )\n v3->m128i_i32[v13 + 2] = v15 + a2;\n }\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__m128i *sub_1370(int a1, unsigned int a2, int *a3) {\n __m128i *v3;\n __m128i si128;\n __m128i v5;\n __m128i v6;\n __m128i v7;\n __m128i *v8;\n __m128i v9;\n __m128i v10;\n __m128i v11;\n int v12;\n long long v13;\n int v14;\n unsigned int v15;\n *a3 = a1;\n v3 = (__m128i *)malloc(4LL * a1);\n if (v3 && a1 > 0) {\n if ((unsigned int)(a1 - 1) <= 2) {\n v12 = 0;\n } else {\n si128 = _mm_load_si128((const __m128i *)&xmmword_2080);\n v5 = _mm_load_si128((const __m128i *)&xmmword_2090);\n v6 = _mm_shuffle_epi32(_mm_cvtsi32_si128(a2), 0);\n v7 = _mm_load_si128((const __m128i *)&xmmword_20A0);\n v8 = v3;\n v9 = _mm_srli_epi64(v6, 32u);\n do {\n v10 = si128;\n ++v8;\n si128 = _mm_add_epi32(si128, v5);\n v11 = _mm_add_epi32(v10, v7);\n v8[-1] = _mm_unpacklo_epi32(\n _mm_shuffle_epi32(_mm_mul_epu32(v11, v6), 8),\n _mm_shuffle_epi32(_mm_mul_epu32(_mm_srli_epi64(v11, 32u), v9), 8));\n } while (v8 != &v3[(unsigned int)a1 >> 2]);\n v12 = a1 & 2147483644;\n if ((a1 & 3) == 0) return v3;\n }\n v13 = v12;\n v14 = a2 * (v12 + 1);\n v3->m128i_i32[v13] = v14;\n if (v12 + 1 < a1) {\n v15 = a2 + v14;\n v3->m128i_i32[v13 + 1] = v15;\n if (a1 > v12 + 2) v3->m128i_i32[v13 + 2] = v15 + a2;\n }\n }\n return v3;\n}", + "ida_pseudo_norm": "__m128i *func0(int a1, unsigned int a2, int *a3) {\n __m128i *v3;\n __m128i si128;\n __m128i v5;\n __m128i v6;\n __m128i v7;\n __m128i *v8;\n __m128i v9;\n __m128i v10;\n __m128i v11;\n int v12;\n long long v13;\n int v14;\n unsigned int v15;\n *a3 = a1;\n v3 = (__m128i *)malloc(4LL * a1);\n if (v3 && a1 > 0) {\n if ((unsigned int)(a1 - 1) <= 2) {\n v12 = 0;\n } else {\n si128 = _mm_load_si128((const __m128i *)&xmmword_2080);\n v5 = _mm_load_si128((const __m128i *)&xmmword_2090);\n v6 = _mm_shuffle_epi32(_mm_cvtsi32_si128(a2), 0);\n v7 = _mm_load_si128((const __m128i *)&xmmword_20A0);\n v8 = v3;\n v9 = _mm_srli_epi64(v6, 32u);\n do {\n v10 = si128;\n ++v8;\n si128 = _mm_add_epi32(si128, v5);\n v11 = _mm_add_epi32(v10, v7);\n v8[-1] = _mm_unpacklo_epi32(\n _mm_shuffle_epi32(_mm_mul_epu32(v11, v6), 8),\n _mm_shuffle_epi32(_mm_mul_epu32(_mm_srli_epi64(v11, 32u), v9), 8));\n } while (v8 != &v3[(unsigned int)a1 >> 2]);\n v12 = a1 & 2147483644;\n if ((a1 & 3) == 0) return v3;\n }\n v13 = v12;\n v14 = a2 * (v12 + 1);\n v3->m128i_i32[v13] = v14;\n if (v12 + 1 < a1) {\n v15 = a2 + v14;\n v3->m128i_i32[v13 + 1] = v15;\n if (a1 > v12 + 2) v3->m128i_i32[v13 + 2] = v15 + a2;\n }\n }\n return v3;\n}" + }, + { + "index": 22, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int nums[], int length) {\n bool exists[1001] = {false};\n int no_duplicate = -1;\n for (int i = 0; i < length; i++) {\n if (exists[nums[i]]) {\n return nums[i];\n } else {\n exists[nums[i]] = true;\n }\n }\n return no_duplicate;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4, 4, 5};\n\n int arr2[] = {1, 2, 3, 4};\n\n int arr3[] = {1, 1, 2, 3, 3, 2, 2};\n\n\n\n assert(func0(arr1, 6) == 4);\n\n assert(func0(arr2, 4) == -1);\n\n assert(func0(arr3, 7) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x420,%rsp\nmov %rdi,-0x418(%rbp)\nmov %esi,-0x41c(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea -0x400(%rbp),%rdx\nmov $0x0,%eax\nmov $0x7d,%ecx\nmov %rdx,%rdi\nrep stos %rax,%es:(%rdi)\nmov %rdi,%rdx\nmov %al,(%rdx)\nadd $0x1,%rdx\nmovl $0xffffffff,-0x404(%rbp)\nmovl $0x0,-0x408(%rbp)\njmp 123f \nmov -0x408(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x418(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncltq\nmovzbl -0x400(%rbp,%rax,1),%eax\ntest %al,%al\nje 1212 \nmov -0x408(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x418(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\njmp 1257 \nmov -0x408(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x418(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncltq\nmovb $0x1,-0x400(%rbp,%rax,1)\naddl $0x1,-0x408(%rbp)\nmov -0x408(%rbp),%eax\ncmp -0x41c(%rbp),%eax\njl 11ca \nmov -0x404(%rbp),%eax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 126b \ncallq 1060 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 420h\nmov [rbp+var_418], rdi\nmov [rbp+var_41C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rdx, [rbp+var_400]\nmov eax, 0\nmov ecx, 7Dh ; '}'\nmov rdi, rdx\nrep stosq\nmov rdx, rdi\nmov [rdx], al\nadd rdx, 1\nmov [rbp+var_404], 0FFFFFFFFh\nmov [rbp+var_408], 0\njmp short loc_123F\nloc_11CA:\nmov eax, [rbp+var_408]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_418]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nmovzx eax, [rbp+rax+var_400]\ntest al, al\njz short loc_1212\nmov eax, [rbp+var_408]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_418]\nadd rax, rdx\nmov eax, [rax]\njmp short loc_1257\nloc_1212:\nmov eax, [rbp+var_408]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_418]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nmov [rbp+rax+var_400], 1\nadd [rbp+var_408], 1\nloc_123F:\nmov eax, [rbp+var_408]\ncmp eax, [rbp+var_41C]\njl loc_11CA\nmov eax, [rbp+var_404]\nloc_1257:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_126B\ncall ___stack_chk_fail\nlocret_126B:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-408h]\n _BYTE v4[1016]; // [rsp+20h] [rbp-400h] BYREF\n unsigned __int64 v5; // [rsp+418h] [rbp-8h]\n\n v5 = __readfsqword(0x28u);\n memset(v4, 0, 1001);\n for ( i = 0; i < a2; ++i )\n {\n if ( v4[*(int *)(4LL * i + a1)] )\n return *(unsigned int *)(4LL * i + a1);\n v4[*(int *)(4LL * i + a1)] = 1;\n }\n return 0xFFFFFFFFLL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 420h\nmov [rbp+var_418], rdi\nmov [rbp+var_41C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rdx, [rbp+var_400]\nmov eax, 0\nmov ecx, 7Dh ; '}'\nmov rdi, rdx\nrep stosq\nmov rdx, rdi\nmov [rdx], al\nadd rdx, 1\nmov [rbp+var_404], 0FFFFFFFFh\nmov [rbp+var_408], 0\njmp short loc_123F\nloc_11CA:\nmov eax, [rbp+var_408]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_418]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nmovzx eax, [rbp+rax+var_400]\ntest al, al\njz short loc_1212\nmov eax, [rbp+var_408]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_418]\nadd rax, rdx\nmov eax, [rax]\njmp short loc_1257\nloc_1212:\nmov eax, [rbp+var_408]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_418]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nmov [rbp+rax+var_400], 1\nadd [rbp+var_408], 1\nloc_123F:\nmov eax, [rbp+var_408]\ncmp eax, [rbp+var_41C]\njl loc_11CA\nmov eax, [rbp+var_404]\nloc_1257:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_126B\ncall ___stack_chk_fail\nlocret_126B:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-408h]\n _BYTE v4[1016]; // [rsp+20h] [rbp-400h] BYREF\n unsigned __int64 v5; // [rsp+418h] [rbp-8h]\n\n v5 = __readfsqword(0x28u);\n memset(v4, 0, 1001);\n for ( i = 0; i < a2; ++i )\n {\n if ( v4[*(int *)(4LL * i + a1)] )\n return *(unsigned int *)(4LL * i + a1);\n v4[*(int *)(4LL * i + a1)] = 1;\n }\n return 0xFFFFFFFFLL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int i;\n uint8_t v4[1016];\n unsigned long long v5;\n v5 = __readfsqword(40u);\n memset(v4, 0, 1001);\n for (i = 0; i < a2; ++i) {\n if (v4[*(int *)(4LL * i + a1)]) return *(unsigned int *)(4LL * i + a1);\n v4[*(int *)(4LL * i + a1)] = 1;\n }\n return 4294967295LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int i;\n uint8_t v4[1016];\n unsigned long long v5;\n v5 = __readfsqword(40u);\n memset(v4, 0, 1001);\n for (i = 0; i < a2; ++i) {\n if (v4[*(int *)(4LL * i + a1)]) return *(unsigned int *)(4LL * i + a1);\n v4[*(int *)(4LL * i + a1)] = 1;\n }\n return 4294967295LL;\n}" + }, + { + "index": 22, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int nums[], int length) {\n bool exists[1001] = {false};\n int no_duplicate = -1;\n for (int i = 0; i < length; i++) {\n if (exists[nums[i]]) {\n return nums[i];\n } else {\n exists[nums[i]] = true;\n }\n }\n return no_duplicate;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4, 4, 5};\n\n int arr2[] = {1, 2, 3, 4};\n\n int arr3[] = {1, 1, 2, 3, 3, 2, 2};\n\n\n\n assert(func0(arr1, 6) == 4);\n\n assert(func0(arr2, 4) == -1);\n\n assert(func0(arr3, 7) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x408,%rsp\nmov %rdi,%r8\nmov %fs:0x28,%rax\nmov %rax,0x3f8(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nmov $0x7d,%ecx\nrep stos %rax,%es:(%rdi)\nmovb $0x0,(%rdi)\ntest %esi,%esi\njle 11df \nmov %r8,%rdx\nlea -0x1(%rsi),%eax\nlea 0x4(%r8,%rax,4),%rsi\nmov (%rdx),%eax\nmovslq %eax,%rcx\ncmpb $0x0,(%rsp,%rcx,1)\njne 11c4 \nmovb $0x1,(%rsp,%rcx,1)\nadd $0x4,%rdx\ncmp %rsi,%rdx\njne 11a7 \nmov $0xffffffff,%eax\nmov 0x3f8(%rsp),%rdi\nxor %fs:0x28,%rdi\njne 11e6 \nadd $0x408,%rsp\nretq\nmov $0xffffffff,%eax\njmp 11c4 \ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 408h\nmov r8, rdi\nmov rax, fs:28h\nmov [rsp+408h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nmov ecx, 7Dh ; '}'\nrep stosq\nmov byte ptr [rdi], 0\ntest esi, esi\njle short loc_11DE\nmov rdx, r8\nmovsxd rsi, esi\nlea rsi, [r8+rsi*4]\nloc_11A6:\nmov eax, [rdx]\nmovsxd rcx, eax\ncmp [rsp+rcx+408h+var_408], 0\njnz short loc_11C3\nmov [rsp+rcx+408h+var_408], 1\nadd rdx, 4\ncmp rdx, rsi\njnz short loc_11A6\nmov eax, 0FFFFFFFFh\nloc_11C3:\nmov rdx, [rsp+408h+var_10]\nsub rdx, fs:28h\njnz short loc_11E5\nadd rsp, 408h\nretn\nloc_11DE:\nmov eax, 0FFFFFFFFh\njmp short loc_11C3\nloc_11E5:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n unsigned int *v2; // rdx\n unsigned int *v3; // rsi\n __int64 result; // rax\n _BYTE v5[1016]; // [rsp+0h] [rbp-408h] BYREF\n unsigned __int64 v6; // [rsp+3F8h] [rbp-10h]\n\n v6 = __readfsqword(0x28u);\n memset(v5, 0, 1001);\n if ( a2 <= 0 )\n return 0xFFFFFFFFLL;\n v2 = a1;\n v3 = &a1[a2];\n while ( 1 )\n {\n result = *v2;\n if ( v5[(int)result] )\n break;\n v5[(int)result] = 1;\n if ( ++v2 == v3 )\n return 0xFFFFFFFFLL;\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nsub rsp, 408h\nmov r8, rdi\nmov rax, fs:28h\nmov [rsp+408h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nmov ecx, 7Dh ; '}'\nrep stosq\nmov byte ptr [rdi], 0\ntest esi, esi\njle short loc_11DE\nmov rdx, r8\nmovsxd rsi, esi\nlea rsi, [r8+rsi*4]\nloc_11A6:\nmov eax, [rdx]\nmovsxd rcx, eax\ncmp [rsp+rcx+408h+var_408], 0\njnz short loc_11C3\nmov [rsp+rcx+408h+var_408], 1\nadd rdx, 4\ncmp rdx, rsi\njnz short loc_11A6\nmov eax, 0FFFFFFFFh\nloc_11C3:\nmov rdx, [rsp+408h+var_10]\nsub rdx, fs:28h\njnz short loc_11E5\nadd rsp, 408h\nretn\nloc_11DE:\nmov eax, 0FFFFFFFFh\njmp short loc_11C3\nloc_11E5:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(unsigned int *a1, int a2)\n{\n unsigned int *v2; // rdx\n unsigned int *v3; // rsi\n __int64 result; // rax\n _BYTE v5[1016]; // [rsp+0h] [rbp-408h] BYREF\n unsigned __int64 v6; // [rsp+3F8h] [rbp-10h]\n\n v6 = __readfsqword(0x28u);\n memset(v5, 0, 1001);\n if ( a2 <= 0 )\n return 0xFFFFFFFFLL;\n v2 = a1;\n v3 = &a1[a2];\n while ( 1 )\n {\n result = *v2;\n if ( v5[(int)result] )\n break;\n v5[(int)result] = 1;\n if ( ++v2 == v3 )\n return 0xFFFFFFFFLL;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(unsigned int *a1, int a2) {\n unsigned int *v2;\n unsigned int *v3;\n long long result;\n uint8_t v5[1016];\n unsigned long long v6;\n v6 = __readfsqword(40u);\n memset(v5, 0, 1001);\n if (a2 <= 0) return 4294967295LL;\n v2 = a1;\n v3 = &a1[a2];\n while (1) {\n result = *v2;\n if (v5[(int)result]) break;\n v5[(int)result] = 1;\n if (++v2 == v3) return 4294967295LL;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n unsigned int *v2;\n unsigned int *v3;\n long long result;\n uint8_t v5[1016];\n unsigned long long v6;\n v6 = __readfsqword(40u);\n memset(v5, 0, 1001);\n if (a2 <= 0) return 4294967295LL;\n v2 = a1;\n v3 = &a1[a2];\n while (1) {\n result = *v2;\n if (v5[(int)result]) break;\n v5[(int)result] = 1;\n if (++v2 == v3) return 4294967295LL;\n }\n return result;\n}" + }, + { + "index": 22, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int nums[], int length) {\n bool exists[1001] = {false};\n int no_duplicate = -1;\n for (int i = 0; i < length; i++) {\n if (exists[nums[i]]) {\n return nums[i];\n } else {\n exists[nums[i]] = true;\n }\n }\n return no_duplicate;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4, 4, 5};\n\n int arr2[] = {1, 2, 3, 4};\n\n int arr3[] = {1, 1, 2, 3, 3, 2, 2};\n\n\n\n assert(func0(arr1, 6) == 4);\n\n assert(func0(arr2, 4) == -1);\n\n assert(func0(arr3, 7) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x408,%rsp\nmov %rdi,%rdx\nmov $0x7d,%ecx\nmov %fs:0x28,%rax\nmov %rax,0x3f8(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nrep stos %rax,%es:(%rdi)\nmovb $0x0,(%rdi)\ntest %esi,%esi\njle 1330 \nlea -0x1(%rsi),%eax\nmov %rdx,%rdi\nlea 0x4(%rdx,%rax,4),%rdx\njmp 12fd \nadd $0x4,%rdi\nmovb $0x1,(%rsp,%rax,1)\ncmp %rdx,%rdi\nje 1330 \nmovslq (%rdi),%rax\ncmpb $0x0,(%rsp,%rax,1)\nmov %rax,%r8\nje 12f0 \nmov 0x3f8(%rsp),%rax\nxor %fs:0x28,%rax\njne 1338 \nmov %r8d,%eax\nadd $0x408,%rsp\nretq\nnopw 0x0(%rax,%rax,1)\nmov $0xffffffff,%r8d\njmp 1309 \ncallq 1060 <__stack_chk_fail@plt>\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 408h\nmov rdx, rdi\nmov ecx, 7Dh ; '}'\nmov rax, fs:28h\nmov [rsp+408h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\nmov byte ptr [rdi], 0\ntest esi, esi\njle short loc_1300\nmovsxd rsi, esi\nmov rdi, rdx\nlea rcx, [rdx+rsi*4]\njmp short loc_12CD\nloc_12C0:\nadd rdi, 4\nmov [rsp+rax+408h+var_408], 1\ncmp rdi, rcx\njz short loc_1300\nloc_12CD:\nmovsxd rax, dword ptr [rdi]\ncmp [rsp+rax+408h+var_408], 0\nmov rdx, rax\njz short loc_12C0\nloc_12D9:\nmov rax, [rsp+408h+var_10]\nsub rax, fs:28h\njnz short loc_1307\nmov eax, edx\nadd rsp, 408h\nretn\nloc_1300:\nmov edx, 0FFFFFFFFh\njmp short loc_12D9\nloc_1307:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int *v2; // rcx\n __int64 v3; // rax\n unsigned int v4; // edx\n _BYTE v6[1016]; // [rsp+0h] [rbp-408h] BYREF\n unsigned __int64 v7; // [rsp+3F8h] [rbp-10h]\n\n v7 = __readfsqword(0x28u);\n memset(v6, 0, 1001);\n if ( a2 <= 0 )\n {\n return (unsigned int)-1;\n }\n else\n {\n v2 = &a1[a2];\n while ( 1 )\n {\n v3 = *a1;\n v4 = *a1;\n if ( v6[v3] )\n break;\n ++a1;\n v6[v3] = 1;\n if ( a1 == v2 )\n return (unsigned int)-1;\n }\n }\n return v4;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\nsub rsp, 408h\nmov rdx, rdi\nmov ecx, 7Dh ; '}'\nmov rax, fs:28h\nmov [rsp+408h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\nmov byte ptr [rdi], 0\ntest esi, esi\njle short loc_1300\nmovsxd rsi, esi\nmov rdi, rdx\nlea rcx, [rdx+rsi*4]\njmp short loc_12CD\nloc_12C0:\nadd rdi, 4\nmov [rsp+rax+408h+var_408], 1\ncmp rdi, rcx\njz short loc_1300\nloc_12CD:\nmovsxd rax, dword ptr [rdi]\ncmp [rsp+rax+408h+var_408], 0\nmov rdx, rax\njz short loc_12C0\nloc_12D9:\nmov rax, [rsp+408h+var_10]\nsub rax, fs:28h\njnz short loc_1307\nmov eax, edx\nadd rsp, 408h\nretn\nloc_1300:\nmov edx, 0FFFFFFFFh\njmp short loc_12D9\nloc_1307:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1280(int *a1, int a2)\n{\n int *v2; // rcx\n __int64 v3; // rax\n unsigned int v4; // edx\n _BYTE v6[1016]; // [rsp+0h] [rbp-408h] BYREF\n unsigned __int64 v7; // [rsp+3F8h] [rbp-10h]\n\n v7 = __readfsqword(0x28u);\n memset(v6, 0, 1001);\n if ( a2 <= 0 )\n {\n return (unsigned int)-1;\n }\n else\n {\n v2 = &a1[a2];\n while ( 1 )\n {\n v3 = *a1;\n v4 = *a1;\n if ( v6[v3] )\n break;\n ++a1;\n v6[v3] = 1;\n if ( a1 == v2 )\n return (unsigned int)-1;\n }\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1280(int *a1, int a2) {\n int *v2;\n long long v3;\n unsigned int v4;\n uint8_t v6[1016];\n unsigned long long v7;\n v7 = __readfsqword(40u);\n memset(v6, 0, 1001);\n if (a2 <= 0) {\n return (unsigned int)-1;\n } else {\n v2 = &a1[a2];\n while (1) {\n v3 = *a1;\n v4 = *a1;\n if (v6[v3]) break;\n ++a1;\n v6[v3] = 1;\n if (a1 == v2) return (unsigned int)-1;\n }\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int *v2;\n long long v3;\n unsigned int v4;\n uint8_t v6[1016];\n unsigned long long v7;\n v7 = __readfsqword(40u);\n memset(v6, 0, 1001);\n if (a2 <= 0) {\n return (unsigned int)-1;\n } else {\n v2 = &a1[a2];\n while (1) {\n v3 = *a1;\n v4 = *a1;\n if (v6[v3]) break;\n ++a1;\n v6[v3] = 1;\n if (a1 == v2) return (unsigned int)-1;\n }\n }\n return v4;\n}" + }, + { + "index": 22, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int nums[], int length) {\n bool exists[1001] = {false};\n int no_duplicate = -1;\n for (int i = 0; i < length; i++) {\n if (exists[nums[i]]) {\n return nums[i];\n } else {\n exists[nums[i]] = true;\n }\n }\n return no_duplicate;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4, 4, 5};\n\n int arr2[] = {1, 2, 3, 4};\n\n int arr3[] = {1, 1, 2, 3, 3, 2, 2};\n\n\n\n assert(func0(arr1, 6) == 4);\n\n assert(func0(arr2, 4) == -1);\n\n assert(func0(arr3, 7) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x408,%rsp\nmov %rdi,%rdx\nmov $0x7d,%ecx\nmov %fs:0x28,%rax\nmov %rax,0x3f8(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nrep stos %rax,%es:(%rdi)\nmovb $0x0,(%rdi)\ntest %esi,%esi\njle 1300 \nlea -0x1(%rsi),%eax\nmov %rdx,%rdi\nlea 0x4(%rdx,%rax,4),%rdx\njmp 12cd \nadd $0x4,%rdi\nmovb $0x1,(%rsp,%rax,1)\ncmp %rdx,%rdi\nje 1300 \nmovslq (%rdi),%rax\ncmpb $0x0,(%rsp,%rax,1)\nmov %rax,%r8\nje 12c0 \nmov 0x3f8(%rsp),%rax\nxor %fs:0x28,%rax\njne 1308 \nmov %r8d,%eax\nadd $0x408,%rsp\nretq\nnopw 0x0(%rax,%rax,1)\nmov $0xffffffff,%r8d\njmp 12d9 \ncallq 1060 <__stack_chk_fail@plt>\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 408h\nmov rdx, rdi\nmov ecx, 7Dh ; '}'\nmov rax, fs:28h\nmov [rsp+408h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\nmov byte ptr [rdi], 0\ntest esi, esi\njle short loc_1300\nmovsxd rsi, esi\nmov rdi, rdx\nlea rcx, [rdx+rsi*4]\njmp short loc_12CD\nloc_12C0:\nadd rdi, 4\nmov [rsp+rax+408h+var_408], 1\ncmp rdi, rcx\njz short loc_1300\nloc_12CD:\nmovsxd rax, dword ptr [rdi]\ncmp [rsp+rax+408h+var_408], 0\nmov rdx, rax\njz short loc_12C0\nloc_12D9:\nmov rax, [rsp+408h+var_10]\nsub rax, fs:28h\njnz short loc_1307\nmov eax, edx\nadd rsp, 408h\nretn\nloc_1300:\nmov edx, 0FFFFFFFFh\njmp short loc_12D9\nloc_1307:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int *v2; // rcx\n __int64 v3; // rax\n unsigned int v4; // edx\n _BYTE v6[1016]; // [rsp+0h] [rbp-408h] BYREF\n unsigned __int64 v7; // [rsp+3F8h] [rbp-10h]\n\n v7 = __readfsqword(0x28u);\n memset(v6, 0, 1001);\n if ( a2 <= 0 )\n {\n return (unsigned int)-1;\n }\n else\n {\n v2 = &a1[a2];\n while ( 1 )\n {\n v3 = *a1;\n v4 = *a1;\n if ( v6[v3] )\n break;\n ++a1;\n v6[v3] = 1;\n if ( a1 == v2 )\n return (unsigned int)-1;\n }\n }\n return v4;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\nsub rsp, 408h\nmov rdx, rdi\nmov ecx, 7Dh ; '}'\nmov rax, fs:28h\nmov [rsp+408h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\nmov byte ptr [rdi], 0\ntest esi, esi\njle short loc_1300\nmovsxd rsi, esi\nmov rdi, rdx\nlea rcx, [rdx+rsi*4]\njmp short loc_12CD\nloc_12C0:\nadd rdi, 4\nmov [rsp+rax+408h+var_408], 1\ncmp rdi, rcx\njz short loc_1300\nloc_12CD:\nmovsxd rax, dword ptr [rdi]\ncmp [rsp+rax+408h+var_408], 0\nmov rdx, rax\njz short loc_12C0\nloc_12D9:\nmov rax, [rsp+408h+var_10]\nsub rax, fs:28h\njnz short loc_1307\nmov eax, edx\nadd rsp, 408h\nretn\nloc_1300:\nmov edx, 0FFFFFFFFh\njmp short loc_12D9\nloc_1307:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1280(int *a1, int a2)\n{\n int *v2; // rcx\n __int64 v3; // rax\n unsigned int v4; // edx\n _BYTE v6[1016]; // [rsp+0h] [rbp-408h] BYREF\n unsigned __int64 v7; // [rsp+3F8h] [rbp-10h]\n\n v7 = __readfsqword(0x28u);\n memset(v6, 0, 1001);\n if ( a2 <= 0 )\n {\n return (unsigned int)-1;\n }\n else\n {\n v2 = &a1[a2];\n while ( 1 )\n {\n v3 = *a1;\n v4 = *a1;\n if ( v6[v3] )\n break;\n ++a1;\n v6[v3] = 1;\n if ( a1 == v2 )\n return (unsigned int)-1;\n }\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1280(int *a1, int a2) {\n int *v2;\n long long v3;\n unsigned int v4;\n uint8_t v6[1016];\n unsigned long long v7;\n v7 = __readfsqword(40u);\n memset(v6, 0, 1001);\n if (a2 <= 0) {\n return (unsigned int)-1;\n } else {\n v2 = &a1[a2];\n while (1) {\n v3 = *a1;\n v4 = *a1;\n if (v6[v3]) break;\n ++a1;\n v6[v3] = 1;\n if (a1 == v2) return (unsigned int)-1;\n }\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int *v2;\n long long v3;\n unsigned int v4;\n uint8_t v6[1016];\n unsigned long long v7;\n v7 = __readfsqword(40u);\n memset(v6, 0, 1001);\n if (a2 <= 0) {\n return (unsigned int)-1;\n } else {\n v2 = &a1[a2];\n while (1) {\n v3 = *a1;\n v4 = *a1;\n if (v6[v3]) break;\n ++a1;\n v6[v3] = 1;\n if (a1 == v2) return (unsigned int)-1;\n }\n }\n return v4;\n}" + }, + { + "index": 23, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(int list1[][3], size_t rows) {\n int maxi = -100000;\n for (size_t i = 0; i < rows; i++) {\n int sum = 0;\n for (size_t j = 0; j < 3; j++) {\n sum += list1[i][j];\n }\n if (sum > maxi) {\n maxi = sum;\n }\n }\n return maxi;\n}", + "test": "int main() {\n\n int data1[][3] = {{1, 2, 3}, {4, 5, 6}, {10, 11, 12}, {7, 8, 9}};\n\n assert(func0(data1, 4) == 33);\n\n\n\n int data2[][3] = {{0, 1, 1}, {1, 1, 2}, {3, 2, 1}};\n\n assert(func0(data2, 3) == 6);\n\n\n\n int data3[][3] = {{0, 1, 3}, {1, 2, 1}, {9, 8, 2}, {0, 1, 0}, {6, 4, 8}};\n\n assert(func0(data3, 5) == 19);\n\n\n\n int data4[][3] = {{0, -1, -1}, {-1, -1, -2}, {-3, -2, -1}};\n\n assert(func0(data4, 3) == -2);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x28(%rbp)\nmov %rsi,-0x30(%rbp)\nmovl $0xfffe7960,-0x18(%rbp)\nmovq $0x0,-0x10(%rbp)\njmp 11df \nmovl $0x0,-0x14(%rbp)\nmovq $0x0,-0x8(%rbp)\njmp 11c5 \nmov -0x10(%rbp),%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x28(%rbp),%rax\nadd %rax,%rdx\nmov -0x8(%rbp),%rax\nmov (%rdx,%rax,4),%eax\nadd %eax,-0x14(%rbp)\naddq $0x1,-0x8(%rbp)\ncmpq $0x2,-0x8(%rbp)\njbe 119b \nmov -0x14(%rbp),%eax\ncmp -0x18(%rbp),%eax\njle 11da \nmov -0x14(%rbp),%eax\nmov %eax,-0x18(%rbp)\naddq $0x1,-0x10(%rbp)\nmov -0x10(%rbp),%rax\ncmp -0x30(%rbp),%rax\njb 118a \nmov -0x18(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_30], rsi\nmov [rbp+var_18], 0FFFE7960h\nmov [rbp+var_10], 0\njmp short loc_11DF\nloc_118A:\nmov [rbp+var_14], 0\nmov [rbp+var_8], 0\njmp short loc_11C5\nloc_119B:\nmov rdx, [rbp+var_10]\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov rax, [rbp+var_8]\nmov eax, [rdx+rax*4]\nadd [rbp+var_14], eax\nadd [rbp+var_8], 1\nloc_11C5:\ncmp [rbp+var_8], 2\njbe short loc_119B\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_18]\njle short loc_11DA\nmov eax, [rbp+var_14]\nmov [rbp+var_18], eax\nloc_11DA:\nadd [rbp+var_10], 1\nloc_11DF:\nmov rax, [rbp+var_10]\ncmp rax, [rbp+var_30]\njb short loc_118A\nmov eax, [rbp+var_18]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, unsigned __int64 a2)\n{\n int v3; // [rsp+18h] [rbp-18h]\n int v4; // [rsp+1Ch] [rbp-14h]\n unsigned __int64 i; // [rsp+20h] [rbp-10h]\n unsigned __int64 j; // [rsp+28h] [rbp-8h]\n\n v3 = -100000;\n for ( i = 0LL; i < a2; ++i )\n {\n v4 = 0;\n for ( j = 0LL; j <= 2; ++j )\n v4 += *(_DWORD *)(a1 + 12 * i + 4 * j);\n if ( v4 > v3 )\n v3 = v4;\n }\n return (unsigned int)v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_30], rsi\nmov [rbp+var_18], 0FFFE7960h\nmov [rbp+var_10], 0\njmp short loc_11DF\nloc_118A:\nmov [rbp+var_14], 0\nmov [rbp+var_8], 0\njmp short loc_11C5\nloc_119B:\nmov rdx, [rbp+var_10]\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov rax, [rbp+var_8]\nmov eax, [rdx+rax*4]\nadd [rbp+var_14], eax\nadd [rbp+var_8], 1\nloc_11C5:\ncmp [rbp+var_8], 2\njbe short loc_119B\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_18]\njle short loc_11DA\nmov eax, [rbp+var_14]\nmov [rbp+var_18], eax\nloc_11DA:\nadd [rbp+var_10], 1\nloc_11DF:\nmov rax, [rbp+var_10]\ncmp rax, [rbp+var_30]\njb short loc_118A\nmov eax, [rbp+var_18]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, unsigned __int64 a2)\n{\n int v3; // [rsp+18h] [rbp-18h]\n int v4; // [rsp+1Ch] [rbp-14h]\n unsigned __int64 i; // [rsp+20h] [rbp-10h]\n unsigned __int64 j; // [rsp+28h] [rbp-8h]\n\n v3 = -100000;\n for ( i = 0LL; i < a2; ++i )\n {\n v4 = 0;\n for ( j = 0LL; j <= 2; ++j )\n v4 += *(_DWORD *)(a1 + 12 * i + 4 * j);\n if ( v4 > v3 )\n v3 = v4;\n }\n return (unsigned int)v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, unsigned long long a2) {\n int v3;\n int v4;\n unsigned long long i;\n unsigned long long j;\n v3 = -100000;\n for (i = 0LL; i < a2; ++i) {\n v4 = 0;\n for (j = 0LL; j <= 2; ++j) v4 += *(uint32_t *)(a1 + 12 * i + 4 * j);\n if (v4 > v3) v3 = v4;\n }\n return (unsigned int)v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, unsigned long long a2) {\n int v3;\n int v4;\n unsigned long long i;\n unsigned long long j;\n v3 = -100000;\n for (i = 0LL; i < a2; ++i) {\n v4 = 0;\n for (j = 0LL; j <= 2; ++j) v4 += *(uint32_t *)(a1 + 12 * i + 4 * j);\n if (v4 > v3) v3 = v4;\n }\n return (unsigned int)v3;\n}" + }, + { + "index": 23, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(int list1[][3], size_t rows) {\n int maxi = -100000;\n for (size_t i = 0; i < rows; i++) {\n int sum = 0;\n for (size_t j = 0; j < 3; j++) {\n sum += list1[i][j];\n }\n if (sum > maxi) {\n maxi = sum;\n }\n }\n return maxi;\n}", + "test": "int main() {\n\n int data1[][3] = {{1, 2, 3}, {4, 5, 6}, {10, 11, 12}, {7, 8, 9}};\n\n assert(func0(data1, 4) == 33);\n\n\n\n int data2[][3] = {{0, 1, 1}, {1, 1, 2}, {3, 2, 1}};\n\n assert(func0(data2, 3) == 6);\n\n\n\n int data3[][3] = {{0, 1, 3}, {1, 2, 1}, {9, 8, 2}, {0, 1, 0}, {6, 4, 8}};\n\n assert(func0(data3, 5) == 19);\n\n\n\n int data4[][3] = {{0, -1, -1}, {-1, -1, -2}, {-3, -2, -1}};\n\n assert(func0(data4, 3) == -2);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %rsi,%rsi\nje 119b \nmov %rdi,%rdx\nlea (%rsi,%rsi,2),%rax\nlea (%rdi,%rax,4),%rsi\nmov $0xfffe7960,%ecx\nmov 0x4(%rdx),%eax\nadd (%rdx),%eax\nadd 0x8(%rdx),%eax\ncmp %eax,%ecx\ncmovl %eax,%ecx\nadd $0xc,%rdx\ncmp %rsi,%rdx\njne 1182 \nmov %ecx,%eax\nretq\nmov $0xfffe7960,%ecx\njmp 1198 \n", + "ida_asm": "func0:\nendbr64\ntest rsi, rsi\njz short loc_119B\nmov rdx, rdi\nlea rax, [rsi+rsi*2]\nlea rsi, [rdi+rax*4]\nmov ecx, 0FFFE7960h\nloc_1182:\nmov eax, [rdx+4]\nadd eax, [rdx]\nadd eax, [rdx+8]\ncmp ecx, eax\ncmovl ecx, eax\nadd rdx, 0Ch\ncmp rdx, rsi\njnz short loc_1182\nloc_1198:\nmov eax, ecx\nretn\nloc_119B:\nmov ecx, 0FFFE7960h\njmp short loc_1198", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, __int64 a2)\n{\n _DWORD *v2; // rdx\n _DWORD *v3; // rsi\n int v4; // ecx\n\n if ( a2 )\n {\n v2 = a1;\n v3 = &a1[3 * a2];\n v4 = -100000;\n do\n {\n if ( v4 < v2[2] + *v2 + v2[1] )\n v4 = v2[2] + *v2 + v2[1];\n v2 += 3;\n }\n while ( v2 != v3 );\n }\n else\n {\n return (unsigned int)-100000;\n }\n return (unsigned int)v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest rsi, rsi\njz short loc_119B\nmov rdx, rdi\nlea rax, [rsi+rsi*2]\nlea rsi, [rdi+rax*4]\nmov ecx, 0FFFE7960h\nloc_1182:\nmov eax, [rdx+4]\nadd eax, [rdx]\nadd eax, [rdx+8]\ncmp ecx, eax\ncmovl ecx, eax\nadd rdx, 0Ch\ncmp rdx, rsi\njnz short loc_1182\nloc_1198:\nmov eax, ecx\nretn\nloc_119B:\nmov ecx, 0FFFE7960h\njmp short loc_1198", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, __int64 a2)\n{\n _DWORD *v2; // rdx\n _DWORD *v3; // rsi\n int v4; // ecx\n\n if ( a2 )\n {\n v2 = a1;\n v3 = &a1[3 * a2];\n v4 = -100000;\n do\n {\n if ( v4 < v2[2] + *v2 + v2[1] )\n v4 = v2[2] + *v2 + v2[1];\n v2 += 3;\n }\n while ( v2 != v3 );\n }\n else\n {\n return (unsigned int)-100000;\n }\n return (unsigned int)v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, long long a2) {\n uint32_t *v2;\n uint32_t *v3;\n int v4;\n if (a2) {\n v2 = a1;\n v3 = &a1[3 * a2];\n v4 = -100000;\n do {\n if (v4 < v2[2] + *v2 + v2[1]) v4 = v2[2] + *v2 + v2[1];\n v2 += 3;\n } while (v2 != v3);\n } else {\n return (unsigned int)-100000;\n }\n return (unsigned int)v4;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, long long a2) {\n uint32_t *v2;\n uint32_t *v3;\n int v4;\n if (a2) {\n v2 = a1;\n v3 = &a1[3 * a2];\n v4 = -100000;\n do {\n if (v4 < v2[2] + *v2 + v2[1]) v4 = v2[2] + *v2 + v2[1];\n v2 += 3;\n } while (v2 != v3);\n } else {\n return (unsigned int)-100000;\n }\n return (unsigned int)v4;\n}" + }, + { + "index": 23, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(int list1[][3], size_t rows) {\n int maxi = -100000;\n for (size_t i = 0; i < rows; i++) {\n int sum = 0;\n for (size_t j = 0; j < 3; j++) {\n sum += list1[i][j];\n }\n if (sum > maxi) {\n maxi = sum;\n }\n }\n return maxi;\n}", + "test": "int main() {\n\n int data1[][3] = {{1, 2, 3}, {4, 5, 6}, {10, 11, 12}, {7, 8, 9}};\n\n assert(func0(data1, 4) == 33);\n\n\n\n int data2[][3] = {{0, 1, 1}, {1, 1, 2}, {3, 2, 1}};\n\n assert(func0(data2, 3) == 6);\n\n\n\n int data3[][3] = {{0, 1, 3}, {1, 2, 1}, {9, 8, 2}, {0, 1, 0}, {6, 4, 8}};\n\n assert(func0(data3, 5) == 19);\n\n\n\n int data4[][3] = {{0, -1, -1}, {-1, -1, -2}, {-3, -2, -1}};\n\n assert(func0(data4, 3) == -2);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %rsi,%rsi\nje 133c \nlea (%rsi,%rsi,2),%rax\nmov $0xfffe7960,%r8d\nlea (%rdi,%rax,4),%rdx\nnopw 0x0(%rax,%rax,1)\nmov 0x4(%rdi),%eax\nadd (%rdi),%eax\nadd 0x8(%rdi),%eax\ncmp %eax,%r8d\ncmovl %eax,%r8d\nadd $0xc,%rdi\ncmp %rdx,%rdi\njne 1320 \nmov %r8d,%eax\nretq\nmov $0xfffe7960,%r8d\nmov %r8d,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest rsi, rsi\njz short loc_1379\nlea rax, [rsi+rsi*2]\nmov edx, 0FFFE7960h\nlea rcx, [rdi+rax*4]\nnop word ptr [rax+rax+00000000h]\nloc_1360:\nmov eax, [rdi+4]\nadd eax, [rdi]\nadd eax, [rdi+8]\ncmp edx, eax\ncmovl edx, eax\nadd rdi, 0Ch\ncmp rdi, rcx\njnz short loc_1360\nmov eax, edx\nretn\nloc_1379:\nmov edx, 0FFFE7960h\nmov eax, edx\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, __int64 a2)\n{\n int v2; // edx\n _DWORD *v3; // rcx\n\n if ( !a2 )\n return 4294867296LL;\n v2 = -100000;\n v3 = &a1[3 * a2];\n do\n {\n if ( v2 < a1[2] + *a1 + a1[1] )\n v2 = a1[2] + *a1 + a1[1];\n a1 += 3;\n }\n while ( a1 != v3 );\n return (unsigned int)v2;\n}", + "ida_strip_asm": "sub_1340:\nendbr64\ntest rsi, rsi\njz short loc_1379\nlea rax, [rsi+rsi*2]\nmov edx, 0FFFE7960h\nlea rcx, [rdi+rax*4]\nnop word ptr [rax+rax+00000000h]\nloc_1360:\nmov eax, [rdi+4]\nadd eax, [rdi]\nadd eax, [rdi+8]\ncmp edx, eax\ncmovl edx, eax\nadd rdi, 0Ch\ncmp rdi, rcx\njnz short loc_1360\nmov eax, edx\nretn\nloc_1379:\nmov edx, 0FFFE7960h\nmov eax, edx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1340(_DWORD *a1, __int64 a2)\n{\n int v2; // edx\n _DWORD *v3; // rcx\n\n if ( !a2 )\n return 4294867296LL;\n v2 = -100000;\n v3 = &a1[3 * a2];\n do\n {\n if ( v2 < a1[2] + *a1 + a1[1] )\n v2 = a1[2] + *a1 + a1[1];\n a1 += 3;\n }\n while ( a1 != v3 );\n return (unsigned int)v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1340(uint32_t *a1, long long a2) {\n int v2;\n uint32_t *v3;\n if (!a2) return 4294867296LL;\n v2 = -100000;\n v3 = &a1[3 * a2];\n do {\n if (v2 < a1[2] + *a1 + a1[1]) v2 = a1[2] + *a1 + a1[1];\n a1 += 3;\n } while (a1 != v3);\n return (unsigned int)v2;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, long long a2) {\n int v2;\n uint32_t *v3;\n if (!a2) return 4294867296LL;\n v2 = -100000;\n v3 = &a1[3 * a2];\n do {\n if (v2 < a1[2] + *a1 + a1[1]) v2 = a1[2] + *a1 + a1[1];\n a1 += 3;\n } while (a1 != v3);\n return (unsigned int)v2;\n}" + }, + { + "index": 24, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int binary) {\n int binary1 = binary;\n int decimal = 0;\n int i = 0;\n while (binary != 0) {\n int dec = binary % 10;\n decimal += dec * (int)pow(2, i);\n binary /= 10;\n i++;\n }\n return decimal;\n}", + "test": "int main() {\n\n assert(func0(100) == 4);\n\n assert(func0(1011) == 11);\n\n assert(func0(1101101) == 109);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %edi,-0x14(%rbp)\nmov -0x14(%rbp),%eax\nmov %eax,-0x8(%rbp)\nmovl $0x0,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 1202 \nmov -0x14(%rbp),%edx\nmovslq %edx,%rax\nimul $0x66666667,%rax,%rax\nshr $0x20,%rax\nmov %eax,%ecx\nsar $0x2,%ecx\nmov %edx,%eax\nsar $0x1f,%eax\nsub %eax,%ecx\nmov %ecx,%eax\nshl $0x2,%eax\nadd %ecx,%eax\nadd %eax,%eax\nsub %eax,%edx\nmov %edx,%eax\nmov %eax,-0x4(%rbp)\ncvtsi2sdl -0xc(%rbp),%xmm0\nmov 0xeb9(%rip),%rax\nmovapd %xmm0,%xmm1\nmovq %rax,%xmm0\ncallq 1060 \ncvttsd2si %xmm0,%eax\nimul -0x4(%rbp),%eax\nadd %eax,-0x10(%rbp)\nmov -0x14(%rbp),%eax\nmovslq %eax,%rdx\nimul $0x66666667,%rdx,%rdx\nshr $0x20,%rdx\nsar $0x2,%edx\nsar $0x1f,%eax\nsub %eax,%edx\nmov %edx,%eax\nmov %eax,-0x14(%rbp)\naddl $0x1,-0xc(%rbp)\ncmpl $0x0,-0x14(%rbp)\njne 118e \nmov -0x10(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov eax, [rbp+var_14]\nmov [rbp+var_8], eax\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp short loc_1204\nloc_118E:\nmov edx, [rbp+var_14]\nmovsxd rax, edx\nimul rax, 66666667h\nshr rax, 20h\nmov ecx, eax\nsar ecx, 2\nmov eax, edx\nsar eax, 1Fh\nsub ecx, eax\nmov eax, ecx\nshl eax, 2\nadd eax, ecx\nadd eax, eax\nsub edx, eax\nmov [rbp+var_4], edx\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_C]\nmov rax, cs:x\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\ncvttsd2si eax, xmm0\nimul eax, [rbp+var_4]\nadd [rbp+var_10], eax\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_14], eax\nadd [rbp+var_C], 1\nloc_1204:\ncmp [rbp+var_14], 0\njnz short loc_118E\nmov eax, [rbp+var_10]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v3; // [rsp+10h] [rbp-10h]\n int v4; // [rsp+14h] [rbp-Ch]\n\n v3 = 0;\n v4 = 0;\n while ( a1 )\n {\n v3 += a1 % 10 * (int)pow(2.0, (double)v4);\n a1 /= 10;\n ++v4;\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov eax, [rbp+var_14]\nmov [rbp+var_8], eax\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp short loc_1204\nloc_118E:\nmov edx, [rbp+var_14]\nmovsxd rax, edx\nimul rax, 66666667h\nshr rax, 20h\nmov ecx, eax\nsar ecx, 2\nmov eax, edx\nsar eax, 1Fh\nsub ecx, eax\nmov eax, ecx\nshl eax, 2\nadd eax, ecx\nadd eax, eax\nsub edx, eax\nmov [rbp+var_4], edx\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_C]\nmov rax, cs:x\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\ncvttsd2si eax, xmm0\nimul eax, [rbp+var_4]\nadd [rbp+var_10], eax\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_14], eax\nadd [rbp+var_C], 1\nloc_1204:\ncmp [rbp+var_14], 0\njnz short loc_118E\nmov eax, [rbp+var_10]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n unsigned int v3; // [rsp+10h] [rbp-10h]\n int v4; // [rsp+14h] [rbp-Ch]\n\n v3 = 0;\n v4 = 0;\n while ( a1 )\n {\n v3 += a1 % 10 * (int)pow(2.0, (double)v4);\n a1 /= 10;\n ++v4;\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n unsigned int v3;\n int v4;\n v3 = 0;\n v4 = 0;\n while (a1) {\n v3 += a1 % 10 * (int)pow(2.0, (double)v4);\n a1 /= 10;\n ++v4;\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v3;\n int v4;\n v3 = 0;\n v4 = 0;\n while (a1) {\n v3 += a1 % 10 * (int)pow(2.0, (double)v4);\n a1 /= 10;\n ++v4;\n }\n return v3;\n}" + }, + { + "index": 24, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int binary) {\n int binary1 = binary;\n int decimal = 0;\n int i = 0;\n while (binary != 0) {\n int dec = binary % 10;\n decimal += dec * (int)pow(2, i);\n binary /= 10;\n i++;\n }\n return decimal;\n}", + "test": "int main() {\n\n assert(func0(100) == 4);\n\n assert(func0(1011) == 11);\n\n assert(func0(1101101) == 109);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmov %edi,%ebx\ntest %edi,%edi\nje 11d2 \nmov $0x0,%ebp\nmov $0x0,%r12d\npxor %xmm1,%xmm1\ncvtsi2sd %ebp,%xmm1\nmov 0xeef(%rip),%rax\nmovq %rax,%xmm0\ncallq 1060 \ncvttsd2si %xmm0,%edx\nmovslq %ebx,%rax\nimul $0x66666667,%rax,%rax\nsar $0x22,%rax\nmov %ebx,%ecx\nsar $0x1f,%ecx\nsub %ecx,%eax\nlea (%rax,%rax,4),%ecx\nadd %ecx,%ecx\nsub %ecx,%ebx\nimul %edx,%ebx\nadd %ebx,%r12d\nmov %eax,%ebx\nadd $0x1,%ebp\ntest %eax,%eax\njne 1182 \nmov %r12d,%eax\npop %rbx\npop %rbp\npop %r12\nretq\nmov %edi,%r12d\njmp 11ca \n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov ebx, edi\ntest edi, edi\njz short loc_11CE\nmov ebp, 0\nmov r12d, 0\nloc_1182:\npxor xmm1, xmm1\ncvtsi2sd xmm1, ebp; y\nmovsd xmm0, cs:x; x\ncall _pow\ncvttsd2si edx, xmm0\nmovsxd rax, ebx\nimul rax, 66666667h\nsar rax, 22h\nmov ecx, ebx\nsar ecx, 1Fh\nsub eax, ecx\nlea ecx, [rax+rax*4]\nadd ecx, ecx\nsub ebx, ecx\nimul ebx, edx\nadd r12d, ebx\nmov ebx, eax\nadd ebp, 1\ntest eax, eax\njnz short loc_1182\nloc_11C6:\nmov eax, r12d\npop rbx\npop rbp\npop r12\nretn\nloc_11CE:\nmov r12d, edi\njmp short loc_11C6", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // ebx\n int v2; // ebp\n unsigned int v3; // r12d\n\n v1 = a1;\n if ( a1 )\n {\n v2 = 0;\n v3 = 0;\n do\n {\n v3 += (int)pow(2.0, (double)v2) * (v1 % 10);\n v1 /= 10;\n ++v2;\n }\n while ( v1 );\n }\n else\n {\n return 0;\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush r12\npush rbp\npush rbx\nmov ebx, edi\ntest edi, edi\njz short loc_11CE\nmov ebp, 0\nmov r12d, 0\nloc_1182:\npxor xmm1, xmm1\ncvtsi2sd xmm1, ebp; y\nmovsd xmm0, cs:x; x\ncall _pow\ncvttsd2si edx, xmm0\nmovsxd rax, ebx\nimul rax, 66666667h\nsar rax, 22h\nmov ecx, ebx\nsar ecx, 1Fh\nsub eax, ecx\nlea ecx, [rax+rax*4]\nadd ecx, ecx\nsub ebx, ecx\nimul ebx, edx\nadd r12d, ebx\nmov ebx, eax\nadd ebp, 1\ntest eax, eax\njnz short loc_1182\nloc_11C6:\nmov eax, r12d\npop rbx\npop rbp\npop r12\nretn\nloc_11CE:\nmov r12d, edi\njmp short loc_11C6", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n int v1; // ebx\n int v2; // ebp\n unsigned int v3; // r12d\n\n v1 = a1;\n if ( a1 )\n {\n v2 = 0;\n v3 = 0;\n do\n {\n v3 += (int)pow(2.0, (double)v2) * (v1 % 10);\n v1 /= 10;\n ++v2;\n }\n while ( v1 );\n }\n else\n {\n return 0;\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n int v1;\n int v2;\n unsigned int v3;\n v1 = a1;\n if (a1) {\n v2 = 0;\n v3 = 0;\n do {\n v3 += (int)pow(2.0, (double)v2) * (v1 % 10);\n v1 /= 10;\n ++v2;\n } while (v1);\n } else {\n return 0;\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v2;\n unsigned int v3;\n v1 = a1;\n if (a1) {\n v2 = 0;\n v3 = 0;\n do {\n v3 += (int)pow(2.0, (double)v2) * (v1 % 10);\n v1 /= 10;\n ++v2;\n } while (v1);\n } else {\n return 0;\n }\n return v3;\n}" + }, + { + "index": 24, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int binary) {\n int binary1 = binary;\n int decimal = 0;\n int i = 0;\n while (binary != 0) {\n int dec = binary % 10;\n decimal += dec * (int)pow(2, i);\n binary /= 10;\n i++;\n }\n return decimal;\n}", + "test": "int main() {\n\n assert(func0(100) == 4);\n\n assert(func0(1011) == 11);\n\n assert(func0(1101101) == 109);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\ntest %edi,%edi\nje 1280 \nmov %edi,%ebx\nxor %ebp,%ebp\nxor %r12d,%r12d\nnopl 0x0(%rax,%rax,1)\npxor %xmm1,%xmm1\nmov 0xe4d(%rip),%rax\ncvtsi2sd %ebp,%xmm1\nadd $0x1,%ebp\nmovq %rax,%xmm0\ncallq 1060 \nmovslq %ebx,%rax\nmov %ebx,%edx\nimul $0x66666667,%rax,%rax\nsar $0x1f,%edx\ncvttsd2si %xmm0,%edi\nsar $0x22,%rax\nsub %edx,%eax\nlea (%rax,%rax,4),%edx\nadd %edx,%edx\nsub %edx,%ebx\nimul %edi,%ebx\nadd %ebx,%r12d\nmov %eax,%ebx\ntest %eax,%eax\njne 1228 \nmov %r12d,%eax\npop %rbx\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax,%rax,1)\nxor %r12d,%r12d\npop %rbx\npop %rbp\nmov %r12d,%eax\npop %r12\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\ntest edi, edi\njz short loc_1278\nmov ebx, edi\nxor r12d, r12d\nxor ebp, ebp\nnop dword ptr [rax+rax+00h]\nloc_1228:\npxor xmm1, xmm1\nmovsd xmm0, cs:x; x\ncvtsi2sd xmm1, r12d; y\nadd r12d, 1\ncall _pow\nmovsxd rax, ebx\nmov ecx, ebx\nimul rax, 66666667h\nsar ecx, 1Fh\ncvttsd2si edx, xmm0\nsar rax, 22h\nsub eax, ecx\nlea ecx, [rax+rax*4]\nadd ecx, ecx\nsub ebx, ecx\nimul edx, ebx\nmov ebx, eax\nadd ebp, edx\ntest eax, eax\njnz short loc_1228\nmov eax, ebp\npop rbx\npop rbp\npop r12\nretn\nloc_1278:\nxor ebp, ebp\npop rbx\nmov eax, ebp\npop rbp\npop r12\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // ebx\n int v2; // r12d\n unsigned int v3; // ebp\n double v4; // xmm1_8\n int v5; // edx\n\n if ( !a1 )\n return 0LL;\n v1 = a1;\n v2 = 0;\n v3 = 0;\n do\n {\n v4 = (double)v2++;\n v5 = v1 % 10 * (int)pow(2.0, v4);\n v1 /= 10;\n v3 += v5;\n }\n while ( v1 );\n return v3;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush r12\npush rbp\npush rbx\ntest edi, edi\njz short loc_1278\nmov ebx, edi\nxor r12d, r12d\nxor ebp, ebp\nnop dword ptr [rax+rax+00h]\nloc_1228:\npxor xmm1, xmm1\nmovsd xmm0, cs:x; x\ncvtsi2sd xmm1, r12d; y\nadd r12d, 1\ncall _pow\nmovsxd rax, ebx\nmov ecx, ebx\nimul rax, 66666667h\nsar ecx, 1Fh\ncvttsd2si edx, xmm0\nsar rax, 22h\nsub eax, ecx\nlea ecx, [rax+rax*4]\nadd ecx, ecx\nsub ebx, ecx\nimul edx, ebx\nmov ebx, eax\nadd ebp, edx\ntest eax, eax\njnz short loc_1228\nmov eax, ebp\npop rbx\npop rbp\npop r12\nretn\nloc_1278:\nxor ebp, ebp\npop rbx\nmov eax, ebp\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(int a1)\n{\n int v1; // ebx\n int v2; // r12d\n unsigned int v3; // ebp\n double v4; // xmm1_8\n int v5; // edx\n\n if ( !a1 )\n return 0LL;\n v1 = a1;\n v2 = 0;\n v3 = 0;\n do\n {\n v4 = (double)v2++;\n v5 = v1 % 10 * (int)pow(2.0, v4);\n v1 /= 10;\n v3 += v5;\n }\n while ( v1 );\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(int a1) {\n int v1;\n int v2;\n unsigned int v3;\n double v4;\n int v5;\n if (!a1) return 0LL;\n v1 = a1;\n v2 = 0;\n v3 = 0;\n do {\n v4 = (double)v2++;\n v5 = v1 % 10 * (int)pow(2.0, v4);\n v1 /= 10;\n v3 += v5;\n } while (v1);\n return v3;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v2;\n unsigned int v3;\n double v4;\n int v5;\n if (!a1) return 0LL;\n v1 = a1;\n v2 = 0;\n v3 = 0;\n do {\n v4 = (double)v2++;\n v5 = v1 % 10 * (int)pow(2.0, v4);\n v1 /= 10;\n v3 += v5;\n } while (v1);\n return v3;\n}" + }, + { + "index": 24, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int binary) {\n int binary1 = binary;\n int decimal = 0;\n int i = 0;\n while (binary != 0) {\n int dec = binary % 10;\n decimal += dec * (int)pow(2, i);\n binary /= 10;\n i++;\n }\n return decimal;\n}", + "test": "int main() {\n\n assert(func0(100) == 4);\n\n assert(func0(1011) == 11);\n\n assert(func0(1101101) == 109);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\ntest %edi,%edi\nje 1280 \nmov %edi,%ebx\nxor %ebp,%ebp\nxor %r12d,%r12d\nnopl 0x0(%rax,%rax,1)\npxor %xmm1,%xmm1\nmov 0xe4d(%rip),%rax\ncvtsi2sd %ebp,%xmm1\nadd $0x1,%ebp\nmovq %rax,%xmm0\ncallq 1060 \nmovslq %ebx,%rax\nmov %ebx,%edx\nimul $0x66666667,%rax,%rax\nsar $0x1f,%edx\ncvttsd2si %xmm0,%edi\nsar $0x22,%rax\nsub %edx,%eax\nlea (%rax,%rax,4),%edx\nadd %edx,%edx\nsub %edx,%ebx\nimul %edi,%ebx\nadd %ebx,%r12d\nmov %eax,%ebx\ntest %eax,%eax\njne 1228 \nmov %r12d,%eax\npop %rbx\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax,%rax,1)\nxor %r12d,%r12d\npop %rbx\npop %rbp\nmov %r12d,%eax\npop %r12\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\ntest edi, edi\njz short loc_1278\nmov ebx, edi\nxor r12d, r12d\nxor ebp, ebp\nnop dword ptr [rax+rax+00h]\nloc_1228:\npxor xmm1, xmm1\nmovsd xmm0, cs:x; x\ncvtsi2sd xmm1, r12d; y\nadd r12d, 1\ncall _pow\nmovsxd rax, ebx\nmov ecx, ebx\nimul rax, 66666667h\nsar ecx, 1Fh\ncvttsd2si edx, xmm0\nsar rax, 22h\nsub eax, ecx\nlea ecx, [rax+rax*4]\nadd ecx, ecx\nsub ebx, ecx\nimul edx, ebx\nmov ebx, eax\nadd ebp, edx\ntest eax, eax\njnz short loc_1228\nmov eax, ebp\npop rbx\npop rbp\npop r12\nretn\nloc_1278:\nxor ebp, ebp\npop rbx\nmov eax, ebp\npop rbp\npop r12\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // ebx\n int v2; // r12d\n unsigned int v3; // ebp\n double v4; // xmm1_8\n int v5; // edx\n\n if ( !a1 )\n return 0LL;\n v1 = a1;\n v2 = 0;\n v3 = 0;\n do\n {\n v4 = (double)v2++;\n v5 = v1 % 10 * (int)pow(2.0, v4);\n v1 /= 10;\n v3 += v5;\n }\n while ( v1 );\n return v3;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush r12\npush rbp\npush rbx\ntest edi, edi\njz short loc_1278\nmov ebx, edi\nxor r12d, r12d\nxor ebp, ebp\nnop dword ptr [rax+rax+00h]\nloc_1228:\npxor xmm1, xmm1\nmovsd xmm0, cs:x; x\ncvtsi2sd xmm1, r12d; y\nadd r12d, 1\ncall _pow\nmovsxd rax, ebx\nmov ecx, ebx\nimul rax, 66666667h\nsar ecx, 1Fh\ncvttsd2si edx, xmm0\nsar rax, 22h\nsub eax, ecx\nlea ecx, [rax+rax*4]\nadd ecx, ecx\nsub ebx, ecx\nimul edx, ebx\nmov ebx, eax\nadd ebp, edx\ntest eax, eax\njnz short loc_1228\nmov eax, ebp\npop rbx\npop rbp\npop r12\nretn\nloc_1278:\nxor ebp, ebp\npop rbx\nmov eax, ebp\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(int a1)\n{\n int v1; // ebx\n int v2; // r12d\n unsigned int v3; // ebp\n double v4; // xmm1_8\n int v5; // edx\n\n if ( !a1 )\n return 0LL;\n v1 = a1;\n v2 = 0;\n v3 = 0;\n do\n {\n v4 = (double)v2++;\n v5 = v1 % 10 * (int)pow(2.0, v4);\n v1 /= 10;\n v3 += v5;\n }\n while ( v1 );\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(int a1) {\n int v1;\n int v2;\n unsigned int v3;\n double v4;\n int v5;\n if (!a1) return 0LL;\n v1 = a1;\n v2 = 0;\n v3 = 0;\n do {\n v4 = (double)v2++;\n v5 = v1 % 10 * (int)pow(2.0, v4);\n v1 /= 10;\n v3 += v5;\n } while (v1);\n return v3;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v2;\n unsigned int v3;\n double v4;\n int v5;\n if (!a1) return 0LL;\n v1 = a1;\n v2 = 0;\n v3 = 0;\n do {\n v4 = (double)v2++;\n v5 = v1 % 10 * (int)pow(2.0, v4);\n v1 /= 10;\n v3 += v5;\n } while (v1);\n return v3;\n}" + }, + { + "index": 25, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int i, j, temp, prod = 1;\n for (i = 1; i < n; i++) {\n temp = arr[i];\n j = i - 1;\n while (j >= 0 && arr[j] > temp) {\n arr[j + 1] = arr[j];\n j--;\n }\n arr[j + 1] = temp;\n }\n for (i = 0; i < n; i++) {\n if (i == 0 || arr[i - 1] != arr[i]) {\n prod *= arr[i];\n }\n }\n return prod;\n}", + "test": "int main() {\n\n int arr1[] = {1, 1, 2, 3};\n\n int arr2[] = {1, 2, 3, 1, 1};\n\n int arr3[] = {1, 1, 4, 5, 6};\n\n int arr4[] = {1, 1, 4, 5, 6, 5, 7, 1, 1, 3, 4};\n\n \n\n assert(func0(arr1, 4) == 6);\n\n assert(func0(arr2, 5) == 6);\n\n assert(func0(arr3, 5) == 120);\n\n assert(func0(arr4, 11) == 2520);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x1,-0x8(%rbp)\nmovl $0x1,-0x10(%rbp)\njmpq 1226 \nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x4(%rbp)\nmov -0x10(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0xc(%rbp)\njmp 11e4 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0xc(%rbp),%edx\nmovslq %edx,%rdx\nadd $0x1,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\nsubl $0x1,-0xc(%rbp)\ncmpl $0x0,-0xc(%rbp)\njs 1205 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x4(%rbp)\njl 11af \nmov -0xc(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0x4(%rbp),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x10(%rbp)\nmov -0x10(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 118b \nmovl $0x0,-0x10(%rbp)\njmp 1294 \ncmpl $0x0,-0x10(%rbp)\nje 1271 \nmov -0x10(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\nje 1290 \nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov -0x8(%rbp),%edx\nimul %edx,%eax\nmov %eax,-0x8(%rbp)\naddl $0x1,-0x10(%rbp)\nmov -0x10(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 123b \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 1\nmov [rbp+var_10], 1\njmp loc_1226\nloc_118B:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_10]\nsub eax, 1\nmov [rbp+var_C], eax\njmp short loc_11E4\nloc_11AF:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nadd rdx, 1\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nsub [rbp+var_C], 1\nloc_11E4:\ncmp [rbp+var_C], 0\njs short loc_1205\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_4], eax\njl short loc_11AF\nloc_1205:\nmov eax, [rbp+var_C]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nadd [rbp+var_10], 1\nloc_1226:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_1C]\njl loc_118B\nmov [rbp+var_10], 0\njmp short loc_1294\nloc_123B:\ncmp [rbp+var_10], 0\njz short loc_1271\nmov eax, [rbp+var_10]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_1290\nloc_1271:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_8]\nimul eax, edx\nmov [rbp+var_8], eax\nloc_1290:\nadd [rbp+var_10], 1\nloc_1294:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_1C]\njl short loc_123B\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+Ch] [rbp-10h]\n int k; // [rsp+Ch] [rbp-10h]\n int j; // [rsp+10h] [rbp-Ch]\n unsigned int v6; // [rsp+14h] [rbp-8h]\n int v7; // [rsp+18h] [rbp-4h]\n\n v6 = 1;\n for ( i = 1; i < a2; ++i )\n {\n v7 = *(_DWORD *)(4LL * i + a1);\n for ( j = i - 1; j >= 0 && v7 < *(_DWORD *)(4LL * j + a1); --j )\n *(_DWORD *)(4 * (j + 1LL) + a1) = *(_DWORD *)(4LL * j + a1);\n *(_DWORD *)(a1 + 4 * (j + 1LL)) = v7;\n }\n for ( k = 0; k < a2; ++k )\n {\n if ( !k || *(_DWORD *)(4LL * k - 4 + a1) != *(_DWORD *)(4LL * k + a1) )\n v6 *= *(_DWORD *)(4LL * k + a1);\n }\n return v6;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 1\nmov [rbp+var_10], 1\njmp loc_1226\nloc_118B:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_10]\nsub eax, 1\nmov [rbp+var_C], eax\njmp short loc_11E4\nloc_11AF:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nadd rdx, 1\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nsub [rbp+var_C], 1\nloc_11E4:\ncmp [rbp+var_C], 0\njs short loc_1205\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_4], eax\njl short loc_11AF\nloc_1205:\nmov eax, [rbp+var_C]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nadd [rbp+var_10], 1\nloc_1226:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_1C]\njl loc_118B\nmov [rbp+var_10], 0\njmp short loc_1294\nloc_123B:\ncmp [rbp+var_10], 0\njz short loc_1271\nmov eax, [rbp+var_10]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_1290\nloc_1271:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_8]\nimul eax, edx\nmov [rbp+var_8], eax\nloc_1290:\nadd [rbp+var_10], 1\nloc_1294:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_1C]\njl short loc_123B\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int i; // [rsp+Ch] [rbp-10h]\n int k; // [rsp+Ch] [rbp-10h]\n int j; // [rsp+10h] [rbp-Ch]\n unsigned int v6; // [rsp+14h] [rbp-8h]\n int v7; // [rsp+18h] [rbp-4h]\n\n v6 = 1;\n for ( i = 1; i < a2; ++i )\n {\n v7 = *(_DWORD *)(4LL * i + a1);\n for ( j = i - 1; j >= 0 && v7 < *(_DWORD *)(4LL * j + a1); --j )\n *(_DWORD *)(4 * (j + 1LL) + a1) = *(_DWORD *)(4LL * j + a1);\n *(_DWORD *)(a1 + 4 * (j + 1LL)) = v7;\n }\n for ( k = 0; k < a2; ++k )\n {\n if ( !k || *(_DWORD *)(4LL * k - 4 + a1) != *(_DWORD *)(4LL * k + a1) )\n v6 *= *(_DWORD *)(4LL * k + a1);\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int i;\n int k;\n int j;\n unsigned int v6;\n int v7;\n v6 = 1;\n for (i = 1; i < a2; ++i) {\n v7 = *(uint32_t *)(4LL * i + a1);\n for (j = i - 1; j >= 0 && v7 < *(uint32_t *)(4LL * j + a1); --j)\n *(uint32_t *)(4 * (j + 1LL) + a1) = *(uint32_t *)(4LL * j + a1);\n *(uint32_t *)(a1 + 4 * (j + 1LL)) = v7;\n }\n for (k = 0; k < a2; ++k) {\n if (!k || *(uint32_t *)(4LL * k - 4 + a1) != *(uint32_t *)(4LL * k + a1))\n v6 *= *(uint32_t *)(4LL * k + a1);\n }\n return v6;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int i;\n int k;\n int j;\n unsigned int v6;\n int v7;\n v6 = 1;\n for (i = 1; i < a2; ++i) {\n v7 = *(uint32_t *)(4LL * i + a1);\n for (j = i - 1; j >= 0 && v7 < *(uint32_t *)(4LL * j + a1); --j)\n *(uint32_t *)(4 * (j + 1LL) + a1) = *(uint32_t *)(4LL * j + a1);\n *(uint32_t *)(a1 + 4 * (j + 1LL)) = v7;\n }\n for (k = 0; k < a2; ++k) {\n if (!k || *(uint32_t *)(4LL * k - 4 + a1) != *(uint32_t *)(4LL * k + a1))\n v6 *= *(uint32_t *)(4LL * k + a1);\n }\n return v6;\n}" + }, + { + "index": 25, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int i, j, temp, prod = 1;\n for (i = 1; i < n; i++) {\n temp = arr[i];\n j = i - 1;\n while (j >= 0 && arr[j] > temp) {\n arr[j + 1] = arr[j];\n j--;\n }\n arr[j + 1] = temp;\n }\n for (i = 0; i < n; i++) {\n if (i == 0 || arr[i - 1] != arr[i]) {\n prod *= arr[i];\n }\n }\n return prod;\n}", + "test": "int main() {\n\n int arr1[] = {1, 1, 2, 3};\n\n int arr2[] = {1, 2, 3, 1, 1};\n\n int arr3[] = {1, 1, 4, 5, 6};\n\n int arr4[] = {1, 1, 4, 5, 6, 5, 7, 1, 1, 3, 4};\n\n \n\n assert(func0(arr1, 4) == 6);\n\n assert(func0(arr2, 5) == 6);\n\n assert(func0(arr3, 5) == 120);\n\n assert(func0(arr4, 11) == 2520);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%esi\njle 11c0 \nmov %rdi,%r10\nlea -0x2(%rsi),%r11d\nmov $0x0,%r9d\njmp 1199 \nmovslq %edx,%rdx\nmov %r8d,0x4(%rdi,%rdx,4)\nlea 0x1(%r9),%rax\nadd $0x4,%r10\ncmp %r11,%r9\nje 11ca \nmov %rax,%r9\nmov 0x4(%r10),%r8d\nmov %r9d,%edx\nmov %r10,%rax\ntest %r9d,%r9d\njs 1181 \nmov (%rax),%ecx\ncmp %r8d,%ecx\njle 1181 \nmov %ecx,0x4(%rax)\nsub $0x1,%edx\nsub $0x4,%rax\ncmp $0xffffffff,%edx\njne 11a8 \njmp 1181 \nje 11ca \nmov $0x1,%edx\nmov %edx,%eax\nretq\nmov $0x0,%eax\nmov $0x1,%edx\njmp 11e2 \nimul (%rdi,%rax,4),%edx\nadd $0x1,%rax\ncmp %eax,%esi\njle 11c7 \ntest %eax,%eax\nje 11d6 \nmov (%rdi,%rax,4),%ecx\ncmp %ecx,-0x4(%rdi,%rax,4)\njne 11d6 \njmp 11da \n", + "ida_asm": "func0:\nendbr64\nmov r10, rdi\ncmp esi, 1\njle short loc_11C1\nmov r9, rdi\nlea r11d, [rsi-1]\nmov r8d, 0\njmp short loc_119B\nloc_1184:\nadd edx, 1\nmovsxd rdx, edx\nmov [r10+rdx*4], edi\nadd r8, 1\nadd r9, 4\ncmp r8, r11\njz short loc_11CD\nloc_119B:\nmov edi, [r9+4]\nmov edx, r8d\nmov rax, r9\ntest r8d, r8d\njs short loc_11FB\nloc_11AA:\nmov ecx, [rax]\ncmp ecx, edi\njle short loc_1184\nmov [rax+4], ecx\nsub edx, 1\nsub rax, 4\ncmp edx, 0FFFFFFFFh\njnz short loc_11AA\njmp short loc_1184\nloc_11C1:\ntest esi, esi\njg short loc_11CD\nmov ecx, 1\nloc_11CA:\nmov eax, ecx\nretn\nloc_11CD:\nmovsxd rdx, esi\nmov eax, 0\nmov ecx, 1\njmp short loc_11EA\nloc_11DC:\nimul ecx, [r10+rax*4]\nloc_11E1:\nadd rax, 1\ncmp rdx, rax\njz short loc_11CA\nloc_11EA:\ntest eax, eax\njz short loc_11DC\nmov esi, [r10+rax*4]\ncmp [r10+rax*4-4], esi\njnz short loc_11DC\njmp short loc_11E1\nloc_11FB:\nlea eax, [r8+1]\ncdqe\nmov [r10+rax*4], edi\nadd r8, 1\nadd r9, 4\njmp short loc_119B", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v3; // r9\n __int64 v4; // r8\n int v5; // edi\n int v6; // edx\n _DWORD *v7; // rax\n unsigned int v8; // ecx\n __int64 v10; // rax\n\n if ( a2 <= 1 )\n {\n if ( a2 <= 0 )\n return 1;\n }\n else\n {\n v3 = a1;\n v4 = 0LL;\n do\n {\n while ( 1 )\n {\n v5 = v3[1];\n v6 = v4;\n v7 = v3;\n if ( (int)v4 >= 0 )\n break;\n a1[(int)v4++ + 1] = v5;\n ++v3;\n }\n do\n {\n if ( *v7 <= v5 )\n break;\n v7[1] = *v7;\n --v6;\n --v7;\n }\n while ( v6 != -1 );\n a1[v6 + 1] = v5;\n ++v4;\n ++v3;\n }\n while ( v4 != a2 - 1 );\n }\n v10 = 0LL;\n v8 = 1;\n do\n {\n if ( !(_DWORD)v10 || a1[v10 - 1] != a1[v10] )\n v8 *= a1[v10];\n ++v10;\n }\n while ( a2 != v10 );\n return v8;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov r10, rdi\ncmp esi, 1\njle short loc_11C1\nmov r9, rdi\nlea r11d, [rsi-1]\nmov r8d, 0\njmp short loc_119B\nloc_1184:\nadd edx, 1\nmovsxd rdx, edx\nmov [r10+rdx*4], edi\nadd r8, 1\nadd r9, 4\ncmp r8, r11\njz short loc_11CD\nloc_119B:\nmov edi, [r9+4]\nmov edx, r8d\nmov rax, r9\ntest r8d, r8d\njs short loc_11FB\nloc_11AA:\nmov ecx, [rax]\ncmp ecx, edi\njle short loc_1184\nmov [rax+4], ecx\nsub edx, 1\nsub rax, 4\ncmp edx, 0FFFFFFFFh\njnz short loc_11AA\njmp short loc_1184\nloc_11C1:\ntest esi, esi\njg short loc_11CD\nmov ecx, 1\nloc_11CA:\nmov eax, ecx\nretn\nloc_11CD:\nmovsxd rdx, esi\nmov eax, 0\nmov ecx, 1\njmp short loc_11EA\nloc_11DC:\nimul ecx, [r10+rax*4]\nloc_11E1:\nadd rax, 1\ncmp rdx, rax\njz short loc_11CA\nloc_11EA:\ntest eax, eax\njz short loc_11DC\nmov esi, [r10+rax*4]\ncmp [r10+rax*4-4], esi\njnz short loc_11DC\njmp short loc_11E1\nloc_11FB:\nlea eax, [r8+1]\ncdqe\nmov [r10+rax*4], edi\nadd r8, 1\nadd r9, 4\njmp short loc_119B", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2)\n{\n _DWORD *v3; // r9\n __int64 v4; // r8\n int v5; // edi\n int v6; // edx\n _DWORD *v7; // rax\n unsigned int v8; // ecx\n __int64 v10; // rax\n\n if ( a2 <= 1 )\n {\n if ( a2 <= 0 )\n return 1;\n }\n else\n {\n v3 = a1;\n v4 = 0LL;\n do\n {\n while ( 1 )\n {\n v5 = v3[1];\n v6 = v4;\n v7 = v3;\n if ( (int)v4 >= 0 )\n break;\n a1[(int)v4++ + 1] = v5;\n ++v3;\n }\n do\n {\n if ( *v7 <= v5 )\n break;\n v7[1] = *v7;\n --v6;\n --v7;\n }\n while ( v6 != -1 );\n a1[v6 + 1] = v5;\n ++v4;\n ++v3;\n }\n while ( v4 != a2 - 1 );\n }\n v10 = 0LL;\n v8 = 1;\n do\n {\n if ( !(_DWORD)v10 || a1[v10 - 1] != a1[v10] )\n v8 *= a1[v10];\n ++v10;\n }\n while ( a2 != v10 );\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2) {\n uint32_t *v3;\n long long v4;\n int v5;\n int v6;\n uint32_t *v7;\n unsigned int v8;\n long long v10;\n if (a2 <= 1) {\n if (a2 <= 0) return 1;\n } else {\n v3 = a1;\n v4 = 0LL;\n do {\n while (1) {\n v5 = v3[1];\n v6 = v4;\n v7 = v3;\n if ((int)v4 >= 0) break;\n a1[(int)v4++ + 1] = v5;\n ++v3;\n }\n do {\n if (*v7 <= v5) break;\n v7[1] = *v7;\n --v6;\n --v7;\n } while (v6 != -1);\n a1[v6 + 1] = v5;\n ++v4;\n ++v3;\n } while (v4 != a2 - 1);\n }\n v10 = 0LL;\n v8 = 1;\n do {\n if (!(uint32_t)v10 || a1[v10 - 1] != a1[v10]) v8 *= a1[v10];\n ++v10;\n } while (a2 != v10);\n return v8;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n uint32_t *v3;\n long long v4;\n int v5;\n int v6;\n uint32_t *v7;\n unsigned int v8;\n long long v10;\n if (a2 <= 1) {\n if (a2 <= 0) return 1;\n } else {\n v3 = a1;\n v4 = 0LL;\n do {\n while (1) {\n v5 = v3[1];\n v6 = v4;\n v7 = v3;\n if ((int)v4 >= 0) break;\n a1[(int)v4++ + 1] = v5;\n ++v3;\n }\n do {\n if (*v7 <= v5) break;\n v7[1] = *v7;\n --v6;\n --v7;\n } while (v6 != -1);\n a1[v6 + 1] = v5;\n ++v4;\n ++v3;\n } while (v4 != a2 - 1);\n }\n v10 = 0LL;\n v8 = 1;\n do {\n if (!(uint32_t)v10 || a1[v10 - 1] != a1[v10]) v8 *= a1[v10];\n ++v10;\n } while (a2 != v10);\n return v8;\n}" + }, + { + "index": 25, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int i, j, temp, prod = 1;\n for (i = 1; i < n; i++) {\n temp = arr[i];\n j = i - 1;\n while (j >= 0 && arr[j] > temp) {\n arr[j + 1] = arr[j];\n j--;\n }\n arr[j + 1] = temp;\n }\n for (i = 0; i < n; i++) {\n if (i == 0 || arr[i - 1] != arr[i]) {\n prod *= arr[i];\n }\n }\n return prod;\n}", + "test": "int main() {\n\n int arr1[] = {1, 1, 2, 3};\n\n int arr2[] = {1, 2, 3, 1, 1};\n\n int arr3[] = {1, 1, 4, 5, 6};\n\n int arr4[] = {1, 1, 4, 5, 6, 5, 7, 1, 1, 3, 4};\n\n \n\n assert(func0(arr1, 4) == 6);\n\n assert(func0(arr2, 5) == 6);\n\n assert(func0(arr3, 5) == 120);\n\n assert(func0(arr4, 11) == 2520);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\ncmp $0x1,%esi\njle 13c0 \nlea 0x4(%rdi),%r10\nlea -0x2(%rsi),%ebx\nxor %r11d,%r11d\nnopl 0x0(%rax,%rax,1)\nlea 0x0(,%r11,4),%rax\nlea -0x4(%r10),%r8\nmov (%r10),%r9d\nsub %rax,%r8\nmov %r10,%rax\nnopl (%rax)\nmov -0x4(%rax),%edx\nmov %rax,%rcx\ncmp %r9d,%edx\njle 1371 \nmov %edx,(%rax)\nlea -0x4(%rcx),%rax\ncmp %rax,%r8\njne 1358 \nmov %rdi,%rcx\nmov %r9d,(%rcx)\nlea 0x1(%r11),%rax\nadd $0x4,%r10\ncmp %rbx,%r11\nje 1390 \nmov %rax,%r11\njmp 1340 \nnopw %cs:0x0(%rax,%rax,1)\nxor %eax,%eax\nmov $0x1,%r8d\nnopl 0x0(%rax,%rax,1)\ntest %rax,%rax\nje 13ae \nmov (%rdi,%rax,4),%ebx\ncmp %ebx,-0x4(%rdi,%rax,4)\nje 13b3 \nimul (%rdi,%rax,4),%r8d\nadd $0x1,%rax\ncmp %eax,%esi\njg 13a0 \nmov %r8d,%eax\npop %rbx\nretq\nje 1390 \nmov $0x1,%r8d\npop %rbx\nmov %r8d,%eax\nretq\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\nlea r9d, [rsi-1]\nxor r8d, r8d\ncmp esi, 1\njle short loc_1365\nloc_12F0:\nmov ecx, [rdi+r8*4+4]\nmov rax, r8\njmp short loc_130D\nloc_1300:\nmov [rdi+rax*4+4], edx\nsub rax, 1\ncmp eax, 0FFFFFFFFh\njz short loc_1360\nloc_130D:\nmov edx, [rdi+rax*4]\ncmp edx, ecx\njg short loc_1300\nadd eax, 1\ncdqe\nlea rax, [rdi+rax*4]\nloc_131D:\nadd r8, 1\nmov [rax], ecx\ncmp r9, r8\njnz short loc_12F0\nloc_1328:\nmovsxd rdx, esi\nxor eax, eax\nmov ecx, 1\nnop word ptr [rax+rax+00h]\nloc_1338:\ntest rax, rax\njz short loc_1346\nmov esi, [rdi+rax*4]\ncmp [rdi+rax*4-4], esi\njz short loc_134A\nloc_1346:\nimul ecx, [rdi+rax*4]\nloc_134A:\nadd rax, 1\ncmp rax, rdx\njnz short loc_1338\nmov eax, ecx\nretn\nloc_1360:\nmov rax, rdi\njmp short loc_131D\nloc_1365:\njz short loc_1328\nmov ecx, 1\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n __int64 v2; // r8\n int v3; // ecx\n __int64 v4; // rax\n int v5; // edx\n _DWORD *v6; // rax\n __int64 v7; // rax\n unsigned int v8; // ecx\n\n v2 = 0LL;\n if ( a2 <= 1 )\n {\n if ( a2 != 1 )\n return 1LL;\n }\n else\n {\n do\n {\n v3 = a1[v2 + 1];\n v4 = v2;\n do\n {\n v5 = a1[v4];\n if ( v5 <= v3 )\n {\n v6 = &a1[(int)v4 + 1];\n goto LABEL_6;\n }\n a1[v4-- + 1] = v5;\n }\n while ( (_DWORD)v4 != -1 );\n v6 = a1;\nLABEL_6:\n ++v2;\n *v6 = v3;\n }\n while ( a2 - 1 != v2 );\n }\n v7 = 0LL;\n v8 = 1;\n do\n {\n if ( !v7 || a1[v7 - 1] != a1[v7] )\n v8 *= a1[v7];\n ++v7;\n }\n while ( v7 != a2 );\n return v8;\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\nlea r9d, [rsi-1]\nxor r8d, r8d\ncmp esi, 1\njle short loc_1365\nloc_12F0:\nmov ecx, [rdi+r8*4+4]\nmov rax, r8\njmp short loc_130D\nloc_1300:\nmov [rdi+rax*4+4], edx\nsub rax, 1\ncmp eax, 0FFFFFFFFh\njz short loc_1360\nloc_130D:\nmov edx, [rdi+rax*4]\ncmp edx, ecx\njg short loc_1300\nadd eax, 1\ncdqe\nlea rax, [rdi+rax*4]\nloc_131D:\nadd r8, 1\nmov [rax], ecx\ncmp r9, r8\njnz short loc_12F0\nloc_1328:\nmovsxd rdx, esi\nxor eax, eax\nmov ecx, 1\nnop word ptr [rax+rax+00h]\nloc_1338:\ntest rax, rax\njz short loc_1346\nmov esi, [rdi+rax*4]\ncmp [rdi+rax*4-4], esi\njz short loc_134A\nloc_1346:\nimul ecx, [rdi+rax*4]\nloc_134A:\nadd rax, 1\ncmp rax, rdx\njnz short loc_1338\nmov eax, ecx\nretn\nloc_1360:\nmov rax, rdi\njmp short loc_131D\nloc_1365:\njz short loc_1328\nmov ecx, 1\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12E0(_DWORD *a1, int a2)\n{\n __int64 v2; // r8\n int v3; // ecx\n __int64 v4; // rax\n int v5; // edx\n _DWORD *v6; // rax\n __int64 v7; // rax\n unsigned int v8; // ecx\n\n v2 = 0LL;\n if ( a2 <= 1 )\n {\n if ( a2 != 1 )\n return 1LL;\n }\n else\n {\n do\n {\n v3 = a1[v2 + 1];\n v4 = v2;\n do\n {\n v5 = a1[v4];\n if ( v5 <= v3 )\n {\n v6 = &a1[(int)v4 + 1];\n goto LABEL_6;\n }\n a1[v4-- + 1] = v5;\n }\n while ( (_DWORD)v4 != -1 );\n v6 = a1;\nLABEL_6:\n ++v2;\n *v6 = v3;\n }\n while ( a2 - 1 != v2 );\n }\n v7 = 0LL;\n v8 = 1;\n do\n {\n if ( !v7 || a1[v7 - 1] != a1[v7] )\n v8 *= a1[v7];\n ++v7;\n }\n while ( v7 != a2 );\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12E0(uint32_t *a1, int a2) {\n long long v2;\n int v3;\n long long v4;\n int v5;\n uint32_t *v6;\n long long v7;\n unsigned int v8;\n v2 = 0LL;\n if (a2 <= 1) {\n if (a2 != 1) return 1LL;\n } else {\n do {\n v3 = a1[v2 + 1];\n v4 = v2;\n do {\n v5 = a1[v4];\n if (v5 <= v3) {\n v6 = &a1[(int)v4 + 1];\n goto LABEL_6;\n }\n a1[v4-- + 1] = v5;\n } while ((uint32_t)v4 != -1);\n v6 = a1;\n LABEL_6:\n ++v2;\n *v6 = v3;\n } while (a2 - 1 != v2);\n }\n v7 = 0LL;\n v8 = 1;\n do {\n if (!v7 || a1[v7 - 1] != a1[v7]) v8 *= a1[v7];\n ++v7;\n } while (v7 != a2);\n return v8;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n long long v2;\n int v3;\n long long v4;\n int v5;\n uint32_t *v6;\n long long v7;\n unsigned int v8;\n v2 = 0LL;\n if (a2 <= 1) {\n if (a2 != 1) return 1LL;\n } else {\n do {\n v3 = a1[v2 + 1];\n v4 = v2;\n do {\n v5 = a1[v4];\n if (v5 <= v3) {\n v6 = &a1[(int)v4 + 1];\n goto LABEL_6;\n }\n a1[v4-- + 1] = v5;\n } while ((uint32_t)v4 != -1);\n v6 = a1;\n LABEL_6:\n ++v2;\n *v6 = v3;\n } while (a2 - 1 != v2);\n }\n v7 = 0LL;\n v8 = 1;\n do {\n if (!v7 || a1[v7 - 1] != a1[v7]) v8 *= a1[v7];\n ++v7;\n } while (v7 != a2);\n return v8;\n}" + }, + { + "index": 25, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int i, j, temp, prod = 1;\n for (i = 1; i < n; i++) {\n temp = arr[i];\n j = i - 1;\n while (j >= 0 && arr[j] > temp) {\n arr[j + 1] = arr[j];\n j--;\n }\n arr[j + 1] = temp;\n }\n for (i = 0; i < n; i++) {\n if (i == 0 || arr[i - 1] != arr[i]) {\n prod *= arr[i];\n }\n }\n return prod;\n}", + "test": "int main() {\n\n int arr1[] = {1, 1, 2, 3};\n\n int arr2[] = {1, 2, 3, 1, 1};\n\n int arr3[] = {1, 1, 4, 5, 6};\n\n int arr4[] = {1, 1, 4, 5, 6, 5, 7, 1, 1, 3, 4};\n\n \n\n assert(func0(arr1, 4) == 6);\n\n assert(func0(arr2, 5) == 6);\n\n assert(func0(arr3, 5) == 120);\n\n assert(func0(arr4, 11) == 2520);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\ncmp $0x1,%esi\njle 1380 \nlea 0x4(%rdi),%r10\nlea -0x2(%rsi),%ebx\nxor %r11d,%r11d\nnopl 0x0(%rax,%rax,1)\nlea 0x0(,%r11,4),%rax\nlea -0x4(%r10),%r8\nmov (%r10),%r9d\nsub %rax,%r8\nmov %r10,%rax\nnopl (%rax)\nmov -0x4(%rax),%edx\nmov %rax,%rcx\ncmp %r9d,%edx\njle 1331 \nmov %edx,(%rax)\nlea -0x4(%rcx),%rax\ncmp %r8,%rax\njne 1318 \nmov %rdi,%rcx\nmov %r9d,(%rcx)\nlea 0x1(%r11),%rax\nadd $0x4,%r10\ncmp %rbx,%r11\nje 1350 \nmov %rax,%r11\njmp 1300 \nnopw %cs:0x0(%rax,%rax,1)\nxor %eax,%eax\nmov $0x1,%r8d\nnopl 0x0(%rax,%rax,1)\ntest %rax,%rax\nje 136e \nmov (%rdi,%rax,4),%ebx\ncmp %ebx,-0x4(%rdi,%rax,4)\nje 1373 \nimul (%rdi,%rax,4),%r8d\nadd $0x1,%rax\ncmp %eax,%esi\njg 1360 \nmov %r8d,%eax\npop %rbx\nretq\nje 1350 \nmov $0x1,%r8d\npop %rbx\nmov %r8d,%eax\nretq\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\nlea r9d, [rsi-1]\nxor r8d, r8d\ncmp esi, 1\njle short loc_1365\nloc_12F0:\nmov ecx, [rdi+r8*4+4]\nmov rax, r8\njmp short loc_130D\nloc_1300:\nmov [rdi+rax*4+4], edx\nsub rax, 1\ncmp eax, 0FFFFFFFFh\njz short loc_1360\nloc_130D:\nmov edx, [rdi+rax*4]\ncmp edx, ecx\njg short loc_1300\nadd eax, 1\ncdqe\nlea rax, [rdi+rax*4]\nloc_131D:\nadd r8, 1\nmov [rax], ecx\ncmp r9, r8\njnz short loc_12F0\nloc_1328:\nmovsxd rdx, esi\nxor eax, eax\nmov ecx, 1\nnop word ptr [rax+rax+00h]\nloc_1338:\ntest rax, rax\njz short loc_1346\nmov esi, [rdi+rax*4]\ncmp [rdi+rax*4-4], esi\njz short loc_134A\nloc_1346:\nimul ecx, [rdi+rax*4]\nloc_134A:\nadd rax, 1\ncmp rax, rdx\njnz short loc_1338\nmov eax, ecx\nretn\nloc_1360:\nmov rax, rdi\njmp short loc_131D\nloc_1365:\njz short loc_1328\nmov ecx, 1\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n __int64 v2; // r8\n int v3; // ecx\n __int64 v4; // rax\n int v5; // edx\n _DWORD *v6; // rax\n __int64 v7; // rax\n unsigned int v8; // ecx\n\n v2 = 0LL;\n if ( a2 <= 1 )\n {\n if ( a2 != 1 )\n return 1LL;\n }\n else\n {\n do\n {\n v3 = a1[v2 + 1];\n v4 = v2;\n do\n {\n v5 = a1[v4];\n if ( v5 <= v3 )\n {\n v6 = &a1[(int)v4 + 1];\n goto LABEL_6;\n }\n a1[v4-- + 1] = v5;\n }\n while ( (_DWORD)v4 != -1 );\n v6 = a1;\nLABEL_6:\n ++v2;\n *v6 = v3;\n }\n while ( a2 - 1 != v2 );\n }\n v7 = 0LL;\n v8 = 1;\n do\n {\n if ( !v7 || a1[v7 - 1] != a1[v7] )\n v8 *= a1[v7];\n ++v7;\n }\n while ( v7 != a2 );\n return v8;\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\nlea r9d, [rsi-1]\nxor r8d, r8d\ncmp esi, 1\njle short loc_1365\nloc_12F0:\nmov ecx, [rdi+r8*4+4]\nmov rax, r8\njmp short loc_130D\nloc_1300:\nmov [rdi+rax*4+4], edx\nsub rax, 1\ncmp eax, 0FFFFFFFFh\njz short loc_1360\nloc_130D:\nmov edx, [rdi+rax*4]\ncmp edx, ecx\njg short loc_1300\nadd eax, 1\ncdqe\nlea rax, [rdi+rax*4]\nloc_131D:\nadd r8, 1\nmov [rax], ecx\ncmp r9, r8\njnz short loc_12F0\nloc_1328:\nmovsxd rdx, esi\nxor eax, eax\nmov ecx, 1\nnop word ptr [rax+rax+00h]\nloc_1338:\ntest rax, rax\njz short loc_1346\nmov esi, [rdi+rax*4]\ncmp [rdi+rax*4-4], esi\njz short loc_134A\nloc_1346:\nimul ecx, [rdi+rax*4]\nloc_134A:\nadd rax, 1\ncmp rax, rdx\njnz short loc_1338\nmov eax, ecx\nretn\nloc_1360:\nmov rax, rdi\njmp short loc_131D\nloc_1365:\njz short loc_1328\nmov ecx, 1\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12E0(_DWORD *a1, int a2)\n{\n __int64 v2; // r8\n int v3; // ecx\n __int64 v4; // rax\n int v5; // edx\n _DWORD *v6; // rax\n __int64 v7; // rax\n unsigned int v8; // ecx\n\n v2 = 0LL;\n if ( a2 <= 1 )\n {\n if ( a2 != 1 )\n return 1LL;\n }\n else\n {\n do\n {\n v3 = a1[v2 + 1];\n v4 = v2;\n do\n {\n v5 = a1[v4];\n if ( v5 <= v3 )\n {\n v6 = &a1[(int)v4 + 1];\n goto LABEL_6;\n }\n a1[v4-- + 1] = v5;\n }\n while ( (_DWORD)v4 != -1 );\n v6 = a1;\nLABEL_6:\n ++v2;\n *v6 = v3;\n }\n while ( a2 - 1 != v2 );\n }\n v7 = 0LL;\n v8 = 1;\n do\n {\n if ( !v7 || a1[v7 - 1] != a1[v7] )\n v8 *= a1[v7];\n ++v7;\n }\n while ( v7 != a2 );\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12E0(uint32_t *a1, int a2) {\n long long v2;\n int v3;\n long long v4;\n int v5;\n uint32_t *v6;\n long long v7;\n unsigned int v8;\n v2 = 0LL;\n if (a2 <= 1) {\n if (a2 != 1) return 1LL;\n } else {\n do {\n v3 = a1[v2 + 1];\n v4 = v2;\n do {\n v5 = a1[v4];\n if (v5 <= v3) {\n v6 = &a1[(int)v4 + 1];\n goto LABEL_6;\n }\n a1[v4-- + 1] = v5;\n } while ((uint32_t)v4 != -1);\n v6 = a1;\n LABEL_6:\n ++v2;\n *v6 = v3;\n } while (a2 - 1 != v2);\n }\n v7 = 0LL;\n v8 = 1;\n do {\n if (!v7 || a1[v7 - 1] != a1[v7]) v8 *= a1[v7];\n ++v7;\n } while (v7 != a2);\n return v8;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n long long v2;\n int v3;\n long long v4;\n int v5;\n uint32_t *v6;\n long long v7;\n unsigned int v8;\n v2 = 0LL;\n if (a2 <= 1) {\n if (a2 != 1) return 1LL;\n } else {\n do {\n v3 = a1[v2 + 1];\n v4 = v2;\n do {\n v5 = a1[v4];\n if (v5 <= v3) {\n v6 = &a1[(int)v4 + 1];\n goto LABEL_6;\n }\n a1[v4-- + 1] = v5;\n } while ((uint32_t)v4 != -1);\n v6 = a1;\n LABEL_6:\n ++v2;\n *v6 = v3;\n } while (a2 - 1 != v2);\n }\n v7 = 0LL;\n v8 = 1;\n do {\n if (!v7 || a1[v7 - 1] != a1[v7]) v8 *= a1[v7];\n ++v7;\n } while (v7 != a2);\n return v8;\n}" + }, + { + "index": 26, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int** test_list, size_t* lengths, size_t num_tuples, int K) {\n int res = 1;\n for (size_t i = 0; i < num_tuples && res; i++) {\n for (size_t j = 0; j < lengths[i] && res; j++) {\n if (test_list[i][j] != K) {\n res = 0;\n }\n }\n }\n return res;\n}", + "test": "int main() {\n\n // First test case\n\n int tuple1_1[] = {4, 4};\n\n int tuple1_2[] = {4, 4, 4};\n\n int tuple1_3[] = {4, 4};\n\n int tuple1_4[] = {4, 4, 4, 4};\n\n int tuple1_5[] = {4};\n\n int* test_list1[] = {tuple1_1, tuple1_2, tuple1_3, tuple1_4, tuple1_5};\n\n size_t lengths1[] = {2, 3, 2, 4, 1};\n\n assert(func0(test_list1, lengths1, 5, 4) == 1);\n\n\n\n // Second test case\n\n int tuple2_1[] = {7, 7, 7};\n\n int tuple2_2[] = {7, 7};\n\n int* test_list2[] = {tuple2_1, tuple2_2};\n\n size_t lengths2[] = {3, 2};\n\n assert(func0(test_list2, lengths2, 2, 7) == 1);\n\n\n\n // Third test case\n\n int tuple3_1[] = {9, 9};\n\n int tuple3_2[] = {9, 9, 9, 9};\n\n int* test_list3[] = {tuple3_1, tuple3_2};\n\n size_t lengths3[] = {2, 4};\n\n assert(func0(test_list3, lengths3, 2, 7) == 0);\n\n\n\n // Fourth test case\n\n int tuple4_1[] = {4, 4};\n\n int tuple4_2[] = {4, 4, 4};\n\n int tuple4_3[] = {4, 4};\n\n int tuple4_4[] = {4, 4, 6, 4};\n\n int tuple4_5[] = {4};\n\n int* test_list4[] = {tuple4_1, tuple4_2, tuple4_3, tuple4_4, tuple4_5};\n\n size_t lengths4[] = {2, 3, 2, 4, 1};\n\n assert(func0(test_list4, lengths4, 5, 4) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x28(%rbp)\nmov %rsi,-0x30(%rbp)\nmov %rdx,-0x38(%rbp)\nmov %ecx,-0x3c(%rbp)\nmovl $0x1,-0x14(%rbp)\nmovq $0x0,-0x10(%rbp)\njmp 11f6 \nmovq $0x0,-0x8(%rbp)\njmp 11cf \nmov -0x10(%rbp),%rax\nlea 0x0(,%rax,8),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0x8(%rbp),%rdx\nshl $0x2,%rdx\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x3c(%rbp)\nje 11ca \nmovl $0x0,-0x14(%rbp)\naddq $0x1,-0x8(%rbp)\nmov -0x10(%rbp),%rax\nlea 0x0(,%rax,8),%rdx\nmov -0x30(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\ncmp %rax,-0x8(%rbp)\njae 11f1 \ncmpl $0x0,-0x14(%rbp)\njne 119b \naddq $0x1,-0x10(%rbp)\nmov -0x10(%rbp),%rax\ncmp -0x38(%rbp),%rax\njae 1206 \ncmpl $0x0,-0x14(%rbp)\njne 1191 \nmov -0x14(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_30], rsi\nmov [rbp+var_38], rdx\nmov [rbp+var_3C], ecx\nmov [rbp+var_14], 1\nmov [rbp+var_10], 0\njmp short loc_11F6\nloc_1191:\nmov [rbp+var_8], 0\njmp short loc_11CF\nloc_119B:\nmov rax, [rbp+var_10]\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov rdx, [rbp+var_8]\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_3C], eax\njz short loc_11CA\nmov [rbp+var_14], 0\nloc_11CA:\nadd [rbp+var_8], 1\nloc_11CF:\nmov rax, [rbp+var_10]\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov rax, [rax]\ncmp [rbp+var_8], rax\njnb short loc_11F1\ncmp [rbp+var_14], 0\njnz short loc_119B\nloc_11F1:\nadd [rbp+var_10], 1\nloc_11F6:\nmov rax, [rbp+var_10]\ncmp rax, [rbp+var_38]\njnb short loc_1206\ncmp [rbp+var_14], 0\njnz short loc_1191\nloc_1206:\nmov eax, [rbp+var_14]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, unsigned __int64 a3, int a4)\n{\n unsigned int v5; // [rsp+28h] [rbp-14h]\n unsigned __int64 i; // [rsp+2Ch] [rbp-10h]\n unsigned __int64 j; // [rsp+34h] [rbp-8h]\n\n v5 = 1;\n for ( i = 0LL; i < a3 && v5; ++i )\n {\n for ( j = 0LL; j < *(_QWORD *)(8 * i + a2) && v5; ++j )\n {\n if ( a4 != *(_DWORD *)(4 * j + *(_QWORD *)(8 * i + a1)) )\n v5 = 0;\n }\n }\n return v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_30], rsi\nmov [rbp+var_38], rdx\nmov [rbp+var_3C], ecx\nmov [rbp+var_14], 1\nmov [rbp+var_10], 0\njmp short loc_11F6\nloc_1191:\nmov [rbp+var_8], 0\njmp short loc_11CF\nloc_119B:\nmov rax, [rbp+var_10]\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov rdx, [rbp+var_8]\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_3C], eax\njz short loc_11CA\nmov [rbp+var_14], 0\nloc_11CA:\nadd [rbp+var_8], 1\nloc_11CF:\nmov rax, [rbp+var_10]\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov rax, [rax]\ncmp [rbp+var_8], rax\njnb short loc_11F1\ncmp [rbp+var_14], 0\njnz short loc_119B\nloc_11F1:\nadd [rbp+var_10], 1\nloc_11F6:\nmov rax, [rbp+var_10]\ncmp rax, [rbp+var_38]\njnb short loc_1206\ncmp [rbp+var_14], 0\njnz short loc_1191\nloc_1206:\nmov eax, [rbp+var_14]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, unsigned __int64 a3, int a4)\n{\n unsigned int v5; // [rsp+28h] [rbp-14h]\n unsigned __int64 i; // [rsp+2Ch] [rbp-10h]\n unsigned __int64 j; // [rsp+34h] [rbp-8h]\n\n v5 = 1;\n for ( i = 0LL; i < a3 && v5; ++i )\n {\n for ( j = 0LL; j < *(_QWORD *)(8 * i + a2) && v5; ++j )\n {\n if ( a4 != *(_DWORD *)(4 * j + *(_QWORD *)(8 * i + a1)) )\n v5 = 0;\n }\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, unsigned long long a3, int a4) {\n unsigned int v5;\n unsigned long long i;\n unsigned long long j;\n v5 = 1;\n for (i = 0LL; i < a3 && v5; ++i) {\n for (j = 0LL; j < *(uint64_t *)(8 * i + a2) && v5; ++j) {\n if (a4 != *(uint32_t *)(4 * j + *(uint64_t *)(8 * i + a1))) v5 = 0;\n }\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, unsigned long long a3, int a4) {\n unsigned int v5;\n unsigned long long i;\n unsigned long long j;\n v5 = 1;\n for (i = 0LL; i < a3 && v5; ++i) {\n for (j = 0LL; j < *(uint64_t *)(8 * i + a2) && v5; ++j) {\n if (a4 != *(uint32_t *)(4 * j + *(uint64_t *)(8 * i + a1))) v5 = 0;\n }\n }\n return v5;\n}" + }, + { + "index": 26, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int** test_list, size_t* lengths, size_t num_tuples, int K) {\n int res = 1;\n for (size_t i = 0; i < num_tuples && res; i++) {\n for (size_t j = 0; j < lengths[i] && res; j++) {\n if (test_list[i][j] != K) {\n res = 0;\n }\n }\n }\n return res;\n}", + "test": "int main() {\n\n // First test case\n\n int tuple1_1[] = {4, 4};\n\n int tuple1_2[] = {4, 4, 4};\n\n int tuple1_3[] = {4, 4};\n\n int tuple1_4[] = {4, 4, 4, 4};\n\n int tuple1_5[] = {4};\n\n int* test_list1[] = {tuple1_1, tuple1_2, tuple1_3, tuple1_4, tuple1_5};\n\n size_t lengths1[] = {2, 3, 2, 4, 1};\n\n assert(func0(test_list1, lengths1, 5, 4) == 1);\n\n\n\n // Second test case\n\n int tuple2_1[] = {7, 7, 7};\n\n int tuple2_2[] = {7, 7};\n\n int* test_list2[] = {tuple2_1, tuple2_2};\n\n size_t lengths2[] = {3, 2};\n\n assert(func0(test_list2, lengths2, 2, 7) == 1);\n\n\n\n // Third test case\n\n int tuple3_1[] = {9, 9};\n\n int tuple3_2[] = {9, 9, 9, 9};\n\n int* test_list3[] = {tuple3_1, tuple3_2};\n\n size_t lengths3[] = {2, 4};\n\n assert(func0(test_list3, lengths3, 2, 7) == 0);\n\n\n\n // Fourth test case\n\n int tuple4_1[] = {4, 4};\n\n int tuple4_2[] = {4, 4, 4};\n\n int tuple4_3[] = {4, 4};\n\n int tuple4_4[] = {4, 4, 6, 4};\n\n int tuple4_5[] = {4};\n\n int* test_list4[] = {tuple4_1, tuple4_2, tuple4_3, tuple4_4, tuple4_5};\n\n size_t lengths4[] = {2, 3, 2, 4, 1};\n\n assert(func0(test_list4, lengths4, 5, 4) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x0,%r10d\ntest %rdx,%rdx\njne 119c \nmov $0x1,%eax\nretq\nadd $0x1,%rax\ncmp %r8,%rax\njae 1193 \ncmp %ecx,(%r9,%rax,4)\nje 117e \nmov $0x0,%eax\nretq\nadd $0x1,%r10\ncmp %r10,%rdx\njbe 11b0 \nmov (%rsi,%r10,8),%r8\ntest %r8,%r8\nje 1193 \nmov (%rdi,%r10,8),%r9\nmov $0x0,%eax\njmp 1187 \nmov $0x1,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov r10d, 0\ntest rdx, rdx\njnz short loc_119C\nmov eax, 1\nretn\nloc_117E:\nadd rax, 1\ncmp rax, r8\njnb short loc_1193\nloc_1187:\ncmp [r9+rax*4], ecx\njz short loc_117E\nmov eax, 0\nretn\nloc_1193:\nadd r10, 1\ncmp r10, rdx\njnb short loc_11B0\nloc_119C:\nmov r8, [rsi+r10*8]\ntest r8, r8\njz short loc_1193\nmov r9, [rdi+r10*8]\nmov eax, 0\njmp short loc_1187\nloc_11B0:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, unsigned __int64 a3, int a4)\n{\n __int64 v4; // r10\n __int64 v6; // rax\n unsigned __int64 v7; // r8\n\n v4 = 0LL;\n if ( !a3 )\n return 1LL;\n while ( 1 )\n {\n v7 = *(_QWORD *)(a2 + 8 * v4);\n if ( v7 )\n break;\nLABEL_6:\n if ( ++v4 >= a3 )\n return 1LL;\n }\n v6 = 0LL;\n while ( *(_DWORD *)(*(_QWORD *)(a1 + 8 * v4) + 4 * v6) == a4 )\n {\n if ( ++v6 >= v7 )\n goto LABEL_6;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov r10d, 0\ntest rdx, rdx\njnz short loc_119C\nmov eax, 1\nretn\nloc_117E:\nadd rax, 1\ncmp rax, r8\njnb short loc_1193\nloc_1187:\ncmp [r9+rax*4], ecx\njz short loc_117E\nmov eax, 0\nretn\nloc_1193:\nadd r10, 1\ncmp r10, rdx\njnb short loc_11B0\nloc_119C:\nmov r8, [rsi+r10*8]\ntest r8, r8\njz short loc_1193\nmov r9, [rdi+r10*8]\nmov eax, 0\njmp short loc_1187\nloc_11B0:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, unsigned __int64 a3, int a4)\n{\n __int64 v4; // r10\n __int64 v6; // rax\n unsigned __int64 v7; // r8\n\n v4 = 0LL;\n if ( !a3 )\n return 1LL;\n while ( 1 )\n {\n v7 = *(_QWORD *)(a2 + 8 * v4);\n if ( v7 )\n break;\nLABEL_6:\n if ( ++v4 >= a3 )\n return 1LL;\n }\n v6 = 0LL;\n while ( *(_DWORD *)(*(_QWORD *)(a1 + 8 * v4) + 4 * v6) == a4 )\n {\n if ( ++v6 >= v7 )\n goto LABEL_6;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, unsigned long long a3, int a4) {\n long long v4;\n long long v6;\n unsigned long long v7;\n v4 = 0LL;\n if (!a3) return 1LL;\n while (1) {\n v7 = *(uint64_t *)(a2 + 8 * v4);\n if (v7) break;\n LABEL_6:\n if (++v4 >= a3) return 1LL;\n }\n v6 = 0LL;\n while (*(uint32_t *)(*(uint64_t *)(a1 + 8 * v4) + 4 * v6) == a4) {\n if (++v6 >= v7) goto LABEL_6;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, unsigned long long a3, int a4) {\n long long v4;\n long long v6;\n unsigned long long v7;\n v4 = 0LL;\n if (!a3) return 1LL;\n while (1) {\n v7 = *(uint64_t *)(a2 + 8 * v4);\n if (v7) break;\n LABEL_6:\n if (++v4 >= a3) return 1LL;\n }\n v6 = 0LL;\n while (*(uint32_t *)(*(uint64_t *)(a1 + 8 * v4) + 4 * v6) == a4) {\n if (++v6 >= v7) goto LABEL_6;\n }\n return 0LL;\n}" + }, + { + "index": 26, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int** test_list, size_t* lengths, size_t num_tuples, int K) {\n int res = 1;\n for (size_t i = 0; i < num_tuples && res; i++) {\n for (size_t j = 0; j < lengths[i] && res; j++) {\n if (test_list[i][j] != K) {\n res = 0;\n }\n }\n }\n return res;\n}", + "test": "int main() {\n\n // First test case\n\n int tuple1_1[] = {4, 4};\n\n int tuple1_2[] = {4, 4, 4};\n\n int tuple1_3[] = {4, 4};\n\n int tuple1_4[] = {4, 4, 4, 4};\n\n int tuple1_5[] = {4};\n\n int* test_list1[] = {tuple1_1, tuple1_2, tuple1_3, tuple1_4, tuple1_5};\n\n size_t lengths1[] = {2, 3, 2, 4, 1};\n\n assert(func0(test_list1, lengths1, 5, 4) == 1);\n\n\n\n // Second test case\n\n int tuple2_1[] = {7, 7, 7};\n\n int tuple2_2[] = {7, 7};\n\n int* test_list2[] = {tuple2_1, tuple2_2};\n\n size_t lengths2[] = {3, 2};\n\n assert(func0(test_list2, lengths2, 2, 7) == 1);\n\n\n\n // Third test case\n\n int tuple3_1[] = {9, 9};\n\n int tuple3_2[] = {9, 9, 9, 9};\n\n int* test_list3[] = {tuple3_1, tuple3_2};\n\n size_t lengths3[] = {2, 4};\n\n assert(func0(test_list3, lengths3, 2, 7) == 0);\n\n\n\n // Fourth test case\n\n int tuple4_1[] = {4, 4};\n\n int tuple4_2[] = {4, 4, 4};\n\n int tuple4_3[] = {4, 4};\n\n int tuple4_4[] = {4, 4, 6, 4};\n\n int tuple4_5[] = {4};\n\n int* test_list4[] = {tuple4_1, tuple4_2, tuple4_3, tuple4_4, tuple4_5};\n\n size_t lengths4[] = {2, 3, 2, 4, 1};\n\n assert(func0(test_list4, lengths4, 5, 4) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nxor %r10d,%r10d\ntest %rdx,%rdx\nje 1512 \nnopl 0x0(%rax)\nmov (%rsi,%r10,8),%r9\ntest %r9,%r9\nje 1509 \nmov (%rdi,%r10,8),%r8\nxor %eax,%eax\ncmp %ecx,(%r8,%rax,4)\nje 1500 \nxor %eax,%eax\nretq\nnopl 0x0(%rax,%rax,1)\nadd $0x1,%rax\ncmp %r9,%rax\njne 14ef \nadd $0x1,%r10\ncmp %r10,%rdx\njne 14e0 \nmov $0x1,%eax\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmov r11, rdi\nxor r10d, r10d\nmov edi, 1\ntest rdx, rdx\njz short loc_151A\nnop dword ptr [rax+00h]\nloc_14C8:\nmov r8, [rsi+r10*8]\nmov eax, 1\nmov edi, 1\ntest r8, r8\njz short loc_1506\nmov r9, [r11+r10*8]\nxor eax, eax\njmp short loc_14EC\nloc_14E8:\ncmp edi, ecx\njnz short loc_1518\nloc_14EC:\nmov edi, [r9+rax*4]\nadd rax, 1\ncmp rax, r8\njnz short loc_14E8\ncmp edi, ecx\nsetz dil\nsetz al\nmovzx edi, dil\nloc_1506:\nadd r10, 1\ncmp r10, rdx\njnb short loc_151A\ntest al, al\njnz short loc_14C8\njmp short loc_151A\nloc_1518:\nxor edi, edi\nloc_151A:\nmov eax, edi\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(__int64 a1, __int64 a2, unsigned __int64 a3, int a4)\n{\n __int64 v5; // r10\n _BOOL4 v6; // edi\n __int64 v7; // r8\n bool v8; // al\n __int64 v9; // rax\n int v10; // edi\n\n v5 = 0LL;\n v6 = 1;\n if ( a3 )\n {\n while ( 1 )\n {\n v7 = *(_QWORD *)(a2 + 8 * v5);\n v8 = 1;\n v6 = 1;\n if ( v7 )\n break;\nLABEL_7:\n if ( ++v5 >= a3 || !v8 )\n return v6;\n }\n v9 = 0LL;\n do\n {\n v10 = *(_DWORD *)(*(_QWORD *)(a1 + 8 * v5) + 4 * v9++);\n if ( v9 == v7 )\n {\n v8 = v10 == a4;\n v6 = v10 == a4;\n goto LABEL_7;\n }\n }\n while ( v10 == a4 );\n return 0;\n }\n return v6;\n}", + "ida_strip_asm": "sub_14B0:\nendbr64\nmov r11, rdi\nxor r10d, r10d\nmov edi, 1\ntest rdx, rdx\njz short loc_151A\nnop dword ptr [rax+00h]\nloc_14C8:\nmov r8, [rsi+r10*8]\nmov eax, 1\nmov edi, 1\ntest r8, r8\njz short loc_1506\nmov r9, [r11+r10*8]\nxor eax, eax\njmp short loc_14EC\nloc_14E8:\ncmp edi, ecx\njnz short loc_1518\nloc_14EC:\nmov edi, [r9+rax*4]\nadd rax, 1\ncmp rax, r8\njnz short loc_14E8\ncmp edi, ecx\nsetz dil\nsetz al\nmovzx edi, dil\nloc_1506:\nadd r10, 1\ncmp r10, rdx\njnb short loc_151A\ntest al, al\njnz short loc_14C8\njmp short loc_151A\nloc_1518:\nxor edi, edi\nloc_151A:\nmov eax, edi\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_14B0(__int64 a1, __int64 a2, unsigned __int64 a3, int a4)\n{\n __int64 v5; // r10\n _BOOL4 v6; // edi\n __int64 v7; // r8\n bool v8; // al\n __int64 v9; // rax\n int v10; // edi\n\n v5 = 0LL;\n v6 = 1;\n if ( a3 )\n {\n while ( 1 )\n {\n v7 = *(_QWORD *)(a2 + 8 * v5);\n v8 = 1;\n v6 = 1;\n if ( v7 )\n break;\nLABEL_7:\n if ( ++v5 >= a3 || !v8 )\n return v6;\n }\n v9 = 0LL;\n do\n {\n v10 = *(_DWORD *)(*(_QWORD *)(a1 + 8 * v5) + 4 * v9++);\n if ( v9 == v7 )\n {\n v8 = v10 == a4;\n v6 = v10 == a4;\n goto LABEL_7;\n }\n }\n while ( v10 == a4 );\n return 0;\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_14B0(long long a1, long long a2, unsigned long long a3, int a4) {\n long long v5;\n int v6;\n long long v7;\n bool v8;\n long long v9;\n int v10;\n v5 = 0LL;\n v6 = 1;\n if (a3) {\n while (1) {\n v7 = *(uint64_t *)(a2 + 8 * v5);\n v8 = 1;\n v6 = 1;\n if (v7) break;\n LABEL_7:\n if (++v5 >= a3 || !v8) return v6;\n }\n v9 = 0LL;\n do {\n v10 = *(uint32_t *)(*(uint64_t *)(a1 + 8 * v5) + 4 * v9++);\n if (v9 == v7) {\n v8 = v10 == a4;\n v6 = v10 == a4;\n goto LABEL_7;\n }\n } while (v10 == a4);\n return 0;\n }\n return v6;\n}", + "ida_pseudo_norm": "uint8_t func0(long long a1, long long a2, unsigned long long a3, int a4) {\n long long v5;\n int v6;\n long long v7;\n bool v8;\n long long v9;\n int v10;\n v5 = 0LL;\n v6 = 1;\n if (a3) {\n while (1) {\n v7 = *(uint64_t *)(a2 + 8 * v5);\n v8 = 1;\n v6 = 1;\n if (v7) break;\n LABEL_7:\n if (++v5 >= a3 || !v8) return v6;\n }\n v9 = 0LL;\n do {\n v10 = *(uint32_t *)(*(uint64_t *)(a1 + 8 * v5) + 4 * v9++);\n if (v9 == v7) {\n v8 = v10 == a4;\n v6 = v10 == a4;\n goto LABEL_7;\n }\n } while (v10 == a4);\n return 0;\n }\n return v6;\n}" + }, + { + "index": 27, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n#define MAX_STRINGS 3\n\n#define MAX_LENGTH 100\n\n\n\n", + "func": "void func0(char input[][MAX_LENGTH], char output[][MAX_LENGTH], int n) {\n for (int i = 0; i < n; i++) {\n int j = 0, k = 0;\n while (input[i][j] != '\\0') {\n if (!isdigit((unsigned char)input[i][j])) {\n output[i][k++] = input[i][j];\n }\n j++;\n }\n output[i][k] = '\\0';\n }\n}", + "test": "int main() {\n\n char input1[MAX_STRINGS][MAX_LENGTH] = {\"4words\", \"3letters\", \"4digits\"};\n\n char expected1[MAX_STRINGS][MAX_LENGTH] = {\"words\", \"letters\", \"digits\"};\n\n char output1[MAX_STRINGS][MAX_LENGTH];\n\n func0(input1, output1, MAX_STRINGS);\n\n for(int i = 0; i < MAX_STRINGS; i++) {\n\n assert(strcmp(output1[i], expected1[i]) == 0);\n\n }\n\n\n\n char input2[MAX_STRINGS][MAX_LENGTH] = {\"28Jan\", \"12Jan\", \"11Jan\"};\n\n char expected2[MAX_STRINGS][MAX_LENGTH] = {\"Jan\", \"Jan\", \"Jan\"};\n\n char output2[MAX_STRINGS][MAX_LENGTH];\n\n func0(input2, output2, MAX_STRINGS);\n\n for(int i = 0; i < MAX_STRINGS; i++) {\n\n assert(strcmp(output2[i], expected2[i]) == 0);\n\n }\n\n\n\n char input3[MAX_STRINGS][MAX_LENGTH] = {\"wonder1\", \"wonder2\", \"wonder3\"};\n\n char expected3[MAX_STRINGS][MAX_LENGTH] = {\"wonder\", \"wonder\", \"wonder\"};\n\n char output3[MAX_STRINGS][MAX_LENGTH];\n\n func0(input3, output3, MAX_STRINGS);\n\n for(int i = 0; i < MAX_STRINGS; i++) {\n\n assert(strcmp(output3[i], expected3[i]) == 0);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %edx,-0x24(%rbp)\nmovl $0x0,-0xc(%rbp)\njmpq 1311 \nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmpq 12a1 \ncallq 10b0 <__ctype_b_loc@plt>\nmov (%rax),%rcx\nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0x8(%rbp),%eax\ncltq\nmovzbl (%rdx,%rax,1),%eax\nmovzbl %al,%eax\nadd %rax,%rax\nadd %rcx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x800,%eax\ntest %eax,%eax\njne 129d \nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rsi\nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x20(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x4(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x4(%rbp)\nmov -0x8(%rbp),%edx\nmovslq %edx,%rdx\nmovzbl (%rsi,%rdx,1),%edx\ncltq\nmov %dl,(%rcx,%rax,1)\naddl $0x1,-0x8(%rbp)\nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0x8(%rbp),%eax\ncltq\nmovzbl (%rdx,%rax,1),%eax\ntest %al,%al\njne 11df \nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x20(%rbp),%rax\nadd %rax,%rdx\nmov -0x4(%rbp),%eax\ncltq\nmovb $0x0,(%rdx,%rax,1)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x24(%rbp),%eax\njl 11cc \nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_C], 0\njmp loc_1311\nloc_11CC:\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp loc_12A1\nloc_11DF:\ncall ___ctype_b_loc\nmov rcx, [rax]\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_8]\ncdqe\nmovzx eax, byte ptr [rdx+rax]\nmovzx eax, al\nadd rax, rax\nadd rax, rcx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 800h\ntest eax, eax\njnz short loc_129D\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_18]\nlea rsi, [rdx+rax]\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_20]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_4]\nlea edx, [rax+1]\nmov [rbp+var_4], edx\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nmovzx edx, byte ptr [rsi+rdx]\ncdqe\nmov [rcx+rax], dl\nloc_129D:\nadd [rbp+var_8], 1\nloc_12A1:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_8]\ncdqe\nmovzx eax, byte ptr [rdx+rax]\ntest al, al\njnz loc_11DF\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_20]\nadd rdx, rax\nmov eax, [rbp+var_4]\ncdqe\nmov byte ptr [rdx+rax], 0\nadd [rbp+var_C], 1\nloc_1311:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_24]\njl loc_11CC\nnop\nnop\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n int v3; // eax\n __int64 result; // rax\n unsigned int i; // [rsp+24h] [rbp-Ch]\n int v7; // [rsp+28h] [rbp-8h]\n int v8; // [rsp+2Ch] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a3 )\n break;\n v7 = 0;\n v8 = 0;\n while ( *(_BYTE *)(a1 + 100LL * (int)i + v7) )\n {\n if ( ((*__ctype_b_loc())[*(unsigned __int8 *)(a1 + 100LL * (int)i + v7)] & 0x800) == 0 )\n {\n v3 = v8++;\n *(_BYTE *)(100LL * (int)i + a2 + v3) = *(_BYTE *)(100LL * (int)i + a1 + v7);\n }\n ++v7;\n }\n *(_BYTE *)(a2 + 100LL * (int)i + v8) = 0;\n }\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_C], 0\njmp loc_1311\nloc_11CC:\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp loc_12A1\nloc_11DF:\ncall ___ctype_b_loc\nmov rcx, [rax]\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_8]\ncdqe\nmovzx eax, byte ptr [rdx+rax]\nmovzx eax, al\nadd rax, rax\nadd rax, rcx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 800h\ntest eax, eax\njnz short loc_129D\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_18]\nlea rsi, [rdx+rax]\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_20]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_4]\nlea edx, [rax+1]\nmov [rbp+var_4], edx\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nmovzx edx, byte ptr [rsi+rdx]\ncdqe\nmov [rcx+rax], dl\nloc_129D:\nadd [rbp+var_8], 1\nloc_12A1:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_8]\ncdqe\nmovzx eax, byte ptr [rdx+rax]\ntest al, al\njnz loc_11DF\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_20]\nadd rdx, rax\nmov eax, [rbp+var_4]\ncdqe\nmov byte ptr [rdx+rax], 0\nadd [rbp+var_C], 1\nloc_1311:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_24]\njl loc_11CC\nnop\nnop\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(__int64 a1, __int64 a2, int a3)\n{\n int v3; // eax\n __int64 result; // rax\n unsigned int i; // [rsp+24h] [rbp-Ch]\n int v7; // [rsp+28h] [rbp-8h]\n int v8; // [rsp+2Ch] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a3 )\n break;\n v7 = 0;\n v8 = 0;\n while ( *(_BYTE *)(a1 + 100LL * (int)i + v7) )\n {\n if ( ((*__ctype_b_loc())[*(unsigned __int8 *)(a1 + 100LL * (int)i + v7)] & 0x800) == 0 )\n {\n v3 = v8++;\n *(_BYTE *)(100LL * (int)i + a2 + v3) = *(_BYTE *)(100LL * (int)i + a1 + v7);\n }\n ++v7;\n }\n *(_BYTE *)(a2 + 100LL * (int)i + v8) = 0;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(long long a1, long long a2, int a3) {\n int v3;\n long long result;\n unsigned int i;\n int v7;\n int v8;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a3) break;\n v7 = 0;\n v8 = 0;\n while (*(uint8_t *)(a1 + 100LL * (int)i + v7)) {\n if (((*__ctype_b_loc())[*(unsigned char *)(a1 + 100LL * (int)i + v7)] &\n 2048) == 0) {\n v3 = v8++;\n *(uint8_t *)(100LL * (int)i + a2 + v3) =\n *(uint8_t *)(100LL * (int)i + a1 + v7);\n }\n ++v7;\n }\n *(uint8_t *)(a2 + 100LL * (int)i + v8) = 0;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3) {\n int v3;\n long long result;\n unsigned int i;\n int v7;\n int v8;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a3) break;\n v7 = 0;\n v8 = 0;\n while (*(uint8_t *)(a1 + 100LL * (int)i + v7)) {\n if (((*__ctype_b_loc())[*(unsigned char *)(a1 + 100LL * (int)i + v7)] &\n 2048) == 0) {\n v3 = v8++;\n *(uint8_t *)(100LL * (int)i + a2 + v3) =\n *(uint8_t *)(100LL * (int)i + a1 + v7);\n }\n ++v7;\n }\n *(uint8_t *)(a2 + 100LL * (int)i + v8) = 0;\n }\n return result;\n}" + }, + { + "index": 27, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n#define MAX_STRINGS 3\n\n#define MAX_LENGTH 100\n\n\n\n", + "func": "void func0(char input[][MAX_LENGTH], char output[][MAX_LENGTH], int n) {\n for (int i = 0; i < n; i++) {\n int j = 0, k = 0;\n while (input[i][j] != '\\0') {\n if (!isdigit((unsigned char)input[i][j])) {\n output[i][k++] = input[i][j];\n }\n j++;\n }\n output[i][k] = '\\0';\n }\n}", + "test": "int main() {\n\n char input1[MAX_STRINGS][MAX_LENGTH] = {\"4words\", \"3letters\", \"4digits\"};\n\n char expected1[MAX_STRINGS][MAX_LENGTH] = {\"words\", \"letters\", \"digits\"};\n\n char output1[MAX_STRINGS][MAX_LENGTH];\n\n func0(input1, output1, MAX_STRINGS);\n\n for(int i = 0; i < MAX_STRINGS; i++) {\n\n assert(strcmp(output1[i], expected1[i]) == 0);\n\n }\n\n\n\n char input2[MAX_STRINGS][MAX_LENGTH] = {\"28Jan\", \"12Jan\", \"11Jan\"};\n\n char expected2[MAX_STRINGS][MAX_LENGTH] = {\"Jan\", \"Jan\", \"Jan\"};\n\n char output2[MAX_STRINGS][MAX_LENGTH];\n\n func0(input2, output2, MAX_STRINGS);\n\n for(int i = 0; i < MAX_STRINGS; i++) {\n\n assert(strcmp(output2[i], expected2[i]) == 0);\n\n }\n\n\n\n char input3[MAX_STRINGS][MAX_LENGTH] = {\"wonder1\", \"wonder2\", \"wonder3\"};\n\n char expected3[MAX_STRINGS][MAX_LENGTH] = {\"wonder\", \"wonder\", \"wonder\"};\n\n char output3[MAX_STRINGS][MAX_LENGTH];\n\n func0(input3, output3, MAX_STRINGS);\n\n for(int i = 0; i < MAX_STRINGS; i++) {\n\n assert(strcmp(output3[i], expected3[i]) == 0);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edx,%edx\njle 1239 \npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %rsi,%rbp\nlea 0x1(%rdi),%r12\nlea -0x1(%rdx),%eax\nlea (%rax,%rax,4),%rax\nlea (%rax,%rax,4),%rax\nlea 0x64(%rsi,%rax,4),%r13\nmov $0x0,%r14d\njmp 1216 \nadd $0x1,%rcx\nmovzbl -0x1(%rcx),%ebx\ntest %bl,%bl\nje 1201 \nmovzbl %bl,%edx\nmov (%rax),%rsi\ntestb $0x8,0x1(%rsi,%rdx,2)\njne 11dc \nmovslq %edi,%rdx\nmov %bl,0x0(%rbp,%rdx,1)\nlea 0x1(%rdi),%edi\njmp 11dc \nmovslq %edi,%rdi\nmovb $0x0,0x0(%rbp,%rdi,1)\nadd $0x64,%rbp\nadd $0x64,%r12\ncmp %r13,%rbp\nje 1230 \nmovzbl -0x1(%r12),%ebx\nmov %r14d,%edi\ntest %bl,%bl\nje 1201 \ncallq 10b0 <__ctype_b_loc@plt>\nmov %r12,%rcx\nmov %r14d,%edi\njmp 11e8 \npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nretq\n", + "ida_asm": "func0:\nendbr64\ntest edx, edx\njle locret_1238\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbp, rsi\nlea r12, [rdi+1]\nmovsxd rdx, edx\nlea rax, [rdx+rdx*4]\nlea rax, [rax+rax*4]\nlea r13, [rsi+rax*4]\nmov r14d, 0\njmp short loc_1215\nloc_11DB:\nadd rcx, 1\nmovzx ebx, byte ptr [rcx-1]\ntest bl, bl\njz short loc_1200\nloc_11E7:\nmovzx edx, bl\nmov rsi, [rax]\ntest byte ptr [rsi+rdx*2+1], 8\njnz short loc_11DB\nmovsxd rdx, edi\nmov [rbp+rdx+0], bl\nlea edi, [rdi+1]\njmp short loc_11DB\nloc_1200:\nmovsxd rdi, edi\nmov byte ptr [rbp+rdi+0], 0\nadd rbp, 64h ; 'd'\nadd r12, 64h ; 'd'\ncmp rbp, r13\njz short loc_122F\nloc_1215:\nmovzx ebx, byte ptr [r12-1]\nmov edi, r14d\ntest bl, bl\njz short loc_1200\ncall ___ctype_b_loc\nmov rcx, r12\nmov edi, r14d\njmp short loc_11E7\nloc_122F:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nlocret_1238:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n __int64 v3; // rbp\n unsigned __int8 *v4; // r12\n __int64 v5; // r13\n unsigned __int8 *v6; // rcx\n unsigned __int8 v7; // bl\n int v8; // edi\n const unsigned __int16 **v9; // rax\n\n if ( a3 > 0 )\n {\n v3 = a2;\n v4 = (unsigned __int8 *)(a1 + 1);\n v5 = a2 + 100LL * a3;\n do\n {\n v7 = *(v4 - 1);\n v8 = 0;\n if ( v7 )\n {\n v9 = __ctype_b_loc();\n v6 = v4;\n v8 = 0;\n do\n {\n if ( ((*v9)[v7] & 0x800) == 0 )\n *(_BYTE *)(v3 + v8++) = v7;\n v7 = *v6++;\n }\n while ( v7 );\n }\n *(_BYTE *)(v3 + v8) = 0;\n v3 += 100LL;\n v4 += 100;\n }\n while ( v3 != v5 );\n }\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\ntest edx, edx\njle locret_1238\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbp, rsi\nlea r12, [rdi+1]\nmovsxd rdx, edx\nlea rax, [rdx+rdx*4]\nlea rax, [rax+rax*4]\nlea r13, [rsi+rax*4]\nmov r14d, 0\njmp short loc_1215\nloc_11DB:\nadd rcx, 1\nmovzx ebx, byte ptr [rcx-1]\ntest bl, bl\njz short loc_1200\nloc_11E7:\nmovzx edx, bl\nmov rsi, [rax]\ntest byte ptr [rsi+rdx*2+1], 8\njnz short loc_11DB\nmovsxd rdx, edi\nmov [rbp+rdx+0], bl\nlea edi, [rdi+1]\njmp short loc_11DB\nloc_1200:\nmovsxd rdi, edi\nmov byte ptr [rbp+rdi+0], 0\nadd rbp, 64h ; 'd'\nadd r12, 64h ; 'd'\ncmp rbp, r13\njz short loc_122F\nloc_1215:\nmovzx ebx, byte ptr [r12-1]\nmov edi, r14d\ntest bl, bl\njz short loc_1200\ncall ___ctype_b_loc\nmov rcx, r12\nmov edi, r14d\njmp short loc_11E7\nloc_122F:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nlocret_1238:\nretn", + "ida_strip_pseudo": "void __fastcall sub_11A9(__int64 a1, __int64 a2, int a3)\n{\n __int64 v3; // rbp\n unsigned __int8 *v4; // r12\n __int64 v5; // r13\n unsigned __int8 *v6; // rcx\n unsigned __int8 v7; // bl\n int v8; // edi\n const unsigned __int16 **v9; // rax\n\n if ( a3 > 0 )\n {\n v3 = a2;\n v4 = (unsigned __int8 *)(a1 + 1);\n v5 = a2 + 100LL * a3;\n do\n {\n v7 = *(v4 - 1);\n v8 = 0;\n if ( v7 )\n {\n v9 = __ctype_b_loc();\n v6 = v4;\n v8 = 0;\n do\n {\n if ( ((*v9)[v7] & 0x800) == 0 )\n *(_BYTE *)(v3 + v8++) = v7;\n v7 = *v6++;\n }\n while ( v7 );\n }\n *(_BYTE *)(v3 + v8) = 0;\n v3 += 100LL;\n v4 += 100;\n }\n while ( v3 != v5 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_11A9(long long a1, long long a2, int a3) {\n long long v3;\n unsigned char *v4;\n long long v5;\n unsigned char *v6;\n unsigned char v7;\n int v8;\n const unsigned short **v9;\n if (a3 > 0) {\n v3 = a2;\n v4 = (unsigned char *)(a1 + 1);\n v5 = a2 + 100LL * a3;\n do {\n v7 = *(v4 - 1);\n v8 = 0;\n if (v7) {\n v9 = __ctype_b_loc();\n v6 = v4;\n v8 = 0;\n do {\n if (((*v9)[v7] & 2048) == 0) *(uint8_t *)(v3 + v8++) = v7;\n v7 = *v6++;\n } while (v7);\n }\n *(uint8_t *)(v3 + v8) = 0;\n v3 += 100LL;\n v4 += 100;\n } while (v3 != v5);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, long long a2, int a3) {\n long long v3;\n unsigned char *v4;\n long long v5;\n unsigned char *v6;\n unsigned char v7;\n int v8;\n const unsigned short **v9;\n if (a3 > 0) {\n v3 = a2;\n v4 = (unsigned char *)(a1 + 1);\n v5 = a2 + 100LL * a3;\n do {\n v7 = *(v4 - 1);\n v8 = 0;\n if (v7) {\n v9 = __ctype_b_loc();\n v6 = v4;\n v8 = 0;\n do {\n if (((*v9)[v7] & 2048) == 0) *(uint8_t *)(v3 + v8++) = v7;\n v7 = *v6++;\n } while (v7);\n }\n *(uint8_t *)(v3 + v8) = 0;\n v3 += 100LL;\n v4 += 100;\n } while (v3 != v5);\n }\n}" + }, + { + "index": 27, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n#define MAX_STRINGS 3\n\n#define MAX_LENGTH 100\n\n\n\n", + "func": "void func0(char input[][MAX_LENGTH], char output[][MAX_LENGTH], int n) {\n for (int i = 0; i < n; i++) {\n int j = 0, k = 0;\n while (input[i][j] != '\\0') {\n if (!isdigit((unsigned char)input[i][j])) {\n output[i][k++] = input[i][j];\n }\n j++;\n }\n output[i][k] = '\\0';\n }\n}", + "test": "int main() {\n\n char input1[MAX_STRINGS][MAX_LENGTH] = {\"4words\", \"3letters\", \"4digits\"};\n\n char expected1[MAX_STRINGS][MAX_LENGTH] = {\"words\", \"letters\", \"digits\"};\n\n char output1[MAX_STRINGS][MAX_LENGTH];\n\n func0(input1, output1, MAX_STRINGS);\n\n for(int i = 0; i < MAX_STRINGS; i++) {\n\n assert(strcmp(output1[i], expected1[i]) == 0);\n\n }\n\n\n\n char input2[MAX_STRINGS][MAX_LENGTH] = {\"28Jan\", \"12Jan\", \"11Jan\"};\n\n char expected2[MAX_STRINGS][MAX_LENGTH] = {\"Jan\", \"Jan\", \"Jan\"};\n\n char output2[MAX_STRINGS][MAX_LENGTH];\n\n func0(input2, output2, MAX_STRINGS);\n\n for(int i = 0; i < MAX_STRINGS; i++) {\n\n assert(strcmp(output2[i], expected2[i]) == 0);\n\n }\n\n\n\n char input3[MAX_STRINGS][MAX_LENGTH] = {\"wonder1\", \"wonder2\", \"wonder3\"};\n\n char expected3[MAX_STRINGS][MAX_LENGTH] = {\"wonder\", \"wonder\", \"wonder\"};\n\n char output3[MAX_STRINGS][MAX_LENGTH];\n\n func0(input3, output3, MAX_STRINGS);\n\n for(int i = 0; i < MAX_STRINGS; i++) {\n\n assert(strcmp(output3[i], expected3[i]) == 0);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %edx,%edx\njle 14bb \npush %r13\nlea -0x1(%rdx),%eax\nlea 0x1(%rdi),%r13\npush %r12\nlea (%rax,%rax,4),%rax\nmov %rsi,%r12\npush %rbp\nlea (%rax,%rax,4),%rax\npush %rbx\nlea 0x65(%rdi,%rax,4),%rbp\nsub $0x8,%rsp\nnopl (%rax)\nmovzbl -0x1(%r13),%ebx\nxor %edi,%edi\ntest %bl,%bl\nje 149a \ncallq 10b0 <__ctype_b_loc@plt>\nmov %r13,%rcx\nxor %edi,%edi\nnopl (%rax)\nmov (%rax),%rsi\nmovzbl %bl,%edx\ntestb $0x8,0x1(%rsi,%rdx,2)\njne 148f \nmovslq %edi,%rdx\nadd $0x1,%edi\nmov %bl,(%r12,%rdx,1)\nmovzbl (%rcx),%ebx\nadd $0x1,%rcx\ntest %bl,%bl\njne 1478 \nmovslq %edi,%rdi\nadd $0x64,%r13\nadd $0x64,%r12\nmovb $0x0,-0x64(%r12,%rdi,1)\ncmp %rbp,%r13\njne 1460 \nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\ntest edx, edx\njle locret_145B\npush r13\nmovsxd rdx, edx\nlea r13, [rdi+1]\npush r12\nlea rax, [rdx+rdx*4]\nmov r12, rsi\npush rbp\nlea rax, [rax+rax*4]\npush rbx\nlea rbp, [rsi+rax*4]\nsub rsp, 8\nnop dword ptr [rax+00h]\nloc_1400:\nmovzx ebx, byte ptr [r13-1]\nxor edi, edi\ntest bl, bl\njz short loc_143A\ncall ___ctype_b_loc\nmov rcx, r13\nxor edi, edi\nnop dword ptr [rax]\nloc_1418:\nmov rsi, [rax]\nmovzx edx, bl\ntest byte ptr [rsi+rdx*2+1], 8\njnz short loc_142F\nmovsxd rdx, edi\nadd edi, 1\nmov [r12+rdx], bl\nloc_142F:\nmovzx ebx, byte ptr [rcx]\nadd rcx, 1\ntest bl, bl\njnz short loc_1418\nloc_143A:\nmovsxd rdi, edi\nadd r12, 64h ; 'd'\nadd r13, 64h ; 'd'\nmov byte ptr [r12+rdi-64h], 0\ncmp r12, rbp\njnz short loc_1400\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nlocret_145B:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n unsigned __int8 *v3; // r13\n __int64 v4; // r12\n __int64 v5; // rbp\n unsigned __int8 v6; // bl\n int v7; // edi\n const unsigned __int16 **v8; // rax\n unsigned __int8 *v9; // rcx\n __int64 v10; // rdx\n\n if ( a3 > 0 )\n {\n v3 = (unsigned __int8 *)(a1 + 1);\n v4 = a2;\n v5 = a2 + 100LL * a3;\n do\n {\n v6 = *(v3 - 1);\n v7 = 0;\n if ( v6 )\n {\n v8 = __ctype_b_loc();\n v9 = v3;\n v7 = 0;\n do\n {\n if ( ((*v8)[v6] & 0x800) == 0 )\n {\n v10 = v7++;\n *(_BYTE *)(v4 + v10) = v6;\n }\n v6 = *v9++;\n }\n while ( v6 );\n }\n v4 += 100LL;\n v3 += 100;\n *(_BYTE *)(v4 + v7 - 100) = 0;\n }\n while ( v4 != v5 );\n }\n}", + "ida_strip_asm": "sub_13D0:\nendbr64\ntest edx, edx\njle locret_145B\npush r13\nmovsxd rdx, edx\nlea r13, [rdi+1]\npush r12\nlea rax, [rdx+rdx*4]\nmov r12, rsi\npush rbp\nlea rax, [rax+rax*4]\npush rbx\nlea rbp, [rsi+rax*4]\nsub rsp, 8\nnop dword ptr [rax+00h]\nloc_1400:\nmovzx ebx, byte ptr [r13-1]\nxor edi, edi\ntest bl, bl\njz short loc_143A\ncall ___ctype_b_loc\nmov rcx, r13\nxor edi, edi\nnop dword ptr [rax]\nloc_1418:\nmov rsi, [rax]\nmovzx edx, bl\ntest byte ptr [rsi+rdx*2+1], 8\njnz short loc_142F\nmovsxd rdx, edi\nadd edi, 1\nmov [r12+rdx], bl\nloc_142F:\nmovzx ebx, byte ptr [rcx]\nadd rcx, 1\ntest bl, bl\njnz short loc_1418\nloc_143A:\nmovsxd rdi, edi\nadd r12, 64h ; 'd'\nadd r13, 64h ; 'd'\nmov byte ptr [r12+rdi-64h], 0\ncmp r12, rbp\njnz short loc_1400\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nlocret_145B:\nretn", + "ida_strip_pseudo": "void __fastcall sub_13D0(__int64 a1, __int64 a2, int a3)\n{\n unsigned __int8 *v3; // r13\n __int64 v4; // r12\n __int64 v5; // rbp\n unsigned __int8 v6; // bl\n int v7; // edi\n const unsigned __int16 **v8; // rax\n unsigned __int8 *v9; // rcx\n __int64 v10; // rdx\n\n if ( a3 > 0 )\n {\n v3 = (unsigned __int8 *)(a1 + 1);\n v4 = a2;\n v5 = a2 + 100LL * a3;\n do\n {\n v6 = *(v3 - 1);\n v7 = 0;\n if ( v6 )\n {\n v8 = __ctype_b_loc();\n v9 = v3;\n v7 = 0;\n do\n {\n if ( ((*v8)[v6] & 0x800) == 0 )\n {\n v10 = v7++;\n *(_BYTE *)(v4 + v10) = v6;\n }\n v6 = *v9++;\n }\n while ( v6 );\n }\n v4 += 100LL;\n v3 += 100;\n *(_BYTE *)(v4 + v7 - 100) = 0;\n }\n while ( v4 != v5 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_13D0(long long a1, long long a2, int a3) {\n unsigned char *v3;\n long long v4;\n long long v5;\n unsigned char v6;\n int v7;\n const unsigned short **v8;\n unsigned char *v9;\n long long v10;\n if (a3 > 0) {\n v3 = (unsigned char *)(a1 + 1);\n v4 = a2;\n v5 = a2 + 100LL * a3;\n do {\n v6 = *(v3 - 1);\n v7 = 0;\n if (v6) {\n v8 = __ctype_b_loc();\n v9 = v3;\n v7 = 0;\n do {\n if (((*v8)[v6] & 2048) == 0) {\n v10 = v7++;\n *(uint8_t *)(v4 + v10) = v6;\n }\n v6 = *v9++;\n } while (v6);\n }\n v4 += 100LL;\n v3 += 100;\n *(uint8_t *)(v4 + v7 - 100) = 0;\n } while (v4 != v5);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, long long a2, int a3) {\n unsigned char *v3;\n long long v4;\n long long v5;\n unsigned char v6;\n int v7;\n const unsigned short **v8;\n unsigned char *v9;\n long long v10;\n if (a3 > 0) {\n v3 = (unsigned char *)(a1 + 1);\n v4 = a2;\n v5 = a2 + 100LL * a3;\n do {\n v6 = *(v3 - 1);\n v7 = 0;\n if (v6) {\n v8 = __ctype_b_loc();\n v9 = v3;\n v7 = 0;\n do {\n if (((*v8)[v6] & 2048) == 0) {\n v10 = v7++;\n *(uint8_t *)(v4 + v10) = v6;\n }\n v6 = *v9++;\n } while (v6);\n }\n v4 += 100LL;\n v3 += 100;\n *(uint8_t *)(v4 + v7 - 100) = 0;\n } while (v4 != v5);\n }\n}" + }, + { + "index": 27, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n#define MAX_STRINGS 3\n\n#define MAX_LENGTH 100\n\n\n\n", + "func": "void func0(char input[][MAX_LENGTH], char output[][MAX_LENGTH], int n) {\n for (int i = 0; i < n; i++) {\n int j = 0, k = 0;\n while (input[i][j] != '\\0') {\n if (!isdigit((unsigned char)input[i][j])) {\n output[i][k++] = input[i][j];\n }\n j++;\n }\n output[i][k] = '\\0';\n }\n}", + "test": "int main() {\n\n char input1[MAX_STRINGS][MAX_LENGTH] = {\"4words\", \"3letters\", \"4digits\"};\n\n char expected1[MAX_STRINGS][MAX_LENGTH] = {\"words\", \"letters\", \"digits\"};\n\n char output1[MAX_STRINGS][MAX_LENGTH];\n\n func0(input1, output1, MAX_STRINGS);\n\n for(int i = 0; i < MAX_STRINGS; i++) {\n\n assert(strcmp(output1[i], expected1[i]) == 0);\n\n }\n\n\n\n char input2[MAX_STRINGS][MAX_LENGTH] = {\"28Jan\", \"12Jan\", \"11Jan\"};\n\n char expected2[MAX_STRINGS][MAX_LENGTH] = {\"Jan\", \"Jan\", \"Jan\"};\n\n char output2[MAX_STRINGS][MAX_LENGTH];\n\n func0(input2, output2, MAX_STRINGS);\n\n for(int i = 0; i < MAX_STRINGS; i++) {\n\n assert(strcmp(output2[i], expected2[i]) == 0);\n\n }\n\n\n\n char input3[MAX_STRINGS][MAX_LENGTH] = {\"wonder1\", \"wonder2\", \"wonder3\"};\n\n char expected3[MAX_STRINGS][MAX_LENGTH] = {\"wonder\", \"wonder\", \"wonder\"};\n\n char output3[MAX_STRINGS][MAX_LENGTH];\n\n func0(input3, output3, MAX_STRINGS);\n\n for(int i = 0; i < MAX_STRINGS; i++) {\n\n assert(strcmp(output3[i], expected3[i]) == 0);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ntest %edx,%edx\njle 14db \npush %r13\nlea -0x1(%rdx),%eax\nlea 0x1(%rdi),%r13\npush %r12\nlea (%rax,%rax,4),%rax\nmov %rsi,%r12\npush %rbp\nlea (%rax,%rax,4),%rax\npush %rbx\nlea 0x65(%rdi,%rax,4),%rbp\nsub $0x8,%rsp\nnopl (%rax)\nmovzbl -0x1(%r13),%ebx\nxor %esi,%esi\ntest %bl,%bl\nje 14ba \ncallq 10b0 <__ctype_b_loc@plt>\nmov %r13,%rdx\nxor %ecx,%ecx\nmov (%rax),%rdi\nnopl 0x0(%rax,%rax,1)\nmovzbl %bl,%esi\ntestb $0x8,0x1(%rdi,%rsi,2)\njne 14ad \nadd $0x1,%rdx\nmov %bl,(%r12,%rcx,1)\nlea 0x1(%rcx),%esi\nmovzbl -0x1(%rdx),%ebx\ntest %bl,%bl\nje 14ba \nmov (%rax),%rdi\nmovslq %esi,%rcx\nmovzbl %bl,%esi\ntestb $0x8,0x1(%rdi,%rsi,2)\nje 148a \nmovzbl (%rdx),%ebx\nadd $0x1,%rdx\ntest %bl,%bl\njne 1480 \nmov %ecx,%esi\nmovslq %esi,%rsi\nadd $0x64,%r13\nadd $0x64,%r12\nmovb $0x0,-0x64(%r12,%rsi,1)\ncmp %r13,%rbp\njne 1460 \nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\ntest edx, edx\njle locret_14CB\npush r13\nmovsxd rdx, edx\nlea r13, [rdi+1]\npush r12\nlea rax, [rdx+rdx*4]\nmov r12, rsi\npush rbp\nlea rax, [rax+rax*4]\npush rbx\nlea rbp, [rsi+rax*4]\nsub rsp, 8\nnop dword ptr [rax+00h]\nloc_1460:\nmovzx ebx, byte ptr [r13-1]\nxor ecx, ecx\ntest bl, bl\njz short loc_14AE\ncall ___ctype_b_loc\nmov rdx, r13\nxor ecx, ecx\njmp short loc_1496\nloc_1480:\nadd rdx, 1\nmov [r12+rcx], bl\nlea esi, [rcx+1]\nmovzx ebx, byte ptr [rdx-1]\nmovsxd rcx, esi\ntest bl, bl\njz short loc_14AE\nloc_1496:\nmov rdi, [rax]\nloc_1499:\nmovzx esi, bl\ntest byte ptr [rdi+rsi*2+1], 8\njz short loc_1480\nmovzx ebx, byte ptr [rdx]\nadd rdx, 1\ntest bl, bl\njnz short loc_1499\nloc_14AE:\nmov byte ptr [r12+rcx], 0\nadd r12, 64h ; 'd'\nadd r13, 64h ; 'd'\ncmp rbp, r12\njnz short loc_1460\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nlocret_14CB:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n unsigned __int8 *v3; // r13\n __int64 v4; // r12\n __int64 v5; // rbp\n unsigned __int8 v6; // bl\n __int64 v7; // rcx\n const unsigned __int16 **v8; // rax\n unsigned __int8 *v9; // rdx\n\n if ( a3 > 0 )\n {\n v3 = (unsigned __int8 *)(a1 + 1);\n v4 = a2;\n v5 = a2 + 100LL * a3;\n do\n {\n v6 = *(v3 - 1);\n v7 = 0LL;\n if ( v6 )\n {\n v8 = __ctype_b_loc();\n v9 = v3;\n v7 = 0LL;\n do\n {\n while ( ((*v8)[v6] & 0x800) == 0 )\n {\n ++v9;\n *(_BYTE *)(v4 + v7) = v6;\n v6 = *(v9 - 1);\n v7 = (int)v7 + 1;\n if ( !v6 )\n goto LABEL_8;\n }\n v6 = *v9++;\n }\n while ( v6 );\n }\nLABEL_8:\n *(_BYTE *)(v4 + v7) = 0;\n v4 += 100LL;\n v3 += 100;\n }\n while ( v5 != v4 );\n }\n}", + "ida_strip_asm": "sub_1430:\nendbr64\ntest edx, edx\njle locret_14CB\npush r13\nmovsxd rdx, edx\nlea r13, [rdi+1]\npush r12\nlea rax, [rdx+rdx*4]\nmov r12, rsi\npush rbp\nlea rax, [rax+rax*4]\npush rbx\nlea rbp, [rsi+rax*4]\nsub rsp, 8\nnop dword ptr [rax+00h]\nloc_1460:\nmovzx ebx, byte ptr [r13-1]\nxor ecx, ecx\ntest bl, bl\njz short loc_14AE\ncall ___ctype_b_loc\nmov rdx, r13\nxor ecx, ecx\njmp short loc_1496\nloc_1480:\nadd rdx, 1\nmov [r12+rcx], bl\nlea esi, [rcx+1]\nmovzx ebx, byte ptr [rdx-1]\nmovsxd rcx, esi\ntest bl, bl\njz short loc_14AE\nloc_1496:\nmov rdi, [rax]\nloc_1499:\nmovzx esi, bl\ntest byte ptr [rdi+rsi*2+1], 8\njz short loc_1480\nmovzx ebx, byte ptr [rdx]\nadd rdx, 1\ntest bl, bl\njnz short loc_1499\nloc_14AE:\nmov byte ptr [r12+rcx], 0\nadd r12, 64h ; 'd'\nadd r13, 64h ; 'd'\ncmp rbp, r12\njnz short loc_1460\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nlocret_14CB:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1430(__int64 a1, __int64 a2, int a3)\n{\n unsigned __int8 *v3; // r13\n __int64 v4; // r12\n __int64 v5; // rbp\n unsigned __int8 v6; // bl\n __int64 v7; // rcx\n const unsigned __int16 **v8; // rax\n unsigned __int8 *v9; // rdx\n\n if ( a3 > 0 )\n {\n v3 = (unsigned __int8 *)(a1 + 1);\n v4 = a2;\n v5 = a2 + 100LL * a3;\n do\n {\n v6 = *(v3 - 1);\n v7 = 0LL;\n if ( v6 )\n {\n v8 = __ctype_b_loc();\n v9 = v3;\n v7 = 0LL;\n do\n {\n while ( ((*v8)[v6] & 0x800) == 0 )\n {\n ++v9;\n *(_BYTE *)(v4 + v7) = v6;\n v6 = *(v9 - 1);\n v7 = (int)v7 + 1;\n if ( !v6 )\n goto LABEL_8;\n }\n v6 = *v9++;\n }\n while ( v6 );\n }\nLABEL_8:\n *(_BYTE *)(v4 + v7) = 0;\n v4 += 100LL;\n v3 += 100;\n }\n while ( v5 != v4 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1430(long long a1, long long a2, int a3) {\n unsigned char *v3;\n long long v4;\n long long v5;\n unsigned char v6;\n long long v7;\n const unsigned short **v8;\n unsigned char *v9;\n if (a3 > 0) {\n v3 = (unsigned char *)(a1 + 1);\n v4 = a2;\n v5 = a2 + 100LL * a3;\n do {\n v6 = *(v3 - 1);\n v7 = 0LL;\n if (v6) {\n v8 = __ctype_b_loc();\n v9 = v3;\n v7 = 0LL;\n do {\n while (((*v8)[v6] & 2048) == 0) {\n ++v9;\n *(uint8_t *)(v4 + v7) = v6;\n v6 = *(v9 - 1);\n v7 = (int)v7 + 1;\n if (!v6) goto LABEL_8;\n }\n v6 = *v9++;\n } while (v6);\n }\n LABEL_8:\n *(uint8_t *)(v4 + v7) = 0;\n v4 += 100LL;\n v3 += 100;\n } while (v5 != v4);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, long long a2, int a3) {\n unsigned char *v3;\n long long v4;\n long long v5;\n unsigned char v6;\n long long v7;\n const unsigned short **v8;\n unsigned char *v9;\n if (a3 > 0) {\n v3 = (unsigned char *)(a1 + 1);\n v4 = a2;\n v5 = a2 + 100LL * a3;\n do {\n v6 = *(v3 - 1);\n v7 = 0LL;\n if (v6) {\n v8 = __ctype_b_loc();\n v9 = v3;\n v7 = 0LL;\n do {\n while (((*v8)[v6] & 2048) == 0) {\n ++v9;\n *(uint8_t *)(v4 + v7) = v6;\n v6 = *(v9 - 1);\n v7 = (int)v7 + 1;\n if (!v6) goto LABEL_8;\n }\n v6 = *v9++;\n } while (v6);\n }\n LABEL_8:\n *(uint8_t *)(v4 + v7) = 0;\n v4 += 100LL;\n v3 += 100;\n } while (v5 != v4);\n }\n}" + }, + { + "index": 28, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int n, int k) {\n if (k > n) return 0;\n if (k == 0 || k == n) return 1;\n return func0(n - 1, k - 1) + func0(n - 1, k);\n}", + "test": "int main() {\n\n assert(func0(5, 2) == 10);\n\n assert(func0(4, 3) == 4);\n\n assert(func0(3, 2) == 3);\n\n assert(func0(14, 6) == 3003);\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x18,%rsp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov -0x18(%rbp),%eax\ncmp -0x14(%rbp),%eax\njle 116b \nmov $0x0,%eax\njmp 11ab \ncmpl $0x0,-0x18(%rbp)\nje 1179 \nmov -0x18(%rbp),%eax\ncmp -0x14(%rbp),%eax\njne 1180 \nmov $0x1,%eax\njmp 11ab \nmov -0x18(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x14(%rbp),%eax\nsub $0x1,%eax\nmov %edx,%esi\nmov %eax,%edi\ncallq 1149 \nmov %eax,%ebx\nmov -0x14(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x18(%rbp),%eax\nmov %eax,%esi\nmov %edx,%edi\ncallq 1149 \nadd %ebx,%eax\nadd $0x18,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 18h\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_14]\njle short loc_116B\nmov eax, 0\njmp short loc_11AB\nloc_116B:\ncmp [rbp+var_18], 0\njz short loc_1179\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_14]\njnz short loc_1180\nloc_1179:\nmov eax, 1\njmp short loc_11AB\nloc_1180:\nmov eax, [rbp+var_18]\nlea edx, [rax-1]\nmov eax, [rbp+var_14]\nsub eax, 1\nmov esi, edx\nmov edi, eax\ncall func0\nmov ebx, eax\nmov eax, [rbp+var_14]\nlea edx, [rax-1]\nmov eax, [rbp+var_18]\nmov esi, eax\nmov edi, edx\ncall func0\nadd eax, ebx\nloc_11AB:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, unsigned int a2)\n{\n int v3; // ebx\n\n if ( (int)a2 > a1 )\n return 0LL;\n if ( !a2 || a2 == a1 )\n return 1LL;\n v3 = func0((unsigned int)(a1 - 1), a2 - 1);\n return v3 + (unsigned int)func0((unsigned int)(a1 - 1), a2);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 18h\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_14]\njle short loc_116B\nmov eax, 0\njmp short loc_11AB\nloc_116B:\ncmp [rbp+var_18], 0\njz short loc_1179\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_14]\njnz short loc_1180\nloc_1179:\nmov eax, 1\njmp short loc_11AB\nloc_1180:\nmov eax, [rbp+var_18]\nlea edx, [rax-1]\nmov eax, [rbp+var_14]\nsub eax, 1\nmov esi, edx\nmov edi, eax\ncall sub_1149\nmov ebx, eax\nmov eax, [rbp+var_14]\nlea edx, [rax-1]\nmov eax, [rbp+var_18]\nmov esi, eax\nmov edi, edx\ncall sub_1149\nadd eax, ebx\nloc_11AB:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, unsigned int a2)\n{\n int v3; // ebx\n\n if ( (int)a2 > a1 )\n return 0LL;\n if ( !a2 || a2 == a1 )\n return 1LL;\n v3 = sub_1149((unsigned int)(a1 - 1), a2 - 1);\n return v3 + (unsigned int)sub_1149((unsigned int)(a1 - 1), a2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, unsigned int a2) {\n int v3;\n if ((int)a2 > a1) return 0LL;\n if (!a2 || a2 == a1) return 1LL;\n v3 = sub_1149((unsigned int)(a1 - 1), a2 - 1);\n return v3 + (unsigned int)sub_1149((unsigned int)(a1 - 1), a2);\n}", + "ida_pseudo_norm": "long long func0(int a1, unsigned int a2) {\n int v3;\n if ((int)a2 > a1) return 0LL;\n if (!a2 || a2 == a1) return 1LL;\n v3 = func0((unsigned int)(a1 - 1), a2 - 1);\n return v3 + (unsigned int)func0((unsigned int)(a1 - 1), a2);\n}" + }, + { + "index": 28, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int n, int k) {\n if (k > n) return 0;\n if (k == 0 || k == n) return 1;\n return func0(n - 1, k - 1) + func0(n - 1, k);\n}", + "test": "int main() {\n\n assert(func0(5, 2) == 10);\n\n assert(func0(4, 3) == 4);\n\n assert(func0(3, 2) == 3);\n\n assert(func0(14, 6) == 3003);\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x0,%eax\ncmp %edi,%esi\njg 118c \npush %r12\npush %rbp\npush %rbx\nmov %esi,%ebx\ntest %esi,%esi\nje 1182 \ncmp %edi,%esi\nje 1182 \nlea -0x1(%rdi),%ebp\nlea -0x1(%rsi),%esi\nmov %ebp,%edi\ncallq 1149 \nmov %eax,%r12d\nmov %ebx,%esi\nmov %ebp,%edi\ncallq 1149 \nadd %r12d,%eax\njmp 1187 \nmov $0x1,%eax\npop %rbx\npop %rbp\npop %r12\nretq\nretq\n", + "ida_asm": "func0:\nendbr64\nmov eax, 0\ncmp esi, edi\njg short locret_118C\npush r12\npush rbp\npush rbx\nmov ebx, esi\ntest esi, esi\njz short loc_1182\ncmp esi, edi\njz short loc_1182\nlea ebp, [rdi-1]\nlea esi, [rsi-1]\nmov edi, ebp\ncall func0\nmov r12d, eax\nmov esi, ebx\nmov edi, ebp\ncall func0\nadd eax, r12d\njmp short loc_1187\nloc_1182:\nmov eax, 1\nloc_1187:\npop rbx\npop rbp\npop r12\nretn\nlocret_118C:\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, unsigned int a2)\n{\n __int64 result; // rax\n int v3; // r12d\n\n result = 0LL;\n if ( (int)a2 <= a1 )\n {\n if ( !a2 || a2 == a1 )\n {\n return 1LL;\n }\n else\n {\n v3 = func0((unsigned int)(a1 - 1), a2 - 1);\n return v3 + (unsigned int)func0((unsigned int)(a1 - 1), a2);\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmov eax, 0\ncmp esi, edi\njg short locret_118C\npush r12\npush rbp\npush rbx\nmov ebx, esi\ntest esi, esi\njz short loc_1182\ncmp esi, edi\njz short loc_1182\nlea ebp, [rdi-1]\nlea esi, [rsi-1]\nmov edi, ebp\ncall sub_1149\nmov r12d, eax\nmov esi, ebx\nmov edi, ebp\ncall sub_1149\nadd eax, r12d\njmp short loc_1187\nloc_1182:\nmov eax, 1\nloc_1187:\npop rbx\npop rbp\npop r12\nretn\nlocret_118C:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, unsigned int a2)\n{\n __int64 result; // rax\n int v3; // r12d\n\n result = 0LL;\n if ( (int)a2 <= a1 )\n {\n if ( !a2 || a2 == a1 )\n {\n return 1LL;\n }\n else\n {\n v3 = sub_1149((unsigned int)(a1 - 1), a2 - 1);\n return v3 + (unsigned int)sub_1149((unsigned int)(a1 - 1), a2);\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, unsigned int a2) {\n long long result;\n int v3;\n result = 0LL;\n if ((int)a2 <= a1) {\n if (!a2 || a2 == a1) {\n return 1LL;\n } else {\n v3 = sub_1149((unsigned int)(a1 - 1), a2 - 1);\n return v3 + (unsigned int)sub_1149((unsigned int)(a1 - 1), a2);\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(int a1, unsigned int a2) {\n long long result;\n int v3;\n result = 0LL;\n if ((int)a2 <= a1) {\n if (!a2 || a2 == a1) {\n return 1LL;\n } else {\n v3 = func0((unsigned int)(a1 - 1), a2 - 1);\n return v3 + (unsigned int)func0((unsigned int)(a1 - 1), a2);\n }\n }\n return result;\n}" + }, + { + "index": 28, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int n, int k) {\n if (k > n) return 0;\n if (k == 0 || k == n) return 1;\n return func0(n - 1, k - 1) + func0(n - 1, k);\n}", + "test": "int main() {\n\n assert(func0(5, 2) == 10);\n\n assert(func0(4, 3) == 4);\n\n assert(func0(3, 2) == 3);\n\n assert(func0(14, 6) == 3003);\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\ncmp %esi,%edi\njl 1290 \nje 12a8 \nmov %esi,%ebp\ntest %esi,%esi\nje 12a8 \nmov %edi,%ebx\nlea -0x1(%rsi),%r13d\nxor %r12d,%r12d\nsub $0x1,%ebx\nmov %r13d,%esi\nmov %ebx,%edi\ncallq 1240 \nadd %eax,%r12d\ncmp %ebp,%ebx\njl 127d \njne 1263 \nadd $0x1,%r12d\nadd $0x8,%rsp\nmov %r12d,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax,%rax,1)\nadd $0x8,%rsp\nxor %r12d,%r12d\npop %rbx\nmov %r12d,%eax\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax)\nmov $0x1,%r12d\njmp 127d \n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 68h\ncmp edi, esi\njl loc_16CB\nmov r9d, esi\ntest esi, esi\njz loc_16D2\ncmp edi, esi\njz loc_16D2\nlea eax, [rsi-9]\nxor ebp, ebp\nmov ebx, edi\nmov [rsp+98h+var_6C], eax\nloc_1278:\nmov eax, ebx\nsub ebx, 1\ncmp r9d, eax\njg loc_158C\njz loc_16C3\ncmp r9d, 1\nlea edx, [r9-2]\nsetz cl\nxor r14d, r14d\ntest cl, cl\njnz loc_16C3\nmov [rsp+98h+var_68], ebp\nmov r13d, edx\nmov ebp, ebx\nloc_12AB:\nmov ecx, ebp\nsub ebp, 1\ncmp ebp, r13d\njl loc_1574\njz loc_16BA\ntest r13d, r13d\nlea eax, [r9-3]\nmov r15d, ebp\nsetz sil\nxor r12d, r12d\ntest sil, sil\njnz loc_16BA\nmov [rsp+98h+var_64], ecx\nmov [rsp+98h+var_5C], ebx\nmov [rsp+98h+var_60], r14d\nmov r14d, eax\nloc_12E9:\nsub r15d, 1\ncmp r15d, r14d\njl loc_1553\ntest r14d, r14d\njz loc_16B1\ncmp r15d, r14d\nlea ecx, [r9-4]\nsetz r10b\nxor ebx, ebx\ntest r10b, r10b\njnz loc_16B1\nmov [rsp+98h+var_50], r12d\nmov eax, r9d\nmov [rsp+98h+var_58], ebp\nmov ebp, r15d\nmov [rsp+98h+var_54], r15d\nmov r15d, r14d\nmov [rsp+98h+var_4C], r13d\nmov r13d, ecx\nloc_1334:\nsub ebp, 1\ncmp ebp, r13d\njl loc_1526\ntest r13d, r13d\njz loc_16A9\ncmp ebp, r13d\nlea ecx, [rax-5]\nsetz r14b\nxor r12d, r12d\ntest r14b, r14b\njnz loc_16A9\nmov [rsp+98h+var_48], ebp\nmov edx, eax\nmov [rsp+98h+var_44], ebx\nmov [rsp+98h+var_40], r15d\nmov [rsp+98h+var_88], r13d\nmov r13d, r12d\nloc_1376:\nsub ebp, 1\ncmp ebp, ecx\njl loc_14F8\ntest ecx, ecx\njz loc_1694\ncmp ebp, ecx\nlea r12d, [rdx-6]\nlea eax, [rdx-7]\nsetz sil\nxor r14d, r14d\ntest sil, sil\njnz loc_1694\nmov [rsp+98h+var_3C], ebp\nmov edi, r13d\nmov r13d, r12d\nloc_13AC:\nsub ebp, 1\ncmp ebp, r13d\njl loc_14E1\ntest r13d, r13d\njz loc_166A\nmov r12d, ebp\nxor ebx, ebx\nlea r9d, [rdx-8]\ncmp ebp, r13d\njz loc_166A\nmov esi, ebp\nmov ebp, r13d\nloc_13D8:\nsub r12d, 1\ncmp r12d, eax\njl loc_14C8\ntest eax, eax\njz loc_1662\nxor r15d, r15d\ncmp r12d, eax\njz loc_1662\nmov [rsp+98h+var_8C], r14d\nmov r11d, ebp\nmov r10d, ebx\nmov ebp, r12d\nmov [rsp+98h+var_90], eax\nmov eax, r12d\nmov r12d, r9d\nloc_1411:\nsub ebp, 1\ncmp ebp, r12d\njl loc_149F\ntest r12d, r12d\njz loc_16A0\nmov r13d, ebp\nxor ebx, ebx\ncmp ebp, r12d\njz loc_16A0\nmov [rsp+98h+var_84], r15d\nmov r14d, ebp\nmov r15d, r10d\nmov ebp, eax\nmov [rsp+98h+var_80], edi\nmov edi, r13d\nmov r13d, esi\nloc_144B:\nmov esi, [rsp+98h+var_6C]\nsub edi, 1\nmov [rsp+98h+var_70], edx\nmov [rsp+98h+var_74], r11d\nmov [rsp+98h+var_78], ecx\nmov [rsp+98h+var_7C], edi\ncall func0\nmov edi, [rsp+98h+var_7C]\nmov ecx, [rsp+98h+var_78]\nadd ebx, eax\nmov r11d, [rsp+98h+var_74]\nmov edx, [rsp+98h+var_70]\ncmp edi, r12d\njl loc_1678\njnz short loc_144B\nmov r10d, r15d\nmov r15d, [rsp+98h+var_84]\nmov edi, [rsp+98h+var_80]\nmov eax, ebp\nmov esi, r13d\nmov ebp, r14d\nlea r15d, [rbx+r15+1]\nloc_149F:\nmov ebx, [rsp+98h+var_90]\ncmp ebp, ebx\njl loc_15B0\njnz loc_1411\nmov r9d, r12d\nmov r14d, [rsp+98h+var_8C]\nmov r12d, eax\nmov eax, [rsp+98h+var_90]\nmov ebp, r11d\nlea ebx, [r10+r15+1]\nloc_14C8:\ncmp r12d, ebp\njl loc_15D1\nloc_14D1:\njnz loc_13D8\nmov r13d, ebp\nlea r14d, [r14+rbx+1]\nmov ebp, esi\nloc_14E1:\ncmp ebp, ecx\njl loc_15E1\nloc_14E9:\njnz loc_13AC\nmov ebp, [rsp+98h+var_3C]\nlea r13d, [r14+rdi+1]\nloc_14F8:\nmov eax, [rsp+98h+var_88]\ncmp ebp, eax\njl loc_15F7\nloc_1504:\njnz loc_1376\nmov ebx, [rsp+98h+var_44]\nmov r12d, r13d\nmov ebp, [rsp+98h+var_48]\nmov eax, edx\nmov r15d, [rsp+98h+var_40]\nmov r13d, [rsp+98h+var_88]\nlea ebx, [rbx+r12+1]\nloc_1526:\ncmp ebp, r15d\njl loc_1618\nloc_152F:\njnz loc_1334\nmov r12d, [rsp+98h+var_50]\nmov r14d, r15d\nmov ebp, [rsp+98h+var_58]\nmov r9d, eax\nmov r13d, [rsp+98h+var_4C]\nmov r15d, [rsp+98h+var_54]\nlea r12d, [r12+rbx+1]\nloc_1553:\ncmp r15d, r13d\njl loc_163D\nloc_155C:\njnz loc_12E9\nmov r14d, [rsp+98h+var_60]\nmov ecx, [rsp+98h+var_64]\nmov ebx, [rsp+98h+var_5C]\nlea r14d, [r14+r12+1]\nloc_1574:\ncmp r9d, ecx\njg loc_1656\nloc_157D:\njnz loc_12AB\nmov ebp, [rsp+98h+var_68]\nlea ebp, [r14+rbp+1]\nloc_158C:\ncmp ebx, r9d\njl short loc_159A\njnz loc_1278\nadd ebp, 1\nloc_159A:\nadd rsp, 68h\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15B0:\nmov ebx, r10d\nmov r9d, r12d\nmov ebp, r11d\nmov r12d, eax\nmov r14d, [rsp+98h+var_8C]\nmov eax, [rsp+98h+var_90]\nadd ebx, r15d\ncmp r12d, ebp\njge loc_14D1\nloc_15D1:\nmov r13d, ebp\nmov ebp, esi\nadd r14d, ebx\ncmp ebp, ecx\njge loc_14E9\nloc_15E1:\nmov ebp, [rsp+98h+var_3C]\nmov eax, [rsp+98h+var_88]\nmov r13d, edi\nadd r13d, r14d\ncmp ebp, eax\njge loc_1504\nloc_15F7:\nmov ebx, [rsp+98h+var_44]\nmov ebp, [rsp+98h+var_48]\nmov r12d, r13d\nmov r13d, eax\nmov r15d, [rsp+98h+var_40]\nmov eax, edx\nadd ebx, r12d\ncmp ebp, r15d\njge loc_152F\nloc_1618:\nmov r12d, [rsp+98h+var_50]\nmov r14d, r15d\nmov r13d, [rsp+98h+var_4C]\nmov r9d, eax\nmov r15d, [rsp+98h+var_54]\nmov ebp, [rsp+98h+var_58]\nadd r12d, ebx\ncmp r15d, r13d\njge loc_155C\nloc_163D:\nmov r14d, [rsp+98h+var_60]\nmov ecx, [rsp+98h+var_64]\nmov ebx, [rsp+98h+var_5C]\nadd r14d, r12d\ncmp r9d, ecx\njle loc_157D\nloc_1656:\nmov ebp, [rsp+98h+var_68]\nadd ebp, r14d\njmp loc_158C\nloc_1662:\nadd ebx, 1\njmp loc_14C8\nloc_166A:\nadd r14d, 1\njmp loc_14E1\nloc_1678:\nmov r10d, r15d\nmov r15d, [rsp+98h+var_84]\nmov eax, ebp\nmov edi, [rsp+98h+var_80]\nmov esi, r13d\nmov ebp, r14d\nadd r15d, ebx\njmp loc_149F\nloc_1694:\nadd r13d, 1\njmp loc_14F8\nloc_16A0:\nadd r15d, 1\njmp loc_149F\nloc_16A9:\nadd ebx, 1\njmp loc_1526\nloc_16B1:\nadd r12d, 1\njmp loc_1553\nloc_16BA:\nadd r14d, 1\njmp loc_1574\nloc_16C3:\nadd ebp, 1\njmp loc_158C\nloc_16CB:\nxor ebp, ebp\njmp loc_159A\nloc_16D2:\nmov ebp, 1\njmp loc_159A", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n int v2; // r9d\n unsigned int v3; // ebp\n int v4; // ebx\n int v5; // eax\n int v6; // r14d\n int v7; // r13d\n int v8; // ebp\n int v9; // ecx\n int v10; // r15d\n int v11; // r12d\n int v12; // r14d\n int v13; // ebx\n int v14; // eax\n int v15; // ebp\n int v16; // r15d\n int v17; // r13d\n int v18; // ecx\n int v19; // edx\n int v20; // r13d\n int v21; // eax\n int v22; // r14d\n int v23; // edi\n int v24; // r13d\n int v25; // r12d\n int v26; // ebx\n int v27; // r9d\n int v28; // esi\n int v29; // ebp\n int v30; // r15d\n int v31; // r11d\n int v32; // r10d\n int v33; // ebp\n int v34; // eax\n int v35; // r12d\n int v36; // r13d\n int v37; // ebx\n int v38; // r14d\n int v39; // r15d\n int v40; // ebp\n __int64 v41; // rdi\n int v42; // eax\n bool v43; // zf\n bool v44; // zf\n int v45; // eax\n bool v46; // zf\n int v47; // r12d\n bool v48; // zf\n bool v49; // zf\n bool v50; // zf\n int v52; // r12d\n int v53; // [rsp+8h] [rbp-90h]\n int v54; // [rsp+Ch] [rbp-8Ch]\n int v55; // [rsp+10h] [rbp-88h]\n int v56; // [rsp+14h] [rbp-84h]\n int v57; // [rsp+18h] [rbp-80h]\n int v58; // [rsp+20h] [rbp-78h]\n int v59; // [rsp+24h] [rbp-74h]\n int v60; // [rsp+28h] [rbp-70h]\n unsigned int v61; // [rsp+2Ch] [rbp-6Ch]\n unsigned int v62; // [rsp+30h] [rbp-68h]\n int v63; // [rsp+34h] [rbp-64h]\n int v64; // [rsp+38h] [rbp-60h]\n int v65; // [rsp+3Ch] [rbp-5Ch]\n int v66; // [rsp+40h] [rbp-58h]\n int v67; // [rsp+44h] [rbp-54h]\n int v68; // [rsp+48h] [rbp-50h]\n int v69; // [rsp+4Ch] [rbp-4Ch]\n int v70; // [rsp+50h] [rbp-48h]\n int v71; // [rsp+54h] [rbp-44h]\n int v72; // [rsp+58h] [rbp-40h]\n int v73; // [rsp+5Ch] [rbp-3Ch]\n\n if ( a1 < a2 )\n return 0;\n v2 = a2;\n if ( !a2 || a1 == a2 )\n return 1;\n v3 = 0;\n v4 = a1;\n v61 = a2 - 9;\n do\n {\n v5 = v4--;\n if ( v2 > v5 )\n goto LABEL_61;\n if ( v2 != v5 )\n {\n v6 = 0;\n if ( v2 != 1 )\n {\n v62 = v3;\n v7 = v2 - 2;\n v8 = v4;\n while ( 1 )\n {\n v9 = v8--;\n if ( v8 < v7 )\n goto LABEL_58;\n if ( v8 == v7 || (v10 = v8, v11 = 0, !v7) )\n {\n ++v6;\nLABEL_58:\n v50 = v2 == v9;\n if ( v2 > v9 )\n goto LABEL_71;\n goto LABEL_59;\n }\n v63 = v9;\n v65 = v4;\n v64 = v6;\n v12 = v2 - 3;\n while ( 1 )\n {\n if ( --v10 < v12 )\n goto LABEL_55;\n if ( !v12 || (v13 = 0, v10 == v12) )\n {\n ++v11;\nLABEL_55:\n v49 = v10 == v7;\n if ( v10 < v7 )\n break;\n goto LABEL_56;\n }\n v68 = v11;\n v14 = v2;\n v66 = v8;\n v15 = v10;\n v67 = v10;\n v16 = v12;\n v69 = v7;\n v17 = v2 - 4;\n while ( 1 )\n {\n if ( --v15 < v17 )\n goto LABEL_52;\n if ( !v17 || (v18 = v14 - 5, v15 == v17) )\n {\n ++v13;\nLABEL_52:\n v48 = v15 == v16;\n if ( v15 < v16 )\n break;\n goto LABEL_53;\n }\n v70 = v15;\n v19 = v14;\n v71 = v13;\n v72 = v16;\n v55 = v17;\n v20 = 0;\n while ( 1 )\n {\n if ( --v15 < v18 )\n goto LABEL_49;\n if ( !v18 || (v21 = v19 - 7, v22 = 0, v15 == v18) )\n {\n ++v20;\nLABEL_49:\n v45 = v55;\n v46 = v15 == v55;\n if ( v15 < v55 )\n break;\n goto LABEL_50;\n }\n v73 = v15;\n v23 = v20;\n v24 = v19 - 6;\n while ( 1 )\n {\n if ( --v15 < v24 )\n goto LABEL_46;\n if ( !v24 || (v25 = v15, v26 = 0, v27 = v19 - 8, v15 == v24) )\n {\n ++v22;\nLABEL_46:\n v44 = v15 == v18;\n if ( v15 < v18 )\n break;\n goto LABEL_47;\n }\n v28 = v15;\n v29 = v24;\n while ( 1 )\n {\n if ( --v25 < v21 )\n goto LABEL_43;\n if ( v21 )\n {\n v30 = 0;\n if ( v25 != v21 )\n break;\n }\n ++v26;\nLABEL_43:\n v43 = v25 == v29;\n if ( v25 < v29 )\n goto LABEL_66;\nLABEL_44:\n if ( v43 )\n {\n v24 = v29;\n v22 += v26 + 1;\n v15 = v28;\n goto LABEL_46;\n }\n }\n v54 = v22;\n v31 = v29;\n v32 = v26;\n v33 = v25;\n v53 = v21;\n v34 = v25;\n v35 = v27;\n while ( 1 )\n {\n if ( --v33 >= v35 )\n {\n if ( !v35 || (v36 = v33, v37 = 0, v33 == v35) )\n {\n ++v30;\n }\n else\n {\n v56 = v30;\n v38 = v33;\n v39 = v32;\n v40 = v34;\n v57 = v23;\n LODWORD(v41) = v36;\n while ( 1 )\n {\n v41 = (unsigned int)(v41 - 1);\n v60 = v19;\n v59 = v31;\n v58 = v18;\n v42 = func0(v41, v61);\n v18 = v58;\n v37 += v42;\n v31 = v59;\n v19 = v60;\n if ( (int)v41 < v35 )\n break;\n if ( (_DWORD)v41 == v35 )\n {\n v32 = v39;\n v23 = v57;\n v34 = v40;\n v33 = v38;\n v30 = v37 + v56 + 1;\n goto LABEL_40;\n }\n }\n v32 = v39;\n v34 = v40;\n v23 = v57;\n v33 = v38;\n v30 = v37 + v56;\n }\n }\nLABEL_40:\n if ( v33 < v53 )\n break;\n if ( v33 == v53 )\n {\n v27 = v35;\n v22 = v54;\n v25 = v34;\n v21 = v53;\n v29 = v31;\n v26 = v32 + v30 + 1;\n goto LABEL_43;\n }\n }\n v27 = v35;\n v29 = v31;\n v25 = v34;\n v22 = v54;\n v21 = v53;\n v26 = v30 + v32;\n v43 = v25 == v31;\n if ( v25 >= v31 )\n goto LABEL_44;\nLABEL_66:\n v24 = v29;\n v15 = v28;\n v22 += v26;\n v44 = v28 == v18;\n if ( v28 < v18 )\n break;\nLABEL_47:\n if ( v44 )\n {\n v15 = v73;\n v20 = v22 + v23 + 1;\n goto LABEL_49;\n }\n }\n v15 = v73;\n v45 = v55;\n v20 = v22 + v23;\n v46 = v73 == v55;\n if ( v73 < v55 )\n break;\nLABEL_50:\n if ( v46 )\n {\n v47 = v20;\n v15 = v70;\n v14 = v19;\n v16 = v72;\n v17 = v55;\n v13 = v71 + v47 + 1;\n goto LABEL_52;\n }\n }\n v15 = v70;\n v52 = v20;\n v17 = v45;\n v16 = v72;\n v14 = v19;\n v13 = v52 + v71;\n v48 = v70 == v72;\n if ( v70 < v72 )\n break;\nLABEL_53:\n if ( v48 )\n {\n v12 = v16;\n v8 = v66;\n v2 = v14;\n v7 = v69;\n v10 = v67;\n v11 = v68 + v13 + 1;\n goto LABEL_55;\n }\n }\n v12 = v16;\n v7 = v69;\n v2 = v14;\n v10 = v67;\n v8 = v66;\n v11 = v13 + v68;\n v49 = v67 == v69;\n if ( v67 < v69 )\n break;\nLABEL_56:\n if ( v49 )\n {\n v9 = v63;\n v4 = v65;\n v6 = v64 + v11 + 1;\n goto LABEL_58;\n }\n }\n v4 = v65;\n v6 = v11 + v64;\n v50 = v2 == v63;\n if ( v2 > v63 )\n {\nLABEL_71:\n v3 = v6 + v62;\n goto LABEL_61;\n }\nLABEL_59:\n if ( v50 )\n {\n v3 = v6 + v62 + 1;\n goto LABEL_61;\n }\n }\n }\n }\n ++v3;\nLABEL_61:\n if ( v4 < v2 )\n return v3;\n }\n while ( v4 != v2 );\n return ++v3;\n}", + "ida_strip_asm": "sub_1240:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 68h\ncmp edi, esi\njl loc_16CB\nmov r9d, esi\ntest esi, esi\njz loc_16D2\ncmp edi, esi\njz loc_16D2\nlea eax, [rsi-9]\nxor ebp, ebp\nmov ebx, edi\nmov [rsp+98h+var_6C], eax\nloc_1278:\nmov eax, ebx\nsub ebx, 1\ncmp r9d, eax\njg loc_158C\njz loc_16C3\ncmp r9d, 1\nlea edx, [r9-2]\nsetz cl\nxor r14d, r14d\ntest cl, cl\njnz loc_16C3\nmov [rsp+98h+var_68], ebp\nmov r13d, edx\nmov ebp, ebx\nloc_12AB:\nmov ecx, ebp\nsub ebp, 1\ncmp ebp, r13d\njl loc_1574\njz loc_16BA\ntest r13d, r13d\nlea eax, [r9-3]\nmov r15d, ebp\nsetz sil\nxor r12d, r12d\ntest sil, sil\njnz loc_16BA\nmov [rsp+98h+var_64], ecx\nmov [rsp+98h+var_5C], ebx\nmov [rsp+98h+var_60], r14d\nmov r14d, eax\nloc_12E9:\nsub r15d, 1\ncmp r15d, r14d\njl loc_1553\ntest r14d, r14d\njz loc_16B1\ncmp r15d, r14d\nlea ecx, [r9-4]\nsetz r10b\nxor ebx, ebx\ntest r10b, r10b\njnz loc_16B1\nmov [rsp+98h+var_50], r12d\nmov eax, r9d\nmov [rsp+98h+var_58], ebp\nmov ebp, r15d\nmov [rsp+98h+var_54], r15d\nmov r15d, r14d\nmov [rsp+98h+var_4C], r13d\nmov r13d, ecx\nloc_1334:\nsub ebp, 1\ncmp ebp, r13d\njl loc_1526\ntest r13d, r13d\njz loc_16A9\ncmp ebp, r13d\nlea ecx, [rax-5]\nsetz r14b\nxor r12d, r12d\ntest r14b, r14b\njnz loc_16A9\nmov [rsp+98h+var_48], ebp\nmov edx, eax\nmov [rsp+98h+var_44], ebx\nmov [rsp+98h+var_40], r15d\nmov [rsp+98h+var_88], r13d\nmov r13d, r12d\nloc_1376:\nsub ebp, 1\ncmp ebp, ecx\njl loc_14F8\ntest ecx, ecx\njz loc_1694\ncmp ebp, ecx\nlea r12d, [rdx-6]\nlea eax, [rdx-7]\nsetz sil\nxor r14d, r14d\ntest sil, sil\njnz loc_1694\nmov [rsp+98h+var_3C], ebp\nmov edi, r13d\nmov r13d, r12d\nloc_13AC:\nsub ebp, 1\ncmp ebp, r13d\njl loc_14E1\ntest r13d, r13d\njz loc_166A\nmov r12d, ebp\nxor ebx, ebx\nlea r9d, [rdx-8]\ncmp ebp, r13d\njz loc_166A\nmov esi, ebp\nmov ebp, r13d\nloc_13D8:\nsub r12d, 1\ncmp r12d, eax\njl loc_14C8\ntest eax, eax\njz loc_1662\nxor r15d, r15d\ncmp r12d, eax\njz loc_1662\nmov [rsp+98h+var_8C], r14d\nmov r11d, ebp\nmov r10d, ebx\nmov ebp, r12d\nmov [rsp+98h+var_90], eax\nmov eax, r12d\nmov r12d, r9d\nloc_1411:\nsub ebp, 1\ncmp ebp, r12d\njl loc_149F\ntest r12d, r12d\njz loc_16A0\nmov r13d, ebp\nxor ebx, ebx\ncmp ebp, r12d\njz loc_16A0\nmov [rsp+98h+var_84], r15d\nmov r14d, ebp\nmov r15d, r10d\nmov ebp, eax\nmov [rsp+98h+var_80], edi\nmov edi, r13d\nmov r13d, esi\nloc_144B:\nmov esi, [rsp+98h+var_6C]\nsub edi, 1\nmov [rsp+98h+var_70], edx\nmov [rsp+98h+var_74], r11d\nmov [rsp+98h+var_78], ecx\nmov [rsp+98h+var_7C], edi\ncall sub_1240\nmov edi, [rsp+98h+var_7C]\nmov ecx, [rsp+98h+var_78]\nadd ebx, eax\nmov r11d, [rsp+98h+var_74]\nmov edx, [rsp+98h+var_70]\ncmp edi, r12d\njl loc_1678\njnz short loc_144B\nmov r10d, r15d\nmov r15d, [rsp+98h+var_84]\nmov edi, [rsp+98h+var_80]\nmov eax, ebp\nmov esi, r13d\nmov ebp, r14d\nlea r15d, [rbx+r15+1]\nloc_149F:\nmov ebx, [rsp+98h+var_90]\ncmp ebp, ebx\njl loc_15B0\njnz loc_1411\nmov r9d, r12d\nmov r14d, [rsp+98h+var_8C]\nmov r12d, eax\nmov eax, [rsp+98h+var_90]\nmov ebp, r11d\nlea ebx, [r10+r15+1]\nloc_14C8:\ncmp r12d, ebp\njl loc_15D1\nloc_14D1:\njnz loc_13D8\nmov r13d, ebp\nlea r14d, [r14+rbx+1]\nmov ebp, esi\nloc_14E1:\ncmp ebp, ecx\njl loc_15E1\nloc_14E9:\njnz loc_13AC\nmov ebp, [rsp+98h+var_3C]\nlea r13d, [r14+rdi+1]\nloc_14F8:\nmov eax, [rsp+98h+var_88]\ncmp ebp, eax\njl loc_15F7\nloc_1504:\njnz loc_1376\nmov ebx, [rsp+98h+var_44]\nmov r12d, r13d\nmov ebp, [rsp+98h+var_48]\nmov eax, edx\nmov r15d, [rsp+98h+var_40]\nmov r13d, [rsp+98h+var_88]\nlea ebx, [rbx+r12+1]\nloc_1526:\ncmp ebp, r15d\njl loc_1618\nloc_152F:\njnz loc_1334\nmov r12d, [rsp+98h+var_50]\nmov r14d, r15d\nmov ebp, [rsp+98h+var_58]\nmov r9d, eax\nmov r13d, [rsp+98h+var_4C]\nmov r15d, [rsp+98h+var_54]\nlea r12d, [r12+rbx+1]\nloc_1553:\ncmp r15d, r13d\njl loc_163D\nloc_155C:\njnz loc_12E9\nmov r14d, [rsp+98h+var_60]\nmov ecx, [rsp+98h+var_64]\nmov ebx, [rsp+98h+var_5C]\nlea r14d, [r14+r12+1]\nloc_1574:\ncmp r9d, ecx\njg loc_1656\nloc_157D:\njnz loc_12AB\nmov ebp, [rsp+98h+var_68]\nlea ebp, [r14+rbp+1]\nloc_158C:\ncmp ebx, r9d\njl short loc_159A\njnz loc_1278\nadd ebp, 1\nloc_159A:\nadd rsp, 68h\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15B0:\nmov ebx, r10d\nmov r9d, r12d\nmov ebp, r11d\nmov r12d, eax\nmov r14d, [rsp+98h+var_8C]\nmov eax, [rsp+98h+var_90]\nadd ebx, r15d\ncmp r12d, ebp\njge loc_14D1\nloc_15D1:\nmov r13d, ebp\nmov ebp, esi\nadd r14d, ebx\ncmp ebp, ecx\njge loc_14E9\nloc_15E1:\nmov ebp, [rsp+98h+var_3C]\nmov eax, [rsp+98h+var_88]\nmov r13d, edi\nadd r13d, r14d\ncmp ebp, eax\njge loc_1504\nloc_15F7:\nmov ebx, [rsp+98h+var_44]\nmov ebp, [rsp+98h+var_48]\nmov r12d, r13d\nmov r13d, eax\nmov r15d, [rsp+98h+var_40]\nmov eax, edx\nadd ebx, r12d\ncmp ebp, r15d\njge loc_152F\nloc_1618:\nmov r12d, [rsp+98h+var_50]\nmov r14d, r15d\nmov r13d, [rsp+98h+var_4C]\nmov r9d, eax\nmov r15d, [rsp+98h+var_54]\nmov ebp, [rsp+98h+var_58]\nadd r12d, ebx\ncmp r15d, r13d\njge loc_155C\nloc_163D:\nmov r14d, [rsp+98h+var_60]\nmov ecx, [rsp+98h+var_64]\nmov ebx, [rsp+98h+var_5C]\nadd r14d, r12d\ncmp r9d, ecx\njle loc_157D\nloc_1656:\nmov ebp, [rsp+98h+var_68]\nadd ebp, r14d\njmp loc_158C\nloc_1662:\nadd ebx, 1\njmp loc_14C8\nloc_166A:\nadd r14d, 1\njmp loc_14E1\nloc_1678:\nmov r10d, r15d\nmov r15d, [rsp+98h+var_84]\nmov eax, ebp\nmov edi, [rsp+98h+var_80]\nmov esi, r13d\nmov ebp, r14d\nadd r15d, ebx\njmp loc_149F\nloc_1694:\nadd r13d, 1\njmp loc_14F8\nloc_16A0:\nadd r15d, 1\njmp loc_149F\nloc_16A9:\nadd ebx, 1\njmp loc_1526\nloc_16B1:\nadd r12d, 1\njmp loc_1553\nloc_16BA:\nadd r14d, 1\njmp loc_1574\nloc_16C3:\nadd ebp, 1\njmp loc_158C\nloc_16CB:\nxor ebp, ebp\njmp loc_159A\nloc_16D2:\nmov ebp, 1\njmp loc_159A", + "ida_strip_pseudo": "__int64 __fastcall sub_1240(int a1, int a2)\n{\n int v2; // r9d\n unsigned int v3; // ebp\n int v4; // ebx\n int v5; // eax\n int v6; // r14d\n int v7; // r13d\n int v8; // ebp\n int v9; // ecx\n int v10; // r15d\n int v11; // r12d\n int v12; // r14d\n int v13; // ebx\n int v14; // eax\n int v15; // ebp\n int v16; // r15d\n int v17; // r13d\n int v18; // ecx\n int v19; // edx\n int v20; // r13d\n int v21; // eax\n int v22; // r14d\n int v23; // edi\n int v24; // r13d\n int v25; // r12d\n int v26; // ebx\n int v27; // r9d\n int v28; // esi\n int v29; // ebp\n int v30; // r15d\n int v31; // r11d\n int v32; // r10d\n int v33; // ebp\n int v34; // eax\n int v35; // r12d\n int v36; // r13d\n int v37; // ebx\n int v38; // r14d\n int v39; // r15d\n int v40; // ebp\n __int64 v41; // rdi\n int v42; // eax\n bool v43; // zf\n bool v44; // zf\n int v45; // eax\n bool v46; // zf\n int v47; // r12d\n bool v48; // zf\n bool v49; // zf\n bool v50; // zf\n int v52; // r12d\n int v53; // [rsp+8h] [rbp-90h]\n int v54; // [rsp+Ch] [rbp-8Ch]\n int v55; // [rsp+10h] [rbp-88h]\n int v56; // [rsp+14h] [rbp-84h]\n int v57; // [rsp+18h] [rbp-80h]\n int v58; // [rsp+20h] [rbp-78h]\n int v59; // [rsp+24h] [rbp-74h]\n int v60; // [rsp+28h] [rbp-70h]\n unsigned int v61; // [rsp+2Ch] [rbp-6Ch]\n unsigned int v62; // [rsp+30h] [rbp-68h]\n int v63; // [rsp+34h] [rbp-64h]\n int v64; // [rsp+38h] [rbp-60h]\n int v65; // [rsp+3Ch] [rbp-5Ch]\n int v66; // [rsp+40h] [rbp-58h]\n int v67; // [rsp+44h] [rbp-54h]\n int v68; // [rsp+48h] [rbp-50h]\n int v69; // [rsp+4Ch] [rbp-4Ch]\n int v70; // [rsp+50h] [rbp-48h]\n int v71; // [rsp+54h] [rbp-44h]\n int v72; // [rsp+58h] [rbp-40h]\n int v73; // [rsp+5Ch] [rbp-3Ch]\n\n if ( a1 < a2 )\n return 0;\n v2 = a2;\n if ( !a2 || a1 == a2 )\n return 1;\n v3 = 0;\n v4 = a1;\n v61 = a2 - 9;\n do\n {\n v5 = v4--;\n if ( v2 > v5 )\n goto LABEL_61;\n if ( v2 != v5 )\n {\n v6 = 0;\n if ( v2 != 1 )\n {\n v62 = v3;\n v7 = v2 - 2;\n v8 = v4;\n while ( 1 )\n {\n v9 = v8--;\n if ( v8 < v7 )\n goto LABEL_58;\n if ( v8 == v7 || (v10 = v8, v11 = 0, !v7) )\n {\n ++v6;\nLABEL_58:\n v50 = v2 == v9;\n if ( v2 > v9 )\n goto LABEL_71;\n goto LABEL_59;\n }\n v63 = v9;\n v65 = v4;\n v64 = v6;\n v12 = v2 - 3;\n while ( 1 )\n {\n if ( --v10 < v12 )\n goto LABEL_55;\n if ( !v12 || (v13 = 0, v10 == v12) )\n {\n ++v11;\nLABEL_55:\n v49 = v10 == v7;\n if ( v10 < v7 )\n break;\n goto LABEL_56;\n }\n v68 = v11;\n v14 = v2;\n v66 = v8;\n v15 = v10;\n v67 = v10;\n v16 = v12;\n v69 = v7;\n v17 = v2 - 4;\n while ( 1 )\n {\n if ( --v15 < v17 )\n goto LABEL_52;\n if ( !v17 || (v18 = v14 - 5, v15 == v17) )\n {\n ++v13;\nLABEL_52:\n v48 = v15 == v16;\n if ( v15 < v16 )\n break;\n goto LABEL_53;\n }\n v70 = v15;\n v19 = v14;\n v71 = v13;\n v72 = v16;\n v55 = v17;\n v20 = 0;\n while ( 1 )\n {\n if ( --v15 < v18 )\n goto LABEL_49;\n if ( !v18 || (v21 = v19 - 7, v22 = 0, v15 == v18) )\n {\n ++v20;\nLABEL_49:\n v45 = v55;\n v46 = v15 == v55;\n if ( v15 < v55 )\n break;\n goto LABEL_50;\n }\n v73 = v15;\n v23 = v20;\n v24 = v19 - 6;\n while ( 1 )\n {\n if ( --v15 < v24 )\n goto LABEL_46;\n if ( !v24 || (v25 = v15, v26 = 0, v27 = v19 - 8, v15 == v24) )\n {\n ++v22;\nLABEL_46:\n v44 = v15 == v18;\n if ( v15 < v18 )\n break;\n goto LABEL_47;\n }\n v28 = v15;\n v29 = v24;\n while ( 1 )\n {\n if ( --v25 < v21 )\n goto LABEL_43;\n if ( v21 )\n {\n v30 = 0;\n if ( v25 != v21 )\n break;\n }\n ++v26;\nLABEL_43:\n v43 = v25 == v29;\n if ( v25 < v29 )\n goto LABEL_66;\nLABEL_44:\n if ( v43 )\n {\n v24 = v29;\n v22 += v26 + 1;\n v15 = v28;\n goto LABEL_46;\n }\n }\n v54 = v22;\n v31 = v29;\n v32 = v26;\n v33 = v25;\n v53 = v21;\n v34 = v25;\n v35 = v27;\n while ( 1 )\n {\n if ( --v33 >= v35 )\n {\n if ( !v35 || (v36 = v33, v37 = 0, v33 == v35) )\n {\n ++v30;\n }\n else\n {\n v56 = v30;\n v38 = v33;\n v39 = v32;\n v40 = v34;\n v57 = v23;\n LODWORD(v41) = v36;\n while ( 1 )\n {\n v41 = (unsigned int)(v41 - 1);\n v60 = v19;\n v59 = v31;\n v58 = v18;\n v42 = sub_1240(v41, v61);\n v18 = v58;\n v37 += v42;\n v31 = v59;\n v19 = v60;\n if ( (int)v41 < v35 )\n break;\n if ( (_DWORD)v41 == v35 )\n {\n v32 = v39;\n v23 = v57;\n v34 = v40;\n v33 = v38;\n v30 = v37 + v56 + 1;\n goto LABEL_40;\n }\n }\n v32 = v39;\n v34 = v40;\n v23 = v57;\n v33 = v38;\n v30 = v37 + v56;\n }\n }\nLABEL_40:\n if ( v33 < v53 )\n break;\n if ( v33 == v53 )\n {\n v27 = v35;\n v22 = v54;\n v25 = v34;\n v21 = v53;\n v29 = v31;\n v26 = v32 + v30 + 1;\n goto LABEL_43;\n }\n }\n v27 = v35;\n v29 = v31;\n v25 = v34;\n v22 = v54;\n v21 = v53;\n v26 = v30 + v32;\n v43 = v25 == v31;\n if ( v25 >= v31 )\n goto LABEL_44;\nLABEL_66:\n v24 = v29;\n v15 = v28;\n v22 += v26;\n v44 = v28 == v18;\n if ( v28 < v18 )\n break;\nLABEL_47:\n if ( v44 )\n {\n v15 = v73;\n v20 = v22 + v23 + 1;\n goto LABEL_49;\n }\n }\n v15 = v73;\n v45 = v55;\n v20 = v22 + v23;\n v46 = v73 == v55;\n if ( v73 < v55 )\n break;\nLABEL_50:\n if ( v46 )\n {\n v47 = v20;\n v15 = v70;\n v14 = v19;\n v16 = v72;\n v17 = v55;\n v13 = v71 + v47 + 1;\n goto LABEL_52;\n }\n }\n v15 = v70;\n v52 = v20;\n v17 = v45;\n v16 = v72;\n v14 = v19;\n v13 = v52 + v71;\n v48 = v70 == v72;\n if ( v70 < v72 )\n break;\nLABEL_53:\n if ( v48 )\n {\n v12 = v16;\n v8 = v66;\n v2 = v14;\n v7 = v69;\n v10 = v67;\n v11 = v68 + v13 + 1;\n goto LABEL_55;\n }\n }\n v12 = v16;\n v7 = v69;\n v2 = v14;\n v10 = v67;\n v8 = v66;\n v11 = v13 + v68;\n v49 = v67 == v69;\n if ( v67 < v69 )\n break;\nLABEL_56:\n if ( v49 )\n {\n v9 = v63;\n v4 = v65;\n v6 = v64 + v11 + 1;\n goto LABEL_58;\n }\n }\n v4 = v65;\n v6 = v11 + v64;\n v50 = v2 == v63;\n if ( v2 > v63 )\n {\nLABEL_71:\n v3 = v6 + v62;\n goto LABEL_61;\n }\nLABEL_59:\n if ( v50 )\n {\n v3 = v6 + v62 + 1;\n goto LABEL_61;\n }\n }\n }\n }\n ++v3;\nLABEL_61:\n if ( v4 < v2 )\n return v3;\n }\n while ( v4 != v2 );\n return ++v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1240(int a1, int a2) {\n int v2;\n unsigned int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n int v8;\n int v9;\n int v10;\n int v11;\n int v12;\n int v13;\n int v14;\n int v15;\n int v16;\n int v17;\n int v18;\n int v19;\n int v20;\n int v21;\n int v22;\n int v23;\n int v24;\n int v25;\n int v26;\n int v27;\n int v28;\n int v29;\n int v30;\n int v31;\n int v32;\n int v33;\n int v34;\n int v35;\n int v36;\n int v37;\n int v38;\n int v39;\n int v40;\n long long v41;\n int v42;\n bool v43;\n bool v44;\n int v45;\n bool v46;\n int v47;\n bool v48;\n bool v49;\n bool v50;\n int v52;\n int v53;\n int v54;\n int v55;\n int v56;\n int v57;\n int v58;\n int v59;\n int v60;\n unsigned int v61;\n unsigned int v62;\n int v63;\n int v64;\n int v65;\n int v66;\n int v67;\n int v68;\n int v69;\n int v70;\n int v71;\n int v72;\n int v73;\n if (a1 < a2) return 0;\n v2 = a2;\n if (!a2 || a1 == a2) return 1;\n v3 = 0;\n v4 = a1;\n v61 = a2 - 9;\n do {\n v5 = v4--;\n if (v2 > v5) goto LABEL_61;\n if (v2 != v5) {\n v6 = 0;\n if (v2 != 1) {\n v62 = v3;\n v7 = v2 - 2;\n v8 = v4;\n while (1) {\n v9 = v8--;\n if (v8 < v7) goto LABEL_58;\n if (v8 == v7 || (v10 = v8, v11 = 0, !v7)) {\n ++v6;\n LABEL_58:\n v50 = v2 == v9;\n if (v2 > v9) goto LABEL_71;\n goto LABEL_59;\n }\n v63 = v9;\n v65 = v4;\n v64 = v6;\n v12 = v2 - 3;\n while (1) {\n if (--v10 < v12) goto LABEL_55;\n if (!v12 || (v13 = 0, v10 == v12)) {\n ++v11;\n LABEL_55:\n v49 = v10 == v7;\n if (v10 < v7) break;\n goto LABEL_56;\n }\n v68 = v11;\n v14 = v2;\n v66 = v8;\n v15 = v10;\n v67 = v10;\n v16 = v12;\n v69 = v7;\n v17 = v2 - 4;\n while (1) {\n if (--v15 < v17) goto LABEL_52;\n if (!v17 || (v18 = v14 - 5, v15 == v17)) {\n ++v13;\n LABEL_52:\n v48 = v15 == v16;\n if (v15 < v16) break;\n goto LABEL_53;\n }\n v70 = v15;\n v19 = v14;\n v71 = v13;\n v72 = v16;\n v55 = v17;\n v20 = 0;\n while (1) {\n if (--v15 < v18) goto LABEL_49;\n if (!v18 || (v21 = v19 - 7, v22 = 0, v15 == v18)) {\n ++v20;\n LABEL_49:\n v45 = v55;\n v46 = v15 == v55;\n if (v15 < v55) break;\n goto LABEL_50;\n }\n v73 = v15;\n v23 = v20;\n v24 = v19 - 6;\n while (1) {\n if (--v15 < v24) goto LABEL_46;\n if (!v24 || (v25 = v15, v26 = 0, v27 = v19 - 8, v15 == v24)) {\n ++v22;\n LABEL_46:\n v44 = v15 == v18;\n if (v15 < v18) break;\n goto LABEL_47;\n }\n v28 = v15;\n v29 = v24;\n while (1) {\n if (--v25 < v21) goto LABEL_43;\n if (v21) {\n v30 = 0;\n if (v25 != v21) break;\n }\n ++v26;\n LABEL_43:\n v43 = v25 == v29;\n if (v25 < v29) goto LABEL_66;\n LABEL_44:\n if (v43) {\n v24 = v29;\n v22 += v26 + 1;\n v15 = v28;\n goto LABEL_46;\n }\n }\n v54 = v22;\n v31 = v29;\n v32 = v26;\n v33 = v25;\n v53 = v21;\n v34 = v25;\n v35 = v27;\n while (1) {\n if (--v33 >= v35) {\n if (!v35 || (v36 = v33, v37 = 0, v33 == v35)) {\n ++v30;\n } else {\n v56 = v30;\n v38 = v33;\n v39 = v32;\n v40 = v34;\n v57 = v23;\n LODWORD(v41) = v36;\n while (1) {\n v41 = (unsigned int)(v41 - 1);\n v60 = v19;\n v59 = v31;\n v58 = v18;\n v42 = sub_1240(v41, v61);\n v18 = v58;\n v37 += v42;\n v31 = v59;\n v19 = v60;\n if ((int)v41 < v35) break;\n if ((uint32_t)v41 == v35) {\n v32 = v39;\n v23 = v57;\n v34 = v40;\n v33 = v38;\n v30 = v37 + v56 + 1;\n goto LABEL_40;\n }\n }\n v32 = v39;\n v34 = v40;\n v23 = v57;\n v33 = v38;\n v30 = v37 + v56;\n }\n }\n LABEL_40:\n if (v33 < v53) break;\n if (v33 == v53) {\n v27 = v35;\n v22 = v54;\n v25 = v34;\n v21 = v53;\n v29 = v31;\n v26 = v32 + v30 + 1;\n goto LABEL_43;\n }\n }\n v27 = v35;\n v29 = v31;\n v25 = v34;\n v22 = v54;\n v21 = v53;\n v26 = v30 + v32;\n v43 = v25 == v31;\n if (v25 >= v31) goto LABEL_44;\n LABEL_66:\n v24 = v29;\n v15 = v28;\n v22 += v26;\n v44 = v28 == v18;\n if (v28 < v18) break;\n LABEL_47:\n if (v44) {\n v15 = v73;\n v20 = v22 + v23 + 1;\n goto LABEL_49;\n }\n }\n v15 = v73;\n v45 = v55;\n v20 = v22 + v23;\n v46 = v73 == v55;\n if (v73 < v55) break;\n LABEL_50:\n if (v46) {\n v47 = v20;\n v15 = v70;\n v14 = v19;\n v16 = v72;\n v17 = v55;\n v13 = v71 + v47 + 1;\n goto LABEL_52;\n }\n }\n v15 = v70;\n v52 = v20;\n v17 = v45;\n v16 = v72;\n v14 = v19;\n v13 = v52 + v71;\n v48 = v70 == v72;\n if (v70 < v72) break;\n LABEL_53:\n if (v48) {\n v12 = v16;\n v8 = v66;\n v2 = v14;\n v7 = v69;\n v10 = v67;\n v11 = v68 + v13 + 1;\n goto LABEL_55;\n }\n }\n v12 = v16;\n v7 = v69;\n v2 = v14;\n v10 = v67;\n v8 = v66;\n v11 = v13 + v68;\n v49 = v67 == v69;\n if (v67 < v69) break;\n LABEL_56:\n if (v49) {\n v9 = v63;\n v4 = v65;\n v6 = v64 + v11 + 1;\n goto LABEL_58;\n }\n }\n v4 = v65;\n v6 = v11 + v64;\n v50 = v2 == v63;\n if (v2 > v63) {\n LABEL_71:\n v3 = v6 + v62;\n goto LABEL_61;\n }\n LABEL_59:\n if (v50) {\n v3 = v6 + v62 + 1;\n goto LABEL_61;\n }\n }\n }\n }\n ++v3;\n LABEL_61:\n if (v4 < v2) return v3;\n } while (v4 != v2);\n return ++v3;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n int v2;\n unsigned int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n int v8;\n int v9;\n int v10;\n int v11;\n int v12;\n int v13;\n int v14;\n int v15;\n int v16;\n int v17;\n int v18;\n int v19;\n int v20;\n int v21;\n int v22;\n int v23;\n int v24;\n int v25;\n int v26;\n int v27;\n int v28;\n int v29;\n int v30;\n int v31;\n int v32;\n int v33;\n int v34;\n int v35;\n int v36;\n int v37;\n int v38;\n int v39;\n int v40;\n long long v41;\n int v42;\n bool v43;\n bool v44;\n int v45;\n bool v46;\n int v47;\n bool v48;\n bool v49;\n bool v50;\n int v52;\n int v53;\n int v54;\n int v55;\n int v56;\n int v57;\n int v58;\n int v59;\n int v60;\n unsigned int v61;\n unsigned int v62;\n int v63;\n int v64;\n int v65;\n int v66;\n int v67;\n int v68;\n int v69;\n int v70;\n int v71;\n int v72;\n int v73;\n if (a1 < a2) return 0;\n v2 = a2;\n if (!a2 || a1 == a2) return 1;\n v3 = 0;\n v4 = a1;\n v61 = a2 - 9;\n do {\n v5 = v4--;\n if (v2 > v5) goto LABEL_61;\n if (v2 != v5) {\n v6 = 0;\n if (v2 != 1) {\n v62 = v3;\n v7 = v2 - 2;\n v8 = v4;\n while (1) {\n v9 = v8--;\n if (v8 < v7) goto LABEL_58;\n if (v8 == v7 || (v10 = v8, v11 = 0, !v7)) {\n ++v6;\n LABEL_58:\n v50 = v2 == v9;\n if (v2 > v9) goto LABEL_71;\n goto LABEL_59;\n }\n v63 = v9;\n v65 = v4;\n v64 = v6;\n v12 = v2 - 3;\n while (1) {\n if (--v10 < v12) goto LABEL_55;\n if (!v12 || (v13 = 0, v10 == v12)) {\n ++v11;\n LABEL_55:\n v49 = v10 == v7;\n if (v10 < v7) break;\n goto LABEL_56;\n }\n v68 = v11;\n v14 = v2;\n v66 = v8;\n v15 = v10;\n v67 = v10;\n v16 = v12;\n v69 = v7;\n v17 = v2 - 4;\n while (1) {\n if (--v15 < v17) goto LABEL_52;\n if (!v17 || (v18 = v14 - 5, v15 == v17)) {\n ++v13;\n LABEL_52:\n v48 = v15 == v16;\n if (v15 < v16) break;\n goto LABEL_53;\n }\n v70 = v15;\n v19 = v14;\n v71 = v13;\n v72 = v16;\n v55 = v17;\n v20 = 0;\n while (1) {\n if (--v15 < v18) goto LABEL_49;\n if (!v18 || (v21 = v19 - 7, v22 = 0, v15 == v18)) {\n ++v20;\n LABEL_49:\n v45 = v55;\n v46 = v15 == v55;\n if (v15 < v55) break;\n goto LABEL_50;\n }\n v73 = v15;\n v23 = v20;\n v24 = v19 - 6;\n while (1) {\n if (--v15 < v24) goto LABEL_46;\n if (!v24 || (v25 = v15, v26 = 0, v27 = v19 - 8, v15 == v24)) {\n ++v22;\n LABEL_46:\n v44 = v15 == v18;\n if (v15 < v18) break;\n goto LABEL_47;\n }\n v28 = v15;\n v29 = v24;\n while (1) {\n if (--v25 < v21) goto LABEL_43;\n if (v21) {\n v30 = 0;\n if (v25 != v21) break;\n }\n ++v26;\n LABEL_43:\n v43 = v25 == v29;\n if (v25 < v29) goto LABEL_66;\n LABEL_44:\n if (v43) {\n v24 = v29;\n v22 += v26 + 1;\n v15 = v28;\n goto LABEL_46;\n }\n }\n v54 = v22;\n v31 = v29;\n v32 = v26;\n v33 = v25;\n v53 = v21;\n v34 = v25;\n v35 = v27;\n while (1) {\n if (--v33 >= v35) {\n if (!v35 || (v36 = v33, v37 = 0, v33 == v35)) {\n ++v30;\n } else {\n v56 = v30;\n v38 = v33;\n v39 = v32;\n v40 = v34;\n v57 = v23;\n LODWORD(v41) = v36;\n while (1) {\n v41 = (unsigned int)(v41 - 1);\n v60 = v19;\n v59 = v31;\n v58 = v18;\n v42 = func0(v41, v61);\n v18 = v58;\n v37 += v42;\n v31 = v59;\n v19 = v60;\n if ((int)v41 < v35) break;\n if ((uint32_t)v41 == v35) {\n v32 = v39;\n v23 = v57;\n v34 = v40;\n v33 = v38;\n v30 = v37 + v56 + 1;\n goto LABEL_40;\n }\n }\n v32 = v39;\n v34 = v40;\n v23 = v57;\n v33 = v38;\n v30 = v37 + v56;\n }\n }\n LABEL_40:\n if (v33 < v53) break;\n if (v33 == v53) {\n v27 = v35;\n v22 = v54;\n v25 = v34;\n v21 = v53;\n v29 = v31;\n v26 = v32 + v30 + 1;\n goto LABEL_43;\n }\n }\n v27 = v35;\n v29 = v31;\n v25 = v34;\n v22 = v54;\n v21 = v53;\n v26 = v30 + v32;\n v43 = v25 == v31;\n if (v25 >= v31) goto LABEL_44;\n LABEL_66:\n v24 = v29;\n v15 = v28;\n v22 += v26;\n v44 = v28 == v18;\n if (v28 < v18) break;\n LABEL_47:\n if (v44) {\n v15 = v73;\n v20 = v22 + v23 + 1;\n goto LABEL_49;\n }\n }\n v15 = v73;\n v45 = v55;\n v20 = v22 + v23;\n v46 = v73 == v55;\n if (v73 < v55) break;\n LABEL_50:\n if (v46) {\n v47 = v20;\n v15 = v70;\n v14 = v19;\n v16 = v72;\n v17 = v55;\n v13 = v71 + v47 + 1;\n goto LABEL_52;\n }\n }\n v15 = v70;\n v52 = v20;\n v17 = v45;\n v16 = v72;\n v14 = v19;\n v13 = v52 + v71;\n v48 = v70 == v72;\n if (v70 < v72) break;\n LABEL_53:\n if (v48) {\n v12 = v16;\n v8 = v66;\n v2 = v14;\n v7 = v69;\n v10 = v67;\n v11 = v68 + v13 + 1;\n goto LABEL_55;\n }\n }\n v12 = v16;\n v7 = v69;\n v2 = v14;\n v10 = v67;\n v8 = v66;\n v11 = v13 + v68;\n v49 = v67 == v69;\n if (v67 < v69) break;\n LABEL_56:\n if (v49) {\n v9 = v63;\n v4 = v65;\n v6 = v64 + v11 + 1;\n goto LABEL_58;\n }\n }\n v4 = v65;\n v6 = v11 + v64;\n v50 = v2 == v63;\n if (v2 > v63) {\n LABEL_71:\n v3 = v6 + v62;\n goto LABEL_61;\n }\n LABEL_59:\n if (v50) {\n v3 = v6 + v62 + 1;\n goto LABEL_61;\n }\n }\n }\n }\n ++v3;\n LABEL_61:\n if (v4 < v2) return v3;\n } while (v4 != v2);\n return ++v3;\n}" + }, + { + "index": 28, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int n, int k) {\n if (k > n) return 0;\n if (k == 0 || k == n) return 1;\n return func0(n - 1, k - 1) + func0(n - 1, k);\n}", + "test": "int main() {\n\n assert(func0(5, 2) == 10);\n\n assert(func0(4, 3) == 4);\n\n assert(func0(3, 2) == 3);\n\n assert(func0(14, 6) == 3003);\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\ncmp %esi,%edi\njl 1290 \nje 12a8 \nmov %esi,%ebp\ntest %esi,%esi\nje 12a8 \nmov %edi,%ebx\nlea -0x1(%rsi),%r13d\nxor %r12d,%r12d\nsub $0x1,%ebx\nmov %r13d,%esi\nmov %ebx,%edi\ncallq 1240 \nadd %eax,%r12d\ncmp %ebp,%ebx\njl 127d \njne 1263 \nadd $0x1,%r12d\nadd $0x8,%rsp\nmov %r12d,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax,%rax,1)\nadd $0x8,%rsp\nxor %r12d,%r12d\npop %rbx\nmov %r12d,%eax\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax)\nmov $0x1,%r12d\njmp 127d \n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 68h\ncmp edi, esi\njl loc_16CB\nmov r9d, esi\ntest esi, esi\njz loc_16D2\ncmp edi, esi\njz loc_16D2\nlea eax, [rsi-9]\nxor ebp, ebp\nmov ebx, edi\nmov [rsp+98h+var_6C], eax\nloc_1278:\nmov eax, ebx\nsub ebx, 1\ncmp r9d, eax\njg loc_158C\njz loc_16C3\ncmp r9d, 1\nlea edx, [r9-2]\nsetz cl\nxor r14d, r14d\ntest cl, cl\njnz loc_16C3\nmov [rsp+98h+var_68], ebp\nmov r13d, edx\nmov ebp, ebx\nloc_12AB:\nmov ecx, ebp\nsub ebp, 1\ncmp ebp, r13d\njl loc_1574\njz loc_16BA\ntest r13d, r13d\nlea eax, [r9-3]\nmov r15d, ebp\nsetz sil\nxor r12d, r12d\ntest sil, sil\njnz loc_16BA\nmov [rsp+98h+var_64], ecx\nmov [rsp+98h+var_5C], ebx\nmov [rsp+98h+var_60], r14d\nmov r14d, eax\nloc_12E9:\nsub r15d, 1\ncmp r15d, r14d\njl loc_1553\ntest r14d, r14d\njz loc_16B1\ncmp r15d, r14d\nlea ecx, [r9-4]\nsetz r10b\nxor ebx, ebx\ntest r10b, r10b\njnz loc_16B1\nmov [rsp+98h+var_50], r12d\nmov eax, r9d\nmov [rsp+98h+var_58], ebp\nmov ebp, r15d\nmov [rsp+98h+var_54], r15d\nmov r15d, r14d\nmov [rsp+98h+var_4C], r13d\nmov r13d, ecx\nloc_1334:\nsub ebp, 1\ncmp ebp, r13d\njl loc_1526\ntest r13d, r13d\njz loc_16A9\ncmp ebp, r13d\nlea ecx, [rax-5]\nsetz r14b\nxor r12d, r12d\ntest r14b, r14b\njnz loc_16A9\nmov [rsp+98h+var_48], ebp\nmov edx, eax\nmov [rsp+98h+var_44], ebx\nmov [rsp+98h+var_40], r15d\nmov [rsp+98h+var_88], r13d\nmov r13d, r12d\nloc_1376:\nsub ebp, 1\ncmp ebp, ecx\njl loc_14F8\ntest ecx, ecx\njz loc_1694\ncmp ebp, ecx\nlea r12d, [rdx-6]\nlea eax, [rdx-7]\nsetz sil\nxor r14d, r14d\ntest sil, sil\njnz loc_1694\nmov [rsp+98h+var_3C], ebp\nmov edi, r13d\nmov r13d, r12d\nloc_13AC:\nsub ebp, 1\ncmp ebp, r13d\njl loc_14E1\ntest r13d, r13d\njz loc_166A\nmov r12d, ebp\nxor ebx, ebx\nlea r9d, [rdx-8]\ncmp ebp, r13d\njz loc_166A\nmov esi, ebp\nmov ebp, r13d\nloc_13D8:\nsub r12d, 1\ncmp r12d, eax\njl loc_14C8\ntest eax, eax\njz loc_1662\nxor r15d, r15d\ncmp r12d, eax\njz loc_1662\nmov [rsp+98h+var_8C], r14d\nmov r11d, ebp\nmov r10d, ebx\nmov ebp, r12d\nmov [rsp+98h+var_90], eax\nmov eax, r12d\nmov r12d, r9d\nloc_1411:\nsub ebp, 1\ncmp ebp, r12d\njl loc_149F\ntest r12d, r12d\njz loc_16A0\nmov r13d, ebp\nxor ebx, ebx\ncmp ebp, r12d\njz loc_16A0\nmov [rsp+98h+var_84], r15d\nmov r14d, ebp\nmov r15d, r10d\nmov ebp, eax\nmov [rsp+98h+var_80], edi\nmov edi, r13d\nmov r13d, esi\nloc_144B:\nmov esi, [rsp+98h+var_6C]\nsub edi, 1\nmov [rsp+98h+var_70], edx\nmov [rsp+98h+var_74], r11d\nmov [rsp+98h+var_78], ecx\nmov [rsp+98h+var_7C], edi\ncall func0\nmov edi, [rsp+98h+var_7C]\nmov ecx, [rsp+98h+var_78]\nadd ebx, eax\nmov r11d, [rsp+98h+var_74]\nmov edx, [rsp+98h+var_70]\ncmp edi, r12d\njl loc_1678\njnz short loc_144B\nmov r10d, r15d\nmov r15d, [rsp+98h+var_84]\nmov edi, [rsp+98h+var_80]\nmov eax, ebp\nmov esi, r13d\nmov ebp, r14d\nlea r15d, [rbx+r15+1]\nloc_149F:\nmov ebx, [rsp+98h+var_90]\ncmp ebp, ebx\njl loc_15B0\njnz loc_1411\nmov r9d, r12d\nmov r14d, [rsp+98h+var_8C]\nmov r12d, eax\nmov eax, [rsp+98h+var_90]\nmov ebp, r11d\nlea ebx, [r10+r15+1]\nloc_14C8:\ncmp r12d, ebp\njl loc_15D1\nloc_14D1:\njnz loc_13D8\nmov r13d, ebp\nlea r14d, [r14+rbx+1]\nmov ebp, esi\nloc_14E1:\ncmp ebp, ecx\njl loc_15E1\nloc_14E9:\njnz loc_13AC\nmov ebp, [rsp+98h+var_3C]\nlea r13d, [r14+rdi+1]\nloc_14F8:\nmov eax, [rsp+98h+var_88]\ncmp ebp, eax\njl loc_15F7\nloc_1504:\njnz loc_1376\nmov ebx, [rsp+98h+var_44]\nmov r12d, r13d\nmov ebp, [rsp+98h+var_48]\nmov eax, edx\nmov r15d, [rsp+98h+var_40]\nmov r13d, [rsp+98h+var_88]\nlea ebx, [rbx+r12+1]\nloc_1526:\ncmp ebp, r15d\njl loc_1618\nloc_152F:\njnz loc_1334\nmov r12d, [rsp+98h+var_50]\nmov r14d, r15d\nmov ebp, [rsp+98h+var_58]\nmov r9d, eax\nmov r13d, [rsp+98h+var_4C]\nmov r15d, [rsp+98h+var_54]\nlea r12d, [r12+rbx+1]\nloc_1553:\ncmp r15d, r13d\njl loc_163D\nloc_155C:\njnz loc_12E9\nmov r14d, [rsp+98h+var_60]\nmov ecx, [rsp+98h+var_64]\nmov ebx, [rsp+98h+var_5C]\nlea r14d, [r14+r12+1]\nloc_1574:\ncmp r9d, ecx\njg loc_1656\nloc_157D:\njnz loc_12AB\nmov ebp, [rsp+98h+var_68]\nlea ebp, [r14+rbp+1]\nloc_158C:\ncmp ebx, r9d\njl short loc_159A\njnz loc_1278\nadd ebp, 1\nloc_159A:\nadd rsp, 68h\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15B0:\nmov ebx, r10d\nmov r9d, r12d\nmov ebp, r11d\nmov r12d, eax\nmov r14d, [rsp+98h+var_8C]\nmov eax, [rsp+98h+var_90]\nadd ebx, r15d\ncmp r12d, ebp\njge loc_14D1\nloc_15D1:\nmov r13d, ebp\nmov ebp, esi\nadd r14d, ebx\ncmp ebp, ecx\njge loc_14E9\nloc_15E1:\nmov ebp, [rsp+98h+var_3C]\nmov eax, [rsp+98h+var_88]\nmov r13d, edi\nadd r13d, r14d\ncmp ebp, eax\njge loc_1504\nloc_15F7:\nmov ebx, [rsp+98h+var_44]\nmov ebp, [rsp+98h+var_48]\nmov r12d, r13d\nmov r13d, eax\nmov r15d, [rsp+98h+var_40]\nmov eax, edx\nadd ebx, r12d\ncmp ebp, r15d\njge loc_152F\nloc_1618:\nmov r12d, [rsp+98h+var_50]\nmov r14d, r15d\nmov r13d, [rsp+98h+var_4C]\nmov r9d, eax\nmov r15d, [rsp+98h+var_54]\nmov ebp, [rsp+98h+var_58]\nadd r12d, ebx\ncmp r15d, r13d\njge loc_155C\nloc_163D:\nmov r14d, [rsp+98h+var_60]\nmov ecx, [rsp+98h+var_64]\nmov ebx, [rsp+98h+var_5C]\nadd r14d, r12d\ncmp r9d, ecx\njle loc_157D\nloc_1656:\nmov ebp, [rsp+98h+var_68]\nadd ebp, r14d\njmp loc_158C\nloc_1662:\nadd ebx, 1\njmp loc_14C8\nloc_166A:\nadd r14d, 1\njmp loc_14E1\nloc_1678:\nmov r10d, r15d\nmov r15d, [rsp+98h+var_84]\nmov eax, ebp\nmov edi, [rsp+98h+var_80]\nmov esi, r13d\nmov ebp, r14d\nadd r15d, ebx\njmp loc_149F\nloc_1694:\nadd r13d, 1\njmp loc_14F8\nloc_16A0:\nadd r15d, 1\njmp loc_149F\nloc_16A9:\nadd ebx, 1\njmp loc_1526\nloc_16B1:\nadd r12d, 1\njmp loc_1553\nloc_16BA:\nadd r14d, 1\njmp loc_1574\nloc_16C3:\nadd ebp, 1\njmp loc_158C\nloc_16CB:\nxor ebp, ebp\njmp loc_159A\nloc_16D2:\nmov ebp, 1\njmp loc_159A", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n int v2; // r9d\n unsigned int v3; // ebp\n int v4; // ebx\n int v5; // eax\n int v6; // r14d\n int v7; // r13d\n int v8; // ebp\n int v9; // ecx\n int v10; // r15d\n int v11; // r12d\n int v12; // r14d\n int v13; // ebx\n int v14; // eax\n int v15; // ebp\n int v16; // r15d\n int v17; // r13d\n int v18; // ecx\n int v19; // edx\n int v20; // r13d\n int v21; // eax\n int v22; // r14d\n int v23; // edi\n int v24; // r13d\n int v25; // r12d\n int v26; // ebx\n int v27; // r9d\n int v28; // esi\n int v29; // ebp\n int v30; // r15d\n int v31; // r11d\n int v32; // r10d\n int v33; // ebp\n int v34; // eax\n int v35; // r12d\n int v36; // r13d\n int v37; // ebx\n int v38; // r14d\n int v39; // r15d\n int v40; // ebp\n __int64 v41; // rdi\n int v42; // eax\n bool v43; // zf\n bool v44; // zf\n int v45; // eax\n bool v46; // zf\n int v47; // r12d\n bool v48; // zf\n bool v49; // zf\n bool v50; // zf\n int v52; // r12d\n int v53; // [rsp+8h] [rbp-90h]\n int v54; // [rsp+Ch] [rbp-8Ch]\n int v55; // [rsp+10h] [rbp-88h]\n int v56; // [rsp+14h] [rbp-84h]\n int v57; // [rsp+18h] [rbp-80h]\n int v58; // [rsp+20h] [rbp-78h]\n int v59; // [rsp+24h] [rbp-74h]\n int v60; // [rsp+28h] [rbp-70h]\n unsigned int v61; // [rsp+2Ch] [rbp-6Ch]\n unsigned int v62; // [rsp+30h] [rbp-68h]\n int v63; // [rsp+34h] [rbp-64h]\n int v64; // [rsp+38h] [rbp-60h]\n int v65; // [rsp+3Ch] [rbp-5Ch]\n int v66; // [rsp+40h] [rbp-58h]\n int v67; // [rsp+44h] [rbp-54h]\n int v68; // [rsp+48h] [rbp-50h]\n int v69; // [rsp+4Ch] [rbp-4Ch]\n int v70; // [rsp+50h] [rbp-48h]\n int v71; // [rsp+54h] [rbp-44h]\n int v72; // [rsp+58h] [rbp-40h]\n int v73; // [rsp+5Ch] [rbp-3Ch]\n\n if ( a1 < a2 )\n return 0;\n v2 = a2;\n if ( !a2 || a1 == a2 )\n return 1;\n v3 = 0;\n v4 = a1;\n v61 = a2 - 9;\n do\n {\n v5 = v4--;\n if ( v2 > v5 )\n goto LABEL_61;\n if ( v2 != v5 )\n {\n v6 = 0;\n if ( v2 != 1 )\n {\n v62 = v3;\n v7 = v2 - 2;\n v8 = v4;\n while ( 1 )\n {\n v9 = v8--;\n if ( v8 < v7 )\n goto LABEL_58;\n if ( v8 == v7 || (v10 = v8, v11 = 0, !v7) )\n {\n ++v6;\nLABEL_58:\n v50 = v2 == v9;\n if ( v2 > v9 )\n goto LABEL_71;\n goto LABEL_59;\n }\n v63 = v9;\n v65 = v4;\n v64 = v6;\n v12 = v2 - 3;\n while ( 1 )\n {\n if ( --v10 < v12 )\n goto LABEL_55;\n if ( !v12 || (v13 = 0, v10 == v12) )\n {\n ++v11;\nLABEL_55:\n v49 = v10 == v7;\n if ( v10 < v7 )\n break;\n goto LABEL_56;\n }\n v68 = v11;\n v14 = v2;\n v66 = v8;\n v15 = v10;\n v67 = v10;\n v16 = v12;\n v69 = v7;\n v17 = v2 - 4;\n while ( 1 )\n {\n if ( --v15 < v17 )\n goto LABEL_52;\n if ( !v17 || (v18 = v14 - 5, v15 == v17) )\n {\n ++v13;\nLABEL_52:\n v48 = v15 == v16;\n if ( v15 < v16 )\n break;\n goto LABEL_53;\n }\n v70 = v15;\n v19 = v14;\n v71 = v13;\n v72 = v16;\n v55 = v17;\n v20 = 0;\n while ( 1 )\n {\n if ( --v15 < v18 )\n goto LABEL_49;\n if ( !v18 || (v21 = v19 - 7, v22 = 0, v15 == v18) )\n {\n ++v20;\nLABEL_49:\n v45 = v55;\n v46 = v15 == v55;\n if ( v15 < v55 )\n break;\n goto LABEL_50;\n }\n v73 = v15;\n v23 = v20;\n v24 = v19 - 6;\n while ( 1 )\n {\n if ( --v15 < v24 )\n goto LABEL_46;\n if ( !v24 || (v25 = v15, v26 = 0, v27 = v19 - 8, v15 == v24) )\n {\n ++v22;\nLABEL_46:\n v44 = v15 == v18;\n if ( v15 < v18 )\n break;\n goto LABEL_47;\n }\n v28 = v15;\n v29 = v24;\n while ( 1 )\n {\n if ( --v25 < v21 )\n goto LABEL_43;\n if ( v21 )\n {\n v30 = 0;\n if ( v25 != v21 )\n break;\n }\n ++v26;\nLABEL_43:\n v43 = v25 == v29;\n if ( v25 < v29 )\n goto LABEL_66;\nLABEL_44:\n if ( v43 )\n {\n v24 = v29;\n v22 += v26 + 1;\n v15 = v28;\n goto LABEL_46;\n }\n }\n v54 = v22;\n v31 = v29;\n v32 = v26;\n v33 = v25;\n v53 = v21;\n v34 = v25;\n v35 = v27;\n while ( 1 )\n {\n if ( --v33 >= v35 )\n {\n if ( !v35 || (v36 = v33, v37 = 0, v33 == v35) )\n {\n ++v30;\n }\n else\n {\n v56 = v30;\n v38 = v33;\n v39 = v32;\n v40 = v34;\n v57 = v23;\n LODWORD(v41) = v36;\n while ( 1 )\n {\n v41 = (unsigned int)(v41 - 1);\n v60 = v19;\n v59 = v31;\n v58 = v18;\n v42 = func0(v41, v61);\n v18 = v58;\n v37 += v42;\n v31 = v59;\n v19 = v60;\n if ( (int)v41 < v35 )\n break;\n if ( (_DWORD)v41 == v35 )\n {\n v32 = v39;\n v23 = v57;\n v34 = v40;\n v33 = v38;\n v30 = v37 + v56 + 1;\n goto LABEL_40;\n }\n }\n v32 = v39;\n v34 = v40;\n v23 = v57;\n v33 = v38;\n v30 = v37 + v56;\n }\n }\nLABEL_40:\n if ( v33 < v53 )\n break;\n if ( v33 == v53 )\n {\n v27 = v35;\n v22 = v54;\n v25 = v34;\n v21 = v53;\n v29 = v31;\n v26 = v32 + v30 + 1;\n goto LABEL_43;\n }\n }\n v27 = v35;\n v29 = v31;\n v25 = v34;\n v22 = v54;\n v21 = v53;\n v26 = v30 + v32;\n v43 = v25 == v31;\n if ( v25 >= v31 )\n goto LABEL_44;\nLABEL_66:\n v24 = v29;\n v15 = v28;\n v22 += v26;\n v44 = v28 == v18;\n if ( v28 < v18 )\n break;\nLABEL_47:\n if ( v44 )\n {\n v15 = v73;\n v20 = v22 + v23 + 1;\n goto LABEL_49;\n }\n }\n v15 = v73;\n v45 = v55;\n v20 = v22 + v23;\n v46 = v73 == v55;\n if ( v73 < v55 )\n break;\nLABEL_50:\n if ( v46 )\n {\n v47 = v20;\n v15 = v70;\n v14 = v19;\n v16 = v72;\n v17 = v55;\n v13 = v71 + v47 + 1;\n goto LABEL_52;\n }\n }\n v15 = v70;\n v52 = v20;\n v17 = v45;\n v16 = v72;\n v14 = v19;\n v13 = v52 + v71;\n v48 = v70 == v72;\n if ( v70 < v72 )\n break;\nLABEL_53:\n if ( v48 )\n {\n v12 = v16;\n v8 = v66;\n v2 = v14;\n v7 = v69;\n v10 = v67;\n v11 = v68 + v13 + 1;\n goto LABEL_55;\n }\n }\n v12 = v16;\n v7 = v69;\n v2 = v14;\n v10 = v67;\n v8 = v66;\n v11 = v13 + v68;\n v49 = v67 == v69;\n if ( v67 < v69 )\n break;\nLABEL_56:\n if ( v49 )\n {\n v9 = v63;\n v4 = v65;\n v6 = v64 + v11 + 1;\n goto LABEL_58;\n }\n }\n v4 = v65;\n v6 = v11 + v64;\n v50 = v2 == v63;\n if ( v2 > v63 )\n {\nLABEL_71:\n v3 = v6 + v62;\n goto LABEL_61;\n }\nLABEL_59:\n if ( v50 )\n {\n v3 = v6 + v62 + 1;\n goto LABEL_61;\n }\n }\n }\n }\n ++v3;\nLABEL_61:\n if ( v4 < v2 )\n return v3;\n }\n while ( v4 != v2 );\n return ++v3;\n}", + "ida_strip_asm": "sub_1240:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 68h\ncmp edi, esi\njl loc_16CB\nmov r9d, esi\ntest esi, esi\njz loc_16D2\ncmp edi, esi\njz loc_16D2\nlea eax, [rsi-9]\nxor ebp, ebp\nmov ebx, edi\nmov [rsp+98h+var_6C], eax\nloc_1278:\nmov eax, ebx\nsub ebx, 1\ncmp r9d, eax\njg loc_158C\njz loc_16C3\ncmp r9d, 1\nlea edx, [r9-2]\nsetz cl\nxor r14d, r14d\ntest cl, cl\njnz loc_16C3\nmov [rsp+98h+var_68], ebp\nmov r13d, edx\nmov ebp, ebx\nloc_12AB:\nmov ecx, ebp\nsub ebp, 1\ncmp ebp, r13d\njl loc_1574\njz loc_16BA\ntest r13d, r13d\nlea eax, [r9-3]\nmov r15d, ebp\nsetz sil\nxor r12d, r12d\ntest sil, sil\njnz loc_16BA\nmov [rsp+98h+var_64], ecx\nmov [rsp+98h+var_5C], ebx\nmov [rsp+98h+var_60], r14d\nmov r14d, eax\nloc_12E9:\nsub r15d, 1\ncmp r15d, r14d\njl loc_1553\ntest r14d, r14d\njz loc_16B1\ncmp r15d, r14d\nlea ecx, [r9-4]\nsetz r10b\nxor ebx, ebx\ntest r10b, r10b\njnz loc_16B1\nmov [rsp+98h+var_50], r12d\nmov eax, r9d\nmov [rsp+98h+var_58], ebp\nmov ebp, r15d\nmov [rsp+98h+var_54], r15d\nmov r15d, r14d\nmov [rsp+98h+var_4C], r13d\nmov r13d, ecx\nloc_1334:\nsub ebp, 1\ncmp ebp, r13d\njl loc_1526\ntest r13d, r13d\njz loc_16A9\ncmp ebp, r13d\nlea ecx, [rax-5]\nsetz r14b\nxor r12d, r12d\ntest r14b, r14b\njnz loc_16A9\nmov [rsp+98h+var_48], ebp\nmov edx, eax\nmov [rsp+98h+var_44], ebx\nmov [rsp+98h+var_40], r15d\nmov [rsp+98h+var_88], r13d\nmov r13d, r12d\nloc_1376:\nsub ebp, 1\ncmp ebp, ecx\njl loc_14F8\ntest ecx, ecx\njz loc_1694\ncmp ebp, ecx\nlea r12d, [rdx-6]\nlea eax, [rdx-7]\nsetz sil\nxor r14d, r14d\ntest sil, sil\njnz loc_1694\nmov [rsp+98h+var_3C], ebp\nmov edi, r13d\nmov r13d, r12d\nloc_13AC:\nsub ebp, 1\ncmp ebp, r13d\njl loc_14E1\ntest r13d, r13d\njz loc_166A\nmov r12d, ebp\nxor ebx, ebx\nlea r9d, [rdx-8]\ncmp ebp, r13d\njz loc_166A\nmov esi, ebp\nmov ebp, r13d\nloc_13D8:\nsub r12d, 1\ncmp r12d, eax\njl loc_14C8\ntest eax, eax\njz loc_1662\nxor r15d, r15d\ncmp r12d, eax\njz loc_1662\nmov [rsp+98h+var_8C], r14d\nmov r11d, ebp\nmov r10d, ebx\nmov ebp, r12d\nmov [rsp+98h+var_90], eax\nmov eax, r12d\nmov r12d, r9d\nloc_1411:\nsub ebp, 1\ncmp ebp, r12d\njl loc_149F\ntest r12d, r12d\njz loc_16A0\nmov r13d, ebp\nxor ebx, ebx\ncmp ebp, r12d\njz loc_16A0\nmov [rsp+98h+var_84], r15d\nmov r14d, ebp\nmov r15d, r10d\nmov ebp, eax\nmov [rsp+98h+var_80], edi\nmov edi, r13d\nmov r13d, esi\nloc_144B:\nmov esi, [rsp+98h+var_6C]\nsub edi, 1\nmov [rsp+98h+var_70], edx\nmov [rsp+98h+var_74], r11d\nmov [rsp+98h+var_78], ecx\nmov [rsp+98h+var_7C], edi\ncall sub_1240\nmov edi, [rsp+98h+var_7C]\nmov ecx, [rsp+98h+var_78]\nadd ebx, eax\nmov r11d, [rsp+98h+var_74]\nmov edx, [rsp+98h+var_70]\ncmp edi, r12d\njl loc_1678\njnz short loc_144B\nmov r10d, r15d\nmov r15d, [rsp+98h+var_84]\nmov edi, [rsp+98h+var_80]\nmov eax, ebp\nmov esi, r13d\nmov ebp, r14d\nlea r15d, [rbx+r15+1]\nloc_149F:\nmov ebx, [rsp+98h+var_90]\ncmp ebp, ebx\njl loc_15B0\njnz loc_1411\nmov r9d, r12d\nmov r14d, [rsp+98h+var_8C]\nmov r12d, eax\nmov eax, [rsp+98h+var_90]\nmov ebp, r11d\nlea ebx, [r10+r15+1]\nloc_14C8:\ncmp r12d, ebp\njl loc_15D1\nloc_14D1:\njnz loc_13D8\nmov r13d, ebp\nlea r14d, [r14+rbx+1]\nmov ebp, esi\nloc_14E1:\ncmp ebp, ecx\njl loc_15E1\nloc_14E9:\njnz loc_13AC\nmov ebp, [rsp+98h+var_3C]\nlea r13d, [r14+rdi+1]\nloc_14F8:\nmov eax, [rsp+98h+var_88]\ncmp ebp, eax\njl loc_15F7\nloc_1504:\njnz loc_1376\nmov ebx, [rsp+98h+var_44]\nmov r12d, r13d\nmov ebp, [rsp+98h+var_48]\nmov eax, edx\nmov r15d, [rsp+98h+var_40]\nmov r13d, [rsp+98h+var_88]\nlea ebx, [rbx+r12+1]\nloc_1526:\ncmp ebp, r15d\njl loc_1618\nloc_152F:\njnz loc_1334\nmov r12d, [rsp+98h+var_50]\nmov r14d, r15d\nmov ebp, [rsp+98h+var_58]\nmov r9d, eax\nmov r13d, [rsp+98h+var_4C]\nmov r15d, [rsp+98h+var_54]\nlea r12d, [r12+rbx+1]\nloc_1553:\ncmp r15d, r13d\njl loc_163D\nloc_155C:\njnz loc_12E9\nmov r14d, [rsp+98h+var_60]\nmov ecx, [rsp+98h+var_64]\nmov ebx, [rsp+98h+var_5C]\nlea r14d, [r14+r12+1]\nloc_1574:\ncmp r9d, ecx\njg loc_1656\nloc_157D:\njnz loc_12AB\nmov ebp, [rsp+98h+var_68]\nlea ebp, [r14+rbp+1]\nloc_158C:\ncmp ebx, r9d\njl short loc_159A\njnz loc_1278\nadd ebp, 1\nloc_159A:\nadd rsp, 68h\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15B0:\nmov ebx, r10d\nmov r9d, r12d\nmov ebp, r11d\nmov r12d, eax\nmov r14d, [rsp+98h+var_8C]\nmov eax, [rsp+98h+var_90]\nadd ebx, r15d\ncmp r12d, ebp\njge loc_14D1\nloc_15D1:\nmov r13d, ebp\nmov ebp, esi\nadd r14d, ebx\ncmp ebp, ecx\njge loc_14E9\nloc_15E1:\nmov ebp, [rsp+98h+var_3C]\nmov eax, [rsp+98h+var_88]\nmov r13d, edi\nadd r13d, r14d\ncmp ebp, eax\njge loc_1504\nloc_15F7:\nmov ebx, [rsp+98h+var_44]\nmov ebp, [rsp+98h+var_48]\nmov r12d, r13d\nmov r13d, eax\nmov r15d, [rsp+98h+var_40]\nmov eax, edx\nadd ebx, r12d\ncmp ebp, r15d\njge loc_152F\nloc_1618:\nmov r12d, [rsp+98h+var_50]\nmov r14d, r15d\nmov r13d, [rsp+98h+var_4C]\nmov r9d, eax\nmov r15d, [rsp+98h+var_54]\nmov ebp, [rsp+98h+var_58]\nadd r12d, ebx\ncmp r15d, r13d\njge loc_155C\nloc_163D:\nmov r14d, [rsp+98h+var_60]\nmov ecx, [rsp+98h+var_64]\nmov ebx, [rsp+98h+var_5C]\nadd r14d, r12d\ncmp r9d, ecx\njle loc_157D\nloc_1656:\nmov ebp, [rsp+98h+var_68]\nadd ebp, r14d\njmp loc_158C\nloc_1662:\nadd ebx, 1\njmp loc_14C8\nloc_166A:\nadd r14d, 1\njmp loc_14E1\nloc_1678:\nmov r10d, r15d\nmov r15d, [rsp+98h+var_84]\nmov eax, ebp\nmov edi, [rsp+98h+var_80]\nmov esi, r13d\nmov ebp, r14d\nadd r15d, ebx\njmp loc_149F\nloc_1694:\nadd r13d, 1\njmp loc_14F8\nloc_16A0:\nadd r15d, 1\njmp loc_149F\nloc_16A9:\nadd ebx, 1\njmp loc_1526\nloc_16B1:\nadd r12d, 1\njmp loc_1553\nloc_16BA:\nadd r14d, 1\njmp loc_1574\nloc_16C3:\nadd ebp, 1\njmp loc_158C\nloc_16CB:\nxor ebp, ebp\njmp loc_159A\nloc_16D2:\nmov ebp, 1\njmp loc_159A", + "ida_strip_pseudo": "__int64 __fastcall sub_1240(int a1, int a2)\n{\n int v2; // r9d\n unsigned int v3; // ebp\n int v4; // ebx\n int v5; // eax\n int v6; // r14d\n int v7; // r13d\n int v8; // ebp\n int v9; // ecx\n int v10; // r15d\n int v11; // r12d\n int v12; // r14d\n int v13; // ebx\n int v14; // eax\n int v15; // ebp\n int v16; // r15d\n int v17; // r13d\n int v18; // ecx\n int v19; // edx\n int v20; // r13d\n int v21; // eax\n int v22; // r14d\n int v23; // edi\n int v24; // r13d\n int v25; // r12d\n int v26; // ebx\n int v27; // r9d\n int v28; // esi\n int v29; // ebp\n int v30; // r15d\n int v31; // r11d\n int v32; // r10d\n int v33; // ebp\n int v34; // eax\n int v35; // r12d\n int v36; // r13d\n int v37; // ebx\n int v38; // r14d\n int v39; // r15d\n int v40; // ebp\n __int64 v41; // rdi\n int v42; // eax\n bool v43; // zf\n bool v44; // zf\n int v45; // eax\n bool v46; // zf\n int v47; // r12d\n bool v48; // zf\n bool v49; // zf\n bool v50; // zf\n int v52; // r12d\n int v53; // [rsp+8h] [rbp-90h]\n int v54; // [rsp+Ch] [rbp-8Ch]\n int v55; // [rsp+10h] [rbp-88h]\n int v56; // [rsp+14h] [rbp-84h]\n int v57; // [rsp+18h] [rbp-80h]\n int v58; // [rsp+20h] [rbp-78h]\n int v59; // [rsp+24h] [rbp-74h]\n int v60; // [rsp+28h] [rbp-70h]\n unsigned int v61; // [rsp+2Ch] [rbp-6Ch]\n unsigned int v62; // [rsp+30h] [rbp-68h]\n int v63; // [rsp+34h] [rbp-64h]\n int v64; // [rsp+38h] [rbp-60h]\n int v65; // [rsp+3Ch] [rbp-5Ch]\n int v66; // [rsp+40h] [rbp-58h]\n int v67; // [rsp+44h] [rbp-54h]\n int v68; // [rsp+48h] [rbp-50h]\n int v69; // [rsp+4Ch] [rbp-4Ch]\n int v70; // [rsp+50h] [rbp-48h]\n int v71; // [rsp+54h] [rbp-44h]\n int v72; // [rsp+58h] [rbp-40h]\n int v73; // [rsp+5Ch] [rbp-3Ch]\n\n if ( a1 < a2 )\n return 0;\n v2 = a2;\n if ( !a2 || a1 == a2 )\n return 1;\n v3 = 0;\n v4 = a1;\n v61 = a2 - 9;\n do\n {\n v5 = v4--;\n if ( v2 > v5 )\n goto LABEL_61;\n if ( v2 != v5 )\n {\n v6 = 0;\n if ( v2 != 1 )\n {\n v62 = v3;\n v7 = v2 - 2;\n v8 = v4;\n while ( 1 )\n {\n v9 = v8--;\n if ( v8 < v7 )\n goto LABEL_58;\n if ( v8 == v7 || (v10 = v8, v11 = 0, !v7) )\n {\n ++v6;\nLABEL_58:\n v50 = v2 == v9;\n if ( v2 > v9 )\n goto LABEL_71;\n goto LABEL_59;\n }\n v63 = v9;\n v65 = v4;\n v64 = v6;\n v12 = v2 - 3;\n while ( 1 )\n {\n if ( --v10 < v12 )\n goto LABEL_55;\n if ( !v12 || (v13 = 0, v10 == v12) )\n {\n ++v11;\nLABEL_55:\n v49 = v10 == v7;\n if ( v10 < v7 )\n break;\n goto LABEL_56;\n }\n v68 = v11;\n v14 = v2;\n v66 = v8;\n v15 = v10;\n v67 = v10;\n v16 = v12;\n v69 = v7;\n v17 = v2 - 4;\n while ( 1 )\n {\n if ( --v15 < v17 )\n goto LABEL_52;\n if ( !v17 || (v18 = v14 - 5, v15 == v17) )\n {\n ++v13;\nLABEL_52:\n v48 = v15 == v16;\n if ( v15 < v16 )\n break;\n goto LABEL_53;\n }\n v70 = v15;\n v19 = v14;\n v71 = v13;\n v72 = v16;\n v55 = v17;\n v20 = 0;\n while ( 1 )\n {\n if ( --v15 < v18 )\n goto LABEL_49;\n if ( !v18 || (v21 = v19 - 7, v22 = 0, v15 == v18) )\n {\n ++v20;\nLABEL_49:\n v45 = v55;\n v46 = v15 == v55;\n if ( v15 < v55 )\n break;\n goto LABEL_50;\n }\n v73 = v15;\n v23 = v20;\n v24 = v19 - 6;\n while ( 1 )\n {\n if ( --v15 < v24 )\n goto LABEL_46;\n if ( !v24 || (v25 = v15, v26 = 0, v27 = v19 - 8, v15 == v24) )\n {\n ++v22;\nLABEL_46:\n v44 = v15 == v18;\n if ( v15 < v18 )\n break;\n goto LABEL_47;\n }\n v28 = v15;\n v29 = v24;\n while ( 1 )\n {\n if ( --v25 < v21 )\n goto LABEL_43;\n if ( v21 )\n {\n v30 = 0;\n if ( v25 != v21 )\n break;\n }\n ++v26;\nLABEL_43:\n v43 = v25 == v29;\n if ( v25 < v29 )\n goto LABEL_66;\nLABEL_44:\n if ( v43 )\n {\n v24 = v29;\n v22 += v26 + 1;\n v15 = v28;\n goto LABEL_46;\n }\n }\n v54 = v22;\n v31 = v29;\n v32 = v26;\n v33 = v25;\n v53 = v21;\n v34 = v25;\n v35 = v27;\n while ( 1 )\n {\n if ( --v33 >= v35 )\n {\n if ( !v35 || (v36 = v33, v37 = 0, v33 == v35) )\n {\n ++v30;\n }\n else\n {\n v56 = v30;\n v38 = v33;\n v39 = v32;\n v40 = v34;\n v57 = v23;\n LODWORD(v41) = v36;\n while ( 1 )\n {\n v41 = (unsigned int)(v41 - 1);\n v60 = v19;\n v59 = v31;\n v58 = v18;\n v42 = sub_1240(v41, v61);\n v18 = v58;\n v37 += v42;\n v31 = v59;\n v19 = v60;\n if ( (int)v41 < v35 )\n break;\n if ( (_DWORD)v41 == v35 )\n {\n v32 = v39;\n v23 = v57;\n v34 = v40;\n v33 = v38;\n v30 = v37 + v56 + 1;\n goto LABEL_40;\n }\n }\n v32 = v39;\n v34 = v40;\n v23 = v57;\n v33 = v38;\n v30 = v37 + v56;\n }\n }\nLABEL_40:\n if ( v33 < v53 )\n break;\n if ( v33 == v53 )\n {\n v27 = v35;\n v22 = v54;\n v25 = v34;\n v21 = v53;\n v29 = v31;\n v26 = v32 + v30 + 1;\n goto LABEL_43;\n }\n }\n v27 = v35;\n v29 = v31;\n v25 = v34;\n v22 = v54;\n v21 = v53;\n v26 = v30 + v32;\n v43 = v25 == v31;\n if ( v25 >= v31 )\n goto LABEL_44;\nLABEL_66:\n v24 = v29;\n v15 = v28;\n v22 += v26;\n v44 = v28 == v18;\n if ( v28 < v18 )\n break;\nLABEL_47:\n if ( v44 )\n {\n v15 = v73;\n v20 = v22 + v23 + 1;\n goto LABEL_49;\n }\n }\n v15 = v73;\n v45 = v55;\n v20 = v22 + v23;\n v46 = v73 == v55;\n if ( v73 < v55 )\n break;\nLABEL_50:\n if ( v46 )\n {\n v47 = v20;\n v15 = v70;\n v14 = v19;\n v16 = v72;\n v17 = v55;\n v13 = v71 + v47 + 1;\n goto LABEL_52;\n }\n }\n v15 = v70;\n v52 = v20;\n v17 = v45;\n v16 = v72;\n v14 = v19;\n v13 = v52 + v71;\n v48 = v70 == v72;\n if ( v70 < v72 )\n break;\nLABEL_53:\n if ( v48 )\n {\n v12 = v16;\n v8 = v66;\n v2 = v14;\n v7 = v69;\n v10 = v67;\n v11 = v68 + v13 + 1;\n goto LABEL_55;\n }\n }\n v12 = v16;\n v7 = v69;\n v2 = v14;\n v10 = v67;\n v8 = v66;\n v11 = v13 + v68;\n v49 = v67 == v69;\n if ( v67 < v69 )\n break;\nLABEL_56:\n if ( v49 )\n {\n v9 = v63;\n v4 = v65;\n v6 = v64 + v11 + 1;\n goto LABEL_58;\n }\n }\n v4 = v65;\n v6 = v11 + v64;\n v50 = v2 == v63;\n if ( v2 > v63 )\n {\nLABEL_71:\n v3 = v6 + v62;\n goto LABEL_61;\n }\nLABEL_59:\n if ( v50 )\n {\n v3 = v6 + v62 + 1;\n goto LABEL_61;\n }\n }\n }\n }\n ++v3;\nLABEL_61:\n if ( v4 < v2 )\n return v3;\n }\n while ( v4 != v2 );\n return ++v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1240(int a1, int a2) {\n int v2;\n unsigned int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n int v8;\n int v9;\n int v10;\n int v11;\n int v12;\n int v13;\n int v14;\n int v15;\n int v16;\n int v17;\n int v18;\n int v19;\n int v20;\n int v21;\n int v22;\n int v23;\n int v24;\n int v25;\n int v26;\n int v27;\n int v28;\n int v29;\n int v30;\n int v31;\n int v32;\n int v33;\n int v34;\n int v35;\n int v36;\n int v37;\n int v38;\n int v39;\n int v40;\n long long v41;\n int v42;\n bool v43;\n bool v44;\n int v45;\n bool v46;\n int v47;\n bool v48;\n bool v49;\n bool v50;\n int v52;\n int v53;\n int v54;\n int v55;\n int v56;\n int v57;\n int v58;\n int v59;\n int v60;\n unsigned int v61;\n unsigned int v62;\n int v63;\n int v64;\n int v65;\n int v66;\n int v67;\n int v68;\n int v69;\n int v70;\n int v71;\n int v72;\n int v73;\n if (a1 < a2) return 0;\n v2 = a2;\n if (!a2 || a1 == a2) return 1;\n v3 = 0;\n v4 = a1;\n v61 = a2 - 9;\n do {\n v5 = v4--;\n if (v2 > v5) goto LABEL_61;\n if (v2 != v5) {\n v6 = 0;\n if (v2 != 1) {\n v62 = v3;\n v7 = v2 - 2;\n v8 = v4;\n while (1) {\n v9 = v8--;\n if (v8 < v7) goto LABEL_58;\n if (v8 == v7 || (v10 = v8, v11 = 0, !v7)) {\n ++v6;\n LABEL_58:\n v50 = v2 == v9;\n if (v2 > v9) goto LABEL_71;\n goto LABEL_59;\n }\n v63 = v9;\n v65 = v4;\n v64 = v6;\n v12 = v2 - 3;\n while (1) {\n if (--v10 < v12) goto LABEL_55;\n if (!v12 || (v13 = 0, v10 == v12)) {\n ++v11;\n LABEL_55:\n v49 = v10 == v7;\n if (v10 < v7) break;\n goto LABEL_56;\n }\n v68 = v11;\n v14 = v2;\n v66 = v8;\n v15 = v10;\n v67 = v10;\n v16 = v12;\n v69 = v7;\n v17 = v2 - 4;\n while (1) {\n if (--v15 < v17) goto LABEL_52;\n if (!v17 || (v18 = v14 - 5, v15 == v17)) {\n ++v13;\n LABEL_52:\n v48 = v15 == v16;\n if (v15 < v16) break;\n goto LABEL_53;\n }\n v70 = v15;\n v19 = v14;\n v71 = v13;\n v72 = v16;\n v55 = v17;\n v20 = 0;\n while (1) {\n if (--v15 < v18) goto LABEL_49;\n if (!v18 || (v21 = v19 - 7, v22 = 0, v15 == v18)) {\n ++v20;\n LABEL_49:\n v45 = v55;\n v46 = v15 == v55;\n if (v15 < v55) break;\n goto LABEL_50;\n }\n v73 = v15;\n v23 = v20;\n v24 = v19 - 6;\n while (1) {\n if (--v15 < v24) goto LABEL_46;\n if (!v24 || (v25 = v15, v26 = 0, v27 = v19 - 8, v15 == v24)) {\n ++v22;\n LABEL_46:\n v44 = v15 == v18;\n if (v15 < v18) break;\n goto LABEL_47;\n }\n v28 = v15;\n v29 = v24;\n while (1) {\n if (--v25 < v21) goto LABEL_43;\n if (v21) {\n v30 = 0;\n if (v25 != v21) break;\n }\n ++v26;\n LABEL_43:\n v43 = v25 == v29;\n if (v25 < v29) goto LABEL_66;\n LABEL_44:\n if (v43) {\n v24 = v29;\n v22 += v26 + 1;\n v15 = v28;\n goto LABEL_46;\n }\n }\n v54 = v22;\n v31 = v29;\n v32 = v26;\n v33 = v25;\n v53 = v21;\n v34 = v25;\n v35 = v27;\n while (1) {\n if (--v33 >= v35) {\n if (!v35 || (v36 = v33, v37 = 0, v33 == v35)) {\n ++v30;\n } else {\n v56 = v30;\n v38 = v33;\n v39 = v32;\n v40 = v34;\n v57 = v23;\n LODWORD(v41) = v36;\n while (1) {\n v41 = (unsigned int)(v41 - 1);\n v60 = v19;\n v59 = v31;\n v58 = v18;\n v42 = sub_1240(v41, v61);\n v18 = v58;\n v37 += v42;\n v31 = v59;\n v19 = v60;\n if ((int)v41 < v35) break;\n if ((uint32_t)v41 == v35) {\n v32 = v39;\n v23 = v57;\n v34 = v40;\n v33 = v38;\n v30 = v37 + v56 + 1;\n goto LABEL_40;\n }\n }\n v32 = v39;\n v34 = v40;\n v23 = v57;\n v33 = v38;\n v30 = v37 + v56;\n }\n }\n LABEL_40:\n if (v33 < v53) break;\n if (v33 == v53) {\n v27 = v35;\n v22 = v54;\n v25 = v34;\n v21 = v53;\n v29 = v31;\n v26 = v32 + v30 + 1;\n goto LABEL_43;\n }\n }\n v27 = v35;\n v29 = v31;\n v25 = v34;\n v22 = v54;\n v21 = v53;\n v26 = v30 + v32;\n v43 = v25 == v31;\n if (v25 >= v31) goto LABEL_44;\n LABEL_66:\n v24 = v29;\n v15 = v28;\n v22 += v26;\n v44 = v28 == v18;\n if (v28 < v18) break;\n LABEL_47:\n if (v44) {\n v15 = v73;\n v20 = v22 + v23 + 1;\n goto LABEL_49;\n }\n }\n v15 = v73;\n v45 = v55;\n v20 = v22 + v23;\n v46 = v73 == v55;\n if (v73 < v55) break;\n LABEL_50:\n if (v46) {\n v47 = v20;\n v15 = v70;\n v14 = v19;\n v16 = v72;\n v17 = v55;\n v13 = v71 + v47 + 1;\n goto LABEL_52;\n }\n }\n v15 = v70;\n v52 = v20;\n v17 = v45;\n v16 = v72;\n v14 = v19;\n v13 = v52 + v71;\n v48 = v70 == v72;\n if (v70 < v72) break;\n LABEL_53:\n if (v48) {\n v12 = v16;\n v8 = v66;\n v2 = v14;\n v7 = v69;\n v10 = v67;\n v11 = v68 + v13 + 1;\n goto LABEL_55;\n }\n }\n v12 = v16;\n v7 = v69;\n v2 = v14;\n v10 = v67;\n v8 = v66;\n v11 = v13 + v68;\n v49 = v67 == v69;\n if (v67 < v69) break;\n LABEL_56:\n if (v49) {\n v9 = v63;\n v4 = v65;\n v6 = v64 + v11 + 1;\n goto LABEL_58;\n }\n }\n v4 = v65;\n v6 = v11 + v64;\n v50 = v2 == v63;\n if (v2 > v63) {\n LABEL_71:\n v3 = v6 + v62;\n goto LABEL_61;\n }\n LABEL_59:\n if (v50) {\n v3 = v6 + v62 + 1;\n goto LABEL_61;\n }\n }\n }\n }\n ++v3;\n LABEL_61:\n if (v4 < v2) return v3;\n } while (v4 != v2);\n return ++v3;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n int v2;\n unsigned int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n int v8;\n int v9;\n int v10;\n int v11;\n int v12;\n int v13;\n int v14;\n int v15;\n int v16;\n int v17;\n int v18;\n int v19;\n int v20;\n int v21;\n int v22;\n int v23;\n int v24;\n int v25;\n int v26;\n int v27;\n int v28;\n int v29;\n int v30;\n int v31;\n int v32;\n int v33;\n int v34;\n int v35;\n int v36;\n int v37;\n int v38;\n int v39;\n int v40;\n long long v41;\n int v42;\n bool v43;\n bool v44;\n int v45;\n bool v46;\n int v47;\n bool v48;\n bool v49;\n bool v50;\n int v52;\n int v53;\n int v54;\n int v55;\n int v56;\n int v57;\n int v58;\n int v59;\n int v60;\n unsigned int v61;\n unsigned int v62;\n int v63;\n int v64;\n int v65;\n int v66;\n int v67;\n int v68;\n int v69;\n int v70;\n int v71;\n int v72;\n int v73;\n if (a1 < a2) return 0;\n v2 = a2;\n if (!a2 || a1 == a2) return 1;\n v3 = 0;\n v4 = a1;\n v61 = a2 - 9;\n do {\n v5 = v4--;\n if (v2 > v5) goto LABEL_61;\n if (v2 != v5) {\n v6 = 0;\n if (v2 != 1) {\n v62 = v3;\n v7 = v2 - 2;\n v8 = v4;\n while (1) {\n v9 = v8--;\n if (v8 < v7) goto LABEL_58;\n if (v8 == v7 || (v10 = v8, v11 = 0, !v7)) {\n ++v6;\n LABEL_58:\n v50 = v2 == v9;\n if (v2 > v9) goto LABEL_71;\n goto LABEL_59;\n }\n v63 = v9;\n v65 = v4;\n v64 = v6;\n v12 = v2 - 3;\n while (1) {\n if (--v10 < v12) goto LABEL_55;\n if (!v12 || (v13 = 0, v10 == v12)) {\n ++v11;\n LABEL_55:\n v49 = v10 == v7;\n if (v10 < v7) break;\n goto LABEL_56;\n }\n v68 = v11;\n v14 = v2;\n v66 = v8;\n v15 = v10;\n v67 = v10;\n v16 = v12;\n v69 = v7;\n v17 = v2 - 4;\n while (1) {\n if (--v15 < v17) goto LABEL_52;\n if (!v17 || (v18 = v14 - 5, v15 == v17)) {\n ++v13;\n LABEL_52:\n v48 = v15 == v16;\n if (v15 < v16) break;\n goto LABEL_53;\n }\n v70 = v15;\n v19 = v14;\n v71 = v13;\n v72 = v16;\n v55 = v17;\n v20 = 0;\n while (1) {\n if (--v15 < v18) goto LABEL_49;\n if (!v18 || (v21 = v19 - 7, v22 = 0, v15 == v18)) {\n ++v20;\n LABEL_49:\n v45 = v55;\n v46 = v15 == v55;\n if (v15 < v55) break;\n goto LABEL_50;\n }\n v73 = v15;\n v23 = v20;\n v24 = v19 - 6;\n while (1) {\n if (--v15 < v24) goto LABEL_46;\n if (!v24 || (v25 = v15, v26 = 0, v27 = v19 - 8, v15 == v24)) {\n ++v22;\n LABEL_46:\n v44 = v15 == v18;\n if (v15 < v18) break;\n goto LABEL_47;\n }\n v28 = v15;\n v29 = v24;\n while (1) {\n if (--v25 < v21) goto LABEL_43;\n if (v21) {\n v30 = 0;\n if (v25 != v21) break;\n }\n ++v26;\n LABEL_43:\n v43 = v25 == v29;\n if (v25 < v29) goto LABEL_66;\n LABEL_44:\n if (v43) {\n v24 = v29;\n v22 += v26 + 1;\n v15 = v28;\n goto LABEL_46;\n }\n }\n v54 = v22;\n v31 = v29;\n v32 = v26;\n v33 = v25;\n v53 = v21;\n v34 = v25;\n v35 = v27;\n while (1) {\n if (--v33 >= v35) {\n if (!v35 || (v36 = v33, v37 = 0, v33 == v35)) {\n ++v30;\n } else {\n v56 = v30;\n v38 = v33;\n v39 = v32;\n v40 = v34;\n v57 = v23;\n LODWORD(v41) = v36;\n while (1) {\n v41 = (unsigned int)(v41 - 1);\n v60 = v19;\n v59 = v31;\n v58 = v18;\n v42 = func0(v41, v61);\n v18 = v58;\n v37 += v42;\n v31 = v59;\n v19 = v60;\n if ((int)v41 < v35) break;\n if ((uint32_t)v41 == v35) {\n v32 = v39;\n v23 = v57;\n v34 = v40;\n v33 = v38;\n v30 = v37 + v56 + 1;\n goto LABEL_40;\n }\n }\n v32 = v39;\n v34 = v40;\n v23 = v57;\n v33 = v38;\n v30 = v37 + v56;\n }\n }\n LABEL_40:\n if (v33 < v53) break;\n if (v33 == v53) {\n v27 = v35;\n v22 = v54;\n v25 = v34;\n v21 = v53;\n v29 = v31;\n v26 = v32 + v30 + 1;\n goto LABEL_43;\n }\n }\n v27 = v35;\n v29 = v31;\n v25 = v34;\n v22 = v54;\n v21 = v53;\n v26 = v30 + v32;\n v43 = v25 == v31;\n if (v25 >= v31) goto LABEL_44;\n LABEL_66:\n v24 = v29;\n v15 = v28;\n v22 += v26;\n v44 = v28 == v18;\n if (v28 < v18) break;\n LABEL_47:\n if (v44) {\n v15 = v73;\n v20 = v22 + v23 + 1;\n goto LABEL_49;\n }\n }\n v15 = v73;\n v45 = v55;\n v20 = v22 + v23;\n v46 = v73 == v55;\n if (v73 < v55) break;\n LABEL_50:\n if (v46) {\n v47 = v20;\n v15 = v70;\n v14 = v19;\n v16 = v72;\n v17 = v55;\n v13 = v71 + v47 + 1;\n goto LABEL_52;\n }\n }\n v15 = v70;\n v52 = v20;\n v17 = v45;\n v16 = v72;\n v14 = v19;\n v13 = v52 + v71;\n v48 = v70 == v72;\n if (v70 < v72) break;\n LABEL_53:\n if (v48) {\n v12 = v16;\n v8 = v66;\n v2 = v14;\n v7 = v69;\n v10 = v67;\n v11 = v68 + v13 + 1;\n goto LABEL_55;\n }\n }\n v12 = v16;\n v7 = v69;\n v2 = v14;\n v10 = v67;\n v8 = v66;\n v11 = v13 + v68;\n v49 = v67 == v69;\n if (v67 < v69) break;\n LABEL_56:\n if (v49) {\n v9 = v63;\n v4 = v65;\n v6 = v64 + v11 + 1;\n goto LABEL_58;\n }\n }\n v4 = v65;\n v6 = v11 + v64;\n v50 = v2 == v63;\n if (v2 > v63) {\n LABEL_71:\n v3 = v6 + v62;\n goto LABEL_61;\n }\n LABEL_59:\n if (v50) {\n v3 = v6 + v62 + 1;\n goto LABEL_61;\n }\n }\n }\n }\n ++v3;\n LABEL_61:\n if (v4 < v2) return v3;\n } while (v4 != v2);\n return ++v3;\n}" + }, + { + "index": 29, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int arr_size) {\n for (int i = 0; i < arr_size; i++) {\n int count = 0;\n for (int j = 0; j < arr_size; j++) {\n if (arr[i] == arr[j]) {\n count++;\n }\n }\n if (count % 2 != 0) {\n return arr[i];\n }\n }\n return -1;\n}", + "test": "int main() {\n\n int array1[] = {1, 2, 3, 1, 2, 3, 1};\n\n assert(func0(array1, 7) == 1);\n\n \n\n int array2[] = {1, 2, 3, 2, 3, 1, 3};\n\n assert(func0(array2, 7) == 3);\n\n \n\n int array3[] = {2, 3, 5, 4, 5, 2, 4, 3, 5, 2, 4, 4, 2};\n\n assert(func0(array3, 13) == 5);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 11f7 \nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11c9 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 11c5 \naddl $0x1,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1191 \nmov -0x8(%rbp),%eax\nand $0x1,%eax\ntest %eax,%eax\nje 11f3 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\njmp 1204 \naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1181 \nmov $0xffffffff,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0\njmp short loc_11F7\nloc_1181:\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11C9\nloc_1191:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11C5\nadd [rbp+var_8], 1\nloc_11C5:\nadd [rbp+var_4], 1\nloc_11C9:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1191\nmov eax, [rbp+var_8]\nand eax, 1\ntest eax, eax\njz short loc_11F3\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\njmp short loc_1204\nloc_11F3:\nadd [rbp+var_C], 1\nloc_11F7:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_1181\nmov eax, 0FFFFFFFFh\nloc_1204:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+10h] [rbp-Ch]\n char v4; // [rsp+14h] [rbp-8h]\n int j; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n v4 = 0;\n for ( j = 0; j < a2; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4LL * j + a1) )\n ++v4;\n }\n if ( (v4 & 1) != 0 )\n return *(unsigned int *)(4LL * i + a1);\n }\n return 0xFFFFFFFFLL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0\njmp short loc_11F7\nloc_1181:\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11C9\nloc_1191:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11C5\nadd [rbp+var_8], 1\nloc_11C5:\nadd [rbp+var_4], 1\nloc_11C9:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1191\nmov eax, [rbp+var_8]\nand eax, 1\ntest eax, eax\njz short loc_11F3\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\njmp short loc_1204\nloc_11F3:\nadd [rbp+var_C], 1\nloc_11F7:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_1181\nmov eax, 0FFFFFFFFh\nloc_1204:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int i; // [rsp+10h] [rbp-Ch]\n char v4; // [rsp+14h] [rbp-8h]\n int j; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n v4 = 0;\n for ( j = 0; j < a2; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4LL * j + a1) )\n ++v4;\n }\n if ( (v4 & 1) != 0 )\n return *(unsigned int *)(4LL * i + a1);\n }\n return 0xFFFFFFFFLL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int i;\n char v4;\n int j;\n for (i = 0; i < a2; ++i) {\n v4 = 0;\n for (j = 0; j < a2; ++j) {\n if (*(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4LL * j + a1)) ++v4;\n }\n if ((v4 & 1) != 0) return *(unsigned int *)(4LL * i + a1);\n }\n return 4294967295LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int i;\n char v4;\n int j;\n for (i = 0; i < a2; ++i) {\n v4 = 0;\n for (j = 0; j < a2; ++j) {\n if (*(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4LL * j + a1)) ++v4;\n }\n if ((v4 & 1) != 0) return *(unsigned int *)(4LL * i + a1);\n }\n return 4294967295LL;\n}" + }, + { + "index": 29, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int arr_size) {\n for (int i = 0; i < arr_size; i++) {\n int count = 0;\n for (int j = 0; j < arr_size; j++) {\n if (arr[i] == arr[j]) {\n count++;\n }\n }\n if (count % 2 != 0) {\n return arr[i];\n }\n }\n return -1;\n}", + "test": "int main() {\n\n int array1[] = {1, 2, 3, 1, 2, 3, 1};\n\n assert(func0(array1, 7) == 1);\n\n \n\n int array2[] = {1, 2, 3, 2, 3, 1, 3};\n\n assert(func0(array2, 7) == 3);\n\n \n\n int array3[] = {2, 3, 5, 4, 5, 2, 4, 3, 5, 2, 4, 4, 2};\n\n assert(func0(array3, 13) == 5);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11c4 \npush %rbx\nlea -0x1(%rsi),%r11d\nmov %rdi,%rbx\nlea 0x4(%rdi,%r11,4),%r8\nmov $0x0,%r9d\njmp 1197 \ntest $0x1,%dl\njne 11bb \nlea 0x1(%r9),%rax\ncmp %r11,%r9\nje 11ca \nmov %rax,%r9\nmov %r9d,%r10d\nmov (%rdi,%r9,4),%esi\nmov %rbx,%rax\nmov $0x0,%edx\ncmp (%rax),%esi\nsete %cl\nmovzbl %cl,%ecx\nadd %ecx,%edx\nadd $0x4,%rax\ncmp %r8,%rax\njne 11a6 \njmp 1186 \nmovslq %r10d,%r10\nmov (%rdi,%r10,4),%eax\npop %rbx\nretq\nmov $0xffffffff,%eax\nretq\nmov $0xffffffff,%eax\njmp 11c2 \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11B7\nmovsxd r10, esi\nlea r8, [rdi+r10*4]\nmov r9d, 0\njmp short loc_118E\nloc_1180:\ntest dl, 1\njnz short loc_11AF\nadd r9, 1\ncmp r9, r10\njz short loc_11BD\nloc_118E:\nmov esi, [rdi+r9*4]\nmov rax, rdi\nmov edx, 0\nloc_119A:\ncmp esi, [rax]\nsetz cl\nmovzx ecx, cl\nadd edx, ecx\nadd rax, 4\ncmp rax, r8\njnz short loc_119A\njmp short loc_1180\nloc_11AF:\nmovsxd r9, r9d\nmov eax, [rdi+r9*4]\nretn\nloc_11B7:\nmov eax, 0FFFFFFFFh\nretn\nloc_11BD:\nmov eax, 0FFFFFFFFh\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n __int64 i; // r9\n _DWORD *v3; // rax\n char v4; // dl\n\n if ( a2 <= 0 )\n return 0xFFFFFFFFLL;\n for ( i = 0LL; i != a2; ++i )\n {\n v3 = a1;\n v4 = 0;\n do\n v4 += a1[i] == *v3++;\n while ( v3 != &a1[a2] );\n if ( (v4 & 1) != 0 )\n return (unsigned int)a1[(int)i];\n }\n return 0xFFFFFFFFLL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11B7\nmovsxd r10, esi\nlea r8, [rdi+r10*4]\nmov r9d, 0\njmp short loc_118E\nloc_1180:\ntest dl, 1\njnz short loc_11AF\nadd r9, 1\ncmp r9, r10\njz short loc_11BD\nloc_118E:\nmov esi, [rdi+r9*4]\nmov rax, rdi\nmov edx, 0\nloc_119A:\ncmp esi, [rax]\nsetz cl\nmovzx ecx, cl\nadd edx, ecx\nadd rax, 4\ncmp rax, r8\njnz short loc_119A\njmp short loc_1180\nloc_11AF:\nmovsxd r9, r9d\nmov eax, [rdi+r9*4]\nretn\nloc_11B7:\nmov eax, 0FFFFFFFFh\nretn\nloc_11BD:\nmov eax, 0FFFFFFFFh\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2)\n{\n __int64 i; // r9\n _DWORD *v3; // rax\n char v4; // dl\n\n if ( a2 <= 0 )\n return 0xFFFFFFFFLL;\n for ( i = 0LL; i != a2; ++i )\n {\n v3 = a1;\n v4 = 0;\n do\n v4 += a1[i] == *v3++;\n while ( v3 != &a1[a2] );\n if ( (v4 & 1) != 0 )\n return (unsigned int)a1[(int)i];\n }\n return 0xFFFFFFFFLL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2) {\n long long i;\n uint32_t *v3;\n char v4;\n if (a2 <= 0) return 4294967295LL;\n for (i = 0LL; i != a2; ++i) {\n v3 = a1;\n v4 = 0;\n do\n v4 += a1[i] == *v3++;\n while (v3 != &a1[a2]);\n if ((v4 & 1) != 0) return (unsigned int)a1[(int)i];\n }\n return 4294967295LL;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n long long i;\n uint32_t *v3;\n char v4;\n if (a2 <= 0) return 4294967295LL;\n for (i = 0LL; i != a2; ++i) {\n v3 = a1;\n v4 = 0;\n do\n v4 += a1[i] == *v3++;\n while (v3 != &a1[a2]);\n if ((v4 & 1) != 0) return (unsigned int)a1[(int)i];\n }\n return 4294967295LL;\n}" + }, + { + "index": 29, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int arr_size) {\n for (int i = 0; i < arr_size; i++) {\n int count = 0;\n for (int j = 0; j < arr_size; j++) {\n if (arr[i] == arr[j]) {\n count++;\n }\n }\n if (count % 2 != 0) {\n return arr[i];\n }\n }\n return -1;\n}", + "test": "int main() {\n\n int array1[] = {1, 2, 3, 1, 2, 3, 1};\n\n assert(func0(array1, 7) == 1);\n\n \n\n int array2[] = {1, 2, 3, 2, 3, 1, 3};\n\n assert(func0(array2, 7) == 3);\n\n \n\n int array3[] = {2, 3, 5, 4, 5, 2, 4, 3, 5, 2, 4, 4, 2};\n\n assert(func0(array3, 13) == 5);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1331 \nlea -0x1(%rsi),%eax\nmov %rdi,%r9\nlea 0x4(%rdi,%rax,4),%rsi\nnopl 0x0(%rax,%rax,1)\nmov (%r9),%r8d\nmov %rdi,%rax\nxor %edx,%edx\nxor %ecx,%ecx\ncmp (%rax),%r8d\nsete %cl\nadd $0x4,%rax\nadd %ecx,%edx\ncmp %rsi,%rax\njne 1310 \nand $0x1,%edx\njne 1337 \nadd $0x4,%r9\ncmp %rax,%r9\njne 1308 \nmov $0xffffffff,%r8d\nmov %r8d,%eax\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1300\nmovsxd rsi, esi\nmov r9, rdi\nlea r8, [rdi+rsi*4]\nnop word ptr [rax+rax+00h]\nloc_12D8:\nmov esi, [r9]\nmov rax, rdi\nxor edx, edx\nloc_12E0:\nxor ecx, ecx\ncmp esi, [rax]\nsetz cl\nadd rax, 4\nadd edx, ecx\ncmp rax, r8\njnz short loc_12E0\nand edx, 1\njnz short loc_1305\nadd r9, 4\ncmp r9, rax\njnz short loc_12D8\nloc_1300:\nmov esi, 0FFFFFFFFh\nloc_1305:\nmov eax, esi\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n unsigned int *v2; // r9\n unsigned int *v3; // r8\n unsigned int v4; // esi\n unsigned int *v5; // rax\n char v6; // dl\n char v7; // cl\n\n if ( a2 <= 0 )\n {\n return (unsigned int)-1;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n while ( 1 )\n {\n v4 = *v2;\n v5 = a1;\n v6 = 0;\n do\n {\n v7 = v4 == *v5++;\n v6 += v7;\n }\n while ( v5 != v3 );\n if ( (v6 & 1) != 0 )\n break;\n if ( ++v2 == v5 )\n return (unsigned int)-1;\n }\n }\n return v4;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\ntest esi, esi\njle short loc_1300\nmovsxd rsi, esi\nmov r9, rdi\nlea r8, [rdi+rsi*4]\nnop word ptr [rax+rax+00h]\nloc_12D8:\nmov esi, [r9]\nmov rax, rdi\nxor edx, edx\nloc_12E0:\nxor ecx, ecx\ncmp esi, [rax]\nsetz cl\nadd rax, 4\nadd edx, ecx\ncmp rax, r8\njnz short loc_12E0\nand edx, 1\njnz short loc_1305\nadd r9, 4\ncmp r9, rax\njnz short loc_12D8\nloc_1300:\nmov esi, 0FFFFFFFFh\nloc_1305:\nmov eax, esi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12C0(unsigned int *a1, int a2)\n{\n unsigned int *v2; // r9\n unsigned int *v3; // r8\n unsigned int v4; // esi\n unsigned int *v5; // rax\n char v6; // dl\n char v7; // cl\n\n if ( a2 <= 0 )\n {\n return (unsigned int)-1;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n while ( 1 )\n {\n v4 = *v2;\n v5 = a1;\n v6 = 0;\n do\n {\n v7 = v4 == *v5++;\n v6 += v7;\n }\n while ( v5 != v3 );\n if ( (v6 & 1) != 0 )\n break;\n if ( ++v2 == v5 )\n return (unsigned int)-1;\n }\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12C0(unsigned int *a1, int a2) {\n unsigned int *v2;\n unsigned int *v3;\n unsigned int v4;\n unsigned int *v5;\n char v6;\n char v7;\n if (a2 <= 0) {\n return (unsigned int)-1;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n while (1) {\n v4 = *v2;\n v5 = a1;\n v6 = 0;\n do {\n v7 = v4 == *v5++;\n v6 += v7;\n } while (v5 != v3);\n if ((v6 & 1) != 0) break;\n if (++v2 == v5) return (unsigned int)-1;\n }\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n unsigned int *v2;\n unsigned int *v3;\n unsigned int v4;\n unsigned int *v5;\n char v6;\n char v7;\n if (a2 <= 0) {\n return (unsigned int)-1;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n while (1) {\n v4 = *v2;\n v5 = a1;\n v6 = 0;\n do {\n v7 = v4 == *v5++;\n v6 += v7;\n } while (v5 != v3);\n if ((v6 & 1) != 0) break;\n if (++v2 == v5) return (unsigned int)-1;\n }\n }\n return v4;\n}" + }, + { + "index": 29, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int arr_size) {\n for (int i = 0; i < arr_size; i++) {\n int count = 0;\n for (int j = 0; j < arr_size; j++) {\n if (arr[i] == arr[j]) {\n count++;\n }\n }\n if (count % 2 != 0) {\n return arr[i];\n }\n }\n return -1;\n}", + "test": "int main() {\n\n int array1[] = {1, 2, 3, 1, 2, 3, 1};\n\n assert(func0(array1, 7) == 1);\n\n \n\n int array2[] = {1, 2, 3, 2, 3, 1, 3};\n\n assert(func0(array2, 7) == 3);\n\n \n\n int array3[] = {2, 3, 5, 4, 5, 2, 4, 3, 5, 2, 4, 4, 2};\n\n assert(func0(array3, 13) == 5);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 13c6 \nmov %esi,%edx\npush %r12\nlea -0x1(%rsi),%eax\nmov %rdi,%r9\nshr $0x2,%edx\npush %rbp\nlea 0x4(%rdi,%rax,4),%r12\nmov %rax,%rbp\npush %rbx\nshl $0x4,%rdx\nmov %esi,%ebx\nadd %rdi,%rdx\nand $0xfffffffc,%ebx\nmov (%r9),%r8d\ncmp $0x3,%ebp\njbe 13c0 \nmovd %r8d,%xmm3\nmov %rdi,%rax\npxor %xmm1,%xmm1\npshufd $0x0,%xmm3,%xmm2\nnopl (%rax)\nmovdqu (%rax),%xmm0\nadd $0x10,%rax\npcmpeqd %xmm2,%xmm0\npsubd %xmm0,%xmm1\ncmp %rax,%rdx\njne 1310 \nmovdqa %xmm1,%xmm0\nmov %ebx,%ecx\npsrldq $0x8,%xmm0\npaddd %xmm0,%xmm1\nmovdqa %xmm1,%xmm0\npsrldq $0x4,%xmm0\npaddd %xmm0,%xmm1\nmovd %xmm1,%eax\ncmp %esi,%ebx\nje 13a0 \nmovslq %ecx,%r11\ncmp (%rdi,%r11,4),%r8d\nlea 0x0(,%r11,4),%r10\nsete %r11b\nmovzbl %r11b,%r11d\nadd %r11d,%eax\nlea 0x1(%rcx),%r11d\ncmp %esi,%r11d\njge 13a0 \ncmp 0x4(%rdi,%r10,1),%r8d\njne 1376 \nadd $0x1,%eax\nlea 0x2(%rcx),%r11d\ncmp %r11d,%esi\njle 13a0 \ncmp 0x8(%rdi,%r10,1),%r8d\njne 1389 \nadd $0x1,%eax\nadd $0x3,%ecx\ncmp %ecx,%esi\njle 13a0 \ncmp 0xc(%rdi,%r10,1),%r8d\njne 13a0 \nadd $0x1,%eax\nnopw 0x0(%rax,%rax,1)\ntest $0x1,%al\njne 13b7 \nadd $0x4,%r9\ncmp %r12,%r9\njne 12f0 \nmov $0xffffffff,%r8d\npop %rbx\nmov %r8d,%eax\npop %rbp\npop %r12\nretq\nxor %ecx,%ecx\nxor %eax,%eax\njmp 1349 \nmov $0xffffffff,%r8d\nmov %r8d,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle loc_13B6\nmov edx, esi\npush r12\nmovsxd rax, esi\nmov r12d, esi\nshr edx, 2\npush rbp\nmov r8, rdi\nmov r9d, esi\nshl rdx, 4\npush rbx\nlea r11d, [rsi-1]\nlea rbx, [rdi+rax*4]\nadd rdx, rdi\nand r12d, 0FFFFFFFCh\nnop dword ptr [rax+00h]\nloc_12F8:\nmov esi, [rdi]\ncmp r11d, 2\njbe loc_13B0\nmovd xmm3, esi\nmov rax, r8\npxor xmm0, xmm0\npshufd xmm2, xmm3, 0\nnop dword ptr [rax+00h]\nloc_1318:\nmovdqu xmm1, xmmword ptr [rax]\nadd rax, 10h\npcmpeqd xmm1, xmm2\npsubd xmm0, xmm1\ncmp rdx, rax\njnz short loc_1318\nmovdqa xmm1, xmm0\nmov ecx, r12d\npsrldq xmm1, 8\npaddd xmm0, xmm1\nmovdqa xmm1, xmm0\npsrldq xmm1, 4\npaddd xmm0, xmm1\nmovd eax, xmm0\ncmp r9d, r12d\njz short loc_138C\nloc_1353:\nmovsxd r10, ecx\nlea rbp, ds:0[r10*4]\ncmp esi, [r8+r10*4]\njnz short loc_1367\nadd eax, 1\nloc_1367:\nlea r10d, [rcx+1]\ncmp r9d, r10d\njle short loc_138C\ncmp esi, [r8+rbp+4]\njnz short loc_137A\nadd eax, 1\nloc_137A:\nadd ecx, 2\ncmp r9d, ecx\njle short loc_138C\ncmp esi, [r8+rbp+8]\njnz short loc_138C\nadd eax, 1\nloc_138C:\ntest al, 1\njnz short loc_13A2\nadd rdi, 4\ncmp rbx, rdi\njnz loc_12F8\nmov esi, 0FFFFFFFFh\nloc_13A2:\npop rbx\nmov eax, esi\npop rbp\npop r12\nretn\nloc_13B0:\nxor ecx, ecx\nxor eax, eax\njmp short loc_1353\nloc_13B6:\nmov eax, 0FFFFFFFFh\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n const __m128i *v2; // r8\n unsigned int v4; // r11d\n unsigned int *v5; // rbx\n const __m128i *v6; // rdx\n unsigned int v7; // r12d\n unsigned int v8; // esi\n const __m128i *v9; // rax\n __m128i v10; // xmm0\n __m128i v11; // xmm2\n __m128i v12; // xmm1\n signed int v13; // ecx\n __m128i v14; // xmm0\n char v15; // al\n __int64 v16; // rbp\n\n if ( a2 <= 0 )\n return 0xFFFFFFFFLL;\n v2 = (const __m128i *)a1;\n v4 = a2 - 1;\n v5 = &a1[a2];\n v6 = (const __m128i *)&a1[4 * ((unsigned int)a2 >> 2)];\n v7 = a2 & 0xFFFFFFFC;\n do\n {\n v8 = *a1;\n if ( v4 <= 2 )\n {\n v13 = 0;\n v15 = 0;\n }\n else\n {\n v9 = v2;\n v10 = 0LL;\n v11 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v8), 0);\n do\n {\n v12 = _mm_loadu_si128(v9++);\n v10 = _mm_sub_epi32(v10, _mm_cmpeq_epi32(v12, v11));\n }\n while ( v6 != v9 );\n v13 = v7;\n v14 = _mm_add_epi32(v10, _mm_srli_si128(v10, 8));\n v15 = _mm_cvtsi128_si32(_mm_add_epi32(v14, _mm_srli_si128(v14, 4)));\n if ( a2 == v7 )\n goto LABEL_15;\n }\n v16 = v13;\n if ( v8 == v2->m128i_i32[v16] )\n ++v15;\n if ( a2 > v13 + 1 )\n {\n if ( v8 == v2->m128i_i32[v16 + 1] )\n ++v15;\n if ( a2 > v13 + 2 && v8 == v2->m128i_i32[v16 + 2] )\n ++v15;\n }\nLABEL_15:\n if ( (v15 & 1) != 0 )\n return v8;\n ++a1;\n }\n while ( v5 != a1 );\n return (unsigned int)-1;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\ntest esi, esi\njle loc_13B6\nmov edx, esi\npush r12\nmovsxd rax, esi\nmov r12d, esi\nshr edx, 2\npush rbp\nmov r8, rdi\nmov r9d, esi\nshl rdx, 4\npush rbx\nlea r11d, [rsi-1]\nlea rbx, [rdi+rax*4]\nadd rdx, rdi\nand r12d, 0FFFFFFFCh\nnop dword ptr [rax+00h]\nloc_12F8:\nmov esi, [rdi]\ncmp r11d, 2\njbe loc_13B0\nmovd xmm3, esi\nmov rax, r8\npxor xmm0, xmm0\npshufd xmm2, xmm3, 0\nnop dword ptr [rax+00h]\nloc_1318:\nmovdqu xmm1, xmmword ptr [rax]\nadd rax, 10h\npcmpeqd xmm1, xmm2\npsubd xmm0, xmm1\ncmp rdx, rax\njnz short loc_1318\nmovdqa xmm1, xmm0\nmov ecx, r12d\npsrldq xmm1, 8\npaddd xmm0, xmm1\nmovdqa xmm1, xmm0\npsrldq xmm1, 4\npaddd xmm0, xmm1\nmovd eax, xmm0\ncmp r9d, r12d\njz short loc_138C\nloc_1353:\nmovsxd r10, ecx\nlea rbp, ds:0[r10*4]\ncmp esi, [r8+r10*4]\njnz short loc_1367\nadd eax, 1\nloc_1367:\nlea r10d, [rcx+1]\ncmp r9d, r10d\njle short loc_138C\ncmp esi, [r8+rbp+4]\njnz short loc_137A\nadd eax, 1\nloc_137A:\nadd ecx, 2\ncmp r9d, ecx\njle short loc_138C\ncmp esi, [r8+rbp+8]\njnz short loc_138C\nadd eax, 1\nloc_138C:\ntest al, 1\njnz short loc_13A2\nadd rdi, 4\ncmp rbx, rdi\njnz loc_12F8\nmov esi, 0FFFFFFFFh\nloc_13A2:\npop rbx\nmov eax, esi\npop rbp\npop r12\nretn\nloc_13B0:\nxor ecx, ecx\nxor eax, eax\njmp short loc_1353\nloc_13B6:\nmov eax, 0FFFFFFFFh\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12C0(unsigned int *a1, int a2)\n{\n const __m128i *v2; // r8\n unsigned int v4; // r11d\n unsigned int *v5; // rbx\n const __m128i *v6; // rdx\n unsigned int v7; // r12d\n unsigned int v8; // esi\n const __m128i *v9; // rax\n __m128i v10; // xmm0\n __m128i v11; // xmm2\n __m128i v12; // xmm1\n signed int v13; // ecx\n __m128i v14; // xmm0\n char v15; // al\n __int64 v16; // rbp\n\n if ( a2 <= 0 )\n return 0xFFFFFFFFLL;\n v2 = (const __m128i *)a1;\n v4 = a2 - 1;\n v5 = &a1[a2];\n v6 = (const __m128i *)&a1[4 * ((unsigned int)a2 >> 2)];\n v7 = a2 & 0xFFFFFFFC;\n do\n {\n v8 = *a1;\n if ( v4 <= 2 )\n {\n v13 = 0;\n v15 = 0;\n }\n else\n {\n v9 = v2;\n v10 = 0LL;\n v11 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v8), 0);\n do\n {\n v12 = _mm_loadu_si128(v9++);\n v10 = _mm_sub_epi32(v10, _mm_cmpeq_epi32(v12, v11));\n }\n while ( v6 != v9 );\n v13 = v7;\n v14 = _mm_add_epi32(v10, _mm_srli_si128(v10, 8));\n v15 = _mm_cvtsi128_si32(_mm_add_epi32(v14, _mm_srli_si128(v14, 4)));\n if ( a2 == v7 )\n goto LABEL_15;\n }\n v16 = v13;\n if ( v8 == v2->m128i_i32[v16] )\n ++v15;\n if ( a2 > v13 + 1 )\n {\n if ( v8 == v2->m128i_i32[v16 + 1] )\n ++v15;\n if ( a2 > v13 + 2 && v8 == v2->m128i_i32[v16 + 2] )\n ++v15;\n }\nLABEL_15:\n if ( (v15 & 1) != 0 )\n return v8;\n ++a1;\n }\n while ( v5 != a1 );\n return (unsigned int)-1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12C0(unsigned int *a1, int a2) {\n const __m128i *v2;\n unsigned int v4;\n unsigned int *v5;\n const __m128i *v6;\n unsigned int v7;\n unsigned int v8;\n const __m128i *v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n signed int v13;\n __m128i v14;\n char v15;\n long long v16;\n if (a2 <= 0) return 4294967295LL;\n v2 = (const __m128i *)a1;\n v4 = a2 - 1;\n v5 = &a1[a2];\n v6 = (const __m128i *)&a1[4 * ((unsigned int)a2 >> 2)];\n v7 = a2 & 4294967292;\n do {\n v8 = *a1;\n if (v4 <= 2) {\n v13 = 0;\n v15 = 0;\n } else {\n v9 = v2;\n v10 = 0LL;\n v11 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v8), 0);\n do {\n v12 = _mm_loadu_si128(v9++);\n v10 = _mm_sub_epi32(v10, _mm_cmpeq_epi32(v12, v11));\n } while (v6 != v9);\n v13 = v7;\n v14 = _mm_add_epi32(v10, _mm_srli_si128(v10, 8));\n v15 = _mm_cvtsi128_si32(_mm_add_epi32(v14, _mm_srli_si128(v14, 4)));\n if (a2 == v7) goto LABEL_15;\n }\n v16 = v13;\n if (v8 == v2->m128i_i32[v16]) ++v15;\n if (a2 > v13 + 1) {\n if (v8 == v2->m128i_i32[v16 + 1]) ++v15;\n if (a2 > v13 + 2 && v8 == v2->m128i_i32[v16 + 2]) ++v15;\n }\n LABEL_15:\n if ((v15 & 1) != 0) return v8;\n ++a1;\n } while (v5 != a1);\n return (unsigned int)-1;\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n const __m128i *v2;\n unsigned int v4;\n unsigned int *v5;\n const __m128i *v6;\n unsigned int v7;\n unsigned int v8;\n const __m128i *v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n signed int v13;\n __m128i v14;\n char v15;\n long long v16;\n if (a2 <= 0) return 4294967295LL;\n v2 = (const __m128i *)a1;\n v4 = a2 - 1;\n v5 = &a1[a2];\n v6 = (const __m128i *)&a1[4 * ((unsigned int)a2 >> 2)];\n v7 = a2 & 4294967292;\n do {\n v8 = *a1;\n if (v4 <= 2) {\n v13 = 0;\n v15 = 0;\n } else {\n v9 = v2;\n v10 = 0LL;\n v11 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v8), 0);\n do {\n v12 = _mm_loadu_si128(v9++);\n v10 = _mm_sub_epi32(v10, _mm_cmpeq_epi32(v12, v11));\n } while (v6 != v9);\n v13 = v7;\n v14 = _mm_add_epi32(v10, _mm_srli_si128(v10, 8));\n v15 = _mm_cvtsi128_si32(_mm_add_epi32(v14, _mm_srli_si128(v14, 4)));\n if (a2 == v7) goto LABEL_15;\n }\n v16 = v13;\n if (v8 == v2->m128i_i32[v16]) ++v15;\n if (a2 > v13 + 1) {\n if (v8 == v2->m128i_i32[v16 + 1]) ++v15;\n if (a2 > v13 + 2 && v8 == v2->m128i_i32[v16 + 2]) ++v15;\n }\n LABEL_15:\n if ((v15 & 1) != 0) return v8;\n ++a1;\n } while (v5 != a1);\n return (unsigned int)-1;\n}" + }, + { + "index": 30, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint check_Equality(char *s, int start, int length) {\n\n return (s[start] == s[start + length - 1]);\n\n}\n\n\n\n", + "func": "int func0(char *s) {\n int result = 0;\n int n = strlen(s);\n for (int i = 0; i < n; i++) {\n for (int j = 1; j <= n - i; j++) {\n if (check_Equality(s, i, j)) {\n result++;\n }\n }\n }\n return result;\n}", + "test": "int main() {\n\n assert(func0(\"abc\") == 3);\n\n assert(func0(\"abcda\") == 6);\n\n assert(func0(\"ab\") == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmovl $0x0,-0x10(%rbp)\nmov -0x18(%rbp),%rax\nmov %rax,%rdi\ncallq 1060 \nmov %eax,-0x4(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 1214 \nmovl $0x1,-0x8(%rbp)\njmp 1205 \nmov -0x8(%rbp),%edx\nmov -0xc(%rbp),%ecx\nmov -0x18(%rbp),%rax\nmov %ecx,%esi\nmov %rax,%rdi\ncallq 1169 \ntest %eax,%eax\nje 1201 \naddl $0x1,-0x10(%rbp)\naddl $0x1,-0x8(%rbp)\nmov -0x4(%rbp),%eax\nsub -0xc(%rbp),%eax\ncmp %eax,-0x8(%rbp)\njle 11e5 \naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x4(%rbp),%eax\njl 11dc \nmov -0x10(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov [rbp+var_10], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_C], 0\njmp short loc_1214\nloc_11DC:\nmov [rbp+var_8], 1\njmp short loc_1205\nloc_11E5:\nmov edx, [rbp+var_8]\nmov ecx, [rbp+var_C]\nmov rax, [rbp+s]\nmov esi, ecx\nmov rdi, rax\ncall check_Equality\ntest eax, eax\njz short loc_1201\nadd [rbp+var_10], 1\nloc_1201:\nadd [rbp+var_8], 1\nloc_1205:\nmov eax, [rbp+var_4]\nsub eax, [rbp+var_C]\ncmp [rbp+var_8], eax\njle short loc_11E5\nadd [rbp+var_C], 1\nloc_1214:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_4]\njl short loc_11DC\nmov eax, [rbp+var_10]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n unsigned int v2; // [rsp+10h] [rbp-10h]\n unsigned int i; // [rsp+14h] [rbp-Ch]\n int j; // [rsp+18h] [rbp-8h]\n int v5; // [rsp+1Ch] [rbp-4h]\n\n v2 = 0;\n v5 = strlen(a1);\n for ( i = 0; (int)i < v5; ++i )\n {\n for ( j = 1; j <= (int)(v5 - i); ++j )\n {\n if ( (unsigned int)check_Equality(a1, i, (unsigned int)j) )\n ++v2;\n }\n }\n return v2;\n}", + "ida_strip_asm": "sub_11AD:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov [rbp+var_10], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_C], 0\njmp short loc_1214\nloc_11DC:\nmov [rbp+var_8], 1\njmp short loc_1205\nloc_11E5:\nmov edx, [rbp+var_8]\nmov ecx, [rbp+var_C]\nmov rax, [rbp+s]\nmov esi, ecx\nmov rdi, rax\ncall sub_1169\ntest eax, eax\njz short loc_1201\nadd [rbp+var_10], 1\nloc_1201:\nadd [rbp+var_8], 1\nloc_1205:\nmov eax, [rbp+var_4]\nsub eax, [rbp+var_C]\ncmp [rbp+var_8], eax\njle short loc_11E5\nadd [rbp+var_C], 1\nloc_1214:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_4]\njl short loc_11DC\nmov eax, [rbp+var_10]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11AD(const char *a1)\n{\n unsigned int v2; // [rsp+10h] [rbp-10h]\n unsigned int i; // [rsp+14h] [rbp-Ch]\n int j; // [rsp+18h] [rbp-8h]\n int v5; // [rsp+1Ch] [rbp-4h]\n\n v2 = 0;\n v5 = strlen(a1);\n for ( i = 0; (int)i < v5; ++i )\n {\n for ( j = 1; j <= (int)(v5 - i); ++j )\n {\n if ( (unsigned int)sub_1169(a1, i, (unsigned int)j) )\n ++v2;\n }\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11AD(const char *a1) {\n unsigned int v2;\n unsigned int i;\n int j;\n int v5;\n v2 = 0;\n v5 = strlen(a1);\n for (i = 0; (int)i < v5; ++i) {\n for (j = 1; j <= (int)(v5 - i); ++j) {\n if ((unsigned int)sub_1169(a1, i, (unsigned int)j)) ++v2;\n }\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n unsigned int v2;\n unsigned int i;\n int j;\n int v5;\n v2 = 0;\n v5 = strlen(a1);\n for (i = 0; (int)i < v5; ++i) {\n for (j = 1; j <= (int)(v5 - i); ++j) {\n if ((unsigned int)check_Equality(a1, i, (unsigned int)j)) ++v2;\n }\n }\n return v2;\n}" + }, + { + "index": 30, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint check_Equality(char *s, int start, int length) {\n\n return (s[start] == s[start + length - 1]);\n\n}\n\n\n\n", + "func": "int func0(char *s) {\n int result = 0;\n int n = strlen(s);\n for (int i = 0; i < n; i++) {\n for (int j = 1; j <= n - i; j++) {\n if (check_Equality(s, i, j)) {\n result++;\n }\n }\n }\n return result;\n}", + "test": "int main() {\n\n assert(func0(\"abc\") == 3);\n\n assert(func0(\"abcda\") == 6);\n\n assert(func0(\"ab\") == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%r14\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%r15\ntest %r15d,%r15d\njle 11db \nadd $0x1,%r15d\nmov %r15d,%r12d\nmov $0x0,%ebp\njmp 11c5 \nmov %ebx,%edx\nmov %r13d,%esi\nmov %r14,%rdi\ncallq 1149 \ncmp $0x1,%eax\nsbb $0xffffffff,%ebp\nadd $0x1,%ebx\ncmp %r12d,%ebx\njne 11a0 \nsub $0x1,%r12d\ncmp $0x1,%r12d\nje 11e0 \nmov %r15d,%r13d\nsub %r12d,%r13d\nlea -0x1(%r12),%eax\nmov $0x1,%ebx\ntest %eax,%eax\njg 11a0 \njmp 11bb \nmov $0x0,%ebp\nmov %ebp,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r14, rdi\ncall _strlen\ntest eax, eax\njle short loc_11F8\nlea r15d, [rax+1]\nmov r12d, r15d\nmov ebp, 0\nloc_11AE:\nmov r13d, r15d\nsub r13d, r12d\nlea eax, [r12-1]\nmov ebx, 1\ntest eax, eax\njle short loc_11FF\nloc_11C2:\nmov edx, ebx\nmov esi, r13d\nmov rdi, r14\ncall check_Equality\ncmp eax, 1\nsbb ebp, 0FFFFFFFFh\nadd ebx, 1\ncmp ebx, r12d\njnz short loc_11C2\nsub r12d, 1\ncmp r12d, 1\njnz short loc_11AE\nloc_11E7:\nmov eax, ebp\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_11F8:\nmov ebp, 0\njmp short loc_11E7\nloc_11FF:\nsub r12d, 1\njmp short loc_11AE", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v1; // eax\n int v2; // r15d\n int v3; // r12d\n unsigned int v4; // ebp\n unsigned int v5; // ebx\n\n v1 = strlen(a1);\n if ( v1 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = v1 + 1;\n v3 = v1 + 1;\n v4 = 0;\n do\n {\n while ( 1 )\n {\n v5 = 1;\n if ( v3 - 1 > 0 )\n break;\n --v3;\n }\n do\n v4 -= ((unsigned int)check_Equality(a1, (unsigned int)(v2 - v3), v5++) == 0) - 1;\n while ( v5 != v3 );\n --v3;\n }\n while ( v3 != 1 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_1184:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r14, rdi\ncall _strlen\ntest eax, eax\njle short loc_11F8\nlea r15d, [rax+1]\nmov r12d, r15d\nmov ebp, 0\nloc_11AE:\nmov r13d, r15d\nsub r13d, r12d\nlea eax, [r12-1]\nmov ebx, 1\ntest eax, eax\njle short loc_11FF\nloc_11C2:\nmov edx, ebx\nmov esi, r13d\nmov rdi, r14\ncall sub_1169\ncmp eax, 1\nsbb ebp, 0FFFFFFFFh\nadd ebx, 1\ncmp ebx, r12d\njnz short loc_11C2\nsub r12d, 1\ncmp r12d, 1\njnz short loc_11AE\nloc_11E7:\nmov eax, ebp\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_11F8:\nmov ebp, 0\njmp short loc_11E7\nloc_11FF:\nsub r12d, 1\njmp short loc_11AE", + "ida_strip_pseudo": "__int64 __fastcall sub_1184(const char *a1)\n{\n int v1; // eax\n int v2; // r15d\n int v3; // r12d\n unsigned int v4; // ebp\n unsigned int v5; // ebx\n\n v1 = strlen(a1);\n if ( v1 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = v1 + 1;\n v3 = v1 + 1;\n v4 = 0;\n do\n {\n while ( 1 )\n {\n v5 = 1;\n if ( v3 - 1 > 0 )\n break;\n --v3;\n }\n do\n v4 -= ((unsigned int)sub_1169(a1, (unsigned int)(v2 - v3), v5++) == 0) - 1;\n while ( v5 != v3 );\n --v3;\n }\n while ( v3 != 1 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1184(const char *a1) {\n int v1;\n int v2;\n int v3;\n unsigned int v4;\n unsigned int v5;\n v1 = strlen(a1);\n if (v1 <= 0) {\n return 0;\n } else {\n v2 = v1 + 1;\n v3 = v1 + 1;\n v4 = 0;\n do {\n while (1) {\n v5 = 1;\n if (v3 - 1 > 0) break;\n --v3;\n }\n do\n v4 -= ((unsigned int)sub_1169(a1, (unsigned int)(v2 - v3), v5++) == 0) -\n 1;\n while (v5 != v3);\n --v3;\n } while (v3 != 1);\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v1;\n int v2;\n int v3;\n unsigned int v4;\n unsigned int v5;\n v1 = strlen(a1);\n if (v1 <= 0) {\n return 0;\n } else {\n v2 = v1 + 1;\n v3 = v1 + 1;\n v4 = 0;\n do {\n while (1) {\n v5 = 1;\n if (v3 - 1 > 0) break;\n --v3;\n }\n do\n v4 -= ((unsigned int)check_Equality(a1, (unsigned int)(v2 - v3),\n v5++) == 0) -\n 1;\n while (v5 != v3);\n --v3;\n } while (v3 != 1);\n }\n return v4;\n}" + }, + { + "index": 30, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint check_Equality(char *s, int start, int length) {\n\n return (s[start] == s[start + length - 1]);\n\n}\n\n\n\n", + "func": "int func0(char *s) {\n int result = 0;\n int n = strlen(s);\n for (int i = 0; i < n; i++) {\n for (int j = 1; j <= n - i; j++) {\n if (check_Equality(s, i, j)) {\n result++;\n }\n }\n }\n return result;\n}", + "test": "int main() {\n\n assert(func0(\"abc\") == 3);\n\n assert(func0(\"abcda\") == 6);\n\n assert(func0(\"ab\") == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\ncallq 1060 \ntest %eax,%eax\njle 1292 \nmov %eax,%r10d\nmov %rbx,%rdi\nxor %r9d,%r9d\nxor %r8d,%r8d\nlea -0x1(%rax),%r11d\nnopl 0x0(%rax)\nmov %r11d,%ecx\nmovzbl (%rdi),%esi\nmov %rdi,%rax\nadd $0x1,%rdi\nsub %r9d,%ecx\nadd %rdi,%rcx\nnopl 0x0(%rax,%rax,1)\nxor %edx,%edx\ncmp (%rax),%sil\nsete %dl\nadd $0x1,%rax\nadd %edx,%r8d\ncmp %rcx,%rax\njne 1270 \nadd $0x1,%r9d\ncmp %r9d,%r10d\njne 1258 \nmov %r8d,%eax\npop %rbx\nretq\nxor %r8d,%r8d\npop %rbx\nmov %r8d,%eax\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest eax, eax\njle short loc_1288\nmov r10d, eax\nmov rdi, rbx\nxor r9d, r9d\nxor edx, edx\nlea r11d, [rax-1]\nloc_1250:\nmov esi, r11d\nmovzx r8d, byte ptr [rdi]\nmov rax, rdi\nadd rdi, 1\nsub esi, r9d\nadd rsi, rdi\nnop dword ptr [rax+00h]\nloc_1268:\nxor ecx, ecx\ncmp r8b, [rax]\nsetz cl\nadd rax, 1\nadd edx, ecx\ncmp rsi, rax\njnz short loc_1268\nadd r9d, 1\ncmp r10d, r9d\njnz short loc_1250\nmov eax, edx\npop rbx\nretn\nloc_1288:\nxor edx, edx\npop rbx\nmov eax, edx\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v1; // eax\n int v2; // r10d\n int v3; // r9d\n unsigned int v4; // edx\n int v5; // r11d\n char v6; // r8\n const char *v7; // rax\n int v8; // ecx\n\n v1 = strlen(a1);\n if ( v1 <= 0 )\n return 0LL;\n v2 = v1;\n v3 = 0;\n v4 = 0;\n v5 = v1 - 1;\n do\n {\n v6 = *a1;\n v7 = a1++;\n do\n {\n v8 = v6 == *v7++;\n v4 += v8;\n }\n while ( &a1[v5 - v3] != v7 );\n ++v3;\n }\n while ( v2 != v3 );\n return v4;\n}", + "ida_strip_asm": "sub_1230:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest eax, eax\njle short loc_1288\nmov r10d, eax\nmov rdi, rbx\nxor r9d, r9d\nxor edx, edx\nlea r11d, [rax-1]\nloc_1250:\nmov esi, r11d\nmovzx r8d, byte ptr [rdi]\nmov rax, rdi\nadd rdi, 1\nsub esi, r9d\nadd rsi, rdi\nnop dword ptr [rax+00h]\nloc_1268:\nxor ecx, ecx\ncmp r8b, [rax]\nsetz cl\nadd rax, 1\nadd edx, ecx\ncmp rsi, rax\njnz short loc_1268\nadd r9d, 1\ncmp r10d, r9d\njnz short loc_1250\nmov eax, edx\npop rbx\nretn\nloc_1288:\nxor edx, edx\npop rbx\nmov eax, edx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1230(const char *a1)\n{\n int v1; // eax\n int v2; // r10d\n int v3; // r9d\n unsigned int v4; // edx\n int v5; // r11d\n char v6; // r8\n const char *v7; // rax\n int v8; // ecx\n\n v1 = strlen(a1);\n if ( v1 <= 0 )\n return 0LL;\n v2 = v1;\n v3 = 0;\n v4 = 0;\n v5 = v1 - 1;\n do\n {\n v6 = *a1;\n v7 = a1++;\n do\n {\n v8 = v6 == *v7++;\n v4 += v8;\n }\n while ( &a1[v5 - v3] != v7 );\n ++v3;\n }\n while ( v2 != v3 );\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1230(const char *a1) {\n int v1;\n int v2;\n int v3;\n unsigned int v4;\n int v5;\n char v6;\n const char *v7;\n int v8;\n v1 = strlen(a1);\n if (v1 <= 0) return 0LL;\n v2 = v1;\n v3 = 0;\n v4 = 0;\n v5 = v1 - 1;\n do {\n v6 = *a1;\n v7 = a1++;\n do {\n v8 = v6 == *v7++;\n v4 += v8;\n } while (&a1[v5 - v3] != v7);\n ++v3;\n } while (v2 != v3);\n return v4;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v1;\n int v2;\n int v3;\n unsigned int v4;\n int v5;\n char v6;\n const char *v7;\n int v8;\n v1 = strlen(a1);\n if (v1 <= 0) return 0LL;\n v2 = v1;\n v3 = 0;\n v4 = 0;\n v5 = v1 - 1;\n do {\n v6 = *a1;\n v7 = a1++;\n do {\n v8 = v6 == *v7++;\n v4 += v8;\n } while (&a1[v5 - v3] != v7);\n ++v3;\n } while (v2 != v3);\n return v4;\n}" + }, + { + "index": 30, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint check_Equality(char *s, int start, int length) {\n\n return (s[start] == s[start + length - 1]);\n\n}\n\n\n\n", + "func": "int func0(char *s) {\n int result = 0;\n int n = strlen(s);\n for (int i = 0; i < n; i++) {\n for (int j = 1; j <= n - i; j++) {\n if (check_Equality(s, i, j)) {\n result++;\n }\n }\n }\n return result;\n}", + "test": "int main() {\n\n assert(func0(\"abc\") == 3);\n\n assert(func0(\"abcda\") == 6);\n\n assert(func0(\"ab\") == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nmov %rdi,%rbx\nsub $0x8,%rsp\ncallq 1060 \ntest %eax,%eax\njle 14ea \nmovdqa 0xe3e(%rip),%xmm5\nmov %rax,%rdx\nmov %eax,%r11d\nmov %eax,%ebp\nmov %rbx,%rdi\nxor %esi,%esi\npxor %xmm4,%xmm4\nxor %r9d,%r9d\npxor %xmm3,%xmm3\nnopw 0x0(%rax,%rax,1)\nlea -0x1(%rdx),%r10d\nmovzbl (%rdi),%r8d\ncmp $0xe,%r10d\njbe 14e0 \nmovd %r8d,%xmm7\nmov %edx,%ecx\npxor %xmm1,%xmm1\nmov %rdi,%rax\npunpcklbw %xmm7,%xmm7\nshr $0x4,%ecx\npunpcklwd %xmm7,%xmm7\nshl $0x4,%rcx\npshufd $0x0,%xmm7,%xmm7\nadd %rdi,%rcx\nnopw 0x0(%rax,%rax,1)\nmovdqu (%rax),%xmm0\nmovdqa %xmm4,%xmm6\nadd $0x10,%rax\npcmpeqb %xmm7,%xmm0\npand %xmm5,%xmm0\npcmpgtb %xmm0,%xmm6\nmovdqa %xmm0,%xmm2\npunpcklbw %xmm6,%xmm2\npunpckhbw %xmm6,%xmm0\nmovdqa %xmm3,%xmm6\npcmpgtw %xmm2,%xmm6\nmovdqa %xmm2,%xmm8\npunpcklwd %xmm6,%xmm8\npunpckhwd %xmm6,%xmm2\nmovdqa %xmm0,%xmm6\npaddd %xmm8,%xmm1\npaddd %xmm2,%xmm1\nmovdqa %xmm3,%xmm2\npcmpgtw %xmm0,%xmm2\npunpcklwd %xmm2,%xmm6\npunpckhwd %xmm2,%xmm0\npaddd %xmm6,%xmm1\npaddd %xmm0,%xmm1\ncmp %rax,%rcx\njne 12b0 \nmovdqa %xmm1,%xmm0\nmov %edx,%ecx\npsrldq $0x8,%xmm0\nand $0xfffffff0,%ecx\npaddd %xmm1,%xmm0\nmovdqa %xmm0,%xmm1\npsrldq $0x4,%xmm1\npaddd %xmm1,%xmm0\nmovd %xmm0,%eax\nadd %eax,%r9d\nlea 0x1(%rcx),%eax\ncmp %ecx,%edx\nje 14c0 \nlea (%rsi,%rax,1),%ecx\nmovslq %ecx,%rcx\ncmp -0x1(%rbx,%rcx,1),%r8b\njne 1356 \nadd $0x1,%r9d\nlea 0x1(%rax),%ecx\ncmp %edx,%ecx\njg 14c0 \nadd %esi,%ecx\nmovslq %ecx,%rcx\ncmp -0x1(%rbx,%rcx,1),%r8b\njne 1371 \nadd $0x1,%r9d\nlea 0x2(%rax),%ecx\ncmp %edx,%ecx\njg 14c0 \nadd %esi,%ecx\nmovslq %ecx,%rcx\ncmp -0x1(%rbx,%rcx,1),%r8b\njne 138c \nadd $0x1,%r9d\nlea 0x3(%rax),%ecx\ncmp %edx,%ecx\njg 14c0 \nadd %esi,%ecx\nmovslq %ecx,%rcx\ncmp -0x1(%rbx,%rcx,1),%r8b\njne 13a7 \nadd $0x1,%r9d\nlea 0x4(%rax),%ecx\ncmp %edx,%ecx\njg 14c0 \nadd %esi,%ecx\nmovslq %ecx,%rcx\ncmp -0x1(%rbx,%rcx,1),%r8b\njne 13c2 \nadd $0x1,%r9d\nlea 0x5(%rax),%ecx\ncmp %edx,%ecx\njg 14c0 \nadd %esi,%ecx\nmovslq %ecx,%rcx\ncmp -0x1(%rbx,%rcx,1),%r8b\njne 13dd \nadd $0x1,%r9d\nlea 0x6(%rax),%ecx\ncmp %edx,%ecx\njg 14c0 \nadd %esi,%ecx\nmovslq %ecx,%rcx\ncmp -0x1(%rbx,%rcx,1),%r8b\njne 13f8 \nadd $0x1,%r9d\nlea 0x7(%rax),%ecx\ncmp %ecx,%edx\njl 14c0 \nadd %esi,%ecx\nmovslq %ecx,%rcx\ncmp -0x1(%rbx,%rcx,1),%r8b\njne 1413 \nadd $0x1,%r9d\nlea 0x8(%rax),%ecx\ncmp %ecx,%edx\njl 14c0 \nadd %esi,%ecx\nmovslq %ecx,%rcx\ncmp -0x1(%rbx,%rcx,1),%r8b\njne 142e \nadd $0x1,%r9d\nlea 0x9(%rax),%ecx\ncmp %ecx,%edx\njl 14c0 \nadd %esi,%ecx\nmovslq %ecx,%rcx\ncmp -0x1(%rbx,%rcx,1),%r8b\njne 1449 \nadd $0x1,%r9d\nlea 0xa(%rax),%ecx\ncmp %ecx,%edx\njl 14c0 \nadd %esi,%ecx\nmovslq %ecx,%rcx\ncmp -0x1(%rbx,%rcx,1),%r8b\njne 1460 \nadd $0x1,%r9d\nlea 0xb(%rax),%ecx\ncmp %ecx,%edx\njl 14c0 \nadd %esi,%ecx\nmovslq %ecx,%rcx\ncmp -0x1(%rbx,%rcx,1),%r8b\njne 1477 \nadd $0x1,%r9d\nlea 0xc(%rax),%ecx\ncmp %ecx,%edx\njl 14c0 \nadd %esi,%ecx\nmovslq %ecx,%rcx\ncmp -0x1(%rbx,%rcx,1),%r8b\njne 148e \nadd $0x1,%r9d\nmov %ebp,%ecx\nlea 0xd(%rax),%edx\nsub %esi,%ecx\ncmp %ecx,%edx\njg 14c0 \nadd %esi,%edx\nmovslq %edx,%rdx\ncmp -0x1(%rbx,%rdx,1),%r8b\njne 14a9 \nadd $0x1,%r9d\nadd $0xe,%eax\ncmp %eax,%ecx\njl 14c0 \nadd %esi,%eax\ncltq\ncmp -0x1(%rbx,%rax,1),%r8b\njne 14c0 \nadd $0x1,%r9d\nadd $0x1,%esi\nadd $0x1,%rdi\nmov %r10d,%edx\ncmp %esi,%r11d\njne 1270 \nadd $0x8,%rsp\nmov %r9d,%eax\npop %rbx\npop %rbp\nretq\nnopl (%rax)\nmov $0x1,%eax\njmpq 1345 \nadd $0x8,%rsp\nxor %r9d,%r9d\nmov %r9d,%eax\npop %rbx\npop %rbp\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\ncall _strlen\ntest eax, eax\njle loc_151D\nmov rcx, rax\nmov r10, rbx\nxor r11d, r11d\nxor edi, edi\npxor xmm6, xmm6\npxor xmm5, xmm5\npxor xmm4, xmm4\npxor xmm3, xmm3\nnop word ptr [rax+rax+00000000h]\nloc_1270:\nlea r8d, [rcx-1]\nmovzx edx, byte ptr [r10]\nmov esi, r11d\ncmp r8d, 0Eh\njbe loc_14E0\nmovd xmm8, edx\nmov r9d, ecx\npxor xmm1, xmm1\nmov rax, r10\npunpcklbw xmm8, xmm8\nshr r9d, 4\npunpcklwd xmm8, xmm8\nshl r9, 4\npshufd xmm8, xmm8, 0\nadd r9, r10\nnop\nloc_12B0:\nmovdqu xmm0, xmmword ptr [rax]\nmovdqa xmm7, xmm4\nadd rax, 10h\npcmpeqb xmm0, xmm8\npcmpgtb xmm7, xmm0\nmovdqa xmm2, xmm0\npunpcklbw xmm2, xmm7\npunpckhbw xmm0, xmm7\nmovdqa xmm7, xmm3\npcmpgtw xmm7, xmm2\nmovdqa xmm9, xmm2\npunpcklwd xmm9, xmm7\npunpckhwd xmm2, xmm7\nmovdqa xmm7, xmm0\npsubd xmm1, xmm9\npsubd xmm1, xmm2\nmovdqa xmm2, xmm3\npcmpgtw xmm2, xmm0\npunpcklwd xmm7, xmm2\npunpckhwd xmm0, xmm2\npsubd xmm1, xmm7\npsubd xmm1, xmm0\ncmp r9, rax\njnz short loc_12B0\nmovdqa xmm0, xmm1\nmov ebp, ecx\npsrldq xmm0, 8\nand ebp, 0FFFFFFF0h\npaddd xmm0, xmm1\nlea r14d, [rbp+1]\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\npaddd xmm0, xmm2\nmovd eax, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm1, 8\npaddd xmm0, xmm1\nlea r12d, [rax+rdi]\ntest cl, 0Fh\njz loc_1510\nmov r9d, ecx\nsub r9d, ebp\nlea r13d, [r9-1]\ncmp r13d, 6\njbe loc_1508\nloc_1366:\nlea r12, [rbx+r11]\nmovdqa xmm7, xmm6\nmovq xmm2, qword ptr [r12+rbp]\nmovzx ebp, dl\nmov eax, ebp\nmov ah, al\nmov ebp, eax\nmovd xmm1, ebp\npshuflw xmm1, xmm1, 0\npcmpeqb xmm2, xmm1\npcmpgtb xmm7, xmm2\nmovdqa xmm1, xmm2\npunpcklbw xmm1, xmm7\npunpcklbw xmm2, xmm7\nmovdqa xmm7, xmm5\npcmpgtw xmm7, xmm1\nmovdqa xmm8, xmm1\npshufd xmm2, xmm2, 4Eh ; 'N'\npunpcklwd xmm8, xmm7\npunpcklwd xmm1, xmm7\nmovdqa xmm7, xmm2\npsubd xmm0, xmm8\npshufd xmm1, xmm1, 4Eh ; 'N'\npsubd xmm0, xmm1\nmovdqa xmm1, xmm5\npcmpgtw xmm1, xmm2\npunpcklwd xmm7, xmm1\npunpcklwd xmm2, xmm1\npsubd xmm0, xmm7\npshufd xmm2, xmm2, 4Eh ; 'N'\npsubd xmm0, xmm2\nmovd r12d, xmm0\npshufd xmm1, xmm0, 0E5h\nmovd ebp, xmm1\nadd ebp, r12d\nadd edi, ebp\nmov ebp, r9d\nand ebp, 0FFFFFFF8h\nadd r14d, ebp\nand r9d, 7\njz loc_14D0\nloc_140A:\nlea r9d, [rsi+r14]\nmovsxd r9, r9d\ncmp dl, [rbx+r9-1]\njnz short loc_141B\nadd edi, 1\nloc_141B:\nlea r9d, [r14+1]\ncmp ecx, r9d\njl loc_14D0\nadd r9d, esi\nmovsxd r9, r9d\ncmp dl, [rbx+r9-1]\njnz short loc_1438\nadd edi, 1\nloc_1438:\nlea r9d, [r14+2]\ncmp ecx, r9d\njl short loc_14B8\nadd r9d, esi\nmovsxd r9, r9d\ncmp dl, [rbx+r9-1]\njnz short loc_1451\nadd edi, 1\nloc_1451:\nlea r9d, [r14+3]\ncmp ecx, r9d\njl short loc_14B8\nadd r9d, esi\nmovsxd r9, r9d\ncmp dl, [rbx+r9-1]\njnz short loc_146A\nadd edi, 1\nloc_146A:\nlea r9d, [r14+4]\ncmp ecx, r9d\njl short loc_14B8\nadd r9d, esi\nmovsxd r9, r9d\ncmp dl, [rbx+r9-1]\njnz short loc_1483\nadd edi, 1\nloc_1483:\nlea r9d, [r14+5]\ncmp ecx, r9d\njl short loc_14B8\nadd r9d, esi\nmovsxd r9, r9d\ncmp dl, [rbx+r9-1]\njnz short loc_149C\nadd edi, 1\nloc_149C:\nlea eax, [r14+6]\ncmp ecx, eax\njl short loc_14B8\nadd esi, eax\nmovsxd rsi, esi\ncmp dl, [rbx+rsi-1]\njnz short loc_14B8\nadd edi, 1\nnop word ptr [rax+rax+00h]\nloc_14B8:\nadd r11, 1\nadd r10, 1\nloc_14C0:\nmov ecx, r8d\njmp loc_1270\nloc_14D0:\ntest r8d, r8d\njnz short loc_14B8\npop rbx\nmov eax, edi\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_14E0:\nxor ebp, ebp\nmov r9d, ecx\nmov r12d, edi\nmov r14d, 1\nsub r9d, ebp\npxor xmm0, xmm0\nlea r13d, [r9-1]\ncmp r13d, 6\nja loc_1366\nnop dword ptr [rax+rax+00h]\nloc_1508:\nmov edi, r12d\njmp loc_140A\nloc_1510:\nadd r11, 1\nadd r10, 1\nmov edi, r12d\njmp short loc_14C0\nloc_151D:\nxor edi, edi\npop rbx\npop rbp\nmov eax, edi\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v2; // eax\n int v3; // ecx\n const __m128i *v4; // r10\n __int64 v5; // r11\n unsigned int v6; // edi\n unsigned int v7; // edx\n __m128i v8; // xmm8\n __m128i v9; // xmm1\n const __m128i *v10; // rax\n __m128i v11; // xmm8\n __m128i v12; // xmm8\n __m128i v13; // xmm0\n __m128i v14; // xmm0\n __m128i v15; // xmm7\n __m128i v16; // xmm2\n __m128i v17; // xmm0\n __m128i v18; // xmm7\n __m128i v19; // xmm1\n __m128i v20; // xmm2\n __int64 v21; // rbp\n __m128i v22; // xmm0\n int v23; // r14d\n int v24; // eax\n __m128i v25; // xmm0\n unsigned int v26; // r12d\n int v27; // r9d\n unsigned int v28; // eax\n __m128i v29; // xmm2\n __m128i v30; // xmm1\n __m128i v31; // xmm2\n __m128i v32; // xmm1\n __m128i v33; // xmm2\n __m128i v34; // xmm0\n\n v2 = strlen(a1);\n if ( v2 > 0 )\n {\n v3 = v2;\n v4 = (const __m128i *)a1;\n v5 = 0LL;\n v6 = 0;\n while ( 1 )\n {\n v7 = v4->m128i_u8[0];\n if ( (unsigned int)(v3 - 1) <= 0xE )\n break;\n v8 = _mm_cvtsi32_si128(v7);\n v9 = 0LL;\n v10 = v4;\n v11 = _mm_unpacklo_epi8(v8, v8);\n v12 = _mm_shuffle_epi32(_mm_unpacklo_epi16(v11, v11), 0);\n do\n {\n v13 = _mm_loadu_si128(v10++);\n v14 = _mm_cmpeq_epi8(v13, v12);\n v15 = _mm_cmpgt_epi8((__m128i)0LL, v14);\n v16 = _mm_unpacklo_epi8(v14, v15);\n v17 = _mm_unpackhi_epi8(v14, v15);\n v18 = _mm_cmpgt_epi16((__m128i)0LL, v16);\n v19 = _mm_sub_epi32(_mm_sub_epi32(v9, _mm_unpacklo_epi16(v16, v18)), _mm_unpackhi_epi16(v16, v18));\n v20 = _mm_cmpgt_epi16((__m128i)0LL, v17);\n v9 = _mm_sub_epi32(_mm_sub_epi32(v19, _mm_unpacklo_epi16(v17, v20)), _mm_unpackhi_epi16(v17, v20));\n }\n while ( &v4[(unsigned int)v3 >> 4] != v10 );\n v21 = v3 & 0xFFFFFFF0;\n v22 = _mm_add_epi32(_mm_srli_si128(v9, 8), v9);\n v23 = v21 + 1;\n v24 = _mm_cvtsi128_si32(_mm_add_epi32(v22, _mm_srli_si128(v22, 4)));\n v25 = _mm_add_epi32(v9, _mm_srli_si128(v9, 8));\n v26 = v24 + v6;\n if ( (v3 & 0xF) != 0 )\n {\n v27 = v3 - v21;\n if ( (unsigned int)(v3 - v21 - 1) > 6 )\n goto LABEL_8;\nLABEL_34:\n v6 = v26;\n goto LABEL_9;\n }\n ++v5;\n v4 = (const __m128i *)((char *)v4 + 1);\n v6 += v24;\nLABEL_30:\n --v3;\n }\n v21 = 0LL;\n v26 = v6;\n v23 = 1;\n v27 = v3;\n v25 = 0LL;\n if ( (unsigned int)(v3 - 1) <= 6 )\n goto LABEL_34;\nLABEL_8:\n v28 = (unsigned __int8)v7;\n BYTE1(v28) = v4->m128i_i8[0];\n v29 = _mm_cmpeq_epi8(\n _mm_loadl_epi64((const __m128i *)&a1[v5 + v21]),\n _mm_shufflelo_epi16(_mm_cvtsi32_si128(v28), 0));\n v30 = _mm_unpacklo_epi8(v29, _mm_cmpgt_epi8((__m128i)0LL, v29));\n v31 = _mm_shuffle_epi32(v30, 78);\n v32 = _mm_unpacklo_epi16(v30, _mm_cmpgt_epi16((__m128i)0LL, v30));\n v33 = _mm_unpacklo_epi16(v31, _mm_cmpgt_epi16((__m128i)0LL, v31));\n v34 = _mm_sub_epi32(\n _mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(v25, v32), _mm_shuffle_epi32(v32, 78)), v33),\n _mm_shuffle_epi32(v33, 78));\n v6 += _mm_cvtsi128_si32(v34) + _mm_cvtsi128_si32(_mm_shuffle_epi32(v34, 229));\n v23 += v27 & 0xFFFFFFF8;\n if ( (v27 & 7) != 0 )\n {\nLABEL_9:\n if ( (_BYTE)v7 == a1[(int)v5 - 1 + v23] )\n ++v6;\n if ( v3 >= v23 + 1 )\n {\n if ( (_BYTE)v7 == a1[(int)v5 + v23] )\n ++v6;\n if ( v3 >= v23 + 2 )\n {\n if ( (_BYTE)v7 == a1[(int)v5 + 1 + v23] )\n ++v6;\n if ( v3 >= v23 + 3 )\n {\n if ( (_BYTE)v7 == a1[(int)v5 + 2 + v23] )\n ++v6;\n if ( v3 >= v23 + 4 )\n {\n if ( (_BYTE)v7 == a1[(int)v5 + 3 + v23] )\n ++v6;\n if ( v3 >= v23 + 5 )\n {\n if ( (_BYTE)v7 == a1[(int)v5 + 4 + v23] )\n ++v6;\n if ( v3 >= v23 + 6 && (_BYTE)v7 == a1[v23 + 5 + (int)v5] )\n ++v6;\n }\n }\n }\n }\nLABEL_29:\n ++v5;\n v4 = (const __m128i *)((char *)v4 + 1);\n goto LABEL_30;\n }\n }\n if ( v3 == 1 )\n return v6;\n goto LABEL_29;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1230:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\ncall _strlen\ntest eax, eax\njle loc_151D\nmov rcx, rax\nmov r10, rbx\nxor r11d, r11d\nxor edi, edi\npxor xmm6, xmm6\npxor xmm5, xmm5\npxor xmm4, xmm4\npxor xmm3, xmm3\nnop word ptr [rax+rax+00000000h]\nloc_1270:\nlea r8d, [rcx-1]\nmovzx edx, byte ptr [r10]\nmov esi, r11d\ncmp r8d, 0Eh\njbe loc_14E0\nmovd xmm8, edx\nmov r9d, ecx\npxor xmm1, xmm1\nmov rax, r10\npunpcklbw xmm8, xmm8\nshr r9d, 4\npunpcklwd xmm8, xmm8\nshl r9, 4\npshufd xmm8, xmm8, 0\nadd r9, r10\nnop\nloc_12B0:\nmovdqu xmm0, xmmword ptr [rax]\nmovdqa xmm7, xmm4\nadd rax, 10h\npcmpeqb xmm0, xmm8\npcmpgtb xmm7, xmm0\nmovdqa xmm2, xmm0\npunpcklbw xmm2, xmm7\npunpckhbw xmm0, xmm7\nmovdqa xmm7, xmm3\npcmpgtw xmm7, xmm2\nmovdqa xmm9, xmm2\npunpcklwd xmm9, xmm7\npunpckhwd xmm2, xmm7\nmovdqa xmm7, xmm0\npsubd xmm1, xmm9\npsubd xmm1, xmm2\nmovdqa xmm2, xmm3\npcmpgtw xmm2, xmm0\npunpcklwd xmm7, xmm2\npunpckhwd xmm0, xmm2\npsubd xmm1, xmm7\npsubd xmm1, xmm0\ncmp r9, rax\njnz short loc_12B0\nmovdqa xmm0, xmm1\nmov ebp, ecx\npsrldq xmm0, 8\nand ebp, 0FFFFFFF0h\npaddd xmm0, xmm1\nlea r14d, [rbp+1]\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\npaddd xmm0, xmm2\nmovd eax, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm1, 8\npaddd xmm0, xmm1\nlea r12d, [rax+rdi]\ntest cl, 0Fh\njz loc_1510\nmov r9d, ecx\nsub r9d, ebp\nlea r13d, [r9-1]\ncmp r13d, 6\njbe loc_1508\nloc_1366:\nlea r12, [rbx+r11]\nmovdqa xmm7, xmm6\nmovq xmm2, qword ptr [r12+rbp]\nmovzx ebp, dl\nmov eax, ebp\nmov ah, al\nmov ebp, eax\nmovd xmm1, ebp\npshuflw xmm1, xmm1, 0\npcmpeqb xmm2, xmm1\npcmpgtb xmm7, xmm2\nmovdqa xmm1, xmm2\npunpcklbw xmm1, xmm7\npunpcklbw xmm2, xmm7\nmovdqa xmm7, xmm5\npcmpgtw xmm7, xmm1\nmovdqa xmm8, xmm1\npshufd xmm2, xmm2, 4Eh ; 'N'\npunpcklwd xmm8, xmm7\npunpcklwd xmm1, xmm7\nmovdqa xmm7, xmm2\npsubd xmm0, xmm8\npshufd xmm1, xmm1, 4Eh ; 'N'\npsubd xmm0, xmm1\nmovdqa xmm1, xmm5\npcmpgtw xmm1, xmm2\npunpcklwd xmm7, xmm1\npunpcklwd xmm2, xmm1\npsubd xmm0, xmm7\npshufd xmm2, xmm2, 4Eh ; 'N'\npsubd xmm0, xmm2\nmovd r12d, xmm0\npshufd xmm1, xmm0, 0E5h\nmovd ebp, xmm1\nadd ebp, r12d\nadd edi, ebp\nmov ebp, r9d\nand ebp, 0FFFFFFF8h\nadd r14d, ebp\nand r9d, 7\njz loc_14D0\nloc_140A:\nlea r9d, [rsi+r14]\nmovsxd r9, r9d\ncmp dl, [rbx+r9-1]\njnz short loc_141B\nadd edi, 1\nloc_141B:\nlea r9d, [r14+1]\ncmp ecx, r9d\njl loc_14D0\nadd r9d, esi\nmovsxd r9, r9d\ncmp dl, [rbx+r9-1]\njnz short loc_1438\nadd edi, 1\nloc_1438:\nlea r9d, [r14+2]\ncmp ecx, r9d\njl short loc_14B8\nadd r9d, esi\nmovsxd r9, r9d\ncmp dl, [rbx+r9-1]\njnz short loc_1451\nadd edi, 1\nloc_1451:\nlea r9d, [r14+3]\ncmp ecx, r9d\njl short loc_14B8\nadd r9d, esi\nmovsxd r9, r9d\ncmp dl, [rbx+r9-1]\njnz short loc_146A\nadd edi, 1\nloc_146A:\nlea r9d, [r14+4]\ncmp ecx, r9d\njl short loc_14B8\nadd r9d, esi\nmovsxd r9, r9d\ncmp dl, [rbx+r9-1]\njnz short loc_1483\nadd edi, 1\nloc_1483:\nlea r9d, [r14+5]\ncmp ecx, r9d\njl short loc_14B8\nadd r9d, esi\nmovsxd r9, r9d\ncmp dl, [rbx+r9-1]\njnz short loc_149C\nadd edi, 1\nloc_149C:\nlea eax, [r14+6]\ncmp ecx, eax\njl short loc_14B8\nadd esi, eax\nmovsxd rsi, esi\ncmp dl, [rbx+rsi-1]\njnz short loc_14B8\nadd edi, 1\nnop word ptr [rax+rax+00h]\nloc_14B8:\nadd r11, 1\nadd r10, 1\nloc_14C0:\nmov ecx, r8d\njmp loc_1270\nloc_14D0:\ntest r8d, r8d\njnz short loc_14B8\npop rbx\nmov eax, edi\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_14E0:\nxor ebp, ebp\nmov r9d, ecx\nmov r12d, edi\nmov r14d, 1\nsub r9d, ebp\npxor xmm0, xmm0\nlea r13d, [r9-1]\ncmp r13d, 6\nja loc_1366\nnop dword ptr [rax+rax+00h]\nloc_1508:\nmov edi, r12d\njmp loc_140A\nloc_1510:\nadd r11, 1\nadd r10, 1\nmov edi, r12d\njmp short loc_14C0\nloc_151D:\nxor edi, edi\npop rbx\npop rbp\nmov eax, edi\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1230(const char *a1)\n{\n int v2; // eax\n int v3; // ecx\n const __m128i *v4; // r10\n __int64 v5; // r11\n unsigned int v6; // edi\n unsigned int v7; // edx\n __m128i v8; // xmm8\n __m128i v9; // xmm1\n const __m128i *v10; // rax\n __m128i v11; // xmm8\n __m128i v12; // xmm8\n __m128i v13; // xmm0\n __m128i v14; // xmm0\n __m128i v15; // xmm7\n __m128i v16; // xmm2\n __m128i v17; // xmm0\n __m128i v18; // xmm7\n __m128i v19; // xmm1\n __m128i v20; // xmm2\n __int64 v21; // rbp\n __m128i v22; // xmm0\n int v23; // r14d\n int v24; // eax\n __m128i v25; // xmm0\n unsigned int v26; // r12d\n int v27; // r9d\n unsigned int v28; // eax\n __m128i v29; // xmm2\n __m128i v30; // xmm1\n __m128i v31; // xmm2\n __m128i v32; // xmm1\n __m128i v33; // xmm2\n __m128i v34; // xmm0\n\n v2 = strlen(a1);\n if ( v2 > 0 )\n {\n v3 = v2;\n v4 = (const __m128i *)a1;\n v5 = 0LL;\n v6 = 0;\n while ( 1 )\n {\n v7 = v4->m128i_u8[0];\n if ( (unsigned int)(v3 - 1) <= 0xE )\n break;\n v8 = _mm_cvtsi32_si128(v7);\n v9 = 0LL;\n v10 = v4;\n v11 = _mm_unpacklo_epi8(v8, v8);\n v12 = _mm_shuffle_epi32(_mm_unpacklo_epi16(v11, v11), 0);\n do\n {\n v13 = _mm_loadu_si128(v10++);\n v14 = _mm_cmpeq_epi8(v13, v12);\n v15 = _mm_cmpgt_epi8((__m128i)0LL, v14);\n v16 = _mm_unpacklo_epi8(v14, v15);\n v17 = _mm_unpackhi_epi8(v14, v15);\n v18 = _mm_cmpgt_epi16((__m128i)0LL, v16);\n v19 = _mm_sub_epi32(_mm_sub_epi32(v9, _mm_unpacklo_epi16(v16, v18)), _mm_unpackhi_epi16(v16, v18));\n v20 = _mm_cmpgt_epi16((__m128i)0LL, v17);\n v9 = _mm_sub_epi32(_mm_sub_epi32(v19, _mm_unpacklo_epi16(v17, v20)), _mm_unpackhi_epi16(v17, v20));\n }\n while ( &v4[(unsigned int)v3 >> 4] != v10 );\n v21 = v3 & 0xFFFFFFF0;\n v22 = _mm_add_epi32(_mm_srli_si128(v9, 8), v9);\n v23 = v21 + 1;\n v24 = _mm_cvtsi128_si32(_mm_add_epi32(v22, _mm_srli_si128(v22, 4)));\n v25 = _mm_add_epi32(v9, _mm_srli_si128(v9, 8));\n v26 = v24 + v6;\n if ( (v3 & 0xF) != 0 )\n {\n v27 = v3 - v21;\n if ( (unsigned int)(v3 - v21 - 1) > 6 )\n goto LABEL_8;\nLABEL_34:\n v6 = v26;\n goto LABEL_9;\n }\n ++v5;\n v4 = (const __m128i *)((char *)v4 + 1);\n v6 += v24;\nLABEL_30:\n --v3;\n }\n v21 = 0LL;\n v26 = v6;\n v23 = 1;\n v27 = v3;\n v25 = 0LL;\n if ( (unsigned int)(v3 - 1) <= 6 )\n goto LABEL_34;\nLABEL_8:\n v28 = (unsigned __int8)v7;\n BYTE1(v28) = v4->m128i_i8[0];\n v29 = _mm_cmpeq_epi8(\n _mm_loadl_epi64((const __m128i *)&a1[v5 + v21]),\n _mm_shufflelo_epi16(_mm_cvtsi32_si128(v28), 0));\n v30 = _mm_unpacklo_epi8(v29, _mm_cmpgt_epi8((__m128i)0LL, v29));\n v31 = _mm_shuffle_epi32(v30, 78);\n v32 = _mm_unpacklo_epi16(v30, _mm_cmpgt_epi16((__m128i)0LL, v30));\n v33 = _mm_unpacklo_epi16(v31, _mm_cmpgt_epi16((__m128i)0LL, v31));\n v34 = _mm_sub_epi32(\n _mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(v25, v32), _mm_shuffle_epi32(v32, 78)), v33),\n _mm_shuffle_epi32(v33, 78));\n v6 += _mm_cvtsi128_si32(v34) + _mm_cvtsi128_si32(_mm_shuffle_epi32(v34, 229));\n v23 += v27 & 0xFFFFFFF8;\n if ( (v27 & 7) != 0 )\n {\nLABEL_9:\n if ( (_BYTE)v7 == a1[(int)v5 - 1 + v23] )\n ++v6;\n if ( v3 >= v23 + 1 )\n {\n if ( (_BYTE)v7 == a1[(int)v5 + v23] )\n ++v6;\n if ( v3 >= v23 + 2 )\n {\n if ( (_BYTE)v7 == a1[(int)v5 + 1 + v23] )\n ++v6;\n if ( v3 >= v23 + 3 )\n {\n if ( (_BYTE)v7 == a1[(int)v5 + 2 + v23] )\n ++v6;\n if ( v3 >= v23 + 4 )\n {\n if ( (_BYTE)v7 == a1[(int)v5 + 3 + v23] )\n ++v6;\n if ( v3 >= v23 + 5 )\n {\n if ( (_BYTE)v7 == a1[(int)v5 + 4 + v23] )\n ++v6;\n if ( v3 >= v23 + 6 && (_BYTE)v7 == a1[v23 + 5 + (int)v5] )\n ++v6;\n }\n }\n }\n }\nLABEL_29:\n ++v5;\n v4 = (const __m128i *)((char *)v4 + 1);\n goto LABEL_30;\n }\n }\n if ( v3 == 1 )\n return v6;\n goto LABEL_29;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1230(const char *a1) {\n int v2;\n int v3;\n const __m128i *v4;\n long long v5;\n unsigned int v6;\n unsigned int v7;\n __m128i v8;\n __m128i v9;\n const __m128i *v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n __m128i v15;\n __m128i v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n __m128i v20;\n long long v21;\n __m128i v22;\n int v23;\n int v24;\n __m128i v25;\n unsigned int v26;\n int v27;\n unsigned int v28;\n __m128i v29;\n __m128i v30;\n __m128i v31;\n __m128i v32;\n __m128i v33;\n __m128i v34;\n v2 = strlen(a1);\n if (v2 > 0) {\n v3 = v2;\n v4 = (const __m128i *)a1;\n v5 = 0LL;\n v6 = 0;\n while (1) {\n v7 = v4->m128i_u8[0];\n if ((unsigned int)(v3 - 1) <= 14) break;\n v8 = _mm_cvtsi32_si128(v7);\n v9 = 0LL;\n v10 = v4;\n v11 = _mm_unpacklo_epi8(v8, v8);\n v12 = _mm_shuffle_epi32(_mm_unpacklo_epi16(v11, v11), 0);\n do {\n v13 = _mm_loadu_si128(v10++);\n v14 = _mm_cmpeq_epi8(v13, v12);\n v15 = _mm_cmpgt_epi8((__m128i)0LL, v14);\n v16 = _mm_unpacklo_epi8(v14, v15);\n v17 = _mm_unpackhi_epi8(v14, v15);\n v18 = _mm_cmpgt_epi16((__m128i)0LL, v16);\n v19 = _mm_sub_epi32(_mm_sub_epi32(v9, _mm_unpacklo_epi16(v16, v18)),\n _mm_unpackhi_epi16(v16, v18));\n v20 = _mm_cmpgt_epi16((__m128i)0LL, v17);\n v9 = _mm_sub_epi32(_mm_sub_epi32(v19, _mm_unpacklo_epi16(v17, v20)),\n _mm_unpackhi_epi16(v17, v20));\n } while (&v4[(unsigned int)v3 >> 4] != v10);\n v21 = v3 & 4294967280;\n v22 = _mm_add_epi32(_mm_srli_si128(v9, 8), v9);\n v23 = v21 + 1;\n v24 = _mm_cvtsi128_si32(_mm_add_epi32(v22, _mm_srli_si128(v22, 4)));\n v25 = _mm_add_epi32(v9, _mm_srli_si128(v9, 8));\n v26 = v24 + v6;\n if ((v3 & 15) != 0) {\n v27 = v3 - v21;\n if ((unsigned int)(v3 - v21 - 1) > 6) goto LABEL_8;\n LABEL_34:\n v6 = v26;\n goto LABEL_9;\n }\n ++v5;\n v4 = (const __m128i *)((char *)v4 + 1);\n v6 += v24;\n LABEL_30:\n --v3;\n }\n v21 = 0LL;\n v26 = v6;\n v23 = 1;\n v27 = v3;\n v25 = 0LL;\n if ((unsigned int)(v3 - 1) <= 6) goto LABEL_34;\n LABEL_8:\n v28 = (unsigned char)v7;\n BYTE1(v28) = v4->m128i_i8[0];\n v29 = _mm_cmpeq_epi8(_mm_loadl_epi64((const __m128i *)&a1[v5 + v21]),\n _mm_shufflelo_epi16(_mm_cvtsi32_si128(v28), 0));\n v30 = _mm_unpacklo_epi8(v29, _mm_cmpgt_epi8((__m128i)0LL, v29));\n v31 = _mm_shuffle_epi32(v30, 78);\n v32 = _mm_unpacklo_epi16(v30, _mm_cmpgt_epi16((__m128i)0LL, v30));\n v33 = _mm_unpacklo_epi16(v31, _mm_cmpgt_epi16((__m128i)0LL, v31));\n v34 = _mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(v25, v32),\n _mm_shuffle_epi32(v32, 78)),\n v33),\n _mm_shuffle_epi32(v33, 78));\n v6 +=\n _mm_cvtsi128_si32(v34) + _mm_cvtsi128_si32(_mm_shuffle_epi32(v34, 229));\n v23 += v27 & 4294967288;\n if ((v27 & 7) != 0) {\n LABEL_9:\n if ((uint8_t)v7 == a1[(int)v5 - 1 + v23]) ++v6;\n if (v3 >= v23 + 1) {\n if ((uint8_t)v7 == a1[(int)v5 + v23]) ++v6;\n if (v3 >= v23 + 2) {\n if ((uint8_t)v7 == a1[(int)v5 + 1 + v23]) ++v6;\n if (v3 >= v23 + 3) {\n if ((uint8_t)v7 == a1[(int)v5 + 2 + v23]) ++v6;\n if (v3 >= v23 + 4) {\n if ((uint8_t)v7 == a1[(int)v5 + 3 + v23]) ++v6;\n if (v3 >= v23 + 5) {\n if ((uint8_t)v7 == a1[(int)v5 + 4 + v23]) ++v6;\n if (v3 >= v23 + 6 && (uint8_t)v7 == a1[v23 + 5 + (int)v5]) ++v6;\n }\n }\n }\n }\n LABEL_29:\n ++v5;\n v4 = (const __m128i *)((char *)v4 + 1);\n goto LABEL_30;\n }\n }\n if (v3 == 1) return v6;\n goto LABEL_29;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v2;\n int v3;\n const __m128i *v4;\n long long v5;\n unsigned int v6;\n unsigned int v7;\n __m128i v8;\n __m128i v9;\n const __m128i *v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n __m128i v15;\n __m128i v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n __m128i v20;\n long long v21;\n __m128i v22;\n int v23;\n int v24;\n __m128i v25;\n unsigned int v26;\n int v27;\n unsigned int v28;\n __m128i v29;\n __m128i v30;\n __m128i v31;\n __m128i v32;\n __m128i v33;\n __m128i v34;\n v2 = strlen(a1);\n if (v2 > 0) {\n v3 = v2;\n v4 = (const __m128i *)a1;\n v5 = 0LL;\n v6 = 0;\n while (1) {\n v7 = v4->m128i_u8[0];\n if ((unsigned int)(v3 - 1) <= 14) break;\n v8 = _mm_cvtsi32_si128(v7);\n v9 = 0LL;\n v10 = v4;\n v11 = _mm_unpacklo_epi8(v8, v8);\n v12 = _mm_shuffle_epi32(_mm_unpacklo_epi16(v11, v11), 0);\n do {\n v13 = _mm_loadu_si128(v10++);\n v14 = _mm_cmpeq_epi8(v13, v12);\n v15 = _mm_cmpgt_epi8((__m128i)0LL, v14);\n v16 = _mm_unpacklo_epi8(v14, v15);\n v17 = _mm_unpackhi_epi8(v14, v15);\n v18 = _mm_cmpgt_epi16((__m128i)0LL, v16);\n v19 = _mm_sub_epi32(_mm_sub_epi32(v9, _mm_unpacklo_epi16(v16, v18)),\n _mm_unpackhi_epi16(v16, v18));\n v20 = _mm_cmpgt_epi16((__m128i)0LL, v17);\n v9 = _mm_sub_epi32(_mm_sub_epi32(v19, _mm_unpacklo_epi16(v17, v20)),\n _mm_unpackhi_epi16(v17, v20));\n } while (&v4[(unsigned int)v3 >> 4] != v10);\n v21 = v3 & 4294967280;\n v22 = _mm_add_epi32(_mm_srli_si128(v9, 8), v9);\n v23 = v21 + 1;\n v24 = _mm_cvtsi128_si32(_mm_add_epi32(v22, _mm_srli_si128(v22, 4)));\n v25 = _mm_add_epi32(v9, _mm_srli_si128(v9, 8));\n v26 = v24 + v6;\n if ((v3 & 15) != 0) {\n v27 = v3 - v21;\n if ((unsigned int)(v3 - v21 - 1) > 6) goto LABEL_8;\n LABEL_34:\n v6 = v26;\n goto LABEL_9;\n }\n ++v5;\n v4 = (const __m128i *)((char *)v4 + 1);\n v6 += v24;\n LABEL_30:\n --v3;\n }\n v21 = 0LL;\n v26 = v6;\n v23 = 1;\n v27 = v3;\n v25 = 0LL;\n if ((unsigned int)(v3 - 1) <= 6) goto LABEL_34;\n LABEL_8:\n v28 = (unsigned char)v7;\n BYTE1(v28) = v4->m128i_i8[0];\n v29 = _mm_cmpeq_epi8(_mm_loadl_epi64((const __m128i *)&a1[v5 + v21]),\n _mm_shufflelo_epi16(_mm_cvtsi32_si128(v28), 0));\n v30 = _mm_unpacklo_epi8(v29, _mm_cmpgt_epi8((__m128i)0LL, v29));\n v31 = _mm_shuffle_epi32(v30, 78);\n v32 = _mm_unpacklo_epi16(v30, _mm_cmpgt_epi16((__m128i)0LL, v30));\n v33 = _mm_unpacklo_epi16(v31, _mm_cmpgt_epi16((__m128i)0LL, v31));\n v34 = _mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(v25, v32),\n _mm_shuffle_epi32(v32, 78)),\n v33),\n _mm_shuffle_epi32(v33, 78));\n v6 +=\n _mm_cvtsi128_si32(v34) + _mm_cvtsi128_si32(_mm_shuffle_epi32(v34, 229));\n v23 += v27 & 4294967288;\n if ((v27 & 7) != 0) {\n LABEL_9:\n if ((uint8_t)v7 == a1[(int)v5 - 1 + v23]) ++v6;\n if (v3 >= v23 + 1) {\n if ((uint8_t)v7 == a1[(int)v5 + v23]) ++v6;\n if (v3 >= v23 + 2) {\n if ((uint8_t)v7 == a1[(int)v5 + 1 + v23]) ++v6;\n if (v3 >= v23 + 3) {\n if ((uint8_t)v7 == a1[(int)v5 + 2 + v23]) ++v6;\n if (v3 >= v23 + 4) {\n if ((uint8_t)v7 == a1[(int)v5 + 3 + v23]) ++v6;\n if (v3 >= v23 + 5) {\n if ((uint8_t)v7 == a1[(int)v5 + 4 + v23]) ++v6;\n if (v3 >= v23 + 6 && (uint8_t)v7 == a1[v23 + 5 + (int)v5]) ++v6;\n }\n }\n }\n }\n LABEL_29:\n ++v5;\n v4 = (const __m128i *)((char *)v4 + 1);\n goto LABEL_30;\n }\n }\n if (v3 == 1) return v6;\n goto LABEL_29;\n }\n return 0LL;\n}" + }, + { + "index": 31, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int key;\n\n int count;\n\n} Element;\n\n\n\nint compare(const void* a, const void* b) {\n\n Element* ea = (Element*)a;\n\n Element* eb = (Element*)b;\n\n if (eb->count != ea->count)\n\n return eb->count - ea->count;\n\n return ea->key - eb->key;\n\n}\n\n\n\n", + "func": "int* func0(int** nums, int numsSize, int* numsColSizes, int k,\n int* returnSize) {\n int max_key = 0;\n for (int i = 0; i < numsSize; i++) {\n for (int j = 0; j < numsColSizes[i]; j++) {\n if (nums[i][j] > max_key) max_key = nums[i][j];\n }\n }\n int* freq = (int*)calloc(max_key + 1, sizeof(int));\n for (int i = 0; i < numsSize; i++) {\n for (int j = 0; j < numsColSizes[i]; j++) {\n freq[nums[i][j]] += 1;\n }\n }\n Element* elements = (Element*)malloc((max_key + 1) * sizeof(Element));\n int count = 0;\n for (int i = 0; i <= max_key; i++) {\n if (freq[i] > 0) {\n elements[count].key = i;\n elements[count].count = freq[i];\n count++;\n }\n }\n qsort(elements, count, sizeof(Element), compare);\n int* result = (int*)malloc(k * sizeof(int));\n for (int i = 0; i < k; i++) {\n result[i] = elements[i].key;\n }\n *returnSize = k;\n free(freq);\n free(elements);\n return result;\n}", + "test": "int main() {\n\n // First test case\n\n int row0[] = {1, 2, 6};\n\n int row1[] = {1, 3, 4, 5, 7, 8};\n\n int row2[] = {1, 3, 5, 6, 8, 9};\n\n int row3[] = {2, 5, 7, 11};\n\n int row4[] = {1, 4, 7, 8, 12};\n\n int* nums1[] = {row0, row1, row2, row3, row4};\n\n int numsColSizes1[] = {3, 6, 6, 4, 5};\n\n int returnSize1;\n\n int* res1 = func0(nums1, 5, numsColSizes1, 3, &returnSize1);\n\n int expected1[] = {1, 5, 7};\n\n for(int i = 0; i < 3; i++) {\n\n assert(res1[i] == expected1[i]);\n\n }\n\n free(res1);\n\n \n\n // Second test case\n\n int returnSize2;\n\n int* res2 = func0(nums1, 5, numsColSizes1, 1, &returnSize2);\n\n int expected2[] = {1};\n\n for(int i = 0; i < 1; i++) {\n\n assert(res2[i] == expected2[i]);\n\n }\n\n free(res2);\n\n \n\n // Third test case\n\n int returnSize3;\n\n int* res3 = func0(nums1, 5, numsColSizes1, 5, &returnSize3);\n\n int expected3[] = {1, 5, 7, 8, 2};\n\n for(int i = 0; i < 5; i++) {\n\n assert(res3[i] == expected3[i]);\n\n }\n\n free(res3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x60,%rsp\nmov %rdi,-0x48(%rbp)\nmov %esi,-0x4c(%rbp)\nmov %rdx,-0x58(%rbp)\nmov %ecx,-0x50(%rbp)\nmov %r8,-0x60(%rbp)\nmovl $0x0,-0x38(%rbp)\nmovl $0x0,-0x34(%rbp)\njmpq 12f2 \nmovl $0x0,-0x30(%rbp)\njmp 12d3 \nmov -0x34(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0x30(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x2,%rdx\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x38(%rbp)\njge 12cf \nmov -0x34(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0x30(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x2,%rdx\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x38(%rbp)\naddl $0x1,-0x30(%rbp)\nmov -0x34(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x58(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x30(%rbp)\njl 127b \naddl $0x1,-0x34(%rbp)\nmov -0x34(%rbp),%eax\ncmp -0x4c(%rbp),%eax\njl 1272 \nmov -0x38(%rbp),%eax\nadd $0x1,%eax\ncltq\nmov $0x4,%esi\nmov %rax,%rdi\ncallq 10e0 \nmov %rax,-0x18(%rbp)\nmovl $0x0,-0x2c(%rbp)\njmpq 13c8 \nmovl $0x0,-0x28(%rbp)\njmp 13a5 \nmov -0x2c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0x28(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x2,%rdx\nadd %rdx,%rax\nmov (%rax),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x2c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x48(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%rax\nmov -0x28(%rbp),%ecx\nmovslq %ecx,%rcx\nshl $0x2,%rcx\nadd %rcx,%rax\nmov (%rax),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nadd $0x1,%edx\nmov %edx,(%rax)\naddl $0x1,-0x28(%rbp)\nmov -0x2c(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x58(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x28(%rbp)\njl 132c \naddl $0x1,-0x2c(%rbp)\nmov -0x2c(%rbp),%eax\ncmp -0x4c(%rbp),%eax\njl 1323 \nmov -0x38(%rbp),%eax\nadd $0x1,%eax\ncltq\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 10f0 \nmov %rax,-0x10(%rbp)\nmovl $0x0,-0x24(%rbp)\nmovl $0x0,-0x20(%rbp)\njmp 1465 \nmov -0x20(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ntest %eax,%eax\njle 1461 \nmov -0x24(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x10(%rbp),%rax\nadd %rax,%rdx\nmov -0x20(%rbp),%eax\nmov %eax,(%rdx)\nmov -0x20(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0x24(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x10(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,0x4(%rdx)\naddl $0x1,-0x24(%rbp)\naddl $0x1,-0x20(%rbp)\nmov -0x20(%rbp),%eax\ncmp -0x38(%rbp),%eax\njle 13fc \nmov -0x24(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x10(%rbp),%rax\nlea -0x295(%rip),%rcx\nmov $0x8,%edx\nmov %rax,%rdi\ncallq 10b0 \nmov -0x50(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10f0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0x1c(%rbp)\njmp 14da \nmov -0x1c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x10(%rbp),%rax\nadd %rdx,%rax\nmov -0x1c(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x1c(%rbp)\nmov -0x1c(%rbp),%eax\ncmp -0x50(%rbp),%eax\njl 14a9 \nmov -0x60(%rbp),%rax\nmov -0x50(%rbp),%edx\nmov %edx,(%rax)\nmov -0x18(%rbp),%rax\nmov %rax,%rdi\ncallq 10a0 \nmov -0x10(%rbp),%rax\nmov %rax,%rdi\ncallq 10a0 \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 60h\nmov [rbp+var_48], rdi\nmov [rbp+var_4C], esi\nmov [rbp+var_58], rdx\nmov [rbp+var_50], ecx\nmov [rbp+var_60], r8\nmov [rbp+var_38], 0\nmov [rbp+var_34], 0\njmp loc_12F2\nloc_1272:\nmov [rbp+var_30], 0\njmp short loc_12D3\nloc_127B:\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_30]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_38], eax\njge short loc_12CF\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_30]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_38], eax\nloc_12CF:\nadd [rbp+var_30], 1\nloc_12D3:\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_30], eax\njl short loc_127B\nadd [rbp+var_34], 1\nloc_12F2:\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_4C]\njl loc_1272\nmov eax, [rbp+var_38]\nadd eax, 1\ncdqe\nmov esi, 4; size\nmov rdi, rax; nmemb\ncall _calloc\nmov [rbp+ptr], rax\nmov [rbp+var_2C], 0\njmp loc_13C8\nloc_1323:\nmov [rbp+var_28], 0\njmp short loc_13A5\nloc_132C:\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_2C]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nadd rax, rcx\nmov rax, [rax]\nmov ecx, [rbp+var_28]\nmovsxd rcx, ecx\nshl rcx, 2\nadd rax, rcx\nmov eax, [rax]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rcx\nadd edx, 1\nmov [rax], edx\nadd [rbp+var_28], 1\nloc_13A5:\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_28], eax\njl loc_132C\nadd [rbp+var_2C], 1\nloc_13C8:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_4C]\njl loc_1323\nmov eax, [rbp+var_38]\nadd eax, 1\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+base], rax\nmov [rbp+var_24], 0\nmov [rbp+var_20], 0\njmp short loc_1465\nloc_13FC:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njle short loc_1461\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rdx, rax\nmov eax, [rbp+var_20]\nmov [rdx], eax\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+base]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx+4], eax\nadd [rbp+var_24], 1\nloc_1461:\nadd [rbp+var_20], 1\nloc_1465:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_38]\njle short loc_13FC\nmov eax, [rbp+var_24]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compare\nmov rcx, rdx; compar\nmov edx, 8; size\nmov rdi, rax; base\ncall _qsort\nmov eax, [rbp+var_50]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_1C], 0\njmp short loc_14DD\nloc_14AC:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_1C], 1\nloc_14DD:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_50]\njl short loc_14AC\nmov rax, [rbp+var_60]\nmov edx, [rbp+var_50]\nmov [rax], edx\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+base]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, __int64 a3, int a4, _DWORD *a5)\n{\n int v9; // [rsp+28h] [rbp-38h]\n int i; // [rsp+2Ch] [rbp-34h]\n int j; // [rsp+30h] [rbp-30h]\n int k; // [rsp+34h] [rbp-2Ch]\n int m; // [rsp+38h] [rbp-28h]\n int v14; // [rsp+3Ch] [rbp-24h]\n int n; // [rsp+40h] [rbp-20h]\n int ii; // [rsp+44h] [rbp-1Ch]\n _DWORD *ptr; // [rsp+48h] [rbp-18h]\n _DWORD *base; // [rsp+50h] [rbp-10h]\n _DWORD *v19; // [rsp+58h] [rbp-8h]\n\n v9 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = 0; j < *(_DWORD *)(4LL * i + a3); ++j )\n {\n if ( v9 < *(_DWORD *)(4LL * j + *(_QWORD *)(8LL * i + a1)) )\n v9 = *(_DWORD *)(4LL * j + *(_QWORD *)(8LL * i + a1));\n }\n }\n ptr = calloc(v9 + 1, 4uLL);\n for ( k = 0; k < a2; ++k )\n {\n for ( m = 0; m < *(_DWORD *)(4LL * k + a3); ++m )\n ++ptr[*(int *)(4LL * m + *(_QWORD *)(8LL * k + a1))];\n }\n base = malloc(8LL * (v9 + 1));\n v14 = 0;\n for ( n = 0; n <= v9; ++n )\n {\n if ( (int)ptr[n] > 0 )\n {\n base[2 * v14] = n;\n base[2 * v14++ + 1] = ptr[n];\n }\n }\n qsort(base, v14, 8uLL, compare);\n v19 = malloc(4LL * a4);\n for ( ii = 0; ii < a4; ++ii )\n v19[ii] = base[2 * ii];\n *a5 = a4;\n free(ptr);\n free(base);\n return v19;\n}", + "ida_strip_asm": "sub_1241:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 60h\nmov [rbp+var_48], rdi\nmov [rbp+var_4C], esi\nmov [rbp+var_58], rdx\nmov [rbp+var_50], ecx\nmov [rbp+var_60], r8\nmov [rbp+var_38], 0\nmov [rbp+var_34], 0\njmp loc_12F2\nloc_1272:\nmov [rbp+var_30], 0\njmp short loc_12D3\nloc_127B:\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_30]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_38], eax\njge short loc_12CF\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_30]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_38], eax\nloc_12CF:\nadd [rbp+var_30], 1\nloc_12D3:\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_30], eax\njl short loc_127B\nadd [rbp+var_34], 1\nloc_12F2:\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_4C]\njl loc_1272\nmov eax, [rbp+var_38]\nadd eax, 1\ncdqe\nmov esi, 4; size\nmov rdi, rax; nmemb\ncall _calloc\nmov [rbp+ptr], rax\nmov [rbp+var_2C], 0\njmp loc_13C8\nloc_1323:\nmov [rbp+var_28], 0\njmp short loc_13A5\nloc_132C:\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_2C]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nadd rax, rcx\nmov rax, [rax]\nmov ecx, [rbp+var_28]\nmovsxd rcx, ecx\nshl rcx, 2\nadd rax, rcx\nmov eax, [rax]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rcx\nadd edx, 1\nmov [rax], edx\nadd [rbp+var_28], 1\nloc_13A5:\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_28], eax\njl loc_132C\nadd [rbp+var_2C], 1\nloc_13C8:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_4C]\njl loc_1323\nmov eax, [rbp+var_38]\nadd eax, 1\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+base], rax\nmov [rbp+var_24], 0\nmov [rbp+var_20], 0\njmp short loc_1465\nloc_13FC:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njle short loc_1461\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rdx, rax\nmov eax, [rbp+var_20]\nmov [rdx], eax\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+base]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx+4], eax\nadd [rbp+var_24], 1\nloc_1461:\nadd [rbp+var_20], 1\nloc_1465:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_38]\njle short loc_13FC\nmov eax, [rbp+var_24]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 8; size\nmov rdi, rax; base\ncall _qsort\nmov eax, [rbp+var_50]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_1C], 0\njmp short loc_14DD\nloc_14AC:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_1C], 1\nloc_14DD:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_50]\njl short loc_14AC\nmov rax, [rbp+var_60]\nmov edx, [rbp+var_50]\nmov [rax], edx\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+base]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1241(__int64 a1, int a2, __int64 a3, int a4, _DWORD *a5)\n{\n int v9; // [rsp+28h] [rbp-38h]\n int i; // [rsp+2Ch] [rbp-34h]\n int j; // [rsp+30h] [rbp-30h]\n int k; // [rsp+34h] [rbp-2Ch]\n int m; // [rsp+38h] [rbp-28h]\n int v14; // [rsp+3Ch] [rbp-24h]\n int n; // [rsp+40h] [rbp-20h]\n int ii; // [rsp+44h] [rbp-1Ch]\n _DWORD *ptr; // [rsp+48h] [rbp-18h]\n _DWORD *base; // [rsp+50h] [rbp-10h]\n _DWORD *v19; // [rsp+58h] [rbp-8h]\n\n v9 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = 0; j < *(_DWORD *)(4LL * i + a3); ++j )\n {\n if ( v9 < *(_DWORD *)(4LL * j + *(_QWORD *)(8LL * i + a1)) )\n v9 = *(_DWORD *)(4LL * j + *(_QWORD *)(8LL * i + a1));\n }\n }\n ptr = calloc(v9 + 1, 4uLL);\n for ( k = 0; k < a2; ++k )\n {\n for ( m = 0; m < *(_DWORD *)(4LL * k + a3); ++m )\n ++ptr[*(int *)(4LL * m + *(_QWORD *)(8LL * k + a1))];\n }\n base = malloc(8LL * (v9 + 1));\n v14 = 0;\n for ( n = 0; n <= v9; ++n )\n {\n if ( (int)ptr[n] > 0 )\n {\n base[2 * v14] = n;\n base[2 * v14++ + 1] = ptr[n];\n }\n }\n qsort(base, v14, 8uLL, compar);\n v19 = malloc(4LL * a4);\n for ( ii = 0; ii < a4; ++ii )\n v19[ii] = base[2 * ii];\n *a5 = a4;\n free(ptr);\n free(base);\n return v19;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1241(long long a1, int a2, long long a3, int a4, uint32_t *a5) {\n int v9;\n int i;\n int j;\n int k;\n int m;\n int v14;\n int n;\n int ii;\n uint32_t *ptr;\n uint32_t *base;\n uint32_t *v19;\n v9 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = 0; j < *(uint32_t *)(4LL * i + a3); ++j) {\n if (v9 < *(uint32_t *)(4LL * j + *(uint64_t *)(8LL * i + a1)))\n v9 = *(uint32_t *)(4LL * j + *(uint64_t *)(8LL * i + a1));\n }\n }\n ptr = calloc(v9 + 1, 4uLL);\n for (k = 0; k < a2; ++k) {\n for (m = 0; m < *(uint32_t *)(4LL * k + a3); ++m)\n ++ptr[*(int *)(4LL * m + *(uint64_t *)(8LL * k + a1))];\n }\n base = malloc(8LL * (v9 + 1));\n v14 = 0;\n for (n = 0; n <= v9; ++n) {\n if ((int)ptr[n] > 0) {\n base[2 * v14] = n;\n base[2 * v14++ + 1] = ptr[n];\n }\n }\n qsort(base, v14, 8uLL, compar);\n v19 = malloc(4LL * a4);\n for (ii = 0; ii < a4; ++ii) v19[ii] = base[2 * ii];\n *a5 = a4;\n free(ptr);\n free(base);\n return v19;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, long long a3, int a4, uint32_t *a5) {\n int v9;\n int i;\n int j;\n int k;\n int m;\n int v14;\n int n;\n int ii;\n uint32_t *ptr;\n uint32_t *base;\n uint32_t *v19;\n v9 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = 0; j < *(uint32_t *)(4LL * i + a3); ++j) {\n if (v9 < *(uint32_t *)(4LL * j + *(uint64_t *)(8LL * i + a1)))\n v9 = *(uint32_t *)(4LL * j + *(uint64_t *)(8LL * i + a1));\n }\n }\n ptr = calloc(v9 + 1, 4uLL);\n for (k = 0; k < a2; ++k) {\n for (m = 0; m < *(uint32_t *)(4LL * k + a3); ++m)\n ++ptr[*(int *)(4LL * m + *(uint64_t *)(8LL * k + a1))];\n }\n base = malloc(8LL * (v9 + 1));\n v14 = 0;\n for (n = 0; n <= v9; ++n) {\n if ((int)ptr[n] > 0) {\n base[2 * v14] = n;\n base[2 * v14++ + 1] = ptr[n];\n }\n }\n qsort(base, v14, 8uLL, compare);\n v19 = malloc(4LL * a4);\n for (ii = 0; ii < a4; ++ii) v19[ii] = base[2 * ii];\n *a5 = a4;\n free(ptr);\n free(base);\n return v19;\n}" + }, + { + "index": 31, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int key;\n\n int count;\n\n} Element;\n\n\n\nint compare(const void* a, const void* b) {\n\n Element* ea = (Element*)a;\n\n Element* eb = (Element*)b;\n\n if (eb->count != ea->count)\n\n return eb->count - ea->count;\n\n return ea->key - eb->key;\n\n}\n\n\n\n", + "func": "int* func0(int** nums, int numsSize, int* numsColSizes, int k,\n int* returnSize) {\n int max_key = 0;\n for (int i = 0; i < numsSize; i++) {\n for (int j = 0; j < numsColSizes[i]; j++) {\n if (nums[i][j] > max_key) max_key = nums[i][j];\n }\n }\n int* freq = (int*)calloc(max_key + 1, sizeof(int));\n for (int i = 0; i < numsSize; i++) {\n for (int j = 0; j < numsColSizes[i]; j++) {\n freq[nums[i][j]] += 1;\n }\n }\n Element* elements = (Element*)malloc((max_key + 1) * sizeof(Element));\n int count = 0;\n for (int i = 0; i <= max_key; i++) {\n if (freq[i] > 0) {\n elements[count].key = i;\n elements[count].count = freq[i];\n count++;\n }\n }\n qsort(elements, count, sizeof(Element), compare);\n int* result = (int*)malloc(k * sizeof(int));\n for (int i = 0; i < k; i++) {\n result[i] = elements[i].key;\n }\n *returnSize = k;\n free(freq);\n free(elements);\n return result;\n}", + "test": "int main() {\n\n // First test case\n\n int row0[] = {1, 2, 6};\n\n int row1[] = {1, 3, 4, 5, 7, 8};\n\n int row2[] = {1, 3, 5, 6, 8, 9};\n\n int row3[] = {2, 5, 7, 11};\n\n int row4[] = {1, 4, 7, 8, 12};\n\n int* nums1[] = {row0, row1, row2, row3, row4};\n\n int numsColSizes1[] = {3, 6, 6, 4, 5};\n\n int returnSize1;\n\n int* res1 = func0(nums1, 5, numsColSizes1, 3, &returnSize1);\n\n int expected1[] = {1, 5, 7};\n\n for(int i = 0; i < 3; i++) {\n\n assert(res1[i] == expected1[i]);\n\n }\n\n free(res1);\n\n \n\n // Second test case\n\n int returnSize2;\n\n int* res2 = func0(nums1, 5, numsColSizes1, 1, &returnSize2);\n\n int expected2[] = {1};\n\n for(int i = 0; i < 1; i++) {\n\n assert(res2[i] == expected2[i]);\n\n }\n\n free(res2);\n\n \n\n // Third test case\n\n int returnSize3;\n\n int* res3 = func0(nums1, 5, numsColSizes1, 5, &returnSize3);\n\n int expected3[] = {1, 5, 7, 8, 2};\n\n for(int i = 0; i < 5; i++) {\n\n assert(res3[i] == expected3[i]);\n\n }\n\n free(res3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov %ecx,%r15d\nmov %r8,(%rsp)\ntest %esi,%esi\njle 1382 \nmov %rdi,%r13\nmov %rdx,%r12\nlea -0x1(%rsi),%r14d\nmov $0x0,%esi\nmov $0x0,%ebx\njmp 1263 \nmov 0x0(%r13,%rsi,8),%rax\nlea -0x1(%rdx),%edx\nlea 0x4(%rax,%rdx,4),%rcx\nmov (%rax),%edx\ncmp %edx,%ebx\ncmovl %edx,%ebx\nadd $0x4,%rax\ncmp %rcx,%rax\njne 1243 \nlea 0x1(%rsi),%rax\ncmp %r14,%rsi\nje 135e \nmov %rax,%rsi\nmov (%r12,%rsi,4),%edx\ntest %edx,%edx\njg 1236 \njmp 1253 \nmov 0x0(%r13,%rsi,8),%rax\nlea -0x1(%rdx),%edx\nlea 0x4(%rax,%rdx,4),%rcx\nmovslq (%rax),%rdx\naddl $0x1,0x0(%rbp,%rdx,4)\nadd $0x4,%rax\ncmp %rax,%rcx\njne 127a \nlea 0x1(%rsi),%rax\ncmp %r14,%rsi\nje 12a1 \nmov %rax,%rsi\nmov (%r12,%rsi,4),%edx\ntest %edx,%edx\njg 126d \njmp 128b \nmov 0x8(%rsp),%rdi\nshl $0x3,%rdi\ncallq 10f0 \nmov %rax,%r12\ntest %ebx,%ebx\njs 12e9 \nmov %ebx,%ebx\nmov $0x0,%eax\nmov $0x0,%ecx\njmp 12d0 \nlea 0x1(%rax),%rdx\ncmp %rax,%rbx\nje 12ee \nmov %rdx,%rax\nmov 0x0(%rbp,%rax,4),%edx\ntest %edx,%edx\njle 12c4 \nmovslq %ecx,%rsi\nlea (%r12,%rsi,8),%rsi\nmov %eax,(%rsi)\nmov %edx,0x4(%rsi)\nadd $0x1,%ecx\njmp 12c4 \nmov $0x0,%ecx\nmovslq %ecx,%rsi\nlea -0x10f(%rip),%rcx\nmov $0x8,%edx\nmov %r12,%rdi\ncallq 10b0 \nmovslq %r15d,%rdi\nshl $0x2,%rdi\ncallq 10f0 \nmov %rax,%rbx\ntest %r15d,%r15d\njle 1335 \nlea -0x1(%r15),%ecx\nmov $0x0,%eax\nmov (%r12,%rax,8),%edx\nmov %edx,(%rbx,%rax,4)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rdx,%rcx\njne 1322 \nmov (%rsp),%rax\nmov %r15d,(%rax)\nmov %rbp,%rdi\ncallq 10a0 \nmov %r12,%rdi\ncallq 10a0 \nmov %rbx,%rax\nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nlea 0x1(%rbx),%eax\ncltq\nmov %rax,0x8(%rsp)\nmov $0x4,%esi\nmov %rax,%rdi\ncallq 10e0 \nmov %rax,%rbp\nmov $0x0,%esi\njmpq 1297 \nmov $0x4,%esi\nmov $0x1,%edi\ncallq 10e0 \nmov %rax,%rbp\nmov $0x8,%edi\ncallq 10f0 \nmov %rax,%r12\nmov $0x0,%ebx\njmpq 12b6 \n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov r15d, ecx\nmov [rsp+48h+var_48], r8\ntest esi, esi\njle loc_1375\nmov r14, rdi\nmov r13, rdx\nmovsxd rsi, esi\nmov r12d, 0\nmov ebx, 0\njmp short loc_125E\nloc_1236:\nmov rax, [r14+r12*8]\nmovsxd rdx, edx\nlea rcx, [rax+rdx*4]\nloc_1241:\nmov edx, [rax]\ncmp ebx, edx\ncmovl ebx, edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_1241\nloc_1251:\nlea rax, [r12+1]\ncmp rax, rsi\njz short loc_1269\nmov r12, rax\nloc_125E:\nmov edx, [r13+r12*4+0]\ntest edx, edx\njg short loc_1236\njmp short loc_1251\nloc_1269:\nlea eax, [rbx+1]\ncdqe\nmov [rsp+48h+var_40], rax\nmov esi, 4; size\nmov rdi, rax; nmemb\ncall _calloc\nmov rbp, rax\nmov esi, 0\njmp short loc_12B2\nloc_128A:\nmov rax, [r14+rsi*8]\nmovsxd rdx, edx\nlea rcx, [rax+rdx*4]\nloc_1295:\nmovsxd rdx, dword ptr [rax]\nadd dword ptr [rbp+rdx*4+0], 1\nadd rax, 4\ncmp rcx, rax\njnz short loc_1295\nloc_12A6:\nlea rax, [rsi+1]\ncmp rsi, r12\njz short loc_12BD\nmov rsi, rax\nloc_12B2:\nmov edx, [r13+rsi*4+0]\ntest edx, edx\njg short loc_128A\njmp short loc_12A6\nloc_12BD:\nmov rdi, [rsp+48h+var_40]\nshl rdi, 3; size\ncall _malloc\nmov r12, rax\ntest ebx, ebx\njs short loc_1303\nloc_12D2:\nlea edi, [rbx+1]\nmov eax, 0\nmov ecx, 0\njmp short loc_12EA\nloc_12E1:\nadd rax, 1\ncmp rax, rdi\njz short loc_1308\nloc_12EA:\nmov edx, [rbp+rax*4+0]\ntest edx, edx\njle short loc_12E1\nmovsxd rsi, ecx\nlea rsi, [r12+rsi*8]\nmov [rsi], eax\nmov [rsi+4], edx\nadd ecx, 1\njmp short loc_12E1\nloc_1303:\nmov ecx, 0\nloc_1308:\nmovsxd rsi, ecx; nmemb\nlea rcx, compare; compar\nmov edx, 8; size\nmov rdi, r12; base\ncall _qsort\nmovsxd r13, r15d\nlea rdi, ds:0[r13*4]; size\ncall _malloc\nmov rbx, rax\ntest r15d, r15d\njle short loc_134C\nmov eax, 0\nloc_133C:\nmov edx, [r12+rax*8]\nmov [rbx+rax*4], edx\nadd rax, 1\ncmp r13, rax\njnz short loc_133C\nloc_134C:\nmov rax, [rsp+48h+var_48]\nmov [rax], r15d\nmov rdi, rbp; ptr\ncall _free\nmov rdi, r12; ptr\ncall _free\nmov rax, rbx\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1375:\nmov esi, 4; size\nmov edi, 1; nmemb\ncall _calloc\nmov rbp, rax\nmov edi, 8; size\ncall _malloc\nmov r12, rax\nmov ebx, 0\njmp loc_12D2", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, __int64 a3, int a4, int *a5)\n{\n __int64 v7; // r12\n int v8; // ebx\n int *v9; // rax\n int *v10; // rcx\n int v11; // edx\n _DWORD *v12; // rbp\n __int64 i; // rsi\n int *v14; // rax\n int *v15; // rcx\n int v16; // edx\n char *v17; // r12\n __int64 v18; // rax\n int v19; // ecx\n int v20; // edx\n char *v21; // rsi\n _DWORD *v22; // rbx\n __int64 v23; // rax\n\n if ( a2 <= 0 )\n {\n v12 = calloc(1uLL, 4uLL);\n v17 = (char *)malloc(8uLL);\n v8 = 0;\n }\n else\n {\n v7 = 0LL;\n v8 = 0;\n while ( 1 )\n {\n v11 = *(_DWORD *)(a3 + 4 * v7);\n if ( v11 > 0 )\n {\n v9 = *(int **)(a1 + 8 * v7);\n v10 = &v9[v11];\n do\n {\n if ( v8 < *v9 )\n v8 = *v9;\n ++v9;\n }\n while ( v9 != v10 );\n }\n if ( v7 + 1 == a2 )\n break;\n ++v7;\n }\n v12 = calloc(v8 + 1, 4uLL);\n for ( i = 0LL; ; ++i )\n {\n v16 = *(_DWORD *)(a3 + 4 * i);\n if ( v16 > 0 )\n {\n v14 = *(int **)(a1 + 8 * i);\n v15 = &v14[v16];\n do\n ++v12[*v14++];\n while ( v15 != v14 );\n }\n if ( i == v7 )\n break;\n }\n v17 = (char *)malloc(8LL * (v8 + 1));\n if ( v8 < 0 )\n {\n v19 = 0;\n goto LABEL_24;\n }\n }\n v18 = 0LL;\n v19 = 0;\n do\n {\n v20 = v12[v18];\n if ( v20 > 0 )\n {\n v21 = &v17[8 * v19];\n *(_DWORD *)v21 = v18;\n *((_DWORD *)v21 + 1) = v20;\n ++v19;\n }\n ++v18;\n }\n while ( v18 != v8 + 1 );\nLABEL_24:\n qsort(v17, v19, 8uLL, compare);\n v22 = malloc(4LL * a4);\n if ( a4 > 0 )\n {\n v23 = 0LL;\n do\n {\n v22[v23] = *(_DWORD *)&v17[8 * v23];\n ++v23;\n }\n while ( a4 != v23 );\n }\n *a5 = a4;\n free(v12);\n free(v17);\n return v22;\n}", + "ida_strip_asm": "sub_11FF:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov r15d, ecx\nmov [rsp+48h+var_48], r8\ntest esi, esi\njle loc_1375\nmov r14, rdi\nmov r13, rdx\nmovsxd rsi, esi\nmov r12d, 0\nmov ebx, 0\njmp short loc_125E\nloc_1236:\nmov rax, [r14+r12*8]\nmovsxd rdx, edx\nlea rcx, [rax+rdx*4]\nloc_1241:\nmov edx, [rax]\ncmp ebx, edx\ncmovl ebx, edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_1241\nloc_1251:\nlea rax, [r12+1]\ncmp rax, rsi\njz short loc_1269\nmov r12, rax\nloc_125E:\nmov edx, [r13+r12*4+0]\ntest edx, edx\njg short loc_1236\njmp short loc_1251\nloc_1269:\nlea eax, [rbx+1]\ncdqe\nmov [rsp+48h+var_40], rax\nmov esi, 4; size\nmov rdi, rax; nmemb\ncall _calloc\nmov rbp, rax\nmov esi, 0\njmp short loc_12B2\nloc_128A:\nmov rax, [r14+rsi*8]\nmovsxd rdx, edx\nlea rcx, [rax+rdx*4]\nloc_1295:\nmovsxd rdx, dword ptr [rax]\nadd dword ptr [rbp+rdx*4+0], 1\nadd rax, 4\ncmp rcx, rax\njnz short loc_1295\nloc_12A6:\nlea rax, [rsi+1]\ncmp rsi, r12\njz short loc_12BD\nmov rsi, rax\nloc_12B2:\nmov edx, [r13+rsi*4+0]\ntest edx, edx\njg short loc_128A\njmp short loc_12A6\nloc_12BD:\nmov rdi, [rsp+48h+var_40]\nshl rdi, 3; size\ncall _malloc\nmov r12, rax\ntest ebx, ebx\njs short loc_1303\nloc_12D2:\nlea edi, [rbx+1]\nmov eax, 0\nmov ecx, 0\njmp short loc_12EA\nloc_12E1:\nadd rax, 1\ncmp rax, rdi\njz short loc_1308\nloc_12EA:\nmov edx, [rbp+rax*4+0]\ntest edx, edx\njle short loc_12E1\nmovsxd rsi, ecx\nlea rsi, [r12+rsi*8]\nmov [rsi], eax\nmov [rsi+4], edx\nadd ecx, 1\njmp short loc_12E1\nloc_1303:\nmov ecx, 0\nloc_1308:\nmovsxd rsi, ecx; nmemb\nlea rcx, compar; compar\nmov edx, 8; size\nmov rdi, r12; base\ncall _qsort\nmovsxd r13, r15d\nlea rdi, ds:0[r13*4]; size\ncall _malloc\nmov rbx, rax\ntest r15d, r15d\njle short loc_134C\nmov eax, 0\nloc_133C:\nmov edx, [r12+rax*8]\nmov [rbx+rax*4], edx\nadd rax, 1\ncmp r13, rax\njnz short loc_133C\nloc_134C:\nmov rax, [rsp+48h+var_48]\nmov [rax], r15d\nmov rdi, rbp; ptr\ncall _free\nmov rdi, r12; ptr\ncall _free\nmov rax, rbx\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1375:\nmov esi, 4; size\nmov edi, 1; nmemb\ncall _calloc\nmov rbp, rax\nmov edi, 8; size\ncall _malloc\nmov r12, rax\nmov ebx, 0\njmp loc_12D2", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11FF(__int64 a1, int a2, __int64 a3, int a4, int *a5)\n{\n __int64 v7; // r12\n int v8; // ebx\n int *v9; // rax\n int *v10; // rcx\n int v11; // edx\n _DWORD *v12; // rbp\n __int64 i; // rsi\n int *v14; // rax\n int *v15; // rcx\n int v16; // edx\n char *v17; // r12\n __int64 v18; // rax\n int v19; // ecx\n int v20; // edx\n char *v21; // rsi\n _DWORD *v22; // rbx\n __int64 v23; // rax\n\n if ( a2 <= 0 )\n {\n v12 = calloc(1uLL, 4uLL);\n v17 = (char *)malloc(8uLL);\n v8 = 0;\n }\n else\n {\n v7 = 0LL;\n v8 = 0;\n while ( 1 )\n {\n v11 = *(_DWORD *)(a3 + 4 * v7);\n if ( v11 > 0 )\n {\n v9 = *(int **)(a1 + 8 * v7);\n v10 = &v9[v11];\n do\n {\n if ( v8 < *v9 )\n v8 = *v9;\n ++v9;\n }\n while ( v9 != v10 );\n }\n if ( v7 + 1 == a2 )\n break;\n ++v7;\n }\n v12 = calloc(v8 + 1, 4uLL);\n for ( i = 0LL; ; ++i )\n {\n v16 = *(_DWORD *)(a3 + 4 * i);\n if ( v16 > 0 )\n {\n v14 = *(int **)(a1 + 8 * i);\n v15 = &v14[v16];\n do\n ++v12[*v14++];\n while ( v15 != v14 );\n }\n if ( i == v7 )\n break;\n }\n v17 = (char *)malloc(8LL * (v8 + 1));\n if ( v8 < 0 )\n {\n v19 = 0;\n goto LABEL_24;\n }\n }\n v18 = 0LL;\n v19 = 0;\n do\n {\n v20 = v12[v18];\n if ( v20 > 0 )\n {\n v21 = &v17[8 * v19];\n *(_DWORD *)v21 = v18;\n *((_DWORD *)v21 + 1) = v20;\n ++v19;\n }\n ++v18;\n }\n while ( v18 != v8 + 1 );\nLABEL_24:\n qsort(v17, v19, 8uLL, compar);\n v22 = malloc(4LL * a4);\n if ( a4 > 0 )\n {\n v23 = 0LL;\n do\n {\n v22[v23] = *(_DWORD *)&v17[8 * v23];\n ++v23;\n }\n while ( a4 != v23 );\n }\n *a5 = a4;\n free(v12);\n free(v17);\n return v22;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11FF(long long a1, int a2, long long a3, int a4, int *a5) {\n long long v7;\n int v8;\n int *v9;\n int *v10;\n int v11;\n uint32_t *v12;\n long long i;\n int *v14;\n int *v15;\n int v16;\n char *v17;\n long long v18;\n int v19;\n int v20;\n char *v21;\n uint32_t *v22;\n long long v23;\n if (a2 <= 0) {\n v12 = calloc(1uLL, 4uLL);\n v17 = (char *)malloc(8uLL);\n v8 = 0;\n } else {\n v7 = 0LL;\n v8 = 0;\n while (1) {\n v11 = *(uint32_t *)(a3 + 4 * v7);\n if (v11 > 0) {\n v9 = *(int **)(a1 + 8 * v7);\n v10 = &v9[v11];\n do {\n if (v8 < *v9) v8 = *v9;\n ++v9;\n } while (v9 != v10);\n }\n if (v7 + 1 == a2) break;\n ++v7;\n }\n v12 = calloc(v8 + 1, 4uLL);\n for (i = 0LL;; ++i) {\n v16 = *(uint32_t *)(a3 + 4 * i);\n if (v16 > 0) {\n v14 = *(int **)(a1 + 8 * i);\n v15 = &v14[v16];\n do\n ++v12[*v14++];\n while (v15 != v14);\n }\n if (i == v7) break;\n }\n v17 = (char *)malloc(8LL * (v8 + 1));\n if (v8 < 0) {\n v19 = 0;\n goto LABEL_24;\n }\n }\n v18 = 0LL;\n v19 = 0;\n do {\n v20 = v12[v18];\n if (v20 > 0) {\n v21 = &v17[8 * v19];\n *(uint32_t *)v21 = v18;\n *((uint32_t *)v21 + 1) = v20;\n ++v19;\n }\n ++v18;\n } while (v18 != v8 + 1);\nLABEL_24:\n qsort(v17, v19, 8uLL, compar);\n v22 = malloc(4LL * a4);\n if (a4 > 0) {\n v23 = 0LL;\n do {\n v22[v23] = *(uint32_t *)&v17[8 * v23];\n ++v23;\n } while (a4 != v23);\n }\n *a5 = a4;\n free(v12);\n free(v17);\n return v22;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, long long a3, int a4, int *a5) {\n long long v7;\n int v8;\n int *v9;\n int *v10;\n int v11;\n uint32_t *v12;\n long long i;\n int *v14;\n int *v15;\n int v16;\n char *v17;\n long long v18;\n int v19;\n int v20;\n char *v21;\n uint32_t *v22;\n long long v23;\n if (a2 <= 0) {\n v12 = calloc(1uLL, 4uLL);\n v17 = (char *)malloc(8uLL);\n v8 = 0;\n } else {\n v7 = 0LL;\n v8 = 0;\n while (1) {\n v11 = *(uint32_t *)(a3 + 4 * v7);\n if (v11 > 0) {\n v9 = *(int **)(a1 + 8 * v7);\n v10 = &v9[v11];\n do {\n if (v8 < *v9) v8 = *v9;\n ++v9;\n } while (v9 != v10);\n }\n if (v7 + 1 == a2) break;\n ++v7;\n }\n v12 = calloc(v8 + 1, 4uLL);\n for (i = 0LL;; ++i) {\n v16 = *(uint32_t *)(a3 + 4 * i);\n if (v16 > 0) {\n v14 = *(int **)(a1 + 8 * i);\n v15 = &v14[v16];\n do\n ++v12[*v14++];\n while (v15 != v14);\n }\n if (i == v7) break;\n }\n v17 = (char *)malloc(8LL * (v8 + 1));\n if (v8 < 0) {\n v19 = 0;\n goto LABEL_24;\n }\n }\n v18 = 0LL;\n v19 = 0;\n do {\n v20 = v12[v18];\n if (v20 > 0) {\n v21 = &v17[8 * v19];\n *(uint32_t *)v21 = v18;\n *((uint32_t *)v21 + 1) = v20;\n ++v19;\n }\n ++v18;\n } while (v18 != v8 + 1);\nLABEL_24:\n qsort(v17, v19, 8uLL, compare);\n v22 = malloc(4LL * a4);\n if (a4 > 0) {\n v23 = 0LL;\n do {\n v22[v23] = *(uint32_t *)&v17[8 * v23];\n ++v23;\n } while (a4 != v23);\n }\n *a5 = a4;\n free(v12);\n free(v17);\n return v22;\n}" + }, + { + "index": 31, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int key;\n\n int count;\n\n} Element;\n\n\n\nint compare(const void* a, const void* b) {\n\n Element* ea = (Element*)a;\n\n Element* eb = (Element*)b;\n\n if (eb->count != ea->count)\n\n return eb->count - ea->count;\n\n return ea->key - eb->key;\n\n}\n\n\n\n", + "func": "int* func0(int** nums, int numsSize, int* numsColSizes, int k,\n int* returnSize) {\n int max_key = 0;\n for (int i = 0; i < numsSize; i++) {\n for (int j = 0; j < numsColSizes[i]; j++) {\n if (nums[i][j] > max_key) max_key = nums[i][j];\n }\n }\n int* freq = (int*)calloc(max_key + 1, sizeof(int));\n for (int i = 0; i < numsSize; i++) {\n for (int j = 0; j < numsColSizes[i]; j++) {\n freq[nums[i][j]] += 1;\n }\n }\n Element* elements = (Element*)malloc((max_key + 1) * sizeof(Element));\n int count = 0;\n for (int i = 0; i <= max_key; i++) {\n if (freq[i] > 0) {\n elements[count].key = i;\n elements[count].count = freq[i];\n count++;\n }\n }\n qsort(elements, count, sizeof(Element), compare);\n int* result = (int*)malloc(k * sizeof(int));\n for (int i = 0; i < k; i++) {\n result[i] = elements[i].key;\n }\n *returnSize = k;\n free(freq);\n free(elements);\n return result;\n}", + "test": "int main() {\n\n // First test case\n\n int row0[] = {1, 2, 6};\n\n int row1[] = {1, 3, 4, 5, 7, 8};\n\n int row2[] = {1, 3, 5, 6, 8, 9};\n\n int row3[] = {2, 5, 7, 11};\n\n int row4[] = {1, 4, 7, 8, 12};\n\n int* nums1[] = {row0, row1, row2, row3, row4};\n\n int numsColSizes1[] = {3, 6, 6, 4, 5};\n\n int returnSize1;\n\n int* res1 = func0(nums1, 5, numsColSizes1, 3, &returnSize1);\n\n int expected1[] = {1, 5, 7};\n\n for(int i = 0; i < 3; i++) {\n\n assert(res1[i] == expected1[i]);\n\n }\n\n free(res1);\n\n \n\n // Second test case\n\n int returnSize2;\n\n int* res2 = func0(nums1, 5, numsColSizes1, 1, &returnSize2);\n\n int expected2[] = {1};\n\n for(int i = 0; i < 1; i++) {\n\n assert(res2[i] == expected2[i]);\n\n }\n\n free(res2);\n\n \n\n // Third test case\n\n int returnSize3;\n\n int* res3 = func0(nums1, 5, numsColSizes1, 5, &returnSize3);\n\n int expected3[] = {1, 5, 7, 8, 2};\n\n for(int i = 0; i < 5; i++) {\n\n assert(res3[i] == expected3[i]);\n\n }\n\n free(res3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\nmov %ecx,%ebp\npush %rbx\nsub $0x18,%rsp\nmov %r8,(%rsp)\ntest %esi,%esi\njle 163d \nmov %rdi,%r13\nmov %rdx,%r14\nlea -0x1(%rsi),%r15d\nxor %edi,%edi\nxor %ebx,%ebx\nxchg %ax,%ax\nmov (%r14,%rdi,4),%eax\ntest %eax,%eax\njle 1515 \nmov 0x0(%r13,%rdi,8),%rdx\nlea -0x1(%rax),%ecx\nlea 0x4(%rdx),%rax\nlea (%rax,%rcx,4),%rsi\njmp 1504 \nnopw 0x0(%rax,%rax,1)\nadd $0x4,%rax\nmovslq (%rdx),%rcx\nmov %rax,%rdx\ncmp %ecx,%ebx\ncmovl %rcx,%rbx\ncmp %rax,%rsi\njne 1500 \nlea 0x1(%rdi),%rax\ncmp %r15,%rdi\nje 1528 \nmov %rax,%rdi\njmp 14e0 \nnopl 0x0(%rax,%rax,1)\nlea 0x1(%rbx),%edi\nmov $0x4,%esi\nmovslq %edi,%rdi\nmov %rdi,0x8(%rsp)\ncallq 10e0 \nmov 0x8(%rsp),%rdi\nxor %esi,%esi\nmov %rax,%r12\nnopw 0x0(%rax,%rax,1)\nmov (%r14,%rsi,4),%eax\ntest %eax,%eax\njle 1584 \nmov 0x0(%r13,%rsi,8),%rcx\nlea -0x1(%rax),%edx\nlea 0x4(%rcx),%rax\nlea (%rax,%rdx,4),%rdx\njmp 1574 \nnopw 0x0(%rax,%rax,1)\nadd $0x4,%rax\nmovslq (%rcx),%rcx\naddl $0x1,(%r12,%rcx,4)\nmov %rax,%rcx\ncmp %rax,%rdx\njne 1570 \nlea 0x1(%rsi),%rax\ncmp %r15,%rsi\nje 1598 \nmov %rax,%rsi\njmp 1550 \nnopw 0x0(%rax,%rax,1)\nshl $0x3,%rdi\ncallq 10f0 \nxor %ecx,%ecx\nxor %esi,%esi\nmov %rax,%r13\nxor %eax,%eax\njmp 15b3 \nnopl 0x0(%rax)\nmov %rdx,%rax\nmov (%r12,%rax,4),%edx\ntest %edx,%edx\njle 15cb \nlea 0x0(%r13,%rsi,8),%rsi\nadd $0x1,%ecx\nmov %eax,(%rsi)\nmov %edx,0x4(%rsi)\nmovslq %ecx,%rsi\nlea 0x1(%rax),%rdx\ncmp %rax,%rbx\njne 15b0 \nmov $0x8,%edx\nlea -0x150(%rip),%rcx\nmov %r13,%rdi\ncallq 10b0 \nmovslq %ebp,%rdi\nshl $0x2,%rdi\ncallq 10f0 \nxor %edx,%edx\nmov %rax,%r14\nlea -0x1(%rbp),%eax\ntest %ebp,%ebp\njle 1615 \nmov 0x0(%r13,%rdx,8),%ecx\nmov %ecx,(%r14,%rdx,4)\nmov %rdx,%rcx\nadd $0x1,%rdx\ncmp %rax,%rcx\njne 1600 \nmov (%rsp),%rax\nmov %r12,%rdi\nmov %ebp,(%rax)\ncallq 10a0 \nmov %r13,%rdi\ncallq 10a0 \nadd $0x18,%rsp\nmov %r14,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmov $0x1,%edi\nmov $0x4,%esi\nxor %ebx,%ebx\ncallq 10e0 \nmov $0x8,%edi\nmov %rax,%r12\njmpq 159c \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12, r8\npush rbp\nmov ebp, ecx\npush rbx\nsub rsp, 18h\ntest esi, esi\njle loc_1606\nmov r14, rdi\nmov r15, rdx\nmovsxd rdi, esi\nxor ecx, ecx\nxor ebx, ebx\nnop dword ptr [rax+00h]\nloc_1490:\nmovsxd rdx, dword ptr [r15+rcx*4]\ntest edx, edx\njle short loc_14DC\nmov rax, [r14+rcx*8]\nlea rsi, [rax+rdx*4]\nand edx, 1\njz short loc_14C0\nmovsxd rdx, dword ptr [rax]\ncmp ebx, edx\ncmovl rbx, rdx\nadd rax, 4\ncmp rsi, rax\njz short loc_14DC\nnop word ptr [rax+rax+00000000h]\nloc_14C0:\nmovsxd rdx, dword ptr [rax]\ncmp ebx, edx\ncmovl rbx, rdx\nmovsxd rdx, dword ptr [rax+4]\ncmp ebx, edx\ncmovl rbx, rdx\nadd rax, 8\ncmp rsi, rax\njnz short loc_14C0\nloc_14DC:\nlea rax, [rcx+1]\ncmp rdi, rax\njz short loc_14F0\nmov rcx, rax\njmp short loc_1490\nloc_14F0:\nlea r8d, [rbx+1]\nmov esi, 4; size\nmov [rsp+48h+var_40], rcx\nmovsxd r8, r8d\nmov rdi, r8; nmemb\nmov [rsp+48h+var_48], r8\ncall _calloc\nmov r8, [rsp+48h+var_48]\nmov rcx, [rsp+48h+var_40]\nxor edi, edi\nmov r13, rax\nnop dword ptr [rax+rax+00h]\nloc_1520:\nmovsxd rdx, dword ptr [r15+rdi*4]\ntest edx, edx\njle short loc_1542\nmov rax, [r14+rdi*8]\nlea rsi, [rax+rdx*4]\nloc_1530:\nmovsxd rdx, dword ptr [rax]\nadd rax, 4\nadd dword ptr [r13+rdx*4+0], 1\ncmp rax, rsi\njnz short loc_1530\nloc_1542:\nlea rax, [rdi+1]\ncmp rcx, rdi\njz short loc_1550\nmov rdi, rax\njmp short loc_1520\nloc_1550:\nlea rdi, ds:0[r8*8]; size\ncall _malloc\nmov r14, rax\ntest ebx, ebx\njs loc_162C\nloc_1568:\nxor eax, eax\nxor ecx, ecx\njmp short loc_1573\nloc_1570:\nmov rax, rdx\nloc_1573:\nmov edx, [r13+rax*4+0]\ntest edx, edx\njle short loc_1594\nmovd xmm0, eax\nmovd xmm1, edx\nmovsxd rsi, ecx\nadd ecx, 1\npunpckldq xmm0, xmm1\nmovq qword ptr [r14+rsi*8], xmm0\nloc_1594:\nlea rdx, [rax+1]\ncmp rax, rbx\njnz short loc_1570\nmovsxd rsi, ecx; nmemb\nloc_15A0:\nmov edx, 8; size\nlea rcx, compare; compar\nmov rdi, r14; base\nmovsxd r15, ebp\ncall _qsort\nlea rdi, ds:0[r15*4]; size\ncall _malloc\nxor edx, edx\nmov rbx, rax\ntest ebp, ebp\njle short loc_15E0\nnop dword ptr [rax]\nloc_15D0:\nmov ecx, [r14+rdx*8]\nmov [rbx+rdx*4], ecx\nadd rdx, 1\ncmp r15, rdx\njnz short loc_15D0\nloc_15E0:\nmov [r12], ebp\nmov rdi, r13; ptr\ncall _free\nmov rdi, r14; ptr\ncall _free\nadd rsp, 18h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1606:\nmov esi, 4; size\nmov edi, 1; nmemb\nxor ebx, ebx\ncall _calloc\nmov edi, 8; size\nmov r13, rax\ncall _malloc\nmov r14, rax\njmp loc_1568\nloc_162C:\nxor esi, esi\njmp loc_15A0", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, __int64 a3, int a4, int *a5)\n{\n __int64 v9; // rdi\n __int64 v10; // rcx\n __int64 v11; // rbx\n __int64 v12; // rdx\n int *v13; // rax\n int *v14; // rsi\n __int64 v15; // rdi\n _DWORD *v16; // r13\n __int64 v17; // rdx\n int *v18; // rax\n int *v19; // rsi\n __int64 v20; // rdx\n _QWORD *v21; // r14\n __int64 v22; // rax\n int v23; // ecx\n signed int v24; // edx\n __int64 v25; // rsi\n size_t v26; // rsi\n _DWORD *v27; // rax\n __int64 v28; // rdx\n _DWORD *v29; // rbx\n __int64 v31; // [rsp+8h] [rbp-40h]\n\n if ( a2 <= 0 )\n {\n v11 = 0LL;\n v16 = calloc(1uLL, 4uLL);\n v21 = malloc(8uLL);\n }\n else\n {\n v9 = a2;\n v10 = 0LL;\n v11 = 0LL;\n while ( 1 )\n {\n v12 = *(int *)(a3 + 4 * v10);\n if ( (int)v12 > 0 )\n {\n v13 = *(int **)(a1 + 8 * v10);\n v14 = &v13[v12];\n if ( (v12 & 1) == 0 )\n goto LABEL_35;\n if ( (int)v11 < *v13 )\n v11 = *v13;\n if ( v14 != ++v13 )\n {\nLABEL_35:\n do\n {\n if ( (int)v11 < *v13 )\n v11 = *v13;\n if ( (int)v11 < v13[1] )\n v11 = v13[1];\n v13 += 2;\n }\n while ( v14 != v13 );\n }\n }\n if ( v9 == v10 + 1 )\n break;\n ++v10;\n }\n v31 = v10;\n v15 = 0LL;\n v16 = calloc((int)v11 + 1, 4uLL);\n while ( 1 )\n {\n v17 = *(int *)(a3 + 4 * v15);\n if ( (int)v17 > 0 )\n {\n v18 = *(int **)(a1 + 8 * v15);\n v19 = &v18[v17];\n do\n {\n v20 = *v18++;\n ++v16[v20];\n }\n while ( v18 != v19 );\n }\n if ( v31 == v15 )\n break;\n ++v15;\n }\n v21 = malloc(8LL * ((int)v11 + 1));\n if ( (int)v11 < 0 )\n {\n v26 = 0LL;\n goto LABEL_28;\n }\n }\n v22 = 0LL;\n v23 = 0;\n while ( 1 )\n {\n v24 = v16[v22];\n if ( v24 > 0 )\n {\n v25 = v23++;\n v21[v25] = _mm_unpacklo_epi32(_mm_cvtsi32_si128(v22), _mm_cvtsi32_si128(v24)).m128i_u64[0];\n }\n if ( v22 == v11 )\n break;\n ++v22;\n }\n v26 = v23;\nLABEL_28:\n qsort(v21, v26, 8uLL, compare);\n v27 = malloc(4LL * a4);\n v28 = 0LL;\n v29 = v27;\n if ( a4 > 0 )\n {\n do\n {\n v27[v28] = v21[v28];\n ++v28;\n }\n while ( a4 != v28 );\n }\n *a5 = a4;\n free(v16);\n free(v21);\n return v29;\n}", + "ida_strip_asm": "sub_1460:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12, r8\npush rbp\nmov ebp, ecx\npush rbx\nsub rsp, 18h\ntest esi, esi\njle loc_1606\nmov r14, rdi\nmov r15, rdx\nmovsxd rdi, esi\nxor ecx, ecx\nxor ebx, ebx\nnop dword ptr [rax+00h]\nloc_1490:\nmovsxd rdx, dword ptr [r15+rcx*4]\ntest edx, edx\njle short loc_14DC\nmov rax, [r14+rcx*8]\nlea rsi, [rax+rdx*4]\nand edx, 1\njz short loc_14C0\nmovsxd rdx, dword ptr [rax]\ncmp ebx, edx\ncmovl rbx, rdx\nadd rax, 4\ncmp rsi, rax\njz short loc_14DC\nnop word ptr [rax+rax+00000000h]\nloc_14C0:\nmovsxd rdx, dword ptr [rax]\ncmp ebx, edx\ncmovl rbx, rdx\nmovsxd rdx, dword ptr [rax+4]\ncmp ebx, edx\ncmovl rbx, rdx\nadd rax, 8\ncmp rsi, rax\njnz short loc_14C0\nloc_14DC:\nlea rax, [rcx+1]\ncmp rdi, rax\njz short loc_14F0\nmov rcx, rax\njmp short loc_1490\nloc_14F0:\nlea r8d, [rbx+1]\nmov esi, 4; size\nmov [rsp+48h+var_40], rcx\nmovsxd r8, r8d\nmov rdi, r8; nmemb\nmov [rsp+48h+var_48], r8\ncall _calloc\nmov r8, [rsp+48h+var_48]\nmov rcx, [rsp+48h+var_40]\nxor edi, edi\nmov r13, rax\nnop dword ptr [rax+rax+00h]\nloc_1520:\nmovsxd rdx, dword ptr [r15+rdi*4]\ntest edx, edx\njle short loc_1542\nmov rax, [r14+rdi*8]\nlea rsi, [rax+rdx*4]\nloc_1530:\nmovsxd rdx, dword ptr [rax]\nadd rax, 4\nadd dword ptr [r13+rdx*4+0], 1\ncmp rax, rsi\njnz short loc_1530\nloc_1542:\nlea rax, [rdi+1]\ncmp rcx, rdi\njz short loc_1550\nmov rdi, rax\njmp short loc_1520\nloc_1550:\nlea rdi, ds:0[r8*8]; size\ncall _malloc\nmov r14, rax\ntest ebx, ebx\njs loc_162C\nloc_1568:\nxor eax, eax\nxor ecx, ecx\njmp short loc_1573\nloc_1570:\nmov rax, rdx\nloc_1573:\nmov edx, [r13+rax*4+0]\ntest edx, edx\njle short loc_1594\nmovd xmm0, eax\nmovd xmm1, edx\nmovsxd rsi, ecx\nadd ecx, 1\npunpckldq xmm0, xmm1\nmovq qword ptr [r14+rsi*8], xmm0\nloc_1594:\nlea rdx, [rax+1]\ncmp rax, rbx\njnz short loc_1570\nmovsxd rsi, ecx; nmemb\nloc_15A0:\nmov edx, 8; size\nlea rcx, compar; compar\nmov rdi, r14; base\nmovsxd r15, ebp\ncall _qsort\nlea rdi, ds:0[r15*4]; size\ncall _malloc\nxor edx, edx\nmov rbx, rax\ntest ebp, ebp\njle short loc_15E0\nnop dword ptr [rax]\nloc_15D0:\nmov ecx, [r14+rdx*8]\nmov [rbx+rdx*4], ecx\nadd rdx, 1\ncmp r15, rdx\njnz short loc_15D0\nloc_15E0:\nmov [r12], ebp\nmov rdi, r13; ptr\ncall _free\nmov rdi, r14; ptr\ncall _free\nadd rsp, 18h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1606:\nmov esi, 4; size\nmov edi, 1; nmemb\nxor ebx, ebx\ncall _calloc\nmov edi, 8; size\nmov r13, rax\ncall _malloc\nmov r14, rax\njmp loc_1568\nloc_162C:\nxor esi, esi\njmp loc_15A0", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1460(__int64 a1, int a2, __int64 a3, int a4, int *a5)\n{\n __int64 v9; // rdi\n __int64 v10; // rcx\n __int64 v11; // rbx\n __int64 v12; // rdx\n int *v13; // rax\n int *v14; // rsi\n __int64 v15; // rdi\n _DWORD *v16; // r13\n __int64 v17; // rdx\n int *v18; // rax\n int *v19; // rsi\n __int64 v20; // rdx\n _QWORD *v21; // r14\n __int64 v22; // rax\n int v23; // ecx\n signed int v24; // edx\n __int64 v25; // rsi\n size_t v26; // rsi\n _DWORD *v27; // rax\n __int64 v28; // rdx\n _DWORD *v29; // rbx\n __int64 v31; // [rsp+8h] [rbp-40h]\n\n if ( a2 <= 0 )\n {\n v11 = 0LL;\n v16 = calloc(1uLL, 4uLL);\n v21 = malloc(8uLL);\n }\n else\n {\n v9 = a2;\n v10 = 0LL;\n v11 = 0LL;\n while ( 1 )\n {\n v12 = *(int *)(a3 + 4 * v10);\n if ( (int)v12 > 0 )\n {\n v13 = *(int **)(a1 + 8 * v10);\n v14 = &v13[v12];\n if ( (v12 & 1) == 0 )\n goto LABEL_35;\n if ( (int)v11 < *v13 )\n v11 = *v13;\n if ( v14 != ++v13 )\n {\nLABEL_35:\n do\n {\n if ( (int)v11 < *v13 )\n v11 = *v13;\n if ( (int)v11 < v13[1] )\n v11 = v13[1];\n v13 += 2;\n }\n while ( v14 != v13 );\n }\n }\n if ( v9 == v10 + 1 )\n break;\n ++v10;\n }\n v31 = v10;\n v15 = 0LL;\n v16 = calloc((int)v11 + 1, 4uLL);\n while ( 1 )\n {\n v17 = *(int *)(a3 + 4 * v15);\n if ( (int)v17 > 0 )\n {\n v18 = *(int **)(a1 + 8 * v15);\n v19 = &v18[v17];\n do\n {\n v20 = *v18++;\n ++v16[v20];\n }\n while ( v18 != v19 );\n }\n if ( v31 == v15 )\n break;\n ++v15;\n }\n v21 = malloc(8LL * ((int)v11 + 1));\n if ( (int)v11 < 0 )\n {\n v26 = 0LL;\n goto LABEL_28;\n }\n }\n v22 = 0LL;\n v23 = 0;\n while ( 1 )\n {\n v24 = v16[v22];\n if ( v24 > 0 )\n {\n v25 = v23++;\n v21[v25] = _mm_unpacklo_epi32(_mm_cvtsi32_si128(v22), _mm_cvtsi32_si128(v24)).m128i_u64[0];\n }\n if ( v22 == v11 )\n break;\n ++v22;\n }\n v26 = v23;\nLABEL_28:\n qsort(v21, v26, 8uLL, compar);\n v27 = malloc(4LL * a4);\n v28 = 0LL;\n v29 = v27;\n if ( a4 > 0 )\n {\n do\n {\n v27[v28] = v21[v28];\n ++v28;\n }\n while ( a4 != v28 );\n }\n *a5 = a4;\n free(v16);\n free(v21);\n return v29;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1460(long long a1, int a2, long long a3, int a4, int *a5) {\n long long v9;\n long long v10;\n long long v11;\n long long v12;\n int *v13;\n int *v14;\n long long v15;\n uint32_t *v16;\n long long v17;\n int *v18;\n int *v19;\n long long v20;\n uint64_t *v21;\n long long v22;\n int v23;\n signed int v24;\n long long v25;\n unsigned int v26;\n uint32_t *v27;\n long long v28;\n uint32_t *v29;\n long long v31;\n if (a2 <= 0) {\n v11 = 0LL;\n v16 = calloc(1uLL, 4uLL);\n v21 = malloc(8uLL);\n } else {\n v9 = a2;\n v10 = 0LL;\n v11 = 0LL;\n while (1) {\n v12 = *(int *)(a3 + 4 * v10);\n if ((int)v12 > 0) {\n v13 = *(int **)(a1 + 8 * v10);\n v14 = &v13[v12];\n if ((v12 & 1) == 0) goto LABEL_35;\n if ((int)v11 < *v13) v11 = *v13;\n if (v14 != ++v13) {\n LABEL_35:\n do {\n if ((int)v11 < *v13) v11 = *v13;\n if ((int)v11 < v13[1]) v11 = v13[1];\n v13 += 2;\n } while (v14 != v13);\n }\n }\n if (v9 == v10 + 1) break;\n ++v10;\n }\n v31 = v10;\n v15 = 0LL;\n v16 = calloc((int)v11 + 1, 4uLL);\n while (1) {\n v17 = *(int *)(a3 + 4 * v15);\n if ((int)v17 > 0) {\n v18 = *(int **)(a1 + 8 * v15);\n v19 = &v18[v17];\n do {\n v20 = *v18++;\n ++v16[v20];\n } while (v18 != v19);\n }\n if (v31 == v15) break;\n ++v15;\n }\n v21 = malloc(8LL * ((int)v11 + 1));\n if ((int)v11 < 0) {\n v26 = 0LL;\n goto LABEL_28;\n }\n }\n v22 = 0LL;\n v23 = 0;\n while (1) {\n v24 = v16[v22];\n if (v24 > 0) {\n v25 = v23++;\n v21[v25] =\n _mm_unpacklo_epi32(_mm_cvtsi32_si128(v22), _mm_cvtsi32_si128(v24))\n .m128i_u64[0];\n }\n if (v22 == v11) break;\n ++v22;\n }\n v26 = v23;\nLABEL_28:\n qsort(v21, v26, 8uLL, compar);\n v27 = malloc(4LL * a4);\n v28 = 0LL;\n v29 = v27;\n if (a4 > 0) {\n do {\n v27[v28] = v21[v28];\n ++v28;\n } while (a4 != v28);\n }\n *a5 = a4;\n free(v16);\n free(v21);\n return v29;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, long long a3, int a4, int *a5) {\n long long v9;\n long long v10;\n long long v11;\n long long v12;\n int *v13;\n int *v14;\n long long v15;\n uint32_t *v16;\n long long v17;\n int *v18;\n int *v19;\n long long v20;\n uint64_t *v21;\n long long v22;\n int v23;\n signed int v24;\n long long v25;\n unsigned int v26;\n uint32_t *v27;\n long long v28;\n uint32_t *v29;\n long long v31;\n if (a2 <= 0) {\n v11 = 0LL;\n v16 = calloc(1uLL, 4uLL);\n v21 = malloc(8uLL);\n } else {\n v9 = a2;\n v10 = 0LL;\n v11 = 0LL;\n while (1) {\n v12 = *(int *)(a3 + 4 * v10);\n if ((int)v12 > 0) {\n v13 = *(int **)(a1 + 8 * v10);\n v14 = &v13[v12];\n if ((v12 & 1) == 0) goto LABEL_35;\n if ((int)v11 < *v13) v11 = *v13;\n if (v14 != ++v13) {\n LABEL_35:\n do {\n if ((int)v11 < *v13) v11 = *v13;\n if ((int)v11 < v13[1]) v11 = v13[1];\n v13 += 2;\n } while (v14 != v13);\n }\n }\n if (v9 == v10 + 1) break;\n ++v10;\n }\n v31 = v10;\n v15 = 0LL;\n v16 = calloc((int)v11 + 1, 4uLL);\n while (1) {\n v17 = *(int *)(a3 + 4 * v15);\n if ((int)v17 > 0) {\n v18 = *(int **)(a1 + 8 * v15);\n v19 = &v18[v17];\n do {\n v20 = *v18++;\n ++v16[v20];\n } while (v18 != v19);\n }\n if (v31 == v15) break;\n ++v15;\n }\n v21 = malloc(8LL * ((int)v11 + 1));\n if ((int)v11 < 0) {\n v26 = 0LL;\n goto LABEL_28;\n }\n }\n v22 = 0LL;\n v23 = 0;\n while (1) {\n v24 = v16[v22];\n if (v24 > 0) {\n v25 = v23++;\n v21[v25] =\n _mm_unpacklo_epi32(_mm_cvtsi32_si128(v22), _mm_cvtsi32_si128(v24))\n .m128i_u64[0];\n }\n if (v22 == v11) break;\n ++v22;\n }\n v26 = v23;\nLABEL_28:\n qsort(v21, v26, 8uLL, compare);\n v27 = malloc(4LL * a4);\n v28 = 0LL;\n v29 = v27;\n if (a4 > 0) {\n do {\n v27[v28] = v21[v28];\n ++v28;\n } while (a4 != v28);\n }\n *a5 = a4;\n free(v16);\n free(v21);\n return v29;\n}" + }, + { + "index": 31, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int key;\n\n int count;\n\n} Element;\n\n\n\nint compare(const void* a, const void* b) {\n\n Element* ea = (Element*)a;\n\n Element* eb = (Element*)b;\n\n if (eb->count != ea->count)\n\n return eb->count - ea->count;\n\n return ea->key - eb->key;\n\n}\n\n\n\n", + "func": "int* func0(int** nums, int numsSize, int* numsColSizes, int k,\n int* returnSize) {\n int max_key = 0;\n for (int i = 0; i < numsSize; i++) {\n for (int j = 0; j < numsColSizes[i]; j++) {\n if (nums[i][j] > max_key) max_key = nums[i][j];\n }\n }\n int* freq = (int*)calloc(max_key + 1, sizeof(int));\n for (int i = 0; i < numsSize; i++) {\n for (int j = 0; j < numsColSizes[i]; j++) {\n freq[nums[i][j]] += 1;\n }\n }\n Element* elements = (Element*)malloc((max_key + 1) * sizeof(Element));\n int count = 0;\n for (int i = 0; i <= max_key; i++) {\n if (freq[i] > 0) {\n elements[count].key = i;\n elements[count].count = freq[i];\n count++;\n }\n }\n qsort(elements, count, sizeof(Element), compare);\n int* result = (int*)malloc(k * sizeof(int));\n for (int i = 0; i < k; i++) {\n result[i] = elements[i].key;\n }\n *returnSize = k;\n free(freq);\n free(elements);\n return result;\n}", + "test": "int main() {\n\n // First test case\n\n int row0[] = {1, 2, 6};\n\n int row1[] = {1, 3, 4, 5, 7, 8};\n\n int row2[] = {1, 3, 5, 6, 8, 9};\n\n int row3[] = {2, 5, 7, 11};\n\n int row4[] = {1, 4, 7, 8, 12};\n\n int* nums1[] = {row0, row1, row2, row3, row4};\n\n int numsColSizes1[] = {3, 6, 6, 4, 5};\n\n int returnSize1;\n\n int* res1 = func0(nums1, 5, numsColSizes1, 3, &returnSize1);\n\n int expected1[] = {1, 5, 7};\n\n for(int i = 0; i < 3; i++) {\n\n assert(res1[i] == expected1[i]);\n\n }\n\n free(res1);\n\n \n\n // Second test case\n\n int returnSize2;\n\n int* res2 = func0(nums1, 5, numsColSizes1, 1, &returnSize2);\n\n int expected2[] = {1};\n\n for(int i = 0; i < 1; i++) {\n\n assert(res2[i] == expected2[i]);\n\n }\n\n free(res2);\n\n \n\n // Third test case\n\n int returnSize3;\n\n int* res3 = func0(nums1, 5, numsColSizes1, 5, &returnSize3);\n\n int expected3[] = {1, 5, 7, 8, 2};\n\n for(int i = 0; i < 5; i++) {\n\n assert(res3[i] == expected3[i]);\n\n }\n\n free(res3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\nmov %r8,%rbp\npush %rbx\nmov %ecx,%ebx\nsub $0x18,%rsp\ntest %esi,%esi\njle 1726 \nlea -0x1(%rsi),%r8d\nmov %rdi,%r14\nmov %rdx,%r15\nxor %esi,%esi\nxor %r12d,%r12d\nxchg %ax,%ax\nmov (%r15,%rsi,4),%ecx\ntest %ecx,%ecx\njle 1581 \nlea -0x1(%rcx),%eax\nmov (%r14,%rsi,8),%rdi\ncmp $0x2,%eax\njbe 171f \nmov %ecx,%edx\nmovd %r12d,%xmm3\nmov %rdi,%rax\nshr $0x2,%edx\npshufd $0x0,%xmm3,%xmm2\nshl $0x4,%rdx\nadd %rdi,%rdx\nnopl (%rax)\nmovdqu (%rax),%xmm0\nadd $0x10,%rax\nmovdqa %xmm0,%xmm1\npcmpgtd %xmm2,%xmm1\npand %xmm1,%xmm0\npandn %xmm2,%xmm1\nmovdqa %xmm1,%xmm2\npor %xmm0,%xmm2\ncmp %rdx,%rax\njne 14d8 \nmovdqa %xmm2,%xmm0\nmov %ecx,%eax\npsrldq $0x8,%xmm0\nand $0xfffffffc,%eax\nmovdqa %xmm0,%xmm1\npcmpgtd %xmm2,%xmm1\npand %xmm1,%xmm0\npandn %xmm2,%xmm1\npor %xmm1,%xmm0\nmovdqa %xmm0,%xmm2\npsrldq $0x4,%xmm2\nmovdqa %xmm2,%xmm1\npcmpgtd %xmm0,%xmm1\npand %xmm1,%xmm2\npandn %xmm0,%xmm1\npor %xmm2,%xmm1\nmovd %xmm1,%r12d\ntest $0x3,%cl\nje 1581 \nmovslq %eax,%rdx\nlea 0x0(,%rdx,4),%r9\nmov (%rdi,%rdx,4),%edx\ncmp %edx,%r12d\ncmovl %edx,%r12d\nlea 0x1(%rax),%edx\ncmp %edx,%ecx\njle 1581 \nmov 0x4(%rdi,%r9,1),%edx\ncmp %edx,%r12d\ncmovl %edx,%r12d\nadd $0x2,%eax\ncmp %eax,%ecx\njle 1581 \nmov 0x8(%rdi,%r9,1),%eax\ncmp %eax,%r12d\ncmovl %eax,%r12d\nlea 0x1(%rsi),%rax\ncmp %r8,%rsi\nje 1598 \nmov %rax,%rsi\njmpq 14a0 \nnopw 0x0(%rax,%rax,1)\nlea 0x1(%r12),%edi\nmov $0x4,%esi\nmov %r8,0x8(%rsp)\nmovslq %edi,%rdi\nmov %rdi,(%rsp)\ncallq 10e0 \nmov (%rsp),%rdi\nmov 0x8(%rsp),%r8\nxor %esi,%esi\nmov %rax,%r13\nnopl 0x0(%rax)\nmov (%r15,%rsi,4),%eax\ntest %eax,%eax\njle 15fd \nmov (%r14,%rsi,8),%rcx\nlea -0x1(%rax),%edx\nlea 0x4(%rcx),%rax\nlea (%rax,%rdx,4),%rdx\njmp 15ec \nnopl 0x0(%rax)\nadd $0x4,%rax\nmovslq (%rcx),%rcx\naddl $0x1,0x0(%r13,%rcx,4)\nmov %rax,%rcx\ncmp %rdx,%rax\njne 15e8 \nlea 0x1(%rsi),%rax\ncmp %r8,%rsi\nje 1610 \nmov %rax,%rsi\njmp 15c8 \nnopl 0x0(%rax,%rax,1)\nshl $0x3,%rdi\ncallq 10f0 \nmovslq %r12d,%r12\nxor %ecx,%ecx\nxor %esi,%esi\nmov %rax,%r14\nxor %eax,%eax\njmp 1633 \nnopw 0x0(%rax,%rax,1)\nmov %rdx,%rax\nmov 0x0(%r13,%rax,4),%edx\ntest %edx,%edx\njle 164b \nlea (%r14,%rsi,8),%rsi\nadd $0x1,%ecx\nmov %eax,(%rsi)\nmov %edx,0x4(%rsi)\nmovslq %ecx,%rsi\nlea 0x1(%rax),%rdx\ncmp %rax,%r12\njne 1630 \nlea -0x20b(%rip),%rcx\nmov $0x8,%edx\nmov %r14,%rdi\ncallq 10b0 \nmovslq %ebx,%rdi\nshl $0x2,%rdi\ncallq 10f0 \nmov %rax,%r12\ntest %ebx,%ebx\njle 16fa \nlea -0x1(%rbx),%eax\ncmp $0x3,%eax\njbe 1745 \nmov %eax,%ecx\nxor %edx,%edx\nshr $0x2,%ecx\nshl $0x4,%rcx\nnopw 0x0(%rax,%rax,1)\nmovdqu (%r14,%rdx,2),%xmm0\nmovdqu 0x10(%r14,%rdx,2),%xmm4\nshufps $0x88,%xmm4,%xmm0\nmovups %xmm0,(%r12,%rdx,1)\nadd $0x10,%rdx\ncmp %rcx,%rdx\njne 1698 \nand $0xfffffffc,%eax\nmovslq %eax,%rdx\nmov (%r14,%rdx,8),%ecx\nmov %ecx,(%r12,%rdx,4)\nlea 0x1(%rax),%edx\ncmp %edx,%ebx\njle 16fa \nmovslq %edx,%rdx\nmov (%r14,%rdx,8),%ecx\nmov %ecx,(%r12,%rdx,4)\nlea 0x2(%rax),%edx\ncmp %edx,%ebx\njle 16fa \nmovslq %edx,%rdx\nadd $0x3,%eax\nmov (%r14,%rdx,8),%ecx\nmov %ecx,(%r12,%rdx,4)\ncmp %eax,%ebx\njle 16fa \ncltq\nmov (%r14,%rax,8),%edx\nmov %edx,(%r12,%rax,4)\nmov %ebx,0x0(%rbp)\nmov %r13,%rdi\ncallq 10a0 \nmov %r14,%rdi\ncallq 10a0 \nadd $0x18,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nxor %eax,%eax\njmpq 1546 \nmov $0x1,%edi\nmov $0x4,%esi\nxor %r12d,%r12d\ncallq 10e0 \nmov $0x8,%edi\nmov %rax,%r13\njmpq 1614 \nxor %eax,%eax\njmpq 16ba \nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12, r8\npush rbp\nmov ebp, ecx\npush rbx\nsub rsp, 18h\ntest esi, esi\njle loc_16FA\nmov r14, rdi\nmov r15, rdx\nmovsxd r8, esi\nxor ecx, ecx\nxor ebx, ebx\nnop dword ptr [rax+00h]\nloc_1470:\nmov esi, [r15+rcx*4]\ntest esi, esi\njle loc_154B\nlea eax, [rsi-1]\nmov rdi, [r14+rcx*8]\ncmp eax, 2\njbe loc_16F3\nmov edx, esi\nmovd xmm3, ebx\nmov rax, rdi\nshr edx, 2\npshufd xmm2, xmm3, 0\nshl rdx, 4\nadd rdx, rdi\nnop dword ptr [rax+00h]\nloc_14A8:\nmovdqu xmm0, xmmword ptr [rax]\nadd rax, 10h\nmovdqa xmm1, xmm0\npcmpgtd xmm1, xmm2\npand xmm0, xmm1\npandn xmm1, xmm2\nmovdqa xmm2, xmm1\npor xmm2, xmm0\ncmp rdx, rax\njnz short loc_14A8\nmovdqa xmm1, xmm2\npsrldq xmm1, 8\nmovdqa xmm0, xmm1\npcmpgtd xmm0, xmm2\npand xmm1, xmm0\npandn xmm0, xmm2\npor xmm0, xmm1\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\nmovdqa xmm1, xmm2\npcmpgtd xmm1, xmm0\npand xmm2, xmm1\npandn xmm1, xmm0\npor xmm1, xmm2\nmovd ebx, xmm1\ntest sil, 3\njz short loc_154B\nmov eax, esi\nand eax, 0FFFFFFFCh\nloc_1516:\nmovsxd rdx, eax\nlea r9, ds:0[rdx*4]\nmov edx, [rdi+rdx*4]\ncmp ebx, edx\ncmovl ebx, edx\nlea edx, [rax+1]\ncmp esi, edx\njle short loc_154B\nmov edx, [rdi+r9+4]\ncmp ebx, edx\ncmovl ebx, edx\nadd eax, 2\ncmp esi, eax\njle short loc_154B\nmov eax, [rdi+r9+8]\ncmp ebx, eax\ncmovl ebx, eax\nloc_154B:\nlea rax, [rcx+1]\ncmp r8, rax\njz short loc_1560\nmov rcx, rax\njmp loc_1470\nloc_1560:\nlea r8d, [rbx+1]\nmov esi, 4; size\nmov [rsp+48h+var_40], rcx\nmovsxd r8, r8d\nmov rdi, r8; nmemb\nmov [rsp+48h+var_48], r8\ncall _calloc\nmov r8, [rsp+48h+var_48]\nmov rcx, [rsp+48h+var_40]\nxor edi, edi\nmov r13, rax\nnop dword ptr [rax+rax+00h]\nloc_1590:\nmovsxd rdx, dword ptr [r15+rdi*4]\ntest edx, edx\njle short loc_15B2\nmov rax, [r14+rdi*8]\nlea rsi, [rax+rdx*4]\nloc_15A0:\nmovsxd rdx, dword ptr [rax]\nadd rax, 4\nadd dword ptr [r13+rdx*4+0], 1\ncmp rsi, rax\njnz short loc_15A0\nloc_15B2:\nlea rax, [rdi+1]\ncmp rcx, rdi\njz short loc_15C0\nmov rdi, rax\njmp short loc_1590\nloc_15C0:\nlea rdi, ds:0[r8*8]; size\ncall _malloc\nmov r14, rax\ntest ebx, ebx\njs loc_1720\nloc_15D8:\nmovsxd rbx, ebx\nxor eax, eax\nxor ecx, ecx\njmp short loc_15EB\nloc_15E8:\nmov rax, rdx\nloc_15EB:\nmov edx, [r13+rax*4+0]\ntest edx, edx\njle short loc_160C\nmovd xmm0, eax\nmovd xmm5, edx\nmovsxd rsi, ecx\nadd ecx, 1\npunpckldq xmm0, xmm5\nmovq qword ptr [r14+rsi*8], xmm0\nloc_160C:\nlea rdx, [rax+1]\ncmp rbx, rax\njnz short loc_15E8\nmovsxd rsi, ecx; nmemb\nloc_1618:\nlea rcx, compare; compar\nmov edx, 8; size\nmov rdi, r14; base\ncall _qsort\nmovsxd rdi, ebp\nshl rdi, 2; size\ncall _malloc\nmov rbx, rax\ntest ebp, ebp\njle loc_16CD\nlea edx, [rbp-1]\ncmp edx, 3\njbe loc_1727\nmov ecx, edx\nxor eax, eax\nshr ecx, 2\nshl rcx, 4\nnop word ptr [rax+rax+00h]\nloc_1660:\nmovdqu xmm0, xmmword ptr [r14+rax*2]\nmovdqu xmm4, xmmword ptr [r14+rax*2+10h]\nshufps xmm0, xmm4, 88h\nmovups xmmword ptr [rbx+rax], xmm0\nadd rax, 10h\ncmp rcx, rax\njnz short loc_1660\nmov eax, edx\nand eax, 0FFFFFFFCh\nloc_1683:\nmovsxd rdx, eax\nmov edi, [r14+rdx*8]\nlea rsi, ds:0[rdx*8]\nlea rcx, ds:0[rdx*4]\nmov [rbx+rdx*4], edi\nlea edx, [rax+1]\ncmp edx, ebp\njge short loc_16CD\nmov edx, [r14+rsi+8]\nmov [rbx+rcx+4], edx\nlea edx, [rax+2]\ncmp ebp, edx\njle short loc_16CD\nmov edx, [r14+rsi+10h]\nadd eax, 3\nmov [rbx+rcx+8], edx\ncmp ebp, eax\njle short loc_16CD\nmov eax, [r14+rsi+18h]\nmov [rbx+rcx+0Ch], eax\nloc_16CD:\nmov [r12], ebp\nmov rdi, r13; ptr\ncall _free\nmov rdi, r14; ptr\ncall _free\nadd rsp, 18h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_16F3:\nxor eax, eax\njmp loc_1516\nloc_16FA:\nmov esi, 4; size\nmov edi, 1; nmemb\nxor ebx, ebx\ncall _calloc\nmov edi, 8; size\nmov r13, rax\ncall _malloc\nmov r14, rax\njmp loc_15D8\nloc_1720:\nxor esi, esi\njmp loc_1618\nloc_1727:\nxor eax, eax\njmp loc_1683", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2, __int64 a3, int a4, int *a5)\n{\n __int64 v9; // r8\n __int64 v10; // rcx\n signed int v11; // ebx\n int v12; // esi\n __int64 v13; // rdi\n const __m128i *v14; // rax\n __m128i v15; // xmm2\n __m128i v16; // xmm0\n __m128i v17; // xmm1\n __m128i v18; // xmm1\n __m128i v19; // xmm0\n __m128i v20; // xmm0\n __m128i v21; // xmm2\n __m128i v22; // xmm1\n int v23; // eax\n __int64 v24; // r9\n __int64 v25; // rdi\n _DWORD *v26; // r13\n __int64 v27; // rdx\n int *v28; // rax\n int *v29; // rsi\n __int64 v30; // rdx\n _QWORD *v31; // r14\n __int64 v32; // rax\n int v33; // ecx\n signed int v34; // edx\n __int64 v35; // rsi\n size_t v36; // rsi\n char *v37; // rbx\n unsigned int v38; // edx\n __int64 v39; // rax\n signed int v40; // eax\n __int64 v41; // rsi\n __int64 v42; // rcx\n __int64 v44; // [rsp+8h] [rbp-40h]\n\n if ( a2 <= 0 )\n {\n v11 = 0;\n v26 = calloc(1uLL, 4uLL);\n v31 = malloc(8uLL);\n goto LABEL_26;\n }\n v9 = a2;\n v10 = 0LL;\n v11 = 0;\n while ( 1 )\n {\n v12 = *(_DWORD *)(a3 + 4 * v10);\n if ( v12 <= 0 )\n goto LABEL_17;\n v13 = *(_QWORD *)(a1 + 8 * v10);\n if ( (unsigned int)(v12 - 1) <= 2 )\n {\n v23 = 0;\n }\n else\n {\n v14 = *(const __m128i **)(a1 + 8 * v10);\n v15 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v11), 0);\n do\n {\n v16 = _mm_loadu_si128(v14++);\n v17 = _mm_cmpgt_epi32(v16, v15);\n v15 = _mm_or_si128(_mm_andnot_si128(v17, v15), _mm_and_si128(v16, v17));\n }\n while ( (const __m128i *)(v13 + 16LL * ((unsigned int)v12 >> 2)) != v14 );\n v18 = _mm_srli_si128(v15, 8);\n v19 = _mm_cmpgt_epi32(v18, v15);\n v20 = _mm_or_si128(_mm_andnot_si128(v19, v15), _mm_and_si128(v18, v19));\n v21 = _mm_srli_si128(v20, 4);\n v22 = _mm_cmpgt_epi32(v21, v20);\n v11 = _mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v22, v20), _mm_and_si128(v21, v22)));\n if ( (v12 & 3) == 0 )\n goto LABEL_17;\n v23 = v12 & 0x7FFFFFFC;\n }\n v24 = 4LL * v23;\n if ( v11 < *(_DWORD *)(v13 + v24) )\n v11 = *(_DWORD *)(v13 + 4LL * v23);\n if ( v12 > v23 + 1 )\n {\n if ( v11 < *(_DWORD *)(v13 + v24 + 4) )\n v11 = *(_DWORD *)(v13 + v24 + 4);\n if ( v12 > v23 + 2 && v11 < *(_DWORD *)(v13 + v24 + 8) )\n v11 = *(_DWORD *)(v13 + v24 + 8);\n }\nLABEL_17:\n if ( v9 == v10 + 1 )\n break;\n ++v10;\n }\n v44 = v10;\n v25 = 0LL;\n v26 = calloc(v11 + 1, 4uLL);\n while ( 1 )\n {\n v27 = *(int *)(a3 + 4 * v25);\n if ( (int)v27 > 0 )\n {\n v28 = *(int **)(a1 + 8 * v25);\n v29 = &v28[v27];\n do\n {\n v30 = *v28++;\n ++v26[v30];\n }\n while ( v29 != v28 );\n }\n if ( v44 == v25 )\n break;\n ++v25;\n }\n v31 = malloc(8LL * (v11 + 1));\n if ( v11 < 0 )\n {\n v36 = 0LL;\n }\n else\n {\nLABEL_26:\n v32 = 0LL;\n v33 = 0;\n while ( 1 )\n {\n v34 = v26[v32];\n if ( v34 > 0 )\n {\n v35 = v33++;\n v31[v35] = _mm_unpacklo_epi32(_mm_cvtsi32_si128(v32), _mm_cvtsi32_si128(v34)).m128i_u64[0];\n }\n if ( v11 == v32 )\n break;\n ++v32;\n }\n v36 = v33;\n }\n qsort(v31, v36, 8uLL, compare);\n v37 = (char *)malloc(4LL * a4);\n if ( a4 > 0 )\n {\n v38 = a4 - 1;\n if ( (unsigned int)(a4 - 1) <= 3 )\n {\n v40 = 0;\n }\n else\n {\n v39 = 0LL;\n do\n {\n *(__m128 *)&v37[v39 * 4] = _mm_shuffle_ps(\n (__m128)_mm_loadu_si128((const __m128i *)&v31[v39]),\n (__m128)_mm_loadu_si128((const __m128i *)&v31[v39 + 2]),\n 136);\n v39 += 4LL;\n }\n while ( 4LL * (v38 >> 2) != v39 );\n v40 = v38 & 0xFFFFFFFC;\n }\n v41 = v40;\n v42 = 4LL * v40;\n *(_DWORD *)&v37[v42] = v31[v41];\n if ( v40 + 1 < a4 )\n {\n *(_DWORD *)&v37[v42 + 4] = v31[v41 + 1];\n if ( a4 > v40 + 2 )\n {\n *(_DWORD *)&v37[v42 + 8] = v31[v41 + 2];\n if ( a4 > v40 + 3 )\n *(_DWORD *)&v37[v42 + 12] = v31[v41 + 3];\n }\n }\n }\n *a5 = a4;\n free(v26);\n free(v31);\n return v37;\n}", + "ida_strip_asm": "sub_1440:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12, r8\npush rbp\nmov ebp, ecx\npush rbx\nsub rsp, 18h\ntest esi, esi\njle loc_16FA\nmov r14, rdi\nmov r15, rdx\nmovsxd r8, esi\nxor ecx, ecx\nxor ebx, ebx\nnop dword ptr [rax+00h]\nloc_1470:\nmov esi, [r15+rcx*4]\ntest esi, esi\njle loc_154B\nlea eax, [rsi-1]\nmov rdi, [r14+rcx*8]\ncmp eax, 2\njbe loc_16F3\nmov edx, esi\nmovd xmm3, ebx\nmov rax, rdi\nshr edx, 2\npshufd xmm2, xmm3, 0\nshl rdx, 4\nadd rdx, rdi\nnop dword ptr [rax+00h]\nloc_14A8:\nmovdqu xmm0, xmmword ptr [rax]\nadd rax, 10h\nmovdqa xmm1, xmm0\npcmpgtd xmm1, xmm2\npand xmm0, xmm1\npandn xmm1, xmm2\nmovdqa xmm2, xmm1\npor xmm2, xmm0\ncmp rdx, rax\njnz short loc_14A8\nmovdqa xmm1, xmm2\npsrldq xmm1, 8\nmovdqa xmm0, xmm1\npcmpgtd xmm0, xmm2\npand xmm1, xmm0\npandn xmm0, xmm2\npor xmm0, xmm1\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\nmovdqa xmm1, xmm2\npcmpgtd xmm1, xmm0\npand xmm2, xmm1\npandn xmm1, xmm0\npor xmm1, xmm2\nmovd ebx, xmm1\ntest sil, 3\njz short loc_154B\nmov eax, esi\nand eax, 0FFFFFFFCh\nloc_1516:\nmovsxd rdx, eax\nlea r9, ds:0[rdx*4]\nmov edx, [rdi+rdx*4]\ncmp ebx, edx\ncmovl ebx, edx\nlea edx, [rax+1]\ncmp esi, edx\njle short loc_154B\nmov edx, [rdi+r9+4]\ncmp ebx, edx\ncmovl ebx, edx\nadd eax, 2\ncmp esi, eax\njle short loc_154B\nmov eax, [rdi+r9+8]\ncmp ebx, eax\ncmovl ebx, eax\nloc_154B:\nlea rax, [rcx+1]\ncmp r8, rax\njz short loc_1560\nmov rcx, rax\njmp loc_1470\nloc_1560:\nlea r8d, [rbx+1]\nmov esi, 4; size\nmov [rsp+48h+var_40], rcx\nmovsxd r8, r8d\nmov rdi, r8; nmemb\nmov [rsp+48h+var_48], r8\ncall _calloc\nmov r8, [rsp+48h+var_48]\nmov rcx, [rsp+48h+var_40]\nxor edi, edi\nmov r13, rax\nnop dword ptr [rax+rax+00h]\nloc_1590:\nmovsxd rdx, dword ptr [r15+rdi*4]\ntest edx, edx\njle short loc_15B2\nmov rax, [r14+rdi*8]\nlea rsi, [rax+rdx*4]\nloc_15A0:\nmovsxd rdx, dword ptr [rax]\nadd rax, 4\nadd dword ptr [r13+rdx*4+0], 1\ncmp rsi, rax\njnz short loc_15A0\nloc_15B2:\nlea rax, [rdi+1]\ncmp rcx, rdi\njz short loc_15C0\nmov rdi, rax\njmp short loc_1590\nloc_15C0:\nlea rdi, ds:0[r8*8]; size\ncall _malloc\nmov r14, rax\ntest ebx, ebx\njs loc_1720\nloc_15D8:\nmovsxd rbx, ebx\nxor eax, eax\nxor ecx, ecx\njmp short loc_15EB\nloc_15E8:\nmov rax, rdx\nloc_15EB:\nmov edx, [r13+rax*4+0]\ntest edx, edx\njle short loc_160C\nmovd xmm0, eax\nmovd xmm5, edx\nmovsxd rsi, ecx\nadd ecx, 1\npunpckldq xmm0, xmm5\nmovq qword ptr [r14+rsi*8], xmm0\nloc_160C:\nlea rdx, [rax+1]\ncmp rbx, rax\njnz short loc_15E8\nmovsxd rsi, ecx; nmemb\nloc_1618:\nlea rcx, compar; compar\nmov edx, 8; size\nmov rdi, r14; base\ncall _qsort\nmovsxd rdi, ebp\nshl rdi, 2; size\ncall _malloc\nmov rbx, rax\ntest ebp, ebp\njle loc_16CD\nlea edx, [rbp-1]\ncmp edx, 3\njbe loc_1727\nmov ecx, edx\nxor eax, eax\nshr ecx, 2\nshl rcx, 4\nnop word ptr [rax+rax+00h]\nloc_1660:\nmovdqu xmm0, xmmword ptr [r14+rax*2]\nmovdqu xmm4, xmmword ptr [r14+rax*2+10h]\nshufps xmm0, xmm4, 88h\nmovups xmmword ptr [rbx+rax], xmm0\nadd rax, 10h\ncmp rcx, rax\njnz short loc_1660\nmov eax, edx\nand eax, 0FFFFFFFCh\nloc_1683:\nmovsxd rdx, eax\nmov edi, [r14+rdx*8]\nlea rsi, ds:0[rdx*8]\nlea rcx, ds:0[rdx*4]\nmov [rbx+rdx*4], edi\nlea edx, [rax+1]\ncmp edx, ebp\njge short loc_16CD\nmov edx, [r14+rsi+8]\nmov [rbx+rcx+4], edx\nlea edx, [rax+2]\ncmp ebp, edx\njle short loc_16CD\nmov edx, [r14+rsi+10h]\nadd eax, 3\nmov [rbx+rcx+8], edx\ncmp ebp, eax\njle short loc_16CD\nmov eax, [r14+rsi+18h]\nmov [rbx+rcx+0Ch], eax\nloc_16CD:\nmov [r12], ebp\nmov rdi, r13; ptr\ncall _free\nmov rdi, r14; ptr\ncall _free\nadd rsp, 18h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_16F3:\nxor eax, eax\njmp loc_1516\nloc_16FA:\nmov esi, 4; size\nmov edi, 1; nmemb\nxor ebx, ebx\ncall _calloc\nmov edi, 8; size\nmov r13, rax\ncall _malloc\nmov r14, rax\njmp loc_15D8\nloc_1720:\nxor esi, esi\njmp loc_1618\nloc_1727:\nxor eax, eax\njmp loc_1683", + "ida_strip_pseudo": "char *__fastcall sub_1440(__int64 a1, int a2, __int64 a3, int a4, int *a5)\n{\n __int64 v9; // r8\n __int64 v10; // rcx\n signed int v11; // ebx\n int v12; // esi\n __int64 v13; // rdi\n const __m128i *v14; // rax\n __m128i v15; // xmm2\n __m128i v16; // xmm0\n __m128i v17; // xmm1\n __m128i v18; // xmm1\n __m128i v19; // xmm0\n __m128i v20; // xmm0\n __m128i v21; // xmm2\n __m128i v22; // xmm1\n int v23; // eax\n __int64 v24; // r9\n __int64 v25; // rdi\n _DWORD *v26; // r13\n __int64 v27; // rdx\n int *v28; // rax\n int *v29; // rsi\n __int64 v30; // rdx\n _QWORD *v31; // r14\n __int64 v32; // rax\n int v33; // ecx\n signed int v34; // edx\n __int64 v35; // rsi\n size_t v36; // rsi\n char *v37; // rbx\n unsigned int v38; // edx\n __int64 v39; // rax\n signed int v40; // eax\n __int64 v41; // rsi\n __int64 v42; // rcx\n __int64 v44; // [rsp+8h] [rbp-40h]\n\n if ( a2 <= 0 )\n {\n v11 = 0;\n v26 = calloc(1uLL, 4uLL);\n v31 = malloc(8uLL);\n goto LABEL_26;\n }\n v9 = a2;\n v10 = 0LL;\n v11 = 0;\n while ( 1 )\n {\n v12 = *(_DWORD *)(a3 + 4 * v10);\n if ( v12 <= 0 )\n goto LABEL_17;\n v13 = *(_QWORD *)(a1 + 8 * v10);\n if ( (unsigned int)(v12 - 1) <= 2 )\n {\n v23 = 0;\n }\n else\n {\n v14 = *(const __m128i **)(a1 + 8 * v10);\n v15 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v11), 0);\n do\n {\n v16 = _mm_loadu_si128(v14++);\n v17 = _mm_cmpgt_epi32(v16, v15);\n v15 = _mm_or_si128(_mm_andnot_si128(v17, v15), _mm_and_si128(v16, v17));\n }\n while ( (const __m128i *)(v13 + 16LL * ((unsigned int)v12 >> 2)) != v14 );\n v18 = _mm_srli_si128(v15, 8);\n v19 = _mm_cmpgt_epi32(v18, v15);\n v20 = _mm_or_si128(_mm_andnot_si128(v19, v15), _mm_and_si128(v18, v19));\n v21 = _mm_srli_si128(v20, 4);\n v22 = _mm_cmpgt_epi32(v21, v20);\n v11 = _mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v22, v20), _mm_and_si128(v21, v22)));\n if ( (v12 & 3) == 0 )\n goto LABEL_17;\n v23 = v12 & 0x7FFFFFFC;\n }\n v24 = 4LL * v23;\n if ( v11 < *(_DWORD *)(v13 + v24) )\n v11 = *(_DWORD *)(v13 + 4LL * v23);\n if ( v12 > v23 + 1 )\n {\n if ( v11 < *(_DWORD *)(v13 + v24 + 4) )\n v11 = *(_DWORD *)(v13 + v24 + 4);\n if ( v12 > v23 + 2 && v11 < *(_DWORD *)(v13 + v24 + 8) )\n v11 = *(_DWORD *)(v13 + v24 + 8);\n }\nLABEL_17:\n if ( v9 == v10 + 1 )\n break;\n ++v10;\n }\n v44 = v10;\n v25 = 0LL;\n v26 = calloc(v11 + 1, 4uLL);\n while ( 1 )\n {\n v27 = *(int *)(a3 + 4 * v25);\n if ( (int)v27 > 0 )\n {\n v28 = *(int **)(a1 + 8 * v25);\n v29 = &v28[v27];\n do\n {\n v30 = *v28++;\n ++v26[v30];\n }\n while ( v29 != v28 );\n }\n if ( v44 == v25 )\n break;\n ++v25;\n }\n v31 = malloc(8LL * (v11 + 1));\n if ( v11 < 0 )\n {\n v36 = 0LL;\n }\n else\n {\nLABEL_26:\n v32 = 0LL;\n v33 = 0;\n while ( 1 )\n {\n v34 = v26[v32];\n if ( v34 > 0 )\n {\n v35 = v33++;\n v31[v35] = _mm_unpacklo_epi32(_mm_cvtsi32_si128(v32), _mm_cvtsi32_si128(v34)).m128i_u64[0];\n }\n if ( v11 == v32 )\n break;\n ++v32;\n }\n v36 = v33;\n }\n qsort(v31, v36, 8uLL, compar);\n v37 = (char *)malloc(4LL * a4);\n if ( a4 > 0 )\n {\n v38 = a4 - 1;\n if ( (unsigned int)(a4 - 1) <= 3 )\n {\n v40 = 0;\n }\n else\n {\n v39 = 0LL;\n do\n {\n *(__m128 *)&v37[v39 * 4] = _mm_shuffle_ps(\n (__m128)_mm_loadu_si128((const __m128i *)&v31[v39]),\n (__m128)_mm_loadu_si128((const __m128i *)&v31[v39 + 2]),\n 136);\n v39 += 4LL;\n }\n while ( 4LL * (v38 >> 2) != v39 );\n v40 = v38 & 0xFFFFFFFC;\n }\n v41 = v40;\n v42 = 4LL * v40;\n *(_DWORD *)&v37[v42] = v31[v41];\n if ( v40 + 1 < a4 )\n {\n *(_DWORD *)&v37[v42 + 4] = v31[v41 + 1];\n if ( a4 > v40 + 2 )\n {\n *(_DWORD *)&v37[v42 + 8] = v31[v41 + 2];\n if ( a4 > v40 + 3 )\n *(_DWORD *)&v37[v42 + 12] = v31[v41 + 3];\n }\n }\n }\n *a5 = a4;\n free(v26);\n free(v31);\n return v37;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1440(long long a1, int a2, long long a3, int a4, int *a5) {\n long long v9;\n long long v10;\n signed int v11;\n int v12;\n long long v13;\n const __m128i *v14;\n __m128i v15;\n __m128i v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n __m128i v20;\n __m128i v21;\n __m128i v22;\n int v23;\n long long v24;\n long long v25;\n uint32_t *v26;\n long long v27;\n int *v28;\n int *v29;\n long long v30;\n uint64_t *v31;\n long long v32;\n int v33;\n signed int v34;\n long long v35;\n unsigned int v36;\n char *v37;\n unsigned int v38;\n long long v39;\n signed int v40;\n long long v41;\n long long v42;\n long long v44;\n if (a2 <= 0) {\n v11 = 0;\n v26 = calloc(1uLL, 4uLL);\n v31 = malloc(8uLL);\n goto LABEL_26;\n }\n v9 = a2;\n v10 = 0LL;\n v11 = 0;\n while (1) {\n v12 = *(uint32_t *)(a3 + 4 * v10);\n if (v12 <= 0) goto LABEL_17;\n v13 = *(uint64_t *)(a1 + 8 * v10);\n if ((unsigned int)(v12 - 1) <= 2) {\n v23 = 0;\n } else {\n v14 = *(const __m128i **)(a1 + 8 * v10);\n v15 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v11), 0);\n do {\n v16 = _mm_loadu_si128(v14++);\n v17 = _mm_cmpgt_epi32(v16, v15);\n v15 = _mm_or_si128(_mm_andnot_si128(v17, v15), _mm_and_si128(v16, v17));\n } while ((const __m128i *)(v13 + 16LL * ((unsigned int)v12 >> 2)) != v14);\n v18 = _mm_srli_si128(v15, 8);\n v19 = _mm_cmpgt_epi32(v18, v15);\n v20 = _mm_or_si128(_mm_andnot_si128(v19, v15), _mm_and_si128(v18, v19));\n v21 = _mm_srli_si128(v20, 4);\n v22 = _mm_cmpgt_epi32(v21, v20);\n v11 = _mm_cvtsi128_si32(\n _mm_or_si128(_mm_andnot_si128(v22, v20), _mm_and_si128(v21, v22)));\n if ((v12 & 3) == 0) goto LABEL_17;\n v23 = v12 & 2147483644;\n }\n v24 = 4LL * v23;\n if (v11 < *(uint32_t *)(v13 + v24)) v11 = *(uint32_t *)(v13 + 4LL * v23);\n if (v12 > v23 + 1) {\n if (v11 < *(uint32_t *)(v13 + v24 + 4))\n v11 = *(uint32_t *)(v13 + v24 + 4);\n if (v12 > v23 + 2 && v11 < *(uint32_t *)(v13 + v24 + 8))\n v11 = *(uint32_t *)(v13 + v24 + 8);\n }\n LABEL_17:\n if (v9 == v10 + 1) break;\n ++v10;\n }\n v44 = v10;\n v25 = 0LL;\n v26 = calloc(v11 + 1, 4uLL);\n while (1) {\n v27 = *(int *)(a3 + 4 * v25);\n if ((int)v27 > 0) {\n v28 = *(int **)(a1 + 8 * v25);\n v29 = &v28[v27];\n do {\n v30 = *v28++;\n ++v26[v30];\n } while (v29 != v28);\n }\n if (v44 == v25) break;\n ++v25;\n }\n v31 = malloc(8LL * (v11 + 1));\n if (v11 < 0) {\n v36 = 0LL;\n } else {\n LABEL_26:\n v32 = 0LL;\n v33 = 0;\n while (1) {\n v34 = v26[v32];\n if (v34 > 0) {\n v35 = v33++;\n v31[v35] =\n _mm_unpacklo_epi32(_mm_cvtsi32_si128(v32), _mm_cvtsi32_si128(v34))\n .m128i_u64[0];\n }\n if (v11 == v32) break;\n ++v32;\n }\n v36 = v33;\n }\n qsort(v31, v36, 8uLL, compar);\n v37 = (char *)malloc(4LL * a4);\n if (a4 > 0) {\n v38 = a4 - 1;\n if ((unsigned int)(a4 - 1) <= 3) {\n v40 = 0;\n } else {\n v39 = 0LL;\n do {\n *(__m128 *)&v37[v39 * 4] = _mm_shuffle_ps(\n (__m128)_mm_loadu_si128((const __m128i *)&v31[v39]),\n (__m128)_mm_loadu_si128((const __m128i *)&v31[v39 + 2]), 136);\n v39 += 4LL;\n } while (4LL * (v38 >> 2) != v39);\n v40 = v38 & 4294967292;\n }\n v41 = v40;\n v42 = 4LL * v40;\n *(uint32_t *)&v37[v42] = v31[v41];\n if (v40 + 1 < a4) {\n *(uint32_t *)&v37[v42 + 4] = v31[v41 + 1];\n if (a4 > v40 + 2) {\n *(uint32_t *)&v37[v42 + 8] = v31[v41 + 2];\n if (a4 > v40 + 3) *(uint32_t *)&v37[v42 + 12] = v31[v41 + 3];\n }\n }\n }\n *a5 = a4;\n free(v26);\n free(v31);\n return v37;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2, long long a3, int a4, int *a5) {\n long long v9;\n long long v10;\n signed int v11;\n int v12;\n long long v13;\n const __m128i *v14;\n __m128i v15;\n __m128i v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n __m128i v20;\n __m128i v21;\n __m128i v22;\n int v23;\n long long v24;\n long long v25;\n uint32_t *v26;\n long long v27;\n int *v28;\n int *v29;\n long long v30;\n uint64_t *v31;\n long long v32;\n int v33;\n signed int v34;\n long long v35;\n unsigned int v36;\n char *v37;\n unsigned int v38;\n long long v39;\n signed int v40;\n long long v41;\n long long v42;\n long long v44;\n if (a2 <= 0) {\n v11 = 0;\n v26 = calloc(1uLL, 4uLL);\n v31 = malloc(8uLL);\n goto LABEL_26;\n }\n v9 = a2;\n v10 = 0LL;\n v11 = 0;\n while (1) {\n v12 = *(uint32_t *)(a3 + 4 * v10);\n if (v12 <= 0) goto LABEL_17;\n v13 = *(uint64_t *)(a1 + 8 * v10);\n if ((unsigned int)(v12 - 1) <= 2) {\n v23 = 0;\n } else {\n v14 = *(const __m128i **)(a1 + 8 * v10);\n v15 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v11), 0);\n do {\n v16 = _mm_loadu_si128(v14++);\n v17 = _mm_cmpgt_epi32(v16, v15);\n v15 = _mm_or_si128(_mm_andnot_si128(v17, v15), _mm_and_si128(v16, v17));\n } while ((const __m128i *)(v13 + 16LL * ((unsigned int)v12 >> 2)) != v14);\n v18 = _mm_srli_si128(v15, 8);\n v19 = _mm_cmpgt_epi32(v18, v15);\n v20 = _mm_or_si128(_mm_andnot_si128(v19, v15), _mm_and_si128(v18, v19));\n v21 = _mm_srli_si128(v20, 4);\n v22 = _mm_cmpgt_epi32(v21, v20);\n v11 = _mm_cvtsi128_si32(\n _mm_or_si128(_mm_andnot_si128(v22, v20), _mm_and_si128(v21, v22)));\n if ((v12 & 3) == 0) goto LABEL_17;\n v23 = v12 & 2147483644;\n }\n v24 = 4LL * v23;\n if (v11 < *(uint32_t *)(v13 + v24)) v11 = *(uint32_t *)(v13 + 4LL * v23);\n if (v12 > v23 + 1) {\n if (v11 < *(uint32_t *)(v13 + v24 + 4))\n v11 = *(uint32_t *)(v13 + v24 + 4);\n if (v12 > v23 + 2 && v11 < *(uint32_t *)(v13 + v24 + 8))\n v11 = *(uint32_t *)(v13 + v24 + 8);\n }\n LABEL_17:\n if (v9 == v10 + 1) break;\n ++v10;\n }\n v44 = v10;\n v25 = 0LL;\n v26 = calloc(v11 + 1, 4uLL);\n while (1) {\n v27 = *(int *)(a3 + 4 * v25);\n if ((int)v27 > 0) {\n v28 = *(int **)(a1 + 8 * v25);\n v29 = &v28[v27];\n do {\n v30 = *v28++;\n ++v26[v30];\n } while (v29 != v28);\n }\n if (v44 == v25) break;\n ++v25;\n }\n v31 = malloc(8LL * (v11 + 1));\n if (v11 < 0) {\n v36 = 0LL;\n } else {\n LABEL_26:\n v32 = 0LL;\n v33 = 0;\n while (1) {\n v34 = v26[v32];\n if (v34 > 0) {\n v35 = v33++;\n v31[v35] =\n _mm_unpacklo_epi32(_mm_cvtsi32_si128(v32), _mm_cvtsi32_si128(v34))\n .m128i_u64[0];\n }\n if (v11 == v32) break;\n ++v32;\n }\n v36 = v33;\n }\n qsort(v31, v36, 8uLL, compare);\n v37 = (char *)malloc(4LL * a4);\n if (a4 > 0) {\n v38 = a4 - 1;\n if ((unsigned int)(a4 - 1) <= 3) {\n v40 = 0;\n } else {\n v39 = 0LL;\n do {\n *(__m128 *)&v37[v39 * 4] = _mm_shuffle_ps(\n (__m128)_mm_loadu_si128((const __m128i *)&v31[v39]),\n (__m128)_mm_loadu_si128((const __m128i *)&v31[v39 + 2]), 136);\n v39 += 4LL;\n } while (4LL * (v38 >> 2) != v39);\n v40 = v38 & 4294967292;\n }\n v41 = v40;\n v42 = 4LL * v40;\n *(uint32_t *)&v37[v42] = v31[v41];\n if (v40 + 1 < a4) {\n *(uint32_t *)&v37[v42 + 4] = v31[v41 + 1];\n if (a4 > v40 + 2) {\n *(uint32_t *)&v37[v42 + 8] = v31[v41 + 2];\n if (a4 > v40 + 3) *(uint32_t *)&v37[v42 + 12] = v31[v41 + 3];\n }\n }\n }\n *a5 = a4;\n free(v26);\n free(v31);\n return v37;\n}" + }, + { + "index": 32, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int maxPrime = -1;\n while (n % 2 == 0) {\n maxPrime = 2;\n n >>= 1;\n }\n for (int i = 3; i <= sqrt(n); i += 2) {\n while (n % i == 0) {\n maxPrime = i;\n n = n / i;\n }\n }\n if (n > 2) {\n maxPrime = n;\n }\n return maxPrime;\n}", + "test": "int main() {\n\n assert(func0(15) == 5);\n\n assert(func0(6) == 3);\n\n assert(func0(2) == 2);\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %edi,-0x14(%rbp)\nmovl $0xffffffff,-0x8(%rbp)\njmp 11ab \nmovl $0x2,-0x8(%rbp)\nsarl -0x14(%rbp)\nmov -0x14(%rbp),%eax\nand $0x1,%eax\ntest %eax,%eax\nje 11a1 \nmovl $0x3,-0x4(%rbp)\njmp 11df \nmov -0x4(%rbp),%eax\nmov %eax,-0x8(%rbp)\nmov -0x14(%rbp),%eax\ncltd\nidivl -0x4(%rbp)\nmov %eax,-0x14(%rbp)\nmov -0x14(%rbp),%eax\ncltd\nidivl -0x4(%rbp)\nmov %edx,%eax\ntest %eax,%eax\nje 11be \naddl $0x2,-0x4(%rbp)\ncvtsi2sdl -0x4(%rbp),%xmm1\nmovsd %xmm1,-0x20(%rbp)\ncvtsi2sdl -0x14(%rbp),%xmm0\ncallq 1090 \ncomisd -0x20(%rbp),%xmm0\njae 11ce \ncmpl $0x2,-0x14(%rbp)\njle 1206 \nmov -0x14(%rbp),%eax\nmov %eax,-0x8(%rbp)\nmov -0x8(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov [rbp+var_8], 0FFFFFFFFh\njmp short loc_11AB\nloc_11A1:\nmov [rbp+var_8], 2\nsar [rbp+var_14], 1\nloc_11AB:\nmov eax, [rbp+var_14]\nand eax, 1\ntest eax, eax\njz short loc_11A1\nmov [rbp+var_4], 3\njmp short loc_11DF\nloc_11BE:\nmov eax, [rbp+var_4]\nmov [rbp+var_8], eax\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\nmov [rbp+var_14], eax\nloc_11CE:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njz short loc_11BE\nadd [rbp+var_4], 2\nloc_11DF:\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_4]\nmovsd [rbp+var_20], xmm1\npxor xmm2, xmm2\ncvtsi2sd xmm2, [rbp+var_14]\nmovq rax, xmm2\nmovq xmm0, rax; x\ncall _sqrt\nmovq rax, xmm0\nmovq xmm3, rax\ncomisd xmm3, [rbp+var_20]\njnb short loc_11CE\ncmp [rbp+var_14], 2\njle short loc_1222\nmov eax, [rbp+var_14]\nmov [rbp+var_8], eax\nloc_1222:\nmov eax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v3; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v3 = -1;\n while ( (a1 & 1) == 0 )\n {\n v3 = 2;\n a1 >>= 1;\n }\n for ( i = 3; sqrt((double)a1) >= (double)i; i += 2 )\n {\n while ( !(a1 % i) )\n {\n v3 = i;\n a1 /= i;\n }\n }\n if ( a1 > 2 )\n return (unsigned int)a1;\n return v3;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov [rbp+var_8], 0FFFFFFFFh\njmp short loc_11AB\nloc_11A1:\nmov [rbp+var_8], 2\nsar [rbp+var_14], 1\nloc_11AB:\nmov eax, [rbp+var_14]\nand eax, 1\ntest eax, eax\njz short loc_11A1\nmov [rbp+var_4], 3\njmp short loc_11DF\nloc_11BE:\nmov eax, [rbp+var_4]\nmov [rbp+var_8], eax\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\nmov [rbp+var_14], eax\nloc_11CE:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njz short loc_11BE\nadd [rbp+var_4], 2\nloc_11DF:\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_4]\nmovsd [rbp+var_20], xmm1\npxor xmm2, xmm2\ncvtsi2sd xmm2, [rbp+var_14]\nmovq rax, xmm2\nmovq xmm0, rax; x\ncall _sqrt\nmovq rax, xmm0\nmovq xmm3, rax\ncomisd xmm3, [rbp+var_20]\njnb short loc_11CE\ncmp [rbp+var_14], 2\njle short loc_1222\nmov eax, [rbp+var_14]\nmov [rbp+var_8], eax\nloc_1222:\nmov eax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(int a1)\n{\n unsigned int v3; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v3 = -1;\n while ( (a1 & 1) == 0 )\n {\n v3 = 2;\n a1 >>= 1;\n }\n for ( i = 3; sqrt((double)a1) >= (double)i; i += 2 )\n {\n while ( !(a1 % i) )\n {\n v3 = i;\n a1 /= i;\n }\n }\n if ( a1 > 2 )\n return (unsigned int)a1;\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(int a1) {\n unsigned int v3;\n int i;\n v3 = -1;\n while ((a1 & 1) == 0) {\n v3 = 2;\n a1 >>= 1;\n }\n for (i = 3; sqrt((double)a1) >= (double)i; i += 2) {\n while (!(a1 % i)) {\n v3 = i;\n a1 /= i;\n }\n }\n if (a1 > 2) return (unsigned int)a1;\n return v3;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v3;\n int i;\n v3 = -1;\n while ((a1 & 1) == 0) {\n v3 = 2;\n a1 >>= 1;\n }\n for (i = 3; sqrt((double)a1) >= (double)i; i += 2) {\n while (!(a1 % i)) {\n v3 = i;\n a1 /= i;\n }\n }\n if (a1 > 2) return (unsigned int)a1;\n return v3;\n}" + }, + { + "index": 32, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int maxPrime = -1;\n while (n % 2 == 0) {\n maxPrime = 2;\n n >>= 1;\n }\n for (int i = 3; i <= sqrt(n); i += 2) {\n while (n % i == 0) {\n maxPrime = i;\n n = n / i;\n }\n }\n if (n > 2) {\n maxPrime = n;\n }\n return maxPrime;\n}", + "test": "int main() {\n\n assert(func0(15) == 5);\n\n assert(func0(6) == 3);\n\n assert(func0(2) == 2);\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nsub $0x10,%rsp\nmov %edi,%ebx\ntest $0x1,%dil\njne 11b1 \nsar %ebx\ntest $0x1,%bl\nje 119d \nmov $0x2,%r12d\nmov $0x3,%ebp\njmp 11cd \nmov $0xffffffff,%r12d\njmp 11aa \nmov %ebx,%eax\ncltd\nidiv %ebp\nmov %eax,%ebx\ncltd\nidiv %ebp\ntest %edx,%edx\nje 11b9 \nmov %ebp,%r12d\nadd $0x2,%ebp\npxor %xmm2,%xmm2\ncvtsi2sd %ebp,%xmm2\nmovsd %xmm2,(%rsp)\npxor %xmm0,%xmm0\ncvtsi2sd %ebx,%xmm0\nmovapd %xmm0,%xmm1\nsqrtsd %xmm1,%xmm1\nmovsd %xmm1,0x8(%rsp)\npxor %xmm3,%xmm3\nucomisd %xmm0,%xmm3\nja 1212 \nmovsd 0x8(%rsp),%xmm4\ncomisd (%rsp),%xmm4\njb 1219 \nmov %ebx,%eax\ncltd\nidiv %ebp\ntest %edx,%edx\nje 11b9 \njmp 11ca \ncallq 1090 \njmp 11fa \ncmp $0x3,%ebx\ncmovge %ebx,%r12d\nmov %r12d,%eax\nadd $0x10,%rsp\npop %rbx\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov ebx, edi\ntest dil, 1\njnz short loc_11B9\nloc_119F:\nsar ebx, 1\ntest bl, 1\njz short loc_119F\nmov r13d, 2\nloc_11AC:\nmov ebp, 3\nmov r12d, 0\njmp short loc_11D5\nloc_11B9:\nmov r13d, 0FFFFFFFFh\njmp short loc_11AC\nloc_11C1:\nmov eax, ebx\ncdq\nidiv ebp\nmov ebx, eax\ncdq\nidiv ebp\ntest edx, edx\njz short loc_11C1\nmov r13d, ebp\nloc_11D2:\nadd ebp, 2\nloc_11D5:\npxor xmm1, xmm1\ncvtsi2sd xmm1, ebp\nmovsd [rsp+38h+var_30], xmm1\npxor xmm0, xmm0\ncvtsi2sd xmm0, ebx; x\nmovq xmm2, r12\nucomisd xmm2, xmm0\nja short loc_120D\nsqrtsd xmm0, xmm0\nloc_11FA:\ncomisd xmm0, [rsp+38h+var_30]\njb short loc_1214\nmov eax, ebx\ncdq\nidiv ebp\ntest edx, edx\njz short loc_11C1\njmp short loc_11D2\nloc_120D:\ncall _sqrt\njmp short loc_11FA\nloc_1214:\ncmp ebx, 2\ncmovle ebx, r13d\nmov eax, ebx\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // ebx\n unsigned int v2; // r13d\n int i; // ebp\n double v4; // xmm0_8\n double v5; // xmm0_8\n\n v1 = a1;\n if ( (a1 & 1) != 0 )\n {\n v2 = -1;\n }\n else\n {\n do\n v1 >>= 1;\n while ( (v1 & 1) == 0 );\n v2 = 2;\n }\n for ( i = 3; ; i += 2 )\n {\n v4 = (double)v1;\n v5 = (double)v1 < 0.0 ? sqrt(v4) : sqrt(v4);\n if ( v5 < (double)i )\n break;\n if ( !(v1 % i) )\n {\n do\n v1 /= i;\n while ( !(v1 % i) );\n v2 = i;\n }\n }\n if ( v1 <= 2 )\n return v2;\n return (unsigned int)v1;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov ebx, edi\ntest dil, 1\njnz short loc_11B9\nloc_119F:\nsar ebx, 1\ntest bl, 1\njz short loc_119F\nmov r13d, 2\nloc_11AC:\nmov ebp, 3\nmov r12d, 0\njmp short loc_11D5\nloc_11B9:\nmov r13d, 0FFFFFFFFh\njmp short loc_11AC\nloc_11C1:\nmov eax, ebx\ncdq\nidiv ebp\nmov ebx, eax\ncdq\nidiv ebp\ntest edx, edx\njz short loc_11C1\nmov r13d, ebp\nloc_11D2:\nadd ebp, 2\nloc_11D5:\npxor xmm1, xmm1\ncvtsi2sd xmm1, ebp\nmovsd [rsp+38h+var_30], xmm1\npxor xmm0, xmm0\ncvtsi2sd xmm0, ebx; x\nmovq xmm2, r12\nucomisd xmm2, xmm0\nja short loc_120D\nsqrtsd xmm0, xmm0\nloc_11FA:\ncomisd xmm0, [rsp+38h+var_30]\njb short loc_1214\nmov eax, ebx\ncdq\nidiv ebp\ntest edx, edx\njz short loc_11C1\njmp short loc_11D2\nloc_120D:\ncall _sqrt\njmp short loc_11FA\nloc_1214:\ncmp ebx, 2\ncmovle ebx, r13d\nmov eax, ebx\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(int a1)\n{\n int v1; // ebx\n unsigned int v2; // r13d\n int i; // ebp\n double v4; // xmm0_8\n double v5; // xmm0_8\n\n v1 = a1;\n if ( (a1 & 1) != 0 )\n {\n v2 = -1;\n }\n else\n {\n do\n v1 >>= 1;\n while ( (v1 & 1) == 0 );\n v2 = 2;\n }\n for ( i = 3; ; i += 2 )\n {\n v4 = (double)v1;\n v5 = (double)v1 < 0.0 ? sqrt(v4) : sqrt(v4);\n if ( v5 < (double)i )\n break;\n if ( !(v1 % i) )\n {\n do\n v1 /= i;\n while ( !(v1 % i) );\n v2 = i;\n }\n }\n if ( v1 <= 2 )\n return v2;\n return (unsigned int)v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(int a1) {\n int v1;\n unsigned int v2;\n int i;\n double v4;\n double v5;\n v1 = a1;\n if ((a1 & 1) != 0) {\n v2 = -1;\n } else {\n do\n v1 >>= 1;\n while ((v1 & 1) == 0);\n v2 = 2;\n }\n for (i = 3;; i += 2) {\n v4 = (double)v1;\n v5 = (double)v1 < 0.0 ? sqrt(v4) : sqrt(v4);\n if (v5 < (double)i) break;\n if (!(v1 % i)) {\n do\n v1 /= i;\n while (!(v1 % i));\n v2 = i;\n }\n }\n if (v1 <= 2) return v2;\n return (unsigned int)v1;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n unsigned int v2;\n int i;\n double v4;\n double v5;\n v1 = a1;\n if ((a1 & 1) != 0) {\n v2 = -1;\n } else {\n do\n v1 >>= 1;\n while ((v1 & 1) == 0);\n v2 = 2;\n }\n for (i = 3;; i += 2) {\n v4 = (double)v1;\n v5 = (double)v1 < 0.0 ? sqrt(v4) : sqrt(v4);\n if (v5 < (double)i) break;\n if (!(v1 % i)) {\n do\n v1 /= i;\n while (!(v1 % i));\n v2 = i;\n }\n }\n if (v1 <= 2) return v2;\n return (unsigned int)v1;\n}" + }, + { + "index": 32, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int maxPrime = -1;\n while (n % 2 == 0) {\n maxPrime = 2;\n n >>= 1;\n }\n for (int i = 3; i <= sqrt(n); i += 2) {\n while (n % i == 0) {\n maxPrime = i;\n n = n / i;\n }\n }\n if (n > 2) {\n maxPrime = n;\n }\n return maxPrime;\n}", + "test": "int main() {\n\n assert(func0(15) == 5);\n\n assert(func0(6) == 3);\n\n assert(func0(2) == 2);\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbx\nsub $0x28,%rsp\ntest $0x1,%dil\njne 12e2 \nnopl (%rax)\nsar %edi\ntest $0x1,%dil\nje 1258 \nmov $0x2,%r12d\npxor %xmm1,%xmm1\nmov $0x3,%ebx\npxor %xmm4,%xmm4\ncvtsi2sd %edi,%xmm1\nnopw 0x0(%rax,%rax,1)\nucomisd %xmm1,%xmm4\npxor %xmm2,%xmm2\nmovapd %xmm1,%xmm3\ncvtsi2sd %ebx,%xmm2\nsqrtsd %xmm3,%xmm3\nja 12ed \ncomisd %xmm2,%xmm3\njb 12d0 \nmov %edi,%eax\ncltd\nidiv %ebx\ntest %edx,%edx\njne 12c1 \nnopl (%rax)\nmov %edi,%eax\ncltd\nidiv %ebx\ncltd\nmov %eax,%edi\nidiv %ebx\ntest %edx,%edx\nje 12a8 \npxor %xmm1,%xmm1\nmov %ebx,%r12d\ncvtsi2sd %edi,%xmm1\nadd $0x2,%ebx\njmp 1280 \nnopw %cs:0x0(%rax,%rax,1)\ncmp $0x3,%edi\ncmovge %edi,%r12d\nadd $0x28,%rsp\npop %rbx\nmov %r12d,%eax\npop %r12\nretq\nmov $0xffffffff,%r12d\njmpq 1266 \nmovapd %xmm1,%xmm0\nmov %edi,0x1c(%rsp)\nmovsd %xmm3,0x10(%rsp)\nmovsd %xmm2,0x8(%rsp)\nmovsd %xmm1,(%rsp)\ncallq 1090 \nmov 0x1c(%rsp),%edi\nmovsd 0x10(%rsp),%xmm3\npxor %xmm4,%xmm4\nmovsd 0x8(%rsp),%xmm2\nmovsd (%rsp),%xmm1\njmpq 1296 \nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 28h\ntest dil, 1\njnz short loc_12C7\nloc_1250:\nsar edi, 1\ntest dil, 1\njz short loc_1250\nmov ebp, 2\nloc_125D:\npxor xmm1, xmm1\nmov ebx, 3\npxor xmm3, xmm3\ncvtsi2sd xmm1, edi\nxchg ax, ax\nloc_1270:\nucomisd xmm3, xmm1\npxor xmm2, xmm2\ncvtsi2sd xmm2, ebx\nja short loc_12CE\nmovapd xmm0, xmm1\nsqrtsd xmm0, xmm0\nloc_1286:\ncomisd xmm0, xmm2\njb short loc_12B8\nmov eax, edi\ncdq\nidiv ebx\ntest edx, edx\njnz short loc_12B0\nnop dword ptr [rax]\nloc_1298:\nmov eax, edi\ncdq\nidiv ebx\ncdq\nmov edi, eax\nidiv ebx\ntest edx, edx\njz short loc_1298\npxor xmm1, xmm1\nmov ebp, ebx\ncvtsi2sd xmm1, edi\nloc_12B0:\nadd ebx, 2\njmp short loc_1270\nloc_12B8:\ncmp edi, 2\ncmovle edi, ebp\nadd rsp, 28h\npop rbx\npop rbp\nmov eax, edi\nretn\nloc_12C7:\nmov ebp, 0FFFFFFFFh\njmp short loc_125D\nloc_12CE:\nmovapd xmm0, xmm1; x\nmov [rsp+38h+var_1C], edi\nmovsd [rsp+38h+var_28], xmm2\nmovsd [rsp+38h+var_30], xmm1\ncall _sqrt\nmov edi, [rsp+38h+var_1C]\nmovsd xmm2, [rsp+38h+var_28]\npxor xmm3, xmm3\nmovsd xmm1, [rsp+38h+var_30]\njmp short loc_1286", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v1; // ebp\n int v2; // ebx\n double v3; // xmm1_8\n double v4; // xmm2_8\n double v5; // xmm0_8\n int v6; // edx\n\n if ( (a1 & 1) != 0 )\n {\n v1 = -1;\n }\n else\n {\n do\n a1 >>= 1;\n while ( (a1 & 1) == 0 );\n v1 = 2;\n }\n v2 = 3;\n v3 = (double)a1;\n while ( 1 )\n {\n v4 = (double)v2;\n if ( v3 < 0.0 )\n {\n v5 = sqrt(v3);\n v4 = (double)v2;\n }\n else\n {\n v5 = sqrt(v3);\n }\n if ( v5 < v4 )\n break;\n if ( !(a1 % v2) )\n {\n do\n {\n v6 = (a1 / v2) >> 31;\n a1 /= v2;\n }\n while ( !(unsigned int)(__SPAIR64__(v6, a1) % v2) );\n v1 = v2;\n v3 = (double)a1;\n }\n v2 += 2;\n }\n if ( a1 <= 2 )\n return v1;\n return (unsigned int)a1;\n}", + "ida_strip_asm": "sub_1240:\nendbr64\npush rbp\npush rbx\nsub rsp, 28h\ntest dil, 1\njnz short loc_12C7\nloc_1250:\nsar edi, 1\ntest dil, 1\njz short loc_1250\nmov ebp, 2\nloc_125D:\npxor xmm1, xmm1\nmov ebx, 3\npxor xmm3, xmm3\ncvtsi2sd xmm1, edi\nxchg ax, ax\nloc_1270:\nucomisd xmm3, xmm1\npxor xmm2, xmm2\ncvtsi2sd xmm2, ebx\nja short loc_12CE\nmovapd xmm0, xmm1\nsqrtsd xmm0, xmm0\nloc_1286:\ncomisd xmm0, xmm2\njb short loc_12B8\nmov eax, edi\ncdq\nidiv ebx\ntest edx, edx\njnz short loc_12B0\nnop dword ptr [rax]\nloc_1298:\nmov eax, edi\ncdq\nidiv ebx\ncdq\nmov edi, eax\nidiv ebx\ntest edx, edx\njz short loc_1298\npxor xmm1, xmm1\nmov ebp, ebx\ncvtsi2sd xmm1, edi\nloc_12B0:\nadd ebx, 2\njmp short loc_1270\nloc_12B8:\ncmp edi, 2\ncmovle edi, ebp\nadd rsp, 28h\npop rbx\npop rbp\nmov eax, edi\nretn\nloc_12C7:\nmov ebp, 0FFFFFFFFh\njmp short loc_125D\nloc_12CE:\nmovapd xmm0, xmm1; x\nmov [rsp+38h+var_1C], edi\nmovsd [rsp+38h+var_28], xmm2\nmovsd [rsp+38h+var_30], xmm1\ncall _sqrt\nmov edi, [rsp+38h+var_1C]\nmovsd xmm2, [rsp+38h+var_28]\npxor xmm3, xmm3\nmovsd xmm1, [rsp+38h+var_30]\njmp short loc_1286", + "ida_strip_pseudo": "__int64 __fastcall sub_1240(int a1)\n{\n unsigned int v1; // ebp\n int v2; // ebx\n double v3; // xmm1_8\n double v4; // xmm2_8\n double v5; // xmm0_8\n int v6; // edx\n\n if ( (a1 & 1) != 0 )\n {\n v1 = -1;\n }\n else\n {\n do\n a1 >>= 1;\n while ( (a1 & 1) == 0 );\n v1 = 2;\n }\n v2 = 3;\n v3 = (double)a1;\n while ( 1 )\n {\n v4 = (double)v2;\n if ( v3 < 0.0 )\n {\n v5 = sqrt(v3);\n v4 = (double)v2;\n }\n else\n {\n v5 = sqrt(v3);\n }\n if ( v5 < v4 )\n break;\n if ( !(a1 % v2) )\n {\n do\n {\n v6 = (a1 / v2) >> 31;\n a1 /= v2;\n }\n while ( !(unsigned int)(__SPAIR64__(v6, a1) % v2) );\n v1 = v2;\n v3 = (double)a1;\n }\n v2 += 2;\n }\n if ( a1 <= 2 )\n return v1;\n return (unsigned int)a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1240(int a1) {\n unsigned int v1;\n int v2;\n double v3;\n double v4;\n double v5;\n int v6;\n if ((a1 & 1) != 0) {\n v1 = -1;\n } else {\n do\n a1 >>= 1;\n while ((a1 & 1) == 0);\n v1 = 2;\n }\n v2 = 3;\n v3 = (double)a1;\n while (1) {\n v4 = (double)v2;\n if (v3 < 0.0) {\n v5 = sqrt(v3);\n v4 = (double)v2;\n } else {\n v5 = sqrt(v3);\n }\n if (v5 < v4) break;\n if (!(a1 % v2)) {\n do {\n v6 = (a1 / v2) >> 31;\n a1 /= v2;\n } while (!(unsigned int)(__SPAIR64__(v6, a1) % v2));\n v1 = v2;\n v3 = (double)a1;\n }\n v2 += 2;\n }\n if (a1 <= 2) return v1;\n return (unsigned int)a1;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v1;\n int v2;\n double v3;\n double v4;\n double v5;\n int v6;\n if ((a1 & 1) != 0) {\n v1 = -1;\n } else {\n do\n a1 >>= 1;\n while ((a1 & 1) == 0);\n v1 = 2;\n }\n v2 = 3;\n v3 = (double)a1;\n while (1) {\n v4 = (double)v2;\n if (v3 < 0.0) {\n v5 = sqrt(v3);\n v4 = (double)v2;\n } else {\n v5 = sqrt(v3);\n }\n if (v5 < v4) break;\n if (!(a1 % v2)) {\n do {\n v6 = (a1 / v2) >> 31;\n a1 /= v2;\n } while (!(unsigned int)(__SPAIR64__(v6, a1) % v2));\n v1 = v2;\n v3 = (double)a1;\n }\n v2 += 2;\n }\n if (a1 <= 2) return v1;\n return (unsigned int)a1;\n}" + }, + { + "index": 32, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int maxPrime = -1;\n while (n % 2 == 0) {\n maxPrime = 2;\n n >>= 1;\n }\n for (int i = 3; i <= sqrt(n); i += 2) {\n while (n % i == 0) {\n maxPrime = i;\n n = n / i;\n }\n }\n if (n > 2) {\n maxPrime = n;\n }\n return maxPrime;\n}", + "test": "int main() {\n\n assert(func0(15) == 5);\n\n assert(func0(6) == 3);\n\n assert(func0(2) == 2);\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbx\nsub $0x28,%rsp\ntest $0x1,%dil\njne 12e2 \nnopl (%rax)\nsar %edi\ntest $0x1,%dil\nje 1258 \nmov $0x2,%r12d\npxor %xmm1,%xmm1\nmov $0x3,%ebx\npxor %xmm4,%xmm4\ncvtsi2sd %edi,%xmm1\nnopw 0x0(%rax,%rax,1)\nucomisd %xmm1,%xmm4\npxor %xmm2,%xmm2\nmovapd %xmm1,%xmm3\ncvtsi2sd %ebx,%xmm2\nsqrtsd %xmm3,%xmm3\nja 12ed \ncomisd %xmm2,%xmm3\njb 12d0 \nmov %edi,%eax\ncltd\nidiv %ebx\ntest %edx,%edx\njne 12c1 \nnopl (%rax)\nmov %edi,%eax\ncltd\nidiv %ebx\ncltd\nmov %eax,%edi\nidiv %ebx\ntest %edx,%edx\nje 12a8 \npxor %xmm1,%xmm1\nmov %ebx,%r12d\ncvtsi2sd %edi,%xmm1\nadd $0x2,%ebx\njmp 1280 \nnopw %cs:0x0(%rax,%rax,1)\ncmp $0x3,%edi\ncmovge %edi,%r12d\nadd $0x28,%rsp\npop %rbx\nmov %r12d,%eax\npop %r12\nretq\nmov $0xffffffff,%r12d\njmpq 1266 \nmovapd %xmm1,%xmm0\nmov %edi,0x1c(%rsp)\nmovsd %xmm3,0x10(%rsp)\nmovsd %xmm2,0x8(%rsp)\nmovsd %xmm1,(%rsp)\ncallq 1090 \nmov 0x1c(%rsp),%edi\nmovsd 0x10(%rsp),%xmm3\npxor %xmm4,%xmm4\nmovsd 0x8(%rsp),%xmm2\nmovsd (%rsp),%xmm1\njmpq 1296 \nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 28h\ntest dil, 1\njnz short loc_12C7\nloc_1250:\nsar edi, 1\ntest dil, 1\njz short loc_1250\nmov ebp, 2\nloc_125D:\npxor xmm1, xmm1\nmov ebx, 3\npxor xmm3, xmm3\ncvtsi2sd xmm1, edi\nxchg ax, ax\nloc_1270:\nucomisd xmm3, xmm1\npxor xmm2, xmm2\ncvtsi2sd xmm2, ebx\nja short loc_12CE\nmovapd xmm0, xmm1\nsqrtsd xmm0, xmm0\nloc_1286:\ncomisd xmm0, xmm2\njb short loc_12B8\nmov eax, edi\ncdq\nidiv ebx\ntest edx, edx\njnz short loc_12B0\nnop dword ptr [rax]\nloc_1298:\nmov eax, edi\ncdq\nidiv ebx\ncdq\nmov edi, eax\nidiv ebx\ntest edx, edx\njz short loc_1298\npxor xmm1, xmm1\nmov ebp, ebx\ncvtsi2sd xmm1, edi\nloc_12B0:\nadd ebx, 2\njmp short loc_1270\nloc_12B8:\ncmp edi, 2\ncmovle edi, ebp\nadd rsp, 28h\npop rbx\npop rbp\nmov eax, edi\nretn\nloc_12C7:\nmov ebp, 0FFFFFFFFh\njmp short loc_125D\nloc_12CE:\nmovapd xmm0, xmm1; x\nmov [rsp+38h+var_1C], edi\nmovsd [rsp+38h+var_28], xmm2\nmovsd [rsp+38h+var_30], xmm1\ncall _sqrt\nmov edi, [rsp+38h+var_1C]\nmovsd xmm2, [rsp+38h+var_28]\npxor xmm3, xmm3\nmovsd xmm1, [rsp+38h+var_30]\njmp short loc_1286", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v1; // ebp\n int v2; // ebx\n double v3; // xmm1_8\n double v4; // xmm2_8\n double v5; // xmm0_8\n int v6; // edx\n\n if ( (a1 & 1) != 0 )\n {\n v1 = -1;\n }\n else\n {\n do\n a1 >>= 1;\n while ( (a1 & 1) == 0 );\n v1 = 2;\n }\n v2 = 3;\n v3 = (double)a1;\n while ( 1 )\n {\n v4 = (double)v2;\n if ( v3 < 0.0 )\n {\n v5 = sqrt(v3);\n v4 = (double)v2;\n }\n else\n {\n v5 = sqrt(v3);\n }\n if ( v5 < v4 )\n break;\n if ( !(a1 % v2) )\n {\n do\n {\n v6 = (a1 / v2) >> 31;\n a1 /= v2;\n }\n while ( !(unsigned int)(__SPAIR64__(v6, a1) % v2) );\n v1 = v2;\n v3 = (double)a1;\n }\n v2 += 2;\n }\n if ( a1 <= 2 )\n return v1;\n return (unsigned int)a1;\n}", + "ida_strip_asm": "sub_1240:\nendbr64\npush rbp\npush rbx\nsub rsp, 28h\ntest dil, 1\njnz short loc_12C7\nloc_1250:\nsar edi, 1\ntest dil, 1\njz short loc_1250\nmov ebp, 2\nloc_125D:\npxor xmm1, xmm1\nmov ebx, 3\npxor xmm3, xmm3\ncvtsi2sd xmm1, edi\nxchg ax, ax\nloc_1270:\nucomisd xmm3, xmm1\npxor xmm2, xmm2\ncvtsi2sd xmm2, ebx\nja short loc_12CE\nmovapd xmm0, xmm1\nsqrtsd xmm0, xmm0\nloc_1286:\ncomisd xmm0, xmm2\njb short loc_12B8\nmov eax, edi\ncdq\nidiv ebx\ntest edx, edx\njnz short loc_12B0\nnop dword ptr [rax]\nloc_1298:\nmov eax, edi\ncdq\nidiv ebx\ncdq\nmov edi, eax\nidiv ebx\ntest edx, edx\njz short loc_1298\npxor xmm1, xmm1\nmov ebp, ebx\ncvtsi2sd xmm1, edi\nloc_12B0:\nadd ebx, 2\njmp short loc_1270\nloc_12B8:\ncmp edi, 2\ncmovle edi, ebp\nadd rsp, 28h\npop rbx\npop rbp\nmov eax, edi\nretn\nloc_12C7:\nmov ebp, 0FFFFFFFFh\njmp short loc_125D\nloc_12CE:\nmovapd xmm0, xmm1; x\nmov [rsp+38h+var_1C], edi\nmovsd [rsp+38h+var_28], xmm2\nmovsd [rsp+38h+var_30], xmm1\ncall _sqrt\nmov edi, [rsp+38h+var_1C]\nmovsd xmm2, [rsp+38h+var_28]\npxor xmm3, xmm3\nmovsd xmm1, [rsp+38h+var_30]\njmp short loc_1286", + "ida_strip_pseudo": "__int64 __fastcall sub_1240(int a1)\n{\n unsigned int v1; // ebp\n int v2; // ebx\n double v3; // xmm1_8\n double v4; // xmm2_8\n double v5; // xmm0_8\n int v6; // edx\n\n if ( (a1 & 1) != 0 )\n {\n v1 = -1;\n }\n else\n {\n do\n a1 >>= 1;\n while ( (a1 & 1) == 0 );\n v1 = 2;\n }\n v2 = 3;\n v3 = (double)a1;\n while ( 1 )\n {\n v4 = (double)v2;\n if ( v3 < 0.0 )\n {\n v5 = sqrt(v3);\n v4 = (double)v2;\n }\n else\n {\n v5 = sqrt(v3);\n }\n if ( v5 < v4 )\n break;\n if ( !(a1 % v2) )\n {\n do\n {\n v6 = (a1 / v2) >> 31;\n a1 /= v2;\n }\n while ( !(unsigned int)(__SPAIR64__(v6, a1) % v2) );\n v1 = v2;\n v3 = (double)a1;\n }\n v2 += 2;\n }\n if ( a1 <= 2 )\n return v1;\n return (unsigned int)a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1240(int a1) {\n unsigned int v1;\n int v2;\n double v3;\n double v4;\n double v5;\n int v6;\n if ((a1 & 1) != 0) {\n v1 = -1;\n } else {\n do\n a1 >>= 1;\n while ((a1 & 1) == 0);\n v1 = 2;\n }\n v2 = 3;\n v3 = (double)a1;\n while (1) {\n v4 = (double)v2;\n if (v3 < 0.0) {\n v5 = sqrt(v3);\n v4 = (double)v2;\n } else {\n v5 = sqrt(v3);\n }\n if (v5 < v4) break;\n if (!(a1 % v2)) {\n do {\n v6 = (a1 / v2) >> 31;\n a1 /= v2;\n } while (!(unsigned int)(__SPAIR64__(v6, a1) % v2));\n v1 = v2;\n v3 = (double)a1;\n }\n v2 += 2;\n }\n if (a1 <= 2) return v1;\n return (unsigned int)a1;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v1;\n int v2;\n double v3;\n double v4;\n double v5;\n int v6;\n if ((a1 & 1) != 0) {\n v1 = -1;\n } else {\n do\n a1 >>= 1;\n while ((a1 & 1) == 0);\n v1 = 2;\n }\n v2 = 3;\n v3 = (double)a1;\n while (1) {\n v4 = (double)v2;\n if (v3 < 0.0) {\n v5 = sqrt(v3);\n v4 = (double)v2;\n } else {\n v5 = sqrt(v3);\n }\n if (v5 < v4) break;\n if (!(a1 % v2)) {\n do {\n v6 = (a1 / v2) >> 31;\n a1 /= v2;\n } while (!(unsigned int)(__SPAIR64__(v6, a1) % v2));\n v1 = v2;\n v3 = (double)a1;\n }\n v2 += 2;\n }\n if (a1 <= 2) return v1;\n return (unsigned int)a1;\n}" + }, + { + "index": 33, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int N) {\n int B_Number = 0;\n int cnt = 0;\n while (N != 0) {\n int rem = N % 2;\n int c = 1;\n for (int i = 0; i < cnt; i++) {\n c *= 10;\n }\n B_Number += rem * c;\n N /= 2;\n cnt++;\n }\n return B_Number;\n}", + "test": "int main() {\n\n assert(func0(10) == 1010);\n\n assert(func0(1) == 1);\n\n assert(func0(20) == 10100);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x24(%rbp)\nmovl $0x0,-0x14(%rbp)\nmovl $0x0,-0x10(%rbp)\njmp 11bd \nmov -0x24(%rbp),%eax\ncltd\nshr $0x1f,%edx\nadd %edx,%eax\nand $0x1,%eax\nsub %edx,%eax\nmov %eax,-0x4(%rbp)\nmovl $0x1,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 1198 \nmov -0xc(%rbp),%edx\nmov %edx,%eax\nshl $0x2,%eax\nadd %edx,%eax\nadd %eax,%eax\nmov %eax,-0xc(%rbp)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x10(%rbp),%eax\njl 1185 \nmov -0x4(%rbp),%eax\nimul -0xc(%rbp),%eax\nadd %eax,-0x14(%rbp)\nmov -0x24(%rbp),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nmov %eax,-0x24(%rbp)\naddl $0x1,-0x10(%rbp)\ncmpl $0x0,-0x24(%rbp)\njne 1164 \nmov -0x14(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_24], edi\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\njmp short loc_11C1\nloc_1164:\nmov edx, [rbp+var_24]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov [rbp+var_4], edx\nmov [rbp+var_C], 1\nmov [rbp+var_8], 0\njmp short loc_119C\nloc_1189:\nmov edx, [rbp+var_C]\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nmov [rbp+var_C], eax\nadd [rbp+var_8], 1\nloc_119C:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_10]\njl short loc_1189\nmov eax, [rbp+var_4]\nimul eax, [rbp+var_C]\nadd [rbp+var_14], eax\nmov eax, [rbp+var_24]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_24], eax\nadd [rbp+var_10], 1\nloc_11C1:\ncmp [rbp+var_24], 0\njnz short loc_1164\nmov eax, [rbp+var_14]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v3; // [rsp+10h] [rbp-14h]\n int v4; // [rsp+14h] [rbp-10h]\n int v5; // [rsp+18h] [rbp-Ch]\n int i; // [rsp+1Ch] [rbp-8h]\n\n v3 = 0;\n v4 = 0;\n while ( a1 )\n {\n v5 = 1;\n for ( i = 0; i < v4; ++i )\n v5 *= 10;\n v3 += v5 * (a1 % 2);\n a1 /= 2;\n ++v4;\n }\n return v3;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_24], edi\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\njmp short loc_11C1\nloc_1164:\nmov edx, [rbp+var_24]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov [rbp+var_4], edx\nmov [rbp+var_C], 1\nmov [rbp+var_8], 0\njmp short loc_119C\nloc_1189:\nmov edx, [rbp+var_C]\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nmov [rbp+var_C], eax\nadd [rbp+var_8], 1\nloc_119C:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_10]\njl short loc_1189\nmov eax, [rbp+var_4]\nimul eax, [rbp+var_C]\nadd [rbp+var_14], eax\nmov eax, [rbp+var_24]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_24], eax\nadd [rbp+var_10], 1\nloc_11C1:\ncmp [rbp+var_24], 0\njnz short loc_1164\nmov eax, [rbp+var_14]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n unsigned int v3; // [rsp+10h] [rbp-14h]\n int v4; // [rsp+14h] [rbp-10h]\n int v5; // [rsp+18h] [rbp-Ch]\n int i; // [rsp+1Ch] [rbp-8h]\n\n v3 = 0;\n v4 = 0;\n while ( a1 )\n {\n v5 = 1;\n for ( i = 0; i < v4; ++i )\n v5 *= 10;\n v3 += v5 * (a1 % 2);\n a1 /= 2;\n ++v4;\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n unsigned int v3;\n int v4;\n int v5;\n int i;\n v3 = 0;\n v4 = 0;\n while (a1) {\n v5 = 1;\n for (i = 0; i < v4; ++i) v5 *= 10;\n v3 += v5 * (a1 % 2);\n a1 /= 2;\n ++v4;\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v3;\n int v4;\n int v5;\n int i;\n v3 = 0;\n v4 = 0;\n while (a1) {\n v5 = 1;\n for (i = 0; i < v4; ++i) v5 *= 10;\n v3 += v5 * (a1 % 2);\n a1 /= 2;\n ++v4;\n }\n return v3;\n}" + }, + { + "index": 33, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int N) {\n int B_Number = 0;\n int cnt = 0;\n while (N != 0) {\n int rem = N % 2;\n int c = 1;\n for (int i = 0; i < cnt; i++) {\n c *= 10;\n }\n B_Number += rem * c;\n N /= 2;\n cnt++;\n }\n return B_Number;\n}", + "test": "int main() {\n\n assert(func0(10) == 1010);\n\n assert(func0(1) == 1);\n\n assert(func0(20) == 10100);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %edi,%r8d\nmov %edi,%r9d\ntest %edi,%edi\nje 11ca \nmov %edi,%edx\nshr $0x1f,%edx\nlea (%rdi,%rdx,1),%eax\nand $0x1,%eax\nsub %edx,%eax\nmov %eax,%edi\nmov $0x0,%esi\nmov $0x0,%r9d\nmov $0x1,%eax\nmov $0x1,%r10d\njmp 1184 \nmov %r10d,%eax\nmov %r11d,%esi\nimul %edi,%eax\nadd %eax,%r9d\nmov %r8d,%edi\nshr $0x1f,%edi\nadd %r8d,%edi\nsar %edi\nmov %edi,%r8d\nlea 0x1(%rsi),%r11d\nje 11ca \nmov %edi,%edx\nshr $0x1f,%edx\nlea (%rdi,%rdx,1),%eax\nand $0x1,%eax\nsub %edx,%eax\nmov %eax,%edi\ntest %r11d,%r11d\njle 117e \nmov $0x0,%edx\nmov %r10d,%eax\nlea (%rax,%rax,4),%eax\nadd %eax,%eax\nmov %edx,%ecx\nadd $0x1,%edx\ncmp %ecx,%esi\njne 11ba \njmp 1181 \nmov %r9d,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njz short loc_11AA\nmov ecx, 0\nmov r8d, 0\nmov r9d, 1\nloc_1162:\nmov edx, edi\nshr edx, 1Fh\nlea eax, [rdi+rdx]\nand eax, 1\nsub eax, edx\nmov esi, eax\ntest ecx, ecx\njle short loc_11A5\nmov edx, 0\nmov eax, r9d\nloc_117D:\nlea eax, [rax+rax*4]\nadd eax, eax\nadd edx, 1\ncmp edx, ecx\njnz short loc_117D\nloc_1189:\nimul eax, esi\nadd r8d, eax\nmov eax, edi\nshr eax, 1Fh\nadd eax, edi\nsar eax, 1\nmov edi, eax\nadd ecx, 1\ntest eax, eax\njnz short loc_1162\nloc_11A1:\nmov eax, r8d\nretn\nloc_11A5:\nmov eax, r9d\njmp short loc_1189\nloc_11AA:\nmov r8d, edi\njmp short loc_11A1", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // ecx\n unsigned int v2; // r8d\n int v3; // edx\n int v4; // eax\n\n if ( a1 )\n {\n v1 = 0;\n v2 = 0;\n do\n {\n if ( v1 <= 0 )\n {\n v4 = 1;\n }\n else\n {\n v3 = 0;\n v4 = 1;\n do\n {\n v4 *= 10;\n ++v3;\n }\n while ( v3 != v1 );\n }\n v2 += a1 % 2 * v4;\n a1 /= 2;\n ++v1;\n }\n while ( a1 );\n }\n else\n {\n return 0;\n }\n return v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ntest edi, edi\njz short loc_11AA\nmov ecx, 0\nmov r8d, 0\nmov r9d, 1\nloc_1162:\nmov edx, edi\nshr edx, 1Fh\nlea eax, [rdi+rdx]\nand eax, 1\nsub eax, edx\nmov esi, eax\ntest ecx, ecx\njle short loc_11A5\nmov edx, 0\nmov eax, r9d\nloc_117D:\nlea eax, [rax+rax*4]\nadd eax, eax\nadd edx, 1\ncmp edx, ecx\njnz short loc_117D\nloc_1189:\nimul eax, esi\nadd r8d, eax\nmov eax, edi\nshr eax, 1Fh\nadd eax, edi\nsar eax, 1\nmov edi, eax\nadd ecx, 1\ntest eax, eax\njnz short loc_1162\nloc_11A1:\nmov eax, r8d\nretn\nloc_11A5:\nmov eax, r9d\njmp short loc_1189\nloc_11AA:\nmov r8d, edi\njmp short loc_11A1", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v1; // ecx\n unsigned int v2; // r8d\n int v3; // edx\n int v4; // eax\n\n if ( a1 )\n {\n v1 = 0;\n v2 = 0;\n do\n {\n if ( v1 <= 0 )\n {\n v4 = 1;\n }\n else\n {\n v3 = 0;\n v4 = 1;\n do\n {\n v4 *= 10;\n ++v3;\n }\n while ( v3 != v1 );\n }\n v2 += a1 % 2 * v4;\n a1 /= 2;\n ++v1;\n }\n while ( a1 );\n }\n else\n {\n return 0;\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v1;\n unsigned int v2;\n int v3;\n int v4;\n if (a1) {\n v1 = 0;\n v2 = 0;\n do {\n if (v1 <= 0) {\n v4 = 1;\n } else {\n v3 = 0;\n v4 = 1;\n do {\n v4 *= 10;\n ++v3;\n } while (v3 != v1);\n }\n v2 += a1 % 2 * v4;\n a1 /= 2;\n ++v1;\n } while (a1);\n } else {\n return 0;\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n unsigned int v2;\n int v3;\n int v4;\n if (a1) {\n v1 = 0;\n v2 = 0;\n do {\n if (v1 <= 0) {\n v4 = 1;\n } else {\n v3 = 0;\n v4 = 1;\n do {\n v4 *= 10;\n ++v3;\n } while (v3 != v1);\n }\n v2 += a1 % 2 * v4;\n a1 /= 2;\n ++v1;\n } while (a1);\n } else {\n return 0;\n }\n return v2;\n}" + }, + { + "index": 33, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int N) {\n int B_Number = 0;\n int cnt = 0;\n while (N != 0) {\n int rem = N % 2;\n int c = 1;\n for (int i = 0; i < cnt; i++) {\n c *= 10;\n }\n B_Number += rem * c;\n N /= 2;\n cnt++;\n }\n return B_Number;\n}", + "test": "int main() {\n\n assert(func0(10) == 1010);\n\n assert(func0(1) == 1);\n\n assert(func0(20) == 10100);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nxor %r10d,%r10d\ntest %edi,%edi\nje 12f0 \nmov %edi,%edx\nxor %r9d,%r9d\nxor %r10d,%r10d\nshr $0x1f,%edx\nlea (%rdi,%rdx,1),%eax\nand $0x1,%eax\nsub %edx,%eax\nmov %eax,%r8d\nmov $0x1,%eax\nnopw %cs:0x0(%rax,%rax,1)\nimul %r8d,%eax\nmov %r9d,%esi\nadd $0x1,%r9d\nadd %eax,%r10d\nmov %edi,%eax\nshr $0x1f,%eax\nadd %edi,%eax\nmov %eax,%edi\nsar %edi\nje 12f0 \nshr $0x1f,%eax\nxor %edx,%edx\nlea (%rdi,%rax,1),%r8d\nand $0x1,%r8d\nsub %eax,%r8d\nmov $0x1,%eax\nlea (%rax,%rax,4),%eax\nmov %edx,%ecx\nadd $0x1,%edx\nadd %eax,%eax\ncmp %ecx,%esi\njne 12e0 \njmp 12b0 \nmov %r10d,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\nmov r8d, edi\ntest edi, edi\njz short loc_1256\nmov edx, edi\nxor esi, esi\nxor r9d, r9d\nshr edx, 1Fh\nlea eax, [rdi+rdx]\nand eax, 1\nsub eax, edx\nnop dword ptr [rax]\nloc_1210:\nadd r9d, eax\nmov eax, r8d\nlea r10d, [rsi+1]\nshr eax, 1Fh\nadd eax, r8d\nmov r8d, eax\nsar r8d, 1\njz short loc_1259\nshr eax, 1Fh\nxor edx, edx\nlea edi, [r8+rax]\nand edi, 1\nsub edi, eax\nmov eax, 1\nnop dword ptr [rax+rax+00h]\nloc_1240:\nlea eax, [rax+rax*4]\nmov ecx, edx\nadd edx, 1\nadd eax, eax\ncmp esi, ecx\njnz short loc_1240\nimul eax, edi\nmov esi, r10d\njmp short loc_1210\nloc_1256:\nxor r9d, r9d\nloc_1259:\nmov eax, r9d\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v1; // r8d\n int v2; // esi\n unsigned int v3; // r9d\n int v4; // eax\n int v5; // eax\n int v6; // edx\n int v7; // edi\n int v8; // eax\n int v9; // ecx\n\n v1 = a1;\n if ( a1 )\n {\n v2 = 0;\n v3 = 0;\n v4 = a1 % 2;\n while ( 1 )\n {\n v3 += v4;\n v5 = v1 + (v1 >> 31);\n v1 = (int)v1 / 2;\n if ( !v1 )\n break;\n v6 = 0;\n v7 = (((_BYTE)v1 + (v5 < 0)) & 1) - ((unsigned int)v5 >> 31);\n v8 = 1;\n do\n {\n v9 = v6++;\n v8 *= 10;\n }\n while ( v2 != v9 );\n v4 = v7 * v8;\n ++v2;\n }\n }\n else\n {\n return 0;\n }\n return v3;\n}", + "ida_strip_asm": "sub_11F0:\nendbr64\nmov r8d, edi\ntest edi, edi\njz short loc_1256\nmov edx, edi\nxor esi, esi\nxor r9d, r9d\nshr edx, 1Fh\nlea eax, [rdi+rdx]\nand eax, 1\nsub eax, edx\nnop dword ptr [rax]\nloc_1210:\nadd r9d, eax\nmov eax, r8d\nlea r10d, [rsi+1]\nshr eax, 1Fh\nadd eax, r8d\nmov r8d, eax\nsar r8d, 1\njz short loc_1259\nshr eax, 1Fh\nxor edx, edx\nlea edi, [r8+rax]\nand edi, 1\nsub edi, eax\nmov eax, 1\nnop dword ptr [rax+rax+00h]\nloc_1240:\nlea eax, [rax+rax*4]\nmov ecx, edx\nadd edx, 1\nadd eax, eax\ncmp esi, ecx\njnz short loc_1240\nimul eax, edi\nmov esi, r10d\njmp short loc_1210\nloc_1256:\nxor r9d, r9d\nloc_1259:\nmov eax, r9d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11F0(int a1)\n{\n unsigned int v1; // r8d\n int v2; // esi\n unsigned int v3; // r9d\n int v4; // eax\n int v5; // eax\n int v6; // edx\n int v7; // edi\n int v8; // eax\n int v9; // ecx\n\n v1 = a1;\n if ( a1 )\n {\n v2 = 0;\n v3 = 0;\n v4 = a1 % 2;\n while ( 1 )\n {\n v3 += v4;\n v5 = v1 + (v1 >> 31);\n v1 = (int)v1 / 2;\n if ( !v1 )\n break;\n v6 = 0;\n v7 = (((_BYTE)v1 + (v5 < 0)) & 1) - ((unsigned int)v5 >> 31);\n v8 = 1;\n do\n {\n v9 = v6++;\n v8 *= 10;\n }\n while ( v2 != v9 );\n v4 = v7 * v8;\n ++v2;\n }\n }\n else\n {\n return 0;\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11F0(int a1) {\n unsigned int v1;\n int v2;\n unsigned int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n int v8;\n int v9;\n v1 = a1;\n if (a1) {\n v2 = 0;\n v3 = 0;\n v4 = a1 % 2;\n while (1) {\n v3 += v4;\n v5 = v1 + (v1 >> 31);\n v1 = (int)v1 / 2;\n if (!v1) break;\n v6 = 0;\n v7 = (((uint8_t)v1 + (v5 < 0)) & 1) - ((unsigned int)v5 >> 31);\n v8 = 1;\n do {\n v9 = v6++;\n v8 *= 10;\n } while (v2 != v9);\n v4 = v7 * v8;\n ++v2;\n }\n } else {\n return 0;\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v1;\n int v2;\n unsigned int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n int v8;\n int v9;\n v1 = a1;\n if (a1) {\n v2 = 0;\n v3 = 0;\n v4 = a1 % 2;\n while (1) {\n v3 += v4;\n v5 = v1 + (v1 >> 31);\n v1 = (int)v1 / 2;\n if (!v1) break;\n v6 = 0;\n v7 = (((uint8_t)v1 + (v5 < 0)) & 1) - ((unsigned int)v5 >> 31);\n v8 = 1;\n do {\n v9 = v6++;\n v8 *= 10;\n } while (v2 != v9);\n v4 = v7 * v8;\n ++v2;\n }\n } else {\n return 0;\n }\n return v3;\n}" + }, + { + "index": 34, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int ar[], int N) {\n int l = 0;\n int r = N - 1;\n while (l <= r) {\n int mid = (l + r) / 2;\n if (ar[mid] != mid + 1 && ar[mid - 1] == mid) {\n return mid + 1;\n } else if (ar[mid] != mid + 1) {\n r = mid - 1;\n } else {\n l = mid + 1;\n }\n }\n return -1;\n}", + "test": "int main() {\n\n int ar1[] = {1, 2, 3, 5};\n\n assert(func0(ar1, 4) == 4);\n\n\n\n int ar2[] = {1, 3, 4, 5};\n\n assert(func0(ar2, 4) == 2);\n\n\n\n int ar3[] = {1, 2, 3, 5, 6, 7};\n\n assert(func0(ar3, 6) == 4);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0xc(%rbp)\nmov -0x1c(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0x8(%rbp)\njmpq 1218 \nmov -0xc(%rbp),%edx\nmov -0x8(%rbp),%eax\nadd %edx,%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov -0x4(%rbp),%edx\nadd $0x1,%edx\ncmp %edx,%eax\nje 11e4 \nmov -0x4(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x4(%rbp)\njne 11e4 \nmov -0x4(%rbp),%eax\nadd $0x1,%eax\njmp 1229 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov -0x4(%rbp),%edx\nadd $0x1,%edx\ncmp %edx,%eax\nje 120f \nmov -0x4(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0x8(%rbp)\njmp 1218 \nmov -0x4(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x8(%rbp),%eax\njle 118d \nmov $0xffffffff,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0\nmov eax, [rbp+var_1C]\nsub eax, 1\nmov [rbp+var_8], eax\njmp loc_1218\nloc_118D:\nmov edx, [rbp+var_C]\nmov eax, [rbp+var_8]\nadd eax, edx\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\nadd eax, 1\ncmp edx, eax\njz short loc_11E4\nmov eax, [rbp+var_4]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_4], eax\njnz short loc_11E4\nmov eax, [rbp+var_4]\nadd eax, 1\njmp short loc_1229\nloc_11E4:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\nadd eax, 1\ncmp edx, eax\njz short loc_120F\nmov eax, [rbp+var_4]\nsub eax, 1\nmov [rbp+var_8], eax\njmp short loc_1218\nloc_120F:\nmov eax, [rbp+var_4]\nadd eax, 1\nmov [rbp+var_C], eax\nloc_1218:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_8]\njle loc_118D\nmov eax, 0FFFFFFFFh\nloc_1229:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int v3; // [rsp+10h] [rbp-Ch]\n int v4; // [rsp+14h] [rbp-8h]\n int v5; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n v4 = a2 - 1;\n while ( v3 <= v4 )\n {\n v5 = (v3 + v4) / 2;\n if ( *(_DWORD *)(4LL * v5 + a1) != v5 + 1 && v5 == *(_DWORD *)(4LL * v5 - 4 + a1) )\n return (unsigned int)(v5 + 1);\n if ( *(_DWORD *)(4LL * v5 + a1) == v5 + 1 )\n v3 = v5 + 1;\n else\n v4 = v5 - 1;\n }\n return 0xFFFFFFFFLL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0\nmov eax, [rbp+var_1C]\nsub eax, 1\nmov [rbp+var_8], eax\njmp loc_1218\nloc_118D:\nmov edx, [rbp+var_C]\nmov eax, [rbp+var_8]\nadd eax, edx\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\nadd eax, 1\ncmp edx, eax\njz short loc_11E4\nmov eax, [rbp+var_4]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_4], eax\njnz short loc_11E4\nmov eax, [rbp+var_4]\nadd eax, 1\njmp short loc_1229\nloc_11E4:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\nadd eax, 1\ncmp edx, eax\njz short loc_120F\nmov eax, [rbp+var_4]\nsub eax, 1\nmov [rbp+var_8], eax\njmp short loc_1218\nloc_120F:\nmov eax, [rbp+var_4]\nadd eax, 1\nmov [rbp+var_C], eax\nloc_1218:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_8]\njle loc_118D\nmov eax, 0FFFFFFFFh\nloc_1229:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int v3; // [rsp+10h] [rbp-Ch]\n int v4; // [rsp+14h] [rbp-8h]\n int v5; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n v4 = a2 - 1;\n while ( v3 <= v4 )\n {\n v5 = (v3 + v4) / 2;\n if ( *(_DWORD *)(4LL * v5 + a1) != v5 + 1 && v5 == *(_DWORD *)(4LL * v5 - 4 + a1) )\n return (unsigned int)(v5 + 1);\n if ( *(_DWORD *)(4LL * v5 + a1) == v5 + 1 )\n v3 = v5 + 1;\n else\n v4 = v5 - 1;\n }\n return 0xFFFFFFFFLL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int v3;\n int v4;\n int v5;\n v3 = 0;\n v4 = a2 - 1;\n while (v3 <= v4) {\n v5 = (v3 + v4) / 2;\n if (*(uint32_t *)(4LL * v5 + a1) != v5 + 1 &&\n v5 == *(uint32_t *)(4LL * v5 - 4 + a1))\n return (unsigned int)(v5 + 1);\n if (*(uint32_t *)(4LL * v5 + a1) == v5 + 1)\n v3 = v5 + 1;\n else\n v4 = v5 - 1;\n }\n return 4294967295LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int v3;\n int v4;\n int v5;\n v3 = 0;\n v4 = a2 - 1;\n while (v3 <= v4) {\n v5 = (v3 + v4) / 2;\n if (*(uint32_t *)(4LL * v5 + a1) != v5 + 1 &&\n v5 == *(uint32_t *)(4LL * v5 - 4 + a1))\n return (unsigned int)(v5 + 1);\n if (*(uint32_t *)(4LL * v5 + a1) == v5 + 1)\n v3 = v5 + 1;\n else\n v4 = v5 - 1;\n }\n return 4294967295LL;\n}" + }, + { + "index": 34, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int ar[], int N) {\n int l = 0;\n int r = N - 1;\n while (l <= r) {\n int mid = (l + r) / 2;\n if (ar[mid] != mid + 1 && ar[mid - 1] == mid) {\n return mid + 1;\n } else if (ar[mid] != mid + 1) {\n r = mid - 1;\n } else {\n l = mid + 1;\n }\n }\n return -1;\n}", + "test": "int main() {\n\n int ar1[] = {1, 2, 3, 5};\n\n assert(func0(ar1, 4) == 4);\n\n\n\n int ar2[] = {1, 3, 4, 5};\n\n assert(func0(ar2, 4) == 2);\n\n\n\n int ar3[] = {1, 2, 3, 5, 6, 7};\n\n assert(func0(ar3, 6) == 4);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x1,%esi\nmov $0x0,%ecx\njmp 1179 \nmov %eax,%ecx\ncmp %ecx,%esi\njl 11ac \nlea (%rsi,%rcx,1),%edx\nmov %edx,%eax\nshr $0x1f,%eax\nadd %edx,%eax\nsar %eax\nmov %eax,%r8d\nmovslq %eax,%rdx\nlea 0x0(,%rdx,4),%r9\nadd $0x1,%eax\ncmp %eax,(%rdi,%rdx,4)\nje 1177 \ncmp %r8d,-0x4(%rdi,%r9,1)\nje 11b1 \nlea -0x1(%r8),%esi\njmp 1179 \nmov $0xffffffff,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nsub esi, 1\nmov ecx, 0\njmp short loc_117A\nloc_1177:\nmov ecx, r8d\nloc_117A:\ncmp esi, ecx\njl short loc_11AB\nlea edx, [rsi+rcx]\nmov eax, edx\nshr eax, 1Fh\nadd eax, edx\nsar eax, 1\nmovsxd rdx, eax\nlea r9, ds:0[rdx*4]\nlea r8d, [rax+1]\ncmp [rdi+rdx*4], r8d\njz short loc_1177\ncmp [rdi+r9-4], eax\njz short loc_11B1\nlea esi, [rax-1]\njmp short loc_117A\nloc_11AB:\nmov r8d, 0FFFFFFFFh\nloc_11B1:\nmov eax, r8d\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int v2; // esi\n int v3; // ecx\n int v4; // eax\n unsigned int v5; // r8d\n\n v2 = a2 - 1;\n v3 = 0;\n while ( v2 >= v3 )\n {\n v4 = (v2 + v3) / 2;\n v5 = v4 + 1;\n if ( *(_DWORD *)(a1 + 4LL * v4) == v4 + 1 )\n {\n v3 = v4 + 1;\n }\n else\n {\n if ( *(_DWORD *)(a1 + 4LL * v4 - 4) == v4 )\n return v5;\n v2 = v4 - 1;\n }\n }\n return (unsigned int)-1;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nsub esi, 1\nmov ecx, 0\njmp short loc_117A\nloc_1177:\nmov ecx, r8d\nloc_117A:\ncmp esi, ecx\njl short loc_11AB\nlea edx, [rsi+rcx]\nmov eax, edx\nshr eax, 1Fh\nadd eax, edx\nsar eax, 1\nmovsxd rdx, eax\nlea r9, ds:0[rdx*4]\nlea r8d, [rax+1]\ncmp [rdi+rdx*4], r8d\njz short loc_1177\ncmp [rdi+r9-4], eax\njz short loc_11B1\nlea esi, [rax-1]\njmp short loc_117A\nloc_11AB:\nmov r8d, 0FFFFFFFFh\nloc_11B1:\nmov eax, r8d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int v2; // esi\n int v3; // ecx\n int v4; // eax\n unsigned int v5; // r8d\n\n v2 = a2 - 1;\n v3 = 0;\n while ( v2 >= v3 )\n {\n v4 = (v2 + v3) / 2;\n v5 = v4 + 1;\n if ( *(_DWORD *)(a1 + 4LL * v4) == v4 + 1 )\n {\n v3 = v4 + 1;\n }\n else\n {\n if ( *(_DWORD *)(a1 + 4LL * v4 - 4) == v4 )\n return v5;\n v2 = v4 - 1;\n }\n }\n return (unsigned int)-1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int v2;\n int v3;\n int v4;\n unsigned int v5;\n v2 = a2 - 1;\n v3 = 0;\n while (v2 >= v3) {\n v4 = (v2 + v3) / 2;\n v5 = v4 + 1;\n if (*(uint32_t *)(a1 + 4LL * v4) == v4 + 1) {\n v3 = v4 + 1;\n } else {\n if (*(uint32_t *)(a1 + 4LL * v4 - 4) == v4) return v5;\n v2 = v4 - 1;\n }\n }\n return (unsigned int)-1;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int v2;\n int v3;\n int v4;\n unsigned int v5;\n v2 = a2 - 1;\n v3 = 0;\n while (v2 >= v3) {\n v4 = (v2 + v3) / 2;\n v5 = v4 + 1;\n if (*(uint32_t *)(a1 + 4LL * v4) == v4 + 1) {\n v3 = v4 + 1;\n } else {\n if (*(uint32_t *)(a1 + 4LL * v4 - 4) == v4) return v5;\n v2 = v4 - 1;\n }\n }\n return (unsigned int)-1;\n}" + }, + { + "index": 34, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int ar[], int N) {\n int l = 0;\n int r = N - 1;\n while (l <= r) {\n int mid = (l + r) / 2;\n if (ar[mid] != mid + 1 && ar[mid - 1] == mid) {\n return mid + 1;\n } else if (ar[mid] != mid + 1) {\n r = mid - 1;\n } else {\n l = mid + 1;\n }\n }\n return -1;\n}", + "test": "int main() {\n\n int ar1[] = {1, 2, 3, 5};\n\n assert(func0(ar1, 4) == 4);\n\n\n\n int ar2[] = {1, 3, 4, 5};\n\n assert(func0(ar2, 4) == 2);\n\n\n\n int ar3[] = {1, 2, 3, 5, 6, 7};\n\n assert(func0(ar3, 6) == 4);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x1,%esi\nxor %ecx,%ecx\nnopl 0x0(%rax)\ncmp %ecx,%esi\njl 1318 \nlea (%rsi,%rcx,1),%edx\nmov %edx,%eax\nshr $0x1f,%eax\nadd %edx,%eax\nsar %eax\nmovslq %eax,%rdx\nlea 0x1(%rax),%r8d\nlea 0x0(,%rdx,4),%r9\ncmp %r8d,(%rdi,%rdx,4)\nje 1328 \ncmp %eax,-0x4(%rdi,%r9,1)\nje 131e \nlea -0x1(%rax),%esi\ncmp %ecx,%esi\njge 12e4 \nnopl 0x0(%rax,%rax,1)\nmov $0xffffffff,%r8d\nmov %r8d,%eax\nretq\nnopw 0x0(%rax,%rax,1)\nmov %r8d,%ecx\njmp 12e0 \nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\nsub esi, 1\nxor ecx, ecx\nnop dword ptr [rax+00000000h]\nloc_1280:\ncmp esi, ecx\njl short loc_12B8\nloc_1284:\nlea edx, [rsi+rcx]\nmov eax, edx\nshr eax, 1Fh\nadd eax, edx\nsar eax, 1\nmovsxd rdx, eax\nlea r8d, [rax+1]\nlea r9, ds:0[rdx*4]\ncmp [rdi+rdx*4], r8d\njz short loc_12C8\ncmp [rdi+r9-4], eax\njz short loc_12BE\nlea esi, [rax-1]\ncmp esi, ecx\njge short loc_1284\nnop dword ptr [rax+rax+00h]\nloc_12B8:\nmov r8d, 0FFFFFFFFh\nloc_12BE:\nmov eax, r8d\nretn\nloc_12C8:\nmov ecx, r8d\njmp short loc_1280", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int v2; // esi\n int i; // ecx\n int v4; // eax\n unsigned int v5; // r8d\n\n v2 = a2 - 1;\n for ( i = 0; v2 >= i; i = v4 + 1 )\n {\n while ( 1 )\n {\n v4 = (v2 + i) / 2;\n v5 = v4 + 1;\n if ( *(_DWORD *)(a1 + 4LL * v4) == v4 + 1 )\n break;\n if ( *(_DWORD *)(a1 + 4LL * v4 - 4) == v4 )\n return v5;\n v2 = v4 - 1;\n if ( v4 - 1 < i )\n return (unsigned int)-1;\n }\n }\n return (unsigned int)-1;\n}", + "ida_strip_asm": "sub_1270:\nendbr64\nsub esi, 1\nxor ecx, ecx\nnop dword ptr [rax+00000000h]\nloc_1280:\ncmp esi, ecx\njl short loc_12B8\nloc_1284:\nlea edx, [rsi+rcx]\nmov eax, edx\nshr eax, 1Fh\nadd eax, edx\nsar eax, 1\nmovsxd rdx, eax\nlea r8d, [rax+1]\nlea r9, ds:0[rdx*4]\ncmp [rdi+rdx*4], r8d\njz short loc_12C8\ncmp [rdi+r9-4], eax\njz short loc_12BE\nlea esi, [rax-1]\ncmp esi, ecx\njge short loc_1284\nnop dword ptr [rax+rax+00h]\nloc_12B8:\nmov r8d, 0FFFFFFFFh\nloc_12BE:\nmov eax, r8d\nretn\nloc_12C8:\nmov ecx, r8d\njmp short loc_1280", + "ida_strip_pseudo": "__int64 __fastcall sub_1270(__int64 a1, int a2)\n{\n int v2; // esi\n int i; // ecx\n int v4; // eax\n unsigned int v5; // r8d\n\n v2 = a2 - 1;\n for ( i = 0; v2 >= i; i = v4 + 1 )\n {\n while ( 1 )\n {\n v4 = (v2 + i) / 2;\n v5 = v4 + 1;\n if ( *(_DWORD *)(a1 + 4LL * v4) == v4 + 1 )\n break;\n if ( *(_DWORD *)(a1 + 4LL * v4 - 4) == v4 )\n return v5;\n v2 = v4 - 1;\n if ( v4 - 1 < i )\n return (unsigned int)-1;\n }\n }\n return (unsigned int)-1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1270(long long a1, int a2) {\n int v2;\n int i;\n int v4;\n unsigned int v5;\n v2 = a2 - 1;\n for (i = 0; v2 >= i; i = v4 + 1) {\n while (1) {\n v4 = (v2 + i) / 2;\n v5 = v4 + 1;\n if (*(uint32_t *)(a1 + 4LL * v4) == v4 + 1) break;\n if (*(uint32_t *)(a1 + 4LL * v4 - 4) == v4) return v5;\n v2 = v4 - 1;\n if (v4 - 1 < i) return (unsigned int)-1;\n }\n }\n return (unsigned int)-1;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int v2;\n int i;\n int v4;\n unsigned int v5;\n v2 = a2 - 1;\n for (i = 0; v2 >= i; i = v4 + 1) {\n while (1) {\n v4 = (v2 + i) / 2;\n v5 = v4 + 1;\n if (*(uint32_t *)(a1 + 4LL * v4) == v4 + 1) break;\n if (*(uint32_t *)(a1 + 4LL * v4 - 4) == v4) return v5;\n v2 = v4 - 1;\n if (v4 - 1 < i) return (unsigned int)-1;\n }\n }\n return (unsigned int)-1;\n}" + }, + { + "index": 35, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) { return n * (n + 1); }", + "test": "int main() {\n\n assert(func0(4) == 20);\n\n assert(func0(5) == 30);\n\n assert(func0(6) == 42);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nadd $0x1,%eax\nimul -0x4(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov eax, [rbp+var_4]\nadd eax, 1\nimul eax, [rbp+var_4]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n return (unsigned int)(a1 * (a1 + 1));\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov eax, [rbp+var_4]\nadd eax, 1\nimul eax, [rbp+var_4]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n return (unsigned int)(a1 * (a1 + 1));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) { return (unsigned int)(a1 * (a1 + 1)); }", + "ida_pseudo_norm": "long long func0(int a1) { return (unsigned int)(a1 * (a1 + 1)); }" + }, + { + "index": 36, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int p, int q, int N) {\n int res;\n while (N > 0) {\n N--;\n p *= 10;\n res = p / q;\n p = p % q;\n }\n return res;\n}", + "test": "int main() {\n\n assert(func0(1, 2, 1) == 5);\n\n assert(func0(3, 5, 1) == 6);\n\n assert(func0(5, 6, 5) == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov %edx,-0x1c(%rbp)\njmp 1183 \nsubl $0x1,-0x1c(%rbp)\nmov -0x14(%rbp),%edx\nmov %edx,%eax\nshl $0x2,%eax\nadd %edx,%eax\nadd %eax,%eax\nmov %eax,-0x14(%rbp)\nmov -0x14(%rbp),%eax\ncltd\nidivl -0x18(%rbp)\nmov %eax,-0x4(%rbp)\nmov -0x14(%rbp),%eax\ncltd\nidivl -0x18(%rbp)\nmov %edx,-0x14(%rbp)\ncmpl $0x0,-0x1c(%rbp)\njg 115c \nmov -0x4(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\njmp short loc_1183\nloc_115C:\nsub [rbp+var_1C], 1\nmov edx, [rbp+var_14]\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nmov [rbp+var_14], eax\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_18]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_18]\nmov [rbp+var_14], edx\nloc_1183:\ncmp [rbp+var_1C], 0\njg short loc_115C\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, int a3)\n{\n int v6; // [rsp+8h] [rbp-14h]\n unsigned int v7; // [rsp+18h] [rbp-4h]\n\n while ( a3 > 0 )\n {\n --a3;\n v6 = 10 * a1;\n v7 = v6 / a2;\n a1 = v6 % a2;\n }\n return v7;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\njmp short loc_1183\nloc_115C:\nsub [rbp+var_1C], 1\nmov edx, [rbp+var_14]\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nmov [rbp+var_14], eax\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_18]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_18]\nmov [rbp+var_14], edx\nloc_1183:\ncmp [rbp+var_1C], 0\njg short loc_115C\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2, int a3)\n{\n int v6; // [rsp+8h] [rbp-14h]\n unsigned int v7; // [rsp+18h] [rbp-4h]\n\n while ( a3 > 0 )\n {\n --a3;\n v6 = 10 * a1;\n v7 = v6 / a2;\n a1 = v6 % a2;\n }\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2, int a3) {\n int v6;\n unsigned int v7;\n while (a3 > 0) {\n --a3;\n v6 = 10 * a1;\n v7 = v6 / a2;\n a1 = v6 % a2;\n }\n return v7;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, int a3) {\n int v6;\n unsigned int v7;\n while (a3 > 0) {\n --a3;\n v6 = 10 * a1;\n v7 = v6 / a2;\n a1 = v6 % a2;\n }\n return v7;\n}" + }, + { + "index": 36, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int p, int q, int N) {\n int res;\n while (N > 0) {\n N--;\n p *= 10;\n res = p / q;\n p = p % q;\n }\n return res;\n}", + "test": "int main() {\n\n assert(func0(1, 2, 1) == 5);\n\n assert(func0(3, 5, 1) == 6);\n\n assert(func0(5, 6, 5) == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %edx,%r8d\ntest %edx,%edx\njle 116c \nlea (%rdi,%rdi,4),%ecx\nadd %ecx,%ecx\nmov %ecx,%eax\ncltd\nidiv %esi\nmov %edx,%edi\nsub $0x1,%r8d\njne 1154 \nmov %ecx,%eax\ncltd\nidiv %esi\nretq\nmov $0x0,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov r8d, edx\ntest edx, edx\njle short loc_116C\nloc_1154:\nlea ecx, [rdi+rdi*4]\nadd ecx, ecx\nmov eax, ecx\ncdq\nidiv esi\nmov edi, edx\nsub r8d, 1\njnz short loc_1154\nmov eax, ecx\ncdq\nidiv esi\nretn\nloc_116C:\nmov eax, 0\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, int a3)\n{\n int v3; // r8d\n int v4; // ecx\n\n v3 = a3;\n if ( a3 <= 0 )\n return 0LL;\n do\n {\n v4 = 10 * a1;\n a1 = 10 * a1 % a2;\n --v3;\n }\n while ( v3 );\n return (unsigned int)(v4 / a2);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmov r8d, edx\ntest edx, edx\njle short loc_116C\nloc_1154:\nlea ecx, [rdi+rdi*4]\nadd ecx, ecx\nmov eax, ecx\ncdq\nidiv esi\nmov edi, edx\nsub r8d, 1\njnz short loc_1154\nmov eax, ecx\ncdq\nidiv esi\nretn\nloc_116C:\nmov eax, 0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2, int a3)\n{\n int v3; // r8d\n int v4; // ecx\n\n v3 = a3;\n if ( a3 <= 0 )\n return 0LL;\n do\n {\n v4 = 10 * a1;\n a1 = 10 * a1 % a2;\n --v3;\n }\n while ( v3 );\n return (unsigned int)(v4 / a2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2, int a3) {\n int v3;\n int v4;\n v3 = a3;\n if (a3 <= 0) return 0LL;\n do {\n v4 = 10 * a1;\n a1 = 10 * a1 % a2;\n --v3;\n } while (v3);\n return (unsigned int)(v4 / a2);\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, int a3) {\n int v3;\n int v4;\n v3 = a3;\n if (a3 <= 0) return 0LL;\n do {\n v4 = 10 * a1;\n a1 = 10 * a1 % a2;\n --v3;\n } while (v3);\n return (unsigned int)(v4 / a2);\n}" + }, + { + "index": 37, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef enum { INT_TYPE, STRING_TYPE } ElementType;\n\n\n\ntypedef struct {\n\n ElementType type;\n\n union {\n\n int i;\n\n char* s;\n\n } value;\n\n} Mixed;\n\n\n\nint compare_ints(const void* a, const void* b) {\n\n int int_a = ((Mixed*)a)->value.i;\n\n int int_b = ((Mixed*)b)->value.i;\n\n return (int_a > int_b) - (int_a < int_b);\n\n}\n\n\n\nint compare_strings(const void* a, const void* b) {\n\n char* str_a = ((Mixed*)a)->value.s;\n\n char* str_b = ((Mixed*)b)->value.s;\n\n return strcmp(str_a, str_b);\n\n}\n\n\n\n", + "func": "Mixed* func0(Mixed* mixed_list, size_t size, size_t* sorted_size) {\n size_t int_count = 0, str_count = 0;\n for (size_t i = 0; i < size; i++) {\n if (mixed_list[i].type == INT_TYPE)\n int_count++;\n else\n str_count++;\n }\n Mixed* int_part = malloc(int_count * sizeof(Mixed));\n Mixed* str_part = malloc(str_count * sizeof(Mixed));\n size_t int_idx = 0, str_idx = 0;\n for (size_t i = 0; i < size; i++) {\n if (mixed_list[i].type == INT_TYPE) {\n int_part[int_idx++] = mixed_list[i];\n } else {\n str_part[str_idx++] = mixed_list[i];\n }\n }\n qsort(int_part, int_count, sizeof(Mixed), compare_ints);\n qsort(str_part, str_count, sizeof(Mixed), compare_strings);\n Mixed* sorted = malloc(size * sizeof(Mixed));\n for (size_t i = 0; i < int_count; i++) {\n sorted[i] = int_part[i];\n }\n for (size_t i = 0; i < str_count; i++) {\n sorted[int_count + i] = str_part[i];\n }\n free(int_part);\n free(str_part);\n *sorted_size = size;\n return sorted;\n}", + "test": "int main() {\n\n Mixed input[] = {\n\n {INT_TYPE, .value.i = 19},\n\n {STRING_TYPE, .value.s = \"red\"},\n\n {INT_TYPE, .value.i = 12},\n\n {STRING_TYPE, .value.s = \"green\"},\n\n {STRING_TYPE, .value.s = \"blue\"},\n\n {INT_TYPE, .value.i = 10},\n\n {STRING_TYPE, .value.s = \"white\"},\n\n {STRING_TYPE, .value.s = \"green\"},\n\n {INT_TYPE, .value.i = 1}\n\n };\n\n size_t size = sizeof(input) / sizeof(input[0]);\n\n\n\n Mixed* sorted = func0(input, size, &size);\n\n\n\n Mixed expected[] = {\n\n {INT_TYPE, .value.i = 1},\n\n {INT_TYPE, .value.i = 10},\n\n {INT_TYPE, .value.i = 12},\n\n {INT_TYPE, .value.i = 19},\n\n {STRING_TYPE, .value.s = \"blue\"},\n\n {STRING_TYPE, .value.s = \"green\"},\n\n {STRING_TYPE, .value.s = \"green\"},\n\n {STRING_TYPE, .value.s = \"red\"},\n\n {STRING_TYPE, .value.s = \"white\"}\n\n };\n\n size_t expected_size = sizeof(expected) / sizeof(expected[0]);\n\n\n\n assert(size == expected_size);\n\n for(size_t i = 0; i < size; i++) {\n\n assert(sorted[i].type == expected[i].type);\n\n if(sorted[i].type == INT_TYPE) {\n\n assert(sorted[i].value.i == expected[i].value.i);\n\n } else {\n\n assert(strcmp(sorted[i].value.s, expected[i].value.s) == 0);\n\n }\n\n }\n\n\n\n // Repeat the assertions\n\n Mixed* sorted2 = func0(input, size, &size);\n\n assert(size == expected_size);\n\n for(size_t i = 0; i < size; i++) {\n\n assert(sorted2[i].type == expected[i].type);\n\n if(sorted2[i].type == INT_TYPE) {\n\n assert(sorted2[i].value.i == expected[i].value.i);\n\n } else {\n\n assert(strcmp(sorted2[i].value.s, expected[i].value.s) == 0);\n\n }\n\n }\n\n\n\n Mixed* sorted3 = func0(input, size, &size);\n\n assert(size == expected_size);\n\n for(size_t i = 0; i < size; i++) {\n\n assert(sorted3[i].type == expected[i].type);\n\n if(sorted3[i].type == INT_TYPE) {\n\n assert(sorted3[i].value.i == expected[i].value.i);\n\n } else {\n\n assert(strcmp(sorted3[i].value.s, expected[i].value.s) == 0);\n\n }\n\n }\n\n\n\n free(sorted);\n\n free(sorted2);\n\n free(sorted3);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nadd $0xffffffffffffff80,%rsp\nmov %rdi,-0x68(%rbp)\nmov %rsi,-0x70(%rbp)\nmov %rdx,-0x78(%rbp)\nmovq $0x0,-0x58(%rbp)\nmovq $0x0,-0x50(%rbp)\nmovq $0x0,-0x48(%rbp)\njmp 12c7 \nmov -0x48(%rbp),%rax\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x68(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ntest %eax,%eax\njne 12bd \naddq $0x1,-0x58(%rbp)\njmp 12c2 \naddq $0x1,-0x50(%rbp)\naddq $0x1,-0x48(%rbp)\nmov -0x48(%rbp),%rax\ncmp -0x70(%rbp),%rax\njb 129e \nmov -0x58(%rbp),%rax\nshl $0x4,%rax\nmov %rax,%rdi\ncallq 10f0 \nmov %rax,-0x18(%rbp)\nmov -0x50(%rbp),%rax\nshl $0x4,%rax\nmov %rax,%rdi\ncallq 10f0 \nmov %rax,-0x10(%rbp)\nmovq $0x0,-0x40(%rbp)\nmovq $0x0,-0x38(%rbp)\nmovq $0x0,-0x30(%rbp)\njmpq 13ad \nmov -0x30(%rbp),%rax\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x68(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ntest %eax,%eax\njne 136c \nmov -0x30(%rbp),%rax\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x68(%rbp),%rax\nlea (%rdx,%rax,1),%rsi\nmov -0x40(%rbp),%rax\nlea 0x1(%rax),%rdx\nmov %rdx,-0x40(%rbp)\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov (%rsi),%rax\nmov 0x8(%rsi),%rdx\nmov %rax,(%rcx)\nmov %rdx,0x8(%rcx)\njmp 13a8 \nmov -0x30(%rbp),%rax\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x68(%rbp),%rax\nlea (%rdx,%rax,1),%rsi\nmov -0x38(%rbp),%rax\nlea 0x1(%rax),%rdx\nmov %rdx,-0x38(%rbp)\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x10(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov (%rsi),%rax\nmov 0x8(%rsi),%rdx\nmov %rax,(%rcx)\nmov %rdx,0x8(%rcx)\naddq $0x1,-0x30(%rbp)\nmov -0x30(%rbp),%rax\ncmp -0x70(%rbp),%rax\njb 1316 \nmov -0x58(%rbp),%rsi\nmov -0x18(%rbp),%rax\nlea -0x1e1(%rip),%rcx\nmov $0x10,%edx\nmov %rax,%rdi\ncallq 10b0 \nmov -0x50(%rbp),%rsi\nmov -0x10(%rbp),%rax\nlea -0x1bb(%rip),%rcx\nmov $0x10,%edx\nmov %rax,%rdi\ncallq 10b0 \nmov -0x70(%rbp),%rax\nshl $0x4,%rax\nmov %rax,%rdi\ncallq 10f0 \nmov %rax,-0x8(%rbp)\nmovq $0x0,-0x28(%rbp)\njmp 1448 \nmov -0x28(%rbp),%rax\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0x28(%rbp),%rdx\nmov %rdx,%rcx\nshl $0x4,%rcx\nmov -0x8(%rbp),%rdx\nadd %rdx,%rcx\nmov 0x8(%rax),%rdx\nmov (%rax),%rax\nmov %rax,(%rcx)\nmov %rdx,0x8(%rcx)\naddq $0x1,-0x28(%rbp)\nmov -0x28(%rbp),%rax\ncmp -0x58(%rbp),%rax\njb 1411 \nmovq $0x0,-0x20(%rbp)\njmp 149a \nmov -0x20(%rbp),%rax\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x10(%rbp),%rax\nadd %rdx,%rax\nmov -0x58(%rbp),%rcx\nmov -0x20(%rbp),%rdx\nadd %rcx,%rdx\nmov %rdx,%rcx\nshl $0x4,%rcx\nmov -0x8(%rbp),%rdx\nadd %rdx,%rcx\nmov 0x8(%rax),%rdx\nmov (%rax),%rax\nmov %rax,(%rcx)\nmov %rdx,0x8(%rcx)\naddq $0x1,-0x20(%rbp)\nmov -0x20(%rbp),%rax\ncmp -0x50(%rbp),%rax\njb 145c \nmov -0x18(%rbp),%rax\nmov %rax,%rdi\ncallq 10a0 \nmov -0x10(%rbp),%rax\nmov %rax,%rdi\ncallq 10a0 \nmov -0x78(%rbp),%rax\nmov -0x70(%rbp),%rdx\nmov %rdx,(%rax)\nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nadd rsp, 0FFFFFFFFFFFFFF80h\nmov [rbp+var_68], rdi\nmov [rbp+var_70], rsi\nmov [rbp+var_78], rdx\nmov [rbp+nmemb], 0\nmov [rbp+var_50], 0\nmov [rbp+var_48], 0\njmp short loc_12C7\nloc_129E:\nmov rax, [rbp+var_48]\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_68]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njnz short loc_12BD\nadd [rbp+nmemb], 1\njmp short loc_12C2\nloc_12BD:\nadd [rbp+var_50], 1\nloc_12C2:\nadd [rbp+var_48], 1\nloc_12C7:\nmov rax, [rbp+var_48]\ncmp rax, [rbp+var_70]\njb short loc_129E\nmov rax, [rbp+nmemb]\nshl rax, 4\nmov rdi, rax; size\ncall _malloc\nmov [rbp+base], rax\nmov rax, [rbp+var_50]\nshl rax, 4\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov [rbp+var_40], 0\nmov [rbp+var_38], 0\nmov [rbp+var_30], 0\njmp loc_13AD\nloc_1316:\nmov rax, [rbp+var_30]\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_68]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njnz short loc_136C\nmov rax, [rbp+var_30]\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_68]\nlea rsi, [rdx+rax]\nmov rax, [rbp+var_40]\nlea rdx, [rax+1]\nmov [rbp+var_40], rdx\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+base]\nlea rcx, [rdx+rax]\nmov rax, [rsi]\nmov rdx, [rsi+8]\nmov [rcx], rax\nmov [rcx+8], rdx\njmp short loc_13A8\nloc_136C:\nmov rax, [rbp+var_30]\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_68]\nlea rsi, [rdx+rax]\nmov rax, [rbp+var_38]\nlea rdx, [rax+1]\nmov [rbp+var_38], rdx\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+ptr]\nlea rcx, [rdx+rax]\nmov rax, [rsi]\nmov rdx, [rsi+8]\nmov [rcx], rax\nmov [rcx+8], rdx\nloc_13A8:\nadd [rbp+var_30], 1\nloc_13AD:\nmov rax, [rbp+var_30]\ncmp rax, [rbp+var_70]\njb loc_1316\nmov rsi, [rbp+nmemb]; nmemb\nmov rax, [rbp+base]\nlea rdx, compare_ints\nmov rcx, rdx; compar\nmov edx, 10h; size\nmov rdi, rax; base\ncall _qsort\nmov rsi, [rbp+var_50]; nmemb\nmov rax, [rbp+ptr]\nlea rdx, compare_strings\nmov rcx, rdx; compar\nmov edx, 10h; size\nmov rdi, rax; base\ncall _qsort\nmov rax, [rbp+var_70]\nshl rax, 4\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_28], 0\njmp short loc_144E\nloc_1417:\nmov rax, [rbp+var_28]\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+base]\nadd rax, rdx\nmov rdx, [rbp+var_28]\nmov rcx, rdx\nshl rcx, 4\nmov rdx, [rbp+var_8]\nadd rcx, rdx\nmov rdx, [rax+8]\nmov rax, [rax]\nmov [rcx], rax\nmov [rcx+8], rdx\nadd [rbp+var_28], 1\nloc_144E:\nmov rax, [rbp+var_28]\ncmp rax, [rbp+nmemb]\njb short loc_1417\nmov [rbp+var_20], 0\njmp short loc_14A0\nloc_1462:\nmov rax, [rbp+var_20]\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rcx, [rbp+nmemb]\nmov rdx, [rbp+var_20]\nadd rdx, rcx\nmov rcx, rdx\nshl rcx, 4\nmov rdx, [rbp+var_8]\nadd rcx, rdx\nmov rdx, [rax+8]\nmov rax, [rax]\nmov [rcx], rax\nmov [rcx+8], rdx\nadd [rbp+var_20], 1\nloc_14A0:\nmov rax, [rbp+var_20]\ncmp rax, [rbp+var_50]\njb short loc_1462\nmov rax, [rbp+base]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_78]\nmov rdx, [rbp+var_70]\nmov [rax], rdx\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, unsigned __int64 a2, unsigned __int64 *a3)\n{\n __int64 v3; // rsi\n __int64 v4; // rax\n char *v5; // rcx\n __int64 v6; // rdx\n __int64 v7; // rax\n char *v8; // rax\n char *v9; // rcx\n __int64 v10; // rdx\n char *v11; // rax\n char *v12; // rcx\n __int64 v13; // rdx\n size_t nmemb; // [rsp+28h] [rbp-58h]\n size_t v18; // [rsp+30h] [rbp-50h]\n unsigned __int64 i; // [rsp+38h] [rbp-48h]\n __int64 v20; // [rsp+40h] [rbp-40h]\n __int64 v21; // [rsp+48h] [rbp-38h]\n unsigned __int64 j; // [rsp+50h] [rbp-30h]\n size_t k; // [rsp+58h] [rbp-28h]\n size_t m; // [rsp+60h] [rbp-20h]\n char *base; // [rsp+68h] [rbp-18h]\n char *ptr; // [rsp+70h] [rbp-10h]\n char *v27; // [rsp+78h] [rbp-8h]\n\n nmemb = 0LL;\n v18 = 0LL;\n for ( i = 0LL; i < a2; ++i )\n {\n if ( *(_DWORD *)(16 * i + a1) )\n ++v18;\n else\n ++nmemb;\n }\n base = (char *)malloc(16 * nmemb);\n ptr = (char *)malloc(16 * v18);\n v20 = 0LL;\n v21 = 0LL;\n for ( j = 0LL; j < a2; ++j )\n {\n v3 = 16 * j + a1;\n if ( *(_DWORD *)v3 )\n {\n v7 = v21++;\n v5 = &ptr[16 * v7];\n }\n else\n {\n v4 = v20++;\n v5 = &base[16 * v4];\n }\n v6 = *(_QWORD *)(v3 + 8);\n *(_QWORD *)v5 = *(_QWORD *)v3;\n *((_QWORD *)v5 + 1) = v6;\n }\n qsort(base, nmemb, 0x10uLL, compare_ints);\n qsort(ptr, v18, 0x10uLL, compare_strings);\n v27 = (char *)malloc(16 * a2);\n for ( k = 0LL; k < nmemb; ++k )\n {\n v8 = &base[16 * k];\n v9 = &v27[16 * k];\n v10 = *((_QWORD *)v8 + 1);\n *(_QWORD *)v9 = *(_QWORD *)v8;\n *((_QWORD *)v9 + 1) = v10;\n }\n for ( m = 0LL; m < v18; ++m )\n {\n v11 = &ptr[16 * m];\n v12 = &v27[16 * nmemb + 16 * m];\n v13 = *((_QWORD *)v11 + 1);\n *(_QWORD *)v12 = *(_QWORD *)v11;\n *((_QWORD *)v12 + 1) = v13;\n }\n free(base);\n free(ptr);\n *a3 = a2;\n return v27;\n}", + "ida_strip_asm": "sub_126C:\nendbr64\npush rbp\nmov rbp, rsp\nadd rsp, 0FFFFFFFFFFFFFF80h\nmov [rbp+var_68], rdi\nmov [rbp+var_70], rsi\nmov [rbp+var_78], rdx\nmov [rbp+nmemb], 0\nmov [rbp+var_50], 0\nmov [rbp+var_48], 0\njmp short loc_12C7\nloc_129E:\nmov rax, [rbp+var_48]\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_68]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njnz short loc_12BD\nadd [rbp+nmemb], 1\njmp short loc_12C2\nloc_12BD:\nadd [rbp+var_50], 1\nloc_12C2:\nadd [rbp+var_48], 1\nloc_12C7:\nmov rax, [rbp+var_48]\ncmp rax, [rbp+var_70]\njb short loc_129E\nmov rax, [rbp+nmemb]\nshl rax, 4\nmov rdi, rax; size\ncall _malloc\nmov [rbp+base], rax\nmov rax, [rbp+var_50]\nshl rax, 4\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov [rbp+var_40], 0\nmov [rbp+var_38], 0\nmov [rbp+var_30], 0\njmp loc_13AD\nloc_1316:\nmov rax, [rbp+var_30]\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_68]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njnz short loc_136C\nmov rax, [rbp+var_30]\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_68]\nlea rsi, [rdx+rax]\nmov rax, [rbp+var_40]\nlea rdx, [rax+1]\nmov [rbp+var_40], rdx\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+base]\nlea rcx, [rdx+rax]\nmov rax, [rsi]\nmov rdx, [rsi+8]\nmov [rcx], rax\nmov [rcx+8], rdx\njmp short loc_13A8\nloc_136C:\nmov rax, [rbp+var_30]\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_68]\nlea rsi, [rdx+rax]\nmov rax, [rbp+var_38]\nlea rdx, [rax+1]\nmov [rbp+var_38], rdx\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+ptr]\nlea rcx, [rdx+rax]\nmov rax, [rsi]\nmov rdx, [rsi+8]\nmov [rcx], rax\nmov [rcx+8], rdx\nloc_13A8:\nadd [rbp+var_30], 1\nloc_13AD:\nmov rax, [rbp+var_30]\ncmp rax, [rbp+var_70]\njb loc_1316\nmov rsi, [rbp+nmemb]; nmemb\nmov rax, [rbp+base]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 10h; size\nmov rdi, rax; base\ncall _qsort\nmov rsi, [rbp+var_50]; nmemb\nmov rax, [rbp+ptr]\nlea rdx, sub_122B\nmov rcx, rdx; compar\nmov edx, 10h; size\nmov rdi, rax; base\ncall _qsort\nmov rax, [rbp+var_70]\nshl rax, 4\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_28], 0\njmp short loc_144E\nloc_1417:\nmov rax, [rbp+var_28]\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+base]\nadd rax, rdx\nmov rdx, [rbp+var_28]\nmov rcx, rdx\nshl rcx, 4\nmov rdx, [rbp+var_8]\nadd rcx, rdx\nmov rdx, [rax+8]\nmov rax, [rax]\nmov [rcx], rax\nmov [rcx+8], rdx\nadd [rbp+var_28], 1\nloc_144E:\nmov rax, [rbp+var_28]\ncmp rax, [rbp+nmemb]\njb short loc_1417\nmov [rbp+var_20], 0\njmp short loc_14A0\nloc_1462:\nmov rax, [rbp+var_20]\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rcx, [rbp+nmemb]\nmov rdx, [rbp+var_20]\nadd rdx, rcx\nmov rcx, rdx\nshl rcx, 4\nmov rdx, [rbp+var_8]\nadd rcx, rdx\nmov rdx, [rax+8]\nmov rax, [rax]\nmov [rcx], rax\nmov [rcx+8], rdx\nadd [rbp+var_20], 1\nloc_14A0:\nmov rax, [rbp+var_20]\ncmp rax, [rbp+var_50]\njb short loc_1462\nmov rax, [rbp+base]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_78]\nmov rdx, [rbp+var_70]\nmov [rax], rdx\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_126C(__int64 a1, unsigned __int64 a2, unsigned __int64 *a3)\n{\n __int64 v3; // rsi\n __int64 v4; // rax\n char *v5; // rcx\n __int64 v6; // rdx\n __int64 v7; // rax\n char *v8; // rax\n char *v9; // rcx\n __int64 v10; // rdx\n char *v11; // rax\n char *v12; // rcx\n __int64 v13; // rdx\n size_t nmemb; // [rsp+28h] [rbp-58h]\n size_t v18; // [rsp+30h] [rbp-50h]\n unsigned __int64 i; // [rsp+38h] [rbp-48h]\n __int64 v20; // [rsp+40h] [rbp-40h]\n __int64 v21; // [rsp+48h] [rbp-38h]\n unsigned __int64 j; // [rsp+50h] [rbp-30h]\n size_t k; // [rsp+58h] [rbp-28h]\n size_t m; // [rsp+60h] [rbp-20h]\n char *base; // [rsp+68h] [rbp-18h]\n char *ptr; // [rsp+70h] [rbp-10h]\n char *v27; // [rsp+78h] [rbp-8h]\n\n nmemb = 0LL;\n v18 = 0LL;\n for ( i = 0LL; i < a2; ++i )\n {\n if ( *(_DWORD *)(16 * i + a1) )\n ++v18;\n else\n ++nmemb;\n }\n base = (char *)malloc(16 * nmemb);\n ptr = (char *)malloc(16 * v18);\n v20 = 0LL;\n v21 = 0LL;\n for ( j = 0LL; j < a2; ++j )\n {\n v3 = 16 * j + a1;\n if ( *(_DWORD *)v3 )\n {\n v7 = v21++;\n v5 = &ptr[16 * v7];\n }\n else\n {\n v4 = v20++;\n v5 = &base[16 * v4];\n }\n v6 = *(_QWORD *)(v3 + 8);\n *(_QWORD *)v5 = *(_QWORD *)v3;\n *((_QWORD *)v5 + 1) = v6;\n }\n qsort(base, nmemb, 0x10uLL, compar);\n qsort(ptr, v18, 0x10uLL, sub_122B);\n v27 = (char *)malloc(16 * a2);\n for ( k = 0LL; k < nmemb; ++k )\n {\n v8 = &base[16 * k];\n v9 = &v27[16 * k];\n v10 = *((_QWORD *)v8 + 1);\n *(_QWORD *)v9 = *(_QWORD *)v8;\n *((_QWORD *)v9 + 1) = v10;\n }\n for ( m = 0LL; m < v18; ++m )\n {\n v11 = &ptr[16 * m];\n v12 = &v27[16 * nmemb + 16 * m];\n v13 = *((_QWORD *)v11 + 1);\n *(_QWORD *)v12 = *(_QWORD *)v11;\n *((_QWORD *)v12 + 1) = v13;\n }\n free(base);\n free(ptr);\n *a3 = a2;\n return v27;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_126C(long long a1, unsigned long long a2, unsigned long long *a3) {\n long long v3;\n long long v4;\n char *v5;\n long long v6;\n long long v7;\n char *v8;\n char *v9;\n long long v10;\n char *v11;\n char *v12;\n long long v13;\n unsigned int nmemb;\n unsigned int v18;\n unsigned long long i;\n long long v20;\n long long v21;\n unsigned long long j;\n unsigned int k;\n unsigned int m;\n char *base;\n char *ptr;\n char *v27;\n nmemb = 0LL;\n v18 = 0LL;\n for (i = 0LL; i < a2; ++i) {\n if (*(uint32_t *)(16 * i + a1))\n ++v18;\n else\n ++nmemb;\n }\n base = (char *)malloc(16 * nmemb);\n ptr = (char *)malloc(16 * v18);\n v20 = 0LL;\n v21 = 0LL;\n for (j = 0LL; j < a2; ++j) {\n v3 = 16 * j + a1;\n if (*(uint32_t *)v3) {\n v7 = v21++;\n v5 = &ptr[16 * v7];\n } else {\n v4 = v20++;\n v5 = &base[16 * v4];\n }\n v6 = *(uint64_t *)(v3 + 8);\n *(uint64_t *)v5 = *(uint64_t *)v3;\n *((uint64_t *)v5 + 1) = v6;\n }\n qsort(base, nmemb, 16uLL, compar);\n qsort(ptr, v18, 16uLL, sub_122B);\n v27 = (char *)malloc(16 * a2);\n for (k = 0LL; k < nmemb; ++k) {\n v8 = &base[16 * k];\n v9 = &v27[16 * k];\n v10 = *((uint64_t *)v8 + 1);\n *(uint64_t *)v9 = *(uint64_t *)v8;\n *((uint64_t *)v9 + 1) = v10;\n }\n for (m = 0LL; m < v18; ++m) {\n v11 = &ptr[16 * m];\n v12 = &v27[16 * nmemb + 16 * m];\n v13 = *((uint64_t *)v11 + 1);\n *(uint64_t *)v12 = *(uint64_t *)v11;\n *((uint64_t *)v12 + 1) = v13;\n }\n free(base);\n free(ptr);\n *a3 = a2;\n return v27;\n}", + "ida_pseudo_norm": "char *func0(long long a1, unsigned long long a2, unsigned long long *a3) {\n long long v3;\n long long v4;\n char *v5;\n long long v6;\n long long v7;\n char *v8;\n char *v9;\n long long v10;\n char *v11;\n char *v12;\n long long v13;\n unsigned int nmemb;\n unsigned int v18;\n unsigned long long i;\n long long v20;\n long long v21;\n unsigned long long j;\n unsigned int k;\n unsigned int m;\n char *base;\n char *ptr;\n char *v27;\n nmemb = 0LL;\n v18 = 0LL;\n for (i = 0LL; i < a2; ++i) {\n if (*(uint32_t *)(16 * i + a1))\n ++v18;\n else\n ++nmemb;\n }\n base = (char *)malloc(16 * nmemb);\n ptr = (char *)malloc(16 * v18);\n v20 = 0LL;\n v21 = 0LL;\n for (j = 0LL; j < a2; ++j) {\n v3 = 16 * j + a1;\n if (*(uint32_t *)v3) {\n v7 = v21++;\n v5 = &ptr[16 * v7];\n } else {\n v4 = v20++;\n v5 = &base[16 * v4];\n }\n v6 = *(uint64_t *)(v3 + 8);\n *(uint64_t *)v5 = *(uint64_t *)v3;\n *((uint64_t *)v5 + 1) = v6;\n }\n qsort(base, nmemb, 16uLL, compare_ints);\n qsort(ptr, v18, 16uLL, compare_strings);\n v27 = (char *)malloc(16 * a2);\n for (k = 0LL; k < nmemb; ++k) {\n v8 = &base[16 * k];\n v9 = &v27[16 * k];\n v10 = *((uint64_t *)v8 + 1);\n *(uint64_t *)v9 = *(uint64_t *)v8;\n *((uint64_t *)v9 + 1) = v10;\n }\n for (m = 0LL; m < v18; ++m) {\n v11 = &ptr[16 * m];\n v12 = &v27[16 * nmemb + 16 * m];\n v13 = *((uint64_t *)v11 + 1);\n *(uint64_t *)v12 = *(uint64_t *)v11;\n *((uint64_t *)v12 + 1) = v13;\n }\n free(base);\n free(ptr);\n *a3 = a2;\n return v27;\n}" + }, + { + "index": 37, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef enum { INT_TYPE, STRING_TYPE } ElementType;\n\n\n\ntypedef struct {\n\n ElementType type;\n\n union {\n\n int i;\n\n char* s;\n\n } value;\n\n} Mixed;\n\n\n\nint compare_ints(const void* a, const void* b) {\n\n int int_a = ((Mixed*)a)->value.i;\n\n int int_b = ((Mixed*)b)->value.i;\n\n return (int_a > int_b) - (int_a < int_b);\n\n}\n\n\n\nint compare_strings(const void* a, const void* b) {\n\n char* str_a = ((Mixed*)a)->value.s;\n\n char* str_b = ((Mixed*)b)->value.s;\n\n return strcmp(str_a, str_b);\n\n}\n\n\n\n", + "func": "Mixed* func0(Mixed* mixed_list, size_t size, size_t* sorted_size) {\n size_t int_count = 0, str_count = 0;\n for (size_t i = 0; i < size; i++) {\n if (mixed_list[i].type == INT_TYPE)\n int_count++;\n else\n str_count++;\n }\n Mixed* int_part = malloc(int_count * sizeof(Mixed));\n Mixed* str_part = malloc(str_count * sizeof(Mixed));\n size_t int_idx = 0, str_idx = 0;\n for (size_t i = 0; i < size; i++) {\n if (mixed_list[i].type == INT_TYPE) {\n int_part[int_idx++] = mixed_list[i];\n } else {\n str_part[str_idx++] = mixed_list[i];\n }\n }\n qsort(int_part, int_count, sizeof(Mixed), compare_ints);\n qsort(str_part, str_count, sizeof(Mixed), compare_strings);\n Mixed* sorted = malloc(size * sizeof(Mixed));\n for (size_t i = 0; i < int_count; i++) {\n sorted[i] = int_part[i];\n }\n for (size_t i = 0; i < str_count; i++) {\n sorted[int_count + i] = str_part[i];\n }\n free(int_part);\n free(str_part);\n *sorted_size = size;\n return sorted;\n}", + "test": "int main() {\n\n Mixed input[] = {\n\n {INT_TYPE, .value.i = 19},\n\n {STRING_TYPE, .value.s = \"red\"},\n\n {INT_TYPE, .value.i = 12},\n\n {STRING_TYPE, .value.s = \"green\"},\n\n {STRING_TYPE, .value.s = \"blue\"},\n\n {INT_TYPE, .value.i = 10},\n\n {STRING_TYPE, .value.s = \"white\"},\n\n {STRING_TYPE, .value.s = \"green\"},\n\n {INT_TYPE, .value.i = 1}\n\n };\n\n size_t size = sizeof(input) / sizeof(input[0]);\n\n\n\n Mixed* sorted = func0(input, size, &size);\n\n\n\n Mixed expected[] = {\n\n {INT_TYPE, .value.i = 1},\n\n {INT_TYPE, .value.i = 10},\n\n {INT_TYPE, .value.i = 12},\n\n {INT_TYPE, .value.i = 19},\n\n {STRING_TYPE, .value.s = \"blue\"},\n\n {STRING_TYPE, .value.s = \"green\"},\n\n {STRING_TYPE, .value.s = \"green\"},\n\n {STRING_TYPE, .value.s = \"red\"},\n\n {STRING_TYPE, .value.s = \"white\"}\n\n };\n\n size_t expected_size = sizeof(expected) / sizeof(expected[0]);\n\n\n\n assert(size == expected_size);\n\n for(size_t i = 0; i < size; i++) {\n\n assert(sorted[i].type == expected[i].type);\n\n if(sorted[i].type == INT_TYPE) {\n\n assert(sorted[i].value.i == expected[i].value.i);\n\n } else {\n\n assert(strcmp(sorted[i].value.s, expected[i].value.s) == 0);\n\n }\n\n }\n\n\n\n // Repeat the assertions\n\n Mixed* sorted2 = func0(input, size, &size);\n\n assert(size == expected_size);\n\n for(size_t i = 0; i < size; i++) {\n\n assert(sorted2[i].type == expected[i].type);\n\n if(sorted2[i].type == INT_TYPE) {\n\n assert(sorted2[i].value.i == expected[i].value.i);\n\n } else {\n\n assert(strcmp(sorted2[i].value.s, expected[i].value.s) == 0);\n\n }\n\n }\n\n\n\n Mixed* sorted3 = func0(input, size, &size);\n\n assert(size == expected_size);\n\n for(size_t i = 0; i < size; i++) {\n\n assert(sorted3[i].type == expected[i].type);\n\n if(sorted3[i].type == INT_TYPE) {\n\n assert(sorted3[i].value.i == expected[i].value.i);\n\n } else {\n\n assert(strcmp(sorted3[i].value.s, expected[i].value.s) == 0);\n\n }\n\n }\n\n\n\n free(sorted);\n\n free(sorted2);\n\n free(sorted3);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov %rsi,(%rsp)\nmov %rdx,0x8(%rsp)\ntest %rsi,%rsi\nje 1399 \nmov %rsi,%rax\nmov %rdi,%rbx\nshl $0x4,%rax\nmov %rax,%r13\nadd %rdi,%r13\nmov $0x0,%r12d\nmov $0x0,%ebp\njmp 1270 \nadd $0x1,%r12\nadd $0x10,%rdi\ncmp %r13,%rdi\nje 136c \ncmpl $0x0,(%rdi)\njne 125f \nadd $0x1,%rbp\njmp 1263 \nmov %rdx,%rcx\nshl $0x4,%rcx\nmovdqu (%rbx),%xmm3\nmovups %xmm3,(%r14,%rcx,1)\nlea 0x1(%rdx),%rdx\nadd $0x10,%rbx\ncmp %r13,%rbx\nje 12b3 \ncmpl $0x0,(%rbx)\njne 127b \nmov %rax,%rcx\nshl $0x4,%rcx\nmovdqu (%rbx),%xmm2\nmovups %xmm2,(%r15,%rcx,1)\nlea 0x1(%rax),%rax\njmp 128f \nlea -0xd1(%rip),%rcx\nmov $0x10,%edx\nmov %rbp,%rsi\nmov %r15,%rdi\ncallq 10b0 \nlea -0xcd(%rip),%rcx\nmov $0x10,%edx\nmov %r12,%rsi\nmov %r14,%rdi\ncallq 10b0 \nmov (%rsp),%rdi\nshl $0x4,%rdi\ncallq 10f0 \nmov %rax,%rbx\ntest %rbp,%rbp\nje 1315 \nmov %rbp,%rdx\nshl $0x4,%rdx\nmov $0x0,%eax\nmovdqu (%r15,%rax,1),%xmm0\nmovups %xmm0,(%rbx,%rax,1)\nadd $0x10,%rax\ncmp %rdx,%rax\njne 1302 \ntest %r12,%r12\nje 133e \nshl $0x4,%r12\nshl $0x4,%rbp\nadd %rbx,%rbp\nmov $0x0,%eax\nmovdqu (%r14,%rax,1),%xmm1\nmovups %xmm1,0x0(%rbp,%rax,1)\nadd $0x10,%rax\ncmp %r12,%rax\njne 132a \nmov %r15,%rdi\ncallq 10a0 \nmov %r14,%rdi\ncallq 10a0 \nmov 0x8(%rsp),%rax\nmov (%rsp),%rsi\nmov %rsi,(%rax)\nmov %rbx,%rax\nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmov %rbp,%rdi\nshl $0x4,%rdi\ncallq 10f0 \nmov %rax,%r15\nmov %r12,%rdi\nshl $0x4,%rdi\ncallq 10f0 \nmov %rax,%r14\nmov $0x0,%edx\nmov $0x0,%eax\njmpq 1298 \nmov $0x0,%edi\ncallq 10f0 \nmov %rax,%r15\nmov $0x0,%edi\ncallq 10f0 \nmov %rax,%r14\nlea -0x1d1(%rip),%rcx\nmov $0x10,%edx\nmov $0x0,%esi\nmov %r15,%rdi\ncallq 10b0 \nlea -0x1cf(%rip),%rcx\nmov $0x10,%edx\nmov $0x0,%esi\nmov %r14,%rdi\ncallq 10b0 \nmov (%rsp),%rbp\nmov %rbp,%rdi\nshl $0x4,%rdi\ncallq 10f0 \nmov %rax,%rbx\nmov %rbp,%r12\njmpq 1315 \n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_48], rsi\nmov [rsp+48h+var_40], rdx\ntest rsi, rsi\njz loc_1390\nmov rax, rsi\nmov rbx, rdi\nshl rax, 4\nmov r13, rax\nadd r13, rdi\nmov r12d, 0\nmov ebp, 0\njmp short loc_126A\nloc_125D:\nadd r12, 1\nloc_1261:\nadd rdi, 10h\ncmp rdi, r13\njz short loc_1275\nloc_126A:\ncmp dword ptr [rdi], 0\njnz short loc_125D\nadd rbp, 1\njmp short loc_1261\nloc_1275:\nmov rdi, rbp\nshl rdi, 4; size\ncall _malloc\nmov r15, rax\nmov rdi, r12\nshl rdi, 4; size\ncall _malloc\nmov r14, rax\nmov edx, 0\nmov eax, 0\njmp short loc_12BC\nloc_129F:\nmov rcx, rdx\nshl rcx, 4\nmovdqu xmm3, xmmword ptr [rbx]\nmovups xmmword ptr [r14+rcx], xmm3\nlea rdx, [rdx+1]\nloc_12B3:\nadd rbx, 10h\ncmp rbx, r13\njz short loc_12D7\nloc_12BC:\ncmp dword ptr [rbx], 0\njnz short loc_129F\nmov rcx, rax\nshl rcx, 4\nmovdqu xmm2, xmmword ptr [rbx]\nmovups xmmword ptr [r15+rcx], xmm2\nlea rax, [rax+1]\njmp short loc_12B3\nloc_12D7:\nlea rcx, compare_ints; compar\nmov edx, 10h; size\nmov rsi, rbp; nmemb\nmov rdi, r15; base\ncall _qsort\nlea rcx, compare_strings; compar\nmov edx, 10h; size\nmov rsi, r12; nmemb\nmov rdi, r14; base\ncall _qsort\nmov rdi, [rsp+48h+var_48]\nshl rdi, 4; size\ncall _malloc\nmov rbx, rax\ntest rbp, rbp\njz short loc_1339\nmov rdx, rbp\nshl rdx, 4\nmov eax, 0\nloc_1326:\nmovdqu xmm0, xmmword ptr [r15+rax]\nmovups xmmword ptr [rbx+rax], xmm0\nadd rax, 10h\ncmp rax, rdx\njnz short loc_1326\nloc_1339:\ntest r12, r12\njz short loc_1362\nshl r12, 4\nshl rbp, 4\nadd rbp, rbx\nmov eax, 0\nloc_134E:\nmovdqu xmm1, xmmword ptr [r14+rax]\nmovups xmmword ptr [rbp+rax+0], xmm1\nadd rax, 10h\ncmp rax, r12\njnz short loc_134E\nloc_1362:\nmov rdi, r15; ptr\ncall _free\nmov rdi, r14; ptr\ncall _free\nmov rax, [rsp+48h+var_40]\nmov rsi, [rsp+48h+var_48]\nmov [rax], rsi\nmov rax, rbx\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1390:\nmov edi, 0; size\ncall _malloc\nmov r15, rax\nmov edi, 0; size\ncall _malloc\nmov r14, rax\nlea rcx, compare_ints; compar\nmov edx, 10h; size\nmov esi, 0; nmemb\nmov rdi, r15; base\ncall _qsort\nlea rcx, compare_strings; compar\nmov edx, 10h; size\nmov esi, 0; nmemb\nmov rdi, r14; base\ncall _qsort\nmov r12, [rsp+48h+var_48]\nmov rdi, r12\nshl rdi, 4; size\ncall _malloc\nmov rbx, rax\nmov rbp, r12\njmp loc_1339", + "ida_pseudo": "char *__fastcall func0(const __m128i *a1, __int64 a2, _QWORD *a3)\n{\n const __m128i *v3; // rbx\n const __m128i *v4; // r13\n size_t v5; // r12\n size_t v6; // rbp\n __m128i *v7; // r15\n __m128i *v8; // r14\n __int64 v9; // rdx\n __int64 v10; // rax\n char *v11; // rbx\n __int64 i; // rax\n __int64 v13; // r12\n char *v14; // rbp\n unsigned __int64 v15; // rax\n\n if ( a2 )\n {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0LL;\n v6 = 0LL;\n do\n {\n if ( a1->m128i_i32[0] )\n ++v5;\n else\n ++v6;\n ++a1;\n }\n while ( a1 != v4 );\n v7 = (__m128i *)malloc(16 * v6);\n v8 = (__m128i *)malloc(16 * v5);\n v9 = 0LL;\n v10 = 0LL;\n do\n {\n if ( v3->m128i_i32[0] )\n v8[v9++] = _mm_loadu_si128(v3);\n else\n v7[v10++] = _mm_loadu_si128(v3);\n ++v3;\n }\n while ( v3 != v4 );\n qsort(v7, v6, 0x10uLL, compare_ints);\n qsort(v8, v5, 0x10uLL, compare_strings);\n v11 = (char *)malloc(16 * a2);\n if ( v6 )\n {\n for ( i = 0LL; i != v6; ++i )\n *(__m128i *)&v11[i * 16] = _mm_loadu_si128(&v7[i]);\n }\n }\n else\n {\n v7 = (__m128i *)malloc(0LL);\n v8 = (__m128i *)malloc(0LL);\n qsort(v7, 0LL, 0x10uLL, compare_ints);\n qsort(v8, 0LL, 0x10uLL, compare_strings);\n v5 = 0LL;\n v11 = (char *)malloc(0LL);\n v6 = 0LL;\n }\n if ( v5 )\n {\n v13 = 16 * v5;\n v14 = &v11[16 * v6];\n v15 = 0LL;\n do\n {\n *(__m128i *)&v14[v15] = _mm_loadu_si128(&v8[v15 / 0x10]);\n v15 += 16LL;\n }\n while ( v15 != v13 );\n }\n free(v7);\n free(v8);\n *a3 = a2;\n return v11;\n}", + "ida_strip_asm": "sub_121C:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_48], rsi\nmov [rsp+48h+var_40], rdx\ntest rsi, rsi\njz loc_1390\nmov rax, rsi\nmov rbx, rdi\nshl rax, 4\nmov r13, rax\nadd r13, rdi\nmov r12d, 0\nmov ebp, 0\njmp short loc_126A\nloc_125D:\nadd r12, 1\nloc_1261:\nadd rdi, 10h\ncmp rdi, r13\njz short loc_1275\nloc_126A:\ncmp dword ptr [rdi], 0\njnz short loc_125D\nadd rbp, 1\njmp short loc_1261\nloc_1275:\nmov rdi, rbp\nshl rdi, 4; size\ncall _malloc\nmov r15, rax\nmov rdi, r12\nshl rdi, 4; size\ncall _malloc\nmov r14, rax\nmov edx, 0\nmov eax, 0\njmp short loc_12BC\nloc_129F:\nmov rcx, rdx\nshl rcx, 4\nmovdqu xmm3, xmmword ptr [rbx]\nmovups xmmword ptr [r14+rcx], xmm3\nlea rdx, [rdx+1]\nloc_12B3:\nadd rbx, 10h\ncmp rbx, r13\njz short loc_12D7\nloc_12BC:\ncmp dword ptr [rbx], 0\njnz short loc_129F\nmov rcx, rax\nshl rcx, 4\nmovdqu xmm2, xmmword ptr [rbx]\nmovups xmmword ptr [r15+rcx], xmm2\nlea rax, [rax+1]\njmp short loc_12B3\nloc_12D7:\nlea rcx, compar; compar\nmov edx, 10h; size\nmov rsi, rbp; nmemb\nmov rdi, r15; base\ncall _qsort\nlea rcx, sub_1202; compar\nmov edx, 10h; size\nmov rsi, r12; nmemb\nmov rdi, r14; base\ncall _qsort\nmov rdi, [rsp+48h+var_48]\nshl rdi, 4; size\ncall _malloc\nmov rbx, rax\ntest rbp, rbp\njz short loc_1339\nmov rdx, rbp\nshl rdx, 4\nmov eax, 0\nloc_1326:\nmovdqu xmm0, xmmword ptr [r15+rax]\nmovups xmmword ptr [rbx+rax], xmm0\nadd rax, 10h\ncmp rax, rdx\njnz short loc_1326\nloc_1339:\ntest r12, r12\njz short loc_1362\nshl r12, 4\nshl rbp, 4\nadd rbp, rbx\nmov eax, 0\nloc_134E:\nmovdqu xmm1, xmmword ptr [r14+rax]\nmovups xmmword ptr [rbp+rax+0], xmm1\nadd rax, 10h\ncmp rax, r12\njnz short loc_134E\nloc_1362:\nmov rdi, r15; ptr\ncall _free\nmov rdi, r14; ptr\ncall _free\nmov rax, [rsp+48h+var_40]\nmov rsi, [rsp+48h+var_48]\nmov [rax], rsi\nmov rax, rbx\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1390:\nmov edi, 0; size\ncall _malloc\nmov r15, rax\nmov edi, 0; size\ncall _malloc\nmov r14, rax\nlea rcx, compar; compar\nmov edx, 10h; size\nmov esi, 0; nmemb\nmov rdi, r15; base\ncall _qsort\nlea rcx, sub_1202; compar\nmov edx, 10h; size\nmov esi, 0; nmemb\nmov rdi, r14; base\ncall _qsort\nmov r12, [rsp+48h+var_48]\nmov rdi, r12\nshl rdi, 4; size\ncall _malloc\nmov rbx, rax\nmov rbp, r12\njmp loc_1339", + "ida_strip_pseudo": "char *__fastcall sub_121C(const __m128i *a1, __int64 a2, _QWORD *a3)\n{\n const __m128i *v3; // rbx\n const __m128i *v4; // r13\n size_t v5; // r12\n size_t v6; // rbp\n __m128i *v7; // r15\n __m128i *v8; // r14\n __int64 v9; // rdx\n __int64 v10; // rax\n char *v11; // rbx\n __int64 i; // rax\n __int64 v13; // r12\n char *v14; // rbp\n unsigned __int64 v15; // rax\n\n if ( a2 )\n {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0LL;\n v6 = 0LL;\n do\n {\n if ( a1->m128i_i32[0] )\n ++v5;\n else\n ++v6;\n ++a1;\n }\n while ( a1 != v4 );\n v7 = (__m128i *)malloc(16 * v6);\n v8 = (__m128i *)malloc(16 * v5);\n v9 = 0LL;\n v10 = 0LL;\n do\n {\n if ( v3->m128i_i32[0] )\n v8[v9++] = _mm_loadu_si128(v3);\n else\n v7[v10++] = _mm_loadu_si128(v3);\n ++v3;\n }\n while ( v3 != v4 );\n qsort(v7, v6, 0x10uLL, compar);\n qsort(v8, v5, 0x10uLL, sub_1202);\n v11 = (char *)malloc(16 * a2);\n if ( v6 )\n {\n for ( i = 0LL; i != v6; ++i )\n *(__m128i *)&v11[i * 16] = _mm_loadu_si128(&v7[i]);\n }\n }\n else\n {\n v7 = (__m128i *)malloc(0LL);\n v8 = (__m128i *)malloc(0LL);\n qsort(v7, 0LL, 0x10uLL, compar);\n qsort(v8, 0LL, 0x10uLL, sub_1202);\n v5 = 0LL;\n v11 = (char *)malloc(0LL);\n v6 = 0LL;\n }\n if ( v5 )\n {\n v13 = 16 * v5;\n v14 = &v11[16 * v6];\n v15 = 0LL;\n do\n {\n *(__m128i *)&v14[v15] = _mm_loadu_si128(&v8[v15 / 0x10]);\n v15 += 16LL;\n }\n while ( v15 != v13 );\n }\n free(v7);\n free(v8);\n *a3 = a2;\n return v11;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_121C(const __m128i *a1, long long a2, uint64_t *a3) {\n const __m128i *v3;\n const __m128i *v4;\n unsigned int v5;\n unsigned int v6;\n __m128i *v7;\n __m128i *v8;\n long long v9;\n long long v10;\n char *v11;\n long long i;\n long long v13;\n char *v14;\n unsigned long long v15;\n if (a2) {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0LL;\n v6 = 0LL;\n do {\n if (a1->m128i_i32[0])\n ++v5;\n else\n ++v6;\n ++a1;\n } while (a1 != v4);\n v7 = (__m128i *)malloc(16 * v6);\n v8 = (__m128i *)malloc(16 * v5);\n v9 = 0LL;\n v10 = 0LL;\n do {\n if (v3->m128i_i32[0])\n v8[v9++] = _mm_loadu_si128(v3);\n else\n v7[v10++] = _mm_loadu_si128(v3);\n ++v3;\n } while (v3 != v4);\n qsort(v7, v6, 16uLL, compar);\n qsort(v8, v5, 16uLL, sub_1202);\n v11 = (char *)malloc(16 * a2);\n if (v6) {\n for (i = 0LL; i != v6; ++i)\n *(__m128i *)&v11[i * 16] = _mm_loadu_si128(&v7[i]);\n }\n } else {\n v7 = (__m128i *)malloc(0LL);\n v8 = (__m128i *)malloc(0LL);\n qsort(v7, 0LL, 16uLL, compar);\n qsort(v8, 0LL, 16uLL, sub_1202);\n v5 = 0LL;\n v11 = (char *)malloc(0LL);\n v6 = 0LL;\n }\n if (v5) {\n v13 = 16 * v5;\n v14 = &v11[16 * v6];\n v15 = 0LL;\n do {\n *(__m128i *)&v14[v15] = _mm_loadu_si128(&v8[v15 / 16]);\n v15 += 16LL;\n } while (v15 != v13);\n }\n free(v7);\n free(v8);\n *a3 = a2;\n return v11;\n}", + "ida_pseudo_norm": "char *func0(const __m128i *a1, long long a2, uint64_t *a3) {\n const __m128i *v3;\n const __m128i *v4;\n unsigned int v5;\n unsigned int v6;\n __m128i *v7;\n __m128i *v8;\n long long v9;\n long long v10;\n char *v11;\n long long i;\n long long v13;\n char *v14;\n unsigned long long v15;\n if (a2) {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0LL;\n v6 = 0LL;\n do {\n if (a1->m128i_i32[0])\n ++v5;\n else\n ++v6;\n ++a1;\n } while (a1 != v4);\n v7 = (__m128i *)malloc(16 * v6);\n v8 = (__m128i *)malloc(16 * v5);\n v9 = 0LL;\n v10 = 0LL;\n do {\n if (v3->m128i_i32[0])\n v8[v9++] = _mm_loadu_si128(v3);\n else\n v7[v10++] = _mm_loadu_si128(v3);\n ++v3;\n } while (v3 != v4);\n qsort(v7, v6, 16uLL, compare_ints);\n qsort(v8, v5, 16uLL, compare_strings);\n v11 = (char *)malloc(16 * a2);\n if (v6) {\n for (i = 0LL; i != v6; ++i)\n *(__m128i *)&v11[i * 16] = _mm_loadu_si128(&v7[i]);\n }\n } else {\n v7 = (__m128i *)malloc(0LL);\n v8 = (__m128i *)malloc(0LL);\n qsort(v7, 0LL, 16uLL, compare_ints);\n qsort(v8, 0LL, 16uLL, compare_strings);\n v5 = 0LL;\n v11 = (char *)malloc(0LL);\n v6 = 0LL;\n }\n if (v5) {\n v13 = 16 * v5;\n v14 = &v11[16 * v6];\n v15 = 0LL;\n do {\n *(__m128i *)&v14[v15] = _mm_loadu_si128(&v8[v15 / 16]);\n v15 += 16LL;\n } while (v15 != v13);\n }\n free(v7);\n free(v8);\n *a3 = a2;\n return v11;\n}" + }, + { + "index": 37, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef enum { INT_TYPE, STRING_TYPE } ElementType;\n\n\n\ntypedef struct {\n\n ElementType type;\n\n union {\n\n int i;\n\n char* s;\n\n } value;\n\n} Mixed;\n\n\n\nint compare_ints(const void* a, const void* b) {\n\n int int_a = ((Mixed*)a)->value.i;\n\n int int_b = ((Mixed*)b)->value.i;\n\n return (int_a > int_b) - (int_a < int_b);\n\n}\n\n\n\nint compare_strings(const void* a, const void* b) {\n\n char* str_a = ((Mixed*)a)->value.s;\n\n char* str_b = ((Mixed*)b)->value.s;\n\n return strcmp(str_a, str_b);\n\n}\n\n\n\n", + "func": "Mixed* func0(Mixed* mixed_list, size_t size, size_t* sorted_size) {\n size_t int_count = 0, str_count = 0;\n for (size_t i = 0; i < size; i++) {\n if (mixed_list[i].type == INT_TYPE)\n int_count++;\n else\n str_count++;\n }\n Mixed* int_part = malloc(int_count * sizeof(Mixed));\n Mixed* str_part = malloc(str_count * sizeof(Mixed));\n size_t int_idx = 0, str_idx = 0;\n for (size_t i = 0; i < size; i++) {\n if (mixed_list[i].type == INT_TYPE) {\n int_part[int_idx++] = mixed_list[i];\n } else {\n str_part[str_idx++] = mixed_list[i];\n }\n }\n qsort(int_part, int_count, sizeof(Mixed), compare_ints);\n qsort(str_part, str_count, sizeof(Mixed), compare_strings);\n Mixed* sorted = malloc(size * sizeof(Mixed));\n for (size_t i = 0; i < int_count; i++) {\n sorted[i] = int_part[i];\n }\n for (size_t i = 0; i < str_count; i++) {\n sorted[int_count + i] = str_part[i];\n }\n free(int_part);\n free(str_part);\n *sorted_size = size;\n return sorted;\n}", + "test": "int main() {\n\n Mixed input[] = {\n\n {INT_TYPE, .value.i = 19},\n\n {STRING_TYPE, .value.s = \"red\"},\n\n {INT_TYPE, .value.i = 12},\n\n {STRING_TYPE, .value.s = \"green\"},\n\n {STRING_TYPE, .value.s = \"blue\"},\n\n {INT_TYPE, .value.i = 10},\n\n {STRING_TYPE, .value.s = \"white\"},\n\n {STRING_TYPE, .value.s = \"green\"},\n\n {INT_TYPE, .value.i = 1}\n\n };\n\n size_t size = sizeof(input) / sizeof(input[0]);\n\n\n\n Mixed* sorted = func0(input, size, &size);\n\n\n\n Mixed expected[] = {\n\n {INT_TYPE, .value.i = 1},\n\n {INT_TYPE, .value.i = 10},\n\n {INT_TYPE, .value.i = 12},\n\n {INT_TYPE, .value.i = 19},\n\n {STRING_TYPE, .value.s = \"blue\"},\n\n {STRING_TYPE, .value.s = \"green\"},\n\n {STRING_TYPE, .value.s = \"green\"},\n\n {STRING_TYPE, .value.s = \"red\"},\n\n {STRING_TYPE, .value.s = \"white\"}\n\n };\n\n size_t expected_size = sizeof(expected) / sizeof(expected[0]);\n\n\n\n assert(size == expected_size);\n\n for(size_t i = 0; i < size; i++) {\n\n assert(sorted[i].type == expected[i].type);\n\n if(sorted[i].type == INT_TYPE) {\n\n assert(sorted[i].value.i == expected[i].value.i);\n\n } else {\n\n assert(strcmp(sorted[i].value.s, expected[i].value.s) == 0);\n\n }\n\n }\n\n\n\n // Repeat the assertions\n\n Mixed* sorted2 = func0(input, size, &size);\n\n assert(size == expected_size);\n\n for(size_t i = 0; i < size; i++) {\n\n assert(sorted2[i].type == expected[i].type);\n\n if(sorted2[i].type == INT_TYPE) {\n\n assert(sorted2[i].value.i == expected[i].value.i);\n\n } else {\n\n assert(strcmp(sorted2[i].value.s, expected[i].value.s) == 0);\n\n }\n\n }\n\n\n\n Mixed* sorted3 = func0(input, size, &size);\n\n assert(size == expected_size);\n\n for(size_t i = 0; i < size; i++) {\n\n assert(sorted3[i].type == expected[i].type);\n\n if(sorted3[i].type == INT_TYPE) {\n\n assert(sorted3[i].value.i == expected[i].value.i);\n\n } else {\n\n assert(strcmp(sorted3[i].value.s, expected[i].value.s) == 0);\n\n }\n\n }\n\n\n\n free(sorted);\n\n free(sorted2);\n\n free(sorted3);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\nmov %rsi,%rbp\npush %rbx\nsub $0x18,%rsp\nmov %rdx,(%rsp)\ntest %rsi,%rsi\nje 1860 \nshl $0x4,%rsi\nmov %rdi,%rbx\nmov %rdi,%rax\nxor %r14d,%r14d\nadd %rdi,%rsi\nxor %r13d,%r13d\njmp 171d \nnopw 0x0(%rax,%rax,1)\nadd $0x10,%rax\nadd $0x1,%r13\ncmp %rsi,%rax\nje 1730 \nmov (%rax),%edi\ntest %edi,%edi\nje 1710 \nadd $0x10,%rax\nadd $0x1,%r14\ncmp %rsi,%rax\njne 171d \nmov %r13,%rdi\nmov %rsi,0x8(%rsp)\nshl $0x4,%rdi\ncallq 10f0 \nmov %r14,%rdi\nshl $0x4,%rdi\nmov %rax,%r12\ncallq 10f0 \nmov 0x8(%rsp),%rsi\nxor %edx,%edx\nmov %rax,%r15\nxor %eax,%eax\njmp 177d \nxchg %ax,%ax\nmovdqu (%rbx),%xmm2\nmov %rax,%rcx\nadd $0x10,%rbx\nadd $0x1,%rax\nshl $0x4,%rcx\nmovups %xmm2,(%r12,%rcx,1)\ncmp %rsi,%rbx\nje 17a0 \nmov (%rbx),%ecx\ntest %ecx,%ecx\nje 1760 \nmovdqu (%rbx),%xmm3\nmov %rdx,%rcx\nadd $0x10,%rbx\nadd $0x1,%rdx\nshl $0x4,%rcx\nmovups %xmm3,(%r15,%rcx,1)\ncmp %rsi,%rbx\njne 177d \nlea -0x117(%rip),%rcx\nmov $0x10,%edx\nmov %r13,%rsi\nmov %r12,%rdi\ncallq 10b0 \nmov $0x10,%edx\nmov %r14,%rsi\nmov %r15,%rdi\nlea -0x119(%rip),%rcx\ncallq 10b0 \nmov %rbp,%rdi\nshl $0x4,%rdi\ncallq 10f0 \nmov %rax,%rbx\ntest %r13,%r13\nje 1803 \nmov %r13,%rax\nxor %edx,%edx\nshl $0x4,%rax\nnopl 0x0(%rax,%rax,1)\nmovdqu (%r12,%rdx,1),%xmm0\nmovups %xmm0,(%rbx,%rdx,1)\nadd $0x10,%rdx\ncmp %rdx,%rax\njne 17f0 \ntest %r14,%r14\nje 182d \nshl $0x4,%r13\nshl $0x4,%r14\nxor %edx,%edx\nadd %rbx,%r13\nnopl (%rax)\nmovdqu (%r15,%rdx,1),%xmm1\nmovups %xmm1,0x0(%r13,%rdx,1)\nadd $0x10,%rdx\ncmp %r14,%rdx\njne 1818 \nmov %r12,%rdi\ncallq 10a0 \nmov %r15,%rdi\ncallq 10a0 \nmov (%rsp),%rax\nmov %rbp,(%rax)\nadd $0x18,%rsp\nmov %rbx,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxor %edi,%edi\ncallq 10f0 \nxor %edi,%edi\nmov %rax,%r12\ncallq 10f0 \nmov $0x10,%edx\nxor %esi,%esi\nmov %r12,%rdi\nmov %rax,%r15\nlea -0x1f5(%rip),%rcx\ncallq 10b0 \nmov $0x10,%edx\nxor %esi,%esi\nmov %r15,%rdi\nlea -0x1eb(%rip),%rcx\ncallq 10b0 \nxor %edi,%edi\ncallq 10f0 \nmov %rax,%rbx\njmp 182d \nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\nmov r13, rsi\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_48], rdx\ntest rsi, rsi\njz loc_1850\nshl rsi, 4\nmov rbx, rdi\nmov rax, rdi\nxor r14d, r14d\nadd rsi, rdi\nxor ebp, ebp\njmp short loc_172D\nloc_1720:\nadd rax, 10h\nadd rbp, 1\ncmp rax, rsi\njz short loc_1740\nloc_172D:\nmov edi, [rax]\ntest edi, edi\njz short loc_1720\nadd rax, 10h\nadd r14, 1\ncmp rax, rsi\njnz short loc_172D\nloc_1740:\nmov rdi, rbp\nmov [rsp+48h+var_40], rsi\nshl rdi, 4; size\ncall _malloc\nmov rdi, r14\nshl rdi, 4; size\nmov r15, rax\ncall _malloc\nmov rsi, [rsp+48h+var_40]\nxor edx, edx\nmov r12, rax\nxor eax, eax\njmp short loc_178D\nloc_1770:\nmovdqu xmm0, xmmword ptr [rbx]\nmov rcx, rax\nadd rbx, 10h\nadd rax, 1\nshl rcx, 4\nmovups xmmword ptr [r15+rcx], xmm0\ncmp rsi, rbx\njz short loc_17B0\nloc_178D:\nmov ecx, [rbx]\ntest ecx, ecx\njz short loc_1770\nmovdqu xmm1, xmmword ptr [rbx]\nmov rcx, rdx\nadd rbx, 10h\nadd rdx, 1\nshl rcx, 4\nmovups xmmword ptr [r12+rcx], xmm1\ncmp rsi, rbx\njnz short loc_178D\nloc_17B0:\nlea rcx, compare_ints; compar\nmov edx, 10h; size\nmov rsi, rbp; nmemb\nmov rdi, r15; base\ncall _qsort\nmov edx, 10h; size\nmov rsi, r14; nmemb\nmov rdi, r12; base\nlea rcx, compare_strings; compar\ncall _qsort\nmov rdi, r13\nshl rdi, 4; size\ncall _malloc\nmov rbx, rax\ntest rbp, rbp\njz short loc_1804\nmov rdx, rbp\nmov rsi, r15; src\nmov rdi, rax; dest\nshl rdx, 4; n\ncall _memcpy\nloc_1804:\ntest r14, r14\njz short loc_1820\nshl rbp, 4\nmov rdx, r14\nmov rsi, r12; src\nlea rdi, [rbx+rbp]; dest\nshl rdx, 4; n\ncall _memcpy\nloc_1820:\nmov rdi, r15; ptr\ncall _free\nmov rdi, r12; ptr\ncall _free\nmov rax, [rsp+48h+var_48]\nmov [rax], r13\nadd rsp, 18h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1850:\nxor edi, edi; size\ncall _malloc\nxor edi, edi; size\nmov r15, rax\ncall _malloc\nmov edx, 10h; size\nxor esi, esi; nmemb\nmov rdi, r15; base\nmov r12, rax\nlea rcx, compare_ints; compar\ncall _qsort\nmov edx, 10h; size\nxor esi, esi; nmemb\nmov rdi, r12; base\nlea rcx, compare_strings; compar\ncall _qsort\nxor edi, edi; size\ncall _malloc\nmov rbx, rax\njmp short loc_1820", + "ida_pseudo": "char *__fastcall func0(const __m128i *a1, __int64 a2, _QWORD *a3)\n{\n const __m128i *v4; // rbx\n const __m128i *v5; // rax\n size_t v6; // r14\n const __m128i *v7; // rsi\n size_t v8; // rbp\n __m128i *v9; // r15\n __m128i *v10; // rax\n __int64 v11; // rdx\n __m128i *v12; // r12\n __int64 v13; // rax\n __m128i v14; // xmm0\n __int64 v15; // rcx\n __m128i v16; // xmm1\n __int64 v17; // rcx\n char *v18; // rax\n char *v19; // rbx\n\n if ( a2 )\n {\n v4 = a1;\n v5 = a1;\n v6 = 0LL;\n v7 = &a1[a2];\n v8 = 0LL;\n do\n {\n while ( !v5->m128i_i32[0] )\n {\n ++v5;\n ++v8;\n if ( v5 == v7 )\n goto LABEL_6;\n }\n ++v5;\n ++v6;\n }\n while ( v5 != v7 );\nLABEL_6:\n v9 = (__m128i *)malloc(16 * v8);\n v10 = (__m128i *)malloc(16 * v6);\n v11 = 0LL;\n v12 = v10;\n v13 = 0LL;\n do\n {\n while ( !v4->m128i_i32[0] )\n {\n v14 = _mm_loadu_si128(v4);\n v15 = v13;\n ++v4;\n ++v13;\n v9[v15] = v14;\n if ( v7 == v4 )\n goto LABEL_10;\n }\n v16 = _mm_loadu_si128(v4);\n v17 = v11;\n ++v4;\n ++v11;\n v12[v17] = v16;\n }\n while ( v7 != v4 );\nLABEL_10:\n qsort(v9, v8, 0x10uLL, compare_ints);\n qsort(v12, v6, 0x10uLL, compare_strings);\n v18 = (char *)malloc(16 * a2);\n v19 = v18;\n if ( v8 )\n memcpy(v18, v9, 16 * v8);\n if ( v6 )\n memcpy(&v19[16 * v8], v12, 16 * v6);\n }\n else\n {\n v9 = (__m128i *)malloc(0LL);\n v12 = (__m128i *)malloc(0LL);\n qsort(v9, 0LL, 0x10uLL, compare_ints);\n qsort(v12, 0LL, 0x10uLL, compare_strings);\n v19 = (char *)malloc(0LL);\n }\n free(v9);\n free(v12);\n *a3 = a2;\n return v19;\n}", + "ida_strip_asm": "sub_16E0:\nendbr64\npush r15\npush r14\npush r13\nmov r13, rsi\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_48], rdx\ntest rsi, rsi\njz loc_1850\nshl rsi, 4\nmov rbx, rdi\nmov rax, rdi\nxor r14d, r14d\nadd rsi, rdi\nxor ebp, ebp\njmp short loc_172D\nloc_1720:\nadd rax, 10h\nadd rbp, 1\ncmp rax, rsi\njz short loc_1740\nloc_172D:\nmov edi, [rax]\ntest edi, edi\njz short loc_1720\nadd rax, 10h\nadd r14, 1\ncmp rax, rsi\njnz short loc_172D\nloc_1740:\nmov rdi, rbp\nmov [rsp+48h+var_40], rsi\nshl rdi, 4; size\ncall _malloc\nmov rdi, r14\nshl rdi, 4; size\nmov r15, rax\ncall _malloc\nmov rsi, [rsp+48h+var_40]\nxor edx, edx\nmov r12, rax\nxor eax, eax\njmp short loc_178D\nloc_1770:\nmovdqu xmm0, xmmword ptr [rbx]\nmov rcx, rax\nadd rbx, 10h\nadd rax, 1\nshl rcx, 4\nmovups xmmword ptr [r15+rcx], xmm0\ncmp rsi, rbx\njz short loc_17B0\nloc_178D:\nmov ecx, [rbx]\ntest ecx, ecx\njz short loc_1770\nmovdqu xmm1, xmmword ptr [rbx]\nmov rcx, rdx\nadd rbx, 10h\nadd rdx, 1\nshl rcx, 4\nmovups xmmword ptr [r12+rcx], xmm1\ncmp rsi, rbx\njnz short loc_178D\nloc_17B0:\nlea rcx, compar; compar\nmov edx, 10h; size\nmov rsi, rbp; nmemb\nmov rdi, r15; base\ncall _qsort\nmov edx, 10h; size\nmov rsi, r14; nmemb\nmov rdi, r12; base\nlea rcx, sub_16C0; compar\ncall _qsort\nmov rdi, r13\nshl rdi, 4; size\ncall _malloc\nmov rbx, rax\ntest rbp, rbp\njz short loc_1804\nmov rdx, rbp\nmov rsi, r15; src\nmov rdi, rax; dest\nshl rdx, 4; n\ncall _memcpy\nloc_1804:\ntest r14, r14\njz short loc_1820\nshl rbp, 4\nmov rdx, r14\nmov rsi, r12; src\nlea rdi, [rbx+rbp]; dest\nshl rdx, 4; n\ncall _memcpy\nloc_1820:\nmov rdi, r15; ptr\ncall _free\nmov rdi, r12; ptr\ncall _free\nmov rax, [rsp+48h+var_48]\nmov [rax], r13\nadd rsp, 18h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1850:\nxor edi, edi; size\ncall _malloc\nxor edi, edi; size\nmov r15, rax\ncall _malloc\nmov edx, 10h; size\nxor esi, esi; nmemb\nmov rdi, r15; base\nmov r12, rax\nlea rcx, compar; compar\ncall _qsort\nmov edx, 10h; size\nxor esi, esi; nmemb\nmov rdi, r12; base\nlea rcx, sub_16C0; compar\ncall _qsort\nxor edi, edi; size\ncall _malloc\nmov rbx, rax\njmp short loc_1820", + "ida_strip_pseudo": "char *__fastcall sub_16E0(const __m128i *a1, __int64 a2, _QWORD *a3)\n{\n const __m128i *v4; // rbx\n const __m128i *v5; // rax\n size_t v6; // r14\n const __m128i *v7; // rsi\n size_t v8; // rbp\n __m128i *v9; // r15\n __m128i *v10; // rax\n __int64 v11; // rdx\n __m128i *v12; // r12\n __int64 v13; // rax\n __m128i v14; // xmm0\n __int64 v15; // rcx\n __m128i v16; // xmm1\n __int64 v17; // rcx\n char *v18; // rax\n char *v19; // rbx\n\n if ( a2 )\n {\n v4 = a1;\n v5 = a1;\n v6 = 0LL;\n v7 = &a1[a2];\n v8 = 0LL;\n do\n {\n while ( !v5->m128i_i32[0] )\n {\n ++v5;\n ++v8;\n if ( v5 == v7 )\n goto LABEL_6;\n }\n ++v5;\n ++v6;\n }\n while ( v5 != v7 );\nLABEL_6:\n v9 = (__m128i *)malloc(16 * v8);\n v10 = (__m128i *)malloc(16 * v6);\n v11 = 0LL;\n v12 = v10;\n v13 = 0LL;\n do\n {\n while ( !v4->m128i_i32[0] )\n {\n v14 = _mm_loadu_si128(v4);\n v15 = v13;\n ++v4;\n ++v13;\n v9[v15] = v14;\n if ( v7 == v4 )\n goto LABEL_10;\n }\n v16 = _mm_loadu_si128(v4);\n v17 = v11;\n ++v4;\n ++v11;\n v12[v17] = v16;\n }\n while ( v7 != v4 );\nLABEL_10:\n qsort(v9, v8, 0x10uLL, compar);\n qsort(v12, v6, 0x10uLL, sub_16C0);\n v18 = (char *)malloc(16 * a2);\n v19 = v18;\n if ( v8 )\n memcpy(v18, v9, 16 * v8);\n if ( v6 )\n memcpy(&v19[16 * v8], v12, 16 * v6);\n }\n else\n {\n v9 = (__m128i *)malloc(0LL);\n v12 = (__m128i *)malloc(0LL);\n qsort(v9, 0LL, 0x10uLL, compar);\n qsort(v12, 0LL, 0x10uLL, sub_16C0);\n v19 = (char *)malloc(0LL);\n }\n free(v9);\n free(v12);\n *a3 = a2;\n return v19;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_16E0(const __m128i *a1, long long a2, uint64_t *a3) {\n const __m128i *v4;\n const __m128i *v5;\n unsigned int v6;\n const __m128i *v7;\n unsigned int v8;\n __m128i *v9;\n __m128i *v10;\n long long v11;\n __m128i *v12;\n long long v13;\n __m128i v14;\n long long v15;\n __m128i v16;\n long long v17;\n char *v18;\n char *v19;\n if (a2) {\n v4 = a1;\n v5 = a1;\n v6 = 0LL;\n v7 = &a1[a2];\n v8 = 0LL;\n do {\n while (!v5->m128i_i32[0]) {\n ++v5;\n ++v8;\n if (v5 == v7) goto LABEL_6;\n }\n ++v5;\n ++v6;\n } while (v5 != v7);\n LABEL_6:\n v9 = (__m128i *)malloc(16 * v8);\n v10 = (__m128i *)malloc(16 * v6);\n v11 = 0LL;\n v12 = v10;\n v13 = 0LL;\n do {\n while (!v4->m128i_i32[0]) {\n v14 = _mm_loadu_si128(v4);\n v15 = v13;\n ++v4;\n ++v13;\n v9[v15] = v14;\n if (v7 == v4) goto LABEL_10;\n }\n v16 = _mm_loadu_si128(v4);\n v17 = v11;\n ++v4;\n ++v11;\n v12[v17] = v16;\n } while (v7 != v4);\n LABEL_10:\n qsort(v9, v8, 16uLL, compar);\n qsort(v12, v6, 16uLL, sub_16C0);\n v18 = (char *)malloc(16 * a2);\n v19 = v18;\n if (v8) memcpy(v18, v9, 16 * v8);\n if (v6) memcpy(&v19[16 * v8], v12, 16 * v6);\n } else {\n v9 = (__m128i *)malloc(0LL);\n v12 = (__m128i *)malloc(0LL);\n qsort(v9, 0LL, 16uLL, compar);\n qsort(v12, 0LL, 16uLL, sub_16C0);\n v19 = (char *)malloc(0LL);\n }\n free(v9);\n free(v12);\n *a3 = a2;\n return v19;\n}", + "ida_pseudo_norm": "char *func0(const __m128i *a1, long long a2, uint64_t *a3) {\n const __m128i *v4;\n const __m128i *v5;\n unsigned int v6;\n const __m128i *v7;\n unsigned int v8;\n __m128i *v9;\n __m128i *v10;\n long long v11;\n __m128i *v12;\n long long v13;\n __m128i v14;\n long long v15;\n __m128i v16;\n long long v17;\n char *v18;\n char *v19;\n if (a2) {\n v4 = a1;\n v5 = a1;\n v6 = 0LL;\n v7 = &a1[a2];\n v8 = 0LL;\n do {\n while (!v5->m128i_i32[0]) {\n ++v5;\n ++v8;\n if (v5 == v7) goto LABEL_6;\n }\n ++v5;\n ++v6;\n } while (v5 != v7);\n LABEL_6:\n v9 = (__m128i *)malloc(16 * v8);\n v10 = (__m128i *)malloc(16 * v6);\n v11 = 0LL;\n v12 = v10;\n v13 = 0LL;\n do {\n while (!v4->m128i_i32[0]) {\n v14 = _mm_loadu_si128(v4);\n v15 = v13;\n ++v4;\n ++v13;\n v9[v15] = v14;\n if (v7 == v4) goto LABEL_10;\n }\n v16 = _mm_loadu_si128(v4);\n v17 = v11;\n ++v4;\n ++v11;\n v12[v17] = v16;\n } while (v7 != v4);\n LABEL_10:\n qsort(v9, v8, 16uLL, compare_ints);\n qsort(v12, v6, 16uLL, compare_strings);\n v18 = (char *)malloc(16 * a2);\n v19 = v18;\n if (v8) memcpy(v18, v9, 16 * v8);\n if (v6) memcpy(&v19[16 * v8], v12, 16 * v6);\n } else {\n v9 = (__m128i *)malloc(0LL);\n v12 = (__m128i *)malloc(0LL);\n qsort(v9, 0LL, 16uLL, compare_ints);\n qsort(v12, 0LL, 16uLL, compare_strings);\n v19 = (char *)malloc(0LL);\n }\n free(v9);\n free(v12);\n *a3 = a2;\n return v19;\n}" + }, + { + "index": 37, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef enum { INT_TYPE, STRING_TYPE } ElementType;\n\n\n\ntypedef struct {\n\n ElementType type;\n\n union {\n\n int i;\n\n char* s;\n\n } value;\n\n} Mixed;\n\n\n\nint compare_ints(const void* a, const void* b) {\n\n int int_a = ((Mixed*)a)->value.i;\n\n int int_b = ((Mixed*)b)->value.i;\n\n return (int_a > int_b) - (int_a < int_b);\n\n}\n\n\n\nint compare_strings(const void* a, const void* b) {\n\n char* str_a = ((Mixed*)a)->value.s;\n\n char* str_b = ((Mixed*)b)->value.s;\n\n return strcmp(str_a, str_b);\n\n}\n\n\n\n", + "func": "Mixed* func0(Mixed* mixed_list, size_t size, size_t* sorted_size) {\n size_t int_count = 0, str_count = 0;\n for (size_t i = 0; i < size; i++) {\n if (mixed_list[i].type == INT_TYPE)\n int_count++;\n else\n str_count++;\n }\n Mixed* int_part = malloc(int_count * sizeof(Mixed));\n Mixed* str_part = malloc(str_count * sizeof(Mixed));\n size_t int_idx = 0, str_idx = 0;\n for (size_t i = 0; i < size; i++) {\n if (mixed_list[i].type == INT_TYPE) {\n int_part[int_idx++] = mixed_list[i];\n } else {\n str_part[str_idx++] = mixed_list[i];\n }\n }\n qsort(int_part, int_count, sizeof(Mixed), compare_ints);\n qsort(str_part, str_count, sizeof(Mixed), compare_strings);\n Mixed* sorted = malloc(size * sizeof(Mixed));\n for (size_t i = 0; i < int_count; i++) {\n sorted[i] = int_part[i];\n }\n for (size_t i = 0; i < str_count; i++) {\n sorted[int_count + i] = str_part[i];\n }\n free(int_part);\n free(str_part);\n *sorted_size = size;\n return sorted;\n}", + "test": "int main() {\n\n Mixed input[] = {\n\n {INT_TYPE, .value.i = 19},\n\n {STRING_TYPE, .value.s = \"red\"},\n\n {INT_TYPE, .value.i = 12},\n\n {STRING_TYPE, .value.s = \"green\"},\n\n {STRING_TYPE, .value.s = \"blue\"},\n\n {INT_TYPE, .value.i = 10},\n\n {STRING_TYPE, .value.s = \"white\"},\n\n {STRING_TYPE, .value.s = \"green\"},\n\n {INT_TYPE, .value.i = 1}\n\n };\n\n size_t size = sizeof(input) / sizeof(input[0]);\n\n\n\n Mixed* sorted = func0(input, size, &size);\n\n\n\n Mixed expected[] = {\n\n {INT_TYPE, .value.i = 1},\n\n {INT_TYPE, .value.i = 10},\n\n {INT_TYPE, .value.i = 12},\n\n {INT_TYPE, .value.i = 19},\n\n {STRING_TYPE, .value.s = \"blue\"},\n\n {STRING_TYPE, .value.s = \"green\"},\n\n {STRING_TYPE, .value.s = \"green\"},\n\n {STRING_TYPE, .value.s = \"red\"},\n\n {STRING_TYPE, .value.s = \"white\"}\n\n };\n\n size_t expected_size = sizeof(expected) / sizeof(expected[0]);\n\n\n\n assert(size == expected_size);\n\n for(size_t i = 0; i < size; i++) {\n\n assert(sorted[i].type == expected[i].type);\n\n if(sorted[i].type == INT_TYPE) {\n\n assert(sorted[i].value.i == expected[i].value.i);\n\n } else {\n\n assert(strcmp(sorted[i].value.s, expected[i].value.s) == 0);\n\n }\n\n }\n\n\n\n // Repeat the assertions\n\n Mixed* sorted2 = func0(input, size, &size);\n\n assert(size == expected_size);\n\n for(size_t i = 0; i < size; i++) {\n\n assert(sorted2[i].type == expected[i].type);\n\n if(sorted2[i].type == INT_TYPE) {\n\n assert(sorted2[i].value.i == expected[i].value.i);\n\n } else {\n\n assert(strcmp(sorted2[i].value.s, expected[i].value.s) == 0);\n\n }\n\n }\n\n\n\n Mixed* sorted3 = func0(input, size, &size);\n\n assert(size == expected_size);\n\n for(size_t i = 0; i < size; i++) {\n\n assert(sorted3[i].type == expected[i].type);\n\n if(sorted3[i].type == INT_TYPE) {\n\n assert(sorted3[i].value.i == expected[i].value.i);\n\n } else {\n\n assert(strcmp(sorted3[i].value.s, expected[i].value.s) == 0);\n\n }\n\n }\n\n\n\n free(sorted);\n\n free(sorted2);\n\n free(sorted3);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\nmov %rsi,%rbp\npush %rbx\nsub $0x18,%rsp\nmov %rdx,0x8(%rsp)\ntest %rsi,%rsi\nje 1cf0 \nlea -0x1(%rsi),%rcx\nmov %rdi,%rbx\ncmp $0x3,%rcx\njbe 1d3f \nmov %rcx,%rdx\npxor %xmm2,%xmm2\npxor %xmm1,%xmm1\nmov %rdi,%rax\nshr %rdx\nmovdqa 0x783(%rip),%xmm6\nmovdqa 0x78b(%rip),%xmm5\nmovdqa %xmm2,%xmm3\nshl $0x5,%rdx\nadd %rdi,%rdx\nmovdqu (%rax),%xmm0\nmovdqu 0x10(%rax),%xmm7\nmovdqa %xmm6,%xmm4\nadd $0x20,%rax\nshufps $0x0,%xmm7,%xmm0\npcmpeqd %xmm1,%xmm0\npand %xmm0,%xmm4\npandn %xmm5,%xmm0\npor %xmm4,%xmm0\nmovdqa %xmm0,%xmm4\npunpckhdq %xmm1,%xmm0\npunpckldq %xmm1,%xmm4\npaddq %xmm0,%xmm2\npaddq %xmm4,%xmm3\ncmp %rdx,%rax\njne 1ac0 \nmovq %xmm3,%r13\nmovq %xmm2,%rdx\npsrldq $0x8,%xmm3\npsrldq $0x8,%xmm2\nmovq %xmm2,%rax\nmovq %xmm3,%r14\nadd %rdx,%r13\nadd %rax,%r14\nmov %rcx,%rax\nand $0xfffffffffffffffe,%rax\nmov %rax,%rdx\nshl $0x4,%rdx\nmov (%rbx,%rdx,1),%r10d\ntest %r10d,%r10d\nje 1cb0 \nadd $0x1,%r13\nlea 0x1(%rax),%rdx\ncmp %rbp,%rdx\njae 1b99 \nshl $0x4,%rdx\nmov (%rbx,%rdx,1),%r9d\ntest %r9d,%r9d\njne 1cc0 \nadd $0x1,%r14\nlea 0x2(%rax),%rdx\ncmp %rbp,%rdx\njae 1b99 \nshl $0x4,%rdx\nmov (%rbx,%rdx,1),%r8d\ntest %r8d,%r8d\njne 1cd0 \nadd $0x1,%r14\nadd $0x3,%rax\ncmp %rax,%rbp\njbe 1b99 \nshl $0x4,%rax\nmov (%rbx,%rax,1),%edi\ntest %edi,%edi\nje 1ce0 \nadd $0x1,%r13\nmov %r14,%rdi\nshl $0x4,%rdi\ncallq 1110 \nmov %r13,%rdi\nshl $0x4,%rdi\nmov %rax,%r12\ncallq 1110 \nmov %rbp,%rcx\nmov %rbx,%rdi\nxor %edx,%edx\nshl $0x4,%rcx\nmov %rax,%r15\nxor %eax,%eax\nadd %rbx,%rcx\njmp 1bed \nnopw 0x0(%rax,%rax,1)\nmovdqu (%rdi),%xmm5\nmov %rax,%rsi\nadd $0x10,%rdi\nadd $0x1,%rax\nshl $0x4,%rsi\nmovups %xmm5,(%r12,%rsi,1)\ncmp %rcx,%rdi\nje 1c10 \nmov (%rdi),%esi\ntest %esi,%esi\nje 1bd0 \nmovdqu (%rdi),%xmm6\nmov %rdx,%rsi\nadd $0x10,%rdi\nadd $0x1,%rdx\nshl $0x4,%rsi\nmovups %xmm6,(%r15,%rsi,1)\ncmp %rcx,%rdi\njne 1bed \nlea -0x1f7(%rip),%rcx\nmov $0x10,%edx\nmov %r14,%rsi\nmov %r12,%rdi\ncallq 10c0 \nmov $0x10,%edx\nmov %r13,%rsi\nmov %r15,%rdi\nlea -0x1f9(%rip),%rcx\ncallq 10c0 \nmov %rbp,%rdi\nshl $0x4,%rdi\ncallq 1110 \nmov %rax,%rbx\ntest %r14,%r14\nje 1c64 \nmov %r14,%rdx\nmov %r12,%rsi\nmov %rax,%rdi\nshl $0x4,%rdx\ncallq 1100 \ntest %r13,%r13\nje 1c83 \nmov %r14,%rax\nmov %r13,%rdx\nmov %r15,%rsi\nshl $0x4,%rax\nshl $0x4,%rdx\nlea (%rbx,%rax,1),%rdi\ncallq 1100 \nmov %r12,%rdi\ncallq 10b0 \nmov %r15,%rdi\ncallq 10b0 \nmov 0x8(%rsp),%rax\nmov %rbp,(%rax)\nadd $0x18,%rsp\nmov %rbx,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl (%rax)\nadd $0x1,%r14\njmpq 1b41 \nnopl 0x0(%rax)\nadd $0x1,%r13\njmpq 1b5f \nnopl 0x0(%rax)\nadd $0x1,%r13\njmpq 1b7d \nnopl 0x0(%rax)\nadd $0x1,%r14\njmpq 1b99 \nnopl 0x0(%rax)\nxor %edi,%edi\ncallq 1110 \nxor %edi,%edi\nmov %rax,%r12\ncallq 1110 \nmov $0x10,%edx\nxor %esi,%esi\nmov %r12,%rdi\nmov %rax,%r15\nlea -0x2f5(%rip),%rcx\ncallq 10c0 \nmov $0x10,%edx\nxor %esi,%esi\nmov %r15,%rdi\nlea -0x2eb(%rip),%rcx\ncallq 10c0 \nxor %edi,%edi\ncallq 1110 \nmov %rax,%rbx\njmpq 1c83 \nxor %eax,%eax\nxor %r13d,%r13d\nxor %r14d,%r14d\njmpq 1b29 \nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rsi\nsub rsp, 18h\nmov [rsp+48h+var_40], rdx\ntest rsi, rsi\njz loc_1BE0\nlea rdx, [rsi-1]\nmov r15, rdi\ncmp rdx, 9\njbe loc_1C2F\nmov rcx, rdx\npxor xmm4, xmm4\npxor xmm5, xmm5\nmov rax, rdi\nshr rcx, 1\nmovdqa xmm7, cs:xmmword_2210\nmovdqa xmm6, cs:xmmword_2220\nmovdqa xmm3, xmm4\nshl rcx, 5\nadd rcx, rdi\nloc_1890:\nmovdqu xmm1, xmmword ptr [rax+10h]\nmovdqu xmm0, xmmword ptr [rax]\nmovdqa xmm2, xmm5\nmovdqa xmm8, xmm7\nadd rax, 20h ; ' '\nshufps xmm0, xmm1, 0\npcmpeqd xmm0, xmm5\npcmpgtd xmm2, xmm0\nmovdqa xmm1, xmm0\npunpckldq xmm1, xmm2\npunpckhdq xmm0, xmm2\nmovdqa xmm2, xmm7\npand xmm8, xmm1\npand xmm2, xmm0\npandn xmm1, xmm6\npandn xmm0, xmm6\npor xmm1, xmm8\npor xmm0, xmm2\npaddq xmm3, xmm1\npaddq xmm4, xmm0\ncmp rax, rcx\njnz short loc_1890\npaddq xmm3, xmm4\nmov rax, rdx\nmovhlps xmm5, xmm3\nmovq rbp, xmm3\nand rax, 0FFFFFFFFFFFFFFFEh\nmovq r14, xmm5\nloc_1901:\nmov rdx, rax\nshl rdx, 4\nmov r8d, [r15+rdx]\ntest r8d, r8d\njz loc_1B40\nadd rbp, 1\nloc_1919:\nlea rcx, [rax+1]\ncmp rcx, rbx\njnb loc_1A28\nmov edi, [r15+rdx+10h]\ntest edi, edi\njnz loc_1B50\nadd r14, 1\nloc_1937:\nlea rcx, [rax+2]\ncmp rcx, rbx\njnb loc_1A28\nmov esi, [r15+rdx+20h]\ntest esi, esi\njnz loc_1B60\nadd r14, 1\nloc_1955:\nlea rcx, [rax+3]\ncmp rcx, rbx\njnb loc_1A28\nmov ecx, [r15+rdx+30h]\ntest ecx, ecx\njnz loc_1B70\nadd r14, 1\nloc_1973:\nlea rcx, [rax+4]\ncmp rcx, rbx\njnb loc_1A28\nmov r13d, [r15+rdx+40h]\ntest r13d, r13d\njnz loc_1B80\nadd r14, 1\nloc_1992:\nlea rcx, [rax+5]\ncmp rcx, rbx\njnb loc_1A28\nmov r12d, [r15+rdx+50h]\ntest r12d, r12d\njnz loc_1B90\nadd r14, 1\nloc_19B1:\nlea rcx, [rax+6]\ncmp rcx, rbx\njnb short loc_1A28\nmov r11d, [r15+rdx+60h]\ntest r11d, r11d\njnz loc_1BA0\nadd r14, 1\nloc_19CC:\nlea rcx, [rax+7]\ncmp rcx, rbx\njnb short loc_1A28\nmov r10d, [r15+rdx+70h]\ntest r10d, r10d\njz loc_1BB0\nadd rbp, 1\nloc_19E7:\nlea rcx, [rax+8]\ncmp rcx, rbx\njnb short loc_1A28\nmov r9d, [r15+rdx+80h]\ntest r9d, r9d\njnz loc_1BC0\nadd r14, 1\nloc_1A05:\nadd rax, 9\ncmp rax, rbx\njnb short loc_1A28\nmov r8d, [r15+rdx+90h]\ntest r8d, r8d\njz loc_1BD0\nadd rbp, 1\nnop dword ptr [rax+rax+00h]\nloc_1A28:\nmov rdi, r14\nshl rdi, 4; size\ncall _malloc\nmov rdi, rbp\nshl rdi, 4; size\nmov r13, rax\ncall _malloc\nmov rsi, rbx\nxor ecx, ecx\nxor edx, edx\nshl rsi, 4\nmov r12, rax\nmov rax, r15\nadd rsi, r15\njmp short loc_1A7E\nloc_1A60:\nmovdqu xmm4, xmmword ptr [rax]\nmov rdi, rdx\nadd rax, 10h\nadd rdx, 1\nshl rdi, 4\nmovups xmmword ptr [r13+rdi+0], xmm4\ncmp rsi, rax\njz short loc_1AA1\nloc_1A7E:\nmov edi, [rax]\ntest edi, edi\njz short loc_1A60\nmovdqu xmm3, xmmword ptr [rax]\nmov rdi, rcx\nadd rax, 10h\nadd rcx, 1\nshl rdi, 4\nmovups xmmword ptr [r12+rdi], xmm3\ncmp rsi, rax\njnz short loc_1A7E\nloc_1AA1:\nlea rcx, compare_ints; compar\nmov edx, 10h; size\nmov rsi, r14; nmemb\nmov rdi, r13; base\ncall _qsort\nmov edx, 10h; size\nmov rsi, rbp; nmemb\nmov rdi, r12; base\nlea rcx, compare_strings; compar\ncall _qsort\nmov rdi, rbx\nshl rdi, 4; size\ncall _malloc\nmov r15, rax\ntest r14, r14\njz short loc_1AF5\nmov rdx, r14\nmov rsi, r13; src\nmov rdi, rax; dest\nshl rdx, 4; n\ncall _memcpy\nloc_1AF5:\ntest rbp, rbp\njz short loc_1B13\nmov rdi, r14\nmov rdx, rbp\nmov rsi, r12; src\nshl rdi, 4\nshl rdx, 4; n\nadd rdi, r15; dest\ncall _memcpy\nloc_1B13:\nmov rdi, r13; ptr\ncall _free\nmov rdi, r12; ptr\ncall _free\nmov rax, [rsp+48h+var_40]\nmov [rax], rbx\nadd rsp, 18h\nmov rax, r15\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1B40:\nadd r14, 1\njmp loc_1919\nloc_1B50:\nadd rbp, 1\njmp loc_1937\nloc_1B60:\nadd rbp, 1\njmp loc_1955\nloc_1B70:\nadd rbp, 1\njmp loc_1973\nloc_1B80:\nadd rbp, 1\njmp loc_1992\nloc_1B90:\nadd rbp, 1\njmp loc_19B1\nloc_1BA0:\nadd rbp, 1\njmp loc_19CC\nloc_1BB0:\nadd r14, 1\njmp loc_19E7\nloc_1BC0:\nadd rbp, 1\njmp loc_1A05\nloc_1BD0:\nadd r14, 1\njmp loc_1A28\nloc_1BE0:\nxor edi, edi; size\ncall _malloc\nxor edi, edi; size\nmov r13, rax\ncall _malloc\nmov edx, 10h; size\nxor esi, esi; nmemb\nmov rdi, r13; base\nmov r12, rax\nlea rcx, compare_ints; compar\ncall _qsort\nmov edx, 10h; size\nxor esi, esi; nmemb\nmov rdi, r12; base\nlea rcx, compare_strings; compar\ncall _qsort\nxor edi, edi; size\ncall _malloc\nmov r15, rax\njmp loc_1B13\nloc_1C2F:\nxor eax, eax\nxor ebp, ebp\nxor r14d, r14d\njmp loc_1901", + "ida_pseudo": "char *__fastcall func0(const __m128i *a1, unsigned __int64 a2, unsigned __int64 *a3)\n{\n unsigned __int64 v4; // rdx\n __m128i v5; // xmm4\n const __m128i *v6; // rax\n __m128i si128; // xmm7\n __m128i v8; // xmm6\n __m128i v9; // xmm3\n __m128 v10; // xmm1\n __m128 v11; // xmm0\n __m128i v12; // xmm0\n __m128i v13; // xmm2\n __m128i v14; // xmm1\n __m128i v15; // xmm0\n __m128 v16; // xmm3\n size_t v17; // rbp\n unsigned __int64 v18; // rax\n size_t v19; // r14\n __int64 v20; // rdx\n __m128i *v21; // r13\n __m128i *v22; // rax\n __int64 v23; // rcx\n __int64 v24; // rdx\n __m128i *v25; // r12\n const __m128i *v26; // rax\n const __m128i *v27; // rsi\n __m128i v28; // xmm4\n __int64 v29; // rdi\n __m128i v30; // xmm3\n __int64 v31; // rdi\n char *v32; // rax\n char *v33; // r15\n\n if ( a2 )\n {\n v4 = a2 - 1;\n if ( a2 - 1 <= 9 )\n {\n v18 = 0LL;\n v17 = 0LL;\n v19 = 0LL;\n }\n else\n {\n v5 = 0LL;\n v6 = a1;\n si128 = _mm_load_si128((const __m128i *)&xmmword_2210);\n v8 = _mm_load_si128((const __m128i *)&xmmword_2220);\n v9 = 0LL;\n do\n {\n v10 = (__m128)_mm_loadu_si128(v6 + 1);\n v11 = (__m128)_mm_loadu_si128(v6);\n v6 += 2;\n v12 = _mm_cmpeq_epi32((__m128i)_mm_shuffle_ps(v11, v10, 0), (__m128i)0LL);\n v13 = _mm_cmpgt_epi32((__m128i)0LL, v12);\n v14 = _mm_unpacklo_epi32(v12, v13);\n v15 = _mm_unpackhi_epi32(v12, v13);\n v9 = _mm_add_epi64(v9, _mm_or_si128(_mm_andnot_si128(v14, v8), _mm_and_si128(si128, v14)));\n v5 = _mm_add_epi64(v5, _mm_or_si128(_mm_andnot_si128(v15, v8), _mm_and_si128(si128, v15)));\n }\n while ( v6 != &a1[2 * (v4 >> 1)] );\n v16 = (__m128)_mm_add_epi64(v9, v5);\n v17 = v16.m128_u64[0];\n v18 = v4 & 0xFFFFFFFFFFFFFFFELL;\n v19 = _mm_movehl_ps((__m128)0LL, v16).m128_u64[0];\n }\n v20 = v18;\n if ( a1[v18].m128i_i32[0] )\n ++v17;\n else\n ++v19;\n if ( v18 + 1 < a2 )\n {\n if ( a1[v20 + 1].m128i_i32[0] )\n ++v17;\n else\n ++v19;\n if ( v18 + 2 < a2 )\n {\n if ( a1[v20 + 2].m128i_i32[0] )\n ++v17;\n else\n ++v19;\n if ( v18 + 3 < a2 )\n {\n if ( a1[v20 + 3].m128i_i32[0] )\n ++v17;\n else\n ++v19;\n if ( v18 + 4 < a2 )\n {\n if ( a1[v20 + 4].m128i_i32[0] )\n ++v17;\n else\n ++v19;\n if ( v18 + 5 < a2 )\n {\n if ( a1[v20 + 5].m128i_i32[0] )\n ++v17;\n else\n ++v19;\n if ( v18 + 6 < a2 )\n {\n if ( a1[v20 + 6].m128i_i32[0] )\n ++v17;\n else\n ++v19;\n if ( v18 + 7 < a2 )\n {\n if ( a1[v20 + 7].m128i_i32[0] )\n ++v17;\n else\n ++v19;\n if ( v18 + 8 < a2 )\n {\n if ( a1[v20 + 8].m128i_i32[0] )\n ++v17;\n else\n ++v19;\n if ( v18 + 9 < a2 )\n {\n if ( a1[v20 + 9].m128i_i32[0] )\n ++v17;\n else\n ++v19;\n }\n }\n }\n }\n }\n }\n }\n }\n }\n v21 = (__m128i *)malloc(16 * v19);\n v22 = (__m128i *)malloc(16 * v17);\n v23 = 0LL;\n v24 = 0LL;\n v25 = v22;\n v26 = a1;\n v27 = &a1[a2];\n do\n {\n while ( !v26->m128i_i32[0] )\n {\n v28 = _mm_loadu_si128(v26);\n v29 = v24;\n ++v26;\n ++v24;\n v21[v29] = v28;\n if ( v27 == v26 )\n goto LABEL_39;\n }\n v30 = _mm_loadu_si128(v26);\n v31 = v23;\n ++v26;\n ++v23;\n v25[v31] = v30;\n }\n while ( v27 != v26 );\nLABEL_39:\n qsort(v21, v19, 0x10uLL, compare_ints);\n qsort(v25, v17, 0x10uLL, compare_strings);\n v32 = (char *)malloc(16 * a2);\n v33 = v32;\n if ( v19 )\n memcpy(v32, v21, 16 * v19);\n if ( v17 )\n memcpy(&v33[16 * v19], v25, 16 * v17);\n }\n else\n {\n v21 = (__m128i *)malloc(0LL);\n v25 = (__m128i *)malloc(0LL);\n qsort(v21, 0LL, 0x10uLL, compare_ints);\n qsort(v25, 0LL, 0x10uLL, compare_strings);\n v33 = (char *)malloc(0LL);\n }\n free(v21);\n free(v25);\n *a3 = a2;\n return v33;\n}", + "ida_strip_asm": "sub_1830:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rsi\nsub rsp, 18h\nmov [rsp+48h+var_40], rdx\ntest rsi, rsi\njz loc_1BE0\nlea rdx, [rsi-1]\nmov r15, rdi\ncmp rdx, 9\njbe loc_1C2F\nmov rcx, rdx\npxor xmm4, xmm4\npxor xmm5, xmm5\nmov rax, rdi\nshr rcx, 1\nmovdqa xmm7, cs:xmmword_2210\nmovdqa xmm6, cs:xmmword_2220\nmovdqa xmm3, xmm4\nshl rcx, 5\nadd rcx, rdi\nloc_1890:\nmovdqu xmm1, xmmword ptr [rax+10h]\nmovdqu xmm0, xmmword ptr [rax]\nmovdqa xmm2, xmm5\nmovdqa xmm8, xmm7\nadd rax, 20h ; ' '\nshufps xmm0, xmm1, 0\npcmpeqd xmm0, xmm5\npcmpgtd xmm2, xmm0\nmovdqa xmm1, xmm0\npunpckldq xmm1, xmm2\npunpckhdq xmm0, xmm2\nmovdqa xmm2, xmm7\npand xmm8, xmm1\npand xmm2, xmm0\npandn xmm1, xmm6\npandn xmm0, xmm6\npor xmm1, xmm8\npor xmm0, xmm2\npaddq xmm3, xmm1\npaddq xmm4, xmm0\ncmp rax, rcx\njnz short loc_1890\npaddq xmm3, xmm4\nmov rax, rdx\nmovhlps xmm5, xmm3\nmovq rbp, xmm3\nand rax, 0FFFFFFFFFFFFFFFEh\nmovq r14, xmm5\nloc_1901:\nmov rdx, rax\nshl rdx, 4\nmov r8d, [r15+rdx]\ntest r8d, r8d\njz loc_1B40\nadd rbp, 1\nloc_1919:\nlea rcx, [rax+1]\ncmp rcx, rbx\njnb loc_1A28\nmov edi, [r15+rdx+10h]\ntest edi, edi\njnz loc_1B50\nadd r14, 1\nloc_1937:\nlea rcx, [rax+2]\ncmp rcx, rbx\njnb loc_1A28\nmov esi, [r15+rdx+20h]\ntest esi, esi\njnz loc_1B60\nadd r14, 1\nloc_1955:\nlea rcx, [rax+3]\ncmp rcx, rbx\njnb loc_1A28\nmov ecx, [r15+rdx+30h]\ntest ecx, ecx\njnz loc_1B70\nadd r14, 1\nloc_1973:\nlea rcx, [rax+4]\ncmp rcx, rbx\njnb loc_1A28\nmov r13d, [r15+rdx+40h]\ntest r13d, r13d\njnz loc_1B80\nadd r14, 1\nloc_1992:\nlea rcx, [rax+5]\ncmp rcx, rbx\njnb loc_1A28\nmov r12d, [r15+rdx+50h]\ntest r12d, r12d\njnz loc_1B90\nadd r14, 1\nloc_19B1:\nlea rcx, [rax+6]\ncmp rcx, rbx\njnb short loc_1A28\nmov r11d, [r15+rdx+60h]\ntest r11d, r11d\njnz loc_1BA0\nadd r14, 1\nloc_19CC:\nlea rcx, [rax+7]\ncmp rcx, rbx\njnb short loc_1A28\nmov r10d, [r15+rdx+70h]\ntest r10d, r10d\njz loc_1BB0\nadd rbp, 1\nloc_19E7:\nlea rcx, [rax+8]\ncmp rcx, rbx\njnb short loc_1A28\nmov r9d, [r15+rdx+80h]\ntest r9d, r9d\njnz loc_1BC0\nadd r14, 1\nloc_1A05:\nadd rax, 9\ncmp rax, rbx\njnb short loc_1A28\nmov r8d, [r15+rdx+90h]\ntest r8d, r8d\njz loc_1BD0\nadd rbp, 1\nnop dword ptr [rax+rax+00h]\nloc_1A28:\nmov rdi, r14\nshl rdi, 4; size\ncall _malloc\nmov rdi, rbp\nshl rdi, 4; size\nmov r13, rax\ncall _malloc\nmov rsi, rbx\nxor ecx, ecx\nxor edx, edx\nshl rsi, 4\nmov r12, rax\nmov rax, r15\nadd rsi, r15\njmp short loc_1A7E\nloc_1A60:\nmovdqu xmm4, xmmword ptr [rax]\nmov rdi, rdx\nadd rax, 10h\nadd rdx, 1\nshl rdi, 4\nmovups xmmword ptr [r13+rdi+0], xmm4\ncmp rsi, rax\njz short loc_1AA1\nloc_1A7E:\nmov edi, [rax]\ntest edi, edi\njz short loc_1A60\nmovdqu xmm3, xmmword ptr [rax]\nmov rdi, rcx\nadd rax, 10h\nadd rcx, 1\nshl rdi, 4\nmovups xmmword ptr [r12+rdi], xmm3\ncmp rsi, rax\njnz short loc_1A7E\nloc_1AA1:\nlea rcx, compar; compar\nmov edx, 10h; size\nmov rsi, r14; nmemb\nmov rdi, r13; base\ncall _qsort\nmov edx, 10h; size\nmov rsi, rbp; nmemb\nmov rdi, r12; base\nlea rcx, sub_1810; compar\ncall _qsort\nmov rdi, rbx\nshl rdi, 4; size\ncall _malloc\nmov r15, rax\ntest r14, r14\njz short loc_1AF5\nmov rdx, r14\nmov rsi, r13; src\nmov rdi, rax; dest\nshl rdx, 4; n\ncall _memcpy\nloc_1AF5:\ntest rbp, rbp\njz short loc_1B13\nmov rdi, r14\nmov rdx, rbp\nmov rsi, r12; src\nshl rdi, 4\nshl rdx, 4; n\nadd rdi, r15; dest\ncall _memcpy\nloc_1B13:\nmov rdi, r13; ptr\ncall _free\nmov rdi, r12; ptr\ncall _free\nmov rax, [rsp+48h+var_40]\nmov [rax], rbx\nadd rsp, 18h\nmov rax, r15\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1B40:\nadd r14, 1\njmp loc_1919\nloc_1B50:\nadd rbp, 1\njmp loc_1937\nloc_1B60:\nadd rbp, 1\njmp loc_1955\nloc_1B70:\nadd rbp, 1\njmp loc_1973\nloc_1B80:\nadd rbp, 1\njmp loc_1992\nloc_1B90:\nadd rbp, 1\njmp loc_19B1\nloc_1BA0:\nadd rbp, 1\njmp loc_19CC\nloc_1BB0:\nadd r14, 1\njmp loc_19E7\nloc_1BC0:\nadd rbp, 1\njmp loc_1A05\nloc_1BD0:\nadd r14, 1\njmp loc_1A28\nloc_1BE0:\nxor edi, edi; size\ncall _malloc\nxor edi, edi; size\nmov r13, rax\ncall _malloc\nmov edx, 10h; size\nxor esi, esi; nmemb\nmov rdi, r13; base\nmov r12, rax\nlea rcx, compar; compar\ncall _qsort\nmov edx, 10h; size\nxor esi, esi; nmemb\nmov rdi, r12; base\nlea rcx, sub_1810; compar\ncall _qsort\nxor edi, edi; size\ncall _malloc\nmov r15, rax\njmp loc_1B13\nloc_1C2F:\nxor eax, eax\nxor ebp, ebp\nxor r14d, r14d\njmp loc_1901", + "ida_strip_pseudo": "char *__fastcall sub_1830(const __m128i *a1, unsigned __int64 a2, unsigned __int64 *a3)\n{\n unsigned __int64 v4; // rdx\n __m128i v5; // xmm4\n const __m128i *v6; // rax\n __m128i si128; // xmm7\n __m128i v8; // xmm6\n __m128i v9; // xmm3\n __m128 v10; // xmm1\n __m128 v11; // xmm0\n __m128i v12; // xmm0\n __m128i v13; // xmm2\n __m128i v14; // xmm1\n __m128i v15; // xmm0\n __m128 v16; // xmm3\n size_t v17; // rbp\n unsigned __int64 v18; // rax\n size_t v19; // r14\n __int64 v20; // rdx\n __m128i *v21; // r13\n __m128i *v22; // rax\n __int64 v23; // rcx\n __int64 v24; // rdx\n __m128i *v25; // r12\n const __m128i *v26; // rax\n const __m128i *v27; // rsi\n __m128i v28; // xmm4\n __int64 v29; // rdi\n __m128i v30; // xmm3\n __int64 v31; // rdi\n char *v32; // rax\n char *v33; // r15\n\n if ( a2 )\n {\n v4 = a2 - 1;\n if ( a2 - 1 <= 9 )\n {\n v18 = 0LL;\n v17 = 0LL;\n v19 = 0LL;\n }\n else\n {\n v5 = 0LL;\n v6 = a1;\n si128 = _mm_load_si128((const __m128i *)&xmmword_2210);\n v8 = _mm_load_si128((const __m128i *)&xmmword_2220);\n v9 = 0LL;\n do\n {\n v10 = (__m128)_mm_loadu_si128(v6 + 1);\n v11 = (__m128)_mm_loadu_si128(v6);\n v6 += 2;\n v12 = _mm_cmpeq_epi32((__m128i)_mm_shuffle_ps(v11, v10, 0), (__m128i)0LL);\n v13 = _mm_cmpgt_epi32((__m128i)0LL, v12);\n v14 = _mm_unpacklo_epi32(v12, v13);\n v15 = _mm_unpackhi_epi32(v12, v13);\n v9 = _mm_add_epi64(v9, _mm_or_si128(_mm_andnot_si128(v14, v8), _mm_and_si128(si128, v14)));\n v5 = _mm_add_epi64(v5, _mm_or_si128(_mm_andnot_si128(v15, v8), _mm_and_si128(si128, v15)));\n }\n while ( v6 != &a1[2 * (v4 >> 1)] );\n v16 = (__m128)_mm_add_epi64(v9, v5);\n v17 = v16.m128_u64[0];\n v18 = v4 & 0xFFFFFFFFFFFFFFFELL;\n v19 = _mm_movehl_ps((__m128)0LL, v16).m128_u64[0];\n }\n v20 = v18;\n if ( a1[v18].m128i_i32[0] )\n ++v17;\n else\n ++v19;\n if ( v18 + 1 < a2 )\n {\n if ( a1[v20 + 1].m128i_i32[0] )\n ++v17;\n else\n ++v19;\n if ( v18 + 2 < a2 )\n {\n if ( a1[v20 + 2].m128i_i32[0] )\n ++v17;\n else\n ++v19;\n if ( v18 + 3 < a2 )\n {\n if ( a1[v20 + 3].m128i_i32[0] )\n ++v17;\n else\n ++v19;\n if ( v18 + 4 < a2 )\n {\n if ( a1[v20 + 4].m128i_i32[0] )\n ++v17;\n else\n ++v19;\n if ( v18 + 5 < a2 )\n {\n if ( a1[v20 + 5].m128i_i32[0] )\n ++v17;\n else\n ++v19;\n if ( v18 + 6 < a2 )\n {\n if ( a1[v20 + 6].m128i_i32[0] )\n ++v17;\n else\n ++v19;\n if ( v18 + 7 < a2 )\n {\n if ( a1[v20 + 7].m128i_i32[0] )\n ++v17;\n else\n ++v19;\n if ( v18 + 8 < a2 )\n {\n if ( a1[v20 + 8].m128i_i32[0] )\n ++v17;\n else\n ++v19;\n if ( v18 + 9 < a2 )\n {\n if ( a1[v20 + 9].m128i_i32[0] )\n ++v17;\n else\n ++v19;\n }\n }\n }\n }\n }\n }\n }\n }\n }\n v21 = (__m128i *)malloc(16 * v19);\n v22 = (__m128i *)malloc(16 * v17);\n v23 = 0LL;\n v24 = 0LL;\n v25 = v22;\n v26 = a1;\n v27 = &a1[a2];\n do\n {\n while ( !v26->m128i_i32[0] )\n {\n v28 = _mm_loadu_si128(v26);\n v29 = v24;\n ++v26;\n ++v24;\n v21[v29] = v28;\n if ( v27 == v26 )\n goto LABEL_39;\n }\n v30 = _mm_loadu_si128(v26);\n v31 = v23;\n ++v26;\n ++v23;\n v25[v31] = v30;\n }\n while ( v27 != v26 );\nLABEL_39:\n qsort(v21, v19, 0x10uLL, compar);\n qsort(v25, v17, 0x10uLL, sub_1810);\n v32 = (char *)malloc(16 * a2);\n v33 = v32;\n if ( v19 )\n memcpy(v32, v21, 16 * v19);\n if ( v17 )\n memcpy(&v33[16 * v19], v25, 16 * v17);\n }\n else\n {\n v21 = (__m128i *)malloc(0LL);\n v25 = (__m128i *)malloc(0LL);\n qsort(v21, 0LL, 0x10uLL, compar);\n qsort(v25, 0LL, 0x10uLL, sub_1810);\n v33 = (char *)malloc(0LL);\n }\n free(v21);\n free(v25);\n *a3 = a2;\n return v33;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1830(const __m128i *a1, unsigned long long a2,\n unsigned long long *a3) {\n unsigned long long v4;\n __m128i v5;\n const __m128i *v6;\n __m128i si128;\n __m128i v8;\n __m128i v9;\n __m128 v10;\n __m128 v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n __m128i v15;\n __m128 v16;\n unsigned int v17;\n unsigned long long v18;\n unsigned int v19;\n long long v20;\n __m128i *v21;\n __m128i *v22;\n long long v23;\n long long v24;\n __m128i *v25;\n const __m128i *v26;\n const __m128i *v27;\n __m128i v28;\n long long v29;\n __m128i v30;\n long long v31;\n char *v32;\n char *v33;\n if (a2) {\n v4 = a2 - 1;\n if (a2 - 1 <= 9) {\n v18 = 0LL;\n v17 = 0LL;\n v19 = 0LL;\n } else {\n v5 = 0LL;\n v6 = a1;\n si128 = _mm_load_si128((const __m128i *)&xmmword_2210);\n v8 = _mm_load_si128((const __m128i *)&xmmword_2220);\n v9 = 0LL;\n do {\n v10 = (__m128)_mm_loadu_si128(v6 + 1);\n v11 = (__m128)_mm_loadu_si128(v6);\n v6 += 2;\n v12 =\n _mm_cmpeq_epi32((__m128i)_mm_shuffle_ps(v11, v10, 0), (__m128i)0LL);\n v13 = _mm_cmpgt_epi32((__m128i)0LL, v12);\n v14 = _mm_unpacklo_epi32(v12, v13);\n v15 = _mm_unpackhi_epi32(v12, v13);\n v9 = _mm_add_epi64(v9, _mm_or_si128(_mm_andnot_si128(v14, v8),\n _mm_and_si128(si128, v14)));\n v5 = _mm_add_epi64(v5, _mm_or_si128(_mm_andnot_si128(v15, v8),\n _mm_and_si128(si128, v15)));\n } while (v6 != &a1[2 * (v4 >> 1)]);\n v16 = (__m128)_mm_add_epi64(v9, v5);\n v17 = v16.m128_u64[0];\n v18 = v4 & 18446744073709551614LL;\n v19 = _mm_movehl_ps((__m128)0LL, v16).m128_u64[0];\n }\n v20 = v18;\n if (a1[v18].m128i_i32[0])\n ++v17;\n else\n ++v19;\n if (v18 + 1 < a2) {\n if (a1[v20 + 1].m128i_i32[0])\n ++v17;\n else\n ++v19;\n if (v18 + 2 < a2) {\n if (a1[v20 + 2].m128i_i32[0])\n ++v17;\n else\n ++v19;\n if (v18 + 3 < a2) {\n if (a1[v20 + 3].m128i_i32[0])\n ++v17;\n else\n ++v19;\n if (v18 + 4 < a2) {\n if (a1[v20 + 4].m128i_i32[0])\n ++v17;\n else\n ++v19;\n if (v18 + 5 < a2) {\n if (a1[v20 + 5].m128i_i32[0])\n ++v17;\n else\n ++v19;\n if (v18 + 6 < a2) {\n if (a1[v20 + 6].m128i_i32[0])\n ++v17;\n else\n ++v19;\n if (v18 + 7 < a2) {\n if (a1[v20 + 7].m128i_i32[0])\n ++v17;\n else\n ++v19;\n if (v18 + 8 < a2) {\n if (a1[v20 + 8].m128i_i32[0])\n ++v17;\n else\n ++v19;\n if (v18 + 9 < a2) {\n if (a1[v20 + 9].m128i_i32[0])\n ++v17;\n else\n ++v19;\n }\n }\n }\n }\n }\n }\n }\n }\n }\n v21 = (__m128i *)malloc(16 * v19);\n v22 = (__m128i *)malloc(16 * v17);\n v23 = 0LL;\n v24 = 0LL;\n v25 = v22;\n v26 = a1;\n v27 = &a1[a2];\n do {\n while (!v26->m128i_i32[0]) {\n v28 = _mm_loadu_si128(v26);\n v29 = v24;\n ++v26;\n ++v24;\n v21[v29] = v28;\n if (v27 == v26) goto LABEL_39;\n }\n v30 = _mm_loadu_si128(v26);\n v31 = v23;\n ++v26;\n ++v23;\n v25[v31] = v30;\n } while (v27 != v26);\n LABEL_39:\n qsort(v21, v19, 16uLL, compar);\n qsort(v25, v17, 16uLL, sub_1810);\n v32 = (char *)malloc(16 * a2);\n v33 = v32;\n if (v19) memcpy(v32, v21, 16 * v19);\n if (v17) memcpy(&v33[16 * v19], v25, 16 * v17);\n } else {\n v21 = (__m128i *)malloc(0LL);\n v25 = (__m128i *)malloc(0LL);\n qsort(v21, 0LL, 16uLL, compar);\n qsort(v25, 0LL, 16uLL, sub_1810);\n v33 = (char *)malloc(0LL);\n }\n free(v21);\n free(v25);\n *a3 = a2;\n return v33;\n}", + "ida_pseudo_norm": "char *func0(const __m128i *a1, unsigned long long a2, unsigned long long *a3) {\n unsigned long long v4;\n __m128i v5;\n const __m128i *v6;\n __m128i si128;\n __m128i v8;\n __m128i v9;\n __m128 v10;\n __m128 v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n __m128i v15;\n __m128 v16;\n unsigned int v17;\n unsigned long long v18;\n unsigned int v19;\n long long v20;\n __m128i *v21;\n __m128i *v22;\n long long v23;\n long long v24;\n __m128i *v25;\n const __m128i *v26;\n const __m128i *v27;\n __m128i v28;\n long long v29;\n __m128i v30;\n long long v31;\n char *v32;\n char *v33;\n if (a2) {\n v4 = a2 - 1;\n if (a2 - 1 <= 9) {\n v18 = 0LL;\n v17 = 0LL;\n v19 = 0LL;\n } else {\n v5 = 0LL;\n v6 = a1;\n si128 = _mm_load_si128((const __m128i *)&xmmword_2210);\n v8 = _mm_load_si128((const __m128i *)&xmmword_2220);\n v9 = 0LL;\n do {\n v10 = (__m128)_mm_loadu_si128(v6 + 1);\n v11 = (__m128)_mm_loadu_si128(v6);\n v6 += 2;\n v12 =\n _mm_cmpeq_epi32((__m128i)_mm_shuffle_ps(v11, v10, 0), (__m128i)0LL);\n v13 = _mm_cmpgt_epi32((__m128i)0LL, v12);\n v14 = _mm_unpacklo_epi32(v12, v13);\n v15 = _mm_unpackhi_epi32(v12, v13);\n v9 = _mm_add_epi64(v9, _mm_or_si128(_mm_andnot_si128(v14, v8),\n _mm_and_si128(si128, v14)));\n v5 = _mm_add_epi64(v5, _mm_or_si128(_mm_andnot_si128(v15, v8),\n _mm_and_si128(si128, v15)));\n } while (v6 != &a1[2 * (v4 >> 1)]);\n v16 = (__m128)_mm_add_epi64(v9, v5);\n v17 = v16.m128_u64[0];\n v18 = v4 & 18446744073709551614LL;\n v19 = _mm_movehl_ps((__m128)0LL, v16).m128_u64[0];\n }\n v20 = v18;\n if (a1[v18].m128i_i32[0])\n ++v17;\n else\n ++v19;\n if (v18 + 1 < a2) {\n if (a1[v20 + 1].m128i_i32[0])\n ++v17;\n else\n ++v19;\n if (v18 + 2 < a2) {\n if (a1[v20 + 2].m128i_i32[0])\n ++v17;\n else\n ++v19;\n if (v18 + 3 < a2) {\n if (a1[v20 + 3].m128i_i32[0])\n ++v17;\n else\n ++v19;\n if (v18 + 4 < a2) {\n if (a1[v20 + 4].m128i_i32[0])\n ++v17;\n else\n ++v19;\n if (v18 + 5 < a2) {\n if (a1[v20 + 5].m128i_i32[0])\n ++v17;\n else\n ++v19;\n if (v18 + 6 < a2) {\n if (a1[v20 + 6].m128i_i32[0])\n ++v17;\n else\n ++v19;\n if (v18 + 7 < a2) {\n if (a1[v20 + 7].m128i_i32[0])\n ++v17;\n else\n ++v19;\n if (v18 + 8 < a2) {\n if (a1[v20 + 8].m128i_i32[0])\n ++v17;\n else\n ++v19;\n if (v18 + 9 < a2) {\n if (a1[v20 + 9].m128i_i32[0])\n ++v17;\n else\n ++v19;\n }\n }\n }\n }\n }\n }\n }\n }\n }\n v21 = (__m128i *)malloc(16 * v19);\n v22 = (__m128i *)malloc(16 * v17);\n v23 = 0LL;\n v24 = 0LL;\n v25 = v22;\n v26 = a1;\n v27 = &a1[a2];\n do {\n while (!v26->m128i_i32[0]) {\n v28 = _mm_loadu_si128(v26);\n v29 = v24;\n ++v26;\n ++v24;\n v21[v29] = v28;\n if (v27 == v26) goto LABEL_39;\n }\n v30 = _mm_loadu_si128(v26);\n v31 = v23;\n ++v26;\n ++v23;\n v25[v31] = v30;\n } while (v27 != v26);\n LABEL_39:\n qsort(v21, v19, 16uLL, compare_ints);\n qsort(v25, v17, 16uLL, compare_strings);\n v32 = (char *)malloc(16 * a2);\n v33 = v32;\n if (v19) memcpy(v32, v21, 16 * v19);\n if (v17) memcpy(&v33[16 * v19], v25, 16 * v17);\n } else {\n v21 = (__m128i *)malloc(0LL);\n v25 = (__m128i *)malloc(0LL);\n qsort(v21, 0LL, 16uLL, compare_ints);\n qsort(v25, 0LL, 16uLL, compare_strings);\n v33 = (char *)malloc(0LL);\n }\n free(v21);\n free(v25);\n *a3 = a2;\n return v33;\n}" + }, + { + "index": 38, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "double func0(int list1[], int size) {\n int first_even = -1;\n int first_odd = -1;\n for (int i = 0; i < size; i++) {\n if (list1[i] % 2 == 0) {\n first_even = list1[i];\n break;\n }\n }\n for (int i = 0; i < size; i++) {\n if (list1[i] % 2 != 0) {\n first_odd = list1[i];\n break;\n }\n }\n if (first_even != -1 && first_odd != -1) {\n return (double)first_even / first_odd;\n }\n return -1;\n}", + "test": "int main() {\n\n int list1[] = {1, 3, 5, 7, 4, 1, 6, 8};\n\n int size1 = sizeof(list1) / sizeof(list1[0]);\n\n assert(func0(list1, size1) == 4);\n\n\n\n int list2[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n int size2 = sizeof(list2) / sizeof(list2[0]);\n\n assert(func0(list2, size2) == 2);\n\n\n\n int list3[] = {1, 5, 7, 9, 10};\n\n int size3 = sizeof(list3) / sizeof(list3[0]);\n\n assert(func0(list3, size3) == 10);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0xffffffff,-0x10(%rbp)\nmovl $0xffffffff,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11cb \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nand $0x1,%eax\ntest %eax,%eax\njne 11c7 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x10(%rbp)\njmp 11d3 \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 118f \nmovl $0x0,-0x4(%rbp)\njmp 1218 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nand $0x1,%eax\ntest %eax,%eax\nje 1214 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0xc(%rbp)\njmp 1220 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11dc \ncmpl $0xffffffff,-0x10(%rbp)\nje 123c \ncmpl $0xffffffff,-0xc(%rbp)\nje 123c \ncvtsi2sdl -0x10(%rbp),%xmm0\ncvtsi2sdl -0xc(%rbp),%xmm1\ndivsd %xmm1,%xmm0\njmp 1244 \nmovsd 0xe54(%rip),%xmm0\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_10], 0FFFFFFFFh\nmov [rbp+var_C], 0FFFFFFFFh\nmov [rbp+var_8], 0\njmp short loc_11CB\nloc_118F:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njnz short loc_11C7\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_10], eax\njmp short loc_11D3\nloc_11C7:\nadd [rbp+var_8], 1\nloc_11CB:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_118F\nloc_11D3:\nmov [rbp+var_4], 0\njmp short loc_1218\nloc_11DC:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njz short loc_1214\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\njmp short loc_1220\nloc_1214:\nadd [rbp+var_4], 1\nloc_1218:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11DC\nloc_1220:\ncmp [rbp+var_10], 0FFFFFFFFh\njz short loc_1244\ncmp [rbp+var_C], 0FFFFFFFFh\njz short loc_1244\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_10]\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_C]\ndivsd xmm0, xmm1\njmp short loc_124C\nloc_1244:\nmovsd xmm0, cs:qword_2078\nloc_124C:\npop rbp\nretn", + "ida_pseudo": "double __fastcall func0(__int64 a1, int a2)\n{\n int v3; // [rsp+Ch] [rbp-10h]\n int v4; // [rsp+10h] [rbp-Ch]\n int i; // [rsp+14h] [rbp-8h]\n int j; // [rsp+18h] [rbp-4h]\n\n v3 = -1;\n v4 = -1;\n for ( i = 0; i < a2; ++i )\n {\n if ( (*(_DWORD *)(4LL * i + a1) & 1) == 0 )\n {\n v3 = *(_DWORD *)(4LL * i + a1);\n break;\n }\n }\n for ( j = 0; j < a2; ++j )\n {\n if ( (*(_DWORD *)(4LL * j + a1) & 1) != 0 )\n {\n v4 = *(_DWORD *)(4LL * j + a1);\n break;\n }\n }\n if ( v3 == -1 || v4 == -1 )\n return -1.0;\n else\n return (double)v3 / (double)v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_10], 0FFFFFFFFh\nmov [rbp+var_C], 0FFFFFFFFh\nmov [rbp+var_8], 0\njmp short loc_11CB\nloc_118F:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njnz short loc_11C7\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_10], eax\njmp short loc_11D3\nloc_11C7:\nadd [rbp+var_8], 1\nloc_11CB:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_118F\nloc_11D3:\nmov [rbp+var_4], 0\njmp short loc_1218\nloc_11DC:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njz short loc_1214\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\njmp short loc_1220\nloc_1214:\nadd [rbp+var_4], 1\nloc_1218:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11DC\nloc_1220:\ncmp [rbp+var_10], 0FFFFFFFFh\njz short loc_1244\ncmp [rbp+var_C], 0FFFFFFFFh\njz short loc_1244\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_10]\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_C]\ndivsd xmm0, xmm1\njmp short loc_124C\nloc_1244:\nmovsd xmm0, cs:qword_2078\nloc_124C:\npop rbp\nretn", + "ida_strip_pseudo": "double __fastcall sub_1169(__int64 a1, int a2)\n{\n int v3; // [rsp+Ch] [rbp-10h]\n int v4; // [rsp+10h] [rbp-Ch]\n int i; // [rsp+14h] [rbp-8h]\n int j; // [rsp+18h] [rbp-4h]\n\n v3 = -1;\n v4 = -1;\n for ( i = 0; i < a2; ++i )\n {\n if ( (*(_DWORD *)(4LL * i + a1) & 1) == 0 )\n {\n v3 = *(_DWORD *)(4LL * i + a1);\n break;\n }\n }\n for ( j = 0; j < a2; ++j )\n {\n if ( (*(_DWORD *)(4LL * j + a1) & 1) != 0 )\n {\n v4 = *(_DWORD *)(4LL * j + a1);\n break;\n }\n }\n if ( v3 == -1 || v4 == -1 )\n return -1.0;\n else\n return (double)v3 / (double)v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1169(long long a1, int a2) {\n int v3;\n int v4;\n int i;\n int j;\n v3 = -1;\n v4 = -1;\n for (i = 0; i < a2; ++i) {\n if ((*(uint32_t *)(4LL * i + a1) & 1) == 0) {\n v3 = *(uint32_t *)(4LL * i + a1);\n break;\n }\n }\n for (j = 0; j < a2; ++j) {\n if ((*(uint32_t *)(4LL * j + a1) & 1) != 0) {\n v4 = *(uint32_t *)(4LL * j + a1);\n break;\n }\n }\n if (v3 == -1 || v4 == -1)\n return -1.0;\n else\n return (double)v3 / (double)v4;\n}", + "ida_pseudo_norm": "double func0(long long a1, int a2) {\n int v3;\n int v4;\n int i;\n int j;\n v3 = -1;\n v4 = -1;\n for (i = 0; i < a2; ++i) {\n if ((*(uint32_t *)(4LL * i + a1) & 1) == 0) {\n v3 = *(uint32_t *)(4LL * i + a1);\n break;\n }\n }\n for (j = 0; j < a2; ++j) {\n if ((*(uint32_t *)(4LL * j + a1) & 1) != 0) {\n v4 = *(uint32_t *)(4LL * j + a1);\n break;\n }\n }\n if (v3 == -1 || v4 == -1)\n return -1.0;\n else\n return (double)v3 / (double)v4;\n}" + }, + { + "index": 38, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "double func0(int list1[], int size) {\n int first_even = -1;\n int first_odd = -1;\n for (int i = 0; i < size; i++) {\n if (list1[i] % 2 == 0) {\n first_even = list1[i];\n break;\n }\n }\n for (int i = 0; i < size; i++) {\n if (list1[i] % 2 != 0) {\n first_odd = list1[i];\n break;\n }\n }\n if (first_even != -1 && first_odd != -1) {\n return (double)first_even / first_odd;\n }\n return -1;\n}", + "test": "int main() {\n\n int list1[] = {1, 3, 5, 7, 4, 1, 6, 8};\n\n int size1 = sizeof(list1) / sizeof(list1[0]);\n\n assert(func0(list1, size1) == 4);\n\n\n\n int list2[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n int size2 = sizeof(list2) / sizeof(list2[0]);\n\n assert(func0(list2, size2) == 2);\n\n\n\n int list3[] = {1, 5, 7, 9, 10};\n\n int size3 = sizeof(list3) / sizeof(list3[0]);\n\n assert(func0(list3, size3) == 10);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11c9 \nmov %rdi,%rax\nlea -0x1(%rsi),%edx\nlea 0x4(%rdi,%rdx,4),%rsi\nmov (%rdi),%edx\ntest $0x1,%dl\nje 1191 \nadd $0x4,%rdi\ncmp %rsi,%rdi\njne 117c \nmov $0xffffffff,%edx\nmov (%rax),%ecx\ntest $0x1,%cl\njne 11aa \nadd $0x4,%rax\ncmp %rsi,%rax\njne 1191 \nmovsd 0xeef(%rip),%xmm0\nretq\ncmp $0xffffffff,%edx\nje 11d2 \ncmp $0xffffffff,%ecx\nje 11d2 \npxor %xmm0,%xmm0\ncvtsi2sd %edx,%xmm0\npxor %xmm1,%xmm1\ncvtsi2sd %ecx,%xmm1\ndivsd %xmm1,%xmm0\nretq\nmovsd 0xec7(%rip),%xmm0\nretq\nmovsd 0xebe(%rip),%xmm0\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11C8\nmov rax, rdi\nmovsxd rsi, esi\nlea rsi, [rdi+rsi*4]\nloc_117B:\nmov edx, [rdi]\ntest dl, 1\njz short loc_1190\nadd rdi, 4\ncmp rdi, rsi\njnz short loc_117B\nmov edx, 0FFFFFFFFh\nloc_1190:\nmov ecx, [rax]\ntest cl, 1\njnz short loc_11A9\nadd rax, 4\ncmp rax, rsi\njnz short loc_1190\nmovsd xmm0, cs:qword_2078\nretn\nloc_11A9:\ncmp edx, 0FFFFFFFFh\njz short loc_11D1\ncmp ecx, 0FFFFFFFFh\njz short loc_11D1\npxor xmm0, xmm0\ncvtsi2sd xmm0, edx\npxor xmm1, xmm1\ncvtsi2sd xmm1, ecx\ndivsd xmm0, xmm1\nretn\nloc_11C8:\nmovsd xmm0, cs:qword_2078\nretn\nloc_11D1:\nmovsd xmm0, cs:qword_2078\nretn", + "ida_pseudo": "double __fastcall func0(int *a1, int a2)\n{\n int *v2; // rax\n int *v3; // rsi\n int v4; // edx\n int v5; // ecx\n\n if ( a2 <= 0 )\n return -1.0;\n v2 = a1;\n v3 = &a1[a2];\n do\n {\n v4 = *a1;\n if ( (*a1 & 1) == 0 )\n goto LABEL_6;\n ++a1;\n }\n while ( a1 != v3 );\n v4 = -1;\nLABEL_6:\n while ( 1 )\n {\n v5 = *v2;\n if ( (*v2 & 1) != 0 )\n break;\n if ( ++v2 == v3 )\n return -1.0;\n }\n if ( v4 == -1 || v5 == -1 )\n return -1.0;\n else\n return (double)v4 / (double)v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11C8\nmov rax, rdi\nmovsxd rsi, esi\nlea rsi, [rdi+rsi*4]\nloc_117B:\nmov edx, [rdi]\ntest dl, 1\njz short loc_1190\nadd rdi, 4\ncmp rdi, rsi\njnz short loc_117B\nmov edx, 0FFFFFFFFh\nloc_1190:\nmov ecx, [rax]\ntest cl, 1\njnz short loc_11A9\nadd rax, 4\ncmp rax, rsi\njnz short loc_1190\nmovsd xmm0, cs:qword_2078\nretn\nloc_11A9:\ncmp edx, 0FFFFFFFFh\njz short loc_11D1\ncmp ecx, 0FFFFFFFFh\njz short loc_11D1\npxor xmm0, xmm0\ncvtsi2sd xmm0, edx\npxor xmm1, xmm1\ncvtsi2sd xmm1, ecx\ndivsd xmm0, xmm1\nretn\nloc_11C8:\nmovsd xmm0, cs:qword_2078\nretn\nloc_11D1:\nmovsd xmm0, cs:qword_2078\nretn", + "ida_strip_pseudo": "double __fastcall sub_1169(int *a1, int a2)\n{\n int *v2; // rax\n int *v3; // rsi\n int v4; // edx\n int v5; // ecx\n\n if ( a2 <= 0 )\n return -1.0;\n v2 = a1;\n v3 = &a1[a2];\n do\n {\n v4 = *a1;\n if ( (*a1 & 1) == 0 )\n goto LABEL_6;\n ++a1;\n }\n while ( a1 != v3 );\n v4 = -1;\nLABEL_6:\n while ( 1 )\n {\n v5 = *v2;\n if ( (*v2 & 1) != 0 )\n break;\n if ( ++v2 == v3 )\n return -1.0;\n }\n if ( v4 == -1 || v5 == -1 )\n return -1.0;\n else\n return (double)v4 / (double)v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1169(int *a1, int a2) {\n int *v2;\n int *v3;\n int v4;\n int v5;\n if (a2 <= 0) return -1.0;\n v2 = a1;\n v3 = &a1[a2];\n do {\n v4 = *a1;\n if ((*a1 & 1) == 0) goto LABEL_6;\n ++a1;\n } while (a1 != v3);\n v4 = -1;\nLABEL_6:\n while (1) {\n v5 = *v2;\n if ((*v2 & 1) != 0) break;\n if (++v2 == v3) return -1.0;\n }\n if (v4 == -1 || v5 == -1)\n return -1.0;\n else\n return (double)v4 / (double)v5;\n}", + "ida_pseudo_norm": "double func0(int *a1, int a2) {\n int *v2;\n int *v3;\n int v4;\n int v5;\n if (a2 <= 0) return -1.0;\n v2 = a1;\n v3 = &a1[a2];\n do {\n v4 = *a1;\n if ((*a1 & 1) == 0) goto LABEL_6;\n ++a1;\n } while (a1 != v3);\n v4 = -1;\nLABEL_6:\n while (1) {\n v5 = *v2;\n if ((*v2 & 1) != 0) break;\n if (++v2 == v3) return -1.0;\n }\n if (v4 == -1 || v5 == -1)\n return -1.0;\n else\n return (double)v4 / (double)v5;\n}" + }, + { + "index": 38, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "double func0(int list1[], int size) {\n int first_even = -1;\n int first_odd = -1;\n for (int i = 0; i < size; i++) {\n if (list1[i] % 2 == 0) {\n first_even = list1[i];\n break;\n }\n }\n for (int i = 0; i < size; i++) {\n if (list1[i] % 2 != 0) {\n first_odd = list1[i];\n break;\n }\n }\n if (first_even != -1 && first_odd != -1) {\n return (double)first_even / first_odd;\n }\n return -1;\n}", + "test": "int main() {\n\n int list1[] = {1, 3, 5, 7, 4, 1, 6, 8};\n\n int size1 = sizeof(list1) / sizeof(list1[0]);\n\n assert(func0(list1, size1) == 4);\n\n\n\n int list2[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n int size2 = sizeof(list2) / sizeof(list2[0]);\n\n assert(func0(list2, size2) == 2);\n\n\n\n int list3[] = {1, 5, 7, 9, 10};\n\n int size3 = sizeof(list3) / sizeof(list3[0]);\n\n assert(func0(list3, size3) == 10);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1370 \nlea -0x1(%rsi),%eax\nlea 0x4(%rdi,%rax,4),%rcx\nmov %rdi,%rax\njmp 1331 \nnopl (%rax)\nadd $0x4,%rax\ncmp %rcx,%rax\nje 1380 \nmov (%rax),%edx\ntest $0x1,%dl\njne 1328 \njmp 1349 \nnopw 0x0(%rax,%rax,1)\nadd $0x4,%rdi\ncmp %rcx,%rdi\nje 1370 \nmov (%rdi),%eax\ntest $0x1,%al\nje 1340 \ncmp $0xffffffff,%edx\nje 1370 \ncmp $0xffffffff,%eax\nje 1370 \npxor %xmm0,%xmm0\npxor %xmm1,%xmm1\ncvtsi2sd %edx,%xmm0\ncvtsi2sd %eax,%xmm1\ndivsd %xmm1,%xmm0\nretq\nxchg %ax,%ax\nmovsd 0xd20(%rip),%xmm0\nretq\nnopl 0x0(%rax)\nmov $0xffffffff,%edx\njmp 1349 \nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1320\nmovsxd rsi, esi\nmov rax, rdi\nlea rcx, [rdi+rsi*4]\njmp short loc_12E1\nloc_12D8:\nadd rax, 4\ncmp rcx, rax\njz short loc_1330\nloc_12E1:\nmov edx, [rax]\ntest dl, 1\njnz short loc_12D8\nmov esi, 1\njmp short loc_12F9\nloc_12F0:\nadd rdi, 4\ncmp rcx, rdi\njz short loc_1320\nloc_12F9:\nmov eax, [rdi]\ntest al, 1\njz short loc_12F0\ncmp eax, 0FFFFFFFFh\njz short loc_1320\ntest sil, sil\njz short loc_1320\npxor xmm0, xmm0\npxor xmm1, xmm1\ncvtsi2sd xmm0, edx\ncvtsi2sd xmm1, eax\ndivsd xmm0, xmm1\nretn\nloc_1320:\nmovsd xmm0, cs:qword_2078\nretn\nloc_1330:\nxor esi, esi\nmov edx, 0FFFFFFFFh\njmp short loc_12F9", + "ida_pseudo": "double __fastcall func0(int *a1, int a2)\n{\n int *v2; // rax\n int *v3; // rcx\n int v4; // edx\n char v5; // si\n int v6; // eax\n\n if ( a2 <= 0 )\n return -1.0;\n v2 = a1;\n v3 = &a1[a2];\n do\n {\n v4 = *v2;\n if ( (*v2 & 1) == 0 )\n {\n v5 = 1;\n goto LABEL_7;\n }\n ++v2;\n }\n while ( v3 != v2 );\n v5 = 0;\n v4 = -1;\nLABEL_7:\n while ( 1 )\n {\n v6 = *a1;\n if ( (*a1 & 1) != 0 )\n break;\n if ( v3 == ++a1 )\n return -1.0;\n }\n if ( v6 == -1 || !v5 )\n return -1.0;\n else\n return (double)v4 / (double)v6;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\ntest esi, esi\njle short loc_1320\nmovsxd rsi, esi\nmov rax, rdi\nlea rcx, [rdi+rsi*4]\njmp short loc_12E1\nloc_12D8:\nadd rax, 4\ncmp rcx, rax\njz short loc_1330\nloc_12E1:\nmov edx, [rax]\ntest dl, 1\njnz short loc_12D8\nmov esi, 1\njmp short loc_12F9\nloc_12F0:\nadd rdi, 4\ncmp rcx, rdi\njz short loc_1320\nloc_12F9:\nmov eax, [rdi]\ntest al, 1\njz short loc_12F0\ncmp eax, 0FFFFFFFFh\njz short loc_1320\ntest sil, sil\njz short loc_1320\npxor xmm0, xmm0\npxor xmm1, xmm1\ncvtsi2sd xmm0, edx\ncvtsi2sd xmm1, eax\ndivsd xmm0, xmm1\nretn\nloc_1320:\nmovsd xmm0, cs:qword_2078\nretn\nloc_1330:\nxor esi, esi\nmov edx, 0FFFFFFFFh\njmp short loc_12F9", + "ida_strip_pseudo": "double __fastcall sub_12C0(int *a1, int a2)\n{\n int *v2; // rax\n int *v3; // rcx\n int v4; // edx\n char v5; // si\n int v6; // eax\n\n if ( a2 <= 0 )\n return -1.0;\n v2 = a1;\n v3 = &a1[a2];\n do\n {\n v4 = *v2;\n if ( (*v2 & 1) == 0 )\n {\n v5 = 1;\n goto LABEL_7;\n }\n ++v2;\n }\n while ( v3 != v2 );\n v5 = 0;\n v4 = -1;\nLABEL_7:\n while ( 1 )\n {\n v6 = *a1;\n if ( (*a1 & 1) != 0 )\n break;\n if ( v3 == ++a1 )\n return -1.0;\n }\n if ( v6 == -1 || !v5 )\n return -1.0;\n else\n return (double)v4 / (double)v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_12C0(int *a1, int a2) {\n int *v2;\n int *v3;\n int v4;\n char v5;\n int v6;\n if (a2 <= 0) return -1.0;\n v2 = a1;\n v3 = &a1[a2];\n do {\n v4 = *v2;\n if ((*v2 & 1) == 0) {\n v5 = 1;\n goto LABEL_7;\n }\n ++v2;\n } while (v3 != v2);\n v5 = 0;\n v4 = -1;\nLABEL_7:\n while (1) {\n v6 = *a1;\n if ((*a1 & 1) != 0) break;\n if (v3 == ++a1) return -1.0;\n }\n if (v6 == -1 || !v5)\n return -1.0;\n else\n return (double)v4 / (double)v6;\n}", + "ida_pseudo_norm": "double func0(int *a1, int a2) {\n int *v2;\n int *v3;\n int v4;\n char v5;\n int v6;\n if (a2 <= 0) return -1.0;\n v2 = a1;\n v3 = &a1[a2];\n do {\n v4 = *v2;\n if ((*v2 & 1) == 0) {\n v5 = 1;\n goto LABEL_7;\n }\n ++v2;\n } while (v3 != v2);\n v5 = 0;\n v4 = -1;\nLABEL_7:\n while (1) {\n v6 = *a1;\n if ((*a1 & 1) != 0) break;\n if (v3 == ++a1) return -1.0;\n }\n if (v6 == -1 || !v5)\n return -1.0;\n else\n return (double)v4 / (double)v6;\n}" + }, + { + "index": 38, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "double func0(int list1[], int size) {\n int first_even = -1;\n int first_odd = -1;\n for (int i = 0; i < size; i++) {\n if (list1[i] % 2 == 0) {\n first_even = list1[i];\n break;\n }\n }\n for (int i = 0; i < size; i++) {\n if (list1[i] % 2 != 0) {\n first_odd = list1[i];\n break;\n }\n }\n if (first_even != -1 && first_odd != -1) {\n return (double)first_even / first_odd;\n }\n return -1;\n}", + "test": "int main() {\n\n int list1[] = {1, 3, 5, 7, 4, 1, 6, 8};\n\n int size1 = sizeof(list1) / sizeof(list1[0]);\n\n assert(func0(list1, size1) == 4);\n\n\n\n int list2[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n int size2 = sizeof(list2) / sizeof(list2[0]);\n\n assert(func0(list2, size2) == 2);\n\n\n\n int list3[] = {1, 5, 7, 9, 10};\n\n int size3 = sizeof(list3) / sizeof(list3[0]);\n\n assert(func0(list3, size3) == 10);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1320 \nlea -0x1(%rsi),%eax\nlea 0x4(%rdi,%rax,4),%rcx\nmov %rdi,%rax\njmp 12e1 \nnopl (%rax)\nadd $0x4,%rax\ncmp %rcx,%rax\nje 1330 \nmov (%rax),%edx\ntest $0x1,%dl\njne 12d8 \njmp 12f9 \nnopw 0x0(%rax,%rax,1)\nadd $0x4,%rdi\ncmp %rcx,%rdi\nje 1320 \nmov (%rdi),%eax\ntest $0x1,%al\nje 12f0 \ncmp $0xffffffff,%edx\nje 1320 \ncmp $0xffffffff,%eax\nje 1320 \npxor %xmm0,%xmm0\npxor %xmm1,%xmm1\ncvtsi2sd %edx,%xmm0\ncvtsi2sd %eax,%xmm1\ndivsd %xmm1,%xmm0\nretq\nxchg %ax,%ax\nmovsd 0xd70(%rip),%xmm0\nretq\nnopl 0x0(%rax)\nmov $0xffffffff,%edx\njmp 12f9 \nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1320\nmovsxd rsi, esi\nmov rax, rdi\nlea rcx, [rdi+rsi*4]\njmp short loc_12E1\nloc_12D8:\nadd rax, 4\ncmp rcx, rax\njz short loc_1330\nloc_12E1:\nmov edx, [rax]\ntest dl, 1\njnz short loc_12D8\nmov esi, 1\njmp short loc_12F9\nloc_12F0:\nadd rdi, 4\ncmp rcx, rdi\njz short loc_1320\nloc_12F9:\nmov eax, [rdi]\ntest al, 1\njz short loc_12F0\ncmp eax, 0FFFFFFFFh\njz short loc_1320\ntest sil, sil\njz short loc_1320\npxor xmm0, xmm0\npxor xmm1, xmm1\ncvtsi2sd xmm0, edx\ncvtsi2sd xmm1, eax\ndivsd xmm0, xmm1\nretn\nloc_1320:\nmovsd xmm0, cs:qword_2078\nretn\nloc_1330:\nxor esi, esi\nmov edx, 0FFFFFFFFh\njmp short loc_12F9", + "ida_pseudo": "double __fastcall func0(int *a1, int a2)\n{\n int *v2; // rax\n int *v3; // rcx\n int v4; // edx\n char v5; // si\n int v6; // eax\n\n if ( a2 <= 0 )\n return -1.0;\n v2 = a1;\n v3 = &a1[a2];\n do\n {\n v4 = *v2;\n if ( (*v2 & 1) == 0 )\n {\n v5 = 1;\n goto LABEL_7;\n }\n ++v2;\n }\n while ( v3 != v2 );\n v5 = 0;\n v4 = -1;\nLABEL_7:\n while ( 1 )\n {\n v6 = *a1;\n if ( (*a1 & 1) != 0 )\n break;\n if ( v3 == ++a1 )\n return -1.0;\n }\n if ( v6 == -1 || !v5 )\n return -1.0;\n else\n return (double)v4 / (double)v6;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\ntest esi, esi\njle short loc_1320\nmovsxd rsi, esi\nmov rax, rdi\nlea rcx, [rdi+rsi*4]\njmp short loc_12E1\nloc_12D8:\nadd rax, 4\ncmp rcx, rax\njz short loc_1330\nloc_12E1:\nmov edx, [rax]\ntest dl, 1\njnz short loc_12D8\nmov esi, 1\njmp short loc_12F9\nloc_12F0:\nadd rdi, 4\ncmp rcx, rdi\njz short loc_1320\nloc_12F9:\nmov eax, [rdi]\ntest al, 1\njz short loc_12F0\ncmp eax, 0FFFFFFFFh\njz short loc_1320\ntest sil, sil\njz short loc_1320\npxor xmm0, xmm0\npxor xmm1, xmm1\ncvtsi2sd xmm0, edx\ncvtsi2sd xmm1, eax\ndivsd xmm0, xmm1\nretn\nloc_1320:\nmovsd xmm0, cs:qword_2078\nretn\nloc_1330:\nxor esi, esi\nmov edx, 0FFFFFFFFh\njmp short loc_12F9", + "ida_strip_pseudo": "double __fastcall sub_12C0(int *a1, int a2)\n{\n int *v2; // rax\n int *v3; // rcx\n int v4; // edx\n char v5; // si\n int v6; // eax\n\n if ( a2 <= 0 )\n return -1.0;\n v2 = a1;\n v3 = &a1[a2];\n do\n {\n v4 = *v2;\n if ( (*v2 & 1) == 0 )\n {\n v5 = 1;\n goto LABEL_7;\n }\n ++v2;\n }\n while ( v3 != v2 );\n v5 = 0;\n v4 = -1;\nLABEL_7:\n while ( 1 )\n {\n v6 = *a1;\n if ( (*a1 & 1) != 0 )\n break;\n if ( v3 == ++a1 )\n return -1.0;\n }\n if ( v6 == -1 || !v5 )\n return -1.0;\n else\n return (double)v4 / (double)v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_12C0(int *a1, int a2) {\n int *v2;\n int *v3;\n int v4;\n char v5;\n int v6;\n if (a2 <= 0) return -1.0;\n v2 = a1;\n v3 = &a1[a2];\n do {\n v4 = *v2;\n if ((*v2 & 1) == 0) {\n v5 = 1;\n goto LABEL_7;\n }\n ++v2;\n } while (v3 != v2);\n v5 = 0;\n v4 = -1;\nLABEL_7:\n while (1) {\n v6 = *a1;\n if ((*a1 & 1) != 0) break;\n if (v3 == ++a1) return -1.0;\n }\n if (v6 == -1 || !v5)\n return -1.0;\n else\n return (double)v4 / (double)v6;\n}", + "ida_pseudo_norm": "double func0(int *a1, int a2) {\n int *v2;\n int *v3;\n int v4;\n char v5;\n int v6;\n if (a2 <= 0) return -1.0;\n v2 = a1;\n v3 = &a1[a2];\n do {\n v4 = *v2;\n if ((*v2 & 1) == 0) {\n v5 = 1;\n goto LABEL_7;\n }\n ++v2;\n } while (v3 != v2);\n v5 = 0;\n v4 = -1;\nLABEL_7:\n while (1) {\n v6 = *a1;\n if ((*a1 & 1) != 0) break;\n if (v3 == ++a1) return -1.0;\n }\n if (v6 == -1 || !v5)\n return -1.0;\n else\n return (double)v4 / (double)v6;\n}" + }, + { + "index": 39, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int freq;\n\n char ch;\n\n} HeapNode;\n\n\n\nvoid swap(HeapNode *a, HeapNode *b) {\n\n HeapNode temp = *a;\n\n *a = *b;\n\n *b = temp;\n\n}\n\n\n\nint compare(HeapNode a, HeapNode b) {\n\n // Higher frequency has higher priority.\n\n // If frequency equal, smaller char (lexicographically) has higher priority.\n\n if(a.freq != b.freq)\n\n return a.freq - b.freq; // positive if a.freq > b.freq.\n\n else\n\n return (b.ch - a.ch); // if a.ch < b.ch then priority: a\n\n}\n\n\n\nvoid heapify_down(HeapNode heap[], int n, int idx) {\n\n int largest = idx;\n\n int left = 2*idx + 1;\n\n int right = 2*idx + 2;\n\n if(left < n && (compare(heap[left], heap[largest]) > 0))\n\n largest = left;\n\n if(right < n && (compare(heap[right], heap[largest]) > 0))\n\n largest = right;\n\n if(largest != idx) {\n\n swap(&heap[idx], &heap[largest]);\n\n heapify_down(heap, n, largest);\n\n }\n\n}\n\n\n\nvoid heapify_up(HeapNode heap[], int idx) {\n\n while(idx > 0) {\n\n int parent = (idx - 1)/2;\n\n if(compare(heap[idx], heap[parent]) > 0) {\n\n swap(&heap[idx], &heap[parent]);\n\n idx = parent;\n\n } else {\n\n break;\n\n }\n\n }\n\n}\n\n\n\nvoid heap_push(HeapNode heap[], int *n, HeapNode node) {\n\n heap[*n] = node;\n\n (*n)++;\n\n heapify_up(heap, (*n)-1);\n\n}\n\n\n\nHeapNode heap_pop(HeapNode heap[], int *n) {\n\n HeapNode top = heap[0];\n\n heap[0] = heap[(*n)-1];\n\n (*n)--;\n\n heapify_down(heap, *n, 0);\n\n return top;\n\n}\n\n\n\n", + "func": "char *func0(const char *S) {\n int len = strlen(S);\n if (len == 0) {\n char *empty = malloc(1);\n if (empty) empty[0] = '\\0';\n return empty;\n }\n int freq[256] = {0};\n for (int i = 0; i < len; i++) {\n freq[(unsigned char)S[i]]++;\n }\n HeapNode heap[256];\n int heapSize = 0;\n for (int i = 0; i < 256; i++) {\n if (freq[i] > 0) {\n HeapNode node;\n node.freq = freq[i];\n node.ch = (char)i;\n heap[heapSize++] = node;\n }\n }\n for (int i = (heapSize / 2) - 1; i >= 0; i--) {\n heapify_down(heap, heapSize, i);\n }\n if (heapSize > 0 && heap[0].freq * 2 > len + 1) {\n char *empty = malloc(1);\n if (empty) empty[0] = '\\0';\n return empty;\n }\n char *result = malloc(len + 1);\n int pos = 0;\n while (heapSize >= 2) {\n HeapNode first = heap_pop(heap, &heapSize);\n HeapNode second = heap_pop(heap, &heapSize);\n result[pos++] = first.ch;\n result[pos++] = second.ch;\n first.freq--;\n second.freq--;\n if (first.freq > 0) {\n heap_push(heap, &heapSize, first);\n }\n if (second.freq > 0) {\n heap_push(heap, &heapSize, second);\n }\n }\n if (heapSize > 0) {\n HeapNode last = heap_pop(heap, &heapSize);\n result[pos++] = last.ch;\n }\n result[pos] = '\\0';\n return result;\n}", + "test": "int main() {\n\n char *res1 = func0(\"aab\");\n\n // The expected output is \"aba\"\n\n assert(strcmp(res1, \"aba\") == 0);\n\n free(res1);\n\n \n\n char *res2 = func0(\"aabb\");\n\n // The expected output is \"abab\"\n\n assert(strcmp(res2, \"abab\") == 0);\n\n free(res2);\n\n \n\n char *res3 = func0(\"abccdd\");\n\n // The expected output is \"cdabcd\"\n\n assert(strcmp(res3, \"cdabcd\") == 0);\n\n free(res3);\n\n \n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0xc60,%rsp\nmov %rdi,-0xc58(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmov -0xc58(%rbp),%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %eax,-0xc3c(%rbp)\ncmpl $0x0,-0xc3c(%rbp)\njne 1553 \nmov $0x1,%edi\ncallq 10f0 \nmov %rax,-0xc28(%rbp)\ncmpq $0x0,-0xc28(%rbp)\nje 1547 \nmov -0xc28(%rbp),%rax\nmovb $0x0,(%rax)\nmov -0xc28(%rbp),%rax\njmpq 186f \nlea -0xc10(%rbp),%rdx\nmov $0x0,%eax\nmov $0x80,%ecx\nmov %rdx,%rdi\nrep stos %rax,%es:(%rdi)\nmovl $0x0,-0xc4c(%rbp)\njmp 15ac \nmov -0xc4c(%rbp),%eax\nmovslq %eax,%rdx\nmov -0xc58(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmovzbl %al,%eax\nmovslq %eax,%rdx\nmov -0xc10(%rbp,%rdx,4),%edx\nadd $0x1,%edx\ncltq\nmov %edx,-0xc10(%rbp,%rax,4)\naddl $0x1,-0xc4c(%rbp)\nmov -0xc4c(%rbp),%eax\ncmp -0xc3c(%rbp),%eax\njl 1576 \nmovl $0x0,-0xc50(%rbp)\nmovl $0x0,-0xc48(%rbp)\njmp 162b \nmov -0xc48(%rbp),%eax\ncltq\nmov -0xc10(%rbp,%rax,4),%eax\ntest %eax,%eax\njle 1624 \nmov -0xc48(%rbp),%eax\ncltq\nmov -0xc10(%rbp,%rax,4),%eax\nmov %eax,-0xc18(%rbp)\nmov -0xc48(%rbp),%eax\nmov %al,-0xc14(%rbp)\nmov -0xc50(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0xc50(%rbp)\ncltq\nmov -0xc18(%rbp),%rdx\nmov %rdx,-0x810(%rbp,%rax,8)\naddl $0x1,-0xc48(%rbp)\ncmpl $0xff,-0xc48(%rbp)\njle 15d0 \nmov -0xc50(%rbp),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nsub $0x1,%eax\nmov %eax,-0xc44(%rbp)\njmp 1675 \nmov -0xc50(%rbp),%ecx\nmov -0xc44(%rbp),%edx\nlea -0x810(%rbp),%rax\nmov %ecx,%esi\nmov %rax,%rdi\ncallq 125a \nsubl $0x1,-0xc44(%rbp)\ncmpl $0x0,-0xc44(%rbp)\njns 1651 \nmov -0xc50(%rbp),%eax\ntest %eax,%eax\njle 16cf \nmov -0x810(%rbp),%eax\nlea (%rax,%rax,1),%edx\nmov -0xc3c(%rbp),%eax\nadd $0x1,%eax\ncmp %eax,%edx\njle 16cf \nmov $0x1,%edi\ncallq 10f0 \nmov %rax,-0xc38(%rbp)\ncmpq $0x0,-0xc38(%rbp)\nje 16c3 \nmov -0xc38(%rbp),%rax\nmovb $0x0,(%rax)\nmov -0xc38(%rbp),%rax\njmpq 186f \nmov -0xc3c(%rbp),%eax\nadd $0x1,%eax\ncltq\nmov %rax,%rdi\ncallq 10f0 \nmov %rax,-0xc30(%rbp)\nmovl $0x0,-0xc40(%rbp)\njmpq 17f4 \nlea -0xc50(%rbp),%rdx\nlea -0x810(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1471 \nmov %rax,-0xc20(%rbp)\nlea -0xc50(%rbp),%rdx\nlea -0x810(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1471 \nmov %rax,-0xc18(%rbp)\nmov -0xc40(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0xc40(%rbp)\nmovslq %eax,%rdx\nmov -0xc30(%rbp),%rax\nadd %rax,%rdx\nmovzbl -0xc1c(%rbp),%eax\nmov %al,(%rdx)\nmov -0xc40(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0xc40(%rbp)\nmovslq %eax,%rdx\nmov -0xc30(%rbp),%rax\nadd %rax,%rdx\nmovzbl -0xc14(%rbp),%eax\nmov %al,(%rdx)\nmov -0xc20(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0xc20(%rbp)\nmov -0xc18(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0xc18(%rbp)\nmov -0xc20(%rbp),%eax\ntest %eax,%eax\njle 17ca \nmov -0xc20(%rbp),%rdx\nlea -0xc50(%rbp),%rcx\nlea -0x810(%rbp),%rax\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 1412 \nmov -0xc18(%rbp),%eax\ntest %eax,%eax\njle 17f4 \nmov -0xc18(%rbp),%rdx\nlea -0xc50(%rbp),%rcx\nlea -0x810(%rbp),%rax\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 1412 \nmov -0xc50(%rbp),%eax\ncmp $0x1,%eax\njg 16f8 \nmov -0xc50(%rbp),%eax\ntest %eax,%eax\njle 1852 \nlea -0xc50(%rbp),%rdx\nlea -0x810(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1471 \nmov %rax,-0xc18(%rbp)\nmov -0xc40(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0xc40(%rbp)\nmovslq %eax,%rdx\nmov -0xc30(%rbp),%rax\nadd %rax,%rdx\nmovzbl -0xc14(%rbp),%eax\nmov %al,(%rdx)\nmov -0xc40(%rbp),%eax\nmovslq %eax,%rdx\nmov -0xc30(%rbp),%rax\nadd %rdx,%rax\nmovb $0x0,(%rax)\nmov -0xc30(%rbp),%rax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 1883 \ncallq 10c0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0C60h\nmov [rbp+s], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_C3C], eax\ncmp [rbp+var_C3C], 0\njnz short loc_1561\nmov edi, 1; size\ncall _malloc\nmov [rbp+var_C28], rax\ncmp [rbp+var_C28], 0\njz short loc_1555\nmov rax, [rbp+var_C28]\nmov byte ptr [rax], 0\nloc_1555:\nmov rax, [rbp+var_C28]\njmp loc_187D\nloc_1561:\nlea rdx, [rbp+var_C10]\nmov eax, 0\nmov ecx, 80h\nmov rdi, rdx\nrep stosq\nmov [rbp+var_C4C], 0\njmp short loc_15BA\nloc_1584:\nmov eax, [rbp+var_C4C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovzx eax, al\nmovsxd rdx, eax\nmov edx, [rbp+rdx*4+var_C10]\nadd edx, 1\ncdqe\nmov [rbp+rax*4+var_C10], edx\nadd [rbp+var_C4C], 1\nloc_15BA:\nmov eax, [rbp+var_C4C]\ncmp eax, [rbp+var_C3C]\njl short loc_1584\nmov [rbp+var_C50], 0\nmov [rbp+var_C48], 0\njmp short loc_1639\nloc_15DE:\nmov eax, [rbp+var_C48]\ncdqe\nmov eax, [rbp+rax*4+var_C10]\ntest eax, eax\njle short loc_1632\nmov eax, [rbp+var_C48]\ncdqe\nmov eax, [rbp+rax*4+var_C10]\nmov dword ptr [rbp+var_C18], eax\nmov eax, [rbp+var_C48]\nmov byte ptr [rbp+var_C18+4], al\nmov eax, [rbp+var_C50]\nlea edx, [rax+1]\nmov [rbp+var_C50], edx\ncdqe\nmov rdx, [rbp+var_C18]\nmov [rbp+rax*8+var_810], rdx\nloc_1632:\nadd [rbp+var_C48], 1\nloc_1639:\ncmp [rbp+var_C48], 0FFh\njle short loc_15DE\nmov eax, [rbp+var_C50]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nsub eax, 1\nmov [rbp+var_C44], eax\njmp short loc_1683\nloc_165F:\nmov ecx, [rbp+var_C50]\nmov edx, [rbp+var_C44]\nlea rax, [rbp+var_810]\nmov esi, ecx\nmov rdi, rax\ncall heapify_down\nsub [rbp+var_C44], 1\nloc_1683:\ncmp [rbp+var_C44], 0\njns short loc_165F\nmov eax, [rbp+var_C50]\ntest eax, eax\njle short loc_16DD\nmov eax, dword ptr [rbp+var_810]\nlea edx, [rax+rax]\nmov eax, [rbp+var_C3C]\nadd eax, 1\ncmp edx, eax\njle short loc_16DD\nmov edi, 1; size\ncall _malloc\nmov [rbp+var_C38], rax\ncmp [rbp+var_C38], 0\njz short loc_16D1\nmov rax, [rbp+var_C38]\nmov byte ptr [rax], 0\nloc_16D1:\nmov rax, [rbp+var_C38]\njmp loc_187D\nloc_16DD:\nmov eax, [rbp+var_C3C]\nadd eax, 1\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_C30], rax\nmov [rbp+var_C40], 0\njmp loc_1802\nloc_1706:\nlea rdx, [rbp+var_C50]\nlea rax, [rbp+var_810]\nmov rsi, rdx\nmov rdi, rax\ncall heap_pop\nmov [rbp+var_C20], rax\nlea rdx, [rbp+var_C50]\nlea rax, [rbp+var_810]\nmov rsi, rdx\nmov rdi, rax\ncall heap_pop\nmov [rbp+var_C18], rax\nmov eax, [rbp+var_C40]\nlea edx, [rax+1]\nmov [rbp+var_C40], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_C30]\nadd rdx, rax\nmovzx eax, byte ptr [rbp+var_C20+4]\nmov [rdx], al\nmov eax, [rbp+var_C40]\nlea edx, [rax+1]\nmov [rbp+var_C40], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_C30]\nadd rdx, rax\nmovzx eax, byte ptr [rbp+var_C18+4]\nmov [rdx], al\nmov eax, dword ptr [rbp+var_C20]\nsub eax, 1\nmov dword ptr [rbp+var_C20], eax\nmov eax, dword ptr [rbp+var_C18]\nsub eax, 1\nmov dword ptr [rbp+var_C18], eax\nmov eax, dword ptr [rbp+var_C20]\ntest eax, eax\njle short loc_17D8\nmov rdx, [rbp+var_C20]\nlea rcx, [rbp+var_C50]\nlea rax, [rbp+var_810]\nmov rsi, rcx\nmov rdi, rax\ncall heap_push\nloc_17D8:\nmov eax, dword ptr [rbp+var_C18]\ntest eax, eax\njle short loc_1802\nmov rdx, [rbp+var_C18]\nlea rcx, [rbp+var_C50]\nlea rax, [rbp+var_810]\nmov rsi, rcx\nmov rdi, rax\ncall heap_push\nloc_1802:\nmov eax, [rbp+var_C50]\ncmp eax, 1\njg loc_1706\nmov eax, [rbp+var_C50]\ntest eax, eax\njle short loc_1860\nlea rdx, [rbp+var_C50]\nlea rax, [rbp+var_810]\nmov rsi, rdx\nmov rdi, rax\ncall heap_pop\nmov [rbp+var_C18], rax\nmov eax, [rbp+var_C40]\nlea edx, [rax+1]\nmov [rbp+var_C40], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_C30]\nadd rdx, rax\nmovzx eax, byte ptr [rbp+var_C18+4]\nmov [rdx], al\nloc_1860:\nmov eax, [rbp+var_C40]\nmovsxd rdx, eax\nmov rax, [rbp+var_C30]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+var_C30]\nloc_187D:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1891\ncall ___stack_chk_fail\nlocret_1891:\nleave\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1)\n{\n int v2; // eax\n int v3; // eax\n int v4; // eax\n int v5; // eax\n int v6; // [rsp+10h] [rbp-C50h] BYREF\n int i; // [rsp+14h] [rbp-C4Ch]\n int j; // [rsp+18h] [rbp-C48h]\n int k; // [rsp+1Ch] [rbp-C44h]\n int v10; // [rsp+20h] [rbp-C40h]\n int v11; // [rsp+24h] [rbp-C3Ch]\n _BYTE *v12; // [rsp+28h] [rbp-C38h]\n _BYTE *v13; // [rsp+30h] [rbp-C30h]\n _BYTE *v14; // [rsp+38h] [rbp-C28h]\n __int64 v15; // [rsp+40h] [rbp-C20h]\n __int64 v16; // [rsp+48h] [rbp-C18h]\n _DWORD v17[256]; // [rsp+50h] [rbp-C10h] BYREF\n _QWORD v18[258]; // [rsp+450h] [rbp-810h] BYREF\n\n v18[257] = __readfsqword(0x28u);\n v11 = strlen(a1);\n if ( v11 )\n {\n memset(v17, 0, sizeof(v17));\n for ( i = 0; i < v11; ++i )\n ++v17[(unsigned __int8)a1[i]];\n v6 = 0;\n for ( j = 0; j <= 255; ++j )\n {\n if ( (int)v17[j] > 0 )\n {\n LODWORD(v16) = v17[j];\n BYTE4(v16) = j;\n v2 = v6++;\n v18[v2] = v16;\n }\n }\n for ( k = v6 / 2 - 1; k >= 0; --k )\n heapify_down(v18, (unsigned int)v6, (unsigned int)k);\n if ( v6 <= 0 || 2 * LODWORD(v18[0]) <= v11 + 1 )\n {\n v13 = malloc(v11 + 1);\n v10 = 0;\n while ( v6 > 1 )\n {\n v15 = heap_pop(v18, &v6);\n v16 = heap_pop(v18, &v6);\n v3 = v10++;\n v13[v3] = BYTE4(v15);\n v4 = v10++;\n v13[v4] = BYTE4(v16);\n LODWORD(v15) = v15 - 1;\n LODWORD(v16) = v16 - 1;\n if ( (int)v15 > 0 )\n heap_push(v18, &v6, v15);\n if ( (int)v16 > 0 )\n heap_push(v18, &v6, v16);\n }\n if ( v6 > 0 )\n {\n v16 = heap_pop(v18, &v6);\n v5 = v10++;\n v13[v5] = BYTE4(v16);\n }\n v13[v10] = 0;\n return v13;\n }\n else\n {\n v12 = malloc(1uLL);\n if ( v12 )\n *v12 = 0;\n return v12;\n }\n }\n else\n {\n v14 = malloc(1uLL);\n if ( v14 )\n *v14 = 0;\n return v14;\n }\n}", + "ida_strip_asm": "sub_14ED:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0C60h\nmov [rbp+s], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_C3C], eax\ncmp [rbp+var_C3C], 0\njnz short loc_1561\nmov edi, 1; size\ncall _malloc\nmov [rbp+var_C28], rax\ncmp [rbp+var_C28], 0\njz short loc_1555\nmov rax, [rbp+var_C28]\nmov byte ptr [rax], 0\nloc_1555:\nmov rax, [rbp+var_C28]\njmp loc_187D\nloc_1561:\nlea rdx, [rbp+var_C10]\nmov eax, 0\nmov ecx, 80h\nmov rdi, rdx\nrep stosq\nmov [rbp+var_C4C], 0\njmp short loc_15BA\nloc_1584:\nmov eax, [rbp+var_C4C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovzx eax, al\nmovsxd rdx, eax\nmov edx, [rbp+rdx*4+var_C10]\nadd edx, 1\ncdqe\nmov [rbp+rax*4+var_C10], edx\nadd [rbp+var_C4C], 1\nloc_15BA:\nmov eax, [rbp+var_C4C]\ncmp eax, [rbp+var_C3C]\njl short loc_1584\nmov [rbp+var_C50], 0\nmov [rbp+var_C48], 0\njmp short loc_1639\nloc_15DE:\nmov eax, [rbp+var_C48]\ncdqe\nmov eax, [rbp+rax*4+var_C10]\ntest eax, eax\njle short loc_1632\nmov eax, [rbp+var_C48]\ncdqe\nmov eax, [rbp+rax*4+var_C10]\nmov dword ptr [rbp+var_C18], eax\nmov eax, [rbp+var_C48]\nmov byte ptr [rbp+var_C18+4], al\nmov eax, [rbp+var_C50]\nlea edx, [rax+1]\nmov [rbp+var_C50], edx\ncdqe\nmov rdx, [rbp+var_C18]\nmov [rbp+rax*8+var_810], rdx\nloc_1632:\nadd [rbp+var_C48], 1\nloc_1639:\ncmp [rbp+var_C48], 0FFh\njle short loc_15DE\nmov eax, [rbp+var_C50]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nsub eax, 1\nmov [rbp+var_C44], eax\njmp short loc_1683\nloc_165F:\nmov ecx, [rbp+var_C50]\nmov edx, [rbp+var_C44]\nlea rax, [rbp+var_810]\nmov esi, ecx\nmov rdi, rax\ncall sub_1256\nsub [rbp+var_C44], 1\nloc_1683:\ncmp [rbp+var_C44], 0\njns short loc_165F\nmov eax, [rbp+var_C50]\ntest eax, eax\njle short loc_16DD\nmov eax, dword ptr [rbp+var_810]\nlea edx, [rax+rax]\nmov eax, [rbp+var_C3C]\nadd eax, 1\ncmp edx, eax\njle short loc_16DD\nmov edi, 1; size\ncall _malloc\nmov [rbp+var_C38], rax\ncmp [rbp+var_C38], 0\njz short loc_16D1\nmov rax, [rbp+var_C38]\nmov byte ptr [rax], 0\nloc_16D1:\nmov rax, [rbp+var_C38]\njmp loc_187D\nloc_16DD:\nmov eax, [rbp+var_C3C]\nadd eax, 1\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_C30], rax\nmov [rbp+var_C40], 0\njmp loc_1802\nloc_1706:\nlea rdx, [rbp+var_C50]\nlea rax, [rbp+var_810]\nmov rsi, rdx\nmov rdi, rax\ncall sub_147F\nmov [rbp+var_C20], rax\nlea rdx, [rbp+var_C50]\nlea rax, [rbp+var_810]\nmov rsi, rdx\nmov rdi, rax\ncall sub_147F\nmov [rbp+var_C18], rax\nmov eax, [rbp+var_C40]\nlea edx, [rax+1]\nmov [rbp+var_C40], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_C30]\nadd rdx, rax\nmovzx eax, byte ptr [rbp+var_C20+4]\nmov [rdx], al\nmov eax, [rbp+var_C40]\nlea edx, [rax+1]\nmov [rbp+var_C40], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_C30]\nadd rdx, rax\nmovzx eax, byte ptr [rbp+var_C18+4]\nmov [rdx], al\nmov eax, dword ptr [rbp+var_C20]\nsub eax, 1\nmov dword ptr [rbp+var_C20], eax\nmov eax, dword ptr [rbp+var_C18]\nsub eax, 1\nmov dword ptr [rbp+var_C18], eax\nmov eax, dword ptr [rbp+var_C20]\ntest eax, eax\njle short loc_17D8\nmov rdx, [rbp+var_C20]\nlea rcx, [rbp+var_C50]\nlea rax, [rbp+var_810]\nmov rsi, rcx\nmov rdi, rax\ncall sub_1420\nloc_17D8:\nmov eax, dword ptr [rbp+var_C18]\ntest eax, eax\njle short loc_1802\nmov rdx, [rbp+var_C18]\nlea rcx, [rbp+var_C50]\nlea rax, [rbp+var_810]\nmov rsi, rcx\nmov rdi, rax\ncall sub_1420\nloc_1802:\nmov eax, [rbp+var_C50]\ncmp eax, 1\njg loc_1706\nmov eax, [rbp+var_C50]\ntest eax, eax\njle short loc_1860\nlea rdx, [rbp+var_C50]\nlea rax, [rbp+var_810]\nmov rsi, rdx\nmov rdi, rax\ncall sub_147F\nmov [rbp+var_C18], rax\nmov eax, [rbp+var_C40]\nlea edx, [rax+1]\nmov [rbp+var_C40], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_C30]\nadd rdx, rax\nmovzx eax, byte ptr [rbp+var_C18+4]\nmov [rdx], al\nloc_1860:\nmov eax, [rbp+var_C40]\nmovsxd rdx, eax\nmov rax, [rbp+var_C30]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+var_C30]\nloc_187D:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1891\ncall ___stack_chk_fail\nlocret_1891:\nleave\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_14ED(const char *a1)\n{\n int v2; // eax\n int v3; // eax\n int v4; // eax\n int v5; // eax\n int v6; // [rsp+10h] [rbp-C50h] BYREF\n int i; // [rsp+14h] [rbp-C4Ch]\n int j; // [rsp+18h] [rbp-C48h]\n int k; // [rsp+1Ch] [rbp-C44h]\n int v10; // [rsp+20h] [rbp-C40h]\n int v11; // [rsp+24h] [rbp-C3Ch]\n _BYTE *v12; // [rsp+28h] [rbp-C38h]\n _BYTE *v13; // [rsp+30h] [rbp-C30h]\n _BYTE *v14; // [rsp+38h] [rbp-C28h]\n __int64 v15; // [rsp+40h] [rbp-C20h]\n __int64 v16; // [rsp+48h] [rbp-C18h]\n _DWORD v17[256]; // [rsp+50h] [rbp-C10h] BYREF\n _QWORD v18[258]; // [rsp+450h] [rbp-810h] BYREF\n\n v18[257] = __readfsqword(0x28u);\n v11 = strlen(a1);\n if ( v11 )\n {\n memset(v17, 0, sizeof(v17));\n for ( i = 0; i < v11; ++i )\n ++v17[(unsigned __int8)a1[i]];\n v6 = 0;\n for ( j = 0; j <= 255; ++j )\n {\n if ( (int)v17[j] > 0 )\n {\n LODWORD(v16) = v17[j];\n BYTE4(v16) = j;\n v2 = v6++;\n v18[v2] = v16;\n }\n }\n for ( k = v6 / 2 - 1; k >= 0; --k )\n sub_1256(v18, (unsigned int)v6, (unsigned int)k);\n if ( v6 <= 0 || 2 * LODWORD(v18[0]) <= v11 + 1 )\n {\n v13 = malloc(v11 + 1);\n v10 = 0;\n while ( v6 > 1 )\n {\n v15 = sub_147F(v18, &v6);\n v16 = sub_147F(v18, &v6);\n v3 = v10++;\n v13[v3] = BYTE4(v15);\n v4 = v10++;\n v13[v4] = BYTE4(v16);\n LODWORD(v15) = v15 - 1;\n LODWORD(v16) = v16 - 1;\n if ( (int)v15 > 0 )\n sub_1420(v18, &v6, v15);\n if ( (int)v16 > 0 )\n sub_1420(v18, &v6, v16);\n }\n if ( v6 > 0 )\n {\n v16 = sub_147F(v18, &v6);\n v5 = v10++;\n v13[v5] = BYTE4(v16);\n }\n v13[v10] = 0;\n return v13;\n }\n else\n {\n v12 = malloc(1uLL);\n if ( v12 )\n *v12 = 0;\n return v12;\n }\n }\n else\n {\n v14 = malloc(1uLL);\n if ( v14 )\n *v14 = 0;\n return v14;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_14ED(const char *a1) {\n int v2;\n int v3;\n int v4;\n int v5;\n int v6;\n int i;\n int j;\n int k;\n int v10;\n int v11;\n uint8_t *v12;\n uint8_t *v13;\n uint8_t *v14;\n long long v15;\n long long v16;\n uint32_t v17[256];\n uint64_t v18[258];\n v18[257] = __readfsqword(40u);\n v11 = strlen(a1);\n if (v11) {\n memset(v17, 0, sizeof(v17));\n for (i = 0; i < v11; ++i) ++v17[(unsigned char)a1[i]];\n v6 = 0;\n for (j = 0; j <= 255; ++j) {\n if ((int)v17[j] > 0) {\n LODWORD(v16) = v17[j];\n BYTE4(v16) = j;\n v2 = v6++;\n v18[v2] = v16;\n }\n }\n for (k = v6 / 2 - 1; k >= 0; --k)\n sub_1256(v18, (unsigned int)v6, (unsigned int)k);\n if (v6 <= 0 || 2 * LODWORD(v18[0]) <= v11 + 1) {\n v13 = malloc(v11 + 1);\n v10 = 0;\n while (v6 > 1) {\n v15 = sub_147F(v18, &v6);\n v16 = sub_147F(v18, &v6);\n v3 = v10++;\n v13[v3] = BYTE4(v15);\n v4 = v10++;\n v13[v4] = BYTE4(v16);\n LODWORD(v15) = v15 - 1;\n LODWORD(v16) = v16 - 1;\n if ((int)v15 > 0) sub_1420(v18, &v6, v15);\n if ((int)v16 > 0) sub_1420(v18, &v6, v16);\n }\n if (v6 > 0) {\n v16 = sub_147F(v18, &v6);\n v5 = v10++;\n v13[v5] = BYTE4(v16);\n }\n v13[v10] = 0;\n return v13;\n } else {\n v12 = malloc(1uLL);\n if (v12) *v12 = 0;\n return v12;\n }\n } else {\n v14 = malloc(1uLL);\n if (v14) *v14 = 0;\n return v14;\n }\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1) {\n int v2;\n int v3;\n int v4;\n int v5;\n int v6;\n int i;\n int j;\n int k;\n int v10;\n int v11;\n uint8_t *v12;\n uint8_t *v13;\n uint8_t *v14;\n long long v15;\n long long v16;\n uint32_t v17[256];\n uint64_t v18[258];\n v18[257] = __readfsqword(40u);\n v11 = strlen(a1);\n if (v11) {\n memset(v17, 0, sizeof(v17));\n for (i = 0; i < v11; ++i) ++v17[(unsigned char)a1[i]];\n v6 = 0;\n for (j = 0; j <= 255; ++j) {\n if ((int)v17[j] > 0) {\n LODWORD(v16) = v17[j];\n BYTE4(v16) = j;\n v2 = v6++;\n v18[v2] = v16;\n }\n }\n for (k = v6 / 2 - 1; k >= 0; --k)\n heapify_down(v18, (unsigned int)v6, (unsigned int)k);\n if (v6 <= 0 || 2 * LODWORD(v18[0]) <= v11 + 1) {\n v13 = malloc(v11 + 1);\n v10 = 0;\n while (v6 > 1) {\n v15 = heap_pop(v18, &v6);\n v16 = heap_pop(v18, &v6);\n v3 = v10++;\n v13[v3] = BYTE4(v15);\n v4 = v10++;\n v13[v4] = BYTE4(v16);\n LODWORD(v15) = v15 - 1;\n LODWORD(v16) = v16 - 1;\n if ((int)v15 > 0) heap_push(v18, &v6, v15);\n if ((int)v16 > 0) heap_push(v18, &v6, v16);\n }\n if (v6 > 0) {\n v16 = heap_pop(v18, &v6);\n v5 = v10++;\n v13[v5] = BYTE4(v16);\n }\n v13[v10] = 0;\n return v13;\n } else {\n v12 = malloc(1uLL);\n if (v12) *v12 = 0;\n return v12;\n }\n } else {\n v14 = malloc(1uLL);\n if (v14) *v14 = 0;\n return v14;\n }\n}" + }, + { + "index": 39, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int freq;\n\n char ch;\n\n} HeapNode;\n\n\n\nvoid swap(HeapNode *a, HeapNode *b) {\n\n HeapNode temp = *a;\n\n *a = *b;\n\n *b = temp;\n\n}\n\n\n\nint compare(HeapNode a, HeapNode b) {\n\n // Higher frequency has higher priority.\n\n // If frequency equal, smaller char (lexicographically) has higher priority.\n\n if(a.freq != b.freq)\n\n return a.freq - b.freq; // positive if a.freq > b.freq.\n\n else\n\n return (b.ch - a.ch); // if a.ch < b.ch then priority: a\n\n}\n\n\n\nvoid heapify_down(HeapNode heap[], int n, int idx) {\n\n int largest = idx;\n\n int left = 2*idx + 1;\n\n int right = 2*idx + 2;\n\n if(left < n && (compare(heap[left], heap[largest]) > 0))\n\n largest = left;\n\n if(right < n && (compare(heap[right], heap[largest]) > 0))\n\n largest = right;\n\n if(largest != idx) {\n\n swap(&heap[idx], &heap[largest]);\n\n heapify_down(heap, n, largest);\n\n }\n\n}\n\n\n\nvoid heapify_up(HeapNode heap[], int idx) {\n\n while(idx > 0) {\n\n int parent = (idx - 1)/2;\n\n if(compare(heap[idx], heap[parent]) > 0) {\n\n swap(&heap[idx], &heap[parent]);\n\n idx = parent;\n\n } else {\n\n break;\n\n }\n\n }\n\n}\n\n\n\nvoid heap_push(HeapNode heap[], int *n, HeapNode node) {\n\n heap[*n] = node;\n\n (*n)++;\n\n heapify_up(heap, (*n)-1);\n\n}\n\n\n\nHeapNode heap_pop(HeapNode heap[], int *n) {\n\n HeapNode top = heap[0];\n\n heap[0] = heap[(*n)-1];\n\n (*n)--;\n\n heapify_down(heap, *n, 0);\n\n return top;\n\n}\n\n\n\n", + "func": "char *func0(const char *S) {\n int len = strlen(S);\n if (len == 0) {\n char *empty = malloc(1);\n if (empty) empty[0] = '\\0';\n return empty;\n }\n int freq[256] = {0};\n for (int i = 0; i < len; i++) {\n freq[(unsigned char)S[i]]++;\n }\n HeapNode heap[256];\n int heapSize = 0;\n for (int i = 0; i < 256; i++) {\n if (freq[i] > 0) {\n HeapNode node;\n node.freq = freq[i];\n node.ch = (char)i;\n heap[heapSize++] = node;\n }\n }\n for (int i = (heapSize / 2) - 1; i >= 0; i--) {\n heapify_down(heap, heapSize, i);\n }\n if (heapSize > 0 && heap[0].freq * 2 > len + 1) {\n char *empty = malloc(1);\n if (empty) empty[0] = '\\0';\n return empty;\n }\n char *result = malloc(len + 1);\n int pos = 0;\n while (heapSize >= 2) {\n HeapNode first = heap_pop(heap, &heapSize);\n HeapNode second = heap_pop(heap, &heapSize);\n result[pos++] = first.ch;\n result[pos++] = second.ch;\n first.freq--;\n second.freq--;\n if (first.freq > 0) {\n heap_push(heap, &heapSize, first);\n }\n if (second.freq > 0) {\n heap_push(heap, &heapSize, second);\n }\n }\n if (heapSize > 0) {\n HeapNode last = heap_pop(heap, &heapSize);\n result[pos++] = last.ch;\n }\n result[pos] = '\\0';\n return result;\n}", + "test": "int main() {\n\n char *res1 = func0(\"aab\");\n\n // The expected output is \"aba\"\n\n assert(strcmp(res1, \"aba\") == 0);\n\n free(res1);\n\n \n\n char *res2 = func0(\"aabb\");\n\n // The expected output is \"abab\"\n\n assert(strcmp(res2, \"abab\") == 0);\n\n free(res2);\n\n \n\n char *res3 = func0(\"abccdd\");\n\n // The expected output is \"cdabcd\"\n\n assert(strcmp(res3, \"cdabcd\") == 0);\n\n free(res3);\n\n \n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0xc38,%rsp\nmov %rdi,%rdx\nmov %fs:0x28,%rax\nmov %rax,0xc28(%rsp)\nxor %eax,%eax\nmov $0xffffffffffffffff,%rcx\nrepnz scas %es:(%rdi),%al\nnot %rcx\ncmp $0x1,%ecx\nje 140e \nlea -0x1(%rcx),%rbx\nlea 0x20(%rsp),%rdi\nmov $0x80,%ecx\nmov $0x0,%eax\nrep stos %rax,%es:(%rdi)\ntest %ebx,%ebx\njle 13e8 \nmov %rdx,%rax\nlea -0x1(%rbx),%ecx\nlea 0x1(%rdx,%rcx,1),%rcx\nmovzbl (%rax),%edx\naddl $0x1,0x20(%rsp,%rdx,4)\nadd $0x1,%rax\ncmp %rcx,%rax\njne 13d7 \nmovl $0x0,0x1c(%rsp)\nmov $0x0,%eax\nmov $0x0,%esi\nmov $0x0,%ecx\nlea 0x420(%rsp),%r8\nmov $0x1,%edi\njmp 1438 \nmov $0x1,%edi\ncallq 10b0 \nmov %rax,%r14\ntest %rax,%rax\nje 15b1 \nmovb $0x0,(%rax)\njmpq 15b1 \nadd $0x1,%rax\ncmp $0x100,%rax\nje 1453 \nmov 0x20(%rsp,%rax,4),%edx\ntest %edx,%edx\njle 142c \nmovslq %ecx,%rsi\nlea (%r8,%rsi,8),%rsi\nmov %edx,(%rsi)\nmov %al,0x4(%rsi)\nlea 0x1(%rcx),%ecx\nmov %edi,%esi\njmp 142c \ntest %sil,%sil\nje 148a \nmov %ecx,0x1c(%rsp)\nmov %ecx,%eax\nshr $0x1f,%eax\nadd %eax,%ecx\nsar %ecx\nsub $0x1,%ecx\nmov %ecx,%ebp\njs 148a \nlea 0x420(%rsp),%r12\nmov %ebp,%edx\nmov 0x1c(%rsp),%esi\nmov %r12,%rdi\ncallq 11e2 \nsub $0x1,%ebp\ncmp $0xffffffff,%ebp\njne 1474 \ncmpl $0x0,0x1c(%rsp)\njle 14a1 \nmov 0x420(%rsp),%eax\nadd %eax,%eax\nlea 0x1(%rbx),%edx\ncmp %edx,%eax\njg 14ce \nlea 0x1(%rbx),%edi\nmovslq %edi,%rdi\ncallq 10b0 \nmov %rax,%r14\nmov 0x1c(%rsp),%eax\ncmp $0x1,%eax\njle 159b \nmov $0x2,%r12d\nmovabs $0xffffffff00000000,%r15\njmp 1519 \nmov $0x1,%edi\ncallq 10b0 \nmov %rax,%r14\ntest %rax,%rax\nje 15b1 \nmovb $0x0,(%rax)\njmpq 15b1 \nmov %edx,%edx\nand %r15,%rbp\nor %rbp,%rdx\nlea 0x1c(%rsp),%rsi\nlea 0x420(%rsp),%rdi\ncallq 1317 \njmp 1576 \nmov 0x1c(%rsp),%eax\nadd $0x2,%r12\ncmp $0x1,%eax\njle 15a3 \nlea 0x1c(%rsp),%r13\nlea 0x420(%rsp),%rbx\nmov %r13,%rsi\nmov %rbx,%rdi\ncallq 1331 \nmov %rax,%rbp\nmov %r13,%rsi\nmov %rbx,%rdi\ncallq 1331 \nmov %rax,%rbx\nmov %rbp,%rax\nshl $0x18,%rax\nsar $0x38,%rax\nmov %al,-0x2(%r14,%r12,1)\nmov %r12d,0xc(%rsp)\nmov %rbx,%rax\nshl $0x18,%rax\nsar $0x38,%rax\nmov %al,-0x1(%r14,%r12,1)\nlea -0x1(%rbp),%edx\nlea -0x1(%rbx),%r13d\ntest %edx,%edx\njg 14ec \ntest %r13d,%r13d\njle 1508 \nmov %r13d,%edx\nand %r15,%rbx\nor %rbx,%rdx\nlea 0x1c(%rsp),%rsi\nlea 0x420(%rsp),%rdi\ncallq 1317 \njmpq 1508 \nmovl $0x0,0xc(%rsp)\ntest %eax,%eax\njg 15d9 \nmovslq 0xc(%rsp),%rax\nmovb $0x0,(%r14,%rax,1)\nmov 0xc28(%rsp),%rax\nxor %fs:0x28,%rax\njne 1607 \nmov %r14,%rax\nadd $0xc38,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nlea 0x1c(%rsp),%rsi\nlea 0x420(%rsp),%rdi\ncallq 1331 \nmov 0xc(%rsp),%ebx\nmovslq %ebx,%rdx\nshl $0x18,%rax\nsar $0x38,%rax\nmov %al,(%r14,%rdx,1)\nlea 0x1(%rbx),%eax\nmov %eax,0xc(%rsp)\njmp 15a7 \ncallq 1090 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 0C28h\nmov rbp, rdi\nmov rax, fs:28h\nmov [rsp+0C58h+var_40], rax\nxor eax, eax\ncall _strlen\ntest eax, eax\njz short loc_143E\nmov rbx, rax\nlea rdi, [rsp+0C58h+var_C48]\nmov ecx, 80h\nmov eax, 0\nrep stosq\njle short loc_1420\nmov rax, rbp\nlea edx, [rbx-1]\nlea rcx, [rbp+rdx+1]\nloc_140F:\nmovzx edx, byte ptr [rax]\nadd [rsp+rdx*4+0C58h+var_C48], 1\nadd rax, 1\ncmp rax, rcx\njnz short loc_140F\nloc_1420:\nmov [rsp+0C58h+var_C4C], 0\nmov eax, 0\nmov esi, 0\nmov ecx, 0\nmov edi, 1\njmp short loc_147E\nloc_143E:\nmov edi, 1; size\ncall _malloc\nmov r13, rax\ntest rax, rax\njz loc_15E2\nmov byte ptr [rax], 0\njmp loc_15E2\nloc_145C:\nmovsxd rsi, ecx\nmov [rsp+rsi*8+0C58h+var_848], edx\nmov [rsp+rsi*8+0C58h+var_844], al\nlea ecx, [rcx+1]\nmov esi, edi\nloc_1472:\nadd rax, 1\ncmp rax, 100h\njz short loc_1488\nloc_147E:\nmov edx, [rsp+rax*4+0C58h+var_C48]\ntest edx, edx\njg short loc_145C\njmp short loc_1472\nloc_1488:\ntest sil, sil\njz loc_164F\nmov [rsp+0C58h+var_C4C], ecx\nmov r12d, ecx\nmov ebp, ecx\nshr ebp, 1Fh\nadd ebp, ecx\nsar ebp, 1\nsub ebp, 1\njs short loc_14C3\nlea r13, [rsp+0C58h+var_848]\nloc_14AE:\nmov edx, ebp\nmov esi, r12d\nmov rdi, r13\ncall heapify_down\nsub ebp, 1\ncmp ebp, 0FFFFFFFFh\njnz short loc_14AE\nloc_14C3:\ntest r12d, r12d\njle loc_1639\nadd ebx, 1\nmov eax, [rsp+0C58h+var_848]\nadd eax, eax\ncmp eax, ebx\njg short loc_1503\nmovsxd rdi, ebx; size\ncall _malloc\nmov r13, rax\ncmp r12d, 1\njle loc_160A\nmov r12d, 2\nmov r14, 0FFFFFFFF00000000h\njmp short loc_1555\nloc_1503:\nmov edi, 1; size\ncall _malloc\nmov r13, rax\ntest rax, rax\njz loc_15E2\nmov byte ptr [rax], 0\njmp loc_15E2\nloc_1521:\nmov eax, eax\nmov rdx, rbp\nand rdx, r14\nor rdx, rax\nlea rsi, [rsp+0C58h+var_C4C]\nlea rdi, [rsp+0C58h+var_848]\ncall heap_push\njmp short loc_15AD\nloc_1540:\nmov eax, [rsp+0C58h+var_C4C]\nlea rdx, [r12+2]\ncmp eax, 1\njle loc_15D5\nmov r12, rdx\nloc_1555:\nlea r15, [rsp+0C58h+var_C4C]\nlea rbx, [rsp+0C58h+var_848]\nmov rsi, r15\nmov rdi, rbx\ncall heap_pop\nmov rbp, rax\nmov rsi, r15\nmov rdi, rbx\ncall heap_pop\nmov rbx, rax\nmov rax, rbp\nshl rax, 18h\nsar rax, 38h\nmov [r13+r12-2], al\nmov rax, rbx\nshl rax, 18h\nsar rax, 38h\nmov [r13+r12-1], al\nlea eax, [rbp-1]\nlea r15d, [rbx-1]\ntest eax, eax\njg loc_1521\nloc_15AD:\ntest r15d, r15d\njle short loc_1540\nmov r15d, r15d\nand rbx, r14\nmov rdx, rbx\nor rdx, r15\nlea rsi, [rsp+0C58h+var_C4C]\nlea rdi, [rsp+0C58h+var_848]\ncall heap_push\njmp loc_1540\nloc_15D5:\ntest eax, eax\njg short loc_1610\nloc_15D9:\nmovsxd r12, r12d\nmov byte ptr [r13+r12+0], 0\nloc_15E2:\nmov rax, [rsp+0C58h+var_40]\nsub rax, fs:28h\njnz short loc_1659\nmov rax, r13\nadd rsp, 0C28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_160A:\nmov r12d, 0\nloc_1610:\nlea rsi, [rsp+0C58h+var_C4C]\nlea rdi, [rsp+0C58h+var_848]\ncall heap_pop\nmovsxd rdx, r12d\nshl rax, 18h\nsar rax, 38h\nmov [r13+rdx+0], al\nlea r12d, [r12+1]\njmp short loc_15D9\nloc_1639:\nlea edi, [rbx+1]\nmovsxd rdi, edi; size\ncall _malloc\nmov r13, rax\nmov r12d, 0\njmp short loc_15D9\nloc_164F:\nmov r12d, [rsp+0C58h+var_C4C]\njmp loc_14C3\nloc_1659:\ncall ___stack_chk_fail", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1)\n{\n int v1; // eax\n int v2; // ebx\n const char *v3; // rax\n __int64 v4; // rax\n char v5; // si\n int v6; // ecx\n _BYTE *v7; // rax\n _BYTE *v8; // r13\n int v9; // edx\n int v10; // r12d\n int v11; // ebp\n int v12; // ebx\n __int64 i; // r12\n _BYTE *v14; // rax\n __int64 v15; // rbp\n __int64 v16; // rbx\n int v17; // r15d\n int v19; // [rsp+Ch] [rbp-C4Ch] BYREF\n _DWORD v20[256]; // [rsp+10h] [rbp-C48h] BYREF\n _DWORD v21[514]; // [rsp+410h] [rbp-848h] BYREF\n unsigned __int64 v22; // [rsp+C18h] [rbp-40h]\n\n v22 = __readfsqword(0x28u);\n v1 = strlen(a1);\n if ( v1 )\n {\n v2 = v1;\n memset(v20, 0, sizeof(v20));\n if ( v1 > 0 )\n {\n v3 = a1;\n do\n ++v20[*(unsigned __int8 *)v3++];\n while ( v3 != &a1[v2 - 1 + 1] );\n }\n v19 = 0;\n v4 = 0LL;\n v5 = 0;\n v6 = 0;\n do\n {\n v9 = v20[v4];\n if ( v9 > 0 )\n {\n v21[2 * v6] = v9;\n LOBYTE(v21[2 * v6++ + 1]) = v4;\n v5 = 1;\n }\n ++v4;\n }\n while ( v4 != 256 );\n if ( v5 )\n {\n v19 = v6;\n v10 = v6;\n v11 = v6 / 2 - 1;\n if ( v11 >= 0 )\n {\n do\n heapify_down(v21, (unsigned int)v10, (unsigned int)v11--);\n while ( v11 != -1 );\n }\n }\n else\n {\n v10 = v19;\n }\n if ( v10 <= 0 )\n {\n v8 = malloc(v2 + 1);\n LODWORD(i) = 0;\n goto LABEL_28;\n }\n v12 = v2 + 1;\n if ( 2 * v21[0] <= v12 )\n {\n v8 = malloc(v12);\n if ( v10 <= 1 )\n {\n LODWORD(i) = 0;\n }\n else\n {\n for ( i = 2LL; ; i += 2LL )\n {\n v15 = heap_pop(v21, &v19);\n v16 = heap_pop(v21, &v19);\n v8[i - 2] = (unsigned __int64)(v15 << 24) >> 56;\n v8[i - 1] = (unsigned __int64)(v16 << 24) >> 56;\n v17 = v16 - 1;\n if ( (int)v15 - 1 > 0 )\n heap_push(v21, &v19, (unsigned int)(v15 - 1) | v15 & 0xFFFFFFFF00000000LL);\n if ( v17 > 0 )\n heap_push(v21, &v19, (unsigned int)v17 | v16 & 0xFFFFFFFF00000000LL);\n if ( v19 <= 1 )\n break;\n }\n if ( v19 <= 0 )\n goto LABEL_28;\n }\n v8[(int)i] = (unsigned __int64)(heap_pop(v21, &v19) << 24) >> 56;\n LODWORD(i) = i + 1;\nLABEL_28:\n v8[(int)i] = 0;\n return v8;\n }\n v14 = malloc(1uLL);\n v8 = v14;\n if ( v14 )\n *v14 = 0;\n }\n else\n {\n v7 = malloc(1uLL);\n v8 = v7;\n if ( v7 )\n *v7 = 0;\n }\n return v8;\n}", + "ida_strip_asm": "sub_13B9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 0C28h\nmov rbp, rdi\nmov rax, fs:28h\nmov [rsp+0C58h+var_40], rax\nxor eax, eax\ncall _strlen\ntest eax, eax\njz short loc_143E\nmov rbx, rax\nlea rdi, [rsp+0C58h+var_C48]\nmov ecx, 80h\nmov eax, 0\nrep stosq\njle short loc_1420\nmov rax, rbp\nlea edx, [rbx-1]\nlea rcx, [rbp+rdx+1]\nloc_140F:\nmovzx edx, byte ptr [rax]\nadd [rsp+rdx*4+0C58h+var_C48], 1\nadd rax, 1\ncmp rax, rcx\njnz short loc_140F\nloc_1420:\nmov [rsp+0C58h+var_C4C], 0\nmov eax, 0\nmov esi, 0\nmov ecx, 0\nmov edi, 1\njmp short loc_147E\nloc_143E:\nmov edi, 1; size\ncall _malloc\nmov r13, rax\ntest rax, rax\njz loc_15E2\nmov byte ptr [rax], 0\njmp loc_15E2\nloc_145C:\nmovsxd rsi, ecx\nmov [rsp+rsi*8+0C58h+var_848], edx\nmov [rsp+rsi*8+0C58h+var_844], al\nlea ecx, [rcx+1]\nmov esi, edi\nloc_1472:\nadd rax, 1\ncmp rax, 100h\njz short loc_1488\nloc_147E:\nmov edx, [rsp+rax*4+0C58h+var_C48]\ntest edx, edx\njg short loc_145C\njmp short loc_1472\nloc_1488:\ntest sil, sil\njz loc_164F\nmov [rsp+0C58h+var_C4C], ecx\nmov r12d, ecx\nmov ebp, ecx\nshr ebp, 1Fh\nadd ebp, ecx\nsar ebp, 1\nsub ebp, 1\njs short loc_14C3\nlea r13, [rsp+0C58h+var_848]\nloc_14AE:\nmov edx, ebp\nmov esi, r12d\nmov rdi, r13\ncall sub_1221\nsub ebp, 1\ncmp ebp, 0FFFFFFFFh\njnz short loc_14AE\nloc_14C3:\ntest r12d, r12d\njle loc_1639\nadd ebx, 1\nmov eax, [rsp+0C58h+var_848]\nadd eax, eax\ncmp eax, ebx\njg short loc_1503\nmovsxd rdi, ebx; size\ncall _malloc\nmov r13, rax\ncmp r12d, 1\njle loc_160A\nmov r12d, 2\nmov r14, 0FFFFFFFF00000000h\njmp short loc_1555\nloc_1503:\nmov edi, 1; size\ncall _malloc\nmov r13, rax\ntest rax, rax\njz loc_15E2\nmov byte ptr [rax], 0\njmp loc_15E2\nloc_1521:\nmov eax, eax\nmov rdx, rbp\nand rdx, r14\nor rdx, rax\nlea rsi, [rsp+0C58h+var_C4C]\nlea rdi, [rsp+0C58h+var_848]\ncall sub_135D\njmp short loc_15AD\nloc_1540:\nmov eax, [rsp+0C58h+var_C4C]\nlea rdx, [r12+2]\ncmp eax, 1\njle loc_15D5\nmov r12, rdx\nloc_1555:\nlea r15, [rsp+0C58h+var_C4C]\nlea rbx, [rsp+0C58h+var_848]\nmov rsi, r15\nmov rdi, rbx\ncall sub_1377\nmov rbp, rax\nmov rsi, r15\nmov rdi, rbx\ncall sub_1377\nmov rbx, rax\nmov rax, rbp\nshl rax, 18h\nsar rax, 38h\nmov [r13+r12-2], al\nmov rax, rbx\nshl rax, 18h\nsar rax, 38h\nmov [r13+r12-1], al\nlea eax, [rbp-1]\nlea r15d, [rbx-1]\ntest eax, eax\njg loc_1521\nloc_15AD:\ntest r15d, r15d\njle short loc_1540\nmov r15d, r15d\nand rbx, r14\nmov rdx, rbx\nor rdx, r15\nlea rsi, [rsp+0C58h+var_C4C]\nlea rdi, [rsp+0C58h+var_848]\ncall sub_135D\njmp loc_1540\nloc_15D5:\ntest eax, eax\njg short loc_1610\nloc_15D9:\nmovsxd r12, r12d\nmov byte ptr [r13+r12+0], 0\nloc_15E2:\nmov rax, [rsp+0C58h+var_40]\nsub rax, fs:28h\njnz short loc_1659\nmov rax, r13\nadd rsp, 0C28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_160A:\nmov r12d, 0\nloc_1610:\nlea rsi, [rsp+0C58h+var_C4C]\nlea rdi, [rsp+0C58h+var_848]\ncall sub_1377\nmovsxd rdx, r12d\nshl rax, 18h\nsar rax, 38h\nmov [r13+rdx+0], al\nlea r12d, [r12+1]\njmp short loc_15D9\nloc_1639:\nlea edi, [rbx+1]\nmovsxd rdi, edi; size\ncall _malloc\nmov r13, rax\nmov r12d, 0\njmp short loc_15D9\nloc_164F:\nmov r12d, [rsp+0C58h+var_C4C]\njmp loc_14C3\nloc_1659:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_BYTE *__fastcall sub_13B9(const char *a1)\n{\n int v1; // eax\n int v2; // ebx\n const char *v3; // rax\n __int64 v4; // rax\n char v5; // si\n int v6; // ecx\n _BYTE *v7; // rax\n _BYTE *v8; // r13\n int v9; // edx\n int v10; // r12d\n int v11; // ebp\n int v12; // ebx\n __int64 i; // r12\n _BYTE *v14; // rax\n __int64 v15; // rbp\n __int64 v16; // rbx\n int v17; // r15d\n int v19; // [rsp+Ch] [rbp-C4Ch] BYREF\n _DWORD v20[256]; // [rsp+10h] [rbp-C48h] BYREF\n _DWORD v21[514]; // [rsp+410h] [rbp-848h] BYREF\n unsigned __int64 v22; // [rsp+C18h] [rbp-40h]\n\n v22 = __readfsqword(0x28u);\n v1 = strlen(a1);\n if ( v1 )\n {\n v2 = v1;\n memset(v20, 0, sizeof(v20));\n if ( v1 > 0 )\n {\n v3 = a1;\n do\n ++v20[*(unsigned __int8 *)v3++];\n while ( v3 != &a1[v2 - 1 + 1] );\n }\n v19 = 0;\n v4 = 0LL;\n v5 = 0;\n v6 = 0;\n do\n {\n v9 = v20[v4];\n if ( v9 > 0 )\n {\n v21[2 * v6] = v9;\n LOBYTE(v21[2 * v6++ + 1]) = v4;\n v5 = 1;\n }\n ++v4;\n }\n while ( v4 != 256 );\n if ( v5 )\n {\n v19 = v6;\n v10 = v6;\n v11 = v6 / 2 - 1;\n if ( v11 >= 0 )\n {\n do\n sub_1221(v21, (unsigned int)v10, (unsigned int)v11--);\n while ( v11 != -1 );\n }\n }\n else\n {\n v10 = v19;\n }\n if ( v10 <= 0 )\n {\n v8 = malloc(v2 + 1);\n LODWORD(i) = 0;\n goto LABEL_28;\n }\n v12 = v2 + 1;\n if ( 2 * v21[0] <= v12 )\n {\n v8 = malloc(v12);\n if ( v10 <= 1 )\n {\n LODWORD(i) = 0;\n }\n else\n {\n for ( i = 2LL; ; i += 2LL )\n {\n v15 = sub_1377(v21, &v19);\n v16 = sub_1377(v21, &v19);\n v8[i - 2] = (unsigned __int64)(v15 << 24) >> 56;\n v8[i - 1] = (unsigned __int64)(v16 << 24) >> 56;\n v17 = v16 - 1;\n if ( (int)v15 - 1 > 0 )\n sub_135D(v21, &v19, (unsigned int)(v15 - 1) | v15 & 0xFFFFFFFF00000000LL);\n if ( v17 > 0 )\n sub_135D(v21, &v19, (unsigned int)v17 | v16 & 0xFFFFFFFF00000000LL);\n if ( v19 <= 1 )\n break;\n }\n if ( v19 <= 0 )\n goto LABEL_28;\n }\n v8[(int)i] = (unsigned __int64)(sub_1377(v21, &v19) << 24) >> 56;\n LODWORD(i) = i + 1;\nLABEL_28:\n v8[(int)i] = 0;\n return v8;\n }\n v14 = malloc(1uLL);\n v8 = v14;\n if ( v14 )\n *v14 = 0;\n }\n else\n {\n v7 = malloc(1uLL);\n v8 = v7;\n if ( v7 )\n *v7 = 0;\n }\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_13B9(const char *a1) {\n int v1;\n int v2;\n const char *v3;\n long long v4;\n char v5;\n int v6;\n uint8_t *v7;\n uint8_t *v8;\n int v9;\n int v10;\n int v11;\n int v12;\n long long i;\n uint8_t *v14;\n long long v15;\n long long v16;\n int v17;\n int v19;\n uint32_t v20[256];\n uint32_t v21[514];\n unsigned long long v22;\n v22 = __readfsqword(40u);\n v1 = strlen(a1);\n if (v1) {\n v2 = v1;\n memset(v20, 0, sizeof(v20));\n if (v1 > 0) {\n v3 = a1;\n do\n ++v20[*(unsigned char *)v3++];\n while (v3 != &a1[v2 - 1 + 1]);\n }\n v19 = 0;\n v4 = 0LL;\n v5 = 0;\n v6 = 0;\n do {\n v9 = v20[v4];\n if (v9 > 0) {\n v21[2 * v6] = v9;\n LOBYTE(v21[2 * v6++ + 1]) = v4;\n v5 = 1;\n }\n ++v4;\n } while (v4 != 256);\n if (v5) {\n v19 = v6;\n v10 = v6;\n v11 = v6 / 2 - 1;\n if (v11 >= 0) {\n do\n sub_1221(v21, (unsigned int)v10, (unsigned int)v11--);\n while (v11 != -1);\n }\n } else {\n v10 = v19;\n }\n if (v10 <= 0) {\n v8 = malloc(v2 + 1);\n LODWORD(i) = 0;\n goto LABEL_28;\n }\n v12 = v2 + 1;\n if (2 * v21[0] <= v12) {\n v8 = malloc(v12);\n if (v10 <= 1) {\n LODWORD(i) = 0;\n } else {\n for (i = 2LL;; i += 2LL) {\n v15 = sub_1377(v21, &v19);\n v16 = sub_1377(v21, &v19);\n v8[i - 2] = (unsigned long long)(v15 << 24) >> 56;\n v8[i - 1] = (unsigned long long)(v16 << 24) >> 56;\n v17 = v16 - 1;\n if ((int)v15 - 1 > 0)\n sub_135D(v21, &v19,\n (unsigned int)(v15 - 1) | v15 & 18446744069414584320LL);\n if (v17 > 0)\n sub_135D(v21, &v19,\n (unsigned int)v17 | v16 & 18446744069414584320LL);\n if (v19 <= 1) break;\n }\n if (v19 <= 0) goto LABEL_28;\n }\n v8[(int)i] = (unsigned long long)(sub_1377(v21, &v19) << 24) >> 56;\n LODWORD(i) = i + 1;\n LABEL_28:\n v8[(int)i] = 0;\n return v8;\n }\n v14 = malloc(1uLL);\n v8 = v14;\n if (v14) *v14 = 0;\n } else {\n v7 = malloc(1uLL);\n v8 = v7;\n if (v7) *v7 = 0;\n }\n return v8;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1) {\n int v1;\n int v2;\n const char *v3;\n long long v4;\n char v5;\n int v6;\n uint8_t *v7;\n uint8_t *v8;\n int v9;\n int v10;\n int v11;\n int v12;\n long long i;\n uint8_t *v14;\n long long v15;\n long long v16;\n int v17;\n int v19;\n uint32_t v20[256];\n uint32_t v21[514];\n unsigned long long v22;\n v22 = __readfsqword(40u);\n v1 = strlen(a1);\n if (v1) {\n v2 = v1;\n memset(v20, 0, sizeof(v20));\n if (v1 > 0) {\n v3 = a1;\n do\n ++v20[*(unsigned char *)v3++];\n while (v3 != &a1[v2 - 1 + 1]);\n }\n v19 = 0;\n v4 = 0LL;\n v5 = 0;\n v6 = 0;\n do {\n v9 = v20[v4];\n if (v9 > 0) {\n v21[2 * v6] = v9;\n LOBYTE(v21[2 * v6++ + 1]) = v4;\n v5 = 1;\n }\n ++v4;\n } while (v4 != 256);\n if (v5) {\n v19 = v6;\n v10 = v6;\n v11 = v6 / 2 - 1;\n if (v11 >= 0) {\n do\n heapify_down(v21, (unsigned int)v10, (unsigned int)v11--);\n while (v11 != -1);\n }\n } else {\n v10 = v19;\n }\n if (v10 <= 0) {\n v8 = malloc(v2 + 1);\n LODWORD(i) = 0;\n goto LABEL_28;\n }\n v12 = v2 + 1;\n if (2 * v21[0] <= v12) {\n v8 = malloc(v12);\n if (v10 <= 1) {\n LODWORD(i) = 0;\n } else {\n for (i = 2LL;; i += 2LL) {\n v15 = heap_pop(v21, &v19);\n v16 = heap_pop(v21, &v19);\n v8[i - 2] = (unsigned long long)(v15 << 24) >> 56;\n v8[i - 1] = (unsigned long long)(v16 << 24) >> 56;\n v17 = v16 - 1;\n if ((int)v15 - 1 > 0)\n heap_push(v21, &v19,\n (unsigned int)(v15 - 1) | v15 & 18446744069414584320LL);\n if (v17 > 0)\n heap_push(v21, &v19,\n (unsigned int)v17 | v16 & 18446744069414584320LL);\n if (v19 <= 1) break;\n }\n if (v19 <= 0) goto LABEL_28;\n }\n v8[(int)i] = (unsigned long long)(heap_pop(v21, &v19) << 24) >> 56;\n LODWORD(i) = i + 1;\n LABEL_28:\n v8[(int)i] = 0;\n return v8;\n }\n v14 = malloc(1uLL);\n v8 = v14;\n if (v14) *v14 = 0;\n } else {\n v7 = malloc(1uLL);\n v8 = v7;\n if (v7) *v7 = 0;\n }\n return v8;\n}" + }, + { + "index": 39, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int freq;\n\n char ch;\n\n} HeapNode;\n\n\n\nvoid swap(HeapNode *a, HeapNode *b) {\n\n HeapNode temp = *a;\n\n *a = *b;\n\n *b = temp;\n\n}\n\n\n\nint compare(HeapNode a, HeapNode b) {\n\n // Higher frequency has higher priority.\n\n // If frequency equal, smaller char (lexicographically) has higher priority.\n\n if(a.freq != b.freq)\n\n return a.freq - b.freq; // positive if a.freq > b.freq.\n\n else\n\n return (b.ch - a.ch); // if a.ch < b.ch then priority: a\n\n}\n\n\n\nvoid heapify_down(HeapNode heap[], int n, int idx) {\n\n int largest = idx;\n\n int left = 2*idx + 1;\n\n int right = 2*idx + 2;\n\n if(left < n && (compare(heap[left], heap[largest]) > 0))\n\n largest = left;\n\n if(right < n && (compare(heap[right], heap[largest]) > 0))\n\n largest = right;\n\n if(largest != idx) {\n\n swap(&heap[idx], &heap[largest]);\n\n heapify_down(heap, n, largest);\n\n }\n\n}\n\n\n\nvoid heapify_up(HeapNode heap[], int idx) {\n\n while(idx > 0) {\n\n int parent = (idx - 1)/2;\n\n if(compare(heap[idx], heap[parent]) > 0) {\n\n swap(&heap[idx], &heap[parent]);\n\n idx = parent;\n\n } else {\n\n break;\n\n }\n\n }\n\n}\n\n\n\nvoid heap_push(HeapNode heap[], int *n, HeapNode node) {\n\n heap[*n] = node;\n\n (*n)++;\n\n heapify_up(heap, (*n)-1);\n\n}\n\n\n\nHeapNode heap_pop(HeapNode heap[], int *n) {\n\n HeapNode top = heap[0];\n\n heap[0] = heap[(*n)-1];\n\n (*n)--;\n\n heapify_down(heap, *n, 0);\n\n return top;\n\n}\n\n\n\n", + "func": "char *func0(const char *S) {\n int len = strlen(S);\n if (len == 0) {\n char *empty = malloc(1);\n if (empty) empty[0] = '\\0';\n return empty;\n }\n int freq[256] = {0};\n for (int i = 0; i < len; i++) {\n freq[(unsigned char)S[i]]++;\n }\n HeapNode heap[256];\n int heapSize = 0;\n for (int i = 0; i < 256; i++) {\n if (freq[i] > 0) {\n HeapNode node;\n node.freq = freq[i];\n node.ch = (char)i;\n heap[heapSize++] = node;\n }\n }\n for (int i = (heapSize / 2) - 1; i >= 0; i--) {\n heapify_down(heap, heapSize, i);\n }\n if (heapSize > 0 && heap[0].freq * 2 > len + 1) {\n char *empty = malloc(1);\n if (empty) empty[0] = '\\0';\n return empty;\n }\n char *result = malloc(len + 1);\n int pos = 0;\n while (heapSize >= 2) {\n HeapNode first = heap_pop(heap, &heapSize);\n HeapNode second = heap_pop(heap, &heapSize);\n result[pos++] = first.ch;\n result[pos++] = second.ch;\n first.freq--;\n second.freq--;\n if (first.freq > 0) {\n heap_push(heap, &heapSize, first);\n }\n if (second.freq > 0) {\n heap_push(heap, &heapSize, second);\n }\n }\n if (heapSize > 0) {\n HeapNode last = heap_pop(heap, &heapSize);\n result[pos++] = last.ch;\n }\n result[pos] = '\\0';\n return result;\n}", + "test": "int main() {\n\n char *res1 = func0(\"aab\");\n\n // The expected output is \"aba\"\n\n assert(strcmp(res1, \"aba\") == 0);\n\n free(res1);\n\n \n\n char *res2 = func0(\"aabb\");\n\n // The expected output is \"abab\"\n\n assert(strcmp(res2, \"abab\") == 0);\n\n free(res2);\n\n \n\n char *res3 = func0(\"abccdd\");\n\n // The expected output is \"cdabcd\"\n\n assert(strcmp(res3, \"cdabcd\") == 0);\n\n free(res3);\n\n \n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\nmov %rdi,%rbp\npush %rbx\nsub $0xc38,%rsp\nmov %fs:0x28,%rax\nmov %rax,0xc28(%rsp)\nxor %eax,%eax\ncallq 10a0 \ntest %eax,%eax\nje 16ea \nlea 0x20(%rsp),%r8\nmov %rax,%rbx\nmov $0x80,%ecx\nmov $0x0,%eax\nmov %r8,%rdi\nrep stos %rax,%es:(%rdi)\njle 1734 \nlea -0x1(%rbx),%eax\nmov %rbp,%rdi\nlea 0x1(%rbp,%rax,1),%rdx\nnopl 0x0(%rax)\nmovzbl (%rdi),%eax\nadd $0x1,%rdi\naddl $0x1,0x20(%rsp,%rax,4)\ncmp %rdx,%rdi\njne 1538 \nmov 0x20(%rsp),%edx\nmovl $0x0,0x1c(%rsp)\nxor %eax,%eax\nxor %ecx,%ecx\nxor %esi,%esi\nlea 0x420(%rsp),%rdi\njmp 156c \nnopl (%rax)\nmov (%r8,%rax,4),%edx\ntest %edx,%edx\njle 1584 \nmovslq %esi,%rcx\nadd $0x1,%esi\nlea (%rdi,%rcx,8),%rcx\nmov %edx,(%rcx)\nmov %al,0x4(%rcx)\nmov $0x1,%ecx\nadd $0x1,%rax\ncmp $0x100,%rax\njne 1568 \ntest %cl,%cl\nje 1701 \nmov %esi,%eax\nmov %esi,0x1c(%rsp)\nsar %eax\nlea -0x1(%rax),%ebp\nje 15c3 \nlea 0x420(%rsp),%rdi\nnopl (%rax)\nmov %ebp,%edx\nsub $0x1,%ebp\ncallq 1320 \nmov 0x1c(%rsp),%esi\ncmp $0xffffffff,%ebp\njne 15b0 \nadd $0x1,%ebx\ntest %esi,%esi\njle 15db \nmov 0x420(%rsp),%eax\nadd %eax,%eax\ncmp %ebx,%eax\njg 16ea \nmovslq %ebx,%rdi\ncallq 10d0 \nmov 0x1c(%rsp),%esi\nmov %rax,%r12\ncmp $0x1,%esi\njle 173b \nmov $0x2,%r15d\nlea 0x420(%rsp),%rdi\nlea 0x1c(%rsp),%rbp\nnopw %cs:0x0(%rax,%rax,1)\nmov %rbp,%rsi\ncallq 1490 \nmov %rbp,%rsi\nmov %rax,%rcx\nmov %rax,%rbx\nshl $0x18,%rcx\nsub $0x1,%ebx\nsar $0x38,%rcx\nmov %rcx,%r13\ncallq 1490 \nmov %r13b,-0x2(%r12,%r15,1)\nmov %rax,%rdx\nmov %r15d,0x4(%rsp)\nlea -0x1(%rax),%r14d\nshl $0x18,%rdx\nsar $0x38,%rdx\nmov %dl,-0x1(%r12,%r15,1)\ntest %ebx,%ebx\njle 167e \nmovslq 0x1c(%rsp),%rax\nmov %rdx,0x8(%rsp)\nmov %rax,%rsi\nlea (%rdi,%rax,8),%rax\nmov %ebx,(%rax)\nmov %r13b,0x4(%rax)\nlea 0x1(%rsi),%eax\nmov %eax,0x1c(%rsp)\ncallq 1400 \nmov 0x8(%rsp),%rdx\nmov 0x1c(%rsp),%esi\ntest %r14d,%r14d\njle 16a4 \nmovslq %esi,%rax\nlea (%rdi,%rax,8),%rax\nmov %r14d,(%rax)\nmov %dl,0x4(%rax)\nlea 0x1(%rsi),%eax\nmov %eax,0x1c(%rsp)\ncallq 1400 \nmov 0x1c(%rsp),%esi\nadd $0x2,%r15\ncmp $0x1,%esi\njg 1610 \nmovslq 0x4(%rsp),%rax\nlea (%r12,%rax,1),%rbx\ncmp $0x1,%esi\nje 1709 \nmovb $0x0,(%rbx)\nmov 0xc28(%rsp),%rax\nxor %fs:0x28,%rax\njne 174b \nadd $0xc38,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmov $0x1,%edi\ncallq 10d0 \nmov %rax,%r12\ntest %rax,%rax\nje 16c2 \nmovb $0x0,(%rax)\njmp 16c2 \nadd $0x1,%ebx\njmpq 15db \nlea 0x1c(%rsp),%rsi\nlea 0x420(%rsp),%rdi\ncallq 1490 \nshl $0x18,%rax\nsar $0x38,%rax\nmov %al,(%rbx)\nmov 0x4(%rsp),%eax\nadd $0x1,%eax\ncltq\nlea (%r12,%rax,1),%rbx\njmp 16bf \nxor %edx,%edx\njmpq 154d \nmovl $0x0,0x4(%rsp)\nmov %rax,%rbx\njmpq 16ba \ncallq 10b0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 0C28h\nmov rax, fs:28h\nmov [rsp+0C58h+var_40], rax\nxor eax, eax\ncall _strlen\ntest eax, eax\njz loc_1740\nlea r8, [rsp+0C58h+var_C48]\nmov rbp, rax\nmov ecx, 80h\nmov eax, 0\nmov rdi, r8\nrep stosq\njle short loc_1561\nlea eax, [rbp-1]\nmov rdi, rbx\nlea rdx, [rbx+rax+1]\nnop dword ptr [rax]\nloc_1550:\nmovzx eax, byte ptr [rdi]\nadd rdi, 1\nadd [rsp+rax*4+0C58h+var_C48], 1\ncmp rdx, rdi\njnz short loc_1550\nloc_1561:\nxor eax, eax\nxor r14d, r14d\nnop word ptr [rax+rax+00000000h]\nloc_1570:\nmov edx, [r8+rax*4]\ntest edx, edx\njle short loc_158D\nmovsxd rsi, r14d\nadd r14d, 1\nmov dword ptr [rsp+rsi*8+0C58h+var_848], edx\nmov byte ptr [rsp+rsi*8+0C58h+var_848+4], al\nloc_158D:\nadd rax, 1\ncmp rax, 100h\njnz short loc_1570\nmov r12d, r14d\nlea rbx, [rsp+0C58h+var_848]\nshr r12d, 1Fh\nadd r12d, r14d\nsar r12d, 1\nsub r12d, 1\njs short loc_15CC\nnop dword ptr [rax+00h]\nloc_15B8:\nmov edx, r12d\nmov esi, r14d\nmov rdi, rbx\ncall heapify_down\nsub r12d, 1\njnb short loc_15B8\nloc_15CC:\nlea eax, [rbp+1]\ntest r14d, r14d\njle loc_1758\nmov ebp, dword ptr [rsp+0C58h+var_848]\nlea edx, [rbp+rbp+0]\ncmp edx, eax\njg loc_1740\nmovsxd rdi, eax; size\ncall _malloc\nmov [rsp+0C58h+var_C58], rax\ncmp r14d, 1\njz loc_1769\nmov r12d, 2\nlea rbx, [rsp+0C58h+var_848]\njmp short loc_1622\nloc_1618:\nmov ebp, dword ptr [rsp+0C58h+var_848]\nmov r12, rax\nloc_1622:\nmovsxd rax, r14d\nlea r13d, [r14-1]\nmov rdi, rbx\nxor edx, edx\nmov rax, [rsp+rax*8+0C58h+var_850]\nmov esi, r13d\nsub r14d, 2\nmovzx r15d, byte ptr [rsp+0C58h+var_848+4]\nmov [rsp+0C58h+var_848], rax\ncall heapify_down\nmov eax, dword ptr [rsp+0C58h+var_848]\nmovsxd rdx, r13d\nmov esi, r14d\nmovzx ecx, byte ptr [rsp+0C58h+var_848+4]\nmov rdx, [rsp+rdx*8+0C58h+var_850]\nmov [rsp+0C58h+var_C50], eax\nmovzx eax, r15b\nmov ah, cl\nmov [rsp+0C58h+var_848], rdx\nxor edx, edx\nmov [rsp+0C58h+var_C49], cl\nmov [rsp+0C58h+var_C4C], ax\ncall heapify_down\nmovzx eax, [rsp+0C58h+var_C4C]\nmov rdi, [rsp+0C58h+var_C58]\nmov ecx, [rsp+0C58h+var_C50]\nmov [rdi+r12-2], ax\nlea eax, [rbp-1]\nlea ebp, [rcx-1]\ntest eax, eax\njle short loc_16CA\nmovsxd rdx, r14d\nmov esi, r14d\nmov rdi, rbx\nmov r14d, r13d\nlea rdx, [rbx+rdx*8]\nmov [rdx], eax\nmov [rdx+4], r15b\ncall heapify_up\nloc_16CA:\ntest ebp, ebp\njle short loc_16F1\nmovzx ecx, [rsp+0C58h+var_C49]\nmovsxd rax, r14d\nmov esi, r14d\nmov rdi, rbx\nlea rax, [rbx+rax*8]\nmov [rax], ebp\nlea ebp, [r14+1]\nmov [rax+4], cl\nmov r14d, ebp\ncall heapify_up\nloc_16F1:\nlea rax, [r12+2]\ncmp r14d, 1\njg loc_1618\nmov rax, [rsp+0C58h+var_C58]\nmovsxd rbp, r12d\nmov r13d, r12d\nadd rbp, rax\ncmp r14d, 1\njz short loc_1778\nloc_1713:\nmov byte ptr [rbp+0], 0\nloc_1717:\nmov rax, [rsp+0C58h+var_40]\nsub rax, fs:28h\njnz short loc_17A4\nmov rax, [rsp+0C58h+var_C58]\nadd rsp, 0C28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1740:\nmov edi, 1; size\ncall _malloc\nmov [rsp+0C58h+var_C58], rax\ntest rax, rax\njz short loc_1717\nmov byte ptr [rax], 0\njmp short loc_1717\nloc_1758:\nmovsxd rdi, eax; size\ncall _malloc\nmov [rsp+0C58h+var_C58], rax\nmov rbp, rax\njmp short loc_1713\nloc_1769:\nmov rbp, [rsp+0C58h+var_C58]\nxor r13d, r13d\nlea rbx, [rsp+0C58h+var_848]\nloc_1778:\nmovzx r12d, byte ptr [rsp+0C58h+var_848+4]\nmov rdi, rbx\nxor edx, edx\nxor esi, esi\ncall heapify_down\nmov rbx, [rsp+0C58h+var_C58]\nlea eax, [r13+1]\ncdqe\nmov [rbp+0], r12b\nlea rbp, [rbx+rax]\njmp loc_1713\nloc_17A4:\ncall ___stack_chk_fail", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1)\n{\n int v1; // eax\n int v2; // ebp\n __int64 v3; // rdx\n __int64 v4; // rax\n __int64 v5; // rax\n int v6; // r14d\n int v7; // edx\n __int64 v8; // rsi\n int v9; // r12d\n int v11; // eax\n int v12; // ebp\n __int64 i; // r12\n int v14; // r13d\n __int64 v15; // rax\n __int64 v16; // rsi\n char v17; // r15\n __int16 v18; // ax\n int v19; // eax\n int v20; // ebp\n __int64 v21; // rdx\n __int64 v22; // rsi\n _QWORD *v23; // rdx\n __int64 v24; // rsi\n _QWORD *v25; // rax\n int v26; // r13d\n _BYTE *v27; // rbp\n _BYTE *v29; // rax\n char v30; // r12\n _BYTE *v31; // [rsp+0h] [rbp-C58h]\n int v32; // [rsp+8h] [rbp-C50h]\n __int16 v33; // [rsp+Ch] [rbp-C4Ch]\n char v34; // [rsp+Fh] [rbp-C49h]\n _QWORD v35[128]; // [rsp+10h] [rbp-C48h] BYREF\n _QWORD v36[265]; // [rsp+410h] [rbp-848h] BYREF\n\n v36[257] = __readfsqword(0x28u);\n v1 = strlen(a1);\n if ( v1 )\n {\n v2 = v1;\n memset(v35, 0, sizeof(v35));\n if ( v1 > 0 )\n {\n v3 = (__int64)&a1[v1 - 1 + 1];\n do\n {\n v4 = *(unsigned __int8 *)a1++;\n ++*((_DWORD *)v35 + v4);\n }\n while ( (const char *)v3 != a1 );\n }\n v5 = 0LL;\n v6 = 0;\n do\n {\n v7 = *((_DWORD *)v35 + v5);\n if ( v7 > 0 )\n {\n v8 = v6++;\n LODWORD(v36[v8]) = v7;\n BYTE4(v36[v8]) = v5;\n }\n ++v5;\n }\n while ( v5 != 256 );\n v9 = v6 / 2 - 1;\n if ( v9 >= 0 )\n {\n do\n heapify_down(v36, (unsigned int)v6, (unsigned int)v9);\n while ( v9-- != 0 );\n }\n v11 = v2 + 1;\n if ( v6 <= 0 )\n {\n v31 = malloc(v11);\n v27 = v31;\n goto LABEL_22;\n }\n v12 = v36[0];\n if ( 2 * LODWORD(v36[0]) <= v11 )\n {\n v31 = malloc(v11);\n if ( v6 == 1 )\n {\n v27 = v31;\n v26 = 0;\n }\n else\n {\n for ( i = 2LL; ; i += 2LL )\n {\n v14 = v6 - 1;\n v15 = v35[v6 + 127];\n v16 = (unsigned int)(v6 - 1);\n v6 -= 2;\n v17 = BYTE4(v36[0]);\n v36[0] = v15;\n heapify_down(v36, v16, 0LL);\n v32 = v36[0];\n LOBYTE(v18) = v17;\n HIBYTE(v18) = BYTE4(v36[0]);\n v36[0] = v35[v14 + 127];\n v34 = HIBYTE(v18);\n v33 = v18;\n heapify_down(v36, (unsigned int)v6, 0LL);\n *(_WORD *)&v31[i - 2] = v33;\n v19 = v12 - 1;\n v20 = v32 - 1;\n if ( v19 > 0 )\n {\n v21 = v6;\n v22 = (unsigned int)v6;\n v6 = v14;\n v23 = &v36[v21];\n *(_DWORD *)v23 = v19;\n *((_BYTE *)v23 + 4) = v17;\n heapify_up(v36, v22);\n }\n if ( v20 > 0 )\n {\n v24 = (unsigned int)v6;\n v25 = &v36[v6];\n *(_DWORD *)v25 = v20;\n *((_BYTE *)v25 + 4) = v34;\n ++v6;\n heapify_up(v36, v24);\n }\n if ( v6 <= 1 )\n break;\n v12 = v36[0];\n }\n v26 = i;\n v27 = &v31[(int)i];\n if ( v6 != 1 )\n goto LABEL_22;\n }\n v30 = BYTE4(v36[0]);\n heapify_down(v36, 0LL, 0LL);\n *v27 = v30;\n v27 = &v31[v26 + 1];\nLABEL_22:\n *v27 = 0;\n return v31;\n }\n }\n v29 = malloc(1uLL);\n v31 = v29;\n if ( v29 )\n *v29 = 0;\n return v31;\n}", + "ida_strip_asm": "sub_14F0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 0C28h\nmov rax, fs:28h\nmov [rsp+0C58h+var_40], rax\nxor eax, eax\ncall _strlen\ntest eax, eax\njz loc_1740\nlea r8, [rsp+0C58h+var_C48]\nmov rbp, rax\nmov ecx, 80h\nmov eax, 0\nmov rdi, r8\nrep stosq\njle short loc_1561\nlea eax, [rbp-1]\nmov rdi, rbx\nlea rdx, [rbx+rax+1]\nnop dword ptr [rax]\nloc_1550:\nmovzx eax, byte ptr [rdi]\nadd rdi, 1\nadd [rsp+rax*4+0C58h+var_C48], 1\ncmp rdx, rdi\njnz short loc_1550\nloc_1561:\nxor eax, eax\nxor r14d, r14d\nnop word ptr [rax+rax+00000000h]\nloc_1570:\nmov edx, [r8+rax*4]\ntest edx, edx\njle short loc_158D\nmovsxd rsi, r14d\nadd r14d, 1\nmov dword ptr [rsp+rsi*8+0C58h+var_848], edx\nmov byte ptr [rsp+rsi*8+0C58h+var_848+4], al\nloc_158D:\nadd rax, 1\ncmp rax, 100h\njnz short loc_1570\nmov r12d, r14d\nlea rbx, [rsp+0C58h+var_848]\nshr r12d, 1Fh\nadd r12d, r14d\nsar r12d, 1\nsub r12d, 1\njs short loc_15CC\nnop dword ptr [rax+00h]\nloc_15B8:\nmov edx, r12d\nmov esi, r14d\nmov rdi, rbx\ncall sub_1330\nsub r12d, 1\njnb short loc_15B8\nloc_15CC:\nlea eax, [rbp+1]\ntest r14d, r14d\njle loc_1758\nmov ebp, dword ptr [rsp+0C58h+var_848]\nlea edx, [rbp+rbp+0]\ncmp edx, eax\njg loc_1740\nmovsxd rdi, eax; size\ncall _malloc\nmov [rsp+0C58h+var_C58], rax\ncmp r14d, 1\njz loc_1769\nmov r12d, 2\nlea rbx, [rsp+0C58h+var_848]\njmp short loc_1622\nloc_1618:\nmov ebp, dword ptr [rsp+0C58h+var_848]\nmov r12, rax\nloc_1622:\nmovsxd rax, r14d\nlea r13d, [r14-1]\nmov rdi, rbx\nxor edx, edx\nmov rax, [rsp+rax*8+0C58h+var_850]\nmov esi, r13d\nsub r14d, 2\nmovzx r15d, byte ptr [rsp+0C58h+var_848+4]\nmov [rsp+0C58h+var_848], rax\ncall sub_1330\nmov eax, dword ptr [rsp+0C58h+var_848]\nmovsxd rdx, r13d\nmov esi, r14d\nmovzx ecx, byte ptr [rsp+0C58h+var_848+4]\nmov rdx, [rsp+rdx*8+0C58h+var_850]\nmov [rsp+0C58h+var_C50], eax\nmovzx eax, r15b\nmov ah, cl\nmov [rsp+0C58h+var_848], rdx\nxor edx, edx\nmov [rsp+0C58h+var_C49], cl\nmov [rsp+0C58h+var_C4C], ax\ncall sub_1330\nmovzx eax, [rsp+0C58h+var_C4C]\nmov rdi, [rsp+0C58h+var_C58]\nmov ecx, [rsp+0C58h+var_C50]\nmov [rdi+r12-2], ax\nlea eax, [rbp-1]\nlea ebp, [rcx-1]\ntest eax, eax\njle short loc_16CA\nmovsxd rdx, r14d\nmov esi, r14d\nmov rdi, rbx\nmov r14d, r13d\nlea rdx, [rbx+rdx*8]\nmov [rdx], eax\nmov [rdx+4], r15b\ncall sub_1420\nloc_16CA:\ntest ebp, ebp\njle short loc_16F1\nmovzx ecx, [rsp+0C58h+var_C49]\nmovsxd rax, r14d\nmov esi, r14d\nmov rdi, rbx\nlea rax, [rbx+rax*8]\nmov [rax], ebp\nlea ebp, [r14+1]\nmov [rax+4], cl\nmov r14d, ebp\ncall sub_1420\nloc_16F1:\nlea rax, [r12+2]\ncmp r14d, 1\njg loc_1618\nmov rax, [rsp+0C58h+var_C58]\nmovsxd rbp, r12d\nmov r13d, r12d\nadd rbp, rax\ncmp r14d, 1\njz short loc_1778\nloc_1713:\nmov byte ptr [rbp+0], 0\nloc_1717:\nmov rax, [rsp+0C58h+var_40]\nsub rax, fs:28h\njnz short loc_17A4\nmov rax, [rsp+0C58h+var_C58]\nadd rsp, 0C28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1740:\nmov edi, 1; size\ncall _malloc\nmov [rsp+0C58h+var_C58], rax\ntest rax, rax\njz short loc_1717\nmov byte ptr [rax], 0\njmp short loc_1717\nloc_1758:\nmovsxd rdi, eax; size\ncall _malloc\nmov [rsp+0C58h+var_C58], rax\nmov rbp, rax\njmp short loc_1713\nloc_1769:\nmov rbp, [rsp+0C58h+var_C58]\nxor r13d, r13d\nlea rbx, [rsp+0C58h+var_848]\nloc_1778:\nmovzx r12d, byte ptr [rsp+0C58h+var_848+4]\nmov rdi, rbx\nxor edx, edx\nxor esi, esi\ncall sub_1330\nmov rbx, [rsp+0C58h+var_C58]\nlea eax, [r13+1]\ncdqe\nmov [rbp+0], r12b\nlea rbp, [rbx+rax]\njmp loc_1713\nloc_17A4:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_BYTE *__fastcall sub_14F0(const char *a1)\n{\n int v1; // eax\n int v2; // ebp\n __int64 v3; // rdx\n __int64 v4; // rax\n __int64 v5; // rax\n int v6; // r14d\n int v7; // edx\n __int64 v8; // rsi\n int v9; // r12d\n int v11; // eax\n int v12; // ebp\n __int64 i; // r12\n int v14; // r13d\n __int64 v15; // rax\n __int64 v16; // rsi\n char v17; // r15\n __int16 v18; // ax\n int v19; // eax\n int v20; // ebp\n __int64 v21; // rdx\n __int64 v22; // rsi\n _QWORD *v23; // rdx\n __int64 v24; // rsi\n _QWORD *v25; // rax\n int v26; // r13d\n _BYTE *v27; // rbp\n _BYTE *v29; // rax\n char v30; // r12\n _BYTE *v31; // [rsp+0h] [rbp-C58h]\n int v32; // [rsp+8h] [rbp-C50h]\n __int16 v33; // [rsp+Ch] [rbp-C4Ch]\n char v34; // [rsp+Fh] [rbp-C49h]\n _QWORD v35[128]; // [rsp+10h] [rbp-C48h] BYREF\n _QWORD v36[265]; // [rsp+410h] [rbp-848h] BYREF\n\n v36[257] = __readfsqword(0x28u);\n v1 = strlen(a1);\n if ( v1 )\n {\n v2 = v1;\n memset(v35, 0, sizeof(v35));\n if ( v1 > 0 )\n {\n v3 = (__int64)&a1[v1 - 1 + 1];\n do\n {\n v4 = *(unsigned __int8 *)a1++;\n ++*((_DWORD *)v35 + v4);\n }\n while ( (const char *)v3 != a1 );\n }\n v5 = 0LL;\n v6 = 0;\n do\n {\n v7 = *((_DWORD *)v35 + v5);\n if ( v7 > 0 )\n {\n v8 = v6++;\n LODWORD(v36[v8]) = v7;\n BYTE4(v36[v8]) = v5;\n }\n ++v5;\n }\n while ( v5 != 256 );\n v9 = v6 / 2 - 1;\n if ( v9 >= 0 )\n {\n do\n sub_1330(v36, (unsigned int)v6, (unsigned int)v9);\n while ( v9-- != 0 );\n }\n v11 = v2 + 1;\n if ( v6 <= 0 )\n {\n v31 = malloc(v11);\n v27 = v31;\n goto LABEL_22;\n }\n v12 = v36[0];\n if ( 2 * LODWORD(v36[0]) <= v11 )\n {\n v31 = malloc(v11);\n if ( v6 == 1 )\n {\n v27 = v31;\n v26 = 0;\n }\n else\n {\n for ( i = 2LL; ; i += 2LL )\n {\n v14 = v6 - 1;\n v15 = v35[v6 + 127];\n v16 = (unsigned int)(v6 - 1);\n v6 -= 2;\n v17 = BYTE4(v36[0]);\n v36[0] = v15;\n sub_1330(v36, v16, 0LL);\n v32 = v36[0];\n LOBYTE(v18) = v17;\n HIBYTE(v18) = BYTE4(v36[0]);\n v36[0] = v35[v14 + 127];\n v34 = HIBYTE(v18);\n v33 = v18;\n sub_1330(v36, (unsigned int)v6, 0LL);\n *(_WORD *)&v31[i - 2] = v33;\n v19 = v12 - 1;\n v20 = v32 - 1;\n if ( v19 > 0 )\n {\n v21 = v6;\n v22 = (unsigned int)v6;\n v6 = v14;\n v23 = &v36[v21];\n *(_DWORD *)v23 = v19;\n *((_BYTE *)v23 + 4) = v17;\n sub_1420(v36, v22);\n }\n if ( v20 > 0 )\n {\n v24 = (unsigned int)v6;\n v25 = &v36[v6];\n *(_DWORD *)v25 = v20;\n *((_BYTE *)v25 + 4) = v34;\n ++v6;\n sub_1420(v36, v24);\n }\n if ( v6 <= 1 )\n break;\n v12 = v36[0];\n }\n v26 = i;\n v27 = &v31[(int)i];\n if ( v6 != 1 )\n goto LABEL_22;\n }\n v30 = BYTE4(v36[0]);\n sub_1330(v36, 0LL, 0LL);\n *v27 = v30;\n v27 = &v31[v26 + 1];\nLABEL_22:\n *v27 = 0;\n return v31;\n }\n }\n v29 = malloc(1uLL);\n v31 = v29;\n if ( v29 )\n *v29 = 0;\n return v31;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_14F0(const char *a1) {\n int v1;\n int v2;\n long long v3;\n long long v4;\n long long v5;\n int v6;\n int v7;\n long long v8;\n int v9;\n int v11;\n int v12;\n long long i;\n int v14;\n long long v15;\n long long v16;\n char v17;\n short v18;\n int v19;\n int v20;\n long long v21;\n long long v22;\n uint64_t *v23;\n long long v24;\n uint64_t *v25;\n int v26;\n uint8_t *v27;\n uint8_t *v29;\n char v30;\n uint8_t *v31;\n int v32;\n short v33;\n char v34;\n uint64_t v35[128];\n uint64_t v36[265];\n v36[257] = __readfsqword(40u);\n v1 = strlen(a1);\n if (v1) {\n v2 = v1;\n memset(v35, 0, sizeof(v35));\n if (v1 > 0) {\n v3 = (long long)&a1[v1 - 1 + 1];\n do {\n v4 = *(unsigned char *)a1++;\n ++*((uint32_t *)v35 + v4);\n } while ((const char *)v3 != a1);\n }\n v5 = 0LL;\n v6 = 0;\n do {\n v7 = *((uint32_t *)v35 + v5);\n if (v7 > 0) {\n v8 = v6++;\n LODWORD(v36[v8]) = v7;\n BYTE4(v36[v8]) = v5;\n }\n ++v5;\n } while (v5 != 256);\n v9 = v6 / 2 - 1;\n if (v9 >= 0) {\n do\n sub_1330(v36, (unsigned int)v6, (unsigned int)v9);\n while (v9-- != 0);\n }\n v11 = v2 + 1;\n if (v6 <= 0) {\n v31 = malloc(v11);\n v27 = v31;\n goto LABEL_22;\n }\n v12 = v36[0];\n if (2 * LODWORD(v36[0]) <= v11) {\n v31 = malloc(v11);\n if (v6 == 1) {\n v27 = v31;\n v26 = 0;\n } else {\n for (i = 2LL;; i += 2LL) {\n v14 = v6 - 1;\n v15 = v35[v6 + 127];\n v16 = (unsigned int)(v6 - 1);\n v6 -= 2;\n v17 = BYTE4(v36[0]);\n v36[0] = v15;\n sub_1330(v36, v16, 0LL);\n v32 = v36[0];\n LOBYTE(v18) = v17;\n HIBYTE(v18) = BYTE4(v36[0]);\n v36[0] = v35[v14 + 127];\n v34 = HIBYTE(v18);\n v33 = v18;\n sub_1330(v36, (unsigned int)v6, 0LL);\n *(unsigned short *)&v31[i - 2] = v33;\n v19 = v12 - 1;\n v20 = v32 - 1;\n if (v19 > 0) {\n v21 = v6;\n v22 = (unsigned int)v6;\n v6 = v14;\n v23 = &v36[v21];\n *(uint32_t *)v23 = v19;\n *((uint8_t *)v23 + 4) = v17;\n sub_1420(v36, v22);\n }\n if (v20 > 0) {\n v24 = (unsigned int)v6;\n v25 = &v36[v6];\n *(uint32_t *)v25 = v20;\n *((uint8_t *)v25 + 4) = v34;\n ++v6;\n sub_1420(v36, v24);\n }\n if (v6 <= 1) break;\n v12 = v36[0];\n }\n v26 = i;\n v27 = &v31[(int)i];\n if (v6 != 1) goto LABEL_22;\n }\n v30 = BYTE4(v36[0]);\n sub_1330(v36, 0LL, 0LL);\n *v27 = v30;\n v27 = &v31[v26 + 1];\n LABEL_22:\n *v27 = 0;\n return v31;\n }\n }\n v29 = malloc(1uLL);\n v31 = v29;\n if (v29) *v29 = 0;\n return v31;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1) {\n int v1;\n int v2;\n long long v3;\n long long v4;\n long long v5;\n int v6;\n int v7;\n long long v8;\n int v9;\n int v11;\n int v12;\n long long i;\n int v14;\n long long v15;\n long long v16;\n char v17;\n short v18;\n int v19;\n int v20;\n long long v21;\n long long v22;\n uint64_t *v23;\n long long v24;\n uint64_t *v25;\n int v26;\n uint8_t *v27;\n uint8_t *v29;\n char v30;\n uint8_t *v31;\n int v32;\n short v33;\n char v34;\n uint64_t v35[128];\n uint64_t v36[265];\n v36[257] = __readfsqword(40u);\n v1 = strlen(a1);\n if (v1) {\n v2 = v1;\n memset(v35, 0, sizeof(v35));\n if (v1 > 0) {\n v3 = (long long)&a1[v1 - 1 + 1];\n do {\n v4 = *(unsigned char *)a1++;\n ++*((uint32_t *)v35 + v4);\n } while ((const char *)v3 != a1);\n }\n v5 = 0LL;\n v6 = 0;\n do {\n v7 = *((uint32_t *)v35 + v5);\n if (v7 > 0) {\n v8 = v6++;\n LODWORD(v36[v8]) = v7;\n BYTE4(v36[v8]) = v5;\n }\n ++v5;\n } while (v5 != 256);\n v9 = v6 / 2 - 1;\n if (v9 >= 0) {\n do\n heapify_down(v36, (unsigned int)v6, (unsigned int)v9);\n while (v9-- != 0);\n }\n v11 = v2 + 1;\n if (v6 <= 0) {\n v31 = malloc(v11);\n v27 = v31;\n goto LABEL_22;\n }\n v12 = v36[0];\n if (2 * LODWORD(v36[0]) <= v11) {\n v31 = malloc(v11);\n if (v6 == 1) {\n v27 = v31;\n v26 = 0;\n } else {\n for (i = 2LL;; i += 2LL) {\n v14 = v6 - 1;\n v15 = v35[v6 + 127];\n v16 = (unsigned int)(v6 - 1);\n v6 -= 2;\n v17 = BYTE4(v36[0]);\n v36[0] = v15;\n heapify_down(v36, v16, 0LL);\n v32 = v36[0];\n LOBYTE(v18) = v17;\n HIBYTE(v18) = BYTE4(v36[0]);\n v36[0] = v35[v14 + 127];\n v34 = HIBYTE(v18);\n v33 = v18;\n heapify_down(v36, (unsigned int)v6, 0LL);\n *(unsigned short *)&v31[i - 2] = v33;\n v19 = v12 - 1;\n v20 = v32 - 1;\n if (v19 > 0) {\n v21 = v6;\n v22 = (unsigned int)v6;\n v6 = v14;\n v23 = &v36[v21];\n *(uint32_t *)v23 = v19;\n *((uint8_t *)v23 + 4) = v17;\n heapify_up(v36, v22);\n }\n if (v20 > 0) {\n v24 = (unsigned int)v6;\n v25 = &v36[v6];\n *(uint32_t *)v25 = v20;\n *((uint8_t *)v25 + 4) = v34;\n ++v6;\n heapify_up(v36, v24);\n }\n if (v6 <= 1) break;\n v12 = v36[0];\n }\n v26 = i;\n v27 = &v31[(int)i];\n if (v6 != 1) goto LABEL_22;\n }\n v30 = BYTE4(v36[0]);\n heapify_down(v36, 0LL, 0LL);\n *v27 = v30;\n v27 = &v31[v26 + 1];\n LABEL_22:\n *v27 = 0;\n return v31;\n }\n }\n v29 = malloc(1uLL);\n v31 = v29;\n if (v29) *v29 = 0;\n return v31;\n}" + }, + { + "index": 39, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int freq;\n\n char ch;\n\n} HeapNode;\n\n\n\nvoid swap(HeapNode *a, HeapNode *b) {\n\n HeapNode temp = *a;\n\n *a = *b;\n\n *b = temp;\n\n}\n\n\n\nint compare(HeapNode a, HeapNode b) {\n\n // Higher frequency has higher priority.\n\n // If frequency equal, smaller char (lexicographically) has higher priority.\n\n if(a.freq != b.freq)\n\n return a.freq - b.freq; // positive if a.freq > b.freq.\n\n else\n\n return (b.ch - a.ch); // if a.ch < b.ch then priority: a\n\n}\n\n\n\nvoid heapify_down(HeapNode heap[], int n, int idx) {\n\n int largest = idx;\n\n int left = 2*idx + 1;\n\n int right = 2*idx + 2;\n\n if(left < n && (compare(heap[left], heap[largest]) > 0))\n\n largest = left;\n\n if(right < n && (compare(heap[right], heap[largest]) > 0))\n\n largest = right;\n\n if(largest != idx) {\n\n swap(&heap[idx], &heap[largest]);\n\n heapify_down(heap, n, largest);\n\n }\n\n}\n\n\n\nvoid heapify_up(HeapNode heap[], int idx) {\n\n while(idx > 0) {\n\n int parent = (idx - 1)/2;\n\n if(compare(heap[idx], heap[parent]) > 0) {\n\n swap(&heap[idx], &heap[parent]);\n\n idx = parent;\n\n } else {\n\n break;\n\n }\n\n }\n\n}\n\n\n\nvoid heap_push(HeapNode heap[], int *n, HeapNode node) {\n\n heap[*n] = node;\n\n (*n)++;\n\n heapify_up(heap, (*n)-1);\n\n}\n\n\n\nHeapNode heap_pop(HeapNode heap[], int *n) {\n\n HeapNode top = heap[0];\n\n heap[0] = heap[(*n)-1];\n\n (*n)--;\n\n heapify_down(heap, *n, 0);\n\n return top;\n\n}\n\n\n\n", + "func": "char *func0(const char *S) {\n int len = strlen(S);\n if (len == 0) {\n char *empty = malloc(1);\n if (empty) empty[0] = '\\0';\n return empty;\n }\n int freq[256] = {0};\n for (int i = 0; i < len; i++) {\n freq[(unsigned char)S[i]]++;\n }\n HeapNode heap[256];\n int heapSize = 0;\n for (int i = 0; i < 256; i++) {\n if (freq[i] > 0) {\n HeapNode node;\n node.freq = freq[i];\n node.ch = (char)i;\n heap[heapSize++] = node;\n }\n }\n for (int i = (heapSize / 2) - 1; i >= 0; i--) {\n heapify_down(heap, heapSize, i);\n }\n if (heapSize > 0 && heap[0].freq * 2 > len + 1) {\n char *empty = malloc(1);\n if (empty) empty[0] = '\\0';\n return empty;\n }\n char *result = malloc(len + 1);\n int pos = 0;\n while (heapSize >= 2) {\n HeapNode first = heap_pop(heap, &heapSize);\n HeapNode second = heap_pop(heap, &heapSize);\n result[pos++] = first.ch;\n result[pos++] = second.ch;\n first.freq--;\n second.freq--;\n if (first.freq > 0) {\n heap_push(heap, &heapSize, first);\n }\n if (second.freq > 0) {\n heap_push(heap, &heapSize, second);\n }\n }\n if (heapSize > 0) {\n HeapNode last = heap_pop(heap, &heapSize);\n result[pos++] = last.ch;\n }\n result[pos] = '\\0';\n return result;\n}", + "test": "int main() {\n\n char *res1 = func0(\"aab\");\n\n // The expected output is \"aba\"\n\n assert(strcmp(res1, \"aba\") == 0);\n\n free(res1);\n\n \n\n char *res2 = func0(\"aabb\");\n\n // The expected output is \"abab\"\n\n assert(strcmp(res2, \"abab\") == 0);\n\n free(res2);\n\n \n\n char *res3 = func0(\"abccdd\");\n\n // The expected output is \"cdabcd\"\n\n assert(strcmp(res3, \"cdabcd\") == 0);\n\n free(res3);\n\n \n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nsub $0xc38,%rsp\nmov %fs:0x28,%rax\nmov %rax,0xc28(%rsp)\nxor %eax,%eax\ncallq 10a0 \ntest %eax,%eax\nje 1829 \nlea 0x20(%rsp),%rsi\nmov %rax,%rbp\nmov $0x80,%ecx\nmov $0x0,%eax\nmov %rsi,%rdi\nrep stos %rax,%es:(%rdi)\njle 15a1 \nlea -0x1(%rbp),%eax\nmov %rbx,%rdi\nlea 0x1(%rbx,%rax,1),%rdx\nnopl (%rax)\nmovzbl (%rdi),%eax\nadd $0x1,%rdi\naddl $0x1,0x20(%rsp,%rax,4)\ncmp %rdi,%rdx\njne 1590 \nxor %eax,%eax\nxor %ebx,%ebx\nlea 0x420(%rsp),%rdi\nnopl (%rax)\nmov (%rsi,%rax,4),%edx\ntest %edx,%edx\njle 15c6 \nmovslq %ebx,%rcx\nadd $0x1,%ebx\nlea (%rdi,%rcx,8),%rcx\nmov %edx,(%rcx)\nmov %al,0x4(%rcx)\nadd $0x1,%rax\ncmp $0x100,%rax\njne 15b0 \nmov %ebx,%eax\nlea 0x420(%rsp),%rdi\nsar %eax\nlea -0x1(%rax),%r12d\nje 15fc \nnopl 0x0(%rax)\nmov %r12d,%edx\nmov %ebx,%esi\nsub $0x1,%r12d\ncallq 1320 \ncmp $0xffffffff,%r12d\njne 15e8 \nlea 0x1(%rbp),%eax\ntest %ebx,%ebx\nje 189f \nmov 0x420(%rsp),%ebp\nlea 0x0(%rbp,%rbp,1),%edx\ncmp %eax,%edx\njg 1829 \nmovslq %eax,%rdi\ncallq 10d0 \nmov %rax,0x10(%rsp)\ncmp $0x1,%ebx\nje 1849 \nmov $0x2,%r15d\nlea 0x420(%rsp),%rdi\njmp 165f \nmov %esi,%ebx\ntest %r12d,%r12d\njg 17a0 \ncmp $0x1,%ebx\njle 1753 \nmov 0x420(%rsp),%ebp\nadd $0x2,%r15\nmovzbl 0x424(%rsp),%r13d\nmovslq %ebx,%rax\nxor %edx,%edx\nmov 0x418(%rsp,%rax,8),%rax\nmov %rax,0x420(%rsp)\nlea -0x1(%rbx),%eax\nmov %eax,%esi\nmov %eax,0xc(%rsp)\ncallq 1320 \nxor %edx,%edx\nmov 0x420(%rsp),%r12d\nmovzbl 0x424(%rsp),%r14d\nmovslq %esi,%rax\nlea -0x2(%rbx),%esi\nshl $0x3,%rax\nsub $0x1,%r12d\nmov %rax,0x18(%rsp)\nmov 0x418(%rsp,%rax,1),%rax\nmov %rax,0x420(%rsp)\ncallq 1320 \nmov 0x10(%rsp),%rax\nlea -0x1(%rbp),%ecx\nmov %r15d,%r8d\nmov %r13b,-0x2(%rax,%r15,1)\nmov %r14b,-0x1(%rax,%r15,1)\ntest %ecx,%ecx\njle 1640 \nmovslq %esi,%rax\nlea (%rdi,%rax,8),%rax\nmov %ecx,(%rax)\nmov %r13b,0x4(%rax)\ntest %esi,%esi\nje 1807 \nmovsbl %r13b,%ebp\njmp 1710 \nxchg %ax,%ax\nmov (%rdx),%rax\nmov %rax,(%r10)\nmov %ecx,(%rdx)\nmov %r13b,0x4(%rdx)\ntest %esi,%esi\nje 173d \nmovslq %esi,%rax\nmov %ecx,%r11d\nlea -0x1(%rax),%esi\nlea (%rdi,%rax,8),%r10\nsar %esi\nmovslq %esi,%rdx\nlea (%rdi,%rdx,8),%rdx\nmov (%rdx),%r9d\nmovsbl 0x4(%rdx),%eax\nsub %r9d,%r11d\nsub %ebp,%eax\ncmp %ecx,%r9d\ncmovne %r11d,%eax\ntest %eax,%eax\njg 1700 \ntest %r12d,%r12d\njg 1810 \nmov 0xc(%rsp),%ebx\ncmp $0x1,%ebx\njg 1654 \nmovslq %r8d,%rbp\nadd 0x10(%rsp),%rbp\ncmp $0x1,%ebx\nje 1859 \nmovb $0x0,0x0(%rbp)\nmov 0xc28(%rsp),%rax\nxor %fs:0x28,%rax\njne 18b4 \nmov 0x10(%rsp),%rax\nadd $0xc38,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw %cs:0x0(%rax,%rax,1)\nmovslq %esi,%rax\nlea (%rdi,%rax,8),%rax\nmov %r12d,(%rax)\nmov %r14b,0x4(%rax)\ntest %esi,%esi\nje 1888 \nmovsbl %r14b,%r9d\njmp 17d1 \nnopl 0x0(%rax)\nmov (%rdx),%rax\nmov %rax,(%r10)\nmov %r12d,(%rdx)\nmov %r14b,0x4(%rdx)\ntest %esi,%esi\nje 17fe \nmovslq %esi,%rax\nmov %r12d,%r8d\nlea -0x1(%rax),%esi\nlea (%rdi,%rax,8),%r10\nsar %esi\nmovslq %esi,%rdx\nlea (%rdi,%rdx,8),%rdx\nmov (%rdx),%ecx\nmovsbl 0x4(%rdx),%eax\nsub %ecx,%r8d\nsub %r9d,%eax\ncmp %ecx,%r12d\ncmovne %r8d,%eax\ntest %eax,%eax\njg 17c0 \nmov 0xc(%rsp),%ebx\njmpq 1654 \ntest %r12d,%r12d\njle 1888 \nnopl 0x0(%rax)\nmov 0x18(%rsp),%rax\nmov 0xc(%rsp),%esi\nmov %ebx,0xc(%rsp)\nadd %rdi,%rax\nmov %r12d,(%rax)\nmov %r14b,0x4(%rax)\njmp 17b6 \nmov $0x1,%edi\ncallq 10d0 \nmov %rax,0x10(%rsp)\ntest %rax,%rax\nje 1768 \nmovb $0x0,(%rax)\njmpq 1768 \nmov 0x10(%rsp),%rbp\nxor %r8d,%r8d\nlea 0x420(%rsp),%rdi\nxor %edx,%edx\nxor %esi,%esi\nmov %r8d,0xc(%rsp)\nmovzbl 0x424(%rsp),%ebx\ncallq 1320 \nmov 0xc(%rsp),%r8d\nmov %bl,0x0(%rbp)\nlea 0x1(%r8),%ebp\nmovslq %ebp,%rbp\nadd 0x10(%rsp),%rbp\njmpq 1764 \nmov 0xc(%rsp),%ebx\nmovslq %r8d,%rbp\nadd 0x10(%rsp),%rbp\ncmp $0x1,%ebx\njne 1764 \njmp 1859 \nmovslq %eax,%rdi\ncallq 10d0 \nmov %rax,0x10(%rsp)\nmov %rax,%rbp\njmpq 1764 \ncallq 10b0 <__stack_chk_fail@plt>\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 0C38h\nmov rax, fs:28h\nmov [rsp+0C68h+var_40], rax\nxor eax, eax\ncall _strlen\ntest eax, eax\njz loc_1798\nlea rsi, [rsp+0C68h+var_C48]\nmov r12, rax\nmov ecx, 80h\nmov eax, 0\nmov rdi, rsi\nrep stosq\njle short loc_15C1\nlea eax, [r12-1]\nmov rdi, rbx\nlea rdx, [rbx+rax+1]\nnop\nloc_15B0:\nmovzx eax, byte ptr [rdi]\nadd rdi, 1\nadd [rsp+rax*4+0C68h+var_C48], 1\ncmp rdi, rdx\njnz short loc_15B0\nloc_15C1:\nxor eax, eax\nxor ebp, ebp\nnop dword ptr [rax]\nloc_15C8:\nmov edx, [rsi+rax*4]\ntest edx, edx\njle short loc_15E3\nmovsxd rcx, ebp\nadd ebp, 1\nmov dword ptr [rsp+rcx*8+0C68h+var_848], edx\nmov byte ptr [rsp+rcx*8+0C68h+var_848+4], al\nloc_15E3:\nadd rax, 1\ncmp rax, 100h\njnz short loc_15C8\nmov ebx, ebp\nlea rdi, [rsp+0C68h+var_848]\nshr ebx, 1Fh\nadd ebx, ebp\nsar ebx, 1\nsub ebx, 1\njs short loc_1616\nnop dword ptr [rax]\nloc_1608:\nmov edx, ebx\nmov esi, ebp\ncall heapify_down\nsub ebx, 1\njnb short loc_1608\nloc_1616:\nlea eax, [r12+1]\ntest ebp, ebp\njle loc_187F\nmov r12d, dword ptr [rsp+0C68h+var_848]\nlea edx, [r12+r12]\ncmp edx, eax\njg loc_1798\nmovsxd rdi, eax; size\ncall _malloc\nmov r10, rax\ncmp ebp, 1\njz loc_1901\nmov [rsp+0C68h+var_C50], rax\nmov r8d, 2\nlea rdi, [rsp+0C68h+var_848]\njmp short loc_167F\nloc_1660:\ntest ecx, ecx\njg loc_17E0\nadd r8, 2\ncmp ebx, 1\njle loc_184F\nloc_1675:\nmov r12d, dword ptr [rsp+0C68h+var_848]\nmov ebp, ebx\nloc_167F:\nmovsxd rax, ebp\nlea ebx, [rbp-1]\nxor edx, edx\nmov [rsp+0C68h+var_C68], r8\nmov rax, [rsp+rax*8+0C68h+var_850]\nmov esi, ebx\nmov [rsp+0C68h+var_C5C], ebx\nsub r12d, 1\nmovzx r15d, byte ptr [rsp+0C68h+var_848+4]\nmov [rsp+0C68h+var_848], rax\ncall heapify_down\nmovsxd r9, ebx\nlea ebx, [rbp-2]\nmovzx r14d, byte ptr [rsp+0C68h+var_848+4]\nmov rdx, [rsp+r9*8+0C68h+var_850]\nmovzx eax, r15b\nmov r13d, dword ptr [rsp+0C68h+var_848]\nmov esi, ebx\nmov ecx, r14d\nmov [rsp+0C68h+var_C58], r9\nmov ah, cl\nmov [rsp+0C68h+var_848], rdx\nxor edx, edx\nmov word ptr [rsp+0C68h+var_C60], ax\ncall heapify_down\nmov r8, [rsp+0C68h+var_C68]\nmov rsi, [rsp+0C68h+var_C50]\nlea ecx, [r13-1]\nmovzx eax, word ptr [rsp+0C68h+var_C60]\nmov r11d, r8d\nmov [rsi+r8-2], ax\ntest r12d, r12d\njle loc_1660\nmovsxd rax, ebx\nlea rax, [rdi+rax*8]\nmov [rax], r12d\nmov [rax+4], r15b\ntest ebx, ebx\njz loc_188F\nmov [rsp+0C68h+var_C60], r8d\nmov r9, [rsp+0C68h+var_C58]\nmovsx r13d, r15b\njmp short loc_1751\nloc_1740:\nmov rax, [rdx]\nmov [r11], rax\nmov [rdx], r12d\nmov [rdx+4], r15b\ntest ebx, ebx\njz short loc_177E\nloc_1751:\nmovsxd rax, ebx\nmov r10d, r12d\nlea ebx, [rax-1]\nlea r11, [rdi+rax*8]\nsar ebx, 1\nmovsxd rdx, ebx\nlea rdx, [rdi+rdx*8]\nmov esi, [rdx]\nmovsx eax, byte ptr [rdx+4]\nsub r10d, esi\nsub eax, r13d\ncmp r12d, esi\ncmovnz eax, r10d\ntest eax, eax\njg short loc_1740\nloc_177E:\nmov r11d, [rsp+0C68h+var_C60]\ntest ecx, ecx\njg loc_1868\nmov ebx, [rsp+0C68h+var_C5C]\nadd r8, 2\njmp loc_1675\nloc_1798:\nmov edi, 1; size\ncall _malloc\nmov r10, rax\ntest rax, rax\njz short loc_17AD\nmov byte ptr [rax], 0\nloc_17AD:\nmov rax, [rsp+0C68h+var_40]\nsub rax, fs:28h\njnz loc_1911\nadd rsp, 0C38h\nmov rax, r10\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_17E0:\nmovsxd rax, ebx\nlea rax, [rdi+rax*8]\nmov [rax], ecx\nmov [rax+4], r14b\ntest ebx, ebx\njz loc_18CE\nloc_17F5:\nmovsx esi, r14b\njmp short loc_1811\nloc_1800:\nmov rax, [rdx]\nmov [rbp+0], rax\nmov [rdx], ecx\nmov [rdx+4], r14b\ntest ebx, ebx\njz short loc_183E\nloc_1811:\nmovsxd rax, ebx\nmov r10d, ecx\nlea ebx, [rax-1]\nlea rbp, [rdi+rax*8]\nsar ebx, 1\nmovsxd rdx, ebx\nlea rdx, [rdi+rdx*8]\nmov r9d, [rdx]\nmovsx eax, byte ptr [rdx+4]\nsub r10d, r9d\nsub eax, esi\ncmp ecx, r9d\ncmovnz eax, r10d\ntest eax, eax\njg short loc_1800\nloc_183E:\nmov ebx, [rsp+0C68h+var_C5C]\nadd r8, 2\ncmp ebx, 1\njg loc_1675\nloc_184F:\nmov r10, [rsp+0C68h+var_C50]\nmovsxd rbp, r11d\nadd rbp, r10\nloc_185A:\ncmp ebx, 1\njz short loc_189C\nloc_185F:\nmov byte ptr [rbp+0], 0\njmp loc_17AD\nloc_1868:\nlea rax, [rdi+r9*8]\nmov ebx, [rsp+0C68h+var_C5C]\nmov [rsp+0C68h+var_C5C], ebp\nmov [rax], ecx\nmov [rax+4], r14b\njmp loc_17F5\nloc_187F:\nmovsxd rdi, eax; size\ncall _malloc\nmov rbp, rax\nmov r10, rax\njmp short loc_185F\nloc_188F:\ntest ecx, ecx\njg short loc_18E0\nmovsxd rbp, r8d\nmov r10, rsi\nadd rbp, rsi\nloc_189C:\nxor edx, edx\nxor esi, esi\nmov [rsp+0C68h+var_C68], r10\nmovzx ebx, byte ptr [rsp+0C68h+var_848+4]\nmov [rsp+0C68h+var_C60], r11d\ncall heapify_down\nmov r11d, [rsp+0C68h+var_C60]\nmov r10, [rsp+0C68h+var_C68]\nmov [rbp+0], bl\nlea ebp, [r11+1]\nmovsxd rbp, ebp\nadd rbp, r10\njmp short loc_185F\nloc_18CE:\nmovsxd rbp, r8d\nmov ebx, [rsp+0C68h+var_C5C]\nmov r10, rsi\nadd rbp, rsi\njmp loc_185A\nloc_18E0:\nmov [rsp+0C68h+var_840], ecx\nmov ebx, 1\nmov [rsp+0C68h+var_83C], r14b\nmov [rsp+0C68h+var_C5C], 2\njmp loc_17F5\nloc_1901:\nmov rbp, rax\nxor r11d, r11d\nlea rdi, [rsp+0C68h+var_848]\njmp short loc_189C\nloc_1911:\ncall ___stack_chk_fail", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1)\n{\n int v1; // eax\n int v2; // r12d\n __int64 v3; // rdx\n __int64 v4; // rax\n __int64 v5; // rax\n int v6; // ebp\n int v7; // edx\n __int64 v8; // rcx\n int v9; // ebx\n int v11; // eax\n int v12; // r12d\n _BYTE *v13; // rax\n _BYTE *v14; // r10\n __int64 v15; // r8\n int v16; // r12d\n char v17; // r15\n int v18; // ebx\n char v19; // r14\n __int16 v20; // ax\n int v21; // r13d\n int v22; // ecx\n int v23; // r11d\n __int64 *v24; // rax\n __int64 *v25; // r11\n __int64 *v26; // rdx\n int v27; // eax\n _BYTE *v28; // rax\n __int64 *v30; // rax\n __int64 *v31; // rbp\n __int64 *v32; // rdx\n int v33; // eax\n _BYTE *v34; // rbp\n __int64 *v35; // rax\n char v36; // bl\n __int64 v37; // [rsp+0h] [rbp-C68h]\n _BYTE *v38; // [rsp+0h] [rbp-C68h]\n __int16 v39; // [rsp+8h] [rbp-C60h]\n int v40; // [rsp+8h] [rbp-C60h]\n int v41; // [rsp+Ch] [rbp-C5Ch]\n __int64 v42; // [rsp+10h] [rbp-C58h]\n _BYTE *v43; // [rsp+18h] [rbp-C50h]\n _QWORD v44[128]; // [rsp+20h] [rbp-C48h] BYREF\n __int64 v45; // [rsp+420h] [rbp-848h] BYREF\n int v46; // [rsp+428h] [rbp-840h]\n char v47; // [rsp+42Ch] [rbp-83Ch]\n unsigned __int64 v48; // [rsp+C28h] [rbp-40h]\n\n v48 = __readfsqword(0x28u);\n v1 = strlen(a1);\n if ( !v1 )\n goto LABEL_27;\n v2 = v1;\n memset(v44, 0, sizeof(v44));\n if ( v1 > 0 )\n {\n v3 = (__int64)&a1[v1 - 1 + 1];\n do\n {\n v4 = *(unsigned __int8 *)a1++;\n ++*((_DWORD *)v44 + v4);\n }\n while ( a1 != (const char *)v3 );\n }\n v5 = 0LL;\n v6 = 0;\n do\n {\n v7 = *((_DWORD *)v44 + v5);\n if ( v7 > 0 )\n {\n v8 = v6++;\n *((_DWORD *)&v45 + 2 * v8) = v7;\n *((_BYTE *)&v45 + 8 * v8 + 4) = v5;\n }\n ++v5;\n }\n while ( v5 != 256 );\n v9 = v6 / 2 - 1;\n if ( v9 >= 0 )\n {\n do\n heapify_down(&v45, (unsigned int)v6, (unsigned int)v9);\n while ( v9-- != 0 );\n }\n v11 = v2 + 1;\n if ( v6 <= 0 )\n {\n v34 = malloc(v11);\n v14 = v34;\n goto LABEL_39;\n }\n v12 = v45;\n if ( 2 * (int)v45 > v11 )\n {\nLABEL_27:\n v28 = malloc(1uLL);\n v14 = v28;\n if ( v28 )\n *v28 = 0;\n return v14;\n }\n v13 = malloc(v11);\n v14 = v13;\n if ( v6 == 1 )\n {\n v34 = v13;\n v23 = 0;\nLABEL_44:\n v38 = v14;\n v36 = BYTE4(v45);\n v40 = v23;\n heapify_down(&v45, 0LL, 0LL);\n v14 = v38;\n *v34 = v36;\n v34 = &v38[v40 + 1];\n goto LABEL_39;\n }\n v43 = v13;\n v15 = 2LL;\n while ( 1 )\n {\n v37 = v15;\n v41 = v6 - 1;\n v16 = v12 - 1;\n v17 = BYTE4(v45);\n v45 = v44[v6 + 127];\n heapify_down(&v45, (unsigned int)(v6 - 1), 0LL);\n v18 = v6 - 2;\n v19 = BYTE4(v45);\n LOBYTE(v20) = v17;\n v21 = v45;\n v42 = v6 - 1;\n HIBYTE(v20) = BYTE4(v45);\n v45 = v44[v42 + 127];\n v39 = v20;\n heapify_down(&v45, (unsigned int)(v6 - 2), 0LL);\n v22 = v21 - 1;\n v23 = v37;\n *(_WORD *)&v43[v37 - 2] = v39;\n if ( v16 > 0 )\n {\n v24 = &v45 + v18;\n *(_DWORD *)v24 = v16;\n *((_BYTE *)v24 + 4) = v17;\n if ( v6 == 2 )\n {\n if ( v22 <= 0 )\n {\n v14 = v43;\n v34 = &v43[(int)v37];\n goto LABEL_44;\n }\n v46 = v21 - 1;\n v18 = 1;\n v47 = v19;\n v41 = 2;\n }\n else\n {\n do\n {\n v25 = &v45 + v18;\n v18 = (v18 - 1) >> 1;\n v26 = &v45 + v18;\n v27 = *((char *)v26 + 4) - v17;\n if ( v16 != *(_DWORD *)v26 )\n v27 = v16 - *(_DWORD *)v26;\n if ( v27 <= 0 )\n break;\n *v25 = *v26;\n *(_DWORD *)v26 = v16;\n *((_BYTE *)v26 + 4) = v17;\n }\n while ( v18 );\n v23 = v37;\n if ( v22 <= 0 )\n {\n v18 = v6 - 1;\n v15 = v37 + 2;\n goto LABEL_17;\n }\n v35 = &v45 + v42;\n v18 = v6 - 1;\n v41 = v6;\n *(_DWORD *)v35 = v22;\n *((_BYTE *)v35 + 4) = v19;\n }\n goto LABEL_33;\n }\n if ( v22 <= 0 )\n {\n v15 = v37 + 2;\n if ( v18 <= 1 )\n goto LABEL_37;\n goto LABEL_17;\n }\n v30 = &v45 + v18;\n *(_DWORD *)v30 = v22;\n *((_BYTE *)v30 + 4) = v19;\n if ( v6 == 2 )\n break;\n do\n {\nLABEL_33:\n v31 = &v45 + v18;\n v18 = (v18 - 1) >> 1;\n v32 = &v45 + v18;\n v33 = *((char *)v32 + 4) - v19;\n if ( v22 != *(_DWORD *)v32 )\n v33 = v22 - *(_DWORD *)v32;\n if ( v33 <= 0 )\n break;\n *v31 = *v32;\n *(_DWORD *)v32 = v22;\n *((_BYTE *)v32 + 4) = v19;\n }\n while ( v18 );\n v18 = v41;\n v15 = v37 + 2;\n if ( v41 <= 1 )\n {\nLABEL_37:\n v14 = v43;\n v34 = &v43[v23];\n goto LABEL_38;\n }\nLABEL_17:\n v12 = v45;\n v6 = v18;\n }\n v18 = v6 - 1;\n v14 = v43;\n v34 = &v43[(int)v37];\nLABEL_38:\n if ( v18 == 1 )\n goto LABEL_44;\nLABEL_39:\n *v34 = 0;\n return v14;\n}", + "ida_strip_asm": "sub_1550:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 0C38h\nmov rax, fs:28h\nmov [rsp+0C68h+var_40], rax\nxor eax, eax\ncall _strlen\ntest eax, eax\njz loc_1798\nlea rsi, [rsp+0C68h+var_C48]\nmov r12, rax\nmov ecx, 80h\nmov eax, 0\nmov rdi, rsi\nrep stosq\njle short loc_15C1\nlea eax, [r12-1]\nmov rdi, rbx\nlea rdx, [rbx+rax+1]\nnop\nloc_15B0:\nmovzx eax, byte ptr [rdi]\nadd rdi, 1\nadd [rsp+rax*4+0C68h+var_C48], 1\ncmp rdi, rdx\njnz short loc_15B0\nloc_15C1:\nxor eax, eax\nxor ebp, ebp\nnop dword ptr [rax]\nloc_15C8:\nmov edx, [rsi+rax*4]\ntest edx, edx\njle short loc_15E3\nmovsxd rcx, ebp\nadd ebp, 1\nmov dword ptr [rsp+rcx*8+0C68h+var_848], edx\nmov byte ptr [rsp+rcx*8+0C68h+var_848+4], al\nloc_15E3:\nadd rax, 1\ncmp rax, 100h\njnz short loc_15C8\nmov ebx, ebp\nlea rdi, [rsp+0C68h+var_848]\nshr ebx, 1Fh\nadd ebx, ebp\nsar ebx, 1\nsub ebx, 1\njs short loc_1616\nnop dword ptr [rax]\nloc_1608:\nmov edx, ebx\nmov esi, ebp\ncall sub_1330\nsub ebx, 1\njnb short loc_1608\nloc_1616:\nlea eax, [r12+1]\ntest ebp, ebp\njle loc_187F\nmov r12d, dword ptr [rsp+0C68h+var_848]\nlea edx, [r12+r12]\ncmp edx, eax\njg loc_1798\nmovsxd rdi, eax; size\ncall _malloc\nmov r10, rax\ncmp ebp, 1\njz loc_1901\nmov [rsp+0C68h+var_C50], rax\nmov r8d, 2\nlea rdi, [rsp+0C68h+var_848]\njmp short loc_167F\nloc_1660:\ntest ecx, ecx\njg loc_17E0\nadd r8, 2\ncmp ebx, 1\njle loc_184F\nloc_1675:\nmov r12d, dword ptr [rsp+0C68h+var_848]\nmov ebp, ebx\nloc_167F:\nmovsxd rax, ebp\nlea ebx, [rbp-1]\nxor edx, edx\nmov [rsp+0C68h+var_C68], r8\nmov rax, [rsp+rax*8+0C68h+var_850]\nmov esi, ebx\nmov [rsp+0C68h+var_C5C], ebx\nsub r12d, 1\nmovzx r15d, byte ptr [rsp+0C68h+var_848+4]\nmov [rsp+0C68h+var_848], rax\ncall sub_1330\nmovsxd r9, ebx\nlea ebx, [rbp-2]\nmovzx r14d, byte ptr [rsp+0C68h+var_848+4]\nmov rdx, [rsp+r9*8+0C68h+var_850]\nmovzx eax, r15b\nmov r13d, dword ptr [rsp+0C68h+var_848]\nmov esi, ebx\nmov ecx, r14d\nmov [rsp+0C68h+var_C58], r9\nmov ah, cl\nmov [rsp+0C68h+var_848], rdx\nxor edx, edx\nmov word ptr [rsp+0C68h+var_C60], ax\ncall sub_1330\nmov r8, [rsp+0C68h+var_C68]\nmov rsi, [rsp+0C68h+var_C50]\nlea ecx, [r13-1]\nmovzx eax, word ptr [rsp+0C68h+var_C60]\nmov r11d, r8d\nmov [rsi+r8-2], ax\ntest r12d, r12d\njle loc_1660\nmovsxd rax, ebx\nlea rax, [rdi+rax*8]\nmov [rax], r12d\nmov [rax+4], r15b\ntest ebx, ebx\njz loc_188F\nmov [rsp+0C68h+var_C60], r8d\nmov r9, [rsp+0C68h+var_C58]\nmovsx r13d, r15b\njmp short loc_1751\nloc_1740:\nmov rax, [rdx]\nmov [r11], rax\nmov [rdx], r12d\nmov [rdx+4], r15b\ntest ebx, ebx\njz short loc_177E\nloc_1751:\nmovsxd rax, ebx\nmov r10d, r12d\nlea ebx, [rax-1]\nlea r11, [rdi+rax*8]\nsar ebx, 1\nmovsxd rdx, ebx\nlea rdx, [rdi+rdx*8]\nmov esi, [rdx]\nmovsx eax, byte ptr [rdx+4]\nsub r10d, esi\nsub eax, r13d\ncmp r12d, esi\ncmovnz eax, r10d\ntest eax, eax\njg short loc_1740\nloc_177E:\nmov r11d, [rsp+0C68h+var_C60]\ntest ecx, ecx\njg loc_1868\nmov ebx, [rsp+0C68h+var_C5C]\nadd r8, 2\njmp loc_1675\nloc_1798:\nmov edi, 1; size\ncall _malloc\nmov r10, rax\ntest rax, rax\njz short loc_17AD\nmov byte ptr [rax], 0\nloc_17AD:\nmov rax, [rsp+0C68h+var_40]\nsub rax, fs:28h\njnz loc_1911\nadd rsp, 0C38h\nmov rax, r10\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_17E0:\nmovsxd rax, ebx\nlea rax, [rdi+rax*8]\nmov [rax], ecx\nmov [rax+4], r14b\ntest ebx, ebx\njz loc_18CE\nloc_17F5:\nmovsx esi, r14b\njmp short loc_1811\nloc_1800:\nmov rax, [rdx]\nmov [rbp+0], rax\nmov [rdx], ecx\nmov [rdx+4], r14b\ntest ebx, ebx\njz short loc_183E\nloc_1811:\nmovsxd rax, ebx\nmov r10d, ecx\nlea ebx, [rax-1]\nlea rbp, [rdi+rax*8]\nsar ebx, 1\nmovsxd rdx, ebx\nlea rdx, [rdi+rdx*8]\nmov r9d, [rdx]\nmovsx eax, byte ptr [rdx+4]\nsub r10d, r9d\nsub eax, esi\ncmp ecx, r9d\ncmovnz eax, r10d\ntest eax, eax\njg short loc_1800\nloc_183E:\nmov ebx, [rsp+0C68h+var_C5C]\nadd r8, 2\ncmp ebx, 1\njg loc_1675\nloc_184F:\nmov r10, [rsp+0C68h+var_C50]\nmovsxd rbp, r11d\nadd rbp, r10\nloc_185A:\ncmp ebx, 1\njz short loc_189C\nloc_185F:\nmov byte ptr [rbp+0], 0\njmp loc_17AD\nloc_1868:\nlea rax, [rdi+r9*8]\nmov ebx, [rsp+0C68h+var_C5C]\nmov [rsp+0C68h+var_C5C], ebp\nmov [rax], ecx\nmov [rax+4], r14b\njmp loc_17F5\nloc_187F:\nmovsxd rdi, eax; size\ncall _malloc\nmov rbp, rax\nmov r10, rax\njmp short loc_185F\nloc_188F:\ntest ecx, ecx\njg short loc_18E0\nmovsxd rbp, r8d\nmov r10, rsi\nadd rbp, rsi\nloc_189C:\nxor edx, edx\nxor esi, esi\nmov [rsp+0C68h+var_C68], r10\nmovzx ebx, byte ptr [rsp+0C68h+var_848+4]\nmov [rsp+0C68h+var_C60], r11d\ncall sub_1330\nmov r11d, [rsp+0C68h+var_C60]\nmov r10, [rsp+0C68h+var_C68]\nmov [rbp+0], bl\nlea ebp, [r11+1]\nmovsxd rbp, ebp\nadd rbp, r10\njmp short loc_185F\nloc_18CE:\nmovsxd rbp, r8d\nmov ebx, [rsp+0C68h+var_C5C]\nmov r10, rsi\nadd rbp, rsi\njmp loc_185A\nloc_18E0:\nmov [rsp+0C68h+var_840], ecx\nmov ebx, 1\nmov [rsp+0C68h+var_83C], r14b\nmov [rsp+0C68h+var_C5C], 2\njmp loc_17F5\nloc_1901:\nmov rbp, rax\nxor r11d, r11d\nlea rdi, [rsp+0C68h+var_848]\njmp short loc_189C\nloc_1911:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1550(const char *a1)\n{\n int v1; // eax\n int v2; // r12d\n __int64 v3; // rdx\n __int64 v4; // rax\n __int64 v5; // rax\n int v6; // ebp\n int v7; // edx\n __int64 v8; // rcx\n int v9; // ebx\n int v11; // eax\n int v12; // r12d\n _BYTE *v13; // rax\n _BYTE *v14; // r10\n __int64 v15; // r8\n int v16; // r12d\n char v17; // r15\n int v18; // ebx\n char v19; // r14\n __int16 v20; // ax\n int v21; // r13d\n int v22; // ecx\n int v23; // r11d\n __int64 *v24; // rax\n __int64 *v25; // r11\n __int64 *v26; // rdx\n int v27; // eax\n _BYTE *v28; // rax\n __int64 *v30; // rax\n __int64 *v31; // rbp\n __int64 *v32; // rdx\n int v33; // eax\n _BYTE *v34; // rbp\n __int64 *v35; // rax\n char v36; // bl\n __int64 v37; // [rsp+0h] [rbp-C68h]\n _BYTE *v38; // [rsp+0h] [rbp-C68h]\n __int16 v39; // [rsp+8h] [rbp-C60h]\n int v40; // [rsp+8h] [rbp-C60h]\n int v41; // [rsp+Ch] [rbp-C5Ch]\n __int64 v42; // [rsp+10h] [rbp-C58h]\n _BYTE *v43; // [rsp+18h] [rbp-C50h]\n _QWORD v44[128]; // [rsp+20h] [rbp-C48h] BYREF\n __int64 v45; // [rsp+420h] [rbp-848h] BYREF\n int v46; // [rsp+428h] [rbp-840h]\n char v47; // [rsp+42Ch] [rbp-83Ch]\n unsigned __int64 v48; // [rsp+C28h] [rbp-40h]\n\n v48 = __readfsqword(0x28u);\n v1 = strlen(a1);\n if ( !v1 )\n goto LABEL_27;\n v2 = v1;\n memset(v44, 0, sizeof(v44));\n if ( v1 > 0 )\n {\n v3 = (__int64)&a1[v1 - 1 + 1];\n do\n {\n v4 = *(unsigned __int8 *)a1++;\n ++*((_DWORD *)v44 + v4);\n }\n while ( a1 != (const char *)v3 );\n }\n v5 = 0LL;\n v6 = 0;\n do\n {\n v7 = *((_DWORD *)v44 + v5);\n if ( v7 > 0 )\n {\n v8 = v6++;\n *((_DWORD *)&v45 + 2 * v8) = v7;\n *((_BYTE *)&v45 + 8 * v8 + 4) = v5;\n }\n ++v5;\n }\n while ( v5 != 256 );\n v9 = v6 / 2 - 1;\n if ( v9 >= 0 )\n {\n do\n sub_1330(&v45, (unsigned int)v6, (unsigned int)v9);\n while ( v9-- != 0 );\n }\n v11 = v2 + 1;\n if ( v6 <= 0 )\n {\n v34 = malloc(v11);\n v14 = v34;\n goto LABEL_39;\n }\n v12 = v45;\n if ( 2 * (int)v45 > v11 )\n {\nLABEL_27:\n v28 = malloc(1uLL);\n v14 = v28;\n if ( v28 )\n *v28 = 0;\n return v14;\n }\n v13 = malloc(v11);\n v14 = v13;\n if ( v6 == 1 )\n {\n v34 = v13;\n v23 = 0;\nLABEL_44:\n v38 = v14;\n v36 = BYTE4(v45);\n v40 = v23;\n sub_1330(&v45, 0LL, 0LL);\n v14 = v38;\n *v34 = v36;\n v34 = &v38[v40 + 1];\n goto LABEL_39;\n }\n v43 = v13;\n v15 = 2LL;\n while ( 1 )\n {\n v37 = v15;\n v41 = v6 - 1;\n v16 = v12 - 1;\n v17 = BYTE4(v45);\n v45 = v44[v6 + 127];\n sub_1330(&v45, (unsigned int)(v6 - 1), 0LL);\n v18 = v6 - 2;\n v19 = BYTE4(v45);\n LOBYTE(v20) = v17;\n v21 = v45;\n v42 = v6 - 1;\n HIBYTE(v20) = BYTE4(v45);\n v45 = v44[v42 + 127];\n v39 = v20;\n sub_1330(&v45, (unsigned int)(v6 - 2), 0LL);\n v22 = v21 - 1;\n v23 = v37;\n *(_WORD *)&v43[v37 - 2] = v39;\n if ( v16 > 0 )\n {\n v24 = &v45 + v18;\n *(_DWORD *)v24 = v16;\n *((_BYTE *)v24 + 4) = v17;\n if ( v6 == 2 )\n {\n if ( v22 <= 0 )\n {\n v14 = v43;\n v34 = &v43[(int)v37];\n goto LABEL_44;\n }\n v46 = v21 - 1;\n v18 = 1;\n v47 = v19;\n v41 = 2;\n }\n else\n {\n do\n {\n v25 = &v45 + v18;\n v18 = (v18 - 1) >> 1;\n v26 = &v45 + v18;\n v27 = *((char *)v26 + 4) - v17;\n if ( v16 != *(_DWORD *)v26 )\n v27 = v16 - *(_DWORD *)v26;\n if ( v27 <= 0 )\n break;\n *v25 = *v26;\n *(_DWORD *)v26 = v16;\n *((_BYTE *)v26 + 4) = v17;\n }\n while ( v18 );\n v23 = v37;\n if ( v22 <= 0 )\n {\n v18 = v6 - 1;\n v15 = v37 + 2;\n goto LABEL_17;\n }\n v35 = &v45 + v42;\n v18 = v6 - 1;\n v41 = v6;\n *(_DWORD *)v35 = v22;\n *((_BYTE *)v35 + 4) = v19;\n }\n goto LABEL_33;\n }\n if ( v22 <= 0 )\n {\n v15 = v37 + 2;\n if ( v18 <= 1 )\n goto LABEL_37;\n goto LABEL_17;\n }\n v30 = &v45 + v18;\n *(_DWORD *)v30 = v22;\n *((_BYTE *)v30 + 4) = v19;\n if ( v6 == 2 )\n break;\n do\n {\nLABEL_33:\n v31 = &v45 + v18;\n v18 = (v18 - 1) >> 1;\n v32 = &v45 + v18;\n v33 = *((char *)v32 + 4) - v19;\n if ( v22 != *(_DWORD *)v32 )\n v33 = v22 - *(_DWORD *)v32;\n if ( v33 <= 0 )\n break;\n *v31 = *v32;\n *(_DWORD *)v32 = v22;\n *((_BYTE *)v32 + 4) = v19;\n }\n while ( v18 );\n v18 = v41;\n v15 = v37 + 2;\n if ( v41 <= 1 )\n {\nLABEL_37:\n v14 = v43;\n v34 = &v43[v23];\n goto LABEL_38;\n }\nLABEL_17:\n v12 = v45;\n v6 = v18;\n }\n v18 = v6 - 1;\n v14 = v43;\n v34 = &v43[(int)v37];\nLABEL_38:\n if ( v18 == 1 )\n goto LABEL_44;\nLABEL_39:\n *v34 = 0;\n return v14;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1550(const char *a1) {\n int v1;\n int v2;\n long long v3;\n long long v4;\n long long v5;\n int v6;\n int v7;\n long long v8;\n int v9;\n int v11;\n int v12;\n uint8_t *v13;\n uint8_t *v14;\n long long v15;\n int v16;\n char v17;\n int v18;\n char v19;\n short v20;\n int v21;\n int v22;\n int v23;\n long long *v24;\n long long *v25;\n long long *v26;\n int v27;\n uint8_t *v28;\n long long *v30;\n long long *v31;\n long long *v32;\n int v33;\n uint8_t *v34;\n long long *v35;\n char v36;\n long long v37;\n uint8_t *v38;\n short v39;\n int v40;\n int v41;\n long long v42;\n uint8_t *v43;\n uint64_t v44[128];\n long long v45;\n int v46;\n char v47;\n unsigned long long v48;\n v48 = __readfsqword(40u);\n v1 = strlen(a1);\n if (!v1) goto LABEL_27;\n v2 = v1;\n memset(v44, 0, sizeof(v44));\n if (v1 > 0) {\n v3 = (long long)&a1[v1 - 1 + 1];\n do {\n v4 = *(unsigned char *)a1++;\n ++*((uint32_t *)v44 + v4);\n } while (a1 != (const char *)v3);\n }\n v5 = 0LL;\n v6 = 0;\n do {\n v7 = *((uint32_t *)v44 + v5);\n if (v7 > 0) {\n v8 = v6++;\n *((uint32_t *)&v45 + 2 * v8) = v7;\n *((uint8_t *)&v45 + 8 * v8 + 4) = v5;\n }\n ++v5;\n } while (v5 != 256);\n v9 = v6 / 2 - 1;\n if (v9 >= 0) {\n do\n sub_1330(&v45, (unsigned int)v6, (unsigned int)v9);\n while (v9-- != 0);\n }\n v11 = v2 + 1;\n if (v6 <= 0) {\n v34 = malloc(v11);\n v14 = v34;\n goto LABEL_39;\n }\n v12 = v45;\n if (2 * (int)v45 > v11) {\n LABEL_27:\n v28 = malloc(1uLL);\n v14 = v28;\n if (v28) *v28 = 0;\n return v14;\n }\n v13 = malloc(v11);\n v14 = v13;\n if (v6 == 1) {\n v34 = v13;\n v23 = 0;\n LABEL_44:\n v38 = v14;\n v36 = BYTE4(v45);\n v40 = v23;\n sub_1330(&v45, 0LL, 0LL);\n v14 = v38;\n *v34 = v36;\n v34 = &v38[v40 + 1];\n goto LABEL_39;\n }\n v43 = v13;\n v15 = 2LL;\n while (1) {\n v37 = v15;\n v41 = v6 - 1;\n v16 = v12 - 1;\n v17 = BYTE4(v45);\n v45 = v44[v6 + 127];\n sub_1330(&v45, (unsigned int)(v6 - 1), 0LL);\n v18 = v6 - 2;\n v19 = BYTE4(v45);\n LOBYTE(v20) = v17;\n v21 = v45;\n v42 = v6 - 1;\n HIBYTE(v20) = BYTE4(v45);\n v45 = v44[v42 + 127];\n v39 = v20;\n sub_1330(&v45, (unsigned int)(v6 - 2), 0LL);\n v22 = v21 - 1;\n v23 = v37;\n *(unsigned short *)&v43[v37 - 2] = v39;\n if (v16 > 0) {\n v24 = &v45 + v18;\n *(uint32_t *)v24 = v16;\n *((uint8_t *)v24 + 4) = v17;\n if (v6 == 2) {\n if (v22 <= 0) {\n v14 = v43;\n v34 = &v43[(int)v37];\n goto LABEL_44;\n }\n v46 = v21 - 1;\n v18 = 1;\n v47 = v19;\n v41 = 2;\n } else {\n do {\n v25 = &v45 + v18;\n v18 = (v18 - 1) >> 1;\n v26 = &v45 + v18;\n v27 = *((char *)v26 + 4) - v17;\n if (v16 != *(uint32_t *)v26) v27 = v16 - *(uint32_t *)v26;\n if (v27 <= 0) break;\n *v25 = *v26;\n *(uint32_t *)v26 = v16;\n *((uint8_t *)v26 + 4) = v17;\n } while (v18);\n v23 = v37;\n if (v22 <= 0) {\n v18 = v6 - 1;\n v15 = v37 + 2;\n goto LABEL_17;\n }\n v35 = &v45 + v42;\n v18 = v6 - 1;\n v41 = v6;\n *(uint32_t *)v35 = v22;\n *((uint8_t *)v35 + 4) = v19;\n }\n goto LABEL_33;\n }\n if (v22 <= 0) {\n v15 = v37 + 2;\n if (v18 <= 1) goto LABEL_37;\n goto LABEL_17;\n }\n v30 = &v45 + v18;\n *(uint32_t *)v30 = v22;\n *((uint8_t *)v30 + 4) = v19;\n if (v6 == 2) break;\n do {\n LABEL_33:\n v31 = &v45 + v18;\n v18 = (v18 - 1) >> 1;\n v32 = &v45 + v18;\n v33 = *((char *)v32 + 4) - v19;\n if (v22 != *(uint32_t *)v32) v33 = v22 - *(uint32_t *)v32;\n if (v33 <= 0) break;\n *v31 = *v32;\n *(uint32_t *)v32 = v22;\n *((uint8_t *)v32 + 4) = v19;\n } while (v18);\n v18 = v41;\n v15 = v37 + 2;\n if (v41 <= 1) {\n LABEL_37:\n v14 = v43;\n v34 = &v43[v23];\n goto LABEL_38;\n }\n LABEL_17:\n v12 = v45;\n v6 = v18;\n }\n v18 = v6 - 1;\n v14 = v43;\n v34 = &v43[(int)v37];\nLABEL_38:\n if (v18 == 1) goto LABEL_44;\nLABEL_39:\n *v34 = 0;\n return v14;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1) {\n int v1;\n int v2;\n long long v3;\n long long v4;\n long long v5;\n int v6;\n int v7;\n long long v8;\n int v9;\n int v11;\n int v12;\n uint8_t *v13;\n uint8_t *v14;\n long long v15;\n int v16;\n char v17;\n int v18;\n char v19;\n short v20;\n int v21;\n int v22;\n int v23;\n long long *v24;\n long long *v25;\n long long *v26;\n int v27;\n uint8_t *v28;\n long long *v30;\n long long *v31;\n long long *v32;\n int v33;\n uint8_t *v34;\n long long *v35;\n char v36;\n long long v37;\n uint8_t *v38;\n short v39;\n int v40;\n int v41;\n long long v42;\n uint8_t *v43;\n uint64_t v44[128];\n long long v45;\n int v46;\n char v47;\n unsigned long long v48;\n v48 = __readfsqword(40u);\n v1 = strlen(a1);\n if (!v1) goto LABEL_27;\n v2 = v1;\n memset(v44, 0, sizeof(v44));\n if (v1 > 0) {\n v3 = (long long)&a1[v1 - 1 + 1];\n do {\n v4 = *(unsigned char *)a1++;\n ++*((uint32_t *)v44 + v4);\n } while (a1 != (const char *)v3);\n }\n v5 = 0LL;\n v6 = 0;\n do {\n v7 = *((uint32_t *)v44 + v5);\n if (v7 > 0) {\n v8 = v6++;\n *((uint32_t *)&v45 + 2 * v8) = v7;\n *((uint8_t *)&v45 + 8 * v8 + 4) = v5;\n }\n ++v5;\n } while (v5 != 256);\n v9 = v6 / 2 - 1;\n if (v9 >= 0) {\n do\n heapify_down(&v45, (unsigned int)v6, (unsigned int)v9);\n while (v9-- != 0);\n }\n v11 = v2 + 1;\n if (v6 <= 0) {\n v34 = malloc(v11);\n v14 = v34;\n goto LABEL_39;\n }\n v12 = v45;\n if (2 * (int)v45 > v11) {\n LABEL_27:\n v28 = malloc(1uLL);\n v14 = v28;\n if (v28) *v28 = 0;\n return v14;\n }\n v13 = malloc(v11);\n v14 = v13;\n if (v6 == 1) {\n v34 = v13;\n v23 = 0;\n LABEL_44:\n v38 = v14;\n v36 = BYTE4(v45);\n v40 = v23;\n heapify_down(&v45, 0LL, 0LL);\n v14 = v38;\n *v34 = v36;\n v34 = &v38[v40 + 1];\n goto LABEL_39;\n }\n v43 = v13;\n v15 = 2LL;\n while (1) {\n v37 = v15;\n v41 = v6 - 1;\n v16 = v12 - 1;\n v17 = BYTE4(v45);\n v45 = v44[v6 + 127];\n heapify_down(&v45, (unsigned int)(v6 - 1), 0LL);\n v18 = v6 - 2;\n v19 = BYTE4(v45);\n LOBYTE(v20) = v17;\n v21 = v45;\n v42 = v6 - 1;\n HIBYTE(v20) = BYTE4(v45);\n v45 = v44[v42 + 127];\n v39 = v20;\n heapify_down(&v45, (unsigned int)(v6 - 2), 0LL);\n v22 = v21 - 1;\n v23 = v37;\n *(unsigned short *)&v43[v37 - 2] = v39;\n if (v16 > 0) {\n v24 = &v45 + v18;\n *(uint32_t *)v24 = v16;\n *((uint8_t *)v24 + 4) = v17;\n if (v6 == 2) {\n if (v22 <= 0) {\n v14 = v43;\n v34 = &v43[(int)v37];\n goto LABEL_44;\n }\n v46 = v21 - 1;\n v18 = 1;\n v47 = v19;\n v41 = 2;\n } else {\n do {\n v25 = &v45 + v18;\n v18 = (v18 - 1) >> 1;\n v26 = &v45 + v18;\n v27 = *((char *)v26 + 4) - v17;\n if (v16 != *(uint32_t *)v26) v27 = v16 - *(uint32_t *)v26;\n if (v27 <= 0) break;\n *v25 = *v26;\n *(uint32_t *)v26 = v16;\n *((uint8_t *)v26 + 4) = v17;\n } while (v18);\n v23 = v37;\n if (v22 <= 0) {\n v18 = v6 - 1;\n v15 = v37 + 2;\n goto LABEL_17;\n }\n v35 = &v45 + v42;\n v18 = v6 - 1;\n v41 = v6;\n *(uint32_t *)v35 = v22;\n *((uint8_t *)v35 + 4) = v19;\n }\n goto LABEL_33;\n }\n if (v22 <= 0) {\n v15 = v37 + 2;\n if (v18 <= 1) goto LABEL_37;\n goto LABEL_17;\n }\n v30 = &v45 + v18;\n *(uint32_t *)v30 = v22;\n *((uint8_t *)v30 + 4) = v19;\n if (v6 == 2) break;\n do {\n LABEL_33:\n v31 = &v45 + v18;\n v18 = (v18 - 1) >> 1;\n v32 = &v45 + v18;\n v33 = *((char *)v32 + 4) - v19;\n if (v22 != *(uint32_t *)v32) v33 = v22 - *(uint32_t *)v32;\n if (v33 <= 0) break;\n *v31 = *v32;\n *(uint32_t *)v32 = v22;\n *((uint8_t *)v32 + 4) = v19;\n } while (v18);\n v18 = v41;\n v15 = v37 + 2;\n if (v41 <= 1) {\n LABEL_37:\n v14 = v43;\n v34 = &v43[v23];\n goto LABEL_38;\n }\n LABEL_17:\n v12 = v45;\n v6 = v18;\n }\n v18 = v6 - 1;\n v14 = v43;\n v34 = &v43[(int)v37];\nLABEL_38:\n if (v18 == 1) goto LABEL_44;\nLABEL_39:\n *v34 = 0;\n return v14;\n}" + }, + { + "index": 40, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int num;\n\n int count;\n\n} freq_t;\n\n\n\nint compare_freq(const void *a, const void *b) {\n\n freq_t *fa = (freq_t *)a;\n\n freq_t *fb = (freq_t *)b;\n\n return fa->num - fb->num;\n\n}\n\n\n\n", + "func": "freq_t *func0(int nums[][4], int num_lists, int list_size, int *unique_count) {\n freq_t *freq = malloc(num_lists * list_size * sizeof(freq_t));\n int total = 0;\n for (int i = 0; i < num_lists; i++) {\n for (int j = 0; j < list_size; j++) {\n int found = 0;\n for (int k = 0; k < total; k++) {\n if (freq[k].num == nums[i][j]) {\n freq[k].count++;\n found = 1;\n break;\n }\n }\n if (!found) {\n freq[total].num = nums[i][j];\n freq[total].count = 1;\n total++;\n }\n }\n }\n qsort(freq, total, sizeof(freq_t), compare_freq);\n *unique_count = total;\n return freq;\n}", + "test": "int main() {\n\n int unique_count1, unique_count2, unique_count3;\n\n\n\n int test1[][4] = {{1, 2, 3, 2}, {4, 5, 6, 2}, {7, 1, 9, 5}};\n\n freq_t *result1 = func0(test1, 3, 4, &unique_count1);\n\n freq_t expected1[] = {{1,2}, {2,3}, {3,1}, {4,1}, {5,2}, {6,1}, {7,1}, {9,1}};\n\n assert(unique_count1 == 8);\n\n for(int i = 0; i < unique_count1; i++) {\n\n assert(result1[i].num == expected1[i].num);\n\n assert(result1[i].count == expected1[i].count);\n\n }\n\n free(result1);\n\n\n\n int test2[][4] = {{1,2,3,4}, {5,6,7,8}, {9,10,11,12}};\n\n freq_t *result2 = func0(test2, 3, 4, &unique_count2);\n\n freq_t expected2[] = {{1,1}, {2,1}, {3,1}, {4,1}, {5,1}, {6,1}, {7,1}, {8,1}, {9,1}, {10,1}, {11,1}, {12,1}};\n\n assert(unique_count2 == 12);\n\n for(int i = 0; i < unique_count2; i++) {\n\n assert(result2[i].num == expected2[i].num);\n\n assert(result2[i].count == expected2[i].count);\n\n }\n\n free(result2);\n\n\n\n int test3[][4] = {{15,20,30,40}, {80,90,100,110}, {30,30,80,90}};\n\n freq_t *result3 = func0(test3, 3, 4, &unique_count3);\n\n freq_t expected3[] = {{15,1}, {20,1}, {30,3}, {40,1}, {80,2}, {90,2}, {100,1}, {110,1}};\n\n assert(unique_count3 == 8);\n\n for(int i = 0; i < unique_count3; i++) {\n\n assert(result3[i].num == expected3[i].num);\n\n assert(result3[i].count == expected3[i].count);\n\n }\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x40,%rsp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmov %edx,-0x30(%rbp)\nmov %rcx,-0x38(%rbp)\nmov -0x2c(%rbp),%eax\nimul -0x30(%rbp),%eax\ncltq\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0x1c(%rbp)\nmovl $0x0,-0x18(%rbp)\njmpq 132f \nmovl $0x0,-0x14(%rbp)\njmpq 131f \nmovl $0x0,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 12bc \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x18(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rcx\nmov -0x28(%rbp),%rax\nadd %rax,%rcx\nmov -0x14(%rbp),%eax\ncltq\nmov (%rcx,%rax,4),%eax\ncmp %eax,%edx\njne 12b8 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov 0x4(%rax),%edx\nadd $0x1,%edx\nmov %edx,0x4(%rax)\nmovl $0x1,-0x10(%rbp)\njmp 12c4 \naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 125d \ncmpl $0x0,-0x10(%rbp)\njne 131b \nmov -0x18(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x28(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x1c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov -0x14(%rbp),%eax\ncltq\nmov (%rcx,%rax,4),%eax\nmov %eax,(%rdx)\nmov -0x1c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmovl $0x1,0x4(%rax)\naddl $0x1,-0x1c(%rbp)\naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\ncmp -0x30(%rbp),%eax\njl 124d \naddl $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 1241 \nmov -0x1c(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x8(%rbp),%rax\nlea -0x183(%rip),%rcx\nmov $0x8,%edx\nmov %rax,%rdi\ncallq 10a0 \nmov -0x38(%rbp),%rax\nmov -0x1c(%rbp),%edx\nmov %edx,(%rax)\nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_30], edx\nmov [rbp+var_38], rcx\nmov eax, [rbp+var_2C]\nimul eax, [rbp+var_30]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+base], rax\nmov [rbp+var_1C], 0\nmov [rbp+var_18], 0\njmp loc_132F\nloc_1241:\nmov [rbp+var_14], 0\njmp loc_131F\nloc_124D:\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp short loc_12BC\nloc_125D:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_18]\ncdqe\nshl rax, 4\nmov rcx, rax\nmov rax, [rbp+var_28]\nadd rcx, rax\nmov eax, [rbp+var_14]\ncdqe\nmov eax, [rcx+rax*4]\ncmp edx, eax\njnz short loc_12B8\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rax+4]\nadd edx, 1\nmov [rax+4], edx\nmov [rbp+var_10], 1\njmp short loc_12C4\nloc_12B8:\nadd [rbp+var_C], 1\nloc_12BC:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_125D\nloc_12C4:\ncmp [rbp+var_10], 0\njnz short loc_131B\nmov eax, [rbp+var_18]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rdx, rax\nmov eax, [rbp+var_14]\ncdqe\nmov eax, [rcx+rax*4]\nmov [rdx], eax\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rax, rdx\nmov dword ptr [rax+4], 1\nadd [rbp+var_1C], 1\nloc_131B:\nadd [rbp+var_14], 1\nloc_131F:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_30]\njl loc_124D\nadd [rbp+var_18], 1\nloc_132F:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_2C]\njl loc_1241\nmov eax, [rbp+var_1C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compare_freq\nmov rcx, rdx; compar\nmov edx, 8; size\nmov rdi, rax; base\ncall _qsort\nmov rax, [rbp+var_38]\nmov edx, [rbp+var_1C]\nmov [rax], edx\nmov rax, [rbp+base]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, int a3, _DWORD *a4)\n{\n int v7; // [rsp+24h] [rbp-1Ch]\n int i; // [rsp+28h] [rbp-18h]\n int j; // [rsp+2Ch] [rbp-14h]\n int v10; // [rsp+30h] [rbp-10h]\n int k; // [rsp+34h] [rbp-Ch]\n _DWORD *base; // [rsp+38h] [rbp-8h]\n\n base = malloc(8LL * a3 * a2);\n v7 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = 0; j < a3; ++j )\n {\n v10 = 0;\n for ( k = 0; k < v7; ++k )\n {\n if ( base[2 * k] == *(_DWORD *)(a1 + 16LL * i + 4LL * j) )\n {\n ++base[2 * k + 1];\n v10 = 1;\n break;\n }\n }\n if ( !v10 )\n {\n base[2 * v7] = *(_DWORD *)(16LL * i + a1 + 4LL * j);\n base[2 * v7++ + 1] = 1;\n }\n }\n }\n qsort(base, v7, 8uLL, compare_freq);\n *a4 = v7;\n return base;\n}", + "ida_strip_asm": "sub_11FB:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_30], edx\nmov [rbp+var_38], rcx\nmov eax, [rbp+var_2C]\nimul eax, [rbp+var_30]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+base], rax\nmov [rbp+var_1C], 0\nmov [rbp+var_18], 0\njmp loc_132F\nloc_1241:\nmov [rbp+var_14], 0\njmp loc_131F\nloc_124D:\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp short loc_12BC\nloc_125D:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_18]\ncdqe\nshl rax, 4\nmov rcx, rax\nmov rax, [rbp+var_28]\nadd rcx, rax\nmov eax, [rbp+var_14]\ncdqe\nmov eax, [rcx+rax*4]\ncmp edx, eax\njnz short loc_12B8\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rax+4]\nadd edx, 1\nmov [rax+4], edx\nmov [rbp+var_10], 1\njmp short loc_12C4\nloc_12B8:\nadd [rbp+var_C], 1\nloc_12BC:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_125D\nloc_12C4:\ncmp [rbp+var_10], 0\njnz short loc_131B\nmov eax, [rbp+var_18]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rdx, rax\nmov eax, [rbp+var_14]\ncdqe\nmov eax, [rcx+rax*4]\nmov [rdx], eax\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rax, rdx\nmov dword ptr [rax+4], 1\nadd [rbp+var_1C], 1\nloc_131B:\nadd [rbp+var_14], 1\nloc_131F:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_30]\njl loc_124D\nadd [rbp+var_18], 1\nloc_132F:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_2C]\njl loc_1241\nmov eax, [rbp+var_1C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 8; size\nmov rdi, rax; base\ncall _qsort\nmov rax, [rbp+var_38]\nmov edx, [rbp+var_1C]\nmov [rax], edx\nmov rax, [rbp+base]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11FB(__int64 a1, int a2, int a3, _DWORD *a4)\n{\n int v7; // [rsp+24h] [rbp-1Ch]\n int i; // [rsp+28h] [rbp-18h]\n int j; // [rsp+2Ch] [rbp-14h]\n int v10; // [rsp+30h] [rbp-10h]\n int k; // [rsp+34h] [rbp-Ch]\n _DWORD *base; // [rsp+38h] [rbp-8h]\n\n base = malloc(8LL * a3 * a2);\n v7 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = 0; j < a3; ++j )\n {\n v10 = 0;\n for ( k = 0; k < v7; ++k )\n {\n if ( base[2 * k] == *(_DWORD *)(a1 + 16LL * i + 4LL * j) )\n {\n ++base[2 * k + 1];\n v10 = 1;\n break;\n }\n }\n if ( !v10 )\n {\n base[2 * v7] = *(_DWORD *)(16LL * i + a1 + 4LL * j);\n base[2 * v7++ + 1] = 1;\n }\n }\n }\n qsort(base, v7, 8uLL, compar);\n *a4 = v7;\n return base;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11FB(long long a1, int a2, int a3, uint32_t *a4) {\n int v7;\n int i;\n int j;\n int v10;\n int k;\n uint32_t *base;\n base = malloc(8LL * a3 * a2);\n v7 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = 0; j < a3; ++j) {\n v10 = 0;\n for (k = 0; k < v7; ++k) {\n if (base[2 * k] == *(uint32_t *)(a1 + 16LL * i + 4LL * j)) {\n ++base[2 * k + 1];\n v10 = 1;\n break;\n }\n }\n if (!v10) {\n base[2 * v7] = *(uint32_t *)(16LL * i + a1 + 4LL * j);\n base[2 * v7++ + 1] = 1;\n }\n }\n }\n qsort(base, v7, 8uLL, compar);\n *a4 = v7;\n return base;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, int a3, uint32_t *a4) {\n int v7;\n int i;\n int j;\n int v10;\n int k;\n uint32_t *base;\n base = malloc(8LL * a3 * a2);\n v7 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = 0; j < a3; ++j) {\n v10 = 0;\n for (k = 0; k < v7; ++k) {\n if (base[2 * k] == *(uint32_t *)(a1 + 16LL * i + 4LL * j)) {\n ++base[2 * k + 1];\n v10 = 1;\n break;\n }\n }\n if (!v10) {\n base[2 * v7] = *(uint32_t *)(16LL * i + a1 + 4LL * j);\n base[2 * v7++ + 1] = 1;\n }\n }\n }\n qsort(base, v7, 8uLL, compare_freq);\n *a4 = v7;\n return base;\n}" + }, + { + "index": 40, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int num;\n\n int count;\n\n} freq_t;\n\n\n\nint compare_freq(const void *a, const void *b) {\n\n freq_t *fa = (freq_t *)a;\n\n freq_t *fb = (freq_t *)b;\n\n return fa->num - fb->num;\n\n}\n\n\n\n", + "func": "freq_t *func0(int nums[][4], int num_lists, int list_size, int *unique_count) {\n freq_t *freq = malloc(num_lists * list_size * sizeof(freq_t));\n int total = 0;\n for (int i = 0; i < num_lists; i++) {\n for (int j = 0; j < list_size; j++) {\n int found = 0;\n for (int k = 0; k < total; k++) {\n if (freq[k].num == nums[i][j]) {\n freq[k].count++;\n found = 1;\n break;\n }\n }\n if (!found) {\n freq[total].num = nums[i][j];\n freq[total].count = 1;\n total++;\n }\n }\n }\n qsort(freq, total, sizeof(freq_t), compare_freq);\n *unique_count = total;\n return freq;\n}", + "test": "int main() {\n\n int unique_count1, unique_count2, unique_count3;\n\n\n\n int test1[][4] = {{1, 2, 3, 2}, {4, 5, 6, 2}, {7, 1, 9, 5}};\n\n freq_t *result1 = func0(test1, 3, 4, &unique_count1);\n\n freq_t expected1[] = {{1,2}, {2,3}, {3,1}, {4,1}, {5,2}, {6,1}, {7,1}, {9,1}};\n\n assert(unique_count1 == 8);\n\n for(int i = 0; i < unique_count1; i++) {\n\n assert(result1[i].num == expected1[i].num);\n\n assert(result1[i].count == expected1[i].count);\n\n }\n\n free(result1);\n\n\n\n int test2[][4] = {{1,2,3,4}, {5,6,7,8}, {9,10,11,12}};\n\n freq_t *result2 = func0(test2, 3, 4, &unique_count2);\n\n freq_t expected2[] = {{1,1}, {2,1}, {3,1}, {4,1}, {5,1}, {6,1}, {7,1}, {8,1}, {9,1}, {10,1}, {11,1}, {12,1}};\n\n assert(unique_count2 == 12);\n\n for(int i = 0; i < unique_count2; i++) {\n\n assert(result2[i].num == expected2[i].num);\n\n assert(result2[i].count == expected2[i].count);\n\n }\n\n free(result2);\n\n\n\n int test3[][4] = {{15,20,30,40}, {80,90,100,110}, {30,30,80,90}};\n\n freq_t *result3 = func0(test3, 3, 4, &unique_count3);\n\n freq_t expected3[] = {{15,1}, {20,1}, {30,3}, {40,1}, {80,2}, {90,2}, {100,1}, {110,1}};\n\n assert(unique_count3 == 8);\n\n for(int i = 0; i < unique_count3; i++) {\n\n assert(result3[i].num == expected3[i].num);\n\n assert(result3[i].count == expected3[i].count);\n\n }\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%r14\nmov %esi,%ebx\nmov %edx,%r12d\nmov %rcx,%r13\nmov %esi,%edi\nimul %edx,%edi\nmovslq %edi,%rdi\nshl $0x3,%rdi\ncallq 10d0 \nmov %rax,%rbp\ntest %ebx,%ebx\njle 127b \nmov %r14,%r10\nlea -0x1(%rbx),%eax\nshl $0x4,%rax\nlea 0x10(%r14,%rax,1),%r11\nmov $0x0,%ebx\nlea 0x8(%rbp),%r9\njmp 126c \naddl $0x1,0x4(%rax)\njmp 1239 \nmovslq %ebx,%rax\nlea 0x0(%rbp,%rax,8),%rax\nmov (%r8,%rdi,4),%edx\nmov %edx,(%rax)\nmovl $0x1,0x4(%rax)\nadd $0x1,%ebx\nadd $0x1,%rdi\ncmp %edi,%r12d\njle 1263 \ntest %ebx,%ebx\njle 1221 \nmov (%r8,%rdi,4),%ecx\nmov %rbp,%rax\nlea -0x1(%rbx),%edx\nlea (%r9,%rdx,8),%rsi\ncmp %ecx,(%rax)\nje 121b \nadd $0x8,%rax\ncmp %rsi,%rax\njne 1254 \njmp 1221 \nadd $0x10,%r10\ncmp %r11,%r10\nje 1280 \ntest %r12d,%r12d\njle 1263 \nmov %r10,%r8\nmov $0x0,%edi\njmp 1242 \nmov $0x0,%ebx\nmovslq %ebx,%rsi\nlea -0xc1(%rip),%rcx\nmov $0x8,%edx\nmov %rbp,%rdi\ncallq 10a0 \nmov %ebx,0x0(%r13)\nmov %rbp,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r14, rdi\nmov ebx, esi\nmov r12d, edx\nmov r13, rcx\nmov edi, esi\nimul edi, edx\nmovsxd rdi, edi\nshl rdi, 3; size\ncall _malloc\nmov rbp, rax\ntest ebx, ebx\njle short loc_1278\nmov r9, r14\nmovsxd rbx, ebx\nshl rbx, 4\nlea r10, [r14+rbx]\nmov ebx, 0\nmovsxd r8, r12d\njmp short loc_1269\nloc_1219:\nadd dword ptr [rax+4], 1\njmp short loc_1236\nloc_121F:\nmovsxd rax, ebx\nlea rax, [rbp+rax*8+0]\nmov edx, [rdi+rsi*4]\nmov [rax], edx\nmov dword ptr [rax+4], 1\nadd ebx, 1\nloc_1236:\nadd rsi, 1\ncmp rsi, r8\njz short loc_1260\nloc_123F:\ntest ebx, ebx\njle short loc_121F\nmov edx, [rdi+rsi*4]\nmov rax, rbp\nmovsxd rcx, ebx\nlea rcx, [rbp+rcx*8+0]\nloc_1251:\ncmp [rax], edx\njz short loc_1219\nadd rax, 8\ncmp rax, rcx\njnz short loc_1251\njmp short loc_121F\nloc_1260:\nadd r9, 10h\ncmp r9, r10\njz short loc_127D\nloc_1269:\ntest r12d, r12d\njle short loc_1260\nmov rdi, r9\nmov esi, 0\njmp short loc_123F\nloc_1278:\nmov ebx, 0\nloc_127D:\nmovsxd rsi, ebx; nmemb\nlea rcx, compare_freq; compar\nmov edx, 8; size\nmov rdi, rbp; base\ncall _qsort\nmov [r13+0], ebx\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, int a3, int *a4)\n{\n _DWORD *v6; // rbp\n __int64 v7; // r9\n __int64 v8; // r10\n int v9; // ebx\n _DWORD *v10; // rax\n __int64 v11; // rsi\n _DWORD *v12; // rax\n\n v6 = malloc(8LL * a3 * a2);\n if ( a2 <= 0 )\n {\n v9 = 0;\n }\n else\n {\n v7 = a1;\n v8 = a1 + 16LL * a2;\n v9 = 0;\n do\n {\n if ( a3 > 0 )\n {\n v11 = 0LL;\n do\n {\n if ( v9 <= 0 )\n {\nLABEL_4:\n v10 = &v6[2 * v9];\n *v10 = *(_DWORD *)(v7 + 4 * v11);\n v10[1] = 1;\n ++v9;\n }\n else\n {\n v12 = v6;\n while ( *v12 != *(_DWORD *)(v7 + 4 * v11) )\n {\n v12 += 2;\n if ( v12 == &v6[2 * v9] )\n goto LABEL_4;\n }\n ++v12[1];\n }\n ++v11;\n }\n while ( v11 != a3 );\n }\n v7 += 16LL;\n }\n while ( v7 != v8 );\n }\n qsort(v6, v9, 8uLL, compare_freq);\n *a4 = v9;\n return v6;\n}", + "ida_strip_asm": "sub_11D2:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r14, rdi\nmov ebx, esi\nmov r12d, edx\nmov r13, rcx\nmov edi, esi\nimul edi, edx\nmovsxd rdi, edi\nshl rdi, 3; size\ncall _malloc\nmov rbp, rax\ntest ebx, ebx\njle short loc_1278\nmov r9, r14\nmovsxd rbx, ebx\nshl rbx, 4\nlea r10, [r14+rbx]\nmov ebx, 0\nmovsxd r8, r12d\njmp short loc_1269\nloc_1219:\nadd dword ptr [rax+4], 1\njmp short loc_1236\nloc_121F:\nmovsxd rax, ebx\nlea rax, [rbp+rax*8+0]\nmov edx, [rdi+rsi*4]\nmov [rax], edx\nmov dword ptr [rax+4], 1\nadd ebx, 1\nloc_1236:\nadd rsi, 1\ncmp rsi, r8\njz short loc_1260\nloc_123F:\ntest ebx, ebx\njle short loc_121F\nmov edx, [rdi+rsi*4]\nmov rax, rbp\nmovsxd rcx, ebx\nlea rcx, [rbp+rcx*8+0]\nloc_1251:\ncmp [rax], edx\njz short loc_1219\nadd rax, 8\ncmp rax, rcx\njnz short loc_1251\njmp short loc_121F\nloc_1260:\nadd r9, 10h\ncmp r9, r10\njz short loc_127D\nloc_1269:\ntest r12d, r12d\njle short loc_1260\nmov rdi, r9\nmov esi, 0\njmp short loc_123F\nloc_1278:\nmov ebx, 0\nloc_127D:\nmovsxd rsi, ebx; nmemb\nlea rcx, compar; compar\nmov edx, 8; size\nmov rdi, rbp; base\ncall _qsort\nmov [r13+0], ebx\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11D2(__int64 a1, int a2, int a3, int *a4)\n{\n _DWORD *v6; // rbp\n __int64 v7; // r9\n __int64 v8; // r10\n int v9; // ebx\n _DWORD *v10; // rax\n __int64 v11; // rsi\n _DWORD *v12; // rax\n\n v6 = malloc(8LL * a3 * a2);\n if ( a2 <= 0 )\n {\n v9 = 0;\n }\n else\n {\n v7 = a1;\n v8 = a1 + 16LL * a2;\n v9 = 0;\n do\n {\n if ( a3 > 0 )\n {\n v11 = 0LL;\n do\n {\n if ( v9 <= 0 )\n {\nLABEL_4:\n v10 = &v6[2 * v9];\n *v10 = *(_DWORD *)(v7 + 4 * v11);\n v10[1] = 1;\n ++v9;\n }\n else\n {\n v12 = v6;\n while ( *v12 != *(_DWORD *)(v7 + 4 * v11) )\n {\n v12 += 2;\n if ( v12 == &v6[2 * v9] )\n goto LABEL_4;\n }\n ++v12[1];\n }\n ++v11;\n }\n while ( v11 != a3 );\n }\n v7 += 16LL;\n }\n while ( v7 != v8 );\n }\n qsort(v6, v9, 8uLL, compar);\n *a4 = v9;\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11D2(long long a1, int a2, int a3, int *a4) {\n uint32_t *v6;\n long long v7;\n long long v8;\n int v9;\n uint32_t *v10;\n long long v11;\n uint32_t *v12;\n v6 = malloc(8LL * a3 * a2);\n if (a2 <= 0) {\n v9 = 0;\n } else {\n v7 = a1;\n v8 = a1 + 16LL * a2;\n v9 = 0;\n do {\n if (a3 > 0) {\n v11 = 0LL;\n do {\n if (v9 <= 0) {\n LABEL_4:\n v10 = &v6[2 * v9];\n *v10 = *(uint32_t *)(v7 + 4 * v11);\n v10[1] = 1;\n ++v9;\n } else {\n v12 = v6;\n while (*v12 != *(uint32_t *)(v7 + 4 * v11)) {\n v12 += 2;\n if (v12 == &v6[2 * v9]) goto LABEL_4;\n }\n ++v12[1];\n }\n ++v11;\n } while (v11 != a3);\n }\n v7 += 16LL;\n } while (v7 != v8);\n }\n qsort(v6, v9, 8uLL, compar);\n *a4 = v9;\n return v6;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, int a3, int *a4) {\n uint32_t *v6;\n long long v7;\n long long v8;\n int v9;\n uint32_t *v10;\n long long v11;\n uint32_t *v12;\n v6 = malloc(8LL * a3 * a2);\n if (a2 <= 0) {\n v9 = 0;\n } else {\n v7 = a1;\n v8 = a1 + 16LL * a2;\n v9 = 0;\n do {\n if (a3 > 0) {\n v11 = 0LL;\n do {\n if (v9 <= 0) {\n LABEL_4:\n v10 = &v6[2 * v9];\n *v10 = *(uint32_t *)(v7 + 4 * v11);\n v10[1] = 1;\n ++v9;\n } else {\n v12 = v6;\n while (*v12 != *(uint32_t *)(v7 + 4 * v11)) {\n v12 += 2;\n if (v12 == &v6[2 * v9]) goto LABEL_4;\n }\n ++v12[1];\n }\n ++v11;\n } while (v11 != a3);\n }\n v7 += 16LL;\n } while (v7 != v8);\n }\n qsort(v6, v9, 8uLL, compare_freq);\n *a4 = v9;\n return v6;\n}" + }, + { + "index": 40, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int num;\n\n int count;\n\n} freq_t;\n\n\n\nint compare_freq(const void *a, const void *b) {\n\n freq_t *fa = (freq_t *)a;\n\n freq_t *fb = (freq_t *)b;\n\n return fa->num - fb->num;\n\n}\n\n\n\n", + "func": "freq_t *func0(int nums[][4], int num_lists, int list_size, int *unique_count) {\n freq_t *freq = malloc(num_lists * list_size * sizeof(freq_t));\n int total = 0;\n for (int i = 0; i < num_lists; i++) {\n for (int j = 0; j < list_size; j++) {\n int found = 0;\n for (int k = 0; k < total; k++) {\n if (freq[k].num == nums[i][j]) {\n freq[k].count++;\n found = 1;\n break;\n }\n }\n if (!found) {\n freq[total].num = nums[i][j];\n freq[total].count = 1;\n total++;\n }\n }\n }\n qsort(freq, total, sizeof(freq_t), compare_freq);\n *unique_count = total;\n return freq;\n}", + "test": "int main() {\n\n int unique_count1, unique_count2, unique_count3;\n\n\n\n int test1[][4] = {{1, 2, 3, 2}, {4, 5, 6, 2}, {7, 1, 9, 5}};\n\n freq_t *result1 = func0(test1, 3, 4, &unique_count1);\n\n freq_t expected1[] = {{1,2}, {2,3}, {3,1}, {4,1}, {5,2}, {6,1}, {7,1}, {9,1}};\n\n assert(unique_count1 == 8);\n\n for(int i = 0; i < unique_count1; i++) {\n\n assert(result1[i].num == expected1[i].num);\n\n assert(result1[i].count == expected1[i].count);\n\n }\n\n free(result1);\n\n\n\n int test2[][4] = {{1,2,3,4}, {5,6,7,8}, {9,10,11,12}};\n\n freq_t *result2 = func0(test2, 3, 4, &unique_count2);\n\n freq_t expected2[] = {{1,1}, {2,1}, {3,1}, {4,1}, {5,1}, {6,1}, {7,1}, {8,1}, {9,1}, {10,1}, {11,1}, {12,1}};\n\n assert(unique_count2 == 12);\n\n for(int i = 0; i < unique_count2; i++) {\n\n assert(result2[i].num == expected2[i].num);\n\n assert(result2[i].count == expected2[i].count);\n\n }\n\n free(result2);\n\n\n\n int test3[][4] = {{15,20,30,40}, {80,90,100,110}, {30,30,80,90}};\n\n freq_t *result3 = func0(test3, 3, 4, &unique_count3);\n\n freq_t expected3[] = {{15,1}, {20,1}, {30,3}, {40,1}, {80,2}, {90,2}, {100,1}, {110,1}};\n\n assert(unique_count3 == 8);\n\n for(int i = 0; i < unique_count3; i++) {\n\n assert(result3[i].num == expected3[i].num);\n\n assert(result3[i].count == expected3[i].count);\n\n }\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\nmov %rdi,%r14\nmov %esi,%edi\nimul %edx,%edi\npush %r13\nmov %edx,%r13d\npush %r12\npush %rbp\nmov %rcx,%rbp\npush %rbx\nmovslq %edi,%rdi\nmov %esi,%ebx\nshl $0x3,%rdi\ncallq 10d0 \nmov %rax,%r12\ntest %ebx,%ebx\njle 17e5 \nlea -0x1(%r13),%r9d\nlea -0x1(%rbx),%eax\nxor %ebx,%ebx\nlea (%r9,%rax,4),%rax\nlea 0x4(%r14,%r9,4),%rdi\nnot %r9\nlea 0x14(%r14,%rax,4),%r10\nshl $0x2,%r9\nlea 0x8(%r12),%r8\nnopw %cs:0x0(%rax,%rax,1)\ntest %r13d,%r13d\njle 179a \nlea (%r9,%rdi,1),%rsi\nmov (%rsi),%edx\ntest %ebx,%ebx\nje 17d0 \nlea -0x1(%rbx),%ecx\nmov %r12,%rax\nlea (%r8,%rcx,8),%rcx\njmp 1789 \nnopl 0x0(%rax,%rax,1)\nadd $0x8,%rax\ncmp %rax,%rcx\nje 17d0 \ncmp %edx,(%rax)\njne 1780 \naddl $0x1,0x4(%rax)\nadd $0x4,%rsi\ncmp %rdi,%rsi\njne 1769 \nadd $0x10,%rdi\ncmp %r10,%rdi\njne 1760 \nmovslq %ebx,%rsi\nmov %r12,%rdi\nlea -0xc0(%rip),%rcx\nmov $0x8,%edx\ncallq 10a0 \nmov %ebx,0x0(%rbp)\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopl 0x0(%rax)\nmovslq %ebx,%rax\nadd $0x1,%ebx\nlea (%r12,%rax,8),%rax\nmov %edx,(%rax)\nmovl $0x1,0x4(%rax)\njmp 1791 \nxor %esi,%esi\nxor %ebx,%ebx\njmp 17a6 \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\nmov r14, rdi\npush r13\nmov r13d, edx\npush r12\nmovsxd r12, esi\nmov edi, r12d\npush rbp\nmov rbp, rcx\nimul edi, edx\npush rbx\nmovsxd rdi, edi\nshl rdi, 3; size\ncall _malloc\nmov rbx, rax\ntest r12d, r12d\njle loc_16D2\nmovsxd rax, r13d\nxor esi, esi; nmemb\nlea r10, ds:0[rax*4]\nlea rax, [rax+r12*4]\nxor r12d, r12d\nlea r8, [r10+r14]\nlea r9, [r14+rax*4]\nnop word ptr [rax+rax+00h]\nloc_1628:\ntest r13d, r13d\njle short loc_1690\nloc_162D:\nmov rdi, r8\nsub rdi, r10\nloc_1633:\nmov edx, [rdi]\nlea rcx, [rbx+rsi*8]\ntest r12d, r12d\njle short loc_1670\nloc_163E:\nmov rax, rbx\njmp short loc_1651\nloc_1648:\nadd rax, 8\ncmp rcx, rax\njz short loc_1670\nloc_1651:\ncmp [rax], edx\njnz short loc_1648\nadd rdi, 4\nadd dword ptr [rax+4], 1\ncmp rdi, r8\njz short loc_1690\nmov edx, [rdi]\njmp short loc_163E\nloc_1670:\nlea rax, [rbx+rsi*8]\nadd rdi, 4\nadd r12d, 1\nmov [rax], edx\nmov dword ptr [rax+4], 1\ncmp rdi, r8\njz short loc_16C0\nmovsxd rsi, r12d\njmp short loc_1633\nloc_1690:\nadd r8, 10h\ncmp r8, r9\njnz short loc_1628\nloc_1699:\nmov rdi, rbx; base\nlea rcx, compare_freq; compar\nmov edx, 8; size\ncall _qsort\nmov [rbp+0], r12d\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_16C0:\nlea r8, [rdi+10h]\nmovsxd rsi, r12d\ncmp r8, r9\njnz loc_162D\njmp short loc_1699\nloc_16D2:\nxor esi, esi\nxor r12d, r12d\njmp short loc_1699", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, int a3, int *a4)\n{\n __int64 v5; // r12\n _DWORD *v7; // rbx\n size_t v8; // rsi\n __int64 v9; // r10\n __int64 v10; // rax\n int v11; // r12d\n int *v12; // r8\n int *v13; // r9\n int *v14; // rdi\n int v15; // edx\n _DWORD *v16; // rax\n _DWORD *v17; // rax\n\n v5 = a2;\n v7 = malloc(8LL * a3 * a2);\n if ( a2 <= 0 )\n {\n v8 = 0LL;\n v11 = 0;\n }\n else\n {\n v8 = 0LL;\n v9 = 4LL * a3;\n v10 = a3 + 4 * v5;\n v11 = 0;\n v12 = (int *)(v9 + a1);\n v13 = (int *)(a1 + 4 * v10);\n while ( a3 <= 0 )\n {\nLABEL_13:\n v12 += 4;\n if ( v12 == v13 )\n goto LABEL_14;\n }\n while ( 2 )\n {\n v14 = &v12[v9 / 0xFFFFFFFFFFFFFFFCLL];\n while ( 1 )\n {\n v15 = *v14;\n if ( v11 > 0 )\n {\n while ( 1 )\n {\n v16 = v7;\n while ( *v16 != v15 )\n {\n v16 += 2;\n if ( &v7[2 * v8] == v16 )\n goto LABEL_11;\n }\n ++v14;\n ++v16[1];\n if ( v14 == v12 )\n goto LABEL_13;\n v15 = *v14;\n }\n }\nLABEL_11:\n v17 = &v7[2 * v8];\n ++v14;\n ++v11;\n *v17 = v15;\n v17[1] = 1;\n if ( v14 == v12 )\n break;\n v8 = v11;\n }\n v12 = v14 + 4;\n v8 = v11;\n if ( v14 + 4 != v13 )\n continue;\n break;\n }\n }\nLABEL_14:\n qsort(v7, v8, 8uLL, compare_freq);\n *a4 = v11;\n return v7;\n}", + "ida_strip_asm": "sub_15D0:\nendbr64\npush r14\nmov r14, rdi\npush r13\nmov r13d, edx\npush r12\nmovsxd r12, esi\nmov edi, r12d\npush rbp\nmov rbp, rcx\nimul edi, edx\npush rbx\nmovsxd rdi, edi\nshl rdi, 3; size\ncall _malloc\nmov rbx, rax\ntest r12d, r12d\njle loc_16D2\nmovsxd rax, r13d\nxor esi, esi; nmemb\nlea r10, ds:0[rax*4]\nlea rax, [rax+r12*4]\nxor r12d, r12d\nlea r8, [r10+r14]\nlea r9, [r14+rax*4]\nnop word ptr [rax+rax+00h]\nloc_1628:\ntest r13d, r13d\njle short loc_1690\nloc_162D:\nmov rdi, r8\nsub rdi, r10\nloc_1633:\nmov edx, [rdi]\nlea rcx, [rbx+rsi*8]\ntest r12d, r12d\njle short loc_1670\nloc_163E:\nmov rax, rbx\njmp short loc_1651\nloc_1648:\nadd rax, 8\ncmp rcx, rax\njz short loc_1670\nloc_1651:\ncmp [rax], edx\njnz short loc_1648\nadd rdi, 4\nadd dword ptr [rax+4], 1\ncmp rdi, r8\njz short loc_1690\nmov edx, [rdi]\njmp short loc_163E\nloc_1670:\nlea rax, [rbx+rsi*8]\nadd rdi, 4\nadd r12d, 1\nmov [rax], edx\nmov dword ptr [rax+4], 1\ncmp rdi, r8\njz short loc_16C0\nmovsxd rsi, r12d\njmp short loc_1633\nloc_1690:\nadd r8, 10h\ncmp r8, r9\njnz short loc_1628\nloc_1699:\nmov rdi, rbx; base\nlea rcx, compar; compar\nmov edx, 8; size\ncall _qsort\nmov [rbp+0], r12d\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_16C0:\nlea r8, [rdi+10h]\nmovsxd rsi, r12d\ncmp r8, r9\njnz loc_162D\njmp short loc_1699\nloc_16D2:\nxor esi, esi\nxor r12d, r12d\njmp short loc_1699", + "ida_strip_pseudo": "_DWORD *__fastcall sub_15D0(__int64 a1, int a2, int a3, int *a4)\n{\n __int64 v5; // r12\n _DWORD *v7; // rbx\n size_t v8; // rsi\n __int64 v9; // r10\n __int64 v10; // rax\n int v11; // r12d\n int *v12; // r8\n int *v13; // r9\n int *v14; // rdi\n int v15; // edx\n _DWORD *v16; // rax\n _DWORD *v17; // rax\n\n v5 = a2;\n v7 = malloc(8LL * a3 * a2);\n if ( a2 <= 0 )\n {\n v8 = 0LL;\n v11 = 0;\n }\n else\n {\n v8 = 0LL;\n v9 = 4LL * a3;\n v10 = a3 + 4 * v5;\n v11 = 0;\n v12 = (int *)(v9 + a1);\n v13 = (int *)(a1 + 4 * v10);\n while ( a3 <= 0 )\n {\nLABEL_13:\n v12 += 4;\n if ( v12 == v13 )\n goto LABEL_14;\n }\n while ( 2 )\n {\n v14 = &v12[v9 / 0xFFFFFFFFFFFFFFFCLL];\n while ( 1 )\n {\n v15 = *v14;\n if ( v11 > 0 )\n {\n while ( 1 )\n {\n v16 = v7;\n while ( *v16 != v15 )\n {\n v16 += 2;\n if ( &v7[2 * v8] == v16 )\n goto LABEL_11;\n }\n ++v14;\n ++v16[1];\n if ( v14 == v12 )\n goto LABEL_13;\n v15 = *v14;\n }\n }\nLABEL_11:\n v17 = &v7[2 * v8];\n ++v14;\n ++v11;\n *v17 = v15;\n v17[1] = 1;\n if ( v14 == v12 )\n break;\n v8 = v11;\n }\n v12 = v14 + 4;\n v8 = v11;\n if ( v14 + 4 != v13 )\n continue;\n break;\n }\n }\nLABEL_14:\n qsort(v7, v8, 8uLL, compar);\n *a4 = v11;\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_15D0(long long a1, int a2, int a3, int *a4) {\n long long v5;\n uint32_t *v7;\n unsigned int v8;\n long long v9;\n long long v10;\n int v11;\n int *v12;\n int *v13;\n int *v14;\n int v15;\n uint32_t *v16;\n uint32_t *v17;\n v5 = a2;\n v7 = malloc(8LL * a3 * a2);\n if (a2 <= 0) {\n v8 = 0LL;\n v11 = 0;\n } else {\n v8 = 0LL;\n v9 = 4LL * a3;\n v10 = a3 + 4 * v5;\n v11 = 0;\n v12 = (int *)(v9 + a1);\n v13 = (int *)(a1 + 4 * v10);\n while (a3 <= 0) {\n LABEL_13:\n v12 += 4;\n if (v12 == v13) goto LABEL_14;\n }\n while (2) {\n v14 = &v12[v9 / 18446744073709551612LL];\n while (1) {\n v15 = *v14;\n if (v11 > 0) {\n while (1) {\n v16 = v7;\n while (*v16 != v15) {\n v16 += 2;\n if (&v7[2 * v8] == v16) goto LABEL_11;\n }\n ++v14;\n ++v16[1];\n if (v14 == v12) goto LABEL_13;\n v15 = *v14;\n }\n }\n LABEL_11:\n v17 = &v7[2 * v8];\n ++v14;\n ++v11;\n *v17 = v15;\n v17[1] = 1;\n if (v14 == v12) break;\n v8 = v11;\n }\n v12 = v14 + 4;\n v8 = v11;\n if (v14 + 4 != v13) continue;\n break;\n }\n }\nLABEL_14:\n qsort(v7, v8, 8uLL, compar);\n *a4 = v11;\n return v7;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, int a3, int *a4) {\n long long v5;\n uint32_t *v7;\n unsigned int v8;\n long long v9;\n long long v10;\n int v11;\n int *v12;\n int *v13;\n int *v14;\n int v15;\n uint32_t *v16;\n uint32_t *v17;\n v5 = a2;\n v7 = malloc(8LL * a3 * a2);\n if (a2 <= 0) {\n v8 = 0LL;\n v11 = 0;\n } else {\n v8 = 0LL;\n v9 = 4LL * a3;\n v10 = a3 + 4 * v5;\n v11 = 0;\n v12 = (int *)(v9 + a1);\n v13 = (int *)(a1 + 4 * v10);\n while (a3 <= 0) {\n LABEL_13:\n v12 += 4;\n if (v12 == v13) goto LABEL_14;\n }\n while (2) {\n v14 = &v12[v9 / 18446744073709551612LL];\n while (1) {\n v15 = *v14;\n if (v11 > 0) {\n while (1) {\n v16 = v7;\n while (*v16 != v15) {\n v16 += 2;\n if (&v7[2 * v8] == v16) goto LABEL_11;\n }\n ++v14;\n ++v16[1];\n if (v14 == v12) goto LABEL_13;\n v15 = *v14;\n }\n }\n LABEL_11:\n v17 = &v7[2 * v8];\n ++v14;\n ++v11;\n *v17 = v15;\n v17[1] = 1;\n if (v14 == v12) break;\n v8 = v11;\n }\n v12 = v14 + 4;\n v8 = v11;\n if (v14 + 4 != v13) continue;\n break;\n }\n }\nLABEL_14:\n qsort(v7, v8, 8uLL, compare_freq);\n *a4 = v11;\n return v7;\n}" + }, + { + "index": 40, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int num;\n\n int count;\n\n} freq_t;\n\n\n\nint compare_freq(const void *a, const void *b) {\n\n freq_t *fa = (freq_t *)a;\n\n freq_t *fb = (freq_t *)b;\n\n return fa->num - fb->num;\n\n}\n\n\n\n", + "func": "freq_t *func0(int nums[][4], int num_lists, int list_size, int *unique_count) {\n freq_t *freq = malloc(num_lists * list_size * sizeof(freq_t));\n int total = 0;\n for (int i = 0; i < num_lists; i++) {\n for (int j = 0; j < list_size; j++) {\n int found = 0;\n for (int k = 0; k < total; k++) {\n if (freq[k].num == nums[i][j]) {\n freq[k].count++;\n found = 1;\n break;\n }\n }\n if (!found) {\n freq[total].num = nums[i][j];\n freq[total].count = 1;\n total++;\n }\n }\n }\n qsort(freq, total, sizeof(freq_t), compare_freq);\n *unique_count = total;\n return freq;\n}", + "test": "int main() {\n\n int unique_count1, unique_count2, unique_count3;\n\n\n\n int test1[][4] = {{1, 2, 3, 2}, {4, 5, 6, 2}, {7, 1, 9, 5}};\n\n freq_t *result1 = func0(test1, 3, 4, &unique_count1);\n\n freq_t expected1[] = {{1,2}, {2,3}, {3,1}, {4,1}, {5,2}, {6,1}, {7,1}, {9,1}};\n\n assert(unique_count1 == 8);\n\n for(int i = 0; i < unique_count1; i++) {\n\n assert(result1[i].num == expected1[i].num);\n\n assert(result1[i].count == expected1[i].count);\n\n }\n\n free(result1);\n\n\n\n int test2[][4] = {{1,2,3,4}, {5,6,7,8}, {9,10,11,12}};\n\n freq_t *result2 = func0(test2, 3, 4, &unique_count2);\n\n freq_t expected2[] = {{1,1}, {2,1}, {3,1}, {4,1}, {5,1}, {6,1}, {7,1}, {8,1}, {9,1}, {10,1}, {11,1}, {12,1}};\n\n assert(unique_count2 == 12);\n\n for(int i = 0; i < unique_count2; i++) {\n\n assert(result2[i].num == expected2[i].num);\n\n assert(result2[i].count == expected2[i].count);\n\n }\n\n free(result2);\n\n\n\n int test3[][4] = {{15,20,30,40}, {80,90,100,110}, {30,30,80,90}};\n\n freq_t *result3 = func0(test3, 3, 4, &unique_count3);\n\n freq_t expected3[] = {{15,1}, {20,1}, {30,3}, {40,1}, {80,2}, {90,2}, {100,1}, {110,1}};\n\n assert(unique_count3 == 8);\n\n for(int i = 0; i < unique_count3; i++) {\n\n assert(result3[i].num == expected3[i].num);\n\n assert(result3[i].count == expected3[i].count);\n\n }\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\nmov %rdi,%r14\nmov %esi,%edi\nimul %edx,%edi\npush %r13\nmov %edx,%r13d\npush %r12\npush %rbp\nmov %rcx,%rbp\npush %rbx\nmovslq %edi,%rdi\nmov %esi,%ebx\nshl $0x3,%rdi\ncallq 10d0 \nmov %rax,%r12\ntest %ebx,%ebx\njle 1985 \nlea -0x1(%r13),%r9d\nlea -0x1(%rbx),%eax\nxor %ebx,%ebx\nlea (%r9,%rax,4),%rax\nlea 0x4(%r14,%r9,4),%rdi\nnot %r9\nlea 0x14(%r14,%rax,4),%r10\nshl $0x2,%r9\nlea 0x8(%r12),%r8\nnopw %cs:0x0(%rax,%rax,1)\ntest %r13d,%r13d\njle 193a \nlea (%r9,%rdi,1),%rsi\nmov (%rsi),%edx\ntest %ebx,%ebx\nje 1970 \nlea -0x1(%rbx),%ecx\nmov %r12,%rax\nlea (%r8,%rcx,8),%rcx\njmp 1929 \nnopl 0x0(%rax,%rax,1)\nadd $0x8,%rax\ncmp %rcx,%rax\nje 1970 \ncmp %edx,(%rax)\njne 1920 \naddl $0x1,0x4(%rax)\nadd $0x4,%rsi\ncmp %rdi,%rsi\njne 1909 \nadd $0x10,%rdi\ncmp %r10,%rdi\njne 1900 \nmovslq %ebx,%rsi\nmov %r12,%rdi\nlea -0xc0(%rip),%rcx\nmov $0x8,%edx\ncallq 10a0 \nmov %ebx,0x0(%rbp)\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopl 0x0(%rax)\nmovslq %ebx,%rax\nadd $0x1,%ebx\nlea (%r12,%rax,8),%rax\nmov %edx,(%rax)\nmovl $0x1,0x4(%rax)\njmp 1931 \nxor %esi,%esi\nxor %ebx,%ebx\njmp 1946 \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\nmov r14, rdi\npush r13\nmov r13d, edx\npush r12\nmovsxd r12, esi\nmov edi, r12d\npush rbp\nmov rbp, rcx\nimul edi, edx\npush rbx\nmovsxd rdi, edi\nshl rdi, 3; size\ncall _malloc\nmov rbx, rax\ntest r12d, r12d\njle loc_1762\nmovsxd rax, r13d\nxor esi, esi; nmemb\nlea r10, ds:0[rax*4]\nlea rax, [rax+r12*4]\nxor r12d, r12d\nlea r8, [r10+r14]\nlea r9, [r14+rax*4]\nnop word ptr [rax+rax+00h]\nloc_16B8:\ntest r13d, r13d\njle short loc_1720\nloc_16BD:\nmov rdi, r8\nsub rdi, r10\nloc_16C3:\nmov edx, [rdi]\nlea rcx, [rbx+rsi*8]\ntest r12d, r12d\njle short loc_1700\nloc_16CE:\nmov rax, rbx\njmp short loc_16E1\nloc_16D8:\nadd rax, 8\ncmp rax, rcx\njz short loc_1700\nloc_16E1:\ncmp [rax], edx\njnz short loc_16D8\nadd rdi, 4\nadd dword ptr [rax+4], 1\ncmp rdi, r8\njz short loc_1720\nmov edx, [rdi]\njmp short loc_16CE\nloc_1700:\nlea rax, [rbx+rsi*8]\nadd rdi, 4\nadd r12d, 1\nmov [rax], edx\nmov dword ptr [rax+4], 1\ncmp rdi, r8\njz short loc_1750\nmovsxd rsi, r12d\njmp short loc_16C3\nloc_1720:\nadd r8, 10h\ncmp r8, r9\njnz short loc_16B8\nloc_1729:\nmov rdi, rbx; base\nlea rcx, compare_freq; compar\nmov edx, 8; size\ncall _qsort\nmov [rbp+0], r12d\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1750:\nlea r8, [rdi+10h]\nmovsxd rsi, r12d\ncmp r8, r9\njnz loc_16BD\njmp short loc_1729\nloc_1762:\nxor esi, esi\nxor r12d, r12d\njmp short loc_1729", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, int a3, int *a4)\n{\n __int64 v5; // r12\n _DWORD *v7; // rbx\n size_t v8; // rsi\n __int64 v9; // r10\n __int64 v10; // rax\n int v11; // r12d\n int *v12; // r8\n int *v13; // r9\n int *v14; // rdi\n int v15; // edx\n _DWORD *v16; // rax\n _DWORD *v17; // rax\n\n v5 = a2;\n v7 = malloc(8LL * a3 * a2);\n if ( a2 <= 0 )\n {\n v8 = 0LL;\n v11 = 0;\n }\n else\n {\n v8 = 0LL;\n v9 = 4LL * a3;\n v10 = a3 + 4 * v5;\n v11 = 0;\n v12 = (int *)(v9 + a1);\n v13 = (int *)(a1 + 4 * v10);\n while ( a3 <= 0 )\n {\nLABEL_13:\n v12 += 4;\n if ( v12 == v13 )\n goto LABEL_14;\n }\n while ( 2 )\n {\n v14 = &v12[v9 / 0xFFFFFFFFFFFFFFFCLL];\n while ( 1 )\n {\n v15 = *v14;\n if ( v11 > 0 )\n {\n while ( 1 )\n {\n v16 = v7;\n while ( *v16 != v15 )\n {\n v16 += 2;\n if ( v16 == &v7[2 * v8] )\n goto LABEL_11;\n }\n ++v14;\n ++v16[1];\n if ( v14 == v12 )\n goto LABEL_13;\n v15 = *v14;\n }\n }\nLABEL_11:\n v17 = &v7[2 * v8];\n ++v14;\n ++v11;\n *v17 = v15;\n v17[1] = 1;\n if ( v14 == v12 )\n break;\n v8 = v11;\n }\n v12 = v14 + 4;\n v8 = v11;\n if ( v14 + 4 != v13 )\n continue;\n break;\n }\n }\nLABEL_14:\n qsort(v7, v8, 8uLL, compare_freq);\n *a4 = v11;\n return v7;\n}", + "ida_strip_asm": "sub_1660:\nendbr64\npush r14\nmov r14, rdi\npush r13\nmov r13d, edx\npush r12\nmovsxd r12, esi\nmov edi, r12d\npush rbp\nmov rbp, rcx\nimul edi, edx\npush rbx\nmovsxd rdi, edi\nshl rdi, 3; size\ncall _malloc\nmov rbx, rax\ntest r12d, r12d\njle loc_1762\nmovsxd rax, r13d\nxor esi, esi; nmemb\nlea r10, ds:0[rax*4]\nlea rax, [rax+r12*4]\nxor r12d, r12d\nlea r8, [r10+r14]\nlea r9, [r14+rax*4]\nnop word ptr [rax+rax+00h]\nloc_16B8:\ntest r13d, r13d\njle short loc_1720\nloc_16BD:\nmov rdi, r8\nsub rdi, r10\nloc_16C3:\nmov edx, [rdi]\nlea rcx, [rbx+rsi*8]\ntest r12d, r12d\njle short loc_1700\nloc_16CE:\nmov rax, rbx\njmp short loc_16E1\nloc_16D8:\nadd rax, 8\ncmp rax, rcx\njz short loc_1700\nloc_16E1:\ncmp [rax], edx\njnz short loc_16D8\nadd rdi, 4\nadd dword ptr [rax+4], 1\ncmp rdi, r8\njz short loc_1720\nmov edx, [rdi]\njmp short loc_16CE\nloc_1700:\nlea rax, [rbx+rsi*8]\nadd rdi, 4\nadd r12d, 1\nmov [rax], edx\nmov dword ptr [rax+4], 1\ncmp rdi, r8\njz short loc_1750\nmovsxd rsi, r12d\njmp short loc_16C3\nloc_1720:\nadd r8, 10h\ncmp r8, r9\njnz short loc_16B8\nloc_1729:\nmov rdi, rbx; base\nlea rcx, compar; compar\nmov edx, 8; size\ncall _qsort\nmov [rbp+0], r12d\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1750:\nlea r8, [rdi+10h]\nmovsxd rsi, r12d\ncmp r8, r9\njnz loc_16BD\njmp short loc_1729\nloc_1762:\nxor esi, esi\nxor r12d, r12d\njmp short loc_1729", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1660(__int64 a1, int a2, int a3, int *a4)\n{\n __int64 v5; // r12\n _DWORD *v7; // rbx\n size_t v8; // rsi\n __int64 v9; // r10\n __int64 v10; // rax\n int v11; // r12d\n int *v12; // r8\n int *v13; // r9\n int *v14; // rdi\n int v15; // edx\n _DWORD *v16; // rax\n _DWORD *v17; // rax\n\n v5 = a2;\n v7 = malloc(8LL * a3 * a2);\n if ( a2 <= 0 )\n {\n v8 = 0LL;\n v11 = 0;\n }\n else\n {\n v8 = 0LL;\n v9 = 4LL * a3;\n v10 = a3 + 4 * v5;\n v11 = 0;\n v12 = (int *)(v9 + a1);\n v13 = (int *)(a1 + 4 * v10);\n while ( a3 <= 0 )\n {\nLABEL_13:\n v12 += 4;\n if ( v12 == v13 )\n goto LABEL_14;\n }\n while ( 2 )\n {\n v14 = &v12[v9 / 0xFFFFFFFFFFFFFFFCLL];\n while ( 1 )\n {\n v15 = *v14;\n if ( v11 > 0 )\n {\n while ( 1 )\n {\n v16 = v7;\n while ( *v16 != v15 )\n {\n v16 += 2;\n if ( v16 == &v7[2 * v8] )\n goto LABEL_11;\n }\n ++v14;\n ++v16[1];\n if ( v14 == v12 )\n goto LABEL_13;\n v15 = *v14;\n }\n }\nLABEL_11:\n v17 = &v7[2 * v8];\n ++v14;\n ++v11;\n *v17 = v15;\n v17[1] = 1;\n if ( v14 == v12 )\n break;\n v8 = v11;\n }\n v12 = v14 + 4;\n v8 = v11;\n if ( v14 + 4 != v13 )\n continue;\n break;\n }\n }\nLABEL_14:\n qsort(v7, v8, 8uLL, compar);\n *a4 = v11;\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1660(long long a1, int a2, int a3, int *a4) {\n long long v5;\n uint32_t *v7;\n unsigned int v8;\n long long v9;\n long long v10;\n int v11;\n int *v12;\n int *v13;\n int *v14;\n int v15;\n uint32_t *v16;\n uint32_t *v17;\n v5 = a2;\n v7 = malloc(8LL * a3 * a2);\n if (a2 <= 0) {\n v8 = 0LL;\n v11 = 0;\n } else {\n v8 = 0LL;\n v9 = 4LL * a3;\n v10 = a3 + 4 * v5;\n v11 = 0;\n v12 = (int *)(v9 + a1);\n v13 = (int *)(a1 + 4 * v10);\n while (a3 <= 0) {\n LABEL_13:\n v12 += 4;\n if (v12 == v13) goto LABEL_14;\n }\n while (2) {\n v14 = &v12[v9 / 18446744073709551612LL];\n while (1) {\n v15 = *v14;\n if (v11 > 0) {\n while (1) {\n v16 = v7;\n while (*v16 != v15) {\n v16 += 2;\n if (v16 == &v7[2 * v8]) goto LABEL_11;\n }\n ++v14;\n ++v16[1];\n if (v14 == v12) goto LABEL_13;\n v15 = *v14;\n }\n }\n LABEL_11:\n v17 = &v7[2 * v8];\n ++v14;\n ++v11;\n *v17 = v15;\n v17[1] = 1;\n if (v14 == v12) break;\n v8 = v11;\n }\n v12 = v14 + 4;\n v8 = v11;\n if (v14 + 4 != v13) continue;\n break;\n }\n }\nLABEL_14:\n qsort(v7, v8, 8uLL, compar);\n *a4 = v11;\n return v7;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, int a3, int *a4) {\n long long v5;\n uint32_t *v7;\n unsigned int v8;\n long long v9;\n long long v10;\n int v11;\n int *v12;\n int *v13;\n int *v14;\n int v15;\n uint32_t *v16;\n uint32_t *v17;\n v5 = a2;\n v7 = malloc(8LL * a3 * a2);\n if (a2 <= 0) {\n v8 = 0LL;\n v11 = 0;\n } else {\n v8 = 0LL;\n v9 = 4LL * a3;\n v10 = a3 + 4 * v5;\n v11 = 0;\n v12 = (int *)(v9 + a1);\n v13 = (int *)(a1 + 4 * v10);\n while (a3 <= 0) {\n LABEL_13:\n v12 += 4;\n if (v12 == v13) goto LABEL_14;\n }\n while (2) {\n v14 = &v12[v9 / 18446744073709551612LL];\n while (1) {\n v15 = *v14;\n if (v11 > 0) {\n while (1) {\n v16 = v7;\n while (*v16 != v15) {\n v16 += 2;\n if (v16 == &v7[2 * v8]) goto LABEL_11;\n }\n ++v14;\n ++v16[1];\n if (v14 == v12) goto LABEL_13;\n v15 = *v14;\n }\n }\n LABEL_11:\n v17 = &v7[2 * v8];\n ++v14;\n ++v11;\n *v17 = v15;\n v17[1] = 1;\n if (v14 == v12) break;\n v8 = v11;\n }\n v12 = v14 + 4;\n v8 = v11;\n if (v14 + 4 != v13) continue;\n break;\n }\n }\nLABEL_14:\n qsort(v7, v8, 8uLL, compare_freq);\n *a4 = v11;\n return v7;\n}" + }, + { + "index": 41, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "int *func0(int *nums, int length, int *output_length) {\n int *even_nums = malloc(length * sizeof(int));\n int count = 0;\n for (int i = 0; i < length; i++) {\n if (nums[i] % 2 == 0) {\n even_nums[count++] = nums[i];\n }\n }\n *output_length = count;\n return even_nums;\n}", + "test": "int main() {\n\n int output_length;\n\n\n\n int nums1[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n int expected1[] = {2, 4, 6, 8, 10};\n\n int *result1 = func0(nums1, 10, &output_length);\n\n assert(output_length == 5);\n\n for (int i = 0; i < output_length; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n free(result1);\n\n\n\n int nums2[] = {10, 20, 45, 67, 84, 93};\n\n int expected2[] = {10, 20, 84};\n\n int *result2 = func0(nums2, 6, &output_length);\n\n assert(output_length == 3);\n\n for (int i = 0; i < output_length; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n free(result2);\n\n\n\n int nums3[] = {5, 7, 9, 8, 6, 4, 3};\n\n int expected3[] = {8, 6, 4};\n\n int *result3 = func0(nums3, 7, &output_length);\n\n assert(output_length == 3);\n\n for (int i = 0; i < output_length; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n free(result3);\n\n\n\n printf(\"All test cases passed!\\n\");\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmov -0x1c(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 1259 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nand $0x1,%eax\ntest %eax,%eax\njne 1255 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x10(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x10(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1205 \nmov -0x28(%rbp),%rax\nmov -0x10(%rbp),%edx\nmov %edx,(%rax)\nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp short loc_1259\nloc_1205:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njnz short loc_1255\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_1255:\nadd [rbp+var_C], 1\nloc_1259:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_1205\nmov rax, [rbp+var_28]\nmov edx, [rbp+var_10]\nmov [rax], edx\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, _DWORD *a3)\n{\n int v3; // eax\n int v6; // [rsp+20h] [rbp-10h]\n int i; // [rsp+24h] [rbp-Ch]\n _DWORD *v8; // [rsp+28h] [rbp-8h]\n\n v8 = malloc(4LL * a2);\n v6 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( (*(_DWORD *)(4LL * i + a1) & 1) == 0 )\n {\n v3 = v6++;\n v8[v3] = *(_DWORD *)(4LL * i + a1);\n }\n }\n *a3 = v6;\n return v8;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp short loc_1259\nloc_1205:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njnz short loc_1255\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_1255:\nadd [rbp+var_C], 1\nloc_1259:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_1205\nmov rax, [rbp+var_28]\nmov edx, [rbp+var_10]\nmov [rax], edx\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11C9(__int64 a1, int a2, _DWORD *a3)\n{\n int v3; // eax\n int v6; // [rsp+20h] [rbp-10h]\n int i; // [rsp+24h] [rbp-Ch]\n _DWORD *v8; // [rsp+28h] [rbp-8h]\n\n v8 = malloc(4LL * a2);\n v6 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( (*(_DWORD *)(4LL * i + a1) & 1) == 0 )\n {\n v3 = v6++;\n v8[v3] = *(_DWORD *)(4LL * i + a1);\n }\n }\n *a3 = v6;\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11C9(long long a1, int a2, uint32_t *a3) {\n int v3;\n int v6;\n int i;\n uint32_t *v8;\n v8 = malloc(4LL * a2);\n v6 = 0;\n for (i = 0; i < a2; ++i) {\n if ((*(uint32_t *)(4LL * i + a1) & 1) == 0) {\n v3 = v6++;\n v8[v3] = *(uint32_t *)(4LL * i + a1);\n }\n }\n *a3 = v6;\n return v8;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, uint32_t *a3) {\n int v3;\n int v6;\n int i;\n uint32_t *v8;\n v8 = malloc(4LL * a2);\n v6 = 0;\n for (i = 0; i < a2; ++i) {\n if ((*(uint32_t *)(4LL * i + a1) & 1) == 0) {\n v3 = v6++;\n v8[v3] = *(uint32_t *)(4LL * i + a1);\n }\n }\n *a3 = v6;\n return v8;\n}" + }, + { + "index": 41, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "int *func0(int *nums, int length, int *output_length) {\n int *even_nums = malloc(length * sizeof(int));\n int count = 0;\n for (int i = 0; i < length; i++) {\n if (nums[i] % 2 == 0) {\n even_nums[count++] = nums[i];\n }\n }\n *output_length = count;\n return even_nums;\n}", + "test": "int main() {\n\n int output_length;\n\n\n\n int nums1[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n int expected1[] = {2, 4, 6, 8, 10};\n\n int *result1 = func0(nums1, 10, &output_length);\n\n assert(output_length == 5);\n\n for (int i = 0; i < output_length; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n free(result1);\n\n\n\n int nums2[] = {10, 20, 45, 67, 84, 93};\n\n int expected2[] = {10, 20, 84};\n\n int *result2 = func0(nums2, 6, &output_length);\n\n assert(output_length == 3);\n\n for (int i = 0; i < output_length; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n free(result2);\n\n\n\n int nums3[] = {5, 7, 9, 8, 6, 4, 3};\n\n int expected3[] = {8, 6, 4};\n\n int *result3 = func0(nums3, 7, &output_length);\n\n assert(output_length == 3);\n\n for (int i = 0; i < output_length; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n free(result3);\n\n\n\n printf(\"All test cases passed!\\n\");\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%r12\nmov %esi,%ebp\nmov %rdx,%rbx\nmovslq %esi,%rdi\nshl $0x2,%rdi\ncallq 10d0 \ntest %ebp,%ebp\njle 1217 \nmov %r12,%rdx\nlea -0x1(%rbp),%ecx\nlea 0x4(%r12,%rcx,4),%rdi\nmov $0x0,%esi\njmp 1204 \nadd $0x4,%rdx\ncmp %rdi,%rdx\nje 121c \nmov (%rdx),%ecx\ntest $0x1,%cl\njne 11fb \nmovslq %esi,%r8\nmov %ecx,(%rax,%r8,4)\nlea 0x1(%rsi),%esi\njmp 11fb \nmov $0x0,%esi\nmov %esi,(%rbx)\npop %rbx\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov r13d, esi\nmov rbp, rdx\nmovsxd r12, esi\nshl r12, 2\nmov rdi, r12; size\ncall _malloc\ntest r13d, r13d\njle short loc_121E\nmov rdx, rbx\nlea rdi, [rbx+r12]\nmov esi, 0\njmp short loc_120B\nloc_1202:\nadd rdx, 4\ncmp rdx, rdi\njz short loc_1223\nloc_120B:\nmov ecx, [rdx]\ntest cl, 1\njnz short loc_1202\nmovsxd r8, esi\nmov [rax+r8*4], ecx\nlea esi, [rsi+1]\njmp short loc_1202\nloc_121E:\nmov esi, 0\nloc_1223:\nmov [rbp+0], esi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(_DWORD *a1, int a2, _DWORD *a3)\n{\n size_t v4; // r12\n _DWORD *result; // rax\n _DWORD *v6; // rdx\n int v7; // esi\n\n v4 = a2;\n result = malloc(v4 * 4);\n if ( a2 <= 0 )\n {\n v7 = 0;\n }\n else\n {\n v6 = a1;\n v7 = 0;\n do\n {\n if ( (*v6 & 1) == 0 )\n result[v7++] = *v6;\n ++v6;\n }\n while ( v6 != &a1[v4] );\n }\n *a3 = v7;\n return result;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov r13d, esi\nmov rbp, rdx\nmovsxd r12, esi\nshl r12, 2\nmov rdi, r12; size\ncall _malloc\ntest r13d, r13d\njle short loc_121E\nmov rdx, rbx\nlea rdi, [rbx+r12]\nmov esi, 0\njmp short loc_120B\nloc_1202:\nadd rdx, 4\ncmp rdx, rdi\njz short loc_1223\nloc_120B:\nmov ecx, [rdx]\ntest cl, 1\njnz short loc_1202\nmovsxd r8, esi\nmov [rax+r8*4], ecx\nlea esi, [rsi+1]\njmp short loc_1202\nloc_121E:\nmov esi, 0\nloc_1223:\nmov [rbp+0], esi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11C9(_DWORD *a1, int a2, _DWORD *a3)\n{\n size_t v4; // r12\n _DWORD *result; // rax\n _DWORD *v6; // rdx\n int v7; // esi\n\n v4 = a2;\n result = malloc(v4 * 4);\n if ( a2 <= 0 )\n {\n v7 = 0;\n }\n else\n {\n v6 = a1;\n v7 = 0;\n do\n {\n if ( (*v6 & 1) == 0 )\n result[v7++] = *v6;\n ++v6;\n }\n while ( v6 != &a1[v4] );\n }\n *a3 = v7;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11C9(uint32_t *a1, int a2, uint32_t *a3) {\n unsigned int v4;\n uint32_t *result;\n uint32_t *v6;\n int v7;\n v4 = a2;\n result = malloc(v4 * 4);\n if (a2 <= 0) {\n v7 = 0;\n } else {\n v6 = a1;\n v7 = 0;\n do {\n if ((*v6 & 1) == 0) result[v7++] = *v6;\n ++v6;\n } while (v6 != &a1[v4]);\n }\n *a3 = v7;\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(uint32_t *a1, int a2, uint32_t *a3) {\n unsigned int v4;\n uint32_t *result;\n uint32_t *v6;\n int v7;\n v4 = a2;\n result = malloc(v4 * 4);\n if (a2 <= 0) {\n v7 = 0;\n } else {\n v6 = a1;\n v7 = 0;\n do {\n if ((*v6 & 1) == 0) result[v7++] = *v6;\n ++v6;\n } while (v6 != &a1[v4]);\n }\n *a3 = v7;\n return result;\n}" + }, + { + "index": 41, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "int *func0(int *nums, int length, int *output_length) {\n int *even_nums = malloc(length * sizeof(int));\n int count = 0;\n for (int i = 0; i < length; i++) {\n if (nums[i] % 2 == 0) {\n even_nums[count++] = nums[i];\n }\n }\n *output_length = count;\n return even_nums;\n}", + "test": "int main() {\n\n int output_length;\n\n\n\n int nums1[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n int expected1[] = {2, 4, 6, 8, 10};\n\n int *result1 = func0(nums1, 10, &output_length);\n\n assert(output_length == 5);\n\n for (int i = 0; i < output_length; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n free(result1);\n\n\n\n int nums2[] = {10, 20, 45, 67, 84, 93};\n\n int expected2[] = {10, 20, 84};\n\n int *result2 = func0(nums2, 6, &output_length);\n\n assert(output_length == 3);\n\n for (int i = 0; i < output_length; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n free(result2);\n\n\n\n int nums3[] = {5, 7, 9, 8, 6, 4, 3};\n\n int expected3[] = {8, 6, 4};\n\n int *result3 = func0(nums3, 7, &output_length);\n\n assert(output_length == 3);\n\n for (int i = 0; i < output_length; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n free(result3);\n\n\n\n printf(\"All test cases passed!\\n\");\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %rdx,%r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nmovslq %esi,%rdi\nmov %rdi,%rbp\nshl $0x2,%rdi\ncallq 10d0 \ntest %ebp,%ebp\njle 14d8 \nlea -0x1(%rbp),%edx\nmov %rbx,%rdi\nxor %esi,%esi\nlea 0x4(%rbx,%rdx,4),%r8\nxchg %ax,%ax\nmov (%rdi),%ecx\ntest $0x1,%cl\njne 14c1 \nmovslq %esi,%r9\nadd $0x1,%esi\nmov %ecx,(%rax,%r9,4)\nadd $0x4,%rdi\ncmp %r8,%rdi\njne 14b0 \npop %rbx\npop %rbp\nmov %esi,(%r12)\npop %r12\nretq\nnopl 0x0(%rax,%rax,1)\nxor %esi,%esi\npop %rbx\npop %rbp\nmov %esi,(%r12)\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r13\nmovsxd r8, esi\nmov r13, rdx\npush r12\nmov r12, r8\npush rbp\nlea rbp, ds:0[r8*4]\npush rbx\nmov rbx, rdi\nmov rdi, rbp; size\nsub rsp, 8\ncall _malloc\ntest r12d, r12d\njle short loc_1490\nmov rcx, rbx\nlea r8, [rbx+rbp]\nxor edi, edi\nnop dword ptr [rax+rax+00000000h]\nloc_1460:\nmov esi, [rcx]\ntest sil, 1\njnz short loc_1472\nmovsxd r9, edi\nadd edi, 1\nmov [rax+r9*4], esi\nloc_1472:\nadd rcx, 4\ncmp rcx, r8\njnz short loc_1460\nmov [r13+0], edi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1490:\nxor edi, edi\nmov [r13+0], edi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(_DWORD *a1, int a2, _DWORD *a3)\n{\n _DWORD *result; // rax\n _DWORD *v6; // rcx\n int v7; // edi\n __int64 v8; // r9\n\n result = malloc(4LL * a2);\n if ( a2 <= 0 )\n {\n *a3 = 0;\n }\n else\n {\n v6 = a1;\n v7 = 0;\n do\n {\n if ( (*v6 & 1) == 0 )\n {\n v8 = v7++;\n result[v8] = *v6;\n }\n ++v6;\n }\n while ( v6 != &a1[a2] );\n *a3 = v7;\n }\n return result;\n}", + "ida_strip_asm": "sub_1420:\nendbr64\npush r13\nmovsxd r8, esi\nmov r13, rdx\npush r12\nmov r12, r8\npush rbp\nlea rbp, ds:0[r8*4]\npush rbx\nmov rbx, rdi\nmov rdi, rbp; size\nsub rsp, 8\ncall _malloc\ntest r12d, r12d\njle short loc_1490\nmov rcx, rbx\nlea r8, [rbx+rbp]\nxor edi, edi\nnop dword ptr [rax+rax+00000000h]\nloc_1460:\nmov esi, [rcx]\ntest sil, 1\njnz short loc_1472\nmovsxd r9, edi\nadd edi, 1\nmov [rax+r9*4], esi\nloc_1472:\nadd rcx, 4\ncmp rcx, r8\njnz short loc_1460\nmov [r13+0], edi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1490:\nxor edi, edi\nmov [r13+0], edi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1420(_DWORD *a1, int a2, _DWORD *a3)\n{\n _DWORD *result; // rax\n _DWORD *v6; // rcx\n int v7; // edi\n __int64 v8; // r9\n\n result = malloc(4LL * a2);\n if ( a2 <= 0 )\n {\n *a3 = 0;\n }\n else\n {\n v6 = a1;\n v7 = 0;\n do\n {\n if ( (*v6 & 1) == 0 )\n {\n v8 = v7++;\n result[v8] = *v6;\n }\n ++v6;\n }\n while ( v6 != &a1[a2] );\n *a3 = v7;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1420(uint32_t *a1, int a2, uint32_t *a3) {\n uint32_t *result;\n uint32_t *v6;\n int v7;\n long long v8;\n result = malloc(4LL * a2);\n if (a2 <= 0) {\n *a3 = 0;\n } else {\n v6 = a1;\n v7 = 0;\n do {\n if ((*v6 & 1) == 0) {\n v8 = v7++;\n result[v8] = *v6;\n }\n ++v6;\n } while (v6 != &a1[a2]);\n *a3 = v7;\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(uint32_t *a1, int a2, uint32_t *a3) {\n uint32_t *result;\n uint32_t *v6;\n int v7;\n long long v8;\n result = malloc(4LL * a2);\n if (a2 <= 0) {\n *a3 = 0;\n } else {\n v6 = a1;\n v7 = 0;\n do {\n if ((*v6 & 1) == 0) {\n v8 = v7++;\n result[v8] = *v6;\n }\n ++v6;\n } while (v6 != &a1[a2]);\n *a3 = v7;\n }\n return result;\n}" + }, + { + "index": 41, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "int *func0(int *nums, int length, int *output_length) {\n int *even_nums = malloc(length * sizeof(int));\n int count = 0;\n for (int i = 0; i < length; i++) {\n if (nums[i] % 2 == 0) {\n even_nums[count++] = nums[i];\n }\n }\n *output_length = count;\n return even_nums;\n}", + "test": "int main() {\n\n int output_length;\n\n\n\n int nums1[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n int expected1[] = {2, 4, 6, 8, 10};\n\n int *result1 = func0(nums1, 10, &output_length);\n\n assert(output_length == 5);\n\n for (int i = 0; i < output_length; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n free(result1);\n\n\n\n int nums2[] = {10, 20, 45, 67, 84, 93};\n\n int expected2[] = {10, 20, 84};\n\n int *result2 = func0(nums2, 6, &output_length);\n\n assert(output_length == 3);\n\n for (int i = 0; i < output_length; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n free(result2);\n\n\n\n int nums3[] = {5, 7, 9, 8, 6, 4, 3};\n\n int expected3[] = {8, 6, 4};\n\n int *result3 = func0(nums3, 7, &output_length);\n\n assert(output_length == 3);\n\n for (int i = 0; i < output_length; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n free(result3);\n\n\n\n printf(\"All test cases passed!\\n\");\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %rdx,%r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nmovslq %esi,%rdi\nmov %rdi,%rbp\nshl $0x2,%rdi\ncallq 10d0 \ntest %ebp,%ebp\njle 1498 \nlea -0x1(%rbp),%edx\nmov %rbx,%rdi\nxor %esi,%esi\nlea 0x4(%rbx,%rdx,4),%r8\nxchg %ax,%ax\nmov (%rdi),%ecx\ntest $0x1,%cl\njne 1481 \nmovslq %esi,%r9\nadd $0x1,%esi\nmov %ecx,(%rax,%r9,4)\nadd $0x4,%rdi\ncmp %r8,%rdi\njne 1470 \npop %rbx\npop %rbp\nmov %esi,(%r12)\npop %r12\nretq\nnopl 0x0(%rax,%rax,1)\nxor %esi,%esi\npop %rbx\npop %rbp\nmov %esi,(%r12)\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r13\nmovsxd r8, esi\nmov r13, rdx\npush r12\nmov r12, r8\npush rbp\nlea rbp, ds:0[r8*4]\npush rbx\nmov rbx, rdi\nmov rdi, rbp; size\nsub rsp, 8\ncall _malloc\ntest r12d, r12d\njle short loc_1480\nmov rcx, rbx\nlea r8, [rbx+rbp]\nxor edi, edi\nnop dword ptr [rax+rax+00000000h]\nloc_1450:\nmov esi, [rcx]\ntest sil, 1\njnz short loc_1462\nmovsxd r9, edi\nadd edi, 1\nmov [rax+r9*4], esi\nloc_1462:\nadd rcx, 4\ncmp rcx, r8\njnz short loc_1450\nmov [r13+0], edi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1480:\nxor edi, edi\nmov [r13+0], edi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(_DWORD *a1, int a2, _DWORD *a3)\n{\n _DWORD *result; // rax\n _DWORD *v6; // rcx\n int v7; // edi\n __int64 v8; // r9\n\n result = malloc(4LL * a2);\n if ( a2 <= 0 )\n {\n *a3 = 0;\n }\n else\n {\n v6 = a1;\n v7 = 0;\n do\n {\n if ( (*v6 & 1) == 0 )\n {\n v8 = v7++;\n result[v8] = *v6;\n }\n ++v6;\n }\n while ( v6 != &a1[a2] );\n *a3 = v7;\n }\n return result;\n}", + "ida_strip_asm": "sub_1410:\nendbr64\npush r13\nmovsxd r8, esi\nmov r13, rdx\npush r12\nmov r12, r8\npush rbp\nlea rbp, ds:0[r8*4]\npush rbx\nmov rbx, rdi\nmov rdi, rbp; size\nsub rsp, 8\ncall _malloc\ntest r12d, r12d\njle short loc_1480\nmov rcx, rbx\nlea r8, [rbx+rbp]\nxor edi, edi\nnop dword ptr [rax+rax+00000000h]\nloc_1450:\nmov esi, [rcx]\ntest sil, 1\njnz short loc_1462\nmovsxd r9, edi\nadd edi, 1\nmov [rax+r9*4], esi\nloc_1462:\nadd rcx, 4\ncmp rcx, r8\njnz short loc_1450\nmov [r13+0], edi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1480:\nxor edi, edi\nmov [r13+0], edi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1410(_DWORD *a1, int a2, _DWORD *a3)\n{\n _DWORD *result; // rax\n _DWORD *v6; // rcx\n int v7; // edi\n __int64 v8; // r9\n\n result = malloc(4LL * a2);\n if ( a2 <= 0 )\n {\n *a3 = 0;\n }\n else\n {\n v6 = a1;\n v7 = 0;\n do\n {\n if ( (*v6 & 1) == 0 )\n {\n v8 = v7++;\n result[v8] = *v6;\n }\n ++v6;\n }\n while ( v6 != &a1[a2] );\n *a3 = v7;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1410(uint32_t *a1, int a2, uint32_t *a3) {\n uint32_t *result;\n uint32_t *v6;\n int v7;\n long long v8;\n result = malloc(4LL * a2);\n if (a2 <= 0) {\n *a3 = 0;\n } else {\n v6 = a1;\n v7 = 0;\n do {\n if ((*v6 & 1) == 0) {\n v8 = v7++;\n result[v8] = *v6;\n }\n ++v6;\n } while (v6 != &a1[a2]);\n *a3 = v7;\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(uint32_t *a1, int a2, uint32_t *a3) {\n uint32_t *result;\n uint32_t *v6;\n int v7;\n long long v8;\n result = malloc(4LL * a2);\n if (a2 <= 0) {\n *a3 = 0;\n } else {\n v6 = a1;\n v7 = 0;\n do {\n if ((*v6 & 1) == 0) {\n v8 = v7++;\n result[v8] = *v6;\n }\n ++v6;\n } while (v6 != &a1[a2]);\n *a3 = v7;\n }\n return result;\n}" + }, + { + "index": 42, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int sum = 0;\n for (int i = 0; i < n; i++) {\n int count = 1;\n for (int j = 0; j < n; j++) {\n if (arr[j] == arr[i] && j != i) {\n count++;\n }\n }\n if (count > 1) {\n sum += arr[i];\n }\n }\n return sum;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 1, 1, 4, 5, 6};\n\n int arr2[] = {1, 2, 3, 1, 1};\n\n int arr3[] = {1, 1, 2};\n\n int arr4[] = {1, 1, 2, 3, 4, 5, 6, 3, 5};\n\n\n\n assert(func0(arr1, 8) == 3);\n\n assert(func0(arr2, 5) == 3);\n\n assert(func0(arr3, 3) == 2);\n\n assert(func0(arr4, 9) == 18);\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 1223 \nmovl $0x1,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11f8 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 11f4 \nmov -0x4(%rbp),%eax\ncmp -0xc(%rbp),%eax\nje 11f4 \naddl $0x1,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11b8 \ncmpl $0x1,-0x8(%rbp)\njle 121f \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nadd %eax,-0x10(%rbp)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11a8 \nmov -0x10(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp short loc_1223\nloc_11A8:\nmov [rbp+var_8], 1\nmov [rbp+var_4], 0\njmp short loc_11F8\nloc_11B8:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11F4\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_C]\njz short loc_11F4\nadd [rbp+var_8], 1\nloc_11F4:\nadd [rbp+var_4], 1\nloc_11F8:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11B8\ncmp [rbp+var_8], 1\njle short loc_121F\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_10], eax\nloc_121F:\nadd [rbp+var_C], 1\nloc_1223:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl loc_11A8\nmov eax, [rbp+var_10]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+Ch] [rbp-10h]\n int i; // [rsp+10h] [rbp-Ch]\n int v5; // [rsp+14h] [rbp-8h]\n int j; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v5 = 1;\n for ( j = 0; j < a2; ++j )\n {\n if ( *(_DWORD *)(4LL * j + a1) == *(_DWORD *)(4LL * i + a1) && j != i )\n ++v5;\n }\n if ( v5 > 1 )\n v3 += *(_DWORD *)(4LL * i + a1);\n }\n return v3;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp short loc_1223\nloc_11A8:\nmov [rbp+var_8], 1\nmov [rbp+var_4], 0\njmp short loc_11F8\nloc_11B8:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11F4\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_C]\njz short loc_11F4\nadd [rbp+var_8], 1\nloc_11F4:\nadd [rbp+var_4], 1\nloc_11F8:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11B8\ncmp [rbp+var_8], 1\njle short loc_121F\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_10], eax\nloc_121F:\nadd [rbp+var_C], 1\nloc_1223:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl loc_11A8\nmov eax, [rbp+var_10]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+Ch] [rbp-10h]\n int i; // [rsp+10h] [rbp-Ch]\n int v5; // [rsp+14h] [rbp-8h]\n int j; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v5 = 1;\n for ( j = 0; j < a2; ++j )\n {\n if ( *(_DWORD *)(4LL * j + a1) == *(_DWORD *)(4LL * i + a1) && j != i )\n ++v5;\n }\n if ( v5 > 1 )\n v3 += *(_DWORD *)(4LL * i + a1);\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2) {\n unsigned int v3;\n int i;\n int v5;\n int j;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n v5 = 1;\n for (j = 0; j < a2; ++j) {\n if (*(uint32_t *)(4LL * j + a1) == *(uint32_t *)(4LL * i + a1) && j != i)\n ++v5;\n }\n if (v5 > 1) v3 += *(uint32_t *)(4LL * i + a1);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n int v5;\n int j;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n v5 = 1;\n for (j = 0; j < a2; ++j) {\n if (*(uint32_t *)(4LL * j + a1) == *(uint32_t *)(4LL * i + a1) && j != i)\n ++v5;\n }\n if (v5 > 1) v3 += *(uint32_t *)(4LL * i + a1);\n }\n return v3;\n}" + }, + { + "index": 42, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int sum = 0;\n for (int i = 0; i < n; i++) {\n int count = 1;\n for (int j = 0; j < n; j++) {\n if (arr[j] == arr[i] && j != i) {\n count++;\n }\n }\n if (count > 1) {\n sum += arr[i];\n }\n }\n return sum;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 1, 1, 4, 5, 6};\n\n int arr2[] = {1, 2, 3, 1, 1};\n\n int arr3[] = {1, 1, 2};\n\n int arr4[] = {1, 1, 2, 3, 4, 5, 6, 3, 5};\n\n\n\n assert(func0(arr1, 8) == 3);\n\n assert(func0(arr2, 5) == 3);\n\n assert(func0(arr3, 3) == 2);\n\n assert(func0(arr4, 9) == 18);\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11ec \nlea -0x1(%rsi),%r8d\nmov $0x0,%r9d\nmov $0x0,%r10d\nmov $0x0,%r11d\njmp 11de \nlea 0x1(%rax),%rdx\ncmp %r8,%rax\nje 11c8 \nmov %rdx,%rax\ncmp %esi,(%rdi,%rax,4)\njne 11a9 \ncmp %r9d,%eax\nsetne %dl\ncmp $0x1,%dl\nsbb $0xffffffff,%ecx\njmp 11a9 \nadd %r10d,%esi\ncmp $0x1,%ecx\ncmovg %esi,%r10d\nlea 0x1(%r9),%rax\ncmp %r8,%r9\nje 11f2 \nmov %rax,%r9\nmov (%rdi,%r9,4),%esi\nmov %r11,%rax\nmov $0x1,%ecx\njmp 11b5 \nmov $0x0,%r10d\nmov %r10d,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11E3\nmovsxd r8, esi\nmov r9d, 0\nmov r10d, 0\njmp short loc_11D3\nloc_11A2:\nadd rax, 1\ncmp rax, r8\njz short loc_11C0\nloc_11AB:\ncmp [rdi+rax*4], ecx\njnz short loc_11A2\ncmp eax, r9d\nsetnz sil\ncmp sil, 1\nsbb edx, 0FFFFFFFFh\njmp short loc_11A2\nloc_11C0:\nadd ecx, r10d\ncmp edx, 1\ncmovg r10d, ecx\nadd r9, 1\ncmp r9, r8\njz short loc_11E9\nloc_11D3:\nmov ecx, [rdi+r9*4]\nmov eax, 0\nmov edx, 1\njmp short loc_11AB\nloc_11E3:\nmov r10d, 0\nloc_11E9:\nmov eax, r10d\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // r9\n unsigned int v3; // r10d\n __int64 v4; // rax\n int v5; // edx\n unsigned int v6; // ecx\n int v7; // ecx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = 0LL;\n v3 = 0;\n do\n {\n v7 = *(_DWORD *)(a1 + 4 * v2);\n v4 = 0LL;\n v5 = 1;\n do\n {\n if ( *(_DWORD *)(a1 + 4 * v4) == v7 )\n v5 -= ((_DWORD)v4 == (_DWORD)v2) - 1;\n ++v4;\n }\n while ( v4 != a2 );\n v6 = v3 + v7;\n if ( v5 > 1 )\n v3 = v6;\n ++v2;\n }\n while ( v2 != a2 );\n }\n return v3;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\ntest esi, esi\njle short loc_11E3\nmovsxd r8, esi\nmov r9d, 0\nmov r10d, 0\njmp short loc_11D3\nloc_11A2:\nadd rax, 1\ncmp rax, r8\njz short loc_11C0\nloc_11AB:\ncmp [rdi+rax*4], ecx\njnz short loc_11A2\ncmp eax, r9d\nsetnz sil\ncmp sil, 1\nsbb edx, 0FFFFFFFFh\njmp short loc_11A2\nloc_11C0:\nadd ecx, r10d\ncmp edx, 1\ncmovg r10d, ecx\nadd r9, 1\ncmp r9, r8\njz short loc_11E9\nloc_11D3:\nmov ecx, [rdi+r9*4]\nmov eax, 0\nmov edx, 1\njmp short loc_11AB\nloc_11E3:\nmov r10d, 0\nloc_11E9:\nmov eax, r10d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2)\n{\n __int64 v2; // r9\n unsigned int v3; // r10d\n __int64 v4; // rax\n int v5; // edx\n unsigned int v6; // ecx\n int v7; // ecx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = 0LL;\n v3 = 0;\n do\n {\n v7 = *(_DWORD *)(a1 + 4 * v2);\n v4 = 0LL;\n v5 = 1;\n do\n {\n if ( *(_DWORD *)(a1 + 4 * v4) == v7 )\n v5 -= ((_DWORD)v4 == (_DWORD)v2) - 1;\n ++v4;\n }\n while ( v4 != a2 );\n v6 = v3 + v7;\n if ( v5 > 1 )\n v3 = v6;\n ++v2;\n }\n while ( v2 != a2 );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n long long v4;\n int v5;\n unsigned int v6;\n int v7;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = 0LL;\n v3 = 0;\n do {\n v7 = *(uint32_t *)(a1 + 4 * v2);\n v4 = 0LL;\n v5 = 1;\n do {\n if (*(uint32_t *)(a1 + 4 * v4) == v7)\n v5 -= ((uint32_t)v4 == (uint32_t)v2) - 1;\n ++v4;\n } while (v4 != a2);\n v6 = v3 + v7;\n if (v5 > 1) v3 = v6;\n ++v2;\n } while (v2 != a2);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n long long v4;\n int v5;\n unsigned int v6;\n int v7;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = 0LL;\n v3 = 0;\n do {\n v7 = *(uint32_t *)(a1 + 4 * v2);\n v4 = 0LL;\n v5 = 1;\n do {\n if (*(uint32_t *)(a1 + 4 * v4) == v7)\n v5 -= ((uint32_t)v4 == (uint32_t)v2) - 1;\n ++v4;\n } while (v4 != a2);\n v6 = v3 + v7;\n if (v5 > 1) v3 = v6;\n ++v2;\n } while (v2 != a2);\n }\n return v3;\n}" + }, + { + "index": 42, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int sum = 0;\n for (int i = 0; i < n; i++) {\n int count = 1;\n for (int j = 0; j < n; j++) {\n if (arr[j] == arr[i] && j != i) {\n count++;\n }\n }\n if (count > 1) {\n sum += arr[i];\n }\n }\n return sum;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 1, 1, 4, 5, 6};\n\n int arr2[] = {1, 2, 3, 1, 1};\n\n int arr3[] = {1, 1, 2};\n\n int arr4[] = {1, 1, 2, 3, 4, 5, 6, 3, 5};\n\n\n\n assert(func0(arr1, 8) == 3);\n\n assert(func0(arr2, 5) == 3);\n\n assert(func0(arr3, 3) == 2);\n\n assert(func0(arr4, 9) == 18);\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 139d \nlea -0x1(%rsi),%r8d\nxor %r9d,%r9d\nxor %r10d,%r10d\nnopw 0x0(%rax,%rax,1)\nmov (%rdi,%r9,4),%esi\nxor %eax,%eax\nmov $0x1,%ecx\njmp 136b \nnopl (%rax)\nmov %rdx,%rax\ncmp %esi,(%rdi,%rax,4)\njne 137c \ncmp %r9d,%eax\nsetne %dl\ncmp $0x1,%dl\nsbb $0xffffffff,%ecx\nlea 0x1(%rax),%rdx\ncmp %rax,%r8\njne 1368 \nadd %r10d,%esi\ncmp $0x1,%ecx\nlea 0x1(%r9),%rax\ncmovne %esi,%r10d\ncmp %r9,%r8\nje 13a0 \nmov %rax,%r9\njmp 1358 \nxor %r10d,%r10d\nmov %r10d,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_135D\nmovsxd r9, esi\nxor r8d, r8d\nxor r10d, r10d\nnop dword ptr [rax+00000000h]\nloc_1318:\nmov esi, [rdi+r8*4]\nxor eax, eax\nmov ecx, 1\njmp short loc_132B\nloc_1328:\nmov rax, rdx\nloc_132B:\ncmp [rdi+rax*4], esi\njnz short loc_133C\ncmp r8d, eax\nsetnz dl\ncmp dl, 1\nsbb ecx, 0FFFFFFFFh\nloc_133C:\nlea rdx, [rax+1]\ncmp r9, rdx\njnz short loc_1328\nadd esi, r10d\ncmp ecx, 1\nlea rdx, [r8+1]\ncmovg r10d, esi\ncmp rax, r8\njz short loc_1360\nmov r8, rdx\njmp short loc_1318\nloc_135D:\nxor r10d, r10d\nloc_1360:\nmov eax, r10d\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // r9\n __int64 v3; // r8\n unsigned int v4; // r10d\n int v5; // esi\n __int64 v6; // rax\n int v7; // ecx\n unsigned int v8; // esi\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a2;\n v3 = 0LL;\n v4 = 0;\n while ( 1 )\n {\n v5 = *(_DWORD *)(a1 + 4 * v3);\n v6 = 0LL;\n v7 = 1;\n while ( 1 )\n {\n if ( *(_DWORD *)(a1 + 4 * v6) == v5 )\n v7 -= ((_DWORD)v3 == (_DWORD)v6) - 1;\n if ( v2 == v6 + 1 )\n break;\n ++v6;\n }\n v8 = v4 + v5;\n if ( v7 > 1 )\n v4 = v8;\n if ( v6 == v3 )\n break;\n ++v3;\n }\n }\n return v4;\n}", + "ida_strip_asm": "sub_1300:\nendbr64\ntest esi, esi\njle short loc_135D\nmovsxd r9, esi\nxor r8d, r8d\nxor r10d, r10d\nnop dword ptr [rax+00000000h]\nloc_1318:\nmov esi, [rdi+r8*4]\nxor eax, eax\nmov ecx, 1\njmp short loc_132B\nloc_1328:\nmov rax, rdx\nloc_132B:\ncmp [rdi+rax*4], esi\njnz short loc_133C\ncmp r8d, eax\nsetnz dl\ncmp dl, 1\nsbb ecx, 0FFFFFFFFh\nloc_133C:\nlea rdx, [rax+1]\ncmp r9, rdx\njnz short loc_1328\nadd esi, r10d\ncmp ecx, 1\nlea rdx, [r8+1]\ncmovg r10d, esi\ncmp rax, r8\njz short loc_1360\nmov r8, rdx\njmp short loc_1318\nloc_135D:\nxor r10d, r10d\nloc_1360:\nmov eax, r10d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1300(__int64 a1, int a2)\n{\n __int64 v2; // r9\n __int64 v3; // r8\n unsigned int v4; // r10d\n int v5; // esi\n __int64 v6; // rax\n int v7; // ecx\n unsigned int v8; // esi\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a2;\n v3 = 0LL;\n v4 = 0;\n while ( 1 )\n {\n v5 = *(_DWORD *)(a1 + 4 * v3);\n v6 = 0LL;\n v7 = 1;\n while ( 1 )\n {\n if ( *(_DWORD *)(a1 + 4 * v6) == v5 )\n v7 -= ((_DWORD)v3 == (_DWORD)v6) - 1;\n if ( v2 == v6 + 1 )\n break;\n ++v6;\n }\n v8 = v4 + v5;\n if ( v7 > 1 )\n v4 = v8;\n if ( v6 == v3 )\n break;\n ++v3;\n }\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1300(long long a1, int a2) {\n long long v2;\n long long v3;\n unsigned int v4;\n int v5;\n long long v6;\n int v7;\n unsigned int v8;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a2;\n v3 = 0LL;\n v4 = 0;\n while (1) {\n v5 = *(uint32_t *)(a1 + 4 * v3);\n v6 = 0LL;\n v7 = 1;\n while (1) {\n if (*(uint32_t *)(a1 + 4 * v6) == v5)\n v7 -= ((uint32_t)v3 == (uint32_t)v6) - 1;\n if (v2 == v6 + 1) break;\n ++v6;\n }\n v8 = v4 + v5;\n if (v7 > 1) v4 = v8;\n if (v6 == v3) break;\n ++v3;\n }\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n long long v3;\n unsigned int v4;\n int v5;\n long long v6;\n int v7;\n unsigned int v8;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a2;\n v3 = 0LL;\n v4 = 0;\n while (1) {\n v5 = *(uint32_t *)(a1 + 4 * v3);\n v6 = 0LL;\n v7 = 1;\n while (1) {\n if (*(uint32_t *)(a1 + 4 * v6) == v5)\n v7 -= ((uint32_t)v3 == (uint32_t)v6) - 1;\n if (v2 == v6 + 1) break;\n ++v6;\n }\n v8 = v4 + v5;\n if (v7 > 1) v4 = v8;\n if (v6 == v3) break;\n ++v3;\n }\n }\n return v4;\n}" + }, + { + "index": 42, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int sum = 0;\n for (int i = 0; i < n; i++) {\n int count = 1;\n for (int j = 0; j < n; j++) {\n if (arr[j] == arr[i] && j != i) {\n count++;\n }\n }\n if (count > 1) {\n sum += arr[i];\n }\n }\n return sum;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 1, 1, 4, 5, 6};\n\n int arr2[] = {1, 2, 3, 1, 1};\n\n int arr3[] = {1, 1, 2};\n\n int arr4[] = {1, 1, 2, 3, 4, 5, 6, 3, 5};\n\n\n\n assert(func0(arr1, 8) == 3);\n\n assert(func0(arr2, 5) == 3);\n\n assert(func0(arr3, 3) == 2);\n\n assert(func0(arr4, 9) == 18);\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 14ac \nmov %esi,%r8d\npush %r14\nxor %ecx,%ecx\nmov %esi,%r10d\npush %r13\nshr $0x2,%r8d\nmov (%rdi,%rcx,4),%r9d\nand $0xfffffffc,%r10d\npush %r12\nshl $0x4,%r8\nxor %r11d,%r11d\npxor %xmm6,%xmm6\npush %rbp\nlea -0x1(%rsi),%ebp\nmovdqa 0xd83(%rip),%xmm7\nadd %rdi,%r8\npush %rbx\nmov %rbp,%rbx\nmovd %ecx,%xmm4\ncmp $0x3,%ebx\njbe 145f \nnopl 0x0(%rax)\nmovd %r9d,%xmm5\npshufd $0x0,%xmm4,%xmm4\npxor %xmm2,%xmm2\nmov %rdi,%rax\nmovdqa 0xd3f(%rip),%xmm3\npshufd $0x0,%xmm5,%xmm5\nnopw %cs:0x0(%rax,%rax,1)\nmovdqa %xmm3,%xmm1\nmovdqu (%rax),%xmm0\nadd $0x10,%rax\npaddd %xmm7,%xmm3\npcmpeqd %xmm4,%xmm1\npcmpeqd %xmm5,%xmm0\npcmpeqd %xmm6,%xmm1\npand %xmm1,%xmm0\npsubd %xmm0,%xmm2\ncmp %rax,%r8\njne 1390 \nmovdqa %xmm2,%xmm0\nmov %r10d,%edx\npsrldq $0x8,%xmm0\npaddd %xmm0,%xmm2\nmovdqa %xmm2,%xmm0\npsrldq $0x4,%xmm0\npaddd %xmm0,%xmm2\nmovd %xmm2,%eax\nadd $0x1,%eax\ncmp %r10d,%esi\nje 143a \nmovslq %edx,%r14\nmov %ecx,%r13d\nlea 0x0(,%r14,4),%r12\ncmp %r9d,(%rdi,%r14,4)\njne 13fa \ncmp %ecx,%edx\njne 1470 \nadd $0x1,%edx\ncmp %esi,%edx\njge 143a \ncmp %r9d,0x4(%rdi,%r12,1)\njne 140d \ncmp %edx,%r13d\njne 1480 \nadd $0x1,%edx\ncmp %edx,%esi\njle 143a \ncmp %r9d,0x8(%rdi,%r12,1)\njne 1420 \ncmp %edx,%r13d\njne 1490 \nadd $0x1,%edx\ncmp %edx,%esi\njle 143a \ncmp %r9d,0xc(%rdi,%r12,1)\njne 143a \ncmp %edx,%r13d\nsetne %dl\ncmp $0x1,%dl\nsbb $0xffffffff,%eax\ncmp $0x1,%eax\nje 1442 \nadd %r9d,%r11d\nlea 0x1(%rcx),%rax\ncmp %rbp,%rcx\nje 14a0 \nmov %rax,%rcx\nmov (%rdi,%rcx,4),%r9d\nmovd %ecx,%xmm4\ncmp $0x3,%ebx\nja 1368 \nxor %edx,%edx\nmov $0x1,%eax\njmpq 13e2 \nnopl 0x0(%rax,%rax,1)\nadd $0x1,%edx\nadd $0x1,%eax\ncmp %edx,%esi\njg 1401 \njmp 143f \nnopl 0x0(%rax)\nadd $0x1,%edx\nadd $0x1,%eax\ncmp %edx,%esi\njg 1414 \njmp 143f \nnopl 0x0(%rax)\nadd $0x1,%edx\nadd $0x1,%eax\ncmp %esi,%edx\njl 1427 \njmp 143f \nnopl 0x0(%rax)\npop %rbx\nmov %r11d,%eax\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nxor %r11d,%r11d\nmov %r11d,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle loc_145C\nmov ecx, esi\npush r14\nmovdqa xmm7, cs:xmmword_20B0\nmov r9d, esi\nshr ecx, 2\npush r13\nmov r8, rdi\nxor r10d, r10d\npush r12\nshl rcx, 4\nmovsxd r12, esi\npxor xmm6, xmm6\npush rbp\nadd rcx, rdi\nlea ebp, [rsi-1]\npush rbx\nmov ebx, esi\nxor esi, esi\nand ebx, 0FFFFFFFCh\nnop word ptr [rax+rax+00h]\nloc_1348:\nmov edx, [r8+rsi*4]\ncmp ebp, 2\njbe loc_1450\nmovd xmm4, esi\nmovdqa xmm3, cs:xmmword_20A0\nmov rax, r8\npxor xmm2, xmm2\npshufd xmm5, xmm4, 0\nmovd xmm4, edx\npshufd xmm4, xmm4, 0\nnop word ptr [rax+rax+00000000h]\nloc_1380:\nmovdqa xmm1, xmm3\nmovdqu xmm0, xmmword ptr [rax]\nadd rax, 10h\npaddd xmm3, xmm7\npcmpeqd xmm1, xmm5\npcmpeqd xmm0, xmm4\npcmpeqd xmm1, xmm6\npand xmm0, xmm1\npsubd xmm2, xmm0\ncmp rax, rcx\njnz short loc_1380\nmovdqa xmm0, xmm2\nmov edi, ebx\npsrldq xmm0, 8\npaddd xmm2, xmm0\nmovdqa xmm0, xmm2\npsrldq xmm0, 4\npaddd xmm2, xmm0\nmovd eax, xmm2\nadd eax, 1\ncmp r9d, ebx\njz short loc_142D\nloc_13D1:\nmovsxd r11, edi\nmov r14d, esi\nlea r13, ds:0[r11*4]\ncmp [r8+r11*4], edx\njnz short loc_13F2\ncmp esi, edi\nsetnz r11b\ncmp r11b, 1\nsbb eax, 0FFFFFFFFh\nloc_13F2:\nlea r11d, [rdi+1]\ncmp r9d, r11d\njle short loc_142D\ncmp [r8+r13+4], edx\njnz short loc_1410\ncmp r11d, r14d\nsetnz r11b\ncmp r11b, 1\nsbb eax, 0FFFFFFFFh\nloc_1410:\nadd edi, 2\ncmp edi, r9d\njge short loc_142D\ncmp [r8+r13+8], edx\njnz short loc_142D\ncmp edi, r14d\nsetnz dil\ncmp dil, 1\nsbb eax, 0FFFFFFFFh\nloc_142D:\nadd edx, r10d\ncmp eax, 1\ncmovg r10d, edx\nadd rsi, 1\ncmp rsi, r12\njnz loc_1348\npop rbx\nmov eax, r10d\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1450:\nxor edi, edi\nmov eax, 1\njmp loc_13D1\nloc_145C:\nxor eax, eax\nretn", + "ida_pseudo": "__int64 __fastcall func0(const __m128i *a1, int a2)\n{\n __m128i si128; // xmm7\n unsigned int v5; // r10d\n __int64 v6; // r12\n const __m128i *v7; // rcx\n unsigned int v8; // ebp\n __int64 v10; // rsi\n unsigned int v11; // ebx\n unsigned int v12; // edx\n __m128i v13; // xmm3\n const __m128i *v14; // rax\n __m128i v15; // xmm2\n __m128i v16; // xmm5\n __m128i v17; // xmm4\n __m128i v18; // xmm1\n __m128i v19; // xmm0\n signed int v20; // edi\n __m128i v21; // xmm2\n int v22; // eax\n __int64 v23; // r13\n int v24; // edi\n unsigned int v25; // edx\n\n if ( a2 > 0 )\n {\n si128 = _mm_load_si128((const __m128i *)&xmmword_20B0);\n v5 = 0;\n v6 = a2;\n v7 = &a1[(unsigned int)a2 >> 2];\n v8 = a2 - 1;\n v10 = 0LL;\n v11 = a2 & 0xFFFFFFFC;\n while ( 1 )\n {\n v12 = a1->m128i_u32[v10];\n if ( v8 <= 2 )\n break;\n v13 = _mm_load_si128((const __m128i *)&xmmword_20A0);\n v14 = a1;\n v15 = 0LL;\n v16 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v10), 0);\n v17 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v12), 0);\n do\n {\n v18 = v13;\n v19 = _mm_loadu_si128(v14++);\n v13 = _mm_add_epi32(v13, si128);\n v15 = _mm_sub_epi32(\n v15,\n _mm_and_si128(_mm_cmpeq_epi32(v19, v17), _mm_cmpeq_epi32(_mm_cmpeq_epi32(v18, v16), (__m128i)0LL)));\n }\n while ( v14 != v7 );\n v20 = v11;\n v21 = _mm_add_epi32(v15, _mm_srli_si128(v15, 8));\n v22 = _mm_cvtsi128_si32(_mm_add_epi32(v21, _mm_srli_si128(v21, 4))) + 1;\n if ( a2 != v11 )\n goto LABEL_7;\nLABEL_15:\n v25 = v5 + v12;\n if ( v22 > 1 )\n v5 = v25;\n if ( ++v10 == v6 )\n return v5;\n }\n v20 = 0;\n v22 = 1;\nLABEL_7:\n v23 = v20;\n if ( a1->m128i_i32[v23] == v12 )\n v22 -= ((_DWORD)v10 == v20) - 1;\n if ( a2 > v20 + 1 )\n {\n if ( a1->m128i_i32[v23 + 1] == v12 )\n v22 -= (v20 + 1 == (_DWORD)v10) - 1;\n v24 = v20 + 2;\n if ( v24 < a2 && a1->m128i_i32[v23 + 2] == v12 )\n v22 -= (v24 == (_DWORD)v10) - 1;\n }\n goto LABEL_15;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1300:\nendbr64\ntest esi, esi\njle loc_145C\nmov ecx, esi\npush r14\nmovdqa xmm7, cs:xmmword_20B0\nmov r9d, esi\nshr ecx, 2\npush r13\nmov r8, rdi\nxor r10d, r10d\npush r12\nshl rcx, 4\nmovsxd r12, esi\npxor xmm6, xmm6\npush rbp\nadd rcx, rdi\nlea ebp, [rsi-1]\npush rbx\nmov ebx, esi\nxor esi, esi\nand ebx, 0FFFFFFFCh\nnop word ptr [rax+rax+00h]\nloc_1348:\nmov edx, [r8+rsi*4]\ncmp ebp, 2\njbe loc_1450\nmovd xmm4, esi\nmovdqa xmm3, cs:xmmword_20A0\nmov rax, r8\npxor xmm2, xmm2\npshufd xmm5, xmm4, 0\nmovd xmm4, edx\npshufd xmm4, xmm4, 0\nnop word ptr [rax+rax+00000000h]\nloc_1380:\nmovdqa xmm1, xmm3\nmovdqu xmm0, xmmword ptr [rax]\nadd rax, 10h\npaddd xmm3, xmm7\npcmpeqd xmm1, xmm5\npcmpeqd xmm0, xmm4\npcmpeqd xmm1, xmm6\npand xmm0, xmm1\npsubd xmm2, xmm0\ncmp rax, rcx\njnz short loc_1380\nmovdqa xmm0, xmm2\nmov edi, ebx\npsrldq xmm0, 8\npaddd xmm2, xmm0\nmovdqa xmm0, xmm2\npsrldq xmm0, 4\npaddd xmm2, xmm0\nmovd eax, xmm2\nadd eax, 1\ncmp r9d, ebx\njz short loc_142D\nloc_13D1:\nmovsxd r11, edi\nmov r14d, esi\nlea r13, ds:0[r11*4]\ncmp [r8+r11*4], edx\njnz short loc_13F2\ncmp esi, edi\nsetnz r11b\ncmp r11b, 1\nsbb eax, 0FFFFFFFFh\nloc_13F2:\nlea r11d, [rdi+1]\ncmp r9d, r11d\njle short loc_142D\ncmp [r8+r13+4], edx\njnz short loc_1410\ncmp r11d, r14d\nsetnz r11b\ncmp r11b, 1\nsbb eax, 0FFFFFFFFh\nloc_1410:\nadd edi, 2\ncmp edi, r9d\njge short loc_142D\ncmp [r8+r13+8], edx\njnz short loc_142D\ncmp edi, r14d\nsetnz dil\ncmp dil, 1\nsbb eax, 0FFFFFFFFh\nloc_142D:\nadd edx, r10d\ncmp eax, 1\ncmovg r10d, edx\nadd rsi, 1\ncmp rsi, r12\njnz loc_1348\npop rbx\nmov eax, r10d\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1450:\nxor edi, edi\nmov eax, 1\njmp loc_13D1\nloc_145C:\nxor eax, eax\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1300(const __m128i *a1, int a2)\n{\n __m128i si128; // xmm7\n unsigned int v5; // r10d\n __int64 v6; // r12\n const __m128i *v7; // rcx\n unsigned int v8; // ebp\n __int64 v10; // rsi\n unsigned int v11; // ebx\n unsigned int v12; // edx\n __m128i v13; // xmm3\n const __m128i *v14; // rax\n __m128i v15; // xmm2\n __m128i v16; // xmm5\n __m128i v17; // xmm4\n __m128i v18; // xmm1\n __m128i v19; // xmm0\n signed int v20; // edi\n __m128i v21; // xmm2\n int v22; // eax\n __int64 v23; // r13\n int v24; // edi\n unsigned int v25; // edx\n\n if ( a2 > 0 )\n {\n si128 = _mm_load_si128((const __m128i *)&xmmword_20B0);\n v5 = 0;\n v6 = a2;\n v7 = &a1[(unsigned int)a2 >> 2];\n v8 = a2 - 1;\n v10 = 0LL;\n v11 = a2 & 0xFFFFFFFC;\n while ( 1 )\n {\n v12 = a1->m128i_u32[v10];\n if ( v8 <= 2 )\n break;\n v13 = _mm_load_si128((const __m128i *)&xmmword_20A0);\n v14 = a1;\n v15 = 0LL;\n v16 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v10), 0);\n v17 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v12), 0);\n do\n {\n v18 = v13;\n v19 = _mm_loadu_si128(v14++);\n v13 = _mm_add_epi32(v13, si128);\n v15 = _mm_sub_epi32(\n v15,\n _mm_and_si128(_mm_cmpeq_epi32(v19, v17), _mm_cmpeq_epi32(_mm_cmpeq_epi32(v18, v16), (__m128i)0LL)));\n }\n while ( v14 != v7 );\n v20 = v11;\n v21 = _mm_add_epi32(v15, _mm_srli_si128(v15, 8));\n v22 = _mm_cvtsi128_si32(_mm_add_epi32(v21, _mm_srli_si128(v21, 4))) + 1;\n if ( a2 != v11 )\n goto LABEL_7;\nLABEL_15:\n v25 = v5 + v12;\n if ( v22 > 1 )\n v5 = v25;\n if ( ++v10 == v6 )\n return v5;\n }\n v20 = 0;\n v22 = 1;\nLABEL_7:\n v23 = v20;\n if ( a1->m128i_i32[v23] == v12 )\n v22 -= ((_DWORD)v10 == v20) - 1;\n if ( a2 > v20 + 1 )\n {\n if ( a1->m128i_i32[v23 + 1] == v12 )\n v22 -= (v20 + 1 == (_DWORD)v10) - 1;\n v24 = v20 + 2;\n if ( v24 < a2 && a1->m128i_i32[v23 + 2] == v12 )\n v22 -= (v24 == (_DWORD)v10) - 1;\n }\n goto LABEL_15;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1300(const __m128i *a1, int a2) {\n __m128i si128;\n unsigned int v5;\n long long v6;\n const __m128i *v7;\n unsigned int v8;\n long long v10;\n unsigned int v11;\n unsigned int v12;\n __m128i v13;\n const __m128i *v14;\n __m128i v15;\n __m128i v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n signed int v20;\n __m128i v21;\n int v22;\n long long v23;\n int v24;\n unsigned int v25;\n if (a2 > 0) {\n si128 = _mm_load_si128((const __m128i *)&xmmword_20B0);\n v5 = 0;\n v6 = a2;\n v7 = &a1[(unsigned int)a2 >> 2];\n v8 = a2 - 1;\n v10 = 0LL;\n v11 = a2 & 4294967292;\n while (1) {\n v12 = a1->m128i_u32[v10];\n if (v8 <= 2) break;\n v13 = _mm_load_si128((const __m128i *)&xmmword_20A0);\n v14 = a1;\n v15 = 0LL;\n v16 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v10), 0);\n v17 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v12), 0);\n do {\n v18 = v13;\n v19 = _mm_loadu_si128(v14++);\n v13 = _mm_add_epi32(v13, si128);\n v15 = _mm_sub_epi32(\n v15, _mm_and_si128(\n _mm_cmpeq_epi32(v19, v17),\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(v18, v16), (__m128i)0LL)));\n } while (v14 != v7);\n v20 = v11;\n v21 = _mm_add_epi32(v15, _mm_srli_si128(v15, 8));\n v22 = _mm_cvtsi128_si32(_mm_add_epi32(v21, _mm_srli_si128(v21, 4))) + 1;\n if (a2 != v11) goto LABEL_7;\n LABEL_15:\n v25 = v5 + v12;\n if (v22 > 1) v5 = v25;\n if (++v10 == v6) return v5;\n }\n v20 = 0;\n v22 = 1;\n LABEL_7:\n v23 = v20;\n if (a1->m128i_i32[v23] == v12) v22 -= ((uint32_t)v10 == v20) - 1;\n if (a2 > v20 + 1) {\n if (a1->m128i_i32[v23 + 1] == v12) v22 -= (v20 + 1 == (uint32_t)v10) - 1;\n v24 = v20 + 2;\n if (v24 < a2 && a1->m128i_i32[v23 + 2] == v12)\n v22 -= (v24 == (uint32_t)v10) - 1;\n }\n goto LABEL_15;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(const __m128i *a1, int a2) {\n __m128i si128;\n unsigned int v5;\n long long v6;\n const __m128i *v7;\n unsigned int v8;\n long long v10;\n unsigned int v11;\n unsigned int v12;\n __m128i v13;\n const __m128i *v14;\n __m128i v15;\n __m128i v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n signed int v20;\n __m128i v21;\n int v22;\n long long v23;\n int v24;\n unsigned int v25;\n if (a2 > 0) {\n si128 = _mm_load_si128((const __m128i *)&xmmword_20B0);\n v5 = 0;\n v6 = a2;\n v7 = &a1[(unsigned int)a2 >> 2];\n v8 = a2 - 1;\n v10 = 0LL;\n v11 = a2 & 4294967292;\n while (1) {\n v12 = a1->m128i_u32[v10];\n if (v8 <= 2) break;\n v13 = _mm_load_si128((const __m128i *)&xmmword_20A0);\n v14 = a1;\n v15 = 0LL;\n v16 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v10), 0);\n v17 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v12), 0);\n do {\n v18 = v13;\n v19 = _mm_loadu_si128(v14++);\n v13 = _mm_add_epi32(v13, si128);\n v15 = _mm_sub_epi32(\n v15, _mm_and_si128(\n _mm_cmpeq_epi32(v19, v17),\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(v18, v16), (__m128i)0LL)));\n } while (v14 != v7);\n v20 = v11;\n v21 = _mm_add_epi32(v15, _mm_srli_si128(v15, 8));\n v22 = _mm_cvtsi128_si32(_mm_add_epi32(v21, _mm_srli_si128(v21, 4))) + 1;\n if (a2 != v11) goto LABEL_7;\n LABEL_15:\n v25 = v5 + v12;\n if (v22 > 1) v5 = v25;\n if (++v10 == v6) return v5;\n }\n v20 = 0;\n v22 = 1;\n LABEL_7:\n v23 = v20;\n if (a1->m128i_i32[v23] == v12) v22 -= ((uint32_t)v10 == v20) - 1;\n if (a2 > v20 + 1) {\n if (a1->m128i_i32[v23 + 1] == v12) v22 -= (v20 + 1 == (uint32_t)v10) - 1;\n v24 = v20 + 2;\n if (v24 < a2 && a1->m128i_i32[v23 + 2] == v12)\n v22 -= (v24 == (uint32_t)v10) - 1;\n }\n goto LABEL_15;\n }\n return 0LL;\n}" + }, + { + "index": 43, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char *func0(const char *text) {\n regex_t regex;\n int regexInit;\n int regexSearch;\n char *patterns = \"^[a-z]+_[a-z]+$\";\n regexInit = regcomp(®ex, patterns, REG_EXTENDED);\n if (regexInit) {\n fprintf(stderr, \"Could not compile regex\\n\");\n return (\"Compilation error\");\n }\n regexSearch = regexec(®ex, text, 0, NULL, 0);\n if (!regexSearch) {\n regfree(®ex);\n return (\"Found a match!\");\n } else if (regexSearch == REG_NOMATCH) {\n regfree(®ex);\n return (\"Not matched!\");\n } else {\n char errorMessage[100];\n regerror(regexSearch, ®ex, errorMessage, sizeof(errorMessage));\n fprintf(stderr, \"Regex match failed: %s\\n\", errorMessage);\n regfree(®ex);\n return (\"Error occurred\");\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"aab_cbbbc\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\"aab_Abbbc\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"Aaab_abbbc\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"aab-cbbbc\"), \"Not matched!\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0xd0,%rsp\nmov %rdi,-0xc8(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0xd93(%rip),%rax\nmov %rax,-0xb8(%rbp)\nmov -0xb8(%rbp),%rcx\nlea -0xb0(%rbp),%rax\nmov $0x1,%edx\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 1100 \nmov %eax,-0xc0(%rbp)\ncmpl $0x0,-0xc0(%rbp)\nje 12d5 \nmov 0x2d70(%rip),%rax\nmov %rax,%rcx\nmov $0x18,%edx\nmov $0x1,%esi\nlea 0xd54(%rip),%rdi\ncallq 1150 \nlea 0xd61(%rip),%rax\njmpq 1395 \nmov -0xc8(%rbp),%rsi\nlea -0xb0(%rbp),%rax\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rax,%rdi\ncallq 1140 \nmov %eax,-0xbc(%rbp)\ncmpl $0x0,-0xbc(%rbp)\njne 1322 \nlea -0xb0(%rbp),%rax\nmov %rax,%rdi\ncallq 10d0 \nlea 0xd23(%rip),%rax\njmp 1395 \ncmpl $0x1,-0xbc(%rbp)\njne 1343 \nlea -0xb0(%rbp),%rax\nmov %rax,%rdi\ncallq 10d0 \nlea 0xd11(%rip),%rax\njmp 1395 \nlea -0x70(%rbp),%rdx\nlea -0xb0(%rbp),%rsi\nmov -0xbc(%rbp),%eax\nmov $0x64,%ecx\nmov %eax,%edi\ncallq 1130 \nmov 0x2cb9(%rip),%rax\nlea -0x70(%rbp),%rdx\nlea 0xced(%rip),%rsi\nmov %rax,%rdi\nmov $0x0,%eax\ncallq 1120 \nlea -0xb0(%rbp),%rax\nmov %rax,%rdi\ncallq 10d0 \nlea 0xce2(%rip),%rax\nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 13a9 \ncallq 10e0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0D0h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aAZAZ; \"^[a-z]+_[a-z]+$\"\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+var_C0], eax\ncmp [rbp+var_C0], 0\njz short loc_12D8\nmov rax, cs:__bss_start\nmov rcx, rax; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rax, aCouldNotCompil; \"Could not compile regex\\n\"\nmov rdi, rax; ptr\ncall _fwrite\nlea rax, aCompilationErr; \"Compilation error\"\njmp loc_139B\nloc_12D8:\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+errcode], eax\ncmp [rbp+errcode], 0\njnz short loc_1325\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nlea rax, s2; \"Found a match!\"\njmp short loc_139B\nloc_1325:\ncmp [rbp+errcode], 1\njnz short loc_1346\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nlea rax, aNotMatched; \"Not matched!\"\njmp short loc_139B\nloc_1346:\nlea rdx, [rbp+errbuf]; errbuf\nlea rsi, [rbp+preg]; preg\nmov eax, [rbp+errcode]\nmov ecx, 64h ; 'd'; errbuf_size\nmov edi, eax; errcode\ncall _regerror\nmov rax, cs:__bss_start\nlea rdx, [rbp+errbuf]\nlea rcx, format; \"Regex match failed: %s\\n\"\nmov rsi, rcx; format\nmov rdi, rax; stream\nmov eax, 0\ncall _fprintf\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nlea rax, aErrorOccurred; \"Error occurred\"\nloc_139B:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_13AF\ncall ___stack_chk_fail\nlocret_13AF:\nleave\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n int errcode; // [rsp+14h] [rbp-BCh]\n regex_t preg; // [rsp+20h] [rbp-B0h] BYREF\n char errbuf[104]; // [rsp+60h] [rbp-70h] BYREF\n unsigned __int64 v5; // [rsp+C8h] [rbp-8h]\n\n v5 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"^[a-z]+_[a-z]+$\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n return \"Compilation error\";\n }\n else\n {\n errcode = regexec(&preg, a1, 0LL, 0LL, 0);\n if ( errcode )\n {\n if ( errcode == 1 )\n {\n regfree(&preg);\n return \"Not matched!\";\n }\n else\n {\n regerror(errcode, &preg, errbuf, 0x64uLL);\n fprintf(_bss_start, \"Regex match failed: %s\\n\", errbuf);\n regfree(&preg);\n return \"Error occurred\";\n }\n }\n else\n {\n regfree(&preg);\n return \"Found a match!\";\n }\n }\n}", + "ida_strip_asm": "sub_1249:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0D0h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aAZAZ; \"^[a-z]+_[a-z]+$\"\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+var_C0], eax\ncmp [rbp+var_C0], 0\njz short loc_12D8\nmov rax, cs:stderr\nmov rcx, rax; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rax, aCouldNotCompil; \"Could not compile regex\\n\"\nmov rdi, rax; ptr\ncall _fwrite\nlea rax, aCompilationErr; \"Compilation error\"\njmp loc_139B\nloc_12D8:\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+errcode], eax\ncmp [rbp+errcode], 0\njnz short loc_1325\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nlea rax, s2; \"Found a match!\"\njmp short loc_139B\nloc_1325:\ncmp [rbp+errcode], 1\njnz short loc_1346\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nlea rax, aNotMatched; \"Not matched!\"\njmp short loc_139B\nloc_1346:\nlea rdx, [rbp+errbuf]; errbuf\nlea rsi, [rbp+preg]; preg\nmov eax, [rbp+errcode]\nmov ecx, 64h ; 'd'; errbuf_size\nmov edi, eax; errcode\ncall _regerror\nmov rax, cs:stderr\nlea rdx, [rbp+errbuf]\nlea rcx, format; \"Regex match failed: %s\\n\"\nmov rsi, rcx; format\nmov rdi, rax; stream\nmov eax, 0\ncall _fprintf\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nlea rax, aErrorOccurred; \"Error occurred\"\nloc_139B:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_13AF\ncall ___stack_chk_fail\nlocret_13AF:\nleave\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1249(const char *a1)\n{\n int errcode; // [rsp+14h] [rbp-BCh]\n regex_t preg; // [rsp+20h] [rbp-B0h] BYREF\n char errbuf[104]; // [rsp+60h] [rbp-70h] BYREF\n unsigned __int64 v5; // [rsp+C8h] [rbp-8h]\n\n v5 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"^[a-z]+_[a-z]+$\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n return \"Compilation error\";\n }\n else\n {\n errcode = regexec(&preg, a1, 0LL, 0LL, 0);\n if ( errcode )\n {\n if ( errcode == 1 )\n {\n regfree(&preg);\n return \"Not matched!\";\n }\n else\n {\n regerror(errcode, &preg, errbuf, 0x64uLL);\n fprintf(stderr, \"Regex match failed: %s\\n\", errbuf);\n regfree(&preg);\n return \"Error occurred\";\n }\n }\n else\n {\n regfree(&preg);\n return \"Found a match!\";\n }\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1249(const char *a1) {\n int errcode;\n regex_t preg;\n char errbuf[104];\n unsigned long long v5;\n v5 = __readfsqword(40u);\n if (regcomp(&preg, \"^[a-z]+_[a-z]+$\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n return \"Compilation error\";\n } else {\n errcode = regexec(&preg, a1, 0LL, 0LL, 0);\n if (errcode) {\n if (errcode == 1) {\n regfree(&preg);\n return \"Not matched!\";\n } else {\n regerror(errcode, &preg, errbuf, 100uLL);\n fprintf(stderr, \"Regex match failed: %s\\n\", errbuf);\n regfree(&preg);\n return \"Error occurred\";\n }\n } else {\n regfree(&preg);\n return \"Found a match!\";\n }\n }\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n int errcode;\n regex_t preg;\n char errbuf[104];\n unsigned long long v5;\n v5 = __readfsqword(40u);\n if (regcomp(&preg, \"^[a-z]+_[a-z]+$\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n return \"Compilation error\";\n } else {\n errcode = regexec(&preg, a1, 0LL, 0LL, 0);\n if (errcode) {\n if (errcode == 1) {\n regfree(&preg);\n return \"Not matched!\";\n } else {\n regerror(errcode, &preg, errbuf, 100uLL);\n fprintf(_bss_start, \"Regex match failed: %s\\n\", errbuf);\n regfree(&preg);\n return \"Error occurred\";\n }\n } else {\n regfree(&preg);\n return \"Found a match!\";\n }\n }\n}" + }, + { + "index": 43, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char *func0(const char *text) {\n regex_t regex;\n int regexInit;\n int regexSearch;\n char *patterns = \"^[a-z]+_[a-z]+$\";\n regexInit = regcomp(®ex, patterns, REG_EXTENDED);\n if (regexInit) {\n fprintf(stderr, \"Could not compile regex\\n\");\n return (\"Compilation error\");\n }\n regexSearch = regexec(®ex, text, 0, NULL, 0);\n if (!regexSearch) {\n regfree(®ex);\n return (\"Found a match!\");\n } else if (regexSearch == REG_NOMATCH) {\n regfree(®ex);\n return (\"Not matched!\");\n } else {\n char errorMessage[100];\n regerror(regexSearch, ®ex, errorMessage, sizeof(errorMessage));\n fprintf(stderr, \"Regex match failed: %s\\n\", errorMessage);\n regfree(®ex);\n return (\"Error occurred\");\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"aab_cbbbc\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\"aab_Abbbc\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"Aaab_abbbc\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"aab-cbbbc\"), \"Not matched!\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0xb8,%rsp\nmov %rdi,%rbx\nmov %fs:0x28,%rax\nmov %rax,0xa8(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nmov $0x1,%edx\nlea 0xde6(%rip),%rsi\ncallq 10f0 \ntest %eax,%eax\njne 12fa \nmov %rsp,%rdi\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rbx,%rsi\ncallq 1110 \ntest %eax,%eax\nje 1320 \ncmp $0x1,%eax\nje 1331 \nlea 0x40(%rsp),%rbp\nmov %rsp,%rbx\nmov $0x64,%ecx\nmov %rbp,%rdx\nmov %rbx,%rsi\nmov %eax,%edi\ncallq 1100 \nmov %rbp,%rcx\nlea 0xdb2(%rip),%rdx\nmov $0x1,%esi\nmov 0x2d5c(%rip),%rdi\nmov $0x0,%eax\ncallq 1130 <__fprintf_chk@plt>\nmov %rbx,%rdi\ncallq 10c0 \nlea 0xd55(%rip),%rax\nmov 0xa8(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 1342 \nadd $0xb8,%rsp\npop %rbx\npop %rbp\nretq\nmov 0x2d1f(%rip),%rcx\nmov $0x18,%edx\nmov $0x1,%esi\nlea 0xd3f(%rip),%rdi\ncallq 1120 \nlea 0xce6(%rip),%rax\njmp 12dd \nmov %rsp,%rdi\ncallq 10c0 \nlea 0xce7(%rip),%rax\njmp 12dd \nmov %rsp,%rdi\ncallq 10c0 \nlea 0xce5(%rip),%rax\njmp 12dd \ncallq 10d0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 0B8h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+0C8h+var_20], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"^[a-z]+_[a-z]+$\"\ncall _regcomp\ntest eax, eax\njnz loc_131A\nmov rdi, rsp; preg\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\ncall _regexec\ntest eax, eax\njz loc_1340\ncmp eax, 1\njz loc_1351\nlea rbp, [rsp+0C8h+errbuf]\nmov rbx, rsp\nmov ecx, 64h ; 'd'; errbuf_size\nmov rdx, rbp; errbuf\nmov rsi, rbx; preg\nmov edi, eax; errcode\ncall _regerror\nmov rcx, rbp\nlea rdx, aRegexMatchFail; \"Regex match failed: %s\\n\"\nmov esi, 2\nmov rdi, cs:__bss_start\nmov eax, 0\ncall ___fprintf_chk\nmov rdi, rbx; preg\ncall _regfree\nlea rax, aErrorOccurred; \"Error occurred\"\nloc_12FD:\nmov rdx, [rsp+0C8h+var_20]\nsub rdx, fs:28h\njnz short loc_1362\nadd rsp, 0B8h\npop rbx\npop rbp\nretn\nloc_131A:\nmov rcx, cs:__bss_start; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nlea rax, aCompilationErr; \"Compilation error\"\njmp short loc_12FD\nloc_1340:\nmov rdi, rsp; preg\ncall _regfree\nlea rax, s2; \"Found a match!\"\njmp short loc_12FD\nloc_1351:\nmov rdi, rsp; preg\ncall _regfree\nlea rax, aNotMatched; \"Not matched!\"\njmp short loc_12FD\nloc_1362:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // eax\n regex_t v3; // [rsp+0h] [rbp-C8h] BYREF\n char errbuf[104]; // [rsp+40h] [rbp-88h] BYREF\n unsigned __int64 v5; // [rsp+A8h] [rbp-20h]\n\n v5 = __readfsqword(0x28u);\n if ( regcomp(&v3, \"^[a-z]+_[a-z]+$\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n return \"Compilation error\";\n }\n else\n {\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n if ( v1 )\n {\n if ( v1 == 1 )\n {\n regfree(&v3);\n return \"Not matched!\";\n }\n else\n {\n regerror(v1, &v3, errbuf, 0x64uLL);\n __fprintf_chk(_bss_start, 2LL, \"Regex match failed: %s\\n\", errbuf);\n regfree(&v3);\n return \"Error occurred\";\n }\n }\n else\n {\n regfree(&v3);\n return \"Found a match!\";\n }\n }\n}", + "ida_strip_asm": "sub_1249:\nendbr64\npush rbp\npush rbx\nsub rsp, 0B8h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+0C8h+var_20], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"^[a-z]+_[a-z]+$\"\ncall _regcomp\ntest eax, eax\njnz loc_131A\nmov rdi, rsp; preg\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\ncall _regexec\ntest eax, eax\njz loc_1340\ncmp eax, 1\njz loc_1351\nlea rbp, [rsp+0C8h+errbuf]\nmov rbx, rsp\nmov ecx, 64h ; 'd'; errbuf_size\nmov rdx, rbp; errbuf\nmov rsi, rbx; preg\nmov edi, eax; errcode\ncall _regerror\nmov rcx, rbp\nlea rdx, aRegexMatchFail; \"Regex match failed: %s\\n\"\nmov esi, 2\nmov rdi, cs:stderr\nmov eax, 0\ncall ___fprintf_chk\nmov rdi, rbx; preg\ncall _regfree\nlea rax, aErrorOccurred; \"Error occurred\"\nloc_12FD:\nmov rdx, [rsp+0C8h+var_20]\nsub rdx, fs:28h\njnz short loc_1362\nadd rsp, 0B8h\npop rbx\npop rbp\nretn\nloc_131A:\nmov rcx, cs:stderr; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nlea rax, aCompilationErr; \"Compilation error\"\njmp short loc_12FD\nloc_1340:\nmov rdi, rsp; preg\ncall _regfree\nlea rax, s2; \"Found a match!\"\njmp short loc_12FD\nloc_1351:\nmov rdi, rsp; preg\ncall _regfree\nlea rax, aNotMatched; \"Not matched!\"\njmp short loc_12FD\nloc_1362:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_1249(char *string)\n{\n int v1; // eax\n regex_t v3; // [rsp+0h] [rbp-C8h] BYREF\n char errbuf[104]; // [rsp+40h] [rbp-88h] BYREF\n unsigned __int64 v5; // [rsp+A8h] [rbp-20h]\n\n v5 = __readfsqword(0x28u);\n if ( regcomp(&v3, \"^[a-z]+_[a-z]+$\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n return \"Compilation error\";\n }\n else\n {\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n if ( v1 )\n {\n if ( v1 == 1 )\n {\n regfree(&v3);\n return \"Not matched!\";\n }\n else\n {\n regerror(v1, &v3, errbuf, 0x64uLL);\n __fprintf_chk(stderr, 2LL, \"Regex match failed: %s\\n\", errbuf);\n regfree(&v3);\n return \"Error occurred\";\n }\n }\n else\n {\n regfree(&v3);\n return \"Found a match!\";\n }\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1249(char *string) {\n int v1;\n regex_t v3;\n char errbuf[104];\n unsigned long long v5;\n v5 = __readfsqword(40u);\n if (regcomp(&v3, \"^[a-z]+_[a-z]+$\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n return \"Compilation error\";\n } else {\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n if (v1) {\n if (v1 == 1) {\n regfree(&v3);\n return \"Not matched!\";\n } else {\n regerror(v1, &v3, errbuf, 100uLL);\n __fprintf_chk(stderr, 2LL, \"Regex match failed: %s\\n\", errbuf);\n regfree(&v3);\n return \"Error occurred\";\n }\n } else {\n regfree(&v3);\n return \"Found a match!\";\n }\n }\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n regex_t v3;\n char errbuf[104];\n unsigned long long v5;\n v5 = __readfsqword(40u);\n if (regcomp(&v3, \"^[a-z]+_[a-z]+$\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n return \"Compilation error\";\n } else {\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n if (v1) {\n if (v1 == 1) {\n regfree(&v3);\n return \"Not matched!\";\n } else {\n regerror(v1, &v3, errbuf, 100uLL);\n __fprintf_chk(_bss_start, 2LL, \"Regex match failed: %s\\n\", errbuf);\n regfree(&v3);\n return \"Error occurred\";\n }\n } else {\n regfree(&v3);\n return \"Found a match!\";\n }\n }\n}" + }, + { + "index": 43, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char *func0(const char *text) {\n regex_t regex;\n int regexInit;\n int regexSearch;\n char *patterns = \"^[a-z]+_[a-z]+$\";\n regexInit = regcomp(®ex, patterns, REG_EXTENDED);\n if (regexInit) {\n fprintf(stderr, \"Could not compile regex\\n\");\n return (\"Compilation error\");\n }\n regexSearch = regexec(®ex, text, 0, NULL, 0);\n if (!regexSearch) {\n regfree(®ex);\n return (\"Found a match!\");\n } else if (regexSearch == REG_NOMATCH) {\n regfree(®ex);\n return (\"Not matched!\");\n } else {\n char errorMessage[100];\n regerror(regexSearch, ®ex, errorMessage, sizeof(errorMessage));\n fprintf(stderr, \"Regex match failed: %s\\n\", errorMessage);\n regfree(®ex);\n return (\"Error occurred\");\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"aab_cbbbc\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\"aab_Abbbc\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"Aaab_abbbc\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"aab-cbbbc\"), \"Not matched!\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov $0x1,%edx\nmov %rdi,%r12\nlea 0xcdc(%rip),%rsi\npush %rbp\nsub $0xb8,%rsp\nmov %fs:0x28,%rax\nmov %rax,0xa8(%rsp)\nxor %eax,%eax\nmov %rsp,%rbp\nmov %rbp,%rdi\ncallq 10f0 \ntest %eax,%eax\njne 1420 \nmov %rbp,%rdi\nxor %r8d,%r8d\nxor %ecx,%ecx\nxor %edx,%edx\nmov %r12,%rsi\ncallq 1110 \nmov %eax,%edi\ntest %eax,%eax\nje 1468 \ncmp $0x1,%eax\nje 1450 \nlea 0x40(%rsp),%r12\nmov $0x64,%ecx\nmov %rbp,%rsi\nmov %r12,%rdx\ncallq 1100 \nmov %r12,%rcx\nmov $0x1,%esi\nxor %eax,%eax\nmov 0x2c42(%rip),%rdi\nlea 0xc85(%rip),%rdx\ncallq 1130 <__fprintf_chk@plt>\nmov %rbp,%rdi\ncallq 10c0 \nlea 0xc39(%rip),%rax\nmov 0xa8(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 1479 \nadd $0xb8,%rsp\npop %rbp\npop %r12\nretq\nnopw 0x0(%rax,%rax,1)\nmov 0x2bf9(%rip),%rcx\nmov $0x18,%edx\nmov $0x1,%esi\nlea 0xc19(%rip),%rdi\ncallq 1120 \nlea 0xbc0(%rip),%rax\njmp 13f9 \nnopw %cs:0x0(%rax,%rax,1)\nmov %rbp,%rdi\ncallq 10c0 \nlea 0xbc6(%rip),%rax\njmp 13f9 \nnopl 0x0(%rax)\nmov %rbp,%rdi\ncallq 10c0 \nlea 0xb9f(%rip),%rax\njmp 13f9 \ncallq 10d0 <__stack_chk_fail@plt>\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov edx, 1; cflags\nmov rbp, rdi\nlea rsi, pattern; \"^[a-z]+_[a-z]+$\"\npush rbx\nsub rsp, 0B8h\nmov rax, fs:28h\nmov [rsp+0C8h+var_20], rax\nxor eax, eax\nmov rbx, rsp\nmov rdi, rbx; preg\ncall _regcomp\ntest eax, eax\njnz loc_1418\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbp; string\nmov rdi, rbx; preg\ncall _regexec\ntest eax, eax\njz loc_1458\ncmp eax, 1\njz loc_1440\nlea rbp, [rsp+0C8h+errbuf]\nmov ecx, 64h ; 'd'; errbuf_size\nmov rsi, rbx; preg\nmov edi, eax; errcode\nmov rdx, rbp; errbuf\ncall _regerror\nmov rcx, rbp\nmov esi, 2\nxor eax, eax\nmov rdi, cs:__bss_start\nlea rdx, aRegexMatchFail; \"Regex match failed: %s\\n\"\ncall ___fprintf_chk\nmov rdi, rbx; preg\ncall _regfree\nlea rax, aErrorOccurred; \"Error occurred\"\nloc_13F8:\nmov rdx, [rsp+0C8h+var_20]\nsub rdx, fs:28h\njnz short loc_1469\nadd rsp, 0B8h\npop rbx\npop rbp\nretn\nloc_1418:\nmov rcx, cs:__bss_start; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nlea rax, aCompilationErr; \"Compilation error\"\njmp short loc_13F8\nloc_1440:\nmov rdi, rbx; preg\ncall _regfree\nlea rax, aNotMatched; \"Not matched!\"\njmp short loc_13F8\nloc_1458:\nmov rdi, rbx; preg\ncall _regfree\nlea rax, s2; \"Found a match!\"\njmp short loc_13F8\nloc_1469:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // eax\n regex_t v3; // [rsp+0h] [rbp-C8h] BYREF\n char errbuf[104]; // [rsp+40h] [rbp-88h] BYREF\n unsigned __int64 v5; // [rsp+A8h] [rbp-20h]\n\n v5 = __readfsqword(0x28u);\n if ( regcomp(&v3, \"^[a-z]+_[a-z]+$\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n return \"Compilation error\";\n }\n else\n {\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n if ( v1 )\n {\n if ( v1 == 1 )\n {\n regfree(&v3);\n return \"Not matched!\";\n }\n else\n {\n regerror(v1, &v3, errbuf, 0x64uLL);\n __fprintf_chk(_bss_start, 2LL, \"Regex match failed: %s\\n\", errbuf);\n regfree(&v3);\n return \"Error occurred\";\n }\n }\n else\n {\n regfree(&v3);\n return \"Found a match!\";\n }\n }\n}", + "ida_strip_asm": "sub_1350:\nendbr64\npush rbp\nmov edx, 1; cflags\nmov rbp, rdi\nlea rsi, pattern; \"^[a-z]+_[a-z]+$\"\npush rbx\nsub rsp, 0B8h\nmov rax, fs:28h\nmov [rsp+0C8h+var_20], rax\nxor eax, eax\nmov rbx, rsp\nmov rdi, rbx; preg\ncall _regcomp\ntest eax, eax\njnz loc_1418\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbp; string\nmov rdi, rbx; preg\ncall _regexec\ntest eax, eax\njz loc_1458\ncmp eax, 1\njz loc_1440\nlea rbp, [rsp+0C8h+errbuf]\nmov ecx, 64h ; 'd'; errbuf_size\nmov rsi, rbx; preg\nmov edi, eax; errcode\nmov rdx, rbp; errbuf\ncall _regerror\nmov rcx, rbp\nmov esi, 2\nxor eax, eax\nmov rdi, cs:stderr\nlea rdx, aRegexMatchFail; \"Regex match failed: %s\\n\"\ncall ___fprintf_chk\nmov rdi, rbx; preg\ncall _regfree\nlea rax, aErrorOccurred; \"Error occurred\"\nloc_13F8:\nmov rdx, [rsp+0C8h+var_20]\nsub rdx, fs:28h\njnz short loc_1469\nadd rsp, 0B8h\npop rbx\npop rbp\nretn\nloc_1418:\nmov rcx, cs:stderr; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nlea rax, aCompilationErr; \"Compilation error\"\njmp short loc_13F8\nloc_1440:\nmov rdi, rbx; preg\ncall _regfree\nlea rax, aNotMatched; \"Not matched!\"\njmp short loc_13F8\nloc_1458:\nmov rdi, rbx; preg\ncall _regfree\nlea rax, s2; \"Found a match!\"\njmp short loc_13F8\nloc_1469:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_1350(char *string)\n{\n int v1; // eax\n regex_t v3; // [rsp+0h] [rbp-C8h] BYREF\n char errbuf[104]; // [rsp+40h] [rbp-88h] BYREF\n unsigned __int64 v5; // [rsp+A8h] [rbp-20h]\n\n v5 = __readfsqword(0x28u);\n if ( regcomp(&v3, \"^[a-z]+_[a-z]+$\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n return \"Compilation error\";\n }\n else\n {\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n if ( v1 )\n {\n if ( v1 == 1 )\n {\n regfree(&v3);\n return \"Not matched!\";\n }\n else\n {\n regerror(v1, &v3, errbuf, 0x64uLL);\n __fprintf_chk(stderr, 2LL, \"Regex match failed: %s\\n\", errbuf);\n regfree(&v3);\n return \"Error occurred\";\n }\n }\n else\n {\n regfree(&v3);\n return \"Found a match!\";\n }\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1350(char *string) {\n int v1;\n regex_t v3;\n char errbuf[104];\n unsigned long long v5;\n v5 = __readfsqword(40u);\n if (regcomp(&v3, \"^[a-z]+_[a-z]+$\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n return \"Compilation error\";\n } else {\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n if (v1) {\n if (v1 == 1) {\n regfree(&v3);\n return \"Not matched!\";\n } else {\n regerror(v1, &v3, errbuf, 100uLL);\n __fprintf_chk(stderr, 2LL, \"Regex match failed: %s\\n\", errbuf);\n regfree(&v3);\n return \"Error occurred\";\n }\n } else {\n regfree(&v3);\n return \"Found a match!\";\n }\n }\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n regex_t v3;\n char errbuf[104];\n unsigned long long v5;\n v5 = __readfsqword(40u);\n if (regcomp(&v3, \"^[a-z]+_[a-z]+$\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n return \"Compilation error\";\n } else {\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n if (v1) {\n if (v1 == 1) {\n regfree(&v3);\n return \"Not matched!\";\n } else {\n regerror(v1, &v3, errbuf, 100uLL);\n __fprintf_chk(_bss_start, 2LL, \"Regex match failed: %s\\n\", errbuf);\n regfree(&v3);\n return \"Error occurred\";\n }\n } else {\n regfree(&v3);\n return \"Found a match!\";\n }\n }\n}" + }, + { + "index": 43, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char *func0(const char *text) {\n regex_t regex;\n int regexInit;\n int regexSearch;\n char *patterns = \"^[a-z]+_[a-z]+$\";\n regexInit = regcomp(®ex, patterns, REG_EXTENDED);\n if (regexInit) {\n fprintf(stderr, \"Could not compile regex\\n\");\n return (\"Compilation error\");\n }\n regexSearch = regexec(®ex, text, 0, NULL, 0);\n if (!regexSearch) {\n regfree(®ex);\n return (\"Found a match!\");\n } else if (regexSearch == REG_NOMATCH) {\n regfree(®ex);\n return (\"Not matched!\");\n } else {\n char errorMessage[100];\n regerror(regexSearch, ®ex, errorMessage, sizeof(errorMessage));\n fprintf(stderr, \"Regex match failed: %s\\n\", errorMessage);\n regfree(®ex);\n return (\"Error occurred\");\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"aab_cbbbc\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\"aab_Abbbc\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"Aaab_abbbc\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"aab-cbbbc\"), \"Not matched!\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov $0x1,%edx\nmov %rdi,%r12\nlea 0xcdc(%rip),%rsi\npush %rbp\nsub $0xb8,%rsp\nmov %fs:0x28,%rax\nmov %rax,0xa8(%rsp)\nxor %eax,%eax\nmov %rsp,%rbp\nmov %rbp,%rdi\ncallq 10f0 \ntest %eax,%eax\njne 1420 \nmov %rbp,%rdi\nxor %r8d,%r8d\nxor %ecx,%ecx\nxor %edx,%edx\nmov %r12,%rsi\ncallq 1110 \nmov %eax,%edi\ntest %eax,%eax\nje 1468 \ncmp $0x1,%eax\nje 1450 \nlea 0x40(%rsp),%r12\nmov $0x64,%ecx\nmov %rbp,%rsi\nmov %r12,%rdx\ncallq 1100 \nmov %r12,%rcx\nmov $0x1,%esi\nxor %eax,%eax\nmov 0x2c42(%rip),%rdi\nlea 0xc85(%rip),%rdx\ncallq 1130 <__fprintf_chk@plt>\nmov %rbp,%rdi\ncallq 10c0 \nlea 0xc39(%rip),%rax\nmov 0xa8(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 1479 \nadd $0xb8,%rsp\npop %rbp\npop %r12\nretq\nnopw 0x0(%rax,%rax,1)\nmov 0x2bf9(%rip),%rcx\nmov $0x18,%edx\nmov $0x1,%esi\nlea 0xc19(%rip),%rdi\ncallq 1120 \nlea 0xbc0(%rip),%rax\njmp 13f9 \nnopw %cs:0x0(%rax,%rax,1)\nmov %rbp,%rdi\ncallq 10c0 \nlea 0xbc6(%rip),%rax\njmp 13f9 \nnopl 0x0(%rax)\nmov %rbp,%rdi\ncallq 10c0 \nlea 0xb9f(%rip),%rax\njmp 13f9 \ncallq 10d0 <__stack_chk_fail@plt>\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov edx, 1; cflags\nmov rbp, rdi\nlea rsi, pattern; \"^[a-z]+_[a-z]+$\"\npush rbx\nsub rsp, 0B8h\nmov rax, fs:28h\nmov [rsp+0C8h+var_20], rax\nxor eax, eax\nmov rbx, rsp\nmov rdi, rbx; preg\ncall _regcomp\ntest eax, eax\njnz loc_1418\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbp; string\nmov rdi, rbx; preg\ncall _regexec\ntest eax, eax\njz loc_1458\ncmp eax, 1\njz loc_1440\nlea rbp, [rsp+0C8h+errbuf]\nmov ecx, 64h ; 'd'; errbuf_size\nmov rsi, rbx; preg\nmov edi, eax; errcode\nmov rdx, rbp; errbuf\ncall _regerror\nmov rcx, rbp\nmov esi, 2\nxor eax, eax\nmov rdi, cs:__bss_start\nlea rdx, aRegexMatchFail; \"Regex match failed: %s\\n\"\ncall ___fprintf_chk\nmov rdi, rbx; preg\ncall _regfree\nlea rax, aErrorOccurred; \"Error occurred\"\nloc_13F8:\nmov rdx, [rsp+0C8h+var_20]\nsub rdx, fs:28h\njnz short loc_1469\nadd rsp, 0B8h\npop rbx\npop rbp\nretn\nloc_1418:\nmov rcx, cs:__bss_start; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nlea rax, aCompilationErr; \"Compilation error\"\njmp short loc_13F8\nloc_1440:\nmov rdi, rbx; preg\ncall _regfree\nlea rax, aNotMatched; \"Not matched!\"\njmp short loc_13F8\nloc_1458:\nmov rdi, rbx; preg\ncall _regfree\nlea rax, s2; \"Found a match!\"\njmp short loc_13F8\nloc_1469:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // eax\n regex_t v3; // [rsp+0h] [rbp-C8h] BYREF\n char errbuf[104]; // [rsp+40h] [rbp-88h] BYREF\n unsigned __int64 v5; // [rsp+A8h] [rbp-20h]\n\n v5 = __readfsqword(0x28u);\n if ( regcomp(&v3, \"^[a-z]+_[a-z]+$\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n return \"Compilation error\";\n }\n else\n {\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n if ( v1 )\n {\n if ( v1 == 1 )\n {\n regfree(&v3);\n return \"Not matched!\";\n }\n else\n {\n regerror(v1, &v3, errbuf, 0x64uLL);\n __fprintf_chk(_bss_start, 2LL, \"Regex match failed: %s\\n\", errbuf);\n regfree(&v3);\n return \"Error occurred\";\n }\n }\n else\n {\n regfree(&v3);\n return \"Found a match!\";\n }\n }\n}", + "ida_strip_asm": "sub_1350:\nendbr64\npush rbp\nmov edx, 1; cflags\nmov rbp, rdi\nlea rsi, pattern; \"^[a-z]+_[a-z]+$\"\npush rbx\nsub rsp, 0B8h\nmov rax, fs:28h\nmov [rsp+0C8h+var_20], rax\nxor eax, eax\nmov rbx, rsp\nmov rdi, rbx; preg\ncall _regcomp\ntest eax, eax\njnz loc_1418\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbp; string\nmov rdi, rbx; preg\ncall _regexec\ntest eax, eax\njz loc_1458\ncmp eax, 1\njz loc_1440\nlea rbp, [rsp+0C8h+errbuf]\nmov ecx, 64h ; 'd'; errbuf_size\nmov rsi, rbx; preg\nmov edi, eax; errcode\nmov rdx, rbp; errbuf\ncall _regerror\nmov rcx, rbp\nmov esi, 2\nxor eax, eax\nmov rdi, cs:stderr\nlea rdx, aRegexMatchFail; \"Regex match failed: %s\\n\"\ncall ___fprintf_chk\nmov rdi, rbx; preg\ncall _regfree\nlea rax, aErrorOccurred; \"Error occurred\"\nloc_13F8:\nmov rdx, [rsp+0C8h+var_20]\nsub rdx, fs:28h\njnz short loc_1469\nadd rsp, 0B8h\npop rbx\npop rbp\nretn\nloc_1418:\nmov rcx, cs:stderr; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nlea rax, aCompilationErr; \"Compilation error\"\njmp short loc_13F8\nloc_1440:\nmov rdi, rbx; preg\ncall _regfree\nlea rax, aNotMatched; \"Not matched!\"\njmp short loc_13F8\nloc_1458:\nmov rdi, rbx; preg\ncall _regfree\nlea rax, s2; \"Found a match!\"\njmp short loc_13F8\nloc_1469:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_1350(char *string)\n{\n int v1; // eax\n regex_t v3; // [rsp+0h] [rbp-C8h] BYREF\n char errbuf[104]; // [rsp+40h] [rbp-88h] BYREF\n unsigned __int64 v5; // [rsp+A8h] [rbp-20h]\n\n v5 = __readfsqword(0x28u);\n if ( regcomp(&v3, \"^[a-z]+_[a-z]+$\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n return \"Compilation error\";\n }\n else\n {\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n if ( v1 )\n {\n if ( v1 == 1 )\n {\n regfree(&v3);\n return \"Not matched!\";\n }\n else\n {\n regerror(v1, &v3, errbuf, 0x64uLL);\n __fprintf_chk(stderr, 2LL, \"Regex match failed: %s\\n\", errbuf);\n regfree(&v3);\n return \"Error occurred\";\n }\n }\n else\n {\n regfree(&v3);\n return \"Found a match!\";\n }\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1350(char *string) {\n int v1;\n regex_t v3;\n char errbuf[104];\n unsigned long long v5;\n v5 = __readfsqword(40u);\n if (regcomp(&v3, \"^[a-z]+_[a-z]+$\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n return \"Compilation error\";\n } else {\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n if (v1) {\n if (v1 == 1) {\n regfree(&v3);\n return \"Not matched!\";\n } else {\n regerror(v1, &v3, errbuf, 100uLL);\n __fprintf_chk(stderr, 2LL, \"Regex match failed: %s\\n\", errbuf);\n regfree(&v3);\n return \"Error occurred\";\n }\n } else {\n regfree(&v3);\n return \"Found a match!\";\n }\n }\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n regex_t v3;\n char errbuf[104];\n unsigned long long v5;\n v5 = __readfsqword(40u);\n if (regcomp(&v3, \"^[a-z]+_[a-z]+$\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n return \"Compilation error\";\n } else {\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n if (v1) {\n if (v1 == 1) {\n regfree(&v3);\n return \"Not matched!\";\n } else {\n regerror(v1, &v3, errbuf, 100uLL);\n __fprintf_chk(_bss_start, 2LL, \"Regex match failed: %s\\n\", errbuf);\n regfree(&v3);\n return \"Error occurred\";\n }\n } else {\n regfree(&v3);\n return \"Found a match!\";\n }\n }\n}" + }, + { + "index": 44, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n regex_t regex;\n int result;\n char* pattern = \"^[[:alnum:]_]+\";\n if (regcomp(®ex, pattern, REG_EXTENDED) != 0) {\n return \"Regex compilation error\";\n }\n result = regexec(®ex, text, 0, NULL, 0);\n regfree(®ex);\n if (result == 0) {\n return \"Found a match!\";\n } else {\n return \"Not matched!\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\" python\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"python\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\" lang\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"foo\"), \"Found a match!\") == 0);\n\n \n\n printf(\"All tests passed.\\n\");\n\n \n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x70,%rsp\nmov %rdi,-0x68(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0xdd9(%rip),%rax\nmov %rax,-0x58(%rbp)\nmov -0x58(%rbp),%rcx\nlea -0x50(%rbp),%rax\nmov $0x1,%edx\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 10f0 \ntest %eax,%eax\nje 1258 \nlea 0xdc1(%rip),%rax\njmp 129d \nmov -0x68(%rbp),%rsi\nlea -0x50(%rbp),%rax\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rax,%rdi\ncallq 1110 \nmov %eax,-0x5c(%rbp)\nlea -0x50(%rbp),%rax\nmov %rax,%rdi\ncallq 10c0 \ncmpl $0x0,-0x5c(%rbp)\njne 1296 \nlea 0xd9b(%rip),%rax\njmp 129d \nlea 0xda1(%rip),%rax\nmov -0x8(%rbp),%rdx\nxor %fs:0x28,%rdx\nje 12b1 \ncallq 10d0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aAlnum; \"^[[:alnum:]_]+\"\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\ntest eax, eax\njz short loc_1258\nlea rax, aRegexCompilati; \"Regex compilation error\"\njmp short loc_129D\nloc_1258:\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_5C], eax\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\ncmp [rbp+var_5C], 0\njnz short loc_1296\nlea rax, aFoundAMatch; \"Found a match!\"\njmp short loc_129D\nloc_1296:\nlea rax, s2; \"Not matched!\"\nloc_129D:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12B1\ncall ___stack_chk_fail\nlocret_12B1:\nleave\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n int v2; // [rsp+14h] [rbp-5Ch]\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n unsigned __int64 v4; // [rsp+68h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"^[[:alnum:]_]+\", 1) )\n return \"Regex compilation error\";\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if ( v2 )\n return \"Not matched!\";\n else\n return \"Found a match!\";\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aAlnum; \"^[[:alnum:]_]+\"\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\ntest eax, eax\njz short loc_1258\nlea rax, aRegexCompilati; \"Regex compilation error\"\njmp short loc_129D\nloc_1258:\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_5C], eax\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\ncmp [rbp+var_5C], 0\njnz short loc_1296\nlea rax, aFoundAMatch; \"Found a match!\"\njmp short loc_129D\nloc_1296:\nlea rax, s2; \"Not matched!\"\nloc_129D:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12B1\ncall ___stack_chk_fail\nlocret_12B1:\nleave\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1209(const char *a1)\n{\n int v2; // [rsp+14h] [rbp-5Ch]\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n unsigned __int64 v4; // [rsp+68h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"^[[:alnum:]_]+\", 1) )\n return \"Regex compilation error\";\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if ( v2 )\n return \"Not matched!\";\n else\n return \"Found a match!\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1209(const char *a1) {\n int v2;\n regex_t preg;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n if (regcomp(&preg, \"^[[:alnum:]_]+\", 1)) return \"Regex compilation error\";\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if (v2)\n return \"Not matched!\";\n else\n return \"Found a match!\";\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n int v2;\n regex_t preg;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n if (regcomp(&preg, \"^[[:alnum:]_]+\", 1)) return \"Regex compilation error\";\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if (v2)\n return \"Not matched!\";\n else\n return \"Found a match!\";\n}" + }, + { + "index": 44, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n regex_t regex;\n int result;\n char* pattern = \"^[[:alnum:]_]+\";\n if (regcomp(®ex, pattern, REG_EXTENDED) != 0) {\n return \"Regex compilation error\";\n }\n result = regexec(®ex, text, 0, NULL, 0);\n regfree(®ex);\n if (result == 0) {\n return \"Found a match!\";\n } else {\n return \"Not matched!\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\" python\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"python\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\" lang\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"foo\"), \"Found a match!\") == 0);\n\n \n\n printf(\"All tests passed.\\n\");\n\n \n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x58,%rsp\nmov %rdi,%rbx\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nmov $0x1,%edx\nlea 0xe23(%rip),%rsi\ncallq 10e0 \nmov %eax,%edx\nlea 0xde1(%rip),%rax\ntest %edx,%edx\nje 123e \nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 127c \nadd $0x58,%rsp\npop %rbx\npop %rbp\nretq\nmov %rsp,%rbp\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rbx,%rsi\nmov %rbp,%rdi\ncallq 10f0 \nmov %eax,%ebx\nmov %rbp,%rdi\ncallq 10b0 \ntest %ebx,%ebx\nlea 0xdad(%rip),%rax\nlea 0xdb5(%rip),%rdx\ncmovne %rdx,%rax\njmp 1227 \ncallq 10c0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+68h+var_20], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"^[[:alnum:]_]+\"\ncall _regcomp\nmov edx, eax\nlea rax, aRegexCompilati; \"Regex compilation error\"\ntest edx, edx\njz short loc_125E\nloc_1247:\nmov rdx, [rsp+68h+var_20]\nsub rdx, fs:28h\njnz short loc_129C\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_125E:\nmov rbp, rsp\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov ebx, eax\nmov rdi, rbp; preg\ncall _regfree\ntest ebx, ebx\nlea rax, s2; \"Not matched!\"\nlea rdx, aFoundAMatch; \"Found a match!\"\ncmovz rax, rdx\njmp short loc_1247\nloc_129C:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // edx\n const char *result; // rax\n int v3; // ebx\n regex_t v4; // [rsp+0h] [rbp-68h] BYREF\n unsigned __int64 v5; // [rsp+48h] [rbp-20h]\n\n v5 = __readfsqword(0x28u);\n v1 = regcomp(&v4, \"^[[:alnum:]_]+\", 1);\n result = \"Regex compilation error\";\n if ( !v1 )\n {\n v3 = regexec(&v4, string, 0LL, 0LL, 0);\n regfree(&v4);\n result = \"Not matched!\";\n if ( !v3 )\n return \"Found a match!\";\n }\n return result;\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+68h+var_20], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"^[[:alnum:]_]+\"\ncall _regcomp\nmov edx, eax\nlea rax, aRegexCompilati; \"Regex compilation error\"\ntest edx, edx\njz short loc_125E\nloc_1247:\nmov rdx, [rsp+68h+var_20]\nsub rdx, fs:28h\njnz short loc_129C\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_125E:\nmov rbp, rsp\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov ebx, eax\nmov rdi, rbp; preg\ncall _regfree\ntest ebx, ebx\nlea rax, s2; \"Not matched!\"\nlea rdx, aFoundAMatch; \"Found a match!\"\ncmovz rax, rdx\njmp short loc_1247\nloc_129C:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_1209(char *string)\n{\n int v1; // edx\n const char *result; // rax\n int v3; // ebx\n regex_t v4; // [rsp+0h] [rbp-68h] BYREF\n unsigned __int64 v5; // [rsp+48h] [rbp-20h]\n\n v5 = __readfsqword(0x28u);\n v1 = regcomp(&v4, \"^[[:alnum:]_]+\", 1);\n result = \"Regex compilation error\";\n if ( !v1 )\n {\n v3 = regexec(&v4, string, 0LL, 0LL, 0);\n regfree(&v4);\n result = \"Not matched!\";\n if ( !v3 )\n return \"Found a match!\";\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1209(char *string) {\n int v1;\n const char *result;\n int v3;\n regex_t v4;\n unsigned long long v5;\n v5 = __readfsqword(40u);\n v1 = regcomp(&v4, \"^[[:alnum:]_]+\", 1);\n result = \"Regex compilation error\";\n if (!v1) {\n v3 = regexec(&v4, string, 0LL, 0LL, 0);\n regfree(&v4);\n result = \"Not matched!\";\n if (!v3) return \"Found a match!\";\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n const char *result;\n int v3;\n regex_t v4;\n unsigned long long v5;\n v5 = __readfsqword(40u);\n v1 = regcomp(&v4, \"^[[:alnum:]_]+\", 1);\n result = \"Regex compilation error\";\n if (!v1) {\n v3 = regexec(&v4, string, 0LL, 0LL, 0);\n regfree(&v4);\n result = \"Not matched!\";\n if (!v3) return \"Found a match!\";\n }\n return result;\n}" + }, + { + "index": 44, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n regex_t regex;\n int result;\n char* pattern = \"^[[:alnum:]_]+\";\n if (regcomp(®ex, pattern, REG_EXTENDED) != 0) {\n return \"Regex compilation error\";\n }\n result = regexec(®ex, text, 0, NULL, 0);\n regfree(®ex);\n if (result == 0) {\n return \"Found a match!\";\n } else {\n return \"Not matched!\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\" python\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"python\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\" lang\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"foo\"), \"Found a match!\") == 0);\n\n \n\n printf(\"All tests passed.\\n\");\n\n \n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov $0x1,%edx\nlea 0xcf6(%rip),%rsi\npush %rbp\nmov %rdi,%rbp\nsub $0x58,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%r12\nmov %r12,%rdi\ncallq 10e0 \nmov %eax,%r8d\nlea 0xc95(%rip),%rax\ntest %r8d,%r8d\njne 13a1 \nxor %edx,%edx\nxor %ecx,%ecx\nmov %rbp,%rsi\nmov %r12,%rdi\ncallq 10f0 \nmov %r12,%rdi\nmov %eax,%ebp\ncallq 10b0 \ntest %ebp,%ebp\nlea 0xc86(%rip),%rax\nlea 0xc8e(%rip),%rdx\ncmovne %rdx,%rax\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 13b9 \nadd $0x58,%rsp\npop %rbp\npop %r12\nretq\ncallq 10c0 <__stack_chk_fail@plt>\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"^[[:alnum:]_]+\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nmov edx, eax\nlea rax, aRegexCompilati; \"Regex compilation error\"\ntest edx, edx\njnz short loc_13A1\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, s2; \"Not matched!\"\nlea rdx, aFoundAMatch; \"Found a match!\"\ncmovz rax, rdx\nloc_13A1:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_13B8\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_13B8:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // edx\n const char *result; // rax\n int v3; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n v1 = regcomp(&_0, \"^[[:alnum:]_]+\", 1);\n result = \"Regex compilation error\";\n if ( !v1 )\n {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if ( !v3 )\n return \"Found a match!\";\n }\n return result;\n}", + "ida_strip_asm": "sub_1330:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"^[[:alnum:]_]+\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nmov edx, eax\nlea rax, aRegexCompilati; \"Regex compilation error\"\ntest edx, edx\njnz short loc_13A1\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, s2; \"Not matched!\"\nlea rdx, aFoundAMatch; \"Found a match!\"\ncmovz rax, rdx\nloc_13A1:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_13B8\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_13B8:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_1330(char *string)\n{\n int v1; // edx\n const char *result; // rax\n int v3; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n v1 = regcomp(&_0, \"^[[:alnum:]_]+\", 1);\n result = \"Regex compilation error\";\n if ( !v1 )\n {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if ( !v3 )\n return \"Found a match!\";\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1330(char *string) {\n int v1;\n const char *result;\n int v3;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n v1 = regcomp(&_0, \"^[[:alnum:]_]+\", 1);\n result = \"Regex compilation error\";\n if (!v1) {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if (!v3) return \"Found a match!\";\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n const char *result;\n int v3;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n v1 = regcomp(&_0, \"^[[:alnum:]_]+\", 1);\n result = \"Regex compilation error\";\n if (!v1) {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if (!v3) return \"Found a match!\";\n }\n return result;\n}" + }, + { + "index": 44, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n regex_t regex;\n int result;\n char* pattern = \"^[[:alnum:]_]+\";\n if (regcomp(®ex, pattern, REG_EXTENDED) != 0) {\n return \"Regex compilation error\";\n }\n result = regexec(®ex, text, 0, NULL, 0);\n regfree(®ex);\n if (result == 0) {\n return \"Found a match!\";\n } else {\n return \"Not matched!\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\" python\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"python\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\" lang\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"foo\"), \"Found a match!\") == 0);\n\n \n\n printf(\"All tests passed.\\n\");\n\n \n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov $0x1,%edx\nlea 0xcf6(%rip),%rsi\npush %rbp\nmov %rdi,%rbp\nsub $0x58,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%r12\nmov %r12,%rdi\ncallq 10e0 \nmov %eax,%r8d\nlea 0xc95(%rip),%rax\ntest %r8d,%r8d\njne 13a1 \nxor %edx,%edx\nxor %ecx,%ecx\nmov %rbp,%rsi\nmov %r12,%rdi\ncallq 10f0 \nmov %r12,%rdi\nmov %eax,%ebp\ncallq 10b0 \ntest %ebp,%ebp\nlea 0xc86(%rip),%rax\nlea 0xc8e(%rip),%rdx\ncmovne %rdx,%rax\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 13b9 \nadd $0x58,%rsp\npop %rbp\npop %r12\nretq\ncallq 10c0 <__stack_chk_fail@plt>\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"^[[:alnum:]_]+\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nmov edx, eax\nlea rax, aRegexCompilati; \"Regex compilation error\"\ntest edx, edx\njnz short loc_13A1\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, s2; \"Not matched!\"\nlea rdx, aFoundAMatch; \"Found a match!\"\ncmovz rax, rdx\nloc_13A1:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_13B8\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_13B8:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // edx\n const char *result; // rax\n int v3; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n v1 = regcomp(&_0, \"^[[:alnum:]_]+\", 1);\n result = \"Regex compilation error\";\n if ( !v1 )\n {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if ( !v3 )\n return \"Found a match!\";\n }\n return result;\n}", + "ida_strip_asm": "sub_1330:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"^[[:alnum:]_]+\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nmov edx, eax\nlea rax, aRegexCompilati; \"Regex compilation error\"\ntest edx, edx\njnz short loc_13A1\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, s2; \"Not matched!\"\nlea rdx, aFoundAMatch; \"Found a match!\"\ncmovz rax, rdx\nloc_13A1:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_13B8\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_13B8:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_1330(char *string)\n{\n int v1; // edx\n const char *result; // rax\n int v3; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n v1 = regcomp(&_0, \"^[[:alnum:]_]+\", 1);\n result = \"Regex compilation error\";\n if ( !v1 )\n {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if ( !v3 )\n return \"Found a match!\";\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1330(char *string) {\n int v1;\n const char *result;\n int v3;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n v1 = regcomp(&_0, \"^[[:alnum:]_]+\", 1);\n result = \"Regex compilation error\";\n if (!v1) {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if (!v3) return \"Found a match!\";\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n const char *result;\n int v3;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n v1 = regcomp(&_0, \"^[[:alnum:]_]+\", 1);\n result = \"Regex compilation error\";\n if (!v1) {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if (!v3) return \"Found a match!\";\n }\n return result;\n}" + }, + { + "index": 45, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\nint find_gcd(int x, int y) {\n\n while (y != 0) {\n\n int temp = y;\n\n y = x % y;\n\n x = temp;\n\n }\n\n return x;\n\n}\n\n\n\n", + "func": "int func0(int *l, int size) {\n int num1 = l[0];\n int num2 = l[1];\n int gcd = find_gcd(num1, num2);\n for (int i = 2; i < size; i++) {\n gcd = find_gcd(gcd, l[i]);\n }\n return gcd;\n}", + "test": "int main() {\n\n int arr1[] = {2, 4, 6, 8, 16};\n\n int arr2[] = {1, 2, 3};\n\n int arr3[] = {2, 4, 6, 8};\n\n assert(func0(arr1, 5) == 2);\n\n assert(func0(arr2, 3) == 1);\n\n assert(func0(arr3, 4) == 2);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov -0x18(%rbp),%rax\nmov (%rax),%eax\nmov %eax,-0x8(%rbp)\nmov -0x18(%rbp),%rax\nmov 0x4(%rax),%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%edx\nmov -0x8(%rbp),%eax\nmov %edx,%esi\nmov %eax,%edi\ncallq 1169 \nmov %eax,-0x10(%rbp)\nmovl $0x2,-0xc(%rbp)\njmp 1204 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x10(%rbp),%eax\nmov %edx,%esi\nmov %eax,%edi\ncallq 1169 \nmov %eax,-0x10(%rbp)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11db \nmov -0x10(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov rax, [rbp+var_18]\nmov eax, [rax]\nmov [rbp+var_8], eax\nmov rax, [rbp+var_18]\nmov eax, [rax+4]\nmov [rbp+var_4], eax\nmov edx, [rbp+var_4]\nmov eax, [rbp+var_8]\nmov esi, edx\nmov edi, eax\ncall find_gcd\nmov [rbp+var_10], eax\nmov [rbp+var_C], 2\njmp short loc_1204\nloc_11DB:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\nmov esi, edx\nmov edi, eax\ncall find_gcd\nmov [rbp+var_10], eax\nadd [rbp+var_C], 1\nloc_1204:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_11DB\nmov eax, [rbp+var_10]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n unsigned int gcd; // [rsp+10h] [rbp-10h]\n int i; // [rsp+14h] [rbp-Ch]\n\n gcd = find_gcd(*a1, a1[1]);\n for ( i = 2; i < a2; ++i )\n gcd = find_gcd(gcd, a1[i]);\n return gcd;\n}", + "ida_strip_asm": "sub_119A:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov rax, [rbp+var_18]\nmov eax, [rax]\nmov [rbp+var_8], eax\nmov rax, [rbp+var_18]\nmov eax, [rax+4]\nmov [rbp+var_4], eax\nmov edx, [rbp+var_4]\nmov eax, [rbp+var_8]\nmov esi, edx\nmov edi, eax\ncall sub_1169\nmov [rbp+var_10], eax\nmov [rbp+var_C], 2\njmp short loc_1204\nloc_11DB:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\nmov esi, edx\nmov edi, eax\ncall sub_1169\nmov [rbp+var_10], eax\nadd [rbp+var_C], 1\nloc_1204:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_11DB\nmov eax, [rbp+var_10]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_119A(unsigned int *a1, int a2)\n{\n unsigned int v3; // [rsp+10h] [rbp-10h]\n int i; // [rsp+14h] [rbp-Ch]\n\n v3 = sub_1169(*a1, a1[1]);\n for ( i = 2; i < a2; ++i )\n v3 = sub_1169(v3, a1[i]);\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_119A(unsigned int *a1, int a2) {\n unsigned int v3;\n int i;\n v3 = sub_1169(*a1, a1[1]);\n for (i = 2; i < a2; ++i) v3 = sub_1169(v3, a1[i]);\n return v3;\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n unsigned int gcd;\n int i;\n gcd = find_gcd(*a1, a1[1]);\n for (i = 2; i < a2; ++i) gcd = find_gcd(gcd, a1[i]);\n return gcd;\n}" + }, + { + "index": 45, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\nint find_gcd(int x, int y) {\n\n while (y != 0) {\n\n int temp = y;\n\n y = x % y;\n\n x = temp;\n\n }\n\n return x;\n\n}\n\n\n\n", + "func": "int func0(int *l, int size) {\n int num1 = l[0];\n int num2 = l[1];\n int gcd = find_gcd(num1, num2);\n for (int i = 2; i < size; i++) {\n gcd = find_gcd(gcd, l[i]);\n }\n return gcd;\n}", + "test": "int main() {\n\n int arr1[] = {2, 4, 6, 8, 16};\n\n int arr2[] = {1, 2, 3};\n\n int arr3[] = {2, 4, 6, 8};\n\n assert(func0(arr1, 5) == 2);\n\n assert(func0(arr2, 3) == 1);\n\n assert(func0(arr3, 4) == 2);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov (%rdi),%eax\nmov 0x4(%rdi),%r8d\ntest %r8d,%r8d\nje 11b9 \nmov %r8d,%ecx\ncltd\nidiv %r8d\nmov %edx,%r8d\nmov %ecx,%eax\ntest %edx,%edx\njne 1196 \ncmp $0x2,%esi\njle 11de \nlea 0x8(%rdi),%r8\nlea -0x3(%rsi),%eax\nlea 0xc(%rdi,%rax,4),%r9\njmp 11d5 \nmov %eax,%ecx\njmp 11a6 \nmov %esi,%edi\nmov %ecx,%eax\ncltd\nidiv %esi\nmov %edx,%esi\nmov %edi,%ecx\ntest %edx,%edx\njne 11bd \nadd $0x4,%r8\ncmp %r9,%r8\nje 11de \nmov (%r8),%esi\ntest %esi,%esi\njne 11bd \njmp 11cc \nmov %ecx,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov eax, [rdi]\nmov r8d, [rdi+4]\ntest r8d, r8d\njz short loc_11D9\nloc_1196:\nmov ecx, r8d\ncdq\nidiv r8d\nmov r8d, edx\nmov eax, ecx\ntest edx, edx\njnz short loc_1196\nloc_11A6:\ncmp esi, 2\njle short loc_11D6\nlea r8, [rdi+8]\nlea eax, [rsi-3]\nlea r9, [rdi+rax*4+0Ch]\nloc_11B7:\nmov esi, [r8]\ntest esi, esi\njz short loc_11CD\nloc_11BE:\nmov edi, esi\nmov eax, ecx\ncdq\nidiv esi\nmov esi, edx\nmov ecx, edi\ntest edx, edx\njnz short loc_11BE\nloc_11CD:\nadd r8, 4\ncmp r8, r9\njnz short loc_11B7\nloc_11D6:\nmov eax, ecx\nretn\nloc_11D9:\nmov ecx, eax\njmp short loc_11A6", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int v2; // eax\n int v3; // r8d\n int v4; // ecx\n int *v5; // r8\n __int64 v6; // r9\n int i; // esi\n int v8; // edi\n\n v2 = *a1;\n v3 = a1[1];\n if ( v3 )\n {\n do\n {\n v4 = v3;\n v3 = v2 % v3;\n v2 = v4;\n }\n while ( v3 );\n }\n else\n {\n v4 = *a1;\n }\n if ( a2 > 2 )\n {\n v5 = a1 + 2;\n v6 = (__int64)&a1[a2 - 3 + 3];\n do\n {\n for ( i = *v5; i; v4 = v8 )\n {\n v8 = i;\n i = v4 % i;\n }\n ++v5;\n }\n while ( v5 != (int *)v6 );\n }\n return (unsigned int)v4;\n}", + "ida_strip_asm": "sub_1187:\nendbr64\nmov eax, [rdi]\nmov r8d, [rdi+4]\ntest r8d, r8d\njz short loc_11D9\nloc_1196:\nmov ecx, r8d\ncdq\nidiv r8d\nmov r8d, edx\nmov eax, ecx\ntest edx, edx\njnz short loc_1196\nloc_11A6:\ncmp esi, 2\njle short loc_11D6\nlea r8, [rdi+8]\nlea eax, [rsi-3]\nlea r9, [rdi+rax*4+0Ch]\nloc_11B7:\nmov esi, [r8]\ntest esi, esi\njz short loc_11CD\nloc_11BE:\nmov edi, esi\nmov eax, ecx\ncdq\nidiv esi\nmov esi, edx\nmov ecx, edi\ntest edx, edx\njnz short loc_11BE\nloc_11CD:\nadd r8, 4\ncmp r8, r9\njnz short loc_11B7\nloc_11D6:\nmov eax, ecx\nretn\nloc_11D9:\nmov ecx, eax\njmp short loc_11A6", + "ida_strip_pseudo": "__int64 __fastcall sub_1187(int *a1, int a2)\n{\n int v2; // eax\n int v3; // r8d\n int v4; // ecx\n int *v5; // r8\n __int64 v6; // r9\n int i; // esi\n int v8; // edi\n\n v2 = *a1;\n v3 = a1[1];\n if ( v3 )\n {\n do\n {\n v4 = v3;\n v3 = v2 % v3;\n v2 = v4;\n }\n while ( v3 );\n }\n else\n {\n v4 = *a1;\n }\n if ( a2 > 2 )\n {\n v5 = a1 + 2;\n v6 = (__int64)&a1[a2 - 3 + 3];\n do\n {\n for ( i = *v5; i; v4 = v8 )\n {\n v8 = i;\n i = v4 % i;\n }\n ++v5;\n }\n while ( v5 != (int *)v6 );\n }\n return (unsigned int)v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1187(int *a1, int a2) {\n int v2;\n int v3;\n int v4;\n int *v5;\n long long v6;\n int i;\n int v8;\n v2 = *a1;\n v3 = a1[1];\n if (v3) {\n do {\n v4 = v3;\n v3 = v2 % v3;\n v2 = v4;\n } while (v3);\n } else {\n v4 = *a1;\n }\n if (a2 > 2) {\n v5 = a1 + 2;\n v6 = (long long)&a1[a2 - 3 + 3];\n do {\n for (i = *v5; i; v4 = v8) {\n v8 = i;\n i = v4 % i;\n }\n ++v5;\n } while (v5 != (int *)v6);\n }\n return (unsigned int)v4;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int v2;\n int v3;\n int v4;\n int *v5;\n long long v6;\n int i;\n int v8;\n v2 = *a1;\n v3 = a1[1];\n if (v3) {\n do {\n v4 = v3;\n v3 = v2 % v3;\n v2 = v4;\n } while (v3);\n } else {\n v4 = *a1;\n }\n if (a2 > 2) {\n v5 = a1 + 2;\n v6 = (long long)&a1[a2 - 3 + 3];\n do {\n for (i = *v5; i; v4 = v8) {\n v8 = i;\n i = v4 % i;\n }\n ++v5;\n } while (v5 != (int *)v6);\n }\n return (unsigned int)v4;\n}" + }, + { + "index": 45, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\nint find_gcd(int x, int y) {\n\n while (y != 0) {\n\n int temp = y;\n\n y = x % y;\n\n x = temp;\n\n }\n\n return x;\n\n}\n\n\n\n", + "func": "int func0(int *l, int size) {\n int num1 = l[0];\n int num2 = l[1];\n int gcd = find_gcd(num1, num2);\n for (int i = 2; i < size; i++) {\n gcd = find_gcd(gcd, l[i]);\n }\n return gcd;\n}", + "test": "int main() {\n\n int arr1[] = {2, 4, 6, 8, 16};\n\n int arr2[] = {1, 2, 3};\n\n int arr3[] = {2, 4, 6, 8};\n\n assert(func0(arr1, 5) == 2);\n\n assert(func0(arr2, 3) == 1);\n\n assert(func0(arr3, 4) == 2);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov 0x4(%rdi),%r8d\nmov (%rdi),%eax\ntest %r8d,%r8d\njne 12eb \njmp 133b \nnopl 0x0(%rax)\nmov %edx,%r8d\ncltd\nidiv %r8d\nmov %r8d,%eax\ntest %edx,%edx\njne 12e8 \ncmp $0x2,%esi\njle 1337 \nlea -0x3(%rsi),%eax\nlea 0x8(%rdi),%rcx\nlea 0xc(%rdi,%rax,4),%rsi\nnopw 0x0(%rax,%rax,1)\nmov (%rcx),%edx\ntest %edx,%edx\nje 132e \nmov %r8d,%eax\nnopl 0x0(%rax)\nmov %edx,%r8d\ncltd\nidiv %r8d\nmov %r8d,%eax\ntest %edx,%edx\njne 1320 \nadd $0x4,%rcx\ncmp %rsi,%rcx\njne 1310 \nmov %r8d,%eax\nretq\nmov %eax,%r8d\njmp 12f6 \n", + "ida_asm": "func0:\nendbr64\nmov ecx, [rdi+4]\nmov eax, [rdi]\ntest ecx, ecx\njnz short loc_12B2\njmp short loc_12F7\nloc_12B0:\nmov ecx, edx\nloc_12B2:\ncdq\nidiv ecx\nmov eax, ecx\ntest edx, edx\njnz short loc_12B0\nloc_12BB:\ncmp esi, 2\njle short loc_12F4\nlea eax, [rsi-3]\nlea r8, [rdi+8]\nlea rsi, [rdi+rax*4+0Ch]\nnop dword ptr [rax+00h]\nloc_12D0:\nmov edx, [r8]\ntest edx, edx\njz short loc_12EB\nmov eax, ecx\nnop dword ptr [rax+00000000h]\nloc_12E0:\nmov ecx, edx\ncdq\nidiv ecx\nmov eax, ecx\ntest edx, edx\njnz short loc_12E0\nloc_12EB:\nadd r8, 4\ncmp r8, rsi\njnz short loc_12D0\nloc_12F4:\nmov eax, ecx\nretn\nloc_12F7:\nmov ecx, eax\njmp short loc_12BB", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int v2; // ecx\n int v3; // eax\n int v4; // edx\n int *v5; // r8\n __int64 v6; // rsi\n int v7; // edx\n int v8; // eax\n\n v2 = a1[1];\n v3 = *a1;\n if ( v2 )\n {\n while ( 1 )\n {\n v4 = v3 % v2;\n v3 = v2;\n if ( !v4 )\n break;\n v2 = v4;\n }\n }\n else\n {\n v2 = *a1;\n }\n if ( a2 > 2 )\n {\n v5 = a1 + 2;\n v6 = (__int64)&a1[a2 - 3 + 3];\n do\n {\n v7 = *v5;\n if ( *v5 )\n {\n v8 = v2;\n do\n {\n v2 = v7;\n v7 = v8 % v7;\n v8 = v2;\n }\n while ( v7 );\n }\n ++v5;\n }\n while ( v5 != (int *)v6 );\n }\n return (unsigned int)v2;\n}", + "ida_strip_asm": "sub_12A0:\nendbr64\nmov ecx, [rdi+4]\nmov eax, [rdi]\ntest ecx, ecx\njnz short loc_12B2\njmp short loc_12F7\nloc_12B0:\nmov ecx, edx\nloc_12B2:\ncdq\nidiv ecx\nmov eax, ecx\ntest edx, edx\njnz short loc_12B0\nloc_12BB:\ncmp esi, 2\njle short loc_12F4\nlea eax, [rsi-3]\nlea r8, [rdi+8]\nlea rsi, [rdi+rax*4+0Ch]\nnop dword ptr [rax+00h]\nloc_12D0:\nmov edx, [r8]\ntest edx, edx\njz short loc_12EB\nmov eax, ecx\nnop dword ptr [rax+00000000h]\nloc_12E0:\nmov ecx, edx\ncdq\nidiv ecx\nmov eax, ecx\ntest edx, edx\njnz short loc_12E0\nloc_12EB:\nadd r8, 4\ncmp r8, rsi\njnz short loc_12D0\nloc_12F4:\nmov eax, ecx\nretn\nloc_12F7:\nmov ecx, eax\njmp short loc_12BB", + "ida_strip_pseudo": "__int64 __fastcall sub_12A0(int *a1, int a2)\n{\n int v2; // ecx\n int v3; // eax\n int v4; // edx\n int *v5; // r8\n __int64 v6; // rsi\n int v7; // edx\n int v8; // eax\n\n v2 = a1[1];\n v3 = *a1;\n if ( v2 )\n {\n while ( 1 )\n {\n v4 = v3 % v2;\n v3 = v2;\n if ( !v4 )\n break;\n v2 = v4;\n }\n }\n else\n {\n v2 = *a1;\n }\n if ( a2 > 2 )\n {\n v5 = a1 + 2;\n v6 = (__int64)&a1[a2 - 3 + 3];\n do\n {\n v7 = *v5;\n if ( *v5 )\n {\n v8 = v2;\n do\n {\n v2 = v7;\n v7 = v8 % v7;\n v8 = v2;\n }\n while ( v7 );\n }\n ++v5;\n }\n while ( v5 != (int *)v6 );\n }\n return (unsigned int)v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12A0(int *a1, int a2) {\n int v2;\n int v3;\n int v4;\n int *v5;\n long long v6;\n int v7;\n int v8;\n v2 = a1[1];\n v3 = *a1;\n if (v2) {\n while (1) {\n v4 = v3 % v2;\n v3 = v2;\n if (!v4) break;\n v2 = v4;\n }\n } else {\n v2 = *a1;\n }\n if (a2 > 2) {\n v5 = a1 + 2;\n v6 = (long long)&a1[a2 - 3 + 3];\n do {\n v7 = *v5;\n if (*v5) {\n v8 = v2;\n do {\n v2 = v7;\n v7 = v8 % v7;\n v8 = v2;\n } while (v7);\n }\n ++v5;\n } while (v5 != (int *)v6);\n }\n return (unsigned int)v2;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int v2;\n int v3;\n int v4;\n int *v5;\n long long v6;\n int v7;\n int v8;\n v2 = a1[1];\n v3 = *a1;\n if (v2) {\n while (1) {\n v4 = v3 % v2;\n v3 = v2;\n if (!v4) break;\n v2 = v4;\n }\n } else {\n v2 = *a1;\n }\n if (a2 > 2) {\n v5 = a1 + 2;\n v6 = (long long)&a1[a2 - 3 + 3];\n do {\n v7 = *v5;\n if (*v5) {\n v8 = v2;\n do {\n v2 = v7;\n v7 = v8 % v7;\n v8 = v2;\n } while (v7);\n }\n ++v5;\n } while (v5 != (int *)v6);\n }\n return (unsigned int)v2;\n}" + }, + { + "index": 46, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int data[], int length) {\n for (int i = 0; i < length; i++) {\n for (int j = i + 1; j < length; j++) {\n if (data[i] == data[j]) {\n return false;\n }\n }\n }\n return true;\n}", + "test": "int main() {\n\n int data1[] = {1, 5, 7, 9};\n\n int data2[] = {2, 4, 5, 5, 7, 9};\n\n int data3[] = {1, 2, 3};\n\n int length1 = sizeof(data1) / sizeof(data1[0]);\n\n int length2 = sizeof(data2) / sizeof(data2[0]);\n\n int length3 = sizeof(data3) / sizeof(data3[0]);\n\n\n\n assert(func0(data1, length1) == true);\n\n assert(func0(data2, length2) == false);\n\n assert(func0(data3, length3) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11d3 \nmov -0x8(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x4(%rbp)\njmp 11c7 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 11c3 \nmov $0x0,%eax\njmp 11e0 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 118c \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1181 \nmov $0x1,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\njmp short loc_11D3\nloc_1181:\nmov eax, [rbp+var_8]\nadd eax, 1\nmov [rbp+var_4], eax\njmp short loc_11C7\nloc_118C:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11C3\nmov eax, 0\njmp short loc_11E0\nloc_11C3:\nadd [rbp+var_4], 1\nloc_11C7:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_118C\nadd [rbp+var_8], 1\nloc_11D3:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_1181\nmov eax, 1\nloc_11E0:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+14h] [rbp-8h]\n int j; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4LL * j + a1) )\n return 0LL;\n }\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\njmp short loc_11D3\nloc_1181:\nmov eax, [rbp+var_8]\nadd eax, 1\nmov [rbp+var_4], eax\njmp short loc_11C7\nloc_118C:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11C3\nmov eax, 0\njmp short loc_11E0\nloc_11C3:\nadd [rbp+var_4], 1\nloc_11C7:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_118C\nadd [rbp+var_8], 1\nloc_11D3:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_1181\nmov eax, 1\nloc_11E0:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int i; // [rsp+14h] [rbp-8h]\n int j; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4LL * j + a1) )\n return 0LL;\n }\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int i;\n int j;\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if (*(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4LL * j + a1))\n return 0LL;\n }\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int i;\n int j;\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if (*(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4LL * j + a1))\n return 0LL;\n }\n }\n return 1LL;\n}" + }, + { + "index": 46, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int data[], int length) {\n for (int i = 0; i < length; i++) {\n for (int j = i + 1; j < length; j++) {\n if (data[i] == data[j]) {\n return false;\n }\n }\n }\n return true;\n}", + "test": "int main() {\n\n int data1[] = {1, 5, 7, 9};\n\n int data2[] = {2, 4, 5, 5, 7, 9};\n\n int data3[] = {1, 2, 3};\n\n int length1 = sizeof(data1) / sizeof(data1[0]);\n\n int length2 = sizeof(data2) / sizeof(data2[0]);\n\n int length3 = sizeof(data3) / sizeof(data3[0]);\n\n\n\n assert(func0(data1, length1) == true);\n\n assert(func0(data2, length2) == false);\n\n assert(func0(data3, length3) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 119d \nlea -0x1(%rsi),%r8d\nadd $0x1,%r8\nmov $0x1,%ecx\ncmp %r8,%rcx\nje 11a3 \nmov -0x4(%rdi,%rcx,4),%edx\nmov %rcx,%rax\ncmp (%rdi,%rax,4),%edx\nje 11a9 \nadd $0x1,%rax\ncmp %eax,%esi\njg 118a \nadd $0x1,%rcx\njmp 117e \nmov $0x1,%eax\nretq\nmov $0x1,%eax\nretq\nmov $0x0,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11A9\nmov r8d, esi\nmovsxd r9, esi\nmov ecx, 1\nloc_117C:\ncmp rcx, r8\njz short loc_11AF\nmov edx, [rdi+rcx*4-4]\nmov rax, rcx\nloc_1188:\ncmp edx, [rdi+rax*4]\njz short loc_11B5\nadd rax, 1\ncmp esi, eax\njg short loc_1188\nlea rax, [rcx+1]\ncmp rcx, r9\njz short loc_11A3\nmov rcx, rax\njmp short loc_117C\nloc_11A3:\nmov eax, 1\nretn\nloc_11A9:\nmov eax, 1\nretn\nloc_11AF:\nmov eax, 1\nretn\nloc_11B5:\nmov eax, 0\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // rcx\n __int64 v3; // rax\n\n if ( a2 <= 0 )\n return 1LL;\n v2 = 1LL;\n while ( 2 )\n {\n if ( v2 == a2 )\n return 1LL;\n v3 = v2;\n do\n {\n if ( *(_DWORD *)(a1 + 4 * v2 - 4) == *(_DWORD *)(a1 + 4 * v3) )\n return 0LL;\n ++v3;\n }\n while ( a2 > (int)v3 );\n if ( v2 != a2 )\n {\n ++v2;\n continue;\n }\n break;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11A9\nmov r8d, esi\nmovsxd r9, esi\nmov ecx, 1\nloc_117C:\ncmp rcx, r8\njz short loc_11AF\nmov edx, [rdi+rcx*4-4]\nmov rax, rcx\nloc_1188:\ncmp edx, [rdi+rax*4]\njz short loc_11B5\nadd rax, 1\ncmp esi, eax\njg short loc_1188\nlea rax, [rcx+1]\ncmp rcx, r9\njz short loc_11A3\nmov rcx, rax\njmp short loc_117C\nloc_11A3:\nmov eax, 1\nretn\nloc_11A9:\nmov eax, 1\nretn\nloc_11AF:\nmov eax, 1\nretn\nloc_11B5:\nmov eax, 0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n __int64 v2; // rcx\n __int64 v3; // rax\n\n if ( a2 <= 0 )\n return 1LL;\n v2 = 1LL;\n while ( 2 )\n {\n if ( v2 == a2 )\n return 1LL;\n v3 = v2;\n do\n {\n if ( *(_DWORD *)(a1 + 4 * v2 - 4) == *(_DWORD *)(a1 + 4 * v3) )\n return 0LL;\n ++v3;\n }\n while ( a2 > (int)v3 );\n if ( v2 != a2 )\n {\n ++v2;\n continue;\n }\n break;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n long long v2;\n long long v3;\n if (a2 <= 0) return 1LL;\n v2 = 1LL;\n while (2) {\n if (v2 == a2) return 1LL;\n v3 = v2;\n do {\n if (*(uint32_t *)(a1 + 4 * v2 - 4) == *(uint32_t *)(a1 + 4 * v3))\n return 0LL;\n ++v3;\n } while (a2 > (int)v3);\n if (v2 != a2) {\n ++v2;\n continue;\n }\n break;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n long long v3;\n if (a2 <= 0) return 1LL;\n v2 = 1LL;\n while (2) {\n if (v2 == a2) return 1LL;\n v3 = v2;\n do {\n if (*(uint32_t *)(a1 + 4 * v2 - 4) == *(uint32_t *)(a1 + 4 * v3))\n return 0LL;\n ++v3;\n } while (a2 > (int)v3);\n if (v2 != a2) {\n ++v2;\n continue;\n }\n break;\n }\n return 1LL;\n}" + }, + { + "index": 46, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int data[], int length) {\n for (int i = 0; i < length; i++) {\n for (int j = i + 1; j < length; j++) {\n if (data[i] == data[j]) {\n return false;\n }\n }\n }\n return true;\n}", + "test": "int main() {\n\n int data1[] = {1, 5, 7, 9};\n\n int data2[] = {2, 4, 5, 5, 7, 9};\n\n int data3[] = {1, 2, 3};\n\n int length1 = sizeof(data1) / sizeof(data1[0]);\n\n int length2 = sizeof(data2) / sizeof(data2[0]);\n\n int length3 = sizeof(data3) / sizeof(data3[0]);\n\n\n\n assert(func0(data1, length1) == true);\n\n assert(func0(data2, length2) == false);\n\n assert(func0(data3, length3) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 12f9 \nlea -0x1(%rsi),%r8d\nmov $0x1,%ecx\nadd $0x1,%r8\ncmp %r8,%rcx\nje 12f9 \nmov -0x4(%rdi,%rcx,4),%edx\nmov %rcx,%rax\njmp 12e0 \nnopl 0x0(%rax,%rax,1)\nadd $0x1,%rax\ncmp %eax,%esi\njle 12f0 \ncmp (%rdi,%rax,4),%edx\njne 12d8 \nxor %eax,%eax\nretq\nnopl 0x0(%rax,%rax,1)\nadd $0x1,%rcx\ncmp %r8,%rcx\njne 12ca \nmov $0x1,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_12B9\nmov r8d, esi\nmov ecx, 1\ncmp rcx, r8\njz short loc_12B9\nloc_1295:\nmov edx, [rdi+rcx*4-4]\nmov rax, rcx\njmp short loc_12A8\nloc_12A0:\nadd rax, 1\ncmp esi, eax\njle short loc_12B0\nloc_12A8:\ncmp edx, [rdi+rax*4]\njnz short loc_12A0\nxor eax, eax\nretn\nloc_12B0:\nadd rcx, 1\ncmp rcx, r8\njnz short loc_1295\nloc_12B9:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 i; // rcx\n __int64 v3; // rax\n\n if ( a2 > 0 )\n {\n for ( i = 1LL; i != a2; ++i )\n {\n v3 = i;\n do\n {\n if ( *(_DWORD *)(a1 + 4 * i - 4) == *(_DWORD *)(a1 + 4 * v3) )\n return 0LL;\n ++v3;\n }\n while ( a2 > (int)v3 );\n }\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\ntest esi, esi\njle short loc_12B9\nmov r8d, esi\nmov ecx, 1\ncmp rcx, r8\njz short loc_12B9\nloc_1295:\nmov edx, [rdi+rcx*4-4]\nmov rax, rcx\njmp short loc_12A8\nloc_12A0:\nadd rax, 1\ncmp esi, eax\njle short loc_12B0\nloc_12A8:\ncmp edx, [rdi+rax*4]\njnz short loc_12A0\nxor eax, eax\nretn\nloc_12B0:\nadd rcx, 1\ncmp rcx, r8\njnz short loc_1295\nloc_12B9:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1280(__int64 a1, int a2)\n{\n __int64 i; // rcx\n __int64 v3; // rax\n\n if ( a2 > 0 )\n {\n for ( i = 1LL; i != a2; ++i )\n {\n v3 = i;\n do\n {\n if ( *(_DWORD *)(a1 + 4 * i - 4) == *(_DWORD *)(a1 + 4 * v3) )\n return 0LL;\n ++v3;\n }\n while ( a2 > (int)v3 );\n }\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1280(long long a1, int a2) {\n long long i;\n long long v3;\n if (a2 > 0) {\n for (i = 1LL; i != a2; ++i) {\n v3 = i;\n do {\n if (*(uint32_t *)(a1 + 4 * i - 4) == *(uint32_t *)(a1 + 4 * v3))\n return 0LL;\n ++v3;\n } while (a2 > (int)v3);\n }\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long i;\n long long v3;\n if (a2 > 0) {\n for (i = 1LL; i != a2; ++i) {\n v3 = i;\n do {\n if (*(uint32_t *)(a1 + 4 * i - 4) == *(uint32_t *)(a1 + 4 * v3))\n return 0LL;\n ++v3;\n } while (a2 > (int)v3);\n }\n }\n return 1LL;\n}" + }, + { + "index": 47, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int A, int B) {\n int variable = 1;\n if (A == B) {\n return 1;\n } else if ((B - A) >= 5) {\n return 0;\n } else {\n for (int i = A + 1; i <= B; i++) {\n variable = (variable * (i % 10)) % 10;\n }\n return variable % 10;\n }\n}", + "test": "int main() {\n\n assert(func0(2, 4) == 2);\n\n assert(func0(6, 8) == 6);\n\n assert(func0(1, 2) == 2);\n\n assert(func0(3, 7) == 0);\n\n assert(func0(20, 23) == 6);\n\n assert(func0(1021, 1024) == 4);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmovl $0x1,-0x8(%rbp)\nmov -0x14(%rbp),%eax\ncmp -0x18(%rbp),%eax\njne 1170 \nmov $0x1,%edx\njmpq 1226 \nmov -0x18(%rbp),%eax\nsub -0x14(%rbp),%eax\ncmp $0x4,%eax\njle 1185 \nmov $0x0,%edx\njmpq 1226 \nmov -0x14(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x4(%rbp)\njmp 11f4 \nmov -0x4(%rbp),%ecx\nmovslq %ecx,%rax\nimul $0x66666667,%rax,%rax\nshr $0x20,%rax\nmov %eax,%edx\nsar $0x2,%edx\nmov %ecx,%eax\nsar $0x1f,%eax\nsub %eax,%edx\nmov %edx,%eax\nshl $0x2,%eax\nadd %edx,%eax\nadd %eax,%eax\nsub %eax,%ecx\nmov %ecx,%edx\nimul -0x8(%rbp),%edx\nmovslq %edx,%rax\nimul $0x66666667,%rax,%rax\nshr $0x20,%rax\nmov %eax,%ecx\nsar $0x2,%ecx\nmov %edx,%eax\nsar $0x1f,%eax\nsub %eax,%ecx\nmov %ecx,%eax\nmov %eax,-0x8(%rbp)\nmov -0x8(%rbp),%ecx\nmov %ecx,%eax\nshl $0x2,%eax\nadd %ecx,%eax\nadd %eax,%eax\nsub %eax,%edx\nmov %edx,%eax\nmov %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x18(%rbp),%eax\njle 1190 \nmov -0x8(%rbp),%ecx\nmovslq %ecx,%rax\nimul $0x66666667,%rax,%rax\nshr $0x20,%rax\nmov %eax,%edx\nsar $0x2,%edx\nmov %ecx,%eax\nsar $0x1f,%eax\nsub %eax,%edx\nmov %edx,%eax\nshl $0x2,%eax\nadd %edx,%eax\nadd %eax,%eax\nsub %eax,%ecx\nmov %ecx,%edx\nmov %edx,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_8], 1\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_18]\njnz short loc_1170\nmov edx, 1\njmp loc_1220\nloc_1170:\nmov eax, [rbp+var_18]\nsub eax, [rbp+var_14]\ncmp eax, 4\njle short loc_1185\nmov edx, 0\njmp loc_1220\nloc_1185:\nmov eax, [rbp+var_14]\nadd eax, 1\nmov [rbp+var_4], eax\njmp short loc_11EE\nloc_1190:\nmov ecx, [rbp+var_4]\nmovsxd rax, ecx\nimul rax, 66666667h\nshr rax, 20h\nmov edx, eax\nsar edx, 2\nmov eax, ecx\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nsub ecx, eax\nmov edx, ecx\nimul edx, [rbp+var_8]\nmovsxd rax, edx\nimul rax, 66666667h\nshr rax, 20h\nsar eax, 2\nmov ecx, edx\nsar ecx, 1Fh\nsub eax, ecx\nmov [rbp+var_8], eax\nmov ecx, [rbp+var_8]\nmov eax, ecx\nshl eax, 2\nadd eax, ecx\nadd eax, eax\nsub edx, eax\nmov [rbp+var_8], edx\nadd [rbp+var_4], 1\nloc_11EE:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_18]\njle short loc_1190\nmov ecx, [rbp+var_8]\nmovsxd rax, ecx\nimul rax, 66666667h\nshr rax, 20h\nmov edx, eax\nsar edx, 2\nmov eax, ecx\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nsub ecx, eax\nmov edx, ecx\nloc_1220:\nmov eax, edx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n int v4; // [rsp+10h] [rbp-8h]\n int i; // [rsp+14h] [rbp-4h]\n\n v4 = 1;\n if ( a1 == a2 )\n {\n return 1;\n }\n else if ( a2 - a1 <= 4 )\n {\n for ( i = a1 + 1; i <= a2; ++i )\n v4 = v4 * (i % 10) % 10;\n return (unsigned int)(v4 % 10);\n }\n else\n {\n return 0;\n }\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_8], 1\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_18]\njnz short loc_1170\nmov edx, 1\njmp loc_1220\nloc_1170:\nmov eax, [rbp+var_18]\nsub eax, [rbp+var_14]\ncmp eax, 4\njle short loc_1185\nmov edx, 0\njmp loc_1220\nloc_1185:\nmov eax, [rbp+var_14]\nadd eax, 1\nmov [rbp+var_4], eax\njmp short loc_11EE\nloc_1190:\nmov ecx, [rbp+var_4]\nmovsxd rax, ecx\nimul rax, 66666667h\nshr rax, 20h\nmov edx, eax\nsar edx, 2\nmov eax, ecx\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nsub ecx, eax\nmov edx, ecx\nimul edx, [rbp+var_8]\nmovsxd rax, edx\nimul rax, 66666667h\nshr rax, 20h\nsar eax, 2\nmov ecx, edx\nsar ecx, 1Fh\nsub eax, ecx\nmov [rbp+var_8], eax\nmov ecx, [rbp+var_8]\nmov eax, ecx\nshl eax, 2\nadd eax, ecx\nadd eax, eax\nsub edx, eax\nmov [rbp+var_8], edx\nadd [rbp+var_4], 1\nloc_11EE:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_18]\njle short loc_1190\nmov ecx, [rbp+var_8]\nmovsxd rax, ecx\nimul rax, 66666667h\nshr rax, 20h\nmov edx, eax\nsar edx, 2\nmov eax, ecx\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nsub ecx, eax\nmov edx, ecx\nloc_1220:\nmov eax, edx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2)\n{\n int v4; // [rsp+10h] [rbp-8h]\n int i; // [rsp+14h] [rbp-4h]\n\n v4 = 1;\n if ( a1 == a2 )\n {\n return 1;\n }\n else if ( a2 - a1 <= 4 )\n {\n for ( i = a1 + 1; i <= a2; ++i )\n v4 = v4 * (i % 10) % 10;\n return (unsigned int)(v4 % 10);\n }\n else\n {\n return 0;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2) {\n int v4;\n int i;\n v4 = 1;\n if (a1 == a2) {\n return 1;\n } else if (a2 - a1 <= 4) {\n for (i = a1 + 1; i <= a2; ++i) v4 = v4 * (i % 10) % 10;\n return (unsigned int)(v4 % 10);\n } else {\n return 0;\n }\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n int v4;\n int i;\n v4 = 1;\n if (a1 == a2) {\n return 1;\n } else if (a2 - a1 <= 4) {\n for (i = a1 + 1; i <= a2; ++i) v4 = v4 * (i % 10) % 10;\n return (unsigned int)(v4 % 10);\n } else {\n return 0;\n }\n}" + }, + { + "index": 47, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int A, int B) {\n int variable = 1;\n if (A == B) {\n return 1;\n } else if ((B - A) >= 5) {\n return 0;\n } else {\n for (int i = A + 1; i <= B; i++) {\n variable = (variable * (i % 10)) % 10;\n }\n return variable % 10;\n }\n}", + "test": "int main() {\n\n assert(func0(2, 4) == 2);\n\n assert(func0(6, 8) == 6);\n\n assert(func0(1, 2) == 2);\n\n assert(func0(3, 7) == 0);\n\n assert(func0(20, 23) == 6);\n\n assert(func0(1021, 1024) == 4);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x1,%eax\ncmp %esi,%edi\nje 11dd \nmov %esi,%edx\nsub %edi,%edx\nmov $0x0,%eax\ncmp $0x4,%edx\njg 11dd \nadd $0x1,%edi\ncmp %edi,%esi\njl 11de \nadd $0x1,%esi\nmov $0x1,%edx\nmovslq %edi,%rax\nimul $0x66666667,%rax,%rax\nsar $0x22,%rax\nmov %edi,%ecx\nsar $0x1f,%ecx\nsub %ecx,%eax\nlea (%rax,%rax,4),%eax\nadd %eax,%eax\nmov %edi,%ecx\nsub %eax,%ecx\nmov %ecx,%eax\nimul %edx,%eax\nmovslq %eax,%rdx\nimul $0x66666667,%rdx,%rdx\nsar $0x22,%rdx\nmov %eax,%ecx\nsar $0x1f,%ecx\nsub %ecx,%edx\nlea (%rdx,%rdx,4),%edx\nadd %edx,%edx\nsub %edx,%eax\nmov %eax,%edx\nadd $0x1,%edi\ncmp %esi,%edi\njne 1177 \nmovslq %edx,%rax\nimul $0x66666667,%rax,%rax\nsar $0x22,%rax\nmov %edx,%ecx\nsar $0x1f,%ecx\nsub %ecx,%eax\nlea (%rax,%rax,4),%eax\nadd %eax,%eax\nsub %eax,%edx\nmov %edx,%eax\nretq\nmov $0x1,%edx\njmp 11bf \n", + "ida_asm": "func0:\nendbr64\nmov eax, 1\ncmp edi, esi\njz locret_11DB\nmov edx, esi\nsub edx, edi\nmov eax, 0\ncmp edx, 4\njg short locret_11DB\nlea ecx, [rdi+1]\ncmp esi, ecx\njl short loc_11DC\nlea edi, [rsi+1]\nmov edx, 1\nloc_1177:\nmovsxd rax, ecx\nimul rax, 66666667h\nsar rax, 22h\nmov esi, ecx\nsar esi, 1Fh\nsub eax, esi\nlea esi, [rax+rax*4]\nadd esi, esi\nmov eax, ecx\nsub eax, esi\nimul eax, edx\nmovsxd rdx, eax\nimul rdx, 66666667h\nsar rdx, 22h\nmov esi, eax\nsar esi, 1Fh\nsub edx, esi\nlea esi, [rdx+rdx*4]\nadd esi, esi\nsub eax, esi\nmov edx, eax\nadd ecx, 1\ncmp ecx, edi\njnz short loc_1177\nloc_11BD:\nmovsxd rax, edx\nimul rax, 66666667h\nsar rax, 22h\nmov ecx, edx\nsar ecx, 1Fh\nsub eax, ecx\nlea ecx, [rax+rax*4]\nadd ecx, ecx\nmov eax, edx\nsub eax, ecx\nlocret_11DB:\nretn\nloc_11DC:\nmov edx, 1\njmp short loc_11BD", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n __int64 result; // rax\n int v3; // ecx\n int v4; // edx\n\n result = 1LL;\n if ( a1 != a2 )\n {\n result = 0LL;\n if ( a2 - a1 <= 4 )\n {\n v3 = a1 + 1;\n if ( a2 < a1 + 1 )\n {\n v4 = 1;\n }\n else\n {\n v4 = 1;\n do\n {\n v4 = v4 * (v3 % 10) % 10;\n ++v3;\n }\n while ( v3 != a2 + 1 );\n }\n return (unsigned int)(v4 % 10);\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmov eax, 1\ncmp edi, esi\njz locret_11DB\nmov edx, esi\nsub edx, edi\nmov eax, 0\ncmp edx, 4\njg short locret_11DB\nlea ecx, [rdi+1]\ncmp esi, ecx\njl short loc_11DC\nlea edi, [rsi+1]\nmov edx, 1\nloc_1177:\nmovsxd rax, ecx\nimul rax, 66666667h\nsar rax, 22h\nmov esi, ecx\nsar esi, 1Fh\nsub eax, esi\nlea esi, [rax+rax*4]\nadd esi, esi\nmov eax, ecx\nsub eax, esi\nimul eax, edx\nmovsxd rdx, eax\nimul rdx, 66666667h\nsar rdx, 22h\nmov esi, eax\nsar esi, 1Fh\nsub edx, esi\nlea esi, [rdx+rdx*4]\nadd esi, esi\nsub eax, esi\nmov edx, eax\nadd ecx, 1\ncmp ecx, edi\njnz short loc_1177\nloc_11BD:\nmovsxd rax, edx\nimul rax, 66666667h\nsar rax, 22h\nmov ecx, edx\nsar ecx, 1Fh\nsub eax, ecx\nlea ecx, [rax+rax*4]\nadd ecx, ecx\nmov eax, edx\nsub eax, ecx\nlocret_11DB:\nretn\nloc_11DC:\nmov edx, 1\njmp short loc_11BD", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2)\n{\n __int64 result; // rax\n int v3; // ecx\n int v4; // edx\n\n result = 1LL;\n if ( a1 != a2 )\n {\n result = 0LL;\n if ( a2 - a1 <= 4 )\n {\n v3 = a1 + 1;\n if ( a2 < a1 + 1 )\n {\n v4 = 1;\n }\n else\n {\n v4 = 1;\n do\n {\n v4 = v4 * (v3 % 10) % 10;\n ++v3;\n }\n while ( v3 != a2 + 1 );\n }\n return (unsigned int)(v4 % 10);\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2) {\n long long result;\n int v3;\n int v4;\n result = 1LL;\n if (a1 != a2) {\n result = 0LL;\n if (a2 - a1 <= 4) {\n v3 = a1 + 1;\n if (a2 < a1 + 1) {\n v4 = 1;\n } else {\n v4 = 1;\n do {\n v4 = v4 * (v3 % 10) % 10;\n ++v3;\n } while (v3 != a2 + 1);\n }\n return (unsigned int)(v4 % 10);\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n long long result;\n int v3;\n int v4;\n result = 1LL;\n if (a1 != a2) {\n result = 0LL;\n if (a2 - a1 <= 4) {\n v3 = a1 + 1;\n if (a2 < a1 + 1) {\n v4 = 1;\n } else {\n v4 = 1;\n do {\n v4 = v4 * (v3 % 10) % 10;\n ++v3;\n } while (v3 != a2 + 1);\n }\n return (unsigned int)(v4 % 10);\n }\n }\n return result;\n}" + }, + { + "index": 47, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int A, int B) {\n int variable = 1;\n if (A == B) {\n return 1;\n } else if ((B - A) >= 5) {\n return 0;\n } else {\n for (int i = A + 1; i <= B; i++) {\n variable = (variable * (i % 10)) % 10;\n }\n return variable % 10;\n }\n}", + "test": "int main() {\n\n assert(func0(2, 4) == 2);\n\n assert(func0(6, 8) == 6);\n\n assert(func0(1, 2) == 2);\n\n assert(func0(3, 7) == 0);\n\n assert(func0(20, 23) == 6);\n\n assert(func0(1021, 1024) == 4);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ncmp %esi,%edi\nje 1330 \nmov %esi,%eax\nsub %edi,%eax\ncmp $0x4,%eax\njle 1328 \nxor %eax,%eax\nretq\nnopl 0x0(%rax)\njmpq 12a0 \nnopl (%rax)\nmov $0x1,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0_part_0:\nlea ecx, [rdi+1]\ncmp ecx, esi\njg short loc_1300\nlea edi, [rsi+1]\nmov eax, 1\nnop\nloc_12B0:\nmovsxd rdx, ecx\nmov esi, ecx\nimul rdx, 66666667h\nsar esi, 1Fh\nsar rdx, 22h\nsub edx, esi\nlea esi, [rdx+rdx*4]\nmov edx, ecx\nadd ecx, 1\nadd esi, esi\nsub edx, esi\nimul edx, eax\nmovsxd rax, edx\nmov esi, edx\nimul rax, 66666667h\nsar esi, 1Fh\nsar rax, 22h\nsub eax, esi\nlea esi, [rax+rax*4]\nmov eax, edx\nadd esi, esi\nsub eax, esi\ncmp ecx, edi\njnz short loc_12B0\nretn\nloc_1300:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0_part_0(int a1, int a2)\n{\n int v2; // ecx\n int v3; // edi\n __int64 result; // rax\n int v5; // esi\n int v6; // edx\n\n v2 = a1 + 1;\n if ( a1 + 1 > a2 )\n return 1LL;\n v3 = a2 + 1;\n LODWORD(result) = 1;\n do\n {\n v5 = 5 * (v2 / 10);\n v6 = v2++;\n result = (unsigned int)((int)result * (v6 - 2 * v5) % 10);\n }\n while ( v2 != v3 );\n return result;\n}", + "ida_strip_asm": "sub_12A0:\nlea ecx, [rdi+1]\ncmp ecx, esi\njg short loc_1300\nlea edi, [rsi+1]\nmov eax, 1\nnop\nloc_12B0:\nmovsxd rdx, ecx\nmov esi, ecx\nimul rdx, 66666667h\nsar esi, 1Fh\nsar rdx, 22h\nsub edx, esi\nlea esi, [rdx+rdx*4]\nmov edx, ecx\nadd ecx, 1\nadd esi, esi\nsub edx, esi\nimul edx, eax\nmovsxd rax, edx\nmov esi, edx\nimul rax, 66666667h\nsar esi, 1Fh\nsar rax, 22h\nsub eax, esi\nlea esi, [rax+rax*4]\nmov eax, edx\nadd esi, esi\nsub eax, esi\ncmp ecx, edi\njnz short loc_12B0\nretn\nloc_1300:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12A0(int a1, int a2)\n{\n int v2; // ecx\n int v3; // edi\n __int64 result; // rax\n int v5; // esi\n int v6; // edx\n\n v2 = a1 + 1;\n if ( a1 + 1 > a2 )\n return 1LL;\n v3 = a2 + 1;\n LODWORD(result) = 1;\n do\n {\n v5 = 5 * (v2 / 10);\n v6 = v2++;\n result = (unsigned int)((int)result * (v6 - 2 * v5) % 10);\n }\n while ( v2 != v3 );\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12A0(int a1, int a2) {\n int v2;\n int v3;\n long long result;\n int v5;\n int v6;\n v2 = a1 + 1;\n if (a1 + 1 > a2) return 1LL;\n v3 = a2 + 1;\n LODWORD(result) = 1;\n do {\n v5 = 5 * (v2 / 10);\n v6 = v2++;\n result = (unsigned int)((int)result * (v6 - 2 * v5) % 10);\n } while (v2 != v3);\n return result;\n}", + "ida_pseudo_norm": "long long func0_part_0(int a1, int a2) {\n int v2;\n int v3;\n long long result;\n int v5;\n int v6;\n v2 = a1 + 1;\n if (a1 + 1 > a2) return 1LL;\n v3 = a2 + 1;\n LODWORD(result) = 1;\n do {\n v5 = 5 * (v2 / 10);\n v6 = v2++;\n result = (unsigned int)((int)result * (v6 - 2 * v5) % 10);\n } while (v2 != v3);\n return result;\n}" + }, + { + "index": 47, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int A, int B) {\n int variable = 1;\n if (A == B) {\n return 1;\n } else if ((B - A) >= 5) {\n return 0;\n } else {\n for (int i = A + 1; i <= B; i++) {\n variable = (variable * (i % 10)) % 10;\n }\n return variable % 10;\n }\n}", + "test": "int main() {\n\n assert(func0(2, 4) == 2);\n\n assert(func0(6, 8) == 6);\n\n assert(func0(1, 2) == 2);\n\n assert(func0(3, 7) == 0);\n\n assert(func0(20, 23) == 6);\n\n assert(func0(1021, 1024) == 4);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x1,%eax\ncmp %esi,%edi\nje 1395 \nmov %esi,%edx\nxor %eax,%eax\nsub %edi,%edx\ncmp $0x4,%edx\njg 1395 \nadd $0x1,%edi\ncmp %edi,%esi\njl 1390 \nadd $0x1,%esi\nmov $0x1,%eax\nnopw 0x0(%rax,%rax,1)\nmovslq %edi,%rdx\nmov %edi,%ecx\nimul $0x66666667,%rdx,%rdx\nsar $0x1f,%ecx\nsar $0x22,%rdx\nsub %ecx,%edx\nmov %edi,%ecx\nadd $0x1,%edi\nlea (%rdx,%rdx,4),%edx\nadd %edx,%edx\nsub %edx,%ecx\nmov %ecx,%edx\nimul %eax,%edx\nmovslq %edx,%rax\nmov %edx,%ecx\nimul $0x66666667,%rax,%rax\nsar $0x1f,%ecx\nsar $0x22,%rax\nsub %ecx,%eax\nlea (%rax,%rax,4),%eax\nadd %eax,%eax\nsub %eax,%edx\nmov %edx,%eax\ncmp %esi,%edi\njne 1340 \nretq\nnopl 0x0(%rax)\nmov $0x1,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0_part_0:\nlea ecx, [rdi+1]\ncmp ecx, esi\njg short loc_1300\nlea edi, [rsi+1]\nmov eax, 1\nnop\nloc_12B0:\nmovsxd rdx, ecx\nmov esi, ecx\nimul rdx, 66666667h\nsar esi, 1Fh\nsar rdx, 22h\nsub edx, esi\nlea esi, [rdx+rdx*4]\nmov edx, ecx\nadd ecx, 1\nadd esi, esi\nsub edx, esi\nimul edx, eax\nmovsxd rax, edx\nmov esi, edx\nimul rax, 66666667h\nsar esi, 1Fh\nsar rax, 22h\nsub eax, esi\nlea esi, [rax+rax*4]\nmov eax, edx\nadd esi, esi\nsub eax, esi\ncmp ecx, edi\njnz short loc_12B0\nretn\nloc_1300:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0_part_0(int a1, int a2)\n{\n int v2; // ecx\n int v3; // edi\n __int64 result; // rax\n int v5; // esi\n int v6; // edx\n\n v2 = a1 + 1;\n if ( a1 + 1 > a2 )\n return 1LL;\n v3 = a2 + 1;\n LODWORD(result) = 1;\n do\n {\n v5 = 5 * (v2 / 10);\n v6 = v2++;\n result = (unsigned int)((int)result * (v6 - 2 * v5) % 10);\n }\n while ( v2 != v3 );\n return result;\n}", + "ida_strip_asm": "sub_12A0:\nlea ecx, [rdi+1]\ncmp ecx, esi\njg short loc_1300\nlea edi, [rsi+1]\nmov eax, 1\nnop\nloc_12B0:\nmovsxd rdx, ecx\nmov esi, ecx\nimul rdx, 66666667h\nsar esi, 1Fh\nsar rdx, 22h\nsub edx, esi\nlea esi, [rdx+rdx*4]\nmov edx, ecx\nadd ecx, 1\nadd esi, esi\nsub edx, esi\nimul edx, eax\nmovsxd rax, edx\nmov esi, edx\nimul rax, 66666667h\nsar esi, 1Fh\nsar rax, 22h\nsub eax, esi\nlea esi, [rax+rax*4]\nmov eax, edx\nadd esi, esi\nsub eax, esi\ncmp ecx, edi\njnz short loc_12B0\nretn\nloc_1300:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12A0(int a1, int a2)\n{\n int v2; // ecx\n int v3; // edi\n __int64 result; // rax\n int v5; // esi\n int v6; // edx\n\n v2 = a1 + 1;\n if ( a1 + 1 > a2 )\n return 1LL;\n v3 = a2 + 1;\n LODWORD(result) = 1;\n do\n {\n v5 = 5 * (v2 / 10);\n v6 = v2++;\n result = (unsigned int)((int)result * (v6 - 2 * v5) % 10);\n }\n while ( v2 != v3 );\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12A0(int a1, int a2) {\n int v2;\n int v3;\n long long result;\n int v5;\n int v6;\n v2 = a1 + 1;\n if (a1 + 1 > a2) return 1LL;\n v3 = a2 + 1;\n LODWORD(result) = 1;\n do {\n v5 = 5 * (v2 / 10);\n v6 = v2++;\n result = (unsigned int)((int)result * (v6 - 2 * v5) % 10);\n } while (v2 != v3);\n return result;\n}", + "ida_pseudo_norm": "long long func0_part_0(int a1, int a2) {\n int v2;\n int v3;\n long long result;\n int v5;\n int v6;\n v2 = a1 + 1;\n if (a1 + 1 > a2) return 1LL;\n v3 = a2 + 1;\n LODWORD(result) = 1;\n do {\n v5 = 5 * (v2 / 10);\n v6 = v2++;\n result = (unsigned int)((int)result * (v6 - 2 * v5) % 10);\n } while (v2 != v3);\n return result;\n}" + }, + { + "index": 48, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int count = 0;\n int res = 0;\n int temp = n;\n while (temp > 0) {\n if (count % 2 == 0) {\n res |= (1 << count);\n }\n count += 1;\n temp >>= 1;\n }\n return (n | res);\n}", + "test": "int main() {\n\n assert(func0(10) == 15);\n\n assert(func0(20) == 21);\n\n assert(func0(30) == 31);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\nmov -0x14(%rbp),%eax\nmov %eax,-0x4(%rbp)\njmp 11ac \nmov -0xc(%rbp),%eax\nand $0x1,%eax\ntest %eax,%eax\njne 11a5 \nmov -0xc(%rbp),%eax\nmov $0x1,%edx\nmov %eax,%ecx\nshl %cl,%edx\nmov %edx,%eax\nor %eax,-0x8(%rbp)\naddl $0x1,-0xc(%rbp)\nsarl -0x4(%rbp)\ncmpl $0x0,-0x4(%rbp)\njg 118a \nmov -0x14(%rbp),%eax\nor -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\nmov eax, [rbp+var_14]\nmov [rbp+var_4], eax\njmp short loc_11AC\nloc_118A:\nmov eax, [rbp+var_C]\nand eax, 1\ntest eax, eax\njnz short loc_11A5\nmov eax, [rbp+var_C]\nmov edx, 1\nmov ecx, eax\nshl edx, cl\nmov eax, edx\nor [rbp+var_8], eax\nloc_11A5:\nadd [rbp+var_C], 1\nsar [rbp+var_4], 1\nloc_11AC:\ncmp [rbp+var_4], 0\njg short loc_118A\nmov eax, [rbp+var_14]\nor eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n char v2; // [rsp+8h] [rbp-Ch]\n int v3; // [rsp+Ch] [rbp-8h]\n int i; // [rsp+10h] [rbp-4h]\n\n v2 = 0;\n v3 = 0;\n for ( i = a1; i > 0; i >>= 1 )\n {\n if ( (v2 & 1) == 0 )\n v3 |= 1 << v2;\n ++v2;\n }\n return v3 | (unsigned int)a1;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\nmov eax, [rbp+var_14]\nmov [rbp+var_4], eax\njmp short loc_11AC\nloc_118A:\nmov eax, [rbp+var_C]\nand eax, 1\ntest eax, eax\njnz short loc_11A5\nmov eax, [rbp+var_C]\nmov edx, 1\nmov ecx, eax\nshl edx, cl\nmov eax, edx\nor [rbp+var_8], eax\nloc_11A5:\nadd [rbp+var_C], 1\nsar [rbp+var_4], 1\nloc_11AC:\ncmp [rbp+var_4], 0\njg short loc_118A\nmov eax, [rbp+var_14]\nor eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n char v2; // [rsp+8h] [rbp-Ch]\n int v3; // [rsp+Ch] [rbp-8h]\n int i; // [rsp+10h] [rbp-4h]\n\n v2 = 0;\n v3 = 0;\n for ( i = a1; i > 0; i >>= 1 )\n {\n if ( (v2 & 1) == 0 )\n v3 |= 1 << v2;\n ++v2;\n }\n return v3 | (unsigned int)a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n char v2;\n int v3;\n int i;\n v2 = 0;\n v3 = 0;\n for (i = a1; i > 0; i >>= 1) {\n if ((v2 & 1) == 0) v3 |= 1 << v2;\n ++v2;\n }\n return v3 | (unsigned int)a1;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n char v2;\n int v3;\n int i;\n v2 = 0;\n v3 = 0;\n for (i = a1; i > 0; i >>= 1) {\n if ((v2 & 1) == 0) v3 |= 1 << v2;\n ++v2;\n }\n return v3 | (unsigned int)a1;\n}" + }, + { + "index": 48, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int count = 0;\n int res = 0;\n int temp = n;\n while (temp > 0) {\n if (count % 2 == 0) {\n res |= (1 << count);\n }\n count += 1;\n temp >>= 1;\n }\n return (n | res);\n}", + "test": "int main() {\n\n assert(func0(10) == 15);\n\n assert(func0(20) == 21);\n\n assert(func0(30) == 31);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\njle 119c \nmov %edi,%edx\nmov $0x0,%eax\nmov $0x0,%ecx\nmov $0x1,%r8d\njmp 118e \nadd $0x1,%ecx\nsar %edx\ntest %edx,%edx\njle 11a1 \ntest $0x1,%cl\njne 1185 \nmov %r8d,%esi\nshl %cl,%esi\nor %esi,%eax\njmp 1185 \nmov $0x0,%eax\nor %edi,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov eax, edi\ntest edi, edi\njle short loc_119F\nmov edx, edi\nmov esi, 0\nmov ecx, 0\nmov edi, 1\njmp short loc_118F\nloc_1186:\nadd ecx, 1\nsar edx, 1\ntest edx, edx\njle short loc_11A4\nloc_118F:\ntest cl, 1\njnz short loc_1186\nmov r8d, edi\nshl r8d, cl\nor esi, r8d\njmp short loc_1186\nloc_119F:\nmov esi, 0\nloc_11A4:\nor eax, esi\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // edx\n int v2; // esi\n char v3; // cl\n\n if ( a1 <= 0 )\n {\n v2 = 0;\n }\n else\n {\n v1 = a1;\n v2 = 0;\n v3 = 0;\n do\n {\n if ( (v3 & 1) == 0 )\n v2 |= 1 << v3;\n ++v3;\n v1 >>= 1;\n }\n while ( v1 > 0 );\n }\n return v2 | (unsigned int)a1;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov eax, edi\ntest edi, edi\njle short loc_119F\nmov edx, edi\nmov esi, 0\nmov ecx, 0\nmov edi, 1\njmp short loc_118F\nloc_1186:\nadd ecx, 1\nsar edx, 1\ntest edx, edx\njle short loc_11A4\nloc_118F:\ntest cl, 1\njnz short loc_1186\nmov r8d, edi\nshl r8d, cl\nor esi, r8d\njmp short loc_1186\nloc_119F:\nmov esi, 0\nloc_11A4:\nor eax, esi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n int v1; // edx\n int v2; // esi\n char v3; // cl\n\n if ( a1 <= 0 )\n {\n v2 = 0;\n }\n else\n {\n v1 = a1;\n v2 = 0;\n v3 = 0;\n do\n {\n if ( (v3 & 1) == 0 )\n v2 |= 1 << v3;\n ++v3;\n v1 >>= 1;\n }\n while ( v1 > 0 );\n }\n return v2 | (unsigned int)a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n int v1;\n int v2;\n char v3;\n if (a1 <= 0) {\n v2 = 0;\n } else {\n v1 = a1;\n v2 = 0;\n v3 = 0;\n do {\n if ((v3 & 1) == 0) v2 |= 1 << v3;\n ++v3;\n v1 >>= 1;\n } while (v1 > 0);\n }\n return v2 | (unsigned int)a1;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v2;\n char v3;\n if (a1 <= 0) {\n v2 = 0;\n } else {\n v1 = a1;\n v2 = 0;\n v3 = 0;\n do {\n if ((v3 & 1) == 0) v2 |= 1 << v3;\n ++v3;\n v1 >>= 1;\n } while (v1 > 0);\n }\n return v2 | (unsigned int)a1;\n}" + }, + { + "index": 48, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int count = 0;\n int res = 0;\n int temp = n;\n while (temp > 0) {\n if (count % 2 == 0) {\n res |= (1 << count);\n }\n count += 1;\n temp >>= 1;\n }\n return (n | res);\n}", + "test": "int main() {\n\n assert(func0(10) == 15);\n\n assert(func0(20) == 21);\n\n assert(func0(30) == 31);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\njle 11a0 \nmov %edi,%edx\nxor %eax,%eax\nxor %ecx,%ecx\nmov $0x1,%r8d\nnopl 0x0(%rax)\ntest $0x1,%cl\njne 1194 \nmov %r8d,%esi\nshl %cl,%esi\nor %esi,%eax\nadd $0x1,%ecx\nsar %edx\njne 1188 \nor %edi,%eax\nretq\nxchg %ax,%ax\nmov %edi,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njle short loc_1258\nmov edx, edi\nxor esi, esi\nxor ecx, ecx\nmov eax, 1\nnop dword ptr [rax+rax+00h]\nloc_1238:\ntest cl, 1\njnz short loc_1246\nmov r8d, eax\nshl r8d, cl\nor esi, r8d\nloc_1246:\nadd ecx, 1\nsar edx, 1\njnz short loc_1238\nmov eax, edi\nor eax, esi\nretn\nloc_1258:\nmov eax, edi\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // edx\n int v2; // esi\n char v3; // cl\n\n if ( a1 <= 0 )\n return (unsigned int)a1;\n v1 = a1;\n v2 = 0;\n v3 = 0;\n do\n {\n if ( (v3 & 1) == 0 )\n v2 |= 1 << v3;\n ++v3;\n v1 >>= 1;\n }\n while ( v1 );\n return v2 | (unsigned int)a1;\n}", + "ida_strip_asm": "sub_1220:\nendbr64\ntest edi, edi\njle short loc_1258\nmov edx, edi\nxor esi, esi\nxor ecx, ecx\nmov eax, 1\nnop dword ptr [rax+rax+00h]\nloc_1238:\ntest cl, 1\njnz short loc_1246\nmov r8d, eax\nshl r8d, cl\nor esi, r8d\nloc_1246:\nadd ecx, 1\nsar edx, 1\njnz short loc_1238\nmov eax, edi\nor eax, esi\nretn\nloc_1258:\nmov eax, edi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1220(int a1)\n{\n int v1; // edx\n int v2; // esi\n char v3; // cl\n\n if ( a1 <= 0 )\n return (unsigned int)a1;\n v1 = a1;\n v2 = 0;\n v3 = 0;\n do\n {\n if ( (v3 & 1) == 0 )\n v2 |= 1 << v3;\n ++v3;\n v1 >>= 1;\n }\n while ( v1 );\n return v2 | (unsigned int)a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1220(int a1) {\n int v1;\n int v2;\n char v3;\n if (a1 <= 0) return (unsigned int)a1;\n v1 = a1;\n v2 = 0;\n v3 = 0;\n do {\n if ((v3 & 1) == 0) v2 |= 1 << v3;\n ++v3;\n v1 >>= 1;\n } while (v1);\n return v2 | (unsigned int)a1;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v2;\n char v3;\n if (a1 <= 0) return (unsigned int)a1;\n v1 = a1;\n v2 = 0;\n v3 = 0;\n do {\n if ((v3 & 1) == 0) v2 |= 1 << v3;\n ++v3;\n v1 >>= 1;\n } while (v1);\n return v2 | (unsigned int)a1;\n}" + }, + { + "index": 49, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int nums[][4], int rowCount, int N, int* result) {\n for (int i = 0; i < rowCount; i++) {\n result[i] = nums[i][N];\n }\n return result;\n}", + "test": "int main() {\n\n int nums1[][4] = {{1, 2, 3, 2}, {4, 5, 6, 2}, {7, 1, 9, 5}};\n\n int nums2[][4] = {{1, 2, 3, 2}, {4, 5, 6, 2}, {7, 1, 9, 5}};\n\n int nums3[][4] = {{1, 2, 3, 2}, {4, 5, 6, 2}, {7, 1, 9, 5}};\n\n int result1[3], result2[3], result3[3];\n\n int expected1[3] = {1, 4, 7};\n\n int expected2[3] = {3, 6, 9};\n\n int expected3[3] = {2, 5, 1};\n\n\n\n func0(nums1, 3, 0, result1);\n\n func0(nums2, 3, 2, result2);\n\n func0(nums3, 3, 1, result3);\n\n \n\n for (int i = 0; i < 3; i++) {\n\n assert(result1[i] == expected1[i]);\n\n assert(result2[i] == expected2[i]);\n\n assert(result3[i] == expected3[i]);\n\n }\n\n \n\n printf(\"All tests passed!\\n\");\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmov %rcx,-0x28(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11de \nmov -0x4(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rax,%rdx\nmov -0x20(%rbp),%eax\ncltq\nmov (%rcx,%rax,4),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11a8 \nmov -0x28(%rbp),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_28], rcx\nmov [rbp+var_4], 0\njmp short loc_11DE\nloc_11A8:\nmov eax, [rbp+var_4]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov eax, [rbp+var_20]\ncdqe\nmov eax, [rcx+rax*4]\nmov [rdx], eax\nadd [rbp+var_4], 1\nloc_11DE:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11A8\nmov rax, [rbp+var_28]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3, __int64 a4)\n{\n int i; // [rsp+24h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n *(_DWORD *)(a4 + 4LL * i) = *(_DWORD *)(16LL * i + a1 + 4LL * a3);\n return a4;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_28], rcx\nmov [rbp+var_4], 0\njmp short loc_11DE\nloc_11A8:\nmov eax, [rbp+var_4]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov eax, [rbp+var_20]\ncdqe\nmov eax, [rcx+rax*4]\nmov [rdx], eax\nadd [rbp+var_4], 1\nloc_11DE:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11A8\nmov rax, [rbp+var_28]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2, int a3, __int64 a4)\n{\n int i; // [rsp+24h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n *(_DWORD *)(a4 + 4LL * i) = *(_DWORD *)(16LL * i + a1 + 4LL * a3);\n return a4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2, int a3, long long a4) {\n int i;\n for (i = 0; i < a2; ++i)\n *(uint32_t *)(a4 + 4LL * i) = *(uint32_t *)(16LL * i + a1 + 4LL * a3);\n return a4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3, long long a4) {\n int i;\n for (i = 0; i < a2; ++i)\n *(uint32_t *)(a4 + 4LL * i) = *(uint32_t *)(16LL * i + a1 + 4LL * a3);\n return a4;\n}" + }, + { + "index": 49, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int nums[][4], int rowCount, int N, int* result) {\n for (int i = 0; i < rowCount; i++) {\n result[i] = nums[i][N];\n }\n return result;\n}", + "test": "int main() {\n\n int nums1[][4] = {{1, 2, 3, 2}, {4, 5, 6, 2}, {7, 1, 9, 5}};\n\n int nums2[][4] = {{1, 2, 3, 2}, {4, 5, 6, 2}, {7, 1, 9, 5}};\n\n int nums3[][4] = {{1, 2, 3, 2}, {4, 5, 6, 2}, {7, 1, 9, 5}};\n\n int result1[3], result2[3], result3[3];\n\n int expected1[3] = {1, 4, 7};\n\n int expected2[3] = {3, 6, 9};\n\n int expected3[3] = {2, 5, 1};\n\n\n\n func0(nums1, 3, 0, result1);\n\n func0(nums2, 3, 2, result2);\n\n func0(nums3, 3, 1, result3);\n\n \n\n for (int i = 0; i < 3; i++) {\n\n assert(result1[i] == expected1[i]);\n\n assert(result2[i] == expected2[i]);\n\n assert(result3[i] == expected3[i]);\n\n }\n\n \n\n printf(\"All tests passed!\\n\");\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rcx,%rax\ntest %esi,%esi\njle 11b7 \nmovslq %edx,%rdx\nlea (%rdi,%rdx,4),%rdi\nmov %rcx,%rdx\nlea -0x1(%rsi),%ecx\nlea 0x4(%rax,%rcx,4),%r8\nmov (%rdi),%esi\nmov %esi,(%rdx)\nadd $0x10,%rdi\nadd $0x4,%rdx\ncmp %r8,%rdx\njne 11a6 \nretq\n", + "ida_asm": "func0:\nendbr64\nmov rax, rcx\ntest esi, esi\njle short locret_11B6\nmovsxd rdx, edx\nlea rdi, [rdi+rdx*4]\nmov rdx, rcx\nmovsxd rsi, esi\nlea r8, [rcx+rsi*4]\nloc_11A5:\nmov esi, [rdi]\nmov [rdx], esi\nadd rdi, 10h\nadd rdx, 4\ncmp rdx, r8\njnz short loc_11A5\nlocret_11B6:\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, int a3, _DWORD *a4)\n{\n _DWORD *result; // rax\n _DWORD *v5; // rdi\n _DWORD *v6; // rdx\n\n result = a4;\n if ( a2 > 0 )\n {\n v5 = (_DWORD *)(a1 + 4LL * a3);\n v6 = a4;\n do\n {\n *v6 = *v5;\n v5 += 4;\n ++v6;\n }\n while ( v6 != &a4[a2] );\n }\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\nmov rax, rcx\ntest esi, esi\njle short locret_11B6\nmovsxd rdx, edx\nlea rdi, [rdi+rdx*4]\nmov rdx, rcx\nmovsxd rsi, esi\nlea r8, [rcx+rsi*4]\nloc_11A5:\nmov esi, [rdi]\nmov [rdx], esi\nadd rdi, 10h\nadd rdx, 4\ncmp rdx, r8\njnz short loc_11A5\nlocret_11B6:\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1189(__int64 a1, int a2, int a3, _DWORD *a4)\n{\n _DWORD *result; // rax\n _DWORD *v5; // rdi\n _DWORD *v6; // rdx\n\n result = a4;\n if ( a2 > 0 )\n {\n v5 = (_DWORD *)(a1 + 4LL * a3);\n v6 = a4;\n do\n {\n *v6 = *v5;\n v5 += 4;\n ++v6;\n }\n while ( v6 != &a4[a2] );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1189(long long a1, int a2, int a3, uint32_t *a4) {\n uint32_t *result;\n uint32_t *v5;\n uint32_t *v6;\n result = a4;\n if (a2 > 0) {\n v5 = (uint32_t *)(a1 + 4LL * a3);\n v6 = a4;\n do {\n *v6 = *v5;\n v5 += 4;\n ++v6;\n } while (v6 != &a4[a2]);\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, int a3, uint32_t *a4) {\n uint32_t *result;\n uint32_t *v5;\n uint32_t *v6;\n result = a4;\n if (a2 > 0) {\n v5 = (uint32_t *)(a1 + 4LL * a3);\n v6 = a4;\n do {\n *v6 = *v5;\n v5 += 4;\n ++v6;\n } while (v6 != &a4[a2]);\n }\n return result;\n}" + }, + { + "index": 50, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n// Function to find the minimum length and corresponding list\n\n", + "func": "void func0(int input_list[][10], int size_list[], int list_count,\n int *min_length, int **min_list) {\n int i, j;\n *min_length = INT_MAX;\n *min_list = NULL;\n for (i = 0; i < list_count; i++) {\n if (size_list[i] < *min_length) {\n *min_length = size_list[i];\n *min_list = input_list[i];\n }\n }\n}", + "test": "int main() {\n\n int list1[][10] = {{0}, {1, 3}, {5, 7}, {9, 11}, {13, 15, 17}};\n\n int sizes1[] = {1, 2, 2, 2, 3};\n\n int *result_list1;\n\n int result_length1;\n\n func0(list1, sizes1, 5, &result_length1, &result_list1);\n\n assert(result_length1 == 1 && result_list1[0] == 0);\n\n\n\n int list2[][10] = {{1,2,3,4,5},{1,2,3,4},{1,2,3},{1,2},{1}};\n\n int sizes2[] = {5, 4, 3, 2, 1};\n\n int *result_list2;\n\n int result_length2;\n\n func0(list2, sizes2, 5, &result_length2, &result_list2);\n\n assert(result_length2 == 1 && result_list2[0] == 1);\n\n\n\n int list3[][10] = {{3,4,5},{6,7,8,9},{10,11,12},{1,2}};\n\n int sizes3[] = {3, 4, 3, 2};\n\n int *result_list3;\n\n int result_length3;\n\n func0(list3, sizes3, 4, &result_length3, &result_list3);\n\n assert(result_length3 == 2 && (result_list3[0] == 1 && result_list3[1] == 2));\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %edx,-0x24(%rbp)\nmov %rcx,-0x30(%rbp)\nmov %r8,-0x38(%rbp)\nmov -0x30(%rbp),%rax\nmovl $0x7fffffff,(%rax)\nmov -0x38(%rbp),%rax\nmovq $0x0,(%rax)\nmovl $0x0,-0x4(%rbp)\njmp 1207 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x30(%rbp),%rax\nmov (%rax),%eax\ncmp %eax,%edx\njge 1203 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x30(%rbp),%rax\nmov %edx,(%rax)\nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0x38(%rbp),%rax\nmov %rdx,(%rax)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x24(%rbp),%eax\njl 11a2 \npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_30], rcx\nmov [rbp+var_38], r8\nmov rax, [rbp+var_30]\nmov dword ptr [rax], 7FFFFFFFh\nmov rax, [rbp+var_38]\nmov qword ptr [rax], 0\nmov [rbp+var_4], 0\njmp short loc_1207\nloc_11A2:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_30]\nmov eax, [rax]\ncmp edx, eax\njge short loc_1203\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_30]\nmov [rax], edx\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov rax, [rbp+var_38]\nmov [rax], rdx\nloc_1203:\nadd [rbp+var_4], 1\nloc_1207:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_24]\njl short loc_11A2\nnop\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3, _DWORD *a4, _QWORD *a5)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+34h] [rbp-4h]\n\n *a4 = 0x7FFFFFFF;\n *a5 = 0LL;\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a3 )\n break;\n if ( *(_DWORD *)(4LL * (int)i + a2) < *a4 )\n {\n *a4 = *(_DWORD *)(4LL * (int)i + a2);\n *a5 = a1 + 40LL * (int)i;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_30], rcx\nmov [rbp+var_38], r8\nmov rax, [rbp+var_30]\nmov dword ptr [rax], 7FFFFFFFh\nmov rax, [rbp+var_38]\nmov qword ptr [rax], 0\nmov [rbp+var_4], 0\njmp short loc_1207\nloc_11A2:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_30]\nmov eax, [rax]\ncmp edx, eax\njge short loc_1203\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_30]\nmov [rax], edx\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov rax, [rbp+var_38]\nmov [rax], rdx\nloc_1203:\nadd [rbp+var_4], 1\nloc_1207:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_24]\njl short loc_11A2\nnop\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, int a3, _DWORD *a4, _QWORD *a5)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+34h] [rbp-4h]\n\n *a4 = 0x7FFFFFFF;\n *a5 = 0LL;\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a3 )\n break;\n if ( *(_DWORD *)(4LL * (int)i + a2) < *a4 )\n {\n *a4 = *(_DWORD *)(4LL * (int)i + a2);\n *a5 = a1 + 40LL * (int)i;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, int a3, uint32_t *a4,\n uint64_t *a5) {\n long long result;\n unsigned int i;\n *a4 = 2147483647;\n *a5 = 0LL;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a3) break;\n if (*(uint32_t *)(4LL * (int)i + a2) < *a4) {\n *a4 = *(uint32_t *)(4LL * (int)i + a2);\n *a5 = a1 + 40LL * (int)i;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3, uint32_t *a4,\n uint64_t *a5) {\n long long result;\n unsigned int i;\n *a4 = 2147483647;\n *a5 = 0LL;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a3) break;\n if (*(uint32_t *)(4LL * (int)i + a2) < *a4) {\n *a4 = *(uint32_t *)(4LL * (int)i + a2);\n *a5 = a1 + 40LL * (int)i;\n }\n }\n return result;\n}" + }, + { + "index": 50, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n// Function to find the minimum length and corresponding list\n\n", + "func": "void func0(int input_list[][10], int size_list[], int list_count,\n int *min_length, int **min_list) {\n int i, j;\n *min_length = INT_MAX;\n *min_list = NULL;\n for (i = 0; i < list_count; i++) {\n if (size_list[i] < *min_length) {\n *min_length = size_list[i];\n *min_list = input_list[i];\n }\n }\n}", + "test": "int main() {\n\n int list1[][10] = {{0}, {1, 3}, {5, 7}, {9, 11}, {13, 15, 17}};\n\n int sizes1[] = {1, 2, 2, 2, 3};\n\n int *result_list1;\n\n int result_length1;\n\n func0(list1, sizes1, 5, &result_length1, &result_list1);\n\n assert(result_length1 == 1 && result_list1[0] == 0);\n\n\n\n int list2[][10] = {{1,2,3,4,5},{1,2,3,4},{1,2,3},{1,2},{1}};\n\n int sizes2[] = {5, 4, 3, 2, 1};\n\n int *result_list2;\n\n int result_length2;\n\n func0(list2, sizes2, 5, &result_length2, &result_list2);\n\n assert(result_length2 == 1 && result_list2[0] == 1);\n\n\n\n int list3[][10] = {{3,4,5},{6,7,8,9},{10,11,12},{1,2}};\n\n int sizes3[] = {3, 4, 3, 2};\n\n int *result_list3;\n\n int result_length3;\n\n func0(list3, sizes3, 4, &result_length3, &result_list3);\n\n assert(result_length3 == 2 && (result_list3[0] == 1 && result_list3[1] == 2));\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmovl $0x7fffffff,(%rcx)\nmovq $0x0,(%r8)\ntest %edx,%edx\njle 11a5 \nmov %rsi,%rax\nlea -0x1(%rdx),%edx\nlea 0x4(%rsi,%rdx,4),%rsi\njmp 1198 \nadd $0x4,%rax\nadd $0x28,%rdi\ncmp %rsi,%rax\nje 11a5 \nmov (%rax),%edx\ncmp (%rcx),%edx\njge 118b \nmov %edx,(%rcx)\nmov %rdi,(%r8)\njmp 118b \nretq\n", + "ida_asm": "func0:\nendbr64\nmov dword ptr [rcx], 7FFFFFFFh\nmov qword ptr [r8], 0\ntest edx, edx\njle short locret_11A4\nmov rax, rsi\nmovsxd rdx, edx\nlea rsi, [rsi+rdx*4]\njmp short loc_1197\nloc_118A:\nadd rax, 4\nadd rdi, 28h ; '('\ncmp rax, rsi\njz short locret_11A4\nloc_1197:\nmov edx, [rax]\ncmp edx, [rcx]\njge short loc_118A\nmov [rcx], edx\nmov [r8], rdi\njmp short loc_118A\nlocret_11A4:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, _DWORD *a2, int a3, _DWORD *a4, _QWORD *a5)\n{\n _DWORD *v5; // rax\n _DWORD *v6; // rsi\n\n *a4 = 0x7FFFFFFF;\n *a5 = 0LL;\n if ( a3 > 0 )\n {\n v5 = a2;\n v6 = &a2[a3];\n do\n {\n if ( *v5 < *a4 )\n {\n *a4 = *v5;\n *a5 = a1;\n }\n ++v5;\n a1 += 40LL;\n }\n while ( v5 != v6 );\n }\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov dword ptr [rcx], 7FFFFFFFh\nmov qword ptr [r8], 0\ntest edx, edx\njle short locret_11A4\nmov rax, rsi\nmovsxd rdx, edx\nlea rsi, [rsi+rdx*4]\njmp short loc_1197\nloc_118A:\nadd rax, 4\nadd rdi, 28h ; '('\ncmp rax, rsi\njz short locret_11A4\nloc_1197:\nmov edx, [rax]\ncmp edx, [rcx]\njge short loc_118A\nmov [rcx], edx\nmov [r8], rdi\njmp short loc_118A\nlocret_11A4:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1169(__int64 a1, _DWORD *a2, int a3, _DWORD *a4, _QWORD *a5)\n{\n _DWORD *v5; // rax\n _DWORD *v6; // rsi\n\n *a4 = 0x7FFFFFFF;\n *a5 = 0LL;\n if ( a3 > 0 )\n {\n v5 = a2;\n v6 = &a2[a3];\n do\n {\n if ( *v5 < *a4 )\n {\n *a4 = *v5;\n *a5 = a1;\n }\n ++v5;\n a1 += 40LL;\n }\n while ( v5 != v6 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1169(long long a1, uint32_t *a2, int a3, uint32_t *a4, uint64_t *a5) {\n uint32_t *v5;\n uint32_t *v6;\n *a4 = 2147483647;\n *a5 = 0LL;\n if (a3 > 0) {\n v5 = a2;\n v6 = &a2[a3];\n do {\n if (*v5 < *a4) {\n *a4 = *v5;\n *a5 = a1;\n }\n ++v5;\n a1 += 40LL;\n } while (v5 != v6);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, uint32_t *a2, int a3, uint32_t *a4, uint64_t *a5) {\n uint32_t *v5;\n uint32_t *v6;\n *a4 = 2147483647;\n *a5 = 0LL;\n if (a3 > 0) {\n v5 = a2;\n v6 = &a2[a3];\n do {\n if (*v5 < *a4) {\n *a4 = *v5;\n *a5 = a1;\n }\n ++v5;\n a1 += 40LL;\n } while (v5 != v6);\n }\n}" + }, + { + "index": 50, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n// Function to find the minimum length and corresponding list\n\n", + "func": "void func0(int input_list[][10], int size_list[], int list_count,\n int *min_length, int **min_list) {\n int i, j;\n *min_length = INT_MAX;\n *min_list = NULL;\n for (i = 0; i < list_count; i++) {\n if (size_list[i] < *min_length) {\n *min_length = size_list[i];\n *min_list = input_list[i];\n }\n }\n}", + "test": "int main() {\n\n int list1[][10] = {{0}, {1, 3}, {5, 7}, {9, 11}, {13, 15, 17}};\n\n int sizes1[] = {1, 2, 2, 2, 3};\n\n int *result_list1;\n\n int result_length1;\n\n func0(list1, sizes1, 5, &result_length1, &result_list1);\n\n assert(result_length1 == 1 && result_list1[0] == 0);\n\n\n\n int list2[][10] = {{1,2,3,4,5},{1,2,3,4},{1,2,3},{1,2},{1}};\n\n int sizes2[] = {5, 4, 3, 2, 1};\n\n int *result_list2;\n\n int result_length2;\n\n func0(list2, sizes2, 5, &result_length2, &result_list2);\n\n assert(result_length2 == 1 && result_list2[0] == 1);\n\n\n\n int list3[][10] = {{3,4,5},{6,7,8,9},{10,11,12},{1,2}};\n\n int sizes3[] = {3, 4, 3, 2};\n\n int *result_list3;\n\n int result_length3;\n\n func0(list3, sizes3, 4, &result_length3, &result_list3);\n\n assert(result_length3 == 2 && (result_list3[0] == 1 && result_list3[1] == 2));\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmovl $0x7fffffff,(%rcx)\nmovq $0x0,(%r8)\ntest %edx,%edx\njle 1182 \nlea -0x1(%rdx),%eax\nmov $0x7fffffff,%edx\nlea 0x4(%rsi,%rax,4),%r9\njmp 116a \nnopl 0x0(%rax)\nmov (%rcx),%edx\nmov (%rsi),%eax\ncmp %edx,%eax\njge 1175 \nmov %eax,(%rcx)\nmov %rdi,(%r8)\nadd $0x4,%rsi\nadd $0x28,%rdi\ncmp %r9,%rsi\njne 1168 \nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\nmov dword ptr [rcx], 7FFFFFFFh\nmov qword ptr [r8], 0\ntest edx, edx\njle short locret_1482\nmovsxd rdx, edx\nlea r9, [rsi+rdx*4]\nmov edx, 7FFFFFFFh\njmp short loc_146A\nloc_1468:\nmov edx, [rcx]\nloc_146A:\nmov eax, [rsi]\ncmp eax, edx\njge short loc_1475\nmov [rcx], eax\nmov [r8], rdi\nloc_1475:\nadd rsi, 4\nadd rdi, 28h ; '('\ncmp rsi, r9\njnz short loc_1468\nlocret_1482:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, int *a2, int a3, int *a4, _QWORD *a5)\n{\n int *v5; // r9\n int i; // edx\n\n *a4 = 0x7FFFFFFF;\n *a5 = 0LL;\n if ( a3 > 0 )\n {\n v5 = &a2[a3];\n for ( i = 0x7FFFFFFF; ; i = *a4 )\n {\n if ( *a2 < i )\n {\n *a4 = *a2;\n *a5 = a1;\n }\n ++a2;\n a1 += 40LL;\n if ( a2 == v5 )\n break;\n }\n }\n}", + "ida_strip_asm": "sub_1440:\nendbr64\nmov dword ptr [rcx], 7FFFFFFFh\nmov qword ptr [r8], 0\ntest edx, edx\njle short locret_1482\nmovsxd rdx, edx\nlea r9, [rsi+rdx*4]\nmov edx, 7FFFFFFFh\njmp short loc_146A\nloc_1468:\nmov edx, [rcx]\nloc_146A:\nmov eax, [rsi]\ncmp eax, edx\njge short loc_1475\nmov [rcx], eax\nmov [r8], rdi\nloc_1475:\nadd rsi, 4\nadd rdi, 28h ; '('\ncmp rsi, r9\njnz short loc_1468\nlocret_1482:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1440(__int64 a1, int *a2, int a3, int *a4, _QWORD *a5)\n{\n int *v5; // r9\n int i; // edx\n\n *a4 = 0x7FFFFFFF;\n *a5 = 0LL;\n if ( a3 > 0 )\n {\n v5 = &a2[a3];\n for ( i = 0x7FFFFFFF; ; i = *a4 )\n {\n if ( *a2 < i )\n {\n *a4 = *a2;\n *a5 = a1;\n }\n ++a2;\n a1 += 40LL;\n if ( a2 == v5 )\n break;\n }\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1440(long long a1, int *a2, int a3, int *a4, uint64_t *a5) {\n int *v5;\n int i;\n *a4 = 2147483647;\n *a5 = 0LL;\n if (a3 > 0) {\n v5 = &a2[a3];\n for (i = 2147483647;; i = *a4) {\n if (*a2 < i) {\n *a4 = *a2;\n *a5 = a1;\n }\n ++a2;\n a1 += 40LL;\n if (a2 == v5) break;\n }\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, int *a2, int a3, int *a4, uint64_t *a5) {\n int *v5;\n int i;\n *a4 = 2147483647;\n *a5 = 0LL;\n if (a3 > 0) {\n v5 = &a2[a3];\n for (i = 2147483647;; i = *a4) {\n if (*a2 < i) {\n *a4 = *a2;\n *a5 = a1;\n }\n ++a2;\n a1 += 40LL;\n if (a2 == v5) break;\n }\n }\n}" + }, + { + "index": 51, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "bool func0(int x, int y, int z) {\n if (x == y && y == z) {\n return true;\n } else {\n return false;\n }\n}", + "test": "int main() {\n\n assert(func0(6, 8, 12) == false);\n\n assert(func0(6, 6, 12) == false);\n\n assert(func0(6, 6, 6) == true);\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov %esi,-0x8(%rbp)\nmov %edx,-0xc(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x8(%rbp),%eax\njne 1171 \nmov -0x8(%rbp),%eax\ncmp -0xc(%rbp),%eax\njne 1171 \nmov $0x1,%eax\njmp 1176 \nmov $0x0,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov [rbp+var_C], edx\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_8]\njnz short loc_1171\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_C]\njnz short loc_1171\nmov eax, 1\njmp short loc_1176\nloc_1171:\nmov eax, 0\nloc_1176:\npop rbp\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(int a1, int a2, int a3)\n{\n return a1 == a2 && a2 == a3;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov [rbp+var_C], edx\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_8]\njnz short loc_1171\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_C]\njnz short loc_1171\nmov eax, 1\njmp short loc_1176\nloc_1171:\nmov eax, 0\nloc_1176:\npop rbp\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1149(int a1, int a2, int a3)\n{\n return a1 == a2 && a2 == a3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1149(int a1, int a2, int a3) { return a1 == a2 && a2 == a3; }", + "ida_pseudo_norm": "uint8_t func0(int a1, int a2, int a3) { return a1 == a2 && a2 == a3; }" + }, + { + "index": 52, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int b, int h) {\n int area = b * h;\n return area;\n}", + "test": "int main() {\n\n assert(func0(10, 20) == 200);\n\n assert(func0(15, 20) == 300);\n\n assert(func0(8, 9) == 72);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov -0x14(%rbp),%eax\nimul -0x18(%rbp),%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov eax, [rbp+var_14]\nimul eax, [rbp+var_18]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n return (unsigned int)(a2 * a1);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov eax, [rbp+var_14]\nimul eax, [rbp+var_18]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2)\n{\n return (unsigned int)(a2 * a1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2) { return (unsigned int)(a2 * a1); }", + "ida_pseudo_norm": "long long func0(int a1, int a2) { return (unsigned int)(a2 * a1); }" + }, + { + "index": 53, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* str) {\n int len = strlen(str);\n if (str[0] == str[len - 1]) {\n return \"Equal\";\n } else {\n return \"Not Equal\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"abcda\"), \"Equal\") == 0);\n\n assert(strcmp(func0(\"ab\"), \"Not Equal\") == 0);\n\n assert(strcmp(func0(\"mad\"), \"Not Equal\") == 0);\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov -0x18(%rbp),%rax\nmov %rax,%rdi\ncallq 1070 \nmov %eax,-0x4(%rbp)\nmov -0x18(%rbp),%rax\nmovzbl (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea -0x1(%rax),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmovzbl (%rax),%eax\ncmp %al,%dl\njne 11cf \nlea 0xe3b(%rip),%rax\njmp 11d6 \nlea 0xe38(%rip),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov rax, [rbp+s]\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njnz short loc_11CF\nlea rax, s2; \"Equal\"\njmp short locret_11D6\nloc_11CF:\nlea rax, aNotEqual; \"Not Equal\"\nlocret_11D6:\nleave\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n if ( *a1 == a1[(int)strlen(a1) - 1] )\n return \"Equal\";\n else\n return \"Not Equal\";\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov rax, [rbp+s]\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njnz short loc_11CF\nlea rax, s2; \"Equal\"\njmp short locret_11D6\nloc_11CF:\nlea rax, aNotEqual; \"Not Equal\"\nlocret_11D6:\nleave\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1189(const char *a1)\n{\n if ( *a1 == a1[(int)strlen(a1) - 1] )\n return \"Equal\";\n else\n return \"Not Equal\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1189(const char *a1) {\n if (*a1 == a1[(int)strlen(a1) - 1])\n return \"Equal\";\n else\n return \"Not Equal\";\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n if (*a1 == a1[(int)strlen(a1) - 1])\n return \"Equal\";\n else\n return \"Not Equal\";\n}" + }, + { + "index": 53, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* str) {\n int len = strlen(str);\n if (str[0] == str[len - 1]) {\n return \"Equal\";\n } else {\n return \"Not Equal\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"abcda\"), \"Equal\") == 0);\n\n assert(strcmp(func0(\"ab\"), \"Not Equal\") == 0);\n\n assert(strcmp(func0(\"mad\"), \"Not Equal\") == 0);\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%rdx\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nsub $0x1,%rax\ncltq\nmovzbl -0x1(%rdx,%rax,1),%eax\ncmp %al,(%rdx)\nlea 0xe90(%rip),%rax\nlea 0xe85(%rip),%rdx\ncmovne %rdx,%rax\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ncdqe\nmovzx eax, byte ptr [rbx+rax-1]\ncmp [rbx], al\nlea rax, s2; \"Not Equal\"\nlea rdx, s2+4; \"Equal\"\ncmovz rax, rdx\npop rbx\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n bool v1; // zf\n const char *result; // rax\n\n v1 = *a1 == a1[(int)strlen(a1) - 1];\n result = \"Not Equal\";\n if ( v1 )\n return \"Equal\";\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ncdqe\nmovzx eax, byte ptr [rbx+rax-1]\ncmp [rbx], al\nlea rax, s2; \"Not Equal\"\nlea rdx, s2+4; \"Equal\"\ncmovz rax, rdx\npop rbx\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1189(const char *a1)\n{\n bool v1; // zf\n const char *result; // rax\n\n v1 = *a1 == a1[(int)strlen(a1) - 1];\n result = \"Not Equal\";\n if ( v1 )\n return \"Equal\";\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1189(const char *a1) {\n bool v1;\n const char *result;\n v1 = *a1 == a1[(int)strlen(a1) - 1];\n result = \"Not Equal\";\n if (v1) return \"Equal\";\n return result;\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n bool v1;\n const char *result;\n v1 = *a1 == a1[(int)strlen(a1) - 1];\n result = \"Not Equal\";\n if (v1) return \"Equal\";\n return result;\n}" + }, + { + "index": 53, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* str) {\n int len = strlen(str);\n if (str[0] == str[len - 1]) {\n return \"Equal\";\n } else {\n return \"Not Equal\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"abcda\"), \"Equal\") == 0);\n\n assert(strcmp(func0(\"ab\"), \"Not Equal\") == 0);\n\n assert(strcmp(func0(\"mad\"), \"Not Equal\") == 0);\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\ncallq 1050 \nlea 0xe90(%rip),%rdx\ncltq\nmovzbl -0x1(%rbx,%rax,1),%eax\ncmp %al,(%rbx)\nlea 0xe84(%rip),%rax\ncmovne %rdx,%rax\npop %rbx\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nlea rdx, s2+4; \"Equal\"\ncdqe\nmovzx eax, byte ptr [rbx+rax-1]\ncmp [rbx], al\nlea rax, s2; \"Not Equal\"\ncmovz rax, rdx\npop rbx\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n bool v1; // zf\n const char *result; // rax\n\n v1 = *a1 == a1[(int)strlen(a1) - 1];\n result = \"Not Equal\";\n if ( v1 )\n return \"Equal\";\n return result;\n}", + "ida_strip_asm": "sub_1260:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nlea rdx, s2+4; \"Equal\"\ncdqe\nmovzx eax, byte ptr [rbx+rax-1]\ncmp [rbx], al\nlea rax, s2; \"Not Equal\"\ncmovz rax, rdx\npop rbx\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1260(const char *a1)\n{\n bool v1; // zf\n const char *result; // rax\n\n v1 = *a1 == a1[(int)strlen(a1) - 1];\n result = \"Not Equal\";\n if ( v1 )\n return \"Equal\";\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1260(const char *a1) {\n bool v1;\n const char *result;\n v1 = *a1 == a1[(int)strlen(a1) - 1];\n result = \"Not Equal\";\n if (v1) return \"Equal\";\n return result;\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n bool v1;\n const char *result;\n v1 = *a1 == a1[(int)strlen(a1) - 1];\n result = \"Not Equal\";\n if (v1) return \"Equal\";\n return result;\n}" + }, + { + "index": 54, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int *my_list, int n) {\n int max_value = 0;\n for (int i = 0; i < n; i++) {\n if (my_list[i] > max_value) {\n max_value = my_list[i];\n }\n }\n int *buckets = malloc((max_value + 1) * sizeof(int));\n for (int j = 0; j <= max_value; j++) {\n buckets[j] = 0;\n }\n for (int i = 0; i < n; i++) {\n buckets[my_list[i]]++;\n }\n int pos = 0;\n for (int j = 0; j <= max_value; j++) {\n for (int a = 0; a < buckets[j]; a++) {\n my_list[pos] = j;\n pos++;\n }\n }\n free(buckets);\n}", + "test": "int main() {\n\n int list1[] = {1, 23, 4, 5, 6, 7, 8};\n\n int size1 = sizeof(list1) / sizeof(list1[0]);\n\n func0(list1, size1);\n\n assert(list1[0] == 1 && list1[1] == 4 && list1[2] == 5 && list1[3] == 6 && list1[4] == 7 && list1[5] == 8 && list1[6] == 23);\n\n\n\n int list2[] = {12, 9, 28, 33, 69, 45};\n\n int size2 = sizeof(list2) / sizeof(list2[0]);\n\n func0(list2, size2);\n\n assert(list2[0] == 9 && list2[1] == 12 && list2[2] == 28 && list2[3] == 33 && list2[4] == 45 && list2[5] == 69);\n\n\n\n int list3[] = {8, 4, 14, 3, 2, 1};\n\n int size3 = sizeof(list3) / sizeof(list3[0]);\n\n func0(list3, size3);\n\n assert(list3[0] == 1 && list3[1] == 2 && list3[2] == 3 && list3[3] == 4 && list3[4] == 8 && list3[5] == 14);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x40,%rsp\nmov %rdi,-0x38(%rbp)\nmov %esi,-0x3c(%rbp)\nmovl $0x0,-0x24(%rbp)\nmovl $0x0,-0x20(%rbp)\njmp 1204 \nmov -0x20(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x24(%rbp)\njge 1200 \nmov -0x20(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x24(%rbp)\naddl $0x1,-0x20(%rbp)\nmov -0x20(%rbp),%eax\ncmp -0x3c(%rbp),%eax\njl 11cc \nmov -0x24(%rbp),%eax\nadd $0x1,%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0x1c(%rbp)\njmp 124b \nmov -0x1c(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmovl $0x0,(%rax)\naddl $0x1,-0x1c(%rbp)\nmov -0x1c(%rbp),%eax\ncmp -0x24(%rbp),%eax\njle 122d \nmovl $0x0,-0x18(%rbp)\njmp 128e \nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nadd $0x1,%edx\nmov %edx,(%rax)\naddl $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%eax\ncmp -0x3c(%rbp),%eax\njl 125c \nmovl $0x0,-0x14(%rbp)\nmovl $0x0,-0x10(%rbp)\njmp 12ef \nmovl $0x0,-0xc(%rbp)\njmp 12d0 \nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x38(%rbp),%rax\nadd %rax,%rdx\nmov -0x10(%rbp),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x14(%rbp)\naddl $0x1,-0xc(%rbp)\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0xc(%rbp)\njl 12af \naddl $0x1,-0x10(%rbp)\nmov -0x10(%rbp),%eax\ncmp -0x24(%rbp),%eax\njle 12a6 \nmov -0x8(%rbp),%rax\nmov %rax,%rdi\ncallq 1080 \nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov [rbp+var_24], 0\nmov [rbp+var_20], 0\njmp short loc_1204\nloc_11CC:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_24], eax\njge short loc_1200\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_24], eax\nloc_1200:\nadd [rbp+var_20], 1\nloc_1204:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_3C]\njl short loc_11CC\nmov eax, [rbp+var_24]\nadd eax, 1\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov [rbp+var_1C], 0\njmp short loc_124B\nloc_122D:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov dword ptr [rax], 0\nadd [rbp+var_1C], 1\nloc_124B:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_24]\njle short loc_122D\nmov [rbp+var_18], 0\njmp short loc_128E\nloc_125C:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nadd edx, 1\nmov [rax], edx\nadd [rbp+var_18], 1\nloc_128E:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_3C]\njl short loc_125C\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\njmp short loc_12EF\nloc_12A6:\nmov [rbp+var_C], 0\njmp short loc_12D0\nloc_12AF:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rdx, rax\nmov eax, [rbp+var_10]\nmov [rdx], eax\nadd [rbp+var_14], 1\nadd [rbp+var_C], 1\nloc_12D0:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_C], eax\njl short loc_12AF\nadd [rbp+var_10], 1\nloc_12EF:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_24]\njle short loc_12A6\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nnop\nleave\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2)\n{\n _DWORD *v2; // rax\n int v3; // [rsp+1Ch] [rbp-24h]\n int i; // [rsp+20h] [rbp-20h]\n int j; // [rsp+24h] [rbp-1Ch]\n int k; // [rsp+28h] [rbp-18h]\n int v7; // [rsp+2Ch] [rbp-14h]\n int m; // [rsp+30h] [rbp-10h]\n int n; // [rsp+34h] [rbp-Ch]\n _DWORD *ptr; // [rsp+38h] [rbp-8h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( v3 < *(_DWORD *)(4LL * i + a1) )\n v3 = *(_DWORD *)(4LL * i + a1);\n }\n ptr = malloc(4LL * (v3 + 1));\n for ( j = 0; j <= v3; ++j )\n ptr[j] = 0;\n for ( k = 0; k < a2; ++k )\n {\n v2 = &ptr[*(int *)(4LL * k + a1)];\n ++*v2;\n }\n v7 = 0;\n for ( m = 0; m <= v3; ++m )\n {\n for ( n = 0; n < ptr[m]; ++n )\n *(_DWORD *)(a1 + 4LL * v7++) = m;\n }\n free(ptr);\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov [rbp+var_24], 0\nmov [rbp+var_20], 0\njmp short loc_1204\nloc_11CC:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_24], eax\njge short loc_1200\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_24], eax\nloc_1200:\nadd [rbp+var_20], 1\nloc_1204:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_3C]\njl short loc_11CC\nmov eax, [rbp+var_24]\nadd eax, 1\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov [rbp+var_1C], 0\njmp short loc_124B\nloc_122D:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov dword ptr [rax], 0\nadd [rbp+var_1C], 1\nloc_124B:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_24]\njle short loc_122D\nmov [rbp+var_18], 0\njmp short loc_128E\nloc_125C:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nadd edx, 1\nmov [rax], edx\nadd [rbp+var_18], 1\nloc_128E:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_3C]\njl short loc_125C\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\njmp short loc_12EF\nloc_12A6:\nmov [rbp+var_C], 0\njmp short loc_12D0\nloc_12AF:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rdx, rax\nmov eax, [rbp+var_10]\nmov [rdx], eax\nadd [rbp+var_14], 1\nadd [rbp+var_C], 1\nloc_12D0:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_C], eax\njl short loc_12AF\nadd [rbp+var_10], 1\nloc_12EF:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_24]\njle short loc_12A6\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nnop\nleave\nretn", + "ida_strip_pseudo": "void __fastcall sub_11A9(__int64 a1, int a2)\n{\n _DWORD *v2; // rax\n int v3; // [rsp+1Ch] [rbp-24h]\n int i; // [rsp+20h] [rbp-20h]\n int j; // [rsp+24h] [rbp-1Ch]\n int k; // [rsp+28h] [rbp-18h]\n int v7; // [rsp+2Ch] [rbp-14h]\n int m; // [rsp+30h] [rbp-10h]\n int n; // [rsp+34h] [rbp-Ch]\n _DWORD *ptr; // [rsp+38h] [rbp-8h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( v3 < *(_DWORD *)(4LL * i + a1) )\n v3 = *(_DWORD *)(4LL * i + a1);\n }\n ptr = malloc(4LL * (v3 + 1));\n for ( j = 0; j <= v3; ++j )\n ptr[j] = 0;\n for ( k = 0; k < a2; ++k )\n {\n v2 = &ptr[*(int *)(4LL * k + a1)];\n ++*v2;\n }\n v7 = 0;\n for ( m = 0; m <= v3; ++m )\n {\n for ( n = 0; n < ptr[m]; ++n )\n *(_DWORD *)(a1 + 4LL * v7++) = m;\n }\n free(ptr);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_11A9(long long a1, int a2) {\n uint32_t *v2;\n int v3;\n int i;\n int j;\n int k;\n int v7;\n int m;\n int n;\n uint32_t *ptr;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n if (v3 < *(uint32_t *)(4LL * i + a1)) v3 = *(uint32_t *)(4LL * i + a1);\n }\n ptr = malloc(4LL * (v3 + 1));\n for (j = 0; j <= v3; ++j) ptr[j] = 0;\n for (k = 0; k < a2; ++k) {\n v2 = &ptr[*(int *)(4LL * k + a1)];\n ++*v2;\n }\n v7 = 0;\n for (m = 0; m <= v3; ++m) {\n for (n = 0; n < ptr[m]; ++n) *(uint32_t *)(a1 + 4LL * v7++) = m;\n }\n free(ptr);\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2) {\n uint32_t *v2;\n int v3;\n int i;\n int j;\n int k;\n int v7;\n int m;\n int n;\n uint32_t *ptr;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n if (v3 < *(uint32_t *)(4LL * i + a1)) v3 = *(uint32_t *)(4LL * i + a1);\n }\n ptr = malloc(4LL * (v3 + 1));\n for (j = 0; j <= v3; ++j) ptr[j] = 0;\n for (k = 0; k < a2; ++k) {\n v2 = &ptr[*(int *)(4LL * k + a1)];\n ++*v2;\n }\n v7 = 0;\n for (m = 0; m <= v3; ++m) {\n for (n = 0; n < ptr[m]; ++n) *(uint32_t *)(a1 + 4LL * v7++) = m;\n }\n free(ptr);\n}" + }, + { + "index": 54, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int *my_list, int n) {\n int max_value = 0;\n for (int i = 0; i < n; i++) {\n if (my_list[i] > max_value) {\n max_value = my_list[i];\n }\n }\n int *buckets = malloc((max_value + 1) * sizeof(int));\n for (int j = 0; j <= max_value; j++) {\n buckets[j] = 0;\n }\n for (int i = 0; i < n; i++) {\n buckets[my_list[i]]++;\n }\n int pos = 0;\n for (int j = 0; j <= max_value; j++) {\n for (int a = 0; a < buckets[j]; a++) {\n my_list[pos] = j;\n pos++;\n }\n }\n free(buckets);\n}", + "test": "int main() {\n\n int list1[] = {1, 23, 4, 5, 6, 7, 8};\n\n int size1 = sizeof(list1) / sizeof(list1[0]);\n\n func0(list1, size1);\n\n assert(list1[0] == 1 && list1[1] == 4 && list1[2] == 5 && list1[3] == 6 && list1[4] == 7 && list1[5] == 8 && list1[6] == 23);\n\n\n\n int list2[] = {12, 9, 28, 33, 69, 45};\n\n int size2 = sizeof(list2) / sizeof(list2[0]);\n\n func0(list2, size2);\n\n assert(list2[0] == 9 && list2[1] == 12 && list2[2] == 28 && list2[3] == 33 && list2[4] == 45 && list2[5] == 69);\n\n\n\n int list3[] = {8, 4, 14, 3, 2, 1};\n\n int size3 = sizeof(list3) / sizeof(list3[0]);\n\n func0(list3, size3);\n\n assert(list3[0] == 1 && list3[1] == 2 && list3[2] == 3 && list3[3] == 4 && list3[4] == 8 && list3[5] == 14);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbp\ntest %esi,%esi\njle 127a \nmov %esi,%r12d\nmov %rdi,%rax\nlea -0x1(%rsi),%edx\nlea 0x4(%rdi,%rdx,4),%rcx\nmov $0x0,%ebx\nmov (%rax),%edx\ncmp %edx,%ebx\ncmovl %edx,%ebx\nadd $0x4,%rax\ncmp %rcx,%rax\njne 11cf \nlea 0x1(%rbx),%edi\nmovslq %edi,%rdi\nshl $0x2,%rdi\ncallq 10b0 \ntest %ebx,%ebx\njs 120b \nmov $0x0,%edx\nmovl $0x0,(%rax,%rdx,4)\nadd $0x1,%rdx\ncmp %edx,%ebx\njge 11f7 \ntest %r12d,%r12d\njle 1226 \nmov $0x0,%edx\nmovslq 0x0(%rbp,%rdx,4),%rcx\naddl $0x1,(%rax,%rcx,4)\nadd $0x1,%rdx\ncmp %edx,%r12d\njg 1210 \ntest %ebx,%ebx\njs 126d \nmov $0x0,%edi\nmov $0x0,%r9d\nlea 0x4(%rbp),%r11\njmp 1260 \nmovslq %r9d,%r10\nlea 0x0(%rbp,%r10,4),%rdx\nlea -0x1(%r8),%esi\nadd %r10,%rsi\nlea (%r11,%rsi,4),%rsi\nmov %ecx,(%rdx)\nadd $0x4,%rdx\ncmp %rsi,%rdx\njne 124a \nadd %r8d,%r9d\nadd $0x1,%rdi\ncmp %edi,%ebx\njl 126d \nmov %edi,%ecx\nmov (%rax,%rdi,4),%r8d\ntest %r8d,%r8d\njg 1237 \njmp 1258 \nmov %rax,%rdi\ncallq 1080 \npop %rbx\npop %rbp\npop %r12\nretq\nmov $0x4,%edi\ncallq 10b0 \nmovl $0x0,(%rax)\nmov $0x0,%ebx\njmp 1226 \n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nmov r12d, esi\ntest esi, esi\njle loc_127F\nmov rax, rdi\nmovsxd rdx, esi\nlea rcx, [rdi+rdx*4]\nmov ebp, 0\nloc_11CE:\nmov edx, [rax]\ncmp ebp, edx\ncmovl ebp, edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_11CE\nlea edi, [rbp+1]\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov r8, rax\ntest ebp, ebp\njs short loc_1212\nloc_11F4:\nmov rax, r8\nmov edx, ebp\nlea rdx, [r8+rdx*4+4]\nloc_11FE:\nmov dword ptr [rax], 0\nadd rax, 4\ncmp rax, rdx\njnz short loc_11FE\ntest r12d, r12d\njle short loc_122D\nloc_1212:\nmov eax, 0\nloc_1217:\nmovsxd rdx, dword ptr [rbx+rax*4]\nadd dword ptr [r8+rdx*4], 1\nadd rax, 1\ncmp r12d, eax\njg short loc_1217\ntest ebp, ebp\njs short loc_1272\nloc_122D:\nlea r11d, [rbp+1]\nmov esi, 0\nmov r9d, 0\njmp short loc_1266\nloc_123E:\nmovsxd r10, r9d\nlea rax, [rbx+r10*4]\nmovsxd rcx, edi\nadd rcx, r10\nlea rcx, [rbx+rcx*4]\nloc_124F:\nmov [rax], edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_124F\nadd r9d, edi\nloc_125D:\nadd rsi, 1\ncmp r11, rsi\njz short loc_1272\nloc_1266:\nmov edx, esi\nmov edi, [r8+rsi*4]\ntest edi, edi\njg short loc_123E\njmp short loc_125D\nloc_1272:\nmov rdi, r8; ptr\ncall _free\npop rbx\npop rbp\npop r12\nretn\nloc_127F:\nmov edi, 4; size\ncall _malloc\nmov r8, rax\nmov ebp, 0\njmp loc_11F4", + "ida_pseudo": "void __fastcall func0(int *a1, int a2)\n{\n int *v3; // rax\n int v4; // ebp\n _DWORD *v5; // r8\n _DWORD *v6; // rax\n __int64 v7; // rax\n __int64 v8; // rsi\n int v9; // r9d\n int *v10; // rax\n int v11; // edi\n\n if ( a2 <= 0 )\n {\n v5 = malloc(4uLL);\n v4 = 0;\n }\n else\n {\n v3 = a1;\n v4 = 0;\n do\n {\n if ( v4 < *v3 )\n v4 = *v3;\n ++v3;\n }\n while ( v3 != &a1[a2] );\n v5 = malloc(4LL * (v4 + 1));\n if ( v4 < 0 )\n {\nLABEL_10:\n v7 = 0LL;\n do\n ++v5[a1[v7++]];\n while ( a2 > (int)v7 );\n if ( v4 < 0 )\n goto LABEL_20;\n goto LABEL_13;\n }\n }\n v6 = v5;\n do\n *v6++ = 0;\n while ( v6 != &v5[v4 + 1] );\n if ( a2 > 0 )\n goto LABEL_10;\nLABEL_13:\n v8 = 0LL;\n v9 = 0;\n do\n {\n v11 = v5[v8];\n if ( v11 > 0 )\n {\n v10 = &a1[v9];\n do\n *v10++ = v8;\n while ( v10 != &a1[v9 + (__int64)v11] );\n v9 += v11;\n }\n ++v8;\n }\n while ( v4 + 1 != v8 );\nLABEL_20:\n free(v5);\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nmov r12d, esi\ntest esi, esi\njle loc_127F\nmov rax, rdi\nmovsxd rdx, esi\nlea rcx, [rdi+rdx*4]\nmov ebp, 0\nloc_11CE:\nmov edx, [rax]\ncmp ebp, edx\ncmovl ebp, edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_11CE\nlea edi, [rbp+1]\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov r8, rax\ntest ebp, ebp\njs short loc_1212\nloc_11F4:\nmov rax, r8\nmov edx, ebp\nlea rdx, [r8+rdx*4+4]\nloc_11FE:\nmov dword ptr [rax], 0\nadd rax, 4\ncmp rax, rdx\njnz short loc_11FE\ntest r12d, r12d\njle short loc_122D\nloc_1212:\nmov eax, 0\nloc_1217:\nmovsxd rdx, dword ptr [rbx+rax*4]\nadd dword ptr [r8+rdx*4], 1\nadd rax, 1\ncmp r12d, eax\njg short loc_1217\ntest ebp, ebp\njs short loc_1272\nloc_122D:\nlea r11d, [rbp+1]\nmov esi, 0\nmov r9d, 0\njmp short loc_1266\nloc_123E:\nmovsxd r10, r9d\nlea rax, [rbx+r10*4]\nmovsxd rcx, edi\nadd rcx, r10\nlea rcx, [rbx+rcx*4]\nloc_124F:\nmov [rax], edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_124F\nadd r9d, edi\nloc_125D:\nadd rsi, 1\ncmp r11, rsi\njz short loc_1272\nloc_1266:\nmov edx, esi\nmov edi, [r8+rsi*4]\ntest edi, edi\njg short loc_123E\njmp short loc_125D\nloc_1272:\nmov rdi, r8; ptr\ncall _free\npop rbx\npop rbp\npop r12\nretn\nloc_127F:\nmov edi, 4; size\ncall _malloc\nmov r8, rax\nmov ebp, 0\njmp loc_11F4", + "ida_strip_pseudo": "void __fastcall sub_11A9(int *a1, int a2)\n{\n int *v3; // rax\n int v4; // ebp\n _DWORD *v5; // r8\n _DWORD *v6; // rax\n __int64 v7; // rax\n __int64 v8; // rsi\n int v9; // r9d\n int *v10; // rax\n int v11; // edi\n\n if ( a2 <= 0 )\n {\n v5 = malloc(4uLL);\n v4 = 0;\n }\n else\n {\n v3 = a1;\n v4 = 0;\n do\n {\n if ( v4 < *v3 )\n v4 = *v3;\n ++v3;\n }\n while ( v3 != &a1[a2] );\n v5 = malloc(4LL * (v4 + 1));\n if ( v4 < 0 )\n {\nLABEL_10:\n v7 = 0LL;\n do\n ++v5[a1[v7++]];\n while ( a2 > (int)v7 );\n if ( v4 < 0 )\n goto LABEL_20;\n goto LABEL_13;\n }\n }\n v6 = v5;\n do\n *v6++ = 0;\n while ( v6 != &v5[v4 + 1] );\n if ( a2 > 0 )\n goto LABEL_10;\nLABEL_13:\n v8 = 0LL;\n v9 = 0;\n do\n {\n v11 = v5[v8];\n if ( v11 > 0 )\n {\n v10 = &a1[v9];\n do\n *v10++ = v8;\n while ( v10 != &a1[v9 + (__int64)v11] );\n v9 += v11;\n }\n ++v8;\n }\n while ( v4 + 1 != v8 );\nLABEL_20:\n free(v5);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_11A9(int *a1, int a2) {\n int *v3;\n int v4;\n uint32_t *v5;\n uint32_t *v6;\n long long v7;\n long long v8;\n int v9;\n int *v10;\n int v11;\n if (a2 <= 0) {\n v5 = malloc(4uLL);\n v4 = 0;\n } else {\n v3 = a1;\n v4 = 0;\n do {\n if (v4 < *v3) v4 = *v3;\n ++v3;\n } while (v3 != &a1[a2]);\n v5 = malloc(4LL * (v4 + 1));\n if (v4 < 0) {\n LABEL_10:\n v7 = 0LL;\n do\n ++v5[a1[v7++]];\n while (a2 > (int)v7);\n if (v4 < 0) goto LABEL_20;\n goto LABEL_13;\n }\n }\n v6 = v5;\n do\n *v6++ = 0;\n while (v6 != &v5[v4 + 1]);\n if (a2 > 0) goto LABEL_10;\nLABEL_13:\n v8 = 0LL;\n v9 = 0;\n do {\n v11 = v5[v8];\n if (v11 > 0) {\n v10 = &a1[v9];\n do\n *v10++ = v8;\n while (v10 != &a1[v9 + (long long)v11]);\n v9 += v11;\n }\n ++v8;\n } while (v4 + 1 != v8);\nLABEL_20:\n free(v5);\n}", + "ida_pseudo_norm": "void func0(int *a1, int a2) {\n int *v3;\n int v4;\n uint32_t *v5;\n uint32_t *v6;\n long long v7;\n long long v8;\n int v9;\n int *v10;\n int v11;\n if (a2 <= 0) {\n v5 = malloc(4uLL);\n v4 = 0;\n } else {\n v3 = a1;\n v4 = 0;\n do {\n if (v4 < *v3) v4 = *v3;\n ++v3;\n } while (v3 != &a1[a2]);\n v5 = malloc(4LL * (v4 + 1));\n if (v4 < 0) {\n LABEL_10:\n v7 = 0LL;\n do\n ++v5[a1[v7++]];\n while (a2 > (int)v7);\n if (v4 < 0) goto LABEL_20;\n goto LABEL_13;\n }\n }\n v6 = v5;\n do\n *v6++ = 0;\n while (v6 != &v5[v4 + 1]);\n if (a2 > 0) goto LABEL_10;\nLABEL_13:\n v8 = 0LL;\n v9 = 0;\n do {\n v11 = v5[v8];\n if (v11 > 0) {\n v10 = &a1[v9];\n do\n *v10++ = v8;\n while (v10 != &a1[v9 + (long long)v11]);\n v9 += v11;\n }\n ++v8;\n } while (v4 + 1 != v8);\nLABEL_20:\n free(v5);\n}" + }, + { + "index": 54, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int *my_list, int n) {\n int max_value = 0;\n for (int i = 0; i < n; i++) {\n if (my_list[i] > max_value) {\n max_value = my_list[i];\n }\n }\n int *buckets = malloc((max_value + 1) * sizeof(int));\n for (int j = 0; j <= max_value; j++) {\n buckets[j] = 0;\n }\n for (int i = 0; i < n; i++) {\n buckets[my_list[i]]++;\n }\n int pos = 0;\n for (int j = 0; j <= max_value; j++) {\n for (int a = 0; a < buckets[j]; a++) {\n my_list[pos] = j;\n pos++;\n }\n }\n free(buckets);\n}", + "test": "int main() {\n\n int list1[] = {1, 23, 4, 5, 6, 7, 8};\n\n int size1 = sizeof(list1) / sizeof(list1[0]);\n\n func0(list1, size1);\n\n assert(list1[0] == 1 && list1[1] == 4 && list1[2] == 5 && list1[3] == 6 && list1[4] == 7 && list1[5] == 8 && list1[6] == 23);\n\n\n\n int list2[] = {12, 9, 28, 33, 69, 45};\n\n int size2 = sizeof(list2) / sizeof(list2[0]);\n\n func0(list2, size2);\n\n assert(list2[0] == 9 && list2[1] == 12 && list2[2] == 28 && list2[3] == 33 && list2[4] == 45 && list2[5] == 69);\n\n\n\n int list3[] = {8, 4, 14, 3, 2, 1};\n\n int size3 = sizeof(list3) / sizeof(list3[0]);\n\n func0(list3, size3);\n\n assert(list3[0] == 1 && list3[1] == 2 && list3[2] == 3 && list3[3] == 4 && list3[4] == 8 && list3[5] == 14);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %esi,%r12d\npush %rbp\nmov %rdi,%rbp\npush %rbx\ntest %esi,%esi\njle 14ac \nlea -0x1(%rsi),%edx\nmov %rdi,%rax\nxor %ebx,%ebx\nlea 0x4(%rdi,%rdx,4),%rcx\nnopl 0x0(%rax,%rax,1)\nmovslq (%rax),%rdx\ncmp %edx,%ebx\ncmovl %rdx,%rbx\nadd $0x4,%rax\ncmp %rcx,%rax\njne 13e8 \nlea 0x1(%rbx),%edi\nmovslq %edi,%rdi\nshl $0x2,%rdi\ncallq 10b0 \nmov %rax,%r9\nmov %rax,%rdx\nlea 0x4(%rax,%rbx,4),%rax\nnopl 0x0(%rax)\nmovl $0x0,(%rdx)\nadd $0x4,%rdx\ncmp %rdx,%rax\njne 1418 \ntest %r12d,%r12d\njle 1451 \nlea -0x1(%r12),%eax\nmov %rbp,%rdx\nlea 0x4(%rbp,%rax,4),%rcx\nnopl 0x0(%rax)\nmovslq (%rdx),%rax\nadd $0x4,%rdx\naddl $0x1,(%r9,%rax,4)\ncmp %rcx,%rdx\njne 1440 \nxor %edi,%edi\nxor %eax,%eax\nlea 0x4(%rbp),%r11\nnopl 0x0(%rax)\nmov (%r9,%rdi,4),%r8d\nmov %edi,%ecx\ntest %r8d,%r8d\njle 148e \nmovslq %eax,%r10\nlea -0x1(%r8),%esi\nadd %r10,%rsi\nlea 0x0(%rbp,%r10,4),%rdx\nlea (%r11,%rsi,4),%rsi\nxchg %ax,%ax\nmov %ecx,(%rdx)\nadd $0x4,%rdx\ncmp %rdx,%rsi\njne 1480 \nadd %r8d,%eax\nlea 0x1(%rdi),%rdx\ncmp %rbx,%rdi\nje 14a0 \nmov %rdx,%rdi\njmp 1460 \nnopl 0x0(%rax)\npop %rbx\nmov %r9,%rdi\npop %rbp\npop %r12\njmpq 1080 \nmov $0x4,%edi\nxor %ebx,%ebx\njmpq 1404 \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\nmov rbp, rdi\npush rbx\ntest esi, esi\njle loc_14BC\nmovsxd rdx, esi\nxor ebx, ebx\nmov r12d, esi\nmov rax, rdi\nlea rcx, [rdi+rdx*4]\nand edx, 1\njz short loc_13E0\nmovsxd rax, dword ptr [rdi]\ncmp ebx, eax\ncmovl rbx, rax\nlea rax, [rdi+4]\ncmp rcx, rax\njz short loc_13FC\nnop dword ptr [rax+00000000h]\nloc_13E0:\nmovsxd rdx, dword ptr [rax]\ncmp ebx, edx\ncmovl rbx, rdx\nmovsxd rdx, dword ptr [rax+4]\ncmp ebx, edx\ncmovl rbx, rdx\nadd rax, 8\ncmp rcx, rax\njnz short loc_13E0\nloc_13FC:\nlea edi, [rbx+1]\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov r8, rax\ntest ebx, ebx\njs short loc_142A\nmovsxd rax, ebx\nmov rdi, r8; s\nxor esi, esi; c\nlea rdx, ds:4[rax*4]; n\ncall _memset\nmov r8, rax\nloc_142A:\nxor eax, eax\nnop dword ptr [rax+00h]\nloc_1430:\nmovsxd rdx, dword ptr [rbp+rax*4+0]\nadd rax, 1\nadd dword ptr [r8+rdx*4], 1\ncmp r12d, eax\njg short loc_1430\ntest ebx, ebx\njs short loc_14B0\nloc_1447:\nxor esi, esi\nxor r9d, r9d\nnop dword ptr [rax+00h]\nloc_1450:\nmov edi, [r8+rsi*4]\nmov edx, esi\ntest edi, edi\njle short loc_1499\nmovsxd r10, r9d\nmovsxd rcx, edi\nadd rcx, r10\nlea rax, [rbp+r10*4+0]\nlea rcx, [rbp+rcx*4+0]\nmov r10, rcx\nsub r10, rax\nand r10d, 4\njz short loc_1488\nmov [rax], esi\nadd rax, 4\ncmp rcx, rax\njz short loc_1496\nnop dword ptr [rax+00h]\nloc_1488:\nmov [rax], edx\nadd rax, 8\nmov [rax-4], edx\ncmp rcx, rax\njnz short loc_1488\nloc_1496:\nadd r9d, edi\nloc_1499:\nlea rax, [rsi+1]\ncmp rbx, rsi\njz short loc_14B0\nmov rsi, rax\njmp short loc_1450\nloc_14B0:\npop rbx\nmov rdi, r8; ptr\npop rbp\npop r12\njmp _free\nloc_14BC:\nmov edi, 4; size\nxor ebx, ebx\ncall _malloc\nmov dword ptr [rax], 0\nmov r8, rax\njmp loc_1447", + "ida_pseudo": "void __fastcall func0(int *a1, int a2)\n{\n __int64 v3; // rbx\n int *v4; // rax\n int *v5; // rcx\n _DWORD *v6; // r8\n __int64 v7; // rax\n __int64 v8; // rdx\n __int64 v9; // rsi\n int v10; // r9d\n int v11; // edi\n int *v12; // rax\n int *v13; // rcx\n _DWORD *v14; // rax\n\n if ( a2 <= 0 )\n {\n v3 = 0LL;\n v14 = malloc(4uLL);\n *v14 = 0;\n v6 = v14;\nLABEL_16:\n v9 = 0LL;\n v10 = 0;\n while ( 1 )\n {\n v11 = v6[v9];\n if ( v11 > 0 )\n {\n v12 = &a1[v10];\n v13 = &a1[v10 + (__int64)v11];\n if ( ((4 * ((_BYTE)v10 + (_BYTE)v11) - 4 * (_BYTE)v10) & 4) == 0 || (*v12 = v9, ++v12, v13 != v12) )\n {\n do\n {\n *v12 = v9;\n v12 += 2;\n *(v12 - 1) = v9;\n }\n while ( v13 != v12 );\n }\n v10 += v11;\n }\n if ( v3 == v9 )\n break;\n ++v9;\n }\n goto LABEL_24;\n }\n v3 = 0LL;\n v4 = a1;\n v5 = &a1[a2];\n if ( (a2 & 1) == 0 )\n goto LABEL_28;\n if ( *a1 > 0 )\n v3 = *a1;\n v4 = a1 + 1;\n if ( v5 != a1 + 1 )\n {\nLABEL_28:\n do\n {\n if ( (int)v3 < *v4 )\n v3 = *v4;\n if ( (int)v3 < v4[1] )\n v3 = v4[1];\n v4 += 2;\n }\n while ( v5 != v4 );\n }\n v6 = malloc(4LL * ((int)v3 + 1));\n if ( (int)v3 >= 0 )\n v6 = memset(v6, 0, 4LL * (int)v3 + 4);\n v7 = 0LL;\n do\n {\n v8 = a1[v7++];\n ++v6[v8];\n }\n while ( a2 > (int)v7 );\n if ( (int)v3 >= 0 )\n goto LABEL_16;\nLABEL_24:\n free(v6);\n}", + "ida_strip_asm": "sub_13A0:\nendbr64\npush r12\npush rbp\nmov rbp, rdi\npush rbx\ntest esi, esi\njle loc_14BC\nmovsxd rdx, esi\nxor ebx, ebx\nmov r12d, esi\nmov rax, rdi\nlea rcx, [rdi+rdx*4]\nand edx, 1\njz short loc_13E0\nmovsxd rax, dword ptr [rdi]\ncmp ebx, eax\ncmovl rbx, rax\nlea rax, [rdi+4]\ncmp rcx, rax\njz short loc_13FC\nnop dword ptr [rax+00000000h]\nloc_13E0:\nmovsxd rdx, dword ptr [rax]\ncmp ebx, edx\ncmovl rbx, rdx\nmovsxd rdx, dword ptr [rax+4]\ncmp ebx, edx\ncmovl rbx, rdx\nadd rax, 8\ncmp rcx, rax\njnz short loc_13E0\nloc_13FC:\nlea edi, [rbx+1]\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov r8, rax\ntest ebx, ebx\njs short loc_142A\nmovsxd rax, ebx\nmov rdi, r8; s\nxor esi, esi; c\nlea rdx, ds:4[rax*4]; n\ncall _memset\nmov r8, rax\nloc_142A:\nxor eax, eax\nnop dword ptr [rax+00h]\nloc_1430:\nmovsxd rdx, dword ptr [rbp+rax*4+0]\nadd rax, 1\nadd dword ptr [r8+rdx*4], 1\ncmp r12d, eax\njg short loc_1430\ntest ebx, ebx\njs short loc_14B0\nloc_1447:\nxor esi, esi\nxor r9d, r9d\nnop dword ptr [rax+00h]\nloc_1450:\nmov edi, [r8+rsi*4]\nmov edx, esi\ntest edi, edi\njle short loc_1499\nmovsxd r10, r9d\nmovsxd rcx, edi\nadd rcx, r10\nlea rax, [rbp+r10*4+0]\nlea rcx, [rbp+rcx*4+0]\nmov r10, rcx\nsub r10, rax\nand r10d, 4\njz short loc_1488\nmov [rax], esi\nadd rax, 4\ncmp rcx, rax\njz short loc_1496\nnop dword ptr [rax+00h]\nloc_1488:\nmov [rax], edx\nadd rax, 8\nmov [rax-4], edx\ncmp rcx, rax\njnz short loc_1488\nloc_1496:\nadd r9d, edi\nloc_1499:\nlea rax, [rsi+1]\ncmp rbx, rsi\njz short loc_14B0\nmov rsi, rax\njmp short loc_1450\nloc_14B0:\npop rbx\nmov rdi, r8; ptr\npop rbp\npop r12\njmp _free\nloc_14BC:\nmov edi, 4; size\nxor ebx, ebx\ncall _malloc\nmov dword ptr [rax], 0\nmov r8, rax\njmp loc_1447", + "ida_strip_pseudo": "void __fastcall sub_13A0(int *a1, int a2)\n{\n __int64 v3; // rbx\n int *v4; // rax\n int *v5; // rcx\n _DWORD *v6; // r8\n __int64 v7; // rax\n __int64 v8; // rdx\n __int64 v9; // rsi\n int v10; // r9d\n int v11; // edi\n int *v12; // rax\n int *v13; // rcx\n _DWORD *v14; // rax\n\n if ( a2 <= 0 )\n {\n v3 = 0LL;\n v14 = malloc(4uLL);\n *v14 = 0;\n v6 = v14;\nLABEL_16:\n v9 = 0LL;\n v10 = 0;\n while ( 1 )\n {\n v11 = v6[v9];\n if ( v11 > 0 )\n {\n v12 = &a1[v10];\n v13 = &a1[v10 + (__int64)v11];\n if ( ((4 * ((_BYTE)v10 + (_BYTE)v11) - 4 * (_BYTE)v10) & 4) == 0 || (*v12 = v9, ++v12, v13 != v12) )\n {\n do\n {\n *v12 = v9;\n v12 += 2;\n *(v12 - 1) = v9;\n }\n while ( v13 != v12 );\n }\n v10 += v11;\n }\n if ( v3 == v9 )\n break;\n ++v9;\n }\n goto LABEL_24;\n }\n v3 = 0LL;\n v4 = a1;\n v5 = &a1[a2];\n if ( (a2 & 1) == 0 )\n goto LABEL_28;\n if ( *a1 > 0 )\n v3 = *a1;\n v4 = a1 + 1;\n if ( v5 != a1 + 1 )\n {\nLABEL_28:\n do\n {\n if ( (int)v3 < *v4 )\n v3 = *v4;\n if ( (int)v3 < v4[1] )\n v3 = v4[1];\n v4 += 2;\n }\n while ( v5 != v4 );\n }\n v6 = malloc(4LL * ((int)v3 + 1));\n if ( (int)v3 >= 0 )\n v6 = memset(v6, 0, 4LL * (int)v3 + 4);\n v7 = 0LL;\n do\n {\n v8 = a1[v7++];\n ++v6[v8];\n }\n while ( a2 > (int)v7 );\n if ( (int)v3 >= 0 )\n goto LABEL_16;\nLABEL_24:\n free(v6);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_13A0(int *a1, int a2) {\n long long v3;\n int *v4;\n int *v5;\n uint32_t *v6;\n long long v7;\n long long v8;\n long long v9;\n int v10;\n int v11;\n int *v12;\n int *v13;\n uint32_t *v14;\n if (a2 <= 0) {\n v3 = 0LL;\n v14 = malloc(4uLL);\n *v14 = 0;\n v6 = v14;\n LABEL_16:\n v9 = 0LL;\n v10 = 0;\n while (1) {\n v11 = v6[v9];\n if (v11 > 0) {\n v12 = &a1[v10];\n v13 = &a1[v10 + (long long)v11];\n if (((4 * ((uint8_t)v10 + (uint8_t)v11) - 4 * (uint8_t)v10) & 4) == 0 ||\n (*v12 = v9, ++v12, v13 != v12)) {\n do {\n *v12 = v9;\n v12 += 2;\n *(v12 - 1) = v9;\n } while (v13 != v12);\n }\n v10 += v11;\n }\n if (v3 == v9) break;\n ++v9;\n }\n goto LABEL_24;\n }\n v3 = 0LL;\n v4 = a1;\n v5 = &a1[a2];\n if ((a2 & 1) == 0) goto LABEL_28;\n if (*a1 > 0) v3 = *a1;\n v4 = a1 + 1;\n if (v5 != a1 + 1) {\n LABEL_28:\n do {\n if ((int)v3 < *v4) v3 = *v4;\n if ((int)v3 < v4[1]) v3 = v4[1];\n v4 += 2;\n } while (v5 != v4);\n }\n v6 = malloc(4LL * ((int)v3 + 1));\n if ((int)v3 >= 0) v6 = memset(v6, 0, 4LL * (int)v3 + 4);\n v7 = 0LL;\n do {\n v8 = a1[v7++];\n ++v6[v8];\n } while (a2 > (int)v7);\n if ((int)v3 >= 0) goto LABEL_16;\nLABEL_24:\n free(v6);\n}", + "ida_pseudo_norm": "void func0(int *a1, int a2) {\n long long v3;\n int *v4;\n int *v5;\n uint32_t *v6;\n long long v7;\n long long v8;\n long long v9;\n int v10;\n int v11;\n int *v12;\n int *v13;\n uint32_t *v14;\n if (a2 <= 0) {\n v3 = 0LL;\n v14 = malloc(4uLL);\n *v14 = 0;\n v6 = v14;\n LABEL_16:\n v9 = 0LL;\n v10 = 0;\n while (1) {\n v11 = v6[v9];\n if (v11 > 0) {\n v12 = &a1[v10];\n v13 = &a1[v10 + (long long)v11];\n if (((4 * ((uint8_t)v10 + (uint8_t)v11) - 4 * (uint8_t)v10) & 4) == 0 ||\n (*v12 = v9, ++v12, v13 != v12)) {\n do {\n *v12 = v9;\n v12 += 2;\n *(v12 - 1) = v9;\n } while (v13 != v12);\n }\n v10 += v11;\n }\n if (v3 == v9) break;\n ++v9;\n }\n goto LABEL_24;\n }\n v3 = 0LL;\n v4 = a1;\n v5 = &a1[a2];\n if ((a2 & 1) == 0) goto LABEL_28;\n if (*a1 > 0) v3 = *a1;\n v4 = a1 + 1;\n if (v5 != a1 + 1) {\n LABEL_28:\n do {\n if ((int)v3 < *v4) v3 = *v4;\n if ((int)v3 < v4[1]) v3 = v4[1];\n v4 += 2;\n } while (v5 != v4);\n }\n v6 = malloc(4LL * ((int)v3 + 1));\n if ((int)v3 >= 0) v6 = memset(v6, 0, 4LL * (int)v3 + 4);\n v7 = 0LL;\n do {\n v8 = a1[v7++];\n ++v6[v8];\n } while (a2 > (int)v7);\n if ((int)v3 >= 0) goto LABEL_16;\nLABEL_24:\n free(v6);\n}" + }, + { + "index": 54, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int *my_list, int n) {\n int max_value = 0;\n for (int i = 0; i < n; i++) {\n if (my_list[i] > max_value) {\n max_value = my_list[i];\n }\n }\n int *buckets = malloc((max_value + 1) * sizeof(int));\n for (int j = 0; j <= max_value; j++) {\n buckets[j] = 0;\n }\n for (int i = 0; i < n; i++) {\n buckets[my_list[i]]++;\n }\n int pos = 0;\n for (int j = 0; j <= max_value; j++) {\n for (int a = 0; a < buckets[j]; a++) {\n my_list[pos] = j;\n pos++;\n }\n }\n free(buckets);\n}", + "test": "int main() {\n\n int list1[] = {1, 23, 4, 5, 6, 7, 8};\n\n int size1 = sizeof(list1) / sizeof(list1[0]);\n\n func0(list1, size1);\n\n assert(list1[0] == 1 && list1[1] == 4 && list1[2] == 5 && list1[3] == 6 && list1[4] == 7 && list1[5] == 8 && list1[6] == 23);\n\n\n\n int list2[] = {12, 9, 28, 33, 69, 45};\n\n int size2 = sizeof(list2) / sizeof(list2[0]);\n\n func0(list2, size2);\n\n assert(list2[0] == 9 && list2[1] == 12 && list2[2] == 28 && list2[3] == 33 && list2[4] == 45 && list2[5] == 69);\n\n\n\n int list3[] = {8, 4, 14, 3, 2, 1};\n\n int size3 = sizeof(list3) / sizeof(list3[0]);\n\n func0(list3, size3);\n\n assert(list3[0] == 1 && list3[1] == 2 && list3[2] == 3 && list3[3] == 4 && list3[4] == 8 && list3[5] == 14);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\ntest %esi,%esi\njle 155c \nlea -0x1(%rsi),%r12d\ncmp $0x2,%r12d\njbe 1579 \nmov %esi,%edx\nmov %rdi,%rax\npxor %xmm2,%xmm2\nshr $0x2,%edx\nshl $0x4,%rdx\nadd %rdi,%rdx\nnopl 0x0(%rax)\nmovdqu (%rax),%xmm0\nadd $0x10,%rax\nmovdqa %xmm0,%xmm1\npcmpgtd %xmm2,%xmm1\npand %xmm1,%xmm0\npandn %xmm2,%xmm1\nmovdqa %xmm1,%xmm2\npor %xmm0,%xmm2\ncmp %rdx,%rax\njne 13d8 \nmovdqa %xmm2,%xmm0\nmov %esi,%eax\npsrldq $0x8,%xmm0\nand $0xfffffffc,%eax\nmovdqa %xmm0,%xmm1\nmovdqa %xmm0,%xmm3\npcmpgtd %xmm2,%xmm1\npand %xmm1,%xmm3\npandn %xmm2,%xmm1\nmovdqa %xmm1,%xmm0\npor %xmm3,%xmm0\nmovdqa %xmm0,%xmm2\npsrldq $0x4,%xmm2\nmovdqa %xmm2,%xmm1\npcmpgtd %xmm0,%xmm1\npand %xmm1,%xmm2\npandn %xmm0,%xmm1\npor %xmm2,%xmm1\nmovd %xmm1,%ebp\ntest $0x3,%sil\nje 147f \nmovslq %eax,%rdx\nmov (%rbx,%rdx,4),%edx\ncmp %edx,%ebp\ncmovl %rdx,%rbp\nlea 0x1(%rax),%edx\ncmp %esi,%edx\njge 147f \nmovslq %edx,%rdx\nmov (%rbx,%rdx,4),%edx\ncmp %edx,%ebp\ncmovl %rdx,%rbp\nadd $0x2,%eax\ncmp %eax,%esi\njle 147f \ncltq\nmov (%rbx,%rax,4),%eax\ncmp %eax,%ebp\ncmovl %rax,%rbp\nlea 0x1(%rbp),%edi\nadd $0x1,%rbp\nmov %r12d,%r12d\nmovslq %edi,%rdi\nshl $0x2,%rdi\ncallq 10d0 \nlea 0x0(,%rbp,4),%rdx\nxor %esi,%esi\nmov %rax,%rdi\ncallq 10c0 \nlea 0x4(%rbx,%r12,4),%rcx\nmov %rax,%rdi\nmov %rbx,%rax\nnopw 0x0(%rax,%rax,1)\nmovslq (%rax),%rdx\nadd $0x4,%rax\naddl $0x1,(%rdi,%rdx,4)\ncmp %rcx,%rax\njne 14b8 \nxor %esi,%esi\nxor %r9d,%r9d\nnopl (%rax)\nmov (%rdi,%rsi,4),%ecx\nmov %esi,%r8d\ntest %ecx,%ecx\njle 1543 \nlea -0x1(%rcx),%eax\ncmp $0x2,%eax\njbe 1555 \nmov %ecx,%edx\nmovslq %r9d,%rax\nmovd %r8d,%xmm4\nshr $0x2,%edx\nlea (%rbx,%rax,4),%rax\npshufd $0x0,%xmm4,%xmm0\nshl $0x4,%rdx\nadd %rax,%rdx\nmovups %xmm0,(%rax)\nadd $0x10,%rax\ncmp %rdx,%rax\njne 1500 \nmov %ecx,%eax\nand $0xfffffffc,%eax\nlea (%r9,%rax,1),%edx\ncmp %eax,%ecx\nje 1540 \nmovslq %edx,%rdx\nmov %r8d,(%rbx,%rdx,4)\nlea 0x0(,%rdx,4),%r10\nlea 0x1(%rax),%edx\ncmp %ecx,%edx\njge 1540 \nadd $0x2,%eax\nmov %r8d,0x4(%rbx,%r10,1)\ncmp %ecx,%eax\njge 1540 \nmov %r8d,0x8(%rbx,%r10,1)\nadd %ecx,%r9d\nadd $0x1,%rsi\ncmp %rbp,%rsi\njne 14d0 \npop %rbx\npop %rbp\npop %r12\njmpq 1090 \nmov %r9d,%edx\nxor %eax,%eax\njmp 1519 \nmov $0x4,%edi\nmov $0x1,%ebp\ncallq 10d0 \nmovl $0x0,(%rax)\nmov %rax,%rdi\njmpq 14c8 \nxor %eax,%eax\nxor %ebp,%ebp\njmpq 144e \nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbx, rdi\ntest esi, esi\njle loc_15A3\nlea eax, [rsi-1]\nmov ebp, esi\ncmp eax, 2\njbe loc_15BE\nmov edx, esi\nmov rax, rdi\npxor xmm2, xmm2\nshr edx, 2\nshl rdx, 4\nadd rdx, rdi\nnop dword ptr [rax+00h]\nloc_13D8:\nmovdqu xmm0, xmmword ptr [rax]\nadd rax, 10h\nmovdqa xmm1, xmm0\npcmpgtd xmm1, xmm2\npand xmm0, xmm1\npandn xmm1, xmm2\nmovdqa xmm2, xmm1\npor xmm2, xmm0\ncmp rax, rdx\njnz short loc_13D8\nmovdqa xmm1, xmm2\nmov eax, ebp\npsrldq xmm1, 8\nand eax, 0FFFFFFFCh\nmovdqa xmm0, xmm1\npcmpgtd xmm0, xmm2\npand xmm1, xmm0\npandn xmm0, xmm2\npor xmm0, xmm1\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\nmovdqa xmm1, xmm2\npcmpgtd xmm1, xmm0\npand xmm2, xmm1\npandn xmm1, xmm0\npor xmm1, xmm2\nmovd r12d, xmm1\ntest bpl, 3\njz short loc_1480\nloc_1447:\nmovsxd rdx, eax\nlea rcx, ds:0[rdx*4]\nmov edx, [rbx+rdx*4]\ncmp r12d, edx\ncmovl r12d, edx\nlea edx, [rax+1]\ncmp ebp, edx\njle short loc_1480\nmov edx, [rbx+rcx+4]\ncmp r12d, edx\ncmovl r12d, edx\nadd eax, 2\ncmp ebp, eax\njle short loc_1480\nmov eax, [rbx+rcx+8]\ncmp r12d, eax\ncmovl r12d, eax\nloc_1480:\nlea edi, [r12+1]\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov r8, rax\ntest r12d, r12d\njs short loc_14B1\nmovsxd rax, r12d\nmov rdi, r8; s\nxor esi, esi; c\nlea rdx, ds:4[rax*4]; n\ncall _memset\nmov r8, rax\nloc_14B1:\nxor eax, eax\nnop dword ptr [rax+rax+00h]\nloc_14B8:\nmovsxd rdx, dword ptr [rbx+rax*4]\nadd rax, 1\nadd dword ptr [r8+rdx*4], 1\ncmp ebp, eax\njg short loc_14B8\ntest r12d, r12d\njs loc_1590\nloc_14D2:\nmovsxd r10, r12d\nxor esi, esi\nxor r9d, r9d\nnop word ptr [rax+rax+00h]\nloc_14E0:\nmov edx, [r8+rsi*4]\nmov edi, esi\ntest edx, edx\njle loc_1577\nlea eax, [rdx-1]\ncmp eax, 2\njbe loc_159C\nmov ecx, edx\nmovsxd rax, r9d\nmovd xmm3, edi\nshr ecx, 2\nlea rax, [rbx+rax*4]\npshufd xmm0, xmm3, 0\nshl rcx, 4\nlea r11, [rcx+rax]\nand ecx, 10h\njz short loc_1530\nmovups xmmword ptr [rax], xmm0\nadd rax, 10h\ncmp r11, rax\njz short loc_1540\nnop dword ptr [rax+rax+00000000h]\nloc_1530:\nmovups xmmword ptr [rax], xmm0\nadd rax, 20h ; ' '\nmovups xmmword ptr [rax-10h], xmm0\ncmp r11, rax\njnz short loc_1530\nloc_1540:\nmov eax, edx\nand eax, 0FFFFFFFCh\nlea ecx, [r9+rax]\ntest dl, 3\njz short loc_1574\nloc_154E:\nmovsxd rcx, ecx\nmov [rbx+rcx*4], edi\nlea r11, ds:0[rcx*4]\nlea ecx, [rax+1]\ncmp ecx, edx\njge short loc_1574\nadd eax, 2\nmov [rbx+r11+4], edi\ncmp edx, eax\njle short loc_1574\nmov [rbx+r11+8], edi\nloc_1574:\nadd r9d, edx\nloc_1577:\nlea rax, [rsi+1]\ncmp r10, rsi\njz short loc_1590\nmov rsi, rax\njmp loc_14E0\nloc_1590:\npop rbx\nmov rdi, r8; ptr\npop rbp\npop r12\njmp _free\nloc_159C:\nmov ecx, r9d\nxor eax, eax\njmp short loc_154E\nloc_15A3:\nmov edi, 4; size\nxor r12d, r12d\ncall _malloc\nmov dword ptr [rax], 0\nmov r8, rax\njmp loc_14D2\nloc_15BE:\nxor eax, eax\nxor r12d, r12d\njmp loc_1447", + "ida_pseudo": "void __fastcall func0(const __m128i *a1, int a2)\n{\n const __m128i *v2; // rax\n __m128i v3; // xmm2\n __m128i v4; // xmm0\n __m128i v5; // xmm1\n __m128i v6; // xmm1\n signed int v7; // eax\n __m128i v8; // xmm0\n __m128i v9; // xmm0\n __m128i v10; // xmm2\n __m128i v11; // xmm1\n int v12; // r12d\n __int64 v13; // rcx\n _DWORD *v14; // r8\n __int64 v15; // rax\n __int64 v16; // rdx\n __int64 v17; // rsi\n int v18; // r9d\n int v19; // edx\n __m128i *v20; // rax\n __m128i v21; // xmm0\n __int64 v22; // rcx\n __m128i *v23; // r11\n int v24; // eax\n int v25; // ecx\n __int64 v26; // r11\n _DWORD *v27; // rax\n\n if ( a2 <= 0 )\n {\n v12 = 0;\n v27 = malloc(4uLL);\n *v27 = 0;\n v14 = v27;\nLABEL_19:\n v17 = 0LL;\n v18 = 0;\n while ( 1 )\n {\n v19 = v14[v17];\n if ( v19 <= 0 )\n goto LABEL_30;\n if ( (unsigned int)(v19 - 1) <= 2 )\n {\n v25 = v18;\n v24 = 0;\n }\n else\n {\n v20 = (__m128i *)((char *)a1 + 4 * v18);\n v21 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v17), 0);\n v22 = (unsigned int)v19 >> 2;\n v23 = &v20[v22];\n if ( ((v22 * 16) & 0x10) == 0 || (*v20 = v21, ++v20, v23 != v20) )\n {\n do\n {\n *v20 = v21;\n v20 += 2;\n v20[-1] = v21;\n }\n while ( v23 != v20 );\n }\n v24 = v19 & 0x7FFFFFFC;\n v25 = v18 + (v19 & 0xFFFFFFFC);\n if ( (v19 & 3) == 0 )\n goto LABEL_29;\n }\n a1->m128i_i32[v25] = v17;\n v26 = v25;\n if ( v24 + 1 < v19 )\n {\n a1->m128i_i32[v26 + 1] = v17;\n if ( v19 > v24 + 2 )\n a1->m128i_i32[v26 + 2] = v17;\n }\nLABEL_29:\n v18 += v19;\nLABEL_30:\n if ( v12 == v17 )\n goto LABEL_32;\n ++v17;\n }\n }\n if ( (unsigned int)(a2 - 1) <= 2 )\n {\n v7 = 0;\n v12 = 0;\n }\n else\n {\n v2 = a1;\n v3 = 0LL;\n do\n {\n v4 = _mm_loadu_si128(v2++);\n v5 = _mm_cmpgt_epi32(v4, v3);\n v3 = _mm_or_si128(_mm_andnot_si128(v5, v3), _mm_and_si128(v4, v5));\n }\n while ( v2 != &a1[(unsigned int)a2 >> 2] );\n v6 = _mm_srli_si128(v3, 8);\n v7 = a2 & 0xFFFFFFFC;\n v8 = _mm_cmpgt_epi32(v6, v3);\n v9 = _mm_or_si128(_mm_andnot_si128(v8, v3), _mm_and_si128(v6, v8));\n v10 = _mm_srli_si128(v9, 4);\n v11 = _mm_cmpgt_epi32(v10, v9);\n v12 = _mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v11, v9), _mm_and_si128(v10, v11)));\n if ( (a2 & 3) == 0 )\n goto LABEL_14;\n }\n v13 = v7;\n if ( v12 < a1->m128i_i32[v13] )\n v12 = a1->m128i_i32[v7];\n if ( a2 > v7 + 1 )\n {\n if ( v12 < a1->m128i_i32[v13 + 1] )\n v12 = a1->m128i_i32[v13 + 1];\n if ( a2 > v7 + 2 && v12 < a1->m128i_i32[v13 + 2] )\n v12 = a1->m128i_i32[v13 + 2];\n }\nLABEL_14:\n v14 = malloc(4LL * (v12 + 1));\n if ( v12 >= 0 )\n v14 = memset(v14, 0, 4LL * v12 + 4);\n v15 = 0LL;\n do\n {\n v16 = a1->m128i_i32[v15++];\n ++v14[v16];\n }\n while ( a2 > (int)v15 );\n if ( v12 >= 0 )\n goto LABEL_19;\nLABEL_32:\n free(v14);\n}", + "ida_strip_asm": "sub_13A0:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbx, rdi\ntest esi, esi\njle loc_15A3\nlea eax, [rsi-1]\nmov ebp, esi\ncmp eax, 2\njbe loc_15BE\nmov edx, esi\nmov rax, rdi\npxor xmm2, xmm2\nshr edx, 2\nshl rdx, 4\nadd rdx, rdi\nnop dword ptr [rax+00h]\nloc_13D8:\nmovdqu xmm0, xmmword ptr [rax]\nadd rax, 10h\nmovdqa xmm1, xmm0\npcmpgtd xmm1, xmm2\npand xmm0, xmm1\npandn xmm1, xmm2\nmovdqa xmm2, xmm1\npor xmm2, xmm0\ncmp rax, rdx\njnz short loc_13D8\nmovdqa xmm1, xmm2\nmov eax, ebp\npsrldq xmm1, 8\nand eax, 0FFFFFFFCh\nmovdqa xmm0, xmm1\npcmpgtd xmm0, xmm2\npand xmm1, xmm0\npandn xmm0, xmm2\npor xmm0, xmm1\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\nmovdqa xmm1, xmm2\npcmpgtd xmm1, xmm0\npand xmm2, xmm1\npandn xmm1, xmm0\npor xmm1, xmm2\nmovd r12d, xmm1\ntest bpl, 3\njz short loc_1480\nloc_1447:\nmovsxd rdx, eax\nlea rcx, ds:0[rdx*4]\nmov edx, [rbx+rdx*4]\ncmp r12d, edx\ncmovl r12d, edx\nlea edx, [rax+1]\ncmp ebp, edx\njle short loc_1480\nmov edx, [rbx+rcx+4]\ncmp r12d, edx\ncmovl r12d, edx\nadd eax, 2\ncmp ebp, eax\njle short loc_1480\nmov eax, [rbx+rcx+8]\ncmp r12d, eax\ncmovl r12d, eax\nloc_1480:\nlea edi, [r12+1]\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov r8, rax\ntest r12d, r12d\njs short loc_14B1\nmovsxd rax, r12d\nmov rdi, r8; s\nxor esi, esi; c\nlea rdx, ds:4[rax*4]; n\ncall _memset\nmov r8, rax\nloc_14B1:\nxor eax, eax\nnop dword ptr [rax+rax+00h]\nloc_14B8:\nmovsxd rdx, dword ptr [rbx+rax*4]\nadd rax, 1\nadd dword ptr [r8+rdx*4], 1\ncmp ebp, eax\njg short loc_14B8\ntest r12d, r12d\njs loc_1590\nloc_14D2:\nmovsxd r10, r12d\nxor esi, esi\nxor r9d, r9d\nnop word ptr [rax+rax+00h]\nloc_14E0:\nmov edx, [r8+rsi*4]\nmov edi, esi\ntest edx, edx\njle loc_1577\nlea eax, [rdx-1]\ncmp eax, 2\njbe loc_159C\nmov ecx, edx\nmovsxd rax, r9d\nmovd xmm3, edi\nshr ecx, 2\nlea rax, [rbx+rax*4]\npshufd xmm0, xmm3, 0\nshl rcx, 4\nlea r11, [rcx+rax]\nand ecx, 10h\njz short loc_1530\nmovups xmmword ptr [rax], xmm0\nadd rax, 10h\ncmp r11, rax\njz short loc_1540\nnop dword ptr [rax+rax+00000000h]\nloc_1530:\nmovups xmmword ptr [rax], xmm0\nadd rax, 20h ; ' '\nmovups xmmword ptr [rax-10h], xmm0\ncmp r11, rax\njnz short loc_1530\nloc_1540:\nmov eax, edx\nand eax, 0FFFFFFFCh\nlea ecx, [r9+rax]\ntest dl, 3\njz short loc_1574\nloc_154E:\nmovsxd rcx, ecx\nmov [rbx+rcx*4], edi\nlea r11, ds:0[rcx*4]\nlea ecx, [rax+1]\ncmp ecx, edx\njge short loc_1574\nadd eax, 2\nmov [rbx+r11+4], edi\ncmp edx, eax\njle short loc_1574\nmov [rbx+r11+8], edi\nloc_1574:\nadd r9d, edx\nloc_1577:\nlea rax, [rsi+1]\ncmp r10, rsi\njz short loc_1590\nmov rsi, rax\njmp loc_14E0\nloc_1590:\npop rbx\nmov rdi, r8; ptr\npop rbp\npop r12\njmp _free\nloc_159C:\nmov ecx, r9d\nxor eax, eax\njmp short loc_154E\nloc_15A3:\nmov edi, 4; size\nxor r12d, r12d\ncall _malloc\nmov dword ptr [rax], 0\nmov r8, rax\njmp loc_14D2\nloc_15BE:\nxor eax, eax\nxor r12d, r12d\njmp loc_1447", + "ida_strip_pseudo": "void __fastcall sub_13A0(const __m128i *a1, int a2)\n{\n const __m128i *v2; // rax\n __m128i v3; // xmm2\n __m128i v4; // xmm0\n __m128i v5; // xmm1\n __m128i v6; // xmm1\n signed int v7; // eax\n __m128i v8; // xmm0\n __m128i v9; // xmm0\n __m128i v10; // xmm2\n __m128i v11; // xmm1\n int v12; // r12d\n __int64 v13; // rcx\n _DWORD *v14; // r8\n __int64 v15; // rax\n __int64 v16; // rdx\n __int64 v17; // rsi\n int v18; // r9d\n int v19; // edx\n __m128i *v20; // rax\n __m128i v21; // xmm0\n __int64 v22; // rcx\n __m128i *v23; // r11\n int v24; // eax\n int v25; // ecx\n __int64 v26; // r11\n _DWORD *v27; // rax\n\n if ( a2 <= 0 )\n {\n v12 = 0;\n v27 = malloc(4uLL);\n *v27 = 0;\n v14 = v27;\nLABEL_19:\n v17 = 0LL;\n v18 = 0;\n while ( 1 )\n {\n v19 = v14[v17];\n if ( v19 <= 0 )\n goto LABEL_30;\n if ( (unsigned int)(v19 - 1) <= 2 )\n {\n v25 = v18;\n v24 = 0;\n }\n else\n {\n v20 = (__m128i *)((char *)a1 + 4 * v18);\n v21 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v17), 0);\n v22 = (unsigned int)v19 >> 2;\n v23 = &v20[v22];\n if ( ((v22 * 16) & 0x10) == 0 || (*v20 = v21, ++v20, v23 != v20) )\n {\n do\n {\n *v20 = v21;\n v20 += 2;\n v20[-1] = v21;\n }\n while ( v23 != v20 );\n }\n v24 = v19 & 0x7FFFFFFC;\n v25 = v18 + (v19 & 0xFFFFFFFC);\n if ( (v19 & 3) == 0 )\n goto LABEL_29;\n }\n a1->m128i_i32[v25] = v17;\n v26 = v25;\n if ( v24 + 1 < v19 )\n {\n a1->m128i_i32[v26 + 1] = v17;\n if ( v19 > v24 + 2 )\n a1->m128i_i32[v26 + 2] = v17;\n }\nLABEL_29:\n v18 += v19;\nLABEL_30:\n if ( v12 == v17 )\n goto LABEL_32;\n ++v17;\n }\n }\n if ( (unsigned int)(a2 - 1) <= 2 )\n {\n v7 = 0;\n v12 = 0;\n }\n else\n {\n v2 = a1;\n v3 = 0LL;\n do\n {\n v4 = _mm_loadu_si128(v2++);\n v5 = _mm_cmpgt_epi32(v4, v3);\n v3 = _mm_or_si128(_mm_andnot_si128(v5, v3), _mm_and_si128(v4, v5));\n }\n while ( v2 != &a1[(unsigned int)a2 >> 2] );\n v6 = _mm_srli_si128(v3, 8);\n v7 = a2 & 0xFFFFFFFC;\n v8 = _mm_cmpgt_epi32(v6, v3);\n v9 = _mm_or_si128(_mm_andnot_si128(v8, v3), _mm_and_si128(v6, v8));\n v10 = _mm_srli_si128(v9, 4);\n v11 = _mm_cmpgt_epi32(v10, v9);\n v12 = _mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v11, v9), _mm_and_si128(v10, v11)));\n if ( (a2 & 3) == 0 )\n goto LABEL_14;\n }\n v13 = v7;\n if ( v12 < a1->m128i_i32[v13] )\n v12 = a1->m128i_i32[v7];\n if ( a2 > v7 + 1 )\n {\n if ( v12 < a1->m128i_i32[v13 + 1] )\n v12 = a1->m128i_i32[v13 + 1];\n if ( a2 > v7 + 2 && v12 < a1->m128i_i32[v13 + 2] )\n v12 = a1->m128i_i32[v13 + 2];\n }\nLABEL_14:\n v14 = malloc(4LL * (v12 + 1));\n if ( v12 >= 0 )\n v14 = memset(v14, 0, 4LL * v12 + 4);\n v15 = 0LL;\n do\n {\n v16 = a1->m128i_i32[v15++];\n ++v14[v16];\n }\n while ( a2 > (int)v15 );\n if ( v12 >= 0 )\n goto LABEL_19;\nLABEL_32:\n free(v14);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_13A0(const __m128i *a1, int a2) {\n const __m128i *v2;\n __m128i v3;\n __m128i v4;\n __m128i v5;\n __m128i v6;\n signed int v7;\n __m128i v8;\n __m128i v9;\n __m128i v10;\n __m128i v11;\n int v12;\n long long v13;\n uint32_t *v14;\n long long v15;\n long long v16;\n long long v17;\n int v18;\n int v19;\n __m128i *v20;\n __m128i v21;\n long long v22;\n __m128i *v23;\n int v24;\n int v25;\n long long v26;\n uint32_t *v27;\n if (a2 <= 0) {\n v12 = 0;\n v27 = malloc(4uLL);\n *v27 = 0;\n v14 = v27;\n LABEL_19:\n v17 = 0LL;\n v18 = 0;\n while (1) {\n v19 = v14[v17];\n if (v19 <= 0) goto LABEL_30;\n if ((unsigned int)(v19 - 1) <= 2) {\n v25 = v18;\n v24 = 0;\n } else {\n v20 = (__m128i *)((char *)a1 + 4 * v18);\n v21 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v17), 0);\n v22 = (unsigned int)v19 >> 2;\n v23 = &v20[v22];\n if (((v22 * 16) & 16) == 0 || (*v20 = v21, ++v20, v23 != v20)) {\n do {\n *v20 = v21;\n v20 += 2;\n v20[-1] = v21;\n } while (v23 != v20);\n }\n v24 = v19 & 2147483644;\n v25 = v18 + (v19 & 4294967292);\n if ((v19 & 3) == 0) goto LABEL_29;\n }\n a1->m128i_i32[v25] = v17;\n v26 = v25;\n if (v24 + 1 < v19) {\n a1->m128i_i32[v26 + 1] = v17;\n if (v19 > v24 + 2) a1->m128i_i32[v26 + 2] = v17;\n }\n LABEL_29:\n v18 += v19;\n LABEL_30:\n if (v12 == v17) goto LABEL_32;\n ++v17;\n }\n }\n if ((unsigned int)(a2 - 1) <= 2) {\n v7 = 0;\n v12 = 0;\n } else {\n v2 = a1;\n v3 = 0LL;\n do {\n v4 = _mm_loadu_si128(v2++);\n v5 = _mm_cmpgt_epi32(v4, v3);\n v3 = _mm_or_si128(_mm_andnot_si128(v5, v3), _mm_and_si128(v4, v5));\n } while (v2 != &a1[(unsigned int)a2 >> 2]);\n v6 = _mm_srli_si128(v3, 8);\n v7 = a2 & 4294967292;\n v8 = _mm_cmpgt_epi32(v6, v3);\n v9 = _mm_or_si128(_mm_andnot_si128(v8, v3), _mm_and_si128(v6, v8));\n v10 = _mm_srli_si128(v9, 4);\n v11 = _mm_cmpgt_epi32(v10, v9);\n v12 = _mm_cvtsi128_si32(\n _mm_or_si128(_mm_andnot_si128(v11, v9), _mm_and_si128(v10, v11)));\n if ((a2 & 3) == 0) goto LABEL_14;\n }\n v13 = v7;\n if (v12 < a1->m128i_i32[v13]) v12 = a1->m128i_i32[v7];\n if (a2 > v7 + 1) {\n if (v12 < a1->m128i_i32[v13 + 1]) v12 = a1->m128i_i32[v13 + 1];\n if (a2 > v7 + 2 && v12 < a1->m128i_i32[v13 + 2])\n v12 = a1->m128i_i32[v13 + 2];\n }\nLABEL_14:\n v14 = malloc(4LL * (v12 + 1));\n if (v12 >= 0) v14 = memset(v14, 0, 4LL * v12 + 4);\n v15 = 0LL;\n do {\n v16 = a1->m128i_i32[v15++];\n ++v14[v16];\n } while (a2 > (int)v15);\n if (v12 >= 0) goto LABEL_19;\nLABEL_32:\n free(v14);\n}", + "ida_pseudo_norm": "void func0(const __m128i *a1, int a2) {\n const __m128i *v2;\n __m128i v3;\n __m128i v4;\n __m128i v5;\n __m128i v6;\n signed int v7;\n __m128i v8;\n __m128i v9;\n __m128i v10;\n __m128i v11;\n int v12;\n long long v13;\n uint32_t *v14;\n long long v15;\n long long v16;\n long long v17;\n int v18;\n int v19;\n __m128i *v20;\n __m128i v21;\n long long v22;\n __m128i *v23;\n int v24;\n int v25;\n long long v26;\n uint32_t *v27;\n if (a2 <= 0) {\n v12 = 0;\n v27 = malloc(4uLL);\n *v27 = 0;\n v14 = v27;\n LABEL_19:\n v17 = 0LL;\n v18 = 0;\n while (1) {\n v19 = v14[v17];\n if (v19 <= 0) goto LABEL_30;\n if ((unsigned int)(v19 - 1) <= 2) {\n v25 = v18;\n v24 = 0;\n } else {\n v20 = (__m128i *)((char *)a1 + 4 * v18);\n v21 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v17), 0);\n v22 = (unsigned int)v19 >> 2;\n v23 = &v20[v22];\n if (((v22 * 16) & 16) == 0 || (*v20 = v21, ++v20, v23 != v20)) {\n do {\n *v20 = v21;\n v20 += 2;\n v20[-1] = v21;\n } while (v23 != v20);\n }\n v24 = v19 & 2147483644;\n v25 = v18 + (v19 & 4294967292);\n if ((v19 & 3) == 0) goto LABEL_29;\n }\n a1->m128i_i32[v25] = v17;\n v26 = v25;\n if (v24 + 1 < v19) {\n a1->m128i_i32[v26 + 1] = v17;\n if (v19 > v24 + 2) a1->m128i_i32[v26 + 2] = v17;\n }\n LABEL_29:\n v18 += v19;\n LABEL_30:\n if (v12 == v17) goto LABEL_32;\n ++v17;\n }\n }\n if ((unsigned int)(a2 - 1) <= 2) {\n v7 = 0;\n v12 = 0;\n } else {\n v2 = a1;\n v3 = 0LL;\n do {\n v4 = _mm_loadu_si128(v2++);\n v5 = _mm_cmpgt_epi32(v4, v3);\n v3 = _mm_or_si128(_mm_andnot_si128(v5, v3), _mm_and_si128(v4, v5));\n } while (v2 != &a1[(unsigned int)a2 >> 2]);\n v6 = _mm_srli_si128(v3, 8);\n v7 = a2 & 4294967292;\n v8 = _mm_cmpgt_epi32(v6, v3);\n v9 = _mm_or_si128(_mm_andnot_si128(v8, v3), _mm_and_si128(v6, v8));\n v10 = _mm_srli_si128(v9, 4);\n v11 = _mm_cmpgt_epi32(v10, v9);\n v12 = _mm_cvtsi128_si32(\n _mm_or_si128(_mm_andnot_si128(v11, v9), _mm_and_si128(v10, v11)));\n if ((a2 & 3) == 0) goto LABEL_14;\n }\n v13 = v7;\n if (v12 < a1->m128i_i32[v13]) v12 = a1->m128i_i32[v7];\n if (a2 > v7 + 1) {\n if (v12 < a1->m128i_i32[v13 + 1]) v12 = a1->m128i_i32[v13 + 1];\n if (a2 > v7 + 2 && v12 < a1->m128i_i32[v13 + 2])\n v12 = a1->m128i_i32[v13 + 2];\n }\nLABEL_14:\n v14 = malloc(4LL * (v12 + 1));\n if (v12 >= 0) v14 = memset(v14, 0, 4LL * v12 + 4);\n v15 = 0LL;\n do {\n v16 = a1->m128i_i32[v15++];\n ++v14[v16];\n } while (a2 > (int)v15);\n if (v12 >= 0) goto LABEL_19;\nLABEL_32:\n free(v14);\n}" + }, + { + "index": 55, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int a, int n, int r) {\n double tn = a * pow(r, n - 1);\n return tn;\n}", + "test": "int main() {\n\n assert(func0(1, 5, 2) == 16);\n\n assert(func0(1, 5, 4) == 256);\n\n assert(func0(2, 6, 3) == 486);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov %edx,-0x1c(%rbp)\ncvtsi2sdl -0x14(%rbp),%xmm2\nmovsd %xmm2,-0x28(%rbp)\nmov -0x18(%rbp),%eax\nsub $0x1,%eax\ncvtsi2sd %eax,%xmm1\ncvtsi2sdl -0x1c(%rbp),%xmm0\ncallq 1060 \nmulsd -0x28(%rbp),%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmovsd -0x8(%rbp),%xmm0\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\npxor xmm2, xmm2\ncvtsi2sd xmm2, [rbp+var_14]\nmovsd [rbp+var_28], xmm2\nmov eax, [rbp+var_18]\nsub eax, 1\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\npxor xmm3, xmm3\ncvtsi2sd xmm3, [rbp+var_1C]\nmovq rax, xmm3\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\nmulsd xmm0, [rbp+var_28]\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "double __fastcall func0(int a1, int a2, int a3)\n{\n return pow((double)a3, (double)(a2 - 1)) * (double)a1;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\npxor xmm2, xmm2\ncvtsi2sd xmm2, [rbp+var_14]\nmovsd [rbp+var_28], xmm2\nmov eax, [rbp+var_18]\nsub eax, 1\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\npxor xmm3, xmm3\ncvtsi2sd xmm3, [rbp+var_1C]\nmovq rax, xmm3\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\nmulsd xmm0, [rbp+var_28]\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "double __fastcall sub_1169(int a1, int a2, int a3)\n{\n return pow((double)a3, (double)(a2 - 1)) * (double)a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1169(int a1, int a2, int a3) {\n return pow((double)a3, (double)(a2 - 1)) * (double)a1;\n}", + "ida_pseudo_norm": "double func0(int a1, int a2, int a3) {\n return pow((double)a3, (double)(a2 - 1)) * (double)a1;\n}" + }, + { + "index": 56, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\nint rev(int num) {\n\n int rev_num = 0;\n\n while (num > 0) {\n\n rev_num = rev_num * 10 + num % 10;\n\n num = num / 10;\n\n }\n\n return rev_num;\n\n}\n\n\n\n", + "func": "int func0(int n) { return (2 * rev(n) == n + 1); }", + "test": "int main() {\n\n assert(func0(70) == 0);\n\n assert(func0(23) == 0);\n\n assert(func0(73) == 1);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x8,%rsp\nmov %edi,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nmov %eax,%edi\ncallq 1149 \nlea (%rax,%rax,1),%edx\nmov -0x4(%rbp),%eax\nadd $0x1,%eax\ncmp %eax,%edx\nsete %al\nmovzbl %al,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 8\nmov [rbp+var_4], edi\nmov eax, [rbp+var_4]\nmov edi, eax\ncall rev\nlea edx, [rax+rax]\nmov eax, [rbp+var_4]\nadd eax, 1\ncmp edx, eax\nsetz al\nmovzx eax, al\nleave\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(unsigned int a1)\n{\n return 2 * (unsigned int)rev(a1) == a1 + 1;\n}", + "ida_strip_asm": "sub_11C4:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 8\nmov [rbp+var_4], edi\nmov eax, [rbp+var_4]\nmov edi, eax\ncall sub_1149\nlea edx, [rax+rax]\nmov eax, [rbp+var_4]\nadd eax, 1\ncmp edx, eax\nsetz al\nmovzx eax, al\nleave\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_11C4(unsigned int a1)\n{\n return 2 * (unsigned int)sub_1149(a1) == a1 + 1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_11C4(unsigned int a1) {\n return 2 * (unsigned int)sub_1149(a1) == a1 + 1;\n}", + "ida_pseudo_norm": "uint8_t func0(unsigned int a1) { return 2 * (unsigned int)rev(a1) == a1 + 1; }" + }, + { + "index": 57, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n for (int i = 0; i < n - 1; i++) {\n for (int j = i + 1; j < n; j++) {\n if (arr[i] < arr[j]) {\n int temp = arr[i];\n arr[i] = arr[j];\n arr[j] = temp;\n }\n }\n }\n int num = arr[0];\n for (int i = 1; i < n; i++) {\n num = num * 10 + arr[i];\n }\n return num;\n}", + "test": "int main() {\n\n int arr1[3] = {1, 2, 3};\n\n int arr2[4] = {4, 5, 6, 1};\n\n int arr3[4] = {1, 2, 3, 9};\n\n \n\n assert(func0(arr1, 3) == 321);\n\n assert(func0(arr2, 4) == 6541);\n\n assert(func0(arr3, 4) == 9321);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmovl $0x0,-0x14(%rbp)\njmpq 1235 \nmov -0x14(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x10(%rbp)\njmpq 1225 \nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njge 1221 \nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x4(%rbp)\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov -0x14(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x28(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rax,%rdx\nmov -0x4(%rbp),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x10(%rbp)\nmov -0x10(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 1192 \naddl $0x1,-0x14(%rbp)\nmov -0x2c(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x14(%rbp)\njl 1184 \nmov -0x28(%rbp),%rax\nmov (%rax),%eax\nmov %eax,-0xc(%rbp)\nmovl $0x1,-0x8(%rbp)\njmp 1283 \nmov -0xc(%rbp),%edx\nmov %edx,%eax\nshl $0x2,%eax\nadd %edx,%eax\nadd %eax,%eax\nmov %eax,%ecx\nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nadd %ecx,%eax\nmov %eax,-0xc(%rbp)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 1256 \nmov -0xc(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_14], 0\njmp loc_1235\nloc_1184:\nmov eax, [rbp+var_14]\nadd eax, 1\nmov [rbp+var_10], eax\njmp loc_1225\nloc_1192:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njge short loc_1221\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nloc_1221:\nadd [rbp+var_10], 1\nloc_1225:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_2C]\njl loc_1192\nadd [rbp+var_14], 1\nloc_1235:\nmov eax, [rbp+var_2C]\nsub eax, 1\ncmp [rbp+var_14], eax\njl loc_1184\nmov rax, [rbp+var_28]\nmov eax, [rax]\nmov [rbp+var_C], eax\nmov [rbp+var_8], 1\njmp short loc_1283\nloc_1256:\nmov edx, [rbp+var_C]\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nmov ecx, eax\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nadd eax, ecx\nmov [rbp+var_C], eax\nadd [rbp+var_8], 1\nloc_1283:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_2C]\njl short loc_1256\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n int i; // [rsp+18h] [rbp-14h]\n int j; // [rsp+1Ch] [rbp-10h]\n unsigned int v5; // [rsp+20h] [rbp-Ch]\n int k; // [rsp+24h] [rbp-8h]\n unsigned int v7; // [rsp+28h] [rbp-4h]\n\n for ( i = 0; i < a2 - 1; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( (int)a1[i] < (int)a1[j] )\n {\n v7 = a1[i];\n a1[i] = a1[j];\n a1[j] = v7;\n }\n }\n }\n v5 = *a1;\n for ( k = 1; k < a2; ++k )\n v5 = 10 * v5 + a1[k];\n return v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_14], 0\njmp loc_1235\nloc_1184:\nmov eax, [rbp+var_14]\nadd eax, 1\nmov [rbp+var_10], eax\njmp loc_1225\nloc_1192:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njge short loc_1221\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nloc_1221:\nadd [rbp+var_10], 1\nloc_1225:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_2C]\njl loc_1192\nadd [rbp+var_14], 1\nloc_1235:\nmov eax, [rbp+var_2C]\nsub eax, 1\ncmp [rbp+var_14], eax\njl loc_1184\nmov rax, [rbp+var_28]\nmov eax, [rax]\nmov [rbp+var_C], eax\nmov [rbp+var_8], 1\njmp short loc_1283\nloc_1256:\nmov edx, [rbp+var_C]\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nmov ecx, eax\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nadd eax, ecx\nmov [rbp+var_C], eax\nadd [rbp+var_8], 1\nloc_1283:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_2C]\njl short loc_1256\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(unsigned int *a1, int a2)\n{\n int i; // [rsp+18h] [rbp-14h]\n int j; // [rsp+1Ch] [rbp-10h]\n unsigned int v5; // [rsp+20h] [rbp-Ch]\n int k; // [rsp+24h] [rbp-8h]\n unsigned int v7; // [rsp+28h] [rbp-4h]\n\n for ( i = 0; i < a2 - 1; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( (int)a1[i] < (int)a1[j] )\n {\n v7 = a1[i];\n a1[i] = a1[j];\n a1[j] = v7;\n }\n }\n }\n v5 = *a1;\n for ( k = 1; k < a2; ++k )\n v5 = 10 * v5 + a1[k];\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(unsigned int *a1, int a2) {\n int i;\n int j;\n unsigned int v5;\n int k;\n unsigned int v7;\n for (i = 0; i < a2 - 1; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if ((int)a1[i] < (int)a1[j]) {\n v7 = a1[i];\n a1[i] = a1[j];\n a1[j] = v7;\n }\n }\n }\n v5 = *a1;\n for (k = 1; k < a2; ++k) v5 = 10 * v5 + a1[k];\n return v5;\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n int i;\n int j;\n unsigned int v5;\n int k;\n unsigned int v7;\n for (i = 0; i < a2 - 1; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if ((int)a1[i] < (int)a1[j]) {\n v7 = a1[i];\n a1[i] = a1[j];\n a1[j] = v7;\n }\n }\n }\n v5 = *a1;\n for (k = 1; k < a2; ++k) v5 = 10 * v5 + a1[k];\n return v5;\n}" + }, + { + "index": 57, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n for (int i = 0; i < n - 1; i++) {\n for (int j = i + 1; j < n; j++) {\n if (arr[i] < arr[j]) {\n int temp = arr[i];\n arr[i] = arr[j];\n arr[j] = temp;\n }\n }\n }\n int num = arr[0];\n for (int i = 1; i < n; i++) {\n num = num * 10 + arr[i];\n }\n return num;\n}", + "test": "int main() {\n\n int arr1[3] = {1, 2, 3};\n\n int arr2[4] = {4, 5, 6, 1};\n\n int arr3[4] = {1, 2, 3, 9};\n\n \n\n assert(func0(arr1, 3) == 321);\n\n assert(func0(arr2, 4) == 6541);\n\n assert(func0(arr3, 4) == 9321);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%esi\njle 11b6 \nmov %rdi,%r8\nlea -0x2(%rsi),%r10d\nadd $0x2,%r10\nmov $0x1,%r9d\njmp 11ac \nadd $0x1,%rax\ncmp %eax,%esi\njle 119f \nmov (%r8),%edx\nmov (%rdi,%rax,4),%ecx\ncmp %ecx,%edx\njge 1185 \nmov %ecx,(%r8)\nmov %edx,(%rdi,%rax,4)\njmp 1185 \nadd $0x1,%r9\nadd $0x4,%r8\ncmp %r10,%r9\nje 11b6 \ncmp %r9d,%esi\njle 119f \nmov %r9,%rax\njmp 118d \nmov (%rdi),%edx\ncmp $0x1,%esi\njle 11da \nlea 0x4(%rdi),%rax\nlea -0x2(%rsi),%ecx\nlea 0x8(%rdi,%rcx,4),%rsi\nlea (%rdx,%rdx,4),%ecx\nmov (%rax),%edx\nlea (%rdx,%rcx,2),%edx\nadd $0x4,%rax\ncmp %rsi,%rax\njne 11c9 \nmov %edx,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\ncmp esi, 1\njle short loc_11F9\nlea r10, [rdi+4]\nlea r12d, [rsi-2]\nmov r11d, esi\nmov rdi, r10\nmov r9d, 1\nlea r13d, [rsi-1]\nlea rbp, [rbx+8]\njmp short loc_11BF\nloc_1199:\nadd rax, 4\ncmp rax, r8\njz short loc_11B2\nloc_11A2:\nmov edx, [rdi-4]\nmov ecx, [rax]\ncmp edx, ecx\njge short loc_1199\nmov [rdi-4], ecx\nmov [rax], edx\njmp short loc_1199\nloc_11B2:\nadd r9, 1\nadd rdi, 4\ncmp r9, r11\njz short loc_11D9\nloc_11BF:\ncmp esi, r9d\njle short loc_11B2\nmov eax, r13d\nsub eax, r9d\nlea rax, [r9+rax-1]\nlea r8, [rbp+rax*4+0]\nmov rax, rdi\njmp short loc_11A2\nloc_11D9:\nmov eax, [rbx]\nlea rcx, [rbx+r12*4+8]\nloc_11E0:\nlea edx, [rax+rax*4]\nmov eax, [r10]\nlea eax, [rax+rdx*2]\nadd r10, 4\ncmp r10, rcx\njnz short loc_11E0\nloc_11F2:\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_11F9:\nmov eax, [rdi]\njmp short loc_11F2", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n unsigned int *v3; // r10\n unsigned int *v4; // rdi\n __int64 i; // r9\n unsigned int *v6; // rax\n signed int v7; // edx\n __int64 result; // rax\n\n if ( a2 <= 1 )\n return *a1;\n v3 = a1 + 1;\n v4 = a1 + 1;\n for ( i = 1LL; i != a2; ++i )\n {\n if ( a2 > (int)i )\n {\n v6 = v4;\n do\n {\n v7 = *(v4 - 1);\n if ( v7 < (int)*v6 )\n {\n *(v4 - 1) = *v6;\n *v6 = v7;\n }\n ++v6;\n }\n while ( v6 != &a1[i + 1 + (unsigned int)(a2 - 1 - i)] );\n }\n ++v4;\n }\n LODWORD(result) = *a1;\n do\n result = *v3++ + 10 * (_DWORD)result;\n while ( v3 != &a1[a2 - 2 + 2] );\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\ncmp esi, 1\njle short loc_11F9\nlea r10, [rdi+4]\nlea r12d, [rsi-2]\nmov r11d, esi\nmov rdi, r10\nmov r9d, 1\nlea r13d, [rsi-1]\nlea rbp, [rbx+8]\njmp short loc_11BF\nloc_1199:\nadd rax, 4\ncmp rax, r8\njz short loc_11B2\nloc_11A2:\nmov edx, [rdi-4]\nmov ecx, [rax]\ncmp edx, ecx\njge short loc_1199\nmov [rdi-4], ecx\nmov [rax], edx\njmp short loc_1199\nloc_11B2:\nadd r9, 1\nadd rdi, 4\ncmp r9, r11\njz short loc_11D9\nloc_11BF:\ncmp esi, r9d\njle short loc_11B2\nmov eax, r13d\nsub eax, r9d\nlea rax, [r9+rax-1]\nlea r8, [rbp+rax*4+0]\nmov rax, rdi\njmp short loc_11A2\nloc_11D9:\nmov eax, [rbx]\nlea rcx, [rbx+r12*4+8]\nloc_11E0:\nlea edx, [rax+rax*4]\nmov eax, [r10]\nlea eax, [rax+rdx*2]\nadd r10, 4\ncmp r10, rcx\njnz short loc_11E0\nloc_11F2:\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_11F9:\nmov eax, [rdi]\njmp short loc_11F2", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(unsigned int *a1, int a2)\n{\n unsigned int *v3; // r10\n unsigned int *v4; // rdi\n __int64 i; // r9\n unsigned int *v6; // rax\n signed int v7; // edx\n __int64 result; // rax\n\n if ( a2 <= 1 )\n return *a1;\n v3 = a1 + 1;\n v4 = a1 + 1;\n for ( i = 1LL; i != a2; ++i )\n {\n if ( a2 > (int)i )\n {\n v6 = v4;\n do\n {\n v7 = *(v4 - 1);\n if ( v7 < (int)*v6 )\n {\n *(v4 - 1) = *v6;\n *v6 = v7;\n }\n ++v6;\n }\n while ( v6 != &a1[i + 1 + (unsigned int)(a2 - 1 - i)] );\n }\n ++v4;\n }\n LODWORD(result) = *a1;\n do\n result = *v3++ + 10 * (_DWORD)result;\n while ( v3 != &a1[a2 - 2 + 2] );\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(unsigned int *a1, int a2) {\n unsigned int *v3;\n unsigned int *v4;\n long long i;\n unsigned int *v6;\n signed int v7;\n long long result;\n if (a2 <= 1) return *a1;\n v3 = a1 + 1;\n v4 = a1 + 1;\n for (i = 1LL; i != a2; ++i) {\n if (a2 > (int)i) {\n v6 = v4;\n do {\n v7 = *(v4 - 1);\n if (v7 < (int)*v6) {\n *(v4 - 1) = *v6;\n *v6 = v7;\n }\n ++v6;\n } while (v6 != &a1[i + 1 + (unsigned int)(a2 - 1 - i)]);\n }\n ++v4;\n }\n LODWORD(result) = *a1;\n do\n result = *v3++ + 10 * (uint32_t)result;\n while (v3 != &a1[a2 - 2 + 2]);\n return result;\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n unsigned int *v3;\n unsigned int *v4;\n long long i;\n unsigned int *v6;\n signed int v7;\n long long result;\n if (a2 <= 1) return *a1;\n v3 = a1 + 1;\n v4 = a1 + 1;\n for (i = 1LL; i != a2; ++i) {\n if (a2 > (int)i) {\n v6 = v4;\n do {\n v7 = *(v4 - 1);\n if (v7 < (int)*v6) {\n *(v4 - 1) = *v6;\n *v6 = v7;\n }\n ++v6;\n } while (v6 != &a1[i + 1 + (unsigned int)(a2 - 1 - i)]);\n }\n ++v4;\n }\n LODWORD(result) = *a1;\n do\n result = *v3++ + 10 * (uint32_t)result;\n while (v3 != &a1[a2 - 2 + 2]);\n return result;\n}" + }, + { + "index": 57, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n for (int i = 0; i < n - 1; i++) {\n for (int j = i + 1; j < n; j++) {\n if (arr[i] < arr[j]) {\n int temp = arr[i];\n arr[i] = arr[j];\n arr[j] = temp;\n }\n }\n }\n int num = arr[0];\n for (int i = 1; i < n; i++) {\n num = num * 10 + arr[i];\n }\n return num;\n}", + "test": "int main() {\n\n int arr1[3] = {1, 2, 3};\n\n int arr2[4] = {4, 5, 6, 1};\n\n int arr3[4] = {1, 2, 3, 9};\n\n \n\n assert(func0(arr1, 3) == 321);\n\n assert(func0(arr2, 4) == 6541);\n\n assert(func0(arr3, 4) == 9321);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%esi\njle 12e5 \nlea -0x2(%rsi),%r10d\nmov %rdi,%r8\nmov $0x1,%r9d\nadd $0x2,%r10\nnopw 0x0(%rax,%rax,1)\ncmp %r9d,%esi\njle 12d8 \nmov %r9,%rax\nnopl 0x0(%rax,%rax,1)\nmov (%r8),%edx\nmov (%rdi,%rax,4),%ecx\ncmp %ecx,%edx\njge 12d0 \nmov %ecx,(%r8)\nmov %edx,(%rdi,%rax,4)\nadd $0x1,%rax\ncmp %eax,%esi\njg 12c0 \nadd $0x1,%r9\nadd $0x4,%r8\ncmp %r10,%r9\njne 12b0 \nmov (%rdi),%r8d\ncmp $0x1,%esi\njle 1313 \nlea -0x2(%rsi),%edx\nlea 0x4(%rdi),%rax\nlea 0x8(%rdi,%rdx,4),%rsi\nnopl 0x0(%rax)\nmov (%rax),%edx\nlea (%r8,%r8,4),%ecx\nadd $0x4,%rax\nlea (%rdx,%rcx,2),%r8d\ncmp %rax,%rsi\njne 1300 \nmov %r8d,%eax\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\ncmp esi, 1\njle loc_1309\nlea r10, [rdi+4]\nlea r12d, [rsi-2]\nmov r11d, esi\nmov r9d, 1\nmov rdi, r10\nlea rbx, [rbp+8]\nlea r13d, [rsi-1]\nnop word ptr [rax+rax+00h]\nloc_12A8:\ncmp esi, r9d\njle short loc_12D7\nmov eax, r13d\nsub eax, r9d\nlea rax, [r9+rax-1]\nlea r8, [rbx+rax*4]\nmov rax, rdi\nnop\nloc_12C0:\nmov edx, [rdi-4]\nmov ecx, [rax]\ncmp edx, ecx\njge short loc_12CE\nmov [rdi-4], ecx\nmov [rax], edx\nloc_12CE:\nadd rax, 4\ncmp rax, r8\njnz short loc_12C0\nloc_12D7:\nadd r9, 1\nadd rdi, 4\ncmp r9, r11\njnz short loc_12A8\nmov eax, [rbp+0]\nlea rcx, [rbx+r12*4]\nnop dword ptr [rax+rax+00h]\nloc_12F0:\nlea edx, [rax+rax*4]\nmov eax, [r10]\nadd r10, 4\nlea eax, [rax+rdx*2]\ncmp rcx, r10\njnz short loc_12F0\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1309:\npop rbx\nmov eax, [rdi]\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n unsigned int *v3; // r10\n __int64 v4; // r9\n unsigned int *v5; // rdi\n unsigned int *v6; // rbx\n unsigned int *v7; // rax\n signed int v8; // edx\n __int64 result; // rax\n int v10; // edx\n int v11; // eax\n\n if ( a2 <= 1 )\n return *a1;\n v3 = a1 + 1;\n v4 = 1LL;\n v5 = a1 + 1;\n v6 = a1 + 2;\n do\n {\n if ( a2 > (int)v4 )\n {\n v7 = v5;\n do\n {\n v8 = *(v5 - 1);\n if ( v8 < (int)*v7 )\n {\n *(v5 - 1) = *v7;\n *v7 = v8;\n }\n ++v7;\n }\n while ( v7 != &v6[v4 - 1 + (unsigned int)(a2 - 1 - v4)] );\n }\n ++v4;\n ++v5;\n }\n while ( v4 != a2 );\n LODWORD(result) = *a1;\n do\n {\n v10 = 5 * result;\n v11 = *v3++;\n result = (unsigned int)(v11 + 2 * v10);\n }\n while ( &v6[a2 - 2] != v3 );\n return result;\n}", + "ida_strip_asm": "sub_1270:\nendbr64\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\ncmp esi, 1\njle loc_1309\nlea r10, [rdi+4]\nlea r12d, [rsi-2]\nmov r11d, esi\nmov r9d, 1\nmov rdi, r10\nlea rbx, [rbp+8]\nlea r13d, [rsi-1]\nnop word ptr [rax+rax+00h]\nloc_12A8:\ncmp esi, r9d\njle short loc_12D7\nmov eax, r13d\nsub eax, r9d\nlea rax, [r9+rax-1]\nlea r8, [rbx+rax*4]\nmov rax, rdi\nnop\nloc_12C0:\nmov edx, [rdi-4]\nmov ecx, [rax]\ncmp edx, ecx\njge short loc_12CE\nmov [rdi-4], ecx\nmov [rax], edx\nloc_12CE:\nadd rax, 4\ncmp rax, r8\njnz short loc_12C0\nloc_12D7:\nadd r9, 1\nadd rdi, 4\ncmp r9, r11\njnz short loc_12A8\nmov eax, [rbp+0]\nlea rcx, [rbx+r12*4]\nnop dword ptr [rax+rax+00h]\nloc_12F0:\nlea edx, [rax+rax*4]\nmov eax, [r10]\nadd r10, 4\nlea eax, [rax+rdx*2]\ncmp rcx, r10\njnz short loc_12F0\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1309:\npop rbx\nmov eax, [rdi]\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1270(unsigned int *a1, int a2)\n{\n unsigned int *v3; // r10\n __int64 v4; // r9\n unsigned int *v5; // rdi\n unsigned int *v6; // rbx\n unsigned int *v7; // rax\n signed int v8; // edx\n __int64 result; // rax\n int v10; // edx\n int v11; // eax\n\n if ( a2 <= 1 )\n return *a1;\n v3 = a1 + 1;\n v4 = 1LL;\n v5 = a1 + 1;\n v6 = a1 + 2;\n do\n {\n if ( a2 > (int)v4 )\n {\n v7 = v5;\n do\n {\n v8 = *(v5 - 1);\n if ( v8 < (int)*v7 )\n {\n *(v5 - 1) = *v7;\n *v7 = v8;\n }\n ++v7;\n }\n while ( v7 != &v6[v4 - 1 + (unsigned int)(a2 - 1 - v4)] );\n }\n ++v4;\n ++v5;\n }\n while ( v4 != a2 );\n LODWORD(result) = *a1;\n do\n {\n v10 = 5 * result;\n v11 = *v3++;\n result = (unsigned int)(v11 + 2 * v10);\n }\n while ( &v6[a2 - 2] != v3 );\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1270(unsigned int *a1, int a2) {\n unsigned int *v3;\n long long v4;\n unsigned int *v5;\n unsigned int *v6;\n unsigned int *v7;\n signed int v8;\n long long result;\n int v10;\n int v11;\n if (a2 <= 1) return *a1;\n v3 = a1 + 1;\n v4 = 1LL;\n v5 = a1 + 1;\n v6 = a1 + 2;\n do {\n if (a2 > (int)v4) {\n v7 = v5;\n do {\n v8 = *(v5 - 1);\n if (v8 < (int)*v7) {\n *(v5 - 1) = *v7;\n *v7 = v8;\n }\n ++v7;\n } while (v7 != &v6[v4 - 1 + (unsigned int)(a2 - 1 - v4)]);\n }\n ++v4;\n ++v5;\n } while (v4 != a2);\n LODWORD(result) = *a1;\n do {\n v10 = 5 * result;\n v11 = *v3++;\n result = (unsigned int)(v11 + 2 * v10);\n } while (&v6[a2 - 2] != v3);\n return result;\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n unsigned int *v3;\n long long v4;\n unsigned int *v5;\n unsigned int *v6;\n unsigned int *v7;\n signed int v8;\n long long result;\n int v10;\n int v11;\n if (a2 <= 1) return *a1;\n v3 = a1 + 1;\n v4 = 1LL;\n v5 = a1 + 1;\n v6 = a1 + 2;\n do {\n if (a2 > (int)v4) {\n v7 = v5;\n do {\n v8 = *(v5 - 1);\n if (v8 < (int)*v7) {\n *(v5 - 1) = *v7;\n *v7 = v8;\n }\n ++v7;\n } while (v7 != &v6[v4 - 1 + (unsigned int)(a2 - 1 - v4)]);\n }\n ++v4;\n ++v5;\n } while (v4 != a2);\n LODWORD(result) = *a1;\n do {\n v10 = 5 * result;\n v11 = *v3++;\n result = (unsigned int)(v11 + 2 * v10);\n } while (&v6[a2 - 2] != v3);\n return result;\n}" + }, + { + "index": 57, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n for (int i = 0; i < n - 1; i++) {\n for (int j = i + 1; j < n; j++) {\n if (arr[i] < arr[j]) {\n int temp = arr[i];\n arr[i] = arr[j];\n arr[j] = temp;\n }\n }\n }\n int num = arr[0];\n for (int i = 1; i < n; i++) {\n num = num * 10 + arr[i];\n }\n return num;\n}", + "test": "int main() {\n\n int arr1[3] = {1, 2, 3};\n\n int arr2[4] = {4, 5, 6, 1};\n\n int arr3[4] = {1, 2, 3, 9};\n\n \n\n assert(func0(arr1, 3) == 321);\n\n assert(func0(arr2, 4) == 6541);\n\n assert(func0(arr3, 4) == 9321);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%esi\njle 12d5 \nlea -0x2(%rsi),%r10d\nmov %rdi,%r8\nmov $0x1,%r9d\nadd $0x2,%r10\nnopw 0x0(%rax,%rax,1)\ncmp %r9d,%esi\njle 12c8 \nmov %r9,%rax\nnopl 0x0(%rax,%rax,1)\nmov (%r8),%edx\nmov (%rdi,%rax,4),%ecx\ncmp %ecx,%edx\njge 12c0 \nmov %ecx,(%r8)\nmov %edx,(%rdi,%rax,4)\nadd $0x1,%rax\ncmp %eax,%esi\njg 12b0 \nadd $0x1,%r9\nadd $0x4,%r8\ncmp %r10,%r9\njne 12a0 \nmov (%rdi),%r8d\ncmp $0x1,%esi\njle 1303 \nlea -0x2(%rsi),%edx\nlea 0x4(%rdi),%rax\nlea 0x8(%rdi,%rdx,4),%rsi\nnopl 0x0(%rax)\nmov (%rax),%edx\nlea (%r8,%r8,4),%ecx\nadd $0x4,%rax\nlea (%rdx,%rcx,2),%r8d\ncmp %rax,%rsi\njne 12f0 \nmov %r8d,%eax\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\ncmp esi, 1\njle loc_1309\nlea r10, [rdi+4]\nlea r12d, [rsi-2]\nmov r11d, esi\nmov r9d, 1\nmov rdi, r10\nlea rbx, [rbp+8]\nlea r13d, [rsi-1]\nnop word ptr [rax+rax+00h]\nloc_12A8:\ncmp esi, r9d\njle short loc_12D7\nmov eax, r13d\nsub eax, r9d\nlea rax, [r9+rax-1]\nlea r8, [rbx+rax*4]\nmov rax, rdi\nnop\nloc_12C0:\nmov edx, [rdi-4]\nmov ecx, [rax]\ncmp edx, ecx\njge short loc_12CE\nmov [rdi-4], ecx\nmov [rax], edx\nloc_12CE:\nadd rax, 4\ncmp r8, rax\njnz short loc_12C0\nloc_12D7:\nadd r9, 1\nadd rdi, 4\ncmp r9, r11\njnz short loc_12A8\nmov eax, [rbp+0]\nlea rcx, [rbx+r12*4]\nnop dword ptr [rax+rax+00h]\nloc_12F0:\nlea edx, [rax+rax*4]\nmov eax, [r10]\nadd r10, 4\nlea eax, [rax+rdx*2]\ncmp rcx, r10\njnz short loc_12F0\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1309:\npop rbx\nmov eax, [rdi]\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n unsigned int *v3; // r10\n __int64 v4; // r9\n unsigned int *v5; // rdi\n unsigned int *v6; // rbx\n unsigned int *v7; // rax\n signed int v8; // edx\n __int64 result; // rax\n int v10; // edx\n int v11; // eax\n\n if ( a2 <= 1 )\n return *a1;\n v3 = a1 + 1;\n v4 = 1LL;\n v5 = a1 + 1;\n v6 = a1 + 2;\n do\n {\n if ( a2 > (int)v4 )\n {\n v7 = v5;\n do\n {\n v8 = *(v5 - 1);\n if ( v8 < (int)*v7 )\n {\n *(v5 - 1) = *v7;\n *v7 = v8;\n }\n ++v7;\n }\n while ( &v6[v4 - 1 + (unsigned int)(a2 - 1 - v4)] != v7 );\n }\n ++v4;\n ++v5;\n }\n while ( v4 != a2 );\n LODWORD(result) = *a1;\n do\n {\n v10 = 5 * result;\n v11 = *v3++;\n result = (unsigned int)(v11 + 2 * v10);\n }\n while ( &v6[a2 - 2] != v3 );\n return result;\n}", + "ida_strip_asm": "sub_1270:\nendbr64\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\ncmp esi, 1\njle loc_1309\nlea r10, [rdi+4]\nlea r12d, [rsi-2]\nmov r11d, esi\nmov r9d, 1\nmov rdi, r10\nlea rbx, [rbp+8]\nlea r13d, [rsi-1]\nnop word ptr [rax+rax+00h]\nloc_12A8:\ncmp esi, r9d\njle short loc_12D7\nmov eax, r13d\nsub eax, r9d\nlea rax, [r9+rax-1]\nlea r8, [rbx+rax*4]\nmov rax, rdi\nnop\nloc_12C0:\nmov edx, [rdi-4]\nmov ecx, [rax]\ncmp edx, ecx\njge short loc_12CE\nmov [rdi-4], ecx\nmov [rax], edx\nloc_12CE:\nadd rax, 4\ncmp r8, rax\njnz short loc_12C0\nloc_12D7:\nadd r9, 1\nadd rdi, 4\ncmp r9, r11\njnz short loc_12A8\nmov eax, [rbp+0]\nlea rcx, [rbx+r12*4]\nnop dword ptr [rax+rax+00h]\nloc_12F0:\nlea edx, [rax+rax*4]\nmov eax, [r10]\nadd r10, 4\nlea eax, [rax+rdx*2]\ncmp rcx, r10\njnz short loc_12F0\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1309:\npop rbx\nmov eax, [rdi]\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1270(unsigned int *a1, int a2)\n{\n unsigned int *v3; // r10\n __int64 v4; // r9\n unsigned int *v5; // rdi\n unsigned int *v6; // rbx\n unsigned int *v7; // rax\n signed int v8; // edx\n __int64 result; // rax\n int v10; // edx\n int v11; // eax\n\n if ( a2 <= 1 )\n return *a1;\n v3 = a1 + 1;\n v4 = 1LL;\n v5 = a1 + 1;\n v6 = a1 + 2;\n do\n {\n if ( a2 > (int)v4 )\n {\n v7 = v5;\n do\n {\n v8 = *(v5 - 1);\n if ( v8 < (int)*v7 )\n {\n *(v5 - 1) = *v7;\n *v7 = v8;\n }\n ++v7;\n }\n while ( &v6[v4 - 1 + (unsigned int)(a2 - 1 - v4)] != v7 );\n }\n ++v4;\n ++v5;\n }\n while ( v4 != a2 );\n LODWORD(result) = *a1;\n do\n {\n v10 = 5 * result;\n v11 = *v3++;\n result = (unsigned int)(v11 + 2 * v10);\n }\n while ( &v6[a2 - 2] != v3 );\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1270(unsigned int *a1, int a2) {\n unsigned int *v3;\n long long v4;\n unsigned int *v5;\n unsigned int *v6;\n unsigned int *v7;\n signed int v8;\n long long result;\n int v10;\n int v11;\n if (a2 <= 1) return *a1;\n v3 = a1 + 1;\n v4 = 1LL;\n v5 = a1 + 1;\n v6 = a1 + 2;\n do {\n if (a2 > (int)v4) {\n v7 = v5;\n do {\n v8 = *(v5 - 1);\n if (v8 < (int)*v7) {\n *(v5 - 1) = *v7;\n *v7 = v8;\n }\n ++v7;\n } while (&v6[v4 - 1 + (unsigned int)(a2 - 1 - v4)] != v7);\n }\n ++v4;\n ++v5;\n } while (v4 != a2);\n LODWORD(result) = *a1;\n do {\n v10 = 5 * result;\n v11 = *v3++;\n result = (unsigned int)(v11 + 2 * v10);\n } while (&v6[a2 - 2] != v3);\n return result;\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n unsigned int *v3;\n long long v4;\n unsigned int *v5;\n unsigned int *v6;\n unsigned int *v7;\n signed int v8;\n long long result;\n int v10;\n int v11;\n if (a2 <= 1) return *a1;\n v3 = a1 + 1;\n v4 = 1LL;\n v5 = a1 + 1;\n v6 = a1 + 2;\n do {\n if (a2 > (int)v4) {\n v7 = v5;\n do {\n v8 = *(v5 - 1);\n if (v8 < (int)*v7) {\n *(v5 - 1) = *v7;\n *v7 = v8;\n }\n ++v7;\n } while (&v6[v4 - 1 + (unsigned int)(a2 - 1 - v4)] != v7);\n }\n ++v4;\n ++v5;\n } while (v4 != a2);\n LODWORD(result) = *a1;\n do {\n v10 = 5 * result;\n v11 = *v3++;\n result = (unsigned int)(v11 + 2 * v10);\n } while (&v6[a2 - 2] != v3);\n return result;\n}" + }, + { + "index": 58, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int x, int y) { return ((x ^ y) < 0); }", + "test": "int main() {\n\n assert(func0(1, -2) == true);\n\n assert(func0(3, 2) == false);\n\n assert(func0(-10, -10) == false);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov %esi,-0x8(%rbp)\nmov -0x4(%rbp),%eax\nxor -0x8(%rbp),%eax\nshr $0x1f,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov eax, [rbp+var_4]\nxor eax, [rbp+var_8]\nshr eax, 1Fh\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1, int a2)\n{\n return (a2 ^ a1) >> 31;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov eax, [rbp+var_4]\nxor eax, [rbp+var_8]\nshr eax, 1Fh\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(unsigned int a1, int a2)\n{\n return (a2 ^ a1) >> 31;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(unsigned int a1, int a2) { return (a2 ^ a1) >> 31; }", + "ida_pseudo_norm": "long long func0(unsigned int a1, int a2) { return (a2 ^ a1) >> 31; }" + }, + { + "index": 59, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) { return 3 * n * n - 2 * n; }", + "test": "int main() {\n\n assert(func0(5) == 65);\n\n assert(func0(10) == 280);\n\n assert(func0(15) == 645);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nimul %eax,%eax\nmov %eax,%edx\nmov %edx,%eax\nadd %eax,%eax\nadd %eax,%edx\nmov -0x4(%rbp),%eax\nadd %eax,%eax\nsub %eax,%edx\nmov %edx,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov eax, [rbp+var_4]\nimul eax, eax\nmov edx, eax\nmov eax, edx\nadd eax, eax\nadd edx, eax\nmov eax, [rbp+var_4]\nadd eax, eax\nsub edx, eax\nmov eax, edx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n return (unsigned int)(3 * a1 * a1 - 2 * a1);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov eax, [rbp+var_4]\nimul eax, eax\nmov edx, eax\nmov eax, edx\nadd eax, eax\nadd edx, eax\nmov eax, [rbp+var_4]\nadd eax, eax\nsub edx, eax\nmov eax, edx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n return (unsigned int)(3 * a1 * a1 - 2 * a1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) { return (unsigned int)(3 * a1 * a1 - 2 * a1); }", + "ida_pseudo_norm": "long long func0(int a1) { return (unsigned int)(3 * a1 * a1 - 2 * a1); }" + }, + { + "index": 60, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int *mls = (int *)malloc(n * sizeof(int));\n int max = 0;\n for (int i = 0; i < n; i++) {\n mls[i] = 1;\n }\n for (int i = 0; i < n; i++) {\n for (int j = 0; j < i; j++) {\n if (abs(arr[i] - arr[j]) <= 1 && mls[i] < mls[j] + 1) {\n mls[i] = mls[j] + 1;\n }\n }\n }\n for (int i = 0; i < n; i++) {\n if (max < mls[i]) {\n max = mls[i];\n }\n }\n free(mls);\n return max;\n}", + "test": "int main() {\n\n int arr1[] = {2, 5, 6, 3, 7, 6, 5, 8};\n\n assert(func0(arr1, 8) == 5);\n\n\n\n int arr2[] = {-2, -1, 5, -1, 4, 0, 3};\n\n assert(func0(arr2, 7) == 4);\n\n\n\n int arr3[] = {9, 11, 13, 15, 18};\n\n assert(func0(arr3, 5) == 1);\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmov -0x2c(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0x1c(%rbp)\nmovl $0x0,-0x18(%rbp)\njmp 121f \nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmovl $0x1,(%rax)\naddl $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 1201 \nmovl $0x0,-0x14(%rbp)\njmpq 1320 \nmovl $0x0,-0x10(%rbp)\njmpq 1310 \nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\nsub %eax,%edx\nmov %edx,%eax\ncmp $0xffffffff,%eax\njl 130c \nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\nsub %eax,%edx\nmov %edx,%eax\ncmp $0x1,%eax\njg 130c \nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x8(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njl 130c \nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x8(%rbp),%rax\nadd %rcx,%rax\nadd $0x1,%edx\nmov %edx,(%rax)\naddl $0x1,-0x10(%rbp)\nmov -0x10(%rbp),%eax\ncmp -0x14(%rbp),%eax\njl 123f \naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 1233 \nmovl $0x0,-0xc(%rbp)\njmp 136d \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x1c(%rbp)\njge 1369 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x1c(%rbp)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 1335 \nmov -0x8(%rbp),%rax\nmov %rax,%rdi\ncallq 1090 \nmov -0x1c(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov [rbp+var_1C], 0\nmov [rbp+var_18], 0\njmp short loc_121F\nloc_1201:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov dword ptr [rax], 1\nadd [rbp+var_18], 1\nloc_121F:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_2C]\njl short loc_1201\nmov [rbp+var_14], 0\njmp loc_131C\nloc_1233:\nmov [rbp+var_10], 0\njmp loc_130C\nloc_123F:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\nsub edx, eax\ncmp edx, 0FFFFFFFFh\njl loc_1308\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\nsub edx, eax\ncmp edx, 1\njg short loc_1308\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_14]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njl short loc_1308\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_14]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rcx\nadd edx, 1\nmov [rax], edx\nloc_1308:\nadd [rbp+var_10], 1\nloc_130C:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_14]\njl loc_123F\nadd [rbp+var_14], 1\nloc_131C:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl loc_1233\nmov [rbp+var_C], 0\njmp short loc_1369\nloc_1331:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_1C], eax\njge short loc_1365\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_1C], eax\nloc_1365:\nadd [rbp+var_C], 1\nloc_1369:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_2C]\njl short loc_1331\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov eax, [rbp+var_1C]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-1Ch]\n int i; // [rsp+18h] [rbp-18h]\n int j; // [rsp+1Ch] [rbp-14h]\n int k; // [rsp+20h] [rbp-10h]\n int m; // [rsp+24h] [rbp-Ch]\n _DWORD *ptr; // [rsp+28h] [rbp-8h]\n\n ptr = malloc(4LL * a2);\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n ptr[i] = 1;\n for ( j = 0; j < a2; ++j )\n {\n for ( k = 0; k < j; ++k )\n {\n if ( *(_DWORD *)(4LL * j + a1) - *(_DWORD *)(4LL * k + a1) >= -1\n && *(_DWORD *)(4LL * j + a1) - *(_DWORD *)(4LL * k + a1) <= 1\n && ptr[k] >= ptr[j] )\n {\n ptr[j] = ptr[k] + 1;\n }\n }\n }\n for ( m = 0; m < a2; ++m )\n {\n if ( (signed int)v3 < ptr[m] )\n v3 = ptr[m];\n }\n free(ptr);\n return v3;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov [rbp+var_1C], 0\nmov [rbp+var_18], 0\njmp short loc_121F\nloc_1201:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov dword ptr [rax], 1\nadd [rbp+var_18], 1\nloc_121F:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_2C]\njl short loc_1201\nmov [rbp+var_14], 0\njmp loc_131C\nloc_1233:\nmov [rbp+var_10], 0\njmp loc_130C\nloc_123F:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\nsub edx, eax\ncmp edx, 0FFFFFFFFh\njl loc_1308\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\nsub edx, eax\ncmp edx, 1\njg short loc_1308\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_14]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njl short loc_1308\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_14]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rcx\nadd edx, 1\nmov [rax], edx\nloc_1308:\nadd [rbp+var_10], 1\nloc_130C:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_14]\njl loc_123F\nadd [rbp+var_14], 1\nloc_131C:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl loc_1233\nmov [rbp+var_C], 0\njmp short loc_1369\nloc_1331:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_1C], eax\njge short loc_1365\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_1C], eax\nloc_1365:\nadd [rbp+var_C], 1\nloc_1369:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_2C]\njl short loc_1331\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov eax, [rbp+var_1C]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11C9(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-1Ch]\n int i; // [rsp+18h] [rbp-18h]\n int j; // [rsp+1Ch] [rbp-14h]\n int k; // [rsp+20h] [rbp-10h]\n int m; // [rsp+24h] [rbp-Ch]\n _DWORD *ptr; // [rsp+28h] [rbp-8h]\n\n ptr = malloc(4LL * a2);\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n ptr[i] = 1;\n for ( j = 0; j < a2; ++j )\n {\n for ( k = 0; k < j; ++k )\n {\n if ( *(_DWORD *)(4LL * j + a1) - *(_DWORD *)(4LL * k + a1) >= -1\n && *(_DWORD *)(4LL * j + a1) - *(_DWORD *)(4LL * k + a1) <= 1\n && ptr[k] >= ptr[j] )\n {\n ptr[j] = ptr[k] + 1;\n }\n }\n }\n for ( m = 0; m < a2; ++m )\n {\n if ( (signed int)v3 < ptr[m] )\n v3 = ptr[m];\n }\n free(ptr);\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11C9(long long a1, int a2) {\n unsigned int v3;\n int i;\n int j;\n int k;\n int m;\n uint32_t *ptr;\n ptr = malloc(4LL * a2);\n v3 = 0;\n for (i = 0; i < a2; ++i) ptr[i] = 1;\n for (j = 0; j < a2; ++j) {\n for (k = 0; k < j; ++k) {\n if (*(uint32_t *)(4LL * j + a1) - *(uint32_t *)(4LL * k + a1) >= -1 &&\n *(uint32_t *)(4LL * j + a1) - *(uint32_t *)(4LL * k + a1) <= 1 &&\n ptr[k] >= ptr[j]) {\n ptr[j] = ptr[k] + 1;\n }\n }\n }\n for (m = 0; m < a2; ++m) {\n if ((signed int)v3 < ptr[m]) v3 = ptr[m];\n }\n free(ptr);\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n int j;\n int k;\n int m;\n uint32_t *ptr;\n ptr = malloc(4LL * a2);\n v3 = 0;\n for (i = 0; i < a2; ++i) ptr[i] = 1;\n for (j = 0; j < a2; ++j) {\n for (k = 0; k < j; ++k) {\n if (*(uint32_t *)(4LL * j + a1) - *(uint32_t *)(4LL * k + a1) >= -1 &&\n *(uint32_t *)(4LL * j + a1) - *(uint32_t *)(4LL * k + a1) <= 1 &&\n ptr[k] >= ptr[j]) {\n ptr[j] = ptr[k] + 1;\n }\n }\n }\n for (m = 0; m < a2; ++m) {\n if ((signed int)v3 < ptr[m]) v3 = ptr[m];\n }\n free(ptr);\n return v3;\n}" + }, + { + "index": 60, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int *mls = (int *)malloc(n * sizeof(int));\n int max = 0;\n for (int i = 0; i < n; i++) {\n mls[i] = 1;\n }\n for (int i = 0; i < n; i++) {\n for (int j = 0; j < i; j++) {\n if (abs(arr[i] - arr[j]) <= 1 && mls[i] < mls[j] + 1) {\n mls[i] = mls[j] + 1;\n }\n }\n }\n for (int i = 0; i < n; i++) {\n if (max < mls[i]) {\n max = mls[i];\n }\n }\n free(mls);\n return max;\n}", + "test": "int main() {\n\n int arr1[] = {2, 5, 6, 3, 7, 6, 5, 8};\n\n assert(func0(arr1, 8) == 5);\n\n\n\n int arr2[] = {-2, -1, 5, -1, 4, 0, 3};\n\n assert(func0(arr2, 7) == 4);\n\n\n\n int arr3[] = {9, 11, 13, 15, 18};\n\n assert(func0(arr3, 5) == 1);\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbx\nmov %esi,%ebp\nmovslq %esi,%rdi\nshl $0x2,%rdi\ncallq 10d0 \nmov %rax,%rdi\ntest %ebp,%ebp\njle 1280 \nmov %rax,%r9\nlea -0x1(%rbp),%r11d\nlea 0x4(%rax,%r11,4),%r10\nmovl $0x1,(%rax)\nadd $0x4,%rax\ncmp %r10,%rax\njne 11fb \nmov $0x0,%esi\nmov $0x0,%ebp\njmp 124c \nlea 0x1(%rdx),%rcx\ncmp %rdx,%rax\nje 1240 \nmov %rcx,%rdx\nmov %r8d,%ecx\nsub (%rbx,%rdx,4),%ecx\nadd $0x1,%ecx\ncmp $0x2,%ecx\nja 1216 \nmov (%rdi,%rdx,4),%ecx\ncmp (%rdi,%rsi,4),%ecx\njl 1216 \nadd $0x1,%ecx\nmov %ecx,(%rdi,%rsi,4)\njmp 1216 \nlea 0x1(%rsi),%rax\ncmp %r11,%rsi\nje 125c \nmov %rax,%rsi\ntest %esi,%esi\njle 1240 \nmov (%rbx,%rsi,4),%r8d\nlea -0x1(%rsi),%eax\nmov %rbp,%rdx\njmp 1222 \nmov $0x0,%ebx\nmov (%r9),%eax\ncmp %eax,%ebx\ncmovl %eax,%ebx\nadd $0x4,%r9\ncmp %r10,%r9\njne 1261 \ncallq 1090 \nmov %ebx,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nmov $0x0,%ebx\njmp 1272 \n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nmov ebp, esi\nmovsxd r11, esi\nlea r12, ds:0[r11*4]\nmov rdi, r12; size\ncall _malloc\nmov rdi, rax; ptr\ntest ebp, ebp\njle loc_1288\nmov r9, rax\nlea r11, [r12+rax]\nloc_11FB:\nmov dword ptr [rax], 1\nadd rax, 4\ncmp rax, r11\njnz short loc_11FB\nmov ecx, 0\nmov r10d, 0\nmov r12d, 0\njmp short loc_124B\nloc_121D:\nlea rdx, [rax+4]\ncmp rax, rcx\njz short loc_1248\nmov rax, rdx\nloc_1229:\nmov edx, esi\nsub edx, [rbx+rax]\nadd edx, 1\ncmp edx, 2\nja short loc_121D\nmov edx, [rdi+rax]\ncmp edx, [rdi+r8]\njl short loc_121D\nadd edx, 1\nmov [rdi+r8], edx\njmp short loc_121D\nloc_1248:\nmov rcx, r8\nloc_124B:\nadd r10d, 1\nlea r8, [rcx+4]\ncmp ebp, r10d\njz short loc_1266\ntest r10d, r10d\njle short loc_1248\nmov esi, [rbx+r8]\nmov rax, r12\njmp short loc_1229\nloc_1266:\nmov ebx, 0\nloc_126B:\nmov eax, [r9]\ncmp ebx, eax\ncmovl ebx, eax\nadd r9, 4\ncmp r9, r11\njnz short loc_126B\nloc_127C:\ncall _free\nmov eax, ebx\npop rbx\npop rbp\npop r12\nretn\nloc_1288:\nmov ebx, 0\njmp short loc_127C", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n char *v4; // rax\n char *v5; // rdi\n char *v6; // r9\n char *v7; // r11\n __int64 v8; // rcx\n int v9; // r10d\n __int64 i; // rax\n int v11; // edx\n __int64 v12; // r8\n int v13; // esi\n unsigned int v14; // ebx\n\n v4 = (char *)malloc(4LL * a2);\n v5 = v4;\n if ( a2 <= 0 )\n {\n v14 = 0;\n }\n else\n {\n v6 = v4;\n v7 = &v4[4 * a2];\n do\n {\n *(_DWORD *)v4 = 1;\n v4 += 4;\n }\n while ( v4 != v7 );\n v8 = 0LL;\n v9 = 0;\n while ( 1 )\n {\n ++v9;\n v12 = v8 + 4;\n if ( a2 == v9 )\n break;\n if ( v9 > 0 )\n {\n v13 = *(_DWORD *)(a1 + v12);\n for ( i = 0LL; ; i += 4LL )\n {\n if ( (unsigned int)(v13 - *(_DWORD *)(a1 + i) + 1) <= 2 )\n {\n v11 = *(_DWORD *)&v5[i];\n if ( v11 >= *(_DWORD *)&v5[v12] )\n *(_DWORD *)&v5[v12] = v11 + 1;\n }\n if ( i == v8 )\n break;\n }\n }\n v8 += 4LL;\n }\n v14 = 0;\n do\n {\n if ( (signed int)v14 < *(_DWORD *)v6 )\n v14 = *(_DWORD *)v6;\n v6 += 4;\n }\n while ( v6 != v7 );\n }\n free(v5);\n return v14;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nmov ebp, esi\nmovsxd r11, esi\nlea r12, ds:0[r11*4]\nmov rdi, r12; size\ncall _malloc\nmov rdi, rax; ptr\ntest ebp, ebp\njle loc_1288\nmov r9, rax\nlea r11, [r12+rax]\nloc_11FB:\nmov dword ptr [rax], 1\nadd rax, 4\ncmp rax, r11\njnz short loc_11FB\nmov ecx, 0\nmov r10d, 0\nmov r12d, 0\njmp short loc_124B\nloc_121D:\nlea rdx, [rax+4]\ncmp rax, rcx\njz short loc_1248\nmov rax, rdx\nloc_1229:\nmov edx, esi\nsub edx, [rbx+rax]\nadd edx, 1\ncmp edx, 2\nja short loc_121D\nmov edx, [rdi+rax]\ncmp edx, [rdi+r8]\njl short loc_121D\nadd edx, 1\nmov [rdi+r8], edx\njmp short loc_121D\nloc_1248:\nmov rcx, r8\nloc_124B:\nadd r10d, 1\nlea r8, [rcx+4]\ncmp ebp, r10d\njz short loc_1266\ntest r10d, r10d\njle short loc_1248\nmov esi, [rbx+r8]\nmov rax, r12\njmp short loc_1229\nloc_1266:\nmov ebx, 0\nloc_126B:\nmov eax, [r9]\ncmp ebx, eax\ncmovl ebx, eax\nadd r9, 4\ncmp r9, r11\njnz short loc_126B\nloc_127C:\ncall _free\nmov eax, ebx\npop rbx\npop rbp\npop r12\nretn\nloc_1288:\nmov ebx, 0\njmp short loc_127C", + "ida_strip_pseudo": "__int64 __fastcall sub_11C9(__int64 a1, int a2)\n{\n char *v4; // rax\n char *v5; // rdi\n char *v6; // r9\n char *v7; // r11\n __int64 v8; // rcx\n int v9; // r10d\n __int64 i; // rax\n int v11; // edx\n __int64 v12; // r8\n int v13; // esi\n unsigned int v14; // ebx\n\n v4 = (char *)malloc(4LL * a2);\n v5 = v4;\n if ( a2 <= 0 )\n {\n v14 = 0;\n }\n else\n {\n v6 = v4;\n v7 = &v4[4 * a2];\n do\n {\n *(_DWORD *)v4 = 1;\n v4 += 4;\n }\n while ( v4 != v7 );\n v8 = 0LL;\n v9 = 0;\n while ( 1 )\n {\n ++v9;\n v12 = v8 + 4;\n if ( a2 == v9 )\n break;\n if ( v9 > 0 )\n {\n v13 = *(_DWORD *)(a1 + v12);\n for ( i = 0LL; ; i += 4LL )\n {\n if ( (unsigned int)(v13 - *(_DWORD *)(a1 + i) + 1) <= 2 )\n {\n v11 = *(_DWORD *)&v5[i];\n if ( v11 >= *(_DWORD *)&v5[v12] )\n *(_DWORD *)&v5[v12] = v11 + 1;\n }\n if ( i == v8 )\n break;\n }\n }\n v8 += 4LL;\n }\n v14 = 0;\n do\n {\n if ( (signed int)v14 < *(_DWORD *)v6 )\n v14 = *(_DWORD *)v6;\n v6 += 4;\n }\n while ( v6 != v7 );\n }\n free(v5);\n return v14;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11C9(long long a1, int a2) {\n char *v4;\n char *v5;\n char *v6;\n char *v7;\n long long v8;\n int v9;\n long long i;\n int v11;\n long long v12;\n int v13;\n unsigned int v14;\n v4 = (char *)malloc(4LL * a2);\n v5 = v4;\n if (a2 <= 0) {\n v14 = 0;\n } else {\n v6 = v4;\n v7 = &v4[4 * a2];\n do {\n *(uint32_t *)v4 = 1;\n v4 += 4;\n } while (v4 != v7);\n v8 = 0LL;\n v9 = 0;\n while (1) {\n ++v9;\n v12 = v8 + 4;\n if (a2 == v9) break;\n if (v9 > 0) {\n v13 = *(uint32_t *)(a1 + v12);\n for (i = 0LL;; i += 4LL) {\n if ((unsigned int)(v13 - *(uint32_t *)(a1 + i) + 1) <= 2) {\n v11 = *(uint32_t *)&v5[i];\n if (v11 >= *(uint32_t *)&v5[v12]) *(uint32_t *)&v5[v12] = v11 + 1;\n }\n if (i == v8) break;\n }\n }\n v8 += 4LL;\n }\n v14 = 0;\n do {\n if ((signed int)v14 < *(uint32_t *)v6) v14 = *(uint32_t *)v6;\n v6 += 4;\n } while (v6 != v7);\n }\n free(v5);\n return v14;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n char *v4;\n char *v5;\n char *v6;\n char *v7;\n long long v8;\n int v9;\n long long i;\n int v11;\n long long v12;\n int v13;\n unsigned int v14;\n v4 = (char *)malloc(4LL * a2);\n v5 = v4;\n if (a2 <= 0) {\n v14 = 0;\n } else {\n v6 = v4;\n v7 = &v4[4 * a2];\n do {\n *(uint32_t *)v4 = 1;\n v4 += 4;\n } while (v4 != v7);\n v8 = 0LL;\n v9 = 0;\n while (1) {\n ++v9;\n v12 = v8 + 4;\n if (a2 == v9) break;\n if (v9 > 0) {\n v13 = *(uint32_t *)(a1 + v12);\n for (i = 0LL;; i += 4LL) {\n if ((unsigned int)(v13 - *(uint32_t *)(a1 + i) + 1) <= 2) {\n v11 = *(uint32_t *)&v5[i];\n if (v11 >= *(uint32_t *)&v5[v12]) *(uint32_t *)&v5[v12] = v11 + 1;\n }\n if (i == v8) break;\n }\n }\n v8 += 4LL;\n }\n v14 = 0;\n do {\n if ((signed int)v14 < *(uint32_t *)v6) v14 = *(uint32_t *)v6;\n v6 += 4;\n } while (v6 != v7);\n }\n free(v5);\n return v14;\n}" + }, + { + "index": 60, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int *mls = (int *)malloc(n * sizeof(int));\n int max = 0;\n for (int i = 0; i < n; i++) {\n mls[i] = 1;\n }\n for (int i = 0; i < n; i++) {\n for (int j = 0; j < i; j++) {\n if (abs(arr[i] - arr[j]) <= 1 && mls[i] < mls[j] + 1) {\n mls[i] = mls[j] + 1;\n }\n }\n }\n for (int i = 0; i < n; i++) {\n if (max < mls[i]) {\n max = mls[i];\n }\n }\n free(mls);\n return max;\n}", + "test": "int main() {\n\n int arr1[] = {2, 5, 6, 3, 7, 6, 5, 8};\n\n assert(func0(arr1, 8) == 5);\n\n\n\n int arr2[] = {-2, -1, 5, -1, 4, 0, 3};\n\n assert(func0(arr2, 7) == 4);\n\n\n\n int arr3[] = {9, 11, 13, 15, 18};\n\n assert(func0(arr3, 5) == 1);\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbx\nmov %rdi,%rbx\nmovslq %esi,%rdi\nmov %rdi,%r12\nshl $0x2,%rdi\nsub $0x8,%rsp\ncallq 10d0 \nmov %rax,%rdi\ntest %r12d,%r12d\njle 141b \nlea -0x1(%r12),%r11d\nmov %rax,%r9\nlea 0x4(%rax,%r11,4),%r10\nnopw %cs:0x0(%rax,%rax,1)\nmovl $0x1,(%rax)\nadd $0x4,%rax\ncmp %r10,%rax\njne 1380 \nxor %esi,%esi\nnopl 0x0(%rax)\ntest %rsi,%rsi\nje 13d8 \nmov (%rbx,%rsi,4),%r8d\nlea -0x1(%rsi),%eax\nxor %edx,%edx\njmp 13b3 \nnopl 0x0(%rax,%rax,1)\nmov %rcx,%rdx\nmov %r8d,%ecx\nsub (%rbx,%rdx,4),%ecx\nadd $0x1,%ecx\ncmp $0x2,%ecx\nja 13cf \nmov (%rdi,%rdx,4),%ecx\ncmp (%rdi,%rsi,4),%ecx\njl 13cf \nadd $0x1,%ecx\nmov %ecx,(%rdi,%rsi,4)\nlea 0x1(%rdx),%rcx\ncmp %rdx,%rax\njne 13b0 \nlea 0x1(%rsi),%rax\ncmp %r11,%rsi\nje 13f0 \nmov %rax,%rsi\njmp 1398 \nnopw %cs:0x0(%rax,%rax,1)\nxor %r12d,%r12d\nnopl 0x0(%rax,%rax,1)\nmov (%r9),%eax\ncmp %eax,%r12d\ncmovl %eax,%r12d\nadd $0x4,%r9\ncmp %r10,%r9\njne 13f8 \ncallq 1090 \nadd $0x8,%rsp\nmov %r12d,%eax\npop %rbx\npop %r12\nretq\ncallq 1090 \nxor %r12d,%r12d\nadd $0x8,%rsp\nmov %r12d,%eax\npop %rbx\npop %r12\nretq\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r12\nmovsxd r12, esi\npush rbp\nmov rbp, r12\nshl r12, 2\npush rbx\nmov rbx, rdi\nmov rdi, r12; size\ncall _malloc\nmov rdi, rax; ptr\ntest ebp, ebp\njle loc_13F6\nlea r11, [r12+rax]\nand r12d, 4\nmov r10, rax\njz short loc_1348\nmov dword ptr [rax], 1\nlea rax, [rax+4]\ncmp rax, r11\njz short loc_135E\nnop dword ptr [rax+00h]\nloc_1348:\nmov dword ptr [rax], 1\nadd rax, 8\nmov dword ptr [rax-4], 1\ncmp rax, r11\njnz short loc_1348\nloc_135E:\nxor r9d, r9d\nxor ecx, ecx\nnop dword ptr [rax+rax+00h]\nloc_1368:\nadd r9d, 1\nmov rsi, rcx\nadd rcx, 4\ncmp ebp, r9d\njz short loc_13B0\nmov r8d, [rbx+rcx]\nxor eax, eax\nxchg ax, ax\nloc_1380:\nmov edx, r8d\nsub edx, [rbx+rax]\nadd edx, 1\ncmp edx, 2\nja short loc_139C\nmov edx, [rdi+rax]\ncmp edx, [rdi+rcx]\njl short loc_139C\nadd edx, 1\nmov [rdi+rcx], edx\nloc_139C:\nlea rdx, [rax+4]\ncmp rax, rsi\njz short loc_1368\nmov rax, rdx\njmp short loc_1380\nloc_13B0:\nmov rax, r11\nxor ebx, ebx\nsub rax, rdi\ntest al, 4\njz short loc_13D0\nmov eax, [rdi]\nlea r10, [rdi+4]\ncmp ebx, eax\ncmovl ebx, eax\ncmp r10, r11\njz short loc_13EA\nnop dword ptr [rax+00h]\nloc_13D0:\nmov eax, [r10]\ncmp ebx, eax\ncmovl ebx, eax\nmov eax, [r10+4]\ncmp ebx, eax\ncmovl ebx, eax\nadd r10, 8\ncmp r10, r11\njnz short loc_13D0\nloc_13EA:\ncall _free\nmov eax, ebx\npop rbx\npop rbp\npop r12\nretn\nloc_13F6:\ncall _free\nxor ebx, ebx\nmov eax, ebx\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n size_t v3; // r12\n int *v5; // rax\n int *v6; // rdi\n int *v7; // r11\n int *v8; // r10\n int v9; // r9d\n __int64 v10; // rcx\n __int64 v11; // rsi\n int v12; // r8d\n unsigned __int64 i; // rax\n int v14; // edx\n int v15; // ebx\n\n v3 = 4LL * a2;\n v5 = (int *)malloc(v3);\n v6 = v5;\n if ( a2 <= 0 )\n {\n free(v5);\n return 0LL;\n }\n else\n {\n v7 = &v5[v3 / 4];\n v8 = v5;\n if ( (v3 & 4) == 0 || (*v5 = 1, ++v5, v5 != v7) )\n {\n do\n {\n *v5 = 1;\n v5 += 2;\n *(v5 - 1) = 1;\n }\n while ( v5 != v7 );\n }\n v9 = 0;\n v10 = 0LL;\n while ( 1 )\n {\n ++v9;\n v11 = v10 * 4;\n ++v10;\n if ( a2 == v9 )\n break;\n v12 = *(_DWORD *)(a1 + v10 * 4);\n for ( i = 0LL; ; i += 4LL )\n {\n if ( (unsigned int)(v12 - *(_DWORD *)(a1 + i) + 1) <= 2 )\n {\n v14 = v6[i / 4];\n if ( v14 >= v6[v10] )\n v6[v10] = v14 + 1;\n }\n if ( i == v11 )\n break;\n }\n }\n v15 = 0;\n if ( (((_BYTE)v7 - (_BYTE)v6) & 4) == 0 )\n goto LABEL_26;\n v8 = v6 + 1;\n if ( *v6 > 0 )\n v15 = *v6;\n if ( v8 != v7 )\n {\nLABEL_26:\n do\n {\n if ( v15 < *v8 )\n v15 = *v8;\n if ( v15 < v8[1] )\n v15 = v8[1];\n v8 += 2;\n }\n while ( v8 != v7 );\n }\n free(v6);\n return (unsigned int)v15;\n }\n}", + "ida_strip_asm": "sub_1300:\nendbr64\npush r12\nmovsxd r12, esi\npush rbp\nmov rbp, r12\nshl r12, 2\npush rbx\nmov rbx, rdi\nmov rdi, r12; size\ncall _malloc\nmov rdi, rax; ptr\ntest ebp, ebp\njle loc_13F6\nlea r11, [r12+rax]\nand r12d, 4\nmov r10, rax\njz short loc_1348\nmov dword ptr [rax], 1\nlea rax, [rax+4]\ncmp rax, r11\njz short loc_135E\nnop dword ptr [rax+00h]\nloc_1348:\nmov dword ptr [rax], 1\nadd rax, 8\nmov dword ptr [rax-4], 1\ncmp rax, r11\njnz short loc_1348\nloc_135E:\nxor r9d, r9d\nxor ecx, ecx\nnop dword ptr [rax+rax+00h]\nloc_1368:\nadd r9d, 1\nmov rsi, rcx\nadd rcx, 4\ncmp ebp, r9d\njz short loc_13B0\nmov r8d, [rbx+rcx]\nxor eax, eax\nxchg ax, ax\nloc_1380:\nmov edx, r8d\nsub edx, [rbx+rax]\nadd edx, 1\ncmp edx, 2\nja short loc_139C\nmov edx, [rdi+rax]\ncmp edx, [rdi+rcx]\njl short loc_139C\nadd edx, 1\nmov [rdi+rcx], edx\nloc_139C:\nlea rdx, [rax+4]\ncmp rax, rsi\njz short loc_1368\nmov rax, rdx\njmp short loc_1380\nloc_13B0:\nmov rax, r11\nxor ebx, ebx\nsub rax, rdi\ntest al, 4\njz short loc_13D0\nmov eax, [rdi]\nlea r10, [rdi+4]\ncmp ebx, eax\ncmovl ebx, eax\ncmp r10, r11\njz short loc_13EA\nnop dword ptr [rax+00h]\nloc_13D0:\nmov eax, [r10]\ncmp ebx, eax\ncmovl ebx, eax\nmov eax, [r10+4]\ncmp ebx, eax\ncmovl ebx, eax\nadd r10, 8\ncmp r10, r11\njnz short loc_13D0\nloc_13EA:\ncall _free\nmov eax, ebx\npop rbx\npop rbp\npop r12\nretn\nloc_13F6:\ncall _free\nxor ebx, ebx\nmov eax, ebx\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1300(__int64 a1, int a2)\n{\n size_t v3; // r12\n int *v5; // rax\n int *v6; // rdi\n int *v7; // r11\n int *v8; // r10\n int v9; // r9d\n __int64 v10; // rcx\n __int64 v11; // rsi\n int v12; // r8d\n unsigned __int64 i; // rax\n int v14; // edx\n int v15; // ebx\n\n v3 = 4LL * a2;\n v5 = (int *)malloc(v3);\n v6 = v5;\n if ( a2 <= 0 )\n {\n free(v5);\n return 0LL;\n }\n else\n {\n v7 = &v5[v3 / 4];\n v8 = v5;\n if ( (v3 & 4) == 0 || (*v5 = 1, ++v5, v5 != v7) )\n {\n do\n {\n *v5 = 1;\n v5 += 2;\n *(v5 - 1) = 1;\n }\n while ( v5 != v7 );\n }\n v9 = 0;\n v10 = 0LL;\n while ( 1 )\n {\n ++v9;\n v11 = v10 * 4;\n ++v10;\n if ( a2 == v9 )\n break;\n v12 = *(_DWORD *)(a1 + v10 * 4);\n for ( i = 0LL; ; i += 4LL )\n {\n if ( (unsigned int)(v12 - *(_DWORD *)(a1 + i) + 1) <= 2 )\n {\n v14 = v6[i / 4];\n if ( v14 >= v6[v10] )\n v6[v10] = v14 + 1;\n }\n if ( i == v11 )\n break;\n }\n }\n v15 = 0;\n if ( (((_BYTE)v7 - (_BYTE)v6) & 4) == 0 )\n goto LABEL_26;\n v8 = v6 + 1;\n if ( *v6 > 0 )\n v15 = *v6;\n if ( v8 != v7 )\n {\nLABEL_26:\n do\n {\n if ( v15 < *v8 )\n v15 = *v8;\n if ( v15 < v8[1] )\n v15 = v8[1];\n v8 += 2;\n }\n while ( v8 != v7 );\n }\n free(v6);\n return (unsigned int)v15;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1300(long long a1, int a2) {\n unsigned int v3;\n int *v5;\n int *v6;\n int *v7;\n int *v8;\n int v9;\n long long v10;\n long long v11;\n int v12;\n unsigned long long i;\n int v14;\n int v15;\n v3 = 4LL * a2;\n v5 = (int *)malloc(v3);\n v6 = v5;\n if (a2 <= 0) {\n free(v5);\n return 0LL;\n } else {\n v7 = &v5[v3 / 4];\n v8 = v5;\n if ((v3 & 4) == 0 || (*v5 = 1, ++v5, v5 != v7)) {\n do {\n *v5 = 1;\n v5 += 2;\n *(v5 - 1) = 1;\n } while (v5 != v7);\n }\n v9 = 0;\n v10 = 0LL;\n while (1) {\n ++v9;\n v11 = v10 * 4;\n ++v10;\n if (a2 == v9) break;\n v12 = *(uint32_t *)(a1 + v10 * 4);\n for (i = 0LL;; i += 4LL) {\n if ((unsigned int)(v12 - *(uint32_t *)(a1 + i) + 1) <= 2) {\n v14 = v6[i / 4];\n if (v14 >= v6[v10]) v6[v10] = v14 + 1;\n }\n if (i == v11) break;\n }\n }\n v15 = 0;\n if ((((uint8_t)v7 - (uint8_t)v6) & 4) == 0) goto LABEL_26;\n v8 = v6 + 1;\n if (*v6 > 0) v15 = *v6;\n if (v8 != v7) {\n LABEL_26:\n do {\n if (v15 < *v8) v15 = *v8;\n if (v15 < v8[1]) v15 = v8[1];\n v8 += 2;\n } while (v8 != v7);\n }\n free(v6);\n return (unsigned int)v15;\n }\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int *v5;\n int *v6;\n int *v7;\n int *v8;\n int v9;\n long long v10;\n long long v11;\n int v12;\n unsigned long long i;\n int v14;\n int v15;\n v3 = 4LL * a2;\n v5 = (int *)malloc(v3);\n v6 = v5;\n if (a2 <= 0) {\n free(v5);\n return 0LL;\n } else {\n v7 = &v5[v3 / 4];\n v8 = v5;\n if ((v3 & 4) == 0 || (*v5 = 1, ++v5, v5 != v7)) {\n do {\n *v5 = 1;\n v5 += 2;\n *(v5 - 1) = 1;\n } while (v5 != v7);\n }\n v9 = 0;\n v10 = 0LL;\n while (1) {\n ++v9;\n v11 = v10 * 4;\n ++v10;\n if (a2 == v9) break;\n v12 = *(uint32_t *)(a1 + v10 * 4);\n for (i = 0LL;; i += 4LL) {\n if ((unsigned int)(v12 - *(uint32_t *)(a1 + i) + 1) <= 2) {\n v14 = v6[i / 4];\n if (v14 >= v6[v10]) v6[v10] = v14 + 1;\n }\n if (i == v11) break;\n }\n }\n v15 = 0;\n if ((((uint8_t)v7 - (uint8_t)v6) & 4) == 0) goto LABEL_26;\n v8 = v6 + 1;\n if (*v6 > 0) v15 = *v6;\n if (v8 != v7) {\n LABEL_26:\n do {\n if (v15 < *v8) v15 = *v8;\n if (v15 < v8[1]) v15 = v8[1];\n v8 += 2;\n } while (v8 != v7);\n }\n free(v6);\n return (unsigned int)v15;\n }\n}" + }, + { + "index": 60, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int *mls = (int *)malloc(n * sizeof(int));\n int max = 0;\n for (int i = 0; i < n; i++) {\n mls[i] = 1;\n }\n for (int i = 0; i < n; i++) {\n for (int j = 0; j < i; j++) {\n if (abs(arr[i] - arr[j]) <= 1 && mls[i] < mls[j] + 1) {\n mls[i] = mls[j] + 1;\n }\n }\n }\n for (int i = 0; i < n; i++) {\n if (max < mls[i]) {\n max = mls[i];\n }\n }\n free(mls);\n return max;\n}", + "test": "int main() {\n\n int arr1[] = {2, 5, 6, 3, 7, 6, 5, 8};\n\n assert(func0(arr1, 8) == 5);\n\n\n\n int arr2[] = {-2, -1, 5, -1, 4, 0, 3};\n\n assert(func0(arr2, 7) == 4);\n\n\n\n int arr3[] = {9, 11, 13, 15, 18};\n\n assert(func0(arr3, 5) == 1);\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nmovslq %esi,%rdi\nmov %rdi,%rbp\nshl $0x2,%rdi\ncallq 10d0 \nmov %rax,%r8\ntest %ebp,%ebp\njle 14ae \nlea -0x1(%rbp),%esi\ncmp $0x2,%esi\njbe 14c1 \nmov %ebp,%edx\nmovdqa 0xd65(%rip),%xmm0\nshr $0x2,%edx\nshl $0x4,%rdx\nadd %rax,%rdx\nnopl (%rax)\nmovups %xmm0,(%rax)\nadd $0x10,%rax\ncmp %rdx,%rax\njne 1348 \nmov %ebp,%eax\nand $0xfffffffc,%eax\ntest $0x3,%bpl\nje 138d \nmovslq %eax,%rdx\nmovl $0x1,(%r8,%rdx,4)\nlea 0x1(%rax),%edx\ncmp %edx,%ebp\njle 138d \nmovslq %edx,%rdx\nadd $0x2,%eax\nmovl $0x1,(%r8,%rdx,4)\ncmp %eax,%ebp\njle 138d \ncltq\nmovl $0x1,(%r8,%rax,4)\nmov $0x1,%edi\ncmp $0x1,%ebp\nje 13d6 \nnopw 0x0(%rax,%rax,1)\nmov (%rbx,%rdi,4),%eax\nxor %edx,%edx\nnopl (%rax)\nmov %eax,%ecx\nsub (%rbx,%rdx,4),%ecx\nadd $0x1,%ecx\ncmp $0x2,%ecx\nja 13c6 \nmov (%r8,%rdx,4),%ecx\ncmp %ecx,(%r8,%rdi,4)\njg 13c6 \nadd $0x1,%ecx\nmov %ecx,(%r8,%rdi,4)\nadd $0x1,%rdx\ncmp %edi,%edx\njl 13a8 \nadd $0x1,%rdi\ncmp %edi,%ebp\njg 13a0 \ncmp $0x2,%esi\njbe 14c8 \nmov %ebp,%edx\nmov %r8,%rax\npxor %xmm2,%xmm2\nshr $0x2,%edx\nshl $0x4,%rdx\nadd %r8,%rdx\nnopw 0x0(%rax,%rax,1)\nmovdqu (%rax),%xmm0\nadd $0x10,%rax\nmovdqa %xmm0,%xmm1\npcmpgtd %xmm2,%xmm1\npand %xmm1,%xmm0\npandn %xmm2,%xmm1\nmovdqa %xmm1,%xmm2\npor %xmm0,%xmm2\ncmp %rdx,%rax\njne 13f8 \nmovdqa %xmm2,%xmm1\nmov %ebp,%eax\npsrldq $0x8,%xmm1\nand $0xfffffffc,%eax\nmovdqa %xmm1,%xmm0\npcmpgtd %xmm2,%xmm0\npand %xmm0,%xmm1\npandn %xmm2,%xmm0\npor %xmm0,%xmm1\nmovdqa %xmm1,%xmm2\npsrldq $0x4,%xmm2\nmovdqa %xmm2,%xmm0\npcmpgtd %xmm1,%xmm0\npand %xmm0,%xmm2\npandn %xmm1,%xmm0\npor %xmm2,%xmm0\nmovd %xmm0,%r12d\ntest $0x3,%bpl\nje 149e \nmovslq %eax,%rdx\nmov (%r8,%rdx,4),%edx\ncmp %edx,%r12d\ncmovl %edx,%r12d\nlea 0x1(%rax),%edx\ncmp %edx,%ebp\njle 149e \nmovslq %edx,%rdx\nmov (%r8,%rdx,4),%edx\ncmp %edx,%r12d\ncmovl %edx,%r12d\nadd $0x2,%eax\ncmp %ebp,%eax\njge 149e \ncltq\nmov (%r8,%rax,4),%eax\ncmp %eax,%r12d\ncmovl %eax,%r12d\nmov %r8,%rdi\ncallq 1090 \nmov %r12d,%eax\npop %rbx\npop %rbp\npop %r12\nretq\nxor %r12d,%r12d\nmov %r8,%rdi\ncallq 1090 \nmov %r12d,%eax\npop %rbx\npop %rbp\npop %r12\nretq\nxor %eax,%eax\njmpq 135f \nxor %eax,%eax\nxor %r12d,%r12d\njmp 1467 \n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rdi\nmovsxd rdi, esi\npush rbx\nmov rbx, rdi\nshl rdi, 2; size\nsub rsp, 8\ncall _malloc\nmov rdi, rax; ptr\ntest ebx, ebx\njle loc_14BE\nlea r8d, [rbx-1]\ncmp r8d, 2\njbe loc_14CE\nmov edx, ebx\nmovdqa xmm0, cs:xmmword_2080\nshr edx, 2\nshl rdx, 4\nlea rcx, [rdx+rax]\nand edx, 10h\njz short loc_1360\nmovups xmmword ptr [rax], xmm0\nlea rax, [rax+10h]\ncmp rax, rcx\njz short loc_1370\nnop dword ptr [rax+rax+00h]\nloc_1360:\nmovups xmmword ptr [rax], xmm0\nadd rax, 20h ; ' '\nmovups xmmword ptr [rax-10h], xmm0\ncmp rax, rcx\njnz short loc_1360\nloc_1370:\nmov eax, ebx\nand eax, 0FFFFFFFCh\ntest bl, 3\njz short loc_13A9\nmov ecx, eax\nmov dword ptr [rdi+rcx*4], 1\nlea rdx, ds:0[rcx*4]\nlea ecx, [rax+1]\ncmp ebx, ecx\njle short loc_13A9\nloc_1392:\nadd eax, 2\nmov dword ptr [rdi+rdx+4], 1\ncmp ebx, eax\njle short loc_13A9\nmov dword ptr [rdi+rdx+8], 1\nloc_13A9:\nmov r9d, ebx\nmov ecx, 1\nnop dword ptr [rax+00000000h]\nloc_13B8:\nmov esi, [rbp+rcx*4+0]\nxor eax, eax\nxchg ax, ax\nloc_13C0:\nmov edx, esi\nsub edx, [rbp+rax*4+0]\nadd edx, 1\ncmp edx, 2\nja short loc_13DC\nmov edx, [rdi+rax*4]\ncmp [rdi+rcx*4], edx\njg short loc_13DC\nadd edx, 1\nmov [rdi+rcx*4], edx\nloc_13DC:\nadd rax, 1\ncmp eax, ecx\njl short loc_13C0\nadd rcx, 1\ncmp rcx, r9\njnz short loc_13B8\ncmp r8d, 2\njbe loc_14E8\nmov edx, ebx\nmov rax, rdi\npxor xmm2, xmm2\nshr edx, 2\nshl rdx, 4\nadd rdx, rdi\nnop word ptr [rax+rax+00h]\nloc_1410:\nmovdqu xmm0, xmmword ptr [rax]\nadd rax, 10h\nmovdqa xmm1, xmm0\npcmpgtd xmm1, xmm2\npand xmm0, xmm1\npandn xmm1, xmm2\nmovdqa xmm2, xmm1\npor xmm2, xmm0\ncmp rax, rdx\njnz short loc_1410\nmovdqa xmm0, xmm2\nmov eax, ebx\npsrldq xmm0, 8\nand eax, 0FFFFFFFCh\nmovdqa xmm1, xmm0\npcmpgtd xmm1, xmm2\npand xmm0, xmm1\npandn xmm1, xmm2\npor xmm1, xmm0\nmovdqa xmm2, xmm1\npsrldq xmm2, 4\nmovdqa xmm0, xmm2\npcmpgtd xmm0, xmm1\npand xmm2, xmm0\npandn xmm0, xmm1\npor xmm0, xmm2\nmovd ebp, xmm0\ntest bl, 3\njz short loc_14B0\nmovsxd rdx, eax\nlea rcx, ds:0[rdx*4]\nmov edx, [rdi+rdx*4]\ncmp ebp, edx\ncmovl ebp, edx\nlea edx, [rax+1]\ncmp ebx, edx\njle short loc_14B0\nloc_1497:\nmov edx, [rdi+rcx+4]\ncmp ebp, edx\ncmovl ebp, edx\nadd eax, 2\ncmp eax, ebx\njge short loc_14B0\nmov eax, [rdi+rcx+8]\ncmp ebp, eax\ncmovl ebp, eax\nloc_14B0:\ncall _free\nadd rsp, 8\nmov eax, ebp\npop rbx\npop rbp\nretn\nloc_14BE:\ncall _free\nxor ebp, ebp\nadd rsp, 8\nmov eax, ebp\npop rbx\npop rbp\nretn\nloc_14CE:\nmov dword ptr [rax], 1\nxor edx, edx\nxor eax, eax\ncmp ebx, 1\njnz loc_1392\nmov ebp, 1\njmp short loc_14B0\nloc_14E8:\nmov ebp, [rdi]\nxor eax, eax\ntest ebp, ebp\ncmovs ebp, eax\nxor ecx, ecx\njmp short loc_1497", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __m128i *v4; // rax\n __m128i *v5; // rdi\n unsigned int v6; // r8d\n __m128i si128; // xmm0\n __int64 v8; // rdx\n __m128i *v9; // rcx\n unsigned int v10; // eax\n __int64 v11; // rdx\n __int64 v12; // rcx\n int v13; // esi\n __int64 v14; // rax\n __int32 v15; // edx\n const __m128i *v16; // rax\n __m128i v17; // xmm2\n __m128i v18; // xmm0\n __m128i v19; // xmm1\n __m128i v20; // xmm0\n signed int v21; // eax\n __m128i v22; // xmm1\n __m128i v23; // xmm1\n __m128i v24; // xmm2\n __m128i v25; // xmm0\n int v26; // ebp\n __int64 v27; // rcx\n\n v4 = (__m128i *)malloc(4LL * a2);\n v5 = v4;\n if ( a2 > 0 )\n {\n v6 = a2 - 1;\n if ( (unsigned int)(a2 - 1) <= 2 )\n {\n v4->m128i_i32[0] = 1;\n v11 = 0LL;\n v10 = 0;\n if ( a2 == 1 )\n {\n v26 = 1;\n goto LABEL_29;\n }\n }\n else\n {\n si128 = _mm_load_si128((const __m128i *)&xmmword_2080);\n v8 = (unsigned int)a2 >> 2;\n v9 = &v4[v8];\n if ( ((v8 * 16) & 0x10) == 0 || (*v4 = si128, ++v4, v4 != v9) )\n {\n do\n {\n *v4 = si128;\n v4 += 2;\n v4[-1] = si128;\n }\n while ( v4 != v9 );\n }\n v10 = a2 & 0x7FFFFFFC;\n if ( (a2 & 3) == 0 )\n goto LABEL_10;\n v5->m128i_i32[v10] = 1;\n v11 = v10;\n if ( a2 <= (int)(v10 + 1) )\n goto LABEL_10;\n }\n v5->m128i_i32[v11 + 1] = 1;\n if ( a2 > (int)(v10 + 2) )\n v5->m128i_i32[v11 + 2] = 1;\nLABEL_10:\n v12 = 1LL;\n do\n {\n v13 = *(_DWORD *)(a1 + 4 * v12);\n v14 = 0LL;\n do\n {\n if ( (unsigned int)(v13 - *(_DWORD *)(a1 + 4 * v14) + 1) <= 2 )\n {\n v15 = v5->m128i_i32[v14];\n if ( v5->m128i_i32[v12] <= v15 )\n v5->m128i_i32[v12] = v15 + 1;\n }\n ++v14;\n }\n while ( (int)v14 < (int)v12 );\n ++v12;\n }\n while ( v12 != a2 );\n if ( v6 <= 2 )\n {\n v26 = v5->m128i_i32[0];\n v21 = 0;\n if ( v5->m128i_i32[0] < 0 )\n v26 = 0;\n v27 = 0LL;\n }\n else\n {\n v16 = v5;\n v17 = 0LL;\n do\n {\n v18 = _mm_loadu_si128(v16++);\n v19 = _mm_cmpgt_epi32(v18, v17);\n v17 = _mm_or_si128(_mm_andnot_si128(v19, v17), _mm_and_si128(v18, v19));\n }\n while ( v16 != &v5[(unsigned int)a2 >> 2] );\n v20 = _mm_srli_si128(v17, 8);\n v21 = a2 & 0xFFFFFFFC;\n v22 = _mm_cmpgt_epi32(v20, v17);\n v23 = _mm_or_si128(_mm_andnot_si128(v22, v17), _mm_and_si128(v20, v22));\n v24 = _mm_srli_si128(v23, 4);\n v25 = _mm_cmpgt_epi32(v24, v23);\n v26 = _mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v25, v23), _mm_and_si128(v24, v25)));\n if ( (a2 & 3) == 0 )\n goto LABEL_29;\n v27 = v21;\n if ( v26 < v5->m128i_i32[v27] )\n v26 = v5->m128i_i32[v21];\n if ( a2 <= v21 + 1 )\n goto LABEL_29;\n }\n if ( v26 < v5->m128i_i32[v27 + 1] )\n v26 = v5->m128i_i32[v27 + 1];\n if ( v21 + 2 < a2 && v26 < v5->m128i_i32[v27 + 2] )\n v26 = v5->m128i_i32[v27 + 2];\nLABEL_29:\n free(v5);\n return (unsigned int)v26;\n }\n free(v4);\n return 0LL;\n}", + "ida_strip_asm": "sub_1300:\nendbr64\npush rbp\nmov rbp, rdi\nmovsxd rdi, esi\npush rbx\nmov rbx, rdi\nshl rdi, 2; size\nsub rsp, 8\ncall _malloc\nmov rdi, rax; ptr\ntest ebx, ebx\njle loc_14BE\nlea r8d, [rbx-1]\ncmp r8d, 2\njbe loc_14CE\nmov edx, ebx\nmovdqa xmm0, cs:xmmword_2080\nshr edx, 2\nshl rdx, 4\nlea rcx, [rdx+rax]\nand edx, 10h\njz short loc_1360\nmovups xmmword ptr [rax], xmm0\nlea rax, [rax+10h]\ncmp rax, rcx\njz short loc_1370\nnop dword ptr [rax+rax+00h]\nloc_1360:\nmovups xmmword ptr [rax], xmm0\nadd rax, 20h ; ' '\nmovups xmmword ptr [rax-10h], xmm0\ncmp rax, rcx\njnz short loc_1360\nloc_1370:\nmov eax, ebx\nand eax, 0FFFFFFFCh\ntest bl, 3\njz short loc_13A9\nmov ecx, eax\nmov dword ptr [rdi+rcx*4], 1\nlea rdx, ds:0[rcx*4]\nlea ecx, [rax+1]\ncmp ebx, ecx\njle short loc_13A9\nloc_1392:\nadd eax, 2\nmov dword ptr [rdi+rdx+4], 1\ncmp ebx, eax\njle short loc_13A9\nmov dword ptr [rdi+rdx+8], 1\nloc_13A9:\nmov r9d, ebx\nmov ecx, 1\nnop dword ptr [rax+00000000h]\nloc_13B8:\nmov esi, [rbp+rcx*4+0]\nxor eax, eax\nxchg ax, ax\nloc_13C0:\nmov edx, esi\nsub edx, [rbp+rax*4+0]\nadd edx, 1\ncmp edx, 2\nja short loc_13DC\nmov edx, [rdi+rax*4]\ncmp [rdi+rcx*4], edx\njg short loc_13DC\nadd edx, 1\nmov [rdi+rcx*4], edx\nloc_13DC:\nadd rax, 1\ncmp eax, ecx\njl short loc_13C0\nadd rcx, 1\ncmp rcx, r9\njnz short loc_13B8\ncmp r8d, 2\njbe loc_14E8\nmov edx, ebx\nmov rax, rdi\npxor xmm2, xmm2\nshr edx, 2\nshl rdx, 4\nadd rdx, rdi\nnop word ptr [rax+rax+00h]\nloc_1410:\nmovdqu xmm0, xmmword ptr [rax]\nadd rax, 10h\nmovdqa xmm1, xmm0\npcmpgtd xmm1, xmm2\npand xmm0, xmm1\npandn xmm1, xmm2\nmovdqa xmm2, xmm1\npor xmm2, xmm0\ncmp rax, rdx\njnz short loc_1410\nmovdqa xmm0, xmm2\nmov eax, ebx\npsrldq xmm0, 8\nand eax, 0FFFFFFFCh\nmovdqa xmm1, xmm0\npcmpgtd xmm1, xmm2\npand xmm0, xmm1\npandn xmm1, xmm2\npor xmm1, xmm0\nmovdqa xmm2, xmm1\npsrldq xmm2, 4\nmovdqa xmm0, xmm2\npcmpgtd xmm0, xmm1\npand xmm2, xmm0\npandn xmm0, xmm1\npor xmm0, xmm2\nmovd ebp, xmm0\ntest bl, 3\njz short loc_14B0\nmovsxd rdx, eax\nlea rcx, ds:0[rdx*4]\nmov edx, [rdi+rdx*4]\ncmp ebp, edx\ncmovl ebp, edx\nlea edx, [rax+1]\ncmp ebx, edx\njle short loc_14B0\nloc_1497:\nmov edx, [rdi+rcx+4]\ncmp ebp, edx\ncmovl ebp, edx\nadd eax, 2\ncmp eax, ebx\njge short loc_14B0\nmov eax, [rdi+rcx+8]\ncmp ebp, eax\ncmovl ebp, eax\nloc_14B0:\ncall _free\nadd rsp, 8\nmov eax, ebp\npop rbx\npop rbp\nretn\nloc_14BE:\ncall _free\nxor ebp, ebp\nadd rsp, 8\nmov eax, ebp\npop rbx\npop rbp\nretn\nloc_14CE:\nmov dword ptr [rax], 1\nxor edx, edx\nxor eax, eax\ncmp ebx, 1\njnz loc_1392\nmov ebp, 1\njmp short loc_14B0\nloc_14E8:\nmov ebp, [rdi]\nxor eax, eax\ntest ebp, ebp\ncmovs ebp, eax\nxor ecx, ecx\njmp short loc_1497", + "ida_strip_pseudo": "__int64 __fastcall sub_1300(__int64 a1, int a2)\n{\n __m128i *v4; // rax\n __m128i *v5; // rdi\n unsigned int v6; // r8d\n __m128i si128; // xmm0\n __int64 v8; // rdx\n __m128i *v9; // rcx\n unsigned int v10; // eax\n __int64 v11; // rdx\n __int64 v12; // rcx\n int v13; // esi\n __int64 v14; // rax\n __int32 v15; // edx\n const __m128i *v16; // rax\n __m128i v17; // xmm2\n __m128i v18; // xmm0\n __m128i v19; // xmm1\n __m128i v20; // xmm0\n signed int v21; // eax\n __m128i v22; // xmm1\n __m128i v23; // xmm1\n __m128i v24; // xmm2\n __m128i v25; // xmm0\n int v26; // ebp\n __int64 v27; // rcx\n\n v4 = (__m128i *)malloc(4LL * a2);\n v5 = v4;\n if ( a2 > 0 )\n {\n v6 = a2 - 1;\n if ( (unsigned int)(a2 - 1) <= 2 )\n {\n v4->m128i_i32[0] = 1;\n v11 = 0LL;\n v10 = 0;\n if ( a2 == 1 )\n {\n v26 = 1;\n goto LABEL_29;\n }\n }\n else\n {\n si128 = _mm_load_si128((const __m128i *)&xmmword_2080);\n v8 = (unsigned int)a2 >> 2;\n v9 = &v4[v8];\n if ( ((v8 * 16) & 0x10) == 0 || (*v4 = si128, ++v4, v4 != v9) )\n {\n do\n {\n *v4 = si128;\n v4 += 2;\n v4[-1] = si128;\n }\n while ( v4 != v9 );\n }\n v10 = a2 & 0x7FFFFFFC;\n if ( (a2 & 3) == 0 )\n goto LABEL_10;\n v5->m128i_i32[v10] = 1;\n v11 = v10;\n if ( a2 <= (int)(v10 + 1) )\n goto LABEL_10;\n }\n v5->m128i_i32[v11 + 1] = 1;\n if ( a2 > (int)(v10 + 2) )\n v5->m128i_i32[v11 + 2] = 1;\nLABEL_10:\n v12 = 1LL;\n do\n {\n v13 = *(_DWORD *)(a1 + 4 * v12);\n v14 = 0LL;\n do\n {\n if ( (unsigned int)(v13 - *(_DWORD *)(a1 + 4 * v14) + 1) <= 2 )\n {\n v15 = v5->m128i_i32[v14];\n if ( v5->m128i_i32[v12] <= v15 )\n v5->m128i_i32[v12] = v15 + 1;\n }\n ++v14;\n }\n while ( (int)v14 < (int)v12 );\n ++v12;\n }\n while ( v12 != a2 );\n if ( v6 <= 2 )\n {\n v26 = v5->m128i_i32[0];\n v21 = 0;\n if ( v5->m128i_i32[0] < 0 )\n v26 = 0;\n v27 = 0LL;\n }\n else\n {\n v16 = v5;\n v17 = 0LL;\n do\n {\n v18 = _mm_loadu_si128(v16++);\n v19 = _mm_cmpgt_epi32(v18, v17);\n v17 = _mm_or_si128(_mm_andnot_si128(v19, v17), _mm_and_si128(v18, v19));\n }\n while ( v16 != &v5[(unsigned int)a2 >> 2] );\n v20 = _mm_srli_si128(v17, 8);\n v21 = a2 & 0xFFFFFFFC;\n v22 = _mm_cmpgt_epi32(v20, v17);\n v23 = _mm_or_si128(_mm_andnot_si128(v22, v17), _mm_and_si128(v20, v22));\n v24 = _mm_srli_si128(v23, 4);\n v25 = _mm_cmpgt_epi32(v24, v23);\n v26 = _mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v25, v23), _mm_and_si128(v24, v25)));\n if ( (a2 & 3) == 0 )\n goto LABEL_29;\n v27 = v21;\n if ( v26 < v5->m128i_i32[v27] )\n v26 = v5->m128i_i32[v21];\n if ( a2 <= v21 + 1 )\n goto LABEL_29;\n }\n if ( v26 < v5->m128i_i32[v27 + 1] )\n v26 = v5->m128i_i32[v27 + 1];\n if ( v21 + 2 < a2 && v26 < v5->m128i_i32[v27 + 2] )\n v26 = v5->m128i_i32[v27 + 2];\nLABEL_29:\n free(v5);\n return (unsigned int)v26;\n }\n free(v4);\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1300(long long a1, int a2) {\n __m128i *v4;\n __m128i *v5;\n unsigned int v6;\n __m128i si128;\n long long v8;\n __m128i *v9;\n unsigned int v10;\n long long v11;\n long long v12;\n int v13;\n long long v14;\n int v15;\n const __m128i *v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n __m128i v20;\n signed int v21;\n __m128i v22;\n __m128i v23;\n __m128i v24;\n __m128i v25;\n int v26;\n long long v27;\n v4 = (__m128i *)malloc(4LL * a2);\n v5 = v4;\n if (a2 > 0) {\n v6 = a2 - 1;\n if ((unsigned int)(a2 - 1) <= 2) {\n v4->m128i_i32[0] = 1;\n v11 = 0LL;\n v10 = 0;\n if (a2 == 1) {\n v26 = 1;\n goto LABEL_29;\n }\n } else {\n si128 = _mm_load_si128((const __m128i *)&xmmword_2080);\n v8 = (unsigned int)a2 >> 2;\n v9 = &v4[v8];\n if (((v8 * 16) & 16) == 0 || (*v4 = si128, ++v4, v4 != v9)) {\n do {\n *v4 = si128;\n v4 += 2;\n v4[-1] = si128;\n } while (v4 != v9);\n }\n v10 = a2 & 2147483644;\n if ((a2 & 3) == 0) goto LABEL_10;\n v5->m128i_i32[v10] = 1;\n v11 = v10;\n if (a2 <= (int)(v10 + 1)) goto LABEL_10;\n }\n v5->m128i_i32[v11 + 1] = 1;\n if (a2 > (int)(v10 + 2)) v5->m128i_i32[v11 + 2] = 1;\n LABEL_10:\n v12 = 1LL;\n do {\n v13 = *(uint32_t *)(a1 + 4 * v12);\n v14 = 0LL;\n do {\n if ((unsigned int)(v13 - *(uint32_t *)(a1 + 4 * v14) + 1) <= 2) {\n v15 = v5->m128i_i32[v14];\n if (v5->m128i_i32[v12] <= v15) v5->m128i_i32[v12] = v15 + 1;\n }\n ++v14;\n } while ((int)v14 < (int)v12);\n ++v12;\n } while (v12 != a2);\n if (v6 <= 2) {\n v26 = v5->m128i_i32[0];\n v21 = 0;\n if (v5->m128i_i32[0] < 0) v26 = 0;\n v27 = 0LL;\n } else {\n v16 = v5;\n v17 = 0LL;\n do {\n v18 = _mm_loadu_si128(v16++);\n v19 = _mm_cmpgt_epi32(v18, v17);\n v17 = _mm_or_si128(_mm_andnot_si128(v19, v17), _mm_and_si128(v18, v19));\n } while (v16 != &v5[(unsigned int)a2 >> 2]);\n v20 = _mm_srli_si128(v17, 8);\n v21 = a2 & 4294967292;\n v22 = _mm_cmpgt_epi32(v20, v17);\n v23 = _mm_or_si128(_mm_andnot_si128(v22, v17), _mm_and_si128(v20, v22));\n v24 = _mm_srli_si128(v23, 4);\n v25 = _mm_cmpgt_epi32(v24, v23);\n v26 = _mm_cvtsi128_si32(\n _mm_or_si128(_mm_andnot_si128(v25, v23), _mm_and_si128(v24, v25)));\n if ((a2 & 3) == 0) goto LABEL_29;\n v27 = v21;\n if (v26 < v5->m128i_i32[v27]) v26 = v5->m128i_i32[v21];\n if (a2 <= v21 + 1) goto LABEL_29;\n }\n if (v26 < v5->m128i_i32[v27 + 1]) v26 = v5->m128i_i32[v27 + 1];\n if (v21 + 2 < a2 && v26 < v5->m128i_i32[v27 + 2])\n v26 = v5->m128i_i32[v27 + 2];\n LABEL_29:\n free(v5);\n return (unsigned int)v26;\n }\n free(v4);\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n __m128i *v4;\n __m128i *v5;\n unsigned int v6;\n __m128i si128;\n long long v8;\n __m128i *v9;\n unsigned int v10;\n long long v11;\n long long v12;\n int v13;\n long long v14;\n int v15;\n const __m128i *v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n __m128i v20;\n signed int v21;\n __m128i v22;\n __m128i v23;\n __m128i v24;\n __m128i v25;\n int v26;\n long long v27;\n v4 = (__m128i *)malloc(4LL * a2);\n v5 = v4;\n if (a2 > 0) {\n v6 = a2 - 1;\n if ((unsigned int)(a2 - 1) <= 2) {\n v4->m128i_i32[0] = 1;\n v11 = 0LL;\n v10 = 0;\n if (a2 == 1) {\n v26 = 1;\n goto LABEL_29;\n }\n } else {\n si128 = _mm_load_si128((const __m128i *)&xmmword_2080);\n v8 = (unsigned int)a2 >> 2;\n v9 = &v4[v8];\n if (((v8 * 16) & 16) == 0 || (*v4 = si128, ++v4, v4 != v9)) {\n do {\n *v4 = si128;\n v4 += 2;\n v4[-1] = si128;\n } while (v4 != v9);\n }\n v10 = a2 & 2147483644;\n if ((a2 & 3) == 0) goto LABEL_10;\n v5->m128i_i32[v10] = 1;\n v11 = v10;\n if (a2 <= (int)(v10 + 1)) goto LABEL_10;\n }\n v5->m128i_i32[v11 + 1] = 1;\n if (a2 > (int)(v10 + 2)) v5->m128i_i32[v11 + 2] = 1;\n LABEL_10:\n v12 = 1LL;\n do {\n v13 = *(uint32_t *)(a1 + 4 * v12);\n v14 = 0LL;\n do {\n if ((unsigned int)(v13 - *(uint32_t *)(a1 + 4 * v14) + 1) <= 2) {\n v15 = v5->m128i_i32[v14];\n if (v5->m128i_i32[v12] <= v15) v5->m128i_i32[v12] = v15 + 1;\n }\n ++v14;\n } while ((int)v14 < (int)v12);\n ++v12;\n } while (v12 != a2);\n if (v6 <= 2) {\n v26 = v5->m128i_i32[0];\n v21 = 0;\n if (v5->m128i_i32[0] < 0) v26 = 0;\n v27 = 0LL;\n } else {\n v16 = v5;\n v17 = 0LL;\n do {\n v18 = _mm_loadu_si128(v16++);\n v19 = _mm_cmpgt_epi32(v18, v17);\n v17 = _mm_or_si128(_mm_andnot_si128(v19, v17), _mm_and_si128(v18, v19));\n } while (v16 != &v5[(unsigned int)a2 >> 2]);\n v20 = _mm_srli_si128(v17, 8);\n v21 = a2 & 4294967292;\n v22 = _mm_cmpgt_epi32(v20, v17);\n v23 = _mm_or_si128(_mm_andnot_si128(v22, v17), _mm_and_si128(v20, v22));\n v24 = _mm_srli_si128(v23, 4);\n v25 = _mm_cmpgt_epi32(v24, v23);\n v26 = _mm_cvtsi128_si32(\n _mm_or_si128(_mm_andnot_si128(v25, v23), _mm_and_si128(v24, v25)));\n if ((a2 & 3) == 0) goto LABEL_29;\n v27 = v21;\n if (v26 < v5->m128i_i32[v27]) v26 = v5->m128i_i32[v21];\n if (a2 <= v21 + 1) goto LABEL_29;\n }\n if (v26 < v5->m128i_i32[v27 + 1]) v26 = v5->m128i_i32[v27 + 1];\n if (v21 + 2 < a2 && v26 < v5->m128i_i32[v27 + 2])\n v26 = v5->m128i_i32[v27 + 2];\n LABEL_29:\n free(v5);\n return (unsigned int)v26;\n }\n free(v4);\n return 0LL;\n}" + }, + { + "index": 61, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *s, int n) {\n int count = 0, sum = 0;\n int max_sum = n * 9;\n int min_sum = -n;\n int size = max_sum - min_sum + 1;\n int *mp = calloc(size, sizeof(int));\n if (!mp) {\n perror(\"Memory allocation failed\");\n exit(EXIT_FAILURE);\n }\n mp[-min_sum] += 1;\n for (int i = 0; i < n; i++) {\n sum += s[i] - '0';\n int key = sum - (i + 1);\n if (key >= min_sum && key <= max_sum) {\n count += mp[key - min_sum];\n mp[key - min_sum] += 1;\n }\n }\n free(mp);\n return count;\n}", + "test": "int main() {\n\n assert(func0(\"112112\", 6) == 6);\n\n assert(func0(\"111\", 3) == 6);\n\n assert(func0(\"1101112\", 7) == 12);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x40,%rsp\nmov %rdi,-0x38(%rbp)\nmov %esi,-0x3c(%rbp)\nmovl $0x0,-0x24(%rbp)\nmovl $0x0,-0x20(%rbp)\nmov -0x3c(%rbp),%edx\nmov %edx,%eax\nshl $0x3,%eax\nadd %edx,%eax\nmov %eax,-0x18(%rbp)\nmov -0x3c(%rbp),%eax\nneg %eax\nmov %eax,-0x14(%rbp)\nmov -0x18(%rbp),%eax\nsub -0x14(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x10(%rbp)\nmov -0x10(%rbp),%eax\ncltq\nmov $0x4,%esi\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\ncmpq $0x0,-0x8(%rbp)\njne 123e \nlea 0xdd9(%rip),%rdi\ncallq 10c0 \nmov $0x1,%edi\ncallq 10d0 \nmov -0x14(%rbp),%eax\nneg %eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x14(%rbp),%eax\nneg %eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x8(%rbp),%rax\nadd %rcx,%rax\nadd $0x1,%edx\nmov %edx,(%rax)\nmovl $0x0,-0x1c(%rbp)\njmpq 1309 \nmov -0x1c(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmovsbl %al,%eax\nsub $0x30,%eax\nadd %eax,-0x20(%rbp)\nmov -0x1c(%rbp),%eax\nlea 0x1(%rax),%edx\nmov -0x20(%rbp),%eax\nsub %edx,%eax\nmov %eax,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x14(%rbp),%eax\njl 1305 \nmov -0xc(%rbp),%eax\ncmp -0x18(%rbp),%eax\njg 1305 \nmov -0xc(%rbp),%eax\nsub -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nadd %eax,-0x24(%rbp)\nmov -0xc(%rbp),%eax\nsub -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0xc(%rbp),%eax\nsub -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x8(%rbp),%rax\nadd %rcx,%rax\nadd $0x1,%edx\nmov %edx,(%rax)\naddl $0x1,-0x1c(%rbp)\nmov -0x1c(%rbp),%eax\ncmp -0x3c(%rbp),%eax\njl 127d \nmov -0x8(%rbp),%rax\nmov %rax,%rdi\ncallq 1090 \nmov -0x24(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov [rbp+var_24], 0\nmov [rbp+var_20], 0\nmov edx, [rbp+var_3C]\nmov eax, edx\nshl eax, 3\nadd eax, edx\nmov [rbp+var_18], eax\nmov eax, [rbp+var_3C]\nneg eax\nmov [rbp+var_14], eax\nmov eax, [rbp+var_18]\nsub eax, [rbp+var_14]\nadd eax, 1\nmov [rbp+var_10], eax\nmov eax, [rbp+var_10]\ncdqe\nmov esi, 4; size\nmov rdi, rax; nmemb\ncall _calloc\nmov [rbp+ptr], rax\ncmp [rbp+ptr], 0\njnz short loc_1241\nlea rax, s; \"Memory allocation failed\"\nmov rdi, rax; s\ncall _perror\nmov edi, 1; status\ncall _exit\nloc_1241:\nmov eax, [rbp+var_14]\nneg eax\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_14]\nneg eax\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rcx\nadd edx, 1\nmov [rax], edx\nmov [rbp+var_1C], 0\njmp loc_130C\nloc_1280:\nmov eax, [rbp+var_1C]\nmovsxd rdx, eax\nmov rax, [rbp+var_38]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nsub eax, 30h ; '0'\nadd [rbp+var_20], eax\nmov eax, [rbp+var_1C]\nlea edx, [rax+1]\nmov eax, [rbp+var_20]\nsub eax, edx\nmov [rbp+var_C], eax\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_14]\njl short loc_1308\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_18]\njg short loc_1308\nmov eax, [rbp+var_C]\nsub eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_24], eax\nmov eax, [rbp+var_C]\nsub eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_C]\nsub eax, [rbp+var_14]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rcx\nadd edx, 1\nmov [rax], edx\nloc_1308:\nadd [rbp+var_1C], 1\nloc_130C:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_3C]\njl loc_1280\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov eax, [rbp+var_24]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+1Ch] [rbp-24h]\n int v4; // [rsp+20h] [rbp-20h]\n int i; // [rsp+24h] [rbp-1Ch]\n int v6; // [rsp+34h] [rbp-Ch]\n _DWORD *ptr; // [rsp+38h] [rbp-8h]\n\n v3 = 0;\n v4 = 0;\n ptr = calloc(10 * a2 + 1, 4uLL);\n if ( !ptr )\n {\n perror(\"Memory allocation failed\");\n exit(1);\n }\n ++ptr[a2];\n for ( i = 0; i < a2; ++i )\n {\n v4 += *(char *)(i + a1) - 48;\n v6 = v4 - (i + 1);\n if ( v6 >= -a2 && v6 <= 9 * a2 )\n v3 += ptr[v6 + a2]++;\n }\n free(ptr);\n return v3;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov [rbp+var_24], 0\nmov [rbp+var_20], 0\nmov edx, [rbp+var_3C]\nmov eax, edx\nshl eax, 3\nadd eax, edx\nmov [rbp+var_18], eax\nmov eax, [rbp+var_3C]\nneg eax\nmov [rbp+var_14], eax\nmov eax, [rbp+var_18]\nsub eax, [rbp+var_14]\nadd eax, 1\nmov [rbp+var_10], eax\nmov eax, [rbp+var_10]\ncdqe\nmov esi, 4; size\nmov rdi, rax; nmemb\ncall _calloc\nmov [rbp+ptr], rax\ncmp [rbp+ptr], 0\njnz short loc_1241\nlea rax, s; \"Memory allocation failed\"\nmov rdi, rax; s\ncall _perror\nmov edi, 1; status\ncall _exit\nloc_1241:\nmov eax, [rbp+var_14]\nneg eax\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_14]\nneg eax\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rcx\nadd edx, 1\nmov [rax], edx\nmov [rbp+var_1C], 0\njmp loc_130C\nloc_1280:\nmov eax, [rbp+var_1C]\nmovsxd rdx, eax\nmov rax, [rbp+var_38]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nsub eax, 30h ; '0'\nadd [rbp+var_20], eax\nmov eax, [rbp+var_1C]\nlea edx, [rax+1]\nmov eax, [rbp+var_20]\nsub eax, edx\nmov [rbp+var_C], eax\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_14]\njl short loc_1308\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_18]\njg short loc_1308\nmov eax, [rbp+var_C]\nsub eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_24], eax\nmov eax, [rbp+var_C]\nsub eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_C]\nsub eax, [rbp+var_14]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rcx\nadd edx, 1\nmov [rax], edx\nloc_1308:\nadd [rbp+var_1C], 1\nloc_130C:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_3C]\njl loc_1280\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov eax, [rbp+var_24]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11C9(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+1Ch] [rbp-24h]\n int v4; // [rsp+20h] [rbp-20h]\n int i; // [rsp+24h] [rbp-1Ch]\n int v6; // [rsp+34h] [rbp-Ch]\n _DWORD *ptr; // [rsp+38h] [rbp-8h]\n\n v3 = 0;\n v4 = 0;\n ptr = calloc(10 * a2 + 1, 4uLL);\n if ( !ptr )\n {\n perror(\"Memory allocation failed\");\n exit(1);\n }\n ++ptr[a2];\n for ( i = 0; i < a2; ++i )\n {\n v4 += *(char *)(i + a1) - 48;\n v6 = v4 - (i + 1);\n if ( v6 >= -a2 && v6 <= 9 * a2 )\n v3 += ptr[v6 + a2]++;\n }\n free(ptr);\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11C9(long long a1, int a2) {\n unsigned int v3;\n int v4;\n int i;\n int v6;\n uint32_t *ptr;\n v3 = 0;\n v4 = 0;\n ptr = calloc(10 * a2 + 1, 4uLL);\n if (!ptr) {\n perror(\"Memory allocation failed\");\n exit(1);\n }\n ++ptr[a2];\n for (i = 0; i < a2; ++i) {\n v4 += *(char *)(i + a1) - 48;\n v6 = v4 - (i + 1);\n if (v6 >= -a2 && v6 <= 9 * a2) v3 += ptr[v6 + a2]++;\n }\n free(ptr);\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int v4;\n int i;\n int v6;\n uint32_t *ptr;\n v3 = 0;\n v4 = 0;\n ptr = calloc(10 * a2 + 1, 4uLL);\n if (!ptr) {\n perror(\"Memory allocation failed\");\n exit(1);\n }\n ++ptr[a2];\n for (i = 0; i < a2; ++i) {\n v4 += *(char *)(i + a1) - 48;\n v6 = v4 - (i + 1);\n if (v6 >= -a2 && v6 <= 9 * a2) v3 += ptr[v6 + a2]++;\n }\n free(ptr);\n return v3;\n}" + }, + { + "index": 61, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *s, int n) {\n int count = 0, sum = 0;\n int max_sum = n * 9;\n int min_sum = -n;\n int size = max_sum - min_sum + 1;\n int *mp = calloc(size, sizeof(int));\n if (!mp) {\n perror(\"Memory allocation failed\");\n exit(EXIT_FAILURE);\n }\n mp[-min_sum] += 1;\n for (int i = 0; i < n; i++) {\n sum += s[i] - '0';\n int key = sum - (i + 1);\n if (key >= min_sum && key <= max_sum) {\n count += mp[key - min_sum];\n mp[key - min_sum] += 1;\n }\n }\n free(mp);\n return count;\n}", + "test": "int main() {\n\n assert(func0(\"112112\", 6) == 6);\n\n assert(func0(\"111\", 3) == 6);\n\n assert(func0(\"1101112\", 7) == 12);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbp\nmov %esi,%ebx\nlea (%rsi,%rsi,8),%eax\nmov %eax,%r14d\nmov %esi,%r13d\nneg %r13d\nlea 0x1(%rsi,%rax,1),%edi\nmovslq %edi,%rdi\nmov $0x4,%esi\ncallq 10b0 \ntest %rax,%rax\nje 1223 \nmov %rax,%rdi\nmovslq %ebx,%rax\naddl $0x1,(%rdi,%rax,4)\ntest %ebx,%ebx\njle 1270 \nlea -0x1(%rbx),%eax\nadd $0x2,%rax\nmov $0x1,%ecx\nmov $0x0,%esi\nmov $0x0,%r12d\njmp 1257 \nlea 0xdda(%rip),%rdi\ncallq 10c0 \nmov $0x1,%edi\ncallq 10d0 \nadd %ebx,%edx\nmovslq %edx,%rdx\nlea (%rdi,%rdx,4),%r8\nmov (%r8),%edx\nadd %edx,%r12d\nadd $0x1,%edx\nmov %edx,(%r8)\nadd $0x1,%rcx\ncmp %rax,%rcx\nje 1276 \nmovsbl -0x1(%rbp,%rcx,1),%edx\nlea -0x30(%rsi,%rdx,1),%esi\nmov %esi,%edx\nsub %ecx,%edx\ncmp %edx,%r13d\njg 124e \ncmp %edx,%r14d\njge 1239 \njmp 124e \nmov $0x0,%r12d\ncallq 1090 \nmov %r12d,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbp, rdi\nmov ebx, esi\nlea r14d, [rsi+rsi*8]\nmov r13d, esi\nneg r13d\nlea edi, [rsi+r14+1]\nmovsxd rdi, edi; nmemb\nmov esi, 4; size\ncall _calloc\ntest rax, rax\njz short loc_121B\nmov rdi, rax; ptr\nmovsxd rsi, ebx\nadd dword ptr [rax+rsi*4], 1\ntest ebx, ebx\njle short loc_126A\nmov edx, 1\nmov ecx, 0\nmov r12d, 0\njmp short loc_1251\nloc_121B:\nlea rdi, s; \"Memory allocation failed\"\ncall _perror\nmov edi, 1; status\ncall _exit\nloc_1231:\nadd eax, ebx\ncdqe\nlea r8, [rdi+rax*4]\nmov eax, [r8]\nadd r12d, eax\nadd eax, 1\nmov [r8], eax\nloc_1245:\nlea rax, [rdx+1]\ncmp rsi, rdx\njz short loc_1270\nmov rdx, rax\nloc_1251:\nmovsx eax, byte ptr [rbp+rdx-1]\nlea ecx, [rcx+rax-30h]\nmov eax, ecx\nsub eax, edx\ncmp r13d, eax\njg short loc_1245\ncmp r14d, eax\njge short loc_1231\njmp short loc_1245\nloc_126A:\nmov r12d, 0\nloc_1270:\ncall _free\nmov eax, r12d\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n char *v3; // rax\n char *v4; // rdi\n __int64 v5; // rdx\n int v6; // ecx\n unsigned int v7; // r12d\n char *v8; // r8\n int v9; // eax\n\n v3 = (char *)calloc(10 * a2 + 1, 4uLL);\n if ( !v3 )\n {\n perror(\"Memory allocation failed\");\n exit(1);\n }\n v4 = v3;\n ++*(_DWORD *)&v3[4 * a2];\n if ( a2 <= 0 )\n {\n v7 = 0;\n }\n else\n {\n v5 = 1LL;\n v6 = 0;\n v7 = 0;\n while ( 1 )\n {\n v6 = v6 + *(char *)(a1 + v5 - 1) - 48;\n v9 = v6 - v5;\n if ( -a2 <= v6 - (int)v5 && 9 * a2 >= v9 )\n {\n v8 = &v4[4 * a2 + 4 * v9];\n v7 += (*(_DWORD *)v8)++;\n }\n if ( a2 == v5 )\n break;\n ++v5;\n }\n }\n free(v4);\n return v7;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbp, rdi\nmov ebx, esi\nlea r14d, [rsi+rsi*8]\nmov r13d, esi\nneg r13d\nlea edi, [rsi+r14+1]\nmovsxd rdi, edi; nmemb\nmov esi, 4; size\ncall _calloc\ntest rax, rax\njz short loc_121B\nmov rdi, rax; ptr\nmovsxd rsi, ebx\nadd dword ptr [rax+rsi*4], 1\ntest ebx, ebx\njle short loc_126A\nmov edx, 1\nmov ecx, 0\nmov r12d, 0\njmp short loc_1251\nloc_121B:\nlea rdi, s; \"Memory allocation failed\"\ncall _perror\nmov edi, 1; status\ncall _exit\nloc_1231:\nadd eax, ebx\ncdqe\nlea r8, [rdi+rax*4]\nmov eax, [r8]\nadd r12d, eax\nadd eax, 1\nmov [r8], eax\nloc_1245:\nlea rax, [rdx+1]\ncmp rsi, rdx\njz short loc_1270\nmov rdx, rax\nloc_1251:\nmovsx eax, byte ptr [rbp+rdx-1]\nlea ecx, [rcx+rax-30h]\nmov eax, ecx\nsub eax, edx\ncmp r13d, eax\njg short loc_1245\ncmp r14d, eax\njge short loc_1231\njmp short loc_1245\nloc_126A:\nmov r12d, 0\nloc_1270:\ncall _free\nmov eax, r12d\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11C9(__int64 a1, int a2)\n{\n char *v3; // rax\n char *v4; // rdi\n __int64 v5; // rdx\n int v6; // ecx\n unsigned int v7; // r12d\n char *v8; // r8\n int v9; // eax\n\n v3 = (char *)calloc(10 * a2 + 1, 4uLL);\n if ( !v3 )\n {\n perror(\"Memory allocation failed\");\n exit(1);\n }\n v4 = v3;\n ++*(_DWORD *)&v3[4 * a2];\n if ( a2 <= 0 )\n {\n v7 = 0;\n }\n else\n {\n v5 = 1LL;\n v6 = 0;\n v7 = 0;\n while ( 1 )\n {\n v6 = v6 + *(char *)(a1 + v5 - 1) - 48;\n v9 = v6 - v5;\n if ( -a2 <= v6 - (int)v5 && 9 * a2 >= v9 )\n {\n v8 = &v4[4 * a2 + 4 * v9];\n v7 += (*(_DWORD *)v8)++;\n }\n if ( a2 == v5 )\n break;\n ++v5;\n }\n }\n free(v4);\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11C9(long long a1, int a2) {\n char *v3;\n char *v4;\n long long v5;\n int v6;\n unsigned int v7;\n char *v8;\n int v9;\n v3 = (char *)calloc(10 * a2 + 1, 4uLL);\n if (!v3) {\n perror(\"Memory allocation failed\");\n exit(1);\n }\n v4 = v3;\n ++*(uint32_t *)&v3[4 * a2];\n if (a2 <= 0) {\n v7 = 0;\n } else {\n v5 = 1LL;\n v6 = 0;\n v7 = 0;\n while (1) {\n v6 = v6 + *(char *)(a1 + v5 - 1) - 48;\n v9 = v6 - v5;\n if (-a2 <= v6 - (int)v5 && 9 * a2 >= v9) {\n v8 = &v4[4 * a2 + 4 * v9];\n v7 += (*(uint32_t *)v8)++;\n }\n if (a2 == v5) break;\n ++v5;\n }\n }\n free(v4);\n return v7;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n char *v3;\n char *v4;\n long long v5;\n int v6;\n unsigned int v7;\n char *v8;\n int v9;\n v3 = (char *)calloc(10 * a2 + 1, 4uLL);\n if (!v3) {\n perror(\"Memory allocation failed\");\n exit(1);\n }\n v4 = v3;\n ++*(uint32_t *)&v3[4 * a2];\n if (a2 <= 0) {\n v7 = 0;\n } else {\n v5 = 1LL;\n v6 = 0;\n v7 = 0;\n while (1) {\n v6 = v6 + *(char *)(a1 + v5 - 1) - 48;\n v9 = v6 - v5;\n if (-a2 <= v6 - (int)v5 && 9 * a2 >= v9) {\n v8 = &v4[4 * a2 + 4 * v9];\n v7 += (*(uint32_t *)v8)++;\n }\n if (a2 == v5) break;\n ++v5;\n }\n }\n free(v4);\n return v7;\n}" + }, + { + "index": 61, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *s, int n) {\n int count = 0, sum = 0;\n int max_sum = n * 9;\n int min_sum = -n;\n int size = max_sum - min_sum + 1;\n int *mp = calloc(size, sizeof(int));\n if (!mp) {\n perror(\"Memory allocation failed\");\n exit(EXIT_FAILURE);\n }\n mp[-min_sum] += 1;\n for (int i = 0; i < n; i++) {\n sum += s[i] - '0';\n int key = sum - (i + 1);\n if (key >= min_sum && key <= max_sum) {\n count += mp[key - min_sum];\n mp[key - min_sum] += 1;\n }\n }\n free(mp);\n return count;\n}", + "test": "int main() {\n\n assert(func0(\"112112\", 6) == 6);\n\n assert(func0(\"111\", 3) == 6);\n\n assert(func0(\"1101112\", 7) == 12);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\nlea (%rsi,%rsi,8),%r13d\npush %r12\nmov %esi,%r12d\npush %rbp\nmov %rdi,%rbp\nlea 0x1(%rsi,%r13,1),%edi\nneg %r12d\npush %rbx\nmovslq %edi,%rdi\nmov %esi,%ebx\nmov $0x4,%esi\ncallq 10b0 \ntest %rax,%rax\nje 1325 \nmov %rax,%rdi\nmovslq %ebx,%rax\naddl $0x1,(%rdi,%rax,4)\ntest %ebx,%ebx\njle 1320 \nlea -0x1(%rbx),%eax\nmov $0x1,%ecx\nxor %esi,%esi\nxor %r14d,%r14d\nadd $0x2,%rax\nnopl 0x0(%rax)\nmovsbl -0x1(%rbp,%rcx,1),%edx\nlea -0x30(%rsi,%rdx,1),%esi\nmov %esi,%edx\nsub %ecx,%edx\ncmp %edx,%r12d\njg 1304 \ncmp %edx,%r13d\njl 1304 \nadd %ebx,%edx\nmovslq %edx,%rdx\nlea (%rdi,%rdx,4),%r8\nmov (%r8),%edx\nadd %edx,%r14d\nadd $0x1,%edx\nmov %edx,(%r8)\nadd $0x1,%rcx\ncmp %rcx,%rax\njne 12d8 \ncallq 1090 \npop %rbx\nmov %r14d,%eax\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nxchg %ax,%ax\nxor %r14d,%r14d\njmp 130d \nlea 0xcd8(%rip),%rdi\ncallq 10c0 \nmov $0x1,%edi\ncallq 10d0 \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\nlea r13d, [rsi+rsi*8]\npush r12\nmov r12d, esi\npush rbp\nmov rbp, rdi\nlea edi, [rsi+r13+1]\nneg r12d\npush rbx\nmovsxd rdi, edi; nmemb\nmov ebx, esi\nmov esi, 4; size\ncall _calloc\ntest rax, rax\njz func0_cold\nmovsxd rsi, ebx\nmov rdi, rax; ptr\nadd dword ptr [rax+rsi*4], 1\ntest ebx, ebx\njle short loc_1340\nmov edx, 1\nxor ecx, ecx\nxor r14d, r14d\njmp short loc_12F3\nloc_12F0:\nmov rdx, rax\nloc_12F3:\nmovsx eax, byte ptr [rbp+rdx-1]\nlea ecx, [rcx+rax-30h]\nmov eax, ecx\nsub eax, edx\ncmp r12d, eax\njg short loc_131E\ncmp r13d, eax\njl short loc_131E\nadd eax, ebx\ncdqe\nlea r8, [rdi+rax*4]\nmov eax, [r8]\nadd r14d, eax\nadd eax, 1\nmov [r8], eax\nloc_131E:\nlea rax, [rdx+1]\ncmp rsi, rdx\njnz short loc_12F0\nloc_1327:\ncall _free\npop rbx\nmov eax, r14d\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1340:\nxor r14d, r14d\njmp short loc_1327", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n char *v3; // rax\n char *v4; // rdi\n __int64 v5; // rdx\n int v6; // ecx\n unsigned int v7; // r14d\n int v8; // eax\n char *v9; // r8\n\n v3 = (char *)calloc(10 * a2 + 1, 4uLL);\n if ( !v3 )\n func0_cold();\n v4 = v3;\n ++*(_DWORD *)&v3[4 * a2];\n if ( a2 <= 0 )\n {\n v7 = 0;\n }\n else\n {\n v5 = 1LL;\n v6 = 0;\n v7 = 0;\n while ( 1 )\n {\n v6 = v6 + *(char *)(a1 + v5 - 1) - 48;\n v8 = v6 - v5;\n if ( -a2 <= v6 - (int)v5 && 9 * a2 >= v8 )\n {\n v9 = &v4[4 * a2 + 4 * v8];\n v7 += (*(_DWORD *)v9)++;\n }\n if ( a2 == v5 )\n break;\n ++v5;\n }\n }\n free(v4);\n return v7;\n}", + "ida_strip_asm": "sub_12A0:\nendbr64\npush r14\npush r13\nlea r13d, [rsi+rsi*8]\npush r12\nmov r12d, esi\npush rbp\nmov rbp, rdi\nlea edi, [rsi+r13+1]\nneg r12d\npush rbx\nmovsxd rdi, edi; nmemb\nmov ebx, esi\nmov esi, 4; size\ncall _calloc\ntest rax, rax\njz loc_10E0\nmovsxd rsi, ebx\nmov rdi, rax; ptr\nadd dword ptr [rax+rsi*4], 1\ntest ebx, ebx\njle short loc_1340\nmov edx, 1\nxor ecx, ecx\nxor r14d, r14d\njmp short loc_12F3\nloc_12F0:\nmov rdx, rax\nloc_12F3:\nmovsx eax, byte ptr [rbp+rdx-1]\nlea ecx, [rcx+rax-30h]\nmov eax, ecx\nsub eax, edx\ncmp r12d, eax\njg short loc_131E\ncmp r13d, eax\njl short loc_131E\nadd eax, ebx\ncdqe\nlea r8, [rdi+rax*4]\nmov eax, [r8]\nadd r14d, eax\nadd eax, 1\nmov [r8], eax\nloc_131E:\nlea rax, [rdx+1]\ncmp rsi, rdx\njnz short loc_12F0\nloc_1327:\ncall _free\npop rbx\nmov eax, r14d\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1340:\nxor r14d, r14d\njmp short loc_1327", + "ida_strip_pseudo": "__int64 __fastcall sub_12A0(__int64 a1, int a2)\n{\n char *v3; // rax\n char *v4; // rdi\n __int64 v5; // rdx\n int v6; // ecx\n unsigned int v7; // r14d\n int v8; // eax\n char *v9; // r8\n\n v3 = (char *)calloc(10 * a2 + 1, 4uLL);\n if ( !v3 )\n {\n perror(\"Memory allocation failed\");\n exit(1);\n }\n v4 = v3;\n ++*(_DWORD *)&v3[4 * a2];\n if ( a2 <= 0 )\n {\n v7 = 0;\n }\n else\n {\n v5 = 1LL;\n v6 = 0;\n v7 = 0;\n while ( 1 )\n {\n v6 = v6 + *(char *)(a1 + v5 - 1) - 48;\n v8 = v6 - v5;\n if ( -a2 <= v6 - (int)v5 && 9 * a2 >= v8 )\n {\n v9 = &v4[4 * a2 + 4 * v8];\n v7 += (*(_DWORD *)v9)++;\n }\n if ( a2 == v5 )\n break;\n ++v5;\n }\n }\n free(v4);\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12A0(long long a1, int a2) {\n char *v3;\n char *v4;\n long long v5;\n int v6;\n unsigned int v7;\n int v8;\n char *v9;\n v3 = (char *)calloc(10 * a2 + 1, 4uLL);\n if (!v3) {\n perror(\"Memory allocation failed\");\n exit(1);\n }\n v4 = v3;\n ++*(uint32_t *)&v3[4 * a2];\n if (a2 <= 0) {\n v7 = 0;\n } else {\n v5 = 1LL;\n v6 = 0;\n v7 = 0;\n while (1) {\n v6 = v6 + *(char *)(a1 + v5 - 1) - 48;\n v8 = v6 - v5;\n if (-a2 <= v6 - (int)v5 && 9 * a2 >= v8) {\n v9 = &v4[4 * a2 + 4 * v8];\n v7 += (*(uint32_t *)v9)++;\n }\n if (a2 == v5) break;\n ++v5;\n }\n }\n free(v4);\n return v7;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n char *v3;\n char *v4;\n long long v5;\n int v6;\n unsigned int v7;\n int v8;\n char *v9;\n v3 = (char *)calloc(10 * a2 + 1, 4uLL);\n if (!v3) func0_cold();\n v4 = v3;\n ++*(uint32_t *)&v3[4 * a2];\n if (a2 <= 0) {\n v7 = 0;\n } else {\n v5 = 1LL;\n v6 = 0;\n v7 = 0;\n while (1) {\n v6 = v6 + *(char *)(a1 + v5 - 1) - 48;\n v8 = v6 - v5;\n if (-a2 <= v6 - (int)v5 && 9 * a2 >= v8) {\n v9 = &v4[4 * a2 + 4 * v8];\n v7 += (*(uint32_t *)v9)++;\n }\n if (a2 == v5) break;\n ++v5;\n }\n }\n free(v4);\n return v7;\n}" + }, + { + "index": 61, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *s, int n) {\n int count = 0, sum = 0;\n int max_sum = n * 9;\n int min_sum = -n;\n int size = max_sum - min_sum + 1;\n int *mp = calloc(size, sizeof(int));\n if (!mp) {\n perror(\"Memory allocation failed\");\n exit(EXIT_FAILURE);\n }\n mp[-min_sum] += 1;\n for (int i = 0; i < n; i++) {\n sum += s[i] - '0';\n int key = sum - (i + 1);\n if (key >= min_sum && key <= max_sum) {\n count += mp[key - min_sum];\n mp[key - min_sum] += 1;\n }\n }\n free(mp);\n return count;\n}", + "test": "int main() {\n\n assert(func0(\"112112\", 6) == 6);\n\n assert(func0(\"111\", 3) == 6);\n\n assert(func0(\"1101112\", 7) == 12);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\nlea (%rsi,%rsi,8),%r13d\npush %r12\nmov %esi,%r12d\npush %rbp\nmov %rdi,%rbp\nlea 0x1(%rsi,%r13,1),%edi\nneg %r12d\npush %rbx\nmovslq %edi,%rdi\nmov %esi,%ebx\nmov $0x4,%esi\ncallq 10b0 \ntest %rax,%rax\nje 1325 \nmov %rax,%rdi\nmovslq %ebx,%rax\naddl $0x1,(%rdi,%rax,4)\ntest %ebx,%ebx\njle 1320 \nlea -0x1(%rbx),%eax\nmov $0x1,%ecx\nxor %esi,%esi\nxor %r14d,%r14d\nadd $0x2,%rax\nnopl 0x0(%rax)\nmovsbl -0x1(%rbp,%rcx,1),%edx\nlea -0x30(%rsi,%rdx,1),%esi\nmov %esi,%edx\nsub %ecx,%edx\ncmp %edx,%r12d\njg 1304 \ncmp %edx,%r13d\njl 1304 \nadd %ebx,%edx\nmovslq %edx,%rdx\nlea (%rdi,%rdx,4),%r8\nmov (%r8),%edx\nadd %edx,%r14d\nadd $0x1,%edx\nmov %edx,(%r8)\nadd $0x1,%rcx\ncmp %rcx,%rax\njne 12d8 \ncallq 1090 \npop %rbx\nmov %r14d,%eax\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nxchg %ax,%ax\nxor %r14d,%r14d\njmp 130d \nlea 0xcd8(%rip),%rdi\ncallq 10c0 \nmov $0x1,%edi\ncallq 10d0 \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\nlea r13d, [rsi+rsi*8]\npush r12\nmov r12d, esi\npush rbp\nmov rbp, rdi\nlea edi, [rsi+r13+1]\nneg r12d\npush rbx\nmovsxd rdi, edi; nmemb\nmov ebx, esi\nmov esi, 4; size\ncall _calloc\ntest rax, rax\njz func0_cold\nmovsxd rsi, ebx\nmov rdi, rax; ptr\nadd dword ptr [rax+rsi*4], 1\ntest ebx, ebx\njle short loc_1340\nmov edx, 1\nxor ecx, ecx\nxor r14d, r14d\njmp short loc_12F3\nloc_12F0:\nmov rdx, rax\nloc_12F3:\nmovsx eax, byte ptr [rbp+rdx-1]\nlea ecx, [rcx+rax-30h]\nmov eax, ecx\nsub eax, edx\ncmp r12d, eax\njg short loc_131E\ncmp r13d, eax\njl short loc_131E\nadd eax, ebx\ncdqe\nlea r8, [rdi+rax*4]\nmov eax, [r8]\nadd r14d, eax\nadd eax, 1\nmov [r8], eax\nloc_131E:\nlea rax, [rdx+1]\ncmp rsi, rdx\njnz short loc_12F0\nloc_1327:\ncall _free\npop rbx\nmov eax, r14d\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1340:\nxor r14d, r14d\njmp short loc_1327", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n char *v3; // rax\n char *v4; // rdi\n __int64 v5; // rdx\n int v6; // ecx\n unsigned int v7; // r14d\n int v8; // eax\n char *v9; // r8\n\n v3 = (char *)calloc(10 * a2 + 1, 4uLL);\n if ( !v3 )\n func0_cold();\n v4 = v3;\n ++*(_DWORD *)&v3[4 * a2];\n if ( a2 <= 0 )\n {\n v7 = 0;\n }\n else\n {\n v5 = 1LL;\n v6 = 0;\n v7 = 0;\n while ( 1 )\n {\n v6 = v6 + *(char *)(a1 + v5 - 1) - 48;\n v8 = v6 - v5;\n if ( -a2 <= v6 - (int)v5 && 9 * a2 >= v8 )\n {\n v9 = &v4[4 * a2 + 4 * v8];\n v7 += (*(_DWORD *)v9)++;\n }\n if ( a2 == v5 )\n break;\n ++v5;\n }\n }\n free(v4);\n return v7;\n}", + "ida_strip_asm": "sub_12A0:\nendbr64\npush r14\npush r13\nlea r13d, [rsi+rsi*8]\npush r12\nmov r12d, esi\npush rbp\nmov rbp, rdi\nlea edi, [rsi+r13+1]\nneg r12d\npush rbx\nmovsxd rdi, edi; nmemb\nmov ebx, esi\nmov esi, 4; size\ncall _calloc\ntest rax, rax\njz loc_10E0\nmovsxd rsi, ebx\nmov rdi, rax; ptr\nadd dword ptr [rax+rsi*4], 1\ntest ebx, ebx\njle short loc_1340\nmov edx, 1\nxor ecx, ecx\nxor r14d, r14d\njmp short loc_12F3\nloc_12F0:\nmov rdx, rax\nloc_12F3:\nmovsx eax, byte ptr [rbp+rdx-1]\nlea ecx, [rcx+rax-30h]\nmov eax, ecx\nsub eax, edx\ncmp r12d, eax\njg short loc_131E\ncmp r13d, eax\njl short loc_131E\nadd eax, ebx\ncdqe\nlea r8, [rdi+rax*4]\nmov eax, [r8]\nadd r14d, eax\nadd eax, 1\nmov [r8], eax\nloc_131E:\nlea rax, [rdx+1]\ncmp rsi, rdx\njnz short loc_12F0\nloc_1327:\ncall _free\npop rbx\nmov eax, r14d\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1340:\nxor r14d, r14d\njmp short loc_1327", + "ida_strip_pseudo": "__int64 __fastcall sub_12A0(__int64 a1, int a2)\n{\n char *v3; // rax\n char *v4; // rdi\n __int64 v5; // rdx\n int v6; // ecx\n unsigned int v7; // r14d\n int v8; // eax\n char *v9; // r8\n\n v3 = (char *)calloc(10 * a2 + 1, 4uLL);\n if ( !v3 )\n {\n perror(\"Memory allocation failed\");\n exit(1);\n }\n v4 = v3;\n ++*(_DWORD *)&v3[4 * a2];\n if ( a2 <= 0 )\n {\n v7 = 0;\n }\n else\n {\n v5 = 1LL;\n v6 = 0;\n v7 = 0;\n while ( 1 )\n {\n v6 = v6 + *(char *)(a1 + v5 - 1) - 48;\n v8 = v6 - v5;\n if ( -a2 <= v6 - (int)v5 && 9 * a2 >= v8 )\n {\n v9 = &v4[4 * a2 + 4 * v8];\n v7 += (*(_DWORD *)v9)++;\n }\n if ( a2 == v5 )\n break;\n ++v5;\n }\n }\n free(v4);\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12A0(long long a1, int a2) {\n char *v3;\n char *v4;\n long long v5;\n int v6;\n unsigned int v7;\n int v8;\n char *v9;\n v3 = (char *)calloc(10 * a2 + 1, 4uLL);\n if (!v3) {\n perror(\"Memory allocation failed\");\n exit(1);\n }\n v4 = v3;\n ++*(uint32_t *)&v3[4 * a2];\n if (a2 <= 0) {\n v7 = 0;\n } else {\n v5 = 1LL;\n v6 = 0;\n v7 = 0;\n while (1) {\n v6 = v6 + *(char *)(a1 + v5 - 1) - 48;\n v8 = v6 - v5;\n if (-a2 <= v6 - (int)v5 && 9 * a2 >= v8) {\n v9 = &v4[4 * a2 + 4 * v8];\n v7 += (*(uint32_t *)v9)++;\n }\n if (a2 == v5) break;\n ++v5;\n }\n }\n free(v4);\n return v7;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n char *v3;\n char *v4;\n long long v5;\n int v6;\n unsigned int v7;\n int v8;\n char *v9;\n v3 = (char *)calloc(10 * a2 + 1, 4uLL);\n if (!v3) func0_cold();\n v4 = v3;\n ++*(uint32_t *)&v3[4 * a2];\n if (a2 <= 0) {\n v7 = 0;\n } else {\n v5 = 1LL;\n v6 = 0;\n v7 = 0;\n while (1) {\n v6 = v6 + *(char *)(a1 + v5 - 1) - 48;\n v8 = v6 - v5;\n if (-a2 <= v6 - (int)v5 && 9 * a2 >= v8) {\n v9 = &v4[4 * a2 + 4 * v8];\n v7 += (*(uint32_t *)v9)++;\n }\n if (a2 == v5) break;\n ++v5;\n }\n }\n free(v4);\n return v7;\n}" + }, + { + "index": 62, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int xs[], int size) {\n int min_val = INT_MAX;\n for (int i = 0; i < size; i++) {\n if (xs[i] < min_val) {\n min_val = xs[i];\n }\n }\n return min_val;\n}", + "test": "int main() {\n\n int arr1[5] = {10, 20, 1, 45, 99};\n\n int arr2[3] = {1, 2, 3};\n\n int arr3[4] = {45, 46, 50, 60};\n\n \n\n assert(func0(arr1, 5) == 1);\n\n assert(func0(arr2, 3) == 1);\n\n assert(func0(arr3, 4) == 45);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x7fffffff,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11c0 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x8(%rbp)\njle 11bc \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1188 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 7FFFFFFFh\nmov [rbp+var_4], 0\njmp short loc_11C0\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_8], eax\njle short loc_11BC\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_8], eax\nloc_11BC:\nadd [rbp+var_4], 1\nloc_11C0:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0x7FFFFFFF;\n for ( i = 0; i < a2; ++i )\n {\n if ( v3 > *(_DWORD *)(4LL * i + a1) )\n v3 = *(_DWORD *)(4LL * i + a1);\n }\n return (unsigned int)v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 7FFFFFFFh\nmov [rbp+var_4], 0\njmp short loc_11C0\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_8], eax\njle short loc_11BC\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_8], eax\nloc_11BC:\nadd [rbp+var_4], 1\nloc_11C0:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0x7FFFFFFF;\n for ( i = 0; i < a2; ++i )\n {\n if ( v3 > *(_DWORD *)(4LL * i + a1) )\n v3 = *(_DWORD *)(4LL * i + a1);\n }\n return (unsigned int)v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int v3;\n int i;\n v3 = 2147483647;\n for (i = 0; i < a2; ++i) {\n if (v3 > *(uint32_t *)(4LL * i + a1)) v3 = *(uint32_t *)(4LL * i + a1);\n }\n return (unsigned int)v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int v3;\n int i;\n v3 = 2147483647;\n for (i = 0; i < a2; ++i) {\n if (v3 > *(uint32_t *)(4LL * i + a1)) v3 = *(uint32_t *)(4LL * i + a1);\n }\n return (unsigned int)v3;\n}" + }, + { + "index": 62, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int xs[], int size) {\n int min_val = INT_MAX;\n for (int i = 0; i < size; i++) {\n if (xs[i] < min_val) {\n min_val = xs[i];\n }\n }\n return min_val;\n}", + "test": "int main() {\n\n int arr1[5] = {10, 20, 1, 45, 99};\n\n int arr2[3] = {1, 2, 3};\n\n int arr3[4] = {45, 46, 50, 60};\n\n \n\n assert(func0(arr1, 5) == 1);\n\n assert(func0(arr2, 3) == 1);\n\n assert(func0(arr3, 4) == 45);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1194 \nmov %rdi,%rax\nlea -0x1(%rsi),%edx\nlea 0x4(%rdi,%rdx,4),%rsi\nmov $0x7fffffff,%edx\nmov (%rax),%ecx\ncmp %ecx,%edx\ncmovg %ecx,%edx\nadd $0x4,%rax\ncmp %rsi,%rax\njne 1181 \nmov %edx,%eax\nretq\nmov $0x7fffffff,%edx\njmp 1191 \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1193\nmov rax, rdi\nmovsxd rsi, esi\nlea rsi, [rdi+rsi*4]\nmov edx, 7FFFFFFFh\nloc_1180:\nmov ecx, [rax]\ncmp edx, ecx\ncmovg edx, ecx\nadd rax, 4\ncmp rax, rsi\njnz short loc_1180\nloc_1190:\nmov eax, edx\nretn\nloc_1193:\nmov edx, 7FFFFFFFh\njmp short loc_1190", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int *v2; // rax\n int *v3; // rsi\n int v4; // edx\n\n if ( a2 <= 0 )\n {\n return 0x7FFFFFFF;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0x7FFFFFFF;\n do\n {\n if ( v4 > *v2 )\n v4 = *v2;\n ++v2;\n }\n while ( v2 != v3 );\n }\n return (unsigned int)v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_1193\nmov rax, rdi\nmovsxd rsi, esi\nlea rsi, [rdi+rsi*4]\nmov edx, 7FFFFFFFh\nloc_1180:\nmov ecx, [rax]\ncmp edx, ecx\ncmovg edx, ecx\nadd rax, 4\ncmp rax, rsi\njnz short loc_1180\nloc_1190:\nmov eax, edx\nretn\nloc_1193:\nmov edx, 7FFFFFFFh\njmp short loc_1190", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int *a1, int a2)\n{\n int *v2; // rax\n int *v3; // rsi\n int v4; // edx\n\n if ( a2 <= 0 )\n {\n return 0x7FFFFFFF;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0x7FFFFFFF;\n do\n {\n if ( v4 > *v2 )\n v4 = *v2;\n ++v2;\n }\n while ( v2 != v3 );\n }\n return (unsigned int)v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int *a1, int a2) {\n int *v2;\n int *v3;\n int v4;\n if (a2 <= 0) {\n return 2147483647;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 2147483647;\n do {\n if (v4 > *v2) v4 = *v2;\n ++v2;\n } while (v2 != v3);\n }\n return (unsigned int)v4;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int *v2;\n int *v3;\n int v4;\n if (a2 <= 0) {\n return 2147483647;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 2147483647;\n do {\n if (v4 > *v2) v4 = *v2;\n ++v2;\n } while (v2 != v3);\n }\n return (unsigned int)v4;\n}" + }, + { + "index": 63, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(int test_list[][2], int list_size) {\n int max_diff = 0;\n for (int i = 0; i < list_size; i++) {\n int diff = abs(test_list[i][1] - test_list[i][0]);\n if (diff > max_diff) {\n max_diff = diff;\n }\n }\n return max_diff;\n}", + "test": "int main() {\n\n int arr1[][2] = {{3, 5}, {1, 7}, {10, 3}, {1, 2}};\n\n int arr2[][2] = {{4, 6}, {2, 17}, {9, 13}, {11, 12}};\n\n int arr3[][2] = {{12, 35}, {21, 27}, {13, 23}, {41, 22}};\n\n \n\n assert(func0(arr1, 4) == 7);\n\n assert(func0(arr2, 4) == 15);\n\n assert(func0(arr3, 4) == 23);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11d6 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov 0x4(%rax),%edx\nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\nsub %eax,%edx\nmov %edx,%eax\nsar $0x1f,%eax\nxor %eax,%edx\nmov %edx,-0x4(%rbp)\nsub %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0xc(%rbp),%eax\njle 11d2 \nmov -0x4(%rbp),%eax\nmov %eax,-0xc(%rbp)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1188 \nmov -0xc(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_11D4\nloc_1188:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax+4]\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov edx, [rdx]\nsub eax, edx\nmov edx, eax\nneg edx\ncmovns eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_C]\njle short loc_11D0\nmov eax, [rbp+var_4]\nmov [rbp+var_C], eax\nloc_11D0:\nadd [rbp+var_8], 1\nloc_11D4:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // rcx\n int v3; // eax\n int v5; // [rsp+10h] [rbp-Ch]\n int i; // [rsp+14h] [rbp-8h]\n\n v5 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v2 = 8LL * i;\n v3 = *(_DWORD *)(v2 + a1 + 4) - *(_DWORD *)(v2 + a1);\n if ( *(_DWORD *)(v2 + a1) - *(_DWORD *)(v2 + a1 + 4) >= 0 )\n v3 = *(_DWORD *)(v2 + a1) - *(_DWORD *)(8LL * i + a1 + 4);\n if ( v3 > v5 )\n v5 = v3;\n }\n return (unsigned int)v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_11D4\nloc_1188:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax+4]\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov edx, [rdx]\nsub eax, edx\nmov edx, eax\nneg edx\ncmovns eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_C]\njle short loc_11D0\nmov eax, [rbp+var_4]\nmov [rbp+var_C], eax\nloc_11D0:\nadd [rbp+var_8], 1\nloc_11D4:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n __int64 v2; // rcx\n int v3; // eax\n int v5; // [rsp+10h] [rbp-Ch]\n int i; // [rsp+14h] [rbp-8h]\n\n v5 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v2 = 8LL * i;\n v3 = *(_DWORD *)(v2 + a1 + 4) - *(_DWORD *)(v2 + a1);\n if ( *(_DWORD *)(v2 + a1) - *(_DWORD *)(v2 + a1 + 4) >= 0 )\n v3 = *(_DWORD *)(v2 + a1) - *(_DWORD *)(8LL * i + a1 + 4);\n if ( v3 > v5 )\n v5 = v3;\n }\n return (unsigned int)v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n long long v2;\n int v3;\n int v5;\n int i;\n v5 = 0;\n for (i = 0; i < a2; ++i) {\n v2 = 8LL * i;\n v3 = *(uint32_t *)(v2 + a1 + 4) - *(uint32_t *)(v2 + a1);\n if (*(uint32_t *)(v2 + a1) - *(uint32_t *)(v2 + a1 + 4) >= 0)\n v3 = *(uint32_t *)(v2 + a1) - *(uint32_t *)(8LL * i + a1 + 4);\n if (v3 > v5) v5 = v3;\n }\n return (unsigned int)v5;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n int v3;\n int v5;\n int i;\n v5 = 0;\n for (i = 0; i < a2; ++i) {\n v2 = 8LL * i;\n v3 = *(uint32_t *)(v2 + a1 + 4) - *(uint32_t *)(v2 + a1);\n if (*(uint32_t *)(v2 + a1) - *(uint32_t *)(v2 + a1 + 4) >= 0)\n v3 = *(uint32_t *)(v2 + a1) - *(uint32_t *)(8LL * i + a1 + 4);\n if (v3 > v5) v5 = v3;\n }\n return (unsigned int)v5;\n}" + }, + { + "index": 63, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(int test_list[][2], int list_size) {\n int max_diff = 0;\n for (int i = 0; i < list_size; i++) {\n int diff = abs(test_list[i][1] - test_list[i][0]);\n if (diff > max_diff) {\n max_diff = diff;\n }\n }\n return max_diff;\n}", + "test": "int main() {\n\n int arr1[][2] = {{3, 5}, {1, 7}, {10, 3}, {1, 2}};\n\n int arr2[][2] = {{4, 6}, {2, 17}, {9, 13}, {11, 12}};\n\n int arr3[][2] = {{12, 35}, {21, 27}, {13, 23}, {41, 22}};\n\n \n\n assert(func0(arr1, 4) == 7);\n\n assert(func0(arr2, 4) == 15);\n\n assert(func0(arr3, 4) == 23);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11a0 \nmov %rdi,%rdx\nlea -0x1(%rsi),%eax\nlea 0x8(%rdi,%rax,8),%rdi\nmov $0x0,%ecx\nmov 0x4(%rdx),%eax\nsub (%rdx),%eax\nmov %eax,%esi\nsar $0x1f,%esi\nxor %esi,%eax\nsub %esi,%eax\ncmp %eax,%ecx\ncmovl %eax,%ecx\nadd $0x8,%rdx\ncmp %rdi,%rdx\njne 1181 \nmov %ecx,%eax\nretq\nmov $0x0,%ecx\njmp 119d \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_119D\nmov rdx, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*8]\nmov esi, 0\nloc_1180:\nmov eax, [rdx+4]\nsub eax, [rdx]\nmov ecx, eax\nneg ecx\ncmovns eax, ecx\ncmp esi, eax\ncmovl esi, eax\nadd rdx, 8\ncmp rdx, rdi\njnz short loc_1180\nloc_119A:\nmov eax, esi\nretn\nloc_119D:\nmov esi, 0\njmp short loc_119A", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rdx\n _DWORD *v3; // rdi\n int v4; // esi\n int v5; // eax\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = &a1[2 * a2];\n v4 = 0;\n do\n {\n v5 = v2[1] - *v2;\n if ( *v2 - v2[1] >= 0 )\n v5 = *v2 - v2[1];\n if ( v4 < v5 )\n v4 = v5;\n v2 += 2;\n }\n while ( v2 != v3 );\n }\n return (unsigned int)v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_119D\nmov rdx, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*8]\nmov esi, 0\nloc_1180:\nmov eax, [rdx+4]\nsub eax, [rdx]\nmov ecx, eax\nneg ecx\ncmovns eax, ecx\ncmp esi, eax\ncmovl esi, eax\nadd rdx, 8\ncmp rdx, rdi\njnz short loc_1180\nloc_119A:\nmov eax, esi\nretn\nloc_119D:\nmov esi, 0\njmp short loc_119A", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rdx\n _DWORD *v3; // rdi\n int v4; // esi\n int v5; // eax\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = &a1[2 * a2];\n v4 = 0;\n do\n {\n v5 = v2[1] - *v2;\n if ( *v2 - v2[1] >= 0 )\n v5 = *v2 - v2[1];\n if ( v4 < v5 )\n v4 = v5;\n v2 += 2;\n }\n while ( v2 != v3 );\n }\n return (unsigned int)v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2) {\n uint32_t *v2;\n uint32_t *v3;\n int v4;\n int v5;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = &a1[2 * a2];\n v4 = 0;\n do {\n v5 = v2[1] - *v2;\n if (*v2 - v2[1] >= 0) v5 = *v2 - v2[1];\n if (v4 < v5) v4 = v5;\n v2 += 2;\n } while (v2 != v3);\n }\n return (unsigned int)v4;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n uint32_t *v3;\n int v4;\n int v5;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = &a1[2 * a2];\n v4 = 0;\n do {\n v5 = v2[1] - *v2;\n if (*v2 - v2[1] >= 0) v5 = *v2 - v2[1];\n if (v4 < v5) v4 = v5;\n v2 += 2;\n } while (v2 != v3);\n }\n return (unsigned int)v4;\n}" + }, + { + "index": 64, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char subject[30];\n\n int marks;\n\n} SubjectMarks;\n\n\n\nint cmp(const void *a, const void *b) {\n\n SubjectMarks *sm1 = (SubjectMarks *)a;\n\n SubjectMarks *sm2 = (SubjectMarks *)b;\n\n return sm1->marks - sm2->marks;\n\n}\n\n\n\n", + "func": "void func0(SubjectMarks sm[], int len) {\n qsort(sm, len, sizeof(SubjectMarks), cmp);\n}", + "test": "int main() {\n\n SubjectMarks sm1[] = {{\"English\", 88}, {\"Science\", 90}, {\"Maths\", 97}, {\"Social sciences\", 82}};\n\n func0(sm1, 4);\n\n assert(sm1[0].marks == 82 && !strcmp(sm1[0].subject, \"Social sciences\"));\n\n assert(sm1[1].marks == 88 && !strcmp(sm1[1].subject, \"English\"));\n\n assert(sm1[2].marks == 90 && !strcmp(sm1[2].subject, \"Science\"));\n\n assert(sm1[3].marks == 97 && !strcmp(sm1[3].subject, \"Maths\"));\n\n\n\n SubjectMarks sm2[] = {{\"Telugu\", 49}, {\"Hindhi\", 54}, {\"Social\", 33}};\n\n func0(sm2, 3);\n\n assert(sm2[0].marks == 33 && !strcmp(sm2[0].subject, \"Social\"));\n\n assert(sm2[1].marks == 49 && !strcmp(sm2[1].subject, \"Telugu\"));\n\n assert(sm2[2].marks == 54 && !strcmp(sm2[2].subject, \"Hindhi\"));\n\n\n\n SubjectMarks sm3[] = {{\"Physics\", 96}, {\"Chemistry\", 97}, {\"Biology\", 45}};\n\n func0(sm3, 3);\n\n assert(sm3[0].marks == 45 && !strcmp(sm3[0].subject, \"Biology\"));\n\n assert(sm3[1].marks == 96 && !strcmp(sm3[1].subject, \"Physics\"));\n\n assert(sm3[2].marks == 97 && !strcmp(sm3[2].subject, \"Chemistry\"));\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %rdi,-0x8(%rbp)\nmov %esi,-0xc(%rbp)\nmov -0xc(%rbp),%esi\nmov -0x8(%rbp),%rax\nlea -0x55(%rip),%rcx\nmov $0x24,%edx\nmov %rax,%rdi\nmov $0x0,%eax\ncallq 1080 \nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+nmemb+4], rdi\nmov dword ptr [rbp+nmemb], esi\nmov esi, dword ptr [rbp+nmemb]; nmemb\nmov rax, [rbp+nmemb+4]\nlea rdx, cmp\nmov rcx, rdx; compar\nmov edx, 24h ; '$'; size\nmov rdi, rax; base\nmov eax, 0\ncall _qsort\nnop\nleave\nretn", + "ida_pseudo": "void __fastcall func0(void *a1, unsigned int a2)\n{\n qsort(a1, a2, 0x24uLL, cmp);\n}", + "ida_strip_asm": "sub_11DD:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+nmemb+4], rdi\nmov dword ptr [rbp+nmemb], esi\nmov esi, dword ptr [rbp+nmemb]; nmemb\nmov rax, [rbp+nmemb+4]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 24h ; '$'; size\nmov rdi, rax; base\nmov eax, 0\ncall _qsort\nnop\nleave\nretn", + "ida_strip_pseudo": "void __fastcall sub_11DD(void *a1, unsigned int a2)\n{\n qsort(a1, a2, 0x24uLL, compar);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_11DD(void *a1, unsigned int a2) { qsort(a1, a2, 36uLL, compar); }", + "ida_pseudo_norm": "void func0(void *a1, unsigned int a2) { qsort(a1, a2, 36uLL, cmp); }" + }, + { + "index": 64, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char subject[30];\n\n int marks;\n\n} SubjectMarks;\n\n\n\nint cmp(const void *a, const void *b) {\n\n SubjectMarks *sm1 = (SubjectMarks *)a;\n\n SubjectMarks *sm2 = (SubjectMarks *)b;\n\n return sm1->marks - sm2->marks;\n\n}\n\n\n\n", + "func": "void func0(SubjectMarks sm[], int len) {\n qsort(sm, len, sizeof(SubjectMarks), cmp);\n}", + "test": "int main() {\n\n SubjectMarks sm1[] = {{\"English\", 88}, {\"Science\", 90}, {\"Maths\", 97}, {\"Social sciences\", 82}};\n\n func0(sm1, 4);\n\n assert(sm1[0].marks == 82 && !strcmp(sm1[0].subject, \"Social sciences\"));\n\n assert(sm1[1].marks == 88 && !strcmp(sm1[1].subject, \"English\"));\n\n assert(sm1[2].marks == 90 && !strcmp(sm1[2].subject, \"Science\"));\n\n assert(sm1[3].marks == 97 && !strcmp(sm1[3].subject, \"Maths\"));\n\n\n\n SubjectMarks sm2[] = {{\"Telugu\", 49}, {\"Hindhi\", 54}, {\"Social\", 33}};\n\n func0(sm2, 3);\n\n assert(sm2[0].marks == 33 && !strcmp(sm2[0].subject, \"Social\"));\n\n assert(sm2[1].marks == 49 && !strcmp(sm2[1].subject, \"Telugu\"));\n\n assert(sm2[2].marks == 54 && !strcmp(sm2[2].subject, \"Hindhi\"));\n\n\n\n SubjectMarks sm3[] = {{\"Physics\", 96}, {\"Chemistry\", 97}, {\"Biology\", 45}};\n\n func0(sm3, 3);\n\n assert(sm3[0].marks == 45 && !strcmp(sm3[0].subject, \"Biology\"));\n\n assert(sm3[1].marks == 96 && !strcmp(sm3[1].subject, \"Physics\"));\n\n assert(sm3[2].marks == 97 && !strcmp(sm3[2].subject, \"Chemistry\"));\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x8,%rsp\nlea -0x1a(%rip),%rcx\nmov $0x24,%edx\nmov $0x0,%eax\ncallq 1070 \nadd $0x8,%rsp\nretq\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\nlea rcx, cmp; compar\nmov edx, 24h ; '$'; size\nmov eax, 0\ncall _qsort\nadd rsp, 8\nretn", + "ida_pseudo": "void __fastcall func0(void *a1, size_t a2)\n{\n qsort(a1, a2, 0x24uLL, cmp);\n}", + "ida_strip_asm": "sub_11B4:\nendbr64\nsub rsp, 8\nlea rcx, compar; compar\nmov edx, 24h ; '$'; size\nmov eax, 0\ncall _qsort\nadd rsp, 8\nretn", + "ida_strip_pseudo": "void __fastcall sub_11B4(void *a1, size_t a2)\n{\n qsort(a1, a2, 0x24uLL, compar);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_11B4(void *a1, unsigned int a2) { qsort(a1, a2, 36uLL, compar); }", + "ida_pseudo_norm": "void func0(void *a1, unsigned int a2) { qsort(a1, a2, 36uLL, cmp); }" + }, + { + "index": 65, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int *data_list, int n) {\n int total = 0;\n for (int i = 0; i < n; i++) {\n if (data_list[i] < 0) {\n int sub_length = -data_list[i];\n i++;\n total += func0(&data_list[i], sub_length);\n i += sub_length - 1;\n } else {\n total += data_list[i];\n }\n }\n return total;\n}", + "test": "int main() {\n\n int list1[] = {1, 2, -2, 3, 4, -2, 5, 6};\n\n int list2[] = {7, 10, -2, 15, 14, -2, 19, 41};\n\n int list3[] = {10, 20, -2, 30, 40, -2, 50, 60};\n\n\n\n assert(func0(list1, 8) == 21);\n\n assert(func0(list2, 8) == 106);\n\n assert(func0(list3, 8) == 210);\n\n\n\n printf(\"All tests passed!\\n\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\njmpq 1234 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ntest %eax,%eax\njns 1217 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nneg %eax\nmov %eax,-0x4(%rbp)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0x4(%rbp),%eax\nmov %eax,%esi\nmov %rdx,%rdi\ncallq 1189 \nadd %eax,-0xc(%rbp)\nmov -0x4(%rbp),%eax\nsub $0x1,%eax\nadd %eax,-0x8(%rbp)\njmp 1230 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nadd %eax,-0xc(%rbp)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11af \nmov -0xc(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp loc_1234\nloc_11AF:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njns short loc_1217\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nneg eax\nmov [rbp+var_4], eax\nadd [rbp+var_8], 1\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov esi, eax\nmov rdi, rdx\ncall func0\nadd [rbp+var_C], eax\nmov eax, [rbp+var_4]\nsub eax, 1\nadd [rbp+var_8], eax\njmp short loc_1230\nloc_1217:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_C], eax\nloc_1230:\nadd [rbp+var_8], 1\nloc_1234:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl loc_11AF\nmov eax, [rbp+var_C]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-Ch]\n int i; // [rsp+18h] [rbp-8h]\n int v5; // [rsp+18h] [rbp-8h]\n unsigned int v6; // [rsp+1Ch] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(int *)(4LL * i + a1) >= 0 )\n {\n v3 += *(_DWORD *)(4LL * i + a1);\n }\n else\n {\n v6 = -*(_DWORD *)(4LL * i + a1);\n v5 = i + 1;\n v3 += func0(a1 + 4LL * v5, v6);\n i = v6 - 1 + v5;\n }\n }\n return v3;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp loc_1234\nloc_11AF:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njns short loc_1217\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nneg eax\nmov [rbp+var_4], eax\nadd [rbp+var_8], 1\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov esi, eax\nmov rdi, rdx\ncall sub_1189\nadd [rbp+var_C], eax\nmov eax, [rbp+var_4]\nsub eax, 1\nadd [rbp+var_8], eax\njmp short loc_1230\nloc_1217:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_C], eax\nloc_1230:\nadd [rbp+var_8], 1\nloc_1234:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl loc_11AF\nmov eax, [rbp+var_C]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-Ch]\n int i; // [rsp+18h] [rbp-8h]\n int v5; // [rsp+18h] [rbp-8h]\n unsigned int v6; // [rsp+1Ch] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(int *)(4LL * i + a1) >= 0 )\n {\n v3 += *(_DWORD *)(4LL * i + a1);\n }\n else\n {\n v6 = -*(_DWORD *)(4LL * i + a1);\n v5 = i + 1;\n v3 += sub_1189(a1 + 4LL * v5, v6);\n i = v6 - 1 + v5;\n }\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2) {\n unsigned int v3;\n int i;\n int v5;\n unsigned int v6;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(int *)(4LL * i + a1) >= 0) {\n v3 += *(uint32_t *)(4LL * i + a1);\n } else {\n v6 = -*(uint32_t *)(4LL * i + a1);\n v5 = i + 1;\n v3 += sub_1189(a1 + 4LL * v5, v6);\n i = v6 - 1 + v5;\n }\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n int v5;\n unsigned int v6;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(int *)(4LL * i + a1) >= 0) {\n v3 += *(uint32_t *)(4LL * i + a1);\n } else {\n v6 = -*(uint32_t *)(4LL * i + a1);\n v5 = i + 1;\n v3 += func0(a1 + 4LL * v5, v6);\n i = v6 - 1 + v5;\n }\n }\n return v3;\n}" + }, + { + "index": 65, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int *data_list, int n) {\n int total = 0;\n for (int i = 0; i < n; i++) {\n if (data_list[i] < 0) {\n int sub_length = -data_list[i];\n i++;\n total += func0(&data_list[i], sub_length);\n i += sub_length - 1;\n } else {\n total += data_list[i];\n }\n }\n return total;\n}", + "test": "int main() {\n\n int list1[] = {1, 2, -2, 3, 4, -2, 5, 6};\n\n int list2[] = {7, 10, -2, 15, 14, -2, 19, 41};\n\n int list3[] = {10, 20, -2, 30, 40, -2, 50, 60};\n\n\n\n assert(func0(list1, 8) == 21);\n\n assert(func0(list2, 8) == 106);\n\n assert(func0(list3, 8) == 210);\n\n\n\n printf(\"All tests passed!\\n\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov $0x0,%r12d\ntest %esi,%esi\njle 11e6 \nmov %rdi,%r14\nmov %esi,%r13d\nmov $0x0,%eax\njmp 11b7 \nadd %ebp,%r12d\nadd $0x1,%eax\ncmp %eax,%r13d\njle 11e6 \nmovslq %eax,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov (%r14,%rdx,4),%ebp\ntest %ebp,%ebp\njns 11ac \nlea 0x1(%rax),%ebx\nmov %ebp,%esi\nneg %esi\nlea 0x4(%r14,%rcx,1),%rdi\ncallq 1189 \nadd %eax,%r12d\nnot %ebp\nlea 0x0(%rbp,%rbx,1),%eax\njmp 11af \nmov %r12d,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r12d, 0\ntest esi, esi\njle short loc_11E6\nmov r14, rdi\nmov r13d, esi\nmov eax, 0\njmp short loc_11CE\nloc_11AC:\nlea ebx, [rax+1]\nmov esi, ebp\nneg esi\nlea rdi, [r14+rcx+4]\ncall func0\nadd r12d, eax\nnot ebp\nlea eax, [rbp+rbx+0]\nloc_11C6:\nadd eax, 1\ncmp r13d, eax\njle short loc_11E6\nloc_11CE:\nmovsxd rdx, eax\nlea rcx, ds:0[rdx*4]\nmov ebp, [r14+rdx*4]\ntest ebp, ebp\njs short loc_11AC\nadd r12d, ebp\njmp short loc_11C6\nloc_11E6:\nmov eax, r12d\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v2; // r12d\n int i; // eax\n int v4; // ebx\n int v5; // ebp\n\n v2 = 0;\n if ( a2 > 0 )\n {\n for ( i = 0; i < a2; ++i )\n {\n v5 = *(_DWORD *)(a1 + 4LL * i);\n if ( v5 < 0 )\n {\n v4 = i + 1;\n v2 += func0(a1 + 4LL * i + 4, (unsigned int)-v5);\n i = ~v5 + v4;\n }\n else\n {\n v2 += v5;\n }\n }\n }\n return v2;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r12d, 0\ntest esi, esi\njle short loc_11E6\nmov r14, rdi\nmov r13d, esi\nmov eax, 0\njmp short loc_11CE\nloc_11AC:\nlea ebx, [rax+1]\nmov esi, ebp\nneg esi\nlea rdi, [r14+rcx+4]\ncall sub_1189\nadd r12d, eax\nnot ebp\nlea eax, [rbp+rbx+0]\nloc_11C6:\nadd eax, 1\ncmp r13d, eax\njle short loc_11E6\nloc_11CE:\nmovsxd rdx, eax\nlea rcx, ds:0[rdx*4]\nmov ebp, [r14+rdx*4]\ntest ebp, ebp\njs short loc_11AC\nadd r12d, ebp\njmp short loc_11C6\nloc_11E6:\nmov eax, r12d\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2)\n{\n unsigned int v2; // r12d\n int i; // eax\n int v4; // ebx\n int v5; // ebp\n\n v2 = 0;\n if ( a2 > 0 )\n {\n for ( i = 0; i < a2; ++i )\n {\n v5 = *(_DWORD *)(a1 + 4LL * i);\n if ( v5 < 0 )\n {\n v4 = i + 1;\n v2 += sub_1189(a1 + 4LL * i + 4, (unsigned int)-v5);\n i = ~v5 + v4;\n }\n else\n {\n v2 += v5;\n }\n }\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2) {\n unsigned int v2;\n int i;\n int v4;\n int v5;\n v2 = 0;\n if (a2 > 0) {\n for (i = 0; i < a2; ++i) {\n v5 = *(uint32_t *)(a1 + 4LL * i);\n if (v5 < 0) {\n v4 = i + 1;\n v2 += sub_1189(a1 + 4LL * i + 4, (unsigned int)-v5);\n i = ~v5 + v4;\n } else {\n v2 += v5;\n }\n }\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v2;\n int i;\n int v4;\n int v5;\n v2 = 0;\n if (a2 > 0) {\n for (i = 0; i < a2; ++i) {\n v5 = *(uint32_t *)(a1 + 4LL * i);\n if (v5 < 0) {\n v4 = i + 1;\n v2 += func0(a1 + 4LL * i + 4, (unsigned int)-v5);\n i = ~v5 + v4;\n } else {\n v2 += v5;\n }\n }\n }\n return v2;\n}" + }, + { + "index": 65, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int *data_list, int n) {\n int total = 0;\n for (int i = 0; i < n; i++) {\n if (data_list[i] < 0) {\n int sub_length = -data_list[i];\n i++;\n total += func0(&data_list[i], sub_length);\n i += sub_length - 1;\n } else {\n total += data_list[i];\n }\n }\n return total;\n}", + "test": "int main() {\n\n int list1[] = {1, 2, -2, 3, 4, -2, 5, 6};\n\n int list2[] = {7, 10, -2, 15, 14, -2, 19, 41};\n\n int list3[] = {10, 20, -2, 30, 40, -2, 50, 60};\n\n\n\n assert(func0(list1, 8) == 21);\n\n assert(func0(list2, 8) == 106);\n\n assert(func0(list3, 8) == 210);\n\n\n\n printf(\"All tests passed!\\n\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\nxor %r12d,%r12d\npush %rbp\npush %rbx\ntest %esi,%esi\njle 1359 \nmov %rdi,%r14\nmov %esi,%r13d\nxor %ebx,%ebx\nmovslq %ebx,%rax\nadd $0x1,%ebx\nmov (%r14,%rax,4),%ebp\nlea 0x0(,%rax,4),%rdx\ntest %ebp,%ebp\njs 1368 \nadd %ebp,%r12d\ncmp %ebx,%r13d\njg 133b \npop %rbx\nmov %r12d,%eax\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopl (%rax)\nmov %ebp,%esi\nlea 0x4(%r14,%rdx,1),%rdi\nsub %ebp,%ebx\nneg %esi\ncallq 1320 \nadd %eax,%r12d\njmp 1354 \nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\nxor r12d, r12d\npush rbp\npush rbx\ntest esi, esi\njle short loc_12F9\nmov r14, rdi\nmov r13d, esi\nxor eax, eax\nloc_12DB:\nmovsxd rdx, eax\nmov ebp, [r14+rdx*4]\nlea rcx, ds:0[rdx*4]\ntest ebp, ebp\njs short loc_1308\nadd r12d, ebp\nloc_12F1:\nadd eax, 1\ncmp r13d, eax\njg short loc_12DB\nloc_12F9:\npop rbx\nmov eax, r12d\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1308:\nmov esi, ebp\nlea rdi, [r14+rcx+4]\nlea ebx, [rax+1]\nnot ebp\nneg esi\ncall func0\nadd r12d, eax\nlea eax, [rbp+rbx+0]\njmp short loc_12F1", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v2; // r12d\n int i; // eax\n int v4; // ebp\n int v6; // ebx\n\n v2 = 0;\n if ( a2 > 0 )\n {\n for ( i = 0; i < a2; ++i )\n {\n v4 = *(_DWORD *)(a1 + 4LL * i);\n if ( v4 < 0 )\n {\n v6 = i + 1;\n v2 += func0(a1 + 4LL * i + 4, (unsigned int)-v4);\n i = ~v4 + v6;\n }\n else\n {\n v2 += v4;\n }\n }\n }\n return v2;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\npush r14\npush r13\npush r12\nxor r12d, r12d\npush rbp\npush rbx\ntest esi, esi\njle short loc_12F9\nmov r14, rdi\nmov r13d, esi\nxor eax, eax\nloc_12DB:\nmovsxd rdx, eax\nmov ebp, [r14+rdx*4]\nlea rcx, ds:0[rdx*4]\ntest ebp, ebp\njs short loc_1308\nadd r12d, ebp\nloc_12F1:\nadd eax, 1\ncmp r13d, eax\njg short loc_12DB\nloc_12F9:\npop rbx\nmov eax, r12d\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1308:\nmov esi, ebp\nlea rdi, [r14+rcx+4]\nlea ebx, [rax+1]\nnot ebp\nneg esi\ncall sub_12C0\nadd r12d, eax\nlea eax, [rbp+rbx+0]\njmp short loc_12F1", + "ida_strip_pseudo": "__int64 __fastcall sub_12C0(__int64 a1, int a2)\n{\n unsigned int v2; // r12d\n int i; // eax\n int v4; // ebp\n int v6; // ebx\n\n v2 = 0;\n if ( a2 > 0 )\n {\n for ( i = 0; i < a2; ++i )\n {\n v4 = *(_DWORD *)(a1 + 4LL * i);\n if ( v4 < 0 )\n {\n v6 = i + 1;\n v2 += sub_12C0(a1 + 4LL * i + 4, (unsigned int)-v4);\n i = ~v4 + v6;\n }\n else\n {\n v2 += v4;\n }\n }\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12C0(long long a1, int a2) {\n unsigned int v2;\n int i;\n int v4;\n int v6;\n v2 = 0;\n if (a2 > 0) {\n for (i = 0; i < a2; ++i) {\n v4 = *(uint32_t *)(a1 + 4LL * i);\n if (v4 < 0) {\n v6 = i + 1;\n v2 += sub_12C0(a1 + 4LL * i + 4, (unsigned int)-v4);\n i = ~v4 + v6;\n } else {\n v2 += v4;\n }\n }\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v2;\n int i;\n int v4;\n int v6;\n v2 = 0;\n if (a2 > 0) {\n for (i = 0; i < a2; ++i) {\n v4 = *(uint32_t *)(a1 + 4LL * i);\n if (v4 < 0) {\n v6 = i + 1;\n v2 += func0(a1 + 4LL * i + 4, (unsigned int)-v4);\n i = ~v4 + v6;\n } else {\n v2 += v4;\n }\n }\n }\n return v2;\n}" + }, + { + "index": 65, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int *data_list, int n) {\n int total = 0;\n for (int i = 0; i < n; i++) {\n if (data_list[i] < 0) {\n int sub_length = -data_list[i];\n i++;\n total += func0(&data_list[i], sub_length);\n i += sub_length - 1;\n } else {\n total += data_list[i];\n }\n }\n return total;\n}", + "test": "int main() {\n\n int list1[] = {1, 2, -2, 3, 4, -2, 5, 6};\n\n int list2[] = {7, 10, -2, 15, 14, -2, 19, 41};\n\n int list3[] = {10, 20, -2, 30, 40, -2, 50, 60};\n\n\n\n assert(func0(list1, 8) == 21);\n\n assert(func0(list2, 8) == 106);\n\n assert(func0(list3, 8) == 210);\n\n\n\n printf(\"All tests passed!\\n\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\nxor %r12d,%r12d\npush %rbp\npush %rbx\ntest %esi,%esi\njle 12f9 \nmov %rdi,%r14\nmov %esi,%r13d\nxor %ebx,%ebx\nmovslq %ebx,%rax\nadd $0x1,%ebx\nmov (%r14,%rax,4),%ebp\nlea 0x0(,%rax,4),%rdx\ntest %ebp,%ebp\njs 1308 \nadd %ebp,%r12d\ncmp %ebx,%r13d\njg 12db \npop %rbx\nmov %r12d,%eax\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopl (%rax)\nmov %ebp,%esi\nlea 0x4(%r14,%rdx,1),%rdi\nsub %ebp,%ebx\nneg %esi\ncallq 12c0 \nadd %eax,%r12d\ncmp %ebx,%r13d\njg 12db \npop %rbx\nmov %r12d,%eax\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nxor ebx, ebx\nsub rsp, 0C8h\ntest esi, esi\njle short loc_1305\nxor r15d, r15d\nmov r13, rdi\nmov r12d, esi\nloc_12E4:\nmovsxd rax, r15d\nmov r14d, [r13+rax*4+0]\nlea rdx, ds:0[rax*4]\ntest r14d, r14d\njs short loc_1320\nadd ebx, r14d\nloc_12FC:\nadd r15d, 1\ncmp r12d, r15d\njg short loc_12E4\nloc_1305:\nadd rsp, 0C8h\nmov eax, ebx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1320:\nmov r8d, r14d\nmov [rsp+0F8h+var_E8], r13\nadd r15d, 1\nxor ebp, ebp\nneg r8d\nlea rcx, [r13+rdx+4]\nmov [rsp+0F8h+var_F0], r14d\nxor eax, eax\nmov [rsp+0F8h+var_EC], r15d\nmov r14, rcx\nmov r15d, r8d\nmov [rsp+0F8h+var_E0], ebx\nmov ebx, r12d\nloc_134F:\nmovsxd rcx, eax\nmov r13d, [r14+rcx*4]\nlea rsi, ds:0[rcx*4]\ntest r13d, r13d\njs short loc_1398\nadd ebp, r13d\nloc_1366:\nadd eax, 1\ncmp r15d, eax\njg short loc_134F\nmov r14d, [rsp+0F8h+var_F0]\nmov r15d, [rsp+0F8h+var_EC]\nmov r12d, ebx\nmov ebx, [rsp+0F8h+var_E0]\nmov r13, [rsp+0F8h+var_E8]\nmov eax, r14d\nnot eax\nadd ebx, ebp\nadd r15d, eax\njmp loc_12FC\nloc_1398:\nadd eax, 1\nmov r8d, r13d\nmov [rsp+0F8h+var_D4], r13d\nlea rcx, [r14+rsi+4]\nmov [rsp+0F8h+var_DC], eax\nneg r8d\nxor r12d, r12d\nxor esi, esi\nmov [rsp+0F8h+var_C8], ebp\nmov [rsp+0F8h+var_D8], r15d\nmov r15d, r8d\nmov [rsp+0F8h+var_D0], r14\nmov r14, rcx\nloc_13C8:\nmovsxd rcx, esi\nmov r13d, [r14+rcx*4]\nlea rax, ds:0[rcx*4]\ntest r13d, r13d\njs short loc_1410\nadd r12d, r13d\nloc_13DF:\nadd esi, 1\ncmp esi, r15d\njl short loc_13C8\nmov r13d, [rsp+0F8h+var_D4]\nmov ebp, [rsp+0F8h+var_C8]\nmov edi, [rsp+0F8h+var_DC]\nmov r15d, [rsp+0F8h+var_D8]\nmov eax, r13d\nmov r14, [rsp+0F8h+var_D0]\nadd ebp, r12d\nnot eax\nadd eax, edi\njmp loc_1366\nloc_1410:\nlea edi, [rsi+1]\nmov r8d, r13d\nmov [rsp+0F8h+var_C0], r13d\nlea rcx, [r14+rax+4]\nmov [rsp+0F8h+var_C4], edi\nneg r8d\nxor ebp, ebp\nxor esi, esi\nmov [rsp+0F8h+var_BC], r12d\nmov [rsp+0F8h+var_B0], r15d\nmov r15d, r8d\nmov [rsp+0F8h+var_B8], r14\nmov r14, rcx\nloc_1440:\nmovsxd rcx, esi\nmov r13d, [r14+rcx*4]\nlea rax, ds:0[rcx*4]\ntest r13d, r13d\njs short loc_1490\nadd ebp, r13d\nloc_1457:\nadd esi, 1\ncmp esi, r15d\njl short loc_1440\nmov r13d, [rsp+0F8h+var_C0]\nmov r12d, [rsp+0F8h+var_BC]\nmov eax, [rsp+0F8h+var_C4]\nmov r15d, [rsp+0F8h+var_B0]\nmov esi, r13d\nmov r14, [rsp+0F8h+var_B8]\nadd r12d, ebp\nnot esi\nadd esi, eax\njmp loc_13DF\nloc_1490:\nlea edi, [rsi+1]\nmov r8d, r13d\nmov [rsp+0F8h+var_A0], r13d\nlea rcx, [r14+rax+4]\nmov [rsp+0F8h+var_AC], edi\nneg r8d\nxor r12d, r12d\nxor esi, esi\nmov [rsp+0F8h+var_9C], ebp\nmov [rsp+0F8h+var_A8], r14\nmov r14, rcx\nmov [rsp+0F8h+var_98], r15d\nmov r15d, r8d\nloc_14C0:\nmovsxd rdx, esi\nmov r13d, [r14+rdx*4]\nlea rax, ds:0[rdx*4]\ntest r13d, r13d\njs short loc_1508\nadd r12d, r13d\nloc_14D7:\nadd esi, 1\ncmp esi, r15d\njl short loc_14C0\nmov r13d, [rsp+0F8h+var_A0]\nmov ebp, [rsp+0F8h+var_9C]\nmov eax, [rsp+0F8h+var_AC]\nmov r14, [rsp+0F8h+var_A8]\nmov esi, r13d\nmov r15d, [rsp+0F8h+var_98]\nadd ebp, r12d\nnot esi\nadd esi, eax\njmp loc_1457\nloc_1508:\nlea edi, [rsi+1]\nmov r8d, r13d\nmov [rsp+0F8h+var_88], r13d\nlea rdx, [r14+rax+4]\nmov [rsp+0F8h+var_94], edi\nneg r8d\nxor ebp, ebp\nxor esi, esi\nmov [rsp+0F8h+var_80], r15d\nmov [rsp+0F8h+var_90], r14\nmov r14d, r8d\nmov [rsp+0F8h+var_84], r12d\nmov r12, rdx\nloc_1538:\nmovsxd rdx, esi\nmov r13d, [r12+rdx*4]\nlea rax, ds:0[rdx*4]\ntest r13d, r13d\njs short loc_1580\nadd ebp, r13d\nloc_154F:\nadd esi, 1\ncmp esi, r14d\njl short loc_1538\nmov r13d, [rsp+0F8h+var_88]\nmov r12d, [rsp+0F8h+var_84]\nmov eax, [rsp+0F8h+var_94]\nmov r14, [rsp+0F8h+var_90]\nmov esi, r13d\nmov r15d, [rsp+0F8h+var_80]\nadd r12d, ebp\nnot esi\nadd esi, eax\njmp loc_14D7\nloc_1580:\nlea edi, [rsi+1]\nmov ecx, r13d\nmov [rsp+0F8h+var_78], r12\nxor esi, esi\nmov [rsp+0F8h+var_7C], edi\nneg ecx\nlea rdx, [r12+rax+4]\nxor r15d, r15d\nmov [rsp+0F8h+var_68], r14d\nmov [rsp+0F8h+var_70], r13d\nmov r13, rdx\nmov [rsp+0F8h+var_6C], ebp\nmov ebp, ecx\nloc_15BA:\nmovsxd rcx, esi\nmov r12d, [r13+rcx*4+0]\nlea rax, ds:0[rcx*4]\ntest r12d, r12d\njs short loc_1610\nadd r15d, r12d\nloc_15D2:\nadd esi, 1\ncmp esi, ebp\njl short loc_15BA\nmov r13d, [rsp+0F8h+var_70]\nmov ebp, [rsp+0F8h+var_6C]\nmov eax, [rsp+0F8h+var_7C]\nmov r12, [rsp+0F8h+var_78]\nmov esi, r13d\nmov r14d, [rsp+0F8h+var_68]\nadd ebp, r15d\nnot esi\nadd esi, eax\njmp loc_154F\nloc_1610:\nlea edi, [rsi+1]\nlea r8, [r13+rax+4]\nmov ecx, r12d\nxor r14d, r14d\nmov [rsp+0F8h+var_64], edi\nneg ecx\nxor esi, esi\nmov edx, r12d\nmov [rsp+0F8h+var_60], r13\nmov r9d, ebp\nmov r13, r8\nmov r11d, r14d\nmov r8d, r15d\nmov r10d, ebx\nloc_1643:\nmovsxd rdi, esi\nmov ebx, [r13+rdi*4+0]\nlea rax, ds:0[rdi*4]\ntest ebx, ebx\njs short loc_1690\nadd r11d, ebx\nloc_165A:\nadd esi, 1\ncmp ecx, esi\njg short loc_1643\nmov eax, [rsp+0F8h+var_64]\nmov esi, edx\nmov r15d, r8d\nmov ebp, r9d\nnot esi\nmov r13, [rsp+0F8h+var_60]\nmov ebx, r10d\nadd r15d, r11d\nadd esi, eax\njmp loc_15D2\nloc_1690:\nlea edi, [rsi+1]\nmov r15d, ebx\nlea r14, [r13+rax+4]\nxor r12d, r12d\nmov [rsp+0F8h+var_58], edi\nneg r15d\nxor esi, esi\nloc_16AA:\nmovsxd rax, esi\nmov ebp, [r14+rax*4]\nlea rdi, ds:0[rax*4]\ntest ebp, ebp\njs short loc_16E0\nadd esi, 1\nadd r12d, ebp\ncmp r15d, esi\njg short loc_16AA\nloc_16C8:\nmov eax, [rsp+0F8h+var_58]\nnot ebx\nadd r11d, r12d\nmov esi, ebx\nadd esi, eax\njmp short loc_165A\nloc_16E0:\nmov [rsp+0F8h+var_4C], edx\nmov edx, ebp\nlea eax, [rsi+1]\nlea rdi, [r14+rdi+4]\nneg edx\nmov [rsp+0F8h+var_3C], r10d\nmov esi, edx\nmov [rsp+0F8h+var_40], r11d\nmov [rsp+0F8h+var_44], r9d\nmov [rsp+0F8h+var_48], r8d\nmov [rsp+0F8h+var_50], ecx\nmov [rsp+0F8h+var_54], eax\ncall func0\nmov esi, [rsp+0F8h+var_54]\nmov ecx, [rsp+0F8h+var_50]\nadd r12d, eax\nmov edx, [rsp+0F8h+var_4C]\nmov r8d, [rsp+0F8h+var_48]\nsub esi, ebp\nmov r9d, [rsp+0F8h+var_44]\nmov r11d, [rsp+0F8h+var_40]\ncmp r15d, esi\nmov r10d, [rsp+0F8h+var_3C]\njg loc_16AA\njmp loc_16C8", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v2; // ebx\n int v3; // r15d\n int v5; // r12d\n int v6; // r14d\n int v8; // ebp\n int v9; // r8d\n int v10; // eax\n __int64 v11; // r14\n int v12; // r15d\n int v13; // ebx\n int v14; // r13d\n int v15; // r12d\n int v16; // esi\n int v17; // r15d\n __int64 v18; // r14\n int v19; // r13d\n __int64 v20; // rax\n int v21; // ebp\n int v22; // esi\n int v23; // r15d\n __int64 v24; // r14\n int v25; // r13d\n __int64 v26; // rax\n int v27; // r12d\n int v28; // esi\n __int64 v29; // r14\n int v30; // r15d\n int v31; // r13d\n __int64 v32; // rdx\n int v33; // ebp\n int v34; // esi\n int v35; // r14d\n __int64 v36; // r12\n int v37; // r13d\n __int64 v38; // rax\n int v39; // edi\n int v40; // esi\n int v41; // ecx\n int v42; // r15d\n __int64 v43; // r13\n int v44; // ebp\n int v45; // r12d\n __int64 v46; // rax\n int v47; // ecx\n int v48; // esi\n int v49; // edx\n int v50; // r9d\n __int64 v51; // r13\n int v52; // r11d\n int v53; // r8d\n int v54; // r10d\n int v55; // ebx\n __int64 v56; // r14\n int v57; // r12d\n int v58; // r15d\n int v59; // esi\n int v60; // ebp\n int v61; // eax\n int v62; // [rsp+8h] [rbp-F0h]\n int v63; // [rsp+Ch] [rbp-ECh]\n __int64 v64; // [rsp+10h] [rbp-E8h]\n unsigned int v65; // [rsp+18h] [rbp-E0h]\n int v66; // [rsp+1Ch] [rbp-DCh]\n int v67; // [rsp+20h] [rbp-D8h]\n int v68; // [rsp+24h] [rbp-D4h]\n __int64 v69; // [rsp+28h] [rbp-D0h]\n int v70; // [rsp+30h] [rbp-C8h]\n int v71; // [rsp+34h] [rbp-C4h]\n int v72; // [rsp+38h] [rbp-C0h]\n int v73; // [rsp+3Ch] [rbp-BCh]\n __int64 v74; // [rsp+40h] [rbp-B8h]\n int v75; // [rsp+48h] [rbp-B0h]\n int v76; // [rsp+4Ch] [rbp-ACh]\n __int64 v77; // [rsp+50h] [rbp-A8h]\n int v78; // [rsp+58h] [rbp-A0h]\n int v79; // [rsp+5Ch] [rbp-9Ch]\n int v80; // [rsp+60h] [rbp-98h]\n int v81; // [rsp+64h] [rbp-94h]\n __int64 v82; // [rsp+68h] [rbp-90h]\n int v83; // [rsp+70h] [rbp-88h]\n int v84; // [rsp+74h] [rbp-84h]\n int v85; // [rsp+78h] [rbp-80h]\n __int64 v86; // [rsp+80h] [rbp-78h]\n int v87; // [rsp+88h] [rbp-70h]\n int v88; // [rsp+8Ch] [rbp-6Ch]\n int v89; // [rsp+90h] [rbp-68h]\n int v90; // [rsp+94h] [rbp-64h]\n __int64 v91; // [rsp+98h] [rbp-60h]\n int v92; // [rsp+A0h] [rbp-58h]\n int v93; // [rsp+A8h] [rbp-50h]\n int v94; // [rsp+ACh] [rbp-4Ch]\n int v95; // [rsp+B0h] [rbp-48h]\n int v96; // [rsp+B4h] [rbp-44h]\n int v97; // [rsp+B8h] [rbp-40h]\n int v98; // [rsp+BCh] [rbp-3Ch]\n\n v2 = 0;\n if ( a2 > 0 )\n {\n v3 = 0;\n v5 = a2;\n do\n {\n v6 = *(_DWORD *)(a1 + 4LL * v3);\n if ( v6 < 0 )\n {\n v64 = a1;\n v8 = 0;\n v9 = -v6;\n v62 = *(_DWORD *)(a1 + 4LL * v3);\n v10 = 0;\n v63 = v3 + 1;\n v11 = a1 + 4LL * v3 + 4;\n v12 = v9;\n v65 = v2;\n v13 = v5;\n do\n {\n v14 = *(_DWORD *)(v11 + 4LL * v10);\n if ( v14 < 0 )\n {\n v68 = *(_DWORD *)(v11 + 4LL * v10);\n v66 = v10 + 1;\n v15 = 0;\n v16 = 0;\n v70 = v8;\n v67 = v12;\n v17 = -v14;\n v69 = v11;\n v18 = v11 + 4LL * v10 + 4;\n do\n {\n v19 = *(_DWORD *)(v18 + 4LL * v16);\n v20 = 4LL * v16;\n if ( v19 < 0 )\n {\n v72 = *(_DWORD *)(v18 + 4LL * v16);\n v71 = v16 + 1;\n v21 = 0;\n v22 = 0;\n v73 = v15;\n v75 = v17;\n v23 = -v19;\n v74 = v18;\n v24 = v18 + v20 + 4;\n do\n {\n v25 = *(_DWORD *)(v24 + 4LL * v22);\n v26 = 4LL * v22;\n if ( v25 < 0 )\n {\n v78 = *(_DWORD *)(v24 + 4LL * v22);\n v76 = v22 + 1;\n v27 = 0;\n v28 = 0;\n v79 = v21;\n v77 = v24;\n v29 = v24 + v26 + 4;\n v80 = v23;\n v30 = -v25;\n do\n {\n v31 = *(_DWORD *)(v29 + 4LL * v28);\n if ( v31 < 0 )\n {\n v83 = *(_DWORD *)(v29 + 4LL * v28);\n v32 = v29 + 4LL * v28 + 4;\n v81 = v28 + 1;\n v33 = 0;\n v34 = 0;\n v85 = v30;\n v82 = v29;\n v35 = -v31;\n v84 = v27;\n v36 = v32;\n do\n {\n v37 = *(_DWORD *)(v36 + 4LL * v34);\n v38 = 4LL * v34;\n if ( v37 < 0 )\n {\n v39 = v34 + 1;\n v86 = v36;\n v40 = 0;\n v41 = -v37;\n v42 = 0;\n v89 = v35;\n v87 = v37;\n v43 = v36 + v38 + 4;\n v88 = v33;\n v44 = v41;\n do\n {\n v45 = *(_DWORD *)(v43 + 4LL * v40);\n v46 = 4LL * v40;\n if ( v45 < 0 )\n {\n v90 = v40 + 1;\n v47 = -v45;\n v48 = 0;\n v49 = v45;\n v91 = v43;\n v50 = v44;\n v51 = v43 + v46 + 4;\n v52 = 0;\n v53 = v42;\n v54 = v13;\n do\n {\n v55 = *(_DWORD *)(v51 + 4LL * v48);\n if ( v55 < 0 )\n {\n v56 = v51 + 4LL * v48 + 4;\n v57 = 0;\n v92 = v48 + 1;\n v58 = -v55;\n v59 = 0;\n do\n {\n while ( 1 )\n {\n v60 = *(_DWORD *)(v56 + 4LL * v59);\n if ( v60 < 0 )\n break;\n ++v59;\n v57 += v60;\n if ( v58 <= v59 )\n goto LABEL_45;\n }\n v94 = v49;\n v98 = v54;\n v97 = v52;\n v96 = v50;\n v95 = v53;\n v93 = v47;\n v61 = func0(v56 + 4LL * v59 + 4, (unsigned int)-v60);\n v47 = v93;\n v57 += v61;\n v49 = v94;\n v53 = v95;\n v59 = v59 + 1 - v60;\n v50 = v96;\n v52 = v97;\n v54 = v98;\n }\n while ( v58 > v59 );\nLABEL_45:\n v52 += v57;\n v48 = v92 + ~v55;\n }\n else\n {\n v52 += v55;\n }\n ++v48;\n }\n while ( v47 > v48 );\n v44 = v50;\n v43 = v91;\n v13 = v54;\n v42 = v52 + v53;\n v40 = v90 + ~v49;\n }\n else\n {\n v42 += v45;\n }\n ++v40;\n }\n while ( v40 < v44 );\n v36 = v86;\n v35 = v89;\n v33 = v42 + v88;\n v34 = v39 + ~v87;\n }\n else\n {\n v33 += v37;\n }\n ++v34;\n }\n while ( v34 < v35 );\n v29 = v82;\n v30 = v85;\n v27 = v33 + v84;\n v28 = v81 + ~v83;\n }\n else\n {\n v27 += v31;\n }\n ++v28;\n }\n while ( v28 < v30 );\n v24 = v77;\n v23 = v80;\n v21 = v27 + v79;\n v22 = v76 + ~v78;\n }\n else\n {\n v21 += v25;\n }\n ++v22;\n }\n while ( v22 < v23 );\n v17 = v75;\n v18 = v74;\n v15 = v21 + v73;\n v16 = v71 + ~v72;\n }\n else\n {\n v15 += v19;\n }\n ++v16;\n }\n while ( v16 < v17 );\n v12 = v67;\n v11 = v69;\n v8 = v15 + v70;\n v10 = v66 + ~v68;\n }\n else\n {\n v8 += v14;\n }\n ++v10;\n }\n while ( v12 > v10 );\n v5 = v13;\n a1 = v64;\n v2 = v8 + v65;\n v3 = ~v62 + v63;\n }\n else\n {\n v2 += v6;\n }\n ++v3;\n }\n while ( v5 > v3 );\n }\n return v2;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nxor ebx, ebx\nsub rsp, 0C8h\ntest esi, esi\njle short loc_1305\nxor r15d, r15d\nmov r13, rdi\nmov r12d, esi\nloc_12E4:\nmovsxd rax, r15d\nmov r14d, [r13+rax*4+0]\nlea rdx, ds:0[rax*4]\ntest r14d, r14d\njs short loc_1320\nadd ebx, r14d\nloc_12FC:\nadd r15d, 1\ncmp r12d, r15d\njg short loc_12E4\nloc_1305:\nadd rsp, 0C8h\nmov eax, ebx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1320:\nmov r8d, r14d\nmov [rsp+0F8h+var_E8], r13\nadd r15d, 1\nxor ebp, ebp\nneg r8d\nlea rcx, [r13+rdx+4]\nmov [rsp+0F8h+var_F0], r14d\nxor eax, eax\nmov [rsp+0F8h+var_EC], r15d\nmov r14, rcx\nmov r15d, r8d\nmov [rsp+0F8h+var_E0], ebx\nmov ebx, r12d\nloc_134F:\nmovsxd rcx, eax\nmov r13d, [r14+rcx*4]\nlea rsi, ds:0[rcx*4]\ntest r13d, r13d\njs short loc_1398\nadd ebp, r13d\nloc_1366:\nadd eax, 1\ncmp r15d, eax\njg short loc_134F\nmov r14d, [rsp+0F8h+var_F0]\nmov r15d, [rsp+0F8h+var_EC]\nmov r12d, ebx\nmov ebx, [rsp+0F8h+var_E0]\nmov r13, [rsp+0F8h+var_E8]\nmov eax, r14d\nnot eax\nadd ebx, ebp\nadd r15d, eax\njmp loc_12FC\nloc_1398:\nadd eax, 1\nmov r8d, r13d\nmov [rsp+0F8h+var_D4], r13d\nlea rcx, [r14+rsi+4]\nmov [rsp+0F8h+var_DC], eax\nneg r8d\nxor r12d, r12d\nxor esi, esi\nmov [rsp+0F8h+var_C8], ebp\nmov [rsp+0F8h+var_D8], r15d\nmov r15d, r8d\nmov [rsp+0F8h+var_D0], r14\nmov r14, rcx\nloc_13C8:\nmovsxd rcx, esi\nmov r13d, [r14+rcx*4]\nlea rax, ds:0[rcx*4]\ntest r13d, r13d\njs short loc_1410\nadd r12d, r13d\nloc_13DF:\nadd esi, 1\ncmp esi, r15d\njl short loc_13C8\nmov r13d, [rsp+0F8h+var_D4]\nmov ebp, [rsp+0F8h+var_C8]\nmov edi, [rsp+0F8h+var_DC]\nmov r15d, [rsp+0F8h+var_D8]\nmov eax, r13d\nmov r14, [rsp+0F8h+var_D0]\nadd ebp, r12d\nnot eax\nadd eax, edi\njmp loc_1366\nloc_1410:\nlea edi, [rsi+1]\nmov r8d, r13d\nmov [rsp+0F8h+var_C0], r13d\nlea rcx, [r14+rax+4]\nmov [rsp+0F8h+var_C4], edi\nneg r8d\nxor ebp, ebp\nxor esi, esi\nmov [rsp+0F8h+var_BC], r12d\nmov [rsp+0F8h+var_B0], r15d\nmov r15d, r8d\nmov [rsp+0F8h+var_B8], r14\nmov r14, rcx\nloc_1440:\nmovsxd rcx, esi\nmov r13d, [r14+rcx*4]\nlea rax, ds:0[rcx*4]\ntest r13d, r13d\njs short loc_1490\nadd ebp, r13d\nloc_1457:\nadd esi, 1\ncmp esi, r15d\njl short loc_1440\nmov r13d, [rsp+0F8h+var_C0]\nmov r12d, [rsp+0F8h+var_BC]\nmov eax, [rsp+0F8h+var_C4]\nmov r15d, [rsp+0F8h+var_B0]\nmov esi, r13d\nmov r14, [rsp+0F8h+var_B8]\nadd r12d, ebp\nnot esi\nadd esi, eax\njmp loc_13DF\nloc_1490:\nlea edi, [rsi+1]\nmov r8d, r13d\nmov [rsp+0F8h+var_A0], r13d\nlea rcx, [r14+rax+4]\nmov [rsp+0F8h+var_AC], edi\nneg r8d\nxor r12d, r12d\nxor esi, esi\nmov [rsp+0F8h+var_9C], ebp\nmov [rsp+0F8h+var_A8], r14\nmov r14, rcx\nmov [rsp+0F8h+var_98], r15d\nmov r15d, r8d\nloc_14C0:\nmovsxd rdx, esi\nmov r13d, [r14+rdx*4]\nlea rax, ds:0[rdx*4]\ntest r13d, r13d\njs short loc_1508\nadd r12d, r13d\nloc_14D7:\nadd esi, 1\ncmp esi, r15d\njl short loc_14C0\nmov r13d, [rsp+0F8h+var_A0]\nmov ebp, [rsp+0F8h+var_9C]\nmov eax, [rsp+0F8h+var_AC]\nmov r14, [rsp+0F8h+var_A8]\nmov esi, r13d\nmov r15d, [rsp+0F8h+var_98]\nadd ebp, r12d\nnot esi\nadd esi, eax\njmp loc_1457\nloc_1508:\nlea edi, [rsi+1]\nmov r8d, r13d\nmov [rsp+0F8h+var_88], r13d\nlea rdx, [r14+rax+4]\nmov [rsp+0F8h+var_94], edi\nneg r8d\nxor ebp, ebp\nxor esi, esi\nmov [rsp+0F8h+var_80], r15d\nmov [rsp+0F8h+var_90], r14\nmov r14d, r8d\nmov [rsp+0F8h+var_84], r12d\nmov r12, rdx\nloc_1538:\nmovsxd rdx, esi\nmov r13d, [r12+rdx*4]\nlea rax, ds:0[rdx*4]\ntest r13d, r13d\njs short loc_1580\nadd ebp, r13d\nloc_154F:\nadd esi, 1\ncmp esi, r14d\njl short loc_1538\nmov r13d, [rsp+0F8h+var_88]\nmov r12d, [rsp+0F8h+var_84]\nmov eax, [rsp+0F8h+var_94]\nmov r14, [rsp+0F8h+var_90]\nmov esi, r13d\nmov r15d, [rsp+0F8h+var_80]\nadd r12d, ebp\nnot esi\nadd esi, eax\njmp loc_14D7\nloc_1580:\nlea edi, [rsi+1]\nmov ecx, r13d\nmov [rsp+0F8h+var_78], r12\nxor esi, esi\nmov [rsp+0F8h+var_7C], edi\nneg ecx\nlea rdx, [r12+rax+4]\nxor r15d, r15d\nmov [rsp+0F8h+var_68], r14d\nmov [rsp+0F8h+var_70], r13d\nmov r13, rdx\nmov [rsp+0F8h+var_6C], ebp\nmov ebp, ecx\nloc_15BA:\nmovsxd rcx, esi\nmov r12d, [r13+rcx*4+0]\nlea rax, ds:0[rcx*4]\ntest r12d, r12d\njs short loc_1610\nadd r15d, r12d\nloc_15D2:\nadd esi, 1\ncmp esi, ebp\njl short loc_15BA\nmov r13d, [rsp+0F8h+var_70]\nmov ebp, [rsp+0F8h+var_6C]\nmov eax, [rsp+0F8h+var_7C]\nmov r12, [rsp+0F8h+var_78]\nmov esi, r13d\nmov r14d, [rsp+0F8h+var_68]\nadd ebp, r15d\nnot esi\nadd esi, eax\njmp loc_154F\nloc_1610:\nlea edi, [rsi+1]\nlea r8, [r13+rax+4]\nmov ecx, r12d\nxor r14d, r14d\nmov [rsp+0F8h+var_64], edi\nneg ecx\nxor esi, esi\nmov edx, r12d\nmov [rsp+0F8h+var_60], r13\nmov r9d, ebp\nmov r13, r8\nmov r11d, r14d\nmov r8d, r15d\nmov r10d, ebx\nloc_1643:\nmovsxd rdi, esi\nmov ebx, [r13+rdi*4+0]\nlea rax, ds:0[rdi*4]\ntest ebx, ebx\njs short loc_1690\nadd r11d, ebx\nloc_165A:\nadd esi, 1\ncmp ecx, esi\njg short loc_1643\nmov eax, [rsp+0F8h+var_64]\nmov esi, edx\nmov r15d, r8d\nmov ebp, r9d\nnot esi\nmov r13, [rsp+0F8h+var_60]\nmov ebx, r10d\nadd r15d, r11d\nadd esi, eax\njmp loc_15D2\nloc_1690:\nlea edi, [rsi+1]\nmov r15d, ebx\nlea r14, [r13+rax+4]\nxor r12d, r12d\nmov [rsp+0F8h+var_58], edi\nneg r15d\nxor esi, esi\nloc_16AA:\nmovsxd rax, esi\nmov ebp, [r14+rax*4]\nlea rdi, ds:0[rax*4]\ntest ebp, ebp\njs short loc_16E0\nadd esi, 1\nadd r12d, ebp\ncmp r15d, esi\njg short loc_16AA\nloc_16C8:\nmov eax, [rsp+0F8h+var_58]\nnot ebx\nadd r11d, r12d\nmov esi, ebx\nadd esi, eax\njmp short loc_165A\nloc_16E0:\nmov [rsp+0F8h+var_4C], edx\nmov edx, ebp\nlea eax, [rsi+1]\nlea rdi, [r14+rdi+4]\nneg edx\nmov [rsp+0F8h+var_3C], r10d\nmov esi, edx\nmov [rsp+0F8h+var_40], r11d\nmov [rsp+0F8h+var_44], r9d\nmov [rsp+0F8h+var_48], r8d\nmov [rsp+0F8h+var_50], ecx\nmov [rsp+0F8h+var_54], eax\ncall sub_12C0\nmov esi, [rsp+0F8h+var_54]\nmov ecx, [rsp+0F8h+var_50]\nadd r12d, eax\nmov edx, [rsp+0F8h+var_4C]\nmov r8d, [rsp+0F8h+var_48]\nsub esi, ebp\nmov r9d, [rsp+0F8h+var_44]\nmov r11d, [rsp+0F8h+var_40]\ncmp r15d, esi\nmov r10d, [rsp+0F8h+var_3C]\njg loc_16AA\njmp loc_16C8", + "ida_strip_pseudo": "__int64 __fastcall sub_12C0(__int64 a1, int a2)\n{\n unsigned int v2; // ebx\n int v3; // r15d\n int v5; // r12d\n int v6; // r14d\n int v8; // ebp\n int v9; // r8d\n int v10; // eax\n __int64 v11; // r14\n int v12; // r15d\n int v13; // ebx\n int v14; // r13d\n int v15; // r12d\n int v16; // esi\n int v17; // r15d\n __int64 v18; // r14\n int v19; // r13d\n __int64 v20; // rax\n int v21; // ebp\n int v22; // esi\n int v23; // r15d\n __int64 v24; // r14\n int v25; // r13d\n __int64 v26; // rax\n int v27; // r12d\n int v28; // esi\n __int64 v29; // r14\n int v30; // r15d\n int v31; // r13d\n __int64 v32; // rdx\n int v33; // ebp\n int v34; // esi\n int v35; // r14d\n __int64 v36; // r12\n int v37; // r13d\n __int64 v38; // rax\n int v39; // edi\n int v40; // esi\n int v41; // ecx\n int v42; // r15d\n __int64 v43; // r13\n int v44; // ebp\n int v45; // r12d\n __int64 v46; // rax\n int v47; // ecx\n int v48; // esi\n int v49; // edx\n int v50; // r9d\n __int64 v51; // r13\n int v52; // r11d\n int v53; // r8d\n int v54; // r10d\n int v55; // ebx\n __int64 v56; // r14\n int v57; // r12d\n int v58; // r15d\n int v59; // esi\n int v60; // ebp\n int v61; // eax\n int v62; // [rsp+8h] [rbp-F0h]\n int v63; // [rsp+Ch] [rbp-ECh]\n __int64 v64; // [rsp+10h] [rbp-E8h]\n unsigned int v65; // [rsp+18h] [rbp-E0h]\n int v66; // [rsp+1Ch] [rbp-DCh]\n int v67; // [rsp+20h] [rbp-D8h]\n int v68; // [rsp+24h] [rbp-D4h]\n __int64 v69; // [rsp+28h] [rbp-D0h]\n int v70; // [rsp+30h] [rbp-C8h]\n int v71; // [rsp+34h] [rbp-C4h]\n int v72; // [rsp+38h] [rbp-C0h]\n int v73; // [rsp+3Ch] [rbp-BCh]\n __int64 v74; // [rsp+40h] [rbp-B8h]\n int v75; // [rsp+48h] [rbp-B0h]\n int v76; // [rsp+4Ch] [rbp-ACh]\n __int64 v77; // [rsp+50h] [rbp-A8h]\n int v78; // [rsp+58h] [rbp-A0h]\n int v79; // [rsp+5Ch] [rbp-9Ch]\n int v80; // [rsp+60h] [rbp-98h]\n int v81; // [rsp+64h] [rbp-94h]\n __int64 v82; // [rsp+68h] [rbp-90h]\n int v83; // [rsp+70h] [rbp-88h]\n int v84; // [rsp+74h] [rbp-84h]\n int v85; // [rsp+78h] [rbp-80h]\n __int64 v86; // [rsp+80h] [rbp-78h]\n int v87; // [rsp+88h] [rbp-70h]\n int v88; // [rsp+8Ch] [rbp-6Ch]\n int v89; // [rsp+90h] [rbp-68h]\n int v90; // [rsp+94h] [rbp-64h]\n __int64 v91; // [rsp+98h] [rbp-60h]\n int v92; // [rsp+A0h] [rbp-58h]\n int v93; // [rsp+A8h] [rbp-50h]\n int v94; // [rsp+ACh] [rbp-4Ch]\n int v95; // [rsp+B0h] [rbp-48h]\n int v96; // [rsp+B4h] [rbp-44h]\n int v97; // [rsp+B8h] [rbp-40h]\n int v98; // [rsp+BCh] [rbp-3Ch]\n\n v2 = 0;\n if ( a2 > 0 )\n {\n v3 = 0;\n v5 = a2;\n do\n {\n v6 = *(_DWORD *)(a1 + 4LL * v3);\n if ( v6 < 0 )\n {\n v64 = a1;\n v8 = 0;\n v9 = -v6;\n v62 = *(_DWORD *)(a1 + 4LL * v3);\n v10 = 0;\n v63 = v3 + 1;\n v11 = a1 + 4LL * v3 + 4;\n v12 = v9;\n v65 = v2;\n v13 = v5;\n do\n {\n v14 = *(_DWORD *)(v11 + 4LL * v10);\n if ( v14 < 0 )\n {\n v68 = *(_DWORD *)(v11 + 4LL * v10);\n v66 = v10 + 1;\n v15 = 0;\n v16 = 0;\n v70 = v8;\n v67 = v12;\n v17 = -v14;\n v69 = v11;\n v18 = v11 + 4LL * v10 + 4;\n do\n {\n v19 = *(_DWORD *)(v18 + 4LL * v16);\n v20 = 4LL * v16;\n if ( v19 < 0 )\n {\n v72 = *(_DWORD *)(v18 + 4LL * v16);\n v71 = v16 + 1;\n v21 = 0;\n v22 = 0;\n v73 = v15;\n v75 = v17;\n v23 = -v19;\n v74 = v18;\n v24 = v18 + v20 + 4;\n do\n {\n v25 = *(_DWORD *)(v24 + 4LL * v22);\n v26 = 4LL * v22;\n if ( v25 < 0 )\n {\n v78 = *(_DWORD *)(v24 + 4LL * v22);\n v76 = v22 + 1;\n v27 = 0;\n v28 = 0;\n v79 = v21;\n v77 = v24;\n v29 = v24 + v26 + 4;\n v80 = v23;\n v30 = -v25;\n do\n {\n v31 = *(_DWORD *)(v29 + 4LL * v28);\n if ( v31 < 0 )\n {\n v83 = *(_DWORD *)(v29 + 4LL * v28);\n v32 = v29 + 4LL * v28 + 4;\n v81 = v28 + 1;\n v33 = 0;\n v34 = 0;\n v85 = v30;\n v82 = v29;\n v35 = -v31;\n v84 = v27;\n v36 = v32;\n do\n {\n v37 = *(_DWORD *)(v36 + 4LL * v34);\n v38 = 4LL * v34;\n if ( v37 < 0 )\n {\n v39 = v34 + 1;\n v86 = v36;\n v40 = 0;\n v41 = -v37;\n v42 = 0;\n v89 = v35;\n v87 = v37;\n v43 = v36 + v38 + 4;\n v88 = v33;\n v44 = v41;\n do\n {\n v45 = *(_DWORD *)(v43 + 4LL * v40);\n v46 = 4LL * v40;\n if ( v45 < 0 )\n {\n v90 = v40 + 1;\n v47 = -v45;\n v48 = 0;\n v49 = v45;\n v91 = v43;\n v50 = v44;\n v51 = v43 + v46 + 4;\n v52 = 0;\n v53 = v42;\n v54 = v13;\n do\n {\n v55 = *(_DWORD *)(v51 + 4LL * v48);\n if ( v55 < 0 )\n {\n v56 = v51 + 4LL * v48 + 4;\n v57 = 0;\n v92 = v48 + 1;\n v58 = -v55;\n v59 = 0;\n do\n {\n while ( 1 )\n {\n v60 = *(_DWORD *)(v56 + 4LL * v59);\n if ( v60 < 0 )\n break;\n ++v59;\n v57 += v60;\n if ( v58 <= v59 )\n goto LABEL_45;\n }\n v94 = v49;\n v98 = v54;\n v97 = v52;\n v96 = v50;\n v95 = v53;\n v93 = v47;\n v61 = sub_12C0(v56 + 4LL * v59 + 4, (unsigned int)-v60);\n v47 = v93;\n v57 += v61;\n v49 = v94;\n v53 = v95;\n v59 = v59 + 1 - v60;\n v50 = v96;\n v52 = v97;\n v54 = v98;\n }\n while ( v58 > v59 );\nLABEL_45:\n v52 += v57;\n v48 = v92 + ~v55;\n }\n else\n {\n v52 += v55;\n }\n ++v48;\n }\n while ( v47 > v48 );\n v44 = v50;\n v43 = v91;\n v13 = v54;\n v42 = v52 + v53;\n v40 = v90 + ~v49;\n }\n else\n {\n v42 += v45;\n }\n ++v40;\n }\n while ( v40 < v44 );\n v36 = v86;\n v35 = v89;\n v33 = v42 + v88;\n v34 = v39 + ~v87;\n }\n else\n {\n v33 += v37;\n }\n ++v34;\n }\n while ( v34 < v35 );\n v29 = v82;\n v30 = v85;\n v27 = v33 + v84;\n v28 = v81 + ~v83;\n }\n else\n {\n v27 += v31;\n }\n ++v28;\n }\n while ( v28 < v30 );\n v24 = v77;\n v23 = v80;\n v21 = v27 + v79;\n v22 = v76 + ~v78;\n }\n else\n {\n v21 += v25;\n }\n ++v22;\n }\n while ( v22 < v23 );\n v17 = v75;\n v18 = v74;\n v15 = v21 + v73;\n v16 = v71 + ~v72;\n }\n else\n {\n v15 += v19;\n }\n ++v16;\n }\n while ( v16 < v17 );\n v12 = v67;\n v11 = v69;\n v8 = v15 + v70;\n v10 = v66 + ~v68;\n }\n else\n {\n v8 += v14;\n }\n ++v10;\n }\n while ( v12 > v10 );\n v5 = v13;\n a1 = v64;\n v2 = v8 + v65;\n v3 = ~v62 + v63;\n }\n else\n {\n v2 += v6;\n }\n ++v3;\n }\n while ( v5 > v3 );\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12C0(long long a1, int a2) {\n unsigned int v2;\n int v3;\n int v5;\n int v6;\n int v8;\n int v9;\n int v10;\n long long v11;\n int v12;\n int v13;\n int v14;\n int v15;\n int v16;\n int v17;\n long long v18;\n int v19;\n long long v20;\n int v21;\n int v22;\n int v23;\n long long v24;\n int v25;\n long long v26;\n int v27;\n int v28;\n long long v29;\n int v30;\n int v31;\n long long v32;\n int v33;\n int v34;\n int v35;\n long long v36;\n int v37;\n long long v38;\n int v39;\n int v40;\n int v41;\n int v42;\n long long v43;\n int v44;\n int v45;\n long long v46;\n int v47;\n int v48;\n int v49;\n int v50;\n long long v51;\n int v52;\n int v53;\n int v54;\n int v55;\n long long v56;\n int v57;\n int v58;\n int v59;\n int v60;\n int v61;\n int v62;\n int v63;\n long long v64;\n unsigned int v65;\n int v66;\n int v67;\n int v68;\n long long v69;\n int v70;\n int v71;\n int v72;\n int v73;\n long long v74;\n int v75;\n int v76;\n long long v77;\n int v78;\n int v79;\n int v80;\n int v81;\n long long v82;\n int v83;\n int v84;\n int v85;\n long long v86;\n int v87;\n int v88;\n int v89;\n int v90;\n long long v91;\n int v92;\n int v93;\n int v94;\n int v95;\n int v96;\n int v97;\n int v98;\n v2 = 0;\n if (a2 > 0) {\n v3 = 0;\n v5 = a2;\n do {\n v6 = *(uint32_t *)(a1 + 4LL * v3);\n if (v6 < 0) {\n v64 = a1;\n v8 = 0;\n v9 = -v6;\n v62 = *(uint32_t *)(a1 + 4LL * v3);\n v10 = 0;\n v63 = v3 + 1;\n v11 = a1 + 4LL * v3 + 4;\n v12 = v9;\n v65 = v2;\n v13 = v5;\n do {\n v14 = *(uint32_t *)(v11 + 4LL * v10);\n if (v14 < 0) {\n v68 = *(uint32_t *)(v11 + 4LL * v10);\n v66 = v10 + 1;\n v15 = 0;\n v16 = 0;\n v70 = v8;\n v67 = v12;\n v17 = -v14;\n v69 = v11;\n v18 = v11 + 4LL * v10 + 4;\n do {\n v19 = *(uint32_t *)(v18 + 4LL * v16);\n v20 = 4LL * v16;\n if (v19 < 0) {\n v72 = *(uint32_t *)(v18 + 4LL * v16);\n v71 = v16 + 1;\n v21 = 0;\n v22 = 0;\n v73 = v15;\n v75 = v17;\n v23 = -v19;\n v74 = v18;\n v24 = v18 + v20 + 4;\n do {\n v25 = *(uint32_t *)(v24 + 4LL * v22);\n v26 = 4LL * v22;\n if (v25 < 0) {\n v78 = *(uint32_t *)(v24 + 4LL * v22);\n v76 = v22 + 1;\n v27 = 0;\n v28 = 0;\n v79 = v21;\n v77 = v24;\n v29 = v24 + v26 + 4;\n v80 = v23;\n v30 = -v25;\n do {\n v31 = *(uint32_t *)(v29 + 4LL * v28);\n if (v31 < 0) {\n v83 = *(uint32_t *)(v29 + 4LL * v28);\n v32 = v29 + 4LL * v28 + 4;\n v81 = v28 + 1;\n v33 = 0;\n v34 = 0;\n v85 = v30;\n v82 = v29;\n v35 = -v31;\n v84 = v27;\n v36 = v32;\n do {\n v37 = *(uint32_t *)(v36 + 4LL * v34);\n v38 = 4LL * v34;\n if (v37 < 0) {\n v39 = v34 + 1;\n v86 = v36;\n v40 = 0;\n v41 = -v37;\n v42 = 0;\n v89 = v35;\n v87 = v37;\n v43 = v36 + v38 + 4;\n v88 = v33;\n v44 = v41;\n do {\n v45 = *(uint32_t *)(v43 + 4LL * v40);\n v46 = 4LL * v40;\n if (v45 < 0) {\n v90 = v40 + 1;\n v47 = -v45;\n v48 = 0;\n v49 = v45;\n v91 = v43;\n v50 = v44;\n v51 = v43 + v46 + 4;\n v52 = 0;\n v53 = v42;\n v54 = v13;\n do {\n v55 = *(uint32_t *)(v51 + 4LL * v48);\n if (v55 < 0) {\n v56 = v51 + 4LL * v48 + 4;\n v57 = 0;\n v92 = v48 + 1;\n v58 = -v55;\n v59 = 0;\n do {\n while (1) {\n v60 = *(uint32_t *)(v56 + 4LL * v59);\n if (v60 < 0) break;\n ++v59;\n v57 += v60;\n if (v58 <= v59) goto LABEL_45;\n }\n v94 = v49;\n v98 = v54;\n v97 = v52;\n v96 = v50;\n v95 = v53;\n v93 = v47;\n v61 = sub_12C0(v56 + 4LL * v59 + 4,\n (unsigned int)-v60);\n v47 = v93;\n v57 += v61;\n v49 = v94;\n v53 = v95;\n v59 = v59 + 1 - v60;\n v50 = v96;\n v52 = v97;\n v54 = v98;\n } while (v58 > v59);\n LABEL_45:\n v52 += v57;\n v48 = v92 + ~v55;\n } else {\n v52 += v55;\n }\n ++v48;\n } while (v47 > v48);\n v44 = v50;\n v43 = v91;\n v13 = v54;\n v42 = v52 + v53;\n v40 = v90 + ~v49;\n } else {\n v42 += v45;\n }\n ++v40;\n } while (v40 < v44);\n v36 = v86;\n v35 = v89;\n v33 = v42 + v88;\n v34 = v39 + ~v87;\n } else {\n v33 += v37;\n }\n ++v34;\n } while (v34 < v35);\n v29 = v82;\n v30 = v85;\n v27 = v33 + v84;\n v28 = v81 + ~v83;\n } else {\n v27 += v31;\n }\n ++v28;\n } while (v28 < v30);\n v24 = v77;\n v23 = v80;\n v21 = v27 + v79;\n v22 = v76 + ~v78;\n } else {\n v21 += v25;\n }\n ++v22;\n } while (v22 < v23);\n v17 = v75;\n v18 = v74;\n v15 = v21 + v73;\n v16 = v71 + ~v72;\n } else {\n v15 += v19;\n }\n ++v16;\n } while (v16 < v17);\n v12 = v67;\n v11 = v69;\n v8 = v15 + v70;\n v10 = v66 + ~v68;\n } else {\n v8 += v14;\n }\n ++v10;\n } while (v12 > v10);\n v5 = v13;\n a1 = v64;\n v2 = v8 + v65;\n v3 = ~v62 + v63;\n } else {\n v2 += v6;\n }\n ++v3;\n } while (v5 > v3);\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v2;\n int v3;\n int v5;\n int v6;\n int v8;\n int v9;\n int v10;\n long long v11;\n int v12;\n int v13;\n int v14;\n int v15;\n int v16;\n int v17;\n long long v18;\n int v19;\n long long v20;\n int v21;\n int v22;\n int v23;\n long long v24;\n int v25;\n long long v26;\n int v27;\n int v28;\n long long v29;\n int v30;\n int v31;\n long long v32;\n int v33;\n int v34;\n int v35;\n long long v36;\n int v37;\n long long v38;\n int v39;\n int v40;\n int v41;\n int v42;\n long long v43;\n int v44;\n int v45;\n long long v46;\n int v47;\n int v48;\n int v49;\n int v50;\n long long v51;\n int v52;\n int v53;\n int v54;\n int v55;\n long long v56;\n int v57;\n int v58;\n int v59;\n int v60;\n int v61;\n int v62;\n int v63;\n long long v64;\n unsigned int v65;\n int v66;\n int v67;\n int v68;\n long long v69;\n int v70;\n int v71;\n int v72;\n int v73;\n long long v74;\n int v75;\n int v76;\n long long v77;\n int v78;\n int v79;\n int v80;\n int v81;\n long long v82;\n int v83;\n int v84;\n int v85;\n long long v86;\n int v87;\n int v88;\n int v89;\n int v90;\n long long v91;\n int v92;\n int v93;\n int v94;\n int v95;\n int v96;\n int v97;\n int v98;\n v2 = 0;\n if (a2 > 0) {\n v3 = 0;\n v5 = a2;\n do {\n v6 = *(uint32_t *)(a1 + 4LL * v3);\n if (v6 < 0) {\n v64 = a1;\n v8 = 0;\n v9 = -v6;\n v62 = *(uint32_t *)(a1 + 4LL * v3);\n v10 = 0;\n v63 = v3 + 1;\n v11 = a1 + 4LL * v3 + 4;\n v12 = v9;\n v65 = v2;\n v13 = v5;\n do {\n v14 = *(uint32_t *)(v11 + 4LL * v10);\n if (v14 < 0) {\n v68 = *(uint32_t *)(v11 + 4LL * v10);\n v66 = v10 + 1;\n v15 = 0;\n v16 = 0;\n v70 = v8;\n v67 = v12;\n v17 = -v14;\n v69 = v11;\n v18 = v11 + 4LL * v10 + 4;\n do {\n v19 = *(uint32_t *)(v18 + 4LL * v16);\n v20 = 4LL * v16;\n if (v19 < 0) {\n v72 = *(uint32_t *)(v18 + 4LL * v16);\n v71 = v16 + 1;\n v21 = 0;\n v22 = 0;\n v73 = v15;\n v75 = v17;\n v23 = -v19;\n v74 = v18;\n v24 = v18 + v20 + 4;\n do {\n v25 = *(uint32_t *)(v24 + 4LL * v22);\n v26 = 4LL * v22;\n if (v25 < 0) {\n v78 = *(uint32_t *)(v24 + 4LL * v22);\n v76 = v22 + 1;\n v27 = 0;\n v28 = 0;\n v79 = v21;\n v77 = v24;\n v29 = v24 + v26 + 4;\n v80 = v23;\n v30 = -v25;\n do {\n v31 = *(uint32_t *)(v29 + 4LL * v28);\n if (v31 < 0) {\n v83 = *(uint32_t *)(v29 + 4LL * v28);\n v32 = v29 + 4LL * v28 + 4;\n v81 = v28 + 1;\n v33 = 0;\n v34 = 0;\n v85 = v30;\n v82 = v29;\n v35 = -v31;\n v84 = v27;\n v36 = v32;\n do {\n v37 = *(uint32_t *)(v36 + 4LL * v34);\n v38 = 4LL * v34;\n if (v37 < 0) {\n v39 = v34 + 1;\n v86 = v36;\n v40 = 0;\n v41 = -v37;\n v42 = 0;\n v89 = v35;\n v87 = v37;\n v43 = v36 + v38 + 4;\n v88 = v33;\n v44 = v41;\n do {\n v45 = *(uint32_t *)(v43 + 4LL * v40);\n v46 = 4LL * v40;\n if (v45 < 0) {\n v90 = v40 + 1;\n v47 = -v45;\n v48 = 0;\n v49 = v45;\n v91 = v43;\n v50 = v44;\n v51 = v43 + v46 + 4;\n v52 = 0;\n v53 = v42;\n v54 = v13;\n do {\n v55 = *(uint32_t *)(v51 + 4LL * v48);\n if (v55 < 0) {\n v56 = v51 + 4LL * v48 + 4;\n v57 = 0;\n v92 = v48 + 1;\n v58 = -v55;\n v59 = 0;\n do {\n while (1) {\n v60 = *(uint32_t *)(v56 + 4LL * v59);\n if (v60 < 0) break;\n ++v59;\n v57 += v60;\n if (v58 <= v59) goto LABEL_45;\n }\n v94 = v49;\n v98 = v54;\n v97 = v52;\n v96 = v50;\n v95 = v53;\n v93 = v47;\n v61 = func0(v56 + 4LL * v59 + 4,\n (unsigned int)-v60);\n v47 = v93;\n v57 += v61;\n v49 = v94;\n v53 = v95;\n v59 = v59 + 1 - v60;\n v50 = v96;\n v52 = v97;\n v54 = v98;\n } while (v58 > v59);\n LABEL_45:\n v52 += v57;\n v48 = v92 + ~v55;\n } else {\n v52 += v55;\n }\n ++v48;\n } while (v47 > v48);\n v44 = v50;\n v43 = v91;\n v13 = v54;\n v42 = v52 + v53;\n v40 = v90 + ~v49;\n } else {\n v42 += v45;\n }\n ++v40;\n } while (v40 < v44);\n v36 = v86;\n v35 = v89;\n v33 = v42 + v88;\n v34 = v39 + ~v87;\n } else {\n v33 += v37;\n }\n ++v34;\n } while (v34 < v35);\n v29 = v82;\n v30 = v85;\n v27 = v33 + v84;\n v28 = v81 + ~v83;\n } else {\n v27 += v31;\n }\n ++v28;\n } while (v28 < v30);\n v24 = v77;\n v23 = v80;\n v21 = v27 + v79;\n v22 = v76 + ~v78;\n } else {\n v21 += v25;\n }\n ++v22;\n } while (v22 < v23);\n v17 = v75;\n v18 = v74;\n v15 = v21 + v73;\n v16 = v71 + ~v72;\n } else {\n v15 += v19;\n }\n ++v16;\n } while (v16 < v17);\n v12 = v67;\n v11 = v69;\n v8 = v15 + v70;\n v10 = v66 + ~v68;\n } else {\n v8 += v14;\n }\n ++v10;\n } while (v12 > v10);\n v5 = v13;\n a1 = v64;\n v2 = v8 + v65;\n v3 = ~v62 + v63;\n } else {\n v2 += v6;\n }\n ++v3;\n } while (v5 > v3);\n }\n return v2;\n}" + }, + { + "index": 66, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int* list, int list_size) {\n int pos_count = 0;\n for (int i = 0; i < list_size; i++) {\n if (list[i] >= 0) {\n pos_count++;\n }\n }\n return pos_count;\n}", + "test": "int main() {\n\n int list1[] = {1, -2, 3, -4};\n\n int list2[] = {3, 4, 5, -1};\n\n int list3[] = {1, 2, 3, 4};\n\n\n\n assert(func0(list1, 4) == 2);\n\n assert(func0(list2, 4) == 3);\n\n assert(func0(list3, 4) == 4);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11aa \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ntest %eax,%eax\njs 11a6 \naddl $0x1,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1188 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11AA\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njs short loc_11A6\nadd [rbp+var_8], 1\nloc_11A6:\nadd [rbp+var_4], 1\nloc_11AA:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(int *)(4LL * i + a1) >= 0 )\n ++v3;\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11AA\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njs short loc_11A6\nadd [rbp+var_8], 1\nloc_11A6:\nadd [rbp+var_4], 1\nloc_11AA:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(int *)(4LL * i + a1) >= 0 )\n ++v3;\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(int *)(4LL * i + a1) >= 0) ++v3;\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(int *)(4LL * i + a1) >= 0) ++v3;\n }\n return v3;\n}" + }, + { + "index": 66, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int* list, int list_size) {\n int pos_count = 0;\n for (int i = 0; i < list_size; i++) {\n if (list[i] >= 0) {\n pos_count++;\n }\n }\n return pos_count;\n}", + "test": "int main() {\n\n int list1[] = {1, -2, 3, -4};\n\n int list2[] = {3, 4, 5, -1};\n\n int list3[] = {1, 2, 3, 4};\n\n\n\n assert(func0(list1, 4) == 2);\n\n assert(func0(list2, 4) == 3);\n\n assert(func0(list3, 4) == 4);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1196 \nmov %rdi,%rax\nlea -0x1(%rsi),%edx\nlea 0x4(%rdi,%rdx,4),%rcx\nmov $0x0,%edx\ncmpl $0x80000000,(%rax)\nadc $0x0,%edx\nadd $0x4,%rax\ncmp %rcx,%rax\njne 1181 \nmov %edx,%eax\nretq\nmov $0x0,%edx\njmp 1193 \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1195\nmov rax, rdi\nmovsxd rsi, esi\nlea rcx, [rdi+rsi*4]\nmov edx, 0\nloc_1180:\ncmp dword ptr [rax], 80000000h\nadc edx, 0\nadd rax, 4\ncmp rax, rcx\njnz short loc_1180\nloc_1192:\nmov eax, edx\nretn\nloc_1195:\nmov edx, 0\njmp short loc_1192", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n unsigned int v3; // edx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = 0;\n do\n v3 += *v2++ < 0x80000000;\n while ( v2 != &a1[a2] );\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_1195\nmov rax, rdi\nmovsxd rsi, esi\nlea rcx, [rdi+rsi*4]\nmov edx, 0\nloc_1180:\ncmp dword ptr [rax], 80000000h\nadc edx, 0\nadd rax, 4\ncmp rax, rcx\njnz short loc_1180\nloc_1192:\nmov eax, edx\nretn\nloc_1195:\nmov edx, 0\njmp short loc_1192", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n unsigned int v3; // edx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = 0;\n do\n v3 += *v2++ < 0x80000000;\n while ( v2 != &a1[a2] );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2) {\n uint32_t *v2;\n unsigned int v3;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = 0;\n do\n v3 += *v2++ < 2147483648;\n while (v2 != &a1[a2]);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n unsigned int v3;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = 0;\n do\n v3 += *v2++ < 2147483648;\n while (v2 != &a1[a2]);\n }\n return v3;\n}" + }, + { + "index": 67, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "unsigned long long func0(int n) {\n unsigned long long** bell = malloc((n + 1) * sizeof(unsigned long long*));\n for (int i = 0; i <= n; i++) {\n bell[i] = malloc((n + 1) * sizeof(unsigned long long));\n for (int j = 0; j <= n; j++) {\n bell[i][j] = 0;\n }\n }\n bell[0][0] = 1;\n for (int i = 1; i <= n; i++) {\n bell[i][0] = bell[i - 1][i - 1];\n for (int j = 1; j <= i; j++) {\n bell[i][j] = bell[i - 1][j - 1] + bell[i][j - 1];\n }\n }\n unsigned long long result = bell[n][0];\n for (int i = 0; i <= n; i++) {\n free(bell[i]);\n }\n free(bell);\n return result;\n}", + "test": "int main() {\n\n assert(func0(2) == 2);\n\n assert(func0(10) == 115975);\n\n return 0;\n\n} \n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x48,%rsp\nmov %edi,-0x44(%rbp)\nmov -0x44(%rbp),%eax\nadd $0x1,%eax\ncltq\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 1090 \nmov %rax,-0x20(%rbp)\nmovl $0x0,-0x34(%rbp)\njmp 122b \nmov -0x44(%rbp),%eax\nadd $0x1,%eax\ncltq\nshl $0x3,%rax\nmov -0x34(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x20(%rbp),%rdx\nlea (%rcx,%rdx,1),%rbx\nmov %rax,%rdi\ncallq 1090 \nmov %rax,(%rbx)\nmovl $0x0,-0x30(%rbp)\njmp 121f \nmov -0x34(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0x30(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x3,%rdx\nadd %rdx,%rax\nmovq $0x0,(%rax)\naddl $0x1,-0x30(%rbp)\nmov -0x30(%rbp),%eax\ncmp -0x44(%rbp),%eax\njle 11f0 \naddl $0x1,-0x34(%rbp)\nmov -0x34(%rbp),%eax\ncmp -0x44(%rbp),%eax\njle 11ba \nmov -0x20(%rbp),%rax\nmov (%rax),%rax\nmovq $0x1,(%rax)\nmovl $0x1,-0x2c(%rbp)\njmpq 1332 \nmov -0x2c(%rbp),%eax\ncltq\nshl $0x3,%rax\nlea -0x8(%rax),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0x2c(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x3,%rdx\nsub $0x8,%rdx\nadd %rax,%rdx\nmov -0x2c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x20(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%rax\nmov (%rdx),%rdx\nmov %rdx,(%rax)\nmovl $0x1,-0x28(%rbp)\njmpq 1322 \nmov -0x2c(%rbp),%eax\ncltq\nshl $0x3,%rax\nlea -0x8(%rax),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0x28(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x3,%rdx\nsub $0x8,%rdx\nadd %rdx,%rax\nmov (%rax),%rcx\nmov -0x2c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0x28(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x3,%rdx\nsub $0x8,%rdx\nadd %rdx,%rax\nmov (%rax),%rdx\nmov -0x2c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rsi\nmov -0x20(%rbp),%rax\nadd %rsi,%rax\nmov (%rax),%rax\nmov -0x28(%rbp),%esi\nmovslq %esi,%rsi\nshl $0x3,%rsi\nadd %rsi,%rax\nadd %rcx,%rdx\nmov %rdx,(%rax)\naddl $0x1,-0x28(%rbp)\nmov -0x28(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njle 129e \naddl $0x1,-0x2c(%rbp)\nmov -0x2c(%rbp),%eax\ncmp -0x44(%rbp),%eax\njle 124d \nmov -0x44(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov (%rax),%rax\nmov %rax,-0x18(%rbp)\nmovl $0x0,-0x24(%rbp)\njmp 1388 \nmov -0x24(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov %rax,%rdi\ncallq 1070 \naddl $0x1,-0x24(%rbp)\nmov -0x24(%rbp),%eax\ncmp -0x44(%rbp),%eax\njle 1365 \nmov -0x20(%rbp),%rax\nmov %rax,%rdi\ncallq 1070 \nmov -0x18(%rbp),%rax\nadd $0x48,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 48h\nmov [rbp+var_44], edi\nmov eax, [rbp+var_44]\nadd eax, 1\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov [rbp+var_34], 0\njmp short loc_122B\nloc_11BA:\nmov eax, [rbp+var_44]\nadd eax, 1\ncdqe\nshl rax, 3\nmov edx, [rbp+var_34]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+ptr]\nlea rbx, [rcx+rdx]\nmov rdi, rax; size\ncall _malloc\nmov [rbx], rax\nmov [rbp+var_30], 0\njmp short loc_121F\nloc_11F0:\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_30]\nmovsxd rdx, edx\nshl rdx, 3\nadd rax, rdx\nmov qword ptr [rax], 0\nadd [rbp+var_30], 1\nloc_121F:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_44]\njle short loc_11F0\nadd [rbp+var_34], 1\nloc_122B:\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_44]\njle short loc_11BA\nmov rax, [rbp+ptr]\nmov rax, [rax]\nmov qword ptr [rax], 1\nmov [rbp+var_2C], 1\njmp loc_1332\nloc_124D:\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 3\nlea rdx, [rax-8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_2C]\nmovsxd rdx, edx\nshl rdx, 3\nsub rdx, 8\nadd rdx, rax\nmov eax, [rbp+var_2C]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rcx\nmov rax, [rax]\nmov rdx, [rdx]\nmov [rax], rdx\nmov [rbp+var_28], 1\njmp loc_1322\nloc_129E:\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 3\nlea rdx, [rax-8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nshl rdx, 3\nsub rdx, 8\nadd rax, rdx\nmov rcx, [rax]\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nshl rdx, 3\nsub rdx, 8\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_2C]\ncdqe\nlea rsi, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rsi\nmov rax, [rax]\nmov esi, [rbp+var_28]\nmovsxd rsi, esi\nshl rsi, 3\nadd rax, rsi\nadd rdx, rcx\nmov [rax], rdx\nadd [rbp+var_28], 1\nloc_1322:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_2C]\njle loc_129E\nadd [rbp+var_2C], 1\nloc_1332:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_44]\njle loc_124D\nmov eax, [rbp+var_44]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rax, [rax]\nmov rax, [rax]\nmov [rbp+var_18], rax\nmov [rbp+var_24], 0\njmp short loc_1388\nloc_1365:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; ptr\ncall _free\nadd [rbp+var_24], 1\nloc_1388:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_44]\njle short loc_1365\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int i; // [rsp+1Ch] [rbp-34h]\n int j; // [rsp+20h] [rbp-30h]\n int k; // [rsp+24h] [rbp-2Ch]\n int m; // [rsp+28h] [rbp-28h]\n int n; // [rsp+2Ch] [rbp-24h]\n _QWORD **ptr; // [rsp+30h] [rbp-20h]\n __int64 v8; // [rsp+38h] [rbp-18h]\n\n ptr = (_QWORD **)malloc(8LL * (a1 + 1));\n for ( i = 0; i <= a1; ++i )\n {\n ptr[i] = malloc(8LL * (a1 + 1));\n for ( j = 0; j <= a1; ++j )\n ptr[i][j] = 0LL;\n }\n **ptr = 1LL;\n for ( k = 1; k <= a1; ++k )\n {\n *ptr[k] = ptr[k - 1][k - 1];\n for ( m = 1; m <= k; ++m )\n ptr[k][m] = ptr[k - 1][m - 1] + ptr[k][m - 1];\n }\n v8 = *ptr[a1];\n for ( n = 0; n <= a1; ++n )\n free(ptr[n]);\n free(ptr);\n return v8;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 48h\nmov [rbp+var_44], edi\nmov eax, [rbp+var_44]\nadd eax, 1\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov [rbp+var_34], 0\njmp short loc_122B\nloc_11BA:\nmov eax, [rbp+var_44]\nadd eax, 1\ncdqe\nshl rax, 3\nmov edx, [rbp+var_34]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+ptr]\nlea rbx, [rcx+rdx]\nmov rdi, rax; size\ncall _malloc\nmov [rbx], rax\nmov [rbp+var_30], 0\njmp short loc_121F\nloc_11F0:\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_30]\nmovsxd rdx, edx\nshl rdx, 3\nadd rax, rdx\nmov qword ptr [rax], 0\nadd [rbp+var_30], 1\nloc_121F:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_44]\njle short loc_11F0\nadd [rbp+var_34], 1\nloc_122B:\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_44]\njle short loc_11BA\nmov rax, [rbp+ptr]\nmov rax, [rax]\nmov qword ptr [rax], 1\nmov [rbp+var_2C], 1\njmp loc_1332\nloc_124D:\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 3\nlea rdx, [rax-8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_2C]\nmovsxd rdx, edx\nshl rdx, 3\nsub rdx, 8\nadd rdx, rax\nmov eax, [rbp+var_2C]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rcx\nmov rax, [rax]\nmov rdx, [rdx]\nmov [rax], rdx\nmov [rbp+var_28], 1\njmp loc_1322\nloc_129E:\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 3\nlea rdx, [rax-8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nshl rdx, 3\nsub rdx, 8\nadd rax, rdx\nmov rcx, [rax]\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nshl rdx, 3\nsub rdx, 8\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_2C]\ncdqe\nlea rsi, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rsi\nmov rax, [rax]\nmov esi, [rbp+var_28]\nmovsxd rsi, esi\nshl rsi, 3\nadd rax, rsi\nadd rdx, rcx\nmov [rax], rdx\nadd [rbp+var_28], 1\nloc_1322:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_2C]\njle loc_129E\nadd [rbp+var_2C], 1\nloc_1332:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_44]\njle loc_124D\nmov eax, [rbp+var_44]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rax, [rax]\nmov rax, [rax]\nmov [rbp+var_18], rax\nmov [rbp+var_24], 0\njmp short loc_1388\nloc_1365:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; ptr\ncall _free\nadd [rbp+var_24], 1\nloc_1388:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_44]\njle short loc_1365\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(int a1)\n{\n int i; // [rsp+1Ch] [rbp-34h]\n int j; // [rsp+20h] [rbp-30h]\n int k; // [rsp+24h] [rbp-2Ch]\n int m; // [rsp+28h] [rbp-28h]\n int n; // [rsp+2Ch] [rbp-24h]\n _QWORD **ptr; // [rsp+30h] [rbp-20h]\n __int64 v8; // [rsp+38h] [rbp-18h]\n\n ptr = (_QWORD **)malloc(8LL * (a1 + 1));\n for ( i = 0; i <= a1; ++i )\n {\n ptr[i] = malloc(8LL * (a1 + 1));\n for ( j = 0; j <= a1; ++j )\n ptr[i][j] = 0LL;\n }\n **ptr = 1LL;\n for ( k = 1; k <= a1; ++k )\n {\n *ptr[k] = ptr[k - 1][k - 1];\n for ( m = 1; m <= k; ++m )\n ptr[k][m] = ptr[k - 1][m - 1] + ptr[k][m - 1];\n }\n v8 = *ptr[a1];\n for ( n = 0; n <= a1; ++n )\n free(ptr[n]);\n free(ptr);\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(int a1) {\n int i;\n int j;\n int k;\n int m;\n int n;\n uint64_t **ptr;\n long long v8;\n ptr = (uint64_t **)malloc(8LL * (a1 + 1));\n for (i = 0; i <= a1; ++i) {\n ptr[i] = malloc(8LL * (a1 + 1));\n for (j = 0; j <= a1; ++j) ptr[i][j] = 0LL;\n }\n **ptr = 1LL;\n for (k = 1; k <= a1; ++k) {\n *ptr[k] = ptr[k - 1][k - 1];\n for (m = 1; m <= k; ++m) ptr[k][m] = ptr[k - 1][m - 1] + ptr[k][m - 1];\n }\n v8 = *ptr[a1];\n for (n = 0; n <= a1; ++n) free(ptr[n]);\n free(ptr);\n return v8;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int i;\n int j;\n int k;\n int m;\n int n;\n uint64_t **ptr;\n long long v8;\n ptr = (uint64_t **)malloc(8LL * (a1 + 1));\n for (i = 0; i <= a1; ++i) {\n ptr[i] = malloc(8LL * (a1 + 1));\n for (j = 0; j <= a1; ++j) ptr[i][j] = 0LL;\n }\n **ptr = 1LL;\n for (k = 1; k <= a1; ++k) {\n *ptr[k] = ptr[k - 1][k - 1];\n for (m = 1; m <= k; ++m) ptr[k][m] = ptr[k - 1][m - 1] + ptr[k][m - 1];\n }\n v8 = *ptr[a1];\n for (n = 0; n <= a1; ++n) free(ptr[n]);\n free(ptr);\n return v8;\n}" + }, + { + "index": 67, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "unsigned long long func0(int n) {\n unsigned long long** bell = malloc((n + 1) * sizeof(unsigned long long*));\n for (int i = 0; i <= n; i++) {\n bell[i] = malloc((n + 1) * sizeof(unsigned long long));\n for (int j = 0; j <= n; j++) {\n bell[i][j] = 0;\n }\n }\n bell[0][0] = 1;\n for (int i = 1; i <= n; i++) {\n bell[i][0] = bell[i - 1][i - 1];\n for (int j = 1; j <= i; j++) {\n bell[i][j] = bell[i - 1][j - 1] + bell[i][j - 1];\n }\n }\n unsigned long long result = bell[n][0];\n for (int i = 0; i <= n; i++) {\n free(bell[i]);\n }\n free(bell);\n return result;\n}", + "test": "int main() {\n\n assert(func0(2) == 2);\n\n assert(func0(10) == 115975);\n\n return 0;\n\n} \n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %edi,%r12d\nlea 0x1(%rdi),%r13d\nmovslq %r13d,%r13\nshl $0x3,%r13\nmov %r13,%rdi\ncallq 1090 \nmov %rax,%rbp\ntest %r12d,%r12d\njs 12b1 \nmov %rax,%rbx\nmov %r12d,%eax\nlea 0x8(,%rax,8),%r14\nlea (%r14,%rbp,1),%r15\njmp 11da \nadd $0x8,%rbx\ncmp %r15,%rbx\nje 11fd \nmov %r13,%rdi\ncallq 1090 \nmov %rax,(%rbx)\nmov %rax,%rdx\nadd %r14,%rax\nmovq $0x0,(%rdx)\nadd $0x8,%rdx\ncmp %rax,%rdx\njne 11eb \njmp 11d1 \nmov 0x0(%rbp),%rax\nmovq $0x1,(%rax)\ntest %r12d,%r12d\njle 1262 \nlea -0x1(%r12),%r9d\nadd $0x2,%r9\nmov $0x0,%r8d\nmov $0x1,%esi\njmp 1230 \nadd $0x1,%rsi\nadd $0x8,%r8\ncmp %r9,%rsi\nje 1277 \nmov 0x0(%rbp,%r8,1),%rdi\nmov 0x0(%rbp,%rsi,8),%rcx\nmov (%rdi,%r8,1),%rax\nmov %rax,(%rcx)\ntest %esi,%esi\njle 1223 \nmov $0x0,%eax\nmov (%rcx,%rax,8),%rdx\nadd (%rdi,%rax,8),%rdx\nmov %rdx,0x8(%rcx,%rax,8)\nadd $0x1,%rax\ncmp %rsi,%rax\njne 124a \njmp 1223 \nmov -0x8(%rbp,%r13,1),%rax\nmov (%rax),%r13\njne 1297 \nmov 0x0(%rbp),%rdi\ncallq 1070 \njmp 1297 \nmov -0x8(%rbp,%r13,1),%rax\nmov (%rax),%r13\nmov $0x0,%ebx\nmov 0x0(%rbp,%rbx,8),%rdi\ncallq 1070 \nadd $0x1,%rbx\ncmp %ebx,%r12d\njge 1284 \nmov %rbp,%rdi\ncallq 1070 \nmov %r13,%rax\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmov (%rax),%rax\nmovq $0x1,(%rax)\njg 120d \nmov -0x8(%rbp,%r13,1),%rax\nmov (%rax),%r13\njmp 1297 \n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r14d, edi\nlea r12d, [rdi+1]\nmovsxd r12, r12d\nshl r12, 3\nmov rdi, r12; size\ncall _malloc\nmov rbp, rax\ntest r14d, r14d\njs loc_1292\nmov rbx, rax\nlea r13d, [r14+1]\nshl r13, 3\nlea r15, [r13+rax+0]\nloc_11CD:\nmov rdi, r12; size\ncall _malloc\nmov [rbx], rax\nmov rdx, rax\nadd rax, r13\nloc_11DE:\nmov qword ptr [rdx], 0\nadd rdx, 8\ncmp rdx, rax\njnz short loc_11DE\nadd rbx, 8\ncmp rbx, r15\njnz short loc_11CD\nmov rax, [rbp+0]\nmov qword ptr [rax], 1\ntest r14d, r14d\njle short loc_1253\nlea r9d, [r14+1]\nmov r8d, 0\nmov esi, 1\nloc_1216:\nmov rdi, [rbp+r8+0]\nmov rcx, [rbp+rsi*8+0]\nmov rax, [rdi+r8]\nmov [rcx], rax\ntest esi, esi\njle short loc_12A6\nmov eax, 0\nloc_1230:\nmov rdx, [rcx+rax*8]\nadd rdx, [rdi+rax*8]\nmov [rcx+rax*8+8], rdx\nadd rax, 1\ncmp rax, rsi\njnz short loc_1230\nadd rsi, 1\nadd r8, 8\ncmp rsi, r9\njnz short loc_1216\nloc_1253:\nmov rax, [rbp+r12-8]\nmov r13, [rax]\nmov rbx, rbp\nlea eax, [r14+1]\nlea r12, [rbp+rax*8+0]\nloc_1267:\nmov rdi, [rbx]; ptr\ncall _free\nadd rbx, 8\ncmp rbx, r12\njnz short loc_1267\nloc_1278:\nmov rdi, rbp; ptr\ncall _free\nmov rax, r13\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1292:\nmov rax, [rax]\nmov qword ptr [rax], 1\nmov rax, [rbp+r12-8]\nmov r13, [rax]\njmp short loc_1278\nloc_12A6:\nadd rsi, 1\nadd r8, 8\njmp loc_1216", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n size_t v2; // r12\n void **v3; // rax\n void **v4; // rbp\n void **v5; // rbx\n __int64 v6; // r13\n void **v7; // r15\n _QWORD *v8; // rax\n _QWORD *v9; // rdx\n _QWORD *v10; // rax\n __int64 v11; // r8\n __int64 v12; // rsi\n _QWORD *v13; // rdi\n _QWORD *v14; // rcx\n __int64 v15; // rax\n __int64 v16; // r13\n void **v17; // rbx\n\n v2 = a1 + 1;\n v3 = (void **)malloc(v2 * 8);\n v4 = v3;\n if ( a1 < 0 )\n {\n *(_QWORD *)*v3 = 1LL;\n v16 = *(_QWORD *)v3[v2 - 1];\n }\n else\n {\n v5 = v3;\n v6 = (unsigned int)(a1 + 1);\n v7 = &v3[v6];\n do\n {\n v8 = malloc(v2 * 8);\n *v5 = v8;\n v9 = v8;\n v10 = &v8[v6];\n do\n *v9++ = 0LL;\n while ( v9 != v10 );\n ++v5;\n }\n while ( v5 != v7 );\n *(_QWORD *)*v4 = 1LL;\n if ( a1 > 0 )\n {\n v11 = 0LL;\n v12 = 1LL;\n do\n {\n while ( 1 )\n {\n v13 = v4[v11];\n v14 = v4[v12];\n *v14 = v13[v11];\n if ( (int)v12 > 0 )\n break;\n ++v12;\n ++v11;\n }\n v15 = 0LL;\n do\n {\n v14[v15 + 1] = v13[v15] + v14[v15];\n ++v15;\n }\n while ( v15 != v12 );\n ++v12;\n ++v11;\n }\n while ( v12 != a1 + 1 );\n }\n v16 = *(_QWORD *)v4[v2 - 1];\n v17 = v4;\n do\n free(*v17++);\n while ( v17 != &v4[a1 + 1] );\n }\n free(v4);\n return v16;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r14d, edi\nlea r12d, [rdi+1]\nmovsxd r12, r12d\nshl r12, 3\nmov rdi, r12; size\ncall _malloc\nmov rbp, rax\ntest r14d, r14d\njs loc_1292\nmov rbx, rax\nlea r13d, [r14+1]\nshl r13, 3\nlea r15, [r13+rax+0]\nloc_11CD:\nmov rdi, r12; size\ncall _malloc\nmov [rbx], rax\nmov rdx, rax\nadd rax, r13\nloc_11DE:\nmov qword ptr [rdx], 0\nadd rdx, 8\ncmp rdx, rax\njnz short loc_11DE\nadd rbx, 8\ncmp rbx, r15\njnz short loc_11CD\nmov rax, [rbp+0]\nmov qword ptr [rax], 1\ntest r14d, r14d\njle short loc_1253\nlea r9d, [r14+1]\nmov r8d, 0\nmov esi, 1\nloc_1216:\nmov rdi, [rbp+r8+0]\nmov rcx, [rbp+rsi*8+0]\nmov rax, [rdi+r8]\nmov [rcx], rax\ntest esi, esi\njle short loc_12A6\nmov eax, 0\nloc_1230:\nmov rdx, [rcx+rax*8]\nadd rdx, [rdi+rax*8]\nmov [rcx+rax*8+8], rdx\nadd rax, 1\ncmp rax, rsi\njnz short loc_1230\nadd rsi, 1\nadd r8, 8\ncmp rsi, r9\njnz short loc_1216\nloc_1253:\nmov rax, [rbp+r12-8]\nmov r13, [rax]\nmov rbx, rbp\nlea eax, [r14+1]\nlea r12, [rbp+rax*8+0]\nloc_1267:\nmov rdi, [rbx]; ptr\ncall _free\nadd rbx, 8\ncmp rbx, r12\njnz short loc_1267\nloc_1278:\nmov rdi, rbp; ptr\ncall _free\nmov rax, r13\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1292:\nmov rax, [rax]\nmov qword ptr [rax], 1\nmov rax, [rbp+r12-8]\nmov r13, [rax]\njmp short loc_1278\nloc_12A6:\nadd rsi, 1\nadd r8, 8\njmp loc_1216", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(int a1)\n{\n size_t v2; // r12\n void **v3; // rax\n void **v4; // rbp\n void **v5; // rbx\n __int64 v6; // r13\n void **v7; // r15\n _QWORD *v8; // rax\n _QWORD *v9; // rdx\n _QWORD *v10; // rax\n __int64 v11; // r8\n __int64 v12; // rsi\n _QWORD *v13; // rdi\n _QWORD *v14; // rcx\n __int64 v15; // rax\n __int64 v16; // r13\n void **v17; // rbx\n\n v2 = a1 + 1;\n v3 = (void **)malloc(v2 * 8);\n v4 = v3;\n if ( a1 < 0 )\n {\n *(_QWORD *)*v3 = 1LL;\n v16 = *(_QWORD *)v3[v2 - 1];\n }\n else\n {\n v5 = v3;\n v6 = (unsigned int)(a1 + 1);\n v7 = &v3[v6];\n do\n {\n v8 = malloc(v2 * 8);\n *v5 = v8;\n v9 = v8;\n v10 = &v8[v6];\n do\n *v9++ = 0LL;\n while ( v9 != v10 );\n ++v5;\n }\n while ( v5 != v7 );\n *(_QWORD *)*v4 = 1LL;\n if ( a1 > 0 )\n {\n v11 = 0LL;\n v12 = 1LL;\n do\n {\n while ( 1 )\n {\n v13 = v4[v11];\n v14 = v4[v12];\n *v14 = v13[v11];\n if ( (int)v12 > 0 )\n break;\n ++v12;\n ++v11;\n }\n v15 = 0LL;\n do\n {\n v14[v15 + 1] = v13[v15] + v14[v15];\n ++v15;\n }\n while ( v15 != v12 );\n ++v12;\n ++v11;\n }\n while ( v12 != a1 + 1 );\n }\n v16 = *(_QWORD *)v4[v2 - 1];\n v17 = v4;\n do\n free(*v17++);\n while ( v17 != &v4[a1 + 1] );\n }\n free(v4);\n return v16;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(int a1) {\n unsigned int v2;\n void **v3;\n void **v4;\n void **v5;\n long long v6;\n void **v7;\n uint64_t *v8;\n uint64_t *v9;\n uint64_t *v10;\n long long v11;\n long long v12;\n uint64_t *v13;\n uint64_t *v14;\n long long v15;\n long long v16;\n void **v17;\n v2 = a1 + 1;\n v3 = (void **)malloc(v2 * 8);\n v4 = v3;\n if (a1 < 0) {\n *(uint64_t *)*v3 = 1LL;\n v16 = *(uint64_t *)v3[v2 - 1];\n } else {\n v5 = v3;\n v6 = (unsigned int)(a1 + 1);\n v7 = &v3[v6];\n do {\n v8 = malloc(v2 * 8);\n *v5 = v8;\n v9 = v8;\n v10 = &v8[v6];\n do\n *v9++ = 0LL;\n while (v9 != v10);\n ++v5;\n } while (v5 != v7);\n *(uint64_t *)*v4 = 1LL;\n if (a1 > 0) {\n v11 = 0LL;\n v12 = 1LL;\n do {\n while (1) {\n v13 = v4[v11];\n v14 = v4[v12];\n *v14 = v13[v11];\n if ((int)v12 > 0) break;\n ++v12;\n ++v11;\n }\n v15 = 0LL;\n do {\n v14[v15 + 1] = v13[v15] + v14[v15];\n ++v15;\n } while (v15 != v12);\n ++v12;\n ++v11;\n } while (v12 != a1 + 1);\n }\n v16 = *(uint64_t *)v4[v2 - 1];\n v17 = v4;\n do\n free(*v17++);\n while (v17 != &v4[a1 + 1]);\n }\n free(v4);\n return v16;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v2;\n void **v3;\n void **v4;\n void **v5;\n long long v6;\n void **v7;\n uint64_t *v8;\n uint64_t *v9;\n uint64_t *v10;\n long long v11;\n long long v12;\n uint64_t *v13;\n uint64_t *v14;\n long long v15;\n long long v16;\n void **v17;\n v2 = a1 + 1;\n v3 = (void **)malloc(v2 * 8);\n v4 = v3;\n if (a1 < 0) {\n *(uint64_t *)*v3 = 1LL;\n v16 = *(uint64_t *)v3[v2 - 1];\n } else {\n v5 = v3;\n v6 = (unsigned int)(a1 + 1);\n v7 = &v3[v6];\n do {\n v8 = malloc(v2 * 8);\n *v5 = v8;\n v9 = v8;\n v10 = &v8[v6];\n do\n *v9++ = 0LL;\n while (v9 != v10);\n ++v5;\n } while (v5 != v7);\n *(uint64_t *)*v4 = 1LL;\n if (a1 > 0) {\n v11 = 0LL;\n v12 = 1LL;\n do {\n while (1) {\n v13 = v4[v11];\n v14 = v4[v12];\n *v14 = v13[v11];\n if ((int)v12 > 0) break;\n ++v12;\n ++v11;\n }\n v15 = 0LL;\n do {\n v14[v15 + 1] = v13[v15] + v14[v15];\n ++v15;\n } while (v15 != v12);\n ++v12;\n ++v11;\n } while (v12 != a1 + 1);\n }\n v16 = *(uint64_t *)v4[v2 - 1];\n v17 = v4;\n do\n free(*v17++);\n while (v17 != &v4[a1 + 1]);\n }\n free(v4);\n return v16;\n}" + }, + { + "index": 67, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "unsigned long long func0(int n) {\n unsigned long long** bell = malloc((n + 1) * sizeof(unsigned long long*));\n for (int i = 0; i <= n; i++) {\n bell[i] = malloc((n + 1) * sizeof(unsigned long long));\n for (int j = 0; j <= n; j++) {\n bell[i][j] = 0;\n }\n }\n bell[0][0] = 1;\n for (int i = 1; i <= n; i++) {\n bell[i][0] = bell[i - 1][i - 1];\n for (int j = 1; j <= i; j++) {\n bell[i][j] = bell[i - 1][j - 1] + bell[i][j - 1];\n }\n }\n unsigned long long result = bell[n][0];\n for (int i = 0; i <= n; i++) {\n free(bell[i]);\n }\n free(bell);\n return result;\n}", + "test": "int main() {\n\n assert(func0(2) == 2);\n\n assert(func0(10) == 115975);\n\n return 0;\n\n} \n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\nlea 0x1(%rdi),%r12d\npush %rbp\nmovslq %r12d,%r12\npush %rbx\nshl $0x3,%r12\nmov %edi,%ebx\nmov %r12,%rdi\nsub $0x8,%rsp\ncallq 1090 \nmov %rax,%rbp\ntest %ebx,%ebx\njs 1330 \nmov %rax,%r15\nmovslq %ebx,%rax\nlea 0x8(,%rax,8),%r13\nlea 0x0(%r13,%rbp,1),%r14\nnopl (%rax)\nmov %r12,%rdi\ncallq 1090 \nmov %rax,(%r15)\nlea (%rax,%r13,1),%rdx\nnopw 0x0(%rax,%rax,1)\nmovq $0x0,(%rax)\nadd $0x8,%rax\ncmp %rax,%rdx\njne 1260 \nadd $0x8,%r15\ncmp %r14,%r15\njne 1248 \nmov 0x0(%rbp),%r8\nmov -0x8(%rbp,%r12,1),%r10\nmovq $0x1,(%r8)\ntest %ebx,%ebx\nje 1344 \nlea -0x1(%rbx),%eax\nmov %r8,%rdi\nxor %ecx,%ecx\nmov $0x1,%edx\nlea 0x8(,%rax,8),%r9\nnopw %cs:0x0(%rax,%rax,1)\nmov 0x8(%rbp,%rcx,1),%rsi\nxor %eax,%eax\nmov %rdx,(%rsi)\njmp 12c4 \nnopl 0x0(%rax)\nadd $0x8,%rax\nadd (%rdi,%rax,1),%rdx\nmov %rdx,0x8(%rsi,%rax,1)\ncmp %rcx,%rax\njne 12c0 \nadd $0x8,%rcx\ncmp %rcx,%r9\nje 12f0 \nmov 0x0(%rbp,%rcx,1),%rdi\nmov (%rdi,%rcx,1),%rdx\njmp 12b0 \nnopw %cs:0x0(%rax,%rax,1)\nmov (%r10),%r13\nxor %r12d,%r12d\njmp 1305 \nnopl 0x0(%rax,%rax,1)\nmov 0x0(%rbp,%r12,8),%r8\nmov %r8,%rdi\nadd $0x1,%r12\ncallq 1070 \ncmp %r12d,%ebx\njge 1300 \nmov %rbp,%rdi\ncallq 1070 \nadd $0x8,%rsp\nmov %r13,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmov (%rax),%rax\nmovq $0x1,(%rax)\nmov -0x8(%rbp,%r12,1),%rax\nmov (%rax),%r13\njmp 1316 \nmov %r8,%rdi\nmov (%r10),%r13\ncallq 1070 \njmp 1316 \nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14d, edi\npush r13\npush r12\nlea r12d, [rdi+1]\npush rbp\nmovsxd r12, r12d\npush rbx\nshl r12, 3\nsub rsp, 18h\nmov [rsp+48h+var_3C], edi\nmov rdi, r12; size\ncall _malloc\nmov rbx, rax\ntest r14d, r14d\njs loc_132B\nmov r15, rax\nmovsxd rax, r14d\nmov r13, rbx\nlea r14, ds:8[rax*8]\nlea rbp, [r14+rbx]\nnop dword ptr [rax]\nloc_1270:\nmov rdi, r12; size\nadd r13, 8\ncall _malloc\nmov rdx, r14; n\nxor esi, esi; c\nmov [r13-8], rax\nmov rdi, rax; s\ncall _memset\ncmp rbp, r13\njnz short loc_1270\nmov rax, [rbx]\nmov qword ptr [rax], 1\nmov eax, [rsp+48h+var_3C]\ntest eax, eax\njz short loc_12F8\nmov r14d, eax\nmov ecx, 1\nmov edx, 1\nnop dword ptr [rax+00000000h]\nloc_12B8:\nmov rsi, [rbx+rcx*8]\nmov rdi, [rbx+rcx*8-8]\nxor eax, eax\nmov [rsi], rdx\nnop word ptr [rax+rax+00000000h]\nloc_12D0:\nadd rdx, [rdi+rax*8]\nmov [rsi+rax*8+8], rdx\nadd rax, 1\ncmp rax, rcx\njnz short loc_12D0\ncmp r14, rcx\njz short loc_12F8\nmov rdx, [rsi+rcx*8]\nadd rcx, 1\njmp short loc_12B8\nloc_12F8:\nmov rax, [rbx+r12-8]\nmov r12, [rax]\nloc_1300:\nmov rdi, [r15]; ptr\nadd r15, 8\ncall _free\ncmp rbp, r15\njnz short loc_1300\nloc_1311:\nmov rdi, rbx; ptr\ncall _free\nadd rsp, 18h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_132B:\nmov rax, [rax]\nmov qword ptr [rax], 1\nmov rax, [rbx+r12-8]\nmov r12, [rax]\njmp short loc_1311", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n size_t v1; // r12\n _QWORD **v2; // rax\n _QWORD **v3; // rbx\n void **v4; // r15\n void **v5; // r13\n size_t v6; // r14\n void **v7; // rbp\n _QWORD *v8; // rax\n __int64 v9; // rcx\n __int64 i; // rdx\n __int64 *v11; // rsi\n _QWORD *v12; // rdi\n __int64 v13; // rax\n __int64 v14; // r12\n void *v15; // rdi\n\n v1 = a1 + 1;\n v2 = (_QWORD **)malloc(v1 * 8);\n v3 = v2;\n if ( a1 < 0 )\n {\n **v2 = 1LL;\n v14 = *v2[v1 - 1];\n }\n else\n {\n v4 = (void **)v2;\n v5 = (void **)v2;\n v6 = 8LL * a1 + 8;\n v7 = (void **)((char *)v2 + v6);\n do\n {\n ++v5;\n v8 = malloc(v1 * 8);\n *(v5 - 1) = v8;\n memset(v8, 0, v6);\n }\n while ( v7 != v5 );\n **v3 = 1LL;\n if ( a1 )\n {\n v9 = 1LL;\n for ( i = 1LL; ; i = v11[v9++] )\n {\n v11 = v3[v9];\n v12 = v3[v9 - 1];\n v13 = 0LL;\n *v11 = i;\n do\n {\n i += v12[v13];\n v11[++v13] = i;\n }\n while ( v13 != v9 );\n if ( a1 == v9 )\n break;\n }\n }\n v14 = *v3[v1 - 1];\n do\n {\n v15 = *v4++;\n free(v15);\n }\n while ( v7 != v4 );\n }\n free(v3);\n return v14;\n}", + "ida_strip_asm": "sub_1220:\nendbr64\npush r15\npush r14\nmov r14d, edi\npush r13\npush r12\nlea r12d, [rdi+1]\npush rbp\nmovsxd r12, r12d\npush rbx\nshl r12, 3\nsub rsp, 18h\nmov [rsp+48h+var_3C], edi\nmov rdi, r12; size\ncall _malloc\nmov rbx, rax\ntest r14d, r14d\njs loc_132B\nmov r15, rax\nmovsxd rax, r14d\nmov r13, rbx\nlea r14, ds:8[rax*8]\nlea rbp, [r14+rbx]\nnop dword ptr [rax]\nloc_1270:\nmov rdi, r12; size\nadd r13, 8\ncall _malloc\nmov rdx, r14; n\nxor esi, esi; c\nmov [r13-8], rax\nmov rdi, rax; s\ncall _memset\ncmp rbp, r13\njnz short loc_1270\nmov rax, [rbx]\nmov qword ptr [rax], 1\nmov eax, [rsp+48h+var_3C]\ntest eax, eax\njz short loc_12F8\nmov r14d, eax\nmov ecx, 1\nmov edx, 1\nnop dword ptr [rax+00000000h]\nloc_12B8:\nmov rsi, [rbx+rcx*8]\nmov rdi, [rbx+rcx*8-8]\nxor eax, eax\nmov [rsi], rdx\nnop word ptr [rax+rax+00000000h]\nloc_12D0:\nadd rdx, [rdi+rax*8]\nmov [rsi+rax*8+8], rdx\nadd rax, 1\ncmp rax, rcx\njnz short loc_12D0\ncmp r14, rcx\njz short loc_12F8\nmov rdx, [rsi+rcx*8]\nadd rcx, 1\njmp short loc_12B8\nloc_12F8:\nmov rax, [rbx+r12-8]\nmov r12, [rax]\nloc_1300:\nmov rdi, [r15]; ptr\nadd r15, 8\ncall _free\ncmp rbp, r15\njnz short loc_1300\nloc_1311:\nmov rdi, rbx; ptr\ncall _free\nadd rsp, 18h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_132B:\nmov rax, [rax]\nmov qword ptr [rax], 1\nmov rax, [rbx+r12-8]\nmov r12, [rax]\njmp short loc_1311", + "ida_strip_pseudo": "__int64 __fastcall sub_1220(int a1)\n{\n size_t v1; // r12\n _QWORD **v2; // rax\n _QWORD **v3; // rbx\n void **v4; // r15\n void **v5; // r13\n size_t v6; // r14\n void **v7; // rbp\n _QWORD *v8; // rax\n __int64 v9; // rcx\n __int64 i; // rdx\n __int64 *v11; // rsi\n _QWORD *v12; // rdi\n __int64 v13; // rax\n __int64 v14; // r12\n void *v15; // rdi\n\n v1 = a1 + 1;\n v2 = (_QWORD **)malloc(v1 * 8);\n v3 = v2;\n if ( a1 < 0 )\n {\n **v2 = 1LL;\n v14 = *v2[v1 - 1];\n }\n else\n {\n v4 = (void **)v2;\n v5 = (void **)v2;\n v6 = 8LL * a1 + 8;\n v7 = (void **)((char *)v2 + v6);\n do\n {\n ++v5;\n v8 = malloc(v1 * 8);\n *(v5 - 1) = v8;\n memset(v8, 0, v6);\n }\n while ( v7 != v5 );\n **v3 = 1LL;\n if ( a1 )\n {\n v9 = 1LL;\n for ( i = 1LL; ; i = v11[v9++] )\n {\n v11 = v3[v9];\n v12 = v3[v9 - 1];\n v13 = 0LL;\n *v11 = i;\n do\n {\n i += v12[v13];\n v11[++v13] = i;\n }\n while ( v13 != v9 );\n if ( a1 == v9 )\n break;\n }\n }\n v14 = *v3[v1 - 1];\n do\n {\n v15 = *v4++;\n free(v15);\n }\n while ( v7 != v4 );\n }\n free(v3);\n return v14;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1220(int a1) {\n unsigned int v1;\n uint64_t **v2;\n uint64_t **v3;\n void **v4;\n void **v5;\n unsigned int v6;\n void **v7;\n uint64_t *v8;\n long long v9;\n long long i;\n long long *v11;\n uint64_t *v12;\n long long v13;\n long long v14;\n void *v15;\n v1 = a1 + 1;\n v2 = (uint64_t **)malloc(v1 * 8);\n v3 = v2;\n if (a1 < 0) {\n **v2 = 1LL;\n v14 = *v2[v1 - 1];\n } else {\n v4 = (void **)v2;\n v5 = (void **)v2;\n v6 = 8LL * a1 + 8;\n v7 = (void **)((char *)v2 + v6);\n do {\n ++v5;\n v8 = malloc(v1 * 8);\n *(v5 - 1) = v8;\n memset(v8, 0, v6);\n } while (v7 != v5);\n **v3 = 1LL;\n if (a1) {\n v9 = 1LL;\n for (i = 1LL;; i = v11[v9++]) {\n v11 = v3[v9];\n v12 = v3[v9 - 1];\n v13 = 0LL;\n *v11 = i;\n do {\n i += v12[v13];\n v11[++v13] = i;\n } while (v13 != v9);\n if (a1 == v9) break;\n }\n }\n v14 = *v3[v1 - 1];\n do {\n v15 = *v4++;\n free(v15);\n } while (v7 != v4);\n }\n free(v3);\n return v14;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v1;\n uint64_t **v2;\n uint64_t **v3;\n void **v4;\n void **v5;\n unsigned int v6;\n void **v7;\n uint64_t *v8;\n long long v9;\n long long i;\n long long *v11;\n uint64_t *v12;\n long long v13;\n long long v14;\n void *v15;\n v1 = a1 + 1;\n v2 = (uint64_t **)malloc(v1 * 8);\n v3 = v2;\n if (a1 < 0) {\n **v2 = 1LL;\n v14 = *v2[v1 - 1];\n } else {\n v4 = (void **)v2;\n v5 = (void **)v2;\n v6 = 8LL * a1 + 8;\n v7 = (void **)((char *)v2 + v6);\n do {\n ++v5;\n v8 = malloc(v1 * 8);\n *(v5 - 1) = v8;\n memset(v8, 0, v6);\n } while (v7 != v5);\n **v3 = 1LL;\n if (a1) {\n v9 = 1LL;\n for (i = 1LL;; i = v11[v9++]) {\n v11 = v3[v9];\n v12 = v3[v9 - 1];\n v13 = 0LL;\n *v11 = i;\n do {\n i += v12[v13];\n v11[++v13] = i;\n } while (v13 != v9);\n if (a1 == v9) break;\n }\n }\n v14 = *v3[v1 - 1];\n do {\n v15 = *v4++;\n free(v15);\n } while (v7 != v4);\n }\n free(v3);\n return v14;\n}" + }, + { + "index": 67, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "unsigned long long func0(int n) {\n unsigned long long** bell = malloc((n + 1) * sizeof(unsigned long long*));\n for (int i = 0; i <= n; i++) {\n bell[i] = malloc((n + 1) * sizeof(unsigned long long));\n for (int j = 0; j <= n; j++) {\n bell[i][j] = 0;\n }\n }\n bell[0][0] = 1;\n for (int i = 1; i <= n; i++) {\n bell[i][0] = bell[i - 1][i - 1];\n for (int j = 1; j <= i; j++) {\n bell[i][j] = bell[i - 1][j - 1] + bell[i][j - 1];\n }\n }\n unsigned long long result = bell[n][0];\n for (int i = 0; i <= n; i++) {\n free(bell[i]);\n }\n free(bell);\n return result;\n}", + "test": "int main() {\n\n assert(func0(2) == 2);\n\n assert(func0(10) == 115975);\n\n return 0;\n\n} \n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nlea 0x1(%rdi),%eax\npush %r14\npush %r13\npush %r12\nmovslq %eax,%r12\npush %rbp\nshl $0x3,%r12\npush %rbx\nmov %edi,%ebx\nmov %r12,%rdi\nsub $0x18,%rsp\nmov %eax,0x4(%rsp)\ncallq 1090 \nmov %rax,%r15\ntest %ebx,%ebx\njs 1357 \nmov %rax,%r14\nmovslq %ebx,%rax\nlea 0x8(%r15,%rax,8),%rax\nmov %rax,0x8(%rsp)\nmov 0x4(%rsp),%eax\nmov %eax,%r13d\nand $0xfffffffe,%eax\nshr %r13d\nmov %eax,%ebp\nshl $0x4,%r13\nnopl 0x0(%rax,%rax,1)\nmov %r12,%rdi\ncallq 1090 \nmov %rax,(%r14)\ntest %ebx,%ebx\nje 1350 \nmov %rax,%rdx\nlea 0x0(%r13,%rax,1),%rsi\npxor %xmm0,%xmm0\nmovups %xmm0,(%rdx)\nadd $0x10,%rdx\ncmp %rsi,%rdx\njne 1280 \nmovslq %ebp,%rdx\ncmp 0x4(%rsp),%ebp\nje 129d \nmovq $0x0,(%rax,%rdx,8)\nadd $0x8,%r14\ncmp %r14,0x8(%rsp)\njne 1260 \nmov (%r15),%rdi\nmov -0x8(%r15,%r12,1),%r10\nmovq $0x1,(%rdi)\ntest %ebx,%ebx\nje 136b \nlea -0x1(%rbx),%r9d\nmov $0x1,%ecx\nmov $0x1,%edx\nadd $0x1,%r9\nnopl 0x0(%rax)\nmov (%r15,%rcx,8),%rsi\nmov -0x8(%r15,%rcx,8),%rdi\nxor %eax,%eax\nmov %rdx,(%rsi)\nnopw %cs:0x0(%rax,%rax,1)\nadd (%rdi,%rax,8),%rdx\nmov %rdx,0x8(%rsi,%rax,8)\nadd $0x1,%rax\ncmp %rax,%rcx\njne 12f0 \ncmp %rcx,%r9\nje 1318 \nmov (%rsi,%rcx,8),%rdx\nadd $0x1,%rcx\njmp 12d8 \nnopl 0x0(%rax)\nmov (%r10),%r12\nxor %ebp,%ebp\nnopl (%rax)\nmov (%r15,%rbp,8),%rdi\nadd $0x1,%rbp\ncallq 1070 \ncmp %ebp,%ebx\njge 1320 \nmov %r15,%rdi\ncallq 1070 \nadd $0x18,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax,%rax,1)\nxor %edx,%edx\njmpq 1295 \nmov (%rax),%rax\nmovq $0x1,(%rax)\nmov -0x8(%r15,%r12,1),%rax\nmov (%rax),%r12\njmp 1331 \nmov (%r10),%r12\ncallq 1070 \njmp 1331 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14d, edi\npush r13\npush r12\nlea r12d, [rdi+1]\npush rbp\nmovsxd r12, r12d\npush rbx\nshl r12, 3\nsub rsp, 18h\nmov [rsp+48h+var_3C], edi\nmov rdi, r12; size\ncall _malloc\nmov rbx, rax\ntest r14d, r14d\njs loc_132B\nmov r15, rax\nmovsxd rax, r14d\nmov r13, rbx\nlea r14, ds:8[rax*8]\nlea rbp, [r14+rbx]\nnop dword ptr [rax]\nloc_1270:\nmov rdi, r12; size\nadd r13, 8\ncall _malloc\nmov rdx, r14; n\nxor esi, esi; c\nmov [r13-8], rax\nmov rdi, rax; s\ncall _memset\ncmp rbp, r13\njnz short loc_1270\nmov rax, [rbx]\nmov qword ptr [rax], 1\nmov eax, [rsp+48h+var_3C]\ntest eax, eax\njz short loc_12F8\nmov r14d, eax\nmov ecx, 1\nmov edx, 1\nnop dword ptr [rax+00000000h]\nloc_12B8:\nmov rsi, [rbx+rcx*8]\nmov rdi, [rbx+rcx*8-8]\nxor eax, eax\nmov [rsi], rdx\nnop word ptr [rax+rax+00000000h]\nloc_12D0:\nadd rdx, [rdi+rax*8]\nmov [rsi+rax*8+8], rdx\nadd rax, 1\ncmp rax, rcx\njnz short loc_12D0\ncmp r14, rcx\njz short loc_12F8\nmov rdx, [rsi+rcx*8]\nadd rcx, 1\njmp short loc_12B8\nloc_12F8:\nmov rax, [rbx+r12-8]\nmov r12, [rax]\nloc_1300:\nmov rdi, [r15]; ptr\nadd r15, 8\ncall _free\ncmp rbp, r15\njnz short loc_1300\nloc_1311:\nmov rdi, rbx; ptr\ncall _free\nadd rsp, 18h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_132B:\nmov rax, [rax]\nmov qword ptr [rax], 1\nmov rax, [rbx+r12-8]\nmov r12, [rax]\njmp short loc_1311", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n size_t v1; // r12\n _QWORD **v2; // rax\n _QWORD **v3; // rbx\n void **v4; // r15\n void **v5; // r13\n size_t v6; // r14\n void **v7; // rbp\n _QWORD *v8; // rax\n __int64 v9; // rcx\n __int64 i; // rdx\n __int64 *v11; // rsi\n _QWORD *v12; // rdi\n __int64 v13; // rax\n __int64 v14; // r12\n void *v15; // rdi\n\n v1 = a1 + 1;\n v2 = (_QWORD **)malloc(v1 * 8);\n v3 = v2;\n if ( a1 < 0 )\n {\n **v2 = 1LL;\n v14 = *v2[v1 - 1];\n }\n else\n {\n v4 = (void **)v2;\n v5 = (void **)v2;\n v6 = 8LL * a1 + 8;\n v7 = (void **)((char *)v2 + v6);\n do\n {\n ++v5;\n v8 = malloc(v1 * 8);\n *(v5 - 1) = v8;\n memset(v8, 0, v6);\n }\n while ( v7 != v5 );\n **v3 = 1LL;\n if ( a1 )\n {\n v9 = 1LL;\n for ( i = 1LL; ; i = v11[v9++] )\n {\n v11 = v3[v9];\n v12 = v3[v9 - 1];\n v13 = 0LL;\n *v11 = i;\n do\n {\n i += v12[v13];\n v11[++v13] = i;\n }\n while ( v13 != v9 );\n if ( a1 == v9 )\n break;\n }\n }\n v14 = *v3[v1 - 1];\n do\n {\n v15 = *v4++;\n free(v15);\n }\n while ( v7 != v4 );\n }\n free(v3);\n return v14;\n}", + "ida_strip_asm": "sub_1220:\nendbr64\npush r15\npush r14\nmov r14d, edi\npush r13\npush r12\nlea r12d, [rdi+1]\npush rbp\nmovsxd r12, r12d\npush rbx\nshl r12, 3\nsub rsp, 18h\nmov [rsp+48h+var_3C], edi\nmov rdi, r12; size\ncall _malloc\nmov rbx, rax\ntest r14d, r14d\njs loc_132B\nmov r15, rax\nmovsxd rax, r14d\nmov r13, rbx\nlea r14, ds:8[rax*8]\nlea rbp, [r14+rbx]\nnop dword ptr [rax]\nloc_1270:\nmov rdi, r12; size\nadd r13, 8\ncall _malloc\nmov rdx, r14; n\nxor esi, esi; c\nmov [r13-8], rax\nmov rdi, rax; s\ncall _memset\ncmp rbp, r13\njnz short loc_1270\nmov rax, [rbx]\nmov qword ptr [rax], 1\nmov eax, [rsp+48h+var_3C]\ntest eax, eax\njz short loc_12F8\nmov r14d, eax\nmov ecx, 1\nmov edx, 1\nnop dword ptr [rax+00000000h]\nloc_12B8:\nmov rsi, [rbx+rcx*8]\nmov rdi, [rbx+rcx*8-8]\nxor eax, eax\nmov [rsi], rdx\nnop word ptr [rax+rax+00000000h]\nloc_12D0:\nadd rdx, [rdi+rax*8]\nmov [rsi+rax*8+8], rdx\nadd rax, 1\ncmp rax, rcx\njnz short loc_12D0\ncmp r14, rcx\njz short loc_12F8\nmov rdx, [rsi+rcx*8]\nadd rcx, 1\njmp short loc_12B8\nloc_12F8:\nmov rax, [rbx+r12-8]\nmov r12, [rax]\nloc_1300:\nmov rdi, [r15]; ptr\nadd r15, 8\ncall _free\ncmp rbp, r15\njnz short loc_1300\nloc_1311:\nmov rdi, rbx; ptr\ncall _free\nadd rsp, 18h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_132B:\nmov rax, [rax]\nmov qword ptr [rax], 1\nmov rax, [rbx+r12-8]\nmov r12, [rax]\njmp short loc_1311", + "ida_strip_pseudo": "__int64 __fastcall sub_1220(int a1)\n{\n size_t v1; // r12\n _QWORD **v2; // rax\n _QWORD **v3; // rbx\n void **v4; // r15\n void **v5; // r13\n size_t v6; // r14\n void **v7; // rbp\n _QWORD *v8; // rax\n __int64 v9; // rcx\n __int64 i; // rdx\n __int64 *v11; // rsi\n _QWORD *v12; // rdi\n __int64 v13; // rax\n __int64 v14; // r12\n void *v15; // rdi\n\n v1 = a1 + 1;\n v2 = (_QWORD **)malloc(v1 * 8);\n v3 = v2;\n if ( a1 < 0 )\n {\n **v2 = 1LL;\n v14 = *v2[v1 - 1];\n }\n else\n {\n v4 = (void **)v2;\n v5 = (void **)v2;\n v6 = 8LL * a1 + 8;\n v7 = (void **)((char *)v2 + v6);\n do\n {\n ++v5;\n v8 = malloc(v1 * 8);\n *(v5 - 1) = v8;\n memset(v8, 0, v6);\n }\n while ( v7 != v5 );\n **v3 = 1LL;\n if ( a1 )\n {\n v9 = 1LL;\n for ( i = 1LL; ; i = v11[v9++] )\n {\n v11 = v3[v9];\n v12 = v3[v9 - 1];\n v13 = 0LL;\n *v11 = i;\n do\n {\n i += v12[v13];\n v11[++v13] = i;\n }\n while ( v13 != v9 );\n if ( a1 == v9 )\n break;\n }\n }\n v14 = *v3[v1 - 1];\n do\n {\n v15 = *v4++;\n free(v15);\n }\n while ( v7 != v4 );\n }\n free(v3);\n return v14;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1220(int a1) {\n unsigned int v1;\n uint64_t **v2;\n uint64_t **v3;\n void **v4;\n void **v5;\n unsigned int v6;\n void **v7;\n uint64_t *v8;\n long long v9;\n long long i;\n long long *v11;\n uint64_t *v12;\n long long v13;\n long long v14;\n void *v15;\n v1 = a1 + 1;\n v2 = (uint64_t **)malloc(v1 * 8);\n v3 = v2;\n if (a1 < 0) {\n **v2 = 1LL;\n v14 = *v2[v1 - 1];\n } else {\n v4 = (void **)v2;\n v5 = (void **)v2;\n v6 = 8LL * a1 + 8;\n v7 = (void **)((char *)v2 + v6);\n do {\n ++v5;\n v8 = malloc(v1 * 8);\n *(v5 - 1) = v8;\n memset(v8, 0, v6);\n } while (v7 != v5);\n **v3 = 1LL;\n if (a1) {\n v9 = 1LL;\n for (i = 1LL;; i = v11[v9++]) {\n v11 = v3[v9];\n v12 = v3[v9 - 1];\n v13 = 0LL;\n *v11 = i;\n do {\n i += v12[v13];\n v11[++v13] = i;\n } while (v13 != v9);\n if (a1 == v9) break;\n }\n }\n v14 = *v3[v1 - 1];\n do {\n v15 = *v4++;\n free(v15);\n } while (v7 != v4);\n }\n free(v3);\n return v14;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v1;\n uint64_t **v2;\n uint64_t **v3;\n void **v4;\n void **v5;\n unsigned int v6;\n void **v7;\n uint64_t *v8;\n long long v9;\n long long i;\n long long *v11;\n uint64_t *v12;\n long long v13;\n long long v14;\n void *v15;\n v1 = a1 + 1;\n v2 = (uint64_t **)malloc(v1 * 8);\n v3 = v2;\n if (a1 < 0) {\n **v2 = 1LL;\n v14 = *v2[v1 - 1];\n } else {\n v4 = (void **)v2;\n v5 = (void **)v2;\n v6 = 8LL * a1 + 8;\n v7 = (void **)((char *)v2 + v6);\n do {\n ++v5;\n v8 = malloc(v1 * 8);\n *(v5 - 1) = v8;\n memset(v8, 0, v6);\n } while (v7 != v5);\n **v3 = 1LL;\n if (a1) {\n v9 = 1LL;\n for (i = 1LL;; i = v11[v9++]) {\n v11 = v3[v9];\n v12 = v3[v9 - 1];\n v13 = 0LL;\n *v11 = i;\n do {\n i += v12[v13];\n v11[++v13] = i;\n } while (v13 != v9);\n if (a1 == v9) break;\n }\n }\n v14 = *v3[v1 - 1];\n do {\n v15 = *v4++;\n free(v15);\n } while (v7 != v4);\n }\n free(v3);\n return v14;\n}" + }, + { + "index": 68, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int A[], int n) {\n bool increasing = true;\n bool decreasing = true;\n for (int i = 0; i < n - 1; i++) {\n if (A[i] > A[i + 1]) {\n increasing = false;\n }\n if (A[i] < A[i + 1]) {\n decreasing = false;\n }\n }\n return increasing || decreasing;\n}", + "test": "int main() {\n\n int array1[] = {6, 5, 4, 4};\n\n int array2[] = {1, 2, 2, 3};\n\n int array3[] = {1, 3, 2};\n\n\n\n assert(func0(array1, 4) == true);\n\n assert(func0(array2, 4) == true);\n\n assert(func0(array3, 3) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovb $0x1,-0x6(%rbp)\nmovb $0x1,-0x5(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11fd \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njle 11c1 \nmovb $0x0,-0x6(%rbp)\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njge 11f9 \nmovb $0x0,-0x5(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x1c(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x4(%rbp)\njl 1189 \ncmpb $0x0,-0x6(%rbp)\njne 1214 \ncmpb $0x0,-0x5(%rbp)\nje 121b \nmov $0x1,%eax\njmp 1220 \nmov $0x0,%eax\nand $0x1,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_6], 1\nmov [rbp+var_5], 1\nmov [rbp+var_4], 0\njmp short loc_11FD\nloc_1189:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_11C1\nmov [rbp+var_6], 0\nloc_11C1:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njge short loc_11F9\nmov [rbp+var_5], 0\nloc_11F9:\nadd [rbp+var_4], 1\nloc_11FD:\nmov eax, [rbp+var_1C]\nsub eax, 1\ncmp [rbp+var_4], eax\njl short loc_1189\ncmp [rbp+var_6], 0\njnz short loc_1214\ncmp [rbp+var_5], 0\njz short loc_121B\nloc_1214:\nmov eax, 1\njmp short loc_1220\nloc_121B:\nmov eax, 0\nloc_1220:\nand eax, 1\npop rbp\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(__int64 a1, int a2)\n{\n char v4; // [rsp+16h] [rbp-6h]\n char v5; // [rsp+17h] [rbp-5h]\n int i; // [rsp+18h] [rbp-4h]\n\n v4 = 1;\n v5 = 1;\n for ( i = 0; i < a2 - 1; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) > *(_DWORD *)(4 * (i + 1LL) + a1) )\n v4 = 0;\n if ( *(_DWORD *)(4LL * i + a1) < *(_DWORD *)(4 * (i + 1LL) + a1) )\n v5 = 0;\n }\n return v4 || v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_6], 1\nmov [rbp+var_5], 1\nmov [rbp+var_4], 0\njmp short loc_11FD\nloc_1189:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_11C1\nmov [rbp+var_6], 0\nloc_11C1:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njge short loc_11F9\nmov [rbp+var_5], 0\nloc_11F9:\nadd [rbp+var_4], 1\nloc_11FD:\nmov eax, [rbp+var_1C]\nsub eax, 1\ncmp [rbp+var_4], eax\njl short loc_1189\ncmp [rbp+var_6], 0\njnz short loc_1214\ncmp [rbp+var_5], 0\njz short loc_121B\nloc_1214:\nmov eax, 1\njmp short loc_1220\nloc_121B:\nmov eax, 0\nloc_1220:\nand eax, 1\npop rbp\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1169(__int64 a1, int a2)\n{\n char v4; // [rsp+16h] [rbp-6h]\n char v5; // [rsp+17h] [rbp-5h]\n int i; // [rsp+18h] [rbp-4h]\n\n v4 = 1;\n v5 = 1;\n for ( i = 0; i < a2 - 1; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) > *(_DWORD *)(4 * (i + 1LL) + a1) )\n v4 = 0;\n if ( *(_DWORD *)(4LL * i + a1) < *(_DWORD *)(4 * (i + 1LL) + a1) )\n v5 = 0;\n }\n return v4 || v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1169(long long a1, int a2) {\n char v4;\n char v5;\n int i;\n v4 = 1;\n v5 = 1;\n for (i = 0; i < a2 - 1; ++i) {\n if (*(uint32_t *)(4LL * i + a1) > *(uint32_t *)(4 * (i + 1LL) + a1)) v4 = 0;\n if (*(uint32_t *)(4LL * i + a1) < *(uint32_t *)(4 * (i + 1LL) + a1)) v5 = 0;\n }\n return v4 || v5;\n}", + "ida_pseudo_norm": "uint8_t func0(long long a1, int a2) {\n char v4;\n char v5;\n int i;\n v4 = 1;\n v5 = 1;\n for (i = 0; i < a2 - 1; ++i) {\n if (*(uint32_t *)(4LL * i + a1) > *(uint32_t *)(4 * (i + 1LL) + a1)) v4 = 0;\n if (*(uint32_t *)(4LL * i + a1) < *(uint32_t *)(4 * (i + 1LL) + a1)) v5 = 0;\n }\n return v4 || v5;\n}" + }, + { + "index": 68, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int A[], int n) {\n bool increasing = true;\n bool decreasing = true;\n for (int i = 0; i < n - 1; i++) {\n if (A[i] > A[i + 1]) {\n increasing = false;\n }\n if (A[i] < A[i + 1]) {\n decreasing = false;\n }\n }\n return increasing || decreasing;\n}", + "test": "int main() {\n\n int array1[] = {6, 5, 4, 4};\n\n int array2[] = {1, 2, 2, 3};\n\n int array3[] = {1, 3, 2};\n\n\n\n assert(func0(array1, 4) == true);\n\n assert(func0(array2, 4) == true);\n\n assert(func0(array3, 3) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%esi\njle 11a9 \nmov %rdi,%rdx\nlea -0x2(%rsi),%eax\nlea 0x4(%rdi,%rax,4),%r8\nmov $0x1,%eax\nmov $0x1,%r9d\nmov $0x0,%edi\njmp 119b \nmov %edi,%r9d\nadd $0x4,%rdx\ncmp %r8,%rdx\nje 11b4 \nmov (%rdx),%esi\nmov 0x4(%rdx),%ecx\ncmp %ecx,%esi\njg 118f \ncmovl %edi,%eax\njmp 1192 \nmov $0x1,%eax\nmov $0x1,%r9d\nor %r9d,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ncmp esi, 1\njle short loc_11AA\nmov rdx, rdi\nlea eax, [rsi-2]\nlea r9, [rdi+rax*4+4]\nmov edi, 1\nmov eax, 1\nmov r8d, 0\njmp short loc_119B\nloc_118F:\nmov eax, r8d\nloc_1192:\nadd rdx, 4\ncmp rdx, r9\njz short loc_11B4\nloc_119B:\nmov esi, [rdx]\nmov ecx, [rdx+4]\ncmp esi, ecx\njg short loc_118F\ncmovl edi, r8d\njmp short loc_1192\nloc_11AA:\nmov edi, 1\nmov eax, 1\nloc_11B4:\nor eax, edi\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rdx\n __int64 v3; // r9\n int v4; // edi\n int v5; // eax\n int v6; // ecx\n\n if ( a2 <= 1 )\n {\n v4 = 1;\n v5 = 1;\n }\n else\n {\n v2 = a1;\n v3 = (__int64)&a1[a2 - 2 + 1];\n v4 = 1;\n v5 = 1;\n do\n {\n v6 = v2[1];\n if ( *v2 > v6 )\n {\n v5 = 0;\n }\n else if ( *v2 < v6 )\n {\n v4 = 0;\n }\n ++v2;\n }\n while ( v2 != (_DWORD *)v3 );\n }\n return v4 | (unsigned int)v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ncmp esi, 1\njle short loc_11AA\nmov rdx, rdi\nlea eax, [rsi-2]\nlea r9, [rdi+rax*4+4]\nmov edi, 1\nmov eax, 1\nmov r8d, 0\njmp short loc_119B\nloc_118F:\nmov eax, r8d\nloc_1192:\nadd rdx, 4\ncmp rdx, r9\njz short loc_11B4\nloc_119B:\nmov esi, [rdx]\nmov ecx, [rdx+4]\ncmp esi, ecx\njg short loc_118F\ncmovl edi, r8d\njmp short loc_1192\nloc_11AA:\nmov edi, 1\nmov eax, 1\nloc_11B4:\nor eax, edi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rdx\n __int64 v3; // r9\n int v4; // edi\n int v5; // eax\n int v6; // ecx\n\n if ( a2 <= 1 )\n {\n v4 = 1;\n v5 = 1;\n }\n else\n {\n v2 = a1;\n v3 = (__int64)&a1[a2 - 2 + 1];\n v4 = 1;\n v5 = 1;\n do\n {\n v6 = v2[1];\n if ( *v2 > v6 )\n {\n v5 = 0;\n }\n else if ( *v2 < v6 )\n {\n v4 = 0;\n }\n ++v2;\n }\n while ( v2 != (_DWORD *)v3 );\n }\n return v4 | (unsigned int)v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2) {\n uint32_t *v2;\n long long v3;\n int v4;\n int v5;\n int v6;\n if (a2 <= 1) {\n v4 = 1;\n v5 = 1;\n } else {\n v2 = a1;\n v3 = (long long)&a1[a2 - 2 + 1];\n v4 = 1;\n v5 = 1;\n do {\n v6 = v2[1];\n if (*v2 > v6) {\n v5 = 0;\n } else if (*v2 < v6) {\n v4 = 0;\n }\n ++v2;\n } while (v2 != (uint32_t *)v3);\n }\n return v4 | (unsigned int)v5;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n long long v3;\n int v4;\n int v5;\n int v6;\n if (a2 <= 1) {\n v4 = 1;\n v5 = 1;\n } else {\n v2 = a1;\n v3 = (long long)&a1[a2 - 2 + 1];\n v4 = 1;\n v5 = 1;\n do {\n v6 = v2[1];\n if (*v2 > v6) {\n v5 = 0;\n } else if (*v2 < v6) {\n v4 = 0;\n }\n ++v2;\n } while (v2 != (uint32_t *)v3);\n }\n return v4 | (unsigned int)v5;\n}" + }, + { + "index": 68, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int A[], int n) {\n bool increasing = true;\n bool decreasing = true;\n for (int i = 0; i < n - 1; i++) {\n if (A[i] > A[i + 1]) {\n increasing = false;\n }\n if (A[i] < A[i + 1]) {\n decreasing = false;\n }\n }\n return increasing || decreasing;\n}", + "test": "int main() {\n\n int array1[] = {6, 5, 4, 4};\n\n int array2[] = {1, 2, 2, 3};\n\n int array3[] = {1, 3, 2};\n\n\n\n assert(func0(array1, 4) == true);\n\n assert(func0(array2, 4) == true);\n\n assert(func0(array3, 3) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%esi\njle 1188 \nlea -0x2(%rsi),%eax\nmov $0x1,%ecx\nxor %esi,%esi\nlea 0x4(%rdi,%rax,4),%rdx\nmov $0x1,%eax\njmp 116c \ncmovl %esi,%eax\nadd $0x4,%rdi\ncmp %rdx,%rdi\nje 1180 \nmov 0x4(%rdi),%r8d\ncmp %r8d,(%rdi)\njle 1160 \nadd $0x4,%rdi\nxor %ecx,%ecx\ncmp %rdx,%rdi\njne 116c \nor %ecx,%eax\nretq\nnopl 0x0(%rax,%rax,1)\nmov $0x1,%eax\nretq\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\ncmp esi, 1\njle short loc_12C8\nlea eax, [rsi-2]\nmov ecx, [rdi]\nlea rdx, [rdi+4]\nmov r8d, 1\nlea rdi, [rdi+rax*4+8]\nxor r9d, r9d\nmov eax, 1\njmp short loc_12AD\nloc_12A0:\ncmovl eax, r9d\nadd rdx, 4\ncmp rdi, rdx\njz short loc_12C1\nloc_12AD:\nmov esi, ecx\nmov ecx, [rdx]\ncmp esi, ecx\njle short loc_12A0\nadd rdx, 4\nxor r8d, r8d\ncmp rdi, rdx\njnz short loc_12AD\nloc_12C1:\nor eax, r8d\nretn\nloc_12C8:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int v2; // ecx\n int *v3; // rdx\n int v4; // r8d\n __int64 v5; // rdi\n int v6; // eax\n int v7; // esi\n\n if ( a2 <= 1 )\n return 1LL;\n v2 = *a1;\n v3 = a1 + 1;\n v4 = 1;\n v5 = (__int64)&a1[a2 - 2 + 2];\n v6 = 1;\n do\n {\n while ( 1 )\n {\n v7 = v2;\n v2 = *v3;\n if ( v7 <= *v3 )\n break;\n ++v3;\n v4 = 0;\n if ( (int *)v5 == v3 )\n return v4 | (unsigned int)v6;\n }\n if ( v7 < v2 )\n v6 = 0;\n ++v3;\n }\n while ( (int *)v5 != v3 );\n return v4 | (unsigned int)v6;\n}", + "ida_strip_asm": "sub_1270:\nendbr64\ncmp esi, 1\njle short loc_12C8\nlea eax, [rsi-2]\nmov ecx, [rdi]\nlea rdx, [rdi+4]\nmov r8d, 1\nlea rdi, [rdi+rax*4+8]\nxor r9d, r9d\nmov eax, 1\njmp short loc_12AD\nloc_12A0:\ncmovl eax, r9d\nadd rdx, 4\ncmp rdi, rdx\njz short loc_12C1\nloc_12AD:\nmov esi, ecx\nmov ecx, [rdx]\ncmp esi, ecx\njle short loc_12A0\nadd rdx, 4\nxor r8d, r8d\ncmp rdi, rdx\njnz short loc_12AD\nloc_12C1:\nor eax, r8d\nretn\nloc_12C8:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1270(int *a1, int a2)\n{\n int v2; // ecx\n int *v3; // rdx\n int v4; // r8d\n __int64 v5; // rdi\n int v6; // eax\n int v7; // esi\n\n if ( a2 <= 1 )\n return 1LL;\n v2 = *a1;\n v3 = a1 + 1;\n v4 = 1;\n v5 = (__int64)&a1[a2 - 2 + 2];\n v6 = 1;\n do\n {\n while ( 1 )\n {\n v7 = v2;\n v2 = *v3;\n if ( v7 <= *v3 )\n break;\n ++v3;\n v4 = 0;\n if ( (int *)v5 == v3 )\n return v4 | (unsigned int)v6;\n }\n if ( v7 < v2 )\n v6 = 0;\n ++v3;\n }\n while ( (int *)v5 != v3 );\n return v4 | (unsigned int)v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1270(int *a1, int a2) {\n int v2;\n int *v3;\n int v4;\n long long v5;\n int v6;\n int v7;\n if (a2 <= 1) return 1LL;\n v2 = *a1;\n v3 = a1 + 1;\n v4 = 1;\n v5 = (long long)&a1[a2 - 2 + 2];\n v6 = 1;\n do {\n while (1) {\n v7 = v2;\n v2 = *v3;\n if (v7 <= *v3) break;\n ++v3;\n v4 = 0;\n if ((int *)v5 == v3) return v4 | (unsigned int)v6;\n }\n if (v7 < v2) v6 = 0;\n ++v3;\n } while ((int *)v5 != v3);\n return v4 | (unsigned int)v6;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int v2;\n int *v3;\n int v4;\n long long v5;\n int v6;\n int v7;\n if (a2 <= 1) return 1LL;\n v2 = *a1;\n v3 = a1 + 1;\n v4 = 1;\n v5 = (long long)&a1[a2 - 2 + 2];\n v6 = 1;\n do {\n while (1) {\n v7 = v2;\n v2 = *v3;\n if (v7 <= *v3) break;\n ++v3;\n v4 = 0;\n if ((int *)v5 == v3) return v4 | (unsigned int)v6;\n }\n if (v7 < v2) v6 = 0;\n ++v3;\n } while ((int *)v5 != v3);\n return v4 | (unsigned int)v6;\n}" + }, + { + "index": 69, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int l[], int s[], int len_l, int len_s) {\n bool sub_set = false;\n if (len_s == 0) {\n sub_set = true;\n } else if (len_s == len_l) {\n bool same = true;\n for (int i = 0; i < len_l; i++) {\n if (l[i] != s[i]) {\n same = false;\n break;\n }\n }\n sub_set = same;\n } else if (len_s > len_l) {\n sub_set = false;\n } else {\n for (int i = 0; i <= len_l - len_s; i++) {\n if (l[i] == s[0]) {\n int n = 1;\n while (n < len_s && l[i + n] == s[n]) {\n n++;\n }\n if (n == len_s) {\n sub_set = true;\n break;\n }\n }\n }\n }\n return sub_set;\n}", + "test": "int main() {\n\n int l[] = {2, 4, 3, 5, 7};\n\n int s1[] = {3, 7};\n\n int s2[] = {4, 3};\n\n int s3[] = {1, 6};\n\n\n\n assert(func0(l, s1, 5, 2) == false);\n\n assert(func0(l, s2, 5, 2) == true);\n\n assert(func0(l, s3, 5, 2) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %edx,-0x24(%rbp)\nmov %ecx,-0x28(%rbp)\nmovb $0x0,-0xe(%rbp)\ncmpl $0x0,-0x28(%rbp)\njne 1192 \nmovb $0x1,-0xe(%rbp)\njmpq 129a \nmov -0x28(%rbp),%eax\ncmp -0x24(%rbp),%eax\njne 11f5 \nmovb $0x1,-0xd(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 11e1 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x20(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\nje 11dd \nmovb $0x0,-0xd(%rbp)\njmp 11e9 \naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x24(%rbp),%eax\njl 11a7 \nmovzbl -0xd(%rbp),%eax\nmov %al,-0xe(%rbp)\njmpq 129a \nmov -0x28(%rbp),%eax\ncmp -0x24(%rbp),%eax\njle 1206 \nmovb $0x0,-0xe(%rbp)\njmpq 129a \nmovl $0x0,-0x8(%rbp)\njmp 128b \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x20(%rbp),%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 1287 \nmovl $0x1,-0x4(%rbp)\njmp 123c \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x28(%rbp),%eax\njge 1279 \nmov -0x8(%rbp),%edx\nmov -0x4(%rbp),%eax\nadd %edx,%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x20(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\nje 1238 \nmov -0x4(%rbp),%eax\ncmp -0x28(%rbp),%eax\njne 1287 \nmovb $0x1,-0xe(%rbp)\njmp 129a \naddl $0x1,-0x8(%rbp)\nmov -0x24(%rbp),%eax\nsub -0x28(%rbp),%eax\ncmp %eax,-0x8(%rbp)\njle 120f \nmovzbl -0xe(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_28], ecx\nmov [rbp+var_E], 0\ncmp [rbp+var_28], 0\njnz short loc_1192\nmov [rbp+var_E], 1\njmp loc_129A\nloc_1192:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_24]\njnz short loc_11F5\nmov [rbp+var_D], 1\nmov [rbp+var_C], 0\njmp short loc_11E1\nloc_11A7:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_11DD\nmov [rbp+var_D], 0\njmp short loc_11E9\nloc_11DD:\nadd [rbp+var_C], 1\nloc_11E1:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_24]\njl short loc_11A7\nloc_11E9:\nmovzx eax, [rbp+var_D]\nmov [rbp+var_E], al\njmp loc_129A\nloc_11F5:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_24]\njle short loc_1206\nmov [rbp+var_E], 0\njmp loc_129A\nloc_1206:\nmov [rbp+var_8], 0\njmp short loc_128B\nloc_120F:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_20]\nmov eax, [rax]\ncmp edx, eax\njnz short loc_1287\nmov [rbp+var_4], 1\njmp short loc_123C\nloc_1238:\nadd [rbp+var_4], 1\nloc_123C:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_28]\njge short loc_1279\nmov edx, [rbp+var_8]\nmov eax, [rbp+var_4]\nadd eax, edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_1238\nloc_1279:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_28]\njnz short loc_1287\nmov [rbp+var_E], 1\njmp short loc_129A\nloc_1287:\nadd [rbp+var_8], 1\nloc_128B:\nmov eax, [rbp+var_24]\nsub eax, [rbp+var_28]\ncmp [rbp+var_8], eax\njle loc_120F\nloc_129A:\nmovzx eax, [rbp+var_E]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, _DWORD *a2, int a3, int a4)\n{\n unsigned __int8 v5; // [rsp+1Ah] [rbp-Eh]\n unsigned __int8 v6; // [rsp+1Bh] [rbp-Dh]\n int i; // [rsp+1Ch] [rbp-Ch]\n int j; // [rsp+20h] [rbp-8h]\n int k; // [rsp+24h] [rbp-4h]\n\n v5 = 0;\n if ( a4 )\n {\n if ( a4 == a3 )\n {\n v6 = 1;\n for ( i = 0; i < a3; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) != a2[i] )\n return 0;\n }\n return v6;\n }\n else if ( a4 <= a3 )\n {\n for ( j = 0; j <= a3 - a4; ++j )\n {\n if ( *(_DWORD *)(4LL * j + a1) == *a2 )\n {\n for ( k = 1; k < a4 && *(_DWORD *)(4LL * (j + k) + a1) == a2[k]; ++k )\n ;\n if ( k == a4 )\n return 1;\n }\n }\n }\n else\n {\n return 0;\n }\n }\n else\n {\n return 1;\n }\n return v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_28], ecx\nmov [rbp+var_E], 0\ncmp [rbp+var_28], 0\njnz short loc_1192\nmov [rbp+var_E], 1\njmp loc_129A\nloc_1192:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_24]\njnz short loc_11F5\nmov [rbp+var_D], 1\nmov [rbp+var_C], 0\njmp short loc_11E1\nloc_11A7:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_11DD\nmov [rbp+var_D], 0\njmp short loc_11E9\nloc_11DD:\nadd [rbp+var_C], 1\nloc_11E1:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_24]\njl short loc_11A7\nloc_11E9:\nmovzx eax, [rbp+var_D]\nmov [rbp+var_E], al\njmp loc_129A\nloc_11F5:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_24]\njle short loc_1206\nmov [rbp+var_E], 0\njmp loc_129A\nloc_1206:\nmov [rbp+var_8], 0\njmp short loc_128B\nloc_120F:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_20]\nmov eax, [rax]\ncmp edx, eax\njnz short loc_1287\nmov [rbp+var_4], 1\njmp short loc_123C\nloc_1238:\nadd [rbp+var_4], 1\nloc_123C:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_28]\njge short loc_1279\nmov edx, [rbp+var_8]\nmov eax, [rbp+var_4]\nadd eax, edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_1238\nloc_1279:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_28]\njnz short loc_1287\nmov [rbp+var_E], 1\njmp short loc_129A\nloc_1287:\nadd [rbp+var_8], 1\nloc_128B:\nmov eax, [rbp+var_24]\nsub eax, [rbp+var_28]\ncmp [rbp+var_8], eax\njle loc_120F\nloc_129A:\nmovzx eax, [rbp+var_E]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, _DWORD *a2, int a3, int a4)\n{\n unsigned __int8 v5; // [rsp+1Ah] [rbp-Eh]\n unsigned __int8 v6; // [rsp+1Bh] [rbp-Dh]\n int i; // [rsp+1Ch] [rbp-Ch]\n int j; // [rsp+20h] [rbp-8h]\n int k; // [rsp+24h] [rbp-4h]\n\n v5 = 0;\n if ( a4 )\n {\n if ( a4 == a3 )\n {\n v6 = 1;\n for ( i = 0; i < a3; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) != a2[i] )\n return 0;\n }\n return v6;\n }\n else if ( a4 <= a3 )\n {\n for ( j = 0; j <= a3 - a4; ++j )\n {\n if ( *(_DWORD *)(4LL * j + a1) == *a2 )\n {\n for ( k = 1; k < a4 && *(_DWORD *)(4LL * (j + k) + a1) == a2[k]; ++k )\n ;\n if ( k == a4 )\n return 1;\n }\n }\n }\n else\n {\n return 0;\n }\n }\n else\n {\n return 1;\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, uint32_t *a2, int a3, int a4) {\n unsigned char v5;\n unsigned char v6;\n int i;\n int j;\n int k;\n v5 = 0;\n if (a4) {\n if (a4 == a3) {\n v6 = 1;\n for (i = 0; i < a3; ++i) {\n if (*(uint32_t *)(4LL * i + a1) != a2[i]) return 0;\n }\n return v6;\n } else if (a4 <= a3) {\n for (j = 0; j <= a3 - a4; ++j) {\n if (*(uint32_t *)(4LL * j + a1) == *a2) {\n for (k = 1; k < a4 && *(uint32_t *)(4LL * (j + k) + a1) == a2[k]; ++k)\n ;\n if (k == a4) return 1;\n }\n }\n } else {\n return 0;\n }\n } else {\n return 1;\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(long long a1, uint32_t *a2, int a3, int a4) {\n unsigned char v5;\n unsigned char v6;\n int i;\n int j;\n int k;\n v5 = 0;\n if (a4) {\n if (a4 == a3) {\n v6 = 1;\n for (i = 0; i < a3; ++i) {\n if (*(uint32_t *)(4LL * i + a1) != a2[i]) return 0;\n }\n return v6;\n } else if (a4 <= a3) {\n for (j = 0; j <= a3 - a4; ++j) {\n if (*(uint32_t *)(4LL * j + a1) == *a2) {\n for (k = 1; k < a4 && *(uint32_t *)(4LL * (j + k) + a1) == a2[k]; ++k)\n ;\n if (k == a4) return 1;\n }\n }\n } else {\n return 0;\n }\n } else {\n return 1;\n }\n return v5;\n}" + }, + { + "index": 69, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int l[], int s[], int len_l, int len_s) {\n bool sub_set = false;\n if (len_s == 0) {\n sub_set = true;\n } else if (len_s == len_l) {\n bool same = true;\n for (int i = 0; i < len_l; i++) {\n if (l[i] != s[i]) {\n same = false;\n break;\n }\n }\n sub_set = same;\n } else if (len_s > len_l) {\n sub_set = false;\n } else {\n for (int i = 0; i <= len_l - len_s; i++) {\n if (l[i] == s[0]) {\n int n = 1;\n while (n < len_s && l[i + n] == s[n]) {\n n++;\n }\n if (n == len_s) {\n sub_set = true;\n break;\n }\n }\n }\n }\n return sub_set;\n}", + "test": "int main() {\n\n int l[] = {2, 4, 3, 5, 7};\n\n int s1[] = {3, 7};\n\n int s2[] = {4, 3};\n\n int s3[] = {1, 6};\n\n\n\n assert(func0(l, s1, 5, 2) == false);\n\n assert(func0(l, s2, 5, 2) == true);\n\n assert(func0(l, s3, 5, 2) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x1,%eax\ntest %ecx,%ecx\nje 123d \npush %r14\npush %rbp\npush %rbx\ncmp %edx,%ecx\nje 11ac \nmov $0x0,%eax\njg 121c \nsub %ecx,%edx\njs 122f \nmov (%rsi),%ebx\nmov $0x0,%r8d\nmov $0x1,%ebp\nlea -0x2(%rcx),%r11d\nadd $0x2,%r11\njmp 11ea \ntest %edx,%edx\njle 1221 \nlea -0x1(%rdx),%ecx\nmov $0x0,%eax\njmp 11bd \nmov %rdx,%rax\nmov (%rsi,%rax,4),%ebx\ncmp %ebx,(%rdi,%rax,4)\njne 1228 \nlea 0x1(%rax),%rdx\ncmp %rcx,%rax\njne 11ba \nmov $0x1,%eax\njmp 121c \nmov %ebp,%r9d\ncmp %r9d,%ecx\nje 1236 \nadd $0x1,%r8d\nadd $0x4,%rdi\ncmp %edx,%r8d\njg 1217 \nmov %rdi,%r10\ncmp %ebx,(%rdi)\njne 11dd \ncmp $0x1,%ecx\njle 11d5 \nmov $0x1,%eax\nmov %eax,%r9d\nmov (%rsi,%rax,4),%r14d\ncmp %r14d,(%r10,%rax,4)\njne 11d8 \nlea 0x1(%rax),%r9d\nadd $0x1,%rax\ncmp %r11,%rax\njne 11fb \njmp 11d8 \nmov $0x0,%eax\npop %rbx\npop %rbp\npop %r14\nretq\nmov $0x1,%eax\njmp 121c \nmov $0x0,%eax\njmp 121c \nmov $0x0,%eax\njmp 121c \nmov $0x1,%eax\njmp 121c \nretq\n", + "ida_asm": "func0:\nendbr64\nmov rax, rdi\nmov rdi, rsi\nmov esi, 1\ntest ecx, ecx\njz loc_122F\npush r14\npush rbx\ncmp ecx, edx\njz short loc_11A4\nmov esi, 0\njg loc_1214\nsub edx, ecx\nmov ebx, [rdi]\nmov rsi, rax\nmov r8d, 0\nmov r11d, ecx\njmp short loc_11E2\nloc_11A4:\ntest edx, edx\njle short loc_121A\nmovsxd rdx, edx\nshl rdx, 2\nmov ecx, 0\nloc_11B4:\nmov ebx, [rdi+rcx]\ncmp [rax+rcx], ebx\njnz short loc_1221\nadd rcx, 4\ncmp rcx, rdx\njnz short loc_11B4\nmov esi, 1\njmp short loc_1214\nloc_11CC:\nmov eax, 1\nloc_11D1:\ncmp ecx, eax\njz short loc_1228\nloc_11D5:\nadd r8d, 1\nadd rsi, 4\ncmp r8d, edx\njg short loc_120F\nloc_11E2:\nmov r9, rsi\ncmp [rsi], ebx\njnz short loc_11D5\ncmp ecx, 1\njle short loc_11CC\nmov eax, 1\nloc_11F3:\nmov r10d, eax\nmov r14d, [rdi+rax*4]\ncmp [r9+rax*4], r14d\njnz short loc_11D1\nadd rax, 1\ncmp rax, r11\njnz short loc_11F3\nlea eax, [r10+1]\njmp short loc_11D1\nloc_120F:\nmov esi, 0\nloc_1214:\nmov eax, esi\npop rbx\npop r14\nretn\nloc_121A:\nmov esi, 1\njmp short loc_1214\nloc_1221:\nmov esi, 0\njmp short loc_1214\nloc_1228:\nmov esi, 1\njmp short loc_1214\nloc_122F:\nmov eax, esi\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, _DWORD *a2, int a3, int a4)\n{\n unsigned int v6; // esi\n int v7; // edx\n _DWORD *v8; // rsi\n int v9; // r8d\n __int64 v10; // rdx\n unsigned __int64 v11; // rcx\n __int64 v12; // rax\n int v13; // r10d\n\n if ( !a4 )\n return 1LL;\n if ( a4 == a3 )\n {\n if ( a3 <= 0 )\n {\n return 1;\n }\n else\n {\n v10 = 4LL * a3;\n v11 = 0LL;\n while ( a1[v11 / 4] == a2[v11 / 4] )\n {\n v11 += 4LL;\n if ( v11 == v10 )\n return 1;\n }\n return 0;\n }\n }\n else\n {\n v6 = 0;\n if ( a4 <= a3 )\n {\n v7 = a3 - a4;\n v8 = a1;\n v9 = 0;\n while ( 1 )\n {\n if ( *v8 == *a2 )\n {\n if ( a4 <= 1 )\n {\n LODWORD(v12) = 1;\n }\n else\n {\n v12 = 1LL;\n while ( 1 )\n {\n v13 = v12;\n if ( v8[v12] != a2[v12] )\n break;\n if ( ++v12 == a4 )\n {\n LODWORD(v12) = v13 + 1;\n break;\n }\n }\n }\n if ( a4 == (_DWORD)v12 )\n return 1;\n }\n ++v9;\n ++v8;\n if ( v9 > v7 )\n return 0;\n }\n }\n }\n return v6;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov rax, rdi\nmov rdi, rsi\nmov esi, 1\ntest ecx, ecx\njz loc_122F\npush r14\npush rbx\ncmp ecx, edx\njz short loc_11A4\nmov esi, 0\njg loc_1214\nsub edx, ecx\nmov ebx, [rdi]\nmov rsi, rax\nmov r8d, 0\nmov r11d, ecx\njmp short loc_11E2\nloc_11A4:\ntest edx, edx\njle short loc_121A\nmovsxd rdx, edx\nshl rdx, 2\nmov ecx, 0\nloc_11B4:\nmov ebx, [rdi+rcx]\ncmp [rax+rcx], ebx\njnz short loc_1221\nadd rcx, 4\ncmp rcx, rdx\njnz short loc_11B4\nmov esi, 1\njmp short loc_1214\nloc_11CC:\nmov eax, 1\nloc_11D1:\ncmp ecx, eax\njz short loc_1228\nloc_11D5:\nadd r8d, 1\nadd rsi, 4\ncmp r8d, edx\njg short loc_120F\nloc_11E2:\nmov r9, rsi\ncmp [rsi], ebx\njnz short loc_11D5\ncmp ecx, 1\njle short loc_11CC\nmov eax, 1\nloc_11F3:\nmov r10d, eax\nmov r14d, [rdi+rax*4]\ncmp [r9+rax*4], r14d\njnz short loc_11D1\nadd rax, 1\ncmp rax, r11\njnz short loc_11F3\nlea eax, [r10+1]\njmp short loc_11D1\nloc_120F:\nmov esi, 0\nloc_1214:\nmov eax, esi\npop rbx\npop r14\nretn\nloc_121A:\nmov esi, 1\njmp short loc_1214\nloc_1221:\nmov esi, 0\njmp short loc_1214\nloc_1228:\nmov esi, 1\njmp short loc_1214\nloc_122F:\nmov eax, esi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, _DWORD *a2, int a3, int a4)\n{\n unsigned int v6; // esi\n int v7; // edx\n _DWORD *v8; // rsi\n int v9; // r8d\n __int64 v10; // rdx\n unsigned __int64 v11; // rcx\n __int64 v12; // rax\n int v13; // r10d\n\n if ( !a4 )\n return 1LL;\n if ( a4 == a3 )\n {\n if ( a3 <= 0 )\n {\n return 1;\n }\n else\n {\n v10 = 4LL * a3;\n v11 = 0LL;\n while ( a1[v11 / 4] == a2[v11 / 4] )\n {\n v11 += 4LL;\n if ( v11 == v10 )\n return 1;\n }\n return 0;\n }\n }\n else\n {\n v6 = 0;\n if ( a4 <= a3 )\n {\n v7 = a3 - a4;\n v8 = a1;\n v9 = 0;\n while ( 1 )\n {\n if ( *v8 == *a2 )\n {\n if ( a4 <= 1 )\n {\n LODWORD(v12) = 1;\n }\n else\n {\n v12 = 1LL;\n while ( 1 )\n {\n v13 = v12;\n if ( v8[v12] != a2[v12] )\n break;\n if ( ++v12 == a4 )\n {\n LODWORD(v12) = v13 + 1;\n break;\n }\n }\n }\n if ( a4 == (_DWORD)v12 )\n return 1;\n }\n ++v9;\n ++v8;\n if ( v9 > v7 )\n return 0;\n }\n }\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, uint32_t *a2, int a3, int a4) {\n unsigned int v6;\n int v7;\n uint32_t *v8;\n int v9;\n long long v10;\n unsigned long long v11;\n long long v12;\n int v13;\n if (!a4) return 1LL;\n if (a4 == a3) {\n if (a3 <= 0) {\n return 1;\n } else {\n v10 = 4LL * a3;\n v11 = 0LL;\n while (a1[v11 / 4] == a2[v11 / 4]) {\n v11 += 4LL;\n if (v11 == v10) return 1;\n }\n return 0;\n }\n } else {\n v6 = 0;\n if (a4 <= a3) {\n v7 = a3 - a4;\n v8 = a1;\n v9 = 0;\n while (1) {\n if (*v8 == *a2) {\n if (a4 <= 1) {\n LODWORD(v12) = 1;\n } else {\n v12 = 1LL;\n while (1) {\n v13 = v12;\n if (v8[v12] != a2[v12]) break;\n if (++v12 == a4) {\n LODWORD(v12) = v13 + 1;\n break;\n }\n }\n }\n if (a4 == (uint32_t)v12) return 1;\n }\n ++v9;\n ++v8;\n if (v9 > v7) return 0;\n }\n }\n }\n return v6;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, uint32_t *a2, int a3, int a4) {\n unsigned int v6;\n int v7;\n uint32_t *v8;\n int v9;\n long long v10;\n unsigned long long v11;\n long long v12;\n int v13;\n if (!a4) return 1LL;\n if (a4 == a3) {\n if (a3 <= 0) {\n return 1;\n } else {\n v10 = 4LL * a3;\n v11 = 0LL;\n while (a1[v11 / 4] == a2[v11 / 4]) {\n v11 += 4LL;\n if (v11 == v10) return 1;\n }\n return 0;\n }\n } else {\n v6 = 0;\n if (a4 <= a3) {\n v7 = a3 - a4;\n v8 = a1;\n v9 = 0;\n while (1) {\n if (*v8 == *a2) {\n if (a4 <= 1) {\n LODWORD(v12) = 1;\n } else {\n v12 = 1LL;\n while (1) {\n v13 = v12;\n if (v8[v12] != a2[v12]) break;\n if (++v12 == a4) {\n LODWORD(v12) = v13 + 1;\n break;\n }\n }\n }\n if (a4 == (uint32_t)v12) return 1;\n }\n ++v9;\n ++v8;\n if (v9 > v7) return 0;\n }\n }\n }\n return v6;\n}" + }, + { + "index": 69, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int l[], int s[], int len_l, int len_s) {\n bool sub_set = false;\n if (len_s == 0) {\n sub_set = true;\n } else if (len_s == len_l) {\n bool same = true;\n for (int i = 0; i < len_l; i++) {\n if (l[i] != s[i]) {\n same = false;\n break;\n }\n }\n sub_set = same;\n } else if (len_s > len_l) {\n sub_set = false;\n } else {\n for (int i = 0; i <= len_l - len_s; i++) {\n if (l[i] == s[0]) {\n int n = 1;\n while (n < len_s && l[i + n] == s[n]) {\n n++;\n }\n if (n == len_s) {\n sub_set = true;\n break;\n }\n }\n }\n }\n return sub_set;\n}", + "test": "int main() {\n\n int l[] = {2, 4, 3, 5, 7};\n\n int s1[] = {3, 7};\n\n int s2[] = {4, 3};\n\n int s3[] = {1, 6};\n\n\n\n assert(func0(l, s1, 5, 2) == false);\n\n assert(func0(l, s2, 5, 2) == true);\n\n assert(func0(l, s3, 5, 2) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x1,%eax\ntest %ecx,%ecx\nje 1328 \npush %rbx\ncmp %edx,%ecx\nje 1330 \nmov $0x0,%eax\njg 1322 \nlea -0x2(%rcx),%r10d\nmov (%rsi),%r11d\nsub %ecx,%edx\nxor %r8d,%r8d\nadd $0x2,%r10\njmp 12ed \nnopl 0x0(%rax,%rax,1)\nadd $0x1,%r8d\nadd $0x4,%rdi\ncmp %r8d,%edx\njl 1354 \ncmp %r11d,(%rdi)\njne 12e0 \ncmp $0x1,%ecx\njle 1358 \nmov $0x1,%eax\njmp 130d \nxchg %ax,%ax\nlea 0x1(%rax),%r9d\nadd $0x1,%rax\ncmp %r10,%rax\nje 1318 \nmov (%rsi,%rax,4),%ebx\nmov %eax,%r9d\ncmp %ebx,(%rdi,%rax,4)\nje 1300 \ncmp %r9d,%ecx\njne 12e0 \nmov $0x1,%eax\npop %rbx\nretq\nnopl 0x0(%rax)\nretq\nnopl 0x0(%rax)\ntest %ecx,%ecx\njle 1322 \nsub $0x1,%ecx\nxor %eax,%eax\njmp 134c \nnopl 0x0(%rax,%rax,1)\nlea 0x1(%rax),%rdx\ncmp %rax,%rcx\nje 131d \nmov %rdx,%rax\nmov (%rsi,%rax,4),%ebx\ncmp %ebx,(%rdi,%rax,4)\nje 1340 \nxor %eax,%eax\npop %rbx\nretq\nmov $0x1,%r9d\njmp 1318 \n", + "ida_asm": "func0:\nendbr64\nmov rax, rdi\nmov rdi, rsi\nmov esi, 1\ntest ecx, ecx\njz short loc_1320\npush rbx\ncmp ecx, edx\njz short loc_1328\nmov esi, 0\njg short loc_1315\nmov r11d, [rdi]\nsub edx, ecx\nmov rsi, rax\nxor r8d, r8d\nmov r10d, ecx\njmp short loc_12DD\nloc_12D0:\nadd r8d, 1\nadd rsi, 4\ncmp edx, r8d\njl short loc_1351\nloc_12DD:\ncmp [rsi], r11d\njnz short loc_12D0\ncmp ecx, 1\njle loc_136E\nmov eax, 1\njmp short loc_1301\nloc_12F8:\nadd rax, 1\ncmp r10, rax\njz short loc_1360\nloc_1301:\nmov ebx, [rdi+rax*4]\nmov r9d, eax\ncmp [rsi+rax*4], ebx\njz short loc_12F8\nloc_130C:\ncmp ecx, eax\njnz short loc_12D0\nloc_1310:\nmov esi, 1\nloc_1315:\nmov eax, esi\npop rbx\nretn\nloc_1320:\nmov eax, esi\nretn\nloc_1328:\ntest ecx, ecx\njle short loc_1315\nmovsxd rcx, ecx\nxor edx, edx\nshl rcx, 2\njmp short loc_1349\nloc_1340:\nadd rdx, 4\ncmp rcx, rdx\njz short loc_1310\nloc_1349:\nmov ebx, [rdi+rdx]\ncmp [rax+rdx], ebx\njz short loc_1340\nloc_1351:\nxor esi, esi\npop rbx\nmov eax, esi\nretn\nloc_1360:\nlea eax, [r9+1]\ncmp ecx, eax\njnz loc_12D0\njmp short loc_1310\nloc_136E:\nmov eax, 1\njmp short loc_130C", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, _DWORD *a2, int a3, int a4)\n{\n unsigned int v6; // esi\n int v7; // edx\n _DWORD *v8; // rsi\n int v9; // r8d\n __int64 v10; // rax\n int v11; // r9d\n unsigned __int64 v13; // rdx\n __int64 v14; // rcx\n\n v6 = 1;\n if ( !a4 )\n return 1LL;\n if ( a4 != a3 )\n {\n v6 = 0;\n if ( a4 <= a3 )\n {\n v7 = a3 - a4;\n v8 = a1;\n v9 = 0;\n while ( 1 )\n {\n if ( *v8 == *a2 )\n {\n if ( a4 <= 1 )\n {\n LODWORD(v10) = 1;\n }\n else\n {\n v10 = 1LL;\n while ( 1 )\n {\n v11 = v10;\n if ( v8[v10] != a2[v10] )\n break;\n if ( a4 == ++v10 )\n {\n if ( a4 != v11 + 1 )\n goto LABEL_5;\n return 1;\n }\n }\n }\n if ( a4 == (_DWORD)v10 )\n return 1;\n }\nLABEL_5:\n ++v9;\n ++v8;\n if ( v7 < v9 )\n return 0LL;\n }\n }\n return v6;\n }\n if ( a4 <= 0 )\n return v6;\n v13 = 0LL;\n v14 = 4LL * a4;\n while ( a1[v13 / 4] == a2[v13 / 4] )\n {\n v13 += 4LL;\n if ( v14 == v13 )\n return 1;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_12A0:\nendbr64\nmov rax, rdi\nmov rdi, rsi\nmov esi, 1\ntest ecx, ecx\njz short loc_1320\npush rbx\ncmp ecx, edx\njz short loc_1328\nmov esi, 0\njg short loc_1315\nmov r11d, [rdi]\nsub edx, ecx\nmov rsi, rax\nxor r8d, r8d\nmov r10d, ecx\njmp short loc_12DD\nloc_12D0:\nadd r8d, 1\nadd rsi, 4\ncmp edx, r8d\njl short loc_1351\nloc_12DD:\ncmp [rsi], r11d\njnz short loc_12D0\ncmp ecx, 1\njle loc_136E\nmov eax, 1\njmp short loc_1301\nloc_12F8:\nadd rax, 1\ncmp r10, rax\njz short loc_1360\nloc_1301:\nmov ebx, [rdi+rax*4]\nmov r9d, eax\ncmp [rsi+rax*4], ebx\njz short loc_12F8\nloc_130C:\ncmp ecx, eax\njnz short loc_12D0\nloc_1310:\nmov esi, 1\nloc_1315:\nmov eax, esi\npop rbx\nretn\nloc_1320:\nmov eax, esi\nretn\nloc_1328:\ntest ecx, ecx\njle short loc_1315\nmovsxd rcx, ecx\nxor edx, edx\nshl rcx, 2\njmp short loc_1349\nloc_1340:\nadd rdx, 4\ncmp rcx, rdx\njz short loc_1310\nloc_1349:\nmov ebx, [rdi+rdx]\ncmp [rax+rdx], ebx\njz short loc_1340\nloc_1351:\nxor esi, esi\npop rbx\nmov eax, esi\nretn\nloc_1360:\nlea eax, [r9+1]\ncmp ecx, eax\njnz loc_12D0\njmp short loc_1310\nloc_136E:\nmov eax, 1\njmp short loc_130C", + "ida_strip_pseudo": "__int64 __fastcall sub_12A0(_DWORD *a1, _DWORD *a2, int a3, int a4)\n{\n unsigned int v6; // esi\n int v7; // edx\n _DWORD *v8; // rsi\n int v9; // r8d\n __int64 v10; // rax\n int v11; // r9d\n unsigned __int64 v13; // rdx\n __int64 v14; // rcx\n\n v6 = 1;\n if ( !a4 )\n return 1LL;\n if ( a4 != a3 )\n {\n v6 = 0;\n if ( a4 <= a3 )\n {\n v7 = a3 - a4;\n v8 = a1;\n v9 = 0;\n while ( 1 )\n {\n if ( *v8 == *a2 )\n {\n if ( a4 <= 1 )\n {\n LODWORD(v10) = 1;\n }\n else\n {\n v10 = 1LL;\n while ( 1 )\n {\n v11 = v10;\n if ( v8[v10] != a2[v10] )\n break;\n if ( a4 == ++v10 )\n {\n if ( a4 != v11 + 1 )\n goto LABEL_5;\n return 1;\n }\n }\n }\n if ( a4 == (_DWORD)v10 )\n return 1;\n }\nLABEL_5:\n ++v9;\n ++v8;\n if ( v7 < v9 )\n return 0LL;\n }\n }\n return v6;\n }\n if ( a4 <= 0 )\n return v6;\n v13 = 0LL;\n v14 = 4LL * a4;\n while ( a1[v13 / 4] == a2[v13 / 4] )\n {\n v13 += 4LL;\n if ( v14 == v13 )\n return 1;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12A0(uint32_t *a1, uint32_t *a2, int a3, int a4) {\n unsigned int v6;\n int v7;\n uint32_t *v8;\n int v9;\n long long v10;\n int v11;\n unsigned long long v13;\n long long v14;\n v6 = 1;\n if (!a4) return 1LL;\n if (a4 != a3) {\n v6 = 0;\n if (a4 <= a3) {\n v7 = a3 - a4;\n v8 = a1;\n v9 = 0;\n while (1) {\n if (*v8 == *a2) {\n if (a4 <= 1) {\n LODWORD(v10) = 1;\n } else {\n v10 = 1LL;\n while (1) {\n v11 = v10;\n if (v8[v10] != a2[v10]) break;\n if (a4 == ++v10) {\n if (a4 != v11 + 1) goto LABEL_5;\n return 1;\n }\n }\n }\n if (a4 == (uint32_t)v10) return 1;\n }\n LABEL_5:\n ++v9;\n ++v8;\n if (v7 < v9) return 0LL;\n }\n }\n return v6;\n }\n if (a4 <= 0) return v6;\n v13 = 0LL;\n v14 = 4LL * a4;\n while (a1[v13 / 4] == a2[v13 / 4]) {\n v13 += 4LL;\n if (v14 == v13) return 1;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, uint32_t *a2, int a3, int a4) {\n unsigned int v6;\n int v7;\n uint32_t *v8;\n int v9;\n long long v10;\n int v11;\n unsigned long long v13;\n long long v14;\n v6 = 1;\n if (!a4) return 1LL;\n if (a4 != a3) {\n v6 = 0;\n if (a4 <= a3) {\n v7 = a3 - a4;\n v8 = a1;\n v9 = 0;\n while (1) {\n if (*v8 == *a2) {\n if (a4 <= 1) {\n LODWORD(v10) = 1;\n } else {\n v10 = 1LL;\n while (1) {\n v11 = v10;\n if (v8[v10] != a2[v10]) break;\n if (a4 == ++v10) {\n if (a4 != v11 + 1) goto LABEL_5;\n return 1;\n }\n }\n }\n if (a4 == (uint32_t)v10) return 1;\n }\n LABEL_5:\n ++v9;\n ++v8;\n if (v7 < v9) return 0LL;\n }\n }\n return v6;\n }\n if (a4 <= 0) return v6;\n v13 = 0LL;\n v14 = 4LL * a4;\n while (a1[v13 / 4] == a2[v13 / 4]) {\n v13 += 4LL;\n if (v14 == v13) return 1;\n }\n return 0LL;\n}" + }, + { + "index": 69, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int l[], int s[], int len_l, int len_s) {\n bool sub_set = false;\n if (len_s == 0) {\n sub_set = true;\n } else if (len_s == len_l) {\n bool same = true;\n for (int i = 0; i < len_l; i++) {\n if (l[i] != s[i]) {\n same = false;\n break;\n }\n }\n sub_set = same;\n } else if (len_s > len_l) {\n sub_set = false;\n } else {\n for (int i = 0; i <= len_l - len_s; i++) {\n if (l[i] == s[0]) {\n int n = 1;\n while (n < len_s && l[i + n] == s[n]) {\n n++;\n }\n if (n == len_s) {\n sub_set = true;\n break;\n }\n }\n }\n }\n return sub_set;\n}", + "test": "int main() {\n\n int l[] = {2, 4, 3, 5, 7};\n\n int s1[] = {3, 7};\n\n int s2[] = {4, 3};\n\n int s3[] = {1, 6};\n\n\n\n assert(func0(l, s1, 5, 2) == false);\n\n assert(func0(l, s2, 5, 2) == true);\n\n assert(func0(l, s3, 5, 2) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x1,%eax\ntest %ecx,%ecx\nje 1318 \npush %rbx\ncmp %edx,%ecx\nje 1320 \nmov $0x0,%eax\njg 1312 \nlea -0x2(%rcx),%r10d\nmov (%rsi),%r11d\nsub %ecx,%edx\nxor %r8d,%r8d\nadd $0x2,%r10\njmp 12dd \nnopl 0x0(%rax,%rax,1)\nadd $0x1,%r8d\nadd $0x4,%rdi\ncmp %r8d,%edx\njl 1344 \ncmp %r11d,(%rdi)\njne 12d0 \ncmp $0x1,%ecx\njle 1348 \nmov $0x1,%eax\njmp 12fd \nxchg %ax,%ax\nlea 0x1(%rax),%r9d\nadd $0x1,%rax\ncmp %rax,%r10\nje 1308 \nmov (%rsi,%rax,4),%ebx\nmov %eax,%r9d\ncmp %ebx,(%rdi,%rax,4)\nje 12f0 \ncmp %r9d,%ecx\njne 12d0 \nmov $0x1,%eax\npop %rbx\nretq\nnopl 0x0(%rax)\nretq\nnopl 0x0(%rax)\ntest %ecx,%ecx\njle 1312 \nsub $0x1,%ecx\nxor %eax,%eax\njmp 133c \nnopl 0x0(%rax,%rax,1)\nlea 0x1(%rax),%rdx\ncmp %rax,%rcx\nje 130d \nmov %rdx,%rax\nmov (%rsi,%rax,4),%ebx\ncmp %ebx,(%rdi,%rax,4)\nje 1330 \nxor %eax,%eax\npop %rbx\nretq\nmov $0x1,%r9d\njmp 1308 \n", + "ida_asm": "func0:\nendbr64\nmov rax, rdi\nmov rdi, rsi\nmov esi, 1\ntest ecx, ecx\njz short loc_1320\npush rbx\ncmp ecx, edx\njz short loc_1328\nmov esi, 0\njg short loc_1315\nmov r11d, [rdi]\nsub edx, ecx\nmov rsi, rax\nxor r8d, r8d\nmov r10d, ecx\njmp short loc_12DD\nloc_12D0:\nadd r8d, 1\nadd rsi, 4\ncmp edx, r8d\njl short loc_1351\nloc_12DD:\ncmp [rsi], r11d\njnz short loc_12D0\ncmp ecx, 1\njle loc_136E\nmov eax, 1\njmp short loc_1301\nloc_12F8:\nadd rax, 1\ncmp r10, rax\njz short loc_1360\nloc_1301:\nmov ebx, [rdi+rax*4]\nmov r9d, eax\ncmp [rsi+rax*4], ebx\njz short loc_12F8\nloc_130C:\ncmp ecx, eax\njnz short loc_12D0\nloc_1310:\nmov esi, 1\nloc_1315:\nmov eax, esi\npop rbx\nretn\nloc_1320:\nmov eax, esi\nretn\nloc_1328:\ntest ecx, ecx\njle short loc_1315\nmovsxd rcx, ecx\nxor edx, edx\nshl rcx, 2\njmp short loc_1349\nloc_1340:\nadd rdx, 4\ncmp rcx, rdx\njz short loc_1310\nloc_1349:\nmov ebx, [rdi+rdx]\ncmp [rax+rdx], ebx\njz short loc_1340\nloc_1351:\nxor esi, esi\npop rbx\nmov eax, esi\nretn\nloc_1360:\nlea eax, [r9+1]\ncmp ecx, eax\njnz loc_12D0\njmp short loc_1310\nloc_136E:\nmov eax, 1\njmp short loc_130C", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, _DWORD *a2, int a3, int a4)\n{\n unsigned int v6; // esi\n int v7; // edx\n _DWORD *v8; // rsi\n int v9; // r8d\n __int64 v10; // rax\n int v11; // r9d\n unsigned __int64 v13; // rdx\n __int64 v14; // rcx\n\n v6 = 1;\n if ( !a4 )\n return 1LL;\n if ( a4 != a3 )\n {\n v6 = 0;\n if ( a4 <= a3 )\n {\n v7 = a3 - a4;\n v8 = a1;\n v9 = 0;\n while ( 1 )\n {\n if ( *v8 == *a2 )\n {\n if ( a4 <= 1 )\n {\n LODWORD(v10) = 1;\n }\n else\n {\n v10 = 1LL;\n while ( 1 )\n {\n v11 = v10;\n if ( v8[v10] != a2[v10] )\n break;\n if ( a4 == ++v10 )\n {\n if ( a4 != v11 + 1 )\n goto LABEL_5;\n return 1;\n }\n }\n }\n if ( a4 == (_DWORD)v10 )\n return 1;\n }\nLABEL_5:\n ++v9;\n ++v8;\n if ( v7 < v9 )\n return 0LL;\n }\n }\n return v6;\n }\n if ( a4 <= 0 )\n return v6;\n v13 = 0LL;\n v14 = 4LL * a4;\n while ( a1[v13 / 4] == a2[v13 / 4] )\n {\n v13 += 4LL;\n if ( v14 == v13 )\n return 1;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_12A0:\nendbr64\nmov rax, rdi\nmov rdi, rsi\nmov esi, 1\ntest ecx, ecx\njz short loc_1320\npush rbx\ncmp ecx, edx\njz short loc_1328\nmov esi, 0\njg short loc_1315\nmov r11d, [rdi]\nsub edx, ecx\nmov rsi, rax\nxor r8d, r8d\nmov r10d, ecx\njmp short loc_12DD\nloc_12D0:\nadd r8d, 1\nadd rsi, 4\ncmp edx, r8d\njl short loc_1351\nloc_12DD:\ncmp [rsi], r11d\njnz short loc_12D0\ncmp ecx, 1\njle loc_136E\nmov eax, 1\njmp short loc_1301\nloc_12F8:\nadd rax, 1\ncmp r10, rax\njz short loc_1360\nloc_1301:\nmov ebx, [rdi+rax*4]\nmov r9d, eax\ncmp [rsi+rax*4], ebx\njz short loc_12F8\nloc_130C:\ncmp ecx, eax\njnz short loc_12D0\nloc_1310:\nmov esi, 1\nloc_1315:\nmov eax, esi\npop rbx\nretn\nloc_1320:\nmov eax, esi\nretn\nloc_1328:\ntest ecx, ecx\njle short loc_1315\nmovsxd rcx, ecx\nxor edx, edx\nshl rcx, 2\njmp short loc_1349\nloc_1340:\nadd rdx, 4\ncmp rcx, rdx\njz short loc_1310\nloc_1349:\nmov ebx, [rdi+rdx]\ncmp [rax+rdx], ebx\njz short loc_1340\nloc_1351:\nxor esi, esi\npop rbx\nmov eax, esi\nretn\nloc_1360:\nlea eax, [r9+1]\ncmp ecx, eax\njnz loc_12D0\njmp short loc_1310\nloc_136E:\nmov eax, 1\njmp short loc_130C", + "ida_strip_pseudo": "__int64 __fastcall sub_12A0(_DWORD *a1, _DWORD *a2, int a3, int a4)\n{\n unsigned int v6; // esi\n int v7; // edx\n _DWORD *v8; // rsi\n int v9; // r8d\n __int64 v10; // rax\n int v11; // r9d\n unsigned __int64 v13; // rdx\n __int64 v14; // rcx\n\n v6 = 1;\n if ( !a4 )\n return 1LL;\n if ( a4 != a3 )\n {\n v6 = 0;\n if ( a4 <= a3 )\n {\n v7 = a3 - a4;\n v8 = a1;\n v9 = 0;\n while ( 1 )\n {\n if ( *v8 == *a2 )\n {\n if ( a4 <= 1 )\n {\n LODWORD(v10) = 1;\n }\n else\n {\n v10 = 1LL;\n while ( 1 )\n {\n v11 = v10;\n if ( v8[v10] != a2[v10] )\n break;\n if ( a4 == ++v10 )\n {\n if ( a4 != v11 + 1 )\n goto LABEL_5;\n return 1;\n }\n }\n }\n if ( a4 == (_DWORD)v10 )\n return 1;\n }\nLABEL_5:\n ++v9;\n ++v8;\n if ( v7 < v9 )\n return 0LL;\n }\n }\n return v6;\n }\n if ( a4 <= 0 )\n return v6;\n v13 = 0LL;\n v14 = 4LL * a4;\n while ( a1[v13 / 4] == a2[v13 / 4] )\n {\n v13 += 4LL;\n if ( v14 == v13 )\n return 1;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12A0(uint32_t *a1, uint32_t *a2, int a3, int a4) {\n unsigned int v6;\n int v7;\n uint32_t *v8;\n int v9;\n long long v10;\n int v11;\n unsigned long long v13;\n long long v14;\n v6 = 1;\n if (!a4) return 1LL;\n if (a4 != a3) {\n v6 = 0;\n if (a4 <= a3) {\n v7 = a3 - a4;\n v8 = a1;\n v9 = 0;\n while (1) {\n if (*v8 == *a2) {\n if (a4 <= 1) {\n LODWORD(v10) = 1;\n } else {\n v10 = 1LL;\n while (1) {\n v11 = v10;\n if (v8[v10] != a2[v10]) break;\n if (a4 == ++v10) {\n if (a4 != v11 + 1) goto LABEL_5;\n return 1;\n }\n }\n }\n if (a4 == (uint32_t)v10) return 1;\n }\n LABEL_5:\n ++v9;\n ++v8;\n if (v7 < v9) return 0LL;\n }\n }\n return v6;\n }\n if (a4 <= 0) return v6;\n v13 = 0LL;\n v14 = 4LL * a4;\n while (a1[v13 / 4] == a2[v13 / 4]) {\n v13 += 4LL;\n if (v14 == v13) return 1;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, uint32_t *a2, int a3, int a4) {\n unsigned int v6;\n int v7;\n uint32_t *v8;\n int v9;\n long long v10;\n int v11;\n unsigned long long v13;\n long long v14;\n v6 = 1;\n if (!a4) return 1LL;\n if (a4 != a3) {\n v6 = 0;\n if (a4 <= a3) {\n v7 = a3 - a4;\n v8 = a1;\n v9 = 0;\n while (1) {\n if (*v8 == *a2) {\n if (a4 <= 1) {\n LODWORD(v10) = 1;\n } else {\n v10 = 1LL;\n while (1) {\n v11 = v10;\n if (v8[v10] != a2[v10]) break;\n if (a4 == ++v10) {\n if (a4 != v11 + 1) goto LABEL_5;\n return 1;\n }\n }\n }\n if (a4 == (uint32_t)v10) return 1;\n }\n LABEL_5:\n ++v9;\n ++v8;\n if (v7 < v9) return 0LL;\n }\n }\n return v6;\n }\n if (a4 <= 0) return v6;\n v13 = 0LL;\n v14 = 4LL * a4;\n while (a1[v13 / 4] == a2[v13 / 4]) {\n v13 += 4LL;\n if (v14 == v13) return 1;\n }\n return 0LL;\n}" + }, + { + "index": 70, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\nint find_equal_tuple(int Input[][10], int array_size, int k) {\n\n int flag = 1;\n\n for (int i = 0; i < array_size; ++i) {\n\n int count = 0;\n\n for (int j = 0; j < 10 && (Input[i][j] != 0 || j == 0); ++j) {\n\n count++;\n\n }\n\n if (count != k) {\n\n flag = 0;\n\n break;\n\n }\n\n }\n\n return flag;\n\n}\n\n\n\n", + "func": "char* func0(int Input[][10], int array_size, int k) {\n if (find_equal_tuple(Input, array_size, k) == 1) {\n return \"All tuples have same length\";\n } else {\n return \"All tuples do not have same length\";\n }\n}", + "test": "int main() {\n\n int Input1[][10] = {{11, 22, 33}, {44, 55, 66}};\n\n int Input2[][10] = {{1, 2, 3}, {4, 5, 6, 7}};\n\n int Input3[][10] = {{1, 2}, {3, 4}};\n\n\n\n assert(func0(Input1, 2, 3) == \"All tuples have same length\");\n\n assert(func0(Input2, 2, 3) == \"All tuples do not have same length\");\n\n assert(func0(Input3, 2, 2) == \"All tuples have same length\");\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %rdi,-0x8(%rbp)\nmov %esi,-0xc(%rbp)\nmov %edx,-0x10(%rbp)\nmov -0x10(%rbp),%edx\nmov -0xc(%rbp),%ecx\nmov -0x8(%rbp),%rax\nmov %ecx,%esi\nmov %rax,%rdi\ncallq 1169 \ncmp $0x1,%eax\njne 1233 \nlea 0xdd7(%rip),%rax\njmp 123a \nlea 0xdee(%rip),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+var_8], rdi\nmov [rbp+var_C], esi\nmov [rbp+var_10], edx\nmov edx, [rbp+var_10]\nmov ecx, [rbp+var_C]\nmov rax, [rbp+var_8]\nmov esi, ecx\nmov rdi, rax\ncall find_equal_tuple\ncmp eax, 1\njnz short loc_1233\nlea rax, aAllTuplesHaveS; \"All tuples have same length\"\njmp short locret_123A\nloc_1233:\nlea rax, aAllTuplesDoNot; \"All tuples do not have same length\"\nlocret_123A:\nleave\nretn", + "ida_pseudo": "const char *__fastcall func0(__int64 a1, unsigned int a2, unsigned int a3)\n{\n if ( (unsigned int)find_equal_tuple(a1, a2, a3) == 1 )\n return \"All tuples have same length\";\n else\n return \"All tuples do not have same length\";\n}", + "ida_strip_asm": "sub_11FB:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+var_8], rdi\nmov [rbp+var_C], esi\nmov [rbp+var_10], edx\nmov edx, [rbp+var_10]\nmov ecx, [rbp+var_C]\nmov rax, [rbp+var_8]\nmov esi, ecx\nmov rdi, rax\ncall sub_1169\ncmp eax, 1\njnz short loc_1233\nlea rax, aAllTuplesHaveS; \"All tuples have same length\"\njmp short locret_123A\nloc_1233:\nlea rax, aAllTuplesDoNot; \"All tuples do not have same length\"\nlocret_123A:\nleave\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_11FB(__int64 a1, unsigned int a2, unsigned int a3)\n{\n if ( (unsigned int)sub_1169(a1, a2, a3) == 1 )\n return \"All tuples have same length\";\n else\n return \"All tuples do not have same length\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char* sub_11FB(long long a1, unsigned int a2, unsigned int a3) {\n if ((unsigned int)sub_1169(a1, a2, a3) == 1)\n return \"All tuples have same length\";\n else\n return \"All tuples do not have same length\";\n}", + "ida_pseudo_norm": "const char* func0(long long a1, unsigned int a2, unsigned int a3) {\n if ((unsigned int)find_equal_tuple(a1, a2, a3) == 1)\n return \"All tuples have same length\";\n else\n return \"All tuples do not have same length\";\n}" + }, + { + "index": 70, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\nint find_equal_tuple(int Input[][10], int array_size, int k) {\n\n int flag = 1;\n\n for (int i = 0; i < array_size; ++i) {\n\n int count = 0;\n\n for (int j = 0; j < 10 && (Input[i][j] != 0 || j == 0); ++j) {\n\n count++;\n\n }\n\n if (count != k) {\n\n flag = 0;\n\n break;\n\n }\n\n }\n\n return flag;\n\n}\n\n\n\n", + "func": "char* func0(int Input[][10], int array_size, int k) {\n if (find_equal_tuple(Input, array_size, k) == 1) {\n return \"All tuples have same length\";\n } else {\n return \"All tuples do not have same length\";\n }\n}", + "test": "int main() {\n\n int Input1[][10] = {{11, 22, 33}, {44, 55, 66}};\n\n int Input2[][10] = {{1, 2, 3}, {4, 5, 6, 7}};\n\n int Input3[][10] = {{1, 2}, {3, 4}};\n\n\n\n assert(func0(Input1, 2, 3) == \"All tuples have same length\");\n\n assert(func0(Input2, 2, 3) == \"All tuples do not have same length\");\n\n assert(func0(Input3, 2, 2) == \"All tuples have same length\");\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ncallq 1169 \ncmp $0x1,%eax\nlea 0xe2b(%rip),%rax\nlea 0xe40(%rip),%rdx\ncmovne %rdx,%rax\nretq\n", + "ida_asm": "func0:\nendbr64\ncall find_equal_tuple\ncmp eax, 1\nlea rax, aAllTuplesDoNot; \"All tuples do not have same length\"\nlea rdx, aAllTuplesHaveS; \"All tuples have same length\"\ncmovz rax, rdx\nretn", + "ida_pseudo": "const char *func0()\n{\n bool v0; // zf\n const char *result; // rax\n\n v0 = (unsigned int)find_equal_tuple() == 1;\n result = \"All tuples do not have same length\";\n if ( v0 )\n return \"All tuples have same length\";\n return result;\n}", + "ida_strip_asm": "sub_11C5:\nendbr64\ncall sub_1169\ncmp eax, 1\nlea rax, aAllTuplesDoNot; \"All tuples do not have same length\"\nlea rdx, aAllTuplesHaveS; \"All tuples have same length\"\ncmovz rax, rdx\nretn", + "ida_strip_pseudo": "const char *sub_11C5()\n{\n bool v0; // zf\n const char *result; // rax\n\n v0 = (unsigned int)sub_1169() == 1;\n result = \"All tuples do not have same length\";\n if ( v0 )\n return \"All tuples have same length\";\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_11C5() {\n bool v0;\n const char *result;\n v0 = (unsigned int)sub_1169() == 1;\n result = \"All tuples do not have same length\";\n if (v0) return \"All tuples have same length\";\n return result;\n}", + "ida_pseudo_norm": "const char *func0() {\n bool v0;\n const char *result;\n v0 = (unsigned int)find_equal_tuple() == 1;\n result = \"All tuples do not have same length\";\n if (v0) return \"All tuples have same length\";\n return result;\n}" + }, + { + "index": 71, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int *nums, int size) {\n float shrink_fact = 1.3;\n int gaps = size;\n int swapped = 1;\n int i = 0;\n while (gaps > 1 || swapped) {\n gaps = (int)((float)gaps / shrink_fact);\n swapped = 0;\n i = 0;\n while (gaps + i < size) {\n if (nums[i] > nums[i + gaps]) {\n int temp = nums[i];\n nums[i] = nums[i + gaps];\n nums[i + gaps] = temp;\n swapped = 1;\n }\n i++;\n }\n }\n}", + "test": "int main() {\n\n int arr1[] = {5, 15, 37, 25, 79};\n\n int arr2[] = {41, 32, 15, 19, 22};\n\n int arr3[] = {99, 15, 13, 47};\n\n func0(arr1, 5);\n\n func0(arr2, 5);\n\n func0(arr3, 4);\n\n assert(arr1[0] == 5 && arr1[1] == 15 && arr1[2] == 25 && arr1[3] == 37 && arr1[4] == 79);\n\n assert(arr2[0] == 15 && arr2[1] == 19 && arr2[2] == 22 && arr2[3] == 32 && arr2[4] == 41);\n\n assert(arr3[0] == 13 && arr3[1] == 15 && arr3[2] == 47 && arr3[3] == 99);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmovss 0xfc0(%rip),%xmm0\nmovss %xmm0,-0x8(%rbp)\nmov -0x2c(%rbp),%eax\nmov %eax,-0x14(%rbp)\nmovl $0x1,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\njmpq 127c \ncvtsi2ssl -0x14(%rbp),%xmm0\ndivss -0x8(%rbp),%xmm0\ncvttss2si %xmm0,%eax\nmov %eax,-0x14(%rbp)\nmovl $0x0,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\njmpq 126b \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0xc(%rbp),%ecx\nmov -0x14(%rbp),%eax\nadd %ecx,%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njle 1267 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x4(%rbp)\nmov -0xc(%rbp),%edx\nmov -0x14(%rbp),%eax\nadd %edx,%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov -0xc(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x28(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\nmov -0xc(%rbp),%edx\nmov -0x14(%rbp),%eax\nadd %edx,%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rax,%rdx\nmov -0x4(%rbp),%eax\nmov %eax,(%rdx)\nmovl $0x1,-0x10(%rbp)\naddl $0x1,-0xc(%rbp)\nmov -0x14(%rbp),%edx\nmov -0xc(%rbp),%eax\nadd %edx,%eax\ncmp %eax,-0x2c(%rbp)\njg 11c2 \ncmpl $0x1,-0x14(%rbp)\njg 119e \ncmpl $0x0,-0x10(%rbp)\njne 119e \npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmovss xmm0, cs:dword_2120\nmovss [rbp+var_8], xmm0\nmov eax, [rbp+var_2C]\nmov [rbp+var_14], eax\nmov [rbp+var_10], 1\nmov [rbp+var_C], 0\njmp loc_1280\nloc_119E:\npxor xmm0, xmm0\ncvtsi2ss xmm0, [rbp+var_14]\ndivss xmm0, [rbp+var_8]\ncvttss2si eax, xmm0\nmov [rbp+var_14], eax\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp loc_126F\nloc_11C6:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov ecx, [rbp+var_C]\nmov eax, [rbp+var_14]\nadd eax, ecx\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_126B\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov edx, [rbp+var_C]\nmov eax, [rbp+var_14]\nadd eax, edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov edx, [rbp+var_C]\nmov eax, [rbp+var_14]\nadd eax, edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nmov [rbp+var_10], 1\nloc_126B:\nadd [rbp+var_C], 1\nloc_126F:\nmov edx, [rbp+var_14]\nmov eax, [rbp+var_C]\nadd eax, edx\ncmp [rbp+var_2C], eax\njg loc_11C6\nloc_1280:\ncmp [rbp+var_14], 1\njg loc_119E\ncmp [rbp+var_10], 0\njnz loc_119E\nnop\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 result; // rax\n int v3; // [rsp+18h] [rbp-14h]\n int v4; // [rsp+1Ch] [rbp-10h]\n int i; // [rsp+20h] [rbp-Ch]\n int v6; // [rsp+28h] [rbp-4h]\n\n result = (unsigned int)a2;\n v3 = a2;\n v4 = 1;\n while ( v3 > 1 || v4 )\n {\n v3 = (int)(float)((float)v3 / 1.3);\n v4 = 0;\n for ( i = 0; ; ++i )\n {\n result = (unsigned int)(v3 + i);\n if ( a2 <= (int)result )\n break;\n if ( *(_DWORD *)(4LL * i + a1) > *(_DWORD *)(4LL * (i + v3) + a1) )\n {\n v6 = *(_DWORD *)(4LL * i + a1);\n *(_DWORD *)(4LL * i + a1) = *(_DWORD *)(4LL * (i + v3) + a1);\n *(_DWORD *)(a1 + 4LL * (i + v3)) = v6;\n v4 = 1;\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmovss xmm0, cs:dword_2120\nmovss [rbp+var_8], xmm0\nmov eax, [rbp+var_2C]\nmov [rbp+var_14], eax\nmov [rbp+var_10], 1\nmov [rbp+var_C], 0\njmp loc_1280\nloc_119E:\npxor xmm0, xmm0\ncvtsi2ss xmm0, [rbp+var_14]\ndivss xmm0, [rbp+var_8]\ncvttss2si eax, xmm0\nmov [rbp+var_14], eax\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp loc_126F\nloc_11C6:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov ecx, [rbp+var_C]\nmov eax, [rbp+var_14]\nadd eax, ecx\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_126B\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov edx, [rbp+var_C]\nmov eax, [rbp+var_14]\nadd eax, edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov edx, [rbp+var_C]\nmov eax, [rbp+var_14]\nadd eax, edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nmov [rbp+var_10], 1\nloc_126B:\nadd [rbp+var_C], 1\nloc_126F:\nmov edx, [rbp+var_14]\nmov eax, [rbp+var_C]\nadd eax, edx\ncmp [rbp+var_2C], eax\njg loc_11C6\nloc_1280:\ncmp [rbp+var_14], 1\njg loc_119E\ncmp [rbp+var_10], 0\njnz loc_119E\nnop\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n __int64 result; // rax\n int v3; // [rsp+18h] [rbp-14h]\n int v4; // [rsp+1Ch] [rbp-10h]\n int i; // [rsp+20h] [rbp-Ch]\n int v6; // [rsp+28h] [rbp-4h]\n\n result = (unsigned int)a2;\n v3 = a2;\n v4 = 1;\n while ( v3 > 1 || v4 )\n {\n v3 = (int)(float)((float)v3 / 1.3);\n v4 = 0;\n for ( i = 0; ; ++i )\n {\n result = (unsigned int)(v3 + i);\n if ( a2 <= (int)result )\n break;\n if ( *(_DWORD *)(4LL * i + a1) > *(_DWORD *)(4LL * (i + v3) + a1) )\n {\n v6 = *(_DWORD *)(4LL * i + a1);\n *(_DWORD *)(4LL * i + a1) = *(_DWORD *)(4LL * (i + v3) + a1);\n *(_DWORD *)(a1 + 4LL * (i + v3)) = v6;\n v4 = 1;\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n long long result;\n int v3;\n int v4;\n int i;\n int v6;\n result = (unsigned int)a2;\n v3 = a2;\n v4 = 1;\n while (v3 > 1 || v4) {\n v3 = (int)(float)((float)v3 / 1.3);\n v4 = 0;\n for (i = 0;; ++i) {\n result = (unsigned int)(v3 + i);\n if (a2 <= (int)result) break;\n if (*(uint32_t *)(4LL * i + a1) > *(uint32_t *)(4LL * (i + v3) + a1)) {\n v6 = *(uint32_t *)(4LL * i + a1);\n *(uint32_t *)(4LL * i + a1) = *(uint32_t *)(4LL * (i + v3) + a1);\n *(uint32_t *)(a1 + 4LL * (i + v3)) = v6;\n v4 = 1;\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long result;\n int v3;\n int v4;\n int i;\n int v6;\n result = (unsigned int)a2;\n v3 = a2;\n v4 = 1;\n while (v3 > 1 || v4) {\n v3 = (int)(float)((float)v3 / 1.3);\n v4 = 0;\n for (i = 0;; ++i) {\n result = (unsigned int)(v3 + i);\n if (a2 <= (int)result) break;\n if (*(uint32_t *)(4LL * i + a1) > *(uint32_t *)(4LL * (i + v3) + a1)) {\n v6 = *(uint32_t *)(4LL * i + a1);\n *(uint32_t *)(4LL * i + a1) = *(uint32_t *)(4LL * (i + v3) + a1);\n *(uint32_t *)(a1 + 4LL * (i + v3)) = v6;\n v4 = 1;\n }\n }\n }\n return result;\n}" + }, + { + "index": 71, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int *nums, int size) {\n float shrink_fact = 1.3;\n int gaps = size;\n int swapped = 1;\n int i = 0;\n while (gaps > 1 || swapped) {\n gaps = (int)((float)gaps / shrink_fact);\n swapped = 0;\n i = 0;\n while (gaps + i < size) {\n if (nums[i] > nums[i + gaps]) {\n int temp = nums[i];\n nums[i] = nums[i + gaps];\n nums[i + gaps] = temp;\n swapped = 1;\n }\n i++;\n }\n }\n}", + "test": "int main() {\n\n int arr1[] = {5, 15, 37, 25, 79};\n\n int arr2[] = {41, 32, 15, 19, 22};\n\n int arr3[] = {99, 15, 13, 47};\n\n func0(arr1, 5);\n\n func0(arr2, 5);\n\n func0(arr3, 4);\n\n assert(arr1[0] == 5 && arr1[1] == 15 && arr1[2] == 25 && arr1[3] == 37 && arr1[4] == 79);\n\n assert(arr2[0] == 15 && arr2[1] == 19 && arr2[2] == 22 && arr2[3] == 32 && arr2[4] == 41);\n\n assert(arr3[0] == 13 && arr3[1] == 15 && arr3[2] == 47 && arr3[3] == 99);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nmov %esi,%edi\nmov %esi,%r9d\nmovss 0xfbd(%rip),%xmm1\nlea -0x1(%rsi),%r13d\nlea 0x4(%rbx),%r12\nmov $0x0,%ebp\nmov $0x1,%esi\njmp 11c3 \nadd $0x4,%rax\ncmp %r10,%rax\nje 11b8 \nmov (%rax),%edx\nmov (%rax,%r8,4),%ecx\ncmp %ecx,%edx\njle 1197 \nmov %ecx,(%rax)\nmov %edx,(%rax,%r8,4)\nmov %esi,%r11d\njmp 1197 \nmov %ebp,%r11d\ncmp $0x1,%r9d\njg 11c3 \ntest %r11d,%r11d\nje 11ef \npxor %xmm0,%xmm0\ncvtsi2ss %r9d,%xmm0\ndivss %xmm1,%xmm0\ncvttss2si %xmm0,%r9d\ncmp %r9d,%edi\njle 11b5 \nmov %rbx,%rax\nmov %r13d,%edx\nsub %r9d,%edx\nlea (%r12,%rdx,4),%r10\nmov %ebp,%r11d\nmovslq %r9d,%r8\njmp 11a0 \npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nmov rbx, rdi\nmov edi, esi\nmov r10d, esi\nmovss xmm1, cs:dword_2004\nmov ebp, 0\nmov esi, 1\njmp short loc_11BA\nloc_118B:\nadd rax, 4\ncmp rax, r9\njz short loc_11AF\nloc_1194:\nmov edx, [rax]\nmov ecx, [rax+r8*4]\ncmp edx, ecx\njle short loc_118B\nmov [rax], ecx\nmov [rax+r8*4], edx\nmov r11d, esi\njmp short loc_118B\nloc_11A9:\nmov r11d, 0\nloc_11AF:\ncmp r10d, 1\njg short loc_11BA\ntest r11d, r11d\njz short loc_11E5\nloc_11BA:\npxor xmm0, xmm0\ncvtsi2ss xmm0, r10d\ndivss xmm0, xmm1\ncvttss2si r10d, xmm0\ncmp edi, r10d\njle short loc_11A9\nmov rax, rbx\nmov edx, edi\nsub edx, r10d\nlea r9, [rbx+rdx*4]\nmov r11d, ebp\nmovsxd r8, r10d\njmp short loc_1194\nloc_11E5:\npop rbx\npop rbp\nretn", + "ida_pseudo": "void __fastcall func0(int *a1, int a2)\n{\n int v2; // r10d\n int *v3; // rax\n int v4; // edx\n int v5; // ecx\n int v6; // r11d\n\n v2 = a2;\n do\n {\n v2 = (int)(float)((float)v2 / 1.3);\n if ( a2 <= v2 )\n {\n v6 = 0;\n }\n else\n {\n v3 = a1;\n v6 = 0;\n do\n {\n v4 = *v3;\n v5 = v3[v2];\n if ( *v3 > v5 )\n {\n *v3 = v5;\n v3[v2] = v4;\n v6 = 1;\n }\n ++v3;\n }\n while ( v3 != &a1[a2 - v2] );\n }\n }\n while ( v2 > 1 || v6 );\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\npush rbx\nmov rbx, rdi\nmov edi, esi\nmov r10d, esi\nmovss xmm1, cs:dword_2004\nmov ebp, 0\nmov esi, 1\njmp short loc_11BA\nloc_118B:\nadd rax, 4\ncmp rax, r9\njz short loc_11AF\nloc_1194:\nmov edx, [rax]\nmov ecx, [rax+r8*4]\ncmp edx, ecx\njle short loc_118B\nmov [rax], ecx\nmov [rax+r8*4], edx\nmov r11d, esi\njmp short loc_118B\nloc_11A9:\nmov r11d, 0\nloc_11AF:\ncmp r10d, 1\njg short loc_11BA\ntest r11d, r11d\njz short loc_11E5\nloc_11BA:\npxor xmm0, xmm0\ncvtsi2ss xmm0, r10d\ndivss xmm0, xmm1\ncvttss2si r10d, xmm0\ncmp edi, r10d\njle short loc_11A9\nmov rax, rbx\nmov edx, edi\nsub edx, r10d\nlea r9, [rbx+rdx*4]\nmov r11d, ebp\nmovsxd r8, r10d\njmp short loc_1194\nloc_11E5:\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "void __fastcall sub_1169(int *a1, int a2)\n{\n int v2; // r10d\n int *v3; // rax\n int v4; // edx\n int v5; // ecx\n int v6; // r11d\n\n v2 = a2;\n do\n {\n v2 = (int)(float)((float)v2 / 1.3);\n if ( a2 <= v2 )\n {\n v6 = 0;\n }\n else\n {\n v3 = a1;\n v6 = 0;\n do\n {\n v4 = *v3;\n v5 = v3[v2];\n if ( *v3 > v5 )\n {\n *v3 = v5;\n v3[v2] = v4;\n v6 = 1;\n }\n ++v3;\n }\n while ( v3 != &a1[a2 - v2] );\n }\n }\n while ( v2 > 1 || v6 );\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1169(int *a1, int a2) {\n int v2;\n int *v3;\n int v4;\n int v5;\n int v6;\n v2 = a2;\n do {\n v2 = (int)(float)((float)v2 / 1.3);\n if (a2 <= v2) {\n v6 = 0;\n } else {\n v3 = a1;\n v6 = 0;\n do {\n v4 = *v3;\n v5 = v3[v2];\n if (*v3 > v5) {\n *v3 = v5;\n v3[v2] = v4;\n v6 = 1;\n }\n ++v3;\n } while (v3 != &a1[a2 - v2]);\n }\n } while (v2 > 1 || v6);\n}", + "ida_pseudo_norm": "void func0(int *a1, int a2) {\n int v2;\n int *v3;\n int v4;\n int v5;\n int v6;\n v2 = a2;\n do {\n v2 = (int)(float)((float)v2 / 1.3);\n if (a2 <= v2) {\n v6 = 0;\n } else {\n v3 = a1;\n v6 = 0;\n do {\n v4 = *v3;\n v5 = v3[v2];\n if (*v3 > v5) {\n *v3 = v5;\n v3[v2] = v4;\n v6 = 1;\n }\n ++v3;\n } while (v3 != &a1[a2 - v2]);\n }\n } while (v2 > 1 || v6);\n}" + }, + { + "index": 71, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int *nums, int size) {\n float shrink_fact = 1.3;\n int gaps = size;\n int swapped = 1;\n int i = 0;\n while (gaps > 1 || swapped) {\n gaps = (int)((float)gaps / shrink_fact);\n swapped = 0;\n i = 0;\n while (gaps + i < size) {\n if (nums[i] > nums[i + gaps]) {\n int temp = nums[i];\n nums[i] = nums[i + gaps];\n nums[i + gaps] = temp;\n swapped = 1;\n }\n i++;\n }\n }\n}", + "test": "int main() {\n\n int arr1[] = {5, 15, 37, 25, 79};\n\n int arr2[] = {41, 32, 15, 19, 22};\n\n int arr3[] = {99, 15, 13, 47};\n\n func0(arr1, 5);\n\n func0(arr2, 5);\n\n func0(arr3, 4);\n\n assert(arr1[0] == 5 && arr1[1] == 15 && arr1[2] == 25 && arr1[3] == 37 && arr1[4] == 79);\n\n assert(arr2[0] == 15 && arr2[1] == 19 && arr2[2] == 22 && arr2[3] == 32 && arr2[4] == 41);\n\n assert(arr3[0] == 13 && arr3[1] == 15 && arr3[2] == 47 && arr3[3] == 99);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmovss 0xe34(%rip),%xmm1\npush %rbp\nmov %esi,%r9d\nlea -0x1(%rsi),%ebp\npush %rbx\nlea 0x4(%rdi),%rbx\nnopl 0x0(%rax,%rax,1)\npxor %xmm0,%xmm0\ncvtsi2ss %r9d,%xmm0\ndivss %xmm1,%xmm0\ncvttss2si %xmm0,%r9d\ncmp %r9d,%esi\njle 1388 \nmov %ebp,%edx\nmov %rdi,%rax\nxor %r11d,%r11d\nmovslq %r9d,%r8\nsub %r9d,%edx\nlea (%rbx,%rdx,4),%r10\nnopl 0x0(%rax)\nmov (%rax),%edx\nmov (%rax,%r8,4),%ecx\ncmp %ecx,%edx\njle 1366 \nmov %ecx,(%rax)\nmov $0x1,%r11d\nmov %edx,(%rax,%r8,4)\nadd $0x4,%rax\ncmp %rax,%r10\njne 1350 \nand $0x1,%r11d\ncmp $0x1,%r9d\njg 1320 \ntest %r11b,%r11b\njne 1320 \npop %rbx\npop %rbp\nretq\nnopl 0x0(%rax)\nxor %r11d,%r11d\njmp 1373 \nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\nmovss xmm1, cs:dword_2004\nmov r11d, esi\nnop\nloc_12D0:\npxor xmm0, xmm0\ncvtsi2ss xmm0, r11d\ndivss xmm0, xmm1\ncvttss2si r11d, xmm0\ncmp esi, r11d\njle short loc_1330\nmov edx, esi\nmov rax, rdi\nxor r10d, r10d\nmovsxd r8, r11d\nsub edx, r11d\nlea r9, [rdi+rdx*4]\nnop dword ptr [rax+00000000h]\nloc_1300:\nmov edx, [rax]\nmov ecx, [rax+r8*4]\ncmp edx, ecx\njle short loc_1316\nmov [rax], ecx\nmov r10d, 1\nmov [rax+r8*4], edx\nloc_1316:\nadd rax, 4\ncmp r9, rax\njnz short loc_1300\nand r10d, 1\nloc_1323:\ncmp r11d, 1\njg short loc_12D0\ntest r10b, r10b\njnz short loc_12D0\nretn\nloc_1330:\nxor r10d, r10d\njmp short loc_1323", + "ida_pseudo": "void __fastcall func0(int *a1, int a2)\n{\n int v2; // r11d\n int *v3; // rax\n char v4; // r10\n int v5; // edx\n int v6; // ecx\n\n v2 = a2;\n do\n {\n v2 = (int)(float)((float)v2 / 1.3);\n if ( a2 <= v2 )\n {\n v4 = 0;\n }\n else\n {\n v3 = a1;\n v4 = 0;\n do\n {\n v5 = *v3;\n v6 = v3[v2];\n if ( *v3 > v6 )\n {\n *v3 = v6;\n v4 = 1;\n v3[v2] = v5;\n }\n ++v3;\n }\n while ( &a1[a2 - v2] != v3 );\n }\n }\n while ( v2 > 1 || v4 );\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\nmovss xmm1, cs:dword_2004\nmov r11d, esi\nnop\nloc_12D0:\npxor xmm0, xmm0\ncvtsi2ss xmm0, r11d\ndivss xmm0, xmm1\ncvttss2si r11d, xmm0\ncmp esi, r11d\njle short loc_1330\nmov edx, esi\nmov rax, rdi\nxor r10d, r10d\nmovsxd r8, r11d\nsub edx, r11d\nlea r9, [rdi+rdx*4]\nnop dword ptr [rax+00000000h]\nloc_1300:\nmov edx, [rax]\nmov ecx, [rax+r8*4]\ncmp edx, ecx\njle short loc_1316\nmov [rax], ecx\nmov r10d, 1\nmov [rax+r8*4], edx\nloc_1316:\nadd rax, 4\ncmp r9, rax\njnz short loc_1300\nand r10d, 1\nloc_1323:\ncmp r11d, 1\njg short loc_12D0\ntest r10b, r10b\njnz short loc_12D0\nretn\nloc_1330:\nxor r10d, r10d\njmp short loc_1323", + "ida_strip_pseudo": "void __fastcall sub_12C0(int *a1, int a2)\n{\n int v2; // r11d\n int *v3; // rax\n char v4; // r10\n int v5; // edx\n int v6; // ecx\n\n v2 = a2;\n do\n {\n v2 = (int)(float)((float)v2 / 1.3);\n if ( a2 <= v2 )\n {\n v4 = 0;\n }\n else\n {\n v3 = a1;\n v4 = 0;\n do\n {\n v5 = *v3;\n v6 = v3[v2];\n if ( *v3 > v6 )\n {\n *v3 = v6;\n v4 = 1;\n v3[v2] = v5;\n }\n ++v3;\n }\n while ( &a1[a2 - v2] != v3 );\n }\n }\n while ( v2 > 1 || v4 );\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_12C0(int *a1, int a2) {\n int v2;\n int *v3;\n char v4;\n int v5;\n int v6;\n v2 = a2;\n do {\n v2 = (int)(float)((float)v2 / 1.3);\n if (a2 <= v2) {\n v4 = 0;\n } else {\n v3 = a1;\n v4 = 0;\n do {\n v5 = *v3;\n v6 = v3[v2];\n if (*v3 > v6) {\n *v3 = v6;\n v4 = 1;\n v3[v2] = v5;\n }\n ++v3;\n } while (&a1[a2 - v2] != v3);\n }\n } while (v2 > 1 || v4);\n}", + "ida_pseudo_norm": "void func0(int *a1, int a2) {\n int v2;\n int *v3;\n char v4;\n int v5;\n int v6;\n v2 = a2;\n do {\n v2 = (int)(float)((float)v2 / 1.3);\n if (a2 <= v2) {\n v4 = 0;\n } else {\n v3 = a1;\n v4 = 0;\n do {\n v5 = *v3;\n v6 = v3[v2];\n if (*v3 > v6) {\n *v3 = v6;\n v4 = 1;\n v3[v2] = v5;\n }\n ++v3;\n } while (&a1[a2 - v2] != v3);\n }\n } while (v2 > 1 || v4);\n}" + }, + { + "index": 71, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int *nums, int size) {\n float shrink_fact = 1.3;\n int gaps = size;\n int swapped = 1;\n int i = 0;\n while (gaps > 1 || swapped) {\n gaps = (int)((float)gaps / shrink_fact);\n swapped = 0;\n i = 0;\n while (gaps + i < size) {\n if (nums[i] > nums[i + gaps]) {\n int temp = nums[i];\n nums[i] = nums[i + gaps];\n nums[i + gaps] = temp;\n swapped = 1;\n }\n i++;\n }\n }\n}", + "test": "int main() {\n\n int arr1[] = {5, 15, 37, 25, 79};\n\n int arr2[] = {41, 32, 15, 19, 22};\n\n int arr3[] = {99, 15, 13, 47};\n\n func0(arr1, 5);\n\n func0(arr2, 5);\n\n func0(arr3, 4);\n\n assert(arr1[0] == 5 && arr1[1] == 15 && arr1[2] == 25 && arr1[3] == 37 && arr1[4] == 79);\n\n assert(arr2[0] == 15 && arr2[1] == 19 && arr2[2] == 22 && arr2[3] == 32 && arr2[4] == 41);\n\n assert(arr3[0] == 13 && arr3[1] == 15 && arr3[2] == 47 && arr3[3] == 99);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nmovss 0xe64(%rip),%xmm1\npush %rbp\nmov %esi,%r9d\nlea -0x1(%rsi),%ebp\npush %rbx\nlea 0x4(%rdi),%rbx\nnopl 0x0(%rax,%rax,1)\npxor %xmm0,%xmm0\ncvtsi2ss %r9d,%xmm0\ndivss %xmm1,%xmm0\ncvttss2si %xmm0,%r9d\ncmp %r9d,%esi\njle 1358 \nmov %ebp,%edx\nmov %rdi,%rax\nxor %r11d,%r11d\nmovslq %r9d,%r8\nsub %r9d,%edx\nlea (%rbx,%rdx,4),%r10\nnopl 0x0(%rax)\nmov (%rax),%edx\nmov (%rax,%r8,4),%ecx\ncmp %ecx,%edx\njle 1336 \nmov %ecx,(%rax)\nmov $0x1,%r11d\nmov %edx,(%rax,%r8,4)\nadd $0x4,%rax\ncmp %rax,%r10\njne 1320 \nand $0x1,%r11d\ncmp $0x1,%r9d\njg 12f0 \ntest %r11b,%r11b\njne 12f0 \npop %rbx\npop %rbp\nretq\nnopl 0x0(%rax)\nxor %r11d,%r11d\njmp 1343 \nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\nmovss xmm1, cs:dword_2004\nmov r11d, esi\nnop\nloc_12D0:\npxor xmm0, xmm0\ncvtsi2ss xmm0, r11d\ndivss xmm0, xmm1\ncvttss2si r11d, xmm0\ncmp esi, r11d\njle short loc_1330\nmov edx, esi\nmov rax, rdi\nxor r10d, r10d\nmovsxd r8, r11d\nsub edx, r11d\nlea r9, [rdi+rdx*4]\nnop dword ptr [rax+00000000h]\nloc_1300:\nmov edx, [rax]\nmov ecx, [rax+r8*4]\ncmp edx, ecx\njle short loc_1316\nmov [rax], ecx\nmov r10d, 1\nmov [rax+r8*4], edx\nloc_1316:\nadd rax, 4\ncmp r9, rax\njnz short loc_1300\nand r10d, 1\nloc_1323:\ncmp r11d, 1\njg short loc_12D0\ntest r10b, r10b\njnz short loc_12D0\nretn\nloc_1330:\nxor r10d, r10d\njmp short loc_1323", + "ida_pseudo": "void __fastcall func0(int *a1, int a2)\n{\n int v2; // r11d\n int *v3; // rax\n char v4; // r10\n int v5; // edx\n int v6; // ecx\n\n v2 = a2;\n do\n {\n v2 = (int)(float)((float)v2 / 1.3);\n if ( a2 <= v2 )\n {\n v4 = 0;\n }\n else\n {\n v3 = a1;\n v4 = 0;\n do\n {\n v5 = *v3;\n v6 = v3[v2];\n if ( *v3 > v6 )\n {\n *v3 = v6;\n v4 = 1;\n v3[v2] = v5;\n }\n ++v3;\n }\n while ( &a1[a2 - v2] != v3 );\n }\n }\n while ( v2 > 1 || v4 );\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\nmovss xmm1, cs:dword_2004\nmov r11d, esi\nnop\nloc_12D0:\npxor xmm0, xmm0\ncvtsi2ss xmm0, r11d\ndivss xmm0, xmm1\ncvttss2si r11d, xmm0\ncmp esi, r11d\njle short loc_1330\nmov edx, esi\nmov rax, rdi\nxor r10d, r10d\nmovsxd r8, r11d\nsub edx, r11d\nlea r9, [rdi+rdx*4]\nnop dword ptr [rax+00000000h]\nloc_1300:\nmov edx, [rax]\nmov ecx, [rax+r8*4]\ncmp edx, ecx\njle short loc_1316\nmov [rax], ecx\nmov r10d, 1\nmov [rax+r8*4], edx\nloc_1316:\nadd rax, 4\ncmp r9, rax\njnz short loc_1300\nand r10d, 1\nloc_1323:\ncmp r11d, 1\njg short loc_12D0\ntest r10b, r10b\njnz short loc_12D0\nretn\nloc_1330:\nxor r10d, r10d\njmp short loc_1323", + "ida_strip_pseudo": "void __fastcall sub_12C0(int *a1, int a2)\n{\n int v2; // r11d\n int *v3; // rax\n char v4; // r10\n int v5; // edx\n int v6; // ecx\n\n v2 = a2;\n do\n {\n v2 = (int)(float)((float)v2 / 1.3);\n if ( a2 <= v2 )\n {\n v4 = 0;\n }\n else\n {\n v3 = a1;\n v4 = 0;\n do\n {\n v5 = *v3;\n v6 = v3[v2];\n if ( *v3 > v6 )\n {\n *v3 = v6;\n v4 = 1;\n v3[v2] = v5;\n }\n ++v3;\n }\n while ( &a1[a2 - v2] != v3 );\n }\n }\n while ( v2 > 1 || v4 );\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_12C0(int *a1, int a2) {\n int v2;\n int *v3;\n char v4;\n int v5;\n int v6;\n v2 = a2;\n do {\n v2 = (int)(float)((float)v2 / 1.3);\n if (a2 <= v2) {\n v4 = 0;\n } else {\n v3 = a1;\n v4 = 0;\n do {\n v5 = *v3;\n v6 = v3[v2];\n if (*v3 > v6) {\n *v3 = v6;\n v4 = 1;\n v3[v2] = v5;\n }\n ++v3;\n } while (&a1[a2 - v2] != v3);\n }\n } while (v2 > 1 || v4);\n}", + "ida_pseudo_norm": "void func0(int *a1, int a2) {\n int v2;\n int *v3;\n char v4;\n int v5;\n int v6;\n v2 = a2;\n do {\n v2 = (int)(float)((float)v2 / 1.3);\n if (a2 <= v2) {\n v4 = 0;\n } else {\n v3 = a1;\n v4 = 0;\n do {\n v5 = *v3;\n v6 = v3[v2];\n if (*v3 > v6) {\n *v3 = v6;\n v4 = 1;\n v3[v2] = v5;\n }\n ++v3;\n } while (&a1[a2 - v2] != v3);\n }\n } while (v2 > 1 || v4);\n}" + }, + { + "index": 72, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int n) {\n if (n % 4 != 2) {\n return true;\n }\n return false;\n}", + "test": "int main() {\n\n assert(func0(5) == true);\n\n assert(func0(10) == false);\n\n assert(func0(15) == true);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncltd\nshr $0x1e,%edx\nadd %edx,%eax\nand $0x3,%eax\nsub %edx,%eax\ncmp $0x2,%eax\nje 116e \nmov $0x1,%eax\njmp 1173 \nmov $0x0,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov edx, [rbp+var_4]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Eh\nadd edx, eax\nand edx, 3\nsub edx, eax\nmov eax, edx\ncmp eax, 2\njz short loc_1174\nmov eax, 1\njmp short loc_1179\nloc_1174:\nmov eax, 0\nloc_1179:\npop rbp\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(int a1)\n{\n return a1 % 4 != 2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov edx, [rbp+var_4]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Eh\nadd edx, eax\nand edx, 3\nsub edx, eax\nmov eax, edx\ncmp eax, 2\njz short loc_1174\nmov eax, 1\njmp short loc_1179\nloc_1174:\nmov eax, 0\nloc_1179:\npop rbp\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1149(int a1)\n{\n return a1 % 4 != 2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1149(int a1) { return a1 % 4 != 2; }", + "ida_pseudo_norm": "uint8_t func0(int a1) { return a1 % 4 != 2; }" + }, + { + "index": 73, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char** tokens;\n\n int count;\n\n} split_result;\n\n\n\n", + "func": "split_result func0(const char* text) {\n split_result result;\n result.tokens = NULL;\n result.count = 0;\n const char* delimiters[] = {\"; \", \", \", \"*\", \"\\n\"};\n int num_delimiters = 4;\n char* temp = strdup(text);\n char* ptr = temp;\n char* match;\n int min_index;\n while (*ptr) {\n min_index = -1;\n size_t min_pos = strlen(ptr);\n for (int i = 0; i < num_delimiters; i++) {\n char* found = strstr(ptr, delimiters[i]);\n if (found && (found - ptr) < min_pos) {\n min_pos = found - ptr;\n min_index = i;\n }\n }\n if (min_index == -1) {\n result.tokens =\n realloc(result.tokens, sizeof(char*) * (result.count + 1));\n result.tokens[result.count++] = strdup(ptr);\n break;\n }\n if (min_pos > 0) {\n result.tokens =\n realloc(result.tokens, sizeof(char*) * (result.count + 1));\n char* token = strndup(ptr, min_pos);\n result.tokens[result.count++] = token;\n }\n ptr += min_pos + strlen(delimiters[min_index]);\n }\n free(temp);\n return result;\n}", + "test": "int main(){\n\n split_result res1 = func0(\"Forces of the \\ndarkness*are coming into the play.\");\n\n assert(res1.count == 3);\n\n assert(strcmp(res1.tokens[0], \"Forces of the \") == 0);\n\n assert(strcmp(res1.tokens[1], \"darkness\") == 0);\n\n assert(strcmp(res1.tokens[2], \"are coming into the play.\") == 0);\n\n for(int i=0;i\nmov %rax,-0x68(%rbp)\nmov -0x68(%rbp),%rax\nmov %rax,-0x78(%rbp)\njmpq 141d \nmovl $0xffffffff,-0x84(%rbp)\nmov -0x78(%rbp),%rax\nmov %rax,%rdi\ncallq 10e0 \nmov %rax,-0x70(%rbp)\nmovl $0x0,-0x80(%rbp)\njmp 133f \nmov -0x80(%rbp),%eax\ncltq\nmov -0x40(%rbp,%rax,8),%rdx\nmov -0x78(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1150 \nmov %rax,-0x58(%rbp)\ncmpq $0x0,-0x58(%rbp)\nje 133b \nmov -0x58(%rbp),%rax\nsub -0x78(%rbp),%rax\ncmp %rax,-0x70(%rbp)\njbe 133b \nmov -0x58(%rbp),%rax\nsub -0x78(%rbp),%rax\nmov %rax,-0x70(%rbp)\nmov -0x80(%rbp),%eax\nmov %eax,-0x84(%rbp)\naddl $0x1,-0x80(%rbp)\nmov -0x80(%rbp),%eax\ncmp -0x7c(%rbp),%eax\njl 12f4 \ncmpl $0xffffffff,-0x84(%rbp)\njne 139e \nmov -0x48(%rbp),%eax\nadd $0x1,%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x50(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1130 \nmov %rax,-0x50(%rbp)\nmov -0x50(%rbp),%rcx\nmov -0x48(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x48(%rbp)\ncltq\nshl $0x3,%rax\nlea (%rcx,%rax,1),%rbx\nmov -0x78(%rbp),%rax\nmov %rax,%rdi\ncallq 1140 \nmov %rax,(%rbx)\njmpq 142c \ncmpq $0x0,-0x70(%rbp)\nje 13fd \nmov -0x48(%rbp),%eax\nadd $0x1,%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x50(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1130 \nmov %rax,-0x50(%rbp)\nmov -0x70(%rbp),%rdx\nmov -0x78(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1110 \nmov %rax,-0x60(%rbp)\nmov -0x50(%rbp),%rcx\nmov -0x48(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x48(%rbp)\ncltq\nshl $0x3,%rax\nlea (%rcx,%rax,1),%rdx\nmov -0x60(%rbp),%rax\nmov %rax,(%rdx)\nmov -0x84(%rbp),%eax\ncltq\nmov -0x40(%rbp,%rax,8),%rax\nmov %rax,%rdi\ncallq 10e0 \nmov -0x70(%rbp),%rdx\nadd %rdx,%rax\nadd %rax,-0x78(%rbp)\nmov -0x78(%rbp),%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 12d1 \nmov -0x68(%rbp),%rax\nmov %rax,%rdi\ncallq 10d0 \nmov -0x50(%rbp),%rax\nmov -0x48(%rbp),%rdx\nmov -0x18(%rbp),%rbx\nxor %fs:0x28,%rbx\nje 1454 \ncallq 10f0 <__stack_chk_fail@plt>\nadd $0x98,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 98h\nmov [rbp+s], rdi\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov [rbp+ptr], 0\nmov dword ptr [rbp+var_48], 0\nlea rax, unk_2008\nmov [rbp+needle], rax\nlea rax, unk_200B\nmov [rbp+var_38], rax\nlea rax, unk_200E\nmov [rbp+var_30], rax\nlea rax, unk_2010\nmov [rbp+var_28], rax\nmov [rbp+var_7C], 4\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strdup\nmov [rbp+var_68], rax\nmov rax, [rbp+var_68]\nmov [rbp+haystack], rax\njmp loc_141D\nloc_12D1:\nmov [rbp+var_84], 0FFFFFFFFh\nmov rax, [rbp+haystack]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+n], rax\nmov [rbp+var_80], 0\njmp short loc_133F\nloc_12F4:\nmov eax, [rbp+var_80]\ncdqe\nmov rdx, [rbp+rax*8+needle]\nmov rax, [rbp+haystack]\nmov rsi, rdx; needle\nmov rdi, rax; haystack\ncall _strstr\nmov [rbp+var_58], rax\ncmp [rbp+var_58], 0\njz short loc_133B\nmov rax, [rbp+var_58]\nsub rax, [rbp+haystack]\ncmp rax, [rbp+n]\njnb short loc_133B\nmov rax, [rbp+var_58]\nsub rax, [rbp+haystack]\nmov [rbp+n], rax\nmov eax, [rbp+var_80]\nmov [rbp+var_84], eax\nloc_133B:\nadd [rbp+var_80], 1\nloc_133F:\nmov eax, [rbp+var_80]\ncmp eax, [rbp+var_7C]\njl short loc_12F4\ncmp [rbp+var_84], 0FFFFFFFFh\njnz short loc_139E\nmov eax, dword ptr [rbp+var_48]\nadd eax, 1\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nmov rsi, rdx; size\nmov rdi, rax; ptr\ncall _realloc\nmov [rbp+ptr], rax\nmov rcx, [rbp+ptr]\nmov eax, dword ptr [rbp+var_48]\nlea edx, [rax+1]\nmov dword ptr [rbp+var_48], edx\ncdqe\nshl rax, 3\nlea rbx, [rcx+rax]\nmov rax, [rbp+haystack]\nmov rdi, rax; s\ncall _strdup\nmov [rbx], rax\njmp loc_142C\nloc_139E:\ncmp [rbp+n], 0\njz short loc_13FD\nmov eax, dword ptr [rbp+var_48]\nadd eax, 1\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nmov rsi, rdx; size\nmov rdi, rax; ptr\ncall _realloc\nmov [rbp+ptr], rax\nmov rdx, [rbp+n]\nmov rax, [rbp+haystack]\nmov rsi, rdx; n\nmov rdi, rax; string\ncall _strndup\nmov [rbp+var_60], rax\nmov rcx, [rbp+ptr]\nmov eax, dword ptr [rbp+var_48]\nlea edx, [rax+1]\nmov dword ptr [rbp+var_48], edx\ncdqe\nshl rax, 3\nlea rdx, [rcx+rax]\nmov rax, [rbp+var_60]\nmov [rdx], rax\nloc_13FD:\nmov eax, [rbp+var_84]\ncdqe\nmov rax, [rbp+rax*8+needle]\nmov rdi, rax; s\ncall _strlen\nmov rdx, [rbp+n]\nadd rax, rdx\nadd [rbp+haystack], rax\nloc_141D:\nmov rax, [rbp+haystack]\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_12D1\nloc_142C:\nmov rax, [rbp+var_68]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+ptr]\nmov rdx, [rbp+var_48]\nmov rcx, [rbp+var_18]\nsub rcx, fs:28h\njz short loc_1454\ncall ___stack_chk_fail\nloc_1454:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "void *__fastcall func0(const char *a1)\n{\n int v1; // eax\n int v3; // [rsp+1Ch] [rbp-84h]\n int i; // [rsp+20h] [rbp-80h]\n char *haystack; // [rsp+28h] [rbp-78h]\n size_t n; // [rsp+30h] [rbp-70h]\n char *v7; // [rsp+38h] [rbp-68h]\n char *v8; // [rsp+40h] [rbp-60h]\n char *v9; // [rsp+48h] [rbp-58h]\n void *ptr; // [rsp+50h] [rbp-50h]\n int v11; // [rsp+58h] [rbp-48h]\n char *needle[7]; // [rsp+60h] [rbp-40h]\n\n needle[5] = (char *)__readfsqword(0x28u);\n ptr = 0LL;\n v11 = 0;\n needle[0] = (char *)&unk_2008;\n needle[1] = (char *)&unk_200B;\n needle[2] = (char *)&unk_200E;\n needle[3] = (char *)&unk_2010;\n v7 = strdup(a1);\n for ( haystack = v7; *haystack; haystack += n + strlen(needle[v3]) )\n {\n v3 = -1;\n n = strlen(haystack);\n for ( i = 0; i < 4; ++i )\n {\n v9 = strstr(haystack, needle[i]);\n if ( v9 && v9 - haystack < n )\n {\n n = v9 - haystack;\n v3 = i;\n }\n }\n if ( v3 == -1 )\n {\n ptr = realloc(ptr, 8LL * (v11 + 1));\n *((_QWORD *)ptr + v11) = strdup(haystack);\n break;\n }\n if ( n )\n {\n ptr = realloc(ptr, 8LL * (v11 + 1));\n v8 = strndup(haystack, n);\n v1 = v11++;\n *((_QWORD *)ptr + v1) = v8;\n }\n }\n free(v7);\n return ptr;\n}", + "ida_strip_asm": "sub_1249:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 98h\nmov [rbp+s], rdi\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov [rbp+ptr], 0\nmov dword ptr [rbp+var_48], 0\nlea rax, unk_2008\nmov [rbp+needle], rax\nlea rax, unk_200B\nmov [rbp+var_38], rax\nlea rax, unk_200E\nmov [rbp+var_30], rax\nlea rax, unk_2010\nmov [rbp+var_28], rax\nmov [rbp+var_7C], 4\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strdup\nmov [rbp+var_68], rax\nmov rax, [rbp+var_68]\nmov [rbp+haystack], rax\njmp loc_141D\nloc_12D1:\nmov [rbp+var_84], 0FFFFFFFFh\nmov rax, [rbp+haystack]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+n], rax\nmov [rbp+var_80], 0\njmp short loc_133F\nloc_12F4:\nmov eax, [rbp+var_80]\ncdqe\nmov rdx, [rbp+rax*8+needle]\nmov rax, [rbp+haystack]\nmov rsi, rdx; needle\nmov rdi, rax; haystack\ncall _strstr\nmov [rbp+var_58], rax\ncmp [rbp+var_58], 0\njz short loc_133B\nmov rax, [rbp+var_58]\nsub rax, [rbp+haystack]\ncmp rax, [rbp+n]\njnb short loc_133B\nmov rax, [rbp+var_58]\nsub rax, [rbp+haystack]\nmov [rbp+n], rax\nmov eax, [rbp+var_80]\nmov [rbp+var_84], eax\nloc_133B:\nadd [rbp+var_80], 1\nloc_133F:\nmov eax, [rbp+var_80]\ncmp eax, [rbp+var_7C]\njl short loc_12F4\ncmp [rbp+var_84], 0FFFFFFFFh\njnz short loc_139E\nmov eax, dword ptr [rbp+var_48]\nadd eax, 1\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nmov rsi, rdx; size\nmov rdi, rax; ptr\ncall _realloc\nmov [rbp+ptr], rax\nmov rcx, [rbp+ptr]\nmov eax, dword ptr [rbp+var_48]\nlea edx, [rax+1]\nmov dword ptr [rbp+var_48], edx\ncdqe\nshl rax, 3\nlea rbx, [rcx+rax]\nmov rax, [rbp+haystack]\nmov rdi, rax; s\ncall _strdup\nmov [rbx], rax\njmp loc_142C\nloc_139E:\ncmp [rbp+n], 0\njz short loc_13FD\nmov eax, dword ptr [rbp+var_48]\nadd eax, 1\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nmov rsi, rdx; size\nmov rdi, rax; ptr\ncall _realloc\nmov [rbp+ptr], rax\nmov rdx, [rbp+n]\nmov rax, [rbp+haystack]\nmov rsi, rdx; n\nmov rdi, rax; string\ncall _strndup\nmov [rbp+var_60], rax\nmov rcx, [rbp+ptr]\nmov eax, dword ptr [rbp+var_48]\nlea edx, [rax+1]\nmov dword ptr [rbp+var_48], edx\ncdqe\nshl rax, 3\nlea rdx, [rcx+rax]\nmov rax, [rbp+var_60]\nmov [rdx], rax\nloc_13FD:\nmov eax, [rbp+var_84]\ncdqe\nmov rax, [rbp+rax*8+needle]\nmov rdi, rax; s\ncall _strlen\nmov rdx, [rbp+n]\nadd rax, rdx\nadd [rbp+haystack], rax\nloc_141D:\nmov rax, [rbp+haystack]\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_12D1\nloc_142C:\nmov rax, [rbp+var_68]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+ptr]\nmov rdx, [rbp+var_48]\nmov rcx, [rbp+var_18]\nsub rcx, fs:28h\njz short loc_1454\ncall ___stack_chk_fail\nloc_1454:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "void *__fastcall sub_1249(const char *a1)\n{\n int v1; // eax\n int v3; // [rsp+1Ch] [rbp-84h]\n int i; // [rsp+20h] [rbp-80h]\n char *haystack; // [rsp+28h] [rbp-78h]\n size_t n; // [rsp+30h] [rbp-70h]\n char *v7; // [rsp+38h] [rbp-68h]\n char *v8; // [rsp+40h] [rbp-60h]\n char *v9; // [rsp+48h] [rbp-58h]\n void *ptr; // [rsp+50h] [rbp-50h]\n int v11; // [rsp+58h] [rbp-48h]\n char *needle[7]; // [rsp+60h] [rbp-40h]\n\n needle[5] = (char *)__readfsqword(0x28u);\n ptr = 0LL;\n v11 = 0;\n needle[0] = (char *)&unk_2008;\n needle[1] = (char *)&unk_200B;\n needle[2] = (char *)&unk_200E;\n needle[3] = (char *)&unk_2010;\n v7 = strdup(a1);\n for ( haystack = v7; *haystack; haystack += n + strlen(needle[v3]) )\n {\n v3 = -1;\n n = strlen(haystack);\n for ( i = 0; i < 4; ++i )\n {\n v9 = strstr(haystack, needle[i]);\n if ( v9 && v9 - haystack < n )\n {\n n = v9 - haystack;\n v3 = i;\n }\n }\n if ( v3 == -1 )\n {\n ptr = realloc(ptr, 8LL * (v11 + 1));\n *((_QWORD *)ptr + v11) = strdup(haystack);\n break;\n }\n if ( n )\n {\n ptr = realloc(ptr, 8LL * (v11 + 1));\n v8 = strndup(haystack, n);\n v1 = v11++;\n *((_QWORD *)ptr + v1) = v8;\n }\n }\n free(v7);\n return ptr;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1249(const char *a1) {\n int v1;\n int v3;\n int i;\n char *haystack;\n unsigned int n;\n char *v7;\n char *v8;\n char *v9;\n void *ptr;\n int v11;\n char *needle[7];\n needle[5] = (char *)__readfsqword(40u);\n ptr = 0LL;\n v11 = 0;\n needle[0] = (char *)&unk_2008;\n needle[1] = (char *)&unk_200B;\n needle[2] = (char *)&unk_200E;\n needle[3] = (char *)&unk_2010;\n v7 = strdup(a1);\n for (haystack = v7; *haystack; haystack += n + strlen(needle[v3])) {\n v3 = -1;\n n = strlen(haystack);\n for (i = 0; i < 4; ++i) {\n v9 = strstr(haystack, needle[i]);\n if (v9 && v9 - haystack < n) {\n n = v9 - haystack;\n v3 = i;\n }\n }\n if (v3 == -1) {\n ptr = realloc(ptr, 8LL * (v11 + 1));\n *((uint64_t *)ptr + v11) = strdup(haystack);\n break;\n }\n if (n) {\n ptr = realloc(ptr, 8LL * (v11 + 1));\n v8 = strndup(haystack, n);\n v1 = v11++;\n *((uint64_t *)ptr + v1) = v8;\n }\n }\n free(v7);\n return ptr;\n}", + "ida_pseudo_norm": "void *func0(const char *a1) {\n int v1;\n int v3;\n int i;\n char *haystack;\n unsigned int n;\n char *v7;\n char *v8;\n char *v9;\n void *ptr;\n int v11;\n char *needle[7];\n needle[5] = (char *)__readfsqword(40u);\n ptr = 0LL;\n v11 = 0;\n needle[0] = (char *)&unk_2008;\n needle[1] = (char *)&unk_200B;\n needle[2] = (char *)&unk_200E;\n needle[3] = (char *)&unk_2010;\n v7 = strdup(a1);\n for (haystack = v7; *haystack; haystack += n + strlen(needle[v3])) {\n v3 = -1;\n n = strlen(haystack);\n for (i = 0; i < 4; ++i) {\n v9 = strstr(haystack, needle[i]);\n if (v9 && v9 - haystack < n) {\n n = v9 - haystack;\n v3 = i;\n }\n }\n if (v3 == -1) {\n ptr = realloc(ptr, 8LL * (v11 + 1));\n *((uint64_t *)ptr + v11) = strdup(haystack);\n break;\n }\n if (n) {\n ptr = realloc(ptr, 8LL * (v11 + 1));\n v8 = strndup(haystack, n);\n v1 = v11++;\n *((uint64_t *)ptr + v1) = v8;\n }\n }\n free(v7);\n return ptr;\n}" + }, + { + "index": 73, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char** tokens;\n\n int count;\n\n} split_result;\n\n\n\n", + "func": "split_result func0(const char* text) {\n split_result result;\n result.tokens = NULL;\n result.count = 0;\n const char* delimiters[] = {\"; \", \", \", \"*\", \"\\n\"};\n int num_delimiters = 4;\n char* temp = strdup(text);\n char* ptr = temp;\n char* match;\n int min_index;\n while (*ptr) {\n min_index = -1;\n size_t min_pos = strlen(ptr);\n for (int i = 0; i < num_delimiters; i++) {\n char* found = strstr(ptr, delimiters[i]);\n if (found && (found - ptr) < min_pos) {\n min_pos = found - ptr;\n min_index = i;\n }\n }\n if (min_index == -1) {\n result.tokens =\n realloc(result.tokens, sizeof(char*) * (result.count + 1));\n result.tokens[result.count++] = strdup(ptr);\n break;\n }\n if (min_pos > 0) {\n result.tokens =\n realloc(result.tokens, sizeof(char*) * (result.count + 1));\n char* token = strndup(ptr, min_pos);\n result.tokens[result.count++] = token;\n }\n ptr += min_pos + strlen(delimiters[min_index]);\n }\n free(temp);\n return result;\n}", + "test": "int main(){\n\n split_result res1 = func0(\"Forces of the \\ndarkness*are coming into the play.\");\n\n assert(res1.count == 3);\n\n assert(strcmp(res1.tokens[0], \"Forces of the \") == 0);\n\n assert(strcmp(res1.tokens[1], \"darkness\") == 0);\n\n assert(strcmp(res1.tokens[2], \"are coming into the play.\") == 0);\n\n for(int i=0;i\nmov %rax,0x18(%rsp)\ncmpb $0x0,(%rax)\nje 13af \nmov %rax,%r12\nmovq $0x0,0x10(%rsp)\nmovl $0x0,0xc(%rsp)\nmov $0xffffffffffffffff,%r15\njmp 12ed \nadd $0x1,%rbx\ncmp $0x4,%rbx\nje 12b7 \nmov 0x20(%rsp,%rbx,8),%rsi\nmov %r12,%rdi\ncallq 1110 \ntest %rax,%rax\nje 128b \nsub %r12,%rax\ncmp %rbp,%rax\njae 128b \nmov %rax,%rbp\nmov %ebx,%r13d\njmp 128b \ncmp $0xffffffff,%r13d\nje 1311 \ntest %rbp,%rbp\njne 1375 \nmovslq %r13d,%r13\nmov 0x20(%rsp,%r13,8),%rdi\nmov $0x0,%eax\nmov %r15,%rcx\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rbp,%rax,1),%rax\nadd %rax,%r12\ncmpb $0x0,(%r12)\nje 1343 \nmov $0x0,%eax\nmov %r15,%rcx\nmov %r12,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rbp\nmov $0x0,%ebx\nmov $0xffffffff,%r13d\njmp 1295 \naddl $0x1,0xc(%rsp)\nmov 0xc(%rsp),%eax\nmovslq %eax,%rbx\nshl $0x3,%rbx\nmov %rbx,%rsi\nmov 0x10(%rsp),%rdi\ncallq 10f0 \nmov %rax,%r15\nmov %rax,0x10(%rsp)\nmov %r12,%rdi\ncallq 1100 \nmov %rax,-0x8(%r15,%rbx,1)\nmov 0x18(%rsp),%rdi\ncallq 10b0 \nmov 0xc(%rsp),%edx\nmov 0x48(%rsp),%rax\nxor %fs:0x28,%rax\njne 13c2 \nmov 0x10(%rsp),%rax\nadd $0x58,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\naddl $0x1,0xc(%rsp)\nmov 0xc(%rsp),%eax\nmovslq %eax,%rbx\nshl $0x3,%rbx\nmov %rbx,%rsi\nmov 0x10(%rsp),%rdi\ncallq 10f0 \nmov %rax,%r14\nmov %rax,0x10(%rsp)\nmov %rbp,%rsi\nmov %r12,%rdi\ncallq 10e0 \nmov %rax,-0x8(%r14,%rbx,1)\njmpq 12c6 \nmovl $0x0,0xc(%rsp)\nmovq $0x0,0x10(%rsp)\njmp 1343 \ncallq 10c0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 48h\nmov rax, fs:28h\nmov [rsp+78h+var_40], rax\nxor eax, eax\nlea rax, unk_2004\nmov [rsp+78h+needle], rax\nlea rax, unk_2007\nmov [rsp+78h+var_60], rax\nlea rax, unk_200A\nmov [rsp+78h+var_58], rax\nlea rax, unk_200C\nmov [rsp+78h+var_50], rax\ncall _strdup\nmov [rsp+78h+ptr], rax\ncmp byte ptr [rax], 0\njz loc_13AF\nmov r12, rax\nmov r14d, 0\nmov r15d, 0\njmp short loc_1314\nloc_12BF:\nsub rax, r12\ncmp rax, rbp\ncmovb r13d, ebx\ncmovb rbp, rax\nloc_12CD:\nadd rbx, 1\ncmp rbx, 4\njz short loc_12EB\nloc_12D7:\nmov rsi, [rsp+rbx*8+78h+needle]; needle\nmov rdi, r12; haystack\ncall _strstr\ntest rax, rax\njnz short loc_12BF\njmp short loc_12CD\nloc_12EB:\ncmp r13d, 0FFFFFFFFh\njz short loc_132C\ntest rbp, rbp\njnz loc_1381\nloc_12FA:\nmovsxd r13, r13d\nmov rdi, [rsp+r13*8+78h+needle]; s\ncall _strlen\nadd rax, rbp\nadd r12, rax\ncmp byte ptr [r12], 0\njz short loc_1352\nloc_1314:\nmov rdi, r12; s\ncall _strlen\nmov rbp, rax\nmov ebx, 0\nmov r13d, 0FFFFFFFFh\njmp short loc_12D7\nloc_132C:\nadd r15d, 1\nmovsxd rbx, r15d\nshl rbx, 3\nmov rsi, rbx; size\nmov rdi, r14; ptr\ncall _realloc\nmov r14, rax\nmov rdi, r12; s\ncall _strdup\nmov [r14+rbx-8], rax\nloc_1352:\nmov rdi, [rsp+78h+ptr]; ptr\ncall _free\nmov edx, r15d\nmov rax, [rsp+78h+var_40]\nsub rax, fs:28h\njnz short loc_13BD\nmov rax, r14\nadd rsp, 48h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1381:\nadd r15d, 1\nmovsxd rbx, r15d\nshl rbx, 3\nmov rsi, rbx; size\nmov rdi, r14; ptr\ncall _realloc\nmov r14, rax\nmov rsi, rbp; n\nmov rdi, r12; string\ncall _strndup\nmov [r14+rbx-8], rax\njmp loc_12FA\nloc_13AF:\nmov r15d, 0\nmov r14d, 0\njmp short loc_1352\nloc_13BD:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(const char *a1)\n{\n char *v1; // rax\n const char *v2; // r12\n char *v3; // r14\n int v4; // r15d\n unsigned __int64 v5; // rax\n int v6; // r13d\n size_t v7; // rbp\n __int64 v8; // rbx\n char *v9; // rax\n size_t v10; // rbx\n char *ptr; // [rsp+8h] [rbp-70h]\n char *needle[13]; // [rsp+10h] [rbp-68h]\n\n needle[5] = (char *)__readfsqword(0x28u);\n needle[0] = (char *)&unk_2004;\n needle[1] = (char *)&unk_2007;\n needle[2] = (char *)&unk_200A;\n needle[3] = (char *)&unk_200C;\n v1 = strdup(a1);\n ptr = v1;\n if ( *v1 )\n {\n v2 = v1;\n v3 = 0LL;\n v4 = 0;\n while ( 1 )\n {\n v7 = strlen(v2);\n v8 = 0LL;\n v6 = -1;\n do\n {\n v9 = strstr(v2, needle[v8]);\n if ( v9 )\n {\n v5 = v9 - v2;\n if ( v5 < v7 )\n {\n v6 = v8;\n v7 = v5;\n }\n }\n ++v8;\n }\n while ( v8 != 4 );\n if ( v6 == -1 )\n break;\n if ( v7 )\n {\n v3 = (char *)realloc(v3, 8LL * ++v4);\n *(_QWORD *)&v3[8 * v4 - 8] = strndup(v2, v7);\n }\n v2 += v7 + strlen(needle[v6]);\n if ( !*v2 )\n goto LABEL_14;\n }\n v10 = 8LL * (v4 + 1);\n v3 = (char *)realloc(v3, v10);\n *(_QWORD *)&v3[v10 - 8] = strdup(v2);\n }\n else\n {\n v3 = 0LL;\n }\nLABEL_14:\n free(ptr);\n return v3;\n}", + "ida_strip_asm": "sub_1249:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 48h\nmov rax, fs:28h\nmov [rsp+78h+var_40], rax\nxor eax, eax\nlea rax, unk_2004\nmov [rsp+78h+needle], rax\nlea rax, unk_2007\nmov [rsp+78h+var_60], rax\nlea rax, unk_200A\nmov [rsp+78h+var_58], rax\nlea rax, unk_200C\nmov [rsp+78h+var_50], rax\ncall _strdup\nmov [rsp+78h+ptr], rax\ncmp byte ptr [rax], 0\njz loc_13AF\nmov r12, rax\nmov r14d, 0\nmov r15d, 0\njmp short loc_1314\nloc_12BF:\nsub rax, r12\ncmp rax, rbp\ncmovb r13d, ebx\ncmovb rbp, rax\nloc_12CD:\nadd rbx, 1\ncmp rbx, 4\njz short loc_12EB\nloc_12D7:\nmov rsi, [rsp+rbx*8+78h+needle]; needle\nmov rdi, r12; haystack\ncall _strstr\ntest rax, rax\njnz short loc_12BF\njmp short loc_12CD\nloc_12EB:\ncmp r13d, 0FFFFFFFFh\njz short loc_132C\ntest rbp, rbp\njnz loc_1381\nloc_12FA:\nmovsxd r13, r13d\nmov rdi, [rsp+r13*8+78h+needle]; s\ncall _strlen\nadd rax, rbp\nadd r12, rax\ncmp byte ptr [r12], 0\njz short loc_1352\nloc_1314:\nmov rdi, r12; s\ncall _strlen\nmov rbp, rax\nmov ebx, 0\nmov r13d, 0FFFFFFFFh\njmp short loc_12D7\nloc_132C:\nadd r15d, 1\nmovsxd rbx, r15d\nshl rbx, 3\nmov rsi, rbx; size\nmov rdi, r14; ptr\ncall _realloc\nmov r14, rax\nmov rdi, r12; s\ncall _strdup\nmov [r14+rbx-8], rax\nloc_1352:\nmov rdi, [rsp+78h+ptr]; ptr\ncall _free\nmov edx, r15d\nmov rax, [rsp+78h+var_40]\nsub rax, fs:28h\njnz short loc_13BD\nmov rax, r14\nadd rsp, 48h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1381:\nadd r15d, 1\nmovsxd rbx, r15d\nshl rbx, 3\nmov rsi, rbx; size\nmov rdi, r14; ptr\ncall _realloc\nmov r14, rax\nmov rsi, rbp; n\nmov rdi, r12; string\ncall _strndup\nmov [r14+rbx-8], rax\njmp loc_12FA\nloc_13AF:\nmov r15d, 0\nmov r14d, 0\njmp short loc_1352\nloc_13BD:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_1249(const char *a1)\n{\n char *v1; // rax\n const char *v2; // r12\n char *v3; // r14\n int v4; // r15d\n unsigned __int64 v5; // rax\n int v6; // r13d\n size_t v7; // rbp\n __int64 v8; // rbx\n char *v9; // rax\n size_t v10; // rbx\n char *ptr; // [rsp+8h] [rbp-70h]\n char *needle[13]; // [rsp+10h] [rbp-68h]\n\n needle[5] = (char *)__readfsqword(0x28u);\n needle[0] = (char *)&unk_2004;\n needle[1] = (char *)&unk_2007;\n needle[2] = (char *)&unk_200A;\n needle[3] = (char *)&unk_200C;\n v1 = strdup(a1);\n ptr = v1;\n if ( *v1 )\n {\n v2 = v1;\n v3 = 0LL;\n v4 = 0;\n while ( 1 )\n {\n v7 = strlen(v2);\n v8 = 0LL;\n v6 = -1;\n do\n {\n v9 = strstr(v2, needle[v8]);\n if ( v9 )\n {\n v5 = v9 - v2;\n if ( v5 < v7 )\n {\n v6 = v8;\n v7 = v5;\n }\n }\n ++v8;\n }\n while ( v8 != 4 );\n if ( v6 == -1 )\n break;\n if ( v7 )\n {\n v3 = (char *)realloc(v3, 8LL * ++v4);\n *(_QWORD *)&v3[8 * v4 - 8] = strndup(v2, v7);\n }\n v2 += v7 + strlen(needle[v6]);\n if ( !*v2 )\n goto LABEL_14;\n }\n v10 = 8LL * (v4 + 1);\n v3 = (char *)realloc(v3, v10);\n *(_QWORD *)&v3[v10 - 8] = strdup(v2);\n }\n else\n {\n v3 = 0LL;\n }\nLABEL_14:\n free(ptr);\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1249(const char *a1) {\n char *v1;\n const char *v2;\n char *v3;\n int v4;\n unsigned long long v5;\n int v6;\n unsigned int v7;\n long long v8;\n char *v9;\n unsigned int v10;\n char *ptr;\n char *needle[13];\n needle[5] = (char *)__readfsqword(40u);\n needle[0] = (char *)&unk_2004;\n needle[1] = (char *)&unk_2007;\n needle[2] = (char *)&unk_200A;\n needle[3] = (char *)&unk_200C;\n v1 = strdup(a1);\n ptr = v1;\n if (*v1) {\n v2 = v1;\n v3 = 0LL;\n v4 = 0;\n while (1) {\n v7 = strlen(v2);\n v8 = 0LL;\n v6 = -1;\n do {\n v9 = strstr(v2, needle[v8]);\n if (v9) {\n v5 = v9 - v2;\n if (v5 < v7) {\n v6 = v8;\n v7 = v5;\n }\n }\n ++v8;\n } while (v8 != 4);\n if (v6 == -1) break;\n if (v7) {\n v3 = (char *)realloc(v3, 8LL * ++v4);\n *(uint64_t *)&v3[8 * v4 - 8] = strndup(v2, v7);\n }\n v2 += v7 + strlen(needle[v6]);\n if (!*v2) goto LABEL_14;\n }\n v10 = 8LL * (v4 + 1);\n v3 = (char *)realloc(v3, v10);\n *(uint64_t *)&v3[v10 - 8] = strdup(v2);\n } else {\n v3 = 0LL;\n }\nLABEL_14:\n free(ptr);\n return v3;\n}", + "ida_pseudo_norm": "char *func0(const char *a1) {\n char *v1;\n const char *v2;\n char *v3;\n int v4;\n unsigned long long v5;\n int v6;\n unsigned int v7;\n long long v8;\n char *v9;\n unsigned int v10;\n char *ptr;\n char *needle[13];\n needle[5] = (char *)__readfsqword(40u);\n needle[0] = (char *)&unk_2004;\n needle[1] = (char *)&unk_2007;\n needle[2] = (char *)&unk_200A;\n needle[3] = (char *)&unk_200C;\n v1 = strdup(a1);\n ptr = v1;\n if (*v1) {\n v2 = v1;\n v3 = 0LL;\n v4 = 0;\n while (1) {\n v7 = strlen(v2);\n v8 = 0LL;\n v6 = -1;\n do {\n v9 = strstr(v2, needle[v8]);\n if (v9) {\n v5 = v9 - v2;\n if (v5 < v7) {\n v6 = v8;\n v7 = v5;\n }\n }\n ++v8;\n } while (v8 != 4);\n if (v6 == -1) break;\n if (v7) {\n v3 = (char *)realloc(v3, 8LL * ++v4);\n *(uint64_t *)&v3[8 * v4 - 8] = strndup(v2, v7);\n }\n v2 += v7 + strlen(needle[v6]);\n if (!*v2) goto LABEL_14;\n }\n v10 = 8LL * (v4 + 1);\n v3 = (char *)realloc(v3, v10);\n *(uint64_t *)&v3[v10 - 8] = strdup(v2);\n } else {\n v3 = 0LL;\n }\nLABEL_14:\n free(ptr);\n return v3;\n}" + }, + { + "index": 73, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char** tokens;\n\n int count;\n\n} split_result;\n\n\n\n", + "func": "split_result func0(const char* text) {\n split_result result;\n result.tokens = NULL;\n result.count = 0;\n const char* delimiters[] = {\"; \", \", \", \"*\", \"\\n\"};\n int num_delimiters = 4;\n char* temp = strdup(text);\n char* ptr = temp;\n char* match;\n int min_index;\n while (*ptr) {\n min_index = -1;\n size_t min_pos = strlen(ptr);\n for (int i = 0; i < num_delimiters; i++) {\n char* found = strstr(ptr, delimiters[i]);\n if (found && (found - ptr) < min_pos) {\n min_pos = found - ptr;\n min_index = i;\n }\n }\n if (min_index == -1) {\n result.tokens =\n realloc(result.tokens, sizeof(char*) * (result.count + 1));\n result.tokens[result.count++] = strdup(ptr);\n break;\n }\n if (min_pos > 0) {\n result.tokens =\n realloc(result.tokens, sizeof(char*) * (result.count + 1));\n char* token = strndup(ptr, min_pos);\n result.tokens[result.count++] = token;\n }\n ptr += min_pos + strlen(delimiters[min_index]);\n }\n free(temp);\n return result;\n}", + "test": "int main(){\n\n split_result res1 = func0(\"Forces of the \\ndarkness*are coming into the play.\");\n\n assert(res1.count == 3);\n\n assert(strcmp(res1.tokens[0], \"Forces of the \") == 0);\n\n assert(strcmp(res1.tokens[1], \"darkness\") == 0);\n\n assert(strcmp(res1.tokens[2], \"are coming into the play.\") == 0);\n\n for(int i=0;i\ncmpb $0x0,(%rax)\nmov %rax,0x18(%rsp)\nje 170b \nmov %r14,0x8(%rsp)\nmov %rax,%r15\nxor %r12d,%r12d\nxor %r13d,%r13d\nnopl 0x0(%rax,%rax,1)\nmov %r15,%rdi\nxor %r14d,%r14d\nmov $0xffffffffffffffff,%rbp\ncallq 10d0 \nmov 0x8(%rsp),%rsi\nmov %r15,%rdi\nmov %rax,%rbx\ncallq 1130 \ntest %rax,%rax\nje 161d \nsub %r15,%rax\ncmp %rbx,%rax\njae 161d \nmov %rax,%rbx\nmovslq %r14d,%rbp\nadd $0x1,%r14\ncmp $0x4,%r14\nje 1643 \nmov 0x20(%rsp,%r14,8),%rsi\nmov %r15,%rdi\ncallq 1130 \ntest %rax,%rax\njne 160f \nadd $0x1,%r14\ncmp $0x4,%r14\njne 1627 \ncmp $0xffffffff,%ebp\nje 16e0 \ntest %rbx,%rbx\njne 16a0 \nmov 0x20(%rsp,%rbp,8),%rdi\ncallq 10d0 \nadd %rax,%rbx\nadd %rbx,%r15\ncmpb $0x0,(%r15)\njne 15e8 \nmov 0x18(%rsp),%rdi\ncallq 10c0 \nmov %r13d,%edx\nmov 0x48(%rsp),%rax\nxor %fs:0x28,%rax\njne 1716 \nadd $0x58,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw 0x0(%rax,%rax,1)\nadd $0x1,%r13d\nmov %r12,%rdi\nmovslq %r13d,%rdx\nshl $0x3,%rdx\nmov %rdx,%rsi\nmov %rdx,0x10(%rsp)\ncallq 1110 \nmov %rbx,%rsi\nmov %r15,%rdi\nmov %rax,%r12\ncallq 1100 \nmov 0x10(%rsp),%rdx\nmov %rax,-0x8(%r12,%rdx,1)\njmpq 1651 \nnopl 0x0(%rax,%rax,1)\nadd $0x1,%r13d\nmov %r12,%rdi\nmovslq %r13d,%rbx\nshl $0x3,%rbx\nmov %rbx,%rsi\ncallq 1110 \nmov %r15,%rdi\nmov %rax,%r12\ncallq 1120 \nmov %rax,-0x8(%r12,%rbx,1)\njmpq 1667 \nxor %r13d,%r13d\nxor %r12d,%r12d\njmpq 1667 \ncallq 10e0 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\nlea rcx, unk_2004\npush r14\nmovq xmm0, rcx\nlea rcx, unk_200A\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+88h+var_40], rax\nlea rax, unk_2007\nmovq xmm1, rax\nlea rax, unk_200C\npunpcklqdq xmm0, xmm1\nmovq xmm2, rax\nmovaps xmmword ptr [rsp+88h+s], xmm0\nmovq xmm0, rcx\npunpcklqdq xmm0, xmm2\nmovaps [rsp+88h+var_58], xmm0\ncall _strdup\ncmp byte ptr [rax], 0\nmov [rsp+88h+ptr], rax\njz loc_16FE\nmov [rsp+88h+var_7C], 0\nmov rbp, rax\nxor r14d, r14d\nlea r13, [rsp+88h+s]\nnop dword ptr [rax+rax+00000000h]\nloc_15F0:\nmov rdi, rbp; s\nxor r15d, r15d\nmov r12d, 0FFFFFFFFh\ncall _strlen\nmov rbx, rax\nloc_1604:\nmov rsi, [r13+r15*8+0]; needle\nmov rdi, rbp; haystack\ncall _strstr\ntest rax, rax\njz short loc_1624\nsub rax, rbp\ncmp rax, rbx\ncmovb r12d, r15d\ncmovb rbx, rax\nloc_1624:\nadd r15, 1\ncmp r15, 4\njnz short loc_1604\ncmp r12d, 0FFFFFFFFh\njz loc_16D0\ntest rbx, rbx\njnz short loc_1690\nloc_163D:\nmovsxd r12, r12d\nmov rdi, [rsp+r12*8+88h+s]; s\ncall _strlen\nadd rax, rbx\nadd rbp, rax\ncmp byte ptr [rbp+0], 0\njnz short loc_15F0\nloc_1656:\nmov rdi, [rsp+88h+ptr]; ptr\ncall _free\nmov edx, [rsp+88h+var_7C]\nmov rax, [rsp+88h+var_40]\nsub rax, fs:28h\njnz loc_170E\nadd rsp, 58h\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1690:\nadd [rsp+88h+var_7C], 1\nmovsxd rdx, [rsp+88h+var_7C]\nmov rdi, r14; ptr\nshl rdx, 3\nmov rsi, rdx; size\nmov [rsp+88h+var_78], rdx\ncall _realloc\nmov rsi, rbx; n\nmov rdi, rbp; string\nmov r14, rax\ncall _strndup\nmov rdx, [rsp+88h+var_78]\nmov [r14+rdx-8], rax\njmp loc_163D\nloc_16D0:\nadd [rsp+88h+var_7C], 1\nmovsxd rbx, [rsp+88h+var_7C]\nmov rdi, r14; ptr\nshl rbx, 3\nmov rsi, rbx; size\ncall _realloc\nmov rdi, rbp; s\nmov r14, rax\ncall _strdup\nmov [r14+rbx-8], rax\njmp loc_1656\nloc_16FE:\nmov [rsp+88h+var_7C], 0\nxor r14d, r14d\njmp loc_1656\nloc_170E:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(const char *a1)\n{\n char *v1; // rax\n const char *v2; // rbp\n char *v3; // r14\n __int64 v4; // r15\n int v5; // r12d\n size_t v6; // rbx\n char *v7; // rax\n unsigned __int64 v8; // rax\n size_t v10; // rbx\n int v11; // [rsp+0h] [rbp-7Ch]\n char *ptr; // [rsp+Ch] [rbp-70h]\n char *s[2]; // [rsp+14h] [rbp-68h]\n __m128i v14; // [rsp+24h] [rbp-58h]\n unsigned __int64 v15; // [rsp+3Ch] [rbp-40h]\n\n v15 = __readfsqword(0x28u);\n *(__m128i *)s = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_2004, (__m128i)(unsigned __int64)&unk_2007);\n v14 = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_200A, (__m128i)(unsigned __int64)&unk_200C);\n v1 = strdup(a1);\n ptr = v1;\n if ( *v1 )\n {\n v11 = 0;\n v2 = v1;\n v3 = 0LL;\n while ( 1 )\n {\n v4 = 0LL;\n v5 = -1;\n v6 = strlen(v2);\n do\n {\n v7 = strstr(v2, s[v4]);\n if ( v7 )\n {\n v8 = v7 - v2;\n if ( v8 < v6 )\n {\n v5 = v4;\n v6 = v8;\n }\n }\n ++v4;\n }\n while ( v4 != 4 );\n if ( v5 == -1 )\n break;\n if ( v6 )\n {\n v3 = (char *)realloc(v3, 8LL * ++v11);\n *(_QWORD *)&v3[8 * v11 - 8] = strndup(v2, v6);\n }\n v2 += v6 + strlen(s[v5]);\n if ( !*v2 )\n goto LABEL_12;\n }\n v10 = 8LL * (v11 + 1);\n v3 = (char *)realloc(v3, v10);\n *(_QWORD *)&v3[v10 - 8] = strdup(v2);\n }\n else\n {\n v3 = 0LL;\n }\nLABEL_12:\n free(ptr);\n return v3;\n}", + "ida_strip_asm": "sub_1560:\nendbr64\npush r15\nlea rcx, unk_2004\npush r14\nmovq xmm0, rcx\nlea rcx, unk_200A\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+88h+var_40], rax\nlea rax, unk_2007\nmovq xmm1, rax\nlea rax, unk_200C\npunpcklqdq xmm0, xmm1\nmovq xmm2, rax\nmovaps xmmword ptr [rsp+88h+s], xmm0\nmovq xmm0, rcx\npunpcklqdq xmm0, xmm2\nmovaps [rsp+88h+var_58], xmm0\ncall _strdup\ncmp byte ptr [rax], 0\nmov [rsp+88h+ptr], rax\njz loc_16FE\nmov [rsp+88h+var_7C], 0\nmov rbp, rax\nxor r14d, r14d\nlea r13, [rsp+88h+s]\nnop dword ptr [rax+rax+00000000h]\nloc_15F0:\nmov rdi, rbp; s\nxor r15d, r15d\nmov r12d, 0FFFFFFFFh\ncall _strlen\nmov rbx, rax\nloc_1604:\nmov rsi, [r13+r15*8+0]; needle\nmov rdi, rbp; haystack\ncall _strstr\ntest rax, rax\njz short loc_1624\nsub rax, rbp\ncmp rax, rbx\ncmovb r12d, r15d\ncmovb rbx, rax\nloc_1624:\nadd r15, 1\ncmp r15, 4\njnz short loc_1604\ncmp r12d, 0FFFFFFFFh\njz loc_16D0\ntest rbx, rbx\njnz short loc_1690\nloc_163D:\nmovsxd r12, r12d\nmov rdi, [rsp+r12*8+88h+s]; s\ncall _strlen\nadd rax, rbx\nadd rbp, rax\ncmp byte ptr [rbp+0], 0\njnz short loc_15F0\nloc_1656:\nmov rdi, [rsp+88h+ptr]; ptr\ncall _free\nmov edx, [rsp+88h+var_7C]\nmov rax, [rsp+88h+var_40]\nsub rax, fs:28h\njnz loc_170E\nadd rsp, 58h\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1690:\nadd [rsp+88h+var_7C], 1\nmovsxd rdx, [rsp+88h+var_7C]\nmov rdi, r14; ptr\nshl rdx, 3\nmov rsi, rdx; size\nmov [rsp+88h+var_78], rdx\ncall _realloc\nmov rsi, rbx; n\nmov rdi, rbp; string\nmov r14, rax\ncall _strndup\nmov rdx, [rsp+88h+var_78]\nmov [r14+rdx-8], rax\njmp loc_163D\nloc_16D0:\nadd [rsp+88h+var_7C], 1\nmovsxd rbx, [rsp+88h+var_7C]\nmov rdi, r14; ptr\nshl rbx, 3\nmov rsi, rbx; size\ncall _realloc\nmov rdi, rbp; s\nmov r14, rax\ncall _strdup\nmov [r14+rbx-8], rax\njmp loc_1656\nloc_16FE:\nmov [rsp+88h+var_7C], 0\nxor r14d, r14d\njmp loc_1656\nloc_170E:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_1560(const char *a1)\n{\n char *v1; // rax\n const char *v2; // rbp\n char *v3; // r14\n __int64 v4; // r15\n int v5; // r12d\n size_t v6; // rbx\n char *v7; // rax\n unsigned __int64 v8; // rax\n size_t v10; // rbx\n int v11; // [rsp+0h] [rbp-7Ch]\n char *ptr; // [rsp+Ch] [rbp-70h]\n char *s[2]; // [rsp+14h] [rbp-68h]\n __m128i v14; // [rsp+24h] [rbp-58h]\n unsigned __int64 v15; // [rsp+3Ch] [rbp-40h]\n\n v15 = __readfsqword(0x28u);\n *(__m128i *)s = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_2004, (__m128i)(unsigned __int64)&unk_2007);\n v14 = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_200A, (__m128i)(unsigned __int64)&unk_200C);\n v1 = strdup(a1);\n ptr = v1;\n if ( *v1 )\n {\n v11 = 0;\n v2 = v1;\n v3 = 0LL;\n while ( 1 )\n {\n v4 = 0LL;\n v5 = -1;\n v6 = strlen(v2);\n do\n {\n v7 = strstr(v2, s[v4]);\n if ( v7 )\n {\n v8 = v7 - v2;\n if ( v8 < v6 )\n {\n v5 = v4;\n v6 = v8;\n }\n }\n ++v4;\n }\n while ( v4 != 4 );\n if ( v5 == -1 )\n break;\n if ( v6 )\n {\n v3 = (char *)realloc(v3, 8LL * ++v11);\n *(_QWORD *)&v3[8 * v11 - 8] = strndup(v2, v6);\n }\n v2 += v6 + strlen(s[v5]);\n if ( !*v2 )\n goto LABEL_12;\n }\n v10 = 8LL * (v11 + 1);\n v3 = (char *)realloc(v3, v10);\n *(_QWORD *)&v3[v10 - 8] = strdup(v2);\n }\n else\n {\n v3 = 0LL;\n }\nLABEL_12:\n free(ptr);\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1560(const char *a1) {\n char *v1;\n const char *v2;\n char *v3;\n long long v4;\n int v5;\n unsigned int v6;\n char *v7;\n unsigned long long v8;\n unsigned int v10;\n int v11;\n char *ptr;\n char *s[2];\n __m128i v14;\n unsigned long long v15;\n v15 = __readfsqword(40u);\n *(__m128i *)s = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_2004,\n (__m128i)(unsigned long long)&unk_2007);\n v14 = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_200A,\n (__m128i)(unsigned long long)&unk_200C);\n v1 = strdup(a1);\n ptr = v1;\n if (*v1) {\n v11 = 0;\n v2 = v1;\n v3 = 0LL;\n while (1) {\n v4 = 0LL;\n v5 = -1;\n v6 = strlen(v2);\n do {\n v7 = strstr(v2, s[v4]);\n if (v7) {\n v8 = v7 - v2;\n if (v8 < v6) {\n v5 = v4;\n v6 = v8;\n }\n }\n ++v4;\n } while (v4 != 4);\n if (v5 == -1) break;\n if (v6) {\n v3 = (char *)realloc(v3, 8LL * ++v11);\n *(uint64_t *)&v3[8 * v11 - 8] = strndup(v2, v6);\n }\n v2 += v6 + strlen(s[v5]);\n if (!*v2) goto LABEL_12;\n }\n v10 = 8LL * (v11 + 1);\n v3 = (char *)realloc(v3, v10);\n *(uint64_t *)&v3[v10 - 8] = strdup(v2);\n } else {\n v3 = 0LL;\n }\nLABEL_12:\n free(ptr);\n return v3;\n}", + "ida_pseudo_norm": "char *func0(const char *a1) {\n char *v1;\n const char *v2;\n char *v3;\n long long v4;\n int v5;\n unsigned int v6;\n char *v7;\n unsigned long long v8;\n unsigned int v10;\n int v11;\n char *ptr;\n char *s[2];\n __m128i v14;\n unsigned long long v15;\n v15 = __readfsqword(40u);\n *(__m128i *)s = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_2004,\n (__m128i)(unsigned long long)&unk_2007);\n v14 = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_200A,\n (__m128i)(unsigned long long)&unk_200C);\n v1 = strdup(a1);\n ptr = v1;\n if (*v1) {\n v11 = 0;\n v2 = v1;\n v3 = 0LL;\n while (1) {\n v4 = 0LL;\n v5 = -1;\n v6 = strlen(v2);\n do {\n v7 = strstr(v2, s[v4]);\n if (v7) {\n v8 = v7 - v2;\n if (v8 < v6) {\n v5 = v4;\n v6 = v8;\n }\n }\n ++v4;\n } while (v4 != 4);\n if (v5 == -1) break;\n if (v6) {\n v3 = (char *)realloc(v3, 8LL * ++v11);\n *(uint64_t *)&v3[8 * v11 - 8] = strndup(v2, v6);\n }\n v2 += v6 + strlen(s[v5]);\n if (!*v2) goto LABEL_12;\n }\n v10 = 8LL * (v11 + 1);\n v3 = (char *)realloc(v3, v10);\n *(uint64_t *)&v3[v10 - 8] = strdup(v2);\n } else {\n v3 = 0LL;\n }\nLABEL_12:\n free(ptr);\n return v3;\n}" + }, + { + "index": 73, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char** tokens;\n\n int count;\n\n} split_result;\n\n\n\n", + "func": "split_result func0(const char* text) {\n split_result result;\n result.tokens = NULL;\n result.count = 0;\n const char* delimiters[] = {\"; \", \", \", \"*\", \"\\n\"};\n int num_delimiters = 4;\n char* temp = strdup(text);\n char* ptr = temp;\n char* match;\n int min_index;\n while (*ptr) {\n min_index = -1;\n size_t min_pos = strlen(ptr);\n for (int i = 0; i < num_delimiters; i++) {\n char* found = strstr(ptr, delimiters[i]);\n if (found && (found - ptr) < min_pos) {\n min_pos = found - ptr;\n min_index = i;\n }\n }\n if (min_index == -1) {\n result.tokens =\n realloc(result.tokens, sizeof(char*) * (result.count + 1));\n result.tokens[result.count++] = strdup(ptr);\n break;\n }\n if (min_pos > 0) {\n result.tokens =\n realloc(result.tokens, sizeof(char*) * (result.count + 1));\n char* token = strndup(ptr, min_pos);\n result.tokens[result.count++] = token;\n }\n ptr += min_pos + strlen(delimiters[min_index]);\n }\n free(temp);\n return result;\n}", + "test": "int main(){\n\n split_result res1 = func0(\"Forces of the \\ndarkness*are coming into the play.\");\n\n assert(res1.count == 3);\n\n assert(strcmp(res1.tokens[0], \"Forces of the \") == 0);\n\n assert(strcmp(res1.tokens[1], \"darkness\") == 0);\n\n assert(strcmp(res1.tokens[2], \"are coming into the play.\") == 0);\n\n for(int i=0;i\ncmpb $0x0,(%rax)\nmov %rax,0x8(%rsp)\nje 1793 \nmov %rax,%r15\nxor %r12d,%r12d\nxor %r14d,%r14d\nmov %r15,%rdi\nmov $0xffffffff,%ebp\ncallq 10e0 \nlea 0xa04(%rip),%rsi\nmov %r15,%rdi\nmov %rax,%rbx\nmov %rax,%r13\ncallq 1150 \ntest %rax,%rax\nje 1628 \nsub %r15,%rax\ncmp %rax,%rbx\ncmova %rax,%rbx\ncmp %r13,%rax\nsbb %ebp,%ebp\nnot %ebp\nlea 0x9dc(%rip),%rsi\nmov %r15,%rdi\ncallq 1150 \ntest %rax,%rax\nje 164c \nsub %r15,%rax\ncmp %rax,%rbx\njbe 164c \nmov %rax,%rbx\nmov $0x1,%ebp\nmov $0x2a,%esi\nmov %r15,%rdi\ncallq 1100 \nmov $0xa,%esi\nmov %r15,%rdi\nmov %rax,%r13\ncallq 1100 \ntest %r13,%r13\nje 16e8 \nsub %r15,%r13\ncmp %r13,%rbx\njbe 16e8 \nlea 0x987(%rip),%rbp\ntest %rax,%rax\nje 1698 \nsub %r15,%rax\ncmp %rax,%r13\njbe 1698 \nmov %rax,%r13\nlea 0x972(%rip),%rbp\nnopl 0x0(%rax)\ntest %r13,%r13\njne 1704 \nmov %rbp,%rdi\ncallq 10e0 \nadd %rax,%r15\ncmpb $0x0,(%r15)\njne 15f0 \nmov 0x8(%rsp),%rdi\ncallq 10d0 \nmov %r14d,%edx\nmov 0x38(%rsp),%rax\nxor %fs:0x28,%rax\njne 179e \nadd $0x48,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl (%rax)\ntest %rax,%rax\nje 1750 \nsub %r15,%rax\nmov %rax,%r13\ncmp %rax,%rbx\njbe 1750 \nlea 0x907(%rip),%rbp\ntest %r13,%r13\nje 169d \nadd $0x1,%r14d\nmov %r12,%rdi\nmovslq %r14d,%rbx\nshl $0x3,%rbx\nmov %rbx,%rsi\ncallq 1130 \nmov %r13,%rsi\nmov %r15,%rdi\nmov %rax,%r12\ncallq 1120 \nmov %rbp,%rdi\nmov %rax,-0x8(%r12,%rbx,1)\ncallq 10e0 \nadd %rax,%r13\nadd %r13,%r15\ncmpb $0x0,(%r15)\njne 15f0 \njmpq 16b2 \nnopw 0x0(%rax,%rax,1)\ncmp $0xffffffff,%ebp\nje 1768 \nmovslq %ebp,%rbp\nmov %rbx,%r13\nmov 0x10(%rsp,%rbp,8),%rbp\njmpq 1698 \nnopl (%rax)\nadd $0x1,%r14d\nmov %r12,%rdi\nmovslq %r14d,%rbx\nshl $0x3,%rbx\nmov %rbx,%rsi\ncallq 1130 \nmov %r15,%rdi\nmov %rax,%r12\ncallq 1140 \nmov %rax,-0x8(%r12,%rbx,1)\njmpq 16b2 \nxor %r14d,%r14d\nxor %r12d,%r12d\njmpq 16b2 \ncallq 10f0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\nlea rdx, asc_200A; \"*\"\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 48h\nmovq xmm0, cs:off_3D70; \"; \"\nmov rax, fs:28h\nmov [rsp+78h+var_40], rax\nxor eax, eax\nlea rax, asc_200C; \"\\n\"\nmovhps xmm0, cs:off_3D78; \", \"\nmovq xmm1, rax\nmovaps xmmword ptr [rsp+78h+s], xmm0\nmovq xmm0, rdx\npunpcklqdq xmm0, xmm1\nmovaps [rsp+78h+var_58], xmm0\ncall _strdup\ncmp byte ptr [rax], 0\nmov [rsp+78h+ptr], rax\njz loc_17A5\nmov rbx, rax\nxor ebp, ebp\nxor r12d, r12d\nnop word ptr [rax+rax+00h]\nloc_15F8:\nmov rdi, rbx; s\nmov r15d, 0FFFFFFFFh\ncall _strlen\nlea rsi, needle; \"; \"\nmov rdi, rbx; haystack\nmov r14, rax\ncall _strstr\ntest rax, rax\njz short loc_1630\nsub rax, rbx\ncmp rax, r14\nsbb r15d, r15d\ncmp rax, r14\ncmovbe r14, rax\nnot r15d\nloc_1630:\nlea rsi, asc_2007; \", \"\nmov rdi, rbx; haystack\ncall _strstr\ntest rax, rax\njz short loc_1655\nsub rax, rbx\ncmp rax, r14\njnb short loc_1655\nmov r14, rax\nmov r15d, 1\nloc_1655:\nmov esi, 2Ah ; '*'; c\nmov rdi, rbx; s\ncall _strchr\nmov esi, 0Ah; c\nmov rdi, rbx; s\nmov r13, rax\ncall _strchr\ntest r13, r13\njz loc_1700\nmov r8, r13\nsub r8, rbx\ncmp r8, r14\njnb short loc_1700\ntest rax, rax\njz short loc_169C\nsub rax, rbx\nmov r15d, 3\nmov r14, rax\ncmp rax, r8\njb short loc_16A5\nloc_169C:\nmov r14, r8\nmov r15d, 2\nloc_16A5:\ntest r14, r14\njnz short loc_171B\nloc_16AA:\nmovsxd rcx, r15d\nmov rdi, [rsp+rcx*8+78h+s]; s\ncall _strlen\nadd rbx, rax\ncmp byte ptr [rbx], 0\njnz loc_15F8\nloc_16C3:\nmov rdi, [rsp+78h+ptr]; ptr\ncall _free\nmov edx, r12d\nmov rax, [rsp+78h+var_40]\nsub rax, fs:28h\njnz loc_17AF\nadd rsp, 48h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1700:\ntest rax, rax\njz short loc_1770\nsub rax, rbx\ncmp rax, r14\njnb short loc_1770\nmov r14, rax\nmov r15d, 3\ntest r14, r14\njz short loc_16AA\nloc_171B:\nadd r12d, 1\nmov rdi, rbp; ptr\nmovsxd r8, r12d\nshl r8, 3\nmov rsi, r8; size\nmov [rsp+78h+var_78], r8\ncall _realloc\nmov rdi, rbx; string\nmov rsi, r14; n\nmov rbp, rax\ncall _strndup\nmov r8, [rsp+78h+var_78]\nmovsxd rcx, r15d\nmov rdi, [rsp+rcx*8+78h+s]; s\nmov [rbp+r8-8], rax\ncall _strlen\nadd rax, r14\nadd rbx, rax\ncmp byte ptr [rbx], 0\njnz loc_15F8\njmp loc_16C3\nloc_1770:\ncmp r15d, 0FFFFFFFFh\njnz loc_16A5\nadd r12d, 1\nmov rdi, rbp; ptr\nmovsxd r13, r12d\nshl r13, 3\nmov rsi, r13; size\ncall _realloc\nmov rdi, rbx; s\nmov rbp, rax\ncall _strdup\nmov [rbp+r13-8], rax\njmp loc_16C3\nloc_17A5:\nxor r12d, r12d\nxor ebp, ebp\njmp loc_16C3\nloc_17AF:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(const char *a1)\n{\n char *v1; // rax\n const char *v2; // rbx\n char *v3; // rbp\n int v4; // r12d\n int v5; // r15d\n size_t v6; // r14\n char *v7; // rax\n unsigned __int64 v8; // rax\n int v9; // r15d\n char *v10; // rax\n unsigned __int64 v11; // rax\n char *v12; // r13\n char *v13; // rax\n unsigned __int64 v15; // rax\n char *v16; // rax\n const char *v17; // rdi\n size_t v18; // r13\n char *ptr; // [rsp+8h] [rbp-70h]\n char *s[2]; // [rsp+10h] [rbp-68h]\n __m128i v21; // [rsp+20h] [rbp-58h]\n unsigned __int64 v22; // [rsp+38h] [rbp-40h]\n\n v22 = __readfsqword(0x28u);\n *(__m128 *)s = _mm_loadh_ps((const double *)&off_3D78);\n v21 = _mm_unpacklo_epi64((__m128i)(unsigned __int64)\"*\", (__m128i)(unsigned __int64)\"\\n\");\n v1 = strdup(a1);\n ptr = v1;\n if ( !*v1 )\n {\n v3 = 0LL;\n goto LABEL_17;\n }\n v2 = v1;\n v3 = 0LL;\n v4 = 0;\n while ( 1 )\n {\n while ( 1 )\n {\n v5 = -1;\n v6 = strlen(v2);\n v7 = strstr(v2, \"; \");\n if ( v7 )\n {\n v8 = v7 - v2;\n v9 = -(v8 < v6);\n if ( v8 <= v6 )\n v6 = v8;\n v5 = ~v9;\n }\n v10 = strstr(v2, \", \");\n if ( v10 )\n {\n v11 = v10 - v2;\n if ( v11 < v6 )\n {\n v6 = v11;\n v5 = 1;\n }\n }\n v12 = strchr(v2, 42);\n v13 = strchr(v2, 10);\n if ( !v12 || v12 - v2 >= v6 )\n break;\n if ( !v13 || (v5 = 3, v6 = v13 - v2, v13 - v2 >= (unsigned __int64)(v12 - v2)) )\n {\n v6 = v12 - v2;\n v5 = 2;\n }\nLABEL_15:\n if ( v6 )\n goto LABEL_21;\nLABEL_16:\n v2 += strlen(s[v5]);\n if ( !*v2 )\n goto LABEL_17;\n }\n if ( !v13 )\n break;\n v15 = v13 - v2;\n if ( v15 >= v6 )\n break;\n v6 = v15;\n v5 = 3;\n if ( !v15 )\n goto LABEL_16;\nLABEL_21:\n v3 = (char *)realloc(v3, 8LL * ++v4);\n v16 = strndup(v2, v6);\n v17 = s[v5];\n *(_QWORD *)&v3[8 * v4 - 8] = v16;\n v2 += v6 + strlen(v17);\n if ( !*v2 )\n goto LABEL_17;\n }\n if ( v5 != -1 )\n goto LABEL_15;\n v18 = 8LL * (v4 + 1);\n v3 = (char *)realloc(v3, v18);\n *(_QWORD *)&v3[v18 - 8] = strdup(v2);\nLABEL_17:\n free(ptr);\n return v3;\n}", + "ida_strip_asm": "sub_1580:\nendbr64\npush r15\nlea rdx, asc_200A; \"*\"\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 48h\nmovq xmm0, cs:off_3D70; \"; \"\nmov rax, fs:28h\nmov [rsp+78h+var_40], rax\nxor eax, eax\nlea rax, asc_200C; \"\\n\"\nmovhps xmm0, cs:off_3D78; \", \"\nmovq xmm1, rax\nmovaps xmmword ptr [rsp+78h+s], xmm0\nmovq xmm0, rdx\npunpcklqdq xmm0, xmm1\nmovaps [rsp+78h+var_58], xmm0\ncall _strdup\ncmp byte ptr [rax], 0\nmov [rsp+78h+ptr], rax\njz loc_17A5\nmov rbx, rax\nxor ebp, ebp\nxor r12d, r12d\nnop word ptr [rax+rax+00h]\nloc_15F8:\nmov rdi, rbx; s\nmov r15d, 0FFFFFFFFh\ncall _strlen\nlea rsi, needle; \"; \"\nmov rdi, rbx; haystack\nmov r14, rax\ncall _strstr\ntest rax, rax\njz short loc_1630\nsub rax, rbx\ncmp rax, r14\nsbb r15d, r15d\ncmp rax, r14\ncmovbe r14, rax\nnot r15d\nloc_1630:\nlea rsi, asc_2007; \", \"\nmov rdi, rbx; haystack\ncall _strstr\ntest rax, rax\njz short loc_1655\nsub rax, rbx\ncmp rax, r14\njnb short loc_1655\nmov r14, rax\nmov r15d, 1\nloc_1655:\nmov esi, 2Ah ; '*'; c\nmov rdi, rbx; s\ncall _strchr\nmov esi, 0Ah; c\nmov rdi, rbx; s\nmov r13, rax\ncall _strchr\ntest r13, r13\njz loc_1700\nmov r8, r13\nsub r8, rbx\ncmp r8, r14\njnb short loc_1700\ntest rax, rax\njz short loc_169C\nsub rax, rbx\nmov r15d, 3\nmov r14, rax\ncmp rax, r8\njb short loc_16A5\nloc_169C:\nmov r14, r8\nmov r15d, 2\nloc_16A5:\ntest r14, r14\njnz short loc_171B\nloc_16AA:\nmovsxd rcx, r15d\nmov rdi, [rsp+rcx*8+78h+s]; s\ncall _strlen\nadd rbx, rax\ncmp byte ptr [rbx], 0\njnz loc_15F8\nloc_16C3:\nmov rdi, [rsp+78h+ptr]; ptr\ncall _free\nmov edx, r12d\nmov rax, [rsp+78h+var_40]\nsub rax, fs:28h\njnz loc_17AF\nadd rsp, 48h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1700:\ntest rax, rax\njz short loc_1770\nsub rax, rbx\ncmp rax, r14\njnb short loc_1770\nmov r14, rax\nmov r15d, 3\ntest r14, r14\njz short loc_16AA\nloc_171B:\nadd r12d, 1\nmov rdi, rbp; ptr\nmovsxd r8, r12d\nshl r8, 3\nmov rsi, r8; size\nmov [rsp+78h+var_78], r8\ncall _realloc\nmov rdi, rbx; string\nmov rsi, r14; n\nmov rbp, rax\ncall _strndup\nmov r8, [rsp+78h+var_78]\nmovsxd rcx, r15d\nmov rdi, [rsp+rcx*8+78h+s]; s\nmov [rbp+r8-8], rax\ncall _strlen\nadd rax, r14\nadd rbx, rax\ncmp byte ptr [rbx], 0\njnz loc_15F8\njmp loc_16C3\nloc_1770:\ncmp r15d, 0FFFFFFFFh\njnz loc_16A5\nadd r12d, 1\nmov rdi, rbp; ptr\nmovsxd r13, r12d\nshl r13, 3\nmov rsi, r13; size\ncall _realloc\nmov rdi, rbx; s\nmov rbp, rax\ncall _strdup\nmov [rbp+r13-8], rax\njmp loc_16C3\nloc_17A5:\nxor r12d, r12d\nxor ebp, ebp\njmp loc_16C3\nloc_17AF:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_1580(const char *a1)\n{\n char *v1; // rax\n const char *v2; // rbx\n char *v3; // rbp\n int v4; // r12d\n int v5; // r15d\n size_t v6; // r14\n char *v7; // rax\n unsigned __int64 v8; // rax\n int v9; // r15d\n char *v10; // rax\n unsigned __int64 v11; // rax\n char *v12; // r13\n char *v13; // rax\n unsigned __int64 v15; // rax\n char *v16; // rax\n const char *v17; // rdi\n size_t v18; // r13\n char *ptr; // [rsp+8h] [rbp-70h]\n char *s[2]; // [rsp+10h] [rbp-68h]\n __m128i v21; // [rsp+20h] [rbp-58h]\n unsigned __int64 v22; // [rsp+38h] [rbp-40h]\n\n v22 = __readfsqword(0x28u);\n *(__m128 *)s = _mm_loadh_ps((const double *)&off_3D78);\n v21 = _mm_unpacklo_epi64((__m128i)(unsigned __int64)\"*\", (__m128i)(unsigned __int64)\"\\n\");\n v1 = strdup(a1);\n ptr = v1;\n if ( !*v1 )\n {\n v3 = 0LL;\n goto LABEL_17;\n }\n v2 = v1;\n v3 = 0LL;\n v4 = 0;\n while ( 1 )\n {\n while ( 1 )\n {\n v5 = -1;\n v6 = strlen(v2);\n v7 = strstr(v2, \"; \");\n if ( v7 )\n {\n v8 = v7 - v2;\n v9 = -(v8 < v6);\n if ( v8 <= v6 )\n v6 = v8;\n v5 = ~v9;\n }\n v10 = strstr(v2, \", \");\n if ( v10 )\n {\n v11 = v10 - v2;\n if ( v11 < v6 )\n {\n v6 = v11;\n v5 = 1;\n }\n }\n v12 = strchr(v2, 42);\n v13 = strchr(v2, 10);\n if ( !v12 || v12 - v2 >= v6 )\n break;\n if ( !v13 || (v5 = 3, v6 = v13 - v2, v13 - v2 >= (unsigned __int64)(v12 - v2)) )\n {\n v6 = v12 - v2;\n v5 = 2;\n }\nLABEL_15:\n if ( v6 )\n goto LABEL_21;\nLABEL_16:\n v2 += strlen(s[v5]);\n if ( !*v2 )\n goto LABEL_17;\n }\n if ( !v13 )\n break;\n v15 = v13 - v2;\n if ( v15 >= v6 )\n break;\n v6 = v15;\n v5 = 3;\n if ( !v15 )\n goto LABEL_16;\nLABEL_21:\n v3 = (char *)realloc(v3, 8LL * ++v4);\n v16 = strndup(v2, v6);\n v17 = s[v5];\n *(_QWORD *)&v3[8 * v4 - 8] = v16;\n v2 += v6 + strlen(v17);\n if ( !*v2 )\n goto LABEL_17;\n }\n if ( v5 != -1 )\n goto LABEL_15;\n v18 = 8LL * (v4 + 1);\n v3 = (char *)realloc(v3, v18);\n *(_QWORD *)&v3[v18 - 8] = strdup(v2);\nLABEL_17:\n free(ptr);\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1580(const char *a1) {\n char *v1;\n const char *v2;\n char *v3;\n int v4;\n int v5;\n unsigned int v6;\n char *v7;\n unsigned long long v8;\n int v9;\n char *v10;\n unsigned long long v11;\n char *v12;\n char *v13;\n unsigned long long v15;\n char *v16;\n const char *v17;\n unsigned int v18;\n char *ptr;\n char *s[2];\n __m128i v21;\n unsigned long long v22;\n v22 = __readfsqword(40u);\n *(__m128 *)s = _mm_loadh_ps((const double *)&off_3D78);\n v21 = _mm_unpacklo_epi64((__m128i)(unsigned long long)\"*\",\n (__m128i)(unsigned long long)\"\\n\");\n v1 = strdup(a1);\n ptr = v1;\n if (!*v1) {\n v3 = 0LL;\n goto LABEL_17;\n }\n v2 = v1;\n v3 = 0LL;\n v4 = 0;\n while (1) {\n while (1) {\n v5 = -1;\n v6 = strlen(v2);\n v7 = strstr(v2, \"; \");\n if (v7) {\n v8 = v7 - v2;\n v9 = -(v8 < v6);\n if (v8 <= v6) v6 = v8;\n v5 = ~v9;\n }\n v10 = strstr(v2, \", \");\n if (v10) {\n v11 = v10 - v2;\n if (v11 < v6) {\n v6 = v11;\n v5 = 1;\n }\n }\n v12 = strchr(v2, 42);\n v13 = strchr(v2, 10);\n if (!v12 || v12 - v2 >= v6) break;\n if (!v13 ||\n (v5 = 3, v6 = v13 - v2, v13 - v2 >= (unsigned long long)(v12 - v2))) {\n v6 = v12 - v2;\n v5 = 2;\n }\n LABEL_15:\n if (v6) goto LABEL_21;\n LABEL_16:\n v2 += strlen(s[v5]);\n if (!*v2) goto LABEL_17;\n }\n if (!v13) break;\n v15 = v13 - v2;\n if (v15 >= v6) break;\n v6 = v15;\n v5 = 3;\n if (!v15) goto LABEL_16;\n LABEL_21:\n v3 = (char *)realloc(v3, 8LL * ++v4);\n v16 = strndup(v2, v6);\n v17 = s[v5];\n *(uint64_t *)&v3[8 * v4 - 8] = v16;\n v2 += v6 + strlen(v17);\n if (!*v2) goto LABEL_17;\n }\n if (v5 != -1) goto LABEL_15;\n v18 = 8LL * (v4 + 1);\n v3 = (char *)realloc(v3, v18);\n *(uint64_t *)&v3[v18 - 8] = strdup(v2);\nLABEL_17:\n free(ptr);\n return v3;\n}", + "ida_pseudo_norm": "char *func0(const char *a1) {\n char *v1;\n const char *v2;\n char *v3;\n int v4;\n int v5;\n unsigned int v6;\n char *v7;\n unsigned long long v8;\n int v9;\n char *v10;\n unsigned long long v11;\n char *v12;\n char *v13;\n unsigned long long v15;\n char *v16;\n const char *v17;\n unsigned int v18;\n char *ptr;\n char *s[2];\n __m128i v21;\n unsigned long long v22;\n v22 = __readfsqword(40u);\n *(__m128 *)s = _mm_loadh_ps((const double *)&off_3D78);\n v21 = _mm_unpacklo_epi64((__m128i)(unsigned long long)\"*\",\n (__m128i)(unsigned long long)\"\\n\");\n v1 = strdup(a1);\n ptr = v1;\n if (!*v1) {\n v3 = 0LL;\n goto LABEL_17;\n }\n v2 = v1;\n v3 = 0LL;\n v4 = 0;\n while (1) {\n while (1) {\n v5 = -1;\n v6 = strlen(v2);\n v7 = strstr(v2, \"; \");\n if (v7) {\n v8 = v7 - v2;\n v9 = -(v8 < v6);\n if (v8 <= v6) v6 = v8;\n v5 = ~v9;\n }\n v10 = strstr(v2, \", \");\n if (v10) {\n v11 = v10 - v2;\n if (v11 < v6) {\n v6 = v11;\n v5 = 1;\n }\n }\n v12 = strchr(v2, 42);\n v13 = strchr(v2, 10);\n if (!v12 || v12 - v2 >= v6) break;\n if (!v13 ||\n (v5 = 3, v6 = v13 - v2, v13 - v2 >= (unsigned long long)(v12 - v2))) {\n v6 = v12 - v2;\n v5 = 2;\n }\n LABEL_15:\n if (v6) goto LABEL_21;\n LABEL_16:\n v2 += strlen(s[v5]);\n if (!*v2) goto LABEL_17;\n }\n if (!v13) break;\n v15 = v13 - v2;\n if (v15 >= v6) break;\n v6 = v15;\n v5 = 3;\n if (!v15) goto LABEL_16;\n LABEL_21:\n v3 = (char *)realloc(v3, 8LL * ++v4);\n v16 = strndup(v2, v6);\n v17 = s[v5];\n *(uint64_t *)&v3[8 * v4 - 8] = v16;\n v2 += v6 + strlen(v17);\n if (!*v2) goto LABEL_17;\n }\n if (v5 != -1) goto LABEL_15;\n v18 = 8LL * (v4 + 1);\n v3 = (char *)realloc(v3, v18);\n *(uint64_t *)&v3[v18 - 8] = strdup(v2);\nLABEL_17:\n free(ptr);\n return v3;\n}" + }, + { + "index": 74, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(char** colors, int colors_len, char** patterns, int patterns_len) {\n if (colors_len != patterns_len) {\n return false;\n }\n char* sdict_keys[100];\n char* sdict_values[100][100];\n int sdict_size = 0;\n char* pset[100];\n int pset_size = 0;\n char* sset[100];\n int sset_size = 0;\n for (int i = 0; i < patterns_len; i++) {\n bool found = false;\n for (int j = 0; j < pset_size; j++) {\n if (strcmp(patterns[i], pset[j]) == 0) {\n found = true;\n break;\n }\n }\n if (!found) {\n pset[pset_size++] = patterns[i];\n }\n found = false;\n for (int j = 0; j < sset_size; j++) {\n if (strcmp(colors[i], sset[j]) == 0) {\n found = true;\n break;\n }\n }\n if (!found) {\n sset[sset_size++] = colors[i];\n }\n int pattern_index = -1;\n for (int j = 0; j < sdict_size; j++) {\n if (strcmp(patterns[i], sdict_keys[j]) == 0) {\n pattern_index = j;\n break;\n }\n }\n if (pattern_index == -1) {\n sdict_keys[sdict_size] = patterns[i];\n sdict_values[sdict_size][0] = colors[i];\n sdict_values[sdict_size][1] = NULL;\n sdict_size++;\n }\n else {\n int k = 0;\n while (sdict_values[pattern_index][k] != NULL && k < 99) {\n k++;\n }\n sdict_values[pattern_index][k] = colors[i];\n sdict_values[pattern_index][k + 1] = NULL;\n }\n }\n if (pset_size != sset_size) {\n return false;\n }\n for (int i = 0; i < sdict_size; i++) {\n char* first_color = sdict_values[i][0];\n for (int j = 1; sdict_values[i][j] != NULL; j++) {\n if (strcmp(first_color, sdict_values[i][j]) != 0) {\n return false;\n }\n }\n }\n return true;\n}", + "test": "int main(){\n\n char* colors1[] = {\"red\", \"green\", \"green\"};\n\n char* patterns1[] = {\"a\", \"b\", \"b\"};\n\n assert(func0(colors1, 3, patterns1, 3) == true);\n\n\n\n char* colors2[] = {\"red\", \"green\", \"greenn\"};\n\n char* patterns2[] = {\"a\", \"b\", \"b\"};\n\n assert(func0(colors2, 3, patterns2, 3) == false);\n\n\n\n char* colors3[] = {\"red\", \"green\", \"greenn\"};\n\n char* patterns3[] = {\"a\", \"b\"};\n\n assert(func0(colors3, 3, patterns3, 2) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nlea -0x14000(%rsp),%r11\nsub $0x1000,%rsp\norq $0x0,(%rsp)\ncmp %r11,%rsp\njne 1199 \nsub $0x250,%rsp\nmov %rdi,-0x14238(%rbp)\nmov %esi,-0x1423c(%rbp)\nmov %rdx,-0x14248(%rbp)\nmov %ecx,-0x14240(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmov -0x1423c(%rbp),%eax\ncmp -0x14240(%rbp),%eax\nje 11f2 \nmov $0x0,%eax\njmpq 16da \nmovl $0x0,-0x14224(%rbp)\nmovl $0x0,-0x14220(%rbp)\nmovl $0x0,-0x1421c(%rbp)\nmovl $0x0,-0x14218(%rbp)\njmpq 15a9 \nmovb $0x0,-0x14225(%rbp)\nmovl $0x0,-0x14214(%rbp)\njmp 127e \nmov -0x14214(%rbp),%eax\ncltq\nmov -0x13ed0(%rbp,%rax,8),%rdx\nmov -0x14218(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x14248(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1090 \ntest %eax,%eax\njne 1277 \nmovb $0x1,-0x14225(%rbp)\njmp 128c \naddl $0x1,-0x14214(%rbp)\nmov -0x14214(%rbp),%eax\ncmp -0x14220(%rbp),%eax\njl 1232 \nmovzbl -0x14225(%rbp),%eax\nxor $0x1,%eax\ntest %al,%al\nje 12d1 \nmov -0x14218(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x14248(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x14220(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x14220(%rbp)\nmov (%rcx),%rdx\ncltq\nmov %rdx,-0x13ed0(%rbp,%rax,8)\nmovb $0x0,-0x14225(%rbp)\nmovl $0x0,-0x14210(%rbp)\njmp 1330 \nmov -0x14210(%rbp),%eax\ncltq\nmov -0x13bb0(%rbp,%rax,8),%rdx\nmov -0x14218(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x14238(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1090 \ntest %eax,%eax\njne 1329 \nmovb $0x1,-0x14225(%rbp)\njmp 133e \naddl $0x1,-0x14210(%rbp)\nmov -0x14210(%rbp),%eax\ncmp -0x1421c(%rbp),%eax\njl 12e4 \nmovzbl -0x14225(%rbp),%eax\nxor $0x1,%eax\ntest %al,%al\nje 1383 \nmov -0x14218(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x14238(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x1421c(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x1421c(%rbp)\nmov (%rcx),%rdx\ncltq\nmov %rdx,-0x13bb0(%rbp,%rax,8)\nmovl $0xffffffff,-0x1420c(%rbp)\nmovl $0x0,-0x14208(%rbp)\njmp 13ea \nmov -0x14208(%rbp),%eax\ncltq\nmov -0x141f0(%rbp,%rax,8),%rdx\nmov -0x14218(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x14248(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1090 \ntest %eax,%eax\njne 13e3 \nmov -0x14208(%rbp),%eax\nmov %eax,-0x1420c(%rbp)\njmp 13f8 \naddl $0x1,-0x14208(%rbp)\nmov -0x14208(%rbp),%eax\ncmp -0x14224(%rbp),%eax\njl 1399 \ncmpl $0xffffffff,-0x1420c(%rbp)\njne 14bb \nmov -0x14218(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x14248(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rdx\nmov -0x14224(%rbp),%eax\ncltq\nmov %rdx,-0x141f0(%rbp,%rax,8)\nmov -0x14218(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x14238(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rcx\nmov -0x14224(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nshl $0x5,%rax\nadd %rbp,%rax\nsub $0x13890,%rax\nmov %rcx,(%rax)\nmov -0x14224(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nshl $0x5,%rax\nadd %rbp,%rax\nsub $0x13888,%rax\nmovq $0x0,(%rax)\naddl $0x1,-0x14224(%rbp)\njmpq 15a2 \nmovl $0x0,-0x14204(%rbp)\njmp 14ce \naddl $0x1,-0x14204(%rbp)\nmov -0x14204(%rbp),%eax\nmovslq %eax,%rcx\nmov -0x1420c(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rcx,%rax\nmov -0x13890(%rbp,%rax,8),%rax\ntest %rax,%rax\nje 1512 \ncmpl $0x62,-0x14204(%rbp)\njle 14c7 \nmov -0x14218(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x14238(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rcx\nmov -0x14204(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x1420c(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rsi,%rax\nmov %rcx,-0x13890(%rbp,%rax,8)\nmov -0x14204(%rbp),%eax\nadd $0x1,%eax\nmovslq %eax,%rcx\nmov -0x1420c(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rcx,%rax\nmovq $0x0,-0x13890(%rbp,%rax,8)\naddl $0x1,-0x14218(%rbp)\nmov -0x14218(%rbp),%eax\ncmp -0x14240(%rbp),%eax\njl 121f \nmov -0x14220(%rbp),%eax\ncmp -0x1421c(%rbp),%eax\nje 15d3 \nmov $0x0,%eax\njmpq 16da \nmovl $0x0,-0x14200(%rbp)\njmpq 16c3 \nmov -0x14200(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nshl $0x5,%rax\nadd %rbp,%rax\nsub $0x13890,%rax\nmov (%rax),%rax\nmov %rax,-0x141f8(%rbp)\nmovl $0x1,-0x141fc(%rbp)\njmp 167d \nmov -0x141fc(%rbp),%eax\nmovslq %eax,%rcx\nmov -0x14200(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rcx,%rax\nmov -0x13890(%rbp,%rax,8),%rdx\nmov -0x141f8(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1090 \ntest %eax,%eax\nje 1676 \nmov $0x0,%eax\njmp 16da \naddl $0x1,-0x141fc(%rbp)\nmov -0x141fc(%rbp),%eax\nmovslq %eax,%rcx\nmov -0x14200(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rcx,%rax\nmov -0x13890(%rbp,%rax,8),%rax\ntest %rax,%rax\njne 1623 \naddl $0x1,-0x14200(%rbp)\nmov -0x14200(%rbp),%eax\ncmp -0x14224(%rbp),%eax\njl 15e2 \nmov $0x1,%eax\nmov -0x8(%rbp),%rdi\nxor %fs:0x28,%rdi\nje 16ee \ncallq 1070 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nlea r11, [rsp+var_14000]\nloc_1199:\nsub rsp, 1000h\nor [rsp+1000h+var_1000], 0\ncmp rsp, r11\njnz short loc_1199\nsub rsp, 250h\nmov [rbp+var_14238], rdi\nmov [rbp+var_1423C], esi\nmov [rbp+var_14248], rdx\nmov [rbp+var_14240], ecx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov eax, [rbp+var_1423C]\ncmp eax, [rbp+var_14240]\njz short loc_11F2\nmov eax, 0\njmp loc_16DA\nloc_11F2:\nmov [rbp+var_14224], 0\nmov [rbp+var_14220], 0\nmov [rbp+var_1421C], 0\nmov [rbp+var_14218], 0\njmp loc_15A9\nloc_121F:\nmov [rbp+var_14225], 0\nmov [rbp+var_14214], 0\njmp short loc_127E\nloc_1232:\nmov eax, [rbp+var_14214]\ncdqe\nmov rdx, [rbp+rax*8+s2]\nmov eax, [rbp+var_14218]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_14248]\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1277\nmov [rbp+var_14225], 1\njmp short loc_128C\nloc_1277:\nadd [rbp+var_14214], 1\nloc_127E:\nmov eax, [rbp+var_14214]\ncmp eax, [rbp+var_14220]\njl short loc_1232\nloc_128C:\nmovzx eax, [rbp+var_14225]\nxor eax, 1\ntest al, al\njz short loc_12D1\nmov eax, [rbp+var_14218]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_14248]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_14220]\nlea edx, [rax+1]\nmov [rbp+var_14220], edx\nmov rdx, [rcx]\ncdqe\nmov [rbp+rax*8+s2], rdx\nloc_12D1:\nmov [rbp+var_14225], 0\nmov [rbp+var_14210], 0\njmp short loc_1330\nloc_12E4:\nmov eax, [rbp+var_14210]\ncdqe\nmov rdx, [rbp+rax*8+var_13BB0]\nmov eax, [rbp+var_14218]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_14238]\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1329\nmov [rbp+var_14225], 1\njmp short loc_133E\nloc_1329:\nadd [rbp+var_14210], 1\nloc_1330:\nmov eax, [rbp+var_14210]\ncmp eax, [rbp+var_1421C]\njl short loc_12E4\nloc_133E:\nmovzx eax, [rbp+var_14225]\nxor eax, 1\ntest al, al\njz short loc_1383\nmov eax, [rbp+var_14218]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_14238]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_1421C]\nlea edx, [rax+1]\nmov [rbp+var_1421C], edx\nmov rdx, [rcx]\ncdqe\nmov [rbp+rax*8+var_13BB0], rdx\nloc_1383:\nmov [rbp+var_1420C], 0FFFFFFFFh\nmov [rbp+var_14208], 0\njmp short loc_13EA\nloc_1399:\nmov eax, [rbp+var_14208]\ncdqe\nmov rdx, [rbp+rax*8+var_141F0]\nmov eax, [rbp+var_14218]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_14248]\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_13E3\nmov eax, [rbp+var_14208]\nmov [rbp+var_1420C], eax\njmp short loc_13F8\nloc_13E3:\nadd [rbp+var_14208], 1\nloc_13EA:\nmov eax, [rbp+var_14208]\ncmp eax, [rbp+var_14224]\njl short loc_1399\nloc_13F8:\ncmp [rbp+var_1420C], 0FFFFFFFFh\njnz loc_14BB\nmov eax, [rbp+var_14218]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_14248]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_14224]\ncdqe\nmov [rbp+rax*8+var_141F0], rdx\nmov eax, [rbp+var_14218]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_14238]\nadd rax, rdx\nmov rcx, [rax]\nmov eax, [rbp+var_14224]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 5\nadd rax, rbp\nsub rax, 13890h\nmov [rax], rcx\nmov eax, [rbp+var_14224]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 5\nadd rax, rbp\nsub rax, 13888h\nmov qword ptr [rax], 0\nadd [rbp+var_14224], 1\njmp loc_15A2\nloc_14BB:\nmov [rbp+var_14204], 0\njmp short loc_14CE\nloc_14C7:\nadd [rbp+var_14204], 1\nloc_14CE:\nmov eax, [rbp+var_14204]\nmovsxd rcx, eax\nmov eax, [rbp+var_1420C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 2\nadd rax, rcx\nmov rax, [rbp+rax*8+var_13890]\ntest rax, rax\njz short loc_1512\ncmp [rbp+var_14204], 62h ; 'b'\njle short loc_14C7\nloc_1512:\nmov eax, [rbp+var_14218]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_14238]\nadd rax, rdx\nmov rcx, [rax]\nmov eax, [rbp+var_14204]\nmovsxd rsi, eax\nmov eax, [rbp+var_1420C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 2\nadd rax, rsi\nmov [rbp+rax*8+var_13890], rcx\nmov eax, [rbp+var_14204]\nadd eax, 1\nmovsxd rcx, eax\nmov eax, [rbp+var_1420C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 2\nadd rax, rcx\nmov [rbp+rax*8+var_13890], 0\nloc_15A2:\nadd [rbp+var_14218], 1\nloc_15A9:\nmov eax, [rbp+var_14218]\ncmp eax, [rbp+var_14240]\njl loc_121F\nmov eax, [rbp+var_14220]\ncmp eax, [rbp+var_1421C]\njz short loc_15D3\nmov eax, 0\njmp loc_16DA\nloc_15D3:\nmov [rbp+var_14200], 0\njmp loc_16C3\nloc_15E2:\nmov eax, [rbp+var_14200]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 5\nadd rax, rbp\nsub rax, 13890h\nmov rax, [rax]\nmov [rbp+s1], rax\nmov [rbp+var_141FC], 1\njmp short loc_167D\nloc_1623:\nmov eax, [rbp+var_141FC]\nmovsxd rcx, eax\nmov eax, [rbp+var_14200]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 2\nadd rax, rcx\nmov rdx, [rbp+rax*8+var_13890]\nmov rax, [rbp+s1]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_1676\nmov eax, 0\njmp short loc_16DA\nloc_1676:\nadd [rbp+var_141FC], 1\nloc_167D:\nmov eax, [rbp+var_141FC]\nmovsxd rcx, eax\nmov eax, [rbp+var_14200]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 2\nadd rax, rcx\nmov rax, [rbp+rax*8+var_13890]\ntest rax, rax\njnz loc_1623\nadd [rbp+var_14200], 1\nloc_16C3:\nmov eax, [rbp+var_14200]\ncmp eax, [rbp+var_14224]\njl loc_15E2\nmov eax, 1\nloc_16DA:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_16EE\ncall ___stack_chk_fail\nlocret_16EE:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3, int a4)\n{\n int v5; // eax\n int v6; // eax\n char v9; // [rsp+23h] [rbp-14225h]\n char v10; // [rsp+23h] [rbp-14225h]\n int v11; // [rsp+24h] [rbp-14224h]\n int v12; // [rsp+28h] [rbp-14220h]\n int v13; // [rsp+2Ch] [rbp-1421Ch]\n int i; // [rsp+30h] [rbp-14218h]\n int j; // [rsp+34h] [rbp-14214h]\n int k; // [rsp+38h] [rbp-14210h]\n int v17; // [rsp+3Ch] [rbp-1420Ch]\n int m; // [rsp+40h] [rbp-14208h]\n int n; // [rsp+44h] [rbp-14204h]\n int ii; // [rsp+48h] [rbp-14200h]\n int jj; // [rsp+4Ch] [rbp-141FCh]\n char *s1; // [rsp+50h] [rbp-141F8h]\n char *v23[62]; // [rsp+58h] [rbp-141F0h]\n char v24; // [rsp+248h] [rbp-14000h] BYREF\n char *s2[9690]; // [rsp+378h] [rbp-13ED0h]\n _QWORD v26[512]; // [rsp+13248h] [rbp-1000h] BYREF\n\n while ( v26 != (_QWORD *)&v24 )\n ;\n v26[511] = __readfsqword(0x28u);\n if ( a2 != a4 )\n return 0LL;\n v11 = 0;\n v12 = 0;\n v13 = 0;\n for ( i = 0; i < a4; ++i )\n {\n v9 = 0;\n for ( j = 0; j < v12; ++j )\n {\n if ( !strcmp(*(const char **)(8LL * i + a3), s2[j]) )\n {\n v9 = 1;\n break;\n }\n }\n if ( v9 != 1 )\n {\n v5 = v12++;\n s2[v5] = *(char **)(8LL * i + a3);\n }\n v10 = 0;\n for ( k = 0; k < v13; ++k )\n {\n if ( !strcmp(*(const char **)(8LL * i + a1), s2[k + 100]) )\n {\n v10 = 1;\n break;\n }\n }\n if ( v10 != 1 )\n {\n v6 = v13++;\n s2[v6 + 100] = *(char **)(8LL * i + a1);\n }\n v17 = -1;\n for ( m = 0; m < v11; ++m )\n {\n if ( !strcmp(*(const char **)(8LL * i + a3), v23[m]) )\n {\n v17 = m;\n break;\n }\n }\n if ( v17 == -1 )\n {\n v23[v11] = *(char **)(8LL * i + a3);\n s2[100 * v11 + 200] = *(char **)(8LL * i + a1);\n s2[100 * v11++ + 201] = 0LL;\n }\n else\n {\n for ( n = 0; (&s2[100 * v17 + 200])[n] && n <= 98; ++n )\n ;\n (&s2[100 * v17 + 200])[n] = *(char **)(8LL * i + a1);\n (&s2[100 * v17 + 201])[n] = 0LL;\n }\n }\n if ( v12 != v13 )\n return 0LL;\n for ( ii = 0; ii < v11; ++ii )\n {\n s1 = s2[100 * ii + 200];\n for ( jj = 1; (&s2[100 * ii + 200])[jj]; ++jj )\n {\n if ( strcmp(s1, (&s2[100 * ii + 200])[jj]) )\n return 0LL;\n }\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nlea r11, [rsp+var_14000]\nloc_1199:\nsub rsp, 1000h\nor [rsp+1000h+var_1000], 0\ncmp rsp, r11\njnz short loc_1199\nsub rsp, 250h\nmov [rbp+var_14238], rdi\nmov [rbp+var_1423C], esi\nmov [rbp+var_14248], rdx\nmov [rbp+var_14240], ecx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov eax, [rbp+var_1423C]\ncmp eax, [rbp+var_14240]\njz short loc_11F2\nmov eax, 0\njmp loc_16DA\nloc_11F2:\nmov [rbp+var_14224], 0\nmov [rbp+var_14220], 0\nmov [rbp+var_1421C], 0\nmov [rbp+var_14218], 0\njmp loc_15A9\nloc_121F:\nmov [rbp+var_14225], 0\nmov [rbp+var_14214], 0\njmp short loc_127E\nloc_1232:\nmov eax, [rbp+var_14214]\ncdqe\nmov rdx, [rbp+rax*8+s2]\nmov eax, [rbp+var_14218]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_14248]\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1277\nmov [rbp+var_14225], 1\njmp short loc_128C\nloc_1277:\nadd [rbp+var_14214], 1\nloc_127E:\nmov eax, [rbp+var_14214]\ncmp eax, [rbp+var_14220]\njl short loc_1232\nloc_128C:\nmovzx eax, [rbp+var_14225]\nxor eax, 1\ntest al, al\njz short loc_12D1\nmov eax, [rbp+var_14218]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_14248]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_14220]\nlea edx, [rax+1]\nmov [rbp+var_14220], edx\nmov rdx, [rcx]\ncdqe\nmov [rbp+rax*8+s2], rdx\nloc_12D1:\nmov [rbp+var_14225], 0\nmov [rbp+var_14210], 0\njmp short loc_1330\nloc_12E4:\nmov eax, [rbp+var_14210]\ncdqe\nmov rdx, [rbp+rax*8+var_13BB0]\nmov eax, [rbp+var_14218]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_14238]\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1329\nmov [rbp+var_14225], 1\njmp short loc_133E\nloc_1329:\nadd [rbp+var_14210], 1\nloc_1330:\nmov eax, [rbp+var_14210]\ncmp eax, [rbp+var_1421C]\njl short loc_12E4\nloc_133E:\nmovzx eax, [rbp+var_14225]\nxor eax, 1\ntest al, al\njz short loc_1383\nmov eax, [rbp+var_14218]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_14238]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_1421C]\nlea edx, [rax+1]\nmov [rbp+var_1421C], edx\nmov rdx, [rcx]\ncdqe\nmov [rbp+rax*8+var_13BB0], rdx\nloc_1383:\nmov [rbp+var_1420C], 0FFFFFFFFh\nmov [rbp+var_14208], 0\njmp short loc_13EA\nloc_1399:\nmov eax, [rbp+var_14208]\ncdqe\nmov rdx, [rbp+rax*8+var_141F0]\nmov eax, [rbp+var_14218]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_14248]\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_13E3\nmov eax, [rbp+var_14208]\nmov [rbp+var_1420C], eax\njmp short loc_13F8\nloc_13E3:\nadd [rbp+var_14208], 1\nloc_13EA:\nmov eax, [rbp+var_14208]\ncmp eax, [rbp+var_14224]\njl short loc_1399\nloc_13F8:\ncmp [rbp+var_1420C], 0FFFFFFFFh\njnz loc_14BB\nmov eax, [rbp+var_14218]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_14248]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_14224]\ncdqe\nmov [rbp+rax*8+var_141F0], rdx\nmov eax, [rbp+var_14218]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_14238]\nadd rax, rdx\nmov rcx, [rax]\nmov eax, [rbp+var_14224]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 5\nadd rax, rbp\nsub rax, 13890h\nmov [rax], rcx\nmov eax, [rbp+var_14224]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 5\nadd rax, rbp\nsub rax, 13888h\nmov qword ptr [rax], 0\nadd [rbp+var_14224], 1\njmp loc_15A2\nloc_14BB:\nmov [rbp+var_14204], 0\njmp short loc_14CE\nloc_14C7:\nadd [rbp+var_14204], 1\nloc_14CE:\nmov eax, [rbp+var_14204]\nmovsxd rcx, eax\nmov eax, [rbp+var_1420C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 2\nadd rax, rcx\nmov rax, [rbp+rax*8+var_13890]\ntest rax, rax\njz short loc_1512\ncmp [rbp+var_14204], 62h ; 'b'\njle short loc_14C7\nloc_1512:\nmov eax, [rbp+var_14218]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_14238]\nadd rax, rdx\nmov rcx, [rax]\nmov eax, [rbp+var_14204]\nmovsxd rsi, eax\nmov eax, [rbp+var_1420C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 2\nadd rax, rsi\nmov [rbp+rax*8+var_13890], rcx\nmov eax, [rbp+var_14204]\nadd eax, 1\nmovsxd rcx, eax\nmov eax, [rbp+var_1420C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 2\nadd rax, rcx\nmov [rbp+rax*8+var_13890], 0\nloc_15A2:\nadd [rbp+var_14218], 1\nloc_15A9:\nmov eax, [rbp+var_14218]\ncmp eax, [rbp+var_14240]\njl loc_121F\nmov eax, [rbp+var_14220]\ncmp eax, [rbp+var_1421C]\njz short loc_15D3\nmov eax, 0\njmp loc_16DA\nloc_15D3:\nmov [rbp+var_14200], 0\njmp loc_16C3\nloc_15E2:\nmov eax, [rbp+var_14200]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 5\nadd rax, rbp\nsub rax, 13890h\nmov rax, [rax]\nmov [rbp+s1], rax\nmov [rbp+var_141FC], 1\njmp short loc_167D\nloc_1623:\nmov eax, [rbp+var_141FC]\nmovsxd rcx, eax\nmov eax, [rbp+var_14200]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 2\nadd rax, rcx\nmov rdx, [rbp+rax*8+var_13890]\nmov rax, [rbp+s1]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_1676\nmov eax, 0\njmp short loc_16DA\nloc_1676:\nadd [rbp+var_141FC], 1\nloc_167D:\nmov eax, [rbp+var_141FC]\nmovsxd rcx, eax\nmov eax, [rbp+var_14200]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 2\nadd rax, rcx\nmov rax, [rbp+rax*8+var_13890]\ntest rax, rax\njnz loc_1623\nadd [rbp+var_14200], 1\nloc_16C3:\nmov eax, [rbp+var_14200]\ncmp eax, [rbp+var_14224]\njl loc_15E2\nmov eax, 1\nloc_16DA:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_16EE\ncall ___stack_chk_fail\nlocret_16EE:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2, __int64 a3, int a4)\n{\n int v5; // eax\n int v6; // eax\n char v9; // [rsp+23h] [rbp-14225h]\n char v10; // [rsp+23h] [rbp-14225h]\n int v11; // [rsp+24h] [rbp-14224h]\n int v12; // [rsp+28h] [rbp-14220h]\n int v13; // [rsp+2Ch] [rbp-1421Ch]\n int i; // [rsp+30h] [rbp-14218h]\n int j; // [rsp+34h] [rbp-14214h]\n int k; // [rsp+38h] [rbp-14210h]\n int v17; // [rsp+3Ch] [rbp-1420Ch]\n int m; // [rsp+40h] [rbp-14208h]\n int n; // [rsp+44h] [rbp-14204h]\n int ii; // [rsp+48h] [rbp-14200h]\n int jj; // [rsp+4Ch] [rbp-141FCh]\n char *s1; // [rsp+50h] [rbp-141F8h]\n char *v23[62]; // [rsp+58h] [rbp-141F0h]\n char v24; // [rsp+248h] [rbp-14000h] BYREF\n char *s2[9690]; // [rsp+378h] [rbp-13ED0h]\n _QWORD v26[512]; // [rsp+13248h] [rbp-1000h] BYREF\n\n while ( v26 != (_QWORD *)&v24 )\n ;\n v26[511] = __readfsqword(0x28u);\n if ( a2 != a4 )\n return 0LL;\n v11 = 0;\n v12 = 0;\n v13 = 0;\n for ( i = 0; i < a4; ++i )\n {\n v9 = 0;\n for ( j = 0; j < v12; ++j )\n {\n if ( !strcmp(*(const char **)(8LL * i + a3), s2[j]) )\n {\n v9 = 1;\n break;\n }\n }\n if ( v9 != 1 )\n {\n v5 = v12++;\n s2[v5] = *(char **)(8LL * i + a3);\n }\n v10 = 0;\n for ( k = 0; k < v13; ++k )\n {\n if ( !strcmp(*(const char **)(8LL * i + a1), s2[k + 100]) )\n {\n v10 = 1;\n break;\n }\n }\n if ( v10 != 1 )\n {\n v6 = v13++;\n s2[v6 + 100] = *(char **)(8LL * i + a1);\n }\n v17 = -1;\n for ( m = 0; m < v11; ++m )\n {\n if ( !strcmp(*(const char **)(8LL * i + a3), v23[m]) )\n {\n v17 = m;\n break;\n }\n }\n if ( v17 == -1 )\n {\n v23[v11] = *(char **)(8LL * i + a3);\n s2[100 * v11 + 200] = *(char **)(8LL * i + a1);\n s2[100 * v11++ + 201] = 0LL;\n }\n else\n {\n for ( n = 0; (&s2[100 * v17 + 200])[n] && n <= 98; ++n )\n ;\n (&s2[100 * v17 + 200])[n] = *(char **)(8LL * i + a1);\n (&s2[100 * v17 + 201])[n] = 0LL;\n }\n }\n if ( v12 != v13 )\n return 0LL;\n for ( ii = 0; ii < v11; ++ii )\n {\n s1 = s2[100 * ii + 200];\n for ( jj = 1; (&s2[100 * ii + 200])[jj]; ++jj )\n {\n if ( strcmp(s1, (&s2[100 * ii + 200])[jj]) )\n return 0LL;\n }\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2, long long a3, int a4) {\n int v5;\n int v6;\n char v9;\n char v10;\n int v11;\n int v12;\n int v13;\n int i;\n int j;\n int k;\n int v17;\n int m;\n int n;\n int ii;\n int jj;\n char *s1;\n char *v23[62];\n char v24;\n char *s2[9690];\n uint64_t v26[512];\n while (v26 != (uint64_t *)&v24)\n ;\n v26[511] = __readfsqword(40u);\n if (a2 != a4) return 0LL;\n v11 = 0;\n v12 = 0;\n v13 = 0;\n for (i = 0; i < a4; ++i) {\n v9 = 0;\n for (j = 0; j < v12; ++j) {\n if (!strcmp(*(const char **)(8LL * i + a3), s2[j])) {\n v9 = 1;\n break;\n }\n }\n if (v9 != 1) {\n v5 = v12++;\n s2[v5] = *(char **)(8LL * i + a3);\n }\n v10 = 0;\n for (k = 0; k < v13; ++k) {\n if (!strcmp(*(const char **)(8LL * i + a1), s2[k + 100])) {\n v10 = 1;\n break;\n }\n }\n if (v10 != 1) {\n v6 = v13++;\n s2[v6 + 100] = *(char **)(8LL * i + a1);\n }\n v17 = -1;\n for (m = 0; m < v11; ++m) {\n if (!strcmp(*(const char **)(8LL * i + a3), v23[m])) {\n v17 = m;\n break;\n }\n }\n if (v17 == -1) {\n v23[v11] = *(char **)(8LL * i + a3);\n s2[100 * v11 + 200] = *(char **)(8LL * i + a1);\n s2[100 * v11++ + 201] = 0LL;\n } else {\n for (n = 0; (&s2[100 * v17 + 200])[n] && n <= 98; ++n)\n ;\n (&s2[100 * v17 + 200])[n] = *(char **)(8LL * i + a1);\n (&s2[100 * v17 + 201])[n] = 0LL;\n }\n }\n if (v12 != v13) return 0LL;\n for (ii = 0; ii < v11; ++ii) {\n s1 = s2[100 * ii + 200];\n for (jj = 1; (&s2[100 * ii + 200])[jj]; ++jj) {\n if (strcmp(s1, (&s2[100 * ii + 200])[jj])) return 0LL;\n }\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3, int a4) {\n int v5;\n int v6;\n char v9;\n char v10;\n int v11;\n int v12;\n int v13;\n int i;\n int j;\n int k;\n int v17;\n int m;\n int n;\n int ii;\n int jj;\n char *s1;\n char *v23[62];\n char v24;\n char *s2[9690];\n uint64_t v26[512];\n while (v26 != (uint64_t *)&v24)\n ;\n v26[511] = __readfsqword(40u);\n if (a2 != a4) return 0LL;\n v11 = 0;\n v12 = 0;\n v13 = 0;\n for (i = 0; i < a4; ++i) {\n v9 = 0;\n for (j = 0; j < v12; ++j) {\n if (!strcmp(*(const char **)(8LL * i + a3), s2[j])) {\n v9 = 1;\n break;\n }\n }\n if (v9 != 1) {\n v5 = v12++;\n s2[v5] = *(char **)(8LL * i + a3);\n }\n v10 = 0;\n for (k = 0; k < v13; ++k) {\n if (!strcmp(*(const char **)(8LL * i + a1), s2[k + 100])) {\n v10 = 1;\n break;\n }\n }\n if (v10 != 1) {\n v6 = v13++;\n s2[v6 + 100] = *(char **)(8LL * i + a1);\n }\n v17 = -1;\n for (m = 0; m < v11; ++m) {\n if (!strcmp(*(const char **)(8LL * i + a3), v23[m])) {\n v17 = m;\n break;\n }\n }\n if (v17 == -1) {\n v23[v11] = *(char **)(8LL * i + a3);\n s2[100 * v11 + 200] = *(char **)(8LL * i + a1);\n s2[100 * v11++ + 201] = 0LL;\n } else {\n for (n = 0; (&s2[100 * v17 + 200])[n] && n <= 98; ++n)\n ;\n (&s2[100 * v17 + 200])[n] = *(char **)(8LL * i + a1);\n (&s2[100 * v17 + 201])[n] = 0LL;\n }\n }\n if (v12 != v13) return 0LL;\n for (ii = 0; ii < v11; ++ii) {\n s1 = s2[100 * ii + 200];\n for (jj = 1; (&s2[100 * ii + 200])[jj]; ++jj) {\n if (strcmp(s1, (&s2[100 * ii + 200])[jj])) return 0LL;\n }\n }\n return 1LL;\n}" + }, + { + "index": 74, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(char** colors, int colors_len, char** patterns, int patterns_len) {\n if (colors_len != patterns_len) {\n return false;\n }\n char* sdict_keys[100];\n char* sdict_values[100][100];\n int sdict_size = 0;\n char* pset[100];\n int pset_size = 0;\n char* sset[100];\n int sset_size = 0;\n for (int i = 0; i < patterns_len; i++) {\n bool found = false;\n for (int j = 0; j < pset_size; j++) {\n if (strcmp(patterns[i], pset[j]) == 0) {\n found = true;\n break;\n }\n }\n if (!found) {\n pset[pset_size++] = patterns[i];\n }\n found = false;\n for (int j = 0; j < sset_size; j++) {\n if (strcmp(colors[i], sset[j]) == 0) {\n found = true;\n break;\n }\n }\n if (!found) {\n sset[sset_size++] = colors[i];\n }\n int pattern_index = -1;\n for (int j = 0; j < sdict_size; j++) {\n if (strcmp(patterns[i], sdict_keys[j]) == 0) {\n pattern_index = j;\n break;\n }\n }\n if (pattern_index == -1) {\n sdict_keys[sdict_size] = patterns[i];\n sdict_values[sdict_size][0] = colors[i];\n sdict_values[sdict_size][1] = NULL;\n sdict_size++;\n }\n else {\n int k = 0;\n while (sdict_values[pattern_index][k] != NULL && k < 99) {\n k++;\n }\n sdict_values[pattern_index][k] = colors[i];\n sdict_values[pattern_index][k + 1] = NULL;\n }\n }\n if (pset_size != sset_size) {\n return false;\n }\n for (int i = 0; i < sdict_size; i++) {\n char* first_color = sdict_values[i][0];\n for (int j = 1; sdict_values[i][j] != NULL; j++) {\n if (strcmp(first_color, sdict_values[i][j]) != 0) {\n return false;\n }\n }\n }\n return true;\n}", + "test": "int main(){\n\n char* colors1[] = {\"red\", \"green\", \"green\"};\n\n char* patterns1[] = {\"a\", \"b\", \"b\"};\n\n assert(func0(colors1, 3, patterns1, 3) == true);\n\n\n\n char* colors2[] = {\"red\", \"green\", \"greenn\"};\n\n char* patterns2[] = {\"a\", \"b\", \"b\"};\n\n assert(func0(colors2, 3, patterns2, 3) == false);\n\n\n\n char* colors3[] = {\"red\", \"green\", \"greenn\"};\n\n char* patterns3[] = {\"a\", \"b\"};\n\n assert(func0(colors3, 3, patterns3, 2) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nlea -0x14000(%rsp),%r11\nsub $0x1000,%rsp\norq $0x0,(%rsp)\ncmp %r11,%rsp\njne 119f \nsub $0x228,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x14218(%rsp)\nxor %eax,%eax\ncmp %ecx,%esi\njne 1407 \ntest %ecx,%ecx\njle 1494 \nmov %rdx,%r14\nmov %rdi,%r15\nlea -0x1(%rcx),%eax\nlea 0x8(%rdx,%rax,8),%rax\nmov %rax,0x10(%rsp)\nmovl $0x0,0xc(%rsp)\nmovl $0x0,0x8(%rsp)\nmov $0x0,%ebp\nlea 0x358(%rsp),%rax\nmov %rax,0x18(%rsp)\nlea 0x678(%rsp),%rax\nmov %rax,0x20(%rsp)\nlea 0x990(%rsp),%rax\nmov %rax,0x28(%rsp)\njmp 129c \nmov %rax,%rbx\nmov %ebx,0x4(%rsp)\nmov 0x30(%rsp,%rbx,8),%rsi\nmov %r12,%rdi\ncallq 1090 \ntest %eax,%eax\nje 1358 \nlea 0x1(%rbx),%rax\ncmp %r13,%rbx\njne 122b \nmovslq %ebp,%rax\nmov (%r14),%rdx\nmov %rdx,0x30(%rsp,%rax,8)\nlea (%rax,%rax,4),%rax\nlea 0x0(,%rax,4),%rcx\nlea (%rax,%rcx,1),%rdx\nshl $0x5,%rdx\nmov (%r15),%rsi\nmov %rsi,0x990(%rsp,%rdx,1)\nmovq $0x0,0x998(%rsp,%rdx,1)\nadd $0x1,%ebp\nadd $0x8,%r14\nadd $0x8,%r15\ncmp 0x10(%rsp),%r14\nje 13f8 \ncmpl $0x0,0x8(%rsp)\njle 12d6 \nmov (%r14),%r12\nlea 0x350(%rsp),%rbx\nmov 0x8(%rsp),%eax\nlea -0x1(%rax),%eax\nmov 0x18(%rsp),%rcx\nlea (%rcx,%rax,8),%r13\nmov (%rbx),%rsi\nmov %r12,%rdi\ncallq 1090 \ntest %eax,%eax\nje 12ef \nadd $0x8,%rbx\ncmp %r13,%rbx\njne 12be \nmov 0x8(%rsp),%ecx\nmovslq %ecx,%rax\nmov (%r14),%rdx\nmov %rdx,0x350(%rsp,%rax,8)\nlea 0x1(%rcx),%eax\nmov %eax,0x8(%rsp)\nmov 0xc(%rsp),%eax\ntest %eax,%eax\njle 1326 \nmov (%r15),%r12\nlea 0x670(%rsp),%rbx\nlea -0x1(%rax),%eax\nmov 0x20(%rsp),%rcx\nlea (%rcx,%rax,8),%r13\nmov (%rbx),%rsi\nmov %r12,%rdi\ncallq 1090 \ntest %eax,%eax\nje 133f \nadd $0x8,%rbx\ncmp %r13,%rbx\njne 130e \nmov 0xc(%rsp),%ecx\nmovslq %ecx,%rax\nmov (%r15),%rdx\nmov %rdx,0x670(%rsp,%rax,8)\nlea 0x1(%rcx),%eax\nmov %eax,0xc(%rsp)\ntest %ebp,%ebp\njle 1250 \nmov (%r14),%r12\nlea -0x1(%rbp),%r13d\nmov $0x0,%ebx\njmpq 122e \nmov 0x4(%rsp),%ecx\ncmp $0xffffffff,%ecx\nje 1250 \nmovslq %ecx,%rdx\nlea (%rdx,%rdx,4),%rdx\nlea (%rdx,%rdx,4),%rdx\nshl $0x5,%rdx\ncmpq $0x0,0x990(%rsp,%rdx,1)\nje 13b4 \nmovslq 0x4(%rsp),%rax\nlea (%rax,%rax,4),%rax\nlea (%rax,%rax,4),%rdi\nshl $0x5,%rdi\nadd 0x28(%rsp),%rdi\nmov $0x1,%edx\nmov %edx,%eax\ncmpq $0x0,(%rdi,%rdx,8)\nsetne %sil\ncmp $0x62,%edx\nsetle %cl\nadd $0x1,%rdx\ntest %cl,%sil\njne 139a \nmovslq %eax,%rsi\nmovslq 0x4(%rsp),%rdx\nlea (%rdx,%rdx,4),%rdx\nlea 0x0(,%rdx,4),%rcx\nlea (%rdx,%rcx,1),%rdi\nlea (%rsi,%rdi,4),%rsi\nmov (%r15),%rdi\nmov %rdi,0x990(%rsp,%rsi,8)\nadd $0x1,%eax\ncltq\nadd %rcx,%rdx\nlea (%rax,%rdx,4),%rax\nmovq $0x0,0x990(%rsp,%rax,8)\njmpq 1289 \nmov $0x0,%eax\nmov 0xc(%rsp),%edx\ncmp %edx,0x8(%rsp)\nje 1430 \nmov 0x14218(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 14b2 \nadd $0x14228,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\ntest %ebp,%ebp\njle 149e \nlea 0x9a0(%rsp),%r12\nlea -0x1(%rbp),%eax\nlea (%rax,%rax,4),%rax\nlea (%rax,%rax,4),%rax\nshl $0x5,%rax\nlea 0xcc0(%rsp,%rax,1),%r13\nmov -0x10(%r12),%rbp\nmov -0x8(%r12),%rsi\ntest %rsi,%rsi\nje 147e \nmov %r12,%rbx\nmov %rbp,%rdi\ncallq 1090 \ntest %eax,%eax\njne 14a8 \nadd $0x8,%rbx\nmov -0x8(%rbx),%rsi\ntest %rsi,%rsi\njne 1465 \nadd $0x320,%r12\ncmp %r12,%r13\njne 1453 \nmov $0x1,%eax\njmpq 1407 \nmov $0x1,%eax\njmpq 1407 \nmov $0x1,%eax\njmpq 1407 \nmov $0x0,%eax\njmpq 1407 \ncallq 1070 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nlea r11, [rsp+30h+var_14030]\nloc_119F:\nsub rsp, 1000h\nor [rsp+1030h+var_1030], 0\ncmp rsp, r11\njnz short loc_119F\nsub rsp, 218h\nmov rax, fs:28h\nmov [rsp+1248h+arg_12FB8], rax\nxor eax, eax\ncmp esi, ecx\njnz loc_13EB\ntest ecx, ecx\njle loc_1473\nmov rbp, rdx\nmov r12, rdi\nmovsxd rcx, ecx\nlea rax, [rdx+rcx*8]\nmov [rsp+1248h+var_1238], rax\nmov [rsp+1248h+var_123C], 0\nmov [rsp+1248h+var_1240], 0\nmov r13d, 0\nlea rax, [rsp+1248h+var_8C8]\nmov [rsp+1248h+var_1230], rax\njmp loc_12AF\nloc_1214:\nmov ecx, [rsp+1248h+var_123C]\nmovsxd rax, ecx\nmov rdx, [r12]\nmov [rsp+rax*8+1248h+var_BE8], rdx\nlea eax, [rcx+1]\nmov [rsp+1248h+var_123C], eax\nloc_122E:\ntest r13d, r13d\njle short loc_125D\nmov r14, [rbp+0]\nmovsxd r15, r13d\nmov ebx, 0\nloc_123F:\nmov rsi, [rsp+rbx*8+1248h+s2]; s2\nmov rdi, r14; s1\ncall _strcmp\ntest eax, eax\njz loc_133C\nadd rbx, 1\ncmp rbx, r15\njnz short loc_123F\nloc_125D:\nmovsxd rax, r13d\nmov rdx, [rbp+0]\nmov [rsp+rax*8+1248h+s2], rdx\nlea rax, [rax+rax*4]\nlea rcx, ds:0[rax*4]\nlea rdx, [rax+rcx]\nshl rdx, 5\nmov rsi, [r12]\nmov [rsp+rdx+1248h+var_8C8], rsi\nmov [rsp+rdx+1248h+var_8C0], 0\nadd r13d, 1\nloc_1299:\nadd rbp, 8\nadd r12, 8\nmov rax, [rsp+1248h+var_1238]\ncmp rbp, rax\njz loc_13DC\nloc_12AF:\ncmp [rsp+1248h+var_1240], 0\njle short loc_12E3\nmov r14, [rbp+0]\nlea rbx, [rsp+1248h+var_F08]\nmovsxd rax, [rsp+1248h+var_1240]\nlea r15, [rbx+rax*8]\nloc_12CB:\nmov rsi, [rbx]; s2\nmov rdi, r14; s1\ncall _strcmp\ntest eax, eax\njz short loc_12FD\nadd rbx, 8\ncmp rbx, r15\njnz short loc_12CB\nloc_12E3:\nmov ecx, [rsp+1248h+var_1240]\nmovsxd rax, ecx\nmov rdx, [rbp+0]\nmov [rsp+rax*8+1248h+var_F08], rdx\nlea eax, [rcx+1]\nmov [rsp+1248h+var_1240], eax\nloc_12FD:\nmov eax, [rsp+1248h+var_123C]\ntest eax, eax\njle loc_1214\nmov r14, [r12]\nlea rbx, [rsp+1248h+var_BE8]\ncdqe\nlea r15, [rbx+rax*8]\nloc_131B:\nmov rsi, [rbx]; s2\nmov rdi, r14; s1\ncall _strcmp\ntest eax, eax\njz loc_122E\nadd rbx, 8\ncmp rbx, r15\njnz short loc_131B\njmp loc_1214\nloc_133C:\nmov r8d, ebx\ncmp ebx, 0FFFFFFFFh\njz loc_125D\nmovsxd rbx, ebx\nlea rdx, [rbx+rbx*4]\nlea rdx, [rdx+rdx*4]\nshl rdx, 5\ncmp [rsp+rdx+1248h+var_8C8], 0\njz short loc_1399\nmovsxd rax, r8d\nlea rax, [rax+rax*4]\nlea rdi, [rax+rax*4]\nshl rdi, 5\nmov rax, [rsp+1248h+var_1230]\nadd rdi, rax\nmov edx, 1\nloc_137E:\ncmp qword ptr [rdi+rdx*8], 0\nsetnz sil\ncmp edx, 62h ; 'b'\nsetle cl\nmov rax, rdx\nadd rdx, 1\ntest sil, cl\njnz short loc_137E\nloc_1399:\nmovsxd rsi, eax\nmovsxd r8, r8d\nlea rdx, [r8+r8*4]\nlea rcx, ds:0[rdx*4]\nlea rdi, [rdx+rcx]\nlea rsi, [rsi+rdi*4]\nmov rdi, [r12]\nmov [rsp+rsi*8+1248h+var_8C8], rdi\nadd eax, 1\ncdqe\nadd rdx, rcx\nlea rax, [rax+rdx*4]\nmov [rsp+rax*8+1248h+var_8C8], 0\njmp loc_1299\nloc_13DC:\nmov eax, 0\nmov edx, [rsp+1248h+var_123C]\ncmp [rsp+1248h+var_1240], edx\njz short loc_1414\nloc_13EB:\nmov rdx, [rsp+1248h+arg_12FB8]\nsub rdx, fs:28h\njnz loc_1491\nadd rsp, 14218h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1414:\ntest r13d, r13d\njle short loc_147D\nlea rbp, [rsp+1248h+var_8B8]\nmovsxd r13, r13d\nlea rax, [r13+r13*4+0]\nlea r13, [rax+rax*4]\nshl r13, 5\nadd r13, rbp\nloc_1434:\nmov r12, [rbp-10h]\nmov rsi, [rbp-8]; s2\ntest rsi, rsi\njz short loc_145D\nmov rbx, rbp\nloc_1444:\nmov rdi, r12; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1487\nadd rbx, 8\nmov rsi, [rbx-8]\ntest rsi, rsi\njnz short loc_1444\nloc_145D:\nadd rbp, 320h\ncmp rbp, r13\njnz short loc_1434\nmov eax, 1\njmp loc_13EB\nloc_1473:\nmov eax, 1\njmp loc_13EB\nloc_147D:\nmov eax, 1\njmp loc_13EB\nloc_1487:\nmov eax, 0\njmp loc_13EB\nloc_1491:\ncall ___stack_chk_fail", + "ida_pseudo": "// positive sp value has been detected, the output may be wrong!\n__int64 __fastcall func0(const char **a1, int a2, const char **a3, int a4)\n{\n __int64 result; // rax\n const char **v5; // rbp\n int v7; // r13d\n const char *v8; // r14\n __int64 v9; // rbx\n int v10; // eax\n __int64 v11; // rdx\n const char *v12; // r14\n const char **v13; // rbx\n const char *v14; // r14\n const char **v15; // rbx\n __int64 v16; // rdx\n bool v17; // si\n bool v18; // cl\n __int64 v19; // rdx\n __int64 v20; // rcx\n _OWORD *v21; // rbp\n _OWORD *v22; // r13\n const char *v23; // r12\n const char *v24; // rsi\n _OWORD *v25; // rbx\n int v26; // [rsp-210h] [rbp-14240h]\n int v27; // [rsp-20Ch] [rbp-1423Ch]\n const char **v28; // [rsp-208h] [rbp-14238h]\n _QWORD v29[63]; // [rsp-1F8h] [rbp-14228h]\n char v30; // [rsp+0h] [rbp-14030h] BYREF\n _QWORD v31[100]; // [rsp+128h] [rbp-13F08h] BYREF\n _QWORD v32[102]; // [rsp+448h] [rbp-13BE8h] BYREF\n _OWORD v33[136]; // [rsp+778h] [rbp-138B8h] BYREF\n __int64 v34; // [rsp+1000h] [rbp-13030h] BYREF\n unsigned __int64 v35; // [rsp+13FF0h] [rbp-40h]\n\n while ( &v30 != (char *)(&v34 - 10240) )\n ;\n v35 = __readfsqword(0x28u);\n result = 0LL;\n if ( a2 == a4 )\n {\n if ( a4 <= 0 )\n {\n return 1LL;\n }\n else\n {\n v5 = a3;\n v28 = &a3[a4];\n v27 = 0;\n v26 = 0;\n v7 = 0;\n do\n {\n if ( v26 <= 0 )\n {\nLABEL_16:\n v31[v26++] = *v5;\n }\n else\n {\n v12 = *v5;\n v13 = (const char **)v31;\n while ( strcmp(v12, *v13) )\n {\n if ( ++v13 == &v31[v26] )\n goto LABEL_16;\n }\n }\n if ( v27 <= 0 )\n {\nLABEL_5:\n v32[v27++] = *a1;\n }\n else\n {\n v14 = *a1;\n v15 = (const char **)v32;\n while ( strcmp(v14, *v15) )\n {\n if ( ++v15 == &v32[v27] )\n goto LABEL_5;\n }\n }\n if ( v7 <= 0 )\n goto LABEL_10;\n v8 = *v5;\n v9 = 0LL;\n while ( 1 )\n {\n v10 = strcmp(v8, (const char *)v29[v9]);\n if ( !v10 )\n break;\n if ( ++v9 == v7 )\n goto LABEL_10;\n }\n if ( (_DWORD)v9 == -1 )\n {\nLABEL_10:\n v29[v7] = *v5;\n v11 = 100LL * v7;\n v32[v11 + 100] = *a1;\n v32[v11 + 101] = 0LL;\n ++v7;\n }\n else\n {\n if ( v32[100 * (int)v9 + 100] )\n {\n v16 = 1LL;\n do\n {\n v17 = v32[100 * (int)v9 + 100 + v16] != 0LL;\n v18 = (int)v16 <= 98;\n v10 = v16++;\n }\n while ( v18 && v17 );\n }\n v19 = 5LL * (int)v9;\n v20 = 20LL * (int)v9;\n v32[4 * v19 + 100 + 4 * v20 + v10] = *a1;\n v32[4 * v20 + 101 + 4 * v19 + v10] = 0LL;\n }\n ++v5;\n ++a1;\n }\n while ( v5 != v28 );\n result = 0LL;\n if ( v26 == v27 )\n {\n if ( v7 <= 0 )\n {\n return 1LL;\n }\n else\n {\n v21 = v33;\n v22 = &v33[50 * v7];\n while ( 1 )\n {\n v23 = (const char *)*((_QWORD *)v21 - 2);\n v24 = (const char *)*((_QWORD *)v21 - 1);\n if ( v24 )\n break;\nLABEL_35:\n v21 += 50;\n if ( v21 == v22 )\n return 1LL;\n }\n v25 = v21;\n while ( !strcmp(v23, v24) )\n {\n v25 = (_OWORD *)((char *)v25 + 8);\n v24 = (const char *)*((_QWORD *)v25 - 1);\n if ( !v24 )\n goto LABEL_35;\n }\n return 0LL;\n }\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nlea r11, [rsp+30h+var_14030]\nloc_119F:\nsub rsp, 1000h\nor [rsp+1030h+var_1030], 0\ncmp rsp, r11\njnz short loc_119F\nsub rsp, 218h\nmov rax, fs:28h\nmov [rsp+1248h+arg_12FB8], rax\nxor eax, eax\ncmp esi, ecx\njnz loc_13EB\ntest ecx, ecx\njle loc_1473\nmov rbp, rdx\nmov r12, rdi\nmovsxd rcx, ecx\nlea rax, [rdx+rcx*8]\nmov [rsp+1248h+var_1238], rax\nmov [rsp+1248h+var_123C], 0\nmov [rsp+1248h+var_1240], 0\nmov r13d, 0\nlea rax, [rsp+1248h+var_8C8]\nmov [rsp+1248h+var_1230], rax\njmp loc_12AF\nloc_1214:\nmov ecx, [rsp+1248h+var_123C]\nmovsxd rax, ecx\nmov rdx, [r12]\nmov [rsp+rax*8+1248h+var_BE8], rdx\nlea eax, [rcx+1]\nmov [rsp+1248h+var_123C], eax\nloc_122E:\ntest r13d, r13d\njle short loc_125D\nmov r14, [rbp+0]\nmovsxd r15, r13d\nmov ebx, 0\nloc_123F:\nmov rsi, [rsp+rbx*8+1248h+s2]; s2\nmov rdi, r14; s1\ncall _strcmp\ntest eax, eax\njz loc_133C\nadd rbx, 1\ncmp rbx, r15\njnz short loc_123F\nloc_125D:\nmovsxd rax, r13d\nmov rdx, [rbp+0]\nmov [rsp+rax*8+1248h+s2], rdx\nlea rax, [rax+rax*4]\nlea rcx, ds:0[rax*4]\nlea rdx, [rax+rcx]\nshl rdx, 5\nmov rsi, [r12]\nmov [rsp+rdx+1248h+var_8C8], rsi\nmov [rsp+rdx+1248h+var_8C0], 0\nadd r13d, 1\nloc_1299:\nadd rbp, 8\nadd r12, 8\nmov rax, [rsp+1248h+var_1238]\ncmp rbp, rax\njz loc_13DC\nloc_12AF:\ncmp [rsp+1248h+var_1240], 0\njle short loc_12E3\nmov r14, [rbp+0]\nlea rbx, [rsp+1248h+var_F08]\nmovsxd rax, [rsp+1248h+var_1240]\nlea r15, [rbx+rax*8]\nloc_12CB:\nmov rsi, [rbx]; s2\nmov rdi, r14; s1\ncall _strcmp\ntest eax, eax\njz short loc_12FD\nadd rbx, 8\ncmp rbx, r15\njnz short loc_12CB\nloc_12E3:\nmov ecx, [rsp+1248h+var_1240]\nmovsxd rax, ecx\nmov rdx, [rbp+0]\nmov [rsp+rax*8+1248h+var_F08], rdx\nlea eax, [rcx+1]\nmov [rsp+1248h+var_1240], eax\nloc_12FD:\nmov eax, [rsp+1248h+var_123C]\ntest eax, eax\njle loc_1214\nmov r14, [r12]\nlea rbx, [rsp+1248h+var_BE8]\ncdqe\nlea r15, [rbx+rax*8]\nloc_131B:\nmov rsi, [rbx]; s2\nmov rdi, r14; s1\ncall _strcmp\ntest eax, eax\njz loc_122E\nadd rbx, 8\ncmp rbx, r15\njnz short loc_131B\njmp loc_1214\nloc_133C:\nmov r8d, ebx\ncmp ebx, 0FFFFFFFFh\njz loc_125D\nmovsxd rbx, ebx\nlea rdx, [rbx+rbx*4]\nlea rdx, [rdx+rdx*4]\nshl rdx, 5\ncmp [rsp+rdx+1248h+var_8C8], 0\njz short loc_1399\nmovsxd rax, r8d\nlea rax, [rax+rax*4]\nlea rdi, [rax+rax*4]\nshl rdi, 5\nmov rax, [rsp+1248h+var_1230]\nadd rdi, rax\nmov edx, 1\nloc_137E:\ncmp qword ptr [rdi+rdx*8], 0\nsetnz sil\ncmp edx, 62h ; 'b'\nsetle cl\nmov rax, rdx\nadd rdx, 1\ntest sil, cl\njnz short loc_137E\nloc_1399:\nmovsxd rsi, eax\nmovsxd r8, r8d\nlea rdx, [r8+r8*4]\nlea rcx, ds:0[rdx*4]\nlea rdi, [rdx+rcx]\nlea rsi, [rsi+rdi*4]\nmov rdi, [r12]\nmov [rsp+rsi*8+1248h+var_8C8], rdi\nadd eax, 1\ncdqe\nadd rdx, rcx\nlea rax, [rax+rdx*4]\nmov [rsp+rax*8+1248h+var_8C8], 0\njmp loc_1299\nloc_13DC:\nmov eax, 0\nmov edx, [rsp+1248h+var_123C]\ncmp [rsp+1248h+var_1240], edx\njz short loc_1414\nloc_13EB:\nmov rdx, [rsp+1248h+arg_12FB8]\nsub rdx, fs:28h\njnz loc_1491\nadd rsp, 14218h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1414:\ntest r13d, r13d\njle short loc_147D\nlea rbp, [rsp+1248h+var_8B8]\nmovsxd r13, r13d\nlea rax, [r13+r13*4+0]\nlea r13, [rax+rax*4]\nshl r13, 5\nadd r13, rbp\nloc_1434:\nmov r12, [rbp-10h]\nmov rsi, [rbp-8]; s2\ntest rsi, rsi\njz short loc_145D\nmov rbx, rbp\nloc_1444:\nmov rdi, r12; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1487\nadd rbx, 8\nmov rsi, [rbx-8]\ntest rsi, rsi\njnz short loc_1444\nloc_145D:\nadd rbp, 320h\ncmp rbp, r13\njnz short loc_1434\nmov eax, 1\njmp loc_13EB\nloc_1473:\nmov eax, 1\njmp loc_13EB\nloc_147D:\nmov eax, 1\njmp loc_13EB\nloc_1487:\nmov eax, 0\njmp loc_13EB\nloc_1491:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "// positive sp value has been detected, the output may be wrong!\n__int64 __fastcall sub_1189(const char **a1, int a2, const char **a3, int a4)\n{\n __int64 result; // rax\n const char **v5; // rbp\n int v7; // r13d\n const char *v8; // r14\n __int64 v9; // rbx\n int v10; // eax\n __int64 v11; // rdx\n const char *v12; // r14\n const char **v13; // rbx\n const char *v14; // r14\n const char **v15; // rbx\n __int64 v16; // rdx\n bool v17; // si\n bool v18; // cl\n __int64 v19; // rdx\n __int64 v20; // rcx\n _OWORD *v21; // rbp\n _OWORD *v22; // r13\n const char *v23; // r12\n const char *v24; // rsi\n _OWORD *v25; // rbx\n int v26; // [rsp-210h] [rbp-14240h]\n int v27; // [rsp-20Ch] [rbp-1423Ch]\n const char **v28; // [rsp-208h] [rbp-14238h]\n _QWORD v29[63]; // [rsp-1F8h] [rbp-14228h]\n char v30; // [rsp+0h] [rbp-14030h] BYREF\n _QWORD v31[100]; // [rsp+128h] [rbp-13F08h] BYREF\n _QWORD v32[102]; // [rsp+448h] [rbp-13BE8h] BYREF\n _OWORD v33[136]; // [rsp+778h] [rbp-138B8h] BYREF\n __int64 v34; // [rsp+1000h] [rbp-13030h] BYREF\n unsigned __int64 v35; // [rsp+13FF0h] [rbp-40h]\n\n while ( &v30 != (char *)(&v34 - 10240) )\n ;\n v35 = __readfsqword(0x28u);\n result = 0LL;\n if ( a2 == a4 )\n {\n if ( a4 <= 0 )\n {\n return 1LL;\n }\n else\n {\n v5 = a3;\n v28 = &a3[a4];\n v27 = 0;\n v26 = 0;\n v7 = 0;\n do\n {\n if ( v26 <= 0 )\n {\nLABEL_16:\n v31[v26++] = *v5;\n }\n else\n {\n v12 = *v5;\n v13 = (const char **)v31;\n while ( strcmp(v12, *v13) )\n {\n if ( ++v13 == &v31[v26] )\n goto LABEL_16;\n }\n }\n if ( v27 <= 0 )\n {\nLABEL_5:\n v32[v27++] = *a1;\n }\n else\n {\n v14 = *a1;\n v15 = (const char **)v32;\n while ( strcmp(v14, *v15) )\n {\n if ( ++v15 == &v32[v27] )\n goto LABEL_5;\n }\n }\n if ( v7 <= 0 )\n goto LABEL_10;\n v8 = *v5;\n v9 = 0LL;\n while ( 1 )\n {\n v10 = strcmp(v8, (const char *)v29[v9]);\n if ( !v10 )\n break;\n if ( ++v9 == v7 )\n goto LABEL_10;\n }\n if ( (_DWORD)v9 == -1 )\n {\nLABEL_10:\n v29[v7] = *v5;\n v11 = 100LL * v7;\n v32[v11 + 100] = *a1;\n v32[v11 + 101] = 0LL;\n ++v7;\n }\n else\n {\n if ( v32[100 * (int)v9 + 100] )\n {\n v16 = 1LL;\n do\n {\n v17 = v32[100 * (int)v9 + 100 + v16] != 0LL;\n v18 = (int)v16 <= 98;\n v10 = v16++;\n }\n while ( v18 && v17 );\n }\n v19 = 5LL * (int)v9;\n v20 = 20LL * (int)v9;\n v32[4 * v19 + 100 + 4 * v20 + v10] = *a1;\n v32[4 * v20 + 101 + 4 * v19 + v10] = 0LL;\n }\n ++v5;\n ++a1;\n }\n while ( v5 != v28 );\n result = 0LL;\n if ( v26 == v27 )\n {\n if ( v7 <= 0 )\n {\n return 1LL;\n }\n else\n {\n v21 = v33;\n v22 = &v33[50 * v7];\n while ( 1 )\n {\n v23 = (const char *)*((_QWORD *)v21 - 2);\n v24 = (const char *)*((_QWORD *)v21 - 1);\n if ( v24 )\n break;\nLABEL_35:\n v21 += 50;\n if ( v21 == v22 )\n return 1LL;\n }\n v25 = v21;\n while ( !strcmp(v23, v24) )\n {\n v25 = (_OWORD *)((char *)v25 + 8);\n v24 = (const char *)*((_QWORD *)v25 - 1);\n if ( !v24 )\n goto LABEL_35;\n }\n return 0LL;\n }\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(const char **a1, int a2, const char **a3, int a4) {\n long long result;\n const char **v5;\n int v7;\n const char *v8;\n long long v9;\n int v10;\n long long v11;\n const char *v12;\n const char **v13;\n const char *v14;\n const char **v15;\n long long v16;\n bool v17;\n bool v18;\n long long v19;\n long long v20;\n long double *v21;\n long double *v22;\n const char *v23;\n const char *v24;\n long double *v25;\n int v26;\n int v27;\n const char **v28;\n uint64_t v29[63];\n char v30;\n uint64_t v31[100];\n uint64_t v32[102];\n long double v33[136];\n long long v34;\n unsigned long long v35;\n while (&v30 != (char *)(&v34 - 10240))\n ;\n v35 = __readfsqword(40u);\n result = 0LL;\n if (a2 == a4) {\n if (a4 <= 0) {\n return 1LL;\n } else {\n v5 = a3;\n v28 = &a3[a4];\n v27 = 0;\n v26 = 0;\n v7 = 0;\n do {\n if (v26 <= 0) {\n LABEL_16:\n v31[v26++] = *v5;\n } else {\n v12 = *v5;\n v13 = (const char **)v31;\n while (strcmp(v12, *v13)) {\n if (++v13 == &v31[v26]) goto LABEL_16;\n }\n }\n if (v27 <= 0) {\n LABEL_5:\n v32[v27++] = *a1;\n } else {\n v14 = *a1;\n v15 = (const char **)v32;\n while (strcmp(v14, *v15)) {\n if (++v15 == &v32[v27]) goto LABEL_5;\n }\n }\n if (v7 <= 0) goto LABEL_10;\n v8 = *v5;\n v9 = 0LL;\n while (1) {\n v10 = strcmp(v8, (const char *)v29[v9]);\n if (!v10) break;\n if (++v9 == v7) goto LABEL_10;\n }\n if ((uint32_t)v9 == -1) {\n LABEL_10:\n v29[v7] = *v5;\n v11 = 100LL * v7;\n v32[v11 + 100] = *a1;\n v32[v11 + 101] = 0LL;\n ++v7;\n } else {\n if (v32[100 * (int)v9 + 100]) {\n v16 = 1LL;\n do {\n v17 = v32[100 * (int)v9 + 100 + v16] != 0LL;\n v18 = (int)v16 <= 98;\n v10 = v16++;\n } while (v18 && v17);\n }\n v19 = 5LL * (int)v9;\n v20 = 20LL * (int)v9;\n v32[4 * v19 + 100 + 4 * v20 + v10] = *a1;\n v32[4 * v20 + 101 + 4 * v19 + v10] = 0LL;\n }\n ++v5;\n ++a1;\n } while (v5 != v28);\n result = 0LL;\n if (v26 == v27) {\n if (v7 <= 0) {\n return 1LL;\n } else {\n v21 = v33;\n v22 = &v33[50 * v7];\n while (1) {\n v23 = (const char *)*((uint64_t *)v21 - 2);\n v24 = (const char *)*((uint64_t *)v21 - 1);\n if (v24) break;\n LABEL_35:\n v21 += 50;\n if (v21 == v22) return 1LL;\n }\n v25 = v21;\n while (!strcmp(v23, v24)) {\n v25 = (long double *)((char *)v25 + 8);\n v24 = (const char *)*((uint64_t *)v25 - 1);\n if (!v24) goto LABEL_35;\n }\n return 0LL;\n }\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(const char **a1, int a2, const char **a3, int a4) {\n long long result;\n const char **v5;\n int v7;\n const char *v8;\n long long v9;\n int v10;\n long long v11;\n const char *v12;\n const char **v13;\n const char *v14;\n const char **v15;\n long long v16;\n bool v17;\n bool v18;\n long long v19;\n long long v20;\n long double *v21;\n long double *v22;\n const char *v23;\n const char *v24;\n long double *v25;\n int v26;\n int v27;\n const char **v28;\n uint64_t v29[63];\n char v30;\n uint64_t v31[100];\n uint64_t v32[102];\n long double v33[136];\n long long v34;\n unsigned long long v35;\n while (&v30 != (char *)(&v34 - 10240))\n ;\n v35 = __readfsqword(40u);\n result = 0LL;\n if (a2 == a4) {\n if (a4 <= 0) {\n return 1LL;\n } else {\n v5 = a3;\n v28 = &a3[a4];\n v27 = 0;\n v26 = 0;\n v7 = 0;\n do {\n if (v26 <= 0) {\n LABEL_16:\n v31[v26++] = *v5;\n } else {\n v12 = *v5;\n v13 = (const char **)v31;\n while (strcmp(v12, *v13)) {\n if (++v13 == &v31[v26]) goto LABEL_16;\n }\n }\n if (v27 <= 0) {\n LABEL_5:\n v32[v27++] = *a1;\n } else {\n v14 = *a1;\n v15 = (const char **)v32;\n while (strcmp(v14, *v15)) {\n if (++v15 == &v32[v27]) goto LABEL_5;\n }\n }\n if (v7 <= 0) goto LABEL_10;\n v8 = *v5;\n v9 = 0LL;\n while (1) {\n v10 = strcmp(v8, (const char *)v29[v9]);\n if (!v10) break;\n if (++v9 == v7) goto LABEL_10;\n }\n if ((uint32_t)v9 == -1) {\n LABEL_10:\n v29[v7] = *v5;\n v11 = 100LL * v7;\n v32[v11 + 100] = *a1;\n v32[v11 + 101] = 0LL;\n ++v7;\n } else {\n if (v32[100 * (int)v9 + 100]) {\n v16 = 1LL;\n do {\n v17 = v32[100 * (int)v9 + 100 + v16] != 0LL;\n v18 = (int)v16 <= 98;\n v10 = v16++;\n } while (v18 && v17);\n }\n v19 = 5LL * (int)v9;\n v20 = 20LL * (int)v9;\n v32[4 * v19 + 100 + 4 * v20 + v10] = *a1;\n v32[4 * v20 + 101 + 4 * v19 + v10] = 0LL;\n }\n ++v5;\n ++a1;\n } while (v5 != v28);\n result = 0LL;\n if (v26 == v27) {\n if (v7 <= 0) {\n return 1LL;\n } else {\n v21 = v33;\n v22 = &v33[50 * v7];\n while (1) {\n v23 = (const char *)*((uint64_t *)v21 - 2);\n v24 = (const char *)*((uint64_t *)v21 - 1);\n if (v24) break;\n LABEL_35:\n v21 += 50;\n if (v21 == v22) return 1LL;\n }\n v25 = v21;\n while (!strcmp(v23, v24)) {\n v25 = (long double *)((char *)v25 + 8);\n v24 = (const char *)*((uint64_t *)v25 - 1);\n if (!v24) goto LABEL_35;\n }\n return 0LL;\n }\n }\n }\n }\n return result;\n}" + }, + { + "index": 74, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(char** colors, int colors_len, char** patterns, int patterns_len) {\n if (colors_len != patterns_len) {\n return false;\n }\n char* sdict_keys[100];\n char* sdict_values[100][100];\n int sdict_size = 0;\n char* pset[100];\n int pset_size = 0;\n char* sset[100];\n int sset_size = 0;\n for (int i = 0; i < patterns_len; i++) {\n bool found = false;\n for (int j = 0; j < pset_size; j++) {\n if (strcmp(patterns[i], pset[j]) == 0) {\n found = true;\n break;\n }\n }\n if (!found) {\n pset[pset_size++] = patterns[i];\n }\n found = false;\n for (int j = 0; j < sset_size; j++) {\n if (strcmp(colors[i], sset[j]) == 0) {\n found = true;\n break;\n }\n }\n if (!found) {\n sset[sset_size++] = colors[i];\n }\n int pattern_index = -1;\n for (int j = 0; j < sdict_size; j++) {\n if (strcmp(patterns[i], sdict_keys[j]) == 0) {\n pattern_index = j;\n break;\n }\n }\n if (pattern_index == -1) {\n sdict_keys[sdict_size] = patterns[i];\n sdict_values[sdict_size][0] = colors[i];\n sdict_values[sdict_size][1] = NULL;\n sdict_size++;\n }\n else {\n int k = 0;\n while (sdict_values[pattern_index][k] != NULL && k < 99) {\n k++;\n }\n sdict_values[pattern_index][k] = colors[i];\n sdict_values[pattern_index][k + 1] = NULL;\n }\n }\n if (pset_size != sset_size) {\n return false;\n }\n for (int i = 0; i < sdict_size; i++) {\n char* first_color = sdict_values[i][0];\n for (int j = 1; sdict_values[i][j] != NULL; j++) {\n if (strcmp(first_color, sdict_values[i][j]) != 0) {\n return false;\n }\n }\n }\n return true;\n}", + "test": "int main(){\n\n char* colors1[] = {\"red\", \"green\", \"green\"};\n\n char* patterns1[] = {\"a\", \"b\", \"b\"};\n\n assert(func0(colors1, 3, patterns1, 3) == true);\n\n\n\n char* colors2[] = {\"red\", \"green\", \"greenn\"};\n\n char* patterns2[] = {\"a\", \"b\", \"b\"};\n\n assert(func0(colors2, 3, patterns2, 3) == false);\n\n\n\n char* colors3[] = {\"red\", \"green\", \"greenn\"};\n\n char* patterns3[] = {\"a\", \"b\"};\n\n assert(func0(colors3, 3, patterns3, 2) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov %esi,%r8d\nmov %rdx,%rsi\ncmp %ecx,%r8d\njne 1630 \nmov %r8d,%edx\njmpq 12a0 \nnopw 0x0(%rax,%rax,1)\nxor %eax,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nlea r11, [rsp+30h+var_14030]\nloc_1366:\nsub rsp, 1000h\nor [rsp+1030h+var_1030], 0\ncmp rsp, r11\njnz short loc_1366\nsub rsp, 228h\nmov rax, fs:28h\nmov [rsp+1258h+arg_12FB8], rax\nxor eax, eax\ncmp esi, ecx\njnz loc_15A4\ntest esi, esi\njle loc_1650\nmovsxd rsi, esi\nmov [rsp+1258h+var_1240], rdi\nmov r13, rdx\nlea rax, [rdx+rsi*8]\nmov [rsp+1258h+var_1248], 0\nmov [rsp+1258h+var_1238], rax\nlea rax, [rsp+1258h+var_8C8]\nmov [rsp+1258h+var_124C], 0\nmov [rsp+1258h+var_1244], 0\nmov [rsp+1258h+var_1230], rax\nnop word ptr [rax+rax+00h]\nloc_13E0:\nmov eax, [rsp+1258h+var_124C]\nmov rbx, [r13+0]\ntest eax, eax\njle loc_1620\nmovsxd r12, [rsp+1258h+var_124C]\nlea r14, [rsp+1258h+var_F08]\nlea rbp, [r14+r12*8]\njmp short loc_1415\nloc_1408:\nadd r14, 8\ncmp rbp, r14\njz loc_1628\nloc_1415:\nmov rsi, [r14]; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1408\nloc_1424:\nmov rax, [rsp+1258h+var_1240]\nmov ecx, [rsp+1258h+var_1248]\nmov rbp, [rax]\ntest ecx, ecx\njle loc_15FF\nmovsxd r14, [rsp+1258h+var_1248]\nlea r15, [rsp+1258h+var_BE8]\nlea r12, [r15+r14*8]\njmp short loc_145D\nloc_1450:\nadd r15, 8\ncmp r15, r12\njz loc_1608\nloc_145D:\nmov rsi, [r15]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1450\nloc_146C:\nmov edx, [rsp+1258h+var_1244]\nmovsxd r12, [rsp+1258h+var_1244]\nxor r15d, r15d\nlea r14, [rsp+1258h+var_1228]\ntest edx, edx\njg short loc_149D\njmp loc_15D0\nloc_1490:\nadd r15, 1\ncmp r15, r12\njz loc_15D0\nloc_149D:\nmov rsi, [r14+r15*8]; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1490\nmovsxd rdx, r15d\nmov rcx, [rsp+1258h+var_1230]\nmovsxd rsi, r15d\nlea rdx, [rdx+rdx*4]\nlea rdi, [rdx+rdx*4]\nmov edx, 1\nshl rdi, 5\nadd rcx, rdi\ncmp [rsp+rdi+1258h+var_8C8], 0\njnz short loc_14EE\njmp short loc_14FA\nloc_14E0:\nadd rdx, 1\ncmp rdx, 64h ; 'd'\njz loc_165A\nloc_14EE:\ncmp qword ptr [rcx+rdx*8], 0\njnz short loc_14E0\nmov eax, edx\nadd edx, 1\nloc_14FA:\nlea rcx, [rsi+rsi*4]\ncdqe\nmovsxd rdx, edx\nlea rcx, [rcx+rcx*4]\nshl rcx, 2\nadd rax, rcx\nadd rcx, rdx\nmov [rsp+rax*8+1258h+var_8C8], rbp\nmov [rsp+rcx*8+1258h+var_8C8], 0\nloc_1525:\nmov rax, [rsp+1258h+var_1238]\nadd r13, 8\nadd [rsp+1258h+var_1240], 8\ncmp r13, rax\njnz loc_13E0\nmov ecx, [rsp+1258h+var_1248]\ncmp [rsp+1258h+var_124C], ecx\njnz short loc_15A4\nmovsxd rax, [rsp+1258h+var_1244]\ntest eax, eax\njle loc_1650\nlea rax, [rax+rax*4]\nlea rbp, [rsp+1258h+var_8B8]\nlea r13, [rax+rax*4]\nshl r13, 5\nadd r13, rbp\nloc_156B:\nmov rsi, [rbp-8]\nmov r12, [rbp-10h]\ntest rsi, rsi\njz loc_1640\nmov rbx, rbp\njmp short loc_1598\nloc_1588:\nmov rsi, [rbx]; s2\nadd rbx, 8\ntest rsi, rsi\njz loc_1640\nloc_1598:\nmov rdi, r12; s1\ncall _strcmp\ntest eax, eax\njz short loc_1588\nloc_15A4:\nxor eax, eax\nloc_15A6:\nmov rdx, [rsp+1258h+arg_12FB8]\nsub rdx, fs:28h\njnz loc_1664\nadd rsp, 14228h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15D0:\nlea rax, [r12+r12*4]\nadd [rsp+1258h+var_1244], 1\nlea rax, [rax+rax*4]\nmov [rsp+r12*8+1258h+var_1228], rbx\nshl rax, 5\nmov [rsp+rax+1258h+var_8C8], rbp\nmov [rsp+rax+1258h+var_8C0], 0\njmp loc_1525\nloc_15FF:\nmovsxd r14, [rsp+1258h+var_1248]\nnop dword ptr [rax+00h]\nloc_1608:\nmov eax, [rsp+1258h+var_1248]\nmov [rsp+r14*8+1258h+var_BE8], rbp\nadd eax, 1\nmov [rsp+1258h+var_1248], eax\njmp loc_146C\nloc_1620:\nmovsxd r12, [rsp+1258h+var_124C]\nnop dword ptr [rax]\nloc_1628:\nmov eax, [rsp+1258h+var_124C]\nmov [rsp+r12*8+1258h+var_F08], rbx\nadd eax, 1\nmov [rsp+1258h+var_124C], eax\njmp loc_1424\nloc_1640:\nadd rbp, 320h\ncmp rbp, r13\njnz loc_156B\nloc_1650:\nmov eax, 1\njmp loc_15A6\nloc_165A:\nmov eax, 63h ; 'c'\njmp loc_14FA\nloc_1664:\ncall ___stack_chk_fail", + "ida_pseudo": "// positive sp value has been detected, the output may be wrong!\n__int64 __fastcall func0(const char **a1, int a2, const char **a3, int a4)\n{\n const char **v4; // r13\n const char *v5; // rbx\n __int64 v6; // r12\n const char **v7; // r14\n const char *v8; // rbp\n __int64 v9; // r14\n const char **v10; // r15\n __int64 v11; // r12\n __int64 v12; // r15\n int v13; // eax\n __int64 v14; // rdx\n _OWORD *v15; // rbp\n const char *v16; // rsi\n const char *v17; // r12\n const char **v18; // rbx\n __int64 v20; // rax\n int v21; // [rsp-21Ch] [rbp-1424Ch]\n int v22; // [rsp-218h] [rbp-14248h]\n int v23; // [rsp-214h] [rbp-14244h]\n const char **v25; // [rsp-208h] [rbp-14238h]\n _QWORD v26[63]; // [rsp-1F8h] [rbp-14228h]\n char v27; // [rsp+0h] [rbp-14030h] BYREF\n _QWORD v28[100]; // [rsp+128h] [rbp-13F08h] BYREF\n _QWORD v29[102]; // [rsp+448h] [rbp-13BE8h] BYREF\n _OWORD v30[136]; // [rsp+778h] [rbp-138B8h] BYREF\n _QWORD v31[9734]; // [rsp+1000h] [rbp-13030h] BYREF\n\n while ( &v27 != (char *)&v31[-10240] )\n ;\n v31[9726] = __readfsqword(0x28u);\n if ( a2 != a4 )\n return 0LL;\n if ( a2 > 0 )\n {\n v4 = a3;\n v22 = 0;\n v25 = &a3[a2];\n v21 = 0;\n v23 = 0;\n do\n {\n v5 = *v4;\n if ( v21 <= 0 )\n {\n v6 = v21;\nLABEL_36:\n v28[v6] = v5;\n ++v21;\n }\n else\n {\n v6 = v21;\n v7 = (const char **)v28;\n while ( strcmp(v5, *v7) )\n {\n if ( &v28[v21] == ++v7 )\n goto LABEL_36;\n }\n }\n v8 = *a1;\n if ( v22 <= 0 )\n {\n v9 = v22;\nLABEL_34:\n v29[v9] = v8;\n ++v22;\n }\n else\n {\n v9 = v22;\n v10 = (const char **)v29;\n while ( strcmp(v8, *v10) )\n {\n if ( ++v10 == &v29[v22] )\n goto LABEL_34;\n }\n }\n v11 = v23;\n v12 = 0LL;\n if ( v23 > 0 )\n {\n while ( 1 )\n {\n v13 = strcmp(v5, (const char *)v26[v12]);\n if ( !v13 )\n break;\n if ( ++v12 == v23 )\n goto LABEL_32;\n }\n v14 = 1LL;\n if ( v29[100 * (int)v12 + 100] )\n {\n do\n {\n if ( !v29[100 * (int)v12 + 100 + v14] )\n {\n v13 = v14;\n LODWORD(v14) = v14 + 1;\n goto LABEL_22;\n }\n ++v14;\n }\n while ( v14 != 100 );\n v13 = 99;\n }\nLABEL_22:\n v29[100 * (int)v12 + 100 + v13] = v8;\n v29[100 * (int)v12 + 100 + (int)v14] = 0LL;\n }\n else\n {\nLABEL_32:\n ++v23;\n v26[v11] = v5;\n v20 = 100 * v11;\n v29[v20 + 100] = v8;\n v29[v20 + 101] = 0LL;\n }\n ++v4;\n ++a1;\n }\n while ( v4 != v25 );\n if ( v21 != v22 )\n return 0LL;\n if ( v23 > 0 )\n {\n v15 = v30;\n while ( 1 )\n {\n v16 = (const char *)*((_QWORD *)v15 - 1);\n v17 = (const char *)*((_QWORD *)v15 - 2);\n if ( v16 )\n break;\nLABEL_37:\n v15 += 50;\n if ( v15 == &v30[50 * v23] )\n return 1LL;\n }\n v18 = (const char **)v15;\n while ( !strcmp(v17, v16) )\n {\n v16 = *v18++;\n if ( !v16 )\n goto LABEL_37;\n }\n return 0LL;\n }\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1350:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nlea r11, [rsp+30h+var_14030]\nloc_1366:\nsub rsp, 1000h\nor [rsp+1030h+var_1030], 0\ncmp rsp, r11\njnz short loc_1366\nsub rsp, 228h\nmov rax, fs:28h\nmov [rsp+1258h+arg_12FB8], rax\nxor eax, eax\ncmp esi, ecx\njnz loc_15A4\ntest esi, esi\njle loc_1650\nmovsxd rsi, esi\nmov [rsp+1258h+var_1240], rdi\nmov r13, rdx\nlea rax, [rdx+rsi*8]\nmov [rsp+1258h+var_1248], 0\nmov [rsp+1258h+var_1238], rax\nlea rax, [rsp+1258h+var_8C8]\nmov [rsp+1258h+var_124C], 0\nmov [rsp+1258h+var_1244], 0\nmov [rsp+1258h+var_1230], rax\nnop word ptr [rax+rax+00h]\nloc_13E0:\nmov eax, [rsp+1258h+var_124C]\nmov rbx, [r13+0]\ntest eax, eax\njle loc_1620\nmovsxd r12, [rsp+1258h+var_124C]\nlea r14, [rsp+1258h+var_F08]\nlea rbp, [r14+r12*8]\njmp short loc_1415\nloc_1408:\nadd r14, 8\ncmp rbp, r14\njz loc_1628\nloc_1415:\nmov rsi, [r14]; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1408\nloc_1424:\nmov rax, [rsp+1258h+var_1240]\nmov ecx, [rsp+1258h+var_1248]\nmov rbp, [rax]\ntest ecx, ecx\njle loc_15FF\nmovsxd r14, [rsp+1258h+var_1248]\nlea r15, [rsp+1258h+var_BE8]\nlea r12, [r15+r14*8]\njmp short loc_145D\nloc_1450:\nadd r15, 8\ncmp r15, r12\njz loc_1608\nloc_145D:\nmov rsi, [r15]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1450\nloc_146C:\nmov edx, [rsp+1258h+var_1244]\nmovsxd r12, [rsp+1258h+var_1244]\nxor r15d, r15d\nlea r14, [rsp+1258h+var_1228]\ntest edx, edx\njg short loc_149D\njmp loc_15D0\nloc_1490:\nadd r15, 1\ncmp r15, r12\njz loc_15D0\nloc_149D:\nmov rsi, [r14+r15*8]; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1490\nmovsxd rdx, r15d\nmov rcx, [rsp+1258h+var_1230]\nmovsxd rsi, r15d\nlea rdx, [rdx+rdx*4]\nlea rdi, [rdx+rdx*4]\nmov edx, 1\nshl rdi, 5\nadd rcx, rdi\ncmp [rsp+rdi+1258h+var_8C8], 0\njnz short loc_14EE\njmp short loc_14FA\nloc_14E0:\nadd rdx, 1\ncmp rdx, 64h ; 'd'\njz loc_165A\nloc_14EE:\ncmp qword ptr [rcx+rdx*8], 0\njnz short loc_14E0\nmov eax, edx\nadd edx, 1\nloc_14FA:\nlea rcx, [rsi+rsi*4]\ncdqe\nmovsxd rdx, edx\nlea rcx, [rcx+rcx*4]\nshl rcx, 2\nadd rax, rcx\nadd rcx, rdx\nmov [rsp+rax*8+1258h+var_8C8], rbp\nmov [rsp+rcx*8+1258h+var_8C8], 0\nloc_1525:\nmov rax, [rsp+1258h+var_1238]\nadd r13, 8\nadd [rsp+1258h+var_1240], 8\ncmp r13, rax\njnz loc_13E0\nmov ecx, [rsp+1258h+var_1248]\ncmp [rsp+1258h+var_124C], ecx\njnz short loc_15A4\nmovsxd rax, [rsp+1258h+var_1244]\ntest eax, eax\njle loc_1650\nlea rax, [rax+rax*4]\nlea rbp, [rsp+1258h+var_8B8]\nlea r13, [rax+rax*4]\nshl r13, 5\nadd r13, rbp\nloc_156B:\nmov rsi, [rbp-8]\nmov r12, [rbp-10h]\ntest rsi, rsi\njz loc_1640\nmov rbx, rbp\njmp short loc_1598\nloc_1588:\nmov rsi, [rbx]; s2\nadd rbx, 8\ntest rsi, rsi\njz loc_1640\nloc_1598:\nmov rdi, r12; s1\ncall _strcmp\ntest eax, eax\njz short loc_1588\nloc_15A4:\nxor eax, eax\nloc_15A6:\nmov rdx, [rsp+1258h+arg_12FB8]\nsub rdx, fs:28h\njnz loc_1664\nadd rsp, 14228h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15D0:\nlea rax, [r12+r12*4]\nadd [rsp+1258h+var_1244], 1\nlea rax, [rax+rax*4]\nmov [rsp+r12*8+1258h+var_1228], rbx\nshl rax, 5\nmov [rsp+rax+1258h+var_8C8], rbp\nmov [rsp+rax+1258h+var_8C0], 0\njmp loc_1525\nloc_15FF:\nmovsxd r14, [rsp+1258h+var_1248]\nnop dword ptr [rax+00h]\nloc_1608:\nmov eax, [rsp+1258h+var_1248]\nmov [rsp+r14*8+1258h+var_BE8], rbp\nadd eax, 1\nmov [rsp+1258h+var_1248], eax\njmp loc_146C\nloc_1620:\nmovsxd r12, [rsp+1258h+var_124C]\nnop dword ptr [rax]\nloc_1628:\nmov eax, [rsp+1258h+var_124C]\nmov [rsp+r12*8+1258h+var_F08], rbx\nadd eax, 1\nmov [rsp+1258h+var_124C], eax\njmp loc_1424\nloc_1640:\nadd rbp, 320h\ncmp rbp, r13\njnz loc_156B\nloc_1650:\nmov eax, 1\njmp loc_15A6\nloc_165A:\nmov eax, 63h ; 'c'\njmp loc_14FA\nloc_1664:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "// positive sp value has been detected, the output may be wrong!\n__int64 __fastcall sub_1350(const char **a1, int a2, const char **a3, int a4)\n{\n const char **v4; // r13\n const char *v5; // rbx\n __int64 v6; // r12\n const char **v7; // r14\n const char *v8; // rbp\n __int64 v9; // r14\n const char **v10; // r15\n __int64 v11; // r12\n __int64 v12; // r15\n int v13; // eax\n __int64 v14; // rdx\n _OWORD *v15; // rbp\n const char *v16; // rsi\n const char *v17; // r12\n const char **v18; // rbx\n __int64 v20; // rax\n int v21; // [rsp-21Ch] [rbp-1424Ch]\n int v22; // [rsp-218h] [rbp-14248h]\n int v23; // [rsp-214h] [rbp-14244h]\n const char **v25; // [rsp-208h] [rbp-14238h]\n _QWORD v26[63]; // [rsp-1F8h] [rbp-14228h]\n char v27; // [rsp+0h] [rbp-14030h] BYREF\n _QWORD v28[100]; // [rsp+128h] [rbp-13F08h] BYREF\n _QWORD v29[102]; // [rsp+448h] [rbp-13BE8h] BYREF\n _OWORD v30[136]; // [rsp+778h] [rbp-138B8h] BYREF\n _QWORD v31[9734]; // [rsp+1000h] [rbp-13030h] BYREF\n\n while ( &v27 != (char *)&v31[-10240] )\n ;\n v31[9726] = __readfsqword(0x28u);\n if ( a2 != a4 )\n return 0LL;\n if ( a2 > 0 )\n {\n v4 = a3;\n v22 = 0;\n v25 = &a3[a2];\n v21 = 0;\n v23 = 0;\n do\n {\n v5 = *v4;\n if ( v21 <= 0 )\n {\n v6 = v21;\nLABEL_36:\n v28[v6] = v5;\n ++v21;\n }\n else\n {\n v6 = v21;\n v7 = (const char **)v28;\n while ( strcmp(v5, *v7) )\n {\n if ( &v28[v21] == ++v7 )\n goto LABEL_36;\n }\n }\n v8 = *a1;\n if ( v22 <= 0 )\n {\n v9 = v22;\nLABEL_34:\n v29[v9] = v8;\n ++v22;\n }\n else\n {\n v9 = v22;\n v10 = (const char **)v29;\n while ( strcmp(v8, *v10) )\n {\n if ( ++v10 == &v29[v22] )\n goto LABEL_34;\n }\n }\n v11 = v23;\n v12 = 0LL;\n if ( v23 > 0 )\n {\n while ( 1 )\n {\n v13 = strcmp(v5, (const char *)v26[v12]);\n if ( !v13 )\n break;\n if ( ++v12 == v23 )\n goto LABEL_32;\n }\n v14 = 1LL;\n if ( v29[100 * (int)v12 + 100] )\n {\n do\n {\n if ( !v29[100 * (int)v12 + 100 + v14] )\n {\n v13 = v14;\n LODWORD(v14) = v14 + 1;\n goto LABEL_22;\n }\n ++v14;\n }\n while ( v14 != 100 );\n v13 = 99;\n }\nLABEL_22:\n v29[100 * (int)v12 + 100 + v13] = v8;\n v29[100 * (int)v12 + 100 + (int)v14] = 0LL;\n }\n else\n {\nLABEL_32:\n ++v23;\n v26[v11] = v5;\n v20 = 100 * v11;\n v29[v20 + 100] = v8;\n v29[v20 + 101] = 0LL;\n }\n ++v4;\n ++a1;\n }\n while ( v4 != v25 );\n if ( v21 != v22 )\n return 0LL;\n if ( v23 > 0 )\n {\n v15 = v30;\n while ( 1 )\n {\n v16 = (const char *)*((_QWORD *)v15 - 1);\n v17 = (const char *)*((_QWORD *)v15 - 2);\n if ( v16 )\n break;\nLABEL_37:\n v15 += 50;\n if ( v15 == &v30[50 * v23] )\n return 1LL;\n }\n v18 = (const char **)v15;\n while ( !strcmp(v17, v16) )\n {\n v16 = *v18++;\n if ( !v16 )\n goto LABEL_37;\n }\n return 0LL;\n }\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1350(const char **a1, int a2, const char **a3, int a4) {\n const char **v4;\n const char *v5;\n long long v6;\n const char **v7;\n const char *v8;\n long long v9;\n const char **v10;\n long long v11;\n long long v12;\n int v13;\n long long v14;\n long double *v15;\n const char *v16;\n const char *v17;\n const char **v18;\n long long v20;\n int v21;\n int v22;\n int v23;\n const char **v25;\n uint64_t v26[63];\n char v27;\n uint64_t v28[100];\n uint64_t v29[102];\n long double v30[136];\n uint64_t v31[9734];\n while (&v27 != (char *)&v31[-10240])\n ;\n v31[9726] = __readfsqword(40u);\n if (a2 != a4) return 0LL;\n if (a2 > 0) {\n v4 = a3;\n v22 = 0;\n v25 = &a3[a2];\n v21 = 0;\n v23 = 0;\n do {\n v5 = *v4;\n if (v21 <= 0) {\n v6 = v21;\n LABEL_36:\n v28[v6] = v5;\n ++v21;\n } else {\n v6 = v21;\n v7 = (const char **)v28;\n while (strcmp(v5, *v7)) {\n if (&v28[v21] == ++v7) goto LABEL_36;\n }\n }\n v8 = *a1;\n if (v22 <= 0) {\n v9 = v22;\n LABEL_34:\n v29[v9] = v8;\n ++v22;\n } else {\n v9 = v22;\n v10 = (const char **)v29;\n while (strcmp(v8, *v10)) {\n if (++v10 == &v29[v22]) goto LABEL_34;\n }\n }\n v11 = v23;\n v12 = 0LL;\n if (v23 > 0) {\n while (1) {\n v13 = strcmp(v5, (const char *)v26[v12]);\n if (!v13) break;\n if (++v12 == v23) goto LABEL_32;\n }\n v14 = 1LL;\n if (v29[100 * (int)v12 + 100]) {\n do {\n if (!v29[100 * (int)v12 + 100 + v14]) {\n v13 = v14;\n LODWORD(v14) = v14 + 1;\n goto LABEL_22;\n }\n ++v14;\n } while (v14 != 100);\n v13 = 99;\n }\n LABEL_22:\n v29[100 * (int)v12 + 100 + v13] = v8;\n v29[100 * (int)v12 + 100 + (int)v14] = 0LL;\n } else {\n LABEL_32:\n ++v23;\n v26[v11] = v5;\n v20 = 100 * v11;\n v29[v20 + 100] = v8;\n v29[v20 + 101] = 0LL;\n }\n ++v4;\n ++a1;\n } while (v4 != v25);\n if (v21 != v22) return 0LL;\n if (v23 > 0) {\n v15 = v30;\n while (1) {\n v16 = (const char *)*((uint64_t *)v15 - 1);\n v17 = (const char *)*((uint64_t *)v15 - 2);\n if (v16) break;\n LABEL_37:\n v15 += 50;\n if (v15 == &v30[50 * v23]) return 1LL;\n }\n v18 = (const char **)v15;\n while (!strcmp(v17, v16)) {\n v16 = *v18++;\n if (!v16) goto LABEL_37;\n }\n return 0LL;\n }\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(const char **a1, int a2, const char **a3, int a4) {\n const char **v4;\n const char *v5;\n long long v6;\n const char **v7;\n const char *v8;\n long long v9;\n const char **v10;\n long long v11;\n long long v12;\n int v13;\n long long v14;\n long double *v15;\n const char *v16;\n const char *v17;\n const char **v18;\n long long v20;\n int v21;\n int v22;\n int v23;\n const char **v25;\n uint64_t v26[63];\n char v27;\n uint64_t v28[100];\n uint64_t v29[102];\n long double v30[136];\n uint64_t v31[9734];\n while (&v27 != (char *)&v31[-10240])\n ;\n v31[9726] = __readfsqword(40u);\n if (a2 != a4) return 0LL;\n if (a2 > 0) {\n v4 = a3;\n v22 = 0;\n v25 = &a3[a2];\n v21 = 0;\n v23 = 0;\n do {\n v5 = *v4;\n if (v21 <= 0) {\n v6 = v21;\n LABEL_36:\n v28[v6] = v5;\n ++v21;\n } else {\n v6 = v21;\n v7 = (const char **)v28;\n while (strcmp(v5, *v7)) {\n if (&v28[v21] == ++v7) goto LABEL_36;\n }\n }\n v8 = *a1;\n if (v22 <= 0) {\n v9 = v22;\n LABEL_34:\n v29[v9] = v8;\n ++v22;\n } else {\n v9 = v22;\n v10 = (const char **)v29;\n while (strcmp(v8, *v10)) {\n if (++v10 == &v29[v22]) goto LABEL_34;\n }\n }\n v11 = v23;\n v12 = 0LL;\n if (v23 > 0) {\n while (1) {\n v13 = strcmp(v5, (const char *)v26[v12]);\n if (!v13) break;\n if (++v12 == v23) goto LABEL_32;\n }\n v14 = 1LL;\n if (v29[100 * (int)v12 + 100]) {\n do {\n if (!v29[100 * (int)v12 + 100 + v14]) {\n v13 = v14;\n LODWORD(v14) = v14 + 1;\n goto LABEL_22;\n }\n ++v14;\n } while (v14 != 100);\n v13 = 99;\n }\n LABEL_22:\n v29[100 * (int)v12 + 100 + v13] = v8;\n v29[100 * (int)v12 + 100 + (int)v14] = 0LL;\n } else {\n LABEL_32:\n ++v23;\n v26[v11] = v5;\n v20 = 100 * v11;\n v29[v20 + 100] = v8;\n v29[v20 + 101] = 0LL;\n }\n ++v4;\n ++a1;\n } while (v4 != v25);\n if (v21 != v22) return 0LL;\n if (v23 > 0) {\n v15 = v30;\n while (1) {\n v16 = (const char *)*((uint64_t *)v15 - 1);\n v17 = (const char *)*((uint64_t *)v15 - 2);\n if (v16) break;\n LABEL_37:\n v15 += 50;\n if (v15 == &v30[50 * v23]) return 1LL;\n }\n v18 = (const char **)v15;\n while (!strcmp(v17, v16)) {\n v16 = *v18++;\n if (!v16) goto LABEL_37;\n }\n return 0LL;\n }\n }\n return 1LL;\n}" + }, + { + "index": 74, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(char** colors, int colors_len, char** patterns, int patterns_len) {\n if (colors_len != patterns_len) {\n return false;\n }\n char* sdict_keys[100];\n char* sdict_values[100][100];\n int sdict_size = 0;\n char* pset[100];\n int pset_size = 0;\n char* sset[100];\n int sset_size = 0;\n for (int i = 0; i < patterns_len; i++) {\n bool found = false;\n for (int j = 0; j < pset_size; j++) {\n if (strcmp(patterns[i], pset[j]) == 0) {\n found = true;\n break;\n }\n }\n if (!found) {\n pset[pset_size++] = patterns[i];\n }\n found = false;\n for (int j = 0; j < sset_size; j++) {\n if (strcmp(colors[i], sset[j]) == 0) {\n found = true;\n break;\n }\n }\n if (!found) {\n sset[sset_size++] = colors[i];\n }\n int pattern_index = -1;\n for (int j = 0; j < sdict_size; j++) {\n if (strcmp(patterns[i], sdict_keys[j]) == 0) {\n pattern_index = j;\n break;\n }\n }\n if (pattern_index == -1) {\n sdict_keys[sdict_size] = patterns[i];\n sdict_values[sdict_size][0] = colors[i];\n sdict_values[sdict_size][1] = NULL;\n sdict_size++;\n }\n else {\n int k = 0;\n while (sdict_values[pattern_index][k] != NULL && k < 99) {\n k++;\n }\n sdict_values[pattern_index][k] = colors[i];\n sdict_values[pattern_index][k + 1] = NULL;\n }\n }\n if (pset_size != sset_size) {\n return false;\n }\n for (int i = 0; i < sdict_size; i++) {\n char* first_color = sdict_values[i][0];\n for (int j = 1; sdict_values[i][j] != NULL; j++) {\n if (strcmp(first_color, sdict_values[i][j]) != 0) {\n return false;\n }\n }\n }\n return true;\n}", + "test": "int main(){\n\n char* colors1[] = {\"red\", \"green\", \"green\"};\n\n char* patterns1[] = {\"a\", \"b\", \"b\"};\n\n assert(func0(colors1, 3, patterns1, 3) == true);\n\n\n\n char* colors2[] = {\"red\", \"green\", \"greenn\"};\n\n char* patterns2[] = {\"a\", \"b\", \"b\"};\n\n assert(func0(colors2, 3, patterns2, 3) == false);\n\n\n\n char* colors3[] = {\"red\", \"green\", \"greenn\"};\n\n char* patterns3[] = {\"a\", \"b\"};\n\n assert(func0(colors3, 3, patterns3, 2) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nmov %esi,%r8d\nmov %rdx,%rsi\ncmp %ecx,%r8d\njne 1660 \nmov %r8d,%edx\njmpq 12d0 \nnopw 0x0(%rax,%rax,1)\nxor %eax,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nlea r11, [rsp+30h+var_14030]\nloc_1366:\nsub rsp, 1000h\nor [rsp+1030h+var_1030], 0\ncmp rsp, r11\njnz short loc_1366\nsub rsp, 228h\nmov rax, fs:28h\nmov [rsp+1258h+arg_12FB8], rax\nxor eax, eax\ncmp esi, ecx\njnz loc_15A4\ntest esi, esi\njle loc_1650\nmovsxd rsi, esi\nmov [rsp+1258h+var_1240], rdi\nmov r13, rdx\nlea rax, [rdx+rsi*8]\nmov [rsp+1258h+var_1248], 0\nmov [rsp+1258h+var_1238], rax\nlea rax, [rsp+1258h+var_8C8]\nmov [rsp+1258h+var_124C], 0\nmov [rsp+1258h+var_1244], 0\nmov [rsp+1258h+var_1230], rax\nnop word ptr [rax+rax+00h]\nloc_13E0:\nmov eax, [rsp+1258h+var_124C]\nmov rbx, [r13+0]\ntest eax, eax\njle loc_1620\nmovsxd r12, [rsp+1258h+var_124C]\nlea r14, [rsp+1258h+var_F08]\nlea rbp, [r14+r12*8]\njmp short loc_1415\nloc_1408:\nadd r14, 8\ncmp r14, rbp\njz loc_1628\nloc_1415:\nmov rsi, [r14]; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1408\nloc_1424:\nmov rax, [rsp+1258h+var_1240]\nmov ecx, [rsp+1258h+var_1248]\nmov rbp, [rax]\ntest ecx, ecx\njle loc_15FF\nmovsxd r14, [rsp+1258h+var_1248]\nlea r15, [rsp+1258h+var_BE8]\nlea r12, [r15+r14*8]\njmp short loc_145D\nloc_1450:\nadd r15, 8\ncmp r15, r12\njz loc_1608\nloc_145D:\nmov rsi, [r15]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1450\nloc_146C:\nmov edx, [rsp+1258h+var_1244]\nmovsxd r12, [rsp+1258h+var_1244]\nxor r15d, r15d\nlea r14, [rsp+1258h+var_1228]\ntest edx, edx\njg short loc_149D\njmp loc_15D0\nloc_1490:\nadd r15, 1\ncmp r15, r12\njz loc_15D0\nloc_149D:\nmov rsi, [r14+r15*8]; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1490\nmovsxd rdx, r15d\nmov rcx, [rsp+1258h+var_1230]\nmovsxd rsi, r15d\nlea rdx, [rdx+rdx*4]\nlea rdi, [rdx+rdx*4]\nmov edx, 1\nshl rdi, 5\nadd rcx, rdi\ncmp [rsp+rdi+1258h+var_8C8], 0\njnz short loc_14EE\njmp short loc_14FA\nloc_14E0:\nadd rdx, 1\ncmp rdx, 64h ; 'd'\njz loc_165A\nloc_14EE:\ncmp qword ptr [rcx+rdx*8], 0\njnz short loc_14E0\nmov eax, edx\nadd edx, 1\nloc_14FA:\nlea rcx, [rsi+rsi*4]\ncdqe\nmovsxd rdx, edx\nlea rcx, [rcx+rcx*4]\nshl rcx, 2\nadd rax, rcx\nadd rcx, rdx\nmov [rsp+rax*8+1258h+var_8C8], rbp\nmov [rsp+rcx*8+1258h+var_8C8], 0\nloc_1525:\nmov rax, [rsp+1258h+var_1238]\nadd r13, 8\nadd [rsp+1258h+var_1240], 8\ncmp r13, rax\njnz loc_13E0\nmov ecx, [rsp+1258h+var_1248]\ncmp [rsp+1258h+var_124C], ecx\njnz short loc_15A4\nmovsxd rax, [rsp+1258h+var_1244]\ntest eax, eax\njle loc_1650\nlea rax, [rax+rax*4]\nlea rbp, [rsp+1258h+var_8B8]\nlea r13, [rax+rax*4]\nshl r13, 5\nadd r13, rbp\nloc_156B:\nmov rsi, [rbp-8]\nmov r12, [rbp-10h]\ntest rsi, rsi\njz loc_1640\nmov rbx, rbp\njmp short loc_1598\nloc_1588:\nmov rsi, [rbx]; s2\nadd rbx, 8\ntest rsi, rsi\njz loc_1640\nloc_1598:\nmov rdi, r12; s1\ncall _strcmp\ntest eax, eax\njz short loc_1588\nloc_15A4:\nxor eax, eax\nloc_15A6:\nmov rdx, [rsp+1258h+arg_12FB8]\nsub rdx, fs:28h\njnz loc_1664\nadd rsp, 14228h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15D0:\nlea rax, [r12+r12*4]\nadd [rsp+1258h+var_1244], 1\nlea rax, [rax+rax*4]\nmov [rsp+r12*8+1258h+var_1228], rbx\nshl rax, 5\nmov [rsp+rax+1258h+var_8C8], rbp\nmov [rsp+rax+1258h+var_8C0], 0\njmp loc_1525\nloc_15FF:\nmovsxd r14, [rsp+1258h+var_1248]\nnop dword ptr [rax+00h]\nloc_1608:\nmov eax, [rsp+1258h+var_1248]\nmov [rsp+r14*8+1258h+var_BE8], rbp\nadd eax, 1\nmov [rsp+1258h+var_1248], eax\njmp loc_146C\nloc_1620:\nmovsxd r12, [rsp+1258h+var_124C]\nnop dword ptr [rax]\nloc_1628:\nmov eax, [rsp+1258h+var_124C]\nmov [rsp+r12*8+1258h+var_F08], rbx\nadd eax, 1\nmov [rsp+1258h+var_124C], eax\njmp loc_1424\nloc_1640:\nadd rbp, 320h\ncmp r13, rbp\njnz loc_156B\nloc_1650:\nmov eax, 1\njmp loc_15A6\nloc_165A:\nmov eax, 63h ; 'c'\njmp loc_14FA\nloc_1664:\ncall ___stack_chk_fail", + "ida_pseudo": "// positive sp value has been detected, the output may be wrong!\n__int64 __fastcall func0(const char **a1, int a2, const char **a3, int a4)\n{\n const char **v4; // r13\n const char *v5; // rbx\n __int64 v6; // r12\n const char **v7; // r14\n const char *v8; // rbp\n __int64 v9; // r14\n const char **v10; // r15\n __int64 v11; // r12\n __int64 v12; // r15\n int v13; // eax\n __int64 v14; // rdx\n _OWORD *v15; // rbp\n const char *v16; // rsi\n const char *v17; // r12\n const char **v18; // rbx\n __int64 v20; // rax\n int v21; // [rsp-21Ch] [rbp-1424Ch]\n int v22; // [rsp-218h] [rbp-14248h]\n int v23; // [rsp-214h] [rbp-14244h]\n const char **v25; // [rsp-208h] [rbp-14238h]\n _QWORD v26[63]; // [rsp-1F8h] [rbp-14228h]\n char v27; // [rsp+0h] [rbp-14030h] BYREF\n _QWORD v28[100]; // [rsp+128h] [rbp-13F08h] BYREF\n _QWORD v29[102]; // [rsp+448h] [rbp-13BE8h] BYREF\n _OWORD v30[136]; // [rsp+778h] [rbp-138B8h] BYREF\n _QWORD v31[9734]; // [rsp+1000h] [rbp-13030h] BYREF\n\n while ( &v27 != (char *)&v31[-10240] )\n ;\n v31[9726] = __readfsqword(0x28u);\n if ( a2 != a4 )\n return 0LL;\n if ( a2 > 0 )\n {\n v4 = a3;\n v22 = 0;\n v25 = &a3[a2];\n v21 = 0;\n v23 = 0;\n do\n {\n v5 = *v4;\n if ( v21 <= 0 )\n {\n v6 = v21;\nLABEL_36:\n v28[v6] = v5;\n ++v21;\n }\n else\n {\n v6 = v21;\n v7 = (const char **)v28;\n while ( strcmp(v5, *v7) )\n {\n if ( ++v7 == &v28[v21] )\n goto LABEL_36;\n }\n }\n v8 = *a1;\n if ( v22 <= 0 )\n {\n v9 = v22;\nLABEL_34:\n v29[v9] = v8;\n ++v22;\n }\n else\n {\n v9 = v22;\n v10 = (const char **)v29;\n while ( strcmp(v8, *v10) )\n {\n if ( ++v10 == &v29[v22] )\n goto LABEL_34;\n }\n }\n v11 = v23;\n v12 = 0LL;\n if ( v23 > 0 )\n {\n while ( 1 )\n {\n v13 = strcmp(v5, (const char *)v26[v12]);\n if ( !v13 )\n break;\n if ( ++v12 == v23 )\n goto LABEL_32;\n }\n v14 = 1LL;\n if ( v29[100 * (int)v12 + 100] )\n {\n do\n {\n if ( !v29[100 * (int)v12 + 100 + v14] )\n {\n v13 = v14;\n LODWORD(v14) = v14 + 1;\n goto LABEL_22;\n }\n ++v14;\n }\n while ( v14 != 100 );\n v13 = 99;\n }\nLABEL_22:\n v29[100 * (int)v12 + 100 + v13] = v8;\n v29[100 * (int)v12 + 100 + (int)v14] = 0LL;\n }\n else\n {\nLABEL_32:\n ++v23;\n v26[v11] = v5;\n v20 = 100 * v11;\n v29[v20 + 100] = v8;\n v29[v20 + 101] = 0LL;\n }\n ++v4;\n ++a1;\n }\n while ( v4 != v25 );\n if ( v21 != v22 )\n return 0LL;\n if ( v23 > 0 )\n {\n v15 = v30;\n while ( 1 )\n {\n v16 = (const char *)*((_QWORD *)v15 - 1);\n v17 = (const char *)*((_QWORD *)v15 - 2);\n if ( v16 )\n break;\nLABEL_37:\n v15 += 50;\n if ( &v30[50 * v23] == v15 )\n return 1LL;\n }\n v18 = (const char **)v15;\n while ( !strcmp(v17, v16) )\n {\n v16 = *v18++;\n if ( !v16 )\n goto LABEL_37;\n }\n return 0LL;\n }\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1350:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nlea r11, [rsp+30h+var_14030]\nloc_1366:\nsub rsp, 1000h\nor [rsp+1030h+var_1030], 0\ncmp rsp, r11\njnz short loc_1366\nsub rsp, 228h\nmov rax, fs:28h\nmov [rsp+1258h+arg_12FB8], rax\nxor eax, eax\ncmp esi, ecx\njnz loc_15A4\ntest esi, esi\njle loc_1650\nmovsxd rsi, esi\nmov [rsp+1258h+var_1240], rdi\nmov r13, rdx\nlea rax, [rdx+rsi*8]\nmov [rsp+1258h+var_1248], 0\nmov [rsp+1258h+var_1238], rax\nlea rax, [rsp+1258h+var_8C8]\nmov [rsp+1258h+var_124C], 0\nmov [rsp+1258h+var_1244], 0\nmov [rsp+1258h+var_1230], rax\nnop word ptr [rax+rax+00h]\nloc_13E0:\nmov eax, [rsp+1258h+var_124C]\nmov rbx, [r13+0]\ntest eax, eax\njle loc_1620\nmovsxd r12, [rsp+1258h+var_124C]\nlea r14, [rsp+1258h+var_F08]\nlea rbp, [r14+r12*8]\njmp short loc_1415\nloc_1408:\nadd r14, 8\ncmp r14, rbp\njz loc_1628\nloc_1415:\nmov rsi, [r14]; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1408\nloc_1424:\nmov rax, [rsp+1258h+var_1240]\nmov ecx, [rsp+1258h+var_1248]\nmov rbp, [rax]\ntest ecx, ecx\njle loc_15FF\nmovsxd r14, [rsp+1258h+var_1248]\nlea r15, [rsp+1258h+var_BE8]\nlea r12, [r15+r14*8]\njmp short loc_145D\nloc_1450:\nadd r15, 8\ncmp r15, r12\njz loc_1608\nloc_145D:\nmov rsi, [r15]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1450\nloc_146C:\nmov edx, [rsp+1258h+var_1244]\nmovsxd r12, [rsp+1258h+var_1244]\nxor r15d, r15d\nlea r14, [rsp+1258h+var_1228]\ntest edx, edx\njg short loc_149D\njmp loc_15D0\nloc_1490:\nadd r15, 1\ncmp r15, r12\njz loc_15D0\nloc_149D:\nmov rsi, [r14+r15*8]; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1490\nmovsxd rdx, r15d\nmov rcx, [rsp+1258h+var_1230]\nmovsxd rsi, r15d\nlea rdx, [rdx+rdx*4]\nlea rdi, [rdx+rdx*4]\nmov edx, 1\nshl rdi, 5\nadd rcx, rdi\ncmp [rsp+rdi+1258h+var_8C8], 0\njnz short loc_14EE\njmp short loc_14FA\nloc_14E0:\nadd rdx, 1\ncmp rdx, 64h ; 'd'\njz loc_165A\nloc_14EE:\ncmp qword ptr [rcx+rdx*8], 0\njnz short loc_14E0\nmov eax, edx\nadd edx, 1\nloc_14FA:\nlea rcx, [rsi+rsi*4]\ncdqe\nmovsxd rdx, edx\nlea rcx, [rcx+rcx*4]\nshl rcx, 2\nadd rax, rcx\nadd rcx, rdx\nmov [rsp+rax*8+1258h+var_8C8], rbp\nmov [rsp+rcx*8+1258h+var_8C8], 0\nloc_1525:\nmov rax, [rsp+1258h+var_1238]\nadd r13, 8\nadd [rsp+1258h+var_1240], 8\ncmp r13, rax\njnz loc_13E0\nmov ecx, [rsp+1258h+var_1248]\ncmp [rsp+1258h+var_124C], ecx\njnz short loc_15A4\nmovsxd rax, [rsp+1258h+var_1244]\ntest eax, eax\njle loc_1650\nlea rax, [rax+rax*4]\nlea rbp, [rsp+1258h+var_8B8]\nlea r13, [rax+rax*4]\nshl r13, 5\nadd r13, rbp\nloc_156B:\nmov rsi, [rbp-8]\nmov r12, [rbp-10h]\ntest rsi, rsi\njz loc_1640\nmov rbx, rbp\njmp short loc_1598\nloc_1588:\nmov rsi, [rbx]; s2\nadd rbx, 8\ntest rsi, rsi\njz loc_1640\nloc_1598:\nmov rdi, r12; s1\ncall _strcmp\ntest eax, eax\njz short loc_1588\nloc_15A4:\nxor eax, eax\nloc_15A6:\nmov rdx, [rsp+1258h+arg_12FB8]\nsub rdx, fs:28h\njnz loc_1664\nadd rsp, 14228h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15D0:\nlea rax, [r12+r12*4]\nadd [rsp+1258h+var_1244], 1\nlea rax, [rax+rax*4]\nmov [rsp+r12*8+1258h+var_1228], rbx\nshl rax, 5\nmov [rsp+rax+1258h+var_8C8], rbp\nmov [rsp+rax+1258h+var_8C0], 0\njmp loc_1525\nloc_15FF:\nmovsxd r14, [rsp+1258h+var_1248]\nnop dword ptr [rax+00h]\nloc_1608:\nmov eax, [rsp+1258h+var_1248]\nmov [rsp+r14*8+1258h+var_BE8], rbp\nadd eax, 1\nmov [rsp+1258h+var_1248], eax\njmp loc_146C\nloc_1620:\nmovsxd r12, [rsp+1258h+var_124C]\nnop dword ptr [rax]\nloc_1628:\nmov eax, [rsp+1258h+var_124C]\nmov [rsp+r12*8+1258h+var_F08], rbx\nadd eax, 1\nmov [rsp+1258h+var_124C], eax\njmp loc_1424\nloc_1640:\nadd rbp, 320h\ncmp r13, rbp\njnz loc_156B\nloc_1650:\nmov eax, 1\njmp loc_15A6\nloc_165A:\nmov eax, 63h ; 'c'\njmp loc_14FA\nloc_1664:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "// positive sp value has been detected, the output may be wrong!\n__int64 __fastcall sub_1350(const char **a1, int a2, const char **a3, int a4)\n{\n const char **v4; // r13\n const char *v5; // rbx\n __int64 v6; // r12\n const char **v7; // r14\n const char *v8; // rbp\n __int64 v9; // r14\n const char **v10; // r15\n __int64 v11; // r12\n __int64 v12; // r15\n int v13; // eax\n __int64 v14; // rdx\n _OWORD *v15; // rbp\n const char *v16; // rsi\n const char *v17; // r12\n const char **v18; // rbx\n __int64 v20; // rax\n int v21; // [rsp-21Ch] [rbp-1424Ch]\n int v22; // [rsp-218h] [rbp-14248h]\n int v23; // [rsp-214h] [rbp-14244h]\n const char **v25; // [rsp-208h] [rbp-14238h]\n _QWORD v26[63]; // [rsp-1F8h] [rbp-14228h]\n char v27; // [rsp+0h] [rbp-14030h] BYREF\n _QWORD v28[100]; // [rsp+128h] [rbp-13F08h] BYREF\n _QWORD v29[102]; // [rsp+448h] [rbp-13BE8h] BYREF\n _OWORD v30[136]; // [rsp+778h] [rbp-138B8h] BYREF\n _QWORD v31[9734]; // [rsp+1000h] [rbp-13030h] BYREF\n\n while ( &v27 != (char *)&v31[-10240] )\n ;\n v31[9726] = __readfsqword(0x28u);\n if ( a2 != a4 )\n return 0LL;\n if ( a2 > 0 )\n {\n v4 = a3;\n v22 = 0;\n v25 = &a3[a2];\n v21 = 0;\n v23 = 0;\n do\n {\n v5 = *v4;\n if ( v21 <= 0 )\n {\n v6 = v21;\nLABEL_36:\n v28[v6] = v5;\n ++v21;\n }\n else\n {\n v6 = v21;\n v7 = (const char **)v28;\n while ( strcmp(v5, *v7) )\n {\n if ( ++v7 == &v28[v21] )\n goto LABEL_36;\n }\n }\n v8 = *a1;\n if ( v22 <= 0 )\n {\n v9 = v22;\nLABEL_34:\n v29[v9] = v8;\n ++v22;\n }\n else\n {\n v9 = v22;\n v10 = (const char **)v29;\n while ( strcmp(v8, *v10) )\n {\n if ( ++v10 == &v29[v22] )\n goto LABEL_34;\n }\n }\n v11 = v23;\n v12 = 0LL;\n if ( v23 > 0 )\n {\n while ( 1 )\n {\n v13 = strcmp(v5, (const char *)v26[v12]);\n if ( !v13 )\n break;\n if ( ++v12 == v23 )\n goto LABEL_32;\n }\n v14 = 1LL;\n if ( v29[100 * (int)v12 + 100] )\n {\n do\n {\n if ( !v29[100 * (int)v12 + 100 + v14] )\n {\n v13 = v14;\n LODWORD(v14) = v14 + 1;\n goto LABEL_22;\n }\n ++v14;\n }\n while ( v14 != 100 );\n v13 = 99;\n }\nLABEL_22:\n v29[100 * (int)v12 + 100 + v13] = v8;\n v29[100 * (int)v12 + 100 + (int)v14] = 0LL;\n }\n else\n {\nLABEL_32:\n ++v23;\n v26[v11] = v5;\n v20 = 100 * v11;\n v29[v20 + 100] = v8;\n v29[v20 + 101] = 0LL;\n }\n ++v4;\n ++a1;\n }\n while ( v4 != v25 );\n if ( v21 != v22 )\n return 0LL;\n if ( v23 > 0 )\n {\n v15 = v30;\n while ( 1 )\n {\n v16 = (const char *)*((_QWORD *)v15 - 1);\n v17 = (const char *)*((_QWORD *)v15 - 2);\n if ( v16 )\n break;\nLABEL_37:\n v15 += 50;\n if ( &v30[50 * v23] == v15 )\n return 1LL;\n }\n v18 = (const char **)v15;\n while ( !strcmp(v17, v16) )\n {\n v16 = *v18++;\n if ( !v16 )\n goto LABEL_37;\n }\n return 0LL;\n }\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1350(const char **a1, int a2, const char **a3, int a4) {\n const char **v4;\n const char *v5;\n long long v6;\n const char **v7;\n const char *v8;\n long long v9;\n const char **v10;\n long long v11;\n long long v12;\n int v13;\n long long v14;\n long double *v15;\n const char *v16;\n const char *v17;\n const char **v18;\n long long v20;\n int v21;\n int v22;\n int v23;\n const char **v25;\n uint64_t v26[63];\n char v27;\n uint64_t v28[100];\n uint64_t v29[102];\n long double v30[136];\n uint64_t v31[9734];\n while (&v27 != (char *)&v31[-10240])\n ;\n v31[9726] = __readfsqword(40u);\n if (a2 != a4) return 0LL;\n if (a2 > 0) {\n v4 = a3;\n v22 = 0;\n v25 = &a3[a2];\n v21 = 0;\n v23 = 0;\n do {\n v5 = *v4;\n if (v21 <= 0) {\n v6 = v21;\n LABEL_36:\n v28[v6] = v5;\n ++v21;\n } else {\n v6 = v21;\n v7 = (const char **)v28;\n while (strcmp(v5, *v7)) {\n if (++v7 == &v28[v21]) goto LABEL_36;\n }\n }\n v8 = *a1;\n if (v22 <= 0) {\n v9 = v22;\n LABEL_34:\n v29[v9] = v8;\n ++v22;\n } else {\n v9 = v22;\n v10 = (const char **)v29;\n while (strcmp(v8, *v10)) {\n if (++v10 == &v29[v22]) goto LABEL_34;\n }\n }\n v11 = v23;\n v12 = 0LL;\n if (v23 > 0) {\n while (1) {\n v13 = strcmp(v5, (const char *)v26[v12]);\n if (!v13) break;\n if (++v12 == v23) goto LABEL_32;\n }\n v14 = 1LL;\n if (v29[100 * (int)v12 + 100]) {\n do {\n if (!v29[100 * (int)v12 + 100 + v14]) {\n v13 = v14;\n LODWORD(v14) = v14 + 1;\n goto LABEL_22;\n }\n ++v14;\n } while (v14 != 100);\n v13 = 99;\n }\n LABEL_22:\n v29[100 * (int)v12 + 100 + v13] = v8;\n v29[100 * (int)v12 + 100 + (int)v14] = 0LL;\n } else {\n LABEL_32:\n ++v23;\n v26[v11] = v5;\n v20 = 100 * v11;\n v29[v20 + 100] = v8;\n v29[v20 + 101] = 0LL;\n }\n ++v4;\n ++a1;\n } while (v4 != v25);\n if (v21 != v22) return 0LL;\n if (v23 > 0) {\n v15 = v30;\n while (1) {\n v16 = (const char *)*((uint64_t *)v15 - 1);\n v17 = (const char *)*((uint64_t *)v15 - 2);\n if (v16) break;\n LABEL_37:\n v15 += 50;\n if (&v30[50 * v23] == v15) return 1LL;\n }\n v18 = (const char **)v15;\n while (!strcmp(v17, v16)) {\n v16 = *v18++;\n if (!v16) goto LABEL_37;\n }\n return 0LL;\n }\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(const char **a1, int a2, const char **a3, int a4) {\n const char **v4;\n const char *v5;\n long long v6;\n const char **v7;\n const char *v8;\n long long v9;\n const char **v10;\n long long v11;\n long long v12;\n int v13;\n long long v14;\n long double *v15;\n const char *v16;\n const char *v17;\n const char **v18;\n long long v20;\n int v21;\n int v22;\n int v23;\n const char **v25;\n uint64_t v26[63];\n char v27;\n uint64_t v28[100];\n uint64_t v29[102];\n long double v30[136];\n uint64_t v31[9734];\n while (&v27 != (char *)&v31[-10240])\n ;\n v31[9726] = __readfsqword(40u);\n if (a2 != a4) return 0LL;\n if (a2 > 0) {\n v4 = a3;\n v22 = 0;\n v25 = &a3[a2];\n v21 = 0;\n v23 = 0;\n do {\n v5 = *v4;\n if (v21 <= 0) {\n v6 = v21;\n LABEL_36:\n v28[v6] = v5;\n ++v21;\n } else {\n v6 = v21;\n v7 = (const char **)v28;\n while (strcmp(v5, *v7)) {\n if (++v7 == &v28[v21]) goto LABEL_36;\n }\n }\n v8 = *a1;\n if (v22 <= 0) {\n v9 = v22;\n LABEL_34:\n v29[v9] = v8;\n ++v22;\n } else {\n v9 = v22;\n v10 = (const char **)v29;\n while (strcmp(v8, *v10)) {\n if (++v10 == &v29[v22]) goto LABEL_34;\n }\n }\n v11 = v23;\n v12 = 0LL;\n if (v23 > 0) {\n while (1) {\n v13 = strcmp(v5, (const char *)v26[v12]);\n if (!v13) break;\n if (++v12 == v23) goto LABEL_32;\n }\n v14 = 1LL;\n if (v29[100 * (int)v12 + 100]) {\n do {\n if (!v29[100 * (int)v12 + 100 + v14]) {\n v13 = v14;\n LODWORD(v14) = v14 + 1;\n goto LABEL_22;\n }\n ++v14;\n } while (v14 != 100);\n v13 = 99;\n }\n LABEL_22:\n v29[100 * (int)v12 + 100 + v13] = v8;\n v29[100 * (int)v12 + 100 + (int)v14] = 0LL;\n } else {\n LABEL_32:\n ++v23;\n v26[v11] = v5;\n v20 = 100 * v11;\n v29[v20 + 100] = v8;\n v29[v20 + 101] = 0LL;\n }\n ++v4;\n ++a1;\n } while (v4 != v25);\n if (v21 != v22) return 0LL;\n if (v23 > 0) {\n v15 = v30;\n while (1) {\n v16 = (const char *)*((uint64_t *)v15 - 1);\n v17 = (const char *)*((uint64_t *)v15 - 2);\n if (v16) break;\n LABEL_37:\n v15 += 50;\n if (&v30[50 * v23] == v15) return 1LL;\n }\n v18 = (const char **)v15;\n while (!strcmp(v17, v16)) {\n v16 = *v18++;\n if (!v16) goto LABEL_37;\n }\n return 0LL;\n }\n }\n return 1LL;\n}" + }, + { + "index": 75, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(int test_list[][3], int list_size, int K) {\n static char res[100];\n int index = 0;\n res[index++] = '[';\n for (int i = 0; i < list_size; i++) {\n bool divisible = true;\n for (int j = 0; j < 3; j++) {\n if (test_list[i][j] % K != 0) {\n divisible = false;\n break;\n }\n }\n if (divisible) {\n if (res[index - 1] != '[') {\n res[index++] = ',';\n res[index++] = ' ';\n }\n res[index++] = '(';\n for (int j = 0; j < 3; j++) {\n char numStr[10];\n sprintf(numStr, \"%d\", test_list[i][j]);\n for (int k = 0; numStr[k] != '\\0'; k++) {\n res[index++] = numStr[k];\n }\n if (j != 2) {\n res[index++] = ',';\n res[index++] = ' ';\n }\n }\n res[index++] = ')';\n }\n }\n res[index++] = ']';\n res[index] = '\\0';\n return res;\n}", + "test": "int main() {\n\n int list1[][3] = {{6, 24, 12}, {7, 9, 6}, {12, 18, 21}};\n\n int list2[][3] = {{5, 25, 30}, {4, 2, 3}, {7, 8, 9}};\n\n int list3[][3] = {{7, 9, 16}, {8, 16, 4}, {19, 17, 18}};\n\n \n\n assert(strcmp(func0(list1, 3, 6), \"[(6, 24, 12)]\") == 0);\n\n assert(strcmp(func0(list2, 3, 5), \"[(5, 25, 30)]\") == 0);\n\n assert(strcmp(func0(list3, 3, 4), \"[(8, 16, 4)]\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x40,%rsp\nmov %rdi,-0x38(%rbp)\nmov %esi,-0x3c(%rbp)\nmov %edx,-0x40(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovl $0x0,-0x28(%rbp)\nmov -0x28(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x28(%rbp)\ncltq\nlea 0x2e59(%rip),%rdx\nmovb $0x5b,(%rax,%rdx,1)\nmovl $0x0,-0x24(%rbp)\njmpq 1384 \nmovb $0x1,-0x29(%rbp)\nmovl $0x0,-0x20(%rbp)\njmp 123d \nmov -0x24(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x38(%rbp),%rax\nadd %rax,%rdx\nmov -0x20(%rbp),%eax\ncltq\nmov (%rdx,%rax,4),%eax\ncltd\nidivl -0x40(%rbp)\nmov %edx,%eax\ntest %eax,%eax\nje 1239 \nmovb $0x0,-0x29(%rbp)\njmp 1243 \naddl $0x1,-0x20(%rbp)\ncmpl $0x2,-0x20(%rbp)\njle 1204 \ncmpb $0x0,-0x29(%rbp)\nje 1380 \nmov -0x28(%rbp),%eax\nsub $0x1,%eax\ncltq\nlea 0x2de4(%rip),%rdx\nmovzbl (%rax,%rdx,1),%eax\ncmp $0x5b,%al\nje 1290 \nmov -0x28(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x28(%rbp)\ncltq\nlea 0x2dca(%rip),%rdx\nmovb $0x2c,(%rax,%rdx,1)\nmov -0x28(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x28(%rbp)\ncltq\nlea 0x2db4(%rip),%rdx\nmovb $0x20,(%rax,%rdx,1)\nmov -0x28(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x28(%rbp)\ncltq\nlea 0x2d9e(%rip),%rdx\nmovb $0x28,(%rax,%rdx,1)\nmovl $0x0,-0x1c(%rbp)\njmpq 1360 \nmov -0x24(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x38(%rbp),%rax\nadd %rax,%rdx\nmov -0x1c(%rbp),%eax\ncltq\nmov (%rdx,%rax,4),%edx\nlea -0x12(%rbp),%rax\nlea 0xd26(%rip),%rsi\nmov %rax,%rdi\nmov $0x0,%eax\ncallq 10b0 \nmovl $0x0,-0x18(%rbp)\njmp 131c \nmov -0x28(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x28(%rbp)\nmov -0x18(%rbp),%edx\nmovslq %edx,%rdx\nmovzbl -0x12(%rbp,%rdx,1),%edx\ncltq\nlea 0x2d2b(%rip),%rcx\nmov %dl,(%rax,%rcx,1)\naddl $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%eax\ncltq\nmovzbl -0x12(%rbp,%rax,1),%eax\ntest %al,%al\njne 12f8 \ncmpl $0x2,-0x1c(%rbp)\nje 135c \nmov -0x28(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x28(%rbp)\ncltq\nlea 0x2cfe(%rip),%rdx\nmovb $0x2c,(%rax,%rdx,1)\nmov -0x28(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x28(%rbp)\ncltq\nlea 0x2ce8(%rip),%rdx\nmovb $0x20,(%rax,%rdx,1)\naddl $0x1,-0x1c(%rbp)\ncmpl $0x2,-0x1c(%rbp)\njle 12b2 \nmov -0x28(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x28(%rbp)\ncltq\nlea 0x2cc4(%rip),%rdx\nmovb $0x29,(%rax,%rdx,1)\naddl $0x1,-0x24(%rbp)\nmov -0x24(%rbp),%eax\ncmp -0x3c(%rbp),%eax\njl 11f7 \nmov -0x28(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x28(%rbp)\ncltq\nlea 0x2c9e(%rip),%rdx\nmovb $0x5d,(%rax,%rdx,1)\nmov -0x28(%rbp),%eax\ncltq\nlea 0x2c8e(%rip),%rdx\nmovb $0x0,(%rax,%rdx,1)\nlea 0x2c83(%rip),%rax\nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 13d1 \ncallq 1080 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov [rbp+var_40], edx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_28], 0\nmov eax, [rbp+var_28]\nlea edx, [rax+1]\nmov [rbp+var_28], edx\ncdqe\nlea rdx, res_1\nmov byte ptr [rax+rdx], 5Bh ; '['\nmov [rbp+var_24], 0\njmp loc_1387\nloc_11F7:\nmov [rbp+var_29], 1\nmov [rbp+var_20], 0\njmp short loc_123D\nloc_1204:\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_38]\nadd rdx, rax\nmov eax, [rbp+var_20]\ncdqe\nmov eax, [rdx+rax*4]\ncdq\nidiv [rbp+var_40]\nmov eax, edx\ntest eax, eax\njz short loc_1239\nmov [rbp+var_29], 0\njmp short loc_1243\nloc_1239:\nadd [rbp+var_20], 1\nloc_123D:\ncmp [rbp+var_20], 2\njle short loc_1204\nloc_1243:\ncmp [rbp+var_29], 0\njz loc_1383\nmov eax, [rbp+var_28]\nsub eax, 1\ncdqe\nlea rdx, res_1\nmovzx eax, byte ptr [rax+rdx]\ncmp al, 5Bh ; '['\njz short loc_1290\nmov eax, [rbp+var_28]\nlea edx, [rax+1]\nmov [rbp+var_28], edx\ncdqe\nlea rdx, res_1\nmov byte ptr [rax+rdx], 2Ch ; ','\nmov eax, [rbp+var_28]\nlea edx, [rax+1]\nmov [rbp+var_28], edx\ncdqe\nlea rdx, res_1\nmov byte ptr [rax+rdx], 20h ; ' '\nloc_1290:\nmov eax, [rbp+var_28]\nlea edx, [rax+1]\nmov [rbp+var_28], edx\ncdqe\nlea rdx, res_1\nmov byte ptr [rax+rdx], 28h ; '('\nmov [rbp+var_1C], 0\njmp loc_1363\nloc_12B2:\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_38]\nadd rdx, rax\nmov eax, [rbp+var_1C]\ncdqe\nmov edx, [rdx+rax*4]\nlea rax, [rbp+s]\nlea rcx, format; \"%d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nmov [rbp+var_18], 0\njmp short loc_131F\nloc_12FB:\nmov eax, [rbp+var_28]\nlea edx, [rax+1]\nmov [rbp+var_28], edx\nmov edx, [rbp+var_18]\nmovsxd rdx, edx\nmovzx edx, [rbp+rdx+s]\ncdqe\nlea rcx, res_1\nmov [rax+rcx], dl\nadd [rbp+var_18], 1\nloc_131F:\nmov eax, [rbp+var_18]\ncdqe\nmovzx eax, [rbp+rax+s]\ntest al, al\njnz short loc_12FB\ncmp [rbp+var_1C], 2\njz short loc_135F\nmov eax, [rbp+var_28]\nlea edx, [rax+1]\nmov [rbp+var_28], edx\ncdqe\nlea rdx, res_1\nmov byte ptr [rax+rdx], 2Ch ; ','\nmov eax, [rbp+var_28]\nlea edx, [rax+1]\nmov [rbp+var_28], edx\ncdqe\nlea rdx, res_1\nmov byte ptr [rax+rdx], 20h ; ' '\nloc_135F:\nadd [rbp+var_1C], 1\nloc_1363:\ncmp [rbp+var_1C], 2\njle loc_12B2\nmov eax, [rbp+var_28]\nlea edx, [rax+1]\nmov [rbp+var_28], edx\ncdqe\nlea rdx, res_1\nmov byte ptr [rax+rdx], 29h ; ')'\nloc_1383:\nadd [rbp+var_24], 1\nloc_1387:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_3C]\njl loc_11F7\nmov eax, [rbp+var_28]\nlea edx, [rax+1]\nmov [rbp+var_28], edx\ncdqe\nlea rdx, res_1\nmov byte ptr [rax+rdx], 5Dh ; ']'\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, res_1\nmov byte ptr [rax+rdx], 0\nlea rax, res_1\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_13D4\ncall ___stack_chk_fail\nlocret_13D4:\nleave\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(__int64 a1, int a2, int a3)\n{\n int v3; // eax\n int v4; // eax\n int v5; // eax\n int v6; // eax\n int v7; // eax\n char v10; // [rsp+17h] [rbp-29h]\n int v11; // [rsp+18h] [rbp-28h]\n int v12; // [rsp+18h] [rbp-28h]\n int i; // [rsp+1Ch] [rbp-24h]\n int j; // [rsp+20h] [rbp-20h]\n int k; // [rsp+24h] [rbp-1Ch]\n int m; // [rsp+28h] [rbp-18h]\n char s[10]; // [rsp+2Eh] [rbp-12h] BYREF\n unsigned __int64 v18; // [rsp+38h] [rbp-8h]\n\n v18 = __readfsqword(0x28u);\n v11 = 1;\n res_1[0] = 91;\n for ( i = 0; i < a2; ++i )\n {\n v10 = 1;\n for ( j = 0; j <= 2; ++j )\n {\n if ( *(_DWORD *)(a1 + 12LL * i + 4LL * j) % a3 )\n {\n v10 = 0;\n break;\n }\n }\n if ( v10 )\n {\n if ( res_1[v11 - 1] != 91 )\n {\n res_1[v11] = 44;\n v3 = v11 + 1;\n v11 += 2;\n res_1[v3] = 32;\n }\n v4 = v11;\n v12 = v11 + 1;\n res_1[v4] = 40;\n for ( k = 0; k <= 2; ++k )\n {\n sprintf(s, \"%d\", *(_DWORD *)(a1 + 12LL * i + 4LL * k));\n for ( m = 0; s[m]; ++m )\n {\n v5 = v12++;\n res_1[v5] = s[m];\n }\n if ( k != 2 )\n {\n res_1[v12] = 44;\n v6 = v12 + 1;\n v12 += 2;\n res_1[v6] = 32;\n }\n }\n v7 = v12;\n v11 = v12 + 1;\n res_1[v7] = 41;\n }\n }\n res_1[v11] = 93;\n res_1[v11 + 1] = 0;\n return res_1;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov [rbp+var_40], edx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_28], 0\nmov eax, [rbp+var_28]\nlea edx, [rax+1]\nmov [rbp+var_28], edx\ncdqe\nlea rdx, unk_4040\nmov byte ptr [rax+rdx], 5Bh ; '['\nmov [rbp+var_24], 0\njmp loc_1387\nloc_11F7:\nmov [rbp+var_29], 1\nmov [rbp+var_20], 0\njmp short loc_123D\nloc_1204:\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_38]\nadd rdx, rax\nmov eax, [rbp+var_20]\ncdqe\nmov eax, [rdx+rax*4]\ncdq\nidiv [rbp+var_40]\nmov eax, edx\ntest eax, eax\njz short loc_1239\nmov [rbp+var_29], 0\njmp short loc_1243\nloc_1239:\nadd [rbp+var_20], 1\nloc_123D:\ncmp [rbp+var_20], 2\njle short loc_1204\nloc_1243:\ncmp [rbp+var_29], 0\njz loc_1383\nmov eax, [rbp+var_28]\nsub eax, 1\ncdqe\nlea rdx, unk_4040\nmovzx eax, byte ptr [rax+rdx]\ncmp al, 5Bh ; '['\njz short loc_1290\nmov eax, [rbp+var_28]\nlea edx, [rax+1]\nmov [rbp+var_28], edx\ncdqe\nlea rdx, unk_4040\nmov byte ptr [rax+rdx], 2Ch ; ','\nmov eax, [rbp+var_28]\nlea edx, [rax+1]\nmov [rbp+var_28], edx\ncdqe\nlea rdx, unk_4040\nmov byte ptr [rax+rdx], 20h ; ' '\nloc_1290:\nmov eax, [rbp+var_28]\nlea edx, [rax+1]\nmov [rbp+var_28], edx\ncdqe\nlea rdx, unk_4040\nmov byte ptr [rax+rdx], 28h ; '('\nmov [rbp+var_1C], 0\njmp loc_1363\nloc_12B2:\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_38]\nadd rdx, rax\nmov eax, [rbp+var_1C]\ncdqe\nmov edx, [rdx+rax*4]\nlea rax, [rbp+s]\nlea rcx, format; \"%d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nmov [rbp+var_18], 0\njmp short loc_131F\nloc_12FB:\nmov eax, [rbp+var_28]\nlea edx, [rax+1]\nmov [rbp+var_28], edx\nmov edx, [rbp+var_18]\nmovsxd rdx, edx\nmovzx edx, [rbp+rdx+s]\ncdqe\nlea rcx, unk_4040\nmov [rax+rcx], dl\nadd [rbp+var_18], 1\nloc_131F:\nmov eax, [rbp+var_18]\ncdqe\nmovzx eax, [rbp+rax+s]\ntest al, al\njnz short loc_12FB\ncmp [rbp+var_1C], 2\njz short loc_135F\nmov eax, [rbp+var_28]\nlea edx, [rax+1]\nmov [rbp+var_28], edx\ncdqe\nlea rdx, unk_4040\nmov byte ptr [rax+rdx], 2Ch ; ','\nmov eax, [rbp+var_28]\nlea edx, [rax+1]\nmov [rbp+var_28], edx\ncdqe\nlea rdx, unk_4040\nmov byte ptr [rax+rdx], 20h ; ' '\nloc_135F:\nadd [rbp+var_1C], 1\nloc_1363:\ncmp [rbp+var_1C], 2\njle loc_12B2\nmov eax, [rbp+var_28]\nlea edx, [rax+1]\nmov [rbp+var_28], edx\ncdqe\nlea rdx, unk_4040\nmov byte ptr [rax+rdx], 29h ; ')'\nloc_1383:\nadd [rbp+var_24], 1\nloc_1387:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_3C]\njl loc_11F7\nmov eax, [rbp+var_28]\nlea edx, [rax+1]\nmov [rbp+var_28], edx\ncdqe\nlea rdx, unk_4040\nmov byte ptr [rax+rdx], 5Dh ; ']'\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, unk_4040\nmov byte ptr [rax+rdx], 0\nlea rax, unk_4040\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_13D4\ncall ___stack_chk_fail\nlocret_13D4:\nleave\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_11A9(__int64 a1, int a2, int a3)\n{\n int v3; // eax\n int v4; // eax\n int v5; // eax\n int v6; // eax\n int v7; // eax\n char v10; // [rsp+17h] [rbp-29h]\n int v11; // [rsp+18h] [rbp-28h]\n int v12; // [rsp+18h] [rbp-28h]\n int i; // [rsp+1Ch] [rbp-24h]\n int j; // [rsp+20h] [rbp-20h]\n int k; // [rsp+24h] [rbp-1Ch]\n int m; // [rsp+28h] [rbp-18h]\n char s[10]; // [rsp+2Eh] [rbp-12h] BYREF\n unsigned __int64 v18; // [rsp+38h] [rbp-8h]\n\n v18 = __readfsqword(0x28u);\n v11 = 1;\n byte_4040[0] = 91;\n for ( i = 0; i < a2; ++i )\n {\n v10 = 1;\n for ( j = 0; j <= 2; ++j )\n {\n if ( *(_DWORD *)(a1 + 12LL * i + 4LL * j) % a3 )\n {\n v10 = 0;\n break;\n }\n }\n if ( v10 )\n {\n if ( byte_4040[v11 - 1] != 91 )\n {\n byte_4040[v11] = 44;\n v3 = v11 + 1;\n v11 += 2;\n byte_4040[v3] = 32;\n }\n v4 = v11;\n v12 = v11 + 1;\n byte_4040[v4] = 40;\n for ( k = 0; k <= 2; ++k )\n {\n sprintf(s, \"%d\", *(_DWORD *)(a1 + 12LL * i + 4LL * k));\n for ( m = 0; s[m]; ++m )\n {\n v5 = v12++;\n byte_4040[v5] = s[m];\n }\n if ( k != 2 )\n {\n byte_4040[v12] = 44;\n v6 = v12 + 1;\n v12 += 2;\n byte_4040[v6] = 32;\n }\n }\n v7 = v12;\n v11 = v12 + 1;\n byte_4040[v7] = 41;\n }\n }\n byte_4040[v11] = 93;\n byte_4040[v11 + 1] = 0;\n return byte_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_11A9(long long a1, int a2, int a3) {\n int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n char v10;\n int v11;\n int v12;\n int i;\n int j;\n int k;\n int m;\n char s[10];\n unsigned long long v18;\n v18 = __readfsqword(40u);\n v11 = 1;\n byte_4040[0] = 91;\n for (i = 0; i < a2; ++i) {\n v10 = 1;\n for (j = 0; j <= 2; ++j) {\n if (*(uint32_t *)(a1 + 12LL * i + 4LL * j) % a3) {\n v10 = 0;\n break;\n }\n }\n if (v10) {\n if (byte_4040[v11 - 1] != 91) {\n byte_4040[v11] = 44;\n v3 = v11 + 1;\n v11 += 2;\n byte_4040[v3] = 32;\n }\n v4 = v11;\n v12 = v11 + 1;\n byte_4040[v4] = 40;\n for (k = 0; k <= 2; ++k) {\n sprintf(s, \"%d\", *(uint32_t *)(a1 + 12LL * i + 4LL * k));\n for (m = 0; s[m]; ++m) {\n v5 = v12++;\n byte_4040[v5] = s[m];\n }\n if (k != 2) {\n byte_4040[v12] = 44;\n v6 = v12 + 1;\n v12 += 2;\n byte_4040[v6] = 32;\n }\n }\n v7 = v12;\n v11 = v12 + 1;\n byte_4040[v7] = 41;\n }\n }\n byte_4040[v11] = 93;\n byte_4040[v11 + 1] = 0;\n return byte_4040;\n}", + "ida_pseudo_norm": "uint8_t *func0(long long a1, int a2, int a3) {\n int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n char v10;\n int v11;\n int v12;\n int i;\n int j;\n int k;\n int m;\n char s[10];\n unsigned long long v18;\n v18 = __readfsqword(40u);\n v11 = 1;\n res_1[0] = 91;\n for (i = 0; i < a2; ++i) {\n v10 = 1;\n for (j = 0; j <= 2; ++j) {\n if (*(uint32_t *)(a1 + 12LL * i + 4LL * j) % a3) {\n v10 = 0;\n break;\n }\n }\n if (v10) {\n if (res_1[v11 - 1] != 91) {\n res_1[v11] = 44;\n v3 = v11 + 1;\n v11 += 2;\n res_1[v3] = 32;\n }\n v4 = v11;\n v12 = v11 + 1;\n res_1[v4] = 40;\n for (k = 0; k <= 2; ++k) {\n sprintf(s, \"%d\", *(uint32_t *)(a1 + 12LL * i + 4LL * k));\n for (m = 0; s[m]; ++m) {\n v5 = v12++;\n res_1[v5] = s[m];\n }\n if (k != 2) {\n res_1[v12] = 44;\n v6 = v12 + 1;\n v12 += 2;\n res_1[v6] = 32;\n }\n }\n v7 = v12;\n v11 = v12 + 1;\n res_1[v7] = 41;\n }\n }\n res_1[v11] = 93;\n res_1[v11 + 1] = 0;\n return res_1;\n}" + }, + { + "index": 75, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(int test_list[][3], int list_size, int K) {\n static char res[100];\n int index = 0;\n res[index++] = '[';\n for (int i = 0; i < list_size; i++) {\n bool divisible = true;\n for (int j = 0; j < 3; j++) {\n if (test_list[i][j] % K != 0) {\n divisible = false;\n break;\n }\n }\n if (divisible) {\n if (res[index - 1] != '[') {\n res[index++] = ',';\n res[index++] = ' ';\n }\n res[index++] = '(';\n for (int j = 0; j < 3; j++) {\n char numStr[10];\n sprintf(numStr, \"%d\", test_list[i][j]);\n for (int k = 0; numStr[k] != '\\0'; k++) {\n res[index++] = numStr[k];\n }\n if (j != 2) {\n res[index++] = ',';\n res[index++] = ' ';\n }\n }\n res[index++] = ')';\n }\n }\n res[index++] = ']';\n res[index] = '\\0';\n return res;\n}", + "test": "int main() {\n\n int list1[][3] = {{6, 24, 12}, {7, 9, 6}, {12, 18, 21}};\n\n int list2[][3] = {{5, 25, 30}, {4, 2, 3}, {7, 8, 9}};\n\n int list3[][3] = {{7, 9, 16}, {8, 16, 4}, {19, 17, 18}};\n\n \n\n assert(strcmp(func0(list1, 3, 6), \"[(6, 24, 12)]\") == 0);\n\n assert(strcmp(func0(list2, 3, 5), \"[(5, 25, 30)]\") == 0);\n\n assert(strcmp(func0(list3, 3, 4), \"[(8, 16, 4)]\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x48,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x38(%rsp)\nxor %eax,%eax\nmovb $0x5b,0x2e8e(%rip)\ntest %esi,%esi\njle 11f2 \nmov %edx,%r12d\nmov %rdi,%rbp\nlea -0x1(%rsi),%eax\nlea (%rax,%rax,2),%rax\nlea 0xc(%rdi,%rax,4),%rax\nmov %rax,0x18(%rsp)\nmov $0x1,%esi\nlea 0x2e67(%rip),%r15\nlea 0x2e(%rsp),%rax\nmov %rax,0x10(%rsp)\nlea -0x1(%r15),%rbx\njmp 1248 \nmov 0xc(%rsp),%ecx\njmpq 12fa \nmov $0x1,%esi\nlea 0x2e42(%rip),%rax\nmovslq %esi,%rdx\nmovb $0x5d,(%rax,%rdx,1)\nadd $0x1,%esi\nmovslq %esi,%rsi\nmovb $0x0,(%rax,%rsi,1)\nmov 0x38(%rsp),%rdi\nxor %fs:0x28,%rdi\njne 1327 \nadd $0x48,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nlea 0x1(%rcx),%esi\nmovslq %ecx,%rcx\nmovb $0x29,(%r15,%rcx,1)\nadd $0xc,%rbp\ncmp 0x18(%rsp),%rbp\nje 11f7 \nmov %rbp,%r14\nmov 0x0(%rbp),%eax\ncltd\nidiv %r12d\ntest %edx,%edx\njne 123d \nmov 0x4(%rbp),%eax\ncltd\nidiv %r12d\ntest %edx,%edx\njne 123d \nmov 0x8(%r14),%eax\ncltd\nidiv %r12d\ntest %edx,%edx\njne 123d \nlea -0x1(%rsi),%eax\ncltq\ncmpb $0x5b,(%r15,%rax,1)\nje 128e \nlea 0x1(%rsi),%eax\nmovslq %esi,%rdx\nmovb $0x2c,(%r15,%rdx,1)\nadd $0x2,%esi\ncltq\nmovb $0x20,(%r15,%rax,1)\nlea 0x1(%rsi),%eax\nmov %eax,0xc(%rsp)\nmovslq %esi,%rsi\nmovb $0x28,(%r15,%rsi,1)\nmov $0x0,%r13d\nmov (%r14,%r13,4),%r8d\nlea 0xd56(%rip),%rcx\nmov $0xa,%edx\nmov $0x1,%esi\nmov 0x10(%rsp),%rdi\nmov $0x0,%eax\ncallq 1090 <__sprintf_chk@plt>\nmovzbl 0x2e(%rsp),%edx\ntest %dl,%dl\nje 11e9 \nmov 0xc(%rsp),%ecx\nlea 0x1(%rcx),%eax\ncltq\nmovslq %ecx,%rcx\nmov 0x10(%rsp),%rsi\nsub %rcx,%rsi\nmov %eax,%ecx\nmov %dl,(%rax,%rbx,1)\nadd $0x1,%rax\nmovzbl -0x1(%rsi,%rax,1),%edx\ntest %dl,%dl\njne 12e8 \ncmp $0x2,%r13\nje 1232 \nmovslq %ecx,%rax\nmovb $0x2c,(%r15,%rax,1)\nlea 0x2(%rcx),%eax\nmov %eax,0xc(%rsp)\nadd $0x1,%ecx\nmovslq %ecx,%rcx\nmovb $0x20,(%r15,%rcx,1)\nadd $0x1,%r13\njmpq 12a3 \ncallq 1070 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 48h\nmov rax, fs:28h\nmov [rsp+78h+var_40], rax\nxor eax, eax\nmov cs:res_1, 5Bh ; '['\ntest esi, esi\njle short loc_11FD\nmov r8d, edx\nmov rcx, rdi\nmovsxd rsi, esi\nlea rax, [rsi+rsi*2]\nlea rdi, [rdi+rax*4]\nmov r9d, 1\nlea r13, res_1\nlea rbp, [r13-1]\nmov r15, rcx\njmp short loc_1265\nloc_11FD:\nmov r9d, 1\nloc_1203:\nlea rax, res_1\nmovsxd rdx, r9d\nmov byte ptr [rax+rdx], 5Dh ; ']'\nadd r9d, 1\nmovsxd r9, r9d\nmov byte ptr [rax+r9], 0\nmov rdx, [rsp+78h+var_40]\nsub rdx, fs:28h\njnz loc_134E\nadd rsp, 48h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1240:\nmov r15, [rsp+78h+var_70]\nmov rdi, [rsp+78h+var_68]\nmov r8d, [rsp+78h+var_5C]\nlea r9d, [rbx+1]\nmovsxd rbx, ebx\nmov byte ptr [r13+rbx+0], 29h ; ')'\nloc_125C:\nadd r15, 0Ch\ncmp r15, rdi\njz short loc_1203\nloc_1265:\nmov rcx, r15\nmov eax, [r15]\ncdq\nidiv r8d\ntest edx, edx\njnz short loc_125C\nmov eax, [r15+4]\ncdq\nidiv r8d\ntest edx, edx\njnz short loc_125C\nmov eax, [rcx+8]\ncdq\nidiv r8d\ntest edx, edx\njnz short loc_125C\nlea eax, [r9-1]\ncdqe\ncmp byte ptr [r13+rax+0], 5Bh ; '['\njz short loc_12B1\nlea eax, [r9+1]\nmovsxd rdx, r9d\nmov byte ptr [r13+rdx+0], 2Ch ; ','\nadd r9d, 2\ncdqe\nmov byte ptr [r13+rax+0], 20h ; ' '\nloc_12B1:\nlea ebx, [r9+1]\nmovsxd r9, r9d\nmov byte ptr [r13+r9+0], 28h ; '('\nmov r12d, 0\nlea r14, [rsp+78h+var_4A]\nmov [rsp+78h+var_70], r15\nmov r15, rcx\nmov [rsp+78h+var_68], rdi\nmov [rsp+78h+var_5C], r8d\nloc_12DB:\nmov r8d, [r15+r12*4]\nlea rcx, unk_2004\nmov edx, 0Ah\nmov esi, 2\nmov rdi, r14\nmov eax, 0\ncall ___sprintf_chk\nmovzx edx, [rsp+78h+var_4A]\ntest dl, dl\njz short loc_1327\nlea eax, [rbx+1]\ncdqe\nmovsxd rbx, ebx\nmov rcx, r14\nsub rcx, rbx\nloc_1314:\nmov [rax+rbp], dl\nmov rbx, rax\nadd rax, 1\nmovzx edx, byte ptr [rcx+rax-1]\ntest dl, dl\njnz short loc_1314\nloc_1327:\ncmp r12, 2\njz loc_1240\nlea eax, [rbx+1]\nmovsxd rdx, ebx\nmov byte ptr [r13+rdx+0], 2Ch ; ','\nadd ebx, 2\ncdqe\nmov byte ptr [r13+rax+0], 20h ; ' '\nadd r12, 1\njmp short loc_12DB\nloc_134E:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(_DWORD *a1, int a2, int a3)\n{\n _DWORD *v5; // rdi\n int v6; // r9d\n _DWORD *v7; // r15\n char *result; // rax\n int v9; // eax\n int v10; // ebx\n __int64 v11; // r12\n char v12; // dl\n __int64 v13; // rax\n _BYTE *v14; // rcx\n int v15; // eax\n int v16; // [rsp+1Ch] [rbp-5Ch]\n _BYTE v17[10]; // [rsp+2Eh] [rbp-4Ah] BYREF\n unsigned __int64 v18; // [rsp+38h] [rbp-40h]\n\n v18 = __readfsqword(0x28u);\n res_1[0] = 91;\n if ( a2 <= 0 )\n {\n v6 = 1;\n }\n else\n {\n v5 = &a1[3 * a2];\n v6 = 1;\n v7 = a1;\n do\n {\n if ( !(*v7 % a3) && !(v7[1] % a3) && !(v7[2] % a3) )\n {\n if ( res_1[v6 - 1] != 91 )\n {\n v9 = v6 + 1;\n res_1[v6] = 44;\n v6 += 2;\n res_1[v9] = 32;\n }\n v10 = v6 + 1;\n res_1[v6] = 40;\n v11 = 0LL;\n v16 = a3;\n while ( 1 )\n {\n __sprintf_chk(v17, 2LL, 10LL, &unk_2004, (unsigned int)v7[v11]);\n v12 = v17[0];\n if ( v17[0] )\n {\n v13 = v10 + 1;\n v14 = &v17[-v10];\n do\n {\n res_1[v13 - 1] = v12;\n v10 = v13++;\n v12 = v14[v13 - 1];\n }\n while ( v12 );\n }\n if ( v11 == 2 )\n break;\n v15 = v10 + 1;\n res_1[v10] = 44;\n v10 += 2;\n res_1[v15] = 32;\n ++v11;\n }\n a3 = v16;\n v6 = v10 + 1;\n res_1[v10] = 41;\n }\n v7 += 3;\n }\n while ( v7 != v5 );\n }\n result = res_1;\n res_1[v6] = 93;\n res_1[v6 + 1] = 0;\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 48h\nmov rax, fs:28h\nmov [rsp+78h+var_40], rax\nxor eax, eax\nmov cs:byte_4040, 5Bh ; '['\ntest esi, esi\njle short loc_11FD\nmov r8d, edx\nmov rcx, rdi\nmovsxd rsi, esi\nlea rax, [rsi+rsi*2]\nlea rdi, [rdi+rax*4]\nmov r9d, 1\nlea r13, byte_4040\nlea rbp, [r13-1]\nmov r15, rcx\njmp short loc_1265\nloc_11FD:\nmov r9d, 1\nloc_1203:\nlea rax, byte_4040\nmovsxd rdx, r9d\nmov byte ptr [rax+rdx], 5Dh ; ']'\nadd r9d, 1\nmovsxd r9, r9d\nmov byte ptr [rax+r9], 0\nmov rdx, [rsp+78h+var_40]\nsub rdx, fs:28h\njnz loc_134E\nadd rsp, 48h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1240:\nmov r15, [rsp+78h+var_70]\nmov rdi, [rsp+78h+var_68]\nmov r8d, [rsp+78h+var_5C]\nlea r9d, [rbx+1]\nmovsxd rbx, ebx\nmov byte ptr [r13+rbx+0], 29h ; ')'\nloc_125C:\nadd r15, 0Ch\ncmp r15, rdi\njz short loc_1203\nloc_1265:\nmov rcx, r15\nmov eax, [r15]\ncdq\nidiv r8d\ntest edx, edx\njnz short loc_125C\nmov eax, [r15+4]\ncdq\nidiv r8d\ntest edx, edx\njnz short loc_125C\nmov eax, [rcx+8]\ncdq\nidiv r8d\ntest edx, edx\njnz short loc_125C\nlea eax, [r9-1]\ncdqe\ncmp byte ptr [r13+rax+0], 5Bh ; '['\njz short loc_12B1\nlea eax, [r9+1]\nmovsxd rdx, r9d\nmov byte ptr [r13+rdx+0], 2Ch ; ','\nadd r9d, 2\ncdqe\nmov byte ptr [r13+rax+0], 20h ; ' '\nloc_12B1:\nlea ebx, [r9+1]\nmovsxd r9, r9d\nmov byte ptr [r13+r9+0], 28h ; '('\nmov r12d, 0\nlea r14, [rsp+78h+var_4A]\nmov [rsp+78h+var_70], r15\nmov r15, rcx\nmov [rsp+78h+var_68], rdi\nmov [rsp+78h+var_5C], r8d\nloc_12DB:\nmov r8d, [r15+r12*4]\nlea rcx, unk_2004\nmov edx, 0Ah\nmov esi, 2\nmov rdi, r14\nmov eax, 0\ncall ___sprintf_chk\nmovzx edx, [rsp+78h+var_4A]\ntest dl, dl\njz short loc_1327\nlea eax, [rbx+1]\ncdqe\nmovsxd rbx, ebx\nmov rcx, r14\nsub rcx, rbx\nloc_1314:\nmov [rax+rbp], dl\nmov rbx, rax\nadd rax, 1\nmovzx edx, byte ptr [rcx+rax-1]\ntest dl, dl\njnz short loc_1314\nloc_1327:\ncmp r12, 2\njz loc_1240\nlea eax, [rbx+1]\nmovsxd rdx, ebx\nmov byte ptr [r13+rdx+0], 2Ch ; ','\nadd ebx, 2\ncdqe\nmov byte ptr [r13+rax+0], 20h ; ' '\nadd r12, 1\njmp short loc_12DB\nloc_134E:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_11A9(_DWORD *a1, int a2, int a3)\n{\n _DWORD *v5; // rdi\n int v6; // r9d\n _DWORD *v7; // r15\n char *result; // rax\n int v9; // eax\n int v10; // ebx\n __int64 v11; // r12\n char v12; // dl\n __int64 v13; // rax\n _BYTE *v14; // rcx\n int v15; // eax\n int v16; // [rsp+1Ch] [rbp-5Ch]\n _BYTE v17[10]; // [rsp+2Eh] [rbp-4Ah] BYREF\n unsigned __int64 v18; // [rsp+38h] [rbp-40h]\n\n v18 = __readfsqword(0x28u);\n byte_4040[0] = 91;\n if ( a2 <= 0 )\n {\n v6 = 1;\n }\n else\n {\n v5 = &a1[3 * a2];\n v6 = 1;\n v7 = a1;\n do\n {\n if ( !(*v7 % a3) && !(v7[1] % a3) && !(v7[2] % a3) )\n {\n if ( byte_4040[v6 - 1] != 91 )\n {\n v9 = v6 + 1;\n byte_4040[v6] = 44;\n v6 += 2;\n byte_4040[v9] = 32;\n }\n v10 = v6 + 1;\n byte_4040[v6] = 40;\n v11 = 0LL;\n v16 = a3;\n while ( 1 )\n {\n __sprintf_chk(v17, 2LL, 10LL, &unk_2004, (unsigned int)v7[v11]);\n v12 = v17[0];\n if ( v17[0] )\n {\n v13 = v10 + 1;\n v14 = &v17[-v10];\n do\n {\n byte_4040[v13 - 1] = v12;\n v10 = v13++;\n v12 = v14[v13 - 1];\n }\n while ( v12 );\n }\n if ( v11 == 2 )\n break;\n v15 = v10 + 1;\n byte_4040[v10] = 44;\n v10 += 2;\n byte_4040[v15] = 32;\n ++v11;\n }\n a3 = v16;\n v6 = v10 + 1;\n byte_4040[v10] = 41;\n }\n v7 += 3;\n }\n while ( v7 != v5 );\n }\n result = byte_4040;\n byte_4040[v6] = 93;\n byte_4040[v6 + 1] = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11A9(uint32_t *a1, int a2, int a3) {\n uint32_t *v5;\n int v6;\n uint32_t *v7;\n char *result;\n int v9;\n int v10;\n long long v11;\n char v12;\n long long v13;\n uint8_t *v14;\n int v15;\n int v16;\n uint8_t v17[10];\n unsigned long long v18;\n v18 = __readfsqword(40u);\n byte_4040[0] = 91;\n if (a2 <= 0) {\n v6 = 1;\n } else {\n v5 = &a1[3 * a2];\n v6 = 1;\n v7 = a1;\n do {\n if (!(*v7 % a3) && !(v7[1] % a3) && !(v7[2] % a3)) {\n if (byte_4040[v6 - 1] != 91) {\n v9 = v6 + 1;\n byte_4040[v6] = 44;\n v6 += 2;\n byte_4040[v9] = 32;\n }\n v10 = v6 + 1;\n byte_4040[v6] = 40;\n v11 = 0LL;\n v16 = a3;\n while (1) {\n __sprintf_chk(v17, 2LL, 10LL, &unk_2004, (unsigned int)v7[v11]);\n v12 = v17[0];\n if (v17[0]) {\n v13 = v10 + 1;\n v14 = &v17[-v10];\n do {\n byte_4040[v13 - 1] = v12;\n v10 = v13++;\n v12 = v14[v13 - 1];\n } while (v12);\n }\n if (v11 == 2) break;\n v15 = v10 + 1;\n byte_4040[v10] = 44;\n v10 += 2;\n byte_4040[v15] = 32;\n ++v11;\n }\n a3 = v16;\n v6 = v10 + 1;\n byte_4040[v10] = 41;\n }\n v7 += 3;\n } while (v7 != v5);\n }\n result = byte_4040;\n byte_4040[v6] = 93;\n byte_4040[v6 + 1] = 0;\n return result;\n}", + "ida_pseudo_norm": "char *func0(uint32_t *a1, int a2, int a3) {\n uint32_t *v5;\n int v6;\n uint32_t *v7;\n char *result;\n int v9;\n int v10;\n long long v11;\n char v12;\n long long v13;\n uint8_t *v14;\n int v15;\n int v16;\n uint8_t v17[10];\n unsigned long long v18;\n v18 = __readfsqword(40u);\n res_1[0] = 91;\n if (a2 <= 0) {\n v6 = 1;\n } else {\n v5 = &a1[3 * a2];\n v6 = 1;\n v7 = a1;\n do {\n if (!(*v7 % a3) && !(v7[1] % a3) && !(v7[2] % a3)) {\n if (res_1[v6 - 1] != 91) {\n v9 = v6 + 1;\n res_1[v6] = 44;\n v6 += 2;\n res_1[v9] = 32;\n }\n v10 = v6 + 1;\n res_1[v6] = 40;\n v11 = 0LL;\n v16 = a3;\n while (1) {\n __sprintf_chk(v17, 2LL, 10LL, &unk_2004, (unsigned int)v7[v11]);\n v12 = v17[0];\n if (v17[0]) {\n v13 = v10 + 1;\n v14 = &v17[-v10];\n do {\n res_1[v13 - 1] = v12;\n v10 = v13++;\n v12 = v14[v13 - 1];\n } while (v12);\n }\n if (v11 == 2) break;\n v15 = v10 + 1;\n res_1[v10] = 44;\n v10 += 2;\n res_1[v15] = 32;\n ++v11;\n }\n a3 = v16;\n v6 = v10 + 1;\n res_1[v10] = 41;\n }\n v7 += 3;\n } while (v7 != v5);\n }\n result = res_1;\n res_1[v6] = 93;\n res_1[v6 + 1] = 0;\n return result;\n}" + }, + { + "index": 75, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(int test_list[][3], int list_size, int K) {\n static char res[100];\n int index = 0;\n res[index++] = '[';\n for (int i = 0; i < list_size; i++) {\n bool divisible = true;\n for (int j = 0; j < 3; j++) {\n if (test_list[i][j] % K != 0) {\n divisible = false;\n break;\n }\n }\n if (divisible) {\n if (res[index - 1] != '[') {\n res[index++] = ',';\n res[index++] = ' ';\n }\n res[index++] = '(';\n for (int j = 0; j < 3; j++) {\n char numStr[10];\n sprintf(numStr, \"%d\", test_list[i][j]);\n for (int k = 0; numStr[k] != '\\0'; k++) {\n res[index++] = numStr[k];\n }\n if (j != 2) {\n res[index++] = ',';\n res[index++] = ' ';\n }\n }\n res[index++] = ')';\n }\n }\n res[index++] = ']';\n res[index] = '\\0';\n return res;\n}", + "test": "int main() {\n\n int list1[][3] = {{6, 24, 12}, {7, 9, 6}, {12, 18, 21}};\n\n int list2[][3] = {{5, 25, 30}, {4, 2, 3}, {7, 8, 9}};\n\n int list3[][3] = {{7, 9, 16}, {8, 16, 4}, {19, 17, 18}};\n\n \n\n assert(strcmp(func0(list1, 3, 6), \"[(6, 24, 12)]\") == 0);\n\n assert(strcmp(func0(list2, 3, 5), \"[(5, 25, 30)]\") == 0);\n\n assert(strcmp(func0(list3, 3, 4), \"[(8, 16, 4)]\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x38,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x28(%rsp)\nxor %eax,%eax\nmovb $0x5b,0x2c87(%rip)\ntest %esi,%esi\njle 1522 \nlea -0x1(%rsi),%eax\nlea 0x2c75(%rip),%r13\nmov %edx,%r14d\nmov %rdi,%rbp\nlea (%rax,%rax,2),%rax\nmov $0x1,%ecx\nlea -0x1(%r13),%r12\nlea 0xc(%rdi,%rax,4),%rax\nmov %rax,0x8(%rsp)\nnopl 0x0(%rax,%rax,1)\nmov 0x0(%rbp),%eax\ncltd\nidiv %r14d\ntest %edx,%edx\njne 14d9 \nmov 0x4(%rbp),%eax\ncltd\nidiv %r14d\ntest %edx,%edx\njne 14d9 \nmov 0x8(%rbp),%eax\ncltd\nidiv %r14d\ntest %edx,%edx\njne 14d9 \nlea -0x1(%rcx),%eax\nlea 0x1(%rcx),%ebx\ncltq\ncmpb $0x5b,0x0(%r13,%rax,1)\nje 1445 \nmovslq %ecx,%rax\nmovslq %ebx,%rbx\nmovb $0x2c,0x0(%r13,%rax,1)\nmovb $0x20,0x0(%r13,%rbx,1)\nlea 0x3(%rcx),%ebx\nadd $0x2,%ecx\nmovslq %ecx,%rcx\nxor %r15d,%r15d\nlea 0x1e(%rsp),%rdi\nmovb $0x28,0x0(%r13,%rcx,1)\nmov 0x0(%rbp,%r15,4),%r8d\nmov $0xa,%edx\nxor %eax,%eax\nmov %rdi,(%rsp)\nlea 0xb97(%rip),%rcx\nmov $0x1,%esi\ncallq 1090 <__sprintf_chk@plt>\nmovzbl 0x1e(%rsp),%edx\nmov (%rsp),%rdi\ntest %dl,%dl\nje 14ab \nlea 0x1(%rbx),%eax\nmov %rdi,%rcx\nmovslq %ebx,%rbx\ncltq\nsub %rbx,%rcx\nnopw 0x0(%rax,%rax,1)\nmov %dl,(%r12,%rax,1)\nmov %eax,%ebx\nadd $0x1,%rax\nmovzbl -0x1(%rcx,%rax,1),%edx\ntest %dl,%dl\njne 1498 \nlea 0x1(%rbx),%ecx\ncmp $0x2,%r15\nje 14d0 \nmovslq %ebx,%rax\nmovslq %ecx,%rcx\nadd $0x2,%ebx\nadd $0x1,%r15\nmovb $0x2c,0x0(%r13,%rax,1)\nmovb $0x20,0x0(%r13,%rcx,1)\njmp 1456 \nmovslq %ebx,%rbx\nmovb $0x29,0x0(%r13,%rbx,1)\nadd $0xc,%rbp\ncmp 0x8(%rsp),%rbp\njne 13f0 \nlea 0x1(%rcx),%eax\ncltq\nmovslq %ecx,%rcx\nmovb $0x5d,0x0(%r13,%rcx,1)\nmovb $0x0,0x0(%r13,%rax,1)\nmov 0x28(%rsp),%rax\nxor %fs:0x28,%rax\njne 1535 \nadd $0x38,%rsp\nlea 0x2b29(%rip),%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmov $0x2,%eax\nmov $0x1,%ecx\nlea 0x2b0d(%rip),%r13\njmp 14eb \ncallq 1070 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov r10d, 1\npush r14\npush r13\npush r12\npush rbp\npush rbx\nlea rbx, res_1\nsub rsp, 38h\nmov rax, fs:28h\nmov [rsp+68h+var_40], rax\nxor eax, eax\nmov cs:res_1, 5Bh ; '['\nmov eax, 2\ntest esi, esi\njle loc_14AF\nmovsxd rsi, esi\nlea rbx, res_1\nmov r9, rdi\nmov r10d, 1\nlea rax, [rsi+rsi*2]\nlea r12, [rbx-1]\nmov rbp, rbx\nmov ebx, edx\nlea rsi, [rdi+rax*4]\nnop word ptr [rax+rax+00000000h]\nloc_13A0:\nmov eax, [r9]\ncdq\nidiv ebx\ntest edx, edx\njnz loc_14E0\nmov eax, [r9+4]\ncdq\nidiv ebx\ntest edx, edx\njnz loc_14E0\nmov eax, [r9+8]\ncdq\nidiv ebx\ntest edx, edx\njnz loc_14E0\nlea eax, [r10-1]\ncdqe\ncmp byte ptr [rbp+rax+0], 5Bh ; '['\njz short loc_13EC\nmovzx edi, cs:word_20F6\nmovsxd rax, r10d\nadd r10d, 2\nmov [rbp+rax+0], di\nloc_13EC:\nlea r13d, [r10+1]\nmovsxd r10, r10d\nmov [rsp+68h+var_68], rsi\nmov r14, r9\nmov byte ptr [rbp+r10+0], 28h ; '('\nlea r9, [r9+0Ch]\nlea r15, [rsp+68h+var_4A]\nmov [rsp+68h+var_5C], ebx\nmov rbx, r14\nmov r14d, r13d\nmov r13, r9\nloc_1416:\nmov r8d, [rbx]\nmov edx, 0Ah\nmov esi, 2\nmov rdi, r15\nlea rcx, unk_2004\nxor eax, eax\ncall ___sprintf_chk\nmovzx edx, [rsp+68h+var_4A]\ntest dl, dl\njz loc_14F0\nlea eax, [r14+1]\nmovsxd r9, r14d\nmov rsi, r15\ncdqe\nsub rsi, r9\nloc_1450:\nmov [r12+rax], dl\nmov rcx, rax\nadd rax, 1\nmovzx edx, byte ptr [rsi+rax-1]\ntest dl, dl\njnz short loc_1450\nloc_1464:\nadd rbx, 4\ncmp rbx, r13\njz short loc_1488\nmovzx eax, cs:word_20F6\nlea r14d, [rcx+2]\nmovsxd rcx, ecx\nmov [rbp+rcx+0], ax\njmp short loc_1416\nloc_1488:\nlea r10d, [rcx+1]\nmovsxd rcx, ecx\nmov rsi, [rsp+68h+var_68]\nmov ebx, [rsp+68h+var_5C]\nmov byte ptr [rbp+rcx+0], 29h ; ')'\nmov r9, r13\nloc_149F:\ncmp r9, rsi\njnz loc_13A0\nmov rbx, rbp\nlea eax, [r10+1]\nloc_14AF:\nmovsxd r10, r10d\ncdqe\nmov byte ptr [rbx+r10], 5Dh ; ']'\nmov byte ptr [rbx+rax], 0\nmov rax, [rsp+68h+var_40]\nsub rax, fs:28h\njnz short loc_14F8\nadd rsp, 38h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14E0:\nadd r9, 0Ch\njmp short loc_149F\nloc_14F0:\nmov ecx, r14d\njmp loc_1464\nloc_14F8:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(unsigned int *a1, int a2, int a3)\n{\n int v3; // r10d\n int v4; // eax\n unsigned int *v5; // r9\n unsigned int *v7; // rsi\n __int64 v8; // rax\n unsigned int *v9; // rbx\n int v10; // r14d\n unsigned int *v11; // r13\n char v12; // dl\n __int64 v13; // rax\n int v14; // ecx\n int v16; // [rsp+Ch] [rbp-5Ch]\n _BYTE v17[10]; // [rsp+1Eh] [rbp-4Ah] BYREF\n unsigned __int64 v18; // [rsp+28h] [rbp-40h]\n\n v3 = 1;\n v18 = __readfsqword(0x28u);\n res_1[0] = 91;\n v4 = 2;\n if ( a2 > 0 )\n {\n v5 = a1;\n v3 = 1;\n v7 = &a1[3 * a2];\n do\n {\n if ( (int)*v5 % a3 || (int)v5[1] % a3 || (int)v5[2] % a3 )\n {\n v5 += 3;\n }\n else\n {\n if ( res_1[v3 - 1] != 91 )\n {\n v8 = v3;\n v3 += 2;\n *(_WORD *)&res_1[v8] = 8236;\n }\n res_1[v3] = 40;\n v16 = a3;\n v9 = v5;\n v10 = v3 + 1;\n v11 = v5 + 3;\n while ( 1 )\n {\n __sprintf_chk(v17, 2LL, 10LL, &unk_2004, *v9);\n v12 = v17[0];\n if ( v17[0] )\n {\n v13 = v10 + 1;\n do\n {\n res_1[v13 - 1] = v12;\n v14 = v13++;\n v12 = v17[v13 - v10 - 1];\n }\n while ( v12 );\n }\n else\n {\n v14 = v10;\n }\n if ( ++v9 == v11 )\n break;\n v10 = v14 + 2;\n *(_WORD *)&res_1[v14] = 8236;\n }\n v3 = v14 + 1;\n a3 = v16;\n res_1[v14] = 41;\n v5 = v11;\n }\n }\n while ( v5 != v7 );\n v4 = v3 + 1;\n }\n res_1[v3] = 93;\n res_1[v4] = 0;\n return res_1;\n}", + "ida_strip_asm": "sub_1330:\nendbr64\npush r15\nmov r10d, 1\npush r14\npush r13\npush r12\npush rbp\npush rbx\nlea rbx, byte_4040\nsub rsp, 38h\nmov rax, fs:28h\nmov [rsp+68h+var_40], rax\nxor eax, eax\nmov cs:byte_4040, 5Bh ; '['\nmov eax, 2\ntest esi, esi\njle loc_14AF\nmovsxd rsi, esi\nlea rbx, byte_4040\nmov r9, rdi\nmov r10d, 1\nlea rax, [rsi+rsi*2]\nlea r12, [rbx-1]\nmov rbp, rbx\nmov ebx, edx\nlea rsi, [rdi+rax*4]\nnop word ptr [rax+rax+00000000h]\nloc_13A0:\nmov eax, [r9]\ncdq\nidiv ebx\ntest edx, edx\njnz loc_14E0\nmov eax, [r9+4]\ncdq\nidiv ebx\ntest edx, edx\njnz loc_14E0\nmov eax, [r9+8]\ncdq\nidiv ebx\ntest edx, edx\njnz loc_14E0\nlea eax, [r10-1]\ncdqe\ncmp byte ptr [rbp+rax+0], 5Bh ; '['\njz short loc_13EC\nmovzx edi, cs:word_20F6\nmovsxd rax, r10d\nadd r10d, 2\nmov [rbp+rax+0], di\nloc_13EC:\nlea r13d, [r10+1]\nmovsxd r10, r10d\nmov [rsp+68h+var_68], rsi\nmov r14, r9\nmov byte ptr [rbp+r10+0], 28h ; '('\nlea r9, [r9+0Ch]\nlea r15, [rsp+68h+var_4A]\nmov [rsp+68h+var_5C], ebx\nmov rbx, r14\nmov r14d, r13d\nmov r13, r9\nloc_1416:\nmov r8d, [rbx]\nmov edx, 0Ah\nmov esi, 2\nmov rdi, r15\nlea rcx, unk_2004\nxor eax, eax\ncall ___sprintf_chk\nmovzx edx, [rsp+68h+var_4A]\ntest dl, dl\njz loc_14F0\nlea eax, [r14+1]\nmovsxd r9, r14d\nmov rsi, r15\ncdqe\nsub rsi, r9\nloc_1450:\nmov [r12+rax], dl\nmov rcx, rax\nadd rax, 1\nmovzx edx, byte ptr [rsi+rax-1]\ntest dl, dl\njnz short loc_1450\nloc_1464:\nadd rbx, 4\ncmp rbx, r13\njz short loc_1488\nmovzx eax, cs:word_20F6\nlea r14d, [rcx+2]\nmovsxd rcx, ecx\nmov [rbp+rcx+0], ax\njmp short loc_1416\nloc_1488:\nlea r10d, [rcx+1]\nmovsxd rcx, ecx\nmov rsi, [rsp+68h+var_68]\nmov ebx, [rsp+68h+var_5C]\nmov byte ptr [rbp+rcx+0], 29h ; ')'\nmov r9, r13\nloc_149F:\ncmp r9, rsi\njnz loc_13A0\nmov rbx, rbp\nlea eax, [r10+1]\nloc_14AF:\nmovsxd r10, r10d\ncdqe\nmov byte ptr [rbx+r10], 5Dh ; ']'\nmov byte ptr [rbx+rax], 0\nmov rax, [rsp+68h+var_40]\nsub rax, fs:28h\njnz short loc_14F8\nadd rsp, 38h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14E0:\nadd r9, 0Ch\njmp short loc_149F\nloc_14F0:\nmov ecx, r14d\njmp loc_1464\nloc_14F8:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_1330(unsigned int *a1, int a2, int a3)\n{\n int v3; // r10d\n int v4; // eax\n unsigned int *v5; // r9\n unsigned int *v7; // rsi\n __int64 v8; // rax\n unsigned int *v9; // rbx\n int v10; // r14d\n unsigned int *v11; // r13\n char v12; // dl\n __int64 v13; // rax\n int v14; // ecx\n int v16; // [rsp+Ch] [rbp-5Ch]\n _BYTE v17[10]; // [rsp+1Eh] [rbp-4Ah] BYREF\n unsigned __int64 v18; // [rsp+28h] [rbp-40h]\n\n v3 = 1;\n v18 = __readfsqword(0x28u);\n byte_4040[0] = 91;\n v4 = 2;\n if ( a2 > 0 )\n {\n v5 = a1;\n v3 = 1;\n v7 = &a1[3 * a2];\n do\n {\n if ( (int)*v5 % a3 || (int)v5[1] % a3 || (int)v5[2] % a3 )\n {\n v5 += 3;\n }\n else\n {\n if ( byte_4040[v3 - 1] != 91 )\n {\n v8 = v3;\n v3 += 2;\n *(_WORD *)&byte_4040[v8] = 8236;\n }\n byte_4040[v3] = 40;\n v16 = a3;\n v9 = v5;\n v10 = v3 + 1;\n v11 = v5 + 3;\n while ( 1 )\n {\n __sprintf_chk(v17, 2LL, 10LL, &unk_2004, *v9);\n v12 = v17[0];\n if ( v17[0] )\n {\n v13 = v10 + 1;\n do\n {\n byte_4040[v13 - 1] = v12;\n v14 = v13++;\n v12 = v17[v13 - v10 - 1];\n }\n while ( v12 );\n }\n else\n {\n v14 = v10;\n }\n if ( ++v9 == v11 )\n break;\n v10 = v14 + 2;\n *(_WORD *)&byte_4040[v14] = 8236;\n }\n v3 = v14 + 1;\n a3 = v16;\n byte_4040[v14] = 41;\n v5 = v11;\n }\n }\n while ( v5 != v7 );\n v4 = v3 + 1;\n }\n byte_4040[v3] = 93;\n byte_4040[v4] = 0;\n return byte_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1330(unsigned int *a1, int a2, int a3) {\n int v3;\n int v4;\n unsigned int *v5;\n unsigned int *v7;\n long long v8;\n unsigned int *v9;\n int v10;\n unsigned int *v11;\n char v12;\n long long v13;\n int v14;\n int v16;\n uint8_t v17[10];\n unsigned long long v18;\n v3 = 1;\n v18 = __readfsqword(40u);\n byte_4040[0] = 91;\n v4 = 2;\n if (a2 > 0) {\n v5 = a1;\n v3 = 1;\n v7 = &a1[3 * a2];\n do {\n if ((int)*v5 % a3 || (int)v5[1] % a3 || (int)v5[2] % a3) {\n v5 += 3;\n } else {\n if (byte_4040[v3 - 1] != 91) {\n v8 = v3;\n v3 += 2;\n *(unsigned short *)&byte_4040[v8] = 8236;\n }\n byte_4040[v3] = 40;\n v16 = a3;\n v9 = v5;\n v10 = v3 + 1;\n v11 = v5 + 3;\n while (1) {\n __sprintf_chk(v17, 2LL, 10LL, &unk_2004, *v9);\n v12 = v17[0];\n if (v17[0]) {\n v13 = v10 + 1;\n do {\n byte_4040[v13 - 1] = v12;\n v14 = v13++;\n v12 = v17[v13 - v10 - 1];\n } while (v12);\n } else {\n v14 = v10;\n }\n if (++v9 == v11) break;\n v10 = v14 + 2;\n *(unsigned short *)&byte_4040[v14] = 8236;\n }\n v3 = v14 + 1;\n a3 = v16;\n byte_4040[v14] = 41;\n v5 = v11;\n }\n } while (v5 != v7);\n v4 = v3 + 1;\n }\n byte_4040[v3] = 93;\n byte_4040[v4] = 0;\n return byte_4040;\n}", + "ida_pseudo_norm": "char *func0(unsigned int *a1, int a2, int a3) {\n int v3;\n int v4;\n unsigned int *v5;\n unsigned int *v7;\n long long v8;\n unsigned int *v9;\n int v10;\n unsigned int *v11;\n char v12;\n long long v13;\n int v14;\n int v16;\n uint8_t v17[10];\n unsigned long long v18;\n v3 = 1;\n v18 = __readfsqword(40u);\n res_1[0] = 91;\n v4 = 2;\n if (a2 > 0) {\n v5 = a1;\n v3 = 1;\n v7 = &a1[3 * a2];\n do {\n if ((int)*v5 % a3 || (int)v5[1] % a3 || (int)v5[2] % a3) {\n v5 += 3;\n } else {\n if (res_1[v3 - 1] != 91) {\n v8 = v3;\n v3 += 2;\n *(unsigned short *)&res_1[v8] = 8236;\n }\n res_1[v3] = 40;\n v16 = a3;\n v9 = v5;\n v10 = v3 + 1;\n v11 = v5 + 3;\n while (1) {\n __sprintf_chk(v17, 2LL, 10LL, &unk_2004, *v9);\n v12 = v17[0];\n if (v17[0]) {\n v13 = v10 + 1;\n do {\n res_1[v13 - 1] = v12;\n v14 = v13++;\n v12 = v17[v13 - v10 - 1];\n } while (v12);\n } else {\n v14 = v10;\n }\n if (++v9 == v11) break;\n v10 = v14 + 2;\n *(unsigned short *)&res_1[v14] = 8236;\n }\n v3 = v14 + 1;\n a3 = v16;\n res_1[v14] = 41;\n v5 = v11;\n }\n } while (v5 != v7);\n v4 = v3 + 1;\n }\n res_1[v3] = 93;\n res_1[v4] = 0;\n return res_1;\n}" + }, + { + "index": 75, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(int test_list[][3], int list_size, int K) {\n static char res[100];\n int index = 0;\n res[index++] = '[';\n for (int i = 0; i < list_size; i++) {\n bool divisible = true;\n for (int j = 0; j < 3; j++) {\n if (test_list[i][j] % K != 0) {\n divisible = false;\n break;\n }\n }\n if (divisible) {\n if (res[index - 1] != '[') {\n res[index++] = ',';\n res[index++] = ' ';\n }\n res[index++] = '(';\n for (int j = 0; j < 3; j++) {\n char numStr[10];\n sprintf(numStr, \"%d\", test_list[i][j]);\n for (int k = 0; numStr[k] != '\\0'; k++) {\n res[index++] = numStr[k];\n }\n if (j != 2) {\n res[index++] = ',';\n res[index++] = ' ';\n }\n }\n res[index++] = ')';\n }\n }\n res[index++] = ']';\n res[index] = '\\0';\n return res;\n}", + "test": "int main() {\n\n int list1[][3] = {{6, 24, 12}, {7, 9, 6}, {12, 18, 21}};\n\n int list2[][3] = {{5, 25, 30}, {4, 2, 3}, {7, 8, 9}};\n\n int list3[][3] = {{7, 9, 16}, {8, 16, 4}, {19, 17, 18}};\n\n \n\n assert(strcmp(func0(list1, 3, 6), \"[(6, 24, 12)]\") == 0);\n\n assert(strcmp(func0(list2, 3, 5), \"[(5, 25, 30)]\") == 0);\n\n assert(strcmp(func0(list3, 3, 4), \"[(8, 16, 4)]\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x38,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x28(%rsp)\nxor %eax,%eax\nmovb $0x5b,0x2ce7(%rip)\ntest %esi,%esi\njle 1567 \nlea -0x1(%rsi),%eax\nmov %edx,%r13d\nmov %rdi,%r12\nmov $0x1,%ecx\nlea (%rax,%rax,2),%rax\nlea 0x2cc6(%rip),%rbp\nlea 0xc(%rdi,%rax,4),%rax\nmov %rax,0x8(%rsp)\nnopl 0x0(%rax)\nmov (%r12),%eax\nlea 0x1(%rcx),%ebx\ncltd\nidiv %r13d\ntest %edx,%edx\njne 1508 \nmov 0x4(%r12),%eax\ncltd\nidiv %r13d\ntest %edx,%edx\njne 1508 \nmov 0x8(%r12),%eax\ncltd\nidiv %r13d\ntest %edx,%edx\njne 1508 \nlea -0x1(%rcx),%eax\ncltq\ncmpb $0x5b,0x0(%rbp,%rax,1)\nje 13df \nmovslq %ecx,%rax\nmovslq %ebx,%rbx\nmovb $0x2c,0x0(%rbp,%rax,1)\nmovb $0x20,0x0(%rbp,%rbx,1)\nlea 0x3(%rcx),%ebx\nadd $0x2,%ecx\nmovslq %ecx,%rcx\nxor %r15d,%r15d\nlea 0x1e(%rsp),%r14\nmovb $0x28,0x0(%rbp,%rcx,1)\nmov (%r12,%r15,4),%r8d\nmov $0xa,%edx\nmov $0x1,%esi\nxor %eax,%eax\nlea 0xbfe(%rip),%rcx\nmov %r14,%rdi\ncallq 1090 <__sprintf_chk@plt>\nmovzbl 0x1e(%rsp),%edx\ntest %dl,%dl\nje 14d9 \nmovslq %ebx,%rcx\nlea 0x1(%rbx),%eax\nmov %dl,0x0(%rbp,%rcx,1)\nmovzbl 0x1f(%rsp),%ecx\ntest %cl,%cl\nje 1550 \ncltq\nlea 0x2(%rbx),%edx\nmov %cl,0x0(%rbp,%rax,1)\nmovzbl 0x20(%rsp),%ecx\ntest %cl,%cl\nje 1560 \nmovslq %edx,%rdx\nlea 0x3(%rbx),%eax\nmov %cl,0x0(%rbp,%rdx,1)\nmovzbl 0x21(%rsp),%ecx\ntest %cl,%cl\nje 1550 \ncltq\nlea 0x4(%rbx),%edx\nmov %cl,0x0(%rbp,%rax,1)\nmovzbl 0x22(%rsp),%ecx\ntest %cl,%cl\nje 1560 \nmovslq %edx,%rdx\nlea 0x5(%rbx),%eax\nmov %cl,0x0(%rbp,%rdx,1)\nmovzbl 0x23(%rsp),%ecx\ntest %cl,%cl\nje 1550 \ncltq\nlea 0x6(%rbx),%edx\nmov %cl,0x0(%rbp,%rax,1)\nmovzbl 0x24(%rsp),%ecx\ntest %cl,%cl\nje 1560 \nmovslq %edx,%rdx\nlea 0x7(%rbx),%eax\nmov %cl,0x0(%rbp,%rdx,1)\nmovzbl 0x25(%rsp),%ecx\ntest %cl,%cl\nje 1550 \ncltq\nlea 0x8(%rbx),%edx\nmov %cl,0x0(%rbp,%rax,1)\nmovzbl 0x26(%rsp),%eax\ntest %al,%al\nje 1560 \nmovslq %edx,%rdx\nadd $0x9,%ebx\nmov %al,0x0(%rbp,%rdx,1)\nlea 0x1(%rbx),%ecx\nmovslq %ebx,%rax\ncmp $0x2,%r15\nje 1500 \nmovslq %ecx,%rcx\nmovb $0x2c,0x0(%rbp,%rax,1)\nadd $0x2,%ebx\nadd $0x1,%r15\nmovb $0x20,0x0(%rbp,%rcx,1)\njmpq 13ef \nxchg %ax,%ax\nmovb $0x29,0x0(%rbp,%rax,1)\nadd $0x2,%ebx\nadd $0xc,%r12\ncmp 0x8(%rsp),%r12\njne 1388 \nmovslq %ecx,%rcx\nmovslq %ebx,%rbx\nmovb $0x5d,0x0(%rbp,%rcx,1)\nmovb $0x0,0x0(%rbp,%rbx,1)\nmov 0x28(%rsp),%rax\nxor %fs:0x28,%rax\njne 157a \nadd $0x38,%rsp\nlea 0x2afe(%rip),%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl (%rax)\nmov %eax,%ebx\njmpq 14d9 \nnopw 0x0(%rax,%rax,1)\nmov %edx,%ebx\njmpq 14d9 \nmov $0x2,%ebx\nmov $0x1,%ecx\nlea 0x2ac8(%rip),%rbp\njmp 1517 \ncallq 1070 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov ecx, 1\npush r14\npush r13\npush r12\npush rbp\nlea rbp, res_1\npush rbx\nsub rsp, 38h\nmov rax, fs:28h\nmov [rsp+68h+var_40], rax\nxor eax, eax\nmov cs:res_1, 5Bh ; '['\nmov eax, 2\ntest esi, esi\njle loc_151E\nmovsxd rsi, esi\nmov rbx, rdi\nmov r13d, edx\nmov ecx, 1\nlea rax, [rsi+rsi*2]\nlea rbp, res_1\nlea r12, [rdi+rax*4]\nlea rax, [rsp+68h+var_4A]\nmov [rsp+68h+var_60], rax\nnop dword ptr [rax+00000000h]\nloc_13A0:\nmov eax, [rbx]\ncdq\nidiv r13d\ntest edx, edx\njnz loc_1558\nmov eax, [rbx+4]\ncdq\nidiv r13d\ntest edx, edx\njnz loc_1558\nmov eax, [rbx+8]\ncdq\nidiv r13d\ntest edx, edx\njnz loc_1558\nlea eax, [rcx-1]\ncdqe\ncmp byte ptr [rbp+rax+0], 5Bh ; '['\njz short loc_13EA\nmovzx esi, cs:word_20F6\nmovsxd rax, ecx\nadd ecx, 2\nmov [rbp+rax+0], si\nloc_13EA:\nlea r15d, [rcx+1]\nmovsxd rcx, ecx\nmov r14, rbx\nmov byte ptr [rbp+rcx+0], 28h ; '('\nlea rbx, [rbx+0Ch]\nloc_13FD:\nmov r8d, [r14]\nmov rdi, [rsp+68h+var_60]\nmov edx, 0Ah\nxor eax, eax\nlea rcx, unk_2004\nmov esi, 2\ncall ___sprintf_chk\nmovzx edx, [rsp+68h+var_4A]\ntest dl, dl\njz loc_1560\nmovsxd rcx, r15d\nlea eax, [r15+1]\nmov [rbp+rcx+0], dl\nmovzx ecx, [rsp+68h+var_49]\ntest cl, cl\njz loc_14E1\ncdqe\nlea edx, [r15+2]\nmov [rbp+rax+0], cl\nmovzx ecx, [rsp+68h+var_48]\ntest cl, cl\njz loc_1550\nmovsxd rdx, edx\nlea eax, [r15+3]\nmov [rbp+rdx+0], cl\nmovzx ecx, [rsp+68h+var_47]\ntest cl, cl\njz short loc_14E1\ncdqe\nlea edx, [r15+4]\nmov [rbp+rax+0], cl\nmovzx ecx, [rsp+68h+var_46]\ntest cl, cl\njz loc_1550\nmovsxd rdx, edx\nlea eax, [r15+5]\nmov [rbp+rdx+0], cl\nmovzx ecx, [rsp+68h+var_45]\ntest cl, cl\njz short loc_14E1\ncdqe\nlea edx, [r15+6]\nmov [rbp+rax+0], cl\nmovzx ecx, [rsp+68h+var_44]\ntest cl, cl\njz loc_1550\nmovsxd rdx, edx\nlea eax, [r15+7]\nmov [rbp+rdx+0], cl\nmovzx ecx, [rsp+68h+var_43]\ntest cl, cl\njz short loc_14E1\ncdqe\nlea edx, [r15+8]\nmov [rbp+rax+0], cl\nmovzx ecx, [rsp+68h+var_42]\ntest cl, cl\njz short loc_1550\nmovsxd rdx, edx\nlea eax, [r15+9]\nmov [rbp+rdx+0], cl\nloc_14E1:\nadd r14, 4\ncmp r14, rbx\njz short loc_1508\nmovzx edi, cs:word_20F6\nlea r15d, [rax+2]\ncdqe\nmov [rbp+rax+0], di\njmp loc_13FD\nloc_1508:\nlea ecx, [rax+1]\ncdqe\nmov byte ptr [rbp+rax+0], 29h ; ')'\nloc_1512:\ncmp rbx, r12\njnz loc_13A0\nlea eax, [rcx+1]\nloc_151E:\nmovsxd rcx, ecx\ncdqe\nmov byte ptr [rbp+rcx+0], 5Dh ; ']'\nmov byte ptr [rbp+rax+0], 0\nmov rax, [rsp+68h+var_40]\nsub rax, fs:28h\njnz short loc_1568\nadd rsp, 38h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1550:\nmov eax, edx\njmp short loc_14E1\nloc_1558:\nadd rbx, 0Ch\njmp short loc_1512\nloc_1560:\nmov eax, r15d\njmp loc_14E1\nloc_1568:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(unsigned int *a1, int a2, int a3)\n{\n int v3; // ecx\n int v4; // eax\n unsigned int *v5; // rbx\n __int64 v7; // rax\n int v8; // r15d\n unsigned int *v9; // r14\n int v10; // eax\n int v11; // edx\n char v13; // [rsp+1Eh] [rbp-4Ah] BYREF\n char v14; // [rsp+1Fh] [rbp-49h]\n char v15; // [rsp+20h] [rbp-48h]\n char v16; // [rsp+21h] [rbp-47h]\n char v17; // [rsp+22h] [rbp-46h]\n char v18; // [rsp+23h] [rbp-45h]\n char v19; // [rsp+24h] [rbp-44h]\n char v20; // [rsp+25h] [rbp-43h]\n char v21; // [rsp+26h] [rbp-42h]\n unsigned __int64 v22; // [rsp+28h] [rbp-40h]\n\n v3 = 1;\n v22 = __readfsqword(0x28u);\n res_1[0] = 91;\n v4 = 2;\n if ( a2 > 0 )\n {\n v5 = a1;\n v3 = 1;\n while ( (int)*v5 % a3 || (int)v5[1] % a3 || (int)v5[2] % a3 )\n {\n v5 += 3;\nLABEL_22:\n if ( v5 == &a1[3 * a2] )\n {\n v4 = v3 + 1;\n goto LABEL_24;\n }\n }\n if ( res_1[v3 - 1] != 91 )\n {\n v7 = v3;\n v3 += 2;\n *(_WORD *)&res_1[v7] = 8236;\n }\n v8 = v3 + 1;\n v9 = v5;\n res_1[v3] = 40;\n v5 += 3;\n while ( 1 )\n {\n __sprintf_chk(&v13, 2LL, 10LL, &unk_2004, *v9);\n if ( v13 )\n {\n v10 = v8 + 1;\n res_1[v8] = v13;\n if ( !v14 )\n goto LABEL_19;\n v11 = v8 + 2;\n res_1[v10] = v14;\n if ( !v15 )\n goto LABEL_25;\n v10 = v8 + 3;\n res_1[v11] = v15;\n if ( !v16 )\n goto LABEL_19;\n v11 = v8 + 4;\n res_1[v10] = v16;\n if ( !v17 )\n goto LABEL_25;\n v10 = v8 + 5;\n res_1[v11] = v17;\n if ( !v18 )\n goto LABEL_19;\n v11 = v8 + 6;\n res_1[v10] = v18;\n if ( !v19 )\n goto LABEL_25;\n v10 = v8 + 7;\n res_1[v11] = v19;\n if ( !v20 )\n goto LABEL_19;\n v11 = v8 + 8;\n res_1[v10] = v20;\n if ( v21 )\n {\n v10 = v8 + 9;\n res_1[v11] = v21;\n }\n else\n {\nLABEL_25:\n v10 = v11;\n }\n }\n else\n {\n v10 = v8;\n }\nLABEL_19:\n if ( ++v9 == v5 )\n {\n v3 = v10 + 1;\n res_1[v10] = 41;\n goto LABEL_22;\n }\n v8 = v10 + 2;\n *(_WORD *)&res_1[v10] = 8236;\n }\n }\nLABEL_24:\n res_1[v3] = 93;\n res_1[v4] = 0;\n return res_1;\n}", + "ida_strip_asm": "sub_1330:\nendbr64\npush r15\nmov ecx, 1\npush r14\npush r13\npush r12\npush rbp\nlea rbp, byte_4040\npush rbx\nsub rsp, 38h\nmov rax, fs:28h\nmov [rsp+68h+var_40], rax\nxor eax, eax\nmov cs:byte_4040, 5Bh ; '['\nmov eax, 2\ntest esi, esi\njle loc_151E\nmovsxd rsi, esi\nmov rbx, rdi\nmov r13d, edx\nmov ecx, 1\nlea rax, [rsi+rsi*2]\nlea rbp, byte_4040\nlea r12, [rdi+rax*4]\nlea rax, [rsp+68h+var_4A]\nmov [rsp+68h+var_60], rax\nnop dword ptr [rax+00000000h]\nloc_13A0:\nmov eax, [rbx]\ncdq\nidiv r13d\ntest edx, edx\njnz loc_1558\nmov eax, [rbx+4]\ncdq\nidiv r13d\ntest edx, edx\njnz loc_1558\nmov eax, [rbx+8]\ncdq\nidiv r13d\ntest edx, edx\njnz loc_1558\nlea eax, [rcx-1]\ncdqe\ncmp byte ptr [rbp+rax+0], 5Bh ; '['\njz short loc_13EA\nmovzx esi, cs:word_20F6\nmovsxd rax, ecx\nadd ecx, 2\nmov [rbp+rax+0], si\nloc_13EA:\nlea r15d, [rcx+1]\nmovsxd rcx, ecx\nmov r14, rbx\nmov byte ptr [rbp+rcx+0], 28h ; '('\nlea rbx, [rbx+0Ch]\nloc_13FD:\nmov r8d, [r14]\nmov rdi, [rsp+68h+var_60]\nmov edx, 0Ah\nxor eax, eax\nlea rcx, unk_2004\nmov esi, 2\ncall ___sprintf_chk\nmovzx edx, [rsp+68h+var_4A]\ntest dl, dl\njz loc_1560\nmovsxd rcx, r15d\nlea eax, [r15+1]\nmov [rbp+rcx+0], dl\nmovzx ecx, [rsp+68h+var_49]\ntest cl, cl\njz loc_14E1\ncdqe\nlea edx, [r15+2]\nmov [rbp+rax+0], cl\nmovzx ecx, [rsp+68h+var_48]\ntest cl, cl\njz loc_1550\nmovsxd rdx, edx\nlea eax, [r15+3]\nmov [rbp+rdx+0], cl\nmovzx ecx, [rsp+68h+var_47]\ntest cl, cl\njz short loc_14E1\ncdqe\nlea edx, [r15+4]\nmov [rbp+rax+0], cl\nmovzx ecx, [rsp+68h+var_46]\ntest cl, cl\njz loc_1550\nmovsxd rdx, edx\nlea eax, [r15+5]\nmov [rbp+rdx+0], cl\nmovzx ecx, [rsp+68h+var_45]\ntest cl, cl\njz short loc_14E1\ncdqe\nlea edx, [r15+6]\nmov [rbp+rax+0], cl\nmovzx ecx, [rsp+68h+var_44]\ntest cl, cl\njz loc_1550\nmovsxd rdx, edx\nlea eax, [r15+7]\nmov [rbp+rdx+0], cl\nmovzx ecx, [rsp+68h+var_43]\ntest cl, cl\njz short loc_14E1\ncdqe\nlea edx, [r15+8]\nmov [rbp+rax+0], cl\nmovzx ecx, [rsp+68h+var_42]\ntest cl, cl\njz short loc_1550\nmovsxd rdx, edx\nlea eax, [r15+9]\nmov [rbp+rdx+0], cl\nloc_14E1:\nadd r14, 4\ncmp r14, rbx\njz short loc_1508\nmovzx edi, cs:word_20F6\nlea r15d, [rax+2]\ncdqe\nmov [rbp+rax+0], di\njmp loc_13FD\nloc_1508:\nlea ecx, [rax+1]\ncdqe\nmov byte ptr [rbp+rax+0], 29h ; ')'\nloc_1512:\ncmp rbx, r12\njnz loc_13A0\nlea eax, [rcx+1]\nloc_151E:\nmovsxd rcx, ecx\ncdqe\nmov byte ptr [rbp+rcx+0], 5Dh ; ']'\nmov byte ptr [rbp+rax+0], 0\nmov rax, [rsp+68h+var_40]\nsub rax, fs:28h\njnz short loc_1568\nadd rsp, 38h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1550:\nmov eax, edx\njmp short loc_14E1\nloc_1558:\nadd rbx, 0Ch\njmp short loc_1512\nloc_1560:\nmov eax, r15d\njmp loc_14E1\nloc_1568:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_1330(unsigned int *a1, int a2, int a3)\n{\n int v3; // ecx\n int v4; // eax\n unsigned int *v5; // rbx\n __int64 v7; // rax\n int v8; // r15d\n unsigned int *v9; // r14\n int v10; // eax\n int v11; // edx\n char v13; // [rsp+1Eh] [rbp-4Ah] BYREF\n char v14; // [rsp+1Fh] [rbp-49h]\n char v15; // [rsp+20h] [rbp-48h]\n char v16; // [rsp+21h] [rbp-47h]\n char v17; // [rsp+22h] [rbp-46h]\n char v18; // [rsp+23h] [rbp-45h]\n char v19; // [rsp+24h] [rbp-44h]\n char v20; // [rsp+25h] [rbp-43h]\n char v21; // [rsp+26h] [rbp-42h]\n unsigned __int64 v22; // [rsp+28h] [rbp-40h]\n\n v3 = 1;\n v22 = __readfsqword(0x28u);\n byte_4040[0] = 91;\n v4 = 2;\n if ( a2 > 0 )\n {\n v5 = a1;\n v3 = 1;\n while ( (int)*v5 % a3 || (int)v5[1] % a3 || (int)v5[2] % a3 )\n {\n v5 += 3;\nLABEL_22:\n if ( v5 == &a1[3 * a2] )\n {\n v4 = v3 + 1;\n goto LABEL_24;\n }\n }\n if ( byte_4040[v3 - 1] != 91 )\n {\n v7 = v3;\n v3 += 2;\n *(_WORD *)&byte_4040[v7] = 8236;\n }\n v8 = v3 + 1;\n v9 = v5;\n byte_4040[v3] = 40;\n v5 += 3;\n while ( 1 )\n {\n __sprintf_chk(&v13, 2LL, 10LL, &unk_2004, *v9);\n if ( v13 )\n {\n v10 = v8 + 1;\n byte_4040[v8] = v13;\n if ( !v14 )\n goto LABEL_19;\n v11 = v8 + 2;\n byte_4040[v10] = v14;\n if ( !v15 )\n goto LABEL_25;\n v10 = v8 + 3;\n byte_4040[v11] = v15;\n if ( !v16 )\n goto LABEL_19;\n v11 = v8 + 4;\n byte_4040[v10] = v16;\n if ( !v17 )\n goto LABEL_25;\n v10 = v8 + 5;\n byte_4040[v11] = v17;\n if ( !v18 )\n goto LABEL_19;\n v11 = v8 + 6;\n byte_4040[v10] = v18;\n if ( !v19 )\n goto LABEL_25;\n v10 = v8 + 7;\n byte_4040[v11] = v19;\n if ( !v20 )\n goto LABEL_19;\n v11 = v8 + 8;\n byte_4040[v10] = v20;\n if ( v21 )\n {\n v10 = v8 + 9;\n byte_4040[v11] = v21;\n }\n else\n {\nLABEL_25:\n v10 = v11;\n }\n }\n else\n {\n v10 = v8;\n }\nLABEL_19:\n if ( ++v9 == v5 )\n {\n v3 = v10 + 1;\n byte_4040[v10] = 41;\n goto LABEL_22;\n }\n v8 = v10 + 2;\n *(_WORD *)&byte_4040[v10] = 8236;\n }\n }\nLABEL_24:\n byte_4040[v3] = 93;\n byte_4040[v4] = 0;\n return byte_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1330(unsigned int *a1, int a2, int a3) {\n int v3;\n int v4;\n unsigned int *v5;\n long long v7;\n int v8;\n unsigned int *v9;\n int v10;\n int v11;\n char v13;\n char v14;\n char v15;\n char v16;\n char v17;\n char v18;\n char v19;\n char v20;\n char v21;\n unsigned long long v22;\n v3 = 1;\n v22 = __readfsqword(40u);\n byte_4040[0] = 91;\n v4 = 2;\n if (a2 > 0) {\n v5 = a1;\n v3 = 1;\n while ((int)*v5 % a3 || (int)v5[1] % a3 || (int)v5[2] % a3) {\n v5 += 3;\n LABEL_22:\n if (v5 == &a1[3 * a2]) {\n v4 = v3 + 1;\n goto LABEL_24;\n }\n }\n if (byte_4040[v3 - 1] != 91) {\n v7 = v3;\n v3 += 2;\n *(unsigned short *)&byte_4040[v7] = 8236;\n }\n v8 = v3 + 1;\n v9 = v5;\n byte_4040[v3] = 40;\n v5 += 3;\n while (1) {\n __sprintf_chk(&v13, 2LL, 10LL, &unk_2004, *v9);\n if (v13) {\n v10 = v8 + 1;\n byte_4040[v8] = v13;\n if (!v14) goto LABEL_19;\n v11 = v8 + 2;\n byte_4040[v10] = v14;\n if (!v15) goto LABEL_25;\n v10 = v8 + 3;\n byte_4040[v11] = v15;\n if (!v16) goto LABEL_19;\n v11 = v8 + 4;\n byte_4040[v10] = v16;\n if (!v17) goto LABEL_25;\n v10 = v8 + 5;\n byte_4040[v11] = v17;\n if (!v18) goto LABEL_19;\n v11 = v8 + 6;\n byte_4040[v10] = v18;\n if (!v19) goto LABEL_25;\n v10 = v8 + 7;\n byte_4040[v11] = v19;\n if (!v20) goto LABEL_19;\n v11 = v8 + 8;\n byte_4040[v10] = v20;\n if (v21) {\n v10 = v8 + 9;\n byte_4040[v11] = v21;\n } else {\n LABEL_25:\n v10 = v11;\n }\n } else {\n v10 = v8;\n }\n LABEL_19:\n if (++v9 == v5) {\n v3 = v10 + 1;\n byte_4040[v10] = 41;\n goto LABEL_22;\n }\n v8 = v10 + 2;\n *(unsigned short *)&byte_4040[v10] = 8236;\n }\n }\nLABEL_24:\n byte_4040[v3] = 93;\n byte_4040[v4] = 0;\n return byte_4040;\n}", + "ida_pseudo_norm": "char *func0(unsigned int *a1, int a2, int a3) {\n int v3;\n int v4;\n unsigned int *v5;\n long long v7;\n int v8;\n unsigned int *v9;\n int v10;\n int v11;\n char v13;\n char v14;\n char v15;\n char v16;\n char v17;\n char v18;\n char v19;\n char v20;\n char v21;\n unsigned long long v22;\n v3 = 1;\n v22 = __readfsqword(40u);\n res_1[0] = 91;\n v4 = 2;\n if (a2 > 0) {\n v5 = a1;\n v3 = 1;\n while ((int)*v5 % a3 || (int)v5[1] % a3 || (int)v5[2] % a3) {\n v5 += 3;\n LABEL_22:\n if (v5 == &a1[3 * a2]) {\n v4 = v3 + 1;\n goto LABEL_24;\n }\n }\n if (res_1[v3 - 1] != 91) {\n v7 = v3;\n v3 += 2;\n *(unsigned short *)&res_1[v7] = 8236;\n }\n v8 = v3 + 1;\n v9 = v5;\n res_1[v3] = 40;\n v5 += 3;\n while (1) {\n __sprintf_chk(&v13, 2LL, 10LL, &unk_2004, *v9);\n if (v13) {\n v10 = v8 + 1;\n res_1[v8] = v13;\n if (!v14) goto LABEL_19;\n v11 = v8 + 2;\n res_1[v10] = v14;\n if (!v15) goto LABEL_25;\n v10 = v8 + 3;\n res_1[v11] = v15;\n if (!v16) goto LABEL_19;\n v11 = v8 + 4;\n res_1[v10] = v16;\n if (!v17) goto LABEL_25;\n v10 = v8 + 5;\n res_1[v11] = v17;\n if (!v18) goto LABEL_19;\n v11 = v8 + 6;\n res_1[v10] = v18;\n if (!v19) goto LABEL_25;\n v10 = v8 + 7;\n res_1[v11] = v19;\n if (!v20) goto LABEL_19;\n v11 = v8 + 8;\n res_1[v10] = v20;\n if (v21) {\n v10 = v8 + 9;\n res_1[v11] = v21;\n } else {\n LABEL_25:\n v10 = v11;\n }\n } else {\n v10 = v8;\n }\n LABEL_19:\n if (++v9 == v5) {\n v3 = v10 + 1;\n res_1[v10] = 41;\n goto LABEL_22;\n }\n v8 = v10 + 2;\n *(unsigned short *)&res_1[v10] = 8236;\n }\n }\nLABEL_24:\n res_1[v3] = 93;\n res_1[v4] = 0;\n return res_1;\n}" + }, + { + "index": 76, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int m, int n) {\n if (n < m) {\n int temp = m;\n m = n;\n n = temp;\n }\n return (int)(m * (m + 1) * (2 * m + 1) / 6 + (n - m) * m * (m + 1) / 2);\n}", + "test": "int main() {\n\n assert(func0(4, 3) == 20);\n\n assert(func0(2, 2) == 5);\n\n assert(func0(1, 1) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov -0x18(%rbp),%eax\ncmp -0x14(%rbp),%eax\njge 1171 \nmov -0x14(%rbp),%eax\nmov %eax,-0x4(%rbp)\nmov -0x18(%rbp),%eax\nmov %eax,-0x14(%rbp)\nmov -0x4(%rbp),%eax\nmov %eax,-0x18(%rbp)\nmov -0x14(%rbp),%eax\nadd $0x1,%eax\nimul -0x14(%rbp),%eax\nmov -0x14(%rbp),%edx\nadd %edx,%edx\nadd $0x1,%edx\nimul %edx,%eax\nmovslq %eax,%rdx\nimul $0x2aaaaaab,%rdx,%rdx\nshr $0x20,%rdx\nsar $0x1f,%eax\nmov %edx,%ecx\nsub %eax,%ecx\nmov -0x18(%rbp),%eax\nsub -0x14(%rbp),%eax\nimul -0x14(%rbp),%eax\nmov -0x14(%rbp),%edx\nadd $0x1,%edx\nimul %edx,%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nadd %ecx,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_14]\njge short loc_1171\nmov eax, [rbp+var_14]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_18]\nmov [rbp+var_14], eax\nmov eax, [rbp+var_4]\nmov [rbp+var_18], eax\nloc_1171:\nmov eax, [rbp+var_14]\nadd eax, 1\nimul eax, [rbp+var_14]\nmov edx, [rbp+var_14]\nadd edx, edx\nadd edx, 1\nimul eax, edx\nmovsxd rdx, eax\nimul rdx, 2AAAAAABh\nshr rdx, 20h\nsar eax, 1Fh\nmov ecx, edx\nsub ecx, eax\nmov eax, [rbp+var_18]\nsub eax, [rbp+var_14]\nimul eax, [rbp+var_14]\nmov edx, [rbp+var_14]\nadd edx, 1\nimul eax, edx\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nadd eax, ecx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n int v3; // [rsp+0h] [rbp-18h]\n int v4; // [rsp+4h] [rbp-14h]\n\n v4 = a1;\n v3 = a2;\n if ( a2 < a1 )\n {\n v4 = a2;\n v3 = a1;\n }\n return (unsigned int)((2 * v4 + 1) * v4 * (v4 + 1) / 6 + (v4 + 1) * v4 * (v3 - v4) / 2);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_14]\njge short loc_1171\nmov eax, [rbp+var_14]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_18]\nmov [rbp+var_14], eax\nmov eax, [rbp+var_4]\nmov [rbp+var_18], eax\nloc_1171:\nmov eax, [rbp+var_14]\nadd eax, 1\nimul eax, [rbp+var_14]\nmov edx, [rbp+var_14]\nadd edx, edx\nadd edx, 1\nimul eax, edx\nmovsxd rdx, eax\nimul rdx, 2AAAAAABh\nshr rdx, 20h\nsar eax, 1Fh\nmov ecx, edx\nsub ecx, eax\nmov eax, [rbp+var_18]\nsub eax, [rbp+var_14]\nimul eax, [rbp+var_14]\nmov edx, [rbp+var_14]\nadd edx, 1\nimul eax, edx\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nadd eax, ecx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2)\n{\n int v3; // [rsp+0h] [rbp-18h]\n int v4; // [rsp+4h] [rbp-14h]\n\n v4 = a1;\n v3 = a2;\n if ( a2 < a1 )\n {\n v4 = a2;\n v3 = a1;\n }\n return (unsigned int)((2 * v4 + 1) * v4 * (v4 + 1) / 6 + (v4 + 1) * v4 * (v3 - v4) / 2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2) {\n int v3;\n int v4;\n v4 = a1;\n v3 = a2;\n if (a2 < a1) {\n v4 = a2;\n v3 = a1;\n }\n return (unsigned int)((2 * v4 + 1) * v4 * (v4 + 1) / 6 +\n (v4 + 1) * v4 * (v3 - v4) / 2);\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n int v3;\n int v4;\n v4 = a1;\n v3 = a2;\n if (a2 < a1) {\n v4 = a2;\n v3 = a1;\n }\n return (unsigned int)((2 * v4 + 1) * v4 * (v4 + 1) / 6 +\n (v4 + 1) * v4 * (v3 - v4) / 2);\n}" + }, + { + "index": 76, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int m, int n) {\n if (n < m) {\n int temp = m;\n m = n;\n n = temp;\n }\n return (int)(m * (m + 1) * (2 * m + 1) / 6 + (n - m) * m * (m + 1) / 2);\n}", + "test": "int main() {\n\n assert(func0(4, 3) == 20);\n\n assert(func0(2, 2) == 5);\n\n assert(func0(1, 1) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ncmp %edi,%esi\njge 1157 \nmov %edi,%eax\nmov %esi,%edi\nmov %eax,%esi\nlea 0x1(%rdi),%ecx\nlea 0x1(%rdi,%rdi,1),%edx\nmov %ecx,%eax\nimul %edi,%eax\nimul %eax,%edx\nmovslq %edx,%rax\nimul $0x2aaaaaab,%rax,%rax\nshr $0x20,%rax\nsar $0x1f,%edx\nsub %edx,%eax\nmov %eax,%edx\nsub %edi,%esi\nimul %edi,%esi\nimul %ecx,%esi\nmov %esi,%eax\nshr $0x1f,%eax\nadd %esi,%eax\nsar %eax\nlea (%rdx,%rax,1),%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ncmp esi, edi\njl short loc_1157\nmov eax, esi\nmov esi, edi\nmov edi, eax\nloc_1157:\nlea ecx, [rsi+1]\nlea edx, [rsi+rsi+1]\nmov eax, ecx\nimul eax, esi\nimul edx, eax\nmovsxd rax, edx\nimul rax, 2AAAAAABh\nshr rax, 20h\nsar edx, 1Fh\nsub eax, edx\nsub edi, esi\nimul edi, esi\nimul edi, ecx\nmov edx, edi\nshr edx, 1Fh\nadd edx, edi\nsar edx, 1\nadd eax, edx\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n int v2; // eax\n\n if ( a2 >= a1 )\n {\n v2 = a2;\n a2 = a1;\n a1 = v2;\n }\n return (unsigned int)((a2 + 1) * a2 * (a1 - a2) / 2 + a2 * (a2 + 1) * (2 * a2 + 1) / 6);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ncmp esi, edi\njl short loc_1157\nmov eax, esi\nmov esi, edi\nmov edi, eax\nloc_1157:\nlea ecx, [rsi+1]\nlea edx, [rsi+rsi+1]\nmov eax, ecx\nimul eax, esi\nimul edx, eax\nmovsxd rax, edx\nimul rax, 2AAAAAABh\nshr rax, 20h\nsar edx, 1Fh\nsub eax, edx\nsub edi, esi\nimul edi, esi\nimul edi, ecx\nmov edx, edi\nshr edx, 1Fh\nadd edx, edi\nsar edx, 1\nadd eax, edx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2)\n{\n int v2; // eax\n\n if ( a2 >= a1 )\n {\n v2 = a2;\n a2 = a1;\n a1 = v2;\n }\n return (unsigned int)((a2 + 1) * a2 * (a1 - a2) / 2 + a2 * (a2 + 1) * (2 * a2 + 1) / 6);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2) {\n int v2;\n if (a2 >= a1) {\n v2 = a2;\n a2 = a1;\n a1 = v2;\n }\n return (unsigned int)((a2 + 1) * a2 * (a1 - a2) / 2 +\n a2 * (a2 + 1) * (2 * a2 + 1) / 6);\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n int v2;\n if (a2 >= a1) {\n v2 = a2;\n a2 = a1;\n a1 = v2;\n }\n return (unsigned int)((a2 + 1) * a2 * (a1 - a2) / 2 +\n a2 * (a2 + 1) * (2 * a2 + 1) / 6);\n}" + }, + { + "index": 76, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int m, int n) {\n if (n < m) {\n int temp = m;\n m = n;\n n = temp;\n }\n return (int)(m * (m + 1) * (2 * m + 1) / 6 + (n - m) * m * (m + 1) / 2);\n}", + "test": "int main() {\n\n assert(func0(4, 3) == 20);\n\n assert(func0(2, 2) == 5);\n\n assert(func0(1, 1) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ncmp %edi,%esi\njge 114e \nmov %edi,%eax\nmov %esi,%edi\nmov %eax,%esi\nlea 0x1(%rdi),%ecx\nlea 0x1(%rdi,%rdi,1),%edx\nsub %edi,%esi\nmov %ecx,%eax\nimul %edi,%esi\nimul %edi,%eax\nimul %ecx,%esi\nimul %eax,%edx\nmovslq %edx,%rax\nsar $0x1f,%edx\nimul $0x2aaaaaab,%rax,%rax\nshr $0x20,%rax\nsub %edx,%eax\nmov %eax,%edx\nmov %esi,%eax\nshr $0x1f,%eax\nadd %esi,%eax\nsar %eax\nlea (%rdx,%rax,1),%eax\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ncmp esi, edi\njl short loc_120E\nmov eax, esi\nmov esi, edi\nmov edi, eax\nloc_120E:\nlea ecx, [rsi+1]\nlea edx, [rsi+rsi+1]\nsub edi, esi\nmov eax, ecx\nimul edi, esi\nimul eax, esi\nimul edi, ecx\nimul edx, eax\nmovsxd rax, edx\nsar edx, 1Fh\nimul rax, 2AAAAAABh\nshr rax, 20h\nsub eax, edx\nmov edx, edi\nshr edx, 1Fh\nadd edx, edi\nsar edx, 1\nadd eax, edx\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n int v2; // eax\n\n if ( a2 >= a1 )\n {\n v2 = a2;\n a2 = a1;\n a1 = v2;\n }\n return (unsigned int)((a2 + 1) * a2 * (a1 - a2) / 2 + a2 * (a2 + 1) * (2 * a2 + 1) / 6);\n}", + "ida_strip_asm": "sub_1200:\nendbr64\ncmp esi, edi\njl short loc_120E\nmov eax, esi\nmov esi, edi\nmov edi, eax\nloc_120E:\nlea ecx, [rsi+1]\nlea edx, [rsi+rsi+1]\nsub edi, esi\nmov eax, ecx\nimul edi, esi\nimul eax, esi\nimul edi, ecx\nimul edx, eax\nmovsxd rax, edx\nsar edx, 1Fh\nimul rax, 2AAAAAABh\nshr rax, 20h\nsub eax, edx\nmov edx, edi\nshr edx, 1Fh\nadd edx, edi\nsar edx, 1\nadd eax, edx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1200(int a1, int a2)\n{\n int v2; // eax\n\n if ( a2 >= a1 )\n {\n v2 = a2;\n a2 = a1;\n a1 = v2;\n }\n return (unsigned int)((a2 + 1) * a2 * (a1 - a2) / 2 + a2 * (a2 + 1) * (2 * a2 + 1) / 6);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1200(int a1, int a2) {\n int v2;\n if (a2 >= a1) {\n v2 = a2;\n a2 = a1;\n a1 = v2;\n }\n return (unsigned int)((a2 + 1) * a2 * (a1 - a2) / 2 +\n a2 * (a2 + 1) * (2 * a2 + 1) / 6);\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n int v2;\n if (a2 >= a1) {\n v2 = a2;\n a2 = a1;\n a1 = v2;\n }\n return (unsigned int)((a2 + 1) * a2 * (a1 - a2) / 2 +\n a2 * (a2 + 1) * (2 * a2 + 1) / 6);\n}" + }, + { + "index": 77, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int n) { return (n % 11 == 0); }", + "test": "int main() {\n\n assert(func0(12345) == false);\n\n assert(func0(1212112) == true);\n\n assert(func0(1212) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov -0x4(%rbp),%ecx\nmovslq %ecx,%rax\nimul $0x2e8ba2e9,%rax,%rax\nshr $0x20,%rax\nmov %eax,%edx\nsar %edx\nmov %ecx,%eax\nsar $0x1f,%eax\nsub %eax,%edx\nmov %edx,%eax\nshl $0x2,%eax\nadd %edx,%eax\nadd %eax,%eax\nadd %edx,%eax\nsub %eax,%ecx\nmov %ecx,%edx\ntest %edx,%edx\nsete %al\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov ecx, [rbp+var_4]\nmovsxd rax, ecx\nimul rax, 2E8BA2E9h\nshr rax, 20h\nmov edx, eax\nsar edx, 1\nmov eax, ecx\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nadd eax, edx\nsub ecx, eax\nmov edx, ecx\ntest edx, edx\nsetz al\npop rbp\nretn", + "ida_pseudo": "bool __fastcall func0(int a1)\n{\n return a1 % 11 == 0;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov ecx, [rbp+var_4]\nmovsxd rax, ecx\nimul rax, 2E8BA2E9h\nshr rax, 20h\nmov edx, eax\nsar edx, 1\nmov eax, ecx\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nadd eax, edx\nsub ecx, eax\nmov edx, ecx\ntest edx, edx\nsetz al\npop rbp\nretn", + "ida_strip_pseudo": "bool __fastcall sub_1149(int a1)\n{\n return a1 % 11 == 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_1149(int a1) { return a1 % 11 == 0; }", + "ida_pseudo_norm": "bool func0(int a1) { return a1 % 11 == 0; }" + }, + { + "index": 78, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n % 2 != 0) {\n return (n + 1) / 2;\n }\n int count = 0;\n for (int i = 0; i < 32; i++) {\n count += (n >> i) & 1;\n }\n int ans = n / 2;\n if (count % 2 != 0) {\n ans += 1;\n }\n return ans;\n}", + "test": "int main() {\n\n assert(func0(5) == 3);\n\n assert(func0(10) == 5);\n\n assert(func0(15) == 8);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov -0x14(%rbp),%eax\nand $0x1,%eax\ntest %eax,%eax\nje 116f \nmov -0x14(%rbp),%eax\nadd $0x1,%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\njmp 11bb \nmovl $0x0,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 1195 \nmov -0x8(%rbp),%eax\nmov -0x14(%rbp),%edx\nmov %eax,%ecx\nsar %cl,%edx\nmov %edx,%eax\nand $0x1,%eax\nadd %eax,-0xc(%rbp)\naddl $0x1,-0x8(%rbp)\ncmpl $0x1f,-0x8(%rbp)\njle 117f \nmov -0x14(%rbp),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nmov %eax,-0x4(%rbp)\nmov -0xc(%rbp),%eax\nand $0x1,%eax\ntest %eax,%eax\nje 11b8 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov eax, [rbp+var_14]\nand eax, 1\ntest eax, eax\njz short loc_116F\nmov eax, [rbp+var_14]\nadd eax, 1\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\njmp short loc_11BB\nloc_116F:\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_1195\nloc_117F:\nmov eax, [rbp+var_8]\nmov edx, [rbp+var_14]\nmov ecx, eax\nsar edx, cl\nmov eax, edx\nand eax, 1\nadd [rbp+var_C], eax\nadd [rbp+var_8], 1\nloc_1195:\ncmp [rbp+var_8], 1Fh\njle short loc_117F\nmov eax, [rbp+var_14]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_4], eax\nmov eax, [rbp+var_C]\nand eax, 1\ntest eax, eax\njz short loc_11B8\nadd [rbp+var_4], 1\nloc_11B8:\nmov eax, [rbp+var_4]\nloc_11BB:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v2; // [rsp+8h] [rbp-Ch]\n int i; // [rsp+Ch] [rbp-8h]\n unsigned int v4; // [rsp+10h] [rbp-4h]\n\n if ( (a1 & 1) != 0 )\n return (unsigned int)((a1 + 1) / 2);\n v2 = 0;\n for ( i = 0; i <= 31; ++i )\n v2 += (a1 >> i) & 1;\n v4 = a1 / 2;\n if ( (v2 & 1) != 0 )\n ++v4;\n return v4;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov eax, [rbp+var_14]\nand eax, 1\ntest eax, eax\njz short loc_116F\nmov eax, [rbp+var_14]\nadd eax, 1\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\njmp short loc_11BB\nloc_116F:\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_1195\nloc_117F:\nmov eax, [rbp+var_8]\nmov edx, [rbp+var_14]\nmov ecx, eax\nsar edx, cl\nmov eax, edx\nand eax, 1\nadd [rbp+var_C], eax\nadd [rbp+var_8], 1\nloc_1195:\ncmp [rbp+var_8], 1Fh\njle short loc_117F\nmov eax, [rbp+var_14]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_4], eax\nmov eax, [rbp+var_C]\nand eax, 1\ntest eax, eax\njz short loc_11B8\nadd [rbp+var_4], 1\nloc_11B8:\nmov eax, [rbp+var_4]\nloc_11BB:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v2; // [rsp+8h] [rbp-Ch]\n int i; // [rsp+Ch] [rbp-8h]\n unsigned int v4; // [rsp+10h] [rbp-4h]\n\n if ( (a1 & 1) != 0 )\n return (unsigned int)((a1 + 1) / 2);\n v2 = 0;\n for ( i = 0; i <= 31; ++i )\n v2 += (a1 >> i) & 1;\n v4 = a1 / 2;\n if ( (v2 & 1) != 0 )\n ++v4;\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v2;\n int i;\n unsigned int v4;\n if ((a1 & 1) != 0) return (unsigned int)((a1 + 1) / 2);\n v2 = 0;\n for (i = 0; i <= 31; ++i) v2 += (a1 >> i) & 1;\n v4 = a1 / 2;\n if ((v2 & 1) != 0) ++v4;\n return v4;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v2;\n int i;\n unsigned int v4;\n if ((a1 & 1) != 0) return (unsigned int)((a1 + 1) / 2);\n v2 = 0;\n for (i = 0; i <= 31; ++i) v2 += (a1 >> i) & 1;\n v4 = a1 / 2;\n if ((v2 & 1) != 0) ++v4;\n return v4;\n}" + }, + { + "index": 78, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n % 2 != 0) {\n return (n + 1) / 2;\n }\n int count = 0;\n for (int i = 0; i < 32; i++) {\n count += (n >> i) & 1;\n }\n int ans = n / 2;\n if (count % 2 != 0) {\n ans += 1;\n }\n return ans;\n}", + "test": "int main() {\n\n assert(func0(5) == 3);\n\n assert(func0(10) == 5);\n\n assert(func0(15) == 8);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x0,%ecx\nmov $0x0,%edx\ntest $0x1,%dil\njne 1181 \nmov %edi,%eax\nsar %cl,%eax\nand $0x1,%eax\nadd %eax,%edx\nadd $0x1,%ecx\ncmp $0x20,%ecx\njne 115d \nmov %edi,%eax\nshr $0x1f,%eax\nadd %edi,%eax\nsar %eax\nand $0x1,%edx\ncmp $0x1,%edx\nsbb $0xffffffff,%eax\nretq\nadd $0x1,%edi\nmov %edi,%eax\nshr $0x1f,%eax\nadd %edi,%eax\nsar %eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov edx, edi\nand edx, 1\nmov ecx, edx\njnz short loc_117A\nloc_1156:\nmov eax, edi\nsar eax, cl\nand eax, 1\nadd edx, eax\nadd ecx, 1\ncmp ecx, 20h ; ' '\njnz short loc_1156\nmov eax, edi\nshr eax, 1Fh\nadd eax, edi\nsar eax, 1\nand edx, 1\ncmp edx, 1\nsbb eax, 0FFFFFFFFh\nretn\nloc_117A:\nadd edi, 1\nmov eax, edi\nshr eax, 1Fh\nadd eax, edi\nsar eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // edx\n int v2; // ecx\n\n v1 = a1 & 1;\n v2 = v1;\n if ( (a1 & 1) != 0 )\n return (unsigned int)((a1 + 1) / 2);\n do\n v1 += (a1 >> v2++) & 1;\n while ( v2 != 32 );\n return a1 / 2 - ((unsigned int)((v1 & 1) == 0) - 1);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmov edx, edi\nand edx, 1\nmov ecx, edx\njnz short loc_117A\nloc_1156:\nmov eax, edi\nsar eax, cl\nand eax, 1\nadd edx, eax\nadd ecx, 1\ncmp ecx, 20h ; ' '\njnz short loc_1156\nmov eax, edi\nshr eax, 1Fh\nadd eax, edi\nsar eax, 1\nand edx, 1\ncmp edx, 1\nsbb eax, 0FFFFFFFFh\nretn\nloc_117A:\nadd edi, 1\nmov eax, edi\nshr eax, 1Fh\nadd eax, edi\nsar eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v1; // edx\n int v2; // ecx\n\n v1 = a1 & 1;\n v2 = v1;\n if ( (a1 & 1) != 0 )\n return (unsigned int)((a1 + 1) / 2);\n do\n v1 += (a1 >> v2++) & 1;\n while ( v2 != 32 );\n return a1 / 2 - ((unsigned int)((v1 & 1) == 0) - 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v1;\n int v2;\n v1 = a1 & 1;\n v2 = v1;\n if ((a1 & 1) != 0) return (unsigned int)((a1 + 1) / 2);\n do\n v1 += (a1 >> v2++) & 1;\n while (v2 != 32);\n return a1 / 2 - ((unsigned int)((v1 & 1) == 0) - 1);\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v2;\n v1 = a1 & 1;\n v2 = v1;\n if ((a1 & 1) != 0) return (unsigned int)((a1 + 1) / 2);\n do\n v1 += (a1 >> v2++) & 1;\n while (v2 != 32);\n return a1 / 2 - ((unsigned int)((v1 & 1) == 0) - 1);\n}" + }, + { + "index": 79, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char *s) {\n char *token = strtok(s, \" \");\n while (token != NULL) {\n if (strlen(token) % 2 != 0) {\n return 1;\n } else {\n return 0;\n }\n token = strtok(NULL, \" \");\n }\n return 0;\n}", + "test": "int main() {\n\n assert(func0(\"Hadoop\") == 0);\n\n assert(func0(\"great\") == 1);\n\n assert(func0(\"structure\") == 1);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov -0x18(%rbp),%rax\nlea 0xe64(%rip),%rsi\nmov %rax,%rdi\ncallq 1090 \nmov %rax,-0x8(%rbp)\ncmpq $0x0,-0x8(%rbp)\nje 11d9 \nmov -0x8(%rbp),%rax\nmov %rax,%rdi\ncallq 1070 \nand $0x1,%eax\ntest %rax,%rax\nje 11d2 \nmov $0x1,%eax\njmp 11de \nmov $0x0,%eax\njmp 11de \nmov $0x0,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nlea rdx, delim; \" \"\nmov rsi, rdx; delim\nmov rdi, rax; s\ncall _strtok\nmov [rbp+var_8], rax\nnop\ncmp [rbp+var_8], 0\njz short loc_11DD\nmov rax, [rbp+var_8]\nmov rdi, rax; s\ncall _strlen\nand eax, 1\ntest rax, rax\njz short loc_11D6\nmov eax, 1\njmp short locret_11E2\nloc_11D6:\nmov eax, 0\njmp short locret_11E2\nloc_11DD:\nmov eax, 0\nlocret_11E2:\nleave\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(char *a1)\n{\n const char *v2; // [rsp+18h] [rbp-8h]\n\n v2 = strtok(a1, \" \");\n return v2 && (strlen(v2) & 1) != 0;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nlea rdx, delim; \" \"\nmov rsi, rdx; delim\nmov rdi, rax; s\ncall _strtok\nmov [rbp+var_8], rax\nnop\ncmp [rbp+var_8], 0\njz short loc_11DD\nmov rax, [rbp+var_8]\nmov rdi, rax; s\ncall _strlen\nand eax, 1\ntest rax, rax\njz short loc_11D6\nmov eax, 1\njmp short locret_11E2\nloc_11D6:\nmov eax, 0\njmp short locret_11E2\nloc_11DD:\nmov eax, 0\nlocret_11E2:\nleave\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1189(char *a1)\n{\n const char *v2; // [rsp+18h] [rbp-8h]\n\n v2 = strtok(a1, \" \");\n return v2 && (strlen(v2) & 1) != 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1189(char *a1) {\n const char *v2;\n v2 = strtok(a1, \" \");\n return v2 && (strlen(v2) & 1) != 0;\n}", + "ida_pseudo_norm": "uint8_t func0(char *a1) {\n const char *v2;\n v2 = strtok(a1, \" \");\n return v2 && (strlen(v2) & 1) != 0;\n}" + }, + { + "index": 79, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char *s) {\n char *token = strtok(s, \" \");\n while (token != NULL) {\n if (strlen(token) % 2 != 0) {\n return 1;\n } else {\n return 0;\n }\n token = strtok(NULL, \" \");\n }\n return 0;\n}", + "test": "int main() {\n\n assert(func0(\"Hadoop\") == 0);\n\n assert(func0(\"great\") == 1);\n\n assert(func0(\"structure\") == 1);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x8,%rsp\nlea 0xe8c(%rip),%rsi\ncallq 1070 \nmov %rax,%rdi\nmov $0x0,%eax\ntest %rdi,%rdi\nje 1198 \nmov $0xffffffffffffffff,%rcx\nrepnz scas %es:(%rdi),%al\nmov %ecx,%eax\nand $0x1,%eax\nadd $0x8,%rsp\nretq\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\nlea rsi, delim; \" \"\ncall _strtok\nmov rdi, rax; s\nmov eax, 0\ntest rdi, rdi\njz short loc_11B2\ncall _strlen\nand eax, 1\nloc_11B2:\nadd rsp, 8\nretn", + "ida_pseudo": "size_t __fastcall func0(char *a1)\n{\n char *v1; // rdi\n size_t result; // rax\n\n v1 = strtok(a1, \" \");\n result = 0LL;\n if ( v1 )\n return strlen(v1) & 1;\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\nsub rsp, 8\nlea rsi, delim; \" \"\ncall _strtok\nmov rdi, rax; s\nmov eax, 0\ntest rdi, rdi\njz short loc_11B2\ncall _strlen\nand eax, 1\nloc_11B2:\nadd rsp, 8\nretn", + "ida_strip_pseudo": "size_t __fastcall sub_1189(char *a1)\n{\n char *v1; // rdi\n size_t result; // rax\n\n v1 = strtok(a1, \" \");\n result = 0LL;\n if ( v1 )\n return strlen(v1) & 1;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned int sub_1189(char *a1) {\n char *v1;\n unsigned int result;\n v1 = strtok(a1, \" \");\n result = 0LL;\n if (v1) return strlen(v1) & 1;\n return result;\n}", + "ida_pseudo_norm": "unsigned int func0(char *a1) {\n char *v1;\n unsigned int result;\n v1 = strtok(a1, \" \");\n result = 0LL;\n if (v1) return strlen(v1) & 1;\n return result;\n}" + }, + { + "index": 79, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char *s) {\n char *token = strtok(s, \" \");\n while (token != NULL) {\n if (strlen(token) % 2 != 0) {\n return 1;\n } else {\n return 0;\n }\n token = strtok(NULL, \" \");\n }\n return 0;\n}", + "test": "int main() {\n\n assert(func0(\"Hadoop\") == 0);\n\n assert(func0(\"great\") == 1);\n\n assert(func0(\"structure\") == 1);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x8,%rsp\nlea 0xdc5(%rip),%rsi\ncallq 1090 \nmov %rax,%rdi\nxor %eax,%eax\ntest %rdi,%rdi\nje 1256 \ncallq 1070 \nand $0x1,%eax\nadd $0x8,%rsp\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\nlea rsi, delim; \" \"\ncall _strtok\nmov rdi, rax; s\nxor eax, eax\ntest rdi, rdi\njz short loc_1256\ncall _strlen\nand eax, 1\nloc_1256:\nadd rsp, 8\nretn", + "ida_pseudo": "size_t __fastcall func0(char *a1)\n{\n char *v1; // rdi\n size_t result; // rax\n\n v1 = strtok(a1, \" \");\n result = 0LL;\n if ( v1 )\n return strlen(v1) & 1;\n return result;\n}", + "ida_strip_asm": "sub_1230:\nendbr64\nsub rsp, 8\nlea rsi, delim; \" \"\ncall _strtok\nmov rdi, rax; s\nxor eax, eax\ntest rdi, rdi\njz short loc_1256\ncall _strlen\nand eax, 1\nloc_1256:\nadd rsp, 8\nretn", + "ida_strip_pseudo": "size_t __fastcall sub_1230(char *a1)\n{\n char *v1; // rdi\n size_t result; // rax\n\n v1 = strtok(a1, \" \");\n result = 0LL;\n if ( v1 )\n return strlen(v1) & 1;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned int sub_1230(char *a1) {\n char *v1;\n unsigned int result;\n v1 = strtok(a1, \" \");\n result = 0LL;\n if (v1) return strlen(v1) & 1;\n return result;\n}", + "ida_pseudo_norm": "unsigned int func0(char *a1) {\n char *v1;\n unsigned int result;\n v1 = strtok(a1, \" \");\n result = 0LL;\n if (v1) return strlen(v1) & 1;\n return result;\n}" + }, + { + "index": 79, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char *s) {\n char *token = strtok(s, \" \");\n while (token != NULL) {\n if (strlen(token) % 2 != 0) {\n return 1;\n } else {\n return 0;\n }\n token = strtok(NULL, \" \");\n }\n return 0;\n}", + "test": "int main() {\n\n assert(func0(\"Hadoop\") == 0);\n\n assert(func0(\"great\") == 1);\n\n assert(func0(\"structure\") == 1);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x8,%rsp\nlea 0xdc5(%rip),%rsi\ncallq 1090 \nmov %rax,%rdi\nxor %eax,%eax\ntest %rdi,%rdi\nje 1256 \ncallq 1070 \nand $0x1,%eax\nadd $0x8,%rsp\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\nlea rsi, delim; \" \"\ncall _strtok\nmov rdi, rax; s\nxor eax, eax\ntest rdi, rdi\njz short loc_1256\ncall _strlen\nand eax, 1\nloc_1256:\nadd rsp, 8\nretn", + "ida_pseudo": "size_t __fastcall func0(char *a1)\n{\n char *v1; // rdi\n size_t result; // rax\n\n v1 = strtok(a1, \" \");\n result = 0LL;\n if ( v1 )\n return strlen(v1) & 1;\n return result;\n}", + "ida_strip_asm": "sub_1230:\nendbr64\nsub rsp, 8\nlea rsi, delim; \" \"\ncall _strtok\nmov rdi, rax; s\nxor eax, eax\ntest rdi, rdi\njz short loc_1256\ncall _strlen\nand eax, 1\nloc_1256:\nadd rsp, 8\nretn", + "ida_strip_pseudo": "size_t __fastcall sub_1230(char *a1)\n{\n char *v1; // rdi\n size_t result; // rax\n\n v1 = strtok(a1, \" \");\n result = 0LL;\n if ( v1 )\n return strlen(v1) & 1;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned int sub_1230(char *a1) {\n char *v1;\n unsigned int result;\n v1 = strtok(a1, \" \");\n result = 0LL;\n if (v1) return strlen(v1) & 1;\n return result;\n}", + "ida_pseudo_norm": "unsigned int func0(char *a1) {\n char *v1;\n unsigned int result;\n v1 = strtok(a1, \" \");\n result = 0LL;\n if (v1) return strlen(v1) & 1;\n return result;\n}" + }, + { + "index": 80, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "double func0(int n) { return (n * (n + 1) * (n + 2)) / 6.0; }", + "test": "int main() {\n\n assert(func0(5) == 35.0);\n\n assert(func0(6) == 56.0);\n\n assert(func0(7) == 84.0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nadd $0x1,%eax\nimul -0x4(%rbp),%eax\nmov -0x4(%rbp),%edx\nadd $0x2,%edx\nimul %edx,%eax\ncvtsi2sd %eax,%xmm0\nmovsd 0xf0d(%rip),%xmm1\ndivsd %xmm1,%xmm0\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov eax, [rbp+var_4]\nadd eax, 1\nimul eax, [rbp+var_4]\nmov edx, [rbp+var_4]\nadd edx, 2\nimul eax, edx\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmovsd xmm1, cs:qword_2060\ndivsd xmm0, xmm1\npop rbp\nretn", + "ida_pseudo": "double __fastcall func0(int a1)\n{\n return (double)((a1 + 2) * a1 * (a1 + 1)) / 6.0;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov eax, [rbp+var_4]\nadd eax, 1\nimul eax, [rbp+var_4]\nmov edx, [rbp+var_4]\nadd edx, 2\nimul eax, edx\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmovsd xmm1, cs:qword_2060\ndivsd xmm0, xmm1\npop rbp\nretn", + "ida_strip_pseudo": "double __fastcall sub_1149(int a1)\n{\n return (double)((a1 + 2) * a1 * (a1 + 1)) / 6.0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1149(int a1) { return (double)((a1 + 2) * a1 * (a1 + 1)) / 6.0; }", + "ida_pseudo_norm": "double func0(int a1) { return (double)((a1 + 2) * a1 * (a1 + 1)) / 6.0; }" + }, + { + "index": 81, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n} Pair;\n\n\n\n", + "func": "Pair *func0(int *test_tup1, int len1, int *test_tup2, int len2) {\n Pair *res = (Pair *)malloc(sizeof(Pair) * len1);\n for (int i = 0; i < len1; i++) {\n res[i].first = test_tup1[i];\n res[i].second = test_tup2[i % len2];\n }\n return res;\n}", + "test": "int main() {\n\n int test_tup1_1[] = {7, 8, 4, 5, 9, 10};\n\n int test_tup2_1[] = {1, 5, 6};\n\n Pair *result1 = func0(test_tup1_1, 6, test_tup2_1, 3);\n\n Pair expected1[] = {{7, 1}, {8, 5}, {4, 6}, {5, 1}, {9, 5}, {10, 6}};\n\n for (int i = 0; i < 6; i++) {\n\n assert(result1[i].first == expected1[i].first && result1[i].second == expected1[i].second);\n\n }\n\n\n\n int test_tup1_2[] = {8, 9, 5, 6, 10, 11};\n\n int test_tup2_2[] = {2, 6, 7};\n\n Pair *result2 = func0(test_tup1_2, 6, test_tup2_2, 3);\n\n Pair expected2[] = {{8, 2}, {9, 6}, {5, 7}, {6, 2}, {10, 6}, {11, 7}};\n\n for (int i = 0; i < 6; i++) {\n\n assert(result2[i].first == expected2[i].first && result2[i].second == expected2[i].second);\n\n }\n\n\n\n int test_tup1_3[] = {9, 10, 6, 7, 11, 12};\n\n int test_tup2_3[] = {3, 7, 8};\n\n Pair *result3 = func0(test_tup1_3, 6, test_tup2_3, 3);\n\n Pair expected3[] = {{9, 3}, {10, 7}, {6, 8}, {7, 3}, {11, 7}, {12, 8}};\n\n for (int i = 0; i < 6; i++) {\n\n assert(result3[i].first == expected3[i].first && result3[i].second == expected3[i].second);\n\n }\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n \n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %ecx,-0x20(%rbp)\nmov -0x1c(%rbp),%eax\ncltq\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 1246 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0xc(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\nmov -0xc(%rbp),%eax\ncltd\nidivl -0x20(%rbp)\nmov %edx,%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov -0xc(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,0x4(%rdx)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11e1 \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp short loc_1246\nloc_11E1:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_C]\ncdq\nidiv [rbp+var_20]\nmov eax, edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx+4], eax\nadd [rbp+var_C], 1\nloc_1246:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_11E1\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, __int64 a3, int a4)\n{\n int i; // [rsp+24h] [rbp-Ch]\n _DWORD *v8; // [rsp+28h] [rbp-8h]\n\n v8 = malloc(8LL * a2);\n for ( i = 0; i < a2; ++i )\n {\n v8[2 * i] = *(_DWORD *)(4LL * i + a1);\n v8[2 * i + 1] = *(_DWORD *)(4LL * (i % a4) + a3);\n }\n return v8;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp short loc_1246\nloc_11E1:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_C]\ncdq\nidiv [rbp+var_20]\nmov eax, edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx+4], eax\nadd [rbp+var_C], 1\nloc_1246:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_11E1\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(__int64 a1, int a2, __int64 a3, int a4)\n{\n int i; // [rsp+24h] [rbp-Ch]\n _DWORD *v8; // [rsp+28h] [rbp-8h]\n\n v8 = malloc(8LL * a2);\n for ( i = 0; i < a2; ++i )\n {\n v8[2 * i] = *(_DWORD *)(4LL * i + a1);\n v8[2 * i + 1] = *(_DWORD *)(4LL * (i % a4) + a3);\n }\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(long long a1, int a2, long long a3, int a4) {\n int i;\n uint32_t *v8;\n v8 = malloc(8LL * a2);\n for (i = 0; i < a2; ++i) {\n v8[2 * i] = *(uint32_t *)(4LL * i + a1);\n v8[2 * i + 1] = *(uint32_t *)(4LL * (i % a4) + a3);\n }\n return v8;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, long long a3, int a4) {\n int i;\n uint32_t *v8;\n v8 = malloc(8LL * a2);\n for (i = 0; i < a2; ++i) {\n v8[2 * i] = *(uint32_t *)(4LL * i + a1);\n v8[2 * i + 1] = *(uint32_t *)(4LL * (i % a4) + a3);\n }\n return v8;\n}" + }, + { + "index": 81, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n} Pair;\n\n\n\n", + "func": "Pair *func0(int *test_tup1, int len1, int *test_tup2, int len2) {\n Pair *res = (Pair *)malloc(sizeof(Pair) * len1);\n for (int i = 0; i < len1; i++) {\n res[i].first = test_tup1[i];\n res[i].second = test_tup2[i % len2];\n }\n return res;\n}", + "test": "int main() {\n\n int test_tup1_1[] = {7, 8, 4, 5, 9, 10};\n\n int test_tup2_1[] = {1, 5, 6};\n\n Pair *result1 = func0(test_tup1_1, 6, test_tup2_1, 3);\n\n Pair expected1[] = {{7, 1}, {8, 5}, {4, 6}, {5, 1}, {9, 5}, {10, 6}};\n\n for (int i = 0; i < 6; i++) {\n\n assert(result1[i].first == expected1[i].first && result1[i].second == expected1[i].second);\n\n }\n\n\n\n int test_tup1_2[] = {8, 9, 5, 6, 10, 11};\n\n int test_tup2_2[] = {2, 6, 7};\n\n Pair *result2 = func0(test_tup1_2, 6, test_tup2_2, 3);\n\n Pair expected2[] = {{8, 2}, {9, 6}, {5, 7}, {6, 2}, {10, 6}, {11, 7}};\n\n for (int i = 0; i < 6; i++) {\n\n assert(result2[i].first == expected2[i].first && result2[i].second == expected2[i].second);\n\n }\n\n\n\n int test_tup1_3[] = {9, 10, 6, 7, 11, 12};\n\n int test_tup2_3[] = {3, 7, 8};\n\n Pair *result3 = func0(test_tup1_3, 6, test_tup2_3, 3);\n\n Pair expected3[] = {{9, 3}, {10, 7}, {6, 8}, {7, 3}, {11, 7}, {12, 8}};\n\n for (int i = 0; i < 6; i++) {\n\n assert(result3[i].first == expected3[i].first && result3[i].second == expected3[i].second);\n\n }\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n \n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbp\nmov %esi,%r13d\nmov %rdx,%r12\nmov %ecx,%ebx\nmovslq %esi,%rdi\nshl $0x3,%rdi\ncallq 10b0 \nmov %rax,%rsi\ntest %r13d,%r13d\njle 1202 \nlea -0x1(%r13),%edi\nmov $0x0,%ecx\nmov 0x0(%rbp,%rcx,4),%eax\nmov %eax,(%rsi,%rcx,8)\nmov %ecx,%eax\ncltd\nidiv %ebx\nmovslq %edx,%rdx\nmov (%r12,%rdx,4),%eax\nmov %eax,0x4(%rsi,%rcx,8)\nmov %rcx,%rax\nadd $0x1,%rcx\ncmp %rdi,%rax\njne 11df \nmov %rsi,%rax\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbp, rdi\nmov r14d, esi\nmov r12, rdx\nmov ebx, ecx\nmovsxd r13, esi\nlea rdi, ds:0[r13*8]; size\ncall _malloc\nmov rsi, rax\ntest r14d, r14d\njle short loc_11FD\nmov ecx, 0\nloc_11DD:\nmov eax, [rbp+rcx*4+0]\nmov [rsi+rcx*8], eax\nmov eax, ecx\ncdq\nidiv ebx\nmovsxd rdx, edx\nmov eax, [r12+rdx*4]\nmov [rsi+rcx*8+4], eax\nadd rcx, 1\ncmp r13, rcx\njnz short loc_11DD\nloc_11FD:\nmov rax, rsi\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, __int64 a3, int a4)\n{\n __int64 v7; // r13\n _DWORD *v8; // rsi\n __int64 v9; // rcx\n\n v7 = a2;\n v8 = malloc(8LL * a2);\n if ( a2 > 0 )\n {\n v9 = 0LL;\n do\n {\n v8[2 * v9] = *(_DWORD *)(a1 + 4 * v9);\n v8[2 * v9 + 1] = *(_DWORD *)(a3 + 4LL * ((int)v9 % a4));\n ++v9;\n }\n while ( v7 != v9 );\n }\n return v8;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbp, rdi\nmov r14d, esi\nmov r12, rdx\nmov ebx, ecx\nmovsxd r13, esi\nlea rdi, ds:0[r13*8]; size\ncall _malloc\nmov rsi, rax\ntest r14d, r14d\njle short loc_11FD\nmov ecx, 0\nloc_11DD:\nmov eax, [rbp+rcx*4+0]\nmov [rsi+rcx*8], eax\nmov eax, ecx\ncdq\nidiv ebx\nmovsxd rdx, edx\nmov eax, [r12+rdx*4]\nmov [rsi+rcx*8+4], eax\nadd rcx, 1\ncmp r13, rcx\njnz short loc_11DD\nloc_11FD:\nmov rax, rsi\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(__int64 a1, int a2, __int64 a3, int a4)\n{\n __int64 v7; // r13\n _DWORD *v8; // rsi\n __int64 v9; // rcx\n\n v7 = a2;\n v8 = malloc(8LL * a2);\n if ( a2 > 0 )\n {\n v9 = 0LL;\n do\n {\n v8[2 * v9] = *(_DWORD *)(a1 + 4 * v9);\n v8[2 * v9 + 1] = *(_DWORD *)(a3 + 4LL * ((int)v9 % a4));\n ++v9;\n }\n while ( v7 != v9 );\n }\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(long long a1, int a2, long long a3, int a4) {\n long long v7;\n uint32_t *v8;\n long long v9;\n v7 = a2;\n v8 = malloc(8LL * a2);\n if (a2 > 0) {\n v9 = 0LL;\n do {\n v8[2 * v9] = *(uint32_t *)(a1 + 4 * v9);\n v8[2 * v9 + 1] = *(uint32_t *)(a3 + 4LL * ((int)v9 % a4));\n ++v9;\n } while (v7 != v9);\n }\n return v8;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, long long a3, int a4) {\n long long v7;\n uint32_t *v8;\n long long v9;\n v7 = a2;\n v8 = malloc(8LL * a2);\n if (a2 > 0) {\n v9 = 0LL;\n do {\n v8[2 * v9] = *(uint32_t *)(a1 + 4 * v9);\n v8[2 * v9 + 1] = *(uint32_t *)(a3 + 4LL * ((int)v9 % a4));\n ++v9;\n } while (v7 != v9);\n }\n return v8;\n}" + }, + { + "index": 81, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n} Pair;\n\n\n\n", + "func": "Pair *func0(int *test_tup1, int len1, int *test_tup2, int len2) {\n Pair *res = (Pair *)malloc(sizeof(Pair) * len1);\n for (int i = 0; i < len1; i++) {\n res[i].first = test_tup1[i];\n res[i].second = test_tup2[i % len2];\n }\n return res;\n}", + "test": "int main() {\n\n int test_tup1_1[] = {7, 8, 4, 5, 9, 10};\n\n int test_tup2_1[] = {1, 5, 6};\n\n Pair *result1 = func0(test_tup1_1, 6, test_tup2_1, 3);\n\n Pair expected1[] = {{7, 1}, {8, 5}, {4, 6}, {5, 1}, {9, 5}, {10, 6}};\n\n for (int i = 0; i < 6; i++) {\n\n assert(result1[i].first == expected1[i].first && result1[i].second == expected1[i].second);\n\n }\n\n\n\n int test_tup1_2[] = {8, 9, 5, 6, 10, 11};\n\n int test_tup2_2[] = {2, 6, 7};\n\n Pair *result2 = func0(test_tup1_2, 6, test_tup2_2, 3);\n\n Pair expected2[] = {{8, 2}, {9, 6}, {5, 7}, {6, 2}, {10, 6}, {11, 7}};\n\n for (int i = 0; i < 6; i++) {\n\n assert(result2[i].first == expected2[i].first && result2[i].second == expected2[i].second);\n\n }\n\n\n\n int test_tup1_3[] = {9, 10, 6, 7, 11, 12};\n\n int test_tup2_3[] = {3, 7, 8};\n\n Pair *result3 = func0(test_tup1_3, 6, test_tup2_3, 3);\n\n Pair expected3[] = {{9, 3}, {10, 7}, {6, 8}, {7, 3}, {11, 7}, {12, 8}};\n\n for (int i = 0; i < 6; i++) {\n\n assert(result3[i].first == expected3[i].first && result3[i].second == expected3[i].second);\n\n }\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n \n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\nmov %rdx,%r12\npush %rbp\nmov %rdi,%rbp\nmovslq %esi,%rdi\npush %rbx\nmov %rdi,%r13\nshl $0x3,%rdi\nmov %ecx,%ebx\nsub $0x8,%rsp\ncallq 10b0 \nmov %rax,%r8\ntest %r13d,%r13d\njle 15dd \nlea -0x1(%r13),%ecx\nxor %esi,%esi\nnopl 0x0(%rax,%rax,1)\nmov 0x0(%rbp,%rsi,4),%eax\nmov %eax,(%r8,%rsi,8)\nmov %esi,%eax\ncltd\nidiv %ebx\nmovslq %edx,%rdx\nmov (%r12,%rdx,4),%eax\nmov %eax,0x4(%r8,%rsi,8)\nmov %rsi,%rax\nadd $0x1,%rsi\ncmp %rax,%rcx\njne 15b8 \nadd $0x8,%rsp\nmov %r8,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\nmovsxd r13, esi\npush r12\nmov r12, rdx\npush rbp\nmov rbp, rdi\nlea rdi, ds:0[r13*8]; size\npush rbx\nmov ebx, ecx\ncall _malloc\nmov rdi, rax\ntest r13d, r13d\njle short loc_14D6\nxor ecx, ecx\nxchg ax, ax\nloc_14B0:\nmov eax, ecx\nmovd xmm0, dword ptr [rbp+rcx*4+0]\ncdq\nidiv ebx\nmovsxd rdx, edx\nmovd xmm1, dword ptr [r12+rdx*4]\npunpckldq xmm0, xmm1\nmovq qword ptr [rdi+rcx*8], xmm0\nadd rcx, 1\ncmp r13, rcx\njnz short loc_14B0\nloc_14D6:\npop rbx\nmov rax, rdi\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, int a2, __int64 a3, int a4)\n{\n _QWORD *v7; // rdi\n __int64 v8; // rcx\n\n v7 = malloc(8LL * a2);\n if ( a2 > 0 )\n {\n v8 = 0LL;\n do\n {\n v7[v8] = _mm_unpacklo_epi32(\n _mm_cvtsi32_si128(*(_DWORD *)(a1 + 4 * v8)),\n _mm_cvtsi32_si128(*(_DWORD *)(a3 + 4LL * ((int)v8 % a4)))).m128i_u64[0];\n ++v8;\n }\n while ( a2 != v8 );\n }\n return v7;\n}", + "ida_strip_asm": "sub_1480:\nendbr64\npush r14\npush r13\nmovsxd r13, esi\npush r12\nmov r12, rdx\npush rbp\nmov rbp, rdi\nlea rdi, ds:0[r13*8]; size\npush rbx\nmov ebx, ecx\ncall _malloc\nmov rdi, rax\ntest r13d, r13d\njle short loc_14D6\nxor ecx, ecx\nxchg ax, ax\nloc_14B0:\nmov eax, ecx\nmovd xmm0, dword ptr [rbp+rcx*4+0]\ncdq\nidiv ebx\nmovsxd rdx, edx\nmovd xmm1, dword ptr [r12+rdx*4]\npunpckldq xmm0, xmm1\nmovq qword ptr [rdi+rcx*8], xmm0\nadd rcx, 1\ncmp r13, rcx\njnz short loc_14B0\nloc_14D6:\npop rbx\nmov rax, rdi\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1480(__int64 a1, int a2, __int64 a3, int a4)\n{\n _QWORD *v7; // rdi\n __int64 v8; // rcx\n\n v7 = malloc(8LL * a2);\n if ( a2 > 0 )\n {\n v8 = 0LL;\n do\n {\n v7[v8] = _mm_unpacklo_epi32(\n _mm_cvtsi32_si128(*(_DWORD *)(a1 + 4 * v8)),\n _mm_cvtsi32_si128(*(_DWORD *)(a3 + 4LL * ((int)v8 % a4)))).m128i_u64[0];\n ++v8;\n }\n while ( a2 != v8 );\n }\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1480(long long a1, int a2, long long a3, int a4) {\n uint64_t *v7;\n long long v8;\n v7 = malloc(8LL * a2);\n if (a2 > 0) {\n v8 = 0LL;\n do {\n v7[v8] = _mm_unpacklo_epi32(\n _mm_cvtsi32_si128(*(uint32_t *)(a1 + 4 * v8)),\n _mm_cvtsi32_si128(*(uint32_t *)(a3 + 4LL * ((int)v8 % a4))))\n .m128i_u64[0];\n ++v8;\n } while (a2 != v8);\n }\n return v7;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, int a2, long long a3, int a4) {\n uint64_t *v7;\n long long v8;\n v7 = malloc(8LL * a2);\n if (a2 > 0) {\n v8 = 0LL;\n do {\n v7[v8] = _mm_unpacklo_epi32(\n _mm_cvtsi32_si128(*(uint32_t *)(a1 + 4 * v8)),\n _mm_cvtsi32_si128(*(uint32_t *)(a3 + 4LL * ((int)v8 % a4))))\n .m128i_u64[0];\n ++v8;\n } while (a2 != v8);\n }\n return v7;\n}" + }, + { + "index": 81, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n} Pair;\n\n\n\n", + "func": "Pair *func0(int *test_tup1, int len1, int *test_tup2, int len2) {\n Pair *res = (Pair *)malloc(sizeof(Pair) * len1);\n for (int i = 0; i < len1; i++) {\n res[i].first = test_tup1[i];\n res[i].second = test_tup2[i % len2];\n }\n return res;\n}", + "test": "int main() {\n\n int test_tup1_1[] = {7, 8, 4, 5, 9, 10};\n\n int test_tup2_1[] = {1, 5, 6};\n\n Pair *result1 = func0(test_tup1_1, 6, test_tup2_1, 3);\n\n Pair expected1[] = {{7, 1}, {8, 5}, {4, 6}, {5, 1}, {9, 5}, {10, 6}};\n\n for (int i = 0; i < 6; i++) {\n\n assert(result1[i].first == expected1[i].first && result1[i].second == expected1[i].second);\n\n }\n\n\n\n int test_tup1_2[] = {8, 9, 5, 6, 10, 11};\n\n int test_tup2_2[] = {2, 6, 7};\n\n Pair *result2 = func0(test_tup1_2, 6, test_tup2_2, 3);\n\n Pair expected2[] = {{8, 2}, {9, 6}, {5, 7}, {6, 2}, {10, 6}, {11, 7}};\n\n for (int i = 0; i < 6; i++) {\n\n assert(result2[i].first == expected2[i].first && result2[i].second == expected2[i].second);\n\n }\n\n\n\n int test_tup1_3[] = {9, 10, 6, 7, 11, 12};\n\n int test_tup2_3[] = {3, 7, 8};\n\n Pair *result3 = func0(test_tup1_3, 6, test_tup2_3, 3);\n\n Pair expected3[] = {{9, 3}, {10, 7}, {6, 8}, {7, 3}, {11, 7}, {12, 8}};\n\n for (int i = 0; i < 6; i++) {\n\n assert(result3[i].first == expected3[i].first && result3[i].second == expected3[i].second);\n\n }\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n \n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\nmov %rdi,%r12\nmovslq %esi,%rdi\npush %rbp\nmov %rdi,%r13\nshl $0x3,%rdi\nmov %rdx,%rbp\npush %rbx\nmov %ecx,%ebx\nsub $0x8,%rsp\ncallq 10b0 \nmov %rax,%r8\ntest %r13d,%r13d\njle 171d \nlea -0x1(%r13),%ecx\ncmp $0x2,%ecx\njbe 172b \nmov %r13d,%edi\nmov %r12,%rdx\nshr $0x2,%edi\nshl $0x4,%rdi\nadd %r12,%rdi\nxchg %ax,%ax\nmovdqu (%rdx),%xmm0\nadd $0x10,%rdx\nadd $0x20,%rax\npshufd $0x55,%xmm0,%xmm1\nmovd %xmm0,-0x20(%rax)\nmovd %xmm1,-0x18(%rax)\nmovdqa %xmm0,%xmm1\npunpckhdq %xmm0,%xmm1\npshufd $0xff,%xmm0,%xmm0\nmovd %xmm1,-0x10(%rax)\nmovd %xmm0,-0x8(%rax)\ncmp %rdi,%rdx\njne 1680 \nmov %r13d,%eax\nand $0xfffffffc,%eax\ntest $0x3,%r13b\nje 16f3 \nmovslq %eax,%rdx\nmov (%r12,%rdx,4),%esi\nmov %esi,(%r8,%rdx,8)\nlea 0x1(%rax),%edx\ncmp %edx,%r13d\njle 16f3 \nmovslq %edx,%rdx\nadd $0x2,%eax\nmov (%r12,%rdx,4),%esi\nmov %esi,(%r8,%rdx,8)\ncmp %eax,%r13d\njle 16f3 \ncltq\nmov (%r12,%rax,4),%edx\nmov %edx,(%r8,%rax,8)\nmov %ecx,%ecx\nxor %esi,%esi\nnopw 0x0(%rax,%rax,1)\nmov %esi,%eax\ncltd\nidiv %ebx\nmovslq %edx,%rdx\nmov 0x0(%rbp,%rdx,4),%eax\nmov %eax,0x4(%r8,%rsi,8)\nmov %rsi,%rax\nadd $0x1,%rsi\ncmp %rcx,%rax\njne 1700 \nadd $0x8,%rsp\nmov %r8,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nxor %eax,%eax\njmp 16c3 \n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\nmov r13, rdi\npush r12\nmovsxd r12, esi\npush rbp\nlea rdi, ds:0[r12*8]; size\nmov rbp, rdx\npush rbx\nmov ebx, ecx\ncall _malloc\nmov rsi, rax\ntest r12d, r12d\njle loc_1589\nlea eax, [r12-1]\nmov r14, r12\ncmp eax, 2\njbe loc_1595\nmov ecx, r12d\nmov rax, r13\nmov rdx, rsi\nshr ecx, 2\nshl rcx, 4\nadd rcx, r13\nnop dword ptr [rax+00h]\nloc_14F8:\nmov edi, [rax+0Ch]\nmov r8d, [rax+8]\nadd rax, 10h\nadd rdx, 20h ; ' '\nmov r9d, [rax-0Ch]\nmov r10d, [rax-10h]\nmov [rdx-10h], r8d\nmov [rdx-20h], r10d\nmov [rdx-18h], r9d\nmov [rdx-8], edi\ncmp rax, rcx\njnz short loc_14F8\nmov eax, r14d\nand eax, 0FFFFFFFCh\ntest r14b, 3\njz short loc_156D\nloc_152F:\nmovsxd rdx, eax\nmov r8d, [r13+rdx*4+0]\nlea rdi, ds:0[rdx*4]\nlea rcx, ds:0[rdx*8]\nmov [rsi+rdx*8], r8d\nlea edx, [rax+1]\ncmp r14d, edx\njle short loc_156D\nmov edx, [r13+rdi+4]\nadd eax, 2\nmov [rsi+rcx+8], edx\ncmp eax, r14d\njge short loc_156D\nmov eax, [r13+rdi+8]\nmov [rsi+rcx+10h], eax\nloc_156D:\nxor ecx, ecx\nnop\nloc_1570:\nmov eax, ecx\ncdq\nidiv ebx\nmovsxd rdx, edx\nmov eax, [rbp+rdx*4+0]\nmov [rsi+rcx*8+4], eax\nadd rcx, 1\ncmp r12, rcx\njnz short loc_1570\nloc_1589:\npop rbx\nmov rax, rsi\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1595:\nxor eax, eax\njmp short loc_152F", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, __int64 a3, int a4)\n{\n __int64 v5; // r12\n _DWORD *v8; // rsi\n __int64 v9; // rax\n _DWORD *v10; // rdx\n int v11; // edi\n int v12; // r8d\n int v13; // r9d\n int v14; // r10d\n int v15; // eax\n __int64 v16; // rdi\n __int64 v17; // rcx\n __int64 i; // rcx\n\n v5 = a2;\n v8 = malloc(8LL * a2);\n if ( (int)v5 > 0 )\n {\n if ( (unsigned int)(v5 - 1) <= 2 )\n {\n v15 = 0;\n }\n else\n {\n v9 = a1;\n v10 = v8;\n do\n {\n v11 = *(_DWORD *)(v9 + 12);\n v12 = *(_DWORD *)(v9 + 8);\n v9 += 16LL;\n v10 += 8;\n v13 = *(_DWORD *)(v9 - 12);\n v14 = *(_DWORD *)(v9 - 16);\n *(v10 - 4) = v12;\n *(v10 - 8) = v14;\n *(v10 - 6) = v13;\n *(v10 - 2) = v11;\n }\n while ( v9 != a1 + 16LL * ((unsigned int)v5 >> 2) );\n v15 = v5 & 0x7FFFFFFC;\n if ( (v5 & 3) == 0 )\n {\nLABEL_9:\n for ( i = 0LL; i != v5; ++i )\n v8[2 * i + 1] = *(_DWORD *)(a3 + 4LL * ((int)i % a4));\n return v8;\n }\n }\n v16 = 4LL * v15;\n v17 = 2LL * v15;\n v8[v17] = *(_DWORD *)(a1 + v16);\n if ( (int)v5 > v15 + 1 )\n {\n v8[v17 + 2] = *(_DWORD *)(a1 + v16 + 4);\n if ( v15 + 2 < (int)v5 )\n v8[v17 + 4] = *(_DWORD *)(a1 + v16 + 8);\n }\n goto LABEL_9;\n }\n return v8;\n}", + "ida_strip_asm": "sub_14A0:\nendbr64\npush r14\npush r13\nmov r13, rdi\npush r12\nmovsxd r12, esi\npush rbp\nlea rdi, ds:0[r12*8]; size\nmov rbp, rdx\npush rbx\nmov ebx, ecx\ncall _malloc\nmov rsi, rax\ntest r12d, r12d\njle loc_1589\nlea eax, [r12-1]\nmov r14, r12\ncmp eax, 2\njbe loc_1595\nmov ecx, r12d\nmov rax, r13\nmov rdx, rsi\nshr ecx, 2\nshl rcx, 4\nadd rcx, r13\nnop dword ptr [rax+00h]\nloc_14F8:\nmov edi, [rax+0Ch]\nmov r8d, [rax+8]\nadd rax, 10h\nadd rdx, 20h ; ' '\nmov r9d, [rax-0Ch]\nmov r10d, [rax-10h]\nmov [rdx-10h], r8d\nmov [rdx-20h], r10d\nmov [rdx-18h], r9d\nmov [rdx-8], edi\ncmp rax, rcx\njnz short loc_14F8\nmov eax, r14d\nand eax, 0FFFFFFFCh\ntest r14b, 3\njz short loc_156D\nloc_152F:\nmovsxd rdx, eax\nmov r8d, [r13+rdx*4+0]\nlea rdi, ds:0[rdx*4]\nlea rcx, ds:0[rdx*8]\nmov [rsi+rdx*8], r8d\nlea edx, [rax+1]\ncmp r14d, edx\njle short loc_156D\nmov edx, [r13+rdi+4]\nadd eax, 2\nmov [rsi+rcx+8], edx\ncmp eax, r14d\njge short loc_156D\nmov eax, [r13+rdi+8]\nmov [rsi+rcx+10h], eax\nloc_156D:\nxor ecx, ecx\nnop\nloc_1570:\nmov eax, ecx\ncdq\nidiv ebx\nmovsxd rdx, edx\nmov eax, [rbp+rdx*4+0]\nmov [rsi+rcx*8+4], eax\nadd rcx, 1\ncmp r12, rcx\njnz short loc_1570\nloc_1589:\npop rbx\nmov rax, rsi\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1595:\nxor eax, eax\njmp short loc_152F", + "ida_strip_pseudo": "_DWORD *__fastcall sub_14A0(__int64 a1, int a2, __int64 a3, int a4)\n{\n __int64 v5; // r12\n _DWORD *v8; // rsi\n __int64 v9; // rax\n _DWORD *v10; // rdx\n int v11; // edi\n int v12; // r8d\n int v13; // r9d\n int v14; // r10d\n int v15; // eax\n __int64 v16; // rdi\n __int64 v17; // rcx\n __int64 i; // rcx\n\n v5 = a2;\n v8 = malloc(8LL * a2);\n if ( (int)v5 > 0 )\n {\n if ( (unsigned int)(v5 - 1) <= 2 )\n {\n v15 = 0;\n }\n else\n {\n v9 = a1;\n v10 = v8;\n do\n {\n v11 = *(_DWORD *)(v9 + 12);\n v12 = *(_DWORD *)(v9 + 8);\n v9 += 16LL;\n v10 += 8;\n v13 = *(_DWORD *)(v9 - 12);\n v14 = *(_DWORD *)(v9 - 16);\n *(v10 - 4) = v12;\n *(v10 - 8) = v14;\n *(v10 - 6) = v13;\n *(v10 - 2) = v11;\n }\n while ( v9 != a1 + 16LL * ((unsigned int)v5 >> 2) );\n v15 = v5 & 0x7FFFFFFC;\n if ( (v5 & 3) == 0 )\n {\nLABEL_9:\n for ( i = 0LL; i != v5; ++i )\n v8[2 * i + 1] = *(_DWORD *)(a3 + 4LL * ((int)i % a4));\n return v8;\n }\n }\n v16 = 4LL * v15;\n v17 = 2LL * v15;\n v8[v17] = *(_DWORD *)(a1 + v16);\n if ( (int)v5 > v15 + 1 )\n {\n v8[v17 + 2] = *(_DWORD *)(a1 + v16 + 4);\n if ( v15 + 2 < (int)v5 )\n v8[v17 + 4] = *(_DWORD *)(a1 + v16 + 8);\n }\n goto LABEL_9;\n }\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_14A0(long long a1, int a2, long long a3, int a4) {\n long long v5;\n uint32_t *v8;\n long long v9;\n uint32_t *v10;\n int v11;\n int v12;\n int v13;\n int v14;\n int v15;\n long long v16;\n long long v17;\n long long i;\n v5 = a2;\n v8 = malloc(8LL * a2);\n if ((int)v5 > 0) {\n if ((unsigned int)(v5 - 1) <= 2) {\n v15 = 0;\n } else {\n v9 = a1;\n v10 = v8;\n do {\n v11 = *(uint32_t *)(v9 + 12);\n v12 = *(uint32_t *)(v9 + 8);\n v9 += 16LL;\n v10 += 8;\n v13 = *(uint32_t *)(v9 - 12);\n v14 = *(uint32_t *)(v9 - 16);\n *(v10 - 4) = v12;\n *(v10 - 8) = v14;\n *(v10 - 6) = v13;\n *(v10 - 2) = v11;\n } while (v9 != a1 + 16LL * ((unsigned int)v5 >> 2));\n v15 = v5 & 2147483644;\n if ((v5 & 3) == 0) {\n LABEL_9:\n for (i = 0LL; i != v5; ++i)\n v8[2 * i + 1] = *(uint32_t *)(a3 + 4LL * ((int)i % a4));\n return v8;\n }\n }\n v16 = 4LL * v15;\n v17 = 2LL * v15;\n v8[v17] = *(uint32_t *)(a1 + v16);\n if ((int)v5 > v15 + 1) {\n v8[v17 + 2] = *(uint32_t *)(a1 + v16 + 4);\n if (v15 + 2 < (int)v5) v8[v17 + 4] = *(uint32_t *)(a1 + v16 + 8);\n }\n goto LABEL_9;\n }\n return v8;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, long long a3, int a4) {\n long long v5;\n uint32_t *v8;\n long long v9;\n uint32_t *v10;\n int v11;\n int v12;\n int v13;\n int v14;\n int v15;\n long long v16;\n long long v17;\n long long i;\n v5 = a2;\n v8 = malloc(8LL * a2);\n if ((int)v5 > 0) {\n if ((unsigned int)(v5 - 1) <= 2) {\n v15 = 0;\n } else {\n v9 = a1;\n v10 = v8;\n do {\n v11 = *(uint32_t *)(v9 + 12);\n v12 = *(uint32_t *)(v9 + 8);\n v9 += 16LL;\n v10 += 8;\n v13 = *(uint32_t *)(v9 - 12);\n v14 = *(uint32_t *)(v9 - 16);\n *(v10 - 4) = v12;\n *(v10 - 8) = v14;\n *(v10 - 6) = v13;\n *(v10 - 2) = v11;\n } while (v9 != a1 + 16LL * ((unsigned int)v5 >> 2));\n v15 = v5 & 2147483644;\n if ((v5 & 3) == 0) {\n LABEL_9:\n for (i = 0LL; i != v5; ++i)\n v8[2 * i + 1] = *(uint32_t *)(a3 + 4LL * ((int)i % a4));\n return v8;\n }\n }\n v16 = 4LL * v15;\n v17 = 2LL * v15;\n v8[v17] = *(uint32_t *)(a1 + v16);\n if ((int)v5 > v15 + 1) {\n v8[v17 + 2] = *(uint32_t *)(a1 + v16 + 4);\n if (v15 + 2 < (int)v5) v8[v17 + 4] = *(uint32_t *)(a1 + v16 + 8);\n }\n goto LABEL_9;\n }\n return v8;\n}" + }, + { + "index": 82, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(double r) {\n double volume = (4.0 / 3.0) * M_PI * r * r * r;\n return volume;\n}", + "test": "int main() {\n\n assert(func0(10) == 4188.790204786391);\n\n assert(func0(25) == 65449.84694978735);\n\n assert(func0(20) == 33510.32163829113);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmovsd %xmm0,-0x18(%rbp)\nmovsd -0x18(%rbp),%xmm1\nmovsd 0xf4d(%rip),%xmm0\nmulsd %xmm1,%xmm0\nmulsd -0x18(%rbp),%xmm0\nmovsd -0x18(%rbp),%xmm1\nmulsd %xmm1,%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmovsd -0x8(%rbp),%xmm0\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmovsd [rbp+var_18], xmm0\nmovsd xmm1, [rbp+var_18]\nmovsd xmm0, cs:qword_2090\nmulsd xmm0, xmm1\nmulsd xmm0, [rbp+var_18]\nmovsd xmm1, [rbp+var_18]\nmulsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "double __fastcall func0(double a1)\n{\n return 4.188790204786391 * a1 * a1 * a1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmovsd [rbp+var_18], xmm0\nmovsd xmm1, [rbp+var_18]\nmovsd xmm0, cs:qword_2090\nmulsd xmm0, xmm1\nmulsd xmm0, [rbp+var_18]\nmovsd xmm1, [rbp+var_18]\nmulsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "double __fastcall sub_1149(double a1)\n{\n return 4.188790204786391 * a1 * a1 * a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1149(double a1) { return 4.188790204786391 * a1 * a1 * a1; }", + "ida_pseudo_norm": "double func0(double a1) { return 4.188790204786391 * a1 * a1 * a1; }" + }, + { + "index": 83, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char *strr) {\n int summ = 0;\n for (int i = 0; strr[i] != '\\0'; i++) {\n summ += (strr[i] - 'a' + 1);\n }\n if (summ % 26 == 0) {\n return 'z';\n } else {\n summ = summ % 26;\n return ('a' + summ - 1);\n }\n}", + "test": "int main() {\n\n assert(func0(\"abc\") == 'f');\n\n assert(func0(\"gfg\") == 't');\n\n assert(func0(\"ab\") == 'c');\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 1182 \nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmovsbl %al,%eax\nsub $0x60,%eax\nadd %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 1165 \nmov -0x8(%rbp),%edx\nmovslq %edx,%rax\nimul $0x4ec4ec4f,%rax,%rax\nshr $0x20,%rax\nmov %eax,%ecx\nsar $0x3,%ecx\nmov %edx,%eax\nsar $0x1f,%eax\nsub %eax,%ecx\nmov %ecx,%eax\nimul $0x1a,%eax,%eax\nsub %eax,%edx\nmov %edx,%eax\ntest %eax,%eax\njne 11c7 \nmov $0x7a,%eax\njmp 11f0 \nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nimul $0x4ec4ec4f,%rdx,%rdx\nshr $0x20,%rdx\nmov %edx,%ecx\nsar $0x3,%ecx\ncltd\nsub %edx,%ecx\nmov %ecx,%edx\nimul $0x1a,%edx,%edx\nsub %edx,%eax\nmov %eax,-0x8(%rbp)\nmov -0x8(%rbp),%eax\nadd $0x60,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_1182\nloc_1165:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nsub eax, 60h ; '`'\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_1182:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1165\nmov edx, [rbp+var_8]\nmovsxd rax, edx\nimul rax, 4EC4EC4Fh\nshr rax, 20h\nsar eax, 3\nmov ecx, edx\nsar ecx, 1Fh\nsub eax, ecx\nimul ecx, eax, 1Ah\nmov eax, edx\nsub eax, ecx\ntest eax, eax\njnz short loc_11C3\nmov eax, 7Ah ; 'z'\njmp short loc_11EA\nloc_11C3:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nimul rdx, 4EC4EC4Fh\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 3\ncdq\nsub ecx, edx\nimul edx, ecx, 1Ah\nsub eax, edx\nmov [rbp+var_8], eax\nmov eax, [rbp+var_8]\nadd eax, 60h ; '`'\nloc_11EA:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1)\n{\n int v2; // [rsp+10h] [rbp-8h]\n int i; // [rsp+14h] [rbp-4h]\n\n v2 = 0;\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n v2 += *(char *)(i + a1) - 96;\n if ( v2 % 26 )\n return (unsigned int)(v2 % 26 + 96);\n else\n return 122LL;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_1182\nloc_1165:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nsub eax, 60h ; '`'\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_1182:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1165\nmov edx, [rbp+var_8]\nmovsxd rax, edx\nimul rax, 4EC4EC4Fh\nshr rax, 20h\nsar eax, 3\nmov ecx, edx\nsar ecx, 1Fh\nsub eax, ecx\nimul ecx, eax, 1Ah\nmov eax, edx\nsub eax, ecx\ntest eax, eax\njnz short loc_11C3\nmov eax, 7Ah ; 'z'\njmp short loc_11EA\nloc_11C3:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nimul rdx, 4EC4EC4Fh\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 3\ncdq\nsub ecx, edx\nimul edx, ecx, 1Ah\nsub eax, edx\nmov [rbp+var_8], eax\nmov eax, [rbp+var_8]\nadd eax, 60h ; '`'\nloc_11EA:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(__int64 a1)\n{\n int v2; // [rsp+10h] [rbp-8h]\n int i; // [rsp+14h] [rbp-4h]\n\n v2 = 0;\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n v2 += *(char *)(i + a1) - 96;\n if ( v2 % 26 )\n return (unsigned int)(v2 % 26 + 96);\n else\n return 122LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(long long a1) {\n int v2;\n int i;\n v2 = 0;\n for (i = 0; *(uint8_t *)(i + a1); ++i) v2 += *(char *)(i + a1) - 96;\n if (v2 % 26)\n return (unsigned int)(v2 % 26 + 96);\n else\n return 122LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1) {\n int v2;\n int i;\n v2 = 0;\n for (i = 0; *(uint8_t *)(i + a1); ++i) v2 += *(char *)(i + a1) - 96;\n if (v2 % 26)\n return (unsigned int)(v2 % 26 + 96);\n else\n return 122LL;\n}" + }, + { + "index": 83, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char *strr) {\n int summ = 0;\n for (int i = 0; strr[i] != '\\0'; i++) {\n summ += (strr[i] - 'a' + 1);\n }\n if (summ % 26 == 0) {\n return 'z';\n } else {\n summ = summ % 26;\n return ('a' + summ - 1);\n }\n}", + "test": "int main() {\n\n assert(func0(\"abc\") == 'f');\n\n assert(func0(\"gfg\") == 't');\n\n assert(func0(\"ab\") == 'c');\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmovzbl (%rdi),%eax\ntest %al,%al\nje 1196 \nadd $0x1,%rdi\nmov $0x0,%edx\nmovsbl %al,%eax\nlea -0x60(%rdx,%rax,1),%edx\nadd $0x1,%rdi\nmovzbl -0x1(%rdi),%eax\ntest %al,%al\njne 115d \nmovslq %edx,%rcx\nimul $0x4ec4ec4f,%rcx,%rcx\nsar $0x23,%rcx\nmov %edx,%eax\nsar $0x1f,%eax\nsub %eax,%ecx\nimul $0x1a,%ecx,%ecx\nsub %ecx,%edx\nlea 0x60(%rdx),%eax\nmov $0x7a,%edx\ncmove %edx,%eax\nretq\nmov $0x7a,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmovzx eax, byte ptr [rdi]\ntest al, al\njz short loc_1198\nadd rdi, 1\nmov edx, 0\nloc_115D:\nmovsx eax, al\nlea edx, [rdx+rax-60h]\nadd rdi, 1\nmovzx eax, byte ptr [rdi-1]\ntest al, al\njnz short loc_115D\nmovsxd rcx, edx\nimul rcx, 4EC4EC4Fh\nsar rcx, 23h\nmov eax, edx\nsar eax, 1Fh\nsub ecx, eax\nimul eax, ecx, 1Ah\nmov ecx, edx\nsub ecx, eax\nlea eax, [rcx+60h]\nmov edx, 7Ah ; 'z'\ncmovz eax, edx\nretn\nloc_1198:\nmov eax, 7Ah ; 'z'\nretn", + "ida_pseudo": "__int64 __fastcall func0(char *a1)\n{\n char v1; // al\n char *v2; // rdi\n int v3; // edx\n __int64 result; // rax\n\n v1 = *a1;\n if ( !*a1 )\n return 122LL;\n v2 = a1 + 1;\n v3 = 0;\n do\n {\n v3 = v3 + v1 - 96;\n v1 = *v2++;\n }\n while ( v1 );\n result = (unsigned int)(v3 % 26 + 96);\n if ( !(v3 % 26) )\n return 122LL;\n return result;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmovzx eax, byte ptr [rdi]\ntest al, al\njz short loc_1198\nadd rdi, 1\nmov edx, 0\nloc_115D:\nmovsx eax, al\nlea edx, [rdx+rax-60h]\nadd rdi, 1\nmovzx eax, byte ptr [rdi-1]\ntest al, al\njnz short loc_115D\nmovsxd rcx, edx\nimul rcx, 4EC4EC4Fh\nsar rcx, 23h\nmov eax, edx\nsar eax, 1Fh\nsub ecx, eax\nimul eax, ecx, 1Ah\nmov ecx, edx\nsub ecx, eax\nlea eax, [rcx+60h]\nmov edx, 7Ah ; 'z'\ncmovz eax, edx\nretn\nloc_1198:\nmov eax, 7Ah ; 'z'\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(char *a1)\n{\n char v1; // al\n char *v2; // rdi\n int v3; // edx\n __int64 result; // rax\n\n v1 = *a1;\n if ( !*a1 )\n return 122LL;\n v2 = a1 + 1;\n v3 = 0;\n do\n {\n v3 = v3 + v1 - 96;\n v1 = *v2++;\n }\n while ( v1 );\n result = (unsigned int)(v3 % 26 + 96);\n if ( !(v3 % 26) )\n return 122LL;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(char *a1) {\n char v1;\n char *v2;\n int v3;\n long long result;\n v1 = *a1;\n if (!*a1) return 122LL;\n v2 = a1 + 1;\n v3 = 0;\n do {\n v3 = v3 + v1 - 96;\n v1 = *v2++;\n } while (v1);\n result = (unsigned int)(v3 % 26 + 96);\n if (!(v3 % 26)) return 122LL;\n return result;\n}", + "ida_pseudo_norm": "long long func0(char *a1) {\n char v1;\n char *v2;\n int v3;\n long long result;\n v1 = *a1;\n if (!*a1) return 122LL;\n v2 = a1 + 1;\n v3 = 0;\n do {\n v3 = v3 + v1 - 96;\n v1 = *v2++;\n } while (v1);\n result = (unsigned int)(v3 % 26 + 96);\n if (!(v3 % 26)) return 122LL;\n return result;\n}" + }, + { + "index": 83, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char *strr) {\n int summ = 0;\n for (int i = 0; strr[i] != '\\0'; i++) {\n summ += (strr[i] - 'a' + 1);\n }\n if (summ % 26 == 0) {\n return 'z';\n } else {\n summ = summ % 26;\n return ('a' + summ - 1);\n }\n}", + "test": "int main() {\n\n assert(func0(\"abc\") == 'f');\n\n assert(func0(\"gfg\") == 't');\n\n assert(func0(\"ab\") == 'c');\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmovsbl (%rdi),%eax\ntest %al,%al\nje 12b0 \nadd $0x1,%rdi\nxor %edx,%edx\nnopl 0x0(%rax)\nadd $0x1,%rdi\nlea -0x60(%rdx,%rax,1),%edx\nmovsbl -0x1(%rdi),%eax\ntest %al,%al\njne 1278 \nmovslq %edx,%rcx\nmov %edx,%eax\nimul $0x4ec4ec4f,%rcx,%rcx\nsar $0x1f,%eax\nsar $0x23,%rcx\nsub %eax,%ecx\nimul $0x1a,%ecx,%ecx\nsub %ecx,%edx\nlea 0x60(%rdx),%eax\nmov $0x7a,%edx\ncmove %edx,%eax\nretq\nxchg %ax,%ax\nmov $0x7a,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmovsx eax, byte ptr [rdi]\ntest al, al\njz short loc_1240\nadd rdi, 1\nxor edx, edx\nnop dword ptr [rax+00000000h]\nloc_1208:\nadd rdi, 1\nlea edx, [rdx+rax-60h]\nmovsx eax, byte ptr [rdi-1]\ntest al, al\njnz short loc_1208\nmovsxd rcx, edx\nmov eax, edx\nimul rcx, 4EC4EC4Fh\nsar eax, 1Fh\nsar rcx, 23h\nsub ecx, eax\nimul eax, ecx, 1Ah\nmov ecx, edx\nmov edx, 7Ah ; 'z'\nsub ecx, eax\nlea eax, [rcx+60h]\ncmovz eax, edx\nretn\nloc_1240:\nmov eax, 7Ah ; 'z'\nretn", + "ida_pseudo": "__int64 __fastcall func0(_BYTE *a1)\n{\n int v1; // eax\n _BYTE *v2; // rdi\n int v3; // edx\n __int64 result; // rax\n\n v1 = (char)*a1;\n if ( !*a1 )\n return 122LL;\n v2 = a1 + 1;\n v3 = 0;\n do\n {\n ++v2;\n v3 = v3 + v1 - 96;\n v1 = (char)*(v2 - 1);\n }\n while ( *(v2 - 1) );\n result = (unsigned int)(v3 % 26 + 96);\n if ( !(v3 % 26) )\n return 122LL;\n return result;\n}", + "ida_strip_asm": "sub_11F0:\nendbr64\nmovsx eax, byte ptr [rdi]\ntest al, al\njz short loc_1240\nadd rdi, 1\nxor edx, edx\nnop dword ptr [rax+00000000h]\nloc_1208:\nadd rdi, 1\nlea edx, [rdx+rax-60h]\nmovsx eax, byte ptr [rdi-1]\ntest al, al\njnz short loc_1208\nmovsxd rcx, edx\nmov eax, edx\nimul rcx, 4EC4EC4Fh\nsar eax, 1Fh\nsar rcx, 23h\nsub ecx, eax\nimul eax, ecx, 1Ah\nmov ecx, edx\nmov edx, 7Ah ; 'z'\nsub ecx, eax\nlea eax, [rcx+60h]\ncmovz eax, edx\nretn\nloc_1240:\nmov eax, 7Ah ; 'z'\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11F0(_BYTE *a1)\n{\n int v1; // eax\n _BYTE *v2; // rdi\n int v3; // edx\n __int64 result; // rax\n\n v1 = (char)*a1;\n if ( !*a1 )\n return 122LL;\n v2 = a1 + 1;\n v3 = 0;\n do\n {\n ++v2;\n v3 = v3 + v1 - 96;\n v1 = (char)*(v2 - 1);\n }\n while ( *(v2 - 1) );\n result = (unsigned int)(v3 % 26 + 96);\n if ( !(v3 % 26) )\n return 122LL;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11F0(uint8_t *a1) {\n int v1;\n uint8_t *v2;\n int v3;\n long long result;\n v1 = (char)*a1;\n if (!*a1) return 122LL;\n v2 = a1 + 1;\n v3 = 0;\n do {\n ++v2;\n v3 = v3 + v1 - 96;\n v1 = (char)*(v2 - 1);\n } while (*(v2 - 1));\n result = (unsigned int)(v3 % 26 + 96);\n if (!(v3 % 26)) return 122LL;\n return result;\n}", + "ida_pseudo_norm": "long long func0(uint8_t *a1) {\n int v1;\n uint8_t *v2;\n int v3;\n long long result;\n v1 = (char)*a1;\n if (!*a1) return 122LL;\n v2 = a1 + 1;\n v3 = 0;\n do {\n ++v2;\n v3 = v3 + v1 - 96;\n v1 = (char)*(v2 - 1);\n } while (*(v2 - 1));\n result = (unsigned int)(v3 % 26 + 96);\n if (!(v3 % 26)) return 122LL;\n return result;\n}" + }, + { + "index": 84, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n == 1 || n == 2) {\n return 1;\n } else {\n return func0(func0(n - 1)) + func0(n - func0(n - 1));\n }\n}", + "test": "int main() {\n\n assert(func0(10) == 6);\n\n assert(func0(2) == 1);\n\n assert(func0(3) == 2);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x18,%rsp\nmov %edi,-0x14(%rbp)\ncmpl $0x1,-0x14(%rbp)\nje 1165 \ncmpl $0x2,-0x14(%rbp)\njne 116c \nmov $0x1,%eax\njmp 119f \nmov -0x14(%rbp),%eax\nsub $0x1,%eax\nmov %eax,%edi\ncallq 1149 \nmov %eax,%edi\ncallq 1149 \nmov %eax,%ebx\nmov -0x14(%rbp),%eax\nsub $0x1,%eax\nmov %eax,%edi\ncallq 1149 \nmov -0x14(%rbp),%edx\nsub %eax,%edx\nmov %edx,%eax\nmov %eax,%edi\ncallq 1149 \nadd %ebx,%eax\nadd $0x18,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 18h\nmov [rbp+var_14], edi\ncmp [rbp+var_14], 1\njz short loc_1165\ncmp [rbp+var_14], 2\njnz short loc_116C\nloc_1165:\nmov eax, 1\njmp short loc_119D\nloc_116C:\nmov eax, [rbp+var_14]\nsub eax, 1\nmov edi, eax\ncall func0\nmov edi, eax\ncall func0\nmov ebx, eax\nmov eax, [rbp+var_14]\nsub eax, 1\nmov edi, eax\ncall func0\nmov edx, [rbp+var_14]\nsub edx, eax\nmov edi, edx\ncall func0\nadd eax, ebx\nloc_119D:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v2; // eax\n int v3; // ebx\n int v4; // eax\n\n if ( a1 == 1 || a1 == 2 )\n return 1LL;\n v2 = func0((unsigned int)(a1 - 1));\n v3 = func0(v2);\n v4 = func0((unsigned int)(a1 - 1));\n return v3 + (unsigned int)func0((unsigned int)(a1 - v4));\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 18h\nmov [rbp+var_14], edi\ncmp [rbp+var_14], 1\njz short loc_1165\ncmp [rbp+var_14], 2\njnz short loc_116C\nloc_1165:\nmov eax, 1\njmp short loc_119D\nloc_116C:\nmov eax, [rbp+var_14]\nsub eax, 1\nmov edi, eax\ncall sub_1149\nmov edi, eax\ncall sub_1149\nmov ebx, eax\nmov eax, [rbp+var_14]\nsub eax, 1\nmov edi, eax\ncall sub_1149\nmov edx, [rbp+var_14]\nsub edx, eax\nmov edi, edx\ncall sub_1149\nadd eax, ebx\nloc_119D:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n unsigned int v2; // eax\n int v3; // ebx\n int v4; // eax\n\n if ( a1 == 1 || a1 == 2 )\n return 1LL;\n v2 = sub_1149((unsigned int)(a1 - 1));\n v3 = sub_1149(v2);\n v4 = sub_1149((unsigned int)(a1 - 1));\n return v3 + (unsigned int)sub_1149((unsigned int)(a1 - v4));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n unsigned int v2;\n int v3;\n int v4;\n if (a1 == 1 || a1 == 2) return 1LL;\n v2 = sub_1149((unsigned int)(a1 - 1));\n v3 = sub_1149(v2);\n v4 = sub_1149((unsigned int)(a1 - 1));\n return v3 + (unsigned int)sub_1149((unsigned int)(a1 - v4));\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v2;\n int v3;\n int v4;\n if (a1 == 1 || a1 == 2) return 1LL;\n v2 = func0((unsigned int)(a1 - 1));\n v3 = func0(v2);\n v4 = func0((unsigned int)(a1 - 1));\n return v3 + (unsigned int)func0((unsigned int)(a1 - v4));\n}" + }, + { + "index": 84, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n == 1 || n == 2) {\n return 1;\n } else {\n return func0(func0(n - 1)) + func0(n - func0(n - 1));\n }\n}", + "test": "int main() {\n\n assert(func0(10) == 6);\n\n assert(func0(2) == 1);\n\n assert(func0(3) == 2);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nlea -0x1(%rdi),%edx\nmov $0x1,%eax\ncmp $0x1,%edx\nja 115b \nretq\npush %r12\npush %rbp\npush %rbx\nmov %edi,%ebx\nmov %edx,%edi\ncallq 1149 \nmov %eax,%r12d\nmov %eax,%edi\ncallq 1149 \nmov %eax,%ebp\nsub %r12d,%ebx\nmov %ebx,%edi\ncallq 1149 \nadd %ebp,%eax\npop %rbx\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\nlea edx, [rdi-1]\nmov eax, 1\ncmp edx, 1\nja short loc_115B\nretn\nloc_115B:\npush r12\npush rbp\npush rbx\nmov ebx, edi\nmov edi, edx\ncall func0\nmov r12d, eax\nmov edi, eax\ncall func0\nmov ebp, eax\nsub ebx, r12d\nmov edi, ebx\ncall func0\nadd eax, ebp\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n __int64 result; // rax\n __int64 v2; // r12\n int v3; // ebp\n\n result = 1LL;\n if ( (unsigned int)(a1 - 1) > 1 )\n {\n v2 = (unsigned int)func0((unsigned int)(a1 - 1));\n v3 = func0(v2);\n return v3 + (unsigned int)func0((unsigned int)(a1 - v2));\n }\n return result;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nlea edx, [rdi-1]\nmov eax, 1\ncmp edx, 1\nja short loc_115B\nretn\nloc_115B:\npush r12\npush rbp\npush rbx\nmov ebx, edi\nmov edi, edx\ncall sub_1149\nmov r12d, eax\nmov edi, eax\ncall sub_1149\nmov ebp, eax\nsub ebx, r12d\nmov edi, ebx\ncall sub_1149\nadd eax, ebp\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n __int64 result; // rax\n __int64 v2; // r12\n int v3; // ebp\n\n result = 1LL;\n if ( (unsigned int)(a1 - 1) > 1 )\n {\n v2 = (unsigned int)sub_1149((unsigned int)(a1 - 1));\n v3 = sub_1149(v2);\n return v3 + (unsigned int)sub_1149((unsigned int)(a1 - v2));\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n long long result;\n long long v2;\n int v3;\n result = 1LL;\n if ((unsigned int)(a1 - 1) > 1) {\n v2 = (unsigned int)sub_1149((unsigned int)(a1 - 1));\n v3 = sub_1149(v2);\n return v3 + (unsigned int)sub_1149((unsigned int)(a1 - v2));\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n long long result;\n long long v2;\n int v3;\n result = 1LL;\n if ((unsigned int)(a1 - 1) > 1) {\n v2 = (unsigned int)func0((unsigned int)(a1 - 1));\n v3 = func0(v2);\n return v3 + (unsigned int)func0((unsigned int)(a1 - v2));\n }\n return result;\n}" + }, + { + "index": 84, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n == 1 || n == 2) {\n return 1;\n } else {\n return func0(func0(n - 1)) + func0(n - func0(n - 1));\n }\n}", + "test": "int main() {\n\n assert(func0(10) == 6);\n\n assert(func0(2) == 1);\n\n assert(func0(3) == 2);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov $0x1,%eax\npush %rbp\nmov %edi,%ebp\nsub $0x1,%edi\npush %rbx\ncmp $0x1,%edi\njbe 122a \nxor %r12d,%r12d\ncallq 11f0 \nmov %eax,%ebx\nmov %eax,%edi\ncallq 11f0 \nsub %ebx,%ebp\nlea -0x1(%rbp),%edi\nadd %eax,%r12d\ncmp $0x1,%edi\nja 120a \nlea 0x1(%r12),%eax\npop %rbx\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov eax, 1\npush r14\npush r13\npush r12\nlea r12d, [rdi-1]\npush rbp\npush rbx\nsub rsp, 38h\ncmp r12d, 1\njbe loc_19DC\nxor ebp, ebp\nmov [rsp+68h+var_44], edi\nmov r14d, r12d\nmov [rsp+68h+var_3C], ebp\nloc_1222:\nmov eax, [rsp+68h+var_44]\nmov [rsp+68h+var_50], r14d\ncmp eax, 3\njz loc_1B63\nmov [rsp+68h+var_58], r14d\nxor ebx, ebx\nsub eax, 2\nmov [rsp+68h+var_40], r14d\nmov [rsp+68h+var_48], ebx\nmov ebx, eax\nloc_1249:\nmov eax, [rsp+68h+var_58]\ncmp eax, 3\njz loc_1AD0\nxor ecx, ecx\nlea r15d, [rax-2]\nmov [rsp+68h+var_54], ebx\nmov r14d, ebx\nmov [rsp+68h+var_4C], ebx\nmov r12d, ecx\nmov ebx, r15d\nloc_126D:\nmov edi, ebx\nmov ebp, ebx\nxor r13d, r13d\ncall func0\nlea edi, [rax-1]\ncmp edi, 1\njbe loc_1B7C\nmov [rsp+68h+var_5C], ebx\nmov ebx, eax\nnop dword ptr [rax+rax+00h]\nloc_1290:\ncall func0\nmov r15d, eax\nmov edi, eax\ncall func0\nsub ebx, r15d\nlea edi, [rbx-1]\nadd r13d, eax\ncmp edi, 1\nja short loc_1290\nmov ebx, [rsp+68h+var_5C]\nadd r13d, 1\nloc_12B5:\ncmp r14d, 3\njz loc_1AA0\nxor r15d, r15d\nlea edi, [rbx-1]\nloc_12C5:\ncall func0\nmov ebx, eax\nmov edi, eax\ncall func0\nsub ebp, ebx\nlea edi, [rbp-1]\nadd r15d, eax\ncmp edi, 1\nja short loc_12C5\nadd r15d, 1\nadd r12d, r13d\nsub r14d, r15d\nlea ebx, [r14-1]\ncmp ebx, 1\nja loc_126D\nmov ecx, r12d\nmov ebp, [rsp+68h+var_54]\nmov ebx, [rsp+68h+var_4C]\nlea r14d, [rcx+1]\ncmp ecx, 1\njbe loc_1ABB\nnop\nloc_1310:\nmov [rsp+68h+var_54], ebp\nxor r15d, r15d\nmov ebp, ecx\nmov [rsp+68h+var_4C], ebx\nmov ebx, r14d\nloc_1320:\nmov edi, ebp\nmov r13d, ebp\nxor r12d, r12d\ncall func0\nlea edi, [rax-1]\ncmp edi, 1\njbe loc_1B87\nmov [rsp+68h+var_5C], ebx\nmov ebx, eax\nnop\nloc_1340:\ncall func0\nmov r14d, eax\nmov edi, eax\ncall func0\nsub ebx, r14d\nlea edi, [rbx-1]\nadd r12d, eax\ncmp edi, 1\nja short loc_1340\nmov ebx, [rsp+68h+var_5C]\nadd r12d, 1\nloc_1365:\ncmp ebx, 3\njz loc_1A90\nxor r14d, r14d\nlea edi, [rbp-1]\nloc_1374:\ncall func0\nmov ebp, eax\nmov edi, eax\ncall func0\nsub r13d, ebp\nlea edi, [r13-1]\nadd r14d, eax\ncmp edi, 1\nja short loc_1374\nlea edx, [r14+1]\nadd r15d, r12d\nsub ebx, edx\nlea ebp, [rbx-1]\ncmp ebp, 1\nja loc_1320\nmov ebp, [rsp+68h+var_54]\nmov ebx, [rsp+68h+var_4C]\nxchg ax, ax\nloc_13B0:\nlea r13d, [r15+1]\nloc_13B4:\nmov [rsp+68h+var_5C], r13d\nxor r12d, r12d\nlea edi, [rbx-1]\nloc_13BF:\ncall func0\nxor r14d, r14d\nlea edi, [rax-1]\nmov r15d, eax\nmov r13d, eax\ncmp edi, 1\njbe loc_1B92\nnop dword ptr [rax+00000000h]\nloc_13E0:\ncall func0\nmov ebx, eax\nmov edi, eax\ncall func0\nsub r13d, ebx\nlea edi, [r13-1]\nadd r14d, eax\ncmp edi, 1\nja short loc_13E0\nadd r14d, 1\nloc_1401:\nsub ebp, r15d\nadd r12d, r14d\nlea edi, [rbp-1]\ncmp edi, 1\nja short loc_13BF\nadd r12d, 1\nsub [rsp+68h+var_58], r12d\nmov eax, [rsp+68h+var_58]\nmov r13d, [rsp+68h+var_5C]\nadd [rsp+68h+var_48], r13d\nlea ebx, [rax-1]\ncmp ebx, 1\nja loc_1249\nmov ebx, [rsp+68h+var_48]\nmov r14d, [rsp+68h+var_40]\nlea eax, [rbx+1]\nmov [rsp+68h+var_58], eax\ncmp ebx, 1\njbe loc_1AEC\nnop dword ptr [rax+rax+00h]\nloc_1450:\nxor r15d, r15d\nmov [rsp+68h+var_40], r14d\nmov r13d, ebx\nmov [rsp+68h+var_48], r15d\nloc_1460:\nmov eax, [rsp+68h+var_58]\ncmp eax, 3\njz loc_1B10\nmov [rsp+68h+var_54], r13d\nlea ebp, [rax-2]\nxor r14d, r14d\nmov ebx, r13d\nmov [rsp+68h+var_4C], r13d\nmov r12d, ebp\nloc_1483:\nmov edi, r12d\nmov r13d, r12d\nxor ebp, ebp\ncall func0\nlea edi, [rax-1]\ncmp edi, 1\njbe loc_1B9D\nmov [rsp+68h+var_5C], ebx\nmov ebx, eax\nnop word ptr [rax+rax+00h]\nloc_14A8:\ncall func0\nmov r15d, eax\nmov edi, eax\ncall func0\nsub ebx, r15d\nlea edi, [rbx-1]\nadd ebp, eax\ncmp edi, 1\nja short loc_14A8\nmov ebx, [rsp+68h+var_5C]\nlea r15d, [rbp+1]\nloc_14CC:\ncmp ebx, 3\njz loc_1A68\nxor ebp, ebp\nlea edi, [r12-1]\nloc_14DC:\ncall func0\nmov r12d, eax\nmov edi, eax\ncall func0\nsub r13d, r12d\nlea edi, [r13-1]\nadd ebp, eax\ncmp edi, 1\nja short loc_14DC\nadd ebp, 1\nadd r14d, r15d\nsub ebx, ebp\nlea r12d, [rbx-1]\ncmp r12d, 1\nja loc_1483\nmov r12d, [rsp+68h+var_54]\nmov r13d, [rsp+68h+var_4C]\nlea r15d, [r14+1]\ncmp r14d, 1\njbe loc_1A83\nnop word ptr [rax+rax+00000000h]\nloc_1530:\nxor edx, edx\nmov [rsp+68h+var_54], r12d\nmov r12d, r15d\nmov [rsp+68h+var_4C], r13d\nmov r15d, edx\nmov r13d, r14d\nloc_1545:\nmov edi, r13d\nmov ebp, r13d\nxor r14d, r14d\ncall func0\nlea edi, [rax-1]\ncmp edi, 1\njbe loc_1BA8\nmov [rsp+68h+var_5C], r13d\nmov ebp, eax\nnop word ptr [rax+rax+00000000h]\nloc_1570:\ncall func0\nmov ebx, eax\nmov edi, eax\ncall func0\nsub ebp, ebx\nlea edi, [rbp-1]\nadd r14d, eax\ncmp edi, 1\nja short loc_1570\nmov ebp, [rsp+68h+var_5C]\nlea ebx, [r14+1]\nloc_1593:\ncmp r12d, 3\njz loc_1A50\nxor r14d, r14d\nlea edi, [r13-1]\nloc_15A4:\ncall func0\nmov r13d, eax\nmov edi, eax\ncall func0\nsub ebp, r13d\nlea edi, [rbp-1]\nadd r14d, eax\ncmp edi, 1\nja short loc_15A4\nlea ecx, [r14+1]\nadd r15d, ebx\nsub r12d, ecx\nlea r13d, [r12-1]\ncmp r13d, 1\nja loc_1545\nmov r12d, [rsp+68h+var_54]\nmov r13d, [rsp+68h+var_4C]\nmov edx, r15d\nnop word ptr [rax+rax+00000000h]\nloc_15F0:\nlea ebx, [rdx+1]\nloc_15F3:\nxor edx, edx\nmov [rsp+68h+var_54], ebx\nsub r13d, 1\nmov [rsp+68h+var_5C], edx\nloc_1601:\nmov ebp, r13d\ncmp r12d, 3\njz loc_1A40\nmov ebx, r13d\nxor r15d, r15d\nlea edi, [r12-2]\nloc_1619:\ncall func0\nmov r14d, eax\nmov edi, eax\ncall func0\nsub ebx, r14d\nlea edi, [rbx-1]\nadd r15d, eax\ncmp edi, 1\nja short loc_1619\nlea r14d, [r15+1]\ncmp r15d, 1\njbe loc_1B28\nxor ebx, ebx\nmov edi, r15d\nloc_1649:\ncall func0\nmov r15d, eax\nmov edi, eax\ncall func0\nsub r14d, r15d\nlea edi, [r14-1]\nadd ebx, eax\ncmp edi, 1\nja short loc_1649\nlea r15d, [rbx+1]\nloc_166A:\nxor ebx, ebx\nlea edi, [r13-1]\nloc_1670:\ncall func0\nmov r13d, eax\nmov edi, eax\ncall func0\nsub ebp, r13d\nlea edi, [rbp-1]\nadd ebx, eax\ncmp edi, 1\nja short loc_1670\nlea edx, [rbx+1]\nadd [rsp+68h+var_5C], r15d\nsub r12d, edx\nlea r13d, [r12-1]\ncmp r13d, 1\nja loc_1601\nmov edx, [rsp+68h+var_5C]\nmov ebx, [rsp+68h+var_54]\nxchg ax, ax\nloc_16B0:\nadd edx, 1\nsub [rsp+68h+var_58], edx\nmov eax, [rsp+68h+var_58]\nadd [rsp+68h+var_48], ebx\nlea r13d, [rax-1]\ncmp r13d, 1\nja loc_1460\nmov r15d, [rsp+68h+var_48]\nmov r14d, [rsp+68h+var_40]\nnop word ptr [rax+rax+00000000h]\nloc_16E0:\nlea ebx, [r15+1]\nloc_16E4:\nxor edx, edx\nlea eax, [r14-1]\nmov [rsp+68h+var_40], ebx\nmov [rsp+68h+var_4C], eax\nmov [rsp+68h+var_48], edx\nloc_16F6:\nmov eax, [rsp+68h+var_4C]\nmov ecx, [rsp+68h+var_50]\nmov r13d, eax\ncmp ecx, 3\njz loc_1B00\nmov [rsp+68h+var_5C], eax\nlea eax, [rcx-2]\nmov [rsp+68h+var_54], 0\nmov [rsp+68h+var_58], eax\nloc_171D:\nmov r12d, [rsp+68h+var_58]\nmov eax, [rsp+68h+var_5C]\nmov ebx, r12d\ncmp eax, 3\njz loc_1A10\nxor r14d, r14d\nlea edi, [rax-2]\nloc_1738:\ncall func0\nmov ebp, eax\nmov edi, eax\ncall func0\nsub r12d, ebp\nlea edi, [r12-1]\nadd r14d, eax\ncmp edi, 1\nja short loc_1738\nlea r15d, [r14+1]\ncmp r14d, 1\njbe loc_1B58\nxor r12d, r12d\nmov edi, r14d\nloc_176A:\ncall func0\nmov ebp, eax\nmov edi, eax\ncall func0\nsub r15d, ebp\nlea edi, [r15-1]\nadd r12d, eax\ncmp edi, 1\nja short loc_176A\nadd r12d, 1\nloc_178B:\nmov eax, [rsp+68h+var_58]\nxor ebp, ebp\nlea edi, [rax-1]\nloc_1794:\ncall func0\nmov r14d, eax\nmov edi, eax\ncall func0\nsub ebx, r14d\nlea edi, [rbx-1]\nadd ebp, eax\ncmp edi, 1\nja short loc_1794\nlea edx, [rbp+1]\nsub [rsp+68h+var_5C], edx\nmov eax, [rsp+68h+var_5C]\nadd [rsp+68h+var_54], r12d\nsub eax, 1\nmov [rsp+68h+var_58], eax\ncmp eax, 1\nja loc_171D\nmov eax, [rsp+68h+var_54]\nlea ecx, [rax+1]\nmov [rsp+68h+var_5C], ecx\ncmp eax, 1\njbe loc_1A29\nnop dword ptr [rax+00h]\nloc_17E8:\nmov [rsp+68h+var_54], 0\nmov [rsp+68h+var_58], eax\nloc_17F4:\nmov r12d, [rsp+68h+var_58]\nmov eax, [rsp+68h+var_5C]\nmov ebx, r12d\ncmp eax, 3\njz loc_1A00\nxor r14d, r14d\nlea edi, [rax-2]\nloc_180F:\ncall func0\nmov ebp, eax\nmov edi, eax\ncall func0\nsub r12d, ebp\nlea edi, [r12-1]\nadd r14d, eax\ncmp edi, 1\nja short loc_180F\nlea r12d, [r14+1]\ncmp r14d, 1\njbe loc_1B48\nxor r15d, r15d\nmov edi, r14d\nloc_1841:\ncall func0\nmov ebp, eax\nmov edi, eax\ncall func0\nsub r12d, ebp\nlea edi, [r12-1]\nadd r15d, eax\ncmp edi, 1\nja short loc_1841\nlea r14d, [r15+1]\nloc_1863:\nmov eax, [rsp+68h+var_58]\nxor ebp, ebp\nlea edi, [rax-1]\nloc_186C:\ncall func0\nmov r12d, eax\nmov edi, eax\ncall func0\nsub ebx, r12d\nlea edi, [rbx-1]\nadd ebp, eax\ncmp edi, 1\nja short loc_186C\nlea edx, [rbp+1]\nsub [rsp+68h+var_5C], edx\nmov eax, [rsp+68h+var_5C]\nadd [rsp+68h+var_54], r14d\nsub eax, 1\nmov [rsp+68h+var_58], eax\ncmp eax, 1\nja loc_17F4\nnop dword ptr [rax+rax+00000000h]\nloc_18B0:\nmov eax, [rsp+68h+var_54]\nadd eax, 1\nmov [rsp+68h+var_54], eax\nloc_18BB:\nmov eax, [rsp+68h+var_4C]\nmov [rsp+68h+var_58], 0\nsub eax, 1\nmov [rsp+68h+var_5C], eax\nloc_18CE:\nmov r14d, [rsp+68h+var_5C]\nmov ebx, r14d\ncmp r13d, 3\njz loc_19F0\nxor r12d, r12d\nlea edi, [r13-2]\nloc_18E7:\ncall func0\nmov ebp, eax\nmov edi, eax\ncall func0\nsub r14d, ebp\nlea edi, [r14-1]\nadd r12d, eax\ncmp edi, 1\nja short loc_18E7\nlea r14d, [r12+1]\ncmp r12d, 1\njbe loc_1B38\nxor r15d, r15d\nmov edi, r12d\nloc_1919:\ncall func0\nmov ebp, eax\nmov edi, eax\ncall func0\nsub r14d, ebp\nlea edi, [r14-1]\nadd r15d, eax\ncmp edi, 1\nja short loc_1919\nlea ebp, [r15+1]\nloc_193A:\nmov eax, [rsp+68h+var_5C]\nxor r15d, r15d\nlea edi, [rax-1]\nloc_1944:\ncall func0\nmov r14d, eax\nmov edi, eax\ncall func0\nsub ebx, r14d\nlea edi, [rbx-1]\nadd r15d, eax\ncmp edi, 1\nja short loc_1944\nlea edx, [r15+1]\nadd [rsp+68h+var_58], ebp\nsub r13d, edx\nlea eax, [r13-1]\nmov [rsp+68h+var_5C], eax\ncmp eax, 1\nja loc_18CE\nnop dword ptr [rax]\nloc_1980:\nmov r12d, [rsp+68h+var_58]\nmov ecx, [rsp+68h+var_54]\nadd [rsp+68h+var_48], ecx\nadd r12d, 1\nsub [rsp+68h+var_50], r12d\nmov eax, [rsp+68h+var_50]\nsub eax, 1\nmov [rsp+68h+var_4C], eax\ncmp eax, 1\nja loc_16F6\nmov edx, [rsp+68h+var_48]\nmov ebx, [rsp+68h+var_40]\nnop word ptr [rax+rax+00h]\nloc_19B8:\nadd edx, 1\nsub [rsp+68h+var_44], edx\nmov eax, [rsp+68h+var_44]\nadd [rsp+68h+var_3C], ebx\nlea r14d, [rax-1]\ncmp r14d, 1\nja loc_1222\nmov ebp, [rsp+68h+var_3C]\nlea eax, [rbp+1]\nloc_19DC:\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_19F0:\nadd [rsp+68h+var_58], 1\njmp short loc_1980\nloc_1A00:\nadd [rsp+68h+var_54], 1\njmp loc_18B0\nloc_1A10:\nadd [rsp+68h+var_54], 1\nmov eax, [rsp+68h+var_54]\nlea ecx, [rax+1]\nmov [rsp+68h+var_5C], ecx\ncmp eax, 1\nja loc_17E8\nloc_1A29:\nmov [rsp+68h+var_54], 1\njmp loc_18BB\nloc_1A40:\nmov edx, [rsp+68h+var_5C]\nmov ebx, [rsp+68h+var_54]\nadd edx, 1\njmp loc_16B0\nloc_1A50:\nmov edx, r15d\nmov r12d, [rsp+68h+var_54]\nmov r13d, [rsp+68h+var_4C]\nadd edx, ebx\njmp loc_15F0\nloc_1A68:\nadd r14d, r15d\nmov r12d, [rsp+68h+var_54]\nmov r13d, [rsp+68h+var_4C]\nlea r15d, [r14+1]\ncmp r14d, 1\nja loc_1530\nloc_1A83:\nmov ebx, 1\njmp loc_15F3\nloc_1A90:\nmov ebp, [rsp+68h+var_54]\nmov ebx, [rsp+68h+var_4C]\nadd r15d, r12d\njmp loc_13B0\nloc_1AA0:\nmov ecx, r12d\nmov ebp, [rsp+68h+var_54]\nmov ebx, [rsp+68h+var_4C]\nadd ecx, r13d\nlea r14d, [rcx+1]\ncmp ecx, 1\nja loc_1310\nloc_1ABB:\nmov r13d, 1\njmp loc_13B4\nloc_1AD0:\nmov ebx, [rsp+68h+var_48]\nmov r14d, [rsp+68h+var_40]\nadd ebx, 1\nlea eax, [rbx+1]\nmov [rsp+68h+var_58], eax\ncmp ebx, 1\nja loc_1450\nloc_1AEC:\nmov ebx, 1\njmp loc_16E4\nloc_1B00:\nmov edx, [rsp+68h+var_48]\nmov ebx, [rsp+68h+var_40]\nadd edx, 1\njmp loc_19B8\nloc_1B10:\nmov r15d, [rsp+68h+var_48]\nmov r14d, [rsp+68h+var_40]\nadd r15d, 1\njmp loc_16E0\nloc_1B28:\nmov r15d, 1\njmp loc_166A\nloc_1B38:\nmov ebp, 1\njmp loc_193A\nloc_1B48:\nmov r14d, 1\njmp loc_1863\nloc_1B58:\nmov r12d, 1\njmp loc_178B\nloc_1B63:\nmov ebp, [rsp+68h+var_3C]\nadd rsp, 38h\npop rbx\nadd ebp, 1\nlea eax, [rbp+1]\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1B7C:\nmov r13d, 1\njmp loc_12B5\nloc_1B87:\nmov r12d, 1\njmp loc_1365\nloc_1B92:\nmov r14d, 1\njmp loc_1401\nloc_1B9D:\nmov r15d, 1\njmp loc_14CC\nloc_1BA8:\nmov ebx, 1\njmp loc_1593", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n __int64 result; // rax\n int v2; // r14d\n int v3; // ebx\n int v4; // r14d\n unsigned int v5; // r12d\n unsigned int v6; // ebx\n unsigned int v7; // ebp\n int v8; // r13d\n int v9; // eax\n __int64 v10; // rdi\n int v11; // ebx\n __int64 v12; // r15\n int v13; // r13d\n int v14; // r15d\n __int64 v15; // rdi\n __int64 v16; // rbx\n unsigned int v17; // ecx\n int v18; // ebp\n int v19; // ebx\n int v20; // r14d\n int v21; // r15d\n unsigned int v22; // ebp\n int v23; // ebx\n unsigned int v24; // r13d\n int v25; // r12d\n int v26; // eax\n __int64 v27; // rdi\n int v28; // ebx\n __int64 v29; // r14\n int v30; // r12d\n int v31; // r14d\n __int64 v32; // rdi\n __int64 v33; // rbp\n int v34; // r13d\n int v35; // r12d\n __int64 v36; // rdi\n int v37; // eax\n int v38; // r14d\n __int64 v39; // rdi\n int v40; // r15d\n int v41; // r13d\n __int64 v42; // rbx\n int v43; // r14d\n unsigned int v44; // ebx\n int v45; // r14d\n unsigned int v46; // r13d\n unsigned int v47; // r14d\n unsigned int v48; // ebx\n unsigned int v49; // r12d\n unsigned int v50; // r13d\n int v51; // ebp\n int v52; // eax\n __int64 v53; // rdi\n int v54; // ebx\n __int64 v55; // r15\n int v56; // r15d\n int v57; // ebp\n __int64 v58; // rdi\n __int64 v59; // r12\n unsigned int v60; // r12d\n unsigned int v61; // r13d\n unsigned int v62; // r15d\n unsigned int v63; // r12d\n int v64; // r15d\n unsigned int v65; // r13d\n unsigned int v66; // ebp\n int v67; // r14d\n int v68; // eax\n __int64 v69; // rdi\n int v70; // ebp\n __int64 v71; // rbx\n int v72; // ebx\n int v73; // r14d\n __int64 v74; // rdi\n __int64 v75; // r13\n int v76; // edx\n int v77; // ebx\n unsigned int v78; // r13d\n unsigned int v79; // ebp\n unsigned int v80; // ebx\n unsigned int v81; // r15d\n __int64 v82; // rdi\n __int64 v83; // r14\n unsigned int v84; // r14d\n int v85; // ebx\n __int64 v86; // rdi\n __int64 v87; // r15\n int v88; // r15d\n int v89; // ebx\n __int64 v90; // rdi\n __int64 v91; // r13\n int v92; // edx\n int v93; // ebx\n int v94; // r15d\n int v95; // ebx\n int v96; // r13d\n int v97; // r12d\n int v98; // ebx\n unsigned int v99; // r14d\n __int64 v100; // rdi\n __int64 v101; // rbp\n unsigned int v102; // r15d\n int v103; // r12d\n __int64 v104; // rdi\n __int64 v105; // rbp\n int v106; // r12d\n int v107; // ebp\n __int64 v108; // rdi\n __int64 v109; // r14\n unsigned int v110; // eax\n unsigned int v111; // r12d\n unsigned int v112; // ebx\n unsigned int v113; // r14d\n __int64 v114; // rdi\n __int64 v115; // rbp\n unsigned int v116; // r12d\n int v117; // r15d\n __int64 v118; // rdi\n __int64 v119; // rbp\n int v120; // r14d\n int v121; // ebp\n __int64 v122; // rdi\n __int64 v123; // r12\n int v124; // r14d\n int v125; // ebx\n unsigned int v126; // r12d\n __int64 v127; // rdi\n __int64 v128; // rbp\n unsigned int v129; // r14d\n int v130; // r15d\n __int64 v131; // rdi\n __int64 v132; // rbp\n int v133; // ebp\n int v134; // r15d\n __int64 v135; // rdi\n __int64 v136; // r14\n int v137; // edx\n int v138; // ebx\n unsigned int v139; // [rsp+Ch] [rbp-5Ch]\n int v140; // [rsp+Ch] [rbp-5Ch]\n int v141; // [rsp+Ch] [rbp-5Ch]\n unsigned int v142; // [rsp+Ch] [rbp-5Ch]\n int v143; // [rsp+Ch] [rbp-5Ch]\n int v144; // [rsp+Ch] [rbp-5Ch]\n unsigned int v145; // [rsp+Ch] [rbp-5Ch]\n int v146; // [rsp+Ch] [rbp-5Ch]\n int v147; // [rsp+10h] [rbp-58h]\n unsigned int v148; // [rsp+10h] [rbp-58h]\n int v149; // [rsp+10h] [rbp-58h]\n unsigned int v150; // [rsp+10h] [rbp-58h]\n int v151; // [rsp+10h] [rbp-58h]\n int v152; // [rsp+14h] [rbp-54h]\n int v153; // [rsp+14h] [rbp-54h]\n unsigned int v154; // [rsp+14h] [rbp-54h]\n unsigned int v155; // [rsp+14h] [rbp-54h]\n int v156; // [rsp+14h] [rbp-54h]\n unsigned int v157; // [rsp+14h] [rbp-54h]\n int v158; // [rsp+14h] [rbp-54h]\n int v159; // [rsp+14h] [rbp-54h]\n int v160; // [rsp+18h] [rbp-50h]\n int v161; // [rsp+1Ch] [rbp-4Ch]\n int v162; // [rsp+1Ch] [rbp-4Ch]\n unsigned int v163; // [rsp+1Ch] [rbp-4Ch]\n unsigned int v164; // [rsp+1Ch] [rbp-4Ch]\n int v165; // [rsp+1Ch] [rbp-4Ch]\n unsigned int v166; // [rsp+20h] [rbp-48h]\n int v167; // [rsp+20h] [rbp-48h]\n int v168; // [rsp+20h] [rbp-48h]\n int v169; // [rsp+24h] [rbp-44h]\n int v170; // [rsp+28h] [rbp-40h]\n int v171; // [rsp+28h] [rbp-40h]\n int v172; // [rsp+28h] [rbp-40h]\n int v173; // [rsp+2Ch] [rbp-3Ch]\n\n result = 1LL;\n if ( (unsigned int)(a1 - 1) > 1 )\n {\n v169 = a1;\n v2 = a1 - 1;\n v173 = 0;\n while ( 1 )\n {\n v160 = v2;\n if ( v169 == 3 )\n return (unsigned int)(v173 + 2);\n v147 = v2;\n v170 = v2;\n v166 = 0;\n v3 = v169 - 2;\n while ( v147 != 3 )\n {\n v152 = v3;\n v4 = v3;\n v161 = v3;\n v5 = 0;\n v6 = v147 - 2;\n while ( 1 )\n {\n v7 = v6;\n v8 = 0;\n v9 = func0(v6);\n v10 = (unsigned int)(v9 - 1);\n if ( (unsigned int)v10 <= 1 )\n {\n v13 = 1;\n }\n else\n {\n v139 = v6;\n v11 = v9;\n do\n {\n v12 = (unsigned int)func0(v10);\n v11 -= v12;\n v10 = (unsigned int)(v11 - 1);\n v8 += func0(v12);\n }\n while ( (unsigned int)v10 > 1 );\n v6 = v139;\n v13 = v8 + 1;\n }\n if ( v4 == 3 )\n break;\n v14 = 0;\n v15 = v6 - 1;\n do\n {\n v16 = (unsigned int)func0(v15);\n v7 -= v16;\n v15 = v7 - 1;\n v14 += func0(v16);\n }\n while ( (unsigned int)v15 > 1 );\n v5 += v13;\n v4 -= v14 + 1;\n v6 = v4 - 1;\n if ( (unsigned int)(v4 - 1) <= 1 )\n {\n v17 = v5;\n v18 = v152;\n v19 = v161;\n v20 = v5 + 1;\n if ( v5 > 1 )\n goto LABEL_16;\nLABEL_124:\n v34 = 1;\n goto LABEL_27;\n }\n }\n v18 = v152;\n v19 = v161;\n v17 = v13 + v5;\n v20 = v13 + v5 + 1;\n if ( v13 + v5 <= 1 )\n goto LABEL_124;\nLABEL_16:\n v153 = v18;\n v21 = 0;\n v22 = v17;\n v162 = v19;\n v23 = v20;\n while ( 1 )\n {\n v24 = v22;\n v25 = 0;\n v26 = func0(v22);\n v27 = (unsigned int)(v26 - 1);\n if ( (unsigned int)v27 <= 1 )\n {\n v30 = 1;\n }\n else\n {\n v140 = v23;\n v28 = v26;\n do\n {\n v29 = (unsigned int)func0(v27);\n v28 -= v29;\n v27 = (unsigned int)(v28 - 1);\n v25 += func0(v29);\n }\n while ( (unsigned int)v27 > 1 );\n v23 = v140;\n v30 = v25 + 1;\n }\n if ( v23 == 3 )\n break;\n v31 = 0;\n v32 = v22 - 1;\n do\n {\n v33 = (unsigned int)func0(v32);\n v24 -= v33;\n v32 = v24 - 1;\n v31 += func0(v33);\n }\n while ( (unsigned int)v32 > 1 );\n v21 += v30;\n v23 -= v31 + 1;\n v22 = v23 - 1;\n if ( (unsigned int)(v23 - 1) <= 1 )\n {\n v18 = v153;\n v19 = v162;\n goto LABEL_26;\n }\n }\n v18 = v153;\n v19 = v162;\n v21 += v30;\nLABEL_26:\n v34 = v21 + 1;\nLABEL_27:\n v141 = v34;\n v35 = 0;\n v36 = (unsigned int)(v19 - 1);\n do\n {\n v37 = func0(v36);\n v38 = 0;\n v39 = (unsigned int)(v37 - 1);\n v40 = v37;\n v41 = v37;\n if ( (unsigned int)v39 <= 1 )\n {\n v43 = 1;\n }\n else\n {\n do\n {\n v42 = (unsigned int)func0(v39);\n v41 -= v42;\n v39 = (unsigned int)(v41 - 1);\n v38 += func0(v42);\n }\n while ( (unsigned int)v39 > 1 );\n v43 = v38 + 1;\n }\n v18 -= v40;\n v35 += v43;\n v36 = (unsigned int)(v18 - 1);\n }\n while ( (unsigned int)v36 > 1 );\n v147 -= v35 + 1;\n v166 += v141;\n v3 = v147 - 1;\n if ( (unsigned int)(v147 - 1) <= 1 )\n {\n v44 = v166;\n v45 = v170;\n v148 = v166 + 1;\n if ( v166 > 1 )\n goto LABEL_34;\nLABEL_126:\n v95 = 1;\n goto LABEL_72;\n }\n }\n v45 = v170;\n v44 = v166 + 1;\n v148 = v166 + 2;\n if ( v166 + 1 <= 1 )\n goto LABEL_126;\nLABEL_34:\n v171 = v45;\n v46 = v44;\n v167 = 0;\n while ( v148 != 3 )\n {\n v154 = v46;\n v47 = 0;\n v48 = v46;\n v163 = v46;\n v49 = v148 - 2;\n while ( 1 )\n {\n v50 = v49;\n v51 = 0;\n v52 = func0(v49);\n v53 = (unsigned int)(v52 - 1);\n if ( (unsigned int)v53 <= 1 )\n {\n v56 = 1;\n }\n else\n {\n v142 = v48;\n v54 = v52;\n do\n {\n v55 = (unsigned int)func0(v53);\n v54 -= v55;\n v53 = (unsigned int)(v54 - 1);\n v51 += func0(v55);\n }\n while ( (unsigned int)v53 > 1 );\n v48 = v142;\n v56 = v51 + 1;\n }\n if ( v48 == 3 )\n break;\n v57 = 0;\n v58 = v49 - 1;\n do\n {\n v59 = (unsigned int)func0(v58);\n v50 -= v59;\n v58 = v50 - 1;\n v57 += func0(v59);\n }\n while ( (unsigned int)v58 > 1 );\n v47 += v56;\n v48 -= v57 + 1;\n v49 = v48 - 1;\n if ( v48 - 1 <= 1 )\n {\n v60 = v154;\n v61 = v163;\n v62 = v47 + 1;\n if ( v47 > 1 )\n goto LABEL_46;\nLABEL_121:\n v77 = 1;\n goto LABEL_57;\n }\n }\n v47 += v56;\n v60 = v154;\n v61 = v163;\n v62 = v47 + 1;\n if ( v47 <= 1 )\n goto LABEL_121;\nLABEL_46:\n v155 = v60;\n v63 = v62;\n v164 = v61;\n v64 = 0;\n v65 = v47;\n while ( 1 )\n {\n v66 = v65;\n v67 = 0;\n v68 = func0(v65);\n v69 = (unsigned int)(v68 - 1);\n if ( (unsigned int)v69 <= 1 )\n {\n v72 = 1;\n }\n else\n {\n v70 = v68;\n do\n {\n v71 = (unsigned int)func0(v69);\n v70 -= v71;\n v69 = (unsigned int)(v70 - 1);\n v67 += func0(v71);\n }\n while ( (unsigned int)v69 > 1 );\n v66 = v65;\n v72 = v67 + 1;\n }\n if ( v63 == 3 )\n break;\n v73 = 0;\n v74 = v65 - 1;\n do\n {\n v75 = (unsigned int)func0(v74);\n v66 -= v75;\n v74 = v66 - 1;\n v73 += func0(v75);\n }\n while ( (unsigned int)v74 > 1 );\n v64 += v72;\n v63 -= v73 + 1;\n v65 = v63 - 1;\n if ( v63 - 1 <= 1 )\n {\n v60 = v155;\n v61 = v164;\n v76 = v64;\n goto LABEL_56;\n }\n }\n v60 = v155;\n v61 = v164;\n v76 = v72 + v64;\nLABEL_56:\n v77 = v76 + 1;\nLABEL_57:\n v156 = v77;\n v78 = v61 - 1;\n v143 = 0;\n while ( 1 )\n {\n v79 = v78;\n if ( v60 == 3 )\n break;\n v80 = v78;\n v81 = 0;\n v82 = v60 - 2;\n do\n {\n v83 = (unsigned int)func0(v82);\n v80 -= v83;\n v82 = v80 - 1;\n v81 += func0(v83);\n }\n while ( (unsigned int)v82 > 1 );\n v84 = v81 + 1;\n if ( v81 <= 1 )\n {\n v88 = 1;\n }\n else\n {\n v85 = 0;\n v86 = v81;\n do\n {\n v87 = (unsigned int)func0(v86);\n v84 -= v87;\n v86 = v84 - 1;\n v85 += func0(v87);\n }\n while ( (unsigned int)v86 > 1 );\n v88 = v85 + 1;\n }\n v89 = 0;\n v90 = v78 - 1;\n do\n {\n v91 = (unsigned int)func0(v90);\n v79 -= v91;\n v90 = v79 - 1;\n v89 += func0(v91);\n }\n while ( (unsigned int)v90 > 1 );\n v143 += v88;\n v60 -= v89 + 1;\n v78 = v60 - 1;\n if ( v60 - 1 <= 1 )\n {\n v92 = v143;\n v93 = v156;\n goto LABEL_69;\n }\n }\n v93 = v156;\n v92 = v143 + 1;\nLABEL_69:\n v148 -= v92 + 1;\n v167 += v93;\n v46 = v148 - 1;\n if ( v148 - 1 <= 1 )\n {\n v94 = v167;\n v45 = v171;\n goto LABEL_71;\n }\n }\n v45 = v171;\n v94 = v167 + 1;\nLABEL_71:\n v95 = v94 + 1;\nLABEL_72:\n v172 = v95;\n v165 = v45 - 1;\n v168 = 0;\n while ( 1 )\n {\n v96 = v165;\n if ( v160 == 3 )\n break;\n v144 = v165;\n v157 = 0;\n v149 = v160 - 2;\n while ( 1 )\n {\n v97 = v149;\n v98 = v149;\n if ( v144 == 3 )\n break;\n v99 = 0;\n v100 = (unsigned int)(v144 - 2);\n do\n {\n v101 = (unsigned int)func0(v100);\n v97 -= v101;\n v100 = (unsigned int)(v97 - 1);\n v99 += func0(v101);\n }\n while ( (unsigned int)v100 > 1 );\n v102 = v99 + 1;\n if ( v99 <= 1 )\n {\n v106 = 1;\n }\n else\n {\n v103 = 0;\n v104 = v99;\n do\n {\n v105 = (unsigned int)func0(v104);\n v102 -= v105;\n v104 = v102 - 1;\n v103 += func0(v105);\n }\n while ( (unsigned int)v104 > 1 );\n v106 = v103 + 1;\n }\n v107 = 0;\n v108 = (unsigned int)(v149 - 1);\n do\n {\n v109 = (unsigned int)func0(v108);\n v98 -= v109;\n v108 = (unsigned int)(v98 - 1);\n v107 += func0(v109);\n }\n while ( (unsigned int)v108 > 1 );\n v144 -= v107 + 1;\n v157 += v106;\n v149 = v144 - 1;\n if ( (unsigned int)(v144 - 1) <= 1 )\n {\n v110 = v157;\n v145 = v157 + 1;\n if ( v157 > 1 )\n goto LABEL_86;\nLABEL_117:\n v159 = 1;\n goto LABEL_98;\n }\n }\n v110 = v157 + 1;\n v145 = v157 + 2;\n if ( v157 + 1 <= 1 )\n goto LABEL_117;\nLABEL_86:\n v158 = 0;\n v150 = v110;\n while ( 1 )\n {\n v111 = v150;\n v112 = v150;\n if ( v145 == 3 )\n break;\n v113 = 0;\n v114 = v145 - 2;\n do\n {\n v115 = (unsigned int)func0(v114);\n v111 -= v115;\n v114 = v111 - 1;\n v113 += func0(v115);\n }\n while ( (unsigned int)v114 > 1 );\n v116 = v113 + 1;\n if ( v113 <= 1 )\n {\n v120 = 1;\n }\n else\n {\n v117 = 0;\n v118 = v113;\n do\n {\n v119 = (unsigned int)func0(v118);\n v116 -= v119;\n v118 = v116 - 1;\n v117 += func0(v119);\n }\n while ( (unsigned int)v118 > 1 );\n v120 = v117 + 1;\n }\n v121 = 0;\n v122 = v150 - 1;\n do\n {\n v123 = (unsigned int)func0(v122);\n v112 -= v123;\n v122 = v112 - 1;\n v121 += func0(v123);\n }\n while ( (unsigned int)v122 > 1 );\n v145 -= v121 + 1;\n v158 += v120;\n v150 = v145 - 1;\n if ( v145 - 1 <= 1 )\n goto LABEL_97;\n }\n ++v158;\nLABEL_97:\n v159 = v158 + 1;\nLABEL_98:\n v151 = 0;\n v146 = v165 - 1;\n while ( 1 )\n {\n v124 = v146;\n v125 = v146;\n if ( v96 == 3 )\n break;\n v126 = 0;\n v127 = (unsigned int)(v96 - 2);\n do\n {\n v128 = (unsigned int)func0(v127);\n v124 -= v128;\n v127 = (unsigned int)(v124 - 1);\n v126 += func0(v128);\n }\n while ( (unsigned int)v127 > 1 );\n v129 = v126 + 1;\n if ( v126 <= 1 )\n {\n v133 = 1;\n }\n else\n {\n v130 = 0;\n v131 = v126;\n do\n {\n v132 = (unsigned int)func0(v131);\n v129 -= v132;\n v131 = v129 - 1;\n v130 += func0(v132);\n }\n while ( (unsigned int)v131 > 1 );\n v133 = v130 + 1;\n }\n v134 = 0;\n v135 = (unsigned int)(v146 - 1);\n do\n {\n v136 = (unsigned int)func0(v135);\n v125 -= v136;\n v135 = (unsigned int)(v125 - 1);\n v134 += func0(v136);\n }\n while ( (unsigned int)v135 > 1 );\n v151 += v133;\n v96 -= v134 + 1;\n v146 = v96 - 1;\n if ( (unsigned int)(v96 - 1) <= 1 )\n goto LABEL_109;\n }\n ++v151;\nLABEL_109:\n v168 += v159;\n v160 -= v151 + 1;\n v165 = v160 - 1;\n if ( (unsigned int)(v160 - 1) <= 1 )\n {\n v137 = v168;\n v138 = v172;\n goto LABEL_111;\n }\n }\n v138 = v172;\n v137 = v168 + 1;\nLABEL_111:\n v169 -= v137 + 1;\n v173 += v138;\n v2 = v169 - 1;\n if ( (unsigned int)(v169 - 1) <= 1 )\n return (unsigned int)(v173 + 1);\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_11F0:\nendbr64\npush r15\nmov eax, 1\npush r14\npush r13\npush r12\nlea r12d, [rdi-1]\npush rbp\npush rbx\nsub rsp, 38h\ncmp r12d, 1\njbe loc_19DC\nxor ebp, ebp\nmov [rsp+68h+var_44], edi\nmov r14d, r12d\nmov [rsp+68h+var_3C], ebp\nloc_1222:\nmov eax, [rsp+68h+var_44]\nmov [rsp+68h+var_50], r14d\ncmp eax, 3\njz loc_1B63\nmov [rsp+68h+var_58], r14d\nxor ebx, ebx\nsub eax, 2\nmov [rsp+68h+var_40], r14d\nmov [rsp+68h+var_48], ebx\nmov ebx, eax\nloc_1249:\nmov eax, [rsp+68h+var_58]\ncmp eax, 3\njz loc_1AD0\nxor ecx, ecx\nlea r15d, [rax-2]\nmov [rsp+68h+var_54], ebx\nmov r14d, ebx\nmov [rsp+68h+var_4C], ebx\nmov r12d, ecx\nmov ebx, r15d\nloc_126D:\nmov edi, ebx\nmov ebp, ebx\nxor r13d, r13d\ncall sub_11F0\nlea edi, [rax-1]\ncmp edi, 1\njbe loc_1B7C\nmov [rsp+68h+var_5C], ebx\nmov ebx, eax\nnop dword ptr [rax+rax+00h]\nloc_1290:\ncall sub_11F0\nmov r15d, eax\nmov edi, eax\ncall sub_11F0\nsub ebx, r15d\nlea edi, [rbx-1]\nadd r13d, eax\ncmp edi, 1\nja short loc_1290\nmov ebx, [rsp+68h+var_5C]\nadd r13d, 1\nloc_12B5:\ncmp r14d, 3\njz loc_1AA0\nxor r15d, r15d\nlea edi, [rbx-1]\nloc_12C5:\ncall sub_11F0\nmov ebx, eax\nmov edi, eax\ncall sub_11F0\nsub ebp, ebx\nlea edi, [rbp-1]\nadd r15d, eax\ncmp edi, 1\nja short loc_12C5\nadd r15d, 1\nadd r12d, r13d\nsub r14d, r15d\nlea ebx, [r14-1]\ncmp ebx, 1\nja loc_126D\nmov ecx, r12d\nmov ebp, [rsp+68h+var_54]\nmov ebx, [rsp+68h+var_4C]\nlea r14d, [rcx+1]\ncmp ecx, 1\njbe loc_1ABB\nnop\nloc_1310:\nmov [rsp+68h+var_54], ebp\nxor r15d, r15d\nmov ebp, ecx\nmov [rsp+68h+var_4C], ebx\nmov ebx, r14d\nloc_1320:\nmov edi, ebp\nmov r13d, ebp\nxor r12d, r12d\ncall sub_11F0\nlea edi, [rax-1]\ncmp edi, 1\njbe loc_1B87\nmov [rsp+68h+var_5C], ebx\nmov ebx, eax\nnop\nloc_1340:\ncall sub_11F0\nmov r14d, eax\nmov edi, eax\ncall sub_11F0\nsub ebx, r14d\nlea edi, [rbx-1]\nadd r12d, eax\ncmp edi, 1\nja short loc_1340\nmov ebx, [rsp+68h+var_5C]\nadd r12d, 1\nloc_1365:\ncmp ebx, 3\njz loc_1A90\nxor r14d, r14d\nlea edi, [rbp-1]\nloc_1374:\ncall sub_11F0\nmov ebp, eax\nmov edi, eax\ncall sub_11F0\nsub r13d, ebp\nlea edi, [r13-1]\nadd r14d, eax\ncmp edi, 1\nja short loc_1374\nlea edx, [r14+1]\nadd r15d, r12d\nsub ebx, edx\nlea ebp, [rbx-1]\ncmp ebp, 1\nja loc_1320\nmov ebp, [rsp+68h+var_54]\nmov ebx, [rsp+68h+var_4C]\nxchg ax, ax\nloc_13B0:\nlea r13d, [r15+1]\nloc_13B4:\nmov [rsp+68h+var_5C], r13d\nxor r12d, r12d\nlea edi, [rbx-1]\nloc_13BF:\ncall sub_11F0\nxor r14d, r14d\nlea edi, [rax-1]\nmov r15d, eax\nmov r13d, eax\ncmp edi, 1\njbe loc_1B92\nnop dword ptr [rax+00000000h]\nloc_13E0:\ncall sub_11F0\nmov ebx, eax\nmov edi, eax\ncall sub_11F0\nsub r13d, ebx\nlea edi, [r13-1]\nadd r14d, eax\ncmp edi, 1\nja short loc_13E0\nadd r14d, 1\nloc_1401:\nsub ebp, r15d\nadd r12d, r14d\nlea edi, [rbp-1]\ncmp edi, 1\nja short loc_13BF\nadd r12d, 1\nsub [rsp+68h+var_58], r12d\nmov eax, [rsp+68h+var_58]\nmov r13d, [rsp+68h+var_5C]\nadd [rsp+68h+var_48], r13d\nlea ebx, [rax-1]\ncmp ebx, 1\nja loc_1249\nmov ebx, [rsp+68h+var_48]\nmov r14d, [rsp+68h+var_40]\nlea eax, [rbx+1]\nmov [rsp+68h+var_58], eax\ncmp ebx, 1\njbe loc_1AEC\nnop dword ptr [rax+rax+00h]\nloc_1450:\nxor r15d, r15d\nmov [rsp+68h+var_40], r14d\nmov r13d, ebx\nmov [rsp+68h+var_48], r15d\nloc_1460:\nmov eax, [rsp+68h+var_58]\ncmp eax, 3\njz loc_1B10\nmov [rsp+68h+var_54], r13d\nlea ebp, [rax-2]\nxor r14d, r14d\nmov ebx, r13d\nmov [rsp+68h+var_4C], r13d\nmov r12d, ebp\nloc_1483:\nmov edi, r12d\nmov r13d, r12d\nxor ebp, ebp\ncall sub_11F0\nlea edi, [rax-1]\ncmp edi, 1\njbe loc_1B9D\nmov [rsp+68h+var_5C], ebx\nmov ebx, eax\nnop word ptr [rax+rax+00h]\nloc_14A8:\ncall sub_11F0\nmov r15d, eax\nmov edi, eax\ncall sub_11F0\nsub ebx, r15d\nlea edi, [rbx-1]\nadd ebp, eax\ncmp edi, 1\nja short loc_14A8\nmov ebx, [rsp+68h+var_5C]\nlea r15d, [rbp+1]\nloc_14CC:\ncmp ebx, 3\njz loc_1A68\nxor ebp, ebp\nlea edi, [r12-1]\nloc_14DC:\ncall sub_11F0\nmov r12d, eax\nmov edi, eax\ncall sub_11F0\nsub r13d, r12d\nlea edi, [r13-1]\nadd ebp, eax\ncmp edi, 1\nja short loc_14DC\nadd ebp, 1\nadd r14d, r15d\nsub ebx, ebp\nlea r12d, [rbx-1]\ncmp r12d, 1\nja loc_1483\nmov r12d, [rsp+68h+var_54]\nmov r13d, [rsp+68h+var_4C]\nlea r15d, [r14+1]\ncmp r14d, 1\njbe loc_1A83\nnop word ptr [rax+rax+00000000h]\nloc_1530:\nxor edx, edx\nmov [rsp+68h+var_54], r12d\nmov r12d, r15d\nmov [rsp+68h+var_4C], r13d\nmov r15d, edx\nmov r13d, r14d\nloc_1545:\nmov edi, r13d\nmov ebp, r13d\nxor r14d, r14d\ncall sub_11F0\nlea edi, [rax-1]\ncmp edi, 1\njbe loc_1BA8\nmov [rsp+68h+var_5C], r13d\nmov ebp, eax\nnop word ptr [rax+rax+00000000h]\nloc_1570:\ncall sub_11F0\nmov ebx, eax\nmov edi, eax\ncall sub_11F0\nsub ebp, ebx\nlea edi, [rbp-1]\nadd r14d, eax\ncmp edi, 1\nja short loc_1570\nmov ebp, [rsp+68h+var_5C]\nlea ebx, [r14+1]\nloc_1593:\ncmp r12d, 3\njz loc_1A50\nxor r14d, r14d\nlea edi, [r13-1]\nloc_15A4:\ncall sub_11F0\nmov r13d, eax\nmov edi, eax\ncall sub_11F0\nsub ebp, r13d\nlea edi, [rbp-1]\nadd r14d, eax\ncmp edi, 1\nja short loc_15A4\nlea ecx, [r14+1]\nadd r15d, ebx\nsub r12d, ecx\nlea r13d, [r12-1]\ncmp r13d, 1\nja loc_1545\nmov r12d, [rsp+68h+var_54]\nmov r13d, [rsp+68h+var_4C]\nmov edx, r15d\nnop word ptr [rax+rax+00000000h]\nloc_15F0:\nlea ebx, [rdx+1]\nloc_15F3:\nxor edx, edx\nmov [rsp+68h+var_54], ebx\nsub r13d, 1\nmov [rsp+68h+var_5C], edx\nloc_1601:\nmov ebp, r13d\ncmp r12d, 3\njz loc_1A40\nmov ebx, r13d\nxor r15d, r15d\nlea edi, [r12-2]\nloc_1619:\ncall sub_11F0\nmov r14d, eax\nmov edi, eax\ncall sub_11F0\nsub ebx, r14d\nlea edi, [rbx-1]\nadd r15d, eax\ncmp edi, 1\nja short loc_1619\nlea r14d, [r15+1]\ncmp r15d, 1\njbe loc_1B28\nxor ebx, ebx\nmov edi, r15d\nloc_1649:\ncall sub_11F0\nmov r15d, eax\nmov edi, eax\ncall sub_11F0\nsub r14d, r15d\nlea edi, [r14-1]\nadd ebx, eax\ncmp edi, 1\nja short loc_1649\nlea r15d, [rbx+1]\nloc_166A:\nxor ebx, ebx\nlea edi, [r13-1]\nloc_1670:\ncall sub_11F0\nmov r13d, eax\nmov edi, eax\ncall sub_11F0\nsub ebp, r13d\nlea edi, [rbp-1]\nadd ebx, eax\ncmp edi, 1\nja short loc_1670\nlea edx, [rbx+1]\nadd [rsp+68h+var_5C], r15d\nsub r12d, edx\nlea r13d, [r12-1]\ncmp r13d, 1\nja loc_1601\nmov edx, [rsp+68h+var_5C]\nmov ebx, [rsp+68h+var_54]\nxchg ax, ax\nloc_16B0:\nadd edx, 1\nsub [rsp+68h+var_58], edx\nmov eax, [rsp+68h+var_58]\nadd [rsp+68h+var_48], ebx\nlea r13d, [rax-1]\ncmp r13d, 1\nja loc_1460\nmov r15d, [rsp+68h+var_48]\nmov r14d, [rsp+68h+var_40]\nnop word ptr [rax+rax+00000000h]\nloc_16E0:\nlea ebx, [r15+1]\nloc_16E4:\nxor edx, edx\nlea eax, [r14-1]\nmov [rsp+68h+var_40], ebx\nmov [rsp+68h+var_4C], eax\nmov [rsp+68h+var_48], edx\nloc_16F6:\nmov eax, [rsp+68h+var_4C]\nmov ecx, [rsp+68h+var_50]\nmov r13d, eax\ncmp ecx, 3\njz loc_1B00\nmov [rsp+68h+var_5C], eax\nlea eax, [rcx-2]\nmov [rsp+68h+var_54], 0\nmov [rsp+68h+var_58], eax\nloc_171D:\nmov r12d, [rsp+68h+var_58]\nmov eax, [rsp+68h+var_5C]\nmov ebx, r12d\ncmp eax, 3\njz loc_1A10\nxor r14d, r14d\nlea edi, [rax-2]\nloc_1738:\ncall sub_11F0\nmov ebp, eax\nmov edi, eax\ncall sub_11F0\nsub r12d, ebp\nlea edi, [r12-1]\nadd r14d, eax\ncmp edi, 1\nja short loc_1738\nlea r15d, [r14+1]\ncmp r14d, 1\njbe loc_1B58\nxor r12d, r12d\nmov edi, r14d\nloc_176A:\ncall sub_11F0\nmov ebp, eax\nmov edi, eax\ncall sub_11F0\nsub r15d, ebp\nlea edi, [r15-1]\nadd r12d, eax\ncmp edi, 1\nja short loc_176A\nadd r12d, 1\nloc_178B:\nmov eax, [rsp+68h+var_58]\nxor ebp, ebp\nlea edi, [rax-1]\nloc_1794:\ncall sub_11F0\nmov r14d, eax\nmov edi, eax\ncall sub_11F0\nsub ebx, r14d\nlea edi, [rbx-1]\nadd ebp, eax\ncmp edi, 1\nja short loc_1794\nlea edx, [rbp+1]\nsub [rsp+68h+var_5C], edx\nmov eax, [rsp+68h+var_5C]\nadd [rsp+68h+var_54], r12d\nsub eax, 1\nmov [rsp+68h+var_58], eax\ncmp eax, 1\nja loc_171D\nmov eax, [rsp+68h+var_54]\nlea ecx, [rax+1]\nmov [rsp+68h+var_5C], ecx\ncmp eax, 1\njbe loc_1A29\nnop dword ptr [rax+00h]\nloc_17E8:\nmov [rsp+68h+var_54], 0\nmov [rsp+68h+var_58], eax\nloc_17F4:\nmov r12d, [rsp+68h+var_58]\nmov eax, [rsp+68h+var_5C]\nmov ebx, r12d\ncmp eax, 3\njz loc_1A00\nxor r14d, r14d\nlea edi, [rax-2]\nloc_180F:\ncall sub_11F0\nmov ebp, eax\nmov edi, eax\ncall sub_11F0\nsub r12d, ebp\nlea edi, [r12-1]\nadd r14d, eax\ncmp edi, 1\nja short loc_180F\nlea r12d, [r14+1]\ncmp r14d, 1\njbe loc_1B48\nxor r15d, r15d\nmov edi, r14d\nloc_1841:\ncall sub_11F0\nmov ebp, eax\nmov edi, eax\ncall sub_11F0\nsub r12d, ebp\nlea edi, [r12-1]\nadd r15d, eax\ncmp edi, 1\nja short loc_1841\nlea r14d, [r15+1]\nloc_1863:\nmov eax, [rsp+68h+var_58]\nxor ebp, ebp\nlea edi, [rax-1]\nloc_186C:\ncall sub_11F0\nmov r12d, eax\nmov edi, eax\ncall sub_11F0\nsub ebx, r12d\nlea edi, [rbx-1]\nadd ebp, eax\ncmp edi, 1\nja short loc_186C\nlea edx, [rbp+1]\nsub [rsp+68h+var_5C], edx\nmov eax, [rsp+68h+var_5C]\nadd [rsp+68h+var_54], r14d\nsub eax, 1\nmov [rsp+68h+var_58], eax\ncmp eax, 1\nja loc_17F4\nnop dword ptr [rax+rax+00000000h]\nloc_18B0:\nmov eax, [rsp+68h+var_54]\nadd eax, 1\nmov [rsp+68h+var_54], eax\nloc_18BB:\nmov eax, [rsp+68h+var_4C]\nmov [rsp+68h+var_58], 0\nsub eax, 1\nmov [rsp+68h+var_5C], eax\nloc_18CE:\nmov r14d, [rsp+68h+var_5C]\nmov ebx, r14d\ncmp r13d, 3\njz loc_19F0\nxor r12d, r12d\nlea edi, [r13-2]\nloc_18E7:\ncall sub_11F0\nmov ebp, eax\nmov edi, eax\ncall sub_11F0\nsub r14d, ebp\nlea edi, [r14-1]\nadd r12d, eax\ncmp edi, 1\nja short loc_18E7\nlea r14d, [r12+1]\ncmp r12d, 1\njbe loc_1B38\nxor r15d, r15d\nmov edi, r12d\nloc_1919:\ncall sub_11F0\nmov ebp, eax\nmov edi, eax\ncall sub_11F0\nsub r14d, ebp\nlea edi, [r14-1]\nadd r15d, eax\ncmp edi, 1\nja short loc_1919\nlea ebp, [r15+1]\nloc_193A:\nmov eax, [rsp+68h+var_5C]\nxor r15d, r15d\nlea edi, [rax-1]\nloc_1944:\ncall sub_11F0\nmov r14d, eax\nmov edi, eax\ncall sub_11F0\nsub ebx, r14d\nlea edi, [rbx-1]\nadd r15d, eax\ncmp edi, 1\nja short loc_1944\nlea edx, [r15+1]\nadd [rsp+68h+var_58], ebp\nsub r13d, edx\nlea eax, [r13-1]\nmov [rsp+68h+var_5C], eax\ncmp eax, 1\nja loc_18CE\nnop dword ptr [rax]\nloc_1980:\nmov r12d, [rsp+68h+var_58]\nmov ecx, [rsp+68h+var_54]\nadd [rsp+68h+var_48], ecx\nadd r12d, 1\nsub [rsp+68h+var_50], r12d\nmov eax, [rsp+68h+var_50]\nsub eax, 1\nmov [rsp+68h+var_4C], eax\ncmp eax, 1\nja loc_16F6\nmov edx, [rsp+68h+var_48]\nmov ebx, [rsp+68h+var_40]\nnop word ptr [rax+rax+00h]\nloc_19B8:\nadd edx, 1\nsub [rsp+68h+var_44], edx\nmov eax, [rsp+68h+var_44]\nadd [rsp+68h+var_3C], ebx\nlea r14d, [rax-1]\ncmp r14d, 1\nja loc_1222\nmov ebp, [rsp+68h+var_3C]\nlea eax, [rbp+1]\nloc_19DC:\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_19F0:\nadd [rsp+68h+var_58], 1\njmp short loc_1980\nloc_1A00:\nadd [rsp+68h+var_54], 1\njmp loc_18B0\nloc_1A10:\nadd [rsp+68h+var_54], 1\nmov eax, [rsp+68h+var_54]\nlea ecx, [rax+1]\nmov [rsp+68h+var_5C], ecx\ncmp eax, 1\nja loc_17E8\nloc_1A29:\nmov [rsp+68h+var_54], 1\njmp loc_18BB\nloc_1A40:\nmov edx, [rsp+68h+var_5C]\nmov ebx, [rsp+68h+var_54]\nadd edx, 1\njmp loc_16B0\nloc_1A50:\nmov edx, r15d\nmov r12d, [rsp+68h+var_54]\nmov r13d, [rsp+68h+var_4C]\nadd edx, ebx\njmp loc_15F0\nloc_1A68:\nadd r14d, r15d\nmov r12d, [rsp+68h+var_54]\nmov r13d, [rsp+68h+var_4C]\nlea r15d, [r14+1]\ncmp r14d, 1\nja loc_1530\nloc_1A83:\nmov ebx, 1\njmp loc_15F3\nloc_1A90:\nmov ebp, [rsp+68h+var_54]\nmov ebx, [rsp+68h+var_4C]\nadd r15d, r12d\njmp loc_13B0\nloc_1AA0:\nmov ecx, r12d\nmov ebp, [rsp+68h+var_54]\nmov ebx, [rsp+68h+var_4C]\nadd ecx, r13d\nlea r14d, [rcx+1]\ncmp ecx, 1\nja loc_1310\nloc_1ABB:\nmov r13d, 1\njmp loc_13B4\nloc_1AD0:\nmov ebx, [rsp+68h+var_48]\nmov r14d, [rsp+68h+var_40]\nadd ebx, 1\nlea eax, [rbx+1]\nmov [rsp+68h+var_58], eax\ncmp ebx, 1\nja loc_1450\nloc_1AEC:\nmov ebx, 1\njmp loc_16E4\nloc_1B00:\nmov edx, [rsp+68h+var_48]\nmov ebx, [rsp+68h+var_40]\nadd edx, 1\njmp loc_19B8\nloc_1B10:\nmov r15d, [rsp+68h+var_48]\nmov r14d, [rsp+68h+var_40]\nadd r15d, 1\njmp loc_16E0\nloc_1B28:\nmov r15d, 1\njmp loc_166A\nloc_1B38:\nmov ebp, 1\njmp loc_193A\nloc_1B48:\nmov r14d, 1\njmp loc_1863\nloc_1B58:\nmov r12d, 1\njmp loc_178B\nloc_1B63:\nmov ebp, [rsp+68h+var_3C]\nadd rsp, 38h\npop rbx\nadd ebp, 1\nlea eax, [rbp+1]\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1B7C:\nmov r13d, 1\njmp loc_12B5\nloc_1B87:\nmov r12d, 1\njmp loc_1365\nloc_1B92:\nmov r14d, 1\njmp loc_1401\nloc_1B9D:\nmov r15d, 1\njmp loc_14CC\nloc_1BA8:\nmov ebx, 1\njmp loc_1593", + "ida_strip_pseudo": "__int64 __fastcall sub_11F0(int a1)\n{\n __int64 result; // rax\n int v2; // r14d\n int v3; // ebx\n int v4; // r14d\n unsigned int v5; // r12d\n unsigned int v6; // ebx\n unsigned int v7; // ebp\n int v8; // r13d\n int v9; // eax\n __int64 v10; // rdi\n int v11; // ebx\n __int64 v12; // r15\n int v13; // r13d\n int v14; // r15d\n __int64 v15; // rdi\n __int64 v16; // rbx\n unsigned int v17; // ecx\n int v18; // ebp\n int v19; // ebx\n int v20; // r14d\n int v21; // r15d\n unsigned int v22; // ebp\n int v23; // ebx\n unsigned int v24; // r13d\n int v25; // r12d\n int v26; // eax\n __int64 v27; // rdi\n int v28; // ebx\n __int64 v29; // r14\n int v30; // r12d\n int v31; // r14d\n __int64 v32; // rdi\n __int64 v33; // rbp\n int v34; // r13d\n int v35; // r12d\n __int64 v36; // rdi\n int v37; // eax\n int v38; // r14d\n __int64 v39; // rdi\n int v40; // r15d\n int v41; // r13d\n __int64 v42; // rbx\n int v43; // r14d\n unsigned int v44; // ebx\n int v45; // r14d\n unsigned int v46; // r13d\n unsigned int v47; // r14d\n unsigned int v48; // ebx\n unsigned int v49; // r12d\n unsigned int v50; // r13d\n int v51; // ebp\n int v52; // eax\n __int64 v53; // rdi\n int v54; // ebx\n __int64 v55; // r15\n int v56; // r15d\n int v57; // ebp\n __int64 v58; // rdi\n __int64 v59; // r12\n unsigned int v60; // r12d\n unsigned int v61; // r13d\n unsigned int v62; // r15d\n unsigned int v63; // r12d\n int v64; // r15d\n unsigned int v65; // r13d\n unsigned int v66; // ebp\n int v67; // r14d\n int v68; // eax\n __int64 v69; // rdi\n int v70; // ebp\n __int64 v71; // rbx\n int v72; // ebx\n int v73; // r14d\n __int64 v74; // rdi\n __int64 v75; // r13\n int v76; // edx\n int v77; // ebx\n unsigned int v78; // r13d\n unsigned int v79; // ebp\n unsigned int v80; // ebx\n unsigned int v81; // r15d\n __int64 v82; // rdi\n __int64 v83; // r14\n unsigned int v84; // r14d\n int v85; // ebx\n __int64 v86; // rdi\n __int64 v87; // r15\n int v88; // r15d\n int v89; // ebx\n __int64 v90; // rdi\n __int64 v91; // r13\n int v92; // edx\n int v93; // ebx\n int v94; // r15d\n int v95; // ebx\n int v96; // r13d\n int v97; // r12d\n int v98; // ebx\n unsigned int v99; // r14d\n __int64 v100; // rdi\n __int64 v101; // rbp\n unsigned int v102; // r15d\n int v103; // r12d\n __int64 v104; // rdi\n __int64 v105; // rbp\n int v106; // r12d\n int v107; // ebp\n __int64 v108; // rdi\n __int64 v109; // r14\n unsigned int v110; // eax\n unsigned int v111; // r12d\n unsigned int v112; // ebx\n unsigned int v113; // r14d\n __int64 v114; // rdi\n __int64 v115; // rbp\n unsigned int v116; // r12d\n int v117; // r15d\n __int64 v118; // rdi\n __int64 v119; // rbp\n int v120; // r14d\n int v121; // ebp\n __int64 v122; // rdi\n __int64 v123; // r12\n int v124; // r14d\n int v125; // ebx\n unsigned int v126; // r12d\n __int64 v127; // rdi\n __int64 v128; // rbp\n unsigned int v129; // r14d\n int v130; // r15d\n __int64 v131; // rdi\n __int64 v132; // rbp\n int v133; // ebp\n int v134; // r15d\n __int64 v135; // rdi\n __int64 v136; // r14\n int v137; // edx\n int v138; // ebx\n unsigned int v139; // [rsp+Ch] [rbp-5Ch]\n int v140; // [rsp+Ch] [rbp-5Ch]\n int v141; // [rsp+Ch] [rbp-5Ch]\n unsigned int v142; // [rsp+Ch] [rbp-5Ch]\n int v143; // [rsp+Ch] [rbp-5Ch]\n int v144; // [rsp+Ch] [rbp-5Ch]\n unsigned int v145; // [rsp+Ch] [rbp-5Ch]\n int v146; // [rsp+Ch] [rbp-5Ch]\n int v147; // [rsp+10h] [rbp-58h]\n unsigned int v148; // [rsp+10h] [rbp-58h]\n int v149; // [rsp+10h] [rbp-58h]\n unsigned int v150; // [rsp+10h] [rbp-58h]\n int v151; // [rsp+10h] [rbp-58h]\n int v152; // [rsp+14h] [rbp-54h]\n int v153; // [rsp+14h] [rbp-54h]\n unsigned int v154; // [rsp+14h] [rbp-54h]\n unsigned int v155; // [rsp+14h] [rbp-54h]\n int v156; // [rsp+14h] [rbp-54h]\n unsigned int v157; // [rsp+14h] [rbp-54h]\n int v158; // [rsp+14h] [rbp-54h]\n int v159; // [rsp+14h] [rbp-54h]\n int v160; // [rsp+18h] [rbp-50h]\n int v161; // [rsp+1Ch] [rbp-4Ch]\n int v162; // [rsp+1Ch] [rbp-4Ch]\n unsigned int v163; // [rsp+1Ch] [rbp-4Ch]\n unsigned int v164; // [rsp+1Ch] [rbp-4Ch]\n int v165; // [rsp+1Ch] [rbp-4Ch]\n unsigned int v166; // [rsp+20h] [rbp-48h]\n int v167; // [rsp+20h] [rbp-48h]\n int v168; // [rsp+20h] [rbp-48h]\n int v169; // [rsp+24h] [rbp-44h]\n int v170; // [rsp+28h] [rbp-40h]\n int v171; // [rsp+28h] [rbp-40h]\n int v172; // [rsp+28h] [rbp-40h]\n int v173; // [rsp+2Ch] [rbp-3Ch]\n\n result = 1LL;\n if ( (unsigned int)(a1 - 1) > 1 )\n {\n v169 = a1;\n v2 = a1 - 1;\n v173 = 0;\n while ( 1 )\n {\n v160 = v2;\n if ( v169 == 3 )\n return (unsigned int)(v173 + 2);\n v147 = v2;\n v170 = v2;\n v166 = 0;\n v3 = v169 - 2;\n while ( v147 != 3 )\n {\n v152 = v3;\n v4 = v3;\n v161 = v3;\n v5 = 0;\n v6 = v147 - 2;\n while ( 1 )\n {\n v7 = v6;\n v8 = 0;\n v9 = sub_11F0(v6);\n v10 = (unsigned int)(v9 - 1);\n if ( (unsigned int)v10 <= 1 )\n {\n v13 = 1;\n }\n else\n {\n v139 = v6;\n v11 = v9;\n do\n {\n v12 = (unsigned int)sub_11F0(v10);\n v11 -= v12;\n v10 = (unsigned int)(v11 - 1);\n v8 += sub_11F0(v12);\n }\n while ( (unsigned int)v10 > 1 );\n v6 = v139;\n v13 = v8 + 1;\n }\n if ( v4 == 3 )\n break;\n v14 = 0;\n v15 = v6 - 1;\n do\n {\n v16 = (unsigned int)sub_11F0(v15);\n v7 -= v16;\n v15 = v7 - 1;\n v14 += sub_11F0(v16);\n }\n while ( (unsigned int)v15 > 1 );\n v5 += v13;\n v4 -= v14 + 1;\n v6 = v4 - 1;\n if ( (unsigned int)(v4 - 1) <= 1 )\n {\n v17 = v5;\n v18 = v152;\n v19 = v161;\n v20 = v5 + 1;\n if ( v5 > 1 )\n goto LABEL_16;\nLABEL_124:\n v34 = 1;\n goto LABEL_27;\n }\n }\n v18 = v152;\n v19 = v161;\n v17 = v13 + v5;\n v20 = v13 + v5 + 1;\n if ( v13 + v5 <= 1 )\n goto LABEL_124;\nLABEL_16:\n v153 = v18;\n v21 = 0;\n v22 = v17;\n v162 = v19;\n v23 = v20;\n while ( 1 )\n {\n v24 = v22;\n v25 = 0;\n v26 = sub_11F0(v22);\n v27 = (unsigned int)(v26 - 1);\n if ( (unsigned int)v27 <= 1 )\n {\n v30 = 1;\n }\n else\n {\n v140 = v23;\n v28 = v26;\n do\n {\n v29 = (unsigned int)sub_11F0(v27);\n v28 -= v29;\n v27 = (unsigned int)(v28 - 1);\n v25 += sub_11F0(v29);\n }\n while ( (unsigned int)v27 > 1 );\n v23 = v140;\n v30 = v25 + 1;\n }\n if ( v23 == 3 )\n break;\n v31 = 0;\n v32 = v22 - 1;\n do\n {\n v33 = (unsigned int)sub_11F0(v32);\n v24 -= v33;\n v32 = v24 - 1;\n v31 += sub_11F0(v33);\n }\n while ( (unsigned int)v32 > 1 );\n v21 += v30;\n v23 -= v31 + 1;\n v22 = v23 - 1;\n if ( (unsigned int)(v23 - 1) <= 1 )\n {\n v18 = v153;\n v19 = v162;\n goto LABEL_26;\n }\n }\n v18 = v153;\n v19 = v162;\n v21 += v30;\nLABEL_26:\n v34 = v21 + 1;\nLABEL_27:\n v141 = v34;\n v35 = 0;\n v36 = (unsigned int)(v19 - 1);\n do\n {\n v37 = sub_11F0(v36);\n v38 = 0;\n v39 = (unsigned int)(v37 - 1);\n v40 = v37;\n v41 = v37;\n if ( (unsigned int)v39 <= 1 )\n {\n v43 = 1;\n }\n else\n {\n do\n {\n v42 = (unsigned int)sub_11F0(v39);\n v41 -= v42;\n v39 = (unsigned int)(v41 - 1);\n v38 += sub_11F0(v42);\n }\n while ( (unsigned int)v39 > 1 );\n v43 = v38 + 1;\n }\n v18 -= v40;\n v35 += v43;\n v36 = (unsigned int)(v18 - 1);\n }\n while ( (unsigned int)v36 > 1 );\n v147 -= v35 + 1;\n v166 += v141;\n v3 = v147 - 1;\n if ( (unsigned int)(v147 - 1) <= 1 )\n {\n v44 = v166;\n v45 = v170;\n v148 = v166 + 1;\n if ( v166 > 1 )\n goto LABEL_34;\nLABEL_126:\n v95 = 1;\n goto LABEL_72;\n }\n }\n v45 = v170;\n v44 = v166 + 1;\n v148 = v166 + 2;\n if ( v166 + 1 <= 1 )\n goto LABEL_126;\nLABEL_34:\n v171 = v45;\n v46 = v44;\n v167 = 0;\n while ( v148 != 3 )\n {\n v154 = v46;\n v47 = 0;\n v48 = v46;\n v163 = v46;\n v49 = v148 - 2;\n while ( 1 )\n {\n v50 = v49;\n v51 = 0;\n v52 = sub_11F0(v49);\n v53 = (unsigned int)(v52 - 1);\n if ( (unsigned int)v53 <= 1 )\n {\n v56 = 1;\n }\n else\n {\n v142 = v48;\n v54 = v52;\n do\n {\n v55 = (unsigned int)sub_11F0(v53);\n v54 -= v55;\n v53 = (unsigned int)(v54 - 1);\n v51 += sub_11F0(v55);\n }\n while ( (unsigned int)v53 > 1 );\n v48 = v142;\n v56 = v51 + 1;\n }\n if ( v48 == 3 )\n break;\n v57 = 0;\n v58 = v49 - 1;\n do\n {\n v59 = (unsigned int)sub_11F0(v58);\n v50 -= v59;\n v58 = v50 - 1;\n v57 += sub_11F0(v59);\n }\n while ( (unsigned int)v58 > 1 );\n v47 += v56;\n v48 -= v57 + 1;\n v49 = v48 - 1;\n if ( v48 - 1 <= 1 )\n {\n v60 = v154;\n v61 = v163;\n v62 = v47 + 1;\n if ( v47 > 1 )\n goto LABEL_46;\nLABEL_121:\n v77 = 1;\n goto LABEL_57;\n }\n }\n v47 += v56;\n v60 = v154;\n v61 = v163;\n v62 = v47 + 1;\n if ( v47 <= 1 )\n goto LABEL_121;\nLABEL_46:\n v155 = v60;\n v63 = v62;\n v164 = v61;\n v64 = 0;\n v65 = v47;\n while ( 1 )\n {\n v66 = v65;\n v67 = 0;\n v68 = sub_11F0(v65);\n v69 = (unsigned int)(v68 - 1);\n if ( (unsigned int)v69 <= 1 )\n {\n v72 = 1;\n }\n else\n {\n v70 = v68;\n do\n {\n v71 = (unsigned int)sub_11F0(v69);\n v70 -= v71;\n v69 = (unsigned int)(v70 - 1);\n v67 += sub_11F0(v71);\n }\n while ( (unsigned int)v69 > 1 );\n v66 = v65;\n v72 = v67 + 1;\n }\n if ( v63 == 3 )\n break;\n v73 = 0;\n v74 = v65 - 1;\n do\n {\n v75 = (unsigned int)sub_11F0(v74);\n v66 -= v75;\n v74 = v66 - 1;\n v73 += sub_11F0(v75);\n }\n while ( (unsigned int)v74 > 1 );\n v64 += v72;\n v63 -= v73 + 1;\n v65 = v63 - 1;\n if ( v63 - 1 <= 1 )\n {\n v60 = v155;\n v61 = v164;\n v76 = v64;\n goto LABEL_56;\n }\n }\n v60 = v155;\n v61 = v164;\n v76 = v72 + v64;\nLABEL_56:\n v77 = v76 + 1;\nLABEL_57:\n v156 = v77;\n v78 = v61 - 1;\n v143 = 0;\n while ( 1 )\n {\n v79 = v78;\n if ( v60 == 3 )\n break;\n v80 = v78;\n v81 = 0;\n v82 = v60 - 2;\n do\n {\n v83 = (unsigned int)sub_11F0(v82);\n v80 -= v83;\n v82 = v80 - 1;\n v81 += sub_11F0(v83);\n }\n while ( (unsigned int)v82 > 1 );\n v84 = v81 + 1;\n if ( v81 <= 1 )\n {\n v88 = 1;\n }\n else\n {\n v85 = 0;\n v86 = v81;\n do\n {\n v87 = (unsigned int)sub_11F0(v86);\n v84 -= v87;\n v86 = v84 - 1;\n v85 += sub_11F0(v87);\n }\n while ( (unsigned int)v86 > 1 );\n v88 = v85 + 1;\n }\n v89 = 0;\n v90 = v78 - 1;\n do\n {\n v91 = (unsigned int)sub_11F0(v90);\n v79 -= v91;\n v90 = v79 - 1;\n v89 += sub_11F0(v91);\n }\n while ( (unsigned int)v90 > 1 );\n v143 += v88;\n v60 -= v89 + 1;\n v78 = v60 - 1;\n if ( v60 - 1 <= 1 )\n {\n v92 = v143;\n v93 = v156;\n goto LABEL_69;\n }\n }\n v93 = v156;\n v92 = v143 + 1;\nLABEL_69:\n v148 -= v92 + 1;\n v167 += v93;\n v46 = v148 - 1;\n if ( v148 - 1 <= 1 )\n {\n v94 = v167;\n v45 = v171;\n goto LABEL_71;\n }\n }\n v45 = v171;\n v94 = v167 + 1;\nLABEL_71:\n v95 = v94 + 1;\nLABEL_72:\n v172 = v95;\n v165 = v45 - 1;\n v168 = 0;\n while ( 1 )\n {\n v96 = v165;\n if ( v160 == 3 )\n break;\n v144 = v165;\n v157 = 0;\n v149 = v160 - 2;\n while ( 1 )\n {\n v97 = v149;\n v98 = v149;\n if ( v144 == 3 )\n break;\n v99 = 0;\n v100 = (unsigned int)(v144 - 2);\n do\n {\n v101 = (unsigned int)sub_11F0(v100);\n v97 -= v101;\n v100 = (unsigned int)(v97 - 1);\n v99 += sub_11F0(v101);\n }\n while ( (unsigned int)v100 > 1 );\n v102 = v99 + 1;\n if ( v99 <= 1 )\n {\n v106 = 1;\n }\n else\n {\n v103 = 0;\n v104 = v99;\n do\n {\n v105 = (unsigned int)sub_11F0(v104);\n v102 -= v105;\n v104 = v102 - 1;\n v103 += sub_11F0(v105);\n }\n while ( (unsigned int)v104 > 1 );\n v106 = v103 + 1;\n }\n v107 = 0;\n v108 = (unsigned int)(v149 - 1);\n do\n {\n v109 = (unsigned int)sub_11F0(v108);\n v98 -= v109;\n v108 = (unsigned int)(v98 - 1);\n v107 += sub_11F0(v109);\n }\n while ( (unsigned int)v108 > 1 );\n v144 -= v107 + 1;\n v157 += v106;\n v149 = v144 - 1;\n if ( (unsigned int)(v144 - 1) <= 1 )\n {\n v110 = v157;\n v145 = v157 + 1;\n if ( v157 > 1 )\n goto LABEL_86;\nLABEL_117:\n v159 = 1;\n goto LABEL_98;\n }\n }\n v110 = v157 + 1;\n v145 = v157 + 2;\n if ( v157 + 1 <= 1 )\n goto LABEL_117;\nLABEL_86:\n v158 = 0;\n v150 = v110;\n while ( 1 )\n {\n v111 = v150;\n v112 = v150;\n if ( v145 == 3 )\n break;\n v113 = 0;\n v114 = v145 - 2;\n do\n {\n v115 = (unsigned int)sub_11F0(v114);\n v111 -= v115;\n v114 = v111 - 1;\n v113 += sub_11F0(v115);\n }\n while ( (unsigned int)v114 > 1 );\n v116 = v113 + 1;\n if ( v113 <= 1 )\n {\n v120 = 1;\n }\n else\n {\n v117 = 0;\n v118 = v113;\n do\n {\n v119 = (unsigned int)sub_11F0(v118);\n v116 -= v119;\n v118 = v116 - 1;\n v117 += sub_11F0(v119);\n }\n while ( (unsigned int)v118 > 1 );\n v120 = v117 + 1;\n }\n v121 = 0;\n v122 = v150 - 1;\n do\n {\n v123 = (unsigned int)sub_11F0(v122);\n v112 -= v123;\n v122 = v112 - 1;\n v121 += sub_11F0(v123);\n }\n while ( (unsigned int)v122 > 1 );\n v145 -= v121 + 1;\n v158 += v120;\n v150 = v145 - 1;\n if ( v145 - 1 <= 1 )\n goto LABEL_97;\n }\n ++v158;\nLABEL_97:\n v159 = v158 + 1;\nLABEL_98:\n v151 = 0;\n v146 = v165 - 1;\n while ( 1 )\n {\n v124 = v146;\n v125 = v146;\n if ( v96 == 3 )\n break;\n v126 = 0;\n v127 = (unsigned int)(v96 - 2);\n do\n {\n v128 = (unsigned int)sub_11F0(v127);\n v124 -= v128;\n v127 = (unsigned int)(v124 - 1);\n v126 += sub_11F0(v128);\n }\n while ( (unsigned int)v127 > 1 );\n v129 = v126 + 1;\n if ( v126 <= 1 )\n {\n v133 = 1;\n }\n else\n {\n v130 = 0;\n v131 = v126;\n do\n {\n v132 = (unsigned int)sub_11F0(v131);\n v129 -= v132;\n v131 = v129 - 1;\n v130 += sub_11F0(v132);\n }\n while ( (unsigned int)v131 > 1 );\n v133 = v130 + 1;\n }\n v134 = 0;\n v135 = (unsigned int)(v146 - 1);\n do\n {\n v136 = (unsigned int)sub_11F0(v135);\n v125 -= v136;\n v135 = (unsigned int)(v125 - 1);\n v134 += sub_11F0(v136);\n }\n while ( (unsigned int)v135 > 1 );\n v151 += v133;\n v96 -= v134 + 1;\n v146 = v96 - 1;\n if ( (unsigned int)(v96 - 1) <= 1 )\n goto LABEL_109;\n }\n ++v151;\nLABEL_109:\n v168 += v159;\n v160 -= v151 + 1;\n v165 = v160 - 1;\n if ( (unsigned int)(v160 - 1) <= 1 )\n {\n v137 = v168;\n v138 = v172;\n goto LABEL_111;\n }\n }\n v138 = v172;\n v137 = v168 + 1;\nLABEL_111:\n v169 -= v137 + 1;\n v173 += v138;\n v2 = v169 - 1;\n if ( (unsigned int)(v169 - 1) <= 1 )\n return (unsigned int)(v173 + 1);\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11F0(int a1) {\n long long result;\n int v2;\n int v3;\n int v4;\n unsigned int v5;\n unsigned int v6;\n unsigned int v7;\n int v8;\n int v9;\n long long v10;\n int v11;\n long long v12;\n int v13;\n int v14;\n long long v15;\n long long v16;\n unsigned int v17;\n int v18;\n int v19;\n int v20;\n int v21;\n unsigned int v22;\n int v23;\n unsigned int v24;\n int v25;\n int v26;\n long long v27;\n int v28;\n long long v29;\n int v30;\n int v31;\n long long v32;\n long long v33;\n int v34;\n int v35;\n long long v36;\n int v37;\n int v38;\n long long v39;\n int v40;\n int v41;\n long long v42;\n int v43;\n unsigned int v44;\n int v45;\n unsigned int v46;\n unsigned int v47;\n unsigned int v48;\n unsigned int v49;\n unsigned int v50;\n int v51;\n int v52;\n long long v53;\n int v54;\n long long v55;\n int v56;\n int v57;\n long long v58;\n long long v59;\n unsigned int v60;\n unsigned int v61;\n unsigned int v62;\n unsigned int v63;\n int v64;\n unsigned int v65;\n unsigned int v66;\n int v67;\n int v68;\n long long v69;\n int v70;\n long long v71;\n int v72;\n int v73;\n long long v74;\n long long v75;\n int v76;\n int v77;\n unsigned int v78;\n unsigned int v79;\n unsigned int v80;\n unsigned int v81;\n long long v82;\n long long v83;\n unsigned int v84;\n int v85;\n long long v86;\n long long v87;\n int v88;\n int v89;\n long long v90;\n long long v91;\n int v92;\n int v93;\n int v94;\n int v95;\n int v96;\n int v97;\n int v98;\n unsigned int v99;\n long long v100;\n long long v101;\n unsigned int v102;\n int v103;\n long long v104;\n long long v105;\n int v106;\n int v107;\n long long v108;\n long long v109;\n unsigned int v110;\n unsigned int v111;\n unsigned int v112;\n unsigned int v113;\n long long v114;\n long long v115;\n unsigned int v116;\n int v117;\n long long v118;\n long long v119;\n int v120;\n int v121;\n long long v122;\n long long v123;\n int v124;\n int v125;\n unsigned int v126;\n long long v127;\n long long v128;\n unsigned int v129;\n int v130;\n long long v131;\n long long v132;\n int v133;\n int v134;\n long long v135;\n long long v136;\n int v137;\n int v138;\n unsigned int v139;\n int v140;\n int v141;\n unsigned int v142;\n int v143;\n int v144;\n unsigned int v145;\n int v146;\n int v147;\n unsigned int v148;\n int v149;\n unsigned int v150;\n int v151;\n int v152;\n int v153;\n unsigned int v154;\n unsigned int v155;\n int v156;\n unsigned int v157;\n int v158;\n int v159;\n int v160;\n int v161;\n int v162;\n unsigned int v163;\n unsigned int v164;\n int v165;\n unsigned int v166;\n int v167;\n int v168;\n int v169;\n int v170;\n int v171;\n int v172;\n int v173;\n result = 1LL;\n if ((unsigned int)(a1 - 1) > 1) {\n v169 = a1;\n v2 = a1 - 1;\n v173 = 0;\n while (1) {\n v160 = v2;\n if (v169 == 3) return (unsigned int)(v173 + 2);\n v147 = v2;\n v170 = v2;\n v166 = 0;\n v3 = v169 - 2;\n while (v147 != 3) {\n v152 = v3;\n v4 = v3;\n v161 = v3;\n v5 = 0;\n v6 = v147 - 2;\n while (1) {\n v7 = v6;\n v8 = 0;\n v9 = sub_11F0(v6);\n v10 = (unsigned int)(v9 - 1);\n if ((unsigned int)v10 <= 1) {\n v13 = 1;\n } else {\n v139 = v6;\n v11 = v9;\n do {\n v12 = (unsigned int)sub_11F0(v10);\n v11 -= v12;\n v10 = (unsigned int)(v11 - 1);\n v8 += sub_11F0(v12);\n } while ((unsigned int)v10 > 1);\n v6 = v139;\n v13 = v8 + 1;\n }\n if (v4 == 3) break;\n v14 = 0;\n v15 = v6 - 1;\n do {\n v16 = (unsigned int)sub_11F0(v15);\n v7 -= v16;\n v15 = v7 - 1;\n v14 += sub_11F0(v16);\n } while ((unsigned int)v15 > 1);\n v5 += v13;\n v4 -= v14 + 1;\n v6 = v4 - 1;\n if ((unsigned int)(v4 - 1) <= 1) {\n v17 = v5;\n v18 = v152;\n v19 = v161;\n v20 = v5 + 1;\n if (v5 > 1) goto LABEL_16;\n LABEL_124:\n v34 = 1;\n goto LABEL_27;\n }\n }\n v18 = v152;\n v19 = v161;\n v17 = v13 + v5;\n v20 = v13 + v5 + 1;\n if (v13 + v5 <= 1) goto LABEL_124;\n LABEL_16:\n v153 = v18;\n v21 = 0;\n v22 = v17;\n v162 = v19;\n v23 = v20;\n while (1) {\n v24 = v22;\n v25 = 0;\n v26 = sub_11F0(v22);\n v27 = (unsigned int)(v26 - 1);\n if ((unsigned int)v27 <= 1) {\n v30 = 1;\n } else {\n v140 = v23;\n v28 = v26;\n do {\n v29 = (unsigned int)sub_11F0(v27);\n v28 -= v29;\n v27 = (unsigned int)(v28 - 1);\n v25 += sub_11F0(v29);\n } while ((unsigned int)v27 > 1);\n v23 = v140;\n v30 = v25 + 1;\n }\n if (v23 == 3) break;\n v31 = 0;\n v32 = v22 - 1;\n do {\n v33 = (unsigned int)sub_11F0(v32);\n v24 -= v33;\n v32 = v24 - 1;\n v31 += sub_11F0(v33);\n } while ((unsigned int)v32 > 1);\n v21 += v30;\n v23 -= v31 + 1;\n v22 = v23 - 1;\n if ((unsigned int)(v23 - 1) <= 1) {\n v18 = v153;\n v19 = v162;\n goto LABEL_26;\n }\n }\n v18 = v153;\n v19 = v162;\n v21 += v30;\n LABEL_26:\n v34 = v21 + 1;\n LABEL_27:\n v141 = v34;\n v35 = 0;\n v36 = (unsigned int)(v19 - 1);\n do {\n v37 = sub_11F0(v36);\n v38 = 0;\n v39 = (unsigned int)(v37 - 1);\n v40 = v37;\n v41 = v37;\n if ((unsigned int)v39 <= 1) {\n v43 = 1;\n } else {\n do {\n v42 = (unsigned int)sub_11F0(v39);\n v41 -= v42;\n v39 = (unsigned int)(v41 - 1);\n v38 += sub_11F0(v42);\n } while ((unsigned int)v39 > 1);\n v43 = v38 + 1;\n }\n v18 -= v40;\n v35 += v43;\n v36 = (unsigned int)(v18 - 1);\n } while ((unsigned int)v36 > 1);\n v147 -= v35 + 1;\n v166 += v141;\n v3 = v147 - 1;\n if ((unsigned int)(v147 - 1) <= 1) {\n v44 = v166;\n v45 = v170;\n v148 = v166 + 1;\n if (v166 > 1) goto LABEL_34;\n LABEL_126:\n v95 = 1;\n goto LABEL_72;\n }\n }\n v45 = v170;\n v44 = v166 + 1;\n v148 = v166 + 2;\n if (v166 + 1 <= 1) goto LABEL_126;\n LABEL_34:\n v171 = v45;\n v46 = v44;\n v167 = 0;\n while (v148 != 3) {\n v154 = v46;\n v47 = 0;\n v48 = v46;\n v163 = v46;\n v49 = v148 - 2;\n while (1) {\n v50 = v49;\n v51 = 0;\n v52 = sub_11F0(v49);\n v53 = (unsigned int)(v52 - 1);\n if ((unsigned int)v53 <= 1) {\n v56 = 1;\n } else {\n v142 = v48;\n v54 = v52;\n do {\n v55 = (unsigned int)sub_11F0(v53);\n v54 -= v55;\n v53 = (unsigned int)(v54 - 1);\n v51 += sub_11F0(v55);\n } while ((unsigned int)v53 > 1);\n v48 = v142;\n v56 = v51 + 1;\n }\n if (v48 == 3) break;\n v57 = 0;\n v58 = v49 - 1;\n do {\n v59 = (unsigned int)sub_11F0(v58);\n v50 -= v59;\n v58 = v50 - 1;\n v57 += sub_11F0(v59);\n } while ((unsigned int)v58 > 1);\n v47 += v56;\n v48 -= v57 + 1;\n v49 = v48 - 1;\n if (v48 - 1 <= 1) {\n v60 = v154;\n v61 = v163;\n v62 = v47 + 1;\n if (v47 > 1) goto LABEL_46;\n LABEL_121:\n v77 = 1;\n goto LABEL_57;\n }\n }\n v47 += v56;\n v60 = v154;\n v61 = v163;\n v62 = v47 + 1;\n if (v47 <= 1) goto LABEL_121;\n LABEL_46:\n v155 = v60;\n v63 = v62;\n v164 = v61;\n v64 = 0;\n v65 = v47;\n while (1) {\n v66 = v65;\n v67 = 0;\n v68 = sub_11F0(v65);\n v69 = (unsigned int)(v68 - 1);\n if ((unsigned int)v69 <= 1) {\n v72 = 1;\n } else {\n v70 = v68;\n do {\n v71 = (unsigned int)sub_11F0(v69);\n v70 -= v71;\n v69 = (unsigned int)(v70 - 1);\n v67 += sub_11F0(v71);\n } while ((unsigned int)v69 > 1);\n v66 = v65;\n v72 = v67 + 1;\n }\n if (v63 == 3) break;\n v73 = 0;\n v74 = v65 - 1;\n do {\n v75 = (unsigned int)sub_11F0(v74);\n v66 -= v75;\n v74 = v66 - 1;\n v73 += sub_11F0(v75);\n } while ((unsigned int)v74 > 1);\n v64 += v72;\n v63 -= v73 + 1;\n v65 = v63 - 1;\n if (v63 - 1 <= 1) {\n v60 = v155;\n v61 = v164;\n v76 = v64;\n goto LABEL_56;\n }\n }\n v60 = v155;\n v61 = v164;\n v76 = v72 + v64;\n LABEL_56:\n v77 = v76 + 1;\n LABEL_57:\n v156 = v77;\n v78 = v61 - 1;\n v143 = 0;\n while (1) {\n v79 = v78;\n if (v60 == 3) break;\n v80 = v78;\n v81 = 0;\n v82 = v60 - 2;\n do {\n v83 = (unsigned int)sub_11F0(v82);\n v80 -= v83;\n v82 = v80 - 1;\n v81 += sub_11F0(v83);\n } while ((unsigned int)v82 > 1);\n v84 = v81 + 1;\n if (v81 <= 1) {\n v88 = 1;\n } else {\n v85 = 0;\n v86 = v81;\n do {\n v87 = (unsigned int)sub_11F0(v86);\n v84 -= v87;\n v86 = v84 - 1;\n v85 += sub_11F0(v87);\n } while ((unsigned int)v86 > 1);\n v88 = v85 + 1;\n }\n v89 = 0;\n v90 = v78 - 1;\n do {\n v91 = (unsigned int)sub_11F0(v90);\n v79 -= v91;\n v90 = v79 - 1;\n v89 += sub_11F0(v91);\n } while ((unsigned int)v90 > 1);\n v143 += v88;\n v60 -= v89 + 1;\n v78 = v60 - 1;\n if (v60 - 1 <= 1) {\n v92 = v143;\n v93 = v156;\n goto LABEL_69;\n }\n }\n v93 = v156;\n v92 = v143 + 1;\n LABEL_69:\n v148 -= v92 + 1;\n v167 += v93;\n v46 = v148 - 1;\n if (v148 - 1 <= 1) {\n v94 = v167;\n v45 = v171;\n goto LABEL_71;\n }\n }\n v45 = v171;\n v94 = v167 + 1;\n LABEL_71:\n v95 = v94 + 1;\n LABEL_72:\n v172 = v95;\n v165 = v45 - 1;\n v168 = 0;\n while (1) {\n v96 = v165;\n if (v160 == 3) break;\n v144 = v165;\n v157 = 0;\n v149 = v160 - 2;\n while (1) {\n v97 = v149;\n v98 = v149;\n if (v144 == 3) break;\n v99 = 0;\n v100 = (unsigned int)(v144 - 2);\n do {\n v101 = (unsigned int)sub_11F0(v100);\n v97 -= v101;\n v100 = (unsigned int)(v97 - 1);\n v99 += sub_11F0(v101);\n } while ((unsigned int)v100 > 1);\n v102 = v99 + 1;\n if (v99 <= 1) {\n v106 = 1;\n } else {\n v103 = 0;\n v104 = v99;\n do {\n v105 = (unsigned int)sub_11F0(v104);\n v102 -= v105;\n v104 = v102 - 1;\n v103 += sub_11F0(v105);\n } while ((unsigned int)v104 > 1);\n v106 = v103 + 1;\n }\n v107 = 0;\n v108 = (unsigned int)(v149 - 1);\n do {\n v109 = (unsigned int)sub_11F0(v108);\n v98 -= v109;\n v108 = (unsigned int)(v98 - 1);\n v107 += sub_11F0(v109);\n } while ((unsigned int)v108 > 1);\n v144 -= v107 + 1;\n v157 += v106;\n v149 = v144 - 1;\n if ((unsigned int)(v144 - 1) <= 1) {\n v110 = v157;\n v145 = v157 + 1;\n if (v157 > 1) goto LABEL_86;\n LABEL_117:\n v159 = 1;\n goto LABEL_98;\n }\n }\n v110 = v157 + 1;\n v145 = v157 + 2;\n if (v157 + 1 <= 1) goto LABEL_117;\n LABEL_86:\n v158 = 0;\n v150 = v110;\n while (1) {\n v111 = v150;\n v112 = v150;\n if (v145 == 3) break;\n v113 = 0;\n v114 = v145 - 2;\n do {\n v115 = (unsigned int)sub_11F0(v114);\n v111 -= v115;\n v114 = v111 - 1;\n v113 += sub_11F0(v115);\n } while ((unsigned int)v114 > 1);\n v116 = v113 + 1;\n if (v113 <= 1) {\n v120 = 1;\n } else {\n v117 = 0;\n v118 = v113;\n do {\n v119 = (unsigned int)sub_11F0(v118);\n v116 -= v119;\n v118 = v116 - 1;\n v117 += sub_11F0(v119);\n } while ((unsigned int)v118 > 1);\n v120 = v117 + 1;\n }\n v121 = 0;\n v122 = v150 - 1;\n do {\n v123 = (unsigned int)sub_11F0(v122);\n v112 -= v123;\n v122 = v112 - 1;\n v121 += sub_11F0(v123);\n } while ((unsigned int)v122 > 1);\n v145 -= v121 + 1;\n v158 += v120;\n v150 = v145 - 1;\n if (v145 - 1 <= 1) goto LABEL_97;\n }\n ++v158;\n LABEL_97:\n v159 = v158 + 1;\n LABEL_98:\n v151 = 0;\n v146 = v165 - 1;\n while (1) {\n v124 = v146;\n v125 = v146;\n if (v96 == 3) break;\n v126 = 0;\n v127 = (unsigned int)(v96 - 2);\n do {\n v128 = (unsigned int)sub_11F0(v127);\n v124 -= v128;\n v127 = (unsigned int)(v124 - 1);\n v126 += sub_11F0(v128);\n } while ((unsigned int)v127 > 1);\n v129 = v126 + 1;\n if (v126 <= 1) {\n v133 = 1;\n } else {\n v130 = 0;\n v131 = v126;\n do {\n v132 = (unsigned int)sub_11F0(v131);\n v129 -= v132;\n v131 = v129 - 1;\n v130 += sub_11F0(v132);\n } while ((unsigned int)v131 > 1);\n v133 = v130 + 1;\n }\n v134 = 0;\n v135 = (unsigned int)(v146 - 1);\n do {\n v136 = (unsigned int)sub_11F0(v135);\n v125 -= v136;\n v135 = (unsigned int)(v125 - 1);\n v134 += sub_11F0(v136);\n } while ((unsigned int)v135 > 1);\n v151 += v133;\n v96 -= v134 + 1;\n v146 = v96 - 1;\n if ((unsigned int)(v96 - 1) <= 1) goto LABEL_109;\n }\n ++v151;\n LABEL_109:\n v168 += v159;\n v160 -= v151 + 1;\n v165 = v160 - 1;\n if ((unsigned int)(v160 - 1) <= 1) {\n v137 = v168;\n v138 = v172;\n goto LABEL_111;\n }\n }\n v138 = v172;\n v137 = v168 + 1;\n LABEL_111:\n v169 -= v137 + 1;\n v173 += v138;\n v2 = v169 - 1;\n if ((unsigned int)(v169 - 1) <= 1) return (unsigned int)(v173 + 1);\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n long long result;\n int v2;\n int v3;\n int v4;\n unsigned int v5;\n unsigned int v6;\n unsigned int v7;\n int v8;\n int v9;\n long long v10;\n int v11;\n long long v12;\n int v13;\n int v14;\n long long v15;\n long long v16;\n unsigned int v17;\n int v18;\n int v19;\n int v20;\n int v21;\n unsigned int v22;\n int v23;\n unsigned int v24;\n int v25;\n int v26;\n long long v27;\n int v28;\n long long v29;\n int v30;\n int v31;\n long long v32;\n long long v33;\n int v34;\n int v35;\n long long v36;\n int v37;\n int v38;\n long long v39;\n int v40;\n int v41;\n long long v42;\n int v43;\n unsigned int v44;\n int v45;\n unsigned int v46;\n unsigned int v47;\n unsigned int v48;\n unsigned int v49;\n unsigned int v50;\n int v51;\n int v52;\n long long v53;\n int v54;\n long long v55;\n int v56;\n int v57;\n long long v58;\n long long v59;\n unsigned int v60;\n unsigned int v61;\n unsigned int v62;\n unsigned int v63;\n int v64;\n unsigned int v65;\n unsigned int v66;\n int v67;\n int v68;\n long long v69;\n int v70;\n long long v71;\n int v72;\n int v73;\n long long v74;\n long long v75;\n int v76;\n int v77;\n unsigned int v78;\n unsigned int v79;\n unsigned int v80;\n unsigned int v81;\n long long v82;\n long long v83;\n unsigned int v84;\n int v85;\n long long v86;\n long long v87;\n int v88;\n int v89;\n long long v90;\n long long v91;\n int v92;\n int v93;\n int v94;\n int v95;\n int v96;\n int v97;\n int v98;\n unsigned int v99;\n long long v100;\n long long v101;\n unsigned int v102;\n int v103;\n long long v104;\n long long v105;\n int v106;\n int v107;\n long long v108;\n long long v109;\n unsigned int v110;\n unsigned int v111;\n unsigned int v112;\n unsigned int v113;\n long long v114;\n long long v115;\n unsigned int v116;\n int v117;\n long long v118;\n long long v119;\n int v120;\n int v121;\n long long v122;\n long long v123;\n int v124;\n int v125;\n unsigned int v126;\n long long v127;\n long long v128;\n unsigned int v129;\n int v130;\n long long v131;\n long long v132;\n int v133;\n int v134;\n long long v135;\n long long v136;\n int v137;\n int v138;\n unsigned int v139;\n int v140;\n int v141;\n unsigned int v142;\n int v143;\n int v144;\n unsigned int v145;\n int v146;\n int v147;\n unsigned int v148;\n int v149;\n unsigned int v150;\n int v151;\n int v152;\n int v153;\n unsigned int v154;\n unsigned int v155;\n int v156;\n unsigned int v157;\n int v158;\n int v159;\n int v160;\n int v161;\n int v162;\n unsigned int v163;\n unsigned int v164;\n int v165;\n unsigned int v166;\n int v167;\n int v168;\n int v169;\n int v170;\n int v171;\n int v172;\n int v173;\n result = 1LL;\n if ((unsigned int)(a1 - 1) > 1) {\n v169 = a1;\n v2 = a1 - 1;\n v173 = 0;\n while (1) {\n v160 = v2;\n if (v169 == 3) return (unsigned int)(v173 + 2);\n v147 = v2;\n v170 = v2;\n v166 = 0;\n v3 = v169 - 2;\n while (v147 != 3) {\n v152 = v3;\n v4 = v3;\n v161 = v3;\n v5 = 0;\n v6 = v147 - 2;\n while (1) {\n v7 = v6;\n v8 = 0;\n v9 = func0(v6);\n v10 = (unsigned int)(v9 - 1);\n if ((unsigned int)v10 <= 1) {\n v13 = 1;\n } else {\n v139 = v6;\n v11 = v9;\n do {\n v12 = (unsigned int)func0(v10);\n v11 -= v12;\n v10 = (unsigned int)(v11 - 1);\n v8 += func0(v12);\n } while ((unsigned int)v10 > 1);\n v6 = v139;\n v13 = v8 + 1;\n }\n if (v4 == 3) break;\n v14 = 0;\n v15 = v6 - 1;\n do {\n v16 = (unsigned int)func0(v15);\n v7 -= v16;\n v15 = v7 - 1;\n v14 += func0(v16);\n } while ((unsigned int)v15 > 1);\n v5 += v13;\n v4 -= v14 + 1;\n v6 = v4 - 1;\n if ((unsigned int)(v4 - 1) <= 1) {\n v17 = v5;\n v18 = v152;\n v19 = v161;\n v20 = v5 + 1;\n if (v5 > 1) goto LABEL_16;\n LABEL_124:\n v34 = 1;\n goto LABEL_27;\n }\n }\n v18 = v152;\n v19 = v161;\n v17 = v13 + v5;\n v20 = v13 + v5 + 1;\n if (v13 + v5 <= 1) goto LABEL_124;\n LABEL_16:\n v153 = v18;\n v21 = 0;\n v22 = v17;\n v162 = v19;\n v23 = v20;\n while (1) {\n v24 = v22;\n v25 = 0;\n v26 = func0(v22);\n v27 = (unsigned int)(v26 - 1);\n if ((unsigned int)v27 <= 1) {\n v30 = 1;\n } else {\n v140 = v23;\n v28 = v26;\n do {\n v29 = (unsigned int)func0(v27);\n v28 -= v29;\n v27 = (unsigned int)(v28 - 1);\n v25 += func0(v29);\n } while ((unsigned int)v27 > 1);\n v23 = v140;\n v30 = v25 + 1;\n }\n if (v23 == 3) break;\n v31 = 0;\n v32 = v22 - 1;\n do {\n v33 = (unsigned int)func0(v32);\n v24 -= v33;\n v32 = v24 - 1;\n v31 += func0(v33);\n } while ((unsigned int)v32 > 1);\n v21 += v30;\n v23 -= v31 + 1;\n v22 = v23 - 1;\n if ((unsigned int)(v23 - 1) <= 1) {\n v18 = v153;\n v19 = v162;\n goto LABEL_26;\n }\n }\n v18 = v153;\n v19 = v162;\n v21 += v30;\n LABEL_26:\n v34 = v21 + 1;\n LABEL_27:\n v141 = v34;\n v35 = 0;\n v36 = (unsigned int)(v19 - 1);\n do {\n v37 = func0(v36);\n v38 = 0;\n v39 = (unsigned int)(v37 - 1);\n v40 = v37;\n v41 = v37;\n if ((unsigned int)v39 <= 1) {\n v43 = 1;\n } else {\n do {\n v42 = (unsigned int)func0(v39);\n v41 -= v42;\n v39 = (unsigned int)(v41 - 1);\n v38 += func0(v42);\n } while ((unsigned int)v39 > 1);\n v43 = v38 + 1;\n }\n v18 -= v40;\n v35 += v43;\n v36 = (unsigned int)(v18 - 1);\n } while ((unsigned int)v36 > 1);\n v147 -= v35 + 1;\n v166 += v141;\n v3 = v147 - 1;\n if ((unsigned int)(v147 - 1) <= 1) {\n v44 = v166;\n v45 = v170;\n v148 = v166 + 1;\n if (v166 > 1) goto LABEL_34;\n LABEL_126:\n v95 = 1;\n goto LABEL_72;\n }\n }\n v45 = v170;\n v44 = v166 + 1;\n v148 = v166 + 2;\n if (v166 + 1 <= 1) goto LABEL_126;\n LABEL_34:\n v171 = v45;\n v46 = v44;\n v167 = 0;\n while (v148 != 3) {\n v154 = v46;\n v47 = 0;\n v48 = v46;\n v163 = v46;\n v49 = v148 - 2;\n while (1) {\n v50 = v49;\n v51 = 0;\n v52 = func0(v49);\n v53 = (unsigned int)(v52 - 1);\n if ((unsigned int)v53 <= 1) {\n v56 = 1;\n } else {\n v142 = v48;\n v54 = v52;\n do {\n v55 = (unsigned int)func0(v53);\n v54 -= v55;\n v53 = (unsigned int)(v54 - 1);\n v51 += func0(v55);\n } while ((unsigned int)v53 > 1);\n v48 = v142;\n v56 = v51 + 1;\n }\n if (v48 == 3) break;\n v57 = 0;\n v58 = v49 - 1;\n do {\n v59 = (unsigned int)func0(v58);\n v50 -= v59;\n v58 = v50 - 1;\n v57 += func0(v59);\n } while ((unsigned int)v58 > 1);\n v47 += v56;\n v48 -= v57 + 1;\n v49 = v48 - 1;\n if (v48 - 1 <= 1) {\n v60 = v154;\n v61 = v163;\n v62 = v47 + 1;\n if (v47 > 1) goto LABEL_46;\n LABEL_121:\n v77 = 1;\n goto LABEL_57;\n }\n }\n v47 += v56;\n v60 = v154;\n v61 = v163;\n v62 = v47 + 1;\n if (v47 <= 1) goto LABEL_121;\n LABEL_46:\n v155 = v60;\n v63 = v62;\n v164 = v61;\n v64 = 0;\n v65 = v47;\n while (1) {\n v66 = v65;\n v67 = 0;\n v68 = func0(v65);\n v69 = (unsigned int)(v68 - 1);\n if ((unsigned int)v69 <= 1) {\n v72 = 1;\n } else {\n v70 = v68;\n do {\n v71 = (unsigned int)func0(v69);\n v70 -= v71;\n v69 = (unsigned int)(v70 - 1);\n v67 += func0(v71);\n } while ((unsigned int)v69 > 1);\n v66 = v65;\n v72 = v67 + 1;\n }\n if (v63 == 3) break;\n v73 = 0;\n v74 = v65 - 1;\n do {\n v75 = (unsigned int)func0(v74);\n v66 -= v75;\n v74 = v66 - 1;\n v73 += func0(v75);\n } while ((unsigned int)v74 > 1);\n v64 += v72;\n v63 -= v73 + 1;\n v65 = v63 - 1;\n if (v63 - 1 <= 1) {\n v60 = v155;\n v61 = v164;\n v76 = v64;\n goto LABEL_56;\n }\n }\n v60 = v155;\n v61 = v164;\n v76 = v72 + v64;\n LABEL_56:\n v77 = v76 + 1;\n LABEL_57:\n v156 = v77;\n v78 = v61 - 1;\n v143 = 0;\n while (1) {\n v79 = v78;\n if (v60 == 3) break;\n v80 = v78;\n v81 = 0;\n v82 = v60 - 2;\n do {\n v83 = (unsigned int)func0(v82);\n v80 -= v83;\n v82 = v80 - 1;\n v81 += func0(v83);\n } while ((unsigned int)v82 > 1);\n v84 = v81 + 1;\n if (v81 <= 1) {\n v88 = 1;\n } else {\n v85 = 0;\n v86 = v81;\n do {\n v87 = (unsigned int)func0(v86);\n v84 -= v87;\n v86 = v84 - 1;\n v85 += func0(v87);\n } while ((unsigned int)v86 > 1);\n v88 = v85 + 1;\n }\n v89 = 0;\n v90 = v78 - 1;\n do {\n v91 = (unsigned int)func0(v90);\n v79 -= v91;\n v90 = v79 - 1;\n v89 += func0(v91);\n } while ((unsigned int)v90 > 1);\n v143 += v88;\n v60 -= v89 + 1;\n v78 = v60 - 1;\n if (v60 - 1 <= 1) {\n v92 = v143;\n v93 = v156;\n goto LABEL_69;\n }\n }\n v93 = v156;\n v92 = v143 + 1;\n LABEL_69:\n v148 -= v92 + 1;\n v167 += v93;\n v46 = v148 - 1;\n if (v148 - 1 <= 1) {\n v94 = v167;\n v45 = v171;\n goto LABEL_71;\n }\n }\n v45 = v171;\n v94 = v167 + 1;\n LABEL_71:\n v95 = v94 + 1;\n LABEL_72:\n v172 = v95;\n v165 = v45 - 1;\n v168 = 0;\n while (1) {\n v96 = v165;\n if (v160 == 3) break;\n v144 = v165;\n v157 = 0;\n v149 = v160 - 2;\n while (1) {\n v97 = v149;\n v98 = v149;\n if (v144 == 3) break;\n v99 = 0;\n v100 = (unsigned int)(v144 - 2);\n do {\n v101 = (unsigned int)func0(v100);\n v97 -= v101;\n v100 = (unsigned int)(v97 - 1);\n v99 += func0(v101);\n } while ((unsigned int)v100 > 1);\n v102 = v99 + 1;\n if (v99 <= 1) {\n v106 = 1;\n } else {\n v103 = 0;\n v104 = v99;\n do {\n v105 = (unsigned int)func0(v104);\n v102 -= v105;\n v104 = v102 - 1;\n v103 += func0(v105);\n } while ((unsigned int)v104 > 1);\n v106 = v103 + 1;\n }\n v107 = 0;\n v108 = (unsigned int)(v149 - 1);\n do {\n v109 = (unsigned int)func0(v108);\n v98 -= v109;\n v108 = (unsigned int)(v98 - 1);\n v107 += func0(v109);\n } while ((unsigned int)v108 > 1);\n v144 -= v107 + 1;\n v157 += v106;\n v149 = v144 - 1;\n if ((unsigned int)(v144 - 1) <= 1) {\n v110 = v157;\n v145 = v157 + 1;\n if (v157 > 1) goto LABEL_86;\n LABEL_117:\n v159 = 1;\n goto LABEL_98;\n }\n }\n v110 = v157 + 1;\n v145 = v157 + 2;\n if (v157 + 1 <= 1) goto LABEL_117;\n LABEL_86:\n v158 = 0;\n v150 = v110;\n while (1) {\n v111 = v150;\n v112 = v150;\n if (v145 == 3) break;\n v113 = 0;\n v114 = v145 - 2;\n do {\n v115 = (unsigned int)func0(v114);\n v111 -= v115;\n v114 = v111 - 1;\n v113 += func0(v115);\n } while ((unsigned int)v114 > 1);\n v116 = v113 + 1;\n if (v113 <= 1) {\n v120 = 1;\n } else {\n v117 = 0;\n v118 = v113;\n do {\n v119 = (unsigned int)func0(v118);\n v116 -= v119;\n v118 = v116 - 1;\n v117 += func0(v119);\n } while ((unsigned int)v118 > 1);\n v120 = v117 + 1;\n }\n v121 = 0;\n v122 = v150 - 1;\n do {\n v123 = (unsigned int)func0(v122);\n v112 -= v123;\n v122 = v112 - 1;\n v121 += func0(v123);\n } while ((unsigned int)v122 > 1);\n v145 -= v121 + 1;\n v158 += v120;\n v150 = v145 - 1;\n if (v145 - 1 <= 1) goto LABEL_97;\n }\n ++v158;\n LABEL_97:\n v159 = v158 + 1;\n LABEL_98:\n v151 = 0;\n v146 = v165 - 1;\n while (1) {\n v124 = v146;\n v125 = v146;\n if (v96 == 3) break;\n v126 = 0;\n v127 = (unsigned int)(v96 - 2);\n do {\n v128 = (unsigned int)func0(v127);\n v124 -= v128;\n v127 = (unsigned int)(v124 - 1);\n v126 += func0(v128);\n } while ((unsigned int)v127 > 1);\n v129 = v126 + 1;\n if (v126 <= 1) {\n v133 = 1;\n } else {\n v130 = 0;\n v131 = v126;\n do {\n v132 = (unsigned int)func0(v131);\n v129 -= v132;\n v131 = v129 - 1;\n v130 += func0(v132);\n } while ((unsigned int)v131 > 1);\n v133 = v130 + 1;\n }\n v134 = 0;\n v135 = (unsigned int)(v146 - 1);\n do {\n v136 = (unsigned int)func0(v135);\n v125 -= v136;\n v135 = (unsigned int)(v125 - 1);\n v134 += func0(v136);\n } while ((unsigned int)v135 > 1);\n v151 += v133;\n v96 -= v134 + 1;\n v146 = v96 - 1;\n if ((unsigned int)(v96 - 1) <= 1) goto LABEL_109;\n }\n ++v151;\n LABEL_109:\n v168 += v159;\n v160 -= v151 + 1;\n v165 = v160 - 1;\n if ((unsigned int)(v160 - 1) <= 1) {\n v137 = v168;\n v138 = v172;\n goto LABEL_111;\n }\n }\n v138 = v172;\n v137 = v168 + 1;\n LABEL_111:\n v169 -= v137 + 1;\n v173 += v138;\n v2 = v169 - 1;\n if ((unsigned int)(v169 - 1) <= 1) return (unsigned int)(v173 + 1);\n }\n }\n return result;\n}" + }, + { + "index": 84, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n == 1 || n == 2) {\n return 1;\n } else {\n return func0(func0(n - 1)) + func0(n - func0(n - 1));\n }\n}", + "test": "int main() {\n\n assert(func0(10) == 6);\n\n assert(func0(2) == 1);\n\n assert(func0(3) == 2);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov $0x1,%eax\npush %rbp\nmov %edi,%ebp\nsub $0x1,%edi\npush %rbx\ncmp $0x1,%edi\njbe 122a \nxor %r12d,%r12d\ncallq 11f0 \nmov %eax,%ebx\nmov %eax,%edi\ncallq 11f0 \nsub %ebx,%ebp\nlea -0x1(%rbp),%edi\nadd %eax,%r12d\ncmp $0x1,%edi\nja 120a \nlea 0x1(%r12),%eax\npop %rbx\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov eax, 1\npush r14\npush r13\npush r12\nlea r12d, [rdi-1]\npush rbp\npush rbx\nsub rsp, 38h\ncmp r12d, 1\njbe loc_19DC\nxor ebp, ebp\nmov [rsp+68h+var_44], edi\nmov r14d, r12d\nmov [rsp+68h+var_3C], ebp\nloc_1222:\nmov eax, [rsp+68h+var_44]\nmov [rsp+68h+var_50], r14d\ncmp eax, 3\njz loc_1B63\nmov [rsp+68h+var_58], r14d\nxor ebx, ebx\nsub eax, 2\nmov [rsp+68h+var_40], r14d\nmov [rsp+68h+var_48], ebx\nmov ebx, eax\nloc_1249:\nmov eax, [rsp+68h+var_58]\ncmp eax, 3\njz loc_1AD0\nxor ecx, ecx\nlea r15d, [rax-2]\nmov [rsp+68h+var_54], ebx\nmov r14d, ebx\nmov [rsp+68h+var_4C], ebx\nmov r12d, ecx\nmov ebx, r15d\nloc_126D:\nmov edi, ebx\nmov ebp, ebx\nxor r13d, r13d\ncall func0\nlea edi, [rax-1]\ncmp edi, 1\njbe loc_1B7C\nmov [rsp+68h+var_5C], ebx\nmov ebx, eax\nnop dword ptr [rax+rax+00h]\nloc_1290:\ncall func0\nmov r15d, eax\nmov edi, eax\ncall func0\nsub ebx, r15d\nlea edi, [rbx-1]\nadd r13d, eax\ncmp edi, 1\nja short loc_1290\nmov ebx, [rsp+68h+var_5C]\nadd r13d, 1\nloc_12B5:\ncmp r14d, 3\njz loc_1AA0\nxor r15d, r15d\nlea edi, [rbx-1]\nloc_12C5:\ncall func0\nmov ebx, eax\nmov edi, eax\ncall func0\nsub ebp, ebx\nlea edi, [rbp-1]\nadd r15d, eax\ncmp edi, 1\nja short loc_12C5\nadd r15d, 1\nadd r12d, r13d\nsub r14d, r15d\nlea ebx, [r14-1]\ncmp ebx, 1\nja loc_126D\nmov ecx, r12d\nmov ebp, [rsp+68h+var_54]\nmov ebx, [rsp+68h+var_4C]\nlea r14d, [rcx+1]\ncmp ecx, 1\njbe loc_1ABB\nnop\nloc_1310:\nmov [rsp+68h+var_54], ebp\nxor r15d, r15d\nmov ebp, ecx\nmov [rsp+68h+var_4C], ebx\nmov ebx, r14d\nloc_1320:\nmov edi, ebp\nmov r13d, ebp\nxor r12d, r12d\ncall func0\nlea edi, [rax-1]\ncmp edi, 1\njbe loc_1B87\nmov [rsp+68h+var_5C], ebx\nmov ebx, eax\nnop\nloc_1340:\ncall func0\nmov r14d, eax\nmov edi, eax\ncall func0\nsub ebx, r14d\nlea edi, [rbx-1]\nadd r12d, eax\ncmp edi, 1\nja short loc_1340\nmov ebx, [rsp+68h+var_5C]\nadd r12d, 1\nloc_1365:\ncmp ebx, 3\njz loc_1A90\nxor r14d, r14d\nlea edi, [rbp-1]\nloc_1374:\ncall func0\nmov ebp, eax\nmov edi, eax\ncall func0\nsub r13d, ebp\nlea edi, [r13-1]\nadd r14d, eax\ncmp edi, 1\nja short loc_1374\nlea edx, [r14+1]\nadd r15d, r12d\nsub ebx, edx\nlea ebp, [rbx-1]\ncmp ebp, 1\nja loc_1320\nmov ebp, [rsp+68h+var_54]\nmov ebx, [rsp+68h+var_4C]\nxchg ax, ax\nloc_13B0:\nlea r13d, [r15+1]\nloc_13B4:\nmov [rsp+68h+var_5C], r13d\nxor r12d, r12d\nlea edi, [rbx-1]\nloc_13BF:\ncall func0\nxor r14d, r14d\nlea edi, [rax-1]\nmov r15d, eax\nmov r13d, eax\ncmp edi, 1\njbe loc_1B92\nnop dword ptr [rax+00000000h]\nloc_13E0:\ncall func0\nmov ebx, eax\nmov edi, eax\ncall func0\nsub r13d, ebx\nlea edi, [r13-1]\nadd r14d, eax\ncmp edi, 1\nja short loc_13E0\nadd r14d, 1\nloc_1401:\nsub ebp, r15d\nadd r12d, r14d\nlea edi, [rbp-1]\ncmp edi, 1\nja short loc_13BF\nadd r12d, 1\nsub [rsp+68h+var_58], r12d\nmov eax, [rsp+68h+var_58]\nmov r13d, [rsp+68h+var_5C]\nadd [rsp+68h+var_48], r13d\nlea ebx, [rax-1]\ncmp ebx, 1\nja loc_1249\nmov ebx, [rsp+68h+var_48]\nmov r14d, [rsp+68h+var_40]\nlea eax, [rbx+1]\nmov [rsp+68h+var_58], eax\ncmp ebx, 1\njbe loc_1AEC\nnop dword ptr [rax+rax+00h]\nloc_1450:\nxor r15d, r15d\nmov [rsp+68h+var_40], r14d\nmov r13d, ebx\nmov [rsp+68h+var_48], r15d\nloc_1460:\nmov eax, [rsp+68h+var_58]\ncmp eax, 3\njz loc_1B10\nmov [rsp+68h+var_54], r13d\nlea ebp, [rax-2]\nxor r14d, r14d\nmov ebx, r13d\nmov [rsp+68h+var_4C], r13d\nmov r12d, ebp\nloc_1483:\nmov edi, r12d\nmov r13d, r12d\nxor ebp, ebp\ncall func0\nlea edi, [rax-1]\ncmp edi, 1\njbe loc_1B9D\nmov [rsp+68h+var_5C], ebx\nmov ebx, eax\nnop word ptr [rax+rax+00h]\nloc_14A8:\ncall func0\nmov r15d, eax\nmov edi, eax\ncall func0\nsub ebx, r15d\nlea edi, [rbx-1]\nadd ebp, eax\ncmp edi, 1\nja short loc_14A8\nmov ebx, [rsp+68h+var_5C]\nlea r15d, [rbp+1]\nloc_14CC:\ncmp ebx, 3\njz loc_1A68\nxor ebp, ebp\nlea edi, [r12-1]\nloc_14DC:\ncall func0\nmov r12d, eax\nmov edi, eax\ncall func0\nsub r13d, r12d\nlea edi, [r13-1]\nadd ebp, eax\ncmp edi, 1\nja short loc_14DC\nadd ebp, 1\nadd r14d, r15d\nsub ebx, ebp\nlea r12d, [rbx-1]\ncmp r12d, 1\nja loc_1483\nmov r12d, [rsp+68h+var_54]\nmov r13d, [rsp+68h+var_4C]\nlea r15d, [r14+1]\ncmp r14d, 1\njbe loc_1A83\nnop word ptr [rax+rax+00000000h]\nloc_1530:\nxor edx, edx\nmov [rsp+68h+var_54], r12d\nmov r12d, r15d\nmov [rsp+68h+var_4C], r13d\nmov r15d, edx\nmov r13d, r14d\nloc_1545:\nmov edi, r13d\nmov ebp, r13d\nxor r14d, r14d\ncall func0\nlea edi, [rax-1]\ncmp edi, 1\njbe loc_1BA8\nmov [rsp+68h+var_5C], r13d\nmov ebp, eax\nnop word ptr [rax+rax+00000000h]\nloc_1570:\ncall func0\nmov ebx, eax\nmov edi, eax\ncall func0\nsub ebp, ebx\nlea edi, [rbp-1]\nadd r14d, eax\ncmp edi, 1\nja short loc_1570\nmov ebp, [rsp+68h+var_5C]\nlea ebx, [r14+1]\nloc_1593:\ncmp r12d, 3\njz loc_1A50\nxor r14d, r14d\nlea edi, [r13-1]\nloc_15A4:\ncall func0\nmov r13d, eax\nmov edi, eax\ncall func0\nsub ebp, r13d\nlea edi, [rbp-1]\nadd r14d, eax\ncmp edi, 1\nja short loc_15A4\nlea ecx, [r14+1]\nadd r15d, ebx\nsub r12d, ecx\nlea r13d, [r12-1]\ncmp r13d, 1\nja loc_1545\nmov r12d, [rsp+68h+var_54]\nmov r13d, [rsp+68h+var_4C]\nmov edx, r15d\nnop word ptr [rax+rax+00000000h]\nloc_15F0:\nlea ebx, [rdx+1]\nloc_15F3:\nxor edx, edx\nmov [rsp+68h+var_54], ebx\nsub r13d, 1\nmov [rsp+68h+var_5C], edx\nloc_1601:\nmov ebp, r13d\ncmp r12d, 3\njz loc_1A40\nmov ebx, r13d\nxor r15d, r15d\nlea edi, [r12-2]\nloc_1619:\ncall func0\nmov r14d, eax\nmov edi, eax\ncall func0\nsub ebx, r14d\nlea edi, [rbx-1]\nadd r15d, eax\ncmp edi, 1\nja short loc_1619\nlea r14d, [r15+1]\ncmp r15d, 1\njbe loc_1B28\nxor ebx, ebx\nmov edi, r15d\nloc_1649:\ncall func0\nmov r15d, eax\nmov edi, eax\ncall func0\nsub r14d, r15d\nlea edi, [r14-1]\nadd ebx, eax\ncmp edi, 1\nja short loc_1649\nlea r15d, [rbx+1]\nloc_166A:\nxor ebx, ebx\nlea edi, [r13-1]\nloc_1670:\ncall func0\nmov r13d, eax\nmov edi, eax\ncall func0\nsub ebp, r13d\nlea edi, [rbp-1]\nadd ebx, eax\ncmp edi, 1\nja short loc_1670\nlea edx, [rbx+1]\nadd [rsp+68h+var_5C], r15d\nsub r12d, edx\nlea r13d, [r12-1]\ncmp r13d, 1\nja loc_1601\nmov edx, [rsp+68h+var_5C]\nmov ebx, [rsp+68h+var_54]\nxchg ax, ax\nloc_16B0:\nadd edx, 1\nsub [rsp+68h+var_58], edx\nmov eax, [rsp+68h+var_58]\nadd [rsp+68h+var_48], ebx\nlea r13d, [rax-1]\ncmp r13d, 1\nja loc_1460\nmov r15d, [rsp+68h+var_48]\nmov r14d, [rsp+68h+var_40]\nnop word ptr [rax+rax+00000000h]\nloc_16E0:\nlea ebx, [r15+1]\nloc_16E4:\nxor edx, edx\nlea eax, [r14-1]\nmov [rsp+68h+var_40], ebx\nmov [rsp+68h+var_4C], eax\nmov [rsp+68h+var_48], edx\nloc_16F6:\nmov eax, [rsp+68h+var_4C]\nmov ecx, [rsp+68h+var_50]\nmov r13d, eax\ncmp ecx, 3\njz loc_1B00\nmov [rsp+68h+var_5C], eax\nlea eax, [rcx-2]\nmov [rsp+68h+var_54], 0\nmov [rsp+68h+var_58], eax\nloc_171D:\nmov r12d, [rsp+68h+var_58]\nmov eax, [rsp+68h+var_5C]\nmov ebx, r12d\ncmp eax, 3\njz loc_1A10\nxor r14d, r14d\nlea edi, [rax-2]\nloc_1738:\ncall func0\nmov ebp, eax\nmov edi, eax\ncall func0\nsub r12d, ebp\nlea edi, [r12-1]\nadd r14d, eax\ncmp edi, 1\nja short loc_1738\nlea r15d, [r14+1]\ncmp r14d, 1\njbe loc_1B58\nxor r12d, r12d\nmov edi, r14d\nloc_176A:\ncall func0\nmov ebp, eax\nmov edi, eax\ncall func0\nsub r15d, ebp\nlea edi, [r15-1]\nadd r12d, eax\ncmp edi, 1\nja short loc_176A\nadd r12d, 1\nloc_178B:\nmov eax, [rsp+68h+var_58]\nxor ebp, ebp\nlea edi, [rax-1]\nloc_1794:\ncall func0\nmov r14d, eax\nmov edi, eax\ncall func0\nsub ebx, r14d\nlea edi, [rbx-1]\nadd ebp, eax\ncmp edi, 1\nja short loc_1794\nlea edx, [rbp+1]\nsub [rsp+68h+var_5C], edx\nmov eax, [rsp+68h+var_5C]\nadd [rsp+68h+var_54], r12d\nsub eax, 1\nmov [rsp+68h+var_58], eax\ncmp eax, 1\nja loc_171D\nmov eax, [rsp+68h+var_54]\nlea ecx, [rax+1]\nmov [rsp+68h+var_5C], ecx\ncmp eax, 1\njbe loc_1A29\nnop dword ptr [rax+00h]\nloc_17E8:\nmov [rsp+68h+var_54], 0\nmov [rsp+68h+var_58], eax\nloc_17F4:\nmov r12d, [rsp+68h+var_58]\nmov eax, [rsp+68h+var_5C]\nmov ebx, r12d\ncmp eax, 3\njz loc_1A00\nxor r14d, r14d\nlea edi, [rax-2]\nloc_180F:\ncall func0\nmov ebp, eax\nmov edi, eax\ncall func0\nsub r12d, ebp\nlea edi, [r12-1]\nadd r14d, eax\ncmp edi, 1\nja short loc_180F\nlea r12d, [r14+1]\ncmp r14d, 1\njbe loc_1B48\nxor r15d, r15d\nmov edi, r14d\nloc_1841:\ncall func0\nmov ebp, eax\nmov edi, eax\ncall func0\nsub r12d, ebp\nlea edi, [r12-1]\nadd r15d, eax\ncmp edi, 1\nja short loc_1841\nlea r14d, [r15+1]\nloc_1863:\nmov eax, [rsp+68h+var_58]\nxor ebp, ebp\nlea edi, [rax-1]\nloc_186C:\ncall func0\nmov r12d, eax\nmov edi, eax\ncall func0\nsub ebx, r12d\nlea edi, [rbx-1]\nadd ebp, eax\ncmp edi, 1\nja short loc_186C\nlea edx, [rbp+1]\nsub [rsp+68h+var_5C], edx\nmov eax, [rsp+68h+var_5C]\nadd [rsp+68h+var_54], r14d\nsub eax, 1\nmov [rsp+68h+var_58], eax\ncmp eax, 1\nja loc_17F4\nnop dword ptr [rax+rax+00000000h]\nloc_18B0:\nmov eax, [rsp+68h+var_54]\nadd eax, 1\nmov [rsp+68h+var_54], eax\nloc_18BB:\nmov eax, [rsp+68h+var_4C]\nmov [rsp+68h+var_58], 0\nsub eax, 1\nmov [rsp+68h+var_5C], eax\nloc_18CE:\nmov r14d, [rsp+68h+var_5C]\nmov ebx, r14d\ncmp r13d, 3\njz loc_19F0\nxor r12d, r12d\nlea edi, [r13-2]\nloc_18E7:\ncall func0\nmov ebp, eax\nmov edi, eax\ncall func0\nsub r14d, ebp\nlea edi, [r14-1]\nadd r12d, eax\ncmp edi, 1\nja short loc_18E7\nlea r14d, [r12+1]\ncmp r12d, 1\njbe loc_1B38\nxor r15d, r15d\nmov edi, r12d\nloc_1919:\ncall func0\nmov ebp, eax\nmov edi, eax\ncall func0\nsub r14d, ebp\nlea edi, [r14-1]\nadd r15d, eax\ncmp edi, 1\nja short loc_1919\nlea ebp, [r15+1]\nloc_193A:\nmov eax, [rsp+68h+var_5C]\nxor r15d, r15d\nlea edi, [rax-1]\nloc_1944:\ncall func0\nmov r14d, eax\nmov edi, eax\ncall func0\nsub ebx, r14d\nlea edi, [rbx-1]\nadd r15d, eax\ncmp edi, 1\nja short loc_1944\nlea edx, [r15+1]\nadd [rsp+68h+var_58], ebp\nsub r13d, edx\nlea eax, [r13-1]\nmov [rsp+68h+var_5C], eax\ncmp eax, 1\nja loc_18CE\nnop dword ptr [rax]\nloc_1980:\nmov r12d, [rsp+68h+var_58]\nmov ecx, [rsp+68h+var_54]\nadd [rsp+68h+var_48], ecx\nadd r12d, 1\nsub [rsp+68h+var_50], r12d\nmov eax, [rsp+68h+var_50]\nsub eax, 1\nmov [rsp+68h+var_4C], eax\ncmp eax, 1\nja loc_16F6\nmov edx, [rsp+68h+var_48]\nmov ebx, [rsp+68h+var_40]\nnop word ptr [rax+rax+00h]\nloc_19B8:\nadd edx, 1\nsub [rsp+68h+var_44], edx\nmov eax, [rsp+68h+var_44]\nadd [rsp+68h+var_3C], ebx\nlea r14d, [rax-1]\ncmp r14d, 1\nja loc_1222\nmov ebp, [rsp+68h+var_3C]\nlea eax, [rbp+1]\nloc_19DC:\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_19F0:\nadd [rsp+68h+var_58], 1\njmp short loc_1980\nloc_1A00:\nadd [rsp+68h+var_54], 1\njmp loc_18B0\nloc_1A10:\nadd [rsp+68h+var_54], 1\nmov eax, [rsp+68h+var_54]\nlea ecx, [rax+1]\nmov [rsp+68h+var_5C], ecx\ncmp eax, 1\nja loc_17E8\nloc_1A29:\nmov [rsp+68h+var_54], 1\njmp loc_18BB\nloc_1A40:\nmov edx, [rsp+68h+var_5C]\nmov ebx, [rsp+68h+var_54]\nadd edx, 1\njmp loc_16B0\nloc_1A50:\nmov edx, r15d\nmov r12d, [rsp+68h+var_54]\nmov r13d, [rsp+68h+var_4C]\nadd edx, ebx\njmp loc_15F0\nloc_1A68:\nadd r14d, r15d\nmov r12d, [rsp+68h+var_54]\nmov r13d, [rsp+68h+var_4C]\nlea r15d, [r14+1]\ncmp r14d, 1\nja loc_1530\nloc_1A83:\nmov ebx, 1\njmp loc_15F3\nloc_1A90:\nmov ebp, [rsp+68h+var_54]\nmov ebx, [rsp+68h+var_4C]\nadd r15d, r12d\njmp loc_13B0\nloc_1AA0:\nmov ecx, r12d\nmov ebp, [rsp+68h+var_54]\nmov ebx, [rsp+68h+var_4C]\nadd ecx, r13d\nlea r14d, [rcx+1]\ncmp ecx, 1\nja loc_1310\nloc_1ABB:\nmov r13d, 1\njmp loc_13B4\nloc_1AD0:\nmov ebx, [rsp+68h+var_48]\nmov r14d, [rsp+68h+var_40]\nadd ebx, 1\nlea eax, [rbx+1]\nmov [rsp+68h+var_58], eax\ncmp ebx, 1\nja loc_1450\nloc_1AEC:\nmov ebx, 1\njmp loc_16E4\nloc_1B00:\nmov edx, [rsp+68h+var_48]\nmov ebx, [rsp+68h+var_40]\nadd edx, 1\njmp loc_19B8\nloc_1B10:\nmov r15d, [rsp+68h+var_48]\nmov r14d, [rsp+68h+var_40]\nadd r15d, 1\njmp loc_16E0\nloc_1B28:\nmov r15d, 1\njmp loc_166A\nloc_1B38:\nmov ebp, 1\njmp loc_193A\nloc_1B48:\nmov r14d, 1\njmp loc_1863\nloc_1B58:\nmov r12d, 1\njmp loc_178B\nloc_1B63:\nmov ebp, [rsp+68h+var_3C]\nadd rsp, 38h\npop rbx\nadd ebp, 1\nlea eax, [rbp+1]\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1B7C:\nmov r13d, 1\njmp loc_12B5\nloc_1B87:\nmov r12d, 1\njmp loc_1365\nloc_1B92:\nmov r14d, 1\njmp loc_1401\nloc_1B9D:\nmov r15d, 1\njmp loc_14CC\nloc_1BA8:\nmov ebx, 1\njmp loc_1593", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n __int64 result; // rax\n int v2; // r14d\n int v3; // ebx\n int v4; // r14d\n unsigned int v5; // r12d\n unsigned int v6; // ebx\n unsigned int v7; // ebp\n int v8; // r13d\n int v9; // eax\n __int64 v10; // rdi\n int v11; // ebx\n __int64 v12; // r15\n int v13; // r13d\n int v14; // r15d\n __int64 v15; // rdi\n __int64 v16; // rbx\n unsigned int v17; // ecx\n int v18; // ebp\n int v19; // ebx\n int v20; // r14d\n int v21; // r15d\n unsigned int v22; // ebp\n int v23; // ebx\n unsigned int v24; // r13d\n int v25; // r12d\n int v26; // eax\n __int64 v27; // rdi\n int v28; // ebx\n __int64 v29; // r14\n int v30; // r12d\n int v31; // r14d\n __int64 v32; // rdi\n __int64 v33; // rbp\n int v34; // r13d\n int v35; // r12d\n __int64 v36; // rdi\n int v37; // eax\n int v38; // r14d\n __int64 v39; // rdi\n int v40; // r15d\n int v41; // r13d\n __int64 v42; // rbx\n int v43; // r14d\n unsigned int v44; // ebx\n int v45; // r14d\n unsigned int v46; // r13d\n unsigned int v47; // r14d\n unsigned int v48; // ebx\n unsigned int v49; // r12d\n unsigned int v50; // r13d\n int v51; // ebp\n int v52; // eax\n __int64 v53; // rdi\n int v54; // ebx\n __int64 v55; // r15\n int v56; // r15d\n int v57; // ebp\n __int64 v58; // rdi\n __int64 v59; // r12\n unsigned int v60; // r12d\n unsigned int v61; // r13d\n unsigned int v62; // r15d\n unsigned int v63; // r12d\n int v64; // r15d\n unsigned int v65; // r13d\n unsigned int v66; // ebp\n int v67; // r14d\n int v68; // eax\n __int64 v69; // rdi\n int v70; // ebp\n __int64 v71; // rbx\n int v72; // ebx\n int v73; // r14d\n __int64 v74; // rdi\n __int64 v75; // r13\n int v76; // edx\n int v77; // ebx\n unsigned int v78; // r13d\n unsigned int v79; // ebp\n unsigned int v80; // ebx\n unsigned int v81; // r15d\n __int64 v82; // rdi\n __int64 v83; // r14\n unsigned int v84; // r14d\n int v85; // ebx\n __int64 v86; // rdi\n __int64 v87; // r15\n int v88; // r15d\n int v89; // ebx\n __int64 v90; // rdi\n __int64 v91; // r13\n int v92; // edx\n int v93; // ebx\n int v94; // r15d\n int v95; // ebx\n int v96; // r13d\n int v97; // r12d\n int v98; // ebx\n unsigned int v99; // r14d\n __int64 v100; // rdi\n __int64 v101; // rbp\n unsigned int v102; // r15d\n int v103; // r12d\n __int64 v104; // rdi\n __int64 v105; // rbp\n int v106; // r12d\n int v107; // ebp\n __int64 v108; // rdi\n __int64 v109; // r14\n unsigned int v110; // eax\n unsigned int v111; // r12d\n unsigned int v112; // ebx\n unsigned int v113; // r14d\n __int64 v114; // rdi\n __int64 v115; // rbp\n unsigned int v116; // r12d\n int v117; // r15d\n __int64 v118; // rdi\n __int64 v119; // rbp\n int v120; // r14d\n int v121; // ebp\n __int64 v122; // rdi\n __int64 v123; // r12\n int v124; // r14d\n int v125; // ebx\n unsigned int v126; // r12d\n __int64 v127; // rdi\n __int64 v128; // rbp\n unsigned int v129; // r14d\n int v130; // r15d\n __int64 v131; // rdi\n __int64 v132; // rbp\n int v133; // ebp\n int v134; // r15d\n __int64 v135; // rdi\n __int64 v136; // r14\n int v137; // edx\n int v138; // ebx\n unsigned int v139; // [rsp+Ch] [rbp-5Ch]\n int v140; // [rsp+Ch] [rbp-5Ch]\n int v141; // [rsp+Ch] [rbp-5Ch]\n unsigned int v142; // [rsp+Ch] [rbp-5Ch]\n int v143; // [rsp+Ch] [rbp-5Ch]\n int v144; // [rsp+Ch] [rbp-5Ch]\n unsigned int v145; // [rsp+Ch] [rbp-5Ch]\n int v146; // [rsp+Ch] [rbp-5Ch]\n int v147; // [rsp+10h] [rbp-58h]\n unsigned int v148; // [rsp+10h] [rbp-58h]\n int v149; // [rsp+10h] [rbp-58h]\n unsigned int v150; // [rsp+10h] [rbp-58h]\n int v151; // [rsp+10h] [rbp-58h]\n int v152; // [rsp+14h] [rbp-54h]\n int v153; // [rsp+14h] [rbp-54h]\n unsigned int v154; // [rsp+14h] [rbp-54h]\n unsigned int v155; // [rsp+14h] [rbp-54h]\n int v156; // [rsp+14h] [rbp-54h]\n unsigned int v157; // [rsp+14h] [rbp-54h]\n int v158; // [rsp+14h] [rbp-54h]\n int v159; // [rsp+14h] [rbp-54h]\n int v160; // [rsp+18h] [rbp-50h]\n int v161; // [rsp+1Ch] [rbp-4Ch]\n int v162; // [rsp+1Ch] [rbp-4Ch]\n unsigned int v163; // [rsp+1Ch] [rbp-4Ch]\n unsigned int v164; // [rsp+1Ch] [rbp-4Ch]\n int v165; // [rsp+1Ch] [rbp-4Ch]\n unsigned int v166; // [rsp+20h] [rbp-48h]\n int v167; // [rsp+20h] [rbp-48h]\n int v168; // [rsp+20h] [rbp-48h]\n int v169; // [rsp+24h] [rbp-44h]\n int v170; // [rsp+28h] [rbp-40h]\n int v171; // [rsp+28h] [rbp-40h]\n int v172; // [rsp+28h] [rbp-40h]\n int v173; // [rsp+2Ch] [rbp-3Ch]\n\n result = 1LL;\n if ( (unsigned int)(a1 - 1) > 1 )\n {\n v169 = a1;\n v2 = a1 - 1;\n v173 = 0;\n while ( 1 )\n {\n v160 = v2;\n if ( v169 == 3 )\n return (unsigned int)(v173 + 2);\n v147 = v2;\n v170 = v2;\n v166 = 0;\n v3 = v169 - 2;\n while ( v147 != 3 )\n {\n v152 = v3;\n v4 = v3;\n v161 = v3;\n v5 = 0;\n v6 = v147 - 2;\n while ( 1 )\n {\n v7 = v6;\n v8 = 0;\n v9 = func0(v6);\n v10 = (unsigned int)(v9 - 1);\n if ( (unsigned int)v10 <= 1 )\n {\n v13 = 1;\n }\n else\n {\n v139 = v6;\n v11 = v9;\n do\n {\n v12 = (unsigned int)func0(v10);\n v11 -= v12;\n v10 = (unsigned int)(v11 - 1);\n v8 += func0(v12);\n }\n while ( (unsigned int)v10 > 1 );\n v6 = v139;\n v13 = v8 + 1;\n }\n if ( v4 == 3 )\n break;\n v14 = 0;\n v15 = v6 - 1;\n do\n {\n v16 = (unsigned int)func0(v15);\n v7 -= v16;\n v15 = v7 - 1;\n v14 += func0(v16);\n }\n while ( (unsigned int)v15 > 1 );\n v5 += v13;\n v4 -= v14 + 1;\n v6 = v4 - 1;\n if ( (unsigned int)(v4 - 1) <= 1 )\n {\n v17 = v5;\n v18 = v152;\n v19 = v161;\n v20 = v5 + 1;\n if ( v5 > 1 )\n goto LABEL_16;\nLABEL_124:\n v34 = 1;\n goto LABEL_27;\n }\n }\n v18 = v152;\n v19 = v161;\n v17 = v13 + v5;\n v20 = v13 + v5 + 1;\n if ( v13 + v5 <= 1 )\n goto LABEL_124;\nLABEL_16:\n v153 = v18;\n v21 = 0;\n v22 = v17;\n v162 = v19;\n v23 = v20;\n while ( 1 )\n {\n v24 = v22;\n v25 = 0;\n v26 = func0(v22);\n v27 = (unsigned int)(v26 - 1);\n if ( (unsigned int)v27 <= 1 )\n {\n v30 = 1;\n }\n else\n {\n v140 = v23;\n v28 = v26;\n do\n {\n v29 = (unsigned int)func0(v27);\n v28 -= v29;\n v27 = (unsigned int)(v28 - 1);\n v25 += func0(v29);\n }\n while ( (unsigned int)v27 > 1 );\n v23 = v140;\n v30 = v25 + 1;\n }\n if ( v23 == 3 )\n break;\n v31 = 0;\n v32 = v22 - 1;\n do\n {\n v33 = (unsigned int)func0(v32);\n v24 -= v33;\n v32 = v24 - 1;\n v31 += func0(v33);\n }\n while ( (unsigned int)v32 > 1 );\n v21 += v30;\n v23 -= v31 + 1;\n v22 = v23 - 1;\n if ( (unsigned int)(v23 - 1) <= 1 )\n {\n v18 = v153;\n v19 = v162;\n goto LABEL_26;\n }\n }\n v18 = v153;\n v19 = v162;\n v21 += v30;\nLABEL_26:\n v34 = v21 + 1;\nLABEL_27:\n v141 = v34;\n v35 = 0;\n v36 = (unsigned int)(v19 - 1);\n do\n {\n v37 = func0(v36);\n v38 = 0;\n v39 = (unsigned int)(v37 - 1);\n v40 = v37;\n v41 = v37;\n if ( (unsigned int)v39 <= 1 )\n {\n v43 = 1;\n }\n else\n {\n do\n {\n v42 = (unsigned int)func0(v39);\n v41 -= v42;\n v39 = (unsigned int)(v41 - 1);\n v38 += func0(v42);\n }\n while ( (unsigned int)v39 > 1 );\n v43 = v38 + 1;\n }\n v18 -= v40;\n v35 += v43;\n v36 = (unsigned int)(v18 - 1);\n }\n while ( (unsigned int)v36 > 1 );\n v147 -= v35 + 1;\n v166 += v141;\n v3 = v147 - 1;\n if ( (unsigned int)(v147 - 1) <= 1 )\n {\n v44 = v166;\n v45 = v170;\n v148 = v166 + 1;\n if ( v166 > 1 )\n goto LABEL_34;\nLABEL_126:\n v95 = 1;\n goto LABEL_72;\n }\n }\n v45 = v170;\n v44 = v166 + 1;\n v148 = v166 + 2;\n if ( v166 + 1 <= 1 )\n goto LABEL_126;\nLABEL_34:\n v171 = v45;\n v46 = v44;\n v167 = 0;\n while ( v148 != 3 )\n {\n v154 = v46;\n v47 = 0;\n v48 = v46;\n v163 = v46;\n v49 = v148 - 2;\n while ( 1 )\n {\n v50 = v49;\n v51 = 0;\n v52 = func0(v49);\n v53 = (unsigned int)(v52 - 1);\n if ( (unsigned int)v53 <= 1 )\n {\n v56 = 1;\n }\n else\n {\n v142 = v48;\n v54 = v52;\n do\n {\n v55 = (unsigned int)func0(v53);\n v54 -= v55;\n v53 = (unsigned int)(v54 - 1);\n v51 += func0(v55);\n }\n while ( (unsigned int)v53 > 1 );\n v48 = v142;\n v56 = v51 + 1;\n }\n if ( v48 == 3 )\n break;\n v57 = 0;\n v58 = v49 - 1;\n do\n {\n v59 = (unsigned int)func0(v58);\n v50 -= v59;\n v58 = v50 - 1;\n v57 += func0(v59);\n }\n while ( (unsigned int)v58 > 1 );\n v47 += v56;\n v48 -= v57 + 1;\n v49 = v48 - 1;\n if ( v48 - 1 <= 1 )\n {\n v60 = v154;\n v61 = v163;\n v62 = v47 + 1;\n if ( v47 > 1 )\n goto LABEL_46;\nLABEL_121:\n v77 = 1;\n goto LABEL_57;\n }\n }\n v47 += v56;\n v60 = v154;\n v61 = v163;\n v62 = v47 + 1;\n if ( v47 <= 1 )\n goto LABEL_121;\nLABEL_46:\n v155 = v60;\n v63 = v62;\n v164 = v61;\n v64 = 0;\n v65 = v47;\n while ( 1 )\n {\n v66 = v65;\n v67 = 0;\n v68 = func0(v65);\n v69 = (unsigned int)(v68 - 1);\n if ( (unsigned int)v69 <= 1 )\n {\n v72 = 1;\n }\n else\n {\n v70 = v68;\n do\n {\n v71 = (unsigned int)func0(v69);\n v70 -= v71;\n v69 = (unsigned int)(v70 - 1);\n v67 += func0(v71);\n }\n while ( (unsigned int)v69 > 1 );\n v66 = v65;\n v72 = v67 + 1;\n }\n if ( v63 == 3 )\n break;\n v73 = 0;\n v74 = v65 - 1;\n do\n {\n v75 = (unsigned int)func0(v74);\n v66 -= v75;\n v74 = v66 - 1;\n v73 += func0(v75);\n }\n while ( (unsigned int)v74 > 1 );\n v64 += v72;\n v63 -= v73 + 1;\n v65 = v63 - 1;\n if ( v63 - 1 <= 1 )\n {\n v60 = v155;\n v61 = v164;\n v76 = v64;\n goto LABEL_56;\n }\n }\n v60 = v155;\n v61 = v164;\n v76 = v72 + v64;\nLABEL_56:\n v77 = v76 + 1;\nLABEL_57:\n v156 = v77;\n v78 = v61 - 1;\n v143 = 0;\n while ( 1 )\n {\n v79 = v78;\n if ( v60 == 3 )\n break;\n v80 = v78;\n v81 = 0;\n v82 = v60 - 2;\n do\n {\n v83 = (unsigned int)func0(v82);\n v80 -= v83;\n v82 = v80 - 1;\n v81 += func0(v83);\n }\n while ( (unsigned int)v82 > 1 );\n v84 = v81 + 1;\n if ( v81 <= 1 )\n {\n v88 = 1;\n }\n else\n {\n v85 = 0;\n v86 = v81;\n do\n {\n v87 = (unsigned int)func0(v86);\n v84 -= v87;\n v86 = v84 - 1;\n v85 += func0(v87);\n }\n while ( (unsigned int)v86 > 1 );\n v88 = v85 + 1;\n }\n v89 = 0;\n v90 = v78 - 1;\n do\n {\n v91 = (unsigned int)func0(v90);\n v79 -= v91;\n v90 = v79 - 1;\n v89 += func0(v91);\n }\n while ( (unsigned int)v90 > 1 );\n v143 += v88;\n v60 -= v89 + 1;\n v78 = v60 - 1;\n if ( v60 - 1 <= 1 )\n {\n v92 = v143;\n v93 = v156;\n goto LABEL_69;\n }\n }\n v93 = v156;\n v92 = v143 + 1;\nLABEL_69:\n v148 -= v92 + 1;\n v167 += v93;\n v46 = v148 - 1;\n if ( v148 - 1 <= 1 )\n {\n v94 = v167;\n v45 = v171;\n goto LABEL_71;\n }\n }\n v45 = v171;\n v94 = v167 + 1;\nLABEL_71:\n v95 = v94 + 1;\nLABEL_72:\n v172 = v95;\n v165 = v45 - 1;\n v168 = 0;\n while ( 1 )\n {\n v96 = v165;\n if ( v160 == 3 )\n break;\n v144 = v165;\n v157 = 0;\n v149 = v160 - 2;\n while ( 1 )\n {\n v97 = v149;\n v98 = v149;\n if ( v144 == 3 )\n break;\n v99 = 0;\n v100 = (unsigned int)(v144 - 2);\n do\n {\n v101 = (unsigned int)func0(v100);\n v97 -= v101;\n v100 = (unsigned int)(v97 - 1);\n v99 += func0(v101);\n }\n while ( (unsigned int)v100 > 1 );\n v102 = v99 + 1;\n if ( v99 <= 1 )\n {\n v106 = 1;\n }\n else\n {\n v103 = 0;\n v104 = v99;\n do\n {\n v105 = (unsigned int)func0(v104);\n v102 -= v105;\n v104 = v102 - 1;\n v103 += func0(v105);\n }\n while ( (unsigned int)v104 > 1 );\n v106 = v103 + 1;\n }\n v107 = 0;\n v108 = (unsigned int)(v149 - 1);\n do\n {\n v109 = (unsigned int)func0(v108);\n v98 -= v109;\n v108 = (unsigned int)(v98 - 1);\n v107 += func0(v109);\n }\n while ( (unsigned int)v108 > 1 );\n v144 -= v107 + 1;\n v157 += v106;\n v149 = v144 - 1;\n if ( (unsigned int)(v144 - 1) <= 1 )\n {\n v110 = v157;\n v145 = v157 + 1;\n if ( v157 > 1 )\n goto LABEL_86;\nLABEL_117:\n v159 = 1;\n goto LABEL_98;\n }\n }\n v110 = v157 + 1;\n v145 = v157 + 2;\n if ( v157 + 1 <= 1 )\n goto LABEL_117;\nLABEL_86:\n v158 = 0;\n v150 = v110;\n while ( 1 )\n {\n v111 = v150;\n v112 = v150;\n if ( v145 == 3 )\n break;\n v113 = 0;\n v114 = v145 - 2;\n do\n {\n v115 = (unsigned int)func0(v114);\n v111 -= v115;\n v114 = v111 - 1;\n v113 += func0(v115);\n }\n while ( (unsigned int)v114 > 1 );\n v116 = v113 + 1;\n if ( v113 <= 1 )\n {\n v120 = 1;\n }\n else\n {\n v117 = 0;\n v118 = v113;\n do\n {\n v119 = (unsigned int)func0(v118);\n v116 -= v119;\n v118 = v116 - 1;\n v117 += func0(v119);\n }\n while ( (unsigned int)v118 > 1 );\n v120 = v117 + 1;\n }\n v121 = 0;\n v122 = v150 - 1;\n do\n {\n v123 = (unsigned int)func0(v122);\n v112 -= v123;\n v122 = v112 - 1;\n v121 += func0(v123);\n }\n while ( (unsigned int)v122 > 1 );\n v145 -= v121 + 1;\n v158 += v120;\n v150 = v145 - 1;\n if ( v145 - 1 <= 1 )\n goto LABEL_97;\n }\n ++v158;\nLABEL_97:\n v159 = v158 + 1;\nLABEL_98:\n v151 = 0;\n v146 = v165 - 1;\n while ( 1 )\n {\n v124 = v146;\n v125 = v146;\n if ( v96 == 3 )\n break;\n v126 = 0;\n v127 = (unsigned int)(v96 - 2);\n do\n {\n v128 = (unsigned int)func0(v127);\n v124 -= v128;\n v127 = (unsigned int)(v124 - 1);\n v126 += func0(v128);\n }\n while ( (unsigned int)v127 > 1 );\n v129 = v126 + 1;\n if ( v126 <= 1 )\n {\n v133 = 1;\n }\n else\n {\n v130 = 0;\n v131 = v126;\n do\n {\n v132 = (unsigned int)func0(v131);\n v129 -= v132;\n v131 = v129 - 1;\n v130 += func0(v132);\n }\n while ( (unsigned int)v131 > 1 );\n v133 = v130 + 1;\n }\n v134 = 0;\n v135 = (unsigned int)(v146 - 1);\n do\n {\n v136 = (unsigned int)func0(v135);\n v125 -= v136;\n v135 = (unsigned int)(v125 - 1);\n v134 += func0(v136);\n }\n while ( (unsigned int)v135 > 1 );\n v151 += v133;\n v96 -= v134 + 1;\n v146 = v96 - 1;\n if ( (unsigned int)(v96 - 1) <= 1 )\n goto LABEL_109;\n }\n ++v151;\nLABEL_109:\n v168 += v159;\n v160 -= v151 + 1;\n v165 = v160 - 1;\n if ( (unsigned int)(v160 - 1) <= 1 )\n {\n v137 = v168;\n v138 = v172;\n goto LABEL_111;\n }\n }\n v138 = v172;\n v137 = v168 + 1;\nLABEL_111:\n v169 -= v137 + 1;\n v173 += v138;\n v2 = v169 - 1;\n if ( (unsigned int)(v169 - 1) <= 1 )\n return (unsigned int)(v173 + 1);\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_11F0:\nendbr64\npush r15\nmov eax, 1\npush r14\npush r13\npush r12\nlea r12d, [rdi-1]\npush rbp\npush rbx\nsub rsp, 38h\ncmp r12d, 1\njbe loc_19DC\nxor ebp, ebp\nmov [rsp+68h+var_44], edi\nmov r14d, r12d\nmov [rsp+68h+var_3C], ebp\nloc_1222:\nmov eax, [rsp+68h+var_44]\nmov [rsp+68h+var_50], r14d\ncmp eax, 3\njz loc_1B63\nmov [rsp+68h+var_58], r14d\nxor ebx, ebx\nsub eax, 2\nmov [rsp+68h+var_40], r14d\nmov [rsp+68h+var_48], ebx\nmov ebx, eax\nloc_1249:\nmov eax, [rsp+68h+var_58]\ncmp eax, 3\njz loc_1AD0\nxor ecx, ecx\nlea r15d, [rax-2]\nmov [rsp+68h+var_54], ebx\nmov r14d, ebx\nmov [rsp+68h+var_4C], ebx\nmov r12d, ecx\nmov ebx, r15d\nloc_126D:\nmov edi, ebx\nmov ebp, ebx\nxor r13d, r13d\ncall sub_11F0\nlea edi, [rax-1]\ncmp edi, 1\njbe loc_1B7C\nmov [rsp+68h+var_5C], ebx\nmov ebx, eax\nnop dword ptr [rax+rax+00h]\nloc_1290:\ncall sub_11F0\nmov r15d, eax\nmov edi, eax\ncall sub_11F0\nsub ebx, r15d\nlea edi, [rbx-1]\nadd r13d, eax\ncmp edi, 1\nja short loc_1290\nmov ebx, [rsp+68h+var_5C]\nadd r13d, 1\nloc_12B5:\ncmp r14d, 3\njz loc_1AA0\nxor r15d, r15d\nlea edi, [rbx-1]\nloc_12C5:\ncall sub_11F0\nmov ebx, eax\nmov edi, eax\ncall sub_11F0\nsub ebp, ebx\nlea edi, [rbp-1]\nadd r15d, eax\ncmp edi, 1\nja short loc_12C5\nadd r15d, 1\nadd r12d, r13d\nsub r14d, r15d\nlea ebx, [r14-1]\ncmp ebx, 1\nja loc_126D\nmov ecx, r12d\nmov ebp, [rsp+68h+var_54]\nmov ebx, [rsp+68h+var_4C]\nlea r14d, [rcx+1]\ncmp ecx, 1\njbe loc_1ABB\nnop\nloc_1310:\nmov [rsp+68h+var_54], ebp\nxor r15d, r15d\nmov ebp, ecx\nmov [rsp+68h+var_4C], ebx\nmov ebx, r14d\nloc_1320:\nmov edi, ebp\nmov r13d, ebp\nxor r12d, r12d\ncall sub_11F0\nlea edi, [rax-1]\ncmp edi, 1\njbe loc_1B87\nmov [rsp+68h+var_5C], ebx\nmov ebx, eax\nnop\nloc_1340:\ncall sub_11F0\nmov r14d, eax\nmov edi, eax\ncall sub_11F0\nsub ebx, r14d\nlea edi, [rbx-1]\nadd r12d, eax\ncmp edi, 1\nja short loc_1340\nmov ebx, [rsp+68h+var_5C]\nadd r12d, 1\nloc_1365:\ncmp ebx, 3\njz loc_1A90\nxor r14d, r14d\nlea edi, [rbp-1]\nloc_1374:\ncall sub_11F0\nmov ebp, eax\nmov edi, eax\ncall sub_11F0\nsub r13d, ebp\nlea edi, [r13-1]\nadd r14d, eax\ncmp edi, 1\nja short loc_1374\nlea edx, [r14+1]\nadd r15d, r12d\nsub ebx, edx\nlea ebp, [rbx-1]\ncmp ebp, 1\nja loc_1320\nmov ebp, [rsp+68h+var_54]\nmov ebx, [rsp+68h+var_4C]\nxchg ax, ax\nloc_13B0:\nlea r13d, [r15+1]\nloc_13B4:\nmov [rsp+68h+var_5C], r13d\nxor r12d, r12d\nlea edi, [rbx-1]\nloc_13BF:\ncall sub_11F0\nxor r14d, r14d\nlea edi, [rax-1]\nmov r15d, eax\nmov r13d, eax\ncmp edi, 1\njbe loc_1B92\nnop dword ptr [rax+00000000h]\nloc_13E0:\ncall sub_11F0\nmov ebx, eax\nmov edi, eax\ncall sub_11F0\nsub r13d, ebx\nlea edi, [r13-1]\nadd r14d, eax\ncmp edi, 1\nja short loc_13E0\nadd r14d, 1\nloc_1401:\nsub ebp, r15d\nadd r12d, r14d\nlea edi, [rbp-1]\ncmp edi, 1\nja short loc_13BF\nadd r12d, 1\nsub [rsp+68h+var_58], r12d\nmov eax, [rsp+68h+var_58]\nmov r13d, [rsp+68h+var_5C]\nadd [rsp+68h+var_48], r13d\nlea ebx, [rax-1]\ncmp ebx, 1\nja loc_1249\nmov ebx, [rsp+68h+var_48]\nmov r14d, [rsp+68h+var_40]\nlea eax, [rbx+1]\nmov [rsp+68h+var_58], eax\ncmp ebx, 1\njbe loc_1AEC\nnop dword ptr [rax+rax+00h]\nloc_1450:\nxor r15d, r15d\nmov [rsp+68h+var_40], r14d\nmov r13d, ebx\nmov [rsp+68h+var_48], r15d\nloc_1460:\nmov eax, [rsp+68h+var_58]\ncmp eax, 3\njz loc_1B10\nmov [rsp+68h+var_54], r13d\nlea ebp, [rax-2]\nxor r14d, r14d\nmov ebx, r13d\nmov [rsp+68h+var_4C], r13d\nmov r12d, ebp\nloc_1483:\nmov edi, r12d\nmov r13d, r12d\nxor ebp, ebp\ncall sub_11F0\nlea edi, [rax-1]\ncmp edi, 1\njbe loc_1B9D\nmov [rsp+68h+var_5C], ebx\nmov ebx, eax\nnop word ptr [rax+rax+00h]\nloc_14A8:\ncall sub_11F0\nmov r15d, eax\nmov edi, eax\ncall sub_11F0\nsub ebx, r15d\nlea edi, [rbx-1]\nadd ebp, eax\ncmp edi, 1\nja short loc_14A8\nmov ebx, [rsp+68h+var_5C]\nlea r15d, [rbp+1]\nloc_14CC:\ncmp ebx, 3\njz loc_1A68\nxor ebp, ebp\nlea edi, [r12-1]\nloc_14DC:\ncall sub_11F0\nmov r12d, eax\nmov edi, eax\ncall sub_11F0\nsub r13d, r12d\nlea edi, [r13-1]\nadd ebp, eax\ncmp edi, 1\nja short loc_14DC\nadd ebp, 1\nadd r14d, r15d\nsub ebx, ebp\nlea r12d, [rbx-1]\ncmp r12d, 1\nja loc_1483\nmov r12d, [rsp+68h+var_54]\nmov r13d, [rsp+68h+var_4C]\nlea r15d, [r14+1]\ncmp r14d, 1\njbe loc_1A83\nnop word ptr [rax+rax+00000000h]\nloc_1530:\nxor edx, edx\nmov [rsp+68h+var_54], r12d\nmov r12d, r15d\nmov [rsp+68h+var_4C], r13d\nmov r15d, edx\nmov r13d, r14d\nloc_1545:\nmov edi, r13d\nmov ebp, r13d\nxor r14d, r14d\ncall sub_11F0\nlea edi, [rax-1]\ncmp edi, 1\njbe loc_1BA8\nmov [rsp+68h+var_5C], r13d\nmov ebp, eax\nnop word ptr [rax+rax+00000000h]\nloc_1570:\ncall sub_11F0\nmov ebx, eax\nmov edi, eax\ncall sub_11F0\nsub ebp, ebx\nlea edi, [rbp-1]\nadd r14d, eax\ncmp edi, 1\nja short loc_1570\nmov ebp, [rsp+68h+var_5C]\nlea ebx, [r14+1]\nloc_1593:\ncmp r12d, 3\njz loc_1A50\nxor r14d, r14d\nlea edi, [r13-1]\nloc_15A4:\ncall sub_11F0\nmov r13d, eax\nmov edi, eax\ncall sub_11F0\nsub ebp, r13d\nlea edi, [rbp-1]\nadd r14d, eax\ncmp edi, 1\nja short loc_15A4\nlea ecx, [r14+1]\nadd r15d, ebx\nsub r12d, ecx\nlea r13d, [r12-1]\ncmp r13d, 1\nja loc_1545\nmov r12d, [rsp+68h+var_54]\nmov r13d, [rsp+68h+var_4C]\nmov edx, r15d\nnop word ptr [rax+rax+00000000h]\nloc_15F0:\nlea ebx, [rdx+1]\nloc_15F3:\nxor edx, edx\nmov [rsp+68h+var_54], ebx\nsub r13d, 1\nmov [rsp+68h+var_5C], edx\nloc_1601:\nmov ebp, r13d\ncmp r12d, 3\njz loc_1A40\nmov ebx, r13d\nxor r15d, r15d\nlea edi, [r12-2]\nloc_1619:\ncall sub_11F0\nmov r14d, eax\nmov edi, eax\ncall sub_11F0\nsub ebx, r14d\nlea edi, [rbx-1]\nadd r15d, eax\ncmp edi, 1\nja short loc_1619\nlea r14d, [r15+1]\ncmp r15d, 1\njbe loc_1B28\nxor ebx, ebx\nmov edi, r15d\nloc_1649:\ncall sub_11F0\nmov r15d, eax\nmov edi, eax\ncall sub_11F0\nsub r14d, r15d\nlea edi, [r14-1]\nadd ebx, eax\ncmp edi, 1\nja short loc_1649\nlea r15d, [rbx+1]\nloc_166A:\nxor ebx, ebx\nlea edi, [r13-1]\nloc_1670:\ncall sub_11F0\nmov r13d, eax\nmov edi, eax\ncall sub_11F0\nsub ebp, r13d\nlea edi, [rbp-1]\nadd ebx, eax\ncmp edi, 1\nja short loc_1670\nlea edx, [rbx+1]\nadd [rsp+68h+var_5C], r15d\nsub r12d, edx\nlea r13d, [r12-1]\ncmp r13d, 1\nja loc_1601\nmov edx, [rsp+68h+var_5C]\nmov ebx, [rsp+68h+var_54]\nxchg ax, ax\nloc_16B0:\nadd edx, 1\nsub [rsp+68h+var_58], edx\nmov eax, [rsp+68h+var_58]\nadd [rsp+68h+var_48], ebx\nlea r13d, [rax-1]\ncmp r13d, 1\nja loc_1460\nmov r15d, [rsp+68h+var_48]\nmov r14d, [rsp+68h+var_40]\nnop word ptr [rax+rax+00000000h]\nloc_16E0:\nlea ebx, [r15+1]\nloc_16E4:\nxor edx, edx\nlea eax, [r14-1]\nmov [rsp+68h+var_40], ebx\nmov [rsp+68h+var_4C], eax\nmov [rsp+68h+var_48], edx\nloc_16F6:\nmov eax, [rsp+68h+var_4C]\nmov ecx, [rsp+68h+var_50]\nmov r13d, eax\ncmp ecx, 3\njz loc_1B00\nmov [rsp+68h+var_5C], eax\nlea eax, [rcx-2]\nmov [rsp+68h+var_54], 0\nmov [rsp+68h+var_58], eax\nloc_171D:\nmov r12d, [rsp+68h+var_58]\nmov eax, [rsp+68h+var_5C]\nmov ebx, r12d\ncmp eax, 3\njz loc_1A10\nxor r14d, r14d\nlea edi, [rax-2]\nloc_1738:\ncall sub_11F0\nmov ebp, eax\nmov edi, eax\ncall sub_11F0\nsub r12d, ebp\nlea edi, [r12-1]\nadd r14d, eax\ncmp edi, 1\nja short loc_1738\nlea r15d, [r14+1]\ncmp r14d, 1\njbe loc_1B58\nxor r12d, r12d\nmov edi, r14d\nloc_176A:\ncall sub_11F0\nmov ebp, eax\nmov edi, eax\ncall sub_11F0\nsub r15d, ebp\nlea edi, [r15-1]\nadd r12d, eax\ncmp edi, 1\nja short loc_176A\nadd r12d, 1\nloc_178B:\nmov eax, [rsp+68h+var_58]\nxor ebp, ebp\nlea edi, [rax-1]\nloc_1794:\ncall sub_11F0\nmov r14d, eax\nmov edi, eax\ncall sub_11F0\nsub ebx, r14d\nlea edi, [rbx-1]\nadd ebp, eax\ncmp edi, 1\nja short loc_1794\nlea edx, [rbp+1]\nsub [rsp+68h+var_5C], edx\nmov eax, [rsp+68h+var_5C]\nadd [rsp+68h+var_54], r12d\nsub eax, 1\nmov [rsp+68h+var_58], eax\ncmp eax, 1\nja loc_171D\nmov eax, [rsp+68h+var_54]\nlea ecx, [rax+1]\nmov [rsp+68h+var_5C], ecx\ncmp eax, 1\njbe loc_1A29\nnop dword ptr [rax+00h]\nloc_17E8:\nmov [rsp+68h+var_54], 0\nmov [rsp+68h+var_58], eax\nloc_17F4:\nmov r12d, [rsp+68h+var_58]\nmov eax, [rsp+68h+var_5C]\nmov ebx, r12d\ncmp eax, 3\njz loc_1A00\nxor r14d, r14d\nlea edi, [rax-2]\nloc_180F:\ncall sub_11F0\nmov ebp, eax\nmov edi, eax\ncall sub_11F0\nsub r12d, ebp\nlea edi, [r12-1]\nadd r14d, eax\ncmp edi, 1\nja short loc_180F\nlea r12d, [r14+1]\ncmp r14d, 1\njbe loc_1B48\nxor r15d, r15d\nmov edi, r14d\nloc_1841:\ncall sub_11F0\nmov ebp, eax\nmov edi, eax\ncall sub_11F0\nsub r12d, ebp\nlea edi, [r12-1]\nadd r15d, eax\ncmp edi, 1\nja short loc_1841\nlea r14d, [r15+1]\nloc_1863:\nmov eax, [rsp+68h+var_58]\nxor ebp, ebp\nlea edi, [rax-1]\nloc_186C:\ncall sub_11F0\nmov r12d, eax\nmov edi, eax\ncall sub_11F0\nsub ebx, r12d\nlea edi, [rbx-1]\nadd ebp, eax\ncmp edi, 1\nja short loc_186C\nlea edx, [rbp+1]\nsub [rsp+68h+var_5C], edx\nmov eax, [rsp+68h+var_5C]\nadd [rsp+68h+var_54], r14d\nsub eax, 1\nmov [rsp+68h+var_58], eax\ncmp eax, 1\nja loc_17F4\nnop dword ptr [rax+rax+00000000h]\nloc_18B0:\nmov eax, [rsp+68h+var_54]\nadd eax, 1\nmov [rsp+68h+var_54], eax\nloc_18BB:\nmov eax, [rsp+68h+var_4C]\nmov [rsp+68h+var_58], 0\nsub eax, 1\nmov [rsp+68h+var_5C], eax\nloc_18CE:\nmov r14d, [rsp+68h+var_5C]\nmov ebx, r14d\ncmp r13d, 3\njz loc_19F0\nxor r12d, r12d\nlea edi, [r13-2]\nloc_18E7:\ncall sub_11F0\nmov ebp, eax\nmov edi, eax\ncall sub_11F0\nsub r14d, ebp\nlea edi, [r14-1]\nadd r12d, eax\ncmp edi, 1\nja short loc_18E7\nlea r14d, [r12+1]\ncmp r12d, 1\njbe loc_1B38\nxor r15d, r15d\nmov edi, r12d\nloc_1919:\ncall sub_11F0\nmov ebp, eax\nmov edi, eax\ncall sub_11F0\nsub r14d, ebp\nlea edi, [r14-1]\nadd r15d, eax\ncmp edi, 1\nja short loc_1919\nlea ebp, [r15+1]\nloc_193A:\nmov eax, [rsp+68h+var_5C]\nxor r15d, r15d\nlea edi, [rax-1]\nloc_1944:\ncall sub_11F0\nmov r14d, eax\nmov edi, eax\ncall sub_11F0\nsub ebx, r14d\nlea edi, [rbx-1]\nadd r15d, eax\ncmp edi, 1\nja short loc_1944\nlea edx, [r15+1]\nadd [rsp+68h+var_58], ebp\nsub r13d, edx\nlea eax, [r13-1]\nmov [rsp+68h+var_5C], eax\ncmp eax, 1\nja loc_18CE\nnop dword ptr [rax]\nloc_1980:\nmov r12d, [rsp+68h+var_58]\nmov ecx, [rsp+68h+var_54]\nadd [rsp+68h+var_48], ecx\nadd r12d, 1\nsub [rsp+68h+var_50], r12d\nmov eax, [rsp+68h+var_50]\nsub eax, 1\nmov [rsp+68h+var_4C], eax\ncmp eax, 1\nja loc_16F6\nmov edx, [rsp+68h+var_48]\nmov ebx, [rsp+68h+var_40]\nnop word ptr [rax+rax+00h]\nloc_19B8:\nadd edx, 1\nsub [rsp+68h+var_44], edx\nmov eax, [rsp+68h+var_44]\nadd [rsp+68h+var_3C], ebx\nlea r14d, [rax-1]\ncmp r14d, 1\nja loc_1222\nmov ebp, [rsp+68h+var_3C]\nlea eax, [rbp+1]\nloc_19DC:\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_19F0:\nadd [rsp+68h+var_58], 1\njmp short loc_1980\nloc_1A00:\nadd [rsp+68h+var_54], 1\njmp loc_18B0\nloc_1A10:\nadd [rsp+68h+var_54], 1\nmov eax, [rsp+68h+var_54]\nlea ecx, [rax+1]\nmov [rsp+68h+var_5C], ecx\ncmp eax, 1\nja loc_17E8\nloc_1A29:\nmov [rsp+68h+var_54], 1\njmp loc_18BB\nloc_1A40:\nmov edx, [rsp+68h+var_5C]\nmov ebx, [rsp+68h+var_54]\nadd edx, 1\njmp loc_16B0\nloc_1A50:\nmov edx, r15d\nmov r12d, [rsp+68h+var_54]\nmov r13d, [rsp+68h+var_4C]\nadd edx, ebx\njmp loc_15F0\nloc_1A68:\nadd r14d, r15d\nmov r12d, [rsp+68h+var_54]\nmov r13d, [rsp+68h+var_4C]\nlea r15d, [r14+1]\ncmp r14d, 1\nja loc_1530\nloc_1A83:\nmov ebx, 1\njmp loc_15F3\nloc_1A90:\nmov ebp, [rsp+68h+var_54]\nmov ebx, [rsp+68h+var_4C]\nadd r15d, r12d\njmp loc_13B0\nloc_1AA0:\nmov ecx, r12d\nmov ebp, [rsp+68h+var_54]\nmov ebx, [rsp+68h+var_4C]\nadd ecx, r13d\nlea r14d, [rcx+1]\ncmp ecx, 1\nja loc_1310\nloc_1ABB:\nmov r13d, 1\njmp loc_13B4\nloc_1AD0:\nmov ebx, [rsp+68h+var_48]\nmov r14d, [rsp+68h+var_40]\nadd ebx, 1\nlea eax, [rbx+1]\nmov [rsp+68h+var_58], eax\ncmp ebx, 1\nja loc_1450\nloc_1AEC:\nmov ebx, 1\njmp loc_16E4\nloc_1B00:\nmov edx, [rsp+68h+var_48]\nmov ebx, [rsp+68h+var_40]\nadd edx, 1\njmp loc_19B8\nloc_1B10:\nmov r15d, [rsp+68h+var_48]\nmov r14d, [rsp+68h+var_40]\nadd r15d, 1\njmp loc_16E0\nloc_1B28:\nmov r15d, 1\njmp loc_166A\nloc_1B38:\nmov ebp, 1\njmp loc_193A\nloc_1B48:\nmov r14d, 1\njmp loc_1863\nloc_1B58:\nmov r12d, 1\njmp loc_178B\nloc_1B63:\nmov ebp, [rsp+68h+var_3C]\nadd rsp, 38h\npop rbx\nadd ebp, 1\nlea eax, [rbp+1]\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1B7C:\nmov r13d, 1\njmp loc_12B5\nloc_1B87:\nmov r12d, 1\njmp loc_1365\nloc_1B92:\nmov r14d, 1\njmp loc_1401\nloc_1B9D:\nmov r15d, 1\njmp loc_14CC\nloc_1BA8:\nmov ebx, 1\njmp loc_1593", + "ida_strip_pseudo": "__int64 __fastcall sub_11F0(int a1)\n{\n __int64 result; // rax\n int v2; // r14d\n int v3; // ebx\n int v4; // r14d\n unsigned int v5; // r12d\n unsigned int v6; // ebx\n unsigned int v7; // ebp\n int v8; // r13d\n int v9; // eax\n __int64 v10; // rdi\n int v11; // ebx\n __int64 v12; // r15\n int v13; // r13d\n int v14; // r15d\n __int64 v15; // rdi\n __int64 v16; // rbx\n unsigned int v17; // ecx\n int v18; // ebp\n int v19; // ebx\n int v20; // r14d\n int v21; // r15d\n unsigned int v22; // ebp\n int v23; // ebx\n unsigned int v24; // r13d\n int v25; // r12d\n int v26; // eax\n __int64 v27; // rdi\n int v28; // ebx\n __int64 v29; // r14\n int v30; // r12d\n int v31; // r14d\n __int64 v32; // rdi\n __int64 v33; // rbp\n int v34; // r13d\n int v35; // r12d\n __int64 v36; // rdi\n int v37; // eax\n int v38; // r14d\n __int64 v39; // rdi\n int v40; // r15d\n int v41; // r13d\n __int64 v42; // rbx\n int v43; // r14d\n unsigned int v44; // ebx\n int v45; // r14d\n unsigned int v46; // r13d\n unsigned int v47; // r14d\n unsigned int v48; // ebx\n unsigned int v49; // r12d\n unsigned int v50; // r13d\n int v51; // ebp\n int v52; // eax\n __int64 v53; // rdi\n int v54; // ebx\n __int64 v55; // r15\n int v56; // r15d\n int v57; // ebp\n __int64 v58; // rdi\n __int64 v59; // r12\n unsigned int v60; // r12d\n unsigned int v61; // r13d\n unsigned int v62; // r15d\n unsigned int v63; // r12d\n int v64; // r15d\n unsigned int v65; // r13d\n unsigned int v66; // ebp\n int v67; // r14d\n int v68; // eax\n __int64 v69; // rdi\n int v70; // ebp\n __int64 v71; // rbx\n int v72; // ebx\n int v73; // r14d\n __int64 v74; // rdi\n __int64 v75; // r13\n int v76; // edx\n int v77; // ebx\n unsigned int v78; // r13d\n unsigned int v79; // ebp\n unsigned int v80; // ebx\n unsigned int v81; // r15d\n __int64 v82; // rdi\n __int64 v83; // r14\n unsigned int v84; // r14d\n int v85; // ebx\n __int64 v86; // rdi\n __int64 v87; // r15\n int v88; // r15d\n int v89; // ebx\n __int64 v90; // rdi\n __int64 v91; // r13\n int v92; // edx\n int v93; // ebx\n int v94; // r15d\n int v95; // ebx\n int v96; // r13d\n int v97; // r12d\n int v98; // ebx\n unsigned int v99; // r14d\n __int64 v100; // rdi\n __int64 v101; // rbp\n unsigned int v102; // r15d\n int v103; // r12d\n __int64 v104; // rdi\n __int64 v105; // rbp\n int v106; // r12d\n int v107; // ebp\n __int64 v108; // rdi\n __int64 v109; // r14\n unsigned int v110; // eax\n unsigned int v111; // r12d\n unsigned int v112; // ebx\n unsigned int v113; // r14d\n __int64 v114; // rdi\n __int64 v115; // rbp\n unsigned int v116; // r12d\n int v117; // r15d\n __int64 v118; // rdi\n __int64 v119; // rbp\n int v120; // r14d\n int v121; // ebp\n __int64 v122; // rdi\n __int64 v123; // r12\n int v124; // r14d\n int v125; // ebx\n unsigned int v126; // r12d\n __int64 v127; // rdi\n __int64 v128; // rbp\n unsigned int v129; // r14d\n int v130; // r15d\n __int64 v131; // rdi\n __int64 v132; // rbp\n int v133; // ebp\n int v134; // r15d\n __int64 v135; // rdi\n __int64 v136; // r14\n int v137; // edx\n int v138; // ebx\n unsigned int v139; // [rsp+Ch] [rbp-5Ch]\n int v140; // [rsp+Ch] [rbp-5Ch]\n int v141; // [rsp+Ch] [rbp-5Ch]\n unsigned int v142; // [rsp+Ch] [rbp-5Ch]\n int v143; // [rsp+Ch] [rbp-5Ch]\n int v144; // [rsp+Ch] [rbp-5Ch]\n unsigned int v145; // [rsp+Ch] [rbp-5Ch]\n int v146; // [rsp+Ch] [rbp-5Ch]\n int v147; // [rsp+10h] [rbp-58h]\n unsigned int v148; // [rsp+10h] [rbp-58h]\n int v149; // [rsp+10h] [rbp-58h]\n unsigned int v150; // [rsp+10h] [rbp-58h]\n int v151; // [rsp+10h] [rbp-58h]\n int v152; // [rsp+14h] [rbp-54h]\n int v153; // [rsp+14h] [rbp-54h]\n unsigned int v154; // [rsp+14h] [rbp-54h]\n unsigned int v155; // [rsp+14h] [rbp-54h]\n int v156; // [rsp+14h] [rbp-54h]\n unsigned int v157; // [rsp+14h] [rbp-54h]\n int v158; // [rsp+14h] [rbp-54h]\n int v159; // [rsp+14h] [rbp-54h]\n int v160; // [rsp+18h] [rbp-50h]\n int v161; // [rsp+1Ch] [rbp-4Ch]\n int v162; // [rsp+1Ch] [rbp-4Ch]\n unsigned int v163; // [rsp+1Ch] [rbp-4Ch]\n unsigned int v164; // [rsp+1Ch] [rbp-4Ch]\n int v165; // [rsp+1Ch] [rbp-4Ch]\n unsigned int v166; // [rsp+20h] [rbp-48h]\n int v167; // [rsp+20h] [rbp-48h]\n int v168; // [rsp+20h] [rbp-48h]\n int v169; // [rsp+24h] [rbp-44h]\n int v170; // [rsp+28h] [rbp-40h]\n int v171; // [rsp+28h] [rbp-40h]\n int v172; // [rsp+28h] [rbp-40h]\n int v173; // [rsp+2Ch] [rbp-3Ch]\n\n result = 1LL;\n if ( (unsigned int)(a1 - 1) > 1 )\n {\n v169 = a1;\n v2 = a1 - 1;\n v173 = 0;\n while ( 1 )\n {\n v160 = v2;\n if ( v169 == 3 )\n return (unsigned int)(v173 + 2);\n v147 = v2;\n v170 = v2;\n v166 = 0;\n v3 = v169 - 2;\n while ( v147 != 3 )\n {\n v152 = v3;\n v4 = v3;\n v161 = v3;\n v5 = 0;\n v6 = v147 - 2;\n while ( 1 )\n {\n v7 = v6;\n v8 = 0;\n v9 = sub_11F0(v6);\n v10 = (unsigned int)(v9 - 1);\n if ( (unsigned int)v10 <= 1 )\n {\n v13 = 1;\n }\n else\n {\n v139 = v6;\n v11 = v9;\n do\n {\n v12 = (unsigned int)sub_11F0(v10);\n v11 -= v12;\n v10 = (unsigned int)(v11 - 1);\n v8 += sub_11F0(v12);\n }\n while ( (unsigned int)v10 > 1 );\n v6 = v139;\n v13 = v8 + 1;\n }\n if ( v4 == 3 )\n break;\n v14 = 0;\n v15 = v6 - 1;\n do\n {\n v16 = (unsigned int)sub_11F0(v15);\n v7 -= v16;\n v15 = v7 - 1;\n v14 += sub_11F0(v16);\n }\n while ( (unsigned int)v15 > 1 );\n v5 += v13;\n v4 -= v14 + 1;\n v6 = v4 - 1;\n if ( (unsigned int)(v4 - 1) <= 1 )\n {\n v17 = v5;\n v18 = v152;\n v19 = v161;\n v20 = v5 + 1;\n if ( v5 > 1 )\n goto LABEL_16;\nLABEL_124:\n v34 = 1;\n goto LABEL_27;\n }\n }\n v18 = v152;\n v19 = v161;\n v17 = v13 + v5;\n v20 = v13 + v5 + 1;\n if ( v13 + v5 <= 1 )\n goto LABEL_124;\nLABEL_16:\n v153 = v18;\n v21 = 0;\n v22 = v17;\n v162 = v19;\n v23 = v20;\n while ( 1 )\n {\n v24 = v22;\n v25 = 0;\n v26 = sub_11F0(v22);\n v27 = (unsigned int)(v26 - 1);\n if ( (unsigned int)v27 <= 1 )\n {\n v30 = 1;\n }\n else\n {\n v140 = v23;\n v28 = v26;\n do\n {\n v29 = (unsigned int)sub_11F0(v27);\n v28 -= v29;\n v27 = (unsigned int)(v28 - 1);\n v25 += sub_11F0(v29);\n }\n while ( (unsigned int)v27 > 1 );\n v23 = v140;\n v30 = v25 + 1;\n }\n if ( v23 == 3 )\n break;\n v31 = 0;\n v32 = v22 - 1;\n do\n {\n v33 = (unsigned int)sub_11F0(v32);\n v24 -= v33;\n v32 = v24 - 1;\n v31 += sub_11F0(v33);\n }\n while ( (unsigned int)v32 > 1 );\n v21 += v30;\n v23 -= v31 + 1;\n v22 = v23 - 1;\n if ( (unsigned int)(v23 - 1) <= 1 )\n {\n v18 = v153;\n v19 = v162;\n goto LABEL_26;\n }\n }\n v18 = v153;\n v19 = v162;\n v21 += v30;\nLABEL_26:\n v34 = v21 + 1;\nLABEL_27:\n v141 = v34;\n v35 = 0;\n v36 = (unsigned int)(v19 - 1);\n do\n {\n v37 = sub_11F0(v36);\n v38 = 0;\n v39 = (unsigned int)(v37 - 1);\n v40 = v37;\n v41 = v37;\n if ( (unsigned int)v39 <= 1 )\n {\n v43 = 1;\n }\n else\n {\n do\n {\n v42 = (unsigned int)sub_11F0(v39);\n v41 -= v42;\n v39 = (unsigned int)(v41 - 1);\n v38 += sub_11F0(v42);\n }\n while ( (unsigned int)v39 > 1 );\n v43 = v38 + 1;\n }\n v18 -= v40;\n v35 += v43;\n v36 = (unsigned int)(v18 - 1);\n }\n while ( (unsigned int)v36 > 1 );\n v147 -= v35 + 1;\n v166 += v141;\n v3 = v147 - 1;\n if ( (unsigned int)(v147 - 1) <= 1 )\n {\n v44 = v166;\n v45 = v170;\n v148 = v166 + 1;\n if ( v166 > 1 )\n goto LABEL_34;\nLABEL_126:\n v95 = 1;\n goto LABEL_72;\n }\n }\n v45 = v170;\n v44 = v166 + 1;\n v148 = v166 + 2;\n if ( v166 + 1 <= 1 )\n goto LABEL_126;\nLABEL_34:\n v171 = v45;\n v46 = v44;\n v167 = 0;\n while ( v148 != 3 )\n {\n v154 = v46;\n v47 = 0;\n v48 = v46;\n v163 = v46;\n v49 = v148 - 2;\n while ( 1 )\n {\n v50 = v49;\n v51 = 0;\n v52 = sub_11F0(v49);\n v53 = (unsigned int)(v52 - 1);\n if ( (unsigned int)v53 <= 1 )\n {\n v56 = 1;\n }\n else\n {\n v142 = v48;\n v54 = v52;\n do\n {\n v55 = (unsigned int)sub_11F0(v53);\n v54 -= v55;\n v53 = (unsigned int)(v54 - 1);\n v51 += sub_11F0(v55);\n }\n while ( (unsigned int)v53 > 1 );\n v48 = v142;\n v56 = v51 + 1;\n }\n if ( v48 == 3 )\n break;\n v57 = 0;\n v58 = v49 - 1;\n do\n {\n v59 = (unsigned int)sub_11F0(v58);\n v50 -= v59;\n v58 = v50 - 1;\n v57 += sub_11F0(v59);\n }\n while ( (unsigned int)v58 > 1 );\n v47 += v56;\n v48 -= v57 + 1;\n v49 = v48 - 1;\n if ( v48 - 1 <= 1 )\n {\n v60 = v154;\n v61 = v163;\n v62 = v47 + 1;\n if ( v47 > 1 )\n goto LABEL_46;\nLABEL_121:\n v77 = 1;\n goto LABEL_57;\n }\n }\n v47 += v56;\n v60 = v154;\n v61 = v163;\n v62 = v47 + 1;\n if ( v47 <= 1 )\n goto LABEL_121;\nLABEL_46:\n v155 = v60;\n v63 = v62;\n v164 = v61;\n v64 = 0;\n v65 = v47;\n while ( 1 )\n {\n v66 = v65;\n v67 = 0;\n v68 = sub_11F0(v65);\n v69 = (unsigned int)(v68 - 1);\n if ( (unsigned int)v69 <= 1 )\n {\n v72 = 1;\n }\n else\n {\n v70 = v68;\n do\n {\n v71 = (unsigned int)sub_11F0(v69);\n v70 -= v71;\n v69 = (unsigned int)(v70 - 1);\n v67 += sub_11F0(v71);\n }\n while ( (unsigned int)v69 > 1 );\n v66 = v65;\n v72 = v67 + 1;\n }\n if ( v63 == 3 )\n break;\n v73 = 0;\n v74 = v65 - 1;\n do\n {\n v75 = (unsigned int)sub_11F0(v74);\n v66 -= v75;\n v74 = v66 - 1;\n v73 += sub_11F0(v75);\n }\n while ( (unsigned int)v74 > 1 );\n v64 += v72;\n v63 -= v73 + 1;\n v65 = v63 - 1;\n if ( v63 - 1 <= 1 )\n {\n v60 = v155;\n v61 = v164;\n v76 = v64;\n goto LABEL_56;\n }\n }\n v60 = v155;\n v61 = v164;\n v76 = v72 + v64;\nLABEL_56:\n v77 = v76 + 1;\nLABEL_57:\n v156 = v77;\n v78 = v61 - 1;\n v143 = 0;\n while ( 1 )\n {\n v79 = v78;\n if ( v60 == 3 )\n break;\n v80 = v78;\n v81 = 0;\n v82 = v60 - 2;\n do\n {\n v83 = (unsigned int)sub_11F0(v82);\n v80 -= v83;\n v82 = v80 - 1;\n v81 += sub_11F0(v83);\n }\n while ( (unsigned int)v82 > 1 );\n v84 = v81 + 1;\n if ( v81 <= 1 )\n {\n v88 = 1;\n }\n else\n {\n v85 = 0;\n v86 = v81;\n do\n {\n v87 = (unsigned int)sub_11F0(v86);\n v84 -= v87;\n v86 = v84 - 1;\n v85 += sub_11F0(v87);\n }\n while ( (unsigned int)v86 > 1 );\n v88 = v85 + 1;\n }\n v89 = 0;\n v90 = v78 - 1;\n do\n {\n v91 = (unsigned int)sub_11F0(v90);\n v79 -= v91;\n v90 = v79 - 1;\n v89 += sub_11F0(v91);\n }\n while ( (unsigned int)v90 > 1 );\n v143 += v88;\n v60 -= v89 + 1;\n v78 = v60 - 1;\n if ( v60 - 1 <= 1 )\n {\n v92 = v143;\n v93 = v156;\n goto LABEL_69;\n }\n }\n v93 = v156;\n v92 = v143 + 1;\nLABEL_69:\n v148 -= v92 + 1;\n v167 += v93;\n v46 = v148 - 1;\n if ( v148 - 1 <= 1 )\n {\n v94 = v167;\n v45 = v171;\n goto LABEL_71;\n }\n }\n v45 = v171;\n v94 = v167 + 1;\nLABEL_71:\n v95 = v94 + 1;\nLABEL_72:\n v172 = v95;\n v165 = v45 - 1;\n v168 = 0;\n while ( 1 )\n {\n v96 = v165;\n if ( v160 == 3 )\n break;\n v144 = v165;\n v157 = 0;\n v149 = v160 - 2;\n while ( 1 )\n {\n v97 = v149;\n v98 = v149;\n if ( v144 == 3 )\n break;\n v99 = 0;\n v100 = (unsigned int)(v144 - 2);\n do\n {\n v101 = (unsigned int)sub_11F0(v100);\n v97 -= v101;\n v100 = (unsigned int)(v97 - 1);\n v99 += sub_11F0(v101);\n }\n while ( (unsigned int)v100 > 1 );\n v102 = v99 + 1;\n if ( v99 <= 1 )\n {\n v106 = 1;\n }\n else\n {\n v103 = 0;\n v104 = v99;\n do\n {\n v105 = (unsigned int)sub_11F0(v104);\n v102 -= v105;\n v104 = v102 - 1;\n v103 += sub_11F0(v105);\n }\n while ( (unsigned int)v104 > 1 );\n v106 = v103 + 1;\n }\n v107 = 0;\n v108 = (unsigned int)(v149 - 1);\n do\n {\n v109 = (unsigned int)sub_11F0(v108);\n v98 -= v109;\n v108 = (unsigned int)(v98 - 1);\n v107 += sub_11F0(v109);\n }\n while ( (unsigned int)v108 > 1 );\n v144 -= v107 + 1;\n v157 += v106;\n v149 = v144 - 1;\n if ( (unsigned int)(v144 - 1) <= 1 )\n {\n v110 = v157;\n v145 = v157 + 1;\n if ( v157 > 1 )\n goto LABEL_86;\nLABEL_117:\n v159 = 1;\n goto LABEL_98;\n }\n }\n v110 = v157 + 1;\n v145 = v157 + 2;\n if ( v157 + 1 <= 1 )\n goto LABEL_117;\nLABEL_86:\n v158 = 0;\n v150 = v110;\n while ( 1 )\n {\n v111 = v150;\n v112 = v150;\n if ( v145 == 3 )\n break;\n v113 = 0;\n v114 = v145 - 2;\n do\n {\n v115 = (unsigned int)sub_11F0(v114);\n v111 -= v115;\n v114 = v111 - 1;\n v113 += sub_11F0(v115);\n }\n while ( (unsigned int)v114 > 1 );\n v116 = v113 + 1;\n if ( v113 <= 1 )\n {\n v120 = 1;\n }\n else\n {\n v117 = 0;\n v118 = v113;\n do\n {\n v119 = (unsigned int)sub_11F0(v118);\n v116 -= v119;\n v118 = v116 - 1;\n v117 += sub_11F0(v119);\n }\n while ( (unsigned int)v118 > 1 );\n v120 = v117 + 1;\n }\n v121 = 0;\n v122 = v150 - 1;\n do\n {\n v123 = (unsigned int)sub_11F0(v122);\n v112 -= v123;\n v122 = v112 - 1;\n v121 += sub_11F0(v123);\n }\n while ( (unsigned int)v122 > 1 );\n v145 -= v121 + 1;\n v158 += v120;\n v150 = v145 - 1;\n if ( v145 - 1 <= 1 )\n goto LABEL_97;\n }\n ++v158;\nLABEL_97:\n v159 = v158 + 1;\nLABEL_98:\n v151 = 0;\n v146 = v165 - 1;\n while ( 1 )\n {\n v124 = v146;\n v125 = v146;\n if ( v96 == 3 )\n break;\n v126 = 0;\n v127 = (unsigned int)(v96 - 2);\n do\n {\n v128 = (unsigned int)sub_11F0(v127);\n v124 -= v128;\n v127 = (unsigned int)(v124 - 1);\n v126 += sub_11F0(v128);\n }\n while ( (unsigned int)v127 > 1 );\n v129 = v126 + 1;\n if ( v126 <= 1 )\n {\n v133 = 1;\n }\n else\n {\n v130 = 0;\n v131 = v126;\n do\n {\n v132 = (unsigned int)sub_11F0(v131);\n v129 -= v132;\n v131 = v129 - 1;\n v130 += sub_11F0(v132);\n }\n while ( (unsigned int)v131 > 1 );\n v133 = v130 + 1;\n }\n v134 = 0;\n v135 = (unsigned int)(v146 - 1);\n do\n {\n v136 = (unsigned int)sub_11F0(v135);\n v125 -= v136;\n v135 = (unsigned int)(v125 - 1);\n v134 += sub_11F0(v136);\n }\n while ( (unsigned int)v135 > 1 );\n v151 += v133;\n v96 -= v134 + 1;\n v146 = v96 - 1;\n if ( (unsigned int)(v96 - 1) <= 1 )\n goto LABEL_109;\n }\n ++v151;\nLABEL_109:\n v168 += v159;\n v160 -= v151 + 1;\n v165 = v160 - 1;\n if ( (unsigned int)(v160 - 1) <= 1 )\n {\n v137 = v168;\n v138 = v172;\n goto LABEL_111;\n }\n }\n v138 = v172;\n v137 = v168 + 1;\nLABEL_111:\n v169 -= v137 + 1;\n v173 += v138;\n v2 = v169 - 1;\n if ( (unsigned int)(v169 - 1) <= 1 )\n return (unsigned int)(v173 + 1);\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11F0(int a1) {\n long long result;\n int v2;\n int v3;\n int v4;\n unsigned int v5;\n unsigned int v6;\n unsigned int v7;\n int v8;\n int v9;\n long long v10;\n int v11;\n long long v12;\n int v13;\n int v14;\n long long v15;\n long long v16;\n unsigned int v17;\n int v18;\n int v19;\n int v20;\n int v21;\n unsigned int v22;\n int v23;\n unsigned int v24;\n int v25;\n int v26;\n long long v27;\n int v28;\n long long v29;\n int v30;\n int v31;\n long long v32;\n long long v33;\n int v34;\n int v35;\n long long v36;\n int v37;\n int v38;\n long long v39;\n int v40;\n int v41;\n long long v42;\n int v43;\n unsigned int v44;\n int v45;\n unsigned int v46;\n unsigned int v47;\n unsigned int v48;\n unsigned int v49;\n unsigned int v50;\n int v51;\n int v52;\n long long v53;\n int v54;\n long long v55;\n int v56;\n int v57;\n long long v58;\n long long v59;\n unsigned int v60;\n unsigned int v61;\n unsigned int v62;\n unsigned int v63;\n int v64;\n unsigned int v65;\n unsigned int v66;\n int v67;\n int v68;\n long long v69;\n int v70;\n long long v71;\n int v72;\n int v73;\n long long v74;\n long long v75;\n int v76;\n int v77;\n unsigned int v78;\n unsigned int v79;\n unsigned int v80;\n unsigned int v81;\n long long v82;\n long long v83;\n unsigned int v84;\n int v85;\n long long v86;\n long long v87;\n int v88;\n int v89;\n long long v90;\n long long v91;\n int v92;\n int v93;\n int v94;\n int v95;\n int v96;\n int v97;\n int v98;\n unsigned int v99;\n long long v100;\n long long v101;\n unsigned int v102;\n int v103;\n long long v104;\n long long v105;\n int v106;\n int v107;\n long long v108;\n long long v109;\n unsigned int v110;\n unsigned int v111;\n unsigned int v112;\n unsigned int v113;\n long long v114;\n long long v115;\n unsigned int v116;\n int v117;\n long long v118;\n long long v119;\n int v120;\n int v121;\n long long v122;\n long long v123;\n int v124;\n int v125;\n unsigned int v126;\n long long v127;\n long long v128;\n unsigned int v129;\n int v130;\n long long v131;\n long long v132;\n int v133;\n int v134;\n long long v135;\n long long v136;\n int v137;\n int v138;\n unsigned int v139;\n int v140;\n int v141;\n unsigned int v142;\n int v143;\n int v144;\n unsigned int v145;\n int v146;\n int v147;\n unsigned int v148;\n int v149;\n unsigned int v150;\n int v151;\n int v152;\n int v153;\n unsigned int v154;\n unsigned int v155;\n int v156;\n unsigned int v157;\n int v158;\n int v159;\n int v160;\n int v161;\n int v162;\n unsigned int v163;\n unsigned int v164;\n int v165;\n unsigned int v166;\n int v167;\n int v168;\n int v169;\n int v170;\n int v171;\n int v172;\n int v173;\n result = 1LL;\n if ((unsigned int)(a1 - 1) > 1) {\n v169 = a1;\n v2 = a1 - 1;\n v173 = 0;\n while (1) {\n v160 = v2;\n if (v169 == 3) return (unsigned int)(v173 + 2);\n v147 = v2;\n v170 = v2;\n v166 = 0;\n v3 = v169 - 2;\n while (v147 != 3) {\n v152 = v3;\n v4 = v3;\n v161 = v3;\n v5 = 0;\n v6 = v147 - 2;\n while (1) {\n v7 = v6;\n v8 = 0;\n v9 = sub_11F0(v6);\n v10 = (unsigned int)(v9 - 1);\n if ((unsigned int)v10 <= 1) {\n v13 = 1;\n } else {\n v139 = v6;\n v11 = v9;\n do {\n v12 = (unsigned int)sub_11F0(v10);\n v11 -= v12;\n v10 = (unsigned int)(v11 - 1);\n v8 += sub_11F0(v12);\n } while ((unsigned int)v10 > 1);\n v6 = v139;\n v13 = v8 + 1;\n }\n if (v4 == 3) break;\n v14 = 0;\n v15 = v6 - 1;\n do {\n v16 = (unsigned int)sub_11F0(v15);\n v7 -= v16;\n v15 = v7 - 1;\n v14 += sub_11F0(v16);\n } while ((unsigned int)v15 > 1);\n v5 += v13;\n v4 -= v14 + 1;\n v6 = v4 - 1;\n if ((unsigned int)(v4 - 1) <= 1) {\n v17 = v5;\n v18 = v152;\n v19 = v161;\n v20 = v5 + 1;\n if (v5 > 1) goto LABEL_16;\n LABEL_124:\n v34 = 1;\n goto LABEL_27;\n }\n }\n v18 = v152;\n v19 = v161;\n v17 = v13 + v5;\n v20 = v13 + v5 + 1;\n if (v13 + v5 <= 1) goto LABEL_124;\n LABEL_16:\n v153 = v18;\n v21 = 0;\n v22 = v17;\n v162 = v19;\n v23 = v20;\n while (1) {\n v24 = v22;\n v25 = 0;\n v26 = sub_11F0(v22);\n v27 = (unsigned int)(v26 - 1);\n if ((unsigned int)v27 <= 1) {\n v30 = 1;\n } else {\n v140 = v23;\n v28 = v26;\n do {\n v29 = (unsigned int)sub_11F0(v27);\n v28 -= v29;\n v27 = (unsigned int)(v28 - 1);\n v25 += sub_11F0(v29);\n } while ((unsigned int)v27 > 1);\n v23 = v140;\n v30 = v25 + 1;\n }\n if (v23 == 3) break;\n v31 = 0;\n v32 = v22 - 1;\n do {\n v33 = (unsigned int)sub_11F0(v32);\n v24 -= v33;\n v32 = v24 - 1;\n v31 += sub_11F0(v33);\n } while ((unsigned int)v32 > 1);\n v21 += v30;\n v23 -= v31 + 1;\n v22 = v23 - 1;\n if ((unsigned int)(v23 - 1) <= 1) {\n v18 = v153;\n v19 = v162;\n goto LABEL_26;\n }\n }\n v18 = v153;\n v19 = v162;\n v21 += v30;\n LABEL_26:\n v34 = v21 + 1;\n LABEL_27:\n v141 = v34;\n v35 = 0;\n v36 = (unsigned int)(v19 - 1);\n do {\n v37 = sub_11F0(v36);\n v38 = 0;\n v39 = (unsigned int)(v37 - 1);\n v40 = v37;\n v41 = v37;\n if ((unsigned int)v39 <= 1) {\n v43 = 1;\n } else {\n do {\n v42 = (unsigned int)sub_11F0(v39);\n v41 -= v42;\n v39 = (unsigned int)(v41 - 1);\n v38 += sub_11F0(v42);\n } while ((unsigned int)v39 > 1);\n v43 = v38 + 1;\n }\n v18 -= v40;\n v35 += v43;\n v36 = (unsigned int)(v18 - 1);\n } while ((unsigned int)v36 > 1);\n v147 -= v35 + 1;\n v166 += v141;\n v3 = v147 - 1;\n if ((unsigned int)(v147 - 1) <= 1) {\n v44 = v166;\n v45 = v170;\n v148 = v166 + 1;\n if (v166 > 1) goto LABEL_34;\n LABEL_126:\n v95 = 1;\n goto LABEL_72;\n }\n }\n v45 = v170;\n v44 = v166 + 1;\n v148 = v166 + 2;\n if (v166 + 1 <= 1) goto LABEL_126;\n LABEL_34:\n v171 = v45;\n v46 = v44;\n v167 = 0;\n while (v148 != 3) {\n v154 = v46;\n v47 = 0;\n v48 = v46;\n v163 = v46;\n v49 = v148 - 2;\n while (1) {\n v50 = v49;\n v51 = 0;\n v52 = sub_11F0(v49);\n v53 = (unsigned int)(v52 - 1);\n if ((unsigned int)v53 <= 1) {\n v56 = 1;\n } else {\n v142 = v48;\n v54 = v52;\n do {\n v55 = (unsigned int)sub_11F0(v53);\n v54 -= v55;\n v53 = (unsigned int)(v54 - 1);\n v51 += sub_11F0(v55);\n } while ((unsigned int)v53 > 1);\n v48 = v142;\n v56 = v51 + 1;\n }\n if (v48 == 3) break;\n v57 = 0;\n v58 = v49 - 1;\n do {\n v59 = (unsigned int)sub_11F0(v58);\n v50 -= v59;\n v58 = v50 - 1;\n v57 += sub_11F0(v59);\n } while ((unsigned int)v58 > 1);\n v47 += v56;\n v48 -= v57 + 1;\n v49 = v48 - 1;\n if (v48 - 1 <= 1) {\n v60 = v154;\n v61 = v163;\n v62 = v47 + 1;\n if (v47 > 1) goto LABEL_46;\n LABEL_121:\n v77 = 1;\n goto LABEL_57;\n }\n }\n v47 += v56;\n v60 = v154;\n v61 = v163;\n v62 = v47 + 1;\n if (v47 <= 1) goto LABEL_121;\n LABEL_46:\n v155 = v60;\n v63 = v62;\n v164 = v61;\n v64 = 0;\n v65 = v47;\n while (1) {\n v66 = v65;\n v67 = 0;\n v68 = sub_11F0(v65);\n v69 = (unsigned int)(v68 - 1);\n if ((unsigned int)v69 <= 1) {\n v72 = 1;\n } else {\n v70 = v68;\n do {\n v71 = (unsigned int)sub_11F0(v69);\n v70 -= v71;\n v69 = (unsigned int)(v70 - 1);\n v67 += sub_11F0(v71);\n } while ((unsigned int)v69 > 1);\n v66 = v65;\n v72 = v67 + 1;\n }\n if (v63 == 3) break;\n v73 = 0;\n v74 = v65 - 1;\n do {\n v75 = (unsigned int)sub_11F0(v74);\n v66 -= v75;\n v74 = v66 - 1;\n v73 += sub_11F0(v75);\n } while ((unsigned int)v74 > 1);\n v64 += v72;\n v63 -= v73 + 1;\n v65 = v63 - 1;\n if (v63 - 1 <= 1) {\n v60 = v155;\n v61 = v164;\n v76 = v64;\n goto LABEL_56;\n }\n }\n v60 = v155;\n v61 = v164;\n v76 = v72 + v64;\n LABEL_56:\n v77 = v76 + 1;\n LABEL_57:\n v156 = v77;\n v78 = v61 - 1;\n v143 = 0;\n while (1) {\n v79 = v78;\n if (v60 == 3) break;\n v80 = v78;\n v81 = 0;\n v82 = v60 - 2;\n do {\n v83 = (unsigned int)sub_11F0(v82);\n v80 -= v83;\n v82 = v80 - 1;\n v81 += sub_11F0(v83);\n } while ((unsigned int)v82 > 1);\n v84 = v81 + 1;\n if (v81 <= 1) {\n v88 = 1;\n } else {\n v85 = 0;\n v86 = v81;\n do {\n v87 = (unsigned int)sub_11F0(v86);\n v84 -= v87;\n v86 = v84 - 1;\n v85 += sub_11F0(v87);\n } while ((unsigned int)v86 > 1);\n v88 = v85 + 1;\n }\n v89 = 0;\n v90 = v78 - 1;\n do {\n v91 = (unsigned int)sub_11F0(v90);\n v79 -= v91;\n v90 = v79 - 1;\n v89 += sub_11F0(v91);\n } while ((unsigned int)v90 > 1);\n v143 += v88;\n v60 -= v89 + 1;\n v78 = v60 - 1;\n if (v60 - 1 <= 1) {\n v92 = v143;\n v93 = v156;\n goto LABEL_69;\n }\n }\n v93 = v156;\n v92 = v143 + 1;\n LABEL_69:\n v148 -= v92 + 1;\n v167 += v93;\n v46 = v148 - 1;\n if (v148 - 1 <= 1) {\n v94 = v167;\n v45 = v171;\n goto LABEL_71;\n }\n }\n v45 = v171;\n v94 = v167 + 1;\n LABEL_71:\n v95 = v94 + 1;\n LABEL_72:\n v172 = v95;\n v165 = v45 - 1;\n v168 = 0;\n while (1) {\n v96 = v165;\n if (v160 == 3) break;\n v144 = v165;\n v157 = 0;\n v149 = v160 - 2;\n while (1) {\n v97 = v149;\n v98 = v149;\n if (v144 == 3) break;\n v99 = 0;\n v100 = (unsigned int)(v144 - 2);\n do {\n v101 = (unsigned int)sub_11F0(v100);\n v97 -= v101;\n v100 = (unsigned int)(v97 - 1);\n v99 += sub_11F0(v101);\n } while ((unsigned int)v100 > 1);\n v102 = v99 + 1;\n if (v99 <= 1) {\n v106 = 1;\n } else {\n v103 = 0;\n v104 = v99;\n do {\n v105 = (unsigned int)sub_11F0(v104);\n v102 -= v105;\n v104 = v102 - 1;\n v103 += sub_11F0(v105);\n } while ((unsigned int)v104 > 1);\n v106 = v103 + 1;\n }\n v107 = 0;\n v108 = (unsigned int)(v149 - 1);\n do {\n v109 = (unsigned int)sub_11F0(v108);\n v98 -= v109;\n v108 = (unsigned int)(v98 - 1);\n v107 += sub_11F0(v109);\n } while ((unsigned int)v108 > 1);\n v144 -= v107 + 1;\n v157 += v106;\n v149 = v144 - 1;\n if ((unsigned int)(v144 - 1) <= 1) {\n v110 = v157;\n v145 = v157 + 1;\n if (v157 > 1) goto LABEL_86;\n LABEL_117:\n v159 = 1;\n goto LABEL_98;\n }\n }\n v110 = v157 + 1;\n v145 = v157 + 2;\n if (v157 + 1 <= 1) goto LABEL_117;\n LABEL_86:\n v158 = 0;\n v150 = v110;\n while (1) {\n v111 = v150;\n v112 = v150;\n if (v145 == 3) break;\n v113 = 0;\n v114 = v145 - 2;\n do {\n v115 = (unsigned int)sub_11F0(v114);\n v111 -= v115;\n v114 = v111 - 1;\n v113 += sub_11F0(v115);\n } while ((unsigned int)v114 > 1);\n v116 = v113 + 1;\n if (v113 <= 1) {\n v120 = 1;\n } else {\n v117 = 0;\n v118 = v113;\n do {\n v119 = (unsigned int)sub_11F0(v118);\n v116 -= v119;\n v118 = v116 - 1;\n v117 += sub_11F0(v119);\n } while ((unsigned int)v118 > 1);\n v120 = v117 + 1;\n }\n v121 = 0;\n v122 = v150 - 1;\n do {\n v123 = (unsigned int)sub_11F0(v122);\n v112 -= v123;\n v122 = v112 - 1;\n v121 += sub_11F0(v123);\n } while ((unsigned int)v122 > 1);\n v145 -= v121 + 1;\n v158 += v120;\n v150 = v145 - 1;\n if (v145 - 1 <= 1) goto LABEL_97;\n }\n ++v158;\n LABEL_97:\n v159 = v158 + 1;\n LABEL_98:\n v151 = 0;\n v146 = v165 - 1;\n while (1) {\n v124 = v146;\n v125 = v146;\n if (v96 == 3) break;\n v126 = 0;\n v127 = (unsigned int)(v96 - 2);\n do {\n v128 = (unsigned int)sub_11F0(v127);\n v124 -= v128;\n v127 = (unsigned int)(v124 - 1);\n v126 += sub_11F0(v128);\n } while ((unsigned int)v127 > 1);\n v129 = v126 + 1;\n if (v126 <= 1) {\n v133 = 1;\n } else {\n v130 = 0;\n v131 = v126;\n do {\n v132 = (unsigned int)sub_11F0(v131);\n v129 -= v132;\n v131 = v129 - 1;\n v130 += sub_11F0(v132);\n } while ((unsigned int)v131 > 1);\n v133 = v130 + 1;\n }\n v134 = 0;\n v135 = (unsigned int)(v146 - 1);\n do {\n v136 = (unsigned int)sub_11F0(v135);\n v125 -= v136;\n v135 = (unsigned int)(v125 - 1);\n v134 += sub_11F0(v136);\n } while ((unsigned int)v135 > 1);\n v151 += v133;\n v96 -= v134 + 1;\n v146 = v96 - 1;\n if ((unsigned int)(v96 - 1) <= 1) goto LABEL_109;\n }\n ++v151;\n LABEL_109:\n v168 += v159;\n v160 -= v151 + 1;\n v165 = v160 - 1;\n if ((unsigned int)(v160 - 1) <= 1) {\n v137 = v168;\n v138 = v172;\n goto LABEL_111;\n }\n }\n v138 = v172;\n v137 = v168 + 1;\n LABEL_111:\n v169 -= v137 + 1;\n v173 += v138;\n v2 = v169 - 1;\n if ((unsigned int)(v169 - 1) <= 1) return (unsigned int)(v173 + 1);\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n long long result;\n int v2;\n int v3;\n int v4;\n unsigned int v5;\n unsigned int v6;\n unsigned int v7;\n int v8;\n int v9;\n long long v10;\n int v11;\n long long v12;\n int v13;\n int v14;\n long long v15;\n long long v16;\n unsigned int v17;\n int v18;\n int v19;\n int v20;\n int v21;\n unsigned int v22;\n int v23;\n unsigned int v24;\n int v25;\n int v26;\n long long v27;\n int v28;\n long long v29;\n int v30;\n int v31;\n long long v32;\n long long v33;\n int v34;\n int v35;\n long long v36;\n int v37;\n int v38;\n long long v39;\n int v40;\n int v41;\n long long v42;\n int v43;\n unsigned int v44;\n int v45;\n unsigned int v46;\n unsigned int v47;\n unsigned int v48;\n unsigned int v49;\n unsigned int v50;\n int v51;\n int v52;\n long long v53;\n int v54;\n long long v55;\n int v56;\n int v57;\n long long v58;\n long long v59;\n unsigned int v60;\n unsigned int v61;\n unsigned int v62;\n unsigned int v63;\n int v64;\n unsigned int v65;\n unsigned int v66;\n int v67;\n int v68;\n long long v69;\n int v70;\n long long v71;\n int v72;\n int v73;\n long long v74;\n long long v75;\n int v76;\n int v77;\n unsigned int v78;\n unsigned int v79;\n unsigned int v80;\n unsigned int v81;\n long long v82;\n long long v83;\n unsigned int v84;\n int v85;\n long long v86;\n long long v87;\n int v88;\n int v89;\n long long v90;\n long long v91;\n int v92;\n int v93;\n int v94;\n int v95;\n int v96;\n int v97;\n int v98;\n unsigned int v99;\n long long v100;\n long long v101;\n unsigned int v102;\n int v103;\n long long v104;\n long long v105;\n int v106;\n int v107;\n long long v108;\n long long v109;\n unsigned int v110;\n unsigned int v111;\n unsigned int v112;\n unsigned int v113;\n long long v114;\n long long v115;\n unsigned int v116;\n int v117;\n long long v118;\n long long v119;\n int v120;\n int v121;\n long long v122;\n long long v123;\n int v124;\n int v125;\n unsigned int v126;\n long long v127;\n long long v128;\n unsigned int v129;\n int v130;\n long long v131;\n long long v132;\n int v133;\n int v134;\n long long v135;\n long long v136;\n int v137;\n int v138;\n unsigned int v139;\n int v140;\n int v141;\n unsigned int v142;\n int v143;\n int v144;\n unsigned int v145;\n int v146;\n int v147;\n unsigned int v148;\n int v149;\n unsigned int v150;\n int v151;\n int v152;\n int v153;\n unsigned int v154;\n unsigned int v155;\n int v156;\n unsigned int v157;\n int v158;\n int v159;\n int v160;\n int v161;\n int v162;\n unsigned int v163;\n unsigned int v164;\n int v165;\n unsigned int v166;\n int v167;\n int v168;\n int v169;\n int v170;\n int v171;\n int v172;\n int v173;\n result = 1LL;\n if ((unsigned int)(a1 - 1) > 1) {\n v169 = a1;\n v2 = a1 - 1;\n v173 = 0;\n while (1) {\n v160 = v2;\n if (v169 == 3) return (unsigned int)(v173 + 2);\n v147 = v2;\n v170 = v2;\n v166 = 0;\n v3 = v169 - 2;\n while (v147 != 3) {\n v152 = v3;\n v4 = v3;\n v161 = v3;\n v5 = 0;\n v6 = v147 - 2;\n while (1) {\n v7 = v6;\n v8 = 0;\n v9 = func0(v6);\n v10 = (unsigned int)(v9 - 1);\n if ((unsigned int)v10 <= 1) {\n v13 = 1;\n } else {\n v139 = v6;\n v11 = v9;\n do {\n v12 = (unsigned int)func0(v10);\n v11 -= v12;\n v10 = (unsigned int)(v11 - 1);\n v8 += func0(v12);\n } while ((unsigned int)v10 > 1);\n v6 = v139;\n v13 = v8 + 1;\n }\n if (v4 == 3) break;\n v14 = 0;\n v15 = v6 - 1;\n do {\n v16 = (unsigned int)func0(v15);\n v7 -= v16;\n v15 = v7 - 1;\n v14 += func0(v16);\n } while ((unsigned int)v15 > 1);\n v5 += v13;\n v4 -= v14 + 1;\n v6 = v4 - 1;\n if ((unsigned int)(v4 - 1) <= 1) {\n v17 = v5;\n v18 = v152;\n v19 = v161;\n v20 = v5 + 1;\n if (v5 > 1) goto LABEL_16;\n LABEL_124:\n v34 = 1;\n goto LABEL_27;\n }\n }\n v18 = v152;\n v19 = v161;\n v17 = v13 + v5;\n v20 = v13 + v5 + 1;\n if (v13 + v5 <= 1) goto LABEL_124;\n LABEL_16:\n v153 = v18;\n v21 = 0;\n v22 = v17;\n v162 = v19;\n v23 = v20;\n while (1) {\n v24 = v22;\n v25 = 0;\n v26 = func0(v22);\n v27 = (unsigned int)(v26 - 1);\n if ((unsigned int)v27 <= 1) {\n v30 = 1;\n } else {\n v140 = v23;\n v28 = v26;\n do {\n v29 = (unsigned int)func0(v27);\n v28 -= v29;\n v27 = (unsigned int)(v28 - 1);\n v25 += func0(v29);\n } while ((unsigned int)v27 > 1);\n v23 = v140;\n v30 = v25 + 1;\n }\n if (v23 == 3) break;\n v31 = 0;\n v32 = v22 - 1;\n do {\n v33 = (unsigned int)func0(v32);\n v24 -= v33;\n v32 = v24 - 1;\n v31 += func0(v33);\n } while ((unsigned int)v32 > 1);\n v21 += v30;\n v23 -= v31 + 1;\n v22 = v23 - 1;\n if ((unsigned int)(v23 - 1) <= 1) {\n v18 = v153;\n v19 = v162;\n goto LABEL_26;\n }\n }\n v18 = v153;\n v19 = v162;\n v21 += v30;\n LABEL_26:\n v34 = v21 + 1;\n LABEL_27:\n v141 = v34;\n v35 = 0;\n v36 = (unsigned int)(v19 - 1);\n do {\n v37 = func0(v36);\n v38 = 0;\n v39 = (unsigned int)(v37 - 1);\n v40 = v37;\n v41 = v37;\n if ((unsigned int)v39 <= 1) {\n v43 = 1;\n } else {\n do {\n v42 = (unsigned int)func0(v39);\n v41 -= v42;\n v39 = (unsigned int)(v41 - 1);\n v38 += func0(v42);\n } while ((unsigned int)v39 > 1);\n v43 = v38 + 1;\n }\n v18 -= v40;\n v35 += v43;\n v36 = (unsigned int)(v18 - 1);\n } while ((unsigned int)v36 > 1);\n v147 -= v35 + 1;\n v166 += v141;\n v3 = v147 - 1;\n if ((unsigned int)(v147 - 1) <= 1) {\n v44 = v166;\n v45 = v170;\n v148 = v166 + 1;\n if (v166 > 1) goto LABEL_34;\n LABEL_126:\n v95 = 1;\n goto LABEL_72;\n }\n }\n v45 = v170;\n v44 = v166 + 1;\n v148 = v166 + 2;\n if (v166 + 1 <= 1) goto LABEL_126;\n LABEL_34:\n v171 = v45;\n v46 = v44;\n v167 = 0;\n while (v148 != 3) {\n v154 = v46;\n v47 = 0;\n v48 = v46;\n v163 = v46;\n v49 = v148 - 2;\n while (1) {\n v50 = v49;\n v51 = 0;\n v52 = func0(v49);\n v53 = (unsigned int)(v52 - 1);\n if ((unsigned int)v53 <= 1) {\n v56 = 1;\n } else {\n v142 = v48;\n v54 = v52;\n do {\n v55 = (unsigned int)func0(v53);\n v54 -= v55;\n v53 = (unsigned int)(v54 - 1);\n v51 += func0(v55);\n } while ((unsigned int)v53 > 1);\n v48 = v142;\n v56 = v51 + 1;\n }\n if (v48 == 3) break;\n v57 = 0;\n v58 = v49 - 1;\n do {\n v59 = (unsigned int)func0(v58);\n v50 -= v59;\n v58 = v50 - 1;\n v57 += func0(v59);\n } while ((unsigned int)v58 > 1);\n v47 += v56;\n v48 -= v57 + 1;\n v49 = v48 - 1;\n if (v48 - 1 <= 1) {\n v60 = v154;\n v61 = v163;\n v62 = v47 + 1;\n if (v47 > 1) goto LABEL_46;\n LABEL_121:\n v77 = 1;\n goto LABEL_57;\n }\n }\n v47 += v56;\n v60 = v154;\n v61 = v163;\n v62 = v47 + 1;\n if (v47 <= 1) goto LABEL_121;\n LABEL_46:\n v155 = v60;\n v63 = v62;\n v164 = v61;\n v64 = 0;\n v65 = v47;\n while (1) {\n v66 = v65;\n v67 = 0;\n v68 = func0(v65);\n v69 = (unsigned int)(v68 - 1);\n if ((unsigned int)v69 <= 1) {\n v72 = 1;\n } else {\n v70 = v68;\n do {\n v71 = (unsigned int)func0(v69);\n v70 -= v71;\n v69 = (unsigned int)(v70 - 1);\n v67 += func0(v71);\n } while ((unsigned int)v69 > 1);\n v66 = v65;\n v72 = v67 + 1;\n }\n if (v63 == 3) break;\n v73 = 0;\n v74 = v65 - 1;\n do {\n v75 = (unsigned int)func0(v74);\n v66 -= v75;\n v74 = v66 - 1;\n v73 += func0(v75);\n } while ((unsigned int)v74 > 1);\n v64 += v72;\n v63 -= v73 + 1;\n v65 = v63 - 1;\n if (v63 - 1 <= 1) {\n v60 = v155;\n v61 = v164;\n v76 = v64;\n goto LABEL_56;\n }\n }\n v60 = v155;\n v61 = v164;\n v76 = v72 + v64;\n LABEL_56:\n v77 = v76 + 1;\n LABEL_57:\n v156 = v77;\n v78 = v61 - 1;\n v143 = 0;\n while (1) {\n v79 = v78;\n if (v60 == 3) break;\n v80 = v78;\n v81 = 0;\n v82 = v60 - 2;\n do {\n v83 = (unsigned int)func0(v82);\n v80 -= v83;\n v82 = v80 - 1;\n v81 += func0(v83);\n } while ((unsigned int)v82 > 1);\n v84 = v81 + 1;\n if (v81 <= 1) {\n v88 = 1;\n } else {\n v85 = 0;\n v86 = v81;\n do {\n v87 = (unsigned int)func0(v86);\n v84 -= v87;\n v86 = v84 - 1;\n v85 += func0(v87);\n } while ((unsigned int)v86 > 1);\n v88 = v85 + 1;\n }\n v89 = 0;\n v90 = v78 - 1;\n do {\n v91 = (unsigned int)func0(v90);\n v79 -= v91;\n v90 = v79 - 1;\n v89 += func0(v91);\n } while ((unsigned int)v90 > 1);\n v143 += v88;\n v60 -= v89 + 1;\n v78 = v60 - 1;\n if (v60 - 1 <= 1) {\n v92 = v143;\n v93 = v156;\n goto LABEL_69;\n }\n }\n v93 = v156;\n v92 = v143 + 1;\n LABEL_69:\n v148 -= v92 + 1;\n v167 += v93;\n v46 = v148 - 1;\n if (v148 - 1 <= 1) {\n v94 = v167;\n v45 = v171;\n goto LABEL_71;\n }\n }\n v45 = v171;\n v94 = v167 + 1;\n LABEL_71:\n v95 = v94 + 1;\n LABEL_72:\n v172 = v95;\n v165 = v45 - 1;\n v168 = 0;\n while (1) {\n v96 = v165;\n if (v160 == 3) break;\n v144 = v165;\n v157 = 0;\n v149 = v160 - 2;\n while (1) {\n v97 = v149;\n v98 = v149;\n if (v144 == 3) break;\n v99 = 0;\n v100 = (unsigned int)(v144 - 2);\n do {\n v101 = (unsigned int)func0(v100);\n v97 -= v101;\n v100 = (unsigned int)(v97 - 1);\n v99 += func0(v101);\n } while ((unsigned int)v100 > 1);\n v102 = v99 + 1;\n if (v99 <= 1) {\n v106 = 1;\n } else {\n v103 = 0;\n v104 = v99;\n do {\n v105 = (unsigned int)func0(v104);\n v102 -= v105;\n v104 = v102 - 1;\n v103 += func0(v105);\n } while ((unsigned int)v104 > 1);\n v106 = v103 + 1;\n }\n v107 = 0;\n v108 = (unsigned int)(v149 - 1);\n do {\n v109 = (unsigned int)func0(v108);\n v98 -= v109;\n v108 = (unsigned int)(v98 - 1);\n v107 += func0(v109);\n } while ((unsigned int)v108 > 1);\n v144 -= v107 + 1;\n v157 += v106;\n v149 = v144 - 1;\n if ((unsigned int)(v144 - 1) <= 1) {\n v110 = v157;\n v145 = v157 + 1;\n if (v157 > 1) goto LABEL_86;\n LABEL_117:\n v159 = 1;\n goto LABEL_98;\n }\n }\n v110 = v157 + 1;\n v145 = v157 + 2;\n if (v157 + 1 <= 1) goto LABEL_117;\n LABEL_86:\n v158 = 0;\n v150 = v110;\n while (1) {\n v111 = v150;\n v112 = v150;\n if (v145 == 3) break;\n v113 = 0;\n v114 = v145 - 2;\n do {\n v115 = (unsigned int)func0(v114);\n v111 -= v115;\n v114 = v111 - 1;\n v113 += func0(v115);\n } while ((unsigned int)v114 > 1);\n v116 = v113 + 1;\n if (v113 <= 1) {\n v120 = 1;\n } else {\n v117 = 0;\n v118 = v113;\n do {\n v119 = (unsigned int)func0(v118);\n v116 -= v119;\n v118 = v116 - 1;\n v117 += func0(v119);\n } while ((unsigned int)v118 > 1);\n v120 = v117 + 1;\n }\n v121 = 0;\n v122 = v150 - 1;\n do {\n v123 = (unsigned int)func0(v122);\n v112 -= v123;\n v122 = v112 - 1;\n v121 += func0(v123);\n } while ((unsigned int)v122 > 1);\n v145 -= v121 + 1;\n v158 += v120;\n v150 = v145 - 1;\n if (v145 - 1 <= 1) goto LABEL_97;\n }\n ++v158;\n LABEL_97:\n v159 = v158 + 1;\n LABEL_98:\n v151 = 0;\n v146 = v165 - 1;\n while (1) {\n v124 = v146;\n v125 = v146;\n if (v96 == 3) break;\n v126 = 0;\n v127 = (unsigned int)(v96 - 2);\n do {\n v128 = (unsigned int)func0(v127);\n v124 -= v128;\n v127 = (unsigned int)(v124 - 1);\n v126 += func0(v128);\n } while ((unsigned int)v127 > 1);\n v129 = v126 + 1;\n if (v126 <= 1) {\n v133 = 1;\n } else {\n v130 = 0;\n v131 = v126;\n do {\n v132 = (unsigned int)func0(v131);\n v129 -= v132;\n v131 = v129 - 1;\n v130 += func0(v132);\n } while ((unsigned int)v131 > 1);\n v133 = v130 + 1;\n }\n v134 = 0;\n v135 = (unsigned int)(v146 - 1);\n do {\n v136 = (unsigned int)func0(v135);\n v125 -= v136;\n v135 = (unsigned int)(v125 - 1);\n v134 += func0(v136);\n } while ((unsigned int)v135 > 1);\n v151 += v133;\n v96 -= v134 + 1;\n v146 = v96 - 1;\n if ((unsigned int)(v96 - 1) <= 1) goto LABEL_109;\n }\n ++v151;\n LABEL_109:\n v168 += v159;\n v160 -= v151 + 1;\n v165 = v160 - 1;\n if ((unsigned int)(v160 - 1) <= 1) {\n v137 = v168;\n v138 = v172;\n goto LABEL_111;\n }\n }\n v138 = v172;\n v137 = v168 + 1;\n LABEL_111:\n v169 -= v137 + 1;\n v173 += v138;\n v2 = v169 - 1;\n if ((unsigned int)(v169 - 1) <= 1) return (unsigned int)(v173 + 1);\n }\n }\n return result;\n}" + }, + { + "index": 85, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "double func0(double r) {\n double surfacearea = 4 * M_PI * r * r;\n return surfacearea;\n}", + "test": "int main() {\n\n assert(func0(10) == 1256.6370614359173);\n\n assert(func0(15) == 2827.4333882308138);\n\n assert(func0(20) == 5026.548245743669);\n\n printf(\"All tests passed successfully!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmovsd %xmm0,-0x18(%rbp)\nmovsd -0x18(%rbp),%xmm1\nmovsd 0xf4d(%rip),%xmm0\nmulsd %xmm1,%xmm0\nmovsd -0x18(%rbp),%xmm1\nmulsd %xmm1,%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmovsd -0x8(%rbp),%xmm0\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmovsd [rbp+var_18], xmm0\nmovsd xmm1, [rbp+var_18]\nmovsd xmm0, cs:qword_20B0\nmulsd xmm0, xmm1\nmovsd xmm1, [rbp+var_18]\nmulsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "double __fastcall func0(double a1)\n{\n return 12.56637061435917 * a1 * a1;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmovsd [rbp+var_18], xmm0\nmovsd xmm1, [rbp+var_18]\nmovsd xmm0, cs:qword_20B0\nmulsd xmm0, xmm1\nmovsd xmm1, [rbp+var_18]\nmulsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "double __fastcall sub_1169(double a1)\n{\n return 12.56637061435917 * a1 * a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1169(double a1) { return 12.56637061435917 * a1 * a1; }", + "ida_pseudo_norm": "double func0(double a1) { return 12.56637061435917 * a1 * a1; }" + }, + { + "index": 86, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) { return 3 * n * (n - 1) + 1; }", + "test": "int main() {\n\n assert(func0(10) == 271);\n\n assert(func0(2) == 7);\n\n assert(func0(9) == 217);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nsub $0x1,%eax\nimul -0x4(%rbp),%eax\nmov %eax,%edx\nmov %edx,%eax\nadd %eax,%eax\nadd %edx,%eax\nadd $0x1,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov eax, [rbp+var_4]\nsub eax, 1\nimul eax, [rbp+var_4]\nmov edx, eax\nmov eax, edx\nadd eax, eax\nadd eax, edx\nadd eax, 1\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n return (unsigned int)(3 * a1 * (a1 - 1) + 1);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov eax, [rbp+var_4]\nsub eax, 1\nimul eax, [rbp+var_4]\nmov edx, eax\nmov eax, edx\nadd eax, eax\nadd eax, edx\nadd eax, 1\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n return (unsigned int)(3 * a1 * (a1 - 1) + 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) { return (unsigned int)(3 * a1 * (a1 - 1) + 1); }", + "ida_pseudo_norm": "long long func0(int a1) { return (unsigned int)(3 * a1 * (a1 - 1) + 1); }" + }, + { + "index": 87, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char *key;\n\n char *value;\n\n} KeyValuePair;\n\n\n\ntypedef struct {\n\n KeyValuePair *pairs;\n\n int size;\n\n} Dictionary;\n\n\n\n", + "func": "Dictionary func0(Dictionary dict1, Dictionary dict2, Dictionary dict3) {\n Dictionary result;\n result.pairs =\n malloc(sizeof(KeyValuePair) * (dict1.size + dict2.size + dict3.size));\n result.size = 0;\n for (int i = 0; i < dict1.size; i++) {\n int found = 0;\n for (int j = 0; j < result.size; j++) {\n if (strcmp(dict1.pairs[i].key, result.pairs[j].key) == 0) {\n found = 1;\n break;\n }\n }\n if (!found) {\n result.pairs[result.size++] = dict1.pairs[i];\n }\n }\n for (int i = 0; i < dict2.size; i++) {\n int found = 0;\n for (int j = 0; j < result.size; j++) {\n if (strcmp(dict2.pairs[i].key, result.pairs[j].key) == 0) {\n found = 1;\n break;\n }\n }\n if (!found) {\n result.pairs[result.size++] = dict2.pairs[i];\n }\n }\n for (int i = 0; i < dict3.size; i++) {\n int found = 0;\n for (int j = 0; j < result.size; j++) {\n if (strcmp(dict3.pairs[i].key, result.pairs[j].key) == 0) {\n found = 1;\n break;\n }\n }\n if (!found) {\n result.pairs[result.size++] = dict3.pairs[i];\n }\n }\n return result;\n}", + "test": "int main() {\n\n KeyValuePair pairs1[] = {{\"R\", \"Red\"}, {\"B\", \"Black\"}, {\"P\", \"Pink\"}};\n\n KeyValuePair pairs2[] = {{\"G\", \"Green\"}, {\"W\", \"White\"}};\n\n KeyValuePair pairs3[] = {{\"O\", \"Orange\"}, {\"W\", \"White\"}, {\"B\", \"Black\"}};\n\n\n\n Dictionary dict1 = {pairs1, 3};\n\n Dictionary dict2 = {pairs2, 2};\n\n Dictionary dict3 = {pairs3, 3};\n\n\n\n Dictionary result = func0(dict1, dict2, dict3);\n\n assert(result.size == 6);\n\n\n\n KeyValuePair pairs4[] = {{\"L\", \"lavender\"}, {\"B\", \"Blue\"}};\n\n Dictionary dict4 = {pairs4, 2};\n\n \n\n result = func0(dict1, dict2, dict4);\n\n assert(result.size == 6);\n\n\n\n result = func0(dict1, dict4, dict2);\n\n assert(result.size == 6);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x70,%rsp\nmov %rsi,%rax\nmov %rdi,%r10\nmov %r10,%rsi\nmov %r11,%rdi\nmov %rax,%rdi\nmov %rsi,-0x50(%rbp)\nmov %rdi,-0x48(%rbp)\nmov %rdx,-0x60(%rbp)\nmov %rcx,-0x58(%rbp)\nmov %r8,-0x70(%rbp)\nmov %r9,-0x68(%rbp)\nmov -0x48(%rbp),%edx\nmov -0x58(%rbp),%eax\nadd %eax,%edx\nmov -0x68(%rbp),%eax\nadd %edx,%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x10(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x34(%rbp)\njmpq 12aa \nmovl $0x0,-0x30(%rbp)\nmovl $0x0,-0x2c(%rbp)\njmp 1262 \nmov -0x10(%rbp),%rax\nmov -0x2c(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x4,%rdx\nadd %rdx,%rax\nmov (%rax),%rdx\nmov -0x50(%rbp),%rax\nmov -0x34(%rbp),%ecx\nmovslq %ecx,%rcx\nshl $0x4,%rcx\nadd %rcx,%rax\nmov (%rax),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10a0 \ntest %eax,%eax\njne 125e \nmovl $0x1,-0x30(%rbp)\njmp 126a \naddl $0x1,-0x2c(%rbp)\nmov -0x8(%rbp),%eax\ncmp %eax,-0x2c(%rbp)\njl 121e \ncmpl $0x0,-0x30(%rbp)\njne 12a6 \nmov -0x50(%rbp),%rax\nmov -0x34(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x4,%rdx\nlea (%rax,%rdx,1),%rsi\nmov -0x10(%rbp),%rcx\nmov -0x8(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x8(%rbp)\ncltq\nshl $0x4,%rax\nadd %rax,%rcx\nmov (%rsi),%rax\nmov 0x8(%rsi),%rdx\nmov %rax,(%rcx)\nmov %rdx,0x8(%rcx)\naddl $0x1,-0x34(%rbp)\nmov -0x48(%rbp),%eax\ncmp %eax,-0x34(%rbp)\njl 120e \nmovl $0x0,-0x28(%rbp)\njmpq 135e \nmovl $0x0,-0x24(%rbp)\nmovl $0x0,-0x20(%rbp)\njmp 1316 \nmov -0x10(%rbp),%rax\nmov -0x20(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x4,%rdx\nadd %rdx,%rax\nmov (%rax),%rdx\nmov -0x60(%rbp),%rax\nmov -0x28(%rbp),%ecx\nmovslq %ecx,%rcx\nshl $0x4,%rcx\nadd %rcx,%rax\nmov (%rax),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10a0 \ntest %eax,%eax\njne 1312 \nmovl $0x1,-0x24(%rbp)\njmp 131e \naddl $0x1,-0x20(%rbp)\nmov -0x8(%rbp),%eax\ncmp %eax,-0x20(%rbp)\njl 12d2 \ncmpl $0x0,-0x24(%rbp)\njne 135a \nmov -0x60(%rbp),%rax\nmov -0x28(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x4,%rdx\nlea (%rax,%rdx,1),%rsi\nmov -0x10(%rbp),%rcx\nmov -0x8(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x8(%rbp)\ncltq\nshl $0x4,%rax\nadd %rax,%rcx\nmov (%rsi),%rax\nmov 0x8(%rsi),%rdx\nmov %rax,(%rcx)\nmov %rdx,0x8(%rcx)\naddl $0x1,-0x28(%rbp)\nmov -0x58(%rbp),%eax\ncmp %eax,-0x28(%rbp)\njl 12c2 \nmovl $0x0,-0x1c(%rbp)\njmpq 1412 \nmovl $0x0,-0x18(%rbp)\nmovl $0x0,-0x14(%rbp)\njmp 13ca \nmov -0x10(%rbp),%rax\nmov -0x14(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x4,%rdx\nadd %rdx,%rax\nmov (%rax),%rdx\nmov -0x70(%rbp),%rax\nmov -0x1c(%rbp),%ecx\nmovslq %ecx,%rcx\nshl $0x4,%rcx\nadd %rcx,%rax\nmov (%rax),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10a0 \ntest %eax,%eax\njne 13c6 \nmovl $0x1,-0x18(%rbp)\njmp 13d2 \naddl $0x1,-0x14(%rbp)\nmov -0x8(%rbp),%eax\ncmp %eax,-0x14(%rbp)\njl 1386 \ncmpl $0x0,-0x18(%rbp)\njne 140e \nmov -0x70(%rbp),%rax\nmov -0x1c(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x4,%rdx\nlea (%rax,%rdx,1),%rsi\nmov -0x10(%rbp),%rcx\nmov -0x8(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x8(%rbp)\ncltq\nshl $0x4,%rax\nadd %rax,%rcx\nmov (%rsi),%rax\nmov 0x8(%rsi),%rdx\nmov %rax,(%rcx)\nmov %rdx,0x8(%rcx)\naddl $0x1,-0x1c(%rbp)\nmov -0x68(%rbp),%eax\ncmp %eax,-0x1c(%rbp)\njl 1376 \nmov -0x10(%rbp),%rax\nmov -0x8(%rbp),%rdx\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov rax, rdi\nmov r10, rsi\nmov rsi, rax\nmov rdi, rdx\nmov rdi, r10\nmov [rbp+var_50], rsi\nmov [rbp+var_48], rdi\nmov [rbp+var_60], rdx\nmov [rbp+var_58], rcx\nmov [rbp+var_70], r8\nmov [rbp+var_68], r9\nmov edx, dword ptr [rbp+var_48]\nmov eax, dword ptr [rbp+var_58]\nadd edx, eax\nmov eax, dword ptr [rbp+var_68]\nadd eax, edx\ncdqe\nshl rax, 4\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_10], rax\nmov dword ptr [rbp+var_8], 0\nmov [rbp+var_34], 0\njmp loc_12AA\nloc_120E:\nmov [rbp+var_30], 0\nmov [rbp+var_2C], 0\njmp short loc_1262\nloc_121E:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_2C]\nmovsxd rdx, edx\nshl rdx, 4\nadd rax, rdx\nmov rdx, [rax]\nmov rax, [rbp+var_50]\nmov ecx, [rbp+var_34]\nmovsxd rcx, ecx\nshl rcx, 4\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_125E\nmov [rbp+var_30], 1\njmp short loc_126A\nloc_125E:\nadd [rbp+var_2C], 1\nloc_1262:\nmov eax, dword ptr [rbp+var_8]\ncmp [rbp+var_2C], eax\njl short loc_121E\nloc_126A:\ncmp [rbp+var_30], 0\njnz short loc_12A6\nmov rax, [rbp+var_50]\nmov edx, [rbp+var_34]\nmovsxd rdx, edx\nshl rdx, 4\nlea rsi, [rax+rdx]\nmov rcx, [rbp+var_10]\nmov eax, dword ptr [rbp+var_8]\nlea edx, [rax+1]\nmov dword ptr [rbp+var_8], edx\ncdqe\nshl rax, 4\nadd rcx, rax\nmov rax, [rsi]\nmov rdx, [rsi+8]\nmov [rcx], rax\nmov [rcx+8], rdx\nloc_12A6:\nadd [rbp+var_34], 1\nloc_12AA:\nmov eax, dword ptr [rbp+var_48]\ncmp [rbp+var_34], eax\njl loc_120E\nmov [rbp+var_28], 0\njmp loc_135E\nloc_12C2:\nmov [rbp+var_24], 0\nmov [rbp+var_20], 0\njmp short loc_1316\nloc_12D2:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nshl rdx, 4\nadd rax, rdx\nmov rdx, [rax]\nmov rax, [rbp+var_60]\nmov ecx, [rbp+var_28]\nmovsxd rcx, ecx\nshl rcx, 4\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1312\nmov [rbp+var_24], 1\njmp short loc_131E\nloc_1312:\nadd [rbp+var_20], 1\nloc_1316:\nmov eax, dword ptr [rbp+var_8]\ncmp [rbp+var_20], eax\njl short loc_12D2\nloc_131E:\ncmp [rbp+var_24], 0\njnz short loc_135A\nmov rax, [rbp+var_60]\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nshl rdx, 4\nlea rsi, [rax+rdx]\nmov rcx, [rbp+var_10]\nmov eax, dword ptr [rbp+var_8]\nlea edx, [rax+1]\nmov dword ptr [rbp+var_8], edx\ncdqe\nshl rax, 4\nadd rcx, rax\nmov rax, [rsi]\nmov rdx, [rsi+8]\nmov [rcx], rax\nmov [rcx+8], rdx\nloc_135A:\nadd [rbp+var_28], 1\nloc_135E:\nmov eax, dword ptr [rbp+var_58]\ncmp [rbp+var_28], eax\njl loc_12C2\nmov [rbp+var_1C], 0\njmp loc_1412\nloc_1376:\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp short loc_13CA\nloc_1386:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nshl rdx, 4\nadd rax, rdx\nmov rdx, [rax]\nmov rax, [rbp+var_70]\nmov ecx, [rbp+var_1C]\nmovsxd rcx, ecx\nshl rcx, 4\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_13C6\nmov [rbp+var_18], 1\njmp short loc_13D2\nloc_13C6:\nadd [rbp+var_14], 1\nloc_13CA:\nmov eax, dword ptr [rbp+var_8]\ncmp [rbp+var_14], eax\njl short loc_1386\nloc_13D2:\ncmp [rbp+var_18], 0\njnz short loc_140E\nmov rax, [rbp+var_70]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nshl rdx, 4\nlea rsi, [rax+rdx]\nmov rcx, [rbp+var_10]\nmov eax, dword ptr [rbp+var_8]\nlea edx, [rax+1]\nmov dword ptr [rbp+var_8], edx\ncdqe\nshl rax, 4\nadd rcx, rax\nmov rax, [rsi]\nmov rdx, [rsi+8]\nmov [rcx], rax\nmov [rcx+8], rdx\nloc_140E:\nadd [rbp+var_1C], 1\nloc_1412:\nmov eax, dword ptr [rbp+var_68]\ncmp [rbp+var_1C], eax\njl loc_1376\nmov rax, [rbp+var_10]\nmov rdx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "const char **__fastcall func0(__int64 a1, int a2, __int64 a3, int a4, __int64 a5, int a6)\n{\n const char **v6; // rsi\n int v7; // eax\n const char **v8; // rcx\n const char *v9; // rdx\n const char **v10; // rsi\n int v11; // eax\n const char **v12; // rcx\n const char *v13; // rdx\n const char **v14; // rsi\n int v15; // eax\n const char **v16; // rcx\n const char *v17; // rdx\n int i; // [rsp+3Ch] [rbp-34h]\n int v25; // [rsp+40h] [rbp-30h]\n int j; // [rsp+44h] [rbp-2Ch]\n int k; // [rsp+48h] [rbp-28h]\n int v28; // [rsp+4Ch] [rbp-24h]\n int m; // [rsp+50h] [rbp-20h]\n int n; // [rsp+54h] [rbp-1Ch]\n int v31; // [rsp+58h] [rbp-18h]\n int ii; // [rsp+5Ch] [rbp-14h]\n const char **v33; // [rsp+60h] [rbp-10h]\n int v34; // [rsp+68h] [rbp-8h]\n\n v33 = (const char **)malloc(16LL * (a4 + a2 + a6));\n v34 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v25 = 0;\n for ( j = 0; j < v34; ++j )\n {\n if ( !strcmp(*(const char **)(16LL * i + a1), v33[2 * j]) )\n {\n v25 = 1;\n break;\n }\n }\n if ( !v25 )\n {\n v6 = (const char **)(a1 + 16LL * i);\n v7 = v34++;\n v8 = &v33[2 * v7];\n v9 = v6[1];\n *v8 = *v6;\n v8[1] = v9;\n }\n }\n for ( k = 0; k < a4; ++k )\n {\n v28 = 0;\n for ( m = 0; m < v34; ++m )\n {\n if ( !strcmp(*(const char **)(16LL * k + a3), v33[2 * m]) )\n {\n v28 = 1;\n break;\n }\n }\n if ( !v28 )\n {\n v10 = (const char **)(a3 + 16LL * k);\n v11 = v34++;\n v12 = &v33[2 * v11];\n v13 = v10[1];\n *v12 = *v10;\n v12[1] = v13;\n }\n }\n for ( n = 0; n < a6; ++n )\n {\n v31 = 0;\n for ( ii = 0; ii < v34; ++ii )\n {\n if ( !strcmp(*(const char **)(16LL * n + a5), v33[2 * ii]) )\n {\n v31 = 1;\n break;\n }\n }\n if ( !v31 )\n {\n v14 = (const char **)(a5 + 16LL * n);\n v15 = v34++;\n v16 = &v33[2 * v15];\n v17 = v14[1];\n *v16 = *v14;\n v16[1] = v17;\n }\n }\n return v33;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov rax, rdi\nmov r10, rsi\nmov rsi, rax\nmov rdi, rdx\nmov rdi, r10\nmov [rbp+var_50], rsi\nmov [rbp+var_48], rdi\nmov [rbp+var_60], rdx\nmov [rbp+var_58], rcx\nmov [rbp+var_70], r8\nmov [rbp+var_68], r9\nmov edx, dword ptr [rbp+var_48]\nmov eax, dword ptr [rbp+var_58]\nadd edx, eax\nmov eax, dword ptr [rbp+var_68]\nadd eax, edx\ncdqe\nshl rax, 4\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_10], rax\nmov dword ptr [rbp+var_8], 0\nmov [rbp+var_34], 0\njmp loc_12AA\nloc_120E:\nmov [rbp+var_30], 0\nmov [rbp+var_2C], 0\njmp short loc_1262\nloc_121E:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_2C]\nmovsxd rdx, edx\nshl rdx, 4\nadd rax, rdx\nmov rdx, [rax]\nmov rax, [rbp+var_50]\nmov ecx, [rbp+var_34]\nmovsxd rcx, ecx\nshl rcx, 4\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_125E\nmov [rbp+var_30], 1\njmp short loc_126A\nloc_125E:\nadd [rbp+var_2C], 1\nloc_1262:\nmov eax, dword ptr [rbp+var_8]\ncmp [rbp+var_2C], eax\njl short loc_121E\nloc_126A:\ncmp [rbp+var_30], 0\njnz short loc_12A6\nmov rax, [rbp+var_50]\nmov edx, [rbp+var_34]\nmovsxd rdx, edx\nshl rdx, 4\nlea rsi, [rax+rdx]\nmov rcx, [rbp+var_10]\nmov eax, dword ptr [rbp+var_8]\nlea edx, [rax+1]\nmov dword ptr [rbp+var_8], edx\ncdqe\nshl rax, 4\nadd rcx, rax\nmov rax, [rsi]\nmov rdx, [rsi+8]\nmov [rcx], rax\nmov [rcx+8], rdx\nloc_12A6:\nadd [rbp+var_34], 1\nloc_12AA:\nmov eax, dword ptr [rbp+var_48]\ncmp [rbp+var_34], eax\njl loc_120E\nmov [rbp+var_28], 0\njmp loc_135E\nloc_12C2:\nmov [rbp+var_24], 0\nmov [rbp+var_20], 0\njmp short loc_1316\nloc_12D2:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nshl rdx, 4\nadd rax, rdx\nmov rdx, [rax]\nmov rax, [rbp+var_60]\nmov ecx, [rbp+var_28]\nmovsxd rcx, ecx\nshl rcx, 4\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1312\nmov [rbp+var_24], 1\njmp short loc_131E\nloc_1312:\nadd [rbp+var_20], 1\nloc_1316:\nmov eax, dword ptr [rbp+var_8]\ncmp [rbp+var_20], eax\njl short loc_12D2\nloc_131E:\ncmp [rbp+var_24], 0\njnz short loc_135A\nmov rax, [rbp+var_60]\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nshl rdx, 4\nlea rsi, [rax+rdx]\nmov rcx, [rbp+var_10]\nmov eax, dword ptr [rbp+var_8]\nlea edx, [rax+1]\nmov dword ptr [rbp+var_8], edx\ncdqe\nshl rax, 4\nadd rcx, rax\nmov rax, [rsi]\nmov rdx, [rsi+8]\nmov [rcx], rax\nmov [rcx+8], rdx\nloc_135A:\nadd [rbp+var_28], 1\nloc_135E:\nmov eax, dword ptr [rbp+var_58]\ncmp [rbp+var_28], eax\njl loc_12C2\nmov [rbp+var_1C], 0\njmp loc_1412\nloc_1376:\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp short loc_13CA\nloc_1386:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nshl rdx, 4\nadd rax, rdx\nmov rdx, [rax]\nmov rax, [rbp+var_70]\nmov ecx, [rbp+var_1C]\nmovsxd rcx, ecx\nshl rcx, 4\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_13C6\nmov [rbp+var_18], 1\njmp short loc_13D2\nloc_13C6:\nadd [rbp+var_14], 1\nloc_13CA:\nmov eax, dword ptr [rbp+var_8]\ncmp [rbp+var_14], eax\njl short loc_1386\nloc_13D2:\ncmp [rbp+var_18], 0\njnz short loc_140E\nmov rax, [rbp+var_70]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nshl rdx, 4\nlea rsi, [rax+rdx]\nmov rcx, [rbp+var_10]\nmov eax, dword ptr [rbp+var_8]\nlea edx, [rax+1]\nmov dword ptr [rbp+var_8], edx\ncdqe\nshl rax, 4\nadd rcx, rax\nmov rax, [rsi]\nmov rdx, [rsi+8]\nmov [rcx], rax\nmov [rcx+8], rdx\nloc_140E:\nadd [rbp+var_1C], 1\nloc_1412:\nmov eax, dword ptr [rbp+var_68]\ncmp [rbp+var_1C], eax\njl loc_1376\nmov rax, [rbp+var_10]\nmov rdx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "const char **__fastcall sub_11A9(__int64 a1, int a2, __int64 a3, int a4, __int64 a5, int a6)\n{\n const char **v6; // rsi\n int v7; // eax\n const char **v8; // rcx\n const char *v9; // rdx\n const char **v10; // rsi\n int v11; // eax\n const char **v12; // rcx\n const char *v13; // rdx\n const char **v14; // rsi\n int v15; // eax\n const char **v16; // rcx\n const char *v17; // rdx\n int i; // [rsp+3Ch] [rbp-34h]\n int v25; // [rsp+40h] [rbp-30h]\n int j; // [rsp+44h] [rbp-2Ch]\n int k; // [rsp+48h] [rbp-28h]\n int v28; // [rsp+4Ch] [rbp-24h]\n int m; // [rsp+50h] [rbp-20h]\n int n; // [rsp+54h] [rbp-1Ch]\n int v31; // [rsp+58h] [rbp-18h]\n int ii; // [rsp+5Ch] [rbp-14h]\n const char **v33; // [rsp+60h] [rbp-10h]\n int v34; // [rsp+68h] [rbp-8h]\n\n v33 = (const char **)malloc(16LL * (a4 + a2 + a6));\n v34 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v25 = 0;\n for ( j = 0; j < v34; ++j )\n {\n if ( !strcmp(*(const char **)(16LL * i + a1), v33[2 * j]) )\n {\n v25 = 1;\n break;\n }\n }\n if ( !v25 )\n {\n v6 = (const char **)(a1 + 16LL * i);\n v7 = v34++;\n v8 = &v33[2 * v7];\n v9 = v6[1];\n *v8 = *v6;\n v8[1] = v9;\n }\n }\n for ( k = 0; k < a4; ++k )\n {\n v28 = 0;\n for ( m = 0; m < v34; ++m )\n {\n if ( !strcmp(*(const char **)(16LL * k + a3), v33[2 * m]) )\n {\n v28 = 1;\n break;\n }\n }\n if ( !v28 )\n {\n v10 = (const char **)(a3 + 16LL * k);\n v11 = v34++;\n v12 = &v33[2 * v11];\n v13 = v10[1];\n *v12 = *v10;\n v12[1] = v13;\n }\n }\n for ( n = 0; n < a6; ++n )\n {\n v31 = 0;\n for ( ii = 0; ii < v34; ++ii )\n {\n if ( !strcmp(*(const char **)(16LL * n + a5), v33[2 * ii]) )\n {\n v31 = 1;\n break;\n }\n }\n if ( !v31 )\n {\n v14 = (const char **)(a5 + 16LL * n);\n v15 = v34++;\n v16 = &v33[2 * v15];\n v17 = v14[1];\n *v16 = *v14;\n v16[1] = v17;\n }\n }\n return v33;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char **sub_11A9(long long a1, int a2, long long a3, int a4, long long a5,\n int a6) {\n const char **v6;\n int v7;\n const char **v8;\n const char *v9;\n const char **v10;\n int v11;\n const char **v12;\n const char *v13;\n const char **v14;\n int v15;\n const char **v16;\n const char *v17;\n int i;\n int v25;\n int j;\n int k;\n int v28;\n int m;\n int n;\n int v31;\n int ii;\n const char **v33;\n int v34;\n v33 = (const char **)malloc(16LL * (a4 + a2 + a6));\n v34 = 0;\n for (i = 0; i < a2; ++i) {\n v25 = 0;\n for (j = 0; j < v34; ++j) {\n if (!strcmp(*(const char **)(16LL * i + a1), v33[2 * j])) {\n v25 = 1;\n break;\n }\n }\n if (!v25) {\n v6 = (const char **)(a1 + 16LL * i);\n v7 = v34++;\n v8 = &v33[2 * v7];\n v9 = v6[1];\n *v8 = *v6;\n v8[1] = v9;\n }\n }\n for (k = 0; k < a4; ++k) {\n v28 = 0;\n for (m = 0; m < v34; ++m) {\n if (!strcmp(*(const char **)(16LL * k + a3), v33[2 * m])) {\n v28 = 1;\n break;\n }\n }\n if (!v28) {\n v10 = (const char **)(a3 + 16LL * k);\n v11 = v34++;\n v12 = &v33[2 * v11];\n v13 = v10[1];\n *v12 = *v10;\n v12[1] = v13;\n }\n }\n for (n = 0; n < a6; ++n) {\n v31 = 0;\n for (ii = 0; ii < v34; ++ii) {\n if (!strcmp(*(const char **)(16LL * n + a5), v33[2 * ii])) {\n v31 = 1;\n break;\n }\n }\n if (!v31) {\n v14 = (const char **)(a5 + 16LL * n);\n v15 = v34++;\n v16 = &v33[2 * v15];\n v17 = v14[1];\n *v16 = *v14;\n v16[1] = v17;\n }\n }\n return v33;\n}", + "ida_pseudo_norm": "const char **func0(long long a1, int a2, long long a3, int a4, long long a5,\n int a6) {\n const char **v6;\n int v7;\n const char **v8;\n const char *v9;\n const char **v10;\n int v11;\n const char **v12;\n const char *v13;\n const char **v14;\n int v15;\n const char **v16;\n const char *v17;\n int i;\n int v25;\n int j;\n int k;\n int v28;\n int m;\n int n;\n int v31;\n int ii;\n const char **v33;\n int v34;\n v33 = (const char **)malloc(16LL * (a4 + a2 + a6));\n v34 = 0;\n for (i = 0; i < a2; ++i) {\n v25 = 0;\n for (j = 0; j < v34; ++j) {\n if (!strcmp(*(const char **)(16LL * i + a1), v33[2 * j])) {\n v25 = 1;\n break;\n }\n }\n if (!v25) {\n v6 = (const char **)(a1 + 16LL * i);\n v7 = v34++;\n v8 = &v33[2 * v7];\n v9 = v6[1];\n *v8 = *v6;\n v8[1] = v9;\n }\n }\n for (k = 0; k < a4; ++k) {\n v28 = 0;\n for (m = 0; m < v34; ++m) {\n if (!strcmp(*(const char **)(16LL * k + a3), v33[2 * m])) {\n v28 = 1;\n break;\n }\n }\n if (!v28) {\n v10 = (const char **)(a3 + 16LL * k);\n v11 = v34++;\n v12 = &v33[2 * v11];\n v13 = v10[1];\n *v12 = *v10;\n v12[1] = v13;\n }\n }\n for (n = 0; n < a6; ++n) {\n v31 = 0;\n for (ii = 0; ii < v34; ++ii) {\n if (!strcmp(*(const char **)(16LL * n + a5), v33[2 * ii])) {\n v31 = 1;\n break;\n }\n }\n if (!v31) {\n v14 = (const char **)(a5 + 16LL * n);\n v15 = v34++;\n v16 = &v33[2 * v15];\n v17 = v14[1];\n *v16 = *v14;\n v16[1] = v17;\n }\n }\n return v33;\n}" + }, + { + "index": 87, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char *key;\n\n char *value;\n\n} KeyValuePair;\n\n\n\ntypedef struct {\n\n KeyValuePair *pairs;\n\n int size;\n\n} Dictionary;\n\n\n\n", + "func": "Dictionary func0(Dictionary dict1, Dictionary dict2, Dictionary dict3) {\n Dictionary result;\n result.pairs =\n malloc(sizeof(KeyValuePair) * (dict1.size + dict2.size + dict3.size));\n result.size = 0;\n for (int i = 0; i < dict1.size; i++) {\n int found = 0;\n for (int j = 0; j < result.size; j++) {\n if (strcmp(dict1.pairs[i].key, result.pairs[j].key) == 0) {\n found = 1;\n break;\n }\n }\n if (!found) {\n result.pairs[result.size++] = dict1.pairs[i];\n }\n }\n for (int i = 0; i < dict2.size; i++) {\n int found = 0;\n for (int j = 0; j < result.size; j++) {\n if (strcmp(dict2.pairs[i].key, result.pairs[j].key) == 0) {\n found = 1;\n break;\n }\n }\n if (!found) {\n result.pairs[result.size++] = dict2.pairs[i];\n }\n }\n for (int i = 0; i < dict3.size; i++) {\n int found = 0;\n for (int j = 0; j < result.size; j++) {\n if (strcmp(dict3.pairs[i].key, result.pairs[j].key) == 0) {\n found = 1;\n break;\n }\n }\n if (!found) {\n result.pairs[result.size++] = dict3.pairs[i];\n }\n }\n return result;\n}", + "test": "int main() {\n\n KeyValuePair pairs1[] = {{\"R\", \"Red\"}, {\"B\", \"Black\"}, {\"P\", \"Pink\"}};\n\n KeyValuePair pairs2[] = {{\"G\", \"Green\"}, {\"W\", \"White\"}};\n\n KeyValuePair pairs3[] = {{\"O\", \"Orange\"}, {\"W\", \"White\"}, {\"B\", \"Black\"}};\n\n\n\n Dictionary dict1 = {pairs1, 3};\n\n Dictionary dict2 = {pairs2, 2};\n\n Dictionary dict3 = {pairs3, 3};\n\n\n\n Dictionary result = func0(dict1, dict2, dict3);\n\n assert(result.size == 6);\n\n\n\n KeyValuePair pairs4[] = {{\"L\", \"lavender\"}, {\"B\", \"Blue\"}};\n\n Dictionary dict4 = {pairs4, 2};\n\n \n\n result = func0(dict1, dict2, dict4);\n\n assert(result.size == 6);\n\n\n\n result = func0(dict1, dict4, dict2);\n\n assert(result.size == 6);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x38,%rsp\nmov %rdi,%rbp\nmov %rsi,%rbx\nmov %rdx,0x20(%rsp)\nmov %rcx,0x10(%rsp)\nmov %r8,0x28(%rsp)\nmov %r9,0x18(%rsp)\nlea (%rcx,%rsi,1),%edi\nadd %r9d,%edi\nmovslq %edi,%rdi\nshl $0x4,%rdi\ncallq 10b0 \nmov %rax,%r14\ntest %ebx,%ebx\njle 1215 \nmov %rbp,%r15\nlea -0x1(%rbx),%eax\nshl $0x4,%rax\nlea 0x10(%rbp,%rax,1),%rax\nmov %rax,(%rsp)\nmov $0x0,%r12d\nlea 0x10(%r14),%rax\nmov %rax,0x8(%rsp)\njmpq 134c \nmov $0x0,%r12d\nmov 0x10(%rsp),%rax\ntest %eax,%eax\njle 124a \nmov 0x20(%rsp),%rdx\nmov %rdx,%r15\nlea -0x1(%rax),%eax\nshl $0x4,%rax\nlea 0x10(%rax,%rdx,1),%rax\nmov %rax,(%rsp)\nlea 0x10(%r14),%rax\nmov %rax,0x8(%rsp)\njmpq 12f5 \nmov 0x18(%rsp),%rax\ntest %eax,%eax\njle 137f \nmov 0x28(%rsp),%rcx\nmov %rcx,%r15\nlea -0x1(%rax),%eax\nshl $0x4,%rax\nlea 0x10(%rax,%rcx,1),%rax\nmov %rax,(%rsp)\nlea 0x10(%r14),%rax\nmov %rax,0x8(%rsp)\njmp 129e \nmovslq %r12d,%rax\nshl $0x4,%rax\nmovdqu (%r15),%xmm0\nmovups %xmm0,(%r14,%rax,1)\nlea 0x1(%r12),%r12d\nadd $0x10,%r15\ncmp (%rsp),%r15\nje 137f \ntest %r12d,%r12d\njle 127a \nmov (%r15),%r13\nmov %r14,%rbx\nlea -0x1(%r12),%ebp\nshl $0x4,%rbp\nadd 0x8(%rsp),%rbp\nmov (%rbx),%rsi\nmov %r13,%rdi\ncallq 10a0 \ntest %eax,%eax\nje 1290 \nadd $0x10,%rbx\ncmp %rbx,%rbp\njne 12b7 \njmp 127a \nmovslq %r12d,%rax\nshl $0x4,%rax\nmovdqu (%r15),%xmm1\nmovups %xmm1,(%r14,%rax,1)\nlea 0x1(%r12),%r12d\nadd $0x10,%r15\ncmp (%rsp),%r15\nje 124a \ntest %r12d,%r12d\njle 12d1 \nmov (%r15),%r13\nmov %r14,%rbx\nlea -0x1(%r12),%ebp\nshl $0x4,%rbp\nadd 0x8(%rsp),%rbp\nmov (%rbx),%rsi\nmov %r13,%rdi\ncallq 10a0 \ntest %eax,%eax\nje 12e7 \nadd $0x10,%rbx\ncmp %rbp,%rbx\njne 130e \njmp 12d1 \nmovslq %r12d,%rax\nshl $0x4,%rax\nmovdqu (%r15),%xmm2\nmovups %xmm2,(%r14,%rax,1)\nlea 0x1(%r12),%r12d\nadd $0x10,%r15\ncmp (%rsp),%r15\nje 121b \ntest %r12d,%r12d\njle 1328 \nmov (%r15),%r13\nmov %r14,%rbx\nlea -0x1(%r12),%ebp\nshl $0x4,%rbp\nadd 0x8(%rsp),%rbp\nmov (%rbx),%rsi\nmov %r13,%rdi\ncallq 10a0 \ntest %eax,%eax\nje 133e \nadd $0x10,%rbx\ncmp %rbp,%rbx\njne 1365 \njmp 1328 \nmov %r12d,%edx\nmov %r14,%rax\nadd $0x38,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 38h\nmov rbp, rdi\nmov rbx, rsi\nmov [rsp+68h+var_48], rdx\nmov [rsp+68h+var_58], rcx\nmov [rsp+68h+var_40], r8\nmov [rsp+68h+var_50], r9\nlea edi, [rcx+rsi]\nadd edi, r9d\nmovsxd rdi, edi\nshl rdi, 4; size\ncall _malloc\nmov r14, rax\ntest ebx, ebx\njle short loc_125C\nmov r15, rbp\nmovsxd rbx, ebx\nshl rbx, 4\nlea rax, [rbx+rbp]\nmov [rsp+68h+var_60], rax\nmov r12d, 0\njmp short loc_122D\nloc_1209:\nmovsxd rax, r12d\nshl rax, 4\nmovdqu xmm0, xmmword ptr [r15]\nmovups xmmword ptr [r14+rax], xmm0\nlea r12d, [r12+1]\nloc_121F:\nadd r15, 10h\nmov rax, [rsp+68h+var_60]\ncmp r15, rax\njz short loc_1262\nloc_122D:\ntest r12d, r12d\njle short loc_1209\nmov r13, [r15]\nmov rbx, r14\nmovsxd rbp, r12d\nshl rbp, 4\nadd rbp, r14\nloc_1242:\nmov rsi, [rbx]; s2\nmov rdi, r13; s1\ncall _strcmp\ntest eax, eax\njz short loc_121F\nadd rbx, 10h\ncmp rbx, rbp\njnz short loc_1242\njmp short loc_1209\nloc_125C:\nmov r12d, 0\nloc_1262:\nmov rax, [rsp+68h+var_58]\ntest eax, eax\njle short loc_12D6\nmov rcx, [rsp+68h+var_48]\nmov r15, rcx\ncdqe\nshl rax, 4\nadd rcx, rax\nmov [rsp+68h+var_60], rcx\njmp short loc_12A7\nloc_1283:\nmovsxd rax, r12d\nshl rax, 4\nmovdqu xmm1, xmmword ptr [r15]\nmovups xmmword ptr [r14+rax], xmm1\nlea r12d, [r12+1]\nloc_1299:\nadd r15, 10h\nmov rax, [rsp+68h+var_60]\ncmp r15, rax\njz short loc_12D6\nloc_12A7:\ntest r12d, r12d\njle short loc_1283\nmov r13, [r15]\nmov rbx, r14\nmovsxd rbp, r12d\nshl rbp, 4\nadd rbp, r14\nloc_12BC:\nmov rsi, [rbx]; s2\nmov rdi, r13; s1\ncall _strcmp\ntest eax, eax\njz short loc_1299\nadd rbx, 10h\ncmp rbx, rbp\njnz short loc_12BC\njmp short loc_1283\nloc_12D6:\nmov rax, [rsp+68h+var_50]\ntest eax, eax\njle short loc_134A\nmov rdx, [rsp+68h+var_40]\nmov r15, rdx\ncdqe\nshl rax, 4\nadd rdx, rax\nmov [rsp+68h+var_60], rdx\njmp short loc_131B\nloc_12F7:\nmovsxd rax, r12d\nshl rax, 4\nmovdqu xmm2, xmmword ptr [r15]\nmovups xmmword ptr [r14+rax], xmm2\nlea r12d, [r12+1]\nloc_130D:\nadd r15, 10h\nmov rax, [rsp+68h+var_60]\ncmp r15, rax\njz short loc_134A\nloc_131B:\ntest r12d, r12d\njle short loc_12F7\nmov r13, [r15]\nmov rbx, r14\nmovsxd rbp, r12d\nshl rbp, 4\nadd rbp, r14\nloc_1330:\nmov rsi, [rbx]; s2\nmov rdi, r13; s1\ncall _strcmp\ntest eax, eax\njz short loc_130D\nadd rbx, 10h\ncmp rbx, rbp\njnz short loc_1330\njmp short loc_12F7\nloc_134A:\nmov edx, r12d\nmov rax, r14\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "__m128i *__fastcall func0(const __m128i *a1, int a2, const __m128i *a3, int a4, const __m128i *a5, int a6)\n{\n __m128i *v6; // r14\n const __m128i *v7; // r15\n int v8; // r12d\n const char *v9; // r13\n const char **v10; // rbx\n const __m128i *v11; // r15\n const char *v12; // r13\n const char **v13; // rbx\n const __m128i *v14; // r15\n const char *v15; // r13\n const char **v16; // rbx\n\n v6 = (__m128i *)malloc(16LL * (a6 + a4 + a2));\n if ( a2 <= 0 )\n {\n v8 = 0;\n }\n else\n {\n v7 = a1;\n v8 = 0;\n do\n {\n if ( v8 <= 0 )\n {\nLABEL_3:\n v6[v8++] = _mm_loadu_si128(v7);\n }\n else\n {\n v9 = (const char *)v7->m128i_i64[0];\n v10 = (const char **)v6;\n while ( strcmp(v9, *v10) )\n {\n v10 += 2;\n if ( v10 == (const char **)&v6[v8] )\n goto LABEL_3;\n }\n }\n ++v7;\n }\n while ( v7 != &a1[a2] );\n }\n if ( a4 > 0 )\n {\n v11 = a3;\n do\n {\n if ( v8 <= 0 )\n {\nLABEL_13:\n v6[v8++] = _mm_loadu_si128(v11);\n }\n else\n {\n v12 = (const char *)v11->m128i_i64[0];\n v13 = (const char **)v6;\n while ( strcmp(v12, *v13) )\n {\n v13 += 2;\n if ( v13 == (const char **)&v6[v8] )\n goto LABEL_13;\n }\n }\n ++v11;\n }\n while ( v11 != &a3[a4] );\n }\n if ( a6 > 0 )\n {\n v14 = a5;\n do\n {\n if ( v8 <= 0 )\n {\nLABEL_22:\n v6[v8++] = _mm_loadu_si128(v14);\n }\n else\n {\n v15 = (const char *)v14->m128i_i64[0];\n v16 = (const char **)v6;\n while ( strcmp(v15, *v16) )\n {\n v16 += 2;\n if ( v16 == (const char **)&v6[v8] )\n goto LABEL_22;\n }\n }\n ++v14;\n }\n while ( v14 != &a5[a6] );\n }\n return v6;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 38h\nmov rbp, rdi\nmov rbx, rsi\nmov [rsp+68h+var_48], rdx\nmov [rsp+68h+var_58], rcx\nmov [rsp+68h+var_40], r8\nmov [rsp+68h+var_50], r9\nlea edi, [rcx+rsi]\nadd edi, r9d\nmovsxd rdi, edi\nshl rdi, 4; size\ncall _malloc\nmov r14, rax\ntest ebx, ebx\njle short loc_125C\nmov r15, rbp\nmovsxd rbx, ebx\nshl rbx, 4\nlea rax, [rbx+rbp]\nmov [rsp+68h+var_60], rax\nmov r12d, 0\njmp short loc_122D\nloc_1209:\nmovsxd rax, r12d\nshl rax, 4\nmovdqu xmm0, xmmword ptr [r15]\nmovups xmmword ptr [r14+rax], xmm0\nlea r12d, [r12+1]\nloc_121F:\nadd r15, 10h\nmov rax, [rsp+68h+var_60]\ncmp r15, rax\njz short loc_1262\nloc_122D:\ntest r12d, r12d\njle short loc_1209\nmov r13, [r15]\nmov rbx, r14\nmovsxd rbp, r12d\nshl rbp, 4\nadd rbp, r14\nloc_1242:\nmov rsi, [rbx]; s2\nmov rdi, r13; s1\ncall _strcmp\ntest eax, eax\njz short loc_121F\nadd rbx, 10h\ncmp rbx, rbp\njnz short loc_1242\njmp short loc_1209\nloc_125C:\nmov r12d, 0\nloc_1262:\nmov rax, [rsp+68h+var_58]\ntest eax, eax\njle short loc_12D6\nmov rcx, [rsp+68h+var_48]\nmov r15, rcx\ncdqe\nshl rax, 4\nadd rcx, rax\nmov [rsp+68h+var_60], rcx\njmp short loc_12A7\nloc_1283:\nmovsxd rax, r12d\nshl rax, 4\nmovdqu xmm1, xmmword ptr [r15]\nmovups xmmword ptr [r14+rax], xmm1\nlea r12d, [r12+1]\nloc_1299:\nadd r15, 10h\nmov rax, [rsp+68h+var_60]\ncmp r15, rax\njz short loc_12D6\nloc_12A7:\ntest r12d, r12d\njle short loc_1283\nmov r13, [r15]\nmov rbx, r14\nmovsxd rbp, r12d\nshl rbp, 4\nadd rbp, r14\nloc_12BC:\nmov rsi, [rbx]; s2\nmov rdi, r13; s1\ncall _strcmp\ntest eax, eax\njz short loc_1299\nadd rbx, 10h\ncmp rbx, rbp\njnz short loc_12BC\njmp short loc_1283\nloc_12D6:\nmov rax, [rsp+68h+var_50]\ntest eax, eax\njle short loc_134A\nmov rdx, [rsp+68h+var_40]\nmov r15, rdx\ncdqe\nshl rax, 4\nadd rdx, rax\nmov [rsp+68h+var_60], rdx\njmp short loc_131B\nloc_12F7:\nmovsxd rax, r12d\nshl rax, 4\nmovdqu xmm2, xmmword ptr [r15]\nmovups xmmword ptr [r14+rax], xmm2\nlea r12d, [r12+1]\nloc_130D:\nadd r15, 10h\nmov rax, [rsp+68h+var_60]\ncmp r15, rax\njz short loc_134A\nloc_131B:\ntest r12d, r12d\njle short loc_12F7\nmov r13, [r15]\nmov rbx, r14\nmovsxd rbp, r12d\nshl rbp, 4\nadd rbp, r14\nloc_1330:\nmov rsi, [rbx]; s2\nmov rdi, r13; s1\ncall _strcmp\ntest eax, eax\njz short loc_130D\nadd rbx, 10h\ncmp rbx, rbp\njnz short loc_1330\njmp short loc_12F7\nloc_134A:\nmov edx, r12d\nmov rax, r14\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "__m128i *__fastcall sub_11A9(const __m128i *a1, int a2, const __m128i *a3, int a4, const __m128i *a5, int a6)\n{\n __m128i *v6; // r14\n const __m128i *v7; // r15\n int v8; // r12d\n const char *v9; // r13\n const char **v10; // rbx\n const __m128i *v11; // r15\n const char *v12; // r13\n const char **v13; // rbx\n const __m128i *v14; // r15\n const char *v15; // r13\n const char **v16; // rbx\n\n v6 = (__m128i *)malloc(16LL * (a6 + a4 + a2));\n if ( a2 <= 0 )\n {\n v8 = 0;\n }\n else\n {\n v7 = a1;\n v8 = 0;\n do\n {\n if ( v8 <= 0 )\n {\nLABEL_3:\n v6[v8++] = _mm_loadu_si128(v7);\n }\n else\n {\n v9 = (const char *)v7->m128i_i64[0];\n v10 = (const char **)v6;\n while ( strcmp(v9, *v10) )\n {\n v10 += 2;\n if ( v10 == (const char **)&v6[v8] )\n goto LABEL_3;\n }\n }\n ++v7;\n }\n while ( v7 != &a1[a2] );\n }\n if ( a4 > 0 )\n {\n v11 = a3;\n do\n {\n if ( v8 <= 0 )\n {\nLABEL_13:\n v6[v8++] = _mm_loadu_si128(v11);\n }\n else\n {\n v12 = (const char *)v11->m128i_i64[0];\n v13 = (const char **)v6;\n while ( strcmp(v12, *v13) )\n {\n v13 += 2;\n if ( v13 == (const char **)&v6[v8] )\n goto LABEL_13;\n }\n }\n ++v11;\n }\n while ( v11 != &a3[a4] );\n }\n if ( a6 > 0 )\n {\n v14 = a5;\n do\n {\n if ( v8 <= 0 )\n {\nLABEL_22:\n v6[v8++] = _mm_loadu_si128(v14);\n }\n else\n {\n v15 = (const char *)v14->m128i_i64[0];\n v16 = (const char **)v6;\n while ( strcmp(v15, *v16) )\n {\n v16 += 2;\n if ( v16 == (const char **)&v6[v8] )\n goto LABEL_22;\n }\n }\n ++v14;\n }\n while ( v14 != &a5[a6] );\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__m128i *sub_11A9(const __m128i *a1, int a2, const __m128i *a3, int a4,\n const __m128i *a5, int a6) {\n __m128i *v6;\n const __m128i *v7;\n int v8;\n const char *v9;\n const char **v10;\n const __m128i *v11;\n const char *v12;\n const char **v13;\n const __m128i *v14;\n const char *v15;\n const char **v16;\n v6 = (__m128i *)malloc(16LL * (a6 + a4 + a2));\n if (a2 <= 0) {\n v8 = 0;\n } else {\n v7 = a1;\n v8 = 0;\n do {\n if (v8 <= 0) {\n LABEL_3:\n v6[v8++] = _mm_loadu_si128(v7);\n } else {\n v9 = (const char *)v7->m128i_i64[0];\n v10 = (const char **)v6;\n while (strcmp(v9, *v10)) {\n v10 += 2;\n if (v10 == (const char **)&v6[v8]) goto LABEL_3;\n }\n }\n ++v7;\n } while (v7 != &a1[a2]);\n }\n if (a4 > 0) {\n v11 = a3;\n do {\n if (v8 <= 0) {\n LABEL_13:\n v6[v8++] = _mm_loadu_si128(v11);\n } else {\n v12 = (const char *)v11->m128i_i64[0];\n v13 = (const char **)v6;\n while (strcmp(v12, *v13)) {\n v13 += 2;\n if (v13 == (const char **)&v6[v8]) goto LABEL_13;\n }\n }\n ++v11;\n } while (v11 != &a3[a4]);\n }\n if (a6 > 0) {\n v14 = a5;\n do {\n if (v8 <= 0) {\n LABEL_22:\n v6[v8++] = _mm_loadu_si128(v14);\n } else {\n v15 = (const char *)v14->m128i_i64[0];\n v16 = (const char **)v6;\n while (strcmp(v15, *v16)) {\n v16 += 2;\n if (v16 == (const char **)&v6[v8]) goto LABEL_22;\n }\n }\n ++v14;\n } while (v14 != &a5[a6]);\n }\n return v6;\n}", + "ida_pseudo_norm": "__m128i *func0(const __m128i *a1, int a2, const __m128i *a3, int a4,\n const __m128i *a5, int a6) {\n __m128i *v6;\n const __m128i *v7;\n int v8;\n const char *v9;\n const char **v10;\n const __m128i *v11;\n const char *v12;\n const char **v13;\n const __m128i *v14;\n const char *v15;\n const char **v16;\n v6 = (__m128i *)malloc(16LL * (a6 + a4 + a2));\n if (a2 <= 0) {\n v8 = 0;\n } else {\n v7 = a1;\n v8 = 0;\n do {\n if (v8 <= 0) {\n LABEL_3:\n v6[v8++] = _mm_loadu_si128(v7);\n } else {\n v9 = (const char *)v7->m128i_i64[0];\n v10 = (const char **)v6;\n while (strcmp(v9, *v10)) {\n v10 += 2;\n if (v10 == (const char **)&v6[v8]) goto LABEL_3;\n }\n }\n ++v7;\n } while (v7 != &a1[a2]);\n }\n if (a4 > 0) {\n v11 = a3;\n do {\n if (v8 <= 0) {\n LABEL_13:\n v6[v8++] = _mm_loadu_si128(v11);\n } else {\n v12 = (const char *)v11->m128i_i64[0];\n v13 = (const char **)v6;\n while (strcmp(v12, *v13)) {\n v13 += 2;\n if (v13 == (const char **)&v6[v8]) goto LABEL_13;\n }\n }\n ++v11;\n } while (v11 != &a3[a4]);\n }\n if (a6 > 0) {\n v14 = a5;\n do {\n if (v8 <= 0) {\n LABEL_22:\n v6[v8++] = _mm_loadu_si128(v14);\n } else {\n v15 = (const char *)v14->m128i_i64[0];\n v16 = (const char **)v6;\n while (strcmp(v15, *v16)) {\n v16 += 2;\n if (v16 == (const char **)&v6[v8]) goto LABEL_22;\n }\n }\n ++v14;\n } while (v14 != &a5[a6]);\n }\n return v6;\n}" + }, + { + "index": 87, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char *key;\n\n char *value;\n\n} KeyValuePair;\n\n\n\ntypedef struct {\n\n KeyValuePair *pairs;\n\n int size;\n\n} Dictionary;\n\n\n\n", + "func": "Dictionary func0(Dictionary dict1, Dictionary dict2, Dictionary dict3) {\n Dictionary result;\n result.pairs =\n malloc(sizeof(KeyValuePair) * (dict1.size + dict2.size + dict3.size));\n result.size = 0;\n for (int i = 0; i < dict1.size; i++) {\n int found = 0;\n for (int j = 0; j < result.size; j++) {\n if (strcmp(dict1.pairs[i].key, result.pairs[j].key) == 0) {\n found = 1;\n break;\n }\n }\n if (!found) {\n result.pairs[result.size++] = dict1.pairs[i];\n }\n }\n for (int i = 0; i < dict2.size; i++) {\n int found = 0;\n for (int j = 0; j < result.size; j++) {\n if (strcmp(dict2.pairs[i].key, result.pairs[j].key) == 0) {\n found = 1;\n break;\n }\n }\n if (!found) {\n result.pairs[result.size++] = dict2.pairs[i];\n }\n }\n for (int i = 0; i < dict3.size; i++) {\n int found = 0;\n for (int j = 0; j < result.size; j++) {\n if (strcmp(dict3.pairs[i].key, result.pairs[j].key) == 0) {\n found = 1;\n break;\n }\n }\n if (!found) {\n result.pairs[result.size++] = dict3.pairs[i];\n }\n }\n return result;\n}", + "test": "int main() {\n\n KeyValuePair pairs1[] = {{\"R\", \"Red\"}, {\"B\", \"Black\"}, {\"P\", \"Pink\"}};\n\n KeyValuePair pairs2[] = {{\"G\", \"Green\"}, {\"W\", \"White\"}};\n\n KeyValuePair pairs3[] = {{\"O\", \"Orange\"}, {\"W\", \"White\"}, {\"B\", \"Black\"}};\n\n\n\n Dictionary dict1 = {pairs1, 3};\n\n Dictionary dict2 = {pairs2, 2};\n\n Dictionary dict3 = {pairs3, 3};\n\n\n\n Dictionary result = func0(dict1, dict2, dict3);\n\n assert(result.size == 6);\n\n\n\n KeyValuePair pairs4[] = {{\"L\", \"lavender\"}, {\"B\", \"Blue\"}};\n\n Dictionary dict4 = {pairs4, 2};\n\n \n\n result = func0(dict1, dict2, dict4);\n\n assert(result.size == 6);\n\n\n\n result = func0(dict1, dict4, dict2);\n\n assert(result.size == 6);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\nmov %rdi,%r14\nlea (%rcx,%rsi,1),%edi\npush %r13\nadd %r9d,%edi\npush %r12\nmovslq %edi,%rdi\npush %rbp\nshl $0x4,%rdi\npush %rbx\nmov %rsi,%rbx\nsub $0x38,%rsp\nmov %rdx,0x20(%rsp)\nmov %rcx,0x10(%rsp)\nmov %r8,0x28(%rsp)\nmov %r9,0x18(%rsp)\ncallq 10b0 \nmov %rax,%r13\ntest %ebx,%ebx\njle 15d8 \nlea -0x1(%rbx),%eax\nxor %ebp,%ebp\nshl $0x4,%rax\nlea 0x10(%r14,%rax,1),%rax\nmov %rax,(%rsp)\nlea 0x10(%r13),%rax\nmov %rax,0x8(%rsp)\nnopl 0x0(%rax)\ntest %ebp,%ebp\nje 1588 \nlea -0x1(%rbp),%ebx\nmov (%r14),%r12\nmov %r13,%r15\nshl $0x4,%rbx\nadd 0x8(%rsp),%rbx\njmp 1455 \nnopl 0x0(%rax)\nadd $0x10,%r15\ncmp %rbx,%r15\nje 1588 \nmov (%r15),%rsi\nmov %r12,%rdi\ncallq 10a0 \ntest %eax,%eax\njne 1448 \nadd $0x10,%r14\ncmp (%rsp),%r14\njne 1428 \nmov 0x10(%rsp),%rax\ntest %eax,%eax\njle 14de \nmov 0x20(%rsp),%r14\nsub $0x1,%eax\nshl $0x4,%rax\nlea 0x10(%r14,%rax,1),%rax\nmov %rax,(%rsp)\nlea 0x10(%r13),%rax\nmov %rax,0x8(%rsp)\nnopl (%rax)\ntest %ebp,%ebp\nje 15b0 \nlea -0x1(%rbp),%ebx\nmov (%r14),%r12\nmov %r13,%r15\nshl $0x4,%rbx\nadd 0x8(%rsp),%rbx\njmp 14c5 \nnopl 0x0(%rax)\nadd $0x10,%r15\ncmp %r15,%rbx\nje 15b0 \nmov (%r15),%rsi\nmov %r12,%rdi\ncallq 10a0 \ntest %eax,%eax\njne 14b8 \nadd $0x10,%r14\ncmp %r14,(%rsp)\njne 1498 \nmov 0x18(%rsp),%rax\ntest %eax,%eax\njle 1542 \nmov 0x28(%rsp),%r14\nsub $0x1,%eax\nshl $0x4,%rax\nlea 0x10(%r14,%rax,1),%rax\nmov %rax,(%rsp)\nlea 0x10(%r13),%rax\nmov %rax,0x8(%rsp)\nnopl (%rax)\ntest %ebp,%ebp\nje 1560 \nlea -0x1(%rbp),%ebx\nmov (%r14),%r12\nmov %r13,%r15\nshl $0x4,%rbx\nadd 0x8(%rsp),%rbx\njmp 1529 \nadd $0x10,%r15\ncmp %r15,%rbx\nje 1560 \nmov (%r15),%rsi\nmov %r12,%rdi\ncallq 10a0 \ntest %eax,%eax\njne 1520 \nadd $0x10,%r14\ncmp (%rsp),%r14\njne 1508 \nadd $0x38,%rsp\nmov %ebp,%edx\nmov %r13,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw %cs:0x0(%rax,%rax,1)\nmovdqu (%r14),%xmm2\nmovslq %ebp,%rax\nadd $0x10,%r14\nadd $0x1,%ebp\nshl $0x4,%rax\nmovups %xmm2,0x0(%r13,%rax,1)\ncmp (%rsp),%r14\njne 1508 \njmp 1542 \nnopl 0x0(%rax)\nmovdqu (%r14),%xmm0\nmovslq %ebp,%rax\nadd $0x10,%r14\nadd $0x1,%ebp\nshl $0x4,%rax\nmovups %xmm0,0x0(%r13,%rax,1)\ncmp (%rsp),%r14\njne 1428 \njmpq 146e \nmovdqu (%r14),%xmm1\nmovslq %ebp,%rax\nadd $0x10,%r14\nadd $0x1,%ebp\nshl $0x4,%rax\nmovups %xmm1,0x0(%r13,%rax,1)\ncmp %r14,(%rsp)\njne 1498 \njmpq 14de \nxor %ebp,%ebp\njmpq 146e \n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14, rdi\nlea edi, [rcx+rsi]\npush r13\nadd edi, r9d\npush r12\nmovsxd rdi, edi\npush rbp\nshl rdi, 4; size\npush rbx\nmov rbx, rsi\nsub rsp, 38h\nmov [rsp+68h+var_48], rdx\nmov [rsp+68h+var_58], rcx\nmov [rsp+68h+var_40], r8\nmov [rsp+68h+var_50], r9\ncall _malloc\nmov r13, rax\ntest ebx, ebx\njle loc_161E\nmovsxd rbx, ebx\nxor r12d, r12d\nshl rbx, 4\nlea rax, [rbx+r14]\nmov [rsp+68h+var_68], rax\nnop dword ptr [rax+rax+00h]\nloc_1460:\nmovsxd rax, r12d\nmov rbx, rax\nmov [rsp+68h+var_60], rax\nshl rbx, 4\nadd rbx, r13\ntest r12d, r12d\njle loc_15B8\nloc_147B:\nmov rbp, [r14]\nmov r15, r13\njmp short loc_1495\nloc_1488:\nadd r15, 10h\ncmp r15, rbx\njz loc_15B8\nloc_1495:\nmov rsi, [r15]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1488\nadd r14, 10h\ncmp [rsp+68h+var_68], r14\njnz short loc_147B\nloc_14AE:\nmov rax, [rsp+68h+var_58]\ntest eax, eax\njle short loc_1516\nmovsxd r15, eax\nmov r14, [rsp+68h+var_48]\nshl r15, 4\nlea rax, [r15+r14]\nmov [rsp+68h+var_68], rax\nnop dword ptr [rax+rax+00h]\nloc_14D0:\nmovsxd rbx, r12d\nmov dword ptr [rsp+68h+var_60], r12d\nshl rbx, 4\nadd rbx, r13\ntest r12d, r12d\njle loc_15F0\nloc_14E8:\nmov rbp, [r14]\nmov r15, r13\njmp short loc_14FD\nloc_14F0:\nadd r15, 10h\ncmp r15, rbx\njz loc_15F0\nloc_14FD:\nmov rsi, [r15]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njnz short loc_14F0\nadd r14, 10h\ncmp [rsp+68h+var_68], r14\njnz short loc_14E8\nloc_1516:\nmov rax, [rsp+68h+var_50]\ntest eax, eax\njle short loc_157A\nmov r14, [rsp+68h+var_40]\ncdqe\nshl rax, 4\nadd rax, r14\nmov [rsp+68h+var_68], rax\nnop dword ptr [rax+00000000h]\nloc_1538:\nmovsxd rbx, r12d\nmov dword ptr [rsp+68h+var_60], r12d\nshl rbx, 4\nadd rbx, r13\ntest r12d, r12d\njle short loc_1590\nloc_154C:\nmov rbp, [r14]\nmov r15, r13\njmp short loc_1561\nloc_1558:\nadd r15, 10h\ncmp rbx, r15\njz short loc_1590\nloc_1561:\nmov rsi, [r15]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1558\nadd r14, 10h\ncmp [rsp+68h+var_68], r14\njnz short loc_154C\nloc_157A:\nadd rsp, 38h\nmov edx, r12d\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1590:\nmovsxd r15, dword ptr [rsp+68h+var_60]\nmovdqu xmm2, xmmword ptr [r14]\nadd r12d, 1\nadd r14, 10h\nshl r15, 4\nmovups xmmword ptr [r13+r15+0], xmm2\ncmp [rsp+68h+var_68], r14\njnz short loc_1538\njmp short loc_157A\nloc_15B8:\nmov r15, [rsp+68h+var_60]\nmov rax, [rsp+68h+var_68]\nadd r14, 10h\nadd r12d, 1\nmovdqu xmm0, xmmword ptr [r14-10h]\nshl r15, 4\nmovups xmmword ptr [r13+r15+0], xmm0\ncmp r14, rax\njnz loc_1460\njmp loc_14AE\nloc_15F0:\nmovsxd rax, dword ptr [rsp+68h+var_60]\nmovdqu xmm1, xmmword ptr [r14]\nadd r14, 10h\nadd r12d, 1\nshl rax, 4\nmovups xmmword ptr [r13+rax+0], xmm1\nmov rax, [rsp+68h+var_68]\ncmp r14, rax\njnz loc_14D0\njmp loc_1516\nloc_161E:\nxor r12d, r12d\njmp loc_14AE", + "ida_pseudo": "__m128i *__fastcall func0(const char **a1, int a2, const __m128i *a3, int a4, const __m128i *a5, int a6)\n{\n const char **v6; // r14\n __m128i *v7; // r13\n int v8; // r12d\n const char *v9; // rbp\n const char **v10; // r15\n const __m128i *v11; // r14\n const char *v12; // rbp\n const char **v13; // r15\n const __m128i *v14; // r14\n const char *v15; // rbp\n const char **v16; // r15\n __m128i v18; // xmm2\n __m128i v19; // xmm1\n const char **v20; // [rsp+0h] [rbp-68h]\n const __m128i *v21; // [rsp+0h] [rbp-68h]\n const __m128i *v22; // [rsp+0h] [rbp-68h]\n __int64 v23; // [rsp+8h] [rbp-60h]\n int v24; // [rsp+8h] [rbp-60h]\n int v25; // [rsp+8h] [rbp-60h]\n\n v6 = a1;\n v7 = (__m128i *)malloc(16LL * (a6 + a4 + a2));\n if ( a2 <= 0 )\n {\n v8 = 0;\n }\n else\n {\n v8 = 0;\n v20 = &a1[2 * a2];\n while ( 1 )\n {\n v23 = v8;\n if ( v8 > 0 )\n break;\nLABEL_25:\n v6 += 2;\n ++v8;\n v7[v23] = _mm_loadu_si128((const __m128i *)v6 - 1);\n if ( v6 == v20 )\n goto LABEL_8;\n }\n do\n {\n v9 = *v6;\n v10 = (const char **)v7;\n while ( strcmp(v9, *v10) )\n {\n v10 += 2;\n if ( v10 == (const char **)&v7[v8] )\n goto LABEL_25;\n }\n v6 += 2;\n }\n while ( v20 != v6 );\n }\nLABEL_8:\n if ( a4 > 0 )\n {\n v11 = a3;\n v21 = &a3[a4];\n while ( 1 )\n {\n v24 = v8;\n if ( v8 > 0 )\n break;\nLABEL_27:\n v19 = _mm_loadu_si128(v11++);\n ++v8;\n v7[v24] = v19;\n if ( v11 == v21 )\n goto LABEL_15;\n }\n do\n {\n v12 = (const char *)v11->m128i_i64[0];\n v13 = (const char **)v7;\n while ( strcmp(v12, *v13) )\n {\n v13 += 2;\n if ( v13 == (const char **)&v7[v8] )\n goto LABEL_27;\n }\n ++v11;\n }\n while ( v21 != v11 );\n }\nLABEL_15:\n if ( a6 > 0 )\n {\n v14 = a5;\n v22 = &a5[a6];\n while ( 1 )\n {\n v25 = v8;\n if ( v8 > 0 )\n break;\nLABEL_23:\n v18 = _mm_loadu_si128(v14);\n ++v8;\n ++v14;\n v7[v25] = v18;\n if ( v22 == v14 )\n return v7;\n }\n do\n {\n v15 = (const char *)v14->m128i_i64[0];\n v16 = (const char **)v7;\n while ( strcmp(v15, *v16) )\n {\n v16 += 2;\n if ( &v7[v8] == (__m128i *)v16 )\n goto LABEL_23;\n }\n ++v14;\n }\n while ( v22 != v14 );\n }\n return v7;\n}", + "ida_strip_asm": "sub_1400:\nendbr64\npush r15\npush r14\nmov r14, rdi\nlea edi, [rcx+rsi]\npush r13\nadd edi, r9d\npush r12\nmovsxd rdi, edi\npush rbp\nshl rdi, 4; size\npush rbx\nmov rbx, rsi\nsub rsp, 38h\nmov [rsp+68h+var_48], rdx\nmov [rsp+68h+var_58], rcx\nmov [rsp+68h+var_40], r8\nmov [rsp+68h+var_50], r9\ncall _malloc\nmov r13, rax\ntest ebx, ebx\njle loc_161E\nmovsxd rbx, ebx\nxor r12d, r12d\nshl rbx, 4\nlea rax, [rbx+r14]\nmov [rsp+68h+var_68], rax\nnop dword ptr [rax+rax+00h]\nloc_1460:\nmovsxd rax, r12d\nmov rbx, rax\nmov [rsp+68h+var_60], rax\nshl rbx, 4\nadd rbx, r13\ntest r12d, r12d\njle loc_15B8\nloc_147B:\nmov rbp, [r14]\nmov r15, r13\njmp short loc_1495\nloc_1488:\nadd r15, 10h\ncmp r15, rbx\njz loc_15B8\nloc_1495:\nmov rsi, [r15]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1488\nadd r14, 10h\ncmp [rsp+68h+var_68], r14\njnz short loc_147B\nloc_14AE:\nmov rax, [rsp+68h+var_58]\ntest eax, eax\njle short loc_1516\nmovsxd r15, eax\nmov r14, [rsp+68h+var_48]\nshl r15, 4\nlea rax, [r15+r14]\nmov [rsp+68h+var_68], rax\nnop dword ptr [rax+rax+00h]\nloc_14D0:\nmovsxd rbx, r12d\nmov dword ptr [rsp+68h+var_60], r12d\nshl rbx, 4\nadd rbx, r13\ntest r12d, r12d\njle loc_15F0\nloc_14E8:\nmov rbp, [r14]\nmov r15, r13\njmp short loc_14FD\nloc_14F0:\nadd r15, 10h\ncmp r15, rbx\njz loc_15F0\nloc_14FD:\nmov rsi, [r15]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njnz short loc_14F0\nadd r14, 10h\ncmp [rsp+68h+var_68], r14\njnz short loc_14E8\nloc_1516:\nmov rax, [rsp+68h+var_50]\ntest eax, eax\njle short loc_157A\nmov r14, [rsp+68h+var_40]\ncdqe\nshl rax, 4\nadd rax, r14\nmov [rsp+68h+var_68], rax\nnop dword ptr [rax+00000000h]\nloc_1538:\nmovsxd rbx, r12d\nmov dword ptr [rsp+68h+var_60], r12d\nshl rbx, 4\nadd rbx, r13\ntest r12d, r12d\njle short loc_1590\nloc_154C:\nmov rbp, [r14]\nmov r15, r13\njmp short loc_1561\nloc_1558:\nadd r15, 10h\ncmp rbx, r15\njz short loc_1590\nloc_1561:\nmov rsi, [r15]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1558\nadd r14, 10h\ncmp [rsp+68h+var_68], r14\njnz short loc_154C\nloc_157A:\nadd rsp, 38h\nmov edx, r12d\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1590:\nmovsxd r15, dword ptr [rsp+68h+var_60]\nmovdqu xmm2, xmmword ptr [r14]\nadd r12d, 1\nadd r14, 10h\nshl r15, 4\nmovups xmmword ptr [r13+r15+0], xmm2\ncmp [rsp+68h+var_68], r14\njnz short loc_1538\njmp short loc_157A\nloc_15B8:\nmov r15, [rsp+68h+var_60]\nmov rax, [rsp+68h+var_68]\nadd r14, 10h\nadd r12d, 1\nmovdqu xmm0, xmmword ptr [r14-10h]\nshl r15, 4\nmovups xmmword ptr [r13+r15+0], xmm0\ncmp r14, rax\njnz loc_1460\njmp loc_14AE\nloc_15F0:\nmovsxd rax, dword ptr [rsp+68h+var_60]\nmovdqu xmm1, xmmword ptr [r14]\nadd r14, 10h\nadd r12d, 1\nshl rax, 4\nmovups xmmword ptr [r13+rax+0], xmm1\nmov rax, [rsp+68h+var_68]\ncmp r14, rax\njnz loc_14D0\njmp loc_1516\nloc_161E:\nxor r12d, r12d\njmp loc_14AE", + "ida_strip_pseudo": "__m128i *__fastcall sub_1400(const char **a1, int a2, const __m128i *a3, int a4, const __m128i *a5, int a6)\n{\n const char **v6; // r14\n __m128i *v7; // r13\n int v8; // r12d\n const char *v9; // rbp\n const char **v10; // r15\n const __m128i *v11; // r14\n const char *v12; // rbp\n const char **v13; // r15\n const __m128i *v14; // r14\n const char *v15; // rbp\n const char **v16; // r15\n __m128i v18; // xmm2\n __m128i v19; // xmm1\n const char **v20; // [rsp+0h] [rbp-68h]\n const __m128i *v21; // [rsp+0h] [rbp-68h]\n const __m128i *v22; // [rsp+0h] [rbp-68h]\n __int64 v23; // [rsp+8h] [rbp-60h]\n int v24; // [rsp+8h] [rbp-60h]\n int v25; // [rsp+8h] [rbp-60h]\n\n v6 = a1;\n v7 = (__m128i *)malloc(16LL * (a6 + a4 + a2));\n if ( a2 <= 0 )\n {\n v8 = 0;\n }\n else\n {\n v8 = 0;\n v20 = &a1[2 * a2];\n while ( 1 )\n {\n v23 = v8;\n if ( v8 > 0 )\n break;\nLABEL_25:\n v6 += 2;\n ++v8;\n v7[v23] = _mm_loadu_si128((const __m128i *)v6 - 1);\n if ( v6 == v20 )\n goto LABEL_8;\n }\n do\n {\n v9 = *v6;\n v10 = (const char **)v7;\n while ( strcmp(v9, *v10) )\n {\n v10 += 2;\n if ( v10 == (const char **)&v7[v8] )\n goto LABEL_25;\n }\n v6 += 2;\n }\n while ( v20 != v6 );\n }\nLABEL_8:\n if ( a4 > 0 )\n {\n v11 = a3;\n v21 = &a3[a4];\n while ( 1 )\n {\n v24 = v8;\n if ( v8 > 0 )\n break;\nLABEL_27:\n v19 = _mm_loadu_si128(v11++);\n ++v8;\n v7[v24] = v19;\n if ( v11 == v21 )\n goto LABEL_15;\n }\n do\n {\n v12 = (const char *)v11->m128i_i64[0];\n v13 = (const char **)v7;\n while ( strcmp(v12, *v13) )\n {\n v13 += 2;\n if ( v13 == (const char **)&v7[v8] )\n goto LABEL_27;\n }\n ++v11;\n }\n while ( v21 != v11 );\n }\nLABEL_15:\n if ( a6 > 0 )\n {\n v14 = a5;\n v22 = &a5[a6];\n while ( 1 )\n {\n v25 = v8;\n if ( v8 > 0 )\n break;\nLABEL_23:\n v18 = _mm_loadu_si128(v14);\n ++v8;\n ++v14;\n v7[v25] = v18;\n if ( v22 == v14 )\n return v7;\n }\n do\n {\n v15 = (const char *)v14->m128i_i64[0];\n v16 = (const char **)v7;\n while ( strcmp(v15, *v16) )\n {\n v16 += 2;\n if ( &v7[v8] == (__m128i *)v16 )\n goto LABEL_23;\n }\n ++v14;\n }\n while ( v22 != v14 );\n }\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__m128i *sub_1400(const char **a1, int a2, const __m128i *a3, int a4,\n const __m128i *a5, int a6) {\n const char **v6;\n __m128i *v7;\n int v8;\n const char *v9;\n const char **v10;\n const __m128i *v11;\n const char *v12;\n const char **v13;\n const __m128i *v14;\n const char *v15;\n const char **v16;\n __m128i v18;\n __m128i v19;\n const char **v20;\n const __m128i *v21;\n const __m128i *v22;\n long long v23;\n int v24;\n int v25;\n v6 = a1;\n v7 = (__m128i *)malloc(16LL * (a6 + a4 + a2));\n if (a2 <= 0) {\n v8 = 0;\n } else {\n v8 = 0;\n v20 = &a1[2 * a2];\n while (1) {\n v23 = v8;\n if (v8 > 0) break;\n LABEL_25:\n v6 += 2;\n ++v8;\n v7[v23] = _mm_loadu_si128((const __m128i *)v6 - 1);\n if (v6 == v20) goto LABEL_8;\n }\n do {\n v9 = *v6;\n v10 = (const char **)v7;\n while (strcmp(v9, *v10)) {\n v10 += 2;\n if (v10 == (const char **)&v7[v8]) goto LABEL_25;\n }\n v6 += 2;\n } while (v20 != v6);\n }\nLABEL_8:\n if (a4 > 0) {\n v11 = a3;\n v21 = &a3[a4];\n while (1) {\n v24 = v8;\n if (v8 > 0) break;\n LABEL_27:\n v19 = _mm_loadu_si128(v11++);\n ++v8;\n v7[v24] = v19;\n if (v11 == v21) goto LABEL_15;\n }\n do {\n v12 = (const char *)v11->m128i_i64[0];\n v13 = (const char **)v7;\n while (strcmp(v12, *v13)) {\n v13 += 2;\n if (v13 == (const char **)&v7[v8]) goto LABEL_27;\n }\n ++v11;\n } while (v21 != v11);\n }\nLABEL_15:\n if (a6 > 0) {\n v14 = a5;\n v22 = &a5[a6];\n while (1) {\n v25 = v8;\n if (v8 > 0) break;\n LABEL_23:\n v18 = _mm_loadu_si128(v14);\n ++v8;\n ++v14;\n v7[v25] = v18;\n if (v22 == v14) return v7;\n }\n do {\n v15 = (const char *)v14->m128i_i64[0];\n v16 = (const char **)v7;\n while (strcmp(v15, *v16)) {\n v16 += 2;\n if (&v7[v8] == (__m128i *)v16) goto LABEL_23;\n }\n ++v14;\n } while (v22 != v14);\n }\n return v7;\n}", + "ida_pseudo_norm": "__m128i *func0(const char **a1, int a2, const __m128i *a3, int a4,\n const __m128i *a5, int a6) {\n const char **v6;\n __m128i *v7;\n int v8;\n const char *v9;\n const char **v10;\n const __m128i *v11;\n const char *v12;\n const char **v13;\n const __m128i *v14;\n const char *v15;\n const char **v16;\n __m128i v18;\n __m128i v19;\n const char **v20;\n const __m128i *v21;\n const __m128i *v22;\n long long v23;\n int v24;\n int v25;\n v6 = a1;\n v7 = (__m128i *)malloc(16LL * (a6 + a4 + a2));\n if (a2 <= 0) {\n v8 = 0;\n } else {\n v8 = 0;\n v20 = &a1[2 * a2];\n while (1) {\n v23 = v8;\n if (v8 > 0) break;\n LABEL_25:\n v6 += 2;\n ++v8;\n v7[v23] = _mm_loadu_si128((const __m128i *)v6 - 1);\n if (v6 == v20) goto LABEL_8;\n }\n do {\n v9 = *v6;\n v10 = (const char **)v7;\n while (strcmp(v9, *v10)) {\n v10 += 2;\n if (v10 == (const char **)&v7[v8]) goto LABEL_25;\n }\n v6 += 2;\n } while (v20 != v6);\n }\nLABEL_8:\n if (a4 > 0) {\n v11 = a3;\n v21 = &a3[a4];\n while (1) {\n v24 = v8;\n if (v8 > 0) break;\n LABEL_27:\n v19 = _mm_loadu_si128(v11++);\n ++v8;\n v7[v24] = v19;\n if (v11 == v21) goto LABEL_15;\n }\n do {\n v12 = (const char *)v11->m128i_i64[0];\n v13 = (const char **)v7;\n while (strcmp(v12, *v13)) {\n v13 += 2;\n if (v13 == (const char **)&v7[v8]) goto LABEL_27;\n }\n ++v11;\n } while (v21 != v11);\n }\nLABEL_15:\n if (a6 > 0) {\n v14 = a5;\n v22 = &a5[a6];\n while (1) {\n v25 = v8;\n if (v8 > 0) break;\n LABEL_23:\n v18 = _mm_loadu_si128(v14);\n ++v8;\n ++v14;\n v7[v25] = v18;\n if (v22 == v14) return v7;\n }\n do {\n v15 = (const char *)v14->m128i_i64[0];\n v16 = (const char **)v7;\n while (strcmp(v15, *v16)) {\n v16 += 2;\n if (&v7[v8] == (__m128i *)v16) goto LABEL_23;\n }\n ++v14;\n } while (v22 != v14);\n }\n return v7;\n}" + }, + { + "index": 87, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char *key;\n\n char *value;\n\n} KeyValuePair;\n\n\n\ntypedef struct {\n\n KeyValuePair *pairs;\n\n int size;\n\n} Dictionary;\n\n\n\n", + "func": "Dictionary func0(Dictionary dict1, Dictionary dict2, Dictionary dict3) {\n Dictionary result;\n result.pairs =\n malloc(sizeof(KeyValuePair) * (dict1.size + dict2.size + dict3.size));\n result.size = 0;\n for (int i = 0; i < dict1.size; i++) {\n int found = 0;\n for (int j = 0; j < result.size; j++) {\n if (strcmp(dict1.pairs[i].key, result.pairs[j].key) == 0) {\n found = 1;\n break;\n }\n }\n if (!found) {\n result.pairs[result.size++] = dict1.pairs[i];\n }\n }\n for (int i = 0; i < dict2.size; i++) {\n int found = 0;\n for (int j = 0; j < result.size; j++) {\n if (strcmp(dict2.pairs[i].key, result.pairs[j].key) == 0) {\n found = 1;\n break;\n }\n }\n if (!found) {\n result.pairs[result.size++] = dict2.pairs[i];\n }\n }\n for (int i = 0; i < dict3.size; i++) {\n int found = 0;\n for (int j = 0; j < result.size; j++) {\n if (strcmp(dict3.pairs[i].key, result.pairs[j].key) == 0) {\n found = 1;\n break;\n }\n }\n if (!found) {\n result.pairs[result.size++] = dict3.pairs[i];\n }\n }\n return result;\n}", + "test": "int main() {\n\n KeyValuePair pairs1[] = {{\"R\", \"Red\"}, {\"B\", \"Black\"}, {\"P\", \"Pink\"}};\n\n KeyValuePair pairs2[] = {{\"G\", \"Green\"}, {\"W\", \"White\"}};\n\n KeyValuePair pairs3[] = {{\"O\", \"Orange\"}, {\"W\", \"White\"}, {\"B\", \"Black\"}};\n\n\n\n Dictionary dict1 = {pairs1, 3};\n\n Dictionary dict2 = {pairs2, 2};\n\n Dictionary dict3 = {pairs3, 3};\n\n\n\n Dictionary result = func0(dict1, dict2, dict3);\n\n assert(result.size == 6);\n\n\n\n KeyValuePair pairs4[] = {{\"L\", \"lavender\"}, {\"B\", \"Blue\"}};\n\n Dictionary dict4 = {pairs4, 2};\n\n \n\n result = func0(dict1, dict2, dict4);\n\n assert(result.size == 6);\n\n\n\n result = func0(dict1, dict4, dict2);\n\n assert(result.size == 6);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\nmov %rdi,%r14\nlea (%rcx,%rsi,1),%edi\npush %r13\nadd %r9d,%edi\npush %r12\nmovslq %edi,%rdi\npush %rbp\nshl $0x4,%rdi\npush %rbx\nmov %rsi,%rbx\nsub $0x38,%rsp\nmov %rdx,0x20(%rsp)\nmov %rcx,0x10(%rsp)\nmov %r8,0x28(%rsp)\nmov %r9,0x18(%rsp)\ncallq 10b0 \nmov %rax,%r13\ntest %ebx,%ebx\njle 1608 \nlea -0x1(%rbx),%eax\nxor %ebp,%ebp\nshl $0x4,%rax\nlea 0x10(%r14,%rax,1),%rax\nmov %rax,(%rsp)\nlea 0x10(%r13),%rax\nmov %rax,0x8(%rsp)\nnopl 0x0(%rax)\ntest %ebp,%ebp\nje 15b8 \nlea -0x1(%rbp),%ebx\nmov (%r14),%r12\nmov %r13,%r15\nshl $0x4,%rbx\nadd 0x8(%rsp),%rbx\njmp 1485 \nnopl 0x0(%rax)\nadd $0x10,%r15\ncmp %r15,%rbx\nje 15b8 \nmov (%r15),%rsi\nmov %r12,%rdi\ncallq 10a0 \ntest %eax,%eax\njne 1478 \nadd $0x10,%r14\ncmp %r14,(%rsp)\njne 1458 \nmov 0x10(%rsp),%rax\ntest %eax,%eax\njle 150e \nmov 0x20(%rsp),%r14\nsub $0x1,%eax\nshl $0x4,%rax\nlea 0x10(%r14,%rax,1),%rax\nmov %rax,(%rsp)\nlea 0x10(%r13),%rax\nmov %rax,0x8(%rsp)\nnopl (%rax)\ntest %ebp,%ebp\nje 15e0 \nlea -0x1(%rbp),%ebx\nmov (%r14),%r12\nmov %r13,%r15\nshl $0x4,%rbx\nadd 0x8(%rsp),%rbx\njmp 14f5 \nnopl 0x0(%rax)\nadd $0x10,%r15\ncmp %r15,%rbx\nje 15e0 \nmov (%r15),%rsi\nmov %r12,%rdi\ncallq 10a0 \ntest %eax,%eax\njne 14e8 \nadd $0x10,%r14\ncmp (%rsp),%r14\njne 14c8 \nmov 0x18(%rsp),%rax\ntest %eax,%eax\njle 1572 \nmov 0x28(%rsp),%r14\nsub $0x1,%eax\nshl $0x4,%rax\nlea 0x10(%r14,%rax,1),%rax\nmov %rax,(%rsp)\nlea 0x10(%r13),%rax\nmov %rax,0x8(%rsp)\nnopl (%rax)\ntest %ebp,%ebp\nje 1590 \nlea -0x1(%rbp),%ebx\nmov (%r14),%r12\nmov %r13,%r15\nshl $0x4,%rbx\nadd 0x8(%rsp),%rbx\njmp 1559 \nadd $0x10,%r15\ncmp %r15,%rbx\nje 1590 \nmov (%r15),%rsi\nmov %r12,%rdi\ncallq 10a0 \ntest %eax,%eax\njne 1550 \nadd $0x10,%r14\ncmp %r14,(%rsp)\njne 1538 \nadd $0x38,%rsp\nmov %ebp,%edx\nmov %r13,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw %cs:0x0(%rax,%rax,1)\nmovdqu (%r14),%xmm2\nmovslq %ebp,%rax\nadd $0x10,%r14\nadd $0x1,%ebp\nshl $0x4,%rax\nmovups %xmm2,0x0(%r13,%rax,1)\ncmp %r14,(%rsp)\njne 1538 \njmp 1572 \nnopl 0x0(%rax)\nmovdqu (%r14),%xmm0\nmovslq %ebp,%rax\nadd $0x10,%r14\nadd $0x1,%ebp\nshl $0x4,%rax\nmovups %xmm0,0x0(%r13,%rax,1)\ncmp %r14,(%rsp)\njne 1458 \njmpq 149e \nmovdqu (%r14),%xmm1\nmovslq %ebp,%rax\nadd $0x10,%r14\nadd $0x1,%ebp\nshl $0x4,%rax\nmovups %xmm1,0x0(%r13,%rax,1)\ncmp (%rsp),%r14\njne 14c8 \njmpq 150e \nxor %ebp,%ebp\njmpq 149e \n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14, rdi\nlea edi, [rcx+rsi]\npush r13\nadd edi, r9d\npush r12\nmovsxd rdi, edi\npush rbp\nshl rdi, 4; size\npush rbx\nmov rbx, rsi\nsub rsp, 38h\nmov [rsp+68h+var_48], rdx\nmov [rsp+68h+var_58], rcx\nmov [rsp+68h+var_40], r8\nmov [rsp+68h+var_50], r9\ncall _malloc\nmov r13, rax\ntest ebx, ebx\njle loc_1616\nmovsxd rbx, ebx\nxor r12d, r12d\nshl rbx, 4\nlea rax, [rbx+r14]\nmov [rsp+68h+var_68], rax\nnop dword ptr [rax+rax+00h]\nloc_1460:\nmovsxd rax, r12d\nmov rbx, rax\nmov [rsp+68h+var_60], rax\nshl rbx, 4\nadd rbx, r13\ntest r12d, r12d\njle loc_15B8\nloc_147B:\nmov rbp, [r14]\nmov r15, r13\njmp short loc_1495\nloc_1488:\nadd r15, 10h\ncmp r15, rbx\njz loc_15B8\nloc_1495:\nmov rsi, [r15]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1488\nmov rax, [rsp+68h+var_68]\nadd r14, 10h\ncmp r14, rax\njnz short loc_147B\nloc_14B1:\nmov rax, [rsp+68h+var_58]\ntest eax, eax\njle short loc_1519\nmovsxd r15, eax\nmov r14, [rsp+68h+var_48]\nshl r15, 4\nlea rax, [r15+r14]\nmov [rsp+68h+var_68], rax\nxchg ax, ax\nloc_14D0:\nmovsxd rbx, r12d\nmov dword ptr [rsp+68h+var_60], r12d\nshl rbx, 4\nadd rbx, r13\ntest r12d, r12d\njle loc_15E8\nloc_14E8:\nmov rbp, [r14]\nmov r15, r13\njmp short loc_14FD\nloc_14F0:\nadd r15, 10h\ncmp rbx, r15\njz loc_15E8\nloc_14FD:\nmov rsi, [r15]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njnz short loc_14F0\nmov rax, [rsp+68h+var_68]\nadd r14, 10h\ncmp r14, rax\njnz short loc_14E8\nloc_1519:\nmov rax, [rsp+68h+var_50]\ntest eax, eax\njle short loc_157A\nmov r14, [rsp+68h+var_40]\ncdqe\nshl rax, 4\nadd rax, r14\nmov [rsp+68h+var_68], rax\nnop dword ptr [rax+00h]\nloc_1538:\nmovsxd rbx, r12d\nmov dword ptr [rsp+68h+var_60], r12d\nshl rbx, 4\nadd rbx, r13\ntest r12d, r12d\njle short loc_1590\nloc_154C:\nmov rbp, [r14]\nmov r15, r13\njmp short loc_1561\nloc_1558:\nadd r15, 10h\ncmp rbx, r15\njz short loc_1590\nloc_1561:\nmov rsi, [r15]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1558\nadd r14, 10h\ncmp [rsp+68h+var_68], r14\njnz short loc_154C\nloc_157A:\nadd rsp, 38h\nmov edx, r12d\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1590:\nmovsxd r15, dword ptr [rsp+68h+var_60]\nmovdqu xmm2, xmmword ptr [r14]\nadd r12d, 1\nadd r14, 10h\nshl r15, 4\nmovups xmmword ptr [r13+r15+0], xmm2\ncmp [rsp+68h+var_68], r14\njnz short loc_1538\njmp short loc_157A\nloc_15B8:\nmov r15, [rsp+68h+var_60]\nmovdqu xmm0, xmmword ptr [r14]\nadd r12d, 1\nadd r14, 10h\nshl r15, 4\nmovups xmmword ptr [r13+r15+0], xmm0\ncmp [rsp+68h+var_68], r14\njnz loc_1460\njmp loc_14B1\nloc_15E8:\nmovsxd rax, dword ptr [rsp+68h+var_60]\nmovdqu xmm1, xmmword ptr [r14]\nadd r14, 10h\nadd r12d, 1\nshl rax, 4\nmovups xmmword ptr [r13+rax+0], xmm1\nmov rax, [rsp+68h+var_68]\ncmp r14, rax\njnz loc_14D0\njmp loc_1519\nloc_1616:\nxor r12d, r12d\njmp loc_14B1", + "ida_pseudo": "__m128i *__fastcall func0(const __m128i *a1, int a2, const __m128i *a3, int a4, const __m128i *a5, int a6)\n{\n const __m128i *v6; // r14\n __m128i *v7; // r13\n int v8; // r12d\n const char *v9; // rbp\n const char **v10; // r15\n const __m128i *v11; // r14\n const char *v12; // rbp\n const char **v13; // r15\n const __m128i *v14; // r14\n const char *v15; // rbp\n const char **v16; // r15\n __m128i v18; // xmm2\n __m128i v19; // xmm0\n __m128i v20; // xmm1\n const __m128i *v21; // [rsp+0h] [rbp-68h]\n const __m128i *v22; // [rsp+0h] [rbp-68h]\n const __m128i *v23; // [rsp+0h] [rbp-68h]\n __int64 v24; // [rsp+8h] [rbp-60h]\n int v25; // [rsp+8h] [rbp-60h]\n int v26; // [rsp+8h] [rbp-60h]\n\n v6 = a1;\n v7 = (__m128i *)malloc(16LL * (a6 + a4 + a2));\n if ( a2 <= 0 )\n {\n v8 = 0;\n }\n else\n {\n v8 = 0;\n v21 = &a1[a2];\n while ( 1 )\n {\n v24 = v8;\n if ( v8 > 0 )\n break;\nLABEL_25:\n v19 = _mm_loadu_si128(v6);\n ++v8;\n ++v6;\n v7[v24] = v19;\n if ( v21 == v6 )\n goto LABEL_8;\n }\n do\n {\n v9 = (const char *)v6->m128i_i64[0];\n v10 = (const char **)v7;\n while ( strcmp(v9, *v10) )\n {\n v10 += 2;\n if ( v10 == (const char **)&v7[v8] )\n goto LABEL_25;\n }\n ++v6;\n }\n while ( v6 != v21 );\n }\nLABEL_8:\n if ( a4 > 0 )\n {\n v11 = a3;\n v22 = &a3[a4];\n while ( 1 )\n {\n v25 = v8;\n if ( v8 > 0 )\n break;\nLABEL_27:\n v20 = _mm_loadu_si128(v11++);\n ++v8;\n v7[v25] = v20;\n if ( v11 == v22 )\n goto LABEL_15;\n }\n do\n {\n v12 = (const char *)v11->m128i_i64[0];\n v13 = (const char **)v7;\n while ( strcmp(v12, *v13) )\n {\n v13 += 2;\n if ( &v7[v8] == (__m128i *)v13 )\n goto LABEL_27;\n }\n ++v11;\n }\n while ( v11 != v22 );\n }\nLABEL_15:\n if ( a6 > 0 )\n {\n v14 = a5;\n v23 = &a5[a6];\n while ( 1 )\n {\n v26 = v8;\n if ( v8 > 0 )\n break;\nLABEL_23:\n v18 = _mm_loadu_si128(v14);\n ++v8;\n ++v14;\n v7[v26] = v18;\n if ( v23 == v14 )\n return v7;\n }\n do\n {\n v15 = (const char *)v14->m128i_i64[0];\n v16 = (const char **)v7;\n while ( strcmp(v15, *v16) )\n {\n v16 += 2;\n if ( &v7[v8] == (__m128i *)v16 )\n goto LABEL_23;\n }\n ++v14;\n }\n while ( v23 != v14 );\n }\n return v7;\n}", + "ida_strip_asm": "sub_1400:\nendbr64\npush r15\npush r14\nmov r14, rdi\nlea edi, [rcx+rsi]\npush r13\nadd edi, r9d\npush r12\nmovsxd rdi, edi\npush rbp\nshl rdi, 4; size\npush rbx\nmov rbx, rsi\nsub rsp, 38h\nmov [rsp+68h+var_48], rdx\nmov [rsp+68h+var_58], rcx\nmov [rsp+68h+var_40], r8\nmov [rsp+68h+var_50], r9\ncall _malloc\nmov r13, rax\ntest ebx, ebx\njle loc_1616\nmovsxd rbx, ebx\nxor r12d, r12d\nshl rbx, 4\nlea rax, [rbx+r14]\nmov [rsp+68h+var_68], rax\nnop dword ptr [rax+rax+00h]\nloc_1460:\nmovsxd rax, r12d\nmov rbx, rax\nmov [rsp+68h+var_60], rax\nshl rbx, 4\nadd rbx, r13\ntest r12d, r12d\njle loc_15B8\nloc_147B:\nmov rbp, [r14]\nmov r15, r13\njmp short loc_1495\nloc_1488:\nadd r15, 10h\ncmp r15, rbx\njz loc_15B8\nloc_1495:\nmov rsi, [r15]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1488\nmov rax, [rsp+68h+var_68]\nadd r14, 10h\ncmp r14, rax\njnz short loc_147B\nloc_14B1:\nmov rax, [rsp+68h+var_58]\ntest eax, eax\njle short loc_1519\nmovsxd r15, eax\nmov r14, [rsp+68h+var_48]\nshl r15, 4\nlea rax, [r15+r14]\nmov [rsp+68h+var_68], rax\nxchg ax, ax\nloc_14D0:\nmovsxd rbx, r12d\nmov dword ptr [rsp+68h+var_60], r12d\nshl rbx, 4\nadd rbx, r13\ntest r12d, r12d\njle loc_15E8\nloc_14E8:\nmov rbp, [r14]\nmov r15, r13\njmp short loc_14FD\nloc_14F0:\nadd r15, 10h\ncmp rbx, r15\njz loc_15E8\nloc_14FD:\nmov rsi, [r15]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njnz short loc_14F0\nmov rax, [rsp+68h+var_68]\nadd r14, 10h\ncmp r14, rax\njnz short loc_14E8\nloc_1519:\nmov rax, [rsp+68h+var_50]\ntest eax, eax\njle short loc_157A\nmov r14, [rsp+68h+var_40]\ncdqe\nshl rax, 4\nadd rax, r14\nmov [rsp+68h+var_68], rax\nnop dword ptr [rax+00h]\nloc_1538:\nmovsxd rbx, r12d\nmov dword ptr [rsp+68h+var_60], r12d\nshl rbx, 4\nadd rbx, r13\ntest r12d, r12d\njle short loc_1590\nloc_154C:\nmov rbp, [r14]\nmov r15, r13\njmp short loc_1561\nloc_1558:\nadd r15, 10h\ncmp rbx, r15\njz short loc_1590\nloc_1561:\nmov rsi, [r15]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1558\nadd r14, 10h\ncmp [rsp+68h+var_68], r14\njnz short loc_154C\nloc_157A:\nadd rsp, 38h\nmov edx, r12d\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1590:\nmovsxd r15, dword ptr [rsp+68h+var_60]\nmovdqu xmm2, xmmword ptr [r14]\nadd r12d, 1\nadd r14, 10h\nshl r15, 4\nmovups xmmword ptr [r13+r15+0], xmm2\ncmp [rsp+68h+var_68], r14\njnz short loc_1538\njmp short loc_157A\nloc_15B8:\nmov r15, [rsp+68h+var_60]\nmovdqu xmm0, xmmword ptr [r14]\nadd r12d, 1\nadd r14, 10h\nshl r15, 4\nmovups xmmword ptr [r13+r15+0], xmm0\ncmp [rsp+68h+var_68], r14\njnz loc_1460\njmp loc_14B1\nloc_15E8:\nmovsxd rax, dword ptr [rsp+68h+var_60]\nmovdqu xmm1, xmmword ptr [r14]\nadd r14, 10h\nadd r12d, 1\nshl rax, 4\nmovups xmmword ptr [r13+rax+0], xmm1\nmov rax, [rsp+68h+var_68]\ncmp r14, rax\njnz loc_14D0\njmp loc_1519\nloc_1616:\nxor r12d, r12d\njmp loc_14B1", + "ida_strip_pseudo": "__m128i *__fastcall sub_1400(const __m128i *a1, int a2, const __m128i *a3, int a4, const __m128i *a5, int a6)\n{\n const __m128i *v6; // r14\n __m128i *v7; // r13\n int v8; // r12d\n const char *v9; // rbp\n const char **v10; // r15\n const __m128i *v11; // r14\n const char *v12; // rbp\n const char **v13; // r15\n const __m128i *v14; // r14\n const char *v15; // rbp\n const char **v16; // r15\n __m128i v18; // xmm2\n __m128i v19; // xmm0\n __m128i v20; // xmm1\n const __m128i *v21; // [rsp+0h] [rbp-68h]\n const __m128i *v22; // [rsp+0h] [rbp-68h]\n const __m128i *v23; // [rsp+0h] [rbp-68h]\n __int64 v24; // [rsp+8h] [rbp-60h]\n int v25; // [rsp+8h] [rbp-60h]\n int v26; // [rsp+8h] [rbp-60h]\n\n v6 = a1;\n v7 = (__m128i *)malloc(16LL * (a6 + a4 + a2));\n if ( a2 <= 0 )\n {\n v8 = 0;\n }\n else\n {\n v8 = 0;\n v21 = &a1[a2];\n while ( 1 )\n {\n v24 = v8;\n if ( v8 > 0 )\n break;\nLABEL_25:\n v19 = _mm_loadu_si128(v6);\n ++v8;\n ++v6;\n v7[v24] = v19;\n if ( v21 == v6 )\n goto LABEL_8;\n }\n do\n {\n v9 = (const char *)v6->m128i_i64[0];\n v10 = (const char **)v7;\n while ( strcmp(v9, *v10) )\n {\n v10 += 2;\n if ( v10 == (const char **)&v7[v8] )\n goto LABEL_25;\n }\n ++v6;\n }\n while ( v6 != v21 );\n }\nLABEL_8:\n if ( a4 > 0 )\n {\n v11 = a3;\n v22 = &a3[a4];\n while ( 1 )\n {\n v25 = v8;\n if ( v8 > 0 )\n break;\nLABEL_27:\n v20 = _mm_loadu_si128(v11++);\n ++v8;\n v7[v25] = v20;\n if ( v11 == v22 )\n goto LABEL_15;\n }\n do\n {\n v12 = (const char *)v11->m128i_i64[0];\n v13 = (const char **)v7;\n while ( strcmp(v12, *v13) )\n {\n v13 += 2;\n if ( &v7[v8] == (__m128i *)v13 )\n goto LABEL_27;\n }\n ++v11;\n }\n while ( v11 != v22 );\n }\nLABEL_15:\n if ( a6 > 0 )\n {\n v14 = a5;\n v23 = &a5[a6];\n while ( 1 )\n {\n v26 = v8;\n if ( v8 > 0 )\n break;\nLABEL_23:\n v18 = _mm_loadu_si128(v14);\n ++v8;\n ++v14;\n v7[v26] = v18;\n if ( v23 == v14 )\n return v7;\n }\n do\n {\n v15 = (const char *)v14->m128i_i64[0];\n v16 = (const char **)v7;\n while ( strcmp(v15, *v16) )\n {\n v16 += 2;\n if ( &v7[v8] == (__m128i *)v16 )\n goto LABEL_23;\n }\n ++v14;\n }\n while ( v23 != v14 );\n }\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__m128i *sub_1400(const __m128i *a1, int a2, const __m128i *a3, int a4,\n const __m128i *a5, int a6) {\n const __m128i *v6;\n __m128i *v7;\n int v8;\n const char *v9;\n const char **v10;\n const __m128i *v11;\n const char *v12;\n const char **v13;\n const __m128i *v14;\n const char *v15;\n const char **v16;\n __m128i v18;\n __m128i v19;\n __m128i v20;\n const __m128i *v21;\n const __m128i *v22;\n const __m128i *v23;\n long long v24;\n int v25;\n int v26;\n v6 = a1;\n v7 = (__m128i *)malloc(16LL * (a6 + a4 + a2));\n if (a2 <= 0) {\n v8 = 0;\n } else {\n v8 = 0;\n v21 = &a1[a2];\n while (1) {\n v24 = v8;\n if (v8 > 0) break;\n LABEL_25:\n v19 = _mm_loadu_si128(v6);\n ++v8;\n ++v6;\n v7[v24] = v19;\n if (v21 == v6) goto LABEL_8;\n }\n do {\n v9 = (const char *)v6->m128i_i64[0];\n v10 = (const char **)v7;\n while (strcmp(v9, *v10)) {\n v10 += 2;\n if (v10 == (const char **)&v7[v8]) goto LABEL_25;\n }\n ++v6;\n } while (v6 != v21);\n }\nLABEL_8:\n if (a4 > 0) {\n v11 = a3;\n v22 = &a3[a4];\n while (1) {\n v25 = v8;\n if (v8 > 0) break;\n LABEL_27:\n v20 = _mm_loadu_si128(v11++);\n ++v8;\n v7[v25] = v20;\n if (v11 == v22) goto LABEL_15;\n }\n do {\n v12 = (const char *)v11->m128i_i64[0];\n v13 = (const char **)v7;\n while (strcmp(v12, *v13)) {\n v13 += 2;\n if (&v7[v8] == (__m128i *)v13) goto LABEL_27;\n }\n ++v11;\n } while (v11 != v22);\n }\nLABEL_15:\n if (a6 > 0) {\n v14 = a5;\n v23 = &a5[a6];\n while (1) {\n v26 = v8;\n if (v8 > 0) break;\n LABEL_23:\n v18 = _mm_loadu_si128(v14);\n ++v8;\n ++v14;\n v7[v26] = v18;\n if (v23 == v14) return v7;\n }\n do {\n v15 = (const char *)v14->m128i_i64[0];\n v16 = (const char **)v7;\n while (strcmp(v15, *v16)) {\n v16 += 2;\n if (&v7[v8] == (__m128i *)v16) goto LABEL_23;\n }\n ++v14;\n } while (v23 != v14);\n }\n return v7;\n}", + "ida_pseudo_norm": "__m128i *func0(const __m128i *a1, int a2, const __m128i *a3, int a4,\n const __m128i *a5, int a6) {\n const __m128i *v6;\n __m128i *v7;\n int v8;\n const char *v9;\n const char **v10;\n const __m128i *v11;\n const char *v12;\n const char **v13;\n const __m128i *v14;\n const char *v15;\n const char **v16;\n __m128i v18;\n __m128i v19;\n __m128i v20;\n const __m128i *v21;\n const __m128i *v22;\n const __m128i *v23;\n long long v24;\n int v25;\n int v26;\n v6 = a1;\n v7 = (__m128i *)malloc(16LL * (a6 + a4 + a2));\n if (a2 <= 0) {\n v8 = 0;\n } else {\n v8 = 0;\n v21 = &a1[a2];\n while (1) {\n v24 = v8;\n if (v8 > 0) break;\n LABEL_25:\n v19 = _mm_loadu_si128(v6);\n ++v8;\n ++v6;\n v7[v24] = v19;\n if (v21 == v6) goto LABEL_8;\n }\n do {\n v9 = (const char *)v6->m128i_i64[0];\n v10 = (const char **)v7;\n while (strcmp(v9, *v10)) {\n v10 += 2;\n if (v10 == (const char **)&v7[v8]) goto LABEL_25;\n }\n ++v6;\n } while (v6 != v21);\n }\nLABEL_8:\n if (a4 > 0) {\n v11 = a3;\n v22 = &a3[a4];\n while (1) {\n v25 = v8;\n if (v8 > 0) break;\n LABEL_27:\n v20 = _mm_loadu_si128(v11++);\n ++v8;\n v7[v25] = v20;\n if (v11 == v22) goto LABEL_15;\n }\n do {\n v12 = (const char *)v11->m128i_i64[0];\n v13 = (const char **)v7;\n while (strcmp(v12, *v13)) {\n v13 += 2;\n if (&v7[v8] == (__m128i *)v13) goto LABEL_27;\n }\n ++v11;\n } while (v11 != v22);\n }\nLABEL_15:\n if (a6 > 0) {\n v14 = a5;\n v23 = &a5[a6];\n while (1) {\n v26 = v8;\n if (v8 > 0) break;\n LABEL_23:\n v18 = _mm_loadu_si128(v14);\n ++v8;\n ++v14;\n v7[v26] = v18;\n if (v23 == v14) return v7;\n }\n do {\n v15 = (const char *)v14->m128i_i64[0];\n v16 = (const char **)v7;\n while (strcmp(v15, *v16)) {\n v16 += 2;\n if (&v7[v8] == (__m128i *)v16) goto LABEL_23;\n }\n ++v14;\n } while (v23 != v14);\n }\n return v7;\n}" + }, + { + "index": 88, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int key;\n\n int value;\n\n} Pair;\n\n\n\nint cmpfunc(const void *a, const void *b) {\n\n return ((Pair *)a)->key - ((Pair *)b)->key;\n\n}\n\n\n\n", + "func": "Pair *func0(int arr[], int size, int *count) {\n qsort(arr, size, sizeof(int), cmpfunc);\n Pair *frequency = malloc(sizeof(Pair) * size);\n int current = arr[0];\n int freq = 1;\n int index = 0;\n for (int i = 1; i < size; i++) {\n if (arr[i] == current) {\n freq++;\n } else {\n frequency[index].key = current;\n frequency[index].value = freq;\n index++;\n current = arr[i];\n freq = 1;\n }\n }\n frequency[index].key = current;\n frequency[index].value = freq;\n index++;\n *count = index;\n return frequency;\n}", + "test": "int main() {\n\n int count1, count2, count3;\n\n \n\n int arr1[] = {10,10,10,10,20,20,20,20,40,40,50,50,30};\n\n Pair *result1 = func0(arr1, 13, &count1);\n\n assert(count1 == 5);\n\n assert(result1[0].key == 10 && result1[0].value == 4);\n\n assert(result1[1].key == 20 && result1[1].value == 4);\n\n assert(result1[2].key == 30 && result1[2].value == 1);\n\n assert(result1[3].key == 40 && result1[3].value == 2);\n\n assert(result1[4].key == 50 && result1[4].value == 2);\n\n free(result1);\n\n\n\n int arr2[] = {1,2,3,4,3,2,4,1,3,1,4};\n\n Pair *result2 = func0(arr2, 11, &count2);\n\n assert(count2 == 4);\n\n assert(result2[0].key == 1 && result2[0].value == 3);\n\n assert(result2[1].key == 2 && result2[1].value == 2);\n\n assert(result2[2].key == 3 && result2[2].value == 3);\n\n assert(result2[3].key == 4 && result2[3].value == 3);\n\n free(result2);\n\n\n\n int arr3[] = {5,6,7,4,9,10,4,5,6,7,9,5};\n\n Pair *result3 = func0(arr3, 12, &count3);\n\n assert(count3 == 6);\n\n assert(result3[0].key == 4 && result3[0].value == 2);\n\n assert(result3[1].key == 5 && result3[1].value == 3);\n\n assert(result3[2].key == 6 && result3[2].value == 2);\n\n assert(result3[3].key == 7 && result3[3].value == 2);\n\n assert(result3[4].key == 9 && result3[4].value == 2);\n\n assert(result3[5].key == 10 && result3[5].value == 1);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x40,%rsp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmov %rdx,-0x38(%rbp)\nmov -0x2c(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x28(%rbp),%rax\nlea -0x4a(%rip),%rcx\nmov $0x4,%edx\nmov %rax,%rdi\ncallq 10a0 \nmov -0x2c(%rbp),%eax\ncltq\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,-0x8(%rbp)\nmov -0x28(%rbp),%rax\nmov (%rax),%eax\nmov %eax,-0x18(%rbp)\nmovl $0x1,-0x14(%rbp)\nmovl $0x0,-0x10(%rbp)\nmovl $0x1,-0xc(%rbp)\njmp 12d1 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x18(%rbp)\njne 1276 \naddl $0x1,-0x14(%rbp)\njmp 12cd \nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov -0x18(%rbp),%eax\nmov %eax,(%rdx)\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov -0x14(%rbp),%eax\nmov %eax,0x4(%rdx)\naddl $0x1,-0x10(%rbp)\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x18(%rbp)\nmovl $0x1,-0x14(%rbp)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 1255 \nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov -0x18(%rbp),%eax\nmov %eax,(%rdx)\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov -0x14(%rbp),%eax\nmov %eax,0x4(%rdx)\naddl $0x1,-0x10(%rbp)\nmov -0x38(%rbp),%rax\nmov -0x10(%rbp),%edx\nmov %edx,(%rax)\nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+base], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmov eax, [rbp+var_2C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, cmpfunc\nmov rcx, rdx; compar\nmov edx, 4; size\nmov rdi, rax; base\ncall _qsort\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov rax, [rbp+base]\nmov eax, [rax]\nmov [rbp+var_18], eax\nmov [rbp+var_14], 1\nmov [rbp+var_10], 0\nmov [rbp+var_C], 1\njmp short loc_12D4\nloc_1258:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_18], eax\njnz short loc_1279\nadd [rbp+var_14], 1\njmp short loc_12D0\nloc_1279:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_18]\nmov [rdx], eax\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_14]\nmov [rdx+4], eax\nadd [rbp+var_10], 1\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_18], eax\nmov [rbp+var_14], 1\nloc_12D0:\nadd [rbp+var_C], 1\nloc_12D4:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_2C]\njl loc_1258\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_18]\nmov [rdx], eax\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_14]\nmov [rdx+4], eax\nadd [rbp+var_10], 1\nmov rax, [rbp+var_38]\nmov edx, [rbp+var_10]\nmov [rax], edx\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2, _DWORD *a3)\n{\n int v5; // [rsp+28h] [rbp-18h]\n int v6; // [rsp+2Ch] [rbp-14h]\n int v7; // [rsp+30h] [rbp-10h]\n int i; // [rsp+34h] [rbp-Ch]\n _DWORD *v9; // [rsp+38h] [rbp-8h]\n\n qsort(a1, a2, 4uLL, cmpfunc);\n v9 = malloc(8LL * a2);\n v5 = *a1;\n v6 = 1;\n v7 = 0;\n for ( i = 1; i < a2; ++i )\n {\n if ( v5 == a1[i] )\n {\n ++v6;\n }\n else\n {\n v9[2 * v7] = v5;\n v9[2 * v7++ + 1] = v6;\n v5 = a1[i];\n v6 = 1;\n }\n }\n v9[2 * v7] = v5;\n v9[2 * v7 + 1] = v6;\n *a3 = v7 + 1;\n return v9;\n}", + "ida_strip_asm": "sub_11EB:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+base], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmov eax, [rbp+var_2C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 4; size\nmov rdi, rax; base\ncall _qsort\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov rax, [rbp+base]\nmov eax, [rax]\nmov [rbp+var_18], eax\nmov [rbp+var_14], 1\nmov [rbp+var_10], 0\nmov [rbp+var_C], 1\njmp short loc_12D4\nloc_1258:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_18], eax\njnz short loc_1279\nadd [rbp+var_14], 1\njmp short loc_12D0\nloc_1279:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_18]\nmov [rdx], eax\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_14]\nmov [rdx+4], eax\nadd [rbp+var_10], 1\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_18], eax\nmov [rbp+var_14], 1\nloc_12D0:\nadd [rbp+var_C], 1\nloc_12D4:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_2C]\njl loc_1258\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_18]\nmov [rdx], eax\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_14]\nmov [rdx+4], eax\nadd [rbp+var_10], 1\nmov rax, [rbp+var_38]\nmov edx, [rbp+var_10]\nmov [rax], edx\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11EB(int *a1, int a2, _DWORD *a3)\n{\n int v5; // [rsp+28h] [rbp-18h]\n int v6; // [rsp+2Ch] [rbp-14h]\n int v7; // [rsp+30h] [rbp-10h]\n int i; // [rsp+34h] [rbp-Ch]\n _DWORD *v9; // [rsp+38h] [rbp-8h]\n\n qsort(a1, a2, 4uLL, compar);\n v9 = malloc(8LL * a2);\n v5 = *a1;\n v6 = 1;\n v7 = 0;\n for ( i = 1; i < a2; ++i )\n {\n if ( v5 == a1[i] )\n {\n ++v6;\n }\n else\n {\n v9[2 * v7] = v5;\n v9[2 * v7++ + 1] = v6;\n v5 = a1[i];\n v6 = 1;\n }\n }\n v9[2 * v7] = v5;\n v9[2 * v7 + 1] = v6;\n *a3 = v7 + 1;\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11EB(int *a1, int a2, uint32_t *a3) {\n int v5;\n int v6;\n int v7;\n int i;\n uint32_t *v9;\n qsort(a1, a2, 4uLL, compar);\n v9 = malloc(8LL * a2);\n v5 = *a1;\n v6 = 1;\n v7 = 0;\n for (i = 1; i < a2; ++i) {\n if (v5 == a1[i]) {\n ++v6;\n } else {\n v9[2 * v7] = v5;\n v9[2 * v7++ + 1] = v6;\n v5 = a1[i];\n v6 = 1;\n }\n }\n v9[2 * v7] = v5;\n v9[2 * v7 + 1] = v6;\n *a3 = v7 + 1;\n return v9;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2, uint32_t *a3) {\n int v5;\n int v6;\n int v7;\n int i;\n uint32_t *v9;\n qsort(a1, a2, 4uLL, cmpfunc);\n v9 = malloc(8LL * a2);\n v5 = *a1;\n v6 = 1;\n v7 = 0;\n for (i = 1; i < a2; ++i) {\n if (v5 == a1[i]) {\n ++v6;\n } else {\n v9[2 * v7] = v5;\n v9[2 * v7++ + 1] = v6;\n v5 = a1[i];\n v6 = 1;\n }\n }\n v9[2 * v7] = v5;\n v9[2 * v7 + 1] = v6;\n *a3 = v7 + 1;\n return v9;\n}" + }, + { + "index": 88, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int key;\n\n int value;\n\n} Pair;\n\n\n\nint cmpfunc(const void *a, const void *b) {\n\n return ((Pair *)a)->key - ((Pair *)b)->key;\n\n}\n\n\n\n", + "func": "Pair *func0(int arr[], int size, int *count) {\n qsort(arr, size, sizeof(int), cmpfunc);\n Pair *frequency = malloc(sizeof(Pair) * size);\n int current = arr[0];\n int freq = 1;\n int index = 0;\n for (int i = 1; i < size; i++) {\n if (arr[i] == current) {\n freq++;\n } else {\n frequency[index].key = current;\n frequency[index].value = freq;\n index++;\n current = arr[i];\n freq = 1;\n }\n }\n frequency[index].key = current;\n frequency[index].value = freq;\n index++;\n *count = index;\n return frequency;\n}", + "test": "int main() {\n\n int count1, count2, count3;\n\n \n\n int arr1[] = {10,10,10,10,20,20,20,20,40,40,50,50,30};\n\n Pair *result1 = func0(arr1, 13, &count1);\n\n assert(count1 == 5);\n\n assert(result1[0].key == 10 && result1[0].value == 4);\n\n assert(result1[1].key == 20 && result1[1].value == 4);\n\n assert(result1[2].key == 30 && result1[2].value == 1);\n\n assert(result1[3].key == 40 && result1[3].value == 2);\n\n assert(result1[4].key == 50 && result1[4].value == 2);\n\n free(result1);\n\n\n\n int arr2[] = {1,2,3,4,3,2,4,1,3,1,4};\n\n Pair *result2 = func0(arr2, 11, &count2);\n\n assert(count2 == 4);\n\n assert(result2[0].key == 1 && result2[0].value == 3);\n\n assert(result2[1].key == 2 && result2[1].value == 2);\n\n assert(result2[2].key == 3 && result2[2].value == 3);\n\n assert(result2[3].key == 4 && result2[3].value == 3);\n\n free(result2);\n\n\n\n int arr3[] = {5,6,7,4,9,10,4,5,6,7,9,5};\n\n Pair *result3 = func0(arr3, 12, &count3);\n\n assert(count3 == 6);\n\n assert(result3[0].key == 4 && result3[0].value == 2);\n\n assert(result3[1].key == 5 && result3[1].value == 3);\n\n assert(result3[2].key == 6 && result3[2].value == 2);\n\n assert(result3[3].key == 7 && result3[3].value == 2);\n\n assert(result3[4].key == 9 && result3[4].value == 2);\n\n assert(result3[5].key == 10 && result3[5].value == 1);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbp\nmov %esi,%r12d\nmov %rdx,%rbx\nmovslq %esi,%r13\nlea -0x2a(%rip),%rcx\nmov $0x4,%edx\nmov %r13,%rsi\ncallq 10a0 \nlea 0x0(,%r13,8),%rdi\ncallq 10d0 \nmov 0x0(%rbp),%edi\ncmp $0x1,%r12d\njle 125f \nlea 0x4(%rbp),%rdx\nlea -0x2(%r12),%ecx\nlea 0x8(%rbp,%rcx,4),%r10\nmov $0x0,%esi\nmov $0x1,%r8d\njmp 1253 \nmovslq %esi,%r9\nlea (%rax,%r9,8),%r9\nmov %edi,(%r9)\nmov %r8d,0x4(%r9)\nadd $0x1,%esi\nmov %ecx,%edi\nmov $0x1,%r8d\nadd $0x4,%rdx\ncmp %r10,%rdx\nje 126a \nmov (%rdx),%ecx\ncmp %edi,%ecx\njne 1231 \nadd $0x1,%r8d\njmp 124a \nmov $0x0,%esi\nmov $0x1,%r8d\nmovslq %esi,%rdx\nlea (%rax,%rdx,8),%rdx\nmov %edi,(%rdx)\nmov %r8d,0x4(%rdx)\nadd $0x1,%esi\nmov %esi,(%rbx)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov r12d, esi\nmov rbx, rdx\nmovsxd r13, esi\nlea rcx, cmpfunc; compar\nmov edx, 4; size\nmov rsi, r13; nmemb\ncall _qsort\nlea rdi, ds:0[r13*8]; size\ncall _malloc\nmov r9, rax\nmov edx, [rbp+0]\ncmp r12d, 1\njle short loc_125F\nlea rax, [rbp+4]\nlea ecx, [r12-2]\nlea r10, [rbp+rcx*4+8]\nmov esi, 0\nmov edi, 1\njmp short loc_123F\nloc_1233:\nadd edi, 1\nloc_1236:\nadd rax, 4\ncmp rax, r10\njz short loc_1269\nloc_123F:\nmov ecx, edx\nmov edx, [rax]\ncmp edx, ecx\njz short loc_1233\nmovsxd r8, esi\nlea r8, [r9+r8*8]\nmov [r8], ecx\nmov [r8+4], edi\nadd esi, 1\nmov edi, 1\njmp short loc_1236\nloc_125F:\nmov esi, 0\nmov edi, 1\nloc_1269:\nmovsxd rax, esi\nlea rax, [r9+rax*8]\nmov [rax], edx\nmov [rax+4], edi\nadd esi, 1\nmov [rbx], esi\nmov rax, r9\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "char *__fastcall func0(int *a1, int a2, _DWORD *a3)\n{\n char *v6; // r9\n int v7; // edx\n int *v8; // rax\n int v9; // esi\n int v10; // edi\n int v11; // ecx\n char *v12; // r8\n char *v13; // rax\n\n qsort(a1, a2, 4uLL, cmpfunc);\n v6 = (char *)malloc(8LL * a2);\n v7 = *a1;\n if ( a2 <= 1 )\n {\n v9 = 0;\n v10 = 1;\n }\n else\n {\n v8 = a1 + 1;\n v9 = 0;\n v10 = 1;\n do\n {\n v11 = v7;\n v7 = *v8;\n if ( *v8 == v11 )\n {\n ++v10;\n }\n else\n {\n v12 = &v6[8 * v9];\n *(_DWORD *)v12 = v11;\n *((_DWORD *)v12 + 1) = v10;\n ++v9;\n v10 = 1;\n }\n ++v8;\n }\n while ( v8 != &a1[a2 - 2 + 2] );\n }\n v13 = &v6[8 * v9];\n *(_DWORD *)v13 = v7;\n *((_DWORD *)v13 + 1) = v10;\n *a3 = v9 + 1;\n return v6;\n}", + "ida_strip_asm": "sub_11D2:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov r12d, esi\nmov rbx, rdx\nmovsxd r13, esi\nlea rcx, compar; compar\nmov edx, 4; size\nmov rsi, r13; nmemb\ncall _qsort\nlea rdi, ds:0[r13*8]; size\ncall _malloc\nmov r9, rax\nmov edx, [rbp+0]\ncmp r12d, 1\njle short loc_125F\nlea rax, [rbp+4]\nlea ecx, [r12-2]\nlea r10, [rbp+rcx*4+8]\nmov esi, 0\nmov edi, 1\njmp short loc_123F\nloc_1233:\nadd edi, 1\nloc_1236:\nadd rax, 4\ncmp rax, r10\njz short loc_1269\nloc_123F:\nmov ecx, edx\nmov edx, [rax]\ncmp edx, ecx\njz short loc_1233\nmovsxd r8, esi\nlea r8, [r9+r8*8]\nmov [r8], ecx\nmov [r8+4], edi\nadd esi, 1\nmov edi, 1\njmp short loc_1236\nloc_125F:\nmov esi, 0\nmov edi, 1\nloc_1269:\nmovsxd rax, esi\nlea rax, [r9+rax*8]\nmov [rax], edx\nmov [rax+4], edi\nadd esi, 1\nmov [rbx], esi\nmov rax, r9\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11D2(int *a1, int a2, _DWORD *a3)\n{\n char *v6; // r9\n int v7; // edx\n int *v8; // rax\n int v9; // esi\n int v10; // edi\n int v11; // ecx\n char *v12; // r8\n char *v13; // rax\n\n qsort(a1, a2, 4uLL, compar);\n v6 = (char *)malloc(8LL * a2);\n v7 = *a1;\n if ( a2 <= 1 )\n {\n v9 = 0;\n v10 = 1;\n }\n else\n {\n v8 = a1 + 1;\n v9 = 0;\n v10 = 1;\n do\n {\n v11 = v7;\n v7 = *v8;\n if ( *v8 == v11 )\n {\n ++v10;\n }\n else\n {\n v12 = &v6[8 * v9];\n *(_DWORD *)v12 = v11;\n *((_DWORD *)v12 + 1) = v10;\n ++v9;\n v10 = 1;\n }\n ++v8;\n }\n while ( v8 != &a1[a2 - 2 + 2] );\n }\n v13 = &v6[8 * v9];\n *(_DWORD *)v13 = v7;\n *((_DWORD *)v13 + 1) = v10;\n *a3 = v9 + 1;\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11D2(int *a1, int a2, uint32_t *a3) {\n char *v6;\n int v7;\n int *v8;\n int v9;\n int v10;\n int v11;\n char *v12;\n char *v13;\n qsort(a1, a2, 4uLL, compar);\n v6 = (char *)malloc(8LL * a2);\n v7 = *a1;\n if (a2 <= 1) {\n v9 = 0;\n v10 = 1;\n } else {\n v8 = a1 + 1;\n v9 = 0;\n v10 = 1;\n do {\n v11 = v7;\n v7 = *v8;\n if (*v8 == v11) {\n ++v10;\n } else {\n v12 = &v6[8 * v9];\n *(uint32_t *)v12 = v11;\n *((uint32_t *)v12 + 1) = v10;\n ++v9;\n v10 = 1;\n }\n ++v8;\n } while (v8 != &a1[a2 - 2 + 2]);\n }\n v13 = &v6[8 * v9];\n *(uint32_t *)v13 = v7;\n *((uint32_t *)v13 + 1) = v10;\n *a3 = v9 + 1;\n return v6;\n}", + "ida_pseudo_norm": "char *func0(int *a1, int a2, uint32_t *a3) {\n char *v6;\n int v7;\n int *v8;\n int v9;\n int v10;\n int v11;\n char *v12;\n char *v13;\n qsort(a1, a2, 4uLL, cmpfunc);\n v6 = (char *)malloc(8LL * a2);\n v7 = *a1;\n if (a2 <= 1) {\n v9 = 0;\n v10 = 1;\n } else {\n v8 = a1 + 1;\n v9 = 0;\n v10 = 1;\n do {\n v11 = v7;\n v7 = *v8;\n if (*v8 == v11) {\n ++v10;\n } else {\n v12 = &v6[8 * v9];\n *(uint32_t *)v12 = v11;\n *((uint32_t *)v12 + 1) = v10;\n ++v9;\n v10 = 1;\n }\n ++v8;\n } while (v8 != &a1[a2 - 2 + 2]);\n }\n v13 = &v6[8 * v9];\n *(uint32_t *)v13 = v7;\n *((uint32_t *)v13 + 1) = v10;\n *a3 = v9 + 1;\n return v6;\n}" + }, + { + "index": 88, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int key;\n\n int value;\n\n} Pair;\n\n\n\nint cmpfunc(const void *a, const void *b) {\n\n return ((Pair *)a)->key - ((Pair *)b)->key;\n\n}\n\n\n\n", + "func": "Pair *func0(int arr[], int size, int *count) {\n qsort(arr, size, sizeof(int), cmpfunc);\n Pair *frequency = malloc(sizeof(Pair) * size);\n int current = arr[0];\n int freq = 1;\n int index = 0;\n for (int i = 1; i < size; i++) {\n if (arr[i] == current) {\n freq++;\n } else {\n frequency[index].key = current;\n frequency[index].value = freq;\n index++;\n current = arr[i];\n freq = 1;\n }\n }\n frequency[index].key = current;\n frequency[index].value = freq;\n index++;\n *count = index;\n return frequency;\n}", + "test": "int main() {\n\n int count1, count2, count3;\n\n \n\n int arr1[] = {10,10,10,10,20,20,20,20,40,40,50,50,30};\n\n Pair *result1 = func0(arr1, 13, &count1);\n\n assert(count1 == 5);\n\n assert(result1[0].key == 10 && result1[0].value == 4);\n\n assert(result1[1].key == 20 && result1[1].value == 4);\n\n assert(result1[2].key == 30 && result1[2].value == 1);\n\n assert(result1[3].key == 40 && result1[3].value == 2);\n\n assert(result1[4].key == 50 && result1[4].value == 2);\n\n free(result1);\n\n\n\n int arr2[] = {1,2,3,4,3,2,4,1,3,1,4};\n\n Pair *result2 = func0(arr2, 11, &count2);\n\n assert(count2 == 4);\n\n assert(result2[0].key == 1 && result2[0].value == 3);\n\n assert(result2[1].key == 2 && result2[1].value == 2);\n\n assert(result2[2].key == 3 && result2[2].value == 3);\n\n assert(result2[3].key == 4 && result2[3].value == 3);\n\n free(result2);\n\n\n\n int arr3[] = {5,6,7,4,9,10,4,5,6,7,9,5};\n\n Pair *result3 = func0(arr3, 12, &count3);\n\n assert(count3 == 6);\n\n assert(result3[0].key == 4 && result3[0].value == 2);\n\n assert(result3[1].key == 5 && result3[1].value == 3);\n\n assert(result3[2].key == 6 && result3[2].value == 2);\n\n assert(result3[3].key == 7 && result3[3].value == 2);\n\n assert(result3[4].key == 9 && result3[4].value == 2);\n\n assert(result3[5].key == 10 && result3[5].value == 1);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nlea -0x1d(%rip),%rcx\nmov %rdi,%r13\npush %r12\nmovslq %esi,%r12\npush %rbp\nmov %r12,%rsi\npush %rbx\nmov %rdx,%rbx\nmov $0x4,%edx\nsub $0x8,%rsp\ncallq 10a0 \nlea 0x0(,%r12,8),%rdi\ncallq 10d0 \nmov 0x0(%r13),%r9d\ncmp $0x1,%r12d\njle 17b0 \nlea -0x2(%r12),%edx\nlea 0x4(%r13),%rcx\nxor %esi,%esi\nmov $0x1,%r10d\nlea 0x8(%r13,%rdx,4),%rbp\njmp 1774 \nnopw 0x0(%rax,%rax,1)\nadd $0x4,%rcx\nmov %r9d,(%rdi)\nmov %r8d,%r9d\nmov %r10d,0x4(%rdi)\nlea 0x8(%rax,%rdx,1),%rdi\nmov $0x1,%r10d\nlea 0x2(%rsi),%edx\nmov %r11d,%esi\ncmp %rbp,%rcx\nje 179b \nmovslq %esi,%rdx\nmov (%rcx),%r8d\nlea 0x1(%rsi),%r11d\nshl $0x3,%rdx\nlea (%rax,%rdx,1),%rdi\ncmp %r9d,%r8d\njne 1750 \nadd $0x4,%rcx\nadd $0x1,%r10d\nmov %r11d,%edx\ncmp %rbp,%rcx\njne 1774 \nmov %r9d,(%rdi)\nmov %r10d,0x4(%rdi)\nmov %edx,(%rbx)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nmov %rax,%rdi\nmov $0x1,%edx\nmov $0x1,%r10d\njmp 179b \n", + "ida_asm": "func0:\nendbr64\npush r13\nlea rcx, cmpfunc; compar\npush r12\nmov r12, rdi\npush rbp\nmovsxd rbp, esi\npush rbx\nmov rsi, rbp; nmemb\nmov rbx, rdx\nmov edx, 4; size\nsub rsp, 8\ncall _qsort\nlea rdi, ds:0[rbp*8]; size\ncall _malloc\nmov edx, [r12]\nmov r9, rax\ncmp ebp, 1\njle short loc_1728\nlea ecx, [rbp-2]\nlea rax, [r12+4]\nxor esi, esi\nmov edi, 1\nlea r10, [r12+rcx*4+8]\njmp short loc_16EF\nloc_16D0:\nmovsxd r8, esi\nadd rax, 4\nadd esi, 1\nlea r8, [r9+r8*8]\nmov [r8+4], edi\nmov edi, 1\nmov [r8], ecx\ncmp rax, r10\njz short loc_1703\nloc_16EF:\nmov ecx, edx\nmov edx, [rax]\ncmp edx, ecx\njnz short loc_16D0\nadd rax, 4\nadd edi, 1\ncmp rax, r10\njnz short loc_16EF\nloc_1703:\nmovsxd rax, esi\nadd esi, 1\nlea rax, [r9+rax*8]\nloc_170D:\nmov [rax], edx\nmov [rax+4], edi\nmov rax, r9\nmov [rbx], esi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1728:\nmov esi, 1\nmov edi, 1\njmp short loc_170D", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2, int *a3)\n{\n _DWORD *v6; // rax\n int v7; // edx\n _DWORD *v8; // r9\n int *v9; // rax\n int v10; // esi\n int v11; // edi\n __int64 v12; // r10\n __int64 v13; // r8\n _DWORD *v14; // r8\n int v15; // ecx\n __int64 v16; // rax\n int v17; // esi\n _DWORD *result; // rax\n\n qsort(a1, a2, 4uLL, cmpfunc);\n v6 = malloc(8LL * a2);\n v7 = *a1;\n v8 = v6;\n if ( a2 <= 1 )\n {\n v17 = 1;\n v11 = 1;\n }\n else\n {\n v9 = a1 + 1;\n v10 = 0;\n v11 = 1;\n v12 = (__int64)&a1[a2 - 2 + 2];\n do\n {\n while ( 1 )\n {\n v15 = v7;\n v7 = *v9;\n if ( *v9 == v15 )\n break;\n v13 = v10;\n ++v9;\n ++v10;\n v14 = &v8[2 * v13];\n v14[1] = v11;\n v11 = 1;\n *v14 = v15;\n if ( v9 == (int *)v12 )\n goto LABEL_6;\n }\n ++v9;\n ++v11;\n }\n while ( v9 != (int *)v12 );\nLABEL_6:\n v16 = v10;\n v17 = v10 + 1;\n v6 = &v8[2 * v16];\n }\n *v6 = v7;\n v6[1] = v11;\n result = v8;\n *a3 = v17;\n return result;\n}", + "ida_strip_asm": "sub_1670:\nendbr64\npush r13\nlea rcx, compar; compar\npush r12\nmov r12, rdi\npush rbp\nmovsxd rbp, esi\npush rbx\nmov rsi, rbp; nmemb\nmov rbx, rdx\nmov edx, 4; size\nsub rsp, 8\ncall _qsort\nlea rdi, ds:0[rbp*8]; size\ncall _malloc\nmov edx, [r12]\nmov r9, rax\ncmp ebp, 1\njle short loc_1728\nlea ecx, [rbp-2]\nlea rax, [r12+4]\nxor esi, esi\nmov edi, 1\nlea r10, [r12+rcx*4+8]\njmp short loc_16EF\nloc_16D0:\nmovsxd r8, esi\nadd rax, 4\nadd esi, 1\nlea r8, [r9+r8*8]\nmov [r8+4], edi\nmov edi, 1\nmov [r8], ecx\ncmp rax, r10\njz short loc_1703\nloc_16EF:\nmov ecx, edx\nmov edx, [rax]\ncmp edx, ecx\njnz short loc_16D0\nadd rax, 4\nadd edi, 1\ncmp rax, r10\njnz short loc_16EF\nloc_1703:\nmovsxd rax, esi\nadd esi, 1\nlea rax, [r9+rax*8]\nloc_170D:\nmov [rax], edx\nmov [rax+4], edi\nmov rax, r9\nmov [rbx], esi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1728:\nmov esi, 1\nmov edi, 1\njmp short loc_170D", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1670(int *a1, int a2, int *a3)\n{\n _DWORD *v6; // rax\n int v7; // edx\n _DWORD *v8; // r9\n int *v9; // rax\n int v10; // esi\n int v11; // edi\n __int64 v12; // r10\n __int64 v13; // r8\n _DWORD *v14; // r8\n int v15; // ecx\n __int64 v16; // rax\n int v17; // esi\n _DWORD *result; // rax\n\n qsort(a1, a2, 4uLL, compar);\n v6 = malloc(8LL * a2);\n v7 = *a1;\n v8 = v6;\n if ( a2 <= 1 )\n {\n v17 = 1;\n v11 = 1;\n }\n else\n {\n v9 = a1 + 1;\n v10 = 0;\n v11 = 1;\n v12 = (__int64)&a1[a2 - 2 + 2];\n do\n {\n while ( 1 )\n {\n v15 = v7;\n v7 = *v9;\n if ( *v9 == v15 )\n break;\n v13 = v10;\n ++v9;\n ++v10;\n v14 = &v8[2 * v13];\n v14[1] = v11;\n v11 = 1;\n *v14 = v15;\n if ( v9 == (int *)v12 )\n goto LABEL_6;\n }\n ++v9;\n ++v11;\n }\n while ( v9 != (int *)v12 );\nLABEL_6:\n v16 = v10;\n v17 = v10 + 1;\n v6 = &v8[2 * v16];\n }\n *v6 = v7;\n v6[1] = v11;\n result = v8;\n *a3 = v17;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1670(int *a1, int a2, int *a3) {\n uint32_t *v6;\n int v7;\n uint32_t *v8;\n int *v9;\n int v10;\n int v11;\n long long v12;\n long long v13;\n uint32_t *v14;\n int v15;\n long long v16;\n int v17;\n uint32_t *result;\n qsort(a1, a2, 4uLL, compar);\n v6 = malloc(8LL * a2);\n v7 = *a1;\n v8 = v6;\n if (a2 <= 1) {\n v17 = 1;\n v11 = 1;\n } else {\n v9 = a1 + 1;\n v10 = 0;\n v11 = 1;\n v12 = (long long)&a1[a2 - 2 + 2];\n do {\n while (1) {\n v15 = v7;\n v7 = *v9;\n if (*v9 == v15) break;\n v13 = v10;\n ++v9;\n ++v10;\n v14 = &v8[2 * v13];\n v14[1] = v11;\n v11 = 1;\n *v14 = v15;\n if (v9 == (int *)v12) goto LABEL_6;\n }\n ++v9;\n ++v11;\n } while (v9 != (int *)v12);\n LABEL_6:\n v16 = v10;\n v17 = v10 + 1;\n v6 = &v8[2 * v16];\n }\n *v6 = v7;\n v6[1] = v11;\n result = v8;\n *a3 = v17;\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2, int *a3) {\n uint32_t *v6;\n int v7;\n uint32_t *v8;\n int *v9;\n int v10;\n int v11;\n long long v12;\n long long v13;\n uint32_t *v14;\n int v15;\n long long v16;\n int v17;\n uint32_t *result;\n qsort(a1, a2, 4uLL, cmpfunc);\n v6 = malloc(8LL * a2);\n v7 = *a1;\n v8 = v6;\n if (a2 <= 1) {\n v17 = 1;\n v11 = 1;\n } else {\n v9 = a1 + 1;\n v10 = 0;\n v11 = 1;\n v12 = (long long)&a1[a2 - 2 + 2];\n do {\n while (1) {\n v15 = v7;\n v7 = *v9;\n if (*v9 == v15) break;\n v13 = v10;\n ++v9;\n ++v10;\n v14 = &v8[2 * v13];\n v14[1] = v11;\n v11 = 1;\n *v14 = v15;\n if (v9 == (int *)v12) goto LABEL_6;\n }\n ++v9;\n ++v11;\n } while (v9 != (int *)v12);\n LABEL_6:\n v16 = v10;\n v17 = v10 + 1;\n v6 = &v8[2 * v16];\n }\n *v6 = v7;\n v6[1] = v11;\n result = v8;\n *a3 = v17;\n return result;\n}" + }, + { + "index": 88, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int key;\n\n int value;\n\n} Pair;\n\n\n\nint cmpfunc(const void *a, const void *b) {\n\n return ((Pair *)a)->key - ((Pair *)b)->key;\n\n}\n\n\n\n", + "func": "Pair *func0(int arr[], int size, int *count) {\n qsort(arr, size, sizeof(int), cmpfunc);\n Pair *frequency = malloc(sizeof(Pair) * size);\n int current = arr[0];\n int freq = 1;\n int index = 0;\n for (int i = 1; i < size; i++) {\n if (arr[i] == current) {\n freq++;\n } else {\n frequency[index].key = current;\n frequency[index].value = freq;\n index++;\n current = arr[i];\n freq = 1;\n }\n }\n frequency[index].key = current;\n frequency[index].value = freq;\n index++;\n *count = index;\n return frequency;\n}", + "test": "int main() {\n\n int count1, count2, count3;\n\n \n\n int arr1[] = {10,10,10,10,20,20,20,20,40,40,50,50,30};\n\n Pair *result1 = func0(arr1, 13, &count1);\n\n assert(count1 == 5);\n\n assert(result1[0].key == 10 && result1[0].value == 4);\n\n assert(result1[1].key == 20 && result1[1].value == 4);\n\n assert(result1[2].key == 30 && result1[2].value == 1);\n\n assert(result1[3].key == 40 && result1[3].value == 2);\n\n assert(result1[4].key == 50 && result1[4].value == 2);\n\n free(result1);\n\n\n\n int arr2[] = {1,2,3,4,3,2,4,1,3,1,4};\n\n Pair *result2 = func0(arr2, 11, &count2);\n\n assert(count2 == 4);\n\n assert(result2[0].key == 1 && result2[0].value == 3);\n\n assert(result2[1].key == 2 && result2[1].value == 2);\n\n assert(result2[2].key == 3 && result2[2].value == 3);\n\n assert(result2[3].key == 4 && result2[3].value == 3);\n\n free(result2);\n\n\n\n int arr3[] = {5,6,7,4,9,10,4,5,6,7,9,5};\n\n Pair *result3 = func0(arr3, 12, &count3);\n\n assert(count3 == 6);\n\n assert(result3[0].key == 4 && result3[0].value == 2);\n\n assert(result3[1].key == 5 && result3[1].value == 3);\n\n assert(result3[2].key == 6 && result3[2].value == 2);\n\n assert(result3[3].key == 7 && result3[3].value == 2);\n\n assert(result3[4].key == 9 && result3[4].value == 2);\n\n assert(result3[5].key == 10 && result3[5].value == 1);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nlea -0x1d(%rip),%rcx\nmov %rdi,%r13\npush %r12\nmovslq %esi,%r12\npush %rbp\nmov %r12,%rsi\npush %rbx\nmov %rdx,%rbx\nmov $0x4,%edx\nsub $0x8,%rsp\ncallq 10a0 \nlea 0x0(,%r12,8),%rdi\ncallq 10d0 \nmov 0x0(%r13),%r9d\ncmp $0x1,%r12d\njle 1738 \nlea -0x2(%r12),%ecx\nlea 0x4(%r13),%rdx\nxor %r11d,%r11d\nxor %ebp,%ebp\nlea 0x8(%r13,%rcx,4),%r12\nmov $0x1,%r10d\nmov $0x1,%r8d\nnopl (%rax)\nmov (%rdx),%esi\nlea 0x0(,%rbp,8),%rdi\nlea (%rax,%rdi,1),%rcx\ncmp %r9d,%esi\nje 1720 \nadd $0x4,%rdx\nmov %r9d,(%rcx)\nadd $0x2,%r11d\nmov %r10d,0x4(%rcx)\nlea 0x8(%rax,%rdi,1),%rcx\ncmp %r12,%rdx\nje 1748 \nmov %r8d,%r11d\nmovslq %r8d,%rbp\nmov %esi,%r9d\nmov $0x1,%r10d\nadd $0x1,%r8d\njmp 16d8 \nnopl 0x0(%rax)\nadd $0x4,%rdx\nadd $0x1,%r10d\ncmp %r12,%rdx\njne 16d8 \nmov %r8d,%r11d\nmov %r9d,%esi\njmp 174e \nnopl (%rax)\nmov %rax,%rcx\nmov %r9d,%esi\nmov $0x1,%r11d\nnopl 0x0(%rax)\nmov $0x1,%r10d\nmov %esi,(%rcx)\nmov %r10d,0x4(%rcx)\nmov %r11d,(%rbx)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r13\nlea rcx, cmpfunc; compar\npush r12\nmov r12, rdi\npush rbp\nmovsxd rbp, esi\npush rbx\nmov rsi, rbp; nmemb\nmov rbx, rdx\nmov edx, 4; size\nsub rsp, 8\ncall _qsort\nlea rdi, ds:0[rbp*8]; size\ncall _malloc\nmov edx, [r12]\nmov r9, rax\ncmp ebp, 1\njle short loc_1728\nlea ecx, [rbp-2]\nlea rax, [r12+4]\nxor esi, esi\nmov edi, 1\nlea r10, [r12+rcx*4+8]\njmp short loc_16EF\nloc_16D0:\nmovsxd r8, esi\nadd rax, 4\nadd esi, 1\nlea r8, [r9+r8*8]\nmov [r8+4], edi\nmov edi, 1\nmov [r8], ecx\ncmp rax, r10\njz short loc_1703\nloc_16EF:\nmov ecx, edx\nmov edx, [rax]\ncmp edx, ecx\njnz short loc_16D0\nadd rax, 4\nadd edi, 1\ncmp rax, r10\njnz short loc_16EF\nloc_1703:\nmovsxd rax, esi\nadd esi, 1\nlea rax, [r9+rax*8]\nloc_170D:\nmov [rax], edx\nmov [rax+4], edi\nmov rax, r9\nmov [rbx], esi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1728:\nmov esi, 1\nmov edi, 1\njmp short loc_170D", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2, int *a3)\n{\n _DWORD *v6; // rax\n int v7; // edx\n _DWORD *v8; // r9\n int *v9; // rax\n int v10; // esi\n int v11; // edi\n __int64 v12; // r10\n __int64 v13; // r8\n _DWORD *v14; // r8\n int v15; // ecx\n __int64 v16; // rax\n int v17; // esi\n _DWORD *result; // rax\n\n qsort(a1, a2, 4uLL, cmpfunc);\n v6 = malloc(8LL * a2);\n v7 = *a1;\n v8 = v6;\n if ( a2 <= 1 )\n {\n v17 = 1;\n v11 = 1;\n }\n else\n {\n v9 = a1 + 1;\n v10 = 0;\n v11 = 1;\n v12 = (__int64)&a1[a2 - 2 + 2];\n do\n {\n while ( 1 )\n {\n v15 = v7;\n v7 = *v9;\n if ( *v9 == v15 )\n break;\n v13 = v10;\n ++v9;\n ++v10;\n v14 = &v8[2 * v13];\n v14[1] = v11;\n v11 = 1;\n *v14 = v15;\n if ( v9 == (int *)v12 )\n goto LABEL_6;\n }\n ++v9;\n ++v11;\n }\n while ( v9 != (int *)v12 );\nLABEL_6:\n v16 = v10;\n v17 = v10 + 1;\n v6 = &v8[2 * v16];\n }\n *v6 = v7;\n v6[1] = v11;\n result = v8;\n *a3 = v17;\n return result;\n}", + "ida_strip_asm": "sub_1670:\nendbr64\npush r13\nlea rcx, compar; compar\npush r12\nmov r12, rdi\npush rbp\nmovsxd rbp, esi\npush rbx\nmov rsi, rbp; nmemb\nmov rbx, rdx\nmov edx, 4; size\nsub rsp, 8\ncall _qsort\nlea rdi, ds:0[rbp*8]; size\ncall _malloc\nmov edx, [r12]\nmov r9, rax\ncmp ebp, 1\njle short loc_1728\nlea ecx, [rbp-2]\nlea rax, [r12+4]\nxor esi, esi\nmov edi, 1\nlea r10, [r12+rcx*4+8]\njmp short loc_16EF\nloc_16D0:\nmovsxd r8, esi\nadd rax, 4\nadd esi, 1\nlea r8, [r9+r8*8]\nmov [r8+4], edi\nmov edi, 1\nmov [r8], ecx\ncmp rax, r10\njz short loc_1703\nloc_16EF:\nmov ecx, edx\nmov edx, [rax]\ncmp edx, ecx\njnz short loc_16D0\nadd rax, 4\nadd edi, 1\ncmp rax, r10\njnz short loc_16EF\nloc_1703:\nmovsxd rax, esi\nadd esi, 1\nlea rax, [r9+rax*8]\nloc_170D:\nmov [rax], edx\nmov [rax+4], edi\nmov rax, r9\nmov [rbx], esi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1728:\nmov esi, 1\nmov edi, 1\njmp short loc_170D", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1670(int *a1, int a2, int *a3)\n{\n _DWORD *v6; // rax\n int v7; // edx\n _DWORD *v8; // r9\n int *v9; // rax\n int v10; // esi\n int v11; // edi\n __int64 v12; // r10\n __int64 v13; // r8\n _DWORD *v14; // r8\n int v15; // ecx\n __int64 v16; // rax\n int v17; // esi\n _DWORD *result; // rax\n\n qsort(a1, a2, 4uLL, compar);\n v6 = malloc(8LL * a2);\n v7 = *a1;\n v8 = v6;\n if ( a2 <= 1 )\n {\n v17 = 1;\n v11 = 1;\n }\n else\n {\n v9 = a1 + 1;\n v10 = 0;\n v11 = 1;\n v12 = (__int64)&a1[a2 - 2 + 2];\n do\n {\n while ( 1 )\n {\n v15 = v7;\n v7 = *v9;\n if ( *v9 == v15 )\n break;\n v13 = v10;\n ++v9;\n ++v10;\n v14 = &v8[2 * v13];\n v14[1] = v11;\n v11 = 1;\n *v14 = v15;\n if ( v9 == (int *)v12 )\n goto LABEL_6;\n }\n ++v9;\n ++v11;\n }\n while ( v9 != (int *)v12 );\nLABEL_6:\n v16 = v10;\n v17 = v10 + 1;\n v6 = &v8[2 * v16];\n }\n *v6 = v7;\n v6[1] = v11;\n result = v8;\n *a3 = v17;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1670(int *a1, int a2, int *a3) {\n uint32_t *v6;\n int v7;\n uint32_t *v8;\n int *v9;\n int v10;\n int v11;\n long long v12;\n long long v13;\n uint32_t *v14;\n int v15;\n long long v16;\n int v17;\n uint32_t *result;\n qsort(a1, a2, 4uLL, compar);\n v6 = malloc(8LL * a2);\n v7 = *a1;\n v8 = v6;\n if (a2 <= 1) {\n v17 = 1;\n v11 = 1;\n } else {\n v9 = a1 + 1;\n v10 = 0;\n v11 = 1;\n v12 = (long long)&a1[a2 - 2 + 2];\n do {\n while (1) {\n v15 = v7;\n v7 = *v9;\n if (*v9 == v15) break;\n v13 = v10;\n ++v9;\n ++v10;\n v14 = &v8[2 * v13];\n v14[1] = v11;\n v11 = 1;\n *v14 = v15;\n if (v9 == (int *)v12) goto LABEL_6;\n }\n ++v9;\n ++v11;\n } while (v9 != (int *)v12);\n LABEL_6:\n v16 = v10;\n v17 = v10 + 1;\n v6 = &v8[2 * v16];\n }\n *v6 = v7;\n v6[1] = v11;\n result = v8;\n *a3 = v17;\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2, int *a3) {\n uint32_t *v6;\n int v7;\n uint32_t *v8;\n int *v9;\n int v10;\n int v11;\n long long v12;\n long long v13;\n uint32_t *v14;\n int v15;\n long long v16;\n int v17;\n uint32_t *result;\n qsort(a1, a2, 4uLL, cmpfunc);\n v6 = malloc(8LL * a2);\n v7 = *a1;\n v8 = v6;\n if (a2 <= 1) {\n v17 = 1;\n v11 = 1;\n } else {\n v9 = a1 + 1;\n v10 = 0;\n v11 = 1;\n v12 = (long long)&a1[a2 - 2 + 2];\n do {\n while (1) {\n v15 = v7;\n v7 = *v9;\n if (*v9 == v15) break;\n v13 = v10;\n ++v9;\n ++v10;\n v14 = &v8[2 * v13];\n v14[1] = v11;\n v11 = 1;\n *v14 = v15;\n if (v9 == (int *)v12) goto LABEL_6;\n }\n ++v9;\n ++v11;\n } while (v9 != (int *)v12);\n LABEL_6:\n v16 = v10;\n v17 = v10 + 1;\n v6 = &v8[2 * v16];\n }\n *v6 = v7;\n v6[1] = v11;\n result = v8;\n *a3 = v17;\n return result;\n}" + }, + { + "index": 89, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int N) { return N - 1; }", + "test": "int main() {\n\n assert(func0(11) == 10);\n\n assert(func0(7) == 6);\n\n assert(func0(12) == 11);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nsub $0x1,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov eax, [rbp+var_4]\nsub eax, 1\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n return (unsigned int)(a1 - 1);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov eax, [rbp+var_4]\nsub eax, 1\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n return (unsigned int)(a1 - 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) { return (unsigned int)(a1 - 1); }", + "ida_pseudo_norm": "long long func0(int a1) { return (unsigned int)(a1 - 1); }" + }, + { + "index": 90, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(char *list1[], int num_elements) {\n int max = strlen(list1[0]);\n for (int i = 0; i < num_elements; i++) {\n if (strlen(list1[i]) > max) {\n max = strlen(list1[i]);\n }\n }\n return max;\n}", + "test": "int main() {\n\n char *list1[] = {\"python\", \"PHP\", \"bigdata\"};\n\n char *list2[] = {\"a\", \"ab\", \"abc\"};\n\n char *list3[] = {\"small\", \"big\", \"tall\"};\n\n\n\n assert(func0(list1, 3) == 7);\n\n assert(func0(list2, 3) == 3);\n\n assert(func0(list3, 3) == 5);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov -0x18(%rbp),%rax\nmov (%rax),%rax\nmov %rax,%rdi\ncallq 1070 \nmov %eax,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 1207 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov %rax,%rdi\ncallq 1070 \nmov -0x8(%rbp),%edx\nmovslq %edx,%rdx\ncmp %rdx,%rax\njbe 1203 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov %rax,%rdi\ncallq 1070 \nmov %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11b7 \nmov -0x8(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov rax, [rbp+var_18]\nmov rax, [rax]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_8], eax\nmov [rbp+var_4], 0\njmp short loc_1207\nloc_11B7:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; s\ncall _strlen\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\ncmp rdx, rax\njnb short loc_1203\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_8], eax\nloc_1203:\nadd [rbp+var_4], 1\nloc_1207:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11B7\nmov eax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char **a1, int a2)\n{\n unsigned int v3; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v3 = strlen(*a1);\n for ( i = 0; i < a2; ++i )\n {\n if ( (int)v3 < strlen(a1[i]) )\n v3 = strlen(a1[i]);\n }\n return v3;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov rax, [rbp+var_18]\nmov rax, [rax]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_8], eax\nmov [rbp+var_4], 0\njmp short loc_1207\nloc_11B7:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; s\ncall _strlen\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\ncmp rdx, rax\njnb short loc_1203\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_8], eax\nloc_1203:\nadd [rbp+var_4], 1\nloc_1207:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11B7\nmov eax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(const char **a1, int a2)\n{\n unsigned int v3; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v3 = strlen(*a1);\n for ( i = 0; i < a2; ++i )\n {\n if ( (int)v3 < strlen(a1[i]) )\n v3 = strlen(a1[i]);\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(const char **a1, int a2) {\n unsigned int v3;\n int i;\n v3 = strlen(*a1);\n for (i = 0; i < a2; ++i) {\n if ((int)v3 < strlen(a1[i])) v3 = strlen(a1[i]);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(const char **a1, int a2) {\n unsigned int v3;\n int i;\n v3 = strlen(*a1);\n for (i = 0; i < a2; ++i) {\n if ((int)v3 < strlen(a1[i])) v3 = strlen(a1[i]);\n }\n return v3;\n}" + }, + { + "index": 90, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(char *list1[], int num_elements) {\n int max = strlen(list1[0]);\n for (int i = 0; i < num_elements; i++) {\n if (strlen(list1[i]) > max) {\n max = strlen(list1[i]);\n }\n }\n return max;\n}", + "test": "int main() {\n\n char *list1[] = {\"python\", \"PHP\", \"bigdata\"};\n\n char *list2[] = {\"a\", \"ab\", \"abc\"};\n\n char *list3[] = {\"small\", \"big\", \"tall\"};\n\n\n\n assert(func0(list1, 3) == 7);\n\n assert(func0(list2, 3) == 3);\n\n assert(func0(list3, 3) == 5);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%r9\nmov (%rdi),%rdi\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nlea -0x1(%rcx),%r8d\ntest %esi,%esi\njle 11c5 \nmov %r9,%rdx\nlea -0x1(%rsi),%eax\nlea 0x8(%r9,%rax,8),%r10\nmov $0xffffffffffffffff,%r9\nmov $0x0,%eax\nmov (%rdx),%rdi\nmov %r9,%rcx\nrepnz scas %es:(%rdi),%al\nnot %rcx\nsub $0x1,%rcx\nmovslq %r8d,%rsi\ncmp %rsi,%rcx\ncmova %ecx,%r8d\nadd $0x8,%rdx\ncmp %r10,%rdx\njne 11a3 \nmov %r8d,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r13, rdi\nmov r12d, esi\nmov rdi, [rdi]; s\ncall _strlen\nmov ebp, eax\ntest r12d, r12d\njle short loc_11D1\nmov rbx, r13\nmovsxd r12, r12d\nlea r12, [r13+r12*8+0]\nloc_11B7:\nmov rdi, [rbx]; s\ncall _strlen\nmovsxd rdx, ebp\ncmp rdx, rax\ncmovb ebp, eax\nadd rbx, 8\ncmp rbx, r12\njnz short loc_11B7\nloc_11D1:\nmov eax, ebp\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char **a1, int a2)\n{\n unsigned int v2; // ebp\n const char **v3; // rbx\n size_t v4; // rax\n\n v2 = strlen(*a1);\n if ( a2 > 0 )\n {\n v3 = a1;\n do\n {\n v4 = strlen(*v3);\n if ( (int)v2 < v4 )\n v2 = v4;\n ++v3;\n }\n while ( v3 != &a1[a2] );\n }\n return v2;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r13, rdi\nmov r12d, esi\nmov rdi, [rdi]; s\ncall _strlen\nmov ebp, eax\ntest r12d, r12d\njle short loc_11D1\nmov rbx, r13\nmovsxd r12, r12d\nlea r12, [r13+r12*8+0]\nloc_11B7:\nmov rdi, [rbx]; s\ncall _strlen\nmovsxd rdx, ebp\ncmp rdx, rax\ncmovb ebp, eax\nadd rbx, 8\ncmp rbx, r12\njnz short loc_11B7\nloc_11D1:\nmov eax, ebp\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(const char **a1, int a2)\n{\n unsigned int v2; // ebp\n const char **v3; // rbx\n size_t v4; // rax\n\n v2 = strlen(*a1);\n if ( a2 > 0 )\n {\n v3 = a1;\n do\n {\n v4 = strlen(*v3);\n if ( (int)v2 < v4 )\n v2 = v4;\n ++v3;\n }\n while ( v3 != &a1[a2] );\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(const char **a1, int a2) {\n unsigned int v2;\n const char **v3;\n unsigned int v4;\n v2 = strlen(*a1);\n if (a2 > 0) {\n v3 = a1;\n do {\n v4 = strlen(*v3);\n if ((int)v2 < v4) v2 = v4;\n ++v3;\n } while (v3 != &a1[a2]);\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(const char **a1, int a2) {\n unsigned int v2;\n const char **v3;\n unsigned int v4;\n v2 = strlen(*a1);\n if (a2 > 0) {\n v3 = a1;\n do {\n v4 = strlen(*v3);\n if ((int)v2 < v4) v2 = v4;\n ++v3;\n } while (v3 != &a1[a2]);\n }\n return v2;\n}" + }, + { + "index": 90, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(char *list1[], int num_elements) {\n int max = strlen(list1[0]);\n for (int i = 0; i < num_elements; i++) {\n if (strlen(list1[i]) > max) {\n max = strlen(list1[i]);\n }\n }\n return max;\n}", + "test": "int main() {\n\n char *list1[] = {\"python\", \"PHP\", \"bigdata\"};\n\n char *list2[] = {\"a\", \"ab\", \"abc\"};\n\n char *list3[] = {\"small\", \"big\", \"tall\"};\n\n\n\n assert(func0(list1, 3) == 7);\n\n assert(func0(list2, 3) == 3);\n\n assert(func0(list3, 3) == 5);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\nmov %esi,%ebp\npush %rbx\nmov %rdi,%rbx\nmov (%rdi),%rdi\ncallq 1070 \nmov %eax,%r12d\ntest %ebp,%ebp\njle 131b \nadd $0x8,%rbx\nlea -0x1(%rbp),%edx\nlea (%rbx,%rdx,8),%rbp\njmp 130c \nnopl 0x0(%rax)\nmov (%rbx),%rdi\nadd $0x8,%rbx\ncallq 1070 \nmovslq %r12d,%rdx\ncmp %rax,%rdx\ncmovb %eax,%r12d\ncmp %rbp,%rbx\njne 1300 \nmov %r12d,%eax\npop %rbx\npop %rbp\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r12\nmovsxd r12, esi\npush rbp\npush rbx\nmov rbx, rdi\nmov rdi, [rdi]; s\ncall _strlen\nmov ebp, eax\ntest r12d, r12d\njle short loc_1322\nlea r12, [rbx+r12*8]\njmp short loc_1310\nloc_1308:\nmov rdi, [rbx]; s\ncall _strlen\nloc_1310:\nmovsxd rdx, ebp\ncmp rdx, rax\ncmovb ebp, eax\nadd rbx, 8\ncmp rbx, r12\njnz short loc_1308\nloc_1322:\nmov eax, ebp\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char **a1, int a2)\n{\n const char **v2; // rbx\n size_t v3; // rax\n unsigned int v4; // ebp\n\n v2 = a1;\n v3 = strlen(*a1);\n v4 = v3;\n if ( a2 > 0 )\n {\n while ( 1 )\n {\n if ( (int)v4 < v3 )\n v4 = v3;\n if ( ++v2 == &a1[a2] )\n break;\n v3 = strlen(*v2);\n }\n }\n return v4;\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\npush r12\nmovsxd r12, esi\npush rbp\npush rbx\nmov rbx, rdi\nmov rdi, [rdi]; s\ncall _strlen\nmov ebp, eax\ntest r12d, r12d\njle short loc_1322\nlea r12, [rbx+r12*8]\njmp short loc_1310\nloc_1308:\nmov rdi, [rbx]; s\ncall _strlen\nloc_1310:\nmovsxd rdx, ebp\ncmp rdx, rax\ncmovb ebp, eax\nadd rbx, 8\ncmp rbx, r12\njnz short loc_1308\nloc_1322:\nmov eax, ebp\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12E0(const char **a1, int a2)\n{\n const char **v2; // rbx\n size_t v3; // rax\n unsigned int v4; // ebp\n\n v2 = a1;\n v3 = strlen(*a1);\n v4 = v3;\n if ( a2 > 0 )\n {\n while ( 1 )\n {\n if ( (int)v4 < v3 )\n v4 = v3;\n if ( ++v2 == &a1[a2] )\n break;\n v3 = strlen(*v2);\n }\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12E0(const char **a1, int a2) {\n const char **v2;\n unsigned int v3;\n unsigned int v4;\n v2 = a1;\n v3 = strlen(*a1);\n v4 = v3;\n if (a2 > 0) {\n while (1) {\n if ((int)v4 < v3) v4 = v3;\n if (++v2 == &a1[a2]) break;\n v3 = strlen(*v2);\n }\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(const char **a1, int a2) {\n const char **v2;\n unsigned int v3;\n unsigned int v4;\n v2 = a1;\n v3 = strlen(*a1);\n v4 = v3;\n if (a2 > 0) {\n while (1) {\n if ((int)v4 < v3) v4 = v3;\n if (++v2 == &a1[a2]) break;\n v3 = strlen(*v2);\n }\n }\n return v4;\n}" + }, + { + "index": 90, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(char *list1[], int num_elements) {\n int max = strlen(list1[0]);\n for (int i = 0; i < num_elements; i++) {\n if (strlen(list1[i]) > max) {\n max = strlen(list1[i]);\n }\n }\n return max;\n}", + "test": "int main() {\n\n char *list1[] = {\"python\", \"PHP\", \"bigdata\"};\n\n char *list2[] = {\"a\", \"ab\", \"abc\"};\n\n char *list3[] = {\"small\", \"big\", \"tall\"};\n\n\n\n assert(func0(list1, 3) == 7);\n\n assert(func0(list2, 3) == 3);\n\n assert(func0(list3, 3) == 5);\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\nmov %esi,%ebp\npush %rbx\nmov %rdi,%rbx\nmov (%rdi),%rdi\ncallq 1070 \nmov %eax,%r12d\ntest %ebp,%ebp\njle 133b \nadd $0x8,%rbx\nlea -0x1(%rbp),%edx\nlea (%rbx,%rdx,8),%rbp\njmp 132c \nnopl 0x0(%rax)\nmov (%rbx),%rdi\nadd $0x8,%rbx\ncallq 1070 \nmovslq %r12d,%rdx\ncmp %rax,%rdx\ncmovb %eax,%r12d\ncmp %rbp,%rbx\njne 1320 \nmov %r12d,%eax\npop %rbx\npop %rbp\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r12\nmovsxd r12, esi\npush rbp\npush rbx\nmov rbx, rdi\nmov rdi, [rdi]; s\ncall _strlen\nmov ebp, eax\ntest r12d, r12d\njle short loc_1322\nlea r12, [rbx+r12*8]\njmp short loc_1310\nloc_1308:\nmov rdi, [rbx]; s\ncall _strlen\nloc_1310:\nmovsxd rdx, ebp\ncmp rdx, rax\ncmovb ebp, eax\nadd rbx, 8\ncmp rbx, r12\njnz short loc_1308\nloc_1322:\nmov eax, ebp\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char **a1, int a2)\n{\n const char **v2; // rbx\n size_t v3; // rax\n unsigned int v4; // ebp\n\n v2 = a1;\n v3 = strlen(*a1);\n v4 = v3;\n if ( a2 > 0 )\n {\n while ( 1 )\n {\n if ( (int)v4 < v3 )\n v4 = v3;\n if ( ++v2 == &a1[a2] )\n break;\n v3 = strlen(*v2);\n }\n }\n return v4;\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\npush r12\nmovsxd r12, esi\npush rbp\npush rbx\nmov rbx, rdi\nmov rdi, [rdi]; s\ncall _strlen\nmov ebp, eax\ntest r12d, r12d\njle short loc_1322\nlea r12, [rbx+r12*8]\njmp short loc_1310\nloc_1308:\nmov rdi, [rbx]; s\ncall _strlen\nloc_1310:\nmovsxd rdx, ebp\ncmp rdx, rax\ncmovb ebp, eax\nadd rbx, 8\ncmp rbx, r12\njnz short loc_1308\nloc_1322:\nmov eax, ebp\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12E0(const char **a1, int a2)\n{\n const char **v2; // rbx\n size_t v3; // rax\n unsigned int v4; // ebp\n\n v2 = a1;\n v3 = strlen(*a1);\n v4 = v3;\n if ( a2 > 0 )\n {\n while ( 1 )\n {\n if ( (int)v4 < v3 )\n v4 = v3;\n if ( ++v2 == &a1[a2] )\n break;\n v3 = strlen(*v2);\n }\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12E0(const char **a1, int a2) {\n const char **v2;\n unsigned int v3;\n unsigned int v4;\n v2 = a1;\n v3 = strlen(*a1);\n v4 = v3;\n if (a2 > 0) {\n while (1) {\n if ((int)v4 < v3) v4 = v3;\n if (++v2 == &a1[a2]) break;\n v3 = strlen(*v2);\n }\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(const char **a1, int a2) {\n const char **v2;\n unsigned int v3;\n unsigned int v4;\n v2 = a1;\n v3 = strlen(*a1);\n v4 = v3;\n if (a2 > 0) {\n while (1) {\n if ((int)v4 < v3) v4 = v3;\n if (++v2 == &a1[a2]) break;\n v3 = strlen(*v2);\n }\n }\n return v4;\n}" + }, + { + "index": 91, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(char *str1[], char *sub_str, int size) {\n for (int i = 0; i < size; i++) {\n if (strstr(str1[i], sub_str) != NULL) {\n return true;\n }\n }\n return false;\n}", + "test": "int main() {\n\n char *array[] = {\"red\", \"black\", \"white\", \"green\", \"orange\"};\n\n int size = sizeof(array) / sizeof(array[0]);\n\n\n\n assert(func0(array, \"ack\", size) == true);\n\n assert(func0(array, \"abc\", size) == false);\n\n assert(func0(array, \"ange\", size) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %edx,-0x24(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11df \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0x20(%rbp),%rdx\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1090 \ntest %rax,%rax\nje 11db \nmov $0x1,%eax\njmp 11ec \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x24(%rbp),%eax\njl 11a9 \nmov $0x0,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+needle], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_4], 0\njmp short loc_11DF\nloc_11A9:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov rdx, [rbp+needle]\nmov rsi, rdx; needle\nmov rdi, rax; haystack\ncall _strstr\ntest rax, rax\njz short loc_11DB\nmov eax, 1\njmp short locret_11EC\nloc_11DB:\nadd [rbp+var_4], 1\nloc_11DF:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_24]\njl short loc_11A9\nmov eax, 0\nlocret_11EC:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, const char *a2, int a3)\n{\n int i; // [rsp+2Ch] [rbp-4h]\n\n for ( i = 0; i < a3; ++i )\n {\n if ( strstr(*(const char **)(8LL * i + a1), a2) )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+needle], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_4], 0\njmp short loc_11DF\nloc_11A9:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov rdx, [rbp+needle]\nmov rsi, rdx; needle\nmov rdi, rax; haystack\ncall _strstr\ntest rax, rax\njz short loc_11DB\nmov eax, 1\njmp short locret_11EC\nloc_11DB:\nadd [rbp+var_4], 1\nloc_11DF:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_24]\njl short loc_11A9\nmov eax, 0\nlocret_11EC:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, const char *a2, int a3)\n{\n int i; // [rsp+2Ch] [rbp-4h]\n\n for ( i = 0; i < a3; ++i )\n {\n if ( strstr(*(const char **)(8LL * i + a1), a2) )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, const char *a2, int a3) {\n int i;\n for (i = 0; i < a3; ++i) {\n if (strstr(*(const char **)(8LL * i + a1), a2)) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, const char *a2, int a3) {\n int i;\n for (i = 0; i < a3; ++i) {\n if (strstr(*(const char **)(8LL * i + a1), a2)) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 91, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(char *str1[], char *sub_str, int size) {\n for (int i = 0; i < size; i++) {\n if (strstr(str1[i], sub_str) != NULL) {\n return true;\n }\n }\n return false;\n}", + "test": "int main() {\n\n char *array[] = {\"red\", \"black\", \"white\", \"green\", \"orange\"};\n\n int size = sizeof(array) / sizeof(array[0]);\n\n\n\n assert(func0(array, \"ack\", size) == true);\n\n assert(func0(array, \"abc\", size) == false);\n\n assert(func0(array, \"ange\", size) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edx,%edx\njle 11be \npush %r12\npush %rbp\npush %rbx\nmov %rsi,%rbp\nmov %rdi,%rbx\nlea -0x1(%rdx),%eax\nlea 0x8(%rdi,%rax,8),%r12\nmov %rbp,%rsi\nmov (%rbx),%rdi\ncallq 1090 \ntest %rax,%rax\njne 11c4 \nadd $0x8,%rbx\ncmp %r12,%rbx\njne 11a3 \njmp 11c9 \nmov $0x0,%eax\nretq\nmov $0x1,%eax\npop %rbx\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\ntest edx, edx\njle short loc_11BD\npush r12\npush rbp\npush rbx\nmov rbp, rsi\nmov rbx, rdi\nmovsxd rdx, edx\nlea r12, [rdi+rdx*8]\nloc_11A2:\nmov rdi, [rbx]; haystack\nmov rsi, rbp; needle\ncall _strstr\ntest rax, rax\njnz short loc_11C3\nadd rbx, 8\ncmp rbx, r12\njnz short loc_11A2\njmp short loc_11C8\nloc_11BD:\nmov eax, 0\nretn\nloc_11C3:\nmov eax, 1\nloc_11C8:\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "char *__fastcall func0(const char **a1, const char *a2, int a3)\n{\n const char **v3; // rbx\n const char **v4; // r12\n char *result; // rax\n\n if ( a3 <= 0 )\n return 0LL;\n v3 = a1;\n v4 = &a1[a3];\n while ( 1 )\n {\n result = strstr(*v3, a2);\n if ( result )\n break;\n if ( ++v3 == v4 )\n return result;\n }\n return (_BYTE *)(&dword_0 + 1);\n}", + "ida_strip_asm": "sub_1189:\nendbr64\ntest edx, edx\njle short loc_11BD\npush r12\npush rbp\npush rbx\nmov rbp, rsi\nmov rbx, rdi\nmovsxd rdx, edx\nlea r12, [rdi+rdx*8]\nloc_11A2:\nmov rdi, [rbx]; haystack\nmov rsi, rbp; needle\ncall _strstr\ntest rax, rax\njnz short loc_11C3\nadd rbx, 8\ncmp rbx, r12\njnz short loc_11A2\njmp short loc_11C8\nloc_11BD:\nmov eax, 0\nretn\nloc_11C3:\nmov eax, 1\nloc_11C8:\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1189(const char **a1, const char *a2, int a3)\n{\n const char **v3; // rbx\n const char **v4; // r12\n char *result; // rax\n\n if ( a3 <= 0 )\n return 0LL;\n v3 = a1;\n v4 = &a1[a3];\n while ( 1 )\n {\n result = strstr(*v3, a2);\n if ( result )\n break;\n if ( ++v3 == v4 )\n return result;\n }\n return (_BYTE *)(&dword_0 + 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1189(const char **a1, const char *a2, int a3) {\n const char **v3;\n const char **v4;\n char *result;\n if (a3 <= 0) return 0LL;\n v3 = a1;\n v4 = &a1[a3];\n while (1) {\n result = strstr(*v3, a2);\n if (result) break;\n if (++v3 == v4) return result;\n }\n return (uint8_t *)(&dword_0 + 1);\n}", + "ida_pseudo_norm": "char *func0(const char **a1, const char *a2, int a3) {\n const char **v3;\n const char **v4;\n char *result;\n if (a3 <= 0) return 0LL;\n v3 = a1;\n v4 = &a1[a3];\n while (1) {\n result = strstr(*v3, a2);\n if (result) break;\n if (++v3 == v4) return result;\n }\n return (uint8_t *)(&dword_0 + 1);\n}" + }, + { + "index": 91, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(char *str1[], char *sub_str, int size) {\n for (int i = 0; i < size; i++) {\n if (strstr(str1[i], sub_str) != NULL) {\n return true;\n }\n }\n return false;\n}", + "test": "int main() {\n\n char *array[] = {\"red\", \"black\", \"white\", \"green\", \"orange\"};\n\n int size = sizeof(array) / sizeof(array[0]);\n\n\n\n assert(func0(array, \"ack\", size) == true);\n\n assert(func0(array, \"abc\", size) == false);\n\n assert(func0(array, \"ange\", size) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %edx,%edx\njle 1333 \nlea -0x1(%rdx),%eax\npush %r12\nlea 0x8(%rdi,%rax,8),%r12\npush %rbp\nmov %rsi,%rbp\npush %rbx\nmov %rdi,%rbx\njmp 1319 \nnopl 0x0(%rax)\nadd $0x8,%rbx\ncmp %r12,%rbx\nje 132e \nmov (%rbx),%rdi\nmov %rbp,%rsi\ncallq 1090 \ntest %rax,%rax\nje 1310 \nmov $0x1,%eax\npop %rbx\npop %rbp\npop %r12\nretq\nxor %eax,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest edx, edx\njle short loc_1303\nmovsxd rdx, edx\npush r12\nlea r12, [rdi+rdx*8]\npush rbp\nmov rbp, rsi\npush rbx\nmov rbx, rdi\njmp short loc_12E9\nloc_12E0:\nadd rbx, 8\ncmp rbx, r12\njz short loc_12FE\nloc_12E9:\nmov rdi, [rbx]; haystack\nmov rsi, rbp; needle\ncall _strstr\ntest rax, rax\njz short loc_12E0\nmov eax, 1\nloc_12FE:\npop rbx\npop rbp\npop r12\nretn\nloc_1303:\nxor eax, eax\nretn", + "ida_pseudo": "char *__fastcall func0(const char **a1, const char *a2, int a3)\n{\n const char **v3; // r12\n const char **v4; // rbx\n char *result; // rax\n\n if ( a3 <= 0 )\n return 0LL;\n v3 = &a1[a3];\n v4 = a1;\n while ( 1 )\n {\n result = strstr(*v4, a2);\n if ( result )\n break;\n if ( ++v4 == v3 )\n return result;\n }\n return (_BYTE *)(&dword_0 + 1);\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\ntest edx, edx\njle short loc_1303\nmovsxd rdx, edx\npush r12\nlea r12, [rdi+rdx*8]\npush rbp\nmov rbp, rsi\npush rbx\nmov rbx, rdi\njmp short loc_12E9\nloc_12E0:\nadd rbx, 8\ncmp rbx, r12\njz short loc_12FE\nloc_12E9:\nmov rdi, [rbx]; haystack\nmov rsi, rbp; needle\ncall _strstr\ntest rax, rax\njz short loc_12E0\nmov eax, 1\nloc_12FE:\npop rbx\npop rbp\npop r12\nretn\nloc_1303:\nxor eax, eax\nretn", + "ida_strip_pseudo": "char *__fastcall sub_12C0(const char **a1, const char *a2, int a3)\n{\n const char **v3; // r12\n const char **v4; // rbx\n char *result; // rax\n\n if ( a3 <= 0 )\n return 0LL;\n v3 = &a1[a3];\n v4 = a1;\n while ( 1 )\n {\n result = strstr(*v4, a2);\n if ( result )\n break;\n if ( ++v4 == v3 )\n return result;\n }\n return (_BYTE *)(&dword_0 + 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_12C0(const char **a1, const char *a2, int a3) {\n const char **v3;\n const char **v4;\n char *result;\n if (a3 <= 0) return 0LL;\n v3 = &a1[a3];\n v4 = a1;\n while (1) {\n result = strstr(*v4, a2);\n if (result) break;\n if (++v4 == v3) return result;\n }\n return (uint8_t *)(&dword_0 + 1);\n}", + "ida_pseudo_norm": "char *func0(const char **a1, const char *a2, int a3) {\n const char **v3;\n const char **v4;\n char *result;\n if (a3 <= 0) return 0LL;\n v3 = &a1[a3];\n v4 = a1;\n while (1) {\n result = strstr(*v4, a2);\n if (result) break;\n if (++v4 == v3) return result;\n }\n return (uint8_t *)(&dword_0 + 1);\n}" + }, + { + "index": 92, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char *n) {\n int length = strlen(n);\n if (length <= 2) {\n return false;\n }\n for (int i = 2; i < length; i++) {\n if (n[i - 2] != n[i]) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n assert(func0(\"1212121\") == true);\n\n assert(func0(\"1991\") == false);\n\n assert(func0(\"121\") == true);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov -0x18(%rbp),%rax\nmov %rax,%rdi\ncallq 1060 \nmov %eax,-0x4(%rbp)\ncmpl $0x2,-0x4(%rbp)\njg 1195 \nmov $0x0,%eax\njmp 11dd \nmovl $0x2,-0x8(%rbp)\njmp 11d0 \nmov -0x8(%rbp),%eax\ncltq\nlea -0x2(%rax),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%edx\nmov -0x8(%rbp),%eax\nmovslq %eax,%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmovzbl (%rax),%eax\ncmp %al,%dl\nje 11cc \nmov $0x0,%eax\njmp 11dd \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x4(%rbp),%eax\njl 119e \nmov $0x1,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\ncmp [rbp+var_4], 2\njg short loc_1195\nmov eax, 0\njmp short locret_11DD\nloc_1195:\nmov [rbp+var_8], 2\njmp short loc_11D0\nloc_119E:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, [rax-2]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_8]\nmovsxd rcx, eax\nmov rax, [rbp+s]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njz short loc_11CC\nmov eax, 0\njmp short locret_11DD\nloc_11CC:\nadd [rbp+var_8], 1\nloc_11D0:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njl short loc_119E\nmov eax, 1\nlocret_11DD:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int i; // [rsp+18h] [rbp-8h]\n int v3; // [rsp+1Ch] [rbp-4h]\n\n v3 = strlen(a1);\n if ( v3 <= 2 )\n return 0LL;\n for ( i = 2; i < v3; ++i )\n {\n if ( a1[i - 2] != a1[i] )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\ncmp [rbp+var_4], 2\njg short loc_1195\nmov eax, 0\njmp short locret_11DD\nloc_1195:\nmov [rbp+var_8], 2\njmp short loc_11D0\nloc_119E:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, [rax-2]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_8]\nmovsxd rcx, eax\nmov rax, [rbp+s]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njz short loc_11CC\nmov eax, 0\njmp short locret_11DD\nloc_11CC:\nadd [rbp+var_8], 1\nloc_11D0:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njl short loc_119E\nmov eax, 1\nlocret_11DD:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1)\n{\n int i; // [rsp+18h] [rbp-8h]\n int v3; // [rsp+1Ch] [rbp-4h]\n\n v3 = strlen(a1);\n if ( v3 <= 2 )\n return 0LL;\n for ( i = 2; i < v3; ++i )\n {\n if ( a1[i - 2] != a1[i] )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1) {\n int i;\n int v3;\n v3 = strlen(a1);\n if (v3 <= 2) return 0LL;\n for (i = 2; i < v3; ++i) {\n if (a1[i - 2] != a1[i]) return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int i;\n int v3;\n v3 = strlen(a1);\n if (v3 <= 2) return 0LL;\n for (i = 2; i < v3; ++i) {\n if (a1[i - 2] != a1[i]) return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": 92, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char *n) {\n int length = strlen(n);\n if (length <= 2) {\n return false;\n }\n for (int i = 2; i < length; i++) {\n if (n[i - 2] != n[i]) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n assert(func0(\"1212121\") == true);\n\n assert(func0(\"1991\") == false);\n\n assert(func0(\"121\") == true);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%rdx\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nsub $0x1,%rcx\ncmp $0x2,%ecx\njle 1192 \nmov %rdx,%rax\nlea -0x3(%rcx),%ecx\nlea 0x1(%rdx,%rcx,1),%rdx\nmovzbl 0x2(%rax),%esi\ncmp %sil,(%rax)\njne 118d \nadd $0x1,%rax\ncmp %rdx,%rax\njne 1175 \nmov $0x1,%eax\nretq\nmov $0x0,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmov edx, 0\ncmp eax, 2\njle short loc_11A8\nmov rdx, rbx\nlea eax, [rax-3]\nlea rax, [rbx+rax+1]\nloc_118B:\nmovzx ecx, byte ptr [rdx+2]\ncmp [rdx], cl\njnz short loc_11A3\nadd rdx, 1\ncmp rdx, rax\njnz short loc_118B\nmov edx, 1\njmp short loc_11A8\nloc_11A3:\nmov edx, 0\nloc_11A8:\nmov eax, edx\npop rbx\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v1; // eax\n unsigned int v2; // edx\n const char *v3; // rdx\n __int64 v4; // rax\n\n v1 = strlen(a1);\n v2 = 0;\n if ( v1 > 2 )\n {\n v3 = a1;\n v4 = (__int64)&a1[v1 - 3 + 1];\n while ( *v3 == v3[2] )\n {\n if ( ++v3 == (const char *)v4 )\n return 1;\n }\n return 0;\n }\n return v2;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmov edx, 0\ncmp eax, 2\njle short loc_11A8\nmov rdx, rbx\nlea eax, [rax-3]\nlea rax, [rbx+rax+1]\nloc_118B:\nmovzx ecx, byte ptr [rdx+2]\ncmp [rdx], cl\njnz short loc_11A3\nadd rdx, 1\ncmp rdx, rax\njnz short loc_118B\nmov edx, 1\njmp short loc_11A8\nloc_11A3:\nmov edx, 0\nloc_11A8:\nmov eax, edx\npop rbx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1)\n{\n int v1; // eax\n unsigned int v2; // edx\n const char *v3; // rdx\n __int64 v4; // rax\n\n v1 = strlen(a1);\n v2 = 0;\n if ( v1 > 2 )\n {\n v3 = a1;\n v4 = (__int64)&a1[v1 - 3 + 1];\n while ( *v3 == v3[2] )\n {\n if ( ++v3 == (const char *)v4 )\n return 1;\n }\n return 0;\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1) {\n int v1;\n unsigned int v2;\n const char *v3;\n long long v4;\n v1 = strlen(a1);\n v2 = 0;\n if (v1 > 2) {\n v3 = a1;\n v4 = (long long)&a1[v1 - 3 + 1];\n while (*v3 == v3[2]) {\n if (++v3 == (const char *)v4) return 1;\n }\n return 0;\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v1;\n unsigned int v2;\n const char *v3;\n long long v4;\n v1 = strlen(a1);\n v2 = 0;\n if (v1 > 2) {\n v3 = a1;\n v4 = (long long)&a1[v1 - 3 + 1];\n while (*v3 == v3[2]) {\n if (++v3 == (const char *)v4) return 1;\n }\n return 0;\n }\n return v2;\n}" + }, + { + "index": 92, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char *n) {\n int length = strlen(n);\n if (length <= 2) {\n return false;\n }\n for (int i = 2; i < length; i++) {\n if (n[i - 2] != n[i]) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n assert(func0(\"1212121\") == true);\n\n assert(func0(\"1991\") == false);\n\n assert(func0(\"121\") == true);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\ncallq 1060 \nxor %r8d,%r8d\ncmp $0x2,%eax\njle 1247 \nsub $0x3,%eax\nmov %rbx,%rdi\nlea 0x1(%rbx,%rax,1),%rax\nmovzbl 0x2(%rdi),%edx\ncmp %dl,(%rdi)\njne 1250 \nadd $0x1,%rdi\ncmp %rax,%rdi\njne 1230 \nmov $0x1,%r8d\nmov %r8d,%eax\npop %rbx\nretq\nnopl 0x0(%rax)\nxor %r8d,%r8d\npop %rbx\nmov %r8d,%eax\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nxor edx, edx\ncmp eax, 2\njle short loc_1257\nsub eax, 3\nmovzx esi, byte ptr [rbx]\nmovzx ecx, byte ptr [rbx+1]\nlea rdx, [rbx+2]\nlea rdi, [rbx+rax+3]\njmp short loc_124B\nloc_1240:\nadd rdx, 1\nmov esi, eax\ncmp rdx, rdi\njz short loc_1260\nloc_124B:\nmov eax, ecx\nmovzx ecx, byte ptr [rdx]\ncmp cl, sil\njz short loc_1240\nxor edx, edx\nloc_1257:\nmov eax, edx\npop rbx\nretn\nloc_1260:\nmov edx, 1\npop rbx\nmov eax, edx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1)\n{\n int v1; // eax\n char v2; // si\n char v3; // cl\n char *v4; // rdx\n __int64 v5; // rdi\n char v6; // al\n\n v1 = strlen((const char *)a1);\n if ( v1 > 2 )\n {\n v2 = *(_BYTE *)a1;\n v3 = *(_BYTE *)(a1 + 1);\n v4 = (char *)(a1 + 2);\n v5 = a1 + (unsigned int)(v1 - 3) + 3;\n while ( 1 )\n {\n v6 = v3;\n v3 = *v4;\n if ( *v4 != v2 )\n break;\n ++v4;\n v2 = v6;\n if ( v4 == (char *)v5 )\n return 1LL;\n }\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nxor edx, edx\ncmp eax, 2\njle short loc_1257\nsub eax, 3\nmovzx esi, byte ptr [rbx]\nmovzx ecx, byte ptr [rbx+1]\nlea rdx, [rbx+2]\nlea rdi, [rbx+rax+3]\njmp short loc_124B\nloc_1240:\nadd rdx, 1\nmov esi, eax\ncmp rdx, rdi\njz short loc_1260\nloc_124B:\nmov eax, ecx\nmovzx ecx, byte ptr [rdx]\ncmp cl, sil\njz short loc_1240\nxor edx, edx\nloc_1257:\nmov eax, edx\npop rbx\nretn\nloc_1260:\nmov edx, 1\npop rbx\nmov eax, edx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(__int64 a1)\n{\n int v1; // eax\n char v2; // si\n char v3; // cl\n char *v4; // rdx\n __int64 v5; // rdi\n char v6; // al\n\n v1 = strlen((const char *)a1);\n if ( v1 > 2 )\n {\n v2 = *(_BYTE *)a1;\n v3 = *(_BYTE *)(a1 + 1);\n v4 = (char *)(a1 + 2);\n v5 = a1 + (unsigned int)(v1 - 3) + 3;\n while ( 1 )\n {\n v6 = v3;\n v3 = *v4;\n if ( *v4 != v2 )\n break;\n ++v4;\n v2 = v6;\n if ( v4 == (char *)v5 )\n return 1LL;\n }\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(long long a1) {\n int v1;\n char v2;\n char v3;\n char *v4;\n long long v5;\n char v6;\n v1 = strlen((const char *)a1);\n if (v1 > 2) {\n v2 = *(uint8_t *)a1;\n v3 = *(uint8_t *)(a1 + 1);\n v4 = (char *)(a1 + 2);\n v5 = a1 + (unsigned int)(v1 - 3) + 3;\n while (1) {\n v6 = v3;\n v3 = *v4;\n if (*v4 != v2) break;\n ++v4;\n v2 = v6;\n if (v4 == (char *)v5) return 1LL;\n }\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1) {\n int v1;\n char v2;\n char v3;\n char *v4;\n long long v5;\n char v6;\n v1 = strlen((const char *)a1);\n if (v1 > 2) {\n v2 = *(uint8_t *)a1;\n v3 = *(uint8_t *)(a1 + 1);\n v4 = (char *)(a1 + 2);\n v5 = a1 + (unsigned int)(v1 - 3) + 3;\n while (1) {\n v6 = v3;\n v3 = *v4;\n if (*v4 != v2) break;\n ++v4;\n v2 = v6;\n if (v4 == (char *)v5) return 1LL;\n }\n }\n return 0LL;\n}" + }, + { + "index": 92, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char *n) {\n int length = strlen(n);\n if (length <= 2) {\n return false;\n }\n for (int i = 2; i < length; i++) {\n if (n[i - 2] != n[i]) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n assert(func0(\"1212121\") == true);\n\n assert(func0(\"1991\") == false);\n\n assert(func0(\"121\") == true);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\ncallq 1060 \nxor %r8d,%r8d\ncmp $0x2,%eax\njle 1259 \nsub $0x3,%eax\nmovzbl (%rbx),%ecx\nmovzbl 0x1(%rbx),%esi\nlea 0x2(%rbx),%rdx\nlea 0x3(%rbx,%rax,1),%rdi\njmp 1242 \nnopw 0x0(%rax,%rax,1)\nmov %eax,%ecx\ncmp %cl,(%rdx)\njne 1260 \nadd $0x1,%rdx\nmov %esi,%eax\nmov %ecx,%esi\ncmp %rdi,%rdx\njne 1240 \nmov $0x1,%r8d\nmov %r8d,%eax\npop %rbx\nretq\nxchg %ax,%ax\nxor %r8d,%r8d\npop %rbx\nmov %r8d,%eax\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nxor edx, edx\ncmp eax, 2\njle short loc_1257\nsub eax, 3\nmovzx esi, byte ptr [rbx]\nmovzx ecx, byte ptr [rbx+1]\nlea rdx, [rbx+2]\nlea rdi, [rbx+rax+3]\njmp short loc_124B\nloc_1240:\nadd rdx, 1\nmov esi, eax\ncmp rdx, rdi\njz short loc_1260\nloc_124B:\nmov eax, ecx\nmovzx ecx, byte ptr [rdx]\ncmp cl, sil\njz short loc_1240\nxor edx, edx\nloc_1257:\nmov eax, edx\npop rbx\nretn\nloc_1260:\nmov edx, 1\npop rbx\nmov eax, edx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1)\n{\n int v1; // eax\n char v2; // si\n char v3; // cl\n char *v4; // rdx\n __int64 v5; // rdi\n char v6; // al\n\n v1 = strlen((const char *)a1);\n if ( v1 > 2 )\n {\n v2 = *(_BYTE *)a1;\n v3 = *(_BYTE *)(a1 + 1);\n v4 = (char *)(a1 + 2);\n v5 = a1 + (unsigned int)(v1 - 3) + 3;\n while ( 1 )\n {\n v6 = v3;\n v3 = *v4;\n if ( *v4 != v2 )\n break;\n ++v4;\n v2 = v6;\n if ( v4 == (char *)v5 )\n return 1LL;\n }\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nxor edx, edx\ncmp eax, 2\njle short loc_1257\nsub eax, 3\nmovzx esi, byte ptr [rbx]\nmovzx ecx, byte ptr [rbx+1]\nlea rdx, [rbx+2]\nlea rdi, [rbx+rax+3]\njmp short loc_124B\nloc_1240:\nadd rdx, 1\nmov esi, eax\ncmp rdx, rdi\njz short loc_1260\nloc_124B:\nmov eax, ecx\nmovzx ecx, byte ptr [rdx]\ncmp cl, sil\njz short loc_1240\nxor edx, edx\nloc_1257:\nmov eax, edx\npop rbx\nretn\nloc_1260:\nmov edx, 1\npop rbx\nmov eax, edx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(__int64 a1)\n{\n int v1; // eax\n char v2; // si\n char v3; // cl\n char *v4; // rdx\n __int64 v5; // rdi\n char v6; // al\n\n v1 = strlen((const char *)a1);\n if ( v1 > 2 )\n {\n v2 = *(_BYTE *)a1;\n v3 = *(_BYTE *)(a1 + 1);\n v4 = (char *)(a1 + 2);\n v5 = a1 + (unsigned int)(v1 - 3) + 3;\n while ( 1 )\n {\n v6 = v3;\n v3 = *v4;\n if ( *v4 != v2 )\n break;\n ++v4;\n v2 = v6;\n if ( v4 == (char *)v5 )\n return 1LL;\n }\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(long long a1) {\n int v1;\n char v2;\n char v3;\n char *v4;\n long long v5;\n char v6;\n v1 = strlen((const char *)a1);\n if (v1 > 2) {\n v2 = *(uint8_t *)a1;\n v3 = *(uint8_t *)(a1 + 1);\n v4 = (char *)(a1 + 2);\n v5 = a1 + (unsigned int)(v1 - 3) + 3;\n while (1) {\n v6 = v3;\n v3 = *v4;\n if (*v4 != v2) break;\n ++v4;\n v2 = v6;\n if (v4 == (char *)v5) return 1LL;\n }\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1) {\n int v1;\n char v2;\n char v3;\n char *v4;\n long long v5;\n char v6;\n v1 = strlen((const char *)a1);\n if (v1 > 2) {\n v2 = *(uint8_t *)a1;\n v3 = *(uint8_t *)(a1 + 1);\n v4 = (char *)(a1 + 2);\n v5 = a1 + (unsigned int)(v1 - 3) + 3;\n while (1) {\n v6 = v3;\n v3 = *v4;\n if (*v4 != v2) break;\n ++v4;\n v2 = v6;\n if (v4 == (char *)v5) return 1LL;\n }\n }\n return 0LL;\n}" + }, + { + "index": 93, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int a, int b) {\n if (b == 0)\n return 1;\n else if (a == 0)\n return 0;\n else if (b == 1)\n return a;\n else\n return a * func0(a, b - 1);\n}", + "test": "int main() {\n\n assert(func0(3, 4) == 81);\n\n assert(func0(2, 3) == 8);\n\n assert(func0(5, 5) == 3125);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %edi,-0x4(%rbp)\nmov %esi,-0x8(%rbp)\ncmpl $0x0,-0x8(%rbp)\njne 1168 \nmov $0x1,%eax\njmp 1196 \ncmpl $0x0,-0x4(%rbp)\njne 1175 \nmov $0x0,%eax\njmp 1196 \ncmpl $0x1,-0x8(%rbp)\njne 1180 \nmov -0x4(%rbp),%eax\njmp 1196 \nmov -0x8(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x4(%rbp),%eax\nmov %edx,%esi\nmov %eax,%edi\ncallq 1149 \nimul -0x4(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\ncmp [rbp+var_8], 0\njnz short loc_1168\nmov eax, 1\njmp short locret_1196\nloc_1168:\ncmp [rbp+var_4], 0\njnz short loc_1175\nmov eax, 0\njmp short locret_1196\nloc_1175:\ncmp [rbp+var_8], 1\njnz short loc_1180\nmov eax, [rbp+var_4]\njmp short locret_1196\nloc_1180:\nmov eax, [rbp+var_8]\nlea edx, [rax-1]\nmov eax, [rbp+var_4]\nmov esi, edx\nmov edi, eax\ncall func0\nimul eax, [rbp+var_4]\nlocret_1196:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1, int a2)\n{\n if ( !a2 )\n return 1LL;\n if ( !a1 )\n return 0LL;\n if ( a2 == 1 )\n return a1;\n return a1 * (unsigned int)func0(a1, (unsigned int)(a2 - 1));\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\ncmp [rbp+var_8], 0\njnz short loc_1168\nmov eax, 1\njmp short locret_1196\nloc_1168:\ncmp [rbp+var_4], 0\njnz short loc_1175\nmov eax, 0\njmp short locret_1196\nloc_1175:\ncmp [rbp+var_8], 1\njnz short loc_1180\nmov eax, [rbp+var_4]\njmp short locret_1196\nloc_1180:\nmov eax, [rbp+var_8]\nlea edx, [rax-1]\nmov eax, [rbp+var_4]\nmov esi, edx\nmov edi, eax\ncall sub_1149\nimul eax, [rbp+var_4]\nlocret_1196:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(unsigned int a1, int a2)\n{\n if ( !a2 )\n return 1LL;\n if ( !a1 )\n return 0LL;\n if ( a2 == 1 )\n return a1;\n return a1 * (unsigned int)sub_1149(a1, (unsigned int)(a2 - 1));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(unsigned int a1, int a2) {\n if (!a2) return 1LL;\n if (!a1) return 0LL;\n if (a2 == 1) return a1;\n return a1 * (unsigned int)sub_1149(a1, (unsigned int)(a2 - 1));\n}", + "ida_pseudo_norm": "long long func0(unsigned int a1, int a2) {\n if (!a2) return 1LL;\n if (!a1) return 0LL;\n if (a2 == 1) return a1;\n return a1 * (unsigned int)func0(a1, (unsigned int)(a2 - 1));\n}" + }, + { + "index": 93, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int a, int b) {\n if (b == 0)\n return 1;\n else if (a == 0)\n return 0;\n else if (b == 1)\n return a;\n else\n return a * func0(a, b - 1);\n}", + "test": "int main() {\n\n assert(func0(3, 4) == 81);\n\n assert(func0(2, 3) == 8);\n\n assert(func0(5, 5) == 3125);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x1,%eax\ntest %esi,%esi\nje 1173 \npush %rbx\nmov %edi,%ebx\nmov %edi,%eax\ntest %edi,%edi\nje 1164 \ncmp $0x1,%esi\njne 1166 \npop %rbx\nretq\nsub $0x1,%esi\ncallq 1149 \nimul %ebx,%eax\njmp 1164 \nretq\n", + "ida_asm": "func0:\nendbr64\nmov eax, 1\ntest esi, esi\njz short locret_1173\npush rbx\nmov ebx, edi\nmov eax, edi\ntest edi, edi\njz short loc_1164\ncmp esi, 1\njnz short loc_1166\nloc_1164:\npop rbx\nretn\nloc_1166:\nsub esi, 1\ncall func0\nimul eax, ebx\njmp short loc_1164\nlocret_1173:\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 result; // rax\n\n result = 1LL;\n if ( a2 )\n {\n result = (unsigned int)a1;\n if ( (_DWORD)a1 )\n {\n if ( a2 != 1 )\n return (unsigned int)a1 * (unsigned int)func0(a1, (unsigned int)(a2 - 1));\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmov eax, 1\ntest esi, esi\njz short locret_1173\npush rbx\nmov ebx, edi\nmov eax, edi\ntest edi, edi\njz short loc_1164\ncmp esi, 1\njnz short loc_1166\nloc_1164:\npop rbx\nretn\nloc_1166:\nsub esi, 1\ncall sub_1149\nimul eax, ebx\njmp short loc_1164\nlocret_1173:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(__int64 a1, int a2)\n{\n __int64 result; // rax\n\n result = 1LL;\n if ( a2 )\n {\n result = (unsigned int)a1;\n if ( (_DWORD)a1 )\n {\n if ( a2 != 1 )\n return (unsigned int)a1 * (unsigned int)sub_1149(a1, (unsigned int)(a2 - 1));\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(long long a1, int a2) {\n long long result;\n result = 1LL;\n if (a2) {\n result = (unsigned int)a1;\n if ((uint32_t)a1) {\n if (a2 != 1)\n return (unsigned int)a1 *\n (unsigned int)sub_1149(a1, (unsigned int)(a2 - 1));\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long result;\n result = 1LL;\n if (a2) {\n result = (unsigned int)a1;\n if ((uint32_t)a1) {\n if (a2 != 1)\n return (unsigned int)a1 *\n (unsigned int)func0(a1, (unsigned int)(a2 - 1));\n }\n }\n return result;\n}" + }, + { + "index": 94, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char test_list[][2][50], int size) {\n int min_index = 0;\n int min_value = atoi(test_list[0][1]);\n for (int i = 1; i < size; i++) {\n int current_value = atoi(test_list[i][1]);\n if (current_value < min_value) {\n min_value = current_value;\n min_index = i;\n }\n }\n return test_list[min_index][0];\n}", + "test": "int main() {\n\n char list1[3][2][50] = {{\"Rash\", \"143\"}, {\"Manjeet\", \"200\"}, {\"Varsha\", \"100\"}};\n\n char list2[3][2][50] = {{\"Yash\", \"185\"}, {\"Dawood\", \"125\"}, {\"Sanya\", \"175\"}};\n\n char list3[3][2][50] = {{\"Sai\", \"345\"}, {\"Salman\", \"145\"}, {\"Ayesha\", \"96\"}};\n\n \n\n assert(strcmp(func0(list1, 3), \"Varsha\") == 0);\n\n assert(strcmp(func0(list2, 3), \"Dawood\") == 0);\n\n assert(strcmp(func0(list3, 3), \"Ayesha\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x10(%rbp)\nmov -0x18(%rbp),%rax\nadd $0x32,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %eax,-0xc(%rbp)\nmovl $0x1,-0x8(%rbp)\njmp 122f \nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nadd $0x32,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0xc(%rbp),%eax\njge 122b \nmov -0x4(%rbp),%eax\nmov %eax,-0xc(%rbp)\nmov -0x8(%rbp),%eax\nmov %eax,-0x10(%rbp)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11df \nmov -0x10(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_10], 0\nmov rax, [rbp+var_18]\nadd rax, 32h ; '2'\nmov rdi, rax; nptr\ncall _atoi\nmov [rbp+var_C], eax\nmov [rbp+var_8], 1\njmp short loc_122F\nloc_11DF:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rax, rdx\nadd rax, 32h ; '2'\nmov rdi, rax; nptr\ncall _atoi\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_C]\njge short loc_122B\nmov eax, [rbp+var_4]\nmov [rbp+var_C], eax\nmov eax, [rbp+var_8]\nmov [rbp+var_10], eax\nloc_122B:\nadd [rbp+var_8], 1\nloc_122F:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_11DF\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rax, rdx\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v3; // [rsp+10h] [rbp-10h]\n __int64 v4; // [rsp+18h] [rbp-8h]\n\n LODWORD(v3) = 0;\n HIDWORD(v3) = atoi((const char *)(a1 + 50));\n LODWORD(v4) = 1;\n while ( (int)v4 < a2 )\n {\n HIDWORD(v4) = atoi((const char *)(100LL * (int)v4 + a1 + 50));\n if ( SHIDWORD(v4) < SHIDWORD(v3) )\n v3 = v4;\n LODWORD(v4) = v4 + 1;\n }\n return 100LL * (int)v3 + a1;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_10], 0\nmov rax, [rbp+var_18]\nadd rax, 32h ; '2'\nmov rdi, rax; nptr\ncall _atoi\nmov [rbp+var_C], eax\nmov [rbp+var_8], 1\njmp short loc_122F\nloc_11DF:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rax, rdx\nadd rax, 32h ; '2'\nmov rdi, rax; nptr\ncall _atoi\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_C]\njge short loc_122B\nmov eax, [rbp+var_4]\nmov [rbp+var_C], eax\nmov eax, [rbp+var_8]\nmov [rbp+var_10], eax\nloc_122B:\nadd [rbp+var_8], 1\nloc_122F:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_11DF\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rax, rdx\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(__int64 a1, int a2)\n{\n __int64 v3; // [rsp+10h] [rbp-10h]\n __int64 v4; // [rsp+18h] [rbp-8h]\n\n LODWORD(v3) = 0;\n HIDWORD(v3) = atoi((const char *)(a1 + 50));\n LODWORD(v4) = 1;\n while ( (int)v4 < a2 )\n {\n HIDWORD(v4) = atoi((const char *)(100LL * (int)v4 + a1 + 50));\n if ( SHIDWORD(v4) < SHIDWORD(v3) )\n v3 = v4;\n LODWORD(v4) = v4 + 1;\n }\n return 100LL * (int)v3 + a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(long long a1, int a2) {\n long long v3;\n long long v4;\n LODWORD(v3) = 0;\n HIDWORD(v3) = atoi((const char *)(a1 + 50));\n LODWORD(v4) = 1;\n while ((int)v4 < a2) {\n HIDWORD(v4) = atoi((const char *)(100LL * (int)v4 + a1 + 50));\n if (SHIDWORD(v4) < SHIDWORD(v3)) v3 = v4;\n LODWORD(v4) = v4 + 1;\n }\n return 100LL * (int)v3 + a1;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v3;\n long long v4;\n LODWORD(v3) = 0;\n HIDWORD(v3) = atoi((const char *)(a1 + 50));\n LODWORD(v4) = 1;\n while ((int)v4 < a2) {\n HIDWORD(v4) = atoi((const char *)(100LL * (int)v4 + a1 + 50));\n if (SHIDWORD(v4) < SHIDWORD(v3)) v3 = v4;\n LODWORD(v4) = v4 + 1;\n }\n return 100LL * (int)v3 + a1;\n}" + }, + { + "index": 94, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char test_list[][2][50], int size) {\n int min_index = 0;\n int min_value = atoi(test_list[0][1]);\n for (int i = 1; i < size; i++) {\n int current_value = atoi(test_list[i][1]);\n if (current_value < min_value) {\n min_value = current_value;\n min_index = i;\n }\n }\n return test_list[min_index][0];\n}", + "test": "int main() {\n\n char list1[3][2][50] = {{\"Rash\", \"143\"}, {\"Manjeet\", \"200\"}, {\"Varsha\", \"100\"}};\n\n char list2[3][2][50] = {{\"Yash\", \"185\"}, {\"Dawood\", \"125\"}, {\"Sanya\", \"175\"}};\n\n char list3[3][2][50] = {{\"Sai\", \"345\"}, {\"Salman\", \"145\"}, {\"Ayesha\", \"96\"}};\n\n \n\n assert(strcmp(func0(list1, 3), \"Varsha\") == 0);\n\n assert(strcmp(func0(list2, 3), \"Dawood\") == 0);\n\n assert(strcmp(func0(list3, 3), \"Ayesha\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%r15\nmov %esi,%r13d\nlea 0x32(%rdi),%rdi\nmov $0xa,%edx\nmov $0x0,%esi\ncallq 1090 \ncmp $0x1,%r13d\njle 11fc \nmov %eax,%r12d\nlea 0x96(%r15),%rbp\nmov $0x1,%ebx\nmov $0x0,%r14d\njmp 11dd \nadd $0x1,%ebx\nadd $0x64,%rbp\ncmp %ebx,%r13d\nje 1202 \nmov $0xa,%edx\nmov $0x0,%esi\nmov %rbp,%rdi\ncallq 1090 \ncmp %r12d,%eax\njge 11d1 \nmov %eax,%r12d\nmov %ebx,%r14d\njmp 11d1 \nmov $0x0,%r14d\nmovslq %r14d,%r14\nlea (%r14,%r14,4),%rax\nlea (%rax,%rax,4),%rax\nlea (%r15,%rax,4),%rax\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r15, rdi\nmov r14d, esi\nlea rdi, [rdi+32h]; nptr\nmov edx, 0Ah; base\nmov esi, 0; endptr\ncall _strtol\ncmp r14d, 1\njle short loc_1234\nmov ebp, eax\nlea r12, [r15+96h]\nmov ebx, 1\nmov r13d, 0\nloc_11EE:\nmov edx, 0Ah; base\nmov esi, 0; endptr\nmov rdi, r12; nptr\ncall _strtol\ncmp eax, ebp\ncmovl ebp, eax\ncmovl r13d, ebx\nadd ebx, 1\nadd r12, 64h ; 'd'\ncmp r14d, ebx\njnz short loc_11EE\nloc_1215:\nmovsxd r13, r13d\nlea rax, [r13+r13*4+0]\nlea rax, [rax+rax*4]\nlea rax, [r15+rax*4]\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1234:\nmov r13d, 0\njmp short loc_1215", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int v2; // eax\n int v3; // ebp\n const char *v4; // r12\n int v5; // ebx\n int v6; // r13d\n int v7; // eax\n\n v2 = strtol((const char *)(a1 + 50), 0LL, 10);\n if ( a2 <= 1 )\n {\n v6 = 0;\n }\n else\n {\n v3 = v2;\n v4 = (const char *)(a1 + 150);\n v5 = 1;\n v6 = 0;\n do\n {\n v7 = strtol(v4, 0LL, 10);\n if ( v7 < v3 )\n {\n v3 = v7;\n v6 = v5;\n }\n ++v5;\n v4 += 100;\n }\n while ( a2 != v5 );\n }\n return a1 + 100LL * v6;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r15, rdi\nmov r14d, esi\nlea rdi, [rdi+32h]; nptr\nmov edx, 0Ah; base\nmov esi, 0; endptr\ncall _strtol\ncmp r14d, 1\njle short loc_1234\nmov ebp, eax\nlea r12, [r15+96h]\nmov ebx, 1\nmov r13d, 0\nloc_11EE:\nmov edx, 0Ah; base\nmov esi, 0; endptr\nmov rdi, r12; nptr\ncall _strtol\ncmp eax, ebp\ncmovl ebp, eax\ncmovl r13d, ebx\nadd ebx, 1\nadd r12, 64h ; 'd'\ncmp r14d, ebx\njnz short loc_11EE\nloc_1215:\nmovsxd r13, r13d\nlea rax, [r13+r13*4+0]\nlea rax, [rax+rax*4]\nlea rax, [r15+rax*4]\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1234:\nmov r13d, 0\njmp short loc_1215", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(__int64 a1, int a2)\n{\n int v2; // eax\n int v3; // ebp\n const char *v4; // r12\n int v5; // ebx\n int v6; // r13d\n int v7; // eax\n\n v2 = strtol((const char *)(a1 + 50), 0LL, 10);\n if ( a2 <= 1 )\n {\n v6 = 0;\n }\n else\n {\n v3 = v2;\n v4 = (const char *)(a1 + 150);\n v5 = 1;\n v6 = 0;\n do\n {\n v7 = strtol(v4, 0LL, 10);\n if ( v7 < v3 )\n {\n v3 = v7;\n v6 = v5;\n }\n ++v5;\n v4 += 100;\n }\n while ( a2 != v5 );\n }\n return a1 + 100LL * v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(long long a1, int a2) {\n int v2;\n int v3;\n const char *v4;\n int v5;\n int v6;\n int v7;\n v2 = strtol((const char *)(a1 + 50), 0LL, 10);\n if (a2 <= 1) {\n v6 = 0;\n } else {\n v3 = v2;\n v4 = (const char *)(a1 + 150);\n v5 = 1;\n v6 = 0;\n do {\n v7 = strtol(v4, 0LL, 10);\n if (v7 < v3) {\n v3 = v7;\n v6 = v5;\n }\n ++v5;\n v4 += 100;\n } while (a2 != v5);\n }\n return a1 + 100LL * v6;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int v2;\n int v3;\n const char *v4;\n int v5;\n int v6;\n int v7;\n v2 = strtol((const char *)(a1 + 50), 0LL, 10);\n if (a2 <= 1) {\n v6 = 0;\n } else {\n v3 = v2;\n v4 = (const char *)(a1 + 150);\n v5 = 1;\n v6 = 0;\n do {\n v7 = strtol(v4, 0LL, 10);\n if (v7 < v3) {\n v3 = v7;\n v6 = v5;\n }\n ++v5;\n v4 += 100;\n } while (a2 != v5);\n }\n return a1 + 100LL * v6;\n}" + }, + { + "index": 94, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char test_list[][2][50], int size) {\n int min_index = 0;\n int min_value = atoi(test_list[0][1]);\n for (int i = 1; i < size; i++) {\n int current_value = atoi(test_list[i][1]);\n if (current_value < min_value) {\n min_value = current_value;\n min_index = i;\n }\n }\n return test_list[min_index][0];\n}", + "test": "int main() {\n\n char list1[3][2][50] = {{\"Rash\", \"143\"}, {\"Manjeet\", \"200\"}, {\"Varsha\", \"100\"}};\n\n char list2[3][2][50] = {{\"Yash\", \"185\"}, {\"Dawood\", \"125\"}, {\"Sanya\", \"175\"}};\n\n char list3[3][2][50] = {{\"Sai\", \"345\"}, {\"Salman\", \"145\"}, {\"Ayesha\", \"96\"}};\n\n \n\n assert(strcmp(func0(list1, 3), \"Varsha\") == 0);\n\n assert(strcmp(func0(list2, 3), \"Dawood\") == 0);\n\n assert(strcmp(func0(list3, 3), \"Ayesha\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmov $0xa,%edx\npush %r14\npush %r13\nmov %rdi,%r13\nadd $0x32,%rdi\npush %r12\npush %rbp\nmov %esi,%ebp\nxor %esi,%esi\npush %rbx\nsub $0x8,%rsp\ncallq 1090 \ncmp $0x1,%ebp\njle 1372 \nmov %eax,%ebx\nlea 0x96(%r13),%r15\nmov $0x1,%r14d\nxor %r12d,%r12d\nxchg %ax,%ax\nxor %esi,%esi\nmov $0xa,%edx\nmov %r15,%rdi\ncallq 1090 \ncmp %ebx,%eax\njge 1358 \nmov %eax,%ebx\nmovslq %r14d,%r12\nadd $0x1,%r14d\nadd $0x64,%r15\ncmp %r14d,%ebp\njne 1340 \nlea (%r12,%r12,4),%rax\nlea (%rax,%rax,4),%rax\nlea 0x0(%r13,%rax,4),%r13\nadd $0x8,%rsp\nmov %r13,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov edx, 0Ah; base\npush r14\npush r13\nmov r13, rdi\nadd rdi, 32h ; '2'; nptr\npush r12\nmov r12d, esi\nxor esi, esi; endptr\npush rbp\npush rbx\nsub rsp, 8\ncall _strtol\ncmp r12d, 1\njle short loc_1384\nmov ebp, eax\nlea r14, [r13+96h]\nmov ebx, 1\nxor r15d, r15d\nnop\nloc_1350:\nxor esi, esi; endptr\nmov rdi, r14; nptr\nmov edx, 0Ah; base\ncall _strtol\ncmp eax, ebp\ncmovl ebp, eax\ncmovl r15d, ebx\nadd ebx, 1\nadd r14, 64h ; 'd'\ncmp r12d, ebx\njnz short loc_1350\nmovsxd r15, r15d\nlea rax, [r15+r15*4]\nlea rax, [rax+rax*4]\nlea r13, [r13+rax*4+0]\nloc_1384:\nadd rsp, 8\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // r13\n int v3; // eax\n int v4; // ebp\n const char *v5; // r14\n int v6; // ebx\n int v7; // r15d\n int v8; // eax\n\n v2 = a1;\n v3 = strtol((const char *)(a1 + 50), 0LL, 10);\n if ( a2 > 1 )\n {\n v4 = v3;\n v5 = (const char *)(a1 + 150);\n v6 = 1;\n v7 = 0;\n do\n {\n v8 = strtol(v5, 0LL, 10);\n if ( v8 < v4 )\n {\n v4 = v8;\n v7 = v6;\n }\n ++v6;\n v5 += 100;\n }\n while ( a2 != v6 );\n return a1 + 100LL * v7;\n }\n return v2;\n}", + "ida_strip_asm": "sub_1310:\nendbr64\npush r15\nmov edx, 0Ah; base\npush r14\npush r13\nmov r13, rdi\nadd rdi, 32h ; '2'; nptr\npush r12\nmov r12d, esi\nxor esi, esi; endptr\npush rbp\npush rbx\nsub rsp, 8\ncall _strtol\ncmp r12d, 1\njle short loc_1384\nmov ebp, eax\nlea r14, [r13+96h]\nmov ebx, 1\nxor r15d, r15d\nnop\nloc_1350:\nxor esi, esi; endptr\nmov rdi, r14; nptr\nmov edx, 0Ah; base\ncall _strtol\ncmp eax, ebp\ncmovl ebp, eax\ncmovl r15d, ebx\nadd ebx, 1\nadd r14, 64h ; 'd'\ncmp r12d, ebx\njnz short loc_1350\nmovsxd r15, r15d\nlea rax, [r15+r15*4]\nlea rax, [rax+rax*4]\nlea r13, [r13+rax*4+0]\nloc_1384:\nadd rsp, 8\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1310(__int64 a1, int a2)\n{\n __int64 v2; // r13\n int v3; // eax\n int v4; // ebp\n const char *v5; // r14\n int v6; // ebx\n int v7; // r15d\n int v8; // eax\n\n v2 = a1;\n v3 = strtol((const char *)(a1 + 50), 0LL, 10);\n if ( a2 > 1 )\n {\n v4 = v3;\n v5 = (const char *)(a1 + 150);\n v6 = 1;\n v7 = 0;\n do\n {\n v8 = strtol(v5, 0LL, 10);\n if ( v8 < v4 )\n {\n v4 = v8;\n v7 = v6;\n }\n ++v6;\n v5 += 100;\n }\n while ( a2 != v6 );\n return a1 + 100LL * v7;\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1310(long long a1, int a2) {\n long long v2;\n int v3;\n int v4;\n const char *v5;\n int v6;\n int v7;\n int v8;\n v2 = a1;\n v3 = strtol((const char *)(a1 + 50), 0LL, 10);\n if (a2 > 1) {\n v4 = v3;\n v5 = (const char *)(a1 + 150);\n v6 = 1;\n v7 = 0;\n do {\n v8 = strtol(v5, 0LL, 10);\n if (v8 < v4) {\n v4 = v8;\n v7 = v6;\n }\n ++v6;\n v5 += 100;\n } while (a2 != v6);\n return a1 + 100LL * v7;\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n int v3;\n int v4;\n const char *v5;\n int v6;\n int v7;\n int v8;\n v2 = a1;\n v3 = strtol((const char *)(a1 + 50), 0LL, 10);\n if (a2 > 1) {\n v4 = v3;\n v5 = (const char *)(a1 + 150);\n v6 = 1;\n v7 = 0;\n do {\n v8 = strtol(v5, 0LL, 10);\n if (v8 < v4) {\n v4 = v8;\n v7 = v6;\n }\n ++v6;\n v5 += 100;\n } while (a2 != v6);\n return a1 + 100LL * v7;\n }\n return v2;\n}" + }, + { + "index": 94, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char test_list[][2][50], int size) {\n int min_index = 0;\n int min_value = atoi(test_list[0][1]);\n for (int i = 1; i < size; i++) {\n int current_value = atoi(test_list[i][1]);\n if (current_value < min_value) {\n min_value = current_value;\n min_index = i;\n }\n }\n return test_list[min_index][0];\n}", + "test": "int main() {\n\n char list1[3][2][50] = {{\"Rash\", \"143\"}, {\"Manjeet\", \"200\"}, {\"Varsha\", \"100\"}};\n\n char list2[3][2][50] = {{\"Yash\", \"185\"}, {\"Dawood\", \"125\"}, {\"Sanya\", \"175\"}};\n\n char list3[3][2][50] = {{\"Sai\", \"345\"}, {\"Salman\", \"145\"}, {\"Ayesha\", \"96\"}};\n\n \n\n assert(strcmp(func0(list1, 3), \"Varsha\") == 0);\n\n assert(strcmp(func0(list2, 3), \"Dawood\") == 0);\n\n assert(strcmp(func0(list3, 3), \"Ayesha\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmov $0xa,%edx\npush %r14\npush %r13\nmov %rdi,%r13\nadd $0x32,%rdi\npush %r12\npush %rbp\nmov %esi,%ebp\nxor %esi,%esi\npush %rbx\nsub $0x8,%rsp\ncallq 1090 \ncmp $0x1,%ebp\njle 1372 \nmov %eax,%ebx\nlea 0x96(%r13),%r15\nmov $0x1,%r14d\nxor %r12d,%r12d\nxchg %ax,%ax\nxor %esi,%esi\nmov $0xa,%edx\nmov %r15,%rdi\ncallq 1090 \ncmp %ebx,%eax\njge 1358 \nmov %eax,%ebx\nmovslq %r14d,%r12\nadd $0x1,%r14d\nadd $0x64,%r15\ncmp %r14d,%ebp\njne 1340 \nlea (%r12,%r12,4),%rax\nlea (%rax,%rax,4),%rax\nlea 0x0(%r13,%rax,4),%r13\nadd $0x8,%rsp\nmov %r13,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov edx, 0Ah; base\npush r14\npush r13\nmov r13, rdi\nadd rdi, 32h ; '2'; nptr\npush r12\nmov r12d, esi\nxor esi, esi; endptr\npush rbp\npush rbx\nsub rsp, 8\ncall _strtol\ncmp r12d, 1\njle short loc_1384\nmov ebp, eax\nlea r14, [r13+96h]\nmov ebx, 1\nxor r15d, r15d\nnop\nloc_1350:\nxor esi, esi; endptr\nmov rdi, r14; nptr\nmov edx, 0Ah; base\ncall _strtol\ncmp eax, ebp\ncmovl ebp, eax\ncmovl r15d, ebx\nadd ebx, 1\nadd r14, 64h ; 'd'\ncmp r12d, ebx\njnz short loc_1350\nmovsxd r15, r15d\nlea rax, [r15+r15*4]\nlea rax, [rax+rax*4]\nlea r13, [r13+rax*4+0]\nloc_1384:\nadd rsp, 8\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // r13\n int v3; // eax\n int v4; // ebp\n const char *v5; // r14\n int v6; // ebx\n int v7; // r15d\n int v8; // eax\n\n v2 = a1;\n v3 = strtol((const char *)(a1 + 50), 0LL, 10);\n if ( a2 > 1 )\n {\n v4 = v3;\n v5 = (const char *)(a1 + 150);\n v6 = 1;\n v7 = 0;\n do\n {\n v8 = strtol(v5, 0LL, 10);\n if ( v8 < v4 )\n {\n v4 = v8;\n v7 = v6;\n }\n ++v6;\n v5 += 100;\n }\n while ( a2 != v6 );\n return a1 + 100LL * v7;\n }\n return v2;\n}", + "ida_strip_asm": "sub_1310:\nendbr64\npush r15\nmov edx, 0Ah; base\npush r14\npush r13\nmov r13, rdi\nadd rdi, 32h ; '2'; nptr\npush r12\nmov r12d, esi\nxor esi, esi; endptr\npush rbp\npush rbx\nsub rsp, 8\ncall _strtol\ncmp r12d, 1\njle short loc_1384\nmov ebp, eax\nlea r14, [r13+96h]\nmov ebx, 1\nxor r15d, r15d\nnop\nloc_1350:\nxor esi, esi; endptr\nmov rdi, r14; nptr\nmov edx, 0Ah; base\ncall _strtol\ncmp eax, ebp\ncmovl ebp, eax\ncmovl r15d, ebx\nadd ebx, 1\nadd r14, 64h ; 'd'\ncmp r12d, ebx\njnz short loc_1350\nmovsxd r15, r15d\nlea rax, [r15+r15*4]\nlea rax, [rax+rax*4]\nlea r13, [r13+rax*4+0]\nloc_1384:\nadd rsp, 8\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1310(__int64 a1, int a2)\n{\n __int64 v2; // r13\n int v3; // eax\n int v4; // ebp\n const char *v5; // r14\n int v6; // ebx\n int v7; // r15d\n int v8; // eax\n\n v2 = a1;\n v3 = strtol((const char *)(a1 + 50), 0LL, 10);\n if ( a2 > 1 )\n {\n v4 = v3;\n v5 = (const char *)(a1 + 150);\n v6 = 1;\n v7 = 0;\n do\n {\n v8 = strtol(v5, 0LL, 10);\n if ( v8 < v4 )\n {\n v4 = v8;\n v7 = v6;\n }\n ++v6;\n v5 += 100;\n }\n while ( a2 != v6 );\n return a1 + 100LL * v7;\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1310(long long a1, int a2) {\n long long v2;\n int v3;\n int v4;\n const char *v5;\n int v6;\n int v7;\n int v8;\n v2 = a1;\n v3 = strtol((const char *)(a1 + 50), 0LL, 10);\n if (a2 > 1) {\n v4 = v3;\n v5 = (const char *)(a1 + 150);\n v6 = 1;\n v7 = 0;\n do {\n v8 = strtol(v5, 0LL, 10);\n if (v8 < v4) {\n v4 = v8;\n v7 = v6;\n }\n ++v6;\n v5 += 100;\n } while (a2 != v6);\n return a1 + 100LL * v7;\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n int v3;\n int v4;\n const char *v5;\n int v6;\n int v7;\n int v8;\n v2 = a1;\n v3 = strtol((const char *)(a1 + 50), 0LL, 10);\n if (a2 > 1) {\n v4 = v3;\n v5 = (const char *)(a1 + 150);\n v6 = 1;\n v7 = 0;\n do {\n v8 = strtol(v5, 0LL, 10);\n if (v8 < v4) {\n v4 = v8;\n v7 = v6;\n }\n ++v6;\n v5 += 100;\n } while (a2 != v6);\n return a1 + 100LL * v7;\n }\n return v2;\n}" + }, + { + "index": 95, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char lst[][50], int size) {\n int minLength = strlen(lst[0]);\n for (int i = 1; i < size; i++) {\n int length = strlen(lst[i]);\n if (length < minLength) {\n minLength = length;\n }\n }\n return minLength;\n}", + "test": "int main() {\n\n char list1[][50] = {\"1\", \"12\"};\n\n char list2[][50] = {\"12\", \"123\", \"1234\"};\n\n char list3[][50] = {\"333\", \"4444\"};\n\n\n\n assert(func0(list1, 2) == 1);\n\n assert(func0(list2, 3) == 2);\n\n assert(func0(list3, 2) == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov -0x18(%rbp),%rax\nmov %rax,%rdi\ncallq 1070 \nmov %eax,-0xc(%rbp)\nmovl $0x1,-0x8(%rbp)\njmp 11f9 \nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nadd %rax,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov %rax,%rdi\ncallq 1070 \nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0xc(%rbp),%eax\njge 11f5 \nmov -0x4(%rbp),%eax\nmov %eax,-0xc(%rbp)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11b4 \nmov -0xc(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov [rbp+var_1C], esi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_C], eax\nmov [rbp+var_8], 1\njmp short loc_11F9\nloc_11B4:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nadd rax, rax\nmov rdx, rax\nmov rax, [rbp+s]\nadd rax, rdx\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_C]\njge short loc_11F5\nmov eax, [rbp+var_4]\nmov [rbp+var_C], eax\nloc_11F5:\nadd [rbp+var_8], 1\nloc_11F9:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_11B4\nmov eax, [rbp+var_C]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-Ch]\n int i; // [rsp+18h] [rbp-8h]\n int v5; // [rsp+1Ch] [rbp-4h]\n\n v3 = strlen(a1);\n for ( i = 1; i < a2; ++i )\n {\n v5 = strlen(&a1[50 * i]);\n if ( v5 < (int)v3 )\n v3 = v5;\n }\n return v3;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov [rbp+var_1C], esi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_C], eax\nmov [rbp+var_8], 1\njmp short loc_11F9\nloc_11B4:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nadd rax, rax\nmov rdx, rax\nmov rax, [rbp+s]\nadd rax, rdx\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_C]\njge short loc_11F5\nmov eax, [rbp+var_4]\nmov [rbp+var_C], eax\nloc_11F5:\nadd [rbp+var_8], 1\nloc_11F9:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_11B4\nmov eax, [rbp+var_C]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(const char *a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-Ch]\n int i; // [rsp+18h] [rbp-8h]\n int v5; // [rsp+1Ch] [rbp-4h]\n\n v3 = strlen(a1);\n for ( i = 1; i < a2; ++i )\n {\n v5 = strlen(&a1[50 * i]);\n if ( v5 < (int)v3 )\n v3 = v5;\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(const char *a1, int a2) {\n unsigned int v3;\n int i;\n int v5;\n v3 = strlen(a1);\n for (i = 1; i < a2; ++i) {\n v5 = strlen(&a1[50 * i]);\n if (v5 < (int)v3) v3 = v5;\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, int a2) {\n unsigned int v3;\n int i;\n int v5;\n v3 = strlen(a1);\n for (i = 1; i < a2; ++i) {\n v5 = strlen(&a1[50 * i]);\n if (v5 < (int)v3) v3 = v5;\n }\n return v3;\n}" + }, + { + "index": 95, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char lst[][50], int size) {\n int minLength = strlen(lst[0]);\n for (int i = 1; i < size; i++) {\n int length = strlen(lst[i]);\n if (length < minLength) {\n minLength = length;\n }\n }\n return minLength;\n}", + "test": "int main() {\n\n char list1[][50] = {\"1\", \"12\"};\n\n char list2[][50] = {\"12\", \"123\", \"1234\"};\n\n char list3[][50] = {\"333\", \"4444\"};\n\n\n\n assert(func0(list1, 2) == 1);\n\n assert(func0(list2, 3) == 2);\n\n assert(func0(list3, 2) == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%r9\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nlea -0x1(%rcx),%r8d\ncmp $0x1,%esi\njle 11c9 \nlea 0x32(%r9),%rdx\nlea -0x2(%rsi),%eax\nlea (%rax,%rax,4),%rax\nlea (%rax,%rax,4),%rax\nlea 0x64(%r9,%rax,2),%r9\nmov $0xffffffffffffffff,%rsi\nmov $0x0,%eax\nmov %rsi,%rcx\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nnot %rcx\nsub $0x1,%rcx\ncmp %ecx,%r8d\ncmovg %ecx,%r8d\nadd $0x32,%rdx\ncmp %r9,%rdx\njne 11aa \nmov %r8d,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12, rdi\nmov r13d, esi\ncall _strlen\nmov ebp, eax\ncmp r13d, 1\njle short loc_11D6\nlea rbx, [r12+32h]\nlea eax, [r13-2]\nlea rax, [rax+rax*4]\nlea rax, [rax+rax*4]\nlea r12, [r12+rax*2+64h]\nloc_11C0:\nmov rdi, rbx; s\ncall _strlen\ncmp ebp, eax\ncmovg ebp, eax\nadd rbx, 32h ; '2'\ncmp rbx, r12\njnz short loc_11C0\nloc_11D6:\nmov eax, ebp\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, int a2)\n{\n unsigned int v2; // ebp\n const char *v3; // rbx\n int v4; // eax\n\n v2 = strlen(a1);\n if ( a2 > 1 )\n {\n v3 = a1 + 50;\n do\n {\n v4 = strlen(v3);\n if ( (int)v2 > v4 )\n v2 = v4;\n v3 += 50;\n }\n while ( v3 != &a1[50 * (a2 - 2) + 100] );\n }\n return v2;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12, rdi\nmov r13d, esi\ncall _strlen\nmov ebp, eax\ncmp r13d, 1\njle short loc_11D6\nlea rbx, [r12+32h]\nlea eax, [r13-2]\nlea rax, [rax+rax*4]\nlea rax, [rax+rax*4]\nlea r12, [r12+rax*2+64h]\nloc_11C0:\nmov rdi, rbx; s\ncall _strlen\ncmp ebp, eax\ncmovg ebp, eax\nadd rbx, 32h ; '2'\ncmp rbx, r12\njnz short loc_11C0\nloc_11D6:\nmov eax, ebp\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(const char *a1, int a2)\n{\n unsigned int v2; // ebp\n const char *v3; // rbx\n int v4; // eax\n\n v2 = strlen(a1);\n if ( a2 > 1 )\n {\n v3 = a1 + 50;\n do\n {\n v4 = strlen(v3);\n if ( (int)v2 > v4 )\n v2 = v4;\n v3 += 50;\n }\n while ( v3 != &a1[50 * (a2 - 2) + 100] );\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(const char *a1, int a2) {\n unsigned int v2;\n const char *v3;\n int v4;\n v2 = strlen(a1);\n if (a2 > 1) {\n v3 = a1 + 50;\n do {\n v4 = strlen(v3);\n if ((int)v2 > v4) v2 = v4;\n v3 += 50;\n } while (v3 != &a1[50 * (a2 - 2) + 100]);\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, int a2) {\n unsigned int v2;\n const char *v3;\n int v4;\n v2 = strlen(a1);\n if (a2 > 1) {\n v3 = a1 + 50;\n do {\n v4 = strlen(v3);\n if ((int)v2 > v4) v2 = v4;\n v3 += 50;\n } while (v3 != &a1[50 * (a2 - 2) + 100]);\n }\n return v2;\n}" + }, + { + "index": 95, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char lst[][50], int size) {\n int minLength = strlen(lst[0]);\n for (int i = 1; i < size; i++) {\n int length = strlen(lst[i]);\n if (length < minLength) {\n minLength = length;\n }\n }\n return minLength;\n}", + "test": "int main() {\n\n char list1[][50] = {\"1\", \"12\"};\n\n char list2[][50] = {\"12\", \"123\", \"1234\"};\n\n char list3[][50] = {\"333\", \"4444\"};\n\n\n\n assert(func0(list1, 2) == 1);\n\n assert(func0(list2, 3) == 2);\n\n assert(func0(list3, 2) == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov %esi,%r13d\npush %r12\npush %rbp\nmov %rdi,%rbp\npush %rbx\nsub $0x8,%rsp\ncallq 1070 \nmov %eax,%r12d\ncmp $0x1,%r13d\njle 1408 \nlea -0x2(%r13),%eax\nlea 0x32(%rbp),%rbx\nlea (%rax,%rax,4),%rax\nlea (%rax,%rax,4),%rax\nlea 0x64(%rbp,%rax,2),%rbp\nnopw 0x0(%rax,%rax,1)\nmov %rbx,%rdi\ncallq 1070 \ncmp %eax,%r12d\ncmovg %eax,%r12d\nadd $0x32,%rbx\ncmp %rbp,%rbx\njne 13f0 \nadd $0x8,%rsp\nmov %r12d,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r13\nmov r13d, esi\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 8\ncall _strlen\nmov ebp, eax\ncmp r13d, 1\njle short loc_13F6\nlea eax, [r13-2]\nlea rbx, [r12+32h]\nlea rax, [rax+rax*4]\nlea rax, [rax+rax*4]\nlea r12, [r12+rax*2+64h]\nnop word ptr [rax+rax+00000000h]\nloc_13E0:\nmov rdi, rbx; s\ncall _strlen\ncmp ebp, eax\ncmovg ebp, eax\nadd rbx, 32h ; '2'\ncmp rbx, r12\njnz short loc_13E0\nloc_13F6:\nadd rsp, 8\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, int a2)\n{\n unsigned int v2; // ebp\n const char *v3; // rbx\n int v4; // eax\n\n v2 = strlen(a1);\n if ( a2 > 1 )\n {\n v3 = a1 + 50;\n do\n {\n v4 = strlen(v3);\n if ( (int)v2 > v4 )\n v2 = v4;\n v3 += 50;\n }\n while ( v3 != &a1[50 * (a2 - 2) + 100] );\n }\n return v2;\n}", + "ida_strip_asm": "sub_13A0:\nendbr64\npush r13\nmov r13d, esi\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 8\ncall _strlen\nmov ebp, eax\ncmp r13d, 1\njle short loc_13F6\nlea eax, [r13-2]\nlea rbx, [r12+32h]\nlea rax, [rax+rax*4]\nlea rax, [rax+rax*4]\nlea r12, [r12+rax*2+64h]\nnop word ptr [rax+rax+00000000h]\nloc_13E0:\nmov rdi, rbx; s\ncall _strlen\ncmp ebp, eax\ncmovg ebp, eax\nadd rbx, 32h ; '2'\ncmp rbx, r12\njnz short loc_13E0\nloc_13F6:\nadd rsp, 8\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_13A0(const char *a1, int a2)\n{\n unsigned int v2; // ebp\n const char *v3; // rbx\n int v4; // eax\n\n v2 = strlen(a1);\n if ( a2 > 1 )\n {\n v3 = a1 + 50;\n do\n {\n v4 = strlen(v3);\n if ( (int)v2 > v4 )\n v2 = v4;\n v3 += 50;\n }\n while ( v3 != &a1[50 * (a2 - 2) + 100] );\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_13A0(const char *a1, int a2) {\n unsigned int v2;\n const char *v3;\n int v4;\n v2 = strlen(a1);\n if (a2 > 1) {\n v3 = a1 + 50;\n do {\n v4 = strlen(v3);\n if ((int)v2 > v4) v2 = v4;\n v3 += 50;\n } while (v3 != &a1[50 * (a2 - 2) + 100]);\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, int a2) {\n unsigned int v2;\n const char *v3;\n int v4;\n v2 = strlen(a1);\n if (a2 > 1) {\n v3 = a1 + 50;\n do {\n v4 = strlen(v3);\n if ((int)v2 > v4) v2 = v4;\n v3 += 50;\n } while (v3 != &a1[50 * (a2 - 2) + 100]);\n }\n return v2;\n}" + }, + { + "index": 95, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char lst[][50], int size) {\n int minLength = strlen(lst[0]);\n for (int i = 1; i < size; i++) {\n int length = strlen(lst[i]);\n if (length < minLength) {\n minLength = length;\n }\n }\n return minLength;\n}", + "test": "int main() {\n\n char list1[][50] = {\"1\", \"12\"};\n\n char list2[][50] = {\"12\", \"123\", \"1234\"};\n\n char list3[][50] = {\"333\", \"4444\"};\n\n\n\n assert(func0(list1, 2) == 1);\n\n assert(func0(list2, 3) == 2);\n\n assert(func0(list3, 2) == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov %esi,%r13d\npush %r12\npush %rbp\nmov %rdi,%rbp\npush %rbx\nsub $0x8,%rsp\ncallq 1070 \nmov %eax,%r12d\ncmp $0x1,%r13d\njle 1408 \nlea -0x2(%r13),%eax\nlea 0x32(%rbp),%rbx\nlea (%rax,%rax,4),%rax\nlea (%rax,%rax,4),%rax\nlea 0x64(%rbp,%rax,2),%rbp\nnopw 0x0(%rax,%rax,1)\nmov %rbx,%rdi\ncallq 1070 \ncmp %eax,%r12d\ncmovg %eax,%r12d\nadd $0x32,%rbx\ncmp %rbx,%rbp\njne 13f0 \nadd $0x8,%rsp\nmov %r12d,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r13\nmov r13d, esi\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 8\ncall _strlen\nmov ebp, eax\ncmp r13d, 1\njle short loc_13F6\nlea eax, [r13-2]\nlea rbx, [r12+32h]\nlea rax, [rax+rax*4]\nlea rax, [rax+rax*4]\nlea r12, [r12+rax*2+64h]\nnop word ptr [rax+rax+00000000h]\nloc_13E0:\nmov rdi, rbx; s\ncall _strlen\ncmp ebp, eax\ncmovg ebp, eax\nadd rbx, 32h ; '2'\ncmp r12, rbx\njnz short loc_13E0\nloc_13F6:\nadd rsp, 8\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, int a2)\n{\n unsigned int v2; // ebp\n const char *v3; // rbx\n int v4; // eax\n\n v2 = strlen(a1);\n if ( a2 > 1 )\n {\n v3 = a1 + 50;\n do\n {\n v4 = strlen(v3);\n if ( (int)v2 > v4 )\n v2 = v4;\n v3 += 50;\n }\n while ( &a1[50 * (a2 - 2) + 100] != v3 );\n }\n return v2;\n}", + "ida_strip_asm": "sub_13A0:\nendbr64\npush r13\nmov r13d, esi\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 8\ncall _strlen\nmov ebp, eax\ncmp r13d, 1\njle short loc_13F6\nlea eax, [r13-2]\nlea rbx, [r12+32h]\nlea rax, [rax+rax*4]\nlea rax, [rax+rax*4]\nlea r12, [r12+rax*2+64h]\nnop word ptr [rax+rax+00000000h]\nloc_13E0:\nmov rdi, rbx; s\ncall _strlen\ncmp ebp, eax\ncmovg ebp, eax\nadd rbx, 32h ; '2'\ncmp r12, rbx\njnz short loc_13E0\nloc_13F6:\nadd rsp, 8\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_13A0(const char *a1, int a2)\n{\n unsigned int v2; // ebp\n const char *v3; // rbx\n int v4; // eax\n\n v2 = strlen(a1);\n if ( a2 > 1 )\n {\n v3 = a1 + 50;\n do\n {\n v4 = strlen(v3);\n if ( (int)v2 > v4 )\n v2 = v4;\n v3 += 50;\n }\n while ( &a1[50 * (a2 - 2) + 100] != v3 );\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_13A0(const char *a1, int a2) {\n unsigned int v2;\n const char *v3;\n int v4;\n v2 = strlen(a1);\n if (a2 > 1) {\n v3 = a1 + 50;\n do {\n v4 = strlen(v3);\n if ((int)v2 > v4) v2 = v4;\n v3 += 50;\n } while (&a1[50 * (a2 - 2) + 100] != v3);\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, int a2) {\n unsigned int v2;\n const char *v3;\n int v4;\n v2 = strlen(a1);\n if (a2 > 1) {\n v3 = a1 + 50;\n do {\n v4 = strlen(v3);\n if ((int)v2 > v4) v2 = v4;\n v3 += 50;\n } while (&a1[50 * (a2 - 2) + 100] != v3);\n }\n return v2;\n}" + }, + { + "index": 96, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int count = 0;\n for (int i = 1; i <= n; i++) {\n if (n % i == 0) {\n count++;\n }\n }\n return count;\n}", + "test": "int main() {\n\n assert(func0(15) == 4);\n\n assert(func0(12) == 6);\n\n assert(func0(9) == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x1,-0x4(%rbp)\njmp 1179 \nmov -0x14(%rbp),%eax\ncltd\nidivl -0x4(%rbp)\nmov %edx,%eax\ntest %eax,%eax\njne 1175 \naddl $0x1,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x14(%rbp),%eax\njle 1164 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 1\njmp short loc_1179\nloc_1164:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njnz short loc_1175\nadd [rbp+var_8], 1\nloc_1175:\nadd [rbp+var_4], 1\nloc_1179:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_14]\njle short loc_1164\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v2; // [rsp+Ch] [rbp-8h]\n int i; // [rsp+10h] [rbp-4h]\n\n v2 = 0;\n for ( i = 1; i <= a1; ++i )\n {\n if ( !(a1 % i) )\n ++v2;\n }\n return v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 1\njmp short loc_1179\nloc_1164:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njnz short loc_1175\nadd [rbp+var_8], 1\nloc_1175:\nadd [rbp+var_4], 1\nloc_1179:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_14]\njle short loc_1164\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n unsigned int v2; // [rsp+Ch] [rbp-8h]\n int i; // [rsp+10h] [rbp-4h]\n\n v2 = 0;\n for ( i = 1; i <= a1; ++i )\n {\n if ( !(a1 % i) )\n ++v2;\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n unsigned int v2;\n int i;\n v2 = 0;\n for (i = 1; i <= a1; ++i) {\n if (!(a1 % i)) ++v2;\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v2;\n int i;\n v2 = 0;\n for (i = 1; i <= a1; ++i) {\n if (!(a1 % i)) ++v2;\n }\n return v2;\n}" + }, + { + "index": 96, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int count = 0;\n for (int i = 1; i <= n; i++) {\n if (n % i == 0) {\n count++;\n }\n }\n return count;\n}", + "test": "int main() {\n\n assert(func0(15) == 4);\n\n assert(func0(12) == 6);\n\n assert(func0(9) == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\njle 1175 \nlea 0x1(%rdi),%r8d\nmov $0x1,%ecx\nmov $0x0,%esi\nmov %edi,%eax\ncltd\nidiv %ecx\ncmp $0x1,%edx\nadc $0x0,%esi\nadd $0x1,%ecx\ncmp %r8d,%ecx\njne 115f \nmov %esi,%eax\nretq\nmov $0x0,%esi\njmp 1172 \n", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njle short loc_1175\nlea r8d, [rdi+1]\nmov ecx, 1\nmov esi, 0\nloc_115F:\nmov eax, edi\ncdq\nidiv ecx\ncmp edx, 1\nadc esi, 0\nadd ecx, 1\ncmp ecx, r8d\njnz short loc_115F\nloc_1172:\nmov eax, esi\nretn\nloc_1175:\nmov esi, 0\njmp short loc_1172", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // ecx\n unsigned int v2; // esi\n\n if ( a1 <= 0 )\n {\n return 0;\n }\n else\n {\n v1 = 1;\n v2 = 0;\n do\n v2 += a1 % v1++ == 0;\n while ( v1 != a1 + 1 );\n }\n return v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ntest edi, edi\njle short loc_1175\nlea r8d, [rdi+1]\nmov ecx, 1\nmov esi, 0\nloc_115F:\nmov eax, edi\ncdq\nidiv ecx\ncmp edx, 1\nadc esi, 0\nadd ecx, 1\ncmp ecx, r8d\njnz short loc_115F\nloc_1172:\nmov eax, esi\nretn\nloc_1175:\nmov esi, 0\njmp short loc_1172", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v1; // ecx\n unsigned int v2; // esi\n\n if ( a1 <= 0 )\n {\n return 0;\n }\n else\n {\n v1 = 1;\n v2 = 0;\n do\n v2 += a1 % v1++ == 0;\n while ( v1 != a1 + 1 );\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v1;\n unsigned int v2;\n if (a1 <= 0) {\n return 0;\n } else {\n v1 = 1;\n v2 = 0;\n do\n v2 += a1 % v1++ == 0;\n while (v1 != a1 + 1);\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n unsigned int v2;\n if (a1 <= 0) {\n return 0;\n } else {\n v1 = 1;\n v2 = 0;\n do\n v2 += a1 % v1++ == 0;\n while (v1 != a1 + 1);\n }\n return v2;\n}" + }, + { + "index": 97, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int key;\n\n int value;\n\n} Pair;\n\n\n\ntypedef struct {\n\n Pair *pairs;\n\n int size;\n\n int capacity;\n\n} Dictionary;\n\n\n\nvoid init_dictionary(Dictionary *dict) {\n\n dict->capacity = 10;\n\n dict->size = 0;\n\n dict->pairs = (Pair *)malloc(dict->capacity * sizeof(Pair));\n\n}\n\n\n\nvoid free_dictionary(Dictionary *dict) {\n\n free(dict->pairs);\n\n}\n\n\n\nvoid dictionary_add(Dictionary *dict, int key) {\n\n for (int i = 0; i < dict->size; i++) {\n\n if (dict->pairs[i].key == key) {\n\n dict->pairs[i].value += 1;\n\n return;\n\n }\n\n }\n\n if (dict->size == dict->capacity) {\n\n dict->capacity *= 2;\n\n dict->pairs = (Pair *)realloc(dict->pairs, dict->capacity * sizeof(Pair));\n\n }\n\n dict->pairs[dict->size].key = key;\n\n dict->pairs[dict->size].value = 1;\n\n dict->size += 1;\n\n}\n\n\n\n", + "func": "Dictionary func0(int list1[][4], int numLists) {\n Dictionary dict;\n init_dictionary(&dict);\n for (int i = 0; i < numLists; i++) {\n for (int j = 0; j < 4; j++) {\n dictionary_add(&dict, list1[i][j]);\n }\n }\n return dict;\n}", + "test": "int main() {\n\n int list1[3][4] = {{1, 2, 3, 2}, {4, 5, 6, 2}, {7, 8, 9, 5}};\n\n Dictionary result1 = func0(list1, 3);\n\n assert(result1.size == 9);\n\n assert(result1.pairs[1].value == 3);\n\n assert(result1.pairs[4].value == 2);\n\n\n\n int list2[3][4] = {{1, 2, 3, 4}, {5, 6, 7, 8}, {9, 10, 11, 12}};\n\n Dictionary result2 = func0(list2, 3);\n\n assert(result2.size == 12);\n\n for (int i = 0; i < result2.size; i++) {\n\n assert(result2.pairs[i].value == 1);\n\n }\n\n\n\n int list3[3][4] = {{20, 30, 40, 17}, {18, 16, 14, 13}, {10, 20, 30, 40}};\n\n Dictionary result3 = func0(list3, 3);\n\n assert(result3.size == 9);\n\n assert(result3.pairs[0].value == 2);\n\n assert(result3.pairs[1].value == 2);\n\n assert(result3.pairs[2].value == 2);\n\n\n\n free_dictionary(&result1);\n\n free_dictionary(&result2);\n\n free_dictionary(&result3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x40,%rsp\nmov %rdi,-0x38(%rbp)\nmov %esi,-0x3c(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea -0x20(%rbp),%rax\nmov %rax,%rdi\ncallq 11c9 \nmovl $0x0,-0x28(%rbp)\njmp 13c1 \nmovl $0x0,-0x24(%rbp)\njmp 13b7 \nmov -0x28(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x38(%rbp),%rax\nadd %rax,%rdx\nmov -0x24(%rbp),%eax\ncltq\nmov (%rdx,%rax,4),%edx\nlea -0x20(%rbp),%rax\nmov %edx,%esi\nmov %rax,%rdi\ncallq 1233 \naddl $0x1,-0x24(%rbp)\ncmpl $0x3,-0x24(%rbp)\njle 138a \naddl $0x1,-0x28(%rbp)\nmov -0x28(%rbp),%eax\ncmp -0x3c(%rbp),%eax\njl 1381 \nmov -0x20(%rbp),%rax\nmov -0x18(%rbp),%rdx\nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 13e5 \ncallq 10a0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [rbp+var_20]\nmov rdi, rax\ncall init_dictionary\nmov [rbp+var_28], 0\njmp short loc_13C1\nloc_1381:\nmov [rbp+var_24], 0\njmp short loc_13B7\nloc_138A:\nmov eax, [rbp+var_28]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_38]\nadd rdx, rax\nmov eax, [rbp+var_24]\ncdqe\nmov edx, [rdx+rax*4]\nlea rax, [rbp+var_20]\nmov esi, edx\nmov rdi, rax\ncall dictionary_add\nadd [rbp+var_24], 1\nloc_13B7:\ncmp [rbp+var_24], 3\njle short loc_138A\nadd [rbp+var_28], 1\nloc_13C1:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_3C]\njl short loc_1381\nmov rax, [rbp+var_20]\nmov rdx, [rbp+var_18]\nmov rcx, [rbp+var_8]\nsub rcx, fs:28h\njz short locret_13E5\ncall ___stack_chk_fail\nlocret_13E5:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-28h]\n int j; // [rsp+1Ch] [rbp-24h]\n _QWORD v5[4]; // [rsp+20h] [rbp-20h] BYREF\n\n v5[3] = __readfsqword(0x28u);\n init_dictionary(v5);\n for ( i = 0; i < a2; ++i )\n {\n for ( j = 0; j <= 3; ++j )\n dictionary_add(v5, *(unsigned int *)(a1 + 16LL * i + 4LL * j));\n }\n return v5[0];\n}", + "ida_strip_asm": "sub_134A:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [rbp+var_20]\nmov rdi, rax\ncall sub_11C9\nmov [rbp+var_28], 0\njmp short loc_13C1\nloc_1381:\nmov [rbp+var_24], 0\njmp short loc_13B7\nloc_138A:\nmov eax, [rbp+var_28]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_38]\nadd rdx, rax\nmov eax, [rbp+var_24]\ncdqe\nmov edx, [rdx+rax*4]\nlea rax, [rbp+var_20]\nmov esi, edx\nmov rdi, rax\ncall sub_1233\nadd [rbp+var_24], 1\nloc_13B7:\ncmp [rbp+var_24], 3\njle short loc_138A\nadd [rbp+var_28], 1\nloc_13C1:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_3C]\njl short loc_1381\nmov rax, [rbp+var_20]\nmov rdx, [rbp+var_18]\nmov rcx, [rbp+var_8]\nsub rcx, fs:28h\njz short locret_13E5\ncall ___stack_chk_fail\nlocret_13E5:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_134A(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-28h]\n int j; // [rsp+1Ch] [rbp-24h]\n _QWORD v5[4]; // [rsp+20h] [rbp-20h] BYREF\n\n v5[3] = __readfsqword(0x28u);\n sub_11C9(v5);\n for ( i = 0; i < a2; ++i )\n {\n for ( j = 0; j <= 3; ++j )\n sub_1233(v5, *(unsigned int *)(a1 + 16LL * i + 4LL * j));\n }\n return v5[0];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_134A(long long a1, int a2) {\n int i;\n int j;\n uint64_t v5[4];\n v5[3] = __readfsqword(40u);\n sub_11C9(v5);\n for (i = 0; i < a2; ++i) {\n for (j = 0; j <= 3; ++j)\n sub_1233(v5, *(unsigned int *)(a1 + 16LL * i + 4LL * j));\n }\n return v5[0];\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int i;\n int j;\n uint64_t v5[4];\n v5[3] = __readfsqword(40u);\n init_dictionary(v5);\n for (i = 0; i < a2; ++i) {\n for (j = 0; j <= 3; ++j)\n dictionary_add(v5, *(unsigned int *)(a1 + 16LL * i + 4LL * j));\n }\n return v5[0];\n}" + }, + { + "index": 97, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int key;\n\n int value;\n\n} Pair;\n\n\n\ntypedef struct {\n\n Pair *pairs;\n\n int size;\n\n int capacity;\n\n} Dictionary;\n\n\n\nvoid init_dictionary(Dictionary *dict) {\n\n dict->capacity = 10;\n\n dict->size = 0;\n\n dict->pairs = (Pair *)malloc(dict->capacity * sizeof(Pair));\n\n}\n\n\n\nvoid free_dictionary(Dictionary *dict) {\n\n free(dict->pairs);\n\n}\n\n\n\nvoid dictionary_add(Dictionary *dict, int key) {\n\n for (int i = 0; i < dict->size; i++) {\n\n if (dict->pairs[i].key == key) {\n\n dict->pairs[i].value += 1;\n\n return;\n\n }\n\n }\n\n if (dict->size == dict->capacity) {\n\n dict->capacity *= 2;\n\n dict->pairs = (Pair *)realloc(dict->pairs, dict->capacity * sizeof(Pair));\n\n }\n\n dict->pairs[dict->size].key = key;\n\n dict->pairs[dict->size].value = 1;\n\n dict->size += 1;\n\n}\n\n\n\n", + "func": "Dictionary func0(int list1[][4], int numLists) {\n Dictionary dict;\n init_dictionary(&dict);\n for (int i = 0; i < numLists; i++) {\n for (int j = 0; j < 4; j++) {\n dictionary_add(&dict, list1[i][j]);\n }\n }\n return dict;\n}", + "test": "int main() {\n\n int list1[3][4] = {{1, 2, 3, 2}, {4, 5, 6, 2}, {7, 8, 9, 5}};\n\n Dictionary result1 = func0(list1, 3);\n\n assert(result1.size == 9);\n\n assert(result1.pairs[1].value == 3);\n\n assert(result1.pairs[4].value == 2);\n\n\n\n int list2[3][4] = {{1, 2, 3, 4}, {5, 6, 7, 8}, {9, 10, 11, 12}};\n\n Dictionary result2 = func0(list2, 3);\n\n assert(result2.size == 12);\n\n for (int i = 0; i < result2.size; i++) {\n\n assert(result2.pairs[i].value == 1);\n\n }\n\n\n\n int list3[3][4] = {{20, 30, 40, 17}, {18, 16, 14, 13}, {10, 20, 30, 40}};\n\n Dictionary result3 = func0(list3, 3);\n\n assert(result3.size == 9);\n\n assert(result3.pairs[0].value == 2);\n\n assert(result3.pairs[1].value == 2);\n\n assert(result3.pairs[2].value == 2);\n\n\n\n free_dictionary(&result1);\n\n free_dictionary(&result2);\n\n free_dictionary(&result3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x28,%rsp\nmov %rdi,%r12\nmov %esi,%ebx\nmov %fs:0x28,%rax\nmov %rax,0x18(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\ncallq 11c9 \ntest %ebx,%ebx\njle 12e9 \nlea 0x10(%r12),%rbp\nlea -0x1(%rbx),%eax\nshl $0x4,%rax\nlea 0x20(%r12,%rax,1),%r13\nmov %rsp,%r12\njmp 12d0 \nadd $0x10,%rbp\ncmp %r13,%rbp\nje 12e9 \nlea -0x10(%rbp),%rbx\nmov (%rbx),%esi\nmov %r12,%rdi\ncallq 1203 \nadd $0x4,%rbx\ncmp %rbp,%rbx\njne 12d4 \njmp 12c7 \nmov (%rsp),%rax\nmov 0x8(%rsp),%rdx\nmov 0x18(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 130d \nadd $0x28,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\ncallq 10a0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov rbp, rdi\nmov ebx, esi\nmov rax, fs:28h\nmov [rsp+48h+var_30], rax\nxor eax, eax\nmov rdi, rsp\ncall init_dictionary\ntest ebx, ebx\njle short loc_12E6\nadd rbp, 10h\nmovsxd rbx, ebx\nshl rbx, 4\nlea r13, [rbx+rbp]\nmov r12, rsp\njmp short loc_12CD\nloc_12C4:\nadd rbp, 10h\ncmp rbp, r13\njz short loc_12E6\nloc_12CD:\nlea rbx, [rbp-10h]\nloc_12D1:\nmov esi, [rbx]\nmov rdi, r12\ncall dictionary_add\nadd rbx, 4\ncmp rbx, rbp\njnz short loc_12D1\njmp short loc_12C4\nloc_12E6:\nmov rax, [rsp+48h+var_48]\nmov rdx, [rsp+48h+var_40]\nmov rcx, [rsp+48h+var_30]\nsub rcx, fs:28h\njnz short loc_130A\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_130A:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int *v2; // rbp\n unsigned int *v3; // rbx\n _QWORD v5[9]; // [rsp+0h] [rbp-48h] BYREF\n\n v5[3] = __readfsqword(0x28u);\n init_dictionary(v5);\n if ( a2 > 0 )\n {\n v2 = (unsigned int *)(a1 + 16);\n do\n {\n v3 = v2 - 4;\n do\n dictionary_add(v5, *v3++);\n while ( v3 != v2 );\n v2 += 4;\n }\n while ( v2 != (unsigned int *)(16LL * a2 + a1 + 16) );\n }\n return v5[0];\n}", + "ida_strip_asm": "sub_1281:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov rbp, rdi\nmov ebx, esi\nmov rax, fs:28h\nmov [rsp+48h+var_30], rax\nxor eax, eax\nmov rdi, rsp\ncall sub_11C9\ntest ebx, ebx\njle short loc_12E6\nadd rbp, 10h\nmovsxd rbx, ebx\nshl rbx, 4\nlea r13, [rbx+rbp]\nmov r12, rsp\njmp short loc_12CD\nloc_12C4:\nadd rbp, 10h\ncmp rbp, r13\njz short loc_12E6\nloc_12CD:\nlea rbx, [rbp-10h]\nloc_12D1:\nmov esi, [rbx]\nmov rdi, r12\ncall sub_1203\nadd rbx, 4\ncmp rbx, rbp\njnz short loc_12D1\njmp short loc_12C4\nloc_12E6:\nmov rax, [rsp+48h+var_48]\nmov rdx, [rsp+48h+var_40]\nmov rcx, [rsp+48h+var_30]\nsub rcx, fs:28h\njnz short loc_130A\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_130A:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1281(__int64 a1, int a2)\n{\n unsigned int *v2; // rbp\n unsigned int *v3; // rbx\n _QWORD v5[9]; // [rsp+0h] [rbp-48h] BYREF\n\n v5[3] = __readfsqword(0x28u);\n sub_11C9(v5);\n if ( a2 > 0 )\n {\n v2 = (unsigned int *)(a1 + 16);\n do\n {\n v3 = v2 - 4;\n do\n sub_1203(v5, *v3++);\n while ( v3 != v2 );\n v2 += 4;\n }\n while ( v2 != (unsigned int *)(16LL * a2 + a1 + 16) );\n }\n return v5[0];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1281(long long a1, int a2) {\n unsigned int *v2;\n unsigned int *v3;\n uint64_t v5[9];\n v5[3] = __readfsqword(40u);\n sub_11C9(v5);\n if (a2 > 0) {\n v2 = (unsigned int *)(a1 + 16);\n do {\n v3 = v2 - 4;\n do\n sub_1203(v5, *v3++);\n while (v3 != v2);\n v2 += 4;\n } while (v2 != (unsigned int *)(16LL * a2 + a1 + 16));\n }\n return v5[0];\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int *v2;\n unsigned int *v3;\n uint64_t v5[9];\n v5[3] = __readfsqword(40u);\n init_dictionary(v5);\n if (a2 > 0) {\n v2 = (unsigned int *)(a1 + 16);\n do {\n v3 = v2 - 4;\n do\n dictionary_add(v5, *v3++);\n while (v3 != v2);\n v2 += 4;\n } while (v2 != (unsigned int *)(16LL * a2 + a1 + 16));\n }\n return v5[0];\n}" + }, + { + "index": 97, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int key;\n\n int value;\n\n} Pair;\n\n\n\ntypedef struct {\n\n Pair *pairs;\n\n int size;\n\n int capacity;\n\n} Dictionary;\n\n\n\nvoid init_dictionary(Dictionary *dict) {\n\n dict->capacity = 10;\n\n dict->size = 0;\n\n dict->pairs = (Pair *)malloc(dict->capacity * sizeof(Pair));\n\n}\n\n\n\nvoid free_dictionary(Dictionary *dict) {\n\n free(dict->pairs);\n\n}\n\n\n\nvoid dictionary_add(Dictionary *dict, int key) {\n\n for (int i = 0; i < dict->size; i++) {\n\n if (dict->pairs[i].key == key) {\n\n dict->pairs[i].value += 1;\n\n return;\n\n }\n\n }\n\n if (dict->size == dict->capacity) {\n\n dict->capacity *= 2;\n\n dict->pairs = (Pair *)realloc(dict->pairs, dict->capacity * sizeof(Pair));\n\n }\n\n dict->pairs[dict->size].key = key;\n\n dict->pairs[dict->size].value = 1;\n\n dict->size += 1;\n\n}\n\n\n\n", + "func": "Dictionary func0(int list1[][4], int numLists) {\n Dictionary dict;\n init_dictionary(&dict);\n for (int i = 0; i < numLists; i++) {\n for (int j = 0; j < 4; j++) {\n dictionary_add(&dict, list1[i][j]);\n }\n }\n return dict;\n}", + "test": "int main() {\n\n int list1[3][4] = {{1, 2, 3, 2}, {4, 5, 6, 2}, {7, 8, 9, 5}};\n\n Dictionary result1 = func0(list1, 3);\n\n assert(result1.size == 9);\n\n assert(result1.pairs[1].value == 3);\n\n assert(result1.pairs[4].value == 2);\n\n\n\n int list2[3][4] = {{1, 2, 3, 4}, {5, 6, 7, 8}, {9, 10, 11, 12}};\n\n Dictionary result2 = func0(list2, 3);\n\n assert(result2.size == 12);\n\n for (int i = 0; i < result2.size; i++) {\n\n assert(result2.pairs[i].value == 1);\n\n }\n\n\n\n int list3[3][4] = {{20, 30, 40, 17}, {18, 16, 14, 13}, {10, 20, 30, 40}};\n\n Dictionary result3 = func0(list3, 3);\n\n assert(result3.size == 9);\n\n assert(result3.pairs[0].value == 2);\n\n assert(result3.pairs[1].value == 2);\n\n assert(result3.pairs[2].value == 2);\n\n\n\n free_dictionary(&result1);\n\n free_dictionary(&result2);\n\n free_dictionary(&result3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\nmov %rdi,%r12\nmov $0x50,%edi\npush %rbp\npush %rbx\nmov %esi,%ebx\nsub $0x28,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x18(%rsp)\nxor %eax,%eax\nmovabs $0xa00000000,%rax\nmov %rax,0x8(%rsp)\ncallq 10c0 \nmov %rax,(%rsp)\ntest %ebx,%ebx\njle 1650 \nlea -0x1(%rbx),%eax\nlea 0x10(%r12),%rbp\nshl $0x4,%rax\nlea 0x20(%r12,%rax,1),%r13\nmov %rsp,%r12\nnopl 0x0(%rax,%rax,1)\nlea -0x10(%rbp),%rbx\nmov (%rbx),%esi\nmov %r12,%rdi\nadd $0x4,%rbx\ncallq 1530 \ncmp %rbp,%rbx\njne 1634 \nadd $0x10,%rbp\ncmp %r13,%rbp\njne 1630 \nmov 0x18(%rsp),%rcx\nxor %fs:0x28,%rcx\nmov (%rsp),%rax\nmov 0x8(%rsp),%rdx\njne 1674 \nadd $0x28,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\ncallq 10a0 <__stack_chk_fail@plt>\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\nmov rbp, rdi\nmov edi, 50h ; 'P'; size\npush rbx\nmovsxd rbx, esi\nsub rsp, 28h\nmov rax, fs:28h\nmov [rsp+48h+var_30], rax\nmov rax, 0A00000000h\nmov [rsp+48h+var_40], rax\ncall _malloc\nmov [rsp+48h+var_48], rax\ntest ebx, ebx\njle short loc_15A8\nadd rbp, 10h\nshl rbx, 4\nmov r12, rsp\nlea r13, [rbx+rbp]\nnop word ptr [rax+rax+00h]\nloc_1588:\nlea rbx, [rbp-10h]\nloc_158C:\nmov esi, [rbx]\nmov rdi, r12\nadd rbx, 4\ncall dictionary_add\ncmp rbx, rbp\njnz short loc_158C\nadd rbp, 10h\ncmp rbp, r13\njnz short loc_1588\nloc_15A8:\nmov rax, [rsp+48h+var_48]\nmov rdx, [rsp+48h+var_40]\nmov rcx, [rsp+48h+var_30]\nsub rcx, fs:28h\njnz short loc_15CC\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_15CC:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int *v2; // rbp\n __int64 v3; // r13\n unsigned int *v4; // rbx\n __int64 v5; // rsi\n _QWORD v7[9]; // [rsp+0h] [rbp-48h] BYREF\n\n v7[3] = __readfsqword(0x28u);\n v7[1] = 0xA00000000LL;\n v7[0] = malloc(0x50uLL);\n if ( a2 > 0 )\n {\n v2 = (unsigned int *)(a1 + 16);\n v3 = 16LL * a2 + a1 + 16;\n do\n {\n v4 = v2 - 4;\n do\n {\n v5 = *v4++;\n dictionary_add(v7, v5);\n }\n while ( v4 != v2 );\n v2 += 4;\n }\n while ( v2 != (unsigned int *)v3 );\n }\n return v7[0];\n}", + "ida_strip_asm": "sub_1530:\nendbr64\npush r13\npush r12\npush rbp\nmov rbp, rdi\nmov edi, 50h ; 'P'; size\npush rbx\nmovsxd rbx, esi\nsub rsp, 28h\nmov rax, fs:28h\nmov [rsp+48h+var_30], rax\nmov rax, 0A00000000h\nmov [rsp+48h+var_40], rax\ncall _malloc\nmov [rsp+48h+var_48], rax\ntest ebx, ebx\njle short loc_15A8\nadd rbp, 10h\nshl rbx, 4\nmov r12, rsp\nlea r13, [rbx+rbp]\nnop word ptr [rax+rax+00h]\nloc_1588:\nlea rbx, [rbp-10h]\nloc_158C:\nmov esi, [rbx]\nmov rdi, r12\nadd rbx, 4\ncall sub_14A0\ncmp rbx, rbp\njnz short loc_158C\nadd rbp, 10h\ncmp rbp, r13\njnz short loc_1588\nloc_15A8:\nmov rax, [rsp+48h+var_48]\nmov rdx, [rsp+48h+var_40]\nmov rcx, [rsp+48h+var_30]\nsub rcx, fs:28h\njnz short loc_15CC\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_15CC:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1530(__int64 a1, int a2)\n{\n unsigned int *v2; // rbp\n __int64 v3; // r13\n unsigned int *v4; // rbx\n __int64 v5; // rsi\n _QWORD v7[9]; // [rsp+0h] [rbp-48h] BYREF\n\n v7[3] = __readfsqword(0x28u);\n v7[1] = 0xA00000000LL;\n v7[0] = malloc(0x50uLL);\n if ( a2 > 0 )\n {\n v2 = (unsigned int *)(a1 + 16);\n v3 = 16LL * a2 + a1 + 16;\n do\n {\n v4 = v2 - 4;\n do\n {\n v5 = *v4++;\n sub_14A0(v7, v5);\n }\n while ( v4 != v2 );\n v2 += 4;\n }\n while ( v2 != (unsigned int *)v3 );\n }\n return v7[0];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1530(long long a1, int a2) {\n unsigned int *v2;\n long long v3;\n unsigned int *v4;\n long long v5;\n uint64_t v7[9];\n v7[3] = __readfsqword(40u);\n v7[1] = 42949672960LL;\n v7[0] = malloc(80uLL);\n if (a2 > 0) {\n v2 = (unsigned int *)(a1 + 16);\n v3 = 16LL * a2 + a1 + 16;\n do {\n v4 = v2 - 4;\n do {\n v5 = *v4++;\n sub_14A0(v7, v5);\n } while (v4 != v2);\n v2 += 4;\n } while (v2 != (unsigned int *)v3);\n }\n return v7[0];\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int *v2;\n long long v3;\n unsigned int *v4;\n long long v5;\n uint64_t v7[9];\n v7[3] = __readfsqword(40u);\n v7[1] = 42949672960LL;\n v7[0] = malloc(80uLL);\n if (a2 > 0) {\n v2 = (unsigned int *)(a1 + 16);\n v3 = 16LL * a2 + a1 + 16;\n do {\n v4 = v2 - 4;\n do {\n v5 = *v4++;\n dictionary_add(v7, v5);\n } while (v4 != v2);\n v2 += 4;\n } while (v2 != (unsigned int *)v3);\n }\n return v7[0];\n}" + }, + { + "index": 97, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int key;\n\n int value;\n\n} Pair;\n\n\n\ntypedef struct {\n\n Pair *pairs;\n\n int size;\n\n int capacity;\n\n} Dictionary;\n\n\n\nvoid init_dictionary(Dictionary *dict) {\n\n dict->capacity = 10;\n\n dict->size = 0;\n\n dict->pairs = (Pair *)malloc(dict->capacity * sizeof(Pair));\n\n}\n\n\n\nvoid free_dictionary(Dictionary *dict) {\n\n free(dict->pairs);\n\n}\n\n\n\nvoid dictionary_add(Dictionary *dict, int key) {\n\n for (int i = 0; i < dict->size; i++) {\n\n if (dict->pairs[i].key == key) {\n\n dict->pairs[i].value += 1;\n\n return;\n\n }\n\n }\n\n if (dict->size == dict->capacity) {\n\n dict->capacity *= 2;\n\n dict->pairs = (Pair *)realloc(dict->pairs, dict->capacity * sizeof(Pair));\n\n }\n\n dict->pairs[dict->size].key = key;\n\n dict->pairs[dict->size].value = 1;\n\n dict->size += 1;\n\n}\n\n\n\n", + "func": "Dictionary func0(int list1[][4], int numLists) {\n Dictionary dict;\n init_dictionary(&dict);\n for (int i = 0; i < numLists; i++) {\n for (int j = 0; j < 4; j++) {\n dictionary_add(&dict, list1[i][j]);\n }\n }\n return dict;\n}", + "test": "int main() {\n\n int list1[3][4] = {{1, 2, 3, 2}, {4, 5, 6, 2}, {7, 8, 9, 5}};\n\n Dictionary result1 = func0(list1, 3);\n\n assert(result1.size == 9);\n\n assert(result1.pairs[1].value == 3);\n\n assert(result1.pairs[4].value == 2);\n\n\n\n int list2[3][4] = {{1, 2, 3, 4}, {5, 6, 7, 8}, {9, 10, 11, 12}};\n\n Dictionary result2 = func0(list2, 3);\n\n assert(result2.size == 12);\n\n for (int i = 0; i < result2.size; i++) {\n\n assert(result2.pairs[i].value == 1);\n\n }\n\n\n\n int list3[3][4] = {{20, 30, 40, 17}, {18, 16, 14, 13}, {10, 20, 30, 40}};\n\n Dictionary result3 = func0(list3, 3);\n\n assert(result3.size == 9);\n\n assert(result3.pairs[0].value == 2);\n\n assert(result3.pairs[1].value == 2);\n\n assert(result3.pairs[2].value == 2);\n\n\n\n free_dictionary(&result1);\n\n free_dictionary(&result2);\n\n free_dictionary(&result3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\nmov %rdi,%rbp\nmov $0x50,%edi\npush %rbx\nmov %esi,%ebx\nsub $0x8,%rsp\ncallq 10c0 \nmov %rax,%rdi\ntest %ebx,%ebx\njle 1674 \nlea -0x1(%rbx),%eax\nlea 0x10(%rbp),%r13\nmov $0xa,%r14d\nshl $0x4,%rax\nlea 0x20(%rbp,%rax,1),%r15\nxor %ebp,%ebp\nnopl 0x0(%rax)\nlea -0x10(%r13),%rbx\nmov (%rbx),%r12d\ntest %ebp,%ebp\nje 1640 \nlea -0x1(%rbp),%eax\nmov %rdi,%rdx\nlea 0x8(%rdi,%rax,8),%rax\njmp 1609 \nadd $0x8,%rdx\ncmp %rax,%rdx\nje 1640 \ncmp (%rdx),%r12d\njne 1600 \naddl $0x1,0x4(%rdx)\nadd $0x4,%rbx\ncmp %r13,%rbx\njne 15ec \nadd $0x10,%r13\ncmp %r15,%r13\njne 15e8 \nadd $0x8,%rsp\nshl $0x20,%r14\nmov %ebp,%edx\nmov %rdi,%rax\npop %rbx\nor %r14,%rdx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\ncmp %ebp,%r14d\nje 1660 \nmovslq %ebp,%rax\nadd $0x1,%ebp\nlea (%rdi,%rax,8),%rax\nmov %r12d,(%rax)\nmovl $0x1,0x4(%rax)\njmp 1612 \nnopl 0x0(%rax,%rax,1)\nadd %r14d,%r14d\nmovslq %r14d,%rsi\nshl $0x3,%rsi\ncallq 10d0 \nmov %rax,%rdi\njmp 1645 \nmov $0xa,%r14d\nxor %ebp,%ebp\njmp 1624 \nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14, rdi\nmov edi, 50h ; 'P'; size\npush r13\npush r12\npush rbp\npush rbx\nmov ebx, esi\nsub rsp, 18h\ncall _malloc\nmov rdi, rax; ptr\ntest ebx, ebx\njle loc_167E\nmovsxd rcx, ebx\nadd r14, 10h\nmov r15d, 0Ah\nxor r12d, r12d\nshl rcx, 4\nadd rcx, r14\nnop dword ptr [rax+rax+00h]\nloc_15D8:\nlea rbp, [r14-10h]\nloc_15DC:\nmov ebx, [rbp+0]\nmovsxd r13, r12d\ntest r12d, r12d\njle short loc_1640\nmovsxd r13, r12d\nmov rax, rdi\nlea rdx, [rdi+r13*8]\njmp short loc_1601\nloc_15F8:\nadd rax, 8\ncmp rdx, rax\njz short loc_1640\nloc_1601:\ncmp ebx, [rax]\njnz short loc_15F8\nadd dword ptr [rax+4], 1\nloc_1609:\nadd rbp, 4\ncmp rbp, r14\njnz short loc_15DC\nadd r14, 10h\ncmp r14, rcx\njnz short loc_15D8\nloc_161B:\nadd rsp, 18h\nshl r15, 20h\nmov edx, r12d\nmov rax, rdi\npop rbx\nor rdx, r15\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1640:\ncmp r15d, r12d\njz short loc_1660\nloc_1645:\nlea rax, [rdi+r13*8]\nadd r12d, 1\nmov [rax], ebx\nmov dword ptr [rax+4], 1\njmp short loc_1609\nloc_1660:\nadd r15d, r15d\nmov [rsp+48h+var_40], rcx\nmovsxd rsi, r15d\nshl rsi, 3; size\ncall _realloc\nmov rcx, [rsp+48h+var_40]\nmov rdi, rax\njmp short loc_1645\nloc_167E:\nmov r15d, 0Ah\nxor r12d, r12d\njmp short loc_161B", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2)\n{\n char *v3; // rdi\n int *v4; // r14\n int v5; // r15d\n int v6; // r12d\n int *v7; // rcx\n int *v8; // rbp\n int v9; // ebx\n __int64 v10; // r13\n char *v11; // rax\n char *v13; // rax\n char *v14; // rax\n int *v15; // [rsp+8h] [rbp-40h]\n\n v3 = (char *)malloc(0x50uLL);\n if ( a2 > 0 )\n {\n v4 = (int *)(a1 + 16);\n v5 = 10;\n v6 = 0;\n v7 = &v4[4 * a2];\n do\n {\n v8 = v4 - 4;\n do\n {\n v9 = *v8;\n v10 = v6;\n if ( v6 <= 0 )\n {\nLABEL_12:\n if ( v5 == v6 )\n {\n v5 *= 2;\n v15 = v7;\n v14 = (char *)realloc(v3, 8LL * v5);\n v7 = v15;\n v3 = v14;\n }\n v13 = &v3[8 * v10];\n ++v6;\n *(_DWORD *)v13 = v9;\n *((_DWORD *)v13 + 1) = 1;\n }\n else\n {\n v10 = v6;\n v11 = v3;\n while ( v9 != *(_DWORD *)v11 )\n {\n v11 += 8;\n if ( &v3[8 * v6] == v11 )\n goto LABEL_12;\n }\n ++*((_DWORD *)v11 + 1);\n }\n ++v8;\n }\n while ( v8 != v4 );\n v4 += 4;\n }\n while ( v4 != v7 );\n }\n return v3;\n}", + "ida_strip_asm": "sub_1590:\nendbr64\npush r15\npush r14\nmov r14, rdi\nmov edi, 50h ; 'P'; size\npush r13\npush r12\npush rbp\npush rbx\nmov ebx, esi\nsub rsp, 18h\ncall _malloc\nmov rdi, rax; ptr\ntest ebx, ebx\njle loc_167E\nmovsxd rcx, ebx\nadd r14, 10h\nmov r15d, 0Ah\nxor r12d, r12d\nshl rcx, 4\nadd rcx, r14\nnop dword ptr [rax+rax+00h]\nloc_15D8:\nlea rbp, [r14-10h]\nloc_15DC:\nmov ebx, [rbp+0]\nmovsxd r13, r12d\ntest r12d, r12d\njle short loc_1640\nmovsxd r13, r12d\nmov rax, rdi\nlea rdx, [rdi+r13*8]\njmp short loc_1601\nloc_15F8:\nadd rax, 8\ncmp rdx, rax\njz short loc_1640\nloc_1601:\ncmp ebx, [rax]\njnz short loc_15F8\nadd dword ptr [rax+4], 1\nloc_1609:\nadd rbp, 4\ncmp rbp, r14\njnz short loc_15DC\nadd r14, 10h\ncmp r14, rcx\njnz short loc_15D8\nloc_161B:\nadd rsp, 18h\nshl r15, 20h\nmov edx, r12d\nmov rax, rdi\npop rbx\nor rdx, r15\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1640:\ncmp r15d, r12d\njz short loc_1660\nloc_1645:\nlea rax, [rdi+r13*8]\nadd r12d, 1\nmov [rax], ebx\nmov dword ptr [rax+4], 1\njmp short loc_1609\nloc_1660:\nadd r15d, r15d\nmov [rsp+48h+var_40], rcx\nmovsxd rsi, r15d\nshl rsi, 3; size\ncall _realloc\nmov rcx, [rsp+48h+var_40]\nmov rdi, rax\njmp short loc_1645\nloc_167E:\nmov r15d, 0Ah\nxor r12d, r12d\njmp short loc_161B", + "ida_strip_pseudo": "char *__fastcall sub_1590(__int64 a1, int a2)\n{\n char *v3; // rdi\n int *v4; // r14\n int v5; // r15d\n int v6; // r12d\n int *v7; // rcx\n int *v8; // rbp\n int v9; // ebx\n __int64 v10; // r13\n char *v11; // rax\n char *v13; // rax\n char *v14; // rax\n int *v15; // [rsp+8h] [rbp-40h]\n\n v3 = (char *)malloc(0x50uLL);\n if ( a2 > 0 )\n {\n v4 = (int *)(a1 + 16);\n v5 = 10;\n v6 = 0;\n v7 = &v4[4 * a2];\n do\n {\n v8 = v4 - 4;\n do\n {\n v9 = *v8;\n v10 = v6;\n if ( v6 <= 0 )\n {\nLABEL_12:\n if ( v5 == v6 )\n {\n v5 *= 2;\n v15 = v7;\n v14 = (char *)realloc(v3, 8LL * v5);\n v7 = v15;\n v3 = v14;\n }\n v13 = &v3[8 * v10];\n ++v6;\n *(_DWORD *)v13 = v9;\n *((_DWORD *)v13 + 1) = 1;\n }\n else\n {\n v10 = v6;\n v11 = v3;\n while ( v9 != *(_DWORD *)v11 )\n {\n v11 += 8;\n if ( &v3[8 * v6] == v11 )\n goto LABEL_12;\n }\n ++*((_DWORD *)v11 + 1);\n }\n ++v8;\n }\n while ( v8 != v4 );\n v4 += 4;\n }\n while ( v4 != v7 );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1590(long long a1, int a2) {\n char *v3;\n int *v4;\n int v5;\n int v6;\n int *v7;\n int *v8;\n int v9;\n long long v10;\n char *v11;\n char *v13;\n char *v14;\n int *v15;\n v3 = (char *)malloc(80uLL);\n if (a2 > 0) {\n v4 = (int *)(a1 + 16);\n v5 = 10;\n v6 = 0;\n v7 = &v4[4 * a2];\n do {\n v8 = v4 - 4;\n do {\n v9 = *v8;\n v10 = v6;\n if (v6 <= 0) {\n LABEL_12:\n if (v5 == v6) {\n v5 *= 2;\n v15 = v7;\n v14 = (char *)realloc(v3, 8LL * v5);\n v7 = v15;\n v3 = v14;\n }\n v13 = &v3[8 * v10];\n ++v6;\n *(uint32_t *)v13 = v9;\n *((uint32_t *)v13 + 1) = 1;\n } else {\n v10 = v6;\n v11 = v3;\n while (v9 != *(uint32_t *)v11) {\n v11 += 8;\n if (&v3[8 * v6] == v11) goto LABEL_12;\n }\n ++*((uint32_t *)v11 + 1);\n }\n ++v8;\n } while (v8 != v4);\n v4 += 4;\n } while (v4 != v7);\n }\n return v3;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2) {\n char *v3;\n int *v4;\n int v5;\n int v6;\n int *v7;\n int *v8;\n int v9;\n long long v10;\n char *v11;\n char *v13;\n char *v14;\n int *v15;\n v3 = (char *)malloc(80uLL);\n if (a2 > 0) {\n v4 = (int *)(a1 + 16);\n v5 = 10;\n v6 = 0;\n v7 = &v4[4 * a2];\n do {\n v8 = v4 - 4;\n do {\n v9 = *v8;\n v10 = v6;\n if (v6 <= 0) {\n LABEL_12:\n if (v5 == v6) {\n v5 *= 2;\n v15 = v7;\n v14 = (char *)realloc(v3, 8LL * v5);\n v7 = v15;\n v3 = v14;\n }\n v13 = &v3[8 * v10];\n ++v6;\n *(uint32_t *)v13 = v9;\n *((uint32_t *)v13 + 1) = 1;\n } else {\n v10 = v6;\n v11 = v3;\n while (v9 != *(uint32_t *)v11) {\n v11 += 8;\n if (&v3[8 * v6] == v11) goto LABEL_12;\n }\n ++*((uint32_t *)v11 + 1);\n }\n ++v8;\n } while (v8 != v4);\n v4 += 4;\n } while (v4 != v7);\n }\n return v3;\n}" + }, + { + "index": 98, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int numbers[], int size) {\n double total = 1;\n for (int i = 0; i < size; i++) {\n total *= numbers[i];\n }\n return total / size;\n}", + "test": "int main() {\n\n int arr1[] = {8, 2, 3, -1, 7};\n\n int arr2[] = {-10, -20, -30};\n\n int arr3[] = {19, 15, 18};\n\n\n\n assert(func0(arr1, 5) == -67.2);\n\n assert(func0(arr2, 3) == -2000.0);\n\n assert(func0(arr3, 3) == 1710.0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovsd 0xf18(%rip),%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 11ba \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncvtsi2sd %eax,%xmm0\nmovsd -0x8(%rbp),%xmm1\nmulsd %xmm1,%xmm0\nmovsd %xmm0,-0x8(%rbp)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 118e \ncvtsi2sdl -0x1c(%rbp),%xmm1\nmovsd -0x8(%rbp),%xmm0\ndivsd %xmm1,%xmm0\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmovsd xmm0, cs:qword_2078\nmovsd [rbp+var_8], xmm0\nmov [rbp+var_C], 0\njmp short loc_11BE\nloc_118E:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmovsd xmm1, [rbp+var_8]\nmulsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nadd [rbp+var_C], 1\nloc_11BE:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_118E\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_1C]\nmovsd xmm0, [rbp+var_8]\ndivsd xmm0, xmm1\npop rbp\nretn", + "ida_pseudo": "double __fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+10h] [rbp-Ch]\n double v4; // [rsp+14h] [rbp-8h]\n\n v4 = 1.0;\n for ( i = 0; i < a2; ++i )\n v4 = (double)*(int *)(4LL * i + a1) * v4;\n return v4 / (double)a2;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmovsd xmm0, cs:qword_2078\nmovsd [rbp+var_8], xmm0\nmov [rbp+var_C], 0\njmp short loc_11BE\nloc_118E:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmovsd xmm1, [rbp+var_8]\nmulsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nadd [rbp+var_C], 1\nloc_11BE:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_118E\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_1C]\nmovsd xmm0, [rbp+var_8]\ndivsd xmm0, xmm1\npop rbp\nretn", + "ida_strip_pseudo": "double __fastcall sub_1169(__int64 a1, int a2)\n{\n int i; // [rsp+10h] [rbp-Ch]\n double v4; // [rsp+14h] [rbp-8h]\n\n v4 = 1.0;\n for ( i = 0; i < a2; ++i )\n v4 = (double)*(int *)(4LL * i + a1) * v4;\n return v4 / (double)a2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1169(long long a1, int a2) {\n int i;\n double v4;\n v4 = 1.0;\n for (i = 0; i < a2; ++i) v4 = (double)*(int *)(4LL * i + a1) * v4;\n return v4 / (double)a2;\n}", + "ida_pseudo_norm": "double func0(long long a1, int a2) {\n int i;\n double v4;\n v4 = 1.0;\n for (i = 0; i < a2; ++i) v4 = (double)*(int *)(4LL * i + a1) * v4;\n return v4 / (double)a2;\n}" + }, + { + "index": 98, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int numbers[], int size) {\n double total = 1;\n for (int i = 0; i < size; i++) {\n total *= numbers[i];\n }\n return total / size;\n}", + "test": "int main() {\n\n int arr1[] = {8, 2, 3, -1, 7};\n\n int arr2[] = {-10, -20, -30};\n\n int arr3[] = {19, 15, 18};\n\n\n\n assert(func0(arr1, 5) == -67.2);\n\n assert(func0(arr2, 3) == -2000.0);\n\n assert(func0(arr3, 3) == 1710.0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11a6 \nmov %rdi,%rax\nlea -0x1(%rsi),%edx\nlea 0x4(%rdi,%rdx,4),%rdx\nmovsd 0xf14(%rip),%xmm0\npxor %xmm1,%xmm1\ncvtsi2sdl (%rax),%xmm1\nmulsd %xmm1,%xmm0\nadd $0x4,%rax\ncmp %rdx,%rax\njne 1184 \npxor %xmm1,%xmm1\ncvtsi2sd %esi,%xmm1\ndivsd %xmm1,%xmm0\nretq\nmovsd 0xeea(%rip),%xmm0\njmp 1199 \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11A5\nmov rax, rdi\nmovsxd rdx, esi\nlea rdx, [rdi+rdx*4]\nmovsd xmm0, cs:qword_2078\nloc_1183:\npxor xmm1, xmm1\ncvtsi2sd xmm1, dword ptr [rax]\nmulsd xmm0, xmm1\nadd rax, 4\ncmp rax, rdx\njnz short loc_1183\nloc_1198:\npxor xmm1, xmm1\ncvtsi2sd xmm1, esi\ndivsd xmm0, xmm1\nretn\nloc_11A5:\nmovsd xmm0, cs:qword_2078\njmp short loc_1198", + "ida_pseudo": "double __fastcall func0(int *a1, int a2)\n{\n int *v2; // rax\n double v3; // xmm0_8\n\n if ( a2 <= 0 )\n {\n v3 = 1.0;\n }\n else\n {\n v2 = a1;\n v3 = 1.0;\n do\n v3 = v3 * (double)*v2++;\n while ( v2 != &a1[a2] );\n }\n return v3 / (double)a2;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11A5\nmov rax, rdi\nmovsxd rdx, esi\nlea rdx, [rdi+rdx*4]\nmovsd xmm0, cs:qword_2078\nloc_1183:\npxor xmm1, xmm1\ncvtsi2sd xmm1, dword ptr [rax]\nmulsd xmm0, xmm1\nadd rax, 4\ncmp rax, rdx\njnz short loc_1183\nloc_1198:\npxor xmm1, xmm1\ncvtsi2sd xmm1, esi\ndivsd xmm0, xmm1\nretn\nloc_11A5:\nmovsd xmm0, cs:qword_2078\njmp short loc_1198", + "ida_strip_pseudo": "double __fastcall sub_1169(int *a1, int a2)\n{\n int *v2; // rax\n double v3; // xmm0_8\n\n if ( a2 <= 0 )\n {\n v3 = 1.0;\n }\n else\n {\n v2 = a1;\n v3 = 1.0;\n do\n v3 = v3 * (double)*v2++;\n while ( v2 != &a1[a2] );\n }\n return v3 / (double)a2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1169(int *a1, int a2) {\n int *v2;\n double v3;\n if (a2 <= 0) {\n v3 = 1.0;\n } else {\n v2 = a1;\n v3 = 1.0;\n do\n v3 = v3 * (double)*v2++;\n while (v2 != &a1[a2]);\n }\n return v3 / (double)a2;\n}", + "ida_pseudo_norm": "double func0(int *a1, int a2) {\n int *v2;\n double v3;\n if (a2 <= 0) {\n v3 = 1.0;\n } else {\n v2 = a1;\n v3 = 1.0;\n do\n v3 = v3 * (double)*v2++;\n while (v2 != &a1[a2]);\n }\n return v3 / (double)a2;\n}" + }, + { + "index": 99, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(int n) {\n static char binary[32];\n int index = 0;\n while (n > 0) {\n binary[index++] = (n % 2) + '0';\n n /= 2;\n }\n binary[index] = '\\0';\n int start = 0;\n int end = index - 1;\n while (start < end) {\n char temp = binary[start];\n binary[start] = binary[end];\n binary[end] = temp;\n start++;\n end--;\n }\n return binary;\n}", + "test": "int main() {\n\n assert(strcmp(func0(8), \"1000\") == 0);\n\n assert(strcmp(func0(18), \"10010\") == 0);\n\n assert(strcmp(func0(7), \"111\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 11b2 \nmov -0x14(%rbp),%eax\ncltd\nshr $0x1f,%edx\nadd %edx,%eax\nand $0x1,%eax\nsub %edx,%eax\nlea 0x30(%rax),%ecx\nmov -0xc(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0xc(%rbp)\ncltq\nlea 0x2ea0(%rip),%rdx\nmov %cl,(%rax,%rdx,1)\nmov -0x14(%rbp),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nmov %eax,-0x14(%rbp)\ncmpl $0x0,-0x14(%rbp)\njg 117d \nmov -0xc(%rbp),%eax\ncltq\nlea 0x2e7c(%rip),%rdx\nmovb $0x0,(%rax,%rdx,1)\nmovl $0x0,-0x8(%rbp)\nmov -0xc(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0x4(%rbp)\njmp 1227 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x2e5a(%rip),%rdx\nmovzbl (%rax,%rdx,1),%eax\nmov %al,-0xd(%rbp)\nmov -0x4(%rbp),%eax\ncltq\nlea 0x2e47(%rip),%rdx\nmovzbl (%rax,%rdx,1),%edx\nmov -0x8(%rbp),%eax\ncltq\nlea 0x2e37(%rip),%rcx\nmov %dl,(%rax,%rcx,1)\nmov -0x4(%rbp),%eax\ncltq\nlea 0x2e28(%rip),%rcx\nmovzbl -0xd(%rbp),%edx\nmov %dl,(%rax,%rcx,1)\naddl $0x1,-0x8(%rbp)\nsubl $0x1,-0x4(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x4(%rbp),%eax\njl 11da \nlea 0x2e0a(%rip),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_C], 0\njmp short loc_11B8\nloc_117D:\nmov edx, [rbp+var_14]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\nlea ecx, [rax+30h]\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\ncdqe\nlea rdx, binary_1\nmov [rax+rdx], cl\nmov eax, [rbp+var_14]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_14], eax\nloc_11B8:\ncmp [rbp+var_14], 0\njg short loc_117D\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, binary_1\nmov byte ptr [rax+rdx], 0\nmov [rbp+var_8], 0\nmov eax, [rbp+var_C]\nsub eax, 1\nmov [rbp+var_4], eax\njmp short loc_122D\nloc_11E0:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, binary_1\nmovzx eax, byte ptr [rax+rdx]\nmov [rbp+var_D], al\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, binary_1\nmovzx edx, byte ptr [rax+rdx]\nmov eax, [rbp+var_8]\ncdqe\nlea rcx, binary_1\nmov [rax+rcx], dl\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, binary_1\nmovzx edx, [rbp+var_D]\nmov [rax+rcx], dl\nadd [rbp+var_8], 1\nsub [rbp+var_4], 1\nloc_122D:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njl short loc_11E0\nlea rax, binary_1\npop rbp\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(int a1)\n{\n int v1; // eax\n char v4; // [rsp+7h] [rbp-Dh]\n int v5; // [rsp+8h] [rbp-Ch]\n int v6; // [rsp+Ch] [rbp-8h]\n int i; // [rsp+10h] [rbp-4h]\n\n v5 = 0;\n while ( a1 > 0 )\n {\n v1 = v5++;\n binary_1[v1] = a1 % 2 + 48;\n a1 /= 2;\n }\n binary_1[v5] = 0;\n v6 = 0;\n for ( i = v5 - 1; v6 < i; --i )\n {\n v4 = binary_1[v6];\n binary_1[v6] = binary_1[i];\n binary_1[i] = v4;\n ++v6;\n }\n return binary_1;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_C], 0\njmp short loc_11B8\nloc_117D:\nmov edx, [rbp+var_14]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\nlea ecx, [rax+30h]\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\ncdqe\nlea rdx, unk_4040\nmov [rax+rdx], cl\nmov eax, [rbp+var_14]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_14], eax\nloc_11B8:\ncmp [rbp+var_14], 0\njg short loc_117D\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, unk_4040\nmov byte ptr [rax+rdx], 0\nmov [rbp+var_8], 0\nmov eax, [rbp+var_C]\nsub eax, 1\nmov [rbp+var_4], eax\njmp short loc_122D\nloc_11E0:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, unk_4040\nmovzx eax, byte ptr [rax+rdx]\nmov [rbp+var_D], al\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, unk_4040\nmovzx edx, byte ptr [rax+rdx]\nmov eax, [rbp+var_8]\ncdqe\nlea rcx, unk_4040\nmov [rax+rcx], dl\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, unk_4040\nmovzx edx, [rbp+var_D]\nmov [rax+rcx], dl\nadd [rbp+var_8], 1\nsub [rbp+var_4], 1\nloc_122D:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njl short loc_11E0\nlea rax, unk_4040\npop rbp\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1169(int a1)\n{\n int v1; // eax\n char v4; // [rsp+7h] [rbp-Dh]\n int v5; // [rsp+8h] [rbp-Ch]\n int v6; // [rsp+Ch] [rbp-8h]\n int i; // [rsp+10h] [rbp-4h]\n\n v5 = 0;\n while ( a1 > 0 )\n {\n v1 = v5++;\n byte_4040[v1] = a1 % 2 + 48;\n a1 /= 2;\n }\n byte_4040[v5] = 0;\n v6 = 0;\n for ( i = v5 - 1; v6 < i; --i )\n {\n v4 = byte_4040[v6];\n byte_4040[v6] = byte_4040[i];\n byte_4040[i] = v4;\n ++v6;\n }\n return byte_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t* sub_1169(int a1) {\n int v1;\n char v4;\n int v5;\n int v6;\n int i;\n v5 = 0;\n while (a1 > 0) {\n v1 = v5++;\n byte_4040[v1] = a1 % 2 + 48;\n a1 /= 2;\n }\n byte_4040[v5] = 0;\n v6 = 0;\n for (i = v5 - 1; v6 < i; --i) {\n v4 = byte_4040[v6];\n byte_4040[v6] = byte_4040[i];\n byte_4040[i] = v4;\n ++v6;\n }\n return byte_4040;\n}", + "ida_pseudo_norm": "uint8_t* func0(int a1) {\n int v1;\n char v4;\n int v5;\n int v6;\n int i;\n v5 = 0;\n while (a1 > 0) {\n v1 = v5++;\n binary_1[v1] = a1 % 2 + 48;\n a1 /= 2;\n }\n binary_1[v5] = 0;\n v6 = 0;\n for (i = v5 - 1; v6 < i; --i) {\n v4 = binary_1[v6];\n binary_1[v6] = binary_1[i];\n binary_1[i] = v4;\n ++v6;\n }\n return binary_1;\n}" + }, + { + "index": 99, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(int n) {\n static char binary[32];\n int index = 0;\n while (n > 0) {\n binary[index++] = (n % 2) + '0';\n n /= 2;\n }\n binary[index] = '\\0';\n int start = 0;\n int end = index - 1;\n while (start < end) {\n char temp = binary[start];\n binary[start] = binary[end];\n binary[end] = temp;\n start++;\n end--;\n }\n return binary;\n}", + "test": "int main() {\n\n assert(strcmp(func0(8), \"1000\") == 0);\n\n assert(strcmp(func0(18), \"10010\") == 0);\n\n assert(strcmp(func0(7), \"111\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\njle 11d9 \nlea 0x2ee4(%rip),%rcx\nmov $0x0,%edx\nmov %edx,%r8d\nadd $0x1,%edx\nmov %edi,%esi\nshr $0x1f,%esi\nlea (%rdi,%rsi,1),%eax\nand $0x1,%eax\nsub %esi,%eax\nadd $0x30,%eax\nmov %al,(%rcx)\nmov %edi,%eax\nmov %edi,%esi\nshr $0x1f,%esi\nadd %esi,%edi\nsar %edi\nadd $0x1,%rcx\ncmp $0x1,%eax\njg 1161 \nmovslq %edx,%rdx\nlea 0x2ea9(%rip),%rax\nmovb $0x0,(%rax,%rdx,1)\ntest %r8d,%r8d\njle 11d1 \nmovslq %r8d,%rdx\nadd %rax,%rdx\nmov $0x0,%eax\nlea 0x2e8e(%rip),%rcx\nmovzbl (%rcx,%rax,1),%esi\nmovzbl (%rdx),%edi\nmov %dil,(%rcx,%rax,1)\nmov %sil,(%rdx)\nadd $0x1,%rax\nsub $0x1,%rdx\nmov %r8d,%esi\nsub %eax,%esi\ncmp %eax,%esi\njg 11b2 \nlea 0x2e68(%rip),%rax\nretq\nmovb $0x0,0x2e60(%rip)\njmp 11d1 \n", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njle loc_11F9\nlea rcx, binary_1\nmov edx, 0\nloc_1181:\nmov r8d, edx\nadd edx, 1\nmov esi, edi\nshr esi, 1Fh\nlea eax, [rdi+rsi]\nand eax, 1\nsub eax, esi\nadd eax, 30h ; '0'\nmov [rcx], al\nmov eax, edi\nmov esi, edi\nshr esi, 1Fh\nadd edi, esi\nsar edi, 1\nadd rcx, 1\ncmp eax, 1\njg short loc_1181\nmovsxd rdx, edx\nlea rax, binary_1\nmov byte ptr [rax+rdx], 0\ntest r8d, r8d\njle short loc_11F1\nmovsxd rdx, r8d\nadd rdx, rax\nmov eax, 0\nlea rcx, binary_1\nloc_11D2:\nmovzx esi, byte ptr [rcx+rax]\nmovzx edi, byte ptr [rdx]\nmov [rcx+rax], dil\nmov [rdx], sil\nadd rax, 1\nsub rdx, 1\nmov esi, r8d\nsub esi, eax\ncmp esi, eax\njg short loc_11D2\nloc_11F1:\nlea rax, binary_1\nretn\nloc_11F9:\nmov cs:binary_1, 0\njmp short loc_11F1", + "ida_pseudo": "char *__fastcall func0(int a1)\n{\n char *v1; // rcx\n int v2; // edx\n int v3; // r8d\n int v4; // eax\n char *v5; // rdx\n __int64 v6; // rax\n char v7; // si\n\n if ( a1 <= 0 )\n {\n binary_1[0] = 0;\n }\n else\n {\n v1 = binary_1;\n v2 = 0;\n do\n {\n v3 = v2++;\n *v1 = a1 % 2 + 48;\n v4 = a1;\n a1 /= 2;\n ++v1;\n }\n while ( v4 > 1 );\n binary_1[v2] = 0;\n if ( v3 > 0 )\n {\n v5 = &binary_1[v3];\n v6 = 0LL;\n do\n {\n v7 = binary_1[v6];\n binary_1[v6] = *v5;\n *v5 = v7;\n ++v6;\n --v5;\n }\n while ( v3 - (int)v6 > (int)v6 );\n }\n }\n return binary_1;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest edi, edi\njle loc_11F9\nlea rcx, byte_4040\nmov edx, 0\nloc_1181:\nmov r8d, edx\nadd edx, 1\nmov esi, edi\nshr esi, 1Fh\nlea eax, [rdi+rsi]\nand eax, 1\nsub eax, esi\nadd eax, 30h ; '0'\nmov [rcx], al\nmov eax, edi\nmov esi, edi\nshr esi, 1Fh\nadd edi, esi\nsar edi, 1\nadd rcx, 1\ncmp eax, 1\njg short loc_1181\nmovsxd rdx, edx\nlea rax, byte_4040\nmov byte ptr [rax+rdx], 0\ntest r8d, r8d\njle short loc_11F1\nmovsxd rdx, r8d\nadd rdx, rax\nmov eax, 0\nlea rcx, byte_4040\nloc_11D2:\nmovzx esi, byte ptr [rcx+rax]\nmovzx edi, byte ptr [rdx]\nmov [rcx+rax], dil\nmov [rdx], sil\nadd rax, 1\nsub rdx, 1\nmov esi, r8d\nsub esi, eax\ncmp esi, eax\njg short loc_11D2\nloc_11F1:\nlea rax, byte_4040\nretn\nloc_11F9:\nmov cs:byte_4040, 0\njmp short loc_11F1", + "ida_strip_pseudo": "char *__fastcall sub_1169(int a1)\n{\n char *v1; // rcx\n int v2; // edx\n int v3; // r8d\n int v4; // eax\n char *v5; // rdx\n __int64 v6; // rax\n char v7; // si\n\n if ( a1 <= 0 )\n {\n byte_4040[0] = 0;\n }\n else\n {\n v1 = byte_4040;\n v2 = 0;\n do\n {\n v3 = v2++;\n *v1 = a1 % 2 + 48;\n v4 = a1;\n a1 /= 2;\n ++v1;\n }\n while ( v4 > 1 );\n byte_4040[v2] = 0;\n if ( v3 > 0 )\n {\n v5 = &byte_4040[v3];\n v6 = 0LL;\n do\n {\n v7 = byte_4040[v6];\n byte_4040[v6] = *v5;\n *v5 = v7;\n ++v6;\n --v5;\n }\n while ( v3 - (int)v6 > (int)v6 );\n }\n }\n return byte_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1169(int a1) {\n char *v1;\n int v2;\n int v3;\n int v4;\n char *v5;\n long long v6;\n char v7;\n if (a1 <= 0) {\n byte_4040[0] = 0;\n } else {\n v1 = byte_4040;\n v2 = 0;\n do {\n v3 = v2++;\n *v1 = a1 % 2 + 48;\n v4 = a1;\n a1 /= 2;\n ++v1;\n } while (v4 > 1);\n byte_4040[v2] = 0;\n if (v3 > 0) {\n v5 = &byte_4040[v3];\n v6 = 0LL;\n do {\n v7 = byte_4040[v6];\n byte_4040[v6] = *v5;\n *v5 = v7;\n ++v6;\n --v5;\n } while (v3 - (int)v6 > (int)v6);\n }\n }\n return byte_4040;\n}", + "ida_pseudo_norm": "char *func0(int a1) {\n char *v1;\n int v2;\n int v3;\n int v4;\n char *v5;\n long long v6;\n char v7;\n if (a1 <= 0) {\n binary_1[0] = 0;\n } else {\n v1 = binary_1;\n v2 = 0;\n do {\n v3 = v2++;\n *v1 = a1 % 2 + 48;\n v4 = a1;\n a1 /= 2;\n ++v1;\n } while (v4 > 1);\n binary_1[v2] = 0;\n if (v3 > 0) {\n v5 = &binary_1[v3];\n v6 = 0LL;\n do {\n v7 = binary_1[v6];\n binary_1[v6] = *v5;\n *v5 = v7;\n ++v6;\n --v5;\n } while (v3 - (int)v6 > (int)v6);\n }\n }\n return binary_1;\n}" + }, + { + "index": 99, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(int n) {\n static char binary[32];\n int index = 0;\n while (n > 0) {\n binary[index++] = (n % 2) + '0';\n n /= 2;\n }\n binary[index] = '\\0';\n int start = 0;\n int end = index - 1;\n while (start < end) {\n char temp = binary[start];\n binary[start] = binary[end];\n binary[end] = temp;\n start++;\n end--;\n }\n return binary;\n}", + "test": "int main() {\n\n assert(strcmp(func0(8), \"1000\") == 0);\n\n assert(strcmp(func0(18), \"10010\") == 0);\n\n assert(strcmp(func0(7), \"111\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\njle 1350 \nlea 0x2d61(%rip),%rsi\nxor %r8d,%r8d\nmov %rsi,%rdx\nnopl (%rax)\nmov %edi,%eax\nadd $0x1,%rdx\nmov %r8d,%ecx\nand $0x1,%eax\nlea 0x1(%r8),%r8d\nadd $0x30,%eax\nmov %al,-0x1(%rdx)\nsar %edi\njne 12e8 \nmovslq %r8d,%r8\nmovb $0x0,(%rsi,%r8,1)\ntest %ecx,%ecx\nje 1340 \nmovslq %ecx,%rdx\nxor %eax,%eax\nadd %rsi,%rdx\nnopw %cs:0x0(%rax,%rax,1)\nmovzbl (%rsi,%rax,1),%edi\nmovzbl (%rdx),%r8d\nsub $0x1,%rdx\nmov %r8b,(%rsi,%rax,1)\nadd $0x1,%rax\nmov %dil,0x1(%rdx)\nmov %ecx,%edi\nsub %eax,%edi\ncmp %eax,%edi\njg 1320 \nlea 0x2cf9(%rip),%rax\nretq\nnopl 0x0(%rax,%rax,1)\nmovb $0x0,0x2ce9(%rip)\nlea 0x2ce2(%rip),%rax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njle short loc_12B8\nlea rsi, binary_1\nxor r8d, r8d\nmov rdx, rsi\nnop dword ptr [rax]\nloc_1258:\nmov eax, edi\nadd rdx, 1\nmov ecx, r8d\nand eax, 1\nlea r8d, [r8+1]\nadd eax, 30h ; '0'\nmov [rdx-1], al\nsar edi, 1\njnz short loc_1258\nmovsxd r8, r8d\nmov byte ptr [rsi+r8], 0\ntest ecx, ecx\njz short loc_12B0\nmovsxd rdx, ecx\nxor eax, eax\nadd rdx, rsi\nnop word ptr [rax+rax+00000000h]\nloc_1290:\nmovzx edi, byte ptr [rsi+rax]\nmovzx r8d, byte ptr [rdx]\nsub rdx, 1\nmov [rsi+rax], r8b\nadd rax, 1\nmov [rdx+1], dil\nmov edi, ecx\nsub edi, eax\ncmp edi, eax\njg short loc_1290\nloc_12B0:\nmov rax, rsi\nretn\nloc_12B8:\nlea rsi, binary_1\nmov cs:binary_1, 0\nmov rax, rsi\nretn", + "ida_pseudo": "char *__fastcall func0(int a1)\n{\n int v1; // r8d\n char *v2; // rdx\n int v3; // ecx\n __int64 v4; // rax\n char *v5; // rdx\n char v6; // di\n char v7; // r8\n\n if ( a1 <= 0 )\n {\n binary_1[0] = 0;\n return binary_1;\n }\n else\n {\n v1 = 0;\n v2 = binary_1;\n do\n {\n ++v2;\n v3 = v1++;\n *(v2 - 1) = (a1 & 1) + 48;\n a1 >>= 1;\n }\n while ( a1 );\n binary_1[v1] = 0;\n if ( v3 )\n {\n v4 = 0LL;\n v5 = &binary_1[v3];\n do\n {\n v6 = binary_1[v4];\n v7 = *v5--;\n binary_1[v4++] = v7;\n v5[1] = v6;\n }\n while ( v3 - (int)v4 > (int)v4 );\n }\n return binary_1;\n }\n}", + "ida_strip_asm": "sub_1240:\nendbr64\ntest edi, edi\njle short loc_12B8\nlea rsi, byte_4040\nxor r8d, r8d\nmov rdx, rsi\nnop dword ptr [rax]\nloc_1258:\nmov eax, edi\nadd rdx, 1\nmov ecx, r8d\nand eax, 1\nlea r8d, [r8+1]\nadd eax, 30h ; '0'\nmov [rdx-1], al\nsar edi, 1\njnz short loc_1258\nmovsxd r8, r8d\nmov byte ptr [rsi+r8], 0\ntest ecx, ecx\njz short loc_12B0\nmovsxd rdx, ecx\nxor eax, eax\nadd rdx, rsi\nnop word ptr [rax+rax+00000000h]\nloc_1290:\nmovzx edi, byte ptr [rsi+rax]\nmovzx r8d, byte ptr [rdx]\nsub rdx, 1\nmov [rsi+rax], r8b\nadd rax, 1\nmov [rdx+1], dil\nmov edi, ecx\nsub edi, eax\ncmp edi, eax\njg short loc_1290\nloc_12B0:\nmov rax, rsi\nretn\nloc_12B8:\nlea rsi, byte_4040\nmov cs:byte_4040, 0\nmov rax, rsi\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1240(int a1)\n{\n int v1; // r8d\n char *v2; // rdx\n int v3; // ecx\n __int64 v4; // rax\n char *v5; // rdx\n char v6; // di\n char v7; // r8\n\n if ( a1 <= 0 )\n {\n byte_4040[0] = 0;\n return byte_4040;\n }\n else\n {\n v1 = 0;\n v2 = byte_4040;\n do\n {\n ++v2;\n v3 = v1++;\n *(v2 - 1) = (a1 & 1) + 48;\n a1 >>= 1;\n }\n while ( a1 );\n byte_4040[v1] = 0;\n if ( v3 )\n {\n v4 = 0LL;\n v5 = &byte_4040[v3];\n do\n {\n v6 = byte_4040[v4];\n v7 = *v5--;\n byte_4040[v4++] = v7;\n v5[1] = v6;\n }\n while ( v3 - (int)v4 > (int)v4 );\n }\n return byte_4040;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1240(int a1) {\n int v1;\n char *v2;\n int v3;\n long long v4;\n char *v5;\n char v6;\n char v7;\n if (a1 <= 0) {\n byte_4040[0] = 0;\n return byte_4040;\n } else {\n v1 = 0;\n v2 = byte_4040;\n do {\n ++v2;\n v3 = v1++;\n *(v2 - 1) = (a1 & 1) + 48;\n a1 >>= 1;\n } while (a1);\n byte_4040[v1] = 0;\n if (v3) {\n v4 = 0LL;\n v5 = &byte_4040[v3];\n do {\n v6 = byte_4040[v4];\n v7 = *v5--;\n byte_4040[v4++] = v7;\n v5[1] = v6;\n } while (v3 - (int)v4 > (int)v4);\n }\n return byte_4040;\n }\n}", + "ida_pseudo_norm": "char *func0(int a1) {\n int v1;\n char *v2;\n int v3;\n long long v4;\n char *v5;\n char v6;\n char v7;\n if (a1 <= 0) {\n binary_1[0] = 0;\n return binary_1;\n } else {\n v1 = 0;\n v2 = binary_1;\n do {\n ++v2;\n v3 = v1++;\n *(v2 - 1) = (a1 & 1) + 48;\n a1 >>= 1;\n } while (a1);\n binary_1[v1] = 0;\n if (v3) {\n v4 = 0LL;\n v5 = &binary_1[v3];\n do {\n v6 = binary_1[v4];\n v7 = *v5--;\n binary_1[v4++] = v7;\n v5[1] = v6;\n } while (v3 - (int)v4 > (int)v4);\n }\n return binary_1;\n }\n}" + }, + { + "index": 99, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(int n) {\n static char binary[32];\n int index = 0;\n while (n > 0) {\n binary[index++] = (n % 2) + '0';\n n /= 2;\n }\n binary[index] = '\\0';\n int start = 0;\n int end = index - 1;\n while (start < end) {\n char temp = binary[start];\n binary[start] = binary[end];\n binary[end] = temp;\n start++;\n end--;\n }\n return binary;\n}", + "test": "int main() {\n\n assert(strcmp(func0(8), \"1000\") == 0);\n\n assert(strcmp(func0(18), \"10010\") == 0);\n\n assert(strcmp(func0(7), \"111\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\njle 14c8 \nlea 0x2ddd(%rip),%r8\nxor %esi,%esi\nmov %r8,%rdx\nnopl 0x0(%rax,%rax,1)\nmov %edi,%eax\nadd $0x1,%rdx\nmov %esi,%ecx\nand $0x1,%eax\nlea 0x1(%rsi),%esi\nadd $0x30,%eax\nmov %al,-0x1(%rdx)\nsar %edi\njne 1270 \nmovslq %esi,%rsi\nmovb $0x0,(%r8,%rsi,1)\ntest %ecx,%ecx\nje 14b9 \nmovslq %ecx,%rax\nmovzbl 0x2d9e(%rip),%edx\nmovzbl (%r8,%rax,1),%esi\nmov %sil,0x2d92(%rip)\nmov %dl,(%r8,%rax,1)\nlea -0x1(%rcx),%eax\ncmp $0x1,%eax\njle 14b9 \ncltq\nmovzbl 0x2d7a(%rip),%edx\nmovzbl (%r8,%rax,1),%esi\nmov %sil,0x2d6e(%rip)\nmov %dl,(%r8,%rax,1)\nlea -0x2(%rcx),%eax\ncmp $0x2,%eax\njle 14b9 \ncltq\nmovzbl 0x2d56(%rip),%edx\nmovzbl (%r8,%rax,1),%esi\nmov %sil,0x2d4a(%rip)\nmov %dl,(%r8,%rax,1)\nlea -0x3(%rcx),%eax\ncmp $0x3,%eax\njle 14b9 \ncltq\nmovzbl 0x2d32(%rip),%edx\nmovzbl (%r8,%rax,1),%esi\nmov %sil,0x2d26(%rip)\nmov %dl,(%r8,%rax,1)\nlea -0x4(%rcx),%eax\ncmp $0x4,%eax\njle 14b9 \ncltq\nmovzbl 0x2d0e(%rip),%edx\nmovzbl (%r8,%rax,1),%esi\nmov %sil,0x2d02(%rip)\nmov %dl,(%r8,%rax,1)\nlea -0x5(%rcx),%eax\ncmp $0x5,%eax\njle 14b9 \ncltq\nmovzbl 0x2cea(%rip),%edx\nmovzbl (%r8,%rax,1),%esi\nmov %sil,0x2cde(%rip)\nmov %dl,(%r8,%rax,1)\nlea -0x6(%rcx),%eax\ncmp $0x6,%eax\njle 14b9 \ncltq\nmovzbl 0x2cc6(%rip),%edx\nmovzbl (%r8,%rax,1),%esi\nmov %sil,0x2cba(%rip)\nmov %dl,(%r8,%rax,1)\nlea -0x7(%rcx),%eax\ncmp $0x7,%eax\njle 14b9 \ncltq\nmovzbl 0x2ca2(%rip),%edx\nmovzbl (%r8,%rax,1),%esi\nmov %sil,0x2c96(%rip)\nmov %dl,(%r8,%rax,1)\nlea -0x8(%rcx),%eax\ncmp $0x8,%eax\njle 14b9 \ncltq\nmovzbl 0x2c7e(%rip),%edx\nmovzbl (%r8,%rax,1),%esi\nmov %sil,0x2c72(%rip)\nmov %dl,(%r8,%rax,1)\nlea -0x9(%rcx),%eax\ncmp $0x9,%eax\njle 14b9 \ncltq\nmovzbl 0x2c5a(%rip),%edx\nmovzbl (%r8,%rax,1),%esi\nmov %sil,0x2c4e(%rip)\nmov %dl,(%r8,%rax,1)\nlea -0xa(%rcx),%eax\ncmp $0xa,%eax\njle 14b9 \ncltq\nmovzbl 0x2c36(%rip),%edx\nmovzbl (%r8,%rax,1),%esi\nmov %sil,0x2c2a(%rip)\nmov %dl,(%r8,%rax,1)\nlea -0xb(%rcx),%eax\ncmp $0xb,%eax\njle 14b9 \ncltq\nmovzbl 0x2c12(%rip),%edx\nmovzbl (%r8,%rax,1),%esi\nmov %sil,0x2c06(%rip)\nmov %dl,(%r8,%rax,1)\nlea -0xc(%rcx),%eax\ncmp $0xc,%eax\njle 14b9 \ncltq\nmovzbl 0x2bf2(%rip),%edx\nmovzbl (%r8,%rax,1),%esi\nmov %sil,0x2be6(%rip)\nmov %dl,(%r8,%rax,1)\nlea -0xd(%rcx),%eax\ncmp $0xd,%eax\njle 14b9 \ncltq\nmovzbl 0x2bd2(%rip),%edx\nmovzbl (%r8,%rax,1),%esi\nmov %sil,0x2bc6(%rip)\nmov %dl,(%r8,%rax,1)\nlea -0xe(%rcx),%eax\ncmp $0xe,%eax\njle 14b9 \ncltq\nmovzbl 0x2bb2(%rip),%edx\nmovzbl (%r8,%rax,1),%esi\nmov %sil,0x2ba6(%rip)\nmov %dl,(%r8,%rax,1)\ncmp $0x1f,%ecx\njne 14b9 \nrolw $0x8,0x2b96(%rip)\nlea 0x2b80(%rip),%rax\nretq\nnopl 0x0(%rax)\nmovb $0x0,0x2b71(%rip)\nlea 0x2b6a(%rip),%rax\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njle short loc_12B8\nlea rsi, binary_1\nxor r8d, r8d\nmov rdx, rsi\nnop dword ptr [rax]\nloc_1258:\nmov eax, edi\nadd rdx, 1\nmov ecx, r8d\nand eax, 1\nlea r8d, [r8+1]\nadd eax, 30h ; '0'\nmov [rdx-1], al\nsar edi, 1\njnz short loc_1258\nmovsxd r8, r8d\nmov byte ptr [rsi+r8], 0\ntest ecx, ecx\njz short loc_12B0\nmovsxd rdx, ecx\nxor eax, eax\nadd rdx, rsi\nnop word ptr [rax+rax+00000000h]\nloc_1290:\nmovzx edi, byte ptr [rsi+rax]\nmovzx r8d, byte ptr [rdx]\nsub rdx, 1\nmov [rsi+rax], r8b\nadd rax, 1\nmov [rdx+1], dil\nmov edi, ecx\nsub edi, eax\ncmp edi, eax\njg short loc_1290\nloc_12B0:\nmov rax, rsi\nretn\nloc_12B8:\nlea rsi, binary_1\nmov cs:binary_1, 0\nmov rax, rsi\nretn", + "ida_pseudo": "char *__fastcall func0(int a1)\n{\n int v1; // r8d\n char *v2; // rdx\n int v3; // ecx\n __int64 v4; // rax\n char *v5; // rdx\n char v6; // di\n char v7; // r8\n\n if ( a1 <= 0 )\n {\n binary_1[0] = 0;\n return binary_1;\n }\n else\n {\n v1 = 0;\n v2 = binary_1;\n do\n {\n ++v2;\n v3 = v1++;\n *(v2 - 1) = (a1 & 1) + 48;\n a1 >>= 1;\n }\n while ( a1 );\n binary_1[v1] = 0;\n if ( v3 )\n {\n v4 = 0LL;\n v5 = &binary_1[v3];\n do\n {\n v6 = binary_1[v4];\n v7 = *v5--;\n binary_1[v4++] = v7;\n v5[1] = v6;\n }\n while ( v3 - (int)v4 > (int)v4 );\n }\n return binary_1;\n }\n}", + "ida_strip_asm": "sub_1240:\nendbr64\ntest edi, edi\njle short loc_12B8\nlea rsi, byte_4040\nxor r8d, r8d\nmov rdx, rsi\nnop dword ptr [rax]\nloc_1258:\nmov eax, edi\nadd rdx, 1\nmov ecx, r8d\nand eax, 1\nlea r8d, [r8+1]\nadd eax, 30h ; '0'\nmov [rdx-1], al\nsar edi, 1\njnz short loc_1258\nmovsxd r8, r8d\nmov byte ptr [rsi+r8], 0\ntest ecx, ecx\njz short loc_12B0\nmovsxd rdx, ecx\nxor eax, eax\nadd rdx, rsi\nnop word ptr [rax+rax+00000000h]\nloc_1290:\nmovzx edi, byte ptr [rsi+rax]\nmovzx r8d, byte ptr [rdx]\nsub rdx, 1\nmov [rsi+rax], r8b\nadd rax, 1\nmov [rdx+1], dil\nmov edi, ecx\nsub edi, eax\ncmp edi, eax\njg short loc_1290\nloc_12B0:\nmov rax, rsi\nretn\nloc_12B8:\nlea rsi, byte_4040\nmov cs:byte_4040, 0\nmov rax, rsi\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1240(int a1)\n{\n int v1; // r8d\n char *v2; // rdx\n int v3; // ecx\n __int64 v4; // rax\n char *v5; // rdx\n char v6; // di\n char v7; // r8\n\n if ( a1 <= 0 )\n {\n byte_4040[0] = 0;\n return byte_4040;\n }\n else\n {\n v1 = 0;\n v2 = byte_4040;\n do\n {\n ++v2;\n v3 = v1++;\n *(v2 - 1) = (a1 & 1) + 48;\n a1 >>= 1;\n }\n while ( a1 );\n byte_4040[v1] = 0;\n if ( v3 )\n {\n v4 = 0LL;\n v5 = &byte_4040[v3];\n do\n {\n v6 = byte_4040[v4];\n v7 = *v5--;\n byte_4040[v4++] = v7;\n v5[1] = v6;\n }\n while ( v3 - (int)v4 > (int)v4 );\n }\n return byte_4040;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1240(int a1) {\n int v1;\n char *v2;\n int v3;\n long long v4;\n char *v5;\n char v6;\n char v7;\n if (a1 <= 0) {\n byte_4040[0] = 0;\n return byte_4040;\n } else {\n v1 = 0;\n v2 = byte_4040;\n do {\n ++v2;\n v3 = v1++;\n *(v2 - 1) = (a1 & 1) + 48;\n a1 >>= 1;\n } while (a1);\n byte_4040[v1] = 0;\n if (v3) {\n v4 = 0LL;\n v5 = &byte_4040[v3];\n do {\n v6 = byte_4040[v4];\n v7 = *v5--;\n byte_4040[v4++] = v7;\n v5[1] = v6;\n } while (v3 - (int)v4 > (int)v4);\n }\n return byte_4040;\n }\n}", + "ida_pseudo_norm": "char *func0(int a1) {\n int v1;\n char *v2;\n int v3;\n long long v4;\n char *v5;\n char v6;\n char v7;\n if (a1 <= 0) {\n binary_1[0] = 0;\n return binary_1;\n } else {\n v1 = 0;\n v2 = binary_1;\n do {\n ++v2;\n v3 = v1++;\n *(v2 - 1) = (a1 & 1) + 48;\n a1 >>= 1;\n } while (a1);\n binary_1[v1] = 0;\n if (v3) {\n v4 = 0LL;\n v5 = &binary_1[v3];\n do {\n v6 = binary_1[v4];\n v7 = *v5--;\n binary_1[v4++] = v7;\n v5[1] = v6;\n } while (v3 - (int)v4 > (int)v4);\n }\n return binary_1;\n }\n}" + }, + { + "index": 100, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int num) {\n for (int i = num + 1; i < INT_MAX; i++) {\n char numstr[20];\n sprintf(numstr, \"%d\", i);\n int len = strlen(numstr);\n int isPalindrome = 1;\n for (int j = 0; j < len / 2; j++) {\n if (numstr[j] != numstr[len - 1 - j]) {\n isPalindrome = 0;\n break;\n }\n }\n if (isPalindrome) {\n return i;\n }\n }\n return -1;\n}", + "test": "int main() {\n\n assert(func0(99) == 101);\n\n assert(func0(1221) == 1331);\n\n assert(func0(120) == 121);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x40,%rsp\nmov %edi,-0x34(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmov -0x34(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x30(%rbp)\njmpq 125a \nmov -0x30(%rbp),%edx\nlea -0x20(%rbp),%rax\nlea 0xe25(%rip),%rsi\nmov %rax,%rdi\nmov $0x0,%eax\ncallq 10b0 \nlea -0x20(%rbp),%rax\nmov %rax,%rdi\ncallq 1080 \nmov %eax,-0x24(%rbp)\nmovl $0x1,-0x2c(%rbp)\nmovl $0x0,-0x28(%rbp)\njmp 123a \nmov -0x28(%rbp),%eax\ncltq\nmovzbl -0x20(%rbp,%rax,1),%edx\nmov -0x24(%rbp),%eax\nsub $0x1,%eax\nsub -0x28(%rbp),%eax\ncltq\nmovzbl -0x20(%rbp,%rax,1),%eax\ncmp %al,%dl\nje 1236 \nmovl $0x0,-0x2c(%rbp)\njmp 124b \naddl $0x1,-0x28(%rbp)\nmov -0x24(%rbp),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\ncmp %eax,-0x28(%rbp)\njl 120f \ncmpl $0x0,-0x2c(%rbp)\nje 1256 \nmov -0x30(%rbp),%eax\njmp 126c \naddl $0x1,-0x30(%rbp)\ncmpl $0x7fffffff,-0x30(%rbp)\njne 11d5 \nmov $0xffffffff,%eax\nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 1280 \ncallq 1090 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_34], edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov eax, [rbp+var_34]\nadd eax, 1\nmov [rbp+var_30], eax\njmp loc_125D\nloc_11D5:\nmov edx, [rbp+var_30]\nlea rax, [rbp+s]\nlea rcx, format; \"%d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_24], eax\nmov [rbp+var_2C], 1\nmov [rbp+var_28], 0\njmp short loc_123D\nloc_1212:\nmov eax, [rbp+var_28]\ncdqe\nmovzx edx, [rbp+rax+s]\nmov eax, [rbp+var_24]\nsub eax, 1\nsub eax, [rbp+var_28]\ncdqe\nmovzx eax, [rbp+rax+s]\ncmp dl, al\njz short loc_1239\nmov [rbp+var_2C], 0\njmp short loc_124E\nloc_1239:\nadd [rbp+var_28], 1\nloc_123D:\nmov eax, [rbp+var_24]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\ncmp [rbp+var_28], eax\njl short loc_1212\nloc_124E:\ncmp [rbp+var_2C], 0\njz short loc_1259\nmov eax, [rbp+var_30]\njmp short loc_126F\nloc_1259:\nadd [rbp+var_30], 1\nloc_125D:\ncmp [rbp+var_30], 7FFFFFFFh\njnz loc_11D5\nmov eax, 0FFFFFFFFh\nloc_126F:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1283\ncall ___stack_chk_fail\nlocret_1283:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int i; // [rsp+10h] [rbp-30h]\n int v3; // [rsp+14h] [rbp-2Ch]\n int j; // [rsp+18h] [rbp-28h]\n int v5; // [rsp+1Ch] [rbp-24h]\n char s[24]; // [rsp+20h] [rbp-20h] BYREF\n unsigned __int64 v7; // [rsp+38h] [rbp-8h]\n\n v7 = __readfsqword(0x28u);\n for ( i = a1 + 1; i != 0x7FFFFFFF; ++i )\n {\n sprintf(s, \"%d\", i);\n v5 = strlen(s);\n v3 = 1;\n for ( j = 0; j < v5 / 2; ++j )\n {\n if ( s[j] != s[v5 - 1 - j] )\n {\n v3 = 0;\n break;\n }\n }\n if ( v3 )\n return i;\n }\n return 0xFFFFFFFFLL;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_34], edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov eax, [rbp+var_34]\nadd eax, 1\nmov [rbp+var_30], eax\njmp loc_125D\nloc_11D5:\nmov edx, [rbp+var_30]\nlea rax, [rbp+s]\nlea rcx, format; \"%d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_24], eax\nmov [rbp+var_2C], 1\nmov [rbp+var_28], 0\njmp short loc_123D\nloc_1212:\nmov eax, [rbp+var_28]\ncdqe\nmovzx edx, [rbp+rax+s]\nmov eax, [rbp+var_24]\nsub eax, 1\nsub eax, [rbp+var_28]\ncdqe\nmovzx eax, [rbp+rax+s]\ncmp dl, al\njz short loc_1239\nmov [rbp+var_2C], 0\njmp short loc_124E\nloc_1239:\nadd [rbp+var_28], 1\nloc_123D:\nmov eax, [rbp+var_24]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\ncmp [rbp+var_28], eax\njl short loc_1212\nloc_124E:\ncmp [rbp+var_2C], 0\njz short loc_1259\nmov eax, [rbp+var_30]\njmp short loc_126F\nloc_1259:\nadd [rbp+var_30], 1\nloc_125D:\ncmp [rbp+var_30], 7FFFFFFFh\njnz loc_11D5\nmov eax, 0FFFFFFFFh\nloc_126F:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1283\ncall ___stack_chk_fail\nlocret_1283:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(int a1)\n{\n unsigned int i; // [rsp+10h] [rbp-30h]\n int v3; // [rsp+14h] [rbp-2Ch]\n int j; // [rsp+18h] [rbp-28h]\n int v5; // [rsp+1Ch] [rbp-24h]\n char s[24]; // [rsp+20h] [rbp-20h] BYREF\n unsigned __int64 v7; // [rsp+38h] [rbp-8h]\n\n v7 = __readfsqword(0x28u);\n for ( i = a1 + 1; i != 0x7FFFFFFF; ++i )\n {\n sprintf(s, \"%d\", i);\n v5 = strlen(s);\n v3 = 1;\n for ( j = 0; j < v5 / 2; ++j )\n {\n if ( s[j] != s[v5 - 1 - j] )\n {\n v3 = 0;\n break;\n }\n }\n if ( v3 )\n return i;\n }\n return 0xFFFFFFFFLL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(int a1) {\n unsigned int i;\n int v3;\n int j;\n int v5;\n char s[24];\n unsigned long long v7;\n v7 = __readfsqword(40u);\n for (i = a1 + 1; i != 2147483647; ++i) {\n sprintf(s, \"%d\", i);\n v5 = strlen(s);\n v3 = 1;\n for (j = 0; j < v5 / 2; ++j) {\n if (s[j] != s[v5 - 1 - j]) {\n v3 = 0;\n break;\n }\n }\n if (v3) return i;\n }\n return 4294967295LL;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int i;\n int v3;\n int j;\n int v5;\n char s[24];\n unsigned long long v7;\n v7 = __readfsqword(40u);\n for (i = a1 + 1; i != 2147483647; ++i) {\n sprintf(s, \"%d\", i);\n v5 = strlen(s);\n v3 = 1;\n for (j = 0; j < v5 / 2; ++j) {\n if (s[j] != s[v5 - 1 - j]) {\n v3 = 0;\n break;\n }\n }\n if (v3) return i;\n }\n return 4294967295LL;\n}" + }, + { + "index": 100, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int num) {\n for (int i = num + 1; i < INT_MAX; i++) {\n char numstr[20];\n sprintf(numstr, \"%d\", i);\n int len = strlen(numstr);\n int isPalindrome = 1;\n for (int j = 0; j < len / 2; j++) {\n if (numstr[j] != numstr[len - 1 - j]) {\n isPalindrome = 0;\n break;\n }\n }\n if (isPalindrome) {\n return i;\n }\n }\n return -1;\n}", + "test": "int main() {\n\n assert(func0(99) == 101);\n\n assert(func0(1221) == 1331);\n\n assert(func0(120) == 121);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x28,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x18(%rsp)\nxor %eax,%eax\ncmp $0x7ffffffe,%edi\nje 11b3 \nlea 0x1(%rdi),%ebp\nmov %rsp,%rbx\njmp 11c9 \nmov $0xffffffff,%ebp\njmp 1233 \nadd $0x1,%ebp\ncmp $0x7fffffff,%ebp\nje 124c \nmov %ebp,%r8d\nlea 0xe31(%rip),%rcx\nmov $0x14,%edx\nmov $0x1,%esi\nmov %rbx,%rdi\nmov $0x0,%eax\ncallq 1090 <__sprintf_chk@plt>\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nmov %rbx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nsub $0x1,%rax\nmov %eax,%ecx\nshr $0x1f,%ecx\nadd %eax,%ecx\nsar %ecx\ncmp $0x1,%eax\njle 1233 \ncltq\nadd %rbx,%rax\nmov $0x0,%edx\nmovzbl -0x1(%rax),%esi\ncmp %sil,(%rbx,%rdx,1)\njne 11ba \nadd $0x1,%rdx\nsub $0x1,%rax\ncmp %edx,%ecx\njg 121d \nmov 0x18(%rsp),%rax\nxor %fs:0x28,%rax\njne 1253 \nmov %ebp,%eax\nadd $0x28,%rsp\npop %rbx\npop %rbp\nretq\nmov $0xffffffff,%ebp\njmp 1233 \ncallq 1070 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 20h\nmov rax, fs:28h\nmov [rsp+38h+var_20], rax\nxor eax, eax\ncmp edi, 7FFFFFFEh\njz loc_1261\nlea ebx, [rdi+1]\nlea rbp, unk_2004\njmp short loc_11E8\nloc_11DD:\nadd ebx, 1\ncmp ebx, 7FFFFFFFh\njz short loc_125A\nloc_11E8:\nmov r12, rsp\nmov r8d, ebx\nmov rcx, rbp\nmov edx, 14h\nmov esi, 2\nmov rdi, r12\nmov eax, 0\ncall ___sprintf_chk\nmov rdi, r12; s\ncall _strlen\nmov ecx, eax\nshr ecx, 1Fh\nadd ecx, eax\nsar ecx, 1\ncmp eax, 1\njle short loc_123F\ncdqe\nlea rdx, [rsp+rax+38h+var_38]\nmov eax, 0\nloc_1229:\nmovzx esi, byte ptr [rdx-1]\ncmp [rsp+rax+38h+var_38], sil\njnz short loc_11DD\nadd rax, 1\nsub rdx, 1\ncmp ecx, eax\njg short loc_1229\nloc_123F:\nmov rax, [rsp+38h+var_20]\nsub rax, fs:28h\njnz short loc_1268\nmov eax, ebx\nadd rsp, 20h\npop rbx\npop rbp\npop r12\nretn\nloc_125A:\nmov ebx, 0FFFFFFFFh\njmp short loc_123F\nloc_1261:\nmov ebx, 0FFFFFFFFh\njmp short loc_123F\nloc_1268:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v1; // ebx\n int v2; // eax\n int v3; // ecx\n char *v4; // rdx\n __int64 v5; // rax\n char v7[24]; // [rsp+0h] [rbp-38h] BYREF\n unsigned __int64 v8; // [rsp+18h] [rbp-20h]\n\n v8 = __readfsqword(0x28u);\n if ( a1 == 2147483646 )\n {\n return (unsigned int)-1;\n }\n else\n {\n v1 = a1 + 1;\n while ( 1 )\n {\n __sprintf_chk(v7, 2LL, 20LL, &unk_2004, v1);\n v2 = strlen(v7);\n v3 = v2 / 2;\n if ( v2 <= 1 )\n break;\n v4 = &v7[v2];\n v5 = 0LL;\n while ( v7[v5] == *(v4 - 1) )\n {\n ++v5;\n --v4;\n if ( v3 <= (int)v5 )\n return v1;\n }\n if ( ++v1 == 0x7FFFFFFF )\n return (unsigned int)-1;\n }\n }\n return v1;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 20h\nmov rax, fs:28h\nmov [rsp+38h+var_20], rax\nxor eax, eax\ncmp edi, 7FFFFFFEh\njz loc_1261\nlea ebx, [rdi+1]\nlea rbp, unk_2004\njmp short loc_11E8\nloc_11DD:\nadd ebx, 1\ncmp ebx, 7FFFFFFFh\njz short loc_125A\nloc_11E8:\nmov r12, rsp\nmov r8d, ebx\nmov rcx, rbp\nmov edx, 14h\nmov esi, 2\nmov rdi, r12\nmov eax, 0\ncall ___sprintf_chk\nmov rdi, r12; s\ncall _strlen\nmov ecx, eax\nshr ecx, 1Fh\nadd ecx, eax\nsar ecx, 1\ncmp eax, 1\njle short loc_123F\ncdqe\nlea rdx, [rsp+rax+38h+var_38]\nmov eax, 0\nloc_1229:\nmovzx esi, byte ptr [rdx-1]\ncmp [rsp+rax+38h+var_38], sil\njnz short loc_11DD\nadd rax, 1\nsub rdx, 1\ncmp ecx, eax\njg short loc_1229\nloc_123F:\nmov rax, [rsp+38h+var_20]\nsub rax, fs:28h\njnz short loc_1268\nmov eax, ebx\nadd rsp, 20h\npop rbx\npop rbp\npop r12\nretn\nloc_125A:\nmov ebx, 0FFFFFFFFh\njmp short loc_123F\nloc_1261:\nmov ebx, 0FFFFFFFFh\njmp short loc_123F\nloc_1268:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(int a1)\n{\n unsigned int v1; // ebx\n int v2; // eax\n int v3; // ecx\n char *v4; // rdx\n __int64 v5; // rax\n char v7[24]; // [rsp+0h] [rbp-38h] BYREF\n unsigned __int64 v8; // [rsp+18h] [rbp-20h]\n\n v8 = __readfsqword(0x28u);\n if ( a1 == 2147483646 )\n {\n return (unsigned int)-1;\n }\n else\n {\n v1 = a1 + 1;\n while ( 1 )\n {\n __sprintf_chk(v7, 2LL, 20LL, &unk_2004, v1);\n v2 = strlen(v7);\n v3 = v2 / 2;\n if ( v2 <= 1 )\n break;\n v4 = &v7[v2];\n v5 = 0LL;\n while ( v7[v5] == *(v4 - 1) )\n {\n ++v5;\n --v4;\n if ( v3 <= (int)v5 )\n return v1;\n }\n if ( ++v1 == 0x7FFFFFFF )\n return (unsigned int)-1;\n }\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(int a1) {\n unsigned int v1;\n int v2;\n int v3;\n char *v4;\n long long v5;\n char v7[24];\n unsigned long long v8;\n v8 = __readfsqword(40u);\n if (a1 == 2147483646) {\n return (unsigned int)-1;\n } else {\n v1 = a1 + 1;\n while (1) {\n __sprintf_chk(v7, 2LL, 20LL, &unk_2004, v1);\n v2 = strlen(v7);\n v3 = v2 / 2;\n if (v2 <= 1) break;\n v4 = &v7[v2];\n v5 = 0LL;\n while (v7[v5] == *(v4 - 1)) {\n ++v5;\n --v4;\n if (v3 <= (int)v5) return v1;\n }\n if (++v1 == 2147483647) return (unsigned int)-1;\n }\n }\n return v1;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v1;\n int v2;\n int v3;\n char *v4;\n long long v5;\n char v7[24];\n unsigned long long v8;\n v8 = __readfsqword(40u);\n if (a1 == 2147483646) {\n return (unsigned int)-1;\n } else {\n v1 = a1 + 1;\n while (1) {\n __sprintf_chk(v7, 2LL, 20LL, &unk_2004, v1);\n v2 = strlen(v7);\n v3 = v2 / 2;\n if (v2 <= 1) break;\n v4 = &v7[v2];\n v5 = 0LL;\n while (v7[v5] == *(v4 - 1)) {\n ++v5;\n --v4;\n if (v3 <= (int)v5) return v1;\n }\n if (++v1 == 2147483647) return (unsigned int)-1;\n }\n }\n return v1;\n}" + }, + { + "index": 100, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int num) {\n for (int i = num + 1; i < INT_MAX; i++) {\n char numstr[20];\n sprintf(numstr, \"%d\", i);\n int len = strlen(numstr);\n int isPalindrome = 1;\n for (int j = 0; j < len / 2; j++) {\n if (numstr[j] != numstr[len - 1 - j]) {\n isPalindrome = 0;\n break;\n }\n }\n if (isPalindrome) {\n return i;\n }\n }\n return -1;\n}", + "test": "int main() {\n\n assert(func0(99) == 101);\n\n assert(func0(1221) == 1331);\n\n assert(func0(120) == 121);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nsub $0x20,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x18(%rsp)\nxor %eax,%eax\ncmp $0x7ffffffe,%edi\nje 1307 \nlea 0x1(%rdi),%r12d\nmov %rsp,%rbp\nlea 0x1(%rsp),%rbx\nnopl 0x0(%rax)\nmov %r12d,%r8d\nlea 0xd92(%rip),%rcx\nmov %rbp,%rdi\nxor %eax,%eax\nmov $0x14,%edx\nmov $0x1,%esi\ncallq 1090 <__sprintf_chk@plt>\nmov %rbp,%rax\nmov (%rax),%ecx\nadd $0x4,%rax\nlea -0x1010101(%rcx),%edx\nnot %ecx\nand %ecx,%edx\nand $0x80808080,%edx\nje 1289 \nmov %edx,%ecx\nshr $0x10,%ecx\ntest $0x8080,%edx\ncmove %ecx,%edx\nlea 0x2(%rax),%rcx\ncmove %rcx,%rax\nmov %edx,%edi\nadd %dl,%dil\nsbb $0x3,%rax\nsub %rbp,%rax\nmov %eax,%ecx\nsar %ecx\nje 1310 \ncltq\nsub $0x1,%ecx\nmov %rbp,%rdx\nadd %rbp,%rax\nadd %rbx,%rcx\njmp 12ed \nnopl 0x0(%rax)\nadd $0x1,%rdx\nsub $0x1,%rax\ncmp %rcx,%rdx\nje 1310 \nmovzbl -0x1(%rax),%esi\ncmp %sil,(%rdx)\nje 12e0 \nadd $0x1,%r12d\ncmp $0x7fffffff,%r12d\njne 1268 \nmov $0xffffffff,%r12d\nnopl (%rax)\nmov 0x18(%rsp),%rax\nxor %fs:0x28,%rax\njne 132c \nadd $0x20,%rsp\nmov %r12d,%eax\npop %rbx\npop %rbp\npop %r12\nretq\ncallq 1070 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r12\nlea r12d, [rdi+1]\npush rbp\npush rbx\nlea rbx, unk_2004\nsub rsp, 20h\nmov rax, fs:28h\nmov [rsp+var_s18], rax\nxor eax, eax\nmov rbp, rsp\ncmp edi, 7FFFFFFEh\njz short loc_12E3\nnop word ptr [rax+rax+00h]\nloc_1288:\nmov rcx, rbx\nmov r8d, r12d\nmov edx, 14h\nmov esi, 2\nmov rdi, rbp\nxor eax, eax\ncall ___sprintf_chk\nmov rdi, rbp; s\ncall _strlen\nmov ecx, eax\nsar ecx, 1\njz short loc_12F0\nmovsxd rcx, ecx\nmov rdx, rbp\nadd rax, rbp\nadd rcx, rbp\njmp short loc_12CD\nloc_12C0:\nadd rdx, 1\nsub rax, 1\ncmp rdx, rcx\njz short loc_12F0\nloc_12CD:\nmovzx esi, byte ptr [rax-1]\ncmp [rdx], sil\njz short loc_12C0\nadd r12d, 1\ncmp r12d, 7FFFFFFFh\njnz short loc_1288\nloc_12E3:\nmov r12d, 0FFFFFFFFh\nnop dword ptr [rax+00000000h]\nloc_12F0:\nmov rax, [rsp+var_s18]\nsub rax, fs:28h\njnz short loc_130C\nadd rsp, 20h\nmov eax, r12d\npop rbx\npop rbp\npop r12\nretn\nloc_130C:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v1; // r12d\n size_t v2; // rax\n int v3; // ecx\n char *v4; // rdx\n char *v5; // rax\n char *v6; // rcx\n char _0[24]; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars18; // [rsp+18h] [rbp+18h]\n\n v1 = a1 + 1;\n vars18 = __readfsqword(0x28u);\n if ( a1 == 2147483646 )\n {\n return (unsigned int)-1;\n }\n else\n {\n while ( 1 )\n {\n __sprintf_chk(_0, 2LL, 20LL, &unk_2004, v1);\n v2 = strlen(_0);\n v3 = (int)v2 >> 1;\n if ( !((int)v2 >> 1) )\n break;\n v4 = _0;\n v5 = &_0[v2];\n v6 = &_0[v3];\n while ( *v4 == *(v5 - 1) )\n {\n ++v4;\n --v5;\n if ( v4 == v6 )\n return v1;\n }\n if ( ++v1 == 0x7FFFFFFF )\n return (unsigned int)-1;\n }\n }\n return v1;\n}", + "ida_strip_asm": "sub_1250:\nendbr64\npush r12\nlea r12d, [rdi+1]\npush rbp\npush rbx\nlea rbx, unk_2004\nsub rsp, 20h\nmov rax, fs:28h\nmov [rsp+var_s18], rax\nxor eax, eax\nmov rbp, rsp\ncmp edi, 7FFFFFFEh\njz short loc_12E3\nnop word ptr [rax+rax+00h]\nloc_1288:\nmov rcx, rbx\nmov r8d, r12d\nmov edx, 14h\nmov esi, 2\nmov rdi, rbp\nxor eax, eax\ncall ___sprintf_chk\nmov rdi, rbp; s\ncall _strlen\nmov ecx, eax\nsar ecx, 1\njz short loc_12F0\nmovsxd rcx, ecx\nmov rdx, rbp\nadd rax, rbp\nadd rcx, rbp\njmp short loc_12CD\nloc_12C0:\nadd rdx, 1\nsub rax, 1\ncmp rdx, rcx\njz short loc_12F0\nloc_12CD:\nmovzx esi, byte ptr [rax-1]\ncmp [rdx], sil\njz short loc_12C0\nadd r12d, 1\ncmp r12d, 7FFFFFFFh\njnz short loc_1288\nloc_12E3:\nmov r12d, 0FFFFFFFFh\nnop dword ptr [rax+00000000h]\nloc_12F0:\nmov rax, [rsp+var_s18]\nsub rax, fs:28h\njnz short loc_130C\nadd rsp, 20h\nmov eax, r12d\npop rbx\npop rbp\npop r12\nretn\nloc_130C:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1250(int a1)\n{\n unsigned int v1; // r12d\n size_t v2; // rax\n int v3; // ecx\n char *v4; // rdx\n char *v5; // rax\n char *v6; // rcx\n char _0[24]; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars18; // [rsp+18h] [rbp+18h]\n\n v1 = a1 + 1;\n vars18 = __readfsqword(0x28u);\n if ( a1 == 2147483646 )\n {\n return (unsigned int)-1;\n }\n else\n {\n while ( 1 )\n {\n __sprintf_chk(_0, 2LL, 20LL, &unk_2004, v1);\n v2 = strlen(_0);\n v3 = (int)v2 >> 1;\n if ( !((int)v2 >> 1) )\n break;\n v4 = _0;\n v5 = &_0[v2];\n v6 = &_0[v3];\n while ( *v4 == *(v5 - 1) )\n {\n ++v4;\n --v5;\n if ( v4 == v6 )\n return v1;\n }\n if ( ++v1 == 0x7FFFFFFF )\n return (unsigned int)-1;\n }\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1250(int a1) {\n unsigned int v1;\n unsigned int v2;\n int v3;\n char *v4;\n char *v5;\n char *v6;\n char _0[24];\n unsigned long long vars18;\n v1 = a1 + 1;\n vars18 = __readfsqword(40u);\n if (a1 == 2147483646) {\n return (unsigned int)-1;\n } else {\n while (1) {\n __sprintf_chk(_0, 2LL, 20LL, &unk_2004, v1);\n v2 = strlen(_0);\n v3 = (int)v2 >> 1;\n if (!((int)v2 >> 1)) break;\n v4 = _0;\n v5 = &_0[v2];\n v6 = &_0[v3];\n while (*v4 == *(v5 - 1)) {\n ++v4;\n --v5;\n if (v4 == v6) return v1;\n }\n if (++v1 == 2147483647) return (unsigned int)-1;\n }\n }\n return v1;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v1;\n unsigned int v2;\n int v3;\n char *v4;\n char *v5;\n char *v6;\n char _0[24];\n unsigned long long vars18;\n v1 = a1 + 1;\n vars18 = __readfsqword(40u);\n if (a1 == 2147483646) {\n return (unsigned int)-1;\n } else {\n while (1) {\n __sprintf_chk(_0, 2LL, 20LL, &unk_2004, v1);\n v2 = strlen(_0);\n v3 = (int)v2 >> 1;\n if (!((int)v2 >> 1)) break;\n v4 = _0;\n v5 = &_0[v2];\n v6 = &_0[v3];\n while (*v4 == *(v5 - 1)) {\n ++v4;\n --v5;\n if (v4 == v6) return v1;\n }\n if (++v1 == 2147483647) return (unsigned int)-1;\n }\n }\n return v1;\n}" + }, + { + "index": 100, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int num) {\n for (int i = num + 1; i < INT_MAX; i++) {\n char numstr[20];\n sprintf(numstr, \"%d\", i);\n int len = strlen(numstr);\n int isPalindrome = 1;\n for (int j = 0; j < len / 2; j++) {\n if (numstr[j] != numstr[len - 1 - j]) {\n isPalindrome = 0;\n break;\n }\n }\n if (isPalindrome) {\n return i;\n }\n }\n return -1;\n}", + "test": "int main() {\n\n assert(func0(99) == 101);\n\n assert(func0(1221) == 1331);\n\n assert(func0(120) == 121);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nsub $0x20,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x18(%rsp)\nxor %eax,%eax\ncmp $0x7ffffffe,%edi\nje 13d1 \nlea 0x1(%rdi),%r12d\nmov %rsp,%rbp\nlea 0xd9e(%rip),%rbx\nnopw %cs:0x0(%rax,%rax,1)\nmov %r12d,%r8d\nmov %rbx,%rcx\nmov $0x14,%edx\nmov $0x1,%esi\nmov %rbp,%rdi\nxor %eax,%eax\ncallq 1090 <__sprintf_chk@plt>\nmov %rbp,%rax\nmov (%rax),%ecx\nadd $0x4,%rax\nlea -0x1010101(%rcx),%edx\nnot %ecx\nand %ecx,%edx\nand $0x80808080,%edx\nje 128d \nmov %edx,%ecx\nshr $0x10,%ecx\ntest $0x8080,%edx\ncmove %ecx,%edx\nlea 0x2(%rax),%rcx\ncmove %rcx,%rax\nmov %edx,%esi\nadd %dl,%sil\nsbb $0x3,%rax\nsub %rbp,%rax\nmov %eax,%ecx\nmov %eax,%edx\nsar %ecx\nje 139a \nsub $0x1,%eax\ncltq\nmovzbl (%rsp,%rax,1),%eax\ncmp %al,(%rsp)\njne 13c0 \ncmp $0x1,%ecx\nje 139a \nlea -0x2(%rdx),%eax\ncltq\nmovzbl (%rsp,%rax,1),%eax\ncmp %al,0x1(%rsp)\njne 13c0 \ncmp $0x2,%ecx\nje 139a \nlea -0x3(%rdx),%eax\ncltq\nmovzbl (%rsp,%rax,1),%eax\ncmp %al,0x2(%rsp)\njne 13c0 \ncmp $0x3,%ecx\nje 139a \nlea -0x4(%rdx),%eax\ncltq\nmovzbl (%rsp,%rax,1),%eax\ncmp %al,0x3(%rsp)\njne 13c0 \ncmp $0x4,%ecx\nje 139a \nlea -0x5(%rdx),%eax\ncltq\nmovzbl (%rsp,%rax,1),%eax\ncmp %al,0x4(%rsp)\njne 13c0 \ncmp $0x5,%ecx\nje 139a \nlea -0x6(%rdx),%eax\ncltq\nmovzbl (%rsp,%rax,1),%eax\ncmp %al,0x5(%rsp)\njne 13c0 \ncmp $0x6,%ecx\nje 139a \nlea -0x7(%rdx),%eax\ncltq\nmovzbl (%rsp,%rax,1),%eax\ncmp %al,0x6(%rsp)\njne 13c0 \ncmp $0x7,%ecx\nje 139a \nlea -0x8(%rdx),%eax\ncltq\nmovzbl (%rsp,%rax,1),%eax\ncmp %al,0x7(%rsp)\njne 13c0 \ncmp $0x9,%ecx\njne 139a \nsub $0x9,%edx\nmovslq %edx,%rdx\nmovzbl (%rsp,%rdx,1),%eax\ncmp %al,0x8(%rsp)\njne 13c0 \nmov 0x18(%rsp),%rax\nxor %fs:0x28,%rax\njne 13d9 \nadd $0x20,%rsp\nmov %r12d,%eax\npop %rbx\npop %rbp\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\nadd $0x1,%r12d\ncmp $0x7fffffff,%r12d\njne 1270 \nmov $0xffffffff,%r12d\njmp 139a \ncallq 1070 <__stack_chk_fail@plt>\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r12\nlea r12d, [rdi+1]\npush rbp\nlea rbp, unk_2004\npush rbx\nsub rsp, 20h\nmov rax, fs:28h\nmov [rsp+38h+var_20], rax\nxor eax, eax\nmov rbx, rsp\ncmp edi, 7FFFFFFEh\njz loc_13C9\nnop word ptr [rax+rax+00000000h]\nloc_1290:\nmov edx, 14h\nmov r8d, r12d\nmov rcx, rbp\nmov esi, 2\nmov rdi, rbx\nxor eax, eax\ncall ___sprintf_chk\nmov rdi, rbx; s\ncall _strlen\nmov edx, eax\nsar edx, 1\njz loc_1396\nlea ecx, [rax-1]\nmovsxd rcx, ecx\nmovzx esi, [rsp+rcx+38h+var_38]\ncmp [rsp+38h+var_38], sil\njnz loc_13B8\ncmp edx, 1\njz loc_1396\nlea ecx, [rax-2]\nmovsxd rcx, ecx\nmovzx edi, [rsp+rcx+38h+var_38]\ncmp [rsp+38h+var_37], dil\njnz loc_13B8\ncmp edx, 2\njz loc_1396\nlea ecx, [rax-3]\nmovsxd rcx, ecx\nmovzx esi, [rsp+rcx+38h+var_38]\ncmp [rsp+38h+var_36], sil\njnz loc_13B8\ncmp edx, 3\njz loc_1396\nlea ecx, [rax-4]\nmovsxd rcx, ecx\nmovzx edi, [rsp+rcx+38h+var_38]\ncmp [rsp+38h+var_35], dil\njnz loc_13B8\ncmp edx, 4\njz short loc_1396\nlea ecx, [rax-5]\nmovsxd rcx, ecx\nmovzx esi, [rsp+rcx+38h+var_38]\ncmp [rsp+38h+var_34], sil\njnz short loc_13B8\ncmp edx, 5\njz short loc_1396\nlea ecx, [rax-6]\nmovsxd rcx, ecx\nmovzx edi, [rsp+rcx+38h+var_38]\ncmp [rsp+38h+var_33], dil\njnz short loc_13B8\ncmp edx, 6\njz short loc_1396\nlea ecx, [rax-7]\nmovsxd rcx, ecx\nmovzx esi, [rsp+rcx+38h+var_38]\ncmp [rsp+38h+var_32], sil\njnz short loc_13B8\ncmp edx, 7\njz short loc_1396\nlea ecx, [rax-8]\nmovsxd rcx, ecx\nmovzx esi, [rsp+rcx+38h+var_38]\ncmp [rsp+38h+var_31], sil\njnz short loc_13B8\ncmp edx, 9\njnz short loc_1396\nsub eax, 9\ncdqe\nmovzx eax, [rsp+rax+38h+var_38]\ncmp [rsp+38h+var_30], al\njnz short loc_13B8\nloc_1396:\nmov rax, [rsp+38h+var_20]\nsub rax, fs:28h\njnz short loc_13D1\nadd rsp, 20h\nmov eax, r12d\npop rbx\npop rbp\npop r12\nretn\nloc_13B8:\nadd r12d, 1\ncmp r12d, 7FFFFFFFh\njnz loc_1290\nloc_13C9:\nmov r12d, 0FFFFFFFFh\njmp short loc_1396\nloc_13D1:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v1; // r12d\n int v2; // eax\n int v3; // edx\n char v5[24]; // [rsp+0h] [rbp-38h] BYREF\n unsigned __int64 v6; // [rsp+18h] [rbp-20h]\n\n v1 = a1 + 1;\n v6 = __readfsqword(0x28u);\n if ( a1 == 2147483646 )\n {\n return (unsigned int)-1;\n }\n else\n {\n while ( 1 )\n {\n __sprintf_chk(v5, 2LL, 20LL, &unk_2004, v1);\n v2 = strlen(v5);\n v3 = v2 >> 1;\n if ( !(v2 >> 1)\n || v5[0] == v5[v2 - 1]\n && (v3 == 1\n || v5[1] == v5[v2 - 2]\n && (v3 == 2\n || v5[2] == v5[v2 - 3]\n && (v3 == 3\n || v5[3] == v5[v2 - 4]\n && (v3 == 4\n || v5[4] == v5[v2 - 5]\n && (v3 == 5\n || v5[5] == v5[v2 - 6]\n && (v3 == 6 || v5[6] == v5[v2 - 7] && (v3 == 7 || v5[7] == v5[v2 - 8] && (v3 != 9 || v5[8] == v5[v2 - 9])))))))) )\n {\n break;\n }\n if ( ++v1 == 0x7FFFFFFF )\n return (unsigned int)-1;\n }\n }\n return v1;\n}", + "ida_strip_asm": "sub_1250:\nendbr64\npush r12\nlea r12d, [rdi+1]\npush rbp\nlea rbp, unk_2004\npush rbx\nsub rsp, 20h\nmov rax, fs:28h\nmov [rsp+38h+var_20], rax\nxor eax, eax\nmov rbx, rsp\ncmp edi, 7FFFFFFEh\njz loc_13C9\nnop word ptr [rax+rax+00000000h]\nloc_1290:\nmov edx, 14h\nmov r8d, r12d\nmov rcx, rbp\nmov esi, 2\nmov rdi, rbx\nxor eax, eax\ncall ___sprintf_chk\nmov rdi, rbx; s\ncall _strlen\nmov edx, eax\nsar edx, 1\njz loc_1396\nlea ecx, [rax-1]\nmovsxd rcx, ecx\nmovzx esi, [rsp+rcx+38h+var_38]\ncmp [rsp+38h+var_38], sil\njnz loc_13B8\ncmp edx, 1\njz loc_1396\nlea ecx, [rax-2]\nmovsxd rcx, ecx\nmovzx edi, [rsp+rcx+38h+var_38]\ncmp [rsp+38h+var_37], dil\njnz loc_13B8\ncmp edx, 2\njz loc_1396\nlea ecx, [rax-3]\nmovsxd rcx, ecx\nmovzx esi, [rsp+rcx+38h+var_38]\ncmp [rsp+38h+var_36], sil\njnz loc_13B8\ncmp edx, 3\njz loc_1396\nlea ecx, [rax-4]\nmovsxd rcx, ecx\nmovzx edi, [rsp+rcx+38h+var_38]\ncmp [rsp+38h+var_35], dil\njnz loc_13B8\ncmp edx, 4\njz short loc_1396\nlea ecx, [rax-5]\nmovsxd rcx, ecx\nmovzx esi, [rsp+rcx+38h+var_38]\ncmp [rsp+38h+var_34], sil\njnz short loc_13B8\ncmp edx, 5\njz short loc_1396\nlea ecx, [rax-6]\nmovsxd rcx, ecx\nmovzx edi, [rsp+rcx+38h+var_38]\ncmp [rsp+38h+var_33], dil\njnz short loc_13B8\ncmp edx, 6\njz short loc_1396\nlea ecx, [rax-7]\nmovsxd rcx, ecx\nmovzx esi, [rsp+rcx+38h+var_38]\ncmp [rsp+38h+var_32], sil\njnz short loc_13B8\ncmp edx, 7\njz short loc_1396\nlea ecx, [rax-8]\nmovsxd rcx, ecx\nmovzx esi, [rsp+rcx+38h+var_38]\ncmp [rsp+38h+var_31], sil\njnz short loc_13B8\ncmp edx, 9\njnz short loc_1396\nsub eax, 9\ncdqe\nmovzx eax, [rsp+rax+38h+var_38]\ncmp [rsp+38h+var_30], al\njnz short loc_13B8\nloc_1396:\nmov rax, [rsp+38h+var_20]\nsub rax, fs:28h\njnz short loc_13D1\nadd rsp, 20h\nmov eax, r12d\npop rbx\npop rbp\npop r12\nretn\nloc_13B8:\nadd r12d, 1\ncmp r12d, 7FFFFFFFh\njnz loc_1290\nloc_13C9:\nmov r12d, 0FFFFFFFFh\njmp short loc_1396\nloc_13D1:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1250(int a1)\n{\n unsigned int v1; // r12d\n int v2; // eax\n int v3; // edx\n char v5[24]; // [rsp+0h] [rbp-38h] BYREF\n unsigned __int64 v6; // [rsp+18h] [rbp-20h]\n\n v1 = a1 + 1;\n v6 = __readfsqword(0x28u);\n if ( a1 == 2147483646 )\n {\n return (unsigned int)-1;\n }\n else\n {\n while ( 1 )\n {\n __sprintf_chk(v5, 2LL, 20LL, &unk_2004, v1);\n v2 = strlen(v5);\n v3 = v2 >> 1;\n if ( !(v2 >> 1)\n || v5[0] == v5[v2 - 1]\n && (v3 == 1\n || v5[1] == v5[v2 - 2]\n && (v3 == 2\n || v5[2] == v5[v2 - 3]\n && (v3 == 3\n || v5[3] == v5[v2 - 4]\n && (v3 == 4\n || v5[4] == v5[v2 - 5]\n && (v3 == 5\n || v5[5] == v5[v2 - 6]\n && (v3 == 6 || v5[6] == v5[v2 - 7] && (v3 == 7 || v5[7] == v5[v2 - 8] && (v3 != 9 || v5[8] == v5[v2 - 9])))))))) )\n {\n break;\n }\n if ( ++v1 == 0x7FFFFFFF )\n return (unsigned int)-1;\n }\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1250(int a1) {\n unsigned int v1;\n int v2;\n int v3;\n char v5[24];\n unsigned long long v6;\n v1 = a1 + 1;\n v6 = __readfsqword(40u);\n if (a1 == 2147483646) {\n return (unsigned int)-1;\n } else {\n while (1) {\n __sprintf_chk(v5, 2LL, 20LL, &unk_2004, v1);\n v2 = strlen(v5);\n v3 = v2 >> 1;\n if (!(v2 >> 1) ||\n v5[0] == v5[v2 - 1] &&\n (v3 == 1 ||\n v5[1] == v5[v2 - 2] &&\n (v3 == 2 ||\n v5[2] == v5[v2 - 3] &&\n (v3 == 3 ||\n v5[3] == v5[v2 - 4] &&\n (v3 == 4 ||\n v5[4] == v5[v2 - 5] &&\n (v3 == 5 ||\n v5[5] == v5[v2 - 6] &&\n (v3 == 6 ||\n v5[6] == v5[v2 - 7] &&\n (v3 == 7 ||\n v5[7] == v5[v2 - 8] &&\n (v3 != 9 ||\n v5[8] == v5[v2 - 9]))))))))) {\n break;\n }\n if (++v1 == 2147483647) return (unsigned int)-1;\n }\n }\n return v1;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v1;\n int v2;\n int v3;\n char v5[24];\n unsigned long long v6;\n v1 = a1 + 1;\n v6 = __readfsqword(40u);\n if (a1 == 2147483646) {\n return (unsigned int)-1;\n } else {\n while (1) {\n __sprintf_chk(v5, 2LL, 20LL, &unk_2004, v1);\n v2 = strlen(v5);\n v3 = v2 >> 1;\n if (!(v2 >> 1) ||\n v5[0] == v5[v2 - 1] &&\n (v3 == 1 ||\n v5[1] == v5[v2 - 2] &&\n (v3 == 2 ||\n v5[2] == v5[v2 - 3] &&\n (v3 == 3 ||\n v5[3] == v5[v2 - 4] &&\n (v3 == 4 ||\n v5[4] == v5[v2 - 5] &&\n (v3 == 5 ||\n v5[5] == v5[v2 - 6] &&\n (v3 == 6 ||\n v5[6] == v5[v2 - 7] &&\n (v3 == 7 ||\n v5[7] == v5[v2 - 8] &&\n (v3 != 9 ||\n v5[8] == v5[v2 - 9]))))))))) {\n break;\n }\n if (++v1 == 2147483647) return (unsigned int)-1;\n }\n }\n return v1;\n}" + }, + { + "index": 101, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n, int k) {\n int i, j, temp;\n for (i = 0; i < n; i++) {\n for (j = 0; j < n - i - 1; j++) {\n if (arr[j] > arr[j + 1]) {\n temp = arr[j];\n arr[j] = arr[j + 1];\n arr[j + 1] = temp;\n }\n }\n }\n return arr[k - 1];\n}", + "test": "int main() {\n\n int arr1[] = {12, 3, 5, 7, 19};\n\n assert(func0(arr1, 5, 2) == 5);\n\n \n\n int arr2[] = {17, 24, 8, 23};\n\n assert(func0(arr2, 4, 3) == 23);\n\n \n\n int arr3[] = {16, 21, 25, 36, 4};\n\n assert(func0(arr3, 5, 4) == 25);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmovl $0x0,-0xc(%rbp)\njmpq 1248 \nmovl $0x0,-0x8(%rbp)\njmpq 1232 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x8(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njle 122e \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x4(%rbp)\nmov -0x8(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0x8(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\nmov -0x8(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0x4(%rbp),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x8(%rbp)\nmov -0x1c(%rbp),%eax\nsub -0xc(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x8(%rbp)\njl 1193 \naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1187 \nmov -0x20(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_C], 0\njmp loc_1248\nloc_1187:\nmov [rbp+var_8], 0\njmp loc_1232\nloc_1193:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_122E\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_8]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_8]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nloc_122E:\nadd [rbp+var_8], 1\nloc_1232:\nmov eax, [rbp+var_1C]\nsub eax, [rbp+var_C]\nsub eax, 1\ncmp [rbp+var_8], eax\njl loc_1193\nadd [rbp+var_C], 1\nloc_1248:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl loc_1187\nmov eax, [rbp+var_20]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n int i; // [rsp+14h] [rbp-Ch]\n int j; // [rsp+18h] [rbp-8h]\n int v6; // [rsp+1Ch] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n for ( j = 0; j < a2 - i - 1; ++j )\n {\n if ( *(_DWORD *)(4LL * j + a1) > *(_DWORD *)(4 * (j + 1LL) + a1) )\n {\n v6 = *(_DWORD *)(4LL * j + a1);\n *(_DWORD *)(4LL * j + a1) = *(_DWORD *)(4 * (j + 1LL) + a1);\n *(_DWORD *)(a1 + 4 * (j + 1LL)) = v6;\n }\n }\n }\n return *(unsigned int *)(4LL * a3 - 4 + a1);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_C], 0\njmp loc_1248\nloc_1187:\nmov [rbp+var_8], 0\njmp loc_1232\nloc_1193:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_122E\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_8]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_8]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nloc_122E:\nadd [rbp+var_8], 1\nloc_1232:\nmov eax, [rbp+var_1C]\nsub eax, [rbp+var_C]\nsub eax, 1\ncmp [rbp+var_8], eax\njl loc_1193\nadd [rbp+var_C], 1\nloc_1248:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl loc_1187\nmov eax, [rbp+var_20]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n int i; // [rsp+14h] [rbp-Ch]\n int j; // [rsp+18h] [rbp-8h]\n int v6; // [rsp+1Ch] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n for ( j = 0; j < a2 - i - 1; ++j )\n {\n if ( *(_DWORD *)(4LL * j + a1) > *(_DWORD *)(4 * (j + 1LL) + a1) )\n {\n v6 = *(_DWORD *)(4LL * j + a1);\n *(_DWORD *)(4LL * j + a1) = *(_DWORD *)(4 * (j + 1LL) + a1);\n *(_DWORD *)(a1 + 4 * (j + 1LL)) = v6;\n }\n }\n }\n return *(unsigned int *)(4LL * a3 - 4 + a1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n int i;\n int j;\n int v6;\n for (i = 0; i < a2; ++i) {\n for (j = 0; j < a2 - i - 1; ++j) {\n if (*(uint32_t *)(4LL * j + a1) > *(uint32_t *)(4 * (j + 1LL) + a1)) {\n v6 = *(uint32_t *)(4LL * j + a1);\n *(uint32_t *)(4LL * j + a1) = *(uint32_t *)(4 * (j + 1LL) + a1);\n *(uint32_t *)(a1 + 4 * (j + 1LL)) = v6;\n }\n }\n }\n return *(unsigned int *)(4LL * a3 - 4 + a1);\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n int i;\n int j;\n int v6;\n for (i = 0; i < a2; ++i) {\n for (j = 0; j < a2 - i - 1; ++j) {\n if (*(uint32_t *)(4LL * j + a1) > *(uint32_t *)(4 * (j + 1LL) + a1)) {\n v6 = *(uint32_t *)(4LL * j + a1);\n *(uint32_t *)(4LL * j + a1) = *(uint32_t *)(4 * (j + 1LL) + a1);\n *(uint32_t *)(a1 + 4 * (j + 1LL)) = v6;\n }\n }\n }\n return *(unsigned int *)(4LL * a3 - 4 + a1);\n}" + }, + { + "index": 101, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n, int k) {\n int i, j, temp;\n for (i = 0; i < n; i++) {\n for (j = 0; j < n - i - 1; j++) {\n if (arr[j] > arr[j + 1]) {\n temp = arr[j];\n arr[j] = arr[j + 1];\n arr[j + 1] = temp;\n }\n }\n }\n return arr[k - 1];\n}", + "test": "int main() {\n\n int arr1[] = {12, 3, 5, 7, 19};\n\n assert(func0(arr1, 5, 2) == 5);\n\n \n\n int arr2[] = {17, 24, 8, 23};\n\n assert(func0(arr2, 4, 3) == 23);\n\n \n\n int arr3[] = {16, 21, 25, 36, 4};\n\n assert(func0(arr3, 5, 4) == 25);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 119e \nlea -0x1(%rsi),%r9d\nlea 0x4(%rdi),%r10\njmp 11aa \nadd $0x4,%rax\ncmp %r8,%rax\nje 11a6 \nmov (%rax),%ecx\nmov 0x4(%rax),%esi\ncmp %esi,%ecx\njle 117b \nmov %esi,(%rax)\nmov %ecx,0x4(%rax)\njmp 117b \nsub $0x1,%r9d\ncmp $0xffffffff,%r9d\njne 11aa \nmovslq %edx,%rax\nmov -0x4(%rdi,%rax,4),%eax\nretq\nsub $0x1,%r9d\ntest %r9d,%r9d\njle 1194 \nmov %rdi,%rax\nlea -0x1(%r9),%ecx\nlea (%r10,%rcx,4),%r8\njmp 1184 \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1198\nlea r10, [rdi+4]\njmp short loc_11A3\nloc_1177:\nadd rax, 4\ncmp rax, r9\njz short loc_11A0\nloc_1180:\nmov ecx, [rax]\nmov r8d, [rax+4]\ncmp ecx, r8d\njle short loc_1177\nmov [rax], r8d\nmov [rax+4], ecx\njmp short loc_1177\nloc_1193:\nsub esi, 1\njnz short loc_11A3\nloc_1198:\nmovsxd rax, edx\nmov eax, [rdi+rax*4-4]\nretn\nloc_11A0:\nsub esi, 1\nloc_11A3:\ncmp esi, 1\njle short loc_1193\nmov rax, rdi\nlea ecx, [rsi-2]\nlea r9, [r10+rcx*4]\njmp short loc_1180", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2, int a3)\n{\n int *v3; // rax\n int v4; // ecx\n int v5; // r8d\n\n if ( a2 > 0 )\n {\n do\n {\n while ( a2 > 1 )\n {\n v3 = a1;\n do\n {\n v4 = *v3;\n v5 = v3[1];\n if ( *v3 > v5 )\n {\n *v3 = v5;\n v3[1] = v4;\n }\n ++v3;\n }\n while ( v3 != &a1[a2 - 2 + 1] );\n --a2;\n }\n --a2;\n }\n while ( a2 );\n }\n return (unsigned int)a1[a3 - 1];\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_1198\nlea r10, [rdi+4]\njmp short loc_11A3\nloc_1177:\nadd rax, 4\ncmp rax, r9\njz short loc_11A0\nloc_1180:\nmov ecx, [rax]\nmov r8d, [rax+4]\ncmp ecx, r8d\njle short loc_1177\nmov [rax], r8d\nmov [rax+4], ecx\njmp short loc_1177\nloc_1193:\nsub esi, 1\njnz short loc_11A3\nloc_1198:\nmovsxd rax, edx\nmov eax, [rdi+rax*4-4]\nretn\nloc_11A0:\nsub esi, 1\nloc_11A3:\ncmp esi, 1\njle short loc_1193\nmov rax, rdi\nlea ecx, [rsi-2]\nlea r9, [r10+rcx*4]\njmp short loc_1180", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int *a1, int a2, int a3)\n{\n int *v3; // rax\n int v4; // ecx\n int v5; // r8d\n\n if ( a2 > 0 )\n {\n do\n {\n while ( a2 > 1 )\n {\n v3 = a1;\n do\n {\n v4 = *v3;\n v5 = v3[1];\n if ( *v3 > v5 )\n {\n *v3 = v5;\n v3[1] = v4;\n }\n ++v3;\n }\n while ( v3 != &a1[a2 - 2 + 1] );\n --a2;\n }\n --a2;\n }\n while ( a2 );\n }\n return (unsigned int)a1[a3 - 1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int *a1, int a2, int a3) {\n int *v3;\n int v4;\n int v5;\n if (a2 > 0) {\n do {\n while (a2 > 1) {\n v3 = a1;\n do {\n v4 = *v3;\n v5 = v3[1];\n if (*v3 > v5) {\n *v3 = v5;\n v3[1] = v4;\n }\n ++v3;\n } while (v3 != &a1[a2 - 2 + 1]);\n --a2;\n }\n --a2;\n } while (a2);\n }\n return (unsigned int)a1[a3 - 1];\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2, int a3) {\n int *v3;\n int v4;\n int v5;\n if (a2 > 0) {\n do {\n while (a2 > 1) {\n v3 = a1;\n do {\n v4 = *v3;\n v5 = v3[1];\n if (*v3 > v5) {\n *v3 = v5;\n v3[1] = v4;\n }\n ++v3;\n } while (v3 != &a1[a2 - 2 + 1]);\n --a2;\n }\n --a2;\n } while (a2);\n }\n return (unsigned int)a1[a3 - 1];\n}" + }, + { + "index": 101, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n, int k) {\n int i, j, temp;\n for (i = 0; i < n; i++) {\n for (j = 0; j < n - i - 1; j++) {\n if (arr[j] > arr[j + 1]) {\n temp = arr[j];\n arr[j] = arr[j + 1];\n arr[j + 1] = temp;\n }\n }\n }\n return arr[k - 1];\n}", + "test": "int main() {\n\n int arr1[] = {12, 3, 5, 7, 19};\n\n assert(func0(arr1, 5, 2) == 5);\n\n \n\n int arr2[] = {17, 24, 8, 23};\n\n assert(func0(arr2, 4, 3) == 23);\n\n \n\n int arr3[] = {16, 21, 25, 36, 4};\n\n assert(func0(arr3, 5, 4) == 25);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1306 \nlea -0x1(%rsi),%ecx\nlea 0x4(%rdi),%r10\ntest %ecx,%ecx\nje 1306 \nnopl 0x0(%rax,%rax,1)\nsub $0x1,%ecx\nmov %rdi,%rax\nmov %rcx,%r9\nlea (%r10,%rcx,4),%r8\nnopl (%rax)\nmov (%rax),%ecx\nmov 0x4(%rax),%esi\ncmp %esi,%ecx\njle 12f6 \nmov %esi,(%rax)\nmov %ecx,0x4(%rax)\nadd $0x4,%rax\ncmp %r8,%rax\njne 12e8 \nmov %r9d,%ecx\ntest %ecx,%ecx\njne 12d8 \nmovslq %edx,%rax\nmov -0x4(%rdi,%rax,4),%eax\nretq\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\nmov r9, rdi\ntest esi, esi\njle short loc_12EC\nlea r10, [rdi+4]\nloc_129F:\ncmp esi, 1\njle short loc_12E7\nnop dword ptr [rax+00h]\nloc_12A8:\nlea ecx, [rsi-2]\nmov rax, r9\nlea r8, [r10+rcx*4]\nnop word ptr [rax+rax+00h]\nloc_12B8:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd ecx, xmm0\nmovd edi, xmm1\ncmp edi, ecx\njge short loc_12D6\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_12D6:\nadd rax, 4\ncmp rax, r8\njnz short loc_12B8\nsub esi, 1\ncmp esi, 1\njg short loc_12A8\nloc_12E7:\nsub esi, 1\njnz short loc_129F\nloc_12EC:\nmovsxd rax, edx\nmov eax, [r9+rax*4-4]\nretn", + "ida_pseudo": "__int64 __fastcall func0(__m128i *a1, int a2, int a3)\n{\n __m128i *v3; // rax\n __m128i v4; // xmm0\n\n if ( a2 > 0 )\n {\n do\n {\n for ( ; a2 > 1; --a2 )\n {\n v3 = a1;\n do\n {\n v4 = _mm_loadl_epi64(v3);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v4, 229)) < _mm_cvtsi128_si32(v4) )\n v3->m128i_i64[0] = _mm_shuffle_epi32(v4, 225).m128i_u64[0];\n v3 = (__m128i *)((char *)v3 + 4);\n }\n while ( v3 != (__m128i *)((char *)a1->m128i_i64 + 4 * (unsigned int)(a2 - 2) + 4) );\n }\n --a2;\n }\n while ( a2 );\n }\n return a1->m128i_u32[a3 - 1];\n}", + "ida_strip_asm": "sub_1290:\nendbr64\nmov r9, rdi\ntest esi, esi\njle short loc_12EC\nlea r10, [rdi+4]\nloc_129F:\ncmp esi, 1\njle short loc_12E7\nnop dword ptr [rax+00h]\nloc_12A8:\nlea ecx, [rsi-2]\nmov rax, r9\nlea r8, [r10+rcx*4]\nnop word ptr [rax+rax+00h]\nloc_12B8:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd ecx, xmm0\nmovd edi, xmm1\ncmp edi, ecx\njge short loc_12D6\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_12D6:\nadd rax, 4\ncmp rax, r8\njnz short loc_12B8\nsub esi, 1\ncmp esi, 1\njg short loc_12A8\nloc_12E7:\nsub esi, 1\njnz short loc_129F\nloc_12EC:\nmovsxd rax, edx\nmov eax, [r9+rax*4-4]\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1290(__m128i *a1, int a2, int a3)\n{\n __m128i *v3; // rax\n __m128i v4; // xmm0\n\n if ( a2 > 0 )\n {\n do\n {\n for ( ; a2 > 1; --a2 )\n {\n v3 = a1;\n do\n {\n v4 = _mm_loadl_epi64(v3);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v4, 229)) < _mm_cvtsi128_si32(v4) )\n v3->m128i_i64[0] = _mm_shuffle_epi32(v4, 225).m128i_u64[0];\n v3 = (__m128i *)((char *)v3 + 4);\n }\n while ( v3 != (__m128i *)((char *)a1->m128i_i64 + 4 * (unsigned int)(a2 - 2) + 4) );\n }\n --a2;\n }\n while ( a2 );\n }\n return a1->m128i_u32[a3 - 1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1290(__m128i *a1, int a2, int a3) {\n __m128i *v3;\n __m128i v4;\n if (a2 > 0) {\n do {\n for (; a2 > 1; --a2) {\n v3 = a1;\n do {\n v4 = _mm_loadl_epi64(v3);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v4, 229)) <\n _mm_cvtsi128_si32(v4))\n v3->m128i_i64[0] = _mm_shuffle_epi32(v4, 225).m128i_u64[0];\n v3 = (__m128i *)((char *)v3 + 4);\n } while (v3 != (__m128i *)((char *)a1->m128i_i64 +\n 4 * (unsigned int)(a2 - 2) + 4));\n }\n --a2;\n } while (a2);\n }\n return a1->m128i_u32[a3 - 1];\n}", + "ida_pseudo_norm": "long long func0(__m128i *a1, int a2, int a3) {\n __m128i *v3;\n __m128i v4;\n if (a2 > 0) {\n do {\n for (; a2 > 1; --a2) {\n v3 = a1;\n do {\n v4 = _mm_loadl_epi64(v3);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v4, 229)) <\n _mm_cvtsi128_si32(v4))\n v3->m128i_i64[0] = _mm_shuffle_epi32(v4, 225).m128i_u64[0];\n v3 = (__m128i *)((char *)v3 + 4);\n } while (v3 != (__m128i *)((char *)a1->m128i_i64 +\n 4 * (unsigned int)(a2 - 2) + 4));\n }\n --a2;\n } while (a2);\n }\n return a1->m128i_u32[a3 - 1];\n}" + }, + { + "index": 101, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n, int k) {\n int i, j, temp;\n for (i = 0; i < n; i++) {\n for (j = 0; j < n - i - 1; j++) {\n if (arr[j] > arr[j + 1]) {\n temp = arr[j];\n arr[j] = arr[j + 1];\n arr[j + 1] = temp;\n }\n }\n }\n return arr[k - 1];\n}", + "test": "int main() {\n\n int arr1[] = {12, 3, 5, 7, 19};\n\n assert(func0(arr1, 5, 2) == 5);\n\n \n\n int arr2[] = {17, 24, 8, 23};\n\n assert(func0(arr2, 4, 3) == 23);\n\n \n\n int arr3[] = {16, 21, 25, 36, 4};\n\n assert(func0(arr3, 5, 4) == 25);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 12d6 \nlea -0x1(%rsi),%ecx\nlea 0x4(%rdi),%r10\ntest %ecx,%ecx\nje 12d6 \nnopl 0x0(%rax,%rax,1)\nsub $0x1,%ecx\nmov %rdi,%rax\nmov %rcx,%r9\nlea (%r10,%rcx,4),%r8\nnopl (%rax)\nmov (%rax),%ecx\nmov 0x4(%rax),%esi\ncmp %esi,%ecx\njle 12c6 \nmov %esi,(%rax)\nmov %ecx,0x4(%rax)\nadd $0x4,%rax\ncmp %r8,%rax\njne 12b8 \nmov %r9d,%ecx\ntest %ecx,%ecx\njne 12a8 \nmovslq %edx,%rax\nmov -0x4(%rdi,%rax,4),%eax\nretq\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\nmov r9, rdi\ntest esi, esi\njle short loc_12EC\nlea r10, [rdi+4]\nloc_129F:\ncmp esi, 1\njle short loc_12E7\nnop dword ptr [rax+00h]\nloc_12A8:\nlea ecx, [rsi-2]\nmov rax, r9\nlea r8, [r10+rcx*4]\nnop word ptr [rax+rax+00h]\nloc_12B8:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd ecx, xmm0\nmovd edi, xmm1\ncmp edi, ecx\njge short loc_12D6\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_12D6:\nadd rax, 4\ncmp rax, r8\njnz short loc_12B8\nsub esi, 1\ncmp esi, 1\njg short loc_12A8\nloc_12E7:\nsub esi, 1\njnz short loc_129F\nloc_12EC:\nmovsxd rax, edx\nmov eax, [r9+rax*4-4]\nretn", + "ida_pseudo": "__int64 __fastcall func0(__m128i *a1, int a2, int a3)\n{\n __m128i *v3; // rax\n __m128i v4; // xmm0\n\n if ( a2 > 0 )\n {\n do\n {\n for ( ; a2 > 1; --a2 )\n {\n v3 = a1;\n do\n {\n v4 = _mm_loadl_epi64(v3);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v4, 229)) < _mm_cvtsi128_si32(v4) )\n v3->m128i_i64[0] = _mm_shuffle_epi32(v4, 225).m128i_u64[0];\n v3 = (__m128i *)((char *)v3 + 4);\n }\n while ( v3 != (__m128i *)((char *)a1->m128i_i64 + 4 * (unsigned int)(a2 - 2) + 4) );\n }\n --a2;\n }\n while ( a2 );\n }\n return a1->m128i_u32[a3 - 1];\n}", + "ida_strip_asm": "sub_1290:\nendbr64\nmov r9, rdi\ntest esi, esi\njle short loc_12EC\nlea r10, [rdi+4]\nloc_129F:\ncmp esi, 1\njle short loc_12E7\nnop dword ptr [rax+00h]\nloc_12A8:\nlea ecx, [rsi-2]\nmov rax, r9\nlea r8, [r10+rcx*4]\nnop word ptr [rax+rax+00h]\nloc_12B8:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd ecx, xmm0\nmovd edi, xmm1\ncmp edi, ecx\njge short loc_12D6\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_12D6:\nadd rax, 4\ncmp rax, r8\njnz short loc_12B8\nsub esi, 1\ncmp esi, 1\njg short loc_12A8\nloc_12E7:\nsub esi, 1\njnz short loc_129F\nloc_12EC:\nmovsxd rax, edx\nmov eax, [r9+rax*4-4]\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1290(__m128i *a1, int a2, int a3)\n{\n __m128i *v3; // rax\n __m128i v4; // xmm0\n\n if ( a2 > 0 )\n {\n do\n {\n for ( ; a2 > 1; --a2 )\n {\n v3 = a1;\n do\n {\n v4 = _mm_loadl_epi64(v3);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v4, 229)) < _mm_cvtsi128_si32(v4) )\n v3->m128i_i64[0] = _mm_shuffle_epi32(v4, 225).m128i_u64[0];\n v3 = (__m128i *)((char *)v3 + 4);\n }\n while ( v3 != (__m128i *)((char *)a1->m128i_i64 + 4 * (unsigned int)(a2 - 2) + 4) );\n }\n --a2;\n }\n while ( a2 );\n }\n return a1->m128i_u32[a3 - 1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1290(__m128i *a1, int a2, int a3) {\n __m128i *v3;\n __m128i v4;\n if (a2 > 0) {\n do {\n for (; a2 > 1; --a2) {\n v3 = a1;\n do {\n v4 = _mm_loadl_epi64(v3);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v4, 229)) <\n _mm_cvtsi128_si32(v4))\n v3->m128i_i64[0] = _mm_shuffle_epi32(v4, 225).m128i_u64[0];\n v3 = (__m128i *)((char *)v3 + 4);\n } while (v3 != (__m128i *)((char *)a1->m128i_i64 +\n 4 * (unsigned int)(a2 - 2) + 4));\n }\n --a2;\n } while (a2);\n }\n return a1->m128i_u32[a3 - 1];\n}", + "ida_pseudo_norm": "long long func0(__m128i *a1, int a2, int a3) {\n __m128i *v3;\n __m128i v4;\n if (a2 > 0) {\n do {\n for (; a2 > 1; --a2) {\n v3 = a1;\n do {\n v4 = _mm_loadl_epi64(v3);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v4, 229)) <\n _mm_cvtsi128_si32(v4))\n v3->m128i_i64[0] = _mm_shuffle_epi32(v4, 225).m128i_u64[0];\n v3 = (__m128i *)((char *)v3 + 4);\n } while (v3 != (__m128i *)((char *)a1->m128i_i64 +\n 4 * (unsigned int)(a2 - 2) + 4));\n }\n --a2;\n } while (a2);\n }\n return a1->m128i_u32[a3 - 1];\n}" + }, + { + "index": 102, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* word, char* output) {\n int word_index = 0;\n int output_index = 0;\n int capitalize_next = 1;\n while (word[word_index] != '\\0') {\n if (word[word_index] == '_') {\n capitalize_next = 1;\n } else {\n if (capitalize_next) {\n output[output_index++] = toupper(word[word_index]);\n capitalize_next = 0;\n } else {\n output[output_index++] = word[word_index];\n }\n }\n word_index++;\n }\n output[output_index] = '\\0';\n return output;\n}", + "test": "int main() {\n\n char output[100];\n\n \n\n assert(strcmp(func0(\"python_program\", output), \"PythonProgram\") == 0);\n\n assert(strcmp(func0(\"python_language\", output), \"PythonLanguage\") == 0);\n\n assert(strcmp(func0(\"programming_language\", output), \"ProgrammingLanguage\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x1,-0x4(%rbp)\njmpq 1260 \nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x5f,%al\njne 11f4 \nmovl $0x1,-0x4(%rbp)\njmp 125c \ncmpl $0x0,-0x4(%rbp)\nje 1236 \nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmovsbl %al,%eax\nmov %eax,%edi\ncallq 1080 \nmov %eax,%ecx\nmov -0x8(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x8(%rbp)\nmovslq %eax,%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov %ecx,%edx\nmov %dl,(%rax)\nmovl $0x0,-0x4(%rbp)\njmp 125c \nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x8(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x8(%rbp)\nmovslq %eax,%rdx\nmov -0x20(%rbp),%rax\nadd %rax,%rdx\nmovzbl (%rcx),%eax\nmov %al,(%rdx)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 11d7 \nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmovb $0x0,(%rax)\nmov -0x20(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\nmov [rbp+var_4], 1\njmp loc_1260\nloc_11D7:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 5Fh ; '_'\njnz short loc_11F4\nmov [rbp+var_4], 1\njmp short loc_125C\nloc_11F4:\ncmp [rbp+var_4], 0\njz short loc_1236\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nmov edi, eax; c\ncall _toupper\nmov ecx, eax\nmov eax, [rbp+var_8]\nlea edx, [rax+1]\nmov [rbp+var_8], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov edx, ecx\nmov [rax], dl\nmov [rbp+var_4], 0\njmp short loc_125C\nloc_1236:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_8]\nlea edx, [rax+1]\nmov [rbp+var_8], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_20]\nadd rdx, rax\nmovzx eax, byte ptr [rcx]\nmov [rdx], al\nloc_125C:\nadd [rbp+var_C], 1\nloc_1260:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_11D7\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+var_20]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2)\n{\n char v2; // cl\n int v3; // eax\n int v4; // eax\n int v6; // [rsp+14h] [rbp-Ch]\n int v7; // [rsp+18h] [rbp-8h]\n int v8; // [rsp+1Ch] [rbp-4h]\n\n v6 = 0;\n v7 = 0;\n v8 = 1;\n while ( *(_BYTE *)(v6 + a1) )\n {\n if ( *(_BYTE *)(v6 + a1) == 95 )\n {\n v8 = 1;\n }\n else if ( v8 )\n {\n v2 = toupper(*(char *)(v6 + a1));\n v3 = v7++;\n *(_BYTE *)(v3 + a2) = v2;\n v8 = 0;\n }\n else\n {\n v4 = v7++;\n *(_BYTE *)(a2 + v4) = *(_BYTE *)(v6 + a1);\n }\n ++v6;\n }\n *(_BYTE *)(v7 + a2) = 0;\n return a2;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\nmov [rbp+var_4], 1\njmp loc_1260\nloc_11D7:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 5Fh ; '_'\njnz short loc_11F4\nmov [rbp+var_4], 1\njmp short loc_125C\nloc_11F4:\ncmp [rbp+var_4], 0\njz short loc_1236\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nmov edi, eax; c\ncall _toupper\nmov ecx, eax\nmov eax, [rbp+var_8]\nlea edx, [rax+1]\nmov [rbp+var_8], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov edx, ecx\nmov [rax], dl\nmov [rbp+var_4], 0\njmp short loc_125C\nloc_1236:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_8]\nlea edx, [rax+1]\nmov [rbp+var_8], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_20]\nadd rdx, rax\nmovzx eax, byte ptr [rcx]\nmov [rdx], al\nloc_125C:\nadd [rbp+var_C], 1\nloc_1260:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_11D7\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+var_20]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(__int64 a1, __int64 a2)\n{\n char v2; // cl\n int v3; // eax\n int v4; // eax\n int v6; // [rsp+14h] [rbp-Ch]\n int v7; // [rsp+18h] [rbp-8h]\n int v8; // [rsp+1Ch] [rbp-4h]\n\n v6 = 0;\n v7 = 0;\n v8 = 1;\n while ( *(_BYTE *)(v6 + a1) )\n {\n if ( *(_BYTE *)(v6 + a1) == 95 )\n {\n v8 = 1;\n }\n else if ( v8 )\n {\n v2 = toupper(*(char *)(v6 + a1));\n v3 = v7++;\n *(_BYTE *)(v3 + a2) = v2;\n v8 = 0;\n }\n else\n {\n v4 = v7++;\n *(_BYTE *)(a2 + v4) = *(_BYTE *)(v6 + a1);\n }\n ++v6;\n }\n *(_BYTE *)(v7 + a2) = 0;\n return a2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(long long a1, long long a2) {\n char v2;\n int v3;\n int v4;\n int v6;\n int v7;\n int v8;\n v6 = 0;\n v7 = 0;\n v8 = 1;\n while (*(uint8_t *)(v6 + a1)) {\n if (*(uint8_t *)(v6 + a1) == 95) {\n v8 = 1;\n } else if (v8) {\n v2 = toupper(*(char *)(v6 + a1));\n v3 = v7++;\n *(uint8_t *)(v3 + a2) = v2;\n v8 = 0;\n } else {\n v4 = v7++;\n *(uint8_t *)(a2 + v4) = *(uint8_t *)(v6 + a1);\n }\n ++v6;\n }\n *(uint8_t *)(v7 + a2) = 0;\n return a2;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2) {\n char v2;\n int v3;\n int v4;\n int v6;\n int v7;\n int v8;\n v6 = 0;\n v7 = 0;\n v8 = 1;\n while (*(uint8_t *)(v6 + a1)) {\n if (*(uint8_t *)(v6 + a1) == 95) {\n v8 = 1;\n } else if (v8) {\n v2 = toupper(*(char *)(v6 + a1));\n v3 = v7++;\n *(uint8_t *)(v3 + a2) = v2;\n v8 = 0;\n } else {\n v4 = v7++;\n *(uint8_t *)(a2 + v4) = *(uint8_t *)(v6 + a1);\n }\n ++v6;\n }\n *(uint8_t *)(v7 + a2) = 0;\n return a2;\n}" + }, + { + "index": 102, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* word, char* output) {\n int word_index = 0;\n int output_index = 0;\n int capitalize_next = 1;\n while (word[word_index] != '\\0') {\n if (word[word_index] == '_') {\n capitalize_next = 1;\n } else {\n if (capitalize_next) {\n output[output_index++] = toupper(word[word_index]);\n capitalize_next = 0;\n } else {\n output[output_index++] = word[word_index];\n }\n }\n word_index++;\n }\n output[output_index] = '\\0';\n return output;\n}", + "test": "int main() {\n\n char output[100];\n\n \n\n assert(strcmp(func0(\"python_program\", output), \"PythonProgram\") == 0);\n\n assert(strcmp(func0(\"python_language\", output), \"PythonLanguage\") == 0);\n\n assert(strcmp(func0(\"programming_language\", output), \"ProgrammingLanguage\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rsi,%r13\nmovzbl (%rdi),%ebx\ntest %bl,%bl\nje 120d \nlea 0x1(%rdi),%rbp\nmov $0x0,%r12d\nmov $0x1,%eax\nmov $0x1,%r14d\nmov $0x0,%r15d\njmp 11e0 \nmovslq %r12d,%rdx\nmov %bl,0x0(%r13,%rdx,1)\nlea 0x1(%r12),%r12d\njmp 11d4 \nmov %r14d,%eax\nadd $0x1,%rbp\nmovzbl -0x1(%rbp),%ebx\ntest %bl,%bl\nje 1213 \ncmp $0x5f,%bl\nje 11d1 \ntest %eax,%eax\nje 11c2 \ncallq 1070 <__ctype_toupper_loc@plt>\nmov %rax,%rdx\nmovslq %r12d,%rax\nmovsbq %bl,%rbx\nmov (%rdx),%rdx\nmov (%rdx,%rbx,4),%edx\nmov %dl,0x0(%r13,%rax,1)\nlea 0x1(%r12),%r12d\nmov %r15d,%eax\njmp 11d4 \nmov $0x0,%r12d\nmovslq %r12d,%r12\nmovb $0x0,0x0(%r13,%r12,1)\nmov %r13,%rax\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r13, rsi\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_122D\nlea rbp, [rdi+1]\nmov r12d, 0\nmov eax, 1\nmov r14d, 1\nmov r15d, 0\njmp short loc_1200\nloc_11E2:\nmovsxd rdx, r12d\nmov [r13+rdx+0], bl\nlea r12d, [r12+1]\njmp short loc_11F4\nloc_11F1:\nmov eax, r14d\nloc_11F4:\nadd rbp, 1\nmovzx ebx, byte ptr [rbp-1]\ntest bl, bl\njz short loc_1233\nloc_1200:\ncmp bl, 5Fh ; '_'\njz short loc_11F1\ntest eax, eax\njz short loc_11E2\ncall ___ctype_toupper_loc\nmov rdx, rax\nmovsxd rax, r12d\nmovsx rbx, bl\nmov rdx, [rdx]\nmov edx, [rdx+rbx*4]\nmov [r13+rax+0], dl\nlea r12d, [r12+1]\nmov eax, r15d\njmp short loc_11F4\nloc_122D:\nmov r12d, 0\nloc_1233:\nmovsxd r12, r12d\nmov byte ptr [r13+r12+0], 0\nmov rax, r13\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "__int64 __fastcall func0(char *a1, __int64 a2)\n{\n char v2; // bl\n char *v3; // rbp\n int v4; // r12d\n int v5; // eax\n\n v2 = *a1;\n if ( *a1 )\n {\n v3 = a1 + 1;\n v4 = 0;\n v5 = 1;\n do\n {\n if ( v2 == 95 )\n {\n v5 = 1;\n }\n else if ( v5 )\n {\n *(_BYTE *)(a2 + v4++) = (*__ctype_toupper_loc())[v2];\n v5 = 0;\n }\n else\n {\n *(_BYTE *)(a2 + v4++) = v2;\n }\n v2 = *v3++;\n }\n while ( v2 );\n }\n else\n {\n v4 = 0;\n }\n *(_BYTE *)(a2 + v4) = 0;\n return a2;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r13, rsi\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_122D\nlea rbp, [rdi+1]\nmov r12d, 0\nmov eax, 1\nmov r14d, 1\nmov r15d, 0\njmp short loc_1200\nloc_11E2:\nmovsxd rdx, r12d\nmov [r13+rdx+0], bl\nlea r12d, [r12+1]\njmp short loc_11F4\nloc_11F1:\nmov eax, r14d\nloc_11F4:\nadd rbp, 1\nmovzx ebx, byte ptr [rbp-1]\ntest bl, bl\njz short loc_1233\nloc_1200:\ncmp bl, 5Fh ; '_'\njz short loc_11F1\ntest eax, eax\njz short loc_11E2\ncall ___ctype_toupper_loc\nmov rdx, rax\nmovsxd rax, r12d\nmovsx rbx, bl\nmov rdx, [rdx]\nmov edx, [rdx+rbx*4]\nmov [r13+rax+0], dl\nlea r12d, [r12+1]\nmov eax, r15d\njmp short loc_11F4\nloc_122D:\nmov r12d, 0\nloc_1233:\nmovsxd r12, r12d\nmov byte ptr [r13+r12+0], 0\nmov rax, r13\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(char *a1, __int64 a2)\n{\n char v2; // bl\n char *v3; // rbp\n int v4; // r12d\n int v5; // eax\n\n v2 = *a1;\n if ( *a1 )\n {\n v3 = a1 + 1;\n v4 = 0;\n v5 = 1;\n do\n {\n if ( v2 == 95 )\n {\n v5 = 1;\n }\n else if ( v5 )\n {\n *(_BYTE *)(a2 + v4++) = (*__ctype_toupper_loc())[v2];\n v5 = 0;\n }\n else\n {\n *(_BYTE *)(a2 + v4++) = v2;\n }\n v2 = *v3++;\n }\n while ( v2 );\n }\n else\n {\n v4 = 0;\n }\n *(_BYTE *)(a2 + v4) = 0;\n return a2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(char *a1, long long a2) {\n char v2;\n char *v3;\n int v4;\n int v5;\n v2 = *a1;\n if (*a1) {\n v3 = a1 + 1;\n v4 = 0;\n v5 = 1;\n do {\n if (v2 == 95) {\n v5 = 1;\n } else if (v5) {\n *(uint8_t *)(a2 + v4++) = (*__ctype_toupper_loc())[v2];\n v5 = 0;\n } else {\n *(uint8_t *)(a2 + v4++) = v2;\n }\n v2 = *v3++;\n } while (v2);\n } else {\n v4 = 0;\n }\n *(uint8_t *)(a2 + v4) = 0;\n return a2;\n}", + "ida_pseudo_norm": "long long func0(char *a1, long long a2) {\n char v2;\n char *v3;\n int v4;\n int v5;\n v2 = *a1;\n if (*a1) {\n v3 = a1 + 1;\n v4 = 0;\n v5 = 1;\n do {\n if (v2 == 95) {\n v5 = 1;\n } else if (v5) {\n *(uint8_t *)(a2 + v4++) = (*__ctype_toupper_loc())[v2];\n v5 = 0;\n } else {\n *(uint8_t *)(a2 + v4++) = v2;\n }\n v2 = *v3++;\n } while (v2);\n } else {\n v4 = 0;\n }\n *(uint8_t *)(a2 + v4) = 0;\n return a2;\n}" + }, + { + "index": 102, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* word, char* output) {\n int word_index = 0;\n int output_index = 0;\n int capitalize_next = 1;\n while (word[word_index] != '\\0') {\n if (word[word_index] == '_') {\n capitalize_next = 1;\n } else {\n if (capitalize_next) {\n output[output_index++] = toupper(word[word_index]);\n capitalize_next = 0;\n } else {\n output[output_index++] = word[word_index];\n }\n }\n word_index++;\n }\n output[output_index] = '\\0';\n return output;\n}", + "test": "int main() {\n\n char output[100];\n\n \n\n assert(strcmp(func0(\"python_program\", output), \"PythonProgram\") == 0);\n\n assert(strcmp(func0(\"python_language\", output), \"PythonLanguage\") == 0);\n\n assert(strcmp(func0(\"programming_language\", output), \"ProgrammingLanguage\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\nmov %rsi,%r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmovsbq (%rdi),%rbx\ntest %bl,%bl\nje 1368 \nlea 0x1(%rdi),%rbp\nxor %r15d,%r15d\nmov $0x1,%eax\nxor %r13d,%r13d\njmp 1322 \nnopw 0x0(%rax,%rax,1)\nadd $0x1,%r15d\nmovslq %r15d,%r13\nlea (%r14,%r13,1),%rdx\ntest %eax,%eax\nje 1358 \nmov %rdx,0x8(%rsp)\ncallq 1070 <__ctype_toupper_loc@plt>\nmov 0x8(%rsp),%rdx\nmov (%rax),%rax\nmov (%rax,%rbx,4),%eax\nmov %al,(%r12)\nmov %rdx,%r12\nxor %eax,%eax\nmovsbq 0x0(%rbp),%rbx\nadd $0x1,%rbp\ntest %bl,%bl\nje 133d \nlea (%r14,%r13,1),%r12\ncmp $0x5f,%bl\njne 12e8 \nmovsbq 0x0(%rbp),%rbx\nadd $0x1,%rbp\nmov $0x1,%eax\ntest %bl,%bl\njne 1322 \nmovb $0x0,(%r12)\nadd $0x18,%rsp\nmov %r14,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\nmov %bl,(%r12)\nmov %rdx,%r12\njmp 1315 \nnopl 0x0(%rax)\nmov %rsi,%r12\njmp 133d \nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r13\nmov r13, rsi\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmovsx rbx, byte ptr [rdi]\ntest bl, bl\njz short loc_1340\nlea rbp, [rdi+1]\nxor r12d, r12d\nmov eax, 1\njmp short loc_130B\nloc_12E0:\ntest eax, eax\njz short loc_12F0\ncall ___ctype_toupper_loc\nmov rax, [rax]\nmovzx ebx, byte ptr [rax+rbx*4]\nloc_12F0:\nmovsxd rax, r12d\nadd rbp, 1\nadd r12d, 1\nmov [r13+rax+0], bl\nmovsx rbx, byte ptr [rbp-1]\nxor eax, eax\ntest bl, bl\njz short loc_1322\nloc_130B:\ncmp bl, 5Fh ; '_'\njnz short loc_12E0\nmovsx rbx, byte ptr [rbp+0]\nadd rbp, 1\nmov eax, 1\ntest bl, bl\njnz short loc_130B\nloc_1322:\nmovsxd r12, r12d\nadd r12, r13\nloc_1328:\nmov byte ptr [r12], 0\nadd rsp, 8\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1340:\nmov r12, rsi\njmp short loc_1328", + "ida_pseudo": "_BYTE *__fastcall func0(char *a1, _BYTE *a2)\n{\n __int64 v2; // rbx\n char *v3; // rbp\n int v4; // r12d\n int v5; // eax\n __int64 v6; // rax\n _BYTE *v7; // r12\n\n v2 = *a1;\n if ( (_BYTE)v2 )\n {\n v3 = a1 + 1;\n v4 = 0;\n v5 = 1;\n do\n {\n while ( (_BYTE)v2 == 95 )\n {\n v2 = *v3++;\n v5 = 1;\n if ( !(_BYTE)v2 )\n goto LABEL_8;\n }\n if ( v5 )\n LOBYTE(v2) = (*__ctype_toupper_loc())[v2];\n v6 = v4;\n ++v3;\n ++v4;\n a2[v6] = v2;\n v2 = *(v3 - 1);\n v5 = 0;\n }\n while ( (_BYTE)v2 );\nLABEL_8:\n v7 = &a2[v4];\n }\n else\n {\n v7 = a2;\n }\n *v7 = 0;\n return a2;\n}", + "ida_strip_asm": "sub_12B0:\nendbr64\npush r13\nmov r13, rsi\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmovsx rbx, byte ptr [rdi]\ntest bl, bl\njz short loc_1340\nlea rbp, [rdi+1]\nxor r12d, r12d\nmov eax, 1\njmp short loc_130B\nloc_12E0:\ntest eax, eax\njz short loc_12F0\ncall ___ctype_toupper_loc\nmov rax, [rax]\nmovzx ebx, byte ptr [rax+rbx*4]\nloc_12F0:\nmovsxd rax, r12d\nadd rbp, 1\nadd r12d, 1\nmov [r13+rax+0], bl\nmovsx rbx, byte ptr [rbp-1]\nxor eax, eax\ntest bl, bl\njz short loc_1322\nloc_130B:\ncmp bl, 5Fh ; '_'\njnz short loc_12E0\nmovsx rbx, byte ptr [rbp+0]\nadd rbp, 1\nmov eax, 1\ntest bl, bl\njnz short loc_130B\nloc_1322:\nmovsxd r12, r12d\nadd r12, r13\nloc_1328:\nmov byte ptr [r12], 0\nadd rsp, 8\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1340:\nmov r12, rsi\njmp short loc_1328", + "ida_strip_pseudo": "_BYTE *__fastcall sub_12B0(char *a1, _BYTE *a2)\n{\n __int64 v2; // rbx\n char *v3; // rbp\n int v4; // r12d\n int v5; // eax\n __int64 v6; // rax\n _BYTE *v7; // r12\n\n v2 = *a1;\n if ( (_BYTE)v2 )\n {\n v3 = a1 + 1;\n v4 = 0;\n v5 = 1;\n do\n {\n while ( (_BYTE)v2 == 95 )\n {\n v2 = *v3++;\n v5 = 1;\n if ( !(_BYTE)v2 )\n goto LABEL_8;\n }\n if ( v5 )\n LOBYTE(v2) = (*__ctype_toupper_loc())[v2];\n v6 = v4;\n ++v3;\n ++v4;\n a2[v6] = v2;\n v2 = *(v3 - 1);\n v5 = 0;\n }\n while ( (_BYTE)v2 );\nLABEL_8:\n v7 = &a2[v4];\n }\n else\n {\n v7 = a2;\n }\n *v7 = 0;\n return a2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_12B0(char *a1, uint8_t *a2) {\n long long v2;\n char *v3;\n int v4;\n int v5;\n long long v6;\n uint8_t *v7;\n v2 = *a1;\n if ((uint8_t)v2) {\n v3 = a1 + 1;\n v4 = 0;\n v5 = 1;\n do {\n while ((uint8_t)v2 == 95) {\n v2 = *v3++;\n v5 = 1;\n if (!(uint8_t)v2) goto LABEL_8;\n }\n if (v5) LOBYTE(v2) = (*__ctype_toupper_loc())[v2];\n v6 = v4;\n ++v3;\n ++v4;\n a2[v6] = v2;\n v2 = *(v3 - 1);\n v5 = 0;\n } while ((uint8_t)v2);\n LABEL_8:\n v7 = &a2[v4];\n } else {\n v7 = a2;\n }\n *v7 = 0;\n return a2;\n}", + "ida_pseudo_norm": "uint8_t *func0(char *a1, uint8_t *a2) {\n long long v2;\n char *v3;\n int v4;\n int v5;\n long long v6;\n uint8_t *v7;\n v2 = *a1;\n if ((uint8_t)v2) {\n v3 = a1 + 1;\n v4 = 0;\n v5 = 1;\n do {\n while ((uint8_t)v2 == 95) {\n v2 = *v3++;\n v5 = 1;\n if (!(uint8_t)v2) goto LABEL_8;\n }\n if (v5) LOBYTE(v2) = (*__ctype_toupper_loc())[v2];\n v6 = v4;\n ++v3;\n ++v4;\n a2[v6] = v2;\n v2 = *(v3 - 1);\n v5 = 0;\n } while ((uint8_t)v2);\n LABEL_8:\n v7 = &a2[v4];\n } else {\n v7 = a2;\n }\n *v7 = 0;\n return a2;\n}" + }, + { + "index": 102, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* word, char* output) {\n int word_index = 0;\n int output_index = 0;\n int capitalize_next = 1;\n while (word[word_index] != '\\0') {\n if (word[word_index] == '_') {\n capitalize_next = 1;\n } else {\n if (capitalize_next) {\n output[output_index++] = toupper(word[word_index]);\n capitalize_next = 0;\n } else {\n output[output_index++] = word[word_index];\n }\n }\n word_index++;\n }\n output[output_index] = '\\0';\n return output;\n}", + "test": "int main() {\n\n char output[100];\n\n \n\n assert(strcmp(func0(\"python_program\", output), \"PythonProgram\") == 0);\n\n assert(strcmp(func0(\"python_language\", output), \"PythonLanguage\") == 0);\n\n assert(strcmp(func0(\"programming_language\", output), \"ProgrammingLanguage\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\nmov %rsi,%r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmovsbq (%rdi),%rbx\ntest %bl,%bl\nje 1368 \nlea 0x1(%rdi),%rbp\nxor %r15d,%r15d\nmov $0x1,%eax\nxor %r13d,%r13d\njmp 1322 \nnopw 0x0(%rax,%rax,1)\nadd $0x1,%r15d\nmovslq %r15d,%r13\nlea (%r14,%r13,1),%rdx\ntest %eax,%eax\nje 1358 \nmov %rdx,0x8(%rsp)\ncallq 1070 <__ctype_toupper_loc@plt>\nmov 0x8(%rsp),%rdx\nmov (%rax),%rax\nmov (%rax,%rbx,4),%eax\nmov %al,(%r12)\nmov %rdx,%r12\nxor %eax,%eax\nmovsbq 0x0(%rbp),%rbx\nadd $0x1,%rbp\ntest %bl,%bl\nje 133d \nlea (%r14,%r13,1),%r12\ncmp $0x5f,%bl\njne 12e8 \nmovsbq 0x0(%rbp),%rbx\nadd $0x1,%rbp\nmov $0x1,%eax\ntest %bl,%bl\njne 1322 \nmovb $0x0,(%r12)\nadd $0x18,%rsp\nmov %r14,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\nmov %bl,(%r12)\nmov %rdx,%r12\njmp 1315 \nnopl 0x0(%rax)\nmov %rsi,%r12\njmp 133d \nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r13\nmov r13, rsi\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmovsx rbx, byte ptr [rdi]\ntest bl, bl\njz short loc_1340\nlea rbp, [rdi+1]\nxor r12d, r12d\nmov eax, 1\njmp short loc_130B\nloc_12E0:\ntest eax, eax\njz short loc_12F0\ncall ___ctype_toupper_loc\nmov rax, [rax]\nmovzx ebx, byte ptr [rax+rbx*4]\nloc_12F0:\nmovsxd rax, r12d\nadd rbp, 1\nadd r12d, 1\nmov [r13+rax+0], bl\nmovsx rbx, byte ptr [rbp-1]\nxor eax, eax\ntest bl, bl\njz short loc_1322\nloc_130B:\ncmp bl, 5Fh ; '_'\njnz short loc_12E0\nmovsx rbx, byte ptr [rbp+0]\nadd rbp, 1\nmov eax, 1\ntest bl, bl\njnz short loc_130B\nloc_1322:\nmovsxd r12, r12d\nadd r12, r13\nloc_1328:\nmov byte ptr [r12], 0\nadd rsp, 8\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1340:\nmov r12, rsi\njmp short loc_1328", + "ida_pseudo": "_BYTE *__fastcall func0(char *a1, _BYTE *a2)\n{\n __int64 v2; // rbx\n char *v3; // rbp\n int v4; // r12d\n int v5; // eax\n __int64 v6; // rax\n _BYTE *v7; // r12\n\n v2 = *a1;\n if ( (_BYTE)v2 )\n {\n v3 = a1 + 1;\n v4 = 0;\n v5 = 1;\n do\n {\n while ( (_BYTE)v2 == 95 )\n {\n v2 = *v3++;\n v5 = 1;\n if ( !(_BYTE)v2 )\n goto LABEL_8;\n }\n if ( v5 )\n LOBYTE(v2) = (*__ctype_toupper_loc())[v2];\n v6 = v4;\n ++v3;\n ++v4;\n a2[v6] = v2;\n v2 = *(v3 - 1);\n v5 = 0;\n }\n while ( (_BYTE)v2 );\nLABEL_8:\n v7 = &a2[v4];\n }\n else\n {\n v7 = a2;\n }\n *v7 = 0;\n return a2;\n}", + "ida_strip_asm": "sub_12B0:\nendbr64\npush r13\nmov r13, rsi\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmovsx rbx, byte ptr [rdi]\ntest bl, bl\njz short loc_1340\nlea rbp, [rdi+1]\nxor r12d, r12d\nmov eax, 1\njmp short loc_130B\nloc_12E0:\ntest eax, eax\njz short loc_12F0\ncall ___ctype_toupper_loc\nmov rax, [rax]\nmovzx ebx, byte ptr [rax+rbx*4]\nloc_12F0:\nmovsxd rax, r12d\nadd rbp, 1\nadd r12d, 1\nmov [r13+rax+0], bl\nmovsx rbx, byte ptr [rbp-1]\nxor eax, eax\ntest bl, bl\njz short loc_1322\nloc_130B:\ncmp bl, 5Fh ; '_'\njnz short loc_12E0\nmovsx rbx, byte ptr [rbp+0]\nadd rbp, 1\nmov eax, 1\ntest bl, bl\njnz short loc_130B\nloc_1322:\nmovsxd r12, r12d\nadd r12, r13\nloc_1328:\nmov byte ptr [r12], 0\nadd rsp, 8\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1340:\nmov r12, rsi\njmp short loc_1328", + "ida_strip_pseudo": "_BYTE *__fastcall sub_12B0(char *a1, _BYTE *a2)\n{\n __int64 v2; // rbx\n char *v3; // rbp\n int v4; // r12d\n int v5; // eax\n __int64 v6; // rax\n _BYTE *v7; // r12\n\n v2 = *a1;\n if ( (_BYTE)v2 )\n {\n v3 = a1 + 1;\n v4 = 0;\n v5 = 1;\n do\n {\n while ( (_BYTE)v2 == 95 )\n {\n v2 = *v3++;\n v5 = 1;\n if ( !(_BYTE)v2 )\n goto LABEL_8;\n }\n if ( v5 )\n LOBYTE(v2) = (*__ctype_toupper_loc())[v2];\n v6 = v4;\n ++v3;\n ++v4;\n a2[v6] = v2;\n v2 = *(v3 - 1);\n v5 = 0;\n }\n while ( (_BYTE)v2 );\nLABEL_8:\n v7 = &a2[v4];\n }\n else\n {\n v7 = a2;\n }\n *v7 = 0;\n return a2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_12B0(char *a1, uint8_t *a2) {\n long long v2;\n char *v3;\n int v4;\n int v5;\n long long v6;\n uint8_t *v7;\n v2 = *a1;\n if ((uint8_t)v2) {\n v3 = a1 + 1;\n v4 = 0;\n v5 = 1;\n do {\n while ((uint8_t)v2 == 95) {\n v2 = *v3++;\n v5 = 1;\n if (!(uint8_t)v2) goto LABEL_8;\n }\n if (v5) LOBYTE(v2) = (*__ctype_toupper_loc())[v2];\n v6 = v4;\n ++v3;\n ++v4;\n a2[v6] = v2;\n v2 = *(v3 - 1);\n v5 = 0;\n } while ((uint8_t)v2);\n LABEL_8:\n v7 = &a2[v4];\n } else {\n v7 = a2;\n }\n *v7 = 0;\n return a2;\n}", + "ida_pseudo_norm": "uint8_t *func0(char *a1, uint8_t *a2) {\n long long v2;\n char *v3;\n int v4;\n int v5;\n long long v6;\n uint8_t *v7;\n v2 = *a1;\n if ((uint8_t)v2) {\n v3 = a1 + 1;\n v4 = 0;\n v5 = 1;\n do {\n while ((uint8_t)v2 == 95) {\n v2 = *v3++;\n v5 = 1;\n if (!(uint8_t)v2) goto LABEL_8;\n }\n if (v5) LOBYTE(v2) = (*__ctype_toupper_loc())[v2];\n v6 = v4;\n ++v3;\n ++v4;\n a2[v6] = v2;\n v2 = *(v3 - 1);\n v5 = 0;\n } while ((uint8_t)v2);\n LABEL_8:\n v7 = &a2[v4];\n } else {\n v7 = a2;\n }\n *v7 = 0;\n return a2;\n}" + }, + { + "index": 103, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n, int m) {\n if (m >= n || n == 0) {\n return 0;\n }\n if (m == 0) {\n return 1;\n }\n return ((n - m) * func0(n - 1, m - 1) + (m + 1) * func0(n - 1, m));\n}", + "test": "int main() {\n\n assert(func0(3, 1) == 4);\n\n assert(func0(4, 1) == 11);\n\n assert(func0(5, 3) == 26);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r12\npush %rbx\nsub $0x10,%rsp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov -0x18(%rbp),%eax\ncmp -0x14(%rbp),%eax\njge 116c \ncmpl $0x0,-0x14(%rbp)\njne 1173 \nmov $0x0,%eax\njmp 11bf \ncmpl $0x0,-0x18(%rbp)\njne 1180 \nmov $0x1,%eax\njmp 11bf \nmov -0x14(%rbp),%eax\nsub -0x18(%rbp),%eax\nmov %eax,%ebx\nmov -0x18(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x14(%rbp),%eax\nsub $0x1,%eax\nmov %edx,%esi\nmov %eax,%edi\ncallq 1149 \nimul %eax,%ebx\nmov -0x18(%rbp),%eax\nlea 0x1(%rax),%r12d\nmov -0x14(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x18(%rbp),%eax\nmov %eax,%esi\nmov %edx,%edi\ncallq 1149 \nimul %r12d,%eax\nadd %ebx,%eax\nadd $0x10,%rsp\npop %rbx\npop %r12\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r12\npush rbx\nsub rsp, 10h\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_14]\njge short loc_116C\ncmp [rbp+var_14], 0\njnz short loc_1173\nloc_116C:\nmov eax, 0\njmp short loc_11BF\nloc_1173:\ncmp [rbp+var_18], 0\njnz short loc_1180\nmov eax, 1\njmp short loc_11BF\nloc_1180:\nmov eax, [rbp+var_14]\nsub eax, [rbp+var_18]\nmov ebx, eax\nmov eax, [rbp+var_18]\nlea edx, [rax-1]\nmov eax, [rbp+var_14]\nsub eax, 1\nmov esi, edx\nmov edi, eax\ncall func0\nimul ebx, eax\nmov eax, [rbp+var_18]\nlea r12d, [rax+1]\nmov eax, [rbp+var_14]\nlea edx, [rax-1]\nmov eax, [rbp+var_18]\nmov esi, eax\nmov edi, edx\ncall func0\nimul eax, r12d\nadd eax, ebx\nloc_11BF:\nadd rsp, 10h\npop rbx\npop r12\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, unsigned int a2)\n{\n int v3; // ebx\n\n if ( (int)a2 >= a1 || !a1 )\n return 0LL;\n if ( !a2 )\n return 1LL;\n v3 = func0((unsigned int)(a1 - 1), a2 - 1) * (a1 - a2);\n return v3 + (a2 + 1) * (unsigned int)func0((unsigned int)(a1 - 1), a2);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\npush r12\npush rbx\nsub rsp, 10h\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_14]\njge short loc_116C\ncmp [rbp+var_14], 0\njnz short loc_1173\nloc_116C:\nmov eax, 0\njmp short loc_11BF\nloc_1173:\ncmp [rbp+var_18], 0\njnz short loc_1180\nmov eax, 1\njmp short loc_11BF\nloc_1180:\nmov eax, [rbp+var_14]\nsub eax, [rbp+var_18]\nmov ebx, eax\nmov eax, [rbp+var_18]\nlea edx, [rax-1]\nmov eax, [rbp+var_14]\nsub eax, 1\nmov esi, edx\nmov edi, eax\ncall sub_1149\nimul ebx, eax\nmov eax, [rbp+var_18]\nlea r12d, [rax+1]\nmov eax, [rbp+var_14]\nlea edx, [rax-1]\nmov eax, [rbp+var_18]\nmov esi, eax\nmov edi, edx\ncall sub_1149\nimul eax, r12d\nadd eax, ebx\nloc_11BF:\nadd rsp, 10h\npop rbx\npop r12\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, unsigned int a2)\n{\n int v3; // ebx\n\n if ( (int)a2 >= a1 || !a1 )\n return 0LL;\n if ( !a2 )\n return 1LL;\n v3 = sub_1149((unsigned int)(a1 - 1), a2 - 1) * (a1 - a2);\n return v3 + (a2 + 1) * (unsigned int)sub_1149((unsigned int)(a1 - 1), a2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, unsigned int a2) {\n int v3;\n if ((int)a2 >= a1 || !a1) return 0LL;\n if (!a2) return 1LL;\n v3 = sub_1149((unsigned int)(a1 - 1), a2 - 1) * (a1 - a2);\n return v3 + (a2 + 1) * (unsigned int)sub_1149((unsigned int)(a1 - 1), a2);\n}", + "ida_pseudo_norm": "long long func0(int a1, unsigned int a2) {\n int v3;\n if ((int)a2 >= a1 || !a1) return 0LL;\n if (!a2) return 1LL;\n v3 = func0((unsigned int)(a1 - 1), a2 - 1) * (a1 - a2);\n return v3 + (a2 + 1) * (unsigned int)func0((unsigned int)(a1 - 1), a2);\n}" + }, + { + "index": 103, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n, int m) {\n if (m >= n || n == 0) {\n return 0;\n }\n if (m == 0) {\n return 1;\n }\n return ((n - m) * func0(n - 1, m - 1) + (m + 1) * func0(n - 1, m));\n}", + "test": "int main() {\n\n assert(func0(3, 1) == 4);\n\n assert(func0(4, 1) == 11);\n\n assert(func0(5, 3) == 26);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ncmp %edi,%esi\njge 119d \npush %r12\npush %rbp\npush %rbx\nmov %esi,%ebx\ntest %edi,%edi\nje 1196 \nmov $0x1,%eax\ntest %esi,%esi\njne 1169 \npop %rbx\npop %rbp\npop %r12\nretq\nmov %edi,%r12d\nsub %esi,%r12d\nlea -0x1(%rdi),%ebp\nlea -0x1(%rsi),%esi\nmov %ebp,%edi\ncallq 1149 \nimul %eax,%r12d\nmov %ebx,%esi\nmov %ebp,%edi\ncallq 1149 \nmov %eax,%esi\nlea 0x1(%rbx),%eax\nimul %esi,%eax\nadd %r12d,%eax\njmp 1164 \nmov $0x0,%eax\njmp 1164 \nmov $0x0,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ncmp esi, edi\njge short loc_119C\npush r12\npush rbp\npush rbx\nmov ebx, esi\ntest edi, edi\njz short loc_1195\nmov eax, 1\ntest esi, esi\njnz short loc_1169\nloc_1164:\npop rbx\npop rbp\npop r12\nretn\nloc_1169:\nmov r12d, edi\nsub r12d, esi\nlea ebp, [rdi-1]\nlea esi, [rsi-1]\nmov edi, ebp\ncall func0\nimul r12d, eax\nmov esi, ebx\nmov edi, ebp\ncall func0\nadd ebx, 1\nimul ebx, eax\nlea eax, [rbx+r12]\njmp short loc_1164\nloc_1195:\nmov eax, 0\njmp short loc_1164\nloc_119C:\nmov eax, 0\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, unsigned int a2)\n{\n __int64 result; // rax\n int v3; // r12d\n\n if ( (int)a2 >= a1 )\n return 0LL;\n if ( !a1 )\n return 0LL;\n result = 1LL;\n if ( a2 )\n {\n v3 = func0((unsigned int)(a1 - 1), a2 - 1) * (a1 - a2);\n return (unsigned int)func0((unsigned int)(a1 - 1), a2) * (a2 + 1) + v3;\n }\n return result;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ncmp esi, edi\njge short loc_119C\npush r12\npush rbp\npush rbx\nmov ebx, esi\ntest edi, edi\njz short loc_1195\nmov eax, 1\ntest esi, esi\njnz short loc_1169\nloc_1164:\npop rbx\npop rbp\npop r12\nretn\nloc_1169:\nmov r12d, edi\nsub r12d, esi\nlea ebp, [rdi-1]\nlea esi, [rsi-1]\nmov edi, ebp\ncall sub_1149\nimul r12d, eax\nmov esi, ebx\nmov edi, ebp\ncall sub_1149\nadd ebx, 1\nimul ebx, eax\nlea eax, [rbx+r12]\njmp short loc_1164\nloc_1195:\nmov eax, 0\njmp short loc_1164\nloc_119C:\nmov eax, 0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, unsigned int a2)\n{\n __int64 result; // rax\n int v3; // r12d\n\n if ( (int)a2 >= a1 )\n return 0LL;\n if ( !a1 )\n return 0LL;\n result = 1LL;\n if ( a2 )\n {\n v3 = sub_1149((unsigned int)(a1 - 1), a2 - 1) * (a1 - a2);\n return (unsigned int)sub_1149((unsigned int)(a1 - 1), a2) * (a2 + 1) + v3;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, unsigned int a2) {\n long long result;\n int v3;\n if ((int)a2 >= a1) return 0LL;\n if (!a1) return 0LL;\n result = 1LL;\n if (a2) {\n v3 = sub_1149((unsigned int)(a1 - 1), a2 - 1) * (a1 - a2);\n return (unsigned int)sub_1149((unsigned int)(a1 - 1), a2) * (a2 + 1) + v3;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(int a1, unsigned int a2) {\n long long result;\n int v3;\n if ((int)a2 >= a1) return 0LL;\n if (!a1) return 0LL;\n result = 1LL;\n if (a2) {\n v3 = func0((unsigned int)(a1 - 1), a2 - 1) * (a1 - a2);\n return (unsigned int)func0((unsigned int)(a1 - 1), a2) * (a2 + 1) + v3;\n }\n return result;\n}" + }, + { + "index": 103, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n, int m) {\n if (m >= n || n == 0) {\n return 0;\n }\n if (m == 0) {\n return 1;\n }\n return ((n - m) * func0(n - 1, m - 1) + (m + 1) * func0(n - 1, m));\n}", + "test": "int main() {\n\n assert(func0(3, 1) == 4);\n\n assert(func0(4, 1) == 11);\n\n assert(func0(5, 3) == 26);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\ntest %edi,%edi\nje 1280 \nmov %edi,%ebx\nmov %esi,%r13d\ncmp %esi,%edi\njle 1280 \ntest %esi,%esi\nje 1288 \nlea 0x1(%rsi),%eax\nlea -0x1(%rsi),%r12d\nmov $0x1,%r15d\nxor %ebp,%ebp\nmov %eax,0xc(%rsp)\nnopw %cs:0x0(%rax,%rax,1)\nmov %ebx,%r14d\nsub $0x1,%ebx\nmov %r12d,%esi\nmov %ebx,%edi\nsub %r13d,%r14d\ncallq 1200 \nimul %r14d,%eax\nimul %r15d,%eax\nimul 0xc(%rsp),%r15d\nadd %eax,%ebp\ncmp %r13d,%ebx\njle 126c \ntest %ebx,%ebx\njne 1240 \nadd $0x18,%rsp\nmov %ebp,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl (%rax)\nxor %ebp,%ebp\njmp 126c \nnopl 0x0(%rax)\nmov $0x1,%ebp\njmp 126c \n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\ncmp edi, esi\njle short loc_1280\nmov ebx, edi\ntest edi, edi\njz short loc_1280\nmov r14d, esi\ntest esi, esi\njz short loc_1288\nlea eax, [rsi-1]\nlea r12d, [rsi+1]\nmov r15d, 1\nxor r13d, r13d\nmov [rsp+48h+var_3C], eax\nnop word ptr [rax+rax+00000000h]\nloc_1240:\nmov ebp, ebx\nmov esi, [rsp+48h+var_3C]\nsub ebx, 1\nmov edi, ebx\nsub ebp, r14d\ncall func0\nimul ebp, eax\nimul ebp, r15d\nimul r15d, r12d\nadd r13d, ebp\ncmp ebx, r14d\njle short loc_126A\ntest ebx, ebx\njnz short loc_1240\nloc_126A:\nadd rsp, 18h\nmov eax, r13d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1280:\nxor r13d, r13d\njmp short loc_126A\nloc_1288:\nmov r13d, 1\njmp short loc_126A", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n unsigned int v2; // ebx\n int v3; // r15d\n unsigned int v4; // r13d\n int v5; // ebp\n int v6; // ebp\n\n if ( a1 > a2 && (v2 = a1) != 0 )\n {\n if ( a2 )\n {\n v3 = 1;\n v4 = 0;\n do\n {\n v5 = v2--;\n v6 = v3 * func0(v2, (unsigned int)(a2 - 1)) * (v5 - a2);\n v3 *= a2 + 1;\n v4 += v6;\n }\n while ( (int)v2 > a2 && v2 );\n }\n else\n {\n return 1;\n }\n }\n else\n {\n return 0;\n }\n return v4;\n}", + "ida_strip_asm": "sub_1200:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\ncmp edi, esi\njle short loc_1280\nmov ebx, edi\ntest edi, edi\njz short loc_1280\nmov r14d, esi\ntest esi, esi\njz short loc_1288\nlea eax, [rsi-1]\nlea r12d, [rsi+1]\nmov r15d, 1\nxor r13d, r13d\nmov [rsp+48h+var_3C], eax\nnop word ptr [rax+rax+00000000h]\nloc_1240:\nmov ebp, ebx\nmov esi, [rsp+48h+var_3C]\nsub ebx, 1\nmov edi, ebx\nsub ebp, r14d\ncall sub_1200\nimul ebp, eax\nimul ebp, r15d\nimul r15d, r12d\nadd r13d, ebp\ncmp ebx, r14d\njle short loc_126A\ntest ebx, ebx\njnz short loc_1240\nloc_126A:\nadd rsp, 18h\nmov eax, r13d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1280:\nxor r13d, r13d\njmp short loc_126A\nloc_1288:\nmov r13d, 1\njmp short loc_126A", + "ida_strip_pseudo": "__int64 __fastcall sub_1200(int a1, int a2)\n{\n unsigned int v2; // ebx\n int v3; // r15d\n unsigned int v4; // r13d\n int v5; // ebp\n int v6; // ebp\n\n if ( a1 > a2 && (v2 = a1) != 0 )\n {\n if ( a2 )\n {\n v3 = 1;\n v4 = 0;\n do\n {\n v5 = v2--;\n v6 = v3 * sub_1200(v2, (unsigned int)(a2 - 1)) * (v5 - a2);\n v3 *= a2 + 1;\n v4 += v6;\n }\n while ( (int)v2 > a2 && v2 );\n }\n else\n {\n return 1;\n }\n }\n else\n {\n return 0;\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1200(int a1, int a2) {\n unsigned int v2;\n int v3;\n unsigned int v4;\n int v5;\n int v6;\n if (a1 > a2 && (v2 = a1) != 0) {\n if (a2) {\n v3 = 1;\n v4 = 0;\n do {\n v5 = v2--;\n v6 = v3 * sub_1200(v2, (unsigned int)(a2 - 1)) * (v5 - a2);\n v3 *= a2 + 1;\n v4 += v6;\n } while ((int)v2 > a2 && v2);\n } else {\n return 1;\n }\n } else {\n return 0;\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n unsigned int v2;\n int v3;\n unsigned int v4;\n int v5;\n int v6;\n if (a1 > a2 && (v2 = a1) != 0) {\n if (a2) {\n v3 = 1;\n v4 = 0;\n do {\n v5 = v2--;\n v6 = v3 * func0(v2, (unsigned int)(a2 - 1)) * (v5 - a2);\n v3 *= a2 + 1;\n v4 += v6;\n } while ((int)v2 > a2 && v2);\n } else {\n return 1;\n }\n } else {\n return 0;\n }\n return v4;\n}" + }, + { + "index": 103, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n, int m) {\n if (m >= n || n == 0) {\n return 0;\n }\n if (m == 0) {\n return 1;\n }\n return ((n - m) * func0(n - 1, m - 1) + (m + 1) * func0(n - 1, m));\n}", + "test": "int main() {\n\n assert(func0(3, 1) == 4);\n\n assert(func0(4, 1) == 11);\n\n assert(func0(5, 3) == 26);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\ntest %edi,%edi\nje 1280 \nmov %edi,%ebx\nmov %esi,%r13d\ncmp %esi,%edi\njle 1280 \ntest %esi,%esi\nje 1288 \nlea 0x1(%rsi),%eax\nlea -0x1(%rsi),%r12d\nmov $0x1,%r15d\nxor %ebp,%ebp\nmov %eax,0xc(%rsp)\nnopw %cs:0x0(%rax,%rax,1)\nmov %ebx,%r14d\nsub $0x1,%ebx\nmov %r12d,%esi\nmov %ebx,%edi\nsub %r13d,%r14d\ncallq 1200 \nimul %r14d,%eax\nimul %r15d,%eax\nimul 0xc(%rsp),%r15d\nadd %eax,%ebp\ncmp %r13d,%ebx\njle 126c \ntest %ebx,%ebx\njne 1240 \nadd $0x18,%rsp\nmov %ebp,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl (%rax)\nxor %ebp,%ebp\njmp 126c \nnopl 0x0(%rax)\nmov $0x1,%ebp\njmp 126c \n", + "ida_asm": "func0_constprop_1:\nxor edx, edx\ncmp edi, 1\njle short loc_1221\nmov eax, 1\nnop dword ptr [rax+00h]\nloc_1210:\nsub edi, 1\nmov ecx, edi\nimul ecx, eax\nadd eax, eax\nadd edx, ecx\ncmp edi, 1\njnz short loc_1210\nloc_1221:\nmov eax, edx\nretn", + "ida_pseudo": "__int64 __fastcall func0_constprop_1(int a1)\n{\n unsigned int v1; // edx\n int v2; // eax\n int v3; // ecx\n\n v1 = 0;\n if ( a1 > 1 )\n {\n v2 = 1;\n do\n {\n --a1;\n v3 = v2 * a1;\n v2 *= 2;\n v1 += v3;\n }\n while ( a1 != 1 );\n }\n return v1;\n}", + "ida_strip_asm": "sub_1200:\nxor edx, edx\ncmp edi, 1\njle short loc_1221\nmov eax, 1\nnop dword ptr [rax+00h]\nloc_1210:\nsub edi, 1\nmov ecx, edi\nimul ecx, eax\nadd eax, eax\nadd edx, ecx\ncmp edi, 1\njnz short loc_1210\nloc_1221:\nmov eax, edx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1200(int a1)\n{\n unsigned int v1; // edx\n int v2; // eax\n int v3; // ecx\n\n v1 = 0;\n if ( a1 > 1 )\n {\n v2 = 1;\n do\n {\n --a1;\n v3 = v2 * a1;\n v2 *= 2;\n v1 += v3;\n }\n while ( a1 != 1 );\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1200(int a1) {\n unsigned int v1;\n int v2;\n int v3;\n v1 = 0;\n if (a1 > 1) {\n v2 = 1;\n do {\n --a1;\n v3 = v2 * a1;\n v2 *= 2;\n v1 += v3;\n } while (a1 != 1);\n }\n return v1;\n}", + "ida_pseudo_norm": "long long func0_constprop_1(int a1) {\n unsigned int v1;\n int v2;\n int v3;\n v1 = 0;\n if (a1 > 1) {\n v2 = 1;\n do {\n --a1;\n v3 = v2 * a1;\n v2 *= 2;\n v1 += v3;\n } while (a1 != 1);\n }\n return v1;\n}" + }, + { + "index": 104, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\nint compare(const void* a, const void* b) {\n\n const char* str1 = *(const char**)a;\n\n const char* str2 = *(const char**)b;\n\n return strcmp(str1, str2);\n\n}\n\n\n\n", + "func": "void func0(char*** input_list, int* lengths, int list_size, char**** result) {\n *result = malloc(list_size * sizeof(char**));\n for (int i = 0; i < list_size; i++) {\n (*result)[i] = malloc(lengths[i] * sizeof(char*));\n for (int j = 0; j < lengths[i]; j++) (*result)[i][j] = input_list[i][j];\n qsort((*result)[i], lengths[i], sizeof(char*), compare);\n }\n}", + "test": "int main() {\n\n char* set1[] = {\"green\", \"orange\"};\n\n char* set2[] = {\"black\", \"white\"};\n\n char* set3[] = {\"white\", \"black\", \"orange\"};\n\n char** input1[] = {set1, set2, set3};\n\n int lengths1[] = {2, 2, 3};\n\n\n\n char* expected1_1[] = {\"green\", \"orange\"};\n\n char* expected1_2[] = {\"black\", \"white\"};\n\n char* expected1_3[] = {\"black\", \"orange\", \"white\"};\n\n char** expected1[] = {expected1_1, expected1_2, expected1_3};\n\n\n\n char*** result1;\n\n func0(input1, lengths1, 3, &result1);\n\n\n\n for (int i = 0; i < 3; i++)\n\n for (int j = 0; j < lengths1[i]; j++)\n\n assert(strcmp(expected1[i][j], result1[i][j]) == 0);\n\n\n\n // Free memory\n\n for (int i = 0; i < 3; i++) free(result1[i]);\n\n free(result1);\n\n\n\n // Note: Additional tests analogous to the other assertions in the Python code have been skipped for brevity.\n\n // They would be written and checked in a similar manner.\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x38,%rsp\nmov %rdi,-0x28(%rbp)\nmov %rsi,-0x30(%rbp)\nmov %edx,-0x34(%rbp)\nmov %rcx,-0x40(%rbp)\nmov -0x34(%rbp),%eax\ncltq\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 10f0 \nmov %rax,%rdx\nmov -0x40(%rbp),%rax\nmov %rdx,(%rax)\nmovl $0x0,-0x18(%rbp)\njmpq 1366 \nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x30(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncltq\nshl $0x3,%rax\nmov -0x40(%rbp),%rdx\nmov (%rdx),%rdx\nmov -0x18(%rbp),%ecx\nmovslq %ecx,%rcx\nshl $0x3,%rcx\nlea (%rdx,%rcx,1),%rbx\nmov %rax,%rdi\ncallq 10f0 \nmov %rax,(%rbx)\nmovl $0x0,-0x14(%rbp)\njmp 1303 \nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0x14(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x3,%rdx\nlea (%rax,%rdx,1),%rcx\nmov -0x40(%rbp),%rax\nmov (%rax),%rax\nmov -0x18(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x3,%rdx\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0x14(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x3,%rdx\nadd %rax,%rdx\nmov (%rcx),%rax\nmov %rax,(%rdx)\naddl $0x1,-0x14(%rbp)\nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x30(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x14(%rbp)\njl 12b0 \nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x30(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmovslq %eax,%rsi\nmov -0x40(%rbp),%rax\nmov (%rax),%rax\nmov -0x18(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x3,%rdx\nadd %rdx,%rax\nmov (%rax),%rax\nlea -0x16c(%rip),%rcx\nmov $0x8,%edx\nmov %rax,%rdi\ncallq 10b0 \naddl $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%eax\ncmp -0x34(%rbp),%eax\njl 126b \nadd $0x38,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+var_28], rdi\nmov [rbp+var_30], rsi\nmov [rbp+var_34], edx\nmov [rbp+var_40], rcx\nmov eax, [rbp+var_34]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov rdx, rax\nmov rax, [rbp+var_40]\nmov [rax], rdx\nmov [rbp+var_18], 0\njmp loc_1369\nloc_126B:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nshl rax, 3\nmov rdx, [rbp+var_40]\nmov rdx, [rdx]\nmov ecx, [rbp+var_18]\nmovsxd rcx, ecx\nshl rcx, 3\nlea rbx, [rdx+rcx]\nmov rdi, rax; size\ncall _malloc\nmov [rbx], rax\nmov [rbp+var_14], 0\njmp short loc_1303\nloc_12B0:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nshl rdx, 3\nlea rcx, [rax+rdx]\nmov rax, [rbp+var_40]\nmov rax, [rax]\nmov edx, [rbp+var_18]\nmovsxd rdx, edx\nshl rdx, 3\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nshl rdx, 3\nadd rdx, rax\nmov rax, [rcx]\nmov [rdx], rax\nadd [rbp+var_14], 1\nloc_1303:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_14], eax\njl short loc_12B0\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov eax, [rax]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+var_40]\nmov rax, [rax]\nmov edx, [rbp+var_18]\nmovsxd rdx, edx\nshl rdx, 3\nadd rax, rdx\nmov rax, [rax]\nlea rdx, compare\nmov rcx, rdx; compar\nmov edx, 8; size\nmov rdi, rax; base\ncall _qsort\nadd [rbp+var_18], 1\nloc_1369:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_34]\njl loc_126B\nnop\nnop\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3, void **a4)\n{\n void **v4; // rbx\n __int64 result; // rax\n unsigned int i; // [rsp+28h] [rbp-18h]\n int j; // [rsp+2Ch] [rbp-14h]\n\n *a4 = malloc(8LL * a3);\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a3 )\n break;\n v4 = (void **)((char *)*a4 + 8 * (int)i);\n *v4 = malloc(8LL * *(int *)(4LL * (int)i + a2));\n for ( j = 0; j < *(_DWORD *)(4LL * (int)i + a2); ++j )\n *(_QWORD *)(*((_QWORD *)*a4 + (int)i) + 8LL * j) = *(_QWORD *)(*(_QWORD *)(8LL * (int)i + a1) + 8LL * j);\n qsort(*((void **)*a4 + (int)i), *(int *)(4LL * (int)i + a2), 8uLL, compare);\n }\n return result;\n}", + "ida_strip_asm": "sub_1228:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+var_28], rdi\nmov [rbp+var_30], rsi\nmov [rbp+var_34], edx\nmov [rbp+var_40], rcx\nmov eax, [rbp+var_34]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov rdx, rax\nmov rax, [rbp+var_40]\nmov [rax], rdx\nmov [rbp+var_18], 0\njmp loc_1369\nloc_126B:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nshl rax, 3\nmov rdx, [rbp+var_40]\nmov rdx, [rdx]\nmov ecx, [rbp+var_18]\nmovsxd rcx, ecx\nshl rcx, 3\nlea rbx, [rdx+rcx]\nmov rdi, rax; size\ncall _malloc\nmov [rbx], rax\nmov [rbp+var_14], 0\njmp short loc_1303\nloc_12B0:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nshl rdx, 3\nlea rcx, [rax+rdx]\nmov rax, [rbp+var_40]\nmov rax, [rax]\nmov edx, [rbp+var_18]\nmovsxd rdx, edx\nshl rdx, 3\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nshl rdx, 3\nadd rdx, rax\nmov rax, [rcx]\nmov [rdx], rax\nadd [rbp+var_14], 1\nloc_1303:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_14], eax\njl short loc_12B0\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov eax, [rax]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+var_40]\nmov rax, [rax]\nmov edx, [rbp+var_18]\nmovsxd rdx, edx\nshl rdx, 3\nadd rax, rdx\nmov rax, [rax]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 8; size\nmov rdi, rax; base\ncall _qsort\nadd [rbp+var_18], 1\nloc_1369:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_34]\njl loc_126B\nnop\nnop\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1228(__int64 a1, __int64 a2, int a3, void **a4)\n{\n void **v4; // rbx\n __int64 result; // rax\n unsigned int i; // [rsp+28h] [rbp-18h]\n int j; // [rsp+2Ch] [rbp-14h]\n\n *a4 = malloc(8LL * a3);\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a3 )\n break;\n v4 = (void **)((char *)*a4 + 8 * (int)i);\n *v4 = malloc(8LL * *(int *)(4LL * (int)i + a2));\n for ( j = 0; j < *(_DWORD *)(4LL * (int)i + a2); ++j )\n *(_QWORD *)(*((_QWORD *)*a4 + (int)i) + 8LL * j) = *(_QWORD *)(*(_QWORD *)(8LL * (int)i + a1) + 8LL * j);\n qsort(*((void **)*a4 + (int)i), *(int *)(4LL * (int)i + a2), 8uLL, compar);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1228(long long a1, long long a2, int a3, void **a4) {\n void **v4;\n long long result;\n unsigned int i;\n int j;\n *a4 = malloc(8LL * a3);\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a3) break;\n v4 = (void **)((char *)*a4 + 8 * (int)i);\n *v4 = malloc(8LL * *(int *)(4LL * (int)i + a2));\n for (j = 0; j < *(uint32_t *)(4LL * (int)i + a2); ++j)\n *(uint64_t *)(*((uint64_t *)*a4 + (int)i) + 8LL * j) =\n *(uint64_t *)(*(uint64_t *)(8LL * (int)i + a1) + 8LL * j);\n qsort(*((void **)*a4 + (int)i), *(int *)(4LL * (int)i + a2), 8uLL, compar);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3, void **a4) {\n void **v4;\n long long result;\n unsigned int i;\n int j;\n *a4 = malloc(8LL * a3);\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a3) break;\n v4 = (void **)((char *)*a4 + 8 * (int)i);\n *v4 = malloc(8LL * *(int *)(4LL * (int)i + a2));\n for (j = 0; j < *(uint32_t *)(4LL * (int)i + a2); ++j)\n *(uint64_t *)(*((uint64_t *)*a4 + (int)i) + 8LL * j) =\n *(uint64_t *)(*(uint64_t *)(8LL * (int)i + a1) + 8LL * j);\n qsort(*((void **)*a4 + (int)i), *(int *)(4LL * (int)i + a2), 8uLL, compare);\n }\n return result;\n}" + }, + { + "index": 104, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\nint compare(const void* a, const void* b) {\n\n const char* str1 = *(const char**)a;\n\n const char* str2 = *(const char**)b;\n\n return strcmp(str1, str2);\n\n}\n\n\n\n", + "func": "void func0(char*** input_list, int* lengths, int list_size, char**** result) {\n *result = malloc(list_size * sizeof(char**));\n for (int i = 0; i < list_size; i++) {\n (*result)[i] = malloc(lengths[i] * sizeof(char*));\n for (int j = 0; j < lengths[i]; j++) (*result)[i][j] = input_list[i][j];\n qsort((*result)[i], lengths[i], sizeof(char*), compare);\n }\n}", + "test": "int main() {\n\n char* set1[] = {\"green\", \"orange\"};\n\n char* set2[] = {\"black\", \"white\"};\n\n char* set3[] = {\"white\", \"black\", \"orange\"};\n\n char** input1[] = {set1, set2, set3};\n\n int lengths1[] = {2, 2, 3};\n\n\n\n char* expected1_1[] = {\"green\", \"orange\"};\n\n char* expected1_2[] = {\"black\", \"white\"};\n\n char* expected1_3[] = {\"black\", \"orange\", \"white\"};\n\n char** expected1[] = {expected1_1, expected1_2, expected1_3};\n\n\n\n char*** result1;\n\n func0(input1, lengths1, 3, &result1);\n\n\n\n for (int i = 0; i < 3; i++)\n\n for (int j = 0; j < lengths1[i]; j++)\n\n assert(strcmp(expected1[i][j], result1[i][j]) == 0);\n\n\n\n // Free memory\n\n for (int i = 0; i < 3; i++) free(result1[i]);\n\n free(result1);\n\n\n\n // Note: Additional tests analogous to the other assertions in the Python code have been skipped for brevity.\n\n // They would be written and checked in a similar manner.\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov %rdi,%r13\nmov %rsi,%r14\nmov %edx,%ebx\nmov %rcx,%r12\nmovslq %edx,%rdi\nshl $0x3,%rdi\ncallq 10f0 \nmov %rax,(%r12)\ntest %ebx,%ebx\njle 12c3 \nmov %r13,%rbp\nlea -0x1(%rbx),%eax\nlea 0x8(%r13,%rax,8),%rax\nmov %rax,0x8(%rsp)\nmov $0x0,%ebx\njmp 127c \nmovslq %esi,%rsi\nmov (%r12),%rax\nmov (%rax,%rbx,1),%rdi\nlea -0x76(%rip),%rcx\nmov $0x8,%edx\ncallq 10b0 \nadd $0x4,%r14\nadd $0x8,%rbx\nadd $0x8,%rbp\ncmp 0x8(%rsp),%rbp\nje 12c3 \nmov %r14,%r13\nmov %rbx,%r15\nadd (%r12),%r15\nmovslq (%r14),%rdi\nshl $0x3,%rdi\ncallq 10f0 \nmov %rax,(%r15)\nmov (%r14),%esi\ntest %esi,%esi\njle 124d \nmov $0x0,%eax\nmov 0x0(%rbp),%rdx\nmov (%rdx,%rax,8),%rcx\nmov (%r12),%rdx\nmov (%rdx,%rbx,1),%rdx\nmov %rcx,(%rdx,%rax,8)\nmov 0x0(%r13),%esi\nadd $0x1,%rax\ncmp %eax,%esi\njg 12a1 \njmp 124d \nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov r15, rdi\nmov r14, rsi\nmov ebx, edx\nmov r12, rcx\nmovsxd r13, edx\nshl r13, 3\nmov rdi, r13; size\ncall _malloc\nmov [r12], rax\ntest ebx, ebx\njle loc_12C1\nmov rbp, r15\nlea rax, [r15+r13]\nmov [rsp+48h+var_40], rax\nmov ebx, 0\nloc_124A:\nmov r13, r14\nmov r15, rbx\nadd r15, [r12]\nmovsxd rdi, dword ptr [r14]\nshl rdi, 3; size\ncall _malloc\nmov [r15], rax\nmov esi, [r14]\ntest esi, esi\njle short loc_128F\nmov eax, 0\nloc_126F:\nmov rdx, [rbp+0]\nmov rcx, [rdx+rax*8]\nmov rdx, [r12]\nmov rdx, [rdx+rbx]\nmov [rdx+rax*8], rcx\nmov esi, [r13+0]\nadd rax, 1\ncmp esi, eax\njg short loc_126F\nloc_128F:\nmovsxd rsi, esi; nmemb\nmov rax, [r12]\nmov rdi, [rax+rbx]; base\nlea rcx, compare; compar\nmov edx, 8; size\ncall _qsort\nadd r14, 4\nadd rbx, 8\nadd rbp, 8\nmov rax, [rsp+48h+var_40]\ncmp rbp, rax\njnz short loc_124A\nloc_12C1:\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(_QWORD *a1, int *a2, int a3, _QWORD *a4)\n{\n size_t v7; // r13\n _QWORD *result; // rax\n _QWORD *v9; // rbp\n __int64 v10; // rbx\n void **v11; // r15\n int v12; // esi\n __int64 v13; // rax\n\n v7 = a3;\n result = malloc(v7 * 8);\n *a4 = result;\n if ( a3 > 0 )\n {\n v9 = a1;\n v10 = 0LL;\n do\n {\n v11 = (void **)(*a4 + v10);\n *v11 = malloc(8LL * *a2);\n v12 = *a2;\n if ( *a2 > 0 )\n {\n v13 = 0LL;\n do\n {\n *(_QWORD *)(*(_QWORD *)(*a4 + v10) + 8 * v13) = *(_QWORD *)(*v9 + 8 * v13);\n v12 = *a2;\n ++v13;\n }\n while ( *a2 > (int)v13 );\n }\n qsort(*(void **)(*a4 + v10), v12, 8uLL, compare);\n ++a2;\n v10 += 8LL;\n ++v9;\n result = &a1[v7];\n }\n while ( v9 != &a1[v7] );\n }\n return result;\n}", + "ida_strip_asm": "sub_1201:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov r15, rdi\nmov r14, rsi\nmov ebx, edx\nmov r12, rcx\nmovsxd r13, edx\nshl r13, 3\nmov rdi, r13; size\ncall _malloc\nmov [r12], rax\ntest ebx, ebx\njle loc_12C1\nmov rbp, r15\nlea rax, [r15+r13]\nmov [rsp+48h+var_40], rax\nmov ebx, 0\nloc_124A:\nmov r13, r14\nmov r15, rbx\nadd r15, [r12]\nmovsxd rdi, dword ptr [r14]\nshl rdi, 3; size\ncall _malloc\nmov [r15], rax\nmov esi, [r14]\ntest esi, esi\njle short loc_128F\nmov eax, 0\nloc_126F:\nmov rdx, [rbp+0]\nmov rcx, [rdx+rax*8]\nmov rdx, [r12]\nmov rdx, [rdx+rbx]\nmov [rdx+rax*8], rcx\nmov esi, [r13+0]\nadd rax, 1\ncmp esi, eax\njg short loc_126F\nloc_128F:\nmovsxd rsi, esi; nmemb\nmov rax, [r12]\nmov rdi, [rax+rbx]; base\nlea rcx, compar; compar\nmov edx, 8; size\ncall _qsort\nadd r14, 4\nadd rbx, 8\nadd rbp, 8\nmov rax, [rsp+48h+var_40]\ncmp rbp, rax\njnz short loc_124A\nloc_12C1:\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1201(_QWORD *a1, int *a2, int a3, _QWORD *a4)\n{\n size_t v7; // r13\n _QWORD *result; // rax\n _QWORD *v9; // rbp\n __int64 v10; // rbx\n void **v11; // r15\n int v12; // esi\n __int64 v13; // rax\n\n v7 = a3;\n result = malloc(v7 * 8);\n *a4 = result;\n if ( a3 > 0 )\n {\n v9 = a1;\n v10 = 0LL;\n do\n {\n v11 = (void **)(*a4 + v10);\n *v11 = malloc(8LL * *a2);\n v12 = *a2;\n if ( *a2 > 0 )\n {\n v13 = 0LL;\n do\n {\n *(_QWORD *)(*(_QWORD *)(*a4 + v10) + 8 * v13) = *(_QWORD *)(*v9 + 8 * v13);\n v12 = *a2;\n ++v13;\n }\n while ( *a2 > (int)v13 );\n }\n qsort(*(void **)(*a4 + v10), v12, 8uLL, compar);\n ++a2;\n v10 += 8LL;\n ++v9;\n result = &a1[v7];\n }\n while ( v9 != &a1[v7] );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1201(uint64_t *a1, int *a2, int a3, uint64_t *a4) {\n unsigned int v7;\n uint64_t *result;\n uint64_t *v9;\n long long v10;\n void **v11;\n int v12;\n long long v13;\n v7 = a3;\n result = malloc(v7 * 8);\n *a4 = result;\n if (a3 > 0) {\n v9 = a1;\n v10 = 0LL;\n do {\n v11 = (void **)(*a4 + v10);\n *v11 = malloc(8LL * *a2);\n v12 = *a2;\n if (*a2 > 0) {\n v13 = 0LL;\n do {\n *(uint64_t *)(*(uint64_t *)(*a4 + v10) + 8 * v13) =\n *(uint64_t *)(*v9 + 8 * v13);\n v12 = *a2;\n ++v13;\n } while (*a2 > (int)v13);\n }\n qsort(*(void **)(*a4 + v10), v12, 8uLL, compar);\n ++a2;\n v10 += 8LL;\n ++v9;\n result = &a1[v7];\n } while (v9 != &a1[v7]);\n }\n return result;\n}", + "ida_pseudo_norm": "uint64_t *func0(uint64_t *a1, int *a2, int a3, uint64_t *a4) {\n unsigned int v7;\n uint64_t *result;\n uint64_t *v9;\n long long v10;\n void **v11;\n int v12;\n long long v13;\n v7 = a3;\n result = malloc(v7 * 8);\n *a4 = result;\n if (a3 > 0) {\n v9 = a1;\n v10 = 0LL;\n do {\n v11 = (void **)(*a4 + v10);\n *v11 = malloc(8LL * *a2);\n v12 = *a2;\n if (*a2 > 0) {\n v13 = 0LL;\n do {\n *(uint64_t *)(*(uint64_t *)(*a4 + v10) + 8 * v13) =\n *(uint64_t *)(*v9 + 8 * v13);\n v12 = *a2;\n ++v13;\n } while (*a2 > (int)v13);\n }\n qsort(*(void **)(*a4 + v10), v12, 8uLL, compare);\n ++a2;\n v10 += 8LL;\n ++v9;\n result = &a1[v7];\n } while (v9 != &a1[v7]);\n }\n return result;\n}" + }, + { + "index": 104, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\nint compare(const void* a, const void* b) {\n\n const char* str1 = *(const char**)a;\n\n const char* str2 = *(const char**)b;\n\n return strcmp(str1, str2);\n\n}\n\n\n\n", + "func": "void func0(char*** input_list, int* lengths, int list_size, char**** result) {\n *result = malloc(list_size * sizeof(char**));\n for (int i = 0; i < list_size; i++) {\n (*result)[i] = malloc(lengths[i] * sizeof(char*));\n for (int j = 0; j < lengths[i]; j++) (*result)[i][j] = input_list[i][j];\n qsort((*result)[i], lengths[i], sizeof(char*), compare);\n }\n}", + "test": "int main() {\n\n char* set1[] = {\"green\", \"orange\"};\n\n char* set2[] = {\"black\", \"white\"};\n\n char* set3[] = {\"white\", \"black\", \"orange\"};\n\n char** input1[] = {set1, set2, set3};\n\n int lengths1[] = {2, 2, 3};\n\n\n\n char* expected1_1[] = {\"green\", \"orange\"};\n\n char* expected1_2[] = {\"black\", \"white\"};\n\n char* expected1_3[] = {\"black\", \"orange\", \"white\"};\n\n char** expected1[] = {expected1_1, expected1_2, expected1_3};\n\n\n\n char*** result1;\n\n func0(input1, lengths1, 3, &result1);\n\n\n\n for (int i = 0; i < 3; i++)\n\n for (int j = 0; j < lengths1[i]; j++)\n\n assert(strcmp(expected1[i][j], result1[i][j]) == 0);\n\n\n\n // Free memory\n\n for (int i = 0; i < 3; i++) free(result1[i]);\n\n free(result1);\n\n\n\n // Note: Additional tests analogous to the other assertions in the Python code have been skipped for brevity.\n\n // They would be written and checked in a similar manner.\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\nmov %rcx,%rbp\npush %rbx\nsub $0x28,%rsp\nmov %rdi,0x18(%rsp)\nmovslq %edx,%rdi\nmov %rdi,%r13\nshl $0x3,%rdi\nmov %rsi,0x8(%rsp)\ncallq 10f0 \nmov %rax,0x0(%rbp)\ntest %r13d,%r13d\njle 14d0 \nmov %rax,%r14\nlea -0x1(%r13),%eax\nxor %r15d,%r15d\nmov %rax,0x10(%rsp)\nlea -0x61(%rip),%r13\nnopl 0x0(%rax)\nmov 0x8(%rsp),%rax\nmovslq (%rax,%r15,4),%r12\nlea 0x0(,%r12,8),%rdi\ncallq 10f0 \nmov %rax,(%r14,%r15,8)\nmov %rax,%rdi\ntest %r12d,%r12d\njle 14a4 \nmov 0x18(%rsp),%rax\nxor %edx,%edx\nmov (%rax,%r15,8),%r8\nlea -0x1(%r12),%eax\nnopw 0x0(%rax,%rax,1)\nmov (%r8,%rdx,8),%rcx\nmov %rcx,(%rdi,%rdx,8)\nmov %rdx,%rcx\nadd $0x1,%rdx\ncmp %rcx,%rax\njne 1490 \nmov %r13,%rcx\nmov $0x8,%edx\nmov %r12,%rsi\ncallq 10b0 \nlea 0x1(%r15),%rax\ncmp %r15,0x10(%rsp)\nje 14d0 \nmov 0x0(%rbp),%r14\nmov %rax,%r15\njmp 1458 \nnopl 0x0(%rax,%rax,1)\nadd $0x28,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov r15, rcx\npush r14\nmovsxd r14, edx\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rsi\nsub rsp, 28h\nmov [rsp+58h+var_48], rdi\nlea rdi, ds:0[r14*8]; size\nmov [rsp+58h+var_40], rcx\ncall _malloc\nmov [r15], rax\ntest r14d, r14d\njle loc_14B8\nmov r13, rax\nlea rax, [rbx+r14*4]\nxor ebp, ebp\nmov [rsp+58h+var_50], rax\nnop dword ptr [rax+00h]\nloc_1440:\nmovsxd r14, dword ptr [rbx]\nlea r15, ds:0[r14*8]\nmov rdi, r15; size\ncall _malloc\nmov [r13+rbp+0], rax\nmov rdi, rax; base\ntest r14d, r14d\njle short loc_1481\nmov rax, [rsp+58h+var_48]\nmov r8, [rax+rbp]\nxor eax, eax\nnop dword ptr [rax+rax+00h]\nloc_1470:\nmov rdx, [r8+rax]\nmov [rdi+rax], rdx\nadd rax, 8\ncmp r15, rax\njnz short loc_1470\nloc_1481:\nmov edx, 8; size\nmov rsi, r14; nmemb\nadd rbx, 4\nadd rbp, 8\nlea rcx, compare; compar\ncall _qsort\nmov rax, [rsp+58h+var_50]\ncmp rbx, rax\njz short loc_14B8\nmov rax, [rsp+58h+var_40]\nmov r13, [rax]\njmp short loc_1440\nloc_14B8:\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int *a2, int a3, char **a4)\n{\n __int64 v5; // r14\n int *v6; // rbx\n char *result; // rax\n char *v8; // r13\n __int64 v9; // rbp\n size_t v10; // r14\n char *v11; // rax\n char *v12; // rdi\n __int64 v13; // r8\n __int64 v14; // rax\n int *v15; // [rsp+8h] [rbp-50h]\n\n v5 = a3;\n v6 = a2;\n result = (char *)malloc(8LL * a3);\n *a4 = result;\n if ( (int)v5 > 0 )\n {\n v8 = result;\n v9 = 0LL;\n v15 = &a2[v5];\n while ( 1 )\n {\n v10 = *v6;\n v11 = (char *)malloc(8 * v10);\n *(_QWORD *)&v8[v9] = v11;\n v12 = v11;\n if ( (int)v10 > 0 )\n {\n v13 = *(_QWORD *)(a1 + v9);\n v14 = 0LL;\n do\n {\n *(_QWORD *)&v12[v14] = *(_QWORD *)(v13 + v14);\n v14 += 8LL;\n }\n while ( 8 * v10 != v14 );\n }\n ++v6;\n v9 += 8LL;\n qsort(v12, v10, 8uLL, compare);\n result = (char *)v15;\n if ( v6 == v15 )\n break;\n v8 = *a4;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_13F0:\nendbr64\npush r15\nmov r15, rcx\npush r14\nmovsxd r14, edx\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rsi\nsub rsp, 28h\nmov [rsp+58h+var_48], rdi\nlea rdi, ds:0[r14*8]; size\nmov [rsp+58h+var_40], rcx\ncall _malloc\nmov [r15], rax\ntest r14d, r14d\njle loc_14B8\nmov r13, rax\nlea rax, [rbx+r14*4]\nxor ebp, ebp\nmov [rsp+58h+var_50], rax\nnop dword ptr [rax+00h]\nloc_1440:\nmovsxd r14, dword ptr [rbx]\nlea r15, ds:0[r14*8]\nmov rdi, r15; size\ncall _malloc\nmov [r13+rbp+0], rax\nmov rdi, rax; base\ntest r14d, r14d\njle short loc_1481\nmov rax, [rsp+58h+var_48]\nmov r8, [rax+rbp]\nxor eax, eax\nnop dword ptr [rax+rax+00h]\nloc_1470:\nmov rdx, [r8+rax]\nmov [rdi+rax], rdx\nadd rax, 8\ncmp r15, rax\njnz short loc_1470\nloc_1481:\nmov edx, 8; size\nmov rsi, r14; nmemb\nadd rbx, 4\nadd rbp, 8\nlea rcx, compar; compar\ncall _qsort\nmov rax, [rsp+58h+var_50]\ncmp rbx, rax\njz short loc_14B8\nmov rax, [rsp+58h+var_40]\nmov r13, [rax]\njmp short loc_1440\nloc_14B8:\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "char *__fastcall sub_13F0(__int64 a1, int *a2, int a3, char **a4)\n{\n __int64 v5; // r14\n int *v6; // rbx\n char *result; // rax\n char *v8; // r13\n __int64 v9; // rbp\n size_t v10; // r14\n char *v11; // rax\n char *v12; // rdi\n __int64 v13; // r8\n __int64 v14; // rax\n int *v15; // [rsp+8h] [rbp-50h]\n\n v5 = a3;\n v6 = a2;\n result = (char *)malloc(8LL * a3);\n *a4 = result;\n if ( (int)v5 > 0 )\n {\n v8 = result;\n v9 = 0LL;\n v15 = &a2[v5];\n while ( 1 )\n {\n v10 = *v6;\n v11 = (char *)malloc(8 * v10);\n *(_QWORD *)&v8[v9] = v11;\n v12 = v11;\n if ( (int)v10 > 0 )\n {\n v13 = *(_QWORD *)(a1 + v9);\n v14 = 0LL;\n do\n {\n *(_QWORD *)&v12[v14] = *(_QWORD *)(v13 + v14);\n v14 += 8LL;\n }\n while ( 8 * v10 != v14 );\n }\n ++v6;\n v9 += 8LL;\n qsort(v12, v10, 8uLL, compar);\n result = (char *)v15;\n if ( v6 == v15 )\n break;\n v8 = *a4;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_13F0(long long a1, int *a2, int a3, char **a4) {\n long long v5;\n int *v6;\n char *result;\n char *v8;\n long long v9;\n unsigned int v10;\n char *v11;\n char *v12;\n long long v13;\n long long v14;\n int *v15;\n v5 = a3;\n v6 = a2;\n result = (char *)malloc(8LL * a3);\n *a4 = result;\n if ((int)v5 > 0) {\n v8 = result;\n v9 = 0LL;\n v15 = &a2[v5];\n while (1) {\n v10 = *v6;\n v11 = (char *)malloc(8 * v10);\n *(uint64_t *)&v8[v9] = v11;\n v12 = v11;\n if ((int)v10 > 0) {\n v13 = *(uint64_t *)(a1 + v9);\n v14 = 0LL;\n do {\n *(uint64_t *)&v12[v14] = *(uint64_t *)(v13 + v14);\n v14 += 8LL;\n } while (8 * v10 != v14);\n }\n ++v6;\n v9 += 8LL;\n qsort(v12, v10, 8uLL, compar);\n result = (char *)v15;\n if (v6 == v15) break;\n v8 = *a4;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int *a2, int a3, char **a4) {\n long long v5;\n int *v6;\n char *result;\n char *v8;\n long long v9;\n unsigned int v10;\n char *v11;\n char *v12;\n long long v13;\n long long v14;\n int *v15;\n v5 = a3;\n v6 = a2;\n result = (char *)malloc(8LL * a3);\n *a4 = result;\n if ((int)v5 > 0) {\n v8 = result;\n v9 = 0LL;\n v15 = &a2[v5];\n while (1) {\n v10 = *v6;\n v11 = (char *)malloc(8 * v10);\n *(uint64_t *)&v8[v9] = v11;\n v12 = v11;\n if ((int)v10 > 0) {\n v13 = *(uint64_t *)(a1 + v9);\n v14 = 0LL;\n do {\n *(uint64_t *)&v12[v14] = *(uint64_t *)(v13 + v14);\n v14 += 8LL;\n } while (8 * v10 != v14);\n }\n ++v6;\n v9 += 8LL;\n qsort(v12, v10, 8uLL, compare);\n result = (char *)v15;\n if (v6 == v15) break;\n v8 = *a4;\n }\n }\n return result;\n}" + }, + { + "index": 104, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\nint compare(const void* a, const void* b) {\n\n const char* str1 = *(const char**)a;\n\n const char* str2 = *(const char**)b;\n\n return strcmp(str1, str2);\n\n}\n\n\n\n", + "func": "void func0(char*** input_list, int* lengths, int list_size, char**** result) {\n *result = malloc(list_size * sizeof(char**));\n for (int i = 0; i < list_size; i++) {\n (*result)[i] = malloc(lengths[i] * sizeof(char*));\n for (int j = 0; j < lengths[i]; j++) (*result)[i][j] = input_list[i][j];\n qsort((*result)[i], lengths[i], sizeof(char*), compare);\n }\n}", + "test": "int main() {\n\n char* set1[] = {\"green\", \"orange\"};\n\n char* set2[] = {\"black\", \"white\"};\n\n char* set3[] = {\"white\", \"black\", \"orange\"};\n\n char** input1[] = {set1, set2, set3};\n\n int lengths1[] = {2, 2, 3};\n\n\n\n char* expected1_1[] = {\"green\", \"orange\"};\n\n char* expected1_2[] = {\"black\", \"white\"};\n\n char* expected1_3[] = {\"black\", \"orange\", \"white\"};\n\n char** expected1[] = {expected1_1, expected1_2, expected1_3};\n\n\n\n char*** result1;\n\n func0(input1, lengths1, 3, &result1);\n\n\n\n for (int i = 0; i < 3; i++)\n\n for (int j = 0; j < lengths1[i]; j++)\n\n assert(strcmp(expected1[i][j], result1[i][j]) == 0);\n\n\n\n // Free memory\n\n for (int i = 0; i < 3; i++) free(result1[i]);\n\n free(result1);\n\n\n\n // Note: Additional tests analogous to the other assertions in the Python code have been skipped for brevity.\n\n // They would be written and checked in a similar manner.\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\nmov %rcx,%rbp\npush %rbx\nsub $0x28,%rsp\nmov %rdi,0x18(%rsp)\nmovslq %edx,%rdi\nmov %rdi,%r13\nshl $0x3,%rdi\nmov %rsi,0x8(%rsp)\ncallq 10f0 \nmov %rax,0x0(%rbp)\ntest %r13d,%r13d\njle 1530 \nmov %rax,%r14\nlea -0x1(%r13),%eax\nxor %r15d,%r15d\nmov %rax,0x10(%rsp)\nlea -0x61(%rip),%r13\nnopl 0x0(%rax)\nmov 0x8(%rsp),%rax\nmovslq (%rax,%r15,4),%r12\nlea 0x0(,%r12,8),%rdi\nmov %r12,%rbx\ncallq 10f0 \nmov %rax,(%r14,%r15,8)\nmov %rax,%rdi\ntest %r12d,%r12d\njle 14e4 \nmov 0x18(%rsp),%rax\nlea 0xf(%rdi),%rcx\nlea -0x1(%r12),%edx\nmov (%rax,%r15,8),%rax\nsub %rax,%rcx\ncmp $0x1e,%rcx\njbe 1510 \ncmp $0x3,%edx\njbe 1510 \nmov %r12d,%ecx\nxor %edx,%edx\nshr %ecx\nshl $0x4,%rcx\nnopl 0x0(%rax,%rax,1)\nmovdqu (%rax,%rdx,1),%xmm0\nmovups %xmm0,(%rdi,%rdx,1)\nadd $0x10,%rdx\ncmp %rcx,%rdx\njne 14c0 \nmov %ebx,%edx\nand $0xfffffffe,%edx\nand $0x1,%ebx\nje 14e4 \nmov (%rax,%rdx,8),%rax\nmov %rax,(%rdi,%rdx,8)\nmov %r13,%rcx\nmov $0x8,%edx\nmov %r12,%rsi\ncallq 10b0 \nlea 0x1(%r15),%rax\ncmp 0x10(%rsp),%r15\nje 1530 \nmov 0x0(%rbp),%r14\nmov %rax,%r15\njmpq 1468 \nnopl 0x0(%rax,%rax,1)\nmov %edx,%ecx\nxor %edx,%edx\nnopl 0x0(%rax)\nmov (%rax,%rdx,8),%r8\nmov %r8,(%rdi,%rdx,8)\nmov %rdx,%r8\nadd $0x1,%rdx\ncmp %r8,%rcx\njne 1518 \njmp 14e4 \nxchg %ax,%ax\nadd $0x28,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov r15, rcx\npush r14\nmovsxd r14, edx\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rsi\nsub rsp, 28h\nmov [rsp+58h+var_48], rdi\nlea rdi, ds:0[r14*8]; size\nmov [rsp+58h+var_40], rcx\ncall _malloc\nmov [r15], rax\ntest r14d, r14d\njle loc_1520\nmov r13, rax\nlea rax, [rbx+r14*4]\nxor ebp, ebp\nmov [rsp+58h+var_50], rax\nnop dword ptr [rax+00h]\nloc_1440:\nmovsxd r14, dword ptr [rbx]\nlea r15, ds:0[r14*8]\nmov r12, r14\nmov rdi, r15; size\ncall _malloc\nmov [r13+rbp+0], rax\nmov rdi, rax; base\ntest r14d, r14d\njle short loc_14A0\nmov rax, [rsp+58h+var_48]\nmov rdx, [rax+rbp]\nlea eax, [r14-1]\ncmp eax, 2\njbe loc_1510\nlea r9, [rdx+8]\nxor eax, eax\ncmp rdi, r9\njnz short loc_14D8\nnop dword ptr [rax+00h]\nloc_1488:\nmov rcx, [rdx+rax]\nmov [rdi+rax], rcx\nadd rax, 8\ncmp r15, rax\njnz short loc_1488\nnop dword ptr [rax+00000000h]\nloc_14A0:\nmov edx, 8; size\nmov rsi, r14; nmemb\nadd rbx, 4\nadd rbp, 8\nlea rcx, compare; compar\ncall _qsort\nmov rax, [rsp+58h+var_50]\ncmp rbx, rax\njz short loc_1520\nmov rax, [rsp+58h+var_40]\nmov r13, [rax]\njmp loc_1440\nloc_14D8:\nmov r8d, r14d\nshr r8d, 1\nshl r8, 4\nnop word ptr [rax+rax+00h]\nloc_14E8:\nmovdqu xmm0, xmmword ptr [rdx+rax]\nmovups xmmword ptr [rdi+rax], xmm0\nadd rax, 10h\ncmp rax, r8\njnz short loc_14E8\nmov eax, r12d\nand eax, 0FFFFFFFEh\nand r12d, 1\njz short loc_14A0\nmov rdx, [rdx+rax*8]\nmov [rdi+rax*8], rdx\njmp short loc_14A0\nloc_1510:\nxor eax, eax\njmp loc_1488\nloc_1520:\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int *a2, int a3, char **a4)\n{\n __int64 v5; // r14\n int *v6; // rbx\n char *result; // rax\n char *v8; // r13\n __int64 v9; // rbp\n size_t v10; // r14\n int v11; // r12d\n _QWORD *v12; // rax\n _QWORD *v13; // rdi\n __int64 v14; // rdx\n __int64 i; // rax\n int *v16; // [rsp+8h] [rbp-50h]\n\n v5 = a3;\n v6 = a2;\n result = (char *)malloc(8LL * a3);\n *a4 = result;\n if ( (int)v5 > 0 )\n {\n v8 = result;\n v9 = 0LL;\n v16 = &a2[v5];\n while ( 1 )\n {\n v10 = *v6;\n v11 = *v6;\n v12 = malloc(8 * v10);\n *(_QWORD *)&v8[v9] = v12;\n v13 = v12;\n if ( (int)v10 <= 0 )\n goto LABEL_7;\n v14 = *(_QWORD *)(a1 + v9);\n if ( (unsigned int)(v10 - 1) <= 2 )\n break;\n i = 0LL;\n if ( v13 == (_QWORD *)(v14 + 8) )\n goto LABEL_6;\n do\n {\n *(__m128i *)&v13[i] = _mm_loadu_si128((const __m128i *)(v14 + i * 8));\n i += 2LL;\n }\n while ( i != 2LL * ((unsigned int)v10 >> 1) );\n if ( (v11 & 1) != 0 )\n v13[v11 & 0xFFFFFFFE] = *(_QWORD *)(v14 + 8LL * (v11 & 0xFFFFFFFE));\nLABEL_7:\n ++v6;\n v9 += 8LL;\n qsort(v13, v10, 8uLL, compare);\n result = (char *)v16;\n if ( v6 == v16 )\n return result;\n v8 = *a4;\n }\n for ( i = 0LL; i != v10; ++i )\nLABEL_6:\n v13[i] = *(_QWORD *)(v14 + i * 8);\n goto LABEL_7;\n }\n return result;\n}", + "ida_strip_asm": "sub_13F0:\nendbr64\npush r15\nmov r15, rcx\npush r14\nmovsxd r14, edx\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rsi\nsub rsp, 28h\nmov [rsp+58h+var_48], rdi\nlea rdi, ds:0[r14*8]; size\nmov [rsp+58h+var_40], rcx\ncall _malloc\nmov [r15], rax\ntest r14d, r14d\njle loc_1520\nmov r13, rax\nlea rax, [rbx+r14*4]\nxor ebp, ebp\nmov [rsp+58h+var_50], rax\nnop dword ptr [rax+00h]\nloc_1440:\nmovsxd r14, dword ptr [rbx]\nlea r15, ds:0[r14*8]\nmov r12, r14\nmov rdi, r15; size\ncall _malloc\nmov [r13+rbp+0], rax\nmov rdi, rax; base\ntest r14d, r14d\njle short loc_14A0\nmov rax, [rsp+58h+var_48]\nmov rdx, [rax+rbp]\nlea eax, [r14-1]\ncmp eax, 2\njbe loc_1510\nlea r9, [rdx+8]\nxor eax, eax\ncmp rdi, r9\njnz short loc_14D8\nnop dword ptr [rax+00h]\nloc_1488:\nmov rcx, [rdx+rax]\nmov [rdi+rax], rcx\nadd rax, 8\ncmp r15, rax\njnz short loc_1488\nnop dword ptr [rax+00000000h]\nloc_14A0:\nmov edx, 8; size\nmov rsi, r14; nmemb\nadd rbx, 4\nadd rbp, 8\nlea rcx, compar; compar\ncall _qsort\nmov rax, [rsp+58h+var_50]\ncmp rbx, rax\njz short loc_1520\nmov rax, [rsp+58h+var_40]\nmov r13, [rax]\njmp loc_1440\nloc_14D8:\nmov r8d, r14d\nshr r8d, 1\nshl r8, 4\nnop word ptr [rax+rax+00h]\nloc_14E8:\nmovdqu xmm0, xmmword ptr [rdx+rax]\nmovups xmmword ptr [rdi+rax], xmm0\nadd rax, 10h\ncmp rax, r8\njnz short loc_14E8\nmov eax, r12d\nand eax, 0FFFFFFFEh\nand r12d, 1\njz short loc_14A0\nmov rdx, [rdx+rax*8]\nmov [rdi+rax*8], rdx\njmp short loc_14A0\nloc_1510:\nxor eax, eax\njmp loc_1488\nloc_1520:\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "char *__fastcall sub_13F0(__int64 a1, int *a2, int a3, char **a4)\n{\n __int64 v5; // r14\n int *v6; // rbx\n char *result; // rax\n char *v8; // r13\n __int64 v9; // rbp\n size_t v10; // r14\n int v11; // r12d\n _QWORD *v12; // rax\n _QWORD *v13; // rdi\n __int64 v14; // rdx\n __int64 i; // rax\n int *v16; // [rsp+8h] [rbp-50h]\n\n v5 = a3;\n v6 = a2;\n result = (char *)malloc(8LL * a3);\n *a4 = result;\n if ( (int)v5 > 0 )\n {\n v8 = result;\n v9 = 0LL;\n v16 = &a2[v5];\n while ( 1 )\n {\n v10 = *v6;\n v11 = *v6;\n v12 = malloc(8 * v10);\n *(_QWORD *)&v8[v9] = v12;\n v13 = v12;\n if ( (int)v10 <= 0 )\n goto LABEL_7;\n v14 = *(_QWORD *)(a1 + v9);\n if ( (unsigned int)(v10 - 1) <= 2 )\n break;\n i = 0LL;\n if ( v13 == (_QWORD *)(v14 + 8) )\n goto LABEL_6;\n do\n {\n *(__m128i *)&v13[i] = _mm_loadu_si128((const __m128i *)(v14 + i * 8));\n i += 2LL;\n }\n while ( i != 2LL * ((unsigned int)v10 >> 1) );\n if ( (v11 & 1) != 0 )\n v13[v11 & 0xFFFFFFFE] = *(_QWORD *)(v14 + 8LL * (v11 & 0xFFFFFFFE));\nLABEL_7:\n ++v6;\n v9 += 8LL;\n qsort(v13, v10, 8uLL, compar);\n result = (char *)v16;\n if ( v6 == v16 )\n return result;\n v8 = *a4;\n }\n for ( i = 0LL; i != v10; ++i )\nLABEL_6:\n v13[i] = *(_QWORD *)(v14 + i * 8);\n goto LABEL_7;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_13F0(long long a1, int *a2, int a3, char **a4) {\n long long v5;\n int *v6;\n char *result;\n char *v8;\n long long v9;\n unsigned int v10;\n int v11;\n uint64_t *v12;\n uint64_t *v13;\n long long v14;\n long long i;\n int *v16;\n v5 = a3;\n v6 = a2;\n result = (char *)malloc(8LL * a3);\n *a4 = result;\n if ((int)v5 > 0) {\n v8 = result;\n v9 = 0LL;\n v16 = &a2[v5];\n while (1) {\n v10 = *v6;\n v11 = *v6;\n v12 = malloc(8 * v10);\n *(uint64_t *)&v8[v9] = v12;\n v13 = v12;\n if ((int)v10 <= 0) goto LABEL_7;\n v14 = *(uint64_t *)(a1 + v9);\n if ((unsigned int)(v10 - 1) <= 2) break;\n i = 0LL;\n if (v13 == (uint64_t *)(v14 + 8)) goto LABEL_6;\n do {\n *(__m128i *)&v13[i] = _mm_loadu_si128((const __m128i *)(v14 + i * 8));\n i += 2LL;\n } while (i != 2LL * ((unsigned int)v10 >> 1));\n if ((v11 & 1) != 0)\n v13[v11 & 4294967294] = *(uint64_t *)(v14 + 8LL * (v11 & 4294967294));\n LABEL_7:\n ++v6;\n v9 += 8LL;\n qsort(v13, v10, 8uLL, compar);\n result = (char *)v16;\n if (v6 == v16) return result;\n v8 = *a4;\n }\n for (i = 0LL; i != v10; ++i)\n LABEL_6:\n v13[i] = *(uint64_t *)(v14 + i * 8);\n goto LABEL_7;\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int *a2, int a3, char **a4) {\n long long v5;\n int *v6;\n char *result;\n char *v8;\n long long v9;\n unsigned int v10;\n int v11;\n uint64_t *v12;\n uint64_t *v13;\n long long v14;\n long long i;\n int *v16;\n v5 = a3;\n v6 = a2;\n result = (char *)malloc(8LL * a3);\n *a4 = result;\n if ((int)v5 > 0) {\n v8 = result;\n v9 = 0LL;\n v16 = &a2[v5];\n while (1) {\n v10 = *v6;\n v11 = *v6;\n v12 = malloc(8 * v10);\n *(uint64_t *)&v8[v9] = v12;\n v13 = v12;\n if ((int)v10 <= 0) goto LABEL_7;\n v14 = *(uint64_t *)(a1 + v9);\n if ((unsigned int)(v10 - 1) <= 2) break;\n i = 0LL;\n if (v13 == (uint64_t *)(v14 + 8)) goto LABEL_6;\n do {\n *(__m128i *)&v13[i] = _mm_loadu_si128((const __m128i *)(v14 + i * 8));\n i += 2LL;\n } while (i != 2LL * ((unsigned int)v10 >> 1));\n if ((v11 & 1) != 0)\n v13[v11 & 4294967294] = *(uint64_t *)(v14 + 8LL * (v11 & 4294967294));\n LABEL_7:\n ++v6;\n v9 += 8LL;\n qsort(v13, v10, 8uLL, compare);\n result = (char *)v16;\n if (v6 == v16) return result;\n v8 = *a4;\n }\n for (i = 0LL; i != v10; ++i)\n LABEL_6:\n v13[i] = *(uint64_t *)(v14 + i * 8);\n goto LABEL_7;\n }\n return result;\n}" + }, + { + "index": 105, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int lst[], int size) {\n int total = 0;\n for (int i = 0; i < size; i++) {\n total += lst[i];\n }\n return total;\n}", + "test": "int main() {\n\n int lst1[] = {1, 0, 1};\n\n int lst2[] = {0, 0};\n\n int lst3[] = {1, 1, 1};\n\n\n\n assert(func0(lst1, 3) == 2);\n\n assert(func0(lst2, 2) == 0);\n\n assert(func0(lst3, 3) == 3);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11a5 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nadd %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1188 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11A5\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_11A5:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n v3 += *(_DWORD *)(4LL * i + a1);\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11A5\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_11A5:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n v3 += *(_DWORD *)(4LL * i + a1);\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) v3 += *(uint32_t *)(4LL * i + a1);\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) v3 += *(uint32_t *)(4LL * i + a1);\n return v3;\n}" + }, + { + "index": 105, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int lst[], int size) {\n int total = 0;\n for (int i = 0; i < size; i++) {\n total += lst[i];\n }\n return total;\n}", + "test": "int main() {\n\n int lst1[] = {1, 0, 1};\n\n int lst2[] = {0, 0};\n\n int lst3[] = {1, 1, 1};\n\n\n\n assert(func0(lst1, 3) == 2);\n\n assert(func0(lst2, 2) == 0);\n\n assert(func0(lst3, 3) == 3);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 118f \nmov %rdi,%rax\nlea -0x1(%rsi),%edx\nlea 0x4(%rdi,%rdx,4),%rcx\nmov $0x0,%edx\nadd (%rax),%edx\nadd $0x4,%rax\ncmp %rcx,%rax\njne 1181 \nmov %edx,%eax\nretq\nmov $0x0,%edx\njmp 118c \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_118E\nmov rax, rdi\nmovsxd rsi, esi\nlea rcx, [rdi+rsi*4]\nmov edx, 0\nloc_1180:\nadd edx, [rax]\nadd rax, 4\ncmp rax, rcx\njnz short loc_1180\nloc_118B:\nmov eax, edx\nretn\nloc_118E:\nmov edx, 0\njmp short loc_118B", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n unsigned int v3; // edx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = 0;\n do\n v3 += *v2++;\n while ( v2 != &a1[a2] );\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_118E\nmov rax, rdi\nmovsxd rsi, esi\nlea rcx, [rdi+rsi*4]\nmov edx, 0\nloc_1180:\nadd edx, [rax]\nadd rax, 4\ncmp rax, rcx\njnz short loc_1180\nloc_118B:\nmov eax, edx\nretn\nloc_118E:\nmov edx, 0\njmp short loc_118B", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n unsigned int v3; // edx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = 0;\n do\n v3 += *v2++;\n while ( v2 != &a1[a2] );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2) {\n uint32_t *v2;\n unsigned int v3;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = 0;\n do\n v3 += *v2++;\n while (v2 != &a1[a2]);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n unsigned int v3;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = 0;\n do\n v3 += *v2++;\n while (v2 != &a1[a2]);\n }\n return v3;\n}" + }, + { + "index": 106, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int *func0(int test_list[], int test_list_size, int test_tup[],\n int test_tup_size, int res[], int res_size) {\n int i, j;\n for (i = 0; i < test_tup_size; i++) {\n res[i] = test_tup[i];\n }\n for (j = 0; j < test_list_size; j++) {\n res[i + j] = test_list[j];\n }\n return res;\n}", + "test": "int main() {\n\n int res1[5], res2[5], res3[5];\n\n \n\n int list1[] = {5, 6, 7}, tup1[] = {9, 10};\n\n int list2[] = {6, 7, 8}, tup2[] = {10, 11};\n\n int list3[] = {7, 8, 9}, tup3[] = {11, 12};\n\n\n\n func0(list1, 3, tup1, 2, res1, 5);\n\n assert(res1[0] == 9 && res1[1] == 10 && res1[2] == 5 && res1[3] == 6 && res1[4] == 7);\n\n\n\n func0(list2, 3, tup2, 2, res2, 5);\n\n assert(res2[0] == 10 && res2[1] == 11 && res2[2] == 6 && res2[3] == 7 && res2[4] == 8);\n\n\n\n func0(list3, 3, tup3, 2, res3, 5);\n\n assert(res3[0] == 11 && res3[1] == 12 && res3[2] == 7 && res3[3] == 8 && res3[4] == 9);\n\n\n\n printf(\"All tests passed!\\n\");\n\n \n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %ecx,-0x20(%rbp)\nmov %r8,-0x30(%rbp)\nmov %r9d,-0x34(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11e1 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov -0x8(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x30(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x20(%rbp),%eax\njl 11b0 \nmovl $0x0,-0x4(%rbp)\njmp 1228 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0x8(%rbp),%ecx\nmov -0x4(%rbp),%edx\nadd %ecx,%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x30(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11f2 \nmov -0x30(%rbp),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov [rbp+var_30], r8\nmov [rbp+var_34], r9d\nmov [rbp+var_8], 0\njmp short loc_11E1\nloc_11B0:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_30]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_8], 1\nloc_11E1:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_20]\njl short loc_11B0\nmov [rbp+var_4], 0\njmp short loc_1228\nloc_11F2:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov ecx, [rbp+var_8]\nmov edx, [rbp+var_4]\nadd edx, ecx\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_30]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_4], 1\nloc_1228:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11F2\nmov rax, [rbp+var_30]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3, int a4, __int64 a5)\n{\n int i; // [rsp+2Ch] [rbp-8h]\n int j; // [rsp+30h] [rbp-4h]\n\n for ( i = 0; i < a4; ++i )\n *(_DWORD *)(4LL * i + a5) = *(_DWORD *)(4LL * i + a3);\n for ( j = 0; j < a2; ++j )\n *(_DWORD *)(4LL * (i + j) + a5) = *(_DWORD *)(4LL * j + a1);\n return a5;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov [rbp+var_30], r8\nmov [rbp+var_34], r9d\nmov [rbp+var_8], 0\njmp short loc_11E1\nloc_11B0:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_30]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_8], 1\nloc_11E1:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_20]\njl short loc_11B0\nmov [rbp+var_4], 0\njmp short loc_1228\nloc_11F2:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov ecx, [rbp+var_8]\nmov edx, [rbp+var_4]\nadd edx, ecx\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_30]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_4], 1\nloc_1228:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11F2\nmov rax, [rbp+var_30]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2, __int64 a3, int a4, __int64 a5)\n{\n int i; // [rsp+2Ch] [rbp-8h]\n int j; // [rsp+30h] [rbp-4h]\n\n for ( i = 0; i < a4; ++i )\n *(_DWORD *)(4LL * i + a5) = *(_DWORD *)(4LL * i + a3);\n for ( j = 0; j < a2; ++j )\n *(_DWORD *)(4LL * (i + j) + a5) = *(_DWORD *)(4LL * j + a1);\n return a5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2, long long a3, int a4, long long a5) {\n int i;\n int j;\n for (i = 0; i < a4; ++i)\n *(uint32_t *)(4LL * i + a5) = *(uint32_t *)(4LL * i + a3);\n for (j = 0; j < a2; ++j)\n *(uint32_t *)(4LL * (i + j) + a5) = *(uint32_t *)(4LL * j + a1);\n return a5;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3, int a4, long long a5) {\n int i;\n int j;\n for (i = 0; i < a4; ++i)\n *(uint32_t *)(4LL * i + a5) = *(uint32_t *)(4LL * i + a3);\n for (j = 0; j < a2; ++j)\n *(uint32_t *)(4LL * (i + j) + a5) = *(uint32_t *)(4LL * j + a1);\n return a5;\n}" + }, + { + "index": 106, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int *func0(int test_list[], int test_list_size, int test_tup[],\n int test_tup_size, int res[], int res_size) {\n int i, j;\n for (i = 0; i < test_tup_size; i++) {\n res[i] = test_tup[i];\n }\n for (j = 0; j < test_list_size; j++) {\n res[i + j] = test_list[j];\n }\n return res;\n}", + "test": "int main() {\n\n int res1[5], res2[5], res3[5];\n\n \n\n int list1[] = {5, 6, 7}, tup1[] = {9, 10};\n\n int list2[] = {6, 7, 8}, tup2[] = {10, 11};\n\n int list3[] = {7, 8, 9}, tup3[] = {11, 12};\n\n\n\n func0(list1, 3, tup1, 2, res1, 5);\n\n assert(res1[0] == 9 && res1[1] == 10 && res1[2] == 5 && res1[3] == 6 && res1[4] == 7);\n\n\n\n func0(list2, 3, tup2, 2, res2, 5);\n\n assert(res2[0] == 10 && res2[1] == 11 && res2[2] == 6 && res2[3] == 7 && res2[4] == 8);\n\n\n\n func0(list3, 3, tup3, 2, res3, 5);\n\n assert(res3[0] == 11 && res3[1] == 12 && res3[2] == 7 && res3[3] == 8 && res3[4] == 9);\n\n\n\n printf(\"All tests passed!\\n\");\n\n \n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %r8,%rax\ntest %ecx,%ecx\njle 11d9 \nlea -0x1(%rcx),%r8d\nmov $0x0,%r9d\nmov (%rdx,%r9,4),%r10d\nmov %r10d,(%rax,%r9,4)\nmov %r9,%r10\nadd $0x1,%r9\ncmp %r8,%r10\njne 119e \ntest %esi,%esi\njle 11d8 \nlea -0x1(%rsi),%r8d\nmovslq %ecx,%rcx\nlea (%rax,%rcx,4),%rsi\nmov $0x0,%edx\nmov (%rdi,%rdx,4),%ecx\nmov %ecx,(%rsi,%rdx,4)\nmov %rdx,%rcx\nadd $0x1,%rdx\ncmp %rcx,%r8\njne 11c6 \nretq\nmov $0x0,%ecx\njmp 11b2 \n", + "ida_asm": "func0:\nendbr64\nmov r10, rdi\nmov rax, r8\ntest ecx, ecx\njle short loc_11DC\nmovsxd r8, ecx\nshl r8, 2\nmov edi, 0\nloc_11A3:\nmov r9d, [rdx+rdi]\nmov [rax+rdi], r9d\nadd rdi, 4\ncmp rdi, r8\njnz short loc_11A3\nloc_11B4:\ntest esi, esi\njle short locret_11DB\nmovsxd rsi, esi\nshl rsi, 2\nmovsxd rcx, ecx\nlea rdi, [rax+rcx*4]\nmov edx, 0\nloc_11CB:\nmov ecx, [r10+rdx]\nmov [rdi+rdx], ecx\nadd rdx, 4\ncmp rdx, rsi\njnz short loc_11CB\nlocret_11DB:\nretn\nloc_11DC:\nmov ecx, 0\njmp short loc_11B4", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3, int a4, __int64 a5)\n{\n __int64 result; // rax\n __int64 v7; // rdi\n __int64 v8; // rsi\n __int64 v9; // rdx\n\n result = a5;\n if ( a4 <= 0 )\n {\n a4 = 0;\n }\n else\n {\n v7 = 0LL;\n do\n {\n *(_DWORD *)(a5 + v7) = *(_DWORD *)(a3 + v7);\n v7 += 4LL;\n }\n while ( v7 != 4LL * a4 );\n }\n if ( a2 > 0 )\n {\n v8 = 4LL * a2;\n v9 = 0LL;\n do\n {\n *(_DWORD *)(a5 + 4LL * a4 + v9) = *(_DWORD *)(a1 + v9);\n v9 += 4LL;\n }\n while ( v9 != v8 );\n }\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\nmov r10, rdi\nmov rax, r8\ntest ecx, ecx\njle short loc_11DC\nmovsxd r8, ecx\nshl r8, 2\nmov edi, 0\nloc_11A3:\nmov r9d, [rdx+rdi]\nmov [rax+rdi], r9d\nadd rdi, 4\ncmp rdi, r8\njnz short loc_11A3\nloc_11B4:\ntest esi, esi\njle short locret_11DB\nmovsxd rsi, esi\nshl rsi, 2\nmovsxd rcx, ecx\nlea rdi, [rax+rcx*4]\nmov edx, 0\nloc_11CB:\nmov ecx, [r10+rdx]\nmov [rdi+rdx], ecx\nadd rdx, 4\ncmp rdx, rsi\njnz short loc_11CB\nlocret_11DB:\nretn\nloc_11DC:\nmov ecx, 0\njmp short loc_11B4", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2, __int64 a3, int a4, __int64 a5)\n{\n __int64 result; // rax\n __int64 v7; // rdi\n __int64 v8; // rsi\n __int64 v9; // rdx\n\n result = a5;\n if ( a4 <= 0 )\n {\n a4 = 0;\n }\n else\n {\n v7 = 0LL;\n do\n {\n *(_DWORD *)(a5 + v7) = *(_DWORD *)(a3 + v7);\n v7 += 4LL;\n }\n while ( v7 != 4LL * a4 );\n }\n if ( a2 > 0 )\n {\n v8 = 4LL * a2;\n v9 = 0LL;\n do\n {\n *(_DWORD *)(a5 + 4LL * a4 + v9) = *(_DWORD *)(a1 + v9);\n v9 += 4LL;\n }\n while ( v9 != v8 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2, long long a3, int a4, long long a5) {\n long long result;\n long long v7;\n long long v8;\n long long v9;\n result = a5;\n if (a4 <= 0) {\n a4 = 0;\n } else {\n v7 = 0LL;\n do {\n *(uint32_t *)(a5 + v7) = *(uint32_t *)(a3 + v7);\n v7 += 4LL;\n } while (v7 != 4LL * a4);\n }\n if (a2 > 0) {\n v8 = 4LL * a2;\n v9 = 0LL;\n do {\n *(uint32_t *)(a5 + 4LL * a4 + v9) = *(uint32_t *)(a1 + v9);\n v9 += 4LL;\n } while (v9 != v8);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3, int a4, long long a5) {\n long long result;\n long long v7;\n long long v8;\n long long v9;\n result = a5;\n if (a4 <= 0) {\n a4 = 0;\n } else {\n v7 = 0LL;\n do {\n *(uint32_t *)(a5 + v7) = *(uint32_t *)(a3 + v7);\n v7 += 4LL;\n } while (v7 != 4LL * a4);\n }\n if (a2 > 0) {\n v8 = 4LL * a2;\n v9 = 0LL;\n do {\n *(uint32_t *)(a5 + 4LL * a4 + v9) = *(uint32_t *)(a1 + v9);\n v9 += 4LL;\n } while (v9 != v8);\n }\n return result;\n}" + }, + { + "index": 106, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int *func0(int test_list[], int test_list_size, int test_tup[],\n int test_tup_size, int res[], int res_size) {\n int i, j;\n for (i = 0; i < test_tup_size; i++) {\n res[i] = test_tup[i];\n }\n for (j = 0; j < test_list_size; j++) {\n res[i + j] = test_list[j];\n }\n return res;\n}", + "test": "int main() {\n\n int res1[5], res2[5], res3[5];\n\n \n\n int list1[] = {5, 6, 7}, tup1[] = {9, 10};\n\n int list2[] = {6, 7, 8}, tup2[] = {10, 11};\n\n int list3[] = {7, 8, 9}, tup3[] = {11, 12};\n\n\n\n func0(list1, 3, tup1, 2, res1, 5);\n\n assert(res1[0] == 9 && res1[1] == 10 && res1[2] == 5 && res1[3] == 6 && res1[4] == 7);\n\n\n\n func0(list2, 3, tup2, 2, res2, 5);\n\n assert(res2[0] == 10 && res2[1] == 11 && res2[2] == 6 && res2[3] == 7 && res2[4] == 8);\n\n\n\n func0(list3, 3, tup3, 2, res3, 5);\n\n assert(res3[0] == 11 && res3[1] == 12 && res3[2] == 7 && res3[3] == 8 && res3[4] == 9);\n\n\n\n printf(\"All tests passed!\\n\");\n\n \n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov %r8,%rax\ntest %ecx,%ecx\njle 11c8 \nlea -0x1(%rcx),%r8d\nxor %r9d,%r9d\nnopw 0x0(%rax,%rax,1)\nmov (%rdx,%r9,4),%r10d\nmov %r10d,(%rax,%r9,4)\nmov %r9,%r10\nadd $0x1,%r9\ncmp %r8,%r10\njne 1188 \ntest %esi,%esi\njle 11c2 \nmovslq %ecx,%rcx\nlea -0x1(%rsi),%r8d\nxor %edx,%edx\nlea (%rax,%rcx,4),%rsi\nnopl (%rax)\nmov (%rdi,%rdx,4),%ecx\nmov %ecx,(%rsi,%rdx,4)\nmov %rdx,%rcx\nadd $0x1,%rdx\ncmp %rcx,%r8\njne 11b0 \nretq\nnopl 0x0(%rax,%rax,1)\nxor %ecx,%ecx\njmp 119c \nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\nmov r10, rdi\nmov rax, r8\ntest ecx, ecx\njle short loc_1410\nmovsxd r8, ecx\nxor edi, edi\nshl r8, 2\nnop word ptr [rax+rax+00000000h]\nloc_13D0:\nmov r9d, [rdx+rdi]\nmov [rax+rdi], r9d\nadd rdi, 4\ncmp rdi, r8\njnz short loc_13D0\nloc_13E1:\ntest esi, esi\njle short locret_1408\nmovsxd rsi, esi\nmovsxd rcx, ecx\nxor edx, edx\nshl rsi, 2\nlea rdi, [rax+rcx*4]\nnop dword ptr [rax]\nloc_13F8:\nmov ecx, [r10+rdx]\nmov [rdi+rdx], ecx\nadd rdx, 4\ncmp rsi, rdx\njnz short loc_13F8\nlocret_1408:\nretn\nloc_1410:\nxor ecx, ecx\njmp short loc_13E1", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3, int a4, __int64 a5)\n{\n __int64 result; // rax\n __int64 v7; // rdi\n __int64 v8; // rdx\n __int64 v9; // rsi\n\n result = a5;\n if ( a4 <= 0 )\n {\n a4 = 0;\n }\n else\n {\n v7 = 0LL;\n do\n {\n *(_DWORD *)(a5 + v7) = *(_DWORD *)(a3 + v7);\n v7 += 4LL;\n }\n while ( v7 != 4LL * a4 );\n }\n if ( a2 > 0 )\n {\n v8 = 0LL;\n v9 = 4LL * a2;\n do\n {\n *(_DWORD *)(a5 + 4LL * a4 + v8) = *(_DWORD *)(a1 + v8);\n v8 += 4LL;\n }\n while ( v9 != v8 );\n }\n return result;\n}", + "ida_strip_asm": "sub_13B0:\nendbr64\nmov r10, rdi\nmov rax, r8\ntest ecx, ecx\njle short loc_1410\nmovsxd r8, ecx\nxor edi, edi\nshl r8, 2\nnop word ptr [rax+rax+00000000h]\nloc_13D0:\nmov r9d, [rdx+rdi]\nmov [rax+rdi], r9d\nadd rdi, 4\ncmp rdi, r8\njnz short loc_13D0\nloc_13E1:\ntest esi, esi\njle short locret_1408\nmovsxd rsi, esi\nmovsxd rcx, ecx\nxor edx, edx\nshl rsi, 2\nlea rdi, [rax+rcx*4]\nnop dword ptr [rax]\nloc_13F8:\nmov ecx, [r10+rdx]\nmov [rdi+rdx], ecx\nadd rdx, 4\ncmp rsi, rdx\njnz short loc_13F8\nlocret_1408:\nretn\nloc_1410:\nxor ecx, ecx\njmp short loc_13E1", + "ida_strip_pseudo": "__int64 __fastcall sub_13B0(__int64 a1, int a2, __int64 a3, int a4, __int64 a5)\n{\n __int64 result; // rax\n __int64 v7; // rdi\n __int64 v8; // rdx\n __int64 v9; // rsi\n\n result = a5;\n if ( a4 <= 0 )\n {\n a4 = 0;\n }\n else\n {\n v7 = 0LL;\n do\n {\n *(_DWORD *)(a5 + v7) = *(_DWORD *)(a3 + v7);\n v7 += 4LL;\n }\n while ( v7 != 4LL * a4 );\n }\n if ( a2 > 0 )\n {\n v8 = 0LL;\n v9 = 4LL * a2;\n do\n {\n *(_DWORD *)(a5 + 4LL * a4 + v8) = *(_DWORD *)(a1 + v8);\n v8 += 4LL;\n }\n while ( v9 != v8 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_13B0(long long a1, int a2, long long a3, int a4, long long a5) {\n long long result;\n long long v7;\n long long v8;\n long long v9;\n result = a5;\n if (a4 <= 0) {\n a4 = 0;\n } else {\n v7 = 0LL;\n do {\n *(uint32_t *)(a5 + v7) = *(uint32_t *)(a3 + v7);\n v7 += 4LL;\n } while (v7 != 4LL * a4);\n }\n if (a2 > 0) {\n v8 = 0LL;\n v9 = 4LL * a2;\n do {\n *(uint32_t *)(a5 + 4LL * a4 + v8) = *(uint32_t *)(a1 + v8);\n v8 += 4LL;\n } while (v9 != v8);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3, int a4, long long a5) {\n long long result;\n long long v7;\n long long v8;\n long long v9;\n result = a5;\n if (a4 <= 0) {\n a4 = 0;\n } else {\n v7 = 0LL;\n do {\n *(uint32_t *)(a5 + v7) = *(uint32_t *)(a3 + v7);\n v7 += 4LL;\n } while (v7 != 4LL * a4);\n }\n if (a2 > 0) {\n v8 = 0LL;\n v9 = 4LL * a2;\n do {\n *(uint32_t *)(a5 + 4LL * a4 + v8) = *(uint32_t *)(a1 + v8);\n v8 += 4LL;\n } while (v9 != v8);\n }\n return result;\n}" + }, + { + "index": 107, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int L, int R) {\n int count = 0;\n for (int i = L; i <= R; i++) {\n if (i >= 10 && i <= 15) {\n count++;\n } else if (i > 15) {\n int k = i;\n while (k != 0) {\n if (k % 16 >= 10) {\n count++;\n }\n k = k / 16;\n }\n }\n }\n return count;\n}", + "test": "int main() {\n\n assert(func0(10, 15) == 6);\n\n assert(func0(2, 4) == 0);\n\n assert(func0(15, 16) == 1);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmovl $0x0,-0xc(%rbp)\nmov -0x14(%rbp),%eax\nmov %eax,-0x8(%rbp)\njmp 11b8 \ncmpl $0x9,-0x8(%rbp)\njle 1178 \ncmpl $0xf,-0x8(%rbp)\njg 1178 \naddl $0x1,-0xc(%rbp)\njmp 11b4 \ncmpl $0xf,-0x8(%rbp)\njle 11b4 \nmov -0x8(%rbp),%eax\nmov %eax,-0x4(%rbp)\njmp 11ae \nmov -0x4(%rbp),%eax\ncltd\nshr $0x1c,%edx\nadd %edx,%eax\nand $0xf,%eax\nsub %edx,%eax\ncmp $0x9,%eax\njle 119d \naddl $0x1,-0xc(%rbp)\nmov -0x4(%rbp),%eax\nlea 0xf(%rax),%edx\ntest %eax,%eax\ncmovs %edx,%eax\nsar $0x4,%eax\nmov %eax,-0x4(%rbp)\ncmpl $0x0,-0x4(%rbp)\njne 1186 \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x18(%rbp),%eax\njle 1166 \nmov -0xc(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_C], 0\nmov eax, [rbp+var_14]\nmov [rbp+var_8], eax\njmp short loc_11BE\nloc_1166:\ncmp [rbp+var_8], 9\njle short loc_1178\ncmp [rbp+var_8], 0Fh\njg short loc_1178\nadd [rbp+var_C], 1\njmp short loc_11BA\nloc_1178:\ncmp [rbp+var_8], 0Fh\njle short loc_11BA\nmov eax, [rbp+var_8]\nmov [rbp+var_4], eax\njmp short loc_11B4\nloc_1186:\nmov edx, [rbp+var_4]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Ch\nadd edx, eax\nand edx, 0Fh\nsub edx, eax\nmov eax, edx\ncmp eax, 9\njle short loc_11A3\nadd [rbp+var_C], 1\nloc_11A3:\nmov eax, [rbp+var_4]\nlea edx, [rax+0Fh]\ntest eax, eax\ncmovs eax, edx\nsar eax, 4\nmov [rbp+var_4], eax\nloc_11B4:\ncmp [rbp+var_4], 0\njnz short loc_1186\nloc_11BA:\nadd [rbp+var_8], 1\nloc_11BE:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_18]\njle short loc_1166\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n unsigned int v3; // [rsp+Ch] [rbp-Ch]\n int i; // [rsp+14h] [rbp-4h]\n\n v3 = 0;\n while ( a1 <= a2 )\n {\n if ( a1 <= 9 || a1 > 15 )\n {\n if ( a1 > 15 )\n {\n for ( i = a1; i; i /= 16 )\n {\n if ( i % 16 > 9 )\n ++v3;\n }\n }\n }\n else\n {\n ++v3;\n }\n ++a1;\n }\n return v3;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_C], 0\nmov eax, [rbp+var_14]\nmov [rbp+var_8], eax\njmp short loc_11BE\nloc_1166:\ncmp [rbp+var_8], 9\njle short loc_1178\ncmp [rbp+var_8], 0Fh\njg short loc_1178\nadd [rbp+var_C], 1\njmp short loc_11BA\nloc_1178:\ncmp [rbp+var_8], 0Fh\njle short loc_11BA\nmov eax, [rbp+var_8]\nmov [rbp+var_4], eax\njmp short loc_11B4\nloc_1186:\nmov edx, [rbp+var_4]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Ch\nadd edx, eax\nand edx, 0Fh\nsub edx, eax\nmov eax, edx\ncmp eax, 9\njle short loc_11A3\nadd [rbp+var_C], 1\nloc_11A3:\nmov eax, [rbp+var_4]\nlea edx, [rax+0Fh]\ntest eax, eax\ncmovs eax, edx\nsar eax, 4\nmov [rbp+var_4], eax\nloc_11B4:\ncmp [rbp+var_4], 0\njnz short loc_1186\nloc_11BA:\nadd [rbp+var_8], 1\nloc_11BE:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_18]\njle short loc_1166\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2)\n{\n unsigned int v3; // [rsp+Ch] [rbp-Ch]\n int i; // [rsp+14h] [rbp-4h]\n\n v3 = 0;\n while ( a1 <= a2 )\n {\n if ( a1 <= 9 || a1 > 15 )\n {\n if ( a1 > 15 )\n {\n for ( i = a1; i; i /= 16 )\n {\n if ( i % 16 > 9 )\n ++v3;\n }\n }\n }\n else\n {\n ++v3;\n }\n ++a1;\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n while (a1 <= a2) {\n if (a1 <= 9 || a1 > 15) {\n if (a1 > 15) {\n for (i = a1; i; i /= 16) {\n if (i % 16 > 9) ++v3;\n }\n }\n } else {\n ++v3;\n }\n ++a1;\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n while (a1 <= a2) {\n if (a1 <= 9 || a1 > 15) {\n if (a1 > 15) {\n for (i = a1; i; i /= 16) {\n if (i % 16 > 9) ++v3;\n }\n }\n } else {\n ++v3;\n }\n ++a1;\n }\n return v3;\n}" + }, + { + "index": 107, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int L, int R) {\n int count = 0;\n for (int i = L; i <= R; i++) {\n if (i >= 10 && i <= 15) {\n count++;\n } else if (i > 15) {\n int k = i;\n while (k != 0) {\n if (k % 16 >= 10) {\n count++;\n }\n k = k / 16;\n }\n }\n }\n return count;\n}", + "test": "int main() {\n\n assert(func0(10, 15) == 6);\n\n assert(func0(2, 4) == 0);\n\n assert(func0(15, 16) == 1);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ncmp %esi,%edi\njg 11a4 \nlea 0x1(%rsi),%r8d\nmov $0x0,%esi\njmp 1169 \ncmp $0xf,%edi\njg 1176 \nadd $0x1,%edi\ncmp %r8d,%edi\nje 11a9 \nlea -0xa(%rdi),%eax\ncmp $0x5,%eax\nja 115c \nadd $0x1,%esi\njmp 1161 \nmov %edi,%edx\nmov %edx,%ecx\nsar $0x1f,%ecx\nshr $0x1c,%ecx\nlea (%rdx,%rcx,1),%eax\nand $0xf,%eax\nsub %ecx,%eax\ncmp $0x9,%eax\nsetg %al\nmovzbl %al,%eax\nadd %eax,%esi\nlea 0xf(%rdx),%eax\ntest %edx,%edx\ncmovns %edx,%eax\nsar $0x4,%eax\nmov %eax,%edx\njne 1178 \njmp 1161 \nmov $0x0,%esi\nmov %esi,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ncmp edi, esi\njg short loc_11A5\nadd esi, 1\nmov r8d, 0\njmp short loc_1168\nloc_115C:\ncmp edi, 0Fh\njg short loc_1176\nloc_1161:\nadd edi, 1\ncmp edi, esi\njz short loc_11AB\nloc_1168:\nlea eax, [rdi-0Ah]\ncmp eax, 5\nja short loc_115C\nadd r8d, 1\njmp short loc_1161\nloc_1176:\nmov edx, edi\nloc_1178:\nmov ecx, edx\nsar ecx, 1Fh\nshr ecx, 1Ch\nlea eax, [rdx+rcx]\nand eax, 0Fh\nsub eax, ecx\ncmp eax, 9\nsetnle al\nmovzx eax, al\nadd r8d, eax\nlea eax, [rdx+0Fh]\ntest edx, edx\ncmovns eax, edx\nsar eax, 4\nmov edx, eax\njnz short loc_1178\njmp short loc_1161\nloc_11A5:\nmov r8d, 0\nloc_11AB:\nmov eax, r8d\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n int v2; // eax\n int v3; // esi\n unsigned int v4; // r8d\n int v5; // edx\n\n if ( a1 > a2 )\n {\n return 0;\n }\n else\n {\n v3 = a2 + 1;\n v4 = 0;\n do\n {\n if ( (unsigned int)(a1 - 10) > 5 )\n {\n if ( a1 > 15 )\n {\n v5 = a1;\n do\n {\n v4 += v5 % 16 > 9;\n v5 /= 16;\n }\n while ( v2 >> 4 );\n }\n }\n else\n {\n ++v4;\n }\n ++a1;\n }\n while ( a1 != v3 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ncmp edi, esi\njg short loc_11A5\nadd esi, 1\nmov r8d, 0\njmp short loc_1168\nloc_115C:\ncmp edi, 0Fh\njg short loc_1176\nloc_1161:\nadd edi, 1\ncmp edi, esi\njz short loc_11AB\nloc_1168:\nlea eax, [rdi-0Ah]\ncmp eax, 5\nja short loc_115C\nadd r8d, 1\njmp short loc_1161\nloc_1176:\nmov edx, edi\nloc_1178:\nmov ecx, edx\nsar ecx, 1Fh\nshr ecx, 1Ch\nlea eax, [rdx+rcx]\nand eax, 0Fh\nsub eax, ecx\ncmp eax, 9\nsetnle al\nmovzx eax, al\nadd r8d, eax\nlea eax, [rdx+0Fh]\ntest edx, edx\ncmovns eax, edx\nsar eax, 4\nmov edx, eax\njnz short loc_1178\njmp short loc_1161\nloc_11A5:\nmov r8d, 0\nloc_11AB:\nmov eax, r8d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2)\n{\n int v2; // eax\n int v3; // esi\n unsigned int v4; // r8d\n int v5; // edx\n\n if ( a1 > a2 )\n {\n return 0;\n }\n else\n {\n v3 = a2 + 1;\n v4 = 0;\n do\n {\n if ( (unsigned int)(a1 - 10) > 5 )\n {\n if ( a1 > 15 )\n {\n v5 = a1;\n do\n {\n v4 += v5 % 16 > 9;\n v5 /= 16;\n }\n while ( v2 >> 4 );\n }\n }\n else\n {\n ++v4;\n }\n ++a1;\n }\n while ( a1 != v3 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2) {\n int v2;\n int v3;\n unsigned int v4;\n int v5;\n if (a1 > a2) {\n return 0;\n } else {\n v3 = a2 + 1;\n v4 = 0;\n do {\n if ((unsigned int)(a1 - 10) > 5) {\n if (a1 > 15) {\n v5 = a1;\n do {\n v4 += v5 % 16 > 9;\n v5 /= 16;\n } while (v2 >> 4);\n }\n } else {\n ++v4;\n }\n ++a1;\n } while (a1 != v3);\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n int v2;\n int v3;\n unsigned int v4;\n int v5;\n if (a1 > a2) {\n return 0;\n } else {\n v3 = a2 + 1;\n v4 = 0;\n do {\n if ((unsigned int)(a1 - 10) > 5) {\n if (a1 > 15) {\n v5 = a1;\n do {\n v4 += v5 % 16 > 9;\n v5 /= 16;\n } while (v2 >> 4);\n }\n } else {\n ++v4;\n }\n ++a1;\n } while (a1 != v3);\n }\n return v4;\n}" + }, + { + "index": 107, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int L, int R) {\n int count = 0;\n for (int i = L; i <= R; i++) {\n if (i >= 10 && i <= 15) {\n count++;\n } else if (i > 15) {\n int k = i;\n while (k != 0) {\n if (k % 16 >= 10) {\n count++;\n }\n k = k / 16;\n }\n }\n }\n return count;\n}", + "test": "int main() {\n\n assert(func0(10, 15) == 6);\n\n assert(func0(2, 4) == 0);\n\n assert(func0(15, 16) == 1);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ncmp %esi,%edi\njg 1198 \nadd $0x1,%esi\nxor %r8d,%r8d\njmp 115b \nadd $0x1,%r8d\nadd $0x1,%edi\ncmp %edi,%esi\nje 118d \nlea -0xa(%rdi),%eax\ncmp $0x5,%eax\njbe 1150 \ncmp $0xf,%edi\njle 1154 \nmov %edi,%eax\nnopw 0x0(%rax,%rax,1)\nmov %eax,%edx\nand $0xf,%edx\ncmp $0x9,%edx\nsetg %dl\nmovzbl %dl,%edx\nadd %edx,%r8d\nsar $0x4,%eax\njne 1170 \nadd $0x1,%edi\ncmp %edi,%esi\njne 115b \nmov %r8d,%eax\nretq\nnopl 0x0(%rax)\nxor %r8d,%r8d\nmov %r8d,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ncmp edi, esi\njg short loc_1268\nadd esi, 1\nxor r8d, r8d\njmp short loc_121B\nloc_1210:\nadd r8d, 1\nloc_1214:\nadd edi, 1\ncmp edi, esi\njz short loc_1260\nloc_121B:\nlea eax, [rdi-0Ah]\ncmp eax, 5\njbe short loc_1210\ncmp edi, 0Fh\njle short loc_1214\nmov eax, edi\nnop word ptr [rax+rax+00h]\nloc_1230:\nmov ecx, eax\nsar ecx, 1Fh\nshr ecx, 1Ch\nlea edx, [rax+rcx]\nand edx, 0Fh\nsub edx, ecx\ncmp edx, 9\nsetnle dl\nmovzx edx, dl\nadd r8d, edx\ntest eax, eax\nlea edx, [rax+0Fh]\ncmovs eax, edx\nsar eax, 4\njnz short loc_1230\nadd edi, 1\ncmp edi, esi\njnz short loc_121B\nloc_1260:\nmov eax, r8d\nretn\nloc_1268:\nxor r8d, r8d\nmov eax, r8d\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n int v2; // esi\n unsigned int v3; // r8d\n int v4; // eax\n\n if ( a1 <= a2 )\n {\n v2 = a2 + 1;\n v3 = 0;\n while ( 1 )\n {\n while ( (unsigned int)(a1 - 10) <= 5 )\n {\n ++v3;\nLABEL_4:\n if ( ++a1 == v2 )\n return v3;\n }\n if ( a1 <= 15 )\n goto LABEL_4;\n v4 = a1;\n do\n {\n v3 += v4 % 16 > 9;\n v4 /= 16;\n }\n while ( v4 );\n if ( ++a1 == v2 )\n return v3;\n }\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1200:\nendbr64\ncmp edi, esi\njg short loc_1268\nadd esi, 1\nxor r8d, r8d\njmp short loc_121B\nloc_1210:\nadd r8d, 1\nloc_1214:\nadd edi, 1\ncmp edi, esi\njz short loc_1260\nloc_121B:\nlea eax, [rdi-0Ah]\ncmp eax, 5\njbe short loc_1210\ncmp edi, 0Fh\njle short loc_1214\nmov eax, edi\nnop word ptr [rax+rax+00h]\nloc_1230:\nmov ecx, eax\nsar ecx, 1Fh\nshr ecx, 1Ch\nlea edx, [rax+rcx]\nand edx, 0Fh\nsub edx, ecx\ncmp edx, 9\nsetnle dl\nmovzx edx, dl\nadd r8d, edx\ntest eax, eax\nlea edx, [rax+0Fh]\ncmovs eax, edx\nsar eax, 4\njnz short loc_1230\nadd edi, 1\ncmp edi, esi\njnz short loc_121B\nloc_1260:\nmov eax, r8d\nretn\nloc_1268:\nxor r8d, r8d\nmov eax, r8d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1200(int a1, int a2)\n{\n int v2; // esi\n unsigned int v3; // r8d\n int v4; // eax\n\n if ( a1 <= a2 )\n {\n v2 = a2 + 1;\n v3 = 0;\n while ( 1 )\n {\n while ( (unsigned int)(a1 - 10) <= 5 )\n {\n ++v3;\nLABEL_4:\n if ( ++a1 == v2 )\n return v3;\n }\n if ( a1 <= 15 )\n goto LABEL_4;\n v4 = a1;\n do\n {\n v3 += v4 % 16 > 9;\n v4 /= 16;\n }\n while ( v4 );\n if ( ++a1 == v2 )\n return v3;\n }\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1200(int a1, int a2) {\n int v2;\n unsigned int v3;\n int v4;\n if (a1 <= a2) {\n v2 = a2 + 1;\n v3 = 0;\n while (1) {\n while ((unsigned int)(a1 - 10) <= 5) {\n ++v3;\n LABEL_4:\n if (++a1 == v2) return v3;\n }\n if (a1 <= 15) goto LABEL_4;\n v4 = a1;\n do {\n v3 += v4 % 16 > 9;\n v4 /= 16;\n } while (v4);\n if (++a1 == v2) return v3;\n }\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n int v2;\n unsigned int v3;\n int v4;\n if (a1 <= a2) {\n v2 = a2 + 1;\n v3 = 0;\n while (1) {\n while ((unsigned int)(a1 - 10) <= 5) {\n ++v3;\n LABEL_4:\n if (++a1 == v2) return v3;\n }\n if (a1 <= 15) goto LABEL_4;\n v4 = a1;\n do {\n v3 += v4 % 16 > 9;\n v4 /= 16;\n } while (v4);\n if (++a1 == v2) return v3;\n }\n }\n return 0LL;\n}" + }, + { + "index": 108, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n// Compare function for qsort\n\nint compare(const void *a, const void *b) {\n\n int int_a = *(const int*) a;\n\n int int_b = *(const int*) b;\n\n return (int_a > int_b) - (int_a < int_b);\n\n}\n\n\n\n// Function to merge three sorted lists\n\n", + "func": "int *func0(int num1[], int size1, int num2[], int size2, int num3[], int size3,\n int *result_size) {\n qsort(num1, size1, sizeof(int), compare);\n qsort(num2, size2, sizeof(int), compare);\n qsort(num3, size3, sizeof(int), compare);\n *result_size = size1 + size2 + size3;\n int *result = malloc(*result_size * sizeof(int));\n if (!result) {\n perror(\"Failed to allocate memory\");\n exit(EXIT_FAILURE);\n }\n int i = 0, j = 0, k = 0, l = 0;\n while (i < size1 && j < size2 && k < size3) {\n if (num1[i] <= num2[j] && num1[i] <= num3[k]) {\n result[l++] = num1[i++];\n } else if (num2[j] <= num1[i] && num2[j] <= num3[k]) {\n result[l++] = num2[j++];\n } else {\n result[l++] = num3[k++];\n }\n }\n while (i < size1 && j < size2) {\n result[l++] = (num1[i] <= num2[j]) ? num1[i++] : num2[j++];\n }\n while (i < size1 && k < size3) {\n result[l++] = (num1[i] <= num3[k]) ? num1[i++] : num3[k++];\n }\n while (j < size2 && k < size3) {\n result[l++] = (num2[j] <= num3[k]) ? num2[j++] : num3[k++];\n }\n while (i < size1) {\n result[l++] = num1[i++];\n }\n while (j < size2) {\n result[l++] = num2[j++];\n }\n while (k < size3) {\n result[l++] = num3[k++];\n }\n return result;\n}", + "test": "int main() {\n\n // First test case\n\n int num1_1[] = {25, 24, 15, 4, 5, 29, 110};\n\n int size1_1 = sizeof(num1_1) / sizeof(num1_1[0]);\n\n int num2_1[] = {19, 20, 11, 56, 25, 233, 154};\n\n int size2_1 = sizeof(num2_1) / sizeof(num2_1[0]);\n\n int num3_1[] = {24, 26, 54, 48};\n\n int size3_1 = sizeof(num3_1) / sizeof(num3_1[0]);\n\n int expected1[] = {4, 5, 11, 15, 19, 20, 24, 24, 25, 25, 26, 29, 48, 54, 56, 110, 154, 233};\n\n int expected_size1 = sizeof(expected1) / sizeof(expected1[0]);\n\n int result_size1;\n\n int *result1 = func0(num1_1, size1_1, num2_1, size2_1, num3_1, size3_1, &result_size1);\n\n assert(result_size1 == expected_size1);\n\n for(int i = 0; i < expected_size1; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n free(result1);\n\n\n\n // Second test case\n\n int num1_2[] = {1, 3, 5, 6, 8, 9};\n\n int size1_2 = sizeof(num1_2) / sizeof(num1_2[0]);\n\n int num2_2[] = {2, 5, 7, 11};\n\n int size2_2 = sizeof(num2_2) / sizeof(num2_2[0]);\n\n int num3_2[] = {1, 4, 7, 8, 12};\n\n int size3_2 = sizeof(num3_2) / sizeof(num3_2[0]);\n\n int expected2[] = {1, 1, 2, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 11, 12};\n\n int expected_size2 = sizeof(expected2) / sizeof(expected2[0]);\n\n int result_size2;\n\n int *result2 = func0(num1_2, size1_2, num2_2, size2_2, num3_2, size3_2, &result_size2);\n\n assert(result_size2 == expected_size2);\n\n for(int i = 0; i < expected_size2; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n free(result2);\n\n\n\n // Third test case\n\n int num1_3[] = {18, 14, 10, 9, 8, 7, 9, 3, 2, 4, 1};\n\n int size1_3 = sizeof(num1_3) / sizeof(num1_3[0]);\n\n int num2_3[] = {25, 35, 22, 85, 14, 65, 75, 25, 58};\n\n int size2_3 = sizeof(num2_3) / sizeof(num2_3[0]);\n\n int num3_3[] = {12, 74, 9, 50, 61, 41};\n\n int size3_3 = sizeof(num3_3) / sizeof(num3_3[0]);\n\n int expected3[] = {1, 2, 3, 4, 7, 8, 9, 9, 9, 10, 12, 14, 14, 18, 22, 25, 25, 35, 41, 50, 58, 61, 65, 74, 75, 85};\n\n int expected_size3 = sizeof(expected3) / sizeof(expected3[0]);\n\n int result_size3;\n\n int *result3 = func0(num1_3, size1_3, num2_3, size2_3, num3_3, size3_3, &result_size3);\n\n assert(result_size3 == expected_size3);\n\n for(int i = 0; i < expected_size3; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x50,%rsp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmov %rdx,-0x38(%rbp)\nmov %ecx,-0x30(%rbp)\nmov %r8,-0x40(%rbp)\nmov %r9d,-0x44(%rbp)\nmov -0x2c(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x28(%rbp),%rax\nlea -0x73(%rip),%rcx\nmov $0x4,%edx\nmov %rax,%rdi\ncallq 10c0 \nmov -0x30(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x38(%rbp),%rax\nlea -0x91(%rip),%rcx\nmov $0x4,%edx\nmov %rax,%rdi\ncallq 10c0 \nmov -0x44(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x40(%rbp),%rax\nlea -0xaf(%rip),%rcx\nmov $0x4,%edx\nmov %rax,%rdi\ncallq 10c0 \nmov -0x2c(%rbp),%edx\nmov -0x30(%rbp),%eax\nadd %eax,%edx\nmov -0x44(%rbp),%eax\nadd %eax,%edx\nmov 0x10(%rbp),%rax\nmov %edx,(%rax)\nmov 0x10(%rbp),%rax\nmov (%rax),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10f0 \nmov %rax,-0x8(%rbp)\ncmpq $0x0,-0x8(%rbp)\njne 130d \nlea 0xd0a(%rip),%rdi\ncallq 1100 \nmov $0x1,%edi\ncallq 1110 \nmovl $0x0,-0x18(%rbp)\nmovl $0x0,-0x14(%rbp)\nmovl $0x0,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\njmpq 14a0 \nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x38(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njg 13cc \nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x40(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njg 13cc \nmov -0x18(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x18(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0xc(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0xc(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\njmpq 14a0 \nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njg 1467 \nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x40(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njg 1467 \nmov -0x14(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x14(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x38(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0xc(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0xc(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\njmp 14a0 \nmov -0x10(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x10(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x40(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0xc(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0xc(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\nmov -0x18(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njge 1550 \nmov -0x14(%rbp),%eax\ncmp -0x30(%rbp),%eax\njge 1550 \nmov -0x10(%rbp),%eax\ncmp -0x44(%rbp),%eax\njl 132e \njmpq 1550 \nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x38(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njg 1517 \nmov -0x18(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x18(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\njmp 1533 \nmov -0x14(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x14(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov -0xc(%rbp),%edx\nlea 0x1(%rdx),%ecx\nmov %ecx,-0xc(%rbp)\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nmov %eax,(%rdx)\nmov -0x18(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njge 15f4 \nmov -0x14(%rbp),%eax\ncmp -0x30(%rbp),%eax\njl 14c9 \njmpq 15f4 \nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x40(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njg 15bb \nmov -0x18(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x18(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\njmp 15d7 \nmov -0x10(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x10(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x40(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov -0xc(%rbp),%edx\nlea 0x1(%rdx),%ecx\nmov %ecx,-0xc(%rbp)\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nmov %eax,(%rdx)\nmov -0x18(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njge 1698 \nmov -0x10(%rbp),%eax\ncmp -0x44(%rbp),%eax\njl 156d \njmpq 1698 \nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x40(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njg 165f \nmov -0x14(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x14(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\njmp 167b \nmov -0x10(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x10(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x40(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov -0xc(%rbp),%edx\nlea 0x1(%rdx),%ecx\nmov %ecx,-0xc(%rbp)\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nmov %eax,(%rdx)\nmov -0x14(%rbp),%eax\ncmp -0x30(%rbp),%eax\njge 16e7 \nmov -0x10(%rbp),%eax\ncmp -0x44(%rbp),%eax\njl 1611 \njmp 16e7 \nmov -0x18(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x18(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0xc(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0xc(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\nmov -0x18(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 16ae \njmp 172a \nmov -0x14(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x14(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x38(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0xc(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0xc(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\nmov -0x14(%rbp),%eax\ncmp -0x30(%rbp),%eax\njl 16f1 \njmp 176d \nmov -0x10(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x10(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x40(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0xc(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0xc(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\nmov -0x10(%rbp),%eax\ncmp -0x44(%rbp),%eax\njl 1734 \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+base], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmov [rbp+var_30], ecx\nmov [rbp+var_40], r8\nmov [rbp+var_44], r9d\nmov eax, [rbp+var_2C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compare\nmov rcx, rdx; compar\nmov edx, 4; size\nmov rdi, rax; base\ncall _qsort\nmov eax, [rbp+var_30]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+var_38]\nlea rdx, compare\nmov rcx, rdx; compar\nmov edx, 4; size\nmov rdi, rax; base\ncall _qsort\nmov eax, [rbp+var_44]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+var_40]\nlea rdx, compare\nmov rcx, rdx; compar\nmov edx, 4; size\nmov rdi, rax; base\ncall _qsort\nmov edx, [rbp+var_2C]\nmov eax, [rbp+var_30]\nadd edx, eax\nmov eax, [rbp+var_44]\nadd edx, eax\nmov rax, [rbp+arg_0]\nmov [rax], edx\nmov rax, [rbp+arg_0]\nmov eax, [rax]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\ncmp [rbp+var_8], 0\njnz short loc_1319\nlea rax, s; \"Failed to allocate memory\"\nmov rdi, rax; s\ncall _perror\nmov edi, 1; status\ncall _exit\nloc_1319:\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp loc_14AC\nloc_133A:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_14]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njg short loc_13D8\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njg short loc_13D8\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\njmp loc_14AC\nloc_13D8:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_18]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njg short loc_1473\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njg short loc_1473\nmov eax, [rbp+var_14]\nlea edx, [rax+1]\nmov [rbp+var_14], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\njmp short loc_14AC\nloc_1473:\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_14AC:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_2C]\njge loc_155C\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_30]\njge loc_155C\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_44]\njl loc_133A\njmp loc_155C\nloc_14D5:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_14]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njg short loc_1523\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rdx\nmov eax, [rax]\njmp short loc_153F\nloc_1523:\nmov eax, [rbp+var_14]\nlea edx, [rax+1]\nmov [rbp+var_14], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov eax, [rax]\nloc_153F:\nmov edx, [rbp+var_C]\nlea ecx, [rdx+1]\nmov [rbp+var_C], ecx\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov [rdx], eax\nloc_155C:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_2C]\njge loc_1600\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_30]\njl loc_14D5\njmp loc_1600\nloc_1579:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njg short loc_15C7\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rdx\nmov eax, [rax]\njmp short loc_15E3\nloc_15C7:\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nadd rax, rdx\nmov eax, [rax]\nloc_15E3:\nmov edx, [rbp+var_C]\nlea ecx, [rdx+1]\nmov [rbp+var_C], ecx\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov [rdx], eax\nloc_1600:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_2C]\njge loc_16A4\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_44]\njl loc_1579\njmp loc_16A4\nloc_161D:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njg short loc_166B\nmov eax, [rbp+var_14]\nlea edx, [rax+1]\nmov [rbp+var_14], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov eax, [rax]\njmp short loc_1687\nloc_166B:\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nadd rax, rdx\nmov eax, [rax]\nloc_1687:\nmov edx, [rbp+var_C]\nlea ecx, [rdx+1]\nmov [rbp+var_C], ecx\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov [rdx], eax\nloc_16A4:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_30]\njge short loc_16F3\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_44]\njl loc_161D\njmp short loc_16F3\nloc_16BA:\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_16F3:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_2C]\njl short loc_16BA\njmp short loc_1736\nloc_16FD:\nmov eax, [rbp+var_14]\nlea edx, [rax+1]\nmov [rbp+var_14], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_1736:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_30]\njl short loc_16FD\njmp short loc_1779\nloc_1740:\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_1779:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_44]\njl short loc_1740\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(char *a1, int a2, char *a3, int a4, char *a5, int a6, int *a7)\n{\n int v7; // eax\n char *v8; // rcx\n int v9; // eax\n int v10; // eax\n char *v11; // rcx\n int v12; // eax\n int v13; // eax\n char *v14; // rcx\n int v15; // eax\n int v16; // eax\n int v17; // eax\n int v18; // eax\n int v19; // edx\n int v20; // eax\n int v21; // eax\n int v22; // eax\n int v23; // edx\n int v24; // eax\n int v25; // eax\n int v26; // eax\n int v27; // edx\n int v28; // eax\n char *v29; // rcx\n int v30; // eax\n int v31; // eax\n char *v32; // rcx\n int v33; // eax\n int v34; // eax\n char *v35; // rcx\n int v36; // eax\n int v42; // [rsp+38h] [rbp-18h]\n int v43; // [rsp+3Ch] [rbp-14h]\n int v44; // [rsp+40h] [rbp-10h]\n int v45; // [rsp+44h] [rbp-Ch]\n _DWORD *v46; // [rsp+48h] [rbp-8h]\n\n qsort(a1, a2, 4uLL, compare);\n qsort(a3, a4, 4uLL, compare);\n qsort(a5, a6, 4uLL, compare);\n *a7 = a6 + a4 + a2;\n v46 = malloc(4LL * *a7);\n if ( !v46 )\n {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v42 = 0;\n v43 = 0;\n v44 = 0;\n v45 = 0;\n while ( v42 < a2 && v43 < a4 && v44 < a6 )\n {\n if ( *(_DWORD *)&a1[4 * v42] > *(_DWORD *)&a3[4 * v43] || *(_DWORD *)&a1[4 * v42] > *(_DWORD *)&a5[4 * v44] )\n {\n if ( *(_DWORD *)&a3[4 * v43] > *(_DWORD *)&a1[4 * v42] || *(_DWORD *)&a3[4 * v43] > *(_DWORD *)&a5[4 * v44] )\n {\n v13 = v44++;\n v14 = &a5[4 * v13];\n v15 = v45++;\n v46[v15] = *(_DWORD *)v14;\n }\n else\n {\n v10 = v43++;\n v11 = &a3[4 * v10];\n v12 = v45++;\n v46[v12] = *(_DWORD *)v11;\n }\n }\n else\n {\n v7 = v42++;\n v8 = &a1[4 * v7];\n v9 = v45++;\n v46[v9] = *(_DWORD *)v8;\n }\n }\n while ( v42 < a2 && v43 < a4 )\n {\n if ( *(_DWORD *)&a1[4 * v42] > *(_DWORD *)&a3[4 * v43] )\n {\n v18 = v43++;\n v17 = *(_DWORD *)&a3[4 * v18];\n }\n else\n {\n v16 = v42++;\n v17 = *(_DWORD *)&a1[4 * v16];\n }\n v19 = v45++;\n v46[v19] = v17;\n }\n while ( v42 < a2 && v44 < a6 )\n {\n if ( *(_DWORD *)&a1[4 * v42] > *(_DWORD *)&a5[4 * v44] )\n {\n v22 = v44++;\n v21 = *(_DWORD *)&a5[4 * v22];\n }\n else\n {\n v20 = v42++;\n v21 = *(_DWORD *)&a1[4 * v20];\n }\n v23 = v45++;\n v46[v23] = v21;\n }\n while ( v43 < a4 && v44 < a6 )\n {\n if ( *(_DWORD *)&a3[4 * v43] > *(_DWORD *)&a5[4 * v44] )\n {\n v26 = v44++;\n v25 = *(_DWORD *)&a5[4 * v26];\n }\n else\n {\n v24 = v43++;\n v25 = *(_DWORD *)&a3[4 * v24];\n }\n v27 = v45++;\n v46[v27] = v25;\n }\n while ( v42 < a2 )\n {\n v28 = v42++;\n v29 = &a1[4 * v28];\n v30 = v45++;\n v46[v30] = *(_DWORD *)v29;\n }\n while ( v43 < a4 )\n {\n v31 = v43++;\n v32 = &a3[4 * v31];\n v33 = v45++;\n v46[v33] = *(_DWORD *)v32;\n }\n while ( v44 < a6 )\n {\n v34 = v44++;\n v35 = &a5[4 * v34];\n v36 = v45++;\n v46[v36] = *(_DWORD *)v35;\n }\n return v46;\n}", + "ida_strip_asm": "sub_1249:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+base], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmov [rbp+var_30], ecx\nmov [rbp+var_40], r8\nmov [rbp+var_44], r9d\nmov eax, [rbp+var_2C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 4; size\nmov rdi, rax; base\ncall _qsort\nmov eax, [rbp+var_30]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+var_38]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 4; size\nmov rdi, rax; base\ncall _qsort\nmov eax, [rbp+var_44]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+var_40]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 4; size\nmov rdi, rax; base\ncall _qsort\nmov edx, [rbp+var_2C]\nmov eax, [rbp+var_30]\nadd edx, eax\nmov eax, [rbp+var_44]\nadd edx, eax\nmov rax, [rbp+arg_0]\nmov [rax], edx\nmov rax, [rbp+arg_0]\nmov eax, [rax]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\ncmp [rbp+var_8], 0\njnz short loc_1319\nlea rax, s; \"Failed to allocate memory\"\nmov rdi, rax; s\ncall _perror\nmov edi, 1; status\ncall _exit\nloc_1319:\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp loc_14AC\nloc_133A:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_14]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njg short loc_13D8\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njg short loc_13D8\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\njmp loc_14AC\nloc_13D8:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_18]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njg short loc_1473\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njg short loc_1473\nmov eax, [rbp+var_14]\nlea edx, [rax+1]\nmov [rbp+var_14], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\njmp short loc_14AC\nloc_1473:\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_14AC:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_2C]\njge loc_155C\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_30]\njge loc_155C\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_44]\njl loc_133A\njmp loc_155C\nloc_14D5:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_14]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njg short loc_1523\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rdx\nmov eax, [rax]\njmp short loc_153F\nloc_1523:\nmov eax, [rbp+var_14]\nlea edx, [rax+1]\nmov [rbp+var_14], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov eax, [rax]\nloc_153F:\nmov edx, [rbp+var_C]\nlea ecx, [rdx+1]\nmov [rbp+var_C], ecx\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov [rdx], eax\nloc_155C:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_2C]\njge loc_1600\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_30]\njl loc_14D5\njmp loc_1600\nloc_1579:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njg short loc_15C7\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rdx\nmov eax, [rax]\njmp short loc_15E3\nloc_15C7:\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nadd rax, rdx\nmov eax, [rax]\nloc_15E3:\nmov edx, [rbp+var_C]\nlea ecx, [rdx+1]\nmov [rbp+var_C], ecx\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov [rdx], eax\nloc_1600:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_2C]\njge loc_16A4\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_44]\njl loc_1579\njmp loc_16A4\nloc_161D:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njg short loc_166B\nmov eax, [rbp+var_14]\nlea edx, [rax+1]\nmov [rbp+var_14], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov eax, [rax]\njmp short loc_1687\nloc_166B:\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nadd rax, rdx\nmov eax, [rax]\nloc_1687:\nmov edx, [rbp+var_C]\nlea ecx, [rdx+1]\nmov [rbp+var_C], ecx\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov [rdx], eax\nloc_16A4:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_30]\njge short loc_16F3\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_44]\njl loc_161D\njmp short loc_16F3\nloc_16BA:\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_16F3:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_2C]\njl short loc_16BA\njmp short loc_1736\nloc_16FD:\nmov eax, [rbp+var_14]\nlea edx, [rax+1]\nmov [rbp+var_14], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_1736:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_30]\njl short loc_16FD\njmp short loc_1779\nloc_1740:\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_1779:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_44]\njl short loc_1740\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1249(char *a1, int a2, char *a3, int a4, char *a5, int a6, int *a7)\n{\n int v7; // eax\n char *v8; // rcx\n int v9; // eax\n int v10; // eax\n char *v11; // rcx\n int v12; // eax\n int v13; // eax\n char *v14; // rcx\n int v15; // eax\n int v16; // eax\n int v17; // eax\n int v18; // eax\n int v19; // edx\n int v20; // eax\n int v21; // eax\n int v22; // eax\n int v23; // edx\n int v24; // eax\n int v25; // eax\n int v26; // eax\n int v27; // edx\n int v28; // eax\n char *v29; // rcx\n int v30; // eax\n int v31; // eax\n char *v32; // rcx\n int v33; // eax\n int v34; // eax\n char *v35; // rcx\n int v36; // eax\n int v42; // [rsp+38h] [rbp-18h]\n int v43; // [rsp+3Ch] [rbp-14h]\n int v44; // [rsp+40h] [rbp-10h]\n int v45; // [rsp+44h] [rbp-Ch]\n _DWORD *v46; // [rsp+48h] [rbp-8h]\n\n qsort(a1, a2, 4uLL, compar);\n qsort(a3, a4, 4uLL, compar);\n qsort(a5, a6, 4uLL, compar);\n *a7 = a6 + a4 + a2;\n v46 = malloc(4LL * *a7);\n if ( !v46 )\n {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v42 = 0;\n v43 = 0;\n v44 = 0;\n v45 = 0;\n while ( v42 < a2 && v43 < a4 && v44 < a6 )\n {\n if ( *(_DWORD *)&a1[4 * v42] > *(_DWORD *)&a3[4 * v43] || *(_DWORD *)&a1[4 * v42] > *(_DWORD *)&a5[4 * v44] )\n {\n if ( *(_DWORD *)&a3[4 * v43] > *(_DWORD *)&a1[4 * v42] || *(_DWORD *)&a3[4 * v43] > *(_DWORD *)&a5[4 * v44] )\n {\n v13 = v44++;\n v14 = &a5[4 * v13];\n v15 = v45++;\n v46[v15] = *(_DWORD *)v14;\n }\n else\n {\n v10 = v43++;\n v11 = &a3[4 * v10];\n v12 = v45++;\n v46[v12] = *(_DWORD *)v11;\n }\n }\n else\n {\n v7 = v42++;\n v8 = &a1[4 * v7];\n v9 = v45++;\n v46[v9] = *(_DWORD *)v8;\n }\n }\n while ( v42 < a2 && v43 < a4 )\n {\n if ( *(_DWORD *)&a1[4 * v42] > *(_DWORD *)&a3[4 * v43] )\n {\n v18 = v43++;\n v17 = *(_DWORD *)&a3[4 * v18];\n }\n else\n {\n v16 = v42++;\n v17 = *(_DWORD *)&a1[4 * v16];\n }\n v19 = v45++;\n v46[v19] = v17;\n }\n while ( v42 < a2 && v44 < a6 )\n {\n if ( *(_DWORD *)&a1[4 * v42] > *(_DWORD *)&a5[4 * v44] )\n {\n v22 = v44++;\n v21 = *(_DWORD *)&a5[4 * v22];\n }\n else\n {\n v20 = v42++;\n v21 = *(_DWORD *)&a1[4 * v20];\n }\n v23 = v45++;\n v46[v23] = v21;\n }\n while ( v43 < a4 && v44 < a6 )\n {\n if ( *(_DWORD *)&a3[4 * v43] > *(_DWORD *)&a5[4 * v44] )\n {\n v26 = v44++;\n v25 = *(_DWORD *)&a5[4 * v26];\n }\n else\n {\n v24 = v43++;\n v25 = *(_DWORD *)&a3[4 * v24];\n }\n v27 = v45++;\n v46[v27] = v25;\n }\n while ( v42 < a2 )\n {\n v28 = v42++;\n v29 = &a1[4 * v28];\n v30 = v45++;\n v46[v30] = *(_DWORD *)v29;\n }\n while ( v43 < a4 )\n {\n v31 = v43++;\n v32 = &a3[4 * v31];\n v33 = v45++;\n v46[v33] = *(_DWORD *)v32;\n }\n while ( v44 < a6 )\n {\n v34 = v44++;\n v35 = &a5[4 * v34];\n v36 = v45++;\n v46[v36] = *(_DWORD *)v35;\n }\n return v46;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1249(char *a1, int a2, char *a3, int a4, char *a5, int a6,\n int *a7) {\n int v7;\n char *v8;\n int v9;\n int v10;\n char *v11;\n int v12;\n int v13;\n char *v14;\n int v15;\n int v16;\n int v17;\n int v18;\n int v19;\n int v20;\n int v21;\n int v22;\n int v23;\n int v24;\n int v25;\n int v26;\n int v27;\n int v28;\n char *v29;\n int v30;\n int v31;\n char *v32;\n int v33;\n int v34;\n char *v35;\n int v36;\n int v42;\n int v43;\n int v44;\n int v45;\n uint32_t *v46;\n qsort(a1, a2, 4uLL, compar);\n qsort(a3, a4, 4uLL, compar);\n qsort(a5, a6, 4uLL, compar);\n *a7 = a6 + a4 + a2;\n v46 = malloc(4LL * *a7);\n if (!v46) {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v42 = 0;\n v43 = 0;\n v44 = 0;\n v45 = 0;\n while (v42 < a2 && v43 < a4 && v44 < a6) {\n if (*(uint32_t *)&a1[4 * v42] > *(uint32_t *)&a3[4 * v43] ||\n *(uint32_t *)&a1[4 * v42] > *(uint32_t *)&a5[4 * v44]) {\n if (*(uint32_t *)&a3[4 * v43] > *(uint32_t *)&a1[4 * v42] ||\n *(uint32_t *)&a3[4 * v43] > *(uint32_t *)&a5[4 * v44]) {\n v13 = v44++;\n v14 = &a5[4 * v13];\n v15 = v45++;\n v46[v15] = *(uint32_t *)v14;\n } else {\n v10 = v43++;\n v11 = &a3[4 * v10];\n v12 = v45++;\n v46[v12] = *(uint32_t *)v11;\n }\n } else {\n v7 = v42++;\n v8 = &a1[4 * v7];\n v9 = v45++;\n v46[v9] = *(uint32_t *)v8;\n }\n }\n while (v42 < a2 && v43 < a4) {\n if (*(uint32_t *)&a1[4 * v42] > *(uint32_t *)&a3[4 * v43]) {\n v18 = v43++;\n v17 = *(uint32_t *)&a3[4 * v18];\n } else {\n v16 = v42++;\n v17 = *(uint32_t *)&a1[4 * v16];\n }\n v19 = v45++;\n v46[v19] = v17;\n }\n while (v42 < a2 && v44 < a6) {\n if (*(uint32_t *)&a1[4 * v42] > *(uint32_t *)&a5[4 * v44]) {\n v22 = v44++;\n v21 = *(uint32_t *)&a5[4 * v22];\n } else {\n v20 = v42++;\n v21 = *(uint32_t *)&a1[4 * v20];\n }\n v23 = v45++;\n v46[v23] = v21;\n }\n while (v43 < a4 && v44 < a6) {\n if (*(uint32_t *)&a3[4 * v43] > *(uint32_t *)&a5[4 * v44]) {\n v26 = v44++;\n v25 = *(uint32_t *)&a5[4 * v26];\n } else {\n v24 = v43++;\n v25 = *(uint32_t *)&a3[4 * v24];\n }\n v27 = v45++;\n v46[v27] = v25;\n }\n while (v42 < a2) {\n v28 = v42++;\n v29 = &a1[4 * v28];\n v30 = v45++;\n v46[v30] = *(uint32_t *)v29;\n }\n while (v43 < a4) {\n v31 = v43++;\n v32 = &a3[4 * v31];\n v33 = v45++;\n v46[v33] = *(uint32_t *)v32;\n }\n while (v44 < a6) {\n v34 = v44++;\n v35 = &a5[4 * v34];\n v36 = v45++;\n v46[v36] = *(uint32_t *)v35;\n }\n return v46;\n}", + "ida_pseudo_norm": "uint32_t *func0(char *a1, int a2, char *a3, int a4, char *a5, int a6, int *a7) {\n int v7;\n char *v8;\n int v9;\n int v10;\n char *v11;\n int v12;\n int v13;\n char *v14;\n int v15;\n int v16;\n int v17;\n int v18;\n int v19;\n int v20;\n int v21;\n int v22;\n int v23;\n int v24;\n int v25;\n int v26;\n int v27;\n int v28;\n char *v29;\n int v30;\n int v31;\n char *v32;\n int v33;\n int v34;\n char *v35;\n int v36;\n int v42;\n int v43;\n int v44;\n int v45;\n uint32_t *v46;\n qsort(a1, a2, 4uLL, compare);\n qsort(a3, a4, 4uLL, compare);\n qsort(a5, a6, 4uLL, compare);\n *a7 = a6 + a4 + a2;\n v46 = malloc(4LL * *a7);\n if (!v46) {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v42 = 0;\n v43 = 0;\n v44 = 0;\n v45 = 0;\n while (v42 < a2 && v43 < a4 && v44 < a6) {\n if (*(uint32_t *)&a1[4 * v42] > *(uint32_t *)&a3[4 * v43] ||\n *(uint32_t *)&a1[4 * v42] > *(uint32_t *)&a5[4 * v44]) {\n if (*(uint32_t *)&a3[4 * v43] > *(uint32_t *)&a1[4 * v42] ||\n *(uint32_t *)&a3[4 * v43] > *(uint32_t *)&a5[4 * v44]) {\n v13 = v44++;\n v14 = &a5[4 * v13];\n v15 = v45++;\n v46[v15] = *(uint32_t *)v14;\n } else {\n v10 = v43++;\n v11 = &a3[4 * v10];\n v12 = v45++;\n v46[v12] = *(uint32_t *)v11;\n }\n } else {\n v7 = v42++;\n v8 = &a1[4 * v7];\n v9 = v45++;\n v46[v9] = *(uint32_t *)v8;\n }\n }\n while (v42 < a2 && v43 < a4) {\n if (*(uint32_t *)&a1[4 * v42] > *(uint32_t *)&a3[4 * v43]) {\n v18 = v43++;\n v17 = *(uint32_t *)&a3[4 * v18];\n } else {\n v16 = v42++;\n v17 = *(uint32_t *)&a1[4 * v16];\n }\n v19 = v45++;\n v46[v19] = v17;\n }\n while (v42 < a2 && v44 < a6) {\n if (*(uint32_t *)&a1[4 * v42] > *(uint32_t *)&a5[4 * v44]) {\n v22 = v44++;\n v21 = *(uint32_t *)&a5[4 * v22];\n } else {\n v20 = v42++;\n v21 = *(uint32_t *)&a1[4 * v20];\n }\n v23 = v45++;\n v46[v23] = v21;\n }\n while (v43 < a4 && v44 < a6) {\n if (*(uint32_t *)&a3[4 * v43] > *(uint32_t *)&a5[4 * v44]) {\n v26 = v44++;\n v25 = *(uint32_t *)&a5[4 * v26];\n } else {\n v24 = v43++;\n v25 = *(uint32_t *)&a3[4 * v24];\n }\n v27 = v45++;\n v46[v27] = v25;\n }\n while (v42 < a2) {\n v28 = v42++;\n v29 = &a1[4 * v28];\n v30 = v45++;\n v46[v30] = *(uint32_t *)v29;\n }\n while (v43 < a4) {\n v31 = v43++;\n v32 = &a3[4 * v31];\n v33 = v45++;\n v46[v33] = *(uint32_t *)v32;\n }\n while (v44 < a6) {\n v34 = v44++;\n v35 = &a5[4 * v34];\n v36 = v45++;\n v46[v36] = *(uint32_t *)v35;\n }\n return v46;\n}" + }, + { + "index": 108, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n// Compare function for qsort\n\nint compare(const void *a, const void *b) {\n\n int int_a = *(const int*) a;\n\n int int_b = *(const int*) b;\n\n return (int_a > int_b) - (int_a < int_b);\n\n}\n\n\n\n// Function to merge three sorted lists\n\n", + "func": "int *func0(int num1[], int size1, int num2[], int size2, int num3[], int size3,\n int *result_size) {\n qsort(num1, size1, sizeof(int), compare);\n qsort(num2, size2, sizeof(int), compare);\n qsort(num3, size3, sizeof(int), compare);\n *result_size = size1 + size2 + size3;\n int *result = malloc(*result_size * sizeof(int));\n if (!result) {\n perror(\"Failed to allocate memory\");\n exit(EXIT_FAILURE);\n }\n int i = 0, j = 0, k = 0, l = 0;\n while (i < size1 && j < size2 && k < size3) {\n if (num1[i] <= num2[j] && num1[i] <= num3[k]) {\n result[l++] = num1[i++];\n } else if (num2[j] <= num1[i] && num2[j] <= num3[k]) {\n result[l++] = num2[j++];\n } else {\n result[l++] = num3[k++];\n }\n }\n while (i < size1 && j < size2) {\n result[l++] = (num1[i] <= num2[j]) ? num1[i++] : num2[j++];\n }\n while (i < size1 && k < size3) {\n result[l++] = (num1[i] <= num3[k]) ? num1[i++] : num3[k++];\n }\n while (j < size2 && k < size3) {\n result[l++] = (num2[j] <= num3[k]) ? num2[j++] : num3[k++];\n }\n while (i < size1) {\n result[l++] = num1[i++];\n }\n while (j < size2) {\n result[l++] = num2[j++];\n }\n while (k < size3) {\n result[l++] = num3[k++];\n }\n return result;\n}", + "test": "int main() {\n\n // First test case\n\n int num1_1[] = {25, 24, 15, 4, 5, 29, 110};\n\n int size1_1 = sizeof(num1_1) / sizeof(num1_1[0]);\n\n int num2_1[] = {19, 20, 11, 56, 25, 233, 154};\n\n int size2_1 = sizeof(num2_1) / sizeof(num2_1[0]);\n\n int num3_1[] = {24, 26, 54, 48};\n\n int size3_1 = sizeof(num3_1) / sizeof(num3_1[0]);\n\n int expected1[] = {4, 5, 11, 15, 19, 20, 24, 24, 25, 25, 26, 29, 48, 54, 56, 110, 154, 233};\n\n int expected_size1 = sizeof(expected1) / sizeof(expected1[0]);\n\n int result_size1;\n\n int *result1 = func0(num1_1, size1_1, num2_1, size2_1, num3_1, size3_1, &result_size1);\n\n assert(result_size1 == expected_size1);\n\n for(int i = 0; i < expected_size1; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n free(result1);\n\n\n\n // Second test case\n\n int num1_2[] = {1, 3, 5, 6, 8, 9};\n\n int size1_2 = sizeof(num1_2) / sizeof(num1_2[0]);\n\n int num2_2[] = {2, 5, 7, 11};\n\n int size2_2 = sizeof(num2_2) / sizeof(num2_2[0]);\n\n int num3_2[] = {1, 4, 7, 8, 12};\n\n int size3_2 = sizeof(num3_2) / sizeof(num3_2[0]);\n\n int expected2[] = {1, 1, 2, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 11, 12};\n\n int expected_size2 = sizeof(expected2) / sizeof(expected2[0]);\n\n int result_size2;\n\n int *result2 = func0(num1_2, size1_2, num2_2, size2_2, num3_2, size3_2, &result_size2);\n\n assert(result_size2 == expected_size2);\n\n for(int i = 0; i < expected_size2; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n free(result2);\n\n\n\n // Third test case\n\n int num1_3[] = {18, 14, 10, 9, 8, 7, 9, 3, 2, 4, 1};\n\n int size1_3 = sizeof(num1_3) / sizeof(num1_3[0]);\n\n int num2_3[] = {25, 35, 22, 85, 14, 65, 75, 25, 58};\n\n int size2_3 = sizeof(num2_3) / sizeof(num2_3[0]);\n\n int num3_3[] = {12, 74, 9, 50, 61, 41};\n\n int size3_3 = sizeof(num3_3) / sizeof(num3_3[0]);\n\n int expected3[] = {1, 2, 3, 4, 7, 8, 9, 9, 9, 10, 12, 14, 14, 18, 22, 25, 25, 35, 41, 50, 58, 61, 65, 74, 75, 85};\n\n int expected_size3 = sizeof(expected3) / sizeof(expected3[0]);\n\n int result_size3;\n\n int *result3 = func0(num1_3, size1_3, num2_3, size2_3, num3_3, size3_3, &result_size3);\n\n assert(result_size3 == expected_size3);\n\n for(int i = 0; i < expected_size3; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%r15\nmov %esi,%ebx\nmov %rdx,%r14\nmov %ecx,%ebp\nmov %r8,%r12\nmov %r9d,%r13d\nmovslq %esi,%rsi\nlea -0x45(%rip),%rcx\nmov $0x4,%edx\ncallq 10c0 \nmovslq %ebp,%rsi\nlea -0x59(%rip),%rcx\nmov $0x4,%edx\nmov %r14,%rdi\ncallq 10c0 \nmovslq %r13d,%rsi\nlea -0x70(%rip),%rcx\nmov $0x4,%edx\nmov %r12,%rdi\ncallq 10c0 \nlea (%rbx,%rbp,1),%edi\nadd %r13d,%edi\nmov 0x40(%rsp),%rax\nmov %edi,(%rax)\nmovslq %edi,%rdi\nshl $0x2,%rdi\ncallq 10f0 \ntest %rax,%rax\nje 1301 \ntest %ebp,%ebp\nsetg %cl\ntest %r13d,%r13d\nsetg %dl\ntest %dl,%cl\nje 12d0 \ntest %ebx,%ebx\njle 12d0 \nmov $0x0,%esi\nmov $0x0,%edx\nmov $0x0,%edi\nmov $0x0,%ecx\njmpq 1359 \nmov $0x0,%r8d\nmov $0x0,%edx\nmov $0x0,%edi\nmov $0x0,%ecx\ncmp %ecx,%ebx\njle 13b4 \ncmp %edi,%ebp\njle 13b4 \nadd $0x1,%r8d\nmovslq %r8d,%rsi\njmpq 139c \nlea 0xcfc(%rip),%rdi\ncallq 1100 \nmov $0x1,%edi\ncallq 1110 \nmovslq %edx,%r8\ncmp (%r12,%r8,4),%r10d\njg 132d \nadd $0x1,%edi\nlea 0x1(%rsi),%r8d\nmov %r10d,(%rax,%rsi,4)\njmp 133f \nlea 0x1(%rsi),%r8d\nmovslq %edx,%r9\nmov (%r12,%r9,4),%r9d\nmov %r9d,(%rax,%rsi,4)\nlea 0x1(%rdx),%edx\nadd $0x1,%rsi\ncmp %ecx,%ebx\nsetg %r10b\ncmp %ebp,%edi\nsetl %r9b\ntest %r9b,%r10b\nje 12e5 \ncmp %r13d,%edx\njge 12e5 \nmovslq %ecx,%r8\nmov (%r15,%r8,4),%r9d\nmovslq %edi,%r8\nmov (%r14,%r8,4),%r10d\ncmp %r10d,%r9d\njg 1317 \nmovslq %edx,%r8\ncmp (%r12,%r8,4),%r9d\njg 132d \nadd $0x1,%ecx\nlea 0x1(%rsi),%r8d\nmov %r9d,(%rax,%rsi,4)\njmp 133f \nadd $0x1,%edi\nmov %r8d,%r9d\nmov %esi,%r8d\nmov %r9d,-0x4(%rax,%rsi,4)\nadd $0x1,%rsi\ncmp %ebx,%ecx\njge 13b4 \ncmp %ebp,%edi\njge 13b4 \nmovslq %ecx,%r8\nmov (%r15,%r8,4),%r9d\nmovslq %edi,%r8\nmov (%r14,%r8,4),%r8d\ncmp %r8d,%r9d\njg 1382 \nadd $0x1,%ecx\njmp 1388 \ncmp %ecx,%ebx\njle 13f9 \ncmp %edx,%r13d\njle 13f9 \nadd $0x1,%r8d\nmovslq %r8d,%rsi\njmp 13e1 \nadd $0x1,%edx\nmov %r8d,%r9d\nmov %esi,%r8d\nmov %r9d,-0x4(%rax,%rsi,4)\nadd $0x1,%rsi\ncmp %ebx,%ecx\njge 13f9 \ncmp %r13d,%edx\njge 13f9 \nmovslq %ecx,%r8\nmov (%r15,%r8,4),%r9d\nmovslq %edx,%r8\nmov (%r12,%r8,4),%r8d\ncmp %r8d,%r9d\njg 13c6 \nadd $0x1,%ecx\njmp 13cc \ncmp %edi,%ebp\njle 143e \ncmp %edx,%r13d\njle 143e \nadd $0x1,%r8d\nmovslq %r8d,%rsi\njmp 1426 \nadd $0x1,%edx\nmov %r8d,%r9d\nmov %esi,%r8d\nmov %r9d,-0x4(%rax,%rsi,4)\nadd $0x1,%rsi\ncmp %ebp,%edi\njge 143e \ncmp %r13d,%edx\njge 143e \nmovslq %edi,%r8\nmov (%r14,%r8,4),%r9d\nmovslq %edx,%r8\nmov (%r12,%r8,4),%r8d\ncmp %r8d,%r9d\njg 140b \nadd $0x1,%edi\njmp 1411 \ncmp %ecx,%ebx\njle 1464 \nmovslq %ecx,%rsi\nmovslq %r8d,%r9\nsub %rsi,%r9\nlea (%rax,%r9,4),%r10\nmov (%r15,%rsi,4),%r9d\nmov %r9d,(%r10,%rsi,4)\nadd $0x1,%rsi\ncmp %esi,%ebx\njg 144f \nsub %ecx,%ebx\nadd %ebx,%r8d\ncmp %edi,%ebp\njle 148a \nmovslq %edi,%rcx\nmovslq %r8d,%rsi\nsub %rcx,%rsi\nlea (%rax,%rsi,4),%r9\nmov (%r14,%rcx,4),%esi\nmov %esi,(%r9,%rcx,4)\nadd $0x1,%rcx\ncmp %ecx,%ebp\njg 1475 \nsub %edi,%ebp\nadd %ebp,%r8d\ncmp %edx,%r13d\njle 14ac \nmovslq %edx,%rdx\nmovslq %r8d,%r8\nsub %rdx,%r8\nlea (%rax,%r8,4),%rsi\nmov (%r12,%rdx,4),%ecx\nmov %ecx,(%rsi,%rdx,4)\nadd $0x1,%rdx\ncmp %edx,%r13d\njg 149c \nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r15, rdi\nmov ebp, esi\nmov r14, rdx\nmov r12d, ecx\nmov r13, r8\nmov ebx, r9d\nmovsxd rsi, esi; nmemb\nlea rcx, compare; compar\nmov edx, 4; size\ncall _qsort\nmovsxd rsi, r12d; nmemb\nlea rcx, compare; compar\nmov edx, 4; size\nmov rdi, r14; base\ncall _qsort\nmovsxd rsi, ebx; nmemb\nlea rcx, compare; compar\nmov edx, 4; size\nmov rdi, r13; base\ncall _qsort\nlea edi, [rbp+r12+0]\nadd edi, ebx\nmov rax, [rsp+38h+arg_0]\nmov [rax], edi\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\ntest rax, rax\njz short loc_1306\nmov rdi, rax\ntest r12d, r12d\nsetnle dl\ntest ebx, ebx\nsetnle al\ntest dl, al\njz short loc_12D7\ntest ebp, ebp\njle short loc_12D7\nmov r9, rdi\nmov r8d, 1\nmov edx, 0\nmov esi, 0\nmov ecx, 0\njmp loc_1360\nloc_12D7:\nmov eax, 0\nmov edx, 0\nmov esi, 0\nmov ecx, 0\nloc_12EB:\ncmp ebp, ecx\njle loc_13BB\ncmp r12d, esi\njle loc_13BB\nadd eax, 1\ncdqe\njmp loc_13A3\nloc_1306:\nlea rdi, s; \"Failed to allocate memory\"\ncall _perror\nmov edi, 1; status\ncall _exit\nloc_131C:\nmovsxd rax, edx\ncmp r11d, [r13+rax*4+0]\njg short loc_1331\nadd esi, 1\nmov eax, r8d\nmov [r9], r11d\njmp short loc_1342\nloc_1331:\nmov eax, r8d\nmovsxd r10, edx\nmov r10d, [r13+r10*4+0]\nmov [r9], r10d\nlea edx, [rdx+1]\nloc_1342:\nadd r8d, 1\nadd r9, 4\ncmp ebp, ecx\nsetnle r11b\ncmp esi, r12d\nsetl r10b\ntest r11b, r10b\njz short loc_12EB\ncmp edx, ebx\njge short loc_12EB\nloc_1360:\nmovsxd rax, ecx\nmov r10d, [r15+rax*4]\nmovsxd rax, esi\nmov r11d, [r14+rax*4]\ncmp r10d, r11d\njg short loc_131C\nmovsxd rax, edx\ncmp r10d, [r13+rax*4+0]\njg short loc_1331\nadd ecx, 1\nmov eax, r8d\nmov [r9], r10d\njmp short loc_1342\nloc_1388:\nadd esi, 1\nmov r8d, r9d\nloc_138E:\nmov [rdi+rax*4-4], r8d\nlea r8, [rax+1]\ncmp ecx, ebp\njge short loc_13BB\ncmp esi, r12d\njge short loc_13BB\nmov rax, r8\nloc_13A3:\nmovsxd r8, ecx\nmov r8d, [r15+r8*4]\nmovsxd r9, esi\nmov r9d, [r14+r9*4]\ncmp r8d, r9d\njg short loc_1388\nadd ecx, 1\njmp short loc_138E\nloc_13BB:\ncmp ebp, ecx\njle short loc_13FD\ncmp ebx, edx\njle short loc_13FD\nadd eax, 1\ncdqe\njmp short loc_13E4\nloc_13CA:\nadd edx, 1\nmov r8d, r9d\nloc_13D0:\nmov [rdi+rax*4-4], r8d\nlea r8, [rax+1]\ncmp ecx, ebp\njge short loc_13FD\ncmp edx, ebx\njge short loc_13FD\nmov rax, r8\nloc_13E4:\nmovsxd r8, ecx\nmov r8d, [r15+r8*4]\nmovsxd r9, edx\nmov r9d, [r13+r9*4+0]\ncmp r8d, r9d\njg short loc_13CA\nadd ecx, 1\njmp short loc_13D0\nloc_13FD:\ncmp r12d, esi\njle short loc_1441\ncmp ebx, edx\njle short loc_1441\nadd eax, 1\ncdqe\njmp short loc_1428\nloc_140D:\nadd edx, 1\nmov r8d, r9d\nloc_1413:\nmov [rdi+rax*4-4], r8d\nlea r8, [rax+1]\ncmp esi, r12d\njge short loc_1441\ncmp edx, ebx\njge short loc_1441\nmov rax, r8\nloc_1428:\nmovsxd r8, esi\nmov r8d, [r14+r8*4]\nmovsxd r9, edx\nmov r9d, [r13+r9*4+0]\ncmp r8d, r9d\njg short loc_140D\nadd esi, 1\njmp short loc_1413\nloc_1441:\ncmp ebp, ecx\njle short loc_1474\nsub ebp, ecx\nmov r9d, ebp\nshl r9, 2\nmovsxd rcx, ecx\nlea r11, [r15+rcx*4]\nmovsxd rcx, eax\nlea r10, [rdi+rcx*4]\nmov ecx, 0\nloc_1461:\nmov r8d, [r11+rcx]\nmov [r10+rcx], r8d\nadd rcx, 4\ncmp rcx, r9\njnz short loc_1461\nadd eax, ebp\nloc_1474:\ncmp r12d, esi\njle short loc_14AA\nsub r12d, esi\nmov r8d, r12d\nshl r8, 2\nmovsxd rsi, esi\nlea r10, [r14+rsi*4]\nmovsxd rcx, eax\nlea r9, [rdi+rcx*4]\nmov ecx, 0\nloc_1496:\nmov esi, [r10+rcx]\nmov [r9+rcx], esi\nadd rcx, 4\ncmp rcx, r8\njnz short loc_1496\nadd eax, r12d\nloc_14AA:\ncmp ebx, edx\njle short loc_14D6\nsub ebx, edx\nshl rbx, 2\nmovsxd rdx, edx\nlea rsi, [r13+rdx*4+0]\ncdqe\nlea rcx, [rdi+rax*4]\nmov eax, 0\nloc_14C7:\nmov edx, [rsi+rax]\nmov [rcx+rax], edx\nadd rax, 4\ncmp rax, rbx\njnz short loc_14C7\nloc_14D6:\nmov rax, rdi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(char *a1, int a2, char *a3, int a4, char *a5, int a6, _DWORD *a7)\n{\n int v13; // edi\n _DWORD *v14; // rax\n _DWORD *v15; // rdi\n _DWORD *v16; // r9\n int v17; // r8d\n int v18; // edx\n int v19; // esi\n int v20; // ecx\n __int64 i; // rax\n int v22; // r10d\n int v23; // r11d\n int v24; // r8d\n int v25; // r9d\n int v26; // r8d\n int v27; // r9d\n int v28; // r8d\n int v29; // r9d\n int v30; // ebp\n char *v31; // r11\n __int64 v32; // rcx\n int v33; // r12d\n __int64 v34; // rcx\n __int64 v35; // rbx\n _DWORD *v36; // rcx\n unsigned __int64 v37; // rax\n\n qsort(a1, a2, 4uLL, compare);\n qsort(a3, a4, 4uLL, compare);\n qsort(a5, a6, 4uLL, compare);\n v13 = a6 + a2 + a4;\n *a7 = v13;\n v14 = malloc(4LL * v13);\n if ( !v14 )\n {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v15 = v14;\n if ( a6 > 0 && a4 > 0 && a2 > 0 )\n {\n v16 = v14;\n v17 = 1;\n v18 = 0;\n v19 = 0;\n v20 = 0;\n while ( 1 )\n {\n v22 = *(_DWORD *)&a1[4 * v20];\n v23 = *(_DWORD *)&a3[4 * v19];\n if ( v22 > v23 )\n break;\n if ( v22 > *(_DWORD *)&a5[4 * v18] )\n goto LABEL_12;\n ++v20;\n LODWORD(i) = v17;\n *v16 = v22;\nLABEL_13:\n ++v17;\n ++v16;\n if ( v19 >= a4 || a2 <= v20 || v18 >= a6 )\n goto LABEL_6;\n }\n if ( v23 <= *(_DWORD *)&a5[4 * v18] )\n {\n ++v19;\n LODWORD(i) = v17;\n *v16 = v23;\n goto LABEL_13;\n }\nLABEL_12:\n LODWORD(i) = v17;\n *v16 = *(_DWORD *)&a5[4 * v18++];\n goto LABEL_13;\n }\n LODWORD(i) = 0;\n v18 = 0;\n v19 = 0;\n v20 = 0;\nLABEL_6:\n if ( a2 > v20 && a4 > v19 )\n {\n for ( i = (int)i + 1; ; ++i )\n {\n v24 = *(_DWORD *)&a1[4 * v20];\n v25 = *(_DWORD *)&a3[4 * v19];\n if ( v24 > v25 )\n {\n ++v19;\n v24 = v25;\n }\n else\n {\n ++v20;\n }\n v15[i - 1] = v24;\n if ( v20 >= a2 || v19 >= a4 )\n break;\n }\n }\n if ( a2 > v20 && a6 > v18 )\n {\n for ( i = (int)i + 1; ; ++i )\n {\n v26 = *(_DWORD *)&a1[4 * v20];\n v27 = *(_DWORD *)&a5[4 * v18];\n if ( v26 > v27 )\n {\n ++v18;\n v26 = v27;\n }\n else\n {\n ++v20;\n }\n v15[i - 1] = v26;\n if ( v20 >= a2 || v18 >= a6 )\n break;\n }\n }\n if ( a4 > v19 && a6 > v18 )\n {\n for ( i = (int)i + 1; ; ++i )\n {\n v28 = *(_DWORD *)&a3[4 * v19];\n v29 = *(_DWORD *)&a5[4 * v18];\n if ( v28 > v29 )\n {\n ++v18;\n v28 = v29;\n }\n else\n {\n ++v19;\n }\n v15[i - 1] = v28;\n if ( v19 >= a4 || v18 >= a6 )\n break;\n }\n }\n if ( a2 > v20 )\n {\n v30 = a2 - v20;\n v31 = &a1[4 * v20];\n v32 = 0LL;\n do\n {\n v15[(int)i + v32] = *(_DWORD *)&v31[v32 * 4];\n ++v32;\n }\n while ( v32 != v30 );\n LODWORD(i) = v30 + i;\n }\n if ( a4 > v19 )\n {\n v33 = a4 - v19;\n v34 = 0LL;\n do\n {\n v15[(int)i + v34] = *(_DWORD *)&a3[4 * v19 + v34 * 4];\n ++v34;\n }\n while ( v34 != v33 );\n LODWORD(i) = v33 + i;\n }\n if ( a6 > v18 )\n {\n v35 = 4LL * (unsigned int)(a6 - v18);\n v36 = &v15[(int)i];\n v37 = 0LL;\n do\n {\n v36[v37 / 4] = *(_DWORD *)&a5[4 * v18 + v37];\n v37 += 4LL;\n }\n while ( v37 != v35 );\n }\n return v15;\n}", + "ida_strip_asm": "sub_1220:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r15, rdi\nmov ebp, esi\nmov r14, rdx\nmov r12d, ecx\nmov r13, r8\nmov ebx, r9d\nmovsxd rsi, esi; nmemb\nlea rcx, compar; compar\nmov edx, 4; size\ncall _qsort\nmovsxd rsi, r12d; nmemb\nlea rcx, compar; compar\nmov edx, 4; size\nmov rdi, r14; base\ncall _qsort\nmovsxd rsi, ebx; nmemb\nlea rcx, compar; compar\nmov edx, 4; size\nmov rdi, r13; base\ncall _qsort\nlea edi, [rbp+r12+0]\nadd edi, ebx\nmov rax, [rsp+38h+arg_0]\nmov [rax], edi\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\ntest rax, rax\njz short loc_1306\nmov rdi, rax\ntest r12d, r12d\nsetnle dl\ntest ebx, ebx\nsetnle al\ntest dl, al\njz short loc_12D7\ntest ebp, ebp\njle short loc_12D7\nmov r9, rdi\nmov r8d, 1\nmov edx, 0\nmov esi, 0\nmov ecx, 0\njmp loc_1360\nloc_12D7:\nmov eax, 0\nmov edx, 0\nmov esi, 0\nmov ecx, 0\nloc_12EB:\ncmp ebp, ecx\njle loc_13BB\ncmp r12d, esi\njle loc_13BB\nadd eax, 1\ncdqe\njmp loc_13A3\nloc_1306:\nlea rdi, s; \"Failed to allocate memory\"\ncall _perror\nmov edi, 1; status\ncall _exit\nloc_131C:\nmovsxd rax, edx\ncmp r11d, [r13+rax*4+0]\njg short loc_1331\nadd esi, 1\nmov eax, r8d\nmov [r9], r11d\njmp short loc_1342\nloc_1331:\nmov eax, r8d\nmovsxd r10, edx\nmov r10d, [r13+r10*4+0]\nmov [r9], r10d\nlea edx, [rdx+1]\nloc_1342:\nadd r8d, 1\nadd r9, 4\ncmp ebp, ecx\nsetnle r11b\ncmp esi, r12d\nsetl r10b\ntest r11b, r10b\njz short loc_12EB\ncmp edx, ebx\njge short loc_12EB\nloc_1360:\nmovsxd rax, ecx\nmov r10d, [r15+rax*4]\nmovsxd rax, esi\nmov r11d, [r14+rax*4]\ncmp r10d, r11d\njg short loc_131C\nmovsxd rax, edx\ncmp r10d, [r13+rax*4+0]\njg short loc_1331\nadd ecx, 1\nmov eax, r8d\nmov [r9], r10d\njmp short loc_1342\nloc_1388:\nadd esi, 1\nmov r8d, r9d\nloc_138E:\nmov [rdi+rax*4-4], r8d\nlea r8, [rax+1]\ncmp ecx, ebp\njge short loc_13BB\ncmp esi, r12d\njge short loc_13BB\nmov rax, r8\nloc_13A3:\nmovsxd r8, ecx\nmov r8d, [r15+r8*4]\nmovsxd r9, esi\nmov r9d, [r14+r9*4]\ncmp r8d, r9d\njg short loc_1388\nadd ecx, 1\njmp short loc_138E\nloc_13BB:\ncmp ebp, ecx\njle short loc_13FD\ncmp ebx, edx\njle short loc_13FD\nadd eax, 1\ncdqe\njmp short loc_13E4\nloc_13CA:\nadd edx, 1\nmov r8d, r9d\nloc_13D0:\nmov [rdi+rax*4-4], r8d\nlea r8, [rax+1]\ncmp ecx, ebp\njge short loc_13FD\ncmp edx, ebx\njge short loc_13FD\nmov rax, r8\nloc_13E4:\nmovsxd r8, ecx\nmov r8d, [r15+r8*4]\nmovsxd r9, edx\nmov r9d, [r13+r9*4+0]\ncmp r8d, r9d\njg short loc_13CA\nadd ecx, 1\njmp short loc_13D0\nloc_13FD:\ncmp r12d, esi\njle short loc_1441\ncmp ebx, edx\njle short loc_1441\nadd eax, 1\ncdqe\njmp short loc_1428\nloc_140D:\nadd edx, 1\nmov r8d, r9d\nloc_1413:\nmov [rdi+rax*4-4], r8d\nlea r8, [rax+1]\ncmp esi, r12d\njge short loc_1441\ncmp edx, ebx\njge short loc_1441\nmov rax, r8\nloc_1428:\nmovsxd r8, esi\nmov r8d, [r14+r8*4]\nmovsxd r9, edx\nmov r9d, [r13+r9*4+0]\ncmp r8d, r9d\njg short loc_140D\nadd esi, 1\njmp short loc_1413\nloc_1441:\ncmp ebp, ecx\njle short loc_1474\nsub ebp, ecx\nmov r9d, ebp\nshl r9, 2\nmovsxd rcx, ecx\nlea r11, [r15+rcx*4]\nmovsxd rcx, eax\nlea r10, [rdi+rcx*4]\nmov ecx, 0\nloc_1461:\nmov r8d, [r11+rcx]\nmov [r10+rcx], r8d\nadd rcx, 4\ncmp rcx, r9\njnz short loc_1461\nadd eax, ebp\nloc_1474:\ncmp r12d, esi\njle short loc_14AA\nsub r12d, esi\nmov r8d, r12d\nshl r8, 2\nmovsxd rsi, esi\nlea r10, [r14+rsi*4]\nmovsxd rcx, eax\nlea r9, [rdi+rcx*4]\nmov ecx, 0\nloc_1496:\nmov esi, [r10+rcx]\nmov [r9+rcx], esi\nadd rcx, 4\ncmp rcx, r8\njnz short loc_1496\nadd eax, r12d\nloc_14AA:\ncmp ebx, edx\njle short loc_14D6\nsub ebx, edx\nshl rbx, 2\nmovsxd rdx, edx\nlea rsi, [r13+rdx*4+0]\ncdqe\nlea rcx, [rdi+rax*4]\nmov eax, 0\nloc_14C7:\nmov edx, [rsi+rax]\nmov [rcx+rax], edx\nadd rax, 4\ncmp rax, rbx\njnz short loc_14C7\nloc_14D6:\nmov rax, rdi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1220(char *a1, int a2, char *a3, int a4, char *a5, int a6, _DWORD *a7)\n{\n int v13; // edi\n _DWORD *v14; // rax\n _DWORD *v15; // rdi\n _DWORD *v16; // r9\n int v17; // r8d\n int v18; // edx\n int v19; // esi\n int v20; // ecx\n __int64 i; // rax\n int v22; // r10d\n int v23; // r11d\n int v24; // r8d\n int v25; // r9d\n int v26; // r8d\n int v27; // r9d\n int v28; // r8d\n int v29; // r9d\n int v30; // ebp\n char *v31; // r11\n __int64 v32; // rcx\n int v33; // r12d\n __int64 v34; // rcx\n __int64 v35; // rbx\n _DWORD *v36; // rcx\n unsigned __int64 v37; // rax\n\n qsort(a1, a2, 4uLL, compar);\n qsort(a3, a4, 4uLL, compar);\n qsort(a5, a6, 4uLL, compar);\n v13 = a6 + a2 + a4;\n *a7 = v13;\n v14 = malloc(4LL * v13);\n if ( !v14 )\n {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v15 = v14;\n if ( a6 > 0 && a4 > 0 && a2 > 0 )\n {\n v16 = v14;\n v17 = 1;\n v18 = 0;\n v19 = 0;\n v20 = 0;\n while ( 1 )\n {\n v22 = *(_DWORD *)&a1[4 * v20];\n v23 = *(_DWORD *)&a3[4 * v19];\n if ( v22 > v23 )\n break;\n if ( v22 > *(_DWORD *)&a5[4 * v18] )\n goto LABEL_12;\n ++v20;\n LODWORD(i) = v17;\n *v16 = v22;\nLABEL_13:\n ++v17;\n ++v16;\n if ( v19 >= a4 || a2 <= v20 || v18 >= a6 )\n goto LABEL_6;\n }\n if ( v23 <= *(_DWORD *)&a5[4 * v18] )\n {\n ++v19;\n LODWORD(i) = v17;\n *v16 = v23;\n goto LABEL_13;\n }\nLABEL_12:\n LODWORD(i) = v17;\n *v16 = *(_DWORD *)&a5[4 * v18++];\n goto LABEL_13;\n }\n LODWORD(i) = 0;\n v18 = 0;\n v19 = 0;\n v20 = 0;\nLABEL_6:\n if ( a2 > v20 && a4 > v19 )\n {\n for ( i = (int)i + 1; ; ++i )\n {\n v24 = *(_DWORD *)&a1[4 * v20];\n v25 = *(_DWORD *)&a3[4 * v19];\n if ( v24 > v25 )\n {\n ++v19;\n v24 = v25;\n }\n else\n {\n ++v20;\n }\n v15[i - 1] = v24;\n if ( v20 >= a2 || v19 >= a4 )\n break;\n }\n }\n if ( a2 > v20 && a6 > v18 )\n {\n for ( i = (int)i + 1; ; ++i )\n {\n v26 = *(_DWORD *)&a1[4 * v20];\n v27 = *(_DWORD *)&a5[4 * v18];\n if ( v26 > v27 )\n {\n ++v18;\n v26 = v27;\n }\n else\n {\n ++v20;\n }\n v15[i - 1] = v26;\n if ( v20 >= a2 || v18 >= a6 )\n break;\n }\n }\n if ( a4 > v19 && a6 > v18 )\n {\n for ( i = (int)i + 1; ; ++i )\n {\n v28 = *(_DWORD *)&a3[4 * v19];\n v29 = *(_DWORD *)&a5[4 * v18];\n if ( v28 > v29 )\n {\n ++v18;\n v28 = v29;\n }\n else\n {\n ++v19;\n }\n v15[i - 1] = v28;\n if ( v19 >= a4 || v18 >= a6 )\n break;\n }\n }\n if ( a2 > v20 )\n {\n v30 = a2 - v20;\n v31 = &a1[4 * v20];\n v32 = 0LL;\n do\n {\n v15[(int)i + v32] = *(_DWORD *)&v31[v32 * 4];\n ++v32;\n }\n while ( v32 != v30 );\n LODWORD(i) = v30 + i;\n }\n if ( a4 > v19 )\n {\n v33 = a4 - v19;\n v34 = 0LL;\n do\n {\n v15[(int)i + v34] = *(_DWORD *)&a3[4 * v19 + v34 * 4];\n ++v34;\n }\n while ( v34 != v33 );\n LODWORD(i) = v33 + i;\n }\n if ( a6 > v18 )\n {\n v35 = 4LL * (unsigned int)(a6 - v18);\n v36 = &v15[(int)i];\n v37 = 0LL;\n do\n {\n v36[v37 / 4] = *(_DWORD *)&a5[4 * v18 + v37];\n v37 += 4LL;\n }\n while ( v37 != v35 );\n }\n return v15;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1220(char *a1, int a2, char *a3, int a4, char *a5, int a6,\n uint32_t *a7) {\n int v13;\n uint32_t *v14;\n uint32_t *v15;\n uint32_t *v16;\n int v17;\n int v18;\n int v19;\n int v20;\n long long i;\n int v22;\n int v23;\n int v24;\n int v25;\n int v26;\n int v27;\n int v28;\n int v29;\n int v30;\n char *v31;\n long long v32;\n int v33;\n long long v34;\n long long v35;\n uint32_t *v36;\n unsigned long long v37;\n qsort(a1, a2, 4uLL, compar);\n qsort(a3, a4, 4uLL, compar);\n qsort(a5, a6, 4uLL, compar);\n v13 = a6 + a2 + a4;\n *a7 = v13;\n v14 = malloc(4LL * v13);\n if (!v14) {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v15 = v14;\n if (a6 > 0 && a4 > 0 && a2 > 0) {\n v16 = v14;\n v17 = 1;\n v18 = 0;\n v19 = 0;\n v20 = 0;\n while (1) {\n v22 = *(uint32_t *)&a1[4 * v20];\n v23 = *(uint32_t *)&a3[4 * v19];\n if (v22 > v23) break;\n if (v22 > *(uint32_t *)&a5[4 * v18]) goto LABEL_12;\n ++v20;\n LODWORD(i) = v17;\n *v16 = v22;\n LABEL_13:\n ++v17;\n ++v16;\n if (v19 >= a4 || a2 <= v20 || v18 >= a6) goto LABEL_6;\n }\n if (v23 <= *(uint32_t *)&a5[4 * v18]) {\n ++v19;\n LODWORD(i) = v17;\n *v16 = v23;\n goto LABEL_13;\n }\n LABEL_12:\n LODWORD(i) = v17;\n *v16 = *(uint32_t *)&a5[4 * v18++];\n goto LABEL_13;\n }\n LODWORD(i) = 0;\n v18 = 0;\n v19 = 0;\n v20 = 0;\nLABEL_6:\n if (a2 > v20 && a4 > v19) {\n for (i = (int)i + 1;; ++i) {\n v24 = *(uint32_t *)&a1[4 * v20];\n v25 = *(uint32_t *)&a3[4 * v19];\n if (v24 > v25) {\n ++v19;\n v24 = v25;\n } else {\n ++v20;\n }\n v15[i - 1] = v24;\n if (v20 >= a2 || v19 >= a4) break;\n }\n }\n if (a2 > v20 && a6 > v18) {\n for (i = (int)i + 1;; ++i) {\n v26 = *(uint32_t *)&a1[4 * v20];\n v27 = *(uint32_t *)&a5[4 * v18];\n if (v26 > v27) {\n ++v18;\n v26 = v27;\n } else {\n ++v20;\n }\n v15[i - 1] = v26;\n if (v20 >= a2 || v18 >= a6) break;\n }\n }\n if (a4 > v19 && a6 > v18) {\n for (i = (int)i + 1;; ++i) {\n v28 = *(uint32_t *)&a3[4 * v19];\n v29 = *(uint32_t *)&a5[4 * v18];\n if (v28 > v29) {\n ++v18;\n v28 = v29;\n } else {\n ++v19;\n }\n v15[i - 1] = v28;\n if (v19 >= a4 || v18 >= a6) break;\n }\n }\n if (a2 > v20) {\n v30 = a2 - v20;\n v31 = &a1[4 * v20];\n v32 = 0LL;\n do {\n v15[(int)i + v32] = *(uint32_t *)&v31[v32 * 4];\n ++v32;\n } while (v32 != v30);\n LODWORD(i) = v30 + i;\n }\n if (a4 > v19) {\n v33 = a4 - v19;\n v34 = 0LL;\n do {\n v15[(int)i + v34] = *(uint32_t *)&a3[4 * v19 + v34 * 4];\n ++v34;\n } while (v34 != v33);\n LODWORD(i) = v33 + i;\n }\n if (a6 > v18) {\n v35 = 4LL * (unsigned int)(a6 - v18);\n v36 = &v15[(int)i];\n v37 = 0LL;\n do {\n v36[v37 / 4] = *(uint32_t *)&a5[4 * v18 + v37];\n v37 += 4LL;\n } while (v37 != v35);\n }\n return v15;\n}", + "ida_pseudo_norm": "uint32_t *func0(char *a1, int a2, char *a3, int a4, char *a5, int a6,\n uint32_t *a7) {\n int v13;\n uint32_t *v14;\n uint32_t *v15;\n uint32_t *v16;\n int v17;\n int v18;\n int v19;\n int v20;\n long long i;\n int v22;\n int v23;\n int v24;\n int v25;\n int v26;\n int v27;\n int v28;\n int v29;\n int v30;\n char *v31;\n long long v32;\n int v33;\n long long v34;\n long long v35;\n uint32_t *v36;\n unsigned long long v37;\n qsort(a1, a2, 4uLL, compare);\n qsort(a3, a4, 4uLL, compare);\n qsort(a5, a6, 4uLL, compare);\n v13 = a6 + a2 + a4;\n *a7 = v13;\n v14 = malloc(4LL * v13);\n if (!v14) {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v15 = v14;\n if (a6 > 0 && a4 > 0 && a2 > 0) {\n v16 = v14;\n v17 = 1;\n v18 = 0;\n v19 = 0;\n v20 = 0;\n while (1) {\n v22 = *(uint32_t *)&a1[4 * v20];\n v23 = *(uint32_t *)&a3[4 * v19];\n if (v22 > v23) break;\n if (v22 > *(uint32_t *)&a5[4 * v18]) goto LABEL_12;\n ++v20;\n LODWORD(i) = v17;\n *v16 = v22;\n LABEL_13:\n ++v17;\n ++v16;\n if (v19 >= a4 || a2 <= v20 || v18 >= a6) goto LABEL_6;\n }\n if (v23 <= *(uint32_t *)&a5[4 * v18]) {\n ++v19;\n LODWORD(i) = v17;\n *v16 = v23;\n goto LABEL_13;\n }\n LABEL_12:\n LODWORD(i) = v17;\n *v16 = *(uint32_t *)&a5[4 * v18++];\n goto LABEL_13;\n }\n LODWORD(i) = 0;\n v18 = 0;\n v19 = 0;\n v20 = 0;\nLABEL_6:\n if (a2 > v20 && a4 > v19) {\n for (i = (int)i + 1;; ++i) {\n v24 = *(uint32_t *)&a1[4 * v20];\n v25 = *(uint32_t *)&a3[4 * v19];\n if (v24 > v25) {\n ++v19;\n v24 = v25;\n } else {\n ++v20;\n }\n v15[i - 1] = v24;\n if (v20 >= a2 || v19 >= a4) break;\n }\n }\n if (a2 > v20 && a6 > v18) {\n for (i = (int)i + 1;; ++i) {\n v26 = *(uint32_t *)&a1[4 * v20];\n v27 = *(uint32_t *)&a5[4 * v18];\n if (v26 > v27) {\n ++v18;\n v26 = v27;\n } else {\n ++v20;\n }\n v15[i - 1] = v26;\n if (v20 >= a2 || v18 >= a6) break;\n }\n }\n if (a4 > v19 && a6 > v18) {\n for (i = (int)i + 1;; ++i) {\n v28 = *(uint32_t *)&a3[4 * v19];\n v29 = *(uint32_t *)&a5[4 * v18];\n if (v28 > v29) {\n ++v18;\n v28 = v29;\n } else {\n ++v19;\n }\n v15[i - 1] = v28;\n if (v19 >= a4 || v18 >= a6) break;\n }\n }\n if (a2 > v20) {\n v30 = a2 - v20;\n v31 = &a1[4 * v20];\n v32 = 0LL;\n do {\n v15[(int)i + v32] = *(uint32_t *)&v31[v32 * 4];\n ++v32;\n } while (v32 != v30);\n LODWORD(i) = v30 + i;\n }\n if (a4 > v19) {\n v33 = a4 - v19;\n v34 = 0LL;\n do {\n v15[(int)i + v34] = *(uint32_t *)&a3[4 * v19 + v34 * 4];\n ++v34;\n } while (v34 != v33);\n LODWORD(i) = v33 + i;\n }\n if (a6 > v18) {\n v35 = 4LL * (unsigned int)(a6 - v18);\n v36 = &v15[(int)i];\n v37 = 0LL;\n do {\n v36[v37 / 4] = *(uint32_t *)&a5[4 * v18 + v37];\n v37 += 4LL;\n } while (v37 != v35);\n }\n return v15;\n}" + }, + { + "index": 108, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n// Compare function for qsort\n\nint compare(const void *a, const void *b) {\n\n int int_a = *(const int*) a;\n\n int int_b = *(const int*) b;\n\n return (int_a > int_b) - (int_a < int_b);\n\n}\n\n\n\n// Function to merge three sorted lists\n\n", + "func": "int *func0(int num1[], int size1, int num2[], int size2, int num3[], int size3,\n int *result_size) {\n qsort(num1, size1, sizeof(int), compare);\n qsort(num2, size2, sizeof(int), compare);\n qsort(num3, size3, sizeof(int), compare);\n *result_size = size1 + size2 + size3;\n int *result = malloc(*result_size * sizeof(int));\n if (!result) {\n perror(\"Failed to allocate memory\");\n exit(EXIT_FAILURE);\n }\n int i = 0, j = 0, k = 0, l = 0;\n while (i < size1 && j < size2 && k < size3) {\n if (num1[i] <= num2[j] && num1[i] <= num3[k]) {\n result[l++] = num1[i++];\n } else if (num2[j] <= num1[i] && num2[j] <= num3[k]) {\n result[l++] = num2[j++];\n } else {\n result[l++] = num3[k++];\n }\n }\n while (i < size1 && j < size2) {\n result[l++] = (num1[i] <= num2[j]) ? num1[i++] : num2[j++];\n }\n while (i < size1 && k < size3) {\n result[l++] = (num1[i] <= num3[k]) ? num1[i++] : num3[k++];\n }\n while (j < size2 && k < size3) {\n result[l++] = (num2[j] <= num3[k]) ? num2[j++] : num3[k++];\n }\n while (i < size1) {\n result[l++] = num1[i++];\n }\n while (j < size2) {\n result[l++] = num2[j++];\n }\n while (k < size3) {\n result[l++] = num3[k++];\n }\n return result;\n}", + "test": "int main() {\n\n // First test case\n\n int num1_1[] = {25, 24, 15, 4, 5, 29, 110};\n\n int size1_1 = sizeof(num1_1) / sizeof(num1_1[0]);\n\n int num2_1[] = {19, 20, 11, 56, 25, 233, 154};\n\n int size2_1 = sizeof(num2_1) / sizeof(num2_1[0]);\n\n int num3_1[] = {24, 26, 54, 48};\n\n int size3_1 = sizeof(num3_1) / sizeof(num3_1[0]);\n\n int expected1[] = {4, 5, 11, 15, 19, 20, 24, 24, 25, 25, 26, 29, 48, 54, 56, 110, 154, 233};\n\n int expected_size1 = sizeof(expected1) / sizeof(expected1[0]);\n\n int result_size1;\n\n int *result1 = func0(num1_1, size1_1, num2_1, size2_1, num3_1, size3_1, &result_size1);\n\n assert(result_size1 == expected_size1);\n\n for(int i = 0; i < expected_size1; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n free(result1);\n\n\n\n // Second test case\n\n int num1_2[] = {1, 3, 5, 6, 8, 9};\n\n int size1_2 = sizeof(num1_2) / sizeof(num1_2[0]);\n\n int num2_2[] = {2, 5, 7, 11};\n\n int size2_2 = sizeof(num2_2) / sizeof(num2_2[0]);\n\n int num3_2[] = {1, 4, 7, 8, 12};\n\n int size3_2 = sizeof(num3_2) / sizeof(num3_2[0]);\n\n int expected2[] = {1, 1, 2, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 11, 12};\n\n int expected_size2 = sizeof(expected2) / sizeof(expected2[0]);\n\n int result_size2;\n\n int *result2 = func0(num1_2, size1_2, num2_2, size2_2, num3_2, size3_2, &result_size2);\n\n assert(result_size2 == expected_size2);\n\n for(int i = 0; i < expected_size2; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n free(result2);\n\n\n\n // Third test case\n\n int num1_3[] = {18, 14, 10, 9, 8, 7, 9, 3, 2, 4, 1};\n\n int size1_3 = sizeof(num1_3) / sizeof(num1_3[0]);\n\n int num2_3[] = {25, 35, 22, 85, 14, 65, 75, 25, 58};\n\n int size2_3 = sizeof(num2_3) / sizeof(num2_3[0]);\n\n int num3_3[] = {12, 74, 9, 50, 61, 41};\n\n int size3_3 = sizeof(num3_3) / sizeof(num3_3[0]);\n\n int expected3[] = {1, 2, 3, 4, 7, 8, 9, 9, 9, 10, 12, 14, 14, 18, 22, 25, 25, 35, 41, 50, 58, 61, 65, 74, 75, 85};\n\n int expected_size3 = sizeof(expected3) / sizeof(expected3[0]);\n\n int result_size3;\n\n int *result3 = func0(num1_3, size1_3, num2_3, size2_3, num3_3, size3_3, &result_size3);\n\n assert(result_size3 == expected_size3);\n\n for(int i = 0; i < expected_size3; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmovslq %esi,%rsi\nmov %r9d,%r15d\npush %r14\nmov %r8,%r14\npush %r13\nmov %rdi,%r13\npush %r12\nmov %rdx,%r12\nmov $0x4,%edx\npush %rbp\nmov %rsi,%rbp\npush %rbx\nmov %ecx,%ebx\nlea -0x4e(%rip),%rcx\nsub $0x18,%rsp\ncallq 10c0 \nmovslq %ebx,%rsi\nmov $0x4,%edx\nmov %r12,%rdi\nlea -0x69(%rip),%rcx\ncallq 10c0 \nmov %r14,%rdi\nmovslq %r15d,%rsi\nmov $0x4,%edx\nlea -0x80(%rip),%rcx\ncallq 10c0 \nmov 0x50(%rsp),%rax\nlea 0x0(%rbp,%rbx,1),%edi\nadd %r15d,%edi\nmov %edi,(%rax)\nmovslq %edi,%rdi\nshl $0x2,%rdi\ncallq 10f0 \ntest %rax,%rax\nje 1b63 \ntest %ebp,%ebp\nsetg %cl\ntest %ebx,%ebx\nsetg %dl\ntest %r15d,%r15d\nmov %ecx,%r8d\nsetg %sil\nmov %edx,%r9d\ntest %sil,%dl\nje 1b50 \ntest %cl,%cl\nje 1b50 \nmov %ebx,0xc(%rsp)\nmov $0x1,%r11d\nxor %edi,%edi\nxor %r10d,%r10d\nxor %ecx,%ecx\njmp 195d \nnopl 0x0(%rax,%rax,1)\ncmp %r8d,%esi\njg 1990 \nmov %esi,-0x4(%rax,%r11,4)\nadd $0x1,%r10d\nnopw %cs:0x0(%rax,%rax,1)\ncmp %ebp,%ecx\nsetl %r8b\ncmp 0xc(%rsp),%r10d\nsetl %r9b\nmov %r8d,%edx\nand %r9d,%edx\ncmp %r15d,%edi\nsetl %sil\nadd $0x1,%r11\ntest %sil,%sil\nje 19a0 \ntest %dl,%dl\nje 1a08 \nmovslq %ecx,%rdx\nmovslq %r10d,%rsi\nmovslq %edi,%r8\nmov %r11d,%ebx\nmov 0x0(%r13,%rdx,4),%edx\nmov (%r12,%rsi,4),%esi\nmov (%r14,%r8,4),%r8d\ncmp %esi,%edx\njg 1918 \ncmp %r8d,%edx\njg 1990 \nmov %edx,-0x4(%rax,%r11,4)\nadd $0x1,%ecx\njmp 1930 \nnopl 0x0(%rax)\nmov %r8d,-0x4(%rax,%r11,4)\nadd $0x1,%edi\njmp 1930 \nnopw 0x0(%rax,%rax,1)\nmov %edx,%r11d\nmov %ebx,%edx\nmov 0xc(%rsp),%ebx\ntest %r11b,%r11b\nje 1a0e \nadd $0x1,%edx\nmovslq %edx,%r11\njmp 19e6 \nnopw %cs:0x0(%rax,%rax,1)\nadd $0x1,%ecx\ncmp %ebp,%ecx\nmov %r8d,-0x4(%rax,%r11,4)\nmov %r11d,%edx\nsetl %r8b\ncmp %ebx,%r10d\nsetl %r9b\nadd $0x1,%r11\ntest %r8b,%r8b\nje 1a0e \ntest %r9b,%r9b\nje 1a0e \nmovslq %ecx,%rdx\nmov 0x0(%r13,%rdx,4),%r8d\nmovslq %r10d,%rdx\nmov (%r12,%rdx,4),%edx\ncmp %edx,%r8d\njle 19c0 \nadd $0x1,%r10d\nmov %edx,%r8d\njmp 19c3 \nnopl 0x0(%rax,%rax,1)\nmov %ebx,%edx\nmov 0xc(%rsp),%ebx\ntest %sil,%sil\nje 1a60 \ntest %r8b,%r8b\nje 1a60 \nadd $0x1,%edx\nmovslq %edx,%r8\njmp 1a3f \nadd $0x1,%ecx\ncmp %r15d,%edi\nmov %esi,-0x4(%rax,%r8,4)\nmov %r8d,%edx\nsetl %sil\nadd $0x1,%r8\ncmp %ebp,%ecx\njge 1a60 \ntest %sil,%sil\nje 1a60 \nmovslq %ecx,%rdx\nmov 0x0(%r13,%rdx,4),%esi\nmovslq %edi,%rdx\nmov (%r14,%rdx,4),%edx\ncmp %edx,%esi\njle 1a20 \nadd $0x1,%edi\nmov %edx,%esi\njmp 1a23 \nnopl 0x0(%rax)\ntest %r9b,%r9b\nje 1aba \ntest %sil,%sil\nje 1aba \nadd $0x1,%edx\nmovslq %edx,%rsi\njmp 1a91 \nnopw 0x0(%rax,%rax,1)\nadd $0x1,%r10d\nmov %r8d,-0x4(%rax,%rsi,4)\nmov %esi,%edx\nadd $0x1,%rsi\ncmp %ebx,%r10d\njge 1aba \ncmp %r15d,%edi\njge 1aba \nmovslq %r10d,%rdx\nmov (%r12,%rdx,4),%r8d\nmovslq %edi,%rdx\nmov (%r14,%rdx,4),%edx\ncmp %edx,%r8d\njle 1a78 \nmov %edx,%r8d\nadd $0x1,%edi\nmov %esi,%edx\nmov %r8d,-0x4(%rax,%rsi,4)\nadd $0x1,%rsi\ncmp %ebx,%r10d\njl 1a8c \ncmp %ecx,%ebp\njle 1ae5 \nmovslq %ecx,%rsi\nmovslq %edx,%r8\nsub %rsi,%r8\nlea (%rax,%r8,4),%r9\nnopl 0x0(%rax,%rax,1)\nmov 0x0(%r13,%rsi,4),%r8d\nmov %r8d,(%r9,%rsi,4)\nadd $0x1,%rsi\ncmp %esi,%ebp\njg 1ad0 \nsub %ecx,%ebp\nadd %ebp,%edx\ncmp %r10d,%ebx\njle 1b15 \nmovslq %r10d,%rcx\nmovslq %edx,%rsi\nsub %rcx,%rsi\nlea (%rax,%rsi,4),%r8\nnopw 0x0(%rax,%rax,1)\nmov (%r12,%rcx,4),%esi\nmov %esi,(%r8,%rcx,4)\nadd $0x1,%rcx\ncmp %ecx,%ebx\njg 1b00 \nsub %r10d,%ebx\nadd %ebx,%edx\ncmp %edi,%r15d\njle 1b40 \nmovslq %edi,%rdi\nmovslq %edx,%rdx\nsub %rdi,%rdx\nlea (%rax,%rdx,4),%rcx\nnopw 0x0(%rax,%rax,1)\nmov (%r14,%rdi,4),%edx\nmov %edx,(%rcx,%rdi,4)\nadd $0x1,%rdi\ncmp %edi,%r15d\njg 1b30 \nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nand %ecx,%edx\nxor %edi,%edi\nxor %r10d,%r10d\nxor %ecx,%ecx\nmov %edx,%r11d\nxor %edx,%edx\njmpq 19a9 \nlea 0x49a(%rip),%rdi\ncallq 1100 \nmov $0x1,%edi\ncallq 1110 \nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmovsxd rsi, esi; nmemb\nmov r15, r8\npush r14\nmov r14, rsi\npush r13\nmov r13d, ecx\npush r12\npush rbp\npush rbx\nlea rbx, compare\nmov rcx, rbx; compar\nsub rsp, 28h\nmov [rsp+58h+base], rdx\nmov edx, 4; size\nmov dword ptr [rsp+58h+var_58], r9d\nmov [rsp+58h+var_48], rdi\ncall _qsort\nmov rdi, [rsp+58h+base]; base\nmovsxd rsi, r13d; nmemb\nmov rcx, rbx; compar\nmov edx, 4; size\ncall _qsort\nmovsxd rsi, dword ptr [rsp+58h+var_58]; nmemb\nmov rdi, r15; base\nmov rcx, rbx; compar\nmov edx, 4; size\ncall _qsort\nmov r9d, dword ptr [rsp+58h+var_58]\nmov rax, [rsp+58h+arg_0]\nlea edi, [r14+r13]\nadd edi, r9d\nmov [rax], edi\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\ntest rax, rax\njz func0_cold\nmov r9d, dword ptr [rsp+58h+var_58]\ntest r14d, r14d\nmov r8, rax\nmov r10, [rsp+58h+base]\nsetnle sil\ntest r13d, r13d\nmov r11, [rsp+58h+var_48]\nsetnle cl\ntest r9d, r9d\nmov edx, esi\nsetnle byte ptr [rsp+58h+var_58]\nmovzx edi, byte ptr [rsp+58h+var_58]\nmov eax, ecx\ntest dil, cl\njz loc_1A40\ntest sil, sil\njz loc_1A40\nmov [rsp+58h+base], r8\nmov ebx, 1\nxor ebp, ebp\nxor ecx, ecx\nxor r12d, r12d\njmp short loc_1811\nloc_17C8:\ncmp esi, eax\njg short loc_1840\nadd ecx, 1\nmov eax, esi\nnop dword ptr [rax+00000000h]\nloc_17D8:\nmov rdi, [rsp+58h+base]\ncmp r14d, r12d\nsetnle dl\ncmp ecx, r13d\nmov [rdi+rbx*4-4], eax\nmov r8d, edx\nsetl al\ncmp ebp, r9d\nsetl sil\nand r8b, al\nlea rdi, [rbx+1]\nmov byte ptr [rsp+58h+var_58], sil\nmov byte ptr [rsp+58h+var_48], r8b\njz short loc_1848\ntest sil, sil\njz short loc_1848\nmov rbx, rdi\nloc_1811:\nmovsxd rax, r12d\nmov edx, [r11+rax*4]\nmovsxd rax, ecx\nmov esi, [r10+rax*4]\nmovsxd rax, ebp\nmov eax, [r15+rax*4]\ncmp esi, edx\njl short loc_17C8\ncmp eax, edx\njl short loc_1840\nadd r12d, 1\nmov eax, edx\njmp short loc_17D8\nloc_1840:\nadd ebp, 1\njmp short loc_17D8\nloc_1848:\nmov r8, [rsp+58h+base]\nloc_184D:\ncmp byte ptr [rsp+58h+var_48], 0\njz short loc_18A8\nadd ebx, 1\nmovsxd rbx, ebx\njmp short loc_188A\nloc_1860:\nadd r12d, 1\nmov eax, edx\nloc_1866:\ncmp r12d, r14d\nmov [r8+rbx*4-4], eax\nlea rdi, [rbx+1]\nsetl sil\ncmp ecx, r13d\nsetl al\nmov edx, esi\ntest al, al\njz short loc_18A8\ntest sil, sil\njz short loc_18A8\nmov rbx, rdi\nloc_188A:\nmovsxd rax, r12d\nmov edx, [r11+rax*4]\nmovsxd rax, ecx\nmov eax, [r10+rax*4]\ncmp eax, edx\njge short loc_1860\nadd ecx, 1\njmp short loc_1866\nloc_18A8:\ncmp byte ptr [rsp+58h+var_58], 0\njz short loc_1904\ntest dl, dl\njz short loc_1904\nadd ebx, 1\nmovsxd rbx, ebx\njmp short loc_18E3\nloc_18C0:\nadd r12d, 1\nmov edx, esi\nloc_18C6:\ncmp r9d, ebp\nmov [r8+rbx*4-4], edx\nlea rsi, [rbx+1]\nsetnle dl\nmov edi, edx\ncmp r14d, r12d\njle short loc_1900\ntest dl, dl\njz short loc_1900\nmov rbx, rsi\nloc_18E3:\nmovsxd rdx, r12d\nmov esi, [r11+rdx*4]\nmovsxd rdx, ebp\nmov edx, [r15+rdx*4]\ncmp edx, esi\njge short loc_18C0\nadd ebp, 1\njmp short loc_18C6\nloc_1900:\nmov byte ptr [rsp+58h+var_58], dil\nloc_1904:\ntest al, al\njz short loc_195E\ncmp byte ptr [rsp+58h+var_58], 0\njz short loc_195E\nadd ebx, 1\nmovsxd rbx, ebx\njmp short loc_193B\nloc_1920:\nmov eax, edx\nadd ecx, 1\nmov [r8+rbx*4-4], eax\nlea rax, [rbx+1]\ncmp r13d, ecx\njle short loc_195E\nloc_1933:\ncmp r9d, ebp\njle short loc_195E\nmov rbx, rax\nloc_193B:\nmovsxd rax, ecx\nmov edx, [r10+rax*4]\nmovsxd rax, ebp\nmov eax, [r15+rax*4]\ncmp eax, edx\njge short loc_1920\nmov [r8+rbx*4-4], eax\nadd ebp, 1\nlea rax, [rbx+1]\ncmp r13d, ecx\njg short loc_1933\nloc_195E:\ncmp r14d, r12d\njle short loc_19AF\nmovsxd rax, ebx\nmov [rsp+58h+var_3C], r9d\nlea rdi, [r8+rax*4]; dest\nlea eax, [r14-1]\nmov [rsp+58h+var_48], r10\nsub r14d, r12d\nsub eax, r12d\nmov dword ptr [rsp+58h+base], ecx\nadd ebx, r14d\nlea rdx, ds:4[rax*4]; n\nmovsxd rax, r12d\nmov [rsp+58h+var_58], r8\nlea rsi, [r11+rax*4]; src\ncall _memcpy\nmov r9d, [rsp+58h+var_3C]\nmov r10, [rsp+58h+var_48]\nmov ecx, dword ptr [rsp+58h+base]\nmov r8, [rsp+58h+var_58]\nloc_19AF:\ncmp r13d, ecx\njle short loc_19F5\nmovsxd rax, ebx\nmov dword ptr [rsp+58h+var_48], r9d\nlea rdi, [r8+rax*4]; dest\nlea eax, [r13-1]\nmov [rsp+58h+base], r8\nsub eax, ecx\nmov dword ptr [rsp+58h+var_58], ecx\nlea rdx, ds:4[rax*4]; n\nmovsxd rax, ecx\nlea rsi, [r10+rax*4]; src\ncall _memcpy\nmov ecx, dword ptr [rsp+58h+var_58]\nmov r9d, dword ptr [rsp+58h+var_48]\nmov r8, [rsp+58h+base]\nsub r13d, ecx\nadd ebx, r13d\nloc_19F5:\ncmp r9d, ebp\njle short loc_1A24\nsub r9d, 1\nmovsxd rbx, ebx\nmov [rsp+58h+var_58], r8\nsub r9d, ebp\nmovsxd rbp, ebp\nlea rdi, [r8+rbx*4]; dest\nlea rdx, ds:4[r9*4]; n\nlea rsi, [r15+rbp*4]; src\ncall _memcpy\nmov r8, [rsp+58h+var_58]\nloc_1A24:\nadd rsp, 28h\nmov rax, r8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1A40:\nand esi, ecx\nxor ebx, ebx\nxor ebp, ebp\nxor ecx, ecx\nmov byte ptr [rsp+58h+var_48], sil\nxor r12d, r12d\njmp loc_184D", + "ida_pseudo": "_DWORD *__fastcall func0(void *a1, int a2, char *a3, int a4, char *a5, int a6, _DWORD *a7)\n{\n int v10; // edi\n _DWORD *v11; // rax\n int v12; // r9d\n _DWORD *v13; // r8\n char *v14; // r10\n _DWORD *v15; // r11\n bool v16; // dl\n bool v17; // al\n __int64 i; // rbx\n int v19; // ebp\n int v20; // ecx\n int v21; // r12d\n int v22; // eax\n int v23; // edx\n int v24; // esi\n int v25; // eax\n int v26; // edx\n int v27; // edx\n int v28; // esi\n __int64 v29; // rax\n int v30; // edx\n int v31; // eax\n char *v32; // rdi\n bool v35; // [rsp+0h] [rbp-58h]\n _DWORD *v36; // [rsp+0h] [rbp-58h]\n int v37; // [rsp+0h] [rbp-58h]\n _DWORD *v38; // [rsp+0h] [rbp-58h]\n int basea; // [rsp+8h] [rbp-50h]\n _DWORD *baseb; // [rsp+8h] [rbp-50h]\n bool v43; // [rsp+10h] [rbp-48h]\n char *v44; // [rsp+10h] [rbp-48h]\n int v45; // [rsp+10h] [rbp-48h]\n int v46; // [rsp+1Ch] [rbp-3Ch]\n\n qsort(a1, a2, 4uLL, compare);\n qsort(a3, a4, 4uLL, compare);\n qsort(a5, a6, 4uLL, compare);\n v10 = a6 + a2 + a4;\n *a7 = v10;\n v11 = malloc(4LL * v10);\n if ( !v11 )\n func0_cold();\n v12 = a6;\n v13 = v11;\n v14 = a3;\n v15 = a1;\n v16 = a2 > 0;\n v35 = a6 > 0;\n v17 = a4 > 0;\n if ( a4 > 0 && v35 && a2 > 0 )\n {\n i = 1LL;\n v19 = 0;\n v20 = 0;\n v21 = 0;\n while ( 1 )\n {\n v23 = v15[v21];\n v24 = *(_DWORD *)&a3[4 * v20];\n v22 = *(_DWORD *)&a5[4 * v19];\n if ( v24 < v23 )\n {\n if ( v24 > v22 )\n goto LABEL_13;\n ++v20;\n v22 = v24;\n }\n else\n {\n if ( v22 < v23 )\n {\nLABEL_13:\n ++v19;\n goto LABEL_7;\n }\n ++v21;\n v22 = v23;\n }\nLABEL_7:\n v16 = a2 > v21;\n v13[i - 1] = v22;\n v17 = v20 < a4;\n v35 = v19 < v12;\n v43 = v20 < a4 && a2 > v21;\n if ( !v43 || v19 >= v12 )\n goto LABEL_14;\n ++i;\n }\n }\n LODWORD(i) = 0;\n v19 = 0;\n v20 = 0;\n v43 = a4 > 0 && a2 > 0;\n v21 = 0;\nLABEL_14:\n if ( v43 )\n {\n for ( i = (int)i + 1; ; ++i )\n {\n v26 = v15[v21];\n v25 = *(_DWORD *)&a3[4 * v20];\n if ( v25 >= v26 )\n {\n ++v21;\n v25 = v26;\n }\n else\n {\n ++v20;\n }\n v13[i - 1] = v25;\n v17 = v20 < a4;\n v16 = v21 < a2;\n if ( v20 >= a4 || v21 >= a2 )\n break;\n }\n }\n if ( v35 && v16 )\n {\n for ( i = (int)i + 1; ; ++i )\n {\n v28 = v15[v21];\n v27 = *(_DWORD *)&a5[4 * v19];\n if ( v27 >= v28 )\n {\n ++v21;\n v27 = v28;\n }\n else\n {\n ++v19;\n }\n v13[i - 1] = v27;\n if ( a2 <= v21 || v12 <= v19 )\n break;\n }\n v35 = v12 > v19;\n }\n if ( v17 && v35 )\n {\n for ( i = (int)i + 1; ; i = v29 )\n {\n v30 = *(_DWORD *)&a3[4 * v20];\n v31 = *(_DWORD *)&a5[4 * v19];\n if ( v31 >= v30 )\n {\n ++v20;\n v13[i - 1] = v30;\n v29 = i + 1;\n if ( a4 <= v20 )\n break;\n }\n else\n {\n v13[i - 1] = v31;\n ++v19;\n v29 = i + 1;\n if ( a4 <= v20 )\n break;\n }\n if ( v12 <= v19 )\n break;\n }\n }\n if ( a2 > v21 )\n {\n v46 = v12;\n v32 = (char *)&v13[(int)i];\n v44 = a3;\n basea = v20;\n LODWORD(i) = a2 - v21 + i;\n v36 = v13;\n memcpy(v32, &v15[v21], 4LL * (unsigned int)(a2 - 1 - v21) + 4);\n v12 = v46;\n v14 = v44;\n v20 = basea;\n v13 = v36;\n }\n if ( a4 > v20 )\n {\n v45 = v12;\n baseb = v13;\n v37 = v20;\n memcpy(&v13[(int)i], &v14[4 * v20], 4LL * (unsigned int)(a4 - 1 - v20) + 4);\n v12 = v45;\n v13 = baseb;\n LODWORD(i) = a4 - v37 + i;\n }\n if ( v12 > v19 )\n {\n v38 = v13;\n memcpy(&v13[(int)i], &a5[4 * v19], 4LL * (unsigned int)(v12 - 1 - v19) + 4);\n return v38;\n }\n return v13;\n}", + "ida_strip_asm": "sub_16E0:\nendbr64\npush r15\nmovsxd rsi, esi; nmemb\nmov r15, r8\npush r14\nmov r14, rsi\npush r13\nmov r13d, ecx\npush r12\npush rbp\npush rbx\nlea rbx, compar\nmov rcx, rbx; compar\nsub rsp, 28h\nmov [rsp+58h+base], rdx\nmov edx, 4; size\nmov dword ptr [rsp+58h+var_58], r9d\nmov [rsp+58h+var_48], rdi\ncall _qsort\nmov rdi, [rsp+58h+base]; base\nmovsxd rsi, r13d; nmemb\nmov rcx, rbx; compar\nmov edx, 4; size\ncall _qsort\nmovsxd rsi, dword ptr [rsp+58h+var_58]; nmemb\nmov rdi, r15; base\nmov rcx, rbx; compar\nmov edx, 4; size\ncall _qsort\nmov r9d, dword ptr [rsp+58h+var_58]\nmov rax, [rsp+58h+arg_0]\nlea edi, [r14+r13]\nadd edi, r9d\nmov [rax], edi\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\ntest rax, rax\njz loc_1140\nmov r9d, dword ptr [rsp+58h+var_58]\ntest r14d, r14d\nmov r8, rax\nmov r10, [rsp+58h+base]\nsetnle sil\ntest r13d, r13d\nmov r11, [rsp+58h+var_48]\nsetnle cl\ntest r9d, r9d\nmov edx, esi\nsetnle byte ptr [rsp+58h+var_58]\nmovzx edi, byte ptr [rsp+58h+var_58]\nmov eax, ecx\ntest dil, cl\njz loc_1A40\ntest sil, sil\njz loc_1A40\nmov [rsp+58h+base], r8\nmov ebx, 1\nxor ebp, ebp\nxor ecx, ecx\nxor r12d, r12d\njmp short loc_1811\nloc_17C8:\ncmp esi, eax\njg short loc_1840\nadd ecx, 1\nmov eax, esi\nnop dword ptr [rax+00000000h]\nloc_17D8:\nmov rdi, [rsp+58h+base]\ncmp r14d, r12d\nsetnle dl\ncmp ecx, r13d\nmov [rdi+rbx*4-4], eax\nmov r8d, edx\nsetl al\ncmp ebp, r9d\nsetl sil\nand r8b, al\nlea rdi, [rbx+1]\nmov byte ptr [rsp+58h+var_58], sil\nmov byte ptr [rsp+58h+var_48], r8b\njz short loc_1848\ntest sil, sil\njz short loc_1848\nmov rbx, rdi\nloc_1811:\nmovsxd rax, r12d\nmov edx, [r11+rax*4]\nmovsxd rax, ecx\nmov esi, [r10+rax*4]\nmovsxd rax, ebp\nmov eax, [r15+rax*4]\ncmp esi, edx\njl short loc_17C8\ncmp eax, edx\njl short loc_1840\nadd r12d, 1\nmov eax, edx\njmp short loc_17D8\nloc_1840:\nadd ebp, 1\njmp short loc_17D8\nloc_1848:\nmov r8, [rsp+58h+base]\nloc_184D:\ncmp byte ptr [rsp+58h+var_48], 0\njz short loc_18A8\nadd ebx, 1\nmovsxd rbx, ebx\njmp short loc_188A\nloc_1860:\nadd r12d, 1\nmov eax, edx\nloc_1866:\ncmp r12d, r14d\nmov [r8+rbx*4-4], eax\nlea rdi, [rbx+1]\nsetl sil\ncmp ecx, r13d\nsetl al\nmov edx, esi\ntest al, al\njz short loc_18A8\ntest sil, sil\njz short loc_18A8\nmov rbx, rdi\nloc_188A:\nmovsxd rax, r12d\nmov edx, [r11+rax*4]\nmovsxd rax, ecx\nmov eax, [r10+rax*4]\ncmp eax, edx\njge short loc_1860\nadd ecx, 1\njmp short loc_1866\nloc_18A8:\ncmp byte ptr [rsp+58h+var_58], 0\njz short loc_1904\ntest dl, dl\njz short loc_1904\nadd ebx, 1\nmovsxd rbx, ebx\njmp short loc_18E3\nloc_18C0:\nadd r12d, 1\nmov edx, esi\nloc_18C6:\ncmp r9d, ebp\nmov [r8+rbx*4-4], edx\nlea rsi, [rbx+1]\nsetnle dl\nmov edi, edx\ncmp r14d, r12d\njle short loc_1900\ntest dl, dl\njz short loc_1900\nmov rbx, rsi\nloc_18E3:\nmovsxd rdx, r12d\nmov esi, [r11+rdx*4]\nmovsxd rdx, ebp\nmov edx, [r15+rdx*4]\ncmp edx, esi\njge short loc_18C0\nadd ebp, 1\njmp short loc_18C6\nloc_1900:\nmov byte ptr [rsp+58h+var_58], dil\nloc_1904:\ntest al, al\njz short loc_195E\ncmp byte ptr [rsp+58h+var_58], 0\njz short loc_195E\nadd ebx, 1\nmovsxd rbx, ebx\njmp short loc_193B\nloc_1920:\nmov eax, edx\nadd ecx, 1\nmov [r8+rbx*4-4], eax\nlea rax, [rbx+1]\ncmp r13d, ecx\njle short loc_195E\nloc_1933:\ncmp r9d, ebp\njle short loc_195E\nmov rbx, rax\nloc_193B:\nmovsxd rax, ecx\nmov edx, [r10+rax*4]\nmovsxd rax, ebp\nmov eax, [r15+rax*4]\ncmp eax, edx\njge short loc_1920\nmov [r8+rbx*4-4], eax\nadd ebp, 1\nlea rax, [rbx+1]\ncmp r13d, ecx\njg short loc_1933\nloc_195E:\ncmp r14d, r12d\njle short loc_19AF\nmovsxd rax, ebx\nmov [rsp+58h+var_3C], r9d\nlea rdi, [r8+rax*4]; dest\nlea eax, [r14-1]\nmov [rsp+58h+var_48], r10\nsub r14d, r12d\nsub eax, r12d\nmov dword ptr [rsp+58h+base], ecx\nadd ebx, r14d\nlea rdx, ds:4[rax*4]; n\nmovsxd rax, r12d\nmov [rsp+58h+var_58], r8\nlea rsi, [r11+rax*4]; src\ncall _memcpy\nmov r9d, [rsp+58h+var_3C]\nmov r10, [rsp+58h+var_48]\nmov ecx, dword ptr [rsp+58h+base]\nmov r8, [rsp+58h+var_58]\nloc_19AF:\ncmp r13d, ecx\njle short loc_19F5\nmovsxd rax, ebx\nmov dword ptr [rsp+58h+var_48], r9d\nlea rdi, [r8+rax*4]; dest\nlea eax, [r13-1]\nmov [rsp+58h+base], r8\nsub eax, ecx\nmov dword ptr [rsp+58h+var_58], ecx\nlea rdx, ds:4[rax*4]; n\nmovsxd rax, ecx\nlea rsi, [r10+rax*4]; src\ncall _memcpy\nmov ecx, dword ptr [rsp+58h+var_58]\nmov r9d, dword ptr [rsp+58h+var_48]\nmov r8, [rsp+58h+base]\nsub r13d, ecx\nadd ebx, r13d\nloc_19F5:\ncmp r9d, ebp\njle short loc_1A24\nsub r9d, 1\nmovsxd rbx, ebx\nmov [rsp+58h+var_58], r8\nsub r9d, ebp\nmovsxd rbp, ebp\nlea rdi, [r8+rbx*4]; dest\nlea rdx, ds:4[r9*4]; n\nlea rsi, [r15+rbp*4]; src\ncall _memcpy\nmov r8, [rsp+58h+var_58]\nloc_1A24:\nadd rsp, 28h\nmov rax, r8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1A40:\nand esi, ecx\nxor ebx, ebx\nxor ebp, ebp\nxor ecx, ecx\nmov byte ptr [rsp+58h+var_48], sil\nxor r12d, r12d\njmp loc_184D", + "ida_strip_pseudo": "_DWORD *__fastcall sub_16E0(void *a1, int a2, char *a3, int a4, char *a5, int a6, _DWORD *a7)\n{\n int v10; // edi\n _DWORD *v11; // rax\n int v12; // r9d\n _DWORD *v13; // r8\n char *v14; // r10\n _DWORD *v15; // r11\n bool v16; // dl\n bool v17; // al\n __int64 i; // rbx\n int v19; // ebp\n int v20; // ecx\n int v21; // r12d\n int v22; // eax\n int v23; // edx\n int v24; // esi\n int v25; // eax\n int v26; // edx\n int v27; // edx\n int v28; // esi\n __int64 v29; // rax\n int v30; // edx\n int v31; // eax\n char *v32; // rdi\n bool v35; // [rsp+0h] [rbp-58h]\n _DWORD *v36; // [rsp+0h] [rbp-58h]\n int v37; // [rsp+0h] [rbp-58h]\n _DWORD *v38; // [rsp+0h] [rbp-58h]\n int basea; // [rsp+8h] [rbp-50h]\n _DWORD *baseb; // [rsp+8h] [rbp-50h]\n bool v43; // [rsp+10h] [rbp-48h]\n char *v44; // [rsp+10h] [rbp-48h]\n int v45; // [rsp+10h] [rbp-48h]\n int v46; // [rsp+1Ch] [rbp-3Ch]\n\n qsort(a1, a2, 4uLL, compar);\n qsort(a3, a4, 4uLL, compar);\n qsort(a5, a6, 4uLL, compar);\n v10 = a6 + a2 + a4;\n *a7 = v10;\n v11 = malloc(4LL * v10);\n if ( !v11 )\n {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v12 = a6;\n v13 = v11;\n v14 = a3;\n v15 = a1;\n v16 = a2 > 0;\n v35 = a6 > 0;\n v17 = a4 > 0;\n if ( a4 > 0 && v35 && a2 > 0 )\n {\n i = 1LL;\n v19 = 0;\n v20 = 0;\n v21 = 0;\n while ( 1 )\n {\n v23 = v15[v21];\n v24 = *(_DWORD *)&a3[4 * v20];\n v22 = *(_DWORD *)&a5[4 * v19];\n if ( v24 < v23 )\n {\n if ( v24 > v22 )\n goto LABEL_13;\n ++v20;\n v22 = v24;\n }\n else\n {\n if ( v22 < v23 )\n {\nLABEL_13:\n ++v19;\n goto LABEL_7;\n }\n ++v21;\n v22 = v23;\n }\nLABEL_7:\n v16 = a2 > v21;\n v13[i - 1] = v22;\n v17 = v20 < a4;\n v35 = v19 < v12;\n v43 = v20 < a4 && a2 > v21;\n if ( !v43 || v19 >= v12 )\n goto LABEL_14;\n ++i;\n }\n }\n LODWORD(i) = 0;\n v19 = 0;\n v20 = 0;\n v43 = a4 > 0 && a2 > 0;\n v21 = 0;\nLABEL_14:\n if ( v43 )\n {\n for ( i = (int)i + 1; ; ++i )\n {\n v26 = v15[v21];\n v25 = *(_DWORD *)&a3[4 * v20];\n if ( v25 >= v26 )\n {\n ++v21;\n v25 = v26;\n }\n else\n {\n ++v20;\n }\n v13[i - 1] = v25;\n v17 = v20 < a4;\n v16 = v21 < a2;\n if ( v20 >= a4 || v21 >= a2 )\n break;\n }\n }\n if ( v35 && v16 )\n {\n for ( i = (int)i + 1; ; ++i )\n {\n v28 = v15[v21];\n v27 = *(_DWORD *)&a5[4 * v19];\n if ( v27 >= v28 )\n {\n ++v21;\n v27 = v28;\n }\n else\n {\n ++v19;\n }\n v13[i - 1] = v27;\n if ( a2 <= v21 || v12 <= v19 )\n break;\n }\n v35 = v12 > v19;\n }\n if ( v17 && v35 )\n {\n for ( i = (int)i + 1; ; i = v29 )\n {\n v30 = *(_DWORD *)&a3[4 * v20];\n v31 = *(_DWORD *)&a5[4 * v19];\n if ( v31 >= v30 )\n {\n ++v20;\n v13[i - 1] = v30;\n v29 = i + 1;\n if ( a4 <= v20 )\n break;\n }\n else\n {\n v13[i - 1] = v31;\n ++v19;\n v29 = i + 1;\n if ( a4 <= v20 )\n break;\n }\n if ( v12 <= v19 )\n break;\n }\n }\n if ( a2 > v21 )\n {\n v46 = v12;\n v32 = (char *)&v13[(int)i];\n v44 = a3;\n basea = v20;\n LODWORD(i) = a2 - v21 + i;\n v36 = v13;\n memcpy(v32, &v15[v21], 4LL * (unsigned int)(a2 - 1 - v21) + 4);\n v12 = v46;\n v14 = v44;\n v20 = basea;\n v13 = v36;\n }\n if ( a4 > v20 )\n {\n v45 = v12;\n baseb = v13;\n v37 = v20;\n memcpy(&v13[(int)i], &v14[4 * v20], 4LL * (unsigned int)(a4 - 1 - v20) + 4);\n v12 = v45;\n v13 = baseb;\n LODWORD(i) = a4 - v37 + i;\n }\n if ( v12 > v19 )\n {\n v38 = v13;\n memcpy(&v13[(int)i], &a5[4 * v19], 4LL * (unsigned int)(v12 - 1 - v19) + 4);\n return v38;\n }\n return v13;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_16E0(void *a1, int a2, char *a3, int a4, char *a5, int a6,\n uint32_t *a7) {\n int v10;\n uint32_t *v11;\n int v12;\n uint32_t *v13;\n char *v14;\n uint32_t *v15;\n bool v16;\n bool v17;\n long long i;\n int v19;\n int v20;\n int v21;\n int v22;\n int v23;\n int v24;\n int v25;\n int v26;\n int v27;\n int v28;\n long long v29;\n int v30;\n int v31;\n char *v32;\n bool v35;\n uint32_t *v36;\n int v37;\n uint32_t *v38;\n int basea;\n uint32_t *baseb;\n bool v43;\n char *v44;\n int v45;\n int v46;\n qsort(a1, a2, 4uLL, compar);\n qsort(a3, a4, 4uLL, compar);\n qsort(a5, a6, 4uLL, compar);\n v10 = a6 + a2 + a4;\n *a7 = v10;\n v11 = malloc(4LL * v10);\n if (!v11) {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v12 = a6;\n v13 = v11;\n v14 = a3;\n v15 = a1;\n v16 = a2 > 0;\n v35 = a6 > 0;\n v17 = a4 > 0;\n if (a4 > 0 && v35 && a2 > 0) {\n i = 1LL;\n v19 = 0;\n v20 = 0;\n v21 = 0;\n while (1) {\n v23 = v15[v21];\n v24 = *(uint32_t *)&a3[4 * v20];\n v22 = *(uint32_t *)&a5[4 * v19];\n if (v24 < v23) {\n if (v24 > v22) goto LABEL_13;\n ++v20;\n v22 = v24;\n } else {\n if (v22 < v23) {\n LABEL_13:\n ++v19;\n goto LABEL_7;\n }\n ++v21;\n v22 = v23;\n }\n LABEL_7:\n v16 = a2 > v21;\n v13[i - 1] = v22;\n v17 = v20 < a4;\n v35 = v19 < v12;\n v43 = v20 < a4 && a2 > v21;\n if (!v43 || v19 >= v12) goto LABEL_14;\n ++i;\n }\n }\n LODWORD(i) = 0;\n v19 = 0;\n v20 = 0;\n v43 = a4 > 0 && a2 > 0;\n v21 = 0;\nLABEL_14:\n if (v43) {\n for (i = (int)i + 1;; ++i) {\n v26 = v15[v21];\n v25 = *(uint32_t *)&a3[4 * v20];\n if (v25 >= v26) {\n ++v21;\n v25 = v26;\n } else {\n ++v20;\n }\n v13[i - 1] = v25;\n v17 = v20 < a4;\n v16 = v21 < a2;\n if (v20 >= a4 || v21 >= a2) break;\n }\n }\n if (v35 && v16) {\n for (i = (int)i + 1;; ++i) {\n v28 = v15[v21];\n v27 = *(uint32_t *)&a5[4 * v19];\n if (v27 >= v28) {\n ++v21;\n v27 = v28;\n } else {\n ++v19;\n }\n v13[i - 1] = v27;\n if (a2 <= v21 || v12 <= v19) break;\n }\n v35 = v12 > v19;\n }\n if (v17 && v35) {\n for (i = (int)i + 1;; i = v29) {\n v30 = *(uint32_t *)&a3[4 * v20];\n v31 = *(uint32_t *)&a5[4 * v19];\n if (v31 >= v30) {\n ++v20;\n v13[i - 1] = v30;\n v29 = i + 1;\n if (a4 <= v20) break;\n } else {\n v13[i - 1] = v31;\n ++v19;\n v29 = i + 1;\n if (a4 <= v20) break;\n }\n if (v12 <= v19) break;\n }\n }\n if (a2 > v21) {\n v46 = v12;\n v32 = (char *)&v13[(int)i];\n v44 = a3;\n basea = v20;\n LODWORD(i) = a2 - v21 + i;\n v36 = v13;\n memcpy(v32, &v15[v21], 4LL * (unsigned int)(a2 - 1 - v21) + 4);\n v12 = v46;\n v14 = v44;\n v20 = basea;\n v13 = v36;\n }\n if (a4 > v20) {\n v45 = v12;\n baseb = v13;\n v37 = v20;\n memcpy(&v13[(int)i], &v14[4 * v20], 4LL * (unsigned int)(a4 - 1 - v20) + 4);\n v12 = v45;\n v13 = baseb;\n LODWORD(i) = a4 - v37 + i;\n }\n if (v12 > v19) {\n v38 = v13;\n memcpy(&v13[(int)i], &a5[4 * v19], 4LL * (unsigned int)(v12 - 1 - v19) + 4);\n return v38;\n }\n return v13;\n}", + "ida_pseudo_norm": "uint32_t *func0(void *a1, int a2, char *a3, int a4, char *a5, int a6,\n uint32_t *a7) {\n int v10;\n uint32_t *v11;\n int v12;\n uint32_t *v13;\n char *v14;\n uint32_t *v15;\n bool v16;\n bool v17;\n long long i;\n int v19;\n int v20;\n int v21;\n int v22;\n int v23;\n int v24;\n int v25;\n int v26;\n int v27;\n int v28;\n long long v29;\n int v30;\n int v31;\n char *v32;\n bool v35;\n uint32_t *v36;\n int v37;\n uint32_t *v38;\n int basea;\n uint32_t *baseb;\n bool v43;\n char *v44;\n int v45;\n int v46;\n qsort(a1, a2, 4uLL, compare);\n qsort(a3, a4, 4uLL, compare);\n qsort(a5, a6, 4uLL, compare);\n v10 = a6 + a2 + a4;\n *a7 = v10;\n v11 = malloc(4LL * v10);\n if (!v11) func0_cold();\n v12 = a6;\n v13 = v11;\n v14 = a3;\n v15 = a1;\n v16 = a2 > 0;\n v35 = a6 > 0;\n v17 = a4 > 0;\n if (a4 > 0 && v35 && a2 > 0) {\n i = 1LL;\n v19 = 0;\n v20 = 0;\n v21 = 0;\n while (1) {\n v23 = v15[v21];\n v24 = *(uint32_t *)&a3[4 * v20];\n v22 = *(uint32_t *)&a5[4 * v19];\n if (v24 < v23) {\n if (v24 > v22) goto LABEL_13;\n ++v20;\n v22 = v24;\n } else {\n if (v22 < v23) {\n LABEL_13:\n ++v19;\n goto LABEL_7;\n }\n ++v21;\n v22 = v23;\n }\n LABEL_7:\n v16 = a2 > v21;\n v13[i - 1] = v22;\n v17 = v20 < a4;\n v35 = v19 < v12;\n v43 = v20 < a4 && a2 > v21;\n if (!v43 || v19 >= v12) goto LABEL_14;\n ++i;\n }\n }\n LODWORD(i) = 0;\n v19 = 0;\n v20 = 0;\n v43 = a4 > 0 && a2 > 0;\n v21 = 0;\nLABEL_14:\n if (v43) {\n for (i = (int)i + 1;; ++i) {\n v26 = v15[v21];\n v25 = *(uint32_t *)&a3[4 * v20];\n if (v25 >= v26) {\n ++v21;\n v25 = v26;\n } else {\n ++v20;\n }\n v13[i - 1] = v25;\n v17 = v20 < a4;\n v16 = v21 < a2;\n if (v20 >= a4 || v21 >= a2) break;\n }\n }\n if (v35 && v16) {\n for (i = (int)i + 1;; ++i) {\n v28 = v15[v21];\n v27 = *(uint32_t *)&a5[4 * v19];\n if (v27 >= v28) {\n ++v21;\n v27 = v28;\n } else {\n ++v19;\n }\n v13[i - 1] = v27;\n if (a2 <= v21 || v12 <= v19) break;\n }\n v35 = v12 > v19;\n }\n if (v17 && v35) {\n for (i = (int)i + 1;; i = v29) {\n v30 = *(uint32_t *)&a3[4 * v20];\n v31 = *(uint32_t *)&a5[4 * v19];\n if (v31 >= v30) {\n ++v20;\n v13[i - 1] = v30;\n v29 = i + 1;\n if (a4 <= v20) break;\n } else {\n v13[i - 1] = v31;\n ++v19;\n v29 = i + 1;\n if (a4 <= v20) break;\n }\n if (v12 <= v19) break;\n }\n }\n if (a2 > v21) {\n v46 = v12;\n v32 = (char *)&v13[(int)i];\n v44 = a3;\n basea = v20;\n LODWORD(i) = a2 - v21 + i;\n v36 = v13;\n memcpy(v32, &v15[v21], 4LL * (unsigned int)(a2 - 1 - v21) + 4);\n v12 = v46;\n v14 = v44;\n v20 = basea;\n v13 = v36;\n }\n if (a4 > v20) {\n v45 = v12;\n baseb = v13;\n v37 = v20;\n memcpy(&v13[(int)i], &v14[4 * v20], 4LL * (unsigned int)(a4 - 1 - v20) + 4);\n v12 = v45;\n v13 = baseb;\n LODWORD(i) = a4 - v37 + i;\n }\n if (v12 > v19) {\n v38 = v13;\n memcpy(&v13[(int)i], &a5[4 * v19], 4LL * (unsigned int)(v12 - 1 - v19) + 4);\n return v38;\n }\n return v13;\n}" + }, + { + "index": 108, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n// Compare function for qsort\n\nint compare(const void *a, const void *b) {\n\n int int_a = *(const int*) a;\n\n int int_b = *(const int*) b;\n\n return (int_a > int_b) - (int_a < int_b);\n\n}\n\n\n\n// Function to merge three sorted lists\n\n", + "func": "int *func0(int num1[], int size1, int num2[], int size2, int num3[], int size3,\n int *result_size) {\n qsort(num1, size1, sizeof(int), compare);\n qsort(num2, size2, sizeof(int), compare);\n qsort(num3, size3, sizeof(int), compare);\n *result_size = size1 + size2 + size3;\n int *result = malloc(*result_size * sizeof(int));\n if (!result) {\n perror(\"Failed to allocate memory\");\n exit(EXIT_FAILURE);\n }\n int i = 0, j = 0, k = 0, l = 0;\n while (i < size1 && j < size2 && k < size3) {\n if (num1[i] <= num2[j] && num1[i] <= num3[k]) {\n result[l++] = num1[i++];\n } else if (num2[j] <= num1[i] && num2[j] <= num3[k]) {\n result[l++] = num2[j++];\n } else {\n result[l++] = num3[k++];\n }\n }\n while (i < size1 && j < size2) {\n result[l++] = (num1[i] <= num2[j]) ? num1[i++] : num2[j++];\n }\n while (i < size1 && k < size3) {\n result[l++] = (num1[i] <= num3[k]) ? num1[i++] : num3[k++];\n }\n while (j < size2 && k < size3) {\n result[l++] = (num2[j] <= num3[k]) ? num2[j++] : num3[k++];\n }\n while (i < size1) {\n result[l++] = num1[i++];\n }\n while (j < size2) {\n result[l++] = num2[j++];\n }\n while (k < size3) {\n result[l++] = num3[k++];\n }\n return result;\n}", + "test": "int main() {\n\n // First test case\n\n int num1_1[] = {25, 24, 15, 4, 5, 29, 110};\n\n int size1_1 = sizeof(num1_1) / sizeof(num1_1[0]);\n\n int num2_1[] = {19, 20, 11, 56, 25, 233, 154};\n\n int size2_1 = sizeof(num2_1) / sizeof(num2_1[0]);\n\n int num3_1[] = {24, 26, 54, 48};\n\n int size3_1 = sizeof(num3_1) / sizeof(num3_1[0]);\n\n int expected1[] = {4, 5, 11, 15, 19, 20, 24, 24, 25, 25, 26, 29, 48, 54, 56, 110, 154, 233};\n\n int expected_size1 = sizeof(expected1) / sizeof(expected1[0]);\n\n int result_size1;\n\n int *result1 = func0(num1_1, size1_1, num2_1, size2_1, num3_1, size3_1, &result_size1);\n\n assert(result_size1 == expected_size1);\n\n for(int i = 0; i < expected_size1; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n free(result1);\n\n\n\n // Second test case\n\n int num1_2[] = {1, 3, 5, 6, 8, 9};\n\n int size1_2 = sizeof(num1_2) / sizeof(num1_2[0]);\n\n int num2_2[] = {2, 5, 7, 11};\n\n int size2_2 = sizeof(num2_2) / sizeof(num2_2[0]);\n\n int num3_2[] = {1, 4, 7, 8, 12};\n\n int size3_2 = sizeof(num3_2) / sizeof(num3_2[0]);\n\n int expected2[] = {1, 1, 2, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 11, 12};\n\n int expected_size2 = sizeof(expected2) / sizeof(expected2[0]);\n\n int result_size2;\n\n int *result2 = func0(num1_2, size1_2, num2_2, size2_2, num3_2, size3_2, &result_size2);\n\n assert(result_size2 == expected_size2);\n\n for(int i = 0; i < expected_size2; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n free(result2);\n\n\n\n // Third test case\n\n int num1_3[] = {18, 14, 10, 9, 8, 7, 9, 3, 2, 4, 1};\n\n int size1_3 = sizeof(num1_3) / sizeof(num1_3[0]);\n\n int num2_3[] = {25, 35, 22, 85, 14, 65, 75, 25, 58};\n\n int size2_3 = sizeof(num2_3) / sizeof(num2_3[0]);\n\n int num3_3[] = {12, 74, 9, 50, 61, 41};\n\n int size3_3 = sizeof(num3_3) / sizeof(num3_3[0]);\n\n int expected3[] = {1, 2, 3, 4, 7, 8, 9, 9, 9, 10, 12, 14, 14, 18, 22, 25, 25, 35, 41, 50, 58, 61, 65, 74, 75, 85};\n\n int expected_size3 = sizeof(expected3) / sizeof(expected3[0]);\n\n int result_size3;\n\n int *result3 = func0(num1_3, size1_3, num2_3, size2_3, num3_3, size3_3, &result_size3);\n\n assert(result_size3 == expected_size3);\n\n for(int i = 0; i < expected_size3; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmovslq %esi,%rsi\nmov %rdi,%r15\npush %r14\nmov %rdx,%r14\nmov $0x4,%edx\npush %r13\nmov %rsi,%r13\npush %r12\npush %rbp\nmov %r9d,%ebp\npush %rbx\nmov %ecx,%ebx\nsub $0x28,%rsp\nmov %ecx,0x4(%rsp)\nlea -0x53(%rip),%rcx\nmov %r8,0x8(%rsp)\nmov %r9d,0x10(%rsp)\ncallq 10d0 \nmovslq %ebx,%rsi\nmov $0x4,%edx\nmov %r14,%rdi\nlea -0x74(%rip),%rcx\ncallq 10d0 \nmov 0x8(%rsp),%r8\nmovslq %ebp,%rsi\nlea -0x88(%rip),%rcx\nmov $0x4,%edx\nmov %r8,%rdi\ncallq 10d0 \nmov 0x60(%rsp),%rax\nlea 0x0(%r13,%rbx,1),%edi\nadd %ebp,%edi\nmov %edi,(%rax)\nmovslq %edi,%rdi\nshl $0x2,%rdi\ncallq 1110 \ntest %rax,%rax\nje 1b33 \ntest %r13d,%r13d\nmov %rax,%r12\nmov 0x8(%rsp),%r8\nsetg %dl\ntest %ebx,%ebx\nsetg %r10b\ntest %ebp,%ebp\nmov %edx,%edi\nsetg %al\nmov %r10d,%esi\ntest %al,%r10b\nje 18f0 \ntest %dl,%dl\nje 18f0 \nmov 0x10(%rsp),%r11d\nmov $0x1,%edx\nxor %ebp,%ebp\nxor %r9d,%r9d\nxor %ecx,%ecx\njmp 18ad \nnopw 0x0(%rax,%rax,1)\ncmp %edi,%esi\njg 18e0 \nmov %esi,-0x4(%r12,%rdx,4)\nadd $0x1,%r9d\nnopl (%rax)\ncmp %r13d,%ecx\nsetl %dil\ncmp 0x4(%rsp),%r9d\nsetl %sil\nmov %edi,%r10d\nand %esi,%r10d\ncmp %r11d,%ebp\nsetl %al\nadd $0x1,%rdx\ntest %al,%al\nje 1900 \ntest %r10b,%r10b\nje 1980 \nmovslq %ecx,%rax\nmovslq %r9d,%rsi\nmovslq %ebp,%rdi\nmov %edx,%ebx\nmov (%r15,%rax,4),%eax\nmov (%r14,%rsi,4),%esi\nmov (%r8,%rdi,4),%edi\ncmp %esi,%eax\njg 1870 \ncmp %edi,%eax\njg 18e0 \nmov %eax,-0x4(%r12,%rdx,4)\nadd $0x1,%ecx\njmp 1880 \nnopw %cs:0x0(%rax,%rax,1)\nmov %edi,-0x4(%r12,%rdx,4)\nadd $0x1,%ebp\njmp 1880 \nnopw 0x0(%rax,%rax,1)\nand %edx,%r10d\nxor %ebx,%ebx\nxor %ebp,%ebp\nxor %r9d,%r9d\nxor %ecx,%ecx\nnopl 0x0(%rax)\ntest %r10b,%r10b\nje 1980 \nadd $0x1,%ebx\nmovslq %ecx,%r10\nmovslq %ebx,%rdx\nxchg %ax,%ax\nmovslq %r9d,%r11\nmov (%r15,%r10,4),%edi\nmov (%r14,%r11,4),%esi\ncmp %edi,%esi\njl 1956 \nadd $0x1,%ecx\nmov %edi,-0x4(%r12,%rdx,4)\nmov %edx,%ebx\ncmp %ecx,%r13d\nsetg %dil\ncmp %r9d,0x4(%rsp)\nsetg %sil\nadd $0x1,%rdx\ntest %sil,%sil\nje 1980 \ntest %dil,%dil\nje 1980 \nmovslq %ecx,%r10\nmov (%r14,%r11,4),%esi\nmov (%r15,%r10,4),%edi\ncmp %edi,%esi\njge 191f \nadd $0x1,%r9d\ncmp %ecx,%r13d\nmov %esi,-0x4(%r12,%rdx,4)\nmov %edx,%ebx\nsetg %dil\ncmp %r9d,0x4(%rsp)\nsetg %sil\nadd $0x1,%rdx\ntest %sil,%sil\nje 1980 \ntest %dil,%dil\njne 1910 \ntest %al,%al\nje 19f4 \ntest %dil,%dil\nje 19f4 \nadd $0x1,%ebx\nmovslq %ecx,%r10\nmovslq %ebx,%rdx\nnopw 0x0(%rax,%rax,1)\nmovslq %ebp,%rdi\nmov (%r15,%r10,4),%r11d\nmov (%r8,%rdi,4),%eax\ncmp %eax,%r11d\njg 19d6 \nadd $0x1,%ecx\ncmp %ebp,0x10(%rsp)\nmov %r11d,-0x4(%r12,%rdx,4)\nmov %edx,%ebx\nsetg %al\nadd $0x1,%rdx\ncmp %ecx,%r13d\njle 19f4 \ntest %al,%al\nje 19f4 \nmovslq %ecx,%r10\nmov (%r8,%rdi,4),%eax\nmov (%r15,%r10,4),%r11d\ncmp %eax,%r11d\njle 19a8 \nadd $0x1,%ebp\ncmp %ebp,0x10(%rsp)\nmov %eax,-0x4(%r12,%rdx,4)\nmov %edx,%ebx\nsetg %al\nadd $0x1,%rdx\ncmp %ecx,%r13d\njle 19f4 \ntest %al,%al\njne 1998 \ntest %sil,%sil\nje 1a65 \ntest %al,%al\nje 1a65 \nadd $0x1,%ebx\nmovslq %r9d,%r11\nmovslq %ebx,%rax\nnopw %cs:0x0(%rax,%rax,1)\nmovslq %ebp,%rdi\nmov (%r14,%r11,4),%esi\nmov (%r8,%rdi,4),%edx\ncmp %edx,%esi\njg 1a4a \nmov %esi,-0x4(%r12,%rax,4)\nmov %eax,%ebx\nadd $0x1,%r9d\nadd $0x1,%rax\ncmp %r9d,0x4(%rsp)\njle 1a65 \ncmp %ebp,0x10(%rsp)\njle 1a65 \nmovslq %r9d,%r11\nmov (%r8,%rdi,4),%edx\nmov (%r14,%r11,4),%esi\ncmp %edx,%esi\njle 1a1f \nmov %edx,-0x4(%r12,%rax,4)\nmov %eax,%ebx\nadd $0x1,%ebp\nadd $0x1,%rax\ncmp %r9d,0x4(%rsp)\njle 1a65 \ncmp %ebp,0x10(%rsp)\njg 1a10 \ncmp %ecx,%r13d\njle 1aad \nmovslq %ebx,%rax\nmov %r8,0x18(%rsp)\nlea (%r12,%rax,4),%rdi\nlea -0x1(%r13),%eax\nmov %r9d,0x14(%rsp)\nsub %ecx,%eax\nmov %ecx,0x8(%rsp)\nlea 0x4(,%rax,4),%rdx\nmovslq %ecx,%rax\nlea (%r15,%rax,4),%rsi\ncallq 1100 \nmov 0x8(%rsp),%ecx\nmov 0x18(%rsp),%r8\nmov 0x14(%rsp),%r9d\nsub %ecx,%r13d\nadd %r13d,%ebx\nmov 0x4(%rsp),%r15d\ncmp %r9d,%r15d\njle 1af5 \nmovslq %ebx,%rax\nmov %r8,0x8(%rsp)\nlea (%r12,%rax,4),%rdi\nlea -0x1(%r15),%eax\nmov %r9d,0x4(%rsp)\nsub %r9d,%eax\nlea 0x4(,%rax,4),%rdx\nmovslq %r9d,%rax\nlea (%r14,%rax,4),%rsi\ncallq 1100 \nmov 0x4(%rsp),%r9d\nmov %r15d,%ecx\nmov 0x8(%rsp),%r8\nsub %r9d,%ecx\nadd %ecx,%ebx\nmov 0x10(%rsp),%eax\ncmp %ebp,%eax\njle 1b21 \nsub $0x1,%eax\nmovslq %ebx,%rbx\nmov %eax,%r9d\nlea (%r12,%rbx,4),%rdi\nsub %ebp,%r9d\nmovslq %ebp,%rbp\nlea 0x4(,%r9,4),%rdx\nlea (%r8,%rbp,4),%rsi\ncallq 1100 \nadd $0x28,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nlea 0x4ca(%rip),%rdi\ncallq 1120 \nmov $0x1,%edi\ncallq 1130 \nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmovsxd rsi, esi; nmemb\nmov r15d, ecx\npush r14\nmov r14, rdx\npush r13\npush r12\npush rbp\npush rbx\nlea rbx, compare\nmov rcx, rbx; compar\nsub rsp, 38h\nmov [rsp+68h+var_60], rdx\nmov edx, 4; size\nmov dword ptr [rsp+68h+var_58], r9d\nmov [rsp+68h+base], r8\nmov dword ptr [rsp+68h+var_50], esi\nmov [rsp+68h+var_40], rdi\ncall _qsort\nmovsxd rsi, r15d; nmemb\nmov rcx, rbx; compar\nmov edx, 4; size\nmov rdi, r14; base\ncall _qsort\nmov rdi, [rsp+68h+base]; base\nmovsxd rsi, dword ptr [rsp+68h+var_58]; nmemb\nmov rcx, rbx; compar\nmov edx, 4; size\ncall _qsort\nmov r10d, dword ptr [rsp+68h+var_50]\nmov r9d, dword ptr [rsp+68h+var_58]\nmov rax, [rsp+68h+arg_0]\nlea edi, [r10+r15]\nadd edi, r9d\nmov [rax], edi\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\ntest rax, rax\njz func0_cold\nmov r10d, dword ptr [rsp+68h+var_50]\nmov r9d, dword ptr [rsp+68h+var_58]\nmov r14, rax\nmov r8, [rsp+68h+base]\nmov r11, [rsp+68h+var_40]\ntest r10d, r10d\nsetnle sil\ntest r15d, r15d\nsetnle dil\ntest r9d, r9d\nmov ecx, esi\nsetnle al\nmov edx, edi\ntest dil, al\njz loc_1860\ntest sil, sil\njz loc_1860\nmov ebx, 1\nxor ebp, ebp\nxor r13d, r13d\nxor r12d, r12d\njmp short loc_182B\nloc_17F0:\ncmp eax, ecx\njl short loc_1858\nadd r13d, 1\nmov eax, ecx\nnop word ptr [rax+rax+00h]\nloc_1800:\ncmp r12d, r10d\nmov [r14+rbx*4-4], eax\nlea rdi, [rbx+1]\nsetl cl\ncmp r13d, r15d\nsetl dl\nmov esi, edx\nand esi, ecx\ncmp ebp, r9d\nsetl al\ntest al, al\njz short loc_1870\ntest sil, sil\njz short loc_1870\nmov rbx, rdi\nloc_182B:\nmovsxd rax, r12d\nmov rdi, [rsp+68h+var_60]\nmov edx, [r11+rax*4]\nmovsxd rax, r13d\nmov ecx, [rdi+rax*4]\nmovsxd rax, ebp\nmov eax, [r8+rax*4]\ncmp ecx, edx\njl short loc_17F0\ncmp eax, edx\njl short loc_1858\nadd r12d, 1\nmov eax, edx\njmp short loc_1800\nloc_1858:\nadd ebp, 1\njmp short loc_1800\nloc_1860:\nand esi, edi\nxor ebx, ebx\nxor ebp, ebp\nxor r13d, r13d\nxor r12d, r12d\nnop dword ptr [rax+00h]\nloc_1870:\ntest sil, sil\njz loc_1901\nadd ebx, 1\nmov dword ptr [rsp+68h+var_58], ebp\nmovsxd rdi, r12d\nmov rbp, [rsp+68h+var_60]\nmov byte ptr [rsp+68h+var_50], al\nmovsxd rbx, ebx\nmovsxd rsi, r13d\njmp short loc_18BF\nloc_1898:\nadd r12d, 1\nmov [r14+rbx*4-4], edx\nlea rax, [rbx+1]\ncmp r10d, r12d\nsetnle cl\ncmp r15d, r13d\nsetnle dl\ntest dl, dl\njz short loc_18F8\ntest cl, cl\njz short loc_18F8\nmovsxd rdi, r12d\nloc_18BC:\nmov rbx, rax\nloc_18BF:\nmov edx, [r11+rdi*4]\nmov eax, [rbp+rsi*4+0]\ncmp eax, edx\njge short loc_1898\nadd r13d, 1\ncmp r10d, r12d\nmov [r14+rbx*4-4], eax\nlea rax, [rbx+1]\nsetnle cl\ncmp r15d, r13d\nsetnle dl\ntest cl, cl\njz short loc_18F8\ntest dl, dl\njz short loc_18F8\nmovsxd rsi, r13d\njmp short loc_18BC\nloc_18F8:\nmov ebp, dword ptr [rsp+68h+var_58]\nmovzx eax, byte ptr [rsp+68h+var_50]\nloc_1901:\ntest al, al\njz short loc_1970\ntest cl, cl\njz short loc_1970\nadd ebx, 1\nmovsxd rdi, r12d\nmovsxd rcx, ebp\nmovsxd rbx, ebx\njmp short loc_1942\nloc_1920:\nadd r12d, 1\ncmp ebp, r9d\nmov [r14+rbx*4-4], esi\nlea rsi, [rbx+1]\nsetl al\ncmp r10d, r12d\njle short loc_1970\ntest al, al\njz short loc_1970\nmovsxd rdi, r12d\nloc_193F:\nmov rbx, rsi\nloc_1942:\nmov esi, [r11+rdi*4]\nmov eax, [r8+rcx*4]\ncmp eax, esi\njge short loc_1920\nadd ebp, 1\nmov [r14+rbx*4-4], eax\nlea rsi, [rbx+1]\ncmp r9d, ebp\nsetnle al\ncmp r10d, r12d\njle short loc_1970\ntest al, al\njz short loc_1970\nmovsxd rcx, ebp\njmp short loc_193F\nloc_1970:\ntest dl, dl\njz short loc_19D8\ntest al, al\njz short loc_19D8\nadd ebx, 1\nmov rdi, [rsp+68h+var_60]\nmovsxd rsi, r13d\nmovsxd rcx, ebp\nmovsxd rbx, ebx\njmp short loc_19AD\nloc_1990:\nadd r13d, 1\nmov [r14+rbx*4-4], edx\nlea rax, [rbx+1]\ncmp r15d, r13d\njle short loc_19D8\ncmp r9d, ebp\njle short loc_19D8\nmovsxd rsi, r13d\nloc_19AA:\nmov rbx, rax\nloc_19AD:\nmov edx, [rdi+rsi*4]\nmov eax, [r8+rcx*4]\ncmp eax, edx\njge short loc_1990\nmov [r14+rbx*4-4], eax\nadd ebp, 1\nlea rax, [rbx+1]\ncmp r15d, r13d\njle short loc_19D8\ncmp r9d, ebp\njle short loc_19D8\nmovsxd rcx, ebp\njmp short loc_19AA\nloc_19D8:\ncmp r10d, r12d\njle short loc_1A23\nmovsxd rax, ebx\nmov dword ptr [rsp+68h+base], r9d\nlea rdi, [r14+rax*4]; dest\nlea eax, [r10-1]\nmov [rsp+68h+var_50], r8\nsub eax, r12d\nmov dword ptr [rsp+68h+var_58], r10d\nlea rdx, ds:4[rax*4]; n\nmovsxd rax, r12d\nlea rsi, [r11+rax*4]; src\ncall _memcpy\nmov r10d, dword ptr [rsp+68h+var_58]\nmov r9d, dword ptr [rsp+68h+base]\nmov r8, [rsp+68h+var_50]\nsub r10d, r12d\nadd ebx, r10d\nloc_1A23:\ncmp r15d, r13d\njle short loc_1A69\nmovsxd rax, ebx\nmov rcx, [rsp+68h+var_60]\nmov dword ptr [rsp+68h+var_50], r9d\nlea rdi, [r14+rax*4]; dest\nlea eax, [r15-1]\nmov [rsp+68h+var_58], r8\nsub r15d, r13d\nsub eax, r13d\nadd ebx, r15d\nlea rdx, ds:4[rax*4]; n\nmovsxd rax, r13d\nlea rsi, [rcx+rax*4]; src\ncall _memcpy\nmov r9d, dword ptr [rsp+68h+var_50]\nmov r8, [rsp+68h+var_58]\nloc_1A69:\ncmp r9d, ebp\njle short loc_1A90\nsub r9d, 1\nmovsxd rbx, ebx\nsub r9d, ebp\nmovsxd rbp, ebp\nlea rdi, [r14+rbx*4]; dest\nlea rdx, ds:4[r9*4]; n\nlea rsi, [r8+rbp*4]; src\ncall _memcpy\nloc_1A90:\nadd rsp, 38h\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(char *a1, int a2, char *a3, int a4, char *a5, int a6, _DWORD *a7)\n{\n int v9; // edi\n _DWORD *v10; // rax\n int v12; // r9d\n _DWORD *v13; // r14\n char *v14; // r8\n bool v15; // cl\n bool v16; // al\n bool v17; // dl\n __int64 i; // rbx\n int v19; // ebp\n int v20; // r13d\n int v21; // r12d\n int v22; // eax\n bool v23; // si\n int v24; // edx\n int v25; // ecx\n __int64 v26; // rdi\n __int64 v27; // rsi\n __int64 v28; // rax\n int v29; // edx\n int v30; // eax\n __int64 v31; // rdi\n __int64 v32; // rcx\n __int64 v33; // rsi\n int v34; // esi\n int v35; // eax\n __int64 v36; // rsi\n __int64 v37; // rcx\n __int64 v38; // rax\n int v39; // edx\n int v40; // eax\n char *v41; // rdi\n int v45; // [rsp+10h] [rbp-58h]\n char *v46; // [rsp+10h] [rbp-58h]\n bool v48; // [rsp+18h] [rbp-50h]\n char *v49; // [rsp+18h] [rbp-50h]\n int v50; // [rsp+18h] [rbp-50h]\n int basea; // [rsp+20h] [rbp-48h]\n\n qsort(a1, a2, 4uLL, compare);\n qsort(a3, a4, 4uLL, compare);\n qsort(a5, a6, 4uLL, compare);\n v9 = a6 + a2 + a4;\n *a7 = v9;\n v10 = malloc(4LL * v9);\n if ( !v10 )\n func0_cold();\n v12 = a6;\n v13 = v10;\n v14 = a5;\n v15 = a2 > 0;\n v16 = a6 > 0;\n v17 = a4 > 0;\n if ( a6 > 0 && a4 > 0 && a2 > 0 )\n {\n i = 1LL;\n v19 = 0;\n v20 = 0;\n v21 = 0;\n while ( 1 )\n {\n v24 = *(_DWORD *)&a1[4 * v21];\n v25 = *(_DWORD *)&a3[4 * v20];\n v22 = *(_DWORD *)&a5[4 * v19];\n if ( v25 < v24 )\n {\n if ( v22 < v25 )\n goto LABEL_13;\n ++v20;\n v22 = v25;\n }\n else\n {\n if ( v22 < v24 )\n {\nLABEL_13:\n ++v19;\n goto LABEL_7;\n }\n ++v21;\n v22 = v24;\n }\nLABEL_7:\n v13[i - 1] = v22;\n v15 = v21 < a2;\n v17 = v20 < a4;\n v23 = v21 < a2 && v20 < a4;\n v16 = v19 < a6;\n if ( v19 >= a6 || !v23 )\n goto LABEL_15;\n ++i;\n }\n }\n v23 = a4 > 0 && a2 > 0;\n LODWORD(i) = 0;\n v19 = 0;\n v20 = 0;\n v21 = 0;\nLABEL_15:\n if ( v23 )\n {\n v26 = v21;\n v48 = v16;\n i = (int)i + 1;\n v27 = v20;\n while ( 1 )\n {\n v29 = *(_DWORD *)&a1[4 * v26];\n v30 = *(_DWORD *)&a3[4 * v27];\n if ( v30 >= v29 )\n {\n ++v21;\n v13[i - 1] = v29;\n v28 = i + 1;\n v15 = a2 > v21;\n v17 = a4 > v20;\n if ( a4 <= v20 || a2 <= v21 )\n {\nLABEL_25:\n v16 = v48;\n break;\n }\n v26 = v21;\n }\n else\n {\n ++v20;\n v13[i - 1] = v30;\n v28 = i + 1;\n v15 = a2 > v21;\n v17 = a4 > v20;\n if ( a2 <= v21 || a4 <= v20 )\n goto LABEL_25;\n v27 = v20;\n }\n i = v28;\n }\n }\n if ( v16 && v15 )\n {\n v31 = v21;\n v32 = v19;\n for ( i = (int)i + 1; ; i = v33 )\n {\n v34 = *(_DWORD *)&a1[4 * v31];\n v35 = *(_DWORD *)&a5[4 * v32];\n if ( v35 >= v34 )\n {\n ++v21;\n v13[i - 1] = v34;\n v33 = i + 1;\n v16 = v19 < a6;\n if ( a2 <= v21 || v19 >= a6 )\n break;\n v31 = v21;\n }\n else\n {\n ++v19;\n v13[i - 1] = v35;\n v33 = i + 1;\n v16 = a6 > v19;\n if ( a2 <= v21 || a6 <= v19 )\n break;\n v32 = v19;\n }\n }\n }\n if ( v17 && v16 )\n {\n v36 = v20;\n v37 = v19;\n for ( i = (int)i + 1; ; i = v38 )\n {\n v39 = *(_DWORD *)&a3[4 * v36];\n v40 = *(_DWORD *)&a5[4 * v37];\n if ( v40 >= v39 )\n {\n ++v20;\n v13[i - 1] = v39;\n v38 = i + 1;\n if ( a4 <= v20 || a6 <= v19 )\n break;\n v36 = v20;\n }\n else\n {\n v13[i - 1] = v40;\n ++v19;\n v38 = i + 1;\n if ( a4 <= v20 || a6 <= v19 )\n break;\n v37 = v19;\n }\n }\n }\n if ( a2 > v21 )\n {\n basea = a6;\n v49 = v14;\n v45 = a2;\n memcpy(&v13[(int)i], &a1[4 * v21], 4LL * (unsigned int)(a2 - 1 - v21) + 4);\n v12 = basea;\n v14 = v49;\n LODWORD(i) = v45 - v21 + i;\n }\n if ( a4 > v20 )\n {\n v50 = v12;\n v41 = (char *)&v13[(int)i];\n v46 = v14;\n LODWORD(i) = a4 - v20 + i;\n memcpy(v41, &a3[4 * v20], 4LL * (unsigned int)(a4 - 1 - v20) + 4);\n v12 = v50;\n v14 = v46;\n }\n if ( v12 > v19 )\n memcpy(&v13[(int)i], &v14[4 * v19], 4LL * (unsigned int)(v12 - 1 - v19) + 4);\n return v13;\n}", + "ida_strip_asm": "sub_1700:\nendbr64\npush r15\nmovsxd rsi, esi; nmemb\nmov r15d, ecx\npush r14\nmov r14, rdx\npush r13\npush r12\npush rbp\npush rbx\nlea rbx, compar\nmov rcx, rbx; compar\nsub rsp, 38h\nmov [rsp+68h+var_60], rdx\nmov edx, 4; size\nmov dword ptr [rsp+68h+var_58], r9d\nmov [rsp+68h+base], r8\nmov dword ptr [rsp+68h+var_50], esi\nmov [rsp+68h+var_40], rdi\ncall _qsort\nmovsxd rsi, r15d; nmemb\nmov rcx, rbx; compar\nmov edx, 4; size\nmov rdi, r14; base\ncall _qsort\nmov rdi, [rsp+68h+base]; base\nmovsxd rsi, dword ptr [rsp+68h+var_58]; nmemb\nmov rcx, rbx; compar\nmov edx, 4; size\ncall _qsort\nmov r10d, dword ptr [rsp+68h+var_50]\nmov r9d, dword ptr [rsp+68h+var_58]\nmov rax, [rsp+68h+arg_0]\nlea edi, [r10+r15]\nadd edi, r9d\nmov [rax], edi\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\ntest rax, rax\njz loc_1140\nmov r10d, dword ptr [rsp+68h+var_50]\nmov r9d, dword ptr [rsp+68h+var_58]\nmov r14, rax\nmov r8, [rsp+68h+base]\nmov r11, [rsp+68h+var_40]\ntest r10d, r10d\nsetnle sil\ntest r15d, r15d\nsetnle dil\ntest r9d, r9d\nmov ecx, esi\nsetnle al\nmov edx, edi\ntest dil, al\njz loc_1860\ntest sil, sil\njz loc_1860\nmov ebx, 1\nxor ebp, ebp\nxor r13d, r13d\nxor r12d, r12d\njmp short loc_182B\nloc_17F0:\ncmp eax, ecx\njl short loc_1858\nadd r13d, 1\nmov eax, ecx\nnop word ptr [rax+rax+00h]\nloc_1800:\ncmp r12d, r10d\nmov [r14+rbx*4-4], eax\nlea rdi, [rbx+1]\nsetl cl\ncmp r13d, r15d\nsetl dl\nmov esi, edx\nand esi, ecx\ncmp ebp, r9d\nsetl al\ntest al, al\njz short loc_1870\ntest sil, sil\njz short loc_1870\nmov rbx, rdi\nloc_182B:\nmovsxd rax, r12d\nmov rdi, [rsp+68h+var_60]\nmov edx, [r11+rax*4]\nmovsxd rax, r13d\nmov ecx, [rdi+rax*4]\nmovsxd rax, ebp\nmov eax, [r8+rax*4]\ncmp ecx, edx\njl short loc_17F0\ncmp eax, edx\njl short loc_1858\nadd r12d, 1\nmov eax, edx\njmp short loc_1800\nloc_1858:\nadd ebp, 1\njmp short loc_1800\nloc_1860:\nand esi, edi\nxor ebx, ebx\nxor ebp, ebp\nxor r13d, r13d\nxor r12d, r12d\nnop dword ptr [rax+00h]\nloc_1870:\ntest sil, sil\njz loc_1901\nadd ebx, 1\nmov dword ptr [rsp+68h+var_58], ebp\nmovsxd rdi, r12d\nmov rbp, [rsp+68h+var_60]\nmov byte ptr [rsp+68h+var_50], al\nmovsxd rbx, ebx\nmovsxd rsi, r13d\njmp short loc_18BF\nloc_1898:\nadd r12d, 1\nmov [r14+rbx*4-4], edx\nlea rax, [rbx+1]\ncmp r10d, r12d\nsetnle cl\ncmp r15d, r13d\nsetnle dl\ntest dl, dl\njz short loc_18F8\ntest cl, cl\njz short loc_18F8\nmovsxd rdi, r12d\nloc_18BC:\nmov rbx, rax\nloc_18BF:\nmov edx, [r11+rdi*4]\nmov eax, [rbp+rsi*4+0]\ncmp eax, edx\njge short loc_1898\nadd r13d, 1\ncmp r10d, r12d\nmov [r14+rbx*4-4], eax\nlea rax, [rbx+1]\nsetnle cl\ncmp r15d, r13d\nsetnle dl\ntest cl, cl\njz short loc_18F8\ntest dl, dl\njz short loc_18F8\nmovsxd rsi, r13d\njmp short loc_18BC\nloc_18F8:\nmov ebp, dword ptr [rsp+68h+var_58]\nmovzx eax, byte ptr [rsp+68h+var_50]\nloc_1901:\ntest al, al\njz short loc_1970\ntest cl, cl\njz short loc_1970\nadd ebx, 1\nmovsxd rdi, r12d\nmovsxd rcx, ebp\nmovsxd rbx, ebx\njmp short loc_1942\nloc_1920:\nadd r12d, 1\ncmp ebp, r9d\nmov [r14+rbx*4-4], esi\nlea rsi, [rbx+1]\nsetl al\ncmp r10d, r12d\njle short loc_1970\ntest al, al\njz short loc_1970\nmovsxd rdi, r12d\nloc_193F:\nmov rbx, rsi\nloc_1942:\nmov esi, [r11+rdi*4]\nmov eax, [r8+rcx*4]\ncmp eax, esi\njge short loc_1920\nadd ebp, 1\nmov [r14+rbx*4-4], eax\nlea rsi, [rbx+1]\ncmp r9d, ebp\nsetnle al\ncmp r10d, r12d\njle short loc_1970\ntest al, al\njz short loc_1970\nmovsxd rcx, ebp\njmp short loc_193F\nloc_1970:\ntest dl, dl\njz short loc_19D8\ntest al, al\njz short loc_19D8\nadd ebx, 1\nmov rdi, [rsp+68h+var_60]\nmovsxd rsi, r13d\nmovsxd rcx, ebp\nmovsxd rbx, ebx\njmp short loc_19AD\nloc_1990:\nadd r13d, 1\nmov [r14+rbx*4-4], edx\nlea rax, [rbx+1]\ncmp r15d, r13d\njle short loc_19D8\ncmp r9d, ebp\njle short loc_19D8\nmovsxd rsi, r13d\nloc_19AA:\nmov rbx, rax\nloc_19AD:\nmov edx, [rdi+rsi*4]\nmov eax, [r8+rcx*4]\ncmp eax, edx\njge short loc_1990\nmov [r14+rbx*4-4], eax\nadd ebp, 1\nlea rax, [rbx+1]\ncmp r15d, r13d\njle short loc_19D8\ncmp r9d, ebp\njle short loc_19D8\nmovsxd rcx, ebp\njmp short loc_19AA\nloc_19D8:\ncmp r10d, r12d\njle short loc_1A23\nmovsxd rax, ebx\nmov dword ptr [rsp+68h+base], r9d\nlea rdi, [r14+rax*4]; dest\nlea eax, [r10-1]\nmov [rsp+68h+var_50], r8\nsub eax, r12d\nmov dword ptr [rsp+68h+var_58], r10d\nlea rdx, ds:4[rax*4]; n\nmovsxd rax, r12d\nlea rsi, [r11+rax*4]; src\ncall _memcpy\nmov r10d, dword ptr [rsp+68h+var_58]\nmov r9d, dword ptr [rsp+68h+base]\nmov r8, [rsp+68h+var_50]\nsub r10d, r12d\nadd ebx, r10d\nloc_1A23:\ncmp r15d, r13d\njle short loc_1A69\nmovsxd rax, ebx\nmov rcx, [rsp+68h+var_60]\nmov dword ptr [rsp+68h+var_50], r9d\nlea rdi, [r14+rax*4]; dest\nlea eax, [r15-1]\nmov [rsp+68h+var_58], r8\nsub r15d, r13d\nsub eax, r13d\nadd ebx, r15d\nlea rdx, ds:4[rax*4]; n\nmovsxd rax, r13d\nlea rsi, [rcx+rax*4]; src\ncall _memcpy\nmov r9d, dword ptr [rsp+68h+var_50]\nmov r8, [rsp+68h+var_58]\nloc_1A69:\ncmp r9d, ebp\njle short loc_1A90\nsub r9d, 1\nmovsxd rbx, ebx\nsub r9d, ebp\nmovsxd rbp, ebp\nlea rdi, [r14+rbx*4]; dest\nlea rdx, ds:4[r9*4]; n\nlea rsi, [r8+rbp*4]; src\ncall _memcpy\nloc_1A90:\nadd rsp, 38h\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1700(char *a1, int a2, char *a3, int a4, char *a5, int a6, _DWORD *a7)\n{\n int v9; // edi\n _DWORD *v10; // rax\n int v12; // r9d\n _DWORD *v13; // r14\n char *v14; // r8\n bool v15; // cl\n bool v16; // al\n bool v17; // dl\n __int64 i; // rbx\n int v19; // ebp\n int v20; // r13d\n int v21; // r12d\n int v22; // eax\n bool v23; // si\n int v24; // edx\n int v25; // ecx\n __int64 v26; // rdi\n __int64 v27; // rsi\n __int64 v28; // rax\n int v29; // edx\n int v30; // eax\n __int64 v31; // rdi\n __int64 v32; // rcx\n __int64 v33; // rsi\n int v34; // esi\n int v35; // eax\n __int64 v36; // rsi\n __int64 v37; // rcx\n __int64 v38; // rax\n int v39; // edx\n int v40; // eax\n char *v41; // rdi\n int v45; // [rsp+10h] [rbp-58h]\n char *v46; // [rsp+10h] [rbp-58h]\n bool v48; // [rsp+18h] [rbp-50h]\n char *v49; // [rsp+18h] [rbp-50h]\n int v50; // [rsp+18h] [rbp-50h]\n int basea; // [rsp+20h] [rbp-48h]\n\n qsort(a1, a2, 4uLL, compar);\n qsort(a3, a4, 4uLL, compar);\n qsort(a5, a6, 4uLL, compar);\n v9 = a6 + a2 + a4;\n *a7 = v9;\n v10 = malloc(4LL * v9);\n if ( !v10 )\n {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v12 = a6;\n v13 = v10;\n v14 = a5;\n v15 = a2 > 0;\n v16 = a6 > 0;\n v17 = a4 > 0;\n if ( a6 > 0 && a4 > 0 && a2 > 0 )\n {\n i = 1LL;\n v19 = 0;\n v20 = 0;\n v21 = 0;\n while ( 1 )\n {\n v24 = *(_DWORD *)&a1[4 * v21];\n v25 = *(_DWORD *)&a3[4 * v20];\n v22 = *(_DWORD *)&a5[4 * v19];\n if ( v25 < v24 )\n {\n if ( v22 < v25 )\n goto LABEL_13;\n ++v20;\n v22 = v25;\n }\n else\n {\n if ( v22 < v24 )\n {\nLABEL_13:\n ++v19;\n goto LABEL_7;\n }\n ++v21;\n v22 = v24;\n }\nLABEL_7:\n v13[i - 1] = v22;\n v15 = v21 < a2;\n v17 = v20 < a4;\n v23 = v21 < a2 && v20 < a4;\n v16 = v19 < a6;\n if ( v19 >= a6 || !v23 )\n goto LABEL_15;\n ++i;\n }\n }\n v23 = a4 > 0 && a2 > 0;\n LODWORD(i) = 0;\n v19 = 0;\n v20 = 0;\n v21 = 0;\nLABEL_15:\n if ( v23 )\n {\n v26 = v21;\n v48 = v16;\n i = (int)i + 1;\n v27 = v20;\n while ( 1 )\n {\n v29 = *(_DWORD *)&a1[4 * v26];\n v30 = *(_DWORD *)&a3[4 * v27];\n if ( v30 >= v29 )\n {\n ++v21;\n v13[i - 1] = v29;\n v28 = i + 1;\n v15 = a2 > v21;\n v17 = a4 > v20;\n if ( a4 <= v20 || a2 <= v21 )\n {\nLABEL_25:\n v16 = v48;\n break;\n }\n v26 = v21;\n }\n else\n {\n ++v20;\n v13[i - 1] = v30;\n v28 = i + 1;\n v15 = a2 > v21;\n v17 = a4 > v20;\n if ( a2 <= v21 || a4 <= v20 )\n goto LABEL_25;\n v27 = v20;\n }\n i = v28;\n }\n }\n if ( v16 && v15 )\n {\n v31 = v21;\n v32 = v19;\n for ( i = (int)i + 1; ; i = v33 )\n {\n v34 = *(_DWORD *)&a1[4 * v31];\n v35 = *(_DWORD *)&a5[4 * v32];\n if ( v35 >= v34 )\n {\n ++v21;\n v13[i - 1] = v34;\n v33 = i + 1;\n v16 = v19 < a6;\n if ( a2 <= v21 || v19 >= a6 )\n break;\n v31 = v21;\n }\n else\n {\n ++v19;\n v13[i - 1] = v35;\n v33 = i + 1;\n v16 = a6 > v19;\n if ( a2 <= v21 || a6 <= v19 )\n break;\n v32 = v19;\n }\n }\n }\n if ( v17 && v16 )\n {\n v36 = v20;\n v37 = v19;\n for ( i = (int)i + 1; ; i = v38 )\n {\n v39 = *(_DWORD *)&a3[4 * v36];\n v40 = *(_DWORD *)&a5[4 * v37];\n if ( v40 >= v39 )\n {\n ++v20;\n v13[i - 1] = v39;\n v38 = i + 1;\n if ( a4 <= v20 || a6 <= v19 )\n break;\n v36 = v20;\n }\n else\n {\n v13[i - 1] = v40;\n ++v19;\n v38 = i + 1;\n if ( a4 <= v20 || a6 <= v19 )\n break;\n v37 = v19;\n }\n }\n }\n if ( a2 > v21 )\n {\n basea = a6;\n v49 = v14;\n v45 = a2;\n memcpy(&v13[(int)i], &a1[4 * v21], 4LL * (unsigned int)(a2 - 1 - v21) + 4);\n v12 = basea;\n v14 = v49;\n LODWORD(i) = v45 - v21 + i;\n }\n if ( a4 > v20 )\n {\n v50 = v12;\n v41 = (char *)&v13[(int)i];\n v46 = v14;\n LODWORD(i) = a4 - v20 + i;\n memcpy(v41, &a3[4 * v20], 4LL * (unsigned int)(a4 - 1 - v20) + 4);\n v12 = v50;\n v14 = v46;\n }\n if ( v12 > v19 )\n memcpy(&v13[(int)i], &v14[4 * v19], 4LL * (unsigned int)(v12 - 1 - v19) + 4);\n return v13;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1700(char *a1, int a2, char *a3, int a4, char *a5, int a6,\n uint32_t *a7) {\n int v9;\n uint32_t *v10;\n int v12;\n uint32_t *v13;\n char *v14;\n bool v15;\n bool v16;\n bool v17;\n long long i;\n int v19;\n int v20;\n int v21;\n int v22;\n bool v23;\n int v24;\n int v25;\n long long v26;\n long long v27;\n long long v28;\n int v29;\n int v30;\n long long v31;\n long long v32;\n long long v33;\n int v34;\n int v35;\n long long v36;\n long long v37;\n long long v38;\n int v39;\n int v40;\n char *v41;\n int v45;\n char *v46;\n bool v48;\n char *v49;\n int v50;\n int basea;\n qsort(a1, a2, 4uLL, compar);\n qsort(a3, a4, 4uLL, compar);\n qsort(a5, a6, 4uLL, compar);\n v9 = a6 + a2 + a4;\n *a7 = v9;\n v10 = malloc(4LL * v9);\n if (!v10) {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v12 = a6;\n v13 = v10;\n v14 = a5;\n v15 = a2 > 0;\n v16 = a6 > 0;\n v17 = a4 > 0;\n if (a6 > 0 && a4 > 0 && a2 > 0) {\n i = 1LL;\n v19 = 0;\n v20 = 0;\n v21 = 0;\n while (1) {\n v24 = *(uint32_t *)&a1[4 * v21];\n v25 = *(uint32_t *)&a3[4 * v20];\n v22 = *(uint32_t *)&a5[4 * v19];\n if (v25 < v24) {\n if (v22 < v25) goto LABEL_13;\n ++v20;\n v22 = v25;\n } else {\n if (v22 < v24) {\n LABEL_13:\n ++v19;\n goto LABEL_7;\n }\n ++v21;\n v22 = v24;\n }\n LABEL_7:\n v13[i - 1] = v22;\n v15 = v21 < a2;\n v17 = v20 < a4;\n v23 = v21 < a2 && v20 < a4;\n v16 = v19 < a6;\n if (v19 >= a6 || !v23) goto LABEL_15;\n ++i;\n }\n }\n v23 = a4 > 0 && a2 > 0;\n LODWORD(i) = 0;\n v19 = 0;\n v20 = 0;\n v21 = 0;\nLABEL_15:\n if (v23) {\n v26 = v21;\n v48 = v16;\n i = (int)i + 1;\n v27 = v20;\n while (1) {\n v29 = *(uint32_t *)&a1[4 * v26];\n v30 = *(uint32_t *)&a3[4 * v27];\n if (v30 >= v29) {\n ++v21;\n v13[i - 1] = v29;\n v28 = i + 1;\n v15 = a2 > v21;\n v17 = a4 > v20;\n if (a4 <= v20 || a2 <= v21) {\n LABEL_25:\n v16 = v48;\n break;\n }\n v26 = v21;\n } else {\n ++v20;\n v13[i - 1] = v30;\n v28 = i + 1;\n v15 = a2 > v21;\n v17 = a4 > v20;\n if (a2 <= v21 || a4 <= v20) goto LABEL_25;\n v27 = v20;\n }\n i = v28;\n }\n }\n if (v16 && v15) {\n v31 = v21;\n v32 = v19;\n for (i = (int)i + 1;; i = v33) {\n v34 = *(uint32_t *)&a1[4 * v31];\n v35 = *(uint32_t *)&a5[4 * v32];\n if (v35 >= v34) {\n ++v21;\n v13[i - 1] = v34;\n v33 = i + 1;\n v16 = v19 < a6;\n if (a2 <= v21 || v19 >= a6) break;\n v31 = v21;\n } else {\n ++v19;\n v13[i - 1] = v35;\n v33 = i + 1;\n v16 = a6 > v19;\n if (a2 <= v21 || a6 <= v19) break;\n v32 = v19;\n }\n }\n }\n if (v17 && v16) {\n v36 = v20;\n v37 = v19;\n for (i = (int)i + 1;; i = v38) {\n v39 = *(uint32_t *)&a3[4 * v36];\n v40 = *(uint32_t *)&a5[4 * v37];\n if (v40 >= v39) {\n ++v20;\n v13[i - 1] = v39;\n v38 = i + 1;\n if (a4 <= v20 || a6 <= v19) break;\n v36 = v20;\n } else {\n v13[i - 1] = v40;\n ++v19;\n v38 = i + 1;\n if (a4 <= v20 || a6 <= v19) break;\n v37 = v19;\n }\n }\n }\n if (a2 > v21) {\n basea = a6;\n v49 = v14;\n v45 = a2;\n memcpy(&v13[(int)i], &a1[4 * v21], 4LL * (unsigned int)(a2 - 1 - v21) + 4);\n v12 = basea;\n v14 = v49;\n LODWORD(i) = v45 - v21 + i;\n }\n if (a4 > v20) {\n v50 = v12;\n v41 = (char *)&v13[(int)i];\n v46 = v14;\n LODWORD(i) = a4 - v20 + i;\n memcpy(v41, &a3[4 * v20], 4LL * (unsigned int)(a4 - 1 - v20) + 4);\n v12 = v50;\n v14 = v46;\n }\n if (v12 > v19)\n memcpy(&v13[(int)i], &v14[4 * v19],\n 4LL * (unsigned int)(v12 - 1 - v19) + 4);\n return v13;\n}", + "ida_pseudo_norm": "uint32_t *func0(char *a1, int a2, char *a3, int a4, char *a5, int a6,\n uint32_t *a7) {\n int v9;\n uint32_t *v10;\n int v12;\n uint32_t *v13;\n char *v14;\n bool v15;\n bool v16;\n bool v17;\n long long i;\n int v19;\n int v20;\n int v21;\n int v22;\n bool v23;\n int v24;\n int v25;\n long long v26;\n long long v27;\n long long v28;\n int v29;\n int v30;\n long long v31;\n long long v32;\n long long v33;\n int v34;\n int v35;\n long long v36;\n long long v37;\n long long v38;\n int v39;\n int v40;\n char *v41;\n int v45;\n char *v46;\n bool v48;\n char *v49;\n int v50;\n int basea;\n qsort(a1, a2, 4uLL, compare);\n qsort(a3, a4, 4uLL, compare);\n qsort(a5, a6, 4uLL, compare);\n v9 = a6 + a2 + a4;\n *a7 = v9;\n v10 = malloc(4LL * v9);\n if (!v10) func0_cold();\n v12 = a6;\n v13 = v10;\n v14 = a5;\n v15 = a2 > 0;\n v16 = a6 > 0;\n v17 = a4 > 0;\n if (a6 > 0 && a4 > 0 && a2 > 0) {\n i = 1LL;\n v19 = 0;\n v20 = 0;\n v21 = 0;\n while (1) {\n v24 = *(uint32_t *)&a1[4 * v21];\n v25 = *(uint32_t *)&a3[4 * v20];\n v22 = *(uint32_t *)&a5[4 * v19];\n if (v25 < v24) {\n if (v22 < v25) goto LABEL_13;\n ++v20;\n v22 = v25;\n } else {\n if (v22 < v24) {\n LABEL_13:\n ++v19;\n goto LABEL_7;\n }\n ++v21;\n v22 = v24;\n }\n LABEL_7:\n v13[i - 1] = v22;\n v15 = v21 < a2;\n v17 = v20 < a4;\n v23 = v21 < a2 && v20 < a4;\n v16 = v19 < a6;\n if (v19 >= a6 || !v23) goto LABEL_15;\n ++i;\n }\n }\n v23 = a4 > 0 && a2 > 0;\n LODWORD(i) = 0;\n v19 = 0;\n v20 = 0;\n v21 = 0;\nLABEL_15:\n if (v23) {\n v26 = v21;\n v48 = v16;\n i = (int)i + 1;\n v27 = v20;\n while (1) {\n v29 = *(uint32_t *)&a1[4 * v26];\n v30 = *(uint32_t *)&a3[4 * v27];\n if (v30 >= v29) {\n ++v21;\n v13[i - 1] = v29;\n v28 = i + 1;\n v15 = a2 > v21;\n v17 = a4 > v20;\n if (a4 <= v20 || a2 <= v21) {\n LABEL_25:\n v16 = v48;\n break;\n }\n v26 = v21;\n } else {\n ++v20;\n v13[i - 1] = v30;\n v28 = i + 1;\n v15 = a2 > v21;\n v17 = a4 > v20;\n if (a2 <= v21 || a4 <= v20) goto LABEL_25;\n v27 = v20;\n }\n i = v28;\n }\n }\n if (v16 && v15) {\n v31 = v21;\n v32 = v19;\n for (i = (int)i + 1;; i = v33) {\n v34 = *(uint32_t *)&a1[4 * v31];\n v35 = *(uint32_t *)&a5[4 * v32];\n if (v35 >= v34) {\n ++v21;\n v13[i - 1] = v34;\n v33 = i + 1;\n v16 = v19 < a6;\n if (a2 <= v21 || v19 >= a6) break;\n v31 = v21;\n } else {\n ++v19;\n v13[i - 1] = v35;\n v33 = i + 1;\n v16 = a6 > v19;\n if (a2 <= v21 || a6 <= v19) break;\n v32 = v19;\n }\n }\n }\n if (v17 && v16) {\n v36 = v20;\n v37 = v19;\n for (i = (int)i + 1;; i = v38) {\n v39 = *(uint32_t *)&a3[4 * v36];\n v40 = *(uint32_t *)&a5[4 * v37];\n if (v40 >= v39) {\n ++v20;\n v13[i - 1] = v39;\n v38 = i + 1;\n if (a4 <= v20 || a6 <= v19) break;\n v36 = v20;\n } else {\n v13[i - 1] = v40;\n ++v19;\n v38 = i + 1;\n if (a4 <= v20 || a6 <= v19) break;\n v37 = v19;\n }\n }\n }\n if (a2 > v21) {\n basea = a6;\n v49 = v14;\n v45 = a2;\n memcpy(&v13[(int)i], &a1[4 * v21], 4LL * (unsigned int)(a2 - 1 - v21) + 4);\n v12 = basea;\n v14 = v49;\n LODWORD(i) = v45 - v21 + i;\n }\n if (a4 > v20) {\n v50 = v12;\n v41 = (char *)&v13[(int)i];\n v46 = v14;\n LODWORD(i) = a4 - v20 + i;\n memcpy(v41, &a3[4 * v20], 4LL * (unsigned int)(a4 - 1 - v20) + 4);\n v12 = v50;\n v14 = v46;\n }\n if (v12 > v19)\n memcpy(&v13[(int)i], &v14[4 * v19],\n 4LL * (unsigned int)(v12 - 1 - v19) + 4);\n return v13;\n}" + }, + { + "index": 109, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(const char* s, int n) {\n int count = 0;\n for (int i = 0; i < n; i++) {\n if (s[i] == '1') {\n count = count + 1;\n }\n }\n return count;\n}", + "test": "int main() {\n\n assert(func0(\"011001\", 6) == 3);\n\n assert(func0(\"11011\", 5) == 4);\n\n assert(func0(\"1010\", 4) == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 1184 \nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x31,%al\njne 1180 \naddl $0x1,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1168 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_1184\nloc_1168:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 31h ; '1'\njnz short loc_1180\nadd [rbp+var_8], 1\nloc_1180:\nadd [rbp+var_4], 1\nloc_1184:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1168\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(_BYTE *)(i + a1) == 49 )\n ++v3;\n }\n return v3;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_1184\nloc_1168:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 31h ; '1'\njnz short loc_1180\nadd [rbp+var_8], 1\nloc_1180:\nadd [rbp+var_4], 1\nloc_1184:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1168\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(_BYTE *)(i + a1) == 49 )\n ++v3;\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(uint8_t *)(i + a1) == 49) ++v3;\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(uint8_t *)(i + a1) == 49) ++v3;\n }\n return v3;\n}" + }, + { + "index": 109, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(const char* s, int n) {\n int count = 0;\n for (int i = 0; i < n; i++) {\n if (s[i] == '1') {\n count = count + 1;\n }\n }\n return count;\n}", + "test": "int main() {\n\n assert(func0(\"011001\", 6) == 3);\n\n assert(func0(\"11011\", 5) == 4);\n\n assert(func0(\"1010\", 4) == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1178 \nmov %rdi,%rax\nlea -0x1(%rsi),%edx\nlea 0x1(%rdi,%rdx,1),%rsi\nmov $0x0,%edx\ncmpb $0x31,(%rax)\nsete %cl\nmovzbl %cl,%ecx\nadd %ecx,%edx\nadd $0x1,%rax\ncmp %rsi,%rax\njne 1161 \nmov %edx,%eax\nretq\nmov $0x0,%edx\njmp 1175 \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1176\nmov rax, rdi\nmovsxd rsi, esi\nadd rdi, rsi\nmov edx, 0\nloc_115F:\ncmp byte ptr [rax], 31h ; '1'\nsetz cl\nmovzx ecx, cl\nadd edx, ecx\nadd rax, 1\ncmp rax, rdi\njnz short loc_115F\nloc_1173:\nmov eax, edx\nretn\nloc_1176:\nmov edx, 0\njmp short loc_1173", + "ida_pseudo": "__int64 __fastcall func0(_BYTE *a1, int a2)\n{\n _BYTE *v2; // rax\n _BYTE *v3; // rdi\n unsigned int v4; // edx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n v4 += *v2++ == 49;\n while ( v2 != v3 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ntest esi, esi\njle short loc_1176\nmov rax, rdi\nmovsxd rsi, esi\nadd rdi, rsi\nmov edx, 0\nloc_115F:\ncmp byte ptr [rax], 31h ; '1'\nsetz cl\nmovzx ecx, cl\nadd edx, ecx\nadd rax, 1\ncmp rax, rdi\njnz short loc_115F\nloc_1173:\nmov eax, edx\nretn\nloc_1176:\nmov edx, 0\njmp short loc_1173", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(_BYTE *a1, int a2)\n{\n _BYTE *v2; // rax\n _BYTE *v3; // rdi\n unsigned int v4; // edx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n v4 += *v2++ == 49;\n while ( v2 != v3 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(uint8_t *a1, int a2) {\n uint8_t *v2;\n uint8_t *v3;\n unsigned int v4;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n v4 += *v2++ == 49;\n while (v2 != v3);\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(uint8_t *a1, int a2) {\n uint8_t *v2;\n uint8_t *v3;\n unsigned int v4;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n v4 += *v2++ == 49;\n while (v2 != v3);\n }\n return v4;\n}" + }, + { + "index": 110, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n} pair;\n\n\n\n", + "func": "pair* func0(pair test_list[], int test_size, int strt_val, int stop_val,\n int* res_size) {\n pair* res = NULL;\n *res_size = 0;\n for (int i = 0; i < test_size; i++) {\n if (test_list[i].first > strt_val) {\n res = realloc(res, (*res_size + 1) * sizeof(pair));\n res[*res_size].first = strt_val;\n res[*res_size].second = test_list[i].first;\n (*res_size)++;\n strt_val = test_list[i].second;\n }\n if (strt_val < stop_val) {\n res = realloc(res, (*res_size + 1) * sizeof(pair));\n res[*res_size].first = strt_val;\n res[*res_size].second = stop_val;\n (*res_size)++;\n }\n }\n return res;\n}", + "test": "int main() {\n\n // Test 1\n\n pair test1[] = { {6, 9}, {15, 34}, {48, 70} };\n\n int res_size1;\n\n pair* result1 = func0(test1, 3, 2, 100, &res_size1);\n\n pair expected1[] = { {2, 6}, {9, 100}, {9, 15}, {34, 100}, {34, 48}, {70, 100} };\n\n assert(res_size1 == 6);\n\n for(int i = 0; i < 6; i++) {\n\n assert(result1[i].first == expected1[i].first);\n\n assert(result1[i].second == expected1[i].second);\n\n }\n\n free(result1);\n\n\n\n // Test 2\n\n pair test2[] = { {7, 2}, {15, 19}, {38, 50} };\n\n int res_size2;\n\n pair* result2 = func0(test2, 3, 5, 60, &res_size2);\n\n pair expected2[] = { {5, 7}, {2, 60}, {2, 15}, {19, 60}, {19, 38}, {50, 60} };\n\n assert(res_size2 == 6);\n\n for(int i = 0; i < 6; i++) {\n\n assert(result2[i].first == expected2[i].first);\n\n assert(result2[i].second == expected2[i].second);\n\n }\n\n free(result2);\n\n\n\n // Test 3\n\n pair test3[] = { {7, 2}, {15, 19}, {38, 50} };\n\n int res_size3;\n\n pair* result3 = func0(test3, 3, 1, 52, &res_size3);\n\n pair expected3[] = { {1, 7}, {2, 52}, {2, 15}, {19, 52}, {19, 38}, {50, 52} };\n\n assert(res_size3 == 6);\n\n for(int i = 0; i < 6; i++) {\n\n assert(result3[i].first == expected3[i].first);\n\n assert(result3[i].second == expected3[i].second);\n\n }\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmov %ecx,-0x24(%rbp)\nmov %r8,-0x30(%rbp)\nmovq $0x0,-0x8(%rbp)\nmov -0x30(%rbp),%rax\nmovl $0x0,(%rax)\nmovl $0x0,-0xc(%rbp)\njmpq 1319 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x20(%rbp)\njge 129f \nmov -0x30(%rbp),%rax\nmov (%rax),%eax\nadd $0x1,%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x8(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\nmov -0x30(%rbp),%rax\nmov (%rax),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov -0x20(%rbp),%eax\nmov %eax,(%rdx)\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x30(%rbp),%rax\nmov (%rax),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,0x4(%rdx)\nmov -0x30(%rbp),%rax\nmov (%rax),%eax\nlea 0x1(%rax),%edx\nmov -0x30(%rbp),%rax\nmov %edx,(%rax)\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov 0x4(%rax),%eax\nmov %eax,-0x20(%rbp)\nmov -0x20(%rbp),%eax\ncmp -0x24(%rbp),%eax\njge 1315 \nmov -0x30(%rbp),%rax\nmov (%rax),%eax\nadd $0x1,%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x8(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\nmov -0x30(%rbp),%rax\nmov (%rax),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov -0x20(%rbp),%eax\nmov %eax,(%rdx)\nmov -0x30(%rbp),%rax\nmov (%rax),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov -0x24(%rbp),%eax\nmov %eax,0x4(%rdx)\nmov -0x30(%rbp),%rax\nmov (%rax),%eax\nlea 0x1(%rax),%edx\nmov -0x30(%rbp),%rax\nmov %edx,(%rax)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11e4 \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_24], ecx\nmov [rbp+var_30], r8\nmov [rbp+ptr], 0\nmov rax, [rbp+var_30]\nmov dword ptr [rax], 0\nmov [rbp+var_C], 0\njmp loc_1319\nloc_11E4:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njge loc_129F\nmov rax, [rbp+var_30]\nmov eax, [rax]\nadd eax, 1\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nmov rsi, rdx; size\nmov rdi, rax; ptr\ncall _realloc\nmov [rbp+ptr], rax\nmov rax, [rbp+var_30]\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov eax, [rbp+var_20]\nmov [rdx], eax\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov rax, [rbp+var_30]\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx+4], eax\nmov rax, [rbp+var_30]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_30]\nmov [rax], edx\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax+4]\nmov [rbp+var_20], eax\nloc_129F:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_24]\njge short loc_1315\nmov rax, [rbp+var_30]\nmov eax, [rax]\nadd eax, 1\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nmov rsi, rdx; size\nmov rdi, rax; ptr\ncall _realloc\nmov [rbp+ptr], rax\nmov rax, [rbp+var_30]\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov eax, [rbp+var_20]\nmov [rdx], eax\nmov rax, [rbp+var_30]\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov eax, [rbp+var_24]\nmov [rdx+4], eax\nmov rax, [rbp+var_30]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_30]\nmov [rax], edx\nloc_1315:\nadd [rbp+var_C], 1\nloc_1319:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl loc_11E4\nmov rax, [rbp+ptr]\nleave\nretn", + "ida_pseudo": "void *__fastcall func0(__int64 a1, int a2, int a3, int a4, int *a5)\n{\n int i; // [rsp+24h] [rbp-Ch]\n void *ptr; // [rsp+28h] [rbp-8h]\n\n ptr = 0LL;\n *a5 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( a3 < *(_DWORD *)(8LL * i + a1) )\n {\n ptr = realloc(ptr, 8LL * (*a5 + 1));\n *((_DWORD *)ptr + 2 * *a5) = a3;\n *((_DWORD *)ptr + 2 * (*a5)++ + 1) = *(_DWORD *)(8LL * i + a1);\n a3 = *(_DWORD *)(8LL * i + a1 + 4);\n }\n if ( a3 < a4 )\n {\n ptr = realloc(ptr, 8LL * (*a5 + 1));\n *((_DWORD *)ptr + 2 * *a5) = a3;\n *((_DWORD *)ptr + 2 * (*a5)++ + 1) = a4;\n }\n }\n return ptr;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_24], ecx\nmov [rbp+var_30], r8\nmov [rbp+ptr], 0\nmov rax, [rbp+var_30]\nmov dword ptr [rax], 0\nmov [rbp+var_C], 0\njmp loc_1319\nloc_11E4:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njge loc_129F\nmov rax, [rbp+var_30]\nmov eax, [rax]\nadd eax, 1\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nmov rsi, rdx; size\nmov rdi, rax; ptr\ncall _realloc\nmov [rbp+ptr], rax\nmov rax, [rbp+var_30]\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov eax, [rbp+var_20]\nmov [rdx], eax\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov rax, [rbp+var_30]\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx+4], eax\nmov rax, [rbp+var_30]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_30]\nmov [rax], edx\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax+4]\nmov [rbp+var_20], eax\nloc_129F:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_24]\njge short loc_1315\nmov rax, [rbp+var_30]\nmov eax, [rax]\nadd eax, 1\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nmov rsi, rdx; size\nmov rdi, rax; ptr\ncall _realloc\nmov [rbp+ptr], rax\nmov rax, [rbp+var_30]\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov eax, [rbp+var_20]\nmov [rdx], eax\nmov rax, [rbp+var_30]\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov eax, [rbp+var_24]\nmov [rdx+4], eax\nmov rax, [rbp+var_30]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_30]\nmov [rax], edx\nloc_1315:\nadd [rbp+var_C], 1\nloc_1319:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl loc_11E4\nmov rax, [rbp+ptr]\nleave\nretn", + "ida_strip_pseudo": "void *__fastcall sub_11A9(__int64 a1, int a2, int a3, int a4, int *a5)\n{\n int i; // [rsp+24h] [rbp-Ch]\n void *ptr; // [rsp+28h] [rbp-8h]\n\n ptr = 0LL;\n *a5 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( a3 < *(_DWORD *)(8LL * i + a1) )\n {\n ptr = realloc(ptr, 8LL * (*a5 + 1));\n *((_DWORD *)ptr + 2 * *a5) = a3;\n *((_DWORD *)ptr + 2 * (*a5)++ + 1) = *(_DWORD *)(8LL * i + a1);\n a3 = *(_DWORD *)(8LL * i + a1 + 4);\n }\n if ( a3 < a4 )\n {\n ptr = realloc(ptr, 8LL * (*a5 + 1));\n *((_DWORD *)ptr + 2 * *a5) = a3;\n *((_DWORD *)ptr + 2 * (*a5)++ + 1) = a4;\n }\n }\n return ptr;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_11A9(long long a1, int a2, int a3, int a4, int *a5) {\n int i;\n void *ptr;\n ptr = 0LL;\n *a5 = 0;\n for (i = 0; i < a2; ++i) {\n if (a3 < *(uint32_t *)(8LL * i + a1)) {\n ptr = realloc(ptr, 8LL * (*a5 + 1));\n *((uint32_t *)ptr + 2 * *a5) = a3;\n *((uint32_t *)ptr + 2 * (*a5)++ + 1) = *(uint32_t *)(8LL * i + a1);\n a3 = *(uint32_t *)(8LL * i + a1 + 4);\n }\n if (a3 < a4) {\n ptr = realloc(ptr, 8LL * (*a5 + 1));\n *((uint32_t *)ptr + 2 * *a5) = a3;\n *((uint32_t *)ptr + 2 * (*a5)++ + 1) = a4;\n }\n }\n return ptr;\n}", + "ida_pseudo_norm": "void *func0(long long a1, int a2, int a3, int a4, int *a5) {\n int i;\n void *ptr;\n ptr = 0LL;\n *a5 = 0;\n for (i = 0; i < a2; ++i) {\n if (a3 < *(uint32_t *)(8LL * i + a1)) {\n ptr = realloc(ptr, 8LL * (*a5 + 1));\n *((uint32_t *)ptr + 2 * *a5) = a3;\n *((uint32_t *)ptr + 2 * (*a5)++ + 1) = *(uint32_t *)(8LL * i + a1);\n a3 = *(uint32_t *)(8LL * i + a1 + 4);\n }\n if (a3 < a4) {\n ptr = realloc(ptr, 8LL * (*a5 + 1));\n *((uint32_t *)ptr + 2 * *a5) = a3;\n *((uint32_t *)ptr + 2 * (*a5)++ + 1) = a4;\n }\n }\n return ptr;\n}" + }, + { + "index": 110, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n} pair;\n\n\n\n", + "func": "pair* func0(pair test_list[], int test_size, int strt_val, int stop_val,\n int* res_size) {\n pair* res = NULL;\n *res_size = 0;\n for (int i = 0; i < test_size; i++) {\n if (test_list[i].first > strt_val) {\n res = realloc(res, (*res_size + 1) * sizeof(pair));\n res[*res_size].first = strt_val;\n res[*res_size].second = test_list[i].first;\n (*res_size)++;\n strt_val = test_list[i].second;\n }\n if (strt_val < stop_val) {\n res = realloc(res, (*res_size + 1) * sizeof(pair));\n res[*res_size].first = strt_val;\n res[*res_size].second = stop_val;\n (*res_size)++;\n }\n }\n return res;\n}", + "test": "int main() {\n\n // Test 1\n\n pair test1[] = { {6, 9}, {15, 34}, {48, 70} };\n\n int res_size1;\n\n pair* result1 = func0(test1, 3, 2, 100, &res_size1);\n\n pair expected1[] = { {2, 6}, {9, 100}, {9, 15}, {34, 100}, {34, 48}, {70, 100} };\n\n assert(res_size1 == 6);\n\n for(int i = 0; i < 6; i++) {\n\n assert(result1[i].first == expected1[i].first);\n\n assert(result1[i].second == expected1[i].second);\n\n }\n\n free(result1);\n\n\n\n // Test 2\n\n pair test2[] = { {7, 2}, {15, 19}, {38, 50} };\n\n int res_size2;\n\n pair* result2 = func0(test2, 3, 5, 60, &res_size2);\n\n pair expected2[] = { {5, 7}, {2, 60}, {2, 15}, {19, 60}, {19, 38}, {50, 60} };\n\n assert(res_size2 == 6);\n\n for(int i = 0; i < 6; i++) {\n\n assert(result2[i].first == expected2[i].first);\n\n assert(result2[i].second == expected2[i].second);\n\n }\n\n free(result2);\n\n\n\n // Test 3\n\n pair test3[] = { {7, 2}, {15, 19}, {38, 50} };\n\n int res_size3;\n\n pair* result3 = func0(test3, 3, 1, 52, &res_size3);\n\n pair expected3[] = { {1, 7}, {2, 52}, {2, 15}, {19, 52}, {19, 38}, {50, 52} };\n\n assert(res_size3 == 6);\n\n for(int i = 0; i < 6; i++) {\n\n assert(result3[i].first == expected3[i].first);\n\n assert(result3[i].second == expected3[i].second);\n\n }\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmovl $0x0,(%r8)\ntest %esi,%esi\njle 125d \npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %edx,%ebp\nmov %ecx,%r14d\nmov %r8,%r12\nmov %rdi,%rbx\nlea -0x1(%rsi),%eax\nlea 0x8(%rdi,%rax,8),%r15\nmov $0x0,%edi\njmp 124e \nmov (%r12),%eax\nlea 0x1(%rax),%esi\nmovslq %esi,%rsi\nshl $0x3,%rsi\ncallq 10b0 \nmov %rax,%rdi\nmov (%r12),%eax\nmovslq %eax,%rdx\nlea (%rdi,%rdx,8),%rdx\nmov %ebp,(%rdx)\nmov %r13d,0x4(%rdx)\nadd $0x1,%eax\nmov %eax,(%r12)\nmov 0x4(%rbx),%ebp\njmp 1256 \nmov (%r12),%eax\nlea 0x1(%rax),%esi\nmovslq %esi,%rsi\nshl $0x3,%rsi\ncallq 10b0 \nmov %rax,%rdi\nmov (%r12),%eax\nmovslq %eax,%rdx\nlea (%rdi,%rdx,8),%rdx\nmov %ebp,(%rdx)\nmov %r14d,0x4(%rdx)\nadd $0x1,%eax\nmov %eax,(%r12)\nadd $0x8,%rbx\ncmp %r15,%rbx\nje 1266 \nmov (%rbx),%r13d\ncmp %ebp,%r13d\njg 11e4 \ncmp %r14d,%ebp\njge 1245 \njmp 1217 \nmov $0x0,%edi\nmov %rdi,%rax\nretq\nmov %rdi,%rax\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\nmov dword ptr [r8], 0\ntest esi, esi\njle loc_125C\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov ebp, edx\nmov r14d, ecx\nmov r12, r8\nmov rbx, rdi\nmovsxd rsi, esi\nlea r15, [rdi+rsi*8]\nmov edi, 0; ptr\njmp short loc_121F\nloc_11E3:\nmov eax, [r12]\nlea esi, [rax+1]\nmovsxd rsi, esi\nshl rsi, 3; size\ncall _realloc\nmov rdi, rax; ptr\nmov eax, [r12]\nmovsxd rdx, eax\nlea rdx, [rdi+rdx*8]\nmov [rdx], ebp\nmov [rdx+4], r13d\nadd eax, 1\nmov [r12], eax\nmov ebp, [rbx+4]\njmp short loc_1227\nloc_1216:\nadd rbx, 8\ncmp rbx, r15\njz short loc_1265\nloc_121F:\nmov r13d, [rbx]\ncmp r13d, ebp\njg short loc_11E3\nloc_1227:\ncmp ebp, r14d\njge short loc_1216\nmov eax, [r12]\nlea esi, [rax+1]\nmovsxd rsi, esi\nshl rsi, 3; size\ncall _realloc\nmov rdi, rax\nmov eax, [r12]\nmovsxd rdx, eax\nlea rdx, [rdi+rdx*8]\nmov [rdx], ebp\nmov [rdx+4], r14d\nadd eax, 1\nmov [r12], eax\njmp short loc_1216\nloc_125C:\nmov edi, 0\nmov rax, rdi\nretn\nloc_1265:\nmov rax, rdi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "char *__fastcall func0(int *a1, int a2, int a3, int a4, int *a5)\n{\n int *v8; // rbx\n int *v9; // r15\n char *v10; // rdi\n int v11; // eax\n char *v12; // rdx\n int v13; // r13d\n int v14; // eax\n char *v15; // rdx\n\n *a5 = 0;\n if ( a2 <= 0 )\n return 0LL;\n v8 = a1;\n v9 = &a1[2 * a2];\n v10 = 0LL;\n do\n {\n v13 = *v8;\n if ( *v8 > a3 )\n {\n v10 = (char *)realloc(v10, 8LL * (*a5 + 1));\n v11 = *a5;\n v12 = &v10[8 * *a5];\n *(_DWORD *)v12 = a3;\n *((_DWORD *)v12 + 1) = v13;\n *a5 = v11 + 1;\n a3 = v8[1];\n }\n if ( a3 < a4 )\n {\n v10 = (char *)realloc(v10, 8LL * (*a5 + 1));\n v14 = *a5;\n v15 = &v10[8 * *a5];\n *(_DWORD *)v15 = a3;\n *((_DWORD *)v15 + 1) = a4;\n *a5 = v14 + 1;\n }\n v8 += 2;\n }\n while ( v8 != v9 );\n return v10;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\nmov dword ptr [r8], 0\ntest esi, esi\njle loc_125C\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov ebp, edx\nmov r14d, ecx\nmov r12, r8\nmov rbx, rdi\nmovsxd rsi, esi\nlea r15, [rdi+rsi*8]\nmov edi, 0; ptr\njmp short loc_121F\nloc_11E3:\nmov eax, [r12]\nlea esi, [rax+1]\nmovsxd rsi, esi\nshl rsi, 3; size\ncall _realloc\nmov rdi, rax; ptr\nmov eax, [r12]\nmovsxd rdx, eax\nlea rdx, [rdi+rdx*8]\nmov [rdx], ebp\nmov [rdx+4], r13d\nadd eax, 1\nmov [r12], eax\nmov ebp, [rbx+4]\njmp short loc_1227\nloc_1216:\nadd rbx, 8\ncmp rbx, r15\njz short loc_1265\nloc_121F:\nmov r13d, [rbx]\ncmp r13d, ebp\njg short loc_11E3\nloc_1227:\ncmp ebp, r14d\njge short loc_1216\nmov eax, [r12]\nlea esi, [rax+1]\nmovsxd rsi, esi\nshl rsi, 3; size\ncall _realloc\nmov rdi, rax\nmov eax, [r12]\nmovsxd rdx, eax\nlea rdx, [rdi+rdx*8]\nmov [rdx], ebp\nmov [rdx+4], r14d\nadd eax, 1\nmov [r12], eax\njmp short loc_1216\nloc_125C:\nmov edi, 0\nmov rax, rdi\nretn\nloc_1265:\nmov rax, rdi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11A9(int *a1, int a2, int a3, int a4, int *a5)\n{\n int *v8; // rbx\n int *v9; // r15\n char *v10; // rdi\n int v11; // eax\n char *v12; // rdx\n int v13; // r13d\n int v14; // eax\n char *v15; // rdx\n\n *a5 = 0;\n if ( a2 <= 0 )\n return 0LL;\n v8 = a1;\n v9 = &a1[2 * a2];\n v10 = 0LL;\n do\n {\n v13 = *v8;\n if ( *v8 > a3 )\n {\n v10 = (char *)realloc(v10, 8LL * (*a5 + 1));\n v11 = *a5;\n v12 = &v10[8 * *a5];\n *(_DWORD *)v12 = a3;\n *((_DWORD *)v12 + 1) = v13;\n *a5 = v11 + 1;\n a3 = v8[1];\n }\n if ( a3 < a4 )\n {\n v10 = (char *)realloc(v10, 8LL * (*a5 + 1));\n v14 = *a5;\n v15 = &v10[8 * *a5];\n *(_DWORD *)v15 = a3;\n *((_DWORD *)v15 + 1) = a4;\n *a5 = v14 + 1;\n }\n v8 += 2;\n }\n while ( v8 != v9 );\n return v10;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11A9(int *a1, int a2, int a3, int a4, int *a5) {\n int *v8;\n int *v9;\n char *v10;\n int v11;\n char *v12;\n int v13;\n int v14;\n char *v15;\n *a5 = 0;\n if (a2 <= 0) return 0LL;\n v8 = a1;\n v9 = &a1[2 * a2];\n v10 = 0LL;\n do {\n v13 = *v8;\n if (*v8 > a3) {\n v10 = (char *)realloc(v10, 8LL * (*a5 + 1));\n v11 = *a5;\n v12 = &v10[8 * *a5];\n *(uint32_t *)v12 = a3;\n *((uint32_t *)v12 + 1) = v13;\n *a5 = v11 + 1;\n a3 = v8[1];\n }\n if (a3 < a4) {\n v10 = (char *)realloc(v10, 8LL * (*a5 + 1));\n v14 = *a5;\n v15 = &v10[8 * *a5];\n *(uint32_t *)v15 = a3;\n *((uint32_t *)v15 + 1) = a4;\n *a5 = v14 + 1;\n }\n v8 += 2;\n } while (v8 != v9);\n return v10;\n}", + "ida_pseudo_norm": "char *func0(int *a1, int a2, int a3, int a4, int *a5) {\n int *v8;\n int *v9;\n char *v10;\n int v11;\n char *v12;\n int v13;\n int v14;\n char *v15;\n *a5 = 0;\n if (a2 <= 0) return 0LL;\n v8 = a1;\n v9 = &a1[2 * a2];\n v10 = 0LL;\n do {\n v13 = *v8;\n if (*v8 > a3) {\n v10 = (char *)realloc(v10, 8LL * (*a5 + 1));\n v11 = *a5;\n v12 = &v10[8 * *a5];\n *(uint32_t *)v12 = a3;\n *((uint32_t *)v12 + 1) = v13;\n *a5 = v11 + 1;\n a3 = v8[1];\n }\n if (a3 < a4) {\n v10 = (char *)realloc(v10, 8LL * (*a5 + 1));\n v14 = *a5;\n v15 = &v10[8 * *a5];\n *(uint32_t *)v15 = a3;\n *((uint32_t *)v15 + 1) = a4;\n *a5 = v14 + 1;\n }\n v8 += 2;\n } while (v8 != v9);\n return v10;\n}" + }, + { + "index": 110, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n} pair;\n\n\n\n", + "func": "pair* func0(pair test_list[], int test_size, int strt_val, int stop_val,\n int* res_size) {\n pair* res = NULL;\n *res_size = 0;\n for (int i = 0; i < test_size; i++) {\n if (test_list[i].first > strt_val) {\n res = realloc(res, (*res_size + 1) * sizeof(pair));\n res[*res_size].first = strt_val;\n res[*res_size].second = test_list[i].first;\n (*res_size)++;\n strt_val = test_list[i].second;\n }\n if (strt_val < stop_val) {\n res = realloc(res, (*res_size + 1) * sizeof(pair));\n res[*res_size].first = strt_val;\n res[*res_size].second = stop_val;\n (*res_size)++;\n }\n }\n return res;\n}", + "test": "int main() {\n\n // Test 1\n\n pair test1[] = { {6, 9}, {15, 34}, {48, 70} };\n\n int res_size1;\n\n pair* result1 = func0(test1, 3, 2, 100, &res_size1);\n\n pair expected1[] = { {2, 6}, {9, 100}, {9, 15}, {34, 100}, {34, 48}, {70, 100} };\n\n assert(res_size1 == 6);\n\n for(int i = 0; i < 6; i++) {\n\n assert(result1[i].first == expected1[i].first);\n\n assert(result1[i].second == expected1[i].second);\n\n }\n\n free(result1);\n\n\n\n // Test 2\n\n pair test2[] = { {7, 2}, {15, 19}, {38, 50} };\n\n int res_size2;\n\n pair* result2 = func0(test2, 3, 5, 60, &res_size2);\n\n pair expected2[] = { {5, 7}, {2, 60}, {2, 15}, {19, 60}, {19, 38}, {50, 60} };\n\n assert(res_size2 == 6);\n\n for(int i = 0; i < 6; i++) {\n\n assert(result2[i].first == expected2[i].first);\n\n assert(result2[i].second == expected2[i].second);\n\n }\n\n free(result2);\n\n\n\n // Test 3\n\n pair test3[] = { {7, 2}, {15, 19}, {38, 50} };\n\n int res_size3;\n\n pair* result3 = func0(test3, 3, 1, 52, &res_size3);\n\n pair expected3[] = { {1, 7}, {2, 52}, {2, 15}, {19, 52}, {19, 38}, {50, 52} };\n\n assert(res_size3 == 6);\n\n for(int i = 0; i < 6; i++) {\n\n assert(result3[i].first == expected3[i].first);\n\n assert(result3[i].second == expected3[i].second);\n\n }\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmovl $0x0,(%r8)\ntest %esi,%esi\njle 16d0 \npush %r15\nlea -0x1(%rsi),%eax\npush %r14\nmov %r8,%r14\npush %r13\nlea 0x8(%rdi,%rax,8),%r13\npush %r12\nmov %ecx,%r12d\npush %rbp\nmov %edx,%ebp\npush %rbx\nmov %rdi,%rbx\nxor %edi,%edi\nsub $0x8,%rsp\njmp 164e \nnopl 0x0(%rax,%rax,1)\ncmp %r12d,%ebp\njl 1689 \nadd $0x8,%rbx\ncmp %r13,%rbx\nje 16bd \nmov (%rbx),%r15d\ncmp %ebp,%r15d\njle 1640 \nmov (%r14),%eax\nlea 0x1(%rax),%esi\nmovslq %esi,%rsi\nshl $0x3,%rsi\ncallq 10b0 \nmovslq (%r14),%rdx\nmov %rax,%rdi\nmov %rdx,%rax\nlea (%rdi,%rdx,8),%rdx\nadd $0x1,%eax\nmov %ebp,(%rdx)\nmov %eax,(%r14)\nmov 0x4(%rbx),%ebp\nmov %r15d,0x4(%rdx)\ncmp %r12d,%ebp\njge 1645 \nmov (%r14),%eax\nadd $0x8,%rbx\nlea 0x1(%rax),%esi\nmovslq %esi,%rsi\nshl $0x3,%rsi\ncallq 10b0 \nmovslq (%r14),%rdx\nmov %rax,%rdi\nmov %rdx,%rax\nlea (%rdi,%rdx,8),%rdx\nadd $0x1,%eax\nmov %ebp,(%rdx)\nmov %r12d,0x4(%rdx)\nmov %eax,(%r14)\ncmp %r13,%rbx\njne 164e \nadd $0x8,%rsp\nmov %rdi,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nxor %edi,%edi\nmov %rdi,%rax\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmov dword ptr [r8], 0\ntest esi, esi\njle loc_15F0\npush r15\nmovsxd rsi, esi\npush r14\nmov r14, r8\npush r13\nmov r13d, ecx\npush r12\nlea r12, [rdi+rsi*8]\npush rbp\nmov ebp, edx\npush rbx\nmov rbx, rdi\nxor edi, edi; ptr\nsub rsp, 8\njmp short loc_155E\nloc_1550:\ncmp ebp, r13d\njl short loc_15A1\nloc_1555:\nadd rbx, 8\ncmp r12, rbx\njz short loc_15D5\nloc_155E:\nmov r15d, [rbx]\ncmp r15d, ebp\njle short loc_1550\nmov eax, [r14]\nlea esi, [rax+1]\nmovsxd rsi, esi\nshl rsi, 3; size\ncall _realloc\nmovsxd rdx, dword ptr [r14]\nmovd xmm0, ebp\nmovd xmm1, r15d\nmov rdi, rax; ptr\npunpckldq xmm0, xmm1\nmov rax, rdx\nmovq qword ptr [rdi+rdx*8], xmm0\nadd eax, 1\nmov [r14], eax\nmov ebp, [rbx+4]\ncmp ebp, r13d\njge short loc_1555\nloc_15A1:\nmov eax, [r14]\nadd rbx, 8\nlea esi, [rax+1]\nmovsxd rsi, esi\nshl rsi, 3; size\ncall _realloc\nmovsxd rdx, dword ptr [r14]\nmov rdi, rax\nmov rax, rdx\nlea rdx, [rdi+rdx*8]\nadd eax, 1\nmov [rdx], ebp\nmov [rdx+4], r13d\nmov [r14], eax\ncmp r12, rbx\njnz short loc_155E\nloc_15D5:\nadd rsp, 8\nmov rax, rdi\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15F0:\nxor eax, eax\nretn", + "ida_pseudo": "char *__fastcall func0(unsigned int *a1, int a2, signed int a3, signed int a4, int *a5)\n{\n unsigned int *v7; // r12\n unsigned int *v9; // rbx\n char *v10; // rdi\n unsigned int v11; // r15d\n int v12; // eax\n signed int *v13; // rdx\n int v14; // eax\n\n *a5 = 0;\n if ( a2 > 0 )\n {\n v7 = &a1[2 * a2];\n v9 = a1;\n v10 = 0LL;\n while ( 1 )\n {\n v11 = *v9;\n if ( (int)*v9 <= a3 )\n {\n if ( a3 >= a4 )\n goto LABEL_4;\nLABEL_7:\n v9 += 2;\n v10 = (char *)realloc(v10, 8LL * (*a5 + 1));\n v13 = (signed int *)&v10[8 * *a5];\n v14 = *a5 + 1;\n *v13 = a3;\n v13[1] = a4;\n *a5 = v14;\n if ( v7 == v9 )\n return v10;\n }\n else\n {\n v10 = (char *)realloc(v10, 8LL * (*a5 + 1));\n v12 = *a5;\n *(_QWORD *)&v10[8 * *a5] = _mm_unpacklo_epi32(_mm_cvtsi32_si128(a3), _mm_cvtsi32_si128(v11)).m128i_u64[0];\n *a5 = v12 + 1;\n a3 = v9[1];\n if ( a3 < a4 )\n goto LABEL_7;\nLABEL_4:\n v9 += 2;\n if ( v7 == v9 )\n return v10;\n }\n }\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1510:\nendbr64\nmov dword ptr [r8], 0\ntest esi, esi\njle loc_15F0\npush r15\nmovsxd rsi, esi\npush r14\nmov r14, r8\npush r13\nmov r13d, ecx\npush r12\nlea r12, [rdi+rsi*8]\npush rbp\nmov ebp, edx\npush rbx\nmov rbx, rdi\nxor edi, edi; ptr\nsub rsp, 8\njmp short loc_155E\nloc_1550:\ncmp ebp, r13d\njl short loc_15A1\nloc_1555:\nadd rbx, 8\ncmp r12, rbx\njz short loc_15D5\nloc_155E:\nmov r15d, [rbx]\ncmp r15d, ebp\njle short loc_1550\nmov eax, [r14]\nlea esi, [rax+1]\nmovsxd rsi, esi\nshl rsi, 3; size\ncall _realloc\nmovsxd rdx, dword ptr [r14]\nmovd xmm0, ebp\nmovd xmm1, r15d\nmov rdi, rax; ptr\npunpckldq xmm0, xmm1\nmov rax, rdx\nmovq qword ptr [rdi+rdx*8], xmm0\nadd eax, 1\nmov [r14], eax\nmov ebp, [rbx+4]\ncmp ebp, r13d\njge short loc_1555\nloc_15A1:\nmov eax, [r14]\nadd rbx, 8\nlea esi, [rax+1]\nmovsxd rsi, esi\nshl rsi, 3; size\ncall _realloc\nmovsxd rdx, dword ptr [r14]\nmov rdi, rax\nmov rax, rdx\nlea rdx, [rdi+rdx*8]\nadd eax, 1\nmov [rdx], ebp\nmov [rdx+4], r13d\nmov [r14], eax\ncmp r12, rbx\njnz short loc_155E\nloc_15D5:\nadd rsp, 8\nmov rax, rdi\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15F0:\nxor eax, eax\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1510(unsigned int *a1, int a2, signed int a3, signed int a4, int *a5)\n{\n unsigned int *v7; // r12\n unsigned int *v9; // rbx\n char *v10; // rdi\n unsigned int v11; // r15d\n int v12; // eax\n signed int *v13; // rdx\n int v14; // eax\n\n *a5 = 0;\n if ( a2 > 0 )\n {\n v7 = &a1[2 * a2];\n v9 = a1;\n v10 = 0LL;\n while ( 1 )\n {\n v11 = *v9;\n if ( (int)*v9 <= a3 )\n {\n if ( a3 >= a4 )\n goto LABEL_4;\nLABEL_7:\n v9 += 2;\n v10 = (char *)realloc(v10, 8LL * (*a5 + 1));\n v13 = (signed int *)&v10[8 * *a5];\n v14 = *a5 + 1;\n *v13 = a3;\n v13[1] = a4;\n *a5 = v14;\n if ( v7 == v9 )\n return v10;\n }\n else\n {\n v10 = (char *)realloc(v10, 8LL * (*a5 + 1));\n v12 = *a5;\n *(_QWORD *)&v10[8 * *a5] = _mm_unpacklo_epi32(_mm_cvtsi32_si128(a3), _mm_cvtsi32_si128(v11)).m128i_u64[0];\n *a5 = v12 + 1;\n a3 = v9[1];\n if ( a3 < a4 )\n goto LABEL_7;\nLABEL_4:\n v9 += 2;\n if ( v7 == v9 )\n return v10;\n }\n }\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1510(unsigned int *a1, int a2, signed int a3, signed int a4,\n int *a5) {\n unsigned int *v7;\n unsigned int *v9;\n char *v10;\n unsigned int v11;\n int v12;\n signed int *v13;\n int v14;\n *a5 = 0;\n if (a2 > 0) {\n v7 = &a1[2 * a2];\n v9 = a1;\n v10 = 0LL;\n while (1) {\n v11 = *v9;\n if ((int)*v9 <= a3) {\n if (a3 >= a4) goto LABEL_4;\n LABEL_7:\n v9 += 2;\n v10 = (char *)realloc(v10, 8LL * (*a5 + 1));\n v13 = (signed int *)&v10[8 * *a5];\n v14 = *a5 + 1;\n *v13 = a3;\n v13[1] = a4;\n *a5 = v14;\n if (v7 == v9) return v10;\n } else {\n v10 = (char *)realloc(v10, 8LL * (*a5 + 1));\n v12 = *a5;\n *(uint64_t *)&v10[8 * *a5] =\n _mm_unpacklo_epi32(_mm_cvtsi32_si128(a3), _mm_cvtsi32_si128(v11))\n .m128i_u64[0];\n *a5 = v12 + 1;\n a3 = v9[1];\n if (a3 < a4) goto LABEL_7;\n LABEL_4:\n v9 += 2;\n if (v7 == v9) return v10;\n }\n }\n }\n return 0LL;\n}", + "ida_pseudo_norm": "char *func0(unsigned int *a1, int a2, signed int a3, signed int a4, int *a5) {\n unsigned int *v7;\n unsigned int *v9;\n char *v10;\n unsigned int v11;\n int v12;\n signed int *v13;\n int v14;\n *a5 = 0;\n if (a2 > 0) {\n v7 = &a1[2 * a2];\n v9 = a1;\n v10 = 0LL;\n while (1) {\n v11 = *v9;\n if ((int)*v9 <= a3) {\n if (a3 >= a4) goto LABEL_4;\n LABEL_7:\n v9 += 2;\n v10 = (char *)realloc(v10, 8LL * (*a5 + 1));\n v13 = (signed int *)&v10[8 * *a5];\n v14 = *a5 + 1;\n *v13 = a3;\n v13[1] = a4;\n *a5 = v14;\n if (v7 == v9) return v10;\n } else {\n v10 = (char *)realloc(v10, 8LL * (*a5 + 1));\n v12 = *a5;\n *(uint64_t *)&v10[8 * *a5] =\n _mm_unpacklo_epi32(_mm_cvtsi32_si128(a3), _mm_cvtsi32_si128(v11))\n .m128i_u64[0];\n *a5 = v12 + 1;\n a3 = v9[1];\n if (a3 < a4) goto LABEL_7;\n LABEL_4:\n v9 += 2;\n if (v7 == v9) return v10;\n }\n }\n }\n return 0LL;\n}" + }, + { + "index": 110, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n} pair;\n\n\n\n", + "func": "pair* func0(pair test_list[], int test_size, int strt_val, int stop_val,\n int* res_size) {\n pair* res = NULL;\n *res_size = 0;\n for (int i = 0; i < test_size; i++) {\n if (test_list[i].first > strt_val) {\n res = realloc(res, (*res_size + 1) * sizeof(pair));\n res[*res_size].first = strt_val;\n res[*res_size].second = test_list[i].first;\n (*res_size)++;\n strt_val = test_list[i].second;\n }\n if (strt_val < stop_val) {\n res = realloc(res, (*res_size + 1) * sizeof(pair));\n res[*res_size].first = strt_val;\n res[*res_size].second = stop_val;\n (*res_size)++;\n }\n }\n return res;\n}", + "test": "int main() {\n\n // Test 1\n\n pair test1[] = { {6, 9}, {15, 34}, {48, 70} };\n\n int res_size1;\n\n pair* result1 = func0(test1, 3, 2, 100, &res_size1);\n\n pair expected1[] = { {2, 6}, {9, 100}, {9, 15}, {34, 100}, {34, 48}, {70, 100} };\n\n assert(res_size1 == 6);\n\n for(int i = 0; i < 6; i++) {\n\n assert(result1[i].first == expected1[i].first);\n\n assert(result1[i].second == expected1[i].second);\n\n }\n\n free(result1);\n\n\n\n // Test 2\n\n pair test2[] = { {7, 2}, {15, 19}, {38, 50} };\n\n int res_size2;\n\n pair* result2 = func0(test2, 3, 5, 60, &res_size2);\n\n pair expected2[] = { {5, 7}, {2, 60}, {2, 15}, {19, 60}, {19, 38}, {50, 60} };\n\n assert(res_size2 == 6);\n\n for(int i = 0; i < 6; i++) {\n\n assert(result2[i].first == expected2[i].first);\n\n assert(result2[i].second == expected2[i].second);\n\n }\n\n free(result2);\n\n\n\n // Test 3\n\n pair test3[] = { {7, 2}, {15, 19}, {38, 50} };\n\n int res_size3;\n\n pair* result3 = func0(test3, 3, 1, 52, &res_size3);\n\n pair expected3[] = { {1, 7}, {2, 52}, {2, 15}, {19, 52}, {19, 38}, {50, 52} };\n\n assert(res_size3 == 6);\n\n for(int i = 0; i < 6; i++) {\n\n assert(result3[i].first == expected3[i].first);\n\n assert(result3[i].second == expected3[i].second);\n\n }\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nmovl $0x0,(%r8)\ntest %esi,%esi\njle 1770 \npush %r15\nlea -0x1(%rsi),%eax\npush %r14\nmov %r8,%r14\npush %r13\nlea 0x8(%rdi,%rax,8),%r13\npush %r12\nmov %ecx,%r12d\npush %rbp\nmov %edx,%ebp\npush %rbx\nmov %rdi,%rbx\nxor %edi,%edi\nsub $0x8,%rsp\njmp 16ee \nnopl 0x0(%rax,%rax,1)\ncmp %r12d,%ebp\njl 1729 \nadd $0x8,%rbx\ncmp %r13,%rbx\nje 175d \nmov (%rbx),%r15d\ncmp %ebp,%r15d\njle 16e0 \nmov (%r14),%eax\nlea 0x1(%rax),%esi\nmovslq %esi,%rsi\nshl $0x3,%rsi\ncallq 10b0 \nmovslq (%r14),%rdx\nmov %rax,%rdi\nmov %rdx,%rax\nlea (%rdi,%rdx,8),%rdx\nadd $0x1,%eax\nmov %ebp,(%rdx)\nmov %eax,(%r14)\nmov 0x4(%rbx),%ebp\nmov %r15d,0x4(%rdx)\ncmp %r12d,%ebp\njge 16e5 \nmov (%r14),%eax\nadd $0x8,%rbx\nlea 0x1(%rax),%esi\nmovslq %esi,%rsi\nshl $0x3,%rsi\ncallq 10b0 \nmovslq (%r14),%rdx\nmov %rax,%rdi\nmov %rdx,%rax\nlea (%rdi,%rdx,8),%rdx\nadd $0x1,%eax\nmov %ebp,(%rdx)\nmov %r12d,0x4(%rdx)\nmov %eax,(%r14)\ncmp %r13,%rbx\njne 16ee \nadd $0x8,%rsp\nmov %rdi,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nxor %edi,%edi\nmov %rdi,%rax\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmov dword ptr [r8], 0\ntest esi, esi\njle loc_1600\npush r15\nmovsxd rsi, esi\npush r14\nmov r14, r8\npush r13\nmov r13d, ecx\npush r12\nlea r12, [rdi+rsi*8]\npush rbp\nmov ebp, edx\npush rbx\nmov rbx, rdi\nxor edi, edi; ptr\nsub rsp, 8\njmp short loc_156E\nloc_1560:\ncmp ebp, r13d\njl short loc_15B1\nloc_1565:\nadd rbx, 8\ncmp rbx, r12\njz short loc_15E5\nloc_156E:\nmov r15d, [rbx]\ncmp r15d, ebp\njle short loc_1560\nmov eax, [r14]\nlea esi, [rax+1]\nmovsxd rsi, esi\nshl rsi, 3; size\ncall _realloc\nmovsxd rdx, dword ptr [r14]\nmovd xmm0, ebp\nmovd xmm1, r15d\nmov rdi, rax; ptr\npunpckldq xmm0, xmm1\nmov rax, rdx\nmovq qword ptr [rdi+rdx*8], xmm0\nadd eax, 1\nmov [r14], eax\nmov ebp, [rbx+4]\ncmp ebp, r13d\njge short loc_1565\nloc_15B1:\nmov eax, [r14]\nadd rbx, 8\nlea esi, [rax+1]\nmovsxd rsi, esi\nshl rsi, 3; size\ncall _realloc\nmovsxd rdx, dword ptr [r14]\nmov rdi, rax\nmov rax, rdx\nlea rdx, [rdi+rdx*8]\nadd eax, 1\nmov [rdx], ebp\nmov [rdx+4], r13d\nmov [r14], eax\ncmp rbx, r12\njnz short loc_156E\nloc_15E5:\nadd rsp, 8\nmov rax, rdi\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1600:\nxor eax, eax\nretn", + "ida_pseudo": "char *__fastcall func0(unsigned int *a1, int a2, signed int a3, signed int a4, int *a5)\n{\n unsigned int *v7; // r12\n unsigned int *v9; // rbx\n char *v10; // rdi\n unsigned int v11; // r15d\n int v12; // eax\n signed int *v13; // rdx\n int v14; // eax\n\n *a5 = 0;\n if ( a2 > 0 )\n {\n v7 = &a1[2 * a2];\n v9 = a1;\n v10 = 0LL;\n while ( 1 )\n {\n v11 = *v9;\n if ( (int)*v9 <= a3 )\n {\n if ( a3 >= a4 )\n goto LABEL_4;\nLABEL_7:\n v9 += 2;\n v10 = (char *)realloc(v10, 8LL * (*a5 + 1));\n v13 = (signed int *)&v10[8 * *a5];\n v14 = *a5 + 1;\n *v13 = a3;\n v13[1] = a4;\n *a5 = v14;\n if ( v9 == v7 )\n return v10;\n }\n else\n {\n v10 = (char *)realloc(v10, 8LL * (*a5 + 1));\n v12 = *a5;\n *(_QWORD *)&v10[8 * *a5] = _mm_unpacklo_epi32(_mm_cvtsi32_si128(a3), _mm_cvtsi32_si128(v11)).m128i_u64[0];\n *a5 = v12 + 1;\n a3 = v9[1];\n if ( a3 < a4 )\n goto LABEL_7;\nLABEL_4:\n v9 += 2;\n if ( v9 == v7 )\n return v10;\n }\n }\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1520:\nendbr64\nmov dword ptr [r8], 0\ntest esi, esi\njle loc_1600\npush r15\nmovsxd rsi, esi\npush r14\nmov r14, r8\npush r13\nmov r13d, ecx\npush r12\nlea r12, [rdi+rsi*8]\npush rbp\nmov ebp, edx\npush rbx\nmov rbx, rdi\nxor edi, edi; ptr\nsub rsp, 8\njmp short loc_156E\nloc_1560:\ncmp ebp, r13d\njl short loc_15B1\nloc_1565:\nadd rbx, 8\ncmp rbx, r12\njz short loc_15E5\nloc_156E:\nmov r15d, [rbx]\ncmp r15d, ebp\njle short loc_1560\nmov eax, [r14]\nlea esi, [rax+1]\nmovsxd rsi, esi\nshl rsi, 3; size\ncall _realloc\nmovsxd rdx, dword ptr [r14]\nmovd xmm0, ebp\nmovd xmm1, r15d\nmov rdi, rax; ptr\npunpckldq xmm0, xmm1\nmov rax, rdx\nmovq qword ptr [rdi+rdx*8], xmm0\nadd eax, 1\nmov [r14], eax\nmov ebp, [rbx+4]\ncmp ebp, r13d\njge short loc_1565\nloc_15B1:\nmov eax, [r14]\nadd rbx, 8\nlea esi, [rax+1]\nmovsxd rsi, esi\nshl rsi, 3; size\ncall _realloc\nmovsxd rdx, dword ptr [r14]\nmov rdi, rax\nmov rax, rdx\nlea rdx, [rdi+rdx*8]\nadd eax, 1\nmov [rdx], ebp\nmov [rdx+4], r13d\nmov [r14], eax\ncmp rbx, r12\njnz short loc_156E\nloc_15E5:\nadd rsp, 8\nmov rax, rdi\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1600:\nxor eax, eax\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1520(unsigned int *a1, int a2, signed int a3, signed int a4, int *a5)\n{\n unsigned int *v7; // r12\n unsigned int *v9; // rbx\n char *v10; // rdi\n unsigned int v11; // r15d\n int v12; // eax\n signed int *v13; // rdx\n int v14; // eax\n\n *a5 = 0;\n if ( a2 > 0 )\n {\n v7 = &a1[2 * a2];\n v9 = a1;\n v10 = 0LL;\n while ( 1 )\n {\n v11 = *v9;\n if ( (int)*v9 <= a3 )\n {\n if ( a3 >= a4 )\n goto LABEL_4;\nLABEL_7:\n v9 += 2;\n v10 = (char *)realloc(v10, 8LL * (*a5 + 1));\n v13 = (signed int *)&v10[8 * *a5];\n v14 = *a5 + 1;\n *v13 = a3;\n v13[1] = a4;\n *a5 = v14;\n if ( v9 == v7 )\n return v10;\n }\n else\n {\n v10 = (char *)realloc(v10, 8LL * (*a5 + 1));\n v12 = *a5;\n *(_QWORD *)&v10[8 * *a5] = _mm_unpacklo_epi32(_mm_cvtsi32_si128(a3), _mm_cvtsi32_si128(v11)).m128i_u64[0];\n *a5 = v12 + 1;\n a3 = v9[1];\n if ( a3 < a4 )\n goto LABEL_7;\nLABEL_4:\n v9 += 2;\n if ( v9 == v7 )\n return v10;\n }\n }\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1520(unsigned int *a1, int a2, signed int a3, signed int a4,\n int *a5) {\n unsigned int *v7;\n unsigned int *v9;\n char *v10;\n unsigned int v11;\n int v12;\n signed int *v13;\n int v14;\n *a5 = 0;\n if (a2 > 0) {\n v7 = &a1[2 * a2];\n v9 = a1;\n v10 = 0LL;\n while (1) {\n v11 = *v9;\n if ((int)*v9 <= a3) {\n if (a3 >= a4) goto LABEL_4;\n LABEL_7:\n v9 += 2;\n v10 = (char *)realloc(v10, 8LL * (*a5 + 1));\n v13 = (signed int *)&v10[8 * *a5];\n v14 = *a5 + 1;\n *v13 = a3;\n v13[1] = a4;\n *a5 = v14;\n if (v9 == v7) return v10;\n } else {\n v10 = (char *)realloc(v10, 8LL * (*a5 + 1));\n v12 = *a5;\n *(uint64_t *)&v10[8 * *a5] =\n _mm_unpacklo_epi32(_mm_cvtsi32_si128(a3), _mm_cvtsi32_si128(v11))\n .m128i_u64[0];\n *a5 = v12 + 1;\n a3 = v9[1];\n if (a3 < a4) goto LABEL_7;\n LABEL_4:\n v9 += 2;\n if (v9 == v7) return v10;\n }\n }\n }\n return 0LL;\n}", + "ida_pseudo_norm": "char *func0(unsigned int *a1, int a2, signed int a3, signed int a4, int *a5) {\n unsigned int *v7;\n unsigned int *v9;\n char *v10;\n unsigned int v11;\n int v12;\n signed int *v13;\n int v14;\n *a5 = 0;\n if (a2 > 0) {\n v7 = &a1[2 * a2];\n v9 = a1;\n v10 = 0LL;\n while (1) {\n v11 = *v9;\n if ((int)*v9 <= a3) {\n if (a3 >= a4) goto LABEL_4;\n LABEL_7:\n v9 += 2;\n v10 = (char *)realloc(v10, 8LL * (*a5 + 1));\n v13 = (signed int *)&v10[8 * *a5];\n v14 = *a5 + 1;\n *v13 = a3;\n v13[1] = a4;\n *a5 = v14;\n if (v9 == v7) return v10;\n } else {\n v10 = (char *)realloc(v10, 8LL * (*a5 + 1));\n v12 = *a5;\n *(uint64_t *)&v10[8 * *a5] =\n _mm_unpacklo_epi32(_mm_cvtsi32_si128(a3), _mm_cvtsi32_si128(v11))\n .m128i_u64[0];\n *a5 = v12 + 1;\n a3 = v9[1];\n if (a3 < a4) goto LABEL_7;\n LABEL_4:\n v9 += 2;\n if (v9 == v7) return v10;\n }\n }\n }\n return 0LL;\n}" + }, + { + "index": 111, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n// Function to compare integers for qsort\n\nint cmpfunc(const void *a, const void *b) {\n\n return (*(int*)a - *(int*)b);\n\n}\n\n\n\n// Function to find common elements in nested lists\n\n", + "func": "int *func0(int **nestedlist, int num_lists, int *sizes, int *result_size) {\n if (num_lists == 0) {\n *result_size = 0;\n return NULL;\n }\n for (int i = 0; i < num_lists; i++) {\n qsort(nestedlist[i], sizes[i], sizeof(int), cmpfunc);\n }\n int *temp = malloc(sizes[0] * sizeof(int));\n int temp_size = 0;\n for (int i = 0; i < sizes[0]; i++) {\n if (i == 0 || nestedlist[0][i] != nestedlist[0][i - 1]) {\n temp[temp_size++] = nestedlist[0][i];\n }\n }\n for (int i = 1; i < num_lists; i++) {\n int *new_temp = malloc(temp_size * sizeof(int));\n int new_size = 0;\n int j = 0, k = 0;\n while (j < temp_size && k < sizes[i]) {\n if (temp[j] < nestedlist[i][k]) {\n j++;\n }\n else if (temp[j] > nestedlist[i][k]) {\n k++;\n }\n else {\n new_temp[new_size++] = temp[j];\n j++;\n k++;\n }\n }\n free(temp);\n temp = new_temp;\n temp_size = new_size;\n if (temp_size == 0) break;\n }\n *result_size = temp_size;\n return temp;\n}", + "test": "int main() {\n\n // First test case\n\n int list1_1[] = {12, 18, 23, 25, 45};\n\n int list1_2[] = {7, 12, 18, 24, 28};\n\n int list1_3[] = {1, 5, 8, 12, 15, 16, 18};\n\n int *nested1[] = {list1_1, list1_2, list1_3};\n\n int sizes1[] = {5, 5, 7};\n\n int result_size1;\n\n int *result1 = func0(nested1, 3, sizes1, &result_size1);\n\n qsort(result1, result_size1, sizeof(int), cmpfunc);\n\n assert(result_size1 == 2 && result1[0] == 12 && result1[1] == 18);\n\n free(result1);\n\n\n\n // Second test case\n\n int list2_1[] = {12, 5, 23, 25, 45};\n\n int list2_2[] = {7, 11, 5, 23, 28};\n\n int list2_3[] = {1, 5, 8, 18, 23, 16};\n\n int *nested2[] = {list2_1, list2_2, list2_3};\n\n int sizes2[] = {5, 5, 6};\n\n int result_size2;\n\n int *result2 = func0(nested2, 3, sizes2, &result_size2);\n\n qsort(result2, result_size2, sizeof(int), cmpfunc);\n\n assert(result_size2 == 2 && result2[0] == 5 && result2[1] == 23);\n\n free(result2);\n\n\n\n // Third test case\n\n int list3_1[] = {2, 3, 4, 1};\n\n int list3_2[] = {4, 5};\n\n int list3_3[] = {6, 4, 8};\n\n int list3_4[] = {4, 5};\n\n int list3_5[] = {6, 8, 4};\n\n int *nested3[] = {list3_1, list3_2, list3_3, list3_4, list3_5};\n\n int sizes3[] = {4, 2, 3, 2, 3};\n\n int result_size3;\n\n int *result3 = func0(nested3, 5, sizes3, &result_size3);\n\n qsort(result3, result_size3, sizeof(int), cmpfunc);\n\n assert(result_size3 == 1 && result3[0] == 4);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x50,%rsp\nmov %rdi,-0x38(%rbp)\nmov %esi,-0x3c(%rbp)\nmov %rdx,-0x48(%rbp)\nmov %rcx,-0x50(%rbp)\ncmpl $0x0,-0x3c(%rbp)\njne 1220 \nmov -0x50(%rbp),%rax\nmovl $0x0,(%rax)\nmov $0x0,%eax\njmpq 1489 \nmovl $0x0,-0x2c(%rbp)\njmp 1271 \nmov -0x2c(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmovslq %eax,%rsi\nmov -0x2c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nlea -0x97(%rip),%rcx\nmov $0x4,%edx\nmov %rax,%rdi\ncallq 10a0 \naddl $0x1,-0x2c(%rbp)\nmov -0x2c(%rbp),%eax\ncmp -0x3c(%rbp),%eax\njl 1229 \nmov -0x48(%rbp),%rax\nmov (%rax),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,-0x10(%rbp)\nmovl $0x0,-0x28(%rbp)\nmovl $0x0,-0x24(%rbp)\njmp 1312 \ncmpl $0x0,-0x24(%rbp)\nje 12db \nmov -0x38(%rbp),%rax\nmov (%rax),%rax\nmov -0x24(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x2,%rdx\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x38(%rbp),%rax\nmov (%rax),%rax\nmov -0x24(%rbp),%ecx\nmovslq %ecx,%rcx\nshl $0x2,%rcx\nsub $0x4,%rcx\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\nje 130e \nmov -0x38(%rbp),%rax\nmov (%rax),%rax\nmov -0x24(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x2,%rdx\nlea (%rax,%rdx,1),%rcx\nmov -0x28(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x28(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x10(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x24(%rbp)\nmov -0x48(%rbp),%rax\nmov (%rax),%eax\ncmp %eax,-0x24(%rbp)\njl 12a1 \nmovl $0x1,-0x20(%rbp)\njmpq 146d \nmov -0x28(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0x1c(%rbp)\nmovl $0x0,-0x18(%rbp)\nmovl $0x0,-0x14(%rbp)\njmpq 1422 \nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x10(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x20(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x38(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%rax\nmov -0x14(%rbp),%ecx\nmovslq %ecx,%rcx\nshl $0x2,%rcx\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njge 13a1 \naddl $0x1,-0x18(%rbp)\njmpq 1422 \nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x10(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x20(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x38(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%rax\nmov -0x14(%rbp),%ecx\nmovslq %ecx,%rcx\nshl $0x2,%rcx\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njle 13e7 \naddl $0x1,-0x14(%rbp)\njmp 1422 \nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x10(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x1c(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x1c(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x18(%rbp)\naddl $0x1,-0x14(%rbp)\nmov -0x18(%rbp),%eax\ncmp -0x28(%rbp),%eax\njge 1449 \nmov -0x20(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x14(%rbp)\njl 1358 \nmov -0x10(%rbp),%rax\nmov %rax,%rdi\ncallq 1090 \nmov -0x8(%rbp),%rax\nmov %rax,-0x10(%rbp)\nmov -0x1c(%rbp),%eax\nmov %eax,-0x28(%rbp)\ncmpl $0x0,-0x28(%rbp)\nje 147b \naddl $0x1,-0x20(%rbp)\nmov -0x20(%rbp),%eax\ncmp -0x3c(%rbp),%eax\njl 1329 \njmp 147c \nmov -0x50(%rbp),%rax\nmov -0x28(%rbp),%edx\nmov %edx,(%rax)\nmov -0x10(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov [rbp+var_48], rdx\nmov [rbp+var_50], rcx\ncmp [rbp+var_3C], 0\njnz short loc_1220\nmov rax, [rbp+var_50]\nmov dword ptr [rax], 0\nmov eax, 0\njmp locret_148C\nloc_1220:\nmov [rbp+var_2C], 0\njmp short loc_1274\nloc_1229:\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax]\nmovsxd rsi, eax; nmemb\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nlea rdx, cmpfunc\nmov rcx, rdx; compar\nmov edx, 4; size\nmov rdi, rax; base\ncall _qsort\nadd [rbp+var_2C], 1\nloc_1274:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_3C]\njl short loc_1229\nmov rax, [rbp+var_48]\nmov eax, [rax]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov [rbp+var_28], 0\nmov [rbp+var_24], 0\njmp short loc_1315\nloc_12A4:\ncmp [rbp+var_24], 0\njz short loc_12DE\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov ecx, [rbp+var_24]\nmovsxd rcx, ecx\nshl rcx, 2\nsub rcx, 4\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_1311\nloc_12DE:\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nshl rdx, 2\nlea rcx, [rax+rdx]\nmov eax, [rbp+var_28]\nlea edx, [rax+1]\nmov [rbp+var_28], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_1311:\nadd [rbp+var_24], 1\nloc_1315:\nmov rax, [rbp+var_48]\nmov eax, [rax]\ncmp [rbp+var_24], eax\njl short loc_12A4\nmov [rbp+var_20], 1\njmp loc_1470\nloc_132C:\nmov eax, [rbp+var_28]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_1C], 0\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp loc_1425\nloc_135B:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_20]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov rax, [rax]\nmov ecx, [rbp+var_14]\nmovsxd rcx, ecx\nshl rcx, 2\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njge short loc_13A4\nadd [rbp+var_18], 1\njmp loc_1425\nloc_13A4:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_20]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov rax, [rax]\nmov ecx, [rbp+var_14]\nmovsxd rcx, ecx\nshl rcx, 2\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_13EA\nadd [rbp+var_14], 1\njmp short loc_1425\nloc_13EA:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_1C]\nlea edx, [rax+1]\nmov [rbp+var_1C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nadd [rbp+var_18], 1\nadd [rbp+var_14], 1\nloc_1425:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_28]\njge short loc_144C\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_14], eax\njl loc_135B\nloc_144C:\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_8]\nmov [rbp+ptr], rax\nmov eax, [rbp+var_1C]\nmov [rbp+var_28], eax\ncmp [rbp+var_28], 0\njz short loc_147E\nadd [rbp+var_20], 1\nloc_1470:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_3C]\njl loc_132C\njmp short loc_147F\nloc_147E:\nnop\nloc_147F:\nmov rax, [rbp+var_50]\nmov edx, [rbp+var_28]\nmov [rax], edx\nmov rax, [rbp+ptr]\nlocret_148C:\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(_QWORD *a1, int a2, int *a3, _DWORD *a4)\n{\n int v5; // eax\n int v6; // eax\n int i; // [rsp+24h] [rbp-2Ch]\n int v10; // [rsp+28h] [rbp-28h]\n int j; // [rsp+2Ch] [rbp-24h]\n int k; // [rsp+30h] [rbp-20h]\n int v13; // [rsp+34h] [rbp-1Ch]\n int v14; // [rsp+38h] [rbp-18h]\n int v15; // [rsp+3Ch] [rbp-14h]\n _DWORD *ptr; // [rsp+40h] [rbp-10h]\n _DWORD *v17; // [rsp+48h] [rbp-8h]\n\n if ( a2 )\n {\n for ( i = 0; i < a2; ++i )\n qsort((void *)a1[i], a3[i], 4uLL, cmpfunc);\n ptr = malloc(4LL * *a3);\n v10 = 0;\n for ( j = 0; j < *a3; ++j )\n {\n if ( !j || *(_DWORD *)(4LL * j + *a1) != *(_DWORD *)(4LL * j - 4 + *a1) )\n {\n v5 = v10++;\n ptr[v5] = *(_DWORD *)(*a1 + 4LL * j);\n }\n }\n for ( k = 1; k < a2; ++k )\n {\n v17 = malloc(4LL * v10);\n v13 = 0;\n v14 = 0;\n v15 = 0;\n while ( v14 < v10 && v15 < a3[k] )\n {\n if ( ptr[v14] >= *(_DWORD *)(4LL * v15 + a1[k]) )\n {\n if ( ptr[v14] <= *(_DWORD *)(4LL * v15 + a1[k]) )\n {\n v6 = v13++;\n v17[v6] = ptr[v14++];\n }\n ++v15;\n }\n else\n {\n ++v14;\n }\n }\n free(ptr);\n ptr = v17;\n v10 = v13;\n if ( !v13 )\n break;\n }\n *a4 = v10;\n return ptr;\n }\n else\n {\n *a4 = 0;\n return 0LL;\n }\n}", + "ida_strip_asm": "sub_11EB:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov [rbp+var_48], rdx\nmov [rbp+var_50], rcx\ncmp [rbp+var_3C], 0\njnz short loc_1220\nmov rax, [rbp+var_50]\nmov dword ptr [rax], 0\nmov eax, 0\njmp locret_148C\nloc_1220:\nmov [rbp+var_2C], 0\njmp short loc_1274\nloc_1229:\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax]\nmovsxd rsi, eax; nmemb\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 4; size\nmov rdi, rax; base\ncall _qsort\nadd [rbp+var_2C], 1\nloc_1274:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_3C]\njl short loc_1229\nmov rax, [rbp+var_48]\nmov eax, [rax]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov [rbp+var_28], 0\nmov [rbp+var_24], 0\njmp short loc_1315\nloc_12A4:\ncmp [rbp+var_24], 0\njz short loc_12DE\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov ecx, [rbp+var_24]\nmovsxd rcx, ecx\nshl rcx, 2\nsub rcx, 4\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_1311\nloc_12DE:\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nshl rdx, 2\nlea rcx, [rax+rdx]\nmov eax, [rbp+var_28]\nlea edx, [rax+1]\nmov [rbp+var_28], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_1311:\nadd [rbp+var_24], 1\nloc_1315:\nmov rax, [rbp+var_48]\nmov eax, [rax]\ncmp [rbp+var_24], eax\njl short loc_12A4\nmov [rbp+var_20], 1\njmp loc_1470\nloc_132C:\nmov eax, [rbp+var_28]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_1C], 0\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp loc_1425\nloc_135B:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_20]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov rax, [rax]\nmov ecx, [rbp+var_14]\nmovsxd rcx, ecx\nshl rcx, 2\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njge short loc_13A4\nadd [rbp+var_18], 1\njmp loc_1425\nloc_13A4:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_20]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov rax, [rax]\nmov ecx, [rbp+var_14]\nmovsxd rcx, ecx\nshl rcx, 2\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_13EA\nadd [rbp+var_14], 1\njmp short loc_1425\nloc_13EA:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_1C]\nlea edx, [rax+1]\nmov [rbp+var_1C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nadd [rbp+var_18], 1\nadd [rbp+var_14], 1\nloc_1425:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_28]\njge short loc_144C\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_14], eax\njl loc_135B\nloc_144C:\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_8]\nmov [rbp+ptr], rax\nmov eax, [rbp+var_1C]\nmov [rbp+var_28], eax\ncmp [rbp+var_28], 0\njz short loc_147E\nadd [rbp+var_20], 1\nloc_1470:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_3C]\njl loc_132C\njmp short loc_147F\nloc_147E:\nnop\nloc_147F:\nmov rax, [rbp+var_50]\nmov edx, [rbp+var_28]\nmov [rax], edx\nmov rax, [rbp+ptr]\nlocret_148C:\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11EB(_QWORD *a1, int a2, int *a3, _DWORD *a4)\n{\n int v5; // eax\n int v6; // eax\n int i; // [rsp+24h] [rbp-2Ch]\n int v10; // [rsp+28h] [rbp-28h]\n int j; // [rsp+2Ch] [rbp-24h]\n int k; // [rsp+30h] [rbp-20h]\n int v13; // [rsp+34h] [rbp-1Ch]\n int v14; // [rsp+38h] [rbp-18h]\n int v15; // [rsp+3Ch] [rbp-14h]\n _DWORD *ptr; // [rsp+40h] [rbp-10h]\n _DWORD *v17; // [rsp+48h] [rbp-8h]\n\n if ( a2 )\n {\n for ( i = 0; i < a2; ++i )\n qsort((void *)a1[i], a3[i], 4uLL, compar);\n ptr = malloc(4LL * *a3);\n v10 = 0;\n for ( j = 0; j < *a3; ++j )\n {\n if ( !j || *(_DWORD *)(4LL * j + *a1) != *(_DWORD *)(4LL * j - 4 + *a1) )\n {\n v5 = v10++;\n ptr[v5] = *(_DWORD *)(*a1 + 4LL * j);\n }\n }\n for ( k = 1; k < a2; ++k )\n {\n v17 = malloc(4LL * v10);\n v13 = 0;\n v14 = 0;\n v15 = 0;\n while ( v14 < v10 && v15 < a3[k] )\n {\n if ( ptr[v14] >= *(_DWORD *)(4LL * v15 + a1[k]) )\n {\n if ( ptr[v14] <= *(_DWORD *)(4LL * v15 + a1[k]) )\n {\n v6 = v13++;\n v17[v6] = ptr[v14++];\n }\n ++v15;\n }\n else\n {\n ++v14;\n }\n }\n free(ptr);\n ptr = v17;\n v10 = v13;\n if ( !v13 )\n break;\n }\n *a4 = v10;\n return ptr;\n }\n else\n {\n *a4 = 0;\n return 0LL;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11EB(uint64_t *a1, int a2, int *a3, uint32_t *a4) {\n int v5;\n int v6;\n int i;\n int v10;\n int j;\n int k;\n int v13;\n int v14;\n int v15;\n uint32_t *ptr;\n uint32_t *v17;\n if (a2) {\n for (i = 0; i < a2; ++i) qsort((void *)a1[i], a3[i], 4uLL, compar);\n ptr = malloc(4LL * *a3);\n v10 = 0;\n for (j = 0; j < *a3; ++j) {\n if (!j ||\n *(uint32_t *)(4LL * j + *a1) != *(uint32_t *)(4LL * j - 4 + *a1)) {\n v5 = v10++;\n ptr[v5] = *(uint32_t *)(*a1 + 4LL * j);\n }\n }\n for (k = 1; k < a2; ++k) {\n v17 = malloc(4LL * v10);\n v13 = 0;\n v14 = 0;\n v15 = 0;\n while (v14 < v10 && v15 < a3[k]) {\n if (ptr[v14] >= *(uint32_t *)(4LL * v15 + a1[k])) {\n if (ptr[v14] <= *(uint32_t *)(4LL * v15 + a1[k])) {\n v6 = v13++;\n v17[v6] = ptr[v14++];\n }\n ++v15;\n } else {\n ++v14;\n }\n }\n free(ptr);\n ptr = v17;\n v10 = v13;\n if (!v13) break;\n }\n *a4 = v10;\n return ptr;\n } else {\n *a4 = 0;\n return 0LL;\n }\n}", + "ida_pseudo_norm": "uint32_t *func0(uint64_t *a1, int a2, int *a3, uint32_t *a4) {\n int v5;\n int v6;\n int i;\n int v10;\n int j;\n int k;\n int v13;\n int v14;\n int v15;\n uint32_t *ptr;\n uint32_t *v17;\n if (a2) {\n for (i = 0; i < a2; ++i) qsort((void *)a1[i], a3[i], 4uLL, cmpfunc);\n ptr = malloc(4LL * *a3);\n v10 = 0;\n for (j = 0; j < *a3; ++j) {\n if (!j ||\n *(uint32_t *)(4LL * j + *a1) != *(uint32_t *)(4LL * j - 4 + *a1)) {\n v5 = v10++;\n ptr[v5] = *(uint32_t *)(*a1 + 4LL * j);\n }\n }\n for (k = 1; k < a2; ++k) {\n v17 = malloc(4LL * v10);\n v13 = 0;\n v14 = 0;\n v15 = 0;\n while (v14 < v10 && v15 < a3[k]) {\n if (ptr[v14] >= *(uint32_t *)(4LL * v15 + a1[k])) {\n if (ptr[v14] <= *(uint32_t *)(4LL * v15 + a1[k])) {\n v6 = v13++;\n v17[v6] = ptr[v14++];\n }\n ++v15;\n } else {\n ++v14;\n }\n }\n free(ptr);\n ptr = v17;\n v10 = v13;\n if (!v13) break;\n }\n *a4 = v10;\n return ptr;\n } else {\n *a4 = 0;\n return 0LL;\n }\n}" + }, + { + "index": 111, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n// Function to compare integers for qsort\n\nint cmpfunc(const void *a, const void *b) {\n\n return (*(int*)a - *(int*)b);\n\n}\n\n\n\n// Function to find common elements in nested lists\n\n", + "func": "int *func0(int **nestedlist, int num_lists, int *sizes, int *result_size) {\n if (num_lists == 0) {\n *result_size = 0;\n return NULL;\n }\n for (int i = 0; i < num_lists; i++) {\n qsort(nestedlist[i], sizes[i], sizeof(int), cmpfunc);\n }\n int *temp = malloc(sizes[0] * sizeof(int));\n int temp_size = 0;\n for (int i = 0; i < sizes[0]; i++) {\n if (i == 0 || nestedlist[0][i] != nestedlist[0][i - 1]) {\n temp[temp_size++] = nestedlist[0][i];\n }\n }\n for (int i = 1; i < num_lists; i++) {\n int *new_temp = malloc(temp_size * sizeof(int));\n int new_size = 0;\n int j = 0, k = 0;\n while (j < temp_size && k < sizes[i]) {\n if (temp[j] < nestedlist[i][k]) {\n j++;\n }\n else if (temp[j] > nestedlist[i][k]) {\n k++;\n }\n else {\n new_temp[new_size++] = temp[j];\n j++;\n k++;\n }\n }\n free(temp);\n temp = new_temp;\n temp_size = new_size;\n if (temp_size == 0) break;\n }\n *result_size = temp_size;\n return temp;\n}", + "test": "int main() {\n\n // First test case\n\n int list1_1[] = {12, 18, 23, 25, 45};\n\n int list1_2[] = {7, 12, 18, 24, 28};\n\n int list1_3[] = {1, 5, 8, 12, 15, 16, 18};\n\n int *nested1[] = {list1_1, list1_2, list1_3};\n\n int sizes1[] = {5, 5, 7};\n\n int result_size1;\n\n int *result1 = func0(nested1, 3, sizes1, &result_size1);\n\n qsort(result1, result_size1, sizeof(int), cmpfunc);\n\n assert(result_size1 == 2 && result1[0] == 12 && result1[1] == 18);\n\n free(result1);\n\n\n\n // Second test case\n\n int list2_1[] = {12, 5, 23, 25, 45};\n\n int list2_2[] = {7, 11, 5, 23, 28};\n\n int list2_3[] = {1, 5, 8, 18, 23, 16};\n\n int *nested2[] = {list2_1, list2_2, list2_3};\n\n int sizes2[] = {5, 5, 6};\n\n int result_size2;\n\n int *result2 = func0(nested2, 3, sizes2, &result_size2);\n\n qsort(result2, result_size2, sizeof(int), cmpfunc);\n\n assert(result_size2 == 2 && result2[0] == 5 && result2[1] == 23);\n\n free(result2);\n\n\n\n // Third test case\n\n int list3_1[] = {2, 3, 4, 1};\n\n int list3_2[] = {4, 5};\n\n int list3_3[] = {6, 4, 8};\n\n int list3_4[] = {4, 5};\n\n int list3_5[] = {6, 8, 4};\n\n int *nested3[] = {list3_1, list3_2, list3_3, list3_4, list3_5};\n\n int sizes3[] = {4, 2, 3, 2, 3};\n\n int result_size3;\n\n int *result3 = func0(nested3, 5, sizes3, &result_size3);\n\n qsort(result3, result_size3, sizeof(int), cmpfunc);\n\n assert(result_size3 == 1 && result3[0] == 4);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov %rcx,(%rsp)\ntest %esi,%esi\njne 120e \nmov (%rsp),%rax\nmovl $0x0,(%rax)\nmov $0x0,%r13d\nmov %r13,%rax\nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmov %rdi,%rbp\nmov %esi,%r13d\nmov %rdx,%r12\nlea -0x1(%rsi),%r15d\nmov $0x0,%ebx\nlea -0x5e(%rip),%r14\njle 124b \nmovslq (%r12,%rbx,4),%rsi\nmov 0x0(%rbp,%rbx,8),%rdi\nmov %r14,%rcx\nmov $0x4,%edx\ncallq 10a0 \nmov %rbx,%rax\nadd $0x1,%rbx\ncmp %r15,%rax\njne 1229 \nmovslq (%r12),%rdi\nshl $0x2,%rdi\ncallq 10d0 \nmov %rax,%r14\nmov (%r12),%edi\ntest %edi,%edi\njle 12a3 \nmov $0x0,%edx\nmov $0x0,%eax\nmov $0x0,%ebx\njmp 1290 \nmov 0x0(%rbp),%rcx\nmov (%rcx,%rdx,1),%esi\nmovslq %ebx,%rcx\nmov %esi,(%r14,%rcx,4)\nlea 0x1(%rbx),%ebx\nadd $0x1,%eax\nadd $0x4,%rdx\ncmp %edi,%eax\nje 12a8 \ntest %eax,%eax\nje 1274 \nmov 0x0(%rbp),%rcx\nmov -0x4(%rcx,%rdx,1),%esi\ncmp %esi,(%rcx,%rdx,1)\njne 1274 \njmp 1285 \nmov $0x0,%ebx\ncmp $0x1,%r13d\njle 135f \nlea 0x4(%r12),%r15\nlea 0x8(%rbp),%r12\nlea -0x2(%r13),%eax\nlea 0x10(%rbp,%rax,8),%rax\nmov %rax,0x8(%rsp)\nmovslq %ebx,%rdi\nshl $0x2,%rdi\ncallq 10d0 \nmov %rax,%r13\ntest %ebx,%ebx\njle 1366 \nmov (%r15),%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov $0x0,%ebp\njmp 12fd \njle 131c \nadd $0x1,%ecx\ncmp %ebx,%edx\njge 132f \ncmp %ecx,%r8d\njle 132f \nmovslq %edx,%rax\nmov (%r14,%rax,4),%esi\nmovslq %ecx,%rax\nmov (%r12),%rdi\nmov (%rdi,%rax,4),%eax\ncmp %eax,%esi\njge 12f4 \nadd $0x1,%edx\njmp 12f9 \nmovslq %ebp,%rax\nmov %esi,0x0(%r13,%rax,4)\nadd $0x1,%edx\nadd $0x1,%ecx\nlea 0x1(%rbp),%ebp\njmp 12f9 \nmov %r14,%rdi\ncallq 1090 \ntest %ebp,%ebp\njne 1346 \nmov (%rsp),%rax\nmov %ebp,(%rax)\njmpq 11fc \nadd $0x4,%r15\nadd $0x8,%r12\ncmp 0x8(%rsp),%r12\nje 133b \nmov %ebp,%ebx\nmov %r13,%r14\njmpq 12c9 \nmov %ebx,%ebp\nmov %r14,%r13\njmp 133b \nmov %r14,%rdi\ncallq 1090 \nmov $0x0,%ebp\njmp 133b \n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov r15d, esi\nmov [rsp+48h+var_48], rdx\nmov [rsp+48h+var_40], rcx\ntest esi, esi\njz loc_133F\nmov r12, rdi\njle loc_136F\nmov rbx, rdx\nmov rbp, rdi\nmovsxd rax, esi\nlea r14, [rdx+rax*4]\nlea r13, cmpfunc\nloc_1215:\nmovsxd rsi, dword ptr [rbx]; nmemb\nmov rdi, [rbp+0]; base\nmov rcx, r13; compar\nmov edx, 4; size\ncall _qsort\nadd rbx, 4\nadd rbp, 8\ncmp rbx, r14\njnz short loc_1215\nmov rbx, [rsp+48h+var_48]\nmovsxd rdi, dword ptr [rbx]\nshl rdi, 2; size\ncall _malloc\nmov r13, rax\nmov edi, [rbx]\ntest edi, edi\njle short loc_1290\nloc_124F:\nmov edx, 0\nmov eax, 0\nmov ebx, 0\njmp short loc_127D\nloc_1260:\nmov rcx, [r12]\nmov esi, [rcx+rdx]\nmovsxd rcx, ebx\nmov [r13+rcx*4+0], esi\nlea ebx, [rbx+1]\nloc_1272:\nadd eax, 1\nadd rdx, 4\ncmp eax, edi\njge short loc_1295\nloc_127D:\ntest eax, eax\njz short loc_1260\nmov rcx, [r12]\nmov esi, [rcx+rdx-4]\ncmp [rcx+rdx], esi\njnz short loc_1260\njmp short loc_1272\nloc_1290:\nmov ebx, 0\nloc_1295:\ncmp r15d, 1\njle loc_1356\nmov r14, [rsp+48h+var_48]\nadd r14, 4\nlea rbp, [r12+8]\nlea eax, [r15-2]\nlea r15, [r12+rax*8+10h]\njmp short loc_130F\nloc_12B7:\njle short loc_12DF\nadd ecx, 1\nloc_12BC:\ncmp edx, ebx\njge short loc_133A\nloc_12C0:\ncmp r8d, ecx\njle short loc_12F3\nmovsxd rax, edx\nmov esi, [r12+rax*4]\nmovsxd rax, ecx\nmov rdi, [rbp+0]\nmov eax, [rdi+rax*4]\ncmp esi, eax\njge short loc_12B7\nadd edx, 1\njmp short loc_12BC\nloc_12DF:\nmovsxd rax, r9d\nmov [r13+rax*4+0], esi\nadd edx, 1\nadd ecx, 1\nlea r9d, [r9+1]\njmp short loc_12BC\nloc_12F3:\nmov ebx, r9d\nloc_12F6:\nmov rdi, r12; ptr\ncall _free\ntest ebx, ebx\njz short loc_1356\nadd r14, 4\nadd rbp, 8\ncmp rbp, r15\njz short loc_1356\nloc_130F:\nmov r12, r13\nmovsxd rdi, ebx\nshl rdi, 2; size\ncall _malloc\nmov r13, rax\ntest ebx, ebx\njle short loc_1349\nmov r8d, [r14]\nmov ecx, 0\nmov edx, 0\nmov r9d, 0\njmp short loc_12C0\nloc_133A:\nmov ebx, r9d\njmp short loc_12F6\nloc_133F:\nmov ebx, esi\nmov r13d, 0\njmp short loc_1356\nloc_1349:\nmov rdi, r12; ptr\ncall _free\nmov ebx, 0\nloc_1356:\nmov rax, [rsp+48h+var_40]\nmov [rax], ebx\nmov rax, r13\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_136F:\nmov rbx, [rsp+48h+var_48]\nmovsxd rdi, dword ptr [rbx]\nshl rdi, 2; size\ncall _malloc\nmov r13, rax\nmov edi, [rbx]\ntest edi, edi\njg loc_124F\nmov ebx, 0\njmp short loc_1356", + "ida_pseudo": "_DWORD *__fastcall func0(_QWORD *a1, int a2, int *a3, int *a4)\n{\n int *v5; // rbx\n void **v6; // rbp\n int *v7; // r14\n _DWORD *v8; // r13\n int v9; // edi\n __int64 v10; // rdx\n int v11; // eax\n int v12; // ebx\n int *v13; // r14\n _QWORD *v14; // rbp\n __int64 v15; // r15\n int v16; // ecx\n int v17; // esi\n int v18; // eax\n int v19; // edx\n int v20; // r9d\n _DWORD *v21; // r12\n int v22; // r8d\n\n if ( !a2 )\n {\n v12 = 0;\n v8 = 0LL;\n goto LABEL_30;\n }\n if ( a2 <= 0 )\n {\n v8 = malloc(4LL * *a3);\n v9 = *a3;\n if ( *a3 <= 0 )\n {\n v12 = 0;\n goto LABEL_30;\n }\n }\n else\n {\n v5 = a3;\n v6 = (void **)a1;\n v7 = &a3[a2];\n do\n qsort(*v6++, *v5++, 4uLL, cmpfunc);\n while ( v5 != v7 );\n v8 = malloc(4LL * *a3);\n v9 = *a3;\n if ( *a3 <= 0 )\n {\n v12 = 0;\n goto LABEL_13;\n }\n }\n v10 = 0LL;\n v11 = 0;\n v12 = 0;\n do\n {\n if ( !v11 || *(_DWORD *)(*a1 + v10) != *(_DWORD *)(*a1 + v10 - 4) )\n v8[v12++] = *(_DWORD *)(*a1 + v10);\n ++v11;\n v10 += 4LL;\n }\n while ( v11 < v9 );\nLABEL_13:\n if ( a2 > 1 )\n {\n v13 = a3 + 1;\n v14 = a1 + 1;\n v15 = (__int64)&a1[(unsigned int)(a2 - 2) + 2];\n while ( 1 )\n {\n v21 = v8;\n v8 = malloc(4LL * v12);\n if ( v12 <= 0 )\n break;\n v22 = *v13;\n v16 = 0;\n v19 = 0;\n v20 = 0;\n do\n {\n if ( v22 <= v16 )\n {\n v12 = v20;\n goto LABEL_23;\n }\n v17 = v21[v19];\n v18 = *(_DWORD *)(*v14 + 4LL * v16);\n if ( v17 >= v18 )\n {\n if ( v17 <= v18 )\n {\n v8[v20] = v17;\n ++v19;\n ++v16;\n ++v20;\n }\n else\n {\n ++v16;\n }\n }\n else\n {\n ++v19;\n }\n }\n while ( v19 < v12 );\n v12 = v20;\nLABEL_23:\n free(v21);\n if ( v12 )\n {\n ++v13;\n if ( ++v14 != (_QWORD *)v15 )\n continue;\n }\n goto LABEL_30;\n }\n free(v21);\n v12 = 0;\n }\nLABEL_30:\n *a4 = v12;\n return v8;\n}", + "ida_strip_asm": "sub_11D2:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov r15d, esi\nmov [rsp+48h+var_48], rdx\nmov [rsp+48h+var_40], rcx\ntest esi, esi\njz loc_133F\nmov r12, rdi\njle loc_136F\nmov rbx, rdx\nmov rbp, rdi\nmovsxd rax, esi\nlea r14, [rdx+rax*4]\nlea r13, compar\nloc_1215:\nmovsxd rsi, dword ptr [rbx]; nmemb\nmov rdi, [rbp+0]; base\nmov rcx, r13; compar\nmov edx, 4; size\ncall _qsort\nadd rbx, 4\nadd rbp, 8\ncmp rbx, r14\njnz short loc_1215\nmov rbx, [rsp+48h+var_48]\nmovsxd rdi, dword ptr [rbx]\nshl rdi, 2; size\ncall _malloc\nmov r13, rax\nmov edi, [rbx]\ntest edi, edi\njle short loc_1290\nloc_124F:\nmov edx, 0\nmov eax, 0\nmov ebx, 0\njmp short loc_127D\nloc_1260:\nmov rcx, [r12]\nmov esi, [rcx+rdx]\nmovsxd rcx, ebx\nmov [r13+rcx*4+0], esi\nlea ebx, [rbx+1]\nloc_1272:\nadd eax, 1\nadd rdx, 4\ncmp eax, edi\njge short loc_1295\nloc_127D:\ntest eax, eax\njz short loc_1260\nmov rcx, [r12]\nmov esi, [rcx+rdx-4]\ncmp [rcx+rdx], esi\njnz short loc_1260\njmp short loc_1272\nloc_1290:\nmov ebx, 0\nloc_1295:\ncmp r15d, 1\njle loc_1356\nmov r14, [rsp+48h+var_48]\nadd r14, 4\nlea rbp, [r12+8]\nlea eax, [r15-2]\nlea r15, [r12+rax*8+10h]\njmp short loc_130F\nloc_12B7:\njle short loc_12DF\nadd ecx, 1\nloc_12BC:\ncmp edx, ebx\njge short loc_133A\nloc_12C0:\ncmp r8d, ecx\njle short loc_12F3\nmovsxd rax, edx\nmov esi, [r12+rax*4]\nmovsxd rax, ecx\nmov rdi, [rbp+0]\nmov eax, [rdi+rax*4]\ncmp esi, eax\njge short loc_12B7\nadd edx, 1\njmp short loc_12BC\nloc_12DF:\nmovsxd rax, r9d\nmov [r13+rax*4+0], esi\nadd edx, 1\nadd ecx, 1\nlea r9d, [r9+1]\njmp short loc_12BC\nloc_12F3:\nmov ebx, r9d\nloc_12F6:\nmov rdi, r12; ptr\ncall _free\ntest ebx, ebx\njz short loc_1356\nadd r14, 4\nadd rbp, 8\ncmp rbp, r15\njz short loc_1356\nloc_130F:\nmov r12, r13\nmovsxd rdi, ebx\nshl rdi, 2; size\ncall _malloc\nmov r13, rax\ntest ebx, ebx\njle short loc_1349\nmov r8d, [r14]\nmov ecx, 0\nmov edx, 0\nmov r9d, 0\njmp short loc_12C0\nloc_133A:\nmov ebx, r9d\njmp short loc_12F6\nloc_133F:\nmov ebx, esi\nmov r13d, 0\njmp short loc_1356\nloc_1349:\nmov rdi, r12; ptr\ncall _free\nmov ebx, 0\nloc_1356:\nmov rax, [rsp+48h+var_40]\nmov [rax], ebx\nmov rax, r13\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_136F:\nmov rbx, [rsp+48h+var_48]\nmovsxd rdi, dword ptr [rbx]\nshl rdi, 2; size\ncall _malloc\nmov r13, rax\nmov edi, [rbx]\ntest edi, edi\njg loc_124F\nmov ebx, 0\njmp short loc_1356", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11D2(_QWORD *a1, int a2, int *a3, int *a4)\n{\n int *v5; // rbx\n void **v6; // rbp\n int *v7; // r14\n _DWORD *v8; // r13\n int v9; // edi\n __int64 v10; // rdx\n int v11; // eax\n int v12; // ebx\n int *v13; // r14\n _QWORD *v14; // rbp\n __int64 v15; // r15\n int v16; // ecx\n int v17; // esi\n int v18; // eax\n int v19; // edx\n int v20; // r9d\n _DWORD *v21; // r12\n int v22; // r8d\n\n if ( !a2 )\n {\n v12 = 0;\n v8 = 0LL;\n goto LABEL_30;\n }\n if ( a2 <= 0 )\n {\n v8 = malloc(4LL * *a3);\n v9 = *a3;\n if ( *a3 <= 0 )\n {\n v12 = 0;\n goto LABEL_30;\n }\n }\n else\n {\n v5 = a3;\n v6 = (void **)a1;\n v7 = &a3[a2];\n do\n qsort(*v6++, *v5++, 4uLL, compar);\n while ( v5 != v7 );\n v8 = malloc(4LL * *a3);\n v9 = *a3;\n if ( *a3 <= 0 )\n {\n v12 = 0;\n goto LABEL_13;\n }\n }\n v10 = 0LL;\n v11 = 0;\n v12 = 0;\n do\n {\n if ( !v11 || *(_DWORD *)(*a1 + v10) != *(_DWORD *)(*a1 + v10 - 4) )\n v8[v12++] = *(_DWORD *)(*a1 + v10);\n ++v11;\n v10 += 4LL;\n }\n while ( v11 < v9 );\nLABEL_13:\n if ( a2 > 1 )\n {\n v13 = a3 + 1;\n v14 = a1 + 1;\n v15 = (__int64)&a1[(unsigned int)(a2 - 2) + 2];\n while ( 1 )\n {\n v21 = v8;\n v8 = malloc(4LL * v12);\n if ( v12 <= 0 )\n break;\n v22 = *v13;\n v16 = 0;\n v19 = 0;\n v20 = 0;\n do\n {\n if ( v22 <= v16 )\n {\n v12 = v20;\n goto LABEL_23;\n }\n v17 = v21[v19];\n v18 = *(_DWORD *)(*v14 + 4LL * v16);\n if ( v17 >= v18 )\n {\n if ( v17 <= v18 )\n {\n v8[v20] = v17;\n ++v19;\n ++v16;\n ++v20;\n }\n else\n {\n ++v16;\n }\n }\n else\n {\n ++v19;\n }\n }\n while ( v19 < v12 );\n v12 = v20;\nLABEL_23:\n free(v21);\n if ( v12 )\n {\n ++v13;\n if ( ++v14 != (_QWORD *)v15 )\n continue;\n }\n goto LABEL_30;\n }\n free(v21);\n v12 = 0;\n }\nLABEL_30:\n *a4 = v12;\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11D2(uint64_t *a1, int a2, int *a3, int *a4) {\n int *v5;\n void **v6;\n int *v7;\n uint32_t *v8;\n int v9;\n long long v10;\n int v11;\n int v12;\n int *v13;\n uint64_t *v14;\n long long v15;\n int v16;\n int v17;\n int v18;\n int v19;\n int v20;\n uint32_t *v21;\n int v22;\n if (!a2) {\n v12 = 0;\n v8 = 0LL;\n goto LABEL_30;\n }\n if (a2 <= 0) {\n v8 = malloc(4LL * *a3);\n v9 = *a3;\n if (*a3 <= 0) {\n v12 = 0;\n goto LABEL_30;\n }\n } else {\n v5 = a3;\n v6 = (void **)a1;\n v7 = &a3[a2];\n do\n qsort(*v6++, *v5++, 4uLL, compar);\n while (v5 != v7);\n v8 = malloc(4LL * *a3);\n v9 = *a3;\n if (*a3 <= 0) {\n v12 = 0;\n goto LABEL_13;\n }\n }\n v10 = 0LL;\n v11 = 0;\n v12 = 0;\n do {\n if (!v11 || *(uint32_t *)(*a1 + v10) != *(uint32_t *)(*a1 + v10 - 4))\n v8[v12++] = *(uint32_t *)(*a1 + v10);\n ++v11;\n v10 += 4LL;\n } while (v11 < v9);\nLABEL_13:\n if (a2 > 1) {\n v13 = a3 + 1;\n v14 = a1 + 1;\n v15 = (long long)&a1[(unsigned int)(a2 - 2) + 2];\n while (1) {\n v21 = v8;\n v8 = malloc(4LL * v12);\n if (v12 <= 0) break;\n v22 = *v13;\n v16 = 0;\n v19 = 0;\n v20 = 0;\n do {\n if (v22 <= v16) {\n v12 = v20;\n goto LABEL_23;\n }\n v17 = v21[v19];\n v18 = *(uint32_t *)(*v14 + 4LL * v16);\n if (v17 >= v18) {\n if (v17 <= v18) {\n v8[v20] = v17;\n ++v19;\n ++v16;\n ++v20;\n } else {\n ++v16;\n }\n } else {\n ++v19;\n }\n } while (v19 < v12);\n v12 = v20;\n LABEL_23:\n free(v21);\n if (v12) {\n ++v13;\n if (++v14 != (uint64_t *)v15) continue;\n }\n goto LABEL_30;\n }\n free(v21);\n v12 = 0;\n }\nLABEL_30:\n *a4 = v12;\n return v8;\n}", + "ida_pseudo_norm": "uint32_t *func0(uint64_t *a1, int a2, int *a3, int *a4) {\n int *v5;\n void **v6;\n int *v7;\n uint32_t *v8;\n int v9;\n long long v10;\n int v11;\n int v12;\n int *v13;\n uint64_t *v14;\n long long v15;\n int v16;\n int v17;\n int v18;\n int v19;\n int v20;\n uint32_t *v21;\n int v22;\n if (!a2) {\n v12 = 0;\n v8 = 0LL;\n goto LABEL_30;\n }\n if (a2 <= 0) {\n v8 = malloc(4LL * *a3);\n v9 = *a3;\n if (*a3 <= 0) {\n v12 = 0;\n goto LABEL_30;\n }\n } else {\n v5 = a3;\n v6 = (void **)a1;\n v7 = &a3[a2];\n do\n qsort(*v6++, *v5++, 4uLL, cmpfunc);\n while (v5 != v7);\n v8 = malloc(4LL * *a3);\n v9 = *a3;\n if (*a3 <= 0) {\n v12 = 0;\n goto LABEL_13;\n }\n }\n v10 = 0LL;\n v11 = 0;\n v12 = 0;\n do {\n if (!v11 || *(uint32_t *)(*a1 + v10) != *(uint32_t *)(*a1 + v10 - 4))\n v8[v12++] = *(uint32_t *)(*a1 + v10);\n ++v11;\n v10 += 4LL;\n } while (v11 < v9);\nLABEL_13:\n if (a2 > 1) {\n v13 = a3 + 1;\n v14 = a1 + 1;\n v15 = (long long)&a1[(unsigned int)(a2 - 2) + 2];\n while (1) {\n v21 = v8;\n v8 = malloc(4LL * v12);\n if (v12 <= 0) break;\n v22 = *v13;\n v16 = 0;\n v19 = 0;\n v20 = 0;\n do {\n if (v22 <= v16) {\n v12 = v20;\n goto LABEL_23;\n }\n v17 = v21[v19];\n v18 = *(uint32_t *)(*v14 + 4LL * v16);\n if (v17 >= v18) {\n if (v17 <= v18) {\n v8[v20] = v17;\n ++v19;\n ++v16;\n ++v20;\n } else {\n ++v16;\n }\n } else {\n ++v19;\n }\n } while (v19 < v12);\n v12 = v20;\n LABEL_23:\n free(v21);\n if (v12) {\n ++v13;\n if (++v14 != (uint64_t *)v15) continue;\n }\n goto LABEL_30;\n }\n free(v21);\n v12 = 0;\n }\nLABEL_30:\n *a4 = v12;\n return v8;\n}" + }, + { + "index": 111, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n// Function to compare integers for qsort\n\nint cmpfunc(const void *a, const void *b) {\n\n return (*(int*)a - *(int*)b);\n\n}\n\n\n\n// Function to find common elements in nested lists\n\n", + "func": "int *func0(int **nestedlist, int num_lists, int *sizes, int *result_size) {\n if (num_lists == 0) {\n *result_size = 0;\n return NULL;\n }\n for (int i = 0; i < num_lists; i++) {\n qsort(nestedlist[i], sizes[i], sizeof(int), cmpfunc);\n }\n int *temp = malloc(sizes[0] * sizeof(int));\n int temp_size = 0;\n for (int i = 0; i < sizes[0]; i++) {\n if (i == 0 || nestedlist[0][i] != nestedlist[0][i - 1]) {\n temp[temp_size++] = nestedlist[0][i];\n }\n }\n for (int i = 1; i < num_lists; i++) {\n int *new_temp = malloc(temp_size * sizeof(int));\n int new_size = 0;\n int j = 0, k = 0;\n while (j < temp_size && k < sizes[i]) {\n if (temp[j] < nestedlist[i][k]) {\n j++;\n }\n else if (temp[j] > nestedlist[i][k]) {\n k++;\n }\n else {\n new_temp[new_size++] = temp[j];\n j++;\n k++;\n }\n }\n free(temp);\n temp = new_temp;\n temp_size = new_size;\n if (temp_size == 0) break;\n }\n *result_size = temp_size;\n return temp;\n}", + "test": "int main() {\n\n // First test case\n\n int list1_1[] = {12, 18, 23, 25, 45};\n\n int list1_2[] = {7, 12, 18, 24, 28};\n\n int list1_3[] = {1, 5, 8, 12, 15, 16, 18};\n\n int *nested1[] = {list1_1, list1_2, list1_3};\n\n int sizes1[] = {5, 5, 7};\n\n int result_size1;\n\n int *result1 = func0(nested1, 3, sizes1, &result_size1);\n\n qsort(result1, result_size1, sizeof(int), cmpfunc);\n\n assert(result_size1 == 2 && result1[0] == 12 && result1[1] == 18);\n\n free(result1);\n\n\n\n // Second test case\n\n int list2_1[] = {12, 5, 23, 25, 45};\n\n int list2_2[] = {7, 11, 5, 23, 28};\n\n int list2_3[] = {1, 5, 8, 18, 23, 16};\n\n int *nested2[] = {list2_1, list2_2, list2_3};\n\n int sizes2[] = {5, 5, 6};\n\n int result_size2;\n\n int *result2 = func0(nested2, 3, sizes2, &result_size2);\n\n qsort(result2, result_size2, sizeof(int), cmpfunc);\n\n assert(result_size2 == 2 && result2[0] == 5 && result2[1] == 23);\n\n free(result2);\n\n\n\n // Third test case\n\n int list3_1[] = {2, 3, 4, 1};\n\n int list3_2[] = {4, 5};\n\n int list3_3[] = {6, 4, 8};\n\n int list3_4[] = {4, 5};\n\n int list3_5[] = {6, 8, 4};\n\n int *nested3[] = {list3_1, list3_2, list3_3, list3_4, list3_5};\n\n int sizes3[] = {4, 2, 3, 2, 3};\n\n int result_size3;\n\n int *result3 = func0(nested3, 5, sizes3, &result_size3);\n\n qsort(result3, result_size3, sizeof(int), cmpfunc);\n\n assert(result_size3 == 1 && result3[0] == 4);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\nje 17b0 \njmpq 1600 \nnopl (%rax)\nmovl $0x0,(%rcx)\nxor %eax,%eax\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0_part_0:\npush r15\npush r14\npush r13\npush r12\npush rbp\nmov ebp, esi\npush rbx\nmov rbx, rdx\nsub rsp, 18h\nmovsxd rax, dword ptr [rdx]\nmov [rsp+48h+var_48], rdi\nmov [rsp+48h+var_40], rcx\ntest esi, esi\njle loc_175B\nmov r15, rdx\nmovsxd rdx, esi\nlea r13, cmpfunc\nmov r12, rdi\nlea r14, [rbx+rdx*4]\nnop dword ptr [rax+rax+00h]\nloc_1600:\nmovsxd rsi, dword ptr [r15]; nmemb\nmov rdi, [r12]; base\nmov rcx, r13; compar\nmov edx, 4; size\nadd r15, 4\nadd r12, 8\ncall _qsort\ncmp r15, r14\njnz short loc_1600\nmovsxd rdi, dword ptr [rbx]\nshl rdi, 2; size\ncall _malloc\nmov r9d, [rbx]\nmov r12, rax\ntest r9d, r9d\njle loc_177C\nloc_163C:\nmov rax, [rsp+48h+var_48]\nxor r13d, r13d\nxor edx, edx\nmov rcx, [rax]\nxor eax, eax\nnop word ptr [rax+rax+00h]\nloc_1650:\nmov edi, [rcx+rax]\nmovsxd rsi, r13d\nadd edx, 1\nadd r13d, 1\nmov [r12+rsi*4], edi\nmov rsi, rax\nadd rax, 4\ncmp edx, r9d\njge short loc_1684\nloc_166D:\nmov edi, [rcx+rsi]\ncmp [rcx+rax], edi\njnz short loc_1650\nadd edx, 1\nmov rsi, rax\nadd rax, 4\ncmp edx, r9d\njl short loc_166D\nloc_1684:\ncmp ebp, 1\njle loc_1734\nmov rdi, [rsp+48h+var_48]\nlea eax, [rbp-2]\nadd rbx, 4\nlea rax, [rdi+rax*8+10h]\nlea r14, [rdi+8]\nmov [rsp+48h+var_48], rax\nnop dword ptr [rax]\nloc_16A8:\nmovsxd rdi, r13d\nmov r15, r12\nshl rdi, 2; size\ncall _malloc\nmov r12, rax\ntest r13d, r13d\njle loc_174E\nmov edi, [rbx]\nxor ebp, ebp\nxor ecx, ecx\nxor edx, edx\njmp short loc_16D8\nloc_16D0:\nadd edx, 1\nloc_16D3:\ncmp edx, r13d\njge short loc_1710\nloc_16D8:\ncmp edi, ecx\njle short loc_1710\nmovsxd rax, edx\nmov r10, [r14]\nmov esi, [r15+rax*4]\nmovsxd rax, ecx\nmov eax, [r10+rax*4]\ncmp esi, eax\njl short loc_16D0\nadd ecx, 1\ncmp esi, eax\njg short loc_16D3\nmovsxd rax, ebp\nadd edx, 1\nadd ebp, 1\nmov [r12+rax*4], esi\ncmp edx, r13d\njl short loc_16D8\nnop word ptr [rax+rax+00h]\nloc_1710:\nmov rdi, r15; ptr\nmov r13d, ebp\ncall _free\ntest ebp, ebp\njz short loc_1734\nmov rax, [rsp+48h+var_48]\nadd r14, 8\nadd rbx, 4\ncmp r14, rax\njnz loc_16A8\nloc_1734:\nmov rax, [rsp+48h+var_40]\nmov [rax], r13d\nadd rsp, 18h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_174E:\nmov rdi, r15; ptr\nxor r13d, r13d\ncall _free\njmp short loc_1734\nloc_175B:\nlea rdi, ds:0[rax*4]; size\ncall _malloc\nmov r9d, [rbx]\nmov r12, rax\ntest r9d, r9d\njg loc_163C\nxor r13d, r13d\njmp short loc_1734\nloc_177C:\nxor r13d, r13d\njmp loc_1684", + "ida_pseudo": "_DWORD *__fastcall func0_part_0(_QWORD *a1, int a2, int *a3, int *a4)\n{\n int *v6; // r15\n void **v7; // r12\n int *v8; // r14\n size_t v9; // rsi\n void *v10; // rdi\n _DWORD *v11; // rax\n int v12; // r9d\n _DWORD *v13; // r12\n int v14; // r13d\n int v15; // edx\n char *v16; // rcx\n __int64 v17; // rax\n __int64 v18; // rsi\n __int64 v19; // rsi\n int *v20; // rbx\n _QWORD *v21; // r14\n void *v22; // r15\n int v23; // edi\n int v24; // ebp\n int v25; // ecx\n int v26; // edx\n int v27; // esi\n int v28; // eax\n __int64 v29; // rax\n _DWORD *v31; // rax\n __int64 v33; // [rsp+0h] [rbp-48h]\n\n if ( a2 <= 0 )\n {\n v31 = malloc(4LL * *a3);\n v12 = *a3;\n v13 = v31;\n if ( *a3 <= 0 )\n {\n v14 = 0;\n goto LABEL_21;\n }\nLABEL_5:\n v14 = 0;\n v15 = 0;\n v16 = (char *)*a1;\n v17 = 0LL;\n while ( 1 )\n {\n v18 = v14;\n ++v15;\n ++v14;\n v13[v18] = *(_DWORD *)&v16[v17];\n v19 = v17;\n v17 += 4LL;\n if ( v15 >= v12 )\n goto LABEL_9;\n while ( *(_DWORD *)&v16[v17] == *(_DWORD *)&v16[v19] )\n {\n ++v15;\n v19 = v17;\n v17 += 4LL;\n if ( v15 >= v12 )\n goto LABEL_9;\n }\n }\n }\n v6 = a3;\n v7 = (void **)a1;\n v8 = &a3[a2];\n do\n {\n v9 = *v6;\n v10 = *v7;\n ++v6;\n ++v7;\n qsort(v10, v9, 4uLL, cmpfunc);\n }\n while ( v6 != v8 );\n v11 = malloc(4LL * *a3);\n v12 = *a3;\n v13 = v11;\n if ( *a3 > 0 )\n goto LABEL_5;\n v14 = 0;\nLABEL_9:\n if ( a2 <= 1 )\n goto LABEL_21;\n v20 = a3 + 1;\n v21 = a1 + 1;\n v33 = (__int64)&a1[(unsigned int)(a2 - 2) + 2];\n do\n {\n v22 = v13;\n v13 = malloc(4LL * v14);\n if ( v14 <= 0 )\n {\n v14 = 0;\n free(v22);\n break;\n }\n v23 = *v20;\n v24 = 0;\n v25 = 0;\n v26 = 0;\n while ( v23 > v25 )\n {\n v27 = *((_DWORD *)v22 + v26);\n v28 = *(_DWORD *)(*v21 + 4LL * v25);\n if ( v27 < v28 )\n {\n ++v26;\nLABEL_14:\n if ( v26 >= v14 )\n break;\n }\n else\n {\n ++v25;\n if ( v27 > v28 )\n goto LABEL_14;\n v29 = v24;\n ++v26;\n ++v24;\n v13[v29] = v27;\n if ( v26 >= v14 )\n break;\n }\n }\n v14 = v24;\n free(v22);\n if ( !v24 )\n break;\n ++v21;\n ++v20;\n }\n while ( v21 != (_QWORD *)v33 );\nLABEL_21:\n *a4 = v14;\n return v13;\n}", + "ida_strip_asm": "sub_15C0:\npush r15\npush r14\npush r13\npush r12\npush rbp\nmov ebp, esi\npush rbx\nmov rbx, rdx\nsub rsp, 18h\nmovsxd rax, dword ptr [rdx]\nmov [rsp+48h+var_48], rdi\nmov [rsp+48h+var_40], rcx\ntest esi, esi\njle loc_175B\nmov r15, rdx\nmovsxd rdx, esi\nlea r13, compar\nmov r12, rdi\nlea r14, [rbx+rdx*4]\nnop dword ptr [rax+rax+00h]\nloc_1600:\nmovsxd rsi, dword ptr [r15]; nmemb\nmov rdi, [r12]; base\nmov rcx, r13; compar\nmov edx, 4; size\nadd r15, 4\nadd r12, 8\ncall _qsort\ncmp r15, r14\njnz short loc_1600\nmovsxd rdi, dword ptr [rbx]\nshl rdi, 2; size\ncall _malloc\nmov r9d, [rbx]\nmov r12, rax\ntest r9d, r9d\njle loc_177C\nloc_163C:\nmov rax, [rsp+48h+var_48]\nxor r13d, r13d\nxor edx, edx\nmov rcx, [rax]\nxor eax, eax\nnop word ptr [rax+rax+00h]\nloc_1650:\nmov edi, [rcx+rax]\nmovsxd rsi, r13d\nadd edx, 1\nadd r13d, 1\nmov [r12+rsi*4], edi\nmov rsi, rax\nadd rax, 4\ncmp edx, r9d\njge short loc_1684\nloc_166D:\nmov edi, [rcx+rsi]\ncmp [rcx+rax], edi\njnz short loc_1650\nadd edx, 1\nmov rsi, rax\nadd rax, 4\ncmp edx, r9d\njl short loc_166D\nloc_1684:\ncmp ebp, 1\njle loc_1734\nmov rdi, [rsp+48h+var_48]\nlea eax, [rbp-2]\nadd rbx, 4\nlea rax, [rdi+rax*8+10h]\nlea r14, [rdi+8]\nmov [rsp+48h+var_48], rax\nnop dword ptr [rax]\nloc_16A8:\nmovsxd rdi, r13d\nmov r15, r12\nshl rdi, 2; size\ncall _malloc\nmov r12, rax\ntest r13d, r13d\njle loc_174E\nmov edi, [rbx]\nxor ebp, ebp\nxor ecx, ecx\nxor edx, edx\njmp short loc_16D8\nloc_16D0:\nadd edx, 1\nloc_16D3:\ncmp edx, r13d\njge short loc_1710\nloc_16D8:\ncmp edi, ecx\njle short loc_1710\nmovsxd rax, edx\nmov r10, [r14]\nmov esi, [r15+rax*4]\nmovsxd rax, ecx\nmov eax, [r10+rax*4]\ncmp esi, eax\njl short loc_16D0\nadd ecx, 1\ncmp esi, eax\njg short loc_16D3\nmovsxd rax, ebp\nadd edx, 1\nadd ebp, 1\nmov [r12+rax*4], esi\ncmp edx, r13d\njl short loc_16D8\nnop word ptr [rax+rax+00h]\nloc_1710:\nmov rdi, r15; ptr\nmov r13d, ebp\ncall _free\ntest ebp, ebp\njz short loc_1734\nmov rax, [rsp+48h+var_48]\nadd r14, 8\nadd rbx, 4\ncmp r14, rax\njnz loc_16A8\nloc_1734:\nmov rax, [rsp+48h+var_40]\nmov [rax], r13d\nadd rsp, 18h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_174E:\nmov rdi, r15; ptr\nxor r13d, r13d\ncall _free\njmp short loc_1734\nloc_175B:\nlea rdi, ds:0[rax*4]; size\ncall _malloc\nmov r9d, [rbx]\nmov r12, rax\ntest r9d, r9d\njg loc_163C\nxor r13d, r13d\njmp short loc_1734\nloc_177C:\nxor r13d, r13d\njmp loc_1684", + "ida_strip_pseudo": "_DWORD *__fastcall sub_15C0(_QWORD *a1, int a2, int *a3, int *a4)\n{\n int *v6; // r15\n void **v7; // r12\n int *v8; // r14\n size_t v9; // rsi\n void *v10; // rdi\n _DWORD *v11; // rax\n int v12; // r9d\n _DWORD *v13; // r12\n int v14; // r13d\n int v15; // edx\n char *v16; // rcx\n __int64 v17; // rax\n __int64 v18; // rsi\n __int64 v19; // rsi\n int *v20; // rbx\n _QWORD *v21; // r14\n void *v22; // r15\n int v23; // edi\n int v24; // ebp\n int v25; // ecx\n int v26; // edx\n int v27; // esi\n int v28; // eax\n __int64 v29; // rax\n _DWORD *v31; // rax\n __int64 v33; // [rsp+0h] [rbp-48h]\n\n if ( a2 <= 0 )\n {\n v31 = malloc(4LL * *a3);\n v12 = *a3;\n v13 = v31;\n if ( *a3 <= 0 )\n {\n v14 = 0;\n goto LABEL_21;\n }\nLABEL_5:\n v14 = 0;\n v15 = 0;\n v16 = (char *)*a1;\n v17 = 0LL;\n while ( 1 )\n {\n v18 = v14;\n ++v15;\n ++v14;\n v13[v18] = *(_DWORD *)&v16[v17];\n v19 = v17;\n v17 += 4LL;\n if ( v15 >= v12 )\n goto LABEL_9;\n while ( *(_DWORD *)&v16[v17] == *(_DWORD *)&v16[v19] )\n {\n ++v15;\n v19 = v17;\n v17 += 4LL;\n if ( v15 >= v12 )\n goto LABEL_9;\n }\n }\n }\n v6 = a3;\n v7 = (void **)a1;\n v8 = &a3[a2];\n do\n {\n v9 = *v6;\n v10 = *v7;\n ++v6;\n ++v7;\n qsort(v10, v9, 4uLL, compar);\n }\n while ( v6 != v8 );\n v11 = malloc(4LL * *a3);\n v12 = *a3;\n v13 = v11;\n if ( *a3 > 0 )\n goto LABEL_5;\n v14 = 0;\nLABEL_9:\n if ( a2 <= 1 )\n goto LABEL_21;\n v20 = a3 + 1;\n v21 = a1 + 1;\n v33 = (__int64)&a1[(unsigned int)(a2 - 2) + 2];\n do\n {\n v22 = v13;\n v13 = malloc(4LL * v14);\n if ( v14 <= 0 )\n {\n v14 = 0;\n free(v22);\n break;\n }\n v23 = *v20;\n v24 = 0;\n v25 = 0;\n v26 = 0;\n while ( v23 > v25 )\n {\n v27 = *((_DWORD *)v22 + v26);\n v28 = *(_DWORD *)(*v21 + 4LL * v25);\n if ( v27 < v28 )\n {\n ++v26;\nLABEL_14:\n if ( v26 >= v14 )\n break;\n }\n else\n {\n ++v25;\n if ( v27 > v28 )\n goto LABEL_14;\n v29 = v24;\n ++v26;\n ++v24;\n v13[v29] = v27;\n if ( v26 >= v14 )\n break;\n }\n }\n v14 = v24;\n free(v22);\n if ( !v24 )\n break;\n ++v21;\n ++v20;\n }\n while ( v21 != (_QWORD *)v33 );\nLABEL_21:\n *a4 = v14;\n return v13;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_15C0(uint64_t *a1, int a2, int *a3, int *a4) {\n int *v6;\n void **v7;\n int *v8;\n unsigned int v9;\n void *v10;\n uint32_t *v11;\n int v12;\n uint32_t *v13;\n int v14;\n int v15;\n char *v16;\n long long v17;\n long long v18;\n long long v19;\n int *v20;\n uint64_t *v21;\n void *v22;\n int v23;\n int v24;\n int v25;\n int v26;\n int v27;\n int v28;\n long long v29;\n uint32_t *v31;\n long long v33;\n if (a2 <= 0) {\n v31 = malloc(4LL * *a3);\n v12 = *a3;\n v13 = v31;\n if (*a3 <= 0) {\n v14 = 0;\n goto LABEL_21;\n }\n LABEL_5:\n v14 = 0;\n v15 = 0;\n v16 = (char *)*a1;\n v17 = 0LL;\n while (1) {\n v18 = v14;\n ++v15;\n ++v14;\n v13[v18] = *(uint32_t *)&v16[v17];\n v19 = v17;\n v17 += 4LL;\n if (v15 >= v12) goto LABEL_9;\n while (*(uint32_t *)&v16[v17] == *(uint32_t *)&v16[v19]) {\n ++v15;\n v19 = v17;\n v17 += 4LL;\n if (v15 >= v12) goto LABEL_9;\n }\n }\n }\n v6 = a3;\n v7 = (void **)a1;\n v8 = &a3[a2];\n do {\n v9 = *v6;\n v10 = *v7;\n ++v6;\n ++v7;\n qsort(v10, v9, 4uLL, compar);\n } while (v6 != v8);\n v11 = malloc(4LL * *a3);\n v12 = *a3;\n v13 = v11;\n if (*a3 > 0) goto LABEL_5;\n v14 = 0;\nLABEL_9:\n if (a2 <= 1) goto LABEL_21;\n v20 = a3 + 1;\n v21 = a1 + 1;\n v33 = (long long)&a1[(unsigned int)(a2 - 2) + 2];\n do {\n v22 = v13;\n v13 = malloc(4LL * v14);\n if (v14 <= 0) {\n v14 = 0;\n free(v22);\n break;\n }\n v23 = *v20;\n v24 = 0;\n v25 = 0;\n v26 = 0;\n while (v23 > v25) {\n v27 = *((uint32_t *)v22 + v26);\n v28 = *(uint32_t *)(*v21 + 4LL * v25);\n if (v27 < v28) {\n ++v26;\n LABEL_14:\n if (v26 >= v14) break;\n } else {\n ++v25;\n if (v27 > v28) goto LABEL_14;\n v29 = v24;\n ++v26;\n ++v24;\n v13[v29] = v27;\n if (v26 >= v14) break;\n }\n }\n v14 = v24;\n free(v22);\n if (!v24) break;\n ++v21;\n ++v20;\n } while (v21 != (uint64_t *)v33);\nLABEL_21:\n *a4 = v14;\n return v13;\n}", + "ida_pseudo_norm": "uint32_t *func0_part_0(uint64_t *a1, int a2, int *a3, int *a4) {\n int *v6;\n void **v7;\n int *v8;\n unsigned int v9;\n void *v10;\n uint32_t *v11;\n int v12;\n uint32_t *v13;\n int v14;\n int v15;\n char *v16;\n long long v17;\n long long v18;\n long long v19;\n int *v20;\n uint64_t *v21;\n void *v22;\n int v23;\n int v24;\n int v25;\n int v26;\n int v27;\n int v28;\n long long v29;\n uint32_t *v31;\n long long v33;\n if (a2 <= 0) {\n v31 = malloc(4LL * *a3);\n v12 = *a3;\n v13 = v31;\n if (*a3 <= 0) {\n v14 = 0;\n goto LABEL_21;\n }\n LABEL_5:\n v14 = 0;\n v15 = 0;\n v16 = (char *)*a1;\n v17 = 0LL;\n while (1) {\n v18 = v14;\n ++v15;\n ++v14;\n v13[v18] = *(uint32_t *)&v16[v17];\n v19 = v17;\n v17 += 4LL;\n if (v15 >= v12) goto LABEL_9;\n while (*(uint32_t *)&v16[v17] == *(uint32_t *)&v16[v19]) {\n ++v15;\n v19 = v17;\n v17 += 4LL;\n if (v15 >= v12) goto LABEL_9;\n }\n }\n }\n v6 = a3;\n v7 = (void **)a1;\n v8 = &a3[a2];\n do {\n v9 = *v6;\n v10 = *v7;\n ++v6;\n ++v7;\n qsort(v10, v9, 4uLL, cmpfunc);\n } while (v6 != v8);\n v11 = malloc(4LL * *a3);\n v12 = *a3;\n v13 = v11;\n if (*a3 > 0) goto LABEL_5;\n v14 = 0;\nLABEL_9:\n if (a2 <= 1) goto LABEL_21;\n v20 = a3 + 1;\n v21 = a1 + 1;\n v33 = (long long)&a1[(unsigned int)(a2 - 2) + 2];\n do {\n v22 = v13;\n v13 = malloc(4LL * v14);\n if (v14 <= 0) {\n v14 = 0;\n free(v22);\n break;\n }\n v23 = *v20;\n v24 = 0;\n v25 = 0;\n v26 = 0;\n while (v23 > v25) {\n v27 = *((uint32_t *)v22 + v26);\n v28 = *(uint32_t *)(*v21 + 4LL * v25);\n if (v27 < v28) {\n ++v26;\n LABEL_14:\n if (v26 >= v14) break;\n } else {\n ++v25;\n if (v27 > v28) goto LABEL_14;\n v29 = v24;\n ++v26;\n ++v24;\n v13[v29] = v27;\n if (v26 >= v14) break;\n }\n }\n v14 = v24;\n free(v22);\n if (!v24) break;\n ++v21;\n ++v20;\n } while (v21 != (uint64_t *)v33);\nLABEL_21:\n *a4 = v14;\n return v13;\n}" + }, + { + "index": 111, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n// Function to compare integers for qsort\n\nint cmpfunc(const void *a, const void *b) {\n\n return (*(int*)a - *(int*)b);\n\n}\n\n\n\n// Function to find common elements in nested lists\n\n", + "func": "int *func0(int **nestedlist, int num_lists, int *sizes, int *result_size) {\n if (num_lists == 0) {\n *result_size = 0;\n return NULL;\n }\n for (int i = 0; i < num_lists; i++) {\n qsort(nestedlist[i], sizes[i], sizeof(int), cmpfunc);\n }\n int *temp = malloc(sizes[0] * sizeof(int));\n int temp_size = 0;\n for (int i = 0; i < sizes[0]; i++) {\n if (i == 0 || nestedlist[0][i] != nestedlist[0][i - 1]) {\n temp[temp_size++] = nestedlist[0][i];\n }\n }\n for (int i = 1; i < num_lists; i++) {\n int *new_temp = malloc(temp_size * sizeof(int));\n int new_size = 0;\n int j = 0, k = 0;\n while (j < temp_size && k < sizes[i]) {\n if (temp[j] < nestedlist[i][k]) {\n j++;\n }\n else if (temp[j] > nestedlist[i][k]) {\n k++;\n }\n else {\n new_temp[new_size++] = temp[j];\n j++;\n k++;\n }\n }\n free(temp);\n temp = new_temp;\n temp_size = new_size;\n if (temp_size == 0) break;\n }\n *result_size = temp_size;\n return temp;\n}", + "test": "int main() {\n\n // First test case\n\n int list1_1[] = {12, 18, 23, 25, 45};\n\n int list1_2[] = {7, 12, 18, 24, 28};\n\n int list1_3[] = {1, 5, 8, 12, 15, 16, 18};\n\n int *nested1[] = {list1_1, list1_2, list1_3};\n\n int sizes1[] = {5, 5, 7};\n\n int result_size1;\n\n int *result1 = func0(nested1, 3, sizes1, &result_size1);\n\n qsort(result1, result_size1, sizeof(int), cmpfunc);\n\n assert(result_size1 == 2 && result1[0] == 12 && result1[1] == 18);\n\n free(result1);\n\n\n\n // Second test case\n\n int list2_1[] = {12, 5, 23, 25, 45};\n\n int list2_2[] = {7, 11, 5, 23, 28};\n\n int list2_3[] = {1, 5, 8, 18, 23, 16};\n\n int *nested2[] = {list2_1, list2_2, list2_3};\n\n int sizes2[] = {5, 5, 6};\n\n int result_size2;\n\n int *result2 = func0(nested2, 3, sizes2, &result_size2);\n\n qsort(result2, result_size2, sizeof(int), cmpfunc);\n\n assert(result_size2 == 2 && result2[0] == 5 && result2[1] == 23);\n\n free(result2);\n\n\n\n // Third test case\n\n int list3_1[] = {2, 3, 4, 1};\n\n int list3_2[] = {4, 5};\n\n int list3_3[] = {6, 4, 8};\n\n int list3_4[] = {4, 5};\n\n int list3_5[] = {6, 8, 4};\n\n int *nested3[] = {list3_1, list3_2, list3_3, list3_4, list3_5};\n\n int sizes3[] = {4, 2, 3, 2, 3};\n\n int result_size3;\n\n int *result3 = func0(nested3, 5, sizes3, &result_size3);\n\n qsort(result3, result_size3, sizeof(int), cmpfunc);\n\n assert(result_size3 == 1 && result3[0] == 4);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\nje 1740 \njmpq 1590 \nnopl (%rax)\nmovl $0x0,(%rcx)\nxor %eax,%eax\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0_part_0:\npush r15\npush r14\npush r13\npush r12\npush rbp\nmov ebp, esi\npush rbx\nmov rbx, rdx\nsub rsp, 18h\nmovsxd rax, dword ptr [rdx]\nmov [rsp+48h+var_48], rdi\nmov [rsp+48h+var_40], rcx\ntest esi, esi\njle loc_1750\nmov r15, rdx\nmovsxd rdx, esi\nlea r13, cmpfunc\nmov r12, rdi\nlea r14, [rbx+rdx*4]\nnop dword ptr [rax+rax+00h]\nloc_1600:\nmovsxd rsi, dword ptr [r15]; nmemb\nmov rdi, [r12]; base\nmov rcx, r13; compar\nmov edx, 4; size\nadd r15, 4\nadd r12, 8\ncall _qsort\ncmp r14, r15\njnz short loc_1600\nmovsxd rdi, dword ptr [rbx]\nshl rdi, 2; size\ncall _malloc\nmov edi, [rbx]\nmov r12, rax\ntest edi, edi\njle loc_176F\nloc_163A:\nmov rax, [rsp+48h+var_48]\nxor r13d, r13d\nmov rdx, [rax]\nxor eax, eax\nnop word ptr [rax+rax+00000000h]\nloc_1650:\nlea rcx, ds:0[rax*4]\ntest rax, rax\njz short loc_1666\nmov esi, [rdx+rax*4-4]\ncmp [rdx+rax*4], esi\njz short loc_1674\nloc_1666:\nmov esi, [rdx+rcx]\nmovsxd rcx, r13d\nadd r13d, 1\nmov [r12+rcx*4], esi\nloc_1674:\nadd rax, 1\ncmp edi, eax\njg short loc_1650\nloc_167C:\ncmp ebp, 1\njle loc_1729\nmov rdi, [rsp+48h+var_48]\nlea eax, [rbp-2]\nadd rbx, 4\nlea rax, [rdi+rax*8+10h]\nlea r14, [rdi+8]\nmov [rsp+48h+var_48], rax\nnop dword ptr [rax]\nloc_16A0:\nmovsxd rdi, r13d\nmov r15, r12\nshl rdi, 2; size\ncall _malloc\nmov r12, rax\ntest r13d, r13d\njle loc_1743\nmov edi, [rbx]\nxor ebp, ebp\nxor ecx, ecx\nxor edx, edx\njmp short loc_16D0\nloc_16C8:\nadd edx, 1\nloc_16CB:\ncmp edx, r13d\njge short loc_1708\nloc_16D0:\ncmp edi, ecx\njle short loc_1708\nmovsxd rax, edx\nmov r10, [r14]\nmov esi, [r15+rax*4]\nmovsxd rax, ecx\nmov eax, [r10+rax*4]\ncmp esi, eax\njl short loc_16C8\nadd ecx, 1\ncmp esi, eax\njg short loc_16CB\nmovsxd rax, ebp\nadd edx, 1\nadd ebp, 1\nmov [r12+rax*4], esi\ncmp edx, r13d\njl short loc_16D0\nnop word ptr [rax+rax+00h]\nloc_1708:\nmov rdi, r15; ptr\nmov r13d, ebp\ncall _free\ntest ebp, ebp\njz short loc_1729\nadd rbx, 4\nadd r14, 8\ncmp [rsp+48h+var_48], r14\njnz loc_16A0\nloc_1729:\nmov rax, [rsp+48h+var_40]\nmov [rax], r13d\nadd rsp, 18h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1743:\nmov rdi, r15; ptr\nxor r13d, r13d\ncall _free\njmp short loc_1729\nloc_1750:\nlea rdi, ds:0[rax*4]; size\ncall _malloc\nmov edi, [rbx]\nmov r12, rax\ntest edi, edi\njg loc_163A\nxor r13d, r13d\njmp short loc_1729\nloc_176F:\nxor r13d, r13d\njmp loc_167C", + "ida_pseudo": "_DWORD *__fastcall func0_part_0(_QWORD *a1, int a2, int *a3, int *a4)\n{\n int *v6; // r15\n void **v7; // r12\n int *v8; // r14\n size_t v9; // rsi\n void *v10; // rdi\n _DWORD *v11; // rax\n int v12; // edi\n _DWORD *v13; // r12\n int v14; // r13d\n _DWORD *v15; // rdx\n __int64 v16; // rax\n __int64 v17; // rcx\n int *v18; // rbx\n _QWORD *v19; // r14\n void *v20; // r15\n int v21; // edi\n int v22; // ebp\n int v23; // ecx\n int v24; // edx\n int v25; // esi\n int v26; // eax\n __int64 v27; // rax\n _DWORD *v29; // rax\n __int64 v31; // [rsp+0h] [rbp-48h]\n\n if ( a2 <= 0 )\n {\n v29 = malloc(4LL * *a3);\n v12 = *a3;\n v13 = v29;\n if ( *a3 <= 0 )\n {\n v14 = 0;\n goto LABEL_22;\n }\n goto LABEL_5;\n }\n v6 = a3;\n v7 = (void **)a1;\n v8 = &a3[a2];\n do\n {\n v9 = *v6;\n v10 = *v7;\n ++v6;\n ++v7;\n qsort(v10, v9, 4uLL, cmpfunc);\n }\n while ( v8 != v6 );\n v11 = malloc(4LL * *a3);\n v12 = *a3;\n v13 = v11;\n if ( *a3 > 0 )\n {\nLABEL_5:\n v14 = 0;\n v15 = (_DWORD *)*a1;\n v16 = 0LL;\n do\n {\n if ( !v16 || v15[v16] != v15[v16 - 1] )\n {\n v17 = v14++;\n v13[v17] = v15[v16];\n }\n ++v16;\n }\n while ( v12 > (int)v16 );\n goto LABEL_10;\n }\n v14 = 0;\nLABEL_10:\n if ( a2 <= 1 )\n goto LABEL_22;\n v18 = a3 + 1;\n v19 = a1 + 1;\n v31 = (__int64)&a1[(unsigned int)(a2 - 2) + 2];\n do\n {\n v20 = v13;\n v13 = malloc(4LL * v14);\n if ( v14 <= 0 )\n {\n v14 = 0;\n free(v20);\n break;\n }\n v21 = *v18;\n v22 = 0;\n v23 = 0;\n v24 = 0;\n while ( v21 > v23 )\n {\n v25 = *((_DWORD *)v20 + v24);\n v26 = *(_DWORD *)(*v19 + 4LL * v23);\n if ( v25 < v26 )\n {\n ++v24;\nLABEL_15:\n if ( v24 >= v14 )\n break;\n }\n else\n {\n ++v23;\n if ( v25 > v26 )\n goto LABEL_15;\n v27 = v22;\n ++v24;\n ++v22;\n v13[v27] = v25;\n if ( v24 >= v14 )\n break;\n }\n }\n v14 = v22;\n free(v20);\n if ( !v22 )\n break;\n ++v18;\n ++v19;\n }\n while ( (_QWORD *)v31 != v19 );\nLABEL_22:\n *a4 = v14;\n return v13;\n}", + "ida_strip_asm": "sub_15C0:\npush r15\npush r14\npush r13\npush r12\npush rbp\nmov ebp, esi\npush rbx\nmov rbx, rdx\nsub rsp, 18h\nmovsxd rax, dword ptr [rdx]\nmov [rsp+48h+var_48], rdi\nmov [rsp+48h+var_40], rcx\ntest esi, esi\njle loc_1750\nmov r15, rdx\nmovsxd rdx, esi\nlea r13, compar\nmov r12, rdi\nlea r14, [rbx+rdx*4]\nnop dword ptr [rax+rax+00h]\nloc_1600:\nmovsxd rsi, dword ptr [r15]; nmemb\nmov rdi, [r12]; base\nmov rcx, r13; compar\nmov edx, 4; size\nadd r15, 4\nadd r12, 8\ncall _qsort\ncmp r14, r15\njnz short loc_1600\nmovsxd rdi, dword ptr [rbx]\nshl rdi, 2; size\ncall _malloc\nmov edi, [rbx]\nmov r12, rax\ntest edi, edi\njle loc_176F\nloc_163A:\nmov rax, [rsp+48h+var_48]\nxor r13d, r13d\nmov rdx, [rax]\nxor eax, eax\nnop word ptr [rax+rax+00000000h]\nloc_1650:\nlea rcx, ds:0[rax*4]\ntest rax, rax\njz short loc_1666\nmov esi, [rdx+rax*4-4]\ncmp [rdx+rax*4], esi\njz short loc_1674\nloc_1666:\nmov esi, [rdx+rcx]\nmovsxd rcx, r13d\nadd r13d, 1\nmov [r12+rcx*4], esi\nloc_1674:\nadd rax, 1\ncmp edi, eax\njg short loc_1650\nloc_167C:\ncmp ebp, 1\njle loc_1729\nmov rdi, [rsp+48h+var_48]\nlea eax, [rbp-2]\nadd rbx, 4\nlea rax, [rdi+rax*8+10h]\nlea r14, [rdi+8]\nmov [rsp+48h+var_48], rax\nnop dword ptr [rax]\nloc_16A0:\nmovsxd rdi, r13d\nmov r15, r12\nshl rdi, 2; size\ncall _malloc\nmov r12, rax\ntest r13d, r13d\njle loc_1743\nmov edi, [rbx]\nxor ebp, ebp\nxor ecx, ecx\nxor edx, edx\njmp short loc_16D0\nloc_16C8:\nadd edx, 1\nloc_16CB:\ncmp edx, r13d\njge short loc_1708\nloc_16D0:\ncmp edi, ecx\njle short loc_1708\nmovsxd rax, edx\nmov r10, [r14]\nmov esi, [r15+rax*4]\nmovsxd rax, ecx\nmov eax, [r10+rax*4]\ncmp esi, eax\njl short loc_16C8\nadd ecx, 1\ncmp esi, eax\njg short loc_16CB\nmovsxd rax, ebp\nadd edx, 1\nadd ebp, 1\nmov [r12+rax*4], esi\ncmp edx, r13d\njl short loc_16D0\nnop word ptr [rax+rax+00h]\nloc_1708:\nmov rdi, r15; ptr\nmov r13d, ebp\ncall _free\ntest ebp, ebp\njz short loc_1729\nadd rbx, 4\nadd r14, 8\ncmp [rsp+48h+var_48], r14\njnz loc_16A0\nloc_1729:\nmov rax, [rsp+48h+var_40]\nmov [rax], r13d\nadd rsp, 18h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1743:\nmov rdi, r15; ptr\nxor r13d, r13d\ncall _free\njmp short loc_1729\nloc_1750:\nlea rdi, ds:0[rax*4]; size\ncall _malloc\nmov edi, [rbx]\nmov r12, rax\ntest edi, edi\njg loc_163A\nxor r13d, r13d\njmp short loc_1729\nloc_176F:\nxor r13d, r13d\njmp loc_167C", + "ida_strip_pseudo": "_DWORD *__fastcall sub_15C0(_QWORD *a1, int a2, int *a3, int *a4)\n{\n int *v6; // r15\n void **v7; // r12\n int *v8; // r14\n size_t v9; // rsi\n void *v10; // rdi\n _DWORD *v11; // rax\n int v12; // edi\n _DWORD *v13; // r12\n int v14; // r13d\n _DWORD *v15; // rdx\n __int64 v16; // rax\n __int64 v17; // rcx\n int *v18; // rbx\n _QWORD *v19; // r14\n void *v20; // r15\n int v21; // edi\n int v22; // ebp\n int v23; // ecx\n int v24; // edx\n int v25; // esi\n int v26; // eax\n __int64 v27; // rax\n _DWORD *v29; // rax\n __int64 v31; // [rsp+0h] [rbp-48h]\n\n if ( a2 <= 0 )\n {\n v29 = malloc(4LL * *a3);\n v12 = *a3;\n v13 = v29;\n if ( *a3 <= 0 )\n {\n v14 = 0;\n goto LABEL_22;\n }\n goto LABEL_5;\n }\n v6 = a3;\n v7 = (void **)a1;\n v8 = &a3[a2];\n do\n {\n v9 = *v6;\n v10 = *v7;\n ++v6;\n ++v7;\n qsort(v10, v9, 4uLL, compar);\n }\n while ( v8 != v6 );\n v11 = malloc(4LL * *a3);\n v12 = *a3;\n v13 = v11;\n if ( *a3 > 0 )\n {\nLABEL_5:\n v14 = 0;\n v15 = (_DWORD *)*a1;\n v16 = 0LL;\n do\n {\n if ( !v16 || v15[v16] != v15[v16 - 1] )\n {\n v17 = v14++;\n v13[v17] = v15[v16];\n }\n ++v16;\n }\n while ( v12 > (int)v16 );\n goto LABEL_10;\n }\n v14 = 0;\nLABEL_10:\n if ( a2 <= 1 )\n goto LABEL_22;\n v18 = a3 + 1;\n v19 = a1 + 1;\n v31 = (__int64)&a1[(unsigned int)(a2 - 2) + 2];\n do\n {\n v20 = v13;\n v13 = malloc(4LL * v14);\n if ( v14 <= 0 )\n {\n v14 = 0;\n free(v20);\n break;\n }\n v21 = *v18;\n v22 = 0;\n v23 = 0;\n v24 = 0;\n while ( v21 > v23 )\n {\n v25 = *((_DWORD *)v20 + v24);\n v26 = *(_DWORD *)(*v19 + 4LL * v23);\n if ( v25 < v26 )\n {\n ++v24;\nLABEL_15:\n if ( v24 >= v14 )\n break;\n }\n else\n {\n ++v23;\n if ( v25 > v26 )\n goto LABEL_15;\n v27 = v22;\n ++v24;\n ++v22;\n v13[v27] = v25;\n if ( v24 >= v14 )\n break;\n }\n }\n v14 = v22;\n free(v20);\n if ( !v22 )\n break;\n ++v18;\n ++v19;\n }\n while ( (_QWORD *)v31 != v19 );\nLABEL_22:\n *a4 = v14;\n return v13;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_15C0(uint64_t *a1, int a2, int *a3, int *a4) {\n int *v6;\n void **v7;\n int *v8;\n unsigned int v9;\n void *v10;\n uint32_t *v11;\n int v12;\n uint32_t *v13;\n int v14;\n uint32_t *v15;\n long long v16;\n long long v17;\n int *v18;\n uint64_t *v19;\n void *v20;\n int v21;\n int v22;\n int v23;\n int v24;\n int v25;\n int v26;\n long long v27;\n uint32_t *v29;\n long long v31;\n if (a2 <= 0) {\n v29 = malloc(4LL * *a3);\n v12 = *a3;\n v13 = v29;\n if (*a3 <= 0) {\n v14 = 0;\n goto LABEL_22;\n }\n goto LABEL_5;\n }\n v6 = a3;\n v7 = (void **)a1;\n v8 = &a3[a2];\n do {\n v9 = *v6;\n v10 = *v7;\n ++v6;\n ++v7;\n qsort(v10, v9, 4uLL, compar);\n } while (v8 != v6);\n v11 = malloc(4LL * *a3);\n v12 = *a3;\n v13 = v11;\n if (*a3 > 0) {\n LABEL_5:\n v14 = 0;\n v15 = (uint32_t *)*a1;\n v16 = 0LL;\n do {\n if (!v16 || v15[v16] != v15[v16 - 1]) {\n v17 = v14++;\n v13[v17] = v15[v16];\n }\n ++v16;\n } while (v12 > (int)v16);\n goto LABEL_10;\n }\n v14 = 0;\nLABEL_10:\n if (a2 <= 1) goto LABEL_22;\n v18 = a3 + 1;\n v19 = a1 + 1;\n v31 = (long long)&a1[(unsigned int)(a2 - 2) + 2];\n do {\n v20 = v13;\n v13 = malloc(4LL * v14);\n if (v14 <= 0) {\n v14 = 0;\n free(v20);\n break;\n }\n v21 = *v18;\n v22 = 0;\n v23 = 0;\n v24 = 0;\n while (v21 > v23) {\n v25 = *((uint32_t *)v20 + v24);\n v26 = *(uint32_t *)(*v19 + 4LL * v23);\n if (v25 < v26) {\n ++v24;\n LABEL_15:\n if (v24 >= v14) break;\n } else {\n ++v23;\n if (v25 > v26) goto LABEL_15;\n v27 = v22;\n ++v24;\n ++v22;\n v13[v27] = v25;\n if (v24 >= v14) break;\n }\n }\n v14 = v22;\n free(v20);\n if (!v22) break;\n ++v18;\n ++v19;\n } while ((uint64_t *)v31 != v19);\nLABEL_22:\n *a4 = v14;\n return v13;\n}", + "ida_pseudo_norm": "uint32_t *func0_part_0(uint64_t *a1, int a2, int *a3, int *a4) {\n int *v6;\n void **v7;\n int *v8;\n unsigned int v9;\n void *v10;\n uint32_t *v11;\n int v12;\n uint32_t *v13;\n int v14;\n uint32_t *v15;\n long long v16;\n long long v17;\n int *v18;\n uint64_t *v19;\n void *v20;\n int v21;\n int v22;\n int v23;\n int v24;\n int v25;\n int v26;\n long long v27;\n uint32_t *v29;\n long long v31;\n if (a2 <= 0) {\n v29 = malloc(4LL * *a3);\n v12 = *a3;\n v13 = v29;\n if (*a3 <= 0) {\n v14 = 0;\n goto LABEL_22;\n }\n goto LABEL_5;\n }\n v6 = a3;\n v7 = (void **)a1;\n v8 = &a3[a2];\n do {\n v9 = *v6;\n v10 = *v7;\n ++v6;\n ++v7;\n qsort(v10, v9, 4uLL, cmpfunc);\n } while (v8 != v6);\n v11 = malloc(4LL * *a3);\n v12 = *a3;\n v13 = v11;\n if (*a3 > 0) {\n LABEL_5:\n v14 = 0;\n v15 = (uint32_t *)*a1;\n v16 = 0LL;\n do {\n if (!v16 || v15[v16] != v15[v16 - 1]) {\n v17 = v14++;\n v13[v17] = v15[v16];\n }\n ++v16;\n } while (v12 > (int)v16);\n goto LABEL_10;\n }\n v14 = 0;\nLABEL_10:\n if (a2 <= 1) goto LABEL_22;\n v18 = a3 + 1;\n v19 = a1 + 1;\n v31 = (long long)&a1[(unsigned int)(a2 - 2) + 2];\n do {\n v20 = v13;\n v13 = malloc(4LL * v14);\n if (v14 <= 0) {\n v14 = 0;\n free(v20);\n break;\n }\n v21 = *v18;\n v22 = 0;\n v23 = 0;\n v24 = 0;\n while (v21 > v23) {\n v25 = *((uint32_t *)v20 + v24);\n v26 = *(uint32_t *)(*v19 + 4LL * v23);\n if (v25 < v26) {\n ++v24;\n LABEL_15:\n if (v24 >= v14) break;\n } else {\n ++v23;\n if (v25 > v26) goto LABEL_15;\n v27 = v22;\n ++v24;\n ++v22;\n v13[v27] = v25;\n if (v24 >= v14) break;\n }\n }\n v14 = v22;\n free(v20);\n if (!v22) break;\n ++v18;\n ++v19;\n } while ((uint64_t *)v31 != v19);\nLABEL_22:\n *a4 = v14;\n return v13;\n}" + }, + { + "index": 112, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int diameter, int height) { return 2 * (diameter + height); }", + "test": "int main() {\n\n assert(func0(2, 4) == 12);\n\n assert(func0(1, 2) == 6);\n\n assert(func0(3, 1) == 8);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov %esi,-0x8(%rbp)\nmov -0x4(%rbp),%edx\nmov -0x8(%rbp),%eax\nadd %edx,%eax\nadd %eax,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov edx, [rbp+var_4]\nmov eax, [rbp+var_8]\nadd eax, edx\nadd eax, eax\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n return (unsigned int)(2 * (a1 + a2));\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov edx, [rbp+var_4]\nmov eax, [rbp+var_8]\nadd eax, edx\nadd eax, eax\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2)\n{\n return (unsigned int)(2 * (a1 + a2));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2) { return (unsigned int)(2 * (a1 + a2)); }", + "ida_pseudo_norm": "long long func0(int a1, int a2) { return (unsigned int)(2 * (a1 + a2)); }" + }, + { + "index": 113, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *text) {\n int len = strlen(text);\n int i;\n while (*text == ' ') {\n text++;\n len--;\n }\n if (len < 1) {\n return -1;\n } else {\n if (text[0] == '+' || text[0] == '-') {\n for (i = 1; i < len; i++) {\n if (text[i] < '0' || text[i] > '9') {\n return 0;\n }\n }\n return 1;\n } else {\n for (i = 0; i < len; i++) {\n if (text[i] < '0' || text[i] > '9') {\n return 0;\n }\n }\n return 1;\n }\n }\n}", + "test": "int main() {\n\n assert(func0(\"python\") == 0);\n\n assert(func0(\"1\") == 1);\n\n assert(func0(\"12345\") == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov -0x18(%rbp),%rax\nmov %rax,%rdi\ncallq 1060 \nmov %eax,-0x8(%rbp)\njmp 1193 \naddq $0x1,-0x18(%rbp)\nsubl $0x1,-0x8(%rbp)\nmov -0x18(%rbp),%rax\nmovzbl (%rax),%eax\ncmp $0x20,%al\nje 118a \ncmpl $0x0,-0x8(%rbp)\njg 11ae \nmov $0xffffffff,%eax\njmpq 1258 \nmov -0x18(%rbp),%rax\nmovzbl (%rax),%eax\ncmp $0x2b,%al\nje 11c4 \nmov -0x18(%rbp),%rax\nmovzbl (%rax),%eax\ncmp $0x2d,%al\njne 120f \nmovl $0x1,-0x4(%rbp)\njmp 1200 \nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x2f,%al\njle 11f5 \nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x39,%al\njle 11fc \nmov $0x0,%eax\njmp 1258 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x8(%rbp),%eax\njl 11cd \nmov $0x1,%eax\njmp 1258 \nmovl $0x0,-0x4(%rbp)\njmp 124b \nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x2f,%al\njle 1240 \nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x39,%al\njle 1247 \nmov $0x0,%eax\njmp 1258 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x8(%rbp),%eax\njl 1218 \nmov $0x1,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_8], eax\njmp short loc_1193\nloc_118A:\nadd [rbp+s], 1\nsub [rbp+var_8], 1\nloc_1193:\nmov rax, [rbp+s]\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njz short loc_118A\ncmp [rbp+var_8], 0\njg short loc_11AE\nmov eax, 0FFFFFFFFh\njmp locret_1258\nloc_11AE:\nmov rax, [rbp+s]\nmovzx eax, byte ptr [rax]\ncmp al, 2Bh ; '+'\njz short loc_11C4\nmov rax, [rbp+s]\nmovzx eax, byte ptr [rax]\ncmp al, 2Dh ; '-'\njnz short loc_120F\nloc_11C4:\nmov [rbp+var_4], 1\njmp short loc_1200\nloc_11CD:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 2Fh ; '/'\njle short loc_11F5\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 39h ; '9'\njle short loc_11FC\nloc_11F5:\nmov eax, 0\njmp short locret_1258\nloc_11FC:\nadd [rbp+var_4], 1\nloc_1200:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_8]\njl short loc_11CD\nmov eax, 1\njmp short locret_1258\nloc_120F:\nmov [rbp+var_4], 0\njmp short loc_124B\nloc_1218:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 2Fh ; '/'\njle short loc_1240\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 39h ; '9'\njle short loc_1247\nloc_1240:\nmov eax, 0\njmp short locret_1258\nloc_1247:\nadd [rbp+var_4], 1\nloc_124B:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_8]\njl short loc_1218\nmov eax, 1\nlocret_1258:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n char *s; // [rsp+8h] [rbp-18h]\n int v3; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n int j; // [rsp+1Ch] [rbp-4h]\n\n s = (char *)a1;\n v3 = strlen(a1);\n while ( *s == 32 )\n {\n ++s;\n --v3;\n }\n if ( v3 <= 0 )\n return 0xFFFFFFFFLL;\n if ( *s == 43 || *s == 45 )\n {\n for ( i = 1; i < v3; ++i )\n {\n if ( s[i] <= 47 || s[i] > 57 )\n return 0LL;\n }\n return 1LL;\n }\n else\n {\n for ( j = 0; j < v3; ++j )\n {\n if ( s[j] <= 47 || s[j] > 57 )\n return 0LL;\n }\n return 1LL;\n }\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_8], eax\njmp short loc_1193\nloc_118A:\nadd [rbp+s], 1\nsub [rbp+var_8], 1\nloc_1193:\nmov rax, [rbp+s]\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njz short loc_118A\ncmp [rbp+var_8], 0\njg short loc_11AE\nmov eax, 0FFFFFFFFh\njmp locret_1258\nloc_11AE:\nmov rax, [rbp+s]\nmovzx eax, byte ptr [rax]\ncmp al, 2Bh ; '+'\njz short loc_11C4\nmov rax, [rbp+s]\nmovzx eax, byte ptr [rax]\ncmp al, 2Dh ; '-'\njnz short loc_120F\nloc_11C4:\nmov [rbp+var_4], 1\njmp short loc_1200\nloc_11CD:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 2Fh ; '/'\njle short loc_11F5\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 39h ; '9'\njle short loc_11FC\nloc_11F5:\nmov eax, 0\njmp short locret_1258\nloc_11FC:\nadd [rbp+var_4], 1\nloc_1200:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_8]\njl short loc_11CD\nmov eax, 1\njmp short locret_1258\nloc_120F:\nmov [rbp+var_4], 0\njmp short loc_124B\nloc_1218:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 2Fh ; '/'\njle short loc_1240\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 39h ; '9'\njle short loc_1247\nloc_1240:\nmov eax, 0\njmp short locret_1258\nloc_1247:\nadd [rbp+var_4], 1\nloc_124B:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_8]\njl short loc_1218\nmov eax, 1\nlocret_1258:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1)\n{\n char *s; // [rsp+8h] [rbp-18h]\n int v3; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n int j; // [rsp+1Ch] [rbp-4h]\n\n s = (char *)a1;\n v3 = strlen(a1);\n while ( *s == 32 )\n {\n ++s;\n --v3;\n }\n if ( v3 <= 0 )\n return 0xFFFFFFFFLL;\n if ( *s == 43 || *s == 45 )\n {\n for ( i = 1; i < v3; ++i )\n {\n if ( s[i] <= 47 || s[i] > 57 )\n return 0LL;\n }\n return 1LL;\n }\n else\n {\n for ( j = 0; j < v3; ++j )\n {\n if ( s[j] <= 47 || s[j] > 57 )\n return 0LL;\n }\n return 1LL;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1) {\n char *s;\n int v3;\n int i;\n int j;\n s = (char *)a1;\n v3 = strlen(a1);\n while (*s == 32) {\n ++s;\n --v3;\n }\n if (v3 <= 0) return 4294967295LL;\n if (*s == 43 || *s == 45) {\n for (i = 1; i < v3; ++i) {\n if (s[i] <= 47 || s[i] > 57) return 0LL;\n }\n return 1LL;\n } else {\n for (j = 0; j < v3; ++j) {\n if (s[j] <= 47 || s[j] > 57) return 0LL;\n }\n return 1LL;\n }\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n char *s;\n int v3;\n int i;\n int j;\n s = (char *)a1;\n v3 = strlen(a1);\n while (*s == 32) {\n ++s;\n --v3;\n }\n if (v3 <= 0) return 4294967295LL;\n if (*s == 43 || *s == 45) {\n for (i = 1; i < v3; ++i) {\n if (s[i] <= 47 || s[i] > 57) return 0LL;\n }\n return 1LL;\n } else {\n for (j = 0; j < v3; ++j) {\n if (s[j] <= 47 || s[j] > 57) return 0LL;\n }\n return 1LL;\n }\n}" + }, + { + "index": 113, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *text) {\n int len = strlen(text);\n int i;\n while (*text == ' ') {\n text++;\n len--;\n }\n if (len < 1) {\n return -1;\n } else {\n if (text[0] == '+' || text[0] == '-') {\n for (i = 1; i < len; i++) {\n if (text[i] < '0' || text[i] > '9') {\n return 0;\n }\n }\n return 1;\n } else {\n for (i = 0; i < len; i++) {\n if (text[i] < '0' || text[i] > '9') {\n return 0;\n }\n }\n return 1;\n }\n }\n}", + "test": "int main() {\n\n assert(func0(\"python\") == 0);\n\n assert(func0(\"1\") == 1);\n\n assert(func0(\"12345\") == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%r8\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nlea -0x1(%rcx),%rsi\nmov %esi,%edx\nmovzbl (%r8),%ecx\ncmp $0x20,%cl\njne 11c2 \nmov %r8,%rax\nadd $0x1,%rax\nmov %r8d,%edx\nsub %eax,%edx\nadd %esi,%edx\nmovzbl (%rax),%ecx\ncmp $0x20,%cl\nje 1173 \nmov $0xffffffff,%esi\ntest %edx,%edx\njle 11f8 \nsub $0x2b,%ecx\ntest $0xfd,%cl\njne 11c7 \ncmp $0x1,%edx\njle 11ec \nlea 0x1(%rax),%rcx\nlea -0x2(%rdx),%edx\nlea 0x2(%rax,%rdx,1),%rdx\nmovzbl (%rcx),%eax\nsub $0x30,%eax\ncmp $0x9,%al\nja 11f3 \nadd $0x1,%rcx\ncmp %rdx,%rcx\njne 11a8 \nmov $0x1,%esi\njmp 11f8 \nmov %r8,%rax\njmp 1186 \nmov %rax,%rcx\nlea -0x1(%rdx),%edx\nlea 0x1(%rax,%rdx,1),%rdx\nmovzbl (%rcx),%eax\nsub $0x30,%eax\ncmp $0x9,%al\nja 11fb \nadd $0x1,%rcx\ncmp %rdx,%rcx\njne 11d2 \nmov $0x1,%esi\njmp 11f8 \nmov $0x1,%esi\njmp 11f8 \nmov $0x0,%esi\nmov %esi,%eax\nretq\nmov $0x0,%esi\njmp 11f8 \n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmovzx ecx, byte ptr [rbx]\ncmp cl, 20h ; ' '\njnz short loc_11CD\nmov rdx, rbx\nloc_1181:\nadd rdx, 1\nmovzx ecx, byte ptr [rdx]\ncmp cl, 20h ; ' '\njz short loc_1181\nsub ebx, edx\nadd eax, ebx\nloc_1191:\nmov esi, 0FFFFFFFFh\ntest eax, eax\njle short loc_1200\nsub ecx, 2Bh ; '+'\ntest cl, 0FDh\njnz short loc_11D2\ncmp eax, 1\njle short loc_11F4\nlea rcx, [rdx+1]\nlea eax, [rax-2]\nlea rdx, [rdx+rax+2]\nloc_11B3:\nmovzx eax, byte ptr [rcx]\nsub eax, 30h ; '0'\ncmp al, 9\nja short loc_11FB\nadd rcx, 1\ncmp rcx, rdx\njnz short loc_11B3\nmov esi, 1\njmp short loc_1200\nloc_11CD:\nmov rdx, rbx\njmp short loc_1191\nloc_11D2:\nmov rcx, rdx\ncdqe\nadd rdx, rax\nloc_11DA:\nmovzx eax, byte ptr [rcx]\nsub eax, 30h ; '0'\ncmp al, 9\nja short loc_1204\nadd rcx, 1\ncmp rcx, rdx\njnz short loc_11DA\nmov esi, 1\njmp short loc_1200\nloc_11F4:\nmov esi, 1\njmp short loc_1200\nloc_11FB:\nmov esi, 0\nloc_1200:\nmov eax, esi\npop rbx\nretn\nloc_1204:\nmov esi, 0\njmp short loc_1200", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v1; // eax\n char v2; // cl\n const char *v3; // rdx\n unsigned int v4; // esi\n _BYTE *v5; // rcx\n __int64 v6; // rdx\n const char *v7; // rcx\n const char *v8; // rdx\n\n v1 = strlen(a1);\n v2 = *a1;\n if ( *a1 == 32 )\n {\n v3 = a1;\n do\n v2 = *++v3;\n while ( *v3 == 32 );\n v1 += (_DWORD)a1 - (_DWORD)v3;\n }\n else\n {\n v3 = a1;\n }\n v4 = -1;\n if ( v1 > 0 )\n {\n if ( ((v2 - 43) & 0xFD) != 0 )\n {\n v7 = v3;\n v8 = &v3[v1];\n while ( (unsigned __int8)(*v7 - 48) <= 9u )\n {\n if ( ++v7 == v8 )\n return 1;\n }\n return 0;\n }\n else if ( v1 <= 1 )\n {\n return 1;\n }\n else\n {\n v5 = v3 + 1;\n v6 = (__int64)&v3[v1 - 2 + 2];\n while ( (unsigned __int8)(*v5 - 48) <= 9u )\n {\n if ( ++v5 == (_BYTE *)v6 )\n return 1;\n }\n return 0;\n }\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmovzx ecx, byte ptr [rbx]\ncmp cl, 20h ; ' '\njnz short loc_11CD\nmov rdx, rbx\nloc_1181:\nadd rdx, 1\nmovzx ecx, byte ptr [rdx]\ncmp cl, 20h ; ' '\njz short loc_1181\nsub ebx, edx\nadd eax, ebx\nloc_1191:\nmov esi, 0FFFFFFFFh\ntest eax, eax\njle short loc_1200\nsub ecx, 2Bh ; '+'\ntest cl, 0FDh\njnz short loc_11D2\ncmp eax, 1\njle short loc_11F4\nlea rcx, [rdx+1]\nlea eax, [rax-2]\nlea rdx, [rdx+rax+2]\nloc_11B3:\nmovzx eax, byte ptr [rcx]\nsub eax, 30h ; '0'\ncmp al, 9\nja short loc_11FB\nadd rcx, 1\ncmp rcx, rdx\njnz short loc_11B3\nmov esi, 1\njmp short loc_1200\nloc_11CD:\nmov rdx, rbx\njmp short loc_1191\nloc_11D2:\nmov rcx, rdx\ncdqe\nadd rdx, rax\nloc_11DA:\nmovzx eax, byte ptr [rcx]\nsub eax, 30h ; '0'\ncmp al, 9\nja short loc_1204\nadd rcx, 1\ncmp rcx, rdx\njnz short loc_11DA\nmov esi, 1\njmp short loc_1200\nloc_11F4:\nmov esi, 1\njmp short loc_1200\nloc_11FB:\nmov esi, 0\nloc_1200:\nmov eax, esi\npop rbx\nretn\nloc_1204:\nmov esi, 0\njmp short loc_1200", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1)\n{\n int v1; // eax\n char v2; // cl\n const char *v3; // rdx\n unsigned int v4; // esi\n _BYTE *v5; // rcx\n __int64 v6; // rdx\n const char *v7; // rcx\n const char *v8; // rdx\n\n v1 = strlen(a1);\n v2 = *a1;\n if ( *a1 == 32 )\n {\n v3 = a1;\n do\n v2 = *++v3;\n while ( *v3 == 32 );\n v1 += (_DWORD)a1 - (_DWORD)v3;\n }\n else\n {\n v3 = a1;\n }\n v4 = -1;\n if ( v1 > 0 )\n {\n if ( ((v2 - 43) & 0xFD) != 0 )\n {\n v7 = v3;\n v8 = &v3[v1];\n while ( (unsigned __int8)(*v7 - 48) <= 9u )\n {\n if ( ++v7 == v8 )\n return 1;\n }\n return 0;\n }\n else if ( v1 <= 1 )\n {\n return 1;\n }\n else\n {\n v5 = v3 + 1;\n v6 = (__int64)&v3[v1 - 2 + 2];\n while ( (unsigned __int8)(*v5 - 48) <= 9u )\n {\n if ( ++v5 == (_BYTE *)v6 )\n return 1;\n }\n return 0;\n }\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1) {\n int v1;\n char v2;\n const char *v3;\n unsigned int v4;\n uint8_t *v5;\n long long v6;\n const char *v7;\n const char *v8;\n v1 = strlen(a1);\n v2 = *a1;\n if (*a1 == 32) {\n v3 = a1;\n do\n v2 = *++v3;\n while (*v3 == 32);\n v1 += (uint32_t)a1 - (uint32_t)v3;\n } else {\n v3 = a1;\n }\n v4 = -1;\n if (v1 > 0) {\n if (((v2 - 43) & 253) != 0) {\n v7 = v3;\n v8 = &v3[v1];\n while ((unsigned char)(*v7 - 48) <= 9u) {\n if (++v7 == v8) return 1;\n }\n return 0;\n } else if (v1 <= 1) {\n return 1;\n } else {\n v5 = v3 + 1;\n v6 = (long long)&v3[v1 - 2 + 2];\n while ((unsigned char)(*v5 - 48) <= 9u) {\n if (++v5 == (uint8_t *)v6) return 1;\n }\n return 0;\n }\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v1;\n char v2;\n const char *v3;\n unsigned int v4;\n uint8_t *v5;\n long long v6;\n const char *v7;\n const char *v8;\n v1 = strlen(a1);\n v2 = *a1;\n if (*a1 == 32) {\n v3 = a1;\n do\n v2 = *++v3;\n while (*v3 == 32);\n v1 += (uint32_t)a1 - (uint32_t)v3;\n } else {\n v3 = a1;\n }\n v4 = -1;\n if (v1 > 0) {\n if (((v2 - 43) & 253) != 0) {\n v7 = v3;\n v8 = &v3[v1];\n while ((unsigned char)(*v7 - 48) <= 9u) {\n if (++v7 == v8) return 1;\n }\n return 0;\n } else if (v1 <= 1) {\n return 1;\n } else {\n v5 = v3 + 1;\n v6 = (long long)&v3[v1 - 2 + 2];\n while ((unsigned char)(*v5 - 48) <= 9u) {\n if (++v5 == (uint8_t *)v6) return 1;\n }\n return 0;\n }\n }\n return v4;\n}" + }, + { + "index": 113, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *text) {\n int len = strlen(text);\n int i;\n while (*text == ' ') {\n text++;\n len--;\n }\n if (len < 1) {\n return -1;\n } else {\n if (text[0] == '+' || text[0] == '-') {\n for (i = 1; i < len; i++) {\n if (text[i] < '0' || text[i] > '9') {\n return 0;\n }\n }\n return 1;\n } else {\n for (i = 0; i < len; i++) {\n if (text[i] < '0' || text[i] > '9') {\n return 0;\n }\n }\n return 1;\n }\n }\n}", + "test": "int main() {\n\n assert(func0(\"python\") == 0);\n\n assert(func0(\"1\") == 1);\n\n assert(func0(\"12345\") == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\ncallq 1060 \nmovzbl (%rbx),%ecx\ncmp $0x20,%cl\njne 12c0 \nmov %rax,%rsi\nmov %rbx,%rdx\nadd $0x1,%rdx\nmov %ebx,%eax\nmovzbl (%rdx),%ecx\nsub %edx,%eax\nadd %esi,%eax\ncmp $0x20,%cl\nje 1230 \ntest %eax,%eax\njle 12b0 \nsub $0x2b,%ecx\nand $0xfd,%ecx\njne 1280 \ncmp $0x1,%eax\nje 127d \nsub $0x2,%eax\nlea 0x1(%rdx),%rcx\nlea 0x2(%rdx,%rax,1),%rdx\njmp 1271 \nnopl 0x0(%rax)\nadd $0x1,%rcx\ncmp %rcx,%rdx\nje 12a3 \nmovzbl (%rcx),%eax\nsub $0x30,%eax\ncmp $0x9,%al\njbe 1268 \nxor %eax,%eax\npop %rbx\nretq\nsub $0x1,%eax\nlea 0x1(%rdx,%rax,1),%rcx\nnopl 0x0(%rax,%rax,1)\nmovzbl (%rdx),%eax\nsub $0x30,%eax\ncmp $0x9,%al\nja 127b \nadd $0x1,%rdx\ncmp %rcx,%rdx\njne 1290 \nmov $0x1,%eax\npop %rbx\nretq\nnopw 0x0(%rax,%rax,1)\nmov $0xffffffff,%eax\npop %rbx\nretq\nnopw 0x0(%rax,%rax,1)\nmov %rbx,%rdx\njmpq 1242 \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmovzx ecx, byte ptr [rbx]\nmov rdx, rbx\ncmp cl, 20h ; ' '\njnz short loc_1241\nnop dword ptr [rax+rax+00000000h]\nloc_1230:\nmovzx ecx, byte ptr [rdx+1]\nadd rdx, 1\ncmp cl, 20h ; ' '\njz short loc_1230\nsub ebx, edx\nadd eax, ebx\nloc_1241:\ntest eax, eax\njle short loc_12C0\nsub ecx, 2Bh ; '+'\nand ecx, 0FDh\njnz short loc_1280\ncmp eax, 1\njz short loc_127D\nsub eax, 2\nlea rcx, [rdx+1]\nlea rdx, [rdx+rax+2]\njmp short loc_1271\nloc_1268:\nadd rcx, 1\ncmp rdx, rcx\njz short loc_12B0\nloc_1271:\nmovzx eax, byte ptr [rcx]\nsub eax, 30h ; '0'\ncmp al, 9\njbe short loc_1268\nloc_127B:\nxor eax, eax\nloc_127D:\npop rbx\nretn\nloc_1280:\ncdqe\nadd rax, rdx\njmp short loc_1299\nloc_1290:\nadd rdx, 1\ncmp rdx, rax\njz short loc_12B0\nloc_1299:\nmovzx esi, byte ptr [rdx]\nlea ecx, [rsi-30h]\ncmp cl, 9\njbe short loc_1290\njmp short loc_127B\nloc_12B0:\nmov eax, 1\npop rbx\nretn\nloc_12C0:\nmov eax, 0FFFFFFFFh\npop rbx\nretn", + "ida_pseudo": "size_t __fastcall func0(const char *a1)\n{\n size_t result; // rax\n char v2; // cl\n const char *v3; // rdx\n _BYTE *v4; // rcx\n __int64 v5; // rdx\n const char *v6; // rax\n\n result = strlen(a1);\n v2 = *a1;\n v3 = a1;\n if ( *a1 == 32 )\n {\n do\n v2 = *++v3;\n while ( v2 == 32 );\n result = (unsigned int)((_DWORD)a1 - (_DWORD)v3 + result);\n }\n if ( (int)result <= 0 )\n return 0xFFFFFFFFLL;\n if ( ((v2 - 43) & 0xFD) != 0 )\n {\n v6 = &v3[(int)result];\n while ( (unsigned __int8)(*v3 - 48) <= 9u )\n {\n if ( ++v3 == v6 )\n return 1LL;\n }\n }\n else\n {\n if ( (_DWORD)result == 1 )\n return result;\n v4 = v3 + 1;\n v5 = (__int64)&v3[(unsigned int)(result - 2) + 2];\n while ( (unsigned __int8)(*v4 - 48) <= 9u )\n {\n if ( (_BYTE *)v5 == ++v4 )\n return 1LL;\n }\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmovzx ecx, byte ptr [rbx]\nmov rdx, rbx\ncmp cl, 20h ; ' '\njnz short loc_1241\nnop dword ptr [rax+rax+00000000h]\nloc_1230:\nmovzx ecx, byte ptr [rdx+1]\nadd rdx, 1\ncmp cl, 20h ; ' '\njz short loc_1230\nsub ebx, edx\nadd eax, ebx\nloc_1241:\ntest eax, eax\njle short loc_12C0\nsub ecx, 2Bh ; '+'\nand ecx, 0FDh\njnz short loc_1280\ncmp eax, 1\njz short loc_127D\nsub eax, 2\nlea rcx, [rdx+1]\nlea rdx, [rdx+rax+2]\njmp short loc_1271\nloc_1268:\nadd rcx, 1\ncmp rdx, rcx\njz short loc_12B0\nloc_1271:\nmovzx eax, byte ptr [rcx]\nsub eax, 30h ; '0'\ncmp al, 9\njbe short loc_1268\nloc_127B:\nxor eax, eax\nloc_127D:\npop rbx\nretn\nloc_1280:\ncdqe\nadd rax, rdx\njmp short loc_1299\nloc_1290:\nadd rdx, 1\ncmp rdx, rax\njz short loc_12B0\nloc_1299:\nmovzx esi, byte ptr [rdx]\nlea ecx, [rsi-30h]\ncmp cl, 9\njbe short loc_1290\njmp short loc_127B\nloc_12B0:\nmov eax, 1\npop rbx\nretn\nloc_12C0:\nmov eax, 0FFFFFFFFh\npop rbx\nretn", + "ida_strip_pseudo": "size_t __fastcall sub_1210(const char *a1)\n{\n size_t result; // rax\n char v2; // cl\n const char *v3; // rdx\n _BYTE *v4; // rcx\n __int64 v5; // rdx\n const char *v6; // rax\n\n result = strlen(a1);\n v2 = *a1;\n v3 = a1;\n if ( *a1 == 32 )\n {\n do\n v2 = *++v3;\n while ( v2 == 32 );\n result = (unsigned int)((_DWORD)a1 - (_DWORD)v3 + result);\n }\n if ( (int)result <= 0 )\n return 0xFFFFFFFFLL;\n if ( ((v2 - 43) & 0xFD) != 0 )\n {\n v6 = &v3[(int)result];\n while ( (unsigned __int8)(*v3 - 48) <= 9u )\n {\n if ( ++v3 == v6 )\n return 1LL;\n }\n }\n else\n {\n if ( (_DWORD)result == 1 )\n return result;\n v4 = v3 + 1;\n v5 = (__int64)&v3[(unsigned int)(result - 2) + 2];\n while ( (unsigned __int8)(*v4 - 48) <= 9u )\n {\n if ( (_BYTE *)v5 == ++v4 )\n return 1LL;\n }\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned int sub_1210(const char *a1) {\n unsigned int result;\n char v2;\n const char *v3;\n uint8_t *v4;\n long long v5;\n const char *v6;\n result = strlen(a1);\n v2 = *a1;\n v3 = a1;\n if (*a1 == 32) {\n do\n v2 = *++v3;\n while (v2 == 32);\n result = (unsigned int)((uint32_t)a1 - (uint32_t)v3 + result);\n }\n if ((int)result <= 0) return 4294967295LL;\n if (((v2 - 43) & 253) != 0) {\n v6 = &v3[(int)result];\n while ((unsigned char)(*v3 - 48) <= 9u) {\n if (++v3 == v6) return 1LL;\n }\n } else {\n if ((uint32_t)result == 1) return result;\n v4 = v3 + 1;\n v5 = (long long)&v3[(unsigned int)(result - 2) + 2];\n while ((unsigned char)(*v4 - 48) <= 9u) {\n if ((uint8_t *)v5 == ++v4) return 1LL;\n }\n }\n return 0LL;\n}", + "ida_pseudo_norm": "unsigned int func0(const char *a1) {\n unsigned int result;\n char v2;\n const char *v3;\n uint8_t *v4;\n long long v5;\n const char *v6;\n result = strlen(a1);\n v2 = *a1;\n v3 = a1;\n if (*a1 == 32) {\n do\n v2 = *++v3;\n while (v2 == 32);\n result = (unsigned int)((uint32_t)a1 - (uint32_t)v3 + result);\n }\n if ((int)result <= 0) return 4294967295LL;\n if (((v2 - 43) & 253) != 0) {\n v6 = &v3[(int)result];\n while ((unsigned char)(*v3 - 48) <= 9u) {\n if (++v3 == v6) return 1LL;\n }\n } else {\n if ((uint32_t)result == 1) return result;\n v4 = v3 + 1;\n v5 = (long long)&v3[(unsigned int)(result - 2) + 2];\n while ((unsigned char)(*v4 - 48) <= 9u) {\n if ((uint8_t *)v5 == ++v4) return 1LL;\n }\n }\n return 0LL;\n}" + }, + { + "index": 113, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *text) {\n int len = strlen(text);\n int i;\n while (*text == ' ') {\n text++;\n len--;\n }\n if (len < 1) {\n return -1;\n } else {\n if (text[0] == '+' || text[0] == '-') {\n for (i = 1; i < len; i++) {\n if (text[i] < '0' || text[i] > '9') {\n return 0;\n }\n }\n return 1;\n } else {\n for (i = 0; i < len; i++) {\n if (text[i] < '0' || text[i] > '9') {\n return 0;\n }\n }\n return 1;\n }\n }\n}", + "test": "int main() {\n\n assert(func0(\"python\") == 0);\n\n assert(func0(\"1\") == 1);\n\n assert(func0(\"12345\") == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\ncallq 1060 \nmovzbl (%rbx),%ecx\ncmp $0x20,%cl\njne 12c0 \nmov %rax,%rsi\nmov %rbx,%rdx\nadd $0x1,%rdx\nmov %ebx,%eax\nmovzbl (%rdx),%ecx\nsub %edx,%eax\nadd %esi,%eax\ncmp $0x20,%cl\nje 1230 \ntest %eax,%eax\njle 12b0 \nsub $0x2b,%ecx\nand $0xfd,%ecx\njne 1280 \ncmp $0x1,%eax\nje 127d \nsub $0x2,%eax\nlea 0x1(%rdx),%rcx\nlea 0x2(%rdx,%rax,1),%rdx\njmp 1271 \nnopl 0x0(%rax)\nadd $0x1,%rcx\ncmp %rcx,%rdx\nje 12a3 \nmovzbl (%rcx),%eax\nsub $0x30,%eax\ncmp $0x9,%al\njbe 1268 \nxor %eax,%eax\npop %rbx\nretq\nsub $0x1,%eax\nlea 0x1(%rdx,%rax,1),%rcx\nnopl 0x0(%rax,%rax,1)\nmovzbl (%rdx),%eax\nsub $0x30,%eax\ncmp $0x9,%al\nja 127b \nadd $0x1,%rdx\ncmp %rdx,%rcx\njne 1290 \nmov $0x1,%eax\npop %rbx\nretq\nnopw 0x0(%rax,%rax,1)\nmov $0xffffffff,%eax\npop %rbx\nretq\nnopw 0x0(%rax,%rax,1)\nmov %rbx,%rdx\njmpq 1242 \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmovzx ecx, byte ptr [rbx]\nmov rdx, rbx\ncmp cl, 20h ; ' '\njnz short loc_1241\nnop dword ptr [rax+rax+00000000h]\nloc_1230:\nmovzx ecx, byte ptr [rdx+1]\nadd rdx, 1\ncmp cl, 20h ; ' '\njz short loc_1230\nsub ebx, edx\nadd eax, ebx\nloc_1241:\ntest eax, eax\njle short loc_12C0\nsub ecx, 2Bh ; '+'\nand ecx, 0FDh\njnz short loc_1280\ncmp eax, 1\njz short loc_127D\nsub eax, 2\nlea rcx, [rdx+1]\nlea rdx, [rdx+rax+2]\njmp short loc_1271\nloc_1268:\nadd rcx, 1\ncmp rdx, rcx\njz short loc_12B0\nloc_1271:\nmovzx eax, byte ptr [rcx]\nsub eax, 30h ; '0'\ncmp al, 9\njbe short loc_1268\nloc_127B:\nxor eax, eax\nloc_127D:\npop rbx\nretn\nloc_1280:\ncdqe\nadd rax, rdx\njmp short loc_1299\nloc_1290:\nadd rdx, 1\ncmp rax, rdx\njz short loc_12B0\nloc_1299:\nmovzx esi, byte ptr [rdx]\nlea ecx, [rsi-30h]\ncmp cl, 9\njbe short loc_1290\njmp short loc_127B\nloc_12B0:\nmov eax, 1\npop rbx\nretn\nloc_12C0:\nmov eax, 0FFFFFFFFh\npop rbx\nretn", + "ida_pseudo": "size_t __fastcall func0(const char *a1)\n{\n size_t result; // rax\n char v2; // cl\n const char *v3; // rdx\n _BYTE *v4; // rcx\n __int64 v5; // rdx\n const char *v6; // rax\n\n result = strlen(a1);\n v2 = *a1;\n v3 = a1;\n if ( *a1 == 32 )\n {\n do\n v2 = *++v3;\n while ( v2 == 32 );\n result = (unsigned int)((_DWORD)a1 - (_DWORD)v3 + result);\n }\n if ( (int)result <= 0 )\n return 0xFFFFFFFFLL;\n if ( ((v2 - 43) & 0xFD) != 0 )\n {\n v6 = &v3[(int)result];\n while ( (unsigned __int8)(*v3 - 48) <= 9u )\n {\n if ( v6 == ++v3 )\n return 1LL;\n }\n }\n else\n {\n if ( (_DWORD)result == 1 )\n return result;\n v4 = v3 + 1;\n v5 = (__int64)&v3[(unsigned int)(result - 2) + 2];\n while ( (unsigned __int8)(*v4 - 48) <= 9u )\n {\n if ( (_BYTE *)v5 == ++v4 )\n return 1LL;\n }\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmovzx ecx, byte ptr [rbx]\nmov rdx, rbx\ncmp cl, 20h ; ' '\njnz short loc_1241\nnop dword ptr [rax+rax+00000000h]\nloc_1230:\nmovzx ecx, byte ptr [rdx+1]\nadd rdx, 1\ncmp cl, 20h ; ' '\njz short loc_1230\nsub ebx, edx\nadd eax, ebx\nloc_1241:\ntest eax, eax\njle short loc_12C0\nsub ecx, 2Bh ; '+'\nand ecx, 0FDh\njnz short loc_1280\ncmp eax, 1\njz short loc_127D\nsub eax, 2\nlea rcx, [rdx+1]\nlea rdx, [rdx+rax+2]\njmp short loc_1271\nloc_1268:\nadd rcx, 1\ncmp rdx, rcx\njz short loc_12B0\nloc_1271:\nmovzx eax, byte ptr [rcx]\nsub eax, 30h ; '0'\ncmp al, 9\njbe short loc_1268\nloc_127B:\nxor eax, eax\nloc_127D:\npop rbx\nretn\nloc_1280:\ncdqe\nadd rax, rdx\njmp short loc_1299\nloc_1290:\nadd rdx, 1\ncmp rax, rdx\njz short loc_12B0\nloc_1299:\nmovzx esi, byte ptr [rdx]\nlea ecx, [rsi-30h]\ncmp cl, 9\njbe short loc_1290\njmp short loc_127B\nloc_12B0:\nmov eax, 1\npop rbx\nretn\nloc_12C0:\nmov eax, 0FFFFFFFFh\npop rbx\nretn", + "ida_strip_pseudo": "size_t __fastcall sub_1210(const char *a1)\n{\n size_t result; // rax\n char v2; // cl\n const char *v3; // rdx\n _BYTE *v4; // rcx\n __int64 v5; // rdx\n const char *v6; // rax\n\n result = strlen(a1);\n v2 = *a1;\n v3 = a1;\n if ( *a1 == 32 )\n {\n do\n v2 = *++v3;\n while ( v2 == 32 );\n result = (unsigned int)((_DWORD)a1 - (_DWORD)v3 + result);\n }\n if ( (int)result <= 0 )\n return 0xFFFFFFFFLL;\n if ( ((v2 - 43) & 0xFD) != 0 )\n {\n v6 = &v3[(int)result];\n while ( (unsigned __int8)(*v3 - 48) <= 9u )\n {\n if ( v6 == ++v3 )\n return 1LL;\n }\n }\n else\n {\n if ( (_DWORD)result == 1 )\n return result;\n v4 = v3 + 1;\n v5 = (__int64)&v3[(unsigned int)(result - 2) + 2];\n while ( (unsigned __int8)(*v4 - 48) <= 9u )\n {\n if ( (_BYTE *)v5 == ++v4 )\n return 1LL;\n }\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned int sub_1210(const char *a1) {\n unsigned int result;\n char v2;\n const char *v3;\n uint8_t *v4;\n long long v5;\n const char *v6;\n result = strlen(a1);\n v2 = *a1;\n v3 = a1;\n if (*a1 == 32) {\n do\n v2 = *++v3;\n while (v2 == 32);\n result = (unsigned int)((uint32_t)a1 - (uint32_t)v3 + result);\n }\n if ((int)result <= 0) return 4294967295LL;\n if (((v2 - 43) & 253) != 0) {\n v6 = &v3[(int)result];\n while ((unsigned char)(*v3 - 48) <= 9u) {\n if (v6 == ++v3) return 1LL;\n }\n } else {\n if ((uint32_t)result == 1) return result;\n v4 = v3 + 1;\n v5 = (long long)&v3[(unsigned int)(result - 2) + 2];\n while ((unsigned char)(*v4 - 48) <= 9u) {\n if ((uint8_t *)v5 == ++v4) return 1LL;\n }\n }\n return 0LL;\n}", + "ida_pseudo_norm": "unsigned int func0(const char *a1) {\n unsigned int result;\n char v2;\n const char *v3;\n uint8_t *v4;\n long long v5;\n const char *v6;\n result = strlen(a1);\n v2 = *a1;\n v3 = a1;\n if (*a1 == 32) {\n do\n v2 = *++v3;\n while (v2 == 32);\n result = (unsigned int)((uint32_t)a1 - (uint32_t)v3 + result);\n }\n if ((int)result <= 0) return 4294967295LL;\n if (((v2 - 43) & 253) != 0) {\n v6 = &v3[(int)result];\n while ((unsigned char)(*v3 - 48) <= 9u) {\n if (v6 == ++v3) return 1LL;\n }\n } else {\n if ((uint32_t)result == 1) return result;\n v4 = v3 + 1;\n v5 = (long long)&v3[(unsigned int)(result - 2) + 2];\n while ((unsigned char)(*v4 - 48) <= 9u) {\n if ((uint8_t *)v5 == ++v4) return 1LL;\n }\n }\n return 0LL;\n}" + }, + { + "index": 114, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int elements[3];\n\n int length;\n\n} Tuple;\n\n\n\ntypedef struct {\n\n Tuple tuple;\n\n int count;\n\n} TupleCount;\n\n\n\n", + "func": "char* func0(Tuple input[], int input_size) {\n TupleCount counts[input_size];\n int unique = 0;\n for (int i = 0; i < input_size; i++) {\n int found = 0;\n for (int j = 0; j < unique; j++) {\n if (counts[j].tuple.length == input[i].length) {\n int match = 1;\n for (int k = 0; k < input[i].length; k++) {\n if (counts[j].tuple.elements[k] != input[i].elements[k]) {\n match = 0;\n break;\n }\n }\n if (match) {\n counts[j].count++;\n found = 1;\n break;\n }\n }\n }\n if (!found) {\n counts[unique].tuple = input[i];\n counts[unique].count = 1;\n unique++;\n }\n }\n int size = 2;\n for (int i = 0; i < unique; i++) {\n size += 2;\n for (int j = 0; j < counts[i].tuple.length; j++) {\n char num[12];\n sprintf(num, \"%d\", counts[i].tuple.elements[j]);\n size += strlen(num) + 2;\n }\n char cnt[12];\n sprintf(cnt, \"%d\", counts[i].count);\n size += strlen(cnt) + 2;\n }\n if (unique > 0) size -= 2;\n size += 1;\n char* result = malloc(size);\n if (result == NULL) {\n fprintf(stderr, \"Memory allocation failed\\n\");\n exit(1);\n }\n strcpy(result, \"[\");\n for (int i = 0; i < unique; i++) {\n strcat(result, \"(\");\n for (int j = 0; j < counts[i].tuple.length; j++) {\n char num[12];\n sprintf(num, \"%d\", counts[i].tuple.elements[j]);\n strcat(result, num);\n if (j < counts[i].tuple.length - 1) strcat(result, \", \");\n }\n strcat(result, \", \");\n char cnt[12];\n sprintf(cnt, \"%d\", counts[i].count);\n strcat(result, cnt);\n strcat(result, \")\");\n if (i < unique - 1) strcat(result, \", \");\n }\n strcat(result, \"]\");\n return result;\n}", + "test": "int main() {\n\n // First test case\n\n Tuple test1[] = {\n\n { .elements = {6, 5, 8}, .length = 3 },\n\n { .elements = {2, 7, 0}, .length = 2 },\n\n { .elements = {6, 5, 8}, .length = 3 },\n\n { .elements = {6, 5, 8}, .length = 3 },\n\n { .elements = {9, 0, 0}, .length = 1 },\n\n { .elements = {2, 7, 0}, .length = 2 }\n\n };\n\n char* res1 = func0(test1, 6);\n\n assert(strcmp(res1, \"[(6, 5, 8, 3), (2, 7, 2), (9, 1)]\") == 0);\n\n free(res1);\n\n\n\n // Second test case\n\n Tuple test2[] = {\n\n { .elements = {4, 2, 4}, .length = 3 },\n\n { .elements = {7, 1, 0}, .length = 2 },\n\n { .elements = {4, 8, 0}, .length = 2 },\n\n { .elements = {4, 2, 4}, .length = 3 },\n\n { .elements = {9, 2, 0}, .length = 2 },\n\n { .elements = {7, 1, 0}, .length = 2 }\n\n };\n\n char* res2 = func0(test2, 6);\n\n assert(strcmp(res2, \"[(4, 2, 4, 2), (7, 1, 2), (4, 8, 1), (9, 2, 1)]\") == 0);\n\n free(res2);\n\n\n\n // Third test case\n\n Tuple test3[] = {\n\n { .elements = {11, 13, 10}, .length = 3 },\n\n { .elements = {17, 21, 0}, .length = 2 },\n\n { .elements = {4, 2, 3}, .length = 3 },\n\n { .elements = {17, 21, 0}, .length = 2 },\n\n { .elements = {9, 2, 0}, .length = 2 },\n\n { .elements = {4, 2, 3}, .length = 3 }\n\n };\n\n char* res3 = func0(test3, 6);\n\n assert(strcmp(res3, \"[(11, 13, 10, 1), (17, 21, 2), (4, 2, 3, 2), (9, 2, 1)]\") == 0);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r12\npush %rbx\nsub $0x70,%rsp\nmov %rdi,-0x78(%rbp)\nmov %esi,-0x7c(%rbp)\nmov %fs:0x28,%rsi\nmov %rsi,-0x18(%rbp)\nxor %esi,%esi\nmov %rsp,%rsi\nmov %rsi,%r12\nmov -0x7c(%rbp),%esi\nmovslq %esi,%rdi\nsub $0x1,%rdi\nmov %rdi,-0x40(%rbp)\nmovslq %esi,%rdi\nmov %rdi,%rax\nmov $0x0,%edx\nimul $0xa0,%rdx,%r8\nimul $0x0,%rax,%rdi\nadd %r8,%rdi\nmov $0xa0,%r8d\nmul %r8\nadd %rdx,%rdi\nmov %rdi,%rdx\nmovslq %esi,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmovslq %esi,%rax\nmov %rax,%rcx\nmov $0x0,%ebx\nimul $0xa0,%rbx,%rdx\nimul $0x0,%rcx,%rax\nlea (%rdx,%rax,1),%rdi\nmov $0xa0,%eax\nmul %rcx\nlea (%rdi,%rdx,1),%rcx\nmov %rcx,%rdx\nmovslq %esi,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%ebx\nmov $0x0,%edx\ndiv %rbx\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rbx\nsub %rdx,%rbx\nmov %rbx,%rdx\ncmp %rdx,%rsp\nje 135f \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 1348 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 1389 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x38(%rbp)\nmovl $0x0,-0x60(%rbp)\nmovl $0x0,-0x64(%rbp)\njmpq 154c \nmovl $0x0,-0x68(%rbp)\nmovl $0x0,-0x6c(%rbp)\njmpq 14d0 \nmov -0x38(%rbp),%rcx\nmov -0x6c(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rcx,%rax\nadd $0xc,%rax\nmov (%rax),%edx\nmov -0x64(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rcx\nmov -0x78(%rbp),%rax\nadd %rcx,%rax\nmov 0xc(%rax),%eax\ncmp %eax,%edx\njne 14cc \nmovl $0x1,-0x5c(%rbp)\nmovl $0x0,-0x58(%rbp)\njmp 145d \nmov -0x38(%rbp),%rcx\nmov -0x58(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x6c(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nadd %rsi,%rax\nmov (%rcx,%rax,4),%edx\nmov -0x64(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rcx\nmov -0x78(%rbp),%rax\nadd %rax,%rcx\nmov -0x58(%rbp),%eax\ncltq\nmov (%rcx,%rax,4),%eax\ncmp %eax,%edx\nje 1459 \nmovl $0x0,-0x5c(%rbp)\njmp 1478 \naddl $0x1,-0x58(%rbp)\nmov -0x64(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x78(%rbp),%rax\nadd %rdx,%rax\nmov 0xc(%rax),%eax\ncmp %eax,-0x58(%rbp)\njl 1411 \ncmpl $0x0,-0x5c(%rbp)\nje 14cc \nmov -0x38(%rbp),%rcx\nmov -0x6c(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rcx,%rax\nadd $0x10,%rax\nmov (%rax),%eax\nlea 0x1(%rax),%ecx\nmov -0x38(%rbp),%rsi\nmov -0x6c(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rsi,%rax\nadd $0x10,%rax\nmov %ecx,(%rax)\nmovl $0x1,-0x68(%rbp)\njmp 14dc \naddl $0x1,-0x6c(%rbp)\nmov -0x6c(%rbp),%eax\ncmp -0x60(%rbp),%eax\njl 13c2 \ncmpl $0x0,-0x68(%rbp)\njne 1548 \nmov -0x64(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x78(%rbp),%rax\nlea (%rdx,%rax,1),%rsi\nmov -0x38(%rbp),%rcx\nmov -0x60(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rax,%rcx\nmov (%rsi),%rax\nmov 0x8(%rsi),%rdx\nmov %rax,(%rcx)\nmov %rdx,0x8(%rcx)\nmov -0x38(%rbp),%rcx\nmov -0x60(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rcx,%rax\nadd $0x10,%rax\nmovl $0x1,(%rax)\naddl $0x1,-0x60(%rbp)\naddl $0x1,-0x64(%rbp)\nmov -0x64(%rbp),%eax\ncmp -0x7c(%rbp),%eax\njl 13af \nmovl $0x2,-0x54(%rbp)\nmovl $0x0,-0x50(%rbp)\njmpq 1649 \naddl $0x2,-0x54(%rbp)\nmovl $0x0,-0x4c(%rbp)\njmp 15cd \nmov -0x38(%rbp),%rcx\nmov -0x4c(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x50(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nadd %rsi,%rax\nmov (%rcx,%rax,4),%edx\nlea -0x24(%rbp),%rax\nlea 0xa65(%rip),%rsi\nmov %rax,%rdi\nmov $0x0,%eax\ncallq 1150 \nlea -0x24(%rbp),%rax\nmov %rax,%rdi\ncallq 10f0 \nmov %eax,%edx\nmov -0x54(%rbp),%eax\nadd %edx,%eax\nadd $0x2,%eax\nmov %eax,-0x54(%rbp)\naddl $0x1,-0x4c(%rbp)\nmov -0x38(%rbp),%rcx\nmov -0x50(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rcx,%rax\nadd $0xc,%rax\nmov (%rax),%eax\ncmp %eax,-0x4c(%rbp)\njl 1578 \nmov -0x38(%rbp),%rcx\nmov -0x50(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rcx,%rax\nadd $0x10,%rax\nmov (%rax),%edx\nlea -0x24(%rbp),%rax\nlea 0x9e9(%rip),%rsi\nmov %rax,%rdi\nmov $0x0,%eax\ncallq 1150 \nlea -0x24(%rbp),%rax\nmov %rax,%rdi\ncallq 10f0 \nmov %eax,%edx\nmov -0x54(%rbp),%eax\nadd %edx,%eax\nadd $0x2,%eax\nmov %eax,-0x54(%rbp)\naddl $0x1,-0x50(%rbp)\nmov -0x50(%rbp),%eax\ncmp -0x60(%rbp),%eax\njl 156b \ncmpl $0x0,-0x60(%rbp)\njle 165f \nsubl $0x2,-0x54(%rbp)\naddl $0x1,-0x54(%rbp)\nmov -0x54(%rbp),%eax\ncltq\nmov %rax,%rdi\ncallq 1130 \nmov %rax,-0x30(%rbp)\ncmpq $0x0,-0x30(%rbp)\njne 16a5 \nmov 0x299e(%rip),%rax\nmov %rax,%rcx\nmov $0x19,%edx\nmov $0x1,%esi\nlea 0x975(%rip),%rdi\ncallq 1170 \nmov $0x1,%edi\ncallq 1160 \nmov -0x30(%rbp),%rax\nmovw $0x5b,(%rax)\nmovl $0x0,-0x48(%rbp)\njmpq 18b5 \nmov -0x30(%rbp),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nmov -0x30(%rbp),%rax\nadd %rdx,%rax\nmovw $0x28,(%rax)\nmovl $0x0,-0x44(%rbp)\njmpq 179e \nmov -0x38(%rbp),%rcx\nmov -0x44(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x48(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nadd %rsi,%rax\nmov (%rcx,%rax,4),%edx\nlea -0x24(%rbp),%rax\nlea 0x8e9(%rip),%rsi\nmov %rax,%rdi\nmov $0x0,%eax\ncallq 1150 \nlea -0x24(%rbp),%rdx\nmov -0x30(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1140 \nmov -0x38(%rbp),%rcx\nmov -0x48(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rcx,%rax\nadd $0xc,%rax\nmov (%rax),%eax\nsub $0x1,%eax\ncmp %eax,-0x44(%rbp)\njge 179a \nmov -0x30(%rbp),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nmov -0x30(%rbp),%rax\nadd %rdx,%rax\nmovw $0x202c,(%rax)\nmovb $0x0,0x2(%rax)\naddl $0x1,-0x44(%rbp)\nmov -0x38(%rbp),%rcx\nmov -0x48(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rcx,%rax\nadd $0xc,%rax\nmov (%rax),%eax\ncmp %eax,-0x44(%rbp)\njl 16f4 \nmov -0x30(%rbp),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nmov -0x30(%rbp),%rax\nadd %rdx,%rax\nmovw $0x202c,(%rax)\nmovb $0x0,0x2(%rax)\nmov -0x38(%rbp),%rcx\nmov -0x48(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rcx,%rax\nadd $0x10,%rax\nmov (%rax),%edx\nlea -0x24(%rbp),%rax\nlea 0x7e2(%rip),%rsi\nmov %rax,%rdi\nmov $0x0,%eax\ncallq 1150 \nlea -0x24(%rbp),%rdx\nmov -0x30(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1140 \nmov -0x30(%rbp),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nmov -0x30(%rbp),%rax\nadd %rdx,%rax\nmovw $0x29,(%rax)\nmov -0x60(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x48(%rbp)\njge 18b1 \nmov -0x30(%rbp),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nmov -0x30(%rbp),%rax\nadd %rdx,%rax\nmovw $0x202c,(%rax)\nmovb $0x0,0x2(%rax)\naddl $0x1,-0x48(%rbp)\nmov -0x48(%rbp),%eax\ncmp -0x60(%rbp),%eax\njl 16ba \nmov -0x30(%rbp),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nmov -0x30(%rbp),%rax\nadd %rdx,%rax\nmovw $0x5d,(%rax)\nmov -0x30(%rbp),%rax\nmov %r12,%rsp\nmov -0x18(%rbp),%rbx\nxor %fs:0x28,%rbx\nje 190a \ncallq 1100 <__stack_chk_fail@plt>\nlea -0x10(%rbp),%rsp\npop %rbx\npop %r12\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 78h\nmov [rbp+var_78], rdi\nmov [rbp+var_7C], esi\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov rax, rsp\nmov rbx, rax\nmov ecx, [rbp+var_7C]\nmovsxd rax, ecx\nsub rax, 1\nmov [rbp+var_40], rax\nmovsxd rax, ecx\nmov rsi, rax\nmov edi, 0\nmov rax, rsi\nmov rdx, rdi\nshld rdx, rax, 2\nshl rax, 2\nadd rax, rsi\nadc rdx, rdi\nshld rdx, rax, 5\nshl rax, 5\nmovsxd rdx, ecx\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 2\nmovsxd rax, ecx\nmov rsi, rax\nmov edi, 0\nmov rax, rsi\nmov rdx, rdi\nshld rdx, rax, 2\nshl rax, 2\nadd rax, rsi\nadc rdx, rdi\nshld rdx, rax, 5\nshl rax, 5\nmovsxd rdx, ecx\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_1344:\ncmp rsp, rdx\njz short loc_135B\nsub rsp, 1000h\nor [rsp+1080h+var_88], 0\njmp short loc_1344\nloc_135B:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1385\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1385:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_38], rax\nmov [rbp+var_6C], 0\nmov [rbp+var_68], 0\njmp loc_1548\nloc_13AB:\nmov [rbp+var_64], 0\nmov [rbp+var_60], 0\njmp loc_14CC\nloc_13BE:\nmov rcx, [rbp+var_38]\nmov eax, [rbp+var_60]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 2\nadd rax, rcx\nadd rax, 0Ch\nmov edx, [rax]\nmov eax, [rbp+var_68]\ncdqe\nshl rax, 4\nmov rcx, rax\nmov rax, [rbp+var_78]\nadd rax, rcx\nmov eax, [rax+0Ch]\ncmp edx, eax\njnz loc_14C8\nmov [rbp+var_5C], 1\nmov [rbp+var_58], 0\njmp short loc_1459\nloc_140D:\nmov rcx, [rbp+var_38]\nmov eax, [rbp+var_58]\nmovsxd rsi, eax\nmov eax, [rbp+var_60]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nadd rax, rsi\nmov edx, [rcx+rax*4]\nmov eax, [rbp+var_68]\ncdqe\nshl rax, 4\nmov rcx, rax\nmov rax, [rbp+var_78]\nadd rcx, rax\nmov eax, [rbp+var_58]\ncdqe\nmov eax, [rcx+rax*4]\ncmp edx, eax\njz short loc_1455\nmov [rbp+var_5C], 0\njmp short loc_1474\nloc_1455:\nadd [rbp+var_58], 1\nloc_1459:\nmov eax, [rbp+var_68]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_78]\nadd rax, rdx\nmov eax, [rax+0Ch]\ncmp [rbp+var_58], eax\njl short loc_140D\nloc_1474:\ncmp [rbp+var_5C], 0\njz short loc_14C8\nmov rcx, [rbp+var_38]\nmov eax, [rbp+var_60]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 2\nadd rax, rcx\nadd rax, 10h\nmov eax, [rax]\nlea ecx, [rax+1]\nmov rsi, [rbp+var_38]\nmov eax, [rbp+var_60]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 2\nadd rax, rsi\nadd rax, 10h\nmov [rax], ecx\nmov [rbp+var_64], 1\njmp short loc_14D8\nloc_14C8:\nadd [rbp+var_60], 1\nloc_14CC:\nmov eax, [rbp+var_60]\ncmp eax, [rbp+var_6C]\njl loc_13BE\nloc_14D8:\ncmp [rbp+var_64], 0\njnz short loc_1544\nmov eax, [rbp+var_68]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_78]\nlea rsi, [rdx+rax]\nmov rcx, [rbp+var_38]\nmov eax, [rbp+var_6C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 2\nadd rcx, rax\nmov rax, [rsi]\nmov rdx, [rsi+8]\nmov [rcx], rax\nmov [rcx+8], rdx\nmov rcx, [rbp+var_38]\nmov eax, [rbp+var_6C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 2\nadd rax, rcx\nadd rax, 10h\nmov dword ptr [rax], 1\nadd [rbp+var_6C], 1\nloc_1544:\nadd [rbp+var_68], 1\nloc_1548:\nmov eax, [rbp+var_68]\ncmp eax, [rbp+var_7C]\njl loc_13AB\nmov [rbp+var_54], 2\nmov [rbp+var_50], 0\njmp loc_164B\nloc_1567:\nadd [rbp+var_54], 2\nmov [rbp+var_4C], 0\njmp short loc_15CC\nloc_1574:\nmov rcx, [rbp+var_38]\nmov eax, [rbp+var_4C]\nmovsxd rsi, eax\nmov eax, [rbp+var_50]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nadd rax, rsi\nmov edx, [rcx+rax*4]\nlea rax, [rbp+s]\nlea rcx, format; \"%d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov edx, eax\nmov eax, [rbp+var_54]\nadd eax, edx\nadd eax, 2\nmov [rbp+var_54], eax\nadd [rbp+var_4C], 1\nloc_15CC:\nmov rcx, [rbp+var_38]\nmov eax, [rbp+var_50]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 2\nadd rax, rcx\nadd rax, 0Ch\nmov eax, [rax]\ncmp [rbp+var_4C], eax\njl short loc_1574\nmov rcx, [rbp+var_38]\nmov eax, [rbp+var_50]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 2\nadd rax, rcx\nadd rax, 10h\nmov edx, [rax]\nlea rax, [rbp+s]\nlea rcx, format; \"%d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov edx, eax\nmov eax, [rbp+var_54]\nadd eax, edx\nadd eax, 2\nmov [rbp+var_54], eax\nadd [rbp+var_50], 1\nloc_164B:\nmov eax, [rbp+var_50]\ncmp eax, [rbp+var_6C]\njl loc_1567\ncmp [rbp+var_6C], 0\njle short loc_1661\nsub [rbp+var_54], 2\nloc_1661:\nadd [rbp+var_54], 1\nmov eax, [rbp+var_54]\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+dest], rax\ncmp [rbp+dest], 0\njnz short loc_16AA\nmov rax, cs:__bss_start\nmov rcx, rax; s\nmov edx, 19h; n\nmov esi, 1; size\nlea rax, aMemoryAllocati; \"Memory allocation failed\\n\"\nmov rdi, rax; ptr\ncall _fwrite\nmov edi, 1; status\ncall _exit\nloc_16AA:\nmov rax, [rbp+dest]\nmov word ptr [rax], 5Bh ; '['\nmov [rbp+var_48], 0\njmp loc_1861\nloc_16BF:\nmov rax, [rbp+dest]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+dest]\nadd rax, rdx\nmov word ptr [rax], 28h ; '('\nmov [rbp+var_44], 0\njmp loc_1780\nloc_16E6:\nmov rcx, [rbp+var_38]\nmov eax, [rbp+var_44]\nmovsxd rsi, eax\nmov eax, [rbp+var_48]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nadd rax, rsi\nmov edx, [rcx+rax*4]\nlea rax, [rbp+s]\nlea rcx, format; \"%d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rdx, [rbp+s]\nmov rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\nmov rcx, [rbp+var_38]\nmov eax, [rbp+var_48]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 2\nadd rax, rcx\nadd rax, 0Ch\nmov eax, [rax]\nsub eax, 1\ncmp [rbp+var_44], eax\njge short loc_177C\nmov rax, [rbp+dest]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+dest]\nadd rax, rdx\nmov word ptr [rax], 202Ch\nmov byte ptr [rax+2], 0\nloc_177C:\nadd [rbp+var_44], 1\nloc_1780:\nmov rcx, [rbp+var_38]\nmov eax, [rbp+var_48]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 2\nadd rax, rcx\nadd rax, 0Ch\nmov eax, [rax]\ncmp [rbp+var_44], eax\njl loc_16E6\nmov rax, [rbp+dest]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+dest]\nadd rax, rdx\nmov word ptr [rax], 202Ch\nmov byte ptr [rax+2], 0\nmov rcx, [rbp+var_38]\nmov eax, [rbp+var_48]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 2\nadd rax, rcx\nadd rax, 10h\nmov edx, [rax]\nlea rax, [rbp+s]\nlea rcx, format; \"%d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rdx, [rbp+s]\nmov rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\nmov rax, [rbp+dest]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+dest]\nadd rax, rdx\nmov word ptr [rax], 29h ; ')'\nmov eax, [rbp+var_6C]\nsub eax, 1\ncmp [rbp+var_48], eax\njge short loc_185D\nmov rax, [rbp+dest]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+dest]\nadd rax, rdx\nmov word ptr [rax], 202Ch\nmov byte ptr [rax+2], 0\nloc_185D:\nadd [rbp+var_48], 1\nloc_1861:\nmov eax, [rbp+var_48]\ncmp eax, [rbp+var_6C]\njl loc_16BF\nmov rax, [rbp+dest]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+dest]\nadd rax, rdx\nmov word ptr [rax], 5Dh ; ']'\nmov rax, [rbp+dest]\nmov rsp, rbx\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njz short loc_18A3\ncall ___stack_chk_fail\nloc_18A3:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2)\n{\n unsigned __int64 v2; // rax\n void *v3; // rsp\n _QWORD *v4; // rsi\n _QWORD *v5; // rcx\n __int64 v6; // rdx\n int v7; // eax\n int v8; // eax\n size_t v9; // rax\n size_t v10; // rax\n size_t v11; // rax\n size_t v12; // rax\n size_t v13; // rax\n size_t v14; // rax\n _BYTE v16[4]; // [rsp+8h] [rbp-80h] BYREF\n int v17; // [rsp+Ch] [rbp-7Ch]\n __int64 v18; // [rsp+10h] [rbp-78h]\n int v19; // [rsp+1Ch] [rbp-6Ch]\n int i; // [rsp+20h] [rbp-68h]\n int v21; // [rsp+24h] [rbp-64h]\n int j; // [rsp+28h] [rbp-60h]\n int v23; // [rsp+2Ch] [rbp-5Ch]\n int k; // [rsp+30h] [rbp-58h]\n int v25; // [rsp+34h] [rbp-54h]\n int m; // [rsp+38h] [rbp-50h]\n int n; // [rsp+3Ch] [rbp-4Ch]\n int ii; // [rsp+40h] [rbp-48h]\n int jj; // [rsp+44h] [rbp-44h]\n __int64 v30; // [rsp+48h] [rbp-40h]\n _BYTE *v31; // [rsp+50h] [rbp-38h]\n char *dest; // [rsp+58h] [rbp-30h]\n char s[12]; // [rsp+64h] [rbp-24h] BYREF\n unsigned __int64 v34; // [rsp+70h] [rbp-18h]\n\n v18 = a1;\n v17 = a2;\n v34 = __readfsqword(0x28u);\n v30 = a2 - 1LL;\n v2 = 16 * ((20LL * a2 + 15) / 0x10uLL);\n while ( v16 != &v16[-(v2 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = alloca(v2 & 0xFFF);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)&v16[(v2 & 0xFFF) - 8] = *(_QWORD *)&v16[(v2 & 0xFFF) - 8];\n v31 = v16;\n v19 = 0;\n for ( i = 0; i < v17; ++i )\n {\n v21 = 0;\n for ( j = 0; j < v19; ++j )\n {\n if ( *(_DWORD *)&v31[20 * j + 12] == *(_DWORD *)(16LL * i + v18 + 12) )\n {\n v23 = 1;\n for ( k = 0; k < *(_DWORD *)(16LL * i + v18 + 12); ++k )\n {\n if ( *(_DWORD *)&v31[20 * j + 4 * k] != *(_DWORD *)(v18 + 16LL * i + 4LL * k) )\n {\n v23 = 0;\n break;\n }\n }\n if ( v23 )\n {\n ++*(_DWORD *)&v31[20 * j + 16];\n v21 = 1;\n break;\n }\n }\n }\n if ( !v21 )\n {\n v4 = (_QWORD *)(16LL * i + v18);\n v5 = &v31[20 * v19];\n v6 = v4[1];\n *v5 = *v4;\n v5[1] = v6;\n *(_DWORD *)&v31[20 * v19++ + 16] = 1;\n }\n }\n v25 = 2;\n for ( m = 0; m < v19; ++m )\n {\n v25 += 2;\n for ( n = 0; n < *(_DWORD *)&v31[20 * m + 12]; ++n )\n {\n sprintf(s, \"%d\", *(_DWORD *)&v31[20 * m + 4 * n]);\n v7 = strlen(s);\n v25 += v7 + 2;\n }\n sprintf(s, \"%d\", *(_DWORD *)&v31[20 * m + 16]);\n v8 = strlen(s);\n v25 += v8 + 2;\n }\n if ( v19 > 0 )\n v25 -= 2;\n dest = (char *)malloc(++v25);\n if ( !dest )\n {\n fwrite(\"Memory allocation failed\\n\", 1uLL, 0x19uLL, _bss_start);\n exit(1);\n }\n *(_WORD *)dest = 91;\n for ( ii = 0; ii < v19; ++ii )\n {\n v9 = strlen(dest);\n *(_WORD *)&dest[v9] = 40;\n for ( jj = 0; jj < *(_DWORD *)&v31[20 * ii + 12]; ++jj )\n {\n sprintf(s, \"%d\", *(_DWORD *)&v31[20 * ii + 4 * jj]);\n strcat(dest, s);\n if ( jj < *(_DWORD *)&v31[20 * ii + 12] - 1 )\n {\n v10 = strlen(dest);\n strcpy(&dest[v10], \", \");\n }\n }\n v11 = strlen(dest);\n strcpy(&dest[v11], \", \");\n sprintf(s, \"%d\", *(_DWORD *)&v31[20 * ii + 16]);\n strcat(dest, s);\n v12 = strlen(dest);\n *(_WORD *)&dest[v12] = 41;\n if ( ii < v19 - 1 )\n {\n v13 = strlen(dest);\n strcpy(&dest[v13], \", \");\n }\n }\n v14 = strlen(dest);\n *(_WORD *)&dest[v14] = 93;\n return dest;\n}", + "ida_strip_asm": "sub_1269:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 78h\nmov [rbp+var_78], rdi\nmov [rbp+var_7C], esi\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov rax, rsp\nmov rbx, rax\nmov ecx, [rbp+var_7C]\nmovsxd rax, ecx\nsub rax, 1\nmov [rbp+var_40], rax\nmovsxd rax, ecx\nmov rsi, rax\nmov edi, 0\nmov rax, rsi\nmov rdx, rdi\nshld rdx, rax, 2\nshl rax, 2\nadd rax, rsi\nadc rdx, rdi\nshld rdx, rax, 5\nshl rax, 5\nmovsxd rdx, ecx\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 2\nmovsxd rax, ecx\nmov rsi, rax\nmov edi, 0\nmov rax, rsi\nmov rdx, rdi\nshld rdx, rax, 2\nshl rax, 2\nadd rax, rsi\nadc rdx, rdi\nshld rdx, rax, 5\nshl rax, 5\nmovsxd rdx, ecx\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_1344:\ncmp rsp, rdx\njz short loc_135B\nsub rsp, 1000h\nor [rsp+1080h+var_88], 0\njmp short loc_1344\nloc_135B:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1385\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1385:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_38], rax\nmov [rbp+var_6C], 0\nmov [rbp+var_68], 0\njmp loc_1548\nloc_13AB:\nmov [rbp+var_64], 0\nmov [rbp+var_60], 0\njmp loc_14CC\nloc_13BE:\nmov rcx, [rbp+var_38]\nmov eax, [rbp+var_60]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 2\nadd rax, rcx\nadd rax, 0Ch\nmov edx, [rax]\nmov eax, [rbp+var_68]\ncdqe\nshl rax, 4\nmov rcx, rax\nmov rax, [rbp+var_78]\nadd rax, rcx\nmov eax, [rax+0Ch]\ncmp edx, eax\njnz loc_14C8\nmov [rbp+var_5C], 1\nmov [rbp+var_58], 0\njmp short loc_1459\nloc_140D:\nmov rcx, [rbp+var_38]\nmov eax, [rbp+var_58]\nmovsxd rsi, eax\nmov eax, [rbp+var_60]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nadd rax, rsi\nmov edx, [rcx+rax*4]\nmov eax, [rbp+var_68]\ncdqe\nshl rax, 4\nmov rcx, rax\nmov rax, [rbp+var_78]\nadd rcx, rax\nmov eax, [rbp+var_58]\ncdqe\nmov eax, [rcx+rax*4]\ncmp edx, eax\njz short loc_1455\nmov [rbp+var_5C], 0\njmp short loc_1474\nloc_1455:\nadd [rbp+var_58], 1\nloc_1459:\nmov eax, [rbp+var_68]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_78]\nadd rax, rdx\nmov eax, [rax+0Ch]\ncmp [rbp+var_58], eax\njl short loc_140D\nloc_1474:\ncmp [rbp+var_5C], 0\njz short loc_14C8\nmov rcx, [rbp+var_38]\nmov eax, [rbp+var_60]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 2\nadd rax, rcx\nadd rax, 10h\nmov eax, [rax]\nlea ecx, [rax+1]\nmov rsi, [rbp+var_38]\nmov eax, [rbp+var_60]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 2\nadd rax, rsi\nadd rax, 10h\nmov [rax], ecx\nmov [rbp+var_64], 1\njmp short loc_14D8\nloc_14C8:\nadd [rbp+var_60], 1\nloc_14CC:\nmov eax, [rbp+var_60]\ncmp eax, [rbp+var_6C]\njl loc_13BE\nloc_14D8:\ncmp [rbp+var_64], 0\njnz short loc_1544\nmov eax, [rbp+var_68]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_78]\nlea rsi, [rdx+rax]\nmov rcx, [rbp+var_38]\nmov eax, [rbp+var_6C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 2\nadd rcx, rax\nmov rax, [rsi]\nmov rdx, [rsi+8]\nmov [rcx], rax\nmov [rcx+8], rdx\nmov rcx, [rbp+var_38]\nmov eax, [rbp+var_6C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 2\nadd rax, rcx\nadd rax, 10h\nmov dword ptr [rax], 1\nadd [rbp+var_6C], 1\nloc_1544:\nadd [rbp+var_68], 1\nloc_1548:\nmov eax, [rbp+var_68]\ncmp eax, [rbp+var_7C]\njl loc_13AB\nmov [rbp+var_54], 2\nmov [rbp+var_50], 0\njmp loc_164B\nloc_1567:\nadd [rbp+var_54], 2\nmov [rbp+var_4C], 0\njmp short loc_15CC\nloc_1574:\nmov rcx, [rbp+var_38]\nmov eax, [rbp+var_4C]\nmovsxd rsi, eax\nmov eax, [rbp+var_50]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nadd rax, rsi\nmov edx, [rcx+rax*4]\nlea rax, [rbp+s]\nlea rcx, format; \"%d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov edx, eax\nmov eax, [rbp+var_54]\nadd eax, edx\nadd eax, 2\nmov [rbp+var_54], eax\nadd [rbp+var_4C], 1\nloc_15CC:\nmov rcx, [rbp+var_38]\nmov eax, [rbp+var_50]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 2\nadd rax, rcx\nadd rax, 0Ch\nmov eax, [rax]\ncmp [rbp+var_4C], eax\njl short loc_1574\nmov rcx, [rbp+var_38]\nmov eax, [rbp+var_50]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 2\nadd rax, rcx\nadd rax, 10h\nmov edx, [rax]\nlea rax, [rbp+s]\nlea rcx, format; \"%d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov edx, eax\nmov eax, [rbp+var_54]\nadd eax, edx\nadd eax, 2\nmov [rbp+var_54], eax\nadd [rbp+var_50], 1\nloc_164B:\nmov eax, [rbp+var_50]\ncmp eax, [rbp+var_6C]\njl loc_1567\ncmp [rbp+var_6C], 0\njle short loc_1661\nsub [rbp+var_54], 2\nloc_1661:\nadd [rbp+var_54], 1\nmov eax, [rbp+var_54]\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+dest], rax\ncmp [rbp+dest], 0\njnz short loc_16AA\nmov rax, cs:stderr\nmov rcx, rax; s\nmov edx, 19h; n\nmov esi, 1; size\nlea rax, aMemoryAllocati; \"Memory allocation failed\\n\"\nmov rdi, rax; ptr\ncall _fwrite\nmov edi, 1; status\ncall _exit\nloc_16AA:\nmov rax, [rbp+dest]\nmov word ptr [rax], 5Bh ; '['\nmov [rbp+var_48], 0\njmp loc_1861\nloc_16BF:\nmov rax, [rbp+dest]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+dest]\nadd rax, rdx\nmov word ptr [rax], 28h ; '('\nmov [rbp+var_44], 0\njmp loc_1780\nloc_16E6:\nmov rcx, [rbp+var_38]\nmov eax, [rbp+var_44]\nmovsxd rsi, eax\nmov eax, [rbp+var_48]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nadd rax, rsi\nmov edx, [rcx+rax*4]\nlea rax, [rbp+s]\nlea rcx, format; \"%d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rdx, [rbp+s]\nmov rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\nmov rcx, [rbp+var_38]\nmov eax, [rbp+var_48]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 2\nadd rax, rcx\nadd rax, 0Ch\nmov eax, [rax]\nsub eax, 1\ncmp [rbp+var_44], eax\njge short loc_177C\nmov rax, [rbp+dest]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+dest]\nadd rax, rdx\nmov word ptr [rax], 202Ch\nmov byte ptr [rax+2], 0\nloc_177C:\nadd [rbp+var_44], 1\nloc_1780:\nmov rcx, [rbp+var_38]\nmov eax, [rbp+var_48]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 2\nadd rax, rcx\nadd rax, 0Ch\nmov eax, [rax]\ncmp [rbp+var_44], eax\njl loc_16E6\nmov rax, [rbp+dest]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+dest]\nadd rax, rdx\nmov word ptr [rax], 202Ch\nmov byte ptr [rax+2], 0\nmov rcx, [rbp+var_38]\nmov eax, [rbp+var_48]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 2\nadd rax, rcx\nadd rax, 10h\nmov edx, [rax]\nlea rax, [rbp+s]\nlea rcx, format; \"%d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rdx, [rbp+s]\nmov rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\nmov rax, [rbp+dest]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+dest]\nadd rax, rdx\nmov word ptr [rax], 29h ; ')'\nmov eax, [rbp+var_6C]\nsub eax, 1\ncmp [rbp+var_48], eax\njge short loc_185D\nmov rax, [rbp+dest]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+dest]\nadd rax, rdx\nmov word ptr [rax], 202Ch\nmov byte ptr [rax+2], 0\nloc_185D:\nadd [rbp+var_48], 1\nloc_1861:\nmov eax, [rbp+var_48]\ncmp eax, [rbp+var_6C]\njl loc_16BF\nmov rax, [rbp+dest]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+dest]\nadd rax, rdx\nmov word ptr [rax], 5Dh ; ']'\nmov rax, [rbp+dest]\nmov rsp, rbx\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njz short loc_18A3\ncall ___stack_chk_fail\nloc_18A3:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1269(__int64 a1, int a2)\n{\n unsigned __int64 v2; // rax\n void *v3; // rsp\n _QWORD *v4; // rsi\n _QWORD *v5; // rcx\n __int64 v6; // rdx\n int v7; // eax\n int v8; // eax\n size_t v9; // rax\n size_t v10; // rax\n size_t v11; // rax\n size_t v12; // rax\n size_t v13; // rax\n size_t v14; // rax\n _BYTE v16[4]; // [rsp+8h] [rbp-80h] BYREF\n int v17; // [rsp+Ch] [rbp-7Ch]\n __int64 v18; // [rsp+10h] [rbp-78h]\n int v19; // [rsp+1Ch] [rbp-6Ch]\n int i; // [rsp+20h] [rbp-68h]\n int v21; // [rsp+24h] [rbp-64h]\n int j; // [rsp+28h] [rbp-60h]\n int v23; // [rsp+2Ch] [rbp-5Ch]\n int k; // [rsp+30h] [rbp-58h]\n int v25; // [rsp+34h] [rbp-54h]\n int m; // [rsp+38h] [rbp-50h]\n int n; // [rsp+3Ch] [rbp-4Ch]\n int ii; // [rsp+40h] [rbp-48h]\n int jj; // [rsp+44h] [rbp-44h]\n __int64 v30; // [rsp+48h] [rbp-40h]\n _BYTE *v31; // [rsp+50h] [rbp-38h]\n char *dest; // [rsp+58h] [rbp-30h]\n char s[12]; // [rsp+64h] [rbp-24h] BYREF\n unsigned __int64 v34; // [rsp+70h] [rbp-18h]\n\n v18 = a1;\n v17 = a2;\n v34 = __readfsqword(0x28u);\n v30 = a2 - 1LL;\n v2 = 16 * ((20LL * a2 + 15) / 0x10uLL);\n while ( v16 != &v16[-(v2 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = alloca(v2 & 0xFFF);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)&v16[(v2 & 0xFFF) - 8] = *(_QWORD *)&v16[(v2 & 0xFFF) - 8];\n v31 = v16;\n v19 = 0;\n for ( i = 0; i < v17; ++i )\n {\n v21 = 0;\n for ( j = 0; j < v19; ++j )\n {\n if ( *(_DWORD *)&v31[20 * j + 12] == *(_DWORD *)(16LL * i + v18 + 12) )\n {\n v23 = 1;\n for ( k = 0; k < *(_DWORD *)(16LL * i + v18 + 12); ++k )\n {\n if ( *(_DWORD *)&v31[20 * j + 4 * k] != *(_DWORD *)(v18 + 16LL * i + 4LL * k) )\n {\n v23 = 0;\n break;\n }\n }\n if ( v23 )\n {\n ++*(_DWORD *)&v31[20 * j + 16];\n v21 = 1;\n break;\n }\n }\n }\n if ( !v21 )\n {\n v4 = (_QWORD *)(16LL * i + v18);\n v5 = &v31[20 * v19];\n v6 = v4[1];\n *v5 = *v4;\n v5[1] = v6;\n *(_DWORD *)&v31[20 * v19++ + 16] = 1;\n }\n }\n v25 = 2;\n for ( m = 0; m < v19; ++m )\n {\n v25 += 2;\n for ( n = 0; n < *(_DWORD *)&v31[20 * m + 12]; ++n )\n {\n sprintf(s, \"%d\", *(_DWORD *)&v31[20 * m + 4 * n]);\n v7 = strlen(s);\n v25 += v7 + 2;\n }\n sprintf(s, \"%d\", *(_DWORD *)&v31[20 * m + 16]);\n v8 = strlen(s);\n v25 += v8 + 2;\n }\n if ( v19 > 0 )\n v25 -= 2;\n dest = (char *)malloc(++v25);\n if ( !dest )\n {\n fwrite(\"Memory allocation failed\\n\", 1uLL, 0x19uLL, stderr);\n exit(1);\n }\n *(_WORD *)dest = 91;\n for ( ii = 0; ii < v19; ++ii )\n {\n v9 = strlen(dest);\n *(_WORD *)&dest[v9] = 40;\n for ( jj = 0; jj < *(_DWORD *)&v31[20 * ii + 12]; ++jj )\n {\n sprintf(s, \"%d\", *(_DWORD *)&v31[20 * ii + 4 * jj]);\n strcat(dest, s);\n if ( jj < *(_DWORD *)&v31[20 * ii + 12] - 1 )\n {\n v10 = strlen(dest);\n strcpy(&dest[v10], \", \");\n }\n }\n v11 = strlen(dest);\n strcpy(&dest[v11], \", \");\n sprintf(s, \"%d\", *(_DWORD *)&v31[20 * ii + 16]);\n strcat(dest, s);\n v12 = strlen(dest);\n *(_WORD *)&dest[v12] = 41;\n if ( ii < v19 - 1 )\n {\n v13 = strlen(dest);\n strcpy(&dest[v13], \", \");\n }\n }\n v14 = strlen(dest);\n *(_WORD *)&dest[v14] = 93;\n return dest;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1269(long long a1, int a2) {\n unsigned long long v2;\n void *v3;\n uint64_t *v4;\n uint64_t *v5;\n long long v6;\n int v7;\n int v8;\n unsigned int v9;\n unsigned int v10;\n unsigned int v11;\n unsigned int v12;\n unsigned int v13;\n unsigned int v14;\n uint8_t v16[4];\n int v17;\n long long v18;\n int v19;\n int i;\n int v21;\n int j;\n int v23;\n int k;\n int v25;\n int m;\n int n;\n int ii;\n int jj;\n long long v30;\n uint8_t *v31;\n char *dest;\n char s[12];\n unsigned long long v34;\n v18 = a1;\n v17 = a2;\n v34 = __readfsqword(40u);\n v30 = a2 - 1LL;\n v2 = 16 * ((20LL * a2 + 15) / 16uLL);\n while (v16 != &v16[-(v2 & 18446744073709547520LL)])\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)&v16[(v2 & 4095) - 8] = *(uint64_t *)&v16[(v2 & 4095) - 8];\n v31 = v16;\n v19 = 0;\n for (i = 0; i < v17; ++i) {\n v21 = 0;\n for (j = 0; j < v19; ++j) {\n if (*(uint32_t *)&v31[20 * j + 12] ==\n *(uint32_t *)(16LL * i + v18 + 12)) {\n v23 = 1;\n for (k = 0; k < *(uint32_t *)(16LL * i + v18 + 12); ++k) {\n if (*(uint32_t *)&v31[20 * j + 4 * k] !=\n *(uint32_t *)(v18 + 16LL * i + 4LL * k)) {\n v23 = 0;\n break;\n }\n }\n if (v23) {\n ++*(uint32_t *)&v31[20 * j + 16];\n v21 = 1;\n break;\n }\n }\n }\n if (!v21) {\n v4 = (uint64_t *)(16LL * i + v18);\n v5 = &v31[20 * v19];\n v6 = v4[1];\n *v5 = *v4;\n v5[1] = v6;\n *(uint32_t *)&v31[20 * v19++ + 16] = 1;\n }\n }\n v25 = 2;\n for (m = 0; m < v19; ++m) {\n v25 += 2;\n for (n = 0; n < *(uint32_t *)&v31[20 * m + 12]; ++n) {\n sprintf(s, \"%d\", *(uint32_t *)&v31[20 * m + 4 * n]);\n v7 = strlen(s);\n v25 += v7 + 2;\n }\n sprintf(s, \"%d\", *(uint32_t *)&v31[20 * m + 16]);\n v8 = strlen(s);\n v25 += v8 + 2;\n }\n if (v19 > 0) v25 -= 2;\n dest = (char *)malloc(++v25);\n if (!dest) {\n fwrite(\"Memory allocation failed\\n\", 1uLL, 25uLL, stderr);\n exit(1);\n }\n *(unsigned short *)dest = 91;\n for (ii = 0; ii < v19; ++ii) {\n v9 = strlen(dest);\n *(unsigned short *)&dest[v9] = 40;\n for (jj = 0; jj < *(uint32_t *)&v31[20 * ii + 12]; ++jj) {\n sprintf(s, \"%d\", *(uint32_t *)&v31[20 * ii + 4 * jj]);\n strcat(dest, s);\n if (jj < *(uint32_t *)&v31[20 * ii + 12] - 1) {\n v10 = strlen(dest);\n strcpy(&dest[v10], \", \");\n }\n }\n v11 = strlen(dest);\n strcpy(&dest[v11], \", \");\n sprintf(s, \"%d\", *(uint32_t *)&v31[20 * ii + 16]);\n strcat(dest, s);\n v12 = strlen(dest);\n *(unsigned short *)&dest[v12] = 41;\n if (ii < v19 - 1) {\n v13 = strlen(dest);\n strcpy(&dest[v13], \", \");\n }\n }\n v14 = strlen(dest);\n *(unsigned short *)&dest[v14] = 93;\n return dest;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2) {\n unsigned long long v2;\n void *v3;\n uint64_t *v4;\n uint64_t *v5;\n long long v6;\n int v7;\n int v8;\n unsigned int v9;\n unsigned int v10;\n unsigned int v11;\n unsigned int v12;\n unsigned int v13;\n unsigned int v14;\n uint8_t v16[4];\n int v17;\n long long v18;\n int v19;\n int i;\n int v21;\n int j;\n int v23;\n int k;\n int v25;\n int m;\n int n;\n int ii;\n int jj;\n long long v30;\n uint8_t *v31;\n char *dest;\n char s[12];\n unsigned long long v34;\n v18 = a1;\n v17 = a2;\n v34 = __readfsqword(40u);\n v30 = a2 - 1LL;\n v2 = 16 * ((20LL * a2 + 15) / 16uLL);\n while (v16 != &v16[-(v2 & 18446744073709547520LL)])\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)&v16[(v2 & 4095) - 8] = *(uint64_t *)&v16[(v2 & 4095) - 8];\n v31 = v16;\n v19 = 0;\n for (i = 0; i < v17; ++i) {\n v21 = 0;\n for (j = 0; j < v19; ++j) {\n if (*(uint32_t *)&v31[20 * j + 12] ==\n *(uint32_t *)(16LL * i + v18 + 12)) {\n v23 = 1;\n for (k = 0; k < *(uint32_t *)(16LL * i + v18 + 12); ++k) {\n if (*(uint32_t *)&v31[20 * j + 4 * k] !=\n *(uint32_t *)(v18 + 16LL * i + 4LL * k)) {\n v23 = 0;\n break;\n }\n }\n if (v23) {\n ++*(uint32_t *)&v31[20 * j + 16];\n v21 = 1;\n break;\n }\n }\n }\n if (!v21) {\n v4 = (uint64_t *)(16LL * i + v18);\n v5 = &v31[20 * v19];\n v6 = v4[1];\n *v5 = *v4;\n v5[1] = v6;\n *(uint32_t *)&v31[20 * v19++ + 16] = 1;\n }\n }\n v25 = 2;\n for (m = 0; m < v19; ++m) {\n v25 += 2;\n for (n = 0; n < *(uint32_t *)&v31[20 * m + 12]; ++n) {\n sprintf(s, \"%d\", *(uint32_t *)&v31[20 * m + 4 * n]);\n v7 = strlen(s);\n v25 += v7 + 2;\n }\n sprintf(s, \"%d\", *(uint32_t *)&v31[20 * m + 16]);\n v8 = strlen(s);\n v25 += v8 + 2;\n }\n if (v19 > 0) v25 -= 2;\n dest = (char *)malloc(++v25);\n if (!dest) {\n fwrite(\"Memory allocation failed\\n\", 1uLL, 25uLL, _bss_start);\n exit(1);\n }\n *(unsigned short *)dest = 91;\n for (ii = 0; ii < v19; ++ii) {\n v9 = strlen(dest);\n *(unsigned short *)&dest[v9] = 40;\n for (jj = 0; jj < *(uint32_t *)&v31[20 * ii + 12]; ++jj) {\n sprintf(s, \"%d\", *(uint32_t *)&v31[20 * ii + 4 * jj]);\n strcat(dest, s);\n if (jj < *(uint32_t *)&v31[20 * ii + 12] - 1) {\n v10 = strlen(dest);\n strcpy(&dest[v10], \", \");\n }\n }\n v11 = strlen(dest);\n strcpy(&dest[v11], \", \");\n sprintf(s, \"%d\", *(uint32_t *)&v31[20 * ii + 16]);\n strcat(dest, s);\n v12 = strlen(dest);\n *(unsigned short *)&dest[v12] = 41;\n if (ii < v19 - 1) {\n v13 = strlen(dest);\n strcpy(&dest[v13], \", \");\n }\n }\n v14 = strlen(dest);\n *(unsigned short *)&dest[v14] = 93;\n return dest;\n}" + }, + { + "index": 114, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int elements[3];\n\n int length;\n\n} Tuple;\n\n\n\ntypedef struct {\n\n Tuple tuple;\n\n int count;\n\n} TupleCount;\n\n\n\n", + "func": "char* func0(Tuple input[], int input_size) {\n TupleCount counts[input_size];\n int unique = 0;\n for (int i = 0; i < input_size; i++) {\n int found = 0;\n for (int j = 0; j < unique; j++) {\n if (counts[j].tuple.length == input[i].length) {\n int match = 1;\n for (int k = 0; k < input[i].length; k++) {\n if (counts[j].tuple.elements[k] != input[i].elements[k]) {\n match = 0;\n break;\n }\n }\n if (match) {\n counts[j].count++;\n found = 1;\n break;\n }\n }\n }\n if (!found) {\n counts[unique].tuple = input[i];\n counts[unique].count = 1;\n unique++;\n }\n }\n int size = 2;\n for (int i = 0; i < unique; i++) {\n size += 2;\n for (int j = 0; j < counts[i].tuple.length; j++) {\n char num[12];\n sprintf(num, \"%d\", counts[i].tuple.elements[j]);\n size += strlen(num) + 2;\n }\n char cnt[12];\n sprintf(cnt, \"%d\", counts[i].count);\n size += strlen(cnt) + 2;\n }\n if (unique > 0) size -= 2;\n size += 1;\n char* result = malloc(size);\n if (result == NULL) {\n fprintf(stderr, \"Memory allocation failed\\n\");\n exit(1);\n }\n strcpy(result, \"[\");\n for (int i = 0; i < unique; i++) {\n strcat(result, \"(\");\n for (int j = 0; j < counts[i].tuple.length; j++) {\n char num[12];\n sprintf(num, \"%d\", counts[i].tuple.elements[j]);\n strcat(result, num);\n if (j < counts[i].tuple.length - 1) strcat(result, \", \");\n }\n strcat(result, \", \");\n char cnt[12];\n sprintf(cnt, \"%d\", counts[i].count);\n strcat(result, cnt);\n strcat(result, \")\");\n if (i < unique - 1) strcat(result, \", \");\n }\n strcat(result, \"]\");\n return result;\n}", + "test": "int main() {\n\n // First test case\n\n Tuple test1[] = {\n\n { .elements = {6, 5, 8}, .length = 3 },\n\n { .elements = {2, 7, 0}, .length = 2 },\n\n { .elements = {6, 5, 8}, .length = 3 },\n\n { .elements = {6, 5, 8}, .length = 3 },\n\n { .elements = {9, 0, 0}, .length = 1 },\n\n { .elements = {2, 7, 0}, .length = 2 }\n\n };\n\n char* res1 = func0(test1, 6);\n\n assert(strcmp(res1, \"[(6, 5, 8, 3), (2, 7, 2), (9, 1)]\") == 0);\n\n free(res1);\n\n\n\n // Second test case\n\n Tuple test2[] = {\n\n { .elements = {4, 2, 4}, .length = 3 },\n\n { .elements = {7, 1, 0}, .length = 2 },\n\n { .elements = {4, 8, 0}, .length = 2 },\n\n { .elements = {4, 2, 4}, .length = 3 },\n\n { .elements = {9, 2, 0}, .length = 2 },\n\n { .elements = {7, 1, 0}, .length = 2 }\n\n };\n\n char* res2 = func0(test2, 6);\n\n assert(strcmp(res2, \"[(4, 2, 4, 2), (7, 1, 2), (4, 8, 1), (9, 2, 1)]\") == 0);\n\n free(res2);\n\n\n\n // Third test case\n\n Tuple test3[] = {\n\n { .elements = {11, 13, 10}, .length = 3 },\n\n { .elements = {17, 21, 0}, .length = 2 },\n\n { .elements = {4, 2, 3}, .length = 3 },\n\n { .elements = {17, 21, 0}, .length = 2 },\n\n { .elements = {9, 2, 0}, .length = 2 },\n\n { .elements = {4, 2, 3}, .length = 3 }\n\n };\n\n char* res3 = func0(test3, 6);\n\n assert(strcmp(res3, \"[(11, 13, 10, 1), (17, 21, 2), (4, 2, 3, 2), (9, 2, 1)]\") == 0);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0x58,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nmovslq %esi,%rax\nlea (%rax,%rax,4),%rax\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffffff0,%rdx\nand $0xfffffffffffff000,%rax\nmov %rsp,%rbx\nsub %rax,%rbx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 1289 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 1272 \nmov %rdx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 129f \norq $0x0,-0x8(%rsp,%rax,1)\nmov %rsp,%r10\nmov %r10,%r11\ntest %esi,%esi\njle 15c4 \nmov %rdi,%r9\nlea -0x1(%rsi),%eax\nshl $0x4,%rax\nlea 0x10(%rdi,%rax,1),%r12\nmov $0x0,%ebx\njmp 133d \nadd $0x1,%ecx\nadd $0x14,%rdx\ncmp %ebx,%ecx\nje 130f \nmov %rdx,%rdi\ncmp %esi,0xc(%rdx)\njne 12c3 \ntest %esi,%esi\njle 12f1 \nmov $0x0,%eax\nmov (%r8,%rax,4),%r15d\ncmp %r15d,(%rdi,%rax,4)\njne 12c3 \nadd $0x1,%rax\ncmp %eax,%esi\njg 12df \nmovslq %ecx,%rcx\nlea 0x0(,%rcx,4),%rax\nlea (%rax,%rcx,1),%rdx\nmov 0x10(%r11,%rdx,4),%eax\nadd $0x1,%eax\nmov %eax,0x10(%r11,%rdx,4)\njmp 1334 \nmovslq %ebx,%rdx\nlea 0x0(,%rdx,4),%rax\nlea (%rax,%rdx,1),%rcx\nmovdqu (%r9),%xmm0\nmovups %xmm0,(%r11,%rcx,4)\nmovl $0x1,0x10(%r11,%rcx,4)\nadd $0x1,%ebx\nadd $0x10,%r9\ncmp %r12,%r9\nje 1355 \ntest %ebx,%ebx\njle 130f \nmov %r9,%r8\nmov 0xc(%r9),%esi\nmov %r11,%rdx\nmov $0x0,%ecx\njmpq 12ce \ntest %ebx,%ebx\njle 15c4 \nmov %r10,-0x68(%rbp)\nlea -0x1(%rbx),%eax\nlea (%rax,%rax,4),%rax\nlea 0x14(%r10,%rax,4),%rax\nmov %rax,-0x70(%rbp)\nmov $0x2,%r13d\nlea -0x44(%rbp),%r14\nmov %ebx,-0x74(%rbp)\nmov %r13d,%r12d\nmov %r10,%r13\njmp 13da \nmov -0x58(%rbp),%rax\nmov 0x10(%rax),%r8d\nlea 0xc6f(%rip),%rcx\nmov $0xc,%edx\nmov $0x1,%esi\nmov %r14,%rdi\nmov $0x0,%eax\ncallq 1130 <__sprintf_chk@plt>\nmov $0x0,%eax\nmov $0xffffffffffffffff,%rcx\nmov %r14,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%r12,%rax,1),%eax\nlea 0x2(%rax),%r12d\nadd $0x14,%r13\ncmp -0x70(%rbp),%r13\nje 15fd \nadd $0x2,%r12d\nmov %r13,-0x58(%rbp)\nmov 0xc(%r13),%r15d\ntest %r15d,%r15d\njle 1386 \nmov $0x0,%ebx\nmov %r13,-0x60(%rbp)\nmov 0x0(%r13,%rbx,4),%r8d\nlea 0xc04(%rip),%rcx\nmov $0xc,%edx\nmov $0x1,%esi\nmov %r14,%rdi\nmov $0x0,%eax\ncallq 1130 <__sprintf_chk@plt>\nmov $0x0,%eax\nmov $0xffffffffffffffff,%rcx\nmov %r14,%rdi\nrepnz scas %es:(%rdi),%al\nsub %ecx,%r12d\nadd $0x1,%rbx\ncmp %ebx,%r15d\njg 13f4 \nmov -0x60(%rbp),%r13\njmpq 1386 \nadd $0x1,%rbx\ncmp %ebx,%r14d\njle 149f \nmov -0x58(%rbp),%rax\nmov (%rax,%rbx,4),%r8d\nlea 0xbaf(%rip),%rcx\nmov $0xc,%edx\nmov $0x1,%esi\nmov %r12,%rdi\nmov %r15d,%eax\ncallq 1130 <__sprintf_chk@plt>\nmov %r12,%rsi\nmov %r13,%rdi\ncallq 1100 \nlea -0x1(%r14),%eax\ncmp %ebx,%eax\njle 143d \nmov $0xffffffffffffffff,%rcx\nmov %r13,%rdi\nmov %r15d,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nlea -0x1(%r13,%rcx,1),%rax\nmovw $0x202c,(%rax)\nmovb $0x0,0x2(%rax)\njmp 143d \nmov $0xffffffffffffffff,%rcx\nmov %r13,%rdi\nmov %r15d,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nlea -0x1(%r13,%rcx,1),%rax\nmovw $0x202c,(%rax)\nmovb $0x0,0x2(%rax)\nmov -0x58(%rbp),%rax\nmov 0x10(%rax),%r8d\nlea 0xb36(%rip),%rcx\nmov $0xc,%edx\nmov $0x1,%esi\nmov %r12,%rdi\nmov %r15d,%eax\ncallq 1130 <__sprintf_chk@plt>\nmov %r12,%rsi\nmov %r13,%rdi\ncallq 1100 \nmov $0xffffffffffffffff,%rcx\nmov %r13,%rdi\nmov %r15d,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nmovw $0x29,-0x1(%r13,%rcx,1)\nmov -0x60(%rbp),%ebx\ncmp %ebx,-0x70(%rbp)\njg 155a \naddl $0x1,-0x60(%rbp)\nmov -0x60(%rbp),%eax\naddq $0x14,-0x68(%rbp)\ncmp %eax,-0x74(%rbp)\nje 1580 \nmov $0xffffffffffffffff,%rcx\nmov %r13,%rdi\nmov %r15d,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nmovw $0x28,-0x1(%r13,%rcx,1)\nmov -0x68(%rbp),%rax\nmov %rax,-0x58(%rbp)\nmov 0xc(%rax),%r14d\ntest %r14d,%r14d\njle 149f \nmov $0x0,%ebx\njmpq 1446 \nmov $0xffffffffffffffff,%rcx\nmov %r13,%rdi\nrepnz scas %es:(%rdi),%al\nnot %rcx\nlea -0x1(%r13,%rcx,1),%rax\nmovw $0x202c,(%rax)\nmovb $0x0,0x2(%rax)\njmp 1510 \nmovw $0x5b,0x0(%r13)\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nmov %r13,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nmovw $0x5d,-0x1(%r13,%rax,1)\nmov -0x38(%rbp),%rax\nxor %fs:0x28,%rax\njne 1639 \nmov %r13,%rax\nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\nmov $0x3,%edi\ncallq 10f0 \nmov %rax,%r13\ntest %rax,%rax\njne 1579 \nmov 0x2a43(%rip),%rcx\nmov $0x19,%edx\nmov $0x1,%esi\nlea 0xa19(%rip),%rdi\ncallq 1120 \nmov $0x1,%edi\ncallq 1110 \nmov -0x74(%rbp),%ebx\nadd $0x1,%eax\nmovslq %eax,%rdi\ncallq 10f0 \nmov %rax,%r13\ntest %rax,%rax\nje 15d6 \nmovw $0x5b,0x0(%r13)\nmovl $0x0,-0x60(%rbp)\nmov $0x0,%r15d\nlea -0x44(%rbp),%r12\nlea -0x1(%rbx),%eax\nmov %eax,-0x70(%rbp)\nmov %ebx,-0x74(%rbp)\njmpq 1521 \ncallq 10d0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 58h\nmov r12, rdi\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nmovsxd rax, esi\nlea rdx, [rax+rax*4]\nlea rdx, ds:0Fh[rdx*4]\nmov rdi, rdx\nand rdi, 0FFFFFFFFFFFFFFF0h\nand rdx, 0FFFFFFFFFFFFF000h\nmov rcx, rsp\nsub rcx, rdx\nloc_12D3:\ncmp rsp, rcx\njz short loc_12EA\nsub rsp, 1000h\nor [rsp+1080h+var_88], 0\njmp short loc_12D3\nloc_12EA:\nmov rdx, rdi\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njz short loc_1301\nor [rsp+rdx+80h+var_88], 0\nloc_1301:\nmov r11, rsp\ntest esi, esi\njle loc_1633\nmov r10, r12\nshl rax, 4\nadd r12, rax\nmov ebx, 0\njmp short loc_139A\nloc_131D:\nadd ecx, 1\nadd rdx, 14h\ncmp ecx, ebx\njz short loc_136C\nloc_1328:\nmov rsi, rdx\ncmp [rdx+0Ch], r9d\njnz short loc_131D\ntest r9d, r9d\njle short loc_134E\nmov eax, 0\nloc_133B:\nmov r15d, [rdi+rax*4]\ncmp [rsi+rax*4], r15d\njnz short loc_131D\nadd rax, 1\ncmp rax, r8\njnz short loc_133B\nloc_134E:\nmovsxd rcx, ecx\nlea rax, ds:0[rcx*4]\nlea rdx, [rax+rcx]\nmov eax, [r11+rdx*4+10h]\nadd eax, 1\nmov [r11+rdx*4+10h], eax\njmp short loc_1391\nloc_136C:\nmovsxd rdx, ebx\nlea rax, ds:0[rdx*4]\nlea rcx, [rax+rdx]\nmovdqu xmm0, xmmword ptr [r10]\nmovups xmmword ptr [r11+rcx*4], xmm0\nmov dword ptr [r11+rcx*4+10h], 1\nadd ebx, 1\nloc_1391:\nadd r10, 10h\ncmp r10, r12\njz short loc_13B5\nloc_139A:\ntest ebx, ebx\njle short loc_136C\nmov rdi, r10\nmov r9d, [r10+0Ch]\nmov rdx, r11\nmov ecx, 0\nmovsxd r8, r9d\njmp loc_1328\nloc_13B5:\ntest ebx, ebx\njle loc_1633\nmov [rbp+var_70], r11\nmovsxd rax, ebx\nlea rax, [rax+rax*4]\nmov [rbp+var_68], rax\nmov [rbp+var_58], 0\nmov eax, 2\nlea r14, [rbp+s]\nmov [rbp+var_74], ebx\nmov r15, r11\njmp short loc_1431\nloc_13E5:\nmov rax, [rbp+var_60]\nmov r8d, [rax+10h]\nlea rcx, unk_2004\nmov edx, 0Ch\nmov esi, 2\nmov rdi, r14\nmov eax, 0\ncall ___sprintf_chk\nmov rdi, r14; s\ncall _strlen\nadd r12d, eax\nlea eax, [r12+2]\nadd r15, 14h\nadd [rbp+var_58], 5\nmov rcx, [rbp+var_58]\nmov rbx, [rbp+var_68]\ncmp rcx, rbx\njz short loc_1491\nloc_1431:\nlea r12d, [rax+2]\nmov [rbp+var_60], r15\nmov eax, [r15+0Ch]\ntest eax, eax\njle short loc_13E5\ncdqe\nmov rbx, [rbp+var_58]\nadd rax, rbx\nmov rdi, [rbp+var_70]\nlea r13, [rdi+rax*4]\nmov rbx, r15\nloc_1455:\nmov r8d, [rbx]\nlea rcx, unk_2004\nmov edx, 0Ch\nmov esi, 2\nmov rdi, r14\nmov eax, 0\ncall ___sprintf_chk\nmov rdi, r14; s\ncall _strlen\nlea r12d, [r12+rax+2]\nadd rbx, 4\ncmp rbx, r13\njnz short loc_1455\njmp loc_13E5\nloc_1491:\nmov r13d, r12d\nmov ebx, [rbp+var_74]\nadd r13d, 1\nmovsxd r14, r13d\nmov rdi, r14; size\ncall _malloc\nmov r15, rax\ntest rax, rax\njz loc_1645\nmov rcx, r14\nmov edx, 2\nlea rsi, asc_2021; \"[\"\nmov rdi, rax\ncall ___memcpy_chk\nmov dword ptr [rbp+var_58], 0\nlea r13, [rbp+s]\nmov [rbp+var_74], ebx\njmp loc_15A5\nloc_14DC:\nadd rbx, 1\nmov rax, [rbp+var_60]\ncmp rbx, rax\njz short loc_1532\nloc_14E9:\nmov r8d, [r12+rbx*4]\nlea rcx, unk_2004\nmov edx, 0Ch\nmov esi, 2\nmov rdi, r13\nmov eax, 0\ncall ___sprintf_chk\nmov rdx, r14\nmov rsi, r13\nmov rdi, r15\ncall ___strcat_chk\ncmp dword ptr [rbp+var_68], ebx\njle short loc_14DC\nmov rdx, r14\nlea rsi, asc_2025; \", \"\nmov rdi, r15\ncall ___strcat_chk\njmp short loc_14DC\nloc_1532:\nmov rdx, r14\nlea rsi, asc_2025; \", \"\nmov rdi, r15\ncall ___strcat_chk\nmov r8d, [r12+10h]\nlea rcx, unk_2004\nmov edx, 0Ch\nmov esi, 2\nmov rdi, r13\nmov eax, 0\ncall ___sprintf_chk\nmov rdx, r14\nmov rsi, r13\nmov rdi, r15\ncall ___strcat_chk\nmov rdx, r14\nlea rsi, asc_2028; \")]\"\nmov rdi, r15\ncall ___strcat_chk\nmov eax, [rbp+var_74]\nsub eax, 1\nmov ebx, dword ptr [rbp+var_58]\ncmp eax, ebx\njg short loc_15E0\nloc_1594:\nadd dword ptr [rbp+var_58], 1\nmov eax, dword ptr [rbp+var_58]\nadd [rbp+var_70], 14h\ncmp [rbp+var_74], eax\njz short loc_1600\nloc_15A5:\nmov rdx, r14\nlea rsi, asc_2023; \"(\"\nmov rdi, r15\ncall ___strcat_chk\nmov rax, [rbp+var_70]\nmov r12, rax\nmov eax, [rax+0Ch]\ntest eax, eax\njle loc_1532\nmovsxd rbx, eax\nmov [rbp+var_60], rbx\nmov ebx, 0\nsub eax, 1\nmov dword ptr [rbp+var_68], eax\njmp loc_14E9\nloc_15E0:\nmov rdx, r14\nlea rsi, asc_2025; \", \"\nmov rdi, r15\ncall ___strcat_chk\njmp short loc_1594\nloc_15F4:\nmov word ptr [r15], 5Bh ; '['\nmov r14d, 3\nloc_1600:\nmov rdx, r14\nlea rsi, asc_2028+2; \"]\"\nmov rdi, r15\ncall ___strcat_chk\nmov rax, [rbp+var_38]\nsub rax, fs:28h\njnz short loc_166C\nmov rax, r15\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1633:\nmov edi, 3; size\ncall _malloc\nmov r15, rax\ntest rax, rax\njnz short loc_15F4\nloc_1645:\nmov rcx, cs:__bss_start; s\nmov edx, 19h; n\nmov esi, 1; size\nlea rdi, aMemoryAllocati; \"Memory allocation failed\\n\"\ncall _fwrite\nmov edi, 1; status\ncall _exit\nloc_166C:\ncall ___stack_chk_fail", + "ida_pseudo": "_WORD *__fastcall func0(const __m128i *a1, int a2)\n{\n signed __int64 v2; // rdx\n void *v3; // rsp\n const __m128i *v4; // r10\n int v5; // ebx\n int i; // ecx\n _DWORD *v7; // rdx\n __int64 v8; // rax\n __int64 v9; // rcx\n int v10; // r9d\n int v11; // eax\n _DWORD *v12; // r15\n int v13; // r12d\n int v14; // r12d\n int v15; // eax\n unsigned int *v16; // r13\n unsigned int *v17; // rbx\n int v18; // ebx\n size_t v19; // r14\n _WORD *v20; // rax\n _WORD *v21; // r15\n _DWORD *v22; // rbx\n _DWORD *v23; // r12\n int v24; // eax\n _WORD *v26; // rax\n _DWORD v28[3]; // [rsp+8h] [rbp-80h] BYREF\n int v29; // [rsp+14h] [rbp-74h]\n _DWORD *v30; // [rsp+18h] [rbp-70h]\n __int64 v31; // [rsp+20h] [rbp-68h]\n _DWORD *v32; // [rsp+28h] [rbp-60h]\n __int64 v33; // [rsp+30h] [rbp-58h]\n char s[12]; // [rsp+44h] [rbp-44h] BYREF\n unsigned __int64 v35; // [rsp+50h] [rbp-38h]\n\n v35 = __readfsqword(0x28u);\n while ( v28 != (_DWORD *)((char *)v28 - ((20LL * a2 + 15) & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v2 = (20 * (_WORD)a2 + 15) & 0xFF0;\n v3 = alloca(v2);\n if ( ((20 * (_WORD)a2 + 15) & 0xFF0) != 0 )\n *(_QWORD *)((char *)&v28[-2] + v2) = *(_QWORD *)((char *)&v28[-2] + v2);\n if ( a2 <= 0 )\n goto LABEL_37;\n v4 = a1;\n v5 = 0;\n do\n {\n if ( v5 > 0 )\n {\n v10 = v4->m128i_i32[3];\n v7 = v28;\n for ( i = 0; i != v5; ++i )\n {\n if ( v7[3] == v10 )\n {\n if ( v10 <= 0 )\n {\nLABEL_13:\n ++*((_DWORD *)&v30 + 5 * i);\n goto LABEL_15;\n }\n v8 = 0LL;\n while ( v7[v8] == v4->m128i_i32[v8] )\n {\n if ( ++v8 == v10 )\n goto LABEL_13;\n }\n }\n v7 += 5;\n }\n }\n v9 = 5LL * v5;\n *(__m128i *)&v28[v9] = _mm_loadu_si128(v4);\n *((_DWORD *)&v30 + v9) = 1;\n ++v5;\nLABEL_15:\n ++v4;\n }\n while ( v4 != &a1[a2] );\n if ( v5 <= 0 )\n {\nLABEL_37:\n v26 = malloc(3uLL);\n v21 = v26;\n if ( v26 )\n {\n *v26 = 91;\n v19 = 3LL;\n goto LABEL_36;\n }\nLABEL_38:\n fwrite(\"Memory allocation failed\\n\", 1uLL, 0x19uLL, _bss_start);\n exit(1);\n }\n v30 = v28;\n v31 = 5LL * v5;\n v33 = 0LL;\n v11 = 2;\n v29 = v5;\n v12 = v28;\n do\n {\n v14 = v11 + 2;\n v32 = v12;\n v15 = v12[3];\n if ( v15 > 0 )\n {\n v16 = &v30[v33 + v15];\n v17 = v12;\n do\n {\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, *v17);\n v14 += strlen(s) + 2;\n ++v17;\n }\n while ( v17 != v16 );\n }\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, (unsigned int)v32[4]);\n v13 = strlen(s) + v14;\n v11 = v13 + 2;\n v12 += 5;\n v33 += 5LL;\n }\n while ( v33 != v31 );\n v18 = v29;\n v19 = v13 + 1;\n v20 = malloc(v19);\n v21 = v20;\n if ( !v20 )\n goto LABEL_38;\n __memcpy_chk(v20, \"[\", 2LL, v13 + 1);\n LODWORD(v33) = 0;\n v29 = v18;\n do\n {\n __strcat_chk(v21, \"(\", v19);\n v23 = v30;\n v24 = v30[3];\n if ( v24 > 0 )\n {\n v32 = (_DWORD *)v24;\n v22 = 0LL;\n LODWORD(v31) = v24 - 1;\n do\n {\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, (unsigned int)v23[(_QWORD)v22]);\n __strcat_chk(v21, s, v19);\n if ( (int)v31 > (int)v22 )\n __strcat_chk(v21, \", \", v19);\n v22 = (_DWORD *)((char *)v22 + 1);\n }\n while ( v22 != v32 );\n }\n __strcat_chk(v21, \", \", v19);\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, (unsigned int)v23[4]);\n __strcat_chk(v21, s, v19);\n __strcat_chk(v21, L\")]\", v19);\n if ( v29 - 1 > (int)v33 )\n __strcat_chk(v21, \", \", v19);\n LODWORD(v33) = v33 + 1;\n v30 += 5;\n }\n while ( v29 != (_DWORD)v33 );\nLABEL_36:\n __strcat_chk(v21, L\"]\", v19);\n return v21;\n}", + "ida_strip_asm": "sub_1289:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 58h\nmov r12, rdi\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nmovsxd rax, esi\nlea rdx, [rax+rax*4]\nlea rdx, ds:0Fh[rdx*4]\nmov rdi, rdx\nand rdi, 0FFFFFFFFFFFFFFF0h\nand rdx, 0FFFFFFFFFFFFF000h\nmov rcx, rsp\nsub rcx, rdx\nloc_12D3:\ncmp rsp, rcx\njz short loc_12EA\nsub rsp, 1000h\nor [rsp+1080h+var_88], 0\njmp short loc_12D3\nloc_12EA:\nmov rdx, rdi\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njz short loc_1301\nor [rsp+rdx+80h+var_88], 0\nloc_1301:\nmov r11, rsp\ntest esi, esi\njle loc_1633\nmov r10, r12\nshl rax, 4\nadd r12, rax\nmov ebx, 0\njmp short loc_139A\nloc_131D:\nadd ecx, 1\nadd rdx, 14h\ncmp ecx, ebx\njz short loc_136C\nloc_1328:\nmov rsi, rdx\ncmp [rdx+0Ch], r9d\njnz short loc_131D\ntest r9d, r9d\njle short loc_134E\nmov eax, 0\nloc_133B:\nmov r15d, [rdi+rax*4]\ncmp [rsi+rax*4], r15d\njnz short loc_131D\nadd rax, 1\ncmp rax, r8\njnz short loc_133B\nloc_134E:\nmovsxd rcx, ecx\nlea rax, ds:0[rcx*4]\nlea rdx, [rax+rcx]\nmov eax, [r11+rdx*4+10h]\nadd eax, 1\nmov [r11+rdx*4+10h], eax\njmp short loc_1391\nloc_136C:\nmovsxd rdx, ebx\nlea rax, ds:0[rdx*4]\nlea rcx, [rax+rdx]\nmovdqu xmm0, xmmword ptr [r10]\nmovups xmmword ptr [r11+rcx*4], xmm0\nmov dword ptr [r11+rcx*4+10h], 1\nadd ebx, 1\nloc_1391:\nadd r10, 10h\ncmp r10, r12\njz short loc_13B5\nloc_139A:\ntest ebx, ebx\njle short loc_136C\nmov rdi, r10\nmov r9d, [r10+0Ch]\nmov rdx, r11\nmov ecx, 0\nmovsxd r8, r9d\njmp loc_1328\nloc_13B5:\ntest ebx, ebx\njle loc_1633\nmov [rbp+var_70], r11\nmovsxd rax, ebx\nlea rax, [rax+rax*4]\nmov [rbp+var_68], rax\nmov [rbp+var_58], 0\nmov eax, 2\nlea r14, [rbp+s]\nmov [rbp+var_74], ebx\nmov r15, r11\njmp short loc_1431\nloc_13E5:\nmov rax, [rbp+var_60]\nmov r8d, [rax+10h]\nlea rcx, unk_2004\nmov edx, 0Ch\nmov esi, 2\nmov rdi, r14\nmov eax, 0\ncall ___sprintf_chk\nmov rdi, r14; s\ncall _strlen\nadd r12d, eax\nlea eax, [r12+2]\nadd r15, 14h\nadd [rbp+var_58], 5\nmov rcx, [rbp+var_58]\nmov rbx, [rbp+var_68]\ncmp rcx, rbx\njz short loc_1491\nloc_1431:\nlea r12d, [rax+2]\nmov [rbp+var_60], r15\nmov eax, [r15+0Ch]\ntest eax, eax\njle short loc_13E5\ncdqe\nmov rbx, [rbp+var_58]\nadd rax, rbx\nmov rdi, [rbp+var_70]\nlea r13, [rdi+rax*4]\nmov rbx, r15\nloc_1455:\nmov r8d, [rbx]\nlea rcx, unk_2004\nmov edx, 0Ch\nmov esi, 2\nmov rdi, r14\nmov eax, 0\ncall ___sprintf_chk\nmov rdi, r14; s\ncall _strlen\nlea r12d, [r12+rax+2]\nadd rbx, 4\ncmp rbx, r13\njnz short loc_1455\njmp loc_13E5\nloc_1491:\nmov r13d, r12d\nmov ebx, [rbp+var_74]\nadd r13d, 1\nmovsxd r14, r13d\nmov rdi, r14; size\ncall _malloc\nmov r15, rax\ntest rax, rax\njz loc_1645\nmov rcx, r14\nmov edx, 2\nlea rsi, asc_2021; \"[\"\nmov rdi, rax\ncall ___memcpy_chk\nmov dword ptr [rbp+var_58], 0\nlea r13, [rbp+s]\nmov [rbp+var_74], ebx\njmp loc_15A5\nloc_14DC:\nadd rbx, 1\nmov rax, [rbp+var_60]\ncmp rbx, rax\njz short loc_1532\nloc_14E9:\nmov r8d, [r12+rbx*4]\nlea rcx, unk_2004\nmov edx, 0Ch\nmov esi, 2\nmov rdi, r13\nmov eax, 0\ncall ___sprintf_chk\nmov rdx, r14\nmov rsi, r13\nmov rdi, r15\ncall ___strcat_chk\ncmp dword ptr [rbp+var_68], ebx\njle short loc_14DC\nmov rdx, r14\nlea rsi, asc_2025; \", \"\nmov rdi, r15\ncall ___strcat_chk\njmp short loc_14DC\nloc_1532:\nmov rdx, r14\nlea rsi, asc_2025; \", \"\nmov rdi, r15\ncall ___strcat_chk\nmov r8d, [r12+10h]\nlea rcx, unk_2004\nmov edx, 0Ch\nmov esi, 2\nmov rdi, r13\nmov eax, 0\ncall ___sprintf_chk\nmov rdx, r14\nmov rsi, r13\nmov rdi, r15\ncall ___strcat_chk\nmov rdx, r14\nlea rsi, asc_2028; \")]\"\nmov rdi, r15\ncall ___strcat_chk\nmov eax, [rbp+var_74]\nsub eax, 1\nmov ebx, dword ptr [rbp+var_58]\ncmp eax, ebx\njg short loc_15E0\nloc_1594:\nadd dword ptr [rbp+var_58], 1\nmov eax, dword ptr [rbp+var_58]\nadd [rbp+var_70], 14h\ncmp [rbp+var_74], eax\njz short loc_1600\nloc_15A5:\nmov rdx, r14\nlea rsi, asc_2023; \"(\"\nmov rdi, r15\ncall ___strcat_chk\nmov rax, [rbp+var_70]\nmov r12, rax\nmov eax, [rax+0Ch]\ntest eax, eax\njle loc_1532\nmovsxd rbx, eax\nmov [rbp+var_60], rbx\nmov ebx, 0\nsub eax, 1\nmov dword ptr [rbp+var_68], eax\njmp loc_14E9\nloc_15E0:\nmov rdx, r14\nlea rsi, asc_2025; \", \"\nmov rdi, r15\ncall ___strcat_chk\njmp short loc_1594\nloc_15F4:\nmov word ptr [r15], 5Bh ; '['\nmov r14d, 3\nloc_1600:\nmov rdx, r14\nlea rsi, asc_2028+2; \"]\"\nmov rdi, r15\ncall ___strcat_chk\nmov rax, [rbp+var_38]\nsub rax, fs:28h\njnz short loc_166C\nmov rax, r15\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1633:\nmov edi, 3; size\ncall _malloc\nmov r15, rax\ntest rax, rax\njnz short loc_15F4\nloc_1645:\nmov rcx, cs:stderr; s\nmov edx, 19h; n\nmov esi, 1; size\nlea rdi, aMemoryAllocati; \"Memory allocation failed\\n\"\ncall _fwrite\nmov edi, 1; status\ncall _exit\nloc_166C:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_WORD *__fastcall sub_1289(const __m128i *a1, int a2)\n{\n signed __int64 v2; // rdx\n void *v3; // rsp\n const __m128i *v4; // r10\n int v5; // ebx\n int i; // ecx\n _DWORD *v7; // rdx\n __int64 v8; // rax\n __int64 v9; // rcx\n int v10; // r9d\n int v11; // eax\n _DWORD *v12; // r15\n int v13; // r12d\n int v14; // r12d\n int v15; // eax\n unsigned int *v16; // r13\n unsigned int *v17; // rbx\n int v18; // ebx\n size_t v19; // r14\n _WORD *v20; // rax\n _WORD *v21; // r15\n _DWORD *v22; // rbx\n _DWORD *v23; // r12\n int v24; // eax\n _WORD *v26; // rax\n _DWORD v28[3]; // [rsp+8h] [rbp-80h] BYREF\n int v29; // [rsp+14h] [rbp-74h]\n _DWORD *v30; // [rsp+18h] [rbp-70h]\n __int64 v31; // [rsp+20h] [rbp-68h]\n _DWORD *v32; // [rsp+28h] [rbp-60h]\n __int64 v33; // [rsp+30h] [rbp-58h]\n char s[12]; // [rsp+44h] [rbp-44h] BYREF\n unsigned __int64 v35; // [rsp+50h] [rbp-38h]\n\n v35 = __readfsqword(0x28u);\n while ( v28 != (_DWORD *)((char *)v28 - ((20LL * a2 + 15) & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v2 = (20 * (_WORD)a2 + 15) & 0xFF0;\n v3 = alloca(v2);\n if ( ((20 * (_WORD)a2 + 15) & 0xFF0) != 0 )\n *(_QWORD *)((char *)&v28[-2] + v2) = *(_QWORD *)((char *)&v28[-2] + v2);\n if ( a2 <= 0 )\n goto LABEL_37;\n v4 = a1;\n v5 = 0;\n do\n {\n if ( v5 > 0 )\n {\n v10 = v4->m128i_i32[3];\n v7 = v28;\n for ( i = 0; i != v5; ++i )\n {\n if ( v7[3] == v10 )\n {\n if ( v10 <= 0 )\n {\nLABEL_13:\n ++*((_DWORD *)&v30 + 5 * i);\n goto LABEL_15;\n }\n v8 = 0LL;\n while ( v7[v8] == v4->m128i_i32[v8] )\n {\n if ( ++v8 == v10 )\n goto LABEL_13;\n }\n }\n v7 += 5;\n }\n }\n v9 = 5LL * v5;\n *(__m128i *)&v28[v9] = _mm_loadu_si128(v4);\n *((_DWORD *)&v30 + v9) = 1;\n ++v5;\nLABEL_15:\n ++v4;\n }\n while ( v4 != &a1[a2] );\n if ( v5 <= 0 )\n {\nLABEL_37:\n v26 = malloc(3uLL);\n v21 = v26;\n if ( v26 )\n {\n *v26 = 91;\n v19 = 3LL;\n goto LABEL_36;\n }\nLABEL_38:\n fwrite(\"Memory allocation failed\\n\", 1uLL, 0x19uLL, stderr);\n exit(1);\n }\n v30 = v28;\n v31 = 5LL * v5;\n v33 = 0LL;\n v11 = 2;\n v29 = v5;\n v12 = v28;\n do\n {\n v14 = v11 + 2;\n v32 = v12;\n v15 = v12[3];\n if ( v15 > 0 )\n {\n v16 = &v30[v33 + v15];\n v17 = v12;\n do\n {\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, *v17);\n v14 += strlen(s) + 2;\n ++v17;\n }\n while ( v17 != v16 );\n }\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, (unsigned int)v32[4]);\n v13 = strlen(s) + v14;\n v11 = v13 + 2;\n v12 += 5;\n v33 += 5LL;\n }\n while ( v33 != v31 );\n v18 = v29;\n v19 = v13 + 1;\n v20 = malloc(v19);\n v21 = v20;\n if ( !v20 )\n goto LABEL_38;\n __memcpy_chk(v20, \"[\", 2LL, v13 + 1);\n LODWORD(v33) = 0;\n v29 = v18;\n do\n {\n __strcat_chk(v21, \"(\", v19);\n v23 = v30;\n v24 = v30[3];\n if ( v24 > 0 )\n {\n v32 = (_DWORD *)v24;\n v22 = 0LL;\n LODWORD(v31) = v24 - 1;\n do\n {\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, (unsigned int)v23[(_QWORD)v22]);\n __strcat_chk(v21, s, v19);\n if ( (int)v31 > (int)v22 )\n __strcat_chk(v21, \", \", v19);\n v22 = (_DWORD *)((char *)v22 + 1);\n }\n while ( v22 != v32 );\n }\n __strcat_chk(v21, \", \", v19);\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, (unsigned int)v23[4]);\n __strcat_chk(v21, s, v19);\n __strcat_chk(v21, L\")]\", v19);\n if ( v29 - 1 > (int)v33 )\n __strcat_chk(v21, \", \", v19);\n LODWORD(v33) = v33 + 1;\n v30 += 5;\n }\n while ( v29 != (_DWORD)v33 );\nLABEL_36:\n __strcat_chk(v21, L\"]\", v19);\n return v21;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned short *sub_1289(const __m128i *a1, int a2) {\n signed long long v2;\n void *v3;\n const __m128i *v4;\n int v5;\n int i;\n uint32_t *v7;\n long long v8;\n long long v9;\n int v10;\n int v11;\n uint32_t *v12;\n int v13;\n int v14;\n int v15;\n unsigned int *v16;\n unsigned int *v17;\n int v18;\n unsigned int v19;\n unsigned short *v20;\n unsigned short *v21;\n uint32_t *v22;\n uint32_t *v23;\n int v24;\n unsigned short *v26;\n uint32_t v28[3];\n int v29;\n uint32_t *v30;\n long long v31;\n uint32_t *v32;\n long long v33;\n char s[12];\n unsigned long long v35;\n v35 = __readfsqword(40u);\n while (v28 != (uint32_t *)((char *)v28 -\n ((20LL * a2 + 15) & 18446744073709547520LL)))\n ;\n v2 = (20 * (unsigned short)a2 + 15) & 4080;\n v3 = alloca(v2);\n if (((20 * (unsigned short)a2 + 15) & 4080) != 0)\n *(uint64_t *)((char *)&v28[-2] + v2) = *(uint64_t *)((char *)&v28[-2] + v2);\n if (a2 <= 0) goto LABEL_37;\n v4 = a1;\n v5 = 0;\n do {\n if (v5 > 0) {\n v10 = v4->m128i_i32[3];\n v7 = v28;\n for (i = 0; i != v5; ++i) {\n if (v7[3] == v10) {\n if (v10 <= 0) {\n LABEL_13:\n ++*((uint32_t *)&v30 + 5 * i);\n goto LABEL_15;\n }\n v8 = 0LL;\n while (v7[v8] == v4->m128i_i32[v8]) {\n if (++v8 == v10) goto LABEL_13;\n }\n }\n v7 += 5;\n }\n }\n v9 = 5LL * v5;\n *(__m128i *)&v28[v9] = _mm_loadu_si128(v4);\n *((uint32_t *)&v30 + v9) = 1;\n ++v5;\n LABEL_15:\n ++v4;\n } while (v4 != &a1[a2]);\n if (v5 <= 0) {\n LABEL_37:\n v26 = malloc(3uLL);\n v21 = v26;\n if (v26) {\n *v26 = 91;\n v19 = 3LL;\n goto LABEL_36;\n }\n LABEL_38:\n fwrite(\"Memory allocation failed\\n\", 1uLL, 25uLL, stderr);\n exit(1);\n }\n v30 = v28;\n v31 = 5LL * v5;\n v33 = 0LL;\n v11 = 2;\n v29 = v5;\n v12 = v28;\n do {\n v14 = v11 + 2;\n v32 = v12;\n v15 = v12[3];\n if (v15 > 0) {\n v16 = &v30[v33 + v15];\n v17 = v12;\n do {\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, *v17);\n v14 += strlen(s) + 2;\n ++v17;\n } while (v17 != v16);\n }\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, (unsigned int)v32[4]);\n v13 = strlen(s) + v14;\n v11 = v13 + 2;\n v12 += 5;\n v33 += 5LL;\n } while (v33 != v31);\n v18 = v29;\n v19 = v13 + 1;\n v20 = malloc(v19);\n v21 = v20;\n if (!v20) goto LABEL_38;\n __memcpy_chk(v20, \"[\", 2LL, v13 + 1);\n LODWORD(v33) = 0;\n v29 = v18;\n do {\n __strcat_chk(v21, \"(\", v19);\n v23 = v30;\n v24 = v30[3];\n if (v24 > 0) {\n v32 = (uint32_t *)v24;\n v22 = 0LL;\n LODWORD(v31) = v24 - 1;\n do {\n __sprintf_chk(s, 2LL, 12LL, &unk_2004,\n (unsigned int)v23[(uint64_t)v22]);\n __strcat_chk(v21, s, v19);\n if ((int)v31 > (int)v22) __strcat_chk(v21, \", \", v19);\n v22 = (uint32_t *)((char *)v22 + 1);\n } while (v22 != v32);\n }\n __strcat_chk(v21, \", \", v19);\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, (unsigned int)v23[4]);\n __strcat_chk(v21, s, v19);\n __strcat_chk(v21, L\")]\", v19);\n if (v29 - 1 > (int)v33) __strcat_chk(v21, \", \", v19);\n LODWORD(v33) = v33 + 1;\n v30 += 5;\n } while (v29 != (uint32_t)v33);\nLABEL_36:\n __strcat_chk(v21, L\"]\", v19);\n return v21;\n}", + "ida_pseudo_norm": "unsigned short *func0(const __m128i *a1, int a2) {\n signed long long v2;\n void *v3;\n const __m128i *v4;\n int v5;\n int i;\n uint32_t *v7;\n long long v8;\n long long v9;\n int v10;\n int v11;\n uint32_t *v12;\n int v13;\n int v14;\n int v15;\n unsigned int *v16;\n unsigned int *v17;\n int v18;\n unsigned int v19;\n unsigned short *v20;\n unsigned short *v21;\n uint32_t *v22;\n uint32_t *v23;\n int v24;\n unsigned short *v26;\n uint32_t v28[3];\n int v29;\n uint32_t *v30;\n long long v31;\n uint32_t *v32;\n long long v33;\n char s[12];\n unsigned long long v35;\n v35 = __readfsqword(40u);\n while (v28 != (uint32_t *)((char *)v28 -\n ((20LL * a2 + 15) & 18446744073709547520LL)))\n ;\n v2 = (20 * (unsigned short)a2 + 15) & 4080;\n v3 = alloca(v2);\n if (((20 * (unsigned short)a2 + 15) & 4080) != 0)\n *(uint64_t *)((char *)&v28[-2] + v2) = *(uint64_t *)((char *)&v28[-2] + v2);\n if (a2 <= 0) goto LABEL_37;\n v4 = a1;\n v5 = 0;\n do {\n if (v5 > 0) {\n v10 = v4->m128i_i32[3];\n v7 = v28;\n for (i = 0; i != v5; ++i) {\n if (v7[3] == v10) {\n if (v10 <= 0) {\n LABEL_13:\n ++*((uint32_t *)&v30 + 5 * i);\n goto LABEL_15;\n }\n v8 = 0LL;\n while (v7[v8] == v4->m128i_i32[v8]) {\n if (++v8 == v10) goto LABEL_13;\n }\n }\n v7 += 5;\n }\n }\n v9 = 5LL * v5;\n *(__m128i *)&v28[v9] = _mm_loadu_si128(v4);\n *((uint32_t *)&v30 + v9) = 1;\n ++v5;\n LABEL_15:\n ++v4;\n } while (v4 != &a1[a2]);\n if (v5 <= 0) {\n LABEL_37:\n v26 = malloc(3uLL);\n v21 = v26;\n if (v26) {\n *v26 = 91;\n v19 = 3LL;\n goto LABEL_36;\n }\n LABEL_38:\n fwrite(\"Memory allocation failed\\n\", 1uLL, 25uLL, _bss_start);\n exit(1);\n }\n v30 = v28;\n v31 = 5LL * v5;\n v33 = 0LL;\n v11 = 2;\n v29 = v5;\n v12 = v28;\n do {\n v14 = v11 + 2;\n v32 = v12;\n v15 = v12[3];\n if (v15 > 0) {\n v16 = &v30[v33 + v15];\n v17 = v12;\n do {\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, *v17);\n v14 += strlen(s) + 2;\n ++v17;\n } while (v17 != v16);\n }\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, (unsigned int)v32[4]);\n v13 = strlen(s) + v14;\n v11 = v13 + 2;\n v12 += 5;\n v33 += 5LL;\n } while (v33 != v31);\n v18 = v29;\n v19 = v13 + 1;\n v20 = malloc(v19);\n v21 = v20;\n if (!v20) goto LABEL_38;\n __memcpy_chk(v20, \"[\", 2LL, v13 + 1);\n LODWORD(v33) = 0;\n v29 = v18;\n do {\n __strcat_chk(v21, \"(\", v19);\n v23 = v30;\n v24 = v30[3];\n if (v24 > 0) {\n v32 = (uint32_t *)v24;\n v22 = 0LL;\n LODWORD(v31) = v24 - 1;\n do {\n __sprintf_chk(s, 2LL, 12LL, &unk_2004,\n (unsigned int)v23[(uint64_t)v22]);\n __strcat_chk(v21, s, v19);\n if ((int)v31 > (int)v22) __strcat_chk(v21, \", \", v19);\n v22 = (uint32_t *)((char *)v22 + 1);\n } while (v22 != v32);\n }\n __strcat_chk(v21, \", \", v19);\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, (unsigned int)v23[4]);\n __strcat_chk(v21, s, v19);\n __strcat_chk(v21, L\")]\", v19);\n if (v29 - 1 > (int)v33) __strcat_chk(v21, \", \", v19);\n LODWORD(v33) = v33 + 1;\n v30 += 5;\n } while (v29 != (uint32_t)v33);\nLABEL_36:\n __strcat_chk(v21, L\"]\", v19);\n return v21;\n}" + }, + { + "index": 114, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int elements[3];\n\n int length;\n\n} Tuple;\n\n\n\ntypedef struct {\n\n Tuple tuple;\n\n int count;\n\n} TupleCount;\n\n\n\n", + "func": "char* func0(Tuple input[], int input_size) {\n TupleCount counts[input_size];\n int unique = 0;\n for (int i = 0; i < input_size; i++) {\n int found = 0;\n for (int j = 0; j < unique; j++) {\n if (counts[j].tuple.length == input[i].length) {\n int match = 1;\n for (int k = 0; k < input[i].length; k++) {\n if (counts[j].tuple.elements[k] != input[i].elements[k]) {\n match = 0;\n break;\n }\n }\n if (match) {\n counts[j].count++;\n found = 1;\n break;\n }\n }\n }\n if (!found) {\n counts[unique].tuple = input[i];\n counts[unique].count = 1;\n unique++;\n }\n }\n int size = 2;\n for (int i = 0; i < unique; i++) {\n size += 2;\n for (int j = 0; j < counts[i].tuple.length; j++) {\n char num[12];\n sprintf(num, \"%d\", counts[i].tuple.elements[j]);\n size += strlen(num) + 2;\n }\n char cnt[12];\n sprintf(cnt, \"%d\", counts[i].count);\n size += strlen(cnt) + 2;\n }\n if (unique > 0) size -= 2;\n size += 1;\n char* result = malloc(size);\n if (result == NULL) {\n fprintf(stderr, \"Memory allocation failed\\n\");\n exit(1);\n }\n strcpy(result, \"[\");\n for (int i = 0; i < unique; i++) {\n strcat(result, \"(\");\n for (int j = 0; j < counts[i].tuple.length; j++) {\n char num[12];\n sprintf(num, \"%d\", counts[i].tuple.elements[j]);\n strcat(result, num);\n if (j < counts[i].tuple.length - 1) strcat(result, \", \");\n }\n strcat(result, \", \");\n char cnt[12];\n sprintf(cnt, \"%d\", counts[i].count);\n strcat(result, cnt);\n strcat(result, \")\");\n if (i < unique - 1) strcat(result, \", \");\n }\n strcat(result, \"]\");\n return result;\n}", + "test": "int main() {\n\n // First test case\n\n Tuple test1[] = {\n\n { .elements = {6, 5, 8}, .length = 3 },\n\n { .elements = {2, 7, 0}, .length = 2 },\n\n { .elements = {6, 5, 8}, .length = 3 },\n\n { .elements = {6, 5, 8}, .length = 3 },\n\n { .elements = {9, 0, 0}, .length = 1 },\n\n { .elements = {2, 7, 0}, .length = 2 }\n\n };\n\n char* res1 = func0(test1, 6);\n\n assert(strcmp(res1, \"[(6, 5, 8, 3), (2, 7, 2), (9, 1)]\") == 0);\n\n free(res1);\n\n\n\n // Second test case\n\n Tuple test2[] = {\n\n { .elements = {4, 2, 4}, .length = 3 },\n\n { .elements = {7, 1, 0}, .length = 2 },\n\n { .elements = {4, 8, 0}, .length = 2 },\n\n { .elements = {4, 2, 4}, .length = 3 },\n\n { .elements = {9, 2, 0}, .length = 2 },\n\n { .elements = {7, 1, 0}, .length = 2 }\n\n };\n\n char* res2 = func0(test2, 6);\n\n assert(strcmp(res2, \"[(4, 2, 4, 2), (7, 1, 2), (4, 8, 1), (9, 2, 1)]\") == 0);\n\n free(res2);\n\n\n\n // Third test case\n\n Tuple test3[] = {\n\n { .elements = {11, 13, 10}, .length = 3 },\n\n { .elements = {17, 21, 0}, .length = 2 },\n\n { .elements = {4, 2, 3}, .length = 3 },\n\n { .elements = {17, 21, 0}, .length = 2 },\n\n { .elements = {9, 2, 0}, .length = 2 },\n\n { .elements = {4, 2, 3}, .length = 3 }\n\n };\n\n char* res3 = func0(test3, 6);\n\n assert(strcmp(res3, \"[(11, 13, 10, 1), (17, 21, 2), (4, 2, 3, 2), (9, 2, 1)]\") == 0);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0x48,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nmovslq %esi,%rax\nmov %rsp,%rbx\nlea (%rax,%rax,4),%rax\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rbx\nand $0xfffffffffffffff0,%rdx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 1563 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 154e \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 19f7 \nmov %rsp,%r9\ntest %esi,%esi\njle 19be \nlea -0x1(%rsi),%eax\nxor %ebx,%ebx\nshl $0x4,%rax\nlea 0x10(%rdi,%rax,1),%r8\nxchg %ax,%ax\ntest %ebx,%ebx\nje 1980 \nmov 0xc(%rdi),%esi\nmov %r9,%rdx\nxor %ecx,%ecx\njmp 15b7 \nnopw 0x0(%rax,%rax,1)\nadd $0x1,%ecx\nadd $0x14,%rdx\ncmp %ebx,%ecx\nje 1980 \ncmp %esi,0xc(%rdx)\njne 15a8 \ntest %esi,%esi\njle 15da \nxor %eax,%eax\nnopw 0x0(%rax,%rax,1)\nmov (%rdi,%rax,4),%r11d\ncmp %r11d,(%rdx,%rax,4)\njne 15a8 \nadd $0x1,%rax\ncmp %eax,%esi\njg 15c8 \nmovslq %ecx,%rcx\nlea (%rcx,%rcx,4),%rax\naddl $0x1,0x10(%r9,%rax,4)\nnopw 0x0(%rax,%rax,1)\nadd $0x10,%rdi\ncmp %r8,%rdi\njne 1590 \nlea -0x1(%rbx),%eax\nlea -0x44(%rbp),%r14\nmov %ebx,-0x58(%rbp)\nmov $0x2,%r10d\nmov %eax,-0x64(%rbp)\nlea (%rax,%rax,4),%rax\nmov %r9,%rbx\nmov %r14,%r13\nlea 0x14(%r9,%rax,4),%rax\nmov %r9,-0x70(%rbp)\nmov %rax,-0x60(%rbp)\nnopl 0x0(%rax,%rax,1)\nmov 0xc(%rbx),%r12d\nlea 0x2(%r10),%r14d\nmov %r14d,%r10d\ntest %r12d,%r12d\njle 16ab \nxor %r15d,%r15d\nnopl 0x0(%rax,%rax,1)\nmov (%rbx,%r15,4),%r8d\nmov $0xc,%edx\nmov $0x1,%esi\nxor %eax,%eax\nlea 0x9ad(%rip),%rcx\nmov %r13,%rdi\ncallq 1130 <__sprintf_chk@plt>\nmov %r13,%rdx\nmov (%rdx),%ecx\nadd $0x4,%rdx\nlea -0x1010101(%rcx),%eax\nnot %ecx\nand %ecx,%eax\nand $0x80808080,%eax\nje 1662 \nmov %eax,%ecx\nshr $0x10,%ecx\ntest $0x8080,%eax\ncmove %ecx,%eax\nlea 0x2(%rdx),%rcx\ncmove %rcx,%rdx\nmov %eax,%esi\nadd %al,%sil\nsbb $0x3,%rdx\nadd $0x1,%r15\nsub %r13,%rdx\nlea 0x2(%r14,%rdx,1),%r10d\nmov %r10d,%r14d\ncmp %r15d,%r12d\njg 1640 \nmov 0x10(%rbx),%r8d\nmov $0xc,%edx\nmov $0x1,%esi\nxor %eax,%eax\nlea 0x942(%rip),%rcx\nmov %r13,%rdi\nmov %r10d,-0x54(%rbp)\ncallq 1130 <__sprintf_chk@plt>\nmov -0x54(%rbp),%r10d\nmov %r13,%rdx\nmov (%rdx),%ecx\nadd $0x4,%rdx\nlea -0x1010101(%rcx),%eax\nnot %ecx\nand %ecx,%eax\nand $0x80808080,%eax\nje 16d5 \nmov %eax,%ecx\nshr $0x10,%ecx\ntest $0x8080,%eax\ncmove %ecx,%eax\nlea 0x2(%rdx),%rcx\ncmove %rcx,%rdx\nmov %eax,%esi\nadd %al,%sil\nsbb $0x3,%rdx\nadd $0x14,%rbx\nsub %r13,%rdx\nadd %r10d,%edx\nlea 0x2(%rdx),%r10d\ncmp %rbx,-0x60(%rbp)\njne 1628 \nmov %edx,%r15d\nmov -0x58(%rbp),%ebx\nmov %r13,%r14\nadd $0x1,%r15d\nmovslq %r15d,%rdi\ncallq 1100 \nmov %rax,%r12\ntest %rax,%rax\nje 19d0 \nmov $0x5b,%edx\nmovl $0x0,-0x60(%rbp)\nlea 0x8ae(%rip),%r15\nmov %dx,(%r12)\nmov %ebx,-0x68(%rbp)\nmov -0x70(%rbp),%rbx\nnopw 0x0(%rax,%rax,1)\nmov %r12,%rdx\nmov (%rdx),%ecx\nadd $0x4,%rdx\nlea -0x1010101(%rcx),%eax\nnot %ecx\nand %ecx,%eax\nand $0x80808080,%eax\nje 176b \nmov %eax,%ecx\nmov $0x28,%r10d\nshr $0x10,%ecx\ntest $0x8080,%eax\ncmove %ecx,%eax\nlea 0x2(%rdx),%rcx\ncmove %rcx,%rdx\nmov %eax,%esi\nadd %al,%sil\nmov 0xc(%rbx),%eax\nsbb $0x3,%rdx\nxor %r13d,%r13d\nlea -0x1(%rax),%esi\nmov %r10w,(%rdx)\nmov %eax,-0x58(%rbp)\nmov %esi,-0x54(%rbp)\ntest %eax,%eax\njle 182c \nmov (%rbx,%r13,4),%r8d\nmov %r14,%rdi\nmov %r15,%rcx\nmov $0xc,%edx\nmov $0x1,%esi\nxor %eax,%eax\ncallq 1130 <__sprintf_chk@plt>\nmov %r12,%rdi\nmov (%rdi),%edx\nadd $0x4,%rdi\nlea -0x1010101(%rdx),%eax\nnot %edx\nand %edx,%eax\nand $0x80808080,%eax\nje 17db \nmov %eax,%edx\nshr $0x10,%edx\ntest $0x8080,%eax\ncmove %edx,%eax\nlea 0x2(%rdi),%rdx\ncmove %rdx,%rdi\nmov %eax,%esi\nadd %al,%sil\nmov %r14,%rsi\nsbb $0x3,%rdi\ncallq 10d0 \ncmp %r13d,-0x54(%rbp)\njg 1968 \nadd $0x1,%r13\ncmp %r13d,-0x58(%rbp)\njg 17bd \nmov %r12,%rdx\nmov (%rdx),%ecx\nadd $0x4,%rdx\nlea -0x1010101(%rcx),%eax\nnot %ecx\nand %ecx,%eax\nand $0x80808080,%eax\nje 182f \nmov %eax,%ecx\nmov $0x202c,%r9d\nmov 0x10(%rbx),%r8d\nmov %r14,%rdi\nshr $0x10,%ecx\ntest $0x8080,%eax\ncmove %ecx,%eax\nlea 0x2(%rdx),%rcx\ncmove %rcx,%rdx\nmov %r15,%rcx\nmov %eax,%esi\nadd %al,%sil\nmov $0x1,%esi\nsbb $0x3,%rdx\nxor %eax,%eax\nmov %r9w,(%rdx)\nmovb $0x0,0x2(%rdx)\nmov $0xc,%edx\ncallq 1130 <__sprintf_chk@plt>\nmov %r12,%rdi\nmov (%rdi),%edx\nadd $0x4,%rdi\nlea -0x1010101(%rdx),%eax\nnot %edx\nand %edx,%eax\nand $0x80808080,%eax\nje 1890 \nmov %eax,%edx\nshr $0x10,%edx\ntest $0x8080,%eax\ncmove %edx,%eax\nlea 0x2(%rdi),%rdx\ncmove %rdx,%rdi\nmov %eax,%esi\nadd %al,%sil\nmov %r14,%rsi\nsbb $0x3,%rdi\ncallq 10d0 \nmov $0x29,%r8d\nmov -0x60(%rbp),%esi\nmov %rax,%rdx\nmov %r8w,(%rax)\nsub %r12,%rdx\ncmp %esi,-0x64(%rbp)\njg 19a8 \naddl $0x1,-0x60(%rbp)\nadd $0x14,%rbx\nmov -0x60(%rbp),%eax\ncmp %eax,-0x68(%rbp)\njne 1768 \nmov %r12,%rdx\nmov (%rdx),%ecx\nadd $0x4,%rdx\nlea -0x1010101(%rcx),%eax\nnot %ecx\nand %ecx,%eax\nand $0x80808080,%eax\nje 1900 \nmov %eax,%ecx\nshr $0x10,%ecx\ntest $0x8080,%eax\ncmove %ecx,%eax\nlea 0x2(%rdx),%rcx\ncmove %rcx,%rdx\nmov $0x5d,%ecx\nmov %eax,%ebx\nadd %al,%bl\nsbb $0x3,%rdx\nmov %cx,(%rdx)\nmov -0x38(%rbp),%rax\nxor %fs:0x28,%rax\njne 1a11 \nlea -0x28(%rbp),%rsp\nmov %r12,%rax\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\nnopl 0x0(%rax)\nmov $0x202c,%edi\nmovb $0x0,0x2(%rax)\nmov %di,(%rax)\njmpq 1822 \nnopl 0x0(%rax)\nmovslq %ebx,%rax\nmovdqu (%rdi),%xmm0\nadd $0x1,%ebx\nlea (%rax,%rax,4),%rax\nlea (%r9,%rax,4),%rax\nmovl $0x1,0x10(%rax)\nmovups %xmm0,(%rax)\njmpq 15f0 \nnopl 0x0(%rax)\nlea 0x1(%r12,%rdx,1),%rax\nmov $0x202c,%esi\nmov %si,(%rax)\nmovb $0x0,0x2(%rax)\njmpq 18e9 \nmov $0x3,%edi\ncallq 1100 \nmov %rax,%r12\ntest %rax,%rax\njne 1a02 \nmov 0x2649(%rip),%rcx\nmov $0x19,%edx\nmov $0x1,%esi\nlea 0x61f(%rip),%rdi\ncallq 1120 \nmov $0x1,%edi\ncallq 1110 \norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 1575 \nmov $0x5b,%eax\nmov %ax,(%r12)\njmpq 18fd \ncallq 10e0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmovsxd r10, esi\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 48h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nlea rax, [r10+r10*4]\nmov rcx, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_1510\nloc_14FB:\nsub rsp, 1000h\nor [rsp+1070h+var_78], 0\ncmp rsp, rcx\njnz short loc_14FB\nloc_1510:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_188E\nloc_1522:\nmov r8, rsp\ntest esi, esi\njle loc_1899\nshl r10, 4\nmov rsi, rdi\nxor ebx, ebx\nadd r10, rdi\nnop dword ptr [rax+00000000h]\nloc_1540:\ntest ebx, ebx\njle loc_1860\nloc_1548:\nmovsxd rdi, dword ptr [rsi+0Ch]\nmov rdx, r8\nxor ecx, ecx\nmov r9, rdi\njmp short loc_156F\nloc_1560:\nadd ecx, 1\nadd rdx, 14h\ncmp ecx, ebx\njz loc_1860\nloc_156F:\ncmp [rdx+0Ch], r9d\njnz short loc_1560\ntest r9d, r9d\njle short loc_1593\nxor eax, eax\nnop dword ptr [rax+00h]\nloc_1580:\nmov r11d, [rsi+rax*4]\ncmp [rdx+rax*4], r11d\njnz short loc_1560\nadd rax, 1\ncmp rax, rdi\njnz short loc_1580\nloc_1593:\nmovsxd rcx, ecx\nadd rsi, 10h\nlea rax, [rcx+rcx*4]\nadd dword ptr [r8+rax*4+10h], 1\ncmp rsi, r10\njnz short loc_1548\nloc_15A9:\ntest ebx, ebx\njle loc_1899\nmovsxd rax, ebx\nmov [rbp+var_60], ebx\nmov r15, r8\nmov r9d, 2\nlea rax, [rax+rax*4]\nmov [rbp+var_58], 0\nlea r12, [rbp+s]\nmov [rbp+var_68], rax\nmov [rbp+var_70], r8\nnop dword ptr [rax+rax+00000000h]\nloc_15E0:\nmovsxd rax, dword ptr [r15+0Ch]\nlea r14d, [r9+2]\nmov r10d, r14d\ntest eax, eax\njle short loc_1638\nmov rbx, [rbp+var_58]\nadd rax, rbx\nmov rbx, [rbp+var_70]\nlea r13, [rbx+rax*4]\nmov rbx, r15\nloc_1601:\nmov r8d, [rbx]\nlea rcx, unk_2004\nmov rdi, r12\nxor eax, eax\nmov edx, 0Ch\nmov esi, 2\nadd rbx, 4\ncall ___sprintf_chk\nmov rdi, r12; s\ncall _strlen\nlea r10d, [r14+rax+2]\nmov r14d, r10d\ncmp r13, rbx\njnz short loc_1601\nloc_1638:\nmov r8d, [r15+10h]\nmov esi, 2\nmov edx, 0Ch\nxor eax, eax\nlea rcx, unk_2004\nmov rdi, r12\nmov [rbp+var_5C], r10d\nadd r15, 14h\ncall ___sprintf_chk\nmov rdi, r12; s\ncall _strlen\nmov r10d, [rbp+var_5C]\nadd [rbp+var_58], 5\nmov rsi, [rbp+var_68]\nmov rbx, [rbp+var_58]\nadd eax, r10d\nlea r9d, [rax+2]\ncmp rbx, rsi\njnz loc_15E0\nadd eax, 1\nmov r8, [rbp+var_70]\nmov ebx, [rbp+var_60]\nmovsxd r15, eax\nmov rdi, r15; size\nmov [rbp+var_58], r8\ncall _malloc\nmov r8, [rbp+var_58]\ntest rax, rax\nmov r13, rax\njz loc_18C5\nmov rcx, r15\nmov edx, 2\nmov rdi, rax\nmov [rbp+var_58], r8\nlea rsi, asc_2028+2; \"[\"\ncall ___memcpy_chk\nlea eax, [rbx-1]\nmov r8, [rbp+var_58]\nmov [rbp+var_60], ebx\nmov dword ptr [rbp+var_70], eax\nmov dword ptr [rbp+var_58], 0\nmov rbx, r8\nnop dword ptr [rax+rax+00h]\nloc_16E8:\nmov rdx, r15\nlea rsi, asc_2023; \"(\"\nmov rdi, r13\ncall ___strcat_chk\nmovsxd rax, dword ptr [rbx+0Ch]\ntest eax, eax\njle short loc_175A\nlea ecx, [rax-1]\nmov [rbp+var_68], rax\nxor r14d, r14d\nmov [rbp+var_5C], ecx\nloc_170F:\nmov r8d, [rbx+r14*4]\nmov edx, 0Ch\nmov esi, 2\nxor eax, eax\nlea rcx, unk_2004\nmov rdi, r12\ncall ___sprintf_chk\nmov rdi, r13; s\ncall _strlen\nmov rdx, r15\nmov rsi, r12\nlea rdi, [r13+rax+0]\ncall ___stpcpy_chk\ncmp [rbp+var_5C], r14d\njg loc_1838\nloc_1750:\nadd r14, 1\ncmp [rbp+var_68], r14\njnz short loc_170F\nloc_175A:\nmov rdx, r15\nlea rsi, asc_2025; \", \"\nmov rdi, r13\nmov r14, r13\ncall ___strcat_chk\nmov r8d, [rbx+10h]\nmov edx, 0Ch\nxor eax, eax\nlea rcx, unk_2004\nmov esi, 2\nmov rdi, r12\ncall ___sprintf_chk\nmov rdi, r13; s\ncall _strlen\nmov rdx, r15\nmov rsi, r12\nlea rdi, [r13+rax+0]\ncall ___stpcpy_chk\nmov edx, 2\nlea rsi, asc_2028; \")[\"\nsub r14, rax\nmov rdi, rax\nadd r14, r15\nmov rcx, r14\ncall ___memcpy_chk\nmov ecx, dword ptr [rbp+var_58]\nmov rdi, rax\ncmp dword ptr [rbp+var_70], ecx\njle short loc_17E7\nlea rcx, [r14-1]\nadd rdi, 1\nmov edx, 3\nlea rsi, asc_2025; \", \"\ncall ___memcpy_chk\nloc_17E7:\nadd dword ptr [rbp+var_58], 1\nmov esi, [rbp+var_60]\nadd rbx, 14h\nmov eax, dword ptr [rbp+var_58]\ncmp eax, esi\njnz loc_16E8\nloc_17FD:\nmov rdx, r15\nlea rsi, asc_2021; \"]\"\nmov rdi, r13\ncall ___strcat_chk\nmov rax, [rbp+var_38]\nsub rax, fs:28h\njnz loc_18C0\nlea rsp, [rbp-28h]\nmov rax, r13\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1838:\nmov rcx, r13\nmov edx, 3\nlea rsi, asc_2025; \", \"\nmov rdi, rax\nsub rcx, rax\nadd rcx, r15\ncall ___memcpy_chk\njmp loc_1750\nloc_1860:\nmovsxd rax, ebx\nmovdqu xmm0, xmmword ptr [rsi]\nadd rsi, 10h\nadd ebx, 1\nlea rax, [rax+rax*4]\nlea rax, [r8+rax*4]\nmov dword ptr [rax+10h], 1\nmovups xmmword ptr [rax], xmm0\ncmp rsi, r10\njnz loc_1540\njmp loc_15A9\nloc_188E:\nor [rsp+rdx+1070h+var_1078], 0\njmp loc_1522\nloc_1899:\nmov edi, 3; size\ncall _malloc\nmov r13, rax\ntest rax, rax\njz short loc_18C5\nmov eax, 5Bh ; '['\nmov r15d, 3\nmov [r13+0], ax\njmp loc_17FD\nloc_18C0:\ncall ___stack_chk_fail\nloc_18C5:\nmov rcx, cs:__bss_start; s\nmov edx, 19h; n\nmov esi, 1; size\nlea rdi, aMemoryAllocati; \"Memory allocation failed\\n\"\ncall _fwrite\nmov edi, 1; status\ncall _exit", + "ida_pseudo": "char *__fastcall func0(const __m128i *a1, int a2)\n{\n __int64 v2; // rdx\n _DWORD *v3; // rcx\n __int16 v4; // dx\n signed __int64 v5; // rdx\n void *v6; // rsp\n __int64 v7; // r10\n const __m128i *v8; // rsi\n int v9; // ebx\n const __m128i *v10; // r10\n _DWORD *v11; // rdx\n int v12; // ecx\n int v13; // r9d\n __int64 v14; // rax\n unsigned int *v15; // r15\n int v16; // r9d\n __int64 v17; // rax\n int v18; // r14d\n int v19; // r10d\n unsigned int *v20; // r13\n unsigned int *v21; // rbx\n __int64 v22; // r8\n __int64 v23; // r8\n int v24; // eax\n int v25; // eax\n int v26; // ebx\n size_t v27; // r15\n char *v28; // rax\n char *v29; // r13\n _DWORD *v30; // r8\n _DWORD *v31; // rbx\n int v32; // eax\n __int64 v33; // r14\n size_t v34; // rax\n __int64 v35; // rax\n size_t v36; // rax\n __int64 v37; // rax\n char *v38; // r14\n __int64 v39; // rax\n __int64 v41; // rax\n __m128i v42; // xmm0\n __m128i *v43; // rax\n _DWORD v45[1022]; // [rsp+8h] [rbp-1070h] BYREF\n _DWORD *v46; // [rsp+1008h] [rbp-70h] BYREF\n __int64 v47; // [rsp+1010h] [rbp-68h]\n int v48; // [rsp+1018h] [rbp-60h]\n int v49; // [rsp+101Ch] [rbp-5Ch]\n _DWORD *v50; // [rsp+1020h] [rbp-58h]\n char s[12]; // [rsp+1034h] [rbp-44h] BYREF\n unsigned __int64 v52; // [rsp+1040h] [rbp-38h]\n\n v52 = __readfsqword(0x28u);\n v2 = 20LL * a2 + 15;\n v3 = (_DWORD *)((char *)&v46 - (v2 & 0xFFFFFFFFFFFFF000LL));\n v4 = v2 & 0xFFF0;\n if ( &v46 != (_DWORD **)v3 )\n {\n while ( v45 != v3 )\n ;\n }\n v5 = v4 & 0xFFF;\n v6 = alloca(v5);\n if ( v5 )\n *(_QWORD *)((char *)&v45[-2] + v5) = *(_QWORD *)((char *)&v45[-2] + v5);\n if ( a2 <= 0 )\n goto LABEL_35;\n v7 = a2;\n v8 = a1;\n v9 = 0;\n v10 = &a1[v7];\n do\n {\n if ( v9 > 0 )\n {\n while ( 1 )\n {\n v11 = v45;\n v12 = 0;\n v13 = v8->m128i_i32[3];\n while ( v11[3] != v13 )\n {\nLABEL_9:\n ++v12;\n v11 += 5;\n if ( v12 == v9 )\n goto LABEL_33;\n }\n if ( v13 > 0 )\n break;\nLABEL_15:\n ++v8;\n ++v45[5 * v12 + 4];\n if ( v8 == v10 )\n goto LABEL_16;\n }\n v14 = 0LL;\n while ( v11[v14] == v8->m128i_i32[v14] )\n {\n if ( ++v14 == v8->m128i_i32[3] )\n goto LABEL_15;\n }\n goto LABEL_9;\n }\nLABEL_33:\n v41 = v9;\n v42 = _mm_loadu_si128(v8++);\n ++v9;\n v43 = (__m128i *)&v45[5 * v41];\n v43[1].m128i_i32[0] = 1;\n *v43 = v42;\n }\n while ( v8 != v10 );\nLABEL_16:\n if ( v9 <= 0 )\n {\nLABEL_35:\n v29 = (char *)malloc(3uLL);\n if ( v29 )\n {\n v27 = 3LL;\n *(_WORD *)v29 = 91;\n goto LABEL_32;\n }\nLABEL_37:\n fwrite(\"Memory allocation failed\\n\", 1uLL, 0x19uLL, _bss_start);\n exit(1);\n }\n v48 = v9;\n v15 = v45;\n v16 = 2;\n v50 = 0LL;\n v47 = 5LL * v9;\n v46 = v45;\n do\n {\n v17 = (int)v15[3];\n v18 = v16 + 2;\n v19 = v16 + 2;\n if ( (int)v17 > 0 )\n {\n v20 = &v46[(_QWORD)v50 + v17];\n v21 = v15;\n do\n {\n v22 = *v21++;\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, v22);\n v19 = v18 + strlen(s) + 2;\n v18 = v19;\n }\n while ( v20 != v21 );\n }\n v23 = v15[4];\n v49 = v19;\n v15 += 5;\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, v23);\n v24 = strlen(s);\n v50 = (_DWORD *)((char *)v50 + 5);\n v25 = v49 + v24;\n v16 = v25 + 2;\n }\n while ( v50 != (_DWORD *)v47 );\n v26 = v48;\n v27 = v25 + 1;\n v50 = v46;\n v28 = (char *)malloc(v27);\n v29 = v28;\n if ( !v28 )\n goto LABEL_37;\n __memcpy_chk(v28, L\"[\", 2LL, v27);\n v30 = v50;\n v48 = v26;\n LODWORD(v46) = v26 - 1;\n LODWORD(v50) = 0;\n v31 = v30;\n do\n {\n __strcat_chk(v29, \"(\", v27);\n v32 = v31[3];\n if ( v32 > 0 )\n {\n v47 = (int)v31[3];\n v33 = 0LL;\n v49 = v32 - 1;\n do\n {\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, (unsigned int)v31[v33]);\n v34 = strlen(v29);\n v35 = __stpcpy_chk(&v29[v34], s, v27);\n if ( v49 > (int)v33 )\n __memcpy_chk(v35, \", \", 3LL, &v29[v27 - v35]);\n ++v33;\n }\n while ( v47 != v33 );\n }\n __strcat_chk(v29, \", \", v27);\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, (unsigned int)v31[4]);\n v36 = strlen(v29);\n v37 = __stpcpy_chk(&v29[v36], s, v27);\n v38 = &v29[v27 - v37];\n v39 = __memcpy_chk(v37, L\")[\", 2LL, v38);\n if ( (int)v46 > (int)v50 )\n __memcpy_chk(v39 + 1, \", \", 3LL, v38 - 1);\n LODWORD(v50) = (_DWORD)v50 + 1;\n v31 += 5;\n }\n while ( (_DWORD)v50 != v48 );\nLABEL_32:\n __strcat_chk(v29, \"]\", v27);\n return v29;\n}", + "ida_strip_asm": "sub_14B0:\nendbr64\npush rbp\nmovsxd r10, esi\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 48h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nlea rax, [r10+r10*4]\nmov rcx, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_1510\nloc_14FB:\nsub rsp, 1000h\nor [rsp+1070h+var_78], 0\ncmp rsp, rcx\njnz short loc_14FB\nloc_1510:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_188E\nloc_1522:\nmov r8, rsp\ntest esi, esi\njle loc_1899\nshl r10, 4\nmov rsi, rdi\nxor ebx, ebx\nadd r10, rdi\nnop dword ptr [rax+00000000h]\nloc_1540:\ntest ebx, ebx\njle loc_1860\nloc_1548:\nmovsxd rdi, dword ptr [rsi+0Ch]\nmov rdx, r8\nxor ecx, ecx\nmov r9, rdi\njmp short loc_156F\nloc_1560:\nadd ecx, 1\nadd rdx, 14h\ncmp ecx, ebx\njz loc_1860\nloc_156F:\ncmp [rdx+0Ch], r9d\njnz short loc_1560\ntest r9d, r9d\njle short loc_1593\nxor eax, eax\nnop dword ptr [rax+00h]\nloc_1580:\nmov r11d, [rsi+rax*4]\ncmp [rdx+rax*4], r11d\njnz short loc_1560\nadd rax, 1\ncmp rax, rdi\njnz short loc_1580\nloc_1593:\nmovsxd rcx, ecx\nadd rsi, 10h\nlea rax, [rcx+rcx*4]\nadd dword ptr [r8+rax*4+10h], 1\ncmp rsi, r10\njnz short loc_1548\nloc_15A9:\ntest ebx, ebx\njle loc_1899\nmovsxd rax, ebx\nmov [rbp+var_60], ebx\nmov r15, r8\nmov r9d, 2\nlea rax, [rax+rax*4]\nmov [rbp+var_58], 0\nlea r12, [rbp+s]\nmov [rbp+var_68], rax\nmov [rbp+var_70], r8\nnop dword ptr [rax+rax+00000000h]\nloc_15E0:\nmovsxd rax, dword ptr [r15+0Ch]\nlea r14d, [r9+2]\nmov r10d, r14d\ntest eax, eax\njle short loc_1638\nmov rbx, [rbp+var_58]\nadd rax, rbx\nmov rbx, [rbp+var_70]\nlea r13, [rbx+rax*4]\nmov rbx, r15\nloc_1601:\nmov r8d, [rbx]\nlea rcx, unk_2004\nmov rdi, r12\nxor eax, eax\nmov edx, 0Ch\nmov esi, 2\nadd rbx, 4\ncall ___sprintf_chk\nmov rdi, r12; s\ncall _strlen\nlea r10d, [r14+rax+2]\nmov r14d, r10d\ncmp r13, rbx\njnz short loc_1601\nloc_1638:\nmov r8d, [r15+10h]\nmov esi, 2\nmov edx, 0Ch\nxor eax, eax\nlea rcx, unk_2004\nmov rdi, r12\nmov [rbp+var_5C], r10d\nadd r15, 14h\ncall ___sprintf_chk\nmov rdi, r12; s\ncall _strlen\nmov r10d, [rbp+var_5C]\nadd [rbp+var_58], 5\nmov rsi, [rbp+var_68]\nmov rbx, [rbp+var_58]\nadd eax, r10d\nlea r9d, [rax+2]\ncmp rbx, rsi\njnz loc_15E0\nadd eax, 1\nmov r8, [rbp+var_70]\nmov ebx, [rbp+var_60]\nmovsxd r15, eax\nmov rdi, r15; size\nmov [rbp+var_58], r8\ncall _malloc\nmov r8, [rbp+var_58]\ntest rax, rax\nmov r13, rax\njz loc_18C5\nmov rcx, r15\nmov edx, 2\nmov rdi, rax\nmov [rbp+var_58], r8\nlea rsi, asc_2028+2; \"[\"\ncall ___memcpy_chk\nlea eax, [rbx-1]\nmov r8, [rbp+var_58]\nmov [rbp+var_60], ebx\nmov dword ptr [rbp+var_70], eax\nmov dword ptr [rbp+var_58], 0\nmov rbx, r8\nnop dword ptr [rax+rax+00h]\nloc_16E8:\nmov rdx, r15\nlea rsi, asc_2023; \"(\"\nmov rdi, r13\ncall ___strcat_chk\nmovsxd rax, dword ptr [rbx+0Ch]\ntest eax, eax\njle short loc_175A\nlea ecx, [rax-1]\nmov [rbp+var_68], rax\nxor r14d, r14d\nmov [rbp+var_5C], ecx\nloc_170F:\nmov r8d, [rbx+r14*4]\nmov edx, 0Ch\nmov esi, 2\nxor eax, eax\nlea rcx, unk_2004\nmov rdi, r12\ncall ___sprintf_chk\nmov rdi, r13; s\ncall _strlen\nmov rdx, r15\nmov rsi, r12\nlea rdi, [r13+rax+0]\ncall ___stpcpy_chk\ncmp [rbp+var_5C], r14d\njg loc_1838\nloc_1750:\nadd r14, 1\ncmp [rbp+var_68], r14\njnz short loc_170F\nloc_175A:\nmov rdx, r15\nlea rsi, asc_2025; \", \"\nmov rdi, r13\nmov r14, r13\ncall ___strcat_chk\nmov r8d, [rbx+10h]\nmov edx, 0Ch\nxor eax, eax\nlea rcx, unk_2004\nmov esi, 2\nmov rdi, r12\ncall ___sprintf_chk\nmov rdi, r13; s\ncall _strlen\nmov rdx, r15\nmov rsi, r12\nlea rdi, [r13+rax+0]\ncall ___stpcpy_chk\nmov edx, 2\nlea rsi, asc_2028; \")[\"\nsub r14, rax\nmov rdi, rax\nadd r14, r15\nmov rcx, r14\ncall ___memcpy_chk\nmov ecx, dword ptr [rbp+var_58]\nmov rdi, rax\ncmp dword ptr [rbp+var_70], ecx\njle short loc_17E7\nlea rcx, [r14-1]\nadd rdi, 1\nmov edx, 3\nlea rsi, asc_2025; \", \"\ncall ___memcpy_chk\nloc_17E7:\nadd dword ptr [rbp+var_58], 1\nmov esi, [rbp+var_60]\nadd rbx, 14h\nmov eax, dword ptr [rbp+var_58]\ncmp eax, esi\njnz loc_16E8\nloc_17FD:\nmov rdx, r15\nlea rsi, asc_2021; \"]\"\nmov rdi, r13\ncall ___strcat_chk\nmov rax, [rbp+var_38]\nsub rax, fs:28h\njnz loc_18C0\nlea rsp, [rbp-28h]\nmov rax, r13\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1838:\nmov rcx, r13\nmov edx, 3\nlea rsi, asc_2025; \", \"\nmov rdi, rax\nsub rcx, rax\nadd rcx, r15\ncall ___memcpy_chk\njmp loc_1750\nloc_1860:\nmovsxd rax, ebx\nmovdqu xmm0, xmmword ptr [rsi]\nadd rsi, 10h\nadd ebx, 1\nlea rax, [rax+rax*4]\nlea rax, [r8+rax*4]\nmov dword ptr [rax+10h], 1\nmovups xmmword ptr [rax], xmm0\ncmp rsi, r10\njnz loc_1540\njmp loc_15A9\nloc_188E:\nor [rsp+rdx+1070h+var_1078], 0\njmp loc_1522\nloc_1899:\nmov edi, 3; size\ncall _malloc\nmov r13, rax\ntest rax, rax\njz short loc_18C5\nmov eax, 5Bh ; '['\nmov r15d, 3\nmov [r13+0], ax\njmp loc_17FD\nloc_18C0:\ncall ___stack_chk_fail\nloc_18C5:\nmov rcx, cs:stderr; s\nmov edx, 19h; n\nmov esi, 1; size\nlea rdi, aMemoryAllocati; \"Memory allocation failed\\n\"\ncall _fwrite\nmov edi, 1; status\ncall _exit", + "ida_strip_pseudo": "char *__fastcall sub_14B0(const __m128i *a1, int a2)\n{\n __int64 v2; // rdx\n _DWORD *v3; // rcx\n __int16 v4; // dx\n signed __int64 v5; // rdx\n void *v6; // rsp\n __int64 v7; // r10\n const __m128i *v8; // rsi\n int v9; // ebx\n const __m128i *v10; // r10\n _DWORD *v11; // rdx\n int v12; // ecx\n int v13; // r9d\n __int64 v14; // rax\n unsigned int *v15; // r15\n int v16; // r9d\n __int64 v17; // rax\n int v18; // r14d\n int v19; // r10d\n unsigned int *v20; // r13\n unsigned int *v21; // rbx\n __int64 v22; // r8\n __int64 v23; // r8\n int v24; // eax\n int v25; // eax\n int v26; // ebx\n size_t v27; // r15\n char *v28; // rax\n char *v29; // r13\n _DWORD *v30; // r8\n _DWORD *v31; // rbx\n int v32; // eax\n __int64 v33; // r14\n size_t v34; // rax\n __int64 v35; // rax\n size_t v36; // rax\n __int64 v37; // rax\n char *v38; // r14\n __int64 v39; // rax\n __int64 v41; // rax\n __m128i v42; // xmm0\n __m128i *v43; // rax\n _DWORD v45[1022]; // [rsp+8h] [rbp-1070h] BYREF\n _DWORD *v46; // [rsp+1008h] [rbp-70h] BYREF\n __int64 v47; // [rsp+1010h] [rbp-68h]\n int v48; // [rsp+1018h] [rbp-60h]\n int v49; // [rsp+101Ch] [rbp-5Ch]\n _DWORD *v50; // [rsp+1020h] [rbp-58h]\n char s[12]; // [rsp+1034h] [rbp-44h] BYREF\n unsigned __int64 v52; // [rsp+1040h] [rbp-38h]\n\n v52 = __readfsqword(0x28u);\n v2 = 20LL * a2 + 15;\n v3 = (_DWORD *)((char *)&v46 - (v2 & 0xFFFFFFFFFFFFF000LL));\n v4 = v2 & 0xFFF0;\n if ( &v46 != (_DWORD **)v3 )\n {\n while ( v45 != v3 )\n ;\n }\n v5 = v4 & 0xFFF;\n v6 = alloca(v5);\n if ( v5 )\n *(_QWORD *)((char *)&v45[-2] + v5) = *(_QWORD *)((char *)&v45[-2] + v5);\n if ( a2 <= 0 )\n goto LABEL_35;\n v7 = a2;\n v8 = a1;\n v9 = 0;\n v10 = &a1[v7];\n do\n {\n if ( v9 > 0 )\n {\n while ( 1 )\n {\n v11 = v45;\n v12 = 0;\n v13 = v8->m128i_i32[3];\n while ( v11[3] != v13 )\n {\nLABEL_9:\n ++v12;\n v11 += 5;\n if ( v12 == v9 )\n goto LABEL_33;\n }\n if ( v13 > 0 )\n break;\nLABEL_15:\n ++v8;\n ++v45[5 * v12 + 4];\n if ( v8 == v10 )\n goto LABEL_16;\n }\n v14 = 0LL;\n while ( v11[v14] == v8->m128i_i32[v14] )\n {\n if ( ++v14 == v8->m128i_i32[3] )\n goto LABEL_15;\n }\n goto LABEL_9;\n }\nLABEL_33:\n v41 = v9;\n v42 = _mm_loadu_si128(v8++);\n ++v9;\n v43 = (__m128i *)&v45[5 * v41];\n v43[1].m128i_i32[0] = 1;\n *v43 = v42;\n }\n while ( v8 != v10 );\nLABEL_16:\n if ( v9 <= 0 )\n {\nLABEL_35:\n v29 = (char *)malloc(3uLL);\n if ( v29 )\n {\n v27 = 3LL;\n *(_WORD *)v29 = 91;\n goto LABEL_32;\n }\nLABEL_37:\n fwrite(\"Memory allocation failed\\n\", 1uLL, 0x19uLL, stderr);\n exit(1);\n }\n v48 = v9;\n v15 = v45;\n v16 = 2;\n v50 = 0LL;\n v47 = 5LL * v9;\n v46 = v45;\n do\n {\n v17 = (int)v15[3];\n v18 = v16 + 2;\n v19 = v16 + 2;\n if ( (int)v17 > 0 )\n {\n v20 = &v46[(_QWORD)v50 + v17];\n v21 = v15;\n do\n {\n v22 = *v21++;\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, v22);\n v19 = v18 + strlen(s) + 2;\n v18 = v19;\n }\n while ( v20 != v21 );\n }\n v23 = v15[4];\n v49 = v19;\n v15 += 5;\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, v23);\n v24 = strlen(s);\n v50 = (_DWORD *)((char *)v50 + 5);\n v25 = v49 + v24;\n v16 = v25 + 2;\n }\n while ( v50 != (_DWORD *)v47 );\n v26 = v48;\n v27 = v25 + 1;\n v50 = v46;\n v28 = (char *)malloc(v27);\n v29 = v28;\n if ( !v28 )\n goto LABEL_37;\n __memcpy_chk(v28, L\"[\", 2LL, v27);\n v30 = v50;\n v48 = v26;\n LODWORD(v46) = v26 - 1;\n LODWORD(v50) = 0;\n v31 = v30;\n do\n {\n __strcat_chk(v29, \"(\", v27);\n v32 = v31[3];\n if ( v32 > 0 )\n {\n v47 = (int)v31[3];\n v33 = 0LL;\n v49 = v32 - 1;\n do\n {\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, (unsigned int)v31[v33]);\n v34 = strlen(v29);\n v35 = __stpcpy_chk(&v29[v34], s, v27);\n if ( v49 > (int)v33 )\n __memcpy_chk(v35, \", \", 3LL, &v29[v27 - v35]);\n ++v33;\n }\n while ( v47 != v33 );\n }\n __strcat_chk(v29, \", \", v27);\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, (unsigned int)v31[4]);\n v36 = strlen(v29);\n v37 = __stpcpy_chk(&v29[v36], s, v27);\n v38 = &v29[v27 - v37];\n v39 = __memcpy_chk(v37, L\")[\", 2LL, v38);\n if ( (int)v46 > (int)v50 )\n __memcpy_chk(v39 + 1, \", \", 3LL, v38 - 1);\n LODWORD(v50) = (_DWORD)v50 + 1;\n v31 += 5;\n }\n while ( (_DWORD)v50 != v48 );\nLABEL_32:\n __strcat_chk(v29, \"]\", v27);\n return v29;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_14B0(const __m128i *a1, int a2) {\n long long v2;\n uint32_t *v3;\n short v4;\n signed long long v5;\n void *v6;\n long long v7;\n const __m128i *v8;\n int v9;\n const __m128i *v10;\n uint32_t *v11;\n int v12;\n int v13;\n long long v14;\n unsigned int *v15;\n int v16;\n long long v17;\n int v18;\n int v19;\n unsigned int *v20;\n unsigned int *v21;\n long long v22;\n long long v23;\n int v24;\n int v25;\n int v26;\n unsigned int v27;\n char *v28;\n char *v29;\n uint32_t *v30;\n uint32_t *v31;\n int v32;\n long long v33;\n unsigned int v34;\n long long v35;\n unsigned int v36;\n long long v37;\n char *v38;\n long long v39;\n long long v41;\n __m128i v42;\n __m128i *v43;\n uint32_t v45[1022];\n uint32_t *v46;\n long long v47;\n int v48;\n int v49;\n uint32_t *v50;\n char s[12];\n unsigned long long v52;\n v52 = __readfsqword(40u);\n v2 = 20LL * a2 + 15;\n v3 = (uint32_t *)((char *)&v46 - (v2 & 18446744073709547520LL));\n v4 = v2 & 65520;\n if (&v46 != (uint32_t **)v3) {\n while (v45 != v3)\n ;\n }\n v5 = v4 & 4095;\n v6 = alloca(v5);\n if (v5)\n *(uint64_t *)((char *)&v45[-2] + v5) = *(uint64_t *)((char *)&v45[-2] + v5);\n if (a2 <= 0) goto LABEL_35;\n v7 = a2;\n v8 = a1;\n v9 = 0;\n v10 = &a1[v7];\n do {\n if (v9 > 0) {\n while (1) {\n v11 = v45;\n v12 = 0;\n v13 = v8->m128i_i32[3];\n while (v11[3] != v13) {\n LABEL_9:\n ++v12;\n v11 += 5;\n if (v12 == v9) goto LABEL_33;\n }\n if (v13 > 0) break;\n LABEL_15:\n ++v8;\n ++v45[5 * v12 + 4];\n if (v8 == v10) goto LABEL_16;\n }\n v14 = 0LL;\n while (v11[v14] == v8->m128i_i32[v14]) {\n if (++v14 == v8->m128i_i32[3]) goto LABEL_15;\n }\n goto LABEL_9;\n }\n LABEL_33:\n v41 = v9;\n v42 = _mm_loadu_si128(v8++);\n ++v9;\n v43 = (__m128i *)&v45[5 * v41];\n v43[1].m128i_i32[0] = 1;\n *v43 = v42;\n } while (v8 != v10);\nLABEL_16:\n if (v9 <= 0) {\n LABEL_35:\n v29 = (char *)malloc(3uLL);\n if (v29) {\n v27 = 3LL;\n *(unsigned short *)v29 = 91;\n goto LABEL_32;\n }\n LABEL_37:\n fwrite(\"Memory allocation failed\\n\", 1uLL, 25uLL, stderr);\n exit(1);\n }\n v48 = v9;\n v15 = v45;\n v16 = 2;\n v50 = 0LL;\n v47 = 5LL * v9;\n v46 = v45;\n do {\n v17 = (int)v15[3];\n v18 = v16 + 2;\n v19 = v16 + 2;\n if ((int)v17 > 0) {\n v20 = &v46[(uint64_t)v50 + v17];\n v21 = v15;\n do {\n v22 = *v21++;\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, v22);\n v19 = v18 + strlen(s) + 2;\n v18 = v19;\n } while (v20 != v21);\n }\n v23 = v15[4];\n v49 = v19;\n v15 += 5;\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, v23);\n v24 = strlen(s);\n v50 = (uint32_t *)((char *)v50 + 5);\n v25 = v49 + v24;\n v16 = v25 + 2;\n } while (v50 != (uint32_t *)v47);\n v26 = v48;\n v27 = v25 + 1;\n v50 = v46;\n v28 = (char *)malloc(v27);\n v29 = v28;\n if (!v28) goto LABEL_37;\n __memcpy_chk(v28, L\"[\", 2LL, v27);\n v30 = v50;\n v48 = v26;\n LODWORD(v46) = v26 - 1;\n LODWORD(v50) = 0;\n v31 = v30;\n do {\n __strcat_chk(v29, \"(\", v27);\n v32 = v31[3];\n if (v32 > 0) {\n v47 = (int)v31[3];\n v33 = 0LL;\n v49 = v32 - 1;\n do {\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, (unsigned int)v31[v33]);\n v34 = strlen(v29);\n v35 = __stpcpy_chk(&v29[v34], s, v27);\n if (v49 > (int)v33) __memcpy_chk(v35, \", \", 3LL, &v29[v27 - v35]);\n ++v33;\n } while (v47 != v33);\n }\n __strcat_chk(v29, \", \", v27);\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, (unsigned int)v31[4]);\n v36 = strlen(v29);\n v37 = __stpcpy_chk(&v29[v36], s, v27);\n v38 = &v29[v27 - v37];\n v39 = __memcpy_chk(v37, L\")[\", 2LL, v38);\n if ((int)v46 > (int)v50) __memcpy_chk(v39 + 1, \", \", 3LL, v38 - 1);\n LODWORD(v50) = (uint32_t)v50 + 1;\n v31 += 5;\n } while ((uint32_t)v50 != v48);\nLABEL_32:\n __strcat_chk(v29, \"]\", v27);\n return v29;\n}", + "ida_pseudo_norm": "char *func0(const __m128i *a1, int a2) {\n long long v2;\n uint32_t *v3;\n short v4;\n signed long long v5;\n void *v6;\n long long v7;\n const __m128i *v8;\n int v9;\n const __m128i *v10;\n uint32_t *v11;\n int v12;\n int v13;\n long long v14;\n unsigned int *v15;\n int v16;\n long long v17;\n int v18;\n int v19;\n unsigned int *v20;\n unsigned int *v21;\n long long v22;\n long long v23;\n int v24;\n int v25;\n int v26;\n unsigned int v27;\n char *v28;\n char *v29;\n uint32_t *v30;\n uint32_t *v31;\n int v32;\n long long v33;\n unsigned int v34;\n long long v35;\n unsigned int v36;\n long long v37;\n char *v38;\n long long v39;\n long long v41;\n __m128i v42;\n __m128i *v43;\n uint32_t v45[1022];\n uint32_t *v46;\n long long v47;\n int v48;\n int v49;\n uint32_t *v50;\n char s[12];\n unsigned long long v52;\n v52 = __readfsqword(40u);\n v2 = 20LL * a2 + 15;\n v3 = (uint32_t *)((char *)&v46 - (v2 & 18446744073709547520LL));\n v4 = v2 & 65520;\n if (&v46 != (uint32_t **)v3) {\n while (v45 != v3)\n ;\n }\n v5 = v4 & 4095;\n v6 = alloca(v5);\n if (v5)\n *(uint64_t *)((char *)&v45[-2] + v5) = *(uint64_t *)((char *)&v45[-2] + v5);\n if (a2 <= 0) goto LABEL_35;\n v7 = a2;\n v8 = a1;\n v9 = 0;\n v10 = &a1[v7];\n do {\n if (v9 > 0) {\n while (1) {\n v11 = v45;\n v12 = 0;\n v13 = v8->m128i_i32[3];\n while (v11[3] != v13) {\n LABEL_9:\n ++v12;\n v11 += 5;\n if (v12 == v9) goto LABEL_33;\n }\n if (v13 > 0) break;\n LABEL_15:\n ++v8;\n ++v45[5 * v12 + 4];\n if (v8 == v10) goto LABEL_16;\n }\n v14 = 0LL;\n while (v11[v14] == v8->m128i_i32[v14]) {\n if (++v14 == v8->m128i_i32[3]) goto LABEL_15;\n }\n goto LABEL_9;\n }\n LABEL_33:\n v41 = v9;\n v42 = _mm_loadu_si128(v8++);\n ++v9;\n v43 = (__m128i *)&v45[5 * v41];\n v43[1].m128i_i32[0] = 1;\n *v43 = v42;\n } while (v8 != v10);\nLABEL_16:\n if (v9 <= 0) {\n LABEL_35:\n v29 = (char *)malloc(3uLL);\n if (v29) {\n v27 = 3LL;\n *(unsigned short *)v29 = 91;\n goto LABEL_32;\n }\n LABEL_37:\n fwrite(\"Memory allocation failed\\n\", 1uLL, 25uLL, _bss_start);\n exit(1);\n }\n v48 = v9;\n v15 = v45;\n v16 = 2;\n v50 = 0LL;\n v47 = 5LL * v9;\n v46 = v45;\n do {\n v17 = (int)v15[3];\n v18 = v16 + 2;\n v19 = v16 + 2;\n if ((int)v17 > 0) {\n v20 = &v46[(uint64_t)v50 + v17];\n v21 = v15;\n do {\n v22 = *v21++;\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, v22);\n v19 = v18 + strlen(s) + 2;\n v18 = v19;\n } while (v20 != v21);\n }\n v23 = v15[4];\n v49 = v19;\n v15 += 5;\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, v23);\n v24 = strlen(s);\n v50 = (uint32_t *)((char *)v50 + 5);\n v25 = v49 + v24;\n v16 = v25 + 2;\n } while (v50 != (uint32_t *)v47);\n v26 = v48;\n v27 = v25 + 1;\n v50 = v46;\n v28 = (char *)malloc(v27);\n v29 = v28;\n if (!v28) goto LABEL_37;\n __memcpy_chk(v28, L\"[\", 2LL, v27);\n v30 = v50;\n v48 = v26;\n LODWORD(v46) = v26 - 1;\n LODWORD(v50) = 0;\n v31 = v30;\n do {\n __strcat_chk(v29, \"(\", v27);\n v32 = v31[3];\n if (v32 > 0) {\n v47 = (int)v31[3];\n v33 = 0LL;\n v49 = v32 - 1;\n do {\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, (unsigned int)v31[v33]);\n v34 = strlen(v29);\n v35 = __stpcpy_chk(&v29[v34], s, v27);\n if (v49 > (int)v33) __memcpy_chk(v35, \", \", 3LL, &v29[v27 - v35]);\n ++v33;\n } while (v47 != v33);\n }\n __strcat_chk(v29, \", \", v27);\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, (unsigned int)v31[4]);\n v36 = strlen(v29);\n v37 = __stpcpy_chk(&v29[v36], s, v27);\n v38 = &v29[v27 - v37];\n v39 = __memcpy_chk(v37, L\")[\", 2LL, v38);\n if ((int)v46 > (int)v50) __memcpy_chk(v39 + 1, \", \", 3LL, v38 - 1);\n LODWORD(v50) = (uint32_t)v50 + 1;\n v31 += 5;\n } while ((uint32_t)v50 != v48);\nLABEL_32:\n __strcat_chk(v29, \"]\", v27);\n return v29;\n}" + }, + { + "index": 114, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int elements[3];\n\n int length;\n\n} Tuple;\n\n\n\ntypedef struct {\n\n Tuple tuple;\n\n int count;\n\n} TupleCount;\n\n\n\n", + "func": "char* func0(Tuple input[], int input_size) {\n TupleCount counts[input_size];\n int unique = 0;\n for (int i = 0; i < input_size; i++) {\n int found = 0;\n for (int j = 0; j < unique; j++) {\n if (counts[j].tuple.length == input[i].length) {\n int match = 1;\n for (int k = 0; k < input[i].length; k++) {\n if (counts[j].tuple.elements[k] != input[i].elements[k]) {\n match = 0;\n break;\n }\n }\n if (match) {\n counts[j].count++;\n found = 1;\n break;\n }\n }\n }\n if (!found) {\n counts[unique].tuple = input[i];\n counts[unique].count = 1;\n unique++;\n }\n }\n int size = 2;\n for (int i = 0; i < unique; i++) {\n size += 2;\n for (int j = 0; j < counts[i].tuple.length; j++) {\n char num[12];\n sprintf(num, \"%d\", counts[i].tuple.elements[j]);\n size += strlen(num) + 2;\n }\n char cnt[12];\n sprintf(cnt, \"%d\", counts[i].count);\n size += strlen(cnt) + 2;\n }\n if (unique > 0) size -= 2;\n size += 1;\n char* result = malloc(size);\n if (result == NULL) {\n fprintf(stderr, \"Memory allocation failed\\n\");\n exit(1);\n }\n strcpy(result, \"[\");\n for (int i = 0; i < unique; i++) {\n strcat(result, \"(\");\n for (int j = 0; j < counts[i].tuple.length; j++) {\n char num[12];\n sprintf(num, \"%d\", counts[i].tuple.elements[j]);\n strcat(result, num);\n if (j < counts[i].tuple.length - 1) strcat(result, \", \");\n }\n strcat(result, \", \");\n char cnt[12];\n sprintf(cnt, \"%d\", counts[i].count);\n strcat(result, cnt);\n strcat(result, \")\");\n if (i < unique - 1) strcat(result, \", \");\n }\n strcat(result, \"]\");\n return result;\n}", + "test": "int main() {\n\n // First test case\n\n Tuple test1[] = {\n\n { .elements = {6, 5, 8}, .length = 3 },\n\n { .elements = {2, 7, 0}, .length = 2 },\n\n { .elements = {6, 5, 8}, .length = 3 },\n\n { .elements = {6, 5, 8}, .length = 3 },\n\n { .elements = {9, 0, 0}, .length = 1 },\n\n { .elements = {2, 7, 0}, .length = 2 }\n\n };\n\n char* res1 = func0(test1, 6);\n\n assert(strcmp(res1, \"[(6, 5, 8, 3), (2, 7, 2), (9, 1)]\") == 0);\n\n free(res1);\n\n\n\n // Second test case\n\n Tuple test2[] = {\n\n { .elements = {4, 2, 4}, .length = 3 },\n\n { .elements = {7, 1, 0}, .length = 2 },\n\n { .elements = {4, 8, 0}, .length = 2 },\n\n { .elements = {4, 2, 4}, .length = 3 },\n\n { .elements = {9, 2, 0}, .length = 2 },\n\n { .elements = {7, 1, 0}, .length = 2 }\n\n };\n\n char* res2 = func0(test2, 6);\n\n assert(strcmp(res2, \"[(4, 2, 4, 2), (7, 1, 2), (4, 8, 1), (9, 2, 1)]\") == 0);\n\n free(res2);\n\n\n\n // Third test case\n\n Tuple test3[] = {\n\n { .elements = {11, 13, 10}, .length = 3 },\n\n { .elements = {17, 21, 0}, .length = 2 },\n\n { .elements = {4, 2, 3}, .length = 3 },\n\n { .elements = {17, 21, 0}, .length = 2 },\n\n { .elements = {9, 2, 0}, .length = 2 },\n\n { .elements = {4, 2, 3}, .length = 3 }\n\n };\n\n char* res3 = func0(test3, 6);\n\n assert(strcmp(res3, \"[(11, 13, 10, 1), (17, 21, 2), (4, 2, 3, 2), (9, 2, 1)]\") == 0);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmovslq %esi,%rdx\nmov %rdx,%rax\nlea (%rdx,%rdx,4),%rdx\nlea 0xf(,%rdx,4),%rdx\nmov %rsp,%rbp\npush %r15\nmov %rdx,%rcx\nand $0xfffffffffffff000,%rdx\npush %r14\nand $0xfffffffffffffff0,%rcx\npush %r13\npush %r12\npush %rbx\nsub $0x48,%rsp\nmov %fs:0x28,%rbx\nmov %rbx,-0x38(%rbp)\nxor %ebx,%ebx\nmov %rsp,%rsi\nsub %rdx,%rsi\nmov %rsi,%rdx\ncmp %rdx,%rsp\nje 14d7 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rdx,%rsp\njne 14c2 \nand $0xfff,%ecx\nsub %rcx,%rsp\ntest %rcx,%rcx\njne 19bf \nmov %rsp,%r8\ntest %eax,%eax\njle 1986 \nsub $0x1,%eax\nmov %rdi,%rsi\nxor %r9d,%r9d\nshl $0x4,%rax\nlea 0x10(%rdi,%rax,1),%rdi\nnopw %cs:0x0(%rax,%rax,1)\ntest %r9d,%r9d\nje 1940 \nmov 0xc(%rsi),%ecx\nmov %r8,%rax\nxor %edx,%edx\njmp 1538 \nnopl 0x0(%rax,%rax,1)\nadd $0x1,%edx\nadd $0x14,%rax\ncmp %r9d,%edx\nje 1940 \ncmp %ecx,0xc(%rax)\njne 1528 \ntest %ecx,%ecx\njle 1561 \nmov (%rsi),%ebx\ncmp %ebx,(%rax)\njne 1528 \ncmp $0x1,%ecx\nje 1561 \nmov 0x4(%rax),%ebx\ncmp %ebx,0x4(%rsi)\njne 1528 \ncmp $0x2,%ecx\nje 1561 \nmov 0x8(%rsi),%ebx\ncmp %ebx,0x8(%rax)\njne 1528 \nmovslq %edx,%rdx\nlea (%rdx,%rdx,4),%rax\naddl $0x1,0x10(%r8,%rax,4)\nxchg %ax,%ax\nadd $0x10,%rsi\ncmp %rdi,%rsi\njne 1510 \nlea -0x1(%r9),%eax\nlea -0x44(%rbp),%r13\nmov %r9d,-0x70(%rbp)\nmov $0x2,%r15d\nmov %eax,-0x6c(%rbp)\nlea (%rax,%rax,4),%rax\nlea 0x14(%r8,%rax,4),%rax\nmov %r8,-0x58(%rbp)\nmov %rax,-0x68(%rbp)\nmov %r13,%rax\nmov %r8,%r13\nmov %rax,%r12\nnopl 0x0(%rax,%rax,1)\nmov 0xc(%r13),%ebx\nadd $0x2,%r15d\nmov %r15d,%r9d\ntest %ebx,%ebx\njle 1634 \nxor %r14d,%r14d\nnopw 0x0(%rax,%rax,1)\nmov 0x0(%r13,%r14,4),%r8d\nmov $0xc,%edx\nmov %r12,%rdi\nxor %eax,%eax\nlea 0xa26(%rip),%rcx\nmov $0x1,%esi\ncallq 1150 <__sprintf_chk@plt>\nmov %r12,%rdx\nmov (%rdx),%ecx\nadd $0x4,%rdx\nlea -0x1010101(%rcx),%eax\nnot %ecx\nand %ecx,%eax\nand $0x80808080,%eax\nje 15eb \nmov %eax,%ecx\nshr $0x10,%ecx\ntest $0x8080,%eax\ncmove %ecx,%eax\nlea 0x2(%rdx),%rcx\ncmove %rcx,%rdx\nmov %eax,%esi\nadd %al,%sil\nsbb $0x3,%rdx\nadd $0x1,%r14\nsub %r12,%rdx\nlea 0x2(%r15,%rdx,1),%r9d\nmov %r9d,%r15d\ncmp %r14d,%ebx\njg 15c8 \nmov 0x10(%r13),%r8d\nmov $0xc,%edx\nmov $0x1,%esi\nxor %eax,%eax\nlea 0x9b9(%rip),%rcx\nmov %r12,%rdi\nmov %r9d,-0x5c(%rbp)\ncallq 1150 <__sprintf_chk@plt>\nmov -0x5c(%rbp),%r9d\nmov %r12,%rdx\nmov (%rdx),%ecx\nadd $0x4,%rdx\nlea -0x1010101(%rcx),%eax\nnot %ecx\nand %ecx,%eax\nand $0x80808080,%eax\nje 165e \nmov %eax,%ecx\nshr $0x10,%ecx\ntest $0x8080,%eax\ncmove %ecx,%eax\nlea 0x2(%rdx),%rcx\ncmove %rcx,%rdx\nmov %eax,%esi\nadd %al,%sil\nsbb $0x3,%rdx\nadd $0x14,%r13\nsub %r12,%rdx\nadd %edx,%r9d\nlea 0x2(%r9),%r15d\ncmp -0x68(%rbp),%r13\njne 15b0 \nmov %r9d,%r14d\nmov %r12,%r13\nadd $0x1,%r14d\nmovslq %r14d,%rdi\ncallq 1110 \nmov %rax,%r12\ntest %rax,%rax\nje 1998 \nmov $0x5b,%edx\nmovl $0x0,-0x68(%rbp)\nlea 0x928(%rip),%r15\nmov %dx,(%r12)\nnopl 0x0(%rax)\nmov %r12,%rdx\nmov (%rdx),%ecx\nadd $0x4,%rdx\nlea -0x1010101(%rcx),%eax\nnot %ecx\nand %ecx,%eax\nand $0x80808080,%eax\nje 16eb \nmov %eax,%ecx\nmov $0x28,%r10d\nshr $0x10,%ecx\ntest $0x8080,%eax\ncmove %ecx,%eax\nlea 0x2(%rdx),%rcx\ncmove %rcx,%rdx\nmov %eax,%esi\nadd %al,%sil\nmov -0x58(%rbp),%rax\nsbb $0x3,%rdx\nmov 0xc(%rax),%eax\nmov %r10w,(%rdx)\nmov %eax,-0x60(%rbp)\ntest %eax,%eax\njle 1803 \nsub $0x1,%eax\nmov %eax,-0x5c(%rbp)\ntest %eax,%eax\njle 1968 \nmov -0x58(%rbp),%r14\nxor %ebx,%ebx\nmov (%r14),%r8d\nmov %r13,%rdi\nmov %r15,%rcx\nmov $0xc,%edx\nmov $0x1,%esi\nxor %eax,%eax\ncallq 1150 <__sprintf_chk@plt>\nmov %r12,%rdi\nmov (%rdi),%edx\nadd $0x4,%rdi\nlea -0x1010101(%rdx),%eax\nnot %edx\nand %edx,%eax\nand $0x80808080,%eax\nje 176d \nmov %eax,%edx\nshr $0x10,%edx\ntest $0x8080,%eax\ncmove %edx,%eax\nlea 0x2(%rdi),%rdx\ncmove %rdx,%rdi\nmov %eax,%esi\nadd %al,%sil\nmov %r13,%rsi\nsbb $0x3,%rdi\nadd $0x1,%ebx\nadd $0x4,%r14\ncallq 10e0 \nmov $0x202c,%edi\nmov %di,(%rax)\nmovb $0x0,0x2(%rax)\ncmp -0x5c(%rbp),%ebx\njl 1750 \ncmp -0x60(%rbp),%ebx\njge 1803 \nmovslq %ebx,%rbx\nmov %rbx,%r14\nmov -0x60(%rbp),%ebx\nmov -0x58(%rbp),%rax\nmov %r15,%rcx\nmov $0xc,%edx\nmov %r13,%rdi\nmov $0x1,%esi\nmov (%rax,%r14,4),%r8d\nxor %eax,%eax\nadd $0x1,%r14\ncallq 1150 <__sprintf_chk@plt>\nmov %r13,%rsi\nmov %r12,%rdi\ncallq 1120 \ncmp %r14d,%ebx\njg 17d0 \nmov %r12,%rdx\nmov (%rdx),%ecx\nadd $0x4,%rdx\nlea -0x1010101(%rcx),%eax\nnot %ecx\nand %ecx,%eax\nand $0x80808080,%eax\nje 1806 \nmov %eax,%ecx\nmov $0x202c,%r9d\nmov %r13,%rdi\nshr $0x10,%ecx\ntest $0x8080,%eax\ncmove %ecx,%eax\nlea 0x2(%rdx),%rcx\ncmove %rcx,%rdx\nmov %r15,%rcx\nmov %eax,%esi\nadd %al,%sil\nmov -0x58(%rbp),%rax\nmov $0x1,%esi\nsbb $0x3,%rdx\nmov %r9w,(%rdx)\nmov 0x10(%rax),%r8d\nxor %eax,%eax\nmovb $0x0,0x2(%rdx)\nmov $0xc,%edx\ncallq 1150 <__sprintf_chk@plt>\nmov %r12,%rdi\nmov (%rdi),%edx\nadd $0x4,%rdi\nlea -0x1010101(%rdx),%eax\nnot %edx\nand %edx,%eax\nand $0x80808080,%eax\nje 186b \nmov %eax,%edx\nshr $0x10,%edx\ntest $0x8080,%eax\ncmove %edx,%eax\nlea 0x2(%rdi),%rdx\ncmove %rdx,%rdi\nmov %eax,%esi\nadd %al,%sil\nmov %r13,%rsi\nsbb $0x3,%rdi\ncallq 10e0 \nmov $0x29,%r8d\nmov -0x6c(%rbp),%esi\nmov %rax,%rdx\nmov %r8w,(%rax)\nsub %r12,%rdx\ncmp %esi,-0x68(%rbp)\njl 1970 \naddl $0x1,-0x68(%rbp)\nmov -0x68(%rbp),%eax\naddq $0x14,-0x58(%rbp)\ncmp %eax,-0x70(%rbp)\njne 16e8 \nmov %r12,%rdx\nmov (%rdx),%ecx\nadd $0x4,%rdx\nlea -0x1010101(%rcx),%eax\nnot %ecx\nand %ecx,%eax\nand $0x80808080,%eax\nje 18dc \nmov %eax,%ecx\nshr $0x10,%ecx\ntest $0x8080,%eax\ncmove %ecx,%eax\nlea 0x2(%rdx),%rcx\ncmove %rcx,%rdx\nmov $0x5d,%ecx\nmov %eax,%ebx\nadd %al,%bl\nsbb $0x3,%rdx\nmov %cx,(%rdx)\nmov -0x38(%rbp),%rax\nxor %fs:0x28,%rax\njne 19d9 \nlea -0x28(%rbp),%rsp\nmov %r12,%rax\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\nnopl (%rax)\nmovslq %r9d,%rax\nmovdqu (%rsi),%xmm0\nadd $0x1,%r9d\nlea (%rax,%rax,4),%rax\nlea (%r8,%rax,4),%rax\nmovl $0x1,0x10(%rax)\nmovups %xmm0,(%rax)\njmpq 1570 \nnopw 0x0(%rax,%rax,1)\nxor %ebx,%ebx\njmpq 17c7 \nlea 0x1(%r12,%rdx,1),%rax\nmov $0x202c,%esi\nmov %si,(%rax)\nmovb $0x0,0x2(%rax)\njmpq 18c4 \nmov $0x3,%edi\ncallq 1110 \nmov %rax,%r12\ntest %rax,%rax\njne 19ca \nmov 0x2681(%rip),%rcx\nmov $0x19,%edx\nmov $0x1,%esi\nlea 0x657(%rip),%rdi\ncallq 1140 \nmov $0x1,%edi\ncallq 1130 \norq $0x0,-0x8(%rsp,%rcx,1)\njmpq 14e9 \nmov $0x5b,%eax\nmov %ax,(%r12)\njmpq 18d9 \ncallq 10f0 <__stack_chk_fail@plt>\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 58h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nmovsxd rax, esi\nmov r8, rsp\nlea rdx, [rax+rax*4]\nlea rdx, ds:0Fh[rdx*4]\nmov rcx, rdx\nand rdx, 0FFFFFFFFFFFFF000h\nsub r8, rdx\nand rcx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, r8\njz short loc_1511\nloc_14FC:\nsub rsp, 1000h\nor [rsp+1080h+var_88], 0\ncmp rsp, r8\njnz short loc_14FC\nloc_1511:\nand ecx, 0FFFh\nsub rsp, rcx\ntest rcx, rcx\njnz loc_18EA\nloc_1523:\nmov r8, rsp\ntest esi, esi\njle loc_18F5\nshl rax, 4\nmov rsi, rdi\nxor ebx, ebx\nlea rdi, [rdi+rax]\nnop dword ptr [rax+rax+00h]\nloc_1540:\ntest ebx, ebx\njle loc_1830\nloc_1548:\nmov ecx, [rsi+0Ch]\nmov rax, r8\nxor edx, edx\njmp short loc_1567\nloc_1558:\nadd edx, 1\nadd rax, 14h\ncmp ebx, edx\njz loc_1830\nloc_1567:\ncmp [rax+0Ch], ecx\njnz short loc_1558\ntest ecx, ecx\njle short loc_1596\nmov r11d, [rsi]\ncmp [rax], r11d\njnz short loc_1558\ncmp ecx, 1\njz short loc_1596\nmov r9d, [rax+4]\ncmp [rsi+4], r9d\njnz short loc_1558\ncmp ecx, 2\njz short loc_1596\nmov r11d, [rsi+8]\ncmp [rax+8], r11d\njnz short loc_1558\nloc_1596:\nmovsxd rdx, edx\nadd rsi, 10h\nlea rax, [rdx+rdx*4]\nadd dword ptr [r8+rax*4+10h], 1\ncmp rsi, rdi\njnz short loc_1548\nloc_15AC:\ntest ebx, ebx\njle loc_18F5\nmovsxd rax, ebx\nmov [rbp+var_60], ebx\nmov r13, r8\nmov r9d, 2\nlea rax, [rax+rax*4]\nmov [rbp+var_58], 0\nlea r15, [rbp+s]\nmov [rbp+var_68], rax\nmov [rbp+var_70], r8\nnop dword ptr [rax+rax+00h]\nloc_15E0:\nmovsxd rax, dword ptr [r13+0Ch]\nlea r14d, [r9+2]\nmov r10d, r14d\ntest eax, eax\njle short loc_1638\nmov rsi, [rbp+var_58]\nmov rbx, r13\nadd rax, rsi\nmov rsi, [rbp+var_70]\nlea r12, [rsi+rax*4]\nloc_1601:\nmov r8d, [rbx]\nlea rcx, unk_2004\nmov rdi, r15\nxor eax, eax\nmov edx, 0Ch\nmov esi, 2\nadd rbx, 4\ncall ___sprintf_chk\nmov rdi, r15; s\ncall _strlen\nlea r10d, [r14+rax+2]\nmov r14d, r10d\ncmp rbx, r12\njnz short loc_1601\nloc_1638:\nmov r8d, [r13+10h]\nmov esi, 2\nmov edx, 0Ch\nxor eax, eax\nlea rcx, unk_2004\nmov rdi, r15\nmov [rbp+var_5C], r10d\nadd r13, 14h\ncall ___sprintf_chk\nmov rdi, r15; s\ncall _strlen\nmov r10d, [rbp+var_5C]\nadd [rbp+var_58], 5\nmov rsi, [rbp+var_68]\nadd r10d, eax\nmov rax, [rbp+var_58]\nlea r9d, [r10+2]\ncmp rax, rsi\njnz loc_15E0\nmov r12d, r10d\nmov r8, [rbp+var_70]\nmov ebx, [rbp+var_60]\nadd r12d, 1\nmovsxd r12, r12d\nmov [rbp+var_58], r8\nmov rdi, r12; size\ncall _malloc\nmov r8, [rbp+var_58]\ntest rax, rax\nmov r13, rax\njz loc_1921\nmov rcx, r12\nmov edx, 2\nmov rdi, rax\nmov [rbp+var_58], r8\nlea rsi, asc_2028+2; \"[\"\ncall ___memcpy_chk\nlea eax, [rbx-1]\nmov r8, [rbp+var_58]\nmov dword ptr [rbp+var_70], ebx\nmov dword ptr [rbp+var_68], eax\nmov dword ptr [rbp+var_58], 0\nmov rbx, r8\nnop word ptr [rax+rax+00000000h]\nloc_16F0:\nmov rdx, r12\nlea rsi, asc_2023; \"(\"\nmov rdi, r13\ncall ___strcat_chk\nmov eax, [rbx+0Ch]\ntest eax, eax\njle short loc_1751\nlea edx, [rax-1]\nxor r14d, r14d\ntest edx, edx\njg loc_1860\nloc_1717:\nmov [rbp+var_5C], eax\nloc_171A:\nmov r8d, [rbx+r14*4]\nlea rcx, unk_2004\nmov rdi, r15\nxor eax, eax\nmov edx, 0Ch\nmov esi, 2\nadd r14, 1\ncall ___sprintf_chk\nmov rdx, r12\nmov rsi, r15\nmov rdi, r13\ncall ___strcat_chk\ncmp [rbp+var_5C], r14d\njg short loc_171A\nloc_1751:\nmov rdx, r12\nlea rsi, asc_2025; \", \"\nmov rdi, r13\nmov r14, r13\ncall ___strcat_chk\nmov r8d, [rbx+10h]\nmov edx, 0Ch\nxor eax, eax\nlea rcx, unk_2004\nmov esi, 2\nmov rdi, r15\ncall ___sprintf_chk\nmov rdi, r13; s\ncall _strlen\nmov rdx, r12\nmov rsi, r15\nlea rdi, [r13+rax+0]\ncall ___stpcpy_chk\nlea rsi, asc_2028; \")[\"\nmov edx, 2\nsub r14, rax\nmov rdi, rax\nadd r14, r12\nmov rcx, r14\ncall ___memcpy_chk\nmov esi, dword ptr [rbp+var_58]\nmov rdi, rax\ncmp dword ptr [rbp+var_68], esi\njle short loc_17DE\nlea rcx, [r14-1]\nadd rdi, 1\nmov edx, 3\nlea rsi, asc_2025; \", \"\ncall ___memcpy_chk\nloc_17DE:\nadd dword ptr [rbp+var_58], 1\nadd rbx, 14h\nmov eax, dword ptr [rbp+var_58]\ncmp dword ptr [rbp+var_70], eax\njnz loc_16F0\nloc_17F2:\nmov rdx, r12\nlea rsi, asc_2021; \"]\"\nmov rdi, r13\ncall ___strcat_chk\nmov rax, [rbp+var_38]\nsub rax, fs:28h\njnz loc_191C\nlea rsp, [rbp-28h]\nmov rax, r13\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1830:\nmovsxd rax, ebx\nmovdqu xmm0, xmmword ptr [rsi]\nadd rsi, 10h\nadd ebx, 1\nlea rax, [rax+rax*4]\nlea rax, [r8+rax*4]\nmov dword ptr [rax+10h], 1\nmovups xmmword ptr [rax], xmm0\ncmp rsi, rdi\njnz loc_1540\njmp loc_15AC\nloc_1860:\nmov [rbp+var_5C], edx\nmov r9, rbx\nmov [rbp+var_60], eax\nmov [rbp+var_78], rbx\nmov ebx, r14d\nmov r14, r9\nloc_1873:\nmov r8d, [r14]\nlea rcx, unk_2004\nmov rdi, r15\nxor eax, eax\nmov edx, 0Ch\nmov esi, 2\nadd ebx, 1\nadd r14, 4\ncall ___sprintf_chk\nmov rdi, r13; s\ncall _strlen\nmov rdx, r12\nmov rsi, r15\nlea rdi, [r13+rax+0]\ncall ___stpcpy_chk\nmov rcx, r13\nmov edx, 3\nlea rsi, asc_2025; \", \"\nsub rcx, rax\nmov rdi, rax\nadd rcx, r12\ncall ___memcpy_chk\ncmp [rbp+var_5C], ebx\njg short loc_1873\nmov eax, [rbp+var_60]\nmovsxd r14, ebx\nmov rbx, [rbp+var_78]\ncmp r14d, eax\njl loc_1717\njmp loc_1751\nloc_18EA:\nor [rsp+rcx+1080h+var_1088], 0\njmp loc_1523\nloc_18F5:\nmov edi, 3; size\ncall _malloc\nmov r13, rax\ntest rax, rax\njz short loc_1921\nmov eax, 5Bh ; '['\nmov r12d, 3\nmov [r13+0], ax\njmp loc_17F2\nloc_191C:\ncall ___stack_chk_fail\nloc_1921:\nmov rcx, cs:__bss_start; s\nmov edx, 19h; n\nmov esi, 1; size\nlea rdi, aMemoryAllocati; \"Memory allocation failed\\n\"\ncall _fwrite\nmov edi, 1; status\ncall _exit", + "ida_pseudo": "char *__fastcall func0(const __m128i *a1, int a2)\n{\n __int64 v2; // rcx\n __int64 *v3; // r8\n __int16 v4; // cx\n signed __int64 v5; // rcx\n void *v6; // rsp\n __int64 v7; // rax\n const __m128i *v8; // rsi\n int v9; // ebx\n const __m128i *v10; // rdi\n int v11; // ecx\n _DWORD *v12; // rax\n int v13; // edx\n unsigned int *v14; // r13\n int v15; // r9d\n __int64 v16; // rax\n int v17; // r14d\n int v18; // r10d\n unsigned int *v19; // rbx\n unsigned int *v20; // r12\n __int64 v21; // r8\n __int64 v22; // r8\n int v23; // eax\n int v24; // ebx\n size_t v25; // r12\n char *v26; // rax\n char *v27; // r13\n unsigned int *v28; // r8\n unsigned int *v29; // rbx\n int v30; // eax\n __int64 v31; // r14\n __int64 v32; // r8\n size_t v33; // rax\n __int64 v34; // rax\n char *v35; // r14\n __int64 v36; // rax\n __int64 v38; // rax\n __m128i v39; // xmm0\n __m128i *v40; // rax\n unsigned int *v41; // r9\n int v42; // ebx\n unsigned int *v43; // r14\n __int64 v44; // r8\n size_t v45; // rax\n __int64 v46; // rax\n _DWORD v48[1022]; // [rsp+8h] [rbp-1080h] BYREF\n __int64 v49; // [rsp+1008h] [rbp-80h] BYREF\n unsigned int *v50; // [rsp+1010h] [rbp-78h]\n unsigned int *v51; // [rsp+1018h] [rbp-70h]\n __int64 v52; // [rsp+1020h] [rbp-68h]\n int v53; // [rsp+1028h] [rbp-60h]\n int v54; // [rsp+102Ch] [rbp-5Ch]\n unsigned int *v55; // [rsp+1030h] [rbp-58h]\n char s[12]; // [rsp+1044h] [rbp-44h] BYREF\n unsigned __int64 v57; // [rsp+1050h] [rbp-38h]\n\n v57 = __readfsqword(0x28u);\n v2 = 20LL * a2 + 15;\n v3 = (__int64 *)((char *)&v49 - (v2 & 0xFFFFFFFFFFFFF000LL));\n v4 = v2 & 0xFFF0;\n if ( &v49 != v3 )\n {\n while ( v48 != (_DWORD *)v3 )\n ;\n }\n v5 = v4 & 0xFFF;\n v6 = alloca(v5);\n if ( v5 )\n *(_QWORD *)((char *)&v48[-2] + v5) = *(_QWORD *)((char *)&v48[-2] + v5);\n if ( a2 <= 0 )\n goto LABEL_40;\n v7 = a2;\n v8 = a1;\n v9 = 0;\n v10 = &a1[v7];\n while ( v9 <= 0 )\n {\nLABEL_34:\n v38 = v9;\n v39 = _mm_loadu_si128(v8++);\n ++v9;\n v40 = (__m128i *)&v48[5 * v38];\n v40[1].m128i_i32[0] = 1;\n *v40 = v39;\n if ( v8 == v10 )\n goto LABEL_18;\n }\n do\n {\n v11 = v8->m128i_i32[3];\n v12 = v48;\n v13 = 0;\n while ( v12[3] != v11\n || v11 > 0\n && (*v12 != v8->m128i_i32[0]\n || v11 != 1 && (v8->m128i_i32[1] != v12[1] || v11 != 2 && v12[2] != v8->m128i_i32[2])) )\n {\n ++v13;\n v12 += 5;\n if ( v9 == v13 )\n goto LABEL_34;\n }\n ++v8;\n ++v48[5 * v13 + 4];\n }\n while ( v8 != v10 );\nLABEL_18:\n if ( v9 <= 0 )\n {\nLABEL_40:\n v27 = (char *)malloc(3uLL);\n if ( v27 )\n {\n v25 = 3LL;\n *(_WORD *)v27 = 91;\n goto LABEL_33;\n }\nLABEL_42:\n fwrite(\"Memory allocation failed\\n\", 1uLL, 0x19uLL, _bss_start);\n exit(1);\n }\n v53 = v9;\n v14 = v48;\n v15 = 2;\n v55 = 0LL;\n v52 = 5LL * v9;\n v51 = v48;\n do\n {\n v16 = (int)v14[3];\n v17 = v15 + 2;\n v18 = v15 + 2;\n if ( (int)v16 > 0 )\n {\n v19 = v14;\n v20 = &v51[(_QWORD)v55 + v16];\n do\n {\n v21 = *v19++;\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, v21);\n v18 = v17 + strlen(s) + 2;\n v17 = v18;\n }\n while ( v19 != v20 );\n }\n v22 = v14[4];\n v54 = v18;\n v14 += 5;\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, v22);\n v23 = strlen(s);\n v55 = (unsigned int *)((char *)v55 + 5);\n v15 = v23 + v54 + 2;\n }\n while ( v55 != (unsigned int *)v52 );\n v24 = v53;\n v25 = v23 + v54 + 1;\n v55 = v51;\n v26 = (char *)malloc(v25);\n v27 = v26;\n if ( !v26 )\n goto LABEL_42;\n __memcpy_chk(v26, L\"[\", 2LL, v25);\n v28 = v55;\n LODWORD(v51) = v24;\n LODWORD(v52) = v24 - 1;\n LODWORD(v55) = 0;\n v29 = v28;\n do\n {\n __strcat_chk(v27, \"(\", v25);\n v30 = v29[3];\n if ( v30 > 0 )\n {\n v31 = 0LL;\n if ( v30 - 1 <= 0 )\n goto LABEL_28;\n v54 = v30 - 1;\n v41 = v29;\n v53 = v30;\n v50 = v29;\n v42 = 0;\n v43 = v41;\n do\n {\n v44 = *v43;\n ++v42;\n ++v43;\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, v44);\n v45 = strlen(v27);\n v46 = __stpcpy_chk(&v27[v45], s, v25);\n __memcpy_chk(v46, \", \", 3LL, &v27[v25 - v46]);\n }\n while ( v54 > v42 );\n v30 = v53;\n v31 = v42;\n v29 = v50;\n if ( (int)v31 < v53 )\n {\nLABEL_28:\n v54 = v30;\n do\n {\n v32 = v29[v31++];\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, v32);\n __strcat_chk(v27, s, v25);\n }\n while ( v54 > (int)v31 );\n }\n }\n __strcat_chk(v27, \", \", v25);\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, v29[4]);\n v33 = strlen(v27);\n v34 = __stpcpy_chk(&v27[v33], s, v25);\n v35 = &v27[v25 - v34];\n v36 = __memcpy_chk(v34, L\")[\", 2LL, v35);\n if ( (int)v52 > (int)v55 )\n __memcpy_chk(v36 + 1, \", \", 3LL, v35 - 1);\n LODWORD(v55) = (_DWORD)v55 + 1;\n v29 += 5;\n }\n while ( (_DWORD)v51 != (_DWORD)v55 );\nLABEL_33:\n __strcat_chk(v27, \"]\", v25);\n return v27;\n}", + "ida_strip_asm": "sub_14B0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 58h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nmovsxd rax, esi\nmov r8, rsp\nlea rdx, [rax+rax*4]\nlea rdx, ds:0Fh[rdx*4]\nmov rcx, rdx\nand rdx, 0FFFFFFFFFFFFF000h\nsub r8, rdx\nand rcx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, r8\njz short loc_1511\nloc_14FC:\nsub rsp, 1000h\nor [rsp+1080h+var_88], 0\ncmp rsp, r8\njnz short loc_14FC\nloc_1511:\nand ecx, 0FFFh\nsub rsp, rcx\ntest rcx, rcx\njnz loc_18EA\nloc_1523:\nmov r8, rsp\ntest esi, esi\njle loc_18F5\nshl rax, 4\nmov rsi, rdi\nxor ebx, ebx\nlea rdi, [rdi+rax]\nnop dword ptr [rax+rax+00h]\nloc_1540:\ntest ebx, ebx\njle loc_1830\nloc_1548:\nmov ecx, [rsi+0Ch]\nmov rax, r8\nxor edx, edx\njmp short loc_1567\nloc_1558:\nadd edx, 1\nadd rax, 14h\ncmp ebx, edx\njz loc_1830\nloc_1567:\ncmp [rax+0Ch], ecx\njnz short loc_1558\ntest ecx, ecx\njle short loc_1596\nmov r11d, [rsi]\ncmp [rax], r11d\njnz short loc_1558\ncmp ecx, 1\njz short loc_1596\nmov r9d, [rax+4]\ncmp [rsi+4], r9d\njnz short loc_1558\ncmp ecx, 2\njz short loc_1596\nmov r11d, [rsi+8]\ncmp [rax+8], r11d\njnz short loc_1558\nloc_1596:\nmovsxd rdx, edx\nadd rsi, 10h\nlea rax, [rdx+rdx*4]\nadd dword ptr [r8+rax*4+10h], 1\ncmp rsi, rdi\njnz short loc_1548\nloc_15AC:\ntest ebx, ebx\njle loc_18F5\nmovsxd rax, ebx\nmov [rbp+var_60], ebx\nmov r13, r8\nmov r9d, 2\nlea rax, [rax+rax*4]\nmov [rbp+var_58], 0\nlea r15, [rbp+s]\nmov [rbp+var_68], rax\nmov [rbp+var_70], r8\nnop dword ptr [rax+rax+00h]\nloc_15E0:\nmovsxd rax, dword ptr [r13+0Ch]\nlea r14d, [r9+2]\nmov r10d, r14d\ntest eax, eax\njle short loc_1638\nmov rsi, [rbp+var_58]\nmov rbx, r13\nadd rax, rsi\nmov rsi, [rbp+var_70]\nlea r12, [rsi+rax*4]\nloc_1601:\nmov r8d, [rbx]\nlea rcx, unk_2004\nmov rdi, r15\nxor eax, eax\nmov edx, 0Ch\nmov esi, 2\nadd rbx, 4\ncall ___sprintf_chk\nmov rdi, r15; s\ncall _strlen\nlea r10d, [r14+rax+2]\nmov r14d, r10d\ncmp rbx, r12\njnz short loc_1601\nloc_1638:\nmov r8d, [r13+10h]\nmov esi, 2\nmov edx, 0Ch\nxor eax, eax\nlea rcx, unk_2004\nmov rdi, r15\nmov [rbp+var_5C], r10d\nadd r13, 14h\ncall ___sprintf_chk\nmov rdi, r15; s\ncall _strlen\nmov r10d, [rbp+var_5C]\nadd [rbp+var_58], 5\nmov rsi, [rbp+var_68]\nadd r10d, eax\nmov rax, [rbp+var_58]\nlea r9d, [r10+2]\ncmp rax, rsi\njnz loc_15E0\nmov r12d, r10d\nmov r8, [rbp+var_70]\nmov ebx, [rbp+var_60]\nadd r12d, 1\nmovsxd r12, r12d\nmov [rbp+var_58], r8\nmov rdi, r12; size\ncall _malloc\nmov r8, [rbp+var_58]\ntest rax, rax\nmov r13, rax\njz loc_1921\nmov rcx, r12\nmov edx, 2\nmov rdi, rax\nmov [rbp+var_58], r8\nlea rsi, asc_2028+2; \"[\"\ncall ___memcpy_chk\nlea eax, [rbx-1]\nmov r8, [rbp+var_58]\nmov dword ptr [rbp+var_70], ebx\nmov dword ptr [rbp+var_68], eax\nmov dword ptr [rbp+var_58], 0\nmov rbx, r8\nnop word ptr [rax+rax+00000000h]\nloc_16F0:\nmov rdx, r12\nlea rsi, asc_2023; \"(\"\nmov rdi, r13\ncall ___strcat_chk\nmov eax, [rbx+0Ch]\ntest eax, eax\njle short loc_1751\nlea edx, [rax-1]\nxor r14d, r14d\ntest edx, edx\njg loc_1860\nloc_1717:\nmov [rbp+var_5C], eax\nloc_171A:\nmov r8d, [rbx+r14*4]\nlea rcx, unk_2004\nmov rdi, r15\nxor eax, eax\nmov edx, 0Ch\nmov esi, 2\nadd r14, 1\ncall ___sprintf_chk\nmov rdx, r12\nmov rsi, r15\nmov rdi, r13\ncall ___strcat_chk\ncmp [rbp+var_5C], r14d\njg short loc_171A\nloc_1751:\nmov rdx, r12\nlea rsi, asc_2025; \", \"\nmov rdi, r13\nmov r14, r13\ncall ___strcat_chk\nmov r8d, [rbx+10h]\nmov edx, 0Ch\nxor eax, eax\nlea rcx, unk_2004\nmov esi, 2\nmov rdi, r15\ncall ___sprintf_chk\nmov rdi, r13; s\ncall _strlen\nmov rdx, r12\nmov rsi, r15\nlea rdi, [r13+rax+0]\ncall ___stpcpy_chk\nlea rsi, asc_2028; \")[\"\nmov edx, 2\nsub r14, rax\nmov rdi, rax\nadd r14, r12\nmov rcx, r14\ncall ___memcpy_chk\nmov esi, dword ptr [rbp+var_58]\nmov rdi, rax\ncmp dword ptr [rbp+var_68], esi\njle short loc_17DE\nlea rcx, [r14-1]\nadd rdi, 1\nmov edx, 3\nlea rsi, asc_2025; \", \"\ncall ___memcpy_chk\nloc_17DE:\nadd dword ptr [rbp+var_58], 1\nadd rbx, 14h\nmov eax, dword ptr [rbp+var_58]\ncmp dword ptr [rbp+var_70], eax\njnz loc_16F0\nloc_17F2:\nmov rdx, r12\nlea rsi, asc_2021; \"]\"\nmov rdi, r13\ncall ___strcat_chk\nmov rax, [rbp+var_38]\nsub rax, fs:28h\njnz loc_191C\nlea rsp, [rbp-28h]\nmov rax, r13\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1830:\nmovsxd rax, ebx\nmovdqu xmm0, xmmword ptr [rsi]\nadd rsi, 10h\nadd ebx, 1\nlea rax, [rax+rax*4]\nlea rax, [r8+rax*4]\nmov dword ptr [rax+10h], 1\nmovups xmmword ptr [rax], xmm0\ncmp rsi, rdi\njnz loc_1540\njmp loc_15AC\nloc_1860:\nmov [rbp+var_5C], edx\nmov r9, rbx\nmov [rbp+var_60], eax\nmov [rbp+var_78], rbx\nmov ebx, r14d\nmov r14, r9\nloc_1873:\nmov r8d, [r14]\nlea rcx, unk_2004\nmov rdi, r15\nxor eax, eax\nmov edx, 0Ch\nmov esi, 2\nadd ebx, 1\nadd r14, 4\ncall ___sprintf_chk\nmov rdi, r13; s\ncall _strlen\nmov rdx, r12\nmov rsi, r15\nlea rdi, [r13+rax+0]\ncall ___stpcpy_chk\nmov rcx, r13\nmov edx, 3\nlea rsi, asc_2025; \", \"\nsub rcx, rax\nmov rdi, rax\nadd rcx, r12\ncall ___memcpy_chk\ncmp [rbp+var_5C], ebx\njg short loc_1873\nmov eax, [rbp+var_60]\nmovsxd r14, ebx\nmov rbx, [rbp+var_78]\ncmp r14d, eax\njl loc_1717\njmp loc_1751\nloc_18EA:\nor [rsp+rcx+1080h+var_1088], 0\njmp loc_1523\nloc_18F5:\nmov edi, 3; size\ncall _malloc\nmov r13, rax\ntest rax, rax\njz short loc_1921\nmov eax, 5Bh ; '['\nmov r12d, 3\nmov [r13+0], ax\njmp loc_17F2\nloc_191C:\ncall ___stack_chk_fail\nloc_1921:\nmov rcx, cs:stderr; s\nmov edx, 19h; n\nmov esi, 1; size\nlea rdi, aMemoryAllocati; \"Memory allocation failed\\n\"\ncall _fwrite\nmov edi, 1; status\ncall _exit", + "ida_strip_pseudo": "char *__fastcall sub_14B0(const __m128i *a1, int a2)\n{\n __int64 v2; // rcx\n __int64 *v3; // r8\n __int16 v4; // cx\n signed __int64 v5; // rcx\n void *v6; // rsp\n __int64 v7; // rax\n const __m128i *v8; // rsi\n int v9; // ebx\n const __m128i *v10; // rdi\n int v11; // ecx\n _DWORD *v12; // rax\n int v13; // edx\n unsigned int *v14; // r13\n int v15; // r9d\n __int64 v16; // rax\n int v17; // r14d\n int v18; // r10d\n unsigned int *v19; // rbx\n unsigned int *v20; // r12\n __int64 v21; // r8\n __int64 v22; // r8\n int v23; // eax\n int v24; // ebx\n size_t v25; // r12\n char *v26; // rax\n char *v27; // r13\n unsigned int *v28; // r8\n unsigned int *v29; // rbx\n int v30; // eax\n __int64 v31; // r14\n __int64 v32; // r8\n size_t v33; // rax\n __int64 v34; // rax\n char *v35; // r14\n __int64 v36; // rax\n __int64 v38; // rax\n __m128i v39; // xmm0\n __m128i *v40; // rax\n unsigned int *v41; // r9\n int v42; // ebx\n unsigned int *v43; // r14\n __int64 v44; // r8\n size_t v45; // rax\n __int64 v46; // rax\n _DWORD v48[1022]; // [rsp+8h] [rbp-1080h] BYREF\n __int64 v49; // [rsp+1008h] [rbp-80h] BYREF\n unsigned int *v50; // [rsp+1010h] [rbp-78h]\n unsigned int *v51; // [rsp+1018h] [rbp-70h]\n __int64 v52; // [rsp+1020h] [rbp-68h]\n int v53; // [rsp+1028h] [rbp-60h]\n int v54; // [rsp+102Ch] [rbp-5Ch]\n unsigned int *v55; // [rsp+1030h] [rbp-58h]\n char s[12]; // [rsp+1044h] [rbp-44h] BYREF\n unsigned __int64 v57; // [rsp+1050h] [rbp-38h]\n\n v57 = __readfsqword(0x28u);\n v2 = 20LL * a2 + 15;\n v3 = (__int64 *)((char *)&v49 - (v2 & 0xFFFFFFFFFFFFF000LL));\n v4 = v2 & 0xFFF0;\n if ( &v49 != v3 )\n {\n while ( v48 != (_DWORD *)v3 )\n ;\n }\n v5 = v4 & 0xFFF;\n v6 = alloca(v5);\n if ( v5 )\n *(_QWORD *)((char *)&v48[-2] + v5) = *(_QWORD *)((char *)&v48[-2] + v5);\n if ( a2 <= 0 )\n goto LABEL_40;\n v7 = a2;\n v8 = a1;\n v9 = 0;\n v10 = &a1[v7];\n while ( v9 <= 0 )\n {\nLABEL_34:\n v38 = v9;\n v39 = _mm_loadu_si128(v8++);\n ++v9;\n v40 = (__m128i *)&v48[5 * v38];\n v40[1].m128i_i32[0] = 1;\n *v40 = v39;\n if ( v8 == v10 )\n goto LABEL_18;\n }\n do\n {\n v11 = v8->m128i_i32[3];\n v12 = v48;\n v13 = 0;\n while ( v12[3] != v11\n || v11 > 0\n && (*v12 != v8->m128i_i32[0]\n || v11 != 1 && (v8->m128i_i32[1] != v12[1] || v11 != 2 && v12[2] != v8->m128i_i32[2])) )\n {\n ++v13;\n v12 += 5;\n if ( v9 == v13 )\n goto LABEL_34;\n }\n ++v8;\n ++v48[5 * v13 + 4];\n }\n while ( v8 != v10 );\nLABEL_18:\n if ( v9 <= 0 )\n {\nLABEL_40:\n v27 = (char *)malloc(3uLL);\n if ( v27 )\n {\n v25 = 3LL;\n *(_WORD *)v27 = 91;\n goto LABEL_33;\n }\nLABEL_42:\n fwrite(\"Memory allocation failed\\n\", 1uLL, 0x19uLL, stderr);\n exit(1);\n }\n v53 = v9;\n v14 = v48;\n v15 = 2;\n v55 = 0LL;\n v52 = 5LL * v9;\n v51 = v48;\n do\n {\n v16 = (int)v14[3];\n v17 = v15 + 2;\n v18 = v15 + 2;\n if ( (int)v16 > 0 )\n {\n v19 = v14;\n v20 = &v51[(_QWORD)v55 + v16];\n do\n {\n v21 = *v19++;\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, v21);\n v18 = v17 + strlen(s) + 2;\n v17 = v18;\n }\n while ( v19 != v20 );\n }\n v22 = v14[4];\n v54 = v18;\n v14 += 5;\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, v22);\n v23 = strlen(s);\n v55 = (unsigned int *)((char *)v55 + 5);\n v15 = v23 + v54 + 2;\n }\n while ( v55 != (unsigned int *)v52 );\n v24 = v53;\n v25 = v23 + v54 + 1;\n v55 = v51;\n v26 = (char *)malloc(v25);\n v27 = v26;\n if ( !v26 )\n goto LABEL_42;\n __memcpy_chk(v26, L\"[\", 2LL, v25);\n v28 = v55;\n LODWORD(v51) = v24;\n LODWORD(v52) = v24 - 1;\n LODWORD(v55) = 0;\n v29 = v28;\n do\n {\n __strcat_chk(v27, \"(\", v25);\n v30 = v29[3];\n if ( v30 > 0 )\n {\n v31 = 0LL;\n if ( v30 - 1 <= 0 )\n goto LABEL_28;\n v54 = v30 - 1;\n v41 = v29;\n v53 = v30;\n v50 = v29;\n v42 = 0;\n v43 = v41;\n do\n {\n v44 = *v43;\n ++v42;\n ++v43;\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, v44);\n v45 = strlen(v27);\n v46 = __stpcpy_chk(&v27[v45], s, v25);\n __memcpy_chk(v46, \", \", 3LL, &v27[v25 - v46]);\n }\n while ( v54 > v42 );\n v30 = v53;\n v31 = v42;\n v29 = v50;\n if ( (int)v31 < v53 )\n {\nLABEL_28:\n v54 = v30;\n do\n {\n v32 = v29[v31++];\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, v32);\n __strcat_chk(v27, s, v25);\n }\n while ( v54 > (int)v31 );\n }\n }\n __strcat_chk(v27, \", \", v25);\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, v29[4]);\n v33 = strlen(v27);\n v34 = __stpcpy_chk(&v27[v33], s, v25);\n v35 = &v27[v25 - v34];\n v36 = __memcpy_chk(v34, L\")[\", 2LL, v35);\n if ( (int)v52 > (int)v55 )\n __memcpy_chk(v36 + 1, \", \", 3LL, v35 - 1);\n LODWORD(v55) = (_DWORD)v55 + 1;\n v29 += 5;\n }\n while ( (_DWORD)v51 != (_DWORD)v55 );\nLABEL_33:\n __strcat_chk(v27, \"]\", v25);\n return v27;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_14B0(const __m128i *a1, int a2) {\n long long v2;\n long long *v3;\n short v4;\n signed long long v5;\n void *v6;\n long long v7;\n const __m128i *v8;\n int v9;\n const __m128i *v10;\n int v11;\n uint32_t *v12;\n int v13;\n unsigned int *v14;\n int v15;\n long long v16;\n int v17;\n int v18;\n unsigned int *v19;\n unsigned int *v20;\n long long v21;\n long long v22;\n int v23;\n int v24;\n unsigned int v25;\n char *v26;\n char *v27;\n unsigned int *v28;\n unsigned int *v29;\n int v30;\n long long v31;\n long long v32;\n unsigned int v33;\n long long v34;\n char *v35;\n long long v36;\n long long v38;\n __m128i v39;\n __m128i *v40;\n unsigned int *v41;\n int v42;\n unsigned int *v43;\n long long v44;\n unsigned int v45;\n long long v46;\n uint32_t v48[1022];\n long long v49;\n unsigned int *v50;\n unsigned int *v51;\n long long v52;\n int v53;\n int v54;\n unsigned int *v55;\n char s[12];\n unsigned long long v57;\n v57 = __readfsqword(40u);\n v2 = 20LL * a2 + 15;\n v3 = (long long *)((char *)&v49 - (v2 & 18446744073709547520LL));\n v4 = v2 & 65520;\n if (&v49 != v3) {\n while (v48 != (uint32_t *)v3)\n ;\n }\n v5 = v4 & 4095;\n v6 = alloca(v5);\n if (v5)\n *(uint64_t *)((char *)&v48[-2] + v5) = *(uint64_t *)((char *)&v48[-2] + v5);\n if (a2 <= 0) goto LABEL_40;\n v7 = a2;\n v8 = a1;\n v9 = 0;\n v10 = &a1[v7];\n while (v9 <= 0) {\n LABEL_34:\n v38 = v9;\n v39 = _mm_loadu_si128(v8++);\n ++v9;\n v40 = (__m128i *)&v48[5 * v38];\n v40[1].m128i_i32[0] = 1;\n *v40 = v39;\n if (v8 == v10) goto LABEL_18;\n }\n do {\n v11 = v8->m128i_i32[3];\n v12 = v48;\n v13 = 0;\n while (v12[3] != v11 ||\n v11 > 0 && (*v12 != v8->m128i_i32[0] ||\n v11 != 1 && (v8->m128i_i32[1] != v12[1] ||\n v11 != 2 && v12[2] != v8->m128i_i32[2]))) {\n ++v13;\n v12 += 5;\n if (v9 == v13) goto LABEL_34;\n }\n ++v8;\n ++v48[5 * v13 + 4];\n } while (v8 != v10);\nLABEL_18:\n if (v9 <= 0) {\n LABEL_40:\n v27 = (char *)malloc(3uLL);\n if (v27) {\n v25 = 3LL;\n *(unsigned short *)v27 = 91;\n goto LABEL_33;\n }\n LABEL_42:\n fwrite(\"Memory allocation failed\\n\", 1uLL, 25uLL, stderr);\n exit(1);\n }\n v53 = v9;\n v14 = v48;\n v15 = 2;\n v55 = 0LL;\n v52 = 5LL * v9;\n v51 = v48;\n do {\n v16 = (int)v14[3];\n v17 = v15 + 2;\n v18 = v15 + 2;\n if ((int)v16 > 0) {\n v19 = v14;\n v20 = &v51[(uint64_t)v55 + v16];\n do {\n v21 = *v19++;\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, v21);\n v18 = v17 + strlen(s) + 2;\n v17 = v18;\n } while (v19 != v20);\n }\n v22 = v14[4];\n v54 = v18;\n v14 += 5;\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, v22);\n v23 = strlen(s);\n v55 = (unsigned int *)((char *)v55 + 5);\n v15 = v23 + v54 + 2;\n } while (v55 != (unsigned int *)v52);\n v24 = v53;\n v25 = v23 + v54 + 1;\n v55 = v51;\n v26 = (char *)malloc(v25);\n v27 = v26;\n if (!v26) goto LABEL_42;\n __memcpy_chk(v26, L\"[\", 2LL, v25);\n v28 = v55;\n LODWORD(v51) = v24;\n LODWORD(v52) = v24 - 1;\n LODWORD(v55) = 0;\n v29 = v28;\n do {\n __strcat_chk(v27, \"(\", v25);\n v30 = v29[3];\n if (v30 > 0) {\n v31 = 0LL;\n if (v30 - 1 <= 0) goto LABEL_28;\n v54 = v30 - 1;\n v41 = v29;\n v53 = v30;\n v50 = v29;\n v42 = 0;\n v43 = v41;\n do {\n v44 = *v43;\n ++v42;\n ++v43;\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, v44);\n v45 = strlen(v27);\n v46 = __stpcpy_chk(&v27[v45], s, v25);\n __memcpy_chk(v46, \", \", 3LL, &v27[v25 - v46]);\n } while (v54 > v42);\n v30 = v53;\n v31 = v42;\n v29 = v50;\n if ((int)v31 < v53) {\n LABEL_28:\n v54 = v30;\n do {\n v32 = v29[v31++];\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, v32);\n __strcat_chk(v27, s, v25);\n } while (v54 > (int)v31);\n }\n }\n __strcat_chk(v27, \", \", v25);\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, v29[4]);\n v33 = strlen(v27);\n v34 = __stpcpy_chk(&v27[v33], s, v25);\n v35 = &v27[v25 - v34];\n v36 = __memcpy_chk(v34, L\")[\", 2LL, v35);\n if ((int)v52 > (int)v55) __memcpy_chk(v36 + 1, \", \", 3LL, v35 - 1);\n LODWORD(v55) = (uint32_t)v55 + 1;\n v29 += 5;\n } while ((uint32_t)v51 != (uint32_t)v55);\nLABEL_33:\n __strcat_chk(v27, \"]\", v25);\n return v27;\n}", + "ida_pseudo_norm": "char *func0(const __m128i *a1, int a2) {\n long long v2;\n long long *v3;\n short v4;\n signed long long v5;\n void *v6;\n long long v7;\n const __m128i *v8;\n int v9;\n const __m128i *v10;\n int v11;\n uint32_t *v12;\n int v13;\n unsigned int *v14;\n int v15;\n long long v16;\n int v17;\n int v18;\n unsigned int *v19;\n unsigned int *v20;\n long long v21;\n long long v22;\n int v23;\n int v24;\n unsigned int v25;\n char *v26;\n char *v27;\n unsigned int *v28;\n unsigned int *v29;\n int v30;\n long long v31;\n long long v32;\n unsigned int v33;\n long long v34;\n char *v35;\n long long v36;\n long long v38;\n __m128i v39;\n __m128i *v40;\n unsigned int *v41;\n int v42;\n unsigned int *v43;\n long long v44;\n unsigned int v45;\n long long v46;\n uint32_t v48[1022];\n long long v49;\n unsigned int *v50;\n unsigned int *v51;\n long long v52;\n int v53;\n int v54;\n unsigned int *v55;\n char s[12];\n unsigned long long v57;\n v57 = __readfsqword(40u);\n v2 = 20LL * a2 + 15;\n v3 = (long long *)((char *)&v49 - (v2 & 18446744073709547520LL));\n v4 = v2 & 65520;\n if (&v49 != v3) {\n while (v48 != (uint32_t *)v3)\n ;\n }\n v5 = v4 & 4095;\n v6 = alloca(v5);\n if (v5)\n *(uint64_t *)((char *)&v48[-2] + v5) = *(uint64_t *)((char *)&v48[-2] + v5);\n if (a2 <= 0) goto LABEL_40;\n v7 = a2;\n v8 = a1;\n v9 = 0;\n v10 = &a1[v7];\n while (v9 <= 0) {\n LABEL_34:\n v38 = v9;\n v39 = _mm_loadu_si128(v8++);\n ++v9;\n v40 = (__m128i *)&v48[5 * v38];\n v40[1].m128i_i32[0] = 1;\n *v40 = v39;\n if (v8 == v10) goto LABEL_18;\n }\n do {\n v11 = v8->m128i_i32[3];\n v12 = v48;\n v13 = 0;\n while (v12[3] != v11 ||\n v11 > 0 && (*v12 != v8->m128i_i32[0] ||\n v11 != 1 && (v8->m128i_i32[1] != v12[1] ||\n v11 != 2 && v12[2] != v8->m128i_i32[2]))) {\n ++v13;\n v12 += 5;\n if (v9 == v13) goto LABEL_34;\n }\n ++v8;\n ++v48[5 * v13 + 4];\n } while (v8 != v10);\nLABEL_18:\n if (v9 <= 0) {\n LABEL_40:\n v27 = (char *)malloc(3uLL);\n if (v27) {\n v25 = 3LL;\n *(unsigned short *)v27 = 91;\n goto LABEL_33;\n }\n LABEL_42:\n fwrite(\"Memory allocation failed\\n\", 1uLL, 25uLL, _bss_start);\n exit(1);\n }\n v53 = v9;\n v14 = v48;\n v15 = 2;\n v55 = 0LL;\n v52 = 5LL * v9;\n v51 = v48;\n do {\n v16 = (int)v14[3];\n v17 = v15 + 2;\n v18 = v15 + 2;\n if ((int)v16 > 0) {\n v19 = v14;\n v20 = &v51[(uint64_t)v55 + v16];\n do {\n v21 = *v19++;\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, v21);\n v18 = v17 + strlen(s) + 2;\n v17 = v18;\n } while (v19 != v20);\n }\n v22 = v14[4];\n v54 = v18;\n v14 += 5;\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, v22);\n v23 = strlen(s);\n v55 = (unsigned int *)((char *)v55 + 5);\n v15 = v23 + v54 + 2;\n } while (v55 != (unsigned int *)v52);\n v24 = v53;\n v25 = v23 + v54 + 1;\n v55 = v51;\n v26 = (char *)malloc(v25);\n v27 = v26;\n if (!v26) goto LABEL_42;\n __memcpy_chk(v26, L\"[\", 2LL, v25);\n v28 = v55;\n LODWORD(v51) = v24;\n LODWORD(v52) = v24 - 1;\n LODWORD(v55) = 0;\n v29 = v28;\n do {\n __strcat_chk(v27, \"(\", v25);\n v30 = v29[3];\n if (v30 > 0) {\n v31 = 0LL;\n if (v30 - 1 <= 0) goto LABEL_28;\n v54 = v30 - 1;\n v41 = v29;\n v53 = v30;\n v50 = v29;\n v42 = 0;\n v43 = v41;\n do {\n v44 = *v43;\n ++v42;\n ++v43;\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, v44);\n v45 = strlen(v27);\n v46 = __stpcpy_chk(&v27[v45], s, v25);\n __memcpy_chk(v46, \", \", 3LL, &v27[v25 - v46]);\n } while (v54 > v42);\n v30 = v53;\n v31 = v42;\n v29 = v50;\n if ((int)v31 < v53) {\n LABEL_28:\n v54 = v30;\n do {\n v32 = v29[v31++];\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, v32);\n __strcat_chk(v27, s, v25);\n } while (v54 > (int)v31);\n }\n }\n __strcat_chk(v27, \", \", v25);\n __sprintf_chk(s, 2LL, 12LL, &unk_2004, v29[4]);\n v33 = strlen(v27);\n v34 = __stpcpy_chk(&v27[v33], s, v25);\n v35 = &v27[v25 - v34];\n v36 = __memcpy_chk(v34, L\")[\", 2LL, v35);\n if ((int)v52 > (int)v55) __memcpy_chk(v36 + 1, \", \", 3LL, v35 - 1);\n LODWORD(v55) = (uint32_t)v55 + 1;\n v29 += 5;\n } while ((uint32_t)v51 != (uint32_t)v55);\nLABEL_33:\n __strcat_chk(v27, \"]\", v25);\n return v27;\n}" + }, + { + "index": 115, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "bool func0(void **list1, int length) {\n for (int i = 0; i < length; i++) {\n if (*((int *)list1[i]) != 0) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n void *list1[3];\n\n\n\n int set1 = 0;\n\n list1[0] = &set1;\n\n list1[1] = &set1;\n\n list1[2] = &set1;\n\n assert(func0(list1, 3) == true);\n\n\n\n int set2 = 1;\n\n list1[0] = &set2;\n\n list1[1] = &set1;\n\n list1[2] = &set1;\n\n assert(func0(list1, 3) == false);\n\n\n\n assert(func0(list1, 0) == true);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11a9 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov (%rax),%eax\ntest %eax,%eax\nje 11a5 \nmov $0x0,%eax\njmp 11b6 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1181 \nmov $0x1,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 0\njmp short loc_11A9\nloc_1181:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov eax, [rax]\ntest eax, eax\njz short loc_11A5\nmov eax, 0\njmp short loc_11B6\nloc_11A5:\nadd [rbp+var_4], 1\nloc_11A9:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1181\nmov eax, 1\nloc_11B6:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n if ( **(_DWORD **)(8LL * i + a1) )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 0\njmp short loc_11A9\nloc_1181:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov eax, [rax]\ntest eax, eax\njz short loc_11A5\nmov eax, 0\njmp short loc_11B6\nloc_11A5:\nadd [rbp+var_4], 1\nloc_11A9:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1181\nmov eax, 1\nloc_11B6:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n if ( **(_DWORD **)(8LL * i + a1) )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int i;\n for (i = 0; i < a2; ++i) {\n if (**(uint32_t **)(8LL * i + a1)) return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int i;\n for (i = 0; i < a2; ++i) {\n if (**(uint32_t **)(8LL * i + a1)) return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": 115, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "bool func0(void **list1, int length) {\n for (int i = 0; i < length; i++) {\n if (*((int *)list1[i]) != 0) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n void *list1[3];\n\n\n\n int set1 = 0;\n\n list1[0] = &set1;\n\n list1[1] = &set1;\n\n list1[2] = &set1;\n\n assert(func0(list1, 3) == true);\n\n\n\n int set2 = 1;\n\n list1[0] = &set2;\n\n list1[1] = &set1;\n\n list1[2] = &set1;\n\n assert(func0(list1, 3) == false);\n\n\n\n assert(func0(list1, 0) == true);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1193 \nmov %rdi,%rax\nlea -0x1(%rsi),%edx\nlea 0x8(%rdi,%rdx,8),%rcx\nmov (%rax),%rdx\ncmpl $0x0,(%rdx)\njne 1199 \nadd $0x8,%rax\ncmp %rcx,%rax\njne 117c \nmov $0x1,%eax\nretq\nmov $0x1,%eax\nretq\nmov $0x0,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1192\nmov rax, rdi\nmovsxd rsi, esi\nlea rcx, [rdi+rsi*8]\nloc_117B:\nmov rdx, [rax]\ncmp dword ptr [rdx], 0\njnz short loc_1198\nadd rax, 8\ncmp rax, rcx\njnz short loc_117B\nmov eax, 1\nretn\nloc_1192:\nmov eax, 1\nretn\nloc_1198:\nmov eax, 0\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD **a1, int a2)\n{\n _DWORD **v2; // rax\n\n if ( a2 <= 0 )\n return 1LL;\n v2 = a1;\n while ( !**v2 )\n {\n if ( ++v2 == &a1[a2] )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_1192\nmov rax, rdi\nmovsxd rsi, esi\nlea rcx, [rdi+rsi*8]\nloc_117B:\nmov rdx, [rax]\ncmp dword ptr [rdx], 0\njnz short loc_1198\nadd rax, 8\ncmp rax, rcx\njnz short loc_117B\nmov eax, 1\nretn\nloc_1192:\nmov eax, 1\nretn\nloc_1198:\nmov eax, 0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD **a1, int a2)\n{\n _DWORD **v2; // rax\n\n if ( a2 <= 0 )\n return 1LL;\n v2 = a1;\n while ( !**v2 )\n {\n if ( ++v2 == &a1[a2] )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t **a1, int a2) {\n uint32_t **v2;\n if (a2 <= 0) return 1LL;\n v2 = a1;\n while (!**v2) {\n if (++v2 == &a1[a2]) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(uint32_t **a1, int a2) {\n uint32_t **v2;\n if (a2 <= 0) return 1LL;\n v2 = a1;\n while (!**v2) {\n if (++v2 == &a1[a2]) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 116, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(int nums[], int size) {\n int result = 0;\n for (int i = 0; i < size; i++) {\n result = result * 10 + nums[i];\n }\n return result;\n}", + "test": "int main() {\n\n int nums1[] = {1, 2, 3};\n\n int size1 = sizeof(nums1) / sizeof(nums1[0]);\n\n assert(func0(nums1, size1) == 123);\n\n\n\n int nums2[] = {4, 5, 6};\n\n int size2 = sizeof(nums2) / sizeof(nums2[0]);\n\n assert(func0(nums2, size2) == 456);\n\n \n\n int nums3[] = {5, 6, 7};\n\n int size3 = sizeof(nums3) / sizeof(nums3[0]);\n\n assert(func0(nums3, size3) == 567);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11b5 \nmov -0x8(%rbp),%edx\nmov %edx,%eax\nshl $0x2,%eax\nadd %edx,%eax\nadd %eax,%eax\nmov %eax,%ecx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nadd %ecx,%eax\nmov %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1188 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11B5\nloc_1188:\nmov edx, [rbp+var_8]\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nmov ecx, eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd eax, ecx\nmov [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_11B5:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n v3 = 10 * v3 + *(_DWORD *)(4LL * i + a1);\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11B5\nloc_1188:\nmov edx, [rbp+var_8]\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nmov ecx, eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd eax, ecx\nmov [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_11B5:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n v3 = 10 * v3 + *(_DWORD *)(4LL * i + a1);\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) v3 = 10 * v3 + *(uint32_t *)(4LL * i + a1);\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) v3 = 10 * v3 + *(uint32_t *)(4LL * i + a1);\n return v3;\n}" + }, + { + "index": 116, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(int nums[], int size) {\n int result = 0;\n for (int i = 0; i < size; i++) {\n result = result * 10 + nums[i];\n }\n return result;\n}", + "test": "int main() {\n\n int nums1[] = {1, 2, 3};\n\n int size1 = sizeof(nums1) / sizeof(nums1[0]);\n\n assert(func0(nums1, size1) == 123);\n\n\n\n int nums2[] = {4, 5, 6};\n\n int size2 = sizeof(nums2) / sizeof(nums2[0]);\n\n assert(func0(nums2, size2) == 456);\n\n \n\n int nums3[] = {5, 6, 7};\n\n int size3 = sizeof(nums3) / sizeof(nums3[0]);\n\n assert(func0(nums3, size3) == 567);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1195 \nmov %rdi,%rax\nlea -0x1(%rsi),%edx\nlea 0x4(%rdi,%rdx,4),%rsi\nmov $0x0,%edx\nlea (%rdx,%rdx,4),%ecx\nmov (%rax),%edx\nlea (%rdx,%rcx,2),%edx\nadd $0x4,%rax\ncmp %rsi,%rax\njne 1181 \nmov %edx,%eax\nretq\nmov $0x0,%edx\njmp 1192 \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1194\nmov rax, rdi\nmovsxd rsi, esi\nlea rsi, [rdi+rsi*4]\nmov edx, 0\nloc_1180:\nlea ecx, [rdx+rdx*4]\nmov edx, [rax]\nlea edx, [rdx+rcx*2]\nadd rax, 4\ncmp rax, rsi\njnz short loc_1180\nloc_1191:\nmov eax, edx\nretn\nloc_1194:\nmov edx, 0\njmp short loc_1191", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n _DWORD *v3; // rsi\n unsigned int v4; // edx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n v4 = *v2++ + 10 * v4;\n while ( v2 != v3 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_1194\nmov rax, rdi\nmovsxd rsi, esi\nlea rsi, [rdi+rsi*4]\nmov edx, 0\nloc_1180:\nlea ecx, [rdx+rdx*4]\nmov edx, [rax]\nlea edx, [rdx+rcx*2]\nadd rax, 4\ncmp rax, rsi\njnz short loc_1180\nloc_1191:\nmov eax, edx\nretn\nloc_1194:\nmov edx, 0\njmp short loc_1191", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n _DWORD *v3; // rsi\n unsigned int v4; // edx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n v4 = *v2++ + 10 * v4;\n while ( v2 != v3 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2) {\n uint32_t *v2;\n uint32_t *v3;\n unsigned int v4;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n v4 = *v2++ + 10 * v4;\n while (v2 != v3);\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n uint32_t *v3;\n unsigned int v4;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n v4 = *v2++ + 10 * v4;\n while (v2 != v3);\n }\n return v4;\n}" + }, + { + "index": 117, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* test_list[], int size) {\n static char res[1000];\n strcpy(res, \"[\");\n for (int i = 0; i < size; i += 2) {\n char temp[100];\n double first, second;\n first = atof(test_list[i]);\n second = atof(test_list[i + 1]);\n snprintf(temp, sizeof(temp), \"(%.2f, %.2f)\", first, second);\n strcat(res, temp);\n if (i < size - 2) {\n strcat(res, \", \");\n }\n }\n strcat(res, \"]\");\n return res;\n}", + "test": "int main() {\n\n char *list1[] = {\"3\", \"4\", \"1\", \"26.45\", \"7.32\", \"8\", \"4\", \"8\"};\n\n char *list2[] = {\"4\", \"4\", \"2\", \"27\", \"4.12\", \"9\", \"7\", \"11\"};\n\n char *list3[] = {\"6\", \"78\", \"5\", \"26.45\", \"1.33\", \"4\", \"82\", \"13\"};\n\n \n\n assert(strcmp(func0(list1, 8), \"[(3.00, 4.00), (1.00, 26.45), (7.32, 8.00), (4.00, 8.00)]\") == 0);\n\n assert(strcmp(func0(list2, 8), \"[(4.00, 4.00), (2.00, 27.00), (4.12, 9.00), (7.00, 11.00)]\") == 0);\n\n assert(strcmp(func0(list3, 8), \"[(6.00, 78.00), (5.00, 26.45), (1.33, 4.00), (82.00, 13.00)]\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0xa0,%rsp\nmov %rdi,-0x98(%rbp)\nmov %esi,-0x9c(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovw $0x5b,0x2e23(%rip)\nmovl $0x0,-0x84(%rbp)\njmpq 131e \nmov -0x84(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x98(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov %rax,%rdi\ncallq 10a0 \nmovq %xmm0,%rax\nmov %rax,-0x80(%rbp)\nmov -0x84(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,8),%rdx\nmov -0x98(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov %rax,%rdi\ncallq 10a0 \nmovq %xmm0,%rax\nmov %rax,-0x78(%rbp)\nmovsd -0x78(%rbp),%xmm0\nmov -0x80(%rbp),%rdx\nlea -0x70(%rbp),%rax\nmovapd %xmm0,%xmm1\nmovq %rdx,%xmm0\nlea 0xd5f(%rip),%rdx\nmov $0x64,%esi\nmov %rax,%rdi\nmov $0x2,%eax\ncallq 10c0 \nlea -0x70(%rbp),%rax\nmov %rax,%rsi\nlea 0x2d77(%rip),%rdi\ncallq 10f0 \nmov -0x9c(%rbp),%eax\nsub $0x2,%eax\ncmp %eax,-0x84(%rbp)\njge 1317 \nlea 0x2d5a(%rip),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nlea 0x2d35(%rip),%rax\nadd %rdx,%rax\nmovw $0x202c,(%rax)\nmovb $0x0,0x2(%rax)\naddl $0x2,-0x84(%rbp)\nmov -0x84(%rbp),%eax\ncmp -0x9c(%rbp),%eax\njl 122c \nlea 0x2d09(%rip),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nlea 0x2ce4(%rip),%rax\nadd %rdx,%rax\nmovw $0x5d,(%rax)\nlea 0x2cd5(%rip),%rax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 137f \ncallq 10b0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0A0h\nmov [rbp+var_98], rdi\nmov [rbp+var_9C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov cs:res_1, 5Bh ; '['\nmov [rbp+var_84], 0\njmp loc_132E\nloc_124C:\nmov eax, [rbp+var_84]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_98]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; nptr\ncall _atof\nmovq rax, xmm0\nmov [rbp+var_80], rax\nmov eax, [rbp+var_84]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_98]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; nptr\ncall _atof\nmovq rax, xmm0\nmov [rbp+var_78], rax\nmovsd xmm0, [rbp+var_78]\nmov rdx, [rbp+var_80]\nlea rax, [rbp+s]\nmovapd xmm1, xmm0\nmovq xmm0, rdx\nlea rdx, format; \"(%.2f, %.2f)\"\nmov esi, 64h ; 'd'; maxlen\nmov rdi, rax; s\nmov eax, 2\ncall _snprintf\nlea rax, [rbp+s]\nmov rsi, rax; src\nlea rax, res_1\nmov rdi, rax; dest\ncall _strcat\nmov eax, [rbp+var_9C]\nsub eax, 2\ncmp [rbp+var_84], eax\njge short loc_1327\nlea rax, res_1\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nlea rax, res_1\nadd rax, rdx\nmov word ptr [rax], 202Ch\nmov byte ptr [rax+2], 0\nloc_1327:\nadd [rbp+var_84], 2\nloc_132E:\nmov eax, [rbp+var_84]\ncmp eax, [rbp+var_9C]\njl loc_124C\nlea rax, res_1\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nlea rax, res_1\nadd rax, rdx\nmov word ptr [rax], 5Dh ; ']'\nlea rax, res_1\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_137C\ncall ___stack_chk_fail\nlocret_137C:\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2)\n{\n double v2; // xmm1_8\n int i; // [rsp+1Ch] [rbp-84h]\n double v5; // [rsp+20h] [rbp-80h]\n char s[104]; // [rsp+30h] [rbp-70h] BYREF\n unsigned __int64 v7; // [rsp+98h] [rbp-8h]\n\n v7 = __readfsqword(0x28u);\n strcpy(res_1, \"[\");\n for ( i = 0; i < a2; i += 2 )\n {\n v5 = atof(*(const char **)(8LL * i + a1));\n v2 = atof(*(const char **)(8 * (i + 1LL) + a1));\n snprintf(s, 0x64uLL, \"(%.2f, %.2f)\", v5, v2);\n strcat(res_1, s);\n if ( i < a2 - 2 )\n strcpy(&res_1[strlen(res_1)], \", \");\n }\n *(_WORD *)&res_1[strlen(res_1)] = 93;\n return res_1;\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0A0h\nmov [rbp+var_98], rdi\nmov [rbp+var_9C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov cs:s, 5Bh ; '['\nmov [rbp+var_84], 0\njmp loc_132E\nloc_124C:\nmov eax, [rbp+var_84]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_98]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; nptr\ncall _atof\nmovq rax, xmm0\nmov [rbp+var_80], rax\nmov eax, [rbp+var_84]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_98]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; nptr\ncall _atof\nmovq rax, xmm0\nmov [rbp+var_78], rax\nmovsd xmm0, [rbp+var_78]\nmov rdx, [rbp+var_80]\nlea rax, [rbp+s]\nmovapd xmm1, xmm0\nmovq xmm0, rdx\nlea rdx, format; \"(%.2f, %.2f)\"\nmov esi, 64h ; 'd'; maxlen\nmov rdi, rax; s\nmov eax, 2\ncall _snprintf\nlea rax, [rbp+s]\nmov rsi, rax; src\nlea rax, s\nmov rdi, rax; dest\ncall _strcat\nmov eax, [rbp+var_9C]\nsub eax, 2\ncmp [rbp+var_84], eax\njge short loc_1327\nlea rax, s\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nlea rax, s\nadd rax, rdx\nmov word ptr [rax], 202Ch\nmov byte ptr [rax+2], 0\nloc_1327:\nadd [rbp+var_84], 2\nloc_132E:\nmov eax, [rbp+var_84]\ncmp eax, [rbp+var_9C]\njl loc_124C\nlea rax, s\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nlea rax, s\nadd rax, rdx\nmov word ptr [rax], 5Dh ; ']'\nlea rax, s\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_137C\ncall ___stack_chk_fail\nlocret_137C:\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1209(__int64 a1, int a2)\n{\n double v2; // xmm1_8\n int i; // [rsp+1Ch] [rbp-84h]\n double v5; // [rsp+20h] [rbp-80h]\n char s[104]; // [rsp+30h] [rbp-70h] BYREF\n unsigned __int64 v7; // [rsp+98h] [rbp-8h]\n\n v7 = __readfsqword(0x28u);\n strcpy(::s, \"[\");\n for ( i = 0; i < a2; i += 2 )\n {\n v5 = atof(*(const char **)(8LL * i + a1));\n v2 = atof(*(const char **)(8 * (i + 1LL) + a1));\n snprintf(s, 0x64uLL, \"(%.2f, %.2f)\", v5, v2);\n strcat(::s, s);\n if ( i < a2 - 2 )\n strcpy(&::s[strlen(::s)], \", \");\n }\n *(_WORD *)&::s[strlen(::s)] = 93;\n return ::s;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1209(long long a1, int a2) {\n double v2;\n int i;\n double v5;\n char s[104];\n unsigned long long v7;\n v7 = __readfsqword(40u);\n strcpy(::s, \"[\");\n for (i = 0; i < a2; i += 2) {\n v5 = atof(*(const char **)(8LL * i + a1));\n v2 = atof(*(const char **)(8 * (i + 1LL) + a1));\n snprintf(s, 100uLL, \"(%.2f, %.2f)\", v5, v2);\n strcat(::s, s);\n if (i < a2 - 2) strcpy(&::s[strlen(::s)], \", \");\n }\n *(unsigned short *)&::s[strlen(::s)] = 93;\n return ::s;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2) {\n double v2;\n int i;\n double v5;\n char s[104];\n unsigned long long v7;\n v7 = __readfsqword(40u);\n strcpy(res_1, \"[\");\n for (i = 0; i < a2; i += 2) {\n v5 = atof(*(const char **)(8LL * i + a1));\n v2 = atof(*(const char **)(8 * (i + 1LL) + a1));\n snprintf(s, 100uLL, \"(%.2f, %.2f)\", v5, v2);\n strcat(res_1, s);\n if (i < a2 - 2) strcpy(&res_1[strlen(res_1)], \", \");\n }\n *(unsigned short *)&res_1[strlen(res_1)] = 93;\n return res_1;\n}" + }, + { + "index": 117, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* test_list[], int size) {\n static char res[1000];\n strcpy(res, \"[\");\n for (int i = 0; i < size; i += 2) {\n char temp[100];\n double first, second;\n first = atof(test_list[i]);\n second = atof(test_list[i + 1]);\n snprintf(temp, sizeof(temp), \"(%.2f, %.2f)\", first, second);\n strcat(res, temp);\n if (i < size - 2) {\n strcat(res, \", \");\n }\n }\n strcat(res, \"]\");\n return res;\n}", + "test": "int main() {\n\n char *list1[] = {\"3\", \"4\", \"1\", \"26.45\", \"7.32\", \"8\", \"4\", \"8\"};\n\n char *list2[] = {\"4\", \"4\", \"2\", \"27\", \"4.12\", \"9\", \"7\", \"11\"};\n\n char *list3[] = {\"6\", \"78\", \"5\", \"26.45\", \"1.33\", \"4\", \"82\", \"13\"};\n\n \n\n assert(strcmp(func0(list1, 8), \"[(3.00, 4.00), (1.00, 26.45), (7.32, 8.00), (4.00, 8.00)]\") == 0);\n\n assert(strcmp(func0(list2, 8), \"[(4.00, 4.00), (2.00, 27.00), (4.12, 9.00), (7.00, 11.00)]\") == 0);\n\n assert(strcmp(func0(list3, 8), \"[(6.00, 78.00), (5.00, 26.45), (1.33, 4.00), (82.00, 13.00)]\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nadd $0xffffffffffffff80,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x78(%rsp)\nxor %eax,%eax\nmovw $0x5b,0x2e4e(%rip)\ntest %esi,%esi\njle 12ab \nmov %rdi,%rbp\nmov %esi,%r13d\nlea -0x1(%rsi),%eax\nshr %eax\nmov %eax,%eax\nlea 0x2(%rax,%rax,1),%r14\nmov $0x0,%ebx\nlea 0x10(%rsp),%r12\njmp 1239 \nmov $0x3e8,%edx\nlea 0xded(%rip),%rsi\nlea 0x2e15(%rip),%rdi\ncallq 1090 <__strcat_chk@plt>\nadd $0x2,%rbx\ncmp %r14,%rbx\nje 12ab \nmov 0x0(%rbp,%rbx,8),%rdi\nmov $0x0,%esi\ncallq 10b0 \nmovsd %xmm0,0x8(%rsp)\nmov 0x8(%rbp,%rbx,8),%rdi\nmov $0x0,%esi\ncallq 10b0 \nmovapd %xmm0,%xmm1\nmovsd 0x8(%rsp),%xmm0\nlea 0xd96(%rip),%r8\nmov $0x64,%ecx\nmov $0x1,%edx\nmov $0x64,%esi\nmov %r12,%rdi\nmov $0x2,%eax\ncallq 10a0 <__snprintf_chk@plt>\nmov $0x3e8,%edx\nmov %r12,%rsi\nlea 0x2da7(%rip),%rdi\ncallq 1090 <__strcat_chk@plt>\nlea -0x2(%r13),%eax\ncmp %ebx,%eax\njle 1230 \njmpq 1218 \nmov $0x3e8,%edx\nlea 0xd5d(%rip),%rsi\nlea 0x2d82(%rip),%rdi\ncallq 1090 <__strcat_chk@plt>\nmov 0x78(%rsp),%rax\nxor %fs:0x28,%rax\njne 12e7 \nlea 0x2d66(%rip),%rax\nsub $0xffffffffffffff80,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\ncallq 10c0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 88h\nmov rax, fs:28h\nmov [rsp+0B8h+var_40], rax\nxor eax, eax\nmov cs:res_1, 5Bh ; '['\ntest esi, esi\njle loc_12CD\nmov rbp, rdi\nlea eax, [rsi-1]\nshr eax, 1\nlea r15d, [rax+1]\nadd r15, r15\nmov ebx, 0\nlea r12, [rsp+0B8h+var_A8]\nlea r14, res_1\nlea r13d, [rsi-2]\njmp short loc_124E\nloc_1245:\nadd rbx, 2\ncmp rbx, r15\njz short loc_12CD\nloc_124E:\nmov rdi, [rbp+rbx*8+0]; nptr\nmov esi, 0; endptr\ncall _strtod\nmovsd [rsp+0B8h+var_B0], xmm0\nmov rdi, [rbp+rbx*8+8]; nptr\nmov esi, 0; endptr\ncall _strtod\nmovapd xmm1, xmm0\nmovsd xmm0, [rsp+0B8h+var_B0]\nlea r8, a2f2f; \"(%.2f, %.2f)\"\nmov ecx, 64h ; 'd'\nmov edx, 2\nmov esi, 64h ; 'd'\nmov rdi, r12\nmov eax, 2\ncall ___snprintf_chk\nmov edx, 3E8h\nmov rsi, r12\nmov rdi, r14\ncall ___strcat_chk\ncmp r13d, ebx\njle short loc_1245\nmov edx, 3E8h\nlea rsi, asc_2011; \", \"\nmov rdi, r14\ncall ___strcat_chk\njmp loc_1245\nloc_12CD:\nmov edx, 3E8h\nlea rsi, asc_2014; \"]\"\nlea rbx, res_1\nmov rdi, rbx\ncall ___strcat_chk\nmov rax, [rsp+0B8h+var_40]\nsub rax, fs:28h\njnz short loc_130D\nmov rax, rbx\nadd rsp, 88h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_130D:\ncall ___stack_chk_fail", + "ida_pseudo": "__int16 *__fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // rbx\n double v3; // xmm1_8\n double v5; // [rsp+8h] [rbp-B0h]\n _BYTE v6[104]; // [rsp+10h] [rbp-A8h] BYREF\n unsigned __int64 v7; // [rsp+78h] [rbp-40h]\n\n v7 = __readfsqword(0x28u);\n res_1 = 91;\n if ( a2 > 0 )\n {\n v2 = 0LL;\n do\n {\n v5 = strtod(*(const char **)(a1 + 8 * v2), 0LL);\n v3 = strtod(*(const char **)(a1 + 8 * v2 + 8), 0LL);\n __snprintf_chk(v6, 100LL, 2LL, 100LL, \"(%.2f, %.2f)\", v5, v3);\n __strcat_chk(&res_1, v6, 1000LL);\n if ( a2 - 2 > (int)v2 )\n __strcat_chk(&res_1, \", \", 1000LL);\n v2 += 2LL;\n }\n while ( v2 != 2LL * (((unsigned int)(a2 - 1) >> 1) + 1) );\n }\n __strcat_chk(&res_1, \"]\", 1000LL);\n return &res_1;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 88h\nmov rax, fs:28h\nmov [rsp+0B8h+var_40], rax\nxor eax, eax\nmov cs:word_4040, 5Bh ; '['\ntest esi, esi\njle loc_12CD\nmov rbp, rdi\nlea eax, [rsi-1]\nshr eax, 1\nlea r15d, [rax+1]\nadd r15, r15\nmov ebx, 0\nlea r12, [rsp+0B8h+var_A8]\nlea r14, word_4040\nlea r13d, [rsi-2]\njmp short loc_124E\nloc_1245:\nadd rbx, 2\ncmp rbx, r15\njz short loc_12CD\nloc_124E:\nmov rdi, [rbp+rbx*8+0]; nptr\nmov esi, 0; endptr\ncall _strtod\nmovsd [rsp+0B8h+var_B0], xmm0\nmov rdi, [rbp+rbx*8+8]; nptr\nmov esi, 0; endptr\ncall _strtod\nmovapd xmm1, xmm0\nmovsd xmm0, [rsp+0B8h+var_B0]\nlea r8, a2f2f; \"(%.2f, %.2f)\"\nmov ecx, 64h ; 'd'\nmov edx, 2\nmov esi, 64h ; 'd'\nmov rdi, r12\nmov eax, 2\ncall ___snprintf_chk\nmov edx, 3E8h\nmov rsi, r12\nmov rdi, r14\ncall ___strcat_chk\ncmp r13d, ebx\njle short loc_1245\nmov edx, 3E8h\nlea rsi, asc_2011; \", \"\nmov rdi, r14\ncall ___strcat_chk\njmp loc_1245\nloc_12CD:\nmov edx, 3E8h\nlea rsi, asc_2014; \"]\"\nlea rbx, word_4040\nmov rdi, rbx\ncall ___strcat_chk\nmov rax, [rsp+0B8h+var_40]\nsub rax, fs:28h\njnz short loc_130D\nmov rax, rbx\nadd rsp, 88h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_130D:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int16 *__fastcall sub_11E9(__int64 a1, int a2)\n{\n __int64 v2; // rbx\n double v3; // xmm1_8\n double v5; // [rsp+8h] [rbp-B0h]\n _BYTE v6[104]; // [rsp+10h] [rbp-A8h] BYREF\n unsigned __int64 v7; // [rsp+78h] [rbp-40h]\n\n v7 = __readfsqword(0x28u);\n word_4040 = 91;\n if ( a2 > 0 )\n {\n v2 = 0LL;\n do\n {\n v5 = strtod(*(const char **)(a1 + 8 * v2), 0LL);\n v3 = strtod(*(const char **)(a1 + 8 * v2 + 8), 0LL);\n __snprintf_chk(v6, 100LL, 2LL, 100LL, \"(%.2f, %.2f)\", v5, v3);\n __strcat_chk(&word_4040, v6, 1000LL);\n if ( a2 - 2 > (int)v2 )\n __strcat_chk(&word_4040, \", \", 1000LL);\n v2 += 2LL;\n }\n while ( v2 != 2LL * (((unsigned int)(a2 - 1) >> 1) + 1) );\n }\n __strcat_chk(&word_4040, \"]\", 1000LL);\n return &word_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "short *sub_11E9(long long a1, int a2) {\n long long v2;\n double v3;\n double v5;\n uint8_t v6[104];\n unsigned long long v7;\n v7 = __readfsqword(40u);\n word_4040 = 91;\n if (a2 > 0) {\n v2 = 0LL;\n do {\n v5 = strtod(*(const char **)(a1 + 8 * v2), 0LL);\n v3 = strtod(*(const char **)(a1 + 8 * v2 + 8), 0LL);\n __snprintf_chk(v6, 100LL, 2LL, 100LL, \"(%.2f, %.2f)\", v5, v3);\n __strcat_chk(&word_4040, v6, 1000LL);\n if (a2 - 2 > (int)v2) __strcat_chk(&word_4040, \", \", 1000LL);\n v2 += 2LL;\n } while (v2 != 2LL * (((unsigned int)(a2 - 1) >> 1) + 1));\n }\n __strcat_chk(&word_4040, \"]\", 1000LL);\n return &word_4040;\n}", + "ida_pseudo_norm": "short *func0(long long a1, int a2) {\n long long v2;\n double v3;\n double v5;\n uint8_t v6[104];\n unsigned long long v7;\n v7 = __readfsqword(40u);\n res_1 = 91;\n if (a2 > 0) {\n v2 = 0LL;\n do {\n v5 = strtod(*(const char **)(a1 + 8 * v2), 0LL);\n v3 = strtod(*(const char **)(a1 + 8 * v2 + 8), 0LL);\n __snprintf_chk(v6, 100LL, 2LL, 100LL, \"(%.2f, %.2f)\", v5, v3);\n __strcat_chk(&res_1, v6, 1000LL);\n if (a2 - 2 > (int)v2) __strcat_chk(&res_1, \", \", 1000LL);\n v2 += 2LL;\n } while (v2 != 2LL * (((unsigned int)(a2 - 1) >> 1) + 1));\n }\n __strcat_chk(&res_1, \"]\", 1000LL);\n return &res_1;\n}" + }, + { + "index": 117, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* test_list[], int size) {\n static char res[1000];\n strcpy(res, \"[\");\n for (int i = 0; i < size; i += 2) {\n char temp[100];\n double first, second;\n first = atof(test_list[i]);\n second = atof(test_list[i + 1]);\n snprintf(temp, sizeof(temp), \"(%.2f, %.2f)\", first, second);\n strcat(res, temp);\n if (i < size - 2) {\n strcat(res, \", \");\n }\n }\n strcat(res, \"]\");\n return res;\n}", + "test": "int main() {\n\n char *list1[] = {\"3\", \"4\", \"1\", \"26.45\", \"7.32\", \"8\", \"4\", \"8\"};\n\n char *list2[] = {\"4\", \"4\", \"2\", \"27\", \"4.12\", \"9\", \"7\", \"11\"};\n\n char *list3[] = {\"6\", \"78\", \"5\", \"26.45\", \"1.33\", \"4\", \"82\", \"13\"};\n\n \n\n assert(strcmp(func0(list1, 8), \"[(3.00, 4.00), (1.00, 26.45), (7.32, 8.00), (4.00, 8.00)]\") == 0);\n\n assert(strcmp(func0(list2, 8), \"[(4.00, 4.00), (2.00, 27.00), (4.12, 9.00), (7.00, 11.00)]\") == 0);\n\n assert(strcmp(func0(list3, 8), \"[(6.00, 78.00), (5.00, 26.45), (1.33, 4.00), (82.00, 13.00)]\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x88,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x78(%rsp)\nxor %eax,%eax\nmov $0x5b,%eax\nmov %ax,0x2bcf(%rip)\ntest %esi,%esi\njle 1574 \nlea -0x2(%rsi),%r14d\nsub $0x1,%esi\nmov %rdi,%rbx\nxor %r15d,%r15d\nshr %esi\nlea 0x2bb1(%rip),%r12\nlea 0x10(%rsp),%rbp\nlea 0x2(%rsi,%rsi,1),%rax\nmov %r12,%r13\nmov %rax,0x8(%rsp)\nnopl 0x0(%rax)\nmov (%rbx,%r15,8),%rdi\nxor %esi,%esi\ncallq 10d0 \nmov 0x8(%rbx,%r15,8),%rdi\nxor %esi,%esi\nmovsd %xmm0,(%rsp)\ncallq 10d0 \nmovsd (%rsp),%xmm2\nmov %rbp,%rdi\nlea 0xb33(%rip),%r8\nmovapd %xmm0,%xmm1\nmov $0x64,%ecx\nmov $0x1,%edx\nmov $0x64,%esi\nmovapd %xmm2,%xmm0\nmov $0x2,%eax\ncallq 10c0 <__snprintf_chk@plt>\nlea 0x2b45(%rip),%rdi\nmov (%rdi),%edx\nadd $0x4,%rdi\nlea -0x1010101(%rdx),%eax\nnot %edx\nand %edx,%eax\nand $0x80808080,%eax\nje 14fb \nmov %eax,%edx\nmov %rbp,%rsi\nshr $0x10,%edx\ntest $0x8080,%eax\ncmove %edx,%eax\nlea 0x2(%rdi),%rdx\ncmove %rdx,%rdi\nmov $0x3e8,%edx\nmov %eax,%ecx\nadd %al,%cl\nsbb $0x3,%rdi\nsub %r12,%rdi\nadd %r13,%rdi\ncallq 1110 <__stpcpy_chk@plt>\nmov %rax,%rdi\ncmp %r15d,%r14d\njle 1565 \nlea 0x2ed7(%rip),%rcx\nmov $0x3,%edx\nlea 0xab6(%rip),%rsi\nsub %rax,%rcx\ncallq 1100 <__memcpy_chk@plt>\nadd $0x2,%r15\ncmp 0x8(%rsp),%r15\njne 14a8 \nmov $0x3e8,%edx\nlea 0xa84(%rip),%rsi\nlea 0x2ab9(%rip),%rdi\ncallq 10b0 <__strcat_chk@plt>\nmov 0x78(%rsp),%rax\nxor %fs:0x28,%rax\njne 15b5 \nadd $0x88,%rsp\nlea 0x2a96(%rip),%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\ncallq 10e0 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 88h\nmov rax, fs:28h\nmov [rsp+0B8h+var_40], rax\nxor eax, eax\nmov eax, 5Bh ; '['\nmov cs:res_1, ax\ntest esi, esi\njle loc_15E0\nlea r14d, [rsi-2]\nsub esi, 1\nmov rbx, rdi\nxor r15d, r15d\nshr esi, 1\nlea rbp, res_1\nlea r12, [rsp+0B8h+var_A8]\nlea r13d, [rsi+1]\nadd r13, r13\nnop dword ptr [rax+rax+00h]\nloc_1510:\nmov rdi, [rbx+r15*8]; nptr\nxor esi, esi; endptr\ncall _strtod\nmov rdi, [rbx+r15*8+8]; nptr\nxor esi, esi; endptr\nmovsd [rsp+0B8h+var_B0], xmm0\ncall _strtod\nmov edx, 2\nmov esi, 64h ; 'd'\nlea r8, a2f2f; \"(%.2f, %.2f)\"\nmovapd xmm1, xmm0\nmovsd xmm0, [rsp+0B8h+var_B0]\nmov ecx, 64h ; 'd'\nmov rdi, r12\nmov eax, 2\ncall ___snprintf_chk\nmov rdi, rbp; s\ncall _strlen\nmov edx, 3E8h\nmov rsi, r12\nlea rdi, [rbp+rax+0]\ncall ___stpcpy_chk\ncmp r14d, r15d\njle short loc_1597\nlea rcx, _end\nmov edx, 3\nlea rsi, asc_2013; \", \"\nmov rdi, rax\nsub rcx, rax\ncall ___memcpy_chk\nloc_1597:\nadd r15, 2\ncmp r15, r13\njnz loc_1510\nloc_15A4:\nmov edx, 3E8h\nlea rsi, unk_2004\nmov rdi, rbp\ncall ___strcat_chk\nmov rax, [rsp+0B8h+var_40]\nsub rax, fs:28h\njnz short loc_15E9\nadd rsp, 88h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15E0:\nlea rbp, res_1\njmp short loc_15A4\nloc_15E9:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // r15\n double v3; // xmm1_8\n size_t v4; // rax\n __int64 v5; // rax\n double v7; // [rsp+8h] [rbp-B0h]\n _BYTE v8[104]; // [rsp+10h] [rbp-A8h] BYREF\n unsigned __int64 v9; // [rsp+78h] [rbp-40h]\n\n v9 = __readfsqword(0x28u);\n strcpy(res_1, \"[\");\n if ( a2 > 0 )\n {\n v2 = 0LL;\n do\n {\n v7 = strtod(*(const char **)(a1 + 8 * v2), 0LL);\n v3 = strtod(*(const char **)(a1 + 8 * v2 + 8), 0LL);\n __snprintf_chk(v8, 100LL, 2LL, 100LL, \"(%.2f, %.2f)\", v7, v3);\n v4 = strlen(res_1);\n v5 = __stpcpy_chk(&res_1[v4], v8, 1000LL);\n if ( a2 - 2 > (int)v2 )\n __memcpy_chk(v5, \", \", 3LL, (char *)&end - v5);\n v2 += 2LL;\n }\n while ( v2 != 2LL * (((unsigned int)(a2 - 1) >> 1) + 1) );\n }\n __strcat_chk(res_1, &unk_2004, 1000LL);\n return res_1;\n}", + "ida_strip_asm": "sub_14B0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 88h\nmov rax, fs:28h\nmov [rsp+0B8h+var_40], rax\nxor eax, eax\nmov eax, 5Bh ; '['\nmov cs:s, ax\ntest esi, esi\njle loc_15E0\nlea r14d, [rsi-2]\nsub esi, 1\nmov rbx, rdi\nxor r15d, r15d\nshr esi, 1\nlea rbp, s\nlea r12, [rsp+0B8h+var_A8]\nlea r13d, [rsi+1]\nadd r13, r13\nnop dword ptr [rax+rax+00h]\nloc_1510:\nmov rdi, [rbx+r15*8]; nptr\nxor esi, esi; endptr\ncall _strtod\nmov rdi, [rbx+r15*8+8]; nptr\nxor esi, esi; endptr\nmovsd [rsp+0B8h+var_B0], xmm0\ncall _strtod\nmov edx, 2\nmov esi, 64h ; 'd'\nlea r8, a2f2f; \"(%.2f, %.2f)\"\nmovapd xmm1, xmm0\nmovsd xmm0, [rsp+0B8h+var_B0]\nmov ecx, 64h ; 'd'\nmov rdi, r12\nmov eax, 2\ncall ___snprintf_chk\nmov rdi, rbp; s\ncall _strlen\nmov edx, 3E8h\nmov rsi, r12\nlea rdi, [rbp+rax+0]\ncall ___stpcpy_chk\ncmp r14d, r15d\njle short loc_1597\nlea rcx, __strcat_chk\nmov edx, 3\nlea rsi, asc_2013; \", \"\nmov rdi, rax\nsub rcx, rax\ncall ___memcpy_chk\nloc_1597:\nadd r15, 2\ncmp r15, r13\njnz loc_1510\nloc_15A4:\nmov edx, 3E8h\nlea rsi, unk_2004\nmov rdi, rbp\ncall ___strcat_chk\nmov rax, [rsp+0B8h+var_40]\nsub rax, fs:28h\njnz short loc_15E9\nadd rsp, 88h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15E0:\nlea rbp, s\njmp short loc_15A4\nloc_15E9:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_14B0(__int64 a1, int a2)\n{\n __int64 v2; // r15\n double v3; // xmm1_8\n size_t v4; // rax\n __int64 v5; // rax\n double v7; // [rsp+8h] [rbp-B0h]\n _BYTE v8[104]; // [rsp+10h] [rbp-A8h] BYREF\n unsigned __int64 v9; // [rsp+78h] [rbp-40h]\n\n v9 = __readfsqword(0x28u);\n strcpy(s, \"[\");\n if ( a2 > 0 )\n {\n v2 = 0LL;\n do\n {\n v7 = strtod(*(const char **)(a1 + 8 * v2), 0LL);\n v3 = strtod(*(const char **)(a1 + 8 * v2 + 8), 0LL);\n __snprintf_chk(v8, 100LL, 2LL, 100LL, \"(%.2f, %.2f)\", v7, v3);\n v4 = strlen(s);\n v5 = __stpcpy_chk(&s[v4], v8, 1000LL);\n if ( a2 - 2 > (int)v2 )\n __memcpy_chk(v5, \", \", 3LL, (char *)&_strcat_chk - v5);\n v2 += 2LL;\n }\n while ( v2 != 2LL * (((unsigned int)(a2 - 1) >> 1) + 1) );\n }\n __strcat_chk(s, &unk_2004, 1000LL);\n return s;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_14B0(long long a1, int a2) {\n long long v2;\n double v3;\n unsigned int v4;\n long long v5;\n double v7;\n uint8_t v8[104];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n strcpy(s, \"[\");\n if (a2 > 0) {\n v2 = 0LL;\n do {\n v7 = strtod(*(const char **)(a1 + 8 * v2), 0LL);\n v3 = strtod(*(const char **)(a1 + 8 * v2 + 8), 0LL);\n __snprintf_chk(v8, 100LL, 2LL, 100LL, \"(%.2f, %.2f)\", v7, v3);\n v4 = strlen(s);\n v5 = __stpcpy_chk(&s[v4], v8, 1000LL);\n if (a2 - 2 > (int)v2)\n __memcpy_chk(v5, \", \", 3LL, (char *)&_strcat_chk - v5);\n v2 += 2LL;\n } while (v2 != 2LL * (((unsigned int)(a2 - 1) >> 1) + 1));\n }\n __strcat_chk(s, &unk_2004, 1000LL);\n return s;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2) {\n long long v2;\n double v3;\n unsigned int v4;\n long long v5;\n double v7;\n uint8_t v8[104];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n strcpy(res_1, \"[\");\n if (a2 > 0) {\n v2 = 0LL;\n do {\n v7 = strtod(*(const char **)(a1 + 8 * v2), 0LL);\n v3 = strtod(*(const char **)(a1 + 8 * v2 + 8), 0LL);\n __snprintf_chk(v8, 100LL, 2LL, 100LL, \"(%.2f, %.2f)\", v7, v3);\n v4 = strlen(res_1);\n v5 = __stpcpy_chk(&res_1[v4], v8, 1000LL);\n if (a2 - 2 > (int)v2) __memcpy_chk(v5, \", \", 3LL, (char *)&end - v5);\n v2 += 2LL;\n } while (v2 != 2LL * (((unsigned int)(a2 - 1) >> 1) + 1));\n }\n __strcat_chk(res_1, &unk_2004, 1000LL);\n return res_1;\n}" + }, + { + "index": 117, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* test_list[], int size) {\n static char res[1000];\n strcpy(res, \"[\");\n for (int i = 0; i < size; i += 2) {\n char temp[100];\n double first, second;\n first = atof(test_list[i]);\n second = atof(test_list[i + 1]);\n snprintf(temp, sizeof(temp), \"(%.2f, %.2f)\", first, second);\n strcat(res, temp);\n if (i < size - 2) {\n strcat(res, \", \");\n }\n }\n strcat(res, \"]\");\n return res;\n}", + "test": "int main() {\n\n char *list1[] = {\"3\", \"4\", \"1\", \"26.45\", \"7.32\", \"8\", \"4\", \"8\"};\n\n char *list2[] = {\"4\", \"4\", \"2\", \"27\", \"4.12\", \"9\", \"7\", \"11\"};\n\n char *list3[] = {\"6\", \"78\", \"5\", \"26.45\", \"1.33\", \"4\", \"82\", \"13\"};\n\n \n\n assert(strcmp(func0(list1, 8), \"[(3.00, 4.00), (1.00, 26.45), (7.32, 8.00), (4.00, 8.00)]\") == 0);\n\n assert(strcmp(func0(list2, 8), \"[(4.00, 4.00), (2.00, 27.00), (4.12, 9.00), (7.00, 11.00)]\") == 0);\n\n assert(strcmp(func0(list3, 8), \"[(6.00, 78.00), (5.00, 26.45), (1.33, 4.00), (82.00, 13.00)]\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x88,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x78(%rsp)\nxor %eax,%eax\nmov $0x5b,%eax\nmov %ax,0x2b8f(%rip)\ntest %esi,%esi\njle 1620 \nlea -0x2(%rsi),%r15d\nmov %rdi,%r13\nmov %esi,%r14d\ntest %r15d,%r15d\njle 1668 \nmov %rdi,%rbp\nxor %ebx,%ebx\nlea 0x10(%rsp),%r12\nnopw %cs:0x0(%rax,%rax,1)\nmov 0x0(%rbp),%rdi\nxor %esi,%esi\ncallq 10d0 \nmov 0x8(%rbp),%rdi\nxor %esi,%esi\nmovsd %xmm0,0x8(%rsp)\ncallq 10d0 \nmovsd 0x8(%rsp),%xmm2\nmov %r12,%rdi\nlea 0xafa(%rip),%r8\nmovapd %xmm0,%xmm1\nmov $0x64,%ecx\nmov $0x1,%edx\nmov $0x64,%esi\nmovapd %xmm2,%xmm0\nmov $0x2,%eax\ncallq 10c0 <__snprintf_chk@plt>\nlea 0x2b0c(%rip),%rdi\nmov (%rdi),%edx\nadd $0x4,%rdi\nlea -0x1010101(%rdx),%eax\nnot %edx\nand %edx,%eax\nand $0x80808080,%eax\nje 1534 \nmov %eax,%edx\nmov %r12,%rsi\nshr $0x10,%edx\ntest $0x8080,%eax\ncmove %edx,%eax\nlea 0x2(%rdi),%rdx\ncmove %rdx,%rdi\nmov $0x3e8,%edx\nmov %eax,%ecx\nadd %al,%cl\nsbb $0x3,%rdi\nadd $0x2,%ebx\nadd $0x10,%rbp\ncallq 1110 <__stpcpy_chk@plt>\nlea 0x2ea5(%rip),%rcx\nmov $0x3,%edx\nlea 0xa84(%rip),%rsi\nmov %rax,%rdi\nsub %rax,%rcx\ncallq 1100 <__memcpy_chk@plt>\ncmp %r15d,%ebx\njl 14e0 \ncmp %ebx,%r14d\njle 1620 \nmovslq %ebx,%rbx\nlea 0xa54(%rip),%rbp\nnopw 0x0(%rax,%rax,1)\nmov 0x0(%r13,%rbx,8),%rdi\nxor %esi,%esi\ncallq 10d0 \nmov 0x8(%r13,%rbx,8),%rdi\nxor %esi,%esi\nadd $0x2,%rbx\nmovsd %xmm0,0x8(%rsp)\ncallq 10d0 \nmov %rbp,%r8\nmov $0x64,%ecx\nmov %r12,%rdi\nmovsd 0x8(%rsp),%xmm2\nmovapd %xmm0,%xmm1\nmov $0x1,%edx\nmov $0x64,%esi\nmov $0x2,%eax\nmovapd %xmm2,%xmm0\ncallq 10c0 <__snprintf_chk@plt>\nmov $0x3e8,%edx\nmov %r12,%rsi\nlea 0x2a2a(%rip),%rdi\ncallq 10b0 <__strcat_chk@plt>\ncmp %ebx,%r14d\njg 15b8 \nmov $0x3e8,%edx\nlea 0x9d8(%rip),%rsi\nlea 0x2a0d(%rip),%rdi\ncallq 10b0 <__strcat_chk@plt>\nmov 0x78(%rsp),%rax\nxor %fs:0x28,%rax\njne 1674 \nadd $0x88,%rsp\nlea 0x29ea(%rip),%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\nxor %ebx,%ebx\nlea 0x10(%rsp),%r12\njmpq 15a8 \ncallq 10e0 <__stack_chk_fail@plt>\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov eax, 5Bh ; '['\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 88h\nmov rdx, fs:28h\nmov [rsp+0B8h+var_40], rdx\nxor edx, edx\nmov cs:res_1, ax\ntest esi, esi\njle loc_1678\nlea edx, [rsi-2]\nmov r12, rdi\nmov r14d, esi\ntest edx, edx\njg loc_15B0\nxor r13d, r13d\nlea rbp, res_1\nlea rbx, [rsp+0B8h+var_A8]\nloc_1509:\nlea r15, a2f2f; \"(%.2f, %.2f)\"\nloc_1510:\nmov rdi, [r12+r13*8]; nptr\nxor esi, esi; endptr\ncall _strtod\nmov rdi, [r12+r13*8+8]; nptr\nxor esi, esi; endptr\nadd r13, 2\nmovsd [rsp+0B8h+var_B8], xmm0\ncall _strtod\nmov r8, r15\nmov ecx, 64h ; 'd'\nmov rdi, rbx\nmovapd xmm1, xmm0\nmovsd xmm0, [rsp+0B8h+var_B8]\nmov edx, 2\nmov esi, 64h ; 'd'\nmov eax, 2\ncall ___snprintf_chk\nmov edx, 3E8h\nmov rsi, rbx\nmov rdi, rbp\ncall ___strcat_chk\ncmp r14d, r13d\njg short loc_1510\nloc_156D:\nmov edx, 3E8h\nlea rsi, unk_2004\nmov rdi, rbp\ncall ___strcat_chk\nmov rax, [rsp+0B8h+var_40]\nsub rax, fs:28h\njnz loc_1684\nadd rsp, 88h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15B0:\nmov [rsp+0B8h+var_B0], rdi\nxor r13d, r13d\nlea rbx, [rsp+0B8h+var_A8]\nmov r15d, edx\nmov r12d, r13d\nlea rbp, res_1\nmov r13, rdi\nloc_15CD:\nmov rdi, [r13+0]; nptr\nxor esi, esi; endptr\nadd r12d, 2\nadd r13, 10h\ncall _strtod\nmov rdi, [r13-8]; nptr\nxor esi, esi; endptr\nmovsd [rsp+0B8h+var_B8], xmm0\ncall _strtod\nlea r8, a2f2f; \"(%.2f, %.2f)\"\nmov ecx, 64h ; 'd'\nmov rdi, rbx\nmovapd xmm1, xmm0\nmovsd xmm0, [rsp+0B8h+var_B8]\nmov edx, 2\nmov esi, 64h ; 'd'\nmov eax, 2\ncall ___snprintf_chk\nmov rdi, rbp; s\ncall _strlen\nmov edx, 3E8h\nmov rsi, rbx\nlea rdi, [rbp+rax+0]\ncall ___stpcpy_chk\nlea rcx, _end\nmov edx, 3\nlea rsi, asc_2013; \", \"\nmov rdi, rax\nsub rcx, rax\ncall ___memcpy_chk\ncmp r12d, r15d\njl loc_15CD\nmovsxd r13, r12d\nmov r12, [rsp+0B8h+var_B0]\ncmp r14d, r13d\njg loc_1509\njmp loc_156D\nloc_1678:\nlea rbp, res_1\njmp loc_156D\nloc_1684:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(const char **a1, int a2)\n{\n const char **v2; // r12\n __int64 v3; // r13\n double v4; // xmm0_8\n const char *v5; // rdi\n double v6; // xmm1_8\n int v8; // r12d\n const char **v9; // r13\n const char *v10; // rdi\n double v11; // xmm1_8\n size_t v12; // rax\n __int64 v13; // rax\n double v14; // [rsp+0h] [rbp-B8h]\n double v15; // [rsp+0h] [rbp-B8h]\n _BYTE v17[104]; // [rsp+10h] [rbp-A8h] BYREF\n unsigned __int64 v18; // [rsp+78h] [rbp-40h]\n\n v18 = __readfsqword(0x28u);\n strcpy(res_1, \"[\");\n if ( a2 > 0 )\n {\n v2 = a1;\n if ( a2 - 2 <= 0 )\n {\n v3 = 0LL;\n do\n {\nLABEL_4:\n v4 = strtod(v2[v3], 0LL);\n v5 = v2[v3 + 1];\n v3 += 2LL;\n v14 = v4;\n v6 = strtod(v5, 0LL);\n __snprintf_chk(v17, 100LL, 2LL, 100LL, \"(%.2f, %.2f)\", v14, v6);\n __strcat_chk(res_1, v17, 1000LL);\n }\n while ( a2 > (int)v3 );\n goto LABEL_5;\n }\n v8 = 0;\n v9 = a1;\n do\n {\n v10 = *v9;\n v8 += 2;\n v9 += 2;\n v15 = strtod(v10, 0LL);\n v11 = strtod(*(v9 - 1), 0LL);\n __snprintf_chk(v17, 100LL, 2LL, 100LL, \"(%.2f, %.2f)\", v15, v11);\n v12 = strlen(res_1);\n v13 = __stpcpy_chk(&res_1[v12], v17, 1000LL);\n __memcpy_chk(v13, \", \", 3LL, (char *)&end - v13);\n }\n while ( v8 < a2 - 2 );\n v3 = v8;\n v2 = a1;\n if ( a2 > (int)v3 )\n goto LABEL_4;\n }\nLABEL_5:\n __strcat_chk(res_1, &unk_2004, 1000LL);\n return res_1;\n}", + "ida_strip_asm": "sub_14B0:\nendbr64\npush r15\nmov eax, 5Bh ; '['\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 88h\nmov rdx, fs:28h\nmov [rsp+0B8h+var_40], rdx\nxor edx, edx\nmov cs:s, ax\ntest esi, esi\njle loc_1678\nlea edx, [rsi-2]\nmov r12, rdi\nmov r14d, esi\ntest edx, edx\njg loc_15B0\nxor r13d, r13d\nlea rbp, s\nlea rbx, [rsp+0B8h+var_A8]\nloc_1509:\nlea r15, a2f2f; \"(%.2f, %.2f)\"\nloc_1510:\nmov rdi, [r12+r13*8]; nptr\nxor esi, esi; endptr\ncall _strtod\nmov rdi, [r12+r13*8+8]; nptr\nxor esi, esi; endptr\nadd r13, 2\nmovsd [rsp+0B8h+var_B8], xmm0\ncall _strtod\nmov r8, r15\nmov ecx, 64h ; 'd'\nmov rdi, rbx\nmovapd xmm1, xmm0\nmovsd xmm0, [rsp+0B8h+var_B8]\nmov edx, 2\nmov esi, 64h ; 'd'\nmov eax, 2\ncall ___snprintf_chk\nmov edx, 3E8h\nmov rsi, rbx\nmov rdi, rbp\ncall ___strcat_chk\ncmp r14d, r13d\njg short loc_1510\nloc_156D:\nmov edx, 3E8h\nlea rsi, unk_2004\nmov rdi, rbp\ncall ___strcat_chk\nmov rax, [rsp+0B8h+var_40]\nsub rax, fs:28h\njnz loc_1684\nadd rsp, 88h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15B0:\nmov [rsp+0B8h+var_B0], rdi\nxor r13d, r13d\nlea rbx, [rsp+0B8h+var_A8]\nmov r15d, edx\nmov r12d, r13d\nlea rbp, s\nmov r13, rdi\nloc_15CD:\nmov rdi, [r13+0]; nptr\nxor esi, esi; endptr\nadd r12d, 2\nadd r13, 10h\ncall _strtod\nmov rdi, [r13-8]; nptr\nxor esi, esi; endptr\nmovsd [rsp+0B8h+var_B8], xmm0\ncall _strtod\nlea r8, a2f2f; \"(%.2f, %.2f)\"\nmov ecx, 64h ; 'd'\nmov rdi, rbx\nmovapd xmm1, xmm0\nmovsd xmm0, [rsp+0B8h+var_B8]\nmov edx, 2\nmov esi, 64h ; 'd'\nmov eax, 2\ncall ___snprintf_chk\nmov rdi, rbp; s\ncall _strlen\nmov edx, 3E8h\nmov rsi, rbx\nlea rdi, [rbp+rax+0]\ncall ___stpcpy_chk\nlea rcx, __strcat_chk\nmov edx, 3\nlea rsi, asc_2013; \", \"\nmov rdi, rax\nsub rcx, rax\ncall ___memcpy_chk\ncmp r12d, r15d\njl loc_15CD\nmovsxd r13, r12d\nmov r12, [rsp+0B8h+var_B0]\ncmp r14d, r13d\njg loc_1509\njmp loc_156D\nloc_1678:\nlea rbp, s\njmp loc_156D\nloc_1684:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_14B0(const char **a1, int a2)\n{\n const char **v2; // r12\n __int64 v3; // r13\n double v4; // xmm0_8\n const char *v5; // rdi\n double v6; // xmm1_8\n int v8; // r12d\n const char **v9; // r13\n const char *v10; // rdi\n double v11; // xmm1_8\n size_t v12; // rax\n __int64 v13; // rax\n double v14; // [rsp+0h] [rbp-B8h]\n double v15; // [rsp+0h] [rbp-B8h]\n _BYTE v17[104]; // [rsp+10h] [rbp-A8h] BYREF\n unsigned __int64 v18; // [rsp+78h] [rbp-40h]\n\n v18 = __readfsqword(0x28u);\n strcpy(s, \"[\");\n if ( a2 > 0 )\n {\n v2 = a1;\n if ( a2 - 2 <= 0 )\n {\n v3 = 0LL;\n do\n {\nLABEL_4:\n v4 = strtod(v2[v3], 0LL);\n v5 = v2[v3 + 1];\n v3 += 2LL;\n v14 = v4;\n v6 = strtod(v5, 0LL);\n __snprintf_chk(v17, 100LL, 2LL, 100LL, \"(%.2f, %.2f)\", v14, v6);\n __strcat_chk(s, v17, 1000LL);\n }\n while ( a2 > (int)v3 );\n goto LABEL_5;\n }\n v8 = 0;\n v9 = a1;\n do\n {\n v10 = *v9;\n v8 += 2;\n v9 += 2;\n v15 = strtod(v10, 0LL);\n v11 = strtod(*(v9 - 1), 0LL);\n __snprintf_chk(v17, 100LL, 2LL, 100LL, \"(%.2f, %.2f)\", v15, v11);\n v12 = strlen(s);\n v13 = __stpcpy_chk(&s[v12], v17, 1000LL);\n __memcpy_chk(v13, \", \", 3LL, (char *)&_strcat_chk - v13);\n }\n while ( v8 < a2 - 2 );\n v3 = v8;\n v2 = a1;\n if ( a2 > (int)v3 )\n goto LABEL_4;\n }\nLABEL_5:\n __strcat_chk(s, &unk_2004, 1000LL);\n return s;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_14B0(const char **a1, int a2) {\n const char **v2;\n long long v3;\n double v4;\n const char *v5;\n double v6;\n int v8;\n const char **v9;\n const char *v10;\n double v11;\n unsigned int v12;\n long long v13;\n double v14;\n double v15;\n uint8_t v17[104];\n unsigned long long v18;\n v18 = __readfsqword(40u);\n strcpy(s, \"[\");\n if (a2 > 0) {\n v2 = a1;\n if (a2 - 2 <= 0) {\n v3 = 0LL;\n do {\n LABEL_4:\n v4 = strtod(v2[v3], 0LL);\n v5 = v2[v3 + 1];\n v3 += 2LL;\n v14 = v4;\n v6 = strtod(v5, 0LL);\n __snprintf_chk(v17, 100LL, 2LL, 100LL, \"(%.2f, %.2f)\", v14, v6);\n __strcat_chk(s, v17, 1000LL);\n } while (a2 > (int)v3);\n goto LABEL_5;\n }\n v8 = 0;\n v9 = a1;\n do {\n v10 = *v9;\n v8 += 2;\n v9 += 2;\n v15 = strtod(v10, 0LL);\n v11 = strtod(*(v9 - 1), 0LL);\n __snprintf_chk(v17, 100LL, 2LL, 100LL, \"(%.2f, %.2f)\", v15, v11);\n v12 = strlen(s);\n v13 = __stpcpy_chk(&s[v12], v17, 1000LL);\n __memcpy_chk(v13, \", \", 3LL, (char *)&_strcat_chk - v13);\n } while (v8 < a2 - 2);\n v3 = v8;\n v2 = a1;\n if (a2 > (int)v3) goto LABEL_4;\n }\nLABEL_5:\n __strcat_chk(s, &unk_2004, 1000LL);\n return s;\n}", + "ida_pseudo_norm": "char *func0(const char **a1, int a2) {\n const char **v2;\n long long v3;\n double v4;\n const char *v5;\n double v6;\n int v8;\n const char **v9;\n const char *v10;\n double v11;\n unsigned int v12;\n long long v13;\n double v14;\n double v15;\n uint8_t v17[104];\n unsigned long long v18;\n v18 = __readfsqword(40u);\n strcpy(res_1, \"[\");\n if (a2 > 0) {\n v2 = a1;\n if (a2 - 2 <= 0) {\n v3 = 0LL;\n do {\n LABEL_4:\n v4 = strtod(v2[v3], 0LL);\n v5 = v2[v3 + 1];\n v3 += 2LL;\n v14 = v4;\n v6 = strtod(v5, 0LL);\n __snprintf_chk(v17, 100LL, 2LL, 100LL, \"(%.2f, %.2f)\", v14, v6);\n __strcat_chk(res_1, v17, 1000LL);\n } while (a2 > (int)v3);\n goto LABEL_5;\n }\n v8 = 0;\n v9 = a1;\n do {\n v10 = *v9;\n v8 += 2;\n v9 += 2;\n v15 = strtod(v10, 0LL);\n v11 = strtod(*(v9 - 1), 0LL);\n __snprintf_chk(v17, 100LL, 2LL, 100LL, \"(%.2f, %.2f)\", v15, v11);\n v12 = strlen(res_1);\n v13 = __stpcpy_chk(&res_1[v12], v17, 1000LL);\n __memcpy_chk(v13, \", \", 3LL, (char *)&end - v13);\n } while (v8 < a2 - 2);\n v3 = v8;\n v2 = a1;\n if (a2 > (int)v3) goto LABEL_4;\n }\nLABEL_5:\n __strcat_chk(res_1, &unk_2004, 1000LL);\n return res_1;\n}" + }, + { + "index": 118, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(const char* string) {\n int count = 1;\n for (const char* ptr = string; *ptr; ptr++) {\n if (*ptr == ' ') {\n count++;\n }\n }\n char** list = malloc((count + 1) * sizeof(char*));\n if (!list) {\n return NULL;\n }\n char* str = strdup(string);\n if (!str) {\n free(list);\n return NULL;\n }\n int index = 0;\n char* token = strtok(str, \" \");\n while (token != NULL) {\n list[index++] = strdup(token);\n token = strtok(NULL, \" \");\n }\n list[index] = NULL;\n free(str);\n return list;\n}", + "test": "int main() {\n\n // First test case\n\n char** result1 = func0(\"python programming\");\n\n assert(strcmp(result1[0], \"python\") == 0);\n\n assert(strcmp(result1[1], \"programming\") == 0);\n\n assert(result1[2] == NULL);\n\n // Free memory\n\n free(result1[0]);\n\n free(result1[1]);\n\n free(result1);\n\n\n\n // Second test case\n\n char** result2 = func0(\"lists tuples strings\");\n\n assert(strcmp(result2[0], \"lists\") == 0);\n\n assert(strcmp(result2[1], \"tuples\") == 0);\n\n assert(strcmp(result2[2], \"strings\") == 0);\n\n assert(result2[3] == NULL);\n\n // Free memory\n\n free(result2[0]);\n\n free(result2[1]);\n\n free(result2[2]);\n\n free(result2);\n\n\n\n // Third test case\n\n char** result3 = func0(\"write a program\");\n\n assert(strcmp(result3[0], \"write\") == 0);\n\n assert(strcmp(result3[1], \"a\") == 0);\n\n assert(strcmp(result3[2], \"program\") == 0);\n\n assert(result3[3] == NULL);\n\n // Free memory\n\n free(result3[0]);\n\n free(result3[1]);\n\n free(result3[2]);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x48,%rsp\nmov %rdi,-0x48(%rbp)\nmovl $0x1,-0x38(%rbp)\nmov -0x48(%rbp),%rax\nmov %rax,-0x30(%rbp)\njmp 121f \nmov -0x30(%rbp),%rax\nmovzbl (%rax),%eax\ncmp $0x20,%al\njne 121a \naddl $0x1,-0x38(%rbp)\naddq $0x1,-0x30(%rbp)\nmov -0x30(%rbp),%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 120b \nmov -0x38(%rbp),%eax\nadd $0x1,%eax\ncltq\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,-0x20(%rbp)\ncmpq $0x0,-0x20(%rbp)\njne 1253 \nmov $0x0,%eax\njmpq 1311 \nmov -0x48(%rbp),%rax\nmov %rax,%rdi\ncallq 10f0 \nmov %rax,-0x18(%rbp)\ncmpq $0x0,-0x18(%rbp)\njne 1280 \nmov -0x20(%rbp),%rax\nmov %rax,%rdi\ncallq 10a0 \nmov $0x0,%eax\njmpq 1311 \nmovl $0x0,-0x34(%rbp)\nmov -0x18(%rbp),%rax\nlea 0xd76(%rip),%rsi\nmov %rax,%rdi\ncallq 10e0 \nmov %rax,-0x28(%rbp)\njmp 12df \nmov -0x34(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x34(%rbp)\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x20(%rbp),%rax\nlea (%rdx,%rax,1),%rbx\nmov -0x28(%rbp),%rax\nmov %rax,%rdi\ncallq 10f0 \nmov %rax,(%rbx)\nlea 0xd37(%rip),%rsi\nmov $0x0,%edi\ncallq 10e0 \nmov %rax,-0x28(%rbp)\ncmpq $0x0,-0x28(%rbp)\njne 12a0 \nmov -0x34(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmovq $0x0,(%rax)\nmov -0x18(%rbp),%rax\nmov %rax,%rdi\ncallq 10a0 \nmov -0x20(%rbp),%rax\nadd $0x48,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 48h\nmov [rbp+s], rdi\nmov [rbp+var_38], 1\nmov rax, [rbp+s]\nmov [rbp+var_30], rax\njmp short loc_121F\nloc_120B:\nmov rax, [rbp+var_30]\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njnz short loc_121A\nadd [rbp+var_38], 1\nloc_121A:\nadd [rbp+var_30], 1\nloc_121F:\nmov rax, [rbp+var_30]\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_120B\nmov eax, [rbp+var_38]\nadd eax, 1\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\ncmp [rbp+ptr], 0\njnz short loc_1253\nmov eax, 0\njmp loc_1317\nloc_1253:\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strdup\nmov [rbp+var_18], rax\ncmp [rbp+var_18], 0\njnz short loc_1280\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov eax, 0\njmp loc_1317\nloc_1280:\nmov [rbp+var_34], 0\nmov rax, [rbp+var_18]\nlea rdx, delim; \" \"\nmov rsi, rdx; delim\nmov rdi, rax; s\ncall _strtok\nmov [rbp+var_28], rax\njmp short loc_12E5\nloc_12A3:\nmov eax, [rbp+var_34]\nlea edx, [rax+1]\nmov [rbp+var_34], edx\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nlea rbx, [rdx+rax]\nmov rax, [rbp+var_28]\nmov rdi, rax; s\ncall _strdup\nmov [rbx], rax\nlea rax, delim; \" \"\nmov rsi, rax; delim\nmov edi, 0; s\ncall _strtok\nmov [rbp+var_28], rax\nloc_12E5:\ncmp [rbp+var_28], 0\njnz short loc_12A3\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov qword ptr [rax], 0\nmov rax, [rbp+var_18]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+ptr]\nloc_1317:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(const char *a1)\n{\n int v2; // eax\n int v3; // [rsp+18h] [rbp-38h]\n int v4; // [rsp+1Ch] [rbp-34h]\n const char *i; // [rsp+20h] [rbp-30h]\n const char *j; // [rsp+28h] [rbp-28h]\n _QWORD *ptr; // [rsp+30h] [rbp-20h]\n char *v8; // [rsp+38h] [rbp-18h]\n\n v3 = 1;\n for ( i = a1; *i; ++i )\n {\n if ( *i == 32 )\n ++v3;\n }\n ptr = malloc(8LL * (v3 + 1));\n if ( !ptr )\n return 0LL;\n v8 = strdup(a1);\n if ( v8 )\n {\n v4 = 0;\n for ( j = strtok(v8, \" \"); j; j = strtok(0LL, \" \") )\n {\n v2 = v4++;\n ptr[v2] = strdup(j);\n }\n ptr[v4] = 0LL;\n free(v8);\n return ptr;\n }\n else\n {\n free(ptr);\n return 0LL;\n }\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 48h\nmov [rbp+s], rdi\nmov [rbp+var_38], 1\nmov rax, [rbp+s]\nmov [rbp+var_30], rax\njmp short loc_121F\nloc_120B:\nmov rax, [rbp+var_30]\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njnz short loc_121A\nadd [rbp+var_38], 1\nloc_121A:\nadd [rbp+var_30], 1\nloc_121F:\nmov rax, [rbp+var_30]\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_120B\nmov eax, [rbp+var_38]\nadd eax, 1\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\ncmp [rbp+ptr], 0\njnz short loc_1253\nmov eax, 0\njmp loc_1317\nloc_1253:\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strdup\nmov [rbp+var_18], rax\ncmp [rbp+var_18], 0\njnz short loc_1280\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov eax, 0\njmp loc_1317\nloc_1280:\nmov [rbp+var_34], 0\nmov rax, [rbp+var_18]\nlea rdx, delim; \" \"\nmov rsi, rdx; delim\nmov rdi, rax; s\ncall _strtok\nmov [rbp+var_28], rax\njmp short loc_12E5\nloc_12A3:\nmov eax, [rbp+var_34]\nlea edx, [rax+1]\nmov [rbp+var_34], edx\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nlea rbx, [rdx+rax]\nmov rax, [rbp+var_28]\nmov rdi, rax; s\ncall _strdup\nmov [rbx], rax\nlea rax, delim; \" \"\nmov rsi, rax; delim\nmov edi, 0; s\ncall _strtok\nmov [rbp+var_28], rax\nloc_12E5:\ncmp [rbp+var_28], 0\njnz short loc_12A3\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov qword ptr [rax], 0\nmov rax, [rbp+var_18]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+ptr]\nloc_1317:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11E9(const char *a1)\n{\n int v2; // eax\n int v3; // [rsp+18h] [rbp-38h]\n int v4; // [rsp+1Ch] [rbp-34h]\n const char *i; // [rsp+20h] [rbp-30h]\n const char *j; // [rsp+28h] [rbp-28h]\n _QWORD *ptr; // [rsp+30h] [rbp-20h]\n char *v8; // [rsp+38h] [rbp-18h]\n\n v3 = 1;\n for ( i = a1; *i; ++i )\n {\n if ( *i == 32 )\n ++v3;\n }\n ptr = malloc(8LL * (v3 + 1));\n if ( !ptr )\n return 0LL;\n v8 = strdup(a1);\n if ( v8 )\n {\n v4 = 0;\n for ( j = strtok(v8, \" \"); j; j = strtok(0LL, \" \") )\n {\n v2 = v4++;\n ptr[v2] = strdup(j);\n }\n ptr[v4] = 0LL;\n free(v8);\n return ptr;\n }\n else\n {\n free(ptr);\n return 0LL;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11E9(const char *a1) {\n int v2;\n int v3;\n int v4;\n const char *i;\n const char *j;\n uint64_t *ptr;\n char *v8;\n v3 = 1;\n for (i = a1; *i; ++i) {\n if (*i == 32) ++v3;\n }\n ptr = malloc(8LL * (v3 + 1));\n if (!ptr) return 0LL;\n v8 = strdup(a1);\n if (v8) {\n v4 = 0;\n for (j = strtok(v8, \" \"); j; j = strtok(0LL, \" \")) {\n v2 = v4++;\n ptr[v2] = strdup(j);\n }\n ptr[v4] = 0LL;\n free(v8);\n return ptr;\n } else {\n free(ptr);\n return 0LL;\n }\n}", + "ida_pseudo_norm": "uint64_t *func0(const char *a1) {\n int v2;\n int v3;\n int v4;\n const char *i;\n const char *j;\n uint64_t *ptr;\n char *v8;\n v3 = 1;\n for (i = a1; *i; ++i) {\n if (*i == 32) ++v3;\n }\n ptr = malloc(8LL * (v3 + 1));\n if (!ptr) return 0LL;\n v8 = strdup(a1);\n if (v8) {\n v4 = 0;\n for (j = strtok(v8, \" \"); j; j = strtok(0LL, \" \")) {\n v2 = v4++;\n ptr[v2] = strdup(j);\n }\n ptr[v4] = 0LL;\n free(v8);\n return ptr;\n } else {\n free(ptr);\n return 0LL;\n }\n}" + }, + { + "index": 118, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(const char* string) {\n int count = 1;\n for (const char* ptr = string; *ptr; ptr++) {\n if (*ptr == ' ') {\n count++;\n }\n }\n char** list = malloc((count + 1) * sizeof(char*));\n if (!list) {\n return NULL;\n }\n char* str = strdup(string);\n if (!str) {\n free(list);\n return NULL;\n }\n int index = 0;\n char* token = strtok(str, \" \");\n while (token != NULL) {\n list[index++] = strdup(token);\n token = strtok(NULL, \" \");\n }\n list[index] = NULL;\n free(str);\n return list;\n}", + "test": "int main() {\n\n // First test case\n\n char** result1 = func0(\"python programming\");\n\n assert(strcmp(result1[0], \"python\") == 0);\n\n assert(strcmp(result1[1], \"programming\") == 0);\n\n assert(result1[2] == NULL);\n\n // Free memory\n\n free(result1[0]);\n\n free(result1[1]);\n\n free(result1);\n\n\n\n // Second test case\n\n char** result2 = func0(\"lists tuples strings\");\n\n assert(strcmp(result2[0], \"lists\") == 0);\n\n assert(strcmp(result2[1], \"tuples\") == 0);\n\n assert(strcmp(result2[2], \"strings\") == 0);\n\n assert(result2[3] == NULL);\n\n // Free memory\n\n free(result2[0]);\n\n free(result2[1]);\n\n free(result2[2]);\n\n free(result2);\n\n\n\n // Third test case\n\n char** result3 = func0(\"write a program\");\n\n assert(strcmp(result3[0], \"write\") == 0);\n\n assert(strcmp(result3[1], \"a\") == 0);\n\n assert(strcmp(result3[2], \"program\") == 0);\n\n assert(result3[3] == NULL);\n\n // Free memory\n\n free(result3[0]);\n\n free(result3[1]);\n\n free(result3[2]);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nmovzbl (%rdi),%eax\ntest %al,%al\nje 1290 \nmov %rdi,%rdx\nmov $0x1,%ecx\ncmp $0x20,%al\nsete %al\nmovzbl %al,%eax\nadd %eax,%ecx\nadd $0x1,%rdx\nmovzbl (%rdx),%eax\ntest %al,%al\njne 11eb \nlea 0x1(%rcx),%edi\nmovslq %edi,%rdi\nshl $0x3,%rdi\ncallq 10b0 \nmov %rax,%rbp\ntest %rax,%rax\nje 1284 \nmov %rbx,%rdi\ncallq 10d0 \nmov %rax,%r14\ntest %rax,%rax\nje 129a \nlea 0xdd6(%rip),%rsi\nmov %rax,%rdi\ncallq 10c0 \nmov %rax,%rdi\ntest %rax,%rax\nje 12a7 \nmov $0x1,%ebx\nlea 0xdba(%rip),%r13\nmov %ebx,%r12d\ncallq 10d0 \nmov %rax,-0x8(%rbp,%rbx,8)\nmov %r13,%rsi\nmov $0x0,%edi\ncallq 10c0 \nmov %rax,%rdi\nadd $0x1,%rbx\ntest %rax,%rax\njne 124a \nmovslq %r12d,%r12\nmovq $0x0,0x0(%rbp,%r12,8)\nmov %r14,%rdi\ncallq 1090 \nmov %rbp,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nmov $0x1,%ecx\njmpq 1200 \nmov %rbp,%rdi\ncallq 1090 \nmov %r14,%rbp\njmp 1284 \nmov $0x0,%r12d\njmp 1270 \n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmovzx eax, byte ptr [rdi]\ntest al, al\njz loc_12B3\nmov rdx, rdi\nmov ecx, 1\nloc_120D:\ncmp al, 20h ; ' '\nsetz al\nmovzx eax, al\nadd ecx, eax\nadd rdx, 1\nmovzx eax, byte ptr [rdx]\ntest al, al\njnz short loc_120D\nloc_1222:\nlea edi, [rcx+1]\nmovsxd rdi, edi\nshl rdi, 3; size\ncall _malloc\nmov rbp, rax\ntest rax, rax\njz short loc_12A5\nmov rdi, rbx; s\ncall _strdup\nmov r12, rax\ntest rax, rax\njz short loc_12BD\nlea rsi, delim; \" \"\nmov rdi, rax; s\ncall _strtok\nmov rdi, rax; s\ntest rax, rax\njz short loc_12CA\nmov ebx, 1\nlea r13, delim; \" \"\nloc_126C:\ncall _strdup\nmov [rbp+rbx*8-8], rax\nmov rsi, r13; delim\nmov edi, 0; s\ncall _strtok\nmov rdi, rax\nmov rax, rbx\nadd rbx, 1\ntest rdi, rdi\njnz short loc_126C\nloc_1292:\ncdqe\nmov qword ptr [rbp+rax*8+0], 0\nmov rdi, r12; ptr\ncall _free\nloc_12A5:\nmov rax, rbp\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_12B3:\nmov ecx, 1\njmp loc_1222\nloc_12BD:\nmov rdi, rbp; ptr\ncall _free\nmov rbp, r12\njmp short loc_12A5\nloc_12CA:\nmov eax, 0\njmp short loc_1292", + "ida_pseudo": "_QWORD *__fastcall func0(char *s)\n{\n char v1; // al\n char *v2; // rdx\n int v3; // ecx\n _QWORD *v4; // rbp\n char *v5; // rax\n char *v6; // r12\n char *v7; // rdi\n __int64 v8; // rbx\n int v9; // eax\n\n v1 = *s;\n if ( *s )\n {\n v2 = s;\n v3 = 1;\n do\n {\n v3 += v1 == 32;\n v1 = *++v2;\n }\n while ( *v2 );\n }\n else\n {\n v3 = 1;\n }\n v4 = malloc(8LL * (v3 + 1));\n if ( v4 )\n {\n v5 = strdup(s);\n v6 = v5;\n if ( v5 )\n {\n v7 = strtok(v5, \" \");\n if ( v7 )\n {\n v8 = 1LL;\n do\n {\n v4[v8 - 1] = strdup(v7);\n v7 = strtok(0LL, \" \");\n v9 = v8++;\n }\n while ( v7 );\n }\n else\n {\n v9 = 0;\n }\n v4[v9] = 0LL;\n free(v6);\n }\n else\n {\n free(v4);\n return 0LL;\n }\n }\n return v4;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmovzx eax, byte ptr [rdi]\ntest al, al\njz loc_12B3\nmov rdx, rdi\nmov ecx, 1\nloc_120D:\ncmp al, 20h ; ' '\nsetz al\nmovzx eax, al\nadd ecx, eax\nadd rdx, 1\nmovzx eax, byte ptr [rdx]\ntest al, al\njnz short loc_120D\nloc_1222:\nlea edi, [rcx+1]\nmovsxd rdi, edi\nshl rdi, 3; size\ncall _malloc\nmov rbp, rax\ntest rax, rax\njz short loc_12A5\nmov rdi, rbx; s\ncall _strdup\nmov r12, rax\ntest rax, rax\njz short loc_12BD\nlea rsi, delim; \" \"\nmov rdi, rax; s\ncall _strtok\nmov rdi, rax; s\ntest rax, rax\njz short loc_12CA\nmov ebx, 1\nlea r13, delim; \" \"\nloc_126C:\ncall _strdup\nmov [rbp+rbx*8-8], rax\nmov rsi, r13; delim\nmov edi, 0; s\ncall _strtok\nmov rdi, rax\nmov rax, rbx\nadd rbx, 1\ntest rdi, rdi\njnz short loc_126C\nloc_1292:\ncdqe\nmov qword ptr [rbp+rax*8+0], 0\nmov rdi, r12; ptr\ncall _free\nloc_12A5:\nmov rax, rbp\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_12B3:\nmov ecx, 1\njmp loc_1222\nloc_12BD:\nmov rdi, rbp; ptr\ncall _free\nmov rbp, r12\njmp short loc_12A5\nloc_12CA:\nmov eax, 0\njmp short loc_1292", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11E9(char *s)\n{\n char v1; // al\n char *v2; // rdx\n int v3; // ecx\n _QWORD *v4; // rbp\n char *v5; // rax\n char *v6; // r12\n char *v7; // rdi\n __int64 v8; // rbx\n int v9; // eax\n\n v1 = *s;\n if ( *s )\n {\n v2 = s;\n v3 = 1;\n do\n {\n v3 += v1 == 32;\n v1 = *++v2;\n }\n while ( *v2 );\n }\n else\n {\n v3 = 1;\n }\n v4 = malloc(8LL * (v3 + 1));\n if ( v4 )\n {\n v5 = strdup(s);\n v6 = v5;\n if ( v5 )\n {\n v7 = strtok(v5, \" \");\n if ( v7 )\n {\n v8 = 1LL;\n do\n {\n v4[v8 - 1] = strdup(v7);\n v7 = strtok(0LL, \" \");\n v9 = v8++;\n }\n while ( v7 );\n }\n else\n {\n v9 = 0;\n }\n v4[v9] = 0LL;\n free(v6);\n }\n else\n {\n free(v4);\n return 0LL;\n }\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11E9(char *s) {\n char v1;\n char *v2;\n int v3;\n uint64_t *v4;\n char *v5;\n char *v6;\n char *v7;\n long long v8;\n int v9;\n v1 = *s;\n if (*s) {\n v2 = s;\n v3 = 1;\n do {\n v3 += v1 == 32;\n v1 = *++v2;\n } while (*v2);\n } else {\n v3 = 1;\n }\n v4 = malloc(8LL * (v3 + 1));\n if (v4) {\n v5 = strdup(s);\n v6 = v5;\n if (v5) {\n v7 = strtok(v5, \" \");\n if (v7) {\n v8 = 1LL;\n do {\n v4[v8 - 1] = strdup(v7);\n v7 = strtok(0LL, \" \");\n v9 = v8++;\n } while (v7);\n } else {\n v9 = 0;\n }\n v4[v9] = 0LL;\n free(v6);\n } else {\n free(v4);\n return 0LL;\n }\n }\n return v4;\n}", + "ida_pseudo_norm": "uint64_t *func0(char *s) {\n char v1;\n char *v2;\n int v3;\n uint64_t *v4;\n char *v5;\n char *v6;\n char *v7;\n long long v8;\n int v9;\n v1 = *s;\n if (*s) {\n v2 = s;\n v3 = 1;\n do {\n v3 += v1 == 32;\n v1 = *++v2;\n } while (*v2);\n } else {\n v3 = 1;\n }\n v4 = malloc(8LL * (v3 + 1));\n if (v4) {\n v5 = strdup(s);\n v6 = v5;\n if (v5) {\n v7 = strtok(v5, \" \");\n if (v7) {\n v8 = 1LL;\n do {\n v4[v8 - 1] = strdup(v7);\n v7 = strtok(0LL, \" \");\n v9 = v8++;\n } while (v7);\n } else {\n v9 = 0;\n }\n v4[v9] = 0LL;\n free(v6);\n } else {\n free(v4);\n return 0LL;\n }\n }\n return v4;\n}" + }, + { + "index": 118, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(const char* string) {\n int count = 1;\n for (const char* ptr = string; *ptr; ptr++) {\n if (*ptr == ' ') {\n count++;\n }\n }\n char** list = malloc((count + 1) * sizeof(char*));\n if (!list) {\n return NULL;\n }\n char* str = strdup(string);\n if (!str) {\n free(list);\n return NULL;\n }\n int index = 0;\n char* token = strtok(str, \" \");\n while (token != NULL) {\n list[index++] = strdup(token);\n token = strtok(NULL, \" \");\n }\n list[index] = NULL;\n free(str);\n return list;\n}", + "test": "int main() {\n\n // First test case\n\n char** result1 = func0(\"python programming\");\n\n assert(strcmp(result1[0], \"python\") == 0);\n\n assert(strcmp(result1[1], \"programming\") == 0);\n\n assert(result1[2] == NULL);\n\n // Free memory\n\n free(result1[0]);\n\n free(result1[1]);\n\n free(result1);\n\n\n\n // Second test case\n\n char** result2 = func0(\"lists tuples strings\");\n\n assert(strcmp(result2[0], \"lists\") == 0);\n\n assert(strcmp(result2[1], \"tuples\") == 0);\n\n assert(strcmp(result2[2], \"strings\") == 0);\n\n assert(result2[3] == NULL);\n\n // Free memory\n\n free(result2[0]);\n\n free(result2[1]);\n\n free(result2[2]);\n\n free(result2);\n\n\n\n // Third test case\n\n char** result3 = func0(\"write a program\");\n\n assert(strcmp(result3[0], \"write\") == 0);\n\n assert(strcmp(result3[1], \"a\") == 0);\n\n assert(strcmp(result3[2], \"program\") == 0);\n\n assert(result3[3] == NULL);\n\n // Free memory\n\n free(result3[0]);\n\n free(result3[1]);\n\n free(result3[2]);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\nmov %rdi,%rbp\npush %rbx\nmovzbl (%rdi),%eax\ntest %al,%al\nje 15a8 \nmov %rdi,%rdx\nmov $0x1,%ecx\nnopw 0x0(%rax,%rax,1)\nlea 0x1(%rcx),%edi\ncmp $0x20,%al\njne 1506 \nlea 0x2(%rcx),%eax\nmov %edi,%ecx\nmov %eax,%edi\nmovzbl 0x1(%rdx),%eax\nadd $0x1,%rdx\ntest %al,%al\njne 14f8 \nmovslq %edi,%rdi\nshl $0x3,%rdi\ncallq 10b0 \nmov %rax,%r12\ntest %rax,%rax\nje 1596 \nmov %rbp,%rdi\ncallq 10d0 \nmov %rax,%r14\ntest %rax,%rax\nje 15bd \nmov %rax,%rdi\nlea 0xac0(%rip),%rsi\ncallq 10c0 \nmov %rax,%rdi\ntest %rax,%rax\nje 15b8 \nmov $0x1,%ebx\nlea 0xaa7(%rip),%r13\nnopl (%rax)\ncallq 10d0 \nxor %edi,%edi\nmov %r13,%rsi\nmovslq %ebx,%rbp\nmov %rax,-0x8(%r12,%rbx,8)\nadd $0x1,%rbx\ncallq 10c0 \nmov %rax,%rdi\ntest %rax,%rax\njne 1560 \nlea (%r12,%rbp,8),%rax\nmovq $0x0,(%rax)\nmov %r14,%rdi\ncallq 1090 \npop %rbx\nmov %r12,%rax\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopw 0x0(%rax,%rax,1)\nmov $0x10,%edi\njmpq 1519 \nnopw 0x0(%rax,%rax,1)\nmov %r12,%rax\njmp 1587 \nmov %r12,%rdi\nxor %r12d,%r12d\ncallq 1090 \njmp 1596 \nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 8\nmovzx eax, byte ptr [rdi]\ntest al, al\njz loc_15A0\nmov rdx, rdi\nmov ecx, 1\nnop dword ptr [rax+00h]\nloc_14E8:\ncmp al, 20h ; ' '\nsetz al\nadd rdx, 1\nmovzx eax, al\nadd ecx, eax\nmovzx eax, byte ptr [rdx]\ntest al, al\njnz short loc_14E8\nlea edi, [rcx+1]\nmovsxd rdi, edi\nshl rdi, 3; size\nloc_1507:\ncall _malloc\nmov rbx, rax\ntest rax, rax\njz loc_15BD\nmov rdi, rbp; s\ncall _strdup\nmov r12, rax\ntest rax, rax\njz loc_15B5\nlea rbp, delim; \" \"\nmov rdi, rax; s\nmov rsi, rbp; delim\ncall _strtok\nmov rdi, rax; s\ntest rax, rax\njz short loc_15B0\nmov r13d, 1\nnop dword ptr [rax+00h]\nloc_1550:\ncall _strdup\nxor edi, edi; s\nmov rsi, rbp; delim\nmov [rbx+r13*8-8], rax\ncall _strtok\nmov rdi, rax\nmov rax, r13\nadd r13, 1\ntest rdi, rdi\njnz short loc_1550\ncdqe\nlea rax, [rbx+rax*8]\nloc_1579:\nmov qword ptr [rax], 0\nmov rdi, r12; ptr\ncall _free\nloc_1588:\nadd rsp, 8\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_15A0:\nmov edi, 10h\njmp loc_1507\nloc_15B0:\nmov rax, rbx\njmp short loc_1579\nloc_15B5:\nmov rdi, rbx; ptr\ncall _free\nloc_15BD:\nxor ebx, ebx\njmp short loc_1588", + "ida_pseudo": "char *__fastcall func0(char *s)\n{\n char v2; // al\n char *v3; // rdx\n int v4; // ecx\n size_t v5; // rdi\n char *v6; // rbx\n char *v7; // rax\n char *v8; // r12\n char *v9; // rdi\n __int64 v10; // r13\n int v11; // eax\n char *v12; // rax\n\n v2 = *s;\n if ( *s )\n {\n v3 = s;\n v4 = 1;\n do\n {\n ++v3;\n v4 += v2 == 32;\n v2 = *v3;\n }\n while ( *v3 );\n v5 = 8LL * (v4 + 1);\n }\n else\n {\n v5 = 16LL;\n }\n v6 = (char *)malloc(v5);\n if ( !v6 )\n return 0LL;\n v7 = strdup(s);\n v8 = v7;\n if ( !v7 )\n {\n free(v6);\n return 0LL;\n }\n v9 = strtok(v7, \" \");\n if ( v9 )\n {\n v10 = 1LL;\n do\n {\n *(_QWORD *)&v6[8 * v10 - 8] = strdup(v9);\n v9 = strtok(0LL, \" \");\n v11 = v10++;\n }\n while ( v9 );\n v12 = &v6[8 * v11];\n }\n else\n {\n v12 = v6;\n }\n *(_QWORD *)v12 = 0LL;\n free(v8);\n return v6;\n}", + "ida_strip_asm": "sub_14C0:\nendbr64\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 8\nmovzx eax, byte ptr [rdi]\ntest al, al\njz loc_15A0\nmov rdx, rdi\nmov ecx, 1\nnop dword ptr [rax+00h]\nloc_14E8:\ncmp al, 20h ; ' '\nsetz al\nadd rdx, 1\nmovzx eax, al\nadd ecx, eax\nmovzx eax, byte ptr [rdx]\ntest al, al\njnz short loc_14E8\nlea edi, [rcx+1]\nmovsxd rdi, edi\nshl rdi, 3; size\nloc_1507:\ncall _malloc\nmov rbx, rax\ntest rax, rax\njz loc_15BD\nmov rdi, rbp; s\ncall _strdup\nmov r12, rax\ntest rax, rax\njz loc_15B5\nlea rbp, delim; \" \"\nmov rdi, rax; s\nmov rsi, rbp; delim\ncall _strtok\nmov rdi, rax; s\ntest rax, rax\njz short loc_15B0\nmov r13d, 1\nnop dword ptr [rax+00h]\nloc_1550:\ncall _strdup\nxor edi, edi; s\nmov rsi, rbp; delim\nmov [rbx+r13*8-8], rax\ncall _strtok\nmov rdi, rax\nmov rax, r13\nadd r13, 1\ntest rdi, rdi\njnz short loc_1550\ncdqe\nlea rax, [rbx+rax*8]\nloc_1579:\nmov qword ptr [rax], 0\nmov rdi, r12; ptr\ncall _free\nloc_1588:\nadd rsp, 8\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_15A0:\nmov edi, 10h\njmp loc_1507\nloc_15B0:\nmov rax, rbx\njmp short loc_1579\nloc_15B5:\nmov rdi, rbx; ptr\ncall _free\nloc_15BD:\nxor ebx, ebx\njmp short loc_1588", + "ida_strip_pseudo": "char *__fastcall sub_14C0(char *s)\n{\n char v2; // al\n char *v3; // rdx\n int v4; // ecx\n size_t v5; // rdi\n char *v6; // rbx\n char *v7; // rax\n char *v8; // r12\n char *v9; // rdi\n __int64 v10; // r13\n int v11; // eax\n char *v12; // rax\n\n v2 = *s;\n if ( *s )\n {\n v3 = s;\n v4 = 1;\n do\n {\n ++v3;\n v4 += v2 == 32;\n v2 = *v3;\n }\n while ( *v3 );\n v5 = 8LL * (v4 + 1);\n }\n else\n {\n v5 = 16LL;\n }\n v6 = (char *)malloc(v5);\n if ( !v6 )\n return 0LL;\n v7 = strdup(s);\n v8 = v7;\n if ( !v7 )\n {\n free(v6);\n return 0LL;\n }\n v9 = strtok(v7, \" \");\n if ( v9 )\n {\n v10 = 1LL;\n do\n {\n *(_QWORD *)&v6[8 * v10 - 8] = strdup(v9);\n v9 = strtok(0LL, \" \");\n v11 = v10++;\n }\n while ( v9 );\n v12 = &v6[8 * v11];\n }\n else\n {\n v12 = v6;\n }\n *(_QWORD *)v12 = 0LL;\n free(v8);\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_14C0(char *s) {\n char v2;\n char *v3;\n int v4;\n unsigned int v5;\n char *v6;\n char *v7;\n char *v8;\n char *v9;\n long long v10;\n int v11;\n char *v12;\n v2 = *s;\n if (*s) {\n v3 = s;\n v4 = 1;\n do {\n ++v3;\n v4 += v2 == 32;\n v2 = *v3;\n } while (*v3);\n v5 = 8LL * (v4 + 1);\n } else {\n v5 = 16LL;\n }\n v6 = (char *)malloc(v5);\n if (!v6) return 0LL;\n v7 = strdup(s);\n v8 = v7;\n if (!v7) {\n free(v6);\n return 0LL;\n }\n v9 = strtok(v7, \" \");\n if (v9) {\n v10 = 1LL;\n do {\n *(uint64_t *)&v6[8 * v10 - 8] = strdup(v9);\n v9 = strtok(0LL, \" \");\n v11 = v10++;\n } while (v9);\n v12 = &v6[8 * v11];\n } else {\n v12 = v6;\n }\n *(uint64_t *)v12 = 0LL;\n free(v8);\n return v6;\n}", + "ida_pseudo_norm": "char *func0(char *s) {\n char v2;\n char *v3;\n int v4;\n unsigned int v5;\n char *v6;\n char *v7;\n char *v8;\n char *v9;\n long long v10;\n int v11;\n char *v12;\n v2 = *s;\n if (*s) {\n v3 = s;\n v4 = 1;\n do {\n ++v3;\n v4 += v2 == 32;\n v2 = *v3;\n } while (*v3);\n v5 = 8LL * (v4 + 1);\n } else {\n v5 = 16LL;\n }\n v6 = (char *)malloc(v5);\n if (!v6) return 0LL;\n v7 = strdup(s);\n v8 = v7;\n if (!v7) {\n free(v6);\n return 0LL;\n }\n v9 = strtok(v7, \" \");\n if (v9) {\n v10 = 1LL;\n do {\n *(uint64_t *)&v6[8 * v10 - 8] = strdup(v9);\n v9 = strtok(0LL, \" \");\n v11 = v10++;\n } while (v9);\n v12 = &v6[8 * v11];\n } else {\n v12 = v6;\n }\n *(uint64_t *)v12 = 0LL;\n free(v8);\n return v6;\n}" + }, + { + "index": 118, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(const char* string) {\n int count = 1;\n for (const char* ptr = string; *ptr; ptr++) {\n if (*ptr == ' ') {\n count++;\n }\n }\n char** list = malloc((count + 1) * sizeof(char*));\n if (!list) {\n return NULL;\n }\n char* str = strdup(string);\n if (!str) {\n free(list);\n return NULL;\n }\n int index = 0;\n char* token = strtok(str, \" \");\n while (token != NULL) {\n list[index++] = strdup(token);\n token = strtok(NULL, \" \");\n }\n list[index] = NULL;\n free(str);\n return list;\n}", + "test": "int main() {\n\n // First test case\n\n char** result1 = func0(\"python programming\");\n\n assert(strcmp(result1[0], \"python\") == 0);\n\n assert(strcmp(result1[1], \"programming\") == 0);\n\n assert(result1[2] == NULL);\n\n // Free memory\n\n free(result1[0]);\n\n free(result1[1]);\n\n free(result1);\n\n\n\n // Second test case\n\n char** result2 = func0(\"lists tuples strings\");\n\n assert(strcmp(result2[0], \"lists\") == 0);\n\n assert(strcmp(result2[1], \"tuples\") == 0);\n\n assert(strcmp(result2[2], \"strings\") == 0);\n\n assert(result2[3] == NULL);\n\n // Free memory\n\n free(result2[0]);\n\n free(result2[1]);\n\n free(result2[2]);\n\n free(result2);\n\n\n\n // Third test case\n\n char** result3 = func0(\"write a program\");\n\n assert(strcmp(result3[0], \"write\") == 0);\n\n assert(strcmp(result3[1], \"a\") == 0);\n\n assert(strcmp(result3[2], \"program\") == 0);\n\n assert(result3[3] == NULL);\n\n // Free memory\n\n free(result3[0]);\n\n free(result3[1]);\n\n free(result3[2]);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\nmov %rdi,%rbp\npush %rbx\nmovzbl (%rdi),%eax\ntest %al,%al\nje 15a8 \nmov %rdi,%rdx\nmov $0x1,%ecx\nnopw 0x0(%rax,%rax,1)\nlea 0x1(%rcx),%edi\ncmp $0x20,%al\njne 1506 \nlea 0x2(%rcx),%eax\nmov %edi,%ecx\nmov %eax,%edi\nmovzbl 0x1(%rdx),%eax\nadd $0x1,%rdx\ntest %al,%al\njne 14f8 \nmovslq %edi,%rdi\nshl $0x3,%rdi\ncallq 10b0 \nmov %rax,%r12\ntest %rax,%rax\nje 1596 \nmov %rbp,%rdi\ncallq 10d0 \nmov %rax,%r14\ntest %rax,%rax\nje 15bd \nmov %rax,%rdi\nlea 0xac0(%rip),%rsi\ncallq 10c0 \nmov %rax,%rdi\ntest %rax,%rax\nje 15b8 \nmov $0x1,%ebx\nlea 0xaa7(%rip),%r13\nnopl (%rax)\ncallq 10d0 \nxor %edi,%edi\nmov %r13,%rsi\nmovslq %ebx,%rbp\nmov %rax,-0x8(%r12,%rbx,8)\nadd $0x1,%rbx\ncallq 10c0 \nmov %rax,%rdi\ntest %rax,%rax\njne 1560 \nlea (%r12,%rbp,8),%rax\nmovq $0x0,(%rax)\nmov %r14,%rdi\ncallq 1090 \npop %rbx\nmov %r12,%rax\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopw 0x0(%rax,%rax,1)\nmov $0x10,%edi\njmpq 1519 \nnopw 0x0(%rax,%rax,1)\nmov %r12,%rax\njmp 1587 \nmov %r12,%rdi\nxor %r12d,%r12d\ncallq 1090 \njmp 1596 \nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 8\nmovzx eax, byte ptr [rdi]\ntest al, al\njz loc_15A0\nmov rdx, rdi\nmov ecx, 1\nnop dword ptr [rax+00h]\nloc_14E8:\ncmp al, 20h ; ' '\nsetz al\nadd rdx, 1\nmovzx eax, al\nadd ecx, eax\nmovzx eax, byte ptr [rdx]\ntest al, al\njnz short loc_14E8\nlea edi, [rcx+1]\nmovsxd rdi, edi\nshl rdi, 3; size\nloc_1507:\ncall _malloc\nmov rbx, rax\ntest rax, rax\njz loc_15BD\nmov rdi, rbp; s\ncall _strdup\nmov r12, rax\ntest rax, rax\njz loc_15B5\nlea rbp, delim; \" \"\nmov rdi, rax; s\nmov rsi, rbp; delim\ncall _strtok\nmov rdi, rax; s\ntest rax, rax\njz short loc_15B0\nmov r13d, 1\nnop dword ptr [rax+00h]\nloc_1550:\ncall _strdup\nxor edi, edi; s\nmov rsi, rbp; delim\nmov [rbx+r13*8-8], rax\ncall _strtok\nmov rdi, rax\nmov rax, r13\nadd r13, 1\ntest rdi, rdi\njnz short loc_1550\ncdqe\nlea rax, [rbx+rax*8]\nloc_1579:\nmov qword ptr [rax], 0\nmov rdi, r12; ptr\ncall _free\nloc_1588:\nadd rsp, 8\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_15A0:\nmov edi, 10h\njmp loc_1507\nloc_15B0:\nmov rax, rbx\njmp short loc_1579\nloc_15B5:\nmov rdi, rbx; ptr\ncall _free\nloc_15BD:\nxor ebx, ebx\njmp short loc_1588", + "ida_pseudo": "char *__fastcall func0(char *s)\n{\n char v2; // al\n char *v3; // rdx\n int v4; // ecx\n size_t v5; // rdi\n char *v6; // rbx\n char *v7; // rax\n char *v8; // r12\n char *v9; // rdi\n __int64 v10; // r13\n int v11; // eax\n char *v12; // rax\n\n v2 = *s;\n if ( *s )\n {\n v3 = s;\n v4 = 1;\n do\n {\n ++v3;\n v4 += v2 == 32;\n v2 = *v3;\n }\n while ( *v3 );\n v5 = 8LL * (v4 + 1);\n }\n else\n {\n v5 = 16LL;\n }\n v6 = (char *)malloc(v5);\n if ( !v6 )\n return 0LL;\n v7 = strdup(s);\n v8 = v7;\n if ( !v7 )\n {\n free(v6);\n return 0LL;\n }\n v9 = strtok(v7, \" \");\n if ( v9 )\n {\n v10 = 1LL;\n do\n {\n *(_QWORD *)&v6[8 * v10 - 8] = strdup(v9);\n v9 = strtok(0LL, \" \");\n v11 = v10++;\n }\n while ( v9 );\n v12 = &v6[8 * v11];\n }\n else\n {\n v12 = v6;\n }\n *(_QWORD *)v12 = 0LL;\n free(v8);\n return v6;\n}", + "ida_strip_asm": "sub_14C0:\nendbr64\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 8\nmovzx eax, byte ptr [rdi]\ntest al, al\njz loc_15A0\nmov rdx, rdi\nmov ecx, 1\nnop dword ptr [rax+00h]\nloc_14E8:\ncmp al, 20h ; ' '\nsetz al\nadd rdx, 1\nmovzx eax, al\nadd ecx, eax\nmovzx eax, byte ptr [rdx]\ntest al, al\njnz short loc_14E8\nlea edi, [rcx+1]\nmovsxd rdi, edi\nshl rdi, 3; size\nloc_1507:\ncall _malloc\nmov rbx, rax\ntest rax, rax\njz loc_15BD\nmov rdi, rbp; s\ncall _strdup\nmov r12, rax\ntest rax, rax\njz loc_15B5\nlea rbp, delim; \" \"\nmov rdi, rax; s\nmov rsi, rbp; delim\ncall _strtok\nmov rdi, rax; s\ntest rax, rax\njz short loc_15B0\nmov r13d, 1\nnop dword ptr [rax+00h]\nloc_1550:\ncall _strdup\nxor edi, edi; s\nmov rsi, rbp; delim\nmov [rbx+r13*8-8], rax\ncall _strtok\nmov rdi, rax\nmov rax, r13\nadd r13, 1\ntest rdi, rdi\njnz short loc_1550\ncdqe\nlea rax, [rbx+rax*8]\nloc_1579:\nmov qword ptr [rax], 0\nmov rdi, r12; ptr\ncall _free\nloc_1588:\nadd rsp, 8\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_15A0:\nmov edi, 10h\njmp loc_1507\nloc_15B0:\nmov rax, rbx\njmp short loc_1579\nloc_15B5:\nmov rdi, rbx; ptr\ncall _free\nloc_15BD:\nxor ebx, ebx\njmp short loc_1588", + "ida_strip_pseudo": "char *__fastcall sub_14C0(char *s)\n{\n char v2; // al\n char *v3; // rdx\n int v4; // ecx\n size_t v5; // rdi\n char *v6; // rbx\n char *v7; // rax\n char *v8; // r12\n char *v9; // rdi\n __int64 v10; // r13\n int v11; // eax\n char *v12; // rax\n\n v2 = *s;\n if ( *s )\n {\n v3 = s;\n v4 = 1;\n do\n {\n ++v3;\n v4 += v2 == 32;\n v2 = *v3;\n }\n while ( *v3 );\n v5 = 8LL * (v4 + 1);\n }\n else\n {\n v5 = 16LL;\n }\n v6 = (char *)malloc(v5);\n if ( !v6 )\n return 0LL;\n v7 = strdup(s);\n v8 = v7;\n if ( !v7 )\n {\n free(v6);\n return 0LL;\n }\n v9 = strtok(v7, \" \");\n if ( v9 )\n {\n v10 = 1LL;\n do\n {\n *(_QWORD *)&v6[8 * v10 - 8] = strdup(v9);\n v9 = strtok(0LL, \" \");\n v11 = v10++;\n }\n while ( v9 );\n v12 = &v6[8 * v11];\n }\n else\n {\n v12 = v6;\n }\n *(_QWORD *)v12 = 0LL;\n free(v8);\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_14C0(char *s) {\n char v2;\n char *v3;\n int v4;\n unsigned int v5;\n char *v6;\n char *v7;\n char *v8;\n char *v9;\n long long v10;\n int v11;\n char *v12;\n v2 = *s;\n if (*s) {\n v3 = s;\n v4 = 1;\n do {\n ++v3;\n v4 += v2 == 32;\n v2 = *v3;\n } while (*v3);\n v5 = 8LL * (v4 + 1);\n } else {\n v5 = 16LL;\n }\n v6 = (char *)malloc(v5);\n if (!v6) return 0LL;\n v7 = strdup(s);\n v8 = v7;\n if (!v7) {\n free(v6);\n return 0LL;\n }\n v9 = strtok(v7, \" \");\n if (v9) {\n v10 = 1LL;\n do {\n *(uint64_t *)&v6[8 * v10 - 8] = strdup(v9);\n v9 = strtok(0LL, \" \");\n v11 = v10++;\n } while (v9);\n v12 = &v6[8 * v11];\n } else {\n v12 = v6;\n }\n *(uint64_t *)v12 = 0LL;\n free(v8);\n return v6;\n}", + "ida_pseudo_norm": "char *func0(char *s) {\n char v2;\n char *v3;\n int v4;\n unsigned int v5;\n char *v6;\n char *v7;\n char *v8;\n char *v9;\n long long v10;\n int v11;\n char *v12;\n v2 = *s;\n if (*s) {\n v3 = s;\n v4 = 1;\n do {\n ++v3;\n v4 += v2 == 32;\n v2 = *v3;\n } while (*v3);\n v5 = 8LL * (v4 + 1);\n } else {\n v5 = 16LL;\n }\n v6 = (char *)malloc(v5);\n if (!v6) return 0LL;\n v7 = strdup(s);\n v8 = v7;\n if (!v7) {\n free(v6);\n return 0LL;\n }\n v9 = strtok(v7, \" \");\n if (v9) {\n v10 = 1LL;\n do {\n *(uint64_t *)&v6[8 * v10 - 8] = strdup(v9);\n v9 = strtok(0LL, \" \");\n v11 = v10++;\n } while (v9);\n v12 = &v6[8 * v11];\n } else {\n v12 = v6;\n }\n *(uint64_t *)v12 = 0LL;\n free(v8);\n return v6;\n}" + }, + { + "index": 119, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int XOR = 0;\n for (int i = 0; i < n; i++) {\n XOR = XOR ^ arr[i];\n }\n return XOR;\n}", + "test": "int main() {\n\n int arr1[] = {1, 1, 2, 2, 3};\n\n assert(func0(arr1, 5) == 3);\n\n \n\n int arr2[] = {1, 1, 3, 3, 4, 4, 5, 5, 7, 7, 8};\n\n assert(func0(arr2, 11) == 8);\n\n \n\n int arr3[] = {1, 2, 2, 3, 3, 4, 4};\n\n assert(func0(arr3, 7) == 1);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11a5 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nxor %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1188 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11A5\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nxor [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_11A5:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n v3 ^= *(_DWORD *)(4LL * i + a1);\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11A5\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nxor [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_11A5:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n v3 ^= *(_DWORD *)(4LL * i + a1);\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) v3 ^= *(uint32_t *)(4LL * i + a1);\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) v3 ^= *(uint32_t *)(4LL * i + a1);\n return v3;\n}" + }, + { + "index": 119, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int XOR = 0;\n for (int i = 0; i < n; i++) {\n XOR = XOR ^ arr[i];\n }\n return XOR;\n}", + "test": "int main() {\n\n int arr1[] = {1, 1, 2, 2, 3};\n\n assert(func0(arr1, 5) == 3);\n\n \n\n int arr2[] = {1, 1, 3, 3, 4, 4, 5, 5, 7, 7, 8};\n\n assert(func0(arr2, 11) == 8);\n\n \n\n int arr3[] = {1, 2, 2, 3, 3, 4, 4};\n\n assert(func0(arr3, 7) == 1);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 118f \nmov %rdi,%rax\nlea -0x1(%rsi),%edx\nlea 0x4(%rdi,%rdx,4),%rcx\nmov $0x0,%edx\nxor (%rax),%edx\nadd $0x4,%rax\ncmp %rcx,%rax\njne 1181 \nmov %edx,%eax\nretq\nmov $0x0,%edx\njmp 118c \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_118E\nmov rax, rdi\nmovsxd rsi, esi\nlea rcx, [rdi+rsi*4]\nmov edx, 0\nloc_1180:\nxor edx, [rax]\nadd rax, 4\ncmp rax, rcx\njnz short loc_1180\nloc_118B:\nmov eax, edx\nretn\nloc_118E:\nmov edx, 0\njmp short loc_118B", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n unsigned int v3; // edx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = 0;\n do\n v3 ^= *v2++;\n while ( v2 != &a1[a2] );\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_118E\nmov rax, rdi\nmovsxd rsi, esi\nlea rcx, [rdi+rsi*4]\nmov edx, 0\nloc_1180:\nxor edx, [rax]\nadd rax, 4\ncmp rax, rcx\njnz short loc_1180\nloc_118B:\nmov eax, edx\nretn\nloc_118E:\nmov edx, 0\njmp short loc_118B", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n unsigned int v3; // edx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = 0;\n do\n v3 ^= *v2++;\n while ( v2 != &a1[a2] );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2) {\n uint32_t *v2;\n unsigned int v3;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = 0;\n do\n v3 ^= *v2++;\n while (v2 != &a1[a2]);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n unsigned int v3;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = 0;\n do\n v3 ^= *v2++;\n while (v2 != &a1[a2]);\n }\n return v3;\n}" + }, + { + "index": 120, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int list1[][2], int size) {\n int result_max = 0;\n for (int i = 0; i < size; i++) {\n int product = abs(list1[i][0] * list1[i][1]);\n if (product > result_max) {\n result_max = product;\n }\n }\n return result_max;\n}", + "test": "int main() {\n\n int arr1[4][2] = {{2, 7}, {2, 6}, {1, 8}, {4, 9}};\n\n assert(func0(arr1, 4) == 36);\n\n\n\n int arr2[3][2] = {{10, 20}, {15, 2}, {5, 10}};\n\n assert(func0(arr2, 3) == 200);\n\n\n\n int arr3[4][2] = {{11, 44}, {10, 15}, {20, 5}, {12, 9}};\n\n assert(func0(arr3, 4) == 484);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11d7 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov 0x4(%rax),%eax\nimul %eax,%edx\nmov %edx,%eax\nsar $0x1f,%eax\nxor %eax,%edx\nmov %edx,-0x4(%rbp)\nsub %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0xc(%rbp),%eax\njle 11d3 \nmov -0x4(%rbp),%eax\nmov %eax,-0xc(%rbp)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1188 \nmov -0xc(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_11D4\nloc_1188:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax+4]\nimul eax, edx\nmov edx, eax\nneg edx\ncmovns eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_C]\njle short loc_11D0\nmov eax, [rbp+var_4]\nmov [rbp+var_C], eax\nloc_11D0:\nadd [rbp+var_8], 1\nloc_11D4:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int v2; // eax\n int v4; // [rsp+10h] [rbp-Ch]\n int i; // [rsp+14h] [rbp-8h]\n\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v2 = *(_DWORD *)(8LL * i + a1) * *(_DWORD *)(8LL * i + a1 + 4);\n if ( v2 <= 0 )\n v2 = -v2;\n if ( v2 > v4 )\n v4 = v2;\n }\n return (unsigned int)v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_11D4\nloc_1188:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax+4]\nimul eax, edx\nmov edx, eax\nneg edx\ncmovns eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_C]\njle short loc_11D0\nmov eax, [rbp+var_4]\nmov [rbp+var_C], eax\nloc_11D0:\nadd [rbp+var_8], 1\nloc_11D4:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int v2; // eax\n int v4; // [rsp+10h] [rbp-Ch]\n int i; // [rsp+14h] [rbp-8h]\n\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v2 = *(_DWORD *)(8LL * i + a1) * *(_DWORD *)(8LL * i + a1 + 4);\n if ( v2 <= 0 )\n v2 = -v2;\n if ( v2 > v4 )\n v4 = v2;\n }\n return (unsigned int)v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int v2;\n int v4;\n int i;\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n v2 = *(uint32_t *)(8LL * i + a1) * *(uint32_t *)(8LL * i + a1 + 4);\n if (v2 <= 0) v2 = -v2;\n if (v2 > v4) v4 = v2;\n }\n return (unsigned int)v4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int v2;\n int v4;\n int i;\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n v2 = *(uint32_t *)(8LL * i + a1) * *(uint32_t *)(8LL * i + a1 + 4);\n if (v2 <= 0) v2 = -v2;\n if (v2 > v4) v4 = v2;\n }\n return (unsigned int)v4;\n}" + }, + { + "index": 120, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int list1[][2], int size) {\n int result_max = 0;\n for (int i = 0; i < size; i++) {\n int product = abs(list1[i][0] * list1[i][1]);\n if (product > result_max) {\n result_max = product;\n }\n }\n return result_max;\n}", + "test": "int main() {\n\n int arr1[4][2] = {{2, 7}, {2, 6}, {1, 8}, {4, 9}};\n\n assert(func0(arr1, 4) == 36);\n\n\n\n int arr2[3][2] = {{10, 20}, {15, 2}, {5, 10}};\n\n assert(func0(arr2, 3) == 200);\n\n\n\n int arr3[4][2] = {{11, 44}, {10, 15}, {20, 5}, {12, 9}};\n\n assert(func0(arr3, 4) == 484);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11a1 \nmov %rdi,%rdx\nlea -0x1(%rsi),%eax\nlea 0x8(%rdi,%rax,8),%rdi\nmov $0x0,%ecx\nmov (%rdx),%eax\nimul 0x4(%rdx),%eax\nmov %eax,%esi\nsar $0x1f,%esi\nxor %esi,%eax\nsub %esi,%eax\ncmp %eax,%ecx\ncmovl %eax,%ecx\nadd $0x8,%rdx\ncmp %rdi,%rdx\njne 1181 \nmov %ecx,%eax\nretq\nmov $0x0,%ecx\njmp 119e \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_119E\nmov rdx, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*8]\nmov esi, 0\nloc_1180:\nmov eax, [rdx]\nimul eax, [rdx+4]\nmov ecx, eax\nneg ecx\ncmovns eax, ecx\ncmp esi, eax\ncmovl esi, eax\nadd rdx, 8\ncmp rdx, rdi\njnz short loc_1180\nloc_119B:\nmov eax, esi\nretn\nloc_119E:\nmov esi, 0\njmp short loc_119B", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rdx\n _DWORD *v3; // rdi\n int v4; // esi\n int v5; // eax\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = &a1[2 * a2];\n v4 = 0;\n do\n {\n v5 = v2[1] * *v2;\n if ( v5 <= 0 )\n v5 = -(v2[1] * *v2);\n if ( v4 < v5 )\n v4 = v5;\n v2 += 2;\n }\n while ( v2 != v3 );\n }\n return (unsigned int)v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_119E\nmov rdx, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*8]\nmov esi, 0\nloc_1180:\nmov eax, [rdx]\nimul eax, [rdx+4]\nmov ecx, eax\nneg ecx\ncmovns eax, ecx\ncmp esi, eax\ncmovl esi, eax\nadd rdx, 8\ncmp rdx, rdi\njnz short loc_1180\nloc_119B:\nmov eax, esi\nretn\nloc_119E:\nmov esi, 0\njmp short loc_119B", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rdx\n _DWORD *v3; // rdi\n int v4; // esi\n int v5; // eax\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = &a1[2 * a2];\n v4 = 0;\n do\n {\n v5 = v2[1] * *v2;\n if ( v5 <= 0 )\n v5 = -(v2[1] * *v2);\n if ( v4 < v5 )\n v4 = v5;\n v2 += 2;\n }\n while ( v2 != v3 );\n }\n return (unsigned int)v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2) {\n uint32_t *v2;\n uint32_t *v3;\n int v4;\n int v5;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = &a1[2 * a2];\n v4 = 0;\n do {\n v5 = v2[1] * *v2;\n if (v5 <= 0) v5 = -(v2[1] * *v2);\n if (v4 < v5) v4 = v5;\n v2 += 2;\n } while (v2 != v3);\n }\n return (unsigned int)v4;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n uint32_t *v3;\n int v4;\n int v5;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = &a1[2 * a2];\n v4 = 0;\n do {\n v5 = v2[1] * *v2;\n if (v5 <= 0) v5 = -(v2[1] * *v2);\n if (v4 < v5) v4 = v5;\n v2 += 2;\n } while (v2 != v3);\n }\n return (unsigned int)v4;\n}" + }, + { + "index": 121, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int A[], int n, int sum, int count) {\n if (count == 3 && sum == 0) {\n return true;\n }\n if (count == 3 || n == 0 || sum < 0) {\n return false;\n }\n return func0(A, n - 1, sum - A[n - 1], count + 1) ||\n func0(A, n - 1, sum, count);\n}", + "test": "int main() {\n\n int A1[] = {2, 7, 4, 0, 9, 5, 1, 3};\n\n int A2[] = {1, 4, 5, 6, 7, 8, 5, 9};\n\n int A3[] = {10, 4, 2, 3, 5};\n\n\n\n assert(func0(A1, 8, 6, 0) == true);\n\n assert(func0(A2, 8, 6, 0) == false);\n\n assert(func0(A3, 5, 15, 0) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x8(%rbp)\nmov %esi,-0xc(%rbp)\nmov %edx,-0x10(%rbp)\nmov %ecx,-0x14(%rbp)\ncmpl $0x3,-0x14(%rbp)\njne 1195 \ncmpl $0x0,-0x10(%rbp)\njne 1195 \nmov $0x1,%eax\njmp 1210 \ncmpl $0x3,-0x14(%rbp)\nje 11a7 \ncmpl $0x0,-0xc(%rbp)\nje 11a7 \ncmpl $0x0,-0x10(%rbp)\njns 11ae \nmov $0x0,%eax\njmp 1210 \nmov -0x14(%rbp),%eax\nlea 0x1(%rax),%ecx\nmov -0xc(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov -0x10(%rbp),%edx\nsub %eax,%edx\nmov -0xc(%rbp),%eax\nlea -0x1(%rax),%esi\nmov -0x8(%rbp),%rax\nmov %rax,%rdi\ncallq 1169 \ntest %al,%al\njne 1201 \nmov -0xc(%rbp),%eax\nlea -0x1(%rax),%esi\nmov -0x14(%rbp),%ecx\nmov -0x10(%rbp),%edx\nmov -0x8(%rbp),%rax\nmov %rax,%rdi\ncallq 1169 \ntest %al,%al\nje 1208 \nmov $0x1,%eax\njmp 120d \nmov $0x0,%eax\nand $0x1,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_8], rdi\nmov [rbp+var_C], esi\nmov [rbp+var_10], edx\nmov [rbp+var_14], ecx\ncmp [rbp+var_14], 3\njnz short loc_1195\ncmp [rbp+var_10], 0\njnz short loc_1195\nmov eax, 1\njmp short locret_1210\nloc_1195:\ncmp [rbp+var_14], 3\njz short loc_11A7\ncmp [rbp+var_C], 0\njz short loc_11A7\ncmp [rbp+var_10], 0\njns short loc_11AE\nloc_11A7:\nmov eax, 0\njmp short locret_1210\nloc_11AE:\nmov eax, [rbp+var_14]\nlea ecx, [rax+1]\nmov eax, [rbp+var_C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_10]\nsub edx, eax\nmov eax, [rbp+var_C]\nlea esi, [rax-1]\nmov rax, [rbp+var_8]\nmov rdi, rax\ncall func0\ntest al, al\njnz short loc_1201\nmov eax, [rbp+var_C]\nlea esi, [rax-1]\nmov ecx, [rbp+var_14]\nmov edx, [rbp+var_10]\nmov rax, [rbp+var_8]\nmov rdi, rax\ncall func0\ntest al, al\njz short loc_1208\nloc_1201:\nmov eax, 1\njmp short loc_120D\nloc_1208:\nmov eax, 0\nloc_120D:\nand eax, 1\nlocret_1210:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3, unsigned int a4)\n{\n if ( a4 == 3 && !a3 )\n return 1LL;\n if ( a4 == 3 || !a2 || a3 < 0 )\n return 0LL;\n return (unsigned __int8)func0(a1, (unsigned int)(a2 - 1), (unsigned int)(a3 - *(_DWORD *)(4LL * a2 - 4 + a1)), a4 + 1)\n || (unsigned __int8)func0(a1, (unsigned int)(a2 - 1), (unsigned int)a3, a4);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_8], rdi\nmov [rbp+var_C], esi\nmov [rbp+var_10], edx\nmov [rbp+var_14], ecx\ncmp [rbp+var_14], 3\njnz short loc_1195\ncmp [rbp+var_10], 0\njnz short loc_1195\nmov eax, 1\njmp short locret_1210\nloc_1195:\ncmp [rbp+var_14], 3\njz short loc_11A7\ncmp [rbp+var_C], 0\njz short loc_11A7\ncmp [rbp+var_10], 0\njns short loc_11AE\nloc_11A7:\nmov eax, 0\njmp short locret_1210\nloc_11AE:\nmov eax, [rbp+var_14]\nlea ecx, [rax+1]\nmov eax, [rbp+var_C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_10]\nsub edx, eax\nmov eax, [rbp+var_C]\nlea esi, [rax-1]\nmov rax, [rbp+var_8]\nmov rdi, rax\ncall sub_1169\ntest al, al\njnz short loc_1201\nmov eax, [rbp+var_C]\nlea esi, [rax-1]\nmov ecx, [rbp+var_14]\nmov edx, [rbp+var_10]\nmov rax, [rbp+var_8]\nmov rdi, rax\ncall sub_1169\ntest al, al\njz short loc_1208\nloc_1201:\nmov eax, 1\njmp short loc_120D\nloc_1208:\nmov eax, 0\nloc_120D:\nand eax, 1\nlocret_1210:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3, unsigned int a4)\n{\n if ( a4 == 3 && !a3 )\n return 1LL;\n if ( a4 == 3 || !a2 || a3 < 0 )\n return 0LL;\n return (unsigned __int8)sub_1169(\n a1,\n (unsigned int)(a2 - 1),\n (unsigned int)(a3 - *(_DWORD *)(4LL * a2 - 4 + a1)),\n a4 + 1)\n || (unsigned __int8)sub_1169(a1, (unsigned int)(a2 - 1), (unsigned int)a3, a4);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3, unsigned int a4) {\n if (a4 == 3 && !a3) return 1LL;\n if (a4 == 3 || !a2 || a3 < 0) return 0LL;\n return (unsigned char)sub_1169(\n a1, (unsigned int)(a2 - 1),\n (unsigned int)(a3 - *(uint32_t *)(4LL * a2 - 4 + a1)), a4 + 1) ||\n (unsigned char)sub_1169(a1, (unsigned int)(a2 - 1), (unsigned int)a3,\n a4);\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3, unsigned int a4) {\n if (a4 == 3 && !a3) return 1LL;\n if (a4 == 3 || !a2 || a3 < 0) return 0LL;\n return (unsigned char)func0(\n a1, (unsigned int)(a2 - 1),\n (unsigned int)(a3 - *(uint32_t *)(4LL * a2 - 4 + a1)), a4 + 1) ||\n (unsigned char)func0(a1, (unsigned int)(a2 - 1), (unsigned int)a3, a4);\n}" + }, + { + "index": 121, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int A[], int n, int sum, int count) {\n if (count == 3 && sum == 0) {\n return true;\n }\n if (count == 3 || n == 0 || sum < 0) {\n return false;\n }\n return func0(A, n - 1, sum - A[n - 1], count + 1) ||\n func0(A, n - 1, sum, count);\n}", + "test": "int main() {\n\n int A1[] = {2, 7, 4, 0, 9, 5, 1, 3};\n\n int A2[] = {1, 4, 5, 6, 7, 8, 5, 9};\n\n int A3[] = {10, 4, 2, 3, 5};\n\n\n\n assert(func0(A1, 8, 6, 0) == true);\n\n assert(func0(A2, 8, 6, 0) == false);\n\n assert(func0(A3, 5, 15, 0) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %edx,%ebx\ncmp $0x3,%ecx\nsete %dl\ntest %ebx,%ebx\nsete %al\nand %dl,%al\njne 11cb \nmov %rdi,%r12\nmov %ecx,%ebp\ntest %esi,%esi\nsete %dil\nmov %ebx,%ecx\nshr $0x1f,%ecx\nor %cl,%dil\njne 11cb \ntest %dl,%dl\njne 11cb \nlea -0x1(%rsi),%r13d\nlea 0x1(%rbp),%ecx\nmovslq %esi,%rsi\nmov %ebx,%edx\nsub -0x4(%r12,%rsi,4),%edx\nmov %r13d,%esi\nmov %r12,%rdi\ncallq 1169 \nmov %eax,%edx\nmov $0x1,%eax\ntest %dl,%dl\nje 11d6 \nand $0x1,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nmov %ebp,%ecx\nmov %ebx,%edx\nmov %r13d,%esi\nmov %r12,%rdi\ncallq 1169 \nmovzbl %al,%eax\njmp 11c8 \n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov ebx, edx\ncmp ecx, 3\nsetz dl\ntest ebx, ebx\nsetz al\nand al, dl\njnz short loc_11CA\nmov r12, rdi\nmov ebp, ecx\ntest esi, esi\nsetz cl\nmov edi, ebx\nshr edi, 1Fh\nor cl, dil\njnz short loc_11CA\ntest dl, dl\njnz short loc_11CA\nlea r13d, [rsi-1]\nlea ecx, [rbp+1]\nmovsxd rsi, esi\nmov edx, ebx\nsub edx, [r12+rsi*4-4]\nmov esi, r13d\nmov rdi, r12\ncall func0\nmov edx, eax\nmov eax, 1\ntest dl, dl\njz short loc_11D5\nloc_11C7:\nand eax, 1\nloc_11CA:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_11D5:\nmov ecx, ebp\nmov edx, ebx\nmov esi, r13d\nmov rdi, r12\ncall func0\nmovzx eax, al\njmp short loc_11C7", + "ida_pseudo": "bool __fastcall func0(__int64 a1, int a2, int a3, unsigned int a4)\n{\n bool result; // al\n char v7; // dl\n char v8; // al\n\n result = a4 == 3 && a3 == 0;\n if ( !result && a3 >= 0 && a2 != 0 && a4 != 3 )\n {\n v7 = func0(a1, (unsigned int)(a2 - 1), (unsigned int)(a3 - *(_DWORD *)(a1 + 4LL * a2 - 4)), a4 + 1);\n v8 = 1;\n if ( !v7 )\n v8 = func0(a1, (unsigned int)(a2 - 1), (unsigned int)a3, a4);\n return v8 & 1;\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov ebx, edx\ncmp ecx, 3\nsetz dl\ntest ebx, ebx\nsetz al\nand al, dl\njnz short loc_11CA\nmov r12, rdi\nmov ebp, ecx\ntest esi, esi\nsetz cl\nmov edi, ebx\nshr edi, 1Fh\nor cl, dil\njnz short loc_11CA\ntest dl, dl\njnz short loc_11CA\nlea r13d, [rsi-1]\nlea ecx, [rbp+1]\nmovsxd rsi, esi\nmov edx, ebx\nsub edx, [r12+rsi*4-4]\nmov esi, r13d\nmov rdi, r12\ncall sub_1169\nmov edx, eax\nmov eax, 1\ntest dl, dl\njz short loc_11D5\nloc_11C7:\nand eax, 1\nloc_11CA:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_11D5:\nmov ecx, ebp\nmov edx, ebx\nmov esi, r13d\nmov rdi, r12\ncall sub_1169\nmovzx eax, al\njmp short loc_11C7", + "ida_strip_pseudo": "bool __fastcall sub_1169(__int64 a1, int a2, int a3, unsigned int a4)\n{\n bool result; // al\n char v7; // dl\n char v8; // al\n\n result = a4 == 3 && a3 == 0;\n if ( !result && a3 >= 0 && a2 != 0 && a4 != 3 )\n {\n v7 = sub_1169(a1, (unsigned int)(a2 - 1), (unsigned int)(a3 - *(_DWORD *)(a1 + 4LL * a2 - 4)), a4 + 1);\n v8 = 1;\n if ( !v7 )\n v8 = sub_1169(a1, (unsigned int)(a2 - 1), (unsigned int)a3, a4);\n return v8 & 1;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_1169(long long a1, int a2, int a3, unsigned int a4) {\n bool result;\n char v7;\n char v8;\n result = a4 == 3 && a3 == 0;\n if (!result && a3 >= 0 && a2 != 0 && a4 != 3) {\n v7 =\n sub_1169(a1, (unsigned int)(a2 - 1),\n (unsigned int)(a3 - *(uint32_t *)(a1 + 4LL * a2 - 4)), a4 + 1);\n v8 = 1;\n if (!v7) v8 = sub_1169(a1, (unsigned int)(a2 - 1), (unsigned int)a3, a4);\n return v8 & 1;\n }\n return result;\n}", + "ida_pseudo_norm": "bool func0(long long a1, int a2, int a3, unsigned int a4) {\n bool result;\n char v7;\n char v8;\n result = a4 == 3 && a3 == 0;\n if (!result && a3 >= 0 && a2 != 0 && a4 != 3) {\n v7 = func0(a1, (unsigned int)(a2 - 1),\n (unsigned int)(a3 - *(uint32_t *)(a1 + 4LL * a2 - 4)), a4 + 1);\n v8 = 1;\n if (!v7) v8 = func0(a1, (unsigned int)(a2 - 1), (unsigned int)a3, a4);\n return v8 & 1;\n }\n return result;\n}" + }, + { + "index": 121, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int A[], int n, int sum, int count) {\n if (count == 3 && sum == 0) {\n return true;\n }\n if (count == 3 || n == 0 || sum < 0) {\n return false;\n }\n return func0(A, n - 1, sum - A[n - 1], count + 1) ||\n func0(A, n - 1, sum, count);\n}", + "test": "int main() {\n\n int A1[] = {2, 7, 4, 0, 9, 5, 1, 3};\n\n int A2[] = {1, 4, 5, 6, 7, 8, 5, 9};\n\n int A3[] = {10, 4, 2, 3, 5};\n\n\n\n assert(func0(A1, 8, 6, 0) == true);\n\n assert(func0(A2, 8, 6, 0) == false);\n\n assert(func0(A3, 5, 15, 0) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x3,%ecx\nsete %r8b\ntest %edx,%edx\nsete %al\nand %r8b,%al\njne 1320 \ntest %esi,%esi\nmov %edx,%r9d\nsete %r10b\nshr $0x1f,%r9d\nor %r9b,%r10b\njne 1320 \ntest %r8b,%r8b\njne 1320 \njmp 1330 \nxchg %ax,%ax\nretq\ndata16 nopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0_part_0:\npush r15\npush r14\nlea r14d, [rcx+1]\npush r13\nmov r13d, ecx\npush r12\nmov r12, rdi\npush rbp\nmov ebp, edx\npush rbx\nmov ebx, esi\nsub rsp, 8\nloc_12BC:\nmovsxd rax, ebx\ncmp r14d, 3\nmov esi, ebp\nsetz dl\nsub esi, [r12+rax*4-4]\nsetz al\nand al, dl\njnz short loc_12F7\nsub ebx, 1\nsetz r15b\ntest esi, esi\njs short loc_1310\nor dl, r15b\njnz short loc_1310\nmov edx, esi\nmov ecx, r14d\nmov esi, ebx\nmov rdi, r12\ncall func0_part_0\ntest al, al\njz short loc_1310\nloc_12F7:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1310:\ncmp r13d, 3\nsetz dl\ntest ebp, ebp\nsetz al\nand al, dl\njnz short loc_12F7\ntest ebp, ebp\njs short loc_12F7\nor dl, r15b\njz short loc_12BC\njmp short loc_12F7", + "ida_pseudo": "char __fastcall func0_part_0(__int64 a1, unsigned int a2, int a3, int a4)\n{\n unsigned int v4; // r14d\n int v8; // esi\n char result; // al\n bool v10; // r15\n\n v4 = a4 + 1;\n do\n {\n v8 = a3 - *(_DWORD *)(a1 + 4LL * (int)a2 - 4);\n result = v4 == 3 && a3 == *(_DWORD *)(a1 + 4LL * (int)a2 - 4);\n if ( result )\n break;\n v10 = --a2 == 0;\n if ( v8 >= 0 && !v10 && v4 != 3 )\n {\n result = func0_part_0(a1, a2, (unsigned int)v8, v4);\n if ( result )\n break;\n }\n result = a4 == 3 && a3 == 0;\n if ( result )\n break;\n }\n while ( a3 >= 0 && !v10 && a4 != 3 );\n return result;\n}", + "ida_strip_asm": "sub_12A0:\npush r15\npush r14\nlea r14d, [rcx+1]\npush r13\nmov r13d, ecx\npush r12\nmov r12, rdi\npush rbp\nmov ebp, edx\npush rbx\nmov ebx, esi\nsub rsp, 8\nloc_12BC:\nmovsxd rax, ebx\ncmp r14d, 3\nmov esi, ebp\nsetz dl\nsub esi, [r12+rax*4-4]\nsetz al\nand al, dl\njnz short loc_12F7\nsub ebx, 1\nsetz r15b\ntest esi, esi\njs short loc_1310\nor dl, r15b\njnz short loc_1310\nmov edx, esi\nmov ecx, r14d\nmov esi, ebx\nmov rdi, r12\ncall sub_12A0\ntest al, al\njz short loc_1310\nloc_12F7:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1310:\ncmp r13d, 3\nsetz dl\ntest ebp, ebp\nsetz al\nand al, dl\njnz short loc_12F7\ntest ebp, ebp\njs short loc_12F7\nor dl, r15b\njz short loc_12BC\njmp short loc_12F7", + "ida_strip_pseudo": "char __fastcall sub_12A0(__int64 a1, unsigned int a2, int a3, int a4)\n{\n unsigned int v4; // r14d\n int v8; // esi\n char result; // al\n bool v10; // r15\n\n v4 = a4 + 1;\n do\n {\n v8 = a3 - *(_DWORD *)(a1 + 4LL * (int)a2 - 4);\n result = v4 == 3 && a3 == *(_DWORD *)(a1 + 4LL * (int)a2 - 4);\n if ( result )\n break;\n v10 = --a2 == 0;\n if ( v8 >= 0 && !v10 && v4 != 3 )\n {\n result = sub_12A0(a1, a2, (unsigned int)v8, v4);\n if ( result )\n break;\n }\n result = a4 == 3 && a3 == 0;\n if ( result )\n break;\n }\n while ( a3 >= 0 && !v10 && a4 != 3 );\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char sub_12A0(long long a1, unsigned int a2, int a3, int a4) {\n unsigned int v4;\n int v8;\n char result;\n bool v10;\n v4 = a4 + 1;\n do {\n v8 = a3 - *(uint32_t *)(a1 + 4LL * (int)a2 - 4);\n result = v4 == 3 && a3 == *(uint32_t *)(a1 + 4LL * (int)a2 - 4);\n if (result) break;\n v10 = --a2 == 0;\n if (v8 >= 0 && !v10 && v4 != 3) {\n result = sub_12A0(a1, a2, (unsigned int)v8, v4);\n if (result) break;\n }\n result = a4 == 3 && a3 == 0;\n if (result) break;\n } while (a3 >= 0 && !v10 && a4 != 3);\n return result;\n}", + "ida_pseudo_norm": "char func0_part_0(long long a1, unsigned int a2, int a3, int a4) {\n unsigned int v4;\n int v8;\n char result;\n bool v10;\n v4 = a4 + 1;\n do {\n v8 = a3 - *(uint32_t *)(a1 + 4LL * (int)a2 - 4);\n result = v4 == 3 && a3 == *(uint32_t *)(a1 + 4LL * (int)a2 - 4);\n if (result) break;\n v10 = --a2 == 0;\n if (v8 >= 0 && !v10 && v4 != 3) {\n result = func0_part_0(a1, a2, (unsigned int)v8, v4);\n if (result) break;\n }\n result = a4 == 3 && a3 == 0;\n if (result) break;\n } while (a3 >= 0 && !v10 && a4 != 3);\n return result;\n}" + }, + { + "index": 121, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int A[], int n, int sum, int count) {\n if (count == 3 && sum == 0) {\n return true;\n }\n if (count == 3 || n == 0 || sum < 0) {\n return false;\n }\n return func0(A, n - 1, sum - A[n - 1], count + 1) ||\n func0(A, n - 1, sum, count);\n}", + "test": "int main() {\n\n int A1[] = {2, 7, 4, 0, 9, 5, 1, 3};\n\n int A2[] = {1, 4, 5, 6, 7, 8, 5, 9};\n\n int A3[] = {10, 4, 2, 3, 5};\n\n\n\n assert(func0(A1, 8, 6, 0) == true);\n\n assert(func0(A2, 8, 6, 0) == false);\n\n assert(func0(A3, 5, 15, 0) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nmov %edx,%r10d\ncmp $0x3,%ecx\nsete %dl\ntest %r10d,%r10d\nsete %al\nand %dl,%al\njne 13d8 \npush %r12\nmov %ecx,%r11d\nmov %r10d,%ecx\npush %rbp\nmov %rdi,%rbp\nsub $0x8,%rsp\ntest %esi,%esi\nsete %dil\nshr $0x1f,%ecx\nor %cl,%dil\njne 13ca \ntest %dl,%dl\njne 13ca \nmovslq %esi,%rax\ncmp $0x2,%r11d\nlea 0x1(%r11),%ecx\nmov %r10d,%r8d\nsete %dl\nsub -0x4(%rbp,%rax,4),%r8d\nsete %al\nand %dl,%al\njne 13ca \nlea -0x1(%rsi),%r12d\ncmp $0x1,%esi\nje 13e0 \ntest %dl,%dl\njne 13e0 \ntest %r8d,%r8d\njs 13e5 \nmov %r8d,%edx\nmov %r12d,%esi\nmov %rbp,%rdi\ncallq 12a0 \ntest %al,%al\nje 13e5 \nadd $0x8,%rsp\npop %rbp\npop %r12\nretq\nnopw 0x0(%rax,%rax,1)\nretq\nnopl 0x0(%rax)\ntest %r12d,%r12d\nje 13ca \nadd $0x8,%rsp\nmov %r12d,%esi\nmov %rbp,%rdi\nmov %r11d,%ecx\npop %rbp\nmov %r10d,%edx\npop %r12\njmpq 12a0 \nnopl (%rax)\n", + "ida_asm": "func0_part_0:\npush r15\npush r14\nlea r14d, [rcx+1]\npush r13\nmov r13d, ecx\npush r12\nmov r12, rdi\npush rbp\nmov ebp, edx\npush rbx\nmov ebx, esi\nsub rsp, 8\nloc_12BC:\nmovsxd rax, ebx\ncmp r14d, 3\nmov esi, ebp\nsetz dl\nsub esi, [r12+rax*4-4]\nsetz al\nand al, dl\njnz short loc_12F7\nsub ebx, 1\nsetz r15b\ntest esi, esi\njs short loc_1310\nor dl, r15b\njnz short loc_1310\nmov edx, esi\nmov ecx, r14d\nmov esi, ebx\nmov rdi, r12\ncall func0_part_0\ntest al, al\njz short loc_1310\nloc_12F7:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1310:\ncmp r13d, 3\nsetz dl\ntest ebp, ebp\nsetz al\nand al, dl\njnz short loc_12F7\ntest ebp, ebp\njs short loc_12F7\nor dl, r15b\njz short loc_12BC\njmp short loc_12F7", + "ida_pseudo": "char __fastcall func0_part_0(__int64 a1, unsigned int a2, int a3, int a4)\n{\n unsigned int v4; // r14d\n int v8; // esi\n char result; // al\n bool v10; // r15\n\n v4 = a4 + 1;\n do\n {\n v8 = a3 - *(_DWORD *)(a1 + 4LL * (int)a2 - 4);\n result = v4 == 3 && a3 == *(_DWORD *)(a1 + 4LL * (int)a2 - 4);\n if ( result )\n break;\n v10 = --a2 == 0;\n if ( v8 >= 0 && !v10 && v4 != 3 )\n {\n result = func0_part_0(a1, a2, (unsigned int)v8, v4);\n if ( result )\n break;\n }\n result = a4 == 3 && a3 == 0;\n if ( result )\n break;\n }\n while ( a3 >= 0 && !v10 && a4 != 3 );\n return result;\n}", + "ida_strip_asm": "sub_12A0:\npush r15\npush r14\nlea r14d, [rcx+1]\npush r13\nmov r13d, ecx\npush r12\nmov r12, rdi\npush rbp\nmov ebp, edx\npush rbx\nmov ebx, esi\nsub rsp, 8\nloc_12BC:\nmovsxd rax, ebx\ncmp r14d, 3\nmov esi, ebp\nsetz dl\nsub esi, [r12+rax*4-4]\nsetz al\nand al, dl\njnz short loc_12F7\nsub ebx, 1\nsetz r15b\ntest esi, esi\njs short loc_1310\nor dl, r15b\njnz short loc_1310\nmov edx, esi\nmov ecx, r14d\nmov esi, ebx\nmov rdi, r12\ncall sub_12A0\ntest al, al\njz short loc_1310\nloc_12F7:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1310:\ncmp r13d, 3\nsetz dl\ntest ebp, ebp\nsetz al\nand al, dl\njnz short loc_12F7\ntest ebp, ebp\njs short loc_12F7\nor dl, r15b\njz short loc_12BC\njmp short loc_12F7", + "ida_strip_pseudo": "char __fastcall sub_12A0(__int64 a1, unsigned int a2, int a3, int a4)\n{\n unsigned int v4; // r14d\n int v8; // esi\n char result; // al\n bool v10; // r15\n\n v4 = a4 + 1;\n do\n {\n v8 = a3 - *(_DWORD *)(a1 + 4LL * (int)a2 - 4);\n result = v4 == 3 && a3 == *(_DWORD *)(a1 + 4LL * (int)a2 - 4);\n if ( result )\n break;\n v10 = --a2 == 0;\n if ( v8 >= 0 && !v10 && v4 != 3 )\n {\n result = sub_12A0(a1, a2, (unsigned int)v8, v4);\n if ( result )\n break;\n }\n result = a4 == 3 && a3 == 0;\n if ( result )\n break;\n }\n while ( a3 >= 0 && !v10 && a4 != 3 );\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char sub_12A0(long long a1, unsigned int a2, int a3, int a4) {\n unsigned int v4;\n int v8;\n char result;\n bool v10;\n v4 = a4 + 1;\n do {\n v8 = a3 - *(uint32_t *)(a1 + 4LL * (int)a2 - 4);\n result = v4 == 3 && a3 == *(uint32_t *)(a1 + 4LL * (int)a2 - 4);\n if (result) break;\n v10 = --a2 == 0;\n if (v8 >= 0 && !v10 && v4 != 3) {\n result = sub_12A0(a1, a2, (unsigned int)v8, v4);\n if (result) break;\n }\n result = a4 == 3 && a3 == 0;\n if (result) break;\n } while (a3 >= 0 && !v10 && a4 != 3);\n return result;\n}", + "ida_pseudo_norm": "char func0_part_0(long long a1, unsigned int a2, int a3, int a4) {\n unsigned int v4;\n int v8;\n char result;\n bool v10;\n v4 = a4 + 1;\n do {\n v8 = a3 - *(uint32_t *)(a1 + 4LL * (int)a2 - 4);\n result = v4 == 3 && a3 == *(uint32_t *)(a1 + 4LL * (int)a2 - 4);\n if (result) break;\n v10 = --a2 == 0;\n if (v8 >= 0 && !v10 && v4 != 3) {\n result = func0_part_0(a1, a2, (unsigned int)v8, v4);\n if (result) break;\n }\n result = a4 == 3 && a3 == 0;\n if (result) break;\n } while (a3 >= 0 && !v10 && a4 != 3);\n return result;\n}" + }, + { + "index": 122, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n#define MAX 3000\n\n\n\n", + "func": "int func0(int n) {\n int primes[MAX] = {0};\n int result[MAX], resultIndex = 0;\n for (int i = 2; i < MAX; i++) {\n if (primes[i] == 0) {\n primes[i] = 1;\n int j = i * 2;\n while (j < MAX) {\n primes[j] -= 1;\n if ((primes[j] + 3) == 0) {\n result[resultIndex++] = j;\n }\n j += i;\n }\n }\n }\n for (int i = 0; i < resultIndex - 1; i++) {\n for (int j = 0; j < resultIndex - i - 1; j++) {\n if (result[j] > result[j + 1]) {\n int temp = result[j];\n result[j] = result[j + 1];\n result[j + 1] = temp;\n }\n }\n }\n return result[n - 1];\n}", + "test": "int main() {\n\n assert(func0(1) == 30);\n\n assert(func0(50) == 273);\n\n assert(func0(1000) == 2664);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nlea -0x5000(%rsp),%r11\nsub $0x1000,%rsp\norq $0x0,(%rsp)\ncmp %r11,%rsp\njne 1199 \nsub $0xe00,%rsp\nmov %edi,-0x5df4(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea -0x5dd0(%rbp),%rax\nmov $0x2ee0,%edx\nmov $0x0,%esi\nmov %rax,%rdi\ncallq 1090 \nmovl $0x0,-0x5de8(%rbp)\nmovl $0x2,-0x5de4(%rbp)\njmpq 12a4 \nmov -0x5de4(%rbp),%eax\ncltq\nmov -0x5dd0(%rbp,%rax,4),%eax\ntest %eax,%eax\njne 129d \nmov -0x5de4(%rbp),%eax\ncltq\nmovl $0x1,-0x5dd0(%rbp,%rax,4)\nmov -0x5de4(%rbp),%eax\nadd %eax,%eax\nmov %eax,-0x5de0(%rbp)\njmp 1291 \nmov -0x5de0(%rbp),%eax\ncltq\nmov -0x5dd0(%rbp,%rax,4),%eax\nlea -0x1(%rax),%edx\nmov -0x5de0(%rbp),%eax\ncltq\nmov %edx,-0x5dd0(%rbp,%rax,4)\nmov -0x5de0(%rbp),%eax\ncltq\nmov -0x5dd0(%rbp,%rax,4),%eax\ncmp $0xfffffffd,%eax\njne 1285 \nmov -0x5de8(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x5de8(%rbp)\ncltq\nmov -0x5de0(%rbp),%edx\nmov %edx,-0x2ef0(%rbp,%rax,4)\nmov -0x5de4(%rbp),%eax\nadd %eax,-0x5de0(%rbp)\ncmpl $0xbb7,-0x5de0(%rbp)\njle 1232 \naddl $0x1,-0x5de4(%rbp)\ncmpl $0xbb7,-0x5de4(%rbp)\njle 11f8 \nmovl $0x0,-0x5ddc(%rbp)\njmpq 136b \nmovl $0x0,-0x5dd8(%rbp)\njmp 1349 \nmov -0x5dd8(%rbp),%eax\ncltq\nmov -0x2ef0(%rbp,%rax,4),%edx\nmov -0x5dd8(%rbp),%eax\nadd $0x1,%eax\ncltq\nmov -0x2ef0(%rbp,%rax,4),%eax\ncmp %eax,%edx\njle 1342 \nmov -0x5dd8(%rbp),%eax\ncltq\nmov -0x2ef0(%rbp,%rax,4),%eax\nmov %eax,-0x5dd4(%rbp)\nmov -0x5dd8(%rbp),%eax\nadd $0x1,%eax\ncltq\nmov -0x2ef0(%rbp,%rax,4),%edx\nmov -0x5dd8(%rbp),%eax\ncltq\nmov %edx,-0x2ef0(%rbp,%rax,4)\nmov -0x5dd8(%rbp),%eax\nadd $0x1,%eax\ncltq\nmov -0x5dd4(%rbp),%edx\nmov %edx,-0x2ef0(%rbp,%rax,4)\naddl $0x1,-0x5dd8(%rbp)\nmov -0x5de8(%rbp),%eax\nsub -0x5ddc(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x5dd8(%rbp)\njl 12cf \naddl $0x1,-0x5ddc(%rbp)\nmov -0x5de8(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x5ddc(%rbp)\njl 12c3 \nmov -0x5df4(%rbp),%eax\nsub $0x1,%eax\ncltq\nmov -0x2ef0(%rbp,%rax,4),%eax\nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 13a6 \ncallq 1070 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nlea r11, [rsp+var_5000]\nloc_1199:\nsub rsp, 1000h\nor [rsp+1000h+var_1000], 0\ncmp rsp, r11\njnz short loc_1199\nsub rsp, 0E00h\nmov [rbp+var_5DF4], edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [rbp+s]\nmov edx, 2EE0h; n\nmov esi, 0; c\nmov rdi, rax; s\ncall _memset\nmov [rbp+var_5DE8], 0\nmov [rbp+var_5DE4], 2\njmp loc_12A4\nloc_11F8:\nmov eax, [rbp+var_5DE4]\ncdqe\nmov eax, [rbp+rax*4+s]\ntest eax, eax\njnz loc_129D\nmov eax, [rbp+var_5DE4]\ncdqe\nmov [rbp+rax*4+s], 1\nmov eax, [rbp+var_5DE4]\nadd eax, eax\nmov [rbp+var_5DE0], eax\njmp short loc_1291\nloc_1232:\nmov eax, [rbp+var_5DE0]\ncdqe\nmov eax, [rbp+rax*4+s]\nlea edx, [rax-1]\nmov eax, [rbp+var_5DE0]\ncdqe\nmov [rbp+rax*4+s], edx\nmov eax, [rbp+var_5DE0]\ncdqe\nmov eax, [rbp+rax*4+s]\ncmp eax, 0FFFFFFFDh\njnz short loc_1285\nmov eax, [rbp+var_5DE8]\nlea edx, [rax+1]\nmov [rbp+var_5DE8], edx\ncdqe\nmov edx, [rbp+var_5DE0]\nmov [rbp+rax*4+var_2EF0], edx\nloc_1285:\nmov eax, [rbp+var_5DE4]\nadd [rbp+var_5DE0], eax\nloc_1291:\ncmp [rbp+var_5DE0], 0BB7h\njle short loc_1232\nloc_129D:\nadd [rbp+var_5DE4], 1\nloc_12A4:\ncmp [rbp+var_5DE4], 0BB7h\njle loc_11F8\nmov [rbp+var_5DDC], 0\njmp loc_136B\nloc_12C3:\nmov [rbp+var_5DD8], 0\njmp short loc_1349\nloc_12CF:\nmov eax, [rbp+var_5DD8]\ncdqe\nmov edx, [rbp+rax*4+var_2EF0]\nmov eax, [rbp+var_5DD8]\nadd eax, 1\ncdqe\nmov eax, [rbp+rax*4+var_2EF0]\ncmp edx, eax\njle short loc_1342\nmov eax, [rbp+var_5DD8]\ncdqe\nmov eax, [rbp+rax*4+var_2EF0]\nmov [rbp+var_5DD4], eax\nmov eax, [rbp+var_5DD8]\nadd eax, 1\ncdqe\nmov edx, [rbp+rax*4+var_2EF0]\nmov eax, [rbp+var_5DD8]\ncdqe\nmov [rbp+rax*4+var_2EF0], edx\nmov eax, [rbp+var_5DD8]\nadd eax, 1\ncdqe\nmov edx, [rbp+var_5DD4]\nmov [rbp+rax*4+var_2EF0], edx\nloc_1342:\nadd [rbp+var_5DD8], 1\nloc_1349:\nmov eax, [rbp+var_5DE8]\nsub eax, [rbp+var_5DDC]\nsub eax, 1\ncmp [rbp+var_5DD8], eax\njl loc_12CF\nadd [rbp+var_5DDC], 1\nloc_136B:\nmov eax, [rbp+var_5DE8]\nsub eax, 1\ncmp [rbp+var_5DDC], eax\njl loc_12C3\nmov eax, [rbp+var_5DF4]\nsub eax, 1\ncdqe\nmov eax, [rbp+rax*4+var_2EF0]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_13A6\ncall ___stack_chk_fail\nlocret_13A6:\nleave\nretn", + "ida_pseudo": "// bad sp value at call has been detected, the output may be wrong!\n__int64 __fastcall func0(int a1)\n{\n int v1; // eax\n int v3; // [rsp+Ch] [rbp-5DE8h]\n int i; // [rsp+10h] [rbp-5DE4h]\n int j; // [rsp+14h] [rbp-5DE0h]\n int k; // [rsp+18h] [rbp-5DDCh]\n int m; // [rsp+1Ch] [rbp-5DD8h]\n int v8; // [rsp+20h] [rbp-5DD4h]\n _DWORD s[884]; // [rsp+24h] [rbp-5DD0h] BYREF\n _BYTE v10[16384]; // [rsp+DF4h] [rbp-5000h] BYREF\n _QWORD v11[512]; // [rsp+4DF4h] [rbp-1000h] BYREF\n\n while ( v11 != (_QWORD *)v10 )\n ;\n v11[511] = __readfsqword(0x28u);\n memset(s, 0, 0x2EE0uLL);\n v3 = 0;\n for ( i = 2; i <= 2999; ++i )\n {\n if ( !s[i] )\n {\n s[i] = 1;\n for ( j = 2 * i; j <= 2999; j += i )\n {\n if ( --s[j] == -3 )\n {\n v1 = v3++;\n *(_DWORD *)&v10[4 * v1 + 8464] = j;\n }\n }\n }\n }\n for ( k = 0; k < v3 - 1; ++k )\n {\n for ( m = 0; m < v3 - k - 1; ++m )\n {\n if ( *(_DWORD *)&v10[4 * m + 8464] > *(_DWORD *)&v10[4 * m + 8468] )\n {\n v8 = *(_DWORD *)&v10[4 * m + 8464];\n *(_DWORD *)&v10[4 * m + 8464] = *(_DWORD *)&v10[4 * m + 8468];\n *(_DWORD *)&v10[4 * m + 8468] = v8;\n }\n }\n }\n return *(unsigned int *)&v10[4 * a1 + 8460];\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nlea r11, [rsp+var_5000]\nloc_1199:\nsub rsp, 1000h\nor [rsp+1000h+var_1000], 0\ncmp rsp, r11\njnz short loc_1199\nsub rsp, 0E00h\nmov [rbp+var_5DF4], edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [rbp+s]\nmov edx, 2EE0h; n\nmov esi, 0; c\nmov rdi, rax; s\ncall _memset\nmov [rbp+var_5DE8], 0\nmov [rbp+var_5DE4], 2\njmp loc_12A4\nloc_11F8:\nmov eax, [rbp+var_5DE4]\ncdqe\nmov eax, [rbp+rax*4+s]\ntest eax, eax\njnz loc_129D\nmov eax, [rbp+var_5DE4]\ncdqe\nmov [rbp+rax*4+s], 1\nmov eax, [rbp+var_5DE4]\nadd eax, eax\nmov [rbp+var_5DE0], eax\njmp short loc_1291\nloc_1232:\nmov eax, [rbp+var_5DE0]\ncdqe\nmov eax, [rbp+rax*4+s]\nlea edx, [rax-1]\nmov eax, [rbp+var_5DE0]\ncdqe\nmov [rbp+rax*4+s], edx\nmov eax, [rbp+var_5DE0]\ncdqe\nmov eax, [rbp+rax*4+s]\ncmp eax, 0FFFFFFFDh\njnz short loc_1285\nmov eax, [rbp+var_5DE8]\nlea edx, [rax+1]\nmov [rbp+var_5DE8], edx\ncdqe\nmov edx, [rbp+var_5DE0]\nmov [rbp+rax*4+var_2EF0], edx\nloc_1285:\nmov eax, [rbp+var_5DE4]\nadd [rbp+var_5DE0], eax\nloc_1291:\ncmp [rbp+var_5DE0], 0BB7h\njle short loc_1232\nloc_129D:\nadd [rbp+var_5DE4], 1\nloc_12A4:\ncmp [rbp+var_5DE4], 0BB7h\njle loc_11F8\nmov [rbp+var_5DDC], 0\njmp loc_136B\nloc_12C3:\nmov [rbp+var_5DD8], 0\njmp short loc_1349\nloc_12CF:\nmov eax, [rbp+var_5DD8]\ncdqe\nmov edx, [rbp+rax*4+var_2EF0]\nmov eax, [rbp+var_5DD8]\nadd eax, 1\ncdqe\nmov eax, [rbp+rax*4+var_2EF0]\ncmp edx, eax\njle short loc_1342\nmov eax, [rbp+var_5DD8]\ncdqe\nmov eax, [rbp+rax*4+var_2EF0]\nmov [rbp+var_5DD4], eax\nmov eax, [rbp+var_5DD8]\nadd eax, 1\ncdqe\nmov edx, [rbp+rax*4+var_2EF0]\nmov eax, [rbp+var_5DD8]\ncdqe\nmov [rbp+rax*4+var_2EF0], edx\nmov eax, [rbp+var_5DD8]\nadd eax, 1\ncdqe\nmov edx, [rbp+var_5DD4]\nmov [rbp+rax*4+var_2EF0], edx\nloc_1342:\nadd [rbp+var_5DD8], 1\nloc_1349:\nmov eax, [rbp+var_5DE8]\nsub eax, [rbp+var_5DDC]\nsub eax, 1\ncmp [rbp+var_5DD8], eax\njl loc_12CF\nadd [rbp+var_5DDC], 1\nloc_136B:\nmov eax, [rbp+var_5DE8]\nsub eax, 1\ncmp [rbp+var_5DDC], eax\njl loc_12C3\nmov eax, [rbp+var_5DF4]\nsub eax, 1\ncdqe\nmov eax, [rbp+rax*4+var_2EF0]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_13A6\ncall ___stack_chk_fail\nlocret_13A6:\nleave\nretn", + "ida_strip_pseudo": "// bad sp value at call has been detected, the output may be wrong!\n__int64 __fastcall sub_1189(int a1)\n{\n int v1; // eax\n int v3; // [rsp+Ch] [rbp-5DE8h]\n int i; // [rsp+10h] [rbp-5DE4h]\n int j; // [rsp+14h] [rbp-5DE0h]\n int k; // [rsp+18h] [rbp-5DDCh]\n int m; // [rsp+1Ch] [rbp-5DD8h]\n int v8; // [rsp+20h] [rbp-5DD4h]\n _DWORD s[884]; // [rsp+24h] [rbp-5DD0h] BYREF\n _BYTE v10[16384]; // [rsp+DF4h] [rbp-5000h] BYREF\n _QWORD v11[512]; // [rsp+4DF4h] [rbp-1000h] BYREF\n\n while ( v11 != (_QWORD *)v10 )\n ;\n v11[511] = __readfsqword(0x28u);\n memset(s, 0, 0x2EE0uLL);\n v3 = 0;\n for ( i = 2; i <= 2999; ++i )\n {\n if ( !s[i] )\n {\n s[i] = 1;\n for ( j = 2 * i; j <= 2999; j += i )\n {\n if ( --s[j] == -3 )\n {\n v1 = v3++;\n *(_DWORD *)&v10[4 * v1 + 8464] = j;\n }\n }\n }\n }\n for ( k = 0; k < v3 - 1; ++k )\n {\n for ( m = 0; m < v3 - k - 1; ++m )\n {\n if ( *(_DWORD *)&v10[4 * m + 8464] > *(_DWORD *)&v10[4 * m + 8468] )\n {\n v8 = *(_DWORD *)&v10[4 * m + 8464];\n *(_DWORD *)&v10[4 * m + 8464] = *(_DWORD *)&v10[4 * m + 8468];\n *(_DWORD *)&v10[4 * m + 8468] = v8;\n }\n }\n }\n return *(unsigned int *)&v10[4 * a1 + 8460];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(int a1) {\n int v1;\n int v3;\n int i;\n int j;\n int k;\n int m;\n int v8;\n uint32_t s[884];\n uint8_t v10[16384];\n uint64_t v11[512];\n while (v11 != (uint64_t *)v10)\n ;\n v11[511] = __readfsqword(40u);\n memset(s, 0, 12000uLL);\n v3 = 0;\n for (i = 2; i <= 2999; ++i) {\n if (!s[i]) {\n s[i] = 1;\n for (j = 2 * i; j <= 2999; j += i) {\n if (--s[j] == -3) {\n v1 = v3++;\n *(uint32_t *)&v10[4 * v1 + 8464] = j;\n }\n }\n }\n }\n for (k = 0; k < v3 - 1; ++k) {\n for (m = 0; m < v3 - k - 1; ++m) {\n if (*(uint32_t *)&v10[4 * m + 8464] > *(uint32_t *)&v10[4 * m + 8468]) {\n v8 = *(uint32_t *)&v10[4 * m + 8464];\n *(uint32_t *)&v10[4 * m + 8464] = *(uint32_t *)&v10[4 * m + 8468];\n *(uint32_t *)&v10[4 * m + 8468] = v8;\n }\n }\n }\n return *(unsigned int *)&v10[4 * a1 + 8460];\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v3;\n int i;\n int j;\n int k;\n int m;\n int v8;\n uint32_t s[884];\n uint8_t v10[16384];\n uint64_t v11[512];\n while (v11 != (uint64_t *)v10)\n ;\n v11[511] = __readfsqword(40u);\n memset(s, 0, 12000uLL);\n v3 = 0;\n for (i = 2; i <= 2999; ++i) {\n if (!s[i]) {\n s[i] = 1;\n for (j = 2 * i; j <= 2999; j += i) {\n if (--s[j] == -3) {\n v1 = v3++;\n *(uint32_t *)&v10[4 * v1 + 8464] = j;\n }\n }\n }\n }\n for (k = 0; k < v3 - 1; ++k) {\n for (m = 0; m < v3 - k - 1; ++m) {\n if (*(uint32_t *)&v10[4 * m + 8464] > *(uint32_t *)&v10[4 * m + 8468]) {\n v8 = *(uint32_t *)&v10[4 * m + 8464];\n *(uint32_t *)&v10[4 * m + 8464] = *(uint32_t *)&v10[4 * m + 8468];\n *(uint32_t *)&v10[4 * m + 8468] = v8;\n }\n }\n }\n return *(unsigned int *)&v10[4 * a1 + 8460];\n}" + }, + { + "index": 122, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n#define MAX 3000\n\n\n\n", + "func": "int func0(int n) {\n int primes[MAX] = {0};\n int result[MAX], resultIndex = 0;\n for (int i = 2; i < MAX; i++) {\n if (primes[i] == 0) {\n primes[i] = 1;\n int j = i * 2;\n while (j < MAX) {\n primes[j] -= 1;\n if ((primes[j] + 3) == 0) {\n result[resultIndex++] = j;\n }\n j += i;\n }\n }\n }\n for (int i = 0; i < resultIndex - 1; i++) {\n for (int j = 0; j < resultIndex - i - 1; j++) {\n if (result[j] > result[j + 1]) {\n int temp = result[j];\n result[j] = result[j + 1];\n result[j + 1] = temp;\n }\n }\n }\n return result[n - 1];\n}", + "test": "int main() {\n\n assert(func0(1) == 30);\n\n assert(func0(50) == 273);\n\n assert(func0(1000) == 2664);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nlea -0x5000(%rsp),%r11\nsub $0x1000,%rsp\norq $0x0,(%rsp)\ncmp %r11,%rsp\njne 1196 \nsub $0xdd0,%rsp\nmov %edi,%ebx\nmov %fs:0x28,%rax\nmov %rax,0x5dc8(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nmov $0x2ee0,%edx\nmov $0x0,%esi\ncallq 1090 \nmov $0x2,%ecx\nmov $0x0,%edi\nmov %rsp,%rsi\njmp 1218 \nadd %rcx,%rax\ncmp $0xbb7,%eax\njg 120b \nmov (%rsi,%rax,4),%edx\nsub $0x1,%edx\nmov %edx,(%rsi,%rax,4)\ncmp $0xfffffffd,%edx\njne 11e4 \nmovslq %edi,%rdx\nmov %eax,0x2ee0(%rsp,%rdx,4)\nlea 0x1(%rdi),%edi\njmp 11e4 \nadd $0x1,%rcx\ncmp $0xbb8,%rcx\nje 1235 \ncmpl $0x0,(%rsi,%rcx,4)\njne 120b \nmovl $0x1,(%rsi,%rcx,4)\nlea (%rcx,%rcx,1),%eax\ncmp $0xbb7,%eax\njg 120b \nlea (%rcx,%rcx,1),%rax\njmp 11ee \nsub $0x1,%edi\ntest %edi,%edi\njle 1279 \nlea 0x2ee4(%rsp),%r8\njmp 1264 \nadd $0x4,%rax\ncmp %rax,%rsi\nje 125f \nmov (%rax),%edx\nmov 0x4(%rax),%ecx\ncmp %ecx,%edx\njle 1246 \nmov %ecx,(%rax)\nmov %edx,0x4(%rax)\njmp 1246 \nsub $0x1,%edi\nje 1279 \ntest %edi,%edi\njle 125f \nlea 0x2ee0(%rsp),%rax\nlea -0x1(%rdi),%edx\nlea (%r8,%rdx,4),%rsi\njmp 124f \nlea -0x1(%rbx),%eax\ncltq\nmov 0x2ee0(%rsp,%rax,4),%eax\nmov 0x5dc8(%rsp),%rbx\nxor %fs:0x28,%rbx\njne 12a1 \nadd $0x5dd0,%rsp\npop %rbx\nretq\ncallq 1070 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbx\nlea r11, [rsp+8+var_5008]\nloc_1196:\nsub rsp, 1000h\nor [rsp+1008h+var_1008], 0\ncmp rsp, r11\njnz short loc_1196\nsub rsp, 0DD0h\nmov ebx, edi\nmov rax, fs:28h\nmov [rsp+1DD8h+arg_3FE8], rax\nxor eax, eax\nmov rdi, rsp; s\nmov edx, 2EE0h; n\nmov esi, 0; c\ncall _memset\nmov r8d, 4\nmov ecx, 2\nmov edi, 0\nmov rsi, rsp\njmp short loc_1222\nloc_11EA:\nadd rax, rcx\ncmp eax, 0BB7h\njg short loc_1211\nloc_11F4:\nmov edx, [rsi+rax*4]\nsub edx, 1\nmov [rsi+rax*4], edx\ncmp edx, 0FFFFFFFDh\njnz short loc_11EA\nmovsxd rdx, edi\nmov [rsp+rdx*4+1DD8h+arg_1100], eax\nlea edi, [rdi+1]\njmp short loc_11EA\nloc_1211:\nadd rcx, 1\nadd r8, 2\ncmp rcx, 0BB8h\njz short loc_123D\nloc_1222:\ncmp dword ptr [rsi+rcx*4], 0\njnz short loc_1211\nmov dword ptr [rsi+rcx*4], 1\ncmp r8d, 0BB7h\njg short loc_1211\nmov rax, r8\njmp short loc_11F4\nloc_123D:\ncmp edi, 1\njle short loc_1283\nlea r8, [rsp+1DD8h+arg_1104]\njmp short loc_126D\nloc_124C:\nadd rax, 4\ncmp rax, rsi\njz short loc_1265\nloc_1255:\nmov edx, [rax]\nmov ecx, [rax+4]\ncmp edx, ecx\njle short loc_124C\nmov [rax], ecx\nmov [rax+4], edx\njmp short loc_124C\nloc_1265:\nsub edi, 1\ncmp edi, 1\njz short loc_1283\nloc_126D:\ncmp edi, 1\njle short loc_12AB\nlea rax, [rsp+1DD8h+arg_1100]\nlea edx, [rdi-2]\nlea rsi, [r8+rdx*4]\njmp short loc_1255\nloc_1283:\nlea eax, [rbx-1]\ncdqe\nmov eax, [rsp+rax*4+1DD8h+arg_1100]\nmov rdx, [rsp+1DD8h+arg_3FE8]\nsub rdx, fs:28h\njnz short loc_12B0\nadd rsp, 5DD0h\npop rbx\nretn\nloc_12AB:\nsub edi, 1\njmp short loc_126D\nloc_12B0:\ncall ___stack_chk_fail", + "ida_pseudo": "// positive sp value has been detected, the output may be wrong!\n__int64 __fastcall func0(int a1)\n{\n __int64 v2; // r8\n __int64 v3; // rcx\n int v4; // edi\n __int64 v5; // rax\n int v6; // edx\n _QWORD *v7; // rax\n int v8; // edx\n int v9; // ecx\n _DWORD v11[884]; // [rsp-DD0h] [rbp-5DD8h] BYREF\n char v12; // [rsp+0h] [rbp-5008h] BYREF\n __int64 v13; // [rsp+1000h] [rbp-4008h] BYREF\n _QWORD v14[1503]; // [rsp+2110h] [rbp-2EF8h] BYREF\n\n while ( &v12 != (char *)(&v13 - 2560) )\n ;\n v14[1501] = __readfsqword(0x28u);\n memset(v11, 0, 0x2EE0uLL);\n v2 = 4LL;\n v3 = 2LL;\n v4 = 0;\n do\n {\n if ( !v11[v3] )\n {\n v11[v3] = 1;\n if ( (int)v2 <= 2999 )\n {\n v5 = v2;\n do\n {\n v6 = v11[v5] - 1;\n v11[v5] = v6;\n if ( v6 == -3 )\n *((_DWORD *)v14 + v4++) = v5;\n v5 += v3;\n }\n while ( (int)v5 <= 2999 );\n }\n }\n ++v3;\n v2 += 2LL;\n }\n while ( v3 != 3000 );\n if ( v4 > 1 )\n {\n do\n {\n while ( v4 <= 1 )\n --v4;\n v7 = v14;\n do\n {\n v8 = *(_DWORD *)v7;\n v9 = *((_DWORD *)v7 + 1);\n if ( *(_DWORD *)v7 > v9 )\n {\n *(_DWORD *)v7 = v9;\n *((_DWORD *)v7 + 1) = v8;\n }\n v7 = (_QWORD *)((char *)v7 + 4);\n }\n while ( v7 != (_QWORD *)((char *)v14 + 4 * (unsigned int)(v4 - 2) + 4) );\n --v4;\n }\n while ( v4 != 1 );\n }\n return *((unsigned int *)v14 + a1 - 1);\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbx\nlea r11, [rsp+8+var_5008]\nloc_1196:\nsub rsp, 1000h\nor [rsp+1008h+var_1008], 0\ncmp rsp, r11\njnz short loc_1196\nsub rsp, 0DD0h\nmov ebx, edi\nmov rax, fs:28h\nmov [rsp+1DD8h+arg_3FE8], rax\nxor eax, eax\nmov rdi, rsp; s\nmov edx, 2EE0h; n\nmov esi, 0; c\ncall _memset\nmov r8d, 4\nmov ecx, 2\nmov edi, 0\nmov rsi, rsp\njmp short loc_1222\nloc_11EA:\nadd rax, rcx\ncmp eax, 0BB7h\njg short loc_1211\nloc_11F4:\nmov edx, [rsi+rax*4]\nsub edx, 1\nmov [rsi+rax*4], edx\ncmp edx, 0FFFFFFFDh\njnz short loc_11EA\nmovsxd rdx, edi\nmov [rsp+rdx*4+1DD8h+arg_1100], eax\nlea edi, [rdi+1]\njmp short loc_11EA\nloc_1211:\nadd rcx, 1\nadd r8, 2\ncmp rcx, 0BB8h\njz short loc_123D\nloc_1222:\ncmp dword ptr [rsi+rcx*4], 0\njnz short loc_1211\nmov dword ptr [rsi+rcx*4], 1\ncmp r8d, 0BB7h\njg short loc_1211\nmov rax, r8\njmp short loc_11F4\nloc_123D:\ncmp edi, 1\njle short loc_1283\nlea r8, [rsp+1DD8h+arg_1104]\njmp short loc_126D\nloc_124C:\nadd rax, 4\ncmp rax, rsi\njz short loc_1265\nloc_1255:\nmov edx, [rax]\nmov ecx, [rax+4]\ncmp edx, ecx\njle short loc_124C\nmov [rax], ecx\nmov [rax+4], edx\njmp short loc_124C\nloc_1265:\nsub edi, 1\ncmp edi, 1\njz short loc_1283\nloc_126D:\ncmp edi, 1\njle short loc_12AB\nlea rax, [rsp+1DD8h+arg_1100]\nlea edx, [rdi-2]\nlea rsi, [r8+rdx*4]\njmp short loc_1255\nloc_1283:\nlea eax, [rbx-1]\ncdqe\nmov eax, [rsp+rax*4+1DD8h+arg_1100]\nmov rdx, [rsp+1DD8h+arg_3FE8]\nsub rdx, fs:28h\njnz short loc_12B0\nadd rsp, 5DD0h\npop rbx\nretn\nloc_12AB:\nsub edi, 1\njmp short loc_126D\nloc_12B0:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "// positive sp value has been detected, the output may be wrong!\n__int64 __fastcall sub_1189(int a1)\n{\n __int64 v2; // r8\n __int64 v3; // rcx\n int v4; // edi\n __int64 v5; // rax\n int v6; // edx\n _QWORD *v7; // rax\n int v8; // edx\n int v9; // ecx\n _DWORD v11[884]; // [rsp-DD0h] [rbp-5DD8h] BYREF\n char v12; // [rsp+0h] [rbp-5008h] BYREF\n __int64 v13; // [rsp+1000h] [rbp-4008h] BYREF\n _QWORD v14[1503]; // [rsp+2110h] [rbp-2EF8h] BYREF\n\n while ( &v12 != (char *)(&v13 - 2560) )\n ;\n v14[1501] = __readfsqword(0x28u);\n memset(v11, 0, 0x2EE0uLL);\n v2 = 4LL;\n v3 = 2LL;\n v4 = 0;\n do\n {\n if ( !v11[v3] )\n {\n v11[v3] = 1;\n if ( (int)v2 <= 2999 )\n {\n v5 = v2;\n do\n {\n v6 = v11[v5] - 1;\n v11[v5] = v6;\n if ( v6 == -3 )\n *((_DWORD *)v14 + v4++) = v5;\n v5 += v3;\n }\n while ( (int)v5 <= 2999 );\n }\n }\n ++v3;\n v2 += 2LL;\n }\n while ( v3 != 3000 );\n if ( v4 > 1 )\n {\n do\n {\n while ( v4 <= 1 )\n --v4;\n v7 = v14;\n do\n {\n v8 = *(_DWORD *)v7;\n v9 = *((_DWORD *)v7 + 1);\n if ( *(_DWORD *)v7 > v9 )\n {\n *(_DWORD *)v7 = v9;\n *((_DWORD *)v7 + 1) = v8;\n }\n v7 = (_QWORD *)((char *)v7 + 4);\n }\n while ( v7 != (_QWORD *)((char *)v14 + 4 * (unsigned int)(v4 - 2) + 4) );\n --v4;\n }\n while ( v4 != 1 );\n }\n return *((unsigned int *)v14 + a1 - 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(int a1) {\n long long v2;\n long long v3;\n int v4;\n long long v5;\n int v6;\n uint64_t *v7;\n int v8;\n int v9;\n uint32_t v11[884];\n char v12;\n long long v13;\n uint64_t v14[1503];\n while (&v12 != (char *)(&v13 - 2560))\n ;\n v14[1501] = __readfsqword(40u);\n memset(v11, 0, 12000uLL);\n v2 = 4LL;\n v3 = 2LL;\n v4 = 0;\n do {\n if (!v11[v3]) {\n v11[v3] = 1;\n if ((int)v2 <= 2999) {\n v5 = v2;\n do {\n v6 = v11[v5] - 1;\n v11[v5] = v6;\n if (v6 == -3) *((uint32_t *)v14 + v4++) = v5;\n v5 += v3;\n } while ((int)v5 <= 2999);\n }\n }\n ++v3;\n v2 += 2LL;\n } while (v3 != 3000);\n if (v4 > 1) {\n do {\n while (v4 <= 1) --v4;\n v7 = v14;\n do {\n v8 = *(uint32_t *)v7;\n v9 = *((uint32_t *)v7 + 1);\n if (*(uint32_t *)v7 > v9) {\n *(uint32_t *)v7 = v9;\n *((uint32_t *)v7 + 1) = v8;\n }\n v7 = (uint64_t *)((char *)v7 + 4);\n } while (v7 !=\n (uint64_t *)((char *)v14 + 4 * (unsigned int)(v4 - 2) + 4));\n --v4;\n } while (v4 != 1);\n }\n return *((unsigned int *)v14 + a1 - 1);\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n long long v2;\n long long v3;\n int v4;\n long long v5;\n int v6;\n uint64_t *v7;\n int v8;\n int v9;\n uint32_t v11[884];\n char v12;\n long long v13;\n uint64_t v14[1503];\n while (&v12 != (char *)(&v13 - 2560))\n ;\n v14[1501] = __readfsqword(40u);\n memset(v11, 0, 12000uLL);\n v2 = 4LL;\n v3 = 2LL;\n v4 = 0;\n do {\n if (!v11[v3]) {\n v11[v3] = 1;\n if ((int)v2 <= 2999) {\n v5 = v2;\n do {\n v6 = v11[v5] - 1;\n v11[v5] = v6;\n if (v6 == -3) *((uint32_t *)v14 + v4++) = v5;\n v5 += v3;\n } while ((int)v5 <= 2999);\n }\n }\n ++v3;\n v2 += 2LL;\n } while (v3 != 3000);\n if (v4 > 1) {\n do {\n while (v4 <= 1) --v4;\n v7 = v14;\n do {\n v8 = *(uint32_t *)v7;\n v9 = *((uint32_t *)v7 + 1);\n if (*(uint32_t *)v7 > v9) {\n *(uint32_t *)v7 = v9;\n *((uint32_t *)v7 + 1) = v8;\n }\n v7 = (uint64_t *)((char *)v7 + 4);\n } while (v7 !=\n (uint64_t *)((char *)v14 + 4 * (unsigned int)(v4 - 2) + 4));\n --v4;\n } while (v4 != 1);\n }\n return *((unsigned int *)v14 + a1 - 1);\n}" + }, + { + "index": 122, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n#define MAX 3000\n\n\n\n", + "func": "int func0(int n) {\n int primes[MAX] = {0};\n int result[MAX], resultIndex = 0;\n for (int i = 2; i < MAX; i++) {\n if (primes[i] == 0) {\n primes[i] = 1;\n int j = i * 2;\n while (j < MAX) {\n primes[j] -= 1;\n if ((primes[j] + 3) == 0) {\n result[resultIndex++] = j;\n }\n j += i;\n }\n }\n }\n for (int i = 0; i < resultIndex - 1; i++) {\n for (int j = 0; j < resultIndex - i - 1; j++) {\n if (result[j] > result[j + 1]) {\n int temp = result[j];\n result[j] = result[j + 1];\n result[j + 1] = temp;\n }\n }\n }\n return result[n - 1];\n}", + "test": "int main() {\n\n assert(func0(1) == 30);\n\n assert(func0(50) == 273);\n\n assert(func0(1000) == 2664);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nlea -0x5000(%rsp),%r11\nsub $0x1000,%rsp\norq $0x0,(%rsp)\ncmp %r11,%rsp\njne 123d \nsub $0xdd0,%rsp\nxor %esi,%esi\nmov $0x2ee0,%edx\nmov %fs:0x28,%rax\nmov %rax,0x5dc8(%rsp)\nxor %eax,%eax\nmov %edi,%ebx\nmov %rsp,%rdi\ncallq 1090 \nmov $0x2,%ecx\nxor %esi,%esi\nmov %rax,%rdi\nxor %eax,%eax\njmp 12a0 \nnopw 0x0(%rax,%rax,1)\nadd $0x1,%rcx\ncmp $0xbb8,%rcx\nje 12f2 \nmov (%rdi,%rcx,4),%eax\ntest %eax,%eax\njne 1290 \nlea (%rcx,%rcx,1),%eax\nmovl $0x1,(%rdi,%rcx,4)\ncmp $0xbb7,%eax\nja 1290 \nlea (%rcx,%rcx,1),%rax\nnopl 0x0(%rax)\nmov (%rdi,%rax,4),%edx\nsub $0x1,%edx\nmov %edx,(%rdi,%rax,4)\ncmp $0xfffffffd,%edx\njne 12db \nmovslq %esi,%rdx\nadd $0x1,%esi\nmov %eax,0x2ee0(%rsp,%rdx,4)\nadd %rcx,%rax\ncmp $0xbb7,%eax\njle 12c0 \nadd $0x1,%rcx\ncmp $0xbb8,%rcx\njne 129d \nsub $0x1,%esi\ntest %esi,%esi\njle 133b \nlea 0x2ee0(%rsp),%r9\nlea 0x2ee4(%rsp),%r8\nnopl 0x0(%rax)\nlea -0x1(%rsi),%edx\nmov %r9,%rax\nmov %rdx,%rsi\nlea (%r8,%rdx,4),%rdi\nnopl (%rax)\nmov (%rax),%edx\nmov 0x4(%rax),%ecx\ncmp %ecx,%edx\njle 132e \nmov %ecx,(%rax)\nmov %edx,0x4(%rax)\nadd $0x4,%rax\ncmp %rdi,%rax\njne 1320 \ntest %esi,%esi\njne 1310 \nlea -0x1(%rbx),%eax\nmov 0x5dc8(%rsp),%rbx\nxor %fs:0x28,%rbx\ncltq\nmov 0x2ee0(%rsp,%rax,4),%eax\njne 1363 \nadd $0x5dd0,%rsp\npop %rbx\nretq\ncallq 1070 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nlea r11, [rsp+8+var_5008]\nloc_123D:\nsub rsp, 1000h\nor [rsp+1008h+var_1008], 0\ncmp rsp, r11\njnz short loc_123D\nsub rsp, 0DD0h\nxor esi, esi; c\nmov edx, 2EE0h; n\nmov rax, fs:28h\nmov [rsp+1DD8h+arg_3FE8], rax\nxor eax, eax\nmov ebx, edi\nmov rdi, rsp; s\ncall _memset\nmov r8d, 4\nmov ecx, 2\nxor esi, esi\nmov rdi, rax\njmp short loc_12A1\nloc_1290:\nadd rcx, 1\nadd r8, 2\ncmp rcx, 0BB8h\njz short loc_12E7\nloc_12A1:\nmov eax, [rdi+rcx*4]\ntest eax, eax\njnz short loc_1290\nmov dword ptr [rdi+rcx*4], 1\ncmp r8, 0BB7h\nja short loc_1290\nmov rax, r8\nnop dword ptr [rax+rax+00h]\nloc_12C0:\nmov edx, [rdi+rax*4]\nsub edx, 1\nmov [rdi+rax*4], edx\ncmp edx, 0FFFFFFFDh\njnz short loc_12DB\nmovsxd rdx, esi\nadd esi, 1\nmov [rsp+rdx*4+1DD8h+arg_1100], eax\nloc_12DB:\nadd rax, rcx\ncmp eax, 0BB7h\njle short loc_12C0\njmp short loc_1290\nloc_12E7:\ncmp esi, 1\njle short loc_133F\nlea r9, [rsp+1DD8h+arg_1100]\nlea r8, [rsp+1DD8h+arg_1104]\nnop dword ptr [rax+00h]\nloc_1300:\ncmp esi, 1\njle short loc_1367\nlea edx, [rsi-2]\nmov rax, r9\nlea rdi, [r8+rdx*4]\nnop\nloc_1310:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd ecx, xmm0\nmovd edx, xmm1\ncmp ecx, edx\njle short loc_132E\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_132E:\nadd rax, 4\ncmp rax, rdi\njnz short loc_1310\nsub esi, 1\ncmp esi, 1\njnz short loc_1300\nloc_133F:\nlea eax, [rbx-1]\ncdqe\nmov eax, [rsp+rax*4+1DD8h+arg_1100]\nmov rdx, [rsp+1DD8h+arg_3FE8]\nsub rdx, fs:28h\njnz short loc_136C\nadd rsp, 5DD0h\npop rbx\nretn\nloc_1367:\nsub esi, 1\njmp short loc_1300\nloc_136C:\ncall ___stack_chk_fail", + "ida_pseudo": "// positive sp value has been detected, the output may be wrong!\n__int64 __fastcall func0(int a1)\n{\n _DWORD *v2; // rax\n unsigned __int64 v3; // r8\n __int64 v4; // rcx\n int v5; // esi\n _DWORD *v6; // rdi\n unsigned __int64 v7; // rax\n int v8; // edx\n __int64 v9; // rdx\n __m128i *v10; // rax\n __m128i v11; // xmm0\n __int64 v13; // [rsp-DD0h] [rbp-5DD8h] BYREF\n char v14; // [rsp+0h] [rbp-5008h] BYREF\n __int64 v15; // [rsp+1000h] [rbp-4008h] BYREF\n _QWORD v16[1503]; // [rsp+2110h] [rbp-2EF8h] BYREF\n\n while ( &v14 != (char *)(&v15 - 2560) )\n ;\n v16[1501] = __readfsqword(0x28u);\n v2 = memset(&v13, 0, 0x2EE0uLL);\n v3 = 4LL;\n v4 = 2LL;\n v5 = 0;\n v6 = v2;\n do\n {\n if ( !v6[v4] )\n {\n v6[v4] = 1;\n if ( v3 <= 0xBB7 )\n {\n v7 = v3;\n do\n {\n v8 = v6[v7] - 1;\n v6[v7] = v8;\n if ( v8 == -3 )\n {\n v9 = v5++;\n *((_DWORD *)v16 + v9) = v7;\n }\n v7 += v4;\n }\n while ( (int)v7 <= 2999 );\n }\n }\n ++v4;\n v3 += 2LL;\n }\n while ( v4 != 3000 );\n if ( v5 > 1 )\n {\n do\n {\n while ( v5 <= 1 )\n --v5;\n v10 = (__m128i *)v16;\n do\n {\n v11 = _mm_loadl_epi64(v10);\n if ( _mm_cvtsi128_si32(v11) > _mm_cvtsi128_si32(_mm_shuffle_epi32(v11, 229)) )\n v10->m128i_i64[0] = _mm_shuffle_epi32(v11, 225).m128i_u64[0];\n v10 = (__m128i *)((char *)v10 + 4);\n }\n while ( v10 != (__m128i *)((char *)v16 + 4 * (unsigned int)(v5 - 2) + 4) );\n --v5;\n }\n while ( v5 != 1 );\n }\n return *((unsigned int *)v16 + a1 - 1);\n}", + "ida_strip_asm": "sub_1230:\nendbr64\npush rbx\nlea r11, [rsp+8+var_5008]\nloc_123D:\nsub rsp, 1000h\nor [rsp+1008h+var_1008], 0\ncmp rsp, r11\njnz short loc_123D\nsub rsp, 0DD0h\nxor esi, esi; c\nmov edx, 2EE0h; n\nmov rax, fs:28h\nmov [rsp+1DD8h+arg_3FE8], rax\nxor eax, eax\nmov ebx, edi\nmov rdi, rsp; s\ncall _memset\nmov r8d, 4\nmov ecx, 2\nxor esi, esi\nmov rdi, rax\njmp short loc_12A1\nloc_1290:\nadd rcx, 1\nadd r8, 2\ncmp rcx, 0BB8h\njz short loc_12E7\nloc_12A1:\nmov eax, [rdi+rcx*4]\ntest eax, eax\njnz short loc_1290\nmov dword ptr [rdi+rcx*4], 1\ncmp r8, 0BB7h\nja short loc_1290\nmov rax, r8\nnop dword ptr [rax+rax+00h]\nloc_12C0:\nmov edx, [rdi+rax*4]\nsub edx, 1\nmov [rdi+rax*4], edx\ncmp edx, 0FFFFFFFDh\njnz short loc_12DB\nmovsxd rdx, esi\nadd esi, 1\nmov [rsp+rdx*4+1DD8h+arg_1100], eax\nloc_12DB:\nadd rax, rcx\ncmp eax, 0BB7h\njle short loc_12C0\njmp short loc_1290\nloc_12E7:\ncmp esi, 1\njle short loc_133F\nlea r9, [rsp+1DD8h+arg_1100]\nlea r8, [rsp+1DD8h+arg_1104]\nnop dword ptr [rax+00h]\nloc_1300:\ncmp esi, 1\njle short loc_1367\nlea edx, [rsi-2]\nmov rax, r9\nlea rdi, [r8+rdx*4]\nnop\nloc_1310:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd ecx, xmm0\nmovd edx, xmm1\ncmp ecx, edx\njle short loc_132E\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_132E:\nadd rax, 4\ncmp rax, rdi\njnz short loc_1310\nsub esi, 1\ncmp esi, 1\njnz short loc_1300\nloc_133F:\nlea eax, [rbx-1]\ncdqe\nmov eax, [rsp+rax*4+1DD8h+arg_1100]\nmov rdx, [rsp+1DD8h+arg_3FE8]\nsub rdx, fs:28h\njnz short loc_136C\nadd rsp, 5DD0h\npop rbx\nretn\nloc_1367:\nsub esi, 1\njmp short loc_1300\nloc_136C:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "// positive sp value has been detected, the output may be wrong!\n__int64 __fastcall sub_1230(int a1)\n{\n _DWORD *v2; // rax\n unsigned __int64 v3; // r8\n __int64 v4; // rcx\n int v5; // esi\n _DWORD *v6; // rdi\n unsigned __int64 v7; // rax\n int v8; // edx\n __int64 v9; // rdx\n __m128i *v10; // rax\n __m128i v11; // xmm0\n __int64 v13; // [rsp-DD0h] [rbp-5DD8h] BYREF\n char v14; // [rsp+0h] [rbp-5008h] BYREF\n __int64 v15; // [rsp+1000h] [rbp-4008h] BYREF\n _QWORD v16[1503]; // [rsp+2110h] [rbp-2EF8h] BYREF\n\n while ( &v14 != (char *)(&v15 - 2560) )\n ;\n v16[1501] = __readfsqword(0x28u);\n v2 = memset(&v13, 0, 0x2EE0uLL);\n v3 = 4LL;\n v4 = 2LL;\n v5 = 0;\n v6 = v2;\n do\n {\n if ( !v6[v4] )\n {\n v6[v4] = 1;\n if ( v3 <= 0xBB7 )\n {\n v7 = v3;\n do\n {\n v8 = v6[v7] - 1;\n v6[v7] = v8;\n if ( v8 == -3 )\n {\n v9 = v5++;\n *((_DWORD *)v16 + v9) = v7;\n }\n v7 += v4;\n }\n while ( (int)v7 <= 2999 );\n }\n }\n ++v4;\n v3 += 2LL;\n }\n while ( v4 != 3000 );\n if ( v5 > 1 )\n {\n do\n {\n while ( v5 <= 1 )\n --v5;\n v10 = (__m128i *)v16;\n do\n {\n v11 = _mm_loadl_epi64(v10);\n if ( _mm_cvtsi128_si32(v11) > _mm_cvtsi128_si32(_mm_shuffle_epi32(v11, 229)) )\n v10->m128i_i64[0] = _mm_shuffle_epi32(v11, 225).m128i_u64[0];\n v10 = (__m128i *)((char *)v10 + 4);\n }\n while ( v10 != (__m128i *)((char *)v16 + 4 * (unsigned int)(v5 - 2) + 4) );\n --v5;\n }\n while ( v5 != 1 );\n }\n return *((unsigned int *)v16 + a1 - 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1230(int a1) {\n uint32_t *v2;\n unsigned long long v3;\n long long v4;\n int v5;\n uint32_t *v6;\n unsigned long long v7;\n int v8;\n long long v9;\n __m128i *v10;\n __m128i v11;\n long long v13;\n char v14;\n long long v15;\n uint64_t v16[1503];\n while (&v14 != (char *)(&v15 - 2560))\n ;\n v16[1501] = __readfsqword(40u);\n v2 = memset(&v13, 0, 12000uLL);\n v3 = 4LL;\n v4 = 2LL;\n v5 = 0;\n v6 = v2;\n do {\n if (!v6[v4]) {\n v6[v4] = 1;\n if (v3 <= 2999) {\n v7 = v3;\n do {\n v8 = v6[v7] - 1;\n v6[v7] = v8;\n if (v8 == -3) {\n v9 = v5++;\n *((uint32_t *)v16 + v9) = v7;\n }\n v7 += v4;\n } while ((int)v7 <= 2999);\n }\n }\n ++v4;\n v3 += 2LL;\n } while (v4 != 3000);\n if (v5 > 1) {\n do {\n while (v5 <= 1) --v5;\n v10 = (__m128i *)v16;\n do {\n v11 = _mm_loadl_epi64(v10);\n if (_mm_cvtsi128_si32(v11) >\n _mm_cvtsi128_si32(_mm_shuffle_epi32(v11, 229)))\n v10->m128i_i64[0] = _mm_shuffle_epi32(v11, 225).m128i_u64[0];\n v10 = (__m128i *)((char *)v10 + 4);\n } while (v10 !=\n (__m128i *)((char *)v16 + 4 * (unsigned int)(v5 - 2) + 4));\n --v5;\n } while (v5 != 1);\n }\n return *((unsigned int *)v16 + a1 - 1);\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n uint32_t *v2;\n unsigned long long v3;\n long long v4;\n int v5;\n uint32_t *v6;\n unsigned long long v7;\n int v8;\n long long v9;\n __m128i *v10;\n __m128i v11;\n long long v13;\n char v14;\n long long v15;\n uint64_t v16[1503];\n while (&v14 != (char *)(&v15 - 2560))\n ;\n v16[1501] = __readfsqword(40u);\n v2 = memset(&v13, 0, 12000uLL);\n v3 = 4LL;\n v4 = 2LL;\n v5 = 0;\n v6 = v2;\n do {\n if (!v6[v4]) {\n v6[v4] = 1;\n if (v3 <= 2999) {\n v7 = v3;\n do {\n v8 = v6[v7] - 1;\n v6[v7] = v8;\n if (v8 == -3) {\n v9 = v5++;\n *((uint32_t *)v16 + v9) = v7;\n }\n v7 += v4;\n } while ((int)v7 <= 2999);\n }\n }\n ++v4;\n v3 += 2LL;\n } while (v4 != 3000);\n if (v5 > 1) {\n do {\n while (v5 <= 1) --v5;\n v10 = (__m128i *)v16;\n do {\n v11 = _mm_loadl_epi64(v10);\n if (_mm_cvtsi128_si32(v11) >\n _mm_cvtsi128_si32(_mm_shuffle_epi32(v11, 229)))\n v10->m128i_i64[0] = _mm_shuffle_epi32(v11, 225).m128i_u64[0];\n v10 = (__m128i *)((char *)v10 + 4);\n } while (v10 !=\n (__m128i *)((char *)v16 + 4 * (unsigned int)(v5 - 2) + 4));\n --v5;\n } while (v5 != 1);\n }\n return *((unsigned int *)v16 + a1 - 1);\n}" + }, + { + "index": 122, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n#define MAX 3000\n\n\n\n", + "func": "int func0(int n) {\n int primes[MAX] = {0};\n int result[MAX], resultIndex = 0;\n for (int i = 2; i < MAX; i++) {\n if (primes[i] == 0) {\n primes[i] = 1;\n int j = i * 2;\n while (j < MAX) {\n primes[j] -= 1;\n if ((primes[j] + 3) == 0) {\n result[resultIndex++] = j;\n }\n j += i;\n }\n }\n }\n for (int i = 0; i < resultIndex - 1; i++) {\n for (int j = 0; j < resultIndex - i - 1; j++) {\n if (result[j] > result[j + 1]) {\n int temp = result[j];\n result[j] = result[j + 1];\n result[j + 1] = temp;\n }\n }\n }\n return result[n - 1];\n}", + "test": "int main() {\n\n assert(func0(1) == 30);\n\n assert(func0(50) == 273);\n\n assert(func0(1000) == 2664);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nlea -0x5000(%rsp),%r11\nsub $0x1000,%rsp\norq $0x0,(%rsp)\ncmp %r11,%rsp\njne 123d \nsub $0xdd0,%rsp\nxor %esi,%esi\nmov $0x2ee0,%edx\nmov %fs:0x28,%rax\nmov %rax,0x5dc8(%rsp)\nxor %eax,%eax\nmov %edi,%ebx\nmov %rsp,%rdi\ncallq 1090 \nmov $0x2,%ecx\nxor %esi,%esi\nmov %rax,%rdi\njmp 1295 \nnopl (%rax)\nadd $0x1,%rcx\ncmp $0xbb8,%rcx\nje 12ea \nmov (%rdi,%rcx,4),%eax\ntest %eax,%eax\njne 1288 \nlea (%rcx,%rcx,1),%eax\nmovl $0x1,(%rdi,%rcx,4)\ncmp $0xbb7,%eax\nja 1288 \nlea (%rcx,%rcx,1),%rax\nnopl 0x0(%rax)\nmov (%rdi,%rax,4),%edx\nsub $0x1,%edx\nmov %edx,(%rdi,%rax,4)\ncmp $0xfffffffd,%edx\njne 12d3 \nmovslq %esi,%rdx\nadd $0x1,%esi\nmov %eax,0x2ee0(%rsp,%rdx,4)\nadd %rcx,%rax\ncmp $0xbb7,%eax\njle 12b8 \nadd $0x1,%rcx\ncmp $0xbb8,%rcx\njne 1295 \nsub $0x1,%esi\ntest %esi,%esi\njle 1333 \nlea 0x2ee0(%rsp),%r9\nlea 0x2ee4(%rsp),%r8\nnopl 0x0(%rax)\nlea -0x1(%rsi),%edx\nmov %r9,%rax\nmov %rdx,%rsi\nlea (%r8,%rdx,4),%rdi\nnopl (%rax)\nmov (%rax),%edx\nmov 0x4(%rax),%ecx\ncmp %ecx,%edx\njle 1326 \nmov %ecx,(%rax)\nmov %edx,0x4(%rax)\nadd $0x4,%rax\ncmp %rdi,%rax\njne 1318 \ntest %esi,%esi\njne 1308 \nlea -0x1(%rbx),%eax\nmov 0x5dc8(%rsp),%rbx\nxor %fs:0x28,%rbx\ncltq\nmov 0x2ee0(%rsp,%rax,4),%eax\njne 135b \nadd $0x5dd0,%rsp\npop %rbx\nretq\ncallq 1070 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbx\nlea r11, [rsp+8+var_5008]\nloc_123D:\nsub rsp, 1000h\nor [rsp+1008h+var_1008], 0\ncmp rsp, r11\njnz short loc_123D\nsub rsp, 0DD0h\nxor esi, esi; c\nmov edx, 2EE0h; n\nmov rax, fs:28h\nmov [rsp+1DD8h+arg_3FE8], rax\nxor eax, eax\nmov ebx, edi\nmov rdi, rsp; s\ncall _memset\nmov r8d, 4\nmov ecx, 2\nxor esi, esi\nmov rdi, rax\njmp short loc_12A1\nloc_1290:\nadd rcx, 1\nadd r8, 2\ncmp rcx, 0BB8h\njz short loc_12E7\nloc_12A1:\nmov eax, [rdi+rcx*4]\ntest eax, eax\njnz short loc_1290\nmov dword ptr [rdi+rcx*4], 1\ncmp r8, 0BB7h\nja short loc_1290\nmov rax, r8\nnop dword ptr [rax+rax+00h]\nloc_12C0:\nmov edx, [rdi+rax*4]\nsub edx, 1\nmov [rdi+rax*4], edx\ncmp edx, 0FFFFFFFDh\njnz short loc_12DB\nmovsxd rdx, esi\nadd esi, 1\nmov [rsp+rdx*4+1DD8h+arg_1100], eax\nloc_12DB:\nadd rax, rcx\ncmp eax, 0BB7h\njle short loc_12C0\njmp short loc_1290\nloc_12E7:\ncmp esi, 1\njle short loc_133F\nlea r9, [rsp+1DD8h+arg_1100]\nlea r8, [rsp+1DD8h+arg_1104]\nnop dword ptr [rax+00h]\nloc_1300:\ncmp esi, 1\njle short loc_1367\nlea edx, [rsi-2]\nmov rax, r9\nlea rdi, [r8+rdx*4]\nnop\nloc_1310:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd edx, xmm0\nmovd ecx, xmm1\ncmp ecx, edx\njge short loc_132E\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_132E:\nadd rax, 4\ncmp rax, rdi\njnz short loc_1310\nsub esi, 1\ncmp esi, 1\njnz short loc_1300\nloc_133F:\nlea eax, [rbx-1]\ncdqe\nmov eax, [rsp+rax*4+1DD8h+arg_1100]\nmov rdx, [rsp+1DD8h+arg_3FE8]\nsub rdx, fs:28h\njnz short loc_136C\nadd rsp, 5DD0h\npop rbx\nretn\nloc_1367:\nsub esi, 1\njmp short loc_1300\nloc_136C:\ncall ___stack_chk_fail", + "ida_pseudo": "// positive sp value has been detected, the output may be wrong!\n__int64 __fastcall func0(int a1)\n{\n _DWORD *v2; // rax\n unsigned __int64 v3; // r8\n __int64 v4; // rcx\n int v5; // esi\n _DWORD *v6; // rdi\n unsigned __int64 v7; // rax\n int v8; // edx\n __int64 v9; // rdx\n __m128i *v10; // rax\n __m128i v11; // xmm0\n __int64 v13; // [rsp-DD0h] [rbp-5DD8h] BYREF\n char v14; // [rsp+0h] [rbp-5008h] BYREF\n __int64 v15; // [rsp+1000h] [rbp-4008h] BYREF\n _QWORD v16[1503]; // [rsp+2110h] [rbp-2EF8h] BYREF\n\n while ( &v14 != (char *)(&v15 - 2560) )\n ;\n v16[1501] = __readfsqword(0x28u);\n v2 = memset(&v13, 0, 0x2EE0uLL);\n v3 = 4LL;\n v4 = 2LL;\n v5 = 0;\n v6 = v2;\n do\n {\n if ( !v6[v4] )\n {\n v6[v4] = 1;\n if ( v3 <= 0xBB7 )\n {\n v7 = v3;\n do\n {\n v8 = v6[v7] - 1;\n v6[v7] = v8;\n if ( v8 == -3 )\n {\n v9 = v5++;\n *((_DWORD *)v16 + v9) = v7;\n }\n v7 += v4;\n }\n while ( (int)v7 <= 2999 );\n }\n }\n ++v4;\n v3 += 2LL;\n }\n while ( v4 != 3000 );\n if ( v5 > 1 )\n {\n do\n {\n while ( v5 <= 1 )\n --v5;\n v10 = (__m128i *)v16;\n do\n {\n v11 = _mm_loadl_epi64(v10);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v11, 229)) < _mm_cvtsi128_si32(v11) )\n v10->m128i_i64[0] = _mm_shuffle_epi32(v11, 225).m128i_u64[0];\n v10 = (__m128i *)((char *)v10 + 4);\n }\n while ( v10 != (__m128i *)((char *)v16 + 4 * (unsigned int)(v5 - 2) + 4) );\n --v5;\n }\n while ( v5 != 1 );\n }\n return *((unsigned int *)v16 + a1 - 1);\n}", + "ida_strip_asm": "sub_1230:\nendbr64\npush rbx\nlea r11, [rsp+8+var_5008]\nloc_123D:\nsub rsp, 1000h\nor [rsp+1008h+var_1008], 0\ncmp rsp, r11\njnz short loc_123D\nsub rsp, 0DD0h\nxor esi, esi; c\nmov edx, 2EE0h; n\nmov rax, fs:28h\nmov [rsp+1DD8h+arg_3FE8], rax\nxor eax, eax\nmov ebx, edi\nmov rdi, rsp; s\ncall _memset\nmov r8d, 4\nmov ecx, 2\nxor esi, esi\nmov rdi, rax\njmp short loc_12A1\nloc_1290:\nadd rcx, 1\nadd r8, 2\ncmp rcx, 0BB8h\njz short loc_12E7\nloc_12A1:\nmov eax, [rdi+rcx*4]\ntest eax, eax\njnz short loc_1290\nmov dword ptr [rdi+rcx*4], 1\ncmp r8, 0BB7h\nja short loc_1290\nmov rax, r8\nnop dword ptr [rax+rax+00h]\nloc_12C0:\nmov edx, [rdi+rax*4]\nsub edx, 1\nmov [rdi+rax*4], edx\ncmp edx, 0FFFFFFFDh\njnz short loc_12DB\nmovsxd rdx, esi\nadd esi, 1\nmov [rsp+rdx*4+1DD8h+arg_1100], eax\nloc_12DB:\nadd rax, rcx\ncmp eax, 0BB7h\njle short loc_12C0\njmp short loc_1290\nloc_12E7:\ncmp esi, 1\njle short loc_133F\nlea r9, [rsp+1DD8h+arg_1100]\nlea r8, [rsp+1DD8h+arg_1104]\nnop dword ptr [rax+00h]\nloc_1300:\ncmp esi, 1\njle short loc_1367\nlea edx, [rsi-2]\nmov rax, r9\nlea rdi, [r8+rdx*4]\nnop\nloc_1310:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd edx, xmm0\nmovd ecx, xmm1\ncmp ecx, edx\njge short loc_132E\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_132E:\nadd rax, 4\ncmp rax, rdi\njnz short loc_1310\nsub esi, 1\ncmp esi, 1\njnz short loc_1300\nloc_133F:\nlea eax, [rbx-1]\ncdqe\nmov eax, [rsp+rax*4+1DD8h+arg_1100]\nmov rdx, [rsp+1DD8h+arg_3FE8]\nsub rdx, fs:28h\njnz short loc_136C\nadd rsp, 5DD0h\npop rbx\nretn\nloc_1367:\nsub esi, 1\njmp short loc_1300\nloc_136C:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "// positive sp value has been detected, the output may be wrong!\n__int64 __fastcall sub_1230(int a1)\n{\n _DWORD *v2; // rax\n unsigned __int64 v3; // r8\n __int64 v4; // rcx\n int v5; // esi\n _DWORD *v6; // rdi\n unsigned __int64 v7; // rax\n int v8; // edx\n __int64 v9; // rdx\n __m128i *v10; // rax\n __m128i v11; // xmm0\n __int64 v13; // [rsp-DD0h] [rbp-5DD8h] BYREF\n char v14; // [rsp+0h] [rbp-5008h] BYREF\n __int64 v15; // [rsp+1000h] [rbp-4008h] BYREF\n _QWORD v16[1503]; // [rsp+2110h] [rbp-2EF8h] BYREF\n\n while ( &v14 != (char *)(&v15 - 2560) )\n ;\n v16[1501] = __readfsqword(0x28u);\n v2 = memset(&v13, 0, 0x2EE0uLL);\n v3 = 4LL;\n v4 = 2LL;\n v5 = 0;\n v6 = v2;\n do\n {\n if ( !v6[v4] )\n {\n v6[v4] = 1;\n if ( v3 <= 0xBB7 )\n {\n v7 = v3;\n do\n {\n v8 = v6[v7] - 1;\n v6[v7] = v8;\n if ( v8 == -3 )\n {\n v9 = v5++;\n *((_DWORD *)v16 + v9) = v7;\n }\n v7 += v4;\n }\n while ( (int)v7 <= 2999 );\n }\n }\n ++v4;\n v3 += 2LL;\n }\n while ( v4 != 3000 );\n if ( v5 > 1 )\n {\n do\n {\n while ( v5 <= 1 )\n --v5;\n v10 = (__m128i *)v16;\n do\n {\n v11 = _mm_loadl_epi64(v10);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v11, 229)) < _mm_cvtsi128_si32(v11) )\n v10->m128i_i64[0] = _mm_shuffle_epi32(v11, 225).m128i_u64[0];\n v10 = (__m128i *)((char *)v10 + 4);\n }\n while ( v10 != (__m128i *)((char *)v16 + 4 * (unsigned int)(v5 - 2) + 4) );\n --v5;\n }\n while ( v5 != 1 );\n }\n return *((unsigned int *)v16 + a1 - 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1230(int a1) {\n uint32_t *v2;\n unsigned long long v3;\n long long v4;\n int v5;\n uint32_t *v6;\n unsigned long long v7;\n int v8;\n long long v9;\n __m128i *v10;\n __m128i v11;\n long long v13;\n char v14;\n long long v15;\n uint64_t v16[1503];\n while (&v14 != (char *)(&v15 - 2560))\n ;\n v16[1501] = __readfsqword(40u);\n v2 = memset(&v13, 0, 12000uLL);\n v3 = 4LL;\n v4 = 2LL;\n v5 = 0;\n v6 = v2;\n do {\n if (!v6[v4]) {\n v6[v4] = 1;\n if (v3 <= 2999) {\n v7 = v3;\n do {\n v8 = v6[v7] - 1;\n v6[v7] = v8;\n if (v8 == -3) {\n v9 = v5++;\n *((uint32_t *)v16 + v9) = v7;\n }\n v7 += v4;\n } while ((int)v7 <= 2999);\n }\n }\n ++v4;\n v3 += 2LL;\n } while (v4 != 3000);\n if (v5 > 1) {\n do {\n while (v5 <= 1) --v5;\n v10 = (__m128i *)v16;\n do {\n v11 = _mm_loadl_epi64(v10);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v11, 229)) <\n _mm_cvtsi128_si32(v11))\n v10->m128i_i64[0] = _mm_shuffle_epi32(v11, 225).m128i_u64[0];\n v10 = (__m128i *)((char *)v10 + 4);\n } while (v10 !=\n (__m128i *)((char *)v16 + 4 * (unsigned int)(v5 - 2) + 4));\n --v5;\n } while (v5 != 1);\n }\n return *((unsigned int *)v16 + a1 - 1);\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n uint32_t *v2;\n unsigned long long v3;\n long long v4;\n int v5;\n uint32_t *v6;\n unsigned long long v7;\n int v8;\n long long v9;\n __m128i *v10;\n __m128i v11;\n long long v13;\n char v14;\n long long v15;\n uint64_t v16[1503];\n while (&v14 != (char *)(&v15 - 2560))\n ;\n v16[1501] = __readfsqword(40u);\n v2 = memset(&v13, 0, 12000uLL);\n v3 = 4LL;\n v4 = 2LL;\n v5 = 0;\n v6 = v2;\n do {\n if (!v6[v4]) {\n v6[v4] = 1;\n if (v3 <= 2999) {\n v7 = v3;\n do {\n v8 = v6[v7] - 1;\n v6[v7] = v8;\n if (v8 == -3) {\n v9 = v5++;\n *((uint32_t *)v16 + v9) = v7;\n }\n v7 += v4;\n } while ((int)v7 <= 2999);\n }\n }\n ++v4;\n v3 += 2LL;\n } while (v4 != 3000);\n if (v5 > 1) {\n do {\n while (v5 <= 1) --v5;\n v10 = (__m128i *)v16;\n do {\n v11 = _mm_loadl_epi64(v10);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v11, 229)) <\n _mm_cvtsi128_si32(v11))\n v10->m128i_i64[0] = _mm_shuffle_epi32(v11, 225).m128i_u64[0];\n v10 = (__m128i *)((char *)v10 + 4);\n } while (v10 !=\n (__m128i *)((char *)v16 + 4 * (unsigned int)(v5 - 2) + 4));\n --v5;\n } while (v5 != 1);\n }\n return *((unsigned int *)v16 + a1 - 1);\n}" + }, + { + "index": 123, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int limit) {\n if (limit < 1) {\n return -1;\n }\n int amicables_sum = 0;\n for (int num = 2; num <= limit; num++) {\n int sum_fact = 0;\n for (int fact = 1; fact < num; fact++) {\n if (num % fact == 0) {\n sum_fact += fact;\n }\n }\n int sum_fact2 = 0;\n for (int fact = 1; fact < sum_fact; fact++) {\n if (sum_fact % fact == 0) {\n sum_fact2 += fact;\n }\n }\n if (num == sum_fact2 && num != sum_fact) {\n amicables_sum += num;\n }\n }\n return amicables_sum;\n}", + "test": "int main() {\n\n assert(func0(999) == 504);\n\n assert(func0(9999) == 31626);\n\n assert(func0(99) == 0);\n\n \n\n // Print \"Tests Passed\" upon successful completion.\n\n printf(\"Tests Passed\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x24(%rbp)\ncmpl $0x0,-0x24(%rbp)\njg 1184 \nmov $0xffffffff,%eax\njmpq 1217 \nmovl $0x0,-0x18(%rbp)\nmovl $0x2,-0x14(%rbp)\njmp 120c \nmovl $0x0,-0x10(%rbp)\nmovl $0x1,-0xc(%rbp)\njmp 11bb \nmov -0x14(%rbp),%eax\ncltd\nidivl -0xc(%rbp)\nmov %edx,%eax\ntest %eax,%eax\njne 11b7 \nmov -0xc(%rbp),%eax\nadd %eax,-0x10(%rbp)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x14(%rbp),%eax\njl 11a4 \nmovl $0x0,-0x8(%rbp)\nmovl $0x1,-0x4(%rbp)\njmp 11ea \nmov -0x10(%rbp),%eax\ncltd\nidivl -0x4(%rbp)\nmov %edx,%eax\ntest %eax,%eax\njne 11e6 \nmov -0x4(%rbp),%eax\nadd %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x10(%rbp),%eax\njl 11d3 \nmov -0x14(%rbp),%eax\ncmp -0x8(%rbp),%eax\njne 1208 \nmov -0x14(%rbp),%eax\ncmp -0x10(%rbp),%eax\nje 1208 \nmov -0x14(%rbp),%eax\nadd %eax,-0x18(%rbp)\naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\ncmp -0x24(%rbp),%eax\njle 1194 \nmov -0x18(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_24], edi\ncmp [rbp+var_24], 0\njg short loc_1184\nmov eax, 0FFFFFFFFh\njmp loc_1217\nloc_1184:\nmov [rbp+var_18], 0\nmov [rbp+var_14], 2\njmp short loc_120C\nloc_1194:\nmov [rbp+var_10], 0\nmov [rbp+var_C], 1\njmp short loc_11BB\nloc_11A4:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_C]\nmov eax, edx\ntest eax, eax\njnz short loc_11B7\nmov eax, [rbp+var_C]\nadd [rbp+var_10], eax\nloc_11B7:\nadd [rbp+var_C], 1\nloc_11BB:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_14]\njl short loc_11A4\nmov [rbp+var_8], 0\nmov [rbp+var_4], 1\njmp short loc_11EA\nloc_11D3:\nmov eax, [rbp+var_10]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njnz short loc_11E6\nmov eax, [rbp+var_4]\nadd [rbp+var_8], eax\nloc_11E6:\nadd [rbp+var_4], 1\nloc_11EA:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_10]\njl short loc_11D3\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_8]\njnz short loc_1208\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_10]\njz short loc_1208\nmov eax, [rbp+var_14]\nadd [rbp+var_18], eax\nloc_1208:\nadd [rbp+var_14], 1\nloc_120C:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_24]\njle short loc_1194\nmov eax, [rbp+var_18]\nloc_1217:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v2; // [rsp+Ch] [rbp-18h]\n int i; // [rsp+10h] [rbp-14h]\n int v4; // [rsp+14h] [rbp-10h]\n int j; // [rsp+18h] [rbp-Ch]\n int v6; // [rsp+1Ch] [rbp-8h]\n int k; // [rsp+20h] [rbp-4h]\n\n if ( a1 <= 0 )\n return 0xFFFFFFFFLL;\n v2 = 0;\n for ( i = 2; i <= a1; ++i )\n {\n v4 = 0;\n for ( j = 1; j < i; ++j )\n {\n if ( !(i % j) )\n v4 += j;\n }\n v6 = 0;\n for ( k = 1; k < v4; ++k )\n {\n if ( !(v4 % k) )\n v6 += k;\n }\n if ( i == v6 && i != v4 )\n v2 += i;\n }\n return v2;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_24], edi\ncmp [rbp+var_24], 0\njg short loc_1184\nmov eax, 0FFFFFFFFh\njmp loc_1217\nloc_1184:\nmov [rbp+var_18], 0\nmov [rbp+var_14], 2\njmp short loc_120C\nloc_1194:\nmov [rbp+var_10], 0\nmov [rbp+var_C], 1\njmp short loc_11BB\nloc_11A4:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_C]\nmov eax, edx\ntest eax, eax\njnz short loc_11B7\nmov eax, [rbp+var_C]\nadd [rbp+var_10], eax\nloc_11B7:\nadd [rbp+var_C], 1\nloc_11BB:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_14]\njl short loc_11A4\nmov [rbp+var_8], 0\nmov [rbp+var_4], 1\njmp short loc_11EA\nloc_11D3:\nmov eax, [rbp+var_10]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njnz short loc_11E6\nmov eax, [rbp+var_4]\nadd [rbp+var_8], eax\nloc_11E6:\nadd [rbp+var_4], 1\nloc_11EA:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_10]\njl short loc_11D3\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_8]\njnz short loc_1208\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_10]\njz short loc_1208\nmov eax, [rbp+var_14]\nadd [rbp+var_18], eax\nloc_1208:\nadd [rbp+var_14], 1\nloc_120C:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_24]\njle short loc_1194\nmov eax, [rbp+var_18]\nloc_1217:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n unsigned int v2; // [rsp+Ch] [rbp-18h]\n int i; // [rsp+10h] [rbp-14h]\n int v4; // [rsp+14h] [rbp-10h]\n int j; // [rsp+18h] [rbp-Ch]\n int v6; // [rsp+1Ch] [rbp-8h]\n int k; // [rsp+20h] [rbp-4h]\n\n if ( a1 <= 0 )\n return 0xFFFFFFFFLL;\n v2 = 0;\n for ( i = 2; i <= a1; ++i )\n {\n v4 = 0;\n for ( j = 1; j < i; ++j )\n {\n if ( !(i % j) )\n v4 += j;\n }\n v6 = 0;\n for ( k = 1; k < v4; ++k )\n {\n if ( !(v4 % k) )\n v6 += k;\n }\n if ( i == v6 && i != v4 )\n v2 += i;\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n unsigned int v2;\n int i;\n int v4;\n int j;\n int v6;\n int k;\n if (a1 <= 0) return 4294967295LL;\n v2 = 0;\n for (i = 2; i <= a1; ++i) {\n v4 = 0;\n for (j = 1; j < i; ++j) {\n if (!(i % j)) v4 += j;\n }\n v6 = 0;\n for (k = 1; k < v4; ++k) {\n if (!(v4 % k)) v6 += k;\n }\n if (i == v6 && i != v4) v2 += i;\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v2;\n int i;\n int v4;\n int j;\n int v6;\n int k;\n if (a1 <= 0) return 4294967295LL;\n v2 = 0;\n for (i = 2; i <= a1; ++i) {\n v4 = 0;\n for (j = 1; j < i; ++j) {\n if (!(i % j)) v4 += j;\n }\n v6 = 0;\n for (k = 1; k < v4; ++k) {\n if (!(v4 % k)) v6 += k;\n }\n if (i == v6 && i != v4) v2 += i;\n }\n return v2;\n}" + }, + { + "index": 123, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int limit) {\n if (limit < 1) {\n return -1;\n }\n int amicables_sum = 0;\n for (int num = 2; num <= limit; num++) {\n int sum_fact = 0;\n for (int fact = 1; fact < num; fact++) {\n if (num % fact == 0) {\n sum_fact += fact;\n }\n }\n int sum_fact2 = 0;\n for (int fact = 1; fact < sum_fact; fact++) {\n if (sum_fact % fact == 0) {\n sum_fact2 += fact;\n }\n }\n if (num == sum_fact2 && num != sum_fact) {\n amicables_sum += num;\n }\n }\n return amicables_sum;\n}", + "test": "int main() {\n\n assert(func0(999) == 504);\n\n assert(func0(9999) == 31626);\n\n assert(func0(99) == 0);\n\n \n\n // Print \"Tests Passed\" upon successful completion.\n\n printf(\"Tests Passed\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\njle 11fa \ncmp $0x1,%edi\njle 1202 \nlea 0x1(%rdi),%r11d\nmov $0x2,%edi\nmov $0x0,%r9d\nmov $0x0,%r10d\njmp 119d \nadd $0x1,%edi\ncmp %edi,%r11d\nje 1208 \nmov $0x1,%esi\nmov %r10d,%ecx\nmov %r10d,%r8d\ncmp $0x1,%edi\njle 11e4 \nmov %edi,%eax\ncltd\nidiv %esi\nlea (%rcx,%rsi,1),%eax\ntest %edx,%edx\ncmove %eax,%ecx\nadd $0x1,%esi\ncmp %edi,%esi\njne 11ad \ncmp $0x1,%ecx\njle 1195 \nmov $0x1,%esi\nmov %r10d,%r8d\nmov %ecx,%eax\ncltd\nidiv %esi\nlea (%r8,%rsi,1),%eax\ntest %edx,%edx\ncmove %eax,%r8d\nadd $0x1,%esi\ncmp %esi,%ecx\njne 11ce \ncmp %r8d,%edi\njne 1195 \ncmp %edi,%ecx\nsetne %dl\nlea (%r9,%rdi,1),%eax\ntest %dl,%dl\ncmovne %eax,%r9d\njmp 1195 \nmov $0xffffffff,%r9d\njmp 1208 \nmov $0x0,%r9d\nmov %r9d,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njle loc_11F7\ncmp edi, 1\njle loc_11FF\nlea r11d, [rdi+1]\nmov edi, 2\nmov r9d, 0\nmov r10d, 0\njmp short loc_119D\nloc_1195:\nadd edi, 1\ncmp r11d, edi\njz short loc_1205\nloc_119D:\nmov esi, 1\nmov ecx, r10d\ncmp edi, 1\njle short loc_1209\nloc_11AA:\nmov eax, edi\ncdq\nidiv esi\nlea eax, [rcx+rsi]\ntest edx, edx\ncmovz ecx, eax\nadd esi, 1\ncmp esi, edi\njnz short loc_11AA\ncmp ecx, 1\njle short loc_1195\nmov esi, 1\nmov r8d, r10d\nloc_11CB:\nmov eax, ecx\ncdq\nidiv esi\nlea eax, [r8+rsi]\ntest edx, edx\ncmovz r8d, eax\nadd esi, 1\ncmp ecx, esi\njnz short loc_11CB\ncmp r8d, edi\njnz short loc_1195\ncmp esi, edi\nsetnz dl\nlea eax, [r9+rdi]\ntest dl, dl\ncmovnz r9d, eax\njmp short loc_1195\nloc_11F7:\nmov r9d, 0FFFFFFFFh\njmp short loc_1205\nloc_11FF:\nmov r9d, 0\nloc_1205:\nmov eax, r9d\nretn\nloc_1209:\nadd edi, 1\njmp short loc_119D", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // r11d\n int v2; // edi\n unsigned int v3; // r9d\n int v4; // esi\n int v5; // ecx\n int v6; // esi\n int v7; // r8d\n\n if ( a1 <= 0 )\n {\n return (unsigned int)-1;\n }\n else if ( a1 <= 1 )\n {\n return 0;\n }\n else\n {\n v1 = a1 + 1;\n v2 = 2;\n v3 = 0;\n do\n {\n while ( 1 )\n {\n v4 = 1;\n v5 = 0;\n if ( v2 > 1 )\n break;\n ++v2;\n }\n do\n {\n if ( !(v2 % v4) )\n v5 += v4;\n ++v4;\n }\n while ( v4 != v2 );\n if ( v5 > 1 )\n {\n v6 = 1;\n v7 = 0;\n do\n {\n if ( !(v5 % v6) )\n v7 += v6;\n ++v6;\n }\n while ( v5 != v6 );\n if ( v7 == v2 && v6 != v2 )\n v3 += v2;\n }\n ++v2;\n }\n while ( v1 != v2 );\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest edi, edi\njle loc_11F7\ncmp edi, 1\njle loc_11FF\nlea r11d, [rdi+1]\nmov edi, 2\nmov r9d, 0\nmov r10d, 0\njmp short loc_119D\nloc_1195:\nadd edi, 1\ncmp r11d, edi\njz short loc_1205\nloc_119D:\nmov esi, 1\nmov ecx, r10d\ncmp edi, 1\njle short loc_1209\nloc_11AA:\nmov eax, edi\ncdq\nidiv esi\nlea eax, [rcx+rsi]\ntest edx, edx\ncmovz ecx, eax\nadd esi, 1\ncmp esi, edi\njnz short loc_11AA\ncmp ecx, 1\njle short loc_1195\nmov esi, 1\nmov r8d, r10d\nloc_11CB:\nmov eax, ecx\ncdq\nidiv esi\nlea eax, [r8+rsi]\ntest edx, edx\ncmovz r8d, eax\nadd esi, 1\ncmp ecx, esi\njnz short loc_11CB\ncmp r8d, edi\njnz short loc_1195\ncmp esi, edi\nsetnz dl\nlea eax, [r9+rdi]\ntest dl, dl\ncmovnz r9d, eax\njmp short loc_1195\nloc_11F7:\nmov r9d, 0FFFFFFFFh\njmp short loc_1205\nloc_11FF:\nmov r9d, 0\nloc_1205:\nmov eax, r9d\nretn\nloc_1209:\nadd edi, 1\njmp short loc_119D", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n int v1; // r11d\n int v2; // edi\n unsigned int v3; // r9d\n int v4; // esi\n int v5; // ecx\n int v6; // esi\n int v7; // r8d\n\n if ( a1 <= 0 )\n {\n return (unsigned int)-1;\n }\n else if ( a1 <= 1 )\n {\n return 0;\n }\n else\n {\n v1 = a1 + 1;\n v2 = 2;\n v3 = 0;\n do\n {\n while ( 1 )\n {\n v4 = 1;\n v5 = 0;\n if ( v2 > 1 )\n break;\n ++v2;\n }\n do\n {\n if ( !(v2 % v4) )\n v5 += v4;\n ++v4;\n }\n while ( v4 != v2 );\n if ( v5 > 1 )\n {\n v6 = 1;\n v7 = 0;\n do\n {\n if ( !(v5 % v6) )\n v7 += v6;\n ++v6;\n }\n while ( v5 != v6 );\n if ( v7 == v2 && v6 != v2 )\n v3 += v2;\n }\n ++v2;\n }\n while ( v1 != v2 );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n int v1;\n int v2;\n unsigned int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n if (a1 <= 0) {\n return (unsigned int)-1;\n } else if (a1 <= 1) {\n return 0;\n } else {\n v1 = a1 + 1;\n v2 = 2;\n v3 = 0;\n do {\n while (1) {\n v4 = 1;\n v5 = 0;\n if (v2 > 1) break;\n ++v2;\n }\n do {\n if (!(v2 % v4)) v5 += v4;\n ++v4;\n } while (v4 != v2);\n if (v5 > 1) {\n v6 = 1;\n v7 = 0;\n do {\n if (!(v5 % v6)) v7 += v6;\n ++v6;\n } while (v5 != v6);\n if (v7 == v2 && v6 != v2) v3 += v2;\n }\n ++v2;\n } while (v1 != v2);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v2;\n unsigned int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n if (a1 <= 0) {\n return (unsigned int)-1;\n } else if (a1 <= 1) {\n return 0;\n } else {\n v1 = a1 + 1;\n v2 = 2;\n v3 = 0;\n do {\n while (1) {\n v4 = 1;\n v5 = 0;\n if (v2 > 1) break;\n ++v2;\n }\n do {\n if (!(v2 % v4)) v5 += v4;\n ++v4;\n } while (v4 != v2);\n if (v5 > 1) {\n v6 = 1;\n v7 = 0;\n do {\n if (!(v5 % v6)) v7 += v6;\n ++v6;\n } while (v5 != v6);\n if (v7 == v2 && v6 != v2) v3 += v2;\n }\n ++v2;\n } while (v1 != v2);\n }\n return v3;\n}" + }, + { + "index": 123, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int limit) {\n if (limit < 1) {\n return -1;\n }\n int amicables_sum = 0;\n for (int num = 2; num <= limit; num++) {\n int sum_fact = 0;\n for (int fact = 1; fact < num; fact++) {\n if (num % fact == 0) {\n sum_fact += fact;\n }\n }\n int sum_fact2 = 0;\n for (int fact = 1; fact < sum_fact; fact++) {\n if (sum_fact % fact == 0) {\n sum_fact2 += fact;\n }\n }\n if (num == sum_fact2 && num != sum_fact) {\n amicables_sum += num;\n }\n }\n return amicables_sum;\n}", + "test": "int main() {\n\n assert(func0(999) == 504);\n\n assert(func0(9999) == 31626);\n\n assert(func0(99) == 0);\n\n \n\n // Print \"Tests Passed\" upon successful completion.\n\n printf(\"Tests Passed\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\njle 12bd \njmpq 1220 \nmov $0xffffffff,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0_part_0:\ncmp edi, 1\njle short loc_129E\nlea r10d, [rdi+1]\nxor r9d, r9d\nmov edi, 2\nnop dword ptr [rax+00000000h]\nloc_1238:\nxor ecx, ecx\nmov esi, 1\nnop\nloc_1240:\nmov eax, edi\ncdq\nidiv esi\nlea eax, [rcx+rsi]\ntest edx, edx\ncmovz ecx, eax\nadd esi, 1\ncmp edi, esi\njnz short loc_1240\ncmp ecx, 1\njle short loc_1292\nxor r8d, r8d\nmov esi, 1\nnop dword ptr [rax+00000000h]\nloc_1268:\nmov eax, ecx\ncdq\nidiv esi\nlea eax, [r8+rsi]\ntest edx, edx\ncmovz r8d, eax\nadd esi, 1\ncmp esi, ecx\njnz short loc_1268\ncmp r8d, edi\njnz short loc_1292\ncmp edi, esi\nlea eax, [r9+rdi]\nsetnz dl\ntest dl, dl\ncmovnz r9d, eax\nloc_1292:\nadd edi, 1\ncmp edi, r10d\njnz short loc_1238\nmov eax, r9d\nretn\nloc_129E:\nxor r9d, r9d\nmov eax, r9d\nretn", + "ida_pseudo": "__int64 __fastcall func0_part_0(int a1)\n{\n int v1; // r10d\n unsigned int v2; // r9d\n int v3; // edi\n int v4; // ecx\n int v5; // esi\n int v6; // r8d\n int i; // esi\n\n if ( a1 <= 1 )\n return 0LL;\n v1 = a1 + 1;\n v2 = 0;\n v3 = 2;\n do\n {\n v4 = 0;\n v5 = 1;\n do\n {\n if ( !(v3 % v5) )\n v4 += v5;\n ++v5;\n }\n while ( v3 != v5 );\n if ( v4 > 1 )\n {\n v6 = 0;\n for ( i = 1; i != v4; ++i )\n {\n if ( !(v4 % i) )\n v6 += i;\n }\n if ( v6 == v3 && v3 != i )\n v2 += v3;\n }\n ++v3;\n }\n while ( v3 != v1 );\n return v2;\n}", + "ida_strip_asm": "sub_1220:\ncmp edi, 1\njle short loc_129E\nlea r10d, [rdi+1]\nxor r9d, r9d\nmov edi, 2\nnop dword ptr [rax+00000000h]\nloc_1238:\nxor ecx, ecx\nmov esi, 1\nnop\nloc_1240:\nmov eax, edi\ncdq\nidiv esi\nlea eax, [rcx+rsi]\ntest edx, edx\ncmovz ecx, eax\nadd esi, 1\ncmp edi, esi\njnz short loc_1240\ncmp ecx, 1\njle short loc_1292\nxor r8d, r8d\nmov esi, 1\nnop dword ptr [rax+00000000h]\nloc_1268:\nmov eax, ecx\ncdq\nidiv esi\nlea eax, [r8+rsi]\ntest edx, edx\ncmovz r8d, eax\nadd esi, 1\ncmp esi, ecx\njnz short loc_1268\ncmp r8d, edi\njnz short loc_1292\ncmp edi, esi\nlea eax, [r9+rdi]\nsetnz dl\ntest dl, dl\ncmovnz r9d, eax\nloc_1292:\nadd edi, 1\ncmp edi, r10d\njnz short loc_1238\nmov eax, r9d\nretn\nloc_129E:\nxor r9d, r9d\nmov eax, r9d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1220(int a1)\n{\n int v1; // r10d\n unsigned int v2; // r9d\n int v3; // edi\n int v4; // ecx\n int v5; // esi\n int v6; // r8d\n int i; // esi\n\n if ( a1 <= 1 )\n return 0LL;\n v1 = a1 + 1;\n v2 = 0;\n v3 = 2;\n do\n {\n v4 = 0;\n v5 = 1;\n do\n {\n if ( !(v3 % v5) )\n v4 += v5;\n ++v5;\n }\n while ( v3 != v5 );\n if ( v4 > 1 )\n {\n v6 = 0;\n for ( i = 1; i != v4; ++i )\n {\n if ( !(v4 % i) )\n v6 += i;\n }\n if ( v6 == v3 && v3 != i )\n v2 += v3;\n }\n ++v3;\n }\n while ( v3 != v1 );\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1220(int a1) {\n int v1;\n unsigned int v2;\n int v3;\n int v4;\n int v5;\n int v6;\n int i;\n if (a1 <= 1) return 0LL;\n v1 = a1 + 1;\n v2 = 0;\n v3 = 2;\n do {\n v4 = 0;\n v5 = 1;\n do {\n if (!(v3 % v5)) v4 += v5;\n ++v5;\n } while (v3 != v5);\n if (v4 > 1) {\n v6 = 0;\n for (i = 1; i != v4; ++i) {\n if (!(v4 % i)) v6 += i;\n }\n if (v6 == v3 && v3 != i) v2 += v3;\n }\n ++v3;\n } while (v3 != v1);\n return v2;\n}", + "ida_pseudo_norm": "long long func0_part_0(int a1) {\n int v1;\n unsigned int v2;\n int v3;\n int v4;\n int v5;\n int v6;\n int i;\n if (a1 <= 1) return 0LL;\n v1 = a1 + 1;\n v2 = 0;\n v3 = 2;\n do {\n v4 = 0;\n v5 = 1;\n do {\n if (!(v3 % v5)) v4 += v5;\n ++v5;\n } while (v3 != v5);\n if (v4 > 1) {\n v6 = 0;\n for (i = 1; i != v4; ++i) {\n if (!(v4 % i)) v6 += i;\n }\n if (v6 == v3 && v3 != i) v2 += v3;\n }\n ++v3;\n } while (v3 != v1);\n return v2;\n}" + }, + { + "index": 123, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int limit) {\n if (limit < 1) {\n return -1;\n }\n int amicables_sum = 0;\n for (int num = 2; num <= limit; num++) {\n int sum_fact = 0;\n for (int fact = 1; fact < num; fact++) {\n if (num % fact == 0) {\n sum_fact += fact;\n }\n }\n int sum_fact2 = 0;\n for (int fact = 1; fact < sum_fact; fact++) {\n if (sum_fact % fact == 0) {\n sum_fact2 += fact;\n }\n }\n if (num == sum_fact2 && num != sum_fact) {\n amicables_sum += num;\n }\n }\n return amicables_sum;\n}", + "test": "int main() {\n\n assert(func0(999) == 504);\n\n assert(func0(9999) == 31626);\n\n assert(func0(99) == 0);\n\n \n\n // Print \"Tests Passed\" upon successful completion.\n\n printf(\"Tests Passed\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\njle 1345 \ncmp $0x1,%edi\nje 133e \nlea 0x1(%rdi),%r10d\nxor %r9d,%r9d\nmov $0x2,%edi\nnopl (%rax)\nxor %ecx,%ecx\nmov $0x1,%esi\nnopw 0x0(%rax,%rax,1)\nmov %edi,%eax\ncltd\nidiv %esi\nlea (%rcx,%rsi,1),%eax\ntest %edx,%edx\ncmove %eax,%ecx\nadd $0x1,%esi\ncmp %esi,%edi\njne 12e0 \ncmp $0x1,%ecx\njle 1332 \nxor %r8d,%r8d\nmov $0x1,%esi\nnopl 0x0(%rax)\nmov %ecx,%eax\ncltd\nidiv %esi\nlea (%r8,%rsi,1),%eax\ntest %edx,%edx\ncmove %eax,%r8d\nadd $0x1,%esi\ncmp %ecx,%esi\njne 1308 \ncmp %edi,%r8d\njne 1332 \ncmp %esi,%edi\nlea (%r9,%rdi,1),%eax\nsetne %dl\ntest %dl,%dl\ncmovne %eax,%r9d\nadd $0x1,%edi\ncmp %r10d,%edi\njne 12d0 \nmov %r9d,%eax\nretq\nxor %r9d,%r9d\nmov %r9d,%eax\nretq\nmov $0xffffffff,%r9d\njmp 133a \nnopl (%rax)\n", + "ida_asm": "func0_part_0:\ncmp edi, 1\njle short loc_129E\nlea r10d, [rdi+1]\nxor r9d, r9d\nmov edi, 2\nnop dword ptr [rax+00000000h]\nloc_1238:\nxor ecx, ecx\nmov esi, 1\nnop\nloc_1240:\nmov eax, edi\ncdq\nidiv esi\nlea eax, [rcx+rsi]\ntest edx, edx\ncmovz ecx, eax\nadd esi, 1\ncmp edi, esi\njnz short loc_1240\ncmp ecx, 1\njle short loc_1292\nxor r8d, r8d\nmov esi, 1\nnop dword ptr [rax+00000000h]\nloc_1268:\nmov eax, ecx\ncdq\nidiv esi\nlea eax, [r8+rsi]\ntest edx, edx\ncmovz r8d, eax\nadd esi, 1\ncmp esi, ecx\njnz short loc_1268\ncmp r8d, edi\njnz short loc_1292\ncmp edi, esi\nlea eax, [r9+rdi]\nsetnz dl\ntest dl, dl\ncmovnz r9d, eax\nloc_1292:\nadd edi, 1\ncmp edi, r10d\njnz short loc_1238\nmov eax, r9d\nretn\nloc_129E:\nxor r9d, r9d\nmov eax, r9d\nretn", + "ida_pseudo": "__int64 __fastcall func0_part_0(int a1)\n{\n int v1; // r10d\n unsigned int v2; // r9d\n int v3; // edi\n int v4; // ecx\n int v5; // esi\n int v6; // r8d\n int i; // esi\n\n if ( a1 <= 1 )\n return 0LL;\n v1 = a1 + 1;\n v2 = 0;\n v3 = 2;\n do\n {\n v4 = 0;\n v5 = 1;\n do\n {\n if ( !(v3 % v5) )\n v4 += v5;\n ++v5;\n }\n while ( v3 != v5 );\n if ( v4 > 1 )\n {\n v6 = 0;\n for ( i = 1; i != v4; ++i )\n {\n if ( !(v4 % i) )\n v6 += i;\n }\n if ( v6 == v3 && v3 != i )\n v2 += v3;\n }\n ++v3;\n }\n while ( v3 != v1 );\n return v2;\n}", + "ida_strip_asm": "sub_1220:\ncmp edi, 1\njle short loc_129E\nlea r10d, [rdi+1]\nxor r9d, r9d\nmov edi, 2\nnop dword ptr [rax+00000000h]\nloc_1238:\nxor ecx, ecx\nmov esi, 1\nnop\nloc_1240:\nmov eax, edi\ncdq\nidiv esi\nlea eax, [rcx+rsi]\ntest edx, edx\ncmovz ecx, eax\nadd esi, 1\ncmp edi, esi\njnz short loc_1240\ncmp ecx, 1\njle short loc_1292\nxor r8d, r8d\nmov esi, 1\nnop dword ptr [rax+00000000h]\nloc_1268:\nmov eax, ecx\ncdq\nidiv esi\nlea eax, [r8+rsi]\ntest edx, edx\ncmovz r8d, eax\nadd esi, 1\ncmp esi, ecx\njnz short loc_1268\ncmp r8d, edi\njnz short loc_1292\ncmp edi, esi\nlea eax, [r9+rdi]\nsetnz dl\ntest dl, dl\ncmovnz r9d, eax\nloc_1292:\nadd edi, 1\ncmp edi, r10d\njnz short loc_1238\nmov eax, r9d\nretn\nloc_129E:\nxor r9d, r9d\nmov eax, r9d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1220(int a1)\n{\n int v1; // r10d\n unsigned int v2; // r9d\n int v3; // edi\n int v4; // ecx\n int v5; // esi\n int v6; // r8d\n int i; // esi\n\n if ( a1 <= 1 )\n return 0LL;\n v1 = a1 + 1;\n v2 = 0;\n v3 = 2;\n do\n {\n v4 = 0;\n v5 = 1;\n do\n {\n if ( !(v3 % v5) )\n v4 += v5;\n ++v5;\n }\n while ( v3 != v5 );\n if ( v4 > 1 )\n {\n v6 = 0;\n for ( i = 1; i != v4; ++i )\n {\n if ( !(v4 % i) )\n v6 += i;\n }\n if ( v6 == v3 && v3 != i )\n v2 += v3;\n }\n ++v3;\n }\n while ( v3 != v1 );\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1220(int a1) {\n int v1;\n unsigned int v2;\n int v3;\n int v4;\n int v5;\n int v6;\n int i;\n if (a1 <= 1) return 0LL;\n v1 = a1 + 1;\n v2 = 0;\n v3 = 2;\n do {\n v4 = 0;\n v5 = 1;\n do {\n if (!(v3 % v5)) v4 += v5;\n ++v5;\n } while (v3 != v5);\n if (v4 > 1) {\n v6 = 0;\n for (i = 1; i != v4; ++i) {\n if (!(v4 % i)) v6 += i;\n }\n if (v6 == v3 && v3 != i) v2 += v3;\n }\n ++v3;\n } while (v3 != v1);\n return v2;\n}", + "ida_pseudo_norm": "long long func0_part_0(int a1) {\n int v1;\n unsigned int v2;\n int v3;\n int v4;\n int v5;\n int v6;\n int i;\n if (a1 <= 1) return 0LL;\n v1 = a1 + 1;\n v2 = 0;\n v3 = 2;\n do {\n v4 = 0;\n v5 = 1;\n do {\n if (!(v3 % v5)) v4 += v5;\n ++v5;\n } while (v3 != v5);\n if (v4 > 1) {\n v6 = 0;\n for (i = 1; i != v4; ++i) {\n if (!(v4 % i)) v6 += i;\n }\n if (v6 == v3 && v3 != i) v2 += v3;\n }\n ++v3;\n } while (v3 != v1);\n return v2;\n}" + }, + { + "index": 124, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "double func0(double a, double b) {\n double complex cn = a + b * I;\n double angle = carg(cn);\n return angle;\n}", + "test": "int main() {\n\n assert(fabs(func0(0, 1) - 1.5707963267948966) < 1e-9);\n\n assert(fabs(func0(2, 1) - 0.4636476090008061) < 1e-9);\n\n assert(fabs(func0(0, 2) - 1.5707963267948966) < 1e-9);\n\n \n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmovsd %xmm0,-0x28(%rbp)\nmovsd %xmm1,-0x30(%rbp)\nmovsd -0x30(%rbp),%xmm0\npxor %xmm1,%xmm1\nmulsd %xmm0,%xmm1\naddsd -0x28(%rbp),%xmm1\nmovsd %xmm1,-0x10(%rbp)\nmovsd %xmm0,-0x8(%rbp)\nmovsd -0x10(%rbp),%xmm0\nmov -0x8(%rbp),%rax\nmovapd %xmm0,%xmm1\nmovq %rax,%xmm0\ncallq 1070 \nmovq %xmm0,%rax\nmov %rax,-0x18(%rbp)\nmovsd -0x18(%rbp),%xmm0\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmovsd [rbp+var_38], xmm0\nmovsd [rbp+var_40], xmm1\nmovsd xmm0, [rbp+var_40]\nmovsd [rbp+y], xmm0\nmovsd xmm1, [rbp+y]\npxor xmm0, xmm0\nmulsd xmm0, xmm1\nmovsd xmm1, [rbp+var_38]\naddsd xmm0, xmm1\nmovsd [rbp+x], xmm0\nmovsd xmm0, [rbp+y]\nmovsd xmm1, [rbp+x]\nmovsd [rbp+var_10], xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+x]\nmov rax, [rbp+y]\nmovapd xmm1, xmm0; x\nmovq xmm0, rax; y\ncall _atan2\nmovq rax, xmm0\nmov [rbp+var_18], rax\nmovsd xmm0, [rbp+var_18]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(double a1, double a2)\n{\n return atan2(a2, 0.0 * a2 + a1);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmovsd [rbp+var_38], xmm0\nmovsd [rbp+var_40], xmm1\nmovsd xmm0, [rbp+var_40]\nmovsd [rbp+y], xmm0\nmovsd xmm1, [rbp+y]\npxor xmm0, xmm0\nmulsd xmm0, xmm1\nmovsd xmm1, [rbp+var_38]\naddsd xmm0, xmm1\nmovsd [rbp+x], xmm0\nmovsd xmm0, [rbp+y]\nmovsd xmm1, [rbp+x]\nmovsd [rbp+var_10], xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+x]\nmov rax, [rbp+y]\nmovapd xmm1, xmm0; x\nmovq xmm0, rax; y\ncall _atan2\nmovq rax, xmm0\nmov [rbp+var_18], rax\nmovsd xmm0, [rbp+var_18]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(double a1, double a2)\n{\n return atan2(a2, 0.0 * a2 + a1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(double a1, double a2) { return atan2(a2, 0.0 * a2 + a1); }", + "ida_pseudo_norm": "long long func0(double a1, double a2) { return atan2(a2, 0.0 * a2 + a1); }" + }, + { + "index": 124, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "double func0(double a, double b) {\n double complex cn = a + b * I;\n double angle = carg(cn);\n return angle;\n}", + "test": "int main() {\n\n assert(fabs(func0(0, 1) - 1.5707963267948966) < 1e-9);\n\n assert(fabs(func0(2, 1) - 0.4636476090008061) < 1e-9);\n\n assert(fabs(func0(0, 2) - 1.5707963267948966) < 1e-9);\n\n \n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x8,%rsp\nmovapd %xmm0,%xmm2\nmovapd %xmm1,%xmm0\nmulsd 0xea7(%rip),%xmm1\naddsd %xmm2,%xmm1\ncallq 1050 \nadd $0x8,%rsp\nretq\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\nmovapd xmm2, xmm0\nmovapd xmm0, xmm1; y\npxor xmm1, xmm1\nmulsd xmm1, xmm0\naddsd xmm1, xmm2; x\ncall _atan2\nadd rsp, 8\nretn", + "ida_pseudo": "double __fastcall func0(double a1, double a2)\n{\n return atan2(a2, 0.0 * a2 + a1);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nsub rsp, 8\nmovapd xmm2, xmm0\nmovapd xmm0, xmm1; y\npxor xmm1, xmm1\nmulsd xmm1, xmm0\naddsd xmm1, xmm2; x\ncall _atan2\nadd rsp, 8\nretn", + "ida_strip_pseudo": "double __fastcall sub_1149(double a1, double a2)\n{\n return atan2(a2, 0.0 * a2 + a1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1149(double a1, double a2) { return atan2(a2, 0.0 * a2 + a1); }", + "ida_pseudo_norm": "double func0(double a1, double a2) { return atan2(a2, 0.0 * a2 + a1); }" + }, + { + "index": 125, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(const char *string, int n) {\n int current_sum = 0;\n int max_sum = 0;\n for (int i = 0; i < n; i++) {\n current_sum += (string[i] == '0' ? 1 : -1);\n if (current_sum < 0) {\n current_sum = 0;\n }\n if (current_sum > max_sum) {\n max_sum = current_sum;\n }\n }\n return max_sum ? max_sum : 0;\n}", + "test": "int main() {\n\n assert(func0(\"11000010001\", 11) == 6);\n\n assert(func0(\"10111\", 5) == 1);\n\n assert(func0(\"11011101100101\", 14) == 2);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11b1 \nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x30,%al\njne 118a \nmov $0x1,%eax\njmp 118f \nmov $0xffffffff,%eax\nadd %eax,-0xc(%rbp)\ncmpl $0x0,-0xc(%rbp)\njns 119f \nmovl $0x0,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x8(%rbp),%eax\njle 11ad \nmov -0xc(%rbp),%eax\nmov %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 116f \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11B1\nloc_116F:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 30h ; '0'\njnz short loc_118A\nmov eax, 1\njmp short loc_118F\nloc_118A:\nmov eax, 0FFFFFFFFh\nloc_118F:\nadd [rbp+var_C], eax\ncmp [rbp+var_C], 0\njns short loc_119F\nmov [rbp+var_C], 0\nloc_119F:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_8]\njle short loc_11AD\nmov eax, [rbp+var_C]\nmov [rbp+var_8], eax\nloc_11AD:\nadd [rbp+var_4], 1\nloc_11B1:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_116F\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int v2; // eax\n int v4; // [rsp+10h] [rbp-Ch]\n int v5; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v4 = 0;\n v5 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(_BYTE *)(i + a1) == 48 )\n v2 = 1;\n else\n v2 = -1;\n v4 += v2;\n if ( v4 < 0 )\n v4 = 0;\n if ( v4 > v5 )\n v5 = v4;\n }\n return (unsigned int)v5;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11B1\nloc_116F:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 30h ; '0'\njnz short loc_118A\nmov eax, 1\njmp short loc_118F\nloc_118A:\nmov eax, 0FFFFFFFFh\nloc_118F:\nadd [rbp+var_C], eax\ncmp [rbp+var_C], 0\njns short loc_119F\nmov [rbp+var_C], 0\nloc_119F:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_8]\njle short loc_11AD\nmov eax, [rbp+var_C]\nmov [rbp+var_8], eax\nloc_11AD:\nadd [rbp+var_4], 1\nloc_11B1:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_116F\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(__int64 a1, int a2)\n{\n int v2; // eax\n int v4; // [rsp+10h] [rbp-Ch]\n int v5; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v4 = 0;\n v5 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(_BYTE *)(i + a1) == 48 )\n v2 = 1;\n else\n v2 = -1;\n v4 += v2;\n if ( v4 < 0 )\n v4 = 0;\n if ( v4 > v5 )\n v5 = v4;\n }\n return (unsigned int)v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(long long a1, int a2) {\n int v2;\n int v4;\n int v5;\n int i;\n v4 = 0;\n v5 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(uint8_t *)(i + a1) == 48)\n v2 = 1;\n else\n v2 = -1;\n v4 += v2;\n if (v4 < 0) v4 = 0;\n if (v4 > v5) v5 = v4;\n }\n return (unsigned int)v5;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int v2;\n int v4;\n int v5;\n int i;\n v4 = 0;\n v5 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(uint8_t *)(i + a1) == 48)\n v2 = 1;\n else\n v2 = -1;\n v4 += v2;\n if (v4 < 0) v4 = 0;\n if (v4 > v5) v5 = v4;\n }\n return (unsigned int)v5;\n}" + }, + { + "index": 125, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(const char *string, int n) {\n int current_sum = 0;\n int max_sum = 0;\n for (int i = 0; i < n; i++) {\n current_sum += (string[i] == '0' ? 1 : -1);\n if (current_sum < 0) {\n current_sum = 0;\n }\n if (current_sum > max_sum) {\n max_sum = current_sum;\n }\n }\n return max_sum ? max_sum : 0;\n}", + "test": "int main() {\n\n assert(func0(\"11000010001\", 11) == 6);\n\n assert(func0(\"10111\", 5) == 1);\n\n assert(func0(\"11011101100101\", 14) == 2);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1190 \nmov %rdi,%rdx\nlea -0x1(%rsi),%eax\nlea 0x1(%rdi,%rax,1),%r8\nmov $0x0,%ecx\nmov $0x0,%eax\nmov $0x0,%edi\ncmpb $0x30,(%rdx)\nsete %sil\nmovzbl %sil,%esi\nlea -0x1(%rax,%rsi,2),%eax\ntest %eax,%eax\ncmovs %edi,%eax\ncmp %eax,%ecx\ncmovl %eax,%ecx\nadd $0x1,%rdx\ncmp %r8,%rdx\njne 116b \nmov %ecx,%eax\nretq\nmov $0x0,%ecx\njmp 118d \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_118E\nmov rdx, rdi\nmovsxd rsi, esi\nadd rdi, rsi\nmov ecx, 0\nmov eax, 0\nloc_1164:\ncmp byte ptr [rdx], 30h ; '0'\nsetz sil\nmovzx esi, sil\nlea eax, [rax+rsi*2-1]\ntest eax, eax\nmov esi, 0\ncmovs eax, esi\ncmp ecx, eax\ncmovl ecx, eax\nadd rdx, 1\ncmp rdx, rdi\njnz short loc_1164\nloc_118B:\nmov eax, ecx\nretn\nloc_118E:\nmov ecx, 0\njmp short loc_118B", + "ida_pseudo": "__int64 __fastcall func0(_BYTE *a1, int a2)\n{\n _BYTE *v2; // rdx\n _BYTE *v3; // rdi\n int v4; // ecx\n int v5; // eax\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n v5 = 0;\n do\n {\n v5 = v5 + 2 * (*v2 == 48) - 1;\n if ( v5 < 0 )\n v5 = 0;\n if ( v4 < v5 )\n v4 = v5;\n ++v2;\n }\n while ( v2 != v3 );\n }\n return (unsigned int)v4;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ntest esi, esi\njle short loc_118E\nmov rdx, rdi\nmovsxd rsi, esi\nadd rdi, rsi\nmov ecx, 0\nmov eax, 0\nloc_1164:\ncmp byte ptr [rdx], 30h ; '0'\nsetz sil\nmovzx esi, sil\nlea eax, [rax+rsi*2-1]\ntest eax, eax\nmov esi, 0\ncmovs eax, esi\ncmp ecx, eax\ncmovl ecx, eax\nadd rdx, 1\ncmp rdx, rdi\njnz short loc_1164\nloc_118B:\nmov eax, ecx\nretn\nloc_118E:\nmov ecx, 0\njmp short loc_118B", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(_BYTE *a1, int a2)\n{\n _BYTE *v2; // rdx\n _BYTE *v3; // rdi\n int v4; // ecx\n int v5; // eax\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n v5 = 0;\n do\n {\n v5 = v5 + 2 * (*v2 == 48) - 1;\n if ( v5 < 0 )\n v5 = 0;\n if ( v4 < v5 )\n v4 = v5;\n ++v2;\n }\n while ( v2 != v3 );\n }\n return (unsigned int)v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(uint8_t *a1, int a2) {\n uint8_t *v2;\n uint8_t *v3;\n int v4;\n int v5;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n v5 = 0;\n do {\n v5 = v5 + 2 * (*v2 == 48) - 1;\n if (v5 < 0) v5 = 0;\n if (v4 < v5) v4 = v5;\n ++v2;\n } while (v2 != v3);\n }\n return (unsigned int)v4;\n}", + "ida_pseudo_norm": "long long func0(uint8_t *a1, int a2) {\n uint8_t *v2;\n uint8_t *v3;\n int v4;\n int v5;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n v5 = 0;\n do {\n v5 = v5 + 2 * (*v2 == 48) - 1;\n if (v5 < 0) v5 = 0;\n if (v4 < v5) v4 = v5;\n ++v2;\n } while (v2 != v3);\n }\n return (unsigned int)v4;\n}" + }, + { + "index": 125, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(const char *string, int n) {\n int current_sum = 0;\n int max_sum = 0;\n for (int i = 0; i < n; i++) {\n current_sum += (string[i] == '0' ? 1 : -1);\n if (current_sum < 0) {\n current_sum = 0;\n }\n if (current_sum > max_sum) {\n max_sum = current_sum;\n }\n }\n return max_sum ? max_sum : 0;\n}", + "test": "int main() {\n\n assert(func0(\"11000010001\", 11) == 6);\n\n assert(func0(\"10111\", 5) == 1);\n\n assert(func0(\"11011101100101\", 14) == 2);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 12d8 \nlea -0x1(%rsi),%eax\nxor %r8d,%r8d\nxor %ecx,%ecx\nlea 0x1(%rdi,%rax,1),%rsi\nxor %eax,%eax\nnopw 0x0(%rax,%rax,1)\nxor %edx,%edx\ncmpb $0x30,(%rdi)\nsete %dl\nlea -0x1(%rax,%rdx,2),%eax\ntest %eax,%eax\ncmovs %ecx,%eax\ncmp %eax,%r8d\ncmovl %eax,%r8d\nadd $0x1,%rdi\ncmp %rsi,%rdi\njne 12b0 \nmov %r8d,%eax\nretq\nnopl (%rax)\nxor %r8d,%r8d\nmov %r8d,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1250\nmovsxd rsi, esi\nxor edx, edx\nxor eax, eax\nlea rcx, [rdi+rsi]\nxor esi, esi\njmp short loc_1237\nloc_1220:\nsub eax, 1\ncmp eax, 0FFFFFFFFh\ncmovz eax, esi\ncmp edx, eax\ncmovl edx, eax\nadd rdi, 1\ncmp rcx, rdi\njz short loc_124D\nloc_1237:\ncmp byte ptr [rdi], 30h ; '0'\njnz short loc_1220\nadd eax, 1\ncmp edx, eax\ncmovl edx, eax\nadd rdi, 1\ncmp rcx, rdi\njnz short loc_1237\nloc_124D:\nmov eax, edx\nretn\nloc_1250:\nxor edx, edx\nmov eax, edx\nretn", + "ida_pseudo": "__int64 __fastcall func0(_BYTE *a1, int a2)\n{\n unsigned int v2; // edx\n int v3; // eax\n _BYTE *v4; // rcx\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 0;\n v3 = 0;\n v4 = &a1[a2];\n do\n {\n while ( *a1 == 48 )\n {\n if ( (int)v2 < ++v3 )\n v2 = v3;\n if ( v4 == ++a1 )\n return v2;\n }\n if ( --v3 == -1 )\n v3 = 0;\n if ( (int)v2 < v3 )\n v2 = v3;\n ++a1;\n }\n while ( v4 != a1 );\n return v2;\n}", + "ida_strip_asm": "sub_1200:\nendbr64\ntest esi, esi\njle short loc_1250\nmovsxd rsi, esi\nxor edx, edx\nxor eax, eax\nlea rcx, [rdi+rsi]\nxor esi, esi\njmp short loc_1237\nloc_1220:\nsub eax, 1\ncmp eax, 0FFFFFFFFh\ncmovz eax, esi\ncmp edx, eax\ncmovl edx, eax\nadd rdi, 1\ncmp rcx, rdi\njz short loc_124D\nloc_1237:\ncmp byte ptr [rdi], 30h ; '0'\njnz short loc_1220\nadd eax, 1\ncmp edx, eax\ncmovl edx, eax\nadd rdi, 1\ncmp rcx, rdi\njnz short loc_1237\nloc_124D:\nmov eax, edx\nretn\nloc_1250:\nxor edx, edx\nmov eax, edx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1200(_BYTE *a1, int a2)\n{\n unsigned int v2; // edx\n int v3; // eax\n _BYTE *v4; // rcx\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 0;\n v3 = 0;\n v4 = &a1[a2];\n do\n {\n while ( *a1 == 48 )\n {\n if ( (int)v2 < ++v3 )\n v2 = v3;\n if ( v4 == ++a1 )\n return v2;\n }\n if ( --v3 == -1 )\n v3 = 0;\n if ( (int)v2 < v3 )\n v2 = v3;\n ++a1;\n }\n while ( v4 != a1 );\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1200(uint8_t *a1, int a2) {\n unsigned int v2;\n int v3;\n uint8_t *v4;\n if (a2 <= 0) return 0LL;\n v2 = 0;\n v3 = 0;\n v4 = &a1[a2];\n do {\n while (*a1 == 48) {\n if ((int)v2 < ++v3) v2 = v3;\n if (v4 == ++a1) return v2;\n }\n if (--v3 == -1) v3 = 0;\n if ((int)v2 < v3) v2 = v3;\n ++a1;\n } while (v4 != a1);\n return v2;\n}", + "ida_pseudo_norm": "long long func0(uint8_t *a1, int a2) {\n unsigned int v2;\n int v3;\n uint8_t *v4;\n if (a2 <= 0) return 0LL;\n v2 = 0;\n v3 = 0;\n v4 = &a1[a2];\n do {\n while (*a1 == 48) {\n if ((int)v2 < ++v3) v2 = v3;\n if (v4 == ++a1) return v2;\n }\n if (--v3 == -1) v3 = 0;\n if ((int)v2 < v3) v2 = v3;\n ++a1;\n } while (v4 != a1);\n return v2;\n}" + }, + { + "index": 126, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int a, int b) {\n int sum = 0;\n for (int i = 1; i < (a < b ? a : b); i++) {\n if (a % i == 0 && b % i == 0) {\n sum += i;\n }\n }\n return sum;\n}", + "test": "int main() {\n\n assert(func0(10, 15) == 6);\n\n assert(func0(100, 150) == 93);\n\n assert(func0(4, 6) == 3);\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x1,-0x4(%rbp)\njmp 118b \nmov -0x14(%rbp),%eax\ncltd\nidivl -0x4(%rbp)\nmov %edx,%eax\ntest %eax,%eax\njne 1187 \nmov -0x18(%rbp),%eax\ncltd\nidivl -0x4(%rbp)\nmov %edx,%eax\ntest %eax,%eax\njne 1187 \nmov -0x4(%rbp),%eax\nadd %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x14(%rbp),%eax\ncmp %eax,-0x18(%rbp)\ncmovle -0x18(%rbp),%eax\ncmp %eax,-0x4(%rbp)\njl 1167 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 1\njmp short loc_118B\nloc_1167:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njnz short loc_1187\nmov eax, [rbp+var_18]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njnz short loc_1187\nmov eax, [rbp+var_4]\nadd [rbp+var_8], eax\nloc_1187:\nadd [rbp+var_4], 1\nloc_118B:\nmov edx, [rbp+var_18]\nmov eax, [rbp+var_14]\ncmp edx, eax\ncmovle eax, edx\ncmp [rbp+var_4], eax\njl short loc_1167\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n int v2; // eax\n unsigned int v4; // [rsp+10h] [rbp-8h]\n int i; // [rsp+14h] [rbp-4h]\n\n v4 = 0;\n for ( i = 1; ; ++i )\n {\n v2 = a1;\n if ( a2 <= a1 )\n v2 = a2;\n if ( i >= v2 )\n break;\n if ( !(a1 % i) && !(a2 % i) )\n v4 += i;\n }\n return v4;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 1\njmp short loc_118B\nloc_1167:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njnz short loc_1187\nmov eax, [rbp+var_18]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njnz short loc_1187\nmov eax, [rbp+var_4]\nadd [rbp+var_8], eax\nloc_1187:\nadd [rbp+var_4], 1\nloc_118B:\nmov edx, [rbp+var_18]\nmov eax, [rbp+var_14]\ncmp edx, eax\ncmovle eax, edx\ncmp [rbp+var_4], eax\njl short loc_1167\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2)\n{\n int v2; // eax\n unsigned int v4; // [rsp+10h] [rbp-8h]\n int i; // [rsp+14h] [rbp-4h]\n\n v4 = 0;\n for ( i = 1; ; ++i )\n {\n v2 = a1;\n if ( a2 <= a1 )\n v2 = a2;\n if ( i >= v2 )\n break;\n if ( !(a1 % i) && !(a2 % i) )\n v4 += i;\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2) {\n int v2;\n unsigned int v4;\n int i;\n v4 = 0;\n for (i = 1;; ++i) {\n v2 = a1;\n if (a2 <= a1) v2 = a2;\n if (i >= v2) break;\n if (!(a1 % i) && !(a2 % i)) v4 += i;\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n int v2;\n unsigned int v4;\n int i;\n v4 = 0;\n for (i = 1;; ++i) {\n v2 = a1;\n if (a2 <= a1) v2 = a2;\n if (i >= v2) break;\n if (!(a1 % i) && !(a2 % i)) v4 += i;\n }\n return v4;\n}" + }, + { + "index": 126, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int a, int b) {\n int sum = 0;\n for (int i = 1; i < (a < b ? a : b); i++) {\n if (a % i == 0 && b % i == 0) {\n sum += i;\n }\n }\n return sum;\n}", + "test": "int main() {\n\n assert(func0(10, 15) == 6);\n\n assert(func0(100, 150) == 93);\n\n assert(func0(4, 6) == 3);\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ncmp %edi,%esi\nmov %edi,%r9d\ncmovle %esi,%r9d\ncmp $0x1,%r9d\njle 118b \nmov $0x1,%ecx\nmov $0x0,%r8d\njmp 1171 \nadd $0x1,%ecx\ncmp %r9d,%ecx\nje 1191 \nmov %edi,%eax\ncltd\nidiv %ecx\ntest %edx,%edx\njne 1169 \nmov %esi,%eax\ncltd\nidiv %ecx\nlea (%r8,%rcx,1),%eax\ntest %edx,%edx\ncmove %eax,%r8d\njmp 1169 \nmov $0x0,%r8d\nmov %r8d,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ncmp esi, edi\nmov r9d, edi\ncmovle r9d, esi\ncmp r9d, 1\njle short loc_118B\nmov ecx, 1\nmov r8d, 0\njmp short loc_1171\nloc_1169:\nadd ecx, 1\ncmp ecx, r9d\njz short loc_1191\nloc_1171:\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_1169\nmov eax, esi\ncdq\nidiv ecx\nlea eax, [r8+rcx]\ntest edx, edx\ncmovz r8d, eax\njmp short loc_1169\nloc_118B:\nmov r8d, 0\nloc_1191:\nmov eax, r8d\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n int v2; // r9d\n int v3; // ecx\n unsigned int v4; // r8d\n\n v2 = a1;\n if ( a2 <= a1 )\n v2 = a2;\n if ( v2 <= 1 )\n {\n return 0;\n }\n else\n {\n v3 = 1;\n v4 = 0;\n do\n {\n if ( !(a1 % v3) && !(a2 % v3) )\n v4 += v3;\n ++v3;\n }\n while ( v3 != v2 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ncmp esi, edi\nmov r9d, edi\ncmovle r9d, esi\ncmp r9d, 1\njle short loc_118B\nmov ecx, 1\nmov r8d, 0\njmp short loc_1171\nloc_1169:\nadd ecx, 1\ncmp ecx, r9d\njz short loc_1191\nloc_1171:\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_1169\nmov eax, esi\ncdq\nidiv ecx\nlea eax, [r8+rcx]\ntest edx, edx\ncmovz r8d, eax\njmp short loc_1169\nloc_118B:\nmov r8d, 0\nloc_1191:\nmov eax, r8d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2)\n{\n int v2; // r9d\n int v3; // ecx\n unsigned int v4; // r8d\n\n v2 = a1;\n if ( a2 <= a1 )\n v2 = a2;\n if ( v2 <= 1 )\n {\n return 0;\n }\n else\n {\n v3 = 1;\n v4 = 0;\n do\n {\n if ( !(a1 % v3) && !(a2 % v3) )\n v4 += v3;\n ++v3;\n }\n while ( v3 != v2 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2) {\n int v2;\n int v3;\n unsigned int v4;\n v2 = a1;\n if (a2 <= a1) v2 = a2;\n if (v2 <= 1) {\n return 0;\n } else {\n v3 = 1;\n v4 = 0;\n do {\n if (!(a1 % v3) && !(a2 % v3)) v4 += v3;\n ++v3;\n } while (v3 != v2);\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n int v2;\n int v3;\n unsigned int v4;\n v2 = a1;\n if (a2 <= a1) v2 = a2;\n if (v2 <= 1) {\n return 0;\n } else {\n v3 = 1;\n v4 = 0;\n do {\n if (!(a1 % v3) && !(a2 % v3)) v4 += v3;\n ++v3;\n } while (v3 != v2);\n }\n return v4;\n}" + }, + { + "index": 127, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int x, int y) {\n if (y < 0) {\n return -func0(x, -y);\n } else if (y == 0) {\n return 0;\n } else if (y == 1) {\n return x;\n } else {\n return x + func0(x, y - 1);\n }\n}", + "test": "int main() {\n\n assert(func0(10, 20) == 200);\n\n assert(func0(5, 10) == 50);\n\n assert(func0(4, 8) == 32);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %edi,-0x4(%rbp)\nmov %esi,-0x8(%rbp)\ncmpl $0x0,-0x8(%rbp)\njns 1178 \nmov -0x8(%rbp),%eax\nneg %eax\nmov %eax,%edx\nmov -0x4(%rbp),%eax\nmov %edx,%esi\nmov %eax,%edi\ncallq 1149 \nneg %eax\njmp 11a7 \ncmpl $0x0,-0x8(%rbp)\njne 1185 \nmov $0x0,%eax\njmp 11a7 \ncmpl $0x1,-0x8(%rbp)\njne 1190 \nmov -0x4(%rbp),%eax\njmp 11a7 \nmov -0x8(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x4(%rbp),%eax\nmov %edx,%esi\nmov %eax,%edi\ncallq 1149 \nmov -0x4(%rbp),%edx\nadd %edx,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\ncmp [rbp+var_8], 0\njns short loc_1178\nmov eax, [rbp+var_8]\nneg eax\nmov edx, eax\nmov eax, [rbp+var_4]\nmov esi, edx\nmov edi, eax\ncall func0\nneg eax\njmp short locret_11A7\nloc_1178:\ncmp [rbp+var_8], 0\njnz short loc_1185\nmov eax, 0\njmp short locret_11A7\nloc_1185:\ncmp [rbp+var_8], 1\njnz short loc_1190\nmov eax, [rbp+var_4]\njmp short locret_11A7\nloc_1190:\nmov eax, [rbp+var_8]\nlea edx, [rax-1]\nmov eax, [rbp+var_4]\nmov esi, edx\nmov edi, eax\ncall func0\nmov edx, [rbp+var_4]\nadd eax, edx\nlocret_11A7:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1, int a2)\n{\n if ( a2 < 0 )\n return (unsigned int)-func0(a1, (unsigned int)-a2);\n if ( !a2 )\n return 0LL;\n if ( a2 == 1 )\n return a1;\n return a1 + (unsigned int)func0(a1, (unsigned int)(a2 - 1));\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\ncmp [rbp+var_8], 0\njns short loc_1178\nmov eax, [rbp+var_8]\nneg eax\nmov edx, eax\nmov eax, [rbp+var_4]\nmov esi, edx\nmov edi, eax\ncall sub_1149\nneg eax\njmp short locret_11A7\nloc_1178:\ncmp [rbp+var_8], 0\njnz short loc_1185\nmov eax, 0\njmp short locret_11A7\nloc_1185:\ncmp [rbp+var_8], 1\njnz short loc_1190\nmov eax, [rbp+var_4]\njmp short locret_11A7\nloc_1190:\nmov eax, [rbp+var_8]\nlea edx, [rax-1]\nmov eax, [rbp+var_4]\nmov esi, edx\nmov edi, eax\ncall sub_1149\nmov edx, [rbp+var_4]\nadd eax, edx\nlocret_11A7:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(unsigned int a1, int a2)\n{\n if ( a2 < 0 )\n return (unsigned int)-sub_1149(a1, (unsigned int)-a2);\n if ( !a2 )\n return 0LL;\n if ( a2 == 1 )\n return a1;\n return a1 + (unsigned int)sub_1149(a1, (unsigned int)(a2 - 1));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(unsigned int a1, int a2) {\n if (a2 < 0) return (unsigned int)-sub_1149(a1, (unsigned int)-a2);\n if (!a2) return 0LL;\n if (a2 == 1) return a1;\n return a1 + (unsigned int)sub_1149(a1, (unsigned int)(a2 - 1));\n}", + "ida_pseudo_norm": "long long func0(unsigned int a1, int a2) {\n if (a2 < 0) return (unsigned int)-func0(a1, (unsigned int)-a2);\n if (!a2) return 0LL;\n if (a2 == 1) return a1;\n return a1 + (unsigned int)func0(a1, (unsigned int)(a2 - 1));\n}" + }, + { + "index": 127, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int x, int y) {\n if (y < 0) {\n return -func0(x, -y);\n } else if (y == 0) {\n return 0;\n } else if (y == 1) {\n return x;\n } else {\n return x + func0(x, y - 1);\n }\n}", + "test": "int main() {\n\n assert(func0(10, 20) == 200);\n\n assert(func0(5, 10) == 50);\n\n assert(func0(4, 8) == 32);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %edi,%ebx\ntest %esi,%esi\njs 1161 \nmov %esi,%eax\nje 115f \nmov %edi,%eax\ncmp $0x1,%esi\njne 116c \npop %rbx\nretq\nneg %esi\ncallq 1149 \nneg %eax\njmp 115f \nsub $0x1,%esi\ncallq 1149 \nadd %ebx,%eax\njmp 115f \n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov ebx, edi\ntest esi, esi\njs short loc_1161\nmov eax, esi\njz short loc_115F\nmov eax, edi\ncmp esi, 1\njnz short loc_116C\nloc_115F:\npop rbx\nretn\nloc_1161:\nneg esi\ncall func0\nneg eax\njmp short loc_115F\nloc_116C:\nsub esi, 1\ncall func0\nadd eax, ebx\njmp short loc_115F", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 result; // rax\n\n if ( a2 < 0 )\n return (unsigned int)-func0(a1, (unsigned int)-a2);\n result = (unsigned int)a2;\n if ( a2 )\n {\n result = (unsigned int)a1;\n if ( a2 != 1 )\n return (unsigned int)a1 + (unsigned int)func0(a1, (unsigned int)(a2 - 1));\n }\n return result;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbx\nmov ebx, edi\ntest esi, esi\njs short loc_1161\nmov eax, esi\njz short loc_115F\nmov eax, edi\ncmp esi, 1\njnz short loc_116C\nloc_115F:\npop rbx\nretn\nloc_1161:\nneg esi\ncall sub_1149\nneg eax\njmp short loc_115F\nloc_116C:\nsub esi, 1\ncall sub_1149\nadd eax, ebx\njmp short loc_115F", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(__int64 a1, int a2)\n{\n __int64 result; // rax\n\n if ( a2 < 0 )\n return (unsigned int)-sub_1149(a1, (unsigned int)-a2);\n result = (unsigned int)a2;\n if ( a2 )\n {\n result = (unsigned int)a1;\n if ( a2 != 1 )\n return (unsigned int)a1 + (unsigned int)sub_1149(a1, (unsigned int)(a2 - 1));\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(long long a1, int a2) {\n long long result;\n if (a2 < 0) return (unsigned int)-sub_1149(a1, (unsigned int)-a2);\n result = (unsigned int)a2;\n if (a2) {\n result = (unsigned int)a1;\n if (a2 != 1)\n return (unsigned int)a1 +\n (unsigned int)sub_1149(a1, (unsigned int)(a2 - 1));\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long result;\n if (a2 < 0) return (unsigned int)-func0(a1, (unsigned int)-a2);\n result = (unsigned int)a2;\n if (a2) {\n result = (unsigned int)a1;\n if (a2 != 1)\n return (unsigned int)a1 + (unsigned int)func0(a1, (unsigned int)(a2 - 1));\n }\n return result;\n}" + }, + { + "index": 127, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int x, int y) {\n if (y < 0) {\n return -func0(x, -y);\n } else if (y == 0) {\n return 0;\n } else if (y == 1) {\n return x;\n } else {\n return x + func0(x, y - 1);\n }\n}", + "test": "int main() {\n\n assert(func0(10, 20) == 200);\n\n assert(func0(5, 10) == 50);\n\n assert(func0(4, 8) == 32);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x1,%eax\nxor %r8d,%r8d\nnopl 0x0(%rax)\ntest %esi,%esi\njs 12ba \nje 12c0 \nmov %edi,%edx\nimul %eax,%edx\nadd %edx,%r8d\ncmp $0x1,%esi\nje 12c0 \nsub $0x1,%esi\ntest %esi,%esi\njns 12a4 \nneg %esi\nneg %eax\njmp 12a0 \nmov %r8d,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\nmov ecx, edi\nmov eax, esi\ntest esi, esi\njns short loc_1240\nneg eax\nmov edi, 0FFFFFFFFh\nmov edx, eax\nxor eax, eax\nloc_1217:\nimul edi, ecx\nlea ecx, [rdx-1]\ntest dl, 1\njnz short loc_1235\nmov eax, edi\nmov edx, ecx\njmp short loc_1235\nloc_1230:\nadd eax, edi\nsub edx, 2\nloc_1235:\nadd eax, edi\ncmp edx, 1\njnz short loc_1230\nlocret_123C:\nretn\nloc_1240:\njz short locret_123C\nmov edx, esi\nmov edi, 1\nxor eax, eax\njmp short loc_1217", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n __int64 result; // rax\n int v4; // edi\n int v5; // edx\n int v6; // eax\n int v7; // edi\n\n result = (unsigned int)a2;\n if ( a2 >= 0 )\n {\n if ( !a2 )\n return result;\n v5 = a2;\n v4 = 1;\n v6 = 0;\n }\n else\n {\n v4 = -1;\n v5 = -a2;\n v6 = 0;\n }\n v7 = a1 * v4;\n if ( (v5 & 1) == 0 )\n {\n v6 = v7;\n --v5;\n }\n while ( 1 )\n {\n result = (unsigned int)(v7 + v6);\n if ( v5 == 1 )\n break;\n v6 = v7 + result;\n v5 -= 2;\n }\n return result;\n}", + "ida_strip_asm": "sub_1200:\nendbr64\nmov ecx, edi\nmov eax, esi\ntest esi, esi\njns short loc_1240\nneg eax\nmov edi, 0FFFFFFFFh\nmov edx, eax\nxor eax, eax\nloc_1217:\nimul edi, ecx\nlea ecx, [rdx-1]\ntest dl, 1\njnz short loc_1235\nmov eax, edi\nmov edx, ecx\njmp short loc_1235\nloc_1230:\nadd eax, edi\nsub edx, 2\nloc_1235:\nadd eax, edi\ncmp edx, 1\njnz short loc_1230\nlocret_123C:\nretn\nloc_1240:\njz short locret_123C\nmov edx, esi\nmov edi, 1\nxor eax, eax\njmp short loc_1217", + "ida_strip_pseudo": "__int64 __fastcall sub_1200(int a1, int a2)\n{\n __int64 result; // rax\n int v4; // edi\n int v5; // edx\n int v6; // eax\n int v7; // edi\n\n result = (unsigned int)a2;\n if ( a2 >= 0 )\n {\n if ( !a2 )\n return result;\n v5 = a2;\n v4 = 1;\n v6 = 0;\n }\n else\n {\n v4 = -1;\n v5 = -a2;\n v6 = 0;\n }\n v7 = a1 * v4;\n if ( (v5 & 1) == 0 )\n {\n v6 = v7;\n --v5;\n }\n while ( 1 )\n {\n result = (unsigned int)(v7 + v6);\n if ( v5 == 1 )\n break;\n v6 = v7 + result;\n v5 -= 2;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1200(int a1, int a2) {\n long long result;\n int v4;\n int v5;\n int v6;\n int v7;\n result = (unsigned int)a2;\n if (a2 >= 0) {\n if (!a2) return result;\n v5 = a2;\n v4 = 1;\n v6 = 0;\n } else {\n v4 = -1;\n v5 = -a2;\n v6 = 0;\n }\n v7 = a1 * v4;\n if ((v5 & 1) == 0) {\n v6 = v7;\n --v5;\n }\n while (1) {\n result = (unsigned int)(v7 + v6);\n if (v5 == 1) break;\n v6 = v7 + result;\n v5 -= 2;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n long long result;\n int v4;\n int v5;\n int v6;\n int v7;\n result = (unsigned int)a2;\n if (a2 >= 0) {\n if (!a2) return result;\n v5 = a2;\n v4 = 1;\n v6 = 0;\n } else {\n v4 = -1;\n v5 = -a2;\n v6 = 0;\n }\n v7 = a1 * v4;\n if ((v5 & 1) == 0) {\n v6 = v7;\n --v5;\n }\n while (1) {\n result = (unsigned int)(v7 + v6);\n if (v5 == 1) break;\n v6 = v7 + result;\n v5 -= 2;\n }\n return result;\n}" + }, + { + "index": 128, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(int n, char* str, int* count) {\n static char* word_len[100];\n int index = 0;\n char* token = strtok(str, \" \");\n while (token != NULL) {\n if (strlen(token) > n) {\n word_len[index++] = token;\n }\n token = strtok(NULL, \" \");\n }\n *count = index;\n return word_len;\n}", + "test": "int main() {\n\n int count;\n\n char test_str1[] = \"python is a programming language\";\n\n char test_str2[] = \"writing a program\";\n\n char test_str3[] = \"sorting list\";\n\n \n\n char** result1 = func0(3, test_str1, &count);\n\n assert(count == 3 && strcmp(result1[0], \"python\") == 0 && strcmp(result1[1], \"programming\") == 0 && strcmp(result1[2], \"language\") == 0);\n\n \n\n char** result2 = func0(2, test_str2, &count);\n\n assert(count == 2 && strcmp(result2[0], \"writing\") == 0 && strcmp(result2[1], \"program\") == 0);\n\n \n\n char** result3 = func0(5, test_str3, &count);\n\n assert(count == 1 && strcmp(result3[0], \"sorting\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %edi,-0x14(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %rdx,-0x28(%rbp)\nmovl $0x0,-0xc(%rbp)\nmov -0x20(%rbp),%rax\nlea 0xe16(%rip),%rsi\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,-0x8(%rbp)\njmp 124e \nmov -0x8(%rbp),%rax\nmov %rax,%rdi\ncallq 1090 \nmov -0x14(%rbp),%edx\nmovslq %edx,%rdx\ncmp %rdx,%rax\njbe 1239 \nmov -0xc(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0xc(%rbp)\ncltq\nlea 0x0(,%rax,8),%rcx\nlea 0x2e0f(%rip),%rdx\nmov -0x8(%rbp),%rax\nmov %rax,(%rcx,%rdx,1)\nlea 0xdc8(%rip),%rsi\nmov $0x0,%edi\ncallq 10d0 \nmov %rax,-0x8(%rbp)\ncmpq $0x0,-0x8(%rbp)\njne 1200 \nmov -0x28(%rbp),%rax\nmov -0xc(%rbp),%edx\nmov %edx,(%rax)\nlea 0x2ddb(%rip),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_14], edi\nmov [rbp+s], rsi\nmov [rbp+var_28], rdx\nmov [rbp+var_C], 0\nmov rax, [rbp+s]\nlea rdx, delim; \" \"\nmov rsi, rdx; delim\nmov rdi, rax; s\ncall _strtok\nmov [rbp+var_8], rax\njmp short loc_1254\nloc_1203:\nmov rax, [rbp+var_8]\nmov rdi, rax; s\ncall _strlen\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\ncmp rdx, rax\njnb short loc_123C\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\ncdqe\nlea rcx, ds:0[rax*8]\nlea rdx, _word_len_1\nmov rax, [rbp+var_8]\nmov [rcx+rdx], rax\nloc_123C:\nlea rax, delim; \" \"\nmov rsi, rax; delim\nmov edi, 0; s\ncall _strtok\nmov [rbp+var_8], rax\nloc_1254:\ncmp [rbp+var_8], 0\njnz short loc_1203\nmov rax, [rbp+var_28]\nmov edx, [rbp+var_C]\nmov [rax], edx\nlea rax, _word_len_1\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(int a1, char *a2, _DWORD *a3)\n{\n int v3; // eax\n int v6; // [rsp+24h] [rbp-Ch]\n const char *i; // [rsp+28h] [rbp-8h]\n\n v6 = 0;\n for ( i = strtok(a2, \" \"); i; i = strtok(0LL, \" \") )\n {\n if ( a1 < strlen(i) )\n {\n v3 = v6++;\n word_len_1[v3] = i;\n }\n }\n *a3 = v6;\n return word_len_1;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_14], edi\nmov [rbp+s], rsi\nmov [rbp+var_28], rdx\nmov [rbp+var_C], 0\nmov rax, [rbp+s]\nlea rdx, delim; \" \"\nmov rsi, rdx; delim\nmov rdi, rax; s\ncall _strtok\nmov [rbp+var_8], rax\njmp short loc_1254\nloc_1203:\nmov rax, [rbp+var_8]\nmov rdi, rax; s\ncall _strlen\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\ncmp rdx, rax\njnb short loc_123C\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\ncdqe\nlea rcx, ds:0[rax*8]\nlea rdx, unk_4040\nmov rax, [rbp+var_8]\nmov [rcx+rdx], rax\nloc_123C:\nlea rax, delim; \" \"\nmov rsi, rax; delim\nmov edi, 0; s\ncall _strtok\nmov [rbp+var_8], rax\nloc_1254:\ncmp [rbp+var_8], 0\njnz short loc_1203\nmov rax, [rbp+var_28]\nmov edx, [rbp+var_C]\nmov [rax], edx\nlea rax, unk_4040\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11C9(int a1, char *a2, _DWORD *a3)\n{\n int v3; // eax\n int v6; // [rsp+24h] [rbp-Ch]\n const char *i; // [rsp+28h] [rbp-8h]\n\n v6 = 0;\n for ( i = strtok(a2, \" \"); i; i = strtok(0LL, \" \") )\n {\n if ( a1 < strlen(i) )\n {\n v3 = v6++;\n qword_4040[v3] = i;\n }\n }\n *a3 = v6;\n return qword_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11C9(int a1, char *a2, uint32_t *a3) {\n int v3;\n int v6;\n const char *i;\n v6 = 0;\n for (i = strtok(a2, \" \"); i; i = strtok(0LL, \" \")) {\n if (a1 < strlen(i)) {\n v3 = v6++;\n qword_4040[v3] = i;\n }\n }\n *a3 = v6;\n return qword_4040;\n}", + "ida_pseudo_norm": "uint64_t *func0(int a1, char *a2, uint32_t *a3) {\n int v3;\n int v6;\n const char *i;\n v6 = 0;\n for (i = strtok(a2, \" \"); i; i = strtok(0LL, \" \")) {\n if (a1 < strlen(i)) {\n v3 = v6++;\n word_len_1[v3] = i;\n }\n }\n *a3 = v6;\n return word_len_1;\n}" + }, + { + "index": 128, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(int n, char* str, int* count) {\n static char* word_len[100];\n int index = 0;\n char* token = strtok(str, \" \");\n while (token != NULL) {\n if (strlen(token) > n) {\n word_len[index++] = token;\n }\n token = strtok(NULL, \" \");\n }\n *count = index;\n return word_len;\n}", + "test": "int main() {\n\n int count;\n\n char test_str1[] = \"python is a programming language\";\n\n char test_str2[] = \"writing a program\";\n\n char test_str3[] = \"sorting list\";\n\n \n\n char** result1 = func0(3, test_str1, &count);\n\n assert(count == 3 && strcmp(result1[0], \"python\") == 0 && strcmp(result1[1], \"programming\") == 0 && strcmp(result1[2], \"language\") == 0);\n\n \n\n char** result2 = func0(2, test_str2, &count);\n\n assert(count == 2 && strcmp(result2[0], \"writing\") == 0 && strcmp(result2[1], \"program\") == 0);\n\n \n\n char** result3 = func0(5, test_str3, &count);\n\n assert(count == 1 && strcmp(result3[0], \"sorting\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %edi,%ebp\nmov %rsi,%rdi\nmov %rdx,%r13\nlea 0xe5e(%rip),%rsi\ncallq 1090 \ntest %rax,%rax\nje 1209 \nmov %rax,%rdx\nmov $0x0,%ebx\nlea 0x2e81(%rip),%r12\njmp 11da \nlea 0xe3c(%rip),%rsi\nmov $0x0,%edi\ncallq 1090 \nmov %rax,%rdx\ntest %rax,%rax\nje 120e \nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nsub $0x1,%rax\nmovslq %ebp,%rcx\ncmp %rcx,%rax\njbe 11c1 \nmovslq %ebx,%rax\nmov %rdx,(%r12,%rax,8)\nlea 0x1(%rbx),%ebx\njmp 11c1 \nmov $0x0,%ebx\nmov %ebx,0x0(%r13)\nlea 0x2e27(%rip),%rax\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12d, edi\nmov rdi, rsi; s\nmov r15, rdx\nlea rsi, delim; \" \"\ncall _strtok\ntest rax, rax\njz short loc_123E\nmov rbx, rax\nmov ebp, 0\nmovsxd r12, r12d\nlea r14, _word_len_1\nlea r13, delim; \" \"\njmp short loc_1225\nloc_1210:\nmov rsi, r13; delim\nmov edi, 0; s\ncall _strtok\nmov rbx, rax\ntest rax, rax\njz short loc_1243\nloc_1225:\nmov rdi, rbx; s\ncall _strlen\ncmp r12, rax\njnb short loc_1210\nmovsxd rax, ebp\nmov [r14+rax*8], rbx\nlea ebp, [rbp+1]\njmp short loc_1210\nloc_123E:\nmov ebp, 0\nloc_1243:\nmov [r15], ebp\nlea rax, _word_len_1\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(int a1, char *a2, _DWORD *a3)\n{\n char *v4; // rax\n char *v5; // rbx\n int v6; // ebp\n\n v4 = strtok(a2, \" \");\n if ( v4 )\n {\n v5 = v4;\n v6 = 0;\n do\n {\n if ( a1 < strlen(v5) )\n word_len_1[v6++] = v5;\n v5 = strtok(0LL, \" \");\n }\n while ( v5 );\n }\n else\n {\n v6 = 0;\n }\n *a3 = v6;\n return word_len_1;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12d, edi\nmov rdi, rsi; s\nmov r15, rdx\nlea rsi, delim; \" \"\ncall _strtok\ntest rax, rax\njz short loc_123E\nmov rbx, rax\nmov ebp, 0\nmovsxd r12, r12d\nlea r14, unk_4040\nlea r13, delim; \" \"\njmp short loc_1225\nloc_1210:\nmov rsi, r13; delim\nmov edi, 0; s\ncall _strtok\nmov rbx, rax\ntest rax, rax\njz short loc_1243\nloc_1225:\nmov rdi, rbx; s\ncall _strlen\ncmp r12, rax\njnb short loc_1210\nmovsxd rax, ebp\nmov [r14+rax*8], rbx\nlea ebp, [rbp+1]\njmp short loc_1210\nloc_123E:\nmov ebp, 0\nloc_1243:\nmov [r15], ebp\nlea rax, unk_4040\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11C9(int a1, char *a2, _DWORD *a3)\n{\n char *v4; // rax\n char *v5; // rbx\n int v6; // ebp\n\n v4 = strtok(a2, \" \");\n if ( v4 )\n {\n v5 = v4;\n v6 = 0;\n do\n {\n if ( a1 < strlen(v5) )\n qword_4040[v6++] = v5;\n v5 = strtok(0LL, \" \");\n }\n while ( v5 );\n }\n else\n {\n v6 = 0;\n }\n *a3 = v6;\n return qword_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11C9(int a1, char *a2, uint32_t *a3) {\n char *v4;\n char *v5;\n int v6;\n v4 = strtok(a2, \" \");\n if (v4) {\n v5 = v4;\n v6 = 0;\n do {\n if (a1 < strlen(v5)) qword_4040[v6++] = v5;\n v5 = strtok(0LL, \" \");\n } while (v5);\n } else {\n v6 = 0;\n }\n *a3 = v6;\n return qword_4040;\n}", + "ida_pseudo_norm": "uint64_t *func0(int a1, char *a2, uint32_t *a3) {\n char *v4;\n char *v5;\n int v6;\n v4 = strtok(a2, \" \");\n if (v4) {\n v5 = v4;\n v6 = 0;\n do {\n if (a1 < strlen(v5)) word_len_1[v6++] = v5;\n v5 = strtok(0LL, \" \");\n } while (v5);\n } else {\n v6 = 0;\n }\n *a3 = v6;\n return word_len_1;\n}" + }, + { + "index": 128, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(int n, char* str, int* count) {\n static char* word_len[100];\n int index = 0;\n char* token = strtok(str, \" \");\n while (token != NULL) {\n if (strlen(token) > n) {\n word_len[index++] = token;\n }\n token = strtok(NULL, \" \");\n }\n *count = index;\n return word_len;\n}", + "test": "int main() {\n\n int count;\n\n char test_str1[] = \"python is a programming language\";\n\n char test_str2[] = \"writing a program\";\n\n char test_str3[] = \"sorting list\";\n\n \n\n char** result1 = func0(3, test_str1, &count);\n\n assert(count == 3 && strcmp(result1[0], \"python\") == 0 && strcmp(result1[1], \"programming\") == 0 && strcmp(result1[2], \"language\") == 0);\n\n \n\n char** result2 = func0(2, test_str2, &count);\n\n assert(count == 2 && strcmp(result2[0], \"writing\") == 0 && strcmp(result2[1], \"program\") == 0);\n\n \n\n char** result3 = func0(5, test_str3, &count);\n\n assert(count == 1 && strcmp(result3[0], \"sorting\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\nmov %rdx,%r13\npush %r12\nmovslq %edi,%r12\nmov %rsi,%rdi\nlea 0xc3a(%rip),%rsi\npush %rbp\npush %rbx\ncallq 10b0 \ntest %rax,%rax\nje 1430 \nmov %rax,%rbx\nxor %ebp,%ebp\nlea 0x2c5e(%rip),%r14\nnopw 0x0(%rax,%rax,1)\nmov %rbx,%rdi\ncallq 1080 \ncmp %r12,%rax\njbe 13ff \nmovslq %ebp,%rax\nadd $0x1,%ebp\nmov %rbx,(%r14,%rax,8)\nlea 0xbfe(%rip),%rsi\nxor %edi,%edi\ncallq 10b0 \nmov %rax,%rbx\ntest %rax,%rax\njne 13e8 \npop %rbx\nmov %ebp,0x0(%r13)\nlea 0x2c1f(%rip),%rax\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopl 0x0(%rax)\nxor %ebp,%ebp\njmp 1415 \nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov r15, rdx\npush r14\npush r13\nlea r13, delim; \" \"\npush r12\nmovsxd r12, edi\nmov rdi, rsi; s\nmov rsi, r13; delim\npush rbp\npush rbx\nsub rsp, 8\ncall _strtok\ntest rax, rax\njz short loc_1420\nmov rbx, rax\nxor ebp, ebp\nlea r14, _word_len_1\nnop dword ptr [rax+rax+00h]\nloc_13E0:\nmov rdi, rbx; s\ncall _strlen\ncmp r12, rax\njnb short loc_13F7\nmovsxd rax, ebp\nadd ebp, 1\nmov [r14+rax*8], rbx\nloc_13F7:\nmov rsi, r13; delim\nxor edi, edi; s\ncall _strtok\nmov rbx, rax\ntest rax, rax\njnz short loc_13E0\nloc_1409:\nmov [r15], ebp\nadd rsp, 8\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1420:\nxor ebp, ebp\nlea r14, _word_len_1\njmp short loc_1409", + "ida_pseudo": "_QWORD *__fastcall func0(int a1, char *a2, _DWORD *a3)\n{\n char *v4; // rax\n char *v5; // rbx\n int v6; // ebp\n __int64 v7; // rax\n\n v4 = strtok(a2, \" \");\n if ( v4 )\n {\n v5 = v4;\n v6 = 0;\n do\n {\n if ( a1 < strlen(v5) )\n {\n v7 = v6++;\n word_len_1[v7] = v5;\n }\n v5 = strtok(0LL, \" \");\n }\n while ( v5 );\n }\n else\n {\n v6 = 0;\n }\n *a3 = v6;\n return word_len_1;\n}", + "ida_strip_asm": "sub_13A0:\nendbr64\npush r15\nmov r15, rdx\npush r14\npush r13\nlea r13, delim; \" \"\npush r12\nmovsxd r12, edi\nmov rdi, rsi; s\nmov rsi, r13; delim\npush rbp\npush rbx\nsub rsp, 8\ncall _strtok\ntest rax, rax\njz short loc_1420\nmov rbx, rax\nxor ebp, ebp\nlea r14, unk_4040\nnop dword ptr [rax+rax+00h]\nloc_13E0:\nmov rdi, rbx; s\ncall _strlen\ncmp r12, rax\njnb short loc_13F7\nmovsxd rax, ebp\nadd ebp, 1\nmov [r14+rax*8], rbx\nloc_13F7:\nmov rsi, r13; delim\nxor edi, edi; s\ncall _strtok\nmov rbx, rax\ntest rax, rax\njnz short loc_13E0\nloc_1409:\nmov [r15], ebp\nadd rsp, 8\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1420:\nxor ebp, ebp\nlea r14, unk_4040\njmp short loc_1409", + "ida_strip_pseudo": "_QWORD *__fastcall sub_13A0(int a1, char *a2, _DWORD *a3)\n{\n char *v4; // rax\n char *v5; // rbx\n int v6; // ebp\n __int64 v7; // rax\n\n v4 = strtok(a2, \" \");\n if ( v4 )\n {\n v5 = v4;\n v6 = 0;\n do\n {\n if ( a1 < strlen(v5) )\n {\n v7 = v6++;\n qword_4040[v7] = v5;\n }\n v5 = strtok(0LL, \" \");\n }\n while ( v5 );\n }\n else\n {\n v6 = 0;\n }\n *a3 = v6;\n return qword_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_13A0(int a1, char *a2, uint32_t *a3) {\n char *v4;\n char *v5;\n int v6;\n long long v7;\n v4 = strtok(a2, \" \");\n if (v4) {\n v5 = v4;\n v6 = 0;\n do {\n if (a1 < strlen(v5)) {\n v7 = v6++;\n qword_4040[v7] = v5;\n }\n v5 = strtok(0LL, \" \");\n } while (v5);\n } else {\n v6 = 0;\n }\n *a3 = v6;\n return qword_4040;\n}", + "ida_pseudo_norm": "uint64_t *func0(int a1, char *a2, uint32_t *a3) {\n char *v4;\n char *v5;\n int v6;\n long long v7;\n v4 = strtok(a2, \" \");\n if (v4) {\n v5 = v4;\n v6 = 0;\n do {\n if (a1 < strlen(v5)) {\n v7 = v6++;\n word_len_1[v7] = v5;\n }\n v5 = strtok(0LL, \" \");\n } while (v5);\n } else {\n v6 = 0;\n }\n *a3 = v6;\n return word_len_1;\n}" + }, + { + "index": 128, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(int n, char* str, int* count) {\n static char* word_len[100];\n int index = 0;\n char* token = strtok(str, \" \");\n while (token != NULL) {\n if (strlen(token) > n) {\n word_len[index++] = token;\n }\n token = strtok(NULL, \" \");\n }\n *count = index;\n return word_len;\n}", + "test": "int main() {\n\n int count;\n\n char test_str1[] = \"python is a programming language\";\n\n char test_str2[] = \"writing a program\";\n\n char test_str3[] = \"sorting list\";\n\n \n\n char** result1 = func0(3, test_str1, &count);\n\n assert(count == 3 && strcmp(result1[0], \"python\") == 0 && strcmp(result1[1], \"programming\") == 0 && strcmp(result1[2], \"language\") == 0);\n\n \n\n char** result2 = func0(2, test_str2, &count);\n\n assert(count == 2 && strcmp(result2[0], \"writing\") == 0 && strcmp(result2[1], \"program\") == 0);\n\n \n\n char** result3 = func0(5, test_str3, &count);\n\n assert(count == 1 && strcmp(result3[0], \"sorting\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\nmov %rdx,%r12\npush %rbp\nmovslq %edi,%rbp\nmov %rsi,%rdi\nlea 0xc37(%rip),%rsi\npush %rbx\nsub $0x8,%rsp\ncallq 10b0 \ntest %rax,%rax\nje 1460 \nmov %rax,%rbx\nxor %r14d,%r14d\nlea 0x2c53(%rip),%r13\nnopl (%rax)\nmov %rbx,%rdi\ncallq 1080 \ncmp %rbp,%rax\njbe 142c \nlea 0xc00(%rip),%rsi\nxor %edi,%edi\nmov %rbx,0x0(%r13,%r14,8)\nlea 0x1(%r14),%r15d\ncallq 10b0 \nmov %rax,%rbx\ntest %rax,%rax\nje 1445 \nmov %rbx,%rdi\nmovslq %r15d,%r14\ncallq 1080 \ncmp %rbp,%rax\nja 13fd \nlea 0xbd1(%rip),%rsi\nxor %edi,%edi\ncallq 10b0 \nmov %rax,%rbx\ntest %rax,%rax\njne 13f0 \nmov %r14d,%r15d\nmov %r15d,(%r12)\nadd $0x8,%rsp\nlea 0x2bec(%rip),%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nxor %r15d,%r15d\njmp 1445 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\nlea r12, delim; \" \"\npush rbp\nmovsxd rbp, edi\nmov rdi, rsi; s\nmov rsi, r12; delim\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rdx\ncall _strtok\ntest rax, rax\njz short loc_1450\nmov r15, rax\nxor ebx, ebx\nlea r14, _word_len_1\nnop dword ptr [rax]\nloc_13E0:\nmov rdi, r15; s\ncall _strlen\ncmp rbp, rax\njnb short loc_1417\nloc_13ED:\nmov rsi, r12; delim\nxor edi, edi; s\nmov [r14+rbx*8], r15\nlea r13d, [rbx+1]\ncall _strtok\nmov r15, rax\ntest rax, rax\njz short loc_1448\nmov rdi, r15; s\nmovsxd rbx, r13d\ncall _strlen\ncmp rbp, rax\njb short loc_13ED\nloc_1417:\nmov rsi, r12; delim\nxor edi, edi; s\ncall _strtok\nmov r15, rax\ntest rax, rax\njnz short loc_13E0\nloc_1429:\nmov rax, [rsp+48h+var_40]\nmov [rax], ebx\nadd rsp, 18h\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1448:\nmov ebx, r13d\njmp short loc_1429\nloc_1450:\nxor ebx, ebx\nlea r14, _word_len_1\njmp short loc_1429", + "ida_pseudo": "_QWORD *__fastcall func0(int a1, char *a2, _DWORD *a3)\n{\n char *v3; // rax\n char *v4; // r15\n __int64 v5; // rbx\n char *v6; // rax\n\n v3 = strtok(a2, \" \");\n if ( v3 )\n {\n v4 = v3;\n v5 = 0LL;\n while ( a1 >= strlen(v4) )\n {\nLABEL_6:\n v4 = strtok(0LL, \" \");\n if ( !v4 )\n goto LABEL_7;\n }\n while ( 1 )\n {\n word_len_1[v5] = v4;\n v6 = strtok(0LL, \" \");\n v4 = v6;\n if ( !v6 )\n break;\n v5 = (int)v5 + 1;\n if ( a1 >= strlen(v6) )\n goto LABEL_6;\n }\n LODWORD(v5) = v5 + 1;\n }\n else\n {\n LODWORD(v5) = 0;\n }\nLABEL_7:\n *a3 = v5;\n return word_len_1;\n}", + "ida_strip_asm": "sub_13A0:\nendbr64\npush r15\npush r14\npush r13\npush r12\nlea r12, delim; \" \"\npush rbp\nmovsxd rbp, edi\nmov rdi, rsi; s\nmov rsi, r12; delim\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rdx\ncall _strtok\ntest rax, rax\njz short loc_1450\nmov r15, rax\nxor ebx, ebx\nlea r14, unk_4040\nnop dword ptr [rax]\nloc_13E0:\nmov rdi, r15; s\ncall _strlen\ncmp rbp, rax\njnb short loc_1417\nloc_13ED:\nmov rsi, r12; delim\nxor edi, edi; s\nmov [r14+rbx*8], r15\nlea r13d, [rbx+1]\ncall _strtok\nmov r15, rax\ntest rax, rax\njz short loc_1448\nmov rdi, r15; s\nmovsxd rbx, r13d\ncall _strlen\ncmp rbp, rax\njb short loc_13ED\nloc_1417:\nmov rsi, r12; delim\nxor edi, edi; s\ncall _strtok\nmov r15, rax\ntest rax, rax\njnz short loc_13E0\nloc_1429:\nmov rax, [rsp+48h+var_40]\nmov [rax], ebx\nadd rsp, 18h\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1448:\nmov ebx, r13d\njmp short loc_1429\nloc_1450:\nxor ebx, ebx\nlea r14, unk_4040\njmp short loc_1429", + "ida_strip_pseudo": "_QWORD *__fastcall sub_13A0(int a1, char *a2, _DWORD *a3)\n{\n char *v3; // rax\n char *v4; // r15\n __int64 v5; // rbx\n char *v6; // rax\n\n v3 = strtok(a2, \" \");\n if ( v3 )\n {\n v4 = v3;\n v5 = 0LL;\n while ( a1 >= strlen(v4) )\n {\nLABEL_6:\n v4 = strtok(0LL, \" \");\n if ( !v4 )\n goto LABEL_7;\n }\n while ( 1 )\n {\n qword_4040[v5] = v4;\n v6 = strtok(0LL, \" \");\n v4 = v6;\n if ( !v6 )\n break;\n v5 = (int)v5 + 1;\n if ( a1 >= strlen(v6) )\n goto LABEL_6;\n }\n LODWORD(v5) = v5 + 1;\n }\n else\n {\n LODWORD(v5) = 0;\n }\nLABEL_7:\n *a3 = v5;\n return qword_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_13A0(int a1, char *a2, uint32_t *a3) {\n char *v3;\n char *v4;\n long long v5;\n char *v6;\n v3 = strtok(a2, \" \");\n if (v3) {\n v4 = v3;\n v5 = 0LL;\n while (a1 >= strlen(v4)) {\n LABEL_6:\n v4 = strtok(0LL, \" \");\n if (!v4) goto LABEL_7;\n }\n while (1) {\n qword_4040[v5] = v4;\n v6 = strtok(0LL, \" \");\n v4 = v6;\n if (!v6) break;\n v5 = (int)v5 + 1;\n if (a1 >= strlen(v6)) goto LABEL_6;\n }\n LODWORD(v5) = v5 + 1;\n } else {\n LODWORD(v5) = 0;\n }\nLABEL_7:\n *a3 = v5;\n return qword_4040;\n}", + "ida_pseudo_norm": "uint64_t *func0(int a1, char *a2, uint32_t *a3) {\n char *v3;\n char *v4;\n long long v5;\n char *v6;\n v3 = strtok(a2, \" \");\n if (v3) {\n v4 = v3;\n v5 = 0LL;\n while (a1 >= strlen(v4)) {\n LABEL_6:\n v4 = strtok(0LL, \" \");\n if (!v4) goto LABEL_7;\n }\n while (1) {\n word_len_1[v5] = v4;\n v6 = strtok(0LL, \" \");\n v4 = v6;\n if (!v6) break;\n v5 = (int)v5 + 1;\n if (a1 >= strlen(v6)) goto LABEL_6;\n }\n LODWORD(v5) = v5 + 1;\n } else {\n LODWORD(v5) = 0;\n }\nLABEL_7:\n *a3 = v5;\n return word_len_1;\n}" + }, + { + "index": 129, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int size, int my_matrix[size][size]) {\n int sum_list[2 * size + 2];\n int index = 0;\n for (int i = 0; i < size; i++) {\n int sum = 0;\n for (int j = 0; j < size; j++) {\n sum += my_matrix[i][j];\n }\n sum_list[index++] = sum;\n }\n for (int j = 0; j < size; j++) {\n int sum = 0;\n for (int i = 0; i < size; i++) {\n sum += my_matrix[i][j];\n }\n sum_list[index++] = sum;\n }\n int result1 = 0;\n for (int i = 0; i < size; i++) {\n result1 += my_matrix[i][i];\n }\n sum_list[index++] = result1;\n int result2 = 0;\n for (int i = size - 1; i >= 0; i--) {\n result2 += my_matrix[i][i];\n }\n sum_list[index++] = result2;\n for (int k = 1; k < index; k++) {\n if (sum_list[k] != sum_list[0]) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n int matrix1[4][4] = {\n\n {7, 12, 1, 14},\n\n {2, 13, 8, 11},\n\n {16, 3, 10, 5},\n\n {9, 6, 15, 4}\n\n };\n\n int matrix2[3][3] = {\n\n {2, 7, 6},\n\n {9, 5, 1},\n\n {4, 3, 8}\n\n };\n\n int matrix3[3][3] = {\n\n {2, 7, 6},\n\n {9, 5, 1},\n\n {4, 3, 7}\n\n };\n\n\n\n assert(func0(4, matrix1) == true);\n\n assert(func0(3, matrix2) == true);\n\n assert(func0(3, matrix3) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r13\npush %r12\nsub $0x60,%rsp\nmov %edi,-0x64(%rbp)\nmov %rsi,-0x70(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmov -0x64(%rbp),%ecx\nmovslq %ecx,%rax\nsub $0x1,%rax\nmov %rax,-0x30(%rbp)\nmovslq %ecx,%rax\nmov %rax,%r12\nmov $0x0,%r13d\nmov %rsp,%rax\nmov %rax,%rdi\nmov -0x64(%rbp),%eax\nadd $0x1,%eax\nadd %eax,%eax\nmovslq %eax,%rdx\nsub $0x1,%rdx\nmov %rdx,-0x28(%rbp)\nmovslq %eax,%rdx\nmov %rdx,%r10\nmov $0x0,%r11d\nmovslq %eax,%rdx\nmov %rdx,%r8\nmov $0x0,%r9d\ncltq\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%esi\nmov $0x0,%edx\ndiv %rsi\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rsi\nsub %rdx,%rsi\nmov %rsi,%rdx\ncmp %rdx,%rsp\nje 122b \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 1214 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 1255 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x20(%rbp)\nmovl $0x0,-0x48(%rbp)\nmovl $0x0,-0x4c(%rbp)\njmp 12d4 \nmovl $0x0,-0x50(%rbp)\nmovl $0x0,-0x54(%rbp)\njmp 12b3 \nmov -0x4c(%rbp),%eax\nmovslq %eax,%rdx\nmovslq %ecx,%rax\nimul %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x70(%rbp),%rax\nadd %rax,%rdx\nmov -0x54(%rbp),%eax\ncltq\nmov (%rdx,%rax,4),%eax\nadd %eax,-0x50(%rbp)\naddl $0x1,-0x54(%rbp)\nmov -0x54(%rbp),%eax\ncmp -0x64(%rbp),%eax\njl 1288 \nmov -0x48(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x48(%rbp)\nmov -0x20(%rbp),%rdx\ncltq\nmov -0x50(%rbp),%esi\nmov %esi,(%rdx,%rax,4)\naddl $0x1,-0x4c(%rbp)\nmov -0x4c(%rbp),%eax\ncmp -0x64(%rbp),%eax\njl 1278 \nmovl $0x0,-0x58(%rbp)\njmp 1341 \nmovl $0x0,-0x5c(%rbp)\nmovl $0x0,-0x60(%rbp)\njmp 1320 \nmov -0x60(%rbp),%eax\nmovslq %eax,%rdx\nmovslq %ecx,%rax\nimul %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x70(%rbp),%rax\nadd %rax,%rdx\nmov -0x58(%rbp),%eax\ncltq\nmov (%rdx,%rax,4),%eax\nadd %eax,-0x5c(%rbp)\naddl $0x1,-0x60(%rbp)\nmov -0x60(%rbp),%eax\ncmp -0x64(%rbp),%eax\njl 12f5 \nmov -0x48(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x48(%rbp)\nmov -0x20(%rbp),%rdx\ncltq\nmov -0x5c(%rbp),%esi\nmov %esi,(%rdx,%rax,4)\naddl $0x1,-0x58(%rbp)\nmov -0x58(%rbp),%eax\ncmp -0x64(%rbp),%eax\njl 12e5 \nmovl $0x0,-0x44(%rbp)\nmovl $0x0,-0x40(%rbp)\njmp 1384 \nmov -0x40(%rbp),%eax\nmovslq %eax,%rdx\nmovslq %ecx,%rax\nimul %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x70(%rbp),%rax\nadd %rax,%rdx\nmov -0x40(%rbp),%eax\ncltq\nmov (%rdx,%rax,4),%eax\nadd %eax,-0x44(%rbp)\naddl $0x1,-0x40(%rbp)\nmov -0x40(%rbp),%eax\ncmp -0x64(%rbp),%eax\njl 1359 \nmov -0x48(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x48(%rbp)\nmov -0x20(%rbp),%rdx\ncltq\nmov -0x44(%rbp),%esi\nmov %esi,(%rdx,%rax,4)\nmovl $0x0,-0x3c(%rbp)\nmov -0x64(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0x38(%rbp)\njmp 13de \nmov -0x38(%rbp),%eax\nmovslq %eax,%rdx\nmovslq %ecx,%rax\nimul %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x70(%rbp),%rax\nadd %rax,%rdx\nmov -0x38(%rbp),%eax\ncltq\nmov (%rdx,%rax,4),%eax\nadd %eax,-0x3c(%rbp)\nsubl $0x1,-0x38(%rbp)\ncmpl $0x0,-0x38(%rbp)\njns 13b3 \nmov -0x48(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x48(%rbp)\nmov -0x20(%rbp),%rdx\ncltq\nmov -0x3c(%rbp),%ecx\nmov %ecx,(%rdx,%rax,4)\nmovl $0x1,-0x34(%rbp)\njmp 1424 \nmov -0x20(%rbp),%rax\nmov -0x34(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%edx\nmov -0x20(%rbp),%rax\nmov (%rax),%eax\ncmp %eax,%edx\nje 1420 \nmov $0x0,%eax\njmp 1431 \naddl $0x1,-0x34(%rbp)\nmov -0x34(%rbp),%eax\ncmp -0x48(%rbp),%eax\njl 1402 \nmov $0x1,%eax\nmov %rdi,%rsp\nmov -0x18(%rbp),%rdi\nxor %fs:0x28,%rdi\nje 1448 \ncallq 1060 <__stack_chk_fail@plt>\nlea -0x10(%rbp),%rsp\npop %r12\npop %r13\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 60h\nmov [rbp+var_54], edi\nmov [rbp+var_60], rsi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov ecx, [rbp+var_54]\nmovsxd rax, ecx\nsub rax, 1\nmov [rbp+var_20], rax\nmov rax, rsp\nmov rdi, rax\nmov eax, [rbp+var_54]\nadd eax, 1\nadd eax, eax\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov esi, 10h\nmov edx, 0\ndiv rsi\nimul rax, 10h\nmov rsi, rax\nand rsi, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rsi\nloc_11E9:\ncmp rsp, rdx\njz short loc_1200\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\njmp short loc_11E9\nloc_1200:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_122A\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_122A:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov [rbp+var_50], 0\nmov [rbp+var_4C], 0\njmp short loc_12A9\nloc_124D:\nmov [rbp+var_48], 0\nmov [rbp+var_44], 0\njmp short loc_1288\nloc_125D:\nmov eax, [rbp+var_4C]\nmovsxd rdx, eax\nmovsxd rax, ecx\nimul rax, rdx\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_60]\nadd rdx, rax\nmov eax, [rbp+var_44]\ncdqe\nmov eax, [rdx+rax*4]\nadd [rbp+var_48], eax\nadd [rbp+var_44], 1\nloc_1288:\nmov eax, [rbp+var_44]\ncmp eax, [rbp+var_54]\njl short loc_125D\nmov eax, [rbp+var_50]\nlea edx, [rax+1]\nmov [rbp+var_50], edx\nmov rdx, [rbp+var_10]\ncdqe\nmov esi, [rbp+var_48]\nmov [rdx+rax*4], esi\nadd [rbp+var_4C], 1\nloc_12A9:\nmov eax, [rbp+var_4C]\ncmp eax, [rbp+var_54]\njl short loc_124D\nmov [rbp+var_40], 0\njmp short loc_1316\nloc_12BA:\nmov [rbp+var_3C], 0\nmov [rbp+var_38], 0\njmp short loc_12F5\nloc_12CA:\nmov eax, [rbp+var_38]\nmovsxd rdx, eax\nmovsxd rax, ecx\nimul rax, rdx\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_60]\nadd rdx, rax\nmov eax, [rbp+var_40]\ncdqe\nmov eax, [rdx+rax*4]\nadd [rbp+var_3C], eax\nadd [rbp+var_38], 1\nloc_12F5:\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_54]\njl short loc_12CA\nmov eax, [rbp+var_50]\nlea edx, [rax+1]\nmov [rbp+var_50], edx\nmov rdx, [rbp+var_10]\ncdqe\nmov esi, [rbp+var_3C]\nmov [rdx+rax*4], esi\nadd [rbp+var_40], 1\nloc_1316:\nmov eax, [rbp+var_40]\ncmp eax, [rbp+var_54]\njl short loc_12BA\nmov [rbp+var_34], 0\nmov [rbp+var_30], 0\njmp short loc_1359\nloc_132E:\nmov eax, [rbp+var_30]\nmovsxd rdx, eax\nmovsxd rax, ecx\nimul rax, rdx\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_60]\nadd rdx, rax\nmov eax, [rbp+var_30]\ncdqe\nmov eax, [rdx+rax*4]\nadd [rbp+var_34], eax\nadd [rbp+var_30], 1\nloc_1359:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_54]\njl short loc_132E\nmov eax, [rbp+var_50]\nlea edx, [rax+1]\nmov [rbp+var_50], edx\nmov rdx, [rbp+var_10]\ncdqe\nmov esi, [rbp+var_34]\nmov [rdx+rax*4], esi\nmov [rbp+var_2C], 0\nmov eax, [rbp+var_54]\nsub eax, 1\nmov [rbp+var_28], eax\njmp short loc_13B3\nloc_1388:\nmov eax, [rbp+var_28]\nmovsxd rdx, eax\nmovsxd rax, ecx\nimul rax, rdx\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_60]\nadd rdx, rax\nmov eax, [rbp+var_28]\ncdqe\nmov eax, [rdx+rax*4]\nadd [rbp+var_2C], eax\nsub [rbp+var_28], 1\nloc_13B3:\ncmp [rbp+var_28], 0\njns short loc_1388\nmov eax, [rbp+var_50]\nlea edx, [rax+1]\nmov [rbp+var_50], edx\nmov rdx, [rbp+var_10]\ncdqe\nmov ecx, [rbp+var_2C]\nmov [rdx+rax*4], ecx\nmov [rbp+var_24], 1\njmp short loc_13F9\nloc_13D7:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov edx, [rax+rdx*4]\nmov rax, [rbp+var_10]\nmov eax, [rax]\ncmp edx, eax\njz short loc_13F5\nmov eax, 0\njmp short loc_1406\nloc_13F5:\nadd [rbp+var_24], 1\nloc_13F9:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_50]\njl short loc_13D7\nmov eax, 1\nloc_1406:\nmov rsp, rdi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_141D\ncall ___stack_chk_fail\nlocret_141D:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, __int64 a2)\n{\n int v2; // eax\n unsigned __int64 v3; // rax\n void *v4; // rsp\n int v5; // eax\n int v6; // eax\n int v7; // eax\n int v8; // eax\n __int64 v10; // [rsp+8h] [rbp-60h] BYREF\n int v11; // [rsp+14h] [rbp-54h]\n int v12; // [rsp+18h] [rbp-50h]\n int i; // [rsp+1Ch] [rbp-4Ch]\n int v14; // [rsp+20h] [rbp-48h]\n int j; // [rsp+24h] [rbp-44h]\n int k; // [rsp+28h] [rbp-40h]\n int v17; // [rsp+2Ch] [rbp-3Ch]\n int m; // [rsp+30h] [rbp-38h]\n int v19; // [rsp+34h] [rbp-34h]\n int n; // [rsp+38h] [rbp-30h]\n int v21; // [rsp+3Ch] [rbp-2Ch]\n int ii; // [rsp+40h] [rbp-28h]\n int jj; // [rsp+44h] [rbp-24h]\n __int64 v24; // [rsp+48h] [rbp-20h]\n __int64 v25; // [rsp+50h] [rbp-18h]\n __int64 *v26; // [rsp+58h] [rbp-10h]\n unsigned __int64 v27; // [rsp+60h] [rbp-8h]\n\n v11 = a1;\n v10 = a2;\n v27 = __readfsqword(0x28u);\n v24 = a1 - 1LL;\n v2 = 2 * (a1 + 1);\n v25 = v2 - 1LL;\n v3 = 16 * ((4LL * v2 + 15) / 0x10uLL);\n while ( &v10 != (__int64 *)((char *)&v10 - (v3 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v4 = alloca(v3 & 0xFFF);\n if ( (v3 & 0xFFF) != 0 )\n *(__int64 *)((char *)&v10 + (v3 & 0xFFF) - 8) = *(__int64 *)((char *)&v10 + (v3 & 0xFFF) - 8);\n v26 = &v10;\n v12 = 0;\n for ( i = 0; i < v11; ++i )\n {\n v14 = 0;\n for ( j = 0; j < v11; ++j )\n v14 += *(_DWORD *)(v10 + 4 * i * (__int64)a1 + 4LL * j);\n v5 = v12++;\n *((_DWORD *)v26 + v5) = v14;\n }\n for ( k = 0; k < v11; ++k )\n {\n v17 = 0;\n for ( m = 0; m < v11; ++m )\n v17 += *(_DWORD *)(v10 + 4 * m * (__int64)a1 + 4LL * k);\n v6 = v12++;\n *((_DWORD *)v26 + v6) = v17;\n }\n v19 = 0;\n for ( n = 0; n < v11; ++n )\n v19 += *(_DWORD *)(v10 + 4 * n * (__int64)a1 + 4LL * n);\n v7 = v12++;\n *((_DWORD *)v26 + v7) = v19;\n v21 = 0;\n for ( ii = v11 - 1; ii >= 0; --ii )\n v21 += *(_DWORD *)(v10 + 4 * ii * (__int64)a1 + 4LL * ii);\n v8 = v12++;\n *((_DWORD *)v26 + v8) = v21;\n for ( jj = 1; jj < v12; ++jj )\n {\n if ( *((_DWORD *)v26 + jj) != *(_DWORD *)v26 )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 60h\nmov [rbp+var_54], edi\nmov [rbp+var_60], rsi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov ecx, [rbp+var_54]\nmovsxd rax, ecx\nsub rax, 1\nmov [rbp+var_20], rax\nmov rax, rsp\nmov rdi, rax\nmov eax, [rbp+var_54]\nadd eax, 1\nadd eax, eax\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov esi, 10h\nmov edx, 0\ndiv rsi\nimul rax, 10h\nmov rsi, rax\nand rsi, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rsi\nloc_11E9:\ncmp rsp, rdx\njz short loc_1200\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\njmp short loc_11E9\nloc_1200:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_122A\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_122A:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov [rbp+var_50], 0\nmov [rbp+var_4C], 0\njmp short loc_12A9\nloc_124D:\nmov [rbp+var_48], 0\nmov [rbp+var_44], 0\njmp short loc_1288\nloc_125D:\nmov eax, [rbp+var_4C]\nmovsxd rdx, eax\nmovsxd rax, ecx\nimul rax, rdx\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_60]\nadd rdx, rax\nmov eax, [rbp+var_44]\ncdqe\nmov eax, [rdx+rax*4]\nadd [rbp+var_48], eax\nadd [rbp+var_44], 1\nloc_1288:\nmov eax, [rbp+var_44]\ncmp eax, [rbp+var_54]\njl short loc_125D\nmov eax, [rbp+var_50]\nlea edx, [rax+1]\nmov [rbp+var_50], edx\nmov rdx, [rbp+var_10]\ncdqe\nmov esi, [rbp+var_48]\nmov [rdx+rax*4], esi\nadd [rbp+var_4C], 1\nloc_12A9:\nmov eax, [rbp+var_4C]\ncmp eax, [rbp+var_54]\njl short loc_124D\nmov [rbp+var_40], 0\njmp short loc_1316\nloc_12BA:\nmov [rbp+var_3C], 0\nmov [rbp+var_38], 0\njmp short loc_12F5\nloc_12CA:\nmov eax, [rbp+var_38]\nmovsxd rdx, eax\nmovsxd rax, ecx\nimul rax, rdx\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_60]\nadd rdx, rax\nmov eax, [rbp+var_40]\ncdqe\nmov eax, [rdx+rax*4]\nadd [rbp+var_3C], eax\nadd [rbp+var_38], 1\nloc_12F5:\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_54]\njl short loc_12CA\nmov eax, [rbp+var_50]\nlea edx, [rax+1]\nmov [rbp+var_50], edx\nmov rdx, [rbp+var_10]\ncdqe\nmov esi, [rbp+var_3C]\nmov [rdx+rax*4], esi\nadd [rbp+var_40], 1\nloc_1316:\nmov eax, [rbp+var_40]\ncmp eax, [rbp+var_54]\njl short loc_12BA\nmov [rbp+var_34], 0\nmov [rbp+var_30], 0\njmp short loc_1359\nloc_132E:\nmov eax, [rbp+var_30]\nmovsxd rdx, eax\nmovsxd rax, ecx\nimul rax, rdx\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_60]\nadd rdx, rax\nmov eax, [rbp+var_30]\ncdqe\nmov eax, [rdx+rax*4]\nadd [rbp+var_34], eax\nadd [rbp+var_30], 1\nloc_1359:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_54]\njl short loc_132E\nmov eax, [rbp+var_50]\nlea edx, [rax+1]\nmov [rbp+var_50], edx\nmov rdx, [rbp+var_10]\ncdqe\nmov esi, [rbp+var_34]\nmov [rdx+rax*4], esi\nmov [rbp+var_2C], 0\nmov eax, [rbp+var_54]\nsub eax, 1\nmov [rbp+var_28], eax\njmp short loc_13B3\nloc_1388:\nmov eax, [rbp+var_28]\nmovsxd rdx, eax\nmovsxd rax, ecx\nimul rax, rdx\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_60]\nadd rdx, rax\nmov eax, [rbp+var_28]\ncdqe\nmov eax, [rdx+rax*4]\nadd [rbp+var_2C], eax\nsub [rbp+var_28], 1\nloc_13B3:\ncmp [rbp+var_28], 0\njns short loc_1388\nmov eax, [rbp+var_50]\nlea edx, [rax+1]\nmov [rbp+var_50], edx\nmov rdx, [rbp+var_10]\ncdqe\nmov ecx, [rbp+var_2C]\nmov [rdx+rax*4], ecx\nmov [rbp+var_24], 1\njmp short loc_13F9\nloc_13D7:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov edx, [rax+rdx*4]\nmov rax, [rbp+var_10]\nmov eax, [rax]\ncmp edx, eax\njz short loc_13F5\nmov eax, 0\njmp short loc_1406\nloc_13F5:\nadd [rbp+var_24], 1\nloc_13F9:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_50]\njl short loc_13D7\nmov eax, 1\nloc_1406:\nmov rsp, rdi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_141D\ncall ___stack_chk_fail\nlocret_141D:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1, __int64 a2)\n{\n int v2; // eax\n unsigned __int64 v3; // rax\n void *v4; // rsp\n int v5; // eax\n int v6; // eax\n int v7; // eax\n int v8; // eax\n __int64 v10; // [rsp+8h] [rbp-60h] BYREF\n int v11; // [rsp+14h] [rbp-54h]\n int v12; // [rsp+18h] [rbp-50h]\n int i; // [rsp+1Ch] [rbp-4Ch]\n int v14; // [rsp+20h] [rbp-48h]\n int j; // [rsp+24h] [rbp-44h]\n int k; // [rsp+28h] [rbp-40h]\n int v17; // [rsp+2Ch] [rbp-3Ch]\n int m; // [rsp+30h] [rbp-38h]\n int v19; // [rsp+34h] [rbp-34h]\n int n; // [rsp+38h] [rbp-30h]\n int v21; // [rsp+3Ch] [rbp-2Ch]\n int ii; // [rsp+40h] [rbp-28h]\n int jj; // [rsp+44h] [rbp-24h]\n __int64 v24; // [rsp+48h] [rbp-20h]\n __int64 v25; // [rsp+50h] [rbp-18h]\n __int64 *v26; // [rsp+58h] [rbp-10h]\n unsigned __int64 v27; // [rsp+60h] [rbp-8h]\n\n v11 = a1;\n v10 = a2;\n v27 = __readfsqword(0x28u);\n v24 = a1 - 1LL;\n v2 = 2 * (a1 + 1);\n v25 = v2 - 1LL;\n v3 = 16 * ((4LL * v2 + 15) / 0x10uLL);\n while ( &v10 != (__int64 *)((char *)&v10 - (v3 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v4 = alloca(v3 & 0xFFF);\n if ( (v3 & 0xFFF) != 0 )\n *(__int64 *)((char *)&v10 + (v3 & 0xFFF) - 8) = *(__int64 *)((char *)&v10 + (v3 & 0xFFF) - 8);\n v26 = &v10;\n v12 = 0;\n for ( i = 0; i < v11; ++i )\n {\n v14 = 0;\n for ( j = 0; j < v11; ++j )\n v14 += *(_DWORD *)(v10 + 4 * i * (__int64)a1 + 4LL * j);\n v5 = v12++;\n *((_DWORD *)v26 + v5) = v14;\n }\n for ( k = 0; k < v11; ++k )\n {\n v17 = 0;\n for ( m = 0; m < v11; ++m )\n v17 += *(_DWORD *)(v10 + 4 * m * (__int64)a1 + 4LL * k);\n v6 = v12++;\n *((_DWORD *)v26 + v6) = v17;\n }\n v19 = 0;\n for ( n = 0; n < v11; ++n )\n v19 += *(_DWORD *)(v10 + 4 * n * (__int64)a1 + 4LL * n);\n v7 = v12++;\n *((_DWORD *)v26 + v7) = v19;\n v21 = 0;\n for ( ii = v11 - 1; ii >= 0; --ii )\n v21 += *(_DWORD *)(v10 + 4 * ii * (__int64)a1 + 4LL * ii);\n v8 = v12++;\n *((_DWORD *)v26 + v8) = v21;\n for ( jj = 1; jj < v12; ++jj )\n {\n if ( *((_DWORD *)v26 + jj) != *(_DWORD *)v26 )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1, long long a2) {\n int v2;\n unsigned long long v3;\n void *v4;\n int v5;\n int v6;\n int v7;\n int v8;\n long long v10;\n int v11;\n int v12;\n int i;\n int v14;\n int j;\n int k;\n int v17;\n int m;\n int v19;\n int n;\n int v21;\n int ii;\n int jj;\n long long v24;\n long long v25;\n long long *v26;\n unsigned long long v27;\n v11 = a1;\n v10 = a2;\n v27 = __readfsqword(40u);\n v24 = a1 - 1LL;\n v2 = 2 * (a1 + 1);\n v25 = v2 - 1LL;\n v3 = 16 * ((4LL * v2 + 15) / 16uLL);\n while (&v10 != (long long *)((char *)&v10 - (v3 & 18446744073709547520LL)))\n ;\n v4 = alloca(v3 & 4095);\n if ((v3 & 4095) != 0)\n *(long long *)((char *)&v10 + (v3 & 4095) - 8) =\n *(long long *)((char *)&v10 + (v3 & 4095) - 8);\n v26 = &v10;\n v12 = 0;\n for (i = 0; i < v11; ++i) {\n v14 = 0;\n for (j = 0; j < v11; ++j)\n v14 += *(uint32_t *)(v10 + 4 * i * (long long)a1 + 4LL * j);\n v5 = v12++;\n *((uint32_t *)v26 + v5) = v14;\n }\n for (k = 0; k < v11; ++k) {\n v17 = 0;\n for (m = 0; m < v11; ++m)\n v17 += *(uint32_t *)(v10 + 4 * m * (long long)a1 + 4LL * k);\n v6 = v12++;\n *((uint32_t *)v26 + v6) = v17;\n }\n v19 = 0;\n for (n = 0; n < v11; ++n)\n v19 += *(uint32_t *)(v10 + 4 * n * (long long)a1 + 4LL * n);\n v7 = v12++;\n *((uint32_t *)v26 + v7) = v19;\n v21 = 0;\n for (ii = v11 - 1; ii >= 0; --ii)\n v21 += *(uint32_t *)(v10 + 4 * ii * (long long)a1 + 4LL * ii);\n v8 = v12++;\n *((uint32_t *)v26 + v8) = v21;\n for (jj = 1; jj < v12; ++jj) {\n if (*((uint32_t *)v26 + jj) != *(uint32_t *)v26) return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(int a1, long long a2) {\n int v2;\n unsigned long long v3;\n void *v4;\n int v5;\n int v6;\n int v7;\n int v8;\n long long v10;\n int v11;\n int v12;\n int i;\n int v14;\n int j;\n int k;\n int v17;\n int m;\n int v19;\n int n;\n int v21;\n int ii;\n int jj;\n long long v24;\n long long v25;\n long long *v26;\n unsigned long long v27;\n v11 = a1;\n v10 = a2;\n v27 = __readfsqword(40u);\n v24 = a1 - 1LL;\n v2 = 2 * (a1 + 1);\n v25 = v2 - 1LL;\n v3 = 16 * ((4LL * v2 + 15) / 16uLL);\n while (&v10 != (long long *)((char *)&v10 - (v3 & 18446744073709547520LL)))\n ;\n v4 = alloca(v3 & 4095);\n if ((v3 & 4095) != 0)\n *(long long *)((char *)&v10 + (v3 & 4095) - 8) =\n *(long long *)((char *)&v10 + (v3 & 4095) - 8);\n v26 = &v10;\n v12 = 0;\n for (i = 0; i < v11; ++i) {\n v14 = 0;\n for (j = 0; j < v11; ++j)\n v14 += *(uint32_t *)(v10 + 4 * i * (long long)a1 + 4LL * j);\n v5 = v12++;\n *((uint32_t *)v26 + v5) = v14;\n }\n for (k = 0; k < v11; ++k) {\n v17 = 0;\n for (m = 0; m < v11; ++m)\n v17 += *(uint32_t *)(v10 + 4 * m * (long long)a1 + 4LL * k);\n v6 = v12++;\n *((uint32_t *)v26 + v6) = v17;\n }\n v19 = 0;\n for (n = 0; n < v11; ++n)\n v19 += *(uint32_t *)(v10 + 4 * n * (long long)a1 + 4LL * n);\n v7 = v12++;\n *((uint32_t *)v26 + v7) = v19;\n v21 = 0;\n for (ii = v11 - 1; ii >= 0; --ii)\n v21 += *(uint32_t *)(v10 + 4 * ii * (long long)a1 + 4LL * ii);\n v8 = v12++;\n *((uint32_t *)v26 + v8) = v21;\n for (jj = 1; jj < v12; ++jj) {\n if (*((uint32_t *)v26 + jj) != *(uint32_t *)v26) return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": 129, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int size, int my_matrix[size][size]) {\n int sum_list[2 * size + 2];\n int index = 0;\n for (int i = 0; i < size; i++) {\n int sum = 0;\n for (int j = 0; j < size; j++) {\n sum += my_matrix[i][j];\n }\n sum_list[index++] = sum;\n }\n for (int j = 0; j < size; j++) {\n int sum = 0;\n for (int i = 0; i < size; i++) {\n sum += my_matrix[i][j];\n }\n sum_list[index++] = sum;\n }\n int result1 = 0;\n for (int i = 0; i < size; i++) {\n result1 += my_matrix[i][i];\n }\n sum_list[index++] = result1;\n int result2 = 0;\n for (int i = size - 1; i >= 0; i--) {\n result2 += my_matrix[i][i];\n }\n sum_list[index++] = result2;\n for (int k = 1; k < index; k++) {\n if (sum_list[k] != sum_list[0]) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n int matrix1[4][4] = {\n\n {7, 12, 1, 14},\n\n {2, 13, 8, 11},\n\n {16, 3, 10, 5},\n\n {9, 6, 15, 4}\n\n };\n\n int matrix2[3][3] = {\n\n {2, 7, 6},\n\n {9, 5, 1},\n\n {4, 3, 8}\n\n };\n\n int matrix3[3][3] = {\n\n {2, 7, 6},\n\n {9, 5, 1},\n\n {4, 3, 7}\n\n };\n\n\n\n assert(func0(4, matrix1) == true);\n\n assert(func0(3, matrix2) == true);\n\n assert(func0(3, matrix3) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0x28,%rsp\nmov %rsi,%r12\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nmovslq %edi,%r11\nlea 0x2(%rdi,%rdi,1),%eax\ncltq\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffffff0,%rdx\nand $0xfffffffffffff000,%rax\nmov %rsp,%rbx\nsub %rax,%rbx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 11ce \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11b7 \nmov %rdx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 11e4 \norq $0x0,-0x8(%rsp,%rax,1)\nlea 0x3(%rsp),%rbx\nmov %rbx,%rax\nshr $0x2,%rax\nmov %rax,-0x48(%rbp)\nand $0xfffffffffffffffc,%rbx\ntest %edi,%edi\njle 1347 \nmov %rbx,%r8\nlea 0x0(,%r11,4),%r9\nlea -0x1(%rdi),%r13d\nlea 0x0(,%r13,4),%rax\nmov %r12,%r10\nlea 0x4(%r12,%rax,1),%rsi\nlea 0x4(%rbx,%rax,1),%r15\nmov %rsi,%rcx\nnot %r13\nshl $0x2,%r13\nmov $0x0,%r14d\njmp 1245 \nmov %edx,(%r8)\nadd $0x4,%r8\nadd %r9,%rcx\ncmp %r15,%r8\nje 125a \nlea 0x0(%r13,%rcx,1),%rax\nmov %r14d,%edx\nadd (%rax),%edx\nadd $0x4,%rax\ncmp %rcx,%rax\njne 124d \njmp 1236 \nlea (%rbx,%r9,1),%r14\nmov %r12,%r13\nmov $0x0,%r15d\njmp 1279 \nmov %ecx,(%r14)\nadd $0x4,%r14\nadd $0x4,%r13\ncmp %rsi,%r13\nje 1295 \nmov %r13,%rdx\nmov %r15d,%ecx\nmov $0x0,%eax\nadd (%rdx),%ecx\nmov %eax,%r8d\nadd $0x1,%eax\nadd %r9,%rdx\ncmp %eax,%edi\njne 1284 \njmp 1269 \nadd %eax,%eax\nmov %eax,%ecx\nadd $0x4,%r9\nmov $0x0,%edx\nmov $0x0,%esi\nadd (%r10),%esi\nmov %edx,%edi\nadd $0x1,%edx\nadd %r9,%r10\ncmp %edi,%r8d\njne 12a7 \nlea 0x1(%rax),%edi\ncltq\nmov %esi,(%rbx,%rax,4)\nlea 0x1(%r11),%rdx\nnot %r11\nlea 0x0(,%r11,4),%rsi\nmovslq %r8d,%rax\nimul %rdx,%rax\nlea (%r12,%rax,4),%rax\nmov $0x0,%edx\nadd (%rax),%edx\nadd %rsi,%rax\nsub $0x1,%r8d\njns 12de \nmovslq %edi,%rdi\nmov %edx,(%rbx,%rdi,4)\ntest %ecx,%ecx\njs 131d \nmov -0x48(%rbp),%rax\nmov 0x0(,%rax,4),%edx\nlea 0x4(%rbx),%rax\nmov %ecx,%ecx\nlea 0x8(%rbx,%rcx,4),%rcx\ncmp %edx,(%rax)\njne 1324 \nadd $0x4,%rax\ncmp %rcx,%rax\njne 1309 \nmov $0x1,%eax\njmp 1329 \nmov $0x1,%eax\njmp 1329 \nmov $0x0,%eax\nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\njne 1367 \nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\nmov -0x48(%rbp),%rax\nmovl $0x0,0x0(,%rax,4)\nmov $0x0,%ecx\nmov $0x1,%edi\nmov $0x0,%edx\njmp 12e9 \ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 38h\nmov r9d, edi\nmov [rbp+var_48], rsi\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nmovsxd r14, edi\nlea eax, [rdi+rdi+2]\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11B8:\ncmp rsp, rdx\njz short loc_11CF\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\njmp short loc_11B8\nloc_11CF:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11E5\nor [rsp+rax+60h+var_68], 0\nloc_11E5:\nlea r13, [rsp+60h+var_5D]\nmov rax, r13\nshr rax, 2\nmov [rbp+var_58], rax\nand r13, 0FFFFFFFFFFFFFFFCh\ntest r9d, r9d\njle loc_1369\nmov r11, r13\nlea r8, ds:0[r14*4]\nmov rax, [rbp+var_48]\nmov rdx, rax\nlea rbx, [r8+rax]\nlea r15, [r13+r8+0]\nmov rsi, r14\nneg rsi\nshl rsi, 2\nmov r10, rbx\nmov r12d, 0\nloc_1230:\nlea rax, [r10+rsi]\nmov ecx, r12d\nloc_1237:\nmov edi, ecx\nadd edi, [rax]\nmov ecx, edi\nadd rax, 4\ncmp rax, r10\njnz short loc_1237\nmov [r11], edi\nadd r11, 4\nadd r10, r8\ncmp r11, r15\njnz short loc_1230\nlea r11, [r13+r8+0]\nmov r10, [rbp+var_48]\nmov r12d, 0\nmov [rbp+var_50], r14\nloc_1268:\nmov rcx, r10\nmov eax, 0\nmov r14d, r12d\nloc_1273:\nmov r15d, r14d\nadd r15d, [rcx]\nmov r14d, r15d\nmov edi, eax\nadd eax, 1\nadd rcx, r8\ncmp r9d, eax\njnz short loc_1273\nmov [r11], r15d\nadd r11, 4\nadd r10, 4\ncmp r10, rbx\njnz short loc_1268\nmov r14, [rbp+var_50]\nlea r11d, [rax+rax]\nmov ebx, r11d\nadd r8, 4\nmov ecx, 0\nmov r10d, 0\nloc_12B3:\nmov r9d, r10d\nadd r9d, [rdx]\nmov r10d, r9d\nmov r12d, ecx\nadd ecx, 1\nadd rdx, r8\ncmp edi, r12d\njnz short loc_12B3\nlea ecx, [r11+1]\nmovsxd rdx, r11d\nmov [r13+rdx*4+0], r9d\nsub rsi, 4\nmovsxd rdx, edi\nimul rdx, r14\ncdqe\nadd rax, rdx\nmov rdx, [rbp+var_48]\nlea rax, [rdx+rax*4-4]\nmov r8d, 0\nloc_12F5:\nmov edx, r8d\nadd edx, [rax]\nmov r8d, edx\nsub edi, 1\nadd rax, rsi\ncmp edi, 0FFFFFFFFh\njnz short loc_12F5\nmovsxd rcx, ecx\nmov [r13+rcx*4+0], edx\ntest r11d, r11d\njs short loc_133F\nloc_1315:\nmov rax, [rbp+var_58]\nmov edx, ds:dword_0[rax*4]\nlea rax, [r13+4]\nmov ebx, ebx\nlea rcx, [r13+rbx*4+8]\nloc_132B:\ncmp [rax], edx\njnz short loc_1346\nadd rax, 4\ncmp rcx, rax\njnz short loc_132B\nmov eax, 1\njmp short loc_134B\nloc_133F:\nmov eax, 1\njmp short loc_134B\nloc_1346:\nmov eax, 0\nloc_134B:\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_138A\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1369:\nmov rax, [rbp+var_58]\nmov ds:dword_0[rax*4], 0\nmov dword ptr ds:byte_4[rax*4], 0\nmov ebx, 0\njmp short loc_1315\nloc_138A:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1, _DWORD *a2)\n{\n __int64 v3; // r14\n signed __int64 v4; // rax\n void *v5; // rsp\n _BYTE *v6; // r11\n __int64 v7; // r8\n _DWORD *v8; // rdx\n _DWORD *v9; // rbx\n __int64 v10; // rsi\n _DWORD *v11; // r10\n _DWORD *v12; // rax\n int v13; // ecx\n int v14; // edi\n _DWORD *v15; // r11\n _DWORD *v16; // r10\n _DWORD *v17; // rcx\n int v18; // eax\n int v19; // r14d\n int v20; // r15d\n int v21; // edi\n __int64 v22; // r14\n int v23; // r11d\n unsigned int v24; // ebx\n __int64 v25; // r8\n int v26; // ecx\n int v27; // r10d\n int v28; // r9d\n int v29; // r12d\n __int64 v30; // rsi\n _DWORD *v31; // rax\n int v32; // r8d\n int v33; // edx\n int *v34; // rax\n unsigned __int64 v36; // rax\n _BYTE v38[3]; // [rsp+8h] [rbp-60h] BYREF\n char v39; // [rsp+Bh] [rbp-5Dh] BYREF\n int v40; // [rsp+Ch] [rbp-5Ch] BYREF\n unsigned __int64 v41; // [rsp+10h] [rbp-58h] BYREF\n __int64 v42; // [rsp+18h] [rbp-50h]\n _DWORD *v43; // [rsp+20h] [rbp-48h]\n unsigned __int64 v44; // [rsp+30h] [rbp-38h]\n\n v43 = a2;\n v44 = __readfsqword(0x28u);\n v3 = a1;\n while ( v38 != &v38[-((4LL * (2 * a1 + 2) + 15) & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v4 = (4 * (2 * (_WORD)a1 + 2) + 15) & 0xFF0;\n v5 = alloca(v4);\n if ( ((4 * (2 * (_WORD)a1 + 2) + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v38[v4 - 8] = *(_QWORD *)&v38[v4 - 8];\n v41 = (unsigned __int64)&v39 >> 2;\n if ( a1 <= 0 )\n {\n v36 = v41;\n *(_DWORD *)(4 * v41) = 0;\n *(_DWORD *)&byte_4[4 * v36] = 0;\n v24 = 0;\n }\n else\n {\n v6 = v38;\n v7 = 4LL * a1;\n v8 = v43;\n v9 = &v43[(unsigned __int64)v7 / 4];\n v10 = -4LL * a1;\n v11 = &v43[(unsigned __int64)v7 / 4];\n do\n {\n v12 = &v11[-v3];\n v13 = 0;\n do\n {\n v14 = *v12 + v13;\n v13 = v14;\n ++v12;\n }\n while ( v12 != v11 );\n *(_DWORD *)v6 = v14;\n v6 += 4;\n v11 = (_DWORD *)((char *)v11 + v7);\n }\n while ( v6 != &v38[v7] );\n v15 = &v38[v7];\n v16 = v43;\n v42 = v3;\n do\n {\n v17 = v16;\n v18 = 0;\n v19 = 0;\n do\n {\n v20 = *v17 + v19;\n v19 = v20;\n v21 = v18++;\n v17 = (_DWORD *)((char *)v17 + v7);\n }\n while ( a1 != v18 );\n *v15++ = v20;\n ++v16;\n }\n while ( v16 != v9 );\n v22 = v42;\n v23 = 2 * v18;\n v24 = 2 * v18;\n v25 = v7 + 4;\n v26 = 0;\n v27 = 0;\n do\n {\n v28 = *v8 + v27;\n v27 = v28;\n v29 = v26++;\n v8 = (_DWORD *)((char *)v8 + v25);\n }\n while ( v21 != v29 );\n *(_DWORD *)&v38[4 * v23] = v28;\n v30 = v10 - 4;\n v31 = &v43[v22 * v21 - 1 + v18];\n v32 = 0;\n do\n {\n v33 = *v31 + v32;\n v32 = v33;\n --v21;\n v31 = (_DWORD *)((char *)v31 + v30);\n }\n while ( v21 != -1 );\n *(_DWORD *)&v38[4 * v23 + 4] = v33;\n if ( v23 < 0 )\n return 1LL;\n }\n v34 = &v40;\n while ( *v34 == *(_DWORD *)(4 * v41) )\n {\n if ( (int *)((char *)&v41 + 4 * v24) == ++v34 )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 38h\nmov r9d, edi\nmov [rbp+var_48], rsi\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nmovsxd r14, edi\nlea eax, [rdi+rdi+2]\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11B8:\ncmp rsp, rdx\njz short loc_11CF\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\njmp short loc_11B8\nloc_11CF:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11E5\nor [rsp+rax+60h+var_68], 0\nloc_11E5:\nlea r13, [rsp+60h+var_5D]\nmov rax, r13\nshr rax, 2\nmov [rbp+var_58], rax\nand r13, 0FFFFFFFFFFFFFFFCh\ntest r9d, r9d\njle loc_1369\nmov r11, r13\nlea r8, ds:0[r14*4]\nmov rax, [rbp+var_48]\nmov rdx, rax\nlea rbx, [r8+rax]\nlea r15, [r13+r8+0]\nmov rsi, r14\nneg rsi\nshl rsi, 2\nmov r10, rbx\nmov r12d, 0\nloc_1230:\nlea rax, [r10+rsi]\nmov ecx, r12d\nloc_1237:\nmov edi, ecx\nadd edi, [rax]\nmov ecx, edi\nadd rax, 4\ncmp rax, r10\njnz short loc_1237\nmov [r11], edi\nadd r11, 4\nadd r10, r8\ncmp r11, r15\njnz short loc_1230\nlea r11, [r13+r8+0]\nmov r10, [rbp+var_48]\nmov r12d, 0\nmov [rbp+var_50], r14\nloc_1268:\nmov rcx, r10\nmov eax, 0\nmov r14d, r12d\nloc_1273:\nmov r15d, r14d\nadd r15d, [rcx]\nmov r14d, r15d\nmov edi, eax\nadd eax, 1\nadd rcx, r8\ncmp r9d, eax\njnz short loc_1273\nmov [r11], r15d\nadd r11, 4\nadd r10, 4\ncmp r10, rbx\njnz short loc_1268\nmov r14, [rbp+var_50]\nlea r11d, [rax+rax]\nmov ebx, r11d\nadd r8, 4\nmov ecx, 0\nmov r10d, 0\nloc_12B3:\nmov r9d, r10d\nadd r9d, [rdx]\nmov r10d, r9d\nmov r12d, ecx\nadd ecx, 1\nadd rdx, r8\ncmp edi, r12d\njnz short loc_12B3\nlea ecx, [r11+1]\nmovsxd rdx, r11d\nmov [r13+rdx*4+0], r9d\nsub rsi, 4\nmovsxd rdx, edi\nimul rdx, r14\ncdqe\nadd rax, rdx\nmov rdx, [rbp+var_48]\nlea rax, [rdx+rax*4-4]\nmov r8d, 0\nloc_12F5:\nmov edx, r8d\nadd edx, [rax]\nmov r8d, edx\nsub edi, 1\nadd rax, rsi\ncmp edi, 0FFFFFFFFh\njnz short loc_12F5\nmovsxd rcx, ecx\nmov [r13+rcx*4+0], edx\ntest r11d, r11d\njs short loc_133F\nloc_1315:\nmov rax, [rbp+var_58]\nmov edx, ds:dword_0[rax*4]\nlea rax, [r13+4]\nmov ebx, ebx\nlea rcx, [r13+rbx*4+8]\nloc_132B:\ncmp [rax], edx\njnz short loc_1346\nadd rax, 4\ncmp rcx, rax\njnz short loc_132B\nmov eax, 1\njmp short loc_134B\nloc_133F:\nmov eax, 1\njmp short loc_134B\nloc_1346:\nmov eax, 0\nloc_134B:\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_138A\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1369:\nmov rax, [rbp+var_58]\nmov ds:dword_0[rax*4], 0\nmov dword ptr ds:byte_4[rax*4], 0\nmov ebx, 0\njmp short loc_1315\nloc_138A:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1, _DWORD *a2)\n{\n __int64 v3; // r14\n signed __int64 v4; // rax\n void *v5; // rsp\n _BYTE *v6; // r11\n __int64 v7; // r8\n _DWORD *v8; // rdx\n _DWORD *v9; // rbx\n __int64 v10; // rsi\n _DWORD *v11; // r10\n _DWORD *v12; // rax\n int v13; // ecx\n int v14; // edi\n _DWORD *v15; // r11\n _DWORD *v16; // r10\n _DWORD *v17; // rcx\n int v18; // eax\n int v19; // r14d\n int v20; // r15d\n int v21; // edi\n __int64 v22; // r14\n int v23; // r11d\n unsigned int v24; // ebx\n __int64 v25; // r8\n int v26; // ecx\n int v27; // r10d\n int v28; // r9d\n int v29; // r12d\n __int64 v30; // rsi\n _DWORD *v31; // rax\n int v32; // r8d\n int v33; // edx\n int *v34; // rax\n unsigned __int64 v36; // rax\n _BYTE v38[3]; // [rsp+8h] [rbp-60h] BYREF\n char v39; // [rsp+Bh] [rbp-5Dh] BYREF\n int v40; // [rsp+Ch] [rbp-5Ch] BYREF\n unsigned __int64 v41; // [rsp+10h] [rbp-58h] BYREF\n __int64 v42; // [rsp+18h] [rbp-50h]\n _DWORD *v43; // [rsp+20h] [rbp-48h]\n unsigned __int64 v44; // [rsp+30h] [rbp-38h]\n\n v43 = a2;\n v44 = __readfsqword(0x28u);\n v3 = a1;\n while ( v38 != &v38[-((4LL * (2 * a1 + 2) + 15) & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v4 = (4 * (2 * (_WORD)a1 + 2) + 15) & 0xFF0;\n v5 = alloca(v4);\n if ( ((4 * (2 * (_WORD)a1 + 2) + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v38[v4 - 8] = *(_QWORD *)&v38[v4 - 8];\n v41 = (unsigned __int64)&v39 >> 2;\n if ( a1 <= 0 )\n {\n v36 = v41;\n *(_DWORD *)(4 * v41) = 0;\n *(_DWORD *)&byte_4[4 * v36] = 0;\n v24 = 0;\n }\n else\n {\n v6 = v38;\n v7 = 4LL * a1;\n v8 = v43;\n v9 = &v43[(unsigned __int64)v7 / 4];\n v10 = -4LL * a1;\n v11 = &v43[(unsigned __int64)v7 / 4];\n do\n {\n v12 = &v11[-v3];\n v13 = 0;\n do\n {\n v14 = *v12 + v13;\n v13 = v14;\n ++v12;\n }\n while ( v12 != v11 );\n *(_DWORD *)v6 = v14;\n v6 += 4;\n v11 = (_DWORD *)((char *)v11 + v7);\n }\n while ( v6 != &v38[v7] );\n v15 = &v38[v7];\n v16 = v43;\n v42 = v3;\n do\n {\n v17 = v16;\n v18 = 0;\n v19 = 0;\n do\n {\n v20 = *v17 + v19;\n v19 = v20;\n v21 = v18++;\n v17 = (_DWORD *)((char *)v17 + v7);\n }\n while ( a1 != v18 );\n *v15++ = v20;\n ++v16;\n }\n while ( v16 != v9 );\n v22 = v42;\n v23 = 2 * v18;\n v24 = 2 * v18;\n v25 = v7 + 4;\n v26 = 0;\n v27 = 0;\n do\n {\n v28 = *v8 + v27;\n v27 = v28;\n v29 = v26++;\n v8 = (_DWORD *)((char *)v8 + v25);\n }\n while ( v21 != v29 );\n *(_DWORD *)&v38[4 * v23] = v28;\n v30 = v10 - 4;\n v31 = &v43[v22 * v21 - 1 + v18];\n v32 = 0;\n do\n {\n v33 = *v31 + v32;\n v32 = v33;\n --v21;\n v31 = (_DWORD *)((char *)v31 + v30);\n }\n while ( v21 != -1 );\n *(_DWORD *)&v38[4 * v23 + 4] = v33;\n if ( v23 < 0 )\n return 1LL;\n }\n v34 = &v40;\n while ( *v34 == *(_DWORD *)(4 * v41) )\n {\n if ( (int *)((char *)&v41 + 4 * v24) == ++v34 )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1, uint32_t *a2) {\n long long v3;\n signed long long v4;\n void *v5;\n uint8_t *v6;\n long long v7;\n uint32_t *v8;\n uint32_t *v9;\n long long v10;\n uint32_t *v11;\n uint32_t *v12;\n int v13;\n int v14;\n uint32_t *v15;\n uint32_t *v16;\n uint32_t *v17;\n int v18;\n int v19;\n int v20;\n int v21;\n long long v22;\n int v23;\n unsigned int v24;\n long long v25;\n int v26;\n int v27;\n int v28;\n int v29;\n long long v30;\n uint32_t *v31;\n int v32;\n int v33;\n int *v34;\n unsigned long long v36;\n uint8_t v38[3];\n char v39;\n int v40;\n unsigned long long v41;\n long long v42;\n uint32_t *v43;\n unsigned long long v44;\n v43 = a2;\n v44 = __readfsqword(40u);\n v3 = a1;\n while (v38 != &v38[-((4LL * (2 * a1 + 2) + 15) & 18446744073709547520LL)])\n ;\n v4 = (4 * (2 * (unsigned short)a1 + 2) + 15) & 4080;\n v5 = alloca(v4);\n if (((4 * (2 * (unsigned short)a1 + 2) + 15) & 4080) != 0)\n *(uint64_t *)&v38[v4 - 8] = *(uint64_t *)&v38[v4 - 8];\n v41 = (unsigned long long)&v39 >> 2;\n if (a1 <= 0) {\n v36 = v41;\n *(uint32_t *)(4 * v41) = 0;\n *(uint32_t *)&byte_4[4 * v36] = 0;\n v24 = 0;\n } else {\n v6 = v38;\n v7 = 4LL * a1;\n v8 = v43;\n v9 = &v43[(unsigned long long)v7 / 4];\n v10 = -4LL * a1;\n v11 = &v43[(unsigned long long)v7 / 4];\n do {\n v12 = &v11[-v3];\n v13 = 0;\n do {\n v14 = *v12 + v13;\n v13 = v14;\n ++v12;\n } while (v12 != v11);\n *(uint32_t *)v6 = v14;\n v6 += 4;\n v11 = (uint32_t *)((char *)v11 + v7);\n } while (v6 != &v38[v7]);\n v15 = &v38[v7];\n v16 = v43;\n v42 = v3;\n do {\n v17 = v16;\n v18 = 0;\n v19 = 0;\n do {\n v20 = *v17 + v19;\n v19 = v20;\n v21 = v18++;\n v17 = (uint32_t *)((char *)v17 + v7);\n } while (a1 != v18);\n *v15++ = v20;\n ++v16;\n } while (v16 != v9);\n v22 = v42;\n v23 = 2 * v18;\n v24 = 2 * v18;\n v25 = v7 + 4;\n v26 = 0;\n v27 = 0;\n do {\n v28 = *v8 + v27;\n v27 = v28;\n v29 = v26++;\n v8 = (uint32_t *)((char *)v8 + v25);\n } while (v21 != v29);\n *(uint32_t *)&v38[4 * v23] = v28;\n v30 = v10 - 4;\n v31 = &v43[v22 * v21 - 1 + v18];\n v32 = 0;\n do {\n v33 = *v31 + v32;\n v32 = v33;\n --v21;\n v31 = (uint32_t *)((char *)v31 + v30);\n } while (v21 != -1);\n *(uint32_t *)&v38[4 * v23 + 4] = v33;\n if (v23 < 0) return 1LL;\n }\n v34 = &v40;\n while (*v34 == *(uint32_t *)(4 * v41)) {\n if ((int *)((char *)&v41 + 4 * v24) == ++v34) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(int a1, uint32_t *a2) {\n long long v3;\n signed long long v4;\n void *v5;\n uint8_t *v6;\n long long v7;\n uint32_t *v8;\n uint32_t *v9;\n long long v10;\n uint32_t *v11;\n uint32_t *v12;\n int v13;\n int v14;\n uint32_t *v15;\n uint32_t *v16;\n uint32_t *v17;\n int v18;\n int v19;\n int v20;\n int v21;\n long long v22;\n int v23;\n unsigned int v24;\n long long v25;\n int v26;\n int v27;\n int v28;\n int v29;\n long long v30;\n uint32_t *v31;\n int v32;\n int v33;\n int *v34;\n unsigned long long v36;\n uint8_t v38[3];\n char v39;\n int v40;\n unsigned long long v41;\n long long v42;\n uint32_t *v43;\n unsigned long long v44;\n v43 = a2;\n v44 = __readfsqword(40u);\n v3 = a1;\n while (v38 != &v38[-((4LL * (2 * a1 + 2) + 15) & 18446744073709547520LL)])\n ;\n v4 = (4 * (2 * (unsigned short)a1 + 2) + 15) & 4080;\n v5 = alloca(v4);\n if (((4 * (2 * (unsigned short)a1 + 2) + 15) & 4080) != 0)\n *(uint64_t *)&v38[v4 - 8] = *(uint64_t *)&v38[v4 - 8];\n v41 = (unsigned long long)&v39 >> 2;\n if (a1 <= 0) {\n v36 = v41;\n *(uint32_t *)(4 * v41) = 0;\n *(uint32_t *)&byte_4[4 * v36] = 0;\n v24 = 0;\n } else {\n v6 = v38;\n v7 = 4LL * a1;\n v8 = v43;\n v9 = &v43[(unsigned long long)v7 / 4];\n v10 = -4LL * a1;\n v11 = &v43[(unsigned long long)v7 / 4];\n do {\n v12 = &v11[-v3];\n v13 = 0;\n do {\n v14 = *v12 + v13;\n v13 = v14;\n ++v12;\n } while (v12 != v11);\n *(uint32_t *)v6 = v14;\n v6 += 4;\n v11 = (uint32_t *)((char *)v11 + v7);\n } while (v6 != &v38[v7]);\n v15 = &v38[v7];\n v16 = v43;\n v42 = v3;\n do {\n v17 = v16;\n v18 = 0;\n v19 = 0;\n do {\n v20 = *v17 + v19;\n v19 = v20;\n v21 = v18++;\n v17 = (uint32_t *)((char *)v17 + v7);\n } while (a1 != v18);\n *v15++ = v20;\n ++v16;\n } while (v16 != v9);\n v22 = v42;\n v23 = 2 * v18;\n v24 = 2 * v18;\n v25 = v7 + 4;\n v26 = 0;\n v27 = 0;\n do {\n v28 = *v8 + v27;\n v27 = v28;\n v29 = v26++;\n v8 = (uint32_t *)((char *)v8 + v25);\n } while (v21 != v29);\n *(uint32_t *)&v38[4 * v23] = v28;\n v30 = v10 - 4;\n v31 = &v43[v22 * v21 - 1 + v18];\n v32 = 0;\n do {\n v33 = *v31 + v32;\n v32 = v33;\n --v21;\n v31 = (uint32_t *)((char *)v31 + v30);\n } while (v21 != -1);\n *(uint32_t *)&v38[4 * v23 + 4] = v33;\n if (v23 < 0) return 1LL;\n }\n v34 = &v40;\n while (*v34 == *(uint32_t *)(4 * v41)) {\n if ((int *)((char *)&v41 + 4 * v24) == ++v34) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 129, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int size, int my_matrix[size][size]) {\n int sum_list[2 * size + 2];\n int index = 0;\n for (int i = 0; i < size; i++) {\n int sum = 0;\n for (int j = 0; j < size; j++) {\n sum += my_matrix[i][j];\n }\n sum_list[index++] = sum;\n }\n for (int j = 0; j < size; j++) {\n int sum = 0;\n for (int i = 0; i < size; i++) {\n sum += my_matrix[i][j];\n }\n sum_list[index++] = sum;\n }\n int result1 = 0;\n for (int i = 0; i < size; i++) {\n result1 += my_matrix[i][i];\n }\n sum_list[index++] = result1;\n int result2 = 0;\n for (int i = size - 1; i >= 0; i--) {\n result2 += my_matrix[i][i];\n }\n sum_list[index++] = result2;\n for (int k = 1; k < index; k++) {\n if (sum_list[k] != sum_list[0]) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n int matrix1[4][4] = {\n\n {7, 12, 1, 14},\n\n {2, 13, 8, 11},\n\n {16, 3, 10, 5},\n\n {9, 6, 15, 4}\n\n };\n\n int matrix2[3][3] = {\n\n {2, 7, 6},\n\n {9, 5, 1},\n\n {4, 3, 8}\n\n };\n\n int matrix3[3][3] = {\n\n {2, 7, 6},\n\n {9, 5, 1},\n\n {4, 3, 7}\n\n };\n\n\n\n assert(func0(4, matrix1) == true);\n\n assert(func0(3, matrix2) == true);\n\n assert(func0(3, matrix3) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\nmovslq %edi,%r13\npush %r12\nmov %rsi,%r12\npush %rbx\nsub $0x28,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nlea 0x2(%rdi,%rdi,1),%eax\nmov %rsp,%rbx\ncltq\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rbx\nand $0xfffffffffffffff0,%rdx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 1398 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 1383 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 1514 \nlea 0x3(%rsp),%rbx\nlea -0x1(%rdi),%r10d\nmov %rbx,%rax\nand $0xfffffffffffffffc,%rbx\nshr $0x2,%rax\nmov %rax,-0x48(%rbp)\ntest %edi,%edi\njle 151f \nmov %r10d,%r14d\nmov %rbx,%r8\nlea 0x0(,%r13,4),%r9\nmov %r12,%r11\nlea 0x0(,%r14,4),%rax\nnot %r14\nlea 0x4(%r12,%rax,1),%rsi\nlea 0x4(%rbx,%rax,1),%r15\nshl $0x2,%r14\nmov %rsi,%rcx\nnopw 0x0(%rax,%rax,1)\nlea (%r14,%rcx,1),%rax\nxor %edx,%edx\nnopw %cs:0x0(%rax,%rax,1)\nadd (%rax),%edx\nadd $0x4,%rax\ncmp %rcx,%rax\njne 1410 \nmov %edx,(%r8)\nadd $0x4,%r8\nlea (%rax,%r9,1),%rcx\ncmp %r15,%r8\njne 1400 \nlea (%rbx,%r9,1),%r15\nmov %r12,%r14\nnopw 0x0(%rax,%rax,1)\nmov %r14,%rdx\nxor %ecx,%ecx\nxor %eax,%eax\nmov %eax,%r8d\nlea 0x1(%rax),%eax\nadd (%rdx),%ecx\nadd %r9,%rdx\ncmp %eax,%edi\njne 1440 \nadd $0x4,%r14\nmov %ecx,(%r15)\nadd $0x4,%r15\ncmp %rsi,%r14\njne 1438 \nadd %edi,%edi\nadd $0x4,%r9\nxor %eax,%eax\nxor %edx,%edx\nmov %edi,%ecx\nnopl 0x0(%rax,%rax,1)\nmov %eax,%esi\nadd (%r11),%edx\nadd $0x1,%eax\nadd %r9,%r11\ncmp %esi,%r8d\njne 1470 \nlea 0x1(%rdi),%r8d\nmovslq %edi,%rdi\nmov %edx,(%rbx,%rdi,4)\nmovslq %r10d,%rax\nmov %r13,%rsi\nxor %edx,%edx\nadd $0x1,%rax\nnot %rsi\nimul %rax,%r13\nshl $0x2,%rsi\nlea (%r12,%r13,4),%rax\nnopl (%rax)\nsub $0x1,%r10d\nadd -0x4(%rax),%edx\nadd %rsi,%rax\ncmp $0xffffffff,%r10d\njne 14a8 \nmovslq %r8d,%r8\nadd $0x2,%ecx\nmov %edx,(%rbx,%r8,4)\ncmp $0x1,%ecx\njle 150d \nmov -0x48(%rbp),%rax\nsub $0x2,%ecx\nlea 0x8(%rbx,%rcx,4),%rcx\nmov 0x0(,%rax,4),%edx\nlea 0x4(%rbx),%rax\njmp 14e9 \nadd $0x4,%rax\ncmp %rax,%rcx\nje 150d \ncmp %edx,(%rax)\nje 14e0 \nxor %eax,%eax\nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\njne 1552 \nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\nmov $0x1,%eax\njmp 14ef \norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 13aa \nmov -0x48(%rbp),%rax\nmovl $0x0,0x0(,%rax,4)\ntest %r10d,%r10d\njns 1545 \nmovl $0x0,0x4(,%rax,4)\nmov $0x2,%ecx\njmp 14c7 \nxor %ecx,%ecx\nmov $0x1,%r8d\njmpq 148a \ncallq 1060 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov r11, rsi\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\nmovsxd r12, edi\npush rbx\nmov r8, r12\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nlea eax, [r12+r12+2]\nmov rcx, rsp\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_1329\nloc_1314:\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\ncmp rsp, rcx\njnz short loc_1314\nloc_1329:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1484\nloc_133B:\nlea r10, [rsp+1040h+var_103D]\nmov rbx, r10\nand r10, 0FFFFFFFFFFFFFFFCh\nshr rbx, 2\ntest r8d, r8d\njle loc_148F\nlea rdi, ds:0[r12*4]\nmov rsi, r10\nmov r9, r11\nlea r13, [rdi+r11]\nlea r14, [r10+rdi]\nmov rcx, r13\nnop dword ptr [rax]\nloc_1370:\nmov rax, rcx\nxor edx, edx\nsub rax, rdi\nnop dword ptr [rax+rax+00000000h]\nloc_1380:\nadd edx, [rax]\nadd rax, 4\ncmp rax, rcx\njnz short loc_1380\nmov [rsi], edx\nadd rsi, 4\nlea rcx, [rax+rdi]\ncmp rsi, r14\njnz short loc_1370\nmov r14, rsi\nmov r15, r11\nloc_13A0:\nmov rdx, r15\nxor eax, eax\nxor ecx, ecx\nnop word ptr [rax+rax+00000000h]\nloc_13B0:\nmov esi, eax\nadd eax, 1\nadd ecx, [rdx]\nadd rdx, rdi\ncmp r8d, eax\njnz short loc_13B0\nadd r15, 4\nmov [r14], ecx\nadd r14, 4\ncmp r15, r13\njnz short loc_13A0\nlea ecx, [rax+rax]\nlea r14, [rdi+4]\nxor edx, edx\nxor r8d, r8d\nnop dword ptr [rax+rax+00h]\nloc_13E0:\nmov r13d, edx\nadd r8d, [r9]\nadd edx, 1\nadd r9, r14\ncmp esi, r13d\njnz short loc_13E0\ncdqe\nmovsxd rdx, ecx\nlea r9d, [rcx+1]\nimul rax, r12\nmov [r10+rdx*4], r8d\nmov r8, 0FFFFFFFFFFFFFFFCh\nxor edx, edx\nsub r8, rdi\nlea rax, [r11+rax*4-4]\nnop dword ptr [rax+rax+00h]\nloc_1418:\nsub esi, 1\nadd edx, [rax]\nadd rax, r8\ncmp esi, 0FFFFFFFFh\njnz short loc_1418\nmovsxd r9, r9d\nadd ecx, 2\nmov [r10+r9*4], edx\ncmp ecx, 1\njle short loc_147D\nloc_1434:\nsub ecx, 2\nmov edx, ds:dword_0[rbx*4]\nlea rax, [r10+4]\nlea rcx, [r10+rcx*4+8]\njmp short loc_1459\nloc_1450:\nadd rax, 4\ncmp rax, rcx\njz short loc_147D\nloc_1459:\ncmp [rax], edx\njz short loc_1450\nxor eax, eax\nloc_145F:\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_14A2\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_147D:\nmov eax, 1\njmp short loc_145F\nloc_1484:\nor [rsp+rdx+1040h+var_1048], 0\njmp loc_133B\nloc_148F:\nmov qword ptr ds:dword_0[rbx*4], 0\nmov ecx, 2\njmp short loc_1434\nloc_14A2:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1, _DWORD *a2)\n{\n __int64 v3; // r12\n __int64 v5; // rdx\n _QWORD *v6; // rcx\n __int16 v7; // dx\n signed __int64 v8; // rdx\n void *v9; // rsp\n __int64 v10; // rdi\n _QWORD *v11; // rsi\n _DWORD *v12; // r9\n _DWORD *v13; // rcx\n int v14; // edx\n _DWORD *v15; // rax\n _DWORD *v16; // r14\n _DWORD *v17; // r15\n _DWORD *v18; // rdx\n int v19; // eax\n int v20; // ecx\n int v21; // esi\n int v22; // ecx\n int v23; // edx\n int v24; // r8d\n int v25; // r13d\n int v26; // r9d\n int v27; // edx\n _DWORD *v28; // rax\n int v29; // ecx\n _DWORD *v30; // rax\n char *v31; // rcx\n _QWORD v34[511]; // [rsp+8h] [rbp-1040h] BYREF\n _QWORD v35[8]; // [rsp+1008h] [rbp-40h] BYREF\n\n v3 = a1;\n v35[1] = __readfsqword(0x28u);\n v5 = 4LL * (2 * a1 + 2) + 15;\n v6 = (_QWORD *)((char *)v35 - (v5 & 0xFFFFFFFFFFFFF000LL));\n v7 = v5 & 0xFFF0;\n if ( v35 != v6 )\n {\n while ( v34 != v6 )\n ;\n }\n v8 = v7 & 0xFFF;\n v9 = alloca(v8);\n if ( v8 )\n *(_QWORD *)((char *)&v34[-1] + v8) = *(_QWORD *)((char *)&v34[-1] + v8);\n if ( a1 <= 0 )\n {\n v34[0] = 0LL;\n v29 = 2;\n }\n else\n {\n v10 = 4LL * a1;\n v11 = v34;\n v12 = a2;\n v13 = &a2[v3];\n do\n {\n v14 = 0;\n v15 = &v13[v10 / 0xFFFFFFFFFFFFFFFCLL];\n do\n v14 += *v15++;\n while ( v15 != v13 );\n *(_DWORD *)v11 = v14;\n v11 = (_QWORD *)((char *)v11 + 4);\n v13 = &v15[(unsigned __int64)v10 / 4];\n }\n while ( v11 != (_QWORD *)((char *)v34 + 4 * v3) );\n v16 = v11;\n v17 = a2;\n do\n {\n v18 = v17;\n v19 = 0;\n v20 = 0;\n do\n {\n v21 = v19++;\n v20 += *v18;\n v18 = (_DWORD *)((char *)v18 + v10);\n }\n while ( a1 != v19 );\n ++v17;\n *v16++ = v20;\n }\n while ( v17 != &a2[v3] );\n v22 = 2 * v19;\n v23 = 0;\n v24 = 0;\n do\n {\n v25 = v23;\n v24 += *v12;\n ++v23;\n v12 = (_DWORD *)((char *)v12 + v10 + 4);\n }\n while ( v21 != v25 );\n v26 = v22 + 1;\n LODWORD(v34[v22 / 2u]) = v24;\n v27 = 0;\n v28 = &a2[v3 * v19 - 1];\n do\n {\n --v21;\n v27 += *v28;\n v28 = (_DWORD *)((char *)v28 - 4 - v10);\n }\n while ( v21 != -1 );\n v29 = v22 + 2;\n *((_DWORD *)v34 + v26) = v27;\n if ( v29 <= 1 )\n return 1LL;\n }\n v30 = (_DWORD *)v34 + 1;\n v31 = (char *)&v34[1] + 4 * (unsigned int)(v29 - 2);\n while ( *v30 == LODWORD(v34[0]) )\n {\n if ( ++v30 == (_DWORD *)v31 )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\npush rbp\nmov r11, rsi\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\nmovsxd r12, edi\npush rbx\nmov r8, r12\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nlea eax, [r12+r12+2]\nmov rcx, rsp\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_1329\nloc_1314:\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\ncmp rsp, rcx\njnz short loc_1314\nloc_1329:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1484\nloc_133B:\nlea r10, [rsp+1040h+var_103D]\nmov rbx, r10\nand r10, 0FFFFFFFFFFFFFFFCh\nshr rbx, 2\ntest r8d, r8d\njle loc_148F\nlea rdi, ds:0[r12*4]\nmov rsi, r10\nmov r9, r11\nlea r13, [rdi+r11]\nlea r14, [r10+rdi]\nmov rcx, r13\nnop dword ptr [rax]\nloc_1370:\nmov rax, rcx\nxor edx, edx\nsub rax, rdi\nnop dword ptr [rax+rax+00000000h]\nloc_1380:\nadd edx, [rax]\nadd rax, 4\ncmp rax, rcx\njnz short loc_1380\nmov [rsi], edx\nadd rsi, 4\nlea rcx, [rax+rdi]\ncmp rsi, r14\njnz short loc_1370\nmov r14, rsi\nmov r15, r11\nloc_13A0:\nmov rdx, r15\nxor eax, eax\nxor ecx, ecx\nnop word ptr [rax+rax+00000000h]\nloc_13B0:\nmov esi, eax\nadd eax, 1\nadd ecx, [rdx]\nadd rdx, rdi\ncmp r8d, eax\njnz short loc_13B0\nadd r15, 4\nmov [r14], ecx\nadd r14, 4\ncmp r15, r13\njnz short loc_13A0\nlea ecx, [rax+rax]\nlea r14, [rdi+4]\nxor edx, edx\nxor r8d, r8d\nnop dword ptr [rax+rax+00h]\nloc_13E0:\nmov r13d, edx\nadd r8d, [r9]\nadd edx, 1\nadd r9, r14\ncmp esi, r13d\njnz short loc_13E0\ncdqe\nmovsxd rdx, ecx\nlea r9d, [rcx+1]\nimul rax, r12\nmov [r10+rdx*4], r8d\nmov r8, 0FFFFFFFFFFFFFFFCh\nxor edx, edx\nsub r8, rdi\nlea rax, [r11+rax*4-4]\nnop dword ptr [rax+rax+00h]\nloc_1418:\nsub esi, 1\nadd edx, [rax]\nadd rax, r8\ncmp esi, 0FFFFFFFFh\njnz short loc_1418\nmovsxd r9, r9d\nadd ecx, 2\nmov [r10+r9*4], edx\ncmp ecx, 1\njle short loc_147D\nloc_1434:\nsub ecx, 2\nmov edx, ds:dword_0[rbx*4]\nlea rax, [r10+4]\nlea rcx, [r10+rcx*4+8]\njmp short loc_1459\nloc_1450:\nadd rax, 4\ncmp rax, rcx\njz short loc_147D\nloc_1459:\ncmp [rax], edx\njz short loc_1450\nxor eax, eax\nloc_145F:\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_14A2\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_147D:\nmov eax, 1\njmp short loc_145F\nloc_1484:\nor [rsp+rdx+1040h+var_1048], 0\njmp loc_133B\nloc_148F:\nmov qword ptr ds:dword_0[rbx*4], 0\nmov ecx, 2\njmp short loc_1434\nloc_14A2:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12C0(int a1, _DWORD *a2)\n{\n __int64 v3; // r12\n __int64 v5; // rdx\n _QWORD *v6; // rcx\n __int16 v7; // dx\n signed __int64 v8; // rdx\n void *v9; // rsp\n __int64 v10; // rdi\n _QWORD *v11; // rsi\n _DWORD *v12; // r9\n _DWORD *v13; // rcx\n int v14; // edx\n _DWORD *v15; // rax\n _DWORD *v16; // r14\n _DWORD *v17; // r15\n _DWORD *v18; // rdx\n int v19; // eax\n int v20; // ecx\n int v21; // esi\n int v22; // ecx\n int v23; // edx\n int v24; // r8d\n int v25; // r13d\n int v26; // r9d\n int v27; // edx\n _DWORD *v28; // rax\n int v29; // ecx\n _DWORD *v30; // rax\n char *v31; // rcx\n _QWORD v34[511]; // [rsp+8h] [rbp-1040h] BYREF\n _QWORD v35[8]; // [rsp+1008h] [rbp-40h] BYREF\n\n v3 = a1;\n v35[1] = __readfsqword(0x28u);\n v5 = 4LL * (2 * a1 + 2) + 15;\n v6 = (_QWORD *)((char *)v35 - (v5 & 0xFFFFFFFFFFFFF000LL));\n v7 = v5 & 0xFFF0;\n if ( v35 != v6 )\n {\n while ( v34 != v6 )\n ;\n }\n v8 = v7 & 0xFFF;\n v9 = alloca(v8);\n if ( v8 )\n *(_QWORD *)((char *)&v34[-1] + v8) = *(_QWORD *)((char *)&v34[-1] + v8);\n if ( a1 <= 0 )\n {\n v34[0] = 0LL;\n v29 = 2;\n }\n else\n {\n v10 = 4LL * a1;\n v11 = v34;\n v12 = a2;\n v13 = &a2[v3];\n do\n {\n v14 = 0;\n v15 = &v13[v10 / 0xFFFFFFFFFFFFFFFCLL];\n do\n v14 += *v15++;\n while ( v15 != v13 );\n *(_DWORD *)v11 = v14;\n v11 = (_QWORD *)((char *)v11 + 4);\n v13 = &v15[(unsigned __int64)v10 / 4];\n }\n while ( v11 != (_QWORD *)((char *)v34 + 4 * v3) );\n v16 = v11;\n v17 = a2;\n do\n {\n v18 = v17;\n v19 = 0;\n v20 = 0;\n do\n {\n v21 = v19++;\n v20 += *v18;\n v18 = (_DWORD *)((char *)v18 + v10);\n }\n while ( a1 != v19 );\n ++v17;\n *v16++ = v20;\n }\n while ( v17 != &a2[v3] );\n v22 = 2 * v19;\n v23 = 0;\n v24 = 0;\n do\n {\n v25 = v23;\n v24 += *v12;\n ++v23;\n v12 = (_DWORD *)((char *)v12 + v10 + 4);\n }\n while ( v21 != v25 );\n v26 = v22 + 1;\n LODWORD(v34[v22 / 2u]) = v24;\n v27 = 0;\n v28 = &a2[v3 * v19 - 1];\n do\n {\n --v21;\n v27 += *v28;\n v28 = (_DWORD *)((char *)v28 - 4 - v10);\n }\n while ( v21 != -1 );\n v29 = v22 + 2;\n *((_DWORD *)v34 + v26) = v27;\n if ( v29 <= 1 )\n return 1LL;\n }\n v30 = (_DWORD *)v34 + 1;\n v31 = (char *)&v34[1] + 4 * (unsigned int)(v29 - 2);\n while ( *v30 == LODWORD(v34[0]) )\n {\n if ( ++v30 == (_DWORD *)v31 )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12C0(int a1, uint32_t *a2) {\n long long v3;\n long long v5;\n uint64_t *v6;\n short v7;\n signed long long v8;\n void *v9;\n long long v10;\n uint64_t *v11;\n uint32_t *v12;\n uint32_t *v13;\n int v14;\n uint32_t *v15;\n uint32_t *v16;\n uint32_t *v17;\n uint32_t *v18;\n int v19;\n int v20;\n int v21;\n int v22;\n int v23;\n int v24;\n int v25;\n int v26;\n int v27;\n uint32_t *v28;\n int v29;\n uint32_t *v30;\n char *v31;\n uint64_t v34[511];\n uint64_t v35[8];\n v3 = a1;\n v35[1] = __readfsqword(40u);\n v5 = 4LL * (2 * a1 + 2) + 15;\n v6 = (uint64_t *)((char *)v35 - (v5 & 18446744073709547520LL));\n v7 = v5 & 65520;\n if (v35 != v6) {\n while (v34 != v6)\n ;\n }\n v8 = v7 & 4095;\n v9 = alloca(v8);\n if (v8)\n *(uint64_t *)((char *)&v34[-1] + v8) = *(uint64_t *)((char *)&v34[-1] + v8);\n if (a1 <= 0) {\n v34[0] = 0LL;\n v29 = 2;\n } else {\n v10 = 4LL * a1;\n v11 = v34;\n v12 = a2;\n v13 = &a2[v3];\n do {\n v14 = 0;\n v15 = &v13[v10 / 18446744073709551612LL];\n do\n v14 += *v15++;\n while (v15 != v13);\n *(uint32_t *)v11 = v14;\n v11 = (uint64_t *)((char *)v11 + 4);\n v13 = &v15[(unsigned long long)v10 / 4];\n } while (v11 != (uint64_t *)((char *)v34 + 4 * v3));\n v16 = v11;\n v17 = a2;\n do {\n v18 = v17;\n v19 = 0;\n v20 = 0;\n do {\n v21 = v19++;\n v20 += *v18;\n v18 = (uint32_t *)((char *)v18 + v10);\n } while (a1 != v19);\n ++v17;\n *v16++ = v20;\n } while (v17 != &a2[v3]);\n v22 = 2 * v19;\n v23 = 0;\n v24 = 0;\n do {\n v25 = v23;\n v24 += *v12;\n ++v23;\n v12 = (uint32_t *)((char *)v12 + v10 + 4);\n } while (v21 != v25);\n v26 = v22 + 1;\n LODWORD(v34[v22 / 2u]) = v24;\n v27 = 0;\n v28 = &a2[v3 * v19 - 1];\n do {\n --v21;\n v27 += *v28;\n v28 = (uint32_t *)((char *)v28 - 4 - v10);\n } while (v21 != -1);\n v29 = v22 + 2;\n *((uint32_t *)v34 + v26) = v27;\n if (v29 <= 1) return 1LL;\n }\n v30 = (uint32_t *)v34 + 1;\n v31 = (char *)&v34[1] + 4 * (unsigned int)(v29 - 2);\n while (*v30 == LODWORD(v34[0])) {\n if (++v30 == (uint32_t *)v31) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(int a1, uint32_t *a2) {\n long long v3;\n long long v5;\n uint64_t *v6;\n short v7;\n signed long long v8;\n void *v9;\n long long v10;\n uint64_t *v11;\n uint32_t *v12;\n uint32_t *v13;\n int v14;\n uint32_t *v15;\n uint32_t *v16;\n uint32_t *v17;\n uint32_t *v18;\n int v19;\n int v20;\n int v21;\n int v22;\n int v23;\n int v24;\n int v25;\n int v26;\n int v27;\n uint32_t *v28;\n int v29;\n uint32_t *v30;\n char *v31;\n uint64_t v34[511];\n uint64_t v35[8];\n v3 = a1;\n v35[1] = __readfsqword(40u);\n v5 = 4LL * (2 * a1 + 2) + 15;\n v6 = (uint64_t *)((char *)v35 - (v5 & 18446744073709547520LL));\n v7 = v5 & 65520;\n if (v35 != v6) {\n while (v34 != v6)\n ;\n }\n v8 = v7 & 4095;\n v9 = alloca(v8);\n if (v8)\n *(uint64_t *)((char *)&v34[-1] + v8) = *(uint64_t *)((char *)&v34[-1] + v8);\n if (a1 <= 0) {\n v34[0] = 0LL;\n v29 = 2;\n } else {\n v10 = 4LL * a1;\n v11 = v34;\n v12 = a2;\n v13 = &a2[v3];\n do {\n v14 = 0;\n v15 = &v13[v10 / 18446744073709551612LL];\n do\n v14 += *v15++;\n while (v15 != v13);\n *(uint32_t *)v11 = v14;\n v11 = (uint64_t *)((char *)v11 + 4);\n v13 = &v15[(unsigned long long)v10 / 4];\n } while (v11 != (uint64_t *)((char *)v34 + 4 * v3));\n v16 = v11;\n v17 = a2;\n do {\n v18 = v17;\n v19 = 0;\n v20 = 0;\n do {\n v21 = v19++;\n v20 += *v18;\n v18 = (uint32_t *)((char *)v18 + v10);\n } while (a1 != v19);\n ++v17;\n *v16++ = v20;\n } while (v17 != &a2[v3]);\n v22 = 2 * v19;\n v23 = 0;\n v24 = 0;\n do {\n v25 = v23;\n v24 += *v12;\n ++v23;\n v12 = (uint32_t *)((char *)v12 + v10 + 4);\n } while (v21 != v25);\n v26 = v22 + 1;\n LODWORD(v34[v22 / 2u]) = v24;\n v27 = 0;\n v28 = &a2[v3 * v19 - 1];\n do {\n --v21;\n v27 += *v28;\n v28 = (uint32_t *)((char *)v28 - 4 - v10);\n } while (v21 != -1);\n v29 = v22 + 2;\n *((uint32_t *)v34 + v26) = v27;\n if (v29 <= 1) return 1LL;\n }\n v30 = (uint32_t *)v34 + 1;\n v31 = (char *)&v34[1] + 4 * (unsigned int)(v29 - 2);\n while (*v30 == LODWORD(v34[0])) {\n if (++v30 == (uint32_t *)v31) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 129, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int size, int my_matrix[size][size]) {\n int sum_list[2 * size + 2];\n int index = 0;\n for (int i = 0; i < size; i++) {\n int sum = 0;\n for (int j = 0; j < size; j++) {\n sum += my_matrix[i][j];\n }\n sum_list[index++] = sum;\n }\n for (int j = 0; j < size; j++) {\n int sum = 0;\n for (int i = 0; i < size; i++) {\n sum += my_matrix[i][j];\n }\n sum_list[index++] = sum;\n }\n int result1 = 0;\n for (int i = 0; i < size; i++) {\n result1 += my_matrix[i][i];\n }\n sum_list[index++] = result1;\n int result2 = 0;\n for (int i = size - 1; i >= 0; i--) {\n result2 += my_matrix[i][i];\n }\n sum_list[index++] = result2;\n for (int k = 1; k < index; k++) {\n if (sum_list[k] != sum_list[0]) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n int matrix1[4][4] = {\n\n {7, 12, 1, 14},\n\n {2, 13, 8, 11},\n\n {16, 3, 10, 5},\n\n {9, 6, 15, 4}\n\n };\n\n int matrix2[3][3] = {\n\n {2, 7, 6},\n\n {9, 5, 1},\n\n {4, 3, 8}\n\n };\n\n int matrix3[3][3] = {\n\n {2, 7, 6},\n\n {9, 5, 1},\n\n {4, 3, 7}\n\n };\n\n\n\n assert(func0(4, matrix1) == true);\n\n assert(func0(3, matrix2) == true);\n\n assert(func0(3, matrix3) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0x38,%rsp\nmov %rsi,-0x48(%rbp)\nmov %rsp,%rbx\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nmovslq %edi,%rax\nmov %rax,-0x50(%rbp)\nlea 0x2(%rdi,%rdi,1),%eax\ncltq\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rbx\nand $0xfffffffffffffff0,%rdx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 132d \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 1318 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 1540 \nlea 0x3(%rsp),%r15\nlea -0x1(%rdi),%r8d\nmov %r15,%rax\nand $0xfffffffffffffffc,%r15\nshr $0x2,%rax\nmov %rax,-0x60(%rbp)\ntest %edi,%edi\njle 154b \nmov -0x50(%rbp),%rax\nmov -0x48(%rbp),%rsi\nmov %edi,%r13d\nmov %edi,%ebx\nshr $0x2,%r13d\nmov %r15,%r9\nand $0xfffffffc,%ebx\nlea 0x0(,%rax,4),%rdx\nmov %r8d,%eax\nmov %rsi,%r11\nshl $0x4,%r13\nshl $0x2,%rax\nmov %rax,-0x58(%rbp)\nlea 0x4(%r15,%rax,1),%r14\nnopl (%rax)\ncmp $0x3,%r8d\njbe 1530 \nlea 0x0(%r13,%rsi,1),%rcx\nmov %rsi,%rax\npxor %xmm0,%xmm0\nxchg %ax,%ax\nmovdqu (%rax),%xmm2\nadd $0x10,%rax\npaddd %xmm2,%xmm0\ncmp %rcx,%rax\njne 13b0 \nmovdqa %xmm0,%xmm1\nmov %ebx,%ecx\npsrldq $0x8,%xmm1\npaddd %xmm1,%xmm0\nmovdqa %xmm0,%xmm1\npsrldq $0x4,%xmm1\npaddd %xmm1,%xmm0\nmovd %xmm0,%eax\ncmp %edi,%ebx\nje 1414 \nmovslq %ecx,%r10\nlea 0x1(%rcx),%r12d\nlea (%rsi,%r10,4),%r10\nadd (%r10),%eax\ncmp %r12d,%edi\njle 1414 \nlea 0x2(%rcx),%r12d\nadd 0x4(%r10),%eax\ncmp %r12d,%edi\njle 1414 \nadd $0x3,%ecx\nadd 0x8(%r10),%eax\ncmp %ecx,%edi\njle 1414 \nadd 0xc(%r10),%eax\nmov %eax,(%r9)\nadd $0x4,%r9\nadd %rdx,%rsi\ncmp %r14,%r9\njne 1398 \nmov -0x48(%rbp),%r10\nmov -0x58(%rbp),%rax\nlea (%r15,%rdx,1),%rbx\nlea 0x4(%r10,%rax,1),%r12\nnopl 0x0(%rax,%rax,1)\nmov %r10,%rcx\nxor %esi,%esi\nxor %eax,%eax\nnopw 0x0(%rax,%rax,1)\nmov %eax,%r9d\nlea 0x1(%rax),%eax\nadd (%rcx),%esi\nadd %rdx,%rcx\ncmp %eax,%edi\njne 1450 \nadd $0x4,%r10\nmov %esi,(%rbx)\nadd $0x4,%rbx\ncmp %r12,%r10\njne 1440 \nadd %edi,%edi\nadd $0x4,%rdx\nxor %eax,%eax\nxor %ecx,%ecx\nmov %edi,%esi\nnopw 0x0(%rax,%rax,1)\nmov %eax,%r10d\nadd (%r11),%ecx\nadd $0x1,%eax\nadd %rdx,%r11\ncmp %r10d,%r9d\njne 1480 \nlea 0x1(%rdi),%r9d\nmovslq %edi,%rdi\nmov %ecx,(%r15,%rdi,4)\nmov -0x50(%rbp),%rbx\nmovslq %r8d,%rax\nxor %edx,%edx\nadd $0x1,%rax\nimul %rbx,%rax\nmov %rbx,%rcx\nmov -0x48(%rbp),%rbx\nnot %rcx\nshl $0x2,%rcx\nlea (%rbx,%rax,4),%rax\nsub $0x1,%r8d\nadd -0x4(%rax),%edx\nadd %rcx,%rax\ncmp $0xffffffff,%r8d\njne 14c0 \nmovslq %r9d,%r9\nadd $0x2,%esi\nmov %edx,(%r15,%r9,4)\ncmp $0x1,%esi\njle 1539 \nmov -0x60(%rbp),%rax\nlea -0x2(%rsi),%ecx\nlea 0x8(%r15,%rcx,4),%rcx\nmov 0x0(,%rax,4),%edx\nlea 0x4(%r15),%rax\njmp 1509 \nnopl 0x0(%rax,%rax,1)\nadd $0x4,%rax\ncmp %rcx,%rax\nje 1539 \ncmp %edx,(%rax)\nje 1500 \nxor %eax,%eax\nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\njne 157d \nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\nnopl (%rax)\nxor %eax,%eax\nxor %ecx,%ecx\njmpq 13e5 \nmov $0x1,%eax\njmp 150f \norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 133f \nmovl $0x0,0x0(,%rax,4)\ntest %r8d,%r8d\njns 1570 \nmovl $0x0,0x4(,%rax,4)\nmov $0x2,%esi\njmpq 14df \nxor %esi,%esi\nmov $0x1,%r9d\njmpq 149c \ncallq 1060 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov r10, rsi\nmov rbp, rsp\npush r15\nmovsxd r15, edi\npush r14\nmov rax, r15\npush r13\npush r12\npush rbx\nsub rsp, 38h\nmov rdx, fs:28h\nmov [rbp+var_38], rdx\nxor edx, edx\nlea edx, [r15+r15+2]\nmov rsi, rsp\nmovsxd rdx, edx\nlea rdx, ds:0Fh[rdx*4]\nmov rcx, rdx\nand rdx, 0FFFFFFFFFFFFF000h\nsub rsi, rdx\nand rcx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rsi\njz short loc_132B\nloc_1316:\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\ncmp rsp, rsi\njnz short loc_1316\nloc_132B:\nand ecx, 0FFFh\nsub rsp, rcx\ntest rcx, rcx\njnz loc_1533\nloc_133D:\nlea r9, [rsp+1060h+var_105D]\nmov rdi, r9\nand r9, 0FFFFFFFFFFFFFFFCh\nshr rdi, 2\ntest eax, eax\njle loc_153E\nmov r11d, eax\nmov [rbp+var_48], r15\nmov r14d, eax\nmov r12d, eax\nmov [rbp+var_50], r10\nshr r11d, 2\nmov rcx, r9\nlea ebx, [rax-1]\nmov [rbp+var_58], r10\nshl r11, 4\nand r14d, 0FFFFFFFCh\nmov rsi, r10\nlea rdx, ds:0[r15*4]\nand r12d, 3\nlea r13, [r9+rdx]\nnop\nloc_1390:\ncmp ebx, 2\njbe loc_1520\nlea r10, [r11+rsi]\nmov r8, rsi\npxor xmm0, xmm0\nnop dword ptr [rax+00h]\nloc_13A8:\nmovdqu xmm2, xmmword ptr [r8]\nadd r8, 10h\npaddd xmm0, xmm2\ncmp r8, r10\njnz short loc_13A8\nmovdqa xmm1, xmm0\nmov r8d, r14d\npsrldq xmm1, 8\npaddd xmm0, xmm1\nmovdqa xmm1, xmm0\npsrldq xmm1, 4\npaddd xmm0, xmm1\ntest r12d, r12d\njz short loc_1412\nloc_13DC:\nmovsxd r10, r8d\nlea r15d, [r8+1]\nlea r10, [rsi+r10*4]\nmovd xmm1, dword ptr [r10]\npaddd xmm0, xmm1\ncmp eax, r15d\njle short loc_1412\nmovd xmm1, dword ptr [r10+4]\nadd r8d, 2\npaddd xmm0, xmm1\ncmp eax, r8d\njle short loc_1412\nmovd xmm1, dword ptr [r10+8]\npaddd xmm0, xmm1\nloc_1412:\nmovd dword ptr [rcx], xmm0\nadd rcx, 4\nadd rsi, rdx\ncmp rcx, r13\njnz loc_1390\nmov r10, [rbp+var_58]\nmov r15, [rbp+var_48]\nmov r8, [rbp+var_50]\nlea r14, [r10+rdx]\nmov r13, r10\nnop dword ptr [rax+00000000h]\nloc_1440:\nmov r11, r13\nxor esi, esi\nxor ebx, ebx\nnop word ptr [rax+rax+00000000h]\nloc_1450:\nmov r12d, esi\nadd esi, 1\nadd ebx, [r11]\nadd r11, rdx\ncmp eax, esi\njnz short loc_1450\nadd r13, 4\nmov [rcx], ebx\nadd rcx, 4\ncmp r13, r14\njnz short loc_1440\nlea ecx, [rsi+rsi]\nlea r13, [r15+1]\nadd rdx, 4\nxor eax, eax\nxor r11d, r11d\nnop\nloc_1480:\nmov ebx, eax\nadd r11d, [r8]\nadd eax, 1\nadd r8, rdx\ncmp r12d, ebx\njnz short loc_1480\nmovsxd rsi, esi\nmovsxd rax, ecx\nneg r13\nxor edx, edx\nimul rsi, r15\nmov [r9+rax*4], r11d\nlea r8d, [rcx+1]\nlea r11, ds:0[r13*4]\nlea rax, [r10+rsi*4-4]\nnop dword ptr [rax+00h]\nloc_14B8:\nsub r12d, 1\nadd edx, [rax]\nadd rax, r11\ncmp r12d, 0FFFFFFFFh\njnz short loc_14B8\nmovsxd r8, r8d\nadd ecx, 2\nmov [r9+r8*4], edx\ncmp ecx, 1\njle short loc_152C\nloc_14D6:\nsub ecx, 2\nmov edx, ds:dword_0[rdi*4]\nlea rax, [r9+4]\nlea rcx, [r9+rcx*4+8]\njmp short loc_14F9\nloc_14F0:\nadd rax, 4\ncmp rcx, rax\njz short loc_152C\nloc_14F9:\ncmp [rax], edx\njz short loc_14F0\nxor eax, eax\nloc_14FF:\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_1551\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1520:\nxor r8d, r8d\npxor xmm0, xmm0\njmp loc_13DC\nloc_152C:\nmov eax, 1\njmp short loc_14FF\nloc_1533:\nor [rsp+rcx+1060h+var_1068], 0\njmp loc_133D\nloc_153E:\nmov qword ptr ds:dword_0[rdi*4], 0\nmov ecx, 2\njmp short loc_14D6\nloc_1551:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1, const __m128i *a2)\n{\n __int64 v3; // rcx\n __int64 *v4; // rsi\n __int16 v5; // cx\n signed __int64 v6; // rcx\n void *v7; // rsp\n _QWORD *v8; // rcx\n const __m128i *v9; // rsi\n __int64 v10; // rdx\n const __m128i *v11; // r8\n __m128i v12; // xmm0\n __m128i v13; // xmm2\n signed int v14; // r8d\n __m128i v15; // xmm0\n __m128i v16; // xmm0\n unsigned int *v17; // r10\n const __m128i *v18; // r10\n __int64 v19; // r15\n const __m128i *v20; // r8\n __int32 *v21; // r14\n const __m128i *v22; // r13\n const __m128i *v23; // r11\n int v24; // esi\n int v25; // ebx\n int v26; // r12d\n int v27; // ecx\n __int64 v28; // rdx\n int v29; // eax\n int v30; // r11d\n int v31; // ebx\n int v32; // edx\n int v33; // r8d\n __int32 *v34; // rax\n int v35; // ecx\n _DWORD *v36; // rax\n char *v37; // rcx\n _QWORD v40[511]; // [rsp+8h] [rbp-1060h] BYREF\n __int64 v41; // [rsp+1008h] [rbp-60h] BYREF\n const __m128i *v42; // [rsp+1010h] [rbp-58h]\n const __m128i *v43; // [rsp+1018h] [rbp-50h]\n __int64 v44; // [rsp+1020h] [rbp-48h]\n unsigned __int64 v45; // [rsp+1030h] [rbp-38h]\n\n v45 = __readfsqword(0x28u);\n v3 = 4LL * (2 * a1 + 2) + 15;\n v4 = (__int64 *)((char *)&v41 - (v3 & 0xFFFFFFFFFFFFF000LL));\n v5 = v3 & 0xFFF0;\n if ( &v41 != v4 )\n {\n while ( v40 != v4 )\n ;\n }\n v6 = v5 & 0xFFF;\n v7 = alloca(v6);\n if ( v6 )\n *(_QWORD *)((char *)&v40[-1] + v6) = *(_QWORD *)((char *)&v40[-1] + v6);\n if ( a1 > 0 )\n {\n v44 = a1;\n v43 = a2;\n v8 = v40;\n v42 = a2;\n v9 = a2;\n v10 = 4LL * a1;\n while ( (unsigned int)(a1 - 1) > 2 )\n {\n v11 = v9;\n v12 = 0LL;\n do\n {\n v13 = _mm_loadu_si128(v11++);\n v12 = _mm_add_epi32(v12, v13);\n }\n while ( v11 != &v9[(unsigned int)a1 >> 2] );\n v14 = a1 & 0xFFFFFFFC;\n v15 = _mm_add_epi32(v12, _mm_srli_si128(v12, 8));\n v16 = _mm_add_epi32(v15, _mm_srli_si128(v15, 4));\n if ( (a1 & 3) != 0 )\n goto LABEL_11;\nLABEL_14:\n *(_DWORD *)v8 = _mm_cvtsi128_si32(v16);\n v8 = (_QWORD *)((char *)v8 + 4);\n v9 = (const __m128i *)((char *)v9 + v10);\n if ( v8 == (_QWORD *)((char *)v40 + 4 * a1) )\n {\n v18 = v42;\n v19 = v44;\n v20 = v43;\n v21 = &v42->m128i_i32[(unsigned __int64)v10 / 4];\n v22 = v42;\n do\n {\n v23 = v22;\n v24 = 0;\n v25 = 0;\n do\n {\n v26 = v24++;\n v25 += v23->m128i_i32[0];\n v23 = (const __m128i *)((char *)v23 + v10);\n }\n while ( a1 != v24 );\n v22 = (const __m128i *)((char *)v22 + 4);\n *(_DWORD *)v8 = v25;\n v8 = (_QWORD *)((char *)v8 + 4);\n }\n while ( v22 != (const __m128i *)v21 );\n v27 = 2 * v24;\n v28 = v10 + 4;\n v29 = 0;\n v30 = 0;\n do\n {\n v31 = v29;\n v30 += v20->m128i_i32[0];\n ++v29;\n v20 = (const __m128i *)((char *)v20 + v28);\n }\n while ( v26 != v31 );\n v32 = 0;\n LODWORD(v40[v27 / 2u]) = v30;\n v33 = v27 + 1;\n v34 = &v18->m128i_i32[v19 * v24 - 1];\n do\n {\n --v26;\n v32 += *v34;\n v34 += -v19 - 1;\n }\n while ( v26 != -1 );\n v35 = v27 + 2;\n *((_DWORD *)v40 + v33) = v32;\n if ( v35 > 1 )\n goto LABEL_24;\n return 1LL;\n }\n }\n v14 = 0;\n v16 = 0LL;\nLABEL_11:\n v17 = (unsigned int *)v9 + v14;\n v16 = _mm_add_epi32(v16, _mm_cvtsi32_si128(*v17));\n if ( a1 > v14 + 1 )\n {\n v16 = _mm_add_epi32(v16, _mm_cvtsi32_si128(v17[1]));\n if ( a1 > v14 + 2 )\n v16 = _mm_add_epi32(v16, _mm_cvtsi32_si128(v17[2]));\n }\n goto LABEL_14;\n }\n v40[0] = 0LL;\n v35 = 2;\nLABEL_24:\n v36 = (_DWORD *)v40 + 1;\n v37 = (char *)&v40[1] + 4 * (unsigned int)(v35 - 2);\n while ( *v36 == LODWORD(v40[0]) )\n {\n if ( v37 == (char *)++v36 )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\npush rbp\nmov r10, rsi\nmov rbp, rsp\npush r15\nmovsxd r15, edi\npush r14\nmov rax, r15\npush r13\npush r12\npush rbx\nsub rsp, 38h\nmov rdx, fs:28h\nmov [rbp+var_38], rdx\nxor edx, edx\nlea edx, [r15+r15+2]\nmov rsi, rsp\nmovsxd rdx, edx\nlea rdx, ds:0Fh[rdx*4]\nmov rcx, rdx\nand rdx, 0FFFFFFFFFFFFF000h\nsub rsi, rdx\nand rcx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rsi\njz short loc_132B\nloc_1316:\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\ncmp rsp, rsi\njnz short loc_1316\nloc_132B:\nand ecx, 0FFFh\nsub rsp, rcx\ntest rcx, rcx\njnz loc_1533\nloc_133D:\nlea r9, [rsp+1060h+var_105D]\nmov rdi, r9\nand r9, 0FFFFFFFFFFFFFFFCh\nshr rdi, 2\ntest eax, eax\njle loc_153E\nmov r11d, eax\nmov [rbp+var_48], r15\nmov r14d, eax\nmov r12d, eax\nmov [rbp+var_50], r10\nshr r11d, 2\nmov rcx, r9\nlea ebx, [rax-1]\nmov [rbp+var_58], r10\nshl r11, 4\nand r14d, 0FFFFFFFCh\nmov rsi, r10\nlea rdx, ds:0[r15*4]\nand r12d, 3\nlea r13, [r9+rdx]\nnop\nloc_1390:\ncmp ebx, 2\njbe loc_1520\nlea r10, [r11+rsi]\nmov r8, rsi\npxor xmm0, xmm0\nnop dword ptr [rax+00h]\nloc_13A8:\nmovdqu xmm2, xmmword ptr [r8]\nadd r8, 10h\npaddd xmm0, xmm2\ncmp r8, r10\njnz short loc_13A8\nmovdqa xmm1, xmm0\nmov r8d, r14d\npsrldq xmm1, 8\npaddd xmm0, xmm1\nmovdqa xmm1, xmm0\npsrldq xmm1, 4\npaddd xmm0, xmm1\ntest r12d, r12d\njz short loc_1412\nloc_13DC:\nmovsxd r10, r8d\nlea r15d, [r8+1]\nlea r10, [rsi+r10*4]\nmovd xmm1, dword ptr [r10]\npaddd xmm0, xmm1\ncmp eax, r15d\njle short loc_1412\nmovd xmm1, dword ptr [r10+4]\nadd r8d, 2\npaddd xmm0, xmm1\ncmp eax, r8d\njle short loc_1412\nmovd xmm1, dword ptr [r10+8]\npaddd xmm0, xmm1\nloc_1412:\nmovd dword ptr [rcx], xmm0\nadd rcx, 4\nadd rsi, rdx\ncmp rcx, r13\njnz loc_1390\nmov r10, [rbp+var_58]\nmov r15, [rbp+var_48]\nmov r8, [rbp+var_50]\nlea r14, [r10+rdx]\nmov r13, r10\nnop dword ptr [rax+00000000h]\nloc_1440:\nmov r11, r13\nxor esi, esi\nxor ebx, ebx\nnop word ptr [rax+rax+00000000h]\nloc_1450:\nmov r12d, esi\nadd esi, 1\nadd ebx, [r11]\nadd r11, rdx\ncmp eax, esi\njnz short loc_1450\nadd r13, 4\nmov [rcx], ebx\nadd rcx, 4\ncmp r13, r14\njnz short loc_1440\nlea ecx, [rsi+rsi]\nlea r13, [r15+1]\nadd rdx, 4\nxor eax, eax\nxor r11d, r11d\nnop\nloc_1480:\nmov ebx, eax\nadd r11d, [r8]\nadd eax, 1\nadd r8, rdx\ncmp r12d, ebx\njnz short loc_1480\nmovsxd rsi, esi\nmovsxd rax, ecx\nneg r13\nxor edx, edx\nimul rsi, r15\nmov [r9+rax*4], r11d\nlea r8d, [rcx+1]\nlea r11, ds:0[r13*4]\nlea rax, [r10+rsi*4-4]\nnop dword ptr [rax+00h]\nloc_14B8:\nsub r12d, 1\nadd edx, [rax]\nadd rax, r11\ncmp r12d, 0FFFFFFFFh\njnz short loc_14B8\nmovsxd r8, r8d\nadd ecx, 2\nmov [r9+r8*4], edx\ncmp ecx, 1\njle short loc_152C\nloc_14D6:\nsub ecx, 2\nmov edx, ds:dword_0[rdi*4]\nlea rax, [r9+4]\nlea rcx, [r9+rcx*4+8]\njmp short loc_14F9\nloc_14F0:\nadd rax, 4\ncmp rcx, rax\njz short loc_152C\nloc_14F9:\ncmp [rax], edx\njz short loc_14F0\nxor eax, eax\nloc_14FF:\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_1551\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1520:\nxor r8d, r8d\npxor xmm0, xmm0\njmp loc_13DC\nloc_152C:\nmov eax, 1\njmp short loc_14FF\nloc_1533:\nor [rsp+rcx+1060h+var_1068], 0\njmp loc_133D\nloc_153E:\nmov qword ptr ds:dword_0[rdi*4], 0\nmov ecx, 2\njmp short loc_14D6\nloc_1551:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12C0(int a1, const __m128i *a2)\n{\n __int64 v3; // rcx\n __int64 *v4; // rsi\n __int16 v5; // cx\n signed __int64 v6; // rcx\n void *v7; // rsp\n _QWORD *v8; // rcx\n const __m128i *v9; // rsi\n __int64 v10; // rdx\n const __m128i *v11; // r8\n __m128i v12; // xmm0\n __m128i v13; // xmm2\n signed int v14; // r8d\n __m128i v15; // xmm0\n __m128i v16; // xmm0\n unsigned int *v17; // r10\n const __m128i *v18; // r10\n __int64 v19; // r15\n const __m128i *v20; // r8\n __int32 *v21; // r14\n const __m128i *v22; // r13\n const __m128i *v23; // r11\n int v24; // esi\n int v25; // ebx\n int v26; // r12d\n int v27; // ecx\n __int64 v28; // rdx\n int v29; // eax\n int v30; // r11d\n int v31; // ebx\n int v32; // edx\n int v33; // r8d\n __int32 *v34; // rax\n int v35; // ecx\n _DWORD *v36; // rax\n char *v37; // rcx\n _QWORD v40[511]; // [rsp+8h] [rbp-1060h] BYREF\n __int64 v41; // [rsp+1008h] [rbp-60h] BYREF\n const __m128i *v42; // [rsp+1010h] [rbp-58h]\n const __m128i *v43; // [rsp+1018h] [rbp-50h]\n __int64 v44; // [rsp+1020h] [rbp-48h]\n unsigned __int64 v45; // [rsp+1030h] [rbp-38h]\n\n v45 = __readfsqword(0x28u);\n v3 = 4LL * (2 * a1 + 2) + 15;\n v4 = (__int64 *)((char *)&v41 - (v3 & 0xFFFFFFFFFFFFF000LL));\n v5 = v3 & 0xFFF0;\n if ( &v41 != v4 )\n {\n while ( v40 != v4 )\n ;\n }\n v6 = v5 & 0xFFF;\n v7 = alloca(v6);\n if ( v6 )\n *(_QWORD *)((char *)&v40[-1] + v6) = *(_QWORD *)((char *)&v40[-1] + v6);\n if ( a1 > 0 )\n {\n v44 = a1;\n v43 = a2;\n v8 = v40;\n v42 = a2;\n v9 = a2;\n v10 = 4LL * a1;\n while ( (unsigned int)(a1 - 1) > 2 )\n {\n v11 = v9;\n v12 = 0LL;\n do\n {\n v13 = _mm_loadu_si128(v11++);\n v12 = _mm_add_epi32(v12, v13);\n }\n while ( v11 != &v9[(unsigned int)a1 >> 2] );\n v14 = a1 & 0xFFFFFFFC;\n v15 = _mm_add_epi32(v12, _mm_srli_si128(v12, 8));\n v16 = _mm_add_epi32(v15, _mm_srli_si128(v15, 4));\n if ( (a1 & 3) != 0 )\n goto LABEL_11;\nLABEL_14:\n *(_DWORD *)v8 = _mm_cvtsi128_si32(v16);\n v8 = (_QWORD *)((char *)v8 + 4);\n v9 = (const __m128i *)((char *)v9 + v10);\n if ( v8 == (_QWORD *)((char *)v40 + 4 * a1) )\n {\n v18 = v42;\n v19 = v44;\n v20 = v43;\n v21 = &v42->m128i_i32[(unsigned __int64)v10 / 4];\n v22 = v42;\n do\n {\n v23 = v22;\n v24 = 0;\n v25 = 0;\n do\n {\n v26 = v24++;\n v25 += v23->m128i_i32[0];\n v23 = (const __m128i *)((char *)v23 + v10);\n }\n while ( a1 != v24 );\n v22 = (const __m128i *)((char *)v22 + 4);\n *(_DWORD *)v8 = v25;\n v8 = (_QWORD *)((char *)v8 + 4);\n }\n while ( v22 != (const __m128i *)v21 );\n v27 = 2 * v24;\n v28 = v10 + 4;\n v29 = 0;\n v30 = 0;\n do\n {\n v31 = v29;\n v30 += v20->m128i_i32[0];\n ++v29;\n v20 = (const __m128i *)((char *)v20 + v28);\n }\n while ( v26 != v31 );\n v32 = 0;\n LODWORD(v40[v27 / 2u]) = v30;\n v33 = v27 + 1;\n v34 = &v18->m128i_i32[v19 * v24 - 1];\n do\n {\n --v26;\n v32 += *v34;\n v34 += -v19 - 1;\n }\n while ( v26 != -1 );\n v35 = v27 + 2;\n *((_DWORD *)v40 + v33) = v32;\n if ( v35 > 1 )\n goto LABEL_24;\n return 1LL;\n }\n }\n v14 = 0;\n v16 = 0LL;\nLABEL_11:\n v17 = (unsigned int *)v9 + v14;\n v16 = _mm_add_epi32(v16, _mm_cvtsi32_si128(*v17));\n if ( a1 > v14 + 1 )\n {\n v16 = _mm_add_epi32(v16, _mm_cvtsi32_si128(v17[1]));\n if ( a1 > v14 + 2 )\n v16 = _mm_add_epi32(v16, _mm_cvtsi32_si128(v17[2]));\n }\n goto LABEL_14;\n }\n v40[0] = 0LL;\n v35 = 2;\nLABEL_24:\n v36 = (_DWORD *)v40 + 1;\n v37 = (char *)&v40[1] + 4 * (unsigned int)(v35 - 2);\n while ( *v36 == LODWORD(v40[0]) )\n {\n if ( v37 == (char *)++v36 )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12C0(int a1, const __m128i *a2) {\n long long v3;\n long long *v4;\n short v5;\n signed long long v6;\n void *v7;\n uint64_t *v8;\n const __m128i *v9;\n long long v10;\n const __m128i *v11;\n __m128i v12;\n __m128i v13;\n signed int v14;\n __m128i v15;\n __m128i v16;\n unsigned int *v17;\n const __m128i *v18;\n long long v19;\n const __m128i *v20;\n int *v21;\n const __m128i *v22;\n const __m128i *v23;\n int v24;\n int v25;\n int v26;\n int v27;\n long long v28;\n int v29;\n int v30;\n int v31;\n int v32;\n int v33;\n int *v34;\n int v35;\n uint32_t *v36;\n char *v37;\n uint64_t v40[511];\n long long v41;\n const __m128i *v42;\n const __m128i *v43;\n long long v44;\n unsigned long long v45;\n v45 = __readfsqword(40u);\n v3 = 4LL * (2 * a1 + 2) + 15;\n v4 = (long long *)((char *)&v41 - (v3 & 18446744073709547520LL));\n v5 = v3 & 65520;\n if (&v41 != v4) {\n while (v40 != v4)\n ;\n }\n v6 = v5 & 4095;\n v7 = alloca(v6);\n if (v6)\n *(uint64_t *)((char *)&v40[-1] + v6) = *(uint64_t *)((char *)&v40[-1] + v6);\n if (a1 > 0) {\n v44 = a1;\n v43 = a2;\n v8 = v40;\n v42 = a2;\n v9 = a2;\n v10 = 4LL * a1;\n while ((unsigned int)(a1 - 1) > 2) {\n v11 = v9;\n v12 = 0LL;\n do {\n v13 = _mm_loadu_si128(v11++);\n v12 = _mm_add_epi32(v12, v13);\n } while (v11 != &v9[(unsigned int)a1 >> 2]);\n v14 = a1 & 4294967292;\n v15 = _mm_add_epi32(v12, _mm_srli_si128(v12, 8));\n v16 = _mm_add_epi32(v15, _mm_srli_si128(v15, 4));\n if ((a1 & 3) != 0) goto LABEL_11;\n LABEL_14:\n *(uint32_t *)v8 = _mm_cvtsi128_si32(v16);\n v8 = (uint64_t *)((char *)v8 + 4);\n v9 = (const __m128i *)((char *)v9 + v10);\n if (v8 == (uint64_t *)((char *)v40 + 4 * a1)) {\n v18 = v42;\n v19 = v44;\n v20 = v43;\n v21 = &v42->m128i_i32[(unsigned long long)v10 / 4];\n v22 = v42;\n do {\n v23 = v22;\n v24 = 0;\n v25 = 0;\n do {\n v26 = v24++;\n v25 += v23->m128i_i32[0];\n v23 = (const __m128i *)((char *)v23 + v10);\n } while (a1 != v24);\n v22 = (const __m128i *)((char *)v22 + 4);\n *(uint32_t *)v8 = v25;\n v8 = (uint64_t *)((char *)v8 + 4);\n } while (v22 != (const __m128i *)v21);\n v27 = 2 * v24;\n v28 = v10 + 4;\n v29 = 0;\n v30 = 0;\n do {\n v31 = v29;\n v30 += v20->m128i_i32[0];\n ++v29;\n v20 = (const __m128i *)((char *)v20 + v28);\n } while (v26 != v31);\n v32 = 0;\n LODWORD(v40[v27 / 2u]) = v30;\n v33 = v27 + 1;\n v34 = &v18->m128i_i32[v19 * v24 - 1];\n do {\n --v26;\n v32 += *v34;\n v34 += -v19 - 1;\n } while (v26 != -1);\n v35 = v27 + 2;\n *((uint32_t *)v40 + v33) = v32;\n if (v35 > 1) goto LABEL_24;\n return 1LL;\n }\n }\n v14 = 0;\n v16 = 0LL;\n LABEL_11:\n v17 = (unsigned int *)v9 + v14;\n v16 = _mm_add_epi32(v16, _mm_cvtsi32_si128(*v17));\n if (a1 > v14 + 1) {\n v16 = _mm_add_epi32(v16, _mm_cvtsi32_si128(v17[1]));\n if (a1 > v14 + 2) v16 = _mm_add_epi32(v16, _mm_cvtsi32_si128(v17[2]));\n }\n goto LABEL_14;\n }\n v40[0] = 0LL;\n v35 = 2;\nLABEL_24:\n v36 = (uint32_t *)v40 + 1;\n v37 = (char *)&v40[1] + 4 * (unsigned int)(v35 - 2);\n while (*v36 == LODWORD(v40[0])) {\n if (v37 == (char *)++v36) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(int a1, const __m128i *a2) {\n long long v3;\n long long *v4;\n short v5;\n signed long long v6;\n void *v7;\n uint64_t *v8;\n const __m128i *v9;\n long long v10;\n const __m128i *v11;\n __m128i v12;\n __m128i v13;\n signed int v14;\n __m128i v15;\n __m128i v16;\n unsigned int *v17;\n const __m128i *v18;\n long long v19;\n const __m128i *v20;\n int *v21;\n const __m128i *v22;\n const __m128i *v23;\n int v24;\n int v25;\n int v26;\n int v27;\n long long v28;\n int v29;\n int v30;\n int v31;\n int v32;\n int v33;\n int *v34;\n int v35;\n uint32_t *v36;\n char *v37;\n uint64_t v40[511];\n long long v41;\n const __m128i *v42;\n const __m128i *v43;\n long long v44;\n unsigned long long v45;\n v45 = __readfsqword(40u);\n v3 = 4LL * (2 * a1 + 2) + 15;\n v4 = (long long *)((char *)&v41 - (v3 & 18446744073709547520LL));\n v5 = v3 & 65520;\n if (&v41 != v4) {\n while (v40 != v4)\n ;\n }\n v6 = v5 & 4095;\n v7 = alloca(v6);\n if (v6)\n *(uint64_t *)((char *)&v40[-1] + v6) = *(uint64_t *)((char *)&v40[-1] + v6);\n if (a1 > 0) {\n v44 = a1;\n v43 = a2;\n v8 = v40;\n v42 = a2;\n v9 = a2;\n v10 = 4LL * a1;\n while ((unsigned int)(a1 - 1) > 2) {\n v11 = v9;\n v12 = 0LL;\n do {\n v13 = _mm_loadu_si128(v11++);\n v12 = _mm_add_epi32(v12, v13);\n } while (v11 != &v9[(unsigned int)a1 >> 2]);\n v14 = a1 & 4294967292;\n v15 = _mm_add_epi32(v12, _mm_srli_si128(v12, 8));\n v16 = _mm_add_epi32(v15, _mm_srli_si128(v15, 4));\n if ((a1 & 3) != 0) goto LABEL_11;\n LABEL_14:\n *(uint32_t *)v8 = _mm_cvtsi128_si32(v16);\n v8 = (uint64_t *)((char *)v8 + 4);\n v9 = (const __m128i *)((char *)v9 + v10);\n if (v8 == (uint64_t *)((char *)v40 + 4 * a1)) {\n v18 = v42;\n v19 = v44;\n v20 = v43;\n v21 = &v42->m128i_i32[(unsigned long long)v10 / 4];\n v22 = v42;\n do {\n v23 = v22;\n v24 = 0;\n v25 = 0;\n do {\n v26 = v24++;\n v25 += v23->m128i_i32[0];\n v23 = (const __m128i *)((char *)v23 + v10);\n } while (a1 != v24);\n v22 = (const __m128i *)((char *)v22 + 4);\n *(uint32_t *)v8 = v25;\n v8 = (uint64_t *)((char *)v8 + 4);\n } while (v22 != (const __m128i *)v21);\n v27 = 2 * v24;\n v28 = v10 + 4;\n v29 = 0;\n v30 = 0;\n do {\n v31 = v29;\n v30 += v20->m128i_i32[0];\n ++v29;\n v20 = (const __m128i *)((char *)v20 + v28);\n } while (v26 != v31);\n v32 = 0;\n LODWORD(v40[v27 / 2u]) = v30;\n v33 = v27 + 1;\n v34 = &v18->m128i_i32[v19 * v24 - 1];\n do {\n --v26;\n v32 += *v34;\n v34 += -v19 - 1;\n } while (v26 != -1);\n v35 = v27 + 2;\n *((uint32_t *)v40 + v33) = v32;\n if (v35 > 1) goto LABEL_24;\n return 1LL;\n }\n }\n v14 = 0;\n v16 = 0LL;\n LABEL_11:\n v17 = (unsigned int *)v9 + v14;\n v16 = _mm_add_epi32(v16, _mm_cvtsi32_si128(*v17));\n if (a1 > v14 + 1) {\n v16 = _mm_add_epi32(v16, _mm_cvtsi32_si128(v17[1]));\n if (a1 > v14 + 2) v16 = _mm_add_epi32(v16, _mm_cvtsi32_si128(v17[2]));\n }\n goto LABEL_14;\n }\n v40[0] = 0LL;\n v35 = 2;\nLABEL_24:\n v36 = (uint32_t *)v40 + 1;\n v37 = (char *)&v40[1] + 4 * (unsigned int)(v35 - 2);\n while (*v36 == LODWORD(v40[0])) {\n if (v37 == (char *)++v36) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 130, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n\n\n", + "func": "int* func0(int nums[], int size) {\n int keys[size];\n int counts[size];\n int unique = 0;\n for (int i = 0; i < size; i++) {\n int num = nums[i];\n int found = 0;\n for (int j = 0; j < unique; j++) {\n if (keys[j] == num) {\n counts[j]++;\n found = 1;\n break;\n }\n }\n if (!found) {\n keys[unique] = num;\n counts[unique] = 1;\n unique++;\n }\n }\n int max_index = 0;\n for (int i = 1; i < unique; i++) {\n if (counts[i] > counts[max_index]) {\n max_index = i;\n }\n }\n static int result[2];\n result[0] = keys[max_index];\n result[1] = counts[max_index];\n return result;\n}", + "test": "int main(){\n\n int nums1[] = {2,3,8,4,7,9,8,2,6,5,1,6,1,2,3,2,4,6,9,1,2};\n\n int size1 = sizeof(nums1)/sizeof(nums1[0]);\n\n int *result;\n\n result = func0(nums1, size1);\n\n assert(result[0] == 2 && result[1] == 5);\n\n\n\n int nums2[] = {2,3,8,4,7,9,8,7,9,15,14,10,12,13,16,16,18};\n\n int size2 = sizeof(nums2)/sizeof(nums2[0]);\n\n result = func0(nums2, size2);\n\n assert(result[0]== 8 && result[1] == 2);\n\n\n\n int nums3[] = {10,20,20,30,40,90,80,50,30,20,50,10};\n\n int size3 = sizeof(nums3)/sizeof(nums3[0]);\n\n result = func0(nums3, size3);\n\n assert(result[0] == 20 && result[1] == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r13\npush %r12\npush %rbx\nsub $0x68,%rsp\nmov %rdi,-0x78(%rbp)\nmov %esi,-0x7c(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x28(%rbp)\nxor %eax,%eax\nmov %rsp,%rax\nmov %rax,%rsi\nmov -0x7c(%rbp),%eax\nmovslq %eax,%rdx\nsub $0x1,%rdx\nmov %rdx,-0x48(%rbp)\nmovslq %eax,%rdx\nmov %rdx,%r12\nmov $0x0,%r13d\nmovslq %eax,%rdx\nmov %rdx,%r10\nmov $0x0,%r11d\ncltq\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%edi\nmov $0x0,%edx\ndiv %rdi\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rdi\nsub %rdx,%rdi\nmov %rdi,%rdx\ncmp %rdx,%rsp\nje 120d \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11f6 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 1237 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x40(%rbp)\nmov -0x7c(%rbp),%eax\nmovslq %eax,%rdx\nsub $0x1,%rdx\nmov %rdx,-0x38(%rbp)\nmovslq %eax,%rdx\nmov %rdx,%r8\nmov $0x0,%r9d\nmovslq %eax,%rdx\nmov %rdx,%rcx\nmov $0x0,%ebx\ncltq\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%ebx\nmov $0x0,%edx\ndiv %rbx\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rbx\nsub %rdx,%rbx\nmov %rbx,%rdx\ncmp %rdx,%rsp\nje 12c0 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 12a9 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 12ea \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x30(%rbp)\nmovl $0x0,-0x50(%rbp)\nmovl $0x0,-0x54(%rbp)\njmpq 13ac \nmov -0x54(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x78(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x4c(%rbp)\nmovl $0x0,-0x58(%rbp)\nmovl $0x0,-0x5c(%rbp)\njmp 1375 \nmov -0x40(%rbp),%rax\nmov -0x5c(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\ncmp %eax,-0x4c(%rbp)\njne 1371 \nmov -0x30(%rbp),%rax\nmov -0x5c(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nlea 0x1(%rax),%ecx\nmov -0x30(%rbp),%rax\nmov -0x5c(%rbp),%edx\nmovslq %edx,%rdx\nmov %ecx,(%rax,%rdx,4)\nmovl $0x1,-0x58(%rbp)\njmp 137d \naddl $0x1,-0x5c(%rbp)\nmov -0x5c(%rbp),%eax\ncmp -0x50(%rbp),%eax\njl 1339 \ncmpl $0x0,-0x58(%rbp)\njne 13a8 \nmov -0x40(%rbp),%rax\nmov -0x50(%rbp),%edx\nmovslq %edx,%rdx\nmov -0x4c(%rbp),%ecx\nmov %ecx,(%rax,%rdx,4)\nmov -0x30(%rbp),%rax\nmov -0x50(%rbp),%edx\nmovslq %edx,%rdx\nmovl $0x1,(%rax,%rdx,4)\naddl $0x1,-0x50(%rbp)\naddl $0x1,-0x54(%rbp)\nmov -0x54(%rbp),%eax\ncmp -0x7c(%rbp),%eax\njl 1310 \nmovl $0x0,-0x60(%rbp)\nmovl $0x1,-0x64(%rbp)\njmp 13f0 \nmov -0x30(%rbp),%rax\nmov -0x64(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%ecx\nmov -0x30(%rbp),%rax\nmov -0x60(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\ncmp %eax,%ecx\njle 13ec \nmov -0x64(%rbp),%eax\nmov %eax,-0x60(%rbp)\naddl $0x1,-0x64(%rbp)\nmov -0x64(%rbp),%eax\ncmp -0x50(%rbp),%eax\njl 13c8 \nmov -0x40(%rbp),%rax\nmov -0x60(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nmov %eax,0x2c0d(%rip)\nmov -0x30(%rbp),%rax\nmov -0x60(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nmov %eax,0x2bfe(%rip)\nlea 0x2bf3(%rip),%rax\nmov %rsi,%rsp\nmov -0x28(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 143c \ncallq 1060 <__stack_chk_fail@plt>\nlea -0x18(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 60h\nmov [rbp+var_58], rdi\nmov [rbp+var_5C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov eax, [rbp+var_5C]\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_28], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11D6:\ncmp rsp, rdx\njz short loc_11ED\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\njmp short loc_11D6\nloc_11ED:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1217\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1217:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_20], rax\nmov eax, [rbp+var_5C]\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_126F:\ncmp rsp, rdx\njz short loc_1286\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\njmp short loc_126F\nloc_1286:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_12B0\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_12B0:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov [rbp+var_44], 0\nmov [rbp+var_40], 0\njmp loc_1372\nloc_12D6:\nmov eax, [rbp+var_40]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_2C], eax\nmov [rbp+var_3C], 0\nmov [rbp+var_38], 0\njmp short loc_133B\nloc_12FF:\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ncmp [rbp+var_2C], eax\njnz short loc_1337\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nlea ecx, [rax+1]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nmov [rbp+var_3C], 1\njmp short loc_1343\nloc_1337:\nadd [rbp+var_38], 1\nloc_133B:\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_44]\njl short loc_12FF\nloc_1343:\ncmp [rbp+var_3C], 0\njnz short loc_136E\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_44]\nmovsxd rdx, edx\nmov ecx, [rbp+var_2C]\nmov [rax+rdx*4], ecx\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_44]\nmovsxd rdx, edx\nmov dword ptr [rax+rdx*4], 1\nadd [rbp+var_44], 1\nloc_136E:\nadd [rbp+var_40], 1\nloc_1372:\nmov eax, [rbp+var_40]\ncmp eax, [rbp+var_5C]\njl loc_12D6\nmov [rbp+var_34], 0\nmov [rbp+var_30], 1\njmp short loc_13B6\nloc_138E:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_30]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_34]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ncmp ecx, eax\njle short loc_13B2\nmov eax, [rbp+var_30]\nmov [rbp+var_34], eax\nloc_13B2:\nadd [rbp+var_30], 1\nloc_13B6:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_44]\njl short loc_138E\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_34]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov cs:result_1, eax\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_34]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov cs:dword_401C, eax\nlea rax, result_1\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1402\ncall ___stack_chk_fail\nlocret_1402:\nleave\nretn", + "ida_pseudo": "int *__fastcall func0(__int64 a1, int a2)\n{\n unsigned __int64 v2; // rax\n void *v3; // rsp\n unsigned __int64 v4; // rax\n void *v5; // rsp\n _BYTE v7[4]; // [rsp+8h] [rbp-60h] BYREF\n int v8; // [rsp+Ch] [rbp-5Ch]\n __int64 v9; // [rsp+10h] [rbp-58h]\n int v10; // [rsp+24h] [rbp-44h]\n int i; // [rsp+28h] [rbp-40h]\n int v12; // [rsp+2Ch] [rbp-3Ch]\n int j; // [rsp+30h] [rbp-38h]\n int v14; // [rsp+34h] [rbp-34h]\n int k; // [rsp+38h] [rbp-30h]\n int v16; // [rsp+3Ch] [rbp-2Ch]\n __int64 v17; // [rsp+40h] [rbp-28h]\n _BYTE *v18; // [rsp+48h] [rbp-20h]\n __int64 v19; // [rsp+50h] [rbp-18h]\n _BYTE *v20; // [rsp+58h] [rbp-10h]\n unsigned __int64 v21; // [rsp+60h] [rbp-8h]\n\n v9 = a1;\n v8 = a2;\n v21 = __readfsqword(0x28u);\n v17 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 0x10uLL);\n while ( v7 != &v7[-(v2 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = alloca(v2 & 0xFFF);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)&v7[(v2 & 0xFFF) - 8] = *(_QWORD *)&v7[(v2 & 0xFFF) - 8];\n v18 = v7;\n v19 = v8 - 1LL;\n v4 = 16 * ((4LL * v8 + 15) / 0x10uLL);\n while ( v7 != &v7[-(v4 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v5 = alloca(v4 & 0xFFF);\n if ( (v4 & 0xFFF) != 0 )\n *(_QWORD *)&v7[(v4 & 0xFFF) - 8] = *(_QWORD *)&v7[(v4 & 0xFFF) - 8];\n v20 = v7;\n v10 = 0;\n for ( i = 0; i < v8; ++i )\n {\n v16 = *(_DWORD *)(4LL * i + v9);\n v12 = 0;\n for ( j = 0; j < v10; ++j )\n {\n if ( v16 == *(_DWORD *)&v18[4 * j] )\n {\n ++*(_DWORD *)&v20[4 * j];\n v12 = 1;\n break;\n }\n }\n if ( !v12 )\n {\n *(_DWORD *)&v18[4 * v10] = v16;\n *(_DWORD *)&v20[4 * v10++] = 1;\n }\n }\n v14 = 0;\n for ( k = 1; k < v10; ++k )\n {\n if ( *(_DWORD *)&v20[4 * k] > *(_DWORD *)&v20[4 * v14] )\n v14 = k;\n }\n result_1 = *(_DWORD *)&v18[4 * v14];\n dword_401C = *(_DWORD *)&v20[4 * v14];\n return &result_1;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 60h\nmov [rbp+var_58], rdi\nmov [rbp+var_5C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov eax, [rbp+var_5C]\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_28], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11D6:\ncmp rsp, rdx\njz short loc_11ED\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\njmp short loc_11D6\nloc_11ED:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1217\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1217:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_20], rax\nmov eax, [rbp+var_5C]\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_126F:\ncmp rsp, rdx\njz short loc_1286\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\njmp short loc_126F\nloc_1286:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_12B0\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_12B0:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov [rbp+var_44], 0\nmov [rbp+var_40], 0\njmp loc_1372\nloc_12D6:\nmov eax, [rbp+var_40]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_2C], eax\nmov [rbp+var_3C], 0\nmov [rbp+var_38], 0\njmp short loc_133B\nloc_12FF:\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ncmp [rbp+var_2C], eax\njnz short loc_1337\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nlea ecx, [rax+1]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nmov [rbp+var_3C], 1\njmp short loc_1343\nloc_1337:\nadd [rbp+var_38], 1\nloc_133B:\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_44]\njl short loc_12FF\nloc_1343:\ncmp [rbp+var_3C], 0\njnz short loc_136E\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_44]\nmovsxd rdx, edx\nmov ecx, [rbp+var_2C]\nmov [rax+rdx*4], ecx\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_44]\nmovsxd rdx, edx\nmov dword ptr [rax+rdx*4], 1\nadd [rbp+var_44], 1\nloc_136E:\nadd [rbp+var_40], 1\nloc_1372:\nmov eax, [rbp+var_40]\ncmp eax, [rbp+var_5C]\njl loc_12D6\nmov [rbp+var_34], 0\nmov [rbp+var_30], 1\njmp short loc_13B6\nloc_138E:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_30]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_34]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ncmp ecx, eax\njle short loc_13B2\nmov eax, [rbp+var_30]\nmov [rbp+var_34], eax\nloc_13B2:\nadd [rbp+var_30], 1\nloc_13B6:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_44]\njl short loc_138E\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_34]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov cs:dword_4018, eax\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_34]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov cs:dword_401C, eax\nlea rax, dword_4018\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1402\ncall ___stack_chk_fail\nlocret_1402:\nleave\nretn", + "ida_strip_pseudo": "int *__fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned __int64 v2; // rax\n void *v3; // rsp\n unsigned __int64 v4; // rax\n void *v5; // rsp\n _BYTE v7[4]; // [rsp+8h] [rbp-60h] BYREF\n int v8; // [rsp+Ch] [rbp-5Ch]\n __int64 v9; // [rsp+10h] [rbp-58h]\n int v10; // [rsp+24h] [rbp-44h]\n int i; // [rsp+28h] [rbp-40h]\n int v12; // [rsp+2Ch] [rbp-3Ch]\n int j; // [rsp+30h] [rbp-38h]\n int v14; // [rsp+34h] [rbp-34h]\n int k; // [rsp+38h] [rbp-30h]\n int v16; // [rsp+3Ch] [rbp-2Ch]\n __int64 v17; // [rsp+40h] [rbp-28h]\n _BYTE *v18; // [rsp+48h] [rbp-20h]\n __int64 v19; // [rsp+50h] [rbp-18h]\n _BYTE *v20; // [rsp+58h] [rbp-10h]\n unsigned __int64 v21; // [rsp+60h] [rbp-8h]\n\n v9 = a1;\n v8 = a2;\n v21 = __readfsqword(0x28u);\n v17 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 0x10uLL);\n while ( v7 != &v7[-(v2 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = alloca(v2 & 0xFFF);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)&v7[(v2 & 0xFFF) - 8] = *(_QWORD *)&v7[(v2 & 0xFFF) - 8];\n v18 = v7;\n v19 = v8 - 1LL;\n v4 = 16 * ((4LL * v8 + 15) / 0x10uLL);\n while ( v7 != &v7[-(v4 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v5 = alloca(v4 & 0xFFF);\n if ( (v4 & 0xFFF) != 0 )\n *(_QWORD *)&v7[(v4 & 0xFFF) - 8] = *(_QWORD *)&v7[(v4 & 0xFFF) - 8];\n v20 = v7;\n v10 = 0;\n for ( i = 0; i < v8; ++i )\n {\n v16 = *(_DWORD *)(4LL * i + v9);\n v12 = 0;\n for ( j = 0; j < v10; ++j )\n {\n if ( v16 == *(_DWORD *)&v18[4 * j] )\n {\n ++*(_DWORD *)&v20[4 * j];\n v12 = 1;\n break;\n }\n }\n if ( !v12 )\n {\n *(_DWORD *)&v18[4 * v10] = v16;\n *(_DWORD *)&v20[4 * v10++] = 1;\n }\n }\n v14 = 0;\n for ( k = 1; k < v10; ++k )\n {\n if ( *(_DWORD *)&v20[4 * k] > *(_DWORD *)&v20[4 * v14] )\n v14 = k;\n }\n dword_4018 = *(_DWORD *)&v18[4 * v14];\n dword_401C = *(_DWORD *)&v20[4 * v14];\n return &dword_4018;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "int *sub_1169(long long a1, int a2) {\n unsigned long long v2;\n void *v3;\n unsigned long long v4;\n void *v5;\n uint8_t v7[4];\n int v8;\n long long v9;\n int v10;\n int i;\n int v12;\n int j;\n int v14;\n int k;\n int v16;\n long long v17;\n uint8_t *v18;\n long long v19;\n uint8_t *v20;\n unsigned long long v21;\n v9 = a1;\n v8 = a2;\n v21 = __readfsqword(40u);\n v17 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 16uLL);\n while (v7 != &v7[-(v2 & 18446744073709547520LL)])\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)&v7[(v2 & 4095) - 8] = *(uint64_t *)&v7[(v2 & 4095) - 8];\n v18 = v7;\n v19 = v8 - 1LL;\n v4 = 16 * ((4LL * v8 + 15) / 16uLL);\n while (v7 != &v7[-(v4 & 18446744073709547520LL)])\n ;\n v5 = alloca(v4 & 4095);\n if ((v4 & 4095) != 0)\n *(uint64_t *)&v7[(v4 & 4095) - 8] = *(uint64_t *)&v7[(v4 & 4095) - 8];\n v20 = v7;\n v10 = 0;\n for (i = 0; i < v8; ++i) {\n v16 = *(uint32_t *)(4LL * i + v9);\n v12 = 0;\n for (j = 0; j < v10; ++j) {\n if (v16 == *(uint32_t *)&v18[4 * j]) {\n ++*(uint32_t *)&v20[4 * j];\n v12 = 1;\n break;\n }\n }\n if (!v12) {\n *(uint32_t *)&v18[4 * v10] = v16;\n *(uint32_t *)&v20[4 * v10++] = 1;\n }\n }\n v14 = 0;\n for (k = 1; k < v10; ++k) {\n if (*(uint32_t *)&v20[4 * k] > *(uint32_t *)&v20[4 * v14]) v14 = k;\n }\n dword_4018 = *(uint32_t *)&v18[4 * v14];\n dword_401C = *(uint32_t *)&v20[4 * v14];\n return &dword_4018;\n}", + "ida_pseudo_norm": "int *func0(long long a1, int a2) {\n unsigned long long v2;\n void *v3;\n unsigned long long v4;\n void *v5;\n uint8_t v7[4];\n int v8;\n long long v9;\n int v10;\n int i;\n int v12;\n int j;\n int v14;\n int k;\n int v16;\n long long v17;\n uint8_t *v18;\n long long v19;\n uint8_t *v20;\n unsigned long long v21;\n v9 = a1;\n v8 = a2;\n v21 = __readfsqword(40u);\n v17 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 16uLL);\n while (v7 != &v7[-(v2 & 18446744073709547520LL)])\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)&v7[(v2 & 4095) - 8] = *(uint64_t *)&v7[(v2 & 4095) - 8];\n v18 = v7;\n v19 = v8 - 1LL;\n v4 = 16 * ((4LL * v8 + 15) / 16uLL);\n while (v7 != &v7[-(v4 & 18446744073709547520LL)])\n ;\n v5 = alloca(v4 & 4095);\n if ((v4 & 4095) != 0)\n *(uint64_t *)&v7[(v4 & 4095) - 8] = *(uint64_t *)&v7[(v4 & 4095) - 8];\n v20 = v7;\n v10 = 0;\n for (i = 0; i < v8; ++i) {\n v16 = *(uint32_t *)(4LL * i + v9);\n v12 = 0;\n for (j = 0; j < v10; ++j) {\n if (v16 == *(uint32_t *)&v18[4 * j]) {\n ++*(uint32_t *)&v20[4 * j];\n v12 = 1;\n break;\n }\n }\n if (!v12) {\n *(uint32_t *)&v18[4 * v10] = v16;\n *(uint32_t *)&v20[4 * v10++] = 1;\n }\n }\n v14 = 0;\n for (k = 1; k < v10; ++k) {\n if (*(uint32_t *)&v20[4 * k] > *(uint32_t *)&v20[4 * v14]) v14 = k;\n }\n result_1 = *(uint32_t *)&v18[4 * v14];\n dword_401C = *(uint32_t *)&v20[4 * v14];\n return &result_1;\n}" + }, + { + "index": 130, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n\n\n", + "func": "int* func0(int nums[], int size) {\n int keys[size];\n int counts[size];\n int unique = 0;\n for (int i = 0; i < size; i++) {\n int num = nums[i];\n int found = 0;\n for (int j = 0; j < unique; j++) {\n if (keys[j] == num) {\n counts[j]++;\n found = 1;\n break;\n }\n }\n if (!found) {\n keys[unique] = num;\n counts[unique] = 1;\n unique++;\n }\n }\n int max_index = 0;\n for (int i = 1; i < unique; i++) {\n if (counts[i] > counts[max_index]) {\n max_index = i;\n }\n }\n static int result[2];\n result[0] = keys[max_index];\n result[1] = counts[max_index];\n return result;\n}", + "test": "int main(){\n\n int nums1[] = {2,3,8,4,7,9,8,2,6,5,1,6,1,2,3,2,4,6,9,1,2};\n\n int size1 = sizeof(nums1)/sizeof(nums1[0]);\n\n int *result;\n\n result = func0(nums1, size1);\n\n assert(result[0] == 2 && result[1] == 5);\n\n\n\n int nums2[] = {2,3,8,4,7,9,8,7,9,15,14,10,12,13,16,16,18};\n\n int size2 = sizeof(nums2)/sizeof(nums2[0]);\n\n result = func0(nums2, size2);\n\n assert(result[0]== 8 && result[1] == 2);\n\n\n\n int nums3[] = {10,20,20,30,40,90,80,50,30,20,50,10};\n\n int size3 = sizeof(nums3)/sizeof(nums3[0]);\n\n result = func0(nums3, size3);\n\n assert(result[0] == 20 && result[1] == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r13\npush %r12\npush %rbx\nsub $0x18,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x28(%rbp)\nxor %eax,%eax\nmovslq %esi,%rax\nshl $0x2,%rax\nlea 0xf(%rax),%rdx\nmov %rdx,%rcx\nand $0xfffffffffffffff0,%rcx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rbx\nsub %rdx,%rbx\nmov %rbx,%rdx\ncmp %rdx,%rsp\nje 11c2 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11ab \nmov %rcx,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\nje 11d9 \norq $0x0,-0x8(%rsp,%rdx,1)\nmov %rsp,%r10\nmov %r10,%r8\nadd $0xf,%rax\nmov %rax,%rdx\nand $0xfffffffffffffff0,%rdx\nand $0xfffffffffffff000,%rax\nmov %rsp,%rbx\nsub %rax,%rbx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 1210 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11f9 \nmov %rdx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 1226 \norq $0x0,-0x8(%rsp,%rax,1)\nmov %rsp,%r11\nmov %r11,%rbx\ntest %esi,%esi\njle 12f3 \nmov %rdi,%r9\nlea -0x1(%rsi),%eax\nlea 0x4(%rdi,%rax,4),%r12\nmov $0x0,%edi\nmov $0x0,%r13d\njmp 1278 \nmov %rdx,%rax\ncmp %ecx,(%r8,%rax,4)\nje 1287 \nlea 0x1(%rax),%rdx\ncmp %rsi,%rax\njne 124c \nmovslq %edi,%rax\nmov %ecx,(%r8,%rax,4)\nmovl $0x1,(%rbx,%rax,4)\nadd $0x1,%edi\nadd $0x4,%r9\ncmp %r12,%r9\nje 1290 \nmov (%r9),%ecx\ntest %edi,%edi\njle 125e \nlea -0x1(%rdi),%esi\nmov %r13,%rax\njmp 124f \nmovslq %eax,%rdx\naddl $0x1,(%rbx,%rdx,4)\njmp 126f \ncmp $0x1,%edi\njle 12fa \nlea -0x2(%rdi),%esi\nadd $0x2,%rsi\nmov $0x1,%eax\nmov $0x0,%edx\nmovslq %edx,%rcx\nmov (%rbx,%rcx,4),%edi\ncmp %edi,(%rbx,%rax,4)\ncmovg %eax,%edx\nadd $0x1,%rax\ncmp %rsi,%rax\njne 12a6 \nmovslq %edx,%rdx\nmov (%r10,%rdx,4),%eax\nmov %eax,0x2d50(%rip)\nmov (%r11,%rdx,4),%eax\nmov %eax,0x2d4a(%rip)\nmov -0x28(%rbp),%rax\nxor %fs:0x28,%rax\njne 1301 \nlea 0x2d30(%rip),%rax\nlea -0x18(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %rbp\nretq\nmov $0x0,%edx\njmp 12bb \nmov $0x0,%edx\njmp 12bb \ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov r10, rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmovsxd rax, esi\nshl rax, 2\nlea rdx, [rax+0Fh]\nmov rdi, rdx\nand rdi, 0FFFFFFFFFFFFFFF0h\nand rdx, 0FFFFFFFFFFFFF000h\nmov rcx, rsp\nsub rcx, rdx\nloc_11A6:\ncmp rsp, rcx\njz short loc_11BD\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11A6\nloc_11BD:\nmov rdx, rdi\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njz short loc_11D4\nor [rsp+rdx+10h+var_18], 0\nloc_11D4:\nmov rcx, rsp\nlea rdx, [rax+0Fh]\nmov rdi, rdx\nand rdi, 0FFFFFFFFFFFFFFF0h\nand rdx, 0FFFFFFFFFFFFF000h\nmov r8, rsp\nsub r8, rdx\nloc_11EF:\ncmp rsp, r8\njz short loc_1206\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11EF\nloc_1206:\nmov rdx, rdi\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njz short loc_121D\nor [rsp+rdx+10h+var_18], 0\nloc_121D:\nmov r9, rsp\ntest esi, esi\njle loc_12CD\nmov r8, r10\nadd r10, rax\nmov edi, 0\njmp short loc_1258\nloc_1235:\ncdqe\nadd dword ptr [r9+rax*4], 1\njmp short loc_124F\nloc_123E:\nmovsxd rax, edi\nmov [rcx+rax*4], edx\nmov dword ptr [r9+rax*4], 1\nadd edi, 1\nloc_124F:\nadd r8, 4\ncmp r8, r10\njz short loc_1277\nloc_1258:\nmov edx, [r8]\ntest edi, edi\njle short loc_123E\nmovsxd rsi, edi\nmov eax, 0\nloc_1267:\ncmp [rcx+rax*4], edx\njz short loc_1235\nadd rax, 1\ncmp rax, rsi\njnz short loc_1267\njmp short loc_123E\nloc_1277:\ncmp edi, 1\njle short loc_12D4\nmov edi, edi\nmov eax, 1\nmov edx, 0\nloc_1288:\nmovsxd rsi, edx\nmov esi, [r9+rsi*4]\ncmp [r9+rax*4], esi\ncmovg edx, eax\nadd rax, 1\ncmp rax, rdi\njnz short loc_1288\nloc_129F:\nmovsxd rdx, edx\nmov eax, [rcx+rdx*4]\nmov cs:result_1, eax\nmov eax, [r9+rdx*4]\nmov cs:dword_401C, eax\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njnz short loc_12DB\nlea rax, result_1\nleave\nretn\nloc_12CD:\nmov edx, 0\njmp short loc_129F\nloc_12D4:\nmov edx, 0\njmp short loc_129F\nloc_12DB:\ncall ___stack_chk_fail", + "ida_pseudo": "int *__fastcall func0(int *a1, int a2)\n{\n __int64 v2; // rax\n signed __int64 v3; // rdx\n void *v4; // rsp\n signed __int64 v5; // rdx\n void *v6; // rsp\n int *v7; // r8\n int *v8; // r10\n int v9; // edi\n int v10; // edx\n __int64 v11; // rax\n __int64 v12; // rax\n int v13; // edx\n _DWORD v16[2]; // [rsp+8h] [rbp-10h] BYREF\n unsigned __int64 v17; // [rsp+10h] [rbp-8h]\n\n v17 = __readfsqword(0x28u);\n v2 = 4LL * a2;\n while ( v16 != (_DWORD *)((char *)v16 - ((v2 + 15) & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v3 = ((_WORD)v2 + 15) & 0xFF0;\n v4 = alloca(v3);\n if ( (((_WORD)v2 + 15) & 0xFF0) != 0 )\n *(_QWORD *)((char *)&v16[-2] + v3) = *(_QWORD *)((char *)&v16[-2] + v3);\n while ( v16 != (_DWORD *)((char *)v16 - ((v2 + 15) & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v5 = ((_WORD)v2 + 15) & 0xFF0;\n v6 = alloca(v5);\n if ( (((_WORD)v2 + 15) & 0xFF0) != 0 )\n *(_QWORD *)((char *)&v16[-2] + v5) = *(_QWORD *)((char *)&v16[-2] + v5);\n if ( a2 <= 0 )\n {\n v13 = 0;\n }\n else\n {\n v7 = a1;\n v8 = &a1[(unsigned __int64)v2 / 4];\n v9 = 0;\n do\n {\n v10 = *v7;\n if ( v9 <= 0 )\n {\nLABEL_11:\n v16[v9] = v10;\n v16[v9++] = 1;\n }\n else\n {\n v11 = 0LL;\n while ( v16[v11] != v10 )\n {\n if ( ++v11 == v9 )\n goto LABEL_11;\n }\n ++v16[(int)v11];\n }\n ++v7;\n }\n while ( v7 != v8 );\n if ( v9 <= 1 )\n {\n v13 = 0;\n }\n else\n {\n v12 = 1LL;\n v13 = 0;\n do\n {\n if ( v16[v12] > v16[v13] )\n v13 = v12;\n ++v12;\n }\n while ( v12 != v9 );\n }\n }\n result_1 = v16[v13];\n dword_401C = v16[v13];\n return &result_1;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov r10, rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmovsxd rax, esi\nshl rax, 2\nlea rdx, [rax+0Fh]\nmov rdi, rdx\nand rdi, 0FFFFFFFFFFFFFFF0h\nand rdx, 0FFFFFFFFFFFFF000h\nmov rcx, rsp\nsub rcx, rdx\nloc_11A6:\ncmp rsp, rcx\njz short loc_11BD\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11A6\nloc_11BD:\nmov rdx, rdi\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njz short loc_11D4\nor [rsp+rdx+10h+var_18], 0\nloc_11D4:\nmov rcx, rsp\nlea rdx, [rax+0Fh]\nmov rdi, rdx\nand rdi, 0FFFFFFFFFFFFFFF0h\nand rdx, 0FFFFFFFFFFFFF000h\nmov r8, rsp\nsub r8, rdx\nloc_11EF:\ncmp rsp, r8\njz short loc_1206\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11EF\nloc_1206:\nmov rdx, rdi\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njz short loc_121D\nor [rsp+rdx+10h+var_18], 0\nloc_121D:\nmov r9, rsp\ntest esi, esi\njle loc_12CD\nmov r8, r10\nadd r10, rax\nmov edi, 0\njmp short loc_1258\nloc_1235:\ncdqe\nadd dword ptr [r9+rax*4], 1\njmp short loc_124F\nloc_123E:\nmovsxd rax, edi\nmov [rcx+rax*4], edx\nmov dword ptr [r9+rax*4], 1\nadd edi, 1\nloc_124F:\nadd r8, 4\ncmp r8, r10\njz short loc_1277\nloc_1258:\nmov edx, [r8]\ntest edi, edi\njle short loc_123E\nmovsxd rsi, edi\nmov eax, 0\nloc_1267:\ncmp [rcx+rax*4], edx\njz short loc_1235\nadd rax, 1\ncmp rax, rsi\njnz short loc_1267\njmp short loc_123E\nloc_1277:\ncmp edi, 1\njle short loc_12D4\nmov edi, edi\nmov eax, 1\nmov edx, 0\nloc_1288:\nmovsxd rsi, edx\nmov esi, [r9+rsi*4]\ncmp [r9+rax*4], esi\ncmovg edx, eax\nadd rax, 1\ncmp rax, rdi\njnz short loc_1288\nloc_129F:\nmovsxd rdx, edx\nmov eax, [rcx+rdx*4]\nmov cs:dword_4018, eax\nmov eax, [r9+rdx*4]\nmov cs:dword_401C, eax\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njnz short loc_12DB\nlea rax, dword_4018\nleave\nretn\nloc_12CD:\nmov edx, 0\njmp short loc_129F\nloc_12D4:\nmov edx, 0\njmp short loc_129F\nloc_12DB:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "int *__fastcall sub_1169(int *a1, int a2)\n{\n __int64 v2; // rax\n signed __int64 v3; // rdx\n void *v4; // rsp\n signed __int64 v5; // rdx\n void *v6; // rsp\n int *v7; // r8\n int *v8; // r10\n int v9; // edi\n int v10; // edx\n __int64 v11; // rax\n __int64 v12; // rax\n int v13; // edx\n _DWORD v16[2]; // [rsp+8h] [rbp-10h] BYREF\n unsigned __int64 v17; // [rsp+10h] [rbp-8h]\n\n v17 = __readfsqword(0x28u);\n v2 = 4LL * a2;\n while ( v16 != (_DWORD *)((char *)v16 - ((v2 + 15) & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v3 = ((_WORD)v2 + 15) & 0xFF0;\n v4 = alloca(v3);\n if ( (((_WORD)v2 + 15) & 0xFF0) != 0 )\n *(_QWORD *)((char *)&v16[-2] + v3) = *(_QWORD *)((char *)&v16[-2] + v3);\n while ( v16 != (_DWORD *)((char *)v16 - ((v2 + 15) & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v5 = ((_WORD)v2 + 15) & 0xFF0;\n v6 = alloca(v5);\n if ( (((_WORD)v2 + 15) & 0xFF0) != 0 )\n *(_QWORD *)((char *)&v16[-2] + v5) = *(_QWORD *)((char *)&v16[-2] + v5);\n if ( a2 <= 0 )\n {\n v13 = 0;\n }\n else\n {\n v7 = a1;\n v8 = &a1[(unsigned __int64)v2 / 4];\n v9 = 0;\n do\n {\n v10 = *v7;\n if ( v9 <= 0 )\n {\nLABEL_11:\n v16[v9] = v10;\n v16[v9++] = 1;\n }\n else\n {\n v11 = 0LL;\n while ( v16[v11] != v10 )\n {\n if ( ++v11 == v9 )\n goto LABEL_11;\n }\n ++v16[(int)v11];\n }\n ++v7;\n }\n while ( v7 != v8 );\n if ( v9 <= 1 )\n {\n v13 = 0;\n }\n else\n {\n v12 = 1LL;\n v13 = 0;\n do\n {\n if ( v16[v12] > v16[v13] )\n v13 = v12;\n ++v12;\n }\n while ( v12 != v9 );\n }\n }\n dword_4018 = v16[v13];\n dword_401C = v16[v13];\n return &dword_4018;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "int *sub_1169(int *a1, int a2) {\n long long v2;\n signed long long v3;\n void *v4;\n signed long long v5;\n void *v6;\n int *v7;\n int *v8;\n int v9;\n int v10;\n long long v11;\n long long v12;\n int v13;\n uint32_t v16[2];\n unsigned long long v17;\n v17 = __readfsqword(40u);\n v2 = 4LL * a2;\n while (v16 !=\n (uint32_t *)((char *)v16 - ((v2 + 15) & 18446744073709547520LL)))\n ;\n v3 = ((unsigned short)v2 + 15) & 4080;\n v4 = alloca(v3);\n if ((((unsigned short)v2 + 15) & 4080) != 0)\n *(uint64_t *)((char *)&v16[-2] + v3) = *(uint64_t *)((char *)&v16[-2] + v3);\n while (v16 !=\n (uint32_t *)((char *)v16 - ((v2 + 15) & 18446744073709547520LL)))\n ;\n v5 = ((unsigned short)v2 + 15) & 4080;\n v6 = alloca(v5);\n if ((((unsigned short)v2 + 15) & 4080) != 0)\n *(uint64_t *)((char *)&v16[-2] + v5) = *(uint64_t *)((char *)&v16[-2] + v5);\n if (a2 <= 0) {\n v13 = 0;\n } else {\n v7 = a1;\n v8 = &a1[(unsigned long long)v2 / 4];\n v9 = 0;\n do {\n v10 = *v7;\n if (v9 <= 0) {\n LABEL_11:\n v16[v9] = v10;\n v16[v9++] = 1;\n } else {\n v11 = 0LL;\n while (v16[v11] != v10) {\n if (++v11 == v9) goto LABEL_11;\n }\n ++v16[(int)v11];\n }\n ++v7;\n } while (v7 != v8);\n if (v9 <= 1) {\n v13 = 0;\n } else {\n v12 = 1LL;\n v13 = 0;\n do {\n if (v16[v12] > v16[v13]) v13 = v12;\n ++v12;\n } while (v12 != v9);\n }\n }\n dword_4018 = v16[v13];\n dword_401C = v16[v13];\n return &dword_4018;\n}", + "ida_pseudo_norm": "int *func0(int *a1, int a2) {\n long long v2;\n signed long long v3;\n void *v4;\n signed long long v5;\n void *v6;\n int *v7;\n int *v8;\n int v9;\n int v10;\n long long v11;\n long long v12;\n int v13;\n uint32_t v16[2];\n unsigned long long v17;\n v17 = __readfsqword(40u);\n v2 = 4LL * a2;\n while (v16 !=\n (uint32_t *)((char *)v16 - ((v2 + 15) & 18446744073709547520LL)))\n ;\n v3 = ((unsigned short)v2 + 15) & 4080;\n v4 = alloca(v3);\n if ((((unsigned short)v2 + 15) & 4080) != 0)\n *(uint64_t *)((char *)&v16[-2] + v3) = *(uint64_t *)((char *)&v16[-2] + v3);\n while (v16 !=\n (uint32_t *)((char *)v16 - ((v2 + 15) & 18446744073709547520LL)))\n ;\n v5 = ((unsigned short)v2 + 15) & 4080;\n v6 = alloca(v5);\n if ((((unsigned short)v2 + 15) & 4080) != 0)\n *(uint64_t *)((char *)&v16[-2] + v5) = *(uint64_t *)((char *)&v16[-2] + v5);\n if (a2 <= 0) {\n v13 = 0;\n } else {\n v7 = a1;\n v8 = &a1[(unsigned long long)v2 / 4];\n v9 = 0;\n do {\n v10 = *v7;\n if (v9 <= 0) {\n LABEL_11:\n v16[v9] = v10;\n v16[v9++] = 1;\n } else {\n v11 = 0LL;\n while (v16[v11] != v10) {\n if (++v11 == v9) goto LABEL_11;\n }\n ++v16[(int)v11];\n }\n ++v7;\n } while (v7 != v8);\n if (v9 <= 1) {\n v13 = 0;\n } else {\n v12 = 1LL;\n v13 = 0;\n do {\n if (v16[v12] > v16[v13]) v13 = v12;\n ++v12;\n } while (v12 != v9);\n }\n }\n result_1 = v16[v13];\n dword_401C = v16[v13];\n return &result_1;\n}" + }, + { + "index": 130, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n\n\n", + "func": "int* func0(int nums[], int size) {\n int keys[size];\n int counts[size];\n int unique = 0;\n for (int i = 0; i < size; i++) {\n int num = nums[i];\n int found = 0;\n for (int j = 0; j < unique; j++) {\n if (keys[j] == num) {\n counts[j]++;\n found = 1;\n break;\n }\n }\n if (!found) {\n keys[unique] = num;\n counts[unique] = 1;\n unique++;\n }\n }\n int max_index = 0;\n for (int i = 1; i < unique; i++) {\n if (counts[i] > counts[max_index]) {\n max_index = i;\n }\n }\n static int result[2];\n result[0] = keys[max_index];\n result[1] = counts[max_index];\n return result;\n}", + "test": "int main(){\n\n int nums1[] = {2,3,8,4,7,9,8,2,6,5,1,6,1,2,3,2,4,6,9,1,2};\n\n int size1 = sizeof(nums1)/sizeof(nums1[0]);\n\n int *result;\n\n result = func0(nums1, size1);\n\n assert(result[0] == 2 && result[1] == 5);\n\n\n\n int nums2[] = {2,3,8,4,7,9,8,7,9,15,14,10,12,13,16,16,18};\n\n int size2 = sizeof(nums2)/sizeof(nums2[0]);\n\n result = func0(nums2, size2);\n\n assert(result[0]== 8 && result[1] == 2);\n\n\n\n int nums3[] = {10,20,20,30,40,90,80,50,30,20,50,10};\n\n int size3 = sizeof(nums3)/sizeof(nums3[0]);\n\n result = func0(nums3, size3);\n\n assert(result[0] == 20 && result[1] == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x18,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmovslq %esi,%rax\nmov %rsp,%rbx\nlea 0xf(,%rax,4),%rax\nmov %rax,%rcx\nmov %rax,%rdx\nand $0xfffffffffffff000,%rcx\nand $0xfffffffffffffff0,%rdx\nsub %rcx,%rbx\nmov %rbx,%rcx\ncmp %rcx,%rsp\nje 144b \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rcx,%rsp\njne 1436 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 1572 \nmov %rax,%rdx\nmov %rsp,%rbx\nand $0xfffffffffffff000,%rax\nmov %rsp,%r8\nsub %rax,%rbx\nand $0xfffffffffffffff0,%rdx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 1490 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 147b \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 15a3 \nlea 0x3(%rsp),%r10\nmov %r10,%rbx\nand $0xfffffffffffffffc,%r10\nshr $0x2,%rbx\ntest %esi,%esi\njle 1598 \nlea -0x1(%rsi),%eax\nxor %r9d,%r9d\nlea 0x4(%rdi,%rax,4),%r11\nnopl (%rax)\nmov (%rdi),%ecx\ntest %r9d,%r9d\nje 1580 \nlea -0x1(%r9),%esi\nxor %eax,%eax\njmp 14f0 \nnopl 0x0(%rax,%rax,1)\nlea 0x1(%rax),%rdx\ncmp %rsi,%rax\nje 1580 \nmov %rdx,%rax\nmovslq %eax,%rdx\ncmp %ecx,(%r8,%rax,4)\njne 14e0 \naddl $0x1,(%r10,%rdx,4)\nadd $0x4,%rdi\ncmp %r11,%rdi\njne 14c8 \nmov 0x0(,%rbx,4),%ecx\ncmp $0x1,%r9d\nje 15ae \nlea -0x2(%r9),%esi\nmov $0x1,%eax\nxor %edi,%edi\nadd $0x2,%rsi\nnopw 0x0(%rax,%rax,1)\nmov (%r10,%rax,4),%edx\ncmp %ecx,%edx\njle 153d \nmov %edx,%ecx\nmovslq %eax,%rdi\nadd $0x1,%rax\ncmp %rax,%rsi\njne 1530 \nmov (%r8,%rdi,4),%eax\nmov %ecx,0x2acc(%rip)\nmov %eax,0x2ac2(%rip)\nmov -0x18(%rbp),%rax\nxor %fs:0x28,%rax\njne 15b2 \nmov -0x8(%rbp),%rbx\nlea 0x2aa8(%rip),%rax\nleaveq\nretq\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 145d \nnopl (%rax)\nmovslq %r9d,%rax\nadd $0x1,%r9d\nmov %ecx,(%r8,%rax,4)\nmovl $0x1,(%r10,%rax,4)\njmpq 14fe \nmov 0x0(,%rbx,4),%ecx\nxor %edi,%edi\njmp 1546 \norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 14a2 \nxor %edi,%edi\njmp 1546 \ncallq 1060 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmovsxd r10, esi\nmov r8, r10\nshl r10, 2\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [r10+0Fh]\nmov rcx, rsp\nmov rsi, rax\nmov rdx, rax\nand rsi, 0FFFFFFFFFFFFF000h\nand rdx, 0FFFFFFFFFFFFFFF0h\nsub rcx, rsi\ncmp rsp, rcx\njz short loc_138A\nloc_1375:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rcx\njnz short loc_1375\nloc_138A:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1432\nloc_139C:\nmov rdx, rax\nmov rcx, rsp\nand rax, 0FFFFFFFFFFFFF000h\nmov rsi, rsp\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_13CC\nloc_13B7:\nsub rsp, 1000h\nor [rsp+2010h+var_1018], 0\ncmp rsp, rcx\njnz short loc_13B7\nloc_13CC:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_14C1\nloc_13DE:\nlea r9, [rsp+2010h+var_200D]\nmov r11, r9\nand r9, 0FFFFFFFFFFFFFFFCh\nshr r11, 2\ntest r8d, r8d\njle loc_14B5\nadd r10, rdi\nxor r8d, r8d\nnop dword ptr [rax]\nloc_1400:\nmov edx, [rdi]\nmovsxd rcx, r8d\ntest r8d, r8d\njle short loc_1440\nloc_140A:\nxor eax, eax\njmp short loc_1419\nloc_1410:\nadd rax, 1\ncmp rcx, rax\njz short loc_1440\nloc_1419:\ncmp edx, [rsi+rax*4]\njnz short loc_1410\ncdqe\nadd rdi, 4\nadd dword ptr [r9+rax*4], 1\ncmp rdi, r10\njz short loc_1458\nmov edx, [rdi]\njmp short loc_140A\nloc_1432:\nor [rsp+rdx+1010h+var_1018], 0\njmp loc_139C\nloc_1440:\nadd rdi, 4\nmov [rsi+rcx*4], edx\nadd r8d, 1\nmov dword ptr [r9+rcx*4], 1\ncmp rdi, r10\njnz short loc_1400\nloc_1458:\nmov edx, ds:dword_0[r11*4]\ncmp r8d, 1\njle short loc_14CC\nmov r8d, r8d\nmov eax, 1\nxor edi, edi\nloc_1470:\nmov ecx, [r9+rax*4]\ncmp edx, ecx\ncmovl edi, eax\ncmovl edx, ecx\nadd rax, 1\ncmp r8, rax\njnz short loc_1470\nloc_1485:\nmovsxd rdi, edi\nmovd xmm1, edx\nmovd xmm0, dword ptr [rsi+rdi*4]\npunpckldq xmm0, xmm1\nmovq cs:result_1, xmm0\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njnz short loc_14D0\nleave\nlea rax, result_1\nretn\nloc_14B5:\nmov edx, ds:dword_0[r11*4]\nxor edi, edi\njmp short loc_1485\nloc_14C1:\nor [rsp+rdx+2010h+var_2018], 0\njmp loc_13DE\nloc_14CC:\nxor edi, edi\njmp short loc_1485\nloc_14D0:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 *__fastcall func0(int *a1, int a2)\n{\n __int64 v2; // r10\n _DWORD *v3; // rcx\n signed __int64 v4; // rdx\n void *v5; // rsp\n _DWORD *v6; // rcx\n signed __int64 v7; // rdx\n void *v8; // rsp\n int *v9; // r10\n int v10; // r8d\n int v11; // edx\n __int64 v12; // rcx\n __int64 v13; // rax\n signed int v14; // edx\n __int64 v15; // rax\n int v16; // edi\n _DWORD v19[1024]; // [rsp+8h] [rbp-2010h] BYREF\n _DWORD v20[1022]; // [rsp+1008h] [rbp-1010h] BYREF\n _QWORD v21[2]; // [rsp+2008h] [rbp-10h] BYREF\n\n v2 = 4LL * a2;\n v21[1] = __readfsqword(0x28u);\n v3 = (_DWORD *)((char *)v21 - ((v2 + 15) & 0xFFFFFFFFFFFFF000LL));\n if ( v21 != (_QWORD *)v3 )\n {\n while ( v20 != v3 )\n ;\n }\n v4 = ((_WORD)v2 + 15) & 0xFF0;\n v5 = alloca(v4);\n if ( (((_WORD)v2 + 15) & 0xFF0) != 0 )\n *(_QWORD *)((char *)&v19[1022] + v4) = *(_QWORD *)((char *)&v19[1022] + v4);\n v6 = (_DWORD *)((char *)v20 - ((v2 + 15) & 0xFFFFFFFFFFFFF000LL));\n if ( v20 != v6 )\n {\n while ( v19 != v6 )\n ;\n }\n v7 = ((_WORD)v2 + 15) & 0xFF0;\n v8 = alloca(v7);\n if ( (((_WORD)v2 + 15) & 0xFF0) != 0 )\n *(_QWORD *)((char *)&v19[-2] + v7) = *(_QWORD *)((char *)&v19[-2] + v7);\n if ( a2 <= 0 )\n {\n v14 = v19[0];\n v16 = 0;\n }\n else\n {\n v9 = &a1[(unsigned __int64)v2 / 4];\n v10 = 0;\n while ( 1 )\n {\n v11 = *a1;\n v12 = v10;\n if ( v10 > 0 )\n break;\nLABEL_17:\n ++a1;\n v20[v10++] = v11;\n v19[v12] = 1;\n if ( a1 == v9 )\n goto LABEL_18;\n }\n while ( 1 )\n {\n v13 = 0LL;\n while ( v11 != v20[v13] )\n {\n if ( v10 == ++v13 )\n goto LABEL_17;\n }\n ++a1;\n ++v19[(int)v13];\n if ( a1 == v9 )\n break;\n v11 = *a1;\n }\nLABEL_18:\n v14 = v19[0];\n if ( v10 <= 1 )\n {\n v16 = 0;\n }\n else\n {\n v15 = 1LL;\n v16 = 0;\n do\n {\n if ( v14 < v19[v15] )\n {\n v16 = v15;\n v14 = v19[v15];\n }\n ++v15;\n }\n while ( v10 != v15 );\n }\n }\n result_1 = _mm_unpacklo_epi32(_mm_cvtsi32_si128(v20[v16]), _mm_cvtsi32_si128(v14)).m128i_u64[0];\n return &result_1;\n}", + "ida_strip_asm": "sub_1330:\nendbr64\npush rbp\nmovsxd r10, esi\nmov r8, r10\nshl r10, 2\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [r10+0Fh]\nmov rcx, rsp\nmov rsi, rax\nmov rdx, rax\nand rsi, 0FFFFFFFFFFFFF000h\nand rdx, 0FFFFFFFFFFFFFFF0h\nsub rcx, rsi\ncmp rsp, rcx\njz short loc_138A\nloc_1375:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rcx\njnz short loc_1375\nloc_138A:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1432\nloc_139C:\nmov rdx, rax\nmov rcx, rsp\nand rax, 0FFFFFFFFFFFFF000h\nmov rsi, rsp\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_13CC\nloc_13B7:\nsub rsp, 1000h\nor [rsp+2010h+var_1018], 0\ncmp rsp, rcx\njnz short loc_13B7\nloc_13CC:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_14C1\nloc_13DE:\nlea r9, [rsp+2010h+var_200D]\nmov r11, r9\nand r9, 0FFFFFFFFFFFFFFFCh\nshr r11, 2\ntest r8d, r8d\njle loc_14B5\nadd r10, rdi\nxor r8d, r8d\nnop dword ptr [rax]\nloc_1400:\nmov edx, [rdi]\nmovsxd rcx, r8d\ntest r8d, r8d\njle short loc_1440\nloc_140A:\nxor eax, eax\njmp short loc_1419\nloc_1410:\nadd rax, 1\ncmp rcx, rax\njz short loc_1440\nloc_1419:\ncmp edx, [rsi+rax*4]\njnz short loc_1410\ncdqe\nadd rdi, 4\nadd dword ptr [r9+rax*4], 1\ncmp rdi, r10\njz short loc_1458\nmov edx, [rdi]\njmp short loc_140A\nloc_1432:\nor [rsp+rdx+1010h+var_1018], 0\njmp loc_139C\nloc_1440:\nadd rdi, 4\nmov [rsi+rcx*4], edx\nadd r8d, 1\nmov dword ptr [r9+rcx*4], 1\ncmp rdi, r10\njnz short loc_1400\nloc_1458:\nmov edx, ds:dword_0[r11*4]\ncmp r8d, 1\njle short loc_14CC\nmov r8d, r8d\nmov eax, 1\nxor edi, edi\nloc_1470:\nmov ecx, [r9+rax*4]\ncmp edx, ecx\ncmovl edi, eax\ncmovl edx, ecx\nadd rax, 1\ncmp r8, rax\njnz short loc_1470\nloc_1485:\nmovsxd rdi, edi\nmovd xmm1, edx\nmovd xmm0, dword ptr [rsi+rdi*4]\npunpckldq xmm0, xmm1\nmovq cs:qword_4018, xmm0\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njnz short loc_14D0\nleave\nlea rax, qword_4018\nretn\nloc_14B5:\nmov edx, ds:dword_0[r11*4]\nxor edi, edi\njmp short loc_1485\nloc_14C1:\nor [rsp+rdx+2010h+var_2018], 0\njmp loc_13DE\nloc_14CC:\nxor edi, edi\njmp short loc_1485\nloc_14D0:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 *__fastcall sub_1330(int *a1, int a2)\n{\n __int64 v2; // r10\n _DWORD *v3; // rcx\n signed __int64 v4; // rdx\n void *v5; // rsp\n _DWORD *v6; // rcx\n signed __int64 v7; // rdx\n void *v8; // rsp\n int *v9; // r10\n int v10; // r8d\n int v11; // edx\n __int64 v12; // rcx\n __int64 v13; // rax\n signed int v14; // edx\n __int64 v15; // rax\n int v16; // edi\n _DWORD v19[1024]; // [rsp+8h] [rbp-2010h] BYREF\n _DWORD v20[1022]; // [rsp+1008h] [rbp-1010h] BYREF\n _QWORD v21[2]; // [rsp+2008h] [rbp-10h] BYREF\n\n v2 = 4LL * a2;\n v21[1] = __readfsqword(0x28u);\n v3 = (_DWORD *)((char *)v21 - ((v2 + 15) & 0xFFFFFFFFFFFFF000LL));\n if ( v21 != (_QWORD *)v3 )\n {\n while ( v20 != v3 )\n ;\n }\n v4 = ((_WORD)v2 + 15) & 0xFF0;\n v5 = alloca(v4);\n if ( (((_WORD)v2 + 15) & 0xFF0) != 0 )\n *(_QWORD *)((char *)&v19[1022] + v4) = *(_QWORD *)((char *)&v19[1022] + v4);\n v6 = (_DWORD *)((char *)v20 - ((v2 + 15) & 0xFFFFFFFFFFFFF000LL));\n if ( v20 != v6 )\n {\n while ( v19 != v6 )\n ;\n }\n v7 = ((_WORD)v2 + 15) & 0xFF0;\n v8 = alloca(v7);\n if ( (((_WORD)v2 + 15) & 0xFF0) != 0 )\n *(_QWORD *)((char *)&v19[-2] + v7) = *(_QWORD *)((char *)&v19[-2] + v7);\n if ( a2 <= 0 )\n {\n v14 = v19[0];\n v16 = 0;\n }\n else\n {\n v9 = &a1[(unsigned __int64)v2 / 4];\n v10 = 0;\n while ( 1 )\n {\n v11 = *a1;\n v12 = v10;\n if ( v10 > 0 )\n break;\nLABEL_17:\n ++a1;\n v20[v10++] = v11;\n v19[v12] = 1;\n if ( a1 == v9 )\n goto LABEL_18;\n }\n while ( 1 )\n {\n v13 = 0LL;\n while ( v11 != v20[v13] )\n {\n if ( v10 == ++v13 )\n goto LABEL_17;\n }\n ++a1;\n ++v19[(int)v13];\n if ( a1 == v9 )\n break;\n v11 = *a1;\n }\nLABEL_18:\n v14 = v19[0];\n if ( v10 <= 1 )\n {\n v16 = 0;\n }\n else\n {\n v15 = 1LL;\n v16 = 0;\n do\n {\n if ( v14 < v19[v15] )\n {\n v16 = v15;\n v14 = v19[v15];\n }\n ++v15;\n }\n while ( v10 != v15 );\n }\n }\n qword_4018 = _mm_unpacklo_epi32(_mm_cvtsi32_si128(v20[v16]), _mm_cvtsi32_si128(v14)).m128i_u64[0];\n return &qword_4018;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long *sub_1330(int *a1, int a2) {\n long long v2;\n uint32_t *v3;\n signed long long v4;\n void *v5;\n uint32_t *v6;\n signed long long v7;\n void *v8;\n int *v9;\n int v10;\n int v11;\n long long v12;\n long long v13;\n signed int v14;\n long long v15;\n int v16;\n uint32_t v19[1024];\n uint32_t v20[1022];\n uint64_t v21[2];\n v2 = 4LL * a2;\n v21[1] = __readfsqword(40u);\n v3 = (uint32_t *)((char *)v21 - ((v2 + 15) & 18446744073709547520LL));\n if (v21 != (uint64_t *)v3) {\n while (v20 != v3)\n ;\n }\n v4 = ((unsigned short)v2 + 15) & 4080;\n v5 = alloca(v4);\n if ((((unsigned short)v2 + 15) & 4080) != 0)\n *(uint64_t *)((char *)&v19[1022] + v4) =\n *(uint64_t *)((char *)&v19[1022] + v4);\n v6 = (uint32_t *)((char *)v20 - ((v2 + 15) & 18446744073709547520LL));\n if (v20 != v6) {\n while (v19 != v6)\n ;\n }\n v7 = ((unsigned short)v2 + 15) & 4080;\n v8 = alloca(v7);\n if ((((unsigned short)v2 + 15) & 4080) != 0)\n *(uint64_t *)((char *)&v19[-2] + v7) = *(uint64_t *)((char *)&v19[-2] + v7);\n if (a2 <= 0) {\n v14 = v19[0];\n v16 = 0;\n } else {\n v9 = &a1[(unsigned long long)v2 / 4];\n v10 = 0;\n while (1) {\n v11 = *a1;\n v12 = v10;\n if (v10 > 0) break;\n LABEL_17:\n ++a1;\n v20[v10++] = v11;\n v19[v12] = 1;\n if (a1 == v9) goto LABEL_18;\n }\n while (1) {\n v13 = 0LL;\n while (v11 != v20[v13]) {\n if (v10 == ++v13) goto LABEL_17;\n }\n ++a1;\n ++v19[(int)v13];\n if (a1 == v9) break;\n v11 = *a1;\n }\n LABEL_18:\n v14 = v19[0];\n if (v10 <= 1) {\n v16 = 0;\n } else {\n v15 = 1LL;\n v16 = 0;\n do {\n if (v14 < v19[v15]) {\n v16 = v15;\n v14 = v19[v15];\n }\n ++v15;\n } while (v10 != v15);\n }\n }\n qword_4018 =\n _mm_unpacklo_epi32(_mm_cvtsi32_si128(v20[v16]), _mm_cvtsi32_si128(v14))\n .m128i_u64[0];\n return &qword_4018;\n}", + "ida_pseudo_norm": "long long *func0(int *a1, int a2) {\n long long v2;\n uint32_t *v3;\n signed long long v4;\n void *v5;\n uint32_t *v6;\n signed long long v7;\n void *v8;\n int *v9;\n int v10;\n int v11;\n long long v12;\n long long v13;\n signed int v14;\n long long v15;\n int v16;\n uint32_t v19[1024];\n uint32_t v20[1022];\n uint64_t v21[2];\n v2 = 4LL * a2;\n v21[1] = __readfsqword(40u);\n v3 = (uint32_t *)((char *)v21 - ((v2 + 15) & 18446744073709547520LL));\n if (v21 != (uint64_t *)v3) {\n while (v20 != v3)\n ;\n }\n v4 = ((unsigned short)v2 + 15) & 4080;\n v5 = alloca(v4);\n if ((((unsigned short)v2 + 15) & 4080) != 0)\n *(uint64_t *)((char *)&v19[1022] + v4) =\n *(uint64_t *)((char *)&v19[1022] + v4);\n v6 = (uint32_t *)((char *)v20 - ((v2 + 15) & 18446744073709547520LL));\n if (v20 != v6) {\n while (v19 != v6)\n ;\n }\n v7 = ((unsigned short)v2 + 15) & 4080;\n v8 = alloca(v7);\n if ((((unsigned short)v2 + 15) & 4080) != 0)\n *(uint64_t *)((char *)&v19[-2] + v7) = *(uint64_t *)((char *)&v19[-2] + v7);\n if (a2 <= 0) {\n v14 = v19[0];\n v16 = 0;\n } else {\n v9 = &a1[(unsigned long long)v2 / 4];\n v10 = 0;\n while (1) {\n v11 = *a1;\n v12 = v10;\n if (v10 > 0) break;\n LABEL_17:\n ++a1;\n v20[v10++] = v11;\n v19[v12] = 1;\n if (a1 == v9) goto LABEL_18;\n }\n while (1) {\n v13 = 0LL;\n while (v11 != v20[v13]) {\n if (v10 == ++v13) goto LABEL_17;\n }\n ++a1;\n ++v19[(int)v13];\n if (a1 == v9) break;\n v11 = *a1;\n }\n LABEL_18:\n v14 = v19[0];\n if (v10 <= 1) {\n v16 = 0;\n } else {\n v15 = 1LL;\n v16 = 0;\n do {\n if (v14 < v19[v15]) {\n v16 = v15;\n v14 = v19[v15];\n }\n ++v15;\n } while (v10 != v15);\n }\n }\n result_1 =\n _mm_unpacklo_epi32(_mm_cvtsi32_si128(v20[v16]), _mm_cvtsi32_si128(v14))\n .m128i_u64[0];\n return &result_1;\n}" + }, + { + "index": 130, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n\n\n", + "func": "int* func0(int nums[], int size) {\n int keys[size];\n int counts[size];\n int unique = 0;\n for (int i = 0; i < size; i++) {\n int num = nums[i];\n int found = 0;\n for (int j = 0; j < unique; j++) {\n if (keys[j] == num) {\n counts[j]++;\n found = 1;\n break;\n }\n }\n if (!found) {\n keys[unique] = num;\n counts[unique] = 1;\n unique++;\n }\n }\n int max_index = 0;\n for (int i = 1; i < unique; i++) {\n if (counts[i] > counts[max_index]) {\n max_index = i;\n }\n }\n static int result[2];\n result[0] = keys[max_index];\n result[1] = counts[max_index];\n return result;\n}", + "test": "int main(){\n\n int nums1[] = {2,3,8,4,7,9,8,2,6,5,1,6,1,2,3,2,4,6,9,1,2};\n\n int size1 = sizeof(nums1)/sizeof(nums1[0]);\n\n int *result;\n\n result = func0(nums1, size1);\n\n assert(result[0] == 2 && result[1] == 5);\n\n\n\n int nums2[] = {2,3,8,4,7,9,8,7,9,15,14,10,12,13,16,16,18};\n\n int size2 = sizeof(nums2)/sizeof(nums2[0]);\n\n result = func0(nums2, size2);\n\n assert(result[0]== 8 && result[1] == 2);\n\n\n\n int nums3[] = {10,20,20,30,40,90,80,50,30,20,50,10};\n\n int size3 = sizeof(nums3)/sizeof(nums3[0]);\n\n result = func0(nums3, size3);\n\n assert(result[0] == 20 && result[1] == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x18,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmovslq %esi,%rax\nmov %rsp,%rbx\nlea 0xf(,%rax,4),%rax\nmov %rax,%rcx\nmov %rax,%rdx\nand $0xfffffffffffff000,%rcx\nand $0xfffffffffffffff0,%rdx\nsub %rcx,%rbx\nmov %rbx,%rcx\ncmp %rcx,%rsp\nje 138b \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rcx,%rsp\njne 1376 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 14b2 \nmov %rax,%rdx\nmov %rsp,%rbx\nand $0xfffffffffffff000,%rax\nmov %rsp,%r8\nsub %rax,%rbx\nand $0xfffffffffffffff0,%rdx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 13d0 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 13bb \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 14e3 \nlea 0x3(%rsp),%r10\nmov %r10,%rbx\nand $0xfffffffffffffffc,%r10\nshr $0x2,%rbx\ntest %esi,%esi\njle 14d8 \nlea -0x1(%rsi),%eax\nxor %r9d,%r9d\nlea 0x4(%rdi,%rax,4),%r11\nnopl (%rax)\nmov (%rdi),%ecx\ntest %r9d,%r9d\nje 14c0 \nlea -0x1(%r9),%esi\nxor %eax,%eax\njmp 1430 \nnopl 0x0(%rax,%rax,1)\nlea 0x1(%rax),%rdx\ncmp %rsi,%rax\nje 14c0 \nmov %rdx,%rax\nmovslq %eax,%rdx\ncmp %ecx,(%r8,%rax,4)\njne 1420 \naddl $0x1,(%r10,%rdx,4)\nadd $0x4,%rdi\ncmp %r11,%rdi\njne 1408 \nmov 0x0(,%rbx,4),%ecx\ncmp $0x1,%r9d\nje 14ee \nlea -0x2(%r9),%esi\nmov $0x1,%eax\nxor %edi,%edi\nadd $0x2,%rsi\nnopw 0x0(%rax,%rax,1)\nmov (%r10,%rax,4),%edx\ncmp %ecx,%edx\njle 147d \nmov %edx,%ecx\nmovslq %eax,%rdi\nadd $0x1,%rax\ncmp %rax,%rsi\njne 1470 \nmov (%r8,%rdi,4),%eax\nmov %ecx,0x2b8c(%rip)\nmov %eax,0x2b82(%rip)\nmov -0x18(%rbp),%rax\nxor %fs:0x28,%rax\njne 14f2 \nmov -0x8(%rbp),%rbx\nlea 0x2b68(%rip),%rax\nleaveq\nretq\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 139d \nnopl (%rax)\nmovslq %r9d,%rax\nadd $0x1,%r9d\nmov %ecx,(%r8,%rax,4)\nmovl $0x1,(%r10,%rax,4)\njmpq 143e \nmov 0x0(,%rbx,4),%ecx\nxor %edi,%edi\njmp 1486 \norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 13e2 \nxor %edi,%edi\njmp 1486 \ncallq 1060 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmovsxd r10, esi\nmov r8, r10\nshl r10, 2\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [r10+0Fh]\nmov rcx, rsp\nmov rsi, rax\nmov rdx, rax\nand rsi, 0FFFFFFFFFFFFF000h\nand rdx, 0FFFFFFFFFFFFFFF0h\nsub rcx, rsi\ncmp rsp, rcx\njz short loc_138A\nloc_1375:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rcx\njnz short loc_1375\nloc_138A:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1432\nloc_139C:\nmov rdx, rax\nmov rcx, rsp\nand rax, 0FFFFFFFFFFFFF000h\nmov rsi, rsp\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_13CC\nloc_13B7:\nsub rsp, 1000h\nor [rsp+2010h+var_1018], 0\ncmp rsp, rcx\njnz short loc_13B7\nloc_13CC:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_14C1\nloc_13DE:\nlea r9, [rsp+2010h+var_200D]\nmov r11, r9\nand r9, 0FFFFFFFFFFFFFFFCh\nshr r11, 2\ntest r8d, r8d\njle loc_14B5\nadd r10, rdi\nxor r8d, r8d\nnop dword ptr [rax]\nloc_1400:\nmov edx, [rdi]\nmovsxd rcx, r8d\ntest r8d, r8d\njle short loc_1440\nloc_140A:\nxor eax, eax\njmp short loc_1419\nloc_1410:\nadd rax, 1\ncmp rcx, rax\njz short loc_1440\nloc_1419:\ncmp edx, [rsi+rax*4]\njnz short loc_1410\ncdqe\nadd rdi, 4\nadd dword ptr [r9+rax*4], 1\ncmp rdi, r10\njz short loc_1458\nmov edx, [rdi]\njmp short loc_140A\nloc_1432:\nor [rsp+rdx+1010h+var_1018], 0\njmp loc_139C\nloc_1440:\nadd rdi, 4\nmov [rsi+rcx*4], edx\nadd r8d, 1\nmov dword ptr [r9+rcx*4], 1\ncmp rdi, r10\njnz short loc_1400\nloc_1458:\nmov edx, ds:dword_0[r11*4]\ncmp r8d, 1\njle short loc_14CC\nmov r8d, r8d\nmov eax, 1\nxor edi, edi\nloc_1470:\nmov ecx, [r9+rax*4]\ncmp edx, ecx\ncmovl edi, eax\ncmovl edx, ecx\nadd rax, 1\ncmp r8, rax\njnz short loc_1470\nloc_1485:\nmovsxd rdi, edi\nmovd xmm1, edx\nmovd xmm0, dword ptr [rsi+rdi*4]\npunpckldq xmm0, xmm1\nmovq cs:result_1, xmm0\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njnz short loc_14D0\nleave\nlea rax, result_1\nretn\nloc_14B5:\nmov edx, ds:dword_0[r11*4]\nxor edi, edi\njmp short loc_1485\nloc_14C1:\nor [rsp+rdx+2010h+var_2018], 0\njmp loc_13DE\nloc_14CC:\nxor edi, edi\njmp short loc_1485\nloc_14D0:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 *__fastcall func0(int *a1, int a2)\n{\n __int64 v2; // r10\n _DWORD *v3; // rcx\n signed __int64 v4; // rdx\n void *v5; // rsp\n _DWORD *v6; // rcx\n signed __int64 v7; // rdx\n void *v8; // rsp\n int *v9; // r10\n int v10; // r8d\n int v11; // edx\n __int64 v12; // rcx\n __int64 v13; // rax\n signed int v14; // edx\n __int64 v15; // rax\n int v16; // edi\n _DWORD v19[1024]; // [rsp+8h] [rbp-2010h] BYREF\n _DWORD v20[1022]; // [rsp+1008h] [rbp-1010h] BYREF\n _QWORD v21[2]; // [rsp+2008h] [rbp-10h] BYREF\n\n v2 = 4LL * a2;\n v21[1] = __readfsqword(0x28u);\n v3 = (_DWORD *)((char *)v21 - ((v2 + 15) & 0xFFFFFFFFFFFFF000LL));\n if ( v21 != (_QWORD *)v3 )\n {\n while ( v20 != v3 )\n ;\n }\n v4 = ((_WORD)v2 + 15) & 0xFF0;\n v5 = alloca(v4);\n if ( (((_WORD)v2 + 15) & 0xFF0) != 0 )\n *(_QWORD *)((char *)&v19[1022] + v4) = *(_QWORD *)((char *)&v19[1022] + v4);\n v6 = (_DWORD *)((char *)v20 - ((v2 + 15) & 0xFFFFFFFFFFFFF000LL));\n if ( v20 != v6 )\n {\n while ( v19 != v6 )\n ;\n }\n v7 = ((_WORD)v2 + 15) & 0xFF0;\n v8 = alloca(v7);\n if ( (((_WORD)v2 + 15) & 0xFF0) != 0 )\n *(_QWORD *)((char *)&v19[-2] + v7) = *(_QWORD *)((char *)&v19[-2] + v7);\n if ( a2 <= 0 )\n {\n v14 = v19[0];\n v16 = 0;\n }\n else\n {\n v9 = &a1[(unsigned __int64)v2 / 4];\n v10 = 0;\n while ( 1 )\n {\n v11 = *a1;\n v12 = v10;\n if ( v10 > 0 )\n break;\nLABEL_17:\n ++a1;\n v20[v10++] = v11;\n v19[v12] = 1;\n if ( a1 == v9 )\n goto LABEL_18;\n }\n while ( 1 )\n {\n v13 = 0LL;\n while ( v11 != v20[v13] )\n {\n if ( v10 == ++v13 )\n goto LABEL_17;\n }\n ++a1;\n ++v19[(int)v13];\n if ( a1 == v9 )\n break;\n v11 = *a1;\n }\nLABEL_18:\n v14 = v19[0];\n if ( v10 <= 1 )\n {\n v16 = 0;\n }\n else\n {\n v15 = 1LL;\n v16 = 0;\n do\n {\n if ( v14 < v19[v15] )\n {\n v16 = v15;\n v14 = v19[v15];\n }\n ++v15;\n }\n while ( v10 != v15 );\n }\n }\n result_1 = _mm_unpacklo_epi32(_mm_cvtsi32_si128(v20[v16]), _mm_cvtsi32_si128(v14)).m128i_u64[0];\n return &result_1;\n}", + "ida_strip_asm": "sub_1330:\nendbr64\npush rbp\nmovsxd r10, esi\nmov r8, r10\nshl r10, 2\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [r10+0Fh]\nmov rcx, rsp\nmov rsi, rax\nmov rdx, rax\nand rsi, 0FFFFFFFFFFFFF000h\nand rdx, 0FFFFFFFFFFFFFFF0h\nsub rcx, rsi\ncmp rsp, rcx\njz short loc_138A\nloc_1375:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rcx\njnz short loc_1375\nloc_138A:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1432\nloc_139C:\nmov rdx, rax\nmov rcx, rsp\nand rax, 0FFFFFFFFFFFFF000h\nmov rsi, rsp\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_13CC\nloc_13B7:\nsub rsp, 1000h\nor [rsp+2010h+var_1018], 0\ncmp rsp, rcx\njnz short loc_13B7\nloc_13CC:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_14C1\nloc_13DE:\nlea r9, [rsp+2010h+var_200D]\nmov r11, r9\nand r9, 0FFFFFFFFFFFFFFFCh\nshr r11, 2\ntest r8d, r8d\njle loc_14B5\nadd r10, rdi\nxor r8d, r8d\nnop dword ptr [rax]\nloc_1400:\nmov edx, [rdi]\nmovsxd rcx, r8d\ntest r8d, r8d\njle short loc_1440\nloc_140A:\nxor eax, eax\njmp short loc_1419\nloc_1410:\nadd rax, 1\ncmp rcx, rax\njz short loc_1440\nloc_1419:\ncmp edx, [rsi+rax*4]\njnz short loc_1410\ncdqe\nadd rdi, 4\nadd dword ptr [r9+rax*4], 1\ncmp rdi, r10\njz short loc_1458\nmov edx, [rdi]\njmp short loc_140A\nloc_1432:\nor [rsp+rdx+1010h+var_1018], 0\njmp loc_139C\nloc_1440:\nadd rdi, 4\nmov [rsi+rcx*4], edx\nadd r8d, 1\nmov dword ptr [r9+rcx*4], 1\ncmp rdi, r10\njnz short loc_1400\nloc_1458:\nmov edx, ds:dword_0[r11*4]\ncmp r8d, 1\njle short loc_14CC\nmov r8d, r8d\nmov eax, 1\nxor edi, edi\nloc_1470:\nmov ecx, [r9+rax*4]\ncmp edx, ecx\ncmovl edi, eax\ncmovl edx, ecx\nadd rax, 1\ncmp r8, rax\njnz short loc_1470\nloc_1485:\nmovsxd rdi, edi\nmovd xmm1, edx\nmovd xmm0, dword ptr [rsi+rdi*4]\npunpckldq xmm0, xmm1\nmovq cs:qword_4018, xmm0\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njnz short loc_14D0\nleave\nlea rax, qword_4018\nretn\nloc_14B5:\nmov edx, ds:dword_0[r11*4]\nxor edi, edi\njmp short loc_1485\nloc_14C1:\nor [rsp+rdx+2010h+var_2018], 0\njmp loc_13DE\nloc_14CC:\nxor edi, edi\njmp short loc_1485\nloc_14D0:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 *__fastcall sub_1330(int *a1, int a2)\n{\n __int64 v2; // r10\n _DWORD *v3; // rcx\n signed __int64 v4; // rdx\n void *v5; // rsp\n _DWORD *v6; // rcx\n signed __int64 v7; // rdx\n void *v8; // rsp\n int *v9; // r10\n int v10; // r8d\n int v11; // edx\n __int64 v12; // rcx\n __int64 v13; // rax\n signed int v14; // edx\n __int64 v15; // rax\n int v16; // edi\n _DWORD v19[1024]; // [rsp+8h] [rbp-2010h] BYREF\n _DWORD v20[1022]; // [rsp+1008h] [rbp-1010h] BYREF\n _QWORD v21[2]; // [rsp+2008h] [rbp-10h] BYREF\n\n v2 = 4LL * a2;\n v21[1] = __readfsqword(0x28u);\n v3 = (_DWORD *)((char *)v21 - ((v2 + 15) & 0xFFFFFFFFFFFFF000LL));\n if ( v21 != (_QWORD *)v3 )\n {\n while ( v20 != v3 )\n ;\n }\n v4 = ((_WORD)v2 + 15) & 0xFF0;\n v5 = alloca(v4);\n if ( (((_WORD)v2 + 15) & 0xFF0) != 0 )\n *(_QWORD *)((char *)&v19[1022] + v4) = *(_QWORD *)((char *)&v19[1022] + v4);\n v6 = (_DWORD *)((char *)v20 - ((v2 + 15) & 0xFFFFFFFFFFFFF000LL));\n if ( v20 != v6 )\n {\n while ( v19 != v6 )\n ;\n }\n v7 = ((_WORD)v2 + 15) & 0xFF0;\n v8 = alloca(v7);\n if ( (((_WORD)v2 + 15) & 0xFF0) != 0 )\n *(_QWORD *)((char *)&v19[-2] + v7) = *(_QWORD *)((char *)&v19[-2] + v7);\n if ( a2 <= 0 )\n {\n v14 = v19[0];\n v16 = 0;\n }\n else\n {\n v9 = &a1[(unsigned __int64)v2 / 4];\n v10 = 0;\n while ( 1 )\n {\n v11 = *a1;\n v12 = v10;\n if ( v10 > 0 )\n break;\nLABEL_17:\n ++a1;\n v20[v10++] = v11;\n v19[v12] = 1;\n if ( a1 == v9 )\n goto LABEL_18;\n }\n while ( 1 )\n {\n v13 = 0LL;\n while ( v11 != v20[v13] )\n {\n if ( v10 == ++v13 )\n goto LABEL_17;\n }\n ++a1;\n ++v19[(int)v13];\n if ( a1 == v9 )\n break;\n v11 = *a1;\n }\nLABEL_18:\n v14 = v19[0];\n if ( v10 <= 1 )\n {\n v16 = 0;\n }\n else\n {\n v15 = 1LL;\n v16 = 0;\n do\n {\n if ( v14 < v19[v15] )\n {\n v16 = v15;\n v14 = v19[v15];\n }\n ++v15;\n }\n while ( v10 != v15 );\n }\n }\n qword_4018 = _mm_unpacklo_epi32(_mm_cvtsi32_si128(v20[v16]), _mm_cvtsi32_si128(v14)).m128i_u64[0];\n return &qword_4018;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long *sub_1330(int *a1, int a2) {\n long long v2;\n uint32_t *v3;\n signed long long v4;\n void *v5;\n uint32_t *v6;\n signed long long v7;\n void *v8;\n int *v9;\n int v10;\n int v11;\n long long v12;\n long long v13;\n signed int v14;\n long long v15;\n int v16;\n uint32_t v19[1024];\n uint32_t v20[1022];\n uint64_t v21[2];\n v2 = 4LL * a2;\n v21[1] = __readfsqword(40u);\n v3 = (uint32_t *)((char *)v21 - ((v2 + 15) & 18446744073709547520LL));\n if (v21 != (uint64_t *)v3) {\n while (v20 != v3)\n ;\n }\n v4 = ((unsigned short)v2 + 15) & 4080;\n v5 = alloca(v4);\n if ((((unsigned short)v2 + 15) & 4080) != 0)\n *(uint64_t *)((char *)&v19[1022] + v4) =\n *(uint64_t *)((char *)&v19[1022] + v4);\n v6 = (uint32_t *)((char *)v20 - ((v2 + 15) & 18446744073709547520LL));\n if (v20 != v6) {\n while (v19 != v6)\n ;\n }\n v7 = ((unsigned short)v2 + 15) & 4080;\n v8 = alloca(v7);\n if ((((unsigned short)v2 + 15) & 4080) != 0)\n *(uint64_t *)((char *)&v19[-2] + v7) = *(uint64_t *)((char *)&v19[-2] + v7);\n if (a2 <= 0) {\n v14 = v19[0];\n v16 = 0;\n } else {\n v9 = &a1[(unsigned long long)v2 / 4];\n v10 = 0;\n while (1) {\n v11 = *a1;\n v12 = v10;\n if (v10 > 0) break;\n LABEL_17:\n ++a1;\n v20[v10++] = v11;\n v19[v12] = 1;\n if (a1 == v9) goto LABEL_18;\n }\n while (1) {\n v13 = 0LL;\n while (v11 != v20[v13]) {\n if (v10 == ++v13) goto LABEL_17;\n }\n ++a1;\n ++v19[(int)v13];\n if (a1 == v9) break;\n v11 = *a1;\n }\n LABEL_18:\n v14 = v19[0];\n if (v10 <= 1) {\n v16 = 0;\n } else {\n v15 = 1LL;\n v16 = 0;\n do {\n if (v14 < v19[v15]) {\n v16 = v15;\n v14 = v19[v15];\n }\n ++v15;\n } while (v10 != v15);\n }\n }\n qword_4018 =\n _mm_unpacklo_epi32(_mm_cvtsi32_si128(v20[v16]), _mm_cvtsi32_si128(v14))\n .m128i_u64[0];\n return &qword_4018;\n}", + "ida_pseudo_norm": "long long *func0(int *a1, int a2) {\n long long v2;\n uint32_t *v3;\n signed long long v4;\n void *v5;\n uint32_t *v6;\n signed long long v7;\n void *v8;\n int *v9;\n int v10;\n int v11;\n long long v12;\n long long v13;\n signed int v14;\n long long v15;\n int v16;\n uint32_t v19[1024];\n uint32_t v20[1022];\n uint64_t v21[2];\n v2 = 4LL * a2;\n v21[1] = __readfsqword(40u);\n v3 = (uint32_t *)((char *)v21 - ((v2 + 15) & 18446744073709547520LL));\n if (v21 != (uint64_t *)v3) {\n while (v20 != v3)\n ;\n }\n v4 = ((unsigned short)v2 + 15) & 4080;\n v5 = alloca(v4);\n if ((((unsigned short)v2 + 15) & 4080) != 0)\n *(uint64_t *)((char *)&v19[1022] + v4) =\n *(uint64_t *)((char *)&v19[1022] + v4);\n v6 = (uint32_t *)((char *)v20 - ((v2 + 15) & 18446744073709547520LL));\n if (v20 != v6) {\n while (v19 != v6)\n ;\n }\n v7 = ((unsigned short)v2 + 15) & 4080;\n v8 = alloca(v7);\n if ((((unsigned short)v2 + 15) & 4080) != 0)\n *(uint64_t *)((char *)&v19[-2] + v7) = *(uint64_t *)((char *)&v19[-2] + v7);\n if (a2 <= 0) {\n v14 = v19[0];\n v16 = 0;\n } else {\n v9 = &a1[(unsigned long long)v2 / 4];\n v10 = 0;\n while (1) {\n v11 = *a1;\n v12 = v10;\n if (v10 > 0) break;\n LABEL_17:\n ++a1;\n v20[v10++] = v11;\n v19[v12] = 1;\n if (a1 == v9) goto LABEL_18;\n }\n while (1) {\n v13 = 0LL;\n while (v11 != v20[v13]) {\n if (v10 == ++v13) goto LABEL_17;\n }\n ++a1;\n ++v19[(int)v13];\n if (a1 == v9) break;\n v11 = *a1;\n }\n LABEL_18:\n v14 = v19[0];\n if (v10 <= 1) {\n v16 = 0;\n } else {\n v15 = 1LL;\n v16 = 0;\n do {\n if (v14 < v19[v15]) {\n v16 = v15;\n v14 = v19[v15];\n }\n ++v15;\n } while (v10 != v15);\n }\n }\n result_1 =\n _mm_unpacklo_epi32(_mm_cvtsi32_si128(v20[v16]), _mm_cvtsi32_si128(v14))\n .m128i_u64[0];\n return &result_1;\n}" + }, + { + "index": 131, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* str1) {\n static char result_string[100];\n int i, j = 0;\n char vowels[100] = \"\";\n for (i = 0; str1[i] != '\\0'; i++) {\n char char1 = str1[i];\n if (strchr(\"aeiouAEIOU\", char1) != NULL) {\n vowels[j++] = char1;\n }\n }\n vowels[j] = '\\0';\n j = 0;\n int k = strlen(vowels) - 1;\n for (i = 0; str1[i] != '\\0'; i++) {\n char char1 = str1[i];\n if (strchr(\"aeiouAEIOU\", char1) != NULL) {\n result_string[j++] = vowels[k--];\n } else {\n result_string[j++] = str1[i];\n }\n }\n result_string[j] = '\\0';\n return result_string;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"Python\"), \"Python\") == 0);\n\n assert(strcmp(func0(\"USA\"), \"ASU\") == 0);\n\n assert(strcmp(func0(\"ab\"), \"ab\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x90,%rsp\nmov %rdi,-0x88(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovl $0x0,-0x78(%rbp)\nmovq $0x0,-0x70(%rbp)\nmovq $0x0,-0x68(%rbp)\nmovq $0x0,-0x60(%rbp)\nmovq $0x0,-0x58(%rbp)\nmovq $0x0,-0x50(%rbp)\nmovq $0x0,-0x48(%rbp)\nmovq $0x0,-0x40(%rbp)\nmovq $0x0,-0x38(%rbp)\nmovq $0x0,-0x30(%rbp)\nmovq $0x0,-0x28(%rbp)\nmovq $0x0,-0x20(%rbp)\nmovq $0x0,-0x18(%rbp)\nmovl $0x0,-0x10(%rbp)\nmovl $0x0,-0x7c(%rbp)\njmp 12a9 \nmov -0x7c(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x88(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmov %al,-0x7d(%rbp)\nmovsbl -0x7d(%rbp),%eax\nmov %eax,%esi\nlea 0xd80(%rip),%rdi\ncallq 10b0 \ntest %rax,%rax\nje 12a5 \nmov -0x78(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x78(%rbp)\ncltq\nmovzbl -0x7d(%rbp),%edx\nmov %dl,-0x70(%rbp,%rax,1)\naddl $0x1,-0x7c(%rbp)\nmov -0x7c(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x88(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 1265 \nmov -0x78(%rbp),%eax\ncltq\nmovb $0x0,-0x70(%rbp,%rax,1)\nmovl $0x0,-0x78(%rbp)\nlea -0x70(%rbp),%rax\nmov %rax,%rdi\ncallq 1090 \nsub $0x1,%eax\nmov %eax,-0x74(%rbp)\nmovl $0x0,-0x7c(%rbp)\njmpq 1371 \nmov -0x7c(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x88(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmov %al,-0x7e(%rbp)\nmovsbl -0x7e(%rbp),%eax\nmov %eax,%esi\nlea 0xcf6(%rip),%rdi\ncallq 10b0 \ntest %rax,%rax\nje 1344 \nmov -0x74(%rbp),%edx\nlea -0x1(%rdx),%eax\nmov %eax,-0x74(%rbp)\nmov -0x78(%rbp),%eax\nlea 0x1(%rax),%ecx\nmov %ecx,-0x78(%rbp)\nmovslq %edx,%rdx\nmovzbl -0x70(%rbp,%rdx,1),%edx\ncltq\nlea 0x2d01(%rip),%rcx\nmov %dl,(%rax,%rcx,1)\njmp 136d \nmov -0x7c(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x88(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x78(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x78(%rbp)\nmovzbl (%rcx),%edx\ncltq\nlea 0x2cd6(%rip),%rcx\nmov %dl,(%rax,%rcx,1)\naddl $0x1,-0x7c(%rbp)\nmov -0x7c(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x88(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 12ef \nmov -0x78(%rbp),%eax\ncltq\nlea 0x2ca8(%rip),%rdx\nmovb $0x0,(%rax,%rdx,1)\nlea 0x2c9d(%rip),%rax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 13b7 \ncallq 10a0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 90h\nmov [rbp+var_88], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_78], 0\nmov qword ptr [rbp+s], 0\nmov [rbp+var_68], 0\nmov [rbp+var_60], 0\nmov [rbp+var_58], 0\nmov [rbp+var_50], 0\nmov [rbp+var_48], 0\nmov [rbp+var_40], 0\nmov [rbp+var_38], 0\nmov [rbp+var_30], 0\nmov [rbp+var_28], 0\nmov [rbp+var_20], 0\nmov [rbp+var_18], 0\nmov [rbp+var_10], 0\nmov [rbp+var_7C], 0\njmp short loc_12AC\nloc_1265:\nmov eax, [rbp+var_7C]\nmovsxd rdx, eax\nmov rax, [rbp+var_88]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_7D], al\nmovsx eax, [rbp+var_7D]\nmov esi, eax; c\nlea rax, s; \"aeiouAEIOU\"\nmov rdi, rax; s\ncall _strchr\ntest rax, rax\njz short loc_12A8\nmov eax, [rbp+var_78]\nlea edx, [rax+1]\nmov [rbp+var_78], edx\ncdqe\nmovzx edx, [rbp+var_7D]\nmov [rbp+rax+s], dl\nloc_12A8:\nadd [rbp+var_7C], 1\nloc_12AC:\nmov eax, [rbp+var_7C]\nmovsxd rdx, eax\nmov rax, [rbp+var_88]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1265\nmov eax, [rbp+var_78]\ncdqe\nmov [rbp+rax+s], 0\nmov [rbp+var_78], 0\nlea rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nsub eax, 1\nmov [rbp+var_74], eax\nmov [rbp+var_7C], 0\njmp loc_1377\nloc_12F2:\nmov eax, [rbp+var_7C]\nmovsxd rdx, eax\nmov rax, [rbp+var_88]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_7E], al\nmovsx eax, [rbp+var_7E]\nmov esi, eax; c\nlea rax, s; \"aeiouAEIOU\"\nmov rdi, rax; s\ncall _strchr\ntest rax, rax\njz short loc_134A\nmov edx, [rbp+var_74]\nlea eax, [rdx-1]\nmov [rbp+var_74], eax\nmov eax, [rbp+var_78]\nlea ecx, [rax+1]\nmov [rbp+var_78], ecx\nmovsxd rdx, edx\nmovzx edx, [rbp+rdx+s]\ncdqe\nlea rcx, result_string_1\nmov [rax+rcx], dl\njmp short loc_1373\nloc_134A:\nmov eax, [rbp+var_7C]\nmovsxd rdx, eax\nmov rax, [rbp+var_88]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_78]\nlea edx, [rax+1]\nmov [rbp+var_78], edx\nmovzx edx, byte ptr [rcx]\ncdqe\nlea rcx, result_string_1\nmov [rax+rcx], dl\nloc_1373:\nadd [rbp+var_7C], 1\nloc_1377:\nmov eax, [rbp+var_7C]\nmovsxd rdx, eax\nmov rax, [rbp+var_88]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_12F2\nmov eax, [rbp+var_78]\ncdqe\nlea rdx, result_string_1\nmov byte ptr [rax+rdx], 0\nlea rax, result_string_1\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_13BD\ncall ___stack_chk_fail\nlocret_13BD:\nleave\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(__int64 a1)\n{\n int v1; // eax\n int v2; // edx\n int v3; // eax\n char v4; // dl\n char v6; // [rsp+13h] [rbp-7Dh]\n int i; // [rsp+14h] [rbp-7Ch]\n int j; // [rsp+14h] [rbp-7Ch]\n int v9; // [rsp+18h] [rbp-78h]\n int v10; // [rsp+18h] [rbp-78h]\n int v11; // [rsp+1Ch] [rbp-74h]\n char s[8]; // [rsp+20h] [rbp-70h] BYREF\n __int64 v13; // [rsp+28h] [rbp-68h]\n __int64 v14; // [rsp+30h] [rbp-60h]\n __int64 v15; // [rsp+38h] [rbp-58h]\n __int64 v16; // [rsp+40h] [rbp-50h]\n __int64 v17; // [rsp+48h] [rbp-48h]\n __int64 v18; // [rsp+50h] [rbp-40h]\n __int64 v19; // [rsp+58h] [rbp-38h]\n __int64 v20; // [rsp+60h] [rbp-30h]\n __int64 v21; // [rsp+68h] [rbp-28h]\n __int64 v22; // [rsp+70h] [rbp-20h]\n __int64 v23; // [rsp+78h] [rbp-18h]\n int v24; // [rsp+80h] [rbp-10h]\n unsigned __int64 v25; // [rsp+88h] [rbp-8h]\n\n v25 = __readfsqword(0x28u);\n v9 = 0;\n *(_QWORD *)s = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0LL;\n v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n v22 = 0LL;\n v23 = 0LL;\n v24 = 0;\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n {\n v6 = *(_BYTE *)(i + a1);\n if ( strchr(\"aeiouAEIOU\", v6) )\n {\n v1 = v9++;\n s[v1] = v6;\n }\n }\n s[v9] = 0;\n v10 = 0;\n v11 = strlen(s) - 1;\n for ( j = 0; *(_BYTE *)(j + a1); ++j )\n {\n if ( strchr(\"aeiouAEIOU\", *(char *)(j + a1)) )\n {\n v2 = v11--;\n v3 = v10++;\n v4 = s[v2];\n }\n else\n {\n v3 = v10++;\n v4 = *(_BYTE *)(j + a1);\n }\n result_string_1[v3] = v4;\n }\n result_string_1[v10] = 0;\n return result_string_1;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 90h\nmov [rbp+var_88], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_78], 0\nmov qword ptr [rbp+s], 0\nmov [rbp+var_68], 0\nmov [rbp+var_60], 0\nmov [rbp+var_58], 0\nmov [rbp+var_50], 0\nmov [rbp+var_48], 0\nmov [rbp+var_40], 0\nmov [rbp+var_38], 0\nmov [rbp+var_30], 0\nmov [rbp+var_28], 0\nmov [rbp+var_20], 0\nmov [rbp+var_18], 0\nmov [rbp+var_10], 0\nmov [rbp+var_7C], 0\njmp short loc_12AC\nloc_1265:\nmov eax, [rbp+var_7C]\nmovsxd rdx, eax\nmov rax, [rbp+var_88]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_7D], al\nmovsx eax, [rbp+var_7D]\nmov esi, eax; c\nlea rax, s; \"aeiouAEIOU\"\nmov rdi, rax; s\ncall _strchr\ntest rax, rax\njz short loc_12A8\nmov eax, [rbp+var_78]\nlea edx, [rax+1]\nmov [rbp+var_78], edx\ncdqe\nmovzx edx, [rbp+var_7D]\nmov [rbp+rax+s], dl\nloc_12A8:\nadd [rbp+var_7C], 1\nloc_12AC:\nmov eax, [rbp+var_7C]\nmovsxd rdx, eax\nmov rax, [rbp+var_88]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1265\nmov eax, [rbp+var_78]\ncdqe\nmov [rbp+rax+s], 0\nmov [rbp+var_78], 0\nlea rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nsub eax, 1\nmov [rbp+var_74], eax\nmov [rbp+var_7C], 0\njmp loc_1377\nloc_12F2:\nmov eax, [rbp+var_7C]\nmovsxd rdx, eax\nmov rax, [rbp+var_88]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_7E], al\nmovsx eax, [rbp+var_7E]\nmov esi, eax; c\nlea rax, s; \"aeiouAEIOU\"\nmov rdi, rax; s\ncall _strchr\ntest rax, rax\njz short loc_134A\nmov edx, [rbp+var_74]\nlea eax, [rdx-1]\nmov [rbp+var_74], eax\nmov eax, [rbp+var_78]\nlea ecx, [rax+1]\nmov [rbp+var_78], ecx\nmovsxd rdx, edx\nmovzx edx, [rbp+rdx+s]\ncdqe\nlea rcx, unk_4040\nmov [rax+rcx], dl\njmp short loc_1373\nloc_134A:\nmov eax, [rbp+var_7C]\nmovsxd rdx, eax\nmov rax, [rbp+var_88]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_78]\nlea edx, [rax+1]\nmov [rbp+var_78], edx\nmovzx edx, byte ptr [rcx]\ncdqe\nlea rcx, unk_4040\nmov [rax+rcx], dl\nloc_1373:\nadd [rbp+var_7C], 1\nloc_1377:\nmov eax, [rbp+var_7C]\nmovsxd rdx, eax\nmov rax, [rbp+var_88]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_12F2\nmov eax, [rbp+var_78]\ncdqe\nlea rdx, unk_4040\nmov byte ptr [rax+rdx], 0\nlea rax, unk_4040\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_13BD\ncall ___stack_chk_fail\nlocret_13BD:\nleave\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_11C9(__int64 a1)\n{\n int v1; // eax\n int v2; // edx\n int v3; // eax\n char v4; // dl\n char v6; // [rsp+13h] [rbp-7Dh]\n int i; // [rsp+14h] [rbp-7Ch]\n int j; // [rsp+14h] [rbp-7Ch]\n int v9; // [rsp+18h] [rbp-78h]\n int v10; // [rsp+18h] [rbp-78h]\n int v11; // [rsp+1Ch] [rbp-74h]\n char s[8]; // [rsp+20h] [rbp-70h] BYREF\n __int64 v13; // [rsp+28h] [rbp-68h]\n __int64 v14; // [rsp+30h] [rbp-60h]\n __int64 v15; // [rsp+38h] [rbp-58h]\n __int64 v16; // [rsp+40h] [rbp-50h]\n __int64 v17; // [rsp+48h] [rbp-48h]\n __int64 v18; // [rsp+50h] [rbp-40h]\n __int64 v19; // [rsp+58h] [rbp-38h]\n __int64 v20; // [rsp+60h] [rbp-30h]\n __int64 v21; // [rsp+68h] [rbp-28h]\n __int64 v22; // [rsp+70h] [rbp-20h]\n __int64 v23; // [rsp+78h] [rbp-18h]\n int v24; // [rsp+80h] [rbp-10h]\n unsigned __int64 v25; // [rsp+88h] [rbp-8h]\n\n v25 = __readfsqword(0x28u);\n v9 = 0;\n *(_QWORD *)s = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0LL;\n v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n v22 = 0LL;\n v23 = 0LL;\n v24 = 0;\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n {\n v6 = *(_BYTE *)(i + a1);\n if ( strchr(\"aeiouAEIOU\", v6) )\n {\n v1 = v9++;\n s[v1] = v6;\n }\n }\n s[v9] = 0;\n v10 = 0;\n v11 = strlen(s) - 1;\n for ( j = 0; *(_BYTE *)(j + a1); ++j )\n {\n if ( strchr(\"aeiouAEIOU\", *(char *)(j + a1)) )\n {\n v2 = v11--;\n v3 = v10++;\n v4 = s[v2];\n }\n else\n {\n v3 = v10++;\n v4 = *(_BYTE *)(j + a1);\n }\n byte_4040[v3] = v4;\n }\n byte_4040[v10] = 0;\n return byte_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_11C9(long long a1) {\n int v1;\n int v2;\n int v3;\n char v4;\n char v6;\n int i;\n int j;\n int v9;\n int v10;\n int v11;\n char s[8];\n long long v13;\n long long v14;\n long long v15;\n long long v16;\n long long v17;\n long long v18;\n long long v19;\n long long v20;\n long long v21;\n long long v22;\n long long v23;\n int v24;\n unsigned long long v25;\n v25 = __readfsqword(40u);\n v9 = 0;\n *(uint64_t *)s = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0LL;\n v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n v22 = 0LL;\n v23 = 0LL;\n v24 = 0;\n for (i = 0; *(uint8_t *)(i + a1); ++i) {\n v6 = *(uint8_t *)(i + a1);\n if (strchr(\"aeiouAEIOU\", v6)) {\n v1 = v9++;\n s[v1] = v6;\n }\n }\n s[v9] = 0;\n v10 = 0;\n v11 = strlen(s) - 1;\n for (j = 0; *(uint8_t *)(j + a1); ++j) {\n if (strchr(\"aeiouAEIOU\", *(char *)(j + a1))) {\n v2 = v11--;\n v3 = v10++;\n v4 = s[v2];\n } else {\n v3 = v10++;\n v4 = *(uint8_t *)(j + a1);\n }\n byte_4040[v3] = v4;\n }\n byte_4040[v10] = 0;\n return byte_4040;\n}", + "ida_pseudo_norm": "uint8_t *func0(long long a1) {\n int v1;\n int v2;\n int v3;\n char v4;\n char v6;\n int i;\n int j;\n int v9;\n int v10;\n int v11;\n char s[8];\n long long v13;\n long long v14;\n long long v15;\n long long v16;\n long long v17;\n long long v18;\n long long v19;\n long long v20;\n long long v21;\n long long v22;\n long long v23;\n int v24;\n unsigned long long v25;\n v25 = __readfsqword(40u);\n v9 = 0;\n *(uint64_t *)s = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0LL;\n v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n v22 = 0LL;\n v23 = 0LL;\n v24 = 0;\n for (i = 0; *(uint8_t *)(i + a1); ++i) {\n v6 = *(uint8_t *)(i + a1);\n if (strchr(\"aeiouAEIOU\", v6)) {\n v1 = v9++;\n s[v1] = v6;\n }\n }\n s[v9] = 0;\n v10 = 0;\n v11 = strlen(s) - 1;\n for (j = 0; *(uint8_t *)(j + a1); ++j) {\n if (strchr(\"aeiouAEIOU\", *(char *)(j + a1))) {\n v2 = v11--;\n v3 = v10++;\n v4 = s[v2];\n } else {\n v3 = v10++;\n v4 = *(uint8_t *)(j + a1);\n }\n result_string_1[v3] = v4;\n }\n result_string_1[v10] = 0;\n return result_string_1;\n}" + }, + { + "index": 131, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* str1) {\n static char result_string[100];\n int i, j = 0;\n char vowels[100] = \"\";\n for (i = 0; str1[i] != '\\0'; i++) {\n char char1 = str1[i];\n if (strchr(\"aeiouAEIOU\", char1) != NULL) {\n vowels[j++] = char1;\n }\n }\n vowels[j] = '\\0';\n j = 0;\n int k = strlen(vowels) - 1;\n for (i = 0; str1[i] != '\\0'; i++) {\n char char1 = str1[i];\n if (strchr(\"aeiouAEIOU\", char1) != NULL) {\n result_string[j++] = vowels[k--];\n } else {\n result_string[j++] = str1[i];\n }\n }\n result_string[j] = '\\0';\n return result_string;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"Python\"), \"Python\") == 0);\n\n assert(strcmp(func0(\"USA\"), \"ASU\") == 0);\n\n assert(strcmp(func0(\"ab\"), \"ab\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x78,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x68(%rsp)\nxor %eax,%eax\nmovq $0x0,(%rsp)\nmovq $0x0,0x8(%rsp)\nmovq $0x0,0x10(%rsp)\nmovq $0x0,0x18(%rsp)\nmovq $0x0,0x20(%rsp)\nmovq $0x0,0x28(%rsp)\nmovq $0x0,0x30(%rsp)\nmovq $0x0,0x38(%rsp)\nmovq $0x0,0x40(%rsp)\nmovq $0x0,0x48(%rsp)\nmovq $0x0,0x50(%rsp)\nmovq $0x0,0x58(%rsp)\nmovl $0x0,0x60(%rsp)\nmovzbl (%rdi),%ebp\ntest %bpl,%bpl\nje 12a0 \nmov %rdi,%r13\nlea 0x1(%rdi),%r12\nmov %ebp,%ebx\nmov $0x0,%r14d\nlea 0xdc8(%rip),%r15\njmp 1250 \nadd $0x1,%r12\nmovzbl -0x1(%r12),%ebx\ntest %bl,%bl\nje 12d5 \nmovsbl %bl,%esi\nmov %r15,%rdi\ncallq 1080 \ntest %rax,%rax\nje 123e \nmovslq %r14d,%rax\nmov %bl,(%rsp,%rax,1)\nlea 0x1(%r14),%r14d\njmp 123e \nmov %bpl,(%rbx,%r14,1)\nadd $0x1,%rbx\nmovzbl -0x1(%r13,%rbx,1),%ebp\ntest %bpl,%bpl\nje 12a5 \nmovsbl %bpl,%esi\nmov %r15,%rdi\ncallq 1080 \nmov %ebx,%ecx\ntest %rax,%rax\nje 126c \nmovslq %r12d,%rdx\nmovzbl (%rsp,%rdx,1),%ebp\nlea -0x1(%r12),%r12d\njmp 126c \nmov $0x0,%ecx\nlea 0x2d94(%rip),%rdx\nmovslq %ecx,%rax\nmovb $0x0,(%rdx,%rax,1)\nmov 0x68(%rsp),%rax\nxor %fs:0x28,%rax\njne 130d \nmov %rdx,%rax\nadd $0x78,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmovslq %r14d,%r14\nmovb $0x0,(%rsp,%r14,1)\nmov %rsp,%rdi\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nlea -0x2(%rcx),%r12d\nmov $0x1,%ebx\nlea 0xd03(%rip),%r15\nlea 0x2d37(%rip),%r14\njmpq 127f \ncallq 1070 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 78h\nmov rax, fs:28h\nmov [rsp+0A8h+var_40], rax\nxor eax, eax\nmov [rsp+0A8h+var_A8], 0\nmov [rsp+0A8h+var_A0], 0\nmov [rsp+0A8h+var_98], 0\nmov [rsp+0A8h+var_90], 0\nmov [rsp+0A8h+var_88], 0\nmov [rsp+0A8h+var_80], 0\nmov [rsp+0A8h+var_78], 0\nmov [rsp+0A8h+var_70], 0\nmov [rsp+0A8h+var_68], 0\nmov [rsp+0A8h+var_60], 0\nmov [rsp+0A8h+var_58], 0\nmov [rsp+0A8h+var_50], 0\nmov [rsp+0A8h+var_48], 0\nmovzx ebp, byte ptr [rdi]\ntest bpl, bpl\njz loc_1309\nmov r14, rdi\nlea r12, [rdi+1]\nmov ebx, ebp\nmov r13d, 0\nlea r15, s; \"aeiouAEIOU\"\njmp short loc_129A\nloc_1282:\nmovsxd rax, r13d\nmov byte ptr [rsp+rax+0A8h+var_A8], bl\nlea r13d, [r13+1]\nloc_128C:\nadd r12, 1\nmovzx ebx, byte ptr [r12-1]\ntest bl, bl\njz short loc_12AC\nloc_129A:\nmovsx esi, bl; c\nmov rdi, r15; s\ncall _strchr\ntest rax, rax\njnz short loc_1282\njmp short loc_128C\nloc_12AC:\nmovsxd r13, r13d\nmov byte ptr [rsp+r13+0A8h+var_A8], 0\nmov rdi, rsp; s\ncall _strlen\nlea r12d, [rax-1]\nmov ebx, 1\nlea r15, s; \"aeiouAEIOU\"\nlea r13, unk_403F\njmp short loc_12E8\nloc_12D5:\nmov [rbx+r13], bpl\nadd rbx, 1\nmovzx ebp, byte ptr [r14+rbx-1]\ntest bpl, bpl\njz short loc_130E\nloc_12E8:\nmovsx esi, bpl; c\nmov rdi, r15; s\ncall _strchr\nmov ecx, ebx\ntest rax, rax\njz short loc_12D5\nmovsxd rdx, r12d\nmovzx ebp, byte ptr [rsp+rdx+0A8h+var_A8]\nlea r12d, [r12-1]\njmp short loc_12D5\nloc_1309:\nmov ecx, 0\nloc_130E:\nlea rdx, result_string_1\nmovsxd rax, ecx\nmov byte ptr [rdx+rax], 0\nmov rax, [rsp+0A8h+var_40]\nsub rax, fs:28h\njnz short loc_133E\nmov rax, rdx\nadd rsp, 78h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_133E:\ncall ___stack_chk_fail", + "ida_pseudo": "_BYTE *__fastcall func0(char *a1)\n{\n char v1; // bp\n char *v2; // r12\n char v3; // bl\n int v4; // r13d\n int v5; // r12d\n __int64 v6; // rbx\n char *v7; // rax\n int v8; // ecx\n _QWORD v10[12]; // [rsp+0h] [rbp-A8h] BYREF\n int v11; // [rsp+60h] [rbp-48h]\n unsigned __int64 v12; // [rsp+68h] [rbp-40h]\n\n v12 = __readfsqword(0x28u);\n memset(v10, 0, sizeof(v10));\n v11 = 0;\n v1 = *a1;\n if ( *a1 )\n {\n v2 = a1 + 1;\n v3 = *a1;\n v4 = 0;\n do\n {\n if ( strchr(\"aeiouAEIOU\", v3) )\n *((_BYTE *)v10 + v4++) = v3;\n v3 = *v2++;\n }\n while ( v3 );\n *((_BYTE *)v10 + v4) = 0;\n v5 = strlen((const char *)v10) - 1;\n v6 = 1LL;\n do\n {\n v7 = strchr(\"aeiouAEIOU\", v1);\n v8 = v6;\n if ( v7 )\n v1 = *((_BYTE *)v10 + v5--);\n *((_BYTE *)&unk_403F + v6++) = v1;\n v1 = a1[v6 - 1];\n }\n while ( v1 );\n }\n else\n {\n v8 = 0;\n }\n result_string_1[v8] = 0;\n return result_string_1;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 78h\nmov rax, fs:28h\nmov [rsp+0A8h+var_40], rax\nxor eax, eax\nmov [rsp+0A8h+var_A8], 0\nmov [rsp+0A8h+var_A0], 0\nmov [rsp+0A8h+var_98], 0\nmov [rsp+0A8h+var_90], 0\nmov [rsp+0A8h+var_88], 0\nmov [rsp+0A8h+var_80], 0\nmov [rsp+0A8h+var_78], 0\nmov [rsp+0A8h+var_70], 0\nmov [rsp+0A8h+var_68], 0\nmov [rsp+0A8h+var_60], 0\nmov [rsp+0A8h+var_58], 0\nmov [rsp+0A8h+var_50], 0\nmov [rsp+0A8h+var_48], 0\nmovzx ebp, byte ptr [rdi]\ntest bpl, bpl\njz loc_1309\nmov r14, rdi\nlea r12, [rdi+1]\nmov ebx, ebp\nmov r13d, 0\nlea r15, s; \"aeiouAEIOU\"\njmp short loc_129A\nloc_1282:\nmovsxd rax, r13d\nmov byte ptr [rsp+rax+0A8h+var_A8], bl\nlea r13d, [r13+1]\nloc_128C:\nadd r12, 1\nmovzx ebx, byte ptr [r12-1]\ntest bl, bl\njz short loc_12AC\nloc_129A:\nmovsx esi, bl; c\nmov rdi, r15; s\ncall _strchr\ntest rax, rax\njnz short loc_1282\njmp short loc_128C\nloc_12AC:\nmovsxd r13, r13d\nmov byte ptr [rsp+r13+0A8h+var_A8], 0\nmov rdi, rsp; s\ncall _strlen\nlea r12d, [rax-1]\nmov ebx, 1\nlea r15, s; \"aeiouAEIOU\"\nlea r13, unk_403F\njmp short loc_12E8\nloc_12D5:\nmov [rbx+r13], bpl\nadd rbx, 1\nmovzx ebp, byte ptr [r14+rbx-1]\ntest bpl, bpl\njz short loc_130E\nloc_12E8:\nmovsx esi, bpl; c\nmov rdi, r15; s\ncall _strchr\nmov ecx, ebx\ntest rax, rax\njz short loc_12D5\nmovsxd rdx, r12d\nmovzx ebp, byte ptr [rsp+rdx+0A8h+var_A8]\nlea r12d, [r12-1]\njmp short loc_12D5\nloc_1309:\nmov ecx, 0\nloc_130E:\nlea rdx, unk_4040\nmovsxd rax, ecx\nmov byte ptr [rdx+rax], 0\nmov rax, [rsp+0A8h+var_40]\nsub rax, fs:28h\njnz short loc_133E\nmov rax, rdx\nadd rsp, 78h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_133E:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_BYTE *__fastcall sub_11C9(char *a1)\n{\n char v1; // bp\n char *v2; // r12\n char v3; // bl\n int v4; // r13d\n int v5; // r12d\n __int64 v6; // rbx\n char *v7; // rax\n int v8; // ecx\n _QWORD v10[12]; // [rsp+0h] [rbp-A8h] BYREF\n int v11; // [rsp+60h] [rbp-48h]\n unsigned __int64 v12; // [rsp+68h] [rbp-40h]\n\n v12 = __readfsqword(0x28u);\n memset(v10, 0, sizeof(v10));\n v11 = 0;\n v1 = *a1;\n if ( *a1 )\n {\n v2 = a1 + 1;\n v3 = *a1;\n v4 = 0;\n do\n {\n if ( strchr(\"aeiouAEIOU\", v3) )\n *((_BYTE *)v10 + v4++) = v3;\n v3 = *v2++;\n }\n while ( v3 );\n *((_BYTE *)v10 + v4) = 0;\n v5 = strlen((const char *)v10) - 1;\n v6 = 1LL;\n do\n {\n v7 = strchr(\"aeiouAEIOU\", v1);\n v8 = v6;\n if ( v7 )\n v1 = *((_BYTE *)v10 + v5--);\n *((_BYTE *)&unk_403F + v6++) = v1;\n v1 = a1[v6 - 1];\n }\n while ( v1 );\n }\n else\n {\n v8 = 0;\n }\n byte_4040[v8] = 0;\n return byte_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_11C9(char *a1) {\n char v1;\n char *v2;\n char v3;\n int v4;\n int v5;\n long long v6;\n char *v7;\n int v8;\n uint64_t v10[12];\n int v11;\n unsigned long long v12;\n v12 = __readfsqword(40u);\n memset(v10, 0, sizeof(v10));\n v11 = 0;\n v1 = *a1;\n if (*a1) {\n v2 = a1 + 1;\n v3 = *a1;\n v4 = 0;\n do {\n if (strchr(\"aeiouAEIOU\", v3)) *((uint8_t *)v10 + v4++) = v3;\n v3 = *v2++;\n } while (v3);\n *((uint8_t *)v10 + v4) = 0;\n v5 = strlen((const char *)v10) - 1;\n v6 = 1LL;\n do {\n v7 = strchr(\"aeiouAEIOU\", v1);\n v8 = v6;\n if (v7) v1 = *((uint8_t *)v10 + v5--);\n *((uint8_t *)&unk_403F + v6++) = v1;\n v1 = a1[v6 - 1];\n } while (v1);\n } else {\n v8 = 0;\n }\n byte_4040[v8] = 0;\n return byte_4040;\n}", + "ida_pseudo_norm": "uint8_t *func0(char *a1) {\n char v1;\n char *v2;\n char v3;\n int v4;\n int v5;\n long long v6;\n char *v7;\n int v8;\n uint64_t v10[12];\n int v11;\n unsigned long long v12;\n v12 = __readfsqword(40u);\n memset(v10, 0, sizeof(v10));\n v11 = 0;\n v1 = *a1;\n if (*a1) {\n v2 = a1 + 1;\n v3 = *a1;\n v4 = 0;\n do {\n if (strchr(\"aeiouAEIOU\", v3)) *((uint8_t *)v10 + v4++) = v3;\n v3 = *v2++;\n } while (v3);\n *((uint8_t *)v10 + v4) = 0;\n v5 = strlen((const char *)v10) - 1;\n v6 = 1LL;\n do {\n v7 = strchr(\"aeiouAEIOU\", v1);\n v8 = v6;\n if (v7) v1 = *((uint8_t *)v10 + v5--);\n *((uint8_t *)&unk_403F + v6++) = v1;\n v1 = a1[v6 - 1];\n } while (v1);\n } else {\n v8 = 0;\n }\n result_string_1[v8] = 0;\n return result_string_1;\n}" + }, + { + "index": 131, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* str1) {\n static char result_string[100];\n int i, j = 0;\n char vowels[100] = \"\";\n for (i = 0; str1[i] != '\\0'; i++) {\n char char1 = str1[i];\n if (strchr(\"aeiouAEIOU\", char1) != NULL) {\n vowels[j++] = char1;\n }\n }\n vowels[j] = '\\0';\n j = 0;\n int k = strlen(vowels) - 1;\n for (i = 0; str1[i] != '\\0'; i++) {\n char char1 = str1[i];\n if (strchr(\"aeiouAEIOU\", char1) != NULL) {\n result_string[j++] = vowels[k--];\n } else {\n result_string[j++] = str1[i];\n }\n }\n result_string[j] = '\\0';\n return result_string;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"Python\"), \"Python\") == 0);\n\n assert(strcmp(func0(\"USA\"), \"ASU\") == 0);\n\n assert(strcmp(func0(\"ab\"), \"ab\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npxor %xmm0,%xmm0\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x78,%rsp\nmovzbl (%rdi),%ebp\nmov %fs:0x28,%rax\nmov %rax,0x68(%rsp)\nxor %eax,%eax\nmovl $0x0,0x60(%rsp)\nmovaps %xmm0,(%rsp)\nmovaps %xmm0,0x10(%rsp)\nmovaps %xmm0,0x20(%rsp)\nmovaps %xmm0,0x30(%rsp)\nmovaps %xmm0,0x40(%rsp)\nmovaps %xmm0,0x50(%rsp)\ntest %bpl,%bpl\nje 13d0 \nmov %rdi,%r13\nlea 0x1(%rdi),%r12\nmov %ebp,%ebx\nxor %r14d,%r14d\nlea 0xd2a(%rip),%r15\nnopw 0x0(%rax,%rax,1)\nmovsbl %bl,%esi\nmov %r15,%rdi\ncallq 1080 \ntest %rax,%rax\nje 12fa \nmovslq %r14d,%rax\nadd $0x1,%r14d\nmov %bl,(%rsp,%rax,1)\nmovzbl (%r12),%ebx\nadd $0x1,%r12\ntest %bl,%bl\njne 12e0 \nmovslq %r14d,%r14\nmov %rsp,%rsi\nmovb $0x0,(%rsp,%r14,1)\nmov %rsi,%rax\nmov (%rax),%ecx\nadd $0x4,%rax\nlea -0x1010101(%rcx),%edx\nnot %ecx\nand %ecx,%edx\nand $0x80808080,%edx\nje 1315 \nmov %edx,%ecx\nmov $0x1,%ebx\nlea 0x2d04(%rip),%r15\nshr $0x10,%ecx\ntest $0x8080,%edx\nlea 0xcb9(%rip),%r14\ncmove %ecx,%edx\nlea 0x2(%rax),%rcx\ncmove %rcx,%rax\nmov %edx,%edi\nadd %dl,%dil\nsbb $0x3,%rax\nsub %rsi,%rax\nlea -0x1(%rax),%r12d\nnopw %cs:0x0(%rax,%rax,1)\nmovsbl %bpl,%esi\nmov %r14,%rdi\ncallq 1080 \nmovslq %ebx,%rdx\ntest %rax,%rax\nje 138f \nmovslq %r12d,%rax\nsub $0x1,%r12d\nmovzbl (%rsp,%rax,1),%ebp\nmov %bpl,(%r15,%rbx,1)\nadd $0x1,%rbx\nmovzbl -0x1(%r13,%rbx,1),%ebp\ntest %bpl,%bpl\njne 1370 \nlea 0x2c97(%rip),%rax\nmovb $0x0,(%rax,%rdx,1)\nmov 0x68(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 13d4 \nadd $0x78,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\nxor %edx,%edx\njmp 13a2 \ncallq 1070 <__stack_chk_fail@plt>\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npxor xmm0, xmm0\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 78h\nmovzx ebx, byte ptr [rdi]\nmov rax, fs:28h\nmov [rsp+0A8h+var_40], rax\nxor eax, eax\nmov [rsp+0A8h+var_48], 0\nmovaps [rsp+0A8h+var_A8], xmm0\nmovaps [rsp+0A8h+var_98], xmm0\nmovaps [rsp+0A8h+var_88], xmm0\nmovaps [rsp+0A8h+var_78], xmm0\nmovaps [rsp+0A8h+var_68], xmm0\nmovaps [rsp+0A8h+var_58], xmm0\ntest bl, bl\njz loc_13B0\nmov r14, rdi\nlea r12, [rdi+1]\nmov ebp, ebx\nxor r15d, r15d\nlea r13, s; \"aeiouAEIOU\"\nnop dword ptr [rax+00000000h]\nloc_1300:\nmovsx esi, bpl; c\nmov rdi, r13; s\ncall _strchr\ntest rax, rax\njz short loc_131C\nmovsxd rax, r15d\nadd r15d, 1\nmov byte ptr [rsp+rax+0A8h+var_A8], bpl\nloc_131C:\nmovzx ebp, byte ptr [r12]\nadd r12, 1\ntest bpl, bpl\njnz short loc_1300\nmovsxd r15, r15d\nmov rdi, rsp; s\nmov ebp, 1\nmov byte ptr [rsp+r15+0A8h+var_A8], 0\nlea r12, unk_403F\ncall _strlen\nlea r15d, [rax-1]\njmp short loc_1353\nloc_1350:\nmov rbp, rax\nloc_1353:\nmovsx esi, bl; c\nmov rdi, r13; s\ncall _strchr\ntest rax, rax\njz short loc_136E\nmovsxd rax, r15d\nsub r15d, 1\nmovzx ebx, byte ptr [rsp+rax+0A8h+var_A8]\nloc_136E:\nlea rax, [rbp+1]\nmov [r12+rbp], bl\nmovzx ebx, byte ptr [r14+rax-1]\ntest bl, bl\njnz short loc_1350\nloc_1380:\nlea rax, result_string_1\nmovsxd rbp, ebp\nmov byte ptr [rax+rbp], 0\nmov rdx, [rsp+0A8h+var_40]\nsub rdx, fs:28h\njnz short loc_13B4\nadd rsp, 78h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_13B0:\nxor ebp, ebp\njmp short loc_1380\nloc_13B4:\ncall ___stack_chk_fail", + "ida_pseudo": "_BYTE *__fastcall func0(char *a1)\n{\n char v1; // bl\n char *v2; // r12\n char v3; // bp\n int v4; // r15d\n __int64 v5; // rax\n __int64 v6; // rbp\n int v7; // r15d\n __int64 v8; // rax\n _BYTE *result; // rax\n _OWORD v10[6]; // [rsp+0h] [rbp-A8h] BYREF\n int v11; // [rsp+60h] [rbp-48h]\n unsigned __int64 v12; // [rsp+68h] [rbp-40h]\n\n v1 = *a1;\n v12 = __readfsqword(0x28u);\n v11 = 0;\n memset(v10, 0, sizeof(v10));\n if ( v1 )\n {\n v2 = a1 + 1;\n v3 = v1;\n v4 = 0;\n do\n {\n if ( strchr(\"aeiouAEIOU\", v3) )\n {\n v5 = v4++;\n *((_BYTE *)v10 + v5) = v3;\n }\n v3 = *v2++;\n }\n while ( v3 );\n v6 = 1LL;\n *((_BYTE *)v10 + v4) = 0;\n v7 = strlen((const char *)v10) - 1;\n while ( 1 )\n {\n if ( strchr(\"aeiouAEIOU\", v1) )\n {\n v8 = v7--;\n v1 = *((_BYTE *)v10 + v8);\n }\n *((_BYTE *)&unk_403F + v6) = v1;\n v1 = a1[v6];\n if ( !v1 )\n break;\n ++v6;\n }\n }\n else\n {\n LODWORD(v6) = 0;\n }\n result = result_string_1;\n result_string_1[(int)v6] = 0;\n return result;\n}", + "ida_strip_asm": "sub_1290:\nendbr64\npush r15\npxor xmm0, xmm0\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 78h\nmovzx ebx, byte ptr [rdi]\nmov rax, fs:28h\nmov [rsp+0A8h+var_40], rax\nxor eax, eax\nmov [rsp+0A8h+var_48], 0\nmovaps [rsp+0A8h+var_A8], xmm0\nmovaps [rsp+0A8h+var_98], xmm0\nmovaps [rsp+0A8h+var_88], xmm0\nmovaps [rsp+0A8h+var_78], xmm0\nmovaps [rsp+0A8h+var_68], xmm0\nmovaps [rsp+0A8h+var_58], xmm0\ntest bl, bl\njz loc_13B0\nmov r14, rdi\nlea r12, [rdi+1]\nmov ebp, ebx\nxor r15d, r15d\nlea r13, s; \"aeiouAEIOU\"\nnop dword ptr [rax+00000000h]\nloc_1300:\nmovsx esi, bpl; c\nmov rdi, r13; s\ncall _strchr\ntest rax, rax\njz short loc_131C\nmovsxd rax, r15d\nadd r15d, 1\nmov byte ptr [rsp+rax+0A8h+var_A8], bpl\nloc_131C:\nmovzx ebp, byte ptr [r12]\nadd r12, 1\ntest bpl, bpl\njnz short loc_1300\nmovsxd r15, r15d\nmov rdi, rsp; s\nmov ebp, 1\nmov byte ptr [rsp+r15+0A8h+var_A8], 0\nlea r12, unk_403F\ncall _strlen\nlea r15d, [rax-1]\njmp short loc_1353\nloc_1350:\nmov rbp, rax\nloc_1353:\nmovsx esi, bl; c\nmov rdi, r13; s\ncall _strchr\ntest rax, rax\njz short loc_136E\nmovsxd rax, r15d\nsub r15d, 1\nmovzx ebx, byte ptr [rsp+rax+0A8h+var_A8]\nloc_136E:\nlea rax, [rbp+1]\nmov [r12+rbp], bl\nmovzx ebx, byte ptr [r14+rax-1]\ntest bl, bl\njnz short loc_1350\nloc_1380:\nlea rax, unk_4040\nmovsxd rbp, ebp\nmov byte ptr [rax+rbp], 0\nmov rdx, [rsp+0A8h+var_40]\nsub rdx, fs:28h\njnz short loc_13B4\nadd rsp, 78h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_13B0:\nxor ebp, ebp\njmp short loc_1380\nloc_13B4:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1290(char *a1)\n{\n char v1; // bl\n char *v2; // r12\n char v3; // bp\n int v4; // r15d\n __int64 v5; // rax\n __int64 v6; // rbp\n int v7; // r15d\n __int64 v8; // rax\n _BYTE *result; // rax\n _OWORD v10[6]; // [rsp+0h] [rbp-A8h] BYREF\n int v11; // [rsp+60h] [rbp-48h]\n unsigned __int64 v12; // [rsp+68h] [rbp-40h]\n\n v1 = *a1;\n v12 = __readfsqword(0x28u);\n v11 = 0;\n memset(v10, 0, sizeof(v10));\n if ( v1 )\n {\n v2 = a1 + 1;\n v3 = v1;\n v4 = 0;\n do\n {\n if ( strchr(\"aeiouAEIOU\", v3) )\n {\n v5 = v4++;\n *((_BYTE *)v10 + v5) = v3;\n }\n v3 = *v2++;\n }\n while ( v3 );\n v6 = 1LL;\n *((_BYTE *)v10 + v4) = 0;\n v7 = strlen((const char *)v10) - 1;\n while ( 1 )\n {\n if ( strchr(\"aeiouAEIOU\", v1) )\n {\n v8 = v7--;\n v1 = *((_BYTE *)v10 + v8);\n }\n *((_BYTE *)&unk_403F + v6) = v1;\n v1 = a1[v6];\n if ( !v1 )\n break;\n ++v6;\n }\n }\n else\n {\n LODWORD(v6) = 0;\n }\n result = byte_4040;\n byte_4040[(int)v6] = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1290(char *a1) {\n char v1;\n char *v2;\n char v3;\n int v4;\n long long v5;\n long long v6;\n int v7;\n long long v8;\n uint8_t *result;\n long double v10[6];\n int v11;\n unsigned long long v12;\n v1 = *a1;\n v12 = __readfsqword(40u);\n v11 = 0;\n memset(v10, 0, sizeof(v10));\n if (v1) {\n v2 = a1 + 1;\n v3 = v1;\n v4 = 0;\n do {\n if (strchr(\"aeiouAEIOU\", v3)) {\n v5 = v4++;\n *((uint8_t *)v10 + v5) = v3;\n }\n v3 = *v2++;\n } while (v3);\n v6 = 1LL;\n *((uint8_t *)v10 + v4) = 0;\n v7 = strlen((const char *)v10) - 1;\n while (1) {\n if (strchr(\"aeiouAEIOU\", v1)) {\n v8 = v7--;\n v1 = *((uint8_t *)v10 + v8);\n }\n *((uint8_t *)&unk_403F + v6) = v1;\n v1 = a1[v6];\n if (!v1) break;\n ++v6;\n }\n } else {\n LODWORD(v6) = 0;\n }\n result = byte_4040;\n byte_4040[(int)v6] = 0;\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(char *a1) {\n char v1;\n char *v2;\n char v3;\n int v4;\n long long v5;\n long long v6;\n int v7;\n long long v8;\n uint8_t *result;\n long double v10[6];\n int v11;\n unsigned long long v12;\n v1 = *a1;\n v12 = __readfsqword(40u);\n v11 = 0;\n memset(v10, 0, sizeof(v10));\n if (v1) {\n v2 = a1 + 1;\n v3 = v1;\n v4 = 0;\n do {\n if (strchr(\"aeiouAEIOU\", v3)) {\n v5 = v4++;\n *((uint8_t *)v10 + v5) = v3;\n }\n v3 = *v2++;\n } while (v3);\n v6 = 1LL;\n *((uint8_t *)v10 + v4) = 0;\n v7 = strlen((const char *)v10) - 1;\n while (1) {\n if (strchr(\"aeiouAEIOU\", v1)) {\n v8 = v7--;\n v1 = *((uint8_t *)v10 + v8);\n }\n *((uint8_t *)&unk_403F + v6) = v1;\n v1 = a1[v6];\n if (!v1) break;\n ++v6;\n }\n } else {\n LODWORD(v6) = 0;\n }\n result = result_string_1;\n result_string_1[(int)v6] = 0;\n return result;\n}" + }, + { + "index": 131, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* str1) {\n static char result_string[100];\n int i, j = 0;\n char vowels[100] = \"\";\n for (i = 0; str1[i] != '\\0'; i++) {\n char char1 = str1[i];\n if (strchr(\"aeiouAEIOU\", char1) != NULL) {\n vowels[j++] = char1;\n }\n }\n vowels[j] = '\\0';\n j = 0;\n int k = strlen(vowels) - 1;\n for (i = 0; str1[i] != '\\0'; i++) {\n char char1 = str1[i];\n if (strchr(\"aeiouAEIOU\", char1) != NULL) {\n result_string[j++] = vowels[k--];\n } else {\n result_string[j++] = str1[i];\n }\n }\n result_string[j] = '\\0';\n return result_string;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"Python\"), \"Python\") == 0);\n\n assert(strcmp(func0(\"USA\"), \"ASU\") == 0);\n\n assert(strcmp(func0(\"ab\"), \"ab\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npxor %xmm0,%xmm0\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x78,%rsp\nmovzbl (%rdi),%ebp\nmov %fs:0x28,%rax\nmov %rax,0x68(%rsp)\nxor %eax,%eax\nmovl $0x0,0x60(%rsp)\nmovaps %xmm0,(%rsp)\nmovaps %xmm0,0x10(%rsp)\nmovaps %xmm0,0x20(%rsp)\nmovaps %xmm0,0x30(%rsp)\nmovaps %xmm0,0x40(%rsp)\nmovaps %xmm0,0x50(%rsp)\ntest %bpl,%bpl\nje 13f8 \nmov %rdi,%r12\nlea 0x1(%rdi),%r15\nmov %ebp,%ebx\nxor %r13d,%r13d\nlea 0xd2a(%rip),%r14\nmovsbl %bl,%esi\nmov %r14,%rdi\ncallq 1080 \ntest %rax,%rax\nje 1312 \nadd $0x1,%r15\nmov %bl,(%rsp,%r13,1)\nlea 0x1(%r13),%eax\nmovzbl -0x1(%r15),%ebx\ntest %bl,%bl\nje 1321 \nmovsbl %bl,%esi\nmov %r14,%rdi\nmovslq %eax,%r13\ncallq 1080 \ntest %rax,%rax\njne 12ea \nmovzbl (%r15),%ebx\nadd $0x1,%r15\ntest %bl,%bl\njne 12da \nmov %r13d,%eax\ncltq\nmov %rsp,%rsi\nmovb $0x0,(%rsp,%rax,1)\nmov %rsi,%rax\nmov (%rax),%ecx\nadd $0x4,%rax\nlea -0x1010101(%rcx),%edx\nnot %ecx\nand %ecx,%edx\nand $0x80808080,%edx\nje 132d \nmov %edx,%ecx\nmov $0x1,%r15d\nlea 0x2ceb(%rip),%r14\nshr $0x10,%ecx\ntest $0x8080,%edx\nlea 0xca0(%rip),%r13\ncmove %ecx,%edx\nlea 0x2(%rax),%rcx\ncmove %rcx,%rax\nmov %edx,%edi\nadd %dl,%dil\nsbb $0x3,%rax\nsub %rsi,%rax\nlea -0x1(%rax),%ebx\nxchg %ax,%ax\nmovsbl %bpl,%esi\nmov %r13,%rdi\ncallq 1080 \nmovslq %r15d,%rdx\ntest %rax,%rax\nje 13b8 \nmovslq %ebx,%rax\nlea -0x1(%rbx),%ecx\nmovzbl (%rsp,%rax,1),%eax\nmov %al,(%r14,%r15,1)\nadd $0x1,%r15\nmovzbl -0x1(%r12,%r15,1),%ebp\ntest %bpl,%bpl\nje 13cb \nmov %ecx,%ebx\njmp 1380 \nnopl (%rax)\nmov %bpl,(%r14,%r15,1)\nadd $0x1,%r15\nmovzbl -0x1(%r12,%r15,1),%ebp\ntest %bpl,%bpl\njne 1380 \nlea 0x2c6e(%rip),%rax\nmovb $0x0,(%rax,%rdx,1)\nmov 0x68(%rsp),%rdi\nxor %fs:0x28,%rdi\njne 13fc \nadd $0x78,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl (%rax)\nxor %edx,%edx\njmp 13cb \ncallq 1070 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npxor xmm0, xmm0\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 78h\nmovzx r12d, byte ptr [rdi]\nmov rax, fs:28h\nmov [rsp+0A8h+var_40], rax\nxor eax, eax\nmov [rsp+0A8h+var_48], 0\nmovaps [rsp+0A8h+var_A8], xmm0\nmovaps [rsp+0A8h+var_98], xmm0\nmovaps [rsp+0A8h+var_88], xmm0\nmovaps [rsp+0A8h+var_78], xmm0\nmovaps [rsp+0A8h+var_68], xmm0\nmovaps [rsp+0A8h+var_58], xmm0\ntest r12b, r12b\njz loc_13D8\nmov r14, rdi\nlea r15, [rdi+1]\nmov ebx, r12d\nxor ebp, ebp\nlea r13, s; \"aeiouAEIOU\"\nloc_12FB:\nmovsx esi, bl; c\nmov rdi, r13; s\ncall _strchr\ntest rax, rax\njz short loc_1331\nloc_130B:\nadd r15, 1\nmov byte ptr [rsp+rbp+0A8h+var_A8], bl\nlea eax, [rbp+1]\nmovzx ebx, byte ptr [r15-1]\ntest bl, bl\njz short loc_133F\nmovsx esi, bl; c\nmov rdi, r13; s\nmovsxd rbp, eax\ncall _strchr\ntest rax, rax\njnz short loc_130B\nloc_1331:\nmovzx ebx, byte ptr [r15]\nadd r15, 1\ntest bl, bl\njnz short loc_12FB\nmov eax, ebp\nloc_133F:\ncdqe\nmov rdi, rsp; s\nmov ebx, 1\nmov byte ptr [rsp+rax+0A8h+var_A8], 0\nlea r15, unk_403F\ncall _strlen\nlea ebp, [rax-1]\nnop dword ptr [rax+00h]\nloc_1360:\nmovsx esi, r12b; c\nmov rdi, r13; s\ncall _strchr\nmovsxd rdx, ebx\ntest rax, rax\njz short loc_1398\nlea ecx, [rbp-1]\nmovsxd rbp, ebp\nmovzx eax, byte ptr [rsp+rbp+0A8h+var_A8]\nmov [r15+rbx], al\nadd rbx, 1\nmovzx r12d, byte ptr [r14+rbx-1]\ntest r12b, r12b\njz short loc_13AB\nmov ebp, ecx\njmp short loc_1360\nloc_1398:\nmov [r15+rbx], r12b\nadd rbx, 1\nmovzx r12d, byte ptr [r14+rbx-1]\ntest r12b, r12b\njnz short loc_1360\nloc_13AB:\nlea rax, result_string_1\nmov byte ptr [rax+rdx], 0\nmov rdx, [rsp+0A8h+var_40]\nsub rdx, fs:28h\njnz short loc_13DC\nadd rsp, 78h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_13D8:\nxor edx, edx\njmp short loc_13AB\nloc_13DC:\ncall ___stack_chk_fail", + "ida_pseudo": "_BYTE *__fastcall func0(char *a1)\n{\n char v1; // r12\n char *v2; // r15\n char v3; // bl\n __int64 v4; // rbp\n int v5; // eax\n __int64 v6; // rbx\n int v7; // ebp\n char *v8; // rax\n __int64 v9; // rdx\n _BYTE *result; // rax\n _OWORD v11[6]; // [rsp+0h] [rbp-A8h] BYREF\n int v12; // [rsp+60h] [rbp-48h]\n unsigned __int64 v13; // [rsp+68h] [rbp-40h]\n\n v1 = *a1;\n v13 = __readfsqword(0x28u);\n v12 = 0;\n memset(v11, 0, sizeof(v11));\n if ( v1 )\n {\n v2 = a1 + 1;\n v3 = v1;\n v4 = 0LL;\n while ( !strchr(\"aeiouAEIOU\", v3) )\n {\nLABEL_6:\n v3 = *v2++;\n if ( !v3 )\n {\n v5 = v4;\n goto LABEL_8;\n }\n }\n while ( 1 )\n {\n ++v2;\n *((_BYTE *)v11 + v4) = v3;\n v5 = v4 + 1;\n v3 = *(v2 - 1);\n if ( !v3 )\n break;\n v4 = v5;\n if ( !strchr(\"aeiouAEIOU\", v3) )\n goto LABEL_6;\n }\nLABEL_8:\n v6 = 1LL;\n *((_BYTE *)v11 + v5) = 0;\n v7 = strlen((const char *)v11) - 1;\n do\n {\n while ( 1 )\n {\n v8 = strchr(\"aeiouAEIOU\", v1);\n v9 = (int)v6;\n if ( !v8 )\n break;\n *((_BYTE *)&unk_403F + v6++) = *((_BYTE *)v11 + v7);\n v1 = a1[v6 - 1];\n if ( !v1 )\n goto LABEL_13;\n --v7;\n }\n *((_BYTE *)&unk_403F + v6++) = v1;\n v1 = a1[v6 - 1];\n }\n while ( v1 );\n }\n else\n {\n v9 = 0LL;\n }\nLABEL_13:\n result = result_string_1;\n result_string_1[v9] = 0;\n return result;\n}", + "ida_strip_asm": "sub_1290:\nendbr64\npush r15\npxor xmm0, xmm0\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 78h\nmovzx r12d, byte ptr [rdi]\nmov rax, fs:28h\nmov [rsp+0A8h+var_40], rax\nxor eax, eax\nmov [rsp+0A8h+var_48], 0\nmovaps [rsp+0A8h+var_A8], xmm0\nmovaps [rsp+0A8h+var_98], xmm0\nmovaps [rsp+0A8h+var_88], xmm0\nmovaps [rsp+0A8h+var_78], xmm0\nmovaps [rsp+0A8h+var_68], xmm0\nmovaps [rsp+0A8h+var_58], xmm0\ntest r12b, r12b\njz loc_13D8\nmov r14, rdi\nlea r15, [rdi+1]\nmov ebx, r12d\nxor ebp, ebp\nlea r13, s; \"aeiouAEIOU\"\nloc_12FB:\nmovsx esi, bl; c\nmov rdi, r13; s\ncall _strchr\ntest rax, rax\njz short loc_1331\nloc_130B:\nadd r15, 1\nmov byte ptr [rsp+rbp+0A8h+var_A8], bl\nlea eax, [rbp+1]\nmovzx ebx, byte ptr [r15-1]\ntest bl, bl\njz short loc_133F\nmovsx esi, bl; c\nmov rdi, r13; s\nmovsxd rbp, eax\ncall _strchr\ntest rax, rax\njnz short loc_130B\nloc_1331:\nmovzx ebx, byte ptr [r15]\nadd r15, 1\ntest bl, bl\njnz short loc_12FB\nmov eax, ebp\nloc_133F:\ncdqe\nmov rdi, rsp; s\nmov ebx, 1\nmov byte ptr [rsp+rax+0A8h+var_A8], 0\nlea r15, unk_403F\ncall _strlen\nlea ebp, [rax-1]\nnop dword ptr [rax+00h]\nloc_1360:\nmovsx esi, r12b; c\nmov rdi, r13; s\ncall _strchr\nmovsxd rdx, ebx\ntest rax, rax\njz short loc_1398\nlea ecx, [rbp-1]\nmovsxd rbp, ebp\nmovzx eax, byte ptr [rsp+rbp+0A8h+var_A8]\nmov [r15+rbx], al\nadd rbx, 1\nmovzx r12d, byte ptr [r14+rbx-1]\ntest r12b, r12b\njz short loc_13AB\nmov ebp, ecx\njmp short loc_1360\nloc_1398:\nmov [r15+rbx], r12b\nadd rbx, 1\nmovzx r12d, byte ptr [r14+rbx-1]\ntest r12b, r12b\njnz short loc_1360\nloc_13AB:\nlea rax, unk_4040\nmov byte ptr [rax+rdx], 0\nmov rdx, [rsp+0A8h+var_40]\nsub rdx, fs:28h\njnz short loc_13DC\nadd rsp, 78h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_13D8:\nxor edx, edx\njmp short loc_13AB\nloc_13DC:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1290(char *a1)\n{\n char v1; // r12\n char *v2; // r15\n char v3; // bl\n __int64 v4; // rbp\n int v5; // eax\n __int64 v6; // rbx\n int v7; // ebp\n char *v8; // rax\n __int64 v9; // rdx\n _BYTE *result; // rax\n _OWORD v11[6]; // [rsp+0h] [rbp-A8h] BYREF\n int v12; // [rsp+60h] [rbp-48h]\n unsigned __int64 v13; // [rsp+68h] [rbp-40h]\n\n v1 = *a1;\n v13 = __readfsqword(0x28u);\n v12 = 0;\n memset(v11, 0, sizeof(v11));\n if ( v1 )\n {\n v2 = a1 + 1;\n v3 = v1;\n v4 = 0LL;\n while ( !strchr(\"aeiouAEIOU\", v3) )\n {\nLABEL_6:\n v3 = *v2++;\n if ( !v3 )\n {\n v5 = v4;\n goto LABEL_8;\n }\n }\n while ( 1 )\n {\n ++v2;\n *((_BYTE *)v11 + v4) = v3;\n v5 = v4 + 1;\n v3 = *(v2 - 1);\n if ( !v3 )\n break;\n v4 = v5;\n if ( !strchr(\"aeiouAEIOU\", v3) )\n goto LABEL_6;\n }\nLABEL_8:\n v6 = 1LL;\n *((_BYTE *)v11 + v5) = 0;\n v7 = strlen((const char *)v11) - 1;\n do\n {\n while ( 1 )\n {\n v8 = strchr(\"aeiouAEIOU\", v1);\n v9 = (int)v6;\n if ( !v8 )\n break;\n *((_BYTE *)&unk_403F + v6++) = *((_BYTE *)v11 + v7);\n v1 = a1[v6 - 1];\n if ( !v1 )\n goto LABEL_13;\n --v7;\n }\n *((_BYTE *)&unk_403F + v6++) = v1;\n v1 = a1[v6 - 1];\n }\n while ( v1 );\n }\n else\n {\n v9 = 0LL;\n }\nLABEL_13:\n result = byte_4040;\n byte_4040[v9] = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1290(char *a1) {\n char v1;\n char *v2;\n char v3;\n long long v4;\n int v5;\n long long v6;\n int v7;\n char *v8;\n long long v9;\n uint8_t *result;\n long double v11[6];\n int v12;\n unsigned long long v13;\n v1 = *a1;\n v13 = __readfsqword(40u);\n v12 = 0;\n memset(v11, 0, sizeof(v11));\n if (v1) {\n v2 = a1 + 1;\n v3 = v1;\n v4 = 0LL;\n while (!strchr(\"aeiouAEIOU\", v3)) {\n LABEL_6:\n v3 = *v2++;\n if (!v3) {\n v5 = v4;\n goto LABEL_8;\n }\n }\n while (1) {\n ++v2;\n *((uint8_t *)v11 + v4) = v3;\n v5 = v4 + 1;\n v3 = *(v2 - 1);\n if (!v3) break;\n v4 = v5;\n if (!strchr(\"aeiouAEIOU\", v3)) goto LABEL_6;\n }\n LABEL_8:\n v6 = 1LL;\n *((uint8_t *)v11 + v5) = 0;\n v7 = strlen((const char *)v11) - 1;\n do {\n while (1) {\n v8 = strchr(\"aeiouAEIOU\", v1);\n v9 = (int)v6;\n if (!v8) break;\n *((uint8_t *)&unk_403F + v6++) = *((uint8_t *)v11 + v7);\n v1 = a1[v6 - 1];\n if (!v1) goto LABEL_13;\n --v7;\n }\n *((uint8_t *)&unk_403F + v6++) = v1;\n v1 = a1[v6 - 1];\n } while (v1);\n } else {\n v9 = 0LL;\n }\nLABEL_13:\n result = byte_4040;\n byte_4040[v9] = 0;\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(char *a1) {\n char v1;\n char *v2;\n char v3;\n long long v4;\n int v5;\n long long v6;\n int v7;\n char *v8;\n long long v9;\n uint8_t *result;\n long double v11[6];\n int v12;\n unsigned long long v13;\n v1 = *a1;\n v13 = __readfsqword(40u);\n v12 = 0;\n memset(v11, 0, sizeof(v11));\n if (v1) {\n v2 = a1 + 1;\n v3 = v1;\n v4 = 0LL;\n while (!strchr(\"aeiouAEIOU\", v3)) {\n LABEL_6:\n v3 = *v2++;\n if (!v3) {\n v5 = v4;\n goto LABEL_8;\n }\n }\n while (1) {\n ++v2;\n *((uint8_t *)v11 + v4) = v3;\n v5 = v4 + 1;\n v3 = *(v2 - 1);\n if (!v3) break;\n v4 = v5;\n if (!strchr(\"aeiouAEIOU\", v3)) goto LABEL_6;\n }\n LABEL_8:\n v6 = 1LL;\n *((uint8_t *)v11 + v5) = 0;\n v7 = strlen((const char *)v11) - 1;\n do {\n while (1) {\n v8 = strchr(\"aeiouAEIOU\", v1);\n v9 = (int)v6;\n if (!v8) break;\n *((uint8_t *)&unk_403F + v6++) = *((uint8_t *)v11 + v7);\n v1 = a1[v6 - 1];\n if (!v1) goto LABEL_13;\n --v7;\n }\n *((uint8_t *)&unk_403F + v6++) = v1;\n v1 = a1[v6 - 1];\n } while (v1);\n } else {\n v9 = 0LL;\n }\nLABEL_13:\n result = result_string_1;\n result_string_1[v9] = 0;\n return result;\n}" + }, + { + "index": 132, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* tup1, char* result) {\n strcpy(result, tup1);\n return result;\n}", + "test": "int main() {\n\n char result[100];\n\n assert(strcmp(func0(\"exercises\", result), \"exercises\") == 0);\n\n assert(strcmp(func0(\"python\", result), \"python\") == 0);\n\n assert(strcmp(func0(\"program\", result), \"program\") == 0);\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %rdi,-0x8(%rbp)\nmov %rsi,-0x10(%rbp)\nmov -0x8(%rbp),%rdx\nmov -0x10(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1080 \nmov -0x10(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+src], rdi\nmov [rbp+dest], rsi\nmov rdx, [rbp+src]\nmov rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\nmov rax, [rbp+dest]\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(const char *a1, char *a2)\n{\n strcpy(a2, a1);\n return a2;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+src], rdi\nmov [rbp+dest], rsi\nmov rdx, [rbp+src]\nmov rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\nmov rax, [rbp+dest]\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11A9(const char *a1, char *a2)\n{\n strcpy(a2, a1);\n return a2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11A9(const char *a1, char *a2) {\n strcpy(a2, a1);\n return a2;\n}", + "ida_pseudo_norm": "char *func0(const char *a1, char *a2) {\n strcpy(a2, a1);\n return a2;\n}" + }, + { + "index": 132, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* tup1, char* result) {\n strcpy(result, tup1);\n return result;\n}", + "test": "int main() {\n\n char result[100];\n\n assert(strcmp(func0(\"exercises\", result), \"exercises\") == 0);\n\n assert(strcmp(func0(\"python\", result), \"python\") == 0);\n\n assert(strcmp(func0(\"program\", result), \"program\") == 0);\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rsi,%rbx\nmov %rdi,%rsi\nmov %rbx,%rdi\ncallq 1070 \npop %rbx\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rsi\nmov rsi, rdi; src\nmov rdi, rbx; dest\ncall _strcpy\npop rbx\nretn", + "ida_pseudo": "char *__fastcall func0(char *src, char *dest)\n{\n return strcpy(dest, src);\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbx\nmov rbx, rsi\nmov rsi, rdi; src\nmov rdi, rbx; dest\ncall _strcpy\npop rbx\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11A9(char *src, char *dest)\n{\n return strcpy(dest, src);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11A9(char *src, char *dest) { return strcpy(dest, src); }", + "ida_pseudo_norm": "char *func0(char *src, char *dest) { return strcpy(dest, src); }" + }, + { + "index": 132, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* tup1, char* result) {\n strcpy(result, tup1);\n return result;\n}", + "test": "int main() {\n\n char result[100];\n\n assert(strcmp(func0(\"exercises\", result), \"exercises\") == 0);\n\n assert(strcmp(func0(\"python\", result), \"python\") == 0);\n\n assert(strcmp(func0(\"program\", result), \"program\") == 0);\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov %rsi,%r8\nsub $0x8,%rsp\nmov %rdi,%rsi\nmov %r8,%rdi\ncallq 1070 \nadd $0x8,%rsp\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmov rdx, rsi\nsub rsp, 8\nmov rsi, rdi; src\nmov rdi, rdx; dest\ncall _strcpy\nadd rsp, 8\nretn", + "ida_pseudo": "char *__fastcall func0(char *src, char *dest)\n{\n return strcpy(dest, src);\n}", + "ida_strip_asm": "sub_12B0:\nendbr64\nmov rdx, rsi\nsub rsp, 8\nmov rsi, rdi; src\nmov rdi, rdx; dest\ncall _strcpy\nadd rsp, 8\nretn", + "ida_strip_pseudo": "char *__fastcall sub_12B0(char *src, char *dest)\n{\n return strcpy(dest, src);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_12B0(char *src, char *dest) { return strcpy(dest, src); }", + "ida_pseudo_norm": "char *func0(char *src, char *dest) { return strcpy(dest, src); }" + }, + { + "index": 132, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* tup1, char* result) {\n strcpy(result, tup1);\n return result;\n}", + "test": "int main() {\n\n char result[100];\n\n assert(strcmp(func0(\"exercises\", result), \"exercises\") == 0);\n\n assert(strcmp(func0(\"python\", result), \"python\") == 0);\n\n assert(strcmp(func0(\"program\", result), \"program\") == 0);\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nmov %rsi,%r8\nsub $0x8,%rsp\nmov %rdi,%rsi\nmov %r8,%rdi\ncallq 1070 \nadd $0x8,%rsp\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmov rdx, rsi\nsub rsp, 8\nmov rsi, rdi; src\nmov rdi, rdx; dest\ncall _strcpy\nadd rsp, 8\nretn", + "ida_pseudo": "char *__fastcall func0(char *src, char *dest)\n{\n return strcpy(dest, src);\n}", + "ida_strip_asm": "sub_1220:\nendbr64\nmov rdx, rsi\nsub rsp, 8\nmov rsi, rdi; src\nmov rdi, rdx; dest\ncall _strcpy\nadd rsp, 8\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1220(char *src, char *dest)\n{\n return strcpy(dest, src);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1220(char *src, char *dest) { return strcpy(dest, src); }", + "ida_pseudo_norm": "char *func0(char *src, char *dest) { return strcpy(dest, src); }" + }, + { + "index": 133, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int nums[], int size) {\n int sum = 0;\n for (int i = 0; i < size; i++) {\n if (nums[i] < 0) {\n sum += nums[i];\n }\n }\n return sum;\n}", + "test": "int main() {\n\n int array1[] = {2, 4, -6, -9, 11, -12, 14, -5, 17};\n\n int array2[] = {10, 15, -14, 13, -18, 12, -20};\n\n int array3[] = {19, -65, 57, 39, 152, -639, 121, 44, 90, -190};\n\n \n\n assert(func0(array1, 9) == -32);\n\n assert(func0(array2, 7) == -52);\n\n assert(func0(array3, 10) == -894);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11bf \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ntest %eax,%eax\njns 11bb \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nadd %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1188 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11BF\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njns short loc_11BB\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nloc_11BB:\nadd [rbp+var_4], 1\nloc_11BF:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(int *)(4LL * i + a1) < 0 )\n v3 += *(_DWORD *)(4LL * i + a1);\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11BF\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njns short loc_11BB\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nloc_11BB:\nadd [rbp+var_4], 1\nloc_11BF:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(int *)(4LL * i + a1) < 0 )\n v3 += *(_DWORD *)(4LL * i + a1);\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(int *)(4LL * i + a1) < 0) v3 += *(uint32_t *)(4LL * i + a1);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(int *)(4LL * i + a1) < 0) v3 += *(uint32_t *)(4LL * i + a1);\n }\n return v3;\n}" + }, + { + "index": 133, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int nums[], int size) {\n int sum = 0;\n for (int i = 0; i < size; i++) {\n if (nums[i] < 0) {\n sum += nums[i];\n }\n }\n return sum;\n}", + "test": "int main() {\n\n int array1[] = {2, 4, -6, -9, 11, -12, 14, -5, 17};\n\n int array2[] = {10, 15, -14, 13, -18, 12, -20};\n\n int array3[] = {19, -65, 57, 39, 152, -639, 121, 44, 90, -190};\n\n \n\n assert(func0(array1, 9) == -32);\n\n assert(func0(array2, 7) == -52);\n\n assert(func0(array3, 10) == -894);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1197 \nmov %rdi,%rax\nlea -0x1(%rsi),%edx\nlea 0x4(%rdi,%rdx,4),%rdi\nmov $0x0,%edx\nmov (%rax),%ecx\nlea (%rdx,%rcx,1),%esi\ntest %ecx,%ecx\ncmovs %esi,%edx\nadd $0x4,%rax\ncmp %rdi,%rax\njne 1181 \nmov %edx,%eax\nretq\nmov $0x0,%edx\njmp 1194 \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1196\nmov rax, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*4]\nmov edx, 0\nloc_1180:\nmov ecx, [rax]\nlea esi, [rdx+rcx]\ntest ecx, ecx\ncmovs edx, esi\nadd rax, 4\ncmp rax, rdi\njnz short loc_1180\nloc_1193:\nmov eax, edx\nretn\nloc_1196:\nmov edx, 0\njmp short loc_1193", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int *v2; // rax\n int *v3; // rdi\n unsigned int v4; // edx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n {\n if ( *v2 < 0 )\n v4 += *v2;\n ++v2;\n }\n while ( v2 != v3 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_1196\nmov rax, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*4]\nmov edx, 0\nloc_1180:\nmov ecx, [rax]\nlea esi, [rdx+rcx]\ntest ecx, ecx\ncmovs edx, esi\nadd rax, 4\ncmp rax, rdi\njnz short loc_1180\nloc_1193:\nmov eax, edx\nretn\nloc_1196:\nmov edx, 0\njmp short loc_1193", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int *a1, int a2)\n{\n int *v2; // rax\n int *v3; // rdi\n unsigned int v4; // edx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n {\n if ( *v2 < 0 )\n v4 += *v2;\n ++v2;\n }\n while ( v2 != v3 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int *a1, int a2) {\n int *v2;\n int *v3;\n unsigned int v4;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do {\n if (*v2 < 0) v4 += *v2;\n ++v2;\n } while (v2 != v3);\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int *v2;\n int *v3;\n unsigned int v4;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do {\n if (*v2 < 0) v4 += *v2;\n ++v2;\n } while (v2 != v3);\n }\n return v4;\n}" + }, + { + "index": 134, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "char* func0(int arr[], int n, int p) {\n int _sum = 0;\n for (int i = 0; i < n; i++) {\n _sum += arr[i];\n }\n if (p == 1) {\n if (_sum % 2 == 0) {\n return \"ODD\";\n } else {\n return \"EVEN\";\n }\n }\n return \"EVEN\";\n}", + "test": "int main() {\n\n int arr1[3] = {5, 7, 10};\n\n assert(func0(arr1, 3, 1)[0] == 'O' && func0(arr1, 3, 1)[1] == 'D' && func0(arr1, 3, 1)[2] == 'D');\n\n\n\n int arr2[2] = {2, 3};\n\n assert(func0(arr2, 2, 3)[0] == 'E' && func0(arr2, 2, 3)[1] == 'V' && func0(arr2, 2, 3)[2] == 'E' && func0(arr2, 2, 3)[3] == 'N');\n\n\n\n int arr3[3] = {1, 2, 3};\n\n assert(func0(arr3, 3, 1)[0] == 'O' && func0(arr3, 3, 1)[1] == 'D' && func0(arr3, 3, 1)[2] == 'D');\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11a8 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nadd %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 118b \ncmpl $0x1,-0x20(%rbp)\njne 11d2 \nmov -0x8(%rbp),%eax\nand $0x1,%eax\ntest %eax,%eax\njne 11c9 \nlea 0xe41(%rip),%rax\njmp 11d9 \nlea 0xe3c(%rip),%rax\njmp 11d9 \nlea 0xe33(%rip),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11A8\nloc_118B:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_11A8:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_118B\ncmp [rbp+var_20], 1\njnz short loc_11D2\nmov eax, [rbp+var_8]\nand eax, 1\ntest eax, eax\njnz short loc_11C9\nlea rax, unk_2008\njmp short loc_11D9\nloc_11C9:\nlea rax, aEven; \"EVEN\"\njmp short loc_11D9\nloc_11D2:\nlea rax, aEven; \"EVEN\"\nloc_11D9:\npop rbp\nretn", + "ida_pseudo": "const char *__fastcall func0(__int64 a1, int a2, int a3)\n{\n int v4; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n v4 += *(_DWORD *)(4LL * i + a1);\n if ( a3 != 1 )\n return \"EVEN\";\n if ( (v4 & 1) != 0 )\n return \"EVEN\";\n return (const char *)&unk_2008;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11A8\nloc_118B:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_11A8:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_118B\ncmp [rbp+var_20], 1\njnz short loc_11D2\nmov eax, [rbp+var_8]\nand eax, 1\ntest eax, eax\njnz short loc_11C9\nlea rax, unk_2008\njmp short loc_11D9\nloc_11C9:\nlea rax, aEven; \"EVEN\"\njmp short loc_11D9\nloc_11D2:\nlea rax, aEven; \"EVEN\"\nloc_11D9:\npop rbp\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n int v4; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n v4 += *(_DWORD *)(4LL * i + a1);\n if ( a3 != 1 )\n return \"EVEN\";\n if ( (v4 & 1) != 0 )\n return \"EVEN\";\n return (const char *)&unk_2008;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1169(long long a1, int a2, int a3) {\n int v4;\n int i;\n v4 = 0;\n for (i = 0; i < a2; ++i) v4 += *(uint32_t *)(4LL * i + a1);\n if (a3 != 1) return \"EVEN\";\n if ((v4 & 1) != 0) return \"EVEN\";\n return (const char *)&unk_2008;\n}", + "ida_pseudo_norm": "const char *func0(long long a1, int a2, int a3) {\n int v4;\n int i;\n v4 = 0;\n for (i = 0; i < a2; ++i) v4 += *(uint32_t *)(4LL * i + a1);\n if (a3 != 1) return \"EVEN\";\n if ((v4 & 1) != 0) return \"EVEN\";\n return (const char *)&unk_2008;\n}" + }, + { + "index": 134, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "char* func0(int arr[], int n, int p) {\n int _sum = 0;\n for (int i = 0; i < n; i++) {\n _sum += arr[i];\n }\n if (p == 1) {\n if (_sum % 2 == 0) {\n return \"ODD\";\n } else {\n return \"EVEN\";\n }\n }\n return \"EVEN\";\n}", + "test": "int main() {\n\n int arr1[3] = {5, 7, 10};\n\n assert(func0(arr1, 3, 1)[0] == 'O' && func0(arr1, 3, 1)[1] == 'D' && func0(arr1, 3, 1)[2] == 'D');\n\n\n\n int arr2[2] = {2, 3};\n\n assert(func0(arr2, 2, 3)[0] == 'E' && func0(arr2, 2, 3)[1] == 'V' && func0(arr2, 2, 3)[2] == 'E' && func0(arr2, 2, 3)[3] == 'N');\n\n\n\n int arr3[3] = {1, 2, 3};\n\n assert(func0(arr3, 3, 1)[0] == 'O' && func0(arr3, 3, 1)[1] == 'D' && func0(arr3, 3, 1)[2] == 'D');\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1199 \nmov %rdi,%rax\nlea -0x1(%rsi),%ecx\nlea 0x4(%rdi,%rcx,4),%rsi\nmov $0x0,%ecx\nadd (%rax),%ecx\nadd $0x4,%rax\ncmp %rsi,%rax\njne 1181 \nlea 0xe75(%rip),%rax\ncmp $0x1,%edx\nje 11a0 \nretq\nmov $0x0,%ecx\njmp 118c \ntest $0x1,%cl\nlea 0xe5a(%rip),%rax\nlea 0xe57(%rip),%rdx\ncmovne %rdx,%rax\njmp 1198 \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1198\nmov rax, rdi\nmovsxd rsi, esi\nlea rsi, [rdi+rsi*4]\nmov ecx, 0\nloc_1180:\nadd ecx, [rax]\nadd rax, 4\ncmp rax, rsi\njnz short loc_1180\nloc_118B:\nlea rax, aEven; \"EVEN\"\ncmp edx, 1\njz short loc_119F\nretn\nloc_1198:\nmov ecx, 0\njmp short loc_118B\nloc_119F:\ntest cl, 1\nlea rdx, unk_2004\ncmovz rax, rdx\nretn", + "ida_pseudo": "const char *__fastcall func0(_DWORD *a1, int a2, int a3)\n{\n _DWORD *v3; // rax\n _DWORD *v4; // rsi\n int v5; // ecx\n const char *result; // rax\n\n if ( a2 <= 0 )\n {\n LOBYTE(v5) = 0;\n }\n else\n {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n do\n v5 += *v3++;\n while ( v3 != v4 );\n }\n result = \"EVEN\";\n if ( a3 == 1 && (v5 & 1) == 0 )\n return (const char *)&unk_2004;\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_1198\nmov rax, rdi\nmovsxd rsi, esi\nlea rsi, [rdi+rsi*4]\nmov ecx, 0\nloc_1180:\nadd ecx, [rax]\nadd rax, 4\ncmp rax, rsi\njnz short loc_1180\nloc_118B:\nlea rax, aEven; \"EVEN\"\ncmp edx, 1\njz short loc_119F\nretn\nloc_1198:\nmov ecx, 0\njmp short loc_118B\nloc_119F:\ntest cl, 1\nlea rdx, unk_2004\ncmovz rax, rdx\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1169(_DWORD *a1, int a2, int a3)\n{\n _DWORD *v3; // rax\n _DWORD *v4; // rsi\n int v5; // ecx\n const char *result; // rax\n\n if ( a2 <= 0 )\n {\n LOBYTE(v5) = 0;\n }\n else\n {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n do\n v5 += *v3++;\n while ( v3 != v4 );\n }\n result = \"EVEN\";\n if ( a3 == 1 && (v5 & 1) == 0 )\n return (const char *)&unk_2004;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1169(uint32_t *a1, int a2, int a3) {\n uint32_t *v3;\n uint32_t *v4;\n int v5;\n const char *result;\n if (a2 <= 0) {\n LOBYTE(v5) = 0;\n } else {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n do\n v5 += *v3++;\n while (v3 != v4);\n }\n result = \"EVEN\";\n if (a3 == 1 && (v5 & 1) == 0) return (const char *)&unk_2004;\n return result;\n}", + "ida_pseudo_norm": "const char *func0(uint32_t *a1, int a2, int a3) {\n uint32_t *v3;\n uint32_t *v4;\n int v5;\n const char *result;\n if (a2 <= 0) {\n LOBYTE(v5) = 0;\n } else {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n do\n v5 += *v3++;\n while (v3 != v4);\n }\n result = \"EVEN\";\n if (a3 == 1 && (v5 & 1) == 0) return (const char *)&unk_2004;\n return result;\n}" + }, + { + "index": 135, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) { return n * (2 * n - 1); }", + "test": "int main() {\n\n assert(func0(10) == 190);\n\n assert(func0(5) == 45);\n\n assert(func0(7) == 91);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nadd %eax,%eax\nsub $0x1,%eax\nimul -0x4(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov eax, [rbp+var_4]\nadd eax, eax\nsub eax, 1\nimul eax, [rbp+var_4]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n return (unsigned int)(a1 * (2 * a1 - 1));\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov eax, [rbp+var_4]\nadd eax, eax\nsub eax, 1\nimul eax, [rbp+var_4]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n return (unsigned int)(a1 * (2 * a1 - 1));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) { return (unsigned int)(a1 * (2 * a1 - 1)); }", + "ida_pseudo_norm": "long long func0(int a1) { return (unsigned int)(a1 * (2 * a1 - 1)); }" + }, + { + "index": 136, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "double func0(int units) {\n double amount;\n int surcharge;\n if (units < 50) {\n amount = units * 2.60;\n surcharge = 25;\n } else if (units <= 100) {\n amount = 130 + ((units - 50) * 3.25);\n surcharge = 35;\n } else if (units <= 200) {\n amount = 130 + 162.50 + ((units - 100) * 5.26);\n surcharge = 45;\n } else {\n amount = 130 + 162.50 + 526 + ((units - 200) * 8.45);\n surcharge = 75;\n }\n double total = amount + surcharge;\n return total;\n}", + "test": "int main() {\n\n assert(func0(75) == 246.25);\n\n assert(func0(265) == 1442.75);\n\n assert(func0(100) == 327.5);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x24(%rbp)\ncmpl $0x31,-0x24(%rbp)\njg 117c \ncvtsi2sdl -0x24(%rbp),%xmm1\nmovsd 0xf21(%rip),%xmm0\nmulsd %xmm1,%xmm0\nmovsd %xmm0,-0x10(%rbp)\nmovl $0x19,-0x14(%rbp)\njmpq 121b \ncmpl $0x64,-0x24(%rbp)\njg 11b2 \nmov -0x24(%rbp),%eax\nsub $0x32,%eax\ncvtsi2sd %eax,%xmm1\nmovsd 0xefc(%rip),%xmm0\nmulsd %xmm0,%xmm1\nmovsd 0xef8(%rip),%xmm0\naddsd %xmm1,%xmm0\nmovsd %xmm0,-0x10(%rbp)\nmovl $0x23,-0x14(%rbp)\njmp 121b \ncmpl $0xc8,-0x24(%rbp)\njg 11eb \nmov -0x24(%rbp),%eax\nsub $0x64,%eax\ncvtsi2sd %eax,%xmm1\nmovsd 0xed3(%rip),%xmm0\nmulsd %xmm0,%xmm1\nmovsd 0xecf(%rip),%xmm0\naddsd %xmm1,%xmm0\nmovsd %xmm0,-0x10(%rbp)\nmovl $0x2d,-0x14(%rbp)\njmp 121b \nmov -0x24(%rbp),%eax\nsub $0xc8,%eax\ncvtsi2sd %eax,%xmm1\nmovsd 0xeb1(%rip),%xmm0\nmulsd %xmm0,%xmm1\nmovsd 0xead(%rip),%xmm0\naddsd %xmm1,%xmm0\nmovsd %xmm0,-0x10(%rbp)\nmovl $0x4b,-0x14(%rbp)\ncvtsi2sdl -0x14(%rbp),%xmm0\nmovsd -0x10(%rbp),%xmm1\naddsd %xmm1,%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmovsd -0x8(%rbp),%xmm0\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_24], edi\ncmp [rbp+var_24], 31h ; '1'\njg short loc_1180\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_24]\nmovsd xmm0, cs:qword_2070\nmulsd xmm0, xmm1\nmovsd [rbp+var_10], xmm0\nmov [rbp+var_14], 19h\njmp loc_122B\nloc_1180:\ncmp [rbp+var_24], 64h ; 'd'\njg short loc_11BA\nmov eax, [rbp+var_24]\nsub eax, 32h ; '2'\npxor xmm1, xmm1\ncvtsi2sd xmm1, eax\nmovsd xmm0, cs:qword_2078\nmulsd xmm1, xmm0\nmovsd xmm0, cs:qword_2080\naddsd xmm0, xmm1\nmovsd [rbp+var_10], xmm0\nmov [rbp+var_14], 23h ; '#'\njmp short loc_122B\nloc_11BA:\ncmp [rbp+var_24], 0C8h\njg short loc_11F7\nmov eax, [rbp+var_24]\nsub eax, 64h ; 'd'\npxor xmm1, xmm1\ncvtsi2sd xmm1, eax\nmovsd xmm0, cs:qword_2088\nmulsd xmm1, xmm0\nmovsd xmm0, cs:qword_2090\naddsd xmm0, xmm1\nmovsd [rbp+var_10], xmm0\nmov [rbp+var_14], 2Dh ; '-'\njmp short loc_122B\nloc_11F7:\nmov eax, [rbp+var_24]\nsub eax, 0C8h\npxor xmm1, xmm1\ncvtsi2sd xmm1, eax\nmovsd xmm0, cs:qword_2098\nmulsd xmm1, xmm0\nmovsd xmm0, cs:qword_20A0\naddsd xmm0, xmm1\nmovsd [rbp+var_10], xmm0\nmov [rbp+var_14], 4Bh ; 'K'\nloc_122B:\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_14]\nmovsd xmm1, [rbp+var_10]\naddsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "double __fastcall func0(int a1)\n{\n int v2; // [rsp+10h] [rbp-14h]\n double v3; // [rsp+14h] [rbp-10h]\n\n if ( a1 > 49 )\n {\n if ( a1 > 100 )\n {\n if ( a1 > 200 )\n {\n v3 = (double)(a1 - 200) * 8.449999999999999 + 818.5;\n v2 = 75;\n }\n else\n {\n v3 = (double)(a1 - 100) * 5.26 + 292.5;\n v2 = 45;\n }\n }\n else\n {\n v3 = (double)(a1 - 50) * 3.25 + 130.0;\n v2 = 35;\n }\n }\n else\n {\n v3 = 2.6 * (double)a1;\n v2 = 25;\n }\n return (double)v2 + v3;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_24], edi\ncmp [rbp+var_24], 31h ; '1'\njg short loc_1180\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_24]\nmovsd xmm0, cs:qword_2070\nmulsd xmm0, xmm1\nmovsd [rbp+var_10], xmm0\nmov [rbp+var_14], 19h\njmp loc_122B\nloc_1180:\ncmp [rbp+var_24], 64h ; 'd'\njg short loc_11BA\nmov eax, [rbp+var_24]\nsub eax, 32h ; '2'\npxor xmm1, xmm1\ncvtsi2sd xmm1, eax\nmovsd xmm0, cs:qword_2078\nmulsd xmm1, xmm0\nmovsd xmm0, cs:qword_2080\naddsd xmm0, xmm1\nmovsd [rbp+var_10], xmm0\nmov [rbp+var_14], 23h ; '#'\njmp short loc_122B\nloc_11BA:\ncmp [rbp+var_24], 0C8h\njg short loc_11F7\nmov eax, [rbp+var_24]\nsub eax, 64h ; 'd'\npxor xmm1, xmm1\ncvtsi2sd xmm1, eax\nmovsd xmm0, cs:qword_2088\nmulsd xmm1, xmm0\nmovsd xmm0, cs:qword_2090\naddsd xmm0, xmm1\nmovsd [rbp+var_10], xmm0\nmov [rbp+var_14], 2Dh ; '-'\njmp short loc_122B\nloc_11F7:\nmov eax, [rbp+var_24]\nsub eax, 0C8h\npxor xmm1, xmm1\ncvtsi2sd xmm1, eax\nmovsd xmm0, cs:qword_2098\nmulsd xmm1, xmm0\nmovsd xmm0, cs:qword_20A0\naddsd xmm0, xmm1\nmovsd [rbp+var_10], xmm0\nmov [rbp+var_14], 4Bh ; 'K'\nloc_122B:\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_14]\nmovsd xmm1, [rbp+var_10]\naddsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "double __fastcall sub_1149(int a1)\n{\n int v2; // [rsp+10h] [rbp-14h]\n double v3; // [rsp+14h] [rbp-10h]\n\n if ( a1 > 49 )\n {\n if ( a1 > 100 )\n {\n if ( a1 > 200 )\n {\n v3 = (double)(a1 - 200) * 8.449999999999999 + 818.5;\n v2 = 75;\n }\n else\n {\n v3 = (double)(a1 - 100) * 5.26 + 292.5;\n v2 = 45;\n }\n }\n else\n {\n v3 = (double)(a1 - 50) * 3.25 + 130.0;\n v2 = 35;\n }\n }\n else\n {\n v3 = 2.6 * (double)a1;\n v2 = 25;\n }\n return (double)v2 + v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1149(int a1) {\n int v2;\n double v3;\n if (a1 > 49) {\n if (a1 > 100) {\n if (a1 > 200) {\n v3 = (double)(a1 - 200) * 8.449999999999999 + 818.5;\n v2 = 75;\n } else {\n v3 = (double)(a1 - 100) * 5.26 + 292.5;\n v2 = 45;\n }\n } else {\n v3 = (double)(a1 - 50) * 3.25 + 130.0;\n v2 = 35;\n }\n } else {\n v3 = 2.6 * (double)a1;\n v2 = 25;\n }\n return (double)v2 + v3;\n}", + "ida_pseudo_norm": "double func0(int a1) {\n int v2;\n double v3;\n if (a1 > 49) {\n if (a1 > 100) {\n if (a1 > 200) {\n v3 = (double)(a1 - 200) * 8.449999999999999 + 818.5;\n v2 = 75;\n } else {\n v3 = (double)(a1 - 100) * 5.26 + 292.5;\n v2 = 45;\n }\n } else {\n v3 = (double)(a1 - 50) * 3.25 + 130.0;\n v2 = 35;\n }\n } else {\n v3 = 2.6 * (double)a1;\n v2 = 25;\n }\n return (double)v2 + v3;\n}" + }, + { + "index": 137, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int nums[], int n) {\n int n1 = 0;\n for (int i = 0; i < n; i++) {\n if (nums[i] == 0) {\n n1++;\n }\n }\n double ratio = ((double)n1 / n);\n ratio = round(ratio * 100) / 100.0;\n return ratio;\n}", + "test": "int main() {\n\n int arr1[] = {0, 1, 2, -1, -5, 6, 0, -3, -2, 3, 4, 6, 8};\n\n assert(func0(arr1, 13) == 0.15);\n\n \n\n int arr2[] = {2, 1, 2, -1, -5, 6, 4, -3, -2, 3, 4, 6, 8};\n\n assert(func0(arr2, 13) == 0.00);\n\n \n\n int arr3[] = {2, 4, -6, -9, 11, -12, 14, -5, 17};\n\n assert(func0(arr3, 9) == 0.00);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 11ce \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ntest %eax,%eax\njne 11ca \naddl $0x1,-0x10(%rbp)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11ac \ncvtsi2sdl -0x10(%rbp),%xmm0\ncvtsi2sdl -0x1c(%rbp),%xmm1\ndivsd %xmm1,%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmovsd -0x8(%rbp),%xmm1\nmovsd 0xe9a(%rip),%xmm0\nmulsd %xmm1,%xmm0\ncallq 1070 \nmovsd 0xe89(%rip),%xmm1\ndivsd %xmm1,%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmovsd -0x8(%rbp),%xmm0\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp short loc_11CE\nloc_11AC:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njnz short loc_11CA\nadd [rbp+var_10], 1\nloc_11CA:\nadd [rbp+var_C], 1\nloc_11CE:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_11AC\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_10]\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_1C]\ndivsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm1, [rbp+var_8]\nmovsd xmm0, cs:qword_2078\nmulsd xmm1, xmm0\nmovq rax, xmm1\nmovq xmm0, rax; x\ncall _round\nmovq rax, xmm0\nmovsd xmm1, cs:qword_2078\nmovq xmm0, rax\ndivsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "double __fastcall func0(__int64 a1, int a2)\n{\n int v3; // [rsp+10h] [rbp-10h]\n int i; // [rsp+14h] [rbp-Ch]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( !*(_DWORD *)(4LL * i + a1) )\n ++v3;\n }\n return round((double)v3 / (double)a2 * 100.0) / 100.0;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp short loc_11CE\nloc_11AC:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njnz short loc_11CA\nadd [rbp+var_10], 1\nloc_11CA:\nadd [rbp+var_C], 1\nloc_11CE:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_11AC\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_10]\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_1C]\ndivsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm1, [rbp+var_8]\nmovsd xmm0, cs:qword_2078\nmulsd xmm1, xmm0\nmovq rax, xmm1\nmovq xmm0, rax; x\ncall _round\nmovq rax, xmm0\nmovsd xmm1, cs:qword_2078\nmovq xmm0, rax\ndivsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "double __fastcall sub_1189(__int64 a1, int a2)\n{\n int v3; // [rsp+10h] [rbp-10h]\n int i; // [rsp+14h] [rbp-Ch]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( !*(_DWORD *)(4LL * i + a1) )\n ++v3;\n }\n return round((double)v3 / (double)a2 * 100.0) / 100.0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1189(long long a1, int a2) {\n int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n if (!*(uint32_t *)(4LL * i + a1)) ++v3;\n }\n return round((double)v3 / (double)a2 * 100.0) / 100.0;\n}", + "ida_pseudo_norm": "double func0(long long a1, int a2) {\n int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n if (!*(uint32_t *)(4LL * i + a1)) ++v3;\n }\n return round((double)v3 / (double)a2 * 100.0) / 100.0;\n}" + }, + { + "index": 137, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int nums[], int n) {\n int n1 = 0;\n for (int i = 0; i < n; i++) {\n if (nums[i] == 0) {\n n1++;\n }\n }\n double ratio = ((double)n1 / n);\n ratio = round(ratio * 100) / 100.0;\n return ratio;\n}", + "test": "int main() {\n\n int arr1[] = {0, 1, 2, -1, -5, 6, 0, -3, -2, 3, 4, 6, 8};\n\n assert(func0(arr1, 13) == 0.15);\n\n \n\n int arr2[] = {2, 1, 2, -1, -5, 6, 4, -3, -2, 3, 4, 6, 8};\n\n assert(func0(arr2, 13) == 0.00);\n\n \n\n int arr3[] = {2, 4, -6, -9, 11, -12, 14, -5, 17};\n\n assert(func0(arr3, 9) == 0.00);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x8,%rsp\ntest %esi,%esi\njle 11e2 \nmov %rdi,%rax\nlea -0x1(%rsi),%edx\nlea 0x4(%rdi,%rdx,4),%rcx\nmov $0x0,%edx\ncmpl $0x1,(%rax)\nadc $0x0,%edx\nadd $0x4,%rax\ncmp %rcx,%rax\njne 11a5 \npxor %xmm0,%xmm0\ncvtsi2sd %edx,%xmm0\npxor %xmm1,%xmm1\ncvtsi2sd %esi,%xmm1\ndivsd %xmm1,%xmm0\nmulsd 0xec0(%rip),%xmm0\ncallq 1070 \ndivsd 0xeb3(%rip),%xmm0\nadd $0x8,%rsp\nretq\nmov $0x0,%edx\njmp 11b4 \n", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\ntest esi, esi\njle short loc_11E1\nmov rax, rdi\nmovsxd rdx, esi\nlea rcx, [rdi+rdx*4]\nmov edx, 0\nloc_11A4:\ncmp dword ptr [rax], 1\nadc edx, 0\nadd rax, 4\ncmp rax, rcx\njnz short loc_11A4\nloc_11B3:\npxor xmm0, xmm0\ncvtsi2sd xmm0, edx\npxor xmm1, xmm1\ncvtsi2sd xmm1, esi\ndivsd xmm0, xmm1\nmulsd xmm0, cs:qword_2078; x\ncall _round\ndivsd xmm0, cs:qword_2078\nadd rsp, 8\nretn\nloc_11E1:\nmov edx, 0\njmp short loc_11B3", + "ida_pseudo": "double __fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n int v3; // edx\n\n if ( a2 <= 0 )\n {\n v3 = 0;\n }\n else\n {\n v2 = a1;\n v3 = 0;\n do\n v3 += *v2++ == 0;\n while ( v2 != &a1[a2] );\n }\n return round((double)v3 / (double)a2 * 100.0) / 100.0;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\nsub rsp, 8\ntest esi, esi\njle short loc_11E1\nmov rax, rdi\nmovsxd rdx, esi\nlea rcx, [rdi+rdx*4]\nmov edx, 0\nloc_11A4:\ncmp dword ptr [rax], 1\nadc edx, 0\nadd rax, 4\ncmp rax, rcx\njnz short loc_11A4\nloc_11B3:\npxor xmm0, xmm0\ncvtsi2sd xmm0, edx\npxor xmm1, xmm1\ncvtsi2sd xmm1, esi\ndivsd xmm0, xmm1\nmulsd xmm0, cs:qword_2078; x\ncall _round\ndivsd xmm0, cs:qword_2078\nadd rsp, 8\nretn\nloc_11E1:\nmov edx, 0\njmp short loc_11B3", + "ida_strip_pseudo": "double __fastcall sub_1189(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n int v3; // edx\n\n if ( a2 <= 0 )\n {\n v3 = 0;\n }\n else\n {\n v2 = a1;\n v3 = 0;\n do\n v3 += *v2++ == 0;\n while ( v2 != &a1[a2] );\n }\n return round((double)v3 / (double)a2 * 100.0) / 100.0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1189(uint32_t *a1, int a2) {\n uint32_t *v2;\n int v3;\n if (a2 <= 0) {\n v3 = 0;\n } else {\n v2 = a1;\n v3 = 0;\n do\n v3 += *v2++ == 0;\n while (v2 != &a1[a2]);\n }\n return round((double)v3 / (double)a2 * 100.0) / 100.0;\n}", + "ida_pseudo_norm": "double func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n int v3;\n if (a2 <= 0) {\n v3 = 0;\n } else {\n v2 = a1;\n v3 = 0;\n do\n v3 += *v2++ == 0;\n while (v2 != &a1[a2]);\n }\n return round((double)v3 / (double)a2 * 100.0) / 100.0;\n}" + }, + { + "index": 137, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int nums[], int n) {\n int n1 = 0;\n for (int i = 0; i < n; i++) {\n if (nums[i] == 0) {\n n1++;\n }\n }\n double ratio = ((double)n1 / n);\n ratio = round(ratio * 100) / 100.0;\n return ratio;\n}", + "test": "int main() {\n\n int arr1[] = {0, 1, 2, -1, -5, 6, 0, -3, -2, 3, 4, 6, 8};\n\n assert(func0(arr1, 13) == 0.15);\n\n \n\n int arr2[] = {2, 1, 2, -1, -5, 6, 4, -3, -2, 3, 4, 6, 8};\n\n assert(func0(arr2, 13) == 0.00);\n\n \n\n int arr3[] = {2, 4, -6, -9, 11, -12, 14, -5, 17};\n\n assert(func0(arr3, 9) == 0.00);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x8,%rsp\ntest %esi,%esi\njle 13f0 \nlea -0x1(%rsi),%eax\nlea 0x4(%rdi,%rax,4),%rdx\nxor %eax,%eax\nnopw %cs:0x0(%rax,%rax,1)\ncmpl $0x1,(%rdi)\nadc $0x0,%eax\nadd $0x4,%rdi\ncmp %rdi,%rdx\njne 13b0 \npxor %xmm0,%xmm0\ncvtsi2sd %eax,%xmm0\npxor %xmm1,%xmm1\ncvtsi2sd %esi,%xmm1\ndivsd %xmm1,%xmm0\nmulsd 0xcb5(%rip),%xmm0\ncallq 1070 \ndivsd 0xca8(%rip),%xmm0\nadd $0x8,%rsp\nretq\nnopl (%rax)\npxor %xmm0,%xmm0\njmp 13c7 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\ntest esi, esi\njle short loc_1378\nmovsxd rax, esi\nlea rdx, [rdi+rax*4]\nxor eax, eax\nnop dword ptr [rax]\nloc_1338:\ncmp dword ptr [rdi], 1\nadc eax, 0\nadd rdi, 4\ncmp rdi, rdx\njnz short loc_1338\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nloc_134F:\npxor xmm1, xmm1\ncvtsi2sd xmm1, esi\ndivsd xmm0, xmm1\nmulsd xmm0, cs:qword_2078; x\ncall _round\ndivsd xmm0, cs:qword_2078\nadd rsp, 8\nretn\nloc_1378:\npxor xmm0, xmm0\njmp short loc_134F", + "ida_pseudo": "double __fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rdx\n int v3; // eax\n double v4; // xmm0_8\n\n if ( a2 <= 0 )\n {\n v4 = 0.0;\n }\n else\n {\n v2 = &a1[a2];\n v3 = 0;\n do\n v3 += *a1++ == 0;\n while ( a1 != v2 );\n v4 = (double)v3;\n }\n return round(v4 / (double)a2 * 100.0) / 100.0;\n}", + "ida_strip_asm": "sub_1320:\nendbr64\nsub rsp, 8\ntest esi, esi\njle short loc_1378\nmovsxd rax, esi\nlea rdx, [rdi+rax*4]\nxor eax, eax\nnop dword ptr [rax]\nloc_1338:\ncmp dword ptr [rdi], 1\nadc eax, 0\nadd rdi, 4\ncmp rdi, rdx\njnz short loc_1338\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nloc_134F:\npxor xmm1, xmm1\ncvtsi2sd xmm1, esi\ndivsd xmm0, xmm1\nmulsd xmm0, cs:qword_2078; x\ncall _round\ndivsd xmm0, cs:qword_2078\nadd rsp, 8\nretn\nloc_1378:\npxor xmm0, xmm0\njmp short loc_134F", + "ida_strip_pseudo": "double __fastcall sub_1320(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rdx\n int v3; // eax\n double v4; // xmm0_8\n\n if ( a2 <= 0 )\n {\n v4 = 0.0;\n }\n else\n {\n v2 = &a1[a2];\n v3 = 0;\n do\n v3 += *a1++ == 0;\n while ( a1 != v2 );\n v4 = (double)v3;\n }\n return round(v4 / (double)a2 * 100.0) / 100.0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1320(uint32_t *a1, int a2) {\n uint32_t *v2;\n int v3;\n double v4;\n if (a2 <= 0) {\n v4 = 0.0;\n } else {\n v2 = &a1[a2];\n v3 = 0;\n do\n v3 += *a1++ == 0;\n while (a1 != v2);\n v4 = (double)v3;\n }\n return round(v4 / (double)a2 * 100.0) / 100.0;\n}", + "ida_pseudo_norm": "double func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n int v3;\n double v4;\n if (a2 <= 0) {\n v4 = 0.0;\n } else {\n v2 = &a1[a2];\n v3 = 0;\n do\n v3 += *a1++ == 0;\n while (a1 != v2);\n v4 = (double)v3;\n }\n return round(v4 / (double)a2 * 100.0) / 100.0;\n}" + }, + { + "index": 137, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int nums[], int n) {\n int n1 = 0;\n for (int i = 0; i < n; i++) {\n if (nums[i] == 0) {\n n1++;\n }\n }\n double ratio = ((double)n1 / n);\n ratio = round(ratio * 100) / 100.0;\n return ratio;\n}", + "test": "int main() {\n\n int arr1[] = {0, 1, 2, -1, -5, 6, 0, -3, -2, 3, 4, 6, 8};\n\n assert(func0(arr1, 13) == 0.15);\n\n \n\n int arr2[] = {2, 1, 2, -1, -5, 6, 4, -3, -2, 3, 4, 6, 8};\n\n assert(func0(arr2, 13) == 0.00);\n\n \n\n int arr3[] = {2, 4, -6, -9, 11, -12, 14, -5, 17};\n\n assert(func0(arr3, 9) == 0.00);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x8,%rsp\ntest %esi,%esi\njle 1408 \nlea -0x1(%rsi),%eax\ncmp $0x3,%eax\njbe 140e \nmov %esi,%edx\npxor %xmm0,%xmm0\nmov %rdi,%rax\nshr $0x2,%edx\nmovdqa %xmm0,%xmm2\nshl $0x4,%rdx\nadd %rdi,%rdx\nnopl 0x0(%rax,%rax,1)\nmovdqu (%rax),%xmm1\nadd $0x10,%rax\npcmpeqd %xmm2,%xmm1\npsubd %xmm1,%xmm0\ncmp %rdx,%rax\njne 1358 \nmovdqa %xmm0,%xmm1\nmov %esi,%edx\npsrldq $0x8,%xmm1\nand $0xfffffffc,%edx\npaddd %xmm1,%xmm0\nmovdqa %xmm0,%xmm1\npsrldq $0x4,%xmm1\npaddd %xmm1,%xmm0\nmovd %xmm0,%eax\ntest $0x3,%sil\nje 13d3 \nmovslq %edx,%rcx\ncmpl $0x1,(%rdi,%rcx,4)\nlea 0x1(%rdx),%ecx\nadc $0x0,%eax\ncmp %esi,%ecx\njge 13d3 \nmovslq %ecx,%rcx\ncmpl $0x1,(%rdi,%rcx,4)\nlea 0x2(%rdx),%ecx\nadc $0x0,%eax\ncmp %ecx,%esi\njle 13d3 \nmovslq %ecx,%rcx\ncmpl $0x1,(%rdi,%rcx,4)\nadc $0x0,%eax\nadd $0x3,%edx\ncmp %edx,%esi\njle 13d3 \nmovslq %edx,%rdx\ncmpl $0x1,(%rdi,%rdx,4)\nadc $0x0,%eax\npxor %xmm0,%xmm0\ncvtsi2sd %eax,%xmm0\npxor %xmm1,%xmm1\ncvtsi2sd %esi,%xmm1\ndivsd %xmm1,%xmm0\nmulsd 0xca1(%rip),%xmm0\ncallq 1070 \ndivsd 0xc94(%rip),%xmm0\nadd $0x8,%rsp\nretq\nnopl 0x0(%rax)\npxor %xmm0,%xmm0\njmp 13db \nxor %edx,%edx\nxor %eax,%eax\njmp 1396 \nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\ntest esi, esi\njle loc_1400\nlea eax, [rsi-1]\nmov rcx, rdi\ncmp eax, 2\njbe loc_1406\nmov edx, esi\npxor xmm0, xmm0\nmov rax, rdi\nshr edx, 2\nmovdqa xmm2, xmm0\nshl rdx, 4\nadd rdx, rdi\nnop word ptr [rax+rax+00000000h]\nloc_1360:\nmovdqu xmm1, xmmword ptr [rax]\nadd rax, 10h\npcmpeqd xmm1, xmm2\npsubd xmm0, xmm1\ncmp rax, rdx\njnz short loc_1360\nmovdqa xmm1, xmm0\nmov edx, esi\npsrldq xmm1, 8\nand edx, 0FFFFFFFCh\npaddd xmm0, xmm1\nmovdqa xmm1, xmm0\npsrldq xmm1, 4\npaddd xmm0, xmm1\nmovd eax, xmm0\ntest sil, 3\njz short loc_13D0\nloc_139E:\nmovsxd rdi, edx\ncmp dword ptr [rcx+rdi*4], 1\nlea r8, ds:0[rdi*4]\nlea edi, [rdx+1]\nadc eax, 0\ncmp esi, edi\njle short loc_13D0\ncmp dword ptr [rcx+r8+4], 1\nadc eax, 0\nadd edx, 2\ncmp esi, edx\njle short loc_13D0\ncmp dword ptr [rcx+r8+8], 1\nadc eax, 0\nloc_13D0:\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nloc_13D8:\npxor xmm1, xmm1\ncvtsi2sd xmm1, esi\ndivsd xmm0, xmm1\nmulsd xmm0, cs:qword_2078; x\ncall _round\ndivsd xmm0, cs:qword_2078\nadd rsp, 8\nretn\nloc_1400:\npxor xmm0, xmm0\njmp short loc_13D8\nloc_1406:\nxor edx, edx\nxor eax, eax\njmp short loc_139E", + "ida_pseudo": "double __fastcall func0(const __m128i *a1, int a2)\n{\n __m128i v2; // xmm0\n const __m128i *v3; // rax\n __m128i v4; // xmm1\n int v5; // edx\n __m128i v6; // xmm0\n int v7; // eax\n __int64 v8; // r8\n double v9; // xmm0_8\n\n if ( a2 <= 0 )\n {\n v9 = 0.0;\n return round(v9 / (double)a2 * 100.0) / 100.0;\n }\n if ( (unsigned int)(a2 - 1) <= 2 )\n {\n v5 = 0;\n v7 = 0;\n goto LABEL_6;\n }\n v2 = 0LL;\n v3 = a1;\n do\n {\n v4 = _mm_loadu_si128(v3++);\n v2 = _mm_sub_epi32(v2, _mm_cmpeq_epi32(v4, (__m128i)0LL));\n }\n while ( v3 != &a1[(unsigned int)a2 >> 2] );\n v5 = a2 & 0x7FFFFFFC;\n v6 = _mm_add_epi32(v2, _mm_srli_si128(v2, 8));\n v7 = _mm_cvtsi128_si32(_mm_add_epi32(v6, _mm_srli_si128(v6, 4)));\n if ( (a2 & 3) != 0 )\n {\nLABEL_6:\n v8 = v5;\n v7 += a1->m128i_i32[v8] == 0;\n if ( a2 > v5 + 1 )\n {\n v7 += a1->m128i_i32[v8 + 1] == 0;\n if ( a2 > v5 + 2 )\n v7 += a1->m128i_i32[v8 + 2] == 0;\n }\n }\n v9 = (double)v7;\n return round(v9 / (double)a2 * 100.0) / 100.0;\n}", + "ida_strip_asm": "sub_1320:\nendbr64\nsub rsp, 8\ntest esi, esi\njle loc_1400\nlea eax, [rsi-1]\nmov rcx, rdi\ncmp eax, 2\njbe loc_1406\nmov edx, esi\npxor xmm0, xmm0\nmov rax, rdi\nshr edx, 2\nmovdqa xmm2, xmm0\nshl rdx, 4\nadd rdx, rdi\nnop word ptr [rax+rax+00000000h]\nloc_1360:\nmovdqu xmm1, xmmword ptr [rax]\nadd rax, 10h\npcmpeqd xmm1, xmm2\npsubd xmm0, xmm1\ncmp rax, rdx\njnz short loc_1360\nmovdqa xmm1, xmm0\nmov edx, esi\npsrldq xmm1, 8\nand edx, 0FFFFFFFCh\npaddd xmm0, xmm1\nmovdqa xmm1, xmm0\npsrldq xmm1, 4\npaddd xmm0, xmm1\nmovd eax, xmm0\ntest sil, 3\njz short loc_13D0\nloc_139E:\nmovsxd rdi, edx\ncmp dword ptr [rcx+rdi*4], 1\nlea r8, ds:0[rdi*4]\nlea edi, [rdx+1]\nadc eax, 0\ncmp esi, edi\njle short loc_13D0\ncmp dword ptr [rcx+r8+4], 1\nadc eax, 0\nadd edx, 2\ncmp esi, edx\njle short loc_13D0\ncmp dword ptr [rcx+r8+8], 1\nadc eax, 0\nloc_13D0:\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nloc_13D8:\npxor xmm1, xmm1\ncvtsi2sd xmm1, esi\ndivsd xmm0, xmm1\nmulsd xmm0, cs:qword_2078; x\ncall _round\ndivsd xmm0, cs:qword_2078\nadd rsp, 8\nretn\nloc_1400:\npxor xmm0, xmm0\njmp short loc_13D8\nloc_1406:\nxor edx, edx\nxor eax, eax\njmp short loc_139E", + "ida_strip_pseudo": "double __fastcall sub_1320(const __m128i *a1, int a2)\n{\n __m128i v2; // xmm0\n const __m128i *v3; // rax\n __m128i v4; // xmm1\n int v5; // edx\n __m128i v6; // xmm0\n int v7; // eax\n __int64 v8; // r8\n double v9; // xmm0_8\n\n if ( a2 <= 0 )\n {\n v9 = 0.0;\n return round(v9 / (double)a2 * 100.0) / 100.0;\n }\n if ( (unsigned int)(a2 - 1) <= 2 )\n {\n v5 = 0;\n v7 = 0;\n goto LABEL_6;\n }\n v2 = 0LL;\n v3 = a1;\n do\n {\n v4 = _mm_loadu_si128(v3++);\n v2 = _mm_sub_epi32(v2, _mm_cmpeq_epi32(v4, (__m128i)0LL));\n }\n while ( v3 != &a1[(unsigned int)a2 >> 2] );\n v5 = a2 & 0x7FFFFFFC;\n v6 = _mm_add_epi32(v2, _mm_srli_si128(v2, 8));\n v7 = _mm_cvtsi128_si32(_mm_add_epi32(v6, _mm_srli_si128(v6, 4)));\n if ( (a2 & 3) != 0 )\n {\nLABEL_6:\n v8 = v5;\n v7 += a1->m128i_i32[v8] == 0;\n if ( a2 > v5 + 1 )\n {\n v7 += a1->m128i_i32[v8 + 1] == 0;\n if ( a2 > v5 + 2 )\n v7 += a1->m128i_i32[v8 + 2] == 0;\n }\n }\n v9 = (double)v7;\n return round(v9 / (double)a2 * 100.0) / 100.0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1320(const __m128i *a1, int a2) {\n __m128i v2;\n const __m128i *v3;\n __m128i v4;\n int v5;\n __m128i v6;\n int v7;\n long long v8;\n double v9;\n if (a2 <= 0) {\n v9 = 0.0;\n return round(v9 / (double)a2 * 100.0) / 100.0;\n }\n if ((unsigned int)(a2 - 1) <= 2) {\n v5 = 0;\n v7 = 0;\n goto LABEL_6;\n }\n v2 = 0LL;\n v3 = a1;\n do {\n v4 = _mm_loadu_si128(v3++);\n v2 = _mm_sub_epi32(v2, _mm_cmpeq_epi32(v4, (__m128i)0LL));\n } while (v3 != &a1[(unsigned int)a2 >> 2]);\n v5 = a2 & 2147483644;\n v6 = _mm_add_epi32(v2, _mm_srli_si128(v2, 8));\n v7 = _mm_cvtsi128_si32(_mm_add_epi32(v6, _mm_srli_si128(v6, 4)));\n if ((a2 & 3) != 0) {\n LABEL_6:\n v8 = v5;\n v7 += a1->m128i_i32[v8] == 0;\n if (a2 > v5 + 1) {\n v7 += a1->m128i_i32[v8 + 1] == 0;\n if (a2 > v5 + 2) v7 += a1->m128i_i32[v8 + 2] == 0;\n }\n }\n v9 = (double)v7;\n return round(v9 / (double)a2 * 100.0) / 100.0;\n}", + "ida_pseudo_norm": "double func0(const __m128i *a1, int a2) {\n __m128i v2;\n const __m128i *v3;\n __m128i v4;\n int v5;\n __m128i v6;\n int v7;\n long long v8;\n double v9;\n if (a2 <= 0) {\n v9 = 0.0;\n return round(v9 / (double)a2 * 100.0) / 100.0;\n }\n if ((unsigned int)(a2 - 1) <= 2) {\n v5 = 0;\n v7 = 0;\n goto LABEL_6;\n }\n v2 = 0LL;\n v3 = a1;\n do {\n v4 = _mm_loadu_si128(v3++);\n v2 = _mm_sub_epi32(v2, _mm_cmpeq_epi32(v4, (__m128i)0LL));\n } while (v3 != &a1[(unsigned int)a2 >> 2]);\n v5 = a2 & 2147483644;\n v6 = _mm_add_epi32(v2, _mm_srli_si128(v2, 8));\n v7 = _mm_cvtsi128_si32(_mm_add_epi32(v6, _mm_srli_si128(v6, 4)));\n if ((a2 & 3) != 0) {\n LABEL_6:\n v8 = v5;\n v7 += a1->m128i_i32[v8] == 0;\n if (a2 > v5 + 1) {\n v7 += a1->m128i_i32[v8 + 1] == 0;\n if (a2 > v5 + 2) v7 += a1->m128i_i32[v8 + 2] == 0;\n }\n }\n v9 = (double)v7;\n return round(v9 / (double)a2 * 100.0) / 100.0;\n}" + }, + { + "index": 138, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int n) {\n if (n % 2 == 1) {\n return false;\n } else {\n return true;\n }\n}", + "test": "int main() {\n\n assert(func0(10) == true);\n\n assert(func0(7) == false);\n\n assert(func0(14) == true);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncltd\nshr $0x1f,%edx\nadd %edx,%eax\nand $0x1,%eax\nsub %edx,%eax\ncmp $0x1,%eax\njne 116e \nmov $0x0,%eax\njmp 1173 \nmov $0x1,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov edx, [rbp+var_4]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\ncmp eax, 1\njnz short loc_1174\nmov eax, 0\njmp short loc_1179\nloc_1174:\nmov eax, 1\nloc_1179:\npop rbp\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(int a1)\n{\n return a1 % 2 != 1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov edx, [rbp+var_4]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\ncmp eax, 1\njnz short loc_1174\nmov eax, 0\njmp short loc_1179\nloc_1174:\nmov eax, 1\nloc_1179:\npop rbp\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1149(int a1)\n{\n return a1 % 2 != 1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1149(int a1) { return a1 % 2 != 1; }", + "ida_pseudo_norm": "uint8_t func0(int a1) { return a1 % 2 != 1; }" + }, + { + "index": 139, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "double func0(double r) {\n double perimeter = 2 * 3.1415 * r;\n return perimeter;\n}", + "test": "int main() {\n\n assert(func0(10) == 62.830000000000005);\n\n assert(func0(5) == 31.415000000000003);\n\n assert(func0(4) == 25.132);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmovsd %xmm0,-0x18(%rbp)\nmovsd -0x18(%rbp),%xmm1\nmovsd 0xf3d(%rip),%xmm0\nmulsd %xmm1,%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmovsd -0x8(%rbp),%xmm0\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmovsd [rbp+var_18], xmm0\nmovsd xmm1, [rbp+var_18]\nmovsd xmm0, cs:qword_2080\nmulsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "double __fastcall func0(double a1)\n{\n return 6.283 * a1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmovsd [rbp+var_18], xmm0\nmovsd xmm1, [rbp+var_18]\nmovsd xmm0, cs:qword_2080\nmulsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "double __fastcall sub_1149(double a1)\n{\n return 6.283 * a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1149(double a1) { return 6.283 * a1; }", + "ida_pseudo_norm": "double func0(double a1) { return 6.283 * a1; }" + }, + { + "index": 140, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n#define MAX_SIZE 100\n\n\n\n", + "func": "int func0(int test_list[][MAX_SIZE], int sizes[], int no_of_lists, int res[]) {\n int res_index = 0;\n bool found[MAX_SIZE] = {false};\n for (int i = 0; i < no_of_lists; ++i) {\n for (int j = 0; j < sizes[i]; ++j) {\n int elem = test_list[i][j];\n if (!found[elem]) {\n found[elem] = true;\n res[res_index++] = elem;\n }\n }\n }\n return res_index;\n}", + "test": "int main() {\n\n int test_list1[][MAX_SIZE] = {{3, 4, 5}, {4, 5, 7}, {1, 4}};\n\n int sizes1[] = {3, 3, 2};\n\n int result1[MAX_SIZE];\n\n int len1 = func0(test_list1, sizes1, 3, result1);\n\n int expected1[] = {3, 4, 5, 7, 1};\n\n assert(len1 == 5);\n\n for (int i = 0; i < len1; ++i) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n\n\n int test_list2[][MAX_SIZE] = {{1, 2, 3}, {4, 2, 3}, {7, 8}};\n\n int sizes2[] = {3, 3, 2};\n\n int result2[MAX_SIZE];\n\n int len2 = func0(test_list2, sizes2, 3, result2);\n\n int expected2[] = {1, 2, 3, 4, 7, 8};\n\n assert(len2 == 6);\n\n for (int i = 0; i < len2; ++i) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n\n\n int test_list3[][MAX_SIZE] = {{7, 8, 9}, {10, 11, 12}, {10, 11}};\n\n int sizes3[] = {3, 3, 2};\n\n int result3[MAX_SIZE];\n\n int len3 = func0(test_list3, sizes3, 3, result3);\n\n int expected3[] = {7, 8, 9, 10, 11, 12};\n\n assert(len3 == 6);\n\n for (int i = 0; i < len3; ++i) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0xa0,%rsp\nmov %rdi,-0x88(%rbp)\nmov %rsi,-0x90(%rbp)\nmov %edx,-0x94(%rbp)\nmov %rcx,-0xa0(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovl $0x0,-0x80(%rbp)\nlea -0x70(%rbp),%rdx\nmov $0x0,%eax\nmov $0xc,%ecx\nmov %rdx,%rdi\nrep stos %rax,%es:(%rdi)\nmov %rdi,%rdx\nmov %eax,(%rdx)\nadd $0x4,%rdx\nmovl $0x0,-0x7c(%rbp)\njmpq 1279 \nmovl $0x0,-0x78(%rbp)\njmp 1253 \nmov -0x7c(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x88(%rbp),%rax\nadd %rax,%rdx\nmov -0x78(%rbp),%eax\ncltq\nmov (%rdx,%rax,4),%eax\nmov %eax,-0x74(%rbp)\nmov -0x74(%rbp),%eax\ncltq\nmovzbl -0x70(%rbp,%rax,1),%eax\nxor $0x1,%eax\ntest %al,%al\nje 124f \nmov -0x74(%rbp),%eax\ncltq\nmovb $0x1,-0x70(%rbp,%rax,1)\nmov -0x80(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x80(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0xa0(%rbp),%rax\nadd %rax,%rdx\nmov -0x74(%rbp),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x78(%rbp)\nmov -0x7c(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x90(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x78(%rbp)\njl 11db \naddl $0x1,-0x7c(%rbp)\nmov -0x7c(%rbp),%eax\ncmp -0x94(%rbp),%eax\njl 11d2 \nmov -0x80(%rbp),%eax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 129f \ncallq 1060 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0A0h\nmov [rbp+var_88], rdi\nmov [rbp+var_90], rsi\nmov [rbp+var_94], edx\nmov [rbp+var_A0], rcx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_80], 0\nlea rdx, [rbp+var_70]\nmov eax, 0\nmov ecx, 0Ch\nmov rdi, rdx\nrep stosq\nmov rdx, rdi\nmov [rdx], eax\nadd rdx, 4\nmov [rbp+var_7C], 0\njmp loc_1279\nloc_11D2:\nmov [rbp+var_78], 0\njmp short loc_1253\nloc_11DB:\nmov eax, [rbp+var_7C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_88]\nadd rdx, rax\nmov eax, [rbp+var_78]\ncdqe\nmov eax, [rdx+rax*4]\nmov [rbp+var_74], eax\nmov eax, [rbp+var_74]\ncdqe\nmovzx eax, [rbp+rax+var_70]\nxor eax, 1\ntest al, al\njz short loc_124F\nmov eax, [rbp+var_74]\ncdqe\nmov [rbp+rax+var_70], 1\nmov eax, [rbp+var_80]\nlea edx, [rax+1]\nmov [rbp+var_80], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_A0]\nadd rdx, rax\nmov eax, [rbp+var_74]\nmov [rdx], eax\nloc_124F:\nadd [rbp+var_78], 1\nloc_1253:\nmov eax, [rbp+var_7C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_90]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_78], eax\njl loc_11DB\nadd [rbp+var_7C], 1\nloc_1279:\nmov eax, [rbp+var_7C]\ncmp eax, [rbp+var_94]\njl loc_11D2\nmov eax, [rbp+var_80]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_129F\ncall ___stack_chk_fail\nlocret_129F:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3, __int64 a4)\n{\n int v4; // eax\n unsigned int v6; // [rsp+20h] [rbp-80h]\n int i; // [rsp+24h] [rbp-7Ch]\n int j; // [rsp+28h] [rbp-78h]\n int v9; // [rsp+2Ch] [rbp-74h]\n _BYTE v10[96]; // [rsp+30h] [rbp-70h] BYREF\n int v11; // [rsp+90h] [rbp-10h]\n unsigned __int64 v12; // [rsp+98h] [rbp-8h]\n\n v12 = __readfsqword(0x28u);\n v6 = 0;\n memset(v10, 0, sizeof(v10));\n v11 = 0;\n for ( i = 0; i < a3; ++i )\n {\n for ( j = 0; j < *(_DWORD *)(4LL * i + a2); ++j )\n {\n v9 = *(_DWORD *)(a1 + 400LL * i + 4LL * j);\n if ( v10[v9] != 1 )\n {\n v10[v9] = 1;\n v4 = v6++;\n *(_DWORD *)(a4 + 4LL * v4) = v9;\n }\n }\n }\n return v6;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0A0h\nmov [rbp+var_88], rdi\nmov [rbp+var_90], rsi\nmov [rbp+var_94], edx\nmov [rbp+var_A0], rcx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_80], 0\nlea rdx, [rbp+var_70]\nmov eax, 0\nmov ecx, 0Ch\nmov rdi, rdx\nrep stosq\nmov rdx, rdi\nmov [rdx], eax\nadd rdx, 4\nmov [rbp+var_7C], 0\njmp loc_1279\nloc_11D2:\nmov [rbp+var_78], 0\njmp short loc_1253\nloc_11DB:\nmov eax, [rbp+var_7C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_88]\nadd rdx, rax\nmov eax, [rbp+var_78]\ncdqe\nmov eax, [rdx+rax*4]\nmov [rbp+var_74], eax\nmov eax, [rbp+var_74]\ncdqe\nmovzx eax, [rbp+rax+var_70]\nxor eax, 1\ntest al, al\njz short loc_124F\nmov eax, [rbp+var_74]\ncdqe\nmov [rbp+rax+var_70], 1\nmov eax, [rbp+var_80]\nlea edx, [rax+1]\nmov [rbp+var_80], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_A0]\nadd rdx, rax\nmov eax, [rbp+var_74]\nmov [rdx], eax\nloc_124F:\nadd [rbp+var_78], 1\nloc_1253:\nmov eax, [rbp+var_7C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_90]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_78], eax\njl loc_11DB\nadd [rbp+var_7C], 1\nloc_1279:\nmov eax, [rbp+var_7C]\ncmp eax, [rbp+var_94]\njl loc_11D2\nmov eax, [rbp+var_80]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_129F\ncall ___stack_chk_fail\nlocret_129F:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, int a3, __int64 a4)\n{\n int v4; // eax\n unsigned int v6; // [rsp+20h] [rbp-80h]\n int i; // [rsp+24h] [rbp-7Ch]\n int j; // [rsp+28h] [rbp-78h]\n int v9; // [rsp+2Ch] [rbp-74h]\n _BYTE v10[96]; // [rsp+30h] [rbp-70h] BYREF\n int v11; // [rsp+90h] [rbp-10h]\n unsigned __int64 v12; // [rsp+98h] [rbp-8h]\n\n v12 = __readfsqword(0x28u);\n v6 = 0;\n memset(v10, 0, sizeof(v10));\n v11 = 0;\n for ( i = 0; i < a3; ++i )\n {\n for ( j = 0; j < *(_DWORD *)(4LL * i + a2); ++j )\n {\n v9 = *(_DWORD *)(a1 + 400LL * i + 4LL * j);\n if ( v10[v9] != 1 )\n {\n v10[v9] = 1;\n v4 = v6++;\n *(_DWORD *)(a4 + 4LL * v4) = v9;\n }\n }\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, int a3, long long a4) {\n int v4;\n unsigned int v6;\n int i;\n int j;\n int v9;\n uint8_t v10[96];\n int v11;\n unsigned long long v12;\n v12 = __readfsqword(40u);\n v6 = 0;\n memset(v10, 0, sizeof(v10));\n v11 = 0;\n for (i = 0; i < a3; ++i) {\n for (j = 0; j < *(uint32_t *)(4LL * i + a2); ++j) {\n v9 = *(uint32_t *)(a1 + 400LL * i + 4LL * j);\n if (v10[v9] != 1) {\n v10[v9] = 1;\n v4 = v6++;\n *(uint32_t *)(a4 + 4LL * v4) = v9;\n }\n }\n }\n return v6;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3, long long a4) {\n int v4;\n unsigned int v6;\n int i;\n int j;\n int v9;\n uint8_t v10[96];\n int v11;\n unsigned long long v12;\n v12 = __readfsqword(40u);\n v6 = 0;\n memset(v10, 0, sizeof(v10));\n v11 = 0;\n for (i = 0; i < a3; ++i) {\n for (j = 0; j < *(uint32_t *)(4LL * i + a2); ++j) {\n v9 = *(uint32_t *)(a1 + 400LL * i + 4LL * j);\n if (v10[v9] != 1) {\n v10[v9] = 1;\n v4 = v6++;\n *(uint32_t *)(a4 + 4LL * v4) = v9;\n }\n }\n }\n return v6;\n}" + }, + { + "index": 140, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n#define MAX_SIZE 100\n\n\n\n", + "func": "int func0(int test_list[][MAX_SIZE], int sizes[], int no_of_lists, int res[]) {\n int res_index = 0;\n bool found[MAX_SIZE] = {false};\n for (int i = 0; i < no_of_lists; ++i) {\n for (int j = 0; j < sizes[i]; ++j) {\n int elem = test_list[i][j];\n if (!found[elem]) {\n found[elem] = true;\n res[res_index++] = elem;\n }\n }\n }\n return res_index;\n}", + "test": "int main() {\n\n int test_list1[][MAX_SIZE] = {{3, 4, 5}, {4, 5, 7}, {1, 4}};\n\n int sizes1[] = {3, 3, 2};\n\n int result1[MAX_SIZE];\n\n int len1 = func0(test_list1, sizes1, 3, result1);\n\n int expected1[] = {3, 4, 5, 7, 1};\n\n assert(len1 == 5);\n\n for (int i = 0; i < len1; ++i) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n\n\n int test_list2[][MAX_SIZE] = {{1, 2, 3}, {4, 2, 3}, {7, 8}};\n\n int sizes2[] = {3, 3, 2};\n\n int result2[MAX_SIZE];\n\n int len2 = func0(test_list2, sizes2, 3, result2);\n\n int expected2[] = {1, 2, 3, 4, 7, 8};\n\n assert(len2 == 6);\n\n for (int i = 0; i < len2; ++i) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n\n\n int test_list3[][MAX_SIZE] = {{7, 8, 9}, {10, 11, 12}, {10, 11}};\n\n int sizes3[] = {3, 3, 2};\n\n int result3[MAX_SIZE];\n\n int len3 = func0(test_list3, sizes3, 3, result3);\n\n int expected3[] = {7, 8, 9, 10, 11, 12};\n\n assert(len3 == 6);\n\n for (int i = 0; i < len3; ++i) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nsub $0x70,%rsp\nmov %rdi,%r11\nmov %rcx,%r10\nmov %fs:0x28,%rax\nmov %rax,0x68(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nmov $0xc,%ecx\nrep stos %rax,%es:(%rdi)\nmovl $0x0,(%rdi)\ntest %edx,%edx\njle 11f7 \nmov %rsi,%r9\nlea -0x1(%rdx),%eax\nlea 0x4(%rsi,%rax,4),%rbx\nmov $0x0,%esi\njmp 11e4 \nadd $0x1,%rax\ncmp %eax,(%r8)\njle 11d4 \nmov (%rdi,%rax,4),%edx\nmovslq %edx,%rcx\ncmpb $0x0,(%rsp,%rcx,1)\njne 11af \nmovb $0x1,(%rsp,%rcx,1)\nmovslq %esi,%rcx\nmov %edx,(%r10,%rcx,4)\nlea 0x1(%rsi),%esi\njmp 11af \nadd $0x4,%r9\nadd $0x190,%r11\ncmp %rbx,%r9\nje 11fc \nmov %r9,%r8\nmov %r11,%rdi\nmov $0x0,%eax\ncmpl $0x0,(%r9)\njg 11b8 \njmp 11d4 \nmov $0x0,%esi\nmov 0x68(%rsp),%rax\nxor %fs:0x28,%rax\njne 1214 \nmov %esi,%eax\nadd $0x70,%rsp\npop %rbx\nretq\ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbx\nsub rsp, 70h\nmov r11, rdi\nmov r10, rcx\nmov rax, fs:28h\nmov [rsp+78h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nmov ecx, 0Ch\nrep stosq\nmov dword ptr [rdi], 0\ntest edx, edx\njle short loc_11F6\nmov r9, rsi\nmovsxd rdx, edx\nlea rbx, [rsi+rdx*4]\nmov esi, 0\njmp short loc_11E3\nloc_11AE:\nadd rax, 1\ncmp [r8], eax\njle short loc_11D3\nloc_11B7:\nmov edx, [rdi+rax*4]\nmovsxd rcx, edx\ncmp [rsp+rcx+78h+var_78], 0\njnz short loc_11AE\nmov [rsp+rcx+78h+var_78], 1\nmovsxd rcx, esi\nmov [r10+rcx*4], edx\nlea esi, [rsi+1]\njmp short loc_11AE\nloc_11D3:\nadd r9, 4\nadd r11, 190h\ncmp r9, rbx\njz short loc_11FB\nloc_11E3:\nmov r8, r9\nmov rdi, r11\nmov eax, 0\ncmp dword ptr [r9], 0\njg short loc_11B7\njmp short loc_11D3\nloc_11F6:\nmov esi, 0\nloc_11FB:\nmov rax, [rsp+78h+var_10]\nsub rax, fs:28h\njnz short loc_1213\nmov eax, esi\nadd rsp, 70h\npop rbx\nretn\nloc_1213:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, _DWORD *a2, int a3, __int64 a4)\n{\n _DWORD *v5; // r9\n _DWORD *v6; // rbx\n unsigned int v7; // esi\n __int64 i; // rax\n int v9; // edx\n _BYTE v11[96]; // [rsp+0h] [rbp-78h] BYREF\n int v12; // [rsp+60h] [rbp-18h]\n unsigned __int64 v13; // [rsp+68h] [rbp-10h]\n\n v13 = __readfsqword(0x28u);\n memset(v11, 0, sizeof(v11));\n v12 = 0;\n if ( a3 <= 0 )\n {\n return 0;\n }\n else\n {\n v5 = a2;\n v6 = &a2[a3];\n v7 = 0;\n do\n {\n for ( i = 0LL; *v5 > (int)i; ++i )\n {\n v9 = *(_DWORD *)(a1 + 4 * i);\n if ( !v11[v9] )\n {\n v11[v9] = 1;\n *(_DWORD *)(a4 + 4LL * (int)v7++) = v9;\n }\n }\n ++v5;\n a1 += 400LL;\n }\n while ( v5 != v6 );\n }\n return v7;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbx\nsub rsp, 70h\nmov r11, rdi\nmov r10, rcx\nmov rax, fs:28h\nmov [rsp+78h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nmov ecx, 0Ch\nrep stosq\nmov dword ptr [rdi], 0\ntest edx, edx\njle short loc_11F6\nmov r9, rsi\nmovsxd rdx, edx\nlea rbx, [rsi+rdx*4]\nmov esi, 0\njmp short loc_11E3\nloc_11AE:\nadd rax, 1\ncmp [r8], eax\njle short loc_11D3\nloc_11B7:\nmov edx, [rdi+rax*4]\nmovsxd rcx, edx\ncmp [rsp+rcx+78h+var_78], 0\njnz short loc_11AE\nmov [rsp+rcx+78h+var_78], 1\nmovsxd rcx, esi\nmov [r10+rcx*4], edx\nlea esi, [rsi+1]\njmp short loc_11AE\nloc_11D3:\nadd r9, 4\nadd r11, 190h\ncmp r9, rbx\njz short loc_11FB\nloc_11E3:\nmov r8, r9\nmov rdi, r11\nmov eax, 0\ncmp dword ptr [r9], 0\njg short loc_11B7\njmp short loc_11D3\nloc_11F6:\nmov esi, 0\nloc_11FB:\nmov rax, [rsp+78h+var_10]\nsub rax, fs:28h\njnz short loc_1213\nmov eax, esi\nadd rsp, 70h\npop rbx\nretn\nloc_1213:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, _DWORD *a2, int a3, __int64 a4)\n{\n _DWORD *v5; // r9\n _DWORD *v6; // rbx\n unsigned int v7; // esi\n __int64 i; // rax\n int v9; // edx\n _BYTE v11[96]; // [rsp+0h] [rbp-78h] BYREF\n int v12; // [rsp+60h] [rbp-18h]\n unsigned __int64 v13; // [rsp+68h] [rbp-10h]\n\n v13 = __readfsqword(0x28u);\n memset(v11, 0, sizeof(v11));\n v12 = 0;\n if ( a3 <= 0 )\n {\n return 0;\n }\n else\n {\n v5 = a2;\n v6 = &a2[a3];\n v7 = 0;\n do\n {\n for ( i = 0LL; *v5 > (int)i; ++i )\n {\n v9 = *(_DWORD *)(a1 + 4 * i);\n if ( !v11[v9] )\n {\n v11[v9] = 1;\n *(_DWORD *)(a4 + 4LL * (int)v7++) = v9;\n }\n }\n ++v5;\n a1 += 400LL;\n }\n while ( v5 != v6 );\n }\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, uint32_t *a2, int a3, long long a4) {\n uint32_t *v5;\n uint32_t *v6;\n unsigned int v7;\n long long i;\n int v9;\n uint8_t v11[96];\n int v12;\n unsigned long long v13;\n v13 = __readfsqword(40u);\n memset(v11, 0, sizeof(v11));\n v12 = 0;\n if (a3 <= 0) {\n return 0;\n } else {\n v5 = a2;\n v6 = &a2[a3];\n v7 = 0;\n do {\n for (i = 0LL; *v5 > (int)i; ++i) {\n v9 = *(uint32_t *)(a1 + 4 * i);\n if (!v11[v9]) {\n v11[v9] = 1;\n *(uint32_t *)(a4 + 4LL * (int)v7++) = v9;\n }\n }\n ++v5;\n a1 += 400LL;\n } while (v5 != v6);\n }\n return v7;\n}", + "ida_pseudo_norm": "long long func0(long long a1, uint32_t *a2, int a3, long long a4) {\n uint32_t *v5;\n uint32_t *v6;\n unsigned int v7;\n long long i;\n int v9;\n uint8_t v11[96];\n int v12;\n unsigned long long v13;\n v13 = __readfsqword(40u);\n memset(v11, 0, sizeof(v11));\n v12 = 0;\n if (a3 <= 0) {\n return 0;\n } else {\n v5 = a2;\n v6 = &a2[a3];\n v7 = 0;\n do {\n for (i = 0LL; *v5 > (int)i; ++i) {\n v9 = *(uint32_t *)(a1 + 4 * i);\n if (!v11[v9]) {\n v11[v9] = 1;\n *(uint32_t *)(a4 + 4LL * (int)v7++) = v9;\n }\n }\n ++v5;\n a1 += 400LL;\n } while (v5 != v6);\n }\n return v7;\n}" + }, + { + "index": 140, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n#define MAX_SIZE 100\n\n\n\n", + "func": "int func0(int test_list[][MAX_SIZE], int sizes[], int no_of_lists, int res[]) {\n int res_index = 0;\n bool found[MAX_SIZE] = {false};\n for (int i = 0; i < no_of_lists; ++i) {\n for (int j = 0; j < sizes[i]; ++j) {\n int elem = test_list[i][j];\n if (!found[elem]) {\n found[elem] = true;\n res[res_index++] = elem;\n }\n }\n }\n return res_index;\n}", + "test": "int main() {\n\n int test_list1[][MAX_SIZE] = {{3, 4, 5}, {4, 5, 7}, {1, 4}};\n\n int sizes1[] = {3, 3, 2};\n\n int result1[MAX_SIZE];\n\n int len1 = func0(test_list1, sizes1, 3, result1);\n\n int expected1[] = {3, 4, 5, 7, 1};\n\n assert(len1 == 5);\n\n for (int i = 0; i < len1; ++i) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n\n\n int test_list2[][MAX_SIZE] = {{1, 2, 3}, {4, 2, 3}, {7, 8}};\n\n int sizes2[] = {3, 3, 2};\n\n int result2[MAX_SIZE];\n\n int len2 = func0(test_list2, sizes2, 3, result2);\n\n int expected2[] = {1, 2, 3, 4, 7, 8};\n\n assert(len2 == 6);\n\n for (int i = 0; i < len2; ++i) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n\n\n int test_list3[][MAX_SIZE] = {{7, 8, 9}, {10, 11, 12}, {10, 11}};\n\n int sizes3[] = {3, 3, 2};\n\n int result3[MAX_SIZE];\n\n int len3 = func0(test_list3, sizes3, 3, result3);\n\n int expected3[] = {7, 8, 9, 10, 11, 12};\n\n assert(len3 == 6);\n\n for (int i = 0; i < len3; ++i) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x78,%rsp\nmov %rdi,%r8\nmov %rcx,%r9\nmov $0xc,%ecx\nmov %fs:0x28,%rax\nmov %rax,0x68(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nrep stos %rax,%es:(%rdi)\nmovl $0x0,(%rdi)\ntest %edx,%edx\njle 15ac \nlea -0x1(%rdx),%eax\nmov %r8,%rdi\nxor %r8d,%r8d\nlea 0x4(%rsi,%rax,4),%r10\nnopl 0x0(%rax)\nmov (%rsi),%edx\nxor %eax,%eax\ntest %edx,%edx\njle 1584 \nmovslq (%rdi,%rax,4),%rcx\ncmpb $0x0,(%rsp,%rcx,1)\nmov %rcx,%rdx\njne 157c \nmovb $0x1,(%rsp,%rcx,1)\nmovslq %r8d,%rcx\nadd $0x1,%r8d\nmov %edx,(%r9,%rcx,4)\nadd $0x1,%rax\ncmp %eax,(%rsi)\njg 1560 \nadd $0x4,%rsi\nadd $0x190,%rdi\ncmp %r10,%rsi\njne 1558 \nmov 0x68(%rsp),%rax\nxor %fs:0x28,%rax\njne 15b1 \nmov %r8d,%eax\nadd $0x78,%rsp\nretq\nxor %r8d,%r8d\njmp 1594 \ncallq 1060 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 78h\nmov r8, rdi\nmov r9, rcx\nmov ecx, 0Ch\nmov rax, fs:28h\nmov [rsp+78h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\nmov dword ptr [rdi], 0\ntest edx, edx\njle short loc_156A\nmovsxd rdx, edx\nxor edi, edi\nlea r10, [rsi+rdx*4]\nnop dword ptr [rax+00h]\nloc_1510:\nmov edx, [rsi]\nxor eax, eax\ntest edx, edx\njle short loc_1543\nnop dword ptr [rax+rax+00000000h]\nloc_1520:\nmovsxd rcx, dword ptr [r8+rax*4]\ncmp [rsp+rcx+78h+var_78], 0\nmov rdx, rcx\njnz short loc_153B\nmov [rsp+rcx+78h+var_78], 1\nmovsxd rcx, edi\nadd edi, 1\nmov [r9+rcx*4], edx\nloc_153B:\nadd rax, 1\ncmp [rsi], eax\njg short loc_1520\nloc_1543:\nadd rsi, 4\nadd r8, 190h\ncmp rsi, r10\njnz short loc_1510\nloc_1553:\nmov rax, [rsp+78h+var_10]\nsub rax, fs:28h\njnz short loc_156E\nmov eax, edi\nadd rsp, 78h\nretn\nloc_156A:\nxor edi, edi\njmp short loc_1553\nloc_156E:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, _DWORD *a2, int a3, __int64 a4)\n{\n unsigned int v6; // edi\n _DWORD *v7; // r10\n __int64 i; // rax\n int v9; // edx\n __int64 v10; // rcx\n _BYTE v12[96]; // [rsp+0h] [rbp-78h] BYREF\n int v13; // [rsp+60h] [rbp-18h]\n unsigned __int64 v14; // [rsp+68h] [rbp-10h]\n\n v14 = __readfsqword(0x28u);\n memset(v12, 0, sizeof(v12));\n v13 = 0;\n if ( a3 <= 0 )\n {\n return 0;\n }\n else\n {\n v6 = 0;\n v7 = &a2[a3];\n do\n {\n for ( i = 0LL; *a2 > (int)i; ++i )\n {\n v9 = *(_DWORD *)(a1 + 4 * i);\n if ( !v12[v9] )\n {\n v12[*(int *)(a1 + 4 * i)] = 1;\n v10 = (int)v6++;\n *(_DWORD *)(a4 + 4 * v10) = v9;\n }\n }\n ++a2;\n a1 += 400LL;\n }\n while ( a2 != v7 );\n }\n return v6;\n}", + "ida_strip_asm": "sub_14D0:\nendbr64\nsub rsp, 78h\nmov r8, rdi\nmov r9, rcx\nmov ecx, 0Ch\nmov rax, fs:28h\nmov [rsp+78h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\nmov dword ptr [rdi], 0\ntest edx, edx\njle short loc_156A\nmovsxd rdx, edx\nxor edi, edi\nlea r10, [rsi+rdx*4]\nnop dword ptr [rax+00h]\nloc_1510:\nmov edx, [rsi]\nxor eax, eax\ntest edx, edx\njle short loc_1543\nnop dword ptr [rax+rax+00000000h]\nloc_1520:\nmovsxd rcx, dword ptr [r8+rax*4]\ncmp [rsp+rcx+78h+var_78], 0\nmov rdx, rcx\njnz short loc_153B\nmov [rsp+rcx+78h+var_78], 1\nmovsxd rcx, edi\nadd edi, 1\nmov [r9+rcx*4], edx\nloc_153B:\nadd rax, 1\ncmp [rsi], eax\njg short loc_1520\nloc_1543:\nadd rsi, 4\nadd r8, 190h\ncmp rsi, r10\njnz short loc_1510\nloc_1553:\nmov rax, [rsp+78h+var_10]\nsub rax, fs:28h\njnz short loc_156E\nmov eax, edi\nadd rsp, 78h\nretn\nloc_156A:\nxor edi, edi\njmp short loc_1553\nloc_156E:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_14D0(__int64 a1, _DWORD *a2, int a3, __int64 a4)\n{\n unsigned int v6; // edi\n _DWORD *v7; // r10\n __int64 i; // rax\n int v9; // edx\n __int64 v10; // rcx\n _BYTE v12[96]; // [rsp+0h] [rbp-78h] BYREF\n int v13; // [rsp+60h] [rbp-18h]\n unsigned __int64 v14; // [rsp+68h] [rbp-10h]\n\n v14 = __readfsqword(0x28u);\n memset(v12, 0, sizeof(v12));\n v13 = 0;\n if ( a3 <= 0 )\n {\n return 0;\n }\n else\n {\n v6 = 0;\n v7 = &a2[a3];\n do\n {\n for ( i = 0LL; *a2 > (int)i; ++i )\n {\n v9 = *(_DWORD *)(a1 + 4 * i);\n if ( !v12[v9] )\n {\n v12[*(int *)(a1 + 4 * i)] = 1;\n v10 = (int)v6++;\n *(_DWORD *)(a4 + 4 * v10) = v9;\n }\n }\n ++a2;\n a1 += 400LL;\n }\n while ( a2 != v7 );\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_14D0(long long a1, uint32_t *a2, int a3, long long a4) {\n unsigned int v6;\n uint32_t *v7;\n long long i;\n int v9;\n long long v10;\n uint8_t v12[96];\n int v13;\n unsigned long long v14;\n v14 = __readfsqword(40u);\n memset(v12, 0, sizeof(v12));\n v13 = 0;\n if (a3 <= 0) {\n return 0;\n } else {\n v6 = 0;\n v7 = &a2[a3];\n do {\n for (i = 0LL; *a2 > (int)i; ++i) {\n v9 = *(uint32_t *)(a1 + 4 * i);\n if (!v12[v9]) {\n v12[*(int *)(a1 + 4 * i)] = 1;\n v10 = (int)v6++;\n *(uint32_t *)(a4 + 4 * v10) = v9;\n }\n }\n ++a2;\n a1 += 400LL;\n } while (a2 != v7);\n }\n return v6;\n}", + "ida_pseudo_norm": "long long func0(long long a1, uint32_t *a2, int a3, long long a4) {\n unsigned int v6;\n uint32_t *v7;\n long long i;\n int v9;\n long long v10;\n uint8_t v12[96];\n int v13;\n unsigned long long v14;\n v14 = __readfsqword(40u);\n memset(v12, 0, sizeof(v12));\n v13 = 0;\n if (a3 <= 0) {\n return 0;\n } else {\n v6 = 0;\n v7 = &a2[a3];\n do {\n for (i = 0LL; *a2 > (int)i; ++i) {\n v9 = *(uint32_t *)(a1 + 4 * i);\n if (!v12[v9]) {\n v12[*(int *)(a1 + 4 * i)] = 1;\n v10 = (int)v6++;\n *(uint32_t *)(a4 + 4 * v10) = v9;\n }\n }\n ++a2;\n a1 += 400LL;\n } while (a2 != v7);\n }\n return v6;\n}" + }, + { + "index": 140, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n#define MAX_SIZE 100\n\n\n\n", + "func": "int func0(int test_list[][MAX_SIZE], int sizes[], int no_of_lists, int res[]) {\n int res_index = 0;\n bool found[MAX_SIZE] = {false};\n for (int i = 0; i < no_of_lists; ++i) {\n for (int j = 0; j < sizes[i]; ++j) {\n int elem = test_list[i][j];\n if (!found[elem]) {\n found[elem] = true;\n res[res_index++] = elem;\n }\n }\n }\n return res_index;\n}", + "test": "int main() {\n\n int test_list1[][MAX_SIZE] = {{3, 4, 5}, {4, 5, 7}, {1, 4}};\n\n int sizes1[] = {3, 3, 2};\n\n int result1[MAX_SIZE];\n\n int len1 = func0(test_list1, sizes1, 3, result1);\n\n int expected1[] = {3, 4, 5, 7, 1};\n\n assert(len1 == 5);\n\n for (int i = 0; i < len1; ++i) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n\n\n int test_list2[][MAX_SIZE] = {{1, 2, 3}, {4, 2, 3}, {7, 8}};\n\n int sizes2[] = {3, 3, 2};\n\n int result2[MAX_SIZE];\n\n int len2 = func0(test_list2, sizes2, 3, result2);\n\n int expected2[] = {1, 2, 3, 4, 7, 8};\n\n assert(len2 == 6);\n\n for (int i = 0; i < len2; ++i) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n\n\n int test_list3[][MAX_SIZE] = {{7, 8, 9}, {10, 11, 12}, {10, 11}};\n\n int sizes3[] = {3, 3, 2};\n\n int result3[MAX_SIZE];\n\n int len3 = func0(test_list3, sizes3, 3, result3);\n\n int expected3[] = {7, 8, 9, 10, 11, 12};\n\n assert(len3 == 6);\n\n for (int i = 0; i < len3; ++i) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%r9\nmov %rcx,%r11\nmov $0xc,%ecx\nsub $0x70,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x68(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nrep stos %rax,%es:(%rdi)\nmovl $0x0,(%rdi)\ntest %edx,%edx\njle 161f \nlea -0x1(%rdx),%eax\nmov %rsi,%r10\nxor %r8d,%r8d\nlea 0x4(%rsi,%rax,4),%rbx\nnopw %cs:0x0(%rax,%rax,1)\nmov (%r10),%edi\nmovslq %r8d,%rsi\nxor %eax,%eax\ntest %edi,%edi\njle 15f6 \nnopl 0x0(%rax)\nmovslq (%r9,%rax,4),%rcx\ncmpb $0x0,(%rsp,%rcx,1)\njne 15ee \nmov %ecx,(%r11,%rsi,4)\nmov (%r10),%edi\nadd $0x1,%rax\nadd $0x1,%r8d\nmovb $0x1,(%rsp,%rcx,1)\ncmp %eax,%edi\njle 15f6 \nmovslq (%r9,%rax,4),%rcx\nmovslq %r8d,%rsi\ncmpb $0x0,(%rsp,%rcx,1)\nje 15ca \nadd $0x1,%rax\ncmp %eax,%edi\njg 15c0 \nadd $0x4,%r10\nadd $0x190,%r9\ncmp %rbx,%r10\njne 15b0 \nmov 0x68(%rsp),%rax\nxor %fs:0x28,%rax\njne 1624 \nadd $0x70,%rsp\nmov %r8d,%eax\npop %rbx\nretq\nxor %r8d,%r8d\njmp 1606 \ncallq 1060 <__stack_chk_fail@plt>\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 78h\nmov r9, rdi\nmov r10, rcx\nmov ecx, 0Ch\nmov rax, fs:28h\nmov [rsp+78h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\nmov dword ptr [rdi], 0\ntest edx, edx\njle loc_159B\nmovsxd rdx, edx\nlea r11, [rsi+rdx*4]\nxchg ax, ax\nloc_1520:\nmov r8d, [rsi]\nxor edx, edx\ntest r8d, r8d\njle short loc_1558\nnop word ptr [rax+rax+00h]\nloc_1530:\nmovsxd rdi, dword ptr [r9+rdx*4]\ncmp [rsp+rdi+78h+var_78], 0\nmov rcx, rdi\njnz short loc_1580\nmov [rsp+rdi+78h+var_78], 1\nlea edi, [rax+1]\ncdqe\nadd rdx, 1\nmov [r10+rax*4], ecx\nmov r8d, [rsi]\nmov eax, edi\ncmp r8d, edx\njg short loc_1530\nloc_1558:\nadd rsi, 4\nadd r9, 190h\ncmp rsi, r11\njnz short loc_1520\nloc_1568:\nmov rdx, [rsp+78h+var_10]\nsub rdx, fs:28h\njnz short loc_159F\nadd rsp, 78h\nretn\nloc_1580:\nadd rdx, 1\ncmp r8d, edx\njg short loc_1530\nadd rsi, 4\nadd r9, 190h\ncmp rsi, r11\njnz short loc_1520\njmp short loc_1568\nloc_159B:\nxor eax, eax\njmp short loc_1568\nloc_159F:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int *a2, int a3, __int64 a4)\n{\n __int64 result; // rax\n int *v7; // r11\n int v8; // r8d\n __int64 v9; // rdx\n int v10; // ecx\n _BYTE v11[96]; // [rsp+0h] [rbp-78h] BYREF\n int v12; // [rsp+60h] [rbp-18h]\n unsigned __int64 v13; // [rsp+68h] [rbp-10h]\n\n v13 = __readfsqword(0x28u);\n result = 0LL;\n memset(v11, 0, sizeof(v11));\n v12 = 0;\n if ( a3 <= 0 )\n return 0LL;\n v7 = &a2[a3];\n do\n {\n while ( 1 )\n {\n v8 = *a2;\n v9 = 0LL;\n if ( *a2 > 0 )\n break;\nLABEL_6:\n ++a2;\n a1 += 400LL;\n if ( a2 == v7 )\n return result;\n }\n do\n {\n while ( 1 )\n {\n v10 = *(_DWORD *)(a1 + 4 * v9);\n if ( v11[v10] )\n break;\n v11[*(int *)(a1 + 4 * v9++)] = 1;\n *(_DWORD *)(a4 + 4LL * (int)result) = v10;\n v8 = *a2;\n result = (unsigned int)(result + 1);\n if ( *a2 <= (int)v9 )\n goto LABEL_6;\n }\n ++v9;\n }\n while ( v8 > (int)v9 );\n ++a2;\n a1 += 400LL;\n }\n while ( a2 != v7 );\n return result;\n}", + "ida_strip_asm": "sub_14E0:\nendbr64\nsub rsp, 78h\nmov r9, rdi\nmov r10, rcx\nmov ecx, 0Ch\nmov rax, fs:28h\nmov [rsp+78h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\nmov dword ptr [rdi], 0\ntest edx, edx\njle loc_159B\nmovsxd rdx, edx\nlea r11, [rsi+rdx*4]\nxchg ax, ax\nloc_1520:\nmov r8d, [rsi]\nxor edx, edx\ntest r8d, r8d\njle short loc_1558\nnop word ptr [rax+rax+00h]\nloc_1530:\nmovsxd rdi, dword ptr [r9+rdx*4]\ncmp [rsp+rdi+78h+var_78], 0\nmov rcx, rdi\njnz short loc_1580\nmov [rsp+rdi+78h+var_78], 1\nlea edi, [rax+1]\ncdqe\nadd rdx, 1\nmov [r10+rax*4], ecx\nmov r8d, [rsi]\nmov eax, edi\ncmp r8d, edx\njg short loc_1530\nloc_1558:\nadd rsi, 4\nadd r9, 190h\ncmp rsi, r11\njnz short loc_1520\nloc_1568:\nmov rdx, [rsp+78h+var_10]\nsub rdx, fs:28h\njnz short loc_159F\nadd rsp, 78h\nretn\nloc_1580:\nadd rdx, 1\ncmp r8d, edx\njg short loc_1530\nadd rsi, 4\nadd r9, 190h\ncmp rsi, r11\njnz short loc_1520\njmp short loc_1568\nloc_159B:\nxor eax, eax\njmp short loc_1568\nloc_159F:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_14E0(__int64 a1, int *a2, int a3, __int64 a4)\n{\n __int64 result; // rax\n int *v7; // r11\n int v8; // r8d\n __int64 v9; // rdx\n int v10; // ecx\n _BYTE v11[96]; // [rsp+0h] [rbp-78h] BYREF\n int v12; // [rsp+60h] [rbp-18h]\n unsigned __int64 v13; // [rsp+68h] [rbp-10h]\n\n v13 = __readfsqword(0x28u);\n result = 0LL;\n memset(v11, 0, sizeof(v11));\n v12 = 0;\n if ( a3 <= 0 )\n return 0LL;\n v7 = &a2[a3];\n do\n {\n while ( 1 )\n {\n v8 = *a2;\n v9 = 0LL;\n if ( *a2 > 0 )\n break;\nLABEL_6:\n ++a2;\n a1 += 400LL;\n if ( a2 == v7 )\n return result;\n }\n do\n {\n while ( 1 )\n {\n v10 = *(_DWORD *)(a1 + 4 * v9);\n if ( v11[v10] )\n break;\n v11[*(int *)(a1 + 4 * v9++)] = 1;\n *(_DWORD *)(a4 + 4LL * (int)result) = v10;\n v8 = *a2;\n result = (unsigned int)(result + 1);\n if ( *a2 <= (int)v9 )\n goto LABEL_6;\n }\n ++v9;\n }\n while ( v8 > (int)v9 );\n ++a2;\n a1 += 400LL;\n }\n while ( a2 != v7 );\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_14E0(long long a1, int *a2, int a3, long long a4) {\n long long result;\n int *v7;\n int v8;\n long long v9;\n int v10;\n uint8_t v11[96];\n int v12;\n unsigned long long v13;\n v13 = __readfsqword(40u);\n result = 0LL;\n memset(v11, 0, sizeof(v11));\n v12 = 0;\n if (a3 <= 0) return 0LL;\n v7 = &a2[a3];\n do {\n while (1) {\n v8 = *a2;\n v9 = 0LL;\n if (*a2 > 0) break;\n LABEL_6:\n ++a2;\n a1 += 400LL;\n if (a2 == v7) return result;\n }\n do {\n while (1) {\n v10 = *(uint32_t *)(a1 + 4 * v9);\n if (v11[v10]) break;\n v11[*(int *)(a1 + 4 * v9++)] = 1;\n *(uint32_t *)(a4 + 4LL * (int)result) = v10;\n v8 = *a2;\n result = (unsigned int)(result + 1);\n if (*a2 <= (int)v9) goto LABEL_6;\n }\n ++v9;\n } while (v8 > (int)v9);\n ++a2;\n a1 += 400LL;\n } while (a2 != v7);\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int *a2, int a3, long long a4) {\n long long result;\n int *v7;\n int v8;\n long long v9;\n int v10;\n uint8_t v11[96];\n int v12;\n unsigned long long v13;\n v13 = __readfsqword(40u);\n result = 0LL;\n memset(v11, 0, sizeof(v11));\n v12 = 0;\n if (a3 <= 0) return 0LL;\n v7 = &a2[a3];\n do {\n while (1) {\n v8 = *a2;\n v9 = 0LL;\n if (*a2 > 0) break;\n LABEL_6:\n ++a2;\n a1 += 400LL;\n if (a2 == v7) return result;\n }\n do {\n while (1) {\n v10 = *(uint32_t *)(a1 + 4 * v9);\n if (v11[v10]) break;\n v11[*(int *)(a1 + 4 * v9++)] = 1;\n *(uint32_t *)(a4 + 4LL * (int)result) = v10;\n v8 = *a2;\n result = (unsigned int)(result + 1);\n if (*a2 <= (int)v9) goto LABEL_6;\n }\n ++v9;\n } while (v8 > (int)v9);\n ++a2;\n a1 += 400LL;\n } while (a2 != v7);\n return result;\n}" + }, + { + "index": 141, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nvoid reverse(int arr[], int start, int end) {\n\n while (start < end) {\n\n int temp = arr[start];\n\n arr[start] = arr[end];\n\n arr[end] = temp;\n\n start++;\n\n end--;\n\n }\n\n}\n\n\n\nint find_max_index(int arr[], int n) {\n\n int max_idx = 0;\n\n for (int i = 1; i < n; i++) {\n\n if (arr[i] > arr[max_idx]) {\n\n max_idx = i;\n\n }\n\n }\n\n return max_idx;\n\n}\n\n\n\n", + "func": "void func0(int arr[], int n) {\n for (int curr_size = n; curr_size > 1; --curr_size) {\n int max_idx = find_max_index(arr, curr_size);\n if (max_idx != curr_size - 1) {\n reverse(arr, 0, max_idx);\n reverse(arr, 0, curr_size - 1);\n }\n }\n}", + "test": "int main() {\n\n int arr1[] = {15, 79, 25, 38, 69};\n\n int arr2[] = {98, 12, 54, 36, 85};\n\n int arr3[] = {41, 42, 32, 12, 23};\n\n\n\n func0(arr1, 5);\n\n func0(arr2, 5);\n\n func0(arr3, 5);\n\n\n\n assert(arr1[0] == 15 && arr1[1] == 25 && arr1[2] == 38 && arr1[3] == 69 && arr1[4] == 79);\n\n assert(arr2[0] == 12 && arr2[1] == 36 && arr2[2] == 54 && arr2[3] == 85 && arr2[4] == 98);\n\n assert(arr3[0] == 12 && arr3[1] == 23 && arr3[2] == 32 && arr3[3] == 41 && arr3[4] == 42);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov -0x1c(%rbp),%eax\nmov %eax,-0x8(%rbp)\njmp 12bf \nmov -0x8(%rbp),%edx\nmov -0x18(%rbp),%rax\nmov %edx,%esi\nmov %rax,%rdi\ncallq 11f0 \nmov %eax,-0x4(%rbp)\nmov -0x8(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x4(%rbp)\nje 12bb \nmov -0x4(%rbp),%edx\nmov -0x18(%rbp),%rax\nmov $0x0,%esi\nmov %rax,%rdi\ncallq 1169 \nmov -0x8(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x18(%rbp),%rax\nmov $0x0,%esi\nmov %rax,%rdi\ncallq 1169 \nsubl $0x1,-0x8(%rbp)\ncmpl $0x1,-0x8(%rbp)\njg 1271 \nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov eax, [rbp+var_1C]\nmov [rbp+var_8], eax\njmp short loc_12BF\nloc_1271:\nmov edx, [rbp+var_8]\nmov rax, [rbp+var_18]\nmov esi, edx\nmov rdi, rax\ncall find_max_index\nmov [rbp+var_4], eax\nmov eax, [rbp+var_8]\nsub eax, 1\ncmp [rbp+var_4], eax\njz short loc_12BB\nmov edx, [rbp+var_4]\nmov rax, [rbp+var_18]\nmov esi, 0\nmov rdi, rax\ncall reverse\nmov eax, [rbp+var_8]\nlea edx, [rax-1]\nmov rax, [rbp+var_18]\nmov esi, 0\nmov rdi, rax\ncall reverse\nloc_12BB:\nsub [rbp+var_8], 1\nloc_12BF:\ncmp [rbp+var_8], 1\njg short loc_1271\nnop\nnop\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, unsigned int a2)\n{\n __int64 result; // rax\n int i; // [rsp+18h] [rbp-8h]\n unsigned int max_index; // [rsp+1Ch] [rbp-4h]\n\n result = a2;\n for ( i = a2; i > 1; --i )\n {\n max_index = find_max_index(a1, (unsigned int)i);\n result = (unsigned int)(i - 1);\n if ( max_index != (_DWORD)result )\n {\n reverse(a1, 0LL, max_index);\n result = reverse(a1, 0LL, (unsigned int)(i - 1));\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1256:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov eax, [rbp+var_1C]\nmov [rbp+var_8], eax\njmp short loc_12BF\nloc_1271:\nmov edx, [rbp+var_8]\nmov rax, [rbp+var_18]\nmov esi, edx\nmov rdi, rax\ncall sub_11F0\nmov [rbp+var_4], eax\nmov eax, [rbp+var_8]\nsub eax, 1\ncmp [rbp+var_4], eax\njz short loc_12BB\nmov edx, [rbp+var_4]\nmov rax, [rbp+var_18]\nmov esi, 0\nmov rdi, rax\ncall sub_1169\nmov eax, [rbp+var_8]\nlea edx, [rax-1]\nmov rax, [rbp+var_18]\nmov esi, 0\nmov rdi, rax\ncall sub_1169\nloc_12BB:\nsub [rbp+var_8], 1\nloc_12BF:\ncmp [rbp+var_8], 1\njg short loc_1271\nnop\nnop\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1256(__int64 a1, unsigned int a2)\n{\n __int64 result; // rax\n int i; // [rsp+18h] [rbp-8h]\n unsigned int v4; // [rsp+1Ch] [rbp-4h]\n\n result = a2;\n for ( i = a2; i > 1; --i )\n {\n v4 = sub_11F0(a1, (unsigned int)i);\n result = (unsigned int)(i - 1);\n if ( v4 != (_DWORD)result )\n {\n sub_1169(a1, 0LL, v4);\n result = sub_1169(a1, 0LL, (unsigned int)(i - 1));\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1256(long long a1, unsigned int a2) {\n long long result;\n int i;\n unsigned int v4;\n result = a2;\n for (i = a2; i > 1; --i) {\n v4 = sub_11F0(a1, (unsigned int)i);\n result = (unsigned int)(i - 1);\n if (v4 != (uint32_t)result) {\n sub_1169(a1, 0LL, v4);\n result = sub_1169(a1, 0LL, (unsigned int)(i - 1));\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, unsigned int a2) {\n long long result;\n int i;\n unsigned int max_index;\n result = a2;\n for (i = a2; i > 1; --i) {\n max_index = find_max_index(a1, (unsigned int)i);\n result = (unsigned int)(i - 1);\n if (max_index != (uint32_t)result) {\n reverse(a1, 0LL, max_index);\n result = reverse(a1, 0LL, (unsigned int)(i - 1));\n }\n }\n return result;\n}" + }, + { + "index": 141, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nvoid reverse(int arr[], int start, int end) {\n\n while (start < end) {\n\n int temp = arr[start];\n\n arr[start] = arr[end];\n\n arr[end] = temp;\n\n start++;\n\n end--;\n\n }\n\n}\n\n\n\nint find_max_index(int arr[], int n) {\n\n int max_idx = 0;\n\n for (int i = 1; i < n; i++) {\n\n if (arr[i] > arr[max_idx]) {\n\n max_idx = i;\n\n }\n\n }\n\n return max_idx;\n\n}\n\n\n\n", + "func": "void func0(int arr[], int n) {\n for (int curr_size = n; curr_size > 1; --curr_size) {\n int max_idx = find_max_index(arr, curr_size);\n if (max_idx != curr_size - 1) {\n reverse(arr, 0, max_idx);\n reverse(arr, 0, curr_size - 1);\n }\n }\n}", + "test": "int main() {\n\n int arr1[] = {15, 79, 25, 38, 69};\n\n int arr2[] = {98, 12, 54, 36, 85};\n\n int arr3[] = {41, 42, 32, 12, 23};\n\n\n\n func0(arr1, 5);\n\n func0(arr2, 5);\n\n func0(arr3, 5);\n\n\n\n assert(arr1[0] == 15 && arr1[1] == 25 && arr1[2] == 38 && arr1[3] == 69 && arr1[4] == 79);\n\n assert(arr2[0] == 12 && arr2[1] == 36 && arr2[2] == 54 && arr2[3] == 85 && arr2[4] == 98);\n\n assert(arr3[0] == 12 && arr3[1] == 23 && arr3[2] == 32 && arr3[3] == 41 && arr3[4] == 42);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nmov %rdi,%rbp\nmov %esi,%ebx\ncmp $0x1,%esi\njg 11ff \npop %rbx\npop %rbp\nretq\nmov %eax,%edx\nmov $0x0,%esi\nmov %rbp,%rdi\ncallq 1169 \nmov %ebx,%edx\nmov $0x0,%esi\nmov %rbp,%rdi\ncallq 1169 \ncmp $0x1,%ebx\nje 11d9 \nmov %ebx,%esi\nmov %rbp,%rdi\ncallq 1190 \nsub $0x1,%ebx\ncmp %eax,%ebx\nje 11fa \njmp 11dc \n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nmov rbp, rdi\nmov ebx, esi\ncmp esi, 1\njg short loc_11DC\nloc_11D4:\npop rbx\npop rbp\nretn\nloc_11D7:\ncmp ebx, 1\njz short loc_11D4\nloc_11DC:\nmov esi, ebx\nmov rdi, rbp\ncall find_max_index\nsub ebx, 1\ncmp ebx, eax\njz short loc_11D7\nmov edx, eax\nmov esi, 0\nmov rdi, rbp\ncall reverse\nmov edx, ebx\nmov esi, 0\nmov rdi, rbp\ncall reverse\njmp short loc_11D7", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v2; // ebx\n unsigned int max_index; // eax\n\n v2 = a2;\n if ( a2 > 1 )\n {\n do\n {\n max_index = find_max_index(a1, v2--);\n if ( v2 != max_index )\n {\n reverse(a1, 0LL, max_index);\n reverse(a1, 0LL, v2);\n }\n }\n while ( v2 != 1 );\n }\n}", + "ida_strip_asm": "sub_11C4:\nendbr64\npush rbp\npush rbx\nmov rbp, rdi\nmov ebx, esi\ncmp esi, 1\njg short loc_11DC\nloc_11D4:\npop rbx\npop rbp\nretn\nloc_11D7:\ncmp ebx, 1\njz short loc_11D4\nloc_11DC:\nmov esi, ebx\nmov rdi, rbp\ncall sub_1190\nsub ebx, 1\ncmp ebx, eax\njz short loc_11D7\nmov edx, eax\nmov esi, 0\nmov rdi, rbp\ncall sub_1169\nmov edx, ebx\nmov esi, 0\nmov rdi, rbp\ncall sub_1169\njmp short loc_11D7", + "ida_strip_pseudo": "void __fastcall sub_11C4(__int64 a1, int a2)\n{\n unsigned int v2; // ebx\n unsigned int v3; // eax\n\n v2 = a2;\n if ( a2 > 1 )\n {\n do\n {\n v3 = sub_1190(a1, v2--);\n if ( v2 != v3 )\n {\n sub_1169(a1, 0LL, v3);\n sub_1169(a1, 0LL, v2);\n }\n }\n while ( v2 != 1 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_11C4(long long a1, int a2) {\n unsigned int v2;\n unsigned int v3;\n v2 = a2;\n if (a2 > 1) {\n do {\n v3 = sub_1190(a1, v2--);\n if (v2 != v3) {\n sub_1169(a1, 0LL, v3);\n sub_1169(a1, 0LL, v2);\n }\n } while (v2 != 1);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2) {\n unsigned int v2;\n unsigned int max_index;\n v2 = a2;\n if (a2 > 1) {\n do {\n max_index = find_max_index(a1, v2--);\n if (v2 != max_index) {\n reverse(a1, 0LL, max_index);\n reverse(a1, 0LL, v2);\n }\n } while (v2 != 1);\n }\n}" + }, + { + "index": 141, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nvoid reverse(int arr[], int start, int end) {\n\n while (start < end) {\n\n int temp = arr[start];\n\n arr[start] = arr[end];\n\n arr[end] = temp;\n\n start++;\n\n end--;\n\n }\n\n}\n\n\n\nint find_max_index(int arr[], int n) {\n\n int max_idx = 0;\n\n for (int i = 1; i < n; i++) {\n\n if (arr[i] > arr[max_idx]) {\n\n max_idx = i;\n\n }\n\n }\n\n return max_idx;\n\n}\n\n\n\n", + "func": "void func0(int arr[], int n) {\n for (int curr_size = n; curr_size > 1; --curr_size) {\n int max_idx = find_max_index(arr, curr_size);\n if (max_idx != curr_size - 1) {\n reverse(arr, 0, max_idx);\n reverse(arr, 0, curr_size - 1);\n }\n }\n}", + "test": "int main() {\n\n int arr1[] = {15, 79, 25, 38, 69};\n\n int arr2[] = {98, 12, 54, 36, 85};\n\n int arr3[] = {41, 42, 32, 12, 23};\n\n\n\n func0(arr1, 5);\n\n func0(arr2, 5);\n\n func0(arr3, 5);\n\n\n\n assert(arr1[0] == 15 && arr1[1] == 25 && arr1[2] == 38 && arr1[3] == 69 && arr1[4] == 79);\n\n assert(arr2[0] == 12 && arr2[1] == 36 && arr2[2] == 54 && arr2[3] == 85 && arr2[4] == 98);\n\n assert(arr3[0] == 12 && arr3[1] == 23 && arr3[2] == 32 && arr3[3] == 41 && arr3[4] == 42);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nnopl 0x0(%rax)\ncmp $0x1,%esi\njle 141f \nmov $0x1,%edx\nxor %eax,%eax\nnopl 0x0(%rax)\nmovslq %eax,%rcx\nmov (%rdi,%rcx,4),%ecx\ncmp %ecx,(%rdi,%rdx,4)\ncmovg %edx,%eax\nadd $0x1,%rdx\ncmp %edx,%esi\njg 13b8 \nsub $0x1,%esi\ncmp %eax,%esi\nje 13a8 \ntest %eax,%eax\njle 13fa \ncltq\nxor %edx,%edx\nnopl 0x0(%rax,%rax,1)\nmov (%rdi,%rdx,4),%ecx\nmov (%rdi,%rax,4),%r8d\nmov %r8d,(%rdi,%rdx,4)\nadd $0x1,%rdx\nmov %ecx,(%rdi,%rax,4)\nsub $0x1,%rax\ncmp %edx,%eax\njg 13e0 \nmovslq %esi,%rdx\nxor %eax,%eax\nmov (%rdi,%rax,4),%ecx\nmov (%rdi,%rdx,4),%r8d\nmov %r8d,(%rdi,%rax,4)\nadd $0x1,%rax\nmov %ecx,(%rdi,%rdx,4)\nsub $0x1,%rdx\ncmp %eax,%edx\njg 1400 \ncmp $0x1,%esi\njg 13ad \nretq\n", + "ida_asm": "func0:\nendbr64\nmov rax, rdi\ncmp esi, 1\njle locret_13F0\nloc_1370:\nmov r8d, esi\nmov edx, 1\nxor ecx, ecx\nnop word ptr [rax+rax+00h]\nloc_1380:\nmovsxd rdi, ecx\nmov r9d, [rax+rdx*4]\ncmp [rax+rdi*4], r9d\ncmovl ecx, edx\nadd rdx, 1\ncmp rdx, r8\njnz short loc_1380\nsub esi, 1\ncmp esi, ecx\njz short loc_13EA\nmovsxd rdi, ecx\nxor edx, edx\ntest ecx, ecx\njle short loc_13CA\nnop word ptr [rax+rax+00000000h]\nloc_13B0:\nmov ecx, [rax+rdx*4]\nmov r8d, [rax+rdi*4]\nmov [rax+rdx*4], r8d\nadd rdx, 1\nmov [rax+rdi*4], ecx\nsub rdi, 1\ncmp edi, edx\njg short loc_13B0\nloc_13CA:\nmovsxd rcx, esi\nxor edx, edx\nnop\nloc_13D0:\nmov edi, [rax+rdx*4]\nmov r8d, [rax+rcx*4]\nmov [rax+rdx*4], r8d\nadd rdx, 1\nmov [rax+rcx*4], edi\nsub rcx, 1\ncmp edx, ecx\njl short loc_13D0\nloc_13EA:\ncmp esi, 1\njnz short loc_1370\nretn\nlocret_13F0:\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 result; // rax\n __int64 v3; // rdx\n int v4; // ecx\n __int64 v5; // rdi\n __int64 v6; // rdx\n int v7; // ecx\n __int64 v8; // rcx\n __int64 v9; // rdx\n int v10; // edi\n\n result = a1;\n if ( a2 > 1 )\n {\n do\n {\n v3 = 1LL;\n v4 = 0;\n do\n {\n if ( *(_DWORD *)(result + 4LL * v4) < *(_DWORD *)(result + 4 * v3) )\n v4 = v3;\n ++v3;\n }\n while ( v3 != a2 );\n if ( --a2 != v4 )\n {\n v5 = v4;\n v6 = 0LL;\n if ( v4 > 0 )\n {\n do\n {\n v7 = *(_DWORD *)(result + 4 * v6);\n *(_DWORD *)(result + 4 * v6++) = *(_DWORD *)(result + 4 * v5);\n *(_DWORD *)(result + 4 * v5--) = v7;\n }\n while ( (int)v5 > (int)v6 );\n }\n v8 = a2;\n v9 = 0LL;\n do\n {\n v10 = *(_DWORD *)(result + 4 * v9);\n *(_DWORD *)(result + 4 * v9++) = *(_DWORD *)(result + 4 * v8);\n *(_DWORD *)(result + 4 * v8--) = v10;\n }\n while ( (int)v9 < (int)v8 );\n }\n }\n while ( a2 != 1 );\n }\n return result;\n}", + "ida_strip_asm": "sub_1360:\nendbr64\nmov rax, rdi\ncmp esi, 1\njle locret_13F0\nloc_1370:\nmov r8d, esi\nmov edx, 1\nxor ecx, ecx\nnop word ptr [rax+rax+00h]\nloc_1380:\nmovsxd rdi, ecx\nmov r9d, [rax+rdx*4]\ncmp [rax+rdi*4], r9d\ncmovl ecx, edx\nadd rdx, 1\ncmp rdx, r8\njnz short loc_1380\nsub esi, 1\ncmp esi, ecx\njz short loc_13EA\nmovsxd rdi, ecx\nxor edx, edx\ntest ecx, ecx\njle short loc_13CA\nnop word ptr [rax+rax+00000000h]\nloc_13B0:\nmov ecx, [rax+rdx*4]\nmov r8d, [rax+rdi*4]\nmov [rax+rdx*4], r8d\nadd rdx, 1\nmov [rax+rdi*4], ecx\nsub rdi, 1\ncmp edi, edx\njg short loc_13B0\nloc_13CA:\nmovsxd rcx, esi\nxor edx, edx\nnop\nloc_13D0:\nmov edi, [rax+rdx*4]\nmov r8d, [rax+rcx*4]\nmov [rax+rdx*4], r8d\nadd rdx, 1\nmov [rax+rcx*4], edi\nsub rcx, 1\ncmp edx, ecx\njl short loc_13D0\nloc_13EA:\ncmp esi, 1\njnz short loc_1370\nretn\nlocret_13F0:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1360(__int64 a1, int a2)\n{\n __int64 result; // rax\n __int64 v3; // rdx\n int v4; // ecx\n __int64 v5; // rdi\n __int64 v6; // rdx\n int v7; // ecx\n __int64 v8; // rcx\n __int64 v9; // rdx\n int v10; // edi\n\n result = a1;\n if ( a2 > 1 )\n {\n do\n {\n v3 = 1LL;\n v4 = 0;\n do\n {\n if ( *(_DWORD *)(result + 4LL * v4) < *(_DWORD *)(result + 4 * v3) )\n v4 = v3;\n ++v3;\n }\n while ( v3 != a2 );\n if ( --a2 != v4 )\n {\n v5 = v4;\n v6 = 0LL;\n if ( v4 > 0 )\n {\n do\n {\n v7 = *(_DWORD *)(result + 4 * v6);\n *(_DWORD *)(result + 4 * v6++) = *(_DWORD *)(result + 4 * v5);\n *(_DWORD *)(result + 4 * v5--) = v7;\n }\n while ( (int)v5 > (int)v6 );\n }\n v8 = a2;\n v9 = 0LL;\n do\n {\n v10 = *(_DWORD *)(result + 4 * v9);\n *(_DWORD *)(result + 4 * v9++) = *(_DWORD *)(result + 4 * v8);\n *(_DWORD *)(result + 4 * v8--) = v10;\n }\n while ( (int)v9 < (int)v8 );\n }\n }\n while ( a2 != 1 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1360(long long a1, int a2) {\n long long result;\n long long v3;\n int v4;\n long long v5;\n long long v6;\n int v7;\n long long v8;\n long long v9;\n int v10;\n result = a1;\n if (a2 > 1) {\n do {\n v3 = 1LL;\n v4 = 0;\n do {\n if (*(uint32_t *)(result + 4LL * v4) < *(uint32_t *)(result + 4 * v3))\n v4 = v3;\n ++v3;\n } while (v3 != a2);\n if (--a2 != v4) {\n v5 = v4;\n v6 = 0LL;\n if (v4 > 0) {\n do {\n v7 = *(uint32_t *)(result + 4 * v6);\n *(uint32_t *)(result + 4 * v6++) = *(uint32_t *)(result + 4 * v5);\n *(uint32_t *)(result + 4 * v5--) = v7;\n } while ((int)v5 > (int)v6);\n }\n v8 = a2;\n v9 = 0LL;\n do {\n v10 = *(uint32_t *)(result + 4 * v9);\n *(uint32_t *)(result + 4 * v9++) = *(uint32_t *)(result + 4 * v8);\n *(uint32_t *)(result + 4 * v8--) = v10;\n } while ((int)v9 < (int)v8);\n }\n } while (a2 != 1);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long result;\n long long v3;\n int v4;\n long long v5;\n long long v6;\n int v7;\n long long v8;\n long long v9;\n int v10;\n result = a1;\n if (a2 > 1) {\n do {\n v3 = 1LL;\n v4 = 0;\n do {\n if (*(uint32_t *)(result + 4LL * v4) < *(uint32_t *)(result + 4 * v3))\n v4 = v3;\n ++v3;\n } while (v3 != a2);\n if (--a2 != v4) {\n v5 = v4;\n v6 = 0LL;\n if (v4 > 0) {\n do {\n v7 = *(uint32_t *)(result + 4 * v6);\n *(uint32_t *)(result + 4 * v6++) = *(uint32_t *)(result + 4 * v5);\n *(uint32_t *)(result + 4 * v5--) = v7;\n } while ((int)v5 > (int)v6);\n }\n v8 = a2;\n v9 = 0LL;\n do {\n v10 = *(uint32_t *)(result + 4 * v9);\n *(uint32_t *)(result + 4 * v9++) = *(uint32_t *)(result + 4 * v8);\n *(uint32_t *)(result + 4 * v8--) = v10;\n } while ((int)v9 < (int)v8);\n }\n } while (a2 != 1);\n }\n return result;\n}" + }, + { + "index": 141, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nvoid reverse(int arr[], int start, int end) {\n\n while (start < end) {\n\n int temp = arr[start];\n\n arr[start] = arr[end];\n\n arr[end] = temp;\n\n start++;\n\n end--;\n\n }\n\n}\n\n\n\nint find_max_index(int arr[], int n) {\n\n int max_idx = 0;\n\n for (int i = 1; i < n; i++) {\n\n if (arr[i] > arr[max_idx]) {\n\n max_idx = i;\n\n }\n\n }\n\n return max_idx;\n\n}\n\n\n\n", + "func": "void func0(int arr[], int n) {\n for (int curr_size = n; curr_size > 1; --curr_size) {\n int max_idx = find_max_index(arr, curr_size);\n if (max_idx != curr_size - 1) {\n reverse(arr, 0, max_idx);\n reverse(arr, 0, curr_size - 1);\n }\n }\n}", + "test": "int main() {\n\n int arr1[] = {15, 79, 25, 38, 69};\n\n int arr2[] = {98, 12, 54, 36, 85};\n\n int arr3[] = {41, 42, 32, 12, 23};\n\n\n\n func0(arr1, 5);\n\n func0(arr2, 5);\n\n func0(arr3, 5);\n\n\n\n assert(arr1[0] == 15 && arr1[1] == 25 && arr1[2] == 38 && arr1[3] == 69 && arr1[4] == 79);\n\n assert(arr2[0] == 12 && arr2[1] == 36 && arr2[2] == 54 && arr2[3] == 85 && arr2[4] == 98);\n\n assert(arr3[0] == 12 && arr3[1] == 23 && arr3[2] == 32 && arr3[3] == 41 && arr3[4] == 42);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%esi\njle 1747 \npush %r14\nmov $0x4,%r10d\nxor %r9d,%r9d\nmov $0x1,%r11d\npush %r13\npush %r12\npush %rbp\npush %rbx\nnopl 0x0(%rax)\nmov (%rdi),%ecx\nmov $0x1,%eax\nxor %r8d,%r8d\nnopw 0x0(%rax,%rax,1)\nmov (%rdi,%rax,4),%edx\ncmp %ecx,%edx\njle 14d4 \nmov %edx,%ecx\nmov %eax,%r8d\nadd $0x1,%rax\ncmp %eax,%esi\njg 14c8 \nlea -0x1(%rsi),%ebx\ncmp %r8d,%ebx\njne 14f8 \nmov %r8d,%esi\ncmp $0x1,%esi\njg 14b8 \npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopl (%rax)\ntest %r8d,%r8d\njle 15ed \nlea -0x1(%r8),%ecx\nmovslq %r8d,%rax\nmov %ecx,%ebp\nlea 0x4(,%rax,4),%r12\nshr %ebp\nlea 0x1(%rbp),%edx\nmov %rdx,%rbp\nlea 0x0(,%rdx,4),%r13\nneg %rdx\nlea (%r12,%rdx,4),%rdx\ncmp %rdx,%r13\njg 171f \ncmp $0x5,%ecx\njbe 171f \nmov %ebp,%ecx\nmov %rdi,%rax\nlea -0x10(%rdi,%r12,1),%rdx\nshr $0x2,%ecx\nshl $0x4,%rcx\nadd %rdi,%rcx\nmovdqu (%rdx),%xmm3\nmovdqu (%rax),%xmm0\nadd $0x10,%rax\nsub $0x10,%rdx\npshufd $0x1b,%xmm3,%xmm1\npshufd $0x1b,%xmm0,%xmm0\nmovups %xmm1,-0x10(%rax)\nmovups %xmm0,0x10(%rdx)\ncmp %rax,%rcx\njne 1550 \nmov %ebp,%eax\nand $0xfffffffc,%eax\nsub %eax,%r8d\ncmp %eax,%ebp\nje 15ed \nmov %eax,%ecx\nmovslq %r8d,%rdx\nshl $0x2,%rcx\nlea (%rdi,%rdx,4),%rdx\nlea (%rdi,%rcx,1),%rbp\nmov (%rdx),%r13d\nmov 0x0(%rbp),%r12d\nmov %r13d,0x0(%rbp)\nlea 0x1(%rax),%ebp\nmov %r12d,(%rdx)\nlea -0x1(%r8),%edx\ncmp %ebp,%edx\njle 15ed \nmovslq %edx,%rdx\nlea 0x4(%rdi,%rcx,1),%r12\nadd $0x2,%eax\nsub $0x2,%r8d\nshl $0x2,%rdx\nmov (%r12),%r13d\nlea (%rdi,%rdx,1),%rbp\nmov 0x0(%rbp),%r14d\nmov %r14d,(%r12)\nmov %r13d,0x0(%rbp)\ncmp %r8d,%eax\njge 15ed \nlea 0x8(%rdi,%rcx,1),%rcx\nlea -0x4(%rdi,%rdx,1),%rax\nmov (%rcx),%r8d\nmov (%rax),%edx\nmov %edx,(%rcx)\nmov %r8d,(%rax)\nlea -0x2(%rsi),%edx\nmovslq %ebx,%rax\nshr %edx\ncmp $0x1,%esi\nlea 0x4(,%rax,4),%r8\nlea 0x1(%rdx),%ecx\nlea 0x0(,%rcx,4),%rbp\nmov %rcx,%rdx\ncmovle %r10,%rbp\nneg %rcx\ncmp $0x1,%esi\nlea 0x4(,%rcx,4),%rcx\ncmovle %r9,%rcx\nlea (%rcx,%rax,4),%rcx\ncmp %rcx,%rbp\njg 16fd \ncmp $0x7,%esi\njle 16fd \ncmp $0x1,%esi\nmov %edx,%esi\nlea -0x10(%rdi,%r8,1),%rdx\nmov %rdi,%rax\ncmovle %r11d,%esi\nmov %esi,%ecx\nshr $0x2,%ecx\nshl $0x4,%rcx\nadd %rdi,%rcx\nnopw 0x0(%rax,%rax,1)\nmovdqu (%rdx),%xmm2\nmovdqu (%rax),%xmm0\nadd $0x10,%rax\nsub $0x10,%rdx\npshufd $0x1b,%xmm2,%xmm1\npshufd $0x1b,%xmm0,%xmm0\nmovups %xmm1,-0x10(%rax)\nmovups %xmm0,0x10(%rdx)\ncmp %rax,%rcx\njne 1660 \nmov %esi,%eax\nmov %ebx,%edx\nand $0xfffffffc,%eax\nsub %eax,%edx\ncmp %eax,%esi\nje 16f6 \nmov %eax,%esi\nmovslq %edx,%rcx\nshl $0x2,%rsi\nlea (%rdi,%rcx,4),%rcx\nlea (%rdi,%rsi,1),%r8\nmov (%rcx),%r12d\nmov (%r8),%ebp\nmov %r12d,(%r8)\nlea 0x1(%rax),%r8d\nmov %ebp,(%rcx)\nlea -0x1(%rdx),%ecx\ncmp %r8d,%ecx\njle 16f6 \nmovslq %ecx,%rcx\nlea 0x4(%rdi,%rsi,1),%rbp\nsub $0x2,%edx\nadd $0x2,%eax\nshl $0x2,%rcx\nmov 0x0(%rbp),%r12d\nlea (%rdi,%rcx,1),%r8\nmov (%r8),%r13d\nmov %r13d,0x0(%rbp)\nmov %r12d,(%r8)\ncmp %eax,%edx\njle 16f6 \nlea 0x8(%rdi,%rsi,1),%rdx\nlea -0x4(%rdi,%rcx,1),%rax\nmov (%rdx),%esi\nmov (%rax),%ecx\nmov %ecx,(%rdx)\nmov %esi,(%rax)\nmov %ebx,%esi\njmpq 14e7 \nxor %edx,%edx\nmov (%rdi,%rdx,4),%ecx\nmov (%rdi,%rax,4),%esi\nmov %esi,(%rdi,%rdx,4)\nadd $0x1,%rdx\nmov %ecx,(%rdi,%rax,4)\nsub $0x1,%rax\ncmp %eax,%edx\njl 1700 \nmov %ebx,%esi\njmpq 14e7 \nxor %edx,%edx\nnopl 0x0(%rax)\nmov (%rdi,%rdx,4),%ecx\nmov (%rdi,%rax,4),%r8d\nmov %r8d,(%rdi,%rdx,4)\nadd $0x1,%rdx\nmov %ecx,(%rdi,%rax,4)\nsub $0x1,%rax\ncmp %edx,%eax\njg 1728 \njmpq 15ed \nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmov rdx, rdi\ncmp esi, 1\njle locret_13FC\nloc_1370:\nmov edi, [rdx]\nmov r9d, esi\nmov eax, 1\nxor ecx, ecx\nnop dword ptr [rax+00h]\nloc_1380:\nmov r8d, [rdx+rax*4]\ncmp r8d, edi\ncmovg ecx, eax\ncmovg edi, r8d\nadd rax, 1\ncmp r9, rax\njnz short loc_1380\nsub esi, 1\ncmp esi, ecx\njnz short loc_13A8\nloc_139E:\ncmp esi, 1\njnz short loc_1370\nretn\nloc_13A8:\ntest ecx, ecx\njle short loc_13D2\nmovsxd rcx, ecx\nxor eax, eax\nnop dword ptr [rax+00000000h]\nloc_13B8:\nmov edi, [rdx+rax*4]\nmov r8d, [rdx+rcx*4]\nmov [rdx+rax*4], r8d\nadd rax, 1\nmov [rdx+rcx*4], edi\nsub rcx, 1\ncmp ecx, eax\njg short loc_13B8\nloc_13D2:\nmovsxd rcx, esi\nxor eax, eax\nnop word ptr [rax+rax+00000000h]\nloc_13E0:\nmov edi, [rdx+rax*4]\nmov r8d, [rdx+rcx*4]\nmov [rdx+rax*4], r8d\nadd rax, 1\nmov [rdx+rcx*4], edi\nsub rcx, 1\ncmp eax, ecx\njl short loc_13E0\njmp short loc_139E\nlocret_13FC:\nretn", + "ida_pseudo": "void __fastcall func0(int *a1, int a2)\n{\n int v3; // edi\n __int64 v4; // rax\n __int64 v5; // rcx\n __int64 v6; // rax\n int v7; // edi\n __int64 v8; // rcx\n __int64 v9; // rax\n int v10; // edi\n\n if ( a2 > 1 )\n {\n do\n {\n v3 = *a1;\n v4 = 1LL;\n LODWORD(v5) = 0;\n do\n {\n if ( a1[v4] > v3 )\n {\n LODWORD(v5) = v4;\n v3 = a1[v4];\n }\n ++v4;\n }\n while ( a2 != v4 );\n if ( --a2 != (_DWORD)v5 )\n {\n if ( (int)v5 > 0 )\n {\n v5 = (int)v5;\n v6 = 0LL;\n do\n {\n v7 = a1[v6];\n a1[v6++] = a1[v5];\n a1[v5--] = v7;\n }\n while ( (int)v5 > (int)v6 );\n }\n v8 = a2;\n v9 = 0LL;\n do\n {\n v10 = a1[v9];\n a1[v9++] = a1[v8];\n a1[v8--] = v10;\n }\n while ( (int)v9 < (int)v8 );\n }\n }\n while ( a2 != 1 );\n }\n}", + "ida_strip_asm": "sub_1360:\nendbr64\nmov rdx, rdi\ncmp esi, 1\njle locret_13FC\nloc_1370:\nmov edi, [rdx]\nmov r9d, esi\nmov eax, 1\nxor ecx, ecx\nnop dword ptr [rax+00h]\nloc_1380:\nmov r8d, [rdx+rax*4]\ncmp r8d, edi\ncmovg ecx, eax\ncmovg edi, r8d\nadd rax, 1\ncmp r9, rax\njnz short loc_1380\nsub esi, 1\ncmp esi, ecx\njnz short loc_13A8\nloc_139E:\ncmp esi, 1\njnz short loc_1370\nretn\nloc_13A8:\ntest ecx, ecx\njle short loc_13D2\nmovsxd rcx, ecx\nxor eax, eax\nnop dword ptr [rax+00000000h]\nloc_13B8:\nmov edi, [rdx+rax*4]\nmov r8d, [rdx+rcx*4]\nmov [rdx+rax*4], r8d\nadd rax, 1\nmov [rdx+rcx*4], edi\nsub rcx, 1\ncmp ecx, eax\njg short loc_13B8\nloc_13D2:\nmovsxd rcx, esi\nxor eax, eax\nnop word ptr [rax+rax+00000000h]\nloc_13E0:\nmov edi, [rdx+rax*4]\nmov r8d, [rdx+rcx*4]\nmov [rdx+rax*4], r8d\nadd rax, 1\nmov [rdx+rcx*4], edi\nsub rcx, 1\ncmp eax, ecx\njl short loc_13E0\njmp short loc_139E\nlocret_13FC:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1360(int *a1, int a2)\n{\n int v3; // edi\n __int64 v4; // rax\n __int64 v5; // rcx\n __int64 v6; // rax\n int v7; // edi\n __int64 v8; // rcx\n __int64 v9; // rax\n int v10; // edi\n\n if ( a2 > 1 )\n {\n do\n {\n v3 = *a1;\n v4 = 1LL;\n LODWORD(v5) = 0;\n do\n {\n if ( a1[v4] > v3 )\n {\n LODWORD(v5) = v4;\n v3 = a1[v4];\n }\n ++v4;\n }\n while ( a2 != v4 );\n if ( --a2 != (_DWORD)v5 )\n {\n if ( (int)v5 > 0 )\n {\n v5 = (int)v5;\n v6 = 0LL;\n do\n {\n v7 = a1[v6];\n a1[v6++] = a1[v5];\n a1[v5--] = v7;\n }\n while ( (int)v5 > (int)v6 );\n }\n v8 = a2;\n v9 = 0LL;\n do\n {\n v10 = a1[v9];\n a1[v9++] = a1[v8];\n a1[v8--] = v10;\n }\n while ( (int)v9 < (int)v8 );\n }\n }\n while ( a2 != 1 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1360(int *a1, int a2) {\n int v3;\n long long v4;\n long long v5;\n long long v6;\n int v7;\n long long v8;\n long long v9;\n int v10;\n if (a2 > 1) {\n do {\n v3 = *a1;\n v4 = 1LL;\n LODWORD(v5) = 0;\n do {\n if (a1[v4] > v3) {\n LODWORD(v5) = v4;\n v3 = a1[v4];\n }\n ++v4;\n } while (a2 != v4);\n if (--a2 != (uint32_t)v5) {\n if ((int)v5 > 0) {\n v5 = (int)v5;\n v6 = 0LL;\n do {\n v7 = a1[v6];\n a1[v6++] = a1[v5];\n a1[v5--] = v7;\n } while ((int)v5 > (int)v6);\n }\n v8 = a2;\n v9 = 0LL;\n do {\n v10 = a1[v9];\n a1[v9++] = a1[v8];\n a1[v8--] = v10;\n } while ((int)v9 < (int)v8);\n }\n } while (a2 != 1);\n }\n}", + "ida_pseudo_norm": "void func0(int *a1, int a2) {\n int v3;\n long long v4;\n long long v5;\n long long v6;\n int v7;\n long long v8;\n long long v9;\n int v10;\n if (a2 > 1) {\n do {\n v3 = *a1;\n v4 = 1LL;\n LODWORD(v5) = 0;\n do {\n if (a1[v4] > v3) {\n LODWORD(v5) = v4;\n v3 = a1[v4];\n }\n ++v4;\n } while (a2 != v4);\n if (--a2 != (uint32_t)v5) {\n if ((int)v5 > 0) {\n v5 = (int)v5;\n v6 = 0LL;\n do {\n v7 = a1[v6];\n a1[v6++] = a1[v5];\n a1[v5--] = v7;\n } while ((int)v5 > (int)v6);\n }\n v8 = a2;\n v9 = 0LL;\n do {\n v10 = a1[v9];\n a1[v9++] = a1[v8];\n a1[v8--] = v10;\n } while ((int)v9 < (int)v8);\n }\n } while (a2 != 1);\n }\n}" + }, + { + "index": 142, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int* list1, int* list2, int* list3, size_t len) {\n int result = 0;\n for (size_t i = 0; i < len; ++i) {\n if (list1[i] == list2[i] && list2[i] == list3[i]) result++;\n }\n return result;\n}", + "test": "int main() {\n\n int list1a[] = {1, 2, 3, 4, 5, 6, 7, 8};\n\n int list2a[] = {2, 2, 3, 1, 2, 6, 7, 9};\n\n int list3a[] = {2, 1, 3, 1, 2, 6, 7, 9};\n\n int list1b[] = {1, 2, 3, 4, 5, 6, 7, 8};\n\n int list2b[] = {2, 2, 3, 1, 2, 6, 7, 8};\n\n int list3b[] = {2, 1, 3, 1, 2, 6, 7, 8};\n\n int list1c[] = {1, 2, 3, 4, 2, 6, 7, 8};\n\n int list2c[] = {2, 2, 3, 1, 2, 6, 7, 8};\n\n int list3c[] = {2, 1, 3, 1, 2, 6, 7, 8};\n\n\n\n assert(func0(list1a, list2a, list3a, sizeof(list1a)/sizeof(list1a[0])) == 3);\n\n assert(func0(list1b, list2b, list3b, sizeof(list1b)/sizeof(list1b[0])) == 4);\n\n assert(func0(list1c, list2c, list3c, sizeof(list1c)/sizeof(list1c[0])) == 5);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %rcx,-0x30(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovq $0x0,-0x8(%rbp)\njmp 11f7 \nmov -0x8(%rbp),%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x8(%rbp),%rax\nlea 0x0(,%rax,4),%rcx\nmov -0x20(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 11f2 \nmov -0x8(%rbp),%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x8(%rbp),%rax\nlea 0x0(,%rax,4),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 11f2 \naddl $0x1,-0xc(%rbp)\naddq $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%rax\ncmp -0x30(%rbp),%rax\njb 1192 \nmov -0xc(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_28], rdx\nmov [rbp+var_30], rcx\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_11F7\nloc_1192:\nmov rax, [rbp+var_8]\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_8]\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11F2\nmov rax, [rbp+var_8]\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_8]\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11F2\nadd [rbp+var_C], 1\nloc_11F2:\nadd [rbp+var_8], 1\nloc_11F7:\nmov rax, [rbp+var_8]\ncmp rax, [rbp+var_30]\njb short loc_1192\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, __int64 a3, unsigned __int64 a4)\n{\n unsigned int v5; // [rsp+24h] [rbp-Ch]\n unsigned __int64 i; // [rsp+28h] [rbp-8h]\n\n v5 = 0;\n for ( i = 0LL; i < a4; ++i )\n {\n if ( *(_DWORD *)(4 * i + a1) == *(_DWORD *)(4 * i + a2) && *(_DWORD *)(4 * i + a2) == *(_DWORD *)(4 * i + a3) )\n ++v5;\n }\n return v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_28], rdx\nmov [rbp+var_30], rcx\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_11F7\nloc_1192:\nmov rax, [rbp+var_8]\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_8]\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11F2\nmov rax, [rbp+var_8]\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_8]\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11F2\nadd [rbp+var_C], 1\nloc_11F2:\nadd [rbp+var_8], 1\nloc_11F7:\nmov rax, [rbp+var_8]\ncmp rax, [rbp+var_30]\njb short loc_1192\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, __int64 a3, unsigned __int64 a4)\n{\n unsigned int v5; // [rsp+24h] [rbp-Ch]\n unsigned __int64 i; // [rsp+28h] [rbp-8h]\n\n v5 = 0;\n for ( i = 0LL; i < a4; ++i )\n {\n if ( *(_DWORD *)(4 * i + a1) == *(_DWORD *)(4 * i + a2) && *(_DWORD *)(4 * i + a2) == *(_DWORD *)(4 * i + a3) )\n ++v5;\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, long long a3,\n unsigned long long a4) {\n unsigned int v5;\n unsigned long long i;\n v5 = 0;\n for (i = 0LL; i < a4; ++i) {\n if (*(uint32_t *)(4 * i + a1) == *(uint32_t *)(4 * i + a2) &&\n *(uint32_t *)(4 * i + a2) == *(uint32_t *)(4 * i + a3))\n ++v5;\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, long long a3,\n unsigned long long a4) {\n unsigned int v5;\n unsigned long long i;\n v5 = 0;\n for (i = 0LL; i < a4; ++i) {\n if (*(uint32_t *)(4 * i + a1) == *(uint32_t *)(4 * i + a2) &&\n *(uint32_t *)(4 * i + a2) == *(uint32_t *)(4 * i + a3))\n ++v5;\n }\n return v5;\n}" + }, + { + "index": 142, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int* list1, int* list2, int* list3, size_t len) {\n int result = 0;\n for (size_t i = 0; i < len; ++i) {\n if (list1[i] == list2[i] && list2[i] == list3[i]) result++;\n }\n return result;\n}", + "test": "int main() {\n\n int list1a[] = {1, 2, 3, 4, 5, 6, 7, 8};\n\n int list2a[] = {2, 2, 3, 1, 2, 6, 7, 9};\n\n int list3a[] = {2, 1, 3, 1, 2, 6, 7, 9};\n\n int list1b[] = {1, 2, 3, 4, 5, 6, 7, 8};\n\n int list2b[] = {2, 2, 3, 1, 2, 6, 7, 8};\n\n int list3b[] = {2, 1, 3, 1, 2, 6, 7, 8};\n\n int list1c[] = {1, 2, 3, 4, 2, 6, 7, 8};\n\n int list2c[] = {2, 2, 3, 1, 2, 6, 7, 8};\n\n int list3c[] = {2, 1, 3, 1, 2, 6, 7, 8};\n\n\n\n assert(func0(list1a, list2a, list3a, sizeof(list1a)/sizeof(list1a[0])) == 3);\n\n assert(func0(list1b, list2b, list3b, sizeof(list1b)/sizeof(list1b[0])) == 4);\n\n assert(func0(list1c, list2c, list3c, sizeof(list1c)/sizeof(list1c[0])) == 5);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %rcx,%rcx\nje 119e \nmov $0x0,%eax\nmov $0x0,%r9d\njmp 1188 \nadd $0x1,%rax\ncmp %rax,%rcx\nje 11a4 \nmov (%rsi,%rax,4),%r8d\ncmp %r8d,(%rdi,%rax,4)\njne 117f \ncmp (%rdx,%rax,4),%r8d\njne 117f \nadd $0x1,%r9d\njmp 117f \nmov $0x0,%r9d\nmov %r9d,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest rcx, rcx\njz short loc_119E\nmov eax, 0\nmov r9d, 0\njmp short loc_1188\nloc_117F:\nadd rax, 1\ncmp rcx, rax\njz short loc_11A4\nloc_1188:\nmov r8d, [rsi+rax*4]\ncmp [rdi+rax*4], r8d\njnz short loc_117F\ncmp r8d, [rdx+rax*4]\njnz short loc_117F\nadd r9d, 1\njmp short loc_117F\nloc_119E:\nmov r9d, 0\nloc_11A4:\nmov eax, r9d\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, __int64 a3, __int64 a4)\n{\n __int64 v4; // rax\n unsigned int v5; // r9d\n int v6; // r8d\n\n if ( a4 )\n {\n v4 = 0LL;\n v5 = 0;\n do\n {\n v6 = *(_DWORD *)(a2 + 4 * v4);\n if ( *(_DWORD *)(a1 + 4 * v4) == v6 && v6 == *(_DWORD *)(a3 + 4 * v4) )\n ++v5;\n ++v4;\n }\n while ( a4 != v4 );\n }\n else\n {\n return 0;\n }\n return v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest rcx, rcx\njz short loc_119E\nmov eax, 0\nmov r9d, 0\njmp short loc_1188\nloc_117F:\nadd rax, 1\ncmp rcx, rax\njz short loc_11A4\nloc_1188:\nmov r8d, [rsi+rax*4]\ncmp [rdi+rax*4], r8d\njnz short loc_117F\ncmp r8d, [rdx+rax*4]\njnz short loc_117F\nadd r9d, 1\njmp short loc_117F\nloc_119E:\nmov r9d, 0\nloc_11A4:\nmov eax, r9d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, __int64 a3, __int64 a4)\n{\n __int64 v4; // rax\n unsigned int v5; // r9d\n int v6; // r8d\n\n if ( a4 )\n {\n v4 = 0LL;\n v5 = 0;\n do\n {\n v6 = *(_DWORD *)(a2 + 4 * v4);\n if ( *(_DWORD *)(a1 + 4 * v4) == v6 && v6 == *(_DWORD *)(a3 + 4 * v4) )\n ++v5;\n ++v4;\n }\n while ( a4 != v4 );\n }\n else\n {\n return 0;\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, long long a3, long long a4) {\n long long v4;\n unsigned int v5;\n int v6;\n if (a4) {\n v4 = 0LL;\n v5 = 0;\n do {\n v6 = *(uint32_t *)(a2 + 4 * v4);\n if (*(uint32_t *)(a1 + 4 * v4) == v6 && v6 == *(uint32_t *)(a3 + 4 * v4))\n ++v5;\n ++v4;\n } while (a4 != v4);\n } else {\n return 0;\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, long long a3, long long a4) {\n long long v4;\n unsigned int v5;\n int v6;\n if (a4) {\n v4 = 0LL;\n v5 = 0;\n do {\n v6 = *(uint32_t *)(a2 + 4 * v4);\n if (*(uint32_t *)(a1 + 4 * v4) == v6 && v6 == *(uint32_t *)(a3 + 4 * v4))\n ++v5;\n ++v4;\n } while (a4 != v4);\n } else {\n return 0;\n }\n return v5;\n}" + }, + { + "index": 142, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int* list1, int* list2, int* list3, size_t len) {\n int result = 0;\n for (size_t i = 0; i < len; ++i) {\n if (list1[i] == list2[i] && list2[i] == list3[i]) result++;\n }\n return result;\n}", + "test": "int main() {\n\n int list1a[] = {1, 2, 3, 4, 5, 6, 7, 8};\n\n int list2a[] = {2, 2, 3, 1, 2, 6, 7, 9};\n\n int list3a[] = {2, 1, 3, 1, 2, 6, 7, 9};\n\n int list1b[] = {1, 2, 3, 4, 5, 6, 7, 8};\n\n int list2b[] = {2, 2, 3, 1, 2, 6, 7, 8};\n\n int list3b[] = {2, 1, 3, 1, 2, 6, 7, 8};\n\n int list1c[] = {1, 2, 3, 4, 2, 6, 7, 8};\n\n int list2c[] = {2, 2, 3, 1, 2, 6, 7, 8};\n\n int list3c[] = {2, 1, 3, 1, 2, 6, 7, 8};\n\n\n\n assert(func0(list1a, list2a, list3a, sizeof(list1a)/sizeof(list1a[0])) == 3);\n\n assert(func0(list1b, list2b, list3b, sizeof(list1b)/sizeof(list1b[0])) == 4);\n\n assert(func0(list1c, list2c, list3c, sizeof(list1c)/sizeof(list1c[0])) == 5);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %rcx,%rcx\nje 1480 \nxor %eax,%eax\nxor %r9d,%r9d\njmp 1459 \nadd $0x1,%rax\ncmp %rax,%rcx\nje 1476 \nmov (%rsi,%rax,4),%r8d\ncmp %r8d,(%rdi,%rax,4)\njne 1450 \ncmp (%rdx,%rax,4),%r8d\njne 1450 \nadd $0x1,%rax\nadd $0x1,%r9d\ncmp %rax,%rcx\njne 1459 \nmov %r9d,%eax\nretq\nnopw 0x0(%rax,%rax,1)\nxor %r9d,%r9d\nmov %r9d,%eax\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest rcx, rcx\njz short loc_1360\nxor eax, eax\nxor r9d, r9d\njmp short loc_1339\nloc_1330:\nadd rax, 1\ncmp rcx, rax\njz short loc_1356\nloc_1339:\nmov r8d, [rsi+rax*4]\ncmp [rdi+rax*4], r8d\njnz short loc_1330\ncmp r8d, [rdx+rax*4]\njnz short loc_1330\nadd rax, 1\nadd r9d, 1\ncmp rcx, rax\njnz short loc_1339\nloc_1356:\nmov eax, r9d\nretn\nloc_1360:\nxor r9d, r9d\nmov eax, r9d\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, __int64 a3, __int64 a4)\n{\n __int64 v4; // rax\n unsigned int v5; // r9d\n int v6; // r8d\n\n if ( !a4 )\n return 0LL;\n v4 = 0LL;\n v5 = 0;\n do\n {\n while ( 1 )\n {\n v6 = *(_DWORD *)(a2 + 4 * v4);\n if ( *(_DWORD *)(a1 + 4 * v4) == v6 && v6 == *(_DWORD *)(a3 + 4 * v4) )\n break;\n if ( a4 == ++v4 )\n return v5;\n }\n ++v4;\n ++v5;\n }\n while ( a4 != v4 );\n return v5;\n}", + "ida_strip_asm": "sub_1320:\nendbr64\ntest rcx, rcx\njz short loc_1360\nxor eax, eax\nxor r9d, r9d\njmp short loc_1339\nloc_1330:\nadd rax, 1\ncmp rcx, rax\njz short loc_1356\nloc_1339:\nmov r8d, [rsi+rax*4]\ncmp [rdi+rax*4], r8d\njnz short loc_1330\ncmp r8d, [rdx+rax*4]\njnz short loc_1330\nadd rax, 1\nadd r9d, 1\ncmp rcx, rax\njnz short loc_1339\nloc_1356:\nmov eax, r9d\nretn\nloc_1360:\nxor r9d, r9d\nmov eax, r9d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1320(__int64 a1, __int64 a2, __int64 a3, __int64 a4)\n{\n __int64 v4; // rax\n unsigned int v5; // r9d\n int v6; // r8d\n\n if ( !a4 )\n return 0LL;\n v4 = 0LL;\n v5 = 0;\n do\n {\n while ( 1 )\n {\n v6 = *(_DWORD *)(a2 + 4 * v4);\n if ( *(_DWORD *)(a1 + 4 * v4) == v6 && v6 == *(_DWORD *)(a3 + 4 * v4) )\n break;\n if ( a4 == ++v4 )\n return v5;\n }\n ++v4;\n ++v5;\n }\n while ( a4 != v4 );\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1320(long long a1, long long a2, long long a3, long long a4) {\n long long v4;\n unsigned int v5;\n int v6;\n if (!a4) return 0LL;\n v4 = 0LL;\n v5 = 0;\n do {\n while (1) {\n v6 = *(uint32_t *)(a2 + 4 * v4);\n if (*(uint32_t *)(a1 + 4 * v4) == v6 && v6 == *(uint32_t *)(a3 + 4 * v4))\n break;\n if (a4 == ++v4) return v5;\n }\n ++v4;\n ++v5;\n } while (a4 != v4);\n return v5;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, long long a3, long long a4) {\n long long v4;\n unsigned int v5;\n int v6;\n if (!a4) return 0LL;\n v4 = 0LL;\n v5 = 0;\n do {\n while (1) {\n v6 = *(uint32_t *)(a2 + 4 * v4);\n if (*(uint32_t *)(a1 + 4 * v4) == v6 && v6 == *(uint32_t *)(a3 + 4 * v4))\n break;\n if (a4 == ++v4) return v5;\n }\n ++v4;\n ++v5;\n } while (a4 != v4);\n return v5;\n}" + }, + { + "index": 143, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int is_list, int length) {\n if (is_list) {\n return 1;\n } else {\n return length;\n }\n}", + "test": "int main() {\n\n // ([1, 2, 3, 4], [5, 6, 7, 8]) -> tuple of length 2\n\n assert(func0(0, 2) == 2);\n\n \n\n // ([1, 2], [3, 4], [5, 6]) -> tuple of length 3\n\n assert(func0(0, 3) == 3);\n\n \n\n // [9, 8, 7, 6, 5, 4, 3, 2, 1] -> list\n\n assert(func0(1, 0) == 1);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov %esi,-0x8(%rbp)\ncmpl $0x0,-0x4(%rbp)\nje 1164 \nmov $0x1,%eax\njmp 1167 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\ncmp [rbp+var_4], 0\njz short loc_1164\nmov eax, 1\njmp short loc_1167\nloc_1164:\nmov eax, [rbp+var_8]\nloc_1167:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, unsigned int a2)\n{\n if ( a1 )\n return 1LL;\n else\n return a2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\ncmp [rbp+var_4], 0\njz short loc_1164\nmov eax, 1\njmp short loc_1167\nloc_1164:\nmov eax, [rbp+var_8]\nloc_1167:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, unsigned int a2)\n{\n if ( a1 )\n return 1LL;\n else\n return a2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, unsigned int a2) {\n if (a1)\n return 1LL;\n else\n return a2;\n}", + "ida_pseudo_norm": "long long func0(int a1, unsigned int a2) {\n if (a1)\n return 1LL;\n else\n return a2;\n}" + }, + { + "index": 144, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int sum = 0;\n for (int i = n - 1; i >= 0; --i) {\n sum += i * arr[i] - (n - 1 - i) * arr[i];\n }\n return sum;\n}", + "test": "int main() {\n\n int arr1[5] = {1, 8, 9, 15, 16};\n\n assert(func0(arr1, 5) == 74);\n\n \n\n int arr2[4] = {1, 2, 3, 4};\n\n assert(func0(arr2, 4) == 10);\n\n \n\n int arr3[9] = {1, 2, 3, 4, 5, 7, 9, 11, 14};\n\n assert(func0(arr3, 9) == 188);\n\n \n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x8(%rbp)\nmov -0x1c(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0x4(%rbp)\njmp 11d5 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nimul -0x4(%rbp),%eax\nmov %eax,%edx\nmov -0x1c(%rbp),%eax\nsub $0x1,%eax\nsub -0x4(%rbp),%eax\nmov %eax,%ecx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rsi\nmov -0x18(%rbp),%rax\nadd %rsi,%rax\nmov (%rax),%eax\nimul %ecx,%eax\nsub %eax,%edx\nmov %edx,%eax\nadd %eax,-0x8(%rbp)\nsubl $0x1,-0x4(%rbp)\ncmpl $0x0,-0x4(%rbp)\njns 118a \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov eax, [rbp+var_1C]\nsub eax, 1\nmov [rbp+var_4], eax\njmp short loc_11D5\nloc_118A:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nimul eax, [rbp+var_4]\nmov ecx, eax\nmov eax, [rbp+var_1C]\nsub eax, 1\nsub eax, [rbp+var_4]\nmov edx, eax\nmov eax, [rbp+var_4]\ncdqe\nlea rsi, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rsi\nmov eax, [rax]\nimul eax, edx\nsub ecx, eax\nmov edx, ecx\nadd [rbp+var_8], edx\nsub [rbp+var_4], 1\nloc_11D5:\ncmp [rbp+var_4], 0\njns short loc_118A\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = a2 - 1; i >= 0; --i )\n v3 += i * *(_DWORD *)(4LL * i + a1) - (a2 - 1 - i) * *(_DWORD *)(4LL * i + a1);\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov eax, [rbp+var_1C]\nsub eax, 1\nmov [rbp+var_4], eax\njmp short loc_11D5\nloc_118A:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nimul eax, [rbp+var_4]\nmov ecx, eax\nmov eax, [rbp+var_1C]\nsub eax, 1\nsub eax, [rbp+var_4]\nmov edx, eax\nmov eax, [rbp+var_4]\ncdqe\nlea rsi, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rsi\nmov eax, [rax]\nimul eax, edx\nsub ecx, eax\nmov edx, ecx\nadd [rbp+var_8], edx\nsub [rbp+var_4], 1\nloc_11D5:\ncmp [rbp+var_4], 0\njns short loc_118A\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = a2 - 1; i >= 0; --i )\n v3 += i * *(_DWORD *)(4LL * i + a1) - (a2 - 1 - i) * *(_DWORD *)(4LL * i + a1);\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = a2 - 1; i >= 0; --i)\n v3 += i * *(uint32_t *)(4LL * i + a1) -\n (a2 - 1 - i) * *(uint32_t *)(4LL * i + a1);\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = a2 - 1; i >= 0; --i)\n v3 += i * *(uint32_t *)(4LL * i + a1) -\n (a2 - 1 - i) * *(uint32_t *)(4LL * i + a1);\n return v3;\n}" + }, + { + "index": 144, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int sum = 0;\n for (int i = n - 1; i >= 0; --i) {\n sum += i * arr[i] - (n - 1 - i) * arr[i];\n }\n return sum;\n}", + "test": "int main() {\n\n int arr1[5] = {1, 8, 9, 15, 16};\n\n assert(func0(arr1, 5) == 74);\n\n \n\n int arr2[4] = {1, 2, 3, 4};\n\n assert(func0(arr2, 4) == 10);\n\n \n\n int arr3[9] = {1, 2, 3, 4, 5, 7, 9, 11, 14};\n\n assert(func0(arr3, 9) == 188);\n\n \n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %esi,%eax\nsub $0x1,%eax\njs 119c \ncltq\nmov $0x0,%ecx\nsub $0x1,%esi\nmov %esi,%edx\nsub %eax,%edx\nmov %eax,%r8d\nsub %edx,%r8d\nmov %r8d,%edx\nimul (%rdi,%rax,4),%edx\nadd %edx,%ecx\nsub $0x1,%rax\ntest %eax,%eax\njns 117e \nmov %ecx,%eax\nretq\nmov $0x0,%ecx\njmp 1199 \n", + "ida_asm": "func0:\nendbr64\nmov eax, esi\nsub eax, 1\njs short loc_119A\ncdqe\nmov ecx, 0\nsub esi, 1\nloc_117E:\nmov r8d, esi\nsub r8d, eax\nmov edx, eax\nsub edx, r8d\nimul edx, [rdi+rax*4]\nadd ecx, edx\nsub rax, 1\ntest eax, eax\njns short loc_117E\nloc_1197:\nmov eax, ecx\nretn\nloc_119A:\nmov ecx, 0\njmp short loc_1197", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // rax\n unsigned int v3; // ecx\n int v4; // esi\n\n LODWORD(v2) = a2 - 1;\n if ( a2 - 1 < 0 )\n {\n return 0;\n }\n else\n {\n v2 = (int)v2;\n v3 = 0;\n v4 = a2 - 1;\n do\n {\n v3 += *(_DWORD *)(a1 + 4 * v2) * (v2 - (v4 - v2));\n --v2;\n }\n while ( (int)v2 >= 0 );\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov eax, esi\nsub eax, 1\njs short loc_119A\ncdqe\nmov ecx, 0\nsub esi, 1\nloc_117E:\nmov r8d, esi\nsub r8d, eax\nmov edx, eax\nsub edx, r8d\nimul edx, [rdi+rax*4]\nadd ecx, edx\nsub rax, 1\ntest eax, eax\njns short loc_117E\nloc_1197:\nmov eax, ecx\nretn\nloc_119A:\nmov ecx, 0\njmp short loc_1197", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n __int64 v2; // rax\n unsigned int v3; // ecx\n int v4; // esi\n\n LODWORD(v2) = a2 - 1;\n if ( a2 - 1 < 0 )\n {\n return 0;\n }\n else\n {\n v2 = (int)v2;\n v3 = 0;\n v4 = a2 - 1;\n do\n {\n v3 += *(_DWORD *)(a1 + 4 * v2) * (v2 - (v4 - v2));\n --v2;\n }\n while ( (int)v2 >= 0 );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n int v4;\n LODWORD(v2) = a2 - 1;\n if (a2 - 1 < 0) {\n return 0;\n } else {\n v2 = (int)v2;\n v3 = 0;\n v4 = a2 - 1;\n do {\n v3 += *(uint32_t *)(a1 + 4 * v2) * (v2 - (v4 - v2));\n --v2;\n } while ((int)v2 >= 0);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n int v4;\n LODWORD(v2) = a2 - 1;\n if (a2 - 1 < 0) {\n return 0;\n } else {\n v2 = (int)v2;\n v3 = 0;\n v4 = a2 - 1;\n do {\n v3 += *(uint32_t *)(a1 + 4 * v2) * (v2 - (v4 - v2));\n --v2;\n } while ((int)v2 >= 0);\n }\n return v3;\n}" + }, + { + "index": 144, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int sum = 0;\n for (int i = n - 1; i >= 0; --i) {\n sum += i * arr[i] - (n - 1 - i) * arr[i];\n }\n return sum;\n}", + "test": "int main() {\n\n int arr1[5] = {1, 8, 9, 15, 16};\n\n assert(func0(arr1, 5) == 74);\n\n \n\n int arr2[4] = {1, 2, 3, 4};\n\n assert(func0(arr2, 4) == 10);\n\n \n\n int arr3[9] = {1, 2, 3, 4, 5, 7, 9, 11, 14};\n\n assert(func0(arr3, 9) == 188);\n\n \n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x1,%esi\njs 12f0 \nmovslq %esi,%rax\nxor %r8d,%r8d\nmov %esi,%edx\nmov %eax,%ecx\nsub %eax,%edx\nsub %edx,%ecx\nmov (%rdi,%rax,4),%edx\nsub $0x1,%rax\nimul %ecx,%edx\nadd %edx,%r8d\ntest %eax,%eax\njns 12d0 \nmov %r8d,%eax\nretq\nnopl (%rax)\nxor %r8d,%r8d\nmov %r8d,%eax\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nsub esi, 1\njs short loc_12B0\nmovsxd rax, esi\nxor ecx, ecx\nxchg ax, ax\nloc_1290:\nmov r8d, esi\nmov edx, eax\nsub r8d, eax\nsub edx, r8d\nimul edx, [rdi+rax*4]\nsub rax, 1\nadd ecx, edx\ntest eax, eax\njns short loc_1290\nmov eax, ecx\nretn\nloc_12B0:\nxor ecx, ecx\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int v2; // esi\n __int64 v3; // rax\n unsigned int v4; // ecx\n int v5; // edx\n\n v2 = a2 - 1;\n if ( v2 < 0 )\n return 0LL;\n v3 = v2;\n v4 = 0;\n do\n {\n v5 = *(_DWORD *)(a1 + 4 * v3) * (v3 - (v2 - v3));\n --v3;\n v4 += v5;\n }\n while ( (int)v3 >= 0 );\n return v4;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\nsub esi, 1\njs short loc_12B0\nmovsxd rax, esi\nxor ecx, ecx\nxchg ax, ax\nloc_1290:\nmov r8d, esi\nmov edx, eax\nsub r8d, eax\nsub edx, r8d\nimul edx, [rdi+rax*4]\nsub rax, 1\nadd ecx, edx\ntest eax, eax\njns short loc_1290\nmov eax, ecx\nretn\nloc_12B0:\nxor ecx, ecx\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1280(__int64 a1, int a2)\n{\n int v2; // esi\n __int64 v3; // rax\n unsigned int v4; // ecx\n int v5; // edx\n\n v2 = a2 - 1;\n if ( v2 < 0 )\n return 0LL;\n v3 = v2;\n v4 = 0;\n do\n {\n v5 = *(_DWORD *)(a1 + 4 * v3) * (v3 - (v2 - v3));\n --v3;\n v4 += v5;\n }\n while ( (int)v3 >= 0 );\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1280(long long a1, int a2) {\n int v2;\n long long v3;\n unsigned int v4;\n int v5;\n v2 = a2 - 1;\n if (v2 < 0) return 0LL;\n v3 = v2;\n v4 = 0;\n do {\n v5 = *(uint32_t *)(a1 + 4 * v3) * (v3 - (v2 - v3));\n --v3;\n v4 += v5;\n } while ((int)v3 >= 0);\n return v4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int v2;\n long long v3;\n unsigned int v4;\n int v5;\n v2 = a2 - 1;\n if (v2 < 0) return 0LL;\n v3 = v2;\n v4 = 0;\n do {\n v5 = *(uint32_t *)(a1 + 4 * v3) * (v3 - (v2 - v3));\n --v3;\n v4 += v5;\n } while ((int)v3 >= 0);\n return v4;\n}" + }, + { + "index": 145, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int minEle = arr[0];\n int maxEle = arr[0];\n for (int i = 1; i < n; i++) {\n if (arr[i] < minEle) {\n minEle = arr[i];\n }\n if (arr[i] > maxEle) {\n maxEle = arr[i];\n }\n }\n return (maxEle - minEle);\n}", + "test": "int main() {\n\n int arr1[] = {2, 1, 5, 3};\n\n int arr2[] = {9, 3, 2, 5, 1};\n\n int arr3[] = {3, 2, 1};\n\n\n\n assert(func0(arr1, 4) == 4);\n\n assert(func0(arr2, 5) == 8);\n\n assert(func0(arr3, 3) == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov -0x18(%rbp),%rax\nmov (%rax),%eax\nmov %eax,-0xc(%rbp)\nmov -0x18(%rbp),%rax\nmov (%rax),%eax\nmov %eax,-0x8(%rbp)\nmovl $0x1,-0x4(%rbp)\njmp 11ff \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0xc(%rbp)\njle 11c7 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0xc(%rbp)\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x8(%rbp)\njge 11fb \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1193 \nmov -0x8(%rbp),%eax\nsub -0xc(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov rax, [rbp+var_18]\nmov eax, [rax]\nmov [rbp+var_C], eax\nmov rax, [rbp+var_18]\nmov eax, [rax]\nmov [rbp+var_8], eax\nmov [rbp+var_4], 1\njmp short loc_11FF\nloc_1193:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_C], eax\njle short loc_11C7\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nloc_11C7:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_8], eax\njge short loc_11FB\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_8], eax\nloc_11FB:\nadd [rbp+var_4], 1\nloc_11FF:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1193\nmov eax, [rbp+var_8]\nsub eax, [rbp+var_C]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int v3; // [rsp+10h] [rbp-Ch]\n int v4; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = *a1;\n v4 = *a1;\n for ( i = 1; i < a2; ++i )\n {\n if ( v3 > a1[i] )\n v3 = a1[i];\n if ( v4 < a1[i] )\n v4 = a1[i];\n }\n return (unsigned int)(v4 - v3);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov rax, [rbp+var_18]\nmov eax, [rax]\nmov [rbp+var_C], eax\nmov rax, [rbp+var_18]\nmov eax, [rax]\nmov [rbp+var_8], eax\nmov [rbp+var_4], 1\njmp short loc_11FF\nloc_1193:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_C], eax\njle short loc_11C7\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nloc_11C7:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_8], eax\njge short loc_11FB\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_8], eax\nloc_11FB:\nadd [rbp+var_4], 1\nloc_11FF:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1193\nmov eax, [rbp+var_8]\nsub eax, [rbp+var_C]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int *a1, int a2)\n{\n int v3; // [rsp+10h] [rbp-Ch]\n int v4; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = *a1;\n v4 = *a1;\n for ( i = 1; i < a2; ++i )\n {\n if ( v3 > a1[i] )\n v3 = a1[i];\n if ( v4 < a1[i] )\n v4 = a1[i];\n }\n return (unsigned int)(v4 - v3);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int *a1, int a2) {\n int v3;\n int v4;\n int i;\n v3 = *a1;\n v4 = *a1;\n for (i = 1; i < a2; ++i) {\n if (v3 > a1[i]) v3 = a1[i];\n if (v4 < a1[i]) v4 = a1[i];\n }\n return (unsigned int)(v4 - v3);\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int v3;\n int v4;\n int i;\n v3 = *a1;\n v4 = *a1;\n for (i = 1; i < a2; ++i) {\n if (v3 > a1[i]) v3 = a1[i];\n if (v4 < a1[i]) v4 = a1[i];\n }\n return (unsigned int)(v4 - v3);\n}" + }, + { + "index": 145, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int minEle = arr[0];\n int maxEle = arr[0];\n for (int i = 1; i < n; i++) {\n if (arr[i] < minEle) {\n minEle = arr[i];\n }\n if (arr[i] > maxEle) {\n maxEle = arr[i];\n }\n }\n return (maxEle - minEle);\n}", + "test": "int main() {\n\n int arr1[] = {2, 1, 5, 3};\n\n int arr2[] = {9, 3, 2, 5, 1};\n\n int arr3[] = {3, 2, 1};\n\n\n\n assert(func0(arr1, 4) == 4);\n\n assert(func0(arr2, 5) == 8);\n\n assert(func0(arr3, 3) == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov (%rdi),%r8d\ncmp $0x1,%esi\njle 119f \nlea 0x4(%rdi),%rcx\nlea -0x2(%rsi),%eax\nlea 0x8(%rdi,%rax,4),%rsi\nmov %r8d,%eax\nmov (%rcx),%edx\ncmp %edx,%r8d\ncmovg %edx,%r8d\ncmp %edx,%eax\ncmovl %edx,%eax\nadd $0x4,%rcx\ncmp %rsi,%rcx\njne 1184 \nsub %r8d,%eax\nretq\nmov %r8d,%eax\njmp 119b \n", + "ida_asm": "func0:\nendbr64\nmov r8d, [rdi]\ncmp esi, 1\njle short loc_119F\nlea rcx, [rdi+4]\nlea eax, [rsi-2]\nlea rsi, [rdi+rax*4+8]\nmov eax, r8d\nloc_1184:\nmov edx, [rcx]\ncmp r8d, edx\ncmovg r8d, edx\ncmp eax, edx\ncmovl eax, edx\nadd rcx, 4\ncmp rcx, rsi\njnz short loc_1184\nloc_119B:\nsub eax, r8d\nretn\nloc_119F:\nmov eax, r8d\njmp short loc_119B", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int v2; // r8d\n int *v3; // rcx\n __int64 v4; // rsi\n int v5; // eax\n\n v2 = *a1;\n if ( a2 <= 1 )\n {\n v5 = *a1;\n }\n else\n {\n v3 = a1 + 1;\n v4 = (__int64)&a1[a2 - 2 + 2];\n v5 = *a1;\n do\n {\n if ( v2 > *v3 )\n v2 = *v3;\n if ( v5 < *v3 )\n v5 = *v3;\n ++v3;\n }\n while ( v3 != (int *)v4 );\n }\n return (unsigned int)(v5 - v2);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov r8d, [rdi]\ncmp esi, 1\njle short loc_119F\nlea rcx, [rdi+4]\nlea eax, [rsi-2]\nlea rsi, [rdi+rax*4+8]\nmov eax, r8d\nloc_1184:\nmov edx, [rcx]\ncmp r8d, edx\ncmovg r8d, edx\ncmp eax, edx\ncmovl eax, edx\nadd rcx, 4\ncmp rcx, rsi\njnz short loc_1184\nloc_119B:\nsub eax, r8d\nretn\nloc_119F:\nmov eax, r8d\njmp short loc_119B", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int *a1, int a2)\n{\n int v2; // r8d\n int *v3; // rcx\n __int64 v4; // rsi\n int v5; // eax\n\n v2 = *a1;\n if ( a2 <= 1 )\n {\n v5 = *a1;\n }\n else\n {\n v3 = a1 + 1;\n v4 = (__int64)&a1[a2 - 2 + 2];\n v5 = *a1;\n do\n {\n if ( v2 > *v3 )\n v2 = *v3;\n if ( v5 < *v3 )\n v5 = *v3;\n ++v3;\n }\n while ( v3 != (int *)v4 );\n }\n return (unsigned int)(v5 - v2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int *a1, int a2) {\n int v2;\n int *v3;\n long long v4;\n int v5;\n v2 = *a1;\n if (a2 <= 1) {\n v5 = *a1;\n } else {\n v3 = a1 + 1;\n v4 = (long long)&a1[a2 - 2 + 2];\n v5 = *a1;\n do {\n if (v2 > *v3) v2 = *v3;\n if (v5 < *v3) v5 = *v3;\n ++v3;\n } while (v3 != (int *)v4);\n }\n return (unsigned int)(v5 - v2);\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int v2;\n int *v3;\n long long v4;\n int v5;\n v2 = *a1;\n if (a2 <= 1) {\n v5 = *a1;\n } else {\n v3 = a1 + 1;\n v4 = (long long)&a1[a2 - 2 + 2];\n v5 = *a1;\n do {\n if (v2 > *v3) v2 = *v3;\n if (v5 < *v3) v5 = *v3;\n ++v3;\n } while (v3 != (int *)v4);\n }\n return (unsigned int)(v5 - v2);\n}" + }, + { + "index": 146, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(char* str1) { return str1[0]; }", + "test": "int main() {\n\n assert(func0(\"python\") == 112);\n\n assert(func0(\"Program\") == 80);\n\n assert(func0(\"Language\") == 76);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x8(%rbp)\nmov -0x8(%rbp),%rax\nmovzbl (%rax),%eax\nmovsbl %al,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_8], rdi\nmov rax, [rbp+var_8]\nmovzx eax, byte ptr [rax]\nmovsx eax, al\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(char *a1)\n{\n return (unsigned int)*a1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_8], rdi\nmov rax, [rbp+var_8]\nmovzx eax, byte ptr [rax]\nmovsx eax, al\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(char *a1)\n{\n return (unsigned int)*a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(char *a1) { return (unsigned int)*a1; }", + "ida_pseudo_norm": "long long func0(char *a1) { return (unsigned int)*a1; }" + }, + { + "index": 147, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(int tri[3][3], int m, int n) {\n for (int i = m - 1; i >= 0; i--) {\n for (int j = 0; j <= i; j++) {\n if (tri[i + 1][j] > tri[i + 1][j + 1]) {\n tri[i][j] += tri[i + 1][j];\n } else {\n tri[i][j] += tri[i + 1][j + 1];\n }\n }\n }\n return tri[0][0];\n}", + "test": "int main() {\n\n int tri1[3][3] = {{1, 0, 0}, {4, 8, 0}, {1, 5, 3}};\n\n int tri2[3][3] = {{13, 0, 0}, {7, 4, 0}, {2, 4, 6}};\n\n int tri3[3][3] = {{2, 0, 0}, {11, 18, 0}, {21, 25, 33}};\n\n\n\n assert(func0(tri1, 2, 2) == 14);\n\n assert(func0(tri2, 2, 2) == 24);\n\n assert(func0(tri3, 2, 2) == 53);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmov -0x1c(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0x8(%rbp)\njmpq 12ed \nmovl $0x0,-0x4(%rbp)\njmpq 12dd \nmov -0x8(%rbp),%eax\ncltq\nlea 0x1(%rax),%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0x4(%rbp),%eax\ncltq\nmov (%rdx,%rax,4),%ecx\nmov -0x8(%rbp),%eax\ncltq\nlea 0x1(%rax),%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0x4(%rbp),%eax\nadd $0x1,%eax\ncltq\nmov (%rdx,%rax,4),%eax\ncmp %eax,%ecx\njle 1262 \nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0x4(%rbp),%eax\ncltq\nmov (%rdx,%rax,4),%esi\nmov -0x8(%rbp),%eax\ncltq\nlea 0x1(%rax),%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0x4(%rbp),%eax\ncltq\nmov (%rdx,%rax,4),%ecx\nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nadd %esi,%ecx\nmov -0x4(%rbp),%eax\ncltq\nmov %ecx,(%rdx,%rax,4)\njmp 12d9 \nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0x4(%rbp),%eax\ncltq\nmov (%rdx,%rax,4),%esi\nmov -0x8(%rbp),%eax\ncltq\nlea 0x1(%rax),%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0x4(%rbp),%eax\nadd $0x1,%eax\ncltq\nmov (%rdx,%rax,4),%ecx\nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nadd %esi,%ecx\nmov -0x4(%rbp),%eax\ncltq\nmov %ecx,(%rdx,%rax,4)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x8(%rbp),%eax\njle 1195 \nsubl $0x1,-0x8(%rbp)\ncmpl $0x0,-0x8(%rbp)\njns 1189 \nmov -0x18(%rbp),%rax\nmov (%rax),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov eax, [rbp+var_1C]\nsub eax, 1\nmov [rbp+var_8], eax\njmp loc_12ED\nloc_1189:\nmov [rbp+var_4], 0\njmp loc_12DD\nloc_1195:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, [rax+1]\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\ncdqe\nmov ecx, [rdx+rax*4]\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, [rax+1]\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\nadd eax, 1\ncdqe\nmov eax, [rdx+rax*4]\ncmp ecx, eax\njle short loc_1262\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\ncdqe\nmov esi, [rdx+rax*4]\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, [rax+1]\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\ncdqe\nmov ecx, [rdx+rax*4]\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nadd ecx, esi\nmov eax, [rbp+var_4]\ncdqe\nmov [rdx+rax*4], ecx\njmp short loc_12D9\nloc_1262:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\ncdqe\nmov esi, [rdx+rax*4]\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, [rax+1]\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\nadd eax, 1\ncdqe\nmov ecx, [rdx+rax*4]\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nadd ecx, esi\nmov eax, [rbp+var_4]\ncdqe\nmov [rdx+rax*4], ecx\nloc_12D9:\nadd [rbp+var_4], 1\nloc_12DD:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_8]\njle loc_1195\nsub [rbp+var_8], 1\nloc_12ED:\ncmp [rbp+var_8], 0\njns loc_1189\nmov rax, [rbp+var_18]\nmov eax, [rax]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n unsigned int v2; // ecx\n int i; // [rsp+18h] [rbp-8h]\n int j; // [rsp+1Ch] [rbp-4h]\n\n for ( i = a2 - 1; i >= 0; --i )\n {\n for ( j = 0; j <= i; ++j )\n {\n if ( (int)a1[3 * i + 3 + j] <= (int)a1[3 * i + 4 + j] )\n v2 = a1[3 * i + 4 + j];\n else\n v2 = a1[3 * i + 3 + j];\n a1[3 * i + j] += v2;\n }\n }\n return *a1;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov eax, [rbp+var_1C]\nsub eax, 1\nmov [rbp+var_8], eax\njmp loc_12ED\nloc_1189:\nmov [rbp+var_4], 0\njmp loc_12DD\nloc_1195:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, [rax+1]\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\ncdqe\nmov ecx, [rdx+rax*4]\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, [rax+1]\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\nadd eax, 1\ncdqe\nmov eax, [rdx+rax*4]\ncmp ecx, eax\njle short loc_1262\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\ncdqe\nmov esi, [rdx+rax*4]\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, [rax+1]\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\ncdqe\nmov ecx, [rdx+rax*4]\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nadd ecx, esi\nmov eax, [rbp+var_4]\ncdqe\nmov [rdx+rax*4], ecx\njmp short loc_12D9\nloc_1262:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\ncdqe\nmov esi, [rdx+rax*4]\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, [rax+1]\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\nadd eax, 1\ncdqe\nmov ecx, [rdx+rax*4]\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nadd ecx, esi\nmov eax, [rbp+var_4]\ncdqe\nmov [rdx+rax*4], ecx\nloc_12D9:\nadd [rbp+var_4], 1\nloc_12DD:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_8]\njle loc_1195\nsub [rbp+var_8], 1\nloc_12ED:\ncmp [rbp+var_8], 0\njns loc_1189\nmov rax, [rbp+var_18]\nmov eax, [rax]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(unsigned int *a1, int a2)\n{\n unsigned int v2; // ecx\n int i; // [rsp+18h] [rbp-8h]\n int j; // [rsp+1Ch] [rbp-4h]\n\n for ( i = a2 - 1; i >= 0; --i )\n {\n for ( j = 0; j <= i; ++j )\n {\n if ( (int)a1[3 * i + 3 + j] <= (int)a1[3 * i + 4 + j] )\n v2 = a1[3 * i + 4 + j];\n else\n v2 = a1[3 * i + 3 + j];\n a1[3 * i + j] += v2;\n }\n }\n return *a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(unsigned int *a1, int a2) {\n unsigned int v2;\n int i;\n int j;\n for (i = a2 - 1; i >= 0; --i) {\n for (j = 0; j <= i; ++j) {\n if ((int)a1[3 * i + 3 + j] <= (int)a1[3 * i + 4 + j])\n v2 = a1[3 * i + 4 + j];\n else\n v2 = a1[3 * i + 3 + j];\n a1[3 * i + j] += v2;\n }\n }\n return *a1;\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n unsigned int v2;\n int i;\n int j;\n for (i = a2 - 1; i >= 0; --i) {\n for (j = 0; j <= i; ++j) {\n if ((int)a1[3 * i + 3 + j] <= (int)a1[3 * i + 4 + j])\n v2 = a1[3 * i + 4 + j];\n else\n v2 = a1[3 * i + 3 + j];\n a1[3 * i + j] += v2;\n }\n }\n return *a1;\n}" + }, + { + "index": 147, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(int tri[3][3], int m, int n) {\n for (int i = m - 1; i >= 0; i--) {\n for (int j = 0; j <= i; j++) {\n if (tri[i + 1][j] > tri[i + 1][j + 1]) {\n tri[i][j] += tri[i + 1][j];\n } else {\n tri[i][j] += tri[i + 1][j + 1];\n }\n }\n }\n return tri[0][0];\n}", + "test": "int main() {\n\n int tri1[3][3] = {{1, 0, 0}, {4, 8, 0}, {1, 5, 3}};\n\n int tri2[3][3] = {{13, 0, 0}, {7, 4, 0}, {2, 4, 6}};\n\n int tri3[3][3] = {{2, 0, 0}, {11, 18, 0}, {21, 25, 33}};\n\n\n\n assert(func0(tri1, 2, 2) == 14);\n\n assert(func0(tri2, 2, 2) == 24);\n\n assert(func0(tri3, 2, 2) == 53);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x1,%esi\njs 11bc \nmovslq %esi,%rax\nlea (%rax,%rax,2),%rax\nlea (%rdi,%rax,4),%r10\njmp 11aa \nadd %edx,(%r8,%rax,4)\nadd $0x1,%rax\ncmp %eax,%esi\njl 119e \nmov (%r9,%rax,4),%ecx\nmov 0x4(%r9,%rax,4),%edx\ncmp %edx,%ecx\njle 117f \nadd %ecx,(%r8,%rax,4)\njmp 1183 \nsub $0x1,%esi\nsub $0xc,%r10\ncmp $0xffffffff,%esi\nje 11bc \ntest %esi,%esi\njs 119e \nlea 0xc(%r10),%r9\nmov %r10,%r8\nmov $0x0,%eax\njmp 118b \nmov (%rdi),%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nsub esi, 1\njs short loc_11BD\nmovsxd rax, esi\nlea rax, [rax+rax*2]\nlea r10, [rdi+rax*4]\njmp short loc_11AF\nloc_117F:\nadd edx, [rcx+rax*4]\nloc_1182:\nmov [rcx+rax*4], edx\nadd rax, 1\ncmp esi, eax\njl short loc_11A3\nloc_118D:\nmov r9d, [r8+rax*4]\nmov edx, [r8+rax*4+4]\ncmp r9d, edx\njle short loc_117F\nmov edx, r9d\nadd edx, [rcx+rax*4]\njmp short loc_1182\nloc_11A3:\nsub esi, 1\nsub r10, 0Ch\ncmp esi, 0FFFFFFFFh\njz short loc_11BD\nloc_11AF:\nlea r8, [r10+0Ch]\nmov rcx, r10\nmov eax, 0\njmp short loc_118D\nloc_11BD:\nmov eax, [rdi]\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n int v2; // esi\n unsigned int *v3; // r10\n unsigned int v4; // edx\n __int64 v5; // rax\n signed int v6; // r9d\n signed int v7; // edx\n unsigned int *v8; // r8\n\n v2 = a2 - 1;\n if ( v2 >= 0 )\n {\n v3 = &a1[3 * v2];\n do\n {\n v8 = v3 + 3;\n v5 = 0LL;\n do\n {\n v6 = v8[v5];\n v7 = v8[v5 + 1];\n if ( v6 <= v7 )\n v4 = v3[v5] + v7;\n else\n v4 = v3[v5] + v6;\n v3[v5++] = v4;\n }\n while ( v2 >= (int)v5 );\n --v2;\n v3 -= 3;\n }\n while ( v2 != -1 );\n }\n return *a1;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nsub esi, 1\njs short loc_11BD\nmovsxd rax, esi\nlea rax, [rax+rax*2]\nlea r10, [rdi+rax*4]\njmp short loc_11AF\nloc_117F:\nadd edx, [rcx+rax*4]\nloc_1182:\nmov [rcx+rax*4], edx\nadd rax, 1\ncmp esi, eax\njl short loc_11A3\nloc_118D:\nmov r9d, [r8+rax*4]\nmov edx, [r8+rax*4+4]\ncmp r9d, edx\njle short loc_117F\nmov edx, r9d\nadd edx, [rcx+rax*4]\njmp short loc_1182\nloc_11A3:\nsub esi, 1\nsub r10, 0Ch\ncmp esi, 0FFFFFFFFh\njz short loc_11BD\nloc_11AF:\nlea r8, [r10+0Ch]\nmov rcx, r10\nmov eax, 0\njmp short loc_118D\nloc_11BD:\nmov eax, [rdi]\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(unsigned int *a1, int a2)\n{\n int v2; // esi\n unsigned int *v3; // r10\n unsigned int v4; // edx\n __int64 v5; // rax\n signed int v6; // r9d\n signed int v7; // edx\n unsigned int *v8; // r8\n\n v2 = a2 - 1;\n if ( v2 >= 0 )\n {\n v3 = &a1[3 * v2];\n do\n {\n v8 = v3 + 3;\n v5 = 0LL;\n do\n {\n v6 = v8[v5];\n v7 = v8[v5 + 1];\n if ( v6 <= v7 )\n v4 = v3[v5] + v7;\n else\n v4 = v3[v5] + v6;\n v3[v5++] = v4;\n }\n while ( v2 >= (int)v5 );\n --v2;\n v3 -= 3;\n }\n while ( v2 != -1 );\n }\n return *a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(unsigned int *a1, int a2) {\n int v2;\n unsigned int *v3;\n unsigned int v4;\n long long v5;\n signed int v6;\n signed int v7;\n unsigned int *v8;\n v2 = a2 - 1;\n if (v2 >= 0) {\n v3 = &a1[3 * v2];\n do {\n v8 = v3 + 3;\n v5 = 0LL;\n do {\n v6 = v8[v5];\n v7 = v8[v5 + 1];\n if (v6 <= v7)\n v4 = v3[v5] + v7;\n else\n v4 = v3[v5] + v6;\n v3[v5++] = v4;\n } while (v2 >= (int)v5);\n --v2;\n v3 -= 3;\n } while (v2 != -1);\n }\n return *a1;\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n int v2;\n unsigned int *v3;\n unsigned int v4;\n long long v5;\n signed int v6;\n signed int v7;\n unsigned int *v8;\n v2 = a2 - 1;\n if (v2 >= 0) {\n v3 = &a1[3 * v2];\n do {\n v8 = v3 + 3;\n v5 = 0LL;\n do {\n v6 = v8[v5];\n v7 = v8[v5 + 1];\n if (v6 <= v7)\n v4 = v3[v5] + v7;\n else\n v4 = v3[v5] + v6;\n v3[v5++] = v4;\n } while (v2 >= (int)v5);\n --v2;\n v3 -= 3;\n } while (v2 != -1);\n }\n return *a1;\n}" + }, + { + "index": 147, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(int tri[3][3], int m, int n) {\n for (int i = m - 1; i >= 0; i--) {\n for (int j = 0; j <= i; j++) {\n if (tri[i + 1][j] > tri[i + 1][j + 1]) {\n tri[i][j] += tri[i + 1][j];\n } else {\n tri[i][j] += tri[i + 1][j + 1];\n }\n }\n }\n return tri[0][0];\n}", + "test": "int main() {\n\n int tri1[3][3] = {{1, 0, 0}, {4, 8, 0}, {1, 5, 3}};\n\n int tri2[3][3] = {{13, 0, 0}, {7, 4, 0}, {2, 4, 6}};\n\n int tri3[3][3] = {{2, 0, 0}, {11, 18, 0}, {21, 25, 33}};\n\n\n\n assert(func0(tri1, 2, 2) == 14);\n\n assert(func0(tri2, 2, 2) == 24);\n\n assert(func0(tri3, 2, 2) == 53);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x1,%esi\nmov %esi,%r9d\njs 135a \nmovslq %esi,%rax\nlea (%rax,%rax,2),%rax\nlea (%rdi,%rax,4),%rcx\nnopw 0x0(%rax,%rax,1)\nlea 0xc(%rcx),%r10\nxor %eax,%eax\nmov (%r10,%rax,4),%r8d\nmov 0x4(%r10,%rax,4),%esi\nmov (%rcx,%rax,4),%edx\nlea (%rsi,%rdx,1),%r11d\nadd %r8d,%edx\ncmp %esi,%r8d\ncmovle %r11d,%edx\nmov %edx,(%rcx,%rax,4)\nadd $0x1,%rax\ncmp %eax,%r9d\njge 1326 \nsub $0x1,%r9d\nsub $0xc,%rcx\ncmp $0xffffffff,%r9d\njne 1320 \nmov (%rdi),%eax\nretq\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\nmov r8d, esi\nmov r11, rdi\nsub r8d, 1\njs short loc_1314\nmovsxd rsi, esi\nlea rax, [rsi+rsi*2]\nlea rsi, [rdi+rax*4]\nnop dword ptr [rax+rax+00h]\nloc_12E0:\nmov r9, rsi\nxor edx, edx\nsub rsi, 0Ch\nmov ecx, [r9]\nloc_12EC:\nmov eax, [rsi+rdx*4]\nmov edi, ecx\nmov ecx, [r9+rdx*4+4]\nlea r10d, [rcx+rax]\nadd eax, edi\ncmp edi, ecx\ncmovle eax, r10d\nmov [rsi+rdx*4], eax\nadd rdx, 1\ncmp r8d, edx\njge short loc_12EC\nsub r8d, 1\njnb short loc_12E0\nloc_1314:\nmov eax, [r11]\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n int v3; // r8d\n unsigned int *v4; // rsi\n unsigned int *v5; // r9\n __int64 v6; // rdx\n signed int v7; // ecx\n unsigned int v8; // eax\n int v9; // edi\n unsigned int v10; // r10d\n unsigned int v11; // eax\n\n v3 = a2 - 1;\n if ( a2 - 1 >= 0 )\n {\n v4 = &a1[3 * a2];\n do\n {\n v5 = v4;\n v6 = 0LL;\n v4 -= 3;\n v7 = *v5;\n do\n {\n v8 = v4[v6];\n v9 = v7;\n v7 = v5[v6 + 1];\n v10 = v7 + v8;\n v11 = v9 + v8;\n if ( v9 <= v7 )\n v11 = v10;\n v4[v6++] = v11;\n }\n while ( v3 >= (int)v6 );\n }\n while ( v3-- != 0 );\n }\n return *a1;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\nmov r8d, esi\nmov r11, rdi\nsub r8d, 1\njs short loc_1314\nmovsxd rsi, esi\nlea rax, [rsi+rsi*2]\nlea rsi, [rdi+rax*4]\nnop dword ptr [rax+rax+00h]\nloc_12E0:\nmov r9, rsi\nxor edx, edx\nsub rsi, 0Ch\nmov ecx, [r9]\nloc_12EC:\nmov eax, [rsi+rdx*4]\nmov edi, ecx\nmov ecx, [r9+rdx*4+4]\nlea r10d, [rcx+rax]\nadd eax, edi\ncmp edi, ecx\ncmovle eax, r10d\nmov [rsi+rdx*4], eax\nadd rdx, 1\ncmp r8d, edx\njge short loc_12EC\nsub r8d, 1\njnb short loc_12E0\nloc_1314:\nmov eax, [r11]\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12C0(unsigned int *a1, int a2)\n{\n int v3; // r8d\n unsigned int *v4; // rsi\n unsigned int *v5; // r9\n __int64 v6; // rdx\n signed int v7; // ecx\n unsigned int v8; // eax\n int v9; // edi\n unsigned int v10; // r10d\n unsigned int v11; // eax\n\n v3 = a2 - 1;\n if ( a2 - 1 >= 0 )\n {\n v4 = &a1[3 * a2];\n do\n {\n v5 = v4;\n v6 = 0LL;\n v4 -= 3;\n v7 = *v5;\n do\n {\n v8 = v4[v6];\n v9 = v7;\n v7 = v5[v6 + 1];\n v10 = v7 + v8;\n v11 = v9 + v8;\n if ( v9 <= v7 )\n v11 = v10;\n v4[v6++] = v11;\n }\n while ( v3 >= (int)v6 );\n }\n while ( v3-- != 0 );\n }\n return *a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12C0(unsigned int *a1, int a2) {\n int v3;\n unsigned int *v4;\n unsigned int *v5;\n long long v6;\n signed int v7;\n unsigned int v8;\n int v9;\n unsigned int v10;\n unsigned int v11;\n v3 = a2 - 1;\n if (a2 - 1 >= 0) {\n v4 = &a1[3 * a2];\n do {\n v5 = v4;\n v6 = 0LL;\n v4 -= 3;\n v7 = *v5;\n do {\n v8 = v4[v6];\n v9 = v7;\n v7 = v5[v6 + 1];\n v10 = v7 + v8;\n v11 = v9 + v8;\n if (v9 <= v7) v11 = v10;\n v4[v6++] = v11;\n } while (v3 >= (int)v6);\n } while (v3-- != 0);\n }\n return *a1;\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n int v3;\n unsigned int *v4;\n unsigned int *v5;\n long long v6;\n signed int v7;\n unsigned int v8;\n int v9;\n unsigned int v10;\n unsigned int v11;\n v3 = a2 - 1;\n if (a2 - 1 >= 0) {\n v4 = &a1[3 * a2];\n do {\n v5 = v4;\n v6 = 0LL;\n v4 -= 3;\n v7 = *v5;\n do {\n v8 = v4[v6];\n v9 = v7;\n v7 = v5[v6 + 1];\n v10 = v7 + v8;\n v11 = v9 + v8;\n if (v9 <= v7) v11 = v10;\n v4[v6++] = v11;\n } while (v3 >= (int)v6);\n } while (v3-- != 0);\n }\n return *a1;\n}" + }, + { + "index": 147, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(int tri[3][3], int m, int n) {\n for (int i = m - 1; i >= 0; i--) {\n for (int j = 0; j <= i; j++) {\n if (tri[i + 1][j] > tri[i + 1][j + 1]) {\n tri[i][j] += tri[i + 1][j];\n } else {\n tri[i][j] += tri[i + 1][j + 1];\n }\n }\n }\n return tri[0][0];\n}", + "test": "int main() {\n\n int tri1[3][3] = {{1, 0, 0}, {4, 8, 0}, {1, 5, 3}};\n\n int tri2[3][3] = {{13, 0, 0}, {7, 4, 0}, {2, 4, 6}};\n\n int tri3[3][3] = {{2, 0, 0}, {11, 18, 0}, {21, 25, 33}};\n\n\n\n assert(func0(tri1, 2, 2) == 14);\n\n assert(func0(tri2, 2, 2) == 24);\n\n assert(func0(tri3, 2, 2) == 53);\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x1,%esi\njs 1378 \nmovslq %esi,%rax\nlea (%rax,%rax,2),%rax\nlea (%rdi,%rax,4),%rax\nnopl 0x0(%rax,%rax,1)\nmov (%rax),%edx\nmov 0xc(%rax),%r8d\nlea 0xc(%rax),%r10\nmov 0x10(%rax),%ecx\nlea (%rcx,%rdx,1),%r9d\nadd %r8d,%edx\ncmp %r8d,%ecx\ncmovge %r9d,%edx\nmov %edx,(%rax)\ntest %esi,%esi\nje 1368 \nmov 0x4(%rax),%edx\nmov 0x14(%rax),%r8d\nlea (%r8,%rdx,1),%r9d\nadd %ecx,%edx\ncmp %ecx,%r8d\ncmovge %r9d,%edx\nmov %edx,0x4(%rax)\ncmp $0x1,%esi\nje 1368 \nmov 0x8(%rax),%edx\nmov 0x18(%rax),%ecx\nlea (%rcx,%rdx,1),%r9d\nadd %r8d,%edx\ncmp %ecx,%r8d\ncmovle %r9d,%edx\nmov %edx,0x8(%rax)\ncmp $0x2,%esi\nje 1368 \nmov $0x3,%edx\nmov (%r10,%rdx,4),%r9d\nmov 0x4(%r10,%rdx,4),%r8d\nmov (%rax,%rdx,4),%ecx\nlea (%r9,%rcx,1),%r11d\nadd %r8d,%ecx\ncmp %r8d,%r9d\ncmovg %r11d,%ecx\nmov %ecx,(%rax,%rdx,4)\nadd $0x1,%rdx\ncmp %edx,%esi\njge 133e \nnopl 0x0(%rax,%rax,1)\nsub $0x1,%esi\nsub $0xc,%rax\ncmp $0xffffffff,%esi\njne 12e0 \nmov (%rdi),%eax\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmov eax, esi\nmov rcx, rdi\nsub eax, 1\njs loc_1561\ncdqe\npush r12\nlea rax, [rax+rax*2]\npush rbp\nlea rax, [rdi+rax*4]\nmov edi, esi\npush rbx\nlea rdx, [rax+0Ch]\nsub edi, 1\njz loc_1514\nnop\nloc_12F0:\nmov r8d, esi\nshr r8d, 1\nlea r9d, [r8-2]\ncmp r8d, 3\njbe loc_1550\nmovq xmm0, qword ptr [rax+0Ch]\nmovq xmm3, qword ptr [rax+10h]\nlea r10, [rax+18h]\nlea r11, [rax+24h]\nmovq xmm1, qword ptr [rax]\nmovq xmm2, qword ptr [rax+8]\nmov ebx, 3\nmovdqa xmm4, xmm0\npcmpgtd xmm0, xmm3\npaddd xmm4, xmm1\npaddd xmm1, xmm3\npand xmm4, xmm0\npandn xmm0, xmm1\nmovq xmm1, qword ptr [rax+18h]\npor xmm0, xmm4\nmovq qword ptr [rax], xmm0\nmovq xmm0, qword ptr [rax+14h]\nmovdqa xmm4, xmm0\npcmpgtd xmm0, xmm1\npaddd xmm4, xmm2\npaddd xmm2, xmm1\npand xmm4, xmm0\npandn xmm0, xmm2\nmovq xmm2, qword ptr [rax+20h]\npor xmm0, xmm4\nmovq qword ptr [rax+8], xmm0\nmovq xmm0, qword ptr [rax+1Ch]\nmovdqa xmm4, xmm0\npcmpgtd xmm0, xmm2\npaddd xmm4, xmm3\npaddd xmm3, xmm2\npand xmm4, xmm0\npandn xmm0, xmm3\npor xmm0, xmm4\nmovq qword ptr [rax+10h], xmm0\ncmp r9d, 4\njbe loc_1540\nloc_13A4:\nmovq xmm0, qword ptr [r11]\nmovq xmm3, qword ptr [r10+10h]\nmov ebp, ebx\nmov r12, r10\nadd ebp, 4\nadd r11, 18h\nadd r10, 18h\nadd ebx, 3\nmovdqa xmm4, xmm0\npcmpgtd xmm0, xmm3\npaddd xmm4, xmm1\npaddd xmm1, xmm3\npand xmm4, xmm0\npandn xmm0, xmm1\nmovq xmm1, qword ptr [r10]\npor xmm0, xmm4\nmovq qword ptr [r10-18h], xmm0\nmovq xmm0, qword ptr [r11-10h]\nmovdqa xmm4, xmm0\npcmpgtd xmm0, xmm1\npaddd xmm4, xmm2\npaddd xmm2, xmm1\npand xmm4, xmm0\npandn xmm0, xmm2\nmovq xmm2, qword ptr [r10+8]\npor xmm0, xmm4\nmovq qword ptr [r10-10h], xmm0\nmovq xmm0, qword ptr [r11-8]\nmovdqa xmm4, xmm0\npcmpgtd xmm0, xmm2\npaddd xmm4, xmm3\npaddd xmm3, xmm2\npand xmm4, xmm0\npandn xmm0, xmm3\npor xmm0, xmm4\nmovq qword ptr [r10-8], xmm0\ncmp ebp, r9d\njb loc_13A4\nlea r9, [r12+28h]\nloc_144D:\nmovq xmm0, qword ptr [r11]\nmovq xmm3, qword ptr [r9]\nadd ebx, 1\nmovq xmm1, qword ptr [r10]\nmovdqa xmm2, xmm0\npcmpgtd xmm0, xmm3\npaddd xmm2, xmm1\npaddd xmm1, xmm3\npand xmm2, xmm0\npandn xmm0, xmm1\npor xmm0, xmm2\nmovq qword ptr [r10], xmm0\ncmp ebx, r8d\njnb short loc_14CC\nxor ebp, ebp\nloc_1487:\nmovq xmm0, qword ptr [r11+rbp*8+8]\nmovq xmm3, qword ptr [r9+rbp*8+8]\nmovq xmm1, qword ptr [r10+rbp*8+8]\nmovdqa xmm2, xmm0\npcmpgtd xmm0, xmm3\npaddd xmm2, xmm1\npaddd xmm1, xmm3\npand xmm2, xmm0\npandn xmm0, xmm1\npor xmm0, xmm2\nmovq qword ptr [r10+rbp*8+8], xmm0\nadd rbp, 1\nlea r12d, [rbx+rbp]\ncmp r12d, r8d\njb short loc_1487\nloc_14CC:\ntest sil, 1\njz short loc_1530\nand esi, 0FFFFFFFEh\nloc_14D5:\nmovsxd rsi, esi\nshl rsi, 2\nadd rdx, rsi\nadd rsi, rax\nmov r9d, [rdx]\nmov r8d, [rdx+4]\nmov edx, [rsi]\nlea r10d, [r8+rdx]\nadd edx, r9d\ncmp r9d, r8d\ncmovle edx, r10d\nsub rax, 0Ch\nmov [rsi], edx\ntest edi, edi\njz short loc_1520\nmov esi, edi\nloc_1505:\nmov edi, esi\nlea rdx, [rax+0Ch]\nsub edi, 1\njnz loc_12F0\nloc_1514:\nxor esi, esi\njmp short loc_14D5\nloc_1520:\npop rbx\nmov eax, [rcx]\npop rbp\npop r12\nretn\nloc_1530:\nsub rax, 0Ch\nmov esi, edi\njmp short loc_1505\nloc_1540:\nlea r9, [rax+28h]\nmov ebx, 3\njmp loc_144D\nloc_1550:\nlea r9, [rax+10h]\nmov r10, rax\nmov r11, rdx\nxor ebx, ebx\njmp loc_144D\nloc_1561:\nmov eax, [rdi]\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, unsigned int i)\n{\n unsigned int *v3; // rax\n const __m128i *v4; // rdx\n unsigned int v5; // edi\n unsigned int v6; // r8d\n unsigned int v7; // r9d\n __m128i v8; // xmm3\n unsigned int *v9; // r10\n const __m128i *v10; // r11\n __m128i v11; // xmm1\n __m128i v12; // xmm2\n int v13; // ebx\n __m128i v14; // xmm4\n __m128i v15; // xmm0\n __m128i v16; // xmm4\n __m128i v17; // xmm0\n __m128i v18; // xmm1\n __m128i v19; // xmm4\n __m128i v20; // xmm0\n __m128i v21; // xmm4\n __m128i v22; // xmm0\n __m128i v23; // xmm2\n __m128i v24; // xmm4\n __m128i v25; // xmm0\n __m128i v26; // xmm0\n __m128i v27; // xmm3\n unsigned int *v28; // r12\n unsigned int v29; // ebp\n __m128i v30; // xmm4\n __m128i v31; // xmm0\n __m128i v32; // xmm4\n __m128i v33; // xmm0\n __m128i v34; // xmm4\n __m128i v35; // xmm0\n __m128i v36; // xmm4\n __m128i v37; // xmm0\n __m128i v38; // xmm4\n __m128i v39; // xmm0\n const __m128i *v40; // r9\n __m128i v41; // xmm3\n unsigned int v42; // ebx\n __m128i v43; // xmm1\n __m128i v44; // xmm2\n __m128i v45; // xmm0\n __int64 v46; // rbp\n __m128i v47; // xmm3\n __m128i v48; // xmm1\n __m128i v49; // xmm2\n __m128i v50; // xmm0\n signed int v51; // esi\n __int64 v52; // rsi\n __int32 *v53; // rdx\n int *v54; // rsi\n __int32 v55; // r9d\n __int32 v56; // r8d\n int v57; // edx\n\n if ( (int)(i - 1) < 0 )\n return *a1;\n v3 = &a1[3 * (i - 1)];\n v4 = (const __m128i *)(v3 + 3);\n v5 = i - 1;\n if ( i != 1 )\n goto LABEL_3;\n while ( 1 )\n {\n v51 = 0;\nLABEL_12:\n v52 = v51;\n v53 = &v4->m128i_i32[v52];\n v54 = (int *)&v3[v52];\n v55 = *v53;\n v56 = v53[1];\n v57 = *v53 + *v54;\n if ( v55 <= v56 )\n v57 = v56 + *v54;\n v3 -= 3;\n *v54 = v57;\n if ( !v5 )\n return *a1;\n for ( i = v5; ; i = v5 )\n {\n v4 = (const __m128i *)(v3 + 3);\n v5 = i - 1;\n if ( i == 1 )\n break;\nLABEL_3:\n v6 = i >> 1;\n v7 = (i >> 1) - 2;\n if ( i >> 1 <= 3 )\n {\n v40 = (const __m128i *)(v3 + 4);\n v9 = v3;\n v10 = v4;\n v13 = 0;\n }\n else\n {\n v8 = _mm_loadl_epi64((const __m128i *)v3 + 1);\n v9 = v3 + 6;\n v10 = (const __m128i *)(v3 + 9);\n v11 = _mm_loadl_epi64((const __m128i *)v3);\n v12 = _mm_loadl_epi64((const __m128i *)(v3 + 2));\n v13 = 3;\n v14 = _mm_loadl_epi64((const __m128i *)(v3 + 3));\n v15 = _mm_cmpgt_epi32(v14, v8);\n v16 = _mm_and_si128(_mm_add_epi32(v14, v11), v15);\n v17 = _mm_andnot_si128(v15, _mm_add_epi32(v11, v8));\n v18 = _mm_loadl_epi64((const __m128i *)(v3 + 6));\n *(_QWORD *)v3 = _mm_or_si128(v17, v16).m128i_u64[0];\n v19 = _mm_loadl_epi64((const __m128i *)(v3 + 5));\n v20 = _mm_cmpgt_epi32(v19, v18);\n v21 = _mm_and_si128(_mm_add_epi32(v19, v12), v20);\n v22 = _mm_andnot_si128(v20, _mm_add_epi32(v12, v18));\n v23 = _mm_loadl_epi64((const __m128i *)v3 + 2);\n *((_QWORD *)v3 + 1) = _mm_or_si128(v22, v21).m128i_u64[0];\n v24 = _mm_loadl_epi64((const __m128i *)(v3 + 7));\n v25 = _mm_cmpgt_epi32(v24, v23);\n *((_QWORD *)v3 + 2) = _mm_or_si128(\n _mm_andnot_si128(v25, _mm_add_epi32(v8, v23)),\n _mm_and_si128(_mm_add_epi32(v24, v8), v25)).m128i_u64[0];\n if ( v7 <= 4 )\n {\n v40 = (const __m128i *)(v3 + 10);\n v13 = 3;\n }\n else\n {\n do\n {\n v26 = _mm_loadl_epi64(v10);\n v27 = _mm_loadl_epi64((const __m128i *)v9 + 1);\n v28 = v9;\n v29 = v13 + 4;\n v10 = (const __m128i *)((char *)v10 + 24);\n v9 += 6;\n v13 += 3;\n v30 = v26;\n v31 = _mm_cmpgt_epi32(v26, v27);\n v32 = _mm_and_si128(_mm_add_epi32(v30, v18), v31);\n v33 = _mm_andnot_si128(v31, _mm_add_epi32(v18, v27));\n v18 = _mm_loadl_epi64((const __m128i *)v9);\n *((_QWORD *)v9 - 3) = _mm_or_si128(v33, v32).m128i_u64[0];\n v34 = _mm_loadl_epi64(v10 - 1);\n v35 = _mm_cmpgt_epi32(v34, v18);\n v36 = _mm_and_si128(_mm_add_epi32(v34, v23), v35);\n v37 = _mm_andnot_si128(v35, _mm_add_epi32(v23, v18));\n v23 = _mm_loadl_epi64((const __m128i *)(v9 + 2));\n *((_QWORD *)v9 - 2) = _mm_or_si128(v37, v36).m128i_u64[0];\n v38 = _mm_loadl_epi64((const __m128i *)((char *)v10 - 8));\n v39 = _mm_cmpgt_epi32(v38, v23);\n *((_QWORD *)v9 - 1) = _mm_or_si128(\n _mm_andnot_si128(v39, _mm_add_epi32(v27, v23)),\n _mm_and_si128(_mm_add_epi32(v38, v27), v39)).m128i_u64[0];\n }\n while ( v29 < v7 );\n v40 = (const __m128i *)(v28 + 10);\n }\n }\n v41 = _mm_loadl_epi64(v40);\n v42 = v13 + 1;\n v43 = _mm_loadl_epi64((const __m128i *)v9);\n v44 = _mm_loadl_epi64(v10);\n v45 = _mm_cmpgt_epi32(v44, v41);\n *(_QWORD *)v9 = _mm_or_si128(\n _mm_andnot_si128(v45, _mm_add_epi32(v43, v41)),\n _mm_and_si128(_mm_add_epi32(v44, v43), v45)).m128i_u64[0];\n if ( v42 < v6 )\n {\n v46 = 0LL;\n do\n {\n v47 = _mm_loadl_epi64((const __m128i *)&v40->m128i_u64[v46 + 1]);\n v48 = _mm_loadl_epi64((const __m128i *)&v9[2 * v46 + 2]);\n v49 = _mm_loadl_epi64((const __m128i *)&v10->m128i_u64[v46 + 1]);\n v50 = _mm_cmpgt_epi32(v49, v47);\n *(_QWORD *)&v9[2 * v46++ + 2] = _mm_or_si128(\n _mm_andnot_si128(v50, _mm_add_epi32(v48, v47)),\n _mm_and_si128(_mm_add_epi32(v49, v48), v50)).m128i_u64[0];\n }\n while ( v42 + (unsigned int)v46 < v6 );\n }\n if ( (i & 1) != 0 )\n {\n v51 = i & 0xFFFFFFFE;\n goto LABEL_12;\n }\n v3 -= 3;\n }\n }\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\nmov eax, esi\nmov rcx, rdi\nsub eax, 1\njs loc_1561\ncdqe\npush r12\nlea rax, [rax+rax*2]\npush rbp\nlea rax, [rdi+rax*4]\nmov edi, esi\npush rbx\nlea rdx, [rax+0Ch]\nsub edi, 1\njz loc_1514\nnop\nloc_12F0:\nmov r8d, esi\nshr r8d, 1\nlea r9d, [r8-2]\ncmp r8d, 3\njbe loc_1550\nmovq xmm0, qword ptr [rax+0Ch]\nmovq xmm3, qword ptr [rax+10h]\nlea r10, [rax+18h]\nlea r11, [rax+24h]\nmovq xmm1, qword ptr [rax]\nmovq xmm2, qword ptr [rax+8]\nmov ebx, 3\nmovdqa xmm4, xmm0\npcmpgtd xmm0, xmm3\npaddd xmm4, xmm1\npaddd xmm1, xmm3\npand xmm4, xmm0\npandn xmm0, xmm1\nmovq xmm1, qword ptr [rax+18h]\npor xmm0, xmm4\nmovq qword ptr [rax], xmm0\nmovq xmm0, qword ptr [rax+14h]\nmovdqa xmm4, xmm0\npcmpgtd xmm0, xmm1\npaddd xmm4, xmm2\npaddd xmm2, xmm1\npand xmm4, xmm0\npandn xmm0, xmm2\nmovq xmm2, qword ptr [rax+20h]\npor xmm0, xmm4\nmovq qword ptr [rax+8], xmm0\nmovq xmm0, qword ptr [rax+1Ch]\nmovdqa xmm4, xmm0\npcmpgtd xmm0, xmm2\npaddd xmm4, xmm3\npaddd xmm3, xmm2\npand xmm4, xmm0\npandn xmm0, xmm3\npor xmm0, xmm4\nmovq qword ptr [rax+10h], xmm0\ncmp r9d, 4\njbe loc_1540\nloc_13A4:\nmovq xmm0, qword ptr [r11]\nmovq xmm3, qword ptr [r10+10h]\nmov ebp, ebx\nmov r12, r10\nadd ebp, 4\nadd r11, 18h\nadd r10, 18h\nadd ebx, 3\nmovdqa xmm4, xmm0\npcmpgtd xmm0, xmm3\npaddd xmm4, xmm1\npaddd xmm1, xmm3\npand xmm4, xmm0\npandn xmm0, xmm1\nmovq xmm1, qword ptr [r10]\npor xmm0, xmm4\nmovq qword ptr [r10-18h], xmm0\nmovq xmm0, qword ptr [r11-10h]\nmovdqa xmm4, xmm0\npcmpgtd xmm0, xmm1\npaddd xmm4, xmm2\npaddd xmm2, xmm1\npand xmm4, xmm0\npandn xmm0, xmm2\nmovq xmm2, qword ptr [r10+8]\npor xmm0, xmm4\nmovq qword ptr [r10-10h], xmm0\nmovq xmm0, qword ptr [r11-8]\nmovdqa xmm4, xmm0\npcmpgtd xmm0, xmm2\npaddd xmm4, xmm3\npaddd xmm3, xmm2\npand xmm4, xmm0\npandn xmm0, xmm3\npor xmm0, xmm4\nmovq qword ptr [r10-8], xmm0\ncmp ebp, r9d\njb loc_13A4\nlea r9, [r12+28h]\nloc_144D:\nmovq xmm0, qword ptr [r11]\nmovq xmm3, qword ptr [r9]\nadd ebx, 1\nmovq xmm1, qword ptr [r10]\nmovdqa xmm2, xmm0\npcmpgtd xmm0, xmm3\npaddd xmm2, xmm1\npaddd xmm1, xmm3\npand xmm2, xmm0\npandn xmm0, xmm1\npor xmm0, xmm2\nmovq qword ptr [r10], xmm0\ncmp ebx, r8d\njnb short loc_14CC\nxor ebp, ebp\nloc_1487:\nmovq xmm0, qword ptr [r11+rbp*8+8]\nmovq xmm3, qword ptr [r9+rbp*8+8]\nmovq xmm1, qword ptr [r10+rbp*8+8]\nmovdqa xmm2, xmm0\npcmpgtd xmm0, xmm3\npaddd xmm2, xmm1\npaddd xmm1, xmm3\npand xmm2, xmm0\npandn xmm0, xmm1\npor xmm0, xmm2\nmovq qword ptr [r10+rbp*8+8], xmm0\nadd rbp, 1\nlea r12d, [rbx+rbp]\ncmp r12d, r8d\njb short loc_1487\nloc_14CC:\ntest sil, 1\njz short loc_1530\nand esi, 0FFFFFFFEh\nloc_14D5:\nmovsxd rsi, esi\nshl rsi, 2\nadd rdx, rsi\nadd rsi, rax\nmov r9d, [rdx]\nmov r8d, [rdx+4]\nmov edx, [rsi]\nlea r10d, [r8+rdx]\nadd edx, r9d\ncmp r9d, r8d\ncmovle edx, r10d\nsub rax, 0Ch\nmov [rsi], edx\ntest edi, edi\njz short loc_1520\nmov esi, edi\nloc_1505:\nmov edi, esi\nlea rdx, [rax+0Ch]\nsub edi, 1\njnz loc_12F0\nloc_1514:\nxor esi, esi\njmp short loc_14D5\nloc_1520:\npop rbx\nmov eax, [rcx]\npop rbp\npop r12\nretn\nloc_1530:\nsub rax, 0Ch\nmov esi, edi\njmp short loc_1505\nloc_1540:\nlea r9, [rax+28h]\nmov ebx, 3\njmp loc_144D\nloc_1550:\nlea r9, [rax+10h]\nmov r10, rax\nmov r11, rdx\nxor ebx, ebx\njmp loc_144D\nloc_1561:\nmov eax, [rdi]\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12C0(unsigned int *a1, unsigned int i)\n{\n unsigned int *v3; // rax\n const __m128i *v4; // rdx\n unsigned int v5; // edi\n unsigned int v6; // r8d\n unsigned int v7; // r9d\n __m128i v8; // xmm3\n unsigned int *v9; // r10\n const __m128i *v10; // r11\n __m128i v11; // xmm1\n __m128i v12; // xmm2\n int v13; // ebx\n __m128i v14; // xmm4\n __m128i v15; // xmm0\n __m128i v16; // xmm4\n __m128i v17; // xmm0\n __m128i v18; // xmm1\n __m128i v19; // xmm4\n __m128i v20; // xmm0\n __m128i v21; // xmm4\n __m128i v22; // xmm0\n __m128i v23; // xmm2\n __m128i v24; // xmm4\n __m128i v25; // xmm0\n __m128i v26; // xmm0\n __m128i v27; // xmm3\n unsigned int *v28; // r12\n unsigned int v29; // ebp\n __m128i v30; // xmm4\n __m128i v31; // xmm0\n __m128i v32; // xmm4\n __m128i v33; // xmm0\n __m128i v34; // xmm4\n __m128i v35; // xmm0\n __m128i v36; // xmm4\n __m128i v37; // xmm0\n __m128i v38; // xmm4\n __m128i v39; // xmm0\n const __m128i *v40; // r9\n __m128i v41; // xmm3\n unsigned int v42; // ebx\n __m128i v43; // xmm1\n __m128i v44; // xmm2\n __m128i v45; // xmm0\n __int64 v46; // rbp\n __m128i v47; // xmm3\n __m128i v48; // xmm1\n __m128i v49; // xmm2\n __m128i v50; // xmm0\n signed int v51; // esi\n __int64 v52; // rsi\n __int32 *v53; // rdx\n int *v54; // rsi\n __int32 v55; // r9d\n __int32 v56; // r8d\n int v57; // edx\n\n if ( (int)(i - 1) < 0 )\n return *a1;\n v3 = &a1[3 * (i - 1)];\n v4 = (const __m128i *)(v3 + 3);\n v5 = i - 1;\n if ( i != 1 )\n goto LABEL_3;\n while ( 1 )\n {\n v51 = 0;\nLABEL_12:\n v52 = v51;\n v53 = &v4->m128i_i32[v52];\n v54 = (int *)&v3[v52];\n v55 = *v53;\n v56 = v53[1];\n v57 = *v53 + *v54;\n if ( v55 <= v56 )\n v57 = v56 + *v54;\n v3 -= 3;\n *v54 = v57;\n if ( !v5 )\n return *a1;\n for ( i = v5; ; i = v5 )\n {\n v4 = (const __m128i *)(v3 + 3);\n v5 = i - 1;\n if ( i == 1 )\n break;\nLABEL_3:\n v6 = i >> 1;\n v7 = (i >> 1) - 2;\n if ( i >> 1 <= 3 )\n {\n v40 = (const __m128i *)(v3 + 4);\n v9 = v3;\n v10 = v4;\n v13 = 0;\n }\n else\n {\n v8 = _mm_loadl_epi64((const __m128i *)v3 + 1);\n v9 = v3 + 6;\n v10 = (const __m128i *)(v3 + 9);\n v11 = _mm_loadl_epi64((const __m128i *)v3);\n v12 = _mm_loadl_epi64((const __m128i *)(v3 + 2));\n v13 = 3;\n v14 = _mm_loadl_epi64((const __m128i *)(v3 + 3));\n v15 = _mm_cmpgt_epi32(v14, v8);\n v16 = _mm_and_si128(_mm_add_epi32(v14, v11), v15);\n v17 = _mm_andnot_si128(v15, _mm_add_epi32(v11, v8));\n v18 = _mm_loadl_epi64((const __m128i *)(v3 + 6));\n *(_QWORD *)v3 = _mm_or_si128(v17, v16).m128i_u64[0];\n v19 = _mm_loadl_epi64((const __m128i *)(v3 + 5));\n v20 = _mm_cmpgt_epi32(v19, v18);\n v21 = _mm_and_si128(_mm_add_epi32(v19, v12), v20);\n v22 = _mm_andnot_si128(v20, _mm_add_epi32(v12, v18));\n v23 = _mm_loadl_epi64((const __m128i *)v3 + 2);\n *((_QWORD *)v3 + 1) = _mm_or_si128(v22, v21).m128i_u64[0];\n v24 = _mm_loadl_epi64((const __m128i *)(v3 + 7));\n v25 = _mm_cmpgt_epi32(v24, v23);\n *((_QWORD *)v3 + 2) = _mm_or_si128(\n _mm_andnot_si128(v25, _mm_add_epi32(v8, v23)),\n _mm_and_si128(_mm_add_epi32(v24, v8), v25)).m128i_u64[0];\n if ( v7 <= 4 )\n {\n v40 = (const __m128i *)(v3 + 10);\n v13 = 3;\n }\n else\n {\n do\n {\n v26 = _mm_loadl_epi64(v10);\n v27 = _mm_loadl_epi64((const __m128i *)v9 + 1);\n v28 = v9;\n v29 = v13 + 4;\n v10 = (const __m128i *)((char *)v10 + 24);\n v9 += 6;\n v13 += 3;\n v30 = v26;\n v31 = _mm_cmpgt_epi32(v26, v27);\n v32 = _mm_and_si128(_mm_add_epi32(v30, v18), v31);\n v33 = _mm_andnot_si128(v31, _mm_add_epi32(v18, v27));\n v18 = _mm_loadl_epi64((const __m128i *)v9);\n *((_QWORD *)v9 - 3) = _mm_or_si128(v33, v32).m128i_u64[0];\n v34 = _mm_loadl_epi64(v10 - 1);\n v35 = _mm_cmpgt_epi32(v34, v18);\n v36 = _mm_and_si128(_mm_add_epi32(v34, v23), v35);\n v37 = _mm_andnot_si128(v35, _mm_add_epi32(v23, v18));\n v23 = _mm_loadl_epi64((const __m128i *)(v9 + 2));\n *((_QWORD *)v9 - 2) = _mm_or_si128(v37, v36).m128i_u64[0];\n v38 = _mm_loadl_epi64((const __m128i *)((char *)v10 - 8));\n v39 = _mm_cmpgt_epi32(v38, v23);\n *((_QWORD *)v9 - 1) = _mm_or_si128(\n _mm_andnot_si128(v39, _mm_add_epi32(v27, v23)),\n _mm_and_si128(_mm_add_epi32(v38, v27), v39)).m128i_u64[0];\n }\n while ( v29 < v7 );\n v40 = (const __m128i *)(v28 + 10);\n }\n }\n v41 = _mm_loadl_epi64(v40);\n v42 = v13 + 1;\n v43 = _mm_loadl_epi64((const __m128i *)v9);\n v44 = _mm_loadl_epi64(v10);\n v45 = _mm_cmpgt_epi32(v44, v41);\n *(_QWORD *)v9 = _mm_or_si128(\n _mm_andnot_si128(v45, _mm_add_epi32(v43, v41)),\n _mm_and_si128(_mm_add_epi32(v44, v43), v45)).m128i_u64[0];\n if ( v42 < v6 )\n {\n v46 = 0LL;\n do\n {\n v47 = _mm_loadl_epi64((const __m128i *)&v40->m128i_u64[v46 + 1]);\n v48 = _mm_loadl_epi64((const __m128i *)&v9[2 * v46 + 2]);\n v49 = _mm_loadl_epi64((const __m128i *)&v10->m128i_u64[v46 + 1]);\n v50 = _mm_cmpgt_epi32(v49, v47);\n *(_QWORD *)&v9[2 * v46++ + 2] = _mm_or_si128(\n _mm_andnot_si128(v50, _mm_add_epi32(v48, v47)),\n _mm_and_si128(_mm_add_epi32(v49, v48), v50)).m128i_u64[0];\n }\n while ( v42 + (unsigned int)v46 < v6 );\n }\n if ( (i & 1) != 0 )\n {\n v51 = i & 0xFFFFFFFE;\n goto LABEL_12;\n }\n v3 -= 3;\n }\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12C0(unsigned int *a1, unsigned int i) {\n unsigned int *v3;\n const __m128i *v4;\n unsigned int v5;\n unsigned int v6;\n unsigned int v7;\n __m128i v8;\n unsigned int *v9;\n const __m128i *v10;\n __m128i v11;\n __m128i v12;\n int v13;\n __m128i v14;\n __m128i v15;\n __m128i v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n __m128i v20;\n __m128i v21;\n __m128i v22;\n __m128i v23;\n __m128i v24;\n __m128i v25;\n __m128i v26;\n __m128i v27;\n unsigned int *v28;\n unsigned int v29;\n __m128i v30;\n __m128i v31;\n __m128i v32;\n __m128i v33;\n __m128i v34;\n __m128i v35;\n __m128i v36;\n __m128i v37;\n __m128i v38;\n __m128i v39;\n const __m128i *v40;\n __m128i v41;\n unsigned int v42;\n __m128i v43;\n __m128i v44;\n __m128i v45;\n long long v46;\n __m128i v47;\n __m128i v48;\n __m128i v49;\n __m128i v50;\n signed int v51;\n long long v52;\n int *v53;\n int *v54;\n int v55;\n int v56;\n int v57;\n if ((int)(i - 1) < 0) return *a1;\n v3 = &a1[3 * (i - 1)];\n v4 = (const __m128i *)(v3 + 3);\n v5 = i - 1;\n if (i != 1) goto LABEL_3;\n while (1) {\n v51 = 0;\n LABEL_12:\n v52 = v51;\n v53 = &v4->m128i_i32[v52];\n v54 = (int *)&v3[v52];\n v55 = *v53;\n v56 = v53[1];\n v57 = *v53 + *v54;\n if (v55 <= v56) v57 = v56 + *v54;\n v3 -= 3;\n *v54 = v57;\n if (!v5) return *a1;\n for (i = v5;; i = v5) {\n v4 = (const __m128i *)(v3 + 3);\n v5 = i - 1;\n if (i == 1) break;\n LABEL_3:\n v6 = i >> 1;\n v7 = (i >> 1) - 2;\n if (i >> 1 <= 3) {\n v40 = (const __m128i *)(v3 + 4);\n v9 = v3;\n v10 = v4;\n v13 = 0;\n } else {\n v8 = _mm_loadl_epi64((const __m128i *)v3 + 1);\n v9 = v3 + 6;\n v10 = (const __m128i *)(v3 + 9);\n v11 = _mm_loadl_epi64((const __m128i *)v3);\n v12 = _mm_loadl_epi64((const __m128i *)(v3 + 2));\n v13 = 3;\n v14 = _mm_loadl_epi64((const __m128i *)(v3 + 3));\n v15 = _mm_cmpgt_epi32(v14, v8);\n v16 = _mm_and_si128(_mm_add_epi32(v14, v11), v15);\n v17 = _mm_andnot_si128(v15, _mm_add_epi32(v11, v8));\n v18 = _mm_loadl_epi64((const __m128i *)(v3 + 6));\n *(uint64_t *)v3 = _mm_or_si128(v17, v16).m128i_u64[0];\n v19 = _mm_loadl_epi64((const __m128i *)(v3 + 5));\n v20 = _mm_cmpgt_epi32(v19, v18);\n v21 = _mm_and_si128(_mm_add_epi32(v19, v12), v20);\n v22 = _mm_andnot_si128(v20, _mm_add_epi32(v12, v18));\n v23 = _mm_loadl_epi64((const __m128i *)v3 + 2);\n *((uint64_t *)v3 + 1) = _mm_or_si128(v22, v21).m128i_u64[0];\n v24 = _mm_loadl_epi64((const __m128i *)(v3 + 7));\n v25 = _mm_cmpgt_epi32(v24, v23);\n *((uint64_t *)v3 + 2) =\n _mm_or_si128(_mm_andnot_si128(v25, _mm_add_epi32(v8, v23)),\n _mm_and_si128(_mm_add_epi32(v24, v8), v25))\n .m128i_u64[0];\n if (v7 <= 4) {\n v40 = (const __m128i *)(v3 + 10);\n v13 = 3;\n } else {\n do {\n v26 = _mm_loadl_epi64(v10);\n v27 = _mm_loadl_epi64((const __m128i *)v9 + 1);\n v28 = v9;\n v29 = v13 + 4;\n v10 = (const __m128i *)((char *)v10 + 24);\n v9 += 6;\n v13 += 3;\n v30 = v26;\n v31 = _mm_cmpgt_epi32(v26, v27);\n v32 = _mm_and_si128(_mm_add_epi32(v30, v18), v31);\n v33 = _mm_andnot_si128(v31, _mm_add_epi32(v18, v27));\n v18 = _mm_loadl_epi64((const __m128i *)v9);\n *((uint64_t *)v9 - 3) = _mm_or_si128(v33, v32).m128i_u64[0];\n v34 = _mm_loadl_epi64(v10 - 1);\n v35 = _mm_cmpgt_epi32(v34, v18);\n v36 = _mm_and_si128(_mm_add_epi32(v34, v23), v35);\n v37 = _mm_andnot_si128(v35, _mm_add_epi32(v23, v18));\n v23 = _mm_loadl_epi64((const __m128i *)(v9 + 2));\n *((uint64_t *)v9 - 2) = _mm_or_si128(v37, v36).m128i_u64[0];\n v38 = _mm_loadl_epi64((const __m128i *)((char *)v10 - 8));\n v39 = _mm_cmpgt_epi32(v38, v23);\n *((uint64_t *)v9 - 1) =\n _mm_or_si128(_mm_andnot_si128(v39, _mm_add_epi32(v27, v23)),\n _mm_and_si128(_mm_add_epi32(v38, v27), v39))\n .m128i_u64[0];\n } while (v29 < v7);\n v40 = (const __m128i *)(v28 + 10);\n }\n }\n v41 = _mm_loadl_epi64(v40);\n v42 = v13 + 1;\n v43 = _mm_loadl_epi64((const __m128i *)v9);\n v44 = _mm_loadl_epi64(v10);\n v45 = _mm_cmpgt_epi32(v44, v41);\n *(uint64_t *)v9 =\n _mm_or_si128(_mm_andnot_si128(v45, _mm_add_epi32(v43, v41)),\n _mm_and_si128(_mm_add_epi32(v44, v43), v45))\n .m128i_u64[0];\n if (v42 < v6) {\n v46 = 0LL;\n do {\n v47 = _mm_loadl_epi64((const __m128i *)&v40->m128i_u64[v46 + 1]);\n v48 = _mm_loadl_epi64((const __m128i *)&v9[2 * v46 + 2]);\n v49 = _mm_loadl_epi64((const __m128i *)&v10->m128i_u64[v46 + 1]);\n v50 = _mm_cmpgt_epi32(v49, v47);\n *(uint64_t *)&v9[2 * v46++ + 2] =\n _mm_or_si128(_mm_andnot_si128(v50, _mm_add_epi32(v48, v47)),\n _mm_and_si128(_mm_add_epi32(v49, v48), v50))\n .m128i_u64[0];\n } while (v42 + (unsigned int)v46 < v6);\n }\n if ((i & 1) != 0) {\n v51 = i & 4294967294;\n goto LABEL_12;\n }\n v3 -= 3;\n }\n }\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, unsigned int i) {\n unsigned int *v3;\n const __m128i *v4;\n unsigned int v5;\n unsigned int v6;\n unsigned int v7;\n __m128i v8;\n unsigned int *v9;\n const __m128i *v10;\n __m128i v11;\n __m128i v12;\n int v13;\n __m128i v14;\n __m128i v15;\n __m128i v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n __m128i v20;\n __m128i v21;\n __m128i v22;\n __m128i v23;\n __m128i v24;\n __m128i v25;\n __m128i v26;\n __m128i v27;\n unsigned int *v28;\n unsigned int v29;\n __m128i v30;\n __m128i v31;\n __m128i v32;\n __m128i v33;\n __m128i v34;\n __m128i v35;\n __m128i v36;\n __m128i v37;\n __m128i v38;\n __m128i v39;\n const __m128i *v40;\n __m128i v41;\n unsigned int v42;\n __m128i v43;\n __m128i v44;\n __m128i v45;\n long long v46;\n __m128i v47;\n __m128i v48;\n __m128i v49;\n __m128i v50;\n signed int v51;\n long long v52;\n int *v53;\n int *v54;\n int v55;\n int v56;\n int v57;\n if ((int)(i - 1) < 0) return *a1;\n v3 = &a1[3 * (i - 1)];\n v4 = (const __m128i *)(v3 + 3);\n v5 = i - 1;\n if (i != 1) goto LABEL_3;\n while (1) {\n v51 = 0;\n LABEL_12:\n v52 = v51;\n v53 = &v4->m128i_i32[v52];\n v54 = (int *)&v3[v52];\n v55 = *v53;\n v56 = v53[1];\n v57 = *v53 + *v54;\n if (v55 <= v56) v57 = v56 + *v54;\n v3 -= 3;\n *v54 = v57;\n if (!v5) return *a1;\n for (i = v5;; i = v5) {\n v4 = (const __m128i *)(v3 + 3);\n v5 = i - 1;\n if (i == 1) break;\n LABEL_3:\n v6 = i >> 1;\n v7 = (i >> 1) - 2;\n if (i >> 1 <= 3) {\n v40 = (const __m128i *)(v3 + 4);\n v9 = v3;\n v10 = v4;\n v13 = 0;\n } else {\n v8 = _mm_loadl_epi64((const __m128i *)v3 + 1);\n v9 = v3 + 6;\n v10 = (const __m128i *)(v3 + 9);\n v11 = _mm_loadl_epi64((const __m128i *)v3);\n v12 = _mm_loadl_epi64((const __m128i *)(v3 + 2));\n v13 = 3;\n v14 = _mm_loadl_epi64((const __m128i *)(v3 + 3));\n v15 = _mm_cmpgt_epi32(v14, v8);\n v16 = _mm_and_si128(_mm_add_epi32(v14, v11), v15);\n v17 = _mm_andnot_si128(v15, _mm_add_epi32(v11, v8));\n v18 = _mm_loadl_epi64((const __m128i *)(v3 + 6));\n *(uint64_t *)v3 = _mm_or_si128(v17, v16).m128i_u64[0];\n v19 = _mm_loadl_epi64((const __m128i *)(v3 + 5));\n v20 = _mm_cmpgt_epi32(v19, v18);\n v21 = _mm_and_si128(_mm_add_epi32(v19, v12), v20);\n v22 = _mm_andnot_si128(v20, _mm_add_epi32(v12, v18));\n v23 = _mm_loadl_epi64((const __m128i *)v3 + 2);\n *((uint64_t *)v3 + 1) = _mm_or_si128(v22, v21).m128i_u64[0];\n v24 = _mm_loadl_epi64((const __m128i *)(v3 + 7));\n v25 = _mm_cmpgt_epi32(v24, v23);\n *((uint64_t *)v3 + 2) =\n _mm_or_si128(_mm_andnot_si128(v25, _mm_add_epi32(v8, v23)),\n _mm_and_si128(_mm_add_epi32(v24, v8), v25))\n .m128i_u64[0];\n if (v7 <= 4) {\n v40 = (const __m128i *)(v3 + 10);\n v13 = 3;\n } else {\n do {\n v26 = _mm_loadl_epi64(v10);\n v27 = _mm_loadl_epi64((const __m128i *)v9 + 1);\n v28 = v9;\n v29 = v13 + 4;\n v10 = (const __m128i *)((char *)v10 + 24);\n v9 += 6;\n v13 += 3;\n v30 = v26;\n v31 = _mm_cmpgt_epi32(v26, v27);\n v32 = _mm_and_si128(_mm_add_epi32(v30, v18), v31);\n v33 = _mm_andnot_si128(v31, _mm_add_epi32(v18, v27));\n v18 = _mm_loadl_epi64((const __m128i *)v9);\n *((uint64_t *)v9 - 3) = _mm_or_si128(v33, v32).m128i_u64[0];\n v34 = _mm_loadl_epi64(v10 - 1);\n v35 = _mm_cmpgt_epi32(v34, v18);\n v36 = _mm_and_si128(_mm_add_epi32(v34, v23), v35);\n v37 = _mm_andnot_si128(v35, _mm_add_epi32(v23, v18));\n v23 = _mm_loadl_epi64((const __m128i *)(v9 + 2));\n *((uint64_t *)v9 - 2) = _mm_or_si128(v37, v36).m128i_u64[0];\n v38 = _mm_loadl_epi64((const __m128i *)((char *)v10 - 8));\n v39 = _mm_cmpgt_epi32(v38, v23);\n *((uint64_t *)v9 - 1) =\n _mm_or_si128(_mm_andnot_si128(v39, _mm_add_epi32(v27, v23)),\n _mm_and_si128(_mm_add_epi32(v38, v27), v39))\n .m128i_u64[0];\n } while (v29 < v7);\n v40 = (const __m128i *)(v28 + 10);\n }\n }\n v41 = _mm_loadl_epi64(v40);\n v42 = v13 + 1;\n v43 = _mm_loadl_epi64((const __m128i *)v9);\n v44 = _mm_loadl_epi64(v10);\n v45 = _mm_cmpgt_epi32(v44, v41);\n *(uint64_t *)v9 =\n _mm_or_si128(_mm_andnot_si128(v45, _mm_add_epi32(v43, v41)),\n _mm_and_si128(_mm_add_epi32(v44, v43), v45))\n .m128i_u64[0];\n if (v42 < v6) {\n v46 = 0LL;\n do {\n v47 = _mm_loadl_epi64((const __m128i *)&v40->m128i_u64[v46 + 1]);\n v48 = _mm_loadl_epi64((const __m128i *)&v9[2 * v46 + 2]);\n v49 = _mm_loadl_epi64((const __m128i *)&v10->m128i_u64[v46 + 1]);\n v50 = _mm_cmpgt_epi32(v49, v47);\n *(uint64_t *)&v9[2 * v46++ + 2] =\n _mm_or_si128(_mm_andnot_si128(v50, _mm_add_epi32(v48, v47)),\n _mm_and_si128(_mm_add_epi32(v49, v48), v50))\n .m128i_u64[0];\n } while (v42 + (unsigned int)v46 < v6);\n }\n if ((i & 1) != 0) {\n v51 = i & 4294967294;\n goto LABEL_12;\n }\n v3 -= 3;\n }\n }\n}" + }, + { + "index": 148, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\nint sum_digits_single(int x) {\n\n int ans = 0;\n\n while (x) {\n\n ans += x % 10;\n\n x /= 10;\n\n }\n\n return ans;\n\n}\n\n\n\nint closest(int x) {\n\n int ans = 0;\n\n while (ans * 10 + 9 <= x) {\n\n ans = ans * 10 + 9;\n\n }\n\n return ans;\n\n}\n\n\n\n", + "func": "int func0(int N) {\n int A = closest(N);\n return sum_digits_single(A) + sum_digits_single(N - A);\n}", + "test": "int main() {\n\n assert(func0(35) == 17);\n\n assert(func0(7) == 7);\n\n assert(func0(100) == 19);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x18,%rsp\nmov %edi,-0x1c(%rbp)\nmov -0x1c(%rbp),%eax\nmov %eax,%edi\ncallq 11b3 \nmov %eax,-0xc(%rbp)\nmov -0xc(%rbp),%eax\nmov %eax,%edi\ncallq 1149 \nmov %eax,%ebx\nmov -0x1c(%rbp),%eax\nsub -0xc(%rbp),%eax\nmov %eax,%edi\ncallq 1149 \nadd %ebx,%eax\nadd $0x18,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 18h\nmov [rbp+var_1C], edi\nmov eax, [rbp+var_1C]\nmov edi, eax\ncall closest\nmov [rbp+var_C], eax\nmov eax, [rbp+var_C]\nmov edi, eax\ncall sum_digits_single\nmov ebx, eax\nmov eax, [rbp+var_1C]\nsub eax, [rbp+var_C]\nmov edi, eax\ncall sum_digits_single\nadd eax, ebx\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1)\n{\n int v1; // ebx\n unsigned int v3; // [rsp+14h] [rbp-Ch]\n\n v3 = closest(a1);\n v1 = sum_digits_single(v3);\n return v1 + (unsigned int)sum_digits_single(a1 - v3);\n}", + "ida_strip_asm": "sub_11F2:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 18h\nmov [rbp+var_1C], edi\nmov eax, [rbp+var_1C]\nmov edi, eax\ncall sub_11B3\nmov [rbp+var_C], eax\nmov eax, [rbp+var_C]\nmov edi, eax\ncall sub_1149\nmov ebx, eax\nmov eax, [rbp+var_1C]\nsub eax, [rbp+var_C]\nmov edi, eax\ncall sub_1149\nadd eax, ebx\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11F2(unsigned int a1)\n{\n int v1; // ebx\n unsigned int v3; // [rsp+14h] [rbp-Ch]\n\n v3 = sub_11B3(a1);\n v1 = sub_1149(v3);\n return v1 + (unsigned int)sub_1149(a1 - v3);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11F2(unsigned int a1) {\n int v1;\n unsigned int v3;\n v3 = sub_11B3(a1);\n v1 = sub_1149(v3);\n return v1 + (unsigned int)sub_1149(a1 - v3);\n}", + "ida_pseudo_norm": "long long func0(unsigned int a1) {\n int v1;\n unsigned int v3;\n v3 = closest(a1);\n v1 = sum_digits_single(v3);\n return v1 + (unsigned int)sum_digits_single(a1 - v3);\n}" + }, + { + "index": 148, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\nint sum_digits_single(int x) {\n\n int ans = 0;\n\n while (x) {\n\n ans += x % 10;\n\n x /= 10;\n\n }\n\n return ans;\n\n}\n\n\n\nint closest(int x) {\n\n int ans = 0;\n\n while (ans * 10 + 9 <= x) {\n\n ans = ans * 10 + 9;\n\n }\n\n return ans;\n\n}\n\n\n\n", + "func": "int func0(int N) {\n int A = closest(N);\n return sum_digits_single(A) + sum_digits_single(N - A);\n}", + "test": "int main() {\n\n assert(func0(35) == 17);\n\n assert(func0(7) == 7);\n\n assert(func0(100) == 19);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmov %edi,%ebx\ncallq 1181 \nmov %eax,%r12d\nmov %eax,%edi\ncallq 1149 \nmov %eax,%ebp\nsub %r12d,%ebx\nmov %ebx,%edi\ncallq 1149 \nadd %ebp,%eax\npop %rbx\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov ebx, edi\ncall closest\nmov r12d, eax\nmov edi, eax\ncall sum_digits_single\nmov ebp, eax\nsub ebx, r12d\nmov edi, ebx\ncall sum_digits_single\nadd eax, ebp\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n __int64 v1; // r12\n int v2; // ebp\n\n v1 = (unsigned int)closest();\n v2 = sum_digits_single(v1);\n return v2 + (unsigned int)sum_digits_single((unsigned int)(a1 - v1));\n}", + "ida_strip_asm": "sub_11AA:\nendbr64\npush r12\npush rbp\npush rbx\nmov ebx, edi\ncall sub_1181\nmov r12d, eax\nmov edi, eax\ncall sub_1149\nmov ebp, eax\nsub ebx, r12d\nmov edi, ebx\ncall sub_1149\nadd eax, ebp\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11AA(int a1)\n{\n __int64 v1; // r12\n int v2; // ebp\n\n v1 = (unsigned int)sub_1181();\n v2 = sub_1149(v1);\n return v2 + (unsigned int)sub_1149((unsigned int)(a1 - v1));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11AA(int a1) {\n long long v1;\n int v2;\n v1 = (unsigned int)sub_1181();\n v2 = sub_1149(v1);\n return v2 + (unsigned int)sub_1149((unsigned int)(a1 - v1));\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n long long v1;\n int v2;\n v1 = (unsigned int)closest();\n v2 = sum_digits_single(v1);\n return v2 + (unsigned int)sum_digits_single((unsigned int)(a1 - v1));\n}" + }, + { + "index": 148, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\nint sum_digits_single(int x) {\n\n int ans = 0;\n\n while (x) {\n\n ans += x % 10;\n\n x /= 10;\n\n }\n\n return ans;\n\n}\n\n\n\nint closest(int x) {\n\n int ans = 0;\n\n while (ans * 10 + 9 <= x) {\n\n ans = ans * 10 + 9;\n\n }\n\n return ans;\n\n}\n\n\n\n", + "func": "int func0(int N) {\n int A = closest(N);\n return sum_digits_single(A) + sum_digits_single(N - A);\n}", + "test": "int main() {\n\n assert(func0(35) == 17);\n\n assert(func0(7) == 7);\n\n assert(func0(100) == 19);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x8,%edi\njle 12a8 \nxor %eax,%eax\nnopl 0x0(%rax,%rax,1)\nlea 0x9(%rax),%esi\nlea (%rsi,%rsi,4),%eax\nadd %eax,%eax\nlea 0x8(%rax),%edx\ncmp %edx,%edi\njg 1230 \nmov %esi,%edx\nxor %r8d,%r8d\nmov $0xcccccccd,%r9d\nnopw 0x0(%rax,%rax,1)\nmov %edx,%eax\nimul %r9,%rax\nshr $0x23,%rax\nlea (%rax,%rax,4),%ecx\nadd %ecx,%ecx\nsub %ecx,%edx\nadd %edx,%r8d\nmov %eax,%edx\ntest %eax,%eax\njne 1250 \nsub %esi,%edi\ntest %edi,%edi\nje 129f \nxor %ecx,%ecx\nnopw 0x0(%rax,%rax,1)\nmovslq %edi,%rax\nmov %edi,%edx\nimul $0x66666667,%rax,%rax\nsar $0x1f,%edx\nsar $0x22,%rax\nsub %edx,%eax\nlea (%rax,%rax,4),%edx\nadd %edx,%edx\nsub %edx,%edi\nadd %edi,%ecx\nmov %eax,%edi\ntest %eax,%eax\njne 1278 \nadd %ecx,%r8d\nmov %r8d,%eax\nretq\nnopl 0x0(%rax,%rax,1)\nxor %r8d,%r8d\njmp 126c \nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\nmov edx, edi\ncmp edi, 8\njle loc_12F0\nxor eax, eax\nnop dword ptr [rax+00000000h]\nloc_1278:\nlea r8d, [rax+9]\nlea eax, [r8+r8*4]\nadd eax, eax\nlea ecx, [rax+8]\ncmp edx, ecx\njg short loc_1278\nmov ecx, r8d\nxor edi, edi\nxchg ax, ax\nloc_1290:\nmovsxd rax, ecx\nmov esi, ecx\nimul rax, 66666667h\nsar esi, 1Fh\nsar rax, 22h\nsub eax, esi\nlea esi, [rax+rax*4]\nadd esi, esi\nsub ecx, esi\nadd edi, ecx\nmov ecx, eax\ntest eax, eax\njnz short loc_1290\nsub edx, r8d\nloc_12B7:\ntest edx, edx\njz short loc_12E6\nxor esi, esi\nnop dword ptr [rax]\nloc_12C0:\nmovsxd rax, edx\nmov ecx, edx\nimul rax, 66666667h\nsar ecx, 1Fh\nsar rax, 22h\nsub eax, ecx\nlea ecx, [rax+rax*4]\nadd ecx, ecx\nsub edx, ecx\nadd esi, edx\nmov edx, eax\ntest eax, eax\njnz short loc_12C0\nadd edi, esi\nloc_12E6:\nmov eax, edi\nretn\nloc_12F0:\nxor edi, edi\njmp short loc_12B7", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // edx\n int v2; // eax\n int v3; // r8d\n int v4; // ecx\n unsigned int v5; // edi\n int v6; // esi\n\n v1 = a1;\n if ( a1 <= 8 )\n {\n v5 = 0;\n }\n else\n {\n v2 = 0;\n do\n {\n v3 = v2 + 9;\n v2 = 10 * (v2 + 9);\n }\n while ( a1 > v2 + 8 );\n v4 = v3;\n v5 = 0;\n do\n {\n v5 += v4 % 10;\n v4 /= 10;\n }\n while ( v4 );\n v1 -= v3;\n }\n if ( v1 )\n {\n v6 = 0;\n do\n {\n v6 += v1 % 10;\n v1 /= 10;\n }\n while ( v1 );\n v5 += v6;\n }\n return v5;\n}", + "ida_strip_asm": "sub_1260:\nendbr64\nmov edx, edi\ncmp edi, 8\njle loc_12F0\nxor eax, eax\nnop dword ptr [rax+00000000h]\nloc_1278:\nlea r8d, [rax+9]\nlea eax, [r8+r8*4]\nadd eax, eax\nlea ecx, [rax+8]\ncmp edx, ecx\njg short loc_1278\nmov ecx, r8d\nxor edi, edi\nxchg ax, ax\nloc_1290:\nmovsxd rax, ecx\nmov esi, ecx\nimul rax, 66666667h\nsar esi, 1Fh\nsar rax, 22h\nsub eax, esi\nlea esi, [rax+rax*4]\nadd esi, esi\nsub ecx, esi\nadd edi, ecx\nmov ecx, eax\ntest eax, eax\njnz short loc_1290\nsub edx, r8d\nloc_12B7:\ntest edx, edx\njz short loc_12E6\nxor esi, esi\nnop dword ptr [rax]\nloc_12C0:\nmovsxd rax, edx\nmov ecx, edx\nimul rax, 66666667h\nsar ecx, 1Fh\nsar rax, 22h\nsub eax, ecx\nlea ecx, [rax+rax*4]\nadd ecx, ecx\nsub edx, ecx\nadd esi, edx\nmov edx, eax\ntest eax, eax\njnz short loc_12C0\nadd edi, esi\nloc_12E6:\nmov eax, edi\nretn\nloc_12F0:\nxor edi, edi\njmp short loc_12B7", + "ida_strip_pseudo": "__int64 __fastcall sub_1260(int a1)\n{\n int v1; // edx\n int v2; // eax\n int v3; // r8d\n int v4; // ecx\n unsigned int v5; // edi\n int v6; // esi\n\n v1 = a1;\n if ( a1 <= 8 )\n {\n v5 = 0;\n }\n else\n {\n v2 = 0;\n do\n {\n v3 = v2 + 9;\n v2 = 10 * (v2 + 9);\n }\n while ( a1 > v2 + 8 );\n v4 = v3;\n v5 = 0;\n do\n {\n v5 += v4 % 10;\n v4 /= 10;\n }\n while ( v4 );\n v1 -= v3;\n }\n if ( v1 )\n {\n v6 = 0;\n do\n {\n v6 += v1 % 10;\n v1 /= 10;\n }\n while ( v1 );\n v5 += v6;\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1260(int a1) {\n int v1;\n int v2;\n int v3;\n int v4;\n unsigned int v5;\n int v6;\n v1 = a1;\n if (a1 <= 8) {\n v5 = 0;\n } else {\n v2 = 0;\n do {\n v3 = v2 + 9;\n v2 = 10 * (v2 + 9);\n } while (a1 > v2 + 8);\n v4 = v3;\n v5 = 0;\n do {\n v5 += v4 % 10;\n v4 /= 10;\n } while (v4);\n v1 -= v3;\n }\n if (v1) {\n v6 = 0;\n do {\n v6 += v1 % 10;\n v1 /= 10;\n } while (v1);\n v5 += v6;\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v2;\n int v3;\n int v4;\n unsigned int v5;\n int v6;\n v1 = a1;\n if (a1 <= 8) {\n v5 = 0;\n } else {\n v2 = 0;\n do {\n v3 = v2 + 9;\n v2 = 10 * (v2 + 9);\n } while (a1 > v2 + 8);\n v4 = v3;\n v5 = 0;\n do {\n v5 += v4 % 10;\n v4 /= 10;\n } while (v4);\n v1 -= v3;\n }\n if (v1) {\n v6 = 0;\n do {\n v6 += v1 % 10;\n v1 /= 10;\n } while (v1);\n v5 += v6;\n }\n return v5;\n}" + }, + { + "index": 149, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int dp[n];\n for (int i = 0; i < n; i++) {\n dp[i] = 1;\n }\n for (int i = 0; i < n; i++) {\n for (int j = 0; j < i; j++) {\n if (arr[i] == arr[j] + 1 || arr[i] == arr[j] - 1) {\n if (dp[i] < dp[j] + 1) {\n dp[i] = dp[j] + 1;\n }\n }\n }\n }\n int result = 1;\n for (int i = 0; i < n; i++) {\n if (result < dp[i]) {\n result = dp[i];\n }\n }\n return result;\n}", + "test": "int main() {\n\n assert(func0((int[]){1, 2, 3, 4, 5, 3, 2}, 7) == 6);\n\n assert(func0((int[]){10, 9, 4, 5, 4, 8, 6}, 7) == 3);\n\n assert(func0((int[]){1, 2, 3, 2, 3, 7, 2, 1}, 8) == 7);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x48,%rsp\nmov %rdi,-0x48(%rbp)\nmov %esi,-0x4c(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmov %rsp,%rax\nmov %rax,%rsi\nmov -0x4c(%rbp),%eax\nmovslq %eax,%rdx\nsub $0x1,%rdx\nmov %rdx,-0x28(%rbp)\nmovslq %eax,%rdx\nmov %rdx,%r8\nmov $0x0,%r9d\nmovslq %eax,%rdx\nmov %rdx,%rcx\nmov $0x0,%ebx\ncltq\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%edi\nmov $0x0,%edx\ndiv %rdi\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rbx\nsub %rdx,%rbx\nmov %rbx,%rdx\ncmp %rdx,%rsp\nje 1228 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 1211 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 1252 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x20(%rbp)\nmovl $0x0,-0x30(%rbp)\njmp 1283 \nmov -0x20(%rbp),%rax\nmov -0x30(%rbp),%edx\nmovslq %edx,%rdx\nmovl $0x1,(%rax,%rdx,4)\naddl $0x1,-0x30(%rbp)\nmov -0x30(%rbp),%eax\ncmp -0x4c(%rbp),%eax\njl 126e \nmovl $0x0,-0x34(%rbp)\njmpq 135a \nmovl $0x0,-0x38(%rbp)\njmpq 134a \nmov -0x34(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov -0x38(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x48(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rdx),%edx\nadd $0x1,%edx\ncmp %edx,%eax\nje 130b \nmov -0x34(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov -0x38(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x48(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rdx),%edx\nsub $0x1,%edx\ncmp %edx,%eax\njne 1346 \nmov -0x20(%rbp),%rax\nmov -0x38(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%ecx\nmov -0x20(%rbp),%rax\nmov -0x34(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\ncmp %eax,%ecx\njl 1346 \nmov -0x20(%rbp),%rax\nmov -0x38(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nlea 0x1(%rax),%ecx\nmov -0x20(%rbp),%rax\nmov -0x34(%rbp),%edx\nmovslq %edx,%rdx\nmov %ecx,(%rax,%rdx,4)\naddl $0x1,-0x38(%rbp)\nmov -0x38(%rbp),%eax\ncmp -0x34(%rbp),%eax\njl 12a3 \naddl $0x1,-0x34(%rbp)\nmov -0x34(%rbp),%eax\ncmp -0x4c(%rbp),%eax\njl 1297 \nmovl $0x1,-0x3c(%rbp)\nmovl $0x0,-0x2c(%rbp)\njmp 139c \nmov -0x20(%rbp),%rax\nmov -0x2c(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\ncmp %eax,-0x3c(%rbp)\njge 1398 \nmov -0x20(%rbp),%rax\nmov -0x2c(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nmov %eax,-0x3c(%rbp)\naddl $0x1,-0x2c(%rbp)\nmov -0x2c(%rbp),%eax\ncmp -0x4c(%rbp),%eax\njl 1376 \nmov -0x3c(%rbp),%eax\nmov %rsi,%rsp\nmov -0x18(%rbp),%rdi\nxor %fs:0x28,%rdi\nje 13be \ncallq 1080 <__stack_chk_fail@plt>\nmov -0x8(%rbp),%rbx\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov eax, [rbp+var_3C]\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11F6:\ncmp rsp, rdx\njz short loc_120D\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_11F6\nloc_120D:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1237\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1237:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov [rbp+var_2C], 0\njmp short loc_1268\nloc_1253:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_2C]\nmovsxd rdx, edx\nmov dword ptr [rax+rdx*4], 1\nadd [rbp+var_2C], 1\nloc_1268:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_3C]\njl short loc_1253\nmov [rbp+var_28], 0\njmp loc_133D\nloc_127C:\nmov [rbp+var_24], 0\njmp loc_132D\nloc_1288:\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_24]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov eax, [rax]\nadd eax, 1\ncmp edx, eax\njz short loc_12EE\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_24]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov eax, [rax]\nsub eax, 1\ncmp edx, eax\njnz short loc_1329\nloc_12EE:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ncmp ecx, eax\njl short loc_1329\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nlea ecx, [rax+1]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nloc_1329:\nadd [rbp+var_24], 1\nloc_132D:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_28]\njl loc_1288\nadd [rbp+var_28], 1\nloc_133D:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_3C]\njl loc_127C\nmov [rbp+var_20], 1\nmov [rbp+var_1C], 0\njmp short loc_137F\nloc_1359:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ncmp [rbp+var_20], eax\njge short loc_137B\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov [rbp+var_20], eax\nloc_137B:\nadd [rbp+var_1C], 1\nloc_137F:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_3C]\njl short loc_1359\nmov eax, [rbp+var_20]\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_13A1\ncall ___stack_chk_fail\nlocret_13A1:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned __int64 v2; // rax\n void *v3; // rsp\n _BYTE v5[4]; // [rsp+8h] [rbp-40h] BYREF\n int v6; // [rsp+Ch] [rbp-3Ch]\n __int64 v7; // [rsp+10h] [rbp-38h]\n int i; // [rsp+1Ch] [rbp-2Ch]\n int j; // [rsp+20h] [rbp-28h]\n int k; // [rsp+24h] [rbp-24h]\n int v11; // [rsp+28h] [rbp-20h]\n int m; // [rsp+2Ch] [rbp-1Ch]\n __int64 v13; // [rsp+30h] [rbp-18h]\n _BYTE *v14; // [rsp+38h] [rbp-10h]\n unsigned __int64 v15; // [rsp+40h] [rbp-8h]\n\n v7 = a1;\n v6 = a2;\n v15 = __readfsqword(0x28u);\n v13 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 0x10uLL);\n while ( v5 != &v5[-(v2 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = alloca(v2 & 0xFFF);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)&v5[(v2 & 0xFFF) - 8] = *(_QWORD *)&v5[(v2 & 0xFFF) - 8];\n v14 = v5;\n for ( i = 0; i < v6; ++i )\n *(_DWORD *)&v14[4 * i] = 1;\n for ( j = 0; j < v6; ++j )\n {\n for ( k = 0; k < j; ++k )\n {\n if ( (*(_DWORD *)(4LL * j + v7) == *(_DWORD *)(4LL * k + v7) + 1\n || *(_DWORD *)(4LL * j + v7) == *(_DWORD *)(4LL * k + v7) - 1)\n && *(_DWORD *)&v14[4 * k] >= *(_DWORD *)&v14[4 * j] )\n {\n *(_DWORD *)&v14[4 * j] = *(_DWORD *)&v14[4 * k] + 1;\n }\n }\n }\n v11 = 1;\n for ( m = 0; m < v6; ++m )\n {\n if ( v11 < *(_DWORD *)&v14[4 * m] )\n v11 = *(_DWORD *)&v14[4 * m];\n }\n return (unsigned int)v11;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov eax, [rbp+var_3C]\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11F6:\ncmp rsp, rdx\njz short loc_120D\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_11F6\nloc_120D:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1237\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1237:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov [rbp+var_2C], 0\njmp short loc_1268\nloc_1253:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_2C]\nmovsxd rdx, edx\nmov dword ptr [rax+rdx*4], 1\nadd [rbp+var_2C], 1\nloc_1268:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_3C]\njl short loc_1253\nmov [rbp+var_28], 0\njmp loc_133D\nloc_127C:\nmov [rbp+var_24], 0\njmp loc_132D\nloc_1288:\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_24]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov eax, [rax]\nadd eax, 1\ncmp edx, eax\njz short loc_12EE\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_24]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov eax, [rax]\nsub eax, 1\ncmp edx, eax\njnz short loc_1329\nloc_12EE:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ncmp ecx, eax\njl short loc_1329\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nlea ecx, [rax+1]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nloc_1329:\nadd [rbp+var_24], 1\nloc_132D:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_28]\njl loc_1288\nadd [rbp+var_28], 1\nloc_133D:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_3C]\njl loc_127C\nmov [rbp+var_20], 1\nmov [rbp+var_1C], 0\njmp short loc_137F\nloc_1359:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ncmp [rbp+var_20], eax\njge short loc_137B\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov [rbp+var_20], eax\nloc_137B:\nadd [rbp+var_1C], 1\nloc_137F:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_3C]\njl short loc_1359\nmov eax, [rbp+var_20]\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_13A1\ncall ___stack_chk_fail\nlocret_13A1:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2)\n{\n unsigned __int64 v2; // rax\n void *v3; // rsp\n _BYTE v5[4]; // [rsp+8h] [rbp-40h] BYREF\n int v6; // [rsp+Ch] [rbp-3Ch]\n __int64 v7; // [rsp+10h] [rbp-38h]\n int i; // [rsp+1Ch] [rbp-2Ch]\n int j; // [rsp+20h] [rbp-28h]\n int k; // [rsp+24h] [rbp-24h]\n int v11; // [rsp+28h] [rbp-20h]\n int m; // [rsp+2Ch] [rbp-1Ch]\n __int64 v13; // [rsp+30h] [rbp-18h]\n _BYTE *v14; // [rsp+38h] [rbp-10h]\n unsigned __int64 v15; // [rsp+40h] [rbp-8h]\n\n v7 = a1;\n v6 = a2;\n v15 = __readfsqword(0x28u);\n v13 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 0x10uLL);\n while ( v5 != &v5[-(v2 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = alloca(v2 & 0xFFF);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)&v5[(v2 & 0xFFF) - 8] = *(_QWORD *)&v5[(v2 & 0xFFF) - 8];\n v14 = v5;\n for ( i = 0; i < v6; ++i )\n *(_DWORD *)&v14[4 * i] = 1;\n for ( j = 0; j < v6; ++j )\n {\n for ( k = 0; k < j; ++k )\n {\n if ( (*(_DWORD *)(4LL * j + v7) == *(_DWORD *)(4LL * k + v7) + 1\n || *(_DWORD *)(4LL * j + v7) == *(_DWORD *)(4LL * k + v7) - 1)\n && *(_DWORD *)&v14[4 * k] >= *(_DWORD *)&v14[4 * j] )\n {\n *(_DWORD *)&v14[4 * j] = *(_DWORD *)&v14[4 * k] + 1;\n }\n }\n }\n v11 = 1;\n for ( m = 0; m < v6; ++m )\n {\n if ( v11 < *(_DWORD *)&v14[4 * m] )\n v11 = *(_DWORD *)&v14[4 * m];\n }\n return (unsigned int)v11;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2) {\n unsigned long long v2;\n void *v3;\n uint8_t v5[4];\n int v6;\n long long v7;\n int i;\n int j;\n int k;\n int v11;\n int m;\n long long v13;\n uint8_t *v14;\n unsigned long long v15;\n v7 = a1;\n v6 = a2;\n v15 = __readfsqword(40u);\n v13 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 16uLL);\n while (v5 != &v5[-(v2 & 18446744073709547520LL)])\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)&v5[(v2 & 4095) - 8] = *(uint64_t *)&v5[(v2 & 4095) - 8];\n v14 = v5;\n for (i = 0; i < v6; ++i) *(uint32_t *)&v14[4 * i] = 1;\n for (j = 0; j < v6; ++j) {\n for (k = 0; k < j; ++k) {\n if ((*(uint32_t *)(4LL * j + v7) == *(uint32_t *)(4LL * k + v7) + 1 ||\n *(uint32_t *)(4LL * j + v7) == *(uint32_t *)(4LL * k + v7) - 1) &&\n *(uint32_t *)&v14[4 * k] >= *(uint32_t *)&v14[4 * j]) {\n *(uint32_t *)&v14[4 * j] = *(uint32_t *)&v14[4 * k] + 1;\n }\n }\n }\n v11 = 1;\n for (m = 0; m < v6; ++m) {\n if (v11 < *(uint32_t *)&v14[4 * m]) v11 = *(uint32_t *)&v14[4 * m];\n }\n return (unsigned int)v11;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned long long v2;\n void *v3;\n uint8_t v5[4];\n int v6;\n long long v7;\n int i;\n int j;\n int k;\n int v11;\n int m;\n long long v13;\n uint8_t *v14;\n unsigned long long v15;\n v7 = a1;\n v6 = a2;\n v15 = __readfsqword(40u);\n v13 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 16uLL);\n while (v5 != &v5[-(v2 & 18446744073709547520LL)])\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)&v5[(v2 & 4095) - 8] = *(uint64_t *)&v5[(v2 & 4095) - 8];\n v14 = v5;\n for (i = 0; i < v6; ++i) *(uint32_t *)&v14[4 * i] = 1;\n for (j = 0; j < v6; ++j) {\n for (k = 0; k < j; ++k) {\n if ((*(uint32_t *)(4LL * j + v7) == *(uint32_t *)(4LL * k + v7) + 1 ||\n *(uint32_t *)(4LL * j + v7) == *(uint32_t *)(4LL * k + v7) - 1) &&\n *(uint32_t *)&v14[4 * k] >= *(uint32_t *)&v14[4 * j]) {\n *(uint32_t *)&v14[4 * j] = *(uint32_t *)&v14[4 * k] + 1;\n }\n }\n }\n v11 = 1;\n for (m = 0; m < v6; ++m) {\n if (v11 < *(uint32_t *)&v14[4 * m]) v11 = *(uint32_t *)&v14[4 * m];\n }\n return (unsigned int)v11;\n}" + }, + { + "index": 149, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int dp[n];\n for (int i = 0; i < n; i++) {\n dp[i] = 1;\n }\n for (int i = 0; i < n; i++) {\n for (int j = 0; j < i; j++) {\n if (arr[i] == arr[j] + 1 || arr[i] == arr[j] - 1) {\n if (dp[i] < dp[j] + 1) {\n dp[i] = dp[j] + 1;\n }\n }\n }\n }\n int result = 1;\n for (int i = 0; i < n; i++) {\n if (result < dp[i]) {\n result = dp[i];\n }\n }\n return result;\n}", + "test": "int main() {\n\n assert(func0((int[]){1, 2, 3, 4, 5, 3, 2}, 7) == 6);\n\n assert(func0((int[]){10, 9, 4, 5, 4, 8, 6}, 7) == 3);\n\n assert(func0((int[]){1, 2, 3, 2, 3, 7, 2, 1}, 8) == 7);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r13\npush %r12\npush %rbx\nsub $0x18,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x28(%rbp)\nxor %eax,%eax\nmovslq %esi,%rax\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffffff0,%rdx\nand $0xfffffffffffff000,%rax\nmov %rsp,%rbx\nsub %rax,%rbx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 11e1 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11ca \nmov %rdx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 11f7 \norq $0x0,-0x8(%rsp,%rax,1)\nmov %rsp,%rax\nmov %rax,%r9\ntest %esi,%esi\njle 12ac \nmov %rax,%r11\nlea -0x1(%rsi),%r12d\nlea 0x4(%rax,%r12,4),%rbx\nmovl $0x1,(%rax)\nadd $0x4,%rax\ncmp %rbx,%rax\njne 1211 \nmov $0x0,%r8d\nmov $0x0,%r13d\njmp 126a \nmov (%r9,%rax,4),%edx\ncmp (%r9,%r8,4),%edx\njl 123f \nadd $0x1,%edx\nmov %edx,(%r9,%r8,4)\nlea 0x1(%rax),%rdx\ncmp %rax,%r10\nje 125e \nmov %rdx,%rax\nmov (%rdi,%rax,4),%edx\nlea 0x1(%rdx),%ecx\ncmp %ecx,%esi\nje 122e \nsub $0x1,%edx\ncmp %edx,%esi\njne 123f \njmp 122e \nlea 0x1(%r8),%rax\ncmp %r12,%r8\nje 127c \nmov %rax,%r8\ntest %r8d,%r8d\njle 125e \nmov (%rdi,%r8,4),%esi\nlea -0x1(%r8),%r10d\nmov %r13,%rax\njmp 124b \nmov $0x1,%eax\nmov (%r11),%edx\ncmp %edx,%eax\ncmovl %edx,%eax\nadd $0x4,%r11\ncmp %rbx,%r11\njne 1281 \nmov -0x28(%rbp),%rbx\nxor %fs:0x28,%rbx\njne 12b3 \nlea -0x18(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %rbp\nretq\nmov $0x1,%eax\njmp 1292 \ncallq 1080 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 10h\nmov r10, rdi\nmov r13d, esi\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nmovsxd r12, esi\nshl r12, 2\nlea rax, [r12+0Fh]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11D0:\ncmp rsp, rdx\njz short loc_11E7\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\njmp short loc_11D0\nloc_11E7:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11FD\nor [rsp+rax+30h+var_38], 0\nloc_11FD:\nmov rdi, rsp\ntest r13d, r13d\njle loc_12B2\nmov r11, rdi\nadd r12, rdi\nmov rax, rdi\nloc_1212:\nmov dword ptr [rax], 1\nadd rax, 4\ncmp rax, r12\njnz short loc_1212\nmov r8d, 0\nmov ebx, 0\nmov r14d, 0\njmp short loc_1267\nloc_1234:\nmov edx, [rdi+rax]\ncmp edx, [rdi+r9]\njl short loc_1244\nadd edx, 1\nmov [rdi+r9], edx\nloc_1244:\nlea rdx, [rax+4]\ncmp rax, r8\njz short loc_1264\nmov rax, rdx\nloc_1250:\nmov edx, [r10+rax]\nlea ecx, [rdx+1]\ncmp esi, ecx\njz short loc_1234\nsub edx, 1\ncmp esi, edx\njnz short loc_1244\njmp short loc_1234\nloc_1264:\nmov r8, r9\nloc_1267:\nadd ebx, 1\nlea r9, [r8+4]\ncmp r13d, ebx\njz short loc_1280\ntest ebx, ebx\njle short loc_1264\nmov esi, [r10+r9]\nmov rax, r14\njmp short loc_1250\nloc_1280:\nmov eax, 1\nloc_1285:\nmov edx, [r11]\ncmp eax, edx\ncmovl eax, edx\nadd r11, 4\ncmp r11, r12\njnz short loc_1285\nloc_1296:\nmov rdx, [rbp+var_28]\nsub rdx, fs:28h\njnz short loc_12B9\nlea rsp, [rbp-20h]\npop rbx\npop r12\npop r13\npop r14\npop rbp\nretn\nloc_12B2:\nmov eax, 1\njmp short loc_1296\nloc_12B9:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v3; // r12\n signed __int64 v4; // rax\n void *v5; // rsp\n _DWORD *v6; // r11\n _BYTE *v7; // r12\n _DWORD *v8; // rax\n __int64 v9; // r8\n int v10; // ebx\n int v11; // edx\n __int64 i; // rax\n int v13; // edx\n __int64 v14; // r9\n int v15; // esi\n __int64 result; // rax\n _BYTE v18[8]; // [rsp+8h] [rbp-30h] BYREF\n unsigned __int64 v19; // [rsp+10h] [rbp-28h]\n\n v19 = __readfsqword(0x28u);\n v3 = 4LL * a2;\n while ( v18 != &v18[-((v3 + 15) & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v4 = ((_WORD)v3 + 15) & 0xFF0;\n v5 = alloca(v4);\n if ( (((_WORD)v3 + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v18[v4 - 8] = *(_QWORD *)&v18[v4 - 8];\n if ( a2 <= 0 )\n return 1LL;\n v6 = v18;\n v7 = &v18[v3];\n v8 = v18;\n do\n *v8++ = 1;\n while ( v8 != (_DWORD *)v7 );\n v9 = 0LL;\n v10 = 0;\n while ( 1 )\n {\n ++v10;\n v14 = v9 + 4;\n if ( a2 == v10 )\n break;\n if ( v10 > 0 )\n {\n v15 = *(_DWORD *)(a1 + v14);\n for ( i = 0LL; ; i += 4LL )\n {\n v13 = *(_DWORD *)(a1 + i);\n if ( v15 == v13 + 1 || v15 == v13 - 1 )\n {\n v11 = *(_DWORD *)&v18[i];\n if ( v11 >= *(_DWORD *)&v18[v14] )\n *(_DWORD *)&v18[v14] = v11 + 1;\n }\n if ( i == v9 )\n break;\n }\n }\n v9 += 4LL;\n }\n result = 1LL;\n do\n {\n if ( (int)result < *v6 )\n result = (unsigned int)*v6;\n ++v6;\n }\n while ( v6 != (_DWORD *)v7 );\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 10h\nmov r10, rdi\nmov r13d, esi\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nmovsxd r12, esi\nshl r12, 2\nlea rax, [r12+0Fh]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11D0:\ncmp rsp, rdx\njz short loc_11E7\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\njmp short loc_11D0\nloc_11E7:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11FD\nor [rsp+rax+30h+var_38], 0\nloc_11FD:\nmov rdi, rsp\ntest r13d, r13d\njle loc_12B2\nmov r11, rdi\nadd r12, rdi\nmov rax, rdi\nloc_1212:\nmov dword ptr [rax], 1\nadd rax, 4\ncmp rax, r12\njnz short loc_1212\nmov r8d, 0\nmov ebx, 0\nmov r14d, 0\njmp short loc_1267\nloc_1234:\nmov edx, [rdi+rax]\ncmp edx, [rdi+r9]\njl short loc_1244\nadd edx, 1\nmov [rdi+r9], edx\nloc_1244:\nlea rdx, [rax+4]\ncmp rax, r8\njz short loc_1264\nmov rax, rdx\nloc_1250:\nmov edx, [r10+rax]\nlea ecx, [rdx+1]\ncmp esi, ecx\njz short loc_1234\nsub edx, 1\ncmp esi, edx\njnz short loc_1244\njmp short loc_1234\nloc_1264:\nmov r8, r9\nloc_1267:\nadd ebx, 1\nlea r9, [r8+4]\ncmp r13d, ebx\njz short loc_1280\ntest ebx, ebx\njle short loc_1264\nmov esi, [r10+r9]\nmov rax, r14\njmp short loc_1250\nloc_1280:\nmov eax, 1\nloc_1285:\nmov edx, [r11]\ncmp eax, edx\ncmovl eax, edx\nadd r11, 4\ncmp r11, r12\njnz short loc_1285\nloc_1296:\nmov rdx, [rbp+var_28]\nsub rdx, fs:28h\njnz short loc_12B9\nlea rsp, [rbp-20h]\npop rbx\npop r12\npop r13\npop r14\npop rbp\nretn\nloc_12B2:\nmov eax, 1\njmp short loc_1296\nloc_12B9:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2)\n{\n __int64 v3; // r12\n signed __int64 v4; // rax\n void *v5; // rsp\n _DWORD *v6; // r11\n _BYTE *v7; // r12\n _DWORD *v8; // rax\n __int64 v9; // r8\n int v10; // ebx\n int v11; // edx\n __int64 i; // rax\n int v13; // edx\n __int64 v14; // r9\n int v15; // esi\n __int64 result; // rax\n _BYTE v18[8]; // [rsp+8h] [rbp-30h] BYREF\n unsigned __int64 v19; // [rsp+10h] [rbp-28h]\n\n v19 = __readfsqword(0x28u);\n v3 = 4LL * a2;\n while ( v18 != &v18[-((v3 + 15) & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v4 = ((_WORD)v3 + 15) & 0xFF0;\n v5 = alloca(v4);\n if ( (((_WORD)v3 + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v18[v4 - 8] = *(_QWORD *)&v18[v4 - 8];\n if ( a2 <= 0 )\n return 1LL;\n v6 = v18;\n v7 = &v18[v3];\n v8 = v18;\n do\n *v8++ = 1;\n while ( v8 != (_DWORD *)v7 );\n v9 = 0LL;\n v10 = 0;\n while ( 1 )\n {\n ++v10;\n v14 = v9 + 4;\n if ( a2 == v10 )\n break;\n if ( v10 > 0 )\n {\n v15 = *(_DWORD *)(a1 + v14);\n for ( i = 0LL; ; i += 4LL )\n {\n v13 = *(_DWORD *)(a1 + i);\n if ( v15 == v13 + 1 || v15 == v13 - 1 )\n {\n v11 = *(_DWORD *)&v18[i];\n if ( v11 >= *(_DWORD *)&v18[v14] )\n *(_DWORD *)&v18[v14] = v11 + 1;\n }\n if ( i == v9 )\n break;\n }\n }\n v9 += 4LL;\n }\n result = 1LL;\n do\n {\n if ( (int)result < *v6 )\n result = (unsigned int)*v6;\n ++v6;\n }\n while ( v6 != (_DWORD *)v7 );\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2) {\n long long v3;\n signed long long v4;\n void *v5;\n uint32_t *v6;\n uint8_t *v7;\n uint32_t *v8;\n long long v9;\n int v10;\n int v11;\n long long i;\n int v13;\n long long v14;\n int v15;\n long long result;\n uint8_t v18[8];\n unsigned long long v19;\n v19 = __readfsqword(40u);\n v3 = 4LL * a2;\n while (v18 != &v18[-((v3 + 15) & 18446744073709547520LL)])\n ;\n v4 = ((unsigned short)v3 + 15) & 4080;\n v5 = alloca(v4);\n if ((((unsigned short)v3 + 15) & 4080) != 0)\n *(uint64_t *)&v18[v4 - 8] = *(uint64_t *)&v18[v4 - 8];\n if (a2 <= 0) return 1LL;\n v6 = v18;\n v7 = &v18[v3];\n v8 = v18;\n do\n *v8++ = 1;\n while (v8 != (uint32_t *)v7);\n v9 = 0LL;\n v10 = 0;\n while (1) {\n ++v10;\n v14 = v9 + 4;\n if (a2 == v10) break;\n if (v10 > 0) {\n v15 = *(uint32_t *)(a1 + v14);\n for (i = 0LL;; i += 4LL) {\n v13 = *(uint32_t *)(a1 + i);\n if (v15 == v13 + 1 || v15 == v13 - 1) {\n v11 = *(uint32_t *)&v18[i];\n if (v11 >= *(uint32_t *)&v18[v14]) *(uint32_t *)&v18[v14] = v11 + 1;\n }\n if (i == v9) break;\n }\n }\n v9 += 4LL;\n }\n result = 1LL;\n do {\n if ((int)result < *v6) result = (unsigned int)*v6;\n ++v6;\n } while (v6 != (uint32_t *)v7);\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v3;\n signed long long v4;\n void *v5;\n uint32_t *v6;\n uint8_t *v7;\n uint32_t *v8;\n long long v9;\n int v10;\n int v11;\n long long i;\n int v13;\n long long v14;\n int v15;\n long long result;\n uint8_t v18[8];\n unsigned long long v19;\n v19 = __readfsqword(40u);\n v3 = 4LL * a2;\n while (v18 != &v18[-((v3 + 15) & 18446744073709547520LL)])\n ;\n v4 = ((unsigned short)v3 + 15) & 4080;\n v5 = alloca(v4);\n if ((((unsigned short)v3 + 15) & 4080) != 0)\n *(uint64_t *)&v18[v4 - 8] = *(uint64_t *)&v18[v4 - 8];\n if (a2 <= 0) return 1LL;\n v6 = v18;\n v7 = &v18[v3];\n v8 = v18;\n do\n *v8++ = 1;\n while (v8 != (uint32_t *)v7);\n v9 = 0LL;\n v10 = 0;\n while (1) {\n ++v10;\n v14 = v9 + 4;\n if (a2 == v10) break;\n if (v10 > 0) {\n v15 = *(uint32_t *)(a1 + v14);\n for (i = 0LL;; i += 4LL) {\n v13 = *(uint32_t *)(a1 + i);\n if (v15 == v13 + 1 || v15 == v13 - 1) {\n v11 = *(uint32_t *)&v18[i];\n if (v11 >= *(uint32_t *)&v18[v14]) *(uint32_t *)&v18[v14] = v11 + 1;\n }\n if (i == v9) break;\n }\n }\n v9 += 4LL;\n }\n result = 1LL;\n do {\n if ((int)result < *v6) result = (unsigned int)*v6;\n ++v6;\n } while (v6 != (uint32_t *)v7);\n return result;\n}" + }, + { + "index": 149, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int dp[n];\n for (int i = 0; i < n; i++) {\n dp[i] = 1;\n }\n for (int i = 0; i < n; i++) {\n for (int j = 0; j < i; j++) {\n if (arr[i] == arr[j] + 1 || arr[i] == arr[j] - 1) {\n if (dp[i] < dp[j] + 1) {\n dp[i] = dp[j] + 1;\n }\n }\n }\n }\n int result = 1;\n for (int i = 0; i < n; i++) {\n if (result < dp[i]) {\n result = dp[i];\n }\n }\n return result;\n}", + "test": "int main() {\n\n assert(func0((int[]){1, 2, 3, 4, 5, 3, 2}, 7) == 6);\n\n assert(func0((int[]){10, 9, 4, 5, 4, 8, 6}, 7) == 3);\n\n assert(func0((int[]){1, 2, 3, 2, 3, 7, 2, 1}, 8) == 7);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r12\npush %rbx\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmovslq %esi,%rax\nmov %rsp,%rbx\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rbx\nand $0xfffffffffffffff0,%rdx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 1369 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 1354 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 1441 \nmov %rsp,%r9\ntest %esi,%esi\njle 144c \nlea -0x1(%rsi),%r12d\nmov %r9,%r11\nmov %r9,%rax\nlea 0x4(%r9,%r12,4),%rbx\nnopl (%rax)\nmovl $0x1,(%rax)\nadd $0x4,%rax\ncmp %rbx,%rax\njne 1398 \nxor %r8d,%r8d\nnopw 0x0(%rax,%rax,1)\ntest %r8,%r8\nje 13ff \nmov (%rdi,%r8,4),%esi\nlea -0x1(%r8),%r10d\nxor %eax,%eax\njmp 13db \nnopl 0x0(%rax)\nsub $0x1,%edx\ncmp %edx,%esi\nje 13e5 \nlea 0x1(%rax),%rdx\ncmp %rax,%r10\nje 13ff \nmov %rdx,%rax\nmov (%rdi,%rax,4),%edx\nlea 0x1(%rdx),%ecx\ncmp %ecx,%esi\njne 13c8 \nmov (%r9,%rax,4),%edx\ncmp (%r9,%r8,4),%edx\njl 13cf \nadd $0x1,%edx\nmov %edx,(%r9,%r8,4)\nlea 0x1(%rax),%rdx\ncmp %rax,%r10\njne 13d8 \nlea 0x1(%r8),%rax\ncmp %r12,%r8\nje 1410 \nmov %rax,%r8\njmp 13b0 \nnopl (%rax)\nmov $0x1,%eax\nnopl (%rax)\nmov (%r11),%edx\ncmp %edx,%eax\ncmovl %edx,%eax\nadd $0x4,%r11\ncmp %rbx,%r11\njne 1418 \nmov -0x18(%rbp),%rbx\nxor %fs:0x28,%rbx\njne 1453 \nlea -0x10(%rbp),%rsp\npop %rbx\npop %r12\npop %rbp\nretq\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 137b \nmov $0x1,%eax\njmp 1429 \ncallq 1080 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmovsxd rdx, esi\nmov r9, rdi\nmov rbp, rsp\npush r13\npush r12\nmov r12, rdx\nshl rdx, 2\npush rbx\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nlea rax, [rdx+0Fh]\nmov rsi, rsp\nmov rcx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rsi, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rsi\njz short loc_132E\nloc_1319:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rsi\njnz short loc_1319\nloc_132E:\nand ecx, 0FFFh\nsub rsp, rcx\ntest rcx, rcx\njnz loc_1432\nloc_1340:\nmov rdi, rsp\ntest r12d, r12d\njle loc_143D\nlea r13, [rdi+rdx]\nand edx, 4\nmov rbx, rdi\nmov rax, rdi\njz short loc_1370\nlea rax, [rdi+4]\nmov dword ptr [rdi], 1\ncmp rax, r13\njz short loc_1386\nnop word ptr [rax+rax+00h]\nloc_1370:\nmov dword ptr [rax], 1\nadd rax, 8\nmov dword ptr [rax-4], 1\ncmp rax, r13\njnz short loc_1370\nloc_1386:\nxor r11d, r11d\nxor r8d, r8d\nnop dword ptr [rax+00h]\nloc_1390:\nadd r11d, 1\nmov r10, r8\nadd r8, 4\ncmp r12d, r11d\njz short loc_13E0\nmov esi, [r9+r8]\nxor eax, eax\njmp short loc_13C3\nloc_13B0:\nsub edx, 1\ncmp esi, edx\njz short loc_13CE\nloc_13B7:\nlea rdx, [rax+4]\ncmp rax, r10\njz short loc_1390\nmov rax, rdx\nloc_13C3:\nmov edx, [r9+rax]\nlea ecx, [rdx+1]\ncmp esi, ecx\njnz short loc_13B0\nloc_13CE:\nmov edx, [rdi+rax]\ncmp edx, [rdi+r8]\njl short loc_13B7\nadd edx, 1\nmov [rdi+r8], edx\njmp short loc_13B7\nloc_13E0:\nmov rdx, r13\nmov eax, 1\nsub rdx, rdi\nand edx, 4\njz short loc_1400\nmov edx, [rdi]\nlea rbx, [rdi+4]\ncmp eax, edx\ncmovl eax, edx\ncmp rbx, r13\njz short loc_1418\nloc_1400:\nmov edx, [rbx]\ncmp eax, edx\ncmovl eax, edx\nmov edx, [rbx+4]\ncmp eax, edx\ncmovl eax, edx\nadd rbx, 8\ncmp rbx, r13\njnz short loc_1400\nloc_1418:\nmov rdx, [rbp+var_28]\nsub rdx, fs:28h\njnz short loc_1444\nlea rsp, [rbp-18h]\npop rbx\npop r12\npop r13\npop rbp\nretn\nloc_1432:\nor [rsp+rcx+1030h+var_1038], 0\njmp loc_1340\nloc_143D:\nmov eax, 1\njmp short loc_1418\nloc_1444:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v3; // rdx\n int *v4; // rsi\n signed __int64 v5; // rcx\n void *v6; // rsp\n int *v7; // r13\n int *v8; // rbx\n int *v9; // rax\n int v10; // r11d\n __int64 v11; // r8\n __int64 v12; // r10\n int v13; // esi\n __int64 i; // rax\n int v15; // edx\n int v16; // edx\n __int64 result; // rax\n int v18; // edx\n __int64 v19; // [rsp+0h] [rbp-1038h]\n int v20; // [rsp+8h] [rbp-1030h] BYREF\n _BYTE v21[4084]; // [rsp+Ch] [rbp-102Ch] BYREF\n _QWORD v22[6]; // [rsp+1008h] [rbp-30h] BYREF\n\n v3 = 4LL * a2;\n v22[1] = __readfsqword(0x28u);\n v4 = (int *)((char *)v22 - ((v3 + 15) & 0xFFFFFFFFFFFFF000LL));\n if ( v22 != (_QWORD *)v4 )\n {\n while ( &v20 != v4 )\n ;\n }\n v5 = ((_WORD)v3 + 15) & 0xFF0;\n v6 = alloca(v5);\n if ( (((_WORD)v3 + 15) & 0xFF0) != 0 )\n *(__int64 *)((char *)&v19 + v5) = *(__int64 *)((char *)&v19 + v5);\n if ( a2 <= 0 )\n return 1LL;\n v7 = (int *)&v21[v3 - 4];\n v8 = &v20;\n v9 = &v20;\n if ( (v3 & 4) == 0 || (v9 = (int *)v21, v20 = 1, v21 != (_BYTE *)v7) )\n {\n do\n {\n *v9 = 1;\n v9 += 2;\n *(v9 - 1) = 1;\n }\n while ( v9 != v7 );\n }\n v10 = 0;\n v11 = 0LL;\n while ( 1 )\n {\n ++v10;\n v12 = v11;\n v11 += 4LL;\n if ( a2 == v10 )\n break;\n v13 = *(_DWORD *)(a1 + v11);\n for ( i = 0LL; ; i += 4LL )\n {\n v15 = *(_DWORD *)(a1 + i);\n if ( v13 == v15 + 1 || v13 == v15 - 1 )\n {\n v16 = *(_DWORD *)&v21[i - 4];\n if ( v16 >= *(_DWORD *)&v21[v11 - 4] )\n *(_DWORD *)&v21[v11 - 4] = v16 + 1;\n }\n if ( i == v12 )\n break;\n }\n }\n result = 1LL;\n if ( (((_BYTE)v7 - (unsigned __int8)&v20) & 4) == 0 )\n goto LABEL_31;\n v8 = (int *)v21;\n if ( v20 > 1 )\n result = (unsigned int)v20;\n if ( v21 != (_BYTE *)v7 )\n {\nLABEL_31:\n do\n {\n if ( (int)result < *v8 )\n result = (unsigned int)*v8;\n v18 = v8[1];\n if ( (int)result < v18 )\n result = (unsigned int)v18;\n v8 += 2;\n }\n while ( v8 != v7 );\n }\n return result;\n}", + "ida_strip_asm": "sub_12D0:\nendbr64\npush rbp\nmovsxd rdx, esi\nmov r9, rdi\nmov rbp, rsp\npush r13\npush r12\nmov r12, rdx\nshl rdx, 2\npush rbx\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nlea rax, [rdx+0Fh]\nmov rsi, rsp\nmov rcx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rsi, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rsi\njz short loc_132E\nloc_1319:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rsi\njnz short loc_1319\nloc_132E:\nand ecx, 0FFFh\nsub rsp, rcx\ntest rcx, rcx\njnz loc_1432\nloc_1340:\nmov rdi, rsp\ntest r12d, r12d\njle loc_143D\nlea r13, [rdi+rdx]\nand edx, 4\nmov rbx, rdi\nmov rax, rdi\njz short loc_1370\nlea rax, [rdi+4]\nmov dword ptr [rdi], 1\ncmp rax, r13\njz short loc_1386\nnop word ptr [rax+rax+00h]\nloc_1370:\nmov dword ptr [rax], 1\nadd rax, 8\nmov dword ptr [rax-4], 1\ncmp rax, r13\njnz short loc_1370\nloc_1386:\nxor r11d, r11d\nxor r8d, r8d\nnop dword ptr [rax+00h]\nloc_1390:\nadd r11d, 1\nmov r10, r8\nadd r8, 4\ncmp r12d, r11d\njz short loc_13E0\nmov esi, [r9+r8]\nxor eax, eax\njmp short loc_13C3\nloc_13B0:\nsub edx, 1\ncmp esi, edx\njz short loc_13CE\nloc_13B7:\nlea rdx, [rax+4]\ncmp rax, r10\njz short loc_1390\nmov rax, rdx\nloc_13C3:\nmov edx, [r9+rax]\nlea ecx, [rdx+1]\ncmp esi, ecx\njnz short loc_13B0\nloc_13CE:\nmov edx, [rdi+rax]\ncmp edx, [rdi+r8]\njl short loc_13B7\nadd edx, 1\nmov [rdi+r8], edx\njmp short loc_13B7\nloc_13E0:\nmov rdx, r13\nmov eax, 1\nsub rdx, rdi\nand edx, 4\njz short loc_1400\nmov edx, [rdi]\nlea rbx, [rdi+4]\ncmp eax, edx\ncmovl eax, edx\ncmp rbx, r13\njz short loc_1418\nloc_1400:\nmov edx, [rbx]\ncmp eax, edx\ncmovl eax, edx\nmov edx, [rbx+4]\ncmp eax, edx\ncmovl eax, edx\nadd rbx, 8\ncmp rbx, r13\njnz short loc_1400\nloc_1418:\nmov rdx, [rbp+var_28]\nsub rdx, fs:28h\njnz short loc_1444\nlea rsp, [rbp-18h]\npop rbx\npop r12\npop r13\npop rbp\nretn\nloc_1432:\nor [rsp+rcx+1030h+var_1038], 0\njmp loc_1340\nloc_143D:\nmov eax, 1\njmp short loc_1418\nloc_1444:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12D0(__int64 a1, int a2)\n{\n __int64 v3; // rdx\n int *v4; // rsi\n signed __int64 v5; // rcx\n void *v6; // rsp\n int *v7; // r13\n int *v8; // rbx\n int *v9; // rax\n int v10; // r11d\n __int64 v11; // r8\n __int64 v12; // r10\n int v13; // esi\n __int64 i; // rax\n int v15; // edx\n int v16; // edx\n __int64 result; // rax\n int v18; // edx\n __int64 v19; // [rsp+0h] [rbp-1038h]\n int v20; // [rsp+8h] [rbp-1030h] BYREF\n _BYTE v21[4084]; // [rsp+Ch] [rbp-102Ch] BYREF\n _QWORD v22[6]; // [rsp+1008h] [rbp-30h] BYREF\n\n v3 = 4LL * a2;\n v22[1] = __readfsqword(0x28u);\n v4 = (int *)((char *)v22 - ((v3 + 15) & 0xFFFFFFFFFFFFF000LL));\n if ( v22 != (_QWORD *)v4 )\n {\n while ( &v20 != v4 )\n ;\n }\n v5 = ((_WORD)v3 + 15) & 0xFF0;\n v6 = alloca(v5);\n if ( (((_WORD)v3 + 15) & 0xFF0) != 0 )\n *(__int64 *)((char *)&v19 + v5) = *(__int64 *)((char *)&v19 + v5);\n if ( a2 <= 0 )\n return 1LL;\n v7 = (int *)&v21[v3 - 4];\n v8 = &v20;\n v9 = &v20;\n if ( (v3 & 4) == 0 || (v9 = (int *)v21, v20 = 1, v21 != (_BYTE *)v7) )\n {\n do\n {\n *v9 = 1;\n v9 += 2;\n *(v9 - 1) = 1;\n }\n while ( v9 != v7 );\n }\n v10 = 0;\n v11 = 0LL;\n while ( 1 )\n {\n ++v10;\n v12 = v11;\n v11 += 4LL;\n if ( a2 == v10 )\n break;\n v13 = *(_DWORD *)(a1 + v11);\n for ( i = 0LL; ; i += 4LL )\n {\n v15 = *(_DWORD *)(a1 + i);\n if ( v13 == v15 + 1 || v13 == v15 - 1 )\n {\n v16 = *(_DWORD *)&v21[i - 4];\n if ( v16 >= *(_DWORD *)&v21[v11 - 4] )\n *(_DWORD *)&v21[v11 - 4] = v16 + 1;\n }\n if ( i == v12 )\n break;\n }\n }\n result = 1LL;\n if ( (((_BYTE)v7 - (unsigned __int8)&v20) & 4) == 0 )\n goto LABEL_31;\n v8 = (int *)v21;\n if ( v20 > 1 )\n result = (unsigned int)v20;\n if ( v21 != (_BYTE *)v7 )\n {\nLABEL_31:\n do\n {\n if ( (int)result < *v8 )\n result = (unsigned int)*v8;\n v18 = v8[1];\n if ( (int)result < v18 )\n result = (unsigned int)v18;\n v8 += 2;\n }\n while ( v8 != v7 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12D0(long long a1, int a2) {\n long long v3;\n int *v4;\n signed long long v5;\n void *v6;\n int *v7;\n int *v8;\n int *v9;\n int v10;\n long long v11;\n long long v12;\n int v13;\n long long i;\n int v15;\n int v16;\n long long result;\n int v18;\n long long v19;\n int v20;\n uint8_t v21[4084];\n uint64_t v22[6];\n v3 = 4LL * a2;\n v22[1] = __readfsqword(40u);\n v4 = (int *)((char *)v22 - ((v3 + 15) & 18446744073709547520LL));\n if (v22 != (uint64_t *)v4) {\n while (&v20 != v4)\n ;\n }\n v5 = ((unsigned short)v3 + 15) & 4080;\n v6 = alloca(v5);\n if ((((unsigned short)v3 + 15) & 4080) != 0)\n *(long long *)((char *)&v19 + v5) = *(long long *)((char *)&v19 + v5);\n if (a2 <= 0) return 1LL;\n v7 = (int *)&v21[v3 - 4];\n v8 = &v20;\n v9 = &v20;\n if ((v3 & 4) == 0 || (v9 = (int *)v21, v20 = 1, v21 != (uint8_t *)v7)) {\n do {\n *v9 = 1;\n v9 += 2;\n *(v9 - 1) = 1;\n } while (v9 != v7);\n }\n v10 = 0;\n v11 = 0LL;\n while (1) {\n ++v10;\n v12 = v11;\n v11 += 4LL;\n if (a2 == v10) break;\n v13 = *(uint32_t *)(a1 + v11);\n for (i = 0LL;; i += 4LL) {\n v15 = *(uint32_t *)(a1 + i);\n if (v13 == v15 + 1 || v13 == v15 - 1) {\n v16 = *(uint32_t *)&v21[i - 4];\n if (v16 >= *(uint32_t *)&v21[v11 - 4])\n *(uint32_t *)&v21[v11 - 4] = v16 + 1;\n }\n if (i == v12) break;\n }\n }\n result = 1LL;\n if ((((uint8_t)v7 - (unsigned char)&v20) & 4) == 0) goto LABEL_31;\n v8 = (int *)v21;\n if (v20 > 1) result = (unsigned int)v20;\n if (v21 != (uint8_t *)v7) {\n LABEL_31:\n do {\n if ((int)result < *v8) result = (unsigned int)*v8;\n v18 = v8[1];\n if ((int)result < v18) result = (unsigned int)v18;\n v8 += 2;\n } while (v8 != v7);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v3;\n int *v4;\n signed long long v5;\n void *v6;\n int *v7;\n int *v8;\n int *v9;\n int v10;\n long long v11;\n long long v12;\n int v13;\n long long i;\n int v15;\n int v16;\n long long result;\n int v18;\n long long v19;\n int v20;\n uint8_t v21[4084];\n uint64_t v22[6];\n v3 = 4LL * a2;\n v22[1] = __readfsqword(40u);\n v4 = (int *)((char *)v22 - ((v3 + 15) & 18446744073709547520LL));\n if (v22 != (uint64_t *)v4) {\n while (&v20 != v4)\n ;\n }\n v5 = ((unsigned short)v3 + 15) & 4080;\n v6 = alloca(v5);\n if ((((unsigned short)v3 + 15) & 4080) != 0)\n *(long long *)((char *)&v19 + v5) = *(long long *)((char *)&v19 + v5);\n if (a2 <= 0) return 1LL;\n v7 = (int *)&v21[v3 - 4];\n v8 = &v20;\n v9 = &v20;\n if ((v3 & 4) == 0 || (v9 = (int *)v21, v20 = 1, v21 != (uint8_t *)v7)) {\n do {\n *v9 = 1;\n v9 += 2;\n *(v9 - 1) = 1;\n } while (v9 != v7);\n }\n v10 = 0;\n v11 = 0LL;\n while (1) {\n ++v10;\n v12 = v11;\n v11 += 4LL;\n if (a2 == v10) break;\n v13 = *(uint32_t *)(a1 + v11);\n for (i = 0LL;; i += 4LL) {\n v15 = *(uint32_t *)(a1 + i);\n if (v13 == v15 + 1 || v13 == v15 - 1) {\n v16 = *(uint32_t *)&v21[i - 4];\n if (v16 >= *(uint32_t *)&v21[v11 - 4])\n *(uint32_t *)&v21[v11 - 4] = v16 + 1;\n }\n if (i == v12) break;\n }\n }\n result = 1LL;\n if ((((uint8_t)v7 - (unsigned char)&v20) & 4) == 0) goto LABEL_31;\n v8 = (int *)v21;\n if (v20 > 1) result = (unsigned int)v20;\n if (v21 != (uint8_t *)v7) {\n LABEL_31:\n do {\n if ((int)result < *v8) result = (unsigned int)*v8;\n v18 = v8[1];\n if ((int)result < v18) result = (unsigned int)v18;\n v8 += 2;\n } while (v8 != v7);\n }\n return result;\n}" + }, + { + "index": 149, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int dp[n];\n for (int i = 0; i < n; i++) {\n dp[i] = 1;\n }\n for (int i = 0; i < n; i++) {\n for (int j = 0; j < i; j++) {\n if (arr[i] == arr[j] + 1 || arr[i] == arr[j] - 1) {\n if (dp[i] < dp[j] + 1) {\n dp[i] = dp[j] + 1;\n }\n }\n }\n }\n int result = 1;\n for (int i = 0; i < n; i++) {\n if (result < dp[i]) {\n result = dp[i];\n }\n }\n return result;\n}", + "test": "int main() {\n\n assert(func0((int[]){1, 2, 3, 4, 5, 3, 2}, 7) == 6);\n\n assert(func0((int[]){10, 9, 4, 5, 4, 8, 6}, 7) == 3);\n\n assert(func0((int[]){1, 2, 3, 2, 3, 7, 2, 1}, 8) == 7);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x18,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmovslq %esi,%rax\nmov %rsp,%rbx\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rbx\nand $0xfffffffffffffff0,%rdx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 1327 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 1312 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 14f5 \nlea 0x3(%rsp),%r10\nmov %r10,%r11\nand $0xfffffffffffffffc,%r10\nshr $0x2,%r11\ntest %esi,%esi\njle 1520 \nlea -0x1(%rsi),%ebx\ncmp $0x2,%ebx\njbe 1527 \nmov %esi,%edx\nmovdqa 0xd89(%rip),%xmm0\nmov %r10,%rax\nshr $0x2,%edx\nshl $0x4,%rdx\nadd %r10,%rdx\nnopl 0x0(%rax)\nmovups %xmm0,(%rax)\nadd $0x10,%rax\ncmp %rdx,%rax\njne 1378 \nmov %esi,%eax\nand $0xfffffffc,%eax\ntest $0x3,%sil\nje 13bd \nmovslq %eax,%rdx\nmovl $0x1,(%r10,%rdx,4)\nlea 0x1(%rax),%edx\ncmp %edx,%esi\njle 13bd \nmovslq %edx,%rdx\nadd $0x2,%eax\nmovl $0x1,(%r10,%rdx,4)\ncmp %eax,%esi\njle 13bd \ncltq\nmovl $0x1,(%r10,%rax,4)\nmov $0x1,%ecx\ncmp $0x1,%esi\nje 1500 \nnopl 0x0(%rax,%rax,1)\nmov (%rdi,%rcx,4),%r9d\nxor %eax,%eax\njmp 13f0 \nnopl 0x0(%rax,%rax,1)\nsub $0x1,%edx\ncmp %edx,%r9d\nje 13fc \nadd $0x1,%rax\ncmp %ecx,%eax\njge 1415 \nmov (%rdi,%rax,4),%edx\nlea 0x1(%rdx),%r8d\ncmp %r9d,%r8d\njne 13e0 \nmov (%r10,%rax,4),%edx\ncmp (%r10,%rcx,4),%edx\njl 13e8 \nadd $0x1,%edx\nadd $0x1,%rax\nmov %edx,(%r10,%rcx,4)\ncmp %ecx,%eax\njl 13f0 \nadd $0x1,%rcx\ncmp %ecx,%esi\njg 13d0 \ncmp $0x2,%ebx\njbe 152e \nmov %esi,%edx\nmovdqa 0xcc0(%rip),%xmm2\nmov %r10,%rax\nshr $0x2,%edx\nshl $0x4,%rdx\nadd %r10,%rdx\nnopl (%rax)\nmovdqu (%rax),%xmm0\nadd $0x10,%rax\nmovdqa %xmm0,%xmm1\npcmpgtd %xmm2,%xmm1\npand %xmm1,%xmm0\npandn %xmm2,%xmm1\nmovdqa %xmm1,%xmm2\npor %xmm0,%xmm2\ncmp %rdx,%rax\njne 1440 \nmovdqa %xmm2,%xmm1\nmov %esi,%edx\npsrldq $0x8,%xmm1\nand $0xfffffffc,%edx\nmovdqa %xmm1,%xmm0\npcmpgtd %xmm2,%xmm0\npand %xmm0,%xmm1\npandn %xmm2,%xmm0\npor %xmm0,%xmm1\nmovdqa %xmm1,%xmm2\npsrldq $0x4,%xmm2\nmovdqa %xmm2,%xmm0\npcmpgtd %xmm1,%xmm0\npand %xmm0,%xmm2\npandn %xmm1,%xmm0\npor %xmm2,%xmm0\nmovd %xmm0,%eax\ntest $0x3,%sil\nje 14e0 \nmovslq %edx,%rcx\nmov (%r10,%rcx,4),%ecx\ncmp %ecx,%eax\ncmovl %ecx,%eax\nadd $0x1,%edx\ncmp %edx,%esi\njle 14e0 \nmovslq %edx,%rcx\nmov (%r10,%rcx,4),%ecx\ncmp %ecx,%eax\ncmovl %ecx,%eax\nadd $0x1,%edx\ncmp %esi,%edx\njge 14e0 \nmovslq %edx,%rdx\nmov (%r10,%rdx,4),%edx\ncmp %edx,%eax\ncmovl %edx,%eax\nmov -0x18(%rbp),%rbx\nxor %fs:0x28,%rbx\njne 1550 \nmov -0x8(%rbp),%rbx\nleaveq\nretq\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 1339 \ncmp $0x2,%ebx\nja 1426 \nmov 0x0(,%r11,4),%eax\ntest %eax,%eax\nmov %esi,%eax\ncmovg 0x0(,%r11,4),%eax\njmp 14e0 \nmov $0x1,%eax\njmp 14e0 \nxor %eax,%eax\njmpq 138f \nmov 0x0(,%r11,4),%edx\nmov $0x1,%eax\ntest %edx,%edx\nmov $0x1,%edx\ncmovg 0x0(,%r11,4),%eax\njmpq 14c1 \ncallq 1080 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov r10, rdi\nmov r9d, esi\nmov rbp, rsp\npush r13\npush r12\npush rbx\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nmovsxd rax, esi\nmov rcx, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_132E\nloc_1319:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rcx\njnz short loc_1319\nloc_132E:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_151A\nloc_1340:\nlea rsi, [rsp+1030h+var_102D]\nmov r13, rsi\nand rsi, 0FFFFFFFFFFFFFFFCh\nshr r13, 2\nmov r11, rsi\ntest r9d, r9d\njle loc_1540\nlea ebx, [r9-1]\ncmp ebx, 2\njbe loc_1525\nmov edx, r9d\nmovdqa xmm0, cs:xmmword_20D0\nmov rax, rsi\nshr edx, 2\nshl rdx, 4\nlea rcx, [rsi+rdx]\nand edx, 10h\njz short loc_1398\nlea rax, [rsi+10h]\nmovups xmmword ptr [rsi], xmm0\ncmp rax, rcx\njz short loc_13A8\nnop dword ptr [rax+rax+00h]\nloc_1398:\nmovups xmmword ptr [rax], xmm0\nadd rax, 20h ; ' '\nmovups xmmword ptr [rax-10h], xmm0\ncmp rax, rcx\njnz short loc_1398\nloc_13A8:\nmov eax, r9d\nand eax, 0FFFFFFFCh\ntest r9b, 3\njz short loc_13DE\nmov edx, eax\nlea ecx, [rax+1]\nlea rdx, [rsi+rdx*4]\nmov dword ptr [rdx], 1\ncmp r9d, ecx\njle short loc_13DE\nloc_13C8:\nadd eax, 2\nmov dword ptr [rdx+4], 1\ncmp r9d, eax\njle short loc_13DE\nmov dword ptr [rdx+8], 1\nloc_13DE:\nmov r12d, r9d\nmov ecx, 1\nnop word ptr [rax+rax+00000000h]\nloc_13F0:\nmov r8d, [r10+rcx*4]\nxor eax, eax\njmp short loc_1410\nloc_1400:\nsub edx, 1\ncmp r8d, edx\njz short loc_141C\nloc_1408:\nadd rax, 1\ncmp eax, ecx\njge short loc_1432\nloc_1410:\nmov edx, [r10+rax*4]\nlea edi, [rdx+1]\ncmp edi, r8d\njnz short loc_1400\nloc_141C:\nmov edx, [rsi+rax*4]\ncmp [rsi+rcx*4], edx\njg short loc_1408\nadd edx, 1\nadd rax, 1\nmov [rsi+rcx*4], edx\ncmp eax, ecx\njl short loc_1410\nloc_1432:\nadd rcx, 1\ncmp rcx, r12\njnz short loc_13F0\ncmp ebx, 2\njbe loc_1547\nmov edx, r9d\nmovdqa xmm2, cs:xmmword_20D0\nmov rax, rsi\nshr edx, 2\nshl rdx, 4\nadd rdx, rsi\nnop dword ptr [rax+00h]\nloc_1460:\nmovdqu xmm0, xmmword ptr [rax]\nadd rax, 10h\nmovdqa xmm1, xmm0\npcmpgtd xmm1, xmm2\npand xmm0, xmm1\npandn xmm1, xmm2\nmovdqa xmm2, xmm1\npor xmm2, xmm0\ncmp rax, rdx\njnz short loc_1460\nmovdqa xmm0, xmm2\nmov edx, r9d\npsrldq xmm0, 8\nand edx, 0FFFFFFFCh\nmovdqa xmm1, xmm0\npcmpgtd xmm1, xmm2\npand xmm0, xmm1\npandn xmm1, xmm2\npor xmm1, xmm0\nmovdqa xmm2, xmm1\npsrldq xmm2, 4\nmovdqa xmm0, xmm2\npcmpgtd xmm0, xmm1\npand xmm2, xmm0\npandn xmm0, xmm1\npor xmm0, xmm2\nmovd eax, xmm0\ntest r9b, 3\njz short loc_1500\nmovsxd rcx, edx\nlea r11, [rsi+rcx*4]\nmov ecx, [r11]\ncmp eax, ecx\ncmovl eax, ecx\nlea ecx, [rdx+1]\ncmp r9d, ecx\njle short loc_1500\nloc_14E6:\nmov ecx, [r11+4]\ncmp eax, ecx\ncmovl eax, ecx\nadd edx, 2\ncmp r9d, edx\njle short loc_1500\nmov edx, [r11+8]\ncmp eax, edx\ncmovl eax, edx\nloc_1500:\nmov rdx, [rbp+var_28]\nsub rdx, fs:28h\njnz short loc_155D\nlea rsp, [rbp-18h]\npop rbx\npop r12\npop r13\npop rbp\nretn\nloc_151A:\nor [rsp+rdx+1030h+var_1038], 0\njmp loc_1340\nloc_1525:\nmov ds:dword_0[r13*4], 1\nmov rdx, rsi\nxor eax, eax\ncmp r9d, 1\njnz loc_13C8\nloc_1540:\nmov eax, 1\njmp short loc_1500\nloc_1547:\nmov eax, ds:dword_0[r13*4]\nmov edx, 1\ntest eax, eax\ncmovle eax, edx\nxor edx, edx\njmp short loc_14E6\nloc_155D:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // rdx\n __m128i *v3; // rcx\n __int16 v4; // dx\n signed __int64 v5; // rdx\n void *v6; // rsp\n int *v7; // r11\n __m128i si128; // xmm0\n __m128i *v9; // rax\n __int64 v10; // rdx\n __m128i *v11; // rcx\n int v12; // eax\n __m128i *v13; // rdx\n __int64 v14; // rcx\n int v15; // r8d\n __int64 v16; // rax\n int v17; // edx\n __int32 v18; // edx\n __m128i v19; // xmm2\n const __m128i *v20; // rax\n __m128i v21; // xmm0\n __m128i v22; // xmm1\n __m128i v23; // xmm0\n unsigned int v24; // edx\n __m128i v25; // xmm1\n __m128i v26; // xmm1\n __m128i v27; // xmm2\n __m128i v28; // xmm0\n __int64 result; // rax\n int v30; // ecx\n int v31; // edx\n __int64 v32; // [rsp+0h] [rbp-1038h]\n __m128i v33; // [rsp+8h] [rbp-1030h] BYREF\n _BYTE v34[4072]; // [rsp+18h] [rbp-1020h] BYREF\n _QWORD v35[6]; // [rsp+1008h] [rbp-30h] BYREF\n\n v35[1] = __readfsqword(0x28u);\n v2 = 4LL * a2 + 15;\n v3 = (__m128i *)((char *)v35 - (v2 & 0xFFFFFFFFFFFFF000LL));\n v4 = v2 & 0xFFF0;\n if ( v35 != (_QWORD *)v3 )\n {\n while ( &v33 != v3 )\n ;\n }\n v5 = v4 & 0xFFF;\n v6 = alloca(v5);\n if ( v5 )\n *(__int64 *)((char *)&v32 + v5) = *(__int64 *)((char *)&v32 + v5);\n v7 = (int *)&v33;\n if ( a2 <= 0 )\n return 1LL;\n if ( (unsigned int)(a2 - 1) > 2 )\n {\n si128 = _mm_load_si128((const __m128i *)&xmmword_20D0);\n v9 = &v33;\n v10 = 16LL * ((unsigned int)a2 >> 2);\n v11 = (__m128i *)((char *)&v33 + v10);\n if ( (v10 & 0x10) == 0 || (v9 = (__m128i *)v34, v33 = si128, v34 != (_BYTE *)v11) )\n {\n do\n {\n *v9 = si128;\n v9 += 2;\n v9[-1] = si128;\n }\n while ( v9 != v11 );\n }\n v12 = a2 & 0x7FFFFFFC;\n if ( (a2 & 3) == 0 )\n goto LABEL_14;\n v13 = (__m128i *)((char *)&v33 + 4 * (unsigned int)v12);\n v13->m128i_i32[0] = 1;\n if ( a2 <= v12 + 1 )\n goto LABEL_14;\n goto LABEL_12;\n }\n v33.m128i_i32[0] = 1;\n v13 = &v33;\n v12 = 0;\n if ( a2 == 1 )\n return 1LL;\nLABEL_12:\n v13->m128i_i32[1] = 1;\n if ( a2 > v12 + 2 )\n v13->m128i_i32[2] = 1;\nLABEL_14:\n v14 = 1LL;\n do\n {\n v15 = *(_DWORD *)(a1 + 4 * v14);\n v16 = 0LL;\n do\n {\n while ( 1 )\n {\n v17 = *(_DWORD *)(a1 + 4 * v16);\n if ( v17 + 1 == v15 || v15 == v17 - 1 )\n {\n v18 = v33.m128i_i32[v16];\n if ( v33.m128i_i32[v14] <= v18 )\n break;\n }\n if ( (int)++v16 >= (int)v14 )\n goto LABEL_21;\n }\n ++v16;\n v33.m128i_i32[v14] = v18 + 1;\n }\n while ( (int)v16 < (int)v14 );\nLABEL_21:\n ++v14;\n }\n while ( v14 != a2 );\n if ( (unsigned int)(a2 - 1) <= 2 )\n {\n result = v33.m128i_u32[0];\n if ( v33.m128i_i32[0] <= 0 )\n result = 1LL;\n v24 = 0;\n goto LABEL_29;\n }\n v19 = _mm_load_si128((const __m128i *)&xmmword_20D0);\n v20 = &v33;\n do\n {\n v21 = _mm_loadu_si128(v20++);\n v22 = _mm_cmpgt_epi32(v21, v19);\n v19 = _mm_or_si128(_mm_andnot_si128(v22, v19), _mm_and_si128(v21, v22));\n }\n while ( v20 != &v33 + ((unsigned int)a2 >> 2) );\n v23 = _mm_srli_si128(v19, 8);\n v24 = a2 & 0xFFFFFFFC;\n v25 = _mm_cmpgt_epi32(v23, v19);\n v26 = _mm_or_si128(_mm_andnot_si128(v25, v19), _mm_and_si128(v23, v25));\n v27 = _mm_srli_si128(v26, 4);\n v28 = _mm_cmpgt_epi32(v27, v26);\n result = (unsigned int)_mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v28, v26), _mm_and_si128(v27, v28)));\n if ( (a2 & 3) != 0 )\n {\n v7 = &v33.m128i_i32[v24];\n if ( (int)result < *v7 )\n result = (unsigned int)*v7;\n if ( a2 > (int)(v24 + 1) )\n {\nLABEL_29:\n v30 = v7[1];\n if ( (int)result < v30 )\n result = (unsigned int)v30;\n if ( a2 > (int)(v24 + 2) )\n {\n v31 = v7[2];\n if ( (int)result < v31 )\n return (unsigned int)v31;\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_12D0:\nendbr64\npush rbp\nmov r10, rdi\nmov r9d, esi\nmov rbp, rsp\npush r13\npush r12\npush rbx\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nmovsxd rax, esi\nmov rcx, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_132E\nloc_1319:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rcx\njnz short loc_1319\nloc_132E:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_151A\nloc_1340:\nlea rsi, [rsp+1030h+var_102D]\nmov r13, rsi\nand rsi, 0FFFFFFFFFFFFFFFCh\nshr r13, 2\nmov r11, rsi\ntest r9d, r9d\njle loc_1540\nlea ebx, [r9-1]\ncmp ebx, 2\njbe loc_1525\nmov edx, r9d\nmovdqa xmm0, cs:xmmword_20D0\nmov rax, rsi\nshr edx, 2\nshl rdx, 4\nlea rcx, [rsi+rdx]\nand edx, 10h\njz short loc_1398\nlea rax, [rsi+10h]\nmovups xmmword ptr [rsi], xmm0\ncmp rax, rcx\njz short loc_13A8\nnop dword ptr [rax+rax+00h]\nloc_1398:\nmovups xmmword ptr [rax], xmm0\nadd rax, 20h ; ' '\nmovups xmmword ptr [rax-10h], xmm0\ncmp rax, rcx\njnz short loc_1398\nloc_13A8:\nmov eax, r9d\nand eax, 0FFFFFFFCh\ntest r9b, 3\njz short loc_13DE\nmov edx, eax\nlea ecx, [rax+1]\nlea rdx, [rsi+rdx*4]\nmov dword ptr [rdx], 1\ncmp r9d, ecx\njle short loc_13DE\nloc_13C8:\nadd eax, 2\nmov dword ptr [rdx+4], 1\ncmp r9d, eax\njle short loc_13DE\nmov dword ptr [rdx+8], 1\nloc_13DE:\nmov r12d, r9d\nmov ecx, 1\nnop word ptr [rax+rax+00000000h]\nloc_13F0:\nmov r8d, [r10+rcx*4]\nxor eax, eax\njmp short loc_1410\nloc_1400:\nsub edx, 1\ncmp r8d, edx\njz short loc_141C\nloc_1408:\nadd rax, 1\ncmp eax, ecx\njge short loc_1432\nloc_1410:\nmov edx, [r10+rax*4]\nlea edi, [rdx+1]\ncmp edi, r8d\njnz short loc_1400\nloc_141C:\nmov edx, [rsi+rax*4]\ncmp [rsi+rcx*4], edx\njg short loc_1408\nadd edx, 1\nadd rax, 1\nmov [rsi+rcx*4], edx\ncmp eax, ecx\njl short loc_1410\nloc_1432:\nadd rcx, 1\ncmp rcx, r12\njnz short loc_13F0\ncmp ebx, 2\njbe loc_1547\nmov edx, r9d\nmovdqa xmm2, cs:xmmword_20D0\nmov rax, rsi\nshr edx, 2\nshl rdx, 4\nadd rdx, rsi\nnop dword ptr [rax+00h]\nloc_1460:\nmovdqu xmm0, xmmword ptr [rax]\nadd rax, 10h\nmovdqa xmm1, xmm0\npcmpgtd xmm1, xmm2\npand xmm0, xmm1\npandn xmm1, xmm2\nmovdqa xmm2, xmm1\npor xmm2, xmm0\ncmp rax, rdx\njnz short loc_1460\nmovdqa xmm0, xmm2\nmov edx, r9d\npsrldq xmm0, 8\nand edx, 0FFFFFFFCh\nmovdqa xmm1, xmm0\npcmpgtd xmm1, xmm2\npand xmm0, xmm1\npandn xmm1, xmm2\npor xmm1, xmm0\nmovdqa xmm2, xmm1\npsrldq xmm2, 4\nmovdqa xmm0, xmm2\npcmpgtd xmm0, xmm1\npand xmm2, xmm0\npandn xmm0, xmm1\npor xmm0, xmm2\nmovd eax, xmm0\ntest r9b, 3\njz short loc_1500\nmovsxd rcx, edx\nlea r11, [rsi+rcx*4]\nmov ecx, [r11]\ncmp eax, ecx\ncmovl eax, ecx\nlea ecx, [rdx+1]\ncmp r9d, ecx\njle short loc_1500\nloc_14E6:\nmov ecx, [r11+4]\ncmp eax, ecx\ncmovl eax, ecx\nadd edx, 2\ncmp r9d, edx\njle short loc_1500\nmov edx, [r11+8]\ncmp eax, edx\ncmovl eax, edx\nloc_1500:\nmov rdx, [rbp+var_28]\nsub rdx, fs:28h\njnz short loc_155D\nlea rsp, [rbp-18h]\npop rbx\npop r12\npop r13\npop rbp\nretn\nloc_151A:\nor [rsp+rdx+1030h+var_1038], 0\njmp loc_1340\nloc_1525:\nmov ds:dword_0[r13*4], 1\nmov rdx, rsi\nxor eax, eax\ncmp r9d, 1\njnz loc_13C8\nloc_1540:\nmov eax, 1\njmp short loc_1500\nloc_1547:\nmov eax, ds:dword_0[r13*4]\nmov edx, 1\ntest eax, eax\ncmovle eax, edx\nxor edx, edx\njmp short loc_14E6\nloc_155D:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12D0(__int64 a1, int a2)\n{\n __int64 v2; // rdx\n __m128i *v3; // rcx\n __int16 v4; // dx\n signed __int64 v5; // rdx\n void *v6; // rsp\n int *v7; // r11\n __m128i si128; // xmm0\n __m128i *v9; // rax\n __int64 v10; // rdx\n __m128i *v11; // rcx\n int v12; // eax\n __m128i *v13; // rdx\n __int64 v14; // rcx\n int v15; // r8d\n __int64 v16; // rax\n int v17; // edx\n __int32 v18; // edx\n __m128i v19; // xmm2\n const __m128i *v20; // rax\n __m128i v21; // xmm0\n __m128i v22; // xmm1\n __m128i v23; // xmm0\n unsigned int v24; // edx\n __m128i v25; // xmm1\n __m128i v26; // xmm1\n __m128i v27; // xmm2\n __m128i v28; // xmm0\n __int64 result; // rax\n int v30; // ecx\n int v31; // edx\n __int64 v32; // [rsp+0h] [rbp-1038h]\n __m128i v33; // [rsp+8h] [rbp-1030h] BYREF\n _BYTE v34[4072]; // [rsp+18h] [rbp-1020h] BYREF\n _QWORD v35[6]; // [rsp+1008h] [rbp-30h] BYREF\n\n v35[1] = __readfsqword(0x28u);\n v2 = 4LL * a2 + 15;\n v3 = (__m128i *)((char *)v35 - (v2 & 0xFFFFFFFFFFFFF000LL));\n v4 = v2 & 0xFFF0;\n if ( v35 != (_QWORD *)v3 )\n {\n while ( &v33 != v3 )\n ;\n }\n v5 = v4 & 0xFFF;\n v6 = alloca(v5);\n if ( v5 )\n *(__int64 *)((char *)&v32 + v5) = *(__int64 *)((char *)&v32 + v5);\n v7 = (int *)&v33;\n if ( a2 <= 0 )\n return 1LL;\n if ( (unsigned int)(a2 - 1) > 2 )\n {\n si128 = _mm_load_si128((const __m128i *)&xmmword_20D0);\n v9 = &v33;\n v10 = 16LL * ((unsigned int)a2 >> 2);\n v11 = (__m128i *)((char *)&v33 + v10);\n if ( (v10 & 0x10) == 0 || (v9 = (__m128i *)v34, v33 = si128, v34 != (_BYTE *)v11) )\n {\n do\n {\n *v9 = si128;\n v9 += 2;\n v9[-1] = si128;\n }\n while ( v9 != v11 );\n }\n v12 = a2 & 0x7FFFFFFC;\n if ( (a2 & 3) == 0 )\n goto LABEL_14;\n v13 = (__m128i *)((char *)&v33 + 4 * (unsigned int)v12);\n v13->m128i_i32[0] = 1;\n if ( a2 <= v12 + 1 )\n goto LABEL_14;\n goto LABEL_12;\n }\n v33.m128i_i32[0] = 1;\n v13 = &v33;\n v12 = 0;\n if ( a2 == 1 )\n return 1LL;\nLABEL_12:\n v13->m128i_i32[1] = 1;\n if ( a2 > v12 + 2 )\n v13->m128i_i32[2] = 1;\nLABEL_14:\n v14 = 1LL;\n do\n {\n v15 = *(_DWORD *)(a1 + 4 * v14);\n v16 = 0LL;\n do\n {\n while ( 1 )\n {\n v17 = *(_DWORD *)(a1 + 4 * v16);\n if ( v17 + 1 == v15 || v15 == v17 - 1 )\n {\n v18 = v33.m128i_i32[v16];\n if ( v33.m128i_i32[v14] <= v18 )\n break;\n }\n if ( (int)++v16 >= (int)v14 )\n goto LABEL_21;\n }\n ++v16;\n v33.m128i_i32[v14] = v18 + 1;\n }\n while ( (int)v16 < (int)v14 );\nLABEL_21:\n ++v14;\n }\n while ( v14 != a2 );\n if ( (unsigned int)(a2 - 1) <= 2 )\n {\n result = v33.m128i_u32[0];\n if ( v33.m128i_i32[0] <= 0 )\n result = 1LL;\n v24 = 0;\n goto LABEL_29;\n }\n v19 = _mm_load_si128((const __m128i *)&xmmword_20D0);\n v20 = &v33;\n do\n {\n v21 = _mm_loadu_si128(v20++);\n v22 = _mm_cmpgt_epi32(v21, v19);\n v19 = _mm_or_si128(_mm_andnot_si128(v22, v19), _mm_and_si128(v21, v22));\n }\n while ( v20 != &v33 + ((unsigned int)a2 >> 2) );\n v23 = _mm_srli_si128(v19, 8);\n v24 = a2 & 0xFFFFFFFC;\n v25 = _mm_cmpgt_epi32(v23, v19);\n v26 = _mm_or_si128(_mm_andnot_si128(v25, v19), _mm_and_si128(v23, v25));\n v27 = _mm_srli_si128(v26, 4);\n v28 = _mm_cmpgt_epi32(v27, v26);\n result = (unsigned int)_mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v28, v26), _mm_and_si128(v27, v28)));\n if ( (a2 & 3) != 0 )\n {\n v7 = &v33.m128i_i32[v24];\n if ( (int)result < *v7 )\n result = (unsigned int)*v7;\n if ( a2 > (int)(v24 + 1) )\n {\nLABEL_29:\n v30 = v7[1];\n if ( (int)result < v30 )\n result = (unsigned int)v30;\n if ( a2 > (int)(v24 + 2) )\n {\n v31 = v7[2];\n if ( (int)result < v31 )\n return (unsigned int)v31;\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12D0(long long a1, int a2) {\n long long v2;\n __m128i *v3;\n short v4;\n signed long long v5;\n void *v6;\n int *v7;\n __m128i si128;\n __m128i *v9;\n long long v10;\n __m128i *v11;\n int v12;\n __m128i *v13;\n long long v14;\n int v15;\n long long v16;\n int v17;\n int v18;\n __m128i v19;\n const __m128i *v20;\n __m128i v21;\n __m128i v22;\n __m128i v23;\n unsigned int v24;\n __m128i v25;\n __m128i v26;\n __m128i v27;\n __m128i v28;\n long long result;\n int v30;\n int v31;\n long long v32;\n __m128i v33;\n uint8_t v34[4072];\n uint64_t v35[6];\n v35[1] = __readfsqword(40u);\n v2 = 4LL * a2 + 15;\n v3 = (__m128i *)((char *)v35 - (v2 & 18446744073709547520LL));\n v4 = v2 & 65520;\n if (v35 != (uint64_t *)v3) {\n while (&v33 != v3)\n ;\n }\n v5 = v4 & 4095;\n v6 = alloca(v5);\n if (v5) *(long long *)((char *)&v32 + v5) = *(long long *)((char *)&v32 + v5);\n v7 = (int *)&v33;\n if (a2 <= 0) return 1LL;\n if ((unsigned int)(a2 - 1) > 2) {\n si128 = _mm_load_si128((const __m128i *)&xmmword_20D0);\n v9 = &v33;\n v10 = 16LL * ((unsigned int)a2 >> 2);\n v11 = (__m128i *)((char *)&v33 + v10);\n if ((v10 & 16) == 0 ||\n (v9 = (__m128i *)v34, v33 = si128, v34 != (uint8_t *)v11)) {\n do {\n *v9 = si128;\n v9 += 2;\n v9[-1] = si128;\n } while (v9 != v11);\n }\n v12 = a2 & 2147483644;\n if ((a2 & 3) == 0) goto LABEL_14;\n v13 = (__m128i *)((char *)&v33 + 4 * (unsigned int)v12);\n v13->m128i_i32[0] = 1;\n if (a2 <= v12 + 1) goto LABEL_14;\n goto LABEL_12;\n }\n v33.m128i_i32[0] = 1;\n v13 = &v33;\n v12 = 0;\n if (a2 == 1) return 1LL;\nLABEL_12:\n v13->m128i_i32[1] = 1;\n if (a2 > v12 + 2) v13->m128i_i32[2] = 1;\nLABEL_14:\n v14 = 1LL;\n do {\n v15 = *(uint32_t *)(a1 + 4 * v14);\n v16 = 0LL;\n do {\n while (1) {\n v17 = *(uint32_t *)(a1 + 4 * v16);\n if (v17 + 1 == v15 || v15 == v17 - 1) {\n v18 = v33.m128i_i32[v16];\n if (v33.m128i_i32[v14] <= v18) break;\n }\n if ((int)++v16 >= (int)v14) goto LABEL_21;\n }\n ++v16;\n v33.m128i_i32[v14] = v18 + 1;\n } while ((int)v16 < (int)v14);\n LABEL_21:\n ++v14;\n } while (v14 != a2);\n if ((unsigned int)(a2 - 1) <= 2) {\n result = v33.m128i_u32[0];\n if (v33.m128i_i32[0] <= 0) result = 1LL;\n v24 = 0;\n goto LABEL_29;\n }\n v19 = _mm_load_si128((const __m128i *)&xmmword_20D0);\n v20 = &v33;\n do {\n v21 = _mm_loadu_si128(v20++);\n v22 = _mm_cmpgt_epi32(v21, v19);\n v19 = _mm_or_si128(_mm_andnot_si128(v22, v19), _mm_and_si128(v21, v22));\n } while (v20 != &v33 + ((unsigned int)a2 >> 2));\n v23 = _mm_srli_si128(v19, 8);\n v24 = a2 & 4294967292;\n v25 = _mm_cmpgt_epi32(v23, v19);\n v26 = _mm_or_si128(_mm_andnot_si128(v25, v19), _mm_and_si128(v23, v25));\n v27 = _mm_srli_si128(v26, 4);\n v28 = _mm_cmpgt_epi32(v27, v26);\n result = (unsigned int)_mm_cvtsi128_si32(\n _mm_or_si128(_mm_andnot_si128(v28, v26), _mm_and_si128(v27, v28)));\n if ((a2 & 3) != 0) {\n v7 = &v33.m128i_i32[v24];\n if ((int)result < *v7) result = (unsigned int)*v7;\n if (a2 > (int)(v24 + 1)) {\n LABEL_29:\n v30 = v7[1];\n if ((int)result < v30) result = (unsigned int)v30;\n if (a2 > (int)(v24 + 2)) {\n v31 = v7[2];\n if ((int)result < v31) return (unsigned int)v31;\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n __m128i *v3;\n short v4;\n signed long long v5;\n void *v6;\n int *v7;\n __m128i si128;\n __m128i *v9;\n long long v10;\n __m128i *v11;\n int v12;\n __m128i *v13;\n long long v14;\n int v15;\n long long v16;\n int v17;\n int v18;\n __m128i v19;\n const __m128i *v20;\n __m128i v21;\n __m128i v22;\n __m128i v23;\n unsigned int v24;\n __m128i v25;\n __m128i v26;\n __m128i v27;\n __m128i v28;\n long long result;\n int v30;\n int v31;\n long long v32;\n __m128i v33;\n uint8_t v34[4072];\n uint64_t v35[6];\n v35[1] = __readfsqword(40u);\n v2 = 4LL * a2 + 15;\n v3 = (__m128i *)((char *)v35 - (v2 & 18446744073709547520LL));\n v4 = v2 & 65520;\n if (v35 != (uint64_t *)v3) {\n while (&v33 != v3)\n ;\n }\n v5 = v4 & 4095;\n v6 = alloca(v5);\n if (v5) *(long long *)((char *)&v32 + v5) = *(long long *)((char *)&v32 + v5);\n v7 = (int *)&v33;\n if (a2 <= 0) return 1LL;\n if ((unsigned int)(a2 - 1) > 2) {\n si128 = _mm_load_si128((const __m128i *)&xmmword_20D0);\n v9 = &v33;\n v10 = 16LL * ((unsigned int)a2 >> 2);\n v11 = (__m128i *)((char *)&v33 + v10);\n if ((v10 & 16) == 0 ||\n (v9 = (__m128i *)v34, v33 = si128, v34 != (uint8_t *)v11)) {\n do {\n *v9 = si128;\n v9 += 2;\n v9[-1] = si128;\n } while (v9 != v11);\n }\n v12 = a2 & 2147483644;\n if ((a2 & 3) == 0) goto LABEL_14;\n v13 = (__m128i *)((char *)&v33 + 4 * (unsigned int)v12);\n v13->m128i_i32[0] = 1;\n if (a2 <= v12 + 1) goto LABEL_14;\n goto LABEL_12;\n }\n v33.m128i_i32[0] = 1;\n v13 = &v33;\n v12 = 0;\n if (a2 == 1) return 1LL;\nLABEL_12:\n v13->m128i_i32[1] = 1;\n if (a2 > v12 + 2) v13->m128i_i32[2] = 1;\nLABEL_14:\n v14 = 1LL;\n do {\n v15 = *(uint32_t *)(a1 + 4 * v14);\n v16 = 0LL;\n do {\n while (1) {\n v17 = *(uint32_t *)(a1 + 4 * v16);\n if (v17 + 1 == v15 || v15 == v17 - 1) {\n v18 = v33.m128i_i32[v16];\n if (v33.m128i_i32[v14] <= v18) break;\n }\n if ((int)++v16 >= (int)v14) goto LABEL_21;\n }\n ++v16;\n v33.m128i_i32[v14] = v18 + 1;\n } while ((int)v16 < (int)v14);\n LABEL_21:\n ++v14;\n } while (v14 != a2);\n if ((unsigned int)(a2 - 1) <= 2) {\n result = v33.m128i_u32[0];\n if (v33.m128i_i32[0] <= 0) result = 1LL;\n v24 = 0;\n goto LABEL_29;\n }\n v19 = _mm_load_si128((const __m128i *)&xmmword_20D0);\n v20 = &v33;\n do {\n v21 = _mm_loadu_si128(v20++);\n v22 = _mm_cmpgt_epi32(v21, v19);\n v19 = _mm_or_si128(_mm_andnot_si128(v22, v19), _mm_and_si128(v21, v22));\n } while (v20 != &v33 + ((unsigned int)a2 >> 2));\n v23 = _mm_srli_si128(v19, 8);\n v24 = a2 & 4294967292;\n v25 = _mm_cmpgt_epi32(v23, v19);\n v26 = _mm_or_si128(_mm_andnot_si128(v25, v19), _mm_and_si128(v23, v25));\n v27 = _mm_srli_si128(v26, 4);\n v28 = _mm_cmpgt_epi32(v27, v26);\n result = (unsigned int)_mm_cvtsi128_si32(\n _mm_or_si128(_mm_andnot_si128(v28, v26), _mm_and_si128(v27, v28)));\n if ((a2 & 3) != 0) {\n v7 = &v33.m128i_i32[v24];\n if ((int)result < *v7) result = (unsigned int)*v7;\n if (a2 > (int)(v24 + 1)) {\n LABEL_29:\n v30 = v7[1];\n if ((int)result < v30) result = (unsigned int)v30;\n if (a2 > (int)(v24 + 2)) {\n v31 = v7[2];\n if ((int)result < v31) return (unsigned int)v31;\n }\n }\n }\n return result;\n}" + }, + { + "index": 150, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int a, int b, int c) {\n if (a == b) {\n return true;\n }\n if ((b - a) * c > 0 && (b - a) % c == 0) {\n return true;\n }\n return false;\n}", + "test": "int main() {\n\n assert(func0(1, 7, 3) == true);\n\n assert(func0(1, -3, 5) == false);\n\n assert(func0(3, 2, 5) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov %esi,-0x8(%rbp)\nmov %edx,-0xc(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x8(%rbp),%eax\njne 1169 \nmov $0x1,%eax\njmp 1193 \nmov -0x8(%rbp),%eax\nsub -0x4(%rbp),%eax\nimul -0xc(%rbp),%eax\ntest %eax,%eax\njle 118e \nmov -0x8(%rbp),%eax\nsub -0x4(%rbp),%eax\ncltd\nidivl -0xc(%rbp)\nmov %edx,%eax\ntest %eax,%eax\njne 118e \nmov $0x1,%eax\njmp 1193 \nmov $0x0,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov [rbp+var_C], edx\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_8]\njnz short loc_1169\nmov eax, 1\njmp short loc_1193\nloc_1169:\nmov eax, [rbp+var_8]\nsub eax, [rbp+var_4]\nimul eax, [rbp+var_C]\ntest eax, eax\njle short loc_118E\nmov eax, [rbp+var_8]\nsub eax, [rbp+var_4]\ncdq\nidiv [rbp+var_C]\nmov eax, edx\ntest eax, eax\njnz short loc_118E\nmov eax, 1\njmp short loc_1193\nloc_118E:\nmov eax, 0\nloc_1193:\npop rbp\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(int a1, int a2, int a3)\n{\n if ( a1 == a2 )\n return 1LL;\n return a3 * (a2 - a1) > 0 && !((a2 - a1) % a3);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov [rbp+var_C], edx\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_8]\njnz short loc_1169\nmov eax, 1\njmp short loc_1193\nloc_1169:\nmov eax, [rbp+var_8]\nsub eax, [rbp+var_4]\nimul eax, [rbp+var_C]\ntest eax, eax\njle short loc_118E\nmov eax, [rbp+var_8]\nsub eax, [rbp+var_4]\ncdq\nidiv [rbp+var_C]\nmov eax, edx\ntest eax, eax\njnz short loc_118E\nmov eax, 1\njmp short loc_1193\nloc_118E:\nmov eax, 0\nloc_1193:\npop rbp\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1149(int a1, int a2, int a3)\n{\n if ( a1 == a2 )\n return 1LL;\n return a3 * (a2 - a1) > 0 && !((a2 - a1) % a3);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1149(int a1, int a2, int a3) {\n if (a1 == a2) return 1LL;\n return a3 * (a2 - a1) > 0 && !((a2 - a1) % a3);\n}", + "ida_pseudo_norm": "uint8_t func0(int a1, int a2, int a3) {\n if (a1 == a2) return 1LL;\n return a3 * (a2 - a1) > 0 && !((a2 - a1) % a3);\n}" + }, + { + "index": 151, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\nint gcd(int p, int q) {\n\n while (q != 0) {\n\n int temp = q;\n\n q = p % q;\n\n p = temp;\n\n }\n\n return p;\n\n}\n\n\n\n", + "func": "int func0(int x, int y) { return gcd(x, y) == 1; }", + "test": "int main() {\n\n assert(func0(17, 13) == 1);\n\n assert(func0(15, 21) == 0);\n\n assert(func0(25, 45) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x8,%rsp\nmov %edi,-0x4(%rbp)\nmov %esi,-0x8(%rbp)\nmov -0x8(%rbp),%edx\nmov -0x4(%rbp),%eax\nmov %edx,%esi\nmov %eax,%edi\ncallq 1149 \ncmp $0x1,%eax\nsete %al\nmovzbl %al,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 8\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov edx, [rbp+var_8]\nmov eax, [rbp+var_4]\nmov esi, edx\nmov edi, eax\ncall gcd\ncmp eax, 1\nsetz al\nmovzx eax, al\nleave\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(unsigned int a1, unsigned int a2)\n{\n return (unsigned int)gcd(a1, a2) == 1;\n}", + "ida_strip_asm": "sub_117A:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 8\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov edx, [rbp+var_8]\nmov eax, [rbp+var_4]\nmov esi, edx\nmov edi, eax\ncall sub_1149\ncmp eax, 1\nsetz al\nmovzx eax, al\nleave\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_117A(unsigned int a1, unsigned int a2)\n{\n return (unsigned int)sub_1149(a1, a2) == 1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_117A(unsigned int a1, unsigned int a2) {\n return (unsigned int)sub_1149(a1, a2) == 1;\n}", + "ida_pseudo_norm": "uint8_t func0(unsigned int a1, unsigned int a2) {\n return (unsigned int)gcd(a1, a2) == 1;\n}" + }, + { + "index": 152, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nvoid merge(int a[], int a_len, int b[], int b_len, int c[]) {\n\n int i = 0, j = 0, k = 0;\n\n while (i < a_len && j < b_len) {\n\n if (a[i] < b[j]) {\n\n c[k++] = a[i++];\n\n } else {\n\n c[k++] = b[j++];\n\n }\n\n }\n\n while (i < a_len) {\n\n c[k++] = a[i++];\n\n }\n\n while (j < b_len) {\n\n c[k++] = b[j++];\n\n }\n\n}\n\n\n\n", + "func": "void func0(int arr[], int len) {\n if (len < 2) {\n return;\n }\n int mid = len / 2;\n int *left = (int *)malloc(mid * sizeof(int));\n int *right = (int *)malloc((len - mid) * sizeof(int));\n for (int i = 0; i < mid; i++) {\n left[i] = arr[i];\n }\n for (int i = mid; i < len; i++) {\n right[i - mid] = arr[i];\n }\n func0(left, mid);\n func0(right, len - mid);\n merge(left, mid, right, len - mid, arr);\n free(left);\n free(right);\n}", + "test": "int main() {\n\n int arr1[] = {3, 4, 2, 6, 5, 7, 1, 9};\n\n func0(arr1, 8);\n\n int sorted1[] = {1, 2, 3, 4, 5, 6, 7, 9};\n\n for (int i = 0; i < 8; i++) {\n\n assert(arr1[i] == sorted1[i]);\n\n }\n\n\n\n int arr2[] = {7, 25, 45, 78, 11, 33, 19};\n\n func0(arr2, 7);\n\n int sorted2[] = {7, 11, 19, 25, 33, 45, 78};\n\n for (int i = 0; i < 7; i++) {\n\n assert(arr2[i] == sorted2[i]);\n\n }\n\n\n\n int arr3[] = {3, 1, 4, 9, 8};\n\n func0(arr3, 5);\n\n int sorted3[] = {1, 3, 4, 8, 9};\n\n for (int i = 0; i < 5; i++) {\n\n assert(arr3[i] == sorted3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\ncmpl $0x1,-0x2c(%rbp)\njle 1461 \nmov -0x2c(%rbp),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nmov %eax,-0x14(%rbp)\nmov -0x14(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x10(%rbp)\nmov -0x2c(%rbp),%eax\nsub -0x14(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0x1c(%rbp)\njmp 13b2 \nmov -0x1c(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov -0x1c(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x10(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x1c(%rbp)\nmov -0x1c(%rbp),%eax\ncmp -0x14(%rbp),%eax\njl 1381 \nmov -0x14(%rbp),%eax\nmov %eax,-0x18(%rbp)\njmp 13f6 \nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x18(%rbp),%eax\nsub -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 13c2 \nmov -0x14(%rbp),%edx\nmov -0x10(%rbp),%rax\nmov %edx,%esi\nmov %rax,%rdi\ncallq 131f \nmov -0x2c(%rbp),%eax\nsub -0x14(%rbp),%eax\nmov %eax,%edx\nmov -0x8(%rbp),%rax\nmov %edx,%esi\nmov %rax,%rdi\ncallq 131f \nmov -0x2c(%rbp),%eax\nsub -0x14(%rbp),%eax\nmov %eax,%ecx\nmov -0x28(%rbp),%rdi\nmov -0x8(%rbp),%rdx\nmov -0x14(%rbp),%esi\nmov -0x10(%rbp),%rax\nmov %rdi,%r8\nmov %rax,%rdi\ncallq 11a9 \nmov -0x10(%rbp),%rax\nmov %rax,%rdi\ncallq 1080 \nmov -0x8(%rbp),%rax\nmov %rax,%rdi\ncallq 1080 \njmp 1462 \nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\ncmp [rbp+var_2C], 1\njle loc_1461\nmov eax, [rbp+var_2C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_14], eax\nmov eax, [rbp+var_14]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov eax, [rbp+var_2C]\nsub eax, [rbp+var_14]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_1C], 0\njmp short loc_13B2\nloc_1381:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+ptr]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_1C], 1\nloc_13B2:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_14]\njl short loc_1381\nmov eax, [rbp+var_14]\nmov [rbp+var_18], eax\njmp short loc_13F6\nloc_13C2:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_18]\nsub eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nadd [rbp+var_18], 1\nloc_13F6:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_2C]\njl short loc_13C2\nmov edx, [rbp+var_14]\nmov rax, [rbp+ptr]\nmov esi, edx\nmov rdi, rax\ncall func0\nmov eax, [rbp+var_2C]\nsub eax, [rbp+var_14]\nmov edx, eax\nmov rax, [rbp+var_8]\nmov esi, edx\nmov rdi, rax\ncall func0\nmov eax, [rbp+var_2C]\nsub eax, [rbp+var_14]\nmov ecx, eax\nmov rdi, [rbp+var_28]\nmov rdx, [rbp+var_8]\nmov esi, [rbp+var_14]\nmov rax, [rbp+ptr]\nmov r8, rdi\nmov rdi, rax\ncall merge\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_8]\nmov rdi, rax; ptr\ncall _free\njmp short locret_1462\nloc_1461:\nnop\nlocret_1462:\nleave\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2)\n{\n signed int i; // [rsp+14h] [rbp-1Ch]\n int j; // [rsp+18h] [rbp-18h]\n unsigned int v4; // [rsp+1Ch] [rbp-14h]\n _DWORD *ptr; // [rsp+20h] [rbp-10h]\n _DWORD *v6; // [rsp+28h] [rbp-8h]\n\n if ( a2 > 1 )\n {\n v4 = a2 / 2;\n ptr = malloc(4LL * (a2 / 2));\n v6 = malloc(4LL * (a2 - a2 / 2));\n for ( i = 0; i < (int)v4; ++i )\n ptr[i] = *(_DWORD *)(4LL * i + a1);\n for ( j = a2 / 2; j < a2; ++j )\n v6[j - v4] = *(_DWORD *)(4LL * j + a1);\n func0(ptr, v4);\n func0(v6, a2 - v4);\n merge(ptr, v4, v6, a2 - v4, a1);\n free(ptr);\n free(v6);\n }\n}", + "ida_strip_asm": "sub_131F:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\ncmp [rbp+var_2C], 1\njle loc_1461\nmov eax, [rbp+var_2C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_14], eax\nmov eax, [rbp+var_14]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov eax, [rbp+var_2C]\nsub eax, [rbp+var_14]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_1C], 0\njmp short loc_13B2\nloc_1381:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+ptr]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_1C], 1\nloc_13B2:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_14]\njl short loc_1381\nmov eax, [rbp+var_14]\nmov [rbp+var_18], eax\njmp short loc_13F6\nloc_13C2:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_18]\nsub eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nadd [rbp+var_18], 1\nloc_13F6:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_2C]\njl short loc_13C2\nmov edx, [rbp+var_14]\nmov rax, [rbp+ptr]\nmov esi, edx\nmov rdi, rax\ncall sub_131F\nmov eax, [rbp+var_2C]\nsub eax, [rbp+var_14]\nmov edx, eax\nmov rax, [rbp+var_8]\nmov esi, edx\nmov rdi, rax\ncall sub_131F\nmov eax, [rbp+var_2C]\nsub eax, [rbp+var_14]\nmov ecx, eax\nmov rdi, [rbp+var_28]\nmov rdx, [rbp+var_8]\nmov esi, [rbp+var_14]\nmov rax, [rbp+ptr]\nmov r8, rdi\nmov rdi, rax\ncall sub_11A9\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_8]\nmov rdi, rax; ptr\ncall _free\njmp short locret_1462\nloc_1461:\nnop\nlocret_1462:\nleave\nretn", + "ida_strip_pseudo": "void __fastcall sub_131F(__int64 a1, int a2)\n{\n signed int i; // [rsp+14h] [rbp-1Ch]\n int j; // [rsp+18h] [rbp-18h]\n unsigned int v4; // [rsp+1Ch] [rbp-14h]\n _DWORD *ptr; // [rsp+20h] [rbp-10h]\n _DWORD *v6; // [rsp+28h] [rbp-8h]\n\n if ( a2 > 1 )\n {\n v4 = a2 / 2;\n ptr = malloc(4LL * (a2 / 2));\n v6 = malloc(4LL * (a2 - a2 / 2));\n for ( i = 0; i < (int)v4; ++i )\n ptr[i] = *(_DWORD *)(4LL * i + a1);\n for ( j = a2 / 2; j < a2; ++j )\n v6[j - v4] = *(_DWORD *)(4LL * j + a1);\n sub_131F(ptr, v4);\n sub_131F(v6, a2 - v4);\n sub_11A9(ptr, v4, v6, a2 - v4, a1);\n free(ptr);\n free(v6);\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_131F(long long a1, int a2) {\n signed int i;\n int j;\n unsigned int v4;\n uint32_t *ptr;\n uint32_t *v6;\n if (a2 > 1) {\n v4 = a2 / 2;\n ptr = malloc(4LL * (a2 / 2));\n v6 = malloc(4LL * (a2 - a2 / 2));\n for (i = 0; i < (int)v4; ++i) ptr[i] = *(uint32_t *)(4LL * i + a1);\n for (j = a2 / 2; j < a2; ++j) v6[j - v4] = *(uint32_t *)(4LL * j + a1);\n sub_131F(ptr, v4);\n sub_131F(v6, a2 - v4);\n sub_11A9(ptr, v4, v6, a2 - v4, a1);\n free(ptr);\n free(v6);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2) {\n signed int i;\n int j;\n unsigned int v4;\n uint32_t *ptr;\n uint32_t *v6;\n if (a2 > 1) {\n v4 = a2 / 2;\n ptr = malloc(4LL * (a2 / 2));\n v6 = malloc(4LL * (a2 - a2 / 2));\n for (i = 0; i < (int)v4; ++i) ptr[i] = *(uint32_t *)(4LL * i + a1);\n for (j = a2 / 2; j < a2; ++j) v6[j - v4] = *(uint32_t *)(4LL * j + a1);\n func0(ptr, v4);\n func0(v6, a2 - v4);\n merge(ptr, v4, v6, a2 - v4, a1);\n free(ptr);\n free(v6);\n }\n}" + }, + { + "index": 152, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nvoid merge(int a[], int a_len, int b[], int b_len, int c[]) {\n\n int i = 0, j = 0, k = 0;\n\n while (i < a_len && j < b_len) {\n\n if (a[i] < b[j]) {\n\n c[k++] = a[i++];\n\n } else {\n\n c[k++] = b[j++];\n\n }\n\n }\n\n while (i < a_len) {\n\n c[k++] = a[i++];\n\n }\n\n while (j < b_len) {\n\n c[k++] = b[j++];\n\n }\n\n}\n\n\n\n", + "func": "void func0(int arr[], int len) {\n if (len < 2) {\n return;\n }\n int mid = len / 2;\n int *left = (int *)malloc(mid * sizeof(int));\n int *right = (int *)malloc((len - mid) * sizeof(int));\n for (int i = 0; i < mid; i++) {\n left[i] = arr[i];\n }\n for (int i = mid; i < len; i++) {\n right[i - mid] = arr[i];\n }\n func0(left, mid);\n func0(right, len - mid);\n merge(left, mid, right, len - mid, arr);\n free(left);\n free(right);\n}", + "test": "int main() {\n\n int arr1[] = {3, 4, 2, 6, 5, 7, 1, 9};\n\n func0(arr1, 8);\n\n int sorted1[] = {1, 2, 3, 4, 5, 6, 7, 9};\n\n for (int i = 0; i < 8; i++) {\n\n assert(arr1[i] == sorted1[i]);\n\n }\n\n\n\n int arr2[] = {7, 25, 45, 78, 11, 33, 19};\n\n func0(arr2, 7);\n\n int sorted2[] = {7, 11, 19, 25, 33, 45, 78};\n\n for (int i = 0; i < 7; i++) {\n\n assert(arr2[i] == sorted2[i]);\n\n }\n\n\n\n int arr3[] = {3, 1, 4, 9, 8};\n\n func0(arr3, 5);\n\n int sorted3[] = {1, 3, 4, 8, 9};\n\n for (int i = 0; i < 5; i++) {\n\n assert(arr3[i] == sorted3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%esi\njle 1340 \npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov %rdi,%rbp\nmov %esi,%r12d\nmov %esi,%r14d\nshr $0x1f,%r14d\nadd %esi,%r14d\nsar %r14d\nmovslq %r14d,%rbx\nlea 0x0(,%rbx,4),%rdi\ncallq 10b0 \nmov %rax,%r13\nmov %r12d,%eax\nsub %r14d,%eax\nmov %eax,0xc(%rsp)\nmovslq %eax,%rdi\nshl $0x2,%rdi\ncallq 10b0 \nmov %rax,%r15\nlea -0x1(%r14),%ecx\nmov $0x0,%eax\nmov 0x0(%rbp,%rax,4),%edx\nmov %edx,0x0(%r13,%rax,4)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rcx,%rdx\njne 12c1 \ncmp %r14d,%r12d\njle 12f5 \nmov %rbx,%rax\nneg %rax\nlea (%r15,%rax,4),%rdx\nmov 0x0(%rbp,%rbx,4),%eax\nmov %eax,(%rdx,%rbx,4)\nadd $0x1,%rbx\ncmp %ebx,%r12d\njg 12e5 \nmov %r14d,%esi\nmov %r13,%rdi\ncallq 125e \nmov 0xc(%rsp),%ebx\nmov %ebx,%esi\nmov %r15,%rdi\ncallq 125e \nmov %rbp,%r8\nmov %ebx,%ecx\nmov %r15,%rdx\nmov %r14d,%esi\nmov %r13,%rdi\ncallq 11a9 \nmov %r13,%rdi\ncallq 1080 \nmov %r15,%rdi\ncallq 1080 \nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nretq\n", + "ida_asm": "func0:\nendbr64\ncmp esi, 1\njle locret_1368\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov r12, rdi\nmov ebx, esi\nmov r15d, esi\nshr r15d, 1Fh\nadd r15d, esi\nsar r15d, 1\nmovsxd rbp, r15d\nshl rbp, 2\nmov rdi, rbp; size\ncall _malloc\nmov r14, rax\nmov eax, ebx\nsub eax, r15d\nmov [rsp+48h+var_3C], eax\nmovsxd rdi, eax\nshl rdi, 2; size\ncall _malloc\nmov r13, rax\nmov eax, 0\nloc_12E6:\nmov edx, [r12+rax]\nmov [r14+rax], edx\nadd rax, 4\ncmp rbp, rax\njnz short loc_12E6\ncmp ebx, r15d\njle short loc_131D\nsub ebx, r15d\nshl rbx, 2\nadd rbp, r12\nmov eax, 0\nloc_130B:\nmov edx, [rbp+rax+0]\nmov [r13+rax+0], edx\nadd rax, 4\ncmp rax, rbx\njnz short loc_130B\nloc_131D:\nmov esi, r15d\nmov rdi, r14\ncall func0\nmov ebx, [rsp+48h+var_3C]\nmov esi, ebx\nmov rdi, r13\ncall func0\nmov r8, r12\nmov ecx, ebx\nmov rdx, r13\nmov esi, r15d\nmov rdi, r14\ncall merge\nmov rdi, r14; ptr\ncall _free\nmov rdi, r13; ptr\ncall _free\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nlocret_1368:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v2; // r15d\n size_t v3; // rbp\n char *v4; // r14\n char *v5; // r13\n __int64 v6; // rax\n size_t v7; // rbp\n __int64 v8; // rax\n unsigned int v9; // [rsp+0h] [rbp-3Ch]\n\n if ( a2 > 1 )\n {\n v2 = a2 / 2;\n v3 = 4LL * (a2 / 2);\n v4 = (char *)malloc(v3);\n v9 = a2 - a2 / 2;\n v5 = (char *)malloc(4LL * (int)v9);\n v6 = 0LL;\n do\n {\n *(_DWORD *)&v4[v6] = *(_DWORD *)(a1 + v6);\n v6 += 4LL;\n }\n while ( v3 != v6 );\n if ( a2 > (int)v2 )\n {\n v7 = a1 + v3;\n v8 = 0LL;\n do\n {\n *(_DWORD *)&v5[v8] = *(_DWORD *)(v7 + v8);\n v8 += 4LL;\n }\n while ( v8 != 4LL * (a2 - v2) );\n }\n func0(v4, v2);\n func0(v5, v9);\n merge(v4, v2, v5, v9, a1);\n free(v4);\n free(v5);\n }\n}", + "ida_strip_asm": "sub_128A:\nendbr64\ncmp esi, 1\njle locret_1368\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov r12, rdi\nmov ebx, esi\nmov r15d, esi\nshr r15d, 1Fh\nadd r15d, esi\nsar r15d, 1\nmovsxd rbp, r15d\nshl rbp, 2\nmov rdi, rbp; size\ncall _malloc\nmov r14, rax\nmov eax, ebx\nsub eax, r15d\nmov [rsp+48h+var_3C], eax\nmovsxd rdi, eax\nshl rdi, 2; size\ncall _malloc\nmov r13, rax\nmov eax, 0\nloc_12E6:\nmov edx, [r12+rax]\nmov [r14+rax], edx\nadd rax, 4\ncmp rbp, rax\njnz short loc_12E6\ncmp ebx, r15d\njle short loc_131D\nsub ebx, r15d\nshl rbx, 2\nadd rbp, r12\nmov eax, 0\nloc_130B:\nmov edx, [rbp+rax+0]\nmov [r13+rax+0], edx\nadd rax, 4\ncmp rax, rbx\njnz short loc_130B\nloc_131D:\nmov esi, r15d\nmov rdi, r14\ncall sub_128A\nmov ebx, [rsp+48h+var_3C]\nmov esi, ebx\nmov rdi, r13\ncall sub_128A\nmov r8, r12\nmov ecx, ebx\nmov rdx, r13\nmov esi, r15d\nmov rdi, r14\ncall sub_11A9\nmov rdi, r14; ptr\ncall _free\nmov rdi, r13; ptr\ncall _free\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nlocret_1368:\nretn", + "ida_strip_pseudo": "void __fastcall sub_128A(__int64 a1, int a2)\n{\n unsigned int v2; // r15d\n size_t v3; // rbp\n char *v4; // r14\n char *v5; // r13\n __int64 v6; // rax\n size_t v7; // rbp\n __int64 v8; // rax\n unsigned int v9; // [rsp+0h] [rbp-3Ch]\n\n if ( a2 > 1 )\n {\n v2 = a2 / 2;\n v3 = 4LL * (a2 / 2);\n v4 = (char *)malloc(v3);\n v9 = a2 - a2 / 2;\n v5 = (char *)malloc(4LL * (int)v9);\n v6 = 0LL;\n do\n {\n *(_DWORD *)&v4[v6] = *(_DWORD *)(a1 + v6);\n v6 += 4LL;\n }\n while ( v3 != v6 );\n if ( a2 > (int)v2 )\n {\n v7 = a1 + v3;\n v8 = 0LL;\n do\n {\n *(_DWORD *)&v5[v8] = *(_DWORD *)(v7 + v8);\n v8 += 4LL;\n }\n while ( v8 != 4LL * (a2 - v2) );\n }\n sub_128A(v4, v2);\n sub_128A(v5, v9);\n sub_11A9(v4, v2, v5, v9, a1);\n free(v4);\n free(v5);\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_128A(long long a1, int a2) {\n unsigned int v2;\n unsigned int v3;\n char *v4;\n char *v5;\n long long v6;\n unsigned int v7;\n long long v8;\n unsigned int v9;\n if (a2 > 1) {\n v2 = a2 / 2;\n v3 = 4LL * (a2 / 2);\n v4 = (char *)malloc(v3);\n v9 = a2 - a2 / 2;\n v5 = (char *)malloc(4LL * (int)v9);\n v6 = 0LL;\n do {\n *(uint32_t *)&v4[v6] = *(uint32_t *)(a1 + v6);\n v6 += 4LL;\n } while (v3 != v6);\n if (a2 > (int)v2) {\n v7 = a1 + v3;\n v8 = 0LL;\n do {\n *(uint32_t *)&v5[v8] = *(uint32_t *)(v7 + v8);\n v8 += 4LL;\n } while (v8 != 4LL * (a2 - v2));\n }\n sub_128A(v4, v2);\n sub_128A(v5, v9);\n sub_11A9(v4, v2, v5, v9, a1);\n free(v4);\n free(v5);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2) {\n unsigned int v2;\n unsigned int v3;\n char *v4;\n char *v5;\n long long v6;\n unsigned int v7;\n long long v8;\n unsigned int v9;\n if (a2 > 1) {\n v2 = a2 / 2;\n v3 = 4LL * (a2 / 2);\n v4 = (char *)malloc(v3);\n v9 = a2 - a2 / 2;\n v5 = (char *)malloc(4LL * (int)v9);\n v6 = 0LL;\n do {\n *(uint32_t *)&v4[v6] = *(uint32_t *)(a1 + v6);\n v6 += 4LL;\n } while (v3 != v6);\n if (a2 > (int)v2) {\n v7 = a1 + v3;\n v8 = 0LL;\n do {\n *(uint32_t *)&v5[v8] = *(uint32_t *)(v7 + v8);\n v8 += 4LL;\n } while (v8 != 4LL * (a2 - v2));\n }\n func0(v4, v2);\n func0(v5, v9);\n merge(v4, v2, v5, v9, a1);\n free(v4);\n free(v5);\n }\n}" + }, + { + "index": 152, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nvoid merge(int a[], int a_len, int b[], int b_len, int c[]) {\n\n int i = 0, j = 0, k = 0;\n\n while (i < a_len && j < b_len) {\n\n if (a[i] < b[j]) {\n\n c[k++] = a[i++];\n\n } else {\n\n c[k++] = b[j++];\n\n }\n\n }\n\n while (i < a_len) {\n\n c[k++] = a[i++];\n\n }\n\n while (j < b_len) {\n\n c[k++] = b[j++];\n\n }\n\n}\n\n\n\n", + "func": "void func0(int arr[], int len) {\n if (len < 2) {\n return;\n }\n int mid = len / 2;\n int *left = (int *)malloc(mid * sizeof(int));\n int *right = (int *)malloc((len - mid) * sizeof(int));\n for (int i = 0; i < mid; i++) {\n left[i] = arr[i];\n }\n for (int i = mid; i < len; i++) {\n right[i - mid] = arr[i];\n }\n func0(left, mid);\n func0(right, len - mid);\n merge(left, mid, right, len - mid, arr);\n free(left);\n free(right);\n}", + "test": "int main() {\n\n int arr1[] = {3, 4, 2, 6, 5, 7, 1, 9};\n\n func0(arr1, 8);\n\n int sorted1[] = {1, 2, 3, 4, 5, 6, 7, 9};\n\n for (int i = 0; i < 8; i++) {\n\n assert(arr1[i] == sorted1[i]);\n\n }\n\n\n\n int arr2[] = {7, 25, 45, 78, 11, 33, 19};\n\n func0(arr2, 7);\n\n int sorted2[] = {7, 11, 19, 25, 33, 45, 78};\n\n for (int i = 0; i < 7; i++) {\n\n assert(arr2[i] == sorted2[i]);\n\n }\n\n\n\n int arr3[] = {3, 1, 4, 9, 8};\n\n func0(arr3, 5);\n\n int sorted3[] = {1, 3, 4, 8, 9};\n\n for (int i = 0; i < 5; i++) {\n\n assert(arr3[i] == sorted3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%esi\njle 1510 \njmp 1520 \nnopl 0x0(%rax,%rax,1)\nretq\ndata16 nopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0_part_0:\npush r15\npush r14\nmov r14, rdi\npush r13\npush r12\npush rbp\nmov ebp, esi\npush rbx\nsar ebp, 1\nmov ebx, esi\nmovsxd rcx, ebp\nmov r15d, ebx\nshl rcx, 2\nsub r15d, ebp\nsub rsp, 18h\nmov rdi, rcx; size\nmov [rsp+48h+var_40], rcx\ncall _malloc\nmovsxd rdi, r15d\nshl rdi, 2; size\nmov r12, rax\ncall _malloc\nmov edx, ebp\nmov rsi, r14; src\nmov rdi, r12; dest\nshl rdx, 2; n\nmov r13, rax\ncall _memcpy\ncmp ebx, ebp\nmov rcx, [rsp+48h+var_40]\njle short loc_152B\nsub ebx, 1\nlea rsi, [r14+rcx]; src\nmov rdi, r13; dest\nsub ebx, ebp\nlea rdx, ds:4[rbx*4]; n\ncall _memcpy\ncmp ebp, 1\njz short loc_1535\nloc_152B:\nmov esi, ebp\nmov rdi, r12\ncall func0_part_0\nloc_1535:\ncmp r15d, 1\njle short loc_1546\nmov esi, r15d\nmov rdi, r13\ncall func0_part_0\nloc_1546:\nmov r8, r14\nmov ecx, r15d\nmov rdx, r13\nmov esi, ebp\nmov rdi, r12\ncall merge\nmov rdi, r12; ptr\ncall _free\nadd rsp, 18h\nmov rdi, r13; ptr\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\njmp _free", + "ida_pseudo": "void __fastcall func0_part_0(char *a1, int a2)\n{\n unsigned int v2; // ebp\n int v3; // r15d\n void *v4; // r12\n void *v5; // r13\n __int64 v6; // rdx\n __int64 v7; // rcx\n\n v2 = a2 >> 1;\n v3 = a2 - (a2 >> 1);\n v4 = malloc(4LL * (a2 >> 1));\n v5 = malloc(4LL * v3);\n memcpy(v4, a1, 4LL * (unsigned int)(a2 >> 1));\n v7 = 4LL * (a2 >> 1);\n if ( a2 <= a2 >> 1 || (memcpy(v5, &a1[4 * v2], 4LL * (a2 - 1 - v2) + 4), v2 != 1) )\n func0_part_0(v4, v2, v6, v7);\n if ( v3 > 1 )\n func0_part_0(v5, (unsigned int)v3, v6, v7);\n merge(v4, v2, v5, (unsigned int)v3, a1);\n free(v4);\n free(v5);\n}", + "ida_strip_asm": "sub_14B0:\npush r15\npush r14\nmov r14, rdi\npush r13\npush r12\npush rbp\nmov ebp, esi\npush rbx\nsar ebp, 1\nmov ebx, esi\nmovsxd rcx, ebp\nmov r15d, ebx\nshl rcx, 2\nsub r15d, ebp\nsub rsp, 18h\nmov rdi, rcx; size\nmov [rsp+48h+var_40], rcx\ncall _malloc\nmovsxd rdi, r15d\nshl rdi, 2; size\nmov r12, rax\ncall _malloc\nmov edx, ebp\nmov rsi, r14; src\nmov rdi, r12; dest\nshl rdx, 2; n\nmov r13, rax\ncall _memcpy\ncmp ebx, ebp\nmov rcx, [rsp+48h+var_40]\njle short loc_152B\nsub ebx, 1\nlea rsi, [r14+rcx]; src\nmov rdi, r13; dest\nsub ebx, ebp\nlea rdx, ds:4[rbx*4]; n\ncall _memcpy\ncmp ebp, 1\njz short loc_1535\nloc_152B:\nmov esi, ebp\nmov rdi, r12\ncall sub_14B0\nloc_1535:\ncmp r15d, 1\njle short loc_1546\nmov esi, r15d\nmov rdi, r13\ncall sub_14B0\nloc_1546:\nmov r8, r14\nmov ecx, r15d\nmov rdx, r13\nmov esi, ebp\nmov rdi, r12\ncall sub_13C0\nmov rdi, r12; ptr\ncall _free\nadd rsp, 18h\nmov rdi, r13; ptr\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\njmp _free", + "ida_strip_pseudo": "void __fastcall sub_14B0(char *a1, int a2)\n{\n unsigned int v2; // ebp\n int v3; // r15d\n void *v4; // r12\n void *v5; // r13\n __int64 v6; // rdx\n __int64 v7; // rcx\n\n v2 = a2 >> 1;\n v3 = a2 - (a2 >> 1);\n v4 = malloc(4LL * (a2 >> 1));\n v5 = malloc(4LL * v3);\n memcpy(v4, a1, 4LL * (unsigned int)(a2 >> 1));\n v7 = 4LL * (a2 >> 1);\n if ( a2 <= a2 >> 1 || (memcpy(v5, &a1[4 * v2], 4LL * (a2 - 1 - v2) + 4), v2 != 1) )\n sub_14B0(v4, v2, v6, v7);\n if ( v3 > 1 )\n sub_14B0(v5, (unsigned int)v3, v6, v7);\n sub_13C0(v4, v2, v5, (unsigned int)v3, a1);\n free(v4);\n free(v5);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_14B0(char *a1, int a2) {\n unsigned int v2;\n int v3;\n void *v4;\n void *v5;\n long long v6;\n long long v7;\n v2 = a2 >> 1;\n v3 = a2 - (a2 >> 1);\n v4 = malloc(4LL * (a2 >> 1));\n v5 = malloc(4LL * v3);\n memcpy(v4, a1, 4LL * (unsigned int)(a2 >> 1));\n v7 = 4LL * (a2 >> 1);\n if (a2 <= a2 >> 1 ||\n (memcpy(v5, &a1[4 * v2], 4LL * (a2 - 1 - v2) + 4), v2 != 1))\n sub_14B0(v4, v2, v6, v7);\n if (v3 > 1) sub_14B0(v5, (unsigned int)v3, v6, v7);\n sub_13C0(v4, v2, v5, (unsigned int)v3, a1);\n free(v4);\n free(v5);\n}", + "ida_pseudo_norm": "void func0_part_0(char *a1, int a2) {\n unsigned int v2;\n int v3;\n void *v4;\n void *v5;\n long long v6;\n long long v7;\n v2 = a2 >> 1;\n v3 = a2 - (a2 >> 1);\n v4 = malloc(4LL * (a2 >> 1));\n v5 = malloc(4LL * v3);\n memcpy(v4, a1, 4LL * (unsigned int)(a2 >> 1));\n v7 = 4LL * (a2 >> 1);\n if (a2 <= a2 >> 1 ||\n (memcpy(v5, &a1[4 * v2], 4LL * (a2 - 1 - v2) + 4), v2 != 1))\n func0_part_0(v4, v2, v6, v7);\n if (v3 > 1) func0_part_0(v5, (unsigned int)v3, v6, v7);\n merge(v4, v2, v5, (unsigned int)v3, a1);\n free(v4);\n free(v5);\n}" + }, + { + "index": 152, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nvoid merge(int a[], int a_len, int b[], int b_len, int c[]) {\n\n int i = 0, j = 0, k = 0;\n\n while (i < a_len && j < b_len) {\n\n if (a[i] < b[j]) {\n\n c[k++] = a[i++];\n\n } else {\n\n c[k++] = b[j++];\n\n }\n\n }\n\n while (i < a_len) {\n\n c[k++] = a[i++];\n\n }\n\n while (j < b_len) {\n\n c[k++] = b[j++];\n\n }\n\n}\n\n\n\n", + "func": "void func0(int arr[], int len) {\n if (len < 2) {\n return;\n }\n int mid = len / 2;\n int *left = (int *)malloc(mid * sizeof(int));\n int *right = (int *)malloc((len - mid) * sizeof(int));\n for (int i = 0; i < mid; i++) {\n left[i] = arr[i];\n }\n for (int i = mid; i < len; i++) {\n right[i - mid] = arr[i];\n }\n func0(left, mid);\n func0(right, len - mid);\n merge(left, mid, right, len - mid, arr);\n free(left);\n free(right);\n}", + "test": "int main() {\n\n int arr1[] = {3, 4, 2, 6, 5, 7, 1, 9};\n\n func0(arr1, 8);\n\n int sorted1[] = {1, 2, 3, 4, 5, 6, 7, 9};\n\n for (int i = 0; i < 8; i++) {\n\n assert(arr1[i] == sorted1[i]);\n\n }\n\n\n\n int arr2[] = {7, 25, 45, 78, 11, 33, 19};\n\n func0(arr2, 7);\n\n int sorted2[] = {7, 11, 19, 25, 33, 45, 78};\n\n for (int i = 0; i < 7; i++) {\n\n assert(arr2[i] == sorted2[i]);\n\n }\n\n\n\n int arr3[] = {3, 1, 4, 9, 8};\n\n func0(arr3, 5);\n\n int sorted3[] = {1, 3, 4, 8, 9};\n\n for (int i = 0; i < 5; i++) {\n\n assert(arr3[i] == sorted3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%esi\njle 17d0 \njmpq 16f0 \nxchg %ax,%ax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0_part_0:\npush r15\npush r14\nmov r14, rdi\npush r13\npush r12\npush rbp\nmov ebp, esi\npush rbx\nsar ebp, 1\nmov ebx, esi\nmovsxd rcx, ebp\nmov r15d, ebx\nshl rcx, 2\nsub r15d, ebp\nsub rsp, 18h\nmov rdi, rcx; size\nmov [rsp+48h+var_40], rcx\ncall _malloc\nmovsxd rdi, r15d\nshl rdi, 2; size\nmov r12, rax\ncall _malloc\nmov edx, ebp\nmov rsi, r14; src\nmov rdi, r12; dest\nshl rdx, 2; n\nmov r13, rax\ncall _memcpy\ncmp ebx, ebp\nmov rcx, [rsp+48h+var_40]\njle short loc_16CB\nsub ebx, 1\nlea rsi, [r14+rcx]; src\nmov rdi, r13; dest\nsub ebx, ebp\nlea rdx, ds:4[rbx*4]; n\ncall _memcpy\ncmp ebp, 1\njz short loc_16D5\nloc_16CB:\nmov esi, ebp\nmov rdi, r12\ncall func0_part_0\nloc_16D5:\ncmp r15d, 1\njle short loc_16E6\nmov esi, r15d\nmov rdi, r13\ncall func0_part_0\nloc_16E6:\nmov r8, r14\nmov ecx, r15d\nmov rdx, r13\nmov esi, ebp\nmov rdi, r12\ncall merge\nmov rdi, r12; ptr\ncall _free\nadd rsp, 18h\nmov rdi, r13; ptr\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\njmp _free", + "ida_pseudo": "void __fastcall func0_part_0(char *a1, int a2)\n{\n unsigned int v2; // ebp\n int v3; // r15d\n void *v4; // r12\n void *v5; // r13\n __int64 v6; // rdx\n __int64 v7; // rcx\n\n v2 = a2 >> 1;\n v3 = a2 - (a2 >> 1);\n v4 = malloc(4LL * (a2 >> 1));\n v5 = malloc(4LL * v3);\n memcpy(v4, a1, 4LL * (unsigned int)(a2 >> 1));\n v7 = 4LL * (a2 >> 1);\n if ( a2 <= a2 >> 1 || (memcpy(v5, &a1[4 * v2], 4LL * (a2 - 1 - v2) + 4), v2 != 1) )\n func0_part_0(v4, v2, v6, v7);\n if ( v3 > 1 )\n func0_part_0(v5, (unsigned int)v3, v6, v7);\n merge(v4, v2, v5, (unsigned int)v3, a1);\n free(v4);\n free(v5);\n}", + "ida_strip_asm": "sub_1650:\npush r15\npush r14\nmov r14, rdi\npush r13\npush r12\npush rbp\nmov ebp, esi\npush rbx\nsar ebp, 1\nmov ebx, esi\nmovsxd rcx, ebp\nmov r15d, ebx\nshl rcx, 2\nsub r15d, ebp\nsub rsp, 18h\nmov rdi, rcx; size\nmov [rsp+48h+var_40], rcx\ncall _malloc\nmovsxd rdi, r15d\nshl rdi, 2; size\nmov r12, rax\ncall _malloc\nmov edx, ebp\nmov rsi, r14; src\nmov rdi, r12; dest\nshl rdx, 2; n\nmov r13, rax\ncall _memcpy\ncmp ebx, ebp\nmov rcx, [rsp+48h+var_40]\njle short loc_16CB\nsub ebx, 1\nlea rsi, [r14+rcx]; src\nmov rdi, r13; dest\nsub ebx, ebp\nlea rdx, ds:4[rbx*4]; n\ncall _memcpy\ncmp ebp, 1\njz short loc_16D5\nloc_16CB:\nmov esi, ebp\nmov rdi, r12\ncall sub_1650\nloc_16D5:\ncmp r15d, 1\njle short loc_16E6\nmov esi, r15d\nmov rdi, r13\ncall sub_1650\nloc_16E6:\nmov r8, r14\nmov ecx, r15d\nmov rdx, r13\nmov esi, ebp\nmov rdi, r12\ncall sub_13A0\nmov rdi, r12; ptr\ncall _free\nadd rsp, 18h\nmov rdi, r13; ptr\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\njmp _free", + "ida_strip_pseudo": "void __fastcall sub_1650(char *a1, int a2)\n{\n unsigned int v2; // ebp\n int v3; // r15d\n void *v4; // r12\n void *v5; // r13\n __int64 v6; // rdx\n __int64 v7; // rcx\n\n v2 = a2 >> 1;\n v3 = a2 - (a2 >> 1);\n v4 = malloc(4LL * (a2 >> 1));\n v5 = malloc(4LL * v3);\n memcpy(v4, a1, 4LL * (unsigned int)(a2 >> 1));\n v7 = 4LL * (a2 >> 1);\n if ( a2 <= a2 >> 1 || (memcpy(v5, &a1[4 * v2], 4LL * (a2 - 1 - v2) + 4), v2 != 1) )\n sub_1650(v4, v2, v6, v7);\n if ( v3 > 1 )\n sub_1650(v5, (unsigned int)v3, v6, v7);\n sub_13A0(v4, v2, v5, (unsigned int)v3, a1);\n free(v4);\n free(v5);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1650(char *a1, int a2) {\n unsigned int v2;\n int v3;\n void *v4;\n void *v5;\n long long v6;\n long long v7;\n v2 = a2 >> 1;\n v3 = a2 - (a2 >> 1);\n v4 = malloc(4LL * (a2 >> 1));\n v5 = malloc(4LL * v3);\n memcpy(v4, a1, 4LL * (unsigned int)(a2 >> 1));\n v7 = 4LL * (a2 >> 1);\n if (a2 <= a2 >> 1 ||\n (memcpy(v5, &a1[4 * v2], 4LL * (a2 - 1 - v2) + 4), v2 != 1))\n sub_1650(v4, v2, v6, v7);\n if (v3 > 1) sub_1650(v5, (unsigned int)v3, v6, v7);\n sub_13A0(v4, v2, v5, (unsigned int)v3, a1);\n free(v4);\n free(v5);\n}", + "ida_pseudo_norm": "void func0_part_0(char *a1, int a2) {\n unsigned int v2;\n int v3;\n void *v4;\n void *v5;\n long long v6;\n long long v7;\n v2 = a2 >> 1;\n v3 = a2 - (a2 >> 1);\n v4 = malloc(4LL * (a2 >> 1));\n v5 = malloc(4LL * v3);\n memcpy(v4, a1, 4LL * (unsigned int)(a2 >> 1));\n v7 = 4LL * (a2 >> 1);\n if (a2 <= a2 >> 1 ||\n (memcpy(v5, &a1[4 * v2], 4LL * (a2 - 1 - v2) + 4), v2 != 1))\n func0_part_0(v4, v2, v6, v7);\n if (v3 > 1) func0_part_0(v5, (unsigned int)v3, v6, v7);\n merge(v4, v2, v5, (unsigned int)v3, a1);\n free(v4);\n free(v5);\n}" + }, + { + "index": 153, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "double* func0(double a, double b, double c) {\n static double vertex[2];\n vertex[0] = -b / (2 * a);\n vertex[1] = ((4 * a * c) - (b * b)) / (4 * a);\n return vertex;\n}", + "test": "int main() {\n\n double *result;\n\n\n\n result = func0(5, 3, 2);\n\n assert(result[0] == -0.3 && result[1] == 1.55);\n\n\n\n result = func0(9, 8, 4);\n\n assert(result[0] == -0.4444444444444444 && result[1] == 2.2222222222222223);\n\n\n\n result = func0(2, 4, 6);\n\n assert(result[0] == -1.0 && result[1] == 4.0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmovsd %xmm0,-0x8(%rbp)\nmovsd %xmm1,-0x10(%rbp)\nmovsd %xmm2,-0x18(%rbp)\nmovsd -0x10(%rbp),%xmm0\nmovq 0xf83(%rip),%xmm1\nxorpd %xmm0,%xmm1\nmovsd -0x8(%rbp),%xmm0\naddsd %xmm0,%xmm0\ndivsd %xmm0,%xmm1\nmovapd %xmm1,%xmm0\nmovsd %xmm0,0x2e96(%rip)\nmovsd -0x8(%rbp),%xmm1\nmovsd 0xf69(%rip),%xmm0\nmulsd %xmm1,%xmm0\nmovapd %xmm0,%xmm1\nmulsd -0x18(%rbp),%xmm1\nmovsd -0x10(%rbp),%xmm0\nmulsd %xmm0,%xmm0\nsubsd %xmm0,%xmm1\nmovapd %xmm1,%xmm0\nmovsd -0x8(%rbp),%xmm2\nmovsd 0xf3e(%rip),%xmm1\nmulsd %xmm2,%xmm1\ndivsd %xmm1,%xmm0\nmovsd %xmm0,0x2e56(%rip)\nlea 0x2e47(%rip),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmovsd [rbp+var_8], xmm0\nmovsd [rbp+var_10], xmm1\nmovsd [rbp+var_18], xmm2\nmovsd xmm0, [rbp+var_10]\nmovq xmm1, cs:qword_20D0\nxorpd xmm1, xmm0\nmovsd xmm0, [rbp+var_8]\nmovapd xmm2, xmm0\naddsd xmm2, xmm0\ndivsd xmm1, xmm2\nmovapd xmm0, xmm1\nmovsd cs:vertex_1, xmm0\nmovsd xmm1, [rbp+var_8]\nmovsd xmm0, cs:qword_20E0\nmulsd xmm0, xmm1\nmovapd xmm1, xmm0\nmulsd xmm1, [rbp+var_18]\nmovsd xmm0, [rbp+var_10]\nmovapd xmm2, xmm0\nmulsd xmm2, xmm0\nmovapd xmm0, xmm1\nsubsd xmm0, xmm2\nmovsd xmm2, [rbp+var_8]\nmovsd xmm1, cs:qword_20E0\nmulsd xmm1, xmm2\ndivsd xmm0, xmm1\nmovsd cs:qword_4028, xmm0\nlea rax, vertex_1\npop rbp\nretn", + "ida_pseudo": "__int64 *__fastcall func0(double a1, double a2, double a3)\n{\n *(double *)&vertex_1 = -a2 / (a1 + a1);\n *(double *)&qword_4028 = (4.0 * a1 * a3 - a2 * a2) / (4.0 * a1);\n return &vertex_1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmovsd [rbp+var_8], xmm0\nmovsd [rbp+var_10], xmm1\nmovsd [rbp+var_18], xmm2\nmovsd xmm0, [rbp+var_10]\nmovq xmm1, cs:qword_20D0\nxorpd xmm1, xmm0\nmovsd xmm0, [rbp+var_8]\nmovapd xmm2, xmm0\naddsd xmm2, xmm0\ndivsd xmm1, xmm2\nmovapd xmm0, xmm1\nmovsd cs:qword_4020, xmm0\nmovsd xmm1, [rbp+var_8]\nmovsd xmm0, cs:qword_20E0\nmulsd xmm0, xmm1\nmovapd xmm1, xmm0\nmulsd xmm1, [rbp+var_18]\nmovsd xmm0, [rbp+var_10]\nmovapd xmm2, xmm0\nmulsd xmm2, xmm0\nmovapd xmm0, xmm1\nsubsd xmm0, xmm2\nmovsd xmm2, [rbp+var_8]\nmovsd xmm1, cs:qword_20E0\nmulsd xmm1, xmm2\ndivsd xmm0, xmm1\nmovsd cs:qword_4028, xmm0\nlea rax, qword_4020\npop rbp\nretn", + "ida_strip_pseudo": "__int64 *__fastcall sub_1149(double a1, double a2, double a3)\n{\n *(double *)&qword_4020 = -a2 / (a1 + a1);\n *(double *)&qword_4028 = (4.0 * a1 * a3 - a2 * a2) / (4.0 * a1);\n return &qword_4020;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long *sub_1149(double a1, double a2, double a3) {\n *(double *)&qword_4020 = -a2 / (a1 + a1);\n *(double *)&qword_4028 = (4.0 * a1 * a3 - a2 * a2) / (4.0 * a1);\n return &qword_4020;\n}", + "ida_pseudo_norm": "long long *func0(double a1, double a2, double a3) {\n *(double *)&vertex_1 = -a2 / (a1 + a1);\n *(double *)&qword_4028 = (4.0 * a1 * a3 - a2 * a2) / (4.0 * a1);\n return &vertex_1;\n}" + }, + { + "index": 154, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int nums[][4], int rows, int N, int* result) {\n for (int i = 0; i < rows; i++) {\n result[i] = nums[i][N];\n }\n return result;\n}", + "test": "int main() {\n\n int nums[3][4] = {{1, 2, 3, 2}, {4, 5, 6, 2}, {7, 1, 9, 5}};\n\n int result[3];\n\n\n\n func0(nums, 3, 0, result);\n\n assert(result[0] == 1 && result[1] == 4 && result[2] == 7);\n\n\n\n func0(nums, 3, 2, result);\n\n assert(result[0] == 3 && result[1] == 6 && result[2] == 9);\n\n\n\n func0(nums, 3, 3, result);\n\n assert(result[0] == 2 && result[1] == 2 && result[2] == 5);\n\n\n\n printf(\"All tests passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmov %rcx,-0x28(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11de \nmov -0x4(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rax,%rdx\nmov -0x20(%rbp),%eax\ncltq\nmov (%rcx,%rax,4),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11a8 \nmov -0x28(%rbp),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_28], rcx\nmov [rbp+var_4], 0\njmp short loc_11DE\nloc_11A8:\nmov eax, [rbp+var_4]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov eax, [rbp+var_20]\ncdqe\nmov eax, [rcx+rax*4]\nmov [rdx], eax\nadd [rbp+var_4], 1\nloc_11DE:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11A8\nmov rax, [rbp+var_28]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3, __int64 a4)\n{\n int i; // [rsp+24h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n *(_DWORD *)(a4 + 4LL * i) = *(_DWORD *)(16LL * i + a1 + 4LL * a3);\n return a4;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_28], rcx\nmov [rbp+var_4], 0\njmp short loc_11DE\nloc_11A8:\nmov eax, [rbp+var_4]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov eax, [rbp+var_20]\ncdqe\nmov eax, [rcx+rax*4]\nmov [rdx], eax\nadd [rbp+var_4], 1\nloc_11DE:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11A8\nmov rax, [rbp+var_28]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2, int a3, __int64 a4)\n{\n int i; // [rsp+24h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n *(_DWORD *)(a4 + 4LL * i) = *(_DWORD *)(16LL * i + a1 + 4LL * a3);\n return a4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2, int a3, long long a4) {\n int i;\n for (i = 0; i < a2; ++i)\n *(uint32_t *)(a4 + 4LL * i) = *(uint32_t *)(16LL * i + a1 + 4LL * a3);\n return a4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3, long long a4) {\n int i;\n for (i = 0; i < a2; ++i)\n *(uint32_t *)(a4 + 4LL * i) = *(uint32_t *)(16LL * i + a1 + 4LL * a3);\n return a4;\n}" + }, + { + "index": 154, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int nums[][4], int rows, int N, int* result) {\n for (int i = 0; i < rows; i++) {\n result[i] = nums[i][N];\n }\n return result;\n}", + "test": "int main() {\n\n int nums[3][4] = {{1, 2, 3, 2}, {4, 5, 6, 2}, {7, 1, 9, 5}};\n\n int result[3];\n\n\n\n func0(nums, 3, 0, result);\n\n assert(result[0] == 1 && result[1] == 4 && result[2] == 7);\n\n\n\n func0(nums, 3, 2, result);\n\n assert(result[0] == 3 && result[1] == 6 && result[2] == 9);\n\n\n\n func0(nums, 3, 3, result);\n\n assert(result[0] == 2 && result[1] == 2 && result[2] == 5);\n\n\n\n printf(\"All tests passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rcx,%rax\ntest %esi,%esi\njle 11b7 \nmovslq %edx,%rdx\nlea (%rdi,%rdx,4),%rdi\nmov %rcx,%rdx\nlea -0x1(%rsi),%ecx\nlea 0x4(%rax,%rcx,4),%r8\nmov (%rdi),%esi\nmov %esi,(%rdx)\nadd $0x10,%rdi\nadd $0x4,%rdx\ncmp %r8,%rdx\njne 11a6 \nretq\n", + "ida_asm": "func0:\nendbr64\nmov rax, rcx\ntest esi, esi\njle short locret_11B6\nmovsxd rdx, edx\nlea rdi, [rdi+rdx*4]\nmov rdx, rcx\nmovsxd rsi, esi\nlea r8, [rcx+rsi*4]\nloc_11A5:\nmov esi, [rdi]\nmov [rdx], esi\nadd rdi, 10h\nadd rdx, 4\ncmp rdx, r8\njnz short loc_11A5\nlocret_11B6:\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, int a3, _DWORD *a4)\n{\n _DWORD *result; // rax\n _DWORD *v5; // rdi\n _DWORD *v6; // rdx\n\n result = a4;\n if ( a2 > 0 )\n {\n v5 = (_DWORD *)(a1 + 4LL * a3);\n v6 = a4;\n do\n {\n *v6 = *v5;\n v5 += 4;\n ++v6;\n }\n while ( v6 != &a4[a2] );\n }\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\nmov rax, rcx\ntest esi, esi\njle short locret_11B6\nmovsxd rdx, edx\nlea rdi, [rdi+rdx*4]\nmov rdx, rcx\nmovsxd rsi, esi\nlea r8, [rcx+rsi*4]\nloc_11A5:\nmov esi, [rdi]\nmov [rdx], esi\nadd rdi, 10h\nadd rdx, 4\ncmp rdx, r8\njnz short loc_11A5\nlocret_11B6:\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1189(__int64 a1, int a2, int a3, _DWORD *a4)\n{\n _DWORD *result; // rax\n _DWORD *v5; // rdi\n _DWORD *v6; // rdx\n\n result = a4;\n if ( a2 > 0 )\n {\n v5 = (_DWORD *)(a1 + 4LL * a3);\n v6 = a4;\n do\n {\n *v6 = *v5;\n v5 += 4;\n ++v6;\n }\n while ( v6 != &a4[a2] );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1189(long long a1, int a2, int a3, uint32_t *a4) {\n uint32_t *result;\n uint32_t *v5;\n uint32_t *v6;\n result = a4;\n if (a2 > 0) {\n v5 = (uint32_t *)(a1 + 4LL * a3);\n v6 = a4;\n do {\n *v6 = *v5;\n v5 += 4;\n ++v6;\n } while (v6 != &a4[a2]);\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, int a3, uint32_t *a4) {\n uint32_t *result;\n uint32_t *v5;\n uint32_t *v6;\n result = a4;\n if (a2 > 0) {\n v5 = (uint32_t *)(a1 + 4LL * a3);\n v6 = a4;\n do {\n *v6 = *v5;\n v5 += 4;\n ++v6;\n } while (v6 != &a4[a2]);\n }\n return result;\n}" + }, + { + "index": 155, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int res = 0, count = 0, temp = n;\n while (temp > 0) {\n if (count % 2 == 1) {\n res = res | (1 << count);\n }\n count++;\n temp >>= 1;\n }\n return n ^ res;\n}", + "test": "int main() {\n\n assert(func0(10) == 0);\n\n assert(func0(20) == 30);\n\n assert(func0(30) == 20);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\nmov -0x14(%rbp),%eax\nmov %eax,-0x4(%rbp)\njmp 1195 \nmov -0x8(%rbp),%eax\ncltd\nshr $0x1f,%edx\nadd %edx,%eax\nand $0x1,%eax\nsub %edx,%eax\ncmp $0x1,%eax\njne 118e \nmov -0x8(%rbp),%eax\nmov $0x1,%edx\nmov %eax,%ecx\nshl %cl,%edx\nmov %edx,%eax\nor %eax,-0xc(%rbp)\naddl $0x1,-0x8(%rbp)\nsarl -0x4(%rbp)\ncmpl $0x0,-0x4(%rbp)\njg 116a \nmov -0x14(%rbp),%eax\nxor -0xc(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\nmov eax, [rbp+var_14]\nmov [rbp+var_4], eax\njmp short loc_119B\nloc_116A:\nmov edx, [rbp+var_8]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\ncmp eax, 1\njnz short loc_1194\nmov eax, [rbp+var_8]\nmov edx, 1\nmov ecx, eax\nshl edx, cl\nmov eax, edx\nor [rbp+var_C], eax\nloc_1194:\nadd [rbp+var_8], 1\nsar [rbp+var_4], 1\nloc_119B:\ncmp [rbp+var_4], 0\njg short loc_116A\nmov eax, [rbp+var_14]\nxor eax, [rbp+var_C]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v2; // [rsp+8h] [rbp-Ch]\n int v3; // [rsp+Ch] [rbp-8h]\n int i; // [rsp+10h] [rbp-4h]\n\n v2 = 0;\n v3 = 0;\n for ( i = a1; i > 0; i >>= 1 )\n {\n if ( v3 % 2 == 1 )\n v2 |= 1 << v3;\n ++v3;\n }\n return v2 ^ (unsigned int)a1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\nmov eax, [rbp+var_14]\nmov [rbp+var_4], eax\njmp short loc_119B\nloc_116A:\nmov edx, [rbp+var_8]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\ncmp eax, 1\njnz short loc_1194\nmov eax, [rbp+var_8]\nmov edx, 1\nmov ecx, eax\nshl edx, cl\nmov eax, edx\nor [rbp+var_C], eax\nloc_1194:\nadd [rbp+var_8], 1\nsar [rbp+var_4], 1\nloc_119B:\ncmp [rbp+var_4], 0\njg short loc_116A\nmov eax, [rbp+var_14]\nxor eax, [rbp+var_C]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v2; // [rsp+8h] [rbp-Ch]\n int v3; // [rsp+Ch] [rbp-8h]\n int i; // [rsp+10h] [rbp-4h]\n\n v2 = 0;\n v3 = 0;\n for ( i = a1; i > 0; i >>= 1 )\n {\n if ( v3 % 2 == 1 )\n v2 |= 1 << v3;\n ++v3;\n }\n return v2 ^ (unsigned int)a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v2;\n int v3;\n int i;\n v2 = 0;\n v3 = 0;\n for (i = a1; i > 0; i >>= 1) {\n if (v3 % 2 == 1) v2 |= 1 << v3;\n ++v3;\n }\n return v2 ^ (unsigned int)a1;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v2;\n int v3;\n int i;\n v2 = 0;\n v3 = 0;\n for (i = a1; i > 0; i >>= 1) {\n if (v3 % 2 == 1) v2 |= 1 << v3;\n ++v3;\n }\n return v2 ^ (unsigned int)a1;\n}" + }, + { + "index": 155, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int res = 0, count = 0, temp = n;\n while (temp > 0) {\n if (count % 2 == 1) {\n res = res | (1 << count);\n }\n count++;\n temp >>= 1;\n }\n return n ^ res;\n}", + "test": "int main() {\n\n assert(func0(10) == 0);\n\n assert(func0(20) == 30);\n\n assert(func0(30) == 20);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %edi,%r10d\nmov %edi,%esi\nmov $0x0,%ecx\nmov $0x0,%eax\nmov $0x1,%r9d\ntest %edi,%edi\njle 1193 \nadd $0x1,%ecx\nsar %esi\ntest %esi,%esi\njle 1193 \nmov %ecx,%r8d\nshr $0x1f,%r8d\nlea (%rcx,%r8,1),%edx\nand $0x1,%edx\nsub %r8d,%edx\nmov %eax,%r8d\nmov %r9d,%edi\nshl %cl,%edi\nor %edi,%eax\ncmp $0x1,%edx\ncmovne %r8d,%eax\njmp 1166 \nxor %r10d,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov eax, edi\ntest edi, edi\njle short loc_1198\nmov r8d, edi\nmov ecx, 0\nmov esi, 0\nmov r11d, 1\nloc_1166:\nmov r9d, ecx\nshr r9d, 1Fh\nlea edx, [rcx+r9]\nand edx, 1\nsub edx, r9d\nmov r9d, esi\nmov r10d, r11d\nshl r10d, cl\nor esi, r10d\ncmp edx, 1\ncmovnz esi, r9d\nadd ecx, 1\nsar r8d, 1\ntest r8d, r8d\njg short loc_1166\nloc_1195:\nxor eax, esi\nretn\nloc_1198:\nmov esi, 0\njmp short loc_1195", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // r8d\n int v2; // ecx\n int v3; // esi\n int v4; // r9d\n\n if ( a1 <= 0 )\n {\n v3 = 0;\n }\n else\n {\n v1 = a1;\n v2 = 0;\n v3 = 0;\n do\n {\n v4 = v3;\n v3 |= 1 << v2;\n if ( v2 % 2 != 1 )\n v3 = v4;\n ++v2;\n v1 >>= 1;\n }\n while ( v1 > 0 );\n }\n return v3 ^ (unsigned int)a1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmov eax, edi\ntest edi, edi\njle short loc_1198\nmov r8d, edi\nmov ecx, 0\nmov esi, 0\nmov r11d, 1\nloc_1166:\nmov r9d, ecx\nshr r9d, 1Fh\nlea edx, [rcx+r9]\nand edx, 1\nsub edx, r9d\nmov r9d, esi\nmov r10d, r11d\nshl r10d, cl\nor esi, r10d\ncmp edx, 1\ncmovnz esi, r9d\nadd ecx, 1\nsar r8d, 1\ntest r8d, r8d\njg short loc_1166\nloc_1195:\nxor eax, esi\nretn\nloc_1198:\nmov esi, 0\njmp short loc_1195", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v1; // r8d\n int v2; // ecx\n int v3; // esi\n int v4; // r9d\n\n if ( a1 <= 0 )\n {\n v3 = 0;\n }\n else\n {\n v1 = a1;\n v2 = 0;\n v3 = 0;\n do\n {\n v4 = v3;\n v3 |= 1 << v2;\n if ( v2 % 2 != 1 )\n v3 = v4;\n ++v2;\n v1 >>= 1;\n }\n while ( v1 > 0 );\n }\n return v3 ^ (unsigned int)a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v1;\n int v2;\n int v3;\n int v4;\n if (a1 <= 0) {\n v3 = 0;\n } else {\n v1 = a1;\n v2 = 0;\n v3 = 0;\n do {\n v4 = v3;\n v3 |= 1 << v2;\n if (v2 % 2 != 1) v3 = v4;\n ++v2;\n v1 >>= 1;\n } while (v1 > 0);\n }\n return v3 ^ (unsigned int)a1;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v2;\n int v3;\n int v4;\n if (a1 <= 0) {\n v3 = 0;\n } else {\n v1 = a1;\n v2 = 0;\n v3 = 0;\n do {\n v4 = v3;\n v3 |= 1 << v2;\n if (v2 % 2 != 1) v3 = v4;\n ++v2;\n v1 >>= 1;\n } while (v1 > 0);\n }\n return v3 ^ (unsigned int)a1;\n}" + }, + { + "index": 155, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int res = 0, count = 0, temp = n;\n while (temp > 0) {\n if (count % 2 == 1) {\n res = res | (1 << count);\n }\n count++;\n temp >>= 1;\n }\n return n ^ res;\n}", + "test": "int main() {\n\n assert(func0(10) == 0);\n\n assert(func0(20) == 30);\n\n assert(func0(30) == 20);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov %edi,%edx\nxor %ecx,%ecx\nxor %eax,%eax\nmov $0x1,%r8d\ntest %edi,%edi\njle 1178 \nadd $0x1,%ecx\nsar %edx\nje 116e \ntest $0x1,%cl\nje 1154 \nmov %r8d,%esi\nshl %cl,%esi\nadd $0x1,%ecx\nor %esi,%eax\nsar %edx\njne 115b \nxor %edi,%eax\nretq\nnopl 0x0(%rax)\nmov %edi,%eax\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njle short loc_1228\nmov edx, edi\nxor ecx, ecx\nxor esi, esi\nmov eax, 1\nnop dword ptr [rax+rax+00h]\nloc_1208:\ntest cl, 1\njz short loc_1216\nmov r8d, eax\nshl r8d, cl\nor esi, r8d\nloc_1216:\nadd ecx, 1\nsar edx, 1\njnz short loc_1208\nmov eax, edi\nxor eax, esi\nretn\nloc_1228:\nmov eax, edi\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // edx\n char v2; // cl\n int v3; // esi\n\n if ( a1 <= 0 )\n return (unsigned int)a1;\n v1 = a1;\n v2 = 0;\n v3 = 0;\n do\n {\n if ( (v2 & 1) != 0 )\n v3 |= 1 << v2;\n ++v2;\n v1 >>= 1;\n }\n while ( v1 );\n return v3 ^ (unsigned int)a1;\n}", + "ida_strip_asm": "sub_11F0:\nendbr64\ntest edi, edi\njle short loc_1228\nmov edx, edi\nxor ecx, ecx\nxor esi, esi\nmov eax, 1\nnop dword ptr [rax+rax+00h]\nloc_1208:\ntest cl, 1\njz short loc_1216\nmov r8d, eax\nshl r8d, cl\nor esi, r8d\nloc_1216:\nadd ecx, 1\nsar edx, 1\njnz short loc_1208\nmov eax, edi\nxor eax, esi\nretn\nloc_1228:\nmov eax, edi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11F0(int a1)\n{\n int v1; // edx\n char v2; // cl\n int v3; // esi\n\n if ( a1 <= 0 )\n return (unsigned int)a1;\n v1 = a1;\n v2 = 0;\n v3 = 0;\n do\n {\n if ( (v2 & 1) != 0 )\n v3 |= 1 << v2;\n ++v2;\n v1 >>= 1;\n }\n while ( v1 );\n return v3 ^ (unsigned int)a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11F0(int a1) {\n int v1;\n char v2;\n int v3;\n if (a1 <= 0) return (unsigned int)a1;\n v1 = a1;\n v2 = 0;\n v3 = 0;\n do {\n if ((v2 & 1) != 0) v3 |= 1 << v2;\n ++v2;\n v1 >>= 1;\n } while (v1);\n return v3 ^ (unsigned int)a1;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n char v2;\n int v3;\n if (a1 <= 0) return (unsigned int)a1;\n v1 = a1;\n v2 = 0;\n v3 = 0;\n do {\n if ((v2 & 1) != 0) v3 |= 1 << v2;\n ++v2;\n v1 >>= 1;\n } while (v1);\n return v3 ^ (unsigned int)a1;\n}" + }, + { + "index": 156, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include // for atoi\n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n} TupleInt;\n\n\n\n\n\n", + "func": "void func0(const char *tuple_str[], int size, TupleInt result[]) {\n for (int i = 0; i < size; i++) {\n result[i].first = atoi(tuple_str[2 * i]);\n result[i].second = atoi(tuple_str[2 * i + 1]);\n }\n}", + "test": "int main() {\n\n const char *input1[] = {\"333\", \"33\", \"1416\", \"55\"};\n\n TupleInt result1[2];\n\n func0(input1, 2, result1);\n\n assert(result1[0].first == 333 && result1[0].second == 33);\n\n assert(result1[1].first == 1416 && result1[1].second == 55);\n\n\n\n const char *input2[] = {\"999\", \"99\", \"1000\", \"500\"};\n\n TupleInt result2[2];\n\n func0(input2, 2, result2);\n\n assert(result2[0].first == 999 && result2[0].second == 99);\n\n assert(result2[1].first == 1000 && result2[1].second == 500);\n\n\n\n const char *input3[] = {\"666\", \"66\", \"1500\", \"555\"};\n\n TupleInt result3[2];\n\n func0(input3, 2, result3);\n\n assert(result3[0].first == 666 && result3[0].second == 66);\n\n assert(result3[1].first == 1500 && result3[1].second == 555);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x38,%rsp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmov %rdx,-0x38(%rbp)\nmovl $0x0,-0x14(%rbp)\njmp 1225 \nmov -0x14(%rbp),%eax\nadd %eax,%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0x14(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x38(%rbp),%rdx\nlea (%rcx,%rdx,1),%rbx\nmov %rax,%rdi\ncallq 1090 \nmov %eax,(%rbx)\nmov -0x14(%rbp),%eax\nadd %eax,%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,8),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0x14(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x38(%rbp),%rdx\nlea (%rcx,%rdx,1),%rbx\nmov %rax,%rdi\ncallq 1090 \nmov %eax,0x4(%rbx)\naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 11aa \nadd $0x38,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmov [rbp+var_14], 0\njmp short loc_1225\nloc_11AA:\nmov eax, [rbp+var_14]\nadd eax, eax\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_38]\nlea rbx, [rcx+rdx]\nmov rdi, rax; nptr\ncall _atoi\nmov [rbx], eax\nmov eax, [rbp+var_14]\nadd eax, eax\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_38]\nlea rbx, [rcx+rdx]\nmov rdi, rax; nptr\ncall _atoi\nmov [rbx+4], eax\nadd [rbp+var_14], 1\nloc_1225:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl loc_11AA\nnop\nnop\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+2Ch] [rbp-14h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a2 )\n break;\n *(_DWORD *)(8LL * (int)i + a3) = atoi(*(const char **)(8LL * (int)(2 * i) + a1));\n *(_DWORD *)(8LL * (int)i + a3 + 4) = atoi(*(const char **)(8 * ((int)(2 * i) + 1LL) + a1));\n }\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmov [rbp+var_14], 0\njmp short loc_1225\nloc_11AA:\nmov eax, [rbp+var_14]\nadd eax, eax\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_38]\nlea rbx, [rcx+rdx]\nmov rdi, rax; nptr\ncall _atoi\nmov [rbx], eax\nmov eax, [rbp+var_14]\nadd eax, eax\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_38]\nlea rbx, [rcx+rdx]\nmov rdi, rax; nptr\ncall _atoi\nmov [rbx+4], eax\nadd [rbp+var_14], 1\nloc_1225:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl loc_11AA\nnop\nnop\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2, __int64 a3)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+2Ch] [rbp-14h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a2 )\n break;\n *(_DWORD *)(8LL * (int)i + a3) = atoi(*(const char **)(8LL * (int)(2 * i) + a1));\n *(_DWORD *)(8LL * (int)i + a3 + 4) = atoi(*(const char **)(8 * ((int)(2 * i) + 1LL) + a1));\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2, long long a3) {\n long long result;\n unsigned int i;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a2) break;\n *(uint32_t *)(8LL * (int)i + a3) =\n atoi(*(const char **)(8LL * (int)(2 * i) + a1));\n *(uint32_t *)(8LL * (int)i + a3 + 4) =\n atoi(*(const char **)(8 * ((int)(2 * i) + 1LL) + a1));\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3) {\n long long result;\n unsigned int i;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a2) break;\n *(uint32_t *)(8LL * (int)i + a3) =\n atoi(*(const char **)(8LL * (int)(2 * i) + a1));\n *(uint32_t *)(8LL * (int)i + a3 + 4) =\n atoi(*(const char **)(8 * ((int)(2 * i) + 1LL) + a1));\n }\n return result;\n}" + }, + { + "index": 156, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include // for atoi\n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n} TupleInt;\n\n\n\n\n\n", + "func": "void func0(const char *tuple_str[], int size, TupleInt result[]) {\n for (int i = 0; i < size; i++) {\n result[i].first = atoi(tuple_str[2 * i]);\n result[i].second = atoi(tuple_str[2 * i + 1]);\n }\n}", + "test": "int main() {\n\n const char *input1[] = {\"333\", \"33\", \"1416\", \"55\"};\n\n TupleInt result1[2];\n\n func0(input1, 2, result1);\n\n assert(result1[0].first == 333 && result1[0].second == 33);\n\n assert(result1[1].first == 1416 && result1[1].second == 55);\n\n\n\n const char *input2[] = {\"999\", \"99\", \"1000\", \"500\"};\n\n TupleInt result2[2];\n\n func0(input2, 2, result2);\n\n assert(result2[0].first == 999 && result2[0].second == 99);\n\n assert(result2[1].first == 1000 && result2[1].second == 500);\n\n\n\n const char *input3[] = {\"666\", \"66\", \"1500\", \"555\"};\n\n TupleInt result3[2];\n\n func0(input3, 2, result3);\n\n assert(result3[0].first == 666 && result3[0].second == 66);\n\n assert(result3[1].first == 1500 && result3[1].second == 555);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11e6 \npush %r12\npush %rbp\npush %rbx\nlea 0x8(%rdi),%rbx\nlea 0x4(%rdx),%rbp\nlea -0x1(%rsi),%eax\nshl $0x4,%rax\nlea 0x18(%rdi,%rax,1),%r12\nmov -0x8(%rbx),%rdi\nmov $0xa,%edx\nmov $0x0,%esi\ncallq 1090 \nmov %eax,-0x4(%rbp)\nmov $0xa,%edx\nmov $0x0,%esi\nmov (%rbx),%rdi\ncallq 1090 \nmov %eax,0x0(%rbp)\nadd $0x10,%rbx\nadd $0x8,%rbp\ncmp %r12,%rbx\njne 11a9 \npop %rbx\npop %rbp\npop %r12\nretq\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short locret_11E4\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nlea rbp, [rdx+4]\nmovsxd rsi, esi\nshl rsi, 4\nlea r12, [rdi+rsi]\nloc_11A7:\nmov rdi, [rbx]; nptr\nmov edx, 0Ah; base\nmov esi, 0; endptr\ncall _strtol\nmov [rbp-4], eax\nmov rdi, [rbx+8]; nptr\nmov edx, 0Ah; base\nmov esi, 0; endptr\ncall _strtol\nmov [rbp+0], eax\nadd rbx, 10h\nadd rbp, 8\ncmp rbx, r12\njnz short loc_11A7\npop rbx\npop rbp\npop r12\nretn\nlocret_11E4:\nretn", + "ida_pseudo": "void __fastcall func0(const char **a1, int a2, __int64 a3)\n{\n const char **v3; // rbx\n _DWORD *v4; // rbp\n\n if ( a2 > 0 )\n {\n v3 = a1;\n v4 = (_DWORD *)(a3 + 4);\n do\n {\n *(v4 - 1) = strtol(*v3, 0LL, 10);\n *v4 = strtol(v3[1], 0LL, 10);\n v3 += 2;\n v4 += 2;\n }\n while ( v3 != &a1[2 * a2] );\n }\n}", + "ida_strip_asm": "sub_1189:\nendbr64\ntest esi, esi\njle short locret_11E4\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nlea rbp, [rdx+4]\nmovsxd rsi, esi\nshl rsi, 4\nlea r12, [rdi+rsi]\nloc_11A7:\nmov rdi, [rbx]; nptr\nmov edx, 0Ah; base\nmov esi, 0; endptr\ncall _strtol\nmov [rbp-4], eax\nmov rdi, [rbx+8]; nptr\nmov edx, 0Ah; base\nmov esi, 0; endptr\ncall _strtol\nmov [rbp+0], eax\nadd rbx, 10h\nadd rbp, 8\ncmp rbx, r12\njnz short loc_11A7\npop rbx\npop rbp\npop r12\nretn\nlocret_11E4:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1189(const char **a1, int a2, __int64 a3)\n{\n const char **v3; // rbx\n _DWORD *v4; // rbp\n\n if ( a2 > 0 )\n {\n v3 = a1;\n v4 = (_DWORD *)(a3 + 4);\n do\n {\n *(v4 - 1) = strtol(*v3, 0LL, 10);\n *v4 = strtol(v3[1], 0LL, 10);\n v3 += 2;\n v4 += 2;\n }\n while ( v3 != &a1[2 * a2] );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1189(const char **a1, int a2, long long a3) {\n const char **v3;\n uint32_t *v4;\n if (a2 > 0) {\n v3 = a1;\n v4 = (uint32_t *)(a3 + 4);\n do {\n *(v4 - 1) = strtol(*v3, 0LL, 10);\n *v4 = strtol(v3[1], 0LL, 10);\n v3 += 2;\n v4 += 2;\n } while (v3 != &a1[2 * a2]);\n }\n}", + "ida_pseudo_norm": "void func0(const char **a1, int a2, long long a3) {\n const char **v3;\n uint32_t *v4;\n if (a2 > 0) {\n v3 = a1;\n v4 = (uint32_t *)(a3 + 4);\n do {\n *(v4 - 1) = strtol(*v3, 0LL, 10);\n *v4 = strtol(v3[1], 0LL, 10);\n v3 += 2;\n v4 += 2;\n } while (v3 != &a1[2 * a2]);\n }\n}" + }, + { + "index": 156, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include // for atoi\n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n} TupleInt;\n\n\n\n\n\n", + "func": "void func0(const char *tuple_str[], int size, TupleInt result[]) {\n for (int i = 0; i < size; i++) {\n result[i].first = atoi(tuple_str[2 * i]);\n result[i].second = atoi(tuple_str[2 * i + 1]);\n }\n}", + "test": "int main() {\n\n const char *input1[] = {\"333\", \"33\", \"1416\", \"55\"};\n\n TupleInt result1[2];\n\n func0(input1, 2, result1);\n\n assert(result1[0].first == 333 && result1[0].second == 33);\n\n assert(result1[1].first == 1416 && result1[1].second == 55);\n\n\n\n const char *input2[] = {\"999\", \"99\", \"1000\", \"500\"};\n\n TupleInt result2[2];\n\n func0(input2, 2, result2);\n\n assert(result2[0].first == 999 && result2[0].second == 99);\n\n assert(result2[1].first == 1000 && result2[1].second == 500);\n\n\n\n const char *input3[] = {\"666\", \"66\", \"1500\", \"555\"};\n\n TupleInt result3[2];\n\n func0(input3, 2, result3);\n\n assert(result3[0].first == 666 && result3[0].second == 66);\n\n assert(result3[1].first == 1500 && result3[1].second == 555);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1450 \nlea -0x1(%rsi),%eax\npush %r12\nshl $0x4,%rax\npush %rbp\nlea 0x4(%rdx),%rbp\npush %rbx\nlea 0x18(%rdi,%rax,1),%r12\nlea 0x8(%rdi),%rbx\nmov -0x8(%rbx),%rdi\nmov $0xa,%edx\nxor %esi,%esi\nadd $0x10,%rbx\nadd $0x8,%rbp\ncallq 1090 \nmov -0x10(%rbx),%rdi\nmov $0xa,%edx\nxor %esi,%esi\nmov %eax,-0xc(%rbp)\ncallq 1090 \nmov %eax,-0x8(%rbp)\ncmp %r12,%rbx\njne 1410 \npop %rbx\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax,%rax,1)\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short locret_1480\nmovsxd rsi, esi\npush r12\nshl rsi, 4\npush rbp\nlea rbp, [rdx+4]\npush rbx\nlea r12, [rdi+rsi]\nmov rbx, rdi\nxchg ax, ax\nloc_1440:\nmov rdi, [rbx]; nptr\nmov edx, 0Ah; base\nxor esi, esi; endptr\nadd rbx, 10h\nadd rbp, 8\ncall _strtol\nmov rdi, [rbx-8]; nptr\nmov edx, 0Ah; base\nxor esi, esi; endptr\nmov [rbp-0Ch], eax\ncall _strtol\nmov [rbp-8], eax\ncmp rbx, r12\njnz short loc_1440\npop rbx\npop rbp\npop r12\nretn\nlocret_1480:\nretn", + "ida_pseudo": "void __fastcall func0(const char **a1, int a2, __int64 a3)\n{\n __int64 v3; // rbp\n const char **v4; // r12\n const char **v5; // rbx\n const char *v6; // rdi\n int v7; // eax\n const char *v8; // rdi\n\n if ( a2 > 0 )\n {\n v3 = a3 + 4;\n v4 = &a1[2 * a2];\n v5 = a1;\n do\n {\n v6 = *v5;\n v5 += 2;\n v3 += 8LL;\n v7 = strtol(v6, 0LL, 10);\n v8 = *(v5 - 1);\n *(_DWORD *)(v3 - 12) = v7;\n *(_DWORD *)(v3 - 8) = strtol(v8, 0LL, 10);\n }\n while ( v5 != v4 );\n }\n}", + "ida_strip_asm": "sub_1420:\nendbr64\ntest esi, esi\njle short locret_1480\nmovsxd rsi, esi\npush r12\nshl rsi, 4\npush rbp\nlea rbp, [rdx+4]\npush rbx\nlea r12, [rdi+rsi]\nmov rbx, rdi\nxchg ax, ax\nloc_1440:\nmov rdi, [rbx]; nptr\nmov edx, 0Ah; base\nxor esi, esi; endptr\nadd rbx, 10h\nadd rbp, 8\ncall _strtol\nmov rdi, [rbx-8]; nptr\nmov edx, 0Ah; base\nxor esi, esi; endptr\nmov [rbp-0Ch], eax\ncall _strtol\nmov [rbp-8], eax\ncmp rbx, r12\njnz short loc_1440\npop rbx\npop rbp\npop r12\nretn\nlocret_1480:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1420(const char **a1, int a2, __int64 a3)\n{\n __int64 v3; // rbp\n const char **v4; // r12\n const char **v5; // rbx\n const char *v6; // rdi\n int v7; // eax\n const char *v8; // rdi\n\n if ( a2 > 0 )\n {\n v3 = a3 + 4;\n v4 = &a1[2 * a2];\n v5 = a1;\n do\n {\n v6 = *v5;\n v5 += 2;\n v3 += 8LL;\n v7 = strtol(v6, 0LL, 10);\n v8 = *(v5 - 1);\n *(_DWORD *)(v3 - 12) = v7;\n *(_DWORD *)(v3 - 8) = strtol(v8, 0LL, 10);\n }\n while ( v5 != v4 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1420(const char **a1, int a2, long long a3) {\n long long v3;\n const char **v4;\n const char **v5;\n const char *v6;\n int v7;\n const char *v8;\n if (a2 > 0) {\n v3 = a3 + 4;\n v4 = &a1[2 * a2];\n v5 = a1;\n do {\n v6 = *v5;\n v5 += 2;\n v3 += 8LL;\n v7 = strtol(v6, 0LL, 10);\n v8 = *(v5 - 1);\n *(uint32_t *)(v3 - 12) = v7;\n *(uint32_t *)(v3 - 8) = strtol(v8, 0LL, 10);\n } while (v5 != v4);\n }\n}", + "ida_pseudo_norm": "void func0(const char **a1, int a2, long long a3) {\n long long v3;\n const char **v4;\n const char **v5;\n const char *v6;\n int v7;\n const char *v8;\n if (a2 > 0) {\n v3 = a3 + 4;\n v4 = &a1[2 * a2];\n v5 = a1;\n do {\n v6 = *v5;\n v5 += 2;\n v3 += 8LL;\n v7 = strtol(v6, 0LL, 10);\n v8 = *(v5 - 1);\n *(uint32_t *)(v3 - 12) = v7;\n *(uint32_t *)(v3 - 8) = strtol(v8, 0LL, 10);\n } while (v5 != v4);\n }\n}" + }, + { + "index": 156, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include // for atoi\n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n} TupleInt;\n\n\n\n\n\n", + "func": "void func0(const char *tuple_str[], int size, TupleInt result[]) {\n for (int i = 0; i < size; i++) {\n result[i].first = atoi(tuple_str[2 * i]);\n result[i].second = atoi(tuple_str[2 * i + 1]);\n }\n}", + "test": "int main() {\n\n const char *input1[] = {\"333\", \"33\", \"1416\", \"55\"};\n\n TupleInt result1[2];\n\n func0(input1, 2, result1);\n\n assert(result1[0].first == 333 && result1[0].second == 33);\n\n assert(result1[1].first == 1416 && result1[1].second == 55);\n\n\n\n const char *input2[] = {\"999\", \"99\", \"1000\", \"500\"};\n\n TupleInt result2[2];\n\n func0(input2, 2, result2);\n\n assert(result2[0].first == 999 && result2[0].second == 99);\n\n assert(result2[1].first == 1000 && result2[1].second == 500);\n\n\n\n const char *input3[] = {\"666\", \"66\", \"1500\", \"555\"};\n\n TupleInt result3[2];\n\n func0(input3, 2, result3);\n\n assert(result3[0].first == 666 && result3[0].second == 66);\n\n assert(result3[1].first == 1500 && result3[1].second == 555);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1480 \nlea -0x1(%rsi),%eax\npush %r12\nshl $0x4,%rax\npush %rbp\nlea 0x4(%rdx),%rbp\npush %rbx\nlea 0x18(%rdi,%rax,1),%r12\nlea 0x8(%rdi),%rbx\nmov -0x8(%rbx),%rdi\nmov $0xa,%edx\nxor %esi,%esi\nadd $0x10,%rbx\nadd $0x8,%rbp\ncallq 1090 \nmov -0x10(%rbx),%rdi\nmov $0xa,%edx\nxor %esi,%esi\nmov %eax,-0xc(%rbp)\ncallq 1090 \nmov %eax,-0x8(%rbp)\ncmp %rbx,%r12\njne 1440 \npop %rbx\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax,%rax,1)\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short locret_1480\nmovsxd rsi, esi\npush r12\nshl rsi, 4\npush rbp\nlea rbp, [rdx+4]\npush rbx\nlea r12, [rdi+rsi]\nmov rbx, rdi\nxchg ax, ax\nloc_1440:\nmov rdi, [rbx]; nptr\nmov edx, 0Ah; base\nxor esi, esi; endptr\nadd rbx, 10h\nadd rbp, 8\ncall _strtol\nmov rdi, [rbx-8]; nptr\nmov edx, 0Ah; base\nxor esi, esi; endptr\nmov [rbp-0Ch], eax\ncall _strtol\nmov [rbp-8], eax\ncmp r12, rbx\njnz short loc_1440\npop rbx\npop rbp\npop r12\nretn\nlocret_1480:\nretn", + "ida_pseudo": "void __fastcall func0(const char **a1, int a2, __int64 a3)\n{\n __int64 v3; // rbp\n const char **v4; // r12\n const char **v5; // rbx\n const char *v6; // rdi\n int v7; // eax\n const char *v8; // rdi\n\n if ( a2 > 0 )\n {\n v3 = a3 + 4;\n v4 = &a1[2 * a2];\n v5 = a1;\n do\n {\n v6 = *v5;\n v5 += 2;\n v3 += 8LL;\n v7 = strtol(v6, 0LL, 10);\n v8 = *(v5 - 1);\n *(_DWORD *)(v3 - 12) = v7;\n *(_DWORD *)(v3 - 8) = strtol(v8, 0LL, 10);\n }\n while ( v4 != v5 );\n }\n}", + "ida_strip_asm": "sub_1420:\nendbr64\ntest esi, esi\njle short locret_1480\nmovsxd rsi, esi\npush r12\nshl rsi, 4\npush rbp\nlea rbp, [rdx+4]\npush rbx\nlea r12, [rdi+rsi]\nmov rbx, rdi\nxchg ax, ax\nloc_1440:\nmov rdi, [rbx]; nptr\nmov edx, 0Ah; base\nxor esi, esi; endptr\nadd rbx, 10h\nadd rbp, 8\ncall _strtol\nmov rdi, [rbx-8]; nptr\nmov edx, 0Ah; base\nxor esi, esi; endptr\nmov [rbp-0Ch], eax\ncall _strtol\nmov [rbp-8], eax\ncmp r12, rbx\njnz short loc_1440\npop rbx\npop rbp\npop r12\nretn\nlocret_1480:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1420(const char **a1, int a2, __int64 a3)\n{\n __int64 v3; // rbp\n const char **v4; // r12\n const char **v5; // rbx\n const char *v6; // rdi\n int v7; // eax\n const char *v8; // rdi\n\n if ( a2 > 0 )\n {\n v3 = a3 + 4;\n v4 = &a1[2 * a2];\n v5 = a1;\n do\n {\n v6 = *v5;\n v5 += 2;\n v3 += 8LL;\n v7 = strtol(v6, 0LL, 10);\n v8 = *(v5 - 1);\n *(_DWORD *)(v3 - 12) = v7;\n *(_DWORD *)(v3 - 8) = strtol(v8, 0LL, 10);\n }\n while ( v4 != v5 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1420(const char **a1, int a2, long long a3) {\n long long v3;\n const char **v4;\n const char **v5;\n const char *v6;\n int v7;\n const char *v8;\n if (a2 > 0) {\n v3 = a3 + 4;\n v4 = &a1[2 * a2];\n v5 = a1;\n do {\n v6 = *v5;\n v5 += 2;\n v3 += 8LL;\n v7 = strtol(v6, 0LL, 10);\n v8 = *(v5 - 1);\n *(uint32_t *)(v3 - 12) = v7;\n *(uint32_t *)(v3 - 8) = strtol(v8, 0LL, 10);\n } while (v4 != v5);\n }\n}", + "ida_pseudo_norm": "void func0(const char **a1, int a2, long long a3) {\n long long v3;\n const char **v4;\n const char **v5;\n const char *v6;\n int v7;\n const char *v8;\n if (a2 > 0) {\n v3 = a3 + 4;\n v4 = &a1[2 * a2];\n v5 = a1;\n do {\n v6 = *v5;\n v5 += 2;\n v3 += 8LL;\n v7 = strtol(v6, 0LL, 10);\n v8 = *(v5 - 1);\n *(uint32_t *)(v3 - 12) = v7;\n *(uint32_t *)(v3 - 8) = strtol(v8, 0LL, 10);\n } while (v4 != v5);\n }\n}" + }, + { + "index": 157, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\nstruct Pair {\n\n int count;\n\n char value;\n\n};\n\n\n\n", + "func": "struct Pair *func0(char *list1, int *returnSize) {\n struct Pair *result =\n (struct Pair *)malloc(sizeof(struct Pair) * strlen(list1));\n char current = list1[0];\n int count = 1;\n int res_idx = 0;\n for (int i = 1; list1[i] != '\\0'; i++) {\n if (list1[i] == current) {\n count++;\n } else {\n result[res_idx].count = count;\n result[res_idx].value = current;\n res_idx++;\n current = list1[i];\n count = 1;\n }\n }\n result[res_idx].count = count;\n result[res_idx].value = current;\n res_idx++;\n *returnSize = res_idx;\n return result;\n}", + "test": "int main() {\n\n int size1, size2, size3;\n\n \n\n struct Pair *encoded1 = func0(\"11234\", &size1);\n\n assert(size1 == 4 && encoded1[0].count == 2 && encoded1[0].value == '1' &&\n\n encoded1[1].count == 1 && encoded1[1].value == '2' &&\n\n encoded1[2].count == 1 && encoded1[2].value == '3' &&\n\n encoded1[3].count == 1 && encoded1[3].value == '4');\n\n\n\n struct Pair *encoded2 = func0(\"automatically\", &size2);\n\n assert(size2 == 12 && encoded2[10].count == 2 && encoded2[10].value == 'l');\n\n \n\n struct Pair *encoded3 = func0(\"python\", &size3);\n\n assert(size3 == 6 && encoded3[0].count == 1 && encoded3[0].value == 'p');\n\n \n\n free(encoded1);\n\n free(encoded2);\n\n free(encoded3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x28(%rbp)\nmov %rsi,-0x30(%rbp)\nmov -0x28(%rbp),%rax\nmov %rax,%rdi\ncallq 10a0 \nshl $0x3,%rax\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,-0x8(%rbp)\nmov -0x28(%rbp),%rax\nmovzbl (%rax),%eax\nmov %al,-0x15(%rbp)\nmovl $0x1,-0x14(%rbp)\nmovl $0x0,-0x10(%rbp)\nmovl $0x1,-0xc(%rbp)\njmp 128b \nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp %al,-0x15(%rbp)\njne 1235 \naddl $0x1,-0x14(%rbp)\njmp 1287 \nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov -0x14(%rbp),%eax\nmov %eax,(%rdx)\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmovzbl -0x15(%rbp),%eax\nmov %al,0x4(%rdx)\naddl $0x1,-0x10(%rbp)\nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmov %al,-0x15(%rbp)\nmovl $0x1,-0x14(%rbp)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 121a \nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov -0x14(%rbp),%eax\nmov %eax,(%rdx)\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmovzbl -0x15(%rbp),%eax\nmov %al,0x4(%rdx)\naddl $0x1,-0x10(%rbp)\nmov -0x30(%rbp),%rax\nmov -0x10(%rbp),%edx\nmov %edx,(%rax)\nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov [rbp+var_30], rsi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov rax, [rbp+s]\nmovzx eax, byte ptr [rax]\nmov [rbp+var_15], al\nmov [rbp+var_14], 1\nmov [rbp+var_10], 0\nmov [rbp+var_C], 1\njmp short loc_128B\nloc_121A:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp [rbp+var_15], al\njnz short loc_1235\nadd [rbp+var_14], 1\njmp short loc_1287\nloc_1235:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_14]\nmov [rdx], eax\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmovzx eax, [rbp+var_15]\nmov [rdx+4], al\nadd [rbp+var_10], 1\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_15], al\nmov [rbp+var_14], 1\nloc_1287:\nadd [rbp+var_C], 1\nloc_128B:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_121A\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_14]\nmov [rdx], eax\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmovzx eax, [rbp+var_15]\nmov [rdx+4], al\nadd [rbp+var_10], 1\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_10]\nmov [rax], edx\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(const char *a1, _DWORD *a2)\n{\n size_t v2; // rax\n char v4; // [rsp+1Bh] [rbp-15h]\n int v5; // [rsp+1Ch] [rbp-14h]\n int v6; // [rsp+20h] [rbp-10h]\n int i; // [rsp+24h] [rbp-Ch]\n _DWORD *v8; // [rsp+28h] [rbp-8h]\n\n v2 = strlen(a1);\n v8 = malloc(8 * v2);\n v4 = *a1;\n v5 = 1;\n v6 = 0;\n for ( i = 1; a1[i]; ++i )\n {\n if ( v4 == a1[i] )\n {\n ++v5;\n }\n else\n {\n v8[2 * v6] = v5;\n LOBYTE(v8[2 * v6++ + 1]) = v4;\n v4 = a1[i];\n v5 = 1;\n }\n }\n v8[2 * v6] = v5;\n LOBYTE(v8[2 * v6 + 1]) = v4;\n *a2 = v6 + 1;\n return v8;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov [rbp+var_30], rsi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov rax, [rbp+s]\nmovzx eax, byte ptr [rax]\nmov [rbp+var_15], al\nmov [rbp+var_14], 1\nmov [rbp+var_10], 0\nmov [rbp+var_C], 1\njmp short loc_128B\nloc_121A:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp [rbp+var_15], al\njnz short loc_1235\nadd [rbp+var_14], 1\njmp short loc_1287\nloc_1235:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_14]\nmov [rdx], eax\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmovzx eax, [rbp+var_15]\nmov [rdx+4], al\nadd [rbp+var_10], 1\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_15], al\nmov [rbp+var_14], 1\nloc_1287:\nadd [rbp+var_C], 1\nloc_128B:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_121A\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_14]\nmov [rdx], eax\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmovzx eax, [rbp+var_15]\nmov [rdx+4], al\nadd [rbp+var_10], 1\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_10]\nmov [rax], edx\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11C9(const char *a1, _DWORD *a2)\n{\n size_t v2; // rax\n char v4; // [rsp+1Bh] [rbp-15h]\n int v5; // [rsp+1Ch] [rbp-14h]\n int v6; // [rsp+20h] [rbp-10h]\n int i; // [rsp+24h] [rbp-Ch]\n _DWORD *v8; // [rsp+28h] [rbp-8h]\n\n v2 = strlen(a1);\n v8 = malloc(8 * v2);\n v4 = *a1;\n v5 = 1;\n v6 = 0;\n for ( i = 1; a1[i]; ++i )\n {\n if ( v4 == a1[i] )\n {\n ++v5;\n }\n else\n {\n v8[2 * v6] = v5;\n LOBYTE(v8[2 * v6++ + 1]) = v4;\n v4 = a1[i];\n v5 = 1;\n }\n }\n v8[2 * v6] = v5;\n LOBYTE(v8[2 * v6 + 1]) = v4;\n *a2 = v6 + 1;\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11C9(const char *a1, uint32_t *a2) {\n unsigned int v2;\n char v4;\n int v5;\n int v6;\n int i;\n uint32_t *v8;\n v2 = strlen(a1);\n v8 = malloc(8 * v2);\n v4 = *a1;\n v5 = 1;\n v6 = 0;\n for (i = 1; a1[i]; ++i) {\n if (v4 == a1[i]) {\n ++v5;\n } else {\n v8[2 * v6] = v5;\n LOBYTE(v8[2 * v6++ + 1]) = v4;\n v4 = a1[i];\n v5 = 1;\n }\n }\n v8[2 * v6] = v5;\n LOBYTE(v8[2 * v6 + 1]) = v4;\n *a2 = v6 + 1;\n return v8;\n}", + "ida_pseudo_norm": "uint32_t *func0(const char *a1, uint32_t *a2) {\n unsigned int v2;\n char v4;\n int v5;\n int v6;\n int i;\n uint32_t *v8;\n v2 = strlen(a1);\n v8 = malloc(8 * v2);\n v4 = *a1;\n v5 = 1;\n v6 = 0;\n for (i = 1; a1[i]; ++i) {\n if (v4 == a1[i]) {\n ++v5;\n } else {\n v8[2 * v6] = v5;\n LOBYTE(v8[2 * v6++ + 1]) = v4;\n v4 = a1[i];\n v5 = 1;\n }\n }\n v8[2 * v6] = v5;\n LOBYTE(v8[2 * v6 + 1]) = v4;\n *a2 = v6 + 1;\n return v8;\n}" + }, + { + "index": 157, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\nstruct Pair {\n\n int count;\n\n char value;\n\n};\n\n\n\n", + "func": "struct Pair *func0(char *list1, int *returnSize) {\n struct Pair *result =\n (struct Pair *)malloc(sizeof(struct Pair) * strlen(list1));\n char current = list1[0];\n int count = 1;\n int res_idx = 0;\n for (int i = 1; list1[i] != '\\0'; i++) {\n if (list1[i] == current) {\n count++;\n } else {\n result[res_idx].count = count;\n result[res_idx].value = current;\n res_idx++;\n current = list1[i];\n count = 1;\n }\n }\n result[res_idx].count = count;\n result[res_idx].value = current;\n res_idx++;\n *returnSize = res_idx;\n return result;\n}", + "test": "int main() {\n\n int size1, size2, size3;\n\n \n\n struct Pair *encoded1 = func0(\"11234\", &size1);\n\n assert(size1 == 4 && encoded1[0].count == 2 && encoded1[0].value == '1' &&\n\n encoded1[1].count == 1 && encoded1[1].value == '2' &&\n\n encoded1[2].count == 1 && encoded1[2].value == '3' &&\n\n encoded1[3].count == 1 && encoded1[3].value == '4');\n\n\n\n struct Pair *encoded2 = func0(\"automatically\", &size2);\n\n assert(size2 == 12 && encoded2[10].count == 2 && encoded2[10].value == 'l');\n\n \n\n struct Pair *encoded3 = func0(\"python\", &size3);\n\n assert(size3 == 6 && encoded3[0].count == 1 && encoded3[0].value == 'p');\n\n \n\n free(encoded1);\n\n free(encoded2);\n\n free(encoded3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbx\nmov %rsi,%rbp\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nlea -0x8(,%rcx,8),%rdi\ncallq 10b0 \nmovzbl (%rbx),%esi\nmovzbl 0x1(%rbx),%edx\ntest %dl,%dl\nje 1223 \nlea 0x2(%rbx),%rdi\nmov $0x0,%ecx\nmov $0x1,%r8d\njmp 1218 \nmovslq %ecx,%r9\nlea (%rax,%r9,8),%r9\nmov %r8d,(%r9)\nmov %sil,0x4(%r9)\nadd $0x1,%ecx\nmov %edx,%esi\nmov $0x1,%r8d\nadd $0x1,%rdi\nmovzbl -0x1(%rdi),%edx\ntest %dl,%dl\nje 122e \ncmp %sil,%dl\njne 11f3 \nadd $0x1,%r8d\njmp 120c \nmov $0x0,%ecx\nmov $0x1,%r8d\nmovslq %ecx,%rdx\nlea (%rax,%rdx,8),%rdx\nmov %r8d,(%rdx)\nmov %sil,0x4(%rdx)\nadd $0x1,%ecx\nmov %ecx,0x0(%rbp)\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov rbp, rsi\ncall _strlen\nlea rdi, ds:0[rax*8]; size\ncall _malloc\nmovzx edi, byte ptr [rbx]\nmovzx ecx, byte ptr [rbx+1]\ntest cl, cl\njz short loc_123C\nlea rdx, [rbx+2]\nmov r8d, 0\nmov r9d, 1\njmp short loc_121D\nloc_1208:\nadd r9d, 1\nloc_120C:\nadd rdx, 1\nmovzx esi, byte ptr [rdx-1]\nmov edi, ecx\ntest sil, sil\njz short loc_124A\nmov ecx, esi\nloc_121D:\ncmp cl, dil\njz short loc_1208\nmovsxd rsi, r8d\nlea rsi, [rax+rsi*8]\nmov [rsi], r9d\nmov [rsi+4], dil\nadd r8d, 1\nmov r9d, 1\njmp short loc_120C\nloc_123C:\nmov ecx, edi\nmov r8d, 0\nmov r9d, 1\nloc_124A:\nmovsxd rdx, r8d\nlea rdx, [rax+rdx*8]\nmov [rdx], r9d\nmov [rdx+4], cl\nadd r8d, 1\nmov [rbp+0], r8d\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, _DWORD *a2)\n{\n size_t v4; // rax\n char *result; // rax\n char v6; // di\n char v7; // cl\n __int64 v8; // rdx\n int v9; // r8d\n int v10; // r9d\n char *v11; // rsi\n char *v12; // rdx\n\n v4 = strlen((const char *)a1);\n result = (char *)malloc(8 * v4);\n v6 = *(_BYTE *)a1;\n v7 = *(_BYTE *)(a1 + 1);\n if ( v7 )\n {\n v8 = a1 + 2;\n v9 = 0;\n v10 = 1;\n while ( 1 )\n {\n if ( v7 == v6 )\n {\n ++v10;\n }\n else\n {\n v11 = &result[8 * v9];\n *(_DWORD *)v11 = v10;\n v11[4] = v6;\n ++v9;\n v10 = 1;\n }\n ++v8;\n v6 = v7;\n if ( !*(_BYTE *)(v8 - 1) )\n break;\n v7 = *(_BYTE *)(v8 - 1);\n }\n }\n else\n {\n v7 = v6;\n v9 = 0;\n v10 = 1;\n }\n v12 = &result[8 * v9];\n *(_DWORD *)v12 = v10;\n v12[4] = v7;\n *a2 = v9 + 1;\n return result;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov rbp, rsi\ncall _strlen\nlea rdi, ds:0[rax*8]; size\ncall _malloc\nmovzx edi, byte ptr [rbx]\nmovzx ecx, byte ptr [rbx+1]\ntest cl, cl\njz short loc_123C\nlea rdx, [rbx+2]\nmov r8d, 0\nmov r9d, 1\njmp short loc_121D\nloc_1208:\nadd r9d, 1\nloc_120C:\nadd rdx, 1\nmovzx esi, byte ptr [rdx-1]\nmov edi, ecx\ntest sil, sil\njz short loc_124A\nmov ecx, esi\nloc_121D:\ncmp cl, dil\njz short loc_1208\nmovsxd rsi, r8d\nlea rsi, [rax+rsi*8]\nmov [rsi], r9d\nmov [rsi+4], dil\nadd r8d, 1\nmov r9d, 1\njmp short loc_120C\nloc_123C:\nmov ecx, edi\nmov r8d, 0\nmov r9d, 1\nloc_124A:\nmovsxd rdx, r8d\nlea rdx, [rax+rdx*8]\nmov [rdx], r9d\nmov [rdx+4], cl\nadd r8d, 1\nmov [rbp+0], r8d\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11C9(__int64 a1, _DWORD *a2)\n{\n size_t v4; // rax\n char *result; // rax\n char v6; // di\n char v7; // cl\n __int64 v8; // rdx\n int v9; // r8d\n int v10; // r9d\n char *v11; // rsi\n char *v12; // rdx\n\n v4 = strlen((const char *)a1);\n result = (char *)malloc(8 * v4);\n v6 = *(_BYTE *)a1;\n v7 = *(_BYTE *)(a1 + 1);\n if ( v7 )\n {\n v8 = a1 + 2;\n v9 = 0;\n v10 = 1;\n while ( 1 )\n {\n if ( v7 == v6 )\n {\n ++v10;\n }\n else\n {\n v11 = &result[8 * v9];\n *(_DWORD *)v11 = v10;\n v11[4] = v6;\n ++v9;\n v10 = 1;\n }\n ++v8;\n v6 = v7;\n if ( !*(_BYTE *)(v8 - 1) )\n break;\n v7 = *(_BYTE *)(v8 - 1);\n }\n }\n else\n {\n v7 = v6;\n v9 = 0;\n v10 = 1;\n }\n v12 = &result[8 * v9];\n *(_DWORD *)v12 = v10;\n v12[4] = v7;\n *a2 = v9 + 1;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11C9(long long a1, uint32_t *a2) {\n unsigned int v4;\n char *result;\n char v6;\n char v7;\n long long v8;\n int v9;\n int v10;\n char *v11;\n char *v12;\n v4 = strlen((const char *)a1);\n result = (char *)malloc(8 * v4);\n v6 = *(uint8_t *)a1;\n v7 = *(uint8_t *)(a1 + 1);\n if (v7) {\n v8 = a1 + 2;\n v9 = 0;\n v10 = 1;\n while (1) {\n if (v7 == v6) {\n ++v10;\n } else {\n v11 = &result[8 * v9];\n *(uint32_t *)v11 = v10;\n v11[4] = v6;\n ++v9;\n v10 = 1;\n }\n ++v8;\n v6 = v7;\n if (!*(uint8_t *)(v8 - 1)) break;\n v7 = *(uint8_t *)(v8 - 1);\n }\n } else {\n v7 = v6;\n v9 = 0;\n v10 = 1;\n }\n v12 = &result[8 * v9];\n *(uint32_t *)v12 = v10;\n v12[4] = v7;\n *a2 = v9 + 1;\n return result;\n}", + "ida_pseudo_norm": "char *func0(long long a1, uint32_t *a2) {\n unsigned int v4;\n char *result;\n char v6;\n char v7;\n long long v8;\n int v9;\n int v10;\n char *v11;\n char *v12;\n v4 = strlen((const char *)a1);\n result = (char *)malloc(8 * v4);\n v6 = *(uint8_t *)a1;\n v7 = *(uint8_t *)(a1 + 1);\n if (v7) {\n v8 = a1 + 2;\n v9 = 0;\n v10 = 1;\n while (1) {\n if (v7 == v6) {\n ++v10;\n } else {\n v11 = &result[8 * v9];\n *(uint32_t *)v11 = v10;\n v11[4] = v6;\n ++v9;\n v10 = 1;\n }\n ++v8;\n v6 = v7;\n if (!*(uint8_t *)(v8 - 1)) break;\n v7 = *(uint8_t *)(v8 - 1);\n }\n } else {\n v7 = v6;\n v9 = 0;\n v10 = 1;\n }\n v12 = &result[8 * v9];\n *(uint32_t *)v12 = v10;\n v12[4] = v7;\n *a2 = v9 + 1;\n return result;\n}" + }, + { + "index": 157, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\nstruct Pair {\n\n int count;\n\n char value;\n\n};\n\n\n\n", + "func": "struct Pair *func0(char *list1, int *returnSize) {\n struct Pair *result =\n (struct Pair *)malloc(sizeof(struct Pair) * strlen(list1));\n char current = list1[0];\n int count = 1;\n int res_idx = 0;\n for (int i = 1; list1[i] != '\\0'; i++) {\n if (list1[i] == current) {\n count++;\n } else {\n result[res_idx].count = count;\n result[res_idx].value = current;\n res_idx++;\n current = list1[i];\n count = 1;\n }\n }\n result[res_idx].count = count;\n result[res_idx].value = current;\n res_idx++;\n *returnSize = res_idx;\n return result;\n}", + "test": "int main() {\n\n int size1, size2, size3;\n\n \n\n struct Pair *encoded1 = func0(\"11234\", &size1);\n\n assert(size1 == 4 && encoded1[0].count == 2 && encoded1[0].value == '1' &&\n\n encoded1[1].count == 1 && encoded1[1].value == '2' &&\n\n encoded1[2].count == 1 && encoded1[2].value == '3' &&\n\n encoded1[3].count == 1 && encoded1[3].value == '4');\n\n\n\n struct Pair *encoded2 = func0(\"automatically\", &size2);\n\n assert(size2 == 12 && encoded2[10].count == 2 && encoded2[10].value == 'l');\n\n \n\n struct Pair *encoded3 = func0(\"python\", &size3);\n\n assert(size3 == 6 && encoded3[0].count == 1 && encoded3[0].value == 'p');\n\n \n\n free(encoded1);\n\n free(encoded2);\n\n free(encoded3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsi,%rbp\npush %rbx\nmov %rdi,%rbx\nsub $0x8,%rsp\ncallq 10a0 \nlea 0x0(,%rax,8),%rdi\ncallq 10d0 \nmovzbl 0x1(%rbx),%ecx\nmovzbl (%rbx),%r10d\ntest %cl,%cl\nje 13f0 \nlea 0x2(%rbx),%rdi\nxor %r8d,%r8d\nmov $0x1,%r11d\njmp 13b8 \nnopl (%rax)\nadd $0x1,%rdi\nmov %r10b,0x4(%r9)\nmov %ecx,%r10d\nmovzbl -0x1(%rdi),%ecx\nmov %r11d,(%r9)\nlea 0x8(%rax,%rdx,1),%r9\nmov $0x1,%r11d\nlea 0x2(%r8),%edx\nmov %ebx,%r8d\ntest %cl,%cl\nje 13dd \nmovslq %r8d,%rdx\nlea 0x1(%r8),%ebx\nshl $0x3,%rdx\nlea (%rax,%rdx,1),%r9\ncmp %cl,%r10b\njne 1390 \nmovzbl (%rdi),%ecx\nadd $0x1,%rdi\nadd $0x1,%r11d\nmov %ebx,%edx\ntest %cl,%cl\njne 13b8 \nmov %r11d,(%r9)\nmov %r10b,0x4(%r9)\nmov %edx,0x0(%rbp)\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nxchg %ax,%ax\nmov %rax,%r9\nmov $0x1,%edx\nmov $0x1,%r11d\njmp 13dd \n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsi\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\nlea rdi, ds:0[rax*8]; size\ncall _malloc\nmovzx edx, byte ptr [rbx+1]\nmovzx esi, byte ptr [rbx]\ntest dl, dl\njz short loc_13F0\nlea rdi, [rbx+2]\nxor r8d, r8d\nmov r9d, 1\njmp short loc_13B8\nloc_1390:\nmovsxd rcx, r8d\nadd rdi, 1\nadd r8d, 1\nlea rcx, [rax+rcx*8]\nmov [rcx], r9d\nmov r9d, 1\nmov [rcx+4], sil\nmovzx ecx, byte ptr [rdi-1]\nmov esi, edx\ntest cl, cl\njz short loc_13CE\nloc_13B6:\nmov edx, ecx\nloc_13B8:\ncmp dl, sil\njnz short loc_1390\nmovzx ecx, byte ptr [rdi]\nadd rdi, 1\nadd r9d, 1\nmov esi, edx\ntest cl, cl\njnz short loc_13B6\nloc_13CE:\nmovsxd rcx, r8d\nadd r8d, 1\nlea rcx, [rax+rcx*8]\nloc_13D9:\nmov [rcx], r9d\nmov [rcx+4], dl\nmov [rbp+0], r8d\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_13F0:\nmov rcx, rax\nmov edx, esi\nmov r8d, 1\nmov r9d, 1\njmp short loc_13D9", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int *a2)\n{\n size_t v3; // rax\n char *result; // rax\n char v5; // dl\n char v6; // si\n char *v7; // rdi\n int v8; // r8d\n int v9; // r9d\n __int64 v10; // rcx\n char *v11; // rcx\n char v12; // cl\n __int64 v13; // rcx\n int v14; // r8d\n char *v15; // rcx\n\n v3 = strlen((const char *)a1);\n result = (char *)malloc(8 * v3);\n v5 = *(_BYTE *)(a1 + 1);\n v6 = *(_BYTE *)a1;\n if ( !v5 )\n {\n v15 = result;\n v5 = *(_BYTE *)a1;\n v14 = 1;\n v9 = 1;\n goto LABEL_8;\n }\n v7 = (char *)(a1 + 2);\n v8 = 0;\n v9 = 1;\n while ( v5 != v6 )\n {\n v10 = v8;\n ++v7;\n ++v8;\n v11 = &result[8 * v10];\n *(_DWORD *)v11 = v9;\n v9 = 1;\n v11[4] = v6;\n v12 = *(v7 - 1);\n v6 = v5;\n if ( !v12 )\n goto LABEL_7;\nLABEL_4:\n v5 = v12;\n }\n v12 = *v7++;\n ++v9;\n v6 = v5;\n if ( v12 )\n goto LABEL_4;\nLABEL_7:\n v13 = v8;\n v14 = v8 + 1;\n v15 = &result[8 * v13];\nLABEL_8:\n *(_DWORD *)v15 = v9;\n v15[4] = v5;\n *a2 = v14;\n return result;\n}", + "ida_strip_asm": "sub_1350:\nendbr64\npush rbp\nmov rbp, rsi\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\nlea rdi, ds:0[rax*8]; size\ncall _malloc\nmovzx edx, byte ptr [rbx+1]\nmovzx esi, byte ptr [rbx]\ntest dl, dl\njz short loc_13F0\nlea rdi, [rbx+2]\nxor r8d, r8d\nmov r9d, 1\njmp short loc_13B8\nloc_1390:\nmovsxd rcx, r8d\nadd rdi, 1\nadd r8d, 1\nlea rcx, [rax+rcx*8]\nmov [rcx], r9d\nmov r9d, 1\nmov [rcx+4], sil\nmovzx ecx, byte ptr [rdi-1]\nmov esi, edx\ntest cl, cl\njz short loc_13CE\nloc_13B6:\nmov edx, ecx\nloc_13B8:\ncmp dl, sil\njnz short loc_1390\nmovzx ecx, byte ptr [rdi]\nadd rdi, 1\nadd r9d, 1\nmov esi, edx\ntest cl, cl\njnz short loc_13B6\nloc_13CE:\nmovsxd rcx, r8d\nadd r8d, 1\nlea rcx, [rax+rcx*8]\nloc_13D9:\nmov [rcx], r9d\nmov [rcx+4], dl\nmov [rbp+0], r8d\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_13F0:\nmov rcx, rax\nmov edx, esi\nmov r8d, 1\nmov r9d, 1\njmp short loc_13D9", + "ida_strip_pseudo": "char *__fastcall sub_1350(__int64 a1, int *a2)\n{\n size_t v3; // rax\n char *result; // rax\n char v5; // dl\n char v6; // si\n char *v7; // rdi\n int v8; // r8d\n int v9; // r9d\n __int64 v10; // rcx\n char *v11; // rcx\n char v12; // cl\n __int64 v13; // rcx\n int v14; // r8d\n char *v15; // rcx\n\n v3 = strlen((const char *)a1);\n result = (char *)malloc(8 * v3);\n v5 = *(_BYTE *)(a1 + 1);\n v6 = *(_BYTE *)a1;\n if ( !v5 )\n {\n v15 = result;\n v5 = *(_BYTE *)a1;\n v14 = 1;\n v9 = 1;\n goto LABEL_8;\n }\n v7 = (char *)(a1 + 2);\n v8 = 0;\n v9 = 1;\n while ( v5 != v6 )\n {\n v10 = v8;\n ++v7;\n ++v8;\n v11 = &result[8 * v10];\n *(_DWORD *)v11 = v9;\n v9 = 1;\n v11[4] = v6;\n v12 = *(v7 - 1);\n v6 = v5;\n if ( !v12 )\n goto LABEL_7;\nLABEL_4:\n v5 = v12;\n }\n v12 = *v7++;\n ++v9;\n v6 = v5;\n if ( v12 )\n goto LABEL_4;\nLABEL_7:\n v13 = v8;\n v14 = v8 + 1;\n v15 = &result[8 * v13];\nLABEL_8:\n *(_DWORD *)v15 = v9;\n v15[4] = v5;\n *a2 = v14;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1350(long long a1, int *a2) {\n unsigned int v3;\n char *result;\n char v5;\n char v6;\n char *v7;\n int v8;\n int v9;\n long long v10;\n char *v11;\n char v12;\n long long v13;\n int v14;\n char *v15;\n v3 = strlen((const char *)a1);\n result = (char *)malloc(8 * v3);\n v5 = *(uint8_t *)(a1 + 1);\n v6 = *(uint8_t *)a1;\n if (!v5) {\n v15 = result;\n v5 = *(uint8_t *)a1;\n v14 = 1;\n v9 = 1;\n goto LABEL_8;\n }\n v7 = (char *)(a1 + 2);\n v8 = 0;\n v9 = 1;\n while (v5 != v6) {\n v10 = v8;\n ++v7;\n ++v8;\n v11 = &result[8 * v10];\n *(uint32_t *)v11 = v9;\n v9 = 1;\n v11[4] = v6;\n v12 = *(v7 - 1);\n v6 = v5;\n if (!v12) goto LABEL_7;\n LABEL_4:\n v5 = v12;\n }\n v12 = *v7++;\n ++v9;\n v6 = v5;\n if (v12) goto LABEL_4;\nLABEL_7:\n v13 = v8;\n v14 = v8 + 1;\n v15 = &result[8 * v13];\nLABEL_8:\n *(uint32_t *)v15 = v9;\n v15[4] = v5;\n *a2 = v14;\n return result;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int *a2) {\n unsigned int v3;\n char *result;\n char v5;\n char v6;\n char *v7;\n int v8;\n int v9;\n long long v10;\n char *v11;\n char v12;\n long long v13;\n int v14;\n char *v15;\n v3 = strlen((const char *)a1);\n result = (char *)malloc(8 * v3);\n v5 = *(uint8_t *)(a1 + 1);\n v6 = *(uint8_t *)a1;\n if (!v5) {\n v15 = result;\n v5 = *(uint8_t *)a1;\n v14 = 1;\n v9 = 1;\n goto LABEL_8;\n }\n v7 = (char *)(a1 + 2);\n v8 = 0;\n v9 = 1;\n while (v5 != v6) {\n v10 = v8;\n ++v7;\n ++v8;\n v11 = &result[8 * v10];\n *(uint32_t *)v11 = v9;\n v9 = 1;\n v11[4] = v6;\n v12 = *(v7 - 1);\n v6 = v5;\n if (!v12) goto LABEL_7;\n LABEL_4:\n v5 = v12;\n }\n v12 = *v7++;\n ++v9;\n v6 = v5;\n if (v12) goto LABEL_4;\nLABEL_7:\n v13 = v8;\n v14 = v8 + 1;\n v15 = &result[8 * v13];\nLABEL_8:\n *(uint32_t *)v15 = v9;\n v15[4] = v5;\n *a2 = v14;\n return result;\n}" + }, + { + "index": 157, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\nstruct Pair {\n\n int count;\n\n char value;\n\n};\n\n\n\n", + "func": "struct Pair *func0(char *list1, int *returnSize) {\n struct Pair *result =\n (struct Pair *)malloc(sizeof(struct Pair) * strlen(list1));\n char current = list1[0];\n int count = 1;\n int res_idx = 0;\n for (int i = 1; list1[i] != '\\0'; i++) {\n if (list1[i] == current) {\n count++;\n } else {\n result[res_idx].count = count;\n result[res_idx].value = current;\n res_idx++;\n current = list1[i];\n count = 1;\n }\n }\n result[res_idx].count = count;\n result[res_idx].value = current;\n res_idx++;\n *returnSize = res_idx;\n return result;\n}", + "test": "int main() {\n\n int size1, size2, size3;\n\n \n\n struct Pair *encoded1 = func0(\"11234\", &size1);\n\n assert(size1 == 4 && encoded1[0].count == 2 && encoded1[0].value == '1' &&\n\n encoded1[1].count == 1 && encoded1[1].value == '2' &&\n\n encoded1[2].count == 1 && encoded1[2].value == '3' &&\n\n encoded1[3].count == 1 && encoded1[3].value == '4');\n\n\n\n struct Pair *encoded2 = func0(\"automatically\", &size2);\n\n assert(size2 == 12 && encoded2[10].count == 2 && encoded2[10].value == 'l');\n\n \n\n struct Pair *encoded3 = func0(\"python\", &size3);\n\n assert(size3 == 6 && encoded3[0].count == 1 && encoded3[0].value == 'p');\n\n \n\n free(encoded1);\n\n free(encoded2);\n\n free(encoded3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsi,%rbp\npush %rbx\nmov %rdi,%rbx\nsub $0x8,%rsp\ncallq 10a0 \nlea 0x0(,%rax,8),%rdi\ncallq 10d0 \nmovzbl 0x1(%rbx),%r8d\nmovzbl (%rbx),%r10d\ntest %r8b,%r8b\nje 1420 \nlea 0x2(%rbx),%rdi\nmov $0x1,%r11d\nxor %ebx,%ebx\nxor %esi,%esi\nmov $0x1,%r9d\njmp 13d1 \nnopw 0x0(%rax,%rax,1)\nadd $0x1,%rdi\nmov %r11d,(%rdx)\nadd $0x2,%ebx\nmov %r10b,0x4(%rdx)\nlea 0x8(%rax,%rcx,1),%rdx\nmovzbl -0x1(%rdi),%ecx\ntest %cl,%cl\nje 1400 \nmov %r9d,%ebx\nmovslq %r9d,%rsi\nmov %r8d,%r10d\nmov $0x1,%r11d\nadd $0x1,%r9d\nmov %ecx,%r8d\nlea 0x0(,%rsi,8),%rcx\nlea (%rax,%rcx,1),%rdx\ncmp %r8b,%r10b\njne 13a0 \nmovzbl (%rdi),%ecx\nadd $0x1,%rdi\nadd $0x1,%r11d\ntest %cl,%cl\njne 13ce \nmov %r9d,%ebx\njmp 1406 \nnopw %cs:0x0(%rax,%rax,1)\nmov $0x1,%r11d\nmov %r11d,(%rdx)\nmov %r8b,0x4(%rdx)\nmov %ebx,0x0(%rbp)\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopw 0x0(%rax,%rax,1)\nmov %rax,%rdx\nmov %r10d,%r8d\nmov $0x1,%ebx\nmov $0x1,%r11d\njmp 1406 \nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsi\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\nlea rdi, ds:0[rax*8]; size\ncall _malloc\nmovzx edx, byte ptr [rbx+1]\nmovzx esi, byte ptr [rbx]\ntest dl, dl\njz short loc_13F0\nlea rdi, [rbx+2]\nxor r8d, r8d\nmov r9d, 1\njmp short loc_13B8\nloc_1390:\nmovsxd rcx, r8d\nadd rdi, 1\nadd r8d, 1\nlea rcx, [rax+rcx*8]\nmov [rcx], r9d\nmov r9d, 1\nmov [rcx+4], sil\nmovzx ecx, byte ptr [rdi-1]\ntest cl, cl\njz short loc_13CC\nloc_13B4:\nmov esi, edx\nmov edx, ecx\nloc_13B8:\ncmp dl, sil\njnz short loc_1390\nmovzx ecx, byte ptr [rdi]\nadd rdi, 1\nadd r9d, 1\ntest cl, cl\njnz short loc_13B4\nloc_13CC:\nmovsxd rcx, r8d\nadd r8d, 1\nlea rcx, [rax+rcx*8]\nloc_13D7:\nmov [rcx], r9d\nmov [rcx+4], dl\nmov [rbp+0], r8d\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_13F0:\nmov rcx, rax\nmov edx, esi\nmov r8d, 1\nmov r9d, 1\njmp short loc_13D7", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int *a2)\n{\n size_t v3; // rax\n char *result; // rax\n char v5; // dl\n char v6; // si\n char *v7; // rdi\n int v8; // r8d\n int v9; // r9d\n __int64 v10; // rcx\n char *v11; // rcx\n char v12; // cl\n __int64 v13; // rcx\n int v14; // r8d\n char *v15; // rcx\n\n v3 = strlen((const char *)a1);\n result = (char *)malloc(8 * v3);\n v5 = *(_BYTE *)(a1 + 1);\n v6 = *(_BYTE *)a1;\n if ( !v5 )\n {\n v15 = result;\n v5 = *(_BYTE *)a1;\n v14 = 1;\n v9 = 1;\n goto LABEL_8;\n }\n v7 = (char *)(a1 + 2);\n v8 = 0;\n v9 = 1;\n while ( v5 != v6 )\n {\n v10 = v8;\n ++v7;\n ++v8;\n v11 = &result[8 * v10];\n *(_DWORD *)v11 = v9;\n v9 = 1;\n v11[4] = v6;\n v12 = *(v7 - 1);\n if ( !v12 )\n goto LABEL_7;\nLABEL_4:\n v6 = v5;\n v5 = v12;\n }\n v12 = *v7++;\n ++v9;\n if ( v12 )\n goto LABEL_4;\nLABEL_7:\n v13 = v8;\n v14 = v8 + 1;\n v15 = &result[8 * v13];\nLABEL_8:\n *(_DWORD *)v15 = v9;\n v15[4] = v5;\n *a2 = v14;\n return result;\n}", + "ida_strip_asm": "sub_1350:\nendbr64\npush rbp\nmov rbp, rsi\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\nlea rdi, ds:0[rax*8]; size\ncall _malloc\nmovzx edx, byte ptr [rbx+1]\nmovzx esi, byte ptr [rbx]\ntest dl, dl\njz short loc_13F0\nlea rdi, [rbx+2]\nxor r8d, r8d\nmov r9d, 1\njmp short loc_13B8\nloc_1390:\nmovsxd rcx, r8d\nadd rdi, 1\nadd r8d, 1\nlea rcx, [rax+rcx*8]\nmov [rcx], r9d\nmov r9d, 1\nmov [rcx+4], sil\nmovzx ecx, byte ptr [rdi-1]\ntest cl, cl\njz short loc_13CC\nloc_13B4:\nmov esi, edx\nmov edx, ecx\nloc_13B8:\ncmp dl, sil\njnz short loc_1390\nmovzx ecx, byte ptr [rdi]\nadd rdi, 1\nadd r9d, 1\ntest cl, cl\njnz short loc_13B4\nloc_13CC:\nmovsxd rcx, r8d\nadd r8d, 1\nlea rcx, [rax+rcx*8]\nloc_13D7:\nmov [rcx], r9d\nmov [rcx+4], dl\nmov [rbp+0], r8d\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_13F0:\nmov rcx, rax\nmov edx, esi\nmov r8d, 1\nmov r9d, 1\njmp short loc_13D7", + "ida_strip_pseudo": "char *__fastcall sub_1350(__int64 a1, int *a2)\n{\n size_t v3; // rax\n char *result; // rax\n char v5; // dl\n char v6; // si\n char *v7; // rdi\n int v8; // r8d\n int v9; // r9d\n __int64 v10; // rcx\n char *v11; // rcx\n char v12; // cl\n __int64 v13; // rcx\n int v14; // r8d\n char *v15; // rcx\n\n v3 = strlen((const char *)a1);\n result = (char *)malloc(8 * v3);\n v5 = *(_BYTE *)(a1 + 1);\n v6 = *(_BYTE *)a1;\n if ( !v5 )\n {\n v15 = result;\n v5 = *(_BYTE *)a1;\n v14 = 1;\n v9 = 1;\n goto LABEL_8;\n }\n v7 = (char *)(a1 + 2);\n v8 = 0;\n v9 = 1;\n while ( v5 != v6 )\n {\n v10 = v8;\n ++v7;\n ++v8;\n v11 = &result[8 * v10];\n *(_DWORD *)v11 = v9;\n v9 = 1;\n v11[4] = v6;\n v12 = *(v7 - 1);\n if ( !v12 )\n goto LABEL_7;\nLABEL_4:\n v6 = v5;\n v5 = v12;\n }\n v12 = *v7++;\n ++v9;\n if ( v12 )\n goto LABEL_4;\nLABEL_7:\n v13 = v8;\n v14 = v8 + 1;\n v15 = &result[8 * v13];\nLABEL_8:\n *(_DWORD *)v15 = v9;\n v15[4] = v5;\n *a2 = v14;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1350(long long a1, int *a2) {\n unsigned int v3;\n char *result;\n char v5;\n char v6;\n char *v7;\n int v8;\n int v9;\n long long v10;\n char *v11;\n char v12;\n long long v13;\n int v14;\n char *v15;\n v3 = strlen((const char *)a1);\n result = (char *)malloc(8 * v3);\n v5 = *(uint8_t *)(a1 + 1);\n v6 = *(uint8_t *)a1;\n if (!v5) {\n v15 = result;\n v5 = *(uint8_t *)a1;\n v14 = 1;\n v9 = 1;\n goto LABEL_8;\n }\n v7 = (char *)(a1 + 2);\n v8 = 0;\n v9 = 1;\n while (v5 != v6) {\n v10 = v8;\n ++v7;\n ++v8;\n v11 = &result[8 * v10];\n *(uint32_t *)v11 = v9;\n v9 = 1;\n v11[4] = v6;\n v12 = *(v7 - 1);\n if (!v12) goto LABEL_7;\n LABEL_4:\n v6 = v5;\n v5 = v12;\n }\n v12 = *v7++;\n ++v9;\n if (v12) goto LABEL_4;\nLABEL_7:\n v13 = v8;\n v14 = v8 + 1;\n v15 = &result[8 * v13];\nLABEL_8:\n *(uint32_t *)v15 = v9;\n v15[4] = v5;\n *a2 = v14;\n return result;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int *a2) {\n unsigned int v3;\n char *result;\n char v5;\n char v6;\n char *v7;\n int v8;\n int v9;\n long long v10;\n char *v11;\n char v12;\n long long v13;\n int v14;\n char *v15;\n v3 = strlen((const char *)a1);\n result = (char *)malloc(8 * v3);\n v5 = *(uint8_t *)(a1 + 1);\n v6 = *(uint8_t *)a1;\n if (!v5) {\n v15 = result;\n v5 = *(uint8_t *)a1;\n v14 = 1;\n v9 = 1;\n goto LABEL_8;\n }\n v7 = (char *)(a1 + 2);\n v8 = 0;\n v9 = 1;\n while (v5 != v6) {\n v10 = v8;\n ++v7;\n ++v8;\n v11 = &result[8 * v10];\n *(uint32_t *)v11 = v9;\n v9 = 1;\n v11[4] = v6;\n v12 = *(v7 - 1);\n if (!v12) goto LABEL_7;\n LABEL_4:\n v6 = v5;\n v5 = v12;\n }\n v12 = *v7++;\n ++v9;\n if (v12) goto LABEL_4;\nLABEL_7:\n v13 = v8;\n v14 = v8 + 1;\n v15 = &result[8 * v13];\nLABEL_8:\n *(uint32_t *)v15 = v9;\n v15[4] = v5;\n *a2 = v14;\n return result;\n}" + }, + { + "index": 158, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n, int k) {\n int max1 = arr[0];\n int res = 0;\n for (int i = 1; i < n; i++) {\n if (arr[i] > max1) {\n max1 = arr[i];\n }\n }\n for (int i = 0; i < n; i++) {\n if ((max1 - arr[i]) % k != 0) {\n return -1;\n } else {\n res += (max1 - arr[i]) / k;\n }\n }\n return res;\n}", + "test": "int main() {\n\n int arr1[] = {2, 2, 2, 2};\n\n int arr2[] = {4, 2, 6, 8};\n\n int arr3[] = {21, 33, 9, 45, 63};\n\n\n\n assert(func0(arr1, 4, 3) == 0);\n\n assert(func0(arr2, 4, 3) == -1);\n\n assert(func0(arr3, 5, 6) == 24);\n\n\n\n printf(\"All test cases passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmov -0x18(%rbp),%rax\nmov (%rax),%eax\nmov %eax,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x1,-0x8(%rbp)\njmp 11ec \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x10(%rbp)\njge 11e8 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x10(%rbp)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11b4 \nmovl $0x0,-0x4(%rbp)\njmp 1253 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov -0x10(%rbp),%edx\nsub %eax,%edx\nmov %edx,%eax\ncltd\nidivl -0x20(%rbp)\nmov %edx,%eax\ntest %eax,%eax\nje 122b \nmov $0xffffffff,%eax\njmp 125e \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov -0x10(%rbp),%edx\nsub %eax,%edx\nmov %edx,%eax\ncltd\nidivl -0x20(%rbp)\nadd %eax,-0xc(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11fd \nmov -0xc(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov rax, [rbp+var_18]\nmov eax, [rax]\nmov [rbp+var_10], eax\nmov [rbp+var_C], 0\nmov [rbp+var_8], 1\njmp short loc_11EC\nloc_11B4:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_10], eax\njge short loc_11E8\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_10], eax\nloc_11E8:\nadd [rbp+var_8], 1\nloc_11EC:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_11B4\nmov [rbp+var_4], 0\njmp short loc_1253\nloc_11FD:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_10]\nsub edx, eax\nmov eax, edx\ncdq\nidiv [rbp+var_20]\nmov eax, edx\ntest eax, eax\njz short loc_122B\nmov eax, 0FFFFFFFFh\njmp short loc_125E\nloc_122B:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_10]\nsub edx, eax\nmov eax, edx\ncdq\nidiv [rbp+var_20]\nadd [rbp+var_C], eax\nadd [rbp+var_4], 1\nloc_1253:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11FD\nmov eax, [rbp+var_C]\nloc_125E:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2, int a3)\n{\n int v4; // [rsp+10h] [rbp-10h]\n unsigned int v5; // [rsp+14h] [rbp-Ch]\n int i; // [rsp+18h] [rbp-8h]\n int j; // [rsp+1Ch] [rbp-4h]\n\n v4 = *a1;\n v5 = 0;\n for ( i = 1; i < a2; ++i )\n {\n if ( v4 < a1[i] )\n v4 = a1[i];\n }\n for ( j = 0; j < a2; ++j )\n {\n if ( (v4 - a1[j]) % a3 )\n return 0xFFFFFFFFLL;\n v5 += (v4 - a1[j]) / a3;\n }\n return v5;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov rax, [rbp+var_18]\nmov eax, [rax]\nmov [rbp+var_10], eax\nmov [rbp+var_C], 0\nmov [rbp+var_8], 1\njmp short loc_11EC\nloc_11B4:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_10], eax\njge short loc_11E8\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_10], eax\nloc_11E8:\nadd [rbp+var_8], 1\nloc_11EC:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_11B4\nmov [rbp+var_4], 0\njmp short loc_1253\nloc_11FD:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_10]\nsub edx, eax\nmov eax, edx\ncdq\nidiv [rbp+var_20]\nmov eax, edx\ntest eax, eax\njz short loc_122B\nmov eax, 0FFFFFFFFh\njmp short loc_125E\nloc_122B:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_10]\nsub edx, eax\nmov eax, edx\ncdq\nidiv [rbp+var_20]\nadd [rbp+var_C], eax\nadd [rbp+var_4], 1\nloc_1253:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11FD\nmov eax, [rbp+var_C]\nloc_125E:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(int *a1, int a2, int a3)\n{\n int v4; // [rsp+10h] [rbp-10h]\n unsigned int v5; // [rsp+14h] [rbp-Ch]\n int i; // [rsp+18h] [rbp-8h]\n int j; // [rsp+1Ch] [rbp-4h]\n\n v4 = *a1;\n v5 = 0;\n for ( i = 1; i < a2; ++i )\n {\n if ( v4 < a1[i] )\n v4 = a1[i];\n }\n for ( j = 0; j < a2; ++j )\n {\n if ( (v4 - a1[j]) % a3 )\n return 0xFFFFFFFFLL;\n v5 += (v4 - a1[j]) / a3;\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(int *a1, int a2, int a3) {\n int v4;\n unsigned int v5;\n int i;\n int j;\n v4 = *a1;\n v5 = 0;\n for (i = 1; i < a2; ++i) {\n if (v4 < a1[i]) v4 = a1[i];\n }\n for (j = 0; j < a2; ++j) {\n if ((v4 - a1[j]) % a3) return 4294967295LL;\n v5 += (v4 - a1[j]) / a3;\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2, int a3) {\n int v4;\n unsigned int v5;\n int i;\n int j;\n v4 = *a1;\n v5 = 0;\n for (i = 1; i < a2; ++i) {\n if (v4 < a1[i]) v4 = a1[i];\n }\n for (j = 0; j < a2; ++j) {\n if ((v4 - a1[j]) % a3) return 4294967295LL;\n v5 += (v4 - a1[j]) / a3;\n }\n return v5;\n}" + }, + { + "index": 158, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n, int k) {\n int max1 = arr[0];\n int res = 0;\n for (int i = 1; i < n; i++) {\n if (arr[i] > max1) {\n max1 = arr[i];\n }\n }\n for (int i = 0; i < n; i++) {\n if ((max1 - arr[i]) % k != 0) {\n return -1;\n } else {\n res += (max1 - arr[i]) / k;\n }\n }\n return res;\n}", + "test": "int main() {\n\n int arr1[] = {2, 2, 2, 2};\n\n int arr2[] = {4, 2, 6, 8};\n\n int arr3[] = {21, 33, 9, 45, 63};\n\n\n\n assert(func0(arr1, 4, 3) == 0);\n\n assert(func0(arr2, 4, 3) == -1);\n\n assert(func0(arr3, 5, 6) == 24);\n\n\n\n printf(\"All test cases passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %edx,%r8d\nmov (%rdi),%r10d\ncmp $0x1,%esi\njle 11e7 \nlea 0x4(%rdi),%rax\nlea -0x2(%rsi),%edx\nlea 0x8(%rdi,%rdx,4),%rcx\nmov (%rax),%edx\ncmp %edx,%r10d\ncmovl %edx,%r10d\nadd $0x4,%rax\ncmp %rcx,%rax\njne 11a4 \nmov $0x0,%r9d\nmov $0x0,%r11d\nmov %r10d,%ecx\nsub (%rdi,%r9,4),%ecx\nmov %ecx,%eax\ncltd\nidiv %r8d\ntest %edx,%edx\njne 11f1 \nmov %ecx,%eax\ncltd\nidiv %r8d\nadd %eax,%r11d\nadd $0x1,%r9\ncmp %r9d,%esi\njg 11c2 \njmp 11f7 \nmov $0x0,%r11d\nje 11b6 \njmp 11f7 \nmov $0xffffffff,%r11d\nmov %r11d,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov r8d, edx\nmov r10d, [rdi]\ncmp esi, 1\njle short loc_11EA\nlea rax, [rdi+4]\nlea edx, [rsi-2]\nlea rcx, [rdi+rdx*4+8]\nloc_11A4:\nmov edx, [rax]\ncmp r10d, edx\ncmovl r10d, edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_11A4\nloc_11B6:\nmov r9, rdi\nmovsxd rsi, esi\nlea rsi, [rdi+rsi*4]\nmov r11d, 0\nloc_11C6:\nmov ecx, r10d\nsub ecx, [r9]\nmov eax, ecx\ncdq\nidiv r8d\ntest edx, edx\njnz short loc_11F6\nmov eax, ecx\ncdq\nidiv r8d\nadd r11d, eax\nadd r9, 4\ncmp r9, rsi\njnz short loc_11C6\njmp short loc_11FC\nloc_11EA:\nmov r11d, 0\ntest esi, esi\njle short loc_11FC\njmp short loc_11B6\nloc_11F6:\nmov r11d, 0FFFFFFFFh\nloc_11FC:\nmov eax, r11d\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2, int a3)\n{\n int v3; // r10d\n int *v4; // rax\n _DWORD *v5; // r9\n _DWORD *v6; // rsi\n unsigned int v7; // r11d\n\n v3 = *a1;\n if ( a2 <= 1 )\n {\n v7 = 0;\n if ( a2 <= 0 )\n return v7;\n }\n else\n {\n v4 = a1 + 1;\n do\n {\n if ( v3 < *v4 )\n v3 = *v4;\n ++v4;\n }\n while ( v4 != &a1[a2 - 2 + 2] );\n }\n v5 = a1;\n v6 = &a1[a2];\n v7 = 0;\n while ( !((v3 - *v5) % a3) )\n {\n v7 += (v3 - *v5++) / a3;\n if ( v5 == v6 )\n return v7;\n }\n return (unsigned int)-1;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\nmov r8d, edx\nmov r10d, [rdi]\ncmp esi, 1\njle short loc_11EA\nlea rax, [rdi+4]\nlea edx, [rsi-2]\nlea rcx, [rdi+rdx*4+8]\nloc_11A4:\nmov edx, [rax]\ncmp r10d, edx\ncmovl r10d, edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_11A4\nloc_11B6:\nmov r9, rdi\nmovsxd rsi, esi\nlea rsi, [rdi+rsi*4]\nmov r11d, 0\nloc_11C6:\nmov ecx, r10d\nsub ecx, [r9]\nmov eax, ecx\ncdq\nidiv r8d\ntest edx, edx\njnz short loc_11F6\nmov eax, ecx\ncdq\nidiv r8d\nadd r11d, eax\nadd r9, 4\ncmp r9, rsi\njnz short loc_11C6\njmp short loc_11FC\nloc_11EA:\nmov r11d, 0\ntest esi, esi\njle short loc_11FC\njmp short loc_11B6\nloc_11F6:\nmov r11d, 0FFFFFFFFh\nloc_11FC:\nmov eax, r11d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(_DWORD *a1, int a2, int a3)\n{\n int v3; // r10d\n int *v4; // rax\n _DWORD *v5; // r9\n _DWORD *v6; // rsi\n unsigned int v7; // r11d\n\n v3 = *a1;\n if ( a2 <= 1 )\n {\n v7 = 0;\n if ( a2 <= 0 )\n return v7;\n }\n else\n {\n v4 = a1 + 1;\n do\n {\n if ( v3 < *v4 )\n v3 = *v4;\n ++v4;\n }\n while ( v4 != &a1[a2 - 2 + 2] );\n }\n v5 = a1;\n v6 = &a1[a2];\n v7 = 0;\n while ( !((v3 - *v5) % a3) )\n {\n v7 += (v3 - *v5++) / a3;\n if ( v5 == v6 )\n return v7;\n }\n return (unsigned int)-1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(uint32_t *a1, int a2, int a3) {\n int v3;\n int *v4;\n uint32_t *v5;\n uint32_t *v6;\n unsigned int v7;\n v3 = *a1;\n if (a2 <= 1) {\n v7 = 0;\n if (a2 <= 0) return v7;\n } else {\n v4 = a1 + 1;\n do {\n if (v3 < *v4) v3 = *v4;\n ++v4;\n } while (v4 != &a1[a2 - 2 + 2]);\n }\n v5 = a1;\n v6 = &a1[a2];\n v7 = 0;\n while (!((v3 - *v5) % a3)) {\n v7 += (v3 - *v5++) / a3;\n if (v5 == v6) return v7;\n }\n return (unsigned int)-1;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2, int a3) {\n int v3;\n int *v4;\n uint32_t *v5;\n uint32_t *v6;\n unsigned int v7;\n v3 = *a1;\n if (a2 <= 1) {\n v7 = 0;\n if (a2 <= 0) return v7;\n } else {\n v4 = a1 + 1;\n do {\n if (v3 < *v4) v3 = *v4;\n ++v4;\n } while (v4 != &a1[a2 - 2 + 2]);\n }\n v5 = a1;\n v6 = &a1[a2];\n v7 = 0;\n while (!((v3 - *v5) % a3)) {\n v7 += (v3 - *v5++) / a3;\n if (v5 == v6) return v7;\n }\n return (unsigned int)-1;\n}" + }, + { + "index": 158, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n, int k) {\n int max1 = arr[0];\n int res = 0;\n for (int i = 1; i < n; i++) {\n if (arr[i] > max1) {\n max1 = arr[i];\n }\n }\n for (int i = 0; i < n; i++) {\n if ((max1 - arr[i]) % k != 0) {\n return -1;\n } else {\n res += (max1 - arr[i]) / k;\n }\n }\n return res;\n}", + "test": "int main() {\n\n int arr1[] = {2, 2, 2, 2};\n\n int arr2[] = {4, 2, 6, 8};\n\n int arr3[] = {21, 33, 9, 45, 63};\n\n\n\n assert(func0(arr1, 4, 3) == 0);\n\n assert(func0(arr2, 4, 3) == -1);\n\n assert(func0(arr3, 5, 6) == 24);\n\n\n\n printf(\"All test cases passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov (%rdi),%r11d\nmov %edx,%r9d\ncmp $0x1,%esi\njle 1340 \nlea -0x2(%rsi),%edx\nlea 0x4(%rdi),%rax\nmov %r11d,%ecx\nlea 0x8(%rdi,%rdx,4),%r8\nxchg %ax,%ax\nmov (%rax),%edx\ncmp %edx,%ecx\ncmovl %edx,%ecx\nadd $0x4,%rax\ncmp %rax,%r8\njne 12f0 \nxor %r8d,%r8d\nxor %r10d,%r10d\njmp 1320 \nnopl 0x0(%rax,%rax,1)\nadd $0x1,%r8\nadd %eax,%r10d\ncmp %r8d,%esi\njle 1333 \nmov (%rdi,%r8,4),%r11d\nmov %ecx,%eax\nsub %r11d,%eax\ncltd\nidiv %r9d\ntest %edx,%edx\nje 1310 \nmov $0xffffffff,%r10d\nmov %r10d,%eax\nretq\nnopw 0x0(%rax,%rax,1)\nmov $0x0,%r10d\njne 1333 \nmov %r11d,%ecx\njmp 1300 \nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\nmov rcx, rdi\nmov r8d, edx\nmov edi, [rdi]\ncmp esi, 1\njle short loc_1340\nlea edx, [rsi-2]\nlea rax, [rcx+4]\nlea r9, [rcx+rdx*4+8]\nmov rdx, r9\nsub rdx, rax\nand edx, 4\njz short loc_12F0\nmov eax, [rax]\ncmp edi, eax\ncmovl edi, eax\nlea rax, [rcx+8]\ncmp rax, r9\njz short loc_1308\nnop dword ptr [rax+rax+00000000h]\nloc_12F0:\nmov edx, [rax]\ncmp edi, edx\ncmovl edi, edx\nmov edx, [rax+4]\ncmp edi, edx\ncmovl edi, edx\nadd rax, 8\ncmp rax, r9\njnz short loc_12F0\nloc_1308:\nmovsxd rsi, esi\nxor r9d, r9d\nlea rsi, [rcx+rsi*4]\njmp short loc_1324\nloc_1318:\nadd rcx, 4\nadd r9d, eax\ncmp rsi, rcx\njz short loc_1336\nloc_1324:\nmov eax, edi\nsub eax, [rcx]\ncdq\nidiv r8d\ntest edx, edx\njz short loc_1318\nmov r9d, 0FFFFFFFFh\nloc_1336:\nmov eax, r9d\nretn\nloc_1340:\nmov r9d, 0\njnz short loc_1336\njmp short loc_1308", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2, int a3)\n{\n _DWORD *v3; // rcx\n int v4; // edi\n int *v5; // rax\n __int64 v6; // r9\n int v7; // eax\n unsigned int v8; // r9d\n _DWORD *v9; // rsi\n int v10; // eax\n\n v3 = a1;\n v4 = *a1;\n if ( a2 <= 1 )\n {\n v8 = 0;\n if ( a2 != 1 )\n return v8;\n }\n else\n {\n v5 = v3 + 1;\n v6 = (__int64)&v3[a2 - 2 + 2];\n if ( ((4 * ((_BYTE)a2 - 2) + 4) & 4) == 0 )\n goto LABEL_20;\n v7 = *v5;\n if ( v4 < v7 )\n v4 = v7;\n v5 = v3 + 2;\n if ( v3 + 2 != (_DWORD *)v6 )\n {\nLABEL_20:\n do\n {\n if ( v4 < *v5 )\n v4 = *v5;\n if ( v4 < v5[1] )\n v4 = v5[1];\n v5 += 2;\n }\n while ( v5 != (int *)v6 );\n }\n }\n v8 = 0;\n v9 = &v3[a2];\n while ( 1 )\n {\n v10 = (v4 - *v3) / a3;\n if ( (v4 - *v3) % a3 )\n break;\n ++v3;\n v8 += v10;\n if ( v9 == v3 )\n return v8;\n }\n return (unsigned int)-1;\n}", + "ida_strip_asm": "sub_12B0:\nendbr64\nmov rcx, rdi\nmov r8d, edx\nmov edi, [rdi]\ncmp esi, 1\njle short loc_1340\nlea edx, [rsi-2]\nlea rax, [rcx+4]\nlea r9, [rcx+rdx*4+8]\nmov rdx, r9\nsub rdx, rax\nand edx, 4\njz short loc_12F0\nmov eax, [rax]\ncmp edi, eax\ncmovl edi, eax\nlea rax, [rcx+8]\ncmp rax, r9\njz short loc_1308\nnop dword ptr [rax+rax+00000000h]\nloc_12F0:\nmov edx, [rax]\ncmp edi, edx\ncmovl edi, edx\nmov edx, [rax+4]\ncmp edi, edx\ncmovl edi, edx\nadd rax, 8\ncmp rax, r9\njnz short loc_12F0\nloc_1308:\nmovsxd rsi, esi\nxor r9d, r9d\nlea rsi, [rcx+rsi*4]\njmp short loc_1324\nloc_1318:\nadd rcx, 4\nadd r9d, eax\ncmp rsi, rcx\njz short loc_1336\nloc_1324:\nmov eax, edi\nsub eax, [rcx]\ncdq\nidiv r8d\ntest edx, edx\njz short loc_1318\nmov r9d, 0FFFFFFFFh\nloc_1336:\nmov eax, r9d\nretn\nloc_1340:\nmov r9d, 0\njnz short loc_1336\njmp short loc_1308", + "ida_strip_pseudo": "__int64 __fastcall sub_12B0(_DWORD *a1, int a2, int a3)\n{\n _DWORD *v3; // rcx\n int v4; // edi\n int *v5; // rax\n __int64 v6; // r9\n int v7; // eax\n unsigned int v8; // r9d\n _DWORD *v9; // rsi\n int v10; // eax\n\n v3 = a1;\n v4 = *a1;\n if ( a2 <= 1 )\n {\n v8 = 0;\n if ( a2 != 1 )\n return v8;\n }\n else\n {\n v5 = v3 + 1;\n v6 = (__int64)&v3[a2 - 2 + 2];\n if ( ((4 * ((_BYTE)a2 - 2) + 4) & 4) == 0 )\n goto LABEL_20;\n v7 = *v5;\n if ( v4 < v7 )\n v4 = v7;\n v5 = v3 + 2;\n if ( v3 + 2 != (_DWORD *)v6 )\n {\nLABEL_20:\n do\n {\n if ( v4 < *v5 )\n v4 = *v5;\n if ( v4 < v5[1] )\n v4 = v5[1];\n v5 += 2;\n }\n while ( v5 != (int *)v6 );\n }\n }\n v8 = 0;\n v9 = &v3[a2];\n while ( 1 )\n {\n v10 = (v4 - *v3) / a3;\n if ( (v4 - *v3) % a3 )\n break;\n ++v3;\n v8 += v10;\n if ( v9 == v3 )\n return v8;\n }\n return (unsigned int)-1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12B0(uint32_t *a1, int a2, int a3) {\n uint32_t *v3;\n int v4;\n int *v5;\n long long v6;\n int v7;\n unsigned int v8;\n uint32_t *v9;\n int v10;\n v3 = a1;\n v4 = *a1;\n if (a2 <= 1) {\n v8 = 0;\n if (a2 != 1) return v8;\n } else {\n v5 = v3 + 1;\n v6 = (long long)&v3[a2 - 2 + 2];\n if (((4 * ((uint8_t)a2 - 2) + 4) & 4) == 0) goto LABEL_20;\n v7 = *v5;\n if (v4 < v7) v4 = v7;\n v5 = v3 + 2;\n if (v3 + 2 != (uint32_t *)v6) {\n LABEL_20:\n do {\n if (v4 < *v5) v4 = *v5;\n if (v4 < v5[1]) v4 = v5[1];\n v5 += 2;\n } while (v5 != (int *)v6);\n }\n }\n v8 = 0;\n v9 = &v3[a2];\n while (1) {\n v10 = (v4 - *v3) / a3;\n if ((v4 - *v3) % a3) break;\n ++v3;\n v8 += v10;\n if (v9 == v3) return v8;\n }\n return (unsigned int)-1;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2, int a3) {\n uint32_t *v3;\n int v4;\n int *v5;\n long long v6;\n int v7;\n unsigned int v8;\n uint32_t *v9;\n int v10;\n v3 = a1;\n v4 = *a1;\n if (a2 <= 1) {\n v8 = 0;\n if (a2 != 1) return v8;\n } else {\n v5 = v3 + 1;\n v6 = (long long)&v3[a2 - 2 + 2];\n if (((4 * ((uint8_t)a2 - 2) + 4) & 4) == 0) goto LABEL_20;\n v7 = *v5;\n if (v4 < v7) v4 = v7;\n v5 = v3 + 2;\n if (v3 + 2 != (uint32_t *)v6) {\n LABEL_20:\n do {\n if (v4 < *v5) v4 = *v5;\n if (v4 < v5[1]) v4 = v5[1];\n v5 += 2;\n } while (v5 != (int *)v6);\n }\n }\n v8 = 0;\n v9 = &v3[a2];\n while (1) {\n v10 = (v4 - *v3) / a3;\n if ((v4 - *v3) % a3) break;\n ++v3;\n v8 += v10;\n if (v9 == v3) return v8;\n }\n return (unsigned int)-1;\n}" + }, + { + "index": 158, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n, int k) {\n int max1 = arr[0];\n int res = 0;\n for (int i = 1; i < n; i++) {\n if (arr[i] > max1) {\n max1 = arr[i];\n }\n }\n for (int i = 0; i < n; i++) {\n if ((max1 - arr[i]) % k != 0) {\n return -1;\n } else {\n res += (max1 - arr[i]) / k;\n }\n }\n return res;\n}", + "test": "int main() {\n\n int arr1[] = {2, 2, 2, 2};\n\n int arr2[] = {4, 2, 6, 8};\n\n int arr3[] = {21, 33, 9, 45, 63};\n\n\n\n assert(func0(arr1, 4, 3) == 0);\n\n assert(func0(arr2, 4, 3) == -1);\n\n assert(func0(arr3, 5, 6) == 24);\n\n\n\n printf(\"All test cases passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nmov (%rdi),%r9d\nmov %edx,%r10d\ncmp $0x1,%esi\njle 13c8 \nlea -0x2(%rsi),%eax\nlea -0x1(%rsi),%ecx\ncmp $0x2,%eax\njbe 13d2 \nmov %ecx,%edx\nmovd %r9d,%xmm3\nmov %rdi,%rax\nshr $0x2,%edx\npshufd $0x0,%xmm3,%xmm2\nshl $0x4,%rdx\nadd %rdi,%rdx\nnopl 0x0(%rax,%rax,1)\nmovdqu 0x4(%rax),%xmm0\nadd $0x10,%rax\nmovdqa %xmm0,%xmm1\npcmpgtd %xmm2,%xmm1\npand %xmm1,%xmm0\npandn %xmm2,%xmm1\nmovdqa %xmm1,%xmm2\npor %xmm0,%xmm2\ncmp %rdx,%rax\njne 12f0 \nmovdqa %xmm2,%xmm0\nmov %ecx,%edx\npsrldq $0x8,%xmm0\nand $0xfffffffc,%edx\nmovdqa %xmm0,%xmm1\nlea 0x1(%rdx),%eax\npcmpgtd %xmm2,%xmm1\npand %xmm1,%xmm0\npandn %xmm2,%xmm1\npor %xmm1,%xmm0\nmovdqa %xmm0,%xmm2\npsrldq $0x4,%xmm2\nmovdqa %xmm2,%xmm1\npcmpgtd %xmm0,%xmm1\npand %xmm1,%xmm2\npandn %xmm0,%xmm1\npor %xmm2,%xmm1\nmovd %xmm1,%r9d\ncmp %ecx,%edx\nje 1395 \nmovslq %eax,%rdx\nmov (%rdi,%rdx,4),%edx\ncmp %edx,%r9d\ncmovl %edx,%r9d\nlea 0x1(%rax),%edx\ncmp %edx,%esi\njle 1395 \nmovslq %edx,%rdx\nmov (%rdi,%rdx,4),%edx\ncmp %edx,%r9d\ncmovl %edx,%r9d\nadd $0x2,%eax\ncmp %eax,%esi\njle 1395 \ncltq\nmov (%rdi,%rax,4),%eax\ncmp %eax,%r9d\ncmovl %eax,%r9d\nxor %ecx,%ecx\nxor %r8d,%r8d\njmp 13ab \nnopl 0x0(%rax)\nadd $0x1,%rcx\nadd %eax,%r8d\ncmp %ecx,%esi\njle 13bf \nmov %r9d,%eax\nsub (%rdi,%rcx,4),%eax\ncltd\nidiv %r10d\ntest %edx,%edx\nje 13a0 \nmov $0xffffffff,%r8d\nmov %r8d,%eax\nretq\nnopl 0x0(%rax,%rax,1)\nmov $0x0,%r8d\nje 1395 \njmp 13bf \nmov $0x1,%eax\njmp 1361 \nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\nmovsxd r9, esi\nmov rcx, rdi\nmov r8d, edx\nmov edi, [rdi]\ncmp r9d, 1\njle loc_13D0\nlea eax, [r9-2]\nlea esi, [r9-1]\ncmp eax, 2\njbe loc_13D9\nmov edx, esi\nmovd xmm3, edi\nmov rax, rcx\nshr edx, 2\npshufd xmm2, xmm3, 0\nshl rdx, 4\nadd rdx, rcx\nnop word ptr [rax+rax+00h]\nloc_12F8:\nmovdqu xmm0, xmmword ptr [rax+4]\nadd rax, 10h\nmovdqa xmm1, xmm0\npcmpgtd xmm1, xmm2\npand xmm0, xmm1\npandn xmm1, xmm2\nmovdqa xmm2, xmm1\npor xmm2, xmm0\ncmp rax, rdx\njnz short loc_12F8\nmovdqa xmm1, xmm2\nmov eax, esi\npsrldq xmm1, 8\nand eax, 0FFFFFFFCh\nmovdqa xmm0, xmm1\nadd eax, 1\nand esi, 3\npcmpgtd xmm0, xmm2\npand xmm1, xmm0\npandn xmm0, xmm2\npor xmm0, xmm1\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\nmovdqa xmm1, xmm2\npcmpgtd xmm1, xmm0\npand xmm2, xmm1\npandn xmm1, xmm0\npor xmm1, xmm2\nmovd edi, xmm1\njz short loc_139E\nloc_1369:\nmovsxd rdx, eax\nlea rsi, ds:0[rdx*4]\nmov edx, [rcx+rdx*4]\ncmp edi, edx\ncmovl edi, edx\nlea edx, [rax+1]\ncmp r9d, edx\njle short loc_139E\nmov edx, [rcx+rsi+4]\ncmp edi, edx\ncmovl edi, edx\nadd eax, 2\ncmp r9d, eax\njle short loc_139E\nmov eax, [rcx+rsi+8]\ncmp edi, eax\ncmovl edi, eax\nloc_139E:\nlea r9, [rcx+r9*4]\nxor esi, esi\njmp short loc_13BB\nloc_13B0:\nadd rcx, 4\nadd esi, eax\ncmp rcx, r9\njz short loc_13CC\nloc_13BB:\nmov eax, edi\nsub eax, [rcx]\ncdq\nidiv r8d\ntest edx, edx\njz short loc_13B0\nmov esi, 0FFFFFFFFh\nloc_13CC:\nmov eax, esi\nretn\nloc_13D0:\nmov esi, 0\njnz short loc_13CC\njmp short loc_139E\nloc_13D9:\nmov eax, 1\njmp short loc_1369", + "ida_pseudo": "__int64 __fastcall func0(signed int *a1, int a2, int a3)\n{\n __int64 v3; // r9\n signed int *v4; // rcx\n signed int v5; // edi\n bool v6; // zf\n unsigned int v7; // esi\n signed int *v8; // rax\n __m128i v9; // xmm2\n __m128i v10; // xmm0\n __m128i v11; // xmm1\n __m128i v12; // xmm1\n signed int v13; // eax\n __m128i v14; // xmm0\n __m128i v15; // xmm0\n __m128i v16; // xmm2\n __m128i v17; // xmm1\n __int64 v18; // rsi\n signed int *v19; // r9\n unsigned int v20; // esi\n int v21; // eax\n\n v3 = a2;\n v4 = a1;\n v5 = *a1;\n v6 = a2 == 1;\n if ( a2 <= 1 )\n {\n v20 = 0;\n if ( !v6 )\n return v20;\n goto LABEL_14;\n }\n v7 = a2 - 1;\n if ( (unsigned int)(v3 - 2) <= 2 )\n {\n v13 = 1;\n }\n else\n {\n v8 = v4;\n v9 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v5), 0);\n do\n {\n v10 = _mm_loadu_si128((const __m128i *)(v8 + 1));\n v8 += 4;\n v11 = _mm_cmpgt_epi32(v10, v9);\n v9 = _mm_or_si128(_mm_andnot_si128(v11, v9), _mm_and_si128(v10, v11));\n }\n while ( v8 != &v4[4 * (v7 >> 2)] );\n v12 = _mm_srli_si128(v9, 8);\n v13 = (v7 & 0xFFFFFFFC) + 1;\n v14 = _mm_cmpgt_epi32(v12, v9);\n v15 = _mm_or_si128(_mm_andnot_si128(v14, v9), _mm_and_si128(v12, v14));\n v16 = _mm_srli_si128(v15, 4);\n v17 = _mm_cmpgt_epi32(v16, v15);\n v5 = _mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v17, v15), _mm_and_si128(v16, v17)));\n if ( (v7 & 3) == 0 )\n goto LABEL_14;\n }\n v18 = v13;\n if ( v5 < v4[v18] )\n v5 = v4[v13];\n if ( (int)v3 > v13 + 1 )\n {\n if ( v5 < v4[v18 + 1] )\n v5 = v4[v18 + 1];\n if ( (int)v3 > v13 + 2 && v5 < v4[v18 + 2] )\n v5 = v4[v18 + 2];\n }\nLABEL_14:\n v19 = &v4[v3];\n v20 = 0;\n while ( 1 )\n {\n v21 = (v5 - *v4) / a3;\n if ( (v5 - *v4) % a3 )\n break;\n ++v4;\n v20 += v21;\n if ( v4 == v19 )\n return v20;\n }\n return (unsigned int)-1;\n}", + "ida_strip_asm": "sub_12B0:\nendbr64\nmovsxd r9, esi\nmov rcx, rdi\nmov r8d, edx\nmov edi, [rdi]\ncmp r9d, 1\njle loc_13D0\nlea eax, [r9-2]\nlea esi, [r9-1]\ncmp eax, 2\njbe loc_13D9\nmov edx, esi\nmovd xmm3, edi\nmov rax, rcx\nshr edx, 2\npshufd xmm2, xmm3, 0\nshl rdx, 4\nadd rdx, rcx\nnop word ptr [rax+rax+00h]\nloc_12F8:\nmovdqu xmm0, xmmword ptr [rax+4]\nadd rax, 10h\nmovdqa xmm1, xmm0\npcmpgtd xmm1, xmm2\npand xmm0, xmm1\npandn xmm1, xmm2\nmovdqa xmm2, xmm1\npor xmm2, xmm0\ncmp rax, rdx\njnz short loc_12F8\nmovdqa xmm1, xmm2\nmov eax, esi\npsrldq xmm1, 8\nand eax, 0FFFFFFFCh\nmovdqa xmm0, xmm1\nadd eax, 1\nand esi, 3\npcmpgtd xmm0, xmm2\npand xmm1, xmm0\npandn xmm0, xmm2\npor xmm0, xmm1\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\nmovdqa xmm1, xmm2\npcmpgtd xmm1, xmm0\npand xmm2, xmm1\npandn xmm1, xmm0\npor xmm1, xmm2\nmovd edi, xmm1\njz short loc_139E\nloc_1369:\nmovsxd rdx, eax\nlea rsi, ds:0[rdx*4]\nmov edx, [rcx+rdx*4]\ncmp edi, edx\ncmovl edi, edx\nlea edx, [rax+1]\ncmp r9d, edx\njle short loc_139E\nmov edx, [rcx+rsi+4]\ncmp edi, edx\ncmovl edi, edx\nadd eax, 2\ncmp r9d, eax\njle short loc_139E\nmov eax, [rcx+rsi+8]\ncmp edi, eax\ncmovl edi, eax\nloc_139E:\nlea r9, [rcx+r9*4]\nxor esi, esi\njmp short loc_13BB\nloc_13B0:\nadd rcx, 4\nadd esi, eax\ncmp rcx, r9\njz short loc_13CC\nloc_13BB:\nmov eax, edi\nsub eax, [rcx]\ncdq\nidiv r8d\ntest edx, edx\njz short loc_13B0\nmov esi, 0FFFFFFFFh\nloc_13CC:\nmov eax, esi\nretn\nloc_13D0:\nmov esi, 0\njnz short loc_13CC\njmp short loc_139E\nloc_13D9:\nmov eax, 1\njmp short loc_1369", + "ida_strip_pseudo": "__int64 __fastcall sub_12B0(signed int *a1, int a2, int a3)\n{\n __int64 v3; // r9\n signed int *v4; // rcx\n signed int v5; // edi\n bool v6; // zf\n unsigned int v7; // esi\n signed int *v8; // rax\n __m128i v9; // xmm2\n __m128i v10; // xmm0\n __m128i v11; // xmm1\n __m128i v12; // xmm1\n signed int v13; // eax\n __m128i v14; // xmm0\n __m128i v15; // xmm0\n __m128i v16; // xmm2\n __m128i v17; // xmm1\n __int64 v18; // rsi\n signed int *v19; // r9\n unsigned int v20; // esi\n int v21; // eax\n\n v3 = a2;\n v4 = a1;\n v5 = *a1;\n v6 = a2 == 1;\n if ( a2 <= 1 )\n {\n v20 = 0;\n if ( !v6 )\n return v20;\n goto LABEL_14;\n }\n v7 = a2 - 1;\n if ( (unsigned int)(v3 - 2) <= 2 )\n {\n v13 = 1;\n }\n else\n {\n v8 = v4;\n v9 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v5), 0);\n do\n {\n v10 = _mm_loadu_si128((const __m128i *)(v8 + 1));\n v8 += 4;\n v11 = _mm_cmpgt_epi32(v10, v9);\n v9 = _mm_or_si128(_mm_andnot_si128(v11, v9), _mm_and_si128(v10, v11));\n }\n while ( v8 != &v4[4 * (v7 >> 2)] );\n v12 = _mm_srli_si128(v9, 8);\n v13 = (v7 & 0xFFFFFFFC) + 1;\n v14 = _mm_cmpgt_epi32(v12, v9);\n v15 = _mm_or_si128(_mm_andnot_si128(v14, v9), _mm_and_si128(v12, v14));\n v16 = _mm_srli_si128(v15, 4);\n v17 = _mm_cmpgt_epi32(v16, v15);\n v5 = _mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v17, v15), _mm_and_si128(v16, v17)));\n if ( (v7 & 3) == 0 )\n goto LABEL_14;\n }\n v18 = v13;\n if ( v5 < v4[v18] )\n v5 = v4[v13];\n if ( (int)v3 > v13 + 1 )\n {\n if ( v5 < v4[v18 + 1] )\n v5 = v4[v18 + 1];\n if ( (int)v3 > v13 + 2 && v5 < v4[v18 + 2] )\n v5 = v4[v18 + 2];\n }\nLABEL_14:\n v19 = &v4[v3];\n v20 = 0;\n while ( 1 )\n {\n v21 = (v5 - *v4) / a3;\n if ( (v5 - *v4) % a3 )\n break;\n ++v4;\n v20 += v21;\n if ( v4 == v19 )\n return v20;\n }\n return (unsigned int)-1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12B0(signed int *a1, int a2, int a3) {\n long long v3;\n signed int *v4;\n signed int v5;\n bool v6;\n unsigned int v7;\n signed int *v8;\n __m128i v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n signed int v13;\n __m128i v14;\n __m128i v15;\n __m128i v16;\n __m128i v17;\n long long v18;\n signed int *v19;\n unsigned int v20;\n int v21;\n v3 = a2;\n v4 = a1;\n v5 = *a1;\n v6 = a2 == 1;\n if (a2 <= 1) {\n v20 = 0;\n if (!v6) return v20;\n goto LABEL_14;\n }\n v7 = a2 - 1;\n if ((unsigned int)(v3 - 2) <= 2) {\n v13 = 1;\n } else {\n v8 = v4;\n v9 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v5), 0);\n do {\n v10 = _mm_loadu_si128((const __m128i *)(v8 + 1));\n v8 += 4;\n v11 = _mm_cmpgt_epi32(v10, v9);\n v9 = _mm_or_si128(_mm_andnot_si128(v11, v9), _mm_and_si128(v10, v11));\n } while (v8 != &v4[4 * (v7 >> 2)]);\n v12 = _mm_srli_si128(v9, 8);\n v13 = (v7 & 4294967292) + 1;\n v14 = _mm_cmpgt_epi32(v12, v9);\n v15 = _mm_or_si128(_mm_andnot_si128(v14, v9), _mm_and_si128(v12, v14));\n v16 = _mm_srli_si128(v15, 4);\n v17 = _mm_cmpgt_epi32(v16, v15);\n v5 = _mm_cvtsi128_si32(\n _mm_or_si128(_mm_andnot_si128(v17, v15), _mm_and_si128(v16, v17)));\n if ((v7 & 3) == 0) goto LABEL_14;\n }\n v18 = v13;\n if (v5 < v4[v18]) v5 = v4[v13];\n if ((int)v3 > v13 + 1) {\n if (v5 < v4[v18 + 1]) v5 = v4[v18 + 1];\n if ((int)v3 > v13 + 2 && v5 < v4[v18 + 2]) v5 = v4[v18 + 2];\n }\nLABEL_14:\n v19 = &v4[v3];\n v20 = 0;\n while (1) {\n v21 = (v5 - *v4) / a3;\n if ((v5 - *v4) % a3) break;\n ++v4;\n v20 += v21;\n if (v4 == v19) return v20;\n }\n return (unsigned int)-1;\n}", + "ida_pseudo_norm": "long long func0(signed int *a1, int a2, int a3) {\n long long v3;\n signed int *v4;\n signed int v5;\n bool v6;\n unsigned int v7;\n signed int *v8;\n __m128i v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n signed int v13;\n __m128i v14;\n __m128i v15;\n __m128i v16;\n __m128i v17;\n long long v18;\n signed int *v19;\n unsigned int v20;\n int v21;\n v3 = a2;\n v4 = a1;\n v5 = *a1;\n v6 = a2 == 1;\n if (a2 <= 1) {\n v20 = 0;\n if (!v6) return v20;\n goto LABEL_14;\n }\n v7 = a2 - 1;\n if ((unsigned int)(v3 - 2) <= 2) {\n v13 = 1;\n } else {\n v8 = v4;\n v9 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v5), 0);\n do {\n v10 = _mm_loadu_si128((const __m128i *)(v8 + 1));\n v8 += 4;\n v11 = _mm_cmpgt_epi32(v10, v9);\n v9 = _mm_or_si128(_mm_andnot_si128(v11, v9), _mm_and_si128(v10, v11));\n } while (v8 != &v4[4 * (v7 >> 2)]);\n v12 = _mm_srli_si128(v9, 8);\n v13 = (v7 & 4294967292) + 1;\n v14 = _mm_cmpgt_epi32(v12, v9);\n v15 = _mm_or_si128(_mm_andnot_si128(v14, v9), _mm_and_si128(v12, v14));\n v16 = _mm_srli_si128(v15, 4);\n v17 = _mm_cmpgt_epi32(v16, v15);\n v5 = _mm_cvtsi128_si32(\n _mm_or_si128(_mm_andnot_si128(v17, v15), _mm_and_si128(v16, v17)));\n if ((v7 & 3) == 0) goto LABEL_14;\n }\n v18 = v13;\n if (v5 < v4[v18]) v5 = v4[v13];\n if ((int)v3 > v13 + 1) {\n if (v5 < v4[v18 + 1]) v5 = v4[v18 + 1];\n if ((int)v3 > v13 + 2 && v5 < v4[v18 + 2]) v5 = v4[v18 + 2];\n }\nLABEL_14:\n v19 = &v4[v3];\n v20 = 0;\n while (1) {\n v21 = (v5 - *v4) / a3;\n if ((v5 - *v4) % a3) break;\n ++v4;\n v20 += v21;\n if (v4 == v19) return v20;\n }\n return (unsigned int)-1;\n}" + }, + { + "index": 159, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "const char* func0(const char* month, int days) {\n const char* season;\n if (strcmp(month, \"January\") == 0 || strcmp(month, \"February\") == 0 ||\n strcmp(month, \"March\") == 0) {\n season = \"winter\";\n } else if (strcmp(month, \"April\") == 0 || strcmp(month, \"May\") == 0 ||\n strcmp(month, \"June\") == 0) {\n season = \"spring\";\n } else if (strcmp(month, \"July\") == 0 || strcmp(month, \"August\") == 0 ||\n strcmp(month, \"September\") == 0) {\n season = \"summer\";\n } else {\n season = \"autumn\";\n }\n if ((strcmp(month, \"March\") == 0 && days > 19) ||\n (strcmp(month, \"June\") == 0 && days > 20) ||\n (strcmp(month, \"September\") == 0 && days > 21)) {\n if (strcmp(month, \"March\") == 0) {\n season = \"spring\";\n }\n if (strcmp(month, \"June\") == 0) {\n season = \"summer\";\n }\n if (strcmp(month, \"September\") == 0) {\n season = \"autumn\";\n }\n } else if ((strcmp(month, \"December\") == 0 && days > 20)) {\n season = \"winter\";\n }\n return season;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"January\", 4), \"winter\") == 0);\n\n assert(strcmp(func0(\"October\", 28), \"autumn\") == 0);\n\n assert(strcmp(func0(\"June\", 6), \"spring\") == 0);\n\n \n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov -0x18(%rbp),%rax\nlea 0xe61(%rip),%rsi\nmov %rax,%rdi\ncallq 1090 \ntest %eax,%eax\nje 11e1 \nmov -0x18(%rbp),%rax\nlea 0xe52(%rip),%rsi\nmov %rax,%rdi\ncallq 1090 \ntest %eax,%eax\nje 11e1 \nmov -0x18(%rbp),%rax\nlea 0xe44(%rip),%rsi\nmov %rax,%rdi\ncallq 1090 \ntest %eax,%eax\njne 11f1 \nlea 0xe37(%rip),%rax\nmov %rax,-0x8(%rbp)\njmpq 12a0 \nmov -0x18(%rbp),%rax\nlea 0xe2a(%rip),%rsi\nmov %rax,%rdi\ncallq 1090 \ntest %eax,%eax\nje 1236 \nmov -0x18(%rbp),%rax\nlea 0xe19(%rip),%rsi\nmov %rax,%rdi\ncallq 1090 \ntest %eax,%eax\nje 1236 \nmov -0x18(%rbp),%rax\nlea 0xe06(%rip),%rsi\nmov %rax,%rdi\ncallq 1090 \ntest %eax,%eax\njne 1243 \nlea 0xdf8(%rip),%rax\nmov %rax,-0x8(%rbp)\njmp 12a0 \nmov -0x18(%rbp),%rax\nlea 0xdee(%rip),%rsi\nmov %rax,%rdi\ncallq 1090 \ntest %eax,%eax\nje 1288 \nmov -0x18(%rbp),%rax\nlea 0xddc(%rip),%rsi\nmov %rax,%rdi\ncallq 1090 \ntest %eax,%eax\nje 1288 \nmov -0x18(%rbp),%rax\nlea 0xdcc(%rip),%rsi\nmov %rax,%rdi\ncallq 1090 \ntest %eax,%eax\njne 1295 \nlea 0xdc3(%rip),%rax\nmov %rax,-0x8(%rbp)\njmp 12a0 \nlea 0xdbd(%rip),%rax\nmov %rax,-0x8(%rbp)\nmov -0x18(%rbp),%rax\nlea 0xd6e(%rip),%rsi\nmov %rax,%rdi\ncallq 1090 \ntest %eax,%eax\njne 12bd \ncmpl $0x13,-0x1c(%rbp)\njg 12f7 \nmov -0x18(%rbp),%rax\nlea 0xd68(%rip),%rsi\nmov %rax,%rdi\ncallq 1090 \ntest %eax,%eax\njne 12da \ncmpl $0x14,-0x1c(%rbp)\njg 12f7 \nmov -0x18(%rbp),%rax\nlea 0xd63(%rip),%rsi\nmov %rax,%rdi\ncallq 1090 \ntest %eax,%eax\njne 135f \ncmpl $0x15,-0x1c(%rbp)\njle 135f \nmov -0x18(%rbp),%rax\nlea 0xd17(%rip),%rsi\nmov %rax,%rdi\ncallq 1090 \ntest %eax,%eax\njne 1319 \nlea 0xd20(%rip),%rax\nmov %rax,-0x8(%rbp)\nmov -0x18(%rbp),%rax\nlea 0xd0c(%rip),%rsi\nmov %rax,%rdi\ncallq 1090 \ntest %eax,%eax\njne 133b \nlea 0xd1b(%rip),%rax\nmov %rax,-0x8(%rbp)\nmov -0x18(%rbp),%rax\nlea 0xd02(%rip),%rsi\nmov %rax,%rdi\ncallq 1090 \ntest %eax,%eax\njne 1387 \nlea 0xd00(%rip),%rax\nmov %rax,-0x8(%rbp)\njmp 1387 \nmov -0x18(%rbp),%rax\nlea 0xcf6(%rip),%rsi\nmov %rax,%rdi\ncallq 1090 \ntest %eax,%eax\njne 1387 \ncmpl $0x14,-0x1c(%rbp)\njle 1387 \nlea 0xc9c(%rip),%rax\nmov %rax,-0x8(%rbp)\nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s1], rdi\nmov [rbp+var_1C], esi\nmov rax, [rbp+s1]\nlea rdx, s2; \"January\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_11EA\nmov rax, [rbp+s1]\nlea rdx, aFebruary; \"February\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_11EA\nmov rax, [rbp+s1]\nlea rdx, aMarch; \"March\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_11FA\nloc_11EA:\nlea rax, aWinter; \"winter\"\nmov [rbp+var_8], rax\njmp loc_12BB\nloc_11FA:\nmov rax, [rbp+s1]\nlea rdx, aApril; \"April\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_1248\nmov rax, [rbp+s1]\nlea rdx, aMay; \"May\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_1248\nmov rax, [rbp+s1]\nlea rdx, aJune; \"June\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1255\nloc_1248:\nlea rax, aSpring; \"spring\"\nmov [rbp+var_8], rax\njmp short loc_12BB\nloc_1255:\nmov rax, [rbp+s1]\nlea rdx, aJuly; \"July\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_12A3\nmov rax, [rbp+s1]\nlea rdx, aAugust; \"August\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_12A3\nmov rax, [rbp+s1]\nlea rdx, aSeptember; \"September\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_12B0\nloc_12A3:\nlea rax, aSummer; \"summer\"\nmov [rbp+var_8], rax\njmp short loc_12BB\nloc_12B0:\nlea rax, aAutumn; \"autumn\"\nmov [rbp+var_8], rax\nloc_12BB:\nmov rax, [rbp+s1]\nlea rdx, aMarch; \"March\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_12DB\ncmp [rbp+var_1C], 13h\njg short loc_131B\nloc_12DB:\nmov rax, [rbp+s1]\nlea rdx, aJune; \"June\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_12FB\ncmp [rbp+var_1C], 14h\njg short loc_131B\nloc_12FB:\nmov rax, [rbp+s1]\nlea rdx, aSeptember; \"September\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_138C\ncmp [rbp+var_1C], 15h\njle short loc_138C\nloc_131B:\nmov rax, [rbp+s1]\nlea rdx, aMarch; \"March\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1340\nlea rax, aSpring; \"spring\"\nmov [rbp+var_8], rax\nloc_1340:\nmov rax, [rbp+s1]\nlea rdx, aJune; \"June\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1365\nlea rax, aSummer; \"summer\"\nmov [rbp+var_8], rax\nloc_1365:\nmov rax, [rbp+s1]\nlea rdx, aSeptember; \"September\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_13B7\nlea rax, aAutumn; \"autumn\"\nmov [rbp+var_8], rax\njmp short loc_13B7\nloc_138C:\nmov rax, [rbp+s1]\nlea rdx, aDecember; \"December\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_13B7\ncmp [rbp+var_1C], 14h\njle short loc_13B7\nlea rax, aWinter; \"winter\"\nmov [rbp+var_8], rax\nloc_13B7:\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1, int a2)\n{\n const char *v3; // [rsp+18h] [rbp-8h]\n\n if ( !strcmp(a1, \"January\") || !strcmp(a1, \"February\") || !strcmp(a1, \"March\") )\n {\n v3 = \"winter\";\n }\n else if ( !strcmp(a1, \"April\") || !strcmp(a1, \"May\") || !strcmp(a1, \"June\") )\n {\n v3 = \"spring\";\n }\n else if ( !strcmp(a1, \"July\") || !strcmp(a1, \"August\") || !strcmp(a1, \"September\") )\n {\n v3 = \"summer\";\n }\n else\n {\n v3 = \"autumn\";\n }\n if ( !strcmp(a1, \"March\") && a2 > 19 || !strcmp(a1, \"June\") && a2 > 20 || !strcmp(a1, \"September\") && a2 > 21 )\n {\n if ( !strcmp(a1, \"March\") )\n v3 = \"spring\";\n if ( !strcmp(a1, \"June\") )\n v3 = \"summer\";\n if ( !strcmp(a1, \"September\") )\n return \"autumn\";\n }\n else if ( !strcmp(a1, \"December\") && a2 > 20 )\n {\n return \"winter\";\n }\n return v3;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s1], rdi\nmov [rbp+var_1C], esi\nmov rax, [rbp+s1]\nlea rdx, s2; \"January\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_11EA\nmov rax, [rbp+s1]\nlea rdx, aFebruary; \"February\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_11EA\nmov rax, [rbp+s1]\nlea rdx, aMarch; \"March\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_11FA\nloc_11EA:\nlea rax, aWinter; \"winter\"\nmov [rbp+var_8], rax\njmp loc_12BB\nloc_11FA:\nmov rax, [rbp+s1]\nlea rdx, aApril; \"April\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_1248\nmov rax, [rbp+s1]\nlea rdx, aMay; \"May\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_1248\nmov rax, [rbp+s1]\nlea rdx, aJune; \"June\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1255\nloc_1248:\nlea rax, aSpring; \"spring\"\nmov [rbp+var_8], rax\njmp short loc_12BB\nloc_1255:\nmov rax, [rbp+s1]\nlea rdx, aJuly; \"July\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_12A3\nmov rax, [rbp+s1]\nlea rdx, aAugust; \"August\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_12A3\nmov rax, [rbp+s1]\nlea rdx, aSeptember; \"September\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_12B0\nloc_12A3:\nlea rax, aSummer; \"summer\"\nmov [rbp+var_8], rax\njmp short loc_12BB\nloc_12B0:\nlea rax, aAutumn; \"autumn\"\nmov [rbp+var_8], rax\nloc_12BB:\nmov rax, [rbp+s1]\nlea rdx, aMarch; \"March\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_12DB\ncmp [rbp+var_1C], 13h\njg short loc_131B\nloc_12DB:\nmov rax, [rbp+s1]\nlea rdx, aJune; \"June\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_12FB\ncmp [rbp+var_1C], 14h\njg short loc_131B\nloc_12FB:\nmov rax, [rbp+s1]\nlea rdx, aSeptember; \"September\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_138C\ncmp [rbp+var_1C], 15h\njle short loc_138C\nloc_131B:\nmov rax, [rbp+s1]\nlea rdx, aMarch; \"March\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1340\nlea rax, aSpring; \"spring\"\nmov [rbp+var_8], rax\nloc_1340:\nmov rax, [rbp+s1]\nlea rdx, aJune; \"June\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1365\nlea rax, aSummer; \"summer\"\nmov [rbp+var_8], rax\nloc_1365:\nmov rax, [rbp+s1]\nlea rdx, aSeptember; \"September\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_13B7\nlea rax, aAutumn; \"autumn\"\nmov [rbp+var_8], rax\njmp short loc_13B7\nloc_138C:\nmov rax, [rbp+s1]\nlea rdx, aDecember; \"December\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_13B7\ncmp [rbp+var_1C], 14h\njle short loc_13B7\nlea rax, aWinter; \"winter\"\nmov [rbp+var_8], rax\nloc_13B7:\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1189(const char *a1, int a2)\n{\n const char *v3; // [rsp+18h] [rbp-8h]\n\n if ( !strcmp(a1, \"January\") || !strcmp(a1, \"February\") || !strcmp(a1, \"March\") )\n {\n v3 = \"winter\";\n }\n else if ( !strcmp(a1, \"April\") || !strcmp(a1, \"May\") || !strcmp(a1, \"June\") )\n {\n v3 = \"spring\";\n }\n else if ( !strcmp(a1, \"July\") || !strcmp(a1, \"August\") || !strcmp(a1, \"September\") )\n {\n v3 = \"summer\";\n }\n else\n {\n v3 = \"autumn\";\n }\n if ( !strcmp(a1, \"March\") && a2 > 19 || !strcmp(a1, \"June\") && a2 > 20 || !strcmp(a1, \"September\") && a2 > 21 )\n {\n if ( !strcmp(a1, \"March\") )\n v3 = \"spring\";\n if ( !strcmp(a1, \"June\") )\n v3 = \"summer\";\n if ( !strcmp(a1, \"September\") )\n return \"autumn\";\n }\n else if ( !strcmp(a1, \"December\") && a2 > 20 )\n {\n return \"winter\";\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1189(const char *a1, int a2) {\n const char *v3;\n if (!strcmp(a1, \"January\") || !strcmp(a1, \"February\") ||\n !strcmp(a1, \"March\")) {\n v3 = \"winter\";\n } else if (!strcmp(a1, \"April\") || !strcmp(a1, \"May\") ||\n !strcmp(a1, \"June\")) {\n v3 = \"spring\";\n } else if (!strcmp(a1, \"July\") || !strcmp(a1, \"August\") ||\n !strcmp(a1, \"September\")) {\n v3 = \"summer\";\n } else {\n v3 = \"autumn\";\n }\n if (!strcmp(a1, \"March\") && a2 > 19 || !strcmp(a1, \"June\") && a2 > 20 ||\n !strcmp(a1, \"September\") && a2 > 21) {\n if (!strcmp(a1, \"March\")) v3 = \"spring\";\n if (!strcmp(a1, \"June\")) v3 = \"summer\";\n if (!strcmp(a1, \"September\")) return \"autumn\";\n } else if (!strcmp(a1, \"December\") && a2 > 20) {\n return \"winter\";\n }\n return v3;\n}", + "ida_pseudo_norm": "const char *func0(const char *a1, int a2) {\n const char *v3;\n if (!strcmp(a1, \"January\") || !strcmp(a1, \"February\") ||\n !strcmp(a1, \"March\")) {\n v3 = \"winter\";\n } else if (!strcmp(a1, \"April\") || !strcmp(a1, \"May\") ||\n !strcmp(a1, \"June\")) {\n v3 = \"spring\";\n } else if (!strcmp(a1, \"July\") || !strcmp(a1, \"August\") ||\n !strcmp(a1, \"September\")) {\n v3 = \"summer\";\n } else {\n v3 = \"autumn\";\n }\n if (!strcmp(a1, \"March\") && a2 > 19 || !strcmp(a1, \"June\") && a2 > 20 ||\n !strcmp(a1, \"September\") && a2 > 21) {\n if (!strcmp(a1, \"March\")) v3 = \"spring\";\n if (!strcmp(a1, \"June\")) v3 = \"summer\";\n if (!strcmp(a1, \"September\")) return \"autumn\";\n } else if (!strcmp(a1, \"December\") && a2 > 20) {\n return \"winter\";\n }\n return v3;\n}" + }, + { + "index": 159, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "const char* func0(const char* month, int days) {\n const char* season;\n if (strcmp(month, \"January\") == 0 || strcmp(month, \"February\") == 0 ||\n strcmp(month, \"March\") == 0) {\n season = \"winter\";\n } else if (strcmp(month, \"April\") == 0 || strcmp(month, \"May\") == 0 ||\n strcmp(month, \"June\") == 0) {\n season = \"spring\";\n } else if (strcmp(month, \"July\") == 0 || strcmp(month, \"August\") == 0 ||\n strcmp(month, \"September\") == 0) {\n season = \"summer\";\n } else {\n season = \"autumn\";\n }\n if ((strcmp(month, \"March\") == 0 && days > 19) ||\n (strcmp(month, \"June\") == 0 && days > 20) ||\n (strcmp(month, \"September\") == 0 && days > 21)) {\n if (strcmp(month, \"March\") == 0) {\n season = \"spring\";\n }\n if (strcmp(month, \"June\") == 0) {\n season = \"summer\";\n }\n if (strcmp(month, \"September\") == 0) {\n season = \"autumn\";\n }\n } else if ((strcmp(month, \"December\") == 0 && days > 20)) {\n season = \"winter\";\n }\n return season;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"January\", 4), \"winter\") == 0);\n\n assert(strcmp(func0(\"October\", 28), \"autumn\") == 0);\n\n assert(strcmp(func0(\"June\", 6), \"spring\") == 0);\n\n \n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%rdx\nmov %esi,%eax\nmov $0x8,%ecx\nlea 0xea2(%rip),%rdi\nmov %rdx,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %cl\nsbb $0x0,%cl\ntest %cl,%cl\nje 1294 \nmov $0x9,%ecx\nlea 0xe8b(%rip),%rdi\nmov %rdx,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %cl\nsbb $0x0,%cl\ntest %cl,%cl\nje 1294 \nmov $0x6,%ecx\nlea 0xe75(%rip),%rdi\nmov %rdx,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %cl\nsbb $0x0,%cl\ntest %cl,%cl\nje 1294 \nmov $0x6,%ecx\nlea 0xe5c(%rip),%rdi\nmov %rdx,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %cl\nsbb $0x0,%cl\nlea 0xe1e(%rip),%r8\ntest %cl,%cl\nje 128c \nmov $0x4,%ecx\nlea 0xe3c(%rip),%rdi\nmov %rdx,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %cl\nsbb $0x0,%cl\ntest %cl,%cl\nje 128c \nmov $0x5,%ecx\nlea 0xe25(%rip),%rdi\nmov %rdx,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %cl\nsbb $0x0,%cl\ntest %cl,%cl\nje 128c \nmov $0x5,%ecx\nlea 0xe0f(%rip),%rdi\nmov %rdx,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %cl\nsbb $0x0,%cl\nlea 0xdc9(%rip),%r8\ntest %cl,%cl\nje 128c \nmov $0x7,%ecx\nlea 0xdf2(%rip),%rdi\nmov %rdx,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %cl\nsbb $0x0,%cl\ntest %cl,%cl\nje 128c \nmov $0xa,%ecx\nlea 0xdde(%rip),%rdi\nmov %rdx,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %cl\nsbb $0x0,%cl\ntest %cl,%cl\nlea 0xd91(%rip),%rcx\ncmovne %rcx,%r8\nmov $0x0,%r9d\njmp 12c6 \nmov $0x6,%ecx\nlea 0xd91(%rip),%rdi\nmov %rdx,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %cl\nsbb $0x0,%cl\ntest %cl,%cl\nsete %r9b\ncmp $0x13,%eax\njle 12bf \ntest %r9b,%r9b\njne 1373 \nlea 0xd3e(%rip),%r8\nmov $0x5,%ecx\nlea 0xd6f(%rip),%rdi\nmov %rdx,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %cl\nsbb $0x0,%cl\ncmp $0x14,%eax\nsetg %r10b\ntest %cl,%cl\njne 12f1 \ntest %r10b,%r10b\njne 13c4 \nmov $0xa,%ecx\nlea 0xd55(%rip),%rdi\nmov %rdx,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %cl\nsbb $0x0,%cl\nmovsbl %cl,%ecx\ncmp $0x15,%eax\njle 1314 \ntest %ecx,%ecx\nje 1342 \nmov $0x9,%ecx\nlea 0xd3c(%rip),%rdi\nmov %rdx,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %al\nsbb $0x0,%al\ntest %al,%al\njne 13c0 \ntest %r10b,%r10b\nlea 0xcc8(%rip),%rax\ncmovne %rax,%r8\njmp 13c0 \ntest %r9b,%r9b\nlea 0xcbf(%rip),%rax\ncmovne %rax,%r8\nmov $0x5,%ecx\nlea 0xce5(%rip),%rdi\nmov %rdx,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %al\nsbb $0x0,%al\ntest %al,%al\njne 139d \nlea 0xca8(%rip),%r8\njmp 13c0 \nmov $0x5,%ecx\nlea 0xcc2(%rip),%rdi\nmov %rdx,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %al\nsbb $0x0,%al\ntest %al,%al\nlea 0xc80(%rip),%r8\nlea 0xc72(%rip),%rax\ncmovne %rax,%r8\nmov $0xa,%ecx\nlea 0xca9(%rip),%rdi\nmov %rdx,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %al\nsbb $0x0,%al\ntest %al,%al\nlea 0xc5d(%rip),%rax\ncmove %rax,%r8\nmov %r8,%rax\nretq\nlea 0xc47(%rip),%r8\njmp 139d \n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nmov ebp, esi\nlea rsi, s1; \"January\"\ncall _strcmp\ntest eax, eax\njz loc_1274\nlea rsi, aFebruary; \"February\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz loc_1274\nlea rsi, aMarch; \"March\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz loc_1274\nlea rsi, aApril; \"April\"\nmov rdi, rbx; s1\ncall _strcmp\nlea r12, aSpring; \"spring\"\ntest eax, eax\njz short loc_126C\nlea rsi, aMay; \"May\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz short loc_126C\nlea rsi, aJune; \"June\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz short loc_126C\nlea rsi, aJuly; \"July\"\nmov rdi, rbx; s1\ncall _strcmp\nlea r12, aSummer; \"summer\"\ntest eax, eax\njz short loc_126C\nlea rsi, aAugust; \"August\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz short loc_126C\nlea rsi, aSeptember; \"September\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\nlea r12, aAutumn; \"autumn\"\nlea rax, aSummer; \"summer\"\ncmovz r12, rax\nloc_126C:\nmov r13d, 0\njmp short loc_129E\nloc_1274:\nlea rsi, aMarch; \"March\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\nsetz r13b\ncmp ebp, 13h\njle short loc_1297\ntest r13b, r13b\njnz loc_1326\nloc_1297:\nlea r12, aWinter; \"winter\"\nloc_129E:\nlea rsi, aJune; \"June\"\nmov rdi, rbx; s1\ncall _strcmp\ncmp ebp, 14h\nsetnle r14b\ntest eax, eax\njnz short loc_12C1\ntest r14b, r14b\njnz loc_1371\nloc_12C1:\nlea rsi, aSeptember; \"September\"\nmov rdi, rbx; s1\ncall _strcmp\ncmp ebp, 15h\njle short loc_12D9\ntest eax, eax\njz short loc_12FC\nloc_12D9:\nlea rsi, aDecember; \"December\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1365\ntest r14b, r14b\nlea rax, aWinter; \"winter\"\ncmovnz r12, rax\njmp short loc_1365\nloc_12FC:\ntest r13b, r13b\nlea rax, aSpring; \"spring\"\ncmovnz r12, rax\nlea rsi, aJune; \"June\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1349\nlea r12, aAutumn; \"autumn\"\njmp short loc_1365\nloc_1326:\nlea rsi, aJune; \"June\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\nlea r12, aSummer; \"summer\"\nlea rax, aSpring; \"spring\"\ncmovnz r12, rax\nloc_1349:\nlea rsi, aSeptember; \"September\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\nlea rax, aAutumn; \"autumn\"\ncmovz r12, rax\nloc_1365:\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1371:\nlea r12, aSummer; \"summer\"\njmp short loc_1349", + "ida_pseudo": "const char *__fastcall func0(char *s1, int a2)\n{\n const char *v2; // r12\n bool v3; // r13\n int v4; // eax\n int v5; // eax\n\n if ( !strcmp(s1, \"January\") || !strcmp(s1, \"February\") || !strcmp(s1, \"March\") )\n {\n v4 = strcmp(s1, \"March\");\n v3 = v4 == 0;\n if ( a2 > 19 && !v4 )\n {\n v2 = \"summer\";\n if ( strcmp(s1, \"June\") )\n v2 = \"spring\";\n goto LABEL_29;\n }\n v2 = \"winter\";\n }\n else\n {\n v2 = \"spring\";\n if ( strcmp(s1, \"April\") )\n {\n if ( strcmp(s1, \"May\") )\n {\n if ( strcmp(s1, \"June\") )\n {\n v2 = \"summer\";\n if ( strcmp(s1, \"July\") )\n {\n if ( strcmp(s1, \"August\") )\n {\n v2 = \"autumn\";\n if ( !strcmp(s1, \"September\") )\n v2 = \"summer\";\n }\n }\n }\n }\n }\n v3 = 0;\n }\n if ( !strcmp(s1, \"June\") && a2 > 20 )\n {\n v2 = \"summer\";\n }\n else\n {\n v5 = strcmp(s1, \"September\");\n if ( a2 <= 21 || v5 )\n {\n if ( !strcmp(s1, \"December\") && a2 > 20 )\n return \"winter\";\n return v2;\n }\n if ( v3 )\n v2 = \"spring\";\n if ( !strcmp(s1, \"June\") )\n return \"autumn\";\n }\nLABEL_29:\n if ( !strcmp(s1, \"September\") )\n return \"autumn\";\n return v2;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nmov ebp, esi\nlea rsi, s1; \"January\"\ncall _strcmp\ntest eax, eax\njz loc_1274\nlea rsi, aFebruary; \"February\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz loc_1274\nlea rsi, aMarch; \"March\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz loc_1274\nlea rsi, aApril; \"April\"\nmov rdi, rbx; s1\ncall _strcmp\nlea r12, aSpring; \"spring\"\ntest eax, eax\njz short loc_126C\nlea rsi, aMay; \"May\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz short loc_126C\nlea rsi, aJune; \"June\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz short loc_126C\nlea rsi, aJuly; \"July\"\nmov rdi, rbx; s1\ncall _strcmp\nlea r12, aSummer; \"summer\"\ntest eax, eax\njz short loc_126C\nlea rsi, aAugust; \"August\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz short loc_126C\nlea rsi, aSeptember; \"September\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\nlea r12, aAutumn; \"autumn\"\nlea rax, aSummer; \"summer\"\ncmovz r12, rax\nloc_126C:\nmov r13d, 0\njmp short loc_129E\nloc_1274:\nlea rsi, aMarch; \"March\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\nsetz r13b\ncmp ebp, 13h\njle short loc_1297\ntest r13b, r13b\njnz loc_1326\nloc_1297:\nlea r12, aWinter; \"winter\"\nloc_129E:\nlea rsi, aJune; \"June\"\nmov rdi, rbx; s1\ncall _strcmp\ncmp ebp, 14h\nsetnle r14b\ntest eax, eax\njnz short loc_12C1\ntest r14b, r14b\njnz loc_1371\nloc_12C1:\nlea rsi, aSeptember; \"September\"\nmov rdi, rbx; s1\ncall _strcmp\ncmp ebp, 15h\njle short loc_12D9\ntest eax, eax\njz short loc_12FC\nloc_12D9:\nlea rsi, aDecember; \"December\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1365\ntest r14b, r14b\nlea rax, aWinter; \"winter\"\ncmovnz r12, rax\njmp short loc_1365\nloc_12FC:\ntest r13b, r13b\nlea rax, aSpring; \"spring\"\ncmovnz r12, rax\nlea rsi, aJune; \"June\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1349\nlea r12, aAutumn; \"autumn\"\njmp short loc_1365\nloc_1326:\nlea rsi, aJune; \"June\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\nlea r12, aSummer; \"summer\"\nlea rax, aSpring; \"spring\"\ncmovnz r12, rax\nloc_1349:\nlea rsi, aSeptember; \"September\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\nlea rax, aAutumn; \"autumn\"\ncmovz r12, rax\nloc_1365:\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1371:\nlea r12, aSummer; \"summer\"\njmp short loc_1349", + "ida_strip_pseudo": "const char *__fastcall sub_1189(char *s1, int a2)\n{\n const char *v2; // r12\n bool v3; // r13\n int v4; // eax\n int v5; // eax\n\n if ( !strcmp(s1, \"January\") || !strcmp(s1, \"February\") || !strcmp(s1, \"March\") )\n {\n v4 = strcmp(s1, \"March\");\n v3 = v4 == 0;\n if ( a2 > 19 && !v4 )\n {\n v2 = \"summer\";\n if ( strcmp(s1, \"June\") )\n v2 = \"spring\";\n goto LABEL_29;\n }\n v2 = \"winter\";\n }\n else\n {\n v2 = \"spring\";\n if ( strcmp(s1, \"April\") )\n {\n if ( strcmp(s1, \"May\") )\n {\n if ( strcmp(s1, \"June\") )\n {\n v2 = \"summer\";\n if ( strcmp(s1, \"July\") )\n {\n if ( strcmp(s1, \"August\") )\n {\n v2 = \"autumn\";\n if ( !strcmp(s1, \"September\") )\n v2 = \"summer\";\n }\n }\n }\n }\n }\n v3 = 0;\n }\n if ( !strcmp(s1, \"June\") && a2 > 20 )\n {\n v2 = \"summer\";\n }\n else\n {\n v5 = strcmp(s1, \"September\");\n if ( a2 <= 21 || v5 )\n {\n if ( !strcmp(s1, \"December\") && a2 > 20 )\n return \"winter\";\n return v2;\n }\n if ( v3 )\n v2 = \"spring\";\n if ( !strcmp(s1, \"June\") )\n return \"autumn\";\n }\nLABEL_29:\n if ( !strcmp(s1, \"September\") )\n return \"autumn\";\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1189(char *s1, int a2) {\n const char *v2;\n bool v3;\n int v4;\n int v5;\n if (!strcmp(s1, \"January\") || !strcmp(s1, \"February\") ||\n !strcmp(s1, \"March\")) {\n v4 = strcmp(s1, \"March\");\n v3 = v4 == 0;\n if (a2 > 19 && !v4) {\n v2 = \"summer\";\n if (strcmp(s1, \"June\")) v2 = \"spring\";\n goto LABEL_29;\n }\n v2 = \"winter\";\n } else {\n v2 = \"spring\";\n if (strcmp(s1, \"April\")) {\n if (strcmp(s1, \"May\")) {\n if (strcmp(s1, \"June\")) {\n v2 = \"summer\";\n if (strcmp(s1, \"July\")) {\n if (strcmp(s1, \"August\")) {\n v2 = \"autumn\";\n if (!strcmp(s1, \"September\")) v2 = \"summer\";\n }\n }\n }\n }\n }\n v3 = 0;\n }\n if (!strcmp(s1, \"June\") && a2 > 20) {\n v2 = \"summer\";\n } else {\n v5 = strcmp(s1, \"September\");\n if (a2 <= 21 || v5) {\n if (!strcmp(s1, \"December\") && a2 > 20) return \"winter\";\n return v2;\n }\n if (v3) v2 = \"spring\";\n if (!strcmp(s1, \"June\")) return \"autumn\";\n }\nLABEL_29:\n if (!strcmp(s1, \"September\")) return \"autumn\";\n return v2;\n}", + "ida_pseudo_norm": "const char *func0(char *s1, int a2) {\n const char *v2;\n bool v3;\n int v4;\n int v5;\n if (!strcmp(s1, \"January\") || !strcmp(s1, \"February\") ||\n !strcmp(s1, \"March\")) {\n v4 = strcmp(s1, \"March\");\n v3 = v4 == 0;\n if (a2 > 19 && !v4) {\n v2 = \"summer\";\n if (strcmp(s1, \"June\")) v2 = \"spring\";\n goto LABEL_29;\n }\n v2 = \"winter\";\n } else {\n v2 = \"spring\";\n if (strcmp(s1, \"April\")) {\n if (strcmp(s1, \"May\")) {\n if (strcmp(s1, \"June\")) {\n v2 = \"summer\";\n if (strcmp(s1, \"July\")) {\n if (strcmp(s1, \"August\")) {\n v2 = \"autumn\";\n if (!strcmp(s1, \"September\")) v2 = \"summer\";\n }\n }\n }\n }\n }\n v3 = 0;\n }\n if (!strcmp(s1, \"June\") && a2 > 20) {\n v2 = \"summer\";\n } else {\n v5 = strcmp(s1, \"September\");\n if (a2 <= 21 || v5) {\n if (!strcmp(s1, \"December\") && a2 > 20) return \"winter\";\n return v2;\n }\n if (v3) v2 = \"spring\";\n if (!strcmp(s1, \"June\")) return \"autumn\";\n }\nLABEL_29:\n if (!strcmp(s1, \"September\")) return \"autumn\";\n return v2;\n}" + }, + { + "index": 159, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "const char* func0(const char* month, int days) {\n const char* season;\n if (strcmp(month, \"January\") == 0 || strcmp(month, \"February\") == 0 ||\n strcmp(month, \"March\") == 0) {\n season = \"winter\";\n } else if (strcmp(month, \"April\") == 0 || strcmp(month, \"May\") == 0 ||\n strcmp(month, \"June\") == 0) {\n season = \"spring\";\n } else if (strcmp(month, \"July\") == 0 || strcmp(month, \"August\") == 0 ||\n strcmp(month, \"September\") == 0) {\n season = \"summer\";\n } else {\n season = \"autumn\";\n }\n if ((strcmp(month, \"March\") == 0 && days > 19) ||\n (strcmp(month, \"June\") == 0 && days > 20) ||\n (strcmp(month, \"September\") == 0 && days > 21)) {\n if (strcmp(month, \"March\") == 0) {\n season = \"spring\";\n }\n if (strcmp(month, \"June\") == 0) {\n season = \"summer\";\n }\n if (strcmp(month, \"September\") == 0) {\n season = \"autumn\";\n }\n } else if ((strcmp(month, \"December\") == 0 && days > 20)) {\n season = \"winter\";\n }\n return season;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"January\", 4), \"winter\") == 0);\n\n assert(strcmp(func0(\"October\", 28), \"autumn\") == 0);\n\n assert(strcmp(func0(\"June\", 6), \"spring\") == 0);\n\n \n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%rax\nmov $0x8,%ecx\nmov %esi,%r10d\nlea 0xd9a(%rip),%rdi\nmov %rax,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nmov $0x6,%ecx\nlea 0xd91(%rip),%rdi\nmov %rax,%rsi\nseta %r11b\nsbb $0x0,%r11b\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nmov $0x5,%ecx\nlea 0xd7e(%rip),%rdi\nmov %rax,%rsi\nseta %r8b\nsbb $0x0,%r8b\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nmov $0xa,%ecx\nmov %rax,%rsi\nmovsbl %r8b,%r8d\nlea 0xd63(%rip),%rdi\nseta %dl\nsbb $0x0,%dl\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nmovsbl %dl,%edx\nseta %r9b\nsbb $0x0,%r9b\nmovsbl %r9b,%r9d\ntest %r11b,%r11b\nje 130b \nmov $0x9,%ecx\nlea 0xd45(%rip),%rdi\nmov %rax,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %cl\nsbb $0x0,%cl\ntest %cl,%cl\njne 13a0 \ntest %r8d,%r8d\njne 1316 \ncmp $0x13,%r10d\njg 1370 \ncmp $0x14,%r10d\nsetg %cl\nmov %ecx,%r11d\ntest %edx,%edx\njne 132c \ntest %cl,%cl\njne 14b0 \ntest %r9d,%r9d\njne 133b \ncmp $0x15,%r10d\njg 1450 \nlea 0xcd7(%rip),%r10\nmov %rax,%rsi\nmov $0x9,%ecx\nlea 0xd0b(%rip),%rdi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %al\nsbb $0x0,%al\ntest %al,%al\njne 1392 \ntest %r11b,%r11b\nlea 0xcb3(%rip),%rax\ncmovne %rax,%r10\nmov %r10,%rax\nretq\nxchg %ax,%ax\ntest %edx,%edx\nlea 0xc92(%rip),%r10\nlea 0xc84(%rip),%rax\ncmovne %rax,%r10\ntest %r9d,%r9d\nlea 0xc84(%rip),%rax\ncmove %rax,%r10\nmov %r10,%rax\nretq\nnopw %cs:0x0(%rax,%rax,1)\ntest %r8d,%r8d\nje 1310 \nmov $0x6,%ecx\nlea 0xc91(%rip),%rdi\nmov %rax,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %cl\nsbb $0x0,%cl\ntest %cl,%cl\nje 1480 \nmov $0x4,%ecx\nlea 0xc78(%rip),%rdi\nmov %rax,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %cl\nsbb $0x0,%cl\ntest %cl,%cl\nje 1480 \ntest %edx,%edx\nje 1480 \nmov $0x5,%ecx\nlea 0xc55(%rip),%rdi\nmov %rax,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %dl\nsbb $0x0,%dl\ntest %dl,%dl\nje 14c0 \nmov $0x7,%ecx\nlea 0xc3b(%rip),%rdi\nmov %rax,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %dl\nsbb $0x0,%dl\ntest %dl,%dl\nje 14c0 \ntest %r9d,%r9d\nje 14c0 \ncmp $0x14,%r10d\nlea 0xbd1(%rip),%r10\nsetg %r11b\njmpq 1342 \nnopw 0x0(%rax,%rax,1)\nlea 0xbbb(%rip),%r10\ntest %r8d,%r8d\nje 1392 \nlea 0xbb2(%rip),%r10\ntest %edx,%edx\njne 1384 \nlea 0xb9c(%rip),%r10\njmpq 1392 \nnopl 0x0(%rax,%rax,1)\ncmp $0x14,%r10d\nsetg %cl\nmov %ecx,%r11d\ntest %edx,%edx\njne 1492 \ntest %cl,%cl\njne 14b0 \ncmp $0x15,%r10d\nlea 0xb67(%rip),%r10\njle 1342 \ntest %r9d,%r9d\njne 1342 \njmp 1467 \nxchg %ax,%ax\nlea 0xb54(%rip),%r10\njmpq 1384 \nnopl 0x0(%rax)\ncmp $0x14,%r10d\nsetg %r11b\ntest %r9d,%r9d\njne 14d3 \ncmp $0x15,%r10d\njg 14b0 \nlea 0xb31(%rip),%r10\njmpq 1342 \n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\nmov r12d, esi\nlea rsi, s1; \"January\"\npush rbp\npush rbx\nmov rbx, rdi\ncall _strcmp\nlea rsi, aMarch; \"March\"\nmov rdi, rbx; s1\nmov r13d, eax\ncall _strcmp\nmov ebp, eax\ntest r13d, r13d\njz short loc_12CA\nlea rsi, aFebruary; \"February\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1330\nloc_12CA:\ntest ebp, ebp\njz short loc_1334\nlea rsi, aJune; \"June\"\nmov rdi, rbx; s1\nlea rbp, s2; \"winter\"\ncall _strcmp\nmov r13d, eax\nloc_12E7:\nlea r14, aSeptember; \"September\"\ntest r13d, r13d\njnz loc_1430\nloc_12F7:\ncmp r12d, 14h\njle short loc_1320\nlea rsi, aSeptember; \"September\"\nmov rdi, rbx; s1\nlea rbp, aSummer; \"summer\"\ncall _strcmp\ntest eax, eax\nlea rax, aAutumn; \"autumn\"\ncmovz rbp, rax\nloc_1320:\npop rbx\nmov rax, rbp\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1330:\ntest ebp, ebp\njnz short loc_1390\nloc_1334:\nlea rbp, s2; \"winter\"\ncmp r12d, 13h\njle short loc_1320\nmov rdi, rbx; s1\nlea rsi, aJune; \"June\"\ncall _strcmp\nmov rdi, rbx; s1\nlea rsi, aSeptember; \"September\"\nmov ebp, eax\ncall _strcmp\ntest ebp, ebp\nlea rdx, aSpring; \"spring\"\npop rbx\nlea rbp, aSummer; \"summer\"\ncmovnz rbp, rdx\ntest eax, eax\nlea rax, aAutumn; \"autumn\"\ncmovz rbp, rax\nmov rax, rbp\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1390:\nlea rsi, aApril; \"April\"\nmov rdi, rbx; s1\ncall _strcmp\nlea rsi, aJune; \"June\"\nmov rdi, rbx; s1\nmov ebp, eax\ncall _strcmp\nmov r13d, eax\ntest ebp, ebp\njz loc_1498\nlea rsi, aMay; \"May\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz loc_1498\ntest r13d, r13d\njz loc_14A8\nlea rsi, aJuly; \"July\"\nmov rdi, rbx; s1\nlea rbp, aSummer; \"summer\"\ncall _strcmp\nlea r14, aSeptember; \"September\"\ntest eax, eax\njz short loc_1430\nlea rsi, aAugust; \"August\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz short loc_1430\nmov rsi, r14; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\nlea rax, aAutumn; \"autumn\"\ncmovnz rbp, rax\nnop word ptr [rax+rax+00000000h]\nloc_1430:\nmov rsi, r14; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1460\ncmp r12d, 15h\njle short loc_1460\nlea rbp, aAutumn; \"autumn\"\npop rbx\nmov rax, rbp\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1460:\nlea rsi, aDecember; \"December\"\nmov rdi, rbx; s1\ncall _strcmp\ncmp r12d, 14h\njle loc_1320\ntest eax, eax\nlea rax, s2; \"winter\"\npop rbx\ncmovz rbp, rax\nmov rax, rbp\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1498:\nlea rbp, aSpring; \"spring\"\njmp loc_12E7\nloc_14A8:\nlea rbp, aSpring; \"spring\"\njmp loc_12F7", + "ida_pseudo": "const char *__fastcall func0(char *s1, int a2)\n{\n int v2; // r13d\n int v3; // ebp\n const char *v4; // rbp\n int v5; // r13d\n int v7; // ebp\n int v8; // eax\n bool v9; // zf\n const char *v10; // rbp\n int v11; // ebp\n int v12; // eax\n\n v2 = strcmp(s1, \"January\");\n v3 = strcmp(s1, \"March\");\n if ( v2 && strcmp(s1, \"February\") )\n {\n if ( v3 )\n {\n v11 = strcmp(s1, \"April\");\n v5 = strcmp(s1, \"June\");\n if ( v11 && strcmp(s1, \"May\") )\n {\n if ( !v5 )\n {\n v4 = \"spring\";\nLABEL_6:\n if ( a2 > 20 )\n {\n v4 = \"summer\";\n if ( !strcmp(s1, \"September\") )\n return \"autumn\";\n }\n return v4;\n }\n v4 = \"summer\";\n if ( strcmp(s1, \"July\") && strcmp(s1, \"August\") && strcmp(s1, \"September\") )\n v4 = \"autumn\";\nLABEL_24:\n if ( !strcmp(s1, \"September\") && a2 > 21 )\n return \"autumn\";\n v12 = strcmp(s1, \"December\");\n if ( a2 > 20 )\n {\n if ( !v12 )\n return \"winter\";\n return v4;\n }\n return v4;\n }\n v4 = \"spring\";\nLABEL_5:\n if ( !v5 )\n goto LABEL_6;\n goto LABEL_24;\n }\n }\n else if ( v3 )\n {\n v4 = \"winter\";\n v5 = strcmp(s1, \"June\");\n goto LABEL_5;\n }\n v4 = \"winter\";\n if ( a2 <= 19 )\n return v4;\n v7 = strcmp(s1, \"June\");\n v8 = strcmp(s1, \"September\");\n v9 = v7 == 0;\n v10 = \"summer\";\n if ( !v9 )\n v10 = \"spring\";\n if ( !v8 )\n return \"autumn\";\n return v10;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\npush r14\npush r13\npush r12\nmov r12d, esi\nlea rsi, s1; \"January\"\npush rbp\npush rbx\nmov rbx, rdi\ncall _strcmp\nlea rsi, aMarch; \"March\"\nmov rdi, rbx; s1\nmov r13d, eax\ncall _strcmp\nmov ebp, eax\ntest r13d, r13d\njz short loc_12CA\nlea rsi, aFebruary; \"February\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1330\nloc_12CA:\ntest ebp, ebp\njz short loc_1334\nlea rsi, aJune; \"June\"\nmov rdi, rbx; s1\nlea rbp, s2; \"winter\"\ncall _strcmp\nmov r13d, eax\nloc_12E7:\nlea r14, aSeptember; \"September\"\ntest r13d, r13d\njnz loc_1430\nloc_12F7:\ncmp r12d, 14h\njle short loc_1320\nlea rsi, aSeptember; \"September\"\nmov rdi, rbx; s1\nlea rbp, aSummer; \"summer\"\ncall _strcmp\ntest eax, eax\nlea rax, aAutumn; \"autumn\"\ncmovz rbp, rax\nloc_1320:\npop rbx\nmov rax, rbp\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1330:\ntest ebp, ebp\njnz short loc_1390\nloc_1334:\nlea rbp, s2; \"winter\"\ncmp r12d, 13h\njle short loc_1320\nmov rdi, rbx; s1\nlea rsi, aJune; \"June\"\ncall _strcmp\nmov rdi, rbx; s1\nlea rsi, aSeptember; \"September\"\nmov ebp, eax\ncall _strcmp\ntest ebp, ebp\nlea rdx, aSpring; \"spring\"\npop rbx\nlea rbp, aSummer; \"summer\"\ncmovnz rbp, rdx\ntest eax, eax\nlea rax, aAutumn; \"autumn\"\ncmovz rbp, rax\nmov rax, rbp\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1390:\nlea rsi, aApril; \"April\"\nmov rdi, rbx; s1\ncall _strcmp\nlea rsi, aJune; \"June\"\nmov rdi, rbx; s1\nmov ebp, eax\ncall _strcmp\nmov r13d, eax\ntest ebp, ebp\njz loc_1498\nlea rsi, aMay; \"May\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz loc_1498\ntest r13d, r13d\njz loc_14A8\nlea rsi, aJuly; \"July\"\nmov rdi, rbx; s1\nlea rbp, aSummer; \"summer\"\ncall _strcmp\nlea r14, aSeptember; \"September\"\ntest eax, eax\njz short loc_1430\nlea rsi, aAugust; \"August\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz short loc_1430\nmov rsi, r14; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\nlea rax, aAutumn; \"autumn\"\ncmovnz rbp, rax\nnop word ptr [rax+rax+00000000h]\nloc_1430:\nmov rsi, r14; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1460\ncmp r12d, 15h\njle short loc_1460\nlea rbp, aAutumn; \"autumn\"\npop rbx\nmov rax, rbp\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1460:\nlea rsi, aDecember; \"December\"\nmov rdi, rbx; s1\ncall _strcmp\ncmp r12d, 14h\njle loc_1320\ntest eax, eax\nlea rax, s2; \"winter\"\npop rbx\ncmovz rbp, rax\nmov rax, rbp\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1498:\nlea rbp, aSpring; \"spring\"\njmp loc_12E7\nloc_14A8:\nlea rbp, aSpring; \"spring\"\njmp loc_12F7", + "ida_strip_pseudo": "const char *__fastcall sub_1280(char *s1, int a2)\n{\n int v2; // r13d\n int v3; // ebp\n const char *v4; // rbp\n int v5; // r13d\n int v7; // ebp\n int v8; // eax\n bool v9; // zf\n const char *v10; // rbp\n int v11; // ebp\n int v12; // eax\n\n v2 = strcmp(s1, \"January\");\n v3 = strcmp(s1, \"March\");\n if ( v2 && strcmp(s1, \"February\") )\n {\n if ( v3 )\n {\n v11 = strcmp(s1, \"April\");\n v5 = strcmp(s1, \"June\");\n if ( v11 && strcmp(s1, \"May\") )\n {\n if ( !v5 )\n {\n v4 = \"spring\";\nLABEL_6:\n if ( a2 > 20 )\n {\n v4 = \"summer\";\n if ( !strcmp(s1, \"September\") )\n return \"autumn\";\n }\n return v4;\n }\n v4 = \"summer\";\n if ( strcmp(s1, \"July\") && strcmp(s1, \"August\") && strcmp(s1, \"September\") )\n v4 = \"autumn\";\nLABEL_24:\n if ( !strcmp(s1, \"September\") && a2 > 21 )\n return \"autumn\";\n v12 = strcmp(s1, \"December\");\n if ( a2 > 20 )\n {\n if ( !v12 )\n return \"winter\";\n return v4;\n }\n return v4;\n }\n v4 = \"spring\";\nLABEL_5:\n if ( !v5 )\n goto LABEL_6;\n goto LABEL_24;\n }\n }\n else if ( v3 )\n {\n v4 = \"winter\";\n v5 = strcmp(s1, \"June\");\n goto LABEL_5;\n }\n v4 = \"winter\";\n if ( a2 <= 19 )\n return v4;\n v7 = strcmp(s1, \"June\");\n v8 = strcmp(s1, \"September\");\n v9 = v7 == 0;\n v10 = \"summer\";\n if ( !v9 )\n v10 = \"spring\";\n if ( !v8 )\n return \"autumn\";\n return v10;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1280(char *s1, int a2) {\n int v2;\n int v3;\n const char *v4;\n int v5;\n int v7;\n int v8;\n bool v9;\n const char *v10;\n int v11;\n int v12;\n v2 = strcmp(s1, \"January\");\n v3 = strcmp(s1, \"March\");\n if (v2 && strcmp(s1, \"February\")) {\n if (v3) {\n v11 = strcmp(s1, \"April\");\n v5 = strcmp(s1, \"June\");\n if (v11 && strcmp(s1, \"May\")) {\n if (!v5) {\n v4 = \"spring\";\n LABEL_6:\n if (a2 > 20) {\n v4 = \"summer\";\n if (!strcmp(s1, \"September\")) return \"autumn\";\n }\n return v4;\n }\n v4 = \"summer\";\n if (strcmp(s1, \"July\") && strcmp(s1, \"August\") &&\n strcmp(s1, \"September\"))\n v4 = \"autumn\";\n LABEL_24:\n if (!strcmp(s1, \"September\") && a2 > 21) return \"autumn\";\n v12 = strcmp(s1, \"December\");\n if (a2 > 20) {\n if (!v12) return \"winter\";\n return v4;\n }\n return v4;\n }\n v4 = \"spring\";\n LABEL_5:\n if (!v5) goto LABEL_6;\n goto LABEL_24;\n }\n } else if (v3) {\n v4 = \"winter\";\n v5 = strcmp(s1, \"June\");\n goto LABEL_5;\n }\n v4 = \"winter\";\n if (a2 <= 19) return v4;\n v7 = strcmp(s1, \"June\");\n v8 = strcmp(s1, \"September\");\n v9 = v7 == 0;\n v10 = \"summer\";\n if (!v9) v10 = \"spring\";\n if (!v8) return \"autumn\";\n return v10;\n}", + "ida_pseudo_norm": "const char *func0(char *s1, int a2) {\n int v2;\n int v3;\n const char *v4;\n int v5;\n int v7;\n int v8;\n bool v9;\n const char *v10;\n int v11;\n int v12;\n v2 = strcmp(s1, \"January\");\n v3 = strcmp(s1, \"March\");\n if (v2 && strcmp(s1, \"February\")) {\n if (v3) {\n v11 = strcmp(s1, \"April\");\n v5 = strcmp(s1, \"June\");\n if (v11 && strcmp(s1, \"May\")) {\n if (!v5) {\n v4 = \"spring\";\n LABEL_6:\n if (a2 > 20) {\n v4 = \"summer\";\n if (!strcmp(s1, \"September\")) return \"autumn\";\n }\n return v4;\n }\n v4 = \"summer\";\n if (strcmp(s1, \"July\") && strcmp(s1, \"August\") &&\n strcmp(s1, \"September\"))\n v4 = \"autumn\";\n LABEL_24:\n if (!strcmp(s1, \"September\") && a2 > 21) return \"autumn\";\n v12 = strcmp(s1, \"December\");\n if (a2 > 20) {\n if (!v12) return \"winter\";\n return v4;\n }\n return v4;\n }\n v4 = \"spring\";\n LABEL_5:\n if (!v5) goto LABEL_6;\n goto LABEL_24;\n }\n } else if (v3) {\n v4 = \"winter\";\n v5 = strcmp(s1, \"June\");\n goto LABEL_5;\n }\n v4 = \"winter\";\n if (a2 <= 19) return v4;\n v7 = strcmp(s1, \"June\");\n v8 = strcmp(s1, \"September\");\n v9 = v7 == 0;\n v10 = \"summer\";\n if (!v9) v10 = \"spring\";\n if (!v8) return \"autumn\";\n return v10;\n}" + }, + { + "index": 159, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "const char* func0(const char* month, int days) {\n const char* season;\n if (strcmp(month, \"January\") == 0 || strcmp(month, \"February\") == 0 ||\n strcmp(month, \"March\") == 0) {\n season = \"winter\";\n } else if (strcmp(month, \"April\") == 0 || strcmp(month, \"May\") == 0 ||\n strcmp(month, \"June\") == 0) {\n season = \"spring\";\n } else if (strcmp(month, \"July\") == 0 || strcmp(month, \"August\") == 0 ||\n strcmp(month, \"September\") == 0) {\n season = \"summer\";\n } else {\n season = \"autumn\";\n }\n if ((strcmp(month, \"March\") == 0 && days > 19) ||\n (strcmp(month, \"June\") == 0 && days > 20) ||\n (strcmp(month, \"September\") == 0 && days > 21)) {\n if (strcmp(month, \"March\") == 0) {\n season = \"spring\";\n }\n if (strcmp(month, \"June\") == 0) {\n season = \"summer\";\n }\n if (strcmp(month, \"September\") == 0) {\n season = \"autumn\";\n }\n } else if ((strcmp(month, \"December\") == 0 && days > 20)) {\n season = \"winter\";\n }\n return season;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"January\", 4), \"winter\") == 0);\n\n assert(strcmp(func0(\"October\", 28), \"autumn\") == 0);\n\n assert(strcmp(func0(\"June\", 6), \"spring\") == 0);\n\n \n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%rax\nmov $0x8,%ecx\nmov %esi,%r10d\nlea 0xd9a(%rip),%rdi\nmov %rax,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nmov $0x6,%ecx\nlea 0xd91(%rip),%rdi\nmov %rax,%rsi\nseta %r11b\nsbb $0x0,%r11b\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nmov $0x5,%ecx\nlea 0xd7e(%rip),%rdi\nmov %rax,%rsi\nseta %r8b\nsbb $0x0,%r8b\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nmov $0xa,%ecx\nmov %rax,%rsi\nmovsbl %r8b,%r8d\nlea 0xd63(%rip),%rdi\nseta %dl\nsbb $0x0,%dl\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nmovsbl %dl,%edx\nseta %r9b\nsbb $0x0,%r9b\nmovsbl %r9b,%r9d\ntest %r11b,%r11b\nje 130b \nmov $0x9,%ecx\nlea 0xd45(%rip),%rdi\nmov %rax,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %cl\nsbb $0x0,%cl\ntest %cl,%cl\njne 13a0 \ntest %r8d,%r8d\njne 1316 \ncmp $0x13,%r10d\njg 1370 \ncmp $0x14,%r10d\nsetg %cl\nmov %ecx,%r11d\ntest %edx,%edx\njne 132c \ntest %cl,%cl\njne 14b0 \ntest %r9d,%r9d\njne 133b \ncmp $0x15,%r10d\njg 1450 \nlea 0xcd7(%rip),%r10\nmov %rax,%rsi\nmov $0x9,%ecx\nlea 0xd0b(%rip),%rdi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %al\nsbb $0x0,%al\ntest %al,%al\njne 1392 \ntest %r11b,%r11b\nlea 0xcb3(%rip),%rax\ncmovne %rax,%r10\nmov %r10,%rax\nretq\nxchg %ax,%ax\ntest %edx,%edx\nlea 0xc92(%rip),%r10\nlea 0xc84(%rip),%rax\ncmovne %rax,%r10\ntest %r9d,%r9d\nlea 0xc84(%rip),%rax\ncmove %rax,%r10\nmov %r10,%rax\nretq\nnopw %cs:0x0(%rax,%rax,1)\ntest %r8d,%r8d\nje 1310 \nmov $0x6,%ecx\nlea 0xc91(%rip),%rdi\nmov %rax,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %cl\nsbb $0x0,%cl\ntest %cl,%cl\nje 1480 \nmov $0x4,%ecx\nlea 0xc78(%rip),%rdi\nmov %rax,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %cl\nsbb $0x0,%cl\ntest %cl,%cl\nje 1480 \ntest %edx,%edx\nje 1480 \nmov $0x5,%ecx\nlea 0xc55(%rip),%rdi\nmov %rax,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %dl\nsbb $0x0,%dl\ntest %dl,%dl\nje 14c0 \nmov $0x7,%ecx\nlea 0xc3b(%rip),%rdi\nmov %rax,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %dl\nsbb $0x0,%dl\ntest %dl,%dl\nje 14c0 \ntest %r9d,%r9d\nje 14c0 \ncmp $0x14,%r10d\nlea 0xbd1(%rip),%r10\nsetg %r11b\njmpq 1342 \nnopw 0x0(%rax,%rax,1)\nlea 0xbbb(%rip),%r10\ntest %r8d,%r8d\nje 1392 \nlea 0xbb2(%rip),%r10\ntest %edx,%edx\njne 1384 \nlea 0xb9c(%rip),%r10\njmpq 1392 \nnopl 0x0(%rax,%rax,1)\ncmp $0x14,%r10d\nsetg %cl\nmov %ecx,%r11d\ntest %edx,%edx\njne 1492 \ntest %cl,%cl\njne 14b0 \ncmp $0x15,%r10d\nlea 0xb67(%rip),%r10\njle 1342 \ntest %r9d,%r9d\njne 1342 \njmp 1467 \nxchg %ax,%ax\nlea 0xb54(%rip),%r10\njmpq 1384 \nnopl 0x0(%rax)\ncmp $0x14,%r10d\nsetg %r11b\ntest %r9d,%r9d\njne 14d3 \ncmp $0x15,%r10d\njg 14b0 \nlea 0xb31(%rip),%r10\njmpq 1342 \n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\nmov r12d, esi\nlea rsi, s1; \"January\"\npush rbp\npush rbx\nmov rbx, rdi\ncall _strcmp\nlea rsi, aMarch; \"March\"\nmov rdi, rbx; s1\nmov r13d, eax\ncall _strcmp\nmov ebp, eax\ntest r13d, r13d\njz short loc_12CA\nlea rsi, aFebruary; \"February\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1330\nloc_12CA:\ntest ebp, ebp\njz short loc_1334\nlea rsi, aJune; \"June\"\nmov rdi, rbx; s1\nlea rbp, s2; \"winter\"\ncall _strcmp\nmov r13d, eax\nloc_12E7:\nlea r14, aSeptember; \"September\"\ntest r13d, r13d\njnz loc_1430\nloc_12F7:\ncmp r12d, 14h\njle short loc_1320\nlea rsi, aSeptember; \"September\"\nmov rdi, rbx; s1\nlea rbp, aSummer; \"summer\"\ncall _strcmp\ntest eax, eax\nlea rax, aAutumn; \"autumn\"\ncmovz rbp, rax\nloc_1320:\npop rbx\nmov rax, rbp\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1330:\ntest ebp, ebp\njnz short loc_1390\nloc_1334:\nlea rbp, s2; \"winter\"\ncmp r12d, 13h\njle short loc_1320\nmov rdi, rbx; s1\nlea rsi, aJune; \"June\"\ncall _strcmp\nmov rdi, rbx; s1\nlea rsi, aSeptember; \"September\"\nmov ebp, eax\ncall _strcmp\ntest ebp, ebp\nlea rdx, aSpring; \"spring\"\npop rbx\nlea rbp, aSummer; \"summer\"\ncmovnz rbp, rdx\ntest eax, eax\nlea rax, aAutumn; \"autumn\"\ncmovz rbp, rax\nmov rax, rbp\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1390:\nlea rsi, aApril; \"April\"\nmov rdi, rbx; s1\ncall _strcmp\nlea rsi, aJune; \"June\"\nmov rdi, rbx; s1\nmov ebp, eax\ncall _strcmp\nmov r13d, eax\ntest ebp, ebp\njz loc_1498\nlea rsi, aMay; \"May\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz loc_1498\ntest r13d, r13d\njz loc_14A8\nlea rsi, aJuly; \"July\"\nmov rdi, rbx; s1\nlea rbp, aSummer; \"summer\"\ncall _strcmp\nlea r14, aSeptember; \"September\"\ntest eax, eax\njz short loc_1430\nlea rsi, aAugust; \"August\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz short loc_1430\nmov rsi, r14; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\nlea rax, aAutumn; \"autumn\"\ncmovnz rbp, rax\nnop word ptr [rax+rax+00000000h]\nloc_1430:\nmov rsi, r14; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1460\ncmp r12d, 15h\njle short loc_1460\nlea rbp, aAutumn; \"autumn\"\npop rbx\nmov rax, rbp\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1460:\nlea rsi, aDecember; \"December\"\nmov rdi, rbx; s1\ncall _strcmp\ncmp r12d, 14h\njle loc_1320\ntest eax, eax\nlea rax, s2; \"winter\"\npop rbx\ncmovz rbp, rax\nmov rax, rbp\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1498:\nlea rbp, aSpring; \"spring\"\njmp loc_12E7\nloc_14A8:\nlea rbp, aSpring; \"spring\"\njmp loc_12F7", + "ida_pseudo": "const char *__fastcall func0(char *s1, int a2)\n{\n int v2; // r13d\n int v3; // ebp\n const char *v4; // rbp\n int v5; // r13d\n int v7; // ebp\n int v8; // eax\n bool v9; // zf\n const char *v10; // rbp\n int v11; // ebp\n int v12; // eax\n\n v2 = strcmp(s1, \"January\");\n v3 = strcmp(s1, \"March\");\n if ( v2 && strcmp(s1, \"February\") )\n {\n if ( v3 )\n {\n v11 = strcmp(s1, \"April\");\n v5 = strcmp(s1, \"June\");\n if ( v11 && strcmp(s1, \"May\") )\n {\n if ( !v5 )\n {\n v4 = \"spring\";\nLABEL_6:\n if ( a2 > 20 )\n {\n v4 = \"summer\";\n if ( !strcmp(s1, \"September\") )\n return \"autumn\";\n }\n return v4;\n }\n v4 = \"summer\";\n if ( strcmp(s1, \"July\") && strcmp(s1, \"August\") && strcmp(s1, \"September\") )\n v4 = \"autumn\";\nLABEL_24:\n if ( !strcmp(s1, \"September\") && a2 > 21 )\n return \"autumn\";\n v12 = strcmp(s1, \"December\");\n if ( a2 > 20 )\n {\n if ( !v12 )\n return \"winter\";\n return v4;\n }\n return v4;\n }\n v4 = \"spring\";\nLABEL_5:\n if ( !v5 )\n goto LABEL_6;\n goto LABEL_24;\n }\n }\n else if ( v3 )\n {\n v4 = \"winter\";\n v5 = strcmp(s1, \"June\");\n goto LABEL_5;\n }\n v4 = \"winter\";\n if ( a2 <= 19 )\n return v4;\n v7 = strcmp(s1, \"June\");\n v8 = strcmp(s1, \"September\");\n v9 = v7 == 0;\n v10 = \"summer\";\n if ( !v9 )\n v10 = \"spring\";\n if ( !v8 )\n return \"autumn\";\n return v10;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\npush r14\npush r13\npush r12\nmov r12d, esi\nlea rsi, s1; \"January\"\npush rbp\npush rbx\nmov rbx, rdi\ncall _strcmp\nlea rsi, aMarch; \"March\"\nmov rdi, rbx; s1\nmov r13d, eax\ncall _strcmp\nmov ebp, eax\ntest r13d, r13d\njz short loc_12CA\nlea rsi, aFebruary; \"February\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1330\nloc_12CA:\ntest ebp, ebp\njz short loc_1334\nlea rsi, aJune; \"June\"\nmov rdi, rbx; s1\nlea rbp, s2; \"winter\"\ncall _strcmp\nmov r13d, eax\nloc_12E7:\nlea r14, aSeptember; \"September\"\ntest r13d, r13d\njnz loc_1430\nloc_12F7:\ncmp r12d, 14h\njle short loc_1320\nlea rsi, aSeptember; \"September\"\nmov rdi, rbx; s1\nlea rbp, aSummer; \"summer\"\ncall _strcmp\ntest eax, eax\nlea rax, aAutumn; \"autumn\"\ncmovz rbp, rax\nloc_1320:\npop rbx\nmov rax, rbp\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1330:\ntest ebp, ebp\njnz short loc_1390\nloc_1334:\nlea rbp, s2; \"winter\"\ncmp r12d, 13h\njle short loc_1320\nmov rdi, rbx; s1\nlea rsi, aJune; \"June\"\ncall _strcmp\nmov rdi, rbx; s1\nlea rsi, aSeptember; \"September\"\nmov ebp, eax\ncall _strcmp\ntest ebp, ebp\nlea rdx, aSpring; \"spring\"\npop rbx\nlea rbp, aSummer; \"summer\"\ncmovnz rbp, rdx\ntest eax, eax\nlea rax, aAutumn; \"autumn\"\ncmovz rbp, rax\nmov rax, rbp\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1390:\nlea rsi, aApril; \"April\"\nmov rdi, rbx; s1\ncall _strcmp\nlea rsi, aJune; \"June\"\nmov rdi, rbx; s1\nmov ebp, eax\ncall _strcmp\nmov r13d, eax\ntest ebp, ebp\njz loc_1498\nlea rsi, aMay; \"May\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz loc_1498\ntest r13d, r13d\njz loc_14A8\nlea rsi, aJuly; \"July\"\nmov rdi, rbx; s1\nlea rbp, aSummer; \"summer\"\ncall _strcmp\nlea r14, aSeptember; \"September\"\ntest eax, eax\njz short loc_1430\nlea rsi, aAugust; \"August\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz short loc_1430\nmov rsi, r14; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\nlea rax, aAutumn; \"autumn\"\ncmovnz rbp, rax\nnop word ptr [rax+rax+00000000h]\nloc_1430:\nmov rsi, r14; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1460\ncmp r12d, 15h\njle short loc_1460\nlea rbp, aAutumn; \"autumn\"\npop rbx\nmov rax, rbp\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1460:\nlea rsi, aDecember; \"December\"\nmov rdi, rbx; s1\ncall _strcmp\ncmp r12d, 14h\njle loc_1320\ntest eax, eax\nlea rax, s2; \"winter\"\npop rbx\ncmovz rbp, rax\nmov rax, rbp\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1498:\nlea rbp, aSpring; \"spring\"\njmp loc_12E7\nloc_14A8:\nlea rbp, aSpring; \"spring\"\njmp loc_12F7", + "ida_strip_pseudo": "const char *__fastcall sub_1280(char *s1, int a2)\n{\n int v2; // r13d\n int v3; // ebp\n const char *v4; // rbp\n int v5; // r13d\n int v7; // ebp\n int v8; // eax\n bool v9; // zf\n const char *v10; // rbp\n int v11; // ebp\n int v12; // eax\n\n v2 = strcmp(s1, \"January\");\n v3 = strcmp(s1, \"March\");\n if ( v2 && strcmp(s1, \"February\") )\n {\n if ( v3 )\n {\n v11 = strcmp(s1, \"April\");\n v5 = strcmp(s1, \"June\");\n if ( v11 && strcmp(s1, \"May\") )\n {\n if ( !v5 )\n {\n v4 = \"spring\";\nLABEL_6:\n if ( a2 > 20 )\n {\n v4 = \"summer\";\n if ( !strcmp(s1, \"September\") )\n return \"autumn\";\n }\n return v4;\n }\n v4 = \"summer\";\n if ( strcmp(s1, \"July\") && strcmp(s1, \"August\") && strcmp(s1, \"September\") )\n v4 = \"autumn\";\nLABEL_24:\n if ( !strcmp(s1, \"September\") && a2 > 21 )\n return \"autumn\";\n v12 = strcmp(s1, \"December\");\n if ( a2 > 20 )\n {\n if ( !v12 )\n return \"winter\";\n return v4;\n }\n return v4;\n }\n v4 = \"spring\";\nLABEL_5:\n if ( !v5 )\n goto LABEL_6;\n goto LABEL_24;\n }\n }\n else if ( v3 )\n {\n v4 = \"winter\";\n v5 = strcmp(s1, \"June\");\n goto LABEL_5;\n }\n v4 = \"winter\";\n if ( a2 <= 19 )\n return v4;\n v7 = strcmp(s1, \"June\");\n v8 = strcmp(s1, \"September\");\n v9 = v7 == 0;\n v10 = \"summer\";\n if ( !v9 )\n v10 = \"spring\";\n if ( !v8 )\n return \"autumn\";\n return v10;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1280(char *s1, int a2) {\n int v2;\n int v3;\n const char *v4;\n int v5;\n int v7;\n int v8;\n bool v9;\n const char *v10;\n int v11;\n int v12;\n v2 = strcmp(s1, \"January\");\n v3 = strcmp(s1, \"March\");\n if (v2 && strcmp(s1, \"February\")) {\n if (v3) {\n v11 = strcmp(s1, \"April\");\n v5 = strcmp(s1, \"June\");\n if (v11 && strcmp(s1, \"May\")) {\n if (!v5) {\n v4 = \"spring\";\n LABEL_6:\n if (a2 > 20) {\n v4 = \"summer\";\n if (!strcmp(s1, \"September\")) return \"autumn\";\n }\n return v4;\n }\n v4 = \"summer\";\n if (strcmp(s1, \"July\") && strcmp(s1, \"August\") &&\n strcmp(s1, \"September\"))\n v4 = \"autumn\";\n LABEL_24:\n if (!strcmp(s1, \"September\") && a2 > 21) return \"autumn\";\n v12 = strcmp(s1, \"December\");\n if (a2 > 20) {\n if (!v12) return \"winter\";\n return v4;\n }\n return v4;\n }\n v4 = \"spring\";\n LABEL_5:\n if (!v5) goto LABEL_6;\n goto LABEL_24;\n }\n } else if (v3) {\n v4 = \"winter\";\n v5 = strcmp(s1, \"June\");\n goto LABEL_5;\n }\n v4 = \"winter\";\n if (a2 <= 19) return v4;\n v7 = strcmp(s1, \"June\");\n v8 = strcmp(s1, \"September\");\n v9 = v7 == 0;\n v10 = \"summer\";\n if (!v9) v10 = \"spring\";\n if (!v8) return \"autumn\";\n return v10;\n}", + "ida_pseudo_norm": "const char *func0(char *s1, int a2) {\n int v2;\n int v3;\n const char *v4;\n int v5;\n int v7;\n int v8;\n bool v9;\n const char *v10;\n int v11;\n int v12;\n v2 = strcmp(s1, \"January\");\n v3 = strcmp(s1, \"March\");\n if (v2 && strcmp(s1, \"February\")) {\n if (v3) {\n v11 = strcmp(s1, \"April\");\n v5 = strcmp(s1, \"June\");\n if (v11 && strcmp(s1, \"May\")) {\n if (!v5) {\n v4 = \"spring\";\n LABEL_6:\n if (a2 > 20) {\n v4 = \"summer\";\n if (!strcmp(s1, \"September\")) return \"autumn\";\n }\n return v4;\n }\n v4 = \"summer\";\n if (strcmp(s1, \"July\") && strcmp(s1, \"August\") &&\n strcmp(s1, \"September\"))\n v4 = \"autumn\";\n LABEL_24:\n if (!strcmp(s1, \"September\") && a2 > 21) return \"autumn\";\n v12 = strcmp(s1, \"December\");\n if (a2 > 20) {\n if (!v12) return \"winter\";\n return v4;\n }\n return v4;\n }\n v4 = \"spring\";\n LABEL_5:\n if (!v5) goto LABEL_6;\n goto LABEL_24;\n }\n } else if (v3) {\n v4 = \"winter\";\n v5 = strcmp(s1, \"June\");\n goto LABEL_5;\n }\n v4 = \"winter\";\n if (a2 <= 19) return v4;\n v7 = strcmp(s1, \"June\");\n v8 = strcmp(s1, \"September\");\n v9 = v7 == 0;\n v10 = \"summer\";\n if (!v9) v10 = \"spring\";\n if (!v8) return \"autumn\";\n return v10;\n}" + }, + { + "index": 160, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(int a, int b, int n) {\n int i = 0;\n static char result[50];\n while (i * a <= n) {\n if ((n - (i * a)) % b == 0) {\n sprintf(result, \"x = %d, y = %d\", i, (n - (i * a)) / b);\n return result;\n }\n i++;\n }\n return \"No solution\";\n}", + "test": "int main() {\n\n assert(strcmp(func0(2, 3, 7), \"x = 2, y = 1\") == 0);\n\n assert(strcmp(func0(4, 2, 7), \"No solution\") == 0);\n\n assert(strcmp(func0(1, 13, 17), \"x = 4, y = 1\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov %edx,-0x1c(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11ff \nmov -0x4(%rbp),%eax\nimul -0x14(%rbp),%eax\nmov -0x1c(%rbp),%edx\nsub %eax,%edx\nmov %edx,%eax\ncltd\nidivl -0x18(%rbp)\nmov %edx,%eax\ntest %eax,%eax\njne 11fb \nmov -0x4(%rbp),%eax\nimul -0x14(%rbp),%eax\nmov -0x1c(%rbp),%edx\nsub %eax,%edx\nmov %edx,%eax\ncltd\nidivl -0x18(%rbp)\nmov %eax,%edx\nmov -0x4(%rbp),%eax\nmov %edx,%ecx\nmov %eax,%edx\nlea 0xe27(%rip),%rsi\nlea 0x2e58(%rip),%rdi\nmov $0x0,%eax\ncallq 1090 \nlea 0x2e47(%rip),%rax\njmp 1212 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nimul -0x14(%rbp),%eax\ncmp %eax,-0x1c(%rbp)\njge 11a7 \nlea 0xe05(%rip),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov [rbp+var_4], 0\njmp short loc_1205\nloc_11A7:\nmov eax, [rbp+var_4]\nimul eax, [rbp+var_14]\nmov edx, [rbp+var_1C]\nsub edx, eax\nmov eax, edx\ncdq\nidiv [rbp+var_18]\nmov eax, edx\ntest eax, eax\njnz short loc_1201\nmov eax, [rbp+var_4]\nimul eax, [rbp+var_14]\nmov edx, [rbp+var_1C]\nsub edx, eax\nmov eax, edx\ncdq\nidiv [rbp+var_18]\nmov edx, eax\nmov eax, [rbp+var_4]\nmov ecx, edx\nmov edx, eax\nlea rax, format; \"x = %d, y = %d\"\nmov rsi, rax; format\nlea rax, result_1\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rax, result_1\njmp short locret_1218\nloc_1201:\nadd [rbp+var_4], 1\nloc_1205:\nmov eax, [rbp+var_4]\nimul eax, [rbp+var_14]\ncmp [rbp+var_1C], eax\njge short loc_11A7\nlea rax, aNoSolution; \"No solution\"\nlocret_1218:\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(int a1, int a2, int a3)\n{\n int i; // [rsp+1Ch] [rbp-4h]\n\n for ( i = 0; a3 >= a1 * i; ++i )\n {\n if ( !((a3 - a1 * i) % a2) )\n {\n sprintf(result_1, \"x = %d, y = %d\", i, (a3 - a1 * i) / a2);\n return result_1;\n }\n }\n return \"No solution\";\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov [rbp+var_4], 0\njmp short loc_1205\nloc_11A7:\nmov eax, [rbp+var_4]\nimul eax, [rbp+var_14]\nmov edx, [rbp+var_1C]\nsub edx, eax\nmov eax, edx\ncdq\nidiv [rbp+var_18]\nmov eax, edx\ntest eax, eax\njnz short loc_1201\nmov eax, [rbp+var_4]\nimul eax, [rbp+var_14]\nmov edx, [rbp+var_1C]\nsub edx, eax\nmov eax, edx\ncdq\nidiv [rbp+var_18]\nmov edx, eax\nmov eax, [rbp+var_4]\nmov ecx, edx\nmov edx, eax\nlea rax, format; \"x = %d, y = %d\"\nmov rsi, rax; format\nlea rax, s\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rax, s\njmp short locret_1218\nloc_1201:\nadd [rbp+var_4], 1\nloc_1205:\nmov eax, [rbp+var_4]\nimul eax, [rbp+var_14]\ncmp [rbp+var_1C], eax\njge short loc_11A7\nlea rax, aNoSolution; \"No solution\"\nlocret_1218:\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1189(int a1, int a2, int a3)\n{\n int i; // [rsp+1Ch] [rbp-4h]\n\n for ( i = 0; a3 >= a1 * i; ++i )\n {\n if ( !((a3 - a1 * i) % a2) )\n {\n sprintf(s, \"x = %d, y = %d\", i, (a3 - a1 * i) / a2);\n return s;\n }\n }\n return \"No solution\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char* sub_1189(int a1, int a2, int a3) {\n int i;\n for (i = 0; a3 >= a1 * i; ++i) {\n if (!((a3 - a1 * i) % a2)) {\n sprintf(s, \"x = %d, y = %d\", i, (a3 - a1 * i) / a2);\n return s;\n }\n }\n return \"No solution\";\n}", + "ida_pseudo_norm": "char* func0(int a1, int a2, int a3) {\n int i;\n for (i = 0; a3 >= a1 * i; ++i) {\n if (!((a3 - a1 * i) % a2)) {\n sprintf(result_1, \"x = %d, y = %d\", i, (a3 - a1 * i) / a2);\n return result_1;\n }\n }\n return \"No solution\";\n}" + }, + { + "index": 160, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(int a, int b, int n) {\n int i = 0;\n static char result[50];\n while (i * a <= n) {\n if ((n - (i * a)) % b == 0) {\n sprintf(result, \"x = %d, y = %d\", i, (n - (i * a)) / b);\n return result;\n }\n i++;\n }\n return \"No solution\";\n}", + "test": "int main() {\n\n assert(strcmp(func0(2, 3, 7), \"x = 2, y = 1\") == 0);\n\n assert(strcmp(func0(4, 2, 7), \"No solution\") == 0);\n\n assert(strcmp(func0(1, 13, 17), \"x = 4, y = 1\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nlea 0xe90(%rip),%rax\ntest %edx,%edx\njs 11f5 \npush %rbx\nmov %edx,%r11d\nmov %edx,%eax\ncltd\nidiv %esi\nmov %edx,%r8d\ntest %edx,%edx\nje 11e7 \nmov %edi,%ebx\nmov %r11d,%r10d\nsub %edi,%r10d\nmov %edi,%ecx\nmov $0x0,%r8d\nadd $0x1,%r8d\ncmp %ecx,%r11d\njl 11ec \nmov %r10d,%r9d\nadd %ebx,%ecx\nsub %edi,%r10d\nmov %r9d,%eax\ncltd\nidiv %esi\ntest %edx,%edx\njne 1198 \nmov %r9d,%eax\ncltd\nidiv %esi\nmov %eax,%r9d\nlea 0xe4d(%rip),%rcx\nmov $0x32,%edx\nmov $0x1,%esi\nlea 0x2e6c(%rip),%rdi\nmov $0x0,%eax\ncallq 1070 <__sprintf_chk@plt>\nlea 0x2e5b(%rip),%rax\npop %rbx\nretq\nmov %r11d,%r9d\njmp 11b3 \nlea 0xe11(%rip),%rax\njmp 11e5 \nretq\n", + "ida_asm": "func0:\nendbr64\nlea rax, aNoSolution; \"No solution\"\ntest edx, edx\njs locret_121C\nmov r10d, edi\nmov edi, esi\nmov r11d, edx\nmov eax, edx\ncdq\nidiv esi\nmov r8d, edx\ntest edx, edx\njz short loc_120F\nmov esi, r11d\nsub esi, r10d\nmov ecx, r10d\nmov r8d, 0\nloc_11BF:\nadd r8d, 1\ncmp r11d, ecx\njl short loc_1214\nmov r9d, esi\nadd ecx, r10d\nsub esi, r10d\nmov eax, r9d\ncdq\nidiv edi\ntest edx, edx\njnz short loc_11BF\nloc_11DB:\npush rbx\nmov eax, r9d\ncdq\nidiv edi\nmov r9d, eax\nlea rcx, aXDYD; \"x = %d, y = %d\"\nmov edx, 32h ; '2'\nmov esi, 2\nlea rbx, result_1\nmov rdi, rbx\nmov eax, 0\ncall ___sprintf_chk\nmov rax, rbx\npop rbx\nretn\nloc_120F:\nmov r9d, r11d\njmp short loc_11DB\nloc_1214:\nlea rax, aNoSolution; \"No solution\"\nretn\nlocret_121C:\nretn", + "ida_pseudo": "const char *__fastcall func0(int a1, int a2, int a3)\n{\n const char *result; // rax\n int v6; // r8d\n int v7; // esi\n int v8; // ecx\n int v9; // r9d\n\n result = \"No solution\";\n if ( a3 >= 0 )\n {\n v6 = a3 % a2;\n if ( a3 % a2 )\n {\n v7 = a3 - a1;\n v8 = a1;\n v6 = 0;\n while ( 1 )\n {\n ++v6;\n if ( a3 < v8 )\n return \"No solution\";\n v9 = v7;\n v8 += a1;\n v7 -= a1;\n if ( !(v9 % a2) )\n goto LABEL_6;\n }\n }\n else\n {\n v9 = a3;\nLABEL_6:\n __sprintf_chk(&result_1, 2LL, 50LL, \"x = %d, y = %d\", v6, v9 / a2);\n return (const char *)&result_1;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\nlea rax, aNoSolution; \"No solution\"\ntest edx, edx\njs locret_121C\nmov r10d, edi\nmov edi, esi\nmov r11d, edx\nmov eax, edx\ncdq\nidiv esi\nmov r8d, edx\ntest edx, edx\njz short loc_120F\nmov esi, r11d\nsub esi, r10d\nmov ecx, r10d\nmov r8d, 0\nloc_11BF:\nadd r8d, 1\ncmp r11d, ecx\njl short loc_1214\nmov r9d, esi\nadd ecx, r10d\nsub esi, r10d\nmov eax, r9d\ncdq\nidiv edi\ntest edx, edx\njnz short loc_11BF\nloc_11DB:\npush rbx\nmov eax, r9d\ncdq\nidiv edi\nmov r9d, eax\nlea rcx, aXDYD; \"x = %d, y = %d\"\nmov edx, 32h ; '2'\nmov esi, 2\nlea rbx, unk_4040\nmov rdi, rbx\nmov eax, 0\ncall ___sprintf_chk\nmov rax, rbx\npop rbx\nretn\nloc_120F:\nmov r9d, r11d\njmp short loc_11DB\nloc_1214:\nlea rax, aNoSolution; \"No solution\"\nretn\nlocret_121C:\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1189(int a1, int a2, int a3)\n{\n const char *result; // rax\n int v6; // r8d\n int v7; // esi\n int v8; // ecx\n int v9; // r9d\n\n result = \"No solution\";\n if ( a3 >= 0 )\n {\n v6 = a3 % a2;\n if ( a3 % a2 )\n {\n v7 = a3 - a1;\n v8 = a1;\n v6 = 0;\n while ( 1 )\n {\n ++v6;\n if ( a3 < v8 )\n return \"No solution\";\n v9 = v7;\n v8 += a1;\n v7 -= a1;\n if ( !(v9 % a2) )\n goto LABEL_6;\n }\n }\n else\n {\n v9 = a3;\nLABEL_6:\n __sprintf_chk(&unk_4040, 2LL, 50LL, \"x = %d, y = %d\", v6, v9 / a2);\n return (const char *)&unk_4040;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1189(int a1, int a2, int a3) {\n const char *result;\n int v6;\n int v7;\n int v8;\n int v9;\n result = \"No solution\";\n if (a3 >= 0) {\n v6 = a3 % a2;\n if (a3 % a2) {\n v7 = a3 - a1;\n v8 = a1;\n v6 = 0;\n while (1) {\n ++v6;\n if (a3 < v8) return \"No solution\";\n v9 = v7;\n v8 += a1;\n v7 -= a1;\n if (!(v9 % a2)) goto LABEL_6;\n }\n } else {\n v9 = a3;\n LABEL_6:\n __sprintf_chk(&unk_4040, 2LL, 50LL, \"x = %d, y = %d\", v6, v9 / a2);\n return (const char *)&unk_4040;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(int a1, int a2, int a3) {\n const char *result;\n int v6;\n int v7;\n int v8;\n int v9;\n result = \"No solution\";\n if (a3 >= 0) {\n v6 = a3 % a2;\n if (a3 % a2) {\n v7 = a3 - a1;\n v8 = a1;\n v6 = 0;\n while (1) {\n ++v6;\n if (a3 < v8) return \"No solution\";\n v9 = v7;\n v8 += a1;\n v7 -= a1;\n if (!(v9 % a2)) goto LABEL_6;\n }\n } else {\n v9 = a3;\n LABEL_6:\n __sprintf_chk(&result_1, 2LL, 50LL, \"x = %d, y = %d\", v6, v9 / a2);\n return (const char *)&result_1;\n }\n }\n return result;\n}" + }, + { + "index": 160, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(int a, int b, int n) {\n int i = 0;\n static char result[50];\n while (i * a <= n) {\n if ((n - (i * a)) % b == 0) {\n sprintf(result, \"x = %d, y = %d\", i, (n - (i * a)) / b);\n return result;\n }\n i++;\n }\n return \"No solution\";\n}", + "test": "int main() {\n\n assert(strcmp(func0(2, 3, 7), \"x = 2, y = 1\") == 0);\n\n assert(strcmp(func0(4, 2, 7), \"No solution\") == 0);\n\n assert(strcmp(func0(1, 13, 17), \"x = 4, y = 1\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nlea 0xd89(%rip),%rax\ntest %edx,%edx\njs 12fe \nmov %edx,%eax\nmov %edx,%r11d\ncltd\nidiv %esi\nmov %edx,%r8d\ntest %edx,%edx\nje 12c3 \nmov %r11d,%r10d\nmov %edi,%ecx\nxor %r8d,%r8d\nsub %edi,%r10d\njmp 12b2 \nnopl 0x0(%rax,%rax,1)\nmov %r10d,%r9d\nadd %edi,%ecx\nsub %edi,%r10d\nmov %r9d,%eax\ncltd\nidiv %esi\ntest %edx,%edx\nje 12c6 \nadd $0x1,%r8d\ncmp %ecx,%r11d\njge 12a0 \nlea 0xd42(%rip),%rax\nretq\nmov %r11d,%r9d\nmov %r9d,%eax\nsub $0x8,%rsp\nlea 0xd3c(%rip),%rcx\ncltd\nlea 0x2d64(%rip),%rdi\nidiv %esi\nmov $0x32,%edx\nmov $0x1,%esi\nmov %eax,%r9d\nxor %eax,%eax\ncallq 1070 <__sprintf_chk@plt>\nlea 0x2d47(%rip),%rax\nadd $0x8,%rsp\nretq\nretq\n", + "ida_asm": "func0:\nendbr64\nlea rax, aNoSolution; \"No solution\"\ntest edx, edx\njs short locret_1308\nmov eax, edx\nmov r11d, edx\ncdq\nidiv esi\nmov r8d, edx\ntest edx, edx\njz short loc_12D4\nmov r10d, edi\nmov edi, r11d\nxor r8d, r8d\nsub edi, r10d\nmov ecx, r10d\njmp short loc_12C3\nloc_12B0:\nmov r9d, edi\nadd ecx, r10d\nsub edi, r10d\nmov eax, r9d\ncdq\nidiv esi\ntest edx, edx\njz short loc_12D7\nloc_12C3:\nadd r8d, 1\ncmp r11d, ecx\njge short loc_12B0\nlea rax, aNoSolution; \"No solution\"\nretn\nloc_12D4:\nmov r9d, r11d\nloc_12D7:\nmov eax, r9d\npush rbx\nlea rbx, result_1\nlea rcx, aXDYD; \"x = %d, y = %d\"\ncdq\nmov rdi, rbx\nidiv esi\nmov edx, 32h ; '2'\nmov esi, 2\nmov r9d, eax\nxor eax, eax\ncall ___sprintf_chk\nmov rax, rbx\npop rbx\nretn\nlocret_1308:\nretn", + "ida_pseudo": "const char *__fastcall func0(int a1, int a2, int a3)\n{\n const char *result; // rax\n int v4; // r8d\n int v6; // edi\n int v7; // ecx\n int v8; // r9d\n\n result = \"No solution\";\n if ( a3 >= 0 )\n {\n v4 = a3 % a2;\n if ( a3 % a2 )\n {\n v4 = 0;\n v6 = a3 - a1;\n v7 = a1;\n while ( 1 )\n {\n ++v4;\n if ( a3 < v7 )\n return \"No solution\";\n v8 = v6;\n v7 += a1;\n v6 -= a1;\n if ( !(v8 % a2) )\n goto LABEL_8;\n }\n }\n else\n {\n v8 = a3;\nLABEL_8:\n __sprintf_chk(&result_1, 2LL, 50LL, \"x = %d, y = %d\", v4, v8 / a2);\n return (const char *)&result_1;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\nlea rax, aNoSolution; \"No solution\"\ntest edx, edx\njs short locret_1308\nmov eax, edx\nmov r11d, edx\ncdq\nidiv esi\nmov r8d, edx\ntest edx, edx\njz short loc_12D4\nmov r10d, edi\nmov edi, r11d\nxor r8d, r8d\nsub edi, r10d\nmov ecx, r10d\njmp short loc_12C3\nloc_12B0:\nmov r9d, edi\nadd ecx, r10d\nsub edi, r10d\nmov eax, r9d\ncdq\nidiv esi\ntest edx, edx\njz short loc_12D7\nloc_12C3:\nadd r8d, 1\ncmp r11d, ecx\njge short loc_12B0\nlea rax, aNoSolution; \"No solution\"\nretn\nloc_12D4:\nmov r9d, r11d\nloc_12D7:\nmov eax, r9d\npush rbx\nlea rbx, unk_4040\nlea rcx, aXDYD; \"x = %d, y = %d\"\ncdq\nmov rdi, rbx\nidiv esi\nmov edx, 32h ; '2'\nmov esi, 2\nmov r9d, eax\nxor eax, eax\ncall ___sprintf_chk\nmov rax, rbx\npop rbx\nretn\nlocret_1308:\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1280(int a1, int a2, int a3)\n{\n const char *result; // rax\n int v4; // r8d\n int v6; // edi\n int v7; // ecx\n int v8; // r9d\n\n result = \"No solution\";\n if ( a3 >= 0 )\n {\n v4 = a3 % a2;\n if ( a3 % a2 )\n {\n v4 = 0;\n v6 = a3 - a1;\n v7 = a1;\n while ( 1 )\n {\n ++v4;\n if ( a3 < v7 )\n return \"No solution\";\n v8 = v6;\n v7 += a1;\n v6 -= a1;\n if ( !(v8 % a2) )\n goto LABEL_8;\n }\n }\n else\n {\n v8 = a3;\nLABEL_8:\n __sprintf_chk(&unk_4040, 2LL, 50LL, \"x = %d, y = %d\", v4, v8 / a2);\n return (const char *)&unk_4040;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1280(int a1, int a2, int a3) {\n const char *result;\n int v4;\n int v6;\n int v7;\n int v8;\n result = \"No solution\";\n if (a3 >= 0) {\n v4 = a3 % a2;\n if (a3 % a2) {\n v4 = 0;\n v6 = a3 - a1;\n v7 = a1;\n while (1) {\n ++v4;\n if (a3 < v7) return \"No solution\";\n v8 = v6;\n v7 += a1;\n v6 -= a1;\n if (!(v8 % a2)) goto LABEL_8;\n }\n } else {\n v8 = a3;\n LABEL_8:\n __sprintf_chk(&unk_4040, 2LL, 50LL, \"x = %d, y = %d\", v4, v8 / a2);\n return (const char *)&unk_4040;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(int a1, int a2, int a3) {\n const char *result;\n int v4;\n int v6;\n int v7;\n int v8;\n result = \"No solution\";\n if (a3 >= 0) {\n v4 = a3 % a2;\n if (a3 % a2) {\n v4 = 0;\n v6 = a3 - a1;\n v7 = a1;\n while (1) {\n ++v4;\n if (a3 < v7) return \"No solution\";\n v8 = v6;\n v7 += a1;\n v6 -= a1;\n if (!(v8 % a2)) goto LABEL_8;\n }\n } else {\n v8 = a3;\n LABEL_8:\n __sprintf_chk(&result_1, 2LL, 50LL, \"x = %d, y = %d\", v4, v8 / a2);\n return (const char *)&result_1;\n }\n }\n return result;\n}" + }, + { + "index": 160, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(int a, int b, int n) {\n int i = 0;\n static char result[50];\n while (i * a <= n) {\n if ((n - (i * a)) % b == 0) {\n sprintf(result, \"x = %d, y = %d\", i, (n - (i * a)) / b);\n return result;\n }\n i++;\n }\n return \"No solution\";\n}", + "test": "int main() {\n\n assert(strcmp(func0(2, 3, 7), \"x = 2, y = 1\") == 0);\n\n assert(strcmp(func0(4, 2, 7), \"No solution\") == 0);\n\n assert(strcmp(func0(1, 13, 17), \"x = 4, y = 1\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nlea 0xd89(%rip),%rax\ntest %edx,%edx\njs 12fe \nmov %edx,%eax\nmov %edx,%r11d\ncltd\nidiv %esi\nmov %edx,%r8d\ntest %edx,%edx\nje 12c3 \nmov %r11d,%r10d\nmov %edi,%ecx\nxor %r8d,%r8d\nsub %edi,%r10d\njmp 12b2 \nnopl 0x0(%rax,%rax,1)\nmov %r10d,%r9d\nadd %edi,%ecx\nsub %edi,%r10d\nmov %r9d,%eax\ncltd\nidiv %esi\ntest %edx,%edx\nje 12c6 \nadd $0x1,%r8d\ncmp %ecx,%r11d\njge 12a0 \nlea 0xd42(%rip),%rax\nretq\nmov %r11d,%r9d\nmov %r9d,%eax\nsub $0x8,%rsp\nlea 0xd3c(%rip),%rcx\ncltd\nlea 0x2d64(%rip),%rdi\nidiv %esi\nmov $0x32,%edx\nmov $0x1,%esi\nmov %eax,%r9d\nxor %eax,%eax\ncallq 1070 <__sprintf_chk@plt>\nlea 0x2d47(%rip),%rax\nadd $0x8,%rsp\nretq\nretq\n", + "ida_asm": "func0:\nendbr64\nlea rax, aNoSolution; \"No solution\"\ntest edx, edx\njs short locret_1308\nmov eax, edx\nmov r11d, edx\ncdq\nidiv esi\nmov r8d, edx\ntest edx, edx\njz short loc_12D4\nmov r10d, edi\nmov edi, r11d\nxor r8d, r8d\nsub edi, r10d\nmov ecx, r10d\njmp short loc_12C3\nloc_12B0:\nmov r9d, edi\nadd ecx, r10d\nsub edi, r10d\nmov eax, r9d\ncdq\nidiv esi\ntest edx, edx\njz short loc_12D7\nloc_12C3:\nadd r8d, 1\ncmp r11d, ecx\njge short loc_12B0\nlea rax, aNoSolution; \"No solution\"\nretn\nloc_12D4:\nmov r9d, r11d\nloc_12D7:\nmov eax, r9d\npush rbx\nlea rbx, result_1\nlea rcx, aXDYD; \"x = %d, y = %d\"\ncdq\nmov rdi, rbx\nidiv esi\nmov edx, 32h ; '2'\nmov esi, 2\nmov r9d, eax\nxor eax, eax\ncall ___sprintf_chk\nmov rax, rbx\npop rbx\nretn\nlocret_1308:\nretn", + "ida_pseudo": "const char *__fastcall func0(int a1, int a2, int a3)\n{\n const char *result; // rax\n int v4; // r8d\n int v6; // edi\n int v7; // ecx\n int v8; // r9d\n\n result = \"No solution\";\n if ( a3 >= 0 )\n {\n v4 = a3 % a2;\n if ( a3 % a2 )\n {\n v4 = 0;\n v6 = a3 - a1;\n v7 = a1;\n while ( 1 )\n {\n ++v4;\n if ( a3 < v7 )\n return \"No solution\";\n v8 = v6;\n v7 += a1;\n v6 -= a1;\n if ( !(v8 % a2) )\n goto LABEL_8;\n }\n }\n else\n {\n v8 = a3;\nLABEL_8:\n __sprintf_chk(&result_1, 2LL, 50LL, \"x = %d, y = %d\", v4, v8 / a2);\n return (const char *)&result_1;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\nlea rax, aNoSolution; \"No solution\"\ntest edx, edx\njs short locret_1308\nmov eax, edx\nmov r11d, edx\ncdq\nidiv esi\nmov r8d, edx\ntest edx, edx\njz short loc_12D4\nmov r10d, edi\nmov edi, r11d\nxor r8d, r8d\nsub edi, r10d\nmov ecx, r10d\njmp short loc_12C3\nloc_12B0:\nmov r9d, edi\nadd ecx, r10d\nsub edi, r10d\nmov eax, r9d\ncdq\nidiv esi\ntest edx, edx\njz short loc_12D7\nloc_12C3:\nadd r8d, 1\ncmp r11d, ecx\njge short loc_12B0\nlea rax, aNoSolution; \"No solution\"\nretn\nloc_12D4:\nmov r9d, r11d\nloc_12D7:\nmov eax, r9d\npush rbx\nlea rbx, unk_4040\nlea rcx, aXDYD; \"x = %d, y = %d\"\ncdq\nmov rdi, rbx\nidiv esi\nmov edx, 32h ; '2'\nmov esi, 2\nmov r9d, eax\nxor eax, eax\ncall ___sprintf_chk\nmov rax, rbx\npop rbx\nretn\nlocret_1308:\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1280(int a1, int a2, int a3)\n{\n const char *result; // rax\n int v4; // r8d\n int v6; // edi\n int v7; // ecx\n int v8; // r9d\n\n result = \"No solution\";\n if ( a3 >= 0 )\n {\n v4 = a3 % a2;\n if ( a3 % a2 )\n {\n v4 = 0;\n v6 = a3 - a1;\n v7 = a1;\n while ( 1 )\n {\n ++v4;\n if ( a3 < v7 )\n return \"No solution\";\n v8 = v6;\n v7 += a1;\n v6 -= a1;\n if ( !(v8 % a2) )\n goto LABEL_8;\n }\n }\n else\n {\n v8 = a3;\nLABEL_8:\n __sprintf_chk(&unk_4040, 2LL, 50LL, \"x = %d, y = %d\", v4, v8 / a2);\n return (const char *)&unk_4040;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1280(int a1, int a2, int a3) {\n const char *result;\n int v4;\n int v6;\n int v7;\n int v8;\n result = \"No solution\";\n if (a3 >= 0) {\n v4 = a3 % a2;\n if (a3 % a2) {\n v4 = 0;\n v6 = a3 - a1;\n v7 = a1;\n while (1) {\n ++v4;\n if (a3 < v7) return \"No solution\";\n v8 = v6;\n v7 += a1;\n v6 -= a1;\n if (!(v8 % a2)) goto LABEL_8;\n }\n } else {\n v8 = a3;\n LABEL_8:\n __sprintf_chk(&unk_4040, 2LL, 50LL, \"x = %d, y = %d\", v4, v8 / a2);\n return (const char *)&unk_4040;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(int a1, int a2, int a3) {\n const char *result;\n int v4;\n int v6;\n int v7;\n int v8;\n result = \"No solution\";\n if (a3 >= 0) {\n v4 = a3 % a2;\n if (a3 % a2) {\n v4 = 0;\n v6 = a3 - a1;\n v7 = a1;\n while (1) {\n ++v4;\n if (a3 < v7) return \"No solution\";\n v8 = v6;\n v7 += a1;\n v6 -= a1;\n if (!(v8 % a2)) goto LABEL_8;\n }\n } else {\n v8 = a3;\n LABEL_8:\n __sprintf_chk(&result_1, 2LL, 50LL, \"x = %d, y = %d\", v4, v8 / a2);\n return (const char *)&result_1;\n }\n }\n return result;\n}" + }, + { + "index": 161, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(const int* list1, int list1_size, const int* list2, int list2_size,\n int* result_size) {\n static int result[1000];\n int index = 0;\n for (int i = 0; i < list1_size; i++) {\n bool found = false;\n for (int j = 0; j < list2_size; j++) {\n if (list1[i] == list2[j]) {\n found = true;\n break;\n }\n }\n if (!found) {\n result[index++] = list1[i];\n }\n }\n *result_size = index;\n return result;\n}", + "test": "int main() {\n\n int result_size;\n\n const int list1[] = {1,2,3,4,5,6,7,8,9,10};\n\n const int list2[] = {2,4,6,8};\n\n const int list3[] = {1, 3, 5, 7};\n\n const int list4[] = {5, 7};\n\n int expected1[] = {1, 3, 5, 7, 9, 10};\n\n int expected2[] = {2, 4, 6, 8, 9, 10};\n\n int expected3[] = {1, 2, 3, 4, 6, 8, 9, 10};\n\n\n\n int* result;\n\n\n\n result = func0(list1, 10, list2, 4, &result_size);\n\n assert(result_size == 6);\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected1[i]);\n\n }\n\n\n\n result = func0(list1, 10, list3, 4, &result_size);\n\n assert(result_size == 6);\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected2[i]);\n\n }\n\n\n\n result = func0(list1, 10, list4, 2, &result_size);\n\n assert(result_size == 8);\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %ecx,-0x20(%rbp)\nmov %r8,-0x30(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\njmpq 1228 \nmovb $0x0,-0xd(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11dd \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 11d9 \nmovb $0x1,-0xd(%rbp)\njmp 11e5 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x20(%rbp),%eax\njl 11a3 \nmovzbl -0xd(%rbp),%eax\nxor $0x1,%eax\ntest %al,%al\nje 1224 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0xc(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0xc(%rbp)\nmov (%rcx),%edx\ncltq\nlea 0x0(,%rax,4),%rcx\nlea 0x2e1f(%rip),%rax\nmov %edx,(%rcx,%rax,1)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1196 \nmov -0x30(%rbp),%rax\nmov -0xc(%rbp),%edx\nmov %edx,(%rax)\nlea 0x2dfc(%rip),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov [rbp+var_30], r8\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp loc_1228\nloc_1196:\nmov [rbp+var_D], 0\nmov [rbp+var_4], 0\njmp short loc_11DD\nloc_11A3:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11D9\nmov [rbp+var_D], 1\njmp short loc_11E5\nloc_11D9:\nadd [rbp+var_4], 1\nloc_11DD:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_20]\njl short loc_11A3\nloc_11E5:\nmovzx eax, [rbp+var_D]\nxor eax, 1\ntest al, al\njz short loc_1224\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\nmov edx, [rcx]\ncdqe\nlea rcx, ds:0[rax*4]\nlea rax, result_1\nmov [rcx+rax], edx\nloc_1224:\nadd [rbp+var_8], 1\nloc_1228:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl loc_1196\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_C]\nmov [rax], edx\nlea rax, result_1\npop rbp\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, __int64 a3, int a4, _DWORD *a5)\n{\n int v5; // eax\n char v7; // [rsp+23h] [rbp-Dh]\n int v8; // [rsp+24h] [rbp-Ch]\n int i; // [rsp+28h] [rbp-8h]\n int j; // [rsp+2Ch] [rbp-4h]\n\n v8 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v7 = 0;\n for ( j = 0; j < a4; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4LL * j + a3) )\n {\n v7 = 1;\n break;\n }\n }\n if ( v7 != 1 )\n {\n v5 = v8++;\n result_1[v5] = *(_DWORD *)(4LL * i + a1);\n }\n }\n *a5 = v8;\n return result_1;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov [rbp+var_30], r8\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp loc_1228\nloc_1196:\nmov [rbp+var_D], 0\nmov [rbp+var_4], 0\njmp short loc_11DD\nloc_11A3:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11D9\nmov [rbp+var_D], 1\njmp short loc_11E5\nloc_11D9:\nadd [rbp+var_4], 1\nloc_11DD:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_20]\njl short loc_11A3\nloc_11E5:\nmovzx eax, [rbp+var_D]\nxor eax, 1\ntest al, al\njz short loc_1224\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\nmov edx, [rcx]\ncdqe\nlea rcx, ds:0[rax*4]\nlea rax, unk_4040\nmov [rcx+rax], edx\nloc_1224:\nadd [rbp+var_8], 1\nloc_1228:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl loc_1196\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_C]\nmov [rax], edx\nlea rax, unk_4040\npop rbp\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1169(__int64 a1, int a2, __int64 a3, int a4, _DWORD *a5)\n{\n int v5; // eax\n char v7; // [rsp+23h] [rbp-Dh]\n int v8; // [rsp+24h] [rbp-Ch]\n int i; // [rsp+28h] [rbp-8h]\n int j; // [rsp+2Ch] [rbp-4h]\n\n v8 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v7 = 0;\n for ( j = 0; j < a4; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4LL * j + a3) )\n {\n v7 = 1;\n break;\n }\n }\n if ( v7 != 1 )\n {\n v5 = v8++;\n dword_4040[v5] = *(_DWORD *)(4LL * i + a1);\n }\n }\n *a5 = v8;\n return dword_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1169(long long a1, int a2, long long a3, int a4, uint32_t *a5) {\n int v5;\n char v7;\n int v8;\n int i;\n int j;\n v8 = 0;\n for (i = 0; i < a2; ++i) {\n v7 = 0;\n for (j = 0; j < a4; ++j) {\n if (*(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4LL * j + a3)) {\n v7 = 1;\n break;\n }\n }\n if (v7 != 1) {\n v5 = v8++;\n dword_4040[v5] = *(uint32_t *)(4LL * i + a1);\n }\n }\n *a5 = v8;\n return dword_4040;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, long long a3, int a4, uint32_t *a5) {\n int v5;\n char v7;\n int v8;\n int i;\n int j;\n v8 = 0;\n for (i = 0; i < a2; ++i) {\n v7 = 0;\n for (j = 0; j < a4; ++j) {\n if (*(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4LL * j + a3)) {\n v7 = 1;\n break;\n }\n }\n if (v7 != 1) {\n v5 = v8++;\n result_1[v5] = *(uint32_t *)(4LL * i + a1);\n }\n }\n *a5 = v8;\n return result_1;\n}" + }, + { + "index": 161, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(const int* list1, int list1_size, const int* list2, int list2_size,\n int* result_size) {\n static int result[1000];\n int index = 0;\n for (int i = 0; i < list1_size; i++) {\n bool found = false;\n for (int j = 0; j < list2_size; j++) {\n if (list1[i] == list2[j]) {\n found = true;\n break;\n }\n }\n if (!found) {\n result[index++] = list1[i];\n }\n }\n *result_size = index;\n return result;\n}", + "test": "int main() {\n\n int result_size;\n\n const int list1[] = {1,2,3,4,5,6,7,8,9,10};\n\n const int list2[] = {2,4,6,8};\n\n const int list3[] = {1, 3, 5, 7};\n\n const int list4[] = {5, 7};\n\n int expected1[] = {1, 3, 5, 7, 9, 10};\n\n int expected2[] = {2, 4, 6, 8, 9, 10};\n\n int expected3[] = {1, 2, 3, 4, 6, 8, 9, 10};\n\n\n\n int* result;\n\n\n\n result = func0(list1, 10, list2, 4, &result_size);\n\n assert(result_size == 6);\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected1[i]);\n\n }\n\n\n\n result = func0(list1, 10, list3, 4, &result_size);\n\n assert(result_size == 6);\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected2[i]);\n\n }\n\n\n\n result = func0(list1, 10, list4, 2, &result_size);\n\n assert(result_size == 8);\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %r8,%rbx\ntest %esi,%esi\njle 1199 \nmov %rdi,%r9\nlea -0x1(%rsi),%eax\nlea 0x4(%rdi,%rax,4),%r10\nmov %rdx,%r11\nlea -0x1(%rcx),%eax\nlea 0x4(%rdx,%rax,4),%rsi\nmov $0x0,%edi\nlea 0x2ea9(%rip),%r8\njmp 11bf \nmov $0x0,%edi\nmov %edi,(%rbx)\nlea 0x2e99(%rip),%rax\npop %rbx\nretq\nmov (%r9),%edx\nmovslq %edi,%rax\nmov %edx,(%r8,%rax,4)\nlea 0x1(%rdi),%edi\nadd $0x4,%r9\ncmp %r10,%r9\nje 119e \ntest %ecx,%ecx\njle 11a9 \nmov (%r9),%edx\nmov %r11,%rax\ncmp (%rax),%edx\nje 11b6 \nadd $0x4,%rax\ncmp %rsi,%rax\njne 11c9 \njmp 11a9 \n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, r8\ntest esi, esi\njle short loc_11CA\nmov r11, rdx\nmov r10d, ecx\nmov r9, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*4]\nmovsxd rax, ecx\nlea rcx, [rdx+rax*4]\nmov esi, 0\nlea r8, result_1\njmp short loc_11B0\nloc_119A:\nmov edx, [r9]\nmovsxd rax, esi\nmov [r8+rax*4], edx\nlea esi, [rsi+1]\nloc_11A7:\nadd r9, 4\ncmp r9, rdi\njz short loc_11CF\nloc_11B0:\ntest r10d, r10d\njle short loc_119A\nmov edx, [r9]\nmov rax, r11\nloc_11BB:\ncmp edx, [rax]\njz short loc_11A7\nadd rax, 4\ncmp rax, rcx\njnz short loc_11BB\njmp short loc_119A\nloc_11CA:\nmov esi, 0\nloc_11CF:\nmov [rbx], esi\nlea rax, result_1\npop rbx\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(_DWORD *a1, int a2, _DWORD *a3, int a4, _DWORD *a5)\n{\n _DWORD *v6; // r9\n _DWORD *v7; // rdi\n _DWORD *v8; // rcx\n int v9; // esi\n _DWORD *v10; // rax\n\n if ( a2 <= 0 )\n {\n v9 = 0;\n }\n else\n {\n v6 = a1;\n v7 = &a1[a2];\n v8 = &a3[a4];\n v9 = 0;\n do\n {\n if ( a4 <= 0 )\n {\nLABEL_3:\n result_1[v9++] = *v6;\n }\n else\n {\n v10 = a3;\n while ( *v6 != *v10 )\n {\n if ( ++v10 == v8 )\n goto LABEL_3;\n }\n }\n ++v6;\n }\n while ( v6 != v7 );\n }\n *a5 = v9;\n return result_1;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbx\nmov rbx, r8\ntest esi, esi\njle short loc_11CA\nmov r11, rdx\nmov r10d, ecx\nmov r9, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*4]\nmovsxd rax, ecx\nlea rcx, [rdx+rax*4]\nmov esi, 0\nlea r8, unk_4040\njmp short loc_11B0\nloc_119A:\nmov edx, [r9]\nmovsxd rax, esi\nmov [r8+rax*4], edx\nlea esi, [rsi+1]\nloc_11A7:\nadd r9, 4\ncmp r9, rdi\njz short loc_11CF\nloc_11B0:\ntest r10d, r10d\njle short loc_119A\nmov edx, [r9]\nmov rax, r11\nloc_11BB:\ncmp edx, [rax]\njz short loc_11A7\nadd rax, 4\ncmp rax, rcx\njnz short loc_11BB\njmp short loc_119A\nloc_11CA:\nmov esi, 0\nloc_11CF:\nmov [rbx], esi\nlea rax, unk_4040\npop rbx\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1169(_DWORD *a1, int a2, _DWORD *a3, int a4, _DWORD *a5)\n{\n _DWORD *v6; // r9\n _DWORD *v7; // rdi\n _DWORD *v8; // rcx\n int v9; // esi\n _DWORD *v10; // rax\n\n if ( a2 <= 0 )\n {\n v9 = 0;\n }\n else\n {\n v6 = a1;\n v7 = &a1[a2];\n v8 = &a3[a4];\n v9 = 0;\n do\n {\n if ( a4 <= 0 )\n {\nLABEL_3:\n dword_4040[v9++] = *v6;\n }\n else\n {\n v10 = a3;\n while ( *v6 != *v10 )\n {\n if ( ++v10 == v8 )\n goto LABEL_3;\n }\n }\n ++v6;\n }\n while ( v6 != v7 );\n }\n *a5 = v9;\n return dword_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1169(uint32_t *a1, int a2, uint32_t *a3, int a4, uint32_t *a5) {\n uint32_t *v6;\n uint32_t *v7;\n uint32_t *v8;\n int v9;\n uint32_t *v10;\n if (a2 <= 0) {\n v9 = 0;\n } else {\n v6 = a1;\n v7 = &a1[a2];\n v8 = &a3[a4];\n v9 = 0;\n do {\n if (a4 <= 0) {\n LABEL_3:\n dword_4040[v9++] = *v6;\n } else {\n v10 = a3;\n while (*v6 != *v10) {\n if (++v10 == v8) goto LABEL_3;\n }\n }\n ++v6;\n } while (v6 != v7);\n }\n *a5 = v9;\n return dword_4040;\n}", + "ida_pseudo_norm": "uint32_t *func0(uint32_t *a1, int a2, uint32_t *a3, int a4, uint32_t *a5) {\n uint32_t *v6;\n uint32_t *v7;\n uint32_t *v8;\n int v9;\n uint32_t *v10;\n if (a2 <= 0) {\n v9 = 0;\n } else {\n v6 = a1;\n v7 = &a1[a2];\n v8 = &a3[a4];\n v9 = 0;\n do {\n if (a4 <= 0) {\n LABEL_3:\n result_1[v9++] = *v6;\n } else {\n v10 = a3;\n while (*v6 != *v10) {\n if (++v10 == v8) goto LABEL_3;\n }\n }\n ++v6;\n } while (v6 != v7);\n }\n *a5 = v9;\n return result_1;\n}" + }, + { + "index": 161, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(const int* list1, int list1_size, const int* list2, int list2_size,\n int* result_size) {\n static int result[1000];\n int index = 0;\n for (int i = 0; i < list1_size; i++) {\n bool found = false;\n for (int j = 0; j < list2_size; j++) {\n if (list1[i] == list2[j]) {\n found = true;\n break;\n }\n }\n if (!found) {\n result[index++] = list1[i];\n }\n }\n *result_size = index;\n return result;\n}", + "test": "int main() {\n\n int result_size;\n\n const int list1[] = {1,2,3,4,5,6,7,8,9,10};\n\n const int list2[] = {2,4,6,8};\n\n const int list3[] = {1, 3, 5, 7};\n\n const int list4[] = {5, 7};\n\n int expected1[] = {1, 3, 5, 7, 9, 10};\n\n int expected2[] = {2, 4, 6, 8, 9, 10};\n\n int expected3[] = {1, 2, 3, 4, 6, 8, 9, 10};\n\n\n\n int* result;\n\n\n\n result = func0(list1, 10, list2, 4, &result_size);\n\n assert(result_size == 6);\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected1[i]);\n\n }\n\n\n\n result = func0(list1, 10, list3, 4, &result_size);\n\n assert(result_size == 6);\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected2[i]);\n\n }\n\n\n\n result = func0(list1, 10, list4, 2, &result_size);\n\n assert(result_size == 8);\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %r8,%rbx\ntest %esi,%esi\njle 14be \nlea -0x1(%rsi),%eax\nmov %rdi,%r9\nlea 0x2be7(%rip),%r8\nxor %r10d,%r10d\nlea 0x4(%rdi,%rax,4),%r11\nlea -0x1(%rcx),%eax\nlea 0x4(%rdx,%rax,4),%rdi\nnopl 0x0(%rax)\nmov (%r9),%esi\nmov %rdx,%rax\ntest %ecx,%ecx\njg 1489 \njmp 14a8 \nnopl 0x0(%rax)\nadd $0x4,%rax\ncmp %rdi,%rax\nje 14a8 \ncmp %esi,(%rax)\njne 1480 \nadd $0x4,%r9\ncmp %r11,%r9\njne 1470 \nmov %r10d,(%rbx)\nlea 0x2ba0(%rip),%rax\npop %rbx\nretq\nnopw 0x0(%rax,%rax,1)\nmovslq %r10d,%rax\nadd $0x4,%r9\nadd $0x1,%r10d\nmov %esi,(%r8,%rax,4)\ncmp %r11,%r9\njne 1470 \njmp 1496 \nxor %r10d,%r10d\nlea 0x2b78(%rip),%rax\nmov %r10d,(%rbx)\npop %rbx\nretq\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, r8\ntest esi, esi\njle short loc_145E\nmovsxd rsi, esi\nmovsxd rax, ecx\nmov r11d, ecx\nmov r9, rdx\nlea r10, [rdi+rsi*4]\nlea rcx, [rdx+rax*4]\nxor esi, esi\nlea r8, result_1\nnop dword ptr [rax+00000000h]\nloc_1410:\nmov edx, [rdi]\ntest r11d, r11d\njle short loc_1440\nloc_1417:\nmov rax, r9\njmp short loc_1429\nloc_1420:\nadd rax, 4\ncmp rax, rcx\njz short loc_1440\nloc_1429:\ncmp [rax], edx\njnz short loc_1420\nadd rdi, 4\ncmp rdi, r10\njz short loc_1455\nmov edx, [rdi]\njmp short loc_1417\nloc_1440:\nadd rdi, 4\nmov [r8+rsi*4], edx\nlea eax, [rsi+1]\ncmp rdi, r10\njz short loc_1457\nmovsxd rsi, eax\njmp short loc_1410\nloc_1455:\nmov eax, esi\nloc_1457:\nmov [rbx], eax\nmov rax, r8\npop rbx\nretn\nloc_145E:\nxor eax, eax\nlea r8, result_1\nmov [rbx], eax\nmov rax, r8\npop rbx\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2, _DWORD *a3, int a4, _DWORD *a5)\n{\n int *v7; // r10\n _DWORD *v8; // rcx\n __int64 i; // rsi\n int v10; // edx\n _DWORD *v11; // rax\n int v12; // eax\n\n if ( a2 <= 0 )\n {\n *a5 = 0;\n return result_1;\n }\n else\n {\n v7 = &a1[a2];\n v8 = &a3[a4];\n for ( i = 0LL; ; i = v12 )\n {\n v10 = *a1;\n if ( a4 > 0 )\n break;\nLABEL_9:\n ++a1;\n result_1[i] = v10;\n v12 = i + 1;\n if ( a1 == v7 )\n goto LABEL_12;\n }\n while ( 1 )\n {\n v11 = a3;\n while ( *v11 != v10 )\n {\n if ( ++v11 == v8 )\n goto LABEL_9;\n }\n if ( ++a1 == v7 )\n break;\n v10 = *a1;\n }\n v12 = i;\nLABEL_12:\n *a5 = v12;\n return result_1;\n }\n}", + "ida_strip_asm": "sub_13E0:\nendbr64\npush rbx\nmov rbx, r8\ntest esi, esi\njle short loc_145E\nmovsxd rsi, esi\nmovsxd rax, ecx\nmov r11d, ecx\nmov r9, rdx\nlea r10, [rdi+rsi*4]\nlea rcx, [rdx+rax*4]\nxor esi, esi\nlea r8, unk_4040\nnop dword ptr [rax+00000000h]\nloc_1410:\nmov edx, [rdi]\ntest r11d, r11d\njle short loc_1440\nloc_1417:\nmov rax, r9\njmp short loc_1429\nloc_1420:\nadd rax, 4\ncmp rax, rcx\njz short loc_1440\nloc_1429:\ncmp [rax], edx\njnz short loc_1420\nadd rdi, 4\ncmp rdi, r10\njz short loc_1455\nmov edx, [rdi]\njmp short loc_1417\nloc_1440:\nadd rdi, 4\nmov [r8+rsi*4], edx\nlea eax, [rsi+1]\ncmp rdi, r10\njz short loc_1457\nmovsxd rsi, eax\njmp short loc_1410\nloc_1455:\nmov eax, esi\nloc_1457:\nmov [rbx], eax\nmov rax, r8\npop rbx\nretn\nloc_145E:\nxor eax, eax\nlea r8, unk_4040\nmov [rbx], eax\nmov rax, r8\npop rbx\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_13E0(int *a1, int a2, _DWORD *a3, int a4, _DWORD *a5)\n{\n int *v7; // r10\n _DWORD *v8; // rcx\n __int64 i; // rsi\n int v10; // edx\n _DWORD *v11; // rax\n int v12; // eax\n\n if ( a2 <= 0 )\n {\n *a5 = 0;\n return dword_4040;\n }\n else\n {\n v7 = &a1[a2];\n v8 = &a3[a4];\n for ( i = 0LL; ; i = v12 )\n {\n v10 = *a1;\n if ( a4 > 0 )\n break;\nLABEL_9:\n ++a1;\n dword_4040[i] = v10;\n v12 = i + 1;\n if ( a1 == v7 )\n goto LABEL_12;\n }\n while ( 1 )\n {\n v11 = a3;\n while ( *v11 != v10 )\n {\n if ( ++v11 == v8 )\n goto LABEL_9;\n }\n if ( ++a1 == v7 )\n break;\n v10 = *a1;\n }\n v12 = i;\nLABEL_12:\n *a5 = v12;\n return dword_4040;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_13E0(int *a1, int a2, uint32_t *a3, int a4, uint32_t *a5) {\n int *v7;\n uint32_t *v8;\n long long i;\n int v10;\n uint32_t *v11;\n int v12;\n if (a2 <= 0) {\n *a5 = 0;\n return dword_4040;\n } else {\n v7 = &a1[a2];\n v8 = &a3[a4];\n for (i = 0LL;; i = v12) {\n v10 = *a1;\n if (a4 > 0) break;\n LABEL_9:\n ++a1;\n dword_4040[i] = v10;\n v12 = i + 1;\n if (a1 == v7) goto LABEL_12;\n }\n while (1) {\n v11 = a3;\n while (*v11 != v10) {\n if (++v11 == v8) goto LABEL_9;\n }\n if (++a1 == v7) break;\n v10 = *a1;\n }\n v12 = i;\n LABEL_12:\n *a5 = v12;\n return dword_4040;\n }\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2, uint32_t *a3, int a4, uint32_t *a5) {\n int *v7;\n uint32_t *v8;\n long long i;\n int v10;\n uint32_t *v11;\n int v12;\n if (a2 <= 0) {\n *a5 = 0;\n return result_1;\n } else {\n v7 = &a1[a2];\n v8 = &a3[a4];\n for (i = 0LL;; i = v12) {\n v10 = *a1;\n if (a4 > 0) break;\n LABEL_9:\n ++a1;\n result_1[i] = v10;\n v12 = i + 1;\n if (a1 == v7) goto LABEL_12;\n }\n while (1) {\n v11 = a3;\n while (*v11 != v10) {\n if (++v11 == v8) goto LABEL_9;\n }\n if (++a1 == v7) break;\n v10 = *a1;\n }\n v12 = i;\n LABEL_12:\n *a5 = v12;\n return result_1;\n }\n}" + }, + { + "index": 161, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(const int* list1, int list1_size, const int* list2, int list2_size,\n int* result_size) {\n static int result[1000];\n int index = 0;\n for (int i = 0; i < list1_size; i++) {\n bool found = false;\n for (int j = 0; j < list2_size; j++) {\n if (list1[i] == list2[j]) {\n found = true;\n break;\n }\n }\n if (!found) {\n result[index++] = list1[i];\n }\n }\n *result_size = index;\n return result;\n}", + "test": "int main() {\n\n int result_size;\n\n const int list1[] = {1,2,3,4,5,6,7,8,9,10};\n\n const int list2[] = {2,4,6,8};\n\n const int list3[] = {1, 3, 5, 7};\n\n const int list4[] = {5, 7};\n\n int expected1[] = {1, 3, 5, 7, 9, 10};\n\n int expected2[] = {2, 4, 6, 8, 9, 10};\n\n int expected3[] = {1, 2, 3, 4, 6, 8, 9, 10};\n\n\n\n int* result;\n\n\n\n result = func0(list1, 10, list2, 4, &result_size);\n\n assert(result_size == 6);\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected1[i]);\n\n }\n\n\n\n result = func0(list1, 10, list3, 4, &result_size);\n\n assert(result_size == 6);\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected2[i]);\n\n }\n\n\n\n result = func0(list1, 10, list4, 2, &result_size);\n\n assert(result_size == 8);\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %r8,%rbx\ntest %esi,%esi\njle 14ce \nlea -0x1(%rsi),%eax\nmov %rdi,%r9\nlea 0x2bd7(%rip),%r8\nxor %r10d,%r10d\nlea 0x4(%rdi,%rax,4),%r11\nlea -0x1(%rcx),%eax\nlea 0x4(%rdx,%rax,4),%rdi\nnopl 0x0(%rax)\nmov (%r9),%esi\nmov %rdx,%rax\ntest %ecx,%ecx\njg 1499 \njmp 14b8 \nnopl 0x0(%rax)\nadd $0x4,%rax\ncmp %rax,%rdi\nje 14b8 \ncmp %esi,(%rax)\njne 1490 \nadd $0x4,%r9\ncmp %r9,%r11\njne 1480 \nmov %r10d,(%rbx)\nlea 0x2b90(%rip),%rax\npop %rbx\nretq\nnopw 0x0(%rax,%rax,1)\nmovslq %r10d,%rax\nadd $0x4,%r9\nadd $0x1,%r10d\nmov %esi,(%r8,%rax,4)\ncmp %r9,%r11\njne 1480 \njmp 14a6 \nxor %r10d,%r10d\nlea 0x2b68(%rip),%rax\nmov %r10d,(%rbx)\npop %rbx\nretq\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, r8\ntest esi, esi\njle short loc_144E\nmovsxd rsi, esi\nmovsxd rax, ecx\nmov r11d, ecx\nmov r9, rdx\nlea r10, [rdi+rsi*4]\nlea rcx, [rdx+rax*4]\nxor esi, esi\nlea r8, result_1\nnop dword ptr [rax+00000000h]\nloc_1400:\nmov edx, [rdi]\ntest r11d, r11d\njle short loc_1430\nloc_1407:\nmov rax, r9\njmp short loc_1419\nloc_1410:\nadd rax, 4\ncmp rax, rcx\njz short loc_1430\nloc_1419:\ncmp [rax], edx\njnz short loc_1410\nadd rdi, 4\ncmp rdi, r10\njz short loc_1445\nmov edx, [rdi]\njmp short loc_1407\nloc_1430:\nadd rdi, 4\nmov [r8+rsi*4], edx\nlea eax, [rsi+1]\ncmp rdi, r10\njz short loc_1447\nmovsxd rsi, eax\njmp short loc_1400\nloc_1445:\nmov eax, esi\nloc_1447:\nmov [rbx], eax\nmov rax, r8\npop rbx\nretn\nloc_144E:\nxor eax, eax\nlea r8, result_1\nmov [rbx], eax\nmov rax, r8\npop rbx\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2, _DWORD *a3, int a4, _DWORD *a5)\n{\n int *v7; // r10\n _DWORD *v8; // rcx\n __int64 i; // rsi\n int v10; // edx\n _DWORD *v11; // rax\n int v12; // eax\n\n if ( a2 <= 0 )\n {\n *a5 = 0;\n return result_1;\n }\n else\n {\n v7 = &a1[a2];\n v8 = &a3[a4];\n for ( i = 0LL; ; i = v12 )\n {\n v10 = *a1;\n if ( a4 > 0 )\n break;\nLABEL_9:\n ++a1;\n result_1[i] = v10;\n v12 = i + 1;\n if ( a1 == v7 )\n goto LABEL_12;\n }\n while ( 1 )\n {\n v11 = a3;\n while ( *v11 != v10 )\n {\n if ( ++v11 == v8 )\n goto LABEL_9;\n }\n if ( ++a1 == v7 )\n break;\n v10 = *a1;\n }\n v12 = i;\nLABEL_12:\n *a5 = v12;\n return result_1;\n }\n}", + "ida_strip_asm": "sub_13D0:\nendbr64\npush rbx\nmov rbx, r8\ntest esi, esi\njle short loc_144E\nmovsxd rsi, esi\nmovsxd rax, ecx\nmov r11d, ecx\nmov r9, rdx\nlea r10, [rdi+rsi*4]\nlea rcx, [rdx+rax*4]\nxor esi, esi\nlea r8, unk_4040\nnop dword ptr [rax+00000000h]\nloc_1400:\nmov edx, [rdi]\ntest r11d, r11d\njle short loc_1430\nloc_1407:\nmov rax, r9\njmp short loc_1419\nloc_1410:\nadd rax, 4\ncmp rax, rcx\njz short loc_1430\nloc_1419:\ncmp [rax], edx\njnz short loc_1410\nadd rdi, 4\ncmp rdi, r10\njz short loc_1445\nmov edx, [rdi]\njmp short loc_1407\nloc_1430:\nadd rdi, 4\nmov [r8+rsi*4], edx\nlea eax, [rsi+1]\ncmp rdi, r10\njz short loc_1447\nmovsxd rsi, eax\njmp short loc_1400\nloc_1445:\nmov eax, esi\nloc_1447:\nmov [rbx], eax\nmov rax, r8\npop rbx\nretn\nloc_144E:\nxor eax, eax\nlea r8, unk_4040\nmov [rbx], eax\nmov rax, r8\npop rbx\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_13D0(int *a1, int a2, _DWORD *a3, int a4, _DWORD *a5)\n{\n int *v7; // r10\n _DWORD *v8; // rcx\n __int64 i; // rsi\n int v10; // edx\n _DWORD *v11; // rax\n int v12; // eax\n\n if ( a2 <= 0 )\n {\n *a5 = 0;\n return dword_4040;\n }\n else\n {\n v7 = &a1[a2];\n v8 = &a3[a4];\n for ( i = 0LL; ; i = v12 )\n {\n v10 = *a1;\n if ( a4 > 0 )\n break;\nLABEL_9:\n ++a1;\n dword_4040[i] = v10;\n v12 = i + 1;\n if ( a1 == v7 )\n goto LABEL_12;\n }\n while ( 1 )\n {\n v11 = a3;\n while ( *v11 != v10 )\n {\n if ( ++v11 == v8 )\n goto LABEL_9;\n }\n if ( ++a1 == v7 )\n break;\n v10 = *a1;\n }\n v12 = i;\nLABEL_12:\n *a5 = v12;\n return dword_4040;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_13D0(int *a1, int a2, uint32_t *a3, int a4, uint32_t *a5) {\n int *v7;\n uint32_t *v8;\n long long i;\n int v10;\n uint32_t *v11;\n int v12;\n if (a2 <= 0) {\n *a5 = 0;\n return dword_4040;\n } else {\n v7 = &a1[a2];\n v8 = &a3[a4];\n for (i = 0LL;; i = v12) {\n v10 = *a1;\n if (a4 > 0) break;\n LABEL_9:\n ++a1;\n dword_4040[i] = v10;\n v12 = i + 1;\n if (a1 == v7) goto LABEL_12;\n }\n while (1) {\n v11 = a3;\n while (*v11 != v10) {\n if (++v11 == v8) goto LABEL_9;\n }\n if (++a1 == v7) break;\n v10 = *a1;\n }\n v12 = i;\n LABEL_12:\n *a5 = v12;\n return dword_4040;\n }\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2, uint32_t *a3, int a4, uint32_t *a5) {\n int *v7;\n uint32_t *v8;\n long long i;\n int v10;\n uint32_t *v11;\n int v12;\n if (a2 <= 0) {\n *a5 = 0;\n return result_1;\n } else {\n v7 = &a1[a2];\n v8 = &a3[a4];\n for (i = 0LL;; i = v12) {\n v10 = *a1;\n if (a4 > 0) break;\n LABEL_9:\n ++a1;\n result_1[i] = v10;\n v12 = i + 1;\n if (a1 == v7) goto LABEL_12;\n }\n while (1) {\n v11 = a3;\n while (*v11 != v10) {\n if (++v11 == v8) goto LABEL_9;\n }\n if (++a1 == v7) break;\n v10 = *a1;\n }\n v12 = i;\n LABEL_12:\n *a5 = v12;\n return result_1;\n }\n}" + }, + { + "index": 162, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n < 1) {\n return 0;\n } else {\n return n + func0(n - 2);\n }\n}", + "test": "int main() {\n\n assert(func0(6) == 12);\n\n assert(func0(10) == 30);\n\n assert(func0(9) == 25);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %edi,-0x4(%rbp)\ncmpl $0x0,-0x4(%rbp)\njg 1165 \nmov $0x0,%eax\njmp 1177 \nmov -0x4(%rbp),%eax\nsub $0x2,%eax\nmov %eax,%edi\ncallq 1149 \nmov -0x4(%rbp),%edx\nadd %edx,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+var_4], edi\ncmp [rbp+var_4], 0\njg short loc_1165\nmov eax, 0\njmp short locret_1177\nloc_1165:\nmov eax, [rbp+var_4]\nsub eax, 2\nmov edi, eax\ncall func0\nmov edx, [rbp+var_4]\nadd eax, edx\nlocret_1177:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n if ( a1 > 0 )\n return a1 + (unsigned int)func0((unsigned int)(a1 - 2));\n else\n return 0LL;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+var_4], edi\ncmp [rbp+var_4], 0\njg short loc_1165\nmov eax, 0\njmp short locret_1177\nloc_1165:\nmov eax, [rbp+var_4]\nsub eax, 2\nmov edi, eax\ncall sub_1149\nmov edx, [rbp+var_4]\nadd eax, edx\nlocret_1177:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n if ( a1 > 0 )\n return a1 + (unsigned int)sub_1149((unsigned int)(a1 - 2));\n else\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n if (a1 > 0)\n return a1 + (unsigned int)sub_1149((unsigned int)(a1 - 2));\n else\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n if (a1 > 0)\n return a1 + (unsigned int)func0((unsigned int)(a1 - 2));\n else\n return 0LL;\n}" + }, + { + "index": 162, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n < 1) {\n return 0;\n } else {\n return n + func0(n - 2);\n }\n}", + "test": "int main() {\n\n assert(func0(6) == 12);\n\n assert(func0(10) == 30);\n\n assert(func0(9) == 25);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x0,%eax\ntest %edi,%edi\njg 1157 \nretq\npush %rbx\nmov %edi,%ebx\nlea -0x2(%rdi),%edi\ncallq 1149 \nadd %ebx,%eax\npop %rbx\nretq\n", + "ida_asm": "func0:\nendbr64\nmov eax, 0\ntest edi, edi\njg short loc_1157\nretn\nloc_1157:\npush rbx\nmov ebx, edi\nlea edi, [rdi-2]\ncall func0\nadd eax, ebx\npop rbx\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n __int64 result; // rax\n\n result = 0LL;\n if ( a1 > 0 )\n return a1 + (unsigned int)func0((unsigned int)(a1 - 2));\n return result;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmov eax, 0\ntest edi, edi\njg short loc_1157\nretn\nloc_1157:\npush rbx\nmov ebx, edi\nlea edi, [rdi-2]\ncall sub_1149\nadd eax, ebx\npop rbx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n __int64 result; // rax\n\n result = 0LL;\n if ( a1 > 0 )\n return a1 + (unsigned int)sub_1149((unsigned int)(a1 - 2));\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n long long result;\n result = 0LL;\n if (a1 > 0) return a1 + (unsigned int)sub_1149((unsigned int)(a1 - 2));\n return result;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n long long result;\n result = 0LL;\n if (a1 > 0) return a1 + (unsigned int)func0((unsigned int)(a1 - 2));\n return result;\n}" + }, + { + "index": 163, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int s, double l) {\n double area = s * (l * l) / (4 * tan(M_PI / s));\n return area;\n}", + "test": "int main() {\n\n assert(func0(4, 20) == 400.00000000000006);\n\n assert(func0(10, 15) == 1731.1969896610804);\n\n assert(func0(9, 7) == 302.90938549487214);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %edi,-0x14(%rbp)\nmovsd %xmm0,-0x20(%rbp)\ncvtsi2sdl -0x14(%rbp),%xmm1\nmovsd -0x20(%rbp),%xmm0\nmulsd %xmm0,%xmm0\nmulsd %xmm0,%xmm1\nmovsd %xmm1,-0x28(%rbp)\ncvtsi2sdl -0x14(%rbp),%xmm1\nmovsd 0xf1f(%rip),%xmm0\ndivsd %xmm1,%xmm0\ncallq 1070 \nmovsd 0xf16(%rip),%xmm1\nmulsd %xmm1,%xmm0\nmovsd -0x28(%rbp),%xmm1\ndivsd %xmm0,%xmm1\nmovapd %xmm1,%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmovsd -0x8(%rbp),%xmm0\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_14], edi\nmovsd [rbp+var_20], xmm0\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_14]\nmovsd xmm0, [rbp+var_20]\nmulsd xmm0, xmm0\nmulsd xmm1, xmm0\nmovsd [rbp+var_28], xmm1\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_14]\nmovsd xmm0, cs:qword_20A0\nmovapd xmm2, xmm0\ndivsd xmm2, xmm1\nmovq rax, xmm2\nmovq xmm0, rax; x\ncall _tan\nmovsd xmm1, cs:qword_20A8\nmulsd xmm1, xmm0\nmovsd xmm0, [rbp+var_28]\ndivsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "double __fastcall func0(int a1, double a2)\n{\n return (double)a1 * (a2 * a2) / (4.0 * tan(3.141592653589793 / (double)a1));\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_14], edi\nmovsd [rbp+var_20], xmm0\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_14]\nmovsd xmm0, [rbp+var_20]\nmulsd xmm0, xmm0\nmulsd xmm1, xmm0\nmovsd [rbp+var_28], xmm1\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_14]\nmovsd xmm0, cs:qword_20A0\nmovapd xmm2, xmm0\ndivsd xmm2, xmm1\nmovq rax, xmm2\nmovq xmm0, rax; x\ncall _tan\nmovsd xmm1, cs:qword_20A8\nmulsd xmm1, xmm0\nmovsd xmm0, [rbp+var_28]\ndivsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "double __fastcall sub_1169(int a1, double a2)\n{\n return (double)a1 * (a2 * a2) / (4.0 * tan(3.141592653589793 / (double)a1));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1169(int a1, double a2) {\n return (double)a1 * (a2 * a2) / (4.0 * tan(3.141592653589793 / (double)a1));\n}", + "ida_pseudo_norm": "double func0(int a1, double a2) {\n return (double)a1 * (a2 * a2) / (4.0 * tan(3.141592653589793 / (double)a1));\n}" + }, + { + "index": 163, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int s, double l) {\n double area = s * (l * l) / (4 * tan(M_PI / s));\n return area;\n}", + "test": "int main() {\n\n assert(func0(4, 20) == 400.00000000000006);\n\n assert(func0(10, 15) == 1731.1969896610804);\n\n assert(func0(9, 7) == 302.90938549487214);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x18,%rsp\nmovsd %xmm0,0x8(%rsp)\npxor %xmm2,%xmm2\ncvtsi2sd %edi,%xmm2\nmovsd 0xea1(%rip),%xmm0\nmovsd %xmm2,(%rsp)\ndivsd %xmm2,%xmm0\ncallq 1050 \nmovapd %xmm0,%xmm1\nmovsd 0x8(%rsp),%xmm0\nmulsd %xmm0,%xmm0\nmulsd (%rsp),%xmm0\nmulsd 0xe80(%rip),%xmm1\ndivsd %xmm1,%xmm0\nadd $0x18,%rsp\nretq\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 18h\nmovsd [rsp+18h+var_10], xmm0\npxor xmm2, xmm2\ncvtsi2sd xmm2, edi\nmovsd xmm0, cs:qword_2008\nmovsd [rsp+18h+var_18], xmm2\ndivsd xmm0, xmm2; x\ncall _tan\nmovapd xmm1, xmm0\nmovsd xmm0, [rsp+18h+var_10]\nmulsd xmm0, xmm0\nmulsd xmm0, [rsp+18h+var_18]\nmulsd xmm1, cs:qword_2010\ndivsd xmm0, xmm1\nadd rsp, 18h\nretn", + "ida_pseudo": "double __fastcall func0(int a1, double a2)\n{\n return a2 * a2 * (double)a1 / (tan(3.141592653589793 / (double)a1) * 4.0);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nsub rsp, 18h\nmovsd [rsp+18h+var_10], xmm0\npxor xmm2, xmm2\ncvtsi2sd xmm2, edi\nmovsd xmm0, cs:qword_2008\nmovsd [rsp+18h+var_18], xmm2\ndivsd xmm0, xmm2; x\ncall _tan\nmovapd xmm1, xmm0\nmovsd xmm0, [rsp+18h+var_10]\nmulsd xmm0, xmm0\nmulsd xmm0, [rsp+18h+var_18]\nmulsd xmm1, cs:qword_2010\ndivsd xmm0, xmm1\nadd rsp, 18h\nretn", + "ida_strip_pseudo": "double __fastcall sub_1149(int a1, double a2)\n{\n return a2 * a2 * (double)a1 / (tan(3.141592653589793 / (double)a1) * 4.0);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1149(int a1, double a2) {\n return a2 * a2 * (double)a1 / (tan(3.141592653589793 / (double)a1) * 4.0);\n}", + "ida_pseudo_norm": "double func0(int a1, double a2) {\n return a2 * a2 * (double)a1 / (tan(3.141592653589793 / (double)a1) * 4.0);\n}" + }, + { + "index": 163, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int s, double l) {\n double area = s * (l * l) / (4 * tan(M_PI / s));\n return area;\n}", + "test": "int main() {\n\n assert(func0(4, 20) == 400.00000000000006);\n\n assert(func0(10, 15) == 1731.1969896610804);\n\n assert(func0(9, 7) == 302.90938549487214);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npxor %xmm2,%xmm2\nsub $0x18,%rsp\ncvtsi2sd %edi,%xmm2\nmovsd %xmm0,0x8(%rsp)\nmovsd 0xe8a(%rip),%xmm0\ndivsd %xmm2,%xmm0\nmovsd %xmm2,(%rsp)\ncallq 1050 \nmovsd 0x8(%rsp),%xmm1\nmovsd (%rsp),%xmm2\nmulsd 0xe71(%rip),%xmm0\nadd $0x18,%rsp\nmulsd %xmm1,%xmm1\nmulsd %xmm2,%xmm1\ndivsd %xmm0,%xmm1\nmovapd %xmm1,%xmm0\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npxor xmm2, xmm2\nsub rsp, 18h\ncvtsi2sd xmm2, edi\nmovsd [rsp+18h+var_10], xmm0\nmovsd xmm0, cs:qword_2008\ndivsd xmm0, xmm2; x\nmovsd [rsp+18h+var_18], xmm2\ncall _tan\nmovsd xmm1, [rsp+18h+var_10]\nmovsd xmm2, [rsp+18h+var_18]\nmulsd xmm0, cs:qword_2010\nadd rsp, 18h\nmulsd xmm1, xmm1\nmulsd xmm1, xmm2\ndivsd xmm1, xmm0\nmovapd xmm0, xmm1\nretn", + "ida_pseudo": "__int128 __usercall func0@(int a1@, double a2@)\n{\n __int128 v2; // xmm1\n\n v2 = *(unsigned __int64 *)&a2;\n *(double *)&v2 = *(double *)&v2 * *(double *)&v2 * (double)a1 / (tan(3.141592653589793 / (double)a1) * 4.0);\n return v2;\n}", + "ida_strip_asm": "sub_1160:\nendbr64\npxor xmm2, xmm2\nsub rsp, 18h\ncvtsi2sd xmm2, edi\nmovsd [rsp+18h+var_10], xmm0\nmovsd xmm0, cs:qword_2008\ndivsd xmm0, xmm2; x\nmovsd [rsp+18h+var_18], xmm2\ncall _tan\nmovsd xmm1, [rsp+18h+var_10]\nmovsd xmm2, [rsp+18h+var_18]\nmulsd xmm0, cs:qword_2010\nadd rsp, 18h\nmulsd xmm1, xmm1\nmulsd xmm1, xmm2\ndivsd xmm1, xmm0\nmovapd xmm0, xmm1\nretn", + "ida_strip_pseudo": "__int128 __usercall sub_1160@(int a1@, double a2@)\n{\n __int128 v2; // xmm1\n\n v2 = *(unsigned __int64 *)&a2;\n *(double *)&v2 = *(double *)&v2 * *(double *)&v2 * (double)a1 / (tan(3.141592653589793 / (double)a1) * 4.0);\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__int128 __usercall sub_1160 @(int a1 @, double a2 @) {\n __int128 v2;\n v2 = *(unsigned long long *)&a2;\n *(double *)&v2 = *(double *)&v2 * *(double *)&v2 * (double)a1 /\n (tan(3.141592653589793 / (double)a1) * 4.0);\n return v2;\n}", + "ida_pseudo_norm": "__int128 __usercall func0 @(int a1 @, double a2 @) {\n __int128 v2;\n v2 = *(unsigned long long *)&a2;\n *(double *)&v2 = *(double *)&v2 * *(double *)&v2 * (double)a1 /\n (tan(3.141592653589793 / (double)a1) * 4.0);\n return v2;\n}" + }, + { + "index": 163, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int s, double l) {\n double area = s * (l * l) / (4 * tan(M_PI / s));\n return area;\n}", + "test": "int main() {\n\n assert(func0(4, 20) == 400.00000000000006);\n\n assert(func0(10, 15) == 1731.1969896610804);\n\n assert(func0(9, 7) == 302.90938549487214);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npxor %xmm2,%xmm2\nsub $0x18,%rsp\ncvtsi2sd %edi,%xmm2\nmovsd %xmm0,0x8(%rsp)\nmovsd 0xe8a(%rip),%xmm0\ndivsd %xmm2,%xmm0\nmovsd %xmm2,(%rsp)\ncallq 1050 \nmovsd 0x8(%rsp),%xmm1\nmovsd (%rsp),%xmm2\nmulsd 0xe71(%rip),%xmm0\nadd $0x18,%rsp\nmulsd %xmm1,%xmm1\nmulsd %xmm2,%xmm1\ndivsd %xmm0,%xmm1\nmovapd %xmm1,%xmm0\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npxor xmm2, xmm2\nsub rsp, 18h\ncvtsi2sd xmm2, edi\nmovsd [rsp+18h+var_10], xmm0\nmovsd xmm0, cs:qword_2008\ndivsd xmm0, xmm2; x\nmovsd [rsp+18h+var_18], xmm2\ncall _tan\nmovsd xmm1, [rsp+18h+var_10]\nmovsd xmm2, [rsp+18h+var_18]\nmulsd xmm0, cs:qword_2010\nadd rsp, 18h\nmulsd xmm1, xmm1\nmulsd xmm1, xmm2\ndivsd xmm1, xmm0\nmovapd xmm0, xmm1\nretn", + "ida_pseudo": "__int128 __usercall func0@(int a1@, double a2@)\n{\n __int128 v2; // xmm1\n\n v2 = *(unsigned __int64 *)&a2;\n *(double *)&v2 = *(double *)&v2 * *(double *)&v2 * (double)a1 / (tan(3.141592653589793 / (double)a1) * 4.0);\n return v2;\n}", + "ida_strip_asm": "sub_1160:\nendbr64\npxor xmm2, xmm2\nsub rsp, 18h\ncvtsi2sd xmm2, edi\nmovsd [rsp+18h+var_10], xmm0\nmovsd xmm0, cs:qword_2008\ndivsd xmm0, xmm2; x\nmovsd [rsp+18h+var_18], xmm2\ncall _tan\nmovsd xmm1, [rsp+18h+var_10]\nmovsd xmm2, [rsp+18h+var_18]\nmulsd xmm0, cs:qword_2010\nadd rsp, 18h\nmulsd xmm1, xmm1\nmulsd xmm1, xmm2\ndivsd xmm1, xmm0\nmovapd xmm0, xmm1\nretn", + "ida_strip_pseudo": "__int128 __usercall sub_1160@(int a1@, double a2@)\n{\n __int128 v2; // xmm1\n\n v2 = *(unsigned __int64 *)&a2;\n *(double *)&v2 = *(double *)&v2 * *(double *)&v2 * (double)a1 / (tan(3.141592653589793 / (double)a1) * 4.0);\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__int128 __usercall sub_1160 @(int a1 @, double a2 @) {\n __int128 v2;\n v2 = *(unsigned long long *)&a2;\n *(double *)&v2 = *(double *)&v2 * *(double *)&v2 * (double)a1 /\n (tan(3.141592653589793 / (double)a1) * 4.0);\n return v2;\n}", + "ida_pseudo_norm": "__int128 __usercall func0 @(int a1 @, double a2 @) {\n __int128 v2;\n v2 = *(unsigned long long *)&a2;\n *(double *)&v2 = *(double *)&v2 * *(double *)&v2 * (double)a1 /\n (tan(3.141592653589793 / (double)a1) * 4.0);\n return v2;\n}" + }, + { + "index": 164, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nint divSum(int n) {\n\n int sum = 1;\n\n int i = 2;\n\n while (i * i <= n) {\n\n if (n % i == 0) {\n\n sum += i + (int)floor(n / i);\n\n }\n\n i++;\n\n }\n\n return sum;\n\n}\n\n\n\n", + "func": "int func0(int num1, int num2) { return divSum(num1) == divSum(num2); }", + "test": "int main() {\n\n assert(func0(36, 57) == 0);\n\n assert(func0(2, 4) == 0);\n\n assert(func0(23, 47) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x8,%rsp\nmov %edi,-0xc(%rbp)\nmov %esi,-0x10(%rbp)\nmov -0xc(%rbp),%eax\nmov %eax,%edi\ncallq 1149 \nmov %eax,%ebx\nmov -0x10(%rbp),%eax\nmov %eax,%edi\ncallq 1149 \ncmp %eax,%ebx\nsete %al\nmovzbl %al,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 8\nmov [rbp+var_C], edi\nmov [rbp+var_10], esi\nmov eax, [rbp+var_C]\nmov edi, eax\ncall divSum\nmov ebx, eax\nmov eax, [rbp+var_10]\nmov edi, eax\ncall divSum\ncmp ebx, eax\nsetz al\nmovzx eax, al\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(unsigned int a1, unsigned int a2)\n{\n int v2; // ebx\n\n v2 = divSum(a1);\n return v2 == (unsigned int)divSum(a2);\n}", + "ida_strip_asm": "sub_11A0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 8\nmov [rbp+var_C], edi\nmov [rbp+var_10], esi\nmov eax, [rbp+var_C]\nmov edi, eax\ncall sub_1149\nmov ebx, eax\nmov eax, [rbp+var_10]\nmov edi, eax\ncall sub_1149\ncmp ebx, eax\nsetz al\nmovzx eax, al\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_11A0(unsigned int a1, unsigned int a2)\n{\n int v2; // ebx\n\n v2 = sub_1149(a1);\n return v2 == (unsigned int)sub_1149(a2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_11A0(unsigned int a1, unsigned int a2) {\n int v2;\n v2 = sub_1149(a1);\n return v2 == (unsigned int)sub_1149(a2);\n}", + "ida_pseudo_norm": "uint8_t func0(unsigned int a1, unsigned int a2) {\n int v2;\n v2 = divSum(a1);\n return v2 == (unsigned int)divSum(a2);\n}" + }, + { + "index": 164, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nint divSum(int n) {\n\n int sum = 1;\n\n int i = 2;\n\n while (i * i <= n) {\n\n if (n % i == 0) {\n\n sum += i + (int)floor(n / i);\n\n }\n\n i++;\n\n }\n\n return sum;\n\n}\n\n\n\n", + "func": "int func0(int num1, int num2) { return divSum(num1) == divSum(num2); }", + "test": "int main() {\n\n assert(func0(36, 57) == 0);\n\n assert(func0(2, 4) == 0);\n\n assert(func0(23, 47) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nmov %esi,%ebp\ncallq 1149 \nmov %eax,%ebx\nmov %ebp,%edi\ncallq 1149 \ncmp %eax,%ebx\nsete %al\nmovzbl %al,%eax\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nmov ebp, esi\ncall divSum\nmov ebx, eax\nmov edi, ebp\ncall divSum\ncmp ebx, eax\nsetz al\nmovzx eax, al\npop rbx\npop rbp\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(__int64 a1, unsigned int a2)\n{\n int v2; // ebx\n\n v2 = ((__int64 (*)(void))divSum)();\n return v2 == (unsigned int)divSum(a2);\n}", + "ida_strip_asm": "sub_1186:\nendbr64\npush rbp\npush rbx\nmov ebp, esi\ncall sub_1149\nmov ebx, eax\nmov edi, ebp\ncall sub_1149\ncmp ebx, eax\nsetz al\nmovzx eax, al\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1186(__int64 a1, unsigned int a2)\n{\n int v2; // ebx\n\n v2 = ((__int64 (*)(void))sub_1149)();\n return v2 == (unsigned int)sub_1149(a2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1186(long long a1, unsigned int a2) {\n int v2;\n v2 = ((long long (*)(void))sub_1149)();\n return v2 == (unsigned int)sub_1149(a2);\n}", + "ida_pseudo_norm": "uint8_t func0(long long a1, unsigned int a2) {\n int v2;\n v2 = ((long long (*)(void))divSum)();\n return v2 == (unsigned int)divSum(a2);\n}" + }, + { + "index": 164, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nint divSum(int n) {\n\n int sum = 1;\n\n int i = 2;\n\n while (i * i <= n) {\n\n if (n % i == 0) {\n\n sum += i + (int)floor(n / i);\n\n }\n\n i++;\n\n }\n\n return sum;\n\n}\n\n\n\n", + "func": "int func0(int num1, int num2) { return divSum(num1) == divSum(num2); }", + "test": "int main() {\n\n assert(func0(36, 57) == 0);\n\n assert(func0(2, 4) == 0);\n\n assert(func0(23, 47) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x1,%r8d\ncmp $0x3,%edi\njle 1284 \nmov $0x2,%ecx\nnopl 0x0(%rax)\nmov %edi,%eax\ncltd\nidiv %ecx\nadd %ecx,%eax\nadd %r8d,%eax\ntest %edx,%edx\ncmove %eax,%r8d\nadd $0x1,%ecx\nmov %ecx,%eax\nimul %ecx,%eax\ncmp %eax,%edi\njge 1268 \nmov $0x1,%edi\ncmp $0x3,%esi\njle 12b2 \nmov $0x2,%ecx\nnopl 0x0(%rax,%rax,1)\nmov %esi,%eax\ncltd\nidiv %ecx\nadd %ecx,%eax\nadd %edi,%eax\ntest %edx,%edx\ncmove %eax,%edi\nadd $0x1,%ecx\nmov %ecx,%eax\nimul %ecx,%eax\ncmp %eax,%esi\njge 1298 \nxor %eax,%eax\ncmp %r8d,%edi\nsete %al\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmov r8d, 1\ncmp edi, 3\njle short loc_1274\nmov ecx, 2\nnop dword ptr [rax+00h]\nloc_1258:\nmov eax, edi\ncdq\nidiv ecx\nadd eax, ecx\nadd eax, r8d\ntest edx, edx\ncmovz r8d, eax\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp edi, eax\njge short loc_1258\nloc_1274:\nmov edi, 1\ncmp esi, 3\njle short loc_12A2\nmov ecx, 2\nnop dword ptr [rax+rax+00h]\nloc_1288:\nmov eax, esi\ncdq\nidiv ecx\nadd eax, ecx\nadd eax, edi\ntest edx, edx\ncmovz edi, eax\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp esi, eax\njge short loc_1288\nloc_12A2:\nxor eax, eax\ncmp edi, r8d\nsetz al\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(int a1, int a2)\n{\n int v2; // r8d\n int v3; // ecx\n int v4; // edi\n int v5; // ecx\n\n v2 = 1;\n if ( a1 > 3 )\n {\n v3 = 2;\n do\n {\n if ( !(a1 % v3) )\n v2 += v3 + a1 / v3;\n ++v3;\n }\n while ( a1 >= v3 * v3 );\n }\n v4 = 1;\n if ( a2 > 3 )\n {\n v5 = 2;\n do\n {\n if ( !(a2 % v5) )\n v4 += v5 + a2 / v5;\n ++v5;\n }\n while ( a2 >= v5 * v5 );\n }\n return v4 == v2;\n}", + "ida_strip_asm": "sub_1240:\nendbr64\nmov r8d, 1\ncmp edi, 3\njle short loc_1274\nmov ecx, 2\nnop dword ptr [rax+00h]\nloc_1258:\nmov eax, edi\ncdq\nidiv ecx\nadd eax, ecx\nadd eax, r8d\ntest edx, edx\ncmovz r8d, eax\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp edi, eax\njge short loc_1258\nloc_1274:\nmov edi, 1\ncmp esi, 3\njle short loc_12A2\nmov ecx, 2\nnop dword ptr [rax+rax+00h]\nloc_1288:\nmov eax, esi\ncdq\nidiv ecx\nadd eax, ecx\nadd eax, edi\ntest edx, edx\ncmovz edi, eax\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp esi, eax\njge short loc_1288\nloc_12A2:\nxor eax, eax\ncmp edi, r8d\nsetz al\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1240(int a1, int a2)\n{\n int v2; // r8d\n int v3; // ecx\n int v4; // edi\n int v5; // ecx\n\n v2 = 1;\n if ( a1 > 3 )\n {\n v3 = 2;\n do\n {\n if ( !(a1 % v3) )\n v2 += v3 + a1 / v3;\n ++v3;\n }\n while ( a1 >= v3 * v3 );\n }\n v4 = 1;\n if ( a2 > 3 )\n {\n v5 = 2;\n do\n {\n if ( !(a2 % v5) )\n v4 += v5 + a2 / v5;\n ++v5;\n }\n while ( a2 >= v5 * v5 );\n }\n return v4 == v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1240(int a1, int a2) {\n int v2;\n int v3;\n int v4;\n int v5;\n v2 = 1;\n if (a1 > 3) {\n v3 = 2;\n do {\n if (!(a1 % v3)) v2 += v3 + a1 / v3;\n ++v3;\n } while (a1 >= v3 * v3);\n }\n v4 = 1;\n if (a2 > 3) {\n v5 = 2;\n do {\n if (!(a2 % v5)) v4 += v5 + a2 / v5;\n ++v5;\n } while (a2 >= v5 * v5);\n }\n return v4 == v2;\n}", + "ida_pseudo_norm": "uint8_t func0(int a1, int a2) {\n int v2;\n int v3;\n int v4;\n int v5;\n v2 = 1;\n if (a1 > 3) {\n v3 = 2;\n do {\n if (!(a1 % v3)) v2 += v3 + a1 / v3;\n ++v3;\n } while (a1 >= v3 * v3);\n }\n v4 = 1;\n if (a2 > 3) {\n v5 = 2;\n do {\n if (!(a2 % v5)) v4 += v5 + a2 / v5;\n ++v5;\n } while (a2 >= v5 * v5);\n }\n return v4 == v2;\n}" + }, + { + "index": 165, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *str1) {\n int count_chars = 0;\n int length = strlen(str1);\n for (int i = 0; i < length; i++) {\n if ((i == (str1[i] - 'A')) || (i == (str1[i] - 'a'))) {\n count_chars += 1;\n }\n }\n return count_chars;\n}", + "test": "int main() {\n\n assert(func0(\"xbcefg\") == 2);\n\n assert(func0(\"ABcED\") == 3);\n\n assert(func0(\"AbgdeF\") == 5);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmovl $0x0,-0xc(%rbp)\nmov -0x18(%rbp),%rax\nmov %rax,%rdi\ncallq 1060 \nmov %eax,-0x4(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11d6 \nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmovsbl %al,%eax\nsub $0x41,%eax\ncmp %eax,-0x8(%rbp)\nje 11ce \nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmovsbl %al,%eax\nsub $0x61,%eax\ncmp %eax,-0x8(%rbp)\njne 11d2 \naddl $0x1,-0xc(%rbp)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x4(%rbp),%eax\njl 1198 \nmov -0xc(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov [rbp+var_C], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_8], 0\njmp short loc_11D6\nloc_1198:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nsub eax, 41h ; 'A'\ncmp [rbp+var_8], eax\njz short loc_11CE\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nsub eax, 61h ; 'a'\ncmp [rbp+var_8], eax\njnz short loc_11D2\nloc_11CE:\nadd [rbp+var_C], 1\nloc_11D2:\nadd [rbp+var_8], 1\nloc_11D6:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njl short loc_1198\nmov eax, [rbp+var_C]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n unsigned int v2; // [rsp+14h] [rbp-Ch]\n int i; // [rsp+18h] [rbp-8h]\n int v4; // [rsp+1Ch] [rbp-4h]\n\n v2 = 0;\n v4 = strlen(a1);\n for ( i = 0; i < v4; ++i )\n {\n if ( i == a1[i] - 65 || i == a1[i] - 97 )\n ++v2;\n }\n return v2;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov [rbp+var_C], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_8], 0\njmp short loc_11D6\nloc_1198:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nsub eax, 41h ; 'A'\ncmp [rbp+var_8], eax\njz short loc_11CE\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nsub eax, 61h ; 'a'\ncmp [rbp+var_8], eax\njnz short loc_11D2\nloc_11CE:\nadd [rbp+var_C], 1\nloc_11D2:\nadd [rbp+var_8], 1\nloc_11D6:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njl short loc_1198\nmov eax, [rbp+var_C]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1)\n{\n unsigned int v2; // [rsp+14h] [rbp-Ch]\n int i; // [rsp+18h] [rbp-8h]\n int v4; // [rsp+1Ch] [rbp-4h]\n\n v2 = 0;\n v4 = strlen(a1);\n for ( i = 0; i < v4; ++i )\n {\n if ( i == a1[i] - 65 || i == a1[i] - 97 )\n ++v2;\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1) {\n unsigned int v2;\n int i;\n int v4;\n v2 = 0;\n v4 = strlen(a1);\n for (i = 0; i < v4; ++i) {\n if (i == a1[i] - 65 || i == a1[i] - 97) ++v2;\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n unsigned int v2;\n int i;\n int v4;\n v2 = 0;\n v4 = strlen(a1);\n for (i = 0; i < v4; ++i) {\n if (i == a1[i] - 65 || i == a1[i] - 97) ++v2;\n }\n return v2;\n}" + }, + { + "index": 165, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *str1) {\n int count_chars = 0;\n int length = strlen(str1);\n for (int i = 0; i < length; i++) {\n if ((i == (str1[i] - 'A')) || (i == (str1[i] - 'a'))) {\n count_chars += 1;\n }\n }\n return count_chars;\n}", + "test": "int main() {\n\n assert(func0(\"xbcefg\") == 2);\n\n assert(func0(\"ABcED\") == 3);\n\n assert(func0(\"AbgdeF\") == 5);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%rsi\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nsub $0x1,%rcx\ntest %ecx,%ecx\njle 119c \nlea -0x1(%rcx),%r8d\nmov $0x0,%eax\nmov $0x0,%edi\njmp 1188 \nadd $0x1,%edi\nlea 0x1(%rax),%rdx\ncmp %r8,%rax\nje 11a1 \nmov %rdx,%rax\nmovsbl (%rsi,%rax,1),%edx\nlea -0x41(%rdx),%ecx\ncmp %eax,%ecx\nje 1179 \nsub $0x61,%edx\ncmp %eax,%edx\njne 117c \njmp 1179 \nmov $0x0,%edi\nmov %edi,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest eax, eax\njle short loc_11AC\nlea edi, [rax-1]\nmov eax, 0\nmov esi, 0\njmp short loc_1198\nloc_1189:\nadd esi, 1\nloc_118C:\nlea rdx, [rax+1]\ncmp rax, rdi\njz short loc_11B1\nmov rax, rdx\nloc_1198:\nmovsx edx, byte ptr [rbx+rax]\nlea ecx, [rdx-41h]\ncmp ecx, eax\njz short loc_1189\nsub edx, 61h ; 'a'\ncmp edx, eax\njnz short loc_118C\njmp short loc_1189\nloc_11AC:\nmov esi, 0\nloc_11B1:\nmov eax, esi\npop rbx\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v2; // eax\n __int64 v3; // rdi\n __int64 v4; // rax\n unsigned int v5; // esi\n int v6; // edx\n\n v2 = strlen(a1);\n if ( v2 <= 0 )\n {\n return 0;\n }\n else\n {\n v3 = (unsigned int)(v2 - 1);\n v4 = 0LL;\n v5 = 0;\n while ( 1 )\n {\n v6 = a1[v4];\n if ( v6 - 65 == (_DWORD)v4 || v6 - 97 == (_DWORD)v4 )\n ++v5;\n if ( v4 == v3 )\n break;\n ++v4;\n }\n }\n return v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest eax, eax\njle short loc_11AC\nlea edi, [rax-1]\nmov eax, 0\nmov esi, 0\njmp short loc_1198\nloc_1189:\nadd esi, 1\nloc_118C:\nlea rdx, [rax+1]\ncmp rax, rdi\njz short loc_11B1\nmov rax, rdx\nloc_1198:\nmovsx edx, byte ptr [rbx+rax]\nlea ecx, [rdx-41h]\ncmp ecx, eax\njz short loc_1189\nsub edx, 61h ; 'a'\ncmp edx, eax\njnz short loc_118C\njmp short loc_1189\nloc_11AC:\nmov esi, 0\nloc_11B1:\nmov eax, esi\npop rbx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1)\n{\n int v2; // eax\n __int64 v3; // rdi\n __int64 v4; // rax\n unsigned int v5; // esi\n int v6; // edx\n\n v2 = strlen(a1);\n if ( v2 <= 0 )\n {\n return 0;\n }\n else\n {\n v3 = (unsigned int)(v2 - 1);\n v4 = 0LL;\n v5 = 0;\n while ( 1 )\n {\n v6 = a1[v4];\n if ( v6 - 65 == (_DWORD)v4 || v6 - 97 == (_DWORD)v4 )\n ++v5;\n if ( v4 == v3 )\n break;\n ++v4;\n }\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1) {\n int v2;\n long long v3;\n long long v4;\n unsigned int v5;\n int v6;\n v2 = strlen(a1);\n if (v2 <= 0) {\n return 0;\n } else {\n v3 = (unsigned int)(v2 - 1);\n v4 = 0LL;\n v5 = 0;\n while (1) {\n v6 = a1[v4];\n if (v6 - 65 == (uint32_t)v4 || v6 - 97 == (uint32_t)v4) ++v5;\n if (v4 == v3) break;\n ++v4;\n }\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v2;\n long long v3;\n long long v4;\n unsigned int v5;\n int v6;\n v2 = strlen(a1);\n if (v2 <= 0) {\n return 0;\n } else {\n v3 = (unsigned int)(v2 - 1);\n v4 = 0LL;\n v5 = 0;\n while (1) {\n v6 = a1[v4];\n if (v6 - 65 == (uint32_t)v4 || v6 - 97 == (uint32_t)v4) ++v5;\n if (v4 == v3) break;\n ++v4;\n }\n }\n return v5;\n}" + }, + { + "index": 165, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *str1) {\n int count_chars = 0;\n int length = strlen(str1);\n for (int i = 0; i < length; i++) {\n if ((i == (str1[i] - 'A')) || (i == (str1[i] - 'a'))) {\n count_chars += 1;\n }\n }\n return count_chars;\n}", + "test": "int main() {\n\n assert(func0(\"xbcefg\") == 2);\n\n assert(func0(\"ABcED\") == 3);\n\n assert(func0(\"AbgdeF\") == 5);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\ncallq 1060 \ntest %eax,%eax\njle 1260 \nlea -0x1(%rax),%esi\nxor %r8d,%r8d\nxor %eax,%eax\njmp 1243 \nnopl 0x0(%rax,%rax,1)\nsub $0x61,%edx\ncmp %eax,%edx\nje 124e \nlea 0x1(%rax),%rdx\ncmp %rsi,%rax\nje 125b \nmov %rdx,%rax\nmovsbl (%rbx,%rax,1),%edx\nlea -0x41(%rdx),%ecx\ncmp %eax,%ecx\njne 1230 \nadd $0x1,%r8d\nlea 0x1(%rax),%rdx\ncmp %rsi,%rax\njne 1240 \nmov %r8d,%eax\npop %rbx\nretq\nxor %r8d,%r8d\npop %rbx\nmov %r8d,%eax\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest eax, eax\njle short loc_1260\nlea edi, [rax-1]\nxor esi, esi\nxor eax, eax\njmp short loc_1243\nloc_1230:\nsub edx, 61h ; 'a'\ncmp eax, edx\njz short loc_124E\nlea rdx, [rax+1]\ncmp rdi, rax\njz short loc_125A\nloc_1240:\nmov rax, rdx\nloc_1243:\nmovsx edx, byte ptr [rbx+rax]\nlea ecx, [rdx-41h]\ncmp eax, ecx\njnz short loc_1230\nloc_124E:\nadd esi, 1\nlea rdx, [rax+1]\ncmp rdi, rax\njnz short loc_1240\nloc_125A:\nmov eax, esi\npop rbx\nretn\nloc_1260:\nxor esi, esi\npop rbx\nmov eax, esi\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v2; // eax\n __int64 v3; // rdi\n unsigned int v4; // esi\n __int64 i; // rax\n __int64 v6; // rdx\n int v7; // edx\n\n v2 = strlen(a1);\n if ( v2 > 0 )\n {\n v3 = (unsigned int)(v2 - 1);\n v4 = 0;\n for ( i = 0LL; ; i = v6 )\n {\n v7 = a1[i];\n if ( (_DWORD)i == v7 - 65 || (_DWORD)i == v7 - 97 )\n {\n ++v4;\n v6 = i + 1;\n if ( v3 == i )\n return v4;\n }\n else\n {\n v6 = i + 1;\n if ( v3 == i )\n return v4;\n }\n }\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest eax, eax\njle short loc_1260\nlea edi, [rax-1]\nxor esi, esi\nxor eax, eax\njmp short loc_1243\nloc_1230:\nsub edx, 61h ; 'a'\ncmp eax, edx\njz short loc_124E\nlea rdx, [rax+1]\ncmp rdi, rax\njz short loc_125A\nloc_1240:\nmov rax, rdx\nloc_1243:\nmovsx edx, byte ptr [rbx+rax]\nlea ecx, [rdx-41h]\ncmp eax, ecx\njnz short loc_1230\nloc_124E:\nadd esi, 1\nlea rdx, [rax+1]\ncmp rdi, rax\njnz short loc_1240\nloc_125A:\nmov eax, esi\npop rbx\nretn\nloc_1260:\nxor esi, esi\npop rbx\nmov eax, esi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(const char *a1)\n{\n int v2; // eax\n __int64 v3; // rdi\n unsigned int v4; // esi\n __int64 i; // rax\n __int64 v6; // rdx\n int v7; // edx\n\n v2 = strlen(a1);\n if ( v2 > 0 )\n {\n v3 = (unsigned int)(v2 - 1);\n v4 = 0;\n for ( i = 0LL; ; i = v6 )\n {\n v7 = a1[i];\n if ( (_DWORD)i == v7 - 65 || (_DWORD)i == v7 - 97 )\n {\n ++v4;\n v6 = i + 1;\n if ( v3 == i )\n return v4;\n }\n else\n {\n v6 = i + 1;\n if ( v3 == i )\n return v4;\n }\n }\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(const char *a1) {\n int v2;\n long long v3;\n unsigned int v4;\n long long i;\n long long v6;\n int v7;\n v2 = strlen(a1);\n if (v2 > 0) {\n v3 = (unsigned int)(v2 - 1);\n v4 = 0;\n for (i = 0LL;; i = v6) {\n v7 = a1[i];\n if ((uint32_t)i == v7 - 65 || (uint32_t)i == v7 - 97) {\n ++v4;\n v6 = i + 1;\n if (v3 == i) return v4;\n } else {\n v6 = i + 1;\n if (v3 == i) return v4;\n }\n }\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v2;\n long long v3;\n unsigned int v4;\n long long i;\n long long v6;\n int v7;\n v2 = strlen(a1);\n if (v2 > 0) {\n v3 = (unsigned int)(v2 - 1);\n v4 = 0;\n for (i = 0LL;; i = v6) {\n v7 = a1[i];\n if ((uint32_t)i == v7 - 65 || (uint32_t)i == v7 - 97) {\n ++v4;\n v6 = i + 1;\n if (v3 == i) return v4;\n } else {\n v6 = i + 1;\n if (v3 == i) return v4;\n }\n }\n }\n return 0LL;\n}" + }, + { + "index": 165, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *str1) {\n int count_chars = 0;\n int length = strlen(str1);\n for (int i = 0; i < length; i++) {\n if ((i == (str1[i] - 'A')) || (i == (str1[i] - 'a'))) {\n count_chars += 1;\n }\n }\n return count_chars;\n}", + "test": "int main() {\n\n assert(func0(\"xbcefg\") == 2);\n\n assert(func0(\"ABcED\") == 3);\n\n assert(func0(\"AbgdeF\") == 5);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\nsub $0x10,%rsp\ncallq 1060 \ntest %eax,%eax\njle 1420 \nmov %rax,%rdi\nmov %eax,%esi\nlea -0x1(%rax),%eax\ncmp $0xe,%eax\njbe 142c \nmovdqa 0xe5e(%rip),%xmm2\nmov %edi,%ecx\nmov %rbx,%rdx\nmovdqa 0xea0(%rip),%xmm11\nmovdqa 0xea7(%rip),%xmm10\nshr $0x4,%ecx\nshl $0x4,%rcx\nmovaps %xmm2,(%rsp)\npxor %xmm2,%xmm2\nadd %rbx,%rcx\nmovdqa %xmm2,%xmm9\nmovdqu (%rdx),%xmm0\npxor %xmm3,%xmm3\nmovdqa (%rsp),%xmm6\npxor %xmm12,%xmm12\nmovdqa %xmm11,%xmm15\nmovdqa %xmm11,%xmm14\nmovdqa %xmm11,%xmm13\nmovdqa 0xe26(%rip),%xmm8\npcmpgtb %xmm0,%xmm3\nmovdqa %xmm0,%xmm1\nmovdqa %xmm6,%xmm5\nadd $0x10,%rdx\npaddd 0xdfe(%rip),%xmm6\nmovdqa 0xe16(%rip),%xmm7\npaddd %xmm5,%xmm8\npunpcklbw %xmm3,%xmm1\npunpckhbw %xmm3,%xmm0\npxor %xmm3,%xmm3\nmovaps %xmm6,(%rsp)\npcmpgtw %xmm1,%xmm3\nmovdqa %xmm1,%xmm4\npaddd %xmm5,%xmm7\nmovdqa 0xdfd(%rip),%xmm6\npcmpgtw %xmm0,%xmm12\npaddd %xmm5,%xmm6\npunpcklwd %xmm3,%xmm4\npunpckhwd %xmm3,%xmm1\nmovdqa %xmm0,%xmm3\npaddd %xmm4,%xmm15\npaddd %xmm10,%xmm4\npunpcklwd %xmm12,%xmm3\npaddd %xmm1,%xmm14\npcmpeqd %xmm5,%xmm4\npaddd %xmm10,%xmm1\npcmpeqd %xmm15,%xmm5\npunpckhwd %xmm12,%xmm0\npaddd %xmm3,%xmm13\npcmpeqd %xmm8,%xmm1\nmovdqa %xmm11,%xmm12\npaddd %xmm10,%xmm3\npcmpeqd %xmm14,%xmm8\npcmpeqd %xmm7,%xmm3\npaddd %xmm0,%xmm12\npcmpeqd %xmm13,%xmm7\npaddd %xmm10,%xmm0\nmovdqa %xmm5,%xmm15\npcmpeqd %xmm6,%xmm0\npcmpeqd %xmm12,%xmm6\nmovdqa %xmm8,%xmm14\npcmpeqd %xmm9,%xmm15\nmovdqa %xmm7,%xmm13\npcmpeqd %xmm9,%xmm14\nmovdqa %xmm6,%xmm12\npcmpeqd %xmm9,%xmm13\npcmpeqd %xmm9,%xmm12\npand %xmm15,%xmm4\npor %xmm4,%xmm5\npand %xmm14,%xmm1\npsubd %xmm5,%xmm2\npor %xmm1,%xmm8\npand %xmm13,%xmm3\npsubd %xmm8,%xmm2\npor %xmm3,%xmm7\npand %xmm12,%xmm0\npsubd %xmm7,%xmm2\npor %xmm0,%xmm6\npsubd %xmm6,%xmm2\ncmp %rcx,%rdx\njne 1270 \nmovdqa %xmm2,%xmm0\nmov %edi,%eax\npsrldq $0x8,%xmm0\nand $0xfffffff0,%eax\nand $0xf,%edi\npaddd %xmm0,%xmm2\nmovdqa %xmm2,%xmm0\npsrldq $0x4,%xmm0\npaddd %xmm0,%xmm2\nmovd %xmm2,%r8d\nje 1416 \ncltq\njmp 13ff \nnopl 0x0(%rax,%rax,1)\nsub $0x61,%edx\ncmp %edx,%eax\nje 140a \nadd $0x1,%rax\ncmp %eax,%esi\njle 1416 \nmovsbl (%rbx,%rax,1),%edx\nlea -0x41(%rdx),%ecx\ncmp %ecx,%eax\njne 13f0 \nadd $0x1,%rax\nadd $0x1,%r8d\ncmp %eax,%esi\njg 13ff \nadd $0x10,%rsp\nmov %r8d,%eax\npop %rbx\nretq\nxor %r8d,%r8d\nadd $0x10,%rsp\nmov %r8d,%eax\npop %rbx\nretq\nxor %eax,%eax\nxor %r8d,%r8d\njmp 13e4 \nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest eax, eax\njle loc_16F0\nmov rcx, rax\nlea eax, [rax-1]\ncmp eax, 0Eh\njbe loc_16F4\nmov edx, ecx\npxor xmm2, xmm2\npxor xmm15, xmm15\nmov rax, rbx\nshr edx, 4\nmovdqa xmm5, xmm2\nmovdqa xmm11, cs:xmmword_2080\nmovdqa xmm10, cs:xmmword_20D0\nshl rdx, 4\nmovdqa xmm4, xmm2\nmovdqa xmm9, cs:xmmword_20E0\nmovdqa xmm8, cs:xmmword_20F0\nadd rdx, rbx\nnop dword ptr [rax+rax+00000000h]\nloc_1280:\nmovdqu xmm0, xmmword ptr [rax]\npxor xmm2, xmm2\nmovdqa xmm14, xmm15\nmovdqa xmm3, cs:xmmword_20A0\nmovdqa xmm7, xmm11\nadd rax, 10h\nmovdqa xmm12, cs:xmmword_20B0\nmovdqa xmm13, cs:xmmword_20C0\npcmpgtb xmm2, xmm0\nmovdqa xmm1, xmm0\npaddd xmm3, xmm7\npaddd xmm12, xmm7\npaddd xmm13, xmm7\npaddd xmm11, cs:xmmword_2090\npunpcklbw xmm1, xmm2\npunpckhbw xmm0, xmm2\nmovdqa xmm2, xmm15\npcmpgtw xmm2, xmm1\npcmpgtw xmm14, xmm0\nmovdqa xmm6, xmm1\npunpcklwd xmm6, xmm2\npunpckhwd xmm1, xmm2\nmovdqa xmm2, xmm0\npunpcklwd xmm2, xmm14\npunpckhwd xmm0, xmm14\nmovdqa xmm14, xmm10\npaddd xmm14, xmm1\npaddd xmm1, xmm9\npcmpeqd xmm14, xmm3\npcmpeqd xmm3, xmm1\npcmpeqd xmm14, xmm5\npcmpeqd xmm3, xmm5\nmovdqa xmm1, xmm14\npand xmm1, xmm3\nmovdqa xmm3, xmm10\npaddd xmm3, xmm2\npaddd xmm2, xmm9\npandn xmm1, xmm8\npcmpeqd xmm3, xmm12\npcmpeqd xmm2, xmm12\nmovdqa xmm12, xmm10\npaddd xmm12, xmm0\npcmpeqd xmm12, xmm13\npcmpeqd xmm2, xmm5\npcmpeqd xmm3, xmm5\npcmpeqd xmm12, xmm5\npand xmm3, xmm2\nmovdqa xmm2, xmm0\npaddd xmm2, xmm9\npandn xmm3, xmm8\npcmpeqd xmm2, xmm13\nmovdqa xmm0, xmm12\npcmpeqd xmm2, xmm5\npand xmm0, xmm2\nmovdqa xmm2, xmm10\npaddd xmm2, xmm6\npaddd xmm6, xmm9\npandn xmm0, xmm8\npcmpeqd xmm2, xmm7\npcmpeqd xmm6, xmm7\npcmpeqd xmm2, xmm5\npcmpeqd xmm6, xmm5\npand xmm2, xmm6\npandn xmm2, xmm8\npaddd xmm2, xmm4\nmovdqa xmm4, xmm0\npaddd xmm1, xmm2\npaddd xmm3, xmm1\npaddd xmm4, xmm3\ncmp rdx, rax\njnz loc_1280\nmovdqa xmm0, xmm4\nmovdqa xmm2, xmm4\nmovdqa xmm5, xmm4\nmov edi, ecx\npsrldq xmm0, 8\nand edi, 0FFFFFFF0h\npsrldq xmm2, 8\npaddd xmm0, xmm4\npaddd xmm5, xmm2\nmov edx, edi\nmovdqa xmm1, xmm0\npsrldq xmm1, 4\npaddd xmm0, xmm1\nmovd eax, xmm0\ntest cl, 0Fh\njz loc_168D\nloc_140E:\nmov esi, ecx\nsub esi, edi\nlea r8d, [rsi-1]\ncmp r8d, 6\njbe loc_1596\nlea eax, [rdx+1]\npxor xmm1, xmm1\nmovd xmm9, edx\nmovq xmm13, cs:qword_2100\nmovd xmm4, eax\nmov eax, edi\npxor xmm7, xmm7\nmovq xmm11, cs:qword_2108\nmovq xmm2, qword ptr [rbx+rax]\npunpckldq xmm9, xmm4\nmovq xmm4, qword ptr cs:xmmword_20E0\npaddd xmm13, xmm9\npaddd xmm11, xmm9\nmovq xmm12, qword ptr cs:xmmword_20A0\npcmpgtb xmm1, xmm2\nmovdqa xmm0, xmm2\npaddd xmm12, xmm9\npunpcklbw xmm2, xmm1\npunpcklbw xmm0, xmm1\npxor xmm1, xmm1\npshufd xmm2, xmm2, 4Eh ; 'N'\nmovdqa xmm3, xmm1\nmovdqa xmm10, xmm0\npcmpgtw xmm1, xmm2\npcmpgtw xmm3, xmm0\nmovdqa xmm8, xmm2\npunpcklwd xmm8, xmm1\npunpcklwd xmm2, xmm1\npunpcklwd xmm0, xmm3\nmovq xmm1, qword ptr cs:xmmword_20D0\npshufd xmm0, xmm0, 4Eh ; 'N'\npshufd xmm2, xmm2, 4Eh ; 'N'\npunpcklwd xmm10, xmm3\nmovdqa xmm6, xmm1\nmovdqa xmm3, xmm1\npaddd xmm6, xmm0\npaddd xmm0, xmm4\npaddd xmm3, xmm8\npaddd xmm8, xmm4\npcmpeqd xmm6, xmm13\npcmpeqd xmm0, xmm13\npcmpeqd xmm3, xmm12\npcmpeqd xmm8, xmm12\npcmpeqd xmm0, xmm7\npcmpeqd xmm6, xmm7\npcmpeqd xmm3, xmm7\npcmpeqd xmm8, xmm7\npand xmm6, xmm0\nmovdqa xmm0, xmm1\npaddd xmm1, xmm10\npaddd xmm0, xmm2\npaddd xmm2, xmm4\npand xmm3, xmm8\npaddd xmm4, xmm10\npcmpeqd xmm1, xmm9\npcmpeqd xmm0, xmm11\npcmpeqd xmm2, xmm11\npcmpeqd xmm4, xmm9\npcmpeqd xmm1, xmm7\npcmpeqd xmm2, xmm7\npcmpeqd xmm0, xmm7\npcmpeqd xmm4, xmm7\npand xmm0, xmm2\nmovq xmm2, qword ptr cs:xmmword_20F0\npand xmm1, xmm4\npandn xmm1, xmm2\npandn xmm6, xmm2\npandn xmm3, xmm2\npaddd xmm5, xmm1\npandn xmm0, xmm2\npaddd xmm6, xmm5\npaddd xmm3, xmm6\npaddd xmm0, xmm3\nmovd edi, xmm0\npshufd xmm7, xmm0, 0E5h\nmovd eax, xmm7\nadd eax, edi\nmov edi, esi\nand edi, 0FFFFFFF8h\nadd edx, edi\nand esi, 7\njz loc_168D\nloc_1596:\nmovsxd rsi, edx\nmovsx esi, byte ptr [rbx+rsi]\nlea edi, [rsi-41h]\ncmp edi, edx\njz loc_1690\nsub esi, 61h ; 'a'\ncmp esi, edx\njz loc_1690\nloc_15B3:\nlea esi, [rdx+1]\ncmp esi, ecx\njge loc_168D\nmovsxd rdi, esi\nmovsx edi, byte ptr [rbx+rdi]\nlea r8d, [rdi-41h]\ncmp esi, r8d\njz loc_16B0\nsub edi, 61h ; 'a'\ncmp esi, edi\njz loc_16B0\nloc_15DD:\nlea esi, [rdx+2]\ncmp ecx, esi\njle loc_168D\nmovsxd rdi, esi\nmovsx edi, byte ptr [rbx+rdi]\nlea r8d, [rdi-41h]\ncmp esi, r8d\njz loc_16C0\nsub edi, 61h ; 'a'\ncmp esi, edi\njz loc_16C0\nloc_1607:\nlea esi, [rdx+3]\ncmp ecx, esi\njle short loc_168D\nmovsxd rdi, esi\nmovsx edi, byte ptr [rbx+rdi]\nlea r8d, [rdi-41h]\ncmp r8d, esi\njz loc_16D0\nsub edi, 61h ; 'a'\ncmp edi, esi\njz loc_16D0\nloc_162D:\nlea esi, [rdx+4]\ncmp ecx, esi\njle short loc_168D\nmovsxd rdi, esi\nmovsx edi, byte ptr [rbx+rdi]\nlea r8d, [rdi-41h]\ncmp esi, r8d\njz loc_16E0\nsub edi, 61h ; 'a'\ncmp esi, edi\njz loc_16E0\nloc_1653:\nlea esi, [rdx+5]\ncmp ecx, esi\njle short loc_168D\nmovsxd rdi, esi\nmovsx edi, byte ptr [rbx+rdi]\nlea r8d, [rdi-41h]\ncmp r8d, esi\njz short loc_16A0\nsub edi, 61h ; 'a'\ncmp esi, edi\njz short loc_16A0\nloc_1671:\nadd edx, 6\ncmp ecx, edx\njle short loc_168D\nmovsxd rcx, edx\nmovsx ecx, byte ptr [rbx+rcx]\nlea esi, [rcx-41h]\ncmp esi, edx\njz short loc_16A8\nsub ecx, 61h ; 'a'\ncmp ecx, edx\njz short loc_16A8\nloc_168D:\npop rbx\nretn\nloc_1690:\nadd eax, 1\njmp loc_15B3\nloc_16A0:\nadd eax, 1\njmp short loc_1671\nloc_16A8:\nadd eax, 1\npop rbx\nretn\nloc_16B0:\nadd eax, 1\njmp loc_15DD\nloc_16C0:\nadd eax, 1\njmp loc_1607\nloc_16D0:\nadd eax, 1\njmp loc_162D\nloc_16E0:\nadd eax, 1\njmp loc_1653\nloc_16F0:\nxor eax, eax\npop rbx\nretn\nloc_16F4:\npxor xmm5, xmm5\nxor edi, edi\nxor edx, edx\nxor eax, eax\njmp loc_140E", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v2; // eax\n int v3; // ecx\n const __m128i *v4; // rax\n __m128i si128; // xmm11\n __m128i v6; // xmm10\n __m128i v7; // xmm4\n __m128i v8; // xmm9\n __m128i v9; // xmm8\n __m128i v10; // xmm0\n __m128i v11; // xmm7\n __m128i v12; // xmm2\n __m128i v13; // xmm3\n __m128i v14; // xmm12\n __m128i v15; // xmm13\n __m128i v16; // xmm1\n __m128i v17; // xmm0\n __m128i v18; // xmm2\n __m128i v19; // xmm14\n __m128i v20; // xmm6\n __m128i v21; // xmm1\n __m128i v22; // xmm2\n __m128i v23; // xmm0\n unsigned int v24; // edi\n __m128i v25; // xmm0\n __m128i v26; // xmm5\n signed int v27; // edx\n __int64 result; // rax\n unsigned int v29; // esi\n __m128i v30; // xmm2\n __m128i v31; // xmm9\n __m128i v32; // xmm4\n __m128i v33; // xmm13\n __m128i v34; // xmm11\n __m128i v35; // xmm1\n __m128i v36; // xmm0\n __m128i v37; // xmm12\n __m128i v38; // xmm2\n __m128i v39; // xmm10\n __m128i v40; // xmm3\n __m128i v41; // xmm8\n __m128i v42; // xmm1\n __m128i v43; // xmm0\n __m128i v44; // xmm2\n __m128i v45; // xmm10\n __m128i v46; // xmm6\n __m128i v47; // xmm0\n __m128i v48; // xmm2\n __m128i v49; // xmm0\n int v50; // esi\n int v51; // esi\n int v52; // edi\n int v53; // esi\n int v54; // edi\n int v55; // esi\n int v56; // edi\n int v57; // esi\n int v58; // edi\n int v59; // esi\n int v60; // edi\n int v61; // edx\n int v62; // ecx\n\n v2 = strlen(a1);\n if ( v2 <= 0 )\n return 0LL;\n v3 = v2;\n if ( (unsigned int)(v2 - 1) <= 0xE )\n {\n v26 = 0LL;\n v24 = 0;\n v27 = 0;\n result = 0LL;\n }\n else\n {\n v4 = (const __m128i *)a1;\n si128 = _mm_load_si128((const __m128i *)&xmmword_2080);\n v6 = _mm_load_si128((const __m128i *)&xmmword_20D0);\n v7 = 0LL;\n v8 = _mm_load_si128((const __m128i *)&xmmword_20E0);\n v9 = _mm_load_si128((const __m128i *)&xmmword_20F0);\n do\n {\n v10 = _mm_loadu_si128(v4);\n v11 = si128;\n ++v4;\n v12 = _mm_cmpgt_epi8((__m128i)0LL, v10);\n v13 = _mm_add_epi32(_mm_load_si128((const __m128i *)&xmmword_20A0), si128);\n v14 = _mm_add_epi32(_mm_load_si128((const __m128i *)&xmmword_20B0), si128);\n v15 = _mm_add_epi32(_mm_load_si128((const __m128i *)&xmmword_20C0), si128);\n si128 = _mm_add_epi32(si128, (__m128i)xmmword_2090);\n v16 = _mm_unpacklo_epi8(v10, v12);\n v17 = _mm_unpackhi_epi8(v10, v12);\n v18 = _mm_cmpgt_epi16((__m128i)0LL, v16);\n v19 = _mm_cmpgt_epi16((__m128i)0LL, v17);\n v20 = _mm_unpacklo_epi16(v16, v18);\n v21 = _mm_unpackhi_epi16(v16, v18);\n v22 = _mm_unpacklo_epi16(v17, v19);\n v23 = _mm_unpackhi_epi16(v17, v19);\n v7 = _mm_add_epi32(\n _mm_andnot_si128(\n _mm_and_si128(\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v6, v23), v15), (__m128i)0LL),\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v23, v8), v15), (__m128i)0LL)),\n v9),\n _mm_add_epi32(\n _mm_andnot_si128(\n _mm_and_si128(\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v6, v22), v14), (__m128i)0LL),\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v22, v8), v14), (__m128i)0LL)),\n v9),\n _mm_add_epi32(\n _mm_andnot_si128(\n _mm_and_si128(\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v6, v21), v13), (__m128i)0LL),\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(v13, _mm_add_epi32(v21, v8)), (__m128i)0LL)),\n v9),\n _mm_add_epi32(\n _mm_andnot_si128(\n _mm_and_si128(\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v6, v20), v11), (__m128i)0LL),\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v20, v8), v11), (__m128i)0LL)),\n v9),\n v7))));\n }\n while ( &a1[16 * ((unsigned int)v3 >> 4)] != (const char *)v4 );\n v24 = v3 & 0x7FFFFFF0;\n v25 = _mm_add_epi32(_mm_srli_si128(v7, 8), v7);\n v26 = _mm_add_epi32(v7, _mm_srli_si128(v7, 8));\n v27 = v3 & 0xFFFFFFF0;\n result = (unsigned int)_mm_cvtsi128_si32(_mm_add_epi32(v25, _mm_srli_si128(v25, 4)));\n if ( (v3 & 0xF) == 0 )\n return result;\n }\n v29 = v3 - v24;\n if ( v3 - v24 - 1 <= 6 )\n goto LABEL_8;\n v30 = _mm_loadl_epi64((const __m128i *)&a1[v24]);\n v31 = _mm_unpacklo_epi32(_mm_cvtsi32_si128(v27), _mm_cvtsi32_si128(v27 + 1));\n v32 = _mm_loadl_epi64((const __m128i *)&xmmword_20E0);\n v33 = _mm_add_epi32(_mm_loadl_epi64((const __m128i *)&qword_2100), v31);\n v34 = _mm_add_epi32(_mm_loadl_epi64((const __m128i *)&qword_2108), v31);\n v35 = _mm_cmpgt_epi8((__m128i)0LL, v30);\n v36 = v30;\n v37 = _mm_add_epi32(_mm_loadl_epi64((const __m128i *)&xmmword_20A0), v31);\n v38 = _mm_shuffle_epi32(_mm_unpacklo_epi8(v30, v35), 78);\n v39 = _mm_unpacklo_epi8(v36, v35);\n v40 = _mm_cmpgt_epi16((__m128i)0LL, v39);\n v41 = _mm_unpacklo_epi16(v38, _mm_cmpgt_epi16((__m128i)0LL, v38));\n v42 = _mm_loadl_epi64((const __m128i *)&xmmword_20D0);\n v43 = _mm_shuffle_epi32(_mm_unpacklo_epi16(v39, v40), 78);\n v44 = _mm_shuffle_epi32(v41, 78);\n v45 = _mm_unpacklo_epi16(v39, v40);\n v46 = _mm_and_si128(\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v42, v43), v33), (__m128i)0LL),\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v43, v32), v33), (__m128i)0LL));\n v47 = _mm_and_si128(\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v42, v44), v34), (__m128i)0LL),\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v44, v32), v34), (__m128i)0LL));\n v48 = _mm_loadl_epi64((const __m128i *)&xmmword_20F0);\n v49 = _mm_add_epi32(\n _mm_andnot_si128(v47, v48),\n _mm_add_epi32(\n _mm_andnot_si128(\n _mm_and_si128(\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v42, v41), v37), (__m128i)0LL),\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v41, v32), v37), (__m128i)0LL)),\n v48),\n _mm_add_epi32(\n _mm_andnot_si128(v46, v48),\n _mm_add_epi32(\n v26,\n _mm_andnot_si128(\n _mm_and_si128(\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v42, v45), v31), (__m128i)0LL),\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v32, v45), v31), (__m128i)0LL)),\n v48)))));\n result = (unsigned int)(_mm_cvtsi128_si32(v49) + _mm_cvtsi128_si32(_mm_shuffle_epi32(v49, 229)));\n v27 += v29 & 0xFFFFFFF8;\n if ( (v29 & 7) != 0 )\n {\nLABEL_8:\n v50 = a1[v27];\n if ( v50 - 65 == v27 || v50 - 97 == v27 )\n result = (unsigned int)(result + 1);\n v51 = v27 + 1;\n if ( v27 + 1 < v3 )\n {\n v52 = a1[v51];\n if ( v51 == v52 - 65 || v51 == v52 - 97 )\n result = (unsigned int)(result + 1);\n v53 = v27 + 2;\n if ( v3 > v27 + 2 )\n {\n v54 = a1[v53];\n if ( v53 == v54 - 65 || v53 == v54 - 97 )\n result = (unsigned int)(result + 1);\n v55 = v27 + 3;\n if ( v3 > v27 + 3 )\n {\n v56 = a1[v55];\n if ( v56 - 65 == v55 || v56 - 97 == v55 )\n result = (unsigned int)(result + 1);\n v57 = v27 + 4;\n if ( v3 > v27 + 4 )\n {\n v58 = a1[v57];\n if ( v57 == v58 - 65 || v57 == v58 - 97 )\n result = (unsigned int)(result + 1);\n v59 = v27 + 5;\n if ( v3 > v27 + 5 )\n {\n v60 = a1[v59];\n if ( v60 - 65 == v59 || v59 == v60 - 97 )\n result = (unsigned int)(result + 1);\n v61 = v27 + 6;\n if ( v3 > v61 )\n {\n v62 = a1[v61];\n if ( v62 - 65 == v61 || v62 - 97 == v61 )\n return (unsigned int)(result + 1);\n }\n }\n }\n }\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest eax, eax\njle loc_16F0\nmov rcx, rax\nlea eax, [rax-1]\ncmp eax, 0Eh\njbe loc_16F4\nmov edx, ecx\npxor xmm2, xmm2\npxor xmm15, xmm15\nmov rax, rbx\nshr edx, 4\nmovdqa xmm5, xmm2\nmovdqa xmm11, cs:xmmword_2080\nmovdqa xmm10, cs:xmmword_20D0\nshl rdx, 4\nmovdqa xmm4, xmm2\nmovdqa xmm9, cs:xmmword_20E0\nmovdqa xmm8, cs:xmmword_20F0\nadd rdx, rbx\nnop dword ptr [rax+rax+00000000h]\nloc_1280:\nmovdqu xmm0, xmmword ptr [rax]\npxor xmm2, xmm2\nmovdqa xmm14, xmm15\nmovdqa xmm3, cs:xmmword_20A0\nmovdqa xmm7, xmm11\nadd rax, 10h\nmovdqa xmm12, cs:xmmword_20B0\nmovdqa xmm13, cs:xmmword_20C0\npcmpgtb xmm2, xmm0\nmovdqa xmm1, xmm0\npaddd xmm3, xmm7\npaddd xmm12, xmm7\npaddd xmm13, xmm7\npaddd xmm11, cs:xmmword_2090\npunpcklbw xmm1, xmm2\npunpckhbw xmm0, xmm2\nmovdqa xmm2, xmm15\npcmpgtw xmm2, xmm1\npcmpgtw xmm14, xmm0\nmovdqa xmm6, xmm1\npunpcklwd xmm6, xmm2\npunpckhwd xmm1, xmm2\nmovdqa xmm2, xmm0\npunpcklwd xmm2, xmm14\npunpckhwd xmm0, xmm14\nmovdqa xmm14, xmm10\npaddd xmm14, xmm1\npaddd xmm1, xmm9\npcmpeqd xmm14, xmm3\npcmpeqd xmm3, xmm1\npcmpeqd xmm14, xmm5\npcmpeqd xmm3, xmm5\nmovdqa xmm1, xmm14\npand xmm1, xmm3\nmovdqa xmm3, xmm10\npaddd xmm3, xmm2\npaddd xmm2, xmm9\npandn xmm1, xmm8\npcmpeqd xmm3, xmm12\npcmpeqd xmm2, xmm12\nmovdqa xmm12, xmm10\npaddd xmm12, xmm0\npcmpeqd xmm12, xmm13\npcmpeqd xmm2, xmm5\npcmpeqd xmm3, xmm5\npcmpeqd xmm12, xmm5\npand xmm3, xmm2\nmovdqa xmm2, xmm0\npaddd xmm2, xmm9\npandn xmm3, xmm8\npcmpeqd xmm2, xmm13\nmovdqa xmm0, xmm12\npcmpeqd xmm2, xmm5\npand xmm0, xmm2\nmovdqa xmm2, xmm10\npaddd xmm2, xmm6\npaddd xmm6, xmm9\npandn xmm0, xmm8\npcmpeqd xmm2, xmm7\npcmpeqd xmm6, xmm7\npcmpeqd xmm2, xmm5\npcmpeqd xmm6, xmm5\npand xmm2, xmm6\npandn xmm2, xmm8\npaddd xmm2, xmm4\nmovdqa xmm4, xmm0\npaddd xmm1, xmm2\npaddd xmm3, xmm1\npaddd xmm4, xmm3\ncmp rdx, rax\njnz loc_1280\nmovdqa xmm0, xmm4\nmovdqa xmm2, xmm4\nmovdqa xmm5, xmm4\nmov edi, ecx\npsrldq xmm0, 8\nand edi, 0FFFFFFF0h\npsrldq xmm2, 8\npaddd xmm0, xmm4\npaddd xmm5, xmm2\nmov edx, edi\nmovdqa xmm1, xmm0\npsrldq xmm1, 4\npaddd xmm0, xmm1\nmovd eax, xmm0\ntest cl, 0Fh\njz loc_168D\nloc_140E:\nmov esi, ecx\nsub esi, edi\nlea r8d, [rsi-1]\ncmp r8d, 6\njbe loc_1596\nlea eax, [rdx+1]\npxor xmm1, xmm1\nmovd xmm9, edx\nmovq xmm13, cs:qword_2100\nmovd xmm4, eax\nmov eax, edi\npxor xmm7, xmm7\nmovq xmm11, cs:qword_2108\nmovq xmm2, qword ptr [rbx+rax]\npunpckldq xmm9, xmm4\nmovq xmm4, qword ptr cs:xmmword_20E0\npaddd xmm13, xmm9\npaddd xmm11, xmm9\nmovq xmm12, qword ptr cs:xmmword_20A0\npcmpgtb xmm1, xmm2\nmovdqa xmm0, xmm2\npaddd xmm12, xmm9\npunpcklbw xmm2, xmm1\npunpcklbw xmm0, xmm1\npxor xmm1, xmm1\npshufd xmm2, xmm2, 4Eh ; 'N'\nmovdqa xmm3, xmm1\nmovdqa xmm10, xmm0\npcmpgtw xmm1, xmm2\npcmpgtw xmm3, xmm0\nmovdqa xmm8, xmm2\npunpcklwd xmm8, xmm1\npunpcklwd xmm2, xmm1\npunpcklwd xmm0, xmm3\nmovq xmm1, qword ptr cs:xmmword_20D0\npshufd xmm0, xmm0, 4Eh ; 'N'\npshufd xmm2, xmm2, 4Eh ; 'N'\npunpcklwd xmm10, xmm3\nmovdqa xmm6, xmm1\nmovdqa xmm3, xmm1\npaddd xmm6, xmm0\npaddd xmm0, xmm4\npaddd xmm3, xmm8\npaddd xmm8, xmm4\npcmpeqd xmm6, xmm13\npcmpeqd xmm0, xmm13\npcmpeqd xmm3, xmm12\npcmpeqd xmm8, xmm12\npcmpeqd xmm0, xmm7\npcmpeqd xmm6, xmm7\npcmpeqd xmm3, xmm7\npcmpeqd xmm8, xmm7\npand xmm6, xmm0\nmovdqa xmm0, xmm1\npaddd xmm1, xmm10\npaddd xmm0, xmm2\npaddd xmm2, xmm4\npand xmm3, xmm8\npaddd xmm4, xmm10\npcmpeqd xmm1, xmm9\npcmpeqd xmm0, xmm11\npcmpeqd xmm2, xmm11\npcmpeqd xmm4, xmm9\npcmpeqd xmm1, xmm7\npcmpeqd xmm2, xmm7\npcmpeqd xmm0, xmm7\npcmpeqd xmm4, xmm7\npand xmm0, xmm2\nmovq xmm2, qword ptr cs:xmmword_20F0\npand xmm1, xmm4\npandn xmm1, xmm2\npandn xmm6, xmm2\npandn xmm3, xmm2\npaddd xmm5, xmm1\npandn xmm0, xmm2\npaddd xmm6, xmm5\npaddd xmm3, xmm6\npaddd xmm0, xmm3\nmovd edi, xmm0\npshufd xmm7, xmm0, 0E5h\nmovd eax, xmm7\nadd eax, edi\nmov edi, esi\nand edi, 0FFFFFFF8h\nadd edx, edi\nand esi, 7\njz loc_168D\nloc_1596:\nmovsxd rsi, edx\nmovsx esi, byte ptr [rbx+rsi]\nlea edi, [rsi-41h]\ncmp edi, edx\njz loc_1690\nsub esi, 61h ; 'a'\ncmp esi, edx\njz loc_1690\nloc_15B3:\nlea esi, [rdx+1]\ncmp esi, ecx\njge loc_168D\nmovsxd rdi, esi\nmovsx edi, byte ptr [rbx+rdi]\nlea r8d, [rdi-41h]\ncmp esi, r8d\njz loc_16B0\nsub edi, 61h ; 'a'\ncmp esi, edi\njz loc_16B0\nloc_15DD:\nlea esi, [rdx+2]\ncmp ecx, esi\njle loc_168D\nmovsxd rdi, esi\nmovsx edi, byte ptr [rbx+rdi]\nlea r8d, [rdi-41h]\ncmp esi, r8d\njz loc_16C0\nsub edi, 61h ; 'a'\ncmp esi, edi\njz loc_16C0\nloc_1607:\nlea esi, [rdx+3]\ncmp ecx, esi\njle short loc_168D\nmovsxd rdi, esi\nmovsx edi, byte ptr [rbx+rdi]\nlea r8d, [rdi-41h]\ncmp r8d, esi\njz loc_16D0\nsub edi, 61h ; 'a'\ncmp edi, esi\njz loc_16D0\nloc_162D:\nlea esi, [rdx+4]\ncmp ecx, esi\njle short loc_168D\nmovsxd rdi, esi\nmovsx edi, byte ptr [rbx+rdi]\nlea r8d, [rdi-41h]\ncmp esi, r8d\njz loc_16E0\nsub edi, 61h ; 'a'\ncmp esi, edi\njz loc_16E0\nloc_1653:\nlea esi, [rdx+5]\ncmp ecx, esi\njle short loc_168D\nmovsxd rdi, esi\nmovsx edi, byte ptr [rbx+rdi]\nlea r8d, [rdi-41h]\ncmp r8d, esi\njz short loc_16A0\nsub edi, 61h ; 'a'\ncmp esi, edi\njz short loc_16A0\nloc_1671:\nadd edx, 6\ncmp ecx, edx\njle short loc_168D\nmovsxd rcx, edx\nmovsx ecx, byte ptr [rbx+rcx]\nlea esi, [rcx-41h]\ncmp esi, edx\njz short loc_16A8\nsub ecx, 61h ; 'a'\ncmp ecx, edx\njz short loc_16A8\nloc_168D:\npop rbx\nretn\nloc_1690:\nadd eax, 1\njmp loc_15B3\nloc_16A0:\nadd eax, 1\njmp short loc_1671\nloc_16A8:\nadd eax, 1\npop rbx\nretn\nloc_16B0:\nadd eax, 1\njmp loc_15DD\nloc_16C0:\nadd eax, 1\njmp loc_1607\nloc_16D0:\nadd eax, 1\njmp loc_162D\nloc_16E0:\nadd eax, 1\njmp loc_1653\nloc_16F0:\nxor eax, eax\npop rbx\nretn\nloc_16F4:\npxor xmm5, xmm5\nxor edi, edi\nxor edx, edx\nxor eax, eax\njmp loc_140E", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(const char *a1)\n{\n int v2; // eax\n int v3; // ecx\n const __m128i *v4; // rax\n __m128i si128; // xmm11\n __m128i v6; // xmm10\n __m128i v7; // xmm4\n __m128i v8; // xmm9\n __m128i v9; // xmm8\n __m128i v10; // xmm0\n __m128i v11; // xmm7\n __m128i v12; // xmm2\n __m128i v13; // xmm3\n __m128i v14; // xmm12\n __m128i v15; // xmm13\n __m128i v16; // xmm1\n __m128i v17; // xmm0\n __m128i v18; // xmm2\n __m128i v19; // xmm14\n __m128i v20; // xmm6\n __m128i v21; // xmm1\n __m128i v22; // xmm2\n __m128i v23; // xmm0\n unsigned int v24; // edi\n __m128i v25; // xmm0\n __m128i v26; // xmm5\n signed int v27; // edx\n __int64 result; // rax\n unsigned int v29; // esi\n __m128i v30; // xmm2\n __m128i v31; // xmm9\n __m128i v32; // xmm4\n __m128i v33; // xmm13\n __m128i v34; // xmm11\n __m128i v35; // xmm1\n __m128i v36; // xmm0\n __m128i v37; // xmm12\n __m128i v38; // xmm2\n __m128i v39; // xmm10\n __m128i v40; // xmm3\n __m128i v41; // xmm8\n __m128i v42; // xmm1\n __m128i v43; // xmm0\n __m128i v44; // xmm2\n __m128i v45; // xmm10\n __m128i v46; // xmm6\n __m128i v47; // xmm0\n __m128i v48; // xmm2\n __m128i v49; // xmm0\n int v50; // esi\n int v51; // esi\n int v52; // edi\n int v53; // esi\n int v54; // edi\n int v55; // esi\n int v56; // edi\n int v57; // esi\n int v58; // edi\n int v59; // esi\n int v60; // edi\n int v61; // edx\n int v62; // ecx\n\n v2 = strlen(a1);\n if ( v2 <= 0 )\n return 0LL;\n v3 = v2;\n if ( (unsigned int)(v2 - 1) <= 0xE )\n {\n v26 = 0LL;\n v24 = 0;\n v27 = 0;\n result = 0LL;\n }\n else\n {\n v4 = (const __m128i *)a1;\n si128 = _mm_load_si128((const __m128i *)&xmmword_2080);\n v6 = _mm_load_si128((const __m128i *)&xmmword_20D0);\n v7 = 0LL;\n v8 = _mm_load_si128((const __m128i *)&xmmword_20E0);\n v9 = _mm_load_si128((const __m128i *)&xmmword_20F0);\n do\n {\n v10 = _mm_loadu_si128(v4);\n v11 = si128;\n ++v4;\n v12 = _mm_cmpgt_epi8((__m128i)0LL, v10);\n v13 = _mm_add_epi32(_mm_load_si128((const __m128i *)&xmmword_20A0), si128);\n v14 = _mm_add_epi32(_mm_load_si128((const __m128i *)&xmmword_20B0), si128);\n v15 = _mm_add_epi32(_mm_load_si128((const __m128i *)&xmmword_20C0), si128);\n si128 = _mm_add_epi32(si128, (__m128i)xmmword_2090);\n v16 = _mm_unpacklo_epi8(v10, v12);\n v17 = _mm_unpackhi_epi8(v10, v12);\n v18 = _mm_cmpgt_epi16((__m128i)0LL, v16);\n v19 = _mm_cmpgt_epi16((__m128i)0LL, v17);\n v20 = _mm_unpacklo_epi16(v16, v18);\n v21 = _mm_unpackhi_epi16(v16, v18);\n v22 = _mm_unpacklo_epi16(v17, v19);\n v23 = _mm_unpackhi_epi16(v17, v19);\n v7 = _mm_add_epi32(\n _mm_andnot_si128(\n _mm_and_si128(\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v6, v23), v15), (__m128i)0LL),\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v23, v8), v15), (__m128i)0LL)),\n v9),\n _mm_add_epi32(\n _mm_andnot_si128(\n _mm_and_si128(\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v6, v22), v14), (__m128i)0LL),\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v22, v8), v14), (__m128i)0LL)),\n v9),\n _mm_add_epi32(\n _mm_andnot_si128(\n _mm_and_si128(\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v6, v21), v13), (__m128i)0LL),\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(v13, _mm_add_epi32(v21, v8)), (__m128i)0LL)),\n v9),\n _mm_add_epi32(\n _mm_andnot_si128(\n _mm_and_si128(\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v6, v20), v11), (__m128i)0LL),\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v20, v8), v11), (__m128i)0LL)),\n v9),\n v7))));\n }\n while ( &a1[16 * ((unsigned int)v3 >> 4)] != (const char *)v4 );\n v24 = v3 & 0x7FFFFFF0;\n v25 = _mm_add_epi32(_mm_srli_si128(v7, 8), v7);\n v26 = _mm_add_epi32(v7, _mm_srli_si128(v7, 8));\n v27 = v3 & 0xFFFFFFF0;\n result = (unsigned int)_mm_cvtsi128_si32(_mm_add_epi32(v25, _mm_srli_si128(v25, 4)));\n if ( (v3 & 0xF) == 0 )\n return result;\n }\n v29 = v3 - v24;\n if ( v3 - v24 - 1 <= 6 )\n goto LABEL_8;\n v30 = _mm_loadl_epi64((const __m128i *)&a1[v24]);\n v31 = _mm_unpacklo_epi32(_mm_cvtsi32_si128(v27), _mm_cvtsi32_si128(v27 + 1));\n v32 = _mm_loadl_epi64((const __m128i *)&xmmword_20E0);\n v33 = _mm_add_epi32(_mm_loadl_epi64((const __m128i *)&qword_2100), v31);\n v34 = _mm_add_epi32(_mm_loadl_epi64((const __m128i *)&qword_2108), v31);\n v35 = _mm_cmpgt_epi8((__m128i)0LL, v30);\n v36 = v30;\n v37 = _mm_add_epi32(_mm_loadl_epi64((const __m128i *)&xmmword_20A0), v31);\n v38 = _mm_shuffle_epi32(_mm_unpacklo_epi8(v30, v35), 78);\n v39 = _mm_unpacklo_epi8(v36, v35);\n v40 = _mm_cmpgt_epi16((__m128i)0LL, v39);\n v41 = _mm_unpacklo_epi16(v38, _mm_cmpgt_epi16((__m128i)0LL, v38));\n v42 = _mm_loadl_epi64((const __m128i *)&xmmword_20D0);\n v43 = _mm_shuffle_epi32(_mm_unpacklo_epi16(v39, v40), 78);\n v44 = _mm_shuffle_epi32(v41, 78);\n v45 = _mm_unpacklo_epi16(v39, v40);\n v46 = _mm_and_si128(\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v42, v43), v33), (__m128i)0LL),\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v43, v32), v33), (__m128i)0LL));\n v47 = _mm_and_si128(\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v42, v44), v34), (__m128i)0LL),\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v44, v32), v34), (__m128i)0LL));\n v48 = _mm_loadl_epi64((const __m128i *)&xmmword_20F0);\n v49 = _mm_add_epi32(\n _mm_andnot_si128(v47, v48),\n _mm_add_epi32(\n _mm_andnot_si128(\n _mm_and_si128(\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v42, v41), v37), (__m128i)0LL),\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v41, v32), v37), (__m128i)0LL)),\n v48),\n _mm_add_epi32(\n _mm_andnot_si128(v46, v48),\n _mm_add_epi32(\n v26,\n _mm_andnot_si128(\n _mm_and_si128(\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v42, v45), v31), (__m128i)0LL),\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v32, v45), v31), (__m128i)0LL)),\n v48)))));\n result = (unsigned int)(_mm_cvtsi128_si32(v49) + _mm_cvtsi128_si32(_mm_shuffle_epi32(v49, 229)));\n v27 += v29 & 0xFFFFFFF8;\n if ( (v29 & 7) != 0 )\n {\nLABEL_8:\n v50 = a1[v27];\n if ( v50 - 65 == v27 || v50 - 97 == v27 )\n result = (unsigned int)(result + 1);\n v51 = v27 + 1;\n if ( v27 + 1 < v3 )\n {\n v52 = a1[v51];\n if ( v51 == v52 - 65 || v51 == v52 - 97 )\n result = (unsigned int)(result + 1);\n v53 = v27 + 2;\n if ( v3 > v27 + 2 )\n {\n v54 = a1[v53];\n if ( v53 == v54 - 65 || v53 == v54 - 97 )\n result = (unsigned int)(result + 1);\n v55 = v27 + 3;\n if ( v3 > v27 + 3 )\n {\n v56 = a1[v55];\n if ( v56 - 65 == v55 || v56 - 97 == v55 )\n result = (unsigned int)(result + 1);\n v57 = v27 + 4;\n if ( v3 > v27 + 4 )\n {\n v58 = a1[v57];\n if ( v57 == v58 - 65 || v57 == v58 - 97 )\n result = (unsigned int)(result + 1);\n v59 = v27 + 5;\n if ( v3 > v27 + 5 )\n {\n v60 = a1[v59];\n if ( v60 - 65 == v59 || v59 == v60 - 97 )\n result = (unsigned int)(result + 1);\n v61 = v27 + 6;\n if ( v3 > v61 )\n {\n v62 = a1[v61];\n if ( v62 - 65 == v61 || v62 - 97 == v61 )\n return (unsigned int)(result + 1);\n }\n }\n }\n }\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(const char *a1) {\n int v2;\n int v3;\n const __m128i *v4;\n __m128i si128;\n __m128i v6;\n __m128i v7;\n __m128i v8;\n __m128i v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n __m128i v15;\n __m128i v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n __m128i v20;\n __m128i v21;\n __m128i v22;\n __m128i v23;\n unsigned int v24;\n __m128i v25;\n __m128i v26;\n signed int v27;\n long long result;\n unsigned int v29;\n __m128i v30;\n __m128i v31;\n __m128i v32;\n __m128i v33;\n __m128i v34;\n __m128i v35;\n __m128i v36;\n __m128i v37;\n __m128i v38;\n __m128i v39;\n __m128i v40;\n __m128i v41;\n __m128i v42;\n __m128i v43;\n __m128i v44;\n __m128i v45;\n __m128i v46;\n __m128i v47;\n __m128i v48;\n __m128i v49;\n int v50;\n int v51;\n int v52;\n int v53;\n int v54;\n int v55;\n int v56;\n int v57;\n int v58;\n int v59;\n int v60;\n int v61;\n int v62;\n v2 = strlen(a1);\n if (v2 <= 0) return 0LL;\n v3 = v2;\n if ((unsigned int)(v2 - 1) <= 14) {\n v26 = 0LL;\n v24 = 0;\n v27 = 0;\n result = 0LL;\n } else {\n v4 = (const __m128i *)a1;\n si128 = _mm_load_si128((const __m128i *)&xmmword_2080);\n v6 = _mm_load_si128((const __m128i *)&xmmword_20D0);\n v7 = 0LL;\n v8 = _mm_load_si128((const __m128i *)&xmmword_20E0);\n v9 = _mm_load_si128((const __m128i *)&xmmword_20F0);\n do {\n v10 = _mm_loadu_si128(v4);\n v11 = si128;\n ++v4;\n v12 = _mm_cmpgt_epi8((__m128i)0LL, v10);\n v13 =\n _mm_add_epi32(_mm_load_si128((const __m128i *)&xmmword_20A0), si128);\n v14 =\n _mm_add_epi32(_mm_load_si128((const __m128i *)&xmmword_20B0), si128);\n v15 =\n _mm_add_epi32(_mm_load_si128((const __m128i *)&xmmword_20C0), si128);\n si128 = _mm_add_epi32(si128, (__m128i)xmmword_2090);\n v16 = _mm_unpacklo_epi8(v10, v12);\n v17 = _mm_unpackhi_epi8(v10, v12);\n v18 = _mm_cmpgt_epi16((__m128i)0LL, v16);\n v19 = _mm_cmpgt_epi16((__m128i)0LL, v17);\n v20 = _mm_unpacklo_epi16(v16, v18);\n v21 = _mm_unpackhi_epi16(v16, v18);\n v22 = _mm_unpacklo_epi16(v17, v19);\n v23 = _mm_unpackhi_epi16(v17, v19);\n v7 = _mm_add_epi32(\n _mm_andnot_si128(\n _mm_and_si128(\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v6, v23), v15),\n (__m128i)0LL),\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v23, v8), v15),\n (__m128i)0LL)),\n v9),\n _mm_add_epi32(\n _mm_andnot_si128(\n _mm_and_si128(\n _mm_cmpeq_epi32(\n _mm_cmpeq_epi32(_mm_add_epi32(v6, v22), v14),\n (__m128i)0LL),\n _mm_cmpeq_epi32(\n _mm_cmpeq_epi32(_mm_add_epi32(v22, v8), v14),\n (__m128i)0LL)),\n v9),\n _mm_add_epi32(\n _mm_andnot_si128(\n _mm_and_si128(\n _mm_cmpeq_epi32(\n _mm_cmpeq_epi32(_mm_add_epi32(v6, v21), v13),\n (__m128i)0LL),\n _mm_cmpeq_epi32(\n _mm_cmpeq_epi32(v13, _mm_add_epi32(v21, v8)),\n (__m128i)0LL)),\n v9),\n _mm_add_epi32(\n _mm_andnot_si128(\n _mm_and_si128(\n _mm_cmpeq_epi32(\n _mm_cmpeq_epi32(_mm_add_epi32(v6, v20), v11),\n (__m128i)0LL),\n _mm_cmpeq_epi32(\n _mm_cmpeq_epi32(_mm_add_epi32(v20, v8), v11),\n (__m128i)0LL)),\n v9),\n v7))));\n } while (&a1[16 * ((unsigned int)v3 >> 4)] != (const char *)v4);\n v24 = v3 & 2147483632;\n v25 = _mm_add_epi32(_mm_srli_si128(v7, 8), v7);\n v26 = _mm_add_epi32(v7, _mm_srli_si128(v7, 8));\n v27 = v3 & 4294967280;\n result = (unsigned int)_mm_cvtsi128_si32(\n _mm_add_epi32(v25, _mm_srli_si128(v25, 4)));\n if ((v3 & 15) == 0) return result;\n }\n v29 = v3 - v24;\n if (v3 - v24 - 1 <= 6) goto LABEL_8;\n v30 = _mm_loadl_epi64((const __m128i *)&a1[v24]);\n v31 = _mm_unpacklo_epi32(_mm_cvtsi32_si128(v27), _mm_cvtsi32_si128(v27 + 1));\n v32 = _mm_loadl_epi64((const __m128i *)&xmmword_20E0);\n v33 = _mm_add_epi32(_mm_loadl_epi64((const __m128i *)&qword_2100), v31);\n v34 = _mm_add_epi32(_mm_loadl_epi64((const __m128i *)&qword_2108), v31);\n v35 = _mm_cmpgt_epi8((__m128i)0LL, v30);\n v36 = v30;\n v37 = _mm_add_epi32(_mm_loadl_epi64((const __m128i *)&xmmword_20A0), v31);\n v38 = _mm_shuffle_epi32(_mm_unpacklo_epi8(v30, v35), 78);\n v39 = _mm_unpacklo_epi8(v36, v35);\n v40 = _mm_cmpgt_epi16((__m128i)0LL, v39);\n v41 = _mm_unpacklo_epi16(v38, _mm_cmpgt_epi16((__m128i)0LL, v38));\n v42 = _mm_loadl_epi64((const __m128i *)&xmmword_20D0);\n v43 = _mm_shuffle_epi32(_mm_unpacklo_epi16(v39, v40), 78);\n v44 = _mm_shuffle_epi32(v41, 78);\n v45 = _mm_unpacklo_epi16(v39, v40);\n v46 = _mm_and_si128(\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v42, v43), v33),\n (__m128i)0LL),\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v43, v32), v33),\n (__m128i)0LL));\n v47 = _mm_and_si128(\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v42, v44), v34),\n (__m128i)0LL),\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v44, v32), v34),\n (__m128i)0LL));\n v48 = _mm_loadl_epi64((const __m128i *)&xmmword_20F0);\n v49 = _mm_add_epi32(\n _mm_andnot_si128(v47, v48),\n _mm_add_epi32(\n _mm_andnot_si128(\n _mm_and_si128(\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v42, v41), v37),\n (__m128i)0LL),\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v41, v32), v37),\n (__m128i)0LL)),\n v48),\n _mm_add_epi32(\n _mm_andnot_si128(v46, v48),\n _mm_add_epi32(\n v26,\n _mm_andnot_si128(\n _mm_and_si128(\n _mm_cmpeq_epi32(\n _mm_cmpeq_epi32(_mm_add_epi32(v42, v45), v31),\n (__m128i)0LL),\n _mm_cmpeq_epi32(\n _mm_cmpeq_epi32(_mm_add_epi32(v32, v45), v31),\n (__m128i)0LL)),\n v48)))));\n result = (unsigned int)(_mm_cvtsi128_si32(v49) +\n _mm_cvtsi128_si32(_mm_shuffle_epi32(v49, 229)));\n v27 += v29 & 4294967288;\n if ((v29 & 7) != 0) {\n LABEL_8:\n v50 = a1[v27];\n if (v50 - 65 == v27 || v50 - 97 == v27) result = (unsigned int)(result + 1);\n v51 = v27 + 1;\n if (v27 + 1 < v3) {\n v52 = a1[v51];\n if (v51 == v52 - 65 || v51 == v52 - 97)\n result = (unsigned int)(result + 1);\n v53 = v27 + 2;\n if (v3 > v27 + 2) {\n v54 = a1[v53];\n if (v53 == v54 - 65 || v53 == v54 - 97)\n result = (unsigned int)(result + 1);\n v55 = v27 + 3;\n if (v3 > v27 + 3) {\n v56 = a1[v55];\n if (v56 - 65 == v55 || v56 - 97 == v55)\n result = (unsigned int)(result + 1);\n v57 = v27 + 4;\n if (v3 > v27 + 4) {\n v58 = a1[v57];\n if (v57 == v58 - 65 || v57 == v58 - 97)\n result = (unsigned int)(result + 1);\n v59 = v27 + 5;\n if (v3 > v27 + 5) {\n v60 = a1[v59];\n if (v60 - 65 == v59 || v59 == v60 - 97)\n result = (unsigned int)(result + 1);\n v61 = v27 + 6;\n if (v3 > v61) {\n v62 = a1[v61];\n if (v62 - 65 == v61 || v62 - 97 == v61)\n return (unsigned int)(result + 1);\n }\n }\n }\n }\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v2;\n int v3;\n const __m128i *v4;\n __m128i si128;\n __m128i v6;\n __m128i v7;\n __m128i v8;\n __m128i v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n __m128i v15;\n __m128i v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n __m128i v20;\n __m128i v21;\n __m128i v22;\n __m128i v23;\n unsigned int v24;\n __m128i v25;\n __m128i v26;\n signed int v27;\n long long result;\n unsigned int v29;\n __m128i v30;\n __m128i v31;\n __m128i v32;\n __m128i v33;\n __m128i v34;\n __m128i v35;\n __m128i v36;\n __m128i v37;\n __m128i v38;\n __m128i v39;\n __m128i v40;\n __m128i v41;\n __m128i v42;\n __m128i v43;\n __m128i v44;\n __m128i v45;\n __m128i v46;\n __m128i v47;\n __m128i v48;\n __m128i v49;\n int v50;\n int v51;\n int v52;\n int v53;\n int v54;\n int v55;\n int v56;\n int v57;\n int v58;\n int v59;\n int v60;\n int v61;\n int v62;\n v2 = strlen(a1);\n if (v2 <= 0) return 0LL;\n v3 = v2;\n if ((unsigned int)(v2 - 1) <= 14) {\n v26 = 0LL;\n v24 = 0;\n v27 = 0;\n result = 0LL;\n } else {\n v4 = (const __m128i *)a1;\n si128 = _mm_load_si128((const __m128i *)&xmmword_2080);\n v6 = _mm_load_si128((const __m128i *)&xmmword_20D0);\n v7 = 0LL;\n v8 = _mm_load_si128((const __m128i *)&xmmword_20E0);\n v9 = _mm_load_si128((const __m128i *)&xmmword_20F0);\n do {\n v10 = _mm_loadu_si128(v4);\n v11 = si128;\n ++v4;\n v12 = _mm_cmpgt_epi8((__m128i)0LL, v10);\n v13 =\n _mm_add_epi32(_mm_load_si128((const __m128i *)&xmmword_20A0), si128);\n v14 =\n _mm_add_epi32(_mm_load_si128((const __m128i *)&xmmword_20B0), si128);\n v15 =\n _mm_add_epi32(_mm_load_si128((const __m128i *)&xmmword_20C0), si128);\n si128 = _mm_add_epi32(si128, (__m128i)xmmword_2090);\n v16 = _mm_unpacklo_epi8(v10, v12);\n v17 = _mm_unpackhi_epi8(v10, v12);\n v18 = _mm_cmpgt_epi16((__m128i)0LL, v16);\n v19 = _mm_cmpgt_epi16((__m128i)0LL, v17);\n v20 = _mm_unpacklo_epi16(v16, v18);\n v21 = _mm_unpackhi_epi16(v16, v18);\n v22 = _mm_unpacklo_epi16(v17, v19);\n v23 = _mm_unpackhi_epi16(v17, v19);\n v7 = _mm_add_epi32(\n _mm_andnot_si128(\n _mm_and_si128(\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v6, v23), v15),\n (__m128i)0LL),\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v23, v8), v15),\n (__m128i)0LL)),\n v9),\n _mm_add_epi32(\n _mm_andnot_si128(\n _mm_and_si128(\n _mm_cmpeq_epi32(\n _mm_cmpeq_epi32(_mm_add_epi32(v6, v22), v14),\n (__m128i)0LL),\n _mm_cmpeq_epi32(\n _mm_cmpeq_epi32(_mm_add_epi32(v22, v8), v14),\n (__m128i)0LL)),\n v9),\n _mm_add_epi32(\n _mm_andnot_si128(\n _mm_and_si128(\n _mm_cmpeq_epi32(\n _mm_cmpeq_epi32(_mm_add_epi32(v6, v21), v13),\n (__m128i)0LL),\n _mm_cmpeq_epi32(\n _mm_cmpeq_epi32(v13, _mm_add_epi32(v21, v8)),\n (__m128i)0LL)),\n v9),\n _mm_add_epi32(\n _mm_andnot_si128(\n _mm_and_si128(\n _mm_cmpeq_epi32(\n _mm_cmpeq_epi32(_mm_add_epi32(v6, v20), v11),\n (__m128i)0LL),\n _mm_cmpeq_epi32(\n _mm_cmpeq_epi32(_mm_add_epi32(v20, v8), v11),\n (__m128i)0LL)),\n v9),\n v7))));\n } while (&a1[16 * ((unsigned int)v3 >> 4)] != (const char *)v4);\n v24 = v3 & 2147483632;\n v25 = _mm_add_epi32(_mm_srli_si128(v7, 8), v7);\n v26 = _mm_add_epi32(v7, _mm_srli_si128(v7, 8));\n v27 = v3 & 4294967280;\n result = (unsigned int)_mm_cvtsi128_si32(\n _mm_add_epi32(v25, _mm_srli_si128(v25, 4)));\n if ((v3 & 15) == 0) return result;\n }\n v29 = v3 - v24;\n if (v3 - v24 - 1 <= 6) goto LABEL_8;\n v30 = _mm_loadl_epi64((const __m128i *)&a1[v24]);\n v31 = _mm_unpacklo_epi32(_mm_cvtsi32_si128(v27), _mm_cvtsi32_si128(v27 + 1));\n v32 = _mm_loadl_epi64((const __m128i *)&xmmword_20E0);\n v33 = _mm_add_epi32(_mm_loadl_epi64((const __m128i *)&qword_2100), v31);\n v34 = _mm_add_epi32(_mm_loadl_epi64((const __m128i *)&qword_2108), v31);\n v35 = _mm_cmpgt_epi8((__m128i)0LL, v30);\n v36 = v30;\n v37 = _mm_add_epi32(_mm_loadl_epi64((const __m128i *)&xmmword_20A0), v31);\n v38 = _mm_shuffle_epi32(_mm_unpacklo_epi8(v30, v35), 78);\n v39 = _mm_unpacklo_epi8(v36, v35);\n v40 = _mm_cmpgt_epi16((__m128i)0LL, v39);\n v41 = _mm_unpacklo_epi16(v38, _mm_cmpgt_epi16((__m128i)0LL, v38));\n v42 = _mm_loadl_epi64((const __m128i *)&xmmword_20D0);\n v43 = _mm_shuffle_epi32(_mm_unpacklo_epi16(v39, v40), 78);\n v44 = _mm_shuffle_epi32(v41, 78);\n v45 = _mm_unpacklo_epi16(v39, v40);\n v46 = _mm_and_si128(\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v42, v43), v33),\n (__m128i)0LL),\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v43, v32), v33),\n (__m128i)0LL));\n v47 = _mm_and_si128(\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v42, v44), v34),\n (__m128i)0LL),\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v44, v32), v34),\n (__m128i)0LL));\n v48 = _mm_loadl_epi64((const __m128i *)&xmmword_20F0);\n v49 = _mm_add_epi32(\n _mm_andnot_si128(v47, v48),\n _mm_add_epi32(\n _mm_andnot_si128(\n _mm_and_si128(\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v42, v41), v37),\n (__m128i)0LL),\n _mm_cmpeq_epi32(_mm_cmpeq_epi32(_mm_add_epi32(v41, v32), v37),\n (__m128i)0LL)),\n v48),\n _mm_add_epi32(\n _mm_andnot_si128(v46, v48),\n _mm_add_epi32(\n v26,\n _mm_andnot_si128(\n _mm_and_si128(\n _mm_cmpeq_epi32(\n _mm_cmpeq_epi32(_mm_add_epi32(v42, v45), v31),\n (__m128i)0LL),\n _mm_cmpeq_epi32(\n _mm_cmpeq_epi32(_mm_add_epi32(v32, v45), v31),\n (__m128i)0LL)),\n v48)))));\n result = (unsigned int)(_mm_cvtsi128_si32(v49) +\n _mm_cvtsi128_si32(_mm_shuffle_epi32(v49, 229)));\n v27 += v29 & 4294967288;\n if ((v29 & 7) != 0) {\n LABEL_8:\n v50 = a1[v27];\n if (v50 - 65 == v27 || v50 - 97 == v27) result = (unsigned int)(result + 1);\n v51 = v27 + 1;\n if (v27 + 1 < v3) {\n v52 = a1[v51];\n if (v51 == v52 - 65 || v51 == v52 - 97)\n result = (unsigned int)(result + 1);\n v53 = v27 + 2;\n if (v3 > v27 + 2) {\n v54 = a1[v53];\n if (v53 == v54 - 65 || v53 == v54 - 97)\n result = (unsigned int)(result + 1);\n v55 = v27 + 3;\n if (v3 > v27 + 3) {\n v56 = a1[v55];\n if (v56 - 65 == v55 || v56 - 97 == v55)\n result = (unsigned int)(result + 1);\n v57 = v27 + 4;\n if (v3 > v27 + 4) {\n v58 = a1[v57];\n if (v57 == v58 - 65 || v57 == v58 - 97)\n result = (unsigned int)(result + 1);\n v59 = v27 + 5;\n if (v3 > v27 + 5) {\n v60 = a1[v59];\n if (v60 - 65 == v59 || v59 == v60 - 97)\n result = (unsigned int)(result + 1);\n v61 = v27 + 6;\n if (v3 > v61) {\n v62 = a1[v61];\n if (v62 - 65 == v61 || v62 - 97 == v61)\n return (unsigned int)(result + 1);\n }\n }\n }\n }\n }\n }\n }\n return result;\n}" + }, + { + "index": 166, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int A[], int N) {\n int evenPair = 0;\n for (int i = 0; i < N; i++) {\n for (int j = i + 1; j < N; j++) {\n if ((A[i] ^ A[j]) % 2 == 0) {\n evenPair++;\n }\n }\n }\n return evenPair;\n}", + "test": "int main() {\n\n int arr1[] = {5, 4, 7, 2, 1};\n\n assert(func0(arr1, 5) == 4);\n\n\n\n int arr2[] = {7, 2, 8, 1, 0, 5, 11};\n\n assert(func0(arr2, 7) == 9);\n\n\n\n int arr3[] = {1, 2, 3};\n\n assert(func0(arr3, 3) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11dc \nmov -0x8(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x4(%rbp)\njmp 11d0 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\nxor %edx,%eax\nand $0x1,%eax\ntest %eax,%eax\njne 11cc \naddl $0x1,-0xc(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1193 \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1188 \nmov -0xc(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_11DC\nloc_1188:\nmov eax, [rbp+var_8]\nadd eax, 1\nmov [rbp+var_4], eax\njmp short loc_11D0\nloc_1193:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nxor eax, edx\nand eax, 1\ntest eax, eax\njnz short loc_11CC\nadd [rbp+var_C], 1\nloc_11CC:\nadd [rbp+var_4], 1\nloc_11D0:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1193\nadd [rbp+var_8], 1\nloc_11DC:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+10h] [rbp-Ch]\n int i; // [rsp+14h] [rbp-8h]\n int j; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( (((unsigned __int8)*(_DWORD *)(4LL * i + a1) ^ (unsigned __int8)*(_DWORD *)(4LL * j + a1)) & 1) == 0 )\n ++v3;\n }\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_11DC\nloc_1188:\nmov eax, [rbp+var_8]\nadd eax, 1\nmov [rbp+var_4], eax\njmp short loc_11D0\nloc_1193:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nxor eax, edx\nand eax, 1\ntest eax, eax\njnz short loc_11CC\nadd [rbp+var_C], 1\nloc_11CC:\nadd [rbp+var_4], 1\nloc_11D0:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1193\nadd [rbp+var_8], 1\nloc_11DC:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+10h] [rbp-Ch]\n int i; // [rsp+14h] [rbp-8h]\n int j; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( (((unsigned __int8)*(_DWORD *)(4LL * i + a1) ^ (unsigned __int8)*(_DWORD *)(4LL * j + a1)) & 1) == 0 )\n ++v3;\n }\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n unsigned int v3;\n int i;\n int j;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if ((((unsigned char)*(uint32_t *)(4LL * i + a1) ^\n (unsigned char)*(uint32_t *)(4LL * j + a1)) &\n 1) == 0)\n ++v3;\n }\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n int j;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if ((((unsigned char)*(uint32_t *)(4LL * i + a1) ^\n (unsigned char)*(uint32_t *)(4LL * j + a1)) &\n 1) == 0)\n ++v3;\n }\n }\n return v3;\n}" + }, + { + "index": 166, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int A[], int N) {\n int evenPair = 0;\n for (int i = 0; i < N; i++) {\n for (int j = i + 1; j < N; j++) {\n if ((A[i] ^ A[j]) % 2 == 0) {\n evenPair++;\n }\n }\n }\n return evenPair;\n}", + "test": "int main() {\n\n int arr1[] = {5, 4, 7, 2, 1};\n\n assert(func0(arr1, 5) == 4);\n\n\n\n int arr2[] = {7, 2, 8, 1, 0, 5, 11};\n\n assert(func0(arr2, 7) == 9);\n\n\n\n int arr3[] = {1, 2, 3};\n\n assert(func0(arr3, 3) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11ae \nlea -0x1(%rsi),%r10d\nadd $0x1,%r10\nmov $0x1,%r9d\nmov $0x0,%ecx\ncmp %r10,%r9\nje 11b3 \nmov -0x4(%rdi,%r9,4),%r8d\nmov %r9,%rax\nmov %r8d,%edx\nxor (%rdi,%rax,4),%edx\nand $0x1,%edx\ncmp $0x1,%edx\nadc $0x0,%ecx\nadd $0x1,%rax\ncmp %eax,%esi\njg 1191 \nadd $0x1,%r9\njmp 1184 \nmov $0x0,%ecx\nmov %ecx,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11B6\nmov r10d, esi\nmovsxd r11, esi\nmov r9d, 1\nmov ecx, 0\njmp short loc_1187\nloc_1184:\nmov r9, rax\nloc_1187:\ncmp r9, r10\njz short loc_11BB\nmov r8d, [rdi+r9*4-4]\nmov rax, r9\nloc_1194:\nmov edx, r8d\nxor edx, [rdi+rax*4]\nand edx, 1\ncmp edx, 1\nadc ecx, 0\nadd rax, 1\ncmp esi, eax\njg short loc_1194\nlea rax, [r9+1]\ncmp r9, r11\njnz short loc_1184\njmp short loc_11BB\nloc_11B6:\nmov ecx, 0\nloc_11BB:\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // r9\n unsigned int v3; // ecx\n __int64 v4; // rax\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = 1LL;\n v3 = 0;\n while ( v2 != a2 )\n {\n v4 = v2;\n do\n v3 += ((*(_DWORD *)(a1 + 4 * v4++) ^ *(_DWORD *)(a1 + 4 * v2 - 4)) & 1) == 0;\n while ( a2 > (int)v4 );\n if ( v2 == a2 )\n break;\n ++v2;\n }\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11B6\nmov r10d, esi\nmovsxd r11, esi\nmov r9d, 1\nmov ecx, 0\njmp short loc_1187\nloc_1184:\nmov r9, rax\nloc_1187:\ncmp r9, r10\njz short loc_11BB\nmov r8d, [rdi+r9*4-4]\nmov rax, r9\nloc_1194:\nmov edx, r8d\nxor edx, [rdi+rax*4]\nand edx, 1\ncmp edx, 1\nadc ecx, 0\nadd rax, 1\ncmp esi, eax\njg short loc_1194\nlea rax, [r9+1]\ncmp r9, r11\njnz short loc_1184\njmp short loc_11BB\nloc_11B6:\nmov ecx, 0\nloc_11BB:\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n __int64 v2; // r9\n unsigned int v3; // ecx\n __int64 v4; // rax\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = 1LL;\n v3 = 0;\n while ( v2 != a2 )\n {\n v4 = v2;\n do\n v3 += ((*(_DWORD *)(a1 + 4 * v4++) ^ *(_DWORD *)(a1 + 4 * v2 - 4)) & 1) == 0;\n while ( a2 > (int)v4 );\n if ( v2 == a2 )\n break;\n ++v2;\n }\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n long long v4;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = 1LL;\n v3 = 0;\n while (v2 != a2) {\n v4 = v2;\n do\n v3 += ((*(uint32_t *)(a1 + 4 * v4++) ^ *(uint32_t *)(a1 + 4 * v2 - 4)) &\n 1) == 0;\n while (a2 > (int)v4);\n if (v2 == a2) break;\n ++v2;\n }\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n long long v4;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = 1LL;\n v3 = 0;\n while (v2 != a2) {\n v4 = v2;\n do\n v3 += ((*(uint32_t *)(a1 + 4 * v4++) ^ *(uint32_t *)(a1 + 4 * v2 - 4)) &\n 1) == 0;\n while (a2 > (int)v4);\n if (v2 == a2) break;\n ++v2;\n }\n }\n return v3;\n}" + }, + { + "index": 166, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int A[], int N) {\n int evenPair = 0;\n for (int i = 0; i < N; i++) {\n for (int j = i + 1; j < N; j++) {\n if ((A[i] ^ A[j]) % 2 == 0) {\n evenPair++;\n }\n }\n }\n return evenPair;\n}", + "test": "int main() {\n\n int arr1[] = {5, 4, 7, 2, 1};\n\n assert(func0(arr1, 5) == 4);\n\n\n\n int arr2[] = {7, 2, 8, 1, 0, 5, 11};\n\n assert(func0(arr2, 7) == 9);\n\n\n\n int arr3[] = {1, 2, 3};\n\n assert(func0(arr3, 3) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 13b4 \nlea -0x1(%rsi),%r10d\nmov $0x1,%r9d\nxor %r8d,%r8d\nadd $0x1,%r10\ncmp %r10,%r9\nje 13b0 \nxchg %ax,%ax\nmov -0x4(%rdi,%r9,4),%ecx\nmov %r9,%rax\nnopl 0x0(%rax,%rax,1)\nmov (%rdi,%rax,4),%edx\nxor %ecx,%edx\nand $0x1,%edx\ncmp $0x1,%edx\nadc $0x0,%r8d\nadd $0x1,%rax\ncmp %eax,%esi\njg 1390 \nadd $0x1,%r9\ncmp %r10,%r9\njne 1380 \nmov %r8d,%eax\nretq\nxor %r8d,%r8d\nmov %r8d,%eax\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_12E3\nmov r10d, esi\nmov r9d, 1\nxor ecx, ecx\ncmp esi, 1\njz short loc_12E0\nnop dword ptr [rax+rax+00000000h]\nloc_12B0:\nmov r8d, [rdi+r9*4-4]\nmov rax, r9\nnop dword ptr [rax+rax+00000000h]\nloc_12C0:\nmov edx, [rdi+rax*4]\nxor edx, r8d\nand edx, 1\ncmp edx, 1\nadc ecx, 0\nadd rax, 1\ncmp esi, eax\njg short loc_12C0\nadd r9, 1\ncmp r9, r10\njnz short loc_12B0\nloc_12E0:\nmov eax, ecx\nretn\nloc_12E3:\nxor ecx, ecx\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // r9\n unsigned int v3; // ecx\n __int64 v4; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 1LL;\n v3 = 0;\n if ( a2 != 1 )\n {\n do\n {\n v4 = v2;\n do\n v3 += (((unsigned __int8)*(_DWORD *)(a1 + 4 * v2 - 4) ^ (unsigned __int8)*(_DWORD *)(a1 + 4 * v4++)) & 1) == 0;\n while ( a2 > (int)v4 );\n ++v2;\n }\n while ( v2 != a2 );\n }\n return v3;\n}", + "ida_strip_asm": "sub_1290:\nendbr64\ntest esi, esi\njle short loc_12E3\nmov r10d, esi\nmov r9d, 1\nxor ecx, ecx\ncmp esi, 1\njz short loc_12E0\nnop dword ptr [rax+rax+00000000h]\nloc_12B0:\nmov r8d, [rdi+r9*4-4]\nmov rax, r9\nnop dword ptr [rax+rax+00000000h]\nloc_12C0:\nmov edx, [rdi+rax*4]\nxor edx, r8d\nand edx, 1\ncmp edx, 1\nadc ecx, 0\nadd rax, 1\ncmp esi, eax\njg short loc_12C0\nadd r9, 1\ncmp r9, r10\njnz short loc_12B0\nloc_12E0:\nmov eax, ecx\nretn\nloc_12E3:\nxor ecx, ecx\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1290(__int64 a1, int a2)\n{\n __int64 v2; // r9\n unsigned int v3; // ecx\n __int64 v4; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 1LL;\n v3 = 0;\n if ( a2 != 1 )\n {\n do\n {\n v4 = v2;\n do\n v3 += (((unsigned __int8)*(_DWORD *)(a1 + 4 * v2 - 4) ^ (unsigned __int8)*(_DWORD *)(a1 + 4 * v4++)) & 1) == 0;\n while ( a2 > (int)v4 );\n ++v2;\n }\n while ( v2 != a2 );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1290(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n long long v4;\n if (a2 <= 0) return 0LL;\n v2 = 1LL;\n v3 = 0;\n if (a2 != 1) {\n do {\n v4 = v2;\n do\n v3 += (((unsigned char)*(uint32_t *)(a1 + 4 * v2 - 4) ^\n (unsigned char)*(uint32_t *)(a1 + 4 * v4++)) &\n 1) == 0;\n while (a2 > (int)v4);\n ++v2;\n } while (v2 != a2);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n long long v4;\n if (a2 <= 0) return 0LL;\n v2 = 1LL;\n v3 = 0;\n if (a2 != 1) {\n do {\n v4 = v2;\n do\n v3 += (((unsigned char)*(uint32_t *)(a1 + 4 * v2 - 4) ^\n (unsigned char)*(uint32_t *)(a1 + 4 * v4++)) &\n 1) == 0;\n while (a2 > (int)v4);\n ++v2;\n } while (v2 != a2);\n }\n return v3;\n}" + }, + { + "index": 167, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int count = 0;\n if (n && !(n & (n - 1))) {\n return n;\n }\n while (n != 0) {\n n >>= 1;\n count += 1;\n }\n return 1 << count;\n}", + "test": "int main() {\n\n assert(func0(0) == 1);\n\n assert(func0(5) == 8);\n\n assert(func0(17) == 32);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmovl $0x0,-0x4(%rbp)\ncmpl $0x0,-0x14(%rbp)\nje 117a \nmov -0x14(%rbp),%eax\nsub $0x1,%eax\nand -0x14(%rbp),%eax\ntest %eax,%eax\njne 117a \nmov -0x14(%rbp),%eax\njmp 118e \nsarl -0x14(%rbp)\naddl $0x1,-0x4(%rbp)\ncmpl $0x0,-0x14(%rbp)\njne 1173 \nmov -0x4(%rbp),%eax\nmov $0x1,%edx\nmov %eax,%ecx\nshl %cl,%edx\nmov %edx,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_4], 0\ncmp [rbp+var_14], 0\njz short loc_117A\nmov eax, [rbp+var_14]\nsub eax, 1\nand eax, [rbp+var_14]\ntest eax, eax\njnz short loc_117A\nmov eax, [rbp+var_14]\njmp short loc_118E\nloc_1173:\nsar [rbp+var_14], 1\nadd [rbp+var_4], 1\nloc_117A:\ncmp [rbp+var_14], 0\njnz short loc_1173\nmov eax, [rbp+var_4]\nmov edx, 1\nmov ecx, eax\nshl edx, cl\nmov eax, edx\nloc_118E:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1)\n{\n int v2; // [rsp+0h] [rbp-14h]\n char v3; // [rsp+10h] [rbp-4h]\n\n v2 = a1;\n v3 = 0;\n if ( a1 && (a1 & (a1 - 1)) == 0 )\n return a1;\n while ( v2 )\n {\n v2 >>= 1;\n ++v3;\n }\n return (unsigned int)(1 << v3);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_4], 0\ncmp [rbp+var_14], 0\njz short loc_117A\nmov eax, [rbp+var_14]\nsub eax, 1\nand eax, [rbp+var_14]\ntest eax, eax\njnz short loc_117A\nmov eax, [rbp+var_14]\njmp short loc_118E\nloc_1173:\nsar [rbp+var_14], 1\nadd [rbp+var_4], 1\nloc_117A:\ncmp [rbp+var_14], 0\njnz short loc_1173\nmov eax, [rbp+var_4]\nmov edx, 1\nmov ecx, eax\nshl edx, cl\nmov eax, edx\nloc_118E:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(unsigned int a1)\n{\n int v2; // [rsp+0h] [rbp-14h]\n char v3; // [rsp+10h] [rbp-4h]\n\n v2 = a1;\n v3 = 0;\n if ( a1 && (a1 & (a1 - 1)) == 0 )\n return a1;\n while ( v2 )\n {\n v2 >>= 1;\n ++v3;\n }\n return (unsigned int)(1 << v3);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(unsigned int a1) {\n int v2;\n char v3;\n v2 = a1;\n v3 = 0;\n if (a1 && (a1 & (a1 - 1)) == 0) return a1;\n while (v2) {\n v2 >>= 1;\n ++v3;\n }\n return (unsigned int)(1 << v3);\n}", + "ida_pseudo_norm": "long long func0(unsigned int a1) {\n int v2;\n char v3;\n v2 = a1;\n v3 = 0;\n if (a1 && (a1 & (a1 - 1)) == 0) return a1;\n while (v2) {\n v2 >>= 1;\n ++v3;\n }\n return (unsigned int)(1 << v3);\n}" + }, + { + "index": 167, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int count = 0;\n if (n && !(n & (n - 1))) {\n return n;\n }\n while (n != 0) {\n n >>= 1;\n count += 1;\n }\n return 1 << count;\n}", + "test": "int main() {\n\n assert(func0(0) == 1);\n\n assert(func0(5) == 8);\n\n assert(func0(17) == 32);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\nje 1166 \nlea -0x1(%rdi),%edx\nmov %edi,%eax\ntest %edi,%edx\nje 116f \nmov $0x0,%edi\nadd $0x1,%edi\nsar %eax\njne 115f \nmov $0x1,%eax\nmov %edi,%ecx\nshl %cl,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njz short loc_1166\nlea edx, [rdi-1]\nmov eax, edi\ntest edx, edi\njz short locret_116F\nmov edi, 0\nloc_115F:\nadd edi, 1\nsar eax, 1\njnz short loc_115F\nloc_1166:\nmov eax, 1\nmov ecx, edi\nshl eax, cl\nlocret_116F:\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1)\n{\n __int64 result; // rax\n\n if ( a1 )\n {\n result = a1;\n if ( (a1 & (a1 - 1)) == 0 )\n return result;\n LOBYTE(a1) = 0;\n do\n {\n LOBYTE(a1) = a1 + 1;\n LODWORD(result) = (int)result >> 1;\n }\n while ( (_DWORD)result );\n }\n return (unsigned int)(1 << a1);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ntest edi, edi\njz short loc_1166\nlea edx, [rdi-1]\nmov eax, edi\ntest edx, edi\njz short locret_116F\nmov edi, 0\nloc_115F:\nadd edi, 1\nsar eax, 1\njnz short loc_115F\nloc_1166:\nmov eax, 1\nmov ecx, edi\nshl eax, cl\nlocret_116F:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(unsigned int a1)\n{\n __int64 result; // rax\n\n if ( a1 )\n {\n result = a1;\n if ( (a1 & (a1 - 1)) == 0 )\n return result;\n LOBYTE(a1) = 0;\n do\n {\n LOBYTE(a1) = a1 + 1;\n LODWORD(result) = (int)result >> 1;\n }\n while ( (_DWORD)result );\n }\n return (unsigned int)(1 << a1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(unsigned int a1) {\n long long result;\n if (a1) {\n result = a1;\n if ((a1 & (a1 - 1)) == 0) return result;\n LOBYTE(a1) = 0;\n do {\n LOBYTE(a1) = a1 + 1;\n LODWORD(result) = (int)result >> 1;\n } while ((uint32_t)result);\n }\n return (unsigned int)(1 << a1);\n}", + "ida_pseudo_norm": "long long func0(unsigned int a1) {\n long long result;\n if (a1) {\n result = a1;\n if ((a1 & (a1 - 1)) == 0) return result;\n LOBYTE(a1) = 0;\n do {\n LOBYTE(a1) = a1 + 1;\n LODWORD(result) = (int)result >> 1;\n } while ((uint32_t)result);\n }\n return (unsigned int)(1 << a1);\n}" + }, + { + "index": 168, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int a[], int n, int x) {\n int count = 0;\n for (int i = 0; i < n; i++) {\n if (a[i] == x) count++;\n }\n return count;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3};\n\n assert(func0(arr1, 3, 4) == 0);\n\n\n\n int arr2[] = {1, 2, 2, 3, 3, 3, 4};\n\n assert(func0(arr2, 7, 3) == 3);\n\n\n\n int arr3[] = {0, 1, 2, 3, 1, 2};\n\n assert(func0(arr3, 6, 1) == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11ae \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x20(%rbp)\njne 11aa \naddl $0x1,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 118b \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11AE\nloc_118B:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njnz short loc_11AA\nadd [rbp+var_8], 1\nloc_11AA:\nadd [rbp+var_4], 1\nloc_11AE:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_118B\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n unsigned int v4; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( a3 == *(_DWORD *)(4LL * i + a1) )\n ++v4;\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11AE\nloc_118B:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njnz short loc_11AA\nadd [rbp+var_8], 1\nloc_11AA:\nadd [rbp+var_4], 1\nloc_11AE:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_118B\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n unsigned int v4; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( a3 == *(_DWORD *)(4LL * i + a1) )\n ++v4;\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n unsigned int v4;\n int i;\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n if (a3 == *(uint32_t *)(4LL * i + a1)) ++v4;\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n unsigned int v4;\n int i;\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n if (a3 == *(uint32_t *)(4LL * i + a1)) ++v4;\n }\n return v4;\n}" + }, + { + "index": 168, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int a[], int n, int x) {\n int count = 0;\n for (int i = 0; i < n; i++) {\n if (a[i] == x) count++;\n }\n return count;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3};\n\n assert(func0(arr1, 3, 4) == 0);\n\n\n\n int arr2[] = {1, 2, 2, 3, 3, 3, 4};\n\n assert(func0(arr2, 7, 3) == 3);\n\n\n\n int arr3[] = {0, 1, 2, 3, 1, 2};\n\n assert(func0(arr3, 6, 1) == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1199 \nmov %rdi,%rax\nlea -0x1(%rsi),%ecx\nlea 0x4(%rdi,%rcx,4),%rdi\nmov $0x0,%ecx\ncmp %edx,(%rax)\nsete %sil\nmovzbl %sil,%esi\nadd %esi,%ecx\nadd $0x4,%rax\ncmp %rdi,%rax\njne 1181 \nmov %ecx,%eax\nretq\nmov $0x0,%ecx\njmp 1196 \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1198\nmov rax, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*4]\nmov ecx, 0\nloc_1180:\ncmp [rax], edx\nsetz sil\nmovzx esi, sil\nadd ecx, esi\nadd rax, 4\ncmp rax, rdi\njnz short loc_1180\nloc_1195:\nmov eax, ecx\nretn\nloc_1198:\nmov ecx, 0\njmp short loc_1195", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2, int a3)\n{\n _DWORD *v3; // rax\n _DWORD *v4; // rdi\n unsigned int v5; // ecx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n do\n v5 += *v3++ == a3;\n while ( v3 != v4 );\n }\n return v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_1198\nmov rax, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*4]\nmov ecx, 0\nloc_1180:\ncmp [rax], edx\nsetz sil\nmovzx esi, sil\nadd ecx, esi\nadd rax, 4\ncmp rax, rdi\njnz short loc_1180\nloc_1195:\nmov eax, ecx\nretn\nloc_1198:\nmov ecx, 0\njmp short loc_1195", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2, int a3)\n{\n _DWORD *v3; // rax\n _DWORD *v4; // rdi\n unsigned int v5; // ecx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n do\n v5 += *v3++ == a3;\n while ( v3 != v4 );\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2, int a3) {\n uint32_t *v3;\n uint32_t *v4;\n unsigned int v5;\n if (a2 <= 0) {\n return 0;\n } else {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n do\n v5 += *v3++ == a3;\n while (v3 != v4);\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2, int a3) {\n uint32_t *v3;\n uint32_t *v4;\n unsigned int v5;\n if (a2 <= 0) {\n return 0;\n } else {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n do\n v5 += *v3++ == a3;\n while (v3 != v4);\n }\n return v5;\n}" + }, + { + "index": 169, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n <= 2) {\n return n;\n }\n int a = 1;\n int b = 2;\n int c;\n for (int i = 3; i <= n; i++) {\n c = 2 * b + a;\n a = b;\n b = c;\n }\n return b;\n}", + "test": "int main() {\n\n assert(func0(4) == 12);\n\n assert(func0(7) == 169);\n\n assert(func0(8) == 408);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\ncmpl $0x2,-0x14(%rbp)\njg 115f \nmov -0x14(%rbp),%eax\njmp 119f \nmovl $0x1,-0x10(%rbp)\nmovl $0x2,-0xc(%rbp)\nmovl $0x3,-0x8(%rbp)\njmp 1194 \nmov -0xc(%rbp),%eax\nlea (%rax,%rax,1),%edx\nmov -0x10(%rbp),%eax\nadd %edx,%eax\nmov %eax,-0x4(%rbp)\nmov -0xc(%rbp),%eax\nmov %eax,-0x10(%rbp)\nmov -0x4(%rbp),%eax\nmov %eax,-0xc(%rbp)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x14(%rbp),%eax\njle 1176 \nmov -0xc(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\ncmp [rbp+var_14], 2\njg short loc_115F\nmov eax, [rbp+var_14]\njmp short loc_119F\nloc_115F:\nmov [rbp+var_10], 1\nmov [rbp+var_C], 2\nmov [rbp+var_8], 3\njmp short loc_1194\nloc_1176:\nmov eax, [rbp+var_C]\nlea edx, [rax+rax]\nmov eax, [rbp+var_10]\nadd eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_C]\nmov [rbp+var_10], eax\nmov eax, [rbp+var_4]\nmov [rbp+var_C], eax\nadd [rbp+var_8], 1\nloc_1194:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_14]\njle short loc_1176\nmov eax, [rbp+var_C]\nloc_119F:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v2; // [rsp+4h] [rbp-10h]\n unsigned int v3; // [rsp+8h] [rbp-Ch]\n int i; // [rsp+Ch] [rbp-8h]\n unsigned int v5; // [rsp+10h] [rbp-4h]\n\n if ( a1 <= 2 )\n return (unsigned int)a1;\n v2 = 1;\n v3 = 2;\n for ( i = 3; i <= a1; ++i )\n {\n v5 = 2 * v3 + v2;\n v2 = v3;\n v3 = v5;\n }\n return v3;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\ncmp [rbp+var_14], 2\njg short loc_115F\nmov eax, [rbp+var_14]\njmp short loc_119F\nloc_115F:\nmov [rbp+var_10], 1\nmov [rbp+var_C], 2\nmov [rbp+var_8], 3\njmp short loc_1194\nloc_1176:\nmov eax, [rbp+var_C]\nlea edx, [rax+rax]\nmov eax, [rbp+var_10]\nadd eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_C]\nmov [rbp+var_10], eax\nmov eax, [rbp+var_4]\nmov [rbp+var_C], eax\nadd [rbp+var_8], 1\nloc_1194:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_14]\njle short loc_1176\nmov eax, [rbp+var_C]\nloc_119F:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v2; // [rsp+4h] [rbp-10h]\n unsigned int v3; // [rsp+8h] [rbp-Ch]\n int i; // [rsp+Ch] [rbp-8h]\n unsigned int v5; // [rsp+10h] [rbp-4h]\n\n if ( a1 <= 2 )\n return (unsigned int)a1;\n v2 = 1;\n v3 = 2;\n for ( i = 3; i <= a1; ++i )\n {\n v5 = 2 * v3 + v2;\n v2 = v3;\n v3 = v5;\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v2;\n unsigned int v3;\n int i;\n unsigned int v5;\n if (a1 <= 2) return (unsigned int)a1;\n v2 = 1;\n v3 = 2;\n for (i = 3; i <= a1; ++i) {\n v5 = 2 * v3 + v2;\n v2 = v3;\n v3 = v5;\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v2;\n unsigned int v3;\n int i;\n unsigned int v5;\n if (a1 <= 2) return (unsigned int)a1;\n v2 = 1;\n v3 = 2;\n for (i = 3; i <= a1; ++i) {\n v5 = 2 * v3 + v2;\n v2 = v3;\n v3 = v5;\n }\n return v3;\n}" + }, + { + "index": 169, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n <= 2) {\n return n;\n }\n int a = 1;\n int b = 2;\n int c;\n for (int i = 3; i <= n; i++) {\n c = 2 * b + a;\n a = b;\n b = c;\n }\n return b;\n}", + "test": "int main() {\n\n assert(func0(4) == 12);\n\n assert(func0(7) == 169);\n\n assert(func0(8) == 408);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %edi,%eax\ncmp $0x2,%edi\njle 1174 \nadd $0x1,%edi\nmov $0x3,%edx\nmov $0x2,%eax\nmov $0x1,%ecx\nmov %eax,%esi\nlea (%rcx,%rax,2),%eax\nadd $0x1,%edx\nmov %esi,%ecx\ncmp %edi,%edx\njne 1166 \nretq\n", + "ida_asm": "func0:\nendbr64\nmov eax, edi\ncmp edi, 2\njle short locret_1174\nadd edi, 1\nmov edx, 3\nmov eax, 2\nmov ecx, 1\nloc_1166:\nmov esi, eax\nlea eax, [rcx+rax*2]\nadd edx, 1\nmov ecx, esi\ncmp edx, edi\njnz short loc_1166\nlocret_1174:\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n __int64 result; // rax\n int v2; // edi\n int v3; // edx\n int v4; // ecx\n int v5; // esi\n\n result = (unsigned int)a1;\n if ( a1 > 2 )\n {\n v2 = a1 + 1;\n v3 = 3;\n LODWORD(result) = 2;\n v4 = 1;\n do\n {\n v5 = result;\n result = (unsigned int)(v4 + 2 * result);\n ++v3;\n v4 = v5;\n }\n while ( v3 != v2 );\n }\n return result;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmov eax, edi\ncmp edi, 2\njle short locret_1174\nadd edi, 1\nmov edx, 3\nmov eax, 2\nmov ecx, 1\nloc_1166:\nmov esi, eax\nlea eax, [rcx+rax*2]\nadd edx, 1\nmov ecx, esi\ncmp edx, edi\njnz short loc_1166\nlocret_1174:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n __int64 result; // rax\n int v2; // edi\n int v3; // edx\n int v4; // ecx\n int v5; // esi\n\n result = (unsigned int)a1;\n if ( a1 > 2 )\n {\n v2 = a1 + 1;\n v3 = 3;\n LODWORD(result) = 2;\n v4 = 1;\n do\n {\n v5 = result;\n result = (unsigned int)(v4 + 2 * result);\n ++v3;\n v4 = v5;\n }\n while ( v3 != v2 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n long long result;\n int v2;\n int v3;\n int v4;\n int v5;\n result = (unsigned int)a1;\n if (a1 > 2) {\n v2 = a1 + 1;\n v3 = 3;\n LODWORD(result) = 2;\n v4 = 1;\n do {\n v5 = result;\n result = (unsigned int)(v4 + 2 * result);\n ++v3;\n v4 = v5;\n } while (v3 != v2);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n long long result;\n int v2;\n int v3;\n int v4;\n int v5;\n result = (unsigned int)a1;\n if (a1 > 2) {\n v2 = a1 + 1;\n v3 = 3;\n LODWORD(result) = 2;\n v4 = 1;\n do {\n v5 = result;\n result = (unsigned int)(v4 + 2 * result);\n ++v3;\n v4 = v5;\n } while (v3 != v2);\n }\n return result;\n}" + }, + { + "index": 170, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int list1[], int m, int n) {\n int sum_range = 0;\n for (int i = m; i <= n; i++) {\n sum_range += list1[i];\n }\n return sum_range;\n}", + "test": "int main() {\n\n int list1[] = {2, 1, 5, 6, 8, 3, 4, 9, 10, 11, 8, 12};\n\n assert(func0(list1, 8, 10) == 29);\n\n assert(func0(list1, 5, 7) == 16);\n\n assert(func0(list1, 7, 10) == 38);\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmovl $0x0,-0x8(%rbp)\nmov -0x1c(%rbp),%eax\nmov %eax,-0x4(%rbp)\njmp 11a7 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nadd %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x20(%rbp),%eax\njle 118a \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_8], 0\nmov eax, [rbp+var_1C]\nmov [rbp+var_4], eax\njmp short loc_11A7\nloc_118A:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_11A7:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_20]\njle short loc_118A\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n unsigned int v4; // [rsp+18h] [rbp-8h]\n\n v4 = 0;\n while ( a2 <= a3 )\n v4 += *(_DWORD *)(4LL * a2++ + a1);\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_8], 0\nmov eax, [rbp+var_1C]\nmov [rbp+var_4], eax\njmp short loc_11A7\nloc_118A:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_11A7:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_20]\njle short loc_118A\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n unsigned int v4; // [rsp+18h] [rbp-8h]\n\n v4 = 0;\n while ( a2 <= a3 )\n v4 += *(_DWORD *)(4LL * a2++ + a1);\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n unsigned int v4;\n v4 = 0;\n while (a2 <= a3) v4 += *(uint32_t *)(4LL * a2++ + a1);\n return v4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n unsigned int v4;\n v4 = 0;\n while (a2 <= a3) v4 += *(uint32_t *)(4LL * a2++ + a1);\n return v4;\n}" + }, + { + "index": 170, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int list1[], int m, int n) {\n int sum_range = 0;\n for (int i = m; i <= n; i++) {\n sum_range += list1[i];\n }\n return sum_range;\n}", + "test": "int main() {\n\n int list1[] = {2, 1, 5, 6, 8, 3, 4, 9, 10, 11, 8, 12};\n\n assert(func0(list1, 8, 10) == 29);\n\n assert(func0(list1, 5, 7) == 16);\n\n assert(func0(list1, 7, 10) == 38);\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ncmp %edx,%esi\njg 1195 \nmovslq %esi,%rcx\nlea (%rdi,%rcx,4),%rax\nsub %esi,%edx\nadd %rcx,%rdx\nlea 0x4(%rdi,%rdx,4),%rcx\nmov $0x0,%edx\nadd (%rax),%edx\nadd $0x4,%rax\ncmp %rcx,%rax\njne 1187 \nmov %edx,%eax\nretq\nmov $0x0,%edx\njmp 1192 \n", + "ida_asm": "func0:\nendbr64\ncmp esi, edx\njg short loc_1195\nmovsxd rcx, esi\nlea rax, [rdi+rcx*4]\nsub edx, esi\nadd rdx, rcx\nlea rcx, [rdi+rdx*4+4]\nmov edx, 0\nloc_1187:\nadd edx, [rax]\nadd rax, 4\ncmp rax, rcx\njnz short loc_1187\nloc_1192:\nmov eax, edx\nretn\nloc_1195:\nmov edx, 0\njmp short loc_1192", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n _DWORD *v3; // rax\n unsigned __int64 v4; // rcx\n unsigned int v5; // edx\n\n if ( a2 > a3 )\n {\n return 0;\n }\n else\n {\n v3 = (_DWORD *)(a1 + 4LL * a2);\n v4 = a1 + 4 * (a2 + (unsigned __int64)(unsigned int)(a3 - a2)) + 4;\n v5 = 0;\n do\n v5 += *v3++;\n while ( v3 != (_DWORD *)v4 );\n }\n return v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ncmp esi, edx\njg short loc_1195\nmovsxd rcx, esi\nlea rax, [rdi+rcx*4]\nsub edx, esi\nadd rdx, rcx\nlea rcx, [rdi+rdx*4+4]\nmov edx, 0\nloc_1187:\nadd edx, [rax]\nadd rax, 4\ncmp rax, rcx\njnz short loc_1187\nloc_1192:\nmov eax, edx\nretn\nloc_1195:\nmov edx, 0\njmp short loc_1192", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n _DWORD *v3; // rax\n unsigned __int64 v4; // rcx\n unsigned int v5; // edx\n\n if ( a2 > a3 )\n {\n return 0;\n }\n else\n {\n v3 = (_DWORD *)(a1 + 4LL * a2);\n v4 = a1 + 4 * (a2 + (unsigned __int64)(unsigned int)(a3 - a2)) + 4;\n v5 = 0;\n do\n v5 += *v3++;\n while ( v3 != (_DWORD *)v4 );\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n uint32_t *v3;\n unsigned long long v4;\n unsigned int v5;\n if (a2 > a3) {\n return 0;\n } else {\n v3 = (uint32_t *)(a1 + 4LL * a2);\n v4 = a1 + 4 * (a2 + (unsigned long long)(unsigned int)(a3 - a2)) + 4;\n v5 = 0;\n do\n v5 += *v3++;\n while (v3 != (uint32_t *)v4);\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n uint32_t *v3;\n unsigned long long v4;\n unsigned int v5;\n if (a2 > a3) {\n return 0;\n } else {\n v3 = (uint32_t *)(a1 + 4LL * a2);\n v4 = a1 + 4 * (a2 + (unsigned long long)(unsigned int)(a3 - a2)) + 4;\n v5 = 0;\n do\n v5 += *v3++;\n while (v3 != (uint32_t *)v4);\n }\n return v5;\n}" + }, + { + "index": 171, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(double a) {\n double perimeter = 5 * a;\n return perimeter;\n}", + "test": "int main() {\n\n assert(func0(5) == 25);\n\n assert(func0(10) == 50);\n\n assert(func0(15) == 75);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmovsd %xmm0,-0x18(%rbp)\nmovsd -0x18(%rbp),%xmm1\nmovsd 0xf15(%rip),%xmm0\nmulsd %xmm1,%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmovsd -0x8(%rbp),%xmm0\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmovsd [rbp+var_18], xmm0\nmovsd xmm1, [rbp+var_18]\nmovsd xmm0, cs:qword_2060\nmulsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "double __fastcall func0(double a1)\n{\n return 5.0 * a1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmovsd [rbp+var_18], xmm0\nmovsd xmm1, [rbp+var_18]\nmovsd xmm0, cs:qword_2060\nmulsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "double __fastcall sub_1149(double a1)\n{\n return 5.0 * a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1149(double a1) { return 5.0 * a1; }", + "ida_pseudo_norm": "double func0(double a1) { return 5.0 * a1; }" + }, + { + "index": 172, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char* s) {\n int count = 0;\n int i;\n int len = 0;\n while (s[len] != '\\0') {\n len++;\n }\n for (i = 0; i < len - 2; i++) {\n if (s[i] == 's' && s[i + 1] == 't' && s[i + 2] == 'd') {\n count++;\n }\n }\n return count;\n}", + "test": "int main() {\n\n assert(func0(\"letstdlenstdporstd\") == 3);\n\n assert(func0(\"truststdsolensporsd\") == 1);\n\n assert(func0(\"makestdsostdworthit\") == 2);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 1169 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 1165 \nmovl $0x0,-0x8(%rbp)\njmp 11d0 \nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x73,%al\njne 11cc \nmov -0x8(%rbp),%eax\ncltq\nlea 0x1(%rax),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x74,%al\njne 11cc \nmov -0x8(%rbp),%eax\ncltq\nlea 0x2(%rax),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x64,%al\njne 11cc \naddl $0x1,-0xc(%rbp)\naddl $0x1,-0x8(%rbp)\nmov -0x4(%rbp),%eax\nsub $0x2,%eax\ncmp %eax,-0x8(%rbp)\njl 1186 \nmov -0xc(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_C], 0\nmov [rbp+var_4], 0\njmp short loc_1169\nloc_1165:\nadd [rbp+var_4], 1\nloc_1169:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1165\nmov [rbp+var_8], 0\njmp short loc_11D0\nloc_1186:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 73h ; 's'\njnz short loc_11CC\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, [rax+1]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 74h ; 't'\njnz short loc_11CC\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, [rax+2]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 64h ; 'd'\njnz short loc_11CC\nadd [rbp+var_C], 1\nloc_11CC:\nadd [rbp+var_8], 1\nloc_11D0:\nmov eax, [rbp+var_4]\nsub eax, 2\ncmp [rbp+var_8], eax\njl short loc_1186\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1)\n{\n unsigned int v2; // [rsp+Ch] [rbp-Ch]\n int j; // [rsp+10h] [rbp-8h]\n int i; // [rsp+14h] [rbp-4h]\n\n v2 = 0;\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n ;\n for ( j = 0; j < i - 2; ++j )\n {\n if ( *(_BYTE *)(j + a1) == 115 && *(_BYTE *)(j + 1LL + a1) == 116 && *(_BYTE *)(j + 2LL + a1) == 100 )\n ++v2;\n }\n return v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_C], 0\nmov [rbp+var_4], 0\njmp short loc_1169\nloc_1165:\nadd [rbp+var_4], 1\nloc_1169:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1165\nmov [rbp+var_8], 0\njmp short loc_11D0\nloc_1186:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 73h ; 's'\njnz short loc_11CC\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, [rax+1]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 74h ; 't'\njnz short loc_11CC\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, [rax+2]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 64h ; 'd'\njnz short loc_11CC\nadd [rbp+var_C], 1\nloc_11CC:\nadd [rbp+var_8], 1\nloc_11D0:\nmov eax, [rbp+var_4]\nsub eax, 2\ncmp [rbp+var_8], eax\njl short loc_1186\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(__int64 a1)\n{\n unsigned int v2; // [rsp+Ch] [rbp-Ch]\n int j; // [rsp+10h] [rbp-8h]\n int i; // [rsp+14h] [rbp-4h]\n\n v2 = 0;\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n ;\n for ( j = 0; j < i - 2; ++j )\n {\n if ( *(_BYTE *)(j + a1) == 115 && *(_BYTE *)(j + 1LL + a1) == 116 && *(_BYTE *)(j + 2LL + a1) == 100 )\n ++v2;\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(long long a1) {\n unsigned int v2;\n int j;\n int i;\n v2 = 0;\n for (i = 0; *(uint8_t *)(i + a1); ++i)\n ;\n for (j = 0; j < i - 2; ++j) {\n if (*(uint8_t *)(j + a1) == 115 && *(uint8_t *)(j + 1LL + a1) == 116 &&\n *(uint8_t *)(j + 2LL + a1) == 100)\n ++v2;\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(long long a1) {\n unsigned int v2;\n int j;\n int i;\n v2 = 0;\n for (i = 0; *(uint8_t *)(i + a1); ++i)\n ;\n for (j = 0; j < i - 2; ++j) {\n if (*(uint8_t *)(j + a1) == 115 && *(uint8_t *)(j + 1LL + a1) == 116 &&\n *(uint8_t *)(j + 2LL + a1) == 100)\n ++v2;\n }\n return v2;\n}" + }, + { + "index": 172, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char* s) {\n int count = 0;\n int i;\n int len = 0;\n while (s[len] != '\\0') {\n len++;\n }\n for (i = 0; i < len - 2; i++) {\n if (s[i] == 's' && s[i + 1] == 't' && s[i + 2] == 'd') {\n count++;\n }\n }\n return count;\n}", + "test": "int main() {\n\n assert(func0(\"letstdlenstdporstd\") == 3);\n\n assert(func0(\"truststdsolensporsd\") == 1);\n\n assert(func0(\"makestdsostdworthit\") == 2);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ncmpb $0x0,(%rdi)\nje 119c \nmov $0x0,%eax\nmov %eax,%ecx\nadd $0x1,%rax\ncmpb $0x0,(%rdi,%rax,1)\njne 1157 \ncmp $0x1,%ecx\njle 11a4 \nmov %rdi,%rax\nlea -0x2(%rcx),%edx\nlea 0x1(%rdi,%rdx,1),%rcx\nmov $0x0,%esi\njmp 1183 \nadd $0x1,%rax\ncmp %rcx,%rax\nje 11a1 \ncmpb $0x73,(%rax)\njne 117a \ncmpb $0x74,0x1(%rax)\njne 117a \ncmpb $0x64,0x2(%rax)\nsete %dl\nmovzbl %dl,%edx\nadd %edx,%esi\njmp 117a \nmov $0x0,%esi\nmov %esi,%eax\nretq\nmov $0x0,%esi\njmp 11a1 \n", + "ida_asm": "func0:\nendbr64\ncmp byte ptr [rdi], 0\njz short loc_119F\nlea rdx, [rdi+1]\nmov eax, 0\nloc_115B:\nmov ecx, eax\nadd eax, 1\nadd rdx, 1\ncmp byte ptr [rdx-1], 0\njnz short loc_115B\nlea edx, [rcx-1]\ncmp eax, 2\njle short loc_11A7\nmov eax, 0\nmov ecx, 0\njmp short loc_1189\nloc_117E:\nadd ecx, 1\nloc_1181:\nadd rax, 1\ncmp edx, eax\njle short loc_11A4\nloc_1189:\ncmp byte ptr [rdi+rax], 73h ; 's'\njnz short loc_1181\ncmp byte ptr [rdi+rax+1], 74h ; 't'\njnz short loc_1181\ncmp byte ptr [rdi+rax+2], 64h ; 'd'\njnz short loc_1181\njmp short loc_117E\nloc_119F:\nmov ecx, 0\nloc_11A4:\nmov eax, ecx\nretn\nloc_11A7:\nmov ecx, 0\njmp short loc_11A4", + "ida_pseudo": "__int64 __fastcall func0(_BYTE *a1)\n{\n _BYTE *v1; // rdx\n int v2; // eax\n int v3; // ecx\n int v4; // edx\n __int64 v5; // rax\n unsigned int v6; // ecx\n\n if ( *a1 )\n {\n v1 = a1 + 1;\n v2 = 0;\n do\n {\n v3 = v2++;\n ++v1;\n }\n while ( *(v1 - 1) );\n v4 = v3 - 1;\n if ( v2 <= 2 )\n {\n return 0;\n }\n else\n {\n v5 = 0LL;\n v6 = 0;\n do\n {\n if ( a1[v5] == 115 && a1[v5 + 1] == 116 && a1[v5 + 2] == 100 )\n ++v6;\n ++v5;\n }\n while ( v4 > (int)v5 );\n }\n }\n else\n {\n return 0;\n }\n return v6;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ncmp byte ptr [rdi], 0\njz short loc_119F\nlea rdx, [rdi+1]\nmov eax, 0\nloc_115B:\nmov ecx, eax\nadd eax, 1\nadd rdx, 1\ncmp byte ptr [rdx-1], 0\njnz short loc_115B\nlea edx, [rcx-1]\ncmp eax, 2\njle short loc_11A7\nmov eax, 0\nmov ecx, 0\njmp short loc_1189\nloc_117E:\nadd ecx, 1\nloc_1181:\nadd rax, 1\ncmp edx, eax\njle short loc_11A4\nloc_1189:\ncmp byte ptr [rdi+rax], 73h ; 's'\njnz short loc_1181\ncmp byte ptr [rdi+rax+1], 74h ; 't'\njnz short loc_1181\ncmp byte ptr [rdi+rax+2], 64h ; 'd'\njnz short loc_1181\njmp short loc_117E\nloc_119F:\nmov ecx, 0\nloc_11A4:\nmov eax, ecx\nretn\nloc_11A7:\nmov ecx, 0\njmp short loc_11A4", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(_BYTE *a1)\n{\n _BYTE *v1; // rdx\n int v2; // eax\n int v3; // ecx\n int v4; // edx\n __int64 v5; // rax\n unsigned int v6; // ecx\n\n if ( *a1 )\n {\n v1 = a1 + 1;\n v2 = 0;\n do\n {\n v3 = v2++;\n ++v1;\n }\n while ( *(v1 - 1) );\n v4 = v3 - 1;\n if ( v2 <= 2 )\n {\n return 0;\n }\n else\n {\n v5 = 0LL;\n v6 = 0;\n do\n {\n if ( a1[v5] == 115 && a1[v5 + 1] == 116 && a1[v5 + 2] == 100 )\n ++v6;\n ++v5;\n }\n while ( v4 > (int)v5 );\n }\n }\n else\n {\n return 0;\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(uint8_t *a1) {\n uint8_t *v1;\n int v2;\n int v3;\n int v4;\n long long v5;\n unsigned int v6;\n if (*a1) {\n v1 = a1 + 1;\n v2 = 0;\n do {\n v3 = v2++;\n ++v1;\n } while (*(v1 - 1));\n v4 = v3 - 1;\n if (v2 <= 2) {\n return 0;\n } else {\n v5 = 0LL;\n v6 = 0;\n do {\n if (a1[v5] == 115 && a1[v5 + 1] == 116 && a1[v5 + 2] == 100) ++v6;\n ++v5;\n } while (v4 > (int)v5);\n }\n } else {\n return 0;\n }\n return v6;\n}", + "ida_pseudo_norm": "long long func0(uint8_t *a1) {\n uint8_t *v1;\n int v2;\n int v3;\n int v4;\n long long v5;\n unsigned int v6;\n if (*a1) {\n v1 = a1 + 1;\n v2 = 0;\n do {\n v3 = v2++;\n ++v1;\n } while (*(v1 - 1));\n v4 = v3 - 1;\n if (v2 <= 2) {\n return 0;\n } else {\n v5 = 0LL;\n v6 = 0;\n do {\n if (a1[v5] == 115 && a1[v5 + 1] == 116 && a1[v5 + 2] == 100) ++v6;\n ++v5;\n } while (v4 > (int)v5);\n }\n } else {\n return 0;\n }\n return v6;\n}" + }, + { + "index": 172, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char* s) {\n int count = 0;\n int i;\n int len = 0;\n while (s[len] != '\\0') {\n len++;\n }\n for (i = 0; i < len - 2; i++) {\n if (s[i] == 's' && s[i + 1] == 't' && s[i + 2] == 'd') {\n count++;\n }\n }\n return count;\n}", + "test": "int main() {\n\n assert(func0(\"letstdlenstdporstd\") == 3);\n\n assert(func0(\"truststdsolensporsd\") == 1);\n\n assert(func0(\"makestdsostdworthit\") == 2);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmovzbl (%rdi),%edx\ntest %dl,%dl\nje 1250 \nxor %eax,%eax\nnopl (%rax)\nmov %eax,%esi\nadd $0x1,%rax\ncmpb $0x0,(%rdi,%rax,1)\njne 1200 \ncmp $0x1,%esi\njle 1250 \nlea -0x2(%rsi),%eax\nxor %r8d,%r8d\nadd %rdi,%rax\njmp 122d \nnopl 0x0(%rax)\ncmp %rax,%rdi\nje 1249 \nmovzbl 0x1(%rdi),%edx\nadd $0x1,%rdi\ncmp $0x73,%dl\njne 1220 \ncmpb $0x74,0x1(%rdi)\njne 1220 \nxor %edx,%edx\ncmpb $0x64,0x2(%rdi)\nsete %dl\nadd %edx,%r8d\ncmp %rax,%rdi\njne 1225 \nmov %r8d,%eax\nretq\nnopl (%rax)\nxor %r8d,%r8d\nmov %r8d,%eax\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ncmp byte ptr [rdi], 0\njz short loc_1250\nlea rdx, [rdi+1]\nxor eax, eax\nnop\nloc_1200:\nadd rdx, 1\nmov ecx, eax\nadd eax, 1\ncmp byte ptr [rdx-1], 0\njnz short loc_1200\nlea edx, [rcx-1]\ncmp eax, 2\njle short loc_1250\nxor eax, eax\nxor ecx, ecx\njmp short loc_1228\nloc_1220:\nadd rax, 1\ncmp edx, eax\njle short loc_1247\nloc_1228:\ncmp byte ptr [rdi+rax], 73h ; 's'\njnz short loc_1220\ncmp byte ptr [rdi+rax+1], 74h ; 't'\njnz short loc_1220\ncmp byte ptr [rdi+rax+2], 64h ; 'd'\njnz short loc_1220\nadd rax, 1\nadd ecx, 1\ncmp edx, eax\njg short loc_1228\nloc_1247:\nmov eax, ecx\nretn\nloc_1250:\nxor ecx, ecx\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(_BYTE *a1)\n{\n _BYTE *v1; // rdx\n int v2; // eax\n int v3; // ecx\n int v4; // edx\n __int64 v5; // rax\n unsigned int v6; // ecx\n\n if ( !*a1 )\n return 0LL;\n v1 = a1 + 1;\n v2 = 0;\n do\n {\n ++v1;\n v3 = v2++;\n }\n while ( *(v1 - 1) );\n v4 = v3 - 1;\n if ( v2 <= 2 )\n return 0LL;\n v5 = 0LL;\n v6 = 0;\n do\n {\n while ( a1[v5] != 115 || a1[v5 + 1] != 116 || a1[v5 + 2] != 100 )\n {\n if ( v4 <= (int)++v5 )\n return v6;\n }\n ++v5;\n ++v6;\n }\n while ( v4 > (int)v5 );\n return v6;\n}", + "ida_strip_asm": "sub_11F0:\nendbr64\ncmp byte ptr [rdi], 0\njz short loc_1250\nlea rdx, [rdi+1]\nxor eax, eax\nnop\nloc_1200:\nadd rdx, 1\nmov ecx, eax\nadd eax, 1\ncmp byte ptr [rdx-1], 0\njnz short loc_1200\nlea edx, [rcx-1]\ncmp eax, 2\njle short loc_1250\nxor eax, eax\nxor ecx, ecx\njmp short loc_1228\nloc_1220:\nadd rax, 1\ncmp edx, eax\njle short loc_1247\nloc_1228:\ncmp byte ptr [rdi+rax], 73h ; 's'\njnz short loc_1220\ncmp byte ptr [rdi+rax+1], 74h ; 't'\njnz short loc_1220\ncmp byte ptr [rdi+rax+2], 64h ; 'd'\njnz short loc_1220\nadd rax, 1\nadd ecx, 1\ncmp edx, eax\njg short loc_1228\nloc_1247:\nmov eax, ecx\nretn\nloc_1250:\nxor ecx, ecx\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11F0(_BYTE *a1)\n{\n _BYTE *v1; // rdx\n int v2; // eax\n int v3; // ecx\n int v4; // edx\n __int64 v5; // rax\n unsigned int v6; // ecx\n\n if ( !*a1 )\n return 0LL;\n v1 = a1 + 1;\n v2 = 0;\n do\n {\n ++v1;\n v3 = v2++;\n }\n while ( *(v1 - 1) );\n v4 = v3 - 1;\n if ( v2 <= 2 )\n return 0LL;\n v5 = 0LL;\n v6 = 0;\n do\n {\n while ( a1[v5] != 115 || a1[v5 + 1] != 116 || a1[v5 + 2] != 100 )\n {\n if ( v4 <= (int)++v5 )\n return v6;\n }\n ++v5;\n ++v6;\n }\n while ( v4 > (int)v5 );\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11F0(uint8_t *a1) {\n uint8_t *v1;\n int v2;\n int v3;\n int v4;\n long long v5;\n unsigned int v6;\n if (!*a1) return 0LL;\n v1 = a1 + 1;\n v2 = 0;\n do {\n ++v1;\n v3 = v2++;\n } while (*(v1 - 1));\n v4 = v3 - 1;\n if (v2 <= 2) return 0LL;\n v5 = 0LL;\n v6 = 0;\n do {\n while (a1[v5] != 115 || a1[v5 + 1] != 116 || a1[v5 + 2] != 100) {\n if (v4 <= (int)++v5) return v6;\n }\n ++v5;\n ++v6;\n } while (v4 > (int)v5);\n return v6;\n}", + "ida_pseudo_norm": "long long func0(uint8_t *a1) {\n uint8_t *v1;\n int v2;\n int v3;\n int v4;\n long long v5;\n unsigned int v6;\n if (!*a1) return 0LL;\n v1 = a1 + 1;\n v2 = 0;\n do {\n ++v1;\n v3 = v2++;\n } while (*(v1 - 1));\n v4 = v3 - 1;\n if (v2 <= 2) return 0LL;\n v5 = 0LL;\n v6 = 0;\n do {\n while (a1[v5] != 115 || a1[v5 + 1] != 116 || a1[v5 + 2] != 100) {\n if (v4 <= (int)++v5) return v6;\n }\n ++v5;\n ++v6;\n } while (v4 > (int)v5);\n return v6;\n}" + }, + { + "index": 172, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char* s) {\n int count = 0;\n int i;\n int len = 0;\n while (s[len] != '\\0') {\n len++;\n }\n for (i = 0; i < len - 2; i++) {\n if (s[i] == 's' && s[i + 1] == 't' && s[i + 2] == 'd') {\n count++;\n }\n }\n return count;\n}", + "test": "int main() {\n\n assert(func0(\"letstdlenstdporstd\") == 3);\n\n assert(func0(\"truststdsolensporsd\") == 1);\n\n assert(func0(\"makestdsostdworthit\") == 2);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ncmpb $0x0,(%rdi)\nje 1250 \nxor %eax,%eax\nnopl 0x0(%rax,%rax,1)\nmov %eax,%ecx\nadd $0x1,%rax\ncmpb $0x0,(%rdi,%rax,1)\njne 1200 \ncmp $0x1,%ecx\njle 1250 \nlea -0x2(%rcx),%eax\nxor %r8d,%r8d\nlea 0x1(%rdi,%rax,1),%rax\njmp 1229 \nxchg %ax,%ax\nadd $0x1,%rdi\ncmp %rdi,%rax\nje 1249 \ncmpb $0x73,(%rdi)\njne 1220 \ncmpb $0x74,0x1(%rdi)\njne 1220 \nxor %edx,%edx\ncmpb $0x64,0x2(%rdi)\nsete %dl\nadd $0x1,%rdi\nadd %edx,%r8d\ncmp %rdi,%rax\njne 1229 \nmov %r8d,%eax\nretq\nnopl (%rax)\nxor %r8d,%r8d\nmov %r8d,%eax\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ncmp byte ptr [rdi], 0\njz short loc_1250\nlea rdx, [rdi+1]\nxor eax, eax\nnop\nloc_1200:\nadd rdx, 1\nmov ecx, eax\nadd eax, 1\ncmp byte ptr [rdx-1], 0\njnz short loc_1200\nlea edx, [rcx-1]\ncmp eax, 2\njle short loc_1250\nxor eax, eax\nxor ecx, ecx\njmp short loc_1228\nloc_1220:\nadd rax, 1\ncmp edx, eax\njle short loc_1247\nloc_1228:\ncmp byte ptr [rdi+rax], 73h ; 's'\njnz short loc_1220\ncmp byte ptr [rdi+rax+1], 74h ; 't'\njnz short loc_1220\ncmp byte ptr [rdi+rax+2], 64h ; 'd'\njnz short loc_1220\nadd rax, 1\nadd ecx, 1\ncmp edx, eax\njg short loc_1228\nloc_1247:\nmov eax, ecx\nretn\nloc_1250:\nxor ecx, ecx\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(_BYTE *a1)\n{\n _BYTE *v1; // rdx\n int v2; // eax\n int v3; // ecx\n int v4; // edx\n __int64 v5; // rax\n unsigned int v6; // ecx\n\n if ( !*a1 )\n return 0LL;\n v1 = a1 + 1;\n v2 = 0;\n do\n {\n ++v1;\n v3 = v2++;\n }\n while ( *(v1 - 1) );\n v4 = v3 - 1;\n if ( v2 <= 2 )\n return 0LL;\n v5 = 0LL;\n v6 = 0;\n do\n {\n while ( a1[v5] != 115 || a1[v5 + 1] != 116 || a1[v5 + 2] != 100 )\n {\n if ( v4 <= (int)++v5 )\n return v6;\n }\n ++v5;\n ++v6;\n }\n while ( v4 > (int)v5 );\n return v6;\n}", + "ida_strip_asm": "sub_11F0:\nendbr64\ncmp byte ptr [rdi], 0\njz short loc_1250\nlea rdx, [rdi+1]\nxor eax, eax\nnop\nloc_1200:\nadd rdx, 1\nmov ecx, eax\nadd eax, 1\ncmp byte ptr [rdx-1], 0\njnz short loc_1200\nlea edx, [rcx-1]\ncmp eax, 2\njle short loc_1250\nxor eax, eax\nxor ecx, ecx\njmp short loc_1228\nloc_1220:\nadd rax, 1\ncmp edx, eax\njle short loc_1247\nloc_1228:\ncmp byte ptr [rdi+rax], 73h ; 's'\njnz short loc_1220\ncmp byte ptr [rdi+rax+1], 74h ; 't'\njnz short loc_1220\ncmp byte ptr [rdi+rax+2], 64h ; 'd'\njnz short loc_1220\nadd rax, 1\nadd ecx, 1\ncmp edx, eax\njg short loc_1228\nloc_1247:\nmov eax, ecx\nretn\nloc_1250:\nxor ecx, ecx\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11F0(_BYTE *a1)\n{\n _BYTE *v1; // rdx\n int v2; // eax\n int v3; // ecx\n int v4; // edx\n __int64 v5; // rax\n unsigned int v6; // ecx\n\n if ( !*a1 )\n return 0LL;\n v1 = a1 + 1;\n v2 = 0;\n do\n {\n ++v1;\n v3 = v2++;\n }\n while ( *(v1 - 1) );\n v4 = v3 - 1;\n if ( v2 <= 2 )\n return 0LL;\n v5 = 0LL;\n v6 = 0;\n do\n {\n while ( a1[v5] != 115 || a1[v5 + 1] != 116 || a1[v5 + 2] != 100 )\n {\n if ( v4 <= (int)++v5 )\n return v6;\n }\n ++v5;\n ++v6;\n }\n while ( v4 > (int)v5 );\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11F0(uint8_t *a1) {\n uint8_t *v1;\n int v2;\n int v3;\n int v4;\n long long v5;\n unsigned int v6;\n if (!*a1) return 0LL;\n v1 = a1 + 1;\n v2 = 0;\n do {\n ++v1;\n v3 = v2++;\n } while (*(v1 - 1));\n v4 = v3 - 1;\n if (v2 <= 2) return 0LL;\n v5 = 0LL;\n v6 = 0;\n do {\n while (a1[v5] != 115 || a1[v5 + 1] != 116 || a1[v5 + 2] != 100) {\n if (v4 <= (int)++v5) return v6;\n }\n ++v5;\n ++v6;\n } while (v4 > (int)v5);\n return v6;\n}", + "ida_pseudo_norm": "long long func0(uint8_t *a1) {\n uint8_t *v1;\n int v2;\n int v3;\n int v4;\n long long v5;\n unsigned int v6;\n if (!*a1) return 0LL;\n v1 = a1 + 1;\n v2 = 0;\n do {\n ++v1;\n v3 = v2++;\n } while (*(v1 - 1));\n v4 = v3 - 1;\n if (v2 <= 2) return 0LL;\n v5 = 0LL;\n v6 = 0;\n do {\n while (a1[v5] != 115 || a1[v5 + 1] != 116 || a1[v5 + 2] != 100) {\n if (v4 <= (int)++v5) return v6;\n }\n ++v5;\n ++v6;\n } while (v4 > (int)v5);\n return v6;\n}" + }, + { + "index": 173, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* text) {\n int i = 0, j = 0;\n char temp[strlen(text) + 1];\n while (text[i]) {\n if (isalnum(text[i])) {\n temp[j++] = text[i];\n }\n i++;\n }\n temp[j] = '\\0';\n strcpy(text, temp);\n return text;\n}", + "test": "int main() {\n\n char text1[] = \"python @#&^%$*program123\";\n\n char text2[] = \"python %^$@!^&*() programming24%$^^() language\";\n\n char text3[] = \"python ^%&^()(+_)(_^&67) program\";\n\n \n\n assert(strcmp(func0(text1), \"pythonprogram123\") == 0);\n\n assert(strcmp(func0(text2), \"pythonprogramming24language\") == 0);\n\n assert(strcmp(func0(text3), \"python67program\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0x38,%rsp\nmov %rdi,-0x58(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nmov %rsp,%rax\nmov %rax,%rbx\nmovl $0x0,-0x4c(%rbp)\nmovl $0x0,-0x50(%rbp)\nmov -0x58(%rbp),%rax\nmov %rax,%rdi\ncallq 10b0 \nadd $0x1,%rax\nmov %rax,%rdx\nsub $0x1,%rdx\nmov %rdx,-0x48(%rbp)\nmov %rax,%r14\nmov $0x0,%r15d\nmov %rax,%r12\nmov $0x0,%r13d\nmov $0x10,%edx\nsub $0x1,%rdx\nadd %rdx,%rax\nmov $0x10,%edi\nmov $0x0,%edx\ndiv %rdi\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rsi\nsub %rdx,%rsi\nmov %rsi,%rdx\ncmp %rdx,%rsp\nje 1299 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 1282 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 12c3 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x0,%rax\nmov %rax,-0x40(%rbp)\njmp 1326 \ncallq 10f0 <__ctype_b_loc@plt>\nmov (%rax),%rax\nmov -0x4c(%rbp),%edx\nmovslq %edx,%rcx\nmov -0x58(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rdx),%edx\nmovsbq %dl,%rdx\nadd %rdx,%rdx\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x8,%eax\ntest %eax,%eax\nje 1322 \nmov -0x4c(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x58(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x50(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x50(%rbp)\nmovzbl (%rcx),%ecx\nmov -0x40(%rbp),%rdx\ncltq\nmov %cl,(%rdx,%rax,1)\naddl $0x1,-0x4c(%rbp)\nmov -0x4c(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x58(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 12d0 \nmov -0x40(%rbp),%rdx\nmov -0x50(%rbp),%eax\ncltq\nmovb $0x0,(%rdx,%rax,1)\nmov -0x40(%rbp),%rdx\nmov -0x58(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10a0 \nmov -0x58(%rbp),%rax\nmov %rbx,%rsp\nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\nje 1375 \ncallq 10c0 <__stack_chk_fail@plt>\nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+s], rdi\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov rax, rsp\nmov rbx, rax\nmov [rbp+var_30], 0\nmov [rbp+var_2C], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nadd rax, 1\nmov rdx, rax\nsub rdx, 1\nmov [rbp+var_28], rdx\nmov edx, 10h\nsub rdx, 1\nadd rax, rdx\nmov esi, 10h\nmov edx, 0\ndiv rsi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_1265:\ncmp rsp, rdx\njz short loc_127C\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_1265\nloc_127C:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_12A6\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_12A6:\nmov rax, rsp\nadd rax, 0\nmov [rbp+src], rax\njmp short loc_1309\nloc_12B3:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_30]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 8\ntest eax, eax\njz short loc_1305\nmov eax, [rbp+var_30]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_2C]\nlea edx, [rax+1]\nmov [rbp+var_2C], edx\nmovzx ecx, byte ptr [rcx]\nmov rdx, [rbp+src]\ncdqe\nmov [rdx+rax], cl\nloc_1305:\nadd [rbp+var_30], 1\nloc_1309:\nmov eax, [rbp+var_30]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_12B3\nmov rdx, [rbp+src]\nmov eax, [rbp+var_2C]\ncdqe\nmov byte ptr [rdx+rax], 0\nmov rdx, [rbp+src]\nmov rax, [rbp+s]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\nmov rax, [rbp+s]\nmov rsp, rbx\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njz short loc_1358\ncall ___stack_chk_fail\nloc_1358:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(char *a1)\n{\n size_t v1; // rax\n unsigned __int64 v2; // rax\n void *v3; // rsp\n int v4; // eax\n _BYTE v6[8]; // [rsp+8h] [rbp-40h] BYREF\n char *s; // [rsp+10h] [rbp-38h]\n int v8; // [rsp+18h] [rbp-30h]\n int v9; // [rsp+1Ch] [rbp-2Ch]\n size_t v10; // [rsp+20h] [rbp-28h]\n char *src; // [rsp+28h] [rbp-20h]\n unsigned __int64 v12; // [rsp+30h] [rbp-18h]\n\n s = a1;\n v12 = __readfsqword(0x28u);\n v8 = 0;\n v9 = 0;\n v1 = strlen(a1) + 1;\n v10 = v1 - 1;\n v2 = 16 * ((v1 + 15) / 0x10);\n while ( v6 != &v6[-(v2 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = alloca(v2 & 0xFFF);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)&v6[(v2 & 0xFFF) - 8] = *(_QWORD *)&v6[(v2 & 0xFFF) - 8];\n src = v6;\n while ( s[v8] )\n {\n if ( ((*__ctype_b_loc())[s[v8]] & 8) != 0 )\n {\n v4 = v9++;\n src[v4] = s[v8];\n }\n ++v8;\n }\n src[v9] = 0;\n strcpy(s, src);\n return s;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+s], rdi\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov rax, rsp\nmov rbx, rax\nmov [rbp+var_30], 0\nmov [rbp+var_2C], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nadd rax, 1\nmov rdx, rax\nsub rdx, 1\nmov [rbp+var_28], rdx\nmov edx, 10h\nsub rdx, 1\nadd rax, rdx\nmov esi, 10h\nmov edx, 0\ndiv rsi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_1265:\ncmp rsp, rdx\njz short loc_127C\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_1265\nloc_127C:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_12A6\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_12A6:\nmov rax, rsp\nadd rax, 0\nmov [rbp+src], rax\njmp short loc_1309\nloc_12B3:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_30]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 8\ntest eax, eax\njz short loc_1305\nmov eax, [rbp+var_30]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_2C]\nlea edx, [rax+1]\nmov [rbp+var_2C], edx\nmovzx ecx, byte ptr [rcx]\nmov rdx, [rbp+src]\ncdqe\nmov [rdx+rax], cl\nloc_1305:\nadd [rbp+var_30], 1\nloc_1309:\nmov eax, [rbp+var_30]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_12B3\nmov rdx, [rbp+src]\nmov eax, [rbp+var_2C]\ncdqe\nmov byte ptr [rdx+rax], 0\nmov rdx, [rbp+src]\nmov rax, [rbp+s]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\nmov rax, [rbp+s]\nmov rsp, rbx\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njz short loc_1358\ncall ___stack_chk_fail\nloc_1358:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11E9(char *a1)\n{\n size_t v1; // rax\n unsigned __int64 v2; // rax\n void *v3; // rsp\n int v4; // eax\n _BYTE v6[8]; // [rsp+8h] [rbp-40h] BYREF\n char *s; // [rsp+10h] [rbp-38h]\n int v8; // [rsp+18h] [rbp-30h]\n int v9; // [rsp+1Ch] [rbp-2Ch]\n size_t v10; // [rsp+20h] [rbp-28h]\n char *src; // [rsp+28h] [rbp-20h]\n unsigned __int64 v12; // [rsp+30h] [rbp-18h]\n\n s = a1;\n v12 = __readfsqword(0x28u);\n v8 = 0;\n v9 = 0;\n v1 = strlen(a1) + 1;\n v10 = v1 - 1;\n v2 = 16 * ((v1 + 15) / 0x10);\n while ( v6 != &v6[-(v2 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = alloca(v2 & 0xFFF);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)&v6[(v2 & 0xFFF) - 8] = *(_QWORD *)&v6[(v2 & 0xFFF) - 8];\n src = v6;\n while ( s[v8] )\n {\n if ( ((*__ctype_b_loc())[s[v8]] & 8) != 0 )\n {\n v4 = v9++;\n src[v4] = s[v8];\n }\n ++v8;\n }\n src[v9] = 0;\n strcpy(s, src);\n return s;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11E9(char *a1) {\n unsigned int v1;\n unsigned long long v2;\n void *v3;\n int v4;\n uint8_t v6[8];\n char *s;\n int v8;\n int v9;\n unsigned int v10;\n char *src;\n unsigned long long v12;\n s = a1;\n v12 = __readfsqword(40u);\n v8 = 0;\n v9 = 0;\n v1 = strlen(a1) + 1;\n v10 = v1 - 1;\n v2 = 16 * ((v1 + 15) / 16);\n while (v6 != &v6[-(v2 & 18446744073709547520LL)])\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)&v6[(v2 & 4095) - 8] = *(uint64_t *)&v6[(v2 & 4095) - 8];\n src = v6;\n while (s[v8]) {\n if (((*__ctype_b_loc())[s[v8]] & 8) != 0) {\n v4 = v9++;\n src[v4] = s[v8];\n }\n ++v8;\n }\n src[v9] = 0;\n strcpy(s, src);\n return s;\n}", + "ida_pseudo_norm": "char *func0(char *a1) {\n unsigned int v1;\n unsigned long long v2;\n void *v3;\n int v4;\n uint8_t v6[8];\n char *s;\n int v8;\n int v9;\n unsigned int v10;\n char *src;\n unsigned long long v12;\n s = a1;\n v12 = __readfsqword(40u);\n v8 = 0;\n v9 = 0;\n v1 = strlen(a1) + 1;\n v10 = v1 - 1;\n v2 = 16 * ((v1 + 15) / 16);\n while (v6 != &v6[-(v2 & 18446744073709547520LL)])\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)&v6[(v2 & 4095) - 8] = *(uint64_t *)&v6[(v2 & 4095) - 8];\n src = v6;\n while (s[v8]) {\n if (((*__ctype_b_loc())[s[v8]] & 8) != 0) {\n v4 = v9++;\n src[v4] = s[v8];\n }\n ++v8;\n }\n src[v9] = 0;\n strcpy(s, src);\n return s;\n}" + }, + { + "index": 173, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* text) {\n int i = 0, j = 0;\n char temp[strlen(text) + 1];\n while (text[i]) {\n if (isalnum(text[i])) {\n temp[j++] = text[i];\n }\n i++;\n }\n temp[j] = '\\0';\n strcpy(text, temp);\n return text;\n}", + "test": "int main() {\n\n char text1[] = \"python @#&^%$*program123\";\n\n char text2[] = \"python %^$@!^&*() programming24%$^^() language\";\n\n char text3[] = \"python ^%&^()(+_)(_^&67) program\";\n\n \n\n assert(strcmp(func0(text1), \"pythonprogram123\") == 0);\n\n assert(strcmp(func0(text2), \"pythonprogramming24language\") == 0);\n\n assert(strcmp(func0(text3), \"python67program\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r13\npush %r12\npush %rbx\nsub $0x18,%rsp\nmov %rdi,%r12\nmov %fs:0x28,%rax\nmov %rax,-0x28(%rbp)\nxor %eax,%eax\nmov $0xffffffffffffffff,%rcx\nrepnz scas %es:(%rdi),%al\nnot %rcx\nadd $0xf,%rcx\nmov %rcx,%rdx\nand $0xfffffffffffffff0,%rdx\nand $0xfffffffffffff000,%rcx\nmov %rsp,%rax\nsub %rcx,%rax\ncmp %rax,%rsp\nje 1207 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11f0 \nmov %rdx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 121d \norq $0x0,-0x8(%rsp,%rax,1)\nmov %rsp,%r13\nmovzbl (%r12),%ebx\ntest %bl,%bl\nje 1260 \ncallq 10b0 <__ctype_b_loc@plt>\nmov (%rax),%rsi\nlea 0x1(%r12),%rax\nmov $0x0,%ecx\njmp 1249 \nadd $0x1,%rax\nmovzbl -0x1(%rax),%ebx\ntest %bl,%bl\nje 1265 \nmovsbq %bl,%rdx\ntestb $0x8,(%rsi,%rdx,2)\nje 123d \nmovslq %ecx,%rdx\nmov %bl,0x0(%r13,%rdx,1)\nlea 0x1(%rcx),%ecx\njmp 123d \nmov $0x0,%ecx\nmovslq %ecx,%rcx\nmovb $0x0,0x0(%r13,%rcx,1)\nmov %r13,%rsi\nmov %r12,%rdi\ncallq 1080 \nmov -0x28(%rbp),%rax\nxor %fs:0x28,%rax\njne 1296 \nmov %r12,%rax\nlea -0x18(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %rbp\nretq\ncallq 1090 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r13\npush r12\npush rbx\nsub rsp, 18h\nmov r12, rdi\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\ncall _strlen\nadd rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_1228:\ncmp rsp, rdx\njz short loc_123F\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\njmp short loc_1228\nloc_123F:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_1255\nor [rsp+rax+30h+var_38], 0\nloc_1255:\nmov r13, rsp\nmovzx ebx, byte ptr [r12]\ntest bl, bl\njz short loc_1298\ncall ___ctype_b_loc\nmov rsi, [rax]\nlea rax, [r12+1]\nmov ecx, 0\njmp short loc_1281\nloc_1275:\nadd rax, 1\nmovzx ebx, byte ptr [rax-1]\ntest bl, bl\njz short loc_129D\nloc_1281:\nmovsx rdx, bl\ntest byte ptr [rsi+rdx*2], 8\njz short loc_1275\nmovsxd rdx, ecx\nmov [r13+rdx+0], bl\nlea ecx, [rcx+1]\njmp short loc_1275\nloc_1298:\nmov ecx, 0\nloc_129D:\nmovsxd rcx, ecx\nmov byte ptr [r13+rcx+0], 0\nmov rsi, r13; src\nmov rdi, r12; dest\ncall _strcpy\nmov rax, [rbp+var_28]\nsub rax, fs:28h\njnz short loc_12CE\nmov rax, r12\nlea rsp, [rbp-18h]\npop rbx\npop r12\npop r13\npop rbp\nretn\nloc_12CE:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(char *dest)\n{\n size_t v1; // rax\n __int16 v2; // cx\n signed __int64 v3; // rax\n void *v4; // rsp\n char v5; // bl\n const unsigned __int16 *v6; // rsi\n char *v7; // rax\n int v8; // ecx\n char v11[8]; // [rsp+8h] [rbp-30h] BYREF\n unsigned __int64 v12; // [rsp+10h] [rbp-28h]\n\n v12 = __readfsqword(0x28u);\n v1 = strlen(dest) + 16;\n v2 = v1 & 0xFFF0;\n while ( v11 != &v11[-(v1 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = v1 & 0xFF0;\n v4 = alloca(v3);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)&v11[v3 - 8] = *(_QWORD *)&v11[v3 - 8];\n v5 = *dest;\n if ( *dest )\n {\n v6 = *__ctype_b_loc();\n v7 = dest + 1;\n v8 = 0;\n do\n {\n if ( (v6[v5] & 8) != 0 )\n v11[v8++] = v5;\n v5 = *v7++;\n }\n while ( v5 );\n }\n else\n {\n v8 = 0;\n }\n v11[v8] = 0;\n strcpy(dest, v11);\n return dest;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\npush r13\npush r12\npush rbx\nsub rsp, 18h\nmov r12, rdi\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\ncall _strlen\nadd rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_1228:\ncmp rsp, rdx\njz short loc_123F\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\njmp short loc_1228\nloc_123F:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_1255\nor [rsp+rax+30h+var_38], 0\nloc_1255:\nmov r13, rsp\nmovzx ebx, byte ptr [r12]\ntest bl, bl\njz short loc_1298\ncall ___ctype_b_loc\nmov rsi, [rax]\nlea rax, [r12+1]\nmov ecx, 0\njmp short loc_1281\nloc_1275:\nadd rax, 1\nmovzx ebx, byte ptr [rax-1]\ntest bl, bl\njz short loc_129D\nloc_1281:\nmovsx rdx, bl\ntest byte ptr [rsi+rdx*2], 8\njz short loc_1275\nmovsxd rdx, ecx\nmov [r13+rdx+0], bl\nlea ecx, [rcx+1]\njmp short loc_1275\nloc_1298:\nmov ecx, 0\nloc_129D:\nmovsxd rcx, ecx\nmov byte ptr [r13+rcx+0], 0\nmov rsi, r13; src\nmov rdi, r12; dest\ncall _strcpy\nmov rax, [rbp+var_28]\nsub rax, fs:28h\njnz short loc_12CE\nmov rax, r12\nlea rsp, [rbp-18h]\npop rbx\npop r12\npop r13\npop rbp\nretn\nloc_12CE:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_11E9(char *dest)\n{\n size_t v1; // rax\n __int16 v2; // cx\n signed __int64 v3; // rax\n void *v4; // rsp\n char v5; // bl\n const unsigned __int16 *v6; // rsi\n char *v7; // rax\n int v8; // ecx\n char v11[8]; // [rsp+8h] [rbp-30h] BYREF\n unsigned __int64 v12; // [rsp+10h] [rbp-28h]\n\n v12 = __readfsqword(0x28u);\n v1 = strlen(dest) + 16;\n v2 = v1 & 0xFFF0;\n while ( v11 != &v11[-(v1 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = v1 & 0xFF0;\n v4 = alloca(v3);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)&v11[v3 - 8] = *(_QWORD *)&v11[v3 - 8];\n v5 = *dest;\n if ( *dest )\n {\n v6 = *__ctype_b_loc();\n v7 = dest + 1;\n v8 = 0;\n do\n {\n if ( (v6[v5] & 8) != 0 )\n v11[v8++] = v5;\n v5 = *v7++;\n }\n while ( v5 );\n }\n else\n {\n v8 = 0;\n }\n v11[v8] = 0;\n strcpy(dest, v11);\n return dest;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11E9(char *dest) {\n unsigned int v1;\n short v2;\n signed long long v3;\n void *v4;\n char v5;\n const unsigned short *v6;\n char *v7;\n int v8;\n char v11[8];\n unsigned long long v12;\n v12 = __readfsqword(40u);\n v1 = strlen(dest) + 16;\n v2 = v1 & 65520;\n while (v11 != &v11[-(v1 & 18446744073709547520LL)])\n ;\n v3 = v1 & 4080;\n v4 = alloca(v3);\n if ((v2 & 4095) != 0) *(uint64_t *)&v11[v3 - 8] = *(uint64_t *)&v11[v3 - 8];\n v5 = *dest;\n if (*dest) {\n v6 = *__ctype_b_loc();\n v7 = dest + 1;\n v8 = 0;\n do {\n if ((v6[v5] & 8) != 0) v11[v8++] = v5;\n v5 = *v7++;\n } while (v5);\n } else {\n v8 = 0;\n }\n v11[v8] = 0;\n strcpy(dest, v11);\n return dest;\n}", + "ida_pseudo_norm": "char *func0(char *dest) {\n unsigned int v1;\n short v2;\n signed long long v3;\n void *v4;\n char v5;\n const unsigned short *v6;\n char *v7;\n int v8;\n char v11[8];\n unsigned long long v12;\n v12 = __readfsqword(40u);\n v1 = strlen(dest) + 16;\n v2 = v1 & 65520;\n while (v11 != &v11[-(v1 & 18446744073709547520LL)])\n ;\n v3 = v1 & 4080;\n v4 = alloca(v3);\n if ((v2 & 4095) != 0) *(uint64_t *)&v11[v3 - 8] = *(uint64_t *)&v11[v3 - 8];\n v5 = *dest;\n if (*dest) {\n v6 = *__ctype_b_loc();\n v7 = dest + 1;\n v8 = 0;\n do {\n if ((v6[v5] & 8) != 0) v11[v8++] = v5;\n v5 = *v7++;\n } while (v5);\n } else {\n v8 = 0;\n }\n v11[v8] = 0;\n strcpy(dest, v11);\n return dest;\n}" + }, + { + "index": 173, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* text) {\n int i = 0, j = 0;\n char temp[strlen(text) + 1];\n while (text[i]) {\n if (isalnum(text[i])) {\n temp[j++] = text[i];\n }\n i++;\n }\n temp[j] = '\\0';\n strcpy(text, temp);\n return text;\n}", + "test": "int main() {\n\n char text1[] = \"python @#&^%$*program123\";\n\n char text2[] = \"python %^$@!^&*() programming24%$^^() language\";\n\n char text3[] = \"python ^%&^()(+_)(_^&67) program\";\n\n \n\n assert(strcmp(func0(text1), \"pythonprogram123\") == 0);\n\n assert(strcmp(func0(text2), \"pythonprogramming24language\") == 0);\n\n assert(strcmp(func0(text3), \"python67program\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r13\npush %r12\nmov %rdi,%r12\npush %rbx\nsub $0x18,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x28(%rbp)\nxor %eax,%eax\ncallq 10a0 \nmov %rsp,%rdi\nadd $0x10,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rdi\nand $0xfffffffffffffff0,%rdx\nmov %rdi,%rax\ncmp %rax,%rsp\nje 13cc \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 13b7 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 1450 \nmovzbl (%r12),%ebx\nmov %rsp,%r13\ntest %bl,%bl\nje 1458 \ncallq 10d0 <__ctype_b_loc@plt>\nxor %ecx,%ecx\nmov (%rax),%rsi\nlea 0x1(%r12),%rax\nnopl (%rax)\nmovsbq %bl,%rdx\ntestb $0x8,(%rsi,%rdx,2)\nje 140d \nmovslq %ecx,%rdx\nadd $0x1,%ecx\nmov %bl,0x0(%r13,%rdx,1)\nmovzbl (%rax),%ebx\nadd $0x1,%rax\ntest %bl,%bl\njne 13f8 \nmovslq %ecx,%rcx\nmov %r13,%rsi\nmov %r12,%rdi\nmovb $0x0,0x0(%r13,%rcx,1)\ncallq 1090 \nmov -0x28(%rbp),%rax\nxor %fs:0x28,%rax\njne 145c \nlea -0x18(%rbp),%rsp\nmov %r12,%rax\npop %rbx\npop %r12\npop %r13\npop %rbp\nretq\nnopl 0x0(%rax)\norq $0x0,-0x8(%rsp,%rdx,1)\njmp 13da \nxor %ecx,%ecx\njmp 1418 \ncallq 10b0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r13\npush r12\nmov r12, rdi\npush rbx\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\ncall _strlen\nmov rcx, rsp\nadd rax, 10h\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_13B9\nloc_13A4:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rcx\njnz short loc_13A4\nloc_13B9:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz short loc_1440\nloc_13C7:\nmovzx ebx, byte ptr [r12]\nmov r13, rsp\ntest bl, bl\njz short loc_144B\ncall ___ctype_b_loc\nxor ecx, ecx\nmov rsi, [rax]\nlea rax, [r12+1]\nnop word ptr [rax+rax+00h]\nloc_13E8:\nmovsx rdx, bl\ntest byte ptr [rsi+rdx*2], 8\njz short loc_13FD\nmovsxd rdx, ecx\nadd ecx, 1\nmov [r13+rdx+0], bl\nloc_13FD:\nmovzx ebx, byte ptr [rax]\nadd rax, 1\ntest bl, bl\njnz short loc_13E8\nloc_1408:\nmovsxd rcx, ecx\nmov rsi, r13; src\nmov rdi, r12; dest\nmov byte ptr [r13+rcx+0], 0\ncall _strcpy\nmov rax, [rbp+var_28]\nsub rax, fs:28h\njnz short loc_144F\nlea rsp, [rbp-18h]\nmov rax, r12\npop rbx\npop r12\npop r13\npop rbp\nretn\nloc_1440:\nor [rsp+rdx+1030h+var_1038], 0\njmp loc_13C7\nloc_144B:\nxor ecx, ecx\njmp short loc_1408\nloc_144F:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(char *dest)\n{\n size_t v1; // rax\n char *v2; // rcx\n signed __int64 v3; // rdx\n void *v4; // rsp\n char v5; // bl\n const unsigned __int16 **v6; // rax\n int v7; // ecx\n const unsigned __int16 *v8; // rsi\n char *v9; // rax\n __int64 v10; // rdx\n char v13[4088]; // [rsp+8h] [rbp-1030h] BYREF\n _QWORD v14[6]; // [rsp+1008h] [rbp-30h] BYREF\n\n v14[1] = __readfsqword(0x28u);\n v1 = strlen(dest);\n v2 = (char *)v14 - ((v1 + 16) & 0xFFFFFFFFFFFFF000LL);\n if ( v14 != (_QWORD *)v2 )\n {\n while ( v13 != v2 )\n ;\n }\n v3 = ((_WORD)v1 + 16) & 0xFF0;\n v4 = alloca(v3);\n if ( (((_WORD)v1 + 16) & 0xFF0) != 0 )\n *(_QWORD *)&v13[v3 - 8] = *(_QWORD *)&v13[v3 - 8];\n v5 = *dest;\n if ( *dest )\n {\n v6 = __ctype_b_loc();\n v7 = 0;\n v8 = *v6;\n v9 = dest + 1;\n do\n {\n if ( (v8[v5] & 8) != 0 )\n {\n v10 = v7++;\n v13[v10] = v5;\n }\n v5 = *v9++;\n }\n while ( v5 );\n }\n else\n {\n v7 = 0;\n }\n v13[v7] = 0;\n strcpy(dest, v13);\n return dest;\n}", + "ida_strip_asm": "sub_1360:\nendbr64\npush rbp\nmov rbp, rsp\npush r13\npush r12\nmov r12, rdi\npush rbx\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\ncall _strlen\nmov rcx, rsp\nadd rax, 10h\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_13B9\nloc_13A4:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rcx\njnz short loc_13A4\nloc_13B9:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz short loc_1440\nloc_13C7:\nmovzx ebx, byte ptr [r12]\nmov r13, rsp\ntest bl, bl\njz short loc_144B\ncall ___ctype_b_loc\nxor ecx, ecx\nmov rsi, [rax]\nlea rax, [r12+1]\nnop word ptr [rax+rax+00h]\nloc_13E8:\nmovsx rdx, bl\ntest byte ptr [rsi+rdx*2], 8\njz short loc_13FD\nmovsxd rdx, ecx\nadd ecx, 1\nmov [r13+rdx+0], bl\nloc_13FD:\nmovzx ebx, byte ptr [rax]\nadd rax, 1\ntest bl, bl\njnz short loc_13E8\nloc_1408:\nmovsxd rcx, ecx\nmov rsi, r13; src\nmov rdi, r12; dest\nmov byte ptr [r13+rcx+0], 0\ncall _strcpy\nmov rax, [rbp+var_28]\nsub rax, fs:28h\njnz short loc_144F\nlea rsp, [rbp-18h]\nmov rax, r12\npop rbx\npop r12\npop r13\npop rbp\nretn\nloc_1440:\nor [rsp+rdx+1030h+var_1038], 0\njmp loc_13C7\nloc_144B:\nxor ecx, ecx\njmp short loc_1408\nloc_144F:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_1360(char *dest)\n{\n size_t v1; // rax\n char *v2; // rcx\n signed __int64 v3; // rdx\n void *v4; // rsp\n char v5; // bl\n const unsigned __int16 **v6; // rax\n int v7; // ecx\n const unsigned __int16 *v8; // rsi\n char *v9; // rax\n __int64 v10; // rdx\n char v13[4088]; // [rsp+8h] [rbp-1030h] BYREF\n _QWORD v14[6]; // [rsp+1008h] [rbp-30h] BYREF\n\n v14[1] = __readfsqword(0x28u);\n v1 = strlen(dest);\n v2 = (char *)v14 - ((v1 + 16) & 0xFFFFFFFFFFFFF000LL);\n if ( v14 != (_QWORD *)v2 )\n {\n while ( v13 != v2 )\n ;\n }\n v3 = ((_WORD)v1 + 16) & 0xFF0;\n v4 = alloca(v3);\n if ( (((_WORD)v1 + 16) & 0xFF0) != 0 )\n *(_QWORD *)&v13[v3 - 8] = *(_QWORD *)&v13[v3 - 8];\n v5 = *dest;\n if ( *dest )\n {\n v6 = __ctype_b_loc();\n v7 = 0;\n v8 = *v6;\n v9 = dest + 1;\n do\n {\n if ( (v8[v5] & 8) != 0 )\n {\n v10 = v7++;\n v13[v10] = v5;\n }\n v5 = *v9++;\n }\n while ( v5 );\n }\n else\n {\n v7 = 0;\n }\n v13[v7] = 0;\n strcpy(dest, v13);\n return dest;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1360(char *dest) {\n unsigned int v1;\n char *v2;\n signed long long v3;\n void *v4;\n char v5;\n const unsigned short **v6;\n int v7;\n const unsigned short *v8;\n char *v9;\n long long v10;\n char v13[4088];\n uint64_t v14[6];\n v14[1] = __readfsqword(40u);\n v1 = strlen(dest);\n v2 = (char *)v14 - ((v1 + 16) & 18446744073709547520LL);\n if (v14 != (uint64_t *)v2) {\n while (v13 != v2)\n ;\n }\n v3 = ((unsigned short)v1 + 16) & 4080;\n v4 = alloca(v3);\n if ((((unsigned short)v1 + 16) & 4080) != 0)\n *(uint64_t *)&v13[v3 - 8] = *(uint64_t *)&v13[v3 - 8];\n v5 = *dest;\n if (*dest) {\n v6 = __ctype_b_loc();\n v7 = 0;\n v8 = *v6;\n v9 = dest + 1;\n do {\n if ((v8[v5] & 8) != 0) {\n v10 = v7++;\n v13[v10] = v5;\n }\n v5 = *v9++;\n } while (v5);\n } else {\n v7 = 0;\n }\n v13[v7] = 0;\n strcpy(dest, v13);\n return dest;\n}", + "ida_pseudo_norm": "char *func0(char *dest) {\n unsigned int v1;\n char *v2;\n signed long long v3;\n void *v4;\n char v5;\n const unsigned short **v6;\n int v7;\n const unsigned short *v8;\n char *v9;\n long long v10;\n char v13[4088];\n uint64_t v14[6];\n v14[1] = __readfsqword(40u);\n v1 = strlen(dest);\n v2 = (char *)v14 - ((v1 + 16) & 18446744073709547520LL);\n if (v14 != (uint64_t *)v2) {\n while (v13 != v2)\n ;\n }\n v3 = ((unsigned short)v1 + 16) & 4080;\n v4 = alloca(v3);\n if ((((unsigned short)v1 + 16) & 4080) != 0)\n *(uint64_t *)&v13[v3 - 8] = *(uint64_t *)&v13[v3 - 8];\n v5 = *dest;\n if (*dest) {\n v6 = __ctype_b_loc();\n v7 = 0;\n v8 = *v6;\n v9 = dest + 1;\n do {\n if ((v8[v5] & 8) != 0) {\n v10 = v7++;\n v13[v10] = v5;\n }\n v5 = *v9++;\n } while (v5);\n } else {\n v7 = 0;\n }\n v13[v7] = 0;\n strcpy(dest, v13);\n return dest;\n}" + }, + { + "index": 173, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* text) {\n int i = 0, j = 0;\n char temp[strlen(text) + 1];\n while (text[i]) {\n if (isalnum(text[i])) {\n temp[j++] = text[i];\n }\n i++;\n }\n temp[j] = '\\0';\n strcpy(text, temp);\n return text;\n}", + "test": "int main() {\n\n char text1[] = \"python @#&^%$*program123\";\n\n char text2[] = \"python %^$@!^&*() programming24%$^^() language\";\n\n char text3[] = \"python ^%&^()(+_)(_^&67) program\";\n\n \n\n assert(strcmp(func0(text1), \"pythonprogram123\") == 0);\n\n assert(strcmp(func0(text2), \"pythonprogramming24language\") == 0);\n\n assert(strcmp(func0(text3), \"python67program\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r13\npush %r12\nmov %rdi,%r12\npush %rbx\nsub $0x18,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x28(%rbp)\nxor %eax,%eax\ncallq 10a0 \nmov %rsp,%rdi\nadd $0x10,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rdi\nand $0xfffffffffffffff0,%rdx\nmov %rdi,%rax\ncmp %rax,%rsp\nje 13cc \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 13b7 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 1470 \nmovzbl (%r12),%ebx\nmov %rsp,%r13\ntest %bl,%bl\nje 147b \ncallq 10d0 <__ctype_b_loc@plt>\nxor %edx,%edx\nmov (%rax),%rsi\nlea 0x1(%r12),%rax\nnopl (%rax)\nmovsbq %bl,%rcx\ntestb $0x8,(%rsi,%rcx,2)\nje 142b \nadd $0x1,%rax\nmov %bl,0x0(%r13,%rdx,1)\nlea 0x1(%rdx),%ecx\nmovzbl -0x1(%rax),%ebx\ntest %bl,%bl\nje 1438 \nmovslq %ecx,%rdx\nmovsbq %bl,%rcx\ntestb $0x8,(%rsi,%rcx,2)\njne 140a \nmovzbl (%rax),%ebx\nadd $0x1,%rax\ntest %bl,%bl\njne 1400 \nmov %edx,%ecx\nmovslq %ecx,%rcx\nmov %r13,%rsi\nmov %r12,%rdi\nmovb $0x0,0x0(%r13,%rcx,1)\ncallq 1090 \nmov -0x28(%rbp),%rax\nxor %fs:0x28,%rax\njne 147f \nlea -0x18(%rbp),%rsp\nmov %r12,%rax\npop %rbx\npop %r12\npop %r13\npop %rbp\nretq\nnopl 0x0(%rax)\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 13de \nxor %ecx,%ecx\njmp 1438 \ncallq 10b0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r13\npush r12\nmov r12, rdi\npush rbx\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\ncall _strlen\nmov rcx, rsp\nadd rax, 10h\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_13B9\nloc_13A4:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rcx\njnz short loc_13A4\nloc_13B9:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1450\nloc_13CB:\nmovzx ebx, byte ptr [r12]\nmov r13, rsp\ntest bl, bl\njz loc_145B\ncall ___ctype_b_loc\nxor edx, edx\nmov rsi, [rax]\nlea rax, [r12+1]\nnop word ptr [rax+rax+00h]\nloc_13F0:\nmovsx rcx, bl\ntest byte ptr [rsi+rcx*2], 8\njz short loc_1440\nadd rax, 1\nmov [r13+rdx+0], bl\nlea ecx, [rdx+1]\nmovzx ebx, byte ptr [rax-1]\nmovsxd rdx, ecx\ntest bl, bl\njnz short loc_13F0\nloc_1411:\nmov byte ptr [r13+rdx+0], 0\nmov rsi, r13; src\nmov rdi, r12; dest\ncall _strcpy\nmov rax, [rbp+var_28]\nsub rax, fs:28h\njnz short loc_145F\nlea rsp, [rbp-18h]\nmov rax, r12\npop rbx\npop r12\npop r13\npop rbp\nretn\nloc_1440:\nmovzx ebx, byte ptr [rax]\nadd rax, 1\ntest bl, bl\njnz short loc_13F0\njmp short loc_1411\nloc_1450:\nor [rsp+rdx+1030h+var_1038], 0\njmp loc_13CB\nloc_145B:\nxor edx, edx\njmp short loc_1411\nloc_145F:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(char *dest)\n{\n size_t v1; // rax\n char *v2; // rcx\n signed __int64 v3; // rdx\n void *v4; // rsp\n char v5; // bl\n const unsigned __int16 **v6; // rax\n __int64 v7; // rdx\n const unsigned __int16 *v8; // rsi\n char *v9; // rax\n char v12[4088]; // [rsp+8h] [rbp-1030h] BYREF\n _QWORD v13[6]; // [rsp+1008h] [rbp-30h] BYREF\n\n v13[1] = __readfsqword(0x28u);\n v1 = strlen(dest);\n v2 = (char *)v13 - ((v1 + 16) & 0xFFFFFFFFFFFFF000LL);\n if ( v13 != (_QWORD *)v2 )\n {\n while ( v12 != v2 )\n ;\n }\n v3 = ((_WORD)v1 + 16) & 0xFF0;\n v4 = alloca(v3);\n if ( (((_WORD)v1 + 16) & 0xFF0) != 0 )\n *(_QWORD *)&v12[v3 - 8] = *(_QWORD *)&v12[v3 - 8];\n v5 = *dest;\n if ( *dest )\n {\n v6 = __ctype_b_loc();\n v7 = 0LL;\n v8 = *v6;\n v9 = dest + 1;\n do\n {\n while ( (v8[v5] & 8) != 0 )\n {\n ++v9;\n v12[v7] = v5;\n v5 = *(v9 - 1);\n v7 = (int)v7 + 1;\n if ( !v5 )\n goto LABEL_9;\n }\n v5 = *v9++;\n }\n while ( v5 );\n }\n else\n {\n v7 = 0LL;\n }\nLABEL_9:\n v12[v7] = 0;\n strcpy(dest, v12);\n return dest;\n}", + "ida_strip_asm": "sub_1360:\nendbr64\npush rbp\nmov rbp, rsp\npush r13\npush r12\nmov r12, rdi\npush rbx\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\ncall _strlen\nmov rcx, rsp\nadd rax, 10h\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_13B9\nloc_13A4:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rcx\njnz short loc_13A4\nloc_13B9:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1450\nloc_13CB:\nmovzx ebx, byte ptr [r12]\nmov r13, rsp\ntest bl, bl\njz loc_145B\ncall ___ctype_b_loc\nxor edx, edx\nmov rsi, [rax]\nlea rax, [r12+1]\nnop word ptr [rax+rax+00h]\nloc_13F0:\nmovsx rcx, bl\ntest byte ptr [rsi+rcx*2], 8\njz short loc_1440\nadd rax, 1\nmov [r13+rdx+0], bl\nlea ecx, [rdx+1]\nmovzx ebx, byte ptr [rax-1]\nmovsxd rdx, ecx\ntest bl, bl\njnz short loc_13F0\nloc_1411:\nmov byte ptr [r13+rdx+0], 0\nmov rsi, r13; src\nmov rdi, r12; dest\ncall _strcpy\nmov rax, [rbp+var_28]\nsub rax, fs:28h\njnz short loc_145F\nlea rsp, [rbp-18h]\nmov rax, r12\npop rbx\npop r12\npop r13\npop rbp\nretn\nloc_1440:\nmovzx ebx, byte ptr [rax]\nadd rax, 1\ntest bl, bl\njnz short loc_13F0\njmp short loc_1411\nloc_1450:\nor [rsp+rdx+1030h+var_1038], 0\njmp loc_13CB\nloc_145B:\nxor edx, edx\njmp short loc_1411\nloc_145F:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_1360(char *dest)\n{\n size_t v1; // rax\n char *v2; // rcx\n signed __int64 v3; // rdx\n void *v4; // rsp\n char v5; // bl\n const unsigned __int16 **v6; // rax\n __int64 v7; // rdx\n const unsigned __int16 *v8; // rsi\n char *v9; // rax\n char v12[4088]; // [rsp+8h] [rbp-1030h] BYREF\n _QWORD v13[6]; // [rsp+1008h] [rbp-30h] BYREF\n\n v13[1] = __readfsqword(0x28u);\n v1 = strlen(dest);\n v2 = (char *)v13 - ((v1 + 16) & 0xFFFFFFFFFFFFF000LL);\n if ( v13 != (_QWORD *)v2 )\n {\n while ( v12 != v2 )\n ;\n }\n v3 = ((_WORD)v1 + 16) & 0xFF0;\n v4 = alloca(v3);\n if ( (((_WORD)v1 + 16) & 0xFF0) != 0 )\n *(_QWORD *)&v12[v3 - 8] = *(_QWORD *)&v12[v3 - 8];\n v5 = *dest;\n if ( *dest )\n {\n v6 = __ctype_b_loc();\n v7 = 0LL;\n v8 = *v6;\n v9 = dest + 1;\n do\n {\n while ( (v8[v5] & 8) != 0 )\n {\n ++v9;\n v12[v7] = v5;\n v5 = *(v9 - 1);\n v7 = (int)v7 + 1;\n if ( !v5 )\n goto LABEL_9;\n }\n v5 = *v9++;\n }\n while ( v5 );\n }\n else\n {\n v7 = 0LL;\n }\nLABEL_9:\n v12[v7] = 0;\n strcpy(dest, v12);\n return dest;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1360(char *dest) {\n unsigned int v1;\n char *v2;\n signed long long v3;\n void *v4;\n char v5;\n const unsigned short **v6;\n long long v7;\n const unsigned short *v8;\n char *v9;\n char v12[4088];\n uint64_t v13[6];\n v13[1] = __readfsqword(40u);\n v1 = strlen(dest);\n v2 = (char *)v13 - ((v1 + 16) & 18446744073709547520LL);\n if (v13 != (uint64_t *)v2) {\n while (v12 != v2)\n ;\n }\n v3 = ((unsigned short)v1 + 16) & 4080;\n v4 = alloca(v3);\n if ((((unsigned short)v1 + 16) & 4080) != 0)\n *(uint64_t *)&v12[v3 - 8] = *(uint64_t *)&v12[v3 - 8];\n v5 = *dest;\n if (*dest) {\n v6 = __ctype_b_loc();\n v7 = 0LL;\n v8 = *v6;\n v9 = dest + 1;\n do {\n while ((v8[v5] & 8) != 0) {\n ++v9;\n v12[v7] = v5;\n v5 = *(v9 - 1);\n v7 = (int)v7 + 1;\n if (!v5) goto LABEL_9;\n }\n v5 = *v9++;\n } while (v5);\n } else {\n v7 = 0LL;\n }\nLABEL_9:\n v12[v7] = 0;\n strcpy(dest, v12);\n return dest;\n}", + "ida_pseudo_norm": "char *func0(char *dest) {\n unsigned int v1;\n char *v2;\n signed long long v3;\n void *v4;\n char v5;\n const unsigned short **v6;\n long long v7;\n const unsigned short *v8;\n char *v9;\n char v12[4088];\n uint64_t v13[6];\n v13[1] = __readfsqword(40u);\n v1 = strlen(dest);\n v2 = (char *)v13 - ((v1 + 16) & 18446744073709547520LL);\n if (v13 != (uint64_t *)v2) {\n while (v12 != v2)\n ;\n }\n v3 = ((unsigned short)v1 + 16) & 4080;\n v4 = alloca(v3);\n if ((((unsigned short)v1 + 16) & 4080) != 0)\n *(uint64_t *)&v12[v3 - 8] = *(uint64_t *)&v12[v3 - 8];\n v5 = *dest;\n if (*dest) {\n v6 = __ctype_b_loc();\n v7 = 0LL;\n v8 = *v6;\n v9 = dest + 1;\n do {\n while ((v8[v5] & 8) != 0) {\n ++v9;\n v12[v7] = v5;\n v5 = *(v9 - 1);\n v7 = (int)v7 + 1;\n if (!v5) goto LABEL_9;\n }\n v5 = *v9++;\n } while (v5);\n } else {\n v7 = 0LL;\n }\nLABEL_9:\n v12[v7] = 0;\n strcpy(dest, v12);\n return dest;\n}" + }, + { + "index": 174, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct Node {\n\n int value;\n\n struct Node *next;\n\n} Node;\n\n\n\ntypedef struct {\n\n char *key;\n\n Node *values;\n\n} KeyValue;\n\n\n\ntypedef struct {\n\n KeyValue *pairs;\n\n int size;\n\n int capacity;\n\n} HashMap;\n\n\n\nvoid appendValue(Node **list, int value) {\n\n Node *new_node = malloc(sizeof(Node));\n\n new_node->value = value;\n\n new_node->next = NULL;\n\n if (*list == NULL) {\n\n *list = new_node;\n\n } else {\n\n Node *current = *list;\n\n while (current->next != NULL) {\n\n current = current->next;\n\n }\n\n current->next = new_node;\n\n }\n\n}\n\n\n\nvoid initHashMap(HashMap *map) {\n\n map->size = 0;\n\n map->capacity = 10;\n\n map->pairs = malloc(map->capacity * sizeof(KeyValue));\n\n}\n\n\n\nvoid insertHashMap(HashMap *map, char *key, int value) {\n\n for (int i = 0; i < map->size; i++) {\n\n if (strcmp(map->pairs[i].key, key) == 0) {\n\n appendValue(&map->pairs[i].values, value);\n\n return;\n\n }\n\n }\n\n if (map->size == map->capacity) {\n\n map->capacity *= 2;\n\n map->pairs = realloc(map->pairs, map->capacity * sizeof(KeyValue));\n\n }\n\n map->pairs[map->size].key = strdup(key);\n\n map->pairs[map->size].values = NULL;\n\n appendValue(&map->pairs[map->size].values, value);\n\n map->size++;\n\n}\n\n\n\n", + "func": "HashMap func0(char l[][2][10], int len) {\n HashMap result;\n initHashMap(&result);\n for (int i = 0; i < len; i++) {\n insertHashMap(&result, l[i][0], atoi(l[i][1]));\n }\n return result;\n}", + "test": "int main() { \n\n char test1[][2][10] = {{\"yellow\", \"1\"}, {\"blue\", \"2\"}, {\"yellow\", \"3\"}, {\"blue\", \"4\"}, {\"red\", \"1\"}};\n\n HashMap result1 = func0(test1, 5);\n\n \n\n char test2[][2][10] = {{\"python\", \"1\"}, {\"python\", \"2\"}, {\"python\", \"3\"}, {\"python\", \"4\"}, {\"python\", \"5\"}};\n\n HashMap result2 = func0(test2, 5);\n\n \n\n char test3[][2][10] = {{\"yellow\", \"100\"}, {\"blue\", \"200\"}, {\"yellow\", \"300\"}, {\"blue\", \"400\"}, {\"red\", \"100\"}};\n\n HashMap result3 = func0(test3, 5);\n\n \n\n assert(result1.size == 3); // manual check summarizing result comparisons\n\n assert(result2.size == 1); // instead of making direct list and map comparisons\n\n assert(result3.size == 3); // as in Python, specific to use case and hash map content\n\n \n\n // Cleanup\n\n for (int i = 0; i < result1.size; i++) free(result1.pairs[i].key);\n\n free(result1.pairs);\n\n for (int i = 0; i < result2.size; i++) free(result2.pairs[i].key);\n\n free(result2.pairs);\n\n for (int i = 0; i < result3.size; i++) free(result3.pairs[i].key);\n\n free(result3.pairs);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x40,%rsp\nmov %rdi,-0x38(%rbp)\nmov %esi,-0x3c(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea -0x20(%rbp),%rax\nmov %rax,%rdi\ncallq 12ad \nmovl $0x0,-0x24(%rbp)\njmp 14e2 \nmov -0x24(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nadd $0xa,%rax\nmov %rax,%rdi\ncallq 1120 \nmov %eax,%ecx\nmov -0x24(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov %rax,%rsi\nlea -0x20(%rbp),%rax\nmov %ecx,%edx\nmov %rax,%rdi\ncallq 12f5 \naddl $0x1,-0x24(%rbp)\nmov -0x24(%rbp),%eax\ncmp -0x3c(%rbp),%eax\njl 1483 \nmov -0x20(%rbp),%rax\nmov -0x18(%rbp),%rdx\nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 1506 \ncallq 10d0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [rbp+var_20]\nmov rdi, rax\ncall initHashMap\nmov [rbp+var_24], 0\njmp short loc_14E1\nloc_1482:\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_38]\nadd rax, rdx\nadd rax, 0Ah\nmov rdi, rax; nptr\ncall _atoi\nmov ecx, eax\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rsi, rax\nlea rax, [rbp+var_20]\nmov edx, ecx\nmov rdi, rax\ncall insertHashMap\nadd [rbp+var_24], 1\nloc_14E1:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_3C]\njl short loc_1482\nmov rax, [rbp+var_20]\nmov rdx, [rbp+var_18]\nmov rcx, [rbp+var_8]\nsub rcx, fs:28h\njz short locret_1505\ncall ___stack_chk_fail\nlocret_1505:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v2; // eax\n int i; // [rsp+1Ch] [rbp-24h]\n _QWORD v5[4]; // [rsp+20h] [rbp-20h] BYREF\n\n v5[3] = __readfsqword(0x28u);\n initHashMap(v5);\n for ( i = 0; i < a2; ++i )\n {\n v2 = atoi((const char *)(20LL * i + a1 + 10));\n insertHashMap(v5, 20LL * i + a1, v2);\n }\n return v5[0];\n}", + "ida_strip_asm": "sub_144B:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [rbp+var_20]\nmov rdi, rax\ncall sub_12AD\nmov [rbp+var_24], 0\njmp short loc_14E1\nloc_1482:\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_38]\nadd rax, rdx\nadd rax, 0Ah\nmov rdi, rax; nptr\ncall _atoi\nmov ecx, eax\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rsi, rax\nlea rax, [rbp+var_20]\nmov edx, ecx\nmov rdi, rax\ncall sub_12F5\nadd [rbp+var_24], 1\nloc_14E1:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_3C]\njl short loc_1482\nmov rax, [rbp+var_20]\nmov rdx, [rbp+var_18]\nmov rcx, [rbp+var_8]\nsub rcx, fs:28h\njz short locret_1505\ncall ___stack_chk_fail\nlocret_1505:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_144B(__int64 a1, int a2)\n{\n unsigned int v2; // eax\n int i; // [rsp+1Ch] [rbp-24h]\n _QWORD v5[4]; // [rsp+20h] [rbp-20h] BYREF\n\n v5[3] = __readfsqword(0x28u);\n sub_12AD(v5);\n for ( i = 0; i < a2; ++i )\n {\n v2 = atoi((const char *)(20LL * i + a1 + 10));\n sub_12F5(v5, 20LL * i + a1, v2);\n }\n return v5[0];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_144B(long long a1, int a2) {\n unsigned int v2;\n int i;\n uint64_t v5[4];\n v5[3] = __readfsqword(40u);\n sub_12AD(v5);\n for (i = 0; i < a2; ++i) {\n v2 = atoi((const char *)(20LL * i + a1 + 10));\n sub_12F5(v5, 20LL * i + a1, v2);\n }\n return v5[0];\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v2;\n int i;\n uint64_t v5[4];\n v5[3] = __readfsqword(40u);\n initHashMap(v5);\n for (i = 0; i < a2; ++i) {\n v2 = atoi((const char *)(20LL * i + a1 + 10));\n insertHashMap(v5, 20LL * i + a1, v2);\n }\n return v5[0];\n}" + }, + { + "index": 174, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct Node {\n\n int value;\n\n struct Node *next;\n\n} Node;\n\n\n\ntypedef struct {\n\n char *key;\n\n Node *values;\n\n} KeyValue;\n\n\n\ntypedef struct {\n\n KeyValue *pairs;\n\n int size;\n\n int capacity;\n\n} HashMap;\n\n\n\nvoid appendValue(Node **list, int value) {\n\n Node *new_node = malloc(sizeof(Node));\n\n new_node->value = value;\n\n new_node->next = NULL;\n\n if (*list == NULL) {\n\n *list = new_node;\n\n } else {\n\n Node *current = *list;\n\n while (current->next != NULL) {\n\n current = current->next;\n\n }\n\n current->next = new_node;\n\n }\n\n}\n\n\n\nvoid initHashMap(HashMap *map) {\n\n map->size = 0;\n\n map->capacity = 10;\n\n map->pairs = malloc(map->capacity * sizeof(KeyValue));\n\n}\n\n\n\nvoid insertHashMap(HashMap *map, char *key, int value) {\n\n for (int i = 0; i < map->size; i++) {\n\n if (strcmp(map->pairs[i].key, key) == 0) {\n\n appendValue(&map->pairs[i].values, value);\n\n return;\n\n }\n\n }\n\n if (map->size == map->capacity) {\n\n map->capacity *= 2;\n\n map->pairs = realloc(map->pairs, map->capacity * sizeof(KeyValue));\n\n }\n\n map->pairs[map->size].key = strdup(key);\n\n map->pairs[map->size].values = NULL;\n\n appendValue(&map->pairs[map->size].values, value);\n\n map->size++;\n\n}\n\n\n\n", + "func": "HashMap func0(char l[][2][10], int len) {\n HashMap result;\n initHashMap(&result);\n for (int i = 0; i < len; i++) {\n insertHashMap(&result, l[i][0], atoi(l[i][1]));\n }\n return result;\n}", + "test": "int main() { \n\n char test1[][2][10] = {{\"yellow\", \"1\"}, {\"blue\", \"2\"}, {\"yellow\", \"3\"}, {\"blue\", \"4\"}, {\"red\", \"1\"}};\n\n HashMap result1 = func0(test1, 5);\n\n \n\n char test2[][2][10] = {{\"python\", \"1\"}, {\"python\", \"2\"}, {\"python\", \"3\"}, {\"python\", \"4\"}, {\"python\", \"5\"}};\n\n HashMap result2 = func0(test2, 5);\n\n \n\n char test3[][2][10] = {{\"yellow\", \"100\"}, {\"blue\", \"200\"}, {\"yellow\", \"300\"}, {\"blue\", \"400\"}, {\"red\", \"100\"}};\n\n HashMap result3 = func0(test3, 5);\n\n \n\n assert(result1.size == 3); // manual check summarizing result comparisons\n\n assert(result2.size == 1); // instead of making direct list and map comparisons\n\n assert(result3.size == 3); // as in Python, specific to use case and hash map content\n\n \n\n // Cleanup\n\n for (int i = 0; i < result1.size; i++) free(result1.pairs[i].key);\n\n free(result1.pairs);\n\n for (int i = 0; i < result2.size; i++) free(result2.pairs[i].key);\n\n free(result2.pairs);\n\n for (int i = 0; i < result3.size; i++) free(result3.pairs[i].key);\n\n free(result3.pairs);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nsub $0x20,%rsp\nmov %rdi,%r12\nmov %esi,%ebp\nmov %fs:0x28,%rax\nmov %rax,0x18(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\ncallq 1270 \ntest %ebp,%ebp\njle 13dc \nlea 0xa(%r12),%rbx\nlea -0x1(%rbp),%eax\nlea (%rax,%rax,4),%rax\nlea 0x1e(%r12,%rax,4),%r12\nmov %rsp,%rbp\nmov $0xa,%edx\nmov $0x0,%esi\nmov %rbx,%rdi\ncallq 1100 \nmov %rax,%rdx\nlea -0xa(%rbx),%rsi\nmov %rbp,%rdi\ncallq 1295 \nadd $0x14,%rbx\ncmp %r12,%rbx\njne 13b2 \nmov (%rsp),%rax\nmov 0x8(%rsp),%rdx\nmov 0x18(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 13fe \nadd $0x20,%rsp\npop %rbx\npop %rbp\npop %r12\nretq\ncallq 10d0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 20h\nmov rbx, rdi\nmov ebp, esi\nmov rax, fs:28h\nmov [rsp+38h+var_20], rax\nxor eax, eax\nmov rdi, rsp\ncall initHashMap\ntest ebp, ebp\njle short loc_13D4\nadd rbx, 0Ah\nmovsxd rbp, ebp\nlea rax, [rbp+rbp*4+0]\nlea r12, [rbx+rax*4]\nmov rbp, rsp\nloc_13AB:\nmov edx, 0Ah; base\nmov esi, 0; endptr\nmov rdi, rbx; nptr\ncall _strtol\nlea rsi, [rbx-0Ah]\nmov edx, eax\nmov rdi, rbp\ncall insertHashMap\nadd rbx, 14h\ncmp rbx, r12\njnz short loc_13AB\nloc_13D4:\nmov rax, [rsp+38h+var_38]\nmov rdx, [rsp+38h+var_30]\nmov rcx, [rsp+38h+var_20]\nsub rcx, fs:28h\njnz short loc_13F6\nadd rsp, 20h\npop rbx\npop rbp\npop r12\nretn\nloc_13F6:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n const char *v2; // rbx\n unsigned int v3; // eax\n _QWORD v5[7]; // [rsp+0h] [rbp-38h] BYREF\n\n v5[3] = __readfsqword(0x28u);\n initHashMap(v5);\n if ( a2 > 0 )\n {\n v2 = (const char *)(a1 + 10);\n do\n {\n v3 = strtol(v2, 0LL, 10);\n insertHashMap(v5, v2 - 10, v3);\n v2 += 20;\n }\n while ( v2 != (const char *)(a1 + 10 + 20LL * a2) );\n }\n return v5[0];\n}", + "ida_strip_asm": "sub_136B:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 20h\nmov rbx, rdi\nmov ebp, esi\nmov rax, fs:28h\nmov [rsp+38h+var_20], rax\nxor eax, eax\nmov rdi, rsp\ncall sub_1270\ntest ebp, ebp\njle short loc_13D4\nadd rbx, 0Ah\nmovsxd rbp, ebp\nlea rax, [rbp+rbp*4+0]\nlea r12, [rbx+rax*4]\nmov rbp, rsp\nloc_13AB:\nmov edx, 0Ah; base\nmov esi, 0; endptr\nmov rdi, rbx; nptr\ncall _strtol\nlea rsi, [rbx-0Ah]\nmov edx, eax\nmov rdi, rbp\ncall sub_1295\nadd rbx, 14h\ncmp rbx, r12\njnz short loc_13AB\nloc_13D4:\nmov rax, [rsp+38h+var_38]\nmov rdx, [rsp+38h+var_30]\nmov rcx, [rsp+38h+var_20]\nsub rcx, fs:28h\njnz short loc_13F6\nadd rsp, 20h\npop rbx\npop rbp\npop r12\nretn\nloc_13F6:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_136B(__int64 a1, int a2)\n{\n const char *v2; // rbx\n unsigned int v3; // eax\n _QWORD v5[7]; // [rsp+0h] [rbp-38h] BYREF\n\n v5[3] = __readfsqword(0x28u);\n sub_1270(v5);\n if ( a2 > 0 )\n {\n v2 = (const char *)(a1 + 10);\n do\n {\n v3 = strtol(v2, 0LL, 10);\n sub_1295(v5, v2 - 10, v3);\n v2 += 20;\n }\n while ( v2 != (const char *)(a1 + 10 + 20LL * a2) );\n }\n return v5[0];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_136B(long long a1, int a2) {\n const char *v2;\n unsigned int v3;\n uint64_t v5[7];\n v5[3] = __readfsqword(40u);\n sub_1270(v5);\n if (a2 > 0) {\n v2 = (const char *)(a1 + 10);\n do {\n v3 = strtol(v2, 0LL, 10);\n sub_1295(v5, v2 - 10, v3);\n v2 += 20;\n } while (v2 != (const char *)(a1 + 10 + 20LL * a2));\n }\n return v5[0];\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n const char *v2;\n unsigned int v3;\n uint64_t v5[7];\n v5[3] = __readfsqword(40u);\n initHashMap(v5);\n if (a2 > 0) {\n v2 = (const char *)(a1 + 10);\n do {\n v3 = strtol(v2, 0LL, 10);\n insertHashMap(v5, v2 - 10, v3);\n v2 += 20;\n } while (v2 != (const char *)(a1 + 10 + 20LL * a2));\n }\n return v5[0];\n}" + }, + { + "index": 174, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct Node {\n\n int value;\n\n struct Node *next;\n\n} Node;\n\n\n\ntypedef struct {\n\n char *key;\n\n Node *values;\n\n} KeyValue;\n\n\n\ntypedef struct {\n\n KeyValue *pairs;\n\n int size;\n\n int capacity;\n\n} HashMap;\n\n\n\nvoid appendValue(Node **list, int value) {\n\n Node *new_node = malloc(sizeof(Node));\n\n new_node->value = value;\n\n new_node->next = NULL;\n\n if (*list == NULL) {\n\n *list = new_node;\n\n } else {\n\n Node *current = *list;\n\n while (current->next != NULL) {\n\n current = current->next;\n\n }\n\n current->next = new_node;\n\n }\n\n}\n\n\n\nvoid initHashMap(HashMap *map) {\n\n map->size = 0;\n\n map->capacity = 10;\n\n map->pairs = malloc(map->capacity * sizeof(KeyValue));\n\n}\n\n\n\nvoid insertHashMap(HashMap *map, char *key, int value) {\n\n for (int i = 0; i < map->size; i++) {\n\n if (strcmp(map->pairs[i].key, key) == 0) {\n\n appendValue(&map->pairs[i].values, value);\n\n return;\n\n }\n\n }\n\n if (map->size == map->capacity) {\n\n map->capacity *= 2;\n\n map->pairs = realloc(map->pairs, map->capacity * sizeof(KeyValue));\n\n }\n\n map->pairs[map->size].key = strdup(key);\n\n map->pairs[map->size].values = NULL;\n\n appendValue(&map->pairs[map->size].values, value);\n\n map->size++;\n\n}\n\n\n\n", + "func": "HashMap func0(char l[][2][10], int len) {\n HashMap result;\n initHashMap(&result);\n for (int i = 0; i < len; i++) {\n insertHashMap(&result, l[i][0], atoi(l[i][1]));\n }\n return result;\n}", + "test": "int main() { \n\n char test1[][2][10] = {{\"yellow\", \"1\"}, {\"blue\", \"2\"}, {\"yellow\", \"3\"}, {\"blue\", \"4\"}, {\"red\", \"1\"}};\n\n HashMap result1 = func0(test1, 5);\n\n \n\n char test2[][2][10] = {{\"python\", \"1\"}, {\"python\", \"2\"}, {\"python\", \"3\"}, {\"python\", \"4\"}, {\"python\", \"5\"}};\n\n HashMap result2 = func0(test2, 5);\n\n \n\n char test3[][2][10] = {{\"yellow\", \"100\"}, {\"blue\", \"200\"}, {\"yellow\", \"300\"}, {\"blue\", \"400\"}, {\"red\", \"100\"}};\n\n HashMap result3 = func0(test3, 5);\n\n \n\n assert(result1.size == 3); // manual check summarizing result comparisons\n\n assert(result2.size == 1); // instead of making direct list and map comparisons\n\n assert(result3.size == 3); // as in Python, specific to use case and hash map content\n\n \n\n // Cleanup\n\n for (int i = 0; i < result1.size; i++) free(result1.pairs[i].key);\n\n free(result1.pairs);\n\n for (int i = 0; i < result2.size; i++) free(result2.pairs[i].key);\n\n free(result2.pairs);\n\n for (int i = 0; i < result3.size; i++) free(result3.pairs[i].key);\n\n free(result3.pairs);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %rdi,%r12\nmov $0xa0,%edi\npush %rbp\nmov %esi,%ebp\npush %rbx\nsub $0x20,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x18(%rsp)\nxor %eax,%eax\nmovabs $0xa00000000,%rax\nmov %rax,0x8(%rsp)\ncallq 1110 \nmov %rax,(%rsp)\ntest %ebp,%ebp\njle 17f7 \nlea -0x1(%rbp),%eax\nlea 0xa(%r12),%rbx\nmov %rsp,%rbp\nlea (%rax,%rax,4),%rax\nlea 0x1e(%r12,%rax,4),%r12\nnopw %cs:0x0(%rax,%rax,1)\nmov %rbx,%rdi\nmov $0xa,%edx\nxor %esi,%esi\ncallq 1100 \nlea -0xa(%rbx),%rsi\nmov %rbp,%rdi\nadd $0x14,%rbx\nmov %rax,%rdx\ncallq 1680 \ncmp %r12,%rbx\njne 17d0 \nmov 0x18(%rsp),%rcx\nxor %fs:0x28,%rcx\nmov (%rsp),%rax\nmov 0x8(%rsp),%rdx\njne 1819 \nadd $0x20,%rsp\npop %rbx\npop %rbp\npop %r12\nretq\ncallq 10d0 <__stack_chk_fail@plt>\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\nmovsxd rbp, esi\npush rbx\nmov rbx, rdi\nmov edi, 0A0h; size\nsub rsp, 20h\nmov rax, fs:28h\nmov [rsp+38h+var_20], rax\nmov rax, 0A00000000h\nmov [rsp+38h+var_30], rax\ncall _malloc\nmov [rsp+38h+var_38], rax\ntest ebp, ebp\njle short loc_170E\nlea rax, [rbp+rbp*4+0]\nadd rbx, 0Ah\nmov rbp, rsp\nlea r12, [rbx+rax*4]\nnop dword ptr [rax+00000000h]\nloc_16E8:\nmov rdi, rbx; nptr\nmov edx, 0Ah; base\nxor esi, esi; endptr\ncall _strtol\nlea rsi, [rbx-0Ah]\nmov rdi, rbp\nadd rbx, 14h\nmov edx, eax\ncall insertHashMap\ncmp rbx, r12\njnz short loc_16E8\nloc_170E:\nmov rax, [rsp+38h+var_38]\nmov rdx, [rsp+38h+var_30]\nmov rcx, [rsp+38h+var_20]\nsub rcx, fs:28h\njnz short loc_1730\nadd rsp, 20h\npop rbx\npop rbp\npop r12\nretn\nloc_1730:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n const char *v2; // rbx\n __int64 v3; // r12\n unsigned int v4; // eax\n const char *v5; // rsi\n _QWORD v7[7]; // [rsp+0h] [rbp-38h] BYREF\n\n v7[3] = __readfsqword(0x28u);\n v7[1] = 0xA00000000LL;\n v7[0] = malloc(0xA0uLL);\n if ( a2 > 0 )\n {\n v2 = (const char *)(a1 + 10);\n v3 = a1 + 10 + 20LL * a2;\n do\n {\n v4 = strtol(v2, 0LL, 10);\n v5 = v2 - 10;\n v2 += 20;\n insertHashMap(v7, v5, v4);\n }\n while ( v2 != (const char *)v3 );\n }\n return v7[0];\n}", + "ida_strip_asm": "sub_1690:\nendbr64\npush r12\npush rbp\nmovsxd rbp, esi\npush rbx\nmov rbx, rdi\nmov edi, 0A0h; size\nsub rsp, 20h\nmov rax, fs:28h\nmov [rsp+38h+var_20], rax\nmov rax, 0A00000000h\nmov [rsp+38h+var_30], rax\ncall _malloc\nmov [rsp+38h+var_38], rax\ntest ebp, ebp\njle short loc_170E\nlea rax, [rbp+rbp*4+0]\nadd rbx, 0Ah\nmov rbp, rsp\nlea r12, [rbx+rax*4]\nnop dword ptr [rax+00000000h]\nloc_16E8:\nmov rdi, rbx; nptr\nmov edx, 0Ah; base\nxor esi, esi; endptr\ncall _strtol\nlea rsi, [rbx-0Ah]\nmov rdi, rbp\nadd rbx, 14h\nmov edx, eax\ncall sub_1560\ncmp rbx, r12\njnz short loc_16E8\nloc_170E:\nmov rax, [rsp+38h+var_38]\nmov rdx, [rsp+38h+var_30]\nmov rcx, [rsp+38h+var_20]\nsub rcx, fs:28h\njnz short loc_1730\nadd rsp, 20h\npop rbx\npop rbp\npop r12\nretn\nloc_1730:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1690(__int64 a1, int a2)\n{\n const char *v2; // rbx\n __int64 v3; // r12\n unsigned int v4; // eax\n const char *v5; // rsi\n _QWORD v7[7]; // [rsp+0h] [rbp-38h] BYREF\n\n v7[3] = __readfsqword(0x28u);\n v7[1] = 0xA00000000LL;\n v7[0] = malloc(0xA0uLL);\n if ( a2 > 0 )\n {\n v2 = (const char *)(a1 + 10);\n v3 = a1 + 10 + 20LL * a2;\n do\n {\n v4 = strtol(v2, 0LL, 10);\n v5 = v2 - 10;\n v2 += 20;\n sub_1560(v7, v5, v4);\n }\n while ( v2 != (const char *)v3 );\n }\n return v7[0];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1690(long long a1, int a2) {\n const char *v2;\n long long v3;\n unsigned int v4;\n const char *v5;\n uint64_t v7[7];\n v7[3] = __readfsqword(40u);\n v7[1] = 42949672960LL;\n v7[0] = malloc(160uLL);\n if (a2 > 0) {\n v2 = (const char *)(a1 + 10);\n v3 = a1 + 10 + 20LL * a2;\n do {\n v4 = strtol(v2, 0LL, 10);\n v5 = v2 - 10;\n v2 += 20;\n sub_1560(v7, v5, v4);\n } while (v2 != (const char *)v3);\n }\n return v7[0];\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n const char *v2;\n long long v3;\n unsigned int v4;\n const char *v5;\n uint64_t v7[7];\n v7[3] = __readfsqword(40u);\n v7[1] = 42949672960LL;\n v7[0] = malloc(160uLL);\n if (a2 > 0) {\n v2 = (const char *)(a1 + 10);\n v3 = a1 + 10 + 20LL * a2;\n do {\n v4 = strtol(v2, 0LL, 10);\n v5 = v2 - 10;\n v2 += 20;\n insertHashMap(v7, v5, v4);\n } while (v2 != (const char *)v3);\n }\n return v7[0];\n}" + }, + { + "index": 174, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct Node {\n\n int value;\n\n struct Node *next;\n\n} Node;\n\n\n\ntypedef struct {\n\n char *key;\n\n Node *values;\n\n} KeyValue;\n\n\n\ntypedef struct {\n\n KeyValue *pairs;\n\n int size;\n\n int capacity;\n\n} HashMap;\n\n\n\nvoid appendValue(Node **list, int value) {\n\n Node *new_node = malloc(sizeof(Node));\n\n new_node->value = value;\n\n new_node->next = NULL;\n\n if (*list == NULL) {\n\n *list = new_node;\n\n } else {\n\n Node *current = *list;\n\n while (current->next != NULL) {\n\n current = current->next;\n\n }\n\n current->next = new_node;\n\n }\n\n}\n\n\n\nvoid initHashMap(HashMap *map) {\n\n map->size = 0;\n\n map->capacity = 10;\n\n map->pairs = malloc(map->capacity * sizeof(KeyValue));\n\n}\n\n\n\nvoid insertHashMap(HashMap *map, char *key, int value) {\n\n for (int i = 0; i < map->size; i++) {\n\n if (strcmp(map->pairs[i].key, key) == 0) {\n\n appendValue(&map->pairs[i].values, value);\n\n return;\n\n }\n\n }\n\n if (map->size == map->capacity) {\n\n map->capacity *= 2;\n\n map->pairs = realloc(map->pairs, map->capacity * sizeof(KeyValue));\n\n }\n\n map->pairs[map->size].key = strdup(key);\n\n map->pairs[map->size].values = NULL;\n\n appendValue(&map->pairs[map->size].values, value);\n\n map->size++;\n\n}\n\n\n\n", + "func": "HashMap func0(char l[][2][10], int len) {\n HashMap result;\n initHashMap(&result);\n for (int i = 0; i < len; i++) {\n insertHashMap(&result, l[i][0], atoi(l[i][1]));\n }\n return result;\n}", + "test": "int main() { \n\n char test1[][2][10] = {{\"yellow\", \"1\"}, {\"blue\", \"2\"}, {\"yellow\", \"3\"}, {\"blue\", \"4\"}, {\"red\", \"1\"}};\n\n HashMap result1 = func0(test1, 5);\n\n \n\n char test2[][2][10] = {{\"python\", \"1\"}, {\"python\", \"2\"}, {\"python\", \"3\"}, {\"python\", \"4\"}, {\"python\", \"5\"}};\n\n HashMap result2 = func0(test2, 5);\n\n \n\n char test3[][2][10] = {{\"yellow\", \"100\"}, {\"blue\", \"200\"}, {\"yellow\", \"300\"}, {\"blue\", \"400\"}, {\"red\", \"100\"}};\n\n HashMap result3 = func0(test3, 5);\n\n \n\n assert(result1.size == 3); // manual check summarizing result comparisons\n\n assert(result2.size == 1); // instead of making direct list and map comparisons\n\n assert(result3.size == 3); // as in Python, specific to use case and hash map content\n\n \n\n // Cleanup\n\n for (int i = 0; i < result1.size; i++) free(result1.pairs[i].key);\n\n free(result1.pairs);\n\n for (int i = 0; i < result2.size; i++) free(result2.pairs[i].key);\n\n free(result2.pairs);\n\n for (int i = 0; i < result3.size; i++) free(result3.pairs[i].key);\n\n free(result3.pairs);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %rdi,%r12\nmov $0xa0,%edi\npush %rbp\nmov %esi,%ebp\npush %rbx\nsub $0x20,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x18(%rsp)\nxor %eax,%eax\nmovabs $0xa00000000,%rax\nmov %rax,0x8(%rsp)\ncallq 1110 \nmov %rax,(%rsp)\ntest %ebp,%ebp\njle 1877 \nlea -0x1(%rbp),%eax\nlea 0xa(%r12),%rbx\nmov %rsp,%rbp\nlea (%rax,%rax,4),%rax\nlea 0x1e(%r12,%rax,4),%r12\nnopw %cs:0x0(%rax,%rax,1)\nmov %rbx,%rdi\nmov $0xa,%edx\nxor %esi,%esi\ncallq 1100 \nlea -0xa(%rbx),%rsi\nmov %rbp,%rdi\nadd $0x14,%rbx\nmov %rax,%rdx\ncallq 1680 \ncmp %r12,%rbx\njne 1850 \nmov 0x18(%rsp),%rcx\nxor %fs:0x28,%rcx\nmov (%rsp),%rax\nmov 0x8(%rsp),%rdx\njne 1899 \nadd $0x20,%rsp\npop %rbx\npop %rbp\npop %r12\nretq\ncallq 10d0 <__stack_chk_fail@plt>\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\nmovsxd rbp, esi\npush rbx\nmov rbx, rdi\nmov edi, 0A0h; size\nsub rsp, 20h\nmov rax, fs:28h\nmov [rsp+38h+var_20], rax\nmov rax, 0A00000000h\nmov [rsp+38h+var_30], rax\ncall _malloc\nmov [rsp+38h+var_38], rax\ntest ebp, ebp\njle short loc_170E\nlea rax, [rbp+rbp*4+0]\nadd rbx, 0Ah\nmov rbp, rsp\nlea r12, [rbx+rax*4]\nnop dword ptr [rax+00000000h]\nloc_16E8:\nmov rdi, rbx; nptr\nmov edx, 0Ah; base\nxor esi, esi; endptr\ncall _strtol\nlea rsi, [rbx-0Ah]\nmov rdi, rbp\nadd rbx, 14h\nmov edx, eax\ncall insertHashMap\ncmp rbx, r12\njnz short loc_16E8\nloc_170E:\nmov rax, [rsp+38h+var_38]\nmov rdx, [rsp+38h+var_30]\nmov rcx, [rsp+38h+var_20]\nsub rcx, fs:28h\njnz short loc_1730\nadd rsp, 20h\npop rbx\npop rbp\npop r12\nretn\nloc_1730:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n const char *v2; // rbx\n __int64 v3; // r12\n unsigned int v4; // eax\n const char *v5; // rsi\n _QWORD v7[7]; // [rsp+0h] [rbp-38h] BYREF\n\n v7[3] = __readfsqword(0x28u);\n v7[1] = 0xA00000000LL;\n v7[0] = malloc(0xA0uLL);\n if ( a2 > 0 )\n {\n v2 = (const char *)(a1 + 10);\n v3 = a1 + 10 + 20LL * a2;\n do\n {\n v4 = strtol(v2, 0LL, 10);\n v5 = v2 - 10;\n v2 += 20;\n insertHashMap(v7, v5, v4);\n }\n while ( v2 != (const char *)v3 );\n }\n return v7[0];\n}", + "ida_strip_asm": "sub_1690:\nendbr64\npush r12\npush rbp\nmovsxd rbp, esi\npush rbx\nmov rbx, rdi\nmov edi, 0A0h; size\nsub rsp, 20h\nmov rax, fs:28h\nmov [rsp+38h+var_20], rax\nmov rax, 0A00000000h\nmov [rsp+38h+var_30], rax\ncall _malloc\nmov [rsp+38h+var_38], rax\ntest ebp, ebp\njle short loc_170E\nlea rax, [rbp+rbp*4+0]\nadd rbx, 0Ah\nmov rbp, rsp\nlea r12, [rbx+rax*4]\nnop dword ptr [rax+00000000h]\nloc_16E8:\nmov rdi, rbx; nptr\nmov edx, 0Ah; base\nxor esi, esi; endptr\ncall _strtol\nlea rsi, [rbx-0Ah]\nmov rdi, rbp\nadd rbx, 14h\nmov edx, eax\ncall sub_1560\ncmp rbx, r12\njnz short loc_16E8\nloc_170E:\nmov rax, [rsp+38h+var_38]\nmov rdx, [rsp+38h+var_30]\nmov rcx, [rsp+38h+var_20]\nsub rcx, fs:28h\njnz short loc_1730\nadd rsp, 20h\npop rbx\npop rbp\npop r12\nretn\nloc_1730:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1690(__int64 a1, int a2)\n{\n const char *v2; // rbx\n __int64 v3; // r12\n unsigned int v4; // eax\n const char *v5; // rsi\n _QWORD v7[7]; // [rsp+0h] [rbp-38h] BYREF\n\n v7[3] = __readfsqword(0x28u);\n v7[1] = 0xA00000000LL;\n v7[0] = malloc(0xA0uLL);\n if ( a2 > 0 )\n {\n v2 = (const char *)(a1 + 10);\n v3 = a1 + 10 + 20LL * a2;\n do\n {\n v4 = strtol(v2, 0LL, 10);\n v5 = v2 - 10;\n v2 += 20;\n sub_1560(v7, v5, v4);\n }\n while ( v2 != (const char *)v3 );\n }\n return v7[0];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1690(long long a1, int a2) {\n const char *v2;\n long long v3;\n unsigned int v4;\n const char *v5;\n uint64_t v7[7];\n v7[3] = __readfsqword(40u);\n v7[1] = 42949672960LL;\n v7[0] = malloc(160uLL);\n if (a2 > 0) {\n v2 = (const char *)(a1 + 10);\n v3 = a1 + 10 + 20LL * a2;\n do {\n v4 = strtol(v2, 0LL, 10);\n v5 = v2 - 10;\n v2 += 20;\n sub_1560(v7, v5, v4);\n } while (v2 != (const char *)v3);\n }\n return v7[0];\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n const char *v2;\n long long v3;\n unsigned int v4;\n const char *v5;\n uint64_t v7[7];\n v7[3] = __readfsqword(40u);\n v7[1] = 42949672960LL;\n v7[0] = malloc(160uLL);\n if (a2 > 0) {\n v2 = (const char *)(a1 + 10);\n v3 = a1 + 10 + 20LL * a2;\n do {\n v4 = strtol(v2, 0LL, 10);\n v5 = v2 - 10;\n v2 += 20;\n insertHashMap(v7, v5, v4);\n } while (v2 != (const char *)v3);\n }\n return v7[0];\n}" + }, + { + "index": 175, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(char* str1) {\n char stack[100];\n int top = -1;\n for (int i = 0; i < strlen(str1); i++) {\n char parenthese = str1[i];\n if (parenthese == '(' || parenthese == '{' || parenthese == '[') {\n stack[++top] = parenthese;\n } else if (top == -1) {\n return false;\n } else {\n char popped = stack[top--];\n if ((parenthese == ')' && popped != '(') ||\n (parenthese == '}' && popped != '{') ||\n (parenthese == ']' && popped != '[')) {\n return false;\n }\n }\n }\n return top == -1;\n}", + "test": "int main() {\n\n assert(func0(\"(){}[]\") == true);\n\n assert(func0(\"()[{)}\") == false);\n\n assert(func0(\"()\") == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x98,%rsp\nmov %rdi,-0x98(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmovl $0xffffffff,-0x88(%rbp)\nmovl $0x0,-0x84(%rbp)\njmpq 128e \nmov -0x84(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x98(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmov %al,-0x8a(%rbp)\ncmpb $0x28,-0x8a(%rbp)\nje 11ff \ncmpb $0x7b,-0x8a(%rbp)\nje 11ff \ncmpb $0x5b,-0x8a(%rbp)\njne 121b \naddl $0x1,-0x88(%rbp)\nmov -0x88(%rbp),%eax\ncltq\nmovzbl -0x8a(%rbp),%edx\nmov %dl,-0x80(%rbp,%rax,1)\njmp 1287 \ncmpl $0xffffffff,-0x88(%rbp)\njne 122e \nmov $0x0,%eax\njmpq 12b9 \nmov -0x88(%rbp),%eax\nlea -0x1(%rax),%edx\nmov %edx,-0x88(%rbp)\ncltq\nmovzbl -0x80(%rbp,%rax,1),%eax\nmov %al,-0x89(%rbp)\ncmpb $0x29,-0x8a(%rbp)\njne 125c \ncmpb $0x28,-0x89(%rbp)\njne 1280 \ncmpb $0x7d,-0x8a(%rbp)\njne 126e \ncmpb $0x7b,-0x89(%rbp)\njne 1280 \ncmpb $0x5d,-0x8a(%rbp)\njne 1287 \ncmpb $0x5b,-0x89(%rbp)\nje 1287 \nmov $0x0,%eax\njmp 12b9 \naddl $0x1,-0x84(%rbp)\nmov -0x84(%rbp),%eax\nmovslq %eax,%rbx\nmov -0x98(%rbp),%rax\nmov %rax,%rdi\ncallq 1070 \ncmp %rax,%rbx\njb 11c8 \ncmpl $0xffffffff,-0x88(%rbp)\nsete %al\nmov -0x18(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 12cd \ncallq 1080 <__stack_chk_fail@plt>\nadd $0x98,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 98h\nmov [rbp+s], rdi\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov [rbp+var_88], 0FFFFFFFFh\nmov [rbp+var_84], 0\njmp loc_128E\nloc_11C8:\nmov eax, [rbp+var_84]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_8A], al\ncmp [rbp+var_8A], 28h ; '('\njz short loc_11FF\ncmp [rbp+var_8A], 7Bh ; '{'\njz short loc_11FF\ncmp [rbp+var_8A], 5Bh ; '['\njnz short loc_121B\nloc_11FF:\nadd [rbp+var_88], 1\nmov eax, [rbp+var_88]\ncdqe\nmovzx edx, [rbp+var_8A]\nmov [rbp+rax+var_80], dl\njmp short loc_1287\nloc_121B:\ncmp [rbp+var_88], 0FFFFFFFFh\njnz short loc_122E\nmov eax, 0\njmp loc_12B9\nloc_122E:\nmov eax, [rbp+var_88]\nlea edx, [rax-1]\nmov [rbp+var_88], edx\ncdqe\nmovzx eax, [rbp+rax+var_80]\nmov [rbp+var_89], al\ncmp [rbp+var_8A], 29h ; ')'\njnz short loc_125C\ncmp [rbp+var_89], 28h ; '('\njnz short loc_1280\nloc_125C:\ncmp [rbp+var_8A], 7Dh ; '}'\njnz short loc_126E\ncmp [rbp+var_89], 7Bh ; '{'\njnz short loc_1280\nloc_126E:\ncmp [rbp+var_8A], 5Dh ; ']'\njnz short loc_1287\ncmp [rbp+var_89], 5Bh ; '['\njz short loc_1287\nloc_1280:\nmov eax, 0\njmp short loc_12B9\nloc_1287:\nadd [rbp+var_84], 1\nloc_128E:\nmov eax, [rbp+var_84]\nmovsxd rbx, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rbx, rax\njb loc_11C8\ncmp [rbp+var_88], 0FFFFFFFFh\nsetz al\nloc_12B9:\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njz short loc_12CD\ncall ___stack_chk_fail\nloc_12CD:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "bool __fastcall func0(const char *a1)\n{\n int v2; // eax\n char v3; // [rsp+16h] [rbp-8Ah]\n char v4; // [rsp+17h] [rbp-89h]\n int v5; // [rsp+18h] [rbp-88h]\n int i; // [rsp+1Ch] [rbp-84h]\n _BYTE v7[104]; // [rsp+20h] [rbp-80h]\n unsigned __int64 v8; // [rsp+88h] [rbp-18h]\n\n v8 = __readfsqword(0x28u);\n v5 = -1;\n for ( i = 0; i < strlen(a1); ++i )\n {\n v3 = a1[i];\n if ( v3 == 40 || v3 == 123 || v3 == 91 )\n {\n v7[++v5] = v3;\n }\n else\n {\n if ( v5 == -1 )\n return 0;\n v2 = v5--;\n v4 = v7[v2];\n if ( v3 == 41 && v4 != 40 || v3 == 125 && v4 != 123 || v3 == 93 && v4 != 91 )\n return 0;\n }\n }\n return v5 == -1;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 98h\nmov [rbp+s], rdi\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov [rbp+var_88], 0FFFFFFFFh\nmov [rbp+var_84], 0\njmp loc_128E\nloc_11C8:\nmov eax, [rbp+var_84]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_8A], al\ncmp [rbp+var_8A], 28h ; '('\njz short loc_11FF\ncmp [rbp+var_8A], 7Bh ; '{'\njz short loc_11FF\ncmp [rbp+var_8A], 5Bh ; '['\njnz short loc_121B\nloc_11FF:\nadd [rbp+var_88], 1\nmov eax, [rbp+var_88]\ncdqe\nmovzx edx, [rbp+var_8A]\nmov [rbp+rax+var_80], dl\njmp short loc_1287\nloc_121B:\ncmp [rbp+var_88], 0FFFFFFFFh\njnz short loc_122E\nmov eax, 0\njmp loc_12B9\nloc_122E:\nmov eax, [rbp+var_88]\nlea edx, [rax-1]\nmov [rbp+var_88], edx\ncdqe\nmovzx eax, [rbp+rax+var_80]\nmov [rbp+var_89], al\ncmp [rbp+var_8A], 29h ; ')'\njnz short loc_125C\ncmp [rbp+var_89], 28h ; '('\njnz short loc_1280\nloc_125C:\ncmp [rbp+var_8A], 7Dh ; '}'\njnz short loc_126E\ncmp [rbp+var_89], 7Bh ; '{'\njnz short loc_1280\nloc_126E:\ncmp [rbp+var_8A], 5Dh ; ']'\njnz short loc_1287\ncmp [rbp+var_89], 5Bh ; '['\njz short loc_1287\nloc_1280:\nmov eax, 0\njmp short loc_12B9\nloc_1287:\nadd [rbp+var_84], 1\nloc_128E:\nmov eax, [rbp+var_84]\nmovsxd rbx, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rbx, rax\njb loc_11C8\ncmp [rbp+var_88], 0FFFFFFFFh\nsetz al\nloc_12B9:\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njz short loc_12CD\ncall ___stack_chk_fail\nloc_12CD:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "bool __fastcall sub_1189(const char *a1)\n{\n int v2; // eax\n char v3; // [rsp+16h] [rbp-8Ah]\n char v4; // [rsp+17h] [rbp-89h]\n int v5; // [rsp+18h] [rbp-88h]\n int i; // [rsp+1Ch] [rbp-84h]\n _BYTE v7[104]; // [rsp+20h] [rbp-80h]\n unsigned __int64 v8; // [rsp+88h] [rbp-18h]\n\n v8 = __readfsqword(0x28u);\n v5 = -1;\n for ( i = 0; i < strlen(a1); ++i )\n {\n v3 = a1[i];\n if ( v3 == 40 || v3 == 123 || v3 == 91 )\n {\n v7[++v5] = v3;\n }\n else\n {\n if ( v5 == -1 )\n return 0;\n v2 = v5--;\n v4 = v7[v2];\n if ( v3 == 41 && v4 != 40 || v3 == 125 && v4 != 123 || v3 == 93 && v4 != 91 )\n return 0;\n }\n }\n return v5 == -1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_1189(const char *a1) {\n int v2;\n char v3;\n char v4;\n int v5;\n int i;\n uint8_t v7[104];\n unsigned long long v8;\n v8 = __readfsqword(40u);\n v5 = -1;\n for (i = 0; i < strlen(a1); ++i) {\n v3 = a1[i];\n if (v3 == 40 || v3 == 123 || v3 == 91) {\n v7[++v5] = v3;\n } else {\n if (v5 == -1) return 0;\n v2 = v5--;\n v4 = v7[v2];\n if (v3 == 41 && v4 != 40 || v3 == 125 && v4 != 123 ||\n v3 == 93 && v4 != 91)\n return 0;\n }\n }\n return v5 == -1;\n}", + "ida_pseudo_norm": "bool func0(const char *a1) {\n int v2;\n char v3;\n char v4;\n int v5;\n int i;\n uint8_t v7[104];\n unsigned long long v8;\n v8 = __readfsqword(40u);\n v5 = -1;\n for (i = 0; i < strlen(a1); ++i) {\n v3 = a1[i];\n if (v3 == 40 || v3 == 123 || v3 == 91) {\n v7[++v5] = v3;\n } else {\n if (v5 == -1) return 0;\n v2 = v5--;\n v4 = v7[v2];\n if (v3 == 41 && v4 != 40 || v3 == 125 && v4 != 123 ||\n v3 == 93 && v4 != 91)\n return 0;\n }\n }\n return v5 == -1;\n}" + }, + { + "index": 175, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(char* str1) {\n char stack[100];\n int top = -1;\n for (int i = 0; i < strlen(str1); i++) {\n char parenthese = str1[i];\n if (parenthese == '(' || parenthese == '{' || parenthese == '[') {\n stack[++top] = parenthese;\n } else if (top == -1) {\n return false;\n } else {\n char popped = stack[top--];\n if ((parenthese == ')' && popped != '(') ||\n (parenthese == '}' && popped != '{') ||\n (parenthese == ']' && popped != '[')) {\n return false;\n }\n }\n }\n return top == -1;\n}", + "test": "int main() {\n\n assert(func0(\"(){}[]\") == true);\n\n assert(func0(\"()[{)}\") == false);\n\n assert(func0(\"()\") == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nsub $0x70,%rsp\nmov %rdi,%r9\nmov %fs:0x28,%rax\nmov %rax,0x68(%rsp)\nxor %eax,%eax\nmov $0x0,%esi\nmov $0xffffffff,%r8d\nmov $0xffffffffffffffff,%r10\njmp 11e8 \ncmp $0xffffffff,%r8d\nje 122b \nlea -0x1(%r8),%ebx\nmovslq %r8d,%r8\nmovzbl (%rsp,%r8,1),%r8d\ncmp $0x29,%cl\nsete %dil\ncmp $0x28,%r8b\nsetne %r11b\nand %r11b,%dil\njne 122b \ncmp $0x7d,%cl\nsete %dl\ncmp $0x7b,%r8b\nsetne %r11b\nand %r11b,%dl\njne 1243 \ncmp $0x5d,%cl\njne 11e1 \ncmp $0x5b,%r8b\njne 122b \nmov %ebx,%r8d\nadd $0x1,%rsi\nmov %r10,%rcx\nmov %r9,%rdi\nrepnz scas %es:(%rdi),%al\nnot %rcx\nsub $0x1,%rcx\ncmp %rsi,%rcx\njbe 1224 \nmovzbl (%r9,%rsi,1),%ecx\nmov %ecx,%edx\nand $0xffffffdf,%edx\ncmp $0x5b,%dl\nsete %dl\ncmp $0x28,%cl\nsete %dil\nor %dil,%dl\nje 1199 \nadd $0x1,%r8d\nmovslq %r8d,%rdx\nmov %cl,(%rsp,%rdx,1)\njmp 11e4 \ncmp $0xffffffff,%r8d\nsete %dl\nmov 0x68(%rsp),%rax\nxor %fs:0x28,%rax\njne 1247 \nmov %edx,%eax\nadd $0x70,%rsp\npop %rbx\nretq\nmov %edi,%edx\njmp 122b \ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 70h\nmov rbp, rdi\nmov rax, fs:28h\nmov [rsp+88h+var_20], rax\nxor eax, eax\nmov ebx, 0\nmov r12d, 0FFFFFFFFh\njmp short loc_1200\nloc_11B5:\ncmp r12d, 0FFFFFFFFh\njz short loc_1239\nlea r8d, [r12-1]\nmovsxd r12, r12d\nmovzx esi, [rsp+r12+88h+var_88]\ncmp dl, 29h ; ')'\nsetz cl\ncmp sil, 28h ; '('\nsetnz dil\nand cl, dil\njnz short loc_1239\ncmp dl, 7Dh ; '}'\nsetz al\ncmp sil, 7Bh ; '{'\nsetnz dil\nand al, dil\njnz short loc_1252\ncmp dl, 5Dh ; ']'\njnz short loc_11F9\ncmp sil, 5Bh ; '['\njnz short loc_1239\nloc_11F9:\nmov r12d, r8d\nloc_11FC:\nadd rbx, 1\nloc_1200:\nmov rdi, rbp; s\ncall _strlen\ncmp rbx, rax\njnb short loc_1232\nmovzx edx, byte ptr [rbp+rbx+0]\nmov eax, edx\nand eax, 0FFFFFFDFh\ncmp al, 5Bh ; '['\nsetz al\ncmp dl, 28h ; '('\nsetz cl\nor al, cl\njz short loc_11B5\nadd r12d, 1\nmovsxd rax, r12d\nmov [rsp+rax+88h+var_88], dl\njmp short loc_11FC\nloc_1232:\ncmp r12d, 0FFFFFFFFh\nsetz al\nloc_1239:\nmov rdx, [rsp+88h+var_20]\nsub rdx, fs:28h\njnz short loc_1256\nadd rsp, 70h\npop rbx\npop rbp\npop r12\nretn\nloc_1252:\nmov eax, ecx\njmp short loc_1239\nloc_1256:\ncall ___stack_chk_fail", + "ida_pseudo": "bool __fastcall func0(char *s)\n{\n size_t v1; // rbx\n int v2; // r12d\n char v3; // si\n bool result; // al\n char v5; // dl\n _BYTE v6[104]; // [rsp+0h] [rbp-88h]\n unsigned __int64 v7; // [rsp+68h] [rbp-20h]\n\n v7 = __readfsqword(0x28u);\n v1 = 0LL;\n v2 = -1;\n while ( 1 )\n {\n if ( v1 >= strlen(s) )\n return v2 == -1;\n v5 = s[v1];\n result = v5 == 40 || (v5 & 0xDF) == 91;\n if ( result )\n {\n v6[++v2] = v5;\n goto LABEL_8;\n }\n if ( v2 == -1 )\n return result;\n v3 = v6[v2];\n if ( v3 != 40 && v5 == 41 )\n return result;\n result = v3 != 123 && v5 == 125;\n if ( result )\n return v3 != 40 && v5 == 41;\n if ( v5 == 93 && v3 != 91 )\n return result;\n --v2;\nLABEL_8:\n ++v1;\n }\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 70h\nmov rbp, rdi\nmov rax, fs:28h\nmov [rsp+88h+var_20], rax\nxor eax, eax\nmov ebx, 0\nmov r12d, 0FFFFFFFFh\njmp short loc_1200\nloc_11B5:\ncmp r12d, 0FFFFFFFFh\njz short loc_1239\nlea r8d, [r12-1]\nmovsxd r12, r12d\nmovzx esi, [rsp+r12+88h+var_88]\ncmp dl, 29h ; ')'\nsetz cl\ncmp sil, 28h ; '('\nsetnz dil\nand cl, dil\njnz short loc_1239\ncmp dl, 7Dh ; '}'\nsetz al\ncmp sil, 7Bh ; '{'\nsetnz dil\nand al, dil\njnz short loc_1252\ncmp dl, 5Dh ; ']'\njnz short loc_11F9\ncmp sil, 5Bh ; '['\njnz short loc_1239\nloc_11F9:\nmov r12d, r8d\nloc_11FC:\nadd rbx, 1\nloc_1200:\nmov rdi, rbp; s\ncall _strlen\ncmp rbx, rax\njnb short loc_1232\nmovzx edx, byte ptr [rbp+rbx+0]\nmov eax, edx\nand eax, 0FFFFFFDFh\ncmp al, 5Bh ; '['\nsetz al\ncmp dl, 28h ; '('\nsetz cl\nor al, cl\njz short loc_11B5\nadd r12d, 1\nmovsxd rax, r12d\nmov [rsp+rax+88h+var_88], dl\njmp short loc_11FC\nloc_1232:\ncmp r12d, 0FFFFFFFFh\nsetz al\nloc_1239:\nmov rdx, [rsp+88h+var_20]\nsub rdx, fs:28h\njnz short loc_1256\nadd rsp, 70h\npop rbx\npop rbp\npop r12\nretn\nloc_1252:\nmov eax, ecx\njmp short loc_1239\nloc_1256:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "bool __fastcall sub_1189(char *s)\n{\n size_t v1; // rbx\n int v2; // r12d\n char v3; // si\n bool result; // al\n char v5; // dl\n _BYTE v6[104]; // [rsp+0h] [rbp-88h]\n unsigned __int64 v7; // [rsp+68h] [rbp-20h]\n\n v7 = __readfsqword(0x28u);\n v1 = 0LL;\n v2 = -1;\n while ( 1 )\n {\n if ( v1 >= strlen(s) )\n return v2 == -1;\n v5 = s[v1];\n result = v5 == 40 || (v5 & 0xDF) == 91;\n if ( result )\n {\n v6[++v2] = v5;\n goto LABEL_8;\n }\n if ( v2 == -1 )\n return result;\n v3 = v6[v2];\n if ( v3 != 40 && v5 == 41 )\n return result;\n result = v3 != 123 && v5 == 125;\n if ( result )\n return v3 != 40 && v5 == 41;\n if ( v5 == 93 && v3 != 91 )\n return result;\n --v2;\nLABEL_8:\n ++v1;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_1189(char *s) {\n unsigned int v1;\n int v2;\n char v3;\n bool result;\n char v5;\n uint8_t v6[104];\n unsigned long long v7;\n v7 = __readfsqword(40u);\n v1 = 0LL;\n v2 = -1;\n while (1) {\n if (v1 >= strlen(s)) return v2 == -1;\n v5 = s[v1];\n result = v5 == 40 || (v5 & 223) == 91;\n if (result) {\n v6[++v2] = v5;\n goto LABEL_8;\n }\n if (v2 == -1) return result;\n v3 = v6[v2];\n if (v3 != 40 && v5 == 41) return result;\n result = v3 != 123 && v5 == 125;\n if (result) return v3 != 40 && v5 == 41;\n if (v5 == 93 && v3 != 91) return result;\n --v2;\n LABEL_8:\n ++v1;\n }\n}", + "ida_pseudo_norm": "bool func0(char *s) {\n unsigned int v1;\n int v2;\n char v3;\n bool result;\n char v5;\n uint8_t v6[104];\n unsigned long long v7;\n v7 = __readfsqword(40u);\n v1 = 0LL;\n v2 = -1;\n while (1) {\n if (v1 >= strlen(s)) return v2 == -1;\n v5 = s[v1];\n result = v5 == 40 || (v5 & 223) == 91;\n if (result) {\n v6[++v2] = v5;\n goto LABEL_8;\n }\n if (v2 == -1) return result;\n v3 = v6[v2];\n if (v3 != 40 && v5 == 41) return result;\n result = v3 != 123 && v5 == 125;\n if (result) return v3 != 40 && v5 == 41;\n if (v5 == 93 && v3 != 91) return result;\n --v2;\n LABEL_8:\n ++v1;\n }\n}" + }, + { + "index": 175, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(char* str1) {\n char stack[100];\n int top = -1;\n for (int i = 0; i < strlen(str1); i++) {\n char parenthese = str1[i];\n if (parenthese == '(' || parenthese == '{' || parenthese == '[') {\n stack[++top] = parenthese;\n } else if (top == -1) {\n return false;\n } else {\n char popped = stack[top--];\n if ((parenthese == ')' && popped != '(') ||\n (parenthese == '}' && popped != '{') ||\n (parenthese == ']' && popped != '[')) {\n return false;\n }\n }\n }\n return top == -1;\n}", + "test": "int main() {\n\n assert(func0(\"(){}[]\") == true);\n\n assert(func0(\"()[{)}\") == false);\n\n assert(func0(\"()\") == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\nsub $0x70,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x68(%rsp)\nxor %eax,%eax\ncallq 1070 \nxor %ecx,%ecx\nmov $0xffffffff,%esi\nmov %rax,%rdi\njmp 126e \nnopl (%rax)\nadd $0x1,%esi\nmovslq %esi,%r8\nmov %dl,(%rsp,%r8,1)\nadd $0x1,%rcx\ncmp %rdi,%rcx\njae 1300 \nmovzbl (%rbx,%rcx,1),%edx\nmov %edx,%r8d\nand $0xffffffdf,%r8d\ncmp $0x5b,%r8b\nsete %al\ncmp $0x28,%dl\nsete %r8b\nor %r8b,%al\njne 1260 \ncmp $0xffffffff,%esi\nje 12e0 \nlea -0x1(%rsi),%r10d\nmovslq %esi,%rsi\ncmp $0x29,%dl\nmovzbl (%rsp,%rsi,1),%esi\nsete %r9b\ncmp $0x28,%sil\nsetne %r8b\ntest %r8b,%r9b\njne 12e0 \ncmp $0x7d,%dl\nsete %al\ncmp $0x7b,%sil\nsetne %r8b\nand %r8b,%al\njne 12dc \ncmp $0x5d,%dl\njne 12d7 \ncmp $0x5b,%sil\njne 12e0 \nmov %r10d,%esi\njmp 126a \nxor %eax,%eax\nxchg %ax,%ax\nmov 0x68(%rsp),%rbx\nxor %fs:0x28,%rbx\njne 1308 \nadd $0x70,%rsp\npop %rbx\nretq\nnopw %cs:0x0(%rax,%rax,1)\ncmp $0xffffffff,%esi\nsete %al\njmp 12e0 \ncallq 1080 <__stack_chk_fail@plt>\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r12\nmov r12d, 0FFFFFFFFh\npush rbp\nmov rbp, rdi\npush rbx\nxor ebx, ebx\nsub rsp, 70h\nmov rax, fs:28h\nmov [rsp+88h+var_20], rax\nxor eax, eax\njmp short loc_126E\nloc_1260:\nadd r12d, 1\nmovsxd rax, r12d\nmov [rsp+rax+88h+var_88], dl\nloc_126A:\nadd rbx, 1\nloc_126E:\nmov rdi, rbp; s\ncall _strlen\ncmp rbx, rax\njnb short loc_12E0\nmovzx edx, byte ptr [rbp+rbx+0]\nmov eax, edx\nand eax, 0FFFFFFDFh\ncmp al, 5Bh ; '['\nsetz al\ncmp dl, 28h ; '('\nsetz cl\nor al, cl\njnz short loc_1260\ncmp r12d, 0FFFFFFFFh\njz short loc_12E7\nlea r8d, [r12-1]\nmovsxd r12, r12d\ncmp dl, 29h ; ')'\nmovzx ecx, [rsp+r12+88h+var_88]\nsetz dil\ncmp cl, 28h ; '('\nsetnz sil\ntest dil, sil\njnz short loc_12E7\ncmp dl, 7Dh ; '}'\nsetz al\ncmp cl, 7Bh ; '{'\nsetnz sil\nand al, sil\njnz short loc_1300\ncmp dl, 5Dh ; ']'\njnz short loc_12D6\ncmp cl, 5Bh ; '['\njnz short loc_12E7\nloc_12D6:\nmov r12d, r8d\njmp short loc_126A\nloc_12E0:\ncmp r12d, 0FFFFFFFFh\nsetz al\nloc_12E7:\nmov rdx, [rsp+88h+var_20]\nsub rdx, fs:28h\njnz short loc_1304\nadd rsp, 70h\npop rbx\npop rbp\npop r12\nretn\nloc_1300:\nxor eax, eax\njmp short loc_12E7\nloc_1304:\ncall ___stack_chk_fail", + "ida_pseudo": "bool __fastcall func0(char *s)\n{\n int v1; // r12d\n size_t v2; // rbx\n char v3; // dl\n bool result; // al\n char v5; // cl\n _BYTE v6[104]; // [rsp+0h] [rbp-88h]\n unsigned __int64 v7; // [rsp+68h] [rbp-20h]\n\n v1 = -1;\n v2 = 0LL;\n v7 = __readfsqword(0x28u);\n while ( 1 )\n {\n if ( v2 >= strlen(s) )\n return v1 == -1;\n v3 = s[v2];\n result = v3 == 40 || (v3 & 0xDF) == 91;\n if ( result )\n {\n v6[++v1] = v3;\n goto LABEL_3;\n }\n if ( v1 == -1 )\n return result;\n v5 = v6[v1];\n if ( v5 != 40 && v3 == 41 )\n return result;\n result = v5 != 123 && v3 == 125;\n if ( result )\n return 0;\n if ( v3 == 93 && v5 != 91 )\n return result;\n --v1;\nLABEL_3:\n ++v2;\n }\n}", + "ida_strip_asm": "sub_1230:\nendbr64\npush r12\nmov r12d, 0FFFFFFFFh\npush rbp\nmov rbp, rdi\npush rbx\nxor ebx, ebx\nsub rsp, 70h\nmov rax, fs:28h\nmov [rsp+88h+var_20], rax\nxor eax, eax\njmp short loc_126E\nloc_1260:\nadd r12d, 1\nmovsxd rax, r12d\nmov [rsp+rax+88h+var_88], dl\nloc_126A:\nadd rbx, 1\nloc_126E:\nmov rdi, rbp; s\ncall _strlen\ncmp rbx, rax\njnb short loc_12E0\nmovzx edx, byte ptr [rbp+rbx+0]\nmov eax, edx\nand eax, 0FFFFFFDFh\ncmp al, 5Bh ; '['\nsetz al\ncmp dl, 28h ; '('\nsetz cl\nor al, cl\njnz short loc_1260\ncmp r12d, 0FFFFFFFFh\njz short loc_12E7\nlea r8d, [r12-1]\nmovsxd r12, r12d\ncmp dl, 29h ; ')'\nmovzx ecx, [rsp+r12+88h+var_88]\nsetz dil\ncmp cl, 28h ; '('\nsetnz sil\ntest dil, sil\njnz short loc_12E7\ncmp dl, 7Dh ; '}'\nsetz al\ncmp cl, 7Bh ; '{'\nsetnz sil\nand al, sil\njnz short loc_1300\ncmp dl, 5Dh ; ']'\njnz short loc_12D6\ncmp cl, 5Bh ; '['\njnz short loc_12E7\nloc_12D6:\nmov r12d, r8d\njmp short loc_126A\nloc_12E0:\ncmp r12d, 0FFFFFFFFh\nsetz al\nloc_12E7:\nmov rdx, [rsp+88h+var_20]\nsub rdx, fs:28h\njnz short loc_1304\nadd rsp, 70h\npop rbx\npop rbp\npop r12\nretn\nloc_1300:\nxor eax, eax\njmp short loc_12E7\nloc_1304:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "bool __fastcall sub_1230(char *s)\n{\n int v1; // r12d\n size_t v2; // rbx\n char v3; // dl\n bool result; // al\n char v5; // cl\n _BYTE v6[104]; // [rsp+0h] [rbp-88h]\n unsigned __int64 v7; // [rsp+68h] [rbp-20h]\n\n v1 = -1;\n v2 = 0LL;\n v7 = __readfsqword(0x28u);\n while ( 1 )\n {\n if ( v2 >= strlen(s) )\n return v1 == -1;\n v3 = s[v2];\n result = v3 == 40 || (v3 & 0xDF) == 91;\n if ( result )\n {\n v6[++v1] = v3;\n goto LABEL_3;\n }\n if ( v1 == -1 )\n return result;\n v5 = v6[v1];\n if ( v5 != 40 && v3 == 41 )\n return result;\n result = v5 != 123 && v3 == 125;\n if ( result )\n return 0;\n if ( v3 == 93 && v5 != 91 )\n return result;\n --v1;\nLABEL_3:\n ++v2;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_1230(char *s) {\n int v1;\n unsigned int v2;\n char v3;\n bool result;\n char v5;\n uint8_t v6[104];\n unsigned long long v7;\n v1 = -1;\n v2 = 0LL;\n v7 = __readfsqword(40u);\n while (1) {\n if (v2 >= strlen(s)) return v1 == -1;\n v3 = s[v2];\n result = v3 == 40 || (v3 & 223) == 91;\n if (result) {\n v6[++v1] = v3;\n goto LABEL_3;\n }\n if (v1 == -1) return result;\n v5 = v6[v1];\n if (v5 != 40 && v3 == 41) return result;\n result = v5 != 123 && v3 == 125;\n if (result) return 0;\n if (v3 == 93 && v5 != 91) return result;\n --v1;\n LABEL_3:\n ++v2;\n }\n}", + "ida_pseudo_norm": "bool func0(char *s) {\n int v1;\n unsigned int v2;\n char v3;\n bool result;\n char v5;\n uint8_t v6[104];\n unsigned long long v7;\n v1 = -1;\n v2 = 0LL;\n v7 = __readfsqword(40u);\n while (1) {\n if (v2 >= strlen(s)) return v1 == -1;\n v3 = s[v2];\n result = v3 == 40 || (v3 & 223) == 91;\n if (result) {\n v6[++v1] = v3;\n goto LABEL_3;\n }\n if (v1 == -1) return result;\n v5 = v6[v1];\n if (v5 != 40 && v3 == 41) return result;\n result = v5 != 123 && v3 == 125;\n if (result) return 0;\n if (v3 == 93 && v5 != 91) return result;\n --v1;\n LABEL_3:\n ++v2;\n }\n}" + }, + { + "index": 175, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(char* str1) {\n char stack[100];\n int top = -1;\n for (int i = 0; i < strlen(str1); i++) {\n char parenthese = str1[i];\n if (parenthese == '(' || parenthese == '{' || parenthese == '[') {\n stack[++top] = parenthese;\n } else if (top == -1) {\n return false;\n } else {\n char popped = stack[top--];\n if ((parenthese == ')' && popped != '(') ||\n (parenthese == '}' && popped != '{') ||\n (parenthese == ']' && popped != '[')) {\n return false;\n }\n }\n }\n return top == -1;\n}", + "test": "int main() {\n\n assert(func0(\"(){}[]\") == true);\n\n assert(func0(\"()[{)}\") == false);\n\n assert(func0(\"()\") == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\nsub $0x70,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x68(%rsp)\nxor %eax,%eax\ncallq 1070 \nxor %ecx,%ecx\nmov $0xffffffff,%esi\nmov %rax,%rdi\njmp 126e \nnopl (%rax)\nadd $0x1,%esi\nmovslq %esi,%r8\nmov %dl,(%rsp,%r8,1)\nadd $0x1,%rcx\ncmp %rdi,%rcx\njae 1300 \nmovzbl (%rbx,%rcx,1),%edx\nmov %edx,%r8d\nand $0xffffffdf,%r8d\ncmp $0x5b,%r8b\nsete %al\ncmp $0x28,%dl\nsete %r8b\nor %r8b,%al\njne 1260 \ncmp $0xffffffff,%esi\nje 12e0 \nlea -0x1(%rsi),%r10d\nmovslq %esi,%rsi\ncmp $0x29,%dl\nmovzbl (%rsp,%rsi,1),%esi\nsete %r9b\ncmp $0x28,%sil\nsetne %r8b\ntest %r8b,%r9b\njne 12e0 \ncmp $0x7d,%dl\nsete %al\ncmp $0x7b,%sil\nsetne %r8b\nand %r8b,%al\njne 12dc \ncmp $0x5d,%dl\njne 12d7 \ncmp $0x5b,%sil\njne 12e0 \nmov %r10d,%esi\njmp 126a \nxor %eax,%eax\nxchg %ax,%ax\nmov 0x68(%rsp),%rbx\nxor %fs:0x28,%rbx\njne 1308 \nadd $0x70,%rsp\npop %rbx\nretq\nnopw %cs:0x0(%rax,%rax,1)\ncmp $0xffffffff,%esi\nsete %al\njmp 12e0 \ncallq 1080 <__stack_chk_fail@plt>\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r12\nmov r12d, 0FFFFFFFFh\npush rbp\nmov rbp, rdi\npush rbx\nxor ebx, ebx\nsub rsp, 70h\nmov rax, fs:28h\nmov [rsp+88h+var_20], rax\nxor eax, eax\njmp short loc_126E\nloc_1260:\nadd r12d, 1\nmovsxd rax, r12d\nmov [rsp+rax+88h+var_88], dl\nloc_126A:\nadd rbx, 1\nloc_126E:\nmov rdi, rbp; s\ncall _strlen\ncmp rbx, rax\njnb short loc_12E0\nmovzx edx, byte ptr [rbp+rbx+0]\nmov eax, edx\nand eax, 0FFFFFFDFh\ncmp al, 5Bh ; '['\nsetz al\ncmp dl, 28h ; '('\nsetz cl\nor al, cl\njnz short loc_1260\ncmp r12d, 0FFFFFFFFh\njz short loc_12E7\nlea r8d, [r12-1]\nmovsxd r12, r12d\ncmp dl, 29h ; ')'\nmovzx ecx, [rsp+r12+88h+var_88]\nsetz dil\ncmp cl, 28h ; '('\nsetnz sil\ntest dil, sil\njnz short loc_12E7\ncmp dl, 7Dh ; '}'\nsetz al\ncmp cl, 7Bh ; '{'\nsetnz sil\nand al, sil\njnz short loc_1300\ncmp dl, 5Dh ; ']'\njnz short loc_12D6\ncmp cl, 5Bh ; '['\njnz short loc_12E7\nloc_12D6:\nmov r12d, r8d\njmp short loc_126A\nloc_12E0:\ncmp r12d, 0FFFFFFFFh\nsetz al\nloc_12E7:\nmov rdx, [rsp+88h+var_20]\nsub rdx, fs:28h\njnz short loc_1304\nadd rsp, 70h\npop rbx\npop rbp\npop r12\nretn\nloc_1300:\nxor eax, eax\njmp short loc_12E7\nloc_1304:\ncall ___stack_chk_fail", + "ida_pseudo": "bool __fastcall func0(char *s)\n{\n int v1; // r12d\n size_t v2; // rbx\n char v3; // dl\n bool result; // al\n char v5; // cl\n _BYTE v6[104]; // [rsp+0h] [rbp-88h]\n unsigned __int64 v7; // [rsp+68h] [rbp-20h]\n\n v1 = -1;\n v2 = 0LL;\n v7 = __readfsqword(0x28u);\n while ( 1 )\n {\n if ( v2 >= strlen(s) )\n return v1 == -1;\n v3 = s[v2];\n result = v3 == 40 || (v3 & 0xDF) == 91;\n if ( result )\n {\n v6[++v1] = v3;\n goto LABEL_3;\n }\n if ( v1 == -1 )\n return result;\n v5 = v6[v1];\n if ( v5 != 40 && v3 == 41 )\n return result;\n result = v5 != 123 && v3 == 125;\n if ( result )\n return 0;\n if ( v3 == 93 && v5 != 91 )\n return result;\n --v1;\nLABEL_3:\n ++v2;\n }\n}", + "ida_strip_asm": "sub_1230:\nendbr64\npush r12\nmov r12d, 0FFFFFFFFh\npush rbp\nmov rbp, rdi\npush rbx\nxor ebx, ebx\nsub rsp, 70h\nmov rax, fs:28h\nmov [rsp+88h+var_20], rax\nxor eax, eax\njmp short loc_126E\nloc_1260:\nadd r12d, 1\nmovsxd rax, r12d\nmov [rsp+rax+88h+var_88], dl\nloc_126A:\nadd rbx, 1\nloc_126E:\nmov rdi, rbp; s\ncall _strlen\ncmp rbx, rax\njnb short loc_12E0\nmovzx edx, byte ptr [rbp+rbx+0]\nmov eax, edx\nand eax, 0FFFFFFDFh\ncmp al, 5Bh ; '['\nsetz al\ncmp dl, 28h ; '('\nsetz cl\nor al, cl\njnz short loc_1260\ncmp r12d, 0FFFFFFFFh\njz short loc_12E7\nlea r8d, [r12-1]\nmovsxd r12, r12d\ncmp dl, 29h ; ')'\nmovzx ecx, [rsp+r12+88h+var_88]\nsetz dil\ncmp cl, 28h ; '('\nsetnz sil\ntest dil, sil\njnz short loc_12E7\ncmp dl, 7Dh ; '}'\nsetz al\ncmp cl, 7Bh ; '{'\nsetnz sil\nand al, sil\njnz short loc_1300\ncmp dl, 5Dh ; ']'\njnz short loc_12D6\ncmp cl, 5Bh ; '['\njnz short loc_12E7\nloc_12D6:\nmov r12d, r8d\njmp short loc_126A\nloc_12E0:\ncmp r12d, 0FFFFFFFFh\nsetz al\nloc_12E7:\nmov rdx, [rsp+88h+var_20]\nsub rdx, fs:28h\njnz short loc_1304\nadd rsp, 70h\npop rbx\npop rbp\npop r12\nretn\nloc_1300:\nxor eax, eax\njmp short loc_12E7\nloc_1304:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "bool __fastcall sub_1230(char *s)\n{\n int v1; // r12d\n size_t v2; // rbx\n char v3; // dl\n bool result; // al\n char v5; // cl\n _BYTE v6[104]; // [rsp+0h] [rbp-88h]\n unsigned __int64 v7; // [rsp+68h] [rbp-20h]\n\n v1 = -1;\n v2 = 0LL;\n v7 = __readfsqword(0x28u);\n while ( 1 )\n {\n if ( v2 >= strlen(s) )\n return v1 == -1;\n v3 = s[v2];\n result = v3 == 40 || (v3 & 0xDF) == 91;\n if ( result )\n {\n v6[++v1] = v3;\n goto LABEL_3;\n }\n if ( v1 == -1 )\n return result;\n v5 = v6[v1];\n if ( v5 != 40 && v3 == 41 )\n return result;\n result = v5 != 123 && v3 == 125;\n if ( result )\n return 0;\n if ( v3 == 93 && v5 != 91 )\n return result;\n --v1;\nLABEL_3:\n ++v2;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_1230(char *s) {\n int v1;\n unsigned int v2;\n char v3;\n bool result;\n char v5;\n uint8_t v6[104];\n unsigned long long v7;\n v1 = -1;\n v2 = 0LL;\n v7 = __readfsqword(40u);\n while (1) {\n if (v2 >= strlen(s)) return v1 == -1;\n v3 = s[v2];\n result = v3 == 40 || (v3 & 223) == 91;\n if (result) {\n v6[++v1] = v3;\n goto LABEL_3;\n }\n if (v1 == -1) return result;\n v5 = v6[v1];\n if (v5 != 40 && v3 == 41) return result;\n result = v5 != 123 && v3 == 125;\n if (result) return 0;\n if (v3 == 93 && v5 != 91) return result;\n --v1;\n LABEL_3:\n ++v2;\n }\n}", + "ida_pseudo_norm": "bool func0(char *s) {\n int v1;\n unsigned int v2;\n char v3;\n bool result;\n char v5;\n uint8_t v6[104];\n unsigned long long v7;\n v1 = -1;\n v2 = 0LL;\n v7 = __readfsqword(40u);\n while (1) {\n if (v2 >= strlen(s)) return v1 == -1;\n v3 = s[v2];\n result = v3 == 40 || (v3 & 223) == 91;\n if (result) {\n v6[++v1] = v3;\n goto LABEL_3;\n }\n if (v1 == -1) return result;\n v5 = v6[v1];\n if (v5 != 40 && v3 == 41) return result;\n result = v5 != 123 && v3 == 125;\n if (result) return 0;\n if (v3 == 93 && v5 != 91) return result;\n --v1;\n LABEL_3:\n ++v2;\n }\n}" + }, + { + "index": 176, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int a, int b, int c) {\n int perimeter = a + b + c;\n return perimeter;\n}", + "test": "int main() {\n\n assert(func0(10, 20, 30) == 60);\n\n assert(func0(3, 4, 5) == 12);\n\n assert(func0(25, 35, 45) == 105);\n\n \n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov %edx,-0x1c(%rbp)\nmov -0x14(%rbp),%edx\nmov -0x18(%rbp),%eax\nadd %eax,%edx\nmov -0x1c(%rbp),%eax\nadd %edx,%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov edx, [rbp+var_14]\nmov eax, [rbp+var_18]\nadd edx, eax\nmov eax, [rbp+var_1C]\nadd eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, int a3)\n{\n return (unsigned int)(a2 + a1 + a3);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov edx, [rbp+var_14]\nmov eax, [rbp+var_18]\nadd edx, eax\nmov eax, [rbp+var_1C]\nadd eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2, int a3)\n{\n return (unsigned int)(a2 + a1 + a3);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2, int a3) {\n return (unsigned int)(a2 + a1 + a3);\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, int a3) { return (unsigned int)(a2 + a1 + a3); }" + }, + { + "index": 177, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int* func0(int L, int R) {\n static int result[2];\n if (2 * L <= R) {\n result[0] = L;\n result[1] = 2 * L;\n return result;\n } else {\n return NULL;\n }\n}", + "test": "int main() {\n\n int* res;\n\n res = func0(3, 8);\n\n assert(res[0] == 3 && res[1] == 6);\n\n\n\n res = func0(2, 6);\n\n assert(res[0] == 2 && res[1] == 4);\n\n\n\n res = func0(1, 3);\n\n assert(res[0] == 1 && res[1] == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov %esi,-0x8(%rbp)\nmov -0x4(%rbp),%eax\nadd %eax,%eax\ncmp %eax,-0x8(%rbp)\njl 117e \nmov -0x4(%rbp),%eax\nmov %eax,0x2eae(%rip)\nmov -0x4(%rbp),%eax\nadd %eax,%eax\nmov %eax,0x2ea7(%rip)\nlea 0x2e9c(%rip),%rax\njmp 1183 \nmov $0x0,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov eax, [rbp+var_4]\nadd eax, eax\ncmp [rbp+var_8], eax\njl short loc_117E\nmov eax, [rbp+var_4]\nmov cs:result_1, eax\nmov eax, [rbp+var_4]\nadd eax, eax\nmov cs:dword_401C, eax\nlea rax, result_1\njmp short loc_1183\nloc_117E:\nmov eax, 0\nloc_1183:\npop rbp\nretn", + "ida_pseudo": "int *__fastcall func0(int a1, int a2)\n{\n if ( a2 < 2 * a1 )\n return 0LL;\n result_1 = a1;\n dword_401C = 2 * a1;\n return &result_1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov eax, [rbp+var_4]\nadd eax, eax\ncmp [rbp+var_8], eax\njl short loc_117E\nmov eax, [rbp+var_4]\nmov cs:dword_4018, eax\nmov eax, [rbp+var_4]\nadd eax, eax\nmov cs:dword_401C, eax\nlea rax, dword_4018\njmp short loc_1183\nloc_117E:\nmov eax, 0\nloc_1183:\npop rbp\nretn", + "ida_strip_pseudo": "int *__fastcall sub_1149(int a1, int a2)\n{\n if ( a2 < 2 * a1 )\n return 0LL;\n dword_4018 = a1;\n dword_401C = 2 * a1;\n return &dword_4018;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "int* sub_1149(int a1, int a2) {\n if (a2 < 2 * a1) return 0LL;\n dword_4018 = a1;\n dword_401C = 2 * a1;\n return &dword_4018;\n}", + "ida_pseudo_norm": "int* func0(int a1, int a2) {\n if (a2 < 2 * a1) return 0LL;\n result_1 = a1;\n dword_401C = 2 * a1;\n return &result_1;\n}" + }, + { + "index": 178, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* patterns[], int pattern_n, char* text) {\n regex_t regex;\n int reti;\n for (int i = 0; i < pattern_n; i++) {\n reti = regcomp(®ex, patterns[i], 0);\n if (reti) {\n fprintf(stderr, \"Could not compile regex\\n\");\n return \"Not Matched!\";\n }\n reti = regexec(®ex, text, 0, NULL, 0);\n if (!reti) {\n regfree(®ex);\n return \"Matched!\";\n }\n regfree(®ex);\n }\n return \"Not Matched!\";\n}", + "test": "int main() {\n\n char* patterns1[1] = {\"language\"};\n\n assert(func0(patterns1, 1, \"python language\") == \"Matched!\");\n\n\n\n char* patterns2[1] = {\"program\"};\n\n assert(func0(patterns2, 1, \"python language\") == \"Not Matched!\");\n\n\n\n char* patterns3[1] = {\"python\"};\n\n assert(func0(patterns3, 1, \"programming language\") == \"Not Matched!\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nadd $0xffffffffffffff80,%rsp\nmov %rdi,-0x68(%rbp)\nmov %esi,-0x6c(%rbp)\nmov %rdx,-0x78(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovl $0x0,-0x58(%rbp)\njmpq 12c6 \nmov -0x58(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x68(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rcx\nlea -0x50(%rbp),%rax\nmov $0x0,%edx\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 10d0 \nmov %eax,-0x54(%rbp)\ncmpl $0x0,-0x54(%rbp)\nje 1278 \nmov 0x2dca(%rip),%rax\nmov %rax,%rcx\nmov $0x18,%edx\nmov $0x1,%esi\nlea 0xd9e(%rip),%rdi\ncallq 10f0 \nlea 0xdab(%rip),%rax\njmp 12d9 \nmov -0x78(%rbp),%rsi\nlea -0x50(%rbp),%rax\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rax,%rdi\ncallq 10e0 \nmov %eax,-0x54(%rbp)\ncmpl $0x0,-0x54(%rbp)\njne 12b6 \nlea -0x50(%rbp),%rax\nmov %rax,%rdi\ncallq 10a0 \nlea 0xd7a(%rip),%rax\njmp 12d9 \nlea -0x50(%rbp),%rax\nmov %rax,%rdi\ncallq 10a0 \naddl $0x1,-0x58(%rbp)\nmov -0x58(%rbp),%eax\ncmp -0x6c(%rbp),%eax\njl 121b \nlea 0xd48(%rip),%rax\nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 12ed \ncallq 10b0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nadd rsp, 0FFFFFFFFFFFFFF80h\nmov [rbp+var_68], rdi\nmov [rbp+var_6C], esi\nmov [rbp+string], rdx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_58], 0\njmp loc_12C9\nloc_121B:\nmov eax, [rbp+var_58]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_68]\nadd rax, rdx\nmov rcx, [rax]\nlea rax, [rbp+preg]\nmov edx, 0; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+var_54], eax\ncmp [rbp+var_54], 0\njz short loc_127B\nmov rax, cs:__bss_start\nmov rcx, rax; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rax, aCouldNotCompil; \"Could not compile regex\\n\"\nmov rdi, rax; ptr\ncall _fwrite\nlea rax, aNotMatched; \"Not Matched!\"\njmp short loc_12DC\nloc_127B:\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_54], eax\ncmp [rbp+var_54], 0\njnz short loc_12B9\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nlea rax, aMatched; \"Matched!\"\njmp short loc_12DC\nloc_12B9:\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nadd [rbp+var_58], 1\nloc_12C9:\nmov eax, [rbp+var_58]\ncmp eax, [rbp+var_6C]\njl loc_121B\nlea rax, aNotMatched; \"Not Matched!\"\nloc_12DC:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12F0\ncall ___stack_chk_fail\nlocret_12F0:\nleave\nretn", + "ida_pseudo": "const char *__fastcall func0(__int64 a1, int a2, const char *a3)\n{\n int i; // [rsp+28h] [rbp-58h]\n regex_t preg; // [rsp+30h] [rbp-50h] BYREF\n unsigned __int64 v7; // [rsp+78h] [rbp-8h]\n\n v7 = __readfsqword(0x28u);\n for ( i = 0; i < a2; ++i )\n {\n if ( regcomp(&preg, *(const char **)(8LL * i + a1), 0) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n return \"Not Matched!\";\n }\n if ( !regexec(&preg, a3, 0LL, 0LL, 0) )\n {\n regfree(&preg);\n return \"Matched!\";\n }\n regfree(&preg);\n }\n return \"Not Matched!\";\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\nadd rsp, 0FFFFFFFFFFFFFF80h\nmov [rbp+var_68], rdi\nmov [rbp+var_6C], esi\nmov [rbp+string], rdx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_58], 0\njmp loc_12C9\nloc_121B:\nmov eax, [rbp+var_58]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_68]\nadd rax, rdx\nmov rcx, [rax]\nlea rax, [rbp+preg]\nmov edx, 0; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+var_54], eax\ncmp [rbp+var_54], 0\njz short loc_127B\nmov rax, cs:stderr\nmov rcx, rax; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rax, aCouldNotCompil; \"Could not compile regex\\n\"\nmov rdi, rax; ptr\ncall _fwrite\nlea rax, aNotMatched; \"Not Matched!\"\njmp short loc_12DC\nloc_127B:\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_54], eax\ncmp [rbp+var_54], 0\njnz short loc_12B9\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nlea rax, aMatched; \"Matched!\"\njmp short loc_12DC\nloc_12B9:\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nadd [rbp+var_58], 1\nloc_12C9:\nmov eax, [rbp+var_58]\ncmp eax, [rbp+var_6C]\njl loc_121B\nlea rax, aNotMatched; \"Not Matched!\"\nloc_12DC:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12F0\ncall ___stack_chk_fail\nlocret_12F0:\nleave\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_11E9(__int64 a1, int a2, const char *a3)\n{\n int i; // [rsp+28h] [rbp-58h]\n regex_t preg; // [rsp+30h] [rbp-50h] BYREF\n unsigned __int64 v7; // [rsp+78h] [rbp-8h]\n\n v7 = __readfsqword(0x28u);\n for ( i = 0; i < a2; ++i )\n {\n if ( regcomp(&preg, *(const char **)(8LL * i + a1), 0) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n return \"Not Matched!\";\n }\n if ( !regexec(&preg, a3, 0LL, 0LL, 0) )\n {\n regfree(&preg);\n return \"Matched!\";\n }\n regfree(&preg);\n }\n return \"Not Matched!\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_11E9(long long a1, int a2, const char *a3) {\n int i;\n regex_t preg;\n unsigned long long v7;\n v7 = __readfsqword(40u);\n for (i = 0; i < a2; ++i) {\n if (regcomp(&preg, *(const char **)(8LL * i + a1), 0)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n return \"Not Matched!\";\n }\n if (!regexec(&preg, a3, 0LL, 0LL, 0)) {\n regfree(&preg);\n return \"Matched!\";\n }\n regfree(&preg);\n }\n return \"Not Matched!\";\n}", + "ida_pseudo_norm": "const char *func0(long long a1, int a2, const char *a3) {\n int i;\n regex_t preg;\n unsigned long long v7;\n v7 = __readfsqword(40u);\n for (i = 0; i < a2; ++i) {\n if (regcomp(&preg, *(const char **)(8LL * i + a1), 0)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n return \"Not Matched!\";\n }\n if (!regexec(&preg, a3, 0LL, 0LL, 0)) {\n regfree(&preg);\n return \"Matched!\";\n }\n regfree(&preg);\n }\n return \"Not Matched!\";\n}" + }, + { + "index": 178, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* patterns[], int pattern_n, char* text) {\n regex_t regex;\n int reti;\n for (int i = 0; i < pattern_n; i++) {\n reti = regcomp(®ex, patterns[i], 0);\n if (reti) {\n fprintf(stderr, \"Could not compile regex\\n\");\n return \"Not Matched!\";\n }\n reti = regexec(®ex, text, 0, NULL, 0);\n if (!reti) {\n regfree(®ex);\n return \"Matched!\";\n }\n regfree(®ex);\n }\n return \"Not Matched!\";\n}", + "test": "int main() {\n\n char* patterns1[1] = {\"language\"};\n\n assert(func0(patterns1, 1, \"python language\") == \"Matched!\");\n\n\n\n char* patterns2[1] = {\"program\"};\n\n assert(func0(patterns2, 1, \"python language\") == \"Not Matched!\");\n\n\n\n char* patterns3[1] = {\"python\"};\n\n assert(func0(patterns3, 1, \"programming language\") == \"Not Matched!\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x58,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nlea 0xdf6(%rip),%rax\ntest %esi,%esi\njle 1298 \nmov %rdx,%r12\nmov %rdi,%rbx\nlea -0x1(%rsi),%eax\nlea 0x8(%rdi,%rax,8),%r13\nmov %rsp,%rbp\nmov $0x0,%edx\nmov (%rbx),%rsi\nmov %rbp,%rdi\ncallq 10d0 \ntest %eax,%eax\njne 1274 \nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %r12,%rsi\nmov %rbp,%rdi\ncallq 10e0 \ntest %eax,%eax\nje 12b3 \nmov %rbp,%rdi\ncallq 10a0 \nadd $0x8,%rbx\ncmp %r13,%rbx\njne 1227 \nlea 0xd92(%rip),%rax\njmp 1298 \nmov 0x2da5(%rip),%rcx\nmov $0x18,%edx\nmov $0x1,%esi\nlea 0xd85(%rip),%rdi\ncallq 10f0 \nlea 0xd6c(%rip),%rax\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 12c4 \nadd $0x58,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nmov %rsp,%rdi\ncallq 10a0 \nlea 0xd46(%rip),%rax\njmp 1298 \ncallq 10b0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+78h+var_30], rax\nxor eax, eax\nlea rax, aNotMatched; \"Not Matched!\"\ntest esi, esi\njle loc_1297\nmov r12, rdx\nmov rbx, rdi\nmovsxd rsi, esi\nlea r13, [rdi+rsi*8]\nmov rbp, rsp\nloc_1226:\nmov rsi, [rbx]; pattern\nmov edx, 0; cflags\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njnz short loc_1273\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, r12; string\nmov rdi, rbp; preg\ncall _regexec\ntest eax, eax\njz short loc_12B2\nmov rdi, rbp; preg\ncall _regfree\nadd rbx, 8\ncmp rbx, r13\njnz short loc_1226\nlea rax, aNotMatched; \"Not Matched!\"\njmp short loc_1297\nloc_1273:\nmov rcx, cs:__bss_start; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nlea rax, aNotMatched; \"Not Matched!\"\nloc_1297:\nmov rdx, [rsp+78h+var_30]\nsub rdx, fs:28h\njnz short loc_12C3\nadd rsp, 58h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_12B2:\nmov rdi, rsp; preg\ncall _regfree\nlea rax, aNotMatched+4; \"Matched!\"\njmp short loc_1297\nloc_12C3:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(const char **a1, int a2, const char *a3)\n{\n char *result; // rax\n const char **v5; // rbx\n regex_t v6; // [rsp+0h] [rbp-78h] BYREF\n unsigned __int64 v7; // [rsp+48h] [rbp-30h]\n\n v7 = __readfsqword(0x28u);\n result = \"Not Matched!\";\n if ( a2 > 0 )\n {\n v5 = a1;\n while ( 1 )\n {\n if ( regcomp(&v6, *v5, 0) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n return \"Not Matched!\";\n }\n if ( !regexec(&v6, a3, 0LL, 0LL, 0) )\n break;\n regfree(&v6);\n if ( ++v5 == &a1[a2] )\n return \"Not Matched!\";\n }\n regfree(&v6);\n return \"Matched!\";\n }\n return result;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+78h+var_30], rax\nxor eax, eax\nlea rax, aNotMatched; \"Not Matched!\"\ntest esi, esi\njle loc_1297\nmov r12, rdx\nmov rbx, rdi\nmovsxd rsi, esi\nlea r13, [rdi+rsi*8]\nmov rbp, rsp\nloc_1226:\nmov rsi, [rbx]; pattern\nmov edx, 0; cflags\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njnz short loc_1273\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, r12; string\nmov rdi, rbp; preg\ncall _regexec\ntest eax, eax\njz short loc_12B2\nmov rdi, rbp; preg\ncall _regfree\nadd rbx, 8\ncmp rbx, r13\njnz short loc_1226\nlea rax, aNotMatched; \"Not Matched!\"\njmp short loc_1297\nloc_1273:\nmov rcx, cs:stderr; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nlea rax, aNotMatched; \"Not Matched!\"\nloc_1297:\nmov rdx, [rsp+78h+var_30]\nsub rdx, fs:28h\njnz short loc_12C3\nadd rsp, 58h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_12B2:\nmov rdi, rsp; preg\ncall _regfree\nlea rax, aNotMatched+4; \"Matched!\"\njmp short loc_1297\nloc_12C3:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_11E9(const char **a1, int a2, const char *a3)\n{\n char *result; // rax\n const char **v5; // rbx\n regex_t v6; // [rsp+0h] [rbp-78h] BYREF\n unsigned __int64 v7; // [rsp+48h] [rbp-30h]\n\n v7 = __readfsqword(0x28u);\n result = \"Not Matched!\";\n if ( a2 > 0 )\n {\n v5 = a1;\n while ( 1 )\n {\n if ( regcomp(&v6, *v5, 0) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n return \"Not Matched!\";\n }\n if ( !regexec(&v6, a3, 0LL, 0LL, 0) )\n break;\n regfree(&v6);\n if ( ++v5 == &a1[a2] )\n return \"Not Matched!\";\n }\n regfree(&v6);\n return \"Matched!\";\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11E9(const char **a1, int a2, const char *a3) {\n char *result;\n const char **v5;\n regex_t v6;\n unsigned long long v7;\n v7 = __readfsqword(40u);\n result = \"Not Matched!\";\n if (a2 > 0) {\n v5 = a1;\n while (1) {\n if (regcomp(&v6, *v5, 0)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n return \"Not Matched!\";\n }\n if (!regexec(&v6, a3, 0LL, 0LL, 0)) break;\n regfree(&v6);\n if (++v5 == &a1[a2]) return \"Not Matched!\";\n }\n regfree(&v6);\n return \"Matched!\";\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(const char **a1, int a2, const char *a3) {\n char *result;\n const char **v5;\n regex_t v6;\n unsigned long long v7;\n v7 = __readfsqword(40u);\n result = \"Not Matched!\";\n if (a2 > 0) {\n v5 = a1;\n while (1) {\n if (regcomp(&v6, *v5, 0)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n return \"Not Matched!\";\n }\n if (!regexec(&v6, a3, 0LL, 0LL, 0)) break;\n regfree(&v6);\n if (++v5 == &a1[a2]) return \"Not Matched!\";\n }\n regfree(&v6);\n return \"Matched!\";\n }\n return result;\n}" + }, + { + "index": 178, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* patterns[], int pattern_n, char* text) {\n regex_t regex;\n int reti;\n for (int i = 0; i < pattern_n; i++) {\n reti = regcomp(®ex, patterns[i], 0);\n if (reti) {\n fprintf(stderr, \"Could not compile regex\\n\");\n return \"Not Matched!\";\n }\n reti = regexec(®ex, text, 0, NULL, 0);\n if (!reti) {\n regfree(®ex);\n return \"Matched!\";\n }\n regfree(®ex);\n }\n return \"Not Matched!\";\n}", + "test": "int main() {\n\n char* patterns1[1] = {\"language\"};\n\n assert(func0(patterns1, 1, \"python language\") == \"Matched!\");\n\n\n\n char* patterns2[1] = {\"program\"};\n\n assert(func0(patterns2, 1, \"python language\") == \"Not Matched!\");\n\n\n\n char* patterns3[1] = {\"python\"};\n\n assert(func0(patterns3, 1, \"programming language\") == \"Not Matched!\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x58,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\ntest %esi,%esi\njle 13d0 \nlea -0x1(%rsi),%eax\nmov %rdx,%r12\nmov %rdi,%rbx\nmov %rsp,%rbp\nlea 0x8(%rdi,%rax,8),%r13\njmp 1377 \nnopl 0x0(%rax)\nmov %rbp,%rdi\nxor %r8d,%r8d\nxor %ecx,%ecx\nxor %edx,%edx\nmov %r12,%rsi\ncallq 10e0 \nmov %rbp,%rdi\ntest %eax,%eax\nje 13e0 \ncallq 10a0 \nadd $0x8,%rbx\ncmp %r13,%rbx\nje 13d0 \nmov (%rbx),%rsi\nxor %edx,%edx\nmov %rbp,%rdi\ncallq 10d0 \ntest %eax,%eax\nje 1350 \nmov 0x2c91(%rip),%rcx\nmov $0x18,%edx\nmov $0x1,%esi\nlea 0xc71(%rip),%rdi\ncallq 10f0 \nlea 0xc58(%rip),%rax\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 13ee \nadd $0x58,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopw 0x0(%rax,%rax,1)\nlea 0xc2d(%rip),%rax\njmp 13ac \nnopl 0x0(%rax)\ncallq 10a0 \nlea 0xc1c(%rip),%rax\njmp 13ac \ncallq 10b0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+78h+var_30], rax\nxor eax, eax\ntest esi, esi\njle short loc_139D\nmovsxd rsi, esi\nmov r12, rdx\nmov rbx, rdi\nmov rbp, rsp\nlea r13, [rdi+rsi*8]\njmp short loc_136F\nloc_1348:\nmov rdi, rbp; preg\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, r12; string\ncall _regexec\nmov rdi, rbp; preg\ntest eax, eax\njz short loc_13C0\ncall _regfree\nadd rbx, 8\ncmp rbx, r13\njz short loc_139D\nloc_136F:\nmov rsi, [rbx]; pattern\nxor edx, edx; cflags\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njz short loc_1348\nmov rcx, cs:__bss_start; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nloc_139D:\nlea rax, aNotMatched; \"Not Matched!\"\nloc_13A4:\nmov rdx, [rsp+78h+var_30]\nsub rdx, fs:28h\njnz short loc_13CE\nadd rsp, 58h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_13C0:\ncall _regfree\nlea rax, aNotMatched+4; \"Matched!\"\njmp short loc_13A4\nloc_13CE:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(const char **a1, int a2, const char *a3)\n{\n const char **v4; // rbx\n regex_t v6; // [rsp+0h] [rbp-78h] BYREF\n unsigned __int64 v7; // [rsp+48h] [rbp-30h]\n\n v7 = __readfsqword(0x28u);\n if ( a2 <= 0 )\n return \"Not Matched!\";\n v4 = a1;\n while ( 1 )\n {\n if ( regcomp(&v6, *v4, 0) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n return \"Not Matched!\";\n }\n if ( !regexec(&v6, a3, 0LL, 0LL, 0) )\n break;\n regfree(&v6);\n if ( ++v4 == &a1[a2] )\n return \"Not Matched!\";\n }\n regfree(&v6);\n return \"Matched!\";\n}", + "ida_strip_asm": "sub_1310:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+78h+var_30], rax\nxor eax, eax\ntest esi, esi\njle short loc_139D\nmovsxd rsi, esi\nmov r12, rdx\nmov rbx, rdi\nmov rbp, rsp\nlea r13, [rdi+rsi*8]\njmp short loc_136F\nloc_1348:\nmov rdi, rbp; preg\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, r12; string\ncall _regexec\nmov rdi, rbp; preg\ntest eax, eax\njz short loc_13C0\ncall _regfree\nadd rbx, 8\ncmp rbx, r13\njz short loc_139D\nloc_136F:\nmov rsi, [rbx]; pattern\nxor edx, edx; cflags\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njz short loc_1348\nmov rcx, cs:stderr; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nloc_139D:\nlea rax, aNotMatched; \"Not Matched!\"\nloc_13A4:\nmov rdx, [rsp+78h+var_30]\nsub rdx, fs:28h\njnz short loc_13CE\nadd rsp, 58h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_13C0:\ncall _regfree\nlea rax, aNotMatched+4; \"Matched!\"\njmp short loc_13A4\nloc_13CE:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_1310(const char **a1, int a2, const char *a3)\n{\n const char **v4; // rbx\n regex_t v6; // [rsp+0h] [rbp-78h] BYREF\n unsigned __int64 v7; // [rsp+48h] [rbp-30h]\n\n v7 = __readfsqword(0x28u);\n if ( a2 <= 0 )\n return \"Not Matched!\";\n v4 = a1;\n while ( 1 )\n {\n if ( regcomp(&v6, *v4, 0) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n return \"Not Matched!\";\n }\n if ( !regexec(&v6, a3, 0LL, 0LL, 0) )\n break;\n regfree(&v6);\n if ( ++v4 == &a1[a2] )\n return \"Not Matched!\";\n }\n regfree(&v6);\n return \"Matched!\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1310(const char **a1, int a2, const char *a3) {\n const char **v4;\n regex_t v6;\n unsigned long long v7;\n v7 = __readfsqword(40u);\n if (a2 <= 0) return \"Not Matched!\";\n v4 = a1;\n while (1) {\n if (regcomp(&v6, *v4, 0)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n return \"Not Matched!\";\n }\n if (!regexec(&v6, a3, 0LL, 0LL, 0)) break;\n regfree(&v6);\n if (++v4 == &a1[a2]) return \"Not Matched!\";\n }\n regfree(&v6);\n return \"Matched!\";\n}", + "ida_pseudo_norm": "char *func0(const char **a1, int a2, const char *a3) {\n const char **v4;\n regex_t v6;\n unsigned long long v7;\n v7 = __readfsqword(40u);\n if (a2 <= 0) return \"Not Matched!\";\n v4 = a1;\n while (1) {\n if (regcomp(&v6, *v4, 0)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n return \"Not Matched!\";\n }\n if (!regexec(&v6, a3, 0LL, 0LL, 0)) break;\n regfree(&v6);\n if (++v4 == &a1[a2]) return \"Not Matched!\";\n }\n regfree(&v6);\n return \"Matched!\";\n}" + }, + { + "index": 178, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* patterns[], int pattern_n, char* text) {\n regex_t regex;\n int reti;\n for (int i = 0; i < pattern_n; i++) {\n reti = regcomp(®ex, patterns[i], 0);\n if (reti) {\n fprintf(stderr, \"Could not compile regex\\n\");\n return \"Not Matched!\";\n }\n reti = regexec(®ex, text, 0, NULL, 0);\n if (!reti) {\n regfree(®ex);\n return \"Matched!\";\n }\n regfree(®ex);\n }\n return \"Not Matched!\";\n}", + "test": "int main() {\n\n char* patterns1[1] = {\"language\"};\n\n assert(func0(patterns1, 1, \"python language\") == \"Matched!\");\n\n\n\n char* patterns2[1] = {\"program\"};\n\n assert(func0(patterns2, 1, \"python language\") == \"Not Matched!\");\n\n\n\n char* patterns3[1] = {\"python\"};\n\n assert(func0(patterns3, 1, \"programming language\") == \"Not Matched!\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x58,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\ntest %esi,%esi\njle 13d0 \nlea -0x1(%rsi),%eax\nmov %rdx,%r12\nmov %rdi,%rbx\nmov %rsp,%rbp\nlea 0x8(%rdi,%rax,8),%r13\njmp 1377 \nnopl 0x0(%rax)\nmov %rbp,%rdi\nxor %r8d,%r8d\nxor %ecx,%ecx\nxor %edx,%edx\nmov %r12,%rsi\ncallq 10e0 \nmov %rbp,%rdi\ntest %eax,%eax\nje 13e0 \ncallq 10a0 \nadd $0x8,%rbx\ncmp %r13,%rbx\nje 13d0 \nmov (%rbx),%rsi\nxor %edx,%edx\nmov %rbp,%rdi\ncallq 10d0 \ntest %eax,%eax\nje 1350 \nmov 0x2c91(%rip),%rcx\nmov $0x18,%edx\nmov $0x1,%esi\nlea 0xc71(%rip),%rdi\ncallq 10f0 \nlea 0xc58(%rip),%rax\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 13ee \nadd $0x58,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopw 0x0(%rax,%rax,1)\nlea 0xc2d(%rip),%rax\njmp 13ac \nnopl 0x0(%rax)\ncallq 10a0 \nlea 0xc1c(%rip),%rax\njmp 13ac \ncallq 10b0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+78h+var_30], rax\nxor eax, eax\ntest esi, esi\njle short loc_139D\nmovsxd rsi, esi\nmov r12, rdx\nmov rbx, rdi\nmov rbp, rsp\nlea r13, [rdi+rsi*8]\njmp short loc_136F\nloc_1348:\nmov rdi, rbp; preg\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, r12; string\ncall _regexec\nmov rdi, rbp; preg\ntest eax, eax\njz short loc_13C0\ncall _regfree\nadd rbx, 8\ncmp rbx, r13\njz short loc_139D\nloc_136F:\nmov rsi, [rbx]; pattern\nxor edx, edx; cflags\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njz short loc_1348\nmov rcx, cs:__bss_start; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nloc_139D:\nlea rax, aNotMatched; \"Not Matched!\"\nloc_13A4:\nmov rdx, [rsp+78h+var_30]\nsub rdx, fs:28h\njnz short loc_13CE\nadd rsp, 58h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_13C0:\ncall _regfree\nlea rax, aNotMatched+4; \"Matched!\"\njmp short loc_13A4\nloc_13CE:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(const char **a1, int a2, const char *a3)\n{\n const char **v4; // rbx\n regex_t v6; // [rsp+0h] [rbp-78h] BYREF\n unsigned __int64 v7; // [rsp+48h] [rbp-30h]\n\n v7 = __readfsqword(0x28u);\n if ( a2 <= 0 )\n return \"Not Matched!\";\n v4 = a1;\n while ( 1 )\n {\n if ( regcomp(&v6, *v4, 0) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n return \"Not Matched!\";\n }\n if ( !regexec(&v6, a3, 0LL, 0LL, 0) )\n break;\n regfree(&v6);\n if ( ++v4 == &a1[a2] )\n return \"Not Matched!\";\n }\n regfree(&v6);\n return \"Matched!\";\n}", + "ida_strip_asm": "sub_1310:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+78h+var_30], rax\nxor eax, eax\ntest esi, esi\njle short loc_139D\nmovsxd rsi, esi\nmov r12, rdx\nmov rbx, rdi\nmov rbp, rsp\nlea r13, [rdi+rsi*8]\njmp short loc_136F\nloc_1348:\nmov rdi, rbp; preg\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, r12; string\ncall _regexec\nmov rdi, rbp; preg\ntest eax, eax\njz short loc_13C0\ncall _regfree\nadd rbx, 8\ncmp rbx, r13\njz short loc_139D\nloc_136F:\nmov rsi, [rbx]; pattern\nxor edx, edx; cflags\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njz short loc_1348\nmov rcx, cs:stderr; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nloc_139D:\nlea rax, aNotMatched; \"Not Matched!\"\nloc_13A4:\nmov rdx, [rsp+78h+var_30]\nsub rdx, fs:28h\njnz short loc_13CE\nadd rsp, 58h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_13C0:\ncall _regfree\nlea rax, aNotMatched+4; \"Matched!\"\njmp short loc_13A4\nloc_13CE:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_1310(const char **a1, int a2, const char *a3)\n{\n const char **v4; // rbx\n regex_t v6; // [rsp+0h] [rbp-78h] BYREF\n unsigned __int64 v7; // [rsp+48h] [rbp-30h]\n\n v7 = __readfsqword(0x28u);\n if ( a2 <= 0 )\n return \"Not Matched!\";\n v4 = a1;\n while ( 1 )\n {\n if ( regcomp(&v6, *v4, 0) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n return \"Not Matched!\";\n }\n if ( !regexec(&v6, a3, 0LL, 0LL, 0) )\n break;\n regfree(&v6);\n if ( ++v4 == &a1[a2] )\n return \"Not Matched!\";\n }\n regfree(&v6);\n return \"Matched!\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1310(const char **a1, int a2, const char *a3) {\n const char **v4;\n regex_t v6;\n unsigned long long v7;\n v7 = __readfsqword(40u);\n if (a2 <= 0) return \"Not Matched!\";\n v4 = a1;\n while (1) {\n if (regcomp(&v6, *v4, 0)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n return \"Not Matched!\";\n }\n if (!regexec(&v6, a3, 0LL, 0LL, 0)) break;\n regfree(&v6);\n if (++v4 == &a1[a2]) return \"Not Matched!\";\n }\n regfree(&v6);\n return \"Matched!\";\n}", + "ida_pseudo_norm": "char *func0(const char **a1, int a2, const char *a3) {\n const char **v4;\n regex_t v6;\n unsigned long long v7;\n v7 = __readfsqword(40u);\n if (a2 <= 0) return \"Not Matched!\";\n v4 = a1;\n while (1) {\n if (regcomp(&v6, *v4, 0)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n return \"Not Matched!\";\n }\n if (!regexec(&v6, a3, 0LL, 0LL, 0)) break;\n regfree(&v6);\n if (++v4 == &a1[a2]) return \"Not Matched!\";\n }\n regfree(&v6);\n return \"Matched!\";\n}" + }, + { + "index": 179, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int x) {\n int terms[100], temp = x, n = 0;\n while (temp > 0) {\n terms[n++] = temp % 10;\n temp /= 10;\n }\n for (int left = 0, right = n - 1; left < right; left++, right--) {\n int temp = terms[left];\n terms[left] = terms[right];\n terms[right] = temp;\n }\n int next_term = 0, i = n;\n while (next_term < x) {\n next_term = 0;\n for (int j = 1; j <= n; j++) {\n next_term += terms[i - j];\n }\n terms[i++] = next_term;\n }\n return (next_term == x);\n}", + "test": "int main() {\n\n assert(func0(14) == true);\n\n assert(func0(12) == false);\n\n assert(func0(197) == true);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x1d0,%rsp\nmov %edi,-0x1c4(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmov -0x1c4(%rbp),%eax\nmov %eax,-0x1c0(%rbp)\nmovl $0x0,-0x1bc(%rbp)\njmp 120f \nmov -0x1bc(%rbp),%esi\nlea 0x1(%rsi),%eax\nmov %eax,-0x1bc(%rbp)\nmov -0x1c0(%rbp),%ecx\nmovslq %ecx,%rax\nimul $0x66666667,%rax,%rax\nshr $0x20,%rax\nmov %eax,%edx\nsar $0x2,%edx\nmov %ecx,%eax\nsar $0x1f,%eax\nsub %eax,%edx\nmov %edx,%eax\nshl $0x2,%eax\nadd %edx,%eax\nadd %eax,%eax\nsub %eax,%ecx\nmov %ecx,%edx\nmovslq %esi,%rax\nmov %edx,-0x1a0(%rbp,%rax,4)\nmov -0x1c0(%rbp),%eax\nmovslq %eax,%rdx\nimul $0x66666667,%rdx,%rdx\nshr $0x20,%rdx\nsar $0x2,%edx\nsar $0x1f,%eax\nsub %eax,%edx\nmov %edx,%eax\nmov %eax,-0x1c0(%rbp)\ncmpl $0x0,-0x1c0(%rbp)\njg 11a5 \nmovl $0x0,-0x1b8(%rbp)\nmov -0x1bc(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0x1b4(%rbp)\njmp 1289 \nmov -0x1b8(%rbp),%eax\ncltq\nmov -0x1a0(%rbp,%rax,4),%eax\nmov %eax,-0x1a4(%rbp)\nmov -0x1b4(%rbp),%eax\ncltq\nmov -0x1a0(%rbp,%rax,4),%edx\nmov -0x1b8(%rbp),%eax\ncltq\nmov %edx,-0x1a0(%rbp,%rax,4)\nmov -0x1b4(%rbp),%eax\ncltq\nmov -0x1a4(%rbp),%edx\nmov %edx,-0x1a0(%rbp,%rax,4)\naddl $0x1,-0x1b8(%rbp)\nsubl $0x1,-0x1b4(%rbp)\nmov -0x1b8(%rbp),%eax\ncmp -0x1b4(%rbp),%eax\njl 1233 \nmovl $0x0,-0x1b0(%rbp)\nmov -0x1bc(%rbp),%eax\nmov %eax,-0x1ac(%rbp)\njmp 1313 \nmovl $0x0,-0x1b0(%rbp)\nmovl $0x1,-0x1a8(%rbp)\njmp 12e7 \nmov -0x1ac(%rbp),%eax\nsub -0x1a8(%rbp),%eax\ncltq\nmov -0x1a0(%rbp,%rax,4),%eax\nadd %eax,-0x1b0(%rbp)\naddl $0x1,-0x1a8(%rbp)\nmov -0x1a8(%rbp),%eax\ncmp -0x1bc(%rbp),%eax\njle 12c5 \nmov -0x1ac(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x1ac(%rbp)\ncltq\nmov -0x1b0(%rbp),%edx\nmov %edx,-0x1a0(%rbp,%rax,4)\nmov -0x1b0(%rbp),%eax\ncmp -0x1c4(%rbp),%eax\njl 12af \nmov -0x1b0(%rbp),%eax\ncmp -0x1c4(%rbp),%eax\nsete %al\nmov -0x8(%rbp),%rdi\nxor %fs:0x28,%rdi\nje 1344 \ncallq 1060 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 1D0h\nmov [rbp+var_1C4], edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov eax, [rbp+var_1C4]\nmov [rbp+var_1C0], eax\nmov [rbp+var_1BC], 0\njmp short loc_120F\nloc_11A5:\nmov esi, [rbp+var_1BC]\nlea eax, [rsi+1]\nmov [rbp+var_1BC], eax\nmov ecx, [rbp+var_1C0]\nmovsxd rax, ecx\nimul rax, 66666667h\nshr rax, 20h\nmov edx, eax\nsar edx, 2\nmov eax, ecx\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nsub ecx, eax\nmov edx, ecx\nmovsxd rax, esi\nmov [rbp+rax*4+var_1A0], edx\nmov eax, [rbp+var_1C0]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_1C0], eax\nloc_120F:\ncmp [rbp+var_1C0], 0\njg short loc_11A5\nmov [rbp+var_1B8], 0\nmov eax, [rbp+var_1BC]\nsub eax, 1\nmov [rbp+var_1B4], eax\njmp short loc_1289\nloc_1233:\nmov eax, [rbp+var_1B8]\ncdqe\nmov eax, [rbp+rax*4+var_1A0]\nmov [rbp+var_1A4], eax\nmov eax, [rbp+var_1B4]\ncdqe\nmov edx, [rbp+rax*4+var_1A0]\nmov eax, [rbp+var_1B8]\ncdqe\nmov [rbp+rax*4+var_1A0], edx\nmov eax, [rbp+var_1B4]\ncdqe\nmov edx, [rbp+var_1A4]\nmov [rbp+rax*4+var_1A0], edx\nadd [rbp+var_1B8], 1\nsub [rbp+var_1B4], 1\nloc_1289:\nmov eax, [rbp+var_1B8]\ncmp eax, [rbp+var_1B4]\njl short loc_1233\nmov [rbp+var_1B0], 0\nmov eax, [rbp+var_1BC]\nmov [rbp+var_1AC], eax\njmp short loc_1313\nloc_12AF:\nmov [rbp+var_1B0], 0\nmov [rbp+var_1A8], 1\njmp short loc_12E7\nloc_12C5:\nmov eax, [rbp+var_1AC]\nsub eax, [rbp+var_1A8]\ncdqe\nmov eax, [rbp+rax*4+var_1A0]\nadd [rbp+var_1B0], eax\nadd [rbp+var_1A8], 1\nloc_12E7:\nmov eax, [rbp+var_1A8]\ncmp eax, [rbp+var_1BC]\njle short loc_12C5\nmov eax, [rbp+var_1AC]\nlea edx, [rax+1]\nmov [rbp+var_1AC], edx\ncdqe\nmov edx, [rbp+var_1B0]\nmov [rbp+rax*4+var_1A0], edx\nloc_1313:\nmov eax, [rbp+var_1B0]\ncmp eax, [rbp+var_1C4]\njl short loc_12AF\nmov eax, [rbp+var_1B0]\ncmp eax, [rbp+var_1C4]\nsetz al\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1344\ncall ___stack_chk_fail\nlocret_1344:\nleave\nretn", + "ida_pseudo": "bool __fastcall func0(int a1)\n{\n int v1; // esi\n int v2; // eax\n int v4; // [rsp+10h] [rbp-1C0h]\n int v5; // [rsp+14h] [rbp-1BCh]\n int v6; // [rsp+18h] [rbp-1B8h]\n int i; // [rsp+1Ch] [rbp-1B4h]\n int v8; // [rsp+20h] [rbp-1B0h]\n int v9; // [rsp+24h] [rbp-1ACh]\n int j; // [rsp+28h] [rbp-1A8h]\n int v11; // [rsp+2Ch] [rbp-1A4h]\n _DWORD v12[102]; // [rsp+30h] [rbp-1A0h]\n unsigned __int64 v13; // [rsp+1C8h] [rbp-8h]\n\n v13 = __readfsqword(0x28u);\n v4 = a1;\n v5 = 0;\n while ( v4 > 0 )\n {\n v1 = v5++;\n v12[v1] = v4 % 10;\n v4 /= 10;\n }\n v6 = 0;\n for ( i = v5 - 1; v6 < i; --i )\n {\n v11 = v12[v6];\n v12[v6] = v12[i];\n v12[i] = v11;\n ++v6;\n }\n v8 = 0;\n v9 = v5;\n while ( v8 < a1 )\n {\n v8 = 0;\n for ( j = 1; j <= v5; ++j )\n v8 += v12[v9 - j];\n v2 = v9++;\n v12[v2] = v8;\n }\n return v8 == a1;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 1D0h\nmov [rbp+var_1C4], edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov eax, [rbp+var_1C4]\nmov [rbp+var_1C0], eax\nmov [rbp+var_1BC], 0\njmp short loc_120F\nloc_11A5:\nmov esi, [rbp+var_1BC]\nlea eax, [rsi+1]\nmov [rbp+var_1BC], eax\nmov ecx, [rbp+var_1C0]\nmovsxd rax, ecx\nimul rax, 66666667h\nshr rax, 20h\nmov edx, eax\nsar edx, 2\nmov eax, ecx\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nsub ecx, eax\nmov edx, ecx\nmovsxd rax, esi\nmov [rbp+rax*4+var_1A0], edx\nmov eax, [rbp+var_1C0]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_1C0], eax\nloc_120F:\ncmp [rbp+var_1C0], 0\njg short loc_11A5\nmov [rbp+var_1B8], 0\nmov eax, [rbp+var_1BC]\nsub eax, 1\nmov [rbp+var_1B4], eax\njmp short loc_1289\nloc_1233:\nmov eax, [rbp+var_1B8]\ncdqe\nmov eax, [rbp+rax*4+var_1A0]\nmov [rbp+var_1A4], eax\nmov eax, [rbp+var_1B4]\ncdqe\nmov edx, [rbp+rax*4+var_1A0]\nmov eax, [rbp+var_1B8]\ncdqe\nmov [rbp+rax*4+var_1A0], edx\nmov eax, [rbp+var_1B4]\ncdqe\nmov edx, [rbp+var_1A4]\nmov [rbp+rax*4+var_1A0], edx\nadd [rbp+var_1B8], 1\nsub [rbp+var_1B4], 1\nloc_1289:\nmov eax, [rbp+var_1B8]\ncmp eax, [rbp+var_1B4]\njl short loc_1233\nmov [rbp+var_1B0], 0\nmov eax, [rbp+var_1BC]\nmov [rbp+var_1AC], eax\njmp short loc_1313\nloc_12AF:\nmov [rbp+var_1B0], 0\nmov [rbp+var_1A8], 1\njmp short loc_12E7\nloc_12C5:\nmov eax, [rbp+var_1AC]\nsub eax, [rbp+var_1A8]\ncdqe\nmov eax, [rbp+rax*4+var_1A0]\nadd [rbp+var_1B0], eax\nadd [rbp+var_1A8], 1\nloc_12E7:\nmov eax, [rbp+var_1A8]\ncmp eax, [rbp+var_1BC]\njle short loc_12C5\nmov eax, [rbp+var_1AC]\nlea edx, [rax+1]\nmov [rbp+var_1AC], edx\ncdqe\nmov edx, [rbp+var_1B0]\nmov [rbp+rax*4+var_1A0], edx\nloc_1313:\nmov eax, [rbp+var_1B0]\ncmp eax, [rbp+var_1C4]\njl short loc_12AF\nmov eax, [rbp+var_1B0]\ncmp eax, [rbp+var_1C4]\nsetz al\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1344\ncall ___stack_chk_fail\nlocret_1344:\nleave\nretn", + "ida_strip_pseudo": "bool __fastcall sub_1169(int a1)\n{\n int v1; // esi\n int v2; // eax\n int v4; // [rsp+10h] [rbp-1C0h]\n int v5; // [rsp+14h] [rbp-1BCh]\n int v6; // [rsp+18h] [rbp-1B8h]\n int i; // [rsp+1Ch] [rbp-1B4h]\n int v8; // [rsp+20h] [rbp-1B0h]\n int v9; // [rsp+24h] [rbp-1ACh]\n int j; // [rsp+28h] [rbp-1A8h]\n int v11; // [rsp+2Ch] [rbp-1A4h]\n _DWORD v12[102]; // [rsp+30h] [rbp-1A0h]\n unsigned __int64 v13; // [rsp+1C8h] [rbp-8h]\n\n v13 = __readfsqword(0x28u);\n v4 = a1;\n v5 = 0;\n while ( v4 > 0 )\n {\n v1 = v5++;\n v12[v1] = v4 % 10;\n v4 /= 10;\n }\n v6 = 0;\n for ( i = v5 - 1; v6 < i; --i )\n {\n v11 = v12[v6];\n v12[v6] = v12[i];\n v12[i] = v11;\n ++v6;\n }\n v8 = 0;\n v9 = v5;\n while ( v8 < a1 )\n {\n v8 = 0;\n for ( j = 1; j <= v5; ++j )\n v8 += v12[v9 - j];\n v2 = v9++;\n v12[v2] = v8;\n }\n return v8 == a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_1169(int a1) {\n int v1;\n int v2;\n int v4;\n int v5;\n int v6;\n int i;\n int v8;\n int v9;\n int j;\n int v11;\n uint32_t v12[102];\n unsigned long long v13;\n v13 = __readfsqword(40u);\n v4 = a1;\n v5 = 0;\n while (v4 > 0) {\n v1 = v5++;\n v12[v1] = v4 % 10;\n v4 /= 10;\n }\n v6 = 0;\n for (i = v5 - 1; v6 < i; --i) {\n v11 = v12[v6];\n v12[v6] = v12[i];\n v12[i] = v11;\n ++v6;\n }\n v8 = 0;\n v9 = v5;\n while (v8 < a1) {\n v8 = 0;\n for (j = 1; j <= v5; ++j) v8 += v12[v9 - j];\n v2 = v9++;\n v12[v2] = v8;\n }\n return v8 == a1;\n}", + "ida_pseudo_norm": "bool func0(int a1) {\n int v1;\n int v2;\n int v4;\n int v5;\n int v6;\n int i;\n int v8;\n int v9;\n int j;\n int v11;\n uint32_t v12[102];\n unsigned long long v13;\n v13 = __readfsqword(40u);\n v4 = a1;\n v5 = 0;\n while (v4 > 0) {\n v1 = v5++;\n v12[v1] = v4 % 10;\n v4 /= 10;\n }\n v6 = 0;\n for (i = v5 - 1; v6 < i; --i) {\n v11 = v12[v6];\n v12[v6] = v12[i];\n v12[i] = v11;\n ++v6;\n }\n v8 = 0;\n v9 = v5;\n while (v8 < a1) {\n v8 = 0;\n for (j = 1; j <= v5; ++j) v8 += v12[v9 - j];\n v2 = v9++;\n v12[v2] = v8;\n }\n return v8 == a1;\n}" + }, + { + "index": 179, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int x) {\n int terms[100], temp = x, n = 0;\n while (temp > 0) {\n terms[n++] = temp % 10;\n temp /= 10;\n }\n for (int left = 0, right = n - 1; left < right; left++, right--) {\n int temp = terms[left];\n terms[left] = terms[right];\n terms[right] = temp;\n }\n int next_term = 0, i = n;\n while (next_term < x) {\n next_term = 0;\n for (int j = 1; j <= n; j++) {\n next_term += terms[i - j];\n }\n terms[i++] = next_term;\n }\n return (next_term == x);\n}", + "test": "int main() {\n\n assert(func0(14) == true);\n\n assert(func0(12) == false);\n\n assert(func0(197) == true);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x1a8,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x198(%rsp)\nxor %eax,%eax\ntest %edi,%edi\njle 122c \nmov %rsp,%rcx\nmov %rcx,%r10\nmov %edi,%edx\nmov $0x0,%esi\nmov %esi,%r9d\nadd $0x1,%esi\nmovslq %edx,%rax\nimul $0x66666667,%rax,%rax\nsar $0x22,%rax\nmov %edx,%r8d\nsar $0x1f,%r8d\nsub %r8d,%eax\nlea (%rax,%rax,4),%r8d\nadd %r8d,%r8d\nmov %edx,%r11d\nsub %r8d,%r11d\nmov %r11d,(%r10)\nmov %edx,%r8d\nmov %eax,%edx\nadd $0x4,%r10\ncmp $0x9,%r8d\njg 119c \ntest %r9d,%r9d\njle 120a \nmovslq %r9d,%rax\nlea (%rsp,%rax,4),%rdx\nmov %r9d,%eax\nmov (%rcx),%r8d\nmov (%rdx),%r10d\nmov %r10d,(%rcx)\nmov %r8d,(%rdx)\nsub $0x1,%eax\nadd $0x4,%rcx\nsub $0x4,%rdx\nmov %r9d,%r8d\nsub %eax,%r8d\ncmp %r8d,%eax\njg 11e8 \nmovslq %esi,%rax\nshl $0x2,%rax\nlea (%rsp,%rax,1),%r8\nlea -0x4(%rsp,%rax,1),%rcx\nmov %r9d,%eax\nshl $0x2,%rax\nsub %rax,%rcx\nmov $0x0,%r9d\njmp 1242 \nmov $0x0,%edx\njmp 125f \nmovl $0x0,(%r8)\nadd $0x4,%r8\nadd $0x4,%rcx\nmov %r8,%rax\nmov %r9d,%edx\ntest %esi,%esi\njle 1233 \nadd -0x4(%rax),%edx\nsub $0x4,%rax\ncmp %rcx,%rax\njne 124c \nmov %edx,(%r8)\ncmp %edx,%edi\njg 123a \ncmp %edx,%edi\nsete %al\nmov 0x198(%rsp),%rdi\nxor %fs:0x28,%rdi\njne 127f \nadd $0x1a8,%rsp\nretq\ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 1A8h\nmov r8d, edi\nmov rax, fs:28h\nmov [rsp+1A8h+var_10], rax\nxor eax, eax\ntest edi, edi\njle loc_1224\nmov rcx, rsp\nmov r9, rcx\nmov edx, edi\nmov edi, 0\nloc_119F:\nmov r10d, edi\nadd edi, 1\nmovsxd rax, edx\nimul rax, 66666667h\nsar rax, 22h\nmov esi, edx\nsar esi, 1Fh\nsub eax, esi\nlea esi, [rax+rax*4]\nadd esi, esi\nmov r11d, edx\nsub r11d, esi\nmov [r9], r11d\nmov esi, edx\nmov edx, eax\nadd r9, 4\ncmp esi, 9\njg short loc_119F\ntest r10d, r10d\njle short loc_1202\nmovsxd rax, r10d\nlea rdx, [rsp+rax*4+1A8h+var_1A8]\nmov eax, r10d\nloc_11E4:\nmov esi, [rcx]\nmov r9d, [rdx]\nmov [rcx], r9d\nmov [rdx], esi\nsub eax, 1\nadd rcx, 4\nsub rdx, 4\nmov esi, r10d\nsub esi, eax\ncmp eax, esi\njg short loc_11E4\nloc_1202:\nmovsxd rax, edi\nshl rax, 2\nlea r9, [rsp+rax+1A8h+var_1A8]\nlea rsi, [rsp+rax+1A8h+var_1AC]\nmov eax, r10d\nshl rax, 2\nsub rsi, rax\nmov r10d, 0\njmp short loc_123A\nloc_1224:\nmov ecx, 0\njmp short loc_1260\nloc_122B:\nmov dword ptr [r9], 0\nadd r9, 4\nadd rsi, 4\nloc_123A:\nmov rax, r9\nmov ecx, r10d\ntest edi, edi\njle short loc_122B\nloc_1244:\nadd ecx, [rax-4]\nsub rax, 4\ncmp rax, rsi\njnz short loc_1244\nmov [r9], ecx\nadd r9, 4\nadd rsi, 4\ncmp r8d, ecx\njg short loc_123A\nloc_1260:\ncmp r8d, ecx\nsetz al\nmov rdx, [rsp+1A8h+var_10]\nsub rdx, fs:28h\njnz short loc_1281\nadd rsp, 1A8h\nretn\nloc_1281:\ncall ___stack_chk_fail", + "ida_pseudo": "bool __fastcall func0(int a1)\n{\n int *v2; // rcx\n int *v3; // r9\n int v4; // edx\n int v5; // edi\n int v6; // r10d\n int v7; // esi\n int *v8; // rdx\n int v9; // eax\n int v10; // esi\n __int64 v11; // rax\n int *v12; // r9\n int *v13; // rsi\n int v14; // ecx\n int *v15; // rax\n _BYTE v17[4]; // [rsp+0h] [rbp-1ACh] BYREF\n _BYTE v18[408]; // [rsp+4h] [rbp-1A8h] BYREF\n unsigned __int64 v19; // [rsp+19Ch] [rbp-10h]\n\n v19 = __readfsqword(0x28u);\n if ( a1 <= 0 )\n {\n v14 = 0;\n }\n else\n {\n v2 = (int *)v18;\n v3 = (int *)v18;\n v4 = a1;\n v5 = 0;\n do\n {\n v6 = v5++;\n *v3 = v4 % 10;\n v7 = v4;\n v4 /= 10;\n ++v3;\n }\n while ( v7 > 9 );\n if ( v6 > 0 )\n {\n v8 = (int *)&v18[4 * v6];\n v9 = v6;\n do\n {\n v10 = *v2;\n *v2 = *v8;\n *v8 = v10;\n --v9;\n ++v2;\n --v8;\n }\n while ( v9 > v6 - v9 );\n }\n v11 = 4LL * v5;\n v12 = (int *)&v18[v11];\n v13 = (int *)&v17[v11 + -4 * (unsigned int)v6];\n do\n {\n while ( 1 )\n {\n v15 = v12;\n v14 = 0;\n if ( v5 > 0 )\n break;\n *v12++ = 0;\n ++v13;\n }\n do\n v14 += *--v15;\n while ( v15 != v13 );\n *v12++ = v14;\n ++v13;\n }\n while ( a1 > v14 );\n }\n return a1 == v14;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nsub rsp, 1A8h\nmov r8d, edi\nmov rax, fs:28h\nmov [rsp+1A8h+var_10], rax\nxor eax, eax\ntest edi, edi\njle loc_1224\nmov rcx, rsp\nmov r9, rcx\nmov edx, edi\nmov edi, 0\nloc_119F:\nmov r10d, edi\nadd edi, 1\nmovsxd rax, edx\nimul rax, 66666667h\nsar rax, 22h\nmov esi, edx\nsar esi, 1Fh\nsub eax, esi\nlea esi, [rax+rax*4]\nadd esi, esi\nmov r11d, edx\nsub r11d, esi\nmov [r9], r11d\nmov esi, edx\nmov edx, eax\nadd r9, 4\ncmp esi, 9\njg short loc_119F\ntest r10d, r10d\njle short loc_1202\nmovsxd rax, r10d\nlea rdx, [rsp+rax*4+1A8h+var_1A8]\nmov eax, r10d\nloc_11E4:\nmov esi, [rcx]\nmov r9d, [rdx]\nmov [rcx], r9d\nmov [rdx], esi\nsub eax, 1\nadd rcx, 4\nsub rdx, 4\nmov esi, r10d\nsub esi, eax\ncmp eax, esi\njg short loc_11E4\nloc_1202:\nmovsxd rax, edi\nshl rax, 2\nlea r9, [rsp+rax+1A8h+var_1A8]\nlea rsi, [rsp+rax+1A8h+var_1AC]\nmov eax, r10d\nshl rax, 2\nsub rsi, rax\nmov r10d, 0\njmp short loc_123A\nloc_1224:\nmov ecx, 0\njmp short loc_1260\nloc_122B:\nmov dword ptr [r9], 0\nadd r9, 4\nadd rsi, 4\nloc_123A:\nmov rax, r9\nmov ecx, r10d\ntest edi, edi\njle short loc_122B\nloc_1244:\nadd ecx, [rax-4]\nsub rax, 4\ncmp rax, rsi\njnz short loc_1244\nmov [r9], ecx\nadd r9, 4\nadd rsi, 4\ncmp r8d, ecx\njg short loc_123A\nloc_1260:\ncmp r8d, ecx\nsetz al\nmov rdx, [rsp+1A8h+var_10]\nsub rdx, fs:28h\njnz short loc_1281\nadd rsp, 1A8h\nretn\nloc_1281:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "bool __fastcall sub_1169(int a1)\n{\n int *v2; // rcx\n int *v3; // r9\n int v4; // edx\n int v5; // edi\n int v6; // r10d\n int v7; // esi\n int *v8; // rdx\n int v9; // eax\n int v10; // esi\n __int64 v11; // rax\n int *v12; // r9\n int *v13; // rsi\n int v14; // ecx\n int *v15; // rax\n _BYTE v17[4]; // [rsp+0h] [rbp-1ACh] BYREF\n _BYTE v18[408]; // [rsp+4h] [rbp-1A8h] BYREF\n unsigned __int64 v19; // [rsp+19Ch] [rbp-10h]\n\n v19 = __readfsqword(0x28u);\n if ( a1 <= 0 )\n {\n v14 = 0;\n }\n else\n {\n v2 = (int *)v18;\n v3 = (int *)v18;\n v4 = a1;\n v5 = 0;\n do\n {\n v6 = v5++;\n *v3 = v4 % 10;\n v7 = v4;\n v4 /= 10;\n ++v3;\n }\n while ( v7 > 9 );\n if ( v6 > 0 )\n {\n v8 = (int *)&v18[4 * v6];\n v9 = v6;\n do\n {\n v10 = *v2;\n *v2 = *v8;\n *v8 = v10;\n --v9;\n ++v2;\n --v8;\n }\n while ( v9 > v6 - v9 );\n }\n v11 = 4LL * v5;\n v12 = (int *)&v18[v11];\n v13 = (int *)&v17[v11 + -4 * (unsigned int)v6];\n do\n {\n while ( 1 )\n {\n v15 = v12;\n v14 = 0;\n if ( v5 > 0 )\n break;\n *v12++ = 0;\n ++v13;\n }\n do\n v14 += *--v15;\n while ( v15 != v13 );\n *v12++ = v14;\n ++v13;\n }\n while ( a1 > v14 );\n }\n return a1 == v14;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_1169(int a1) {\n int *v2;\n int *v3;\n int v4;\n int v5;\n int v6;\n int v7;\n int *v8;\n int v9;\n int v10;\n long long v11;\n int *v12;\n int *v13;\n int v14;\n int *v15;\n uint8_t v17[4];\n uint8_t v18[408];\n unsigned long long v19;\n v19 = __readfsqword(40u);\n if (a1 <= 0) {\n v14 = 0;\n } else {\n v2 = (int *)v18;\n v3 = (int *)v18;\n v4 = a1;\n v5 = 0;\n do {\n v6 = v5++;\n *v3 = v4 % 10;\n v7 = v4;\n v4 /= 10;\n ++v3;\n } while (v7 > 9);\n if (v6 > 0) {\n v8 = (int *)&v18[4 * v6];\n v9 = v6;\n do {\n v10 = *v2;\n *v2 = *v8;\n *v8 = v10;\n --v9;\n ++v2;\n --v8;\n } while (v9 > v6 - v9);\n }\n v11 = 4LL * v5;\n v12 = (int *)&v18[v11];\n v13 = (int *)&v17[v11 + -4 * (unsigned int)v6];\n do {\n while (1) {\n v15 = v12;\n v14 = 0;\n if (v5 > 0) break;\n *v12++ = 0;\n ++v13;\n }\n do\n v14 += *--v15;\n while (v15 != v13);\n *v12++ = v14;\n ++v13;\n } while (a1 > v14);\n }\n return a1 == v14;\n}", + "ida_pseudo_norm": "bool func0(int a1) {\n int *v2;\n int *v3;\n int v4;\n int v5;\n int v6;\n int v7;\n int *v8;\n int v9;\n int v10;\n long long v11;\n int *v12;\n int *v13;\n int v14;\n int *v15;\n uint8_t v17[4];\n uint8_t v18[408];\n unsigned long long v19;\n v19 = __readfsqword(40u);\n if (a1 <= 0) {\n v14 = 0;\n } else {\n v2 = (int *)v18;\n v3 = (int *)v18;\n v4 = a1;\n v5 = 0;\n do {\n v6 = v5++;\n *v3 = v4 % 10;\n v7 = v4;\n v4 /= 10;\n ++v3;\n } while (v7 > 9);\n if (v6 > 0) {\n v8 = (int *)&v18[4 * v6];\n v9 = v6;\n do {\n v10 = *v2;\n *v2 = *v8;\n *v8 = v10;\n --v9;\n ++v2;\n --v8;\n } while (v9 > v6 - v9);\n }\n v11 = 4LL * v5;\n v12 = (int *)&v18[v11];\n v13 = (int *)&v17[v11 + -4 * (unsigned int)v6];\n do {\n while (1) {\n v15 = v12;\n v14 = 0;\n if (v5 > 0) break;\n *v12++ = 0;\n ++v13;\n }\n do\n v14 += *--v15;\n while (v15 != v13);\n *v12++ = v14;\n ++v13;\n } while (a1 > v14);\n }\n return a1 == v14;\n}" + }, + { + "index": 179, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int x) {\n int terms[100], temp = x, n = 0;\n while (temp > 0) {\n terms[n++] = temp % 10;\n temp /= 10;\n }\n for (int left = 0, right = n - 1; left < right; left++, right--) {\n int temp = terms[left];\n terms[left] = terms[right];\n terms[right] = temp;\n }\n int next_term = 0, i = n;\n while (next_term < x) {\n next_term = 0;\n for (int j = 1; j <= n; j++) {\n next_term += terms[i - j];\n }\n terms[i++] = next_term;\n }\n return (next_term == x);\n}", + "test": "int main() {\n\n assert(func0(14) == true);\n\n assert(func0(12) == false);\n\n assert(func0(197) == true);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x1a8,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x198(%rsp)\nxor %eax,%eax\ntest %edi,%edi\njle 12fc \nmov %rsp,%rsi\nmov %edi,%edx\nxor %r10d,%r10d\nmov $0xcccccccd,%ebp\nmov %rsi,%rcx\nmov %rsi,%r11\nnopl 0x0(%rax,%rax,1)\nmov %edx,%eax\nmov %edx,%ebx\nmov %r10d,%r9d\nadd $0x4,%r11\nimul %rbp,%rax\nadd $0x1,%r10d\nshr $0x23,%rax\nmov %eax,%r8d\nlea (%rax,%rax,4),%eax\nadd %eax,%eax\nsub %eax,%ebx\nmov %ebx,-0x4(%r11)\nmov %ebx,%eax\nmov %edx,%ebx\nmov %r8d,%edx\ncmp $0x9,%ebx\njg 1250 \ntest %r9d,%r9d\nje 12b8 \nmovslq %r9d,%rdx\nlea (%rsi,%rdx,4),%r8\nmov %r9d,%edx\njmp 129b \nnopw 0x0(%rax,%rax,1)\nmov (%r8),%eax\nmov (%rcx),%r11d\nsub $0x1,%edx\nmov %eax,(%rcx)\nmov %r9d,%eax\nsub %edx,%eax\nadd $0x4,%rcx\nsub $0x4,%r8\nmov %r11d,0x4(%r8)\ncmp %eax,%edx\njg 1298 \nmovslq %r10d,%rax\nshl $0x2,%rax\nlea -0x4(%rsp,%rax,1),%rcx\nadd %rax,%rsi\nmov %r9d,%eax\nshl $0x2,%rax\nsub %rax,%rcx\nnopl 0x0(%rax)\nmov %rsi,%rax\nxor %edx,%edx\nnopl (%rax)\nadd -0x4(%rax),%edx\nsub $0x4,%rax\ncmp %rcx,%rax\njne 12e0 \nmov %edx,(%rsi)\ncmp %edx,%edi\njle 1300 \nadd $0x4,%rsi\nadd $0x4,%rcx\njmp 12d8 \nxor %edx,%edx\nxchg %ax,%ax\ncmp %edx,%edi\nsete %al\nmov 0x198(%rsp),%rdi\nxor %fs:0x28,%rdi\njne 1322 \nadd $0x1a8,%rsp\npop %rbx\npop %rbp\nretq\ncallq 1060 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nsub rsp, 1A0h\nmov rax, fs:28h\nmov [rsp+1A8h+var_10], rax\nxor eax, eax\ntest edi, edi\njle loc_1313\nmov r8, rsp\nmov edx, edi\nxor esi, esi\nmov ebx, 0CCCCCCCDh\nmov r9, r8\nnop word ptr [rax+rax+00000000h]\nloc_1250:\nmov eax, edx\nmov r11d, edx\nmov r10d, esi\nadd r9, 4\nimul rax, rbx\nadd esi, 1\nshr rax, 23h\nlea ecx, [rax+rax*4]\nadd ecx, ecx\nsub r11d, ecx\nmov ecx, edx\nmov edx, eax\nmov [r9-4], r11d\ncmp ecx, 9\njg short loc_1250\nxor ebx, ebx\ntest r10d, r10d\njz short loc_12B4\nmovsxd rbx, r10d\nmov rdx, r8\nmov eax, r10d\nlea rcx, [r8+rbx*4]\nloc_1290:\nmov r9d, [rdx]\nmov r11d, [rcx]\nsub eax, 1\nadd rdx, 4\nsub rcx, 4\nmov [rdx-4], r11d\nmov [rcx+4], r9d\nmov r9d, r10d\nsub r9d, eax\ncmp eax, r9d\njg short loc_1290\nloc_12B4:\nmovsxd rax, esi\nshl rbx, 2\nshl rax, 2\nlea rcx, [r8+rax-4]\nlea rsi, [r8+rax]\nsub rcx, rbx\nnop dword ptr [rax+rax+00h]\nloc_12D0:\nmov rax, rsi\nxor edx, edx\nnop dword ptr [rax]\nloc_12D8:\nadd edx, [rax-4]\nsub rax, 4\ncmp rax, rcx\njnz short loc_12D8\nmov [rsi], edx\nadd rcx, 4\nadd rsi, 4\ncmp edi, edx\njg short loc_12D0\nloc_12F2:\ncmp edi, edx\nsetz al\nmov rdx, [rsp+1A8h+var_10]\nsub rdx, fs:28h\njnz short loc_1317\nadd rsp, 1A0h\npop rbx\nretn\nloc_1313:\nxor edx, edx\njmp short loc_12F2\nloc_1317:\ncall ___stack_chk_fail", + "ida_pseudo": "bool __fastcall func0(int a1)\n{\n unsigned int v1; // edx\n int v2; // esi\n _DWORD *v3; // r9\n int v4; // r10d\n unsigned int v5; // r11d\n int v6; // ecx\n __int64 v7; // rbx\n int *v8; // rdx\n int v9; // eax\n int *v10; // rcx\n int v11; // r9d\n int v12; // r11d\n int *v13; // rsi\n __int64 v14; // rcx\n int *v15; // rax\n int v16; // edx\n _DWORD v18[102]; // [rsp+0h] [rbp-1A8h] BYREF\n unsigned __int64 v19; // [rsp+198h] [rbp-10h]\n\n v19 = __readfsqword(0x28u);\n if ( a1 <= 0 )\n {\n v16 = 0;\n }\n else\n {\n v1 = a1;\n v2 = 0;\n v3 = v18;\n do\n {\n v4 = v2;\n ++v3;\n ++v2;\n v5 = v1 % 0xA;\n v6 = v1;\n v1 /= 0xAu;\n *(v3 - 1) = v5;\n }\n while ( v6 > 9 );\n v7 = 0LL;\n if ( v4 )\n {\n v7 = v4;\n v8 = v18;\n v9 = v4;\n v10 = &v18[v4];\n do\n {\n v11 = *v8;\n v12 = *v10;\n --v9;\n ++v8;\n --v10;\n *(v8 - 1) = v12;\n v10[1] = v11;\n }\n while ( v9 > v4 - v9 );\n }\n v13 = &v18[v2];\n v14 = (__int64)&v13[-v7 - 1];\n do\n {\n v15 = v13;\n v16 = 0;\n do\n v16 += *--v15;\n while ( v15 != (int *)v14 );\n *v13 = v16;\n v14 += 4LL;\n ++v13;\n }\n while ( a1 > v16 );\n }\n return a1 == v16;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbx\nsub rsp, 1A0h\nmov rax, fs:28h\nmov [rsp+1A8h+var_10], rax\nxor eax, eax\ntest edi, edi\njle loc_1313\nmov r8, rsp\nmov edx, edi\nxor esi, esi\nmov ebx, 0CCCCCCCDh\nmov r9, r8\nnop word ptr [rax+rax+00000000h]\nloc_1250:\nmov eax, edx\nmov r11d, edx\nmov r10d, esi\nadd r9, 4\nimul rax, rbx\nadd esi, 1\nshr rax, 23h\nlea ecx, [rax+rax*4]\nadd ecx, ecx\nsub r11d, ecx\nmov ecx, edx\nmov edx, eax\nmov [r9-4], r11d\ncmp ecx, 9\njg short loc_1250\nxor ebx, ebx\ntest r10d, r10d\njz short loc_12B4\nmovsxd rbx, r10d\nmov rdx, r8\nmov eax, r10d\nlea rcx, [r8+rbx*4]\nloc_1290:\nmov r9d, [rdx]\nmov r11d, [rcx]\nsub eax, 1\nadd rdx, 4\nsub rcx, 4\nmov [rdx-4], r11d\nmov [rcx+4], r9d\nmov r9d, r10d\nsub r9d, eax\ncmp eax, r9d\njg short loc_1290\nloc_12B4:\nmovsxd rax, esi\nshl rbx, 2\nshl rax, 2\nlea rcx, [r8+rax-4]\nlea rsi, [r8+rax]\nsub rcx, rbx\nnop dword ptr [rax+rax+00h]\nloc_12D0:\nmov rax, rsi\nxor edx, edx\nnop dword ptr [rax]\nloc_12D8:\nadd edx, [rax-4]\nsub rax, 4\ncmp rax, rcx\njnz short loc_12D8\nmov [rsi], edx\nadd rcx, 4\nadd rsi, 4\ncmp edi, edx\njg short loc_12D0\nloc_12F2:\ncmp edi, edx\nsetz al\nmov rdx, [rsp+1A8h+var_10]\nsub rdx, fs:28h\njnz short loc_1317\nadd rsp, 1A0h\npop rbx\nretn\nloc_1313:\nxor edx, edx\njmp short loc_12F2\nloc_1317:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "bool __fastcall sub_1210(int a1)\n{\n unsigned int v1; // edx\n int v2; // esi\n _DWORD *v3; // r9\n int v4; // r10d\n unsigned int v5; // r11d\n int v6; // ecx\n __int64 v7; // rbx\n int *v8; // rdx\n int v9; // eax\n int *v10; // rcx\n int v11; // r9d\n int v12; // r11d\n int *v13; // rsi\n __int64 v14; // rcx\n int *v15; // rax\n int v16; // edx\n _DWORD v18[102]; // [rsp+0h] [rbp-1A8h] BYREF\n unsigned __int64 v19; // [rsp+198h] [rbp-10h]\n\n v19 = __readfsqword(0x28u);\n if ( a1 <= 0 )\n {\n v16 = 0;\n }\n else\n {\n v1 = a1;\n v2 = 0;\n v3 = v18;\n do\n {\n v4 = v2;\n ++v3;\n ++v2;\n v5 = v1 % 0xA;\n v6 = v1;\n v1 /= 0xAu;\n *(v3 - 1) = v5;\n }\n while ( v6 > 9 );\n v7 = 0LL;\n if ( v4 )\n {\n v7 = v4;\n v8 = v18;\n v9 = v4;\n v10 = &v18[v4];\n do\n {\n v11 = *v8;\n v12 = *v10;\n --v9;\n ++v8;\n --v10;\n *(v8 - 1) = v12;\n v10[1] = v11;\n }\n while ( v9 > v4 - v9 );\n }\n v13 = &v18[v2];\n v14 = (__int64)&v13[-v7 - 1];\n do\n {\n v15 = v13;\n v16 = 0;\n do\n v16 += *--v15;\n while ( v15 != (int *)v14 );\n *v13 = v16;\n v14 += 4LL;\n ++v13;\n }\n while ( a1 > v16 );\n }\n return a1 == v16;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_1210(int a1) {\n unsigned int v1;\n int v2;\n uint32_t *v3;\n int v4;\n unsigned int v5;\n int v6;\n long long v7;\n int *v8;\n int v9;\n int *v10;\n int v11;\n int v12;\n int *v13;\n long long v14;\n int *v15;\n int v16;\n uint32_t v18[102];\n unsigned long long v19;\n v19 = __readfsqword(40u);\n if (a1 <= 0) {\n v16 = 0;\n } else {\n v1 = a1;\n v2 = 0;\n v3 = v18;\n do {\n v4 = v2;\n ++v3;\n ++v2;\n v5 = v1 % 10;\n v6 = v1;\n v1 /= 10u;\n *(v3 - 1) = v5;\n } while (v6 > 9);\n v7 = 0LL;\n if (v4) {\n v7 = v4;\n v8 = v18;\n v9 = v4;\n v10 = &v18[v4];\n do {\n v11 = *v8;\n v12 = *v10;\n --v9;\n ++v8;\n --v10;\n *(v8 - 1) = v12;\n v10[1] = v11;\n } while (v9 > v4 - v9);\n }\n v13 = &v18[v2];\n v14 = (long long)&v13[-v7 - 1];\n do {\n v15 = v13;\n v16 = 0;\n do\n v16 += *--v15;\n while (v15 != (int *)v14);\n *v13 = v16;\n v14 += 4LL;\n ++v13;\n } while (a1 > v16);\n }\n return a1 == v16;\n}", + "ida_pseudo_norm": "bool func0(int a1) {\n unsigned int v1;\n int v2;\n uint32_t *v3;\n int v4;\n unsigned int v5;\n int v6;\n long long v7;\n int *v8;\n int v9;\n int *v10;\n int v11;\n int v12;\n int *v13;\n long long v14;\n int *v15;\n int v16;\n uint32_t v18[102];\n unsigned long long v19;\n v19 = __readfsqword(40u);\n if (a1 <= 0) {\n v16 = 0;\n } else {\n v1 = a1;\n v2 = 0;\n v3 = v18;\n do {\n v4 = v2;\n ++v3;\n ++v2;\n v5 = v1 % 10;\n v6 = v1;\n v1 /= 10u;\n *(v3 - 1) = v5;\n } while (v6 > 9);\n v7 = 0LL;\n if (v4) {\n v7 = v4;\n v8 = v18;\n v9 = v4;\n v10 = &v18[v4];\n do {\n v11 = *v8;\n v12 = *v10;\n --v9;\n ++v8;\n --v10;\n *(v8 - 1) = v12;\n v10[1] = v11;\n } while (v9 > v4 - v9);\n }\n v13 = &v18[v2];\n v14 = (long long)&v13[-v7 - 1];\n do {\n v15 = v13;\n v16 = 0;\n do\n v16 += *--v15;\n while (v15 != (int *)v14);\n *v13 = v16;\n v14 += 4LL;\n ++v13;\n } while (a1 > v16);\n }\n return a1 == v16;\n}" + }, + { + "index": 179, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int x) {\n int terms[100], temp = x, n = 0;\n while (temp > 0) {\n terms[n++] = temp % 10;\n temp /= 10;\n }\n for (int left = 0, right = n - 1; left < right; left++, right--) {\n int temp = terms[left];\n terms[left] = terms[right];\n terms[right] = temp;\n }\n int next_term = 0, i = n;\n while (next_term < x) {\n next_term = 0;\n for (int j = 1; j <= n; j++) {\n next_term += terms[i - j];\n }\n terms[i++] = next_term;\n }\n return (next_term == x);\n}", + "test": "int main() {\n\n assert(func0(14) == true);\n\n assert(func0(12) == false);\n\n assert(func0(197) == true);\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r12\npush %rbp\npush %rbx\nsub $0x1a8,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x198(%rsp)\nxor %eax,%eax\ntest %edi,%edi\njle 15f9 \nmov %rsp,%rbx\nmov %edi,%edx\nxor %esi,%esi\nmov $0xcccccccd,%r10d\nmov %rbx,%r11\nmov %rbx,%r8\nmov %edx,%eax\nmov %edx,%ebp\nmov %esi,%r9d\nadd $0x4,%r8\nimul %r10,%rax\nadd $0x1,%esi\nshr $0x23,%rax\nlea (%rax,%rax,4),%ecx\nadd %ecx,%ecx\nsub %ecx,%ebp\nmov %edx,%ecx\nmov %eax,%edx\nmov %ebp,-0x4(%r8)\ncmp $0x9,%ecx\njg 1250 \ntest %r9d,%r9d\nje 1513 \nlea -0x1(%r9),%ecx\nmovslq %r9d,%r8\nmov %ecx,%edx\nlea 0x4(,%r8,4),%r8\nshr %edx\nlea 0x1(%rdx),%eax\nmov %rax,%rdx\nlea 0x0(,%rax,4),%r10\nneg %rax\nlea (%r8,%rax,4),%rax\ncmp %rax,%r10\njg 1626 \ncmp $0x5,%ecx\njbe 1626 \nlea -0x10(%rbx,%r8,1),%rax\nmovdqa (%rsp),%xmm0\nmov %edx,%ecx\nmovdqu (%rax),%xmm3\nshr $0x2,%ecx\npshufd $0x1b,%xmm0,%xmm0\npshufd $0x1b,%xmm3,%xmm1\nmovaps %xmm1,(%rsp)\nmovups %xmm0,(%rax)\ncmp $0x1,%ecx\nje 14b0 \nmovdqa 0x10(%rsp),%xmm0\nmovdqu -0x10(%rax),%xmm4\npshufd $0x1b,%xmm0,%xmm0\npshufd $0x1b,%xmm4,%xmm1\nmovaps %xmm1,0x10(%rsp)\nmovups %xmm0,-0x10(%rax)\ncmp $0x2,%ecx\nje 14b0 \nmovdqa 0x20(%rsp),%xmm0\nmovdqu -0x20(%rax),%xmm5\npshufd $0x1b,%xmm0,%xmm0\npshufd $0x1b,%xmm5,%xmm1\nmovaps %xmm1,0x20(%rsp)\nmovups %xmm0,-0x20(%rax)\ncmp $0x3,%ecx\nje 14b0 \nmovdqa 0x30(%rsp),%xmm0\nmovdqu -0x30(%rax),%xmm6\npshufd $0x1b,%xmm0,%xmm0\npshufd $0x1b,%xmm6,%xmm1\nmovaps %xmm1,0x30(%rsp)\nmovups %xmm0,-0x30(%rax)\ncmp $0x4,%ecx\nje 14b0 \nmovdqa 0x40(%rsp),%xmm0\nmovdqu -0x40(%rax),%xmm7\npshufd $0x1b,%xmm0,%xmm0\npshufd $0x1b,%xmm7,%xmm1\nmovaps %xmm1,0x40(%rsp)\nmovups %xmm0,-0x40(%rax)\ncmp $0x5,%ecx\nje 14b0 \nmovdqa 0x50(%rsp),%xmm0\nmovdqu -0x50(%rax),%xmm7\npshufd $0x1b,%xmm0,%xmm0\npshufd $0x1b,%xmm7,%xmm1\nmovaps %xmm1,0x50(%rsp)\nmovups %xmm0,-0x50(%rax)\ncmp $0x6,%ecx\nje 14b0 \nmovdqa 0x60(%rsp),%xmm0\nmovdqu -0x60(%rax),%xmm6\npshufd $0x1b,%xmm0,%xmm0\npshufd $0x1b,%xmm6,%xmm1\nmovaps %xmm1,0x60(%rsp)\nmovups %xmm0,-0x60(%rax)\ncmp $0x7,%ecx\nje 14b0 \nmovdqa 0x70(%rsp),%xmm0\nmovdqu -0x70(%rax),%xmm5\npshufd $0x1b,%xmm0,%xmm0\npshufd $0x1b,%xmm5,%xmm1\nmovaps %xmm1,0x70(%rsp)\nmovups %xmm0,-0x70(%rax)\ncmp $0x8,%ecx\nje 14b0 \nmovdqa 0x80(%rsp),%xmm0\nmovdqu -0x80(%rax),%xmm7\npshufd $0x1b,%xmm0,%xmm0\npshufd $0x1b,%xmm7,%xmm1\nmovaps %xmm1,0x80(%rsp)\nmovups %xmm0,-0x80(%rax)\ncmp $0x9,%ecx\nje 14b0 \nmovdqa 0x90(%rsp),%xmm0\nmovdqu -0x90(%rax),%xmm4\npshufd $0x1b,%xmm0,%xmm0\npshufd $0x1b,%xmm4,%xmm1\nmovaps %xmm1,0x90(%rsp)\nmovups %xmm0,-0x90(%rax)\ncmp $0xa,%ecx\nje 14b0 \nmovdqa 0xa0(%rsp),%xmm0\nmovdqu -0xa0(%rax),%xmm5\npshufd $0x1b,%xmm0,%xmm0\npshufd $0x1b,%xmm5,%xmm1\nmovaps %xmm1,0xa0(%rsp)\nmovups %xmm0,-0xa0(%rax)\ncmp $0xc,%ecx\njne 14b0 \nmovdqa 0xb0(%rsp),%xmm0\nmovdqu -0xb0(%rax),%xmm6\npshufd $0x1b,%xmm0,%xmm0\npshufd $0x1b,%xmm6,%xmm1\nmovaps %xmm1,0xb0(%rsp)\nmovups %xmm0,-0xb0(%rax)\nmov %edx,%eax\nmov %r9d,%ecx\nand $0xfffffffc,%eax\nsub %eax,%ecx\ncmp %eax,%edx\nje 1513 \nmovslq %eax,%r8\nmovslq %ecx,%rdx\nmov (%rsp,%r8,4),%r10d\nmov (%rsp,%rdx,4),%r11d\nmov %r11d,(%rsp,%r8,4)\nlea 0x1(%rax),%r8d\nmov %r10d,(%rsp,%rdx,4)\nlea -0x1(%rcx),%edx\ncmp %edx,%r8d\njge 1513 \nmovslq %r8d,%r8\nmovslq %edx,%rdx\nadd $0x2,%eax\nsub $0x2,%ecx\nmov (%rsp,%r8,4),%r10d\nmov (%rsp,%rdx,4),%r11d\nmov %r11d,(%rsp,%r8,4)\nmov %r10d,(%rsp,%rdx,4)\ncmp %ecx,%eax\njge 1513 \ncltq\nmovslq %ecx,%rcx\nmov (%rsp,%rax,4),%edx\nmov (%rsp,%rcx,4),%r8d\nmov %r8d,(%rsp,%rax,4)\nmov %edx,(%rsp,%rcx,4)\nmovslq %esi,%rax\nmov %esi,%ebp\nmov %esi,%edx\nlea -0x10(%rbx,%rax,4),%r8\nmov %esi,%ebx\nlea 0x1(%rdx),%r11d\nand $0xfffffffc,%ebp\nshr $0x2,%ebx\nlea 0x1(%rbp),%r12d\nshl $0x4,%rbx\ncmp $0x3,%r9d\njbe 15f0 \nnopl (%rax)\nmov %r8,%rcx\nmov %r8,%rax\npxor %xmm1,%xmm1\nsub %rbx,%rcx\nnopl (%rax)\nmovdqu (%rax),%xmm2\nsub $0x10,%rax\npshufd $0x1b,%xmm2,%xmm0\npaddd %xmm0,%xmm1\ncmp %rax,%rcx\njne 1550 \nmovdqa %xmm1,%xmm0\nmov %r12d,%ecx\npsrldq $0x8,%xmm0\npaddd %xmm0,%xmm1\nmovdqa %xmm1,%xmm0\npsrldq $0x4,%xmm0\npaddd %xmm0,%xmm1\nmovd %xmm1,%eax\ncmp %esi,%ebp\nje 15d3 \nmov %edx,%r10d\nsub %ecx,%r10d\nmovslq %r10d,%r10\nadd (%rsp,%r10,4),%eax\nlea 0x1(%rcx),%r10d\ncmp %r9d,%ecx\njg 15d3 \nmov %edx,%r14d\nsub %r10d,%r14d\nmovslq %r14d,%r10\nadd (%rsp,%r10,4),%eax\nlea 0x2(%rcx),%r10d\ncmp %esi,%r10d\njg 15d3 \nmov %edx,%r14d\nadd $0x3,%ecx\nsub %r10d,%r14d\nmovslq %r14d,%r10\nadd (%rsp,%r10,4),%eax\ncmp %esi,%ecx\njg 15d3 \nsub %ecx,%edx\nmovslq %edx,%rdx\nadd (%rsp,%rdx,4),%eax\nmov %eax,0x10(%r8)\ncmp %edi,%eax\njge 1600 \nmov %r11d,%edx\nadd $0x4,%r8\nlea 0x1(%rdx),%r11d\ncmp $0x3,%r9d\nja 1540 \nmov $0x1,%ecx\nxor %eax,%eax\njmp 158b \nxor %eax,%eax\nnopl 0x0(%rax,%rax,1)\ncmp %eax,%edi\nsete %al\nmov 0x198(%rsp),%rdi\nxor %fs:0x28,%rdi\njne 1656 \nadd $0x1a8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r14\nretq\nlea -0x4(%rbx,%r8,1),%rdx\nmov %r9d,%eax\nxchg %ax,%ax\nmov (%r11),%ecx\nmov (%rdx),%r8d\nsub $0x1,%eax\nadd $0x4,%r11\nsub $0x4,%rdx\nmov %r8d,-0x4(%r11)\nmov %ecx,0x4(%rdx)\nmov %r9d,%ecx\nsub %eax,%ecx\ncmp %ecx,%eax\njg 1630 \njmpq 1513 \ncallq 1060 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov r8d, edi\npush rbx\nsub rsp, 1A8h\nmov rax, fs:28h\nmov [rsp+1B8h+var_20], rax\nxor eax, eax\ntest edi, edi\njle loc_13AE\nmov r11, rsp\nmov esi, edi\nxor edx, edx\nmov ebp, 0CCCCCCCDh\nmov rcx, r11\nmov r10, r11\nnop dword ptr [rax]\nloc_1250:\nmov eax, esi\nmov ebx, esi\nmov edi, edx\nadd r10, 4\nimul rax, rbp\nadd edx, 1\nshr rax, 23h\nlea r9d, [rax+rax*4]\nadd r9d, r9d\nsub ebx, r9d\nmov r9d, esi\nmov esi, eax\nmov [r10-4], ebx\ncmp r9d, 9\njg short loc_1250\ntest edi, edi\njz short loc_12B4\nmovsxd rax, edi\nlea rsi, [r11+rax*4]\nmov eax, edi\nnop dword ptr [rax+rax+00h]\nloc_1290:\nmov r9d, [rcx]\nmov r10d, [rsi]\nsub eax, 1\nadd rcx, 4\nsub rsi, 4\nmov [rcx-4], r10d\nmov [rsi+4], r9d\nmov r9d, edi\nsub r9d, eax\ncmp eax, r9d\njg short loc_1290\nloc_12B4:\nlea r10d, [rdi+1]\nmovsxd rax, edx\nmov ebx, r10d\nlea rsi, [r11+rax*4-10h]\nmov r11d, r10d\nand r10d, 3\nshr r11d, 2\nand ebx, 0FFFFFFFCh\nshl r11, 4\nadd ebx, 1\nnop dword ptr [rax+rax+00000000h]\nloc_12E0:\ncmp edi, 2\njle loc_13A5\nmov rcx, rsi\nmov rax, rsi\npxor xmm1, xmm1\nsub rcx, r11\nnop word ptr [rax+rax+00000000h]\nloc_1300:\nmovdqu xmm2, xmmword ptr [rax]\nsub rax, 10h\npshufd xmm0, xmm2, 1Bh\npaddd xmm1, xmm0\ncmp rcx, rax\njnz short loc_1300\nmovdqa xmm0, xmm1\nmov ecx, ebx\npsrldq xmm0, 8\npaddd xmm1, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm0, 4\npaddd xmm1, xmm0\nmovd eax, xmm1\ntest r10d, r10d\njz short loc_136F\nloc_133B:\nmov r9d, edx\nlea ebp, [rcx+1]\nsub r9d, ecx\nmovsxd r9, r9d\nadd eax, [rsp+r9*4+1B8h+var_1B8]\ncmp ecx, edi\njg short loc_136F\nmov r9d, edx\nadd ecx, 2\nsub r9d, ebp\nmovsxd r9, r9d\nadd eax, [rsp+r9*4+1B8h+var_1B8]\ncmp ebp, edi\njg short loc_136F\nmov r9d, edx\nsub r9d, ecx\nmovsxd rcx, r9d\nadd eax, [rsp+rcx*4+1B8h+var_1B8]\nloc_136F:\nmov [rsi+10h], eax\nadd edx, 1\nadd rsi, 4\ncmp r8d, eax\njg loc_12E0\nloc_1382:\ncmp r8d, eax\nsetz al\nmov rdx, [rsp+1B8h+var_20]\nsub rdx, fs:28h\njnz short loc_13B2\nadd rsp, 1A8h\npop rbx\npop rbp\nretn\nloc_13A5:\nmov ecx, 1\nxor eax, eax\njmp short loc_133B\nloc_13AE:\nxor eax, eax\njmp short loc_1382\nloc_13B2:\ncall ___stack_chk_fail", + "ida_pseudo": "bool __fastcall func0(int a1)\n{\n unsigned int v2; // esi\n int v3; // edx\n int *v4; // rcx\n _DWORD *v5; // r10\n int v6; // edi\n unsigned int v7; // ebx\n int v8; // r9d\n int *v9; // rsi\n int v10; // eax\n int v11; // r9d\n int v12; // r10d\n const __m128i *v13; // rsi\n const __m128i *v14; // rax\n __m128i v15; // xmm1\n __m128i v16; // xmm2\n signed int v17; // ecx\n __m128i v18; // xmm1\n int v19; // eax\n int v20; // ebp\n int v21; // ecx\n _DWORD v23[102]; // [rsp+0h] [rbp-1B8h] BYREF\n unsigned __int64 v24; // [rsp+198h] [rbp-20h]\n\n v24 = __readfsqword(0x28u);\n if ( a1 > 0 )\n {\n v2 = a1;\n v3 = 0;\n v4 = v23;\n v5 = v23;\n do\n {\n v6 = v3;\n ++v5;\n ++v3;\n v7 = v2 % 0xA;\n v8 = v2;\n v2 /= 0xAu;\n *(v5 - 1) = v7;\n }\n while ( v8 > 9 );\n if ( v6 )\n {\n v9 = &v23[v6];\n v10 = v6;\n do\n {\n v11 = *v4;\n v12 = *v9;\n --v10;\n ++v4;\n --v9;\n *(v4 - 1) = v12;\n v9[1] = v11;\n }\n while ( v10 > v6 - v10 );\n }\n v13 = (const __m128i *)&v23[v3 - 4];\n while ( v6 > 2 )\n {\n v14 = v13;\n v15 = 0LL;\n do\n {\n v16 = _mm_loadu_si128(v14--);\n v15 = _mm_add_epi32(v15, _mm_shuffle_epi32(v16, 27));\n }\n while ( &v13[-((unsigned int)(v6 + 1) >> 2)] != v14 );\n v17 = ((v6 + 1) & 0xFFFFFFFC) + 1;\n v18 = _mm_add_epi32(v15, _mm_srli_si128(v15, 8));\n v19 = _mm_cvtsi128_si32(_mm_add_epi32(v18, _mm_srli_si128(v18, 4)));\n if ( ((v6 + 1) & 3) != 0 )\n goto LABEL_12;\nLABEL_15:\n v13[1].m128i_i32[0] = v19;\n ++v3;\n v13 = (const __m128i *)((char *)v13 + 4);\n if ( a1 <= v19 )\n return a1 == v19;\n }\n v17 = 1;\n v19 = 0;\nLABEL_12:\n v20 = v17 + 1;\n v19 += v23[v3 - v17];\n if ( v17 <= v6 )\n {\n v21 = v17 + 2;\n v19 += v23[v3 - v20];\n if ( v20 <= v6 )\n v19 += v23[v3 - v21];\n }\n goto LABEL_15;\n }\n v19 = 0;\n return a1 == v19;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbp\nmov r8d, edi\npush rbx\nsub rsp, 1A8h\nmov rax, fs:28h\nmov [rsp+1B8h+var_20], rax\nxor eax, eax\ntest edi, edi\njle loc_13AE\nmov r11, rsp\nmov esi, edi\nxor edx, edx\nmov ebp, 0CCCCCCCDh\nmov rcx, r11\nmov r10, r11\nnop dword ptr [rax]\nloc_1250:\nmov eax, esi\nmov ebx, esi\nmov edi, edx\nadd r10, 4\nimul rax, rbp\nadd edx, 1\nshr rax, 23h\nlea r9d, [rax+rax*4]\nadd r9d, r9d\nsub ebx, r9d\nmov r9d, esi\nmov esi, eax\nmov [r10-4], ebx\ncmp r9d, 9\njg short loc_1250\ntest edi, edi\njz short loc_12B4\nmovsxd rax, edi\nlea rsi, [r11+rax*4]\nmov eax, edi\nnop dword ptr [rax+rax+00h]\nloc_1290:\nmov r9d, [rcx]\nmov r10d, [rsi]\nsub eax, 1\nadd rcx, 4\nsub rsi, 4\nmov [rcx-4], r10d\nmov [rsi+4], r9d\nmov r9d, edi\nsub r9d, eax\ncmp eax, r9d\njg short loc_1290\nloc_12B4:\nlea r10d, [rdi+1]\nmovsxd rax, edx\nmov ebx, r10d\nlea rsi, [r11+rax*4-10h]\nmov r11d, r10d\nand r10d, 3\nshr r11d, 2\nand ebx, 0FFFFFFFCh\nshl r11, 4\nadd ebx, 1\nnop dword ptr [rax+rax+00000000h]\nloc_12E0:\ncmp edi, 2\njle loc_13A5\nmov rcx, rsi\nmov rax, rsi\npxor xmm1, xmm1\nsub rcx, r11\nnop word ptr [rax+rax+00000000h]\nloc_1300:\nmovdqu xmm2, xmmword ptr [rax]\nsub rax, 10h\npshufd xmm0, xmm2, 1Bh\npaddd xmm1, xmm0\ncmp rcx, rax\njnz short loc_1300\nmovdqa xmm0, xmm1\nmov ecx, ebx\npsrldq xmm0, 8\npaddd xmm1, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm0, 4\npaddd xmm1, xmm0\nmovd eax, xmm1\ntest r10d, r10d\njz short loc_136F\nloc_133B:\nmov r9d, edx\nlea ebp, [rcx+1]\nsub r9d, ecx\nmovsxd r9, r9d\nadd eax, [rsp+r9*4+1B8h+var_1B8]\ncmp ecx, edi\njg short loc_136F\nmov r9d, edx\nadd ecx, 2\nsub r9d, ebp\nmovsxd r9, r9d\nadd eax, [rsp+r9*4+1B8h+var_1B8]\ncmp ebp, edi\njg short loc_136F\nmov r9d, edx\nsub r9d, ecx\nmovsxd rcx, r9d\nadd eax, [rsp+rcx*4+1B8h+var_1B8]\nloc_136F:\nmov [rsi+10h], eax\nadd edx, 1\nadd rsi, 4\ncmp r8d, eax\njg loc_12E0\nloc_1382:\ncmp r8d, eax\nsetz al\nmov rdx, [rsp+1B8h+var_20]\nsub rdx, fs:28h\njnz short loc_13B2\nadd rsp, 1A8h\npop rbx\npop rbp\nretn\nloc_13A5:\nmov ecx, 1\nxor eax, eax\njmp short loc_133B\nloc_13AE:\nxor eax, eax\njmp short loc_1382\nloc_13B2:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "bool __fastcall sub_1210(int a1)\n{\n unsigned int v2; // esi\n int v3; // edx\n int *v4; // rcx\n _DWORD *v5; // r10\n int v6; // edi\n unsigned int v7; // ebx\n int v8; // r9d\n int *v9; // rsi\n int v10; // eax\n int v11; // r9d\n int v12; // r10d\n const __m128i *v13; // rsi\n const __m128i *v14; // rax\n __m128i v15; // xmm1\n __m128i v16; // xmm2\n signed int v17; // ecx\n __m128i v18; // xmm1\n int v19; // eax\n int v20; // ebp\n int v21; // ecx\n _DWORD v23[102]; // [rsp+0h] [rbp-1B8h] BYREF\n unsigned __int64 v24; // [rsp+198h] [rbp-20h]\n\n v24 = __readfsqword(0x28u);\n if ( a1 > 0 )\n {\n v2 = a1;\n v3 = 0;\n v4 = v23;\n v5 = v23;\n do\n {\n v6 = v3;\n ++v5;\n ++v3;\n v7 = v2 % 0xA;\n v8 = v2;\n v2 /= 0xAu;\n *(v5 - 1) = v7;\n }\n while ( v8 > 9 );\n if ( v6 )\n {\n v9 = &v23[v6];\n v10 = v6;\n do\n {\n v11 = *v4;\n v12 = *v9;\n --v10;\n ++v4;\n --v9;\n *(v4 - 1) = v12;\n v9[1] = v11;\n }\n while ( v10 > v6 - v10 );\n }\n v13 = (const __m128i *)&v23[v3 - 4];\n while ( v6 > 2 )\n {\n v14 = v13;\n v15 = 0LL;\n do\n {\n v16 = _mm_loadu_si128(v14--);\n v15 = _mm_add_epi32(v15, _mm_shuffle_epi32(v16, 27));\n }\n while ( &v13[-((unsigned int)(v6 + 1) >> 2)] != v14 );\n v17 = ((v6 + 1) & 0xFFFFFFFC) + 1;\n v18 = _mm_add_epi32(v15, _mm_srli_si128(v15, 8));\n v19 = _mm_cvtsi128_si32(_mm_add_epi32(v18, _mm_srli_si128(v18, 4)));\n if ( ((v6 + 1) & 3) != 0 )\n goto LABEL_12;\nLABEL_15:\n v13[1].m128i_i32[0] = v19;\n ++v3;\n v13 = (const __m128i *)((char *)v13 + 4);\n if ( a1 <= v19 )\n return a1 == v19;\n }\n v17 = 1;\n v19 = 0;\nLABEL_12:\n v20 = v17 + 1;\n v19 += v23[v3 - v17];\n if ( v17 <= v6 )\n {\n v21 = v17 + 2;\n v19 += v23[v3 - v20];\n if ( v20 <= v6 )\n v19 += v23[v3 - v21];\n }\n goto LABEL_15;\n }\n v19 = 0;\n return a1 == v19;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_1210(int a1) {\n unsigned int v2;\n int v3;\n int *v4;\n uint32_t *v5;\n int v6;\n unsigned int v7;\n int v8;\n int *v9;\n int v10;\n int v11;\n int v12;\n const __m128i *v13;\n const __m128i *v14;\n __m128i v15;\n __m128i v16;\n signed int v17;\n __m128i v18;\n int v19;\n int v20;\n int v21;\n uint32_t v23[102];\n unsigned long long v24;\n v24 = __readfsqword(40u);\n if (a1 > 0) {\n v2 = a1;\n v3 = 0;\n v4 = v23;\n v5 = v23;\n do {\n v6 = v3;\n ++v5;\n ++v3;\n v7 = v2 % 10;\n v8 = v2;\n v2 /= 10u;\n *(v5 - 1) = v7;\n } while (v8 > 9);\n if (v6) {\n v9 = &v23[v6];\n v10 = v6;\n do {\n v11 = *v4;\n v12 = *v9;\n --v10;\n ++v4;\n --v9;\n *(v4 - 1) = v12;\n v9[1] = v11;\n } while (v10 > v6 - v10);\n }\n v13 = (const __m128i *)&v23[v3 - 4];\n while (v6 > 2) {\n v14 = v13;\n v15 = 0LL;\n do {\n v16 = _mm_loadu_si128(v14--);\n v15 = _mm_add_epi32(v15, _mm_shuffle_epi32(v16, 27));\n } while (&v13[-((unsigned int)(v6 + 1) >> 2)] != v14);\n v17 = ((v6 + 1) & 4294967292) + 1;\n v18 = _mm_add_epi32(v15, _mm_srli_si128(v15, 8));\n v19 = _mm_cvtsi128_si32(_mm_add_epi32(v18, _mm_srli_si128(v18, 4)));\n if (((v6 + 1) & 3) != 0) goto LABEL_12;\n LABEL_15:\n v13[1].m128i_i32[0] = v19;\n ++v3;\n v13 = (const __m128i *)((char *)v13 + 4);\n if (a1 <= v19) return a1 == v19;\n }\n v17 = 1;\n v19 = 0;\n LABEL_12:\n v20 = v17 + 1;\n v19 += v23[v3 - v17];\n if (v17 <= v6) {\n v21 = v17 + 2;\n v19 += v23[v3 - v20];\n if (v20 <= v6) v19 += v23[v3 - v21];\n }\n goto LABEL_15;\n }\n v19 = 0;\n return a1 == v19;\n}", + "ida_pseudo_norm": "bool func0(int a1) {\n unsigned int v2;\n int v3;\n int *v4;\n uint32_t *v5;\n int v6;\n unsigned int v7;\n int v8;\n int *v9;\n int v10;\n int v11;\n int v12;\n const __m128i *v13;\n const __m128i *v14;\n __m128i v15;\n __m128i v16;\n signed int v17;\n __m128i v18;\n int v19;\n int v20;\n int v21;\n uint32_t v23[102];\n unsigned long long v24;\n v24 = __readfsqword(40u);\n if (a1 > 0) {\n v2 = a1;\n v3 = 0;\n v4 = v23;\n v5 = v23;\n do {\n v6 = v3;\n ++v5;\n ++v3;\n v7 = v2 % 10;\n v8 = v2;\n v2 /= 10u;\n *(v5 - 1) = v7;\n } while (v8 > 9);\n if (v6) {\n v9 = &v23[v6];\n v10 = v6;\n do {\n v11 = *v4;\n v12 = *v9;\n --v10;\n ++v4;\n --v9;\n *(v4 - 1) = v12;\n v9[1] = v11;\n } while (v10 > v6 - v10);\n }\n v13 = (const __m128i *)&v23[v3 - 4];\n while (v6 > 2) {\n v14 = v13;\n v15 = 0LL;\n do {\n v16 = _mm_loadu_si128(v14--);\n v15 = _mm_add_epi32(v15, _mm_shuffle_epi32(v16, 27));\n } while (&v13[-((unsigned int)(v6 + 1) >> 2)] != v14);\n v17 = ((v6 + 1) & 4294967292) + 1;\n v18 = _mm_add_epi32(v15, _mm_srli_si128(v15, 8));\n v19 = _mm_cvtsi128_si32(_mm_add_epi32(v18, _mm_srli_si128(v18, 4)));\n if (((v6 + 1) & 3) != 0) goto LABEL_12;\n LABEL_15:\n v13[1].m128i_i32[0] = v19;\n ++v3;\n v13 = (const __m128i *)((char *)v13 + 4);\n if (a1 <= v19) return a1 == v19;\n }\n v17 = 1;\n v19 = 0;\n LABEL_12:\n v20 = v17 + 1;\n v19 += v23[v3 - v17];\n if (v17 <= v6) {\n v21 = v17 + 2;\n v19 += v23[v3 - v20];\n if (v20 <= v6) v19 += v23[v3 - v21];\n }\n goto LABEL_15;\n }\n v19 = 0;\n return a1 == v19;\n}" + }, + { + "index": 180, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(double slat, double slon, double elat, double elon) {\n double dist = 6371.01 * acos(sin(slat) * sin(elat) +\n cos(slat) * cos(elat) * cos(slon - elon));\n return dist;\n}", + "test": "int main() {\n\n assert(func0(23.5, 67.5, 25.5, 69.5) == 12179.372041317429);\n\n assert(func0(10.5, 20.5, 30.5, 40.5) == 6069.397933300514);\n\n assert(func0(10, 20, 30, 40) == 6783.751974994595);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x40,%rsp\nmovsd %xmm0,-0x18(%rbp)\nmovsd %xmm1,-0x20(%rbp)\nmovsd %xmm2,-0x28(%rbp)\nmovsd %xmm3,-0x30(%rbp)\nmov -0x18(%rbp),%rax\nmovq %rax,%xmm0\ncallq 10b0 \nmovsd %xmm0,-0x38(%rbp)\nmov -0x28(%rbp),%rax\nmovq %rax,%xmm0\ncallq 10b0 \nmovapd %xmm0,%xmm4\nmulsd -0x38(%rbp),%xmm4\nmovsd %xmm4,-0x38(%rbp)\nmov -0x18(%rbp),%rax\nmovq %rax,%xmm0\ncallq 1090 \nmovsd %xmm0,-0x40(%rbp)\nmov -0x28(%rbp),%rax\nmovq %rax,%xmm0\ncallq 1090 \nmovapd %xmm0,%xmm5\nmulsd -0x40(%rbp),%xmm5\nmovsd %xmm5,-0x40(%rbp)\nmovsd -0x20(%rbp),%xmm0\nsubsd -0x30(%rbp),%xmm0\ncallq 1090 \nmulsd -0x40(%rbp),%xmm0\naddsd -0x38(%rbp),%xmm0\ncallq 10a0 \nmovsd 0xe9b(%rip),%xmm1\nmulsd %xmm1,%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmovsd -0x8(%rbp),%xmm0\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmovsd [rbp+x], xmm0\nmovsd [rbp+var_20], xmm1\nmovsd [rbp+var_28], xmm2\nmovsd [rbp+var_30], xmm3\nmov rax, [rbp+x]\nmovq xmm0, rax; x\ncall _sin\nmovsd [rbp+var_38], xmm0\nmov rax, [rbp+var_28]\nmovq xmm0, rax; x\ncall _sin\nmovapd xmm4, xmm0\nmulsd xmm4, [rbp+var_38]\nmovsd [rbp+var_38], xmm4\nmov rax, [rbp+x]\nmovq xmm0, rax; x\ncall _cos\nmovsd [rbp+var_40], xmm0\nmov rax, [rbp+var_28]\nmovq xmm0, rax; x\ncall _cos\nmovapd xmm5, xmm0\nmulsd xmm5, [rbp+var_40]\nmovsd [rbp+var_40], xmm5\nmovsd xmm0, [rbp+var_20]\nsubsd xmm0, [rbp+var_30]\nmovq rax, xmm0\nmovq xmm0, rax; x\ncall _cos\nmulsd xmm0, [rbp+var_40]\naddsd xmm0, [rbp+var_38]\nmovq rax, xmm0\nmovq xmm0, rax; x\ncall _acos\nmovsd xmm1, cs:qword_20C8\nmulsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "double __fastcall func0(double a1, double a2, double a3, double a4)\n{\n double v4; // xmm0_8\n double v6; // [rsp+0h] [rbp-40h]\n double v7; // [rsp+0h] [rbp-40h]\n double v8; // [rsp+8h] [rbp-38h]\n double v9; // [rsp+8h] [rbp-38h]\n\n v8 = sin(a1);\n v9 = sin(a3) * v8;\n v6 = cos(a1);\n v7 = cos(a3) * v6;\n v4 = cos(a2 - a4);\n return acos(v4 * v7 + v9) * 6371.01;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmovsd [rbp+x], xmm0\nmovsd [rbp+var_20], xmm1\nmovsd [rbp+var_28], xmm2\nmovsd [rbp+var_30], xmm3\nmov rax, [rbp+x]\nmovq xmm0, rax; x\ncall _sin\nmovsd [rbp+var_38], xmm0\nmov rax, [rbp+var_28]\nmovq xmm0, rax; x\ncall _sin\nmovapd xmm4, xmm0\nmulsd xmm4, [rbp+var_38]\nmovsd [rbp+var_38], xmm4\nmov rax, [rbp+x]\nmovq xmm0, rax; x\ncall _cos\nmovsd [rbp+var_40], xmm0\nmov rax, [rbp+var_28]\nmovq xmm0, rax; x\ncall _cos\nmovapd xmm5, xmm0\nmulsd xmm5, [rbp+var_40]\nmovsd [rbp+var_40], xmm5\nmovsd xmm0, [rbp+var_20]\nsubsd xmm0, [rbp+var_30]\nmovq rax, xmm0\nmovq xmm0, rax; x\ncall _cos\nmulsd xmm0, [rbp+var_40]\naddsd xmm0, [rbp+var_38]\nmovq rax, xmm0\nmovq xmm0, rax; x\ncall _acos\nmovsd xmm1, cs:qword_20C8\nmulsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "double __fastcall sub_11A9(double a1, double a2, double a3, double a4)\n{\n double v4; // xmm0_8\n double v6; // [rsp+0h] [rbp-40h]\n double v7; // [rsp+0h] [rbp-40h]\n double v8; // [rsp+8h] [rbp-38h]\n double v9; // [rsp+8h] [rbp-38h]\n\n v8 = sin(a1);\n v9 = sin(a3) * v8;\n v6 = cos(a1);\n v7 = cos(a3) * v6;\n v4 = cos(a2 - a4);\n return acos(v4 * v7 + v9) * 6371.01;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_11A9(double a1, double a2, double a3, double a4) {\n double v4;\n double v6;\n double v7;\n double v8;\n double v9;\n v8 = sin(a1);\n v9 = sin(a3) * v8;\n v6 = cos(a1);\n v7 = cos(a3) * v6;\n v4 = cos(a2 - a4);\n return acos(v4 * v7 + v9) * 6371.01;\n}", + "ida_pseudo_norm": "double func0(double a1, double a2, double a3, double a4) {\n double v4;\n double v6;\n double v7;\n double v8;\n double v9;\n v8 = sin(a1);\n v9 = sin(a3) * v8;\n v6 = cos(a1);\n v7 = cos(a3) * v6;\n v4 = cos(a2 - a4);\n return acos(v4 * v7 + v9) * 6371.01;\n}" + }, + { + "index": 180, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(double slat, double slon, double elat, double elon) {\n double dist = 6371.01 * acos(sin(slat) * sin(elat) +\n cos(slat) * cos(elat) * cos(slon - elon));\n return dist;\n}", + "test": "int main() {\n\n assert(func0(23.5, 67.5, 25.5, 69.5) == 12179.372041317429);\n\n assert(func0(10.5, 20.5, 30.5, 40.5) == 6069.397933300514);\n\n assert(func0(10, 20, 30, 40) == 6783.751974994595);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x38,%rsp\nmovsd %xmm0,0x8(%rsp)\nmovsd %xmm1,0x10(%rsp)\nmovapd %xmm2,%xmm0\nmovsd %xmm3,0x18(%rsp)\nlea 0x28(%rsp),%r12\nlea 0x20(%rsp),%r13\nmov %r13,%rsi\nmov %r12,%rdi\ncallq 1090 \nmov 0x20(%rsp),%rbx\nmov 0x28(%rsp),%rbp\nmov %r13,%rsi\nmov %r12,%rdi\nmovsd 0x8(%rsp),%xmm0\ncallq 1090 \nmovsd 0x10(%rsp),%xmm0\nsubsd 0x18(%rsp),%xmm0\ncallq 10a0 \nmovapd %xmm0,%xmm1\nmovq %rbx,%xmm0\nmulsd 0x20(%rsp),%xmm0\nmulsd %xmm1,%xmm0\nmovq %rbp,%xmm1\nmulsd 0x28(%rsp),%xmm1\naddsd %xmm1,%xmm0\ncallq 10b0 \nmulsd 0xeab(%rip),%xmm0\nadd $0x38,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 38h\nmovsd [rsp+58h+x], xmm0\nmovsd [rsp+58h+var_48], xmm1\nmovapd xmm0, xmm2; x\nmovsd [rsp+58h+var_40], xmm3\nlea r12, [rsp+58h+sinx]\nlea r13, [rsp+58h+cosx]\nmov rsi, r13; cosx\nmov rdi, r12; sinx\ncall _sincos\nmov rbx, [rsp+58h+cosx]\nmov rbp, [rsp+58h+sinx]\nmov rsi, r13; cosx\nmov rdi, r12; sinx\nmovsd xmm0, [rsp+58h+x]; x\ncall _sincos\nmovsd xmm0, [rsp+58h+var_48]\nsubsd xmm0, [rsp+58h+var_40]; x\ncall _cos\nmovapd xmm1, xmm0\nmovq xmm0, rbx\nmulsd xmm0, [rsp+58h+cosx]\nmulsd xmm0, xmm1\nmovq xmm1, rbp\nmulsd xmm1, [rsp+58h+sinx]\naddsd xmm0, xmm1; x\ncall _acos\nmulsd xmm0, cs:qword_20D0\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "double __fastcall func0(double a1, double a2, double a3, double a4)\n{\n double v4; // rbx\n double v5; // rbp\n double v6; // xmm1_8\n double cosx; // [rsp+20h] [rbp-38h] BYREF\n double sinx[6]; // [rsp+28h] [rbp-30h] BYREF\n\n sincos(a3, sinx, &cosx);\n v4 = cosx;\n v5 = sinx[0];\n sincos(a1, sinx, &cosx);\n v6 = cos(a2 - a4);\n return acos(v4 * cosx * v6 + v5 * sinx[0]) * 6371.01;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 38h\nmovsd [rsp+58h+x], xmm0\nmovsd [rsp+58h+var_48], xmm1\nmovapd xmm0, xmm2; x\nmovsd [rsp+58h+var_40], xmm3\nlea r12, [rsp+58h+sinx]\nlea r13, [rsp+58h+cosx]\nmov rsi, r13; cosx\nmov rdi, r12; sinx\ncall _sincos\nmov rbx, [rsp+58h+cosx]\nmov rbp, [rsp+58h+sinx]\nmov rsi, r13; cosx\nmov rdi, r12; sinx\nmovsd xmm0, [rsp+58h+x]; x\ncall _sincos\nmovsd xmm0, [rsp+58h+var_48]\nsubsd xmm0, [rsp+58h+var_40]; x\ncall _cos\nmovapd xmm1, xmm0\nmovq xmm0, rbx\nmulsd xmm0, [rsp+58h+cosx]\nmulsd xmm0, xmm1\nmovq xmm1, rbp\nmulsd xmm1, [rsp+58h+sinx]\naddsd xmm0, xmm1; x\ncall _acos\nmulsd xmm0, cs:qword_20D0\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "double __fastcall sub_11A9(double a1, double a2, double a3, double a4)\n{\n double v4; // rbx\n double v5; // rbp\n double v6; // xmm1_8\n double cosx; // [rsp+20h] [rbp-38h] BYREF\n double sinx[6]; // [rsp+28h] [rbp-30h] BYREF\n\n sincos(a3, sinx, &cosx);\n v4 = cosx;\n v5 = sinx[0];\n sincos(a1, sinx, &cosx);\n v6 = cos(a2 - a4);\n return acos(v4 * cosx * v6 + v5 * sinx[0]) * 6371.01;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_11A9(double a1, double a2, double a3, double a4) {\n double v4;\n double v5;\n double v6;\n double cosx;\n double sinx[6];\n sincos(a3, sinx, &cosx);\n v4 = cosx;\n v5 = sinx[0];\n sincos(a1, sinx, &cosx);\n v6 = cos(a2 - a4);\n return acos(v4 * cosx * v6 + v5 * sinx[0]) * 6371.01;\n}", + "ida_pseudo_norm": "double func0(double a1, double a2, double a3, double a4) {\n double v4;\n double v5;\n double v6;\n double cosx;\n double sinx[6];\n sincos(a3, sinx, &cosx);\n v4 = cosx;\n v5 = sinx[0];\n sincos(a1, sinx, &cosx);\n v6 = cos(a2 - a4);\n return acos(v4 * cosx * v6 + v5 * sinx[0]) * 6371.01;\n}" + }, + { + "index": 180, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(double slat, double slon, double elat, double elon) {\n double dist = 6371.01 * acos(sin(slat) * sin(elat) +\n cos(slat) * cos(elat) * cos(slon - elon));\n return dist;\n}", + "test": "int main() {\n\n assert(func0(23.5, 67.5, 25.5, 69.5) == 12179.372041317429);\n\n assert(func0(10.5, 20.5, 30.5, 40.5) == 6069.397933300514);\n\n assert(func0(10, 20, 30, 40) == 6783.751974994595);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\nsub $0x48,%rsp\nlea 0x38(%rsp),%rbp\nlea 0x30(%rsp),%r12\nmovsd %xmm0,0x28(%rsp)\nmovapd %xmm2,%xmm0\nmov %r12,%rsi\nmov %rbp,%rdi\nmovsd %xmm1,0x20(%rsp)\nmovsd %xmm3,0x8(%rsp)\ncallq 1090 \nmovsd 0x28(%rsp),%xmm4\nmov %r12,%rsi\nmov %rbp,%rdi\nmovsd 0x30(%rsp),%xmm2\nmovsd 0x38(%rsp),%xmm3\nmovapd %xmm4,%xmm0\nmovsd %xmm2,0x18(%rsp)\nmovsd %xmm3,0x10(%rsp)\ncallq 1090 \nmovsd 0x20(%rsp),%xmm1\nsubsd 0x8(%rsp),%xmm1\nmovapd %xmm1,%xmm0\ncallq 10a0 \nmovsd 0x18(%rsp),%xmm2\nmulsd 0x30(%rsp),%xmm2\nmovsd 0x10(%rsp),%xmm3\nmulsd 0x38(%rsp),%xmm3\nmulsd %xmm0,%xmm2\nmovapd %xmm3,%xmm0\naddsd %xmm2,%xmm0\ncallq 10b0 \nmulsd 0xd8f(%rip),%xmm0\nadd $0x48,%rsp\npop %rbp\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\nmovq r14, xmm0\nmovapd xmm0, xmm2; x\npush rbp\npush rbx\nsub rsp, 30h\nlea rbx, [rsp+48h+sinx]\nlea rbp, [rsp+48h+cosx]\nmovsd [rsp+48h+var_30], xmm1\nmov rsi, rbp; cosx\nmov rdi, rbx; sinx\nmovsd [rsp+48h+var_48], xmm3\ncall _sincos\nmov rsi, rbp; cosx\nmov rdi, rbx; sinx\nmovq xmm0, r14; x\nmovsd xmm2, [rsp+48h+cosx]\nmovsd xmm3, [rsp+48h+sinx]\nmovsd [rsp+48h+var_38], xmm2\nmovsd [rsp+48h+var_40], xmm3\ncall _sincos\nmovsd xmm1, [rsp+48h+var_30]\nsubsd xmm1, [rsp+48h+var_48]\nmovapd xmm0, xmm1; x\ncall _cos\nmovsd xmm2, [rsp+48h+var_38]\nmulsd xmm2, [rsp+48h+cosx]\nmovapd xmm1, xmm0\nmovsd xmm3, [rsp+48h+var_40]\nmulsd xmm3, [rsp+48h+sinx]\nmovapd xmm0, xmm2\nmulsd xmm0, xmm1\naddsd xmm0, xmm3; x\ncall _acos\nmulsd xmm0, cs:qword_20D0\nadd rsp, 30h\npop rbx\npop rbp\npop r14\nretn", + "ida_pseudo": "double __fastcall func0(double a1, double a2, double a3, double a4)\n{\n double v4; // xmm0_8\n double v6; // [rsp+8h] [rbp-40h]\n double v7; // [rsp+10h] [rbp-38h]\n double cosx; // [rsp+20h] [rbp-28h] BYREF\n double sinx[4]; // [rsp+28h] [rbp-20h] BYREF\n\n sincos(a3, sinx, &cosx);\n v7 = cosx;\n v6 = sinx[0];\n sincos(a1, sinx, &cosx);\n v4 = cos(a2 - a4);\n return acos(v7 * cosx * v4 + v6 * sinx[0]) * 6371.01;\n}", + "ida_strip_asm": "sub_12B0:\nendbr64\npush r14\nmovq r14, xmm0\nmovapd xmm0, xmm2; x\npush rbp\npush rbx\nsub rsp, 30h\nlea rbx, [rsp+48h+sinx]\nlea rbp, [rsp+48h+cosx]\nmovsd [rsp+48h+var_30], xmm1\nmov rsi, rbp; cosx\nmov rdi, rbx; sinx\nmovsd [rsp+48h+var_48], xmm3\ncall _sincos\nmov rsi, rbp; cosx\nmov rdi, rbx; sinx\nmovq xmm0, r14; x\nmovsd xmm2, [rsp+48h+cosx]\nmovsd xmm3, [rsp+48h+sinx]\nmovsd [rsp+48h+var_38], xmm2\nmovsd [rsp+48h+var_40], xmm3\ncall _sincos\nmovsd xmm1, [rsp+48h+var_30]\nsubsd xmm1, [rsp+48h+var_48]\nmovapd xmm0, xmm1; x\ncall _cos\nmovsd xmm2, [rsp+48h+var_38]\nmulsd xmm2, [rsp+48h+cosx]\nmovapd xmm1, xmm0\nmovsd xmm3, [rsp+48h+var_40]\nmulsd xmm3, [rsp+48h+sinx]\nmovapd xmm0, xmm2\nmulsd xmm0, xmm1\naddsd xmm0, xmm3; x\ncall _acos\nmulsd xmm0, cs:qword_20D0\nadd rsp, 30h\npop rbx\npop rbp\npop r14\nretn", + "ida_strip_pseudo": "double __fastcall sub_12B0(double a1, double a2, double a3, double a4)\n{\n double v4; // xmm0_8\n double v6; // [rsp+8h] [rbp-40h]\n double v7; // [rsp+10h] [rbp-38h]\n double cosx; // [rsp+20h] [rbp-28h] BYREF\n double sinx[4]; // [rsp+28h] [rbp-20h] BYREF\n\n sincos(a3, sinx, &cosx);\n v7 = cosx;\n v6 = sinx[0];\n sincos(a1, sinx, &cosx);\n v4 = cos(a2 - a4);\n return acos(v7 * cosx * v4 + v6 * sinx[0]) * 6371.01;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_12B0(double a1, double a2, double a3, double a4) {\n double v4;\n double v6;\n double v7;\n double cosx;\n double sinx[4];\n sincos(a3, sinx, &cosx);\n v7 = cosx;\n v6 = sinx[0];\n sincos(a1, sinx, &cosx);\n v4 = cos(a2 - a4);\n return acos(v7 * cosx * v4 + v6 * sinx[0]) * 6371.01;\n}", + "ida_pseudo_norm": "double func0(double a1, double a2, double a3, double a4) {\n double v4;\n double v6;\n double v7;\n double cosx;\n double sinx[4];\n sincos(a3, sinx, &cosx);\n v7 = cosx;\n v6 = sinx[0];\n sincos(a1, sinx, &cosx);\n v4 = cos(a2 - a4);\n return acos(v7 * cosx * v4 + v6 * sinx[0]) * 6371.01;\n}" + }, + { + "index": 180, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(double slat, double slon, double elat, double elon) {\n double dist = 6371.01 * acos(sin(slat) * sin(elat) +\n cos(slat) * cos(elat) * cos(slon - elon));\n return dist;\n}", + "test": "int main() {\n\n assert(func0(23.5, 67.5, 25.5, 69.5) == 12179.372041317429);\n\n assert(func0(10.5, 20.5, 30.5, 40.5) == 6069.397933300514);\n\n assert(func0(10, 20, 30, 40) == 6783.751974994595);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\nsub $0x48,%rsp\nlea 0x38(%rsp),%rbp\nlea 0x30(%rsp),%r12\nmovsd %xmm0,0x28(%rsp)\nmovapd %xmm2,%xmm0\nmov %r12,%rsi\nmov %rbp,%rdi\nmovsd %xmm1,0x20(%rsp)\nmovsd %xmm3,0x8(%rsp)\ncallq 1090 \nmovsd 0x28(%rsp),%xmm4\nmov %r12,%rsi\nmov %rbp,%rdi\nmovsd 0x30(%rsp),%xmm2\nmovsd 0x38(%rsp),%xmm3\nmovapd %xmm4,%xmm0\nmovsd %xmm2,0x18(%rsp)\nmovsd %xmm3,0x10(%rsp)\ncallq 1090 \nmovsd 0x20(%rsp),%xmm1\nsubsd 0x8(%rsp),%xmm1\nmovapd %xmm1,%xmm0\ncallq 10a0 \nmovsd 0x18(%rsp),%xmm2\nmulsd 0x30(%rsp),%xmm2\nmovsd 0x10(%rsp),%xmm3\nmulsd 0x38(%rsp),%xmm3\nmulsd %xmm0,%xmm2\nmovapd %xmm3,%xmm0\naddsd %xmm2,%xmm0\ncallq 10b0 \nmulsd 0xd8f(%rip),%xmm0\nadd $0x48,%rsp\npop %rbp\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\nmovq r14, xmm0\nmovapd xmm0, xmm2; x\npush rbp\npush rbx\nsub rsp, 30h\nlea rbx, [rsp+48h+sinx]\nlea rbp, [rsp+48h+cosx]\nmovsd [rsp+48h+var_30], xmm1\nmov rsi, rbp; cosx\nmov rdi, rbx; sinx\nmovsd [rsp+48h+var_48], xmm3\ncall _sincos\nmov rsi, rbp; cosx\nmov rdi, rbx; sinx\nmovq xmm0, r14; x\nmovsd xmm2, [rsp+48h+cosx]\nmovsd xmm3, [rsp+48h+sinx]\nmovsd [rsp+48h+var_38], xmm2\nmovsd [rsp+48h+var_40], xmm3\ncall _sincos\nmovsd xmm1, [rsp+48h+var_30]\nsubsd xmm1, [rsp+48h+var_48]\nmovapd xmm0, xmm1; x\ncall _cos\nmovsd xmm2, [rsp+48h+var_38]\nmulsd xmm2, [rsp+48h+cosx]\nmovapd xmm1, xmm0\nmovsd xmm3, [rsp+48h+var_40]\nmulsd xmm3, [rsp+48h+sinx]\nmovapd xmm0, xmm2\nmulsd xmm0, xmm1\naddsd xmm0, xmm3; x\ncall _acos\nmulsd xmm0, cs:qword_20D0\nadd rsp, 30h\npop rbx\npop rbp\npop r14\nretn", + "ida_pseudo": "double __fastcall func0(double a1, double a2, double a3, double a4)\n{\n double v4; // xmm0_8\n double v6; // [rsp+8h] [rbp-40h]\n double v7; // [rsp+10h] [rbp-38h]\n double cosx; // [rsp+20h] [rbp-28h] BYREF\n double sinx[4]; // [rsp+28h] [rbp-20h] BYREF\n\n sincos(a3, sinx, &cosx);\n v7 = cosx;\n v6 = sinx[0];\n sincos(a1, sinx, &cosx);\n v4 = cos(a2 - a4);\n return acos(v7 * cosx * v4 + v6 * sinx[0]) * 6371.01;\n}", + "ida_strip_asm": "sub_12B0:\nendbr64\npush r14\nmovq r14, xmm0\nmovapd xmm0, xmm2; x\npush rbp\npush rbx\nsub rsp, 30h\nlea rbx, [rsp+48h+sinx]\nlea rbp, [rsp+48h+cosx]\nmovsd [rsp+48h+var_30], xmm1\nmov rsi, rbp; cosx\nmov rdi, rbx; sinx\nmovsd [rsp+48h+var_48], xmm3\ncall _sincos\nmov rsi, rbp; cosx\nmov rdi, rbx; sinx\nmovq xmm0, r14; x\nmovsd xmm2, [rsp+48h+cosx]\nmovsd xmm3, [rsp+48h+sinx]\nmovsd [rsp+48h+var_38], xmm2\nmovsd [rsp+48h+var_40], xmm3\ncall _sincos\nmovsd xmm1, [rsp+48h+var_30]\nsubsd xmm1, [rsp+48h+var_48]\nmovapd xmm0, xmm1; x\ncall _cos\nmovsd xmm2, [rsp+48h+var_38]\nmulsd xmm2, [rsp+48h+cosx]\nmovapd xmm1, xmm0\nmovsd xmm3, [rsp+48h+var_40]\nmulsd xmm3, [rsp+48h+sinx]\nmovapd xmm0, xmm2\nmulsd xmm0, xmm1\naddsd xmm0, xmm3; x\ncall _acos\nmulsd xmm0, cs:qword_20D0\nadd rsp, 30h\npop rbx\npop rbp\npop r14\nretn", + "ida_strip_pseudo": "double __fastcall sub_12B0(double a1, double a2, double a3, double a4)\n{\n double v4; // xmm0_8\n double v6; // [rsp+8h] [rbp-40h]\n double v7; // [rsp+10h] [rbp-38h]\n double cosx; // [rsp+20h] [rbp-28h] BYREF\n double sinx[4]; // [rsp+28h] [rbp-20h] BYREF\n\n sincos(a3, sinx, &cosx);\n v7 = cosx;\n v6 = sinx[0];\n sincos(a1, sinx, &cosx);\n v4 = cos(a2 - a4);\n return acos(v7 * cosx * v4 + v6 * sinx[0]) * 6371.01;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_12B0(double a1, double a2, double a3, double a4) {\n double v4;\n double v6;\n double v7;\n double cosx;\n double sinx[4];\n sincos(a3, sinx, &cosx);\n v7 = cosx;\n v6 = sinx[0];\n sincos(a1, sinx, &cosx);\n v4 = cos(a2 - a4);\n return acos(v7 * cosx * v4 + v6 * sinx[0]) * 6371.01;\n}", + "ida_pseudo_norm": "double func0(double a1, double a2, double a3, double a4) {\n double v4;\n double v6;\n double v7;\n double cosx;\n double sinx[4];\n sincos(a3, sinx, &cosx);\n v7 = cosx;\n v6 = sinx[0];\n sincos(a1, sinx, &cosx);\n v4 = cos(a2 - a4);\n return acos(v7 * cosx * v4 + v6 * sinx[0]) * 6371.01;\n}" + }, + { + "index": 181, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char *func0(char *arr[], int n) {\n if (n == 0) return \"\";\n char *prefix = strdup(arr[0]);\n for (int i = 1; i < n; i++) {\n int j = 0;\n while (prefix[j] && arr[i][j] && prefix[j] == arr[i][j]) {\n j++;\n }\n prefix[j] = '\\0';\n }\n return prefix;\n}", + "test": "int main() {\n\n char *arr1[] = {\"tablets\", \"tables\", \"taxi\", \"tamarind\"};\n\n assert(strcmp(func0(arr1, 4), \"ta\") == 0);\n\n\n\n char *arr2[] = {\"apples\", \"ape\", \"april\"};\n\n assert(strcmp(func0(arr2, 3), \"ap\") == 0);\n\n\n\n char *arr3[] = {\"teens\", \"teenager\", \"teenmar\"};\n\n assert(strcmp(func0(arr3, 3), \"teen\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\ncmpl $0x0,-0x1c(%rbp)\njne 11ce \nlea 0xe3f(%rip),%rax\njmpq 128e \nmov -0x18(%rbp),%rax\nmov (%rax),%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\nmovl $0x1,-0x10(%rbp)\njmpq 127e \nmovl $0x0,-0xc(%rbp)\njmp 11fa \naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ntest %al,%al\nje 126a \nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rdx\nmov -0xc(%rbp),%eax\ncltq\nadd %rdx,%rax\nmovzbl (%rax),%eax\ntest %al,%al\nje 126a \nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%edx\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%rcx\nmov -0xc(%rbp),%eax\ncltq\nadd %rcx,%rax\nmovzbl (%rax),%eax\ncmp %al,%dl\nje 11f6 \nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmovb $0x0,(%rax)\naddl $0x1,-0x10(%rbp)\nmov -0x10(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11ed \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\ncmp [rbp+var_1C], 0\njnz short loc_11CE\nlea rax, unk_2008\njmp locret_128E\nloc_11CE:\nmov rax, [rbp+var_18]\nmov rax, [rax]\nmov rdi, rax; s\ncall _strdup\nmov [rbp+var_8], rax\nmov [rbp+var_10], 1\njmp loc_127E\nloc_11ED:\nmov [rbp+var_C], 0\njmp short loc_11FA\nloc_11F6:\nadd [rbp+var_C], 1\nloc_11FA:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njz short loc_126A\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njz short loc_126A\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov rcx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njz short loc_11F6\nloc_126A:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov byte ptr [rax], 0\nadd [rbp+var_10], 1\nloc_127E:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_1C]\njl loc_11ED\nmov rax, [rbp+var_8]\nlocret_128E:\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(const char **a1, int a2)\n{\n int i; // [rsp+10h] [rbp-10h]\n int j; // [rsp+14h] [rbp-Ch]\n char *v5; // [rsp+18h] [rbp-8h]\n\n if ( !a2 )\n return (char *)&unk_2008;\n v5 = strdup(*a1);\n for ( i = 1; i < a2; ++i )\n {\n for ( j = 0; v5[j] && a1[i][j] && v5[j] == a1[i][j]; ++j )\n ;\n v5[j] = 0;\n }\n return v5;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\ncmp [rbp+var_1C], 0\njnz short loc_11CE\nlea rax, unk_2008\njmp locret_128E\nloc_11CE:\nmov rax, [rbp+var_18]\nmov rax, [rax]\nmov rdi, rax; s\ncall _strdup\nmov [rbp+var_8], rax\nmov [rbp+var_10], 1\njmp loc_127E\nloc_11ED:\nmov [rbp+var_C], 0\njmp short loc_11FA\nloc_11F6:\nadd [rbp+var_C], 1\nloc_11FA:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njz short loc_126A\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njz short loc_126A\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov rcx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njz short loc_11F6\nloc_126A:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov byte ptr [rax], 0\nadd [rbp+var_10], 1\nloc_127E:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_1C]\njl loc_11ED\nmov rax, [rbp+var_8]\nlocret_128E:\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11A9(const char **a1, int a2)\n{\n int i; // [rsp+10h] [rbp-10h]\n int j; // [rsp+14h] [rbp-Ch]\n char *v5; // [rsp+18h] [rbp-8h]\n\n if ( !a2 )\n return (char *)&unk_2008;\n v5 = strdup(*a1);\n for ( i = 1; i < a2; ++i )\n {\n for ( j = 0; v5[j] && a1[i][j] && v5[j] == a1[i][j]; ++j )\n ;\n v5[j] = 0;\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11A9(const char **a1, int a2) {\n int i;\n int j;\n char *v5;\n if (!a2) return (char *)&unk_2008;\n v5 = strdup(*a1);\n for (i = 1; i < a2; ++i) {\n for (j = 0; v5[j] && a1[i][j] && v5[j] == a1[i][j]; ++j)\n ;\n v5[j] = 0;\n }\n return v5;\n}", + "ida_pseudo_norm": "char *func0(const char **a1, int a2) {\n int i;\n int j;\n char *v5;\n if (!a2) return (char *)&unk_2008;\n v5 = strdup(*a1);\n for (i = 1; i < a2; ++i) {\n for (j = 0; v5[j] && a1[i][j] && v5[j] == a1[i][j]; ++j)\n ;\n v5[j] = 0;\n }\n return v5;\n}" + }, + { + "index": 181, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char *func0(char *arr[], int n) {\n if (n == 0) return \"\";\n char *prefix = strdup(arr[0]);\n for (int i = 1; i < n; i++) {\n int j = 0;\n while (prefix[j] && arr[i][j] && prefix[j] == arr[i][j]) {\n j++;\n }\n prefix[j] = '\\0';\n }\n return prefix;\n}", + "test": "int main() {\n\n char *arr1[] = {\"tablets\", \"tables\", \"taxi\", \"tamarind\"};\n\n assert(strcmp(func0(arr1, 4), \"ta\") == 0);\n\n\n\n char *arr2[] = {\"apples\", \"ape\", \"april\"};\n\n assert(strcmp(func0(arr2, 3), \"ap\") == 0);\n\n\n\n char *arr3[] = {\"teens\", \"teenager\", \"teenmar\"};\n\n assert(strcmp(func0(arr3, 3), \"teen\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nlea 0xe8f(%rip),%rax\ntest %esi,%esi\njne 1199 \nretq\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbp\nmov %esi,%ebx\nmov (%rdi),%rdi\ncallq 1090 \ncmp $0x1,%ebx\njle 11f9 \nlea 0x8(%rbp),%r8\nlea -0x2(%rbx),%edx\nlea 0x10(%rbp,%rdx,8),%r9\njmp 11ce \nmov %rax,%rcx\nmovb $0x0,(%rcx)\nadd $0x8,%r8\ncmp %r9,%r8\nje 11f9 \nmovzbl (%rax),%edx\ntest %dl,%dl\nje 11bf \nmov (%r8),%rdi\nmov %rax,%rcx\nmovzbl (%rdi),%esi\ncmp %dl,%sil\njne 11c2 \ntest %sil,%sil\nje 11c2 \nadd $0x1,%rcx\nmovzbl (%rcx),%edx\nadd $0x1,%rdi\ntest %dl,%dl\njne 11db \njmp 11c2 \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\nlea rax, s2+2; \"\"\ntest esi, esi\njnz short loc_11B9\nretn\nloc_11B9:\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov ebx, esi\nmov rdi, [rdi]; s\ncall _strdup\ncmp ebx, 1\njle short loc_1219\nlea r8, [rbp+8]\nlea edx, [rbx-2]\nlea r9, [rbp+rdx*8+10h]\njmp short loc_11EE\nloc_11DF:\nmov rcx, rax\nloc_11E2:\nmov byte ptr [rcx], 0\nadd r8, 8\ncmp r8, r9\njz short loc_1219\nloc_11EE:\nmovzx edx, byte ptr [rax]\ntest dl, dl\njz short loc_11DF\nmov rdi, [r8]\nmov rcx, rax\nloc_11FB:\nmovzx esi, byte ptr [rdi]\ncmp sil, dl\njnz short loc_11E2\ntest sil, sil\njz short loc_11E2\nadd rcx, 1\nmovzx edx, byte ptr [rcx]\nadd rdi, 1\ntest dl, dl\njnz short loc_11FB\njmp short loc_11E2\nloc_1219:\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_pseudo": "char *__fastcall func0(const char **a1, int a2)\n{\n char *result; // rax\n _BYTE **v3; // r8\n __int64 v4; // r9\n char *v5; // rcx\n char v6; // dl\n _BYTE *v7; // rdi\n\n result = (char *)\"\";\n if ( a2 )\n {\n result = strdup(*a1);\n if ( a2 > 1 )\n {\n v3 = (_BYTE **)(a1 + 1);\n v4 = (__int64)&a1[(unsigned int)(a2 - 2) + 2];\n do\n {\n v6 = *result;\n if ( *result )\n {\n v7 = *v3;\n v5 = result;\n do\n {\n if ( *v7 != v6 )\n break;\n if ( !*v7 )\n break;\n v6 = *++v5;\n ++v7;\n }\n while ( *v5 );\n }\n else\n {\n v5 = result;\n }\n *v5 = 0;\n ++v3;\n }\n while ( v3 != (_BYTE **)v4 );\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\nlea rax, s2+2; \"\"\ntest esi, esi\njnz short loc_11B9\nretn\nloc_11B9:\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov ebx, esi\nmov rdi, [rdi]; s\ncall _strdup\ncmp ebx, 1\njle short loc_1219\nlea r8, [rbp+8]\nlea edx, [rbx-2]\nlea r9, [rbp+rdx*8+10h]\njmp short loc_11EE\nloc_11DF:\nmov rcx, rax\nloc_11E2:\nmov byte ptr [rcx], 0\nadd r8, 8\ncmp r8, r9\njz short loc_1219\nloc_11EE:\nmovzx edx, byte ptr [rax]\ntest dl, dl\njz short loc_11DF\nmov rdi, [r8]\nmov rcx, rax\nloc_11FB:\nmovzx esi, byte ptr [rdi]\ncmp sil, dl\njnz short loc_11E2\ntest sil, sil\njz short loc_11E2\nadd rcx, 1\nmovzx edx, byte ptr [rcx]\nadd rdi, 1\ntest dl, dl\njnz short loc_11FB\njmp short loc_11E2\nloc_1219:\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11A9(const char **a1, int a2)\n{\n char *result; // rax\n _BYTE **v3; // r8\n __int64 v4; // r9\n char *v5; // rcx\n char v6; // dl\n _BYTE *v7; // rdi\n\n result = (char *)\"\";\n if ( a2 )\n {\n result = strdup(*a1);\n if ( a2 > 1 )\n {\n v3 = (_BYTE **)(a1 + 1);\n v4 = (__int64)&a1[(unsigned int)(a2 - 2) + 2];\n do\n {\n v6 = *result;\n if ( *result )\n {\n v7 = *v3;\n v5 = result;\n do\n {\n if ( *v7 != v6 )\n break;\n if ( !*v7 )\n break;\n v6 = *++v5;\n ++v7;\n }\n while ( *v5 );\n }\n else\n {\n v5 = result;\n }\n *v5 = 0;\n ++v3;\n }\n while ( v3 != (_BYTE **)v4 );\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11A9(const char **a1, int a2) {\n char *result;\n uint8_t **v3;\n long long v4;\n char *v5;\n char v6;\n uint8_t *v7;\n result = (char *)\"\";\n if (a2) {\n result = strdup(*a1);\n if (a2 > 1) {\n v3 = (uint8_t **)(a1 + 1);\n v4 = (long long)&a1[(unsigned int)(a2 - 2) + 2];\n do {\n v6 = *result;\n if (*result) {\n v7 = *v3;\n v5 = result;\n do {\n if (*v7 != v6) break;\n if (!*v7) break;\n v6 = *++v5;\n ++v7;\n } while (*v5);\n } else {\n v5 = result;\n }\n *v5 = 0;\n ++v3;\n } while (v3 != (uint8_t **)v4);\n }\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(const char **a1, int a2) {\n char *result;\n uint8_t **v3;\n long long v4;\n char *v5;\n char v6;\n uint8_t *v7;\n result = (char *)\"\";\n if (a2) {\n result = strdup(*a1);\n if (a2 > 1) {\n v3 = (uint8_t **)(a1 + 1);\n v4 = (long long)&a1[(unsigned int)(a2 - 2) + 2];\n do {\n v6 = *result;\n if (*result) {\n v7 = *v3;\n v5 = result;\n do {\n if (*v7 != v6) break;\n if (!*v7) break;\n v6 = *++v5;\n ++v7;\n } while (*v5);\n } else {\n v5 = result;\n }\n *v5 = 0;\n ++v3;\n } while (v3 != (uint8_t **)v4);\n }\n }\n return result;\n}" + }, + { + "index": 181, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char *func0(char *arr[], int n) {\n if (n == 0) return \"\";\n char *prefix = strdup(arr[0]);\n for (int i = 1; i < n; i++) {\n int j = 0;\n while (prefix[j] && arr[i][j] && prefix[j] == arr[i][j]) {\n j++;\n }\n prefix[j] = '\\0';\n }\n return prefix;\n}", + "test": "int main() {\n\n char *arr1[] = {\"tablets\", \"tables\", \"taxi\", \"tamarind\"};\n\n assert(strcmp(func0(arr1, 4), \"ta\") == 0);\n\n\n\n char *arr2[] = {\"apples\", \"ape\", \"april\"};\n\n assert(strcmp(func0(arr2, 3), \"ap\") == 0);\n\n\n\n char *arr3[] = {\"teens\", \"teenager\", \"teenmar\"};\n\n assert(strcmp(func0(arr3, 3), \"teen\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njne 13a0 \nlea 0xc81(%rip),%rax\nretq\njmpq 1300 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0_part_0:\npush rbp\nmov ebp, esi\npush rbx\nmov rbx, rdi\nsub rsp, 8\nmov rdi, [rdi]; s\ncall _strdup\ncmp ebp, 1\njle short loc_13A9\nlea edx, [rbp-2]\nlea r8, [rbx+8]\nlea r9, [rbx+rdx*8+10h]\nnop dword ptr [rax+00h]\nloc_1368:\nmovzx edx, byte ptr [rax]\ntest dl, dl\njz short loc_13B0\nmov rdi, [r8]\nmov rcx, rax\njmp short loc_1395\nloc_1380:\ntest sil, sil\njz short loc_139D\nmovzx edx, byte ptr [rcx+1]\nadd rcx, 1\nadd rdi, 1\ntest dl, dl\njz short loc_139D\nloc_1395:\nmovzx esi, byte ptr [rdi]\ncmp sil, dl\njz short loc_1380\nloc_139D:\nadd r8, 8\nmov byte ptr [rcx], 0\ncmp r8, r9\njnz short loc_1368\nloc_13A9:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_13B0:\nmov rcx, rax\nadd r8, 8\nmov byte ptr [rcx], 0\ncmp r8, r9\njnz short loc_1368\njmp short loc_13A9", + "ida_pseudo": "char *__fastcall func0_part_0(const char **a1, int a2)\n{\n char *result; // rax\n _BYTE **v3; // r8\n __int64 v4; // r9\n char v5; // dl\n _BYTE *v6; // rdi\n char *v7; // rcx\n\n result = strdup(*a1);\n if ( a2 > 1 )\n {\n v3 = (_BYTE **)(a1 + 1);\n v4 = (__int64)&a1[(unsigned int)(a2 - 2) + 2];\n do\n {\n while ( 1 )\n {\n v5 = *result;\n if ( *result )\n break;\n ++v3;\n *result = 0;\n if ( v3 == (_BYTE **)v4 )\n return result;\n }\n v6 = *v3;\n v7 = result;\n do\n {\n if ( *v6 != v5 )\n break;\n if ( !*v6 )\n break;\n v5 = *++v7;\n ++v6;\n }\n while ( v5 );\n ++v3;\n *v7 = 0;\n }\n while ( v3 != (_BYTE **)v4 );\n }\n return result;\n}", + "ida_strip_asm": "sub_1340:\npush rbp\nmov ebp, esi\npush rbx\nmov rbx, rdi\nsub rsp, 8\nmov rdi, [rdi]; s\ncall _strdup\ncmp ebp, 1\njle short loc_13A9\nlea edx, [rbp-2]\nlea r8, [rbx+8]\nlea r9, [rbx+rdx*8+10h]\nnop dword ptr [rax+00h]\nloc_1368:\nmovzx edx, byte ptr [rax]\ntest dl, dl\njz short loc_13B0\nmov rdi, [r8]\nmov rcx, rax\njmp short loc_1395\nloc_1380:\ntest sil, sil\njz short loc_139D\nmovzx edx, byte ptr [rcx+1]\nadd rcx, 1\nadd rdi, 1\ntest dl, dl\njz short loc_139D\nloc_1395:\nmovzx esi, byte ptr [rdi]\ncmp sil, dl\njz short loc_1380\nloc_139D:\nadd r8, 8\nmov byte ptr [rcx], 0\ncmp r8, r9\njnz short loc_1368\nloc_13A9:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_13B0:\nmov rcx, rax\nadd r8, 8\nmov byte ptr [rcx], 0\ncmp r8, r9\njnz short loc_1368\njmp short loc_13A9", + "ida_strip_pseudo": "char *__fastcall sub_1340(const char **a1, int a2)\n{\n char *result; // rax\n _BYTE **v3; // r8\n __int64 v4; // r9\n char v5; // dl\n _BYTE *v6; // rdi\n char *v7; // rcx\n\n result = strdup(*a1);\n if ( a2 > 1 )\n {\n v3 = (_BYTE **)(a1 + 1);\n v4 = (__int64)&a1[(unsigned int)(a2 - 2) + 2];\n do\n {\n while ( 1 )\n {\n v5 = *result;\n if ( *result )\n break;\n ++v3;\n *result = 0;\n if ( v3 == (_BYTE **)v4 )\n return result;\n }\n v6 = *v3;\n v7 = result;\n do\n {\n if ( *v6 != v5 )\n break;\n if ( !*v6 )\n break;\n v5 = *++v7;\n ++v6;\n }\n while ( v5 );\n ++v3;\n *v7 = 0;\n }\n while ( v3 != (_BYTE **)v4 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1340(const char **a1, int a2) {\n char *result;\n uint8_t **v3;\n long long v4;\n char v5;\n uint8_t *v6;\n char *v7;\n result = strdup(*a1);\n if (a2 > 1) {\n v3 = (uint8_t **)(a1 + 1);\n v4 = (long long)&a1[(unsigned int)(a2 - 2) + 2];\n do {\n while (1) {\n v5 = *result;\n if (*result) break;\n ++v3;\n *result = 0;\n if (v3 == (uint8_t **)v4) return result;\n }\n v6 = *v3;\n v7 = result;\n do {\n if (*v6 != v5) break;\n if (!*v6) break;\n v5 = *++v7;\n ++v6;\n } while (v5);\n ++v3;\n *v7 = 0;\n } while (v3 != (uint8_t **)v4);\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0_part_0(const char **a1, int a2) {\n char *result;\n uint8_t **v3;\n long long v4;\n char v5;\n uint8_t *v6;\n char *v7;\n result = strdup(*a1);\n if (a2 > 1) {\n v3 = (uint8_t **)(a1 + 1);\n v4 = (long long)&a1[(unsigned int)(a2 - 2) + 2];\n do {\n while (1) {\n v5 = *result;\n if (*result) break;\n ++v3;\n *result = 0;\n if (v3 == (uint8_t **)v4) return result;\n }\n v6 = *v3;\n v7 = result;\n do {\n if (*v6 != v5) break;\n if (!*v6) break;\n v5 = *++v7;\n ++v6;\n } while (v5);\n ++v3;\n *v7 = 0;\n } while (v3 != (uint8_t **)v4);\n }\n return result;\n}" + }, + { + "index": 181, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char *func0(char *arr[], int n) {\n if (n == 0) return \"\";\n char *prefix = strdup(arr[0]);\n for (int i = 1; i < n; i++) {\n int j = 0;\n while (prefix[j] && arr[i][j] && prefix[j] == arr[i][j]) {\n j++;\n }\n prefix[j] = '\\0';\n }\n return prefix;\n}", + "test": "int main() {\n\n char *arr1[] = {\"tablets\", \"tables\", \"taxi\", \"tamarind\"};\n\n assert(strcmp(func0(arr1, 4), \"ta\") == 0);\n\n\n\n char *arr2[] = {\"apples\", \"ape\", \"april\"};\n\n assert(strcmp(func0(arr2, 3), \"ap\") == 0);\n\n\n\n char *arr3[] = {\"teens\", \"teenager\", \"teenmar\"};\n\n assert(strcmp(func0(arr3, 3), \"teen\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nlea 0xc55(%rip),%rax\ntest %esi,%esi\njne 13d0 \nretq\npush %rbp\nmov %rdi,%rbp\npush %rbx\nmov %esi,%ebx\nsub $0x8,%rsp\nmov (%rdi),%rdi\ncallq 1090 \ncmp $0x1,%ebx\njle 1439 \nlea -0x2(%rbx),%edx\nlea 0x8(%rbp),%r8\nlea 0x10(%rbp,%rdx,8),%r9\nnopl 0x0(%rax)\nmovzbl (%rax),%edx\ntest %dl,%dl\nje 1440 \nmov (%r8),%rdi\nmov %rax,%rcx\njmp 1425 \nnopw 0x0(%rax,%rax,1)\ntest %sil,%sil\nje 142d \nmovzbl 0x1(%rcx),%edx\nadd $0x1,%rcx\nadd $0x1,%rdi\ntest %dl,%dl\nje 142d \nmovzbl (%rdi),%esi\ncmp %dl,%sil\nje 1410 \nadd $0x8,%r8\nmovb $0x0,(%rcx)\ncmp %r9,%r8\njne 13f8 \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nmov %rax,%rcx\nadd $0x8,%r8\nmovb $0x0,(%rcx)\ncmp %r9,%r8\njne 13f8 \njmp 1439 \nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0_part_0:\npush rbp\nmov ebp, esi\npush rbx\nmov rbx, rdi\nsub rsp, 8\nmov rdi, [rdi]; s\ncall _strdup\ncmp ebp, 1\njle short loc_13A9\nlea edx, [rbp-2]\nlea r8, [rbx+8]\nlea r9, [rbx+rdx*8+10h]\nnop dword ptr [rax+00h]\nloc_1368:\nmovzx edx, byte ptr [rax]\ntest dl, dl\njz short loc_13B0\nmov rdi, [r8]\nmov rcx, rax\njmp short loc_1395\nloc_1380:\ntest sil, sil\njz short loc_139D\nmovzx edx, byte ptr [rcx+1]\nadd rcx, 1\nadd rdi, 1\ntest dl, dl\njz short loc_139D\nloc_1395:\nmovzx esi, byte ptr [rdi]\ncmp sil, dl\njz short loc_1380\nloc_139D:\nadd r8, 8\nmov byte ptr [rcx], 0\ncmp r9, r8\njnz short loc_1368\nloc_13A9:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_13B0:\nmov rcx, rax\nadd r8, 8\nmov byte ptr [rcx], 0\ncmp r9, r8\njnz short loc_1368\njmp short loc_13A9", + "ida_pseudo": "char *__fastcall func0_part_0(const char **a1, int a2)\n{\n char *result; // rax\n _BYTE **v3; // r8\n __int64 v4; // r9\n char v5; // dl\n _BYTE *v6; // rdi\n char *v7; // rcx\n\n result = strdup(*a1);\n if ( a2 > 1 )\n {\n v3 = (_BYTE **)(a1 + 1);\n v4 = (__int64)&a1[(unsigned int)(a2 - 2) + 2];\n do\n {\n while ( 1 )\n {\n v5 = *result;\n if ( *result )\n break;\n ++v3;\n *result = 0;\n if ( (_BYTE **)v4 == v3 )\n return result;\n }\n v6 = *v3;\n v7 = result;\n do\n {\n if ( *v6 != v5 )\n break;\n if ( !*v6 )\n break;\n v5 = *++v7;\n ++v6;\n }\n while ( v5 );\n ++v3;\n *v7 = 0;\n }\n while ( (_BYTE **)v4 != v3 );\n }\n return result;\n}", + "ida_strip_asm": "sub_1340:\npush rbp\nmov ebp, esi\npush rbx\nmov rbx, rdi\nsub rsp, 8\nmov rdi, [rdi]; s\ncall _strdup\ncmp ebp, 1\njle short loc_13A9\nlea edx, [rbp-2]\nlea r8, [rbx+8]\nlea r9, [rbx+rdx*8+10h]\nnop dword ptr [rax+00h]\nloc_1368:\nmovzx edx, byte ptr [rax]\ntest dl, dl\njz short loc_13B0\nmov rdi, [r8]\nmov rcx, rax\njmp short loc_1395\nloc_1380:\ntest sil, sil\njz short loc_139D\nmovzx edx, byte ptr [rcx+1]\nadd rcx, 1\nadd rdi, 1\ntest dl, dl\njz short loc_139D\nloc_1395:\nmovzx esi, byte ptr [rdi]\ncmp sil, dl\njz short loc_1380\nloc_139D:\nadd r8, 8\nmov byte ptr [rcx], 0\ncmp r9, r8\njnz short loc_1368\nloc_13A9:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_13B0:\nmov rcx, rax\nadd r8, 8\nmov byte ptr [rcx], 0\ncmp r9, r8\njnz short loc_1368\njmp short loc_13A9", + "ida_strip_pseudo": "char *__fastcall sub_1340(const char **a1, int a2)\n{\n char *result; // rax\n _BYTE **v3; // r8\n __int64 v4; // r9\n char v5; // dl\n _BYTE *v6; // rdi\n char *v7; // rcx\n\n result = strdup(*a1);\n if ( a2 > 1 )\n {\n v3 = (_BYTE **)(a1 + 1);\n v4 = (__int64)&a1[(unsigned int)(a2 - 2) + 2];\n do\n {\n while ( 1 )\n {\n v5 = *result;\n if ( *result )\n break;\n ++v3;\n *result = 0;\n if ( (_BYTE **)v4 == v3 )\n return result;\n }\n v6 = *v3;\n v7 = result;\n do\n {\n if ( *v6 != v5 )\n break;\n if ( !*v6 )\n break;\n v5 = *++v7;\n ++v6;\n }\n while ( v5 );\n ++v3;\n *v7 = 0;\n }\n while ( (_BYTE **)v4 != v3 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1340(const char **a1, int a2) {\n char *result;\n uint8_t **v3;\n long long v4;\n char v5;\n uint8_t *v6;\n char *v7;\n result = strdup(*a1);\n if (a2 > 1) {\n v3 = (uint8_t **)(a1 + 1);\n v4 = (long long)&a1[(unsigned int)(a2 - 2) + 2];\n do {\n while (1) {\n v5 = *result;\n if (*result) break;\n ++v3;\n *result = 0;\n if ((uint8_t **)v4 == v3) return result;\n }\n v6 = *v3;\n v7 = result;\n do {\n if (*v6 != v5) break;\n if (!*v6) break;\n v5 = *++v7;\n ++v6;\n } while (v5);\n ++v3;\n *v7 = 0;\n } while ((uint8_t **)v4 != v3);\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0_part_0(const char **a1, int a2) {\n char *result;\n uint8_t **v3;\n long long v4;\n char v5;\n uint8_t *v6;\n char *v7;\n result = strdup(*a1);\n if (a2 > 1) {\n v3 = (uint8_t **)(a1 + 1);\n v4 = (long long)&a1[(unsigned int)(a2 - 2) + 2];\n do {\n while (1) {\n v5 = *result;\n if (*result) break;\n ++v3;\n *result = 0;\n if ((uint8_t **)v4 == v3) return result;\n }\n v6 = *v3;\n v7 = result;\n do {\n if (*v6 != v5) break;\n if (!*v6) break;\n v5 = *++v7;\n ++v6;\n } while (v5);\n ++v3;\n *v7 = 0;\n } while ((uint8_t **)v4 != v3);\n }\n return result;\n}" + }, + { + "index": 182, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(char *string, char uppercase_characters[],\n char lowercase_characters[], char numerical_characters[],\n char special_characters[]) {\n int upper_idx = 0, lower_idx = 0, num_idx = 0, special_idx = 0;\n int len = strlen(string);\n for (int i = 0; i < len; i++) {\n if (isupper(string[i])) {\n uppercase_characters[upper_idx++] = string[i];\n } else if (islower(string[i])) {\n lowercase_characters[lower_idx++] = string[i];\n } else if (isdigit(string[i])) {\n numerical_characters[num_idx++] = string[i];\n } else if (string[i] == ',' || string[i] == '.' || string[i] == '!' ||\n string[i] == '?') {\n special_characters[special_idx++] = string[i];\n }\n }\n uppercase_characters[upper_idx] = '\\0';\n lowercase_characters[lower_idx] = '\\0';\n numerical_characters[num_idx] = '\\0';\n special_characters[special_idx] = '\\0';\n}", + "test": "int main() {\n\n char uppers[100], lowers[100], nums[100], specials[100];\n\n\n\n func0(\"ThisIsGeeksforGeeks\", uppers, lowers, nums, specials);\n\n assert(strcmp(uppers, \"TIGG\") == 0);\n\n assert(strcmp(lowers, \"hisseeksforeeks\") == 0);\n\n assert(strcmp(nums, \"\") == 0);\n\n assert(strcmp(specials, \"\") == 0);\n\n\n\n func0(\"Hithere2\", uppers, lowers, nums, specials);\n\n assert(strcmp(uppers, \"H\") == 0);\n\n assert(strcmp(lowers, \"ithere\") == 0);\n\n assert(strcmp(nums, \"2\") == 0);\n\n assert(strcmp(specials, \"\") == 0);\n\n\n\n func0(\"HeyFolks32\", uppers, lowers, nums, specials);\n\n assert(strcmp(uppers, \"HF\") == 0);\n\n assert(strcmp(lowers, \"eyolks\") == 0);\n\n assert(strcmp(nums, \"32\") == 0);\n\n assert(strcmp(specials, \"\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x50,%rsp\nmov %rdi,-0x28(%rbp)\nmov %rsi,-0x30(%rbp)\nmov %rdx,-0x38(%rbp)\nmov %rcx,-0x40(%rbp)\nmov %r8,-0x48(%rbp)\nmovl $0x0,-0x18(%rbp)\nmovl $0x0,-0x14(%rbp)\nmovl $0x0,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\nmov -0x28(%rbp),%rax\nmov %rax,%rdi\ncallq 1090 \nmov %eax,-0x4(%rbp)\nmovl $0x0,-0x8(%rbp)\njmpq 13ab \ncallq 10d0 <__ctype_b_loc@plt>\nmov (%rax),%rax\nmov -0x8(%rbp),%edx\nmovslq %edx,%rcx\nmov -0x28(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rdx),%edx\nmovsbq %dl,%rdx\nadd %rdx,%rdx\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x100,%eax\ntest %eax,%eax\nje 127c \nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x18(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x18(%rbp)\nmovslq %eax,%rdx\nmov -0x30(%rbp),%rax\nadd %rax,%rdx\nmovzbl (%rcx),%eax\nmov %al,(%rdx)\njmpq 13a7 \ncallq 10d0 <__ctype_b_loc@plt>\nmov (%rax),%rax\nmov -0x8(%rbp),%edx\nmovslq %edx,%rcx\nmov -0x28(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rdx),%edx\nmovsbq %dl,%rdx\nadd %rdx,%rdx\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x200,%eax\ntest %eax,%eax\nje 12d8 \nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x14(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x14(%rbp)\nmovslq %eax,%rdx\nmov -0x38(%rbp),%rax\nadd %rax,%rdx\nmovzbl (%rcx),%eax\nmov %al,(%rdx)\njmpq 13a7 \ncallq 10d0 <__ctype_b_loc@plt>\nmov (%rax),%rax\nmov -0x8(%rbp),%edx\nmovslq %edx,%rcx\nmov -0x28(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rdx),%edx\nmovsbq %dl,%rdx\nadd %rdx,%rdx\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x800,%eax\ntest %eax,%eax\nje 1331 \nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x10(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x10(%rbp)\nmovslq %eax,%rdx\nmov -0x40(%rbp),%rax\nadd %rax,%rdx\nmovzbl (%rcx),%eax\nmov %al,(%rdx)\njmp 13a7 \nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x2c,%al\nje 1381 \nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x2e,%al\nje 1381 \nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x21,%al\nje 1381 \nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x3f,%al\njne 13a7 \nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0xc(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0xc(%rbp)\nmovslq %eax,%rdx\nmov -0x48(%rbp),%rax\nadd %rax,%rdx\nmovzbl (%rcx),%eax\nmov %al,(%rdx)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x4(%rbp),%eax\njl 1220 \nmov -0x18(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x30(%rbp),%rax\nadd %rdx,%rax\nmovb $0x0,(%rax)\nmov -0x14(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmovb $0x0,(%rax)\nmov -0x10(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x40(%rbp),%rax\nadd %rdx,%rax\nmovb $0x0,(%rax)\nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmovb $0x0,(%rax)\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+s], rdi\nmov [rbp+var_30], rsi\nmov [rbp+var_38], rdx\nmov [rbp+var_40], rcx\nmov [rbp+var_48], r8\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_8], 0\njmp loc_13AB\nloc_1220:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_8]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 100h\ntest eax, eax\njz short loc_127C\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rdx, rax\nmovzx eax, byte ptr [rcx]\nmov [rdx], al\njmp loc_13A7\nloc_127C:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_8]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 200h\ntest eax, eax\njz short loc_12D8\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_14]\nlea edx, [rax+1]\nmov [rbp+var_14], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_38]\nadd rdx, rax\nmovzx eax, byte ptr [rcx]\nmov [rdx], al\njmp loc_13A7\nloc_12D8:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_8]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 800h\ntest eax, eax\njz short loc_1331\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_40]\nadd rdx, rax\nmovzx eax, byte ptr [rcx]\nmov [rdx], al\njmp short loc_13A7\nloc_1331:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 2Ch ; ','\njz short loc_1381\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 2Eh ; '.'\njz short loc_1381\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 21h ; '!'\njz short loc_1381\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 3Fh ; '?'\njnz short loc_13A7\nloc_1381:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_48]\nadd rdx, rax\nmovzx eax, byte ptr [rcx]\nmov [rdx], al\nloc_13A7:\nadd [rbp+var_8], 1\nloc_13AB:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njl loc_1220\nmov eax, [rbp+var_18]\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+var_40]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov byte ptr [rax], 0\nnop\nleave\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1, __int64 a2, __int64 a3, __int64 a4, __int64 a5)\n{\n int v5; // eax\n int v6; // eax\n int v7; // eax\n int v8; // eax\n _BYTE *result; // rax\n int v13; // [rsp+38h] [rbp-18h]\n int v14; // [rsp+3Ch] [rbp-14h]\n int v15; // [rsp+40h] [rbp-10h]\n int v16; // [rsp+44h] [rbp-Ch]\n int i; // [rsp+48h] [rbp-8h]\n int v18; // [rsp+4Ch] [rbp-4h]\n\n v13 = 0;\n v14 = 0;\n v15 = 0;\n v16 = 0;\n v18 = strlen(a1);\n for ( i = 0; i < v18; ++i )\n {\n if ( ((*__ctype_b_loc())[a1[i]] & 0x100) != 0 )\n {\n v5 = v13++;\n *(_BYTE *)(a2 + v5) = a1[i];\n }\n else if ( ((*__ctype_b_loc())[a1[i]] & 0x200) != 0 )\n {\n v6 = v14++;\n *(_BYTE *)(a3 + v6) = a1[i];\n }\n else if ( ((*__ctype_b_loc())[a1[i]] & 0x800) != 0 )\n {\n v7 = v15++;\n *(_BYTE *)(a4 + v7) = a1[i];\n }\n else if ( a1[i] == 44 || a1[i] == 46 || a1[i] == 33 || a1[i] == 63 )\n {\n v8 = v16++;\n *(_BYTE *)(a5 + v8) = a1[i];\n }\n }\n *(_BYTE *)(v13 + a2) = 0;\n *(_BYTE *)(v14 + a3) = 0;\n *(_BYTE *)(v15 + a4) = 0;\n result = (_BYTE *)(v16 + a5);\n *result = 0;\n return result;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+s], rdi\nmov [rbp+var_30], rsi\nmov [rbp+var_38], rdx\nmov [rbp+var_40], rcx\nmov [rbp+var_48], r8\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_8], 0\njmp loc_13AB\nloc_1220:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_8]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 100h\ntest eax, eax\njz short loc_127C\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rdx, rax\nmovzx eax, byte ptr [rcx]\nmov [rdx], al\njmp loc_13A7\nloc_127C:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_8]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 200h\ntest eax, eax\njz short loc_12D8\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_14]\nlea edx, [rax+1]\nmov [rbp+var_14], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_38]\nadd rdx, rax\nmovzx eax, byte ptr [rcx]\nmov [rdx], al\njmp loc_13A7\nloc_12D8:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_8]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 800h\ntest eax, eax\njz short loc_1331\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_40]\nadd rdx, rax\nmovzx eax, byte ptr [rcx]\nmov [rdx], al\njmp short loc_13A7\nloc_1331:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 2Ch ; ','\njz short loc_1381\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 2Eh ; '.'\njz short loc_1381\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 21h ; '!'\njz short loc_1381\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 3Fh ; '?'\njnz short loc_13A7\nloc_1381:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_48]\nadd rdx, rax\nmovzx eax, byte ptr [rcx]\nmov [rdx], al\nloc_13A7:\nadd [rbp+var_8], 1\nloc_13AB:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njl loc_1220\nmov eax, [rbp+var_18]\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+var_40]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov byte ptr [rax], 0\nnop\nleave\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_11C9(const char *a1, __int64 a2, __int64 a3, __int64 a4, __int64 a5)\n{\n int v5; // eax\n int v6; // eax\n int v7; // eax\n int v8; // eax\n _BYTE *result; // rax\n int v13; // [rsp+38h] [rbp-18h]\n int v14; // [rsp+3Ch] [rbp-14h]\n int v15; // [rsp+40h] [rbp-10h]\n int v16; // [rsp+44h] [rbp-Ch]\n int i; // [rsp+48h] [rbp-8h]\n int v18; // [rsp+4Ch] [rbp-4h]\n\n v13 = 0;\n v14 = 0;\n v15 = 0;\n v16 = 0;\n v18 = strlen(a1);\n for ( i = 0; i < v18; ++i )\n {\n if ( ((*__ctype_b_loc())[a1[i]] & 0x100) != 0 )\n {\n v5 = v13++;\n *(_BYTE *)(a2 + v5) = a1[i];\n }\n else if ( ((*__ctype_b_loc())[a1[i]] & 0x200) != 0 )\n {\n v6 = v14++;\n *(_BYTE *)(a3 + v6) = a1[i];\n }\n else if ( ((*__ctype_b_loc())[a1[i]] & 0x800) != 0 )\n {\n v7 = v15++;\n *(_BYTE *)(a4 + v7) = a1[i];\n }\n else if ( a1[i] == 44 || a1[i] == 46 || a1[i] == 33 || a1[i] == 63 )\n {\n v8 = v16++;\n *(_BYTE *)(a5 + v8) = a1[i];\n }\n }\n *(_BYTE *)(v13 + a2) = 0;\n *(_BYTE *)(v14 + a3) = 0;\n *(_BYTE *)(v15 + a4) = 0;\n result = (_BYTE *)(v16 + a5);\n *result = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_11C9(const char *a1, long long a2, long long a3, long long a4,\n long long a5) {\n int v5;\n int v6;\n int v7;\n int v8;\n uint8_t *result;\n int v13;\n int v14;\n int v15;\n int v16;\n int i;\n int v18;\n v13 = 0;\n v14 = 0;\n v15 = 0;\n v16 = 0;\n v18 = strlen(a1);\n for (i = 0; i < v18; ++i) {\n if (((*__ctype_b_loc())[a1[i]] & 256) != 0) {\n v5 = v13++;\n *(uint8_t *)(a2 + v5) = a1[i];\n } else if (((*__ctype_b_loc())[a1[i]] & 512) != 0) {\n v6 = v14++;\n *(uint8_t *)(a3 + v6) = a1[i];\n } else if (((*__ctype_b_loc())[a1[i]] & 2048) != 0) {\n v7 = v15++;\n *(uint8_t *)(a4 + v7) = a1[i];\n } else if (a1[i] == 44 || a1[i] == 46 || a1[i] == 33 || a1[i] == 63) {\n v8 = v16++;\n *(uint8_t *)(a5 + v8) = a1[i];\n }\n }\n *(uint8_t *)(v13 + a2) = 0;\n *(uint8_t *)(v14 + a3) = 0;\n *(uint8_t *)(v15 + a4) = 0;\n result = (uint8_t *)(v16 + a5);\n *result = 0;\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1, long long a2, long long a3, long long a4,\n long long a5) {\n int v5;\n int v6;\n int v7;\n int v8;\n uint8_t *result;\n int v13;\n int v14;\n int v15;\n int v16;\n int i;\n int v18;\n v13 = 0;\n v14 = 0;\n v15 = 0;\n v16 = 0;\n v18 = strlen(a1);\n for (i = 0; i < v18; ++i) {\n if (((*__ctype_b_loc())[a1[i]] & 256) != 0) {\n v5 = v13++;\n *(uint8_t *)(a2 + v5) = a1[i];\n } else if (((*__ctype_b_loc())[a1[i]] & 512) != 0) {\n v6 = v14++;\n *(uint8_t *)(a3 + v6) = a1[i];\n } else if (((*__ctype_b_loc())[a1[i]] & 2048) != 0) {\n v7 = v15++;\n *(uint8_t *)(a4 + v7) = a1[i];\n } else if (a1[i] == 44 || a1[i] == 46 || a1[i] == 33 || a1[i] == 63) {\n v8 = v16++;\n *(uint8_t *)(a5 + v8) = a1[i];\n }\n }\n *(uint8_t *)(v13 + a2) = 0;\n *(uint8_t *)(v14 + a3) = 0;\n *(uint8_t *)(v15 + a4) = 0;\n result = (uint8_t *)(v16 + a5);\n *result = 0;\n return result;\n}" + }, + { + "index": 182, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(char *string, char uppercase_characters[],\n char lowercase_characters[], char numerical_characters[],\n char special_characters[]) {\n int upper_idx = 0, lower_idx = 0, num_idx = 0, special_idx = 0;\n int len = strlen(string);\n for (int i = 0; i < len; i++) {\n if (isupper(string[i])) {\n uppercase_characters[upper_idx++] = string[i];\n } else if (islower(string[i])) {\n lowercase_characters[lower_idx++] = string[i];\n } else if (isdigit(string[i])) {\n numerical_characters[num_idx++] = string[i];\n } else if (string[i] == ',' || string[i] == '.' || string[i] == '!' ||\n string[i] == '?') {\n special_characters[special_idx++] = string[i];\n }\n }\n uppercase_characters[upper_idx] = '\\0';\n lowercase_characters[lower_idx] = '\\0';\n numerical_characters[num_idx] = '\\0';\n special_characters[special_idx] = '\\0';\n}", + "test": "int main() {\n\n char uppers[100], lowers[100], nums[100], specials[100];\n\n\n\n func0(\"ThisIsGeeksforGeeks\", uppers, lowers, nums, specials);\n\n assert(strcmp(uppers, \"TIGG\") == 0);\n\n assert(strcmp(lowers, \"hisseeksforeeks\") == 0);\n\n assert(strcmp(nums, \"\") == 0);\n\n assert(strcmp(specials, \"\") == 0);\n\n\n\n func0(\"Hithere2\", uppers, lowers, nums, specials);\n\n assert(strcmp(uppers, \"H\") == 0);\n\n assert(strcmp(lowers, \"ithere\") == 0);\n\n assert(strcmp(nums, \"2\") == 0);\n\n assert(strcmp(specials, \"\") == 0);\n\n\n\n func0(\"HeyFolks32\", uppers, lowers, nums, specials);\n\n assert(strcmp(uppers, \"HF\") == 0);\n\n assert(strcmp(lowers, \"eyolks\") == 0);\n\n assert(strcmp(nums, \"32\") == 0);\n\n assert(strcmp(specials, \"\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%r13\nmov %rsi,%rbp\nmov %rdx,%r12\nmov %rcx,%r14\nmov %r8,%r15\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nlea -0x1(%rcx),%rbx\ntest %ebx,%ebx\njle 1263 \ncallq 1090 <__ctype_b_loc@plt>\nmov %r13,%rdx\nlea -0x1(%rbx),%ecx\nlea 0x1(%r13,%rcx,1),%r9\nmov $0x0,%r11d\nmov $0x0,%r10d\nmov $0x0,%r8d\nmov $0x0,%edi\nmovabs $0x8000500200000000,%rbx\njmp 1215 \ntest $0x200,%si\nje 1237 \nmovslq %r8d,%rsi\nmov %cl,(%r12,%rsi,1)\nlea 0x1(%r8),%r8d\nadd $0x1,%rdx\ncmp %r9,%rdx\nje 127a \nmovzbl (%rdx),%ecx\nmovsbq %cl,%r13\nmov (%rax),%rsi\nmovzwl (%rsi,%r13,2),%esi\ntest $0x100,%si\nje 11fa \nmovslq %edi,%rsi\nmov %cl,0x0(%rbp,%rsi,1)\nlea 0x1(%rdi),%edi\njmp 120c \ntest $0x800,%si\nje 124b \nmovslq %r10d,%rsi\nmov %cl,(%r14,%rsi,1)\nlea 0x1(%r10),%r10d\njmp 120c \ncmp $0x3f,%cl\nja 120c \nbt %rcx,%rbx\njae 120c \nmovslq %r11d,%rsi\nmov %cl,(%r15,%rsi,1)\nlea 0x1(%r11),%r11d\njmp 120c \nmov $0x0,%r11d\nmov $0x0,%r10d\nmov $0x0,%r8d\nmov $0x0,%edi\nmovslq %edi,%rdi\nmovb $0x0,0x0(%rbp,%rdi,1)\nmovslq %r8d,%r8\nmovb $0x0,(%r12,%r8,1)\nmovslq %r10d,%r10\nmovb $0x0,(%r14,%r10,1)\nmovslq %r11d,%r11\nmovb $0x0,(%r15,%r11,1)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12, rdi\nmov rbx, rsi\nmov rbp, rdx\nmov r13, rcx\nmov r15, r8\ncall _strlen\ntest eax, eax\njle loc_1293\nmov r14, rax\ncall ___ctype_b_loc\nmov r8, rax\nmov rax, r12\nlea edx, [r14-1]\nlea r12, [r12+rdx+1]\nmov r11d, 0\nmov r10d, 0\nmov r9d, 0\nmov edi, 0\njmp short loc_1240\nloc_1227:\ntest ch, 2\njz short loc_125E\nmovsxd rcx, r9d\nmov [rbp+rcx+0], dl\nlea r9d, [r9+1]\nloc_1237:\nadd rax, 1\ncmp rax, r12\njz short loc_12AA\nloc_1240:\nmovzx edx, byte ptr [rax]\nmovsx rsi, dl\nmov rcx, [r8]\nmovzx ecx, word ptr [rcx+rsi*2]\ntest ch, 1\njz short loc_1227\nmovsxd rcx, edi\nmov [rbx+rcx], dl\nlea edi, [rdi+1]\njmp short loc_1237\nloc_125E:\ntest ch, 8\njz short loc_1271\nmovsxd rcx, r10d\nmov [r13+rcx+0], dl\nlea r10d, [r10+1]\njmp short loc_1237\nloc_1271:\ncmp dl, 3Fh ; '?'\nja short loc_1237\nmov rcx, 8000500200000000h\nbt rcx, rdx\njnb short loc_1237\nmovsxd rcx, r11d\nmov [r15+rcx], dl\nlea r11d, [r11+1]\njmp short loc_1237\nloc_1293:\nmov r11d, 0\nmov r10d, 0\nmov r9d, 0\nmov edi, 0\nloc_12AA:\nmovsxd rdi, edi\nmov byte ptr [rbx+rdi], 0\nmovsxd r9, r9d\nmov byte ptr [rbp+r9+0], 0\nmovsxd r10, r10d\nmov byte ptr [r13+r10+0], 0\nmovsxd r11, r11d\nmov byte ptr [r15+r11], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "unsigned __int8 *__fastcall func0(const char *a1, __int64 a2, __int64 a3, __int64 a4, __int64 a5)\n{\n unsigned __int8 *result; // rax\n int v9; // r14d\n const unsigned __int16 **v10; // r8\n __int64 v11; // r12\n int v12; // r11d\n int v13; // r10d\n int v14; // r9d\n int v15; // edi\n unsigned __int64 v16; // rdx\n unsigned __int16 v17; // cx\n unsigned __int64 v18; // rcx\n\n result = (unsigned __int8 *)strlen(a1);\n if ( (int)result <= 0 )\n {\n v12 = 0;\n v13 = 0;\n v14 = 0;\n v15 = 0;\n }\n else\n {\n v9 = (int)result;\n v10 = __ctype_b_loc();\n result = (unsigned __int8 *)a1;\n v11 = (__int64)&a1[v9 - 1 + 1];\n v12 = 0;\n v13 = 0;\n v14 = 0;\n v15 = 0;\n do\n {\n v16 = *result;\n v17 = (*v10)[(char)v16];\n if ( (v17 & 0x100) != 0 )\n {\n *(_BYTE *)(a2 + v15++) = v16;\n }\n else if ( (v17 & 0x200) != 0 )\n {\n *(_BYTE *)(a3 + v14++) = v16;\n }\n else if ( (v17 & 0x800) != 0 )\n {\n *(_BYTE *)(a4 + v13++) = v16;\n }\n else if ( (unsigned __int8)v16 <= 0x3Fu )\n {\n v18 = 0x8000500200000000LL;\n if ( _bittest64((const __int64 *)&v18, v16) )\n *(_BYTE *)(a5 + v12++) = v16;\n }\n ++result;\n }\n while ( result != (unsigned __int8 *)v11 );\n }\n *(_BYTE *)(a2 + v15) = 0;\n *(_BYTE *)(a3 + v14) = 0;\n *(_BYTE *)(a4 + v13) = 0;\n *(_BYTE *)(a5 + v12) = 0;\n return result;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12, rdi\nmov rbx, rsi\nmov rbp, rdx\nmov r13, rcx\nmov r15, r8\ncall _strlen\ntest eax, eax\njle loc_1293\nmov r14, rax\ncall ___ctype_b_loc\nmov r8, rax\nmov rax, r12\nlea edx, [r14-1]\nlea r12, [r12+rdx+1]\nmov r11d, 0\nmov r10d, 0\nmov r9d, 0\nmov edi, 0\njmp short loc_1240\nloc_1227:\ntest ch, 2\njz short loc_125E\nmovsxd rcx, r9d\nmov [rbp+rcx+0], dl\nlea r9d, [r9+1]\nloc_1237:\nadd rax, 1\ncmp rax, r12\njz short loc_12AA\nloc_1240:\nmovzx edx, byte ptr [rax]\nmovsx rsi, dl\nmov rcx, [r8]\nmovzx ecx, word ptr [rcx+rsi*2]\ntest ch, 1\njz short loc_1227\nmovsxd rcx, edi\nmov [rbx+rcx], dl\nlea edi, [rdi+1]\njmp short loc_1237\nloc_125E:\ntest ch, 8\njz short loc_1271\nmovsxd rcx, r10d\nmov [r13+rcx+0], dl\nlea r10d, [r10+1]\njmp short loc_1237\nloc_1271:\ncmp dl, 3Fh ; '?'\nja short loc_1237\nmov rcx, 8000500200000000h\nbt rcx, rdx\njnb short loc_1237\nmovsxd rcx, r11d\nmov [r15+rcx], dl\nlea r11d, [r11+1]\njmp short loc_1237\nloc_1293:\nmov r11d, 0\nmov r10d, 0\nmov r9d, 0\nmov edi, 0\nloc_12AA:\nmovsxd rdi, edi\nmov byte ptr [rbx+rdi], 0\nmovsxd r9, r9d\nmov byte ptr [rbp+r9+0], 0\nmovsxd r10, r10d\nmov byte ptr [r13+r10+0], 0\nmovsxd r11, r11d\nmov byte ptr [r15+r11], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "unsigned __int8 *__fastcall sub_11C9(const char *a1, __int64 a2, __int64 a3, __int64 a4, __int64 a5)\n{\n unsigned __int8 *result; // rax\n int v9; // r14d\n const unsigned __int16 **v10; // r8\n __int64 v11; // r12\n int v12; // r11d\n int v13; // r10d\n int v14; // r9d\n int v15; // edi\n unsigned __int64 v16; // rdx\n unsigned __int16 v17; // cx\n unsigned __int64 v18; // rcx\n\n result = (unsigned __int8 *)strlen(a1);\n if ( (int)result <= 0 )\n {\n v12 = 0;\n v13 = 0;\n v14 = 0;\n v15 = 0;\n }\n else\n {\n v9 = (int)result;\n v10 = __ctype_b_loc();\n result = (unsigned __int8 *)a1;\n v11 = (__int64)&a1[v9 - 1 + 1];\n v12 = 0;\n v13 = 0;\n v14 = 0;\n v15 = 0;\n do\n {\n v16 = *result;\n v17 = (*v10)[(char)v16];\n if ( (v17 & 0x100) != 0 )\n {\n *(_BYTE *)(a2 + v15++) = v16;\n }\n else if ( (v17 & 0x200) != 0 )\n {\n *(_BYTE *)(a3 + v14++) = v16;\n }\n else if ( (v17 & 0x800) != 0 )\n {\n *(_BYTE *)(a4 + v13++) = v16;\n }\n else if ( (unsigned __int8)v16 <= 0x3Fu )\n {\n v18 = 0x8000500200000000LL;\n if ( _bittest64((const __int64 *)&v18, v16) )\n *(_BYTE *)(a5 + v12++) = v16;\n }\n ++result;\n }\n while ( result != (unsigned __int8 *)v11 );\n }\n *(_BYTE *)(a2 + v15) = 0;\n *(_BYTE *)(a3 + v14) = 0;\n *(_BYTE *)(a4 + v13) = 0;\n *(_BYTE *)(a5 + v12) = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned char *sub_11C9(const char *a1, long long a2, long long a3,\n long long a4, long long a5) {\n unsigned char *result;\n int v9;\n const unsigned short **v10;\n long long v11;\n int v12;\n int v13;\n int v14;\n int v15;\n unsigned long long v16;\n unsigned short v17;\n unsigned long long v18;\n result = (unsigned char *)strlen(a1);\n if ((int)result <= 0) {\n v12 = 0;\n v13 = 0;\n v14 = 0;\n v15 = 0;\n } else {\n v9 = (int)result;\n v10 = __ctype_b_loc();\n result = (unsigned char *)a1;\n v11 = (long long)&a1[v9 - 1 + 1];\n v12 = 0;\n v13 = 0;\n v14 = 0;\n v15 = 0;\n do {\n v16 = *result;\n v17 = (*v10)[(char)v16];\n if ((v17 & 256) != 0) {\n *(uint8_t *)(a2 + v15++) = v16;\n } else if ((v17 & 512) != 0) {\n *(uint8_t *)(a3 + v14++) = v16;\n } else if ((v17 & 2048) != 0) {\n *(uint8_t *)(a4 + v13++) = v16;\n } else if ((unsigned char)v16 <= 63u) {\n v18 = 9223460006374932480LL;\n if (_bittest64((const long long *)&v18, v16))\n *(uint8_t *)(a5 + v12++) = v16;\n }\n ++result;\n } while (result != (unsigned char *)v11);\n }\n *(uint8_t *)(a2 + v15) = 0;\n *(uint8_t *)(a3 + v14) = 0;\n *(uint8_t *)(a4 + v13) = 0;\n *(uint8_t *)(a5 + v12) = 0;\n return result;\n}", + "ida_pseudo_norm": "unsigned char *func0(const char *a1, long long a2, long long a3, long long a4,\n long long a5) {\n unsigned char *result;\n int v9;\n const unsigned short **v10;\n long long v11;\n int v12;\n int v13;\n int v14;\n int v15;\n unsigned long long v16;\n unsigned short v17;\n unsigned long long v18;\n result = (unsigned char *)strlen(a1);\n if ((int)result <= 0) {\n v12 = 0;\n v13 = 0;\n v14 = 0;\n v15 = 0;\n } else {\n v9 = (int)result;\n v10 = __ctype_b_loc();\n result = (unsigned char *)a1;\n v11 = (long long)&a1[v9 - 1 + 1];\n v12 = 0;\n v13 = 0;\n v14 = 0;\n v15 = 0;\n do {\n v16 = *result;\n v17 = (*v10)[(char)v16];\n if ((v17 & 256) != 0) {\n *(uint8_t *)(a2 + v15++) = v16;\n } else if ((v17 & 512) != 0) {\n *(uint8_t *)(a3 + v14++) = v16;\n } else if ((v17 & 2048) != 0) {\n *(uint8_t *)(a4 + v13++) = v16;\n } else if ((unsigned char)v16 <= 63u) {\n v18 = 9223460006374932480LL;\n if (_bittest64((const long long *)&v18, v16))\n *(uint8_t *)(a5 + v12++) = v16;\n }\n ++result;\n } while (result != (unsigned char *)v11);\n }\n *(uint8_t *)(a2 + v15) = 0;\n *(uint8_t *)(a3 + v14) = 0;\n *(uint8_t *)(a4 + v13) = 0;\n *(uint8_t *)(a5 + v12) = 0;\n return result;\n}" + }, + { + "index": 182, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(char *string, char uppercase_characters[],\n char lowercase_characters[], char numerical_characters[],\n char special_characters[]) {\n int upper_idx = 0, lower_idx = 0, num_idx = 0, special_idx = 0;\n int len = strlen(string);\n for (int i = 0; i < len; i++) {\n if (isupper(string[i])) {\n uppercase_characters[upper_idx++] = string[i];\n } else if (islower(string[i])) {\n lowercase_characters[lower_idx++] = string[i];\n } else if (isdigit(string[i])) {\n numerical_characters[num_idx++] = string[i];\n } else if (string[i] == ',' || string[i] == '.' || string[i] == '!' ||\n string[i] == '?') {\n special_characters[special_idx++] = string[i];\n }\n }\n uppercase_characters[upper_idx] = '\\0';\n lowercase_characters[lower_idx] = '\\0';\n numerical_characters[num_idx] = '\\0';\n special_characters[special_idx] = '\\0';\n}", + "test": "int main() {\n\n char uppers[100], lowers[100], nums[100], specials[100];\n\n\n\n func0(\"ThisIsGeeksforGeeks\", uppers, lowers, nums, specials);\n\n assert(strcmp(uppers, \"TIGG\") == 0);\n\n assert(strcmp(lowers, \"hisseeksforeeks\") == 0);\n\n assert(strcmp(nums, \"\") == 0);\n\n assert(strcmp(specials, \"\") == 0);\n\n\n\n func0(\"Hithere2\", uppers, lowers, nums, specials);\n\n assert(strcmp(uppers, \"H\") == 0);\n\n assert(strcmp(lowers, \"ithere\") == 0);\n\n assert(strcmp(nums, \"2\") == 0);\n\n assert(strcmp(specials, \"\") == 0);\n\n\n\n func0(\"HeyFolks32\", uppers, lowers, nums, specials);\n\n assert(strcmp(uppers, \"HF\") == 0);\n\n assert(strcmp(lowers, \"eyolks\") == 0);\n\n assert(strcmp(nums, \"32\") == 0);\n\n assert(strcmp(specials, \"\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\nmov %rdi,%r13\npush %r12\npush %rbp\nmov %rdx,%rbp\npush %rbx\nmov %rsi,%rbx\nsub $0x38,%rsp\nmov %rcx,0x8(%rsp)\nmov %r8,0x10(%rsp)\ncallq 1080 \ntest %eax,%eax\njle 1620 \nmov %rax,%r14\nxor %r12d,%r12d\nxor %r15d,%r15d\ncallq 10b0 <__ctype_b_loc@plt>\nlea -0x1(%r14),%edx\nmov %r13,%rdi\nxor %r11d,%r11d\nlea 0x1(%r13,%rdx,1),%rsi\nxor %edx,%edx\nxor %r13d,%r13d\nmovl $0x0,0x2c(%rsp)\nmov %rsi,0x18(%rsp)\nmovl $0x0,0x28(%rsp)\nmovl $0x0,0x24(%rsp)\njmp 1541 \nnopl 0x0(%rax,%rax,1)\nadd $0x1,%r12d\nmov %r8b,(%r10)\nmovslq %r12d,%r11\nlea (%rbx,%r11,1),%r10\nadd $0x1,%rdi\ncmp %rdi,0x18(%rsp)\nje 1596 \nmovsbq (%rdi),%rsi\nmov (%rax),%rcx\nlea (%rbx,%r11,1),%r10\nmov 0x10(%rsp),%r14\nmovzwl (%rcx,%rsi,2),%r9d\nmov 0x8(%rsp),%rcx\nmov %rsi,%r8\nlea 0x0(%rbp,%rdx,1),%rsi\nadd %r15,%r14\nadd %r13,%rcx\ntest $0x100,%r9w\njne 1528 \ntest $0x200,%r9w\nje 15b8 \naddl $0x1,0x24(%rsp)\nmovslq 0x24(%rsp),%rdx\nadd $0x1,%rdi\nmov %r8b,(%rsi)\nlea 0x0(%rbp,%rdx,1),%rsi\ncmp %rdi,0x18(%rsp)\njne 1541 \nmovb $0x0,(%r10)\nmovb $0x0,(%rsi)\nmovb $0x0,(%rcx)\nmovb $0x0,(%r14)\nadd $0x38,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax,%rax,1)\ntest $0x800,%r9w\nje 15e0 \naddl $0x1,0x28(%rsp)\nmovslq 0x28(%rsp),%r13\nmov %r8b,(%rcx)\nmov 0x8(%rsp),%rcx\nadd %r13,%rcx\njmpq 1536 \nnopw 0x0(%rax,%rax,1)\ncmp $0x3f,%r8b\nja 1536 \nmovabs $0x8000500200000000,%r9\nbt %r8,%r9\njae 1536 \nmov %r8b,(%r14)\nmov 0x10(%rsp),%r8\naddl $0x1,0x2c(%rsp)\nmovslq 0x2c(%rsp),%r15\nlea (%r8,%r15,1),%r14\njmpq 1536 \nnopl 0x0(%rax)\nmov 0x10(%rsp),%r14\nmov 0x8(%rsp),%rcx\nmov %rbp,%rsi\nmov %rbx,%r10\njmpq 1596 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14, rdi\npush r13\nmov r13, r8\npush r12\nmov r12, rcx\npush rbp\nmov rbp, rdx\npush rbx\nmov rbx, rsi\nsub rsp, 8\ncall _strlen\ntest eax, eax\njle short loc_1545\nmov r15, rax\ncall ___ctype_b_loc\nmov rdx, r14\nxor r11d, r11d\nxor r8d, r8d\nmov r9, rax\nlea eax, [r15-1]\nxor r10d, r10d\nxor edi, edi\nlea r14, [r14+rax+1]\njmp short loc_1503\nloc_14F0:\nmovsxd rcx, edi\nadd edi, 1\nmov [rbx+rcx], sil\nloc_14FA:\nadd rdx, 1\ncmp r14, rdx\njz short loc_152D\nloc_1503:\nmovsx rsi, byte ptr [rdx]\nmov rcx, [r9]\nmovzx ecx, word ptr [rcx+rsi*2]\ntest ch, 1\njnz short loc_14F0\ntest ch, 2\njz short loc_1568\nmovsxd rcx, r10d\nadd rdx, 1\nadd r10d, 1\nmov [rbp+rcx+0], sil\ncmp r14, rdx\njnz short loc_1503\nloc_152D:\nmovsxd rdi, edi\nmovsxd r10, r10d\nmovsxd r8, r8d\nmovsxd r11, r11d\nadd rbx, rdi\nadd rbp, r10\nadd r12, r8\nadd r13, r11\nloc_1545:\nmov byte ptr [rbx], 0\nmov byte ptr [rbp+0], 0\nmov byte ptr [r12], 0\nmov byte ptr [r13+0], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1568:\nand ch, 8\njz short loc_1580\nmovsxd rcx, r8d\nadd r8d, 1\nmov [r12+rcx], sil\njmp short loc_14FA\nloc_1580:\ncmp sil, 3Fh ; '?'\nja loc_14FA\nmov rcx, 8000500200000000h\nbt rcx, rsi\njnb loc_14FA\nmovsxd rcx, r11d\nadd r11d, 1\nmov [r13+rcx+0], sil\njmp loc_14FA", + "ida_pseudo": "size_t __fastcall func0(const char *a1, _BYTE *a2, _BYTE *a3, _BYTE *a4, _BYTE *a5)\n{\n size_t result; // rax\n int v11; // r15d\n const unsigned __int16 **v12; // rax\n const char *v13; // rdx\n int v14; // r11d\n int v15; // r8d\n const unsigned __int16 **v16; // r9\n int v17; // r10d\n int v18; // edi\n __int64 v19; // r14\n __int64 v20; // rcx\n unsigned __int64 v21; // rsi\n unsigned __int16 v22; // cx\n __int64 v23; // rcx\n __int64 v24; // rcx\n unsigned __int64 v25; // rcx\n __int64 v26; // rcx\n\n result = strlen(a1);\n if ( (int)result > 0 )\n {\n v11 = result;\n v12 = __ctype_b_loc();\n v13 = a1;\n v14 = 0;\n v15 = 0;\n v16 = v12;\n result = (unsigned int)(v11 - 1);\n v17 = 0;\n v18 = 0;\n v19 = (__int64)&a1[result + 1];\n while ( 1 )\n {\n while ( 1 )\n {\n v21 = *v13;\n v22 = (*v16)[v21];\n if ( (v22 & 0x100) == 0 )\n break;\n v20 = v18++;\n a2[v20] = v21;\nLABEL_4:\n if ( (const char *)v19 == ++v13 )\n goto LABEL_8;\n }\n if ( (v22 & 0x200) == 0 )\n {\n if ( (v22 & 0x800) != 0 )\n {\n v24 = v15++;\n a4[v24] = v21;\n }\n else if ( (unsigned __int8)v21 <= 0x3Fu )\n {\n v25 = 0x8000500200000000LL;\n if ( _bittest64((const __int64 *)&v25, v21) )\n {\n v26 = v14++;\n a5[v26] = v21;\n }\n }\n goto LABEL_4;\n }\n v23 = v17;\n ++v13;\n ++v17;\n a3[v23] = v21;\n if ( (const char *)v19 == v13 )\n {\nLABEL_8:\n a2 += v18;\n a3 += v17;\n a4 += v15;\n a5 += v14;\n break;\n }\n }\n }\n *a2 = 0;\n *a3 = 0;\n *a4 = 0;\n *a5 = 0;\n return result;\n}", + "ida_strip_asm": "sub_14A0:\nendbr64\npush r15\npush r14\nmov r14, rdi\npush r13\nmov r13, r8\npush r12\nmov r12, rcx\npush rbp\nmov rbp, rdx\npush rbx\nmov rbx, rsi\nsub rsp, 8\ncall _strlen\ntest eax, eax\njle short loc_1545\nmov r15, rax\ncall ___ctype_b_loc\nmov rdx, r14\nxor r11d, r11d\nxor r8d, r8d\nmov r9, rax\nlea eax, [r15-1]\nxor r10d, r10d\nxor edi, edi\nlea r14, [r14+rax+1]\njmp short loc_1503\nloc_14F0:\nmovsxd rcx, edi\nadd edi, 1\nmov [rbx+rcx], sil\nloc_14FA:\nadd rdx, 1\ncmp r14, rdx\njz short loc_152D\nloc_1503:\nmovsx rsi, byte ptr [rdx]\nmov rcx, [r9]\nmovzx ecx, word ptr [rcx+rsi*2]\ntest ch, 1\njnz short loc_14F0\ntest ch, 2\njz short loc_1568\nmovsxd rcx, r10d\nadd rdx, 1\nadd r10d, 1\nmov [rbp+rcx+0], sil\ncmp r14, rdx\njnz short loc_1503\nloc_152D:\nmovsxd rdi, edi\nmovsxd r10, r10d\nmovsxd r8, r8d\nmovsxd r11, r11d\nadd rbx, rdi\nadd rbp, r10\nadd r12, r8\nadd r13, r11\nloc_1545:\nmov byte ptr [rbx], 0\nmov byte ptr [rbp+0], 0\nmov byte ptr [r12], 0\nmov byte ptr [r13+0], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1568:\nand ch, 8\njz short loc_1580\nmovsxd rcx, r8d\nadd r8d, 1\nmov [r12+rcx], sil\njmp short loc_14FA\nloc_1580:\ncmp sil, 3Fh ; '?'\nja loc_14FA\nmov rcx, 8000500200000000h\nbt rcx, rsi\njnb loc_14FA\nmovsxd rcx, r11d\nadd r11d, 1\nmov [r13+rcx+0], sil\njmp loc_14FA", + "ida_strip_pseudo": "size_t __fastcall sub_14A0(const char *a1, _BYTE *a2, _BYTE *a3, _BYTE *a4, _BYTE *a5)\n{\n size_t result; // rax\n int v11; // r15d\n const unsigned __int16 **v12; // rax\n const char *v13; // rdx\n int v14; // r11d\n int v15; // r8d\n const unsigned __int16 **v16; // r9\n int v17; // r10d\n int v18; // edi\n __int64 v19; // r14\n __int64 v20; // rcx\n unsigned __int64 v21; // rsi\n unsigned __int16 v22; // cx\n __int64 v23; // rcx\n __int64 v24; // rcx\n unsigned __int64 v25; // rcx\n __int64 v26; // rcx\n\n result = strlen(a1);\n if ( (int)result > 0 )\n {\n v11 = result;\n v12 = __ctype_b_loc();\n v13 = a1;\n v14 = 0;\n v15 = 0;\n v16 = v12;\n result = (unsigned int)(v11 - 1);\n v17 = 0;\n v18 = 0;\n v19 = (__int64)&a1[result + 1];\n while ( 1 )\n {\n while ( 1 )\n {\n v21 = *v13;\n v22 = (*v16)[v21];\n if ( (v22 & 0x100) == 0 )\n break;\n v20 = v18++;\n a2[v20] = v21;\nLABEL_4:\n if ( (const char *)v19 == ++v13 )\n goto LABEL_8;\n }\n if ( (v22 & 0x200) == 0 )\n {\n if ( (v22 & 0x800) != 0 )\n {\n v24 = v15++;\n a4[v24] = v21;\n }\n else if ( (unsigned __int8)v21 <= 0x3Fu )\n {\n v25 = 0x8000500200000000LL;\n if ( _bittest64((const __int64 *)&v25, v21) )\n {\n v26 = v14++;\n a5[v26] = v21;\n }\n }\n goto LABEL_4;\n }\n v23 = v17;\n ++v13;\n ++v17;\n a3[v23] = v21;\n if ( (const char *)v19 == v13 )\n {\nLABEL_8:\n a2 += v18;\n a3 += v17;\n a4 += v15;\n a5 += v14;\n break;\n }\n }\n }\n *a2 = 0;\n *a3 = 0;\n *a4 = 0;\n *a5 = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned int sub_14A0(const char *a1, uint8_t *a2, uint8_t *a3, uint8_t *a4,\n uint8_t *a5) {\n unsigned int result;\n int v11;\n const unsigned short **v12;\n const char *v13;\n int v14;\n int v15;\n const unsigned short **v16;\n int v17;\n int v18;\n long long v19;\n long long v20;\n unsigned long long v21;\n unsigned short v22;\n long long v23;\n long long v24;\n unsigned long long v25;\n long long v26;\n result = strlen(a1);\n if ((int)result > 0) {\n v11 = result;\n v12 = __ctype_b_loc();\n v13 = a1;\n v14 = 0;\n v15 = 0;\n v16 = v12;\n result = (unsigned int)(v11 - 1);\n v17 = 0;\n v18 = 0;\n v19 = (long long)&a1[result + 1];\n while (1) {\n while (1) {\n v21 = *v13;\n v22 = (*v16)[v21];\n if ((v22 & 256) == 0) break;\n v20 = v18++;\n a2[v20] = v21;\n LABEL_4:\n if ((const char *)v19 == ++v13) goto LABEL_8;\n }\n if ((v22 & 512) == 0) {\n if ((v22 & 2048) != 0) {\n v24 = v15++;\n a4[v24] = v21;\n } else if ((unsigned char)v21 <= 63u) {\n v25 = 9223460006374932480LL;\n if (_bittest64((const long long *)&v25, v21)) {\n v26 = v14++;\n a5[v26] = v21;\n }\n }\n goto LABEL_4;\n }\n v23 = v17;\n ++v13;\n ++v17;\n a3[v23] = v21;\n if ((const char *)v19 == v13) {\n LABEL_8:\n a2 += v18;\n a3 += v17;\n a4 += v15;\n a5 += v14;\n break;\n }\n }\n }\n *a2 = 0;\n *a3 = 0;\n *a4 = 0;\n *a5 = 0;\n return result;\n}", + "ida_pseudo_norm": "unsigned int func0(const char *a1, uint8_t *a2, uint8_t *a3, uint8_t *a4,\n uint8_t *a5) {\n unsigned int result;\n int v11;\n const unsigned short **v12;\n const char *v13;\n int v14;\n int v15;\n const unsigned short **v16;\n int v17;\n int v18;\n long long v19;\n long long v20;\n unsigned long long v21;\n unsigned short v22;\n long long v23;\n long long v24;\n unsigned long long v25;\n long long v26;\n result = strlen(a1);\n if ((int)result > 0) {\n v11 = result;\n v12 = __ctype_b_loc();\n v13 = a1;\n v14 = 0;\n v15 = 0;\n v16 = v12;\n result = (unsigned int)(v11 - 1);\n v17 = 0;\n v18 = 0;\n v19 = (long long)&a1[result + 1];\n while (1) {\n while (1) {\n v21 = *v13;\n v22 = (*v16)[v21];\n if ((v22 & 256) == 0) break;\n v20 = v18++;\n a2[v20] = v21;\n LABEL_4:\n if ((const char *)v19 == ++v13) goto LABEL_8;\n }\n if ((v22 & 512) == 0) {\n if ((v22 & 2048) != 0) {\n v24 = v15++;\n a4[v24] = v21;\n } else if ((unsigned char)v21 <= 63u) {\n v25 = 9223460006374932480LL;\n if (_bittest64((const long long *)&v25, v21)) {\n v26 = v14++;\n a5[v26] = v21;\n }\n }\n goto LABEL_4;\n }\n v23 = v17;\n ++v13;\n ++v17;\n a3[v23] = v21;\n if ((const char *)v19 == v13) {\n LABEL_8:\n a2 += v18;\n a3 += v17;\n a4 += v15;\n a5 += v14;\n break;\n }\n }\n }\n *a2 = 0;\n *a3 = 0;\n *a4 = 0;\n *a5 = 0;\n return result;\n}" + }, + { + "index": 182, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(char *string, char uppercase_characters[],\n char lowercase_characters[], char numerical_characters[],\n char special_characters[]) {\n int upper_idx = 0, lower_idx = 0, num_idx = 0, special_idx = 0;\n int len = strlen(string);\n for (int i = 0; i < len; i++) {\n if (isupper(string[i])) {\n uppercase_characters[upper_idx++] = string[i];\n } else if (islower(string[i])) {\n lowercase_characters[lower_idx++] = string[i];\n } else if (isdigit(string[i])) {\n numerical_characters[num_idx++] = string[i];\n } else if (string[i] == ',' || string[i] == '.' || string[i] == '!' ||\n string[i] == '?') {\n special_characters[special_idx++] = string[i];\n }\n }\n uppercase_characters[upper_idx] = '\\0';\n lowercase_characters[lower_idx] = '\\0';\n numerical_characters[num_idx] = '\\0';\n special_characters[special_idx] = '\\0';\n}", + "test": "int main() {\n\n char uppers[100], lowers[100], nums[100], specials[100];\n\n\n\n func0(\"ThisIsGeeksforGeeks\", uppers, lowers, nums, specials);\n\n assert(strcmp(uppers, \"TIGG\") == 0);\n\n assert(strcmp(lowers, \"hisseeksforeeks\") == 0);\n\n assert(strcmp(nums, \"\") == 0);\n\n assert(strcmp(specials, \"\") == 0);\n\n\n\n func0(\"Hithere2\", uppers, lowers, nums, specials);\n\n assert(strcmp(uppers, \"H\") == 0);\n\n assert(strcmp(lowers, \"ithere\") == 0);\n\n assert(strcmp(nums, \"2\") == 0);\n\n assert(strcmp(specials, \"\") == 0);\n\n\n\n func0(\"HeyFolks32\", uppers, lowers, nums, specials);\n\n assert(strcmp(uppers, \"HF\") == 0);\n\n assert(strcmp(lowers, \"eyolks\") == 0);\n\n assert(strcmp(nums, \"32\") == 0);\n\n assert(strcmp(specials, \"\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\nmov %rdi,%r13\npush %r12\npush %rbp\nmov %rdx,%rbp\npush %rbx\nmov %rsi,%rbx\nsub $0x38,%rsp\nmov %rcx,0x8(%rsp)\nmov %r8,0x10(%rsp)\ncallq 1080 \ntest %eax,%eax\njle 1620 \nmov %rax,%r14\nxor %r12d,%r12d\nxor %r15d,%r15d\ncallq 10b0 <__ctype_b_loc@plt>\nlea -0x1(%r14),%edx\nmov %r13,%rdi\nxor %r11d,%r11d\nlea 0x1(%r13,%rdx,1),%rsi\nxor %edx,%edx\nxor %r13d,%r13d\nmovl $0x0,0x2c(%rsp)\nmov %rsi,0x18(%rsp)\nmovl $0x0,0x28(%rsp)\nmovl $0x0,0x24(%rsp)\njmp 1541 \nnopl 0x0(%rax,%rax,1)\nadd $0x1,%r12d\nmov %r8b,(%r10)\nmovslq %r12d,%r11\nlea (%rbx,%r11,1),%r10\nadd $0x1,%rdi\ncmp %rdi,0x18(%rsp)\nje 1596 \nmovsbq (%rdi),%rsi\nmov (%rax),%rcx\nlea (%rbx,%r11,1),%r10\nmov 0x10(%rsp),%r14\nmovzwl (%rcx,%rsi,2),%r9d\nmov 0x8(%rsp),%rcx\nmov %rsi,%r8\nlea 0x0(%rbp,%rdx,1),%rsi\nadd %r15,%r14\nadd %r13,%rcx\ntest $0x100,%r9w\njne 1528 \ntest $0x200,%r9w\nje 15b8 \naddl $0x1,0x24(%rsp)\nmovslq 0x24(%rsp),%rdx\nadd $0x1,%rdi\nmov %r8b,(%rsi)\nlea 0x0(%rbp,%rdx,1),%rsi\ncmp %rdi,0x18(%rsp)\njne 1541 \nmovb $0x0,(%r10)\nmovb $0x0,(%rsi)\nmovb $0x0,(%rcx)\nmovb $0x0,(%r14)\nadd $0x38,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax,%rax,1)\ntest $0x800,%r9w\nje 15e0 \naddl $0x1,0x28(%rsp)\nmovslq 0x28(%rsp),%r13\nmov %r8b,(%rcx)\nmov 0x8(%rsp),%rcx\nadd %r13,%rcx\njmpq 1536 \nnopw 0x0(%rax,%rax,1)\ncmp $0x3f,%r8b\nja 1536 \nmovabs $0x8000500200000000,%r9\nbt %r8,%r9\njae 1536 \nmov %r8b,(%r14)\nmov 0x10(%rsp),%r8\naddl $0x1,0x2c(%rsp)\nmovslq 0x2c(%rsp),%r15\nlea (%r8,%r15,1),%r14\njmpq 1536 \nnopl 0x0(%rax)\nmov 0x10(%rsp),%r14\nmov 0x8(%rsp),%rcx\nmov %rbp,%rsi\nmov %rbx,%r10\njmpq 1596 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14, rdi\npush r13\nmov r13, r8\npush r12\nmov r12, rcx\npush rbp\nmov rbp, rdx\npush rbx\nmov rbx, rsi\nsub rsp, 8\ncall _strlen\ntest eax, eax\njle short loc_1545\nmov r15, rax\ncall ___ctype_b_loc\nmov rdx, r14\nxor r11d, r11d\nxor r8d, r8d\nmov r9, rax\nlea eax, [r15-1]\nxor r10d, r10d\nxor edi, edi\nlea r14, [r14+rax+1]\njmp short loc_1503\nloc_14F0:\nmovsxd rcx, edi\nadd edi, 1\nmov [rbx+rcx], sil\nloc_14FA:\nadd rdx, 1\ncmp r14, rdx\njz short loc_152D\nloc_1503:\nmovsx rsi, byte ptr [rdx]\nmov rcx, [r9]\nmovzx ecx, word ptr [rcx+rsi*2]\ntest ch, 1\njnz short loc_14F0\ntest ch, 2\njz short loc_1568\nmovsxd rcx, r10d\nadd rdx, 1\nadd r10d, 1\nmov [rbp+rcx+0], sil\ncmp r14, rdx\njnz short loc_1503\nloc_152D:\nmovsxd rdi, edi\nmovsxd r10, r10d\nmovsxd r8, r8d\nmovsxd r11, r11d\nadd rbx, rdi\nadd rbp, r10\nadd r12, r8\nadd r13, r11\nloc_1545:\nmov byte ptr [rbx], 0\nmov byte ptr [rbp+0], 0\nmov byte ptr [r12], 0\nmov byte ptr [r13+0], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1568:\nand ch, 8\njz short loc_1580\nmovsxd rcx, r8d\nadd r8d, 1\nmov [r12+rcx], sil\njmp short loc_14FA\nloc_1580:\ncmp sil, 3Fh ; '?'\nja loc_14FA\nmov rcx, 8000500200000000h\nbt rcx, rsi\njnb loc_14FA\nmovsxd rcx, r11d\nadd r11d, 1\nmov [r13+rcx+0], sil\njmp loc_14FA", + "ida_pseudo": "size_t __fastcall func0(const char *a1, _BYTE *a2, _BYTE *a3, _BYTE *a4, _BYTE *a5)\n{\n size_t result; // rax\n int v11; // r15d\n const unsigned __int16 **v12; // rax\n const char *v13; // rdx\n int v14; // r11d\n int v15; // r8d\n const unsigned __int16 **v16; // r9\n int v17; // r10d\n int v18; // edi\n __int64 v19; // r14\n __int64 v20; // rcx\n unsigned __int64 v21; // rsi\n unsigned __int16 v22; // cx\n __int64 v23; // rcx\n __int64 v24; // rcx\n unsigned __int64 v25; // rcx\n __int64 v26; // rcx\n\n result = strlen(a1);\n if ( (int)result > 0 )\n {\n v11 = result;\n v12 = __ctype_b_loc();\n v13 = a1;\n v14 = 0;\n v15 = 0;\n v16 = v12;\n result = (unsigned int)(v11 - 1);\n v17 = 0;\n v18 = 0;\n v19 = (__int64)&a1[result + 1];\n while ( 1 )\n {\n while ( 1 )\n {\n v21 = *v13;\n v22 = (*v16)[v21];\n if ( (v22 & 0x100) == 0 )\n break;\n v20 = v18++;\n a2[v20] = v21;\nLABEL_4:\n if ( (const char *)v19 == ++v13 )\n goto LABEL_8;\n }\n if ( (v22 & 0x200) == 0 )\n {\n if ( (v22 & 0x800) != 0 )\n {\n v24 = v15++;\n a4[v24] = v21;\n }\n else if ( (unsigned __int8)v21 <= 0x3Fu )\n {\n v25 = 0x8000500200000000LL;\n if ( _bittest64((const __int64 *)&v25, v21) )\n {\n v26 = v14++;\n a5[v26] = v21;\n }\n }\n goto LABEL_4;\n }\n v23 = v17;\n ++v13;\n ++v17;\n a3[v23] = v21;\n if ( (const char *)v19 == v13 )\n {\nLABEL_8:\n a2 += v18;\n a3 += v17;\n a4 += v15;\n a5 += v14;\n break;\n }\n }\n }\n *a2 = 0;\n *a3 = 0;\n *a4 = 0;\n *a5 = 0;\n return result;\n}", + "ida_strip_asm": "sub_14A0:\nendbr64\npush r15\npush r14\nmov r14, rdi\npush r13\nmov r13, r8\npush r12\nmov r12, rcx\npush rbp\nmov rbp, rdx\npush rbx\nmov rbx, rsi\nsub rsp, 8\ncall _strlen\ntest eax, eax\njle short loc_1545\nmov r15, rax\ncall ___ctype_b_loc\nmov rdx, r14\nxor r11d, r11d\nxor r8d, r8d\nmov r9, rax\nlea eax, [r15-1]\nxor r10d, r10d\nxor edi, edi\nlea r14, [r14+rax+1]\njmp short loc_1503\nloc_14F0:\nmovsxd rcx, edi\nadd edi, 1\nmov [rbx+rcx], sil\nloc_14FA:\nadd rdx, 1\ncmp r14, rdx\njz short loc_152D\nloc_1503:\nmovsx rsi, byte ptr [rdx]\nmov rcx, [r9]\nmovzx ecx, word ptr [rcx+rsi*2]\ntest ch, 1\njnz short loc_14F0\ntest ch, 2\njz short loc_1568\nmovsxd rcx, r10d\nadd rdx, 1\nadd r10d, 1\nmov [rbp+rcx+0], sil\ncmp r14, rdx\njnz short loc_1503\nloc_152D:\nmovsxd rdi, edi\nmovsxd r10, r10d\nmovsxd r8, r8d\nmovsxd r11, r11d\nadd rbx, rdi\nadd rbp, r10\nadd r12, r8\nadd r13, r11\nloc_1545:\nmov byte ptr [rbx], 0\nmov byte ptr [rbp+0], 0\nmov byte ptr [r12], 0\nmov byte ptr [r13+0], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1568:\nand ch, 8\njz short loc_1580\nmovsxd rcx, r8d\nadd r8d, 1\nmov [r12+rcx], sil\njmp short loc_14FA\nloc_1580:\ncmp sil, 3Fh ; '?'\nja loc_14FA\nmov rcx, 8000500200000000h\nbt rcx, rsi\njnb loc_14FA\nmovsxd rcx, r11d\nadd r11d, 1\nmov [r13+rcx+0], sil\njmp loc_14FA", + "ida_strip_pseudo": "size_t __fastcall sub_14A0(const char *a1, _BYTE *a2, _BYTE *a3, _BYTE *a4, _BYTE *a5)\n{\n size_t result; // rax\n int v11; // r15d\n const unsigned __int16 **v12; // rax\n const char *v13; // rdx\n int v14; // r11d\n int v15; // r8d\n const unsigned __int16 **v16; // r9\n int v17; // r10d\n int v18; // edi\n __int64 v19; // r14\n __int64 v20; // rcx\n unsigned __int64 v21; // rsi\n unsigned __int16 v22; // cx\n __int64 v23; // rcx\n __int64 v24; // rcx\n unsigned __int64 v25; // rcx\n __int64 v26; // rcx\n\n result = strlen(a1);\n if ( (int)result > 0 )\n {\n v11 = result;\n v12 = __ctype_b_loc();\n v13 = a1;\n v14 = 0;\n v15 = 0;\n v16 = v12;\n result = (unsigned int)(v11 - 1);\n v17 = 0;\n v18 = 0;\n v19 = (__int64)&a1[result + 1];\n while ( 1 )\n {\n while ( 1 )\n {\n v21 = *v13;\n v22 = (*v16)[v21];\n if ( (v22 & 0x100) == 0 )\n break;\n v20 = v18++;\n a2[v20] = v21;\nLABEL_4:\n if ( (const char *)v19 == ++v13 )\n goto LABEL_8;\n }\n if ( (v22 & 0x200) == 0 )\n {\n if ( (v22 & 0x800) != 0 )\n {\n v24 = v15++;\n a4[v24] = v21;\n }\n else if ( (unsigned __int8)v21 <= 0x3Fu )\n {\n v25 = 0x8000500200000000LL;\n if ( _bittest64((const __int64 *)&v25, v21) )\n {\n v26 = v14++;\n a5[v26] = v21;\n }\n }\n goto LABEL_4;\n }\n v23 = v17;\n ++v13;\n ++v17;\n a3[v23] = v21;\n if ( (const char *)v19 == v13 )\n {\nLABEL_8:\n a2 += v18;\n a3 += v17;\n a4 += v15;\n a5 += v14;\n break;\n }\n }\n }\n *a2 = 0;\n *a3 = 0;\n *a4 = 0;\n *a5 = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned int sub_14A0(const char *a1, uint8_t *a2, uint8_t *a3, uint8_t *a4,\n uint8_t *a5) {\n unsigned int result;\n int v11;\n const unsigned short **v12;\n const char *v13;\n int v14;\n int v15;\n const unsigned short **v16;\n int v17;\n int v18;\n long long v19;\n long long v20;\n unsigned long long v21;\n unsigned short v22;\n long long v23;\n long long v24;\n unsigned long long v25;\n long long v26;\n result = strlen(a1);\n if ((int)result > 0) {\n v11 = result;\n v12 = __ctype_b_loc();\n v13 = a1;\n v14 = 0;\n v15 = 0;\n v16 = v12;\n result = (unsigned int)(v11 - 1);\n v17 = 0;\n v18 = 0;\n v19 = (long long)&a1[result + 1];\n while (1) {\n while (1) {\n v21 = *v13;\n v22 = (*v16)[v21];\n if ((v22 & 256) == 0) break;\n v20 = v18++;\n a2[v20] = v21;\n LABEL_4:\n if ((const char *)v19 == ++v13) goto LABEL_8;\n }\n if ((v22 & 512) == 0) {\n if ((v22 & 2048) != 0) {\n v24 = v15++;\n a4[v24] = v21;\n } else if ((unsigned char)v21 <= 63u) {\n v25 = 9223460006374932480LL;\n if (_bittest64((const long long *)&v25, v21)) {\n v26 = v14++;\n a5[v26] = v21;\n }\n }\n goto LABEL_4;\n }\n v23 = v17;\n ++v13;\n ++v17;\n a3[v23] = v21;\n if ((const char *)v19 == v13) {\n LABEL_8:\n a2 += v18;\n a3 += v17;\n a4 += v15;\n a5 += v14;\n break;\n }\n }\n }\n *a2 = 0;\n *a3 = 0;\n *a4 = 0;\n *a5 = 0;\n return result;\n}", + "ida_pseudo_norm": "unsigned int func0(const char *a1, uint8_t *a2, uint8_t *a3, uint8_t *a4,\n uint8_t *a5) {\n unsigned int result;\n int v11;\n const unsigned short **v12;\n const char *v13;\n int v14;\n int v15;\n const unsigned short **v16;\n int v17;\n int v18;\n long long v19;\n long long v20;\n unsigned long long v21;\n unsigned short v22;\n long long v23;\n long long v24;\n unsigned long long v25;\n long long v26;\n result = strlen(a1);\n if ((int)result > 0) {\n v11 = result;\n v12 = __ctype_b_loc();\n v13 = a1;\n v14 = 0;\n v15 = 0;\n v16 = v12;\n result = (unsigned int)(v11 - 1);\n v17 = 0;\n v18 = 0;\n v19 = (long long)&a1[result + 1];\n while (1) {\n while (1) {\n v21 = *v13;\n v22 = (*v16)[v21];\n if ((v22 & 256) == 0) break;\n v20 = v18++;\n a2[v20] = v21;\n LABEL_4:\n if ((const char *)v19 == ++v13) goto LABEL_8;\n }\n if ((v22 & 512) == 0) {\n if ((v22 & 2048) != 0) {\n v24 = v15++;\n a4[v24] = v21;\n } else if ((unsigned char)v21 <= 63u) {\n v25 = 9223460006374932480LL;\n if (_bittest64((const long long *)&v25, v21)) {\n v26 = v14++;\n a5[v26] = v21;\n }\n }\n goto LABEL_4;\n }\n v23 = v17;\n ++v13;\n ++v17;\n a3[v23] = v21;\n if ((const char *)v19 == v13) {\n LABEL_8:\n a2 += v18;\n a3 += v17;\n a4 += v15;\n a5 += v14;\n break;\n }\n }\n }\n *a2 = 0;\n *a3 = 0;\n *a4 = 0;\n *a5 = 0;\n return result;\n}" + }, + { + "index": 183, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n, int k) {\n int count = 0;\n for (int i = 0; i < n; i++) {\n for (int j = i + 1; j < n; j++) {\n if (arr[i] - arr[j] == k || arr[j] - arr[i] == k) {\n count++;\n }\n }\n }\n return count;\n}", + "test": "int main() {\n\n int arr1[] = {1, 5, 3, 4, 2};\n\n int arr2[] = {8, 12, 16, 4, 0, 20};\n\n int arr3[] = {2, 4, 1, 3, 4};\n\n \n\n assert(func0(arr1, 5, 3) == 2);\n\n assert(func0(arr2, 6, 4) == 5);\n\n assert(func0(arr3, 5, 2) == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\njmpq 1217 \nmov -0x8(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x4(%rbp)\njmp 120b \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\nsub %eax,%edx\nmov %edx,%eax\ncmp %eax,-0x20(%rbp)\nje 1203 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\nsub %eax,%edx\nmov %edx,%eax\ncmp %eax,-0x20(%rbp)\njne 1207 \naddl $0x1,-0xc(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1199 \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 118e \nmov -0xc(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp loc_1213\nloc_118E:\nmov eax, [rbp+var_8]\nadd eax, 1\nmov [rbp+var_4], eax\njmp short loc_1207\nloc_1199:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nsub edx, eax\ncmp [rbp+var_20], edx\njz short loc_11FF\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nsub edx, eax\ncmp [rbp+var_20], edx\njnz short loc_1203\nloc_11FF:\nadd [rbp+var_C], 1\nloc_1203:\nadd [rbp+var_4], 1\nloc_1207:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1199\nadd [rbp+var_8], 1\nloc_1213:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl loc_118E\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n unsigned int v4; // [rsp+14h] [rbp-Ch]\n int i; // [rsp+18h] [rbp-8h]\n int j; // [rsp+1Ch] [rbp-4h]\n\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( a3 == *(_DWORD *)(4LL * i + a1) - *(_DWORD *)(4LL * j + a1)\n || a3 == *(_DWORD *)(4LL * j + a1) - *(_DWORD *)(4LL * i + a1) )\n {\n ++v4;\n }\n }\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp loc_1213\nloc_118E:\nmov eax, [rbp+var_8]\nadd eax, 1\nmov [rbp+var_4], eax\njmp short loc_1207\nloc_1199:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nsub edx, eax\ncmp [rbp+var_20], edx\njz short loc_11FF\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nsub edx, eax\ncmp [rbp+var_20], edx\njnz short loc_1203\nloc_11FF:\nadd [rbp+var_C], 1\nloc_1203:\nadd [rbp+var_4], 1\nloc_1207:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1199\nadd [rbp+var_8], 1\nloc_1213:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl loc_118E\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n unsigned int v4; // [rsp+14h] [rbp-Ch]\n int i; // [rsp+18h] [rbp-8h]\n int j; // [rsp+1Ch] [rbp-4h]\n\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( a3 == *(_DWORD *)(4LL * i + a1) - *(_DWORD *)(4LL * j + a1)\n || a3 == *(_DWORD *)(4LL * j + a1) - *(_DWORD *)(4LL * i + a1) )\n {\n ++v4;\n }\n }\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n unsigned int v4;\n int i;\n int j;\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if (a3 == *(uint32_t *)(4LL * i + a1) - *(uint32_t *)(4LL * j + a1) ||\n a3 == *(uint32_t *)(4LL * j + a1) - *(uint32_t *)(4LL * i + a1)) {\n ++v4;\n }\n }\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n unsigned int v4;\n int i;\n int j;\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if (a3 == *(uint32_t *)(4LL * i + a1) - *(uint32_t *)(4LL * j + a1) ||\n a3 == *(uint32_t *)(4LL * j + a1) - *(uint32_t *)(4LL * i + a1)) {\n ++v4;\n }\n }\n }\n return v4;\n}" + }, + { + "index": 183, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n, int k) {\n int count = 0;\n for (int i = 0; i < n; i++) {\n for (int j = i + 1; j < n; j++) {\n if (arr[i] - arr[j] == k || arr[j] - arr[i] == k) {\n count++;\n }\n }\n }\n return count;\n}", + "test": "int main() {\n\n int arr1[] = {1, 5, 3, 4, 2};\n\n int arr2[] = {8, 12, 16, 4, 0, 20};\n\n int arr3[] = {2, 4, 1, 3, 4};\n\n \n\n assert(func0(arr1, 5, 3) == 2);\n\n assert(func0(arr2, 6, 4) == 5);\n\n assert(func0(arr3, 5, 2) == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11bd \npush %rbx\nlea -0x1(%rsi),%ebx\nadd $0x1,%rbx\nmov $0x1,%r11d\nmov $0x0,%r10d\njmp 11ae \nadd $0x1,%r10d\nadd $0x1,%rax\ncmp %eax,%esi\njle 11aa \nmov (%rdi,%rax,4),%ecx\nmov %r9d,%r8d\nsub %ecx,%r8d\ncmp %edx,%r8d\nje 1187 \nsub %r9d,%ecx\ncmp %edx,%ecx\njne 118b \njmp 1187 \nadd $0x1,%r11\ncmp %rbx,%r11\nje 11c7 \nmov -0x4(%rdi,%r11,4),%r9d\nmov %r11,%rax\njmp 1193 \nmov $0x0,%r10d\nmov %r10d,%eax\nretq\nmov %r10d,%eax\npop %rbx\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11C6\npush rbp\npush rbx\nmov r10, rdi\nmov ebx, esi\nmovsxd rbp, esi\nmov r11d, 1\nmov r9d, 0\njmp short loc_11B7\nloc_1189:\nadd r9d, 1\nloc_118D:\nadd rax, 1\ncmp esi, eax\njle short loc_11AB\nloc_1195:\nmov ecx, [r10+rax*4]\nmov edi, r8d\nsub edi, ecx\ncmp edi, edx\njz short loc_1189\nsub ecx, r8d\ncmp ecx, edx\njnz short loc_118D\njmp short loc_1189\nloc_11AB:\nlea rax, [r11+1]\ncmp r11, rbp\njz short loc_11D0\nmov r11, rax\nloc_11B7:\ncmp r11, rbx\njz short loc_11D0\nmov r8d, [r10+r11*4-4]\nmov rax, r11\njmp short loc_1195\nloc_11C6:\nmov r9d, 0\nmov eax, r9d\nretn\nloc_11D0:\nmov eax, r9d\npop rbx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n __int64 v3; // r11\n unsigned int v4; // r9d\n __int64 v5; // rax\n int v6; // ecx\n int v7; // r8d\n\n if ( a2 <= 0 )\n return 0LL;\n v3 = 1LL;\n v4 = 0;\n while ( v3 != a2 )\n {\n v7 = *(_DWORD *)(a1 + 4 * v3 - 4);\n v5 = v3;\n do\n {\n v6 = *(_DWORD *)(a1 + 4 * v5);\n if ( v7 - v6 == a3 || v6 - v7 == a3 )\n ++v4;\n ++v5;\n }\n while ( a2 > (int)v5 );\n if ( v3 == a2 )\n break;\n ++v3;\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11C6\npush rbp\npush rbx\nmov r10, rdi\nmov ebx, esi\nmovsxd rbp, esi\nmov r11d, 1\nmov r9d, 0\njmp short loc_11B7\nloc_1189:\nadd r9d, 1\nloc_118D:\nadd rax, 1\ncmp esi, eax\njle short loc_11AB\nloc_1195:\nmov ecx, [r10+rax*4]\nmov edi, r8d\nsub edi, ecx\ncmp edi, edx\njz short loc_1189\nsub ecx, r8d\ncmp ecx, edx\njnz short loc_118D\njmp short loc_1189\nloc_11AB:\nlea rax, [r11+1]\ncmp r11, rbp\njz short loc_11D0\nmov r11, rax\nloc_11B7:\ncmp r11, rbx\njz short loc_11D0\nmov r8d, [r10+r11*4-4]\nmov rax, r11\njmp short loc_1195\nloc_11C6:\nmov r9d, 0\nmov eax, r9d\nretn\nloc_11D0:\nmov eax, r9d\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n __int64 v3; // r11\n unsigned int v4; // r9d\n __int64 v5; // rax\n int v6; // ecx\n int v7; // r8d\n\n if ( a2 <= 0 )\n return 0LL;\n v3 = 1LL;\n v4 = 0;\n while ( v3 != a2 )\n {\n v7 = *(_DWORD *)(a1 + 4 * v3 - 4);\n v5 = v3;\n do\n {\n v6 = *(_DWORD *)(a1 + 4 * v5);\n if ( v7 - v6 == a3 || v6 - v7 == a3 )\n ++v4;\n ++v5;\n }\n while ( a2 > (int)v5 );\n if ( v3 == a2 )\n break;\n ++v3;\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n long long v3;\n unsigned int v4;\n long long v5;\n int v6;\n int v7;\n if (a2 <= 0) return 0LL;\n v3 = 1LL;\n v4 = 0;\n while (v3 != a2) {\n v7 = *(uint32_t *)(a1 + 4 * v3 - 4);\n v5 = v3;\n do {\n v6 = *(uint32_t *)(a1 + 4 * v5);\n if (v7 - v6 == a3 || v6 - v7 == a3) ++v4;\n ++v5;\n } while (a2 > (int)v5);\n if (v3 == a2) break;\n ++v3;\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n long long v3;\n unsigned int v4;\n long long v5;\n int v6;\n int v7;\n if (a2 <= 0) return 0LL;\n v3 = 1LL;\n v4 = 0;\n while (v3 != a2) {\n v7 = *(uint32_t *)(a1 + 4 * v3 - 4);\n v5 = v3;\n do {\n v6 = *(uint32_t *)(a1 + 4 * v5);\n if (v7 - v6 == a3 || v6 - v7 == a3) ++v4;\n ++v5;\n } while (a2 > (int)v5);\n if (v3 == a2) break;\n ++v3;\n }\n return v4;\n}" + }, + { + "index": 183, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n, int k) {\n int count = 0;\n for (int i = 0; i < n; i++) {\n for (int j = i + 1; j < n; j++) {\n if (arr[i] - arr[j] == k || arr[j] - arr[i] == k) {\n count++;\n }\n }\n }\n return count;\n}", + "test": "int main() {\n\n int arr1[] = {1, 5, 3, 4, 2};\n\n int arr2[] = {8, 12, 16, 4, 0, 20};\n\n int arr3[] = {2, 4, 1, 3, 4};\n\n \n\n assert(func0(arr1, 5, 3) == 2);\n\n assert(func0(arr2, 6, 4) == 5);\n\n assert(func0(arr3, 5, 2) == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1407 \npush %rbx\nlea -0x1(%rsi),%ebx\nmov $0x1,%r11d\nxor %r10d,%r10d\nadd $0x1,%rbx\ncmp %rbx,%r11\nje 1402 \nxchg %ax,%ax\nmov -0x4(%rdi,%r11,4),%r9d\nmov %r11,%rax\njmp 13df \nnopw 0x0(%rax,%rax,1)\nsub %r9d,%ecx\ncmp %edx,%ecx\nje 13ed \nadd $0x1,%rax\ncmp %eax,%esi\njle 13f9 \nmov (%rdi,%rax,4),%ecx\nmov %r9d,%r8d\nsub %ecx,%r8d\ncmp %edx,%r8d\njne 13d0 \nadd $0x1,%rax\nadd $0x1,%r10d\ncmp %eax,%esi\njg 13df \nadd $0x1,%r11\ncmp %rbx,%r11\njne 13c0 \nmov %r10d,%eax\npop %rbx\nretq\nxor %r10d,%r10d\nmov %r10d,%eax\nretq\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_12F7\npush rbx\nmov r11d, 1\nmov ebx, esi\nxor r10d, r10d\ncmp esi, 1\njz short loc_12F2\nnop dword ptr [rax+00000000h]\nloc_12B0:\nmov r9d, [rdi+r11*4-4]\nmov rax, r11\njmp short loc_12CF\nloc_12C0:\nsub ecx, r9d\ncmp edx, ecx\njz short loc_12DD\nadd rax, 1\ncmp esi, eax\njle short loc_12E9\nloc_12CF:\nmov ecx, [rdi+rax*4]\nmov r8d, r9d\nsub r8d, ecx\ncmp edx, r8d\njnz short loc_12C0\nloc_12DD:\nadd rax, 1\nadd r10d, 1\ncmp esi, eax\njg short loc_12CF\nloc_12E9:\nadd r11, 1\ncmp r11, rbx\njnz short loc_12B0\nloc_12F2:\nmov eax, r10d\npop rbx\nretn\nloc_12F7:\nxor eax, eax\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n __int64 v3; // r11\n unsigned int v4; // r10d\n int v5; // r9d\n __int64 v6; // rax\n int v7; // ecx\n\n if ( a2 <= 0 )\n return 0LL;\n v3 = 1LL;\n v4 = 0;\n if ( a2 != 1 )\n {\n do\n {\n v5 = *(_DWORD *)(a1 + 4 * v3 - 4);\n v6 = v3;\n do\n {\n while ( 1 )\n {\n v7 = *(_DWORD *)(a1 + 4 * v6);\n if ( a3 == v5 - v7 || a3 == v7 - v5 )\n break;\n if ( a2 <= (int)++v6 )\n goto LABEL_8;\n }\n ++v6;\n ++v4;\n }\n while ( a2 > (int)v6 );\nLABEL_8:\n ++v3;\n }\n while ( v3 != a2 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_1290:\nendbr64\ntest esi, esi\njle short loc_12F7\npush rbx\nmov r11d, 1\nmov ebx, esi\nxor r10d, r10d\ncmp esi, 1\njz short loc_12F2\nnop dword ptr [rax+00000000h]\nloc_12B0:\nmov r9d, [rdi+r11*4-4]\nmov rax, r11\njmp short loc_12CF\nloc_12C0:\nsub ecx, r9d\ncmp edx, ecx\njz short loc_12DD\nadd rax, 1\ncmp esi, eax\njle short loc_12E9\nloc_12CF:\nmov ecx, [rdi+rax*4]\nmov r8d, r9d\nsub r8d, ecx\ncmp edx, r8d\njnz short loc_12C0\nloc_12DD:\nadd rax, 1\nadd r10d, 1\ncmp esi, eax\njg short loc_12CF\nloc_12E9:\nadd r11, 1\ncmp r11, rbx\njnz short loc_12B0\nloc_12F2:\nmov eax, r10d\npop rbx\nretn\nloc_12F7:\nxor eax, eax\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1290(__int64 a1, int a2, int a3)\n{\n __int64 v3; // r11\n unsigned int v4; // r10d\n int v5; // r9d\n __int64 v6; // rax\n int v7; // ecx\n\n if ( a2 <= 0 )\n return 0LL;\n v3 = 1LL;\n v4 = 0;\n if ( a2 != 1 )\n {\n do\n {\n v5 = *(_DWORD *)(a1 + 4 * v3 - 4);\n v6 = v3;\n do\n {\n while ( 1 )\n {\n v7 = *(_DWORD *)(a1 + 4 * v6);\n if ( a3 == v5 - v7 || a3 == v7 - v5 )\n break;\n if ( a2 <= (int)++v6 )\n goto LABEL_8;\n }\n ++v6;\n ++v4;\n }\n while ( a2 > (int)v6 );\nLABEL_8:\n ++v3;\n }\n while ( v3 != a2 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1290(long long a1, int a2, int a3) {\n long long v3;\n unsigned int v4;\n int v5;\n long long v6;\n int v7;\n if (a2 <= 0) return 0LL;\n v3 = 1LL;\n v4 = 0;\n if (a2 != 1) {\n do {\n v5 = *(uint32_t *)(a1 + 4 * v3 - 4);\n v6 = v3;\n do {\n while (1) {\n v7 = *(uint32_t *)(a1 + 4 * v6);\n if (a3 == v5 - v7 || a3 == v7 - v5) break;\n if (a2 <= (int)++v6) goto LABEL_8;\n }\n ++v6;\n ++v4;\n } while (a2 > (int)v6);\n LABEL_8:\n ++v3;\n } while (v3 != a2);\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n long long v3;\n unsigned int v4;\n int v5;\n long long v6;\n int v7;\n if (a2 <= 0) return 0LL;\n v3 = 1LL;\n v4 = 0;\n if (a2 != 1) {\n do {\n v5 = *(uint32_t *)(a1 + 4 * v3 - 4);\n v6 = v3;\n do {\n while (1) {\n v7 = *(uint32_t *)(a1 + 4 * v6);\n if (a3 == v5 - v7 || a3 == v7 - v5) break;\n if (a2 <= (int)++v6) goto LABEL_8;\n }\n ++v6;\n ++v4;\n } while (a2 > (int)v6);\n LABEL_8:\n ++v3;\n } while (v3 != a2);\n }\n return v4;\n}" + }, + { + "index": 184, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int list[], int count, int num) {\n for (int i = 0; i < count; i++) {\n if (list[i] < num) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n int arr1[] = {220, 330, 500};\n\n int arr2[] = {12, 17, 21};\n\n int arr3[] = {1, 2, 3, 4};\n\n \n\n assert(func0(arr1, 3, 200) == true);\n\n assert(func0(arr2, 3, 20) == false);\n\n assert(func0(arr3, 4, 10) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11aa \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x20(%rbp)\njle 11a6 \nmov $0x0,%eax\njmp 11b7 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1184 \nmov $0x1,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_4], 0\njmp short loc_11AA\nloc_1184:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njle short loc_11A6\nmov eax, 0\njmp short loc_11B7\nloc_11A6:\nadd [rbp+var_4], 1\nloc_11AA:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1184\nmov eax, 1\nloc_11B7:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n int i; // [rsp+1Ch] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n if ( a3 > *(_DWORD *)(4LL * i + a1) )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_4], 0\njmp short loc_11AA\nloc_1184:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njle short loc_11A6\nmov eax, 0\njmp short loc_11B7\nloc_11A6:\nadd [rbp+var_4], 1\nloc_11AA:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1184\nmov eax, 1\nloc_11B7:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n int i; // [rsp+1Ch] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n if ( a3 > *(_DWORD *)(4LL * i + a1) )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n int i;\n for (i = 0; i < a2; ++i) {\n if (a3 > *(uint32_t *)(4LL * i + a1)) return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n int i;\n for (i = 0; i < a2; ++i) {\n if (a3 > *(uint32_t *)(4LL * i + a1)) return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": 184, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int list[], int count, int num) {\n for (int i = 0; i < count; i++) {\n if (list[i] < num) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n int arr1[] = {220, 330, 500};\n\n int arr2[] = {12, 17, 21};\n\n int arr3[] = {1, 2, 3, 4};\n\n \n\n assert(func0(arr1, 3, 200) == true);\n\n assert(func0(arr2, 3, 20) == false);\n\n assert(func0(arr3, 4, 10) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 118f \nmov %rdi,%rax\nlea -0x1(%rsi),%ecx\nlea 0x4(%rdi,%rcx,4),%rcx\ncmp %edx,(%rax)\njl 1195 \nadd $0x4,%rax\ncmp %rcx,%rax\njne 117c \nmov $0x1,%eax\nretq\nmov $0x1,%eax\nretq\nmov $0x0,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_118E\nmov rax, rdi\nmovsxd rsi, esi\nlea rcx, [rdi+rsi*4]\nloc_117B:\ncmp [rax], edx\njl short loc_1194\nadd rax, 4\ncmp rax, rcx\njnz short loc_117B\nmov eax, 1\nretn\nloc_118E:\nmov eax, 1\nretn\nloc_1194:\nmov eax, 0\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2, int a3)\n{\n _DWORD *v3; // rax\n\n if ( a2 <= 0 )\n return 1LL;\n v3 = a1;\n while ( *v3 >= a3 )\n {\n if ( ++v3 == &a1[a2] )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_118E\nmov rax, rdi\nmovsxd rsi, esi\nlea rcx, [rdi+rsi*4]\nloc_117B:\ncmp [rax], edx\njl short loc_1194\nadd rax, 4\ncmp rax, rcx\njnz short loc_117B\nmov eax, 1\nretn\nloc_118E:\nmov eax, 1\nretn\nloc_1194:\nmov eax, 0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2, int a3)\n{\n _DWORD *v3; // rax\n\n if ( a2 <= 0 )\n return 1LL;\n v3 = a1;\n while ( *v3 >= a3 )\n {\n if ( ++v3 == &a1[a2] )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2, int a3) {\n uint32_t *v3;\n if (a2 <= 0) return 1LL;\n v3 = a1;\n while (*v3 >= a3) {\n if (++v3 == &a1[a2]) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2, int a3) {\n uint32_t *v3;\n if (a2 <= 0) return 1LL;\n v3 = a1;\n while (*v3 >= a3) {\n if (++v3 == &a1[a2]) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 185, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double* func0(double a, double b, double c) {\n static double focus[2];\n focus[0] = -b / (2 * a);\n focus[1] = ((4 * a * c) - (b * b) + 1) / (4 * a);\n return focus;\n}", + "test": "int main() {\n\n double *result;\n\n\n\n result = func0(5, 3, 2);\n\n assert(result[0] == -0.3);\n\n assert(result[1] == 1.6);\n\n\n\n result = func0(9, 8, 4);\n\n assert(result[0] == -0.4444444444444444);\n\n assert(result[1] == 2.25);\n\n\n\n result = func0(2, 4, 6);\n\n assert(result[0] == -1.0);\n\n assert(result[1] == 4.125);\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmovsd %xmm0,-0x8(%rbp)\nmovsd %xmm1,-0x10(%rbp)\nmovsd %xmm2,-0x18(%rbp)\nmovsd -0x10(%rbp),%xmm0\nmovq 0xf63(%rip),%xmm1\nxorpd %xmm0,%xmm1\nmovsd -0x8(%rbp),%xmm0\naddsd %xmm0,%xmm0\ndivsd %xmm0,%xmm1\nmovapd %xmm1,%xmm0\nmovsd %xmm0,0x2e76(%rip)\nmovsd -0x8(%rbp),%xmm1\nmovsd 0xf49(%rip),%xmm0\nmulsd %xmm1,%xmm0\nmovapd %xmm0,%xmm1\nmulsd -0x18(%rbp),%xmm1\nmovsd -0x10(%rbp),%xmm0\nmulsd %xmm0,%xmm0\nsubsd %xmm0,%xmm1\nmovsd 0xf2f(%rip),%xmm0\naddsd %xmm1,%xmm0\nmovsd -0x8(%rbp),%xmm2\nmovsd 0xf16(%rip),%xmm1\nmulsd %xmm2,%xmm1\ndivsd %xmm1,%xmm0\nmovsd %xmm0,0x2e2e(%rip)\nlea 0x2e1f(%rip),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmovsd [rbp+var_8], xmm0\nmovsd [rbp+var_10], xmm1\nmovsd [rbp+var_18], xmm2\nmovsd xmm0, [rbp+var_10]\nmovq xmm1, cs:qword_20E0\nxorpd xmm1, xmm0\nmovsd xmm0, [rbp+var_8]\nmovapd xmm2, xmm0\naddsd xmm2, xmm0\ndivsd xmm1, xmm2\nmovapd xmm0, xmm1\nmovsd cs:focus_1, xmm0\nmovsd xmm1, [rbp+var_8]\nmovsd xmm0, cs:qword_20F0\nmulsd xmm0, xmm1\nmovapd xmm1, xmm0\nmulsd xmm1, [rbp+var_18]\nmovsd xmm0, [rbp+var_10]\nmulsd xmm0, xmm0\nsubsd xmm1, xmm0\nmovsd xmm0, cs:qword_20F8\naddsd xmm0, xmm1\nmovsd xmm2, [rbp+var_8]\nmovsd xmm1, cs:qword_20F0\nmulsd xmm1, xmm2\ndivsd xmm0, xmm1\nmovsd cs:qword_4028, xmm0\nlea rax, focus_1\npop rbp\nretn", + "ida_pseudo": "__int64 *__fastcall func0(double a1, double a2, double a3)\n{\n *(double *)&focus_1 = -a2 / (a1 + a1);\n *(double *)&qword_4028 = (4.0 * a1 * a3 - a2 * a2 + 1.0) / (4.0 * a1);\n return &focus_1;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmovsd [rbp+var_8], xmm0\nmovsd [rbp+var_10], xmm1\nmovsd [rbp+var_18], xmm2\nmovsd xmm0, [rbp+var_10]\nmovq xmm1, cs:qword_20E0\nxorpd xmm1, xmm0\nmovsd xmm0, [rbp+var_8]\nmovapd xmm2, xmm0\naddsd xmm2, xmm0\ndivsd xmm1, xmm2\nmovapd xmm0, xmm1\nmovsd cs:qword_4020, xmm0\nmovsd xmm1, [rbp+var_8]\nmovsd xmm0, cs:qword_20F0\nmulsd xmm0, xmm1\nmovapd xmm1, xmm0\nmulsd xmm1, [rbp+var_18]\nmovsd xmm0, [rbp+var_10]\nmulsd xmm0, xmm0\nsubsd xmm1, xmm0\nmovsd xmm0, cs:qword_20F8\naddsd xmm0, xmm1\nmovsd xmm2, [rbp+var_8]\nmovsd xmm1, cs:qword_20F0\nmulsd xmm1, xmm2\ndivsd xmm0, xmm1\nmovsd cs:qword_4028, xmm0\nlea rax, qword_4020\npop rbp\nretn", + "ida_strip_pseudo": "__int64 *__fastcall sub_1169(double a1, double a2, double a3)\n{\n *(double *)&qword_4020 = -a2 / (a1 + a1);\n *(double *)&qword_4028 = (4.0 * a1 * a3 - a2 * a2 + 1.0) / (4.0 * a1);\n return &qword_4020;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long *sub_1169(double a1, double a2, double a3) {\n *(double *)&qword_4020 = -a2 / (a1 + a1);\n *(double *)&qword_4028 = (4.0 * a1 * a3 - a2 * a2 + 1.0) / (4.0 * a1);\n return &qword_4020;\n}", + "ida_pseudo_norm": "long long *func0(double a1, double a2, double a3) {\n *(double *)&focus_1 = -a2 / (a1 + a1);\n *(double *)&qword_4028 = (4.0 * a1 * a3 - a2 * a2 + 1.0) / (4.0 * a1);\n return &focus_1;\n}" + }, + { + "index": 186, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char *func0(const char *text, const char *pattern) {\n regex_t regex;\n int reti;\n reti = regcomp(®ex, pattern, 0);\n if (reti) {\n return (\"Regex compilation failed!\");\n }\n reti = regexec(®ex, text, 0, NULL, 0);\n regfree(®ex);\n if (!reti) {\n return (\"Matched!\");\n }\n else {\n return (\"Not Matched!\");\n }\n}", + "test": "int main() {\n\n // Test the function implementation\n\n assert(strcmp(func0(\"The quick brown fox jumps over the lazy dog.\", \"fox\"), \"Matched!\") == 0);\n\n assert(strcmp(func0(\"The quick brown fox jumps over the lazy dog.\", \"horse\"), \"Not Matched!\") == 0);\n\n assert(strcmp(func0(\"The quick brown fox jumps over the lazy dog.\", \"lazy\"), \"Matched!\") == 0);\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x70,%rsp\nmov %rdi,-0x68(%rbp)\nmov %rsi,-0x70(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmov -0x70(%rbp),%rcx\nlea -0x50(%rbp),%rax\nmov $0x0,%edx\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 10f0 \nmov %eax,-0x54(%rbp)\ncmpl $0x0,-0x54(%rbp)\nje 1256 \nlea 0xdb4(%rip),%rax\njmp 129b \nmov -0x68(%rbp),%rsi\nlea -0x50(%rbp),%rax\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rax,%rdi\ncallq 1110 \nmov %eax,-0x54(%rbp)\nlea -0x50(%rbp),%rax\nmov %rax,%rdi\ncallq 10c0 \ncmpl $0x0,-0x54(%rbp)\njne 1294 \nlea 0xd90(%rip),%rax\njmp 129b \nlea 0xd90(%rip),%rax\nmov -0x8(%rbp),%rdx\nxor %fs:0x28,%rdx\nje 12af \ncallq 10d0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov [rbp+pattern], rsi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 0; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+var_54], eax\ncmp [rbp+var_54], 0\njz short loc_1256\nlea rax, aRegexCompilati; \"Regex compilation failed!\"\njmp short loc_129B\nloc_1256:\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_54], eax\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\ncmp [rbp+var_54], 0\njnz short loc_1294\nlea rax, s2; \"Matched!\"\njmp short loc_129B\nloc_1294:\nlea rax, aNotMatched; \"Not Matched!\"\nloc_129B:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12AF\ncall ___stack_chk_fail\nlocret_12AF:\nleave\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1, const char *a2)\n{\n int v3; // [rsp+1Ch] [rbp-54h]\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n unsigned __int64 v5; // [rsp+68h] [rbp-8h]\n\n v5 = __readfsqword(0x28u);\n if ( regcomp(&preg, a2, 0) )\n return \"Regex compilation failed!\";\n v3 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if ( v3 )\n return \"Not Matched!\";\n else\n return \"Matched!\";\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov [rbp+pattern], rsi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 0; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+var_54], eax\ncmp [rbp+var_54], 0\njz short loc_1256\nlea rax, aRegexCompilati; \"Regex compilation failed!\"\njmp short loc_129B\nloc_1256:\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_54], eax\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\ncmp [rbp+var_54], 0\njnz short loc_1294\nlea rax, s2; \"Matched!\"\njmp short loc_129B\nloc_1294:\nlea rax, aNotMatched; \"Not Matched!\"\nloc_129B:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12AF\ncall ___stack_chk_fail\nlocret_12AF:\nleave\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1209(const char *a1, const char *a2)\n{\n int v3; // [rsp+1Ch] [rbp-54h]\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n unsigned __int64 v5; // [rsp+68h] [rbp-8h]\n\n v5 = __readfsqword(0x28u);\n if ( regcomp(&preg, a2, 0) )\n return \"Regex compilation failed!\";\n v3 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if ( v3 )\n return \"Not Matched!\";\n else\n return \"Matched!\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1209(const char *a1, const char *a2) {\n int v3;\n regex_t preg;\n unsigned long long v5;\n v5 = __readfsqword(40u);\n if (regcomp(&preg, a2, 0)) return \"Regex compilation failed!\";\n v3 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if (v3)\n return \"Not Matched!\";\n else\n return \"Matched!\";\n}", + "ida_pseudo_norm": "const char *func0(const char *a1, const char *a2) {\n int v3;\n regex_t preg;\n unsigned long long v5;\n v5 = __readfsqword(40u);\n if (regcomp(&preg, a2, 0)) return \"Regex compilation failed!\";\n v3 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if (v3)\n return \"Not Matched!\";\n else\n return \"Matched!\";\n}" + }, + { + "index": 186, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char *func0(const char *text, const char *pattern) {\n regex_t regex;\n int reti;\n reti = regcomp(®ex, pattern, 0);\n if (reti) {\n return (\"Regex compilation failed!\");\n }\n reti = regexec(®ex, text, 0, NULL, 0);\n regfree(®ex);\n if (!reti) {\n return (\"Matched!\");\n }\n else {\n return (\"Not Matched!\");\n }\n}", + "test": "int main() {\n\n // Test the function implementation\n\n assert(strcmp(func0(\"The quick brown fox jumps over the lazy dog.\", \"fox\"), \"Matched!\") == 0);\n\n assert(strcmp(func0(\"The quick brown fox jumps over the lazy dog.\", \"horse\"), \"Not Matched!\") == 0);\n\n assert(strcmp(func0(\"The quick brown fox jumps over the lazy dog.\", \"lazy\"), \"Matched!\") == 0);\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x58,%rsp\nmov %rdi,%rbx\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nmov $0x0,%edx\ncallq 10e0 \nmov %eax,%edx\nlea 0xde8(%rip),%rax\ntest %edx,%edx\nje 1237 \nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 1275 \nadd $0x58,%rsp\npop %rbx\npop %rbp\nretq\nmov %rsp,%rbp\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rbx,%rsi\nmov %rbp,%rdi\ncallq 10f0 \nmov %eax,%ebx\nmov %rbp,%rdi\ncallq 10b0 \ntest %ebx,%ebx\nlea 0xdba(%rip),%rax\nlea 0xdaf(%rip),%rdx\ncmovne %rdx,%rax\njmp 1220 \ncallq 10c0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+68h+var_20], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 0; cflags\ncall _regcomp\nmov edx, eax\nlea rax, aRegexCompilati; \"Regex compilation failed!\"\ntest edx, edx\njz short loc_1257\nloc_1240:\nmov rdx, [rsp+68h+var_20]\nsub rdx, fs:28h\njnz short loc_1295\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1257:\nmov rbp, rsp\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov ebx, eax\nmov rdi, rbp; preg\ncall _regfree\ntest ebx, ebx\nlea rax, s2; \"Not Matched!\"\nlea rdx, s2+4; \"Matched!\"\ncmovz rax, rdx\njmp short loc_1240\nloc_1295:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string, const char *a2)\n{\n int v2; // edx\n const char *result; // rax\n int v4; // ebx\n regex_t v5; // [rsp+0h] [rbp-68h] BYREF\n unsigned __int64 v6; // [rsp+48h] [rbp-20h]\n\n v6 = __readfsqword(0x28u);\n v2 = regcomp(&v5, a2, 0);\n result = \"Regex compilation failed!\";\n if ( !v2 )\n {\n v4 = regexec(&v5, string, 0LL, 0LL, 0);\n regfree(&v5);\n result = \"Not Matched!\";\n if ( !v4 )\n return \"Matched!\";\n }\n return result;\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+68h+var_20], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 0; cflags\ncall _regcomp\nmov edx, eax\nlea rax, aRegexCompilati; \"Regex compilation failed!\"\ntest edx, edx\njz short loc_1257\nloc_1240:\nmov rdx, [rsp+68h+var_20]\nsub rdx, fs:28h\njnz short loc_1295\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1257:\nmov rbp, rsp\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov ebx, eax\nmov rdi, rbp; preg\ncall _regfree\ntest ebx, ebx\nlea rax, s2; \"Not Matched!\"\nlea rdx, s2+4; \"Matched!\"\ncmovz rax, rdx\njmp short loc_1240\nloc_1295:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_1209(char *string, const char *a2)\n{\n int v2; // edx\n const char *result; // rax\n int v4; // ebx\n regex_t v5; // [rsp+0h] [rbp-68h] BYREF\n unsigned __int64 v6; // [rsp+48h] [rbp-20h]\n\n v6 = __readfsqword(0x28u);\n v2 = regcomp(&v5, a2, 0);\n result = \"Regex compilation failed!\";\n if ( !v2 )\n {\n v4 = regexec(&v5, string, 0LL, 0LL, 0);\n regfree(&v5);\n result = \"Not Matched!\";\n if ( !v4 )\n return \"Matched!\";\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1209(char *string, const char *a2) {\n int v2;\n const char *result;\n int v4;\n regex_t v5;\n unsigned long long v6;\n v6 = __readfsqword(40u);\n v2 = regcomp(&v5, a2, 0);\n result = \"Regex compilation failed!\";\n if (!v2) {\n v4 = regexec(&v5, string, 0LL, 0LL, 0);\n regfree(&v5);\n result = \"Not Matched!\";\n if (!v4) return \"Matched!\";\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string, const char *a2) {\n int v2;\n const char *result;\n int v4;\n regex_t v5;\n unsigned long long v6;\n v6 = __readfsqword(40u);\n v2 = regcomp(&v5, a2, 0);\n result = \"Regex compilation failed!\";\n if (!v2) {\n v4 = regexec(&v5, string, 0LL, 0LL, 0);\n regfree(&v5);\n result = \"Not Matched!\";\n if (!v4) return \"Matched!\";\n }\n return result;\n}" + }, + { + "index": 186, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char *func0(const char *text, const char *pattern) {\n regex_t regex;\n int reti;\n reti = regcomp(®ex, pattern, 0);\n if (reti) {\n return (\"Regex compilation failed!\");\n }\n reti = regexec(®ex, text, 0, NULL, 0);\n regfree(®ex);\n if (!reti) {\n return (\"Matched!\");\n }\n else {\n return (\"Not Matched!\");\n }\n}", + "test": "int main() {\n\n // Test the function implementation\n\n assert(strcmp(func0(\"The quick brown fox jumps over the lazy dog.\", \"fox\"), \"Matched!\") == 0);\n\n assert(strcmp(func0(\"The quick brown fox jumps over the lazy dog.\", \"horse\"), \"Not Matched!\") == 0);\n\n assert(strcmp(func0(\"The quick brown fox jumps over the lazy dog.\", \"lazy\"), \"Matched!\") == 0);\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nxor %edx,%edx\npush %rbp\nmov %rdi,%rbp\nsub $0x58,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%r12\nmov %r12,%rdi\ncallq 10e0 \nmov %eax,%r8d\nlea 0xcdf(%rip),%rax\ntest %r8d,%r8d\njne 1357 \nxor %edx,%edx\nxor %ecx,%ecx\nmov %rbp,%rsi\nmov %r12,%rdi\ncallq 10f0 \nmov %r12,%rdi\nmov %eax,%ebp\ncallq 10b0 \ntest %ebp,%ebp\nlea 0xcd6(%rip),%rax\nlea 0xccb(%rip),%rdx\ncmovne %rdx,%rax\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 136f \nadd $0x58,%rsp\npop %rbp\npop %r12\nretq\ncallq 10c0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\nxor edx, edx; cflags\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nmov edx, eax\nlea rax, aRegexCompilati; \"Regex compilation failed!\"\ntest edx, edx\njnz short loc_1367\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, s2; \"Not Matched!\"\nlea rdx, s2+4; \"Matched!\"\ncmovz rax, rdx\nloc_1367:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_137E\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_137E:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string, const char *a2)\n{\n int v2; // edx\n const char *result; // rax\n int v4; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n v2 = regcomp(&_0, a2, 0);\n result = \"Regex compilation failed!\";\n if ( !v2 )\n {\n v4 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not Matched!\";\n if ( !v4 )\n return \"Matched!\";\n }\n return result;\n}", + "ida_strip_asm": "sub_1300:\nendbr64\npush rbp\nxor edx, edx; cflags\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nmov edx, eax\nlea rax, aRegexCompilati; \"Regex compilation failed!\"\ntest edx, edx\njnz short loc_1367\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, s2; \"Not Matched!\"\nlea rdx, s2+4; \"Matched!\"\ncmovz rax, rdx\nloc_1367:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_137E\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_137E:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_1300(char *string, const char *a2)\n{\n int v2; // edx\n const char *result; // rax\n int v4; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n v2 = regcomp(&_0, a2, 0);\n result = \"Regex compilation failed!\";\n if ( !v2 )\n {\n v4 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not Matched!\";\n if ( !v4 )\n return \"Matched!\";\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1300(char *string, const char *a2) {\n int v2;\n const char *result;\n int v4;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n v2 = regcomp(&_0, a2, 0);\n result = \"Regex compilation failed!\";\n if (!v2) {\n v4 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not Matched!\";\n if (!v4) return \"Matched!\";\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string, const char *a2) {\n int v2;\n const char *result;\n int v4;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n v2 = regcomp(&_0, a2, 0);\n result = \"Regex compilation failed!\";\n if (!v2) {\n v4 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not Matched!\";\n if (!v4) return \"Matched!\";\n }\n return result;\n}" + }, + { + "index": 186, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char *func0(const char *text, const char *pattern) {\n regex_t regex;\n int reti;\n reti = regcomp(®ex, pattern, 0);\n if (reti) {\n return (\"Regex compilation failed!\");\n }\n reti = regexec(®ex, text, 0, NULL, 0);\n regfree(®ex);\n if (!reti) {\n return (\"Matched!\");\n }\n else {\n return (\"Not Matched!\");\n }\n}", + "test": "int main() {\n\n // Test the function implementation\n\n assert(strcmp(func0(\"The quick brown fox jumps over the lazy dog.\", \"fox\"), \"Matched!\") == 0);\n\n assert(strcmp(func0(\"The quick brown fox jumps over the lazy dog.\", \"horse\"), \"Not Matched!\") == 0);\n\n assert(strcmp(func0(\"The quick brown fox jumps over the lazy dog.\", \"lazy\"), \"Matched!\") == 0);\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nxor %edx,%edx\npush %rbp\nmov %rdi,%rbp\nsub $0x58,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%r12\nmov %r12,%rdi\ncallq 10e0 \nmov %eax,%r8d\nlea 0xcdf(%rip),%rax\ntest %r8d,%r8d\njne 1357 \nxor %edx,%edx\nxor %ecx,%ecx\nmov %rbp,%rsi\nmov %r12,%rdi\ncallq 10f0 \nmov %r12,%rdi\nmov %eax,%ebp\ncallq 10b0 \ntest %ebp,%ebp\nlea 0xcd6(%rip),%rax\nlea 0xccb(%rip),%rdx\ncmovne %rdx,%rax\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 136f \nadd $0x58,%rsp\npop %rbp\npop %r12\nretq\ncallq 10c0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\nxor edx, edx; cflags\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nmov edx, eax\nlea rax, aRegexCompilati; \"Regex compilation failed!\"\ntest edx, edx\njnz short loc_1367\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, s2; \"Not Matched!\"\nlea rdx, s2+4; \"Matched!\"\ncmovz rax, rdx\nloc_1367:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_137E\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_137E:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string, const char *a2)\n{\n int v2; // edx\n const char *result; // rax\n int v4; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n v2 = regcomp(&_0, a2, 0);\n result = \"Regex compilation failed!\";\n if ( !v2 )\n {\n v4 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not Matched!\";\n if ( !v4 )\n return \"Matched!\";\n }\n return result;\n}", + "ida_strip_asm": "sub_1300:\nendbr64\npush rbp\nxor edx, edx; cflags\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nmov edx, eax\nlea rax, aRegexCompilati; \"Regex compilation failed!\"\ntest edx, edx\njnz short loc_1367\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, s2; \"Not Matched!\"\nlea rdx, s2+4; \"Matched!\"\ncmovz rax, rdx\nloc_1367:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_137E\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_137E:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_1300(char *string, const char *a2)\n{\n int v2; // edx\n const char *result; // rax\n int v4; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n v2 = regcomp(&_0, a2, 0);\n result = \"Regex compilation failed!\";\n if ( !v2 )\n {\n v4 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not Matched!\";\n if ( !v4 )\n return \"Matched!\";\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1300(char *string, const char *a2) {\n int v2;\n const char *result;\n int v4;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n v2 = regcomp(&_0, a2, 0);\n result = \"Regex compilation failed!\";\n if (!v2) {\n v4 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not Matched!\";\n if (!v4) return \"Matched!\";\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string, const char *a2) {\n int v2;\n const char *result;\n int v4;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n v2 = regcomp(&_0, a2, 0);\n result = \"Regex compilation failed!\";\n if (!v2) {\n v4 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not Matched!\";\n if (!v4) return \"Matched!\";\n }\n return result;\n}" + }, + { + "index": 187, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *X, const char *Y, int m, int n) {\n if (m == 0 || n == 0) {\n return 0;\n } else if (X[m - 1] == Y[n - 1]) {\n return 1 + func0(X, Y, m - 1, n - 1);\n } else {\n int left = func0(X, Y, m, n - 1);\n int right = func0(X, Y, m - 1, n);\n return (left > right) ? left : right;\n }\n}", + "test": "int main() {\n\n assert(func0(\"AGGTAB\", \"GXTXAYB\", 6, 7) == 4);\n\n assert(func0(\"ABCDGH\", \"AEDFHR\", 6, 6) == 3);\n\n assert(func0(\"AXYT\", \"AYZX\", 4, 4) == 2);\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %edx,-0x24(%rbp)\nmov %ecx,-0x28(%rbp)\ncmpl $0x0,-0x24(%rbp)\nje 118f \ncmpl $0x0,-0x28(%rbp)\njne 1199 \nmov $0x0,%eax\njmpq 122a \nmov -0x24(%rbp),%eax\ncltq\nlea -0x1(%rax),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%edx\nmov -0x28(%rbp),%eax\ncltq\nlea -0x1(%rax),%rcx\nmov -0x20(%rbp),%rax\nadd %rcx,%rax\nmovzbl (%rax),%eax\ncmp %al,%dl\njne 11e4 \nmov -0x28(%rbp),%eax\nlea -0x1(%rax),%ecx\nmov -0x24(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x20(%rbp),%rsi\nmov -0x18(%rbp),%rax\nmov %rax,%rdi\ncallq 1169 \nadd $0x1,%eax\njmp 122a \nmov -0x28(%rbp),%eax\nlea -0x1(%rax),%ecx\nmov -0x24(%rbp),%edx\nmov -0x20(%rbp),%rsi\nmov -0x18(%rbp),%rax\nmov %rax,%rdi\ncallq 1169 \nmov %eax,-0x8(%rbp)\nmov -0x24(%rbp),%eax\nlea -0x1(%rax),%edi\nmov -0x28(%rbp),%edx\nmov -0x20(%rbp),%rsi\nmov -0x18(%rbp),%rax\nmov %edx,%ecx\nmov %edi,%edx\nmov %rax,%rdi\ncallq 1169 \nmov %eax,-0x4(%rbp)\nmov -0x8(%rbp),%eax\ncmp %eax,-0x4(%rbp)\ncmovge -0x4(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_28], ecx\ncmp [rbp+var_24], 0\njz short loc_118F\ncmp [rbp+var_28], 0\njnz short loc_1199\nloc_118F:\nmov eax, 0\njmp locret_122B\nloc_1199:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_28]\ncdqe\nlea rcx, [rax-1]\nmov rax, [rbp+var_20]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njnz short loc_11E4\nmov eax, [rbp+var_28]\nlea ecx, [rax-1]\nmov eax, [rbp+var_24]\nlea edx, [rax-1]\nmov rsi, [rbp+var_20]\nmov rax, [rbp+var_18]\nmov rdi, rax\ncall func0\nadd eax, 1\njmp short locret_122B\nloc_11E4:\nmov eax, [rbp+var_28]\nlea ecx, [rax-1]\nmov edx, [rbp+var_24]\nmov rsi, [rbp+var_20]\nmov rax, [rbp+var_18]\nmov rdi, rax\ncall func0\nmov [rbp+var_8], eax\nmov eax, [rbp+var_24]\nlea edi, [rax-1]\nmov edx, [rbp+var_28]\nmov rsi, [rbp+var_20]\nmov rax, [rbp+var_18]\nmov ecx, edx\nmov edx, edi\nmov rdi, rax\ncall func0\nmov [rbp+var_4], eax\nmov edx, [rbp+var_4]\nmov eax, [rbp+var_8]\ncmp edx, eax\ncmovge eax, edx\nlocret_122B:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, unsigned int a3, unsigned int a4)\n{\n __int64 result; // rax\n unsigned int v5; // edx\n unsigned int v8; // [rsp+28h] [rbp-8h]\n\n if ( !a3 || !a4 )\n return 0LL;\n if ( *(_BYTE *)((int)a3 - 1LL + a1) == *(_BYTE *)((int)a4 - 1LL + a2) )\n return (unsigned int)func0(a1, a2, a3 - 1, a4 - 1) + 1;\n v8 = func0(a1, a2, a3, a4 - 1);\n v5 = func0(a1, a2, a3 - 1, a4);\n result = v8;\n if ( (int)v5 >= (int)v8 )\n return v5;\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_28], ecx\ncmp [rbp+var_24], 0\njz short loc_118F\ncmp [rbp+var_28], 0\njnz short loc_1199\nloc_118F:\nmov eax, 0\njmp locret_122B\nloc_1199:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_28]\ncdqe\nlea rcx, [rax-1]\nmov rax, [rbp+var_20]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njnz short loc_11E4\nmov eax, [rbp+var_28]\nlea ecx, [rax-1]\nmov eax, [rbp+var_24]\nlea edx, [rax-1]\nmov rsi, [rbp+var_20]\nmov rax, [rbp+var_18]\nmov rdi, rax\ncall sub_1169\nadd eax, 1\njmp short locret_122B\nloc_11E4:\nmov eax, [rbp+var_28]\nlea ecx, [rax-1]\nmov edx, [rbp+var_24]\nmov rsi, [rbp+var_20]\nmov rax, [rbp+var_18]\nmov rdi, rax\ncall sub_1169\nmov [rbp+var_8], eax\nmov eax, [rbp+var_24]\nlea edi, [rax-1]\nmov edx, [rbp+var_28]\nmov rsi, [rbp+var_20]\nmov rax, [rbp+var_18]\nmov ecx, edx\nmov edx, edi\nmov rdi, rax\ncall sub_1169\nmov [rbp+var_4], eax\nmov edx, [rbp+var_4]\nmov eax, [rbp+var_8]\ncmp edx, eax\ncmovge eax, edx\nlocret_122B:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, unsigned int a3, unsigned int a4)\n{\n __int64 result; // rax\n unsigned int v5; // edx\n unsigned int v8; // [rsp+28h] [rbp-8h]\n\n if ( !a3 || !a4 )\n return 0LL;\n if ( *(_BYTE *)((int)a3 - 1LL + a1) == *(_BYTE *)((int)a4 - 1LL + a2) )\n return (unsigned int)sub_1169(a1, a2, a3 - 1, a4 - 1) + 1;\n v8 = sub_1169(a1, a2, a3, a4 - 1);\n v5 = sub_1169(a1, a2, a3 - 1, a4);\n result = v8;\n if ( (int)v5 >= (int)v8 )\n return v5;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, unsigned int a3,\n unsigned int a4) {\n long long result;\n unsigned int v5;\n unsigned int v8;\n if (!a3 || !a4) return 0LL;\n if (*(uint8_t *)((int)a3 - 1LL + a1) == *(uint8_t *)((int)a4 - 1LL + a2))\n return (unsigned int)sub_1169(a1, a2, a3 - 1, a4 - 1) + 1;\n v8 = sub_1169(a1, a2, a3, a4 - 1);\n v5 = sub_1169(a1, a2, a3 - 1, a4);\n result = v8;\n if ((int)v5 >= (int)v8) return v5;\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, unsigned int a3, unsigned int a4) {\n long long result;\n unsigned int v5;\n unsigned int v8;\n if (!a3 || !a4) return 0LL;\n if (*(uint8_t *)((int)a3 - 1LL + a1) == *(uint8_t *)((int)a4 - 1LL + a2))\n return (unsigned int)func0(a1, a2, a3 - 1, a4 - 1) + 1;\n v8 = func0(a1, a2, a3, a4 - 1);\n v5 = func0(a1, a2, a3 - 1, a4);\n result = v8;\n if ((int)v5 >= (int)v8) return v5;\n return result;\n}" + }, + { + "index": 187, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *X, const char *Y, int m, int n) {\n if (m == 0 || n == 0) {\n return 0;\n } else if (X[m - 1] == Y[n - 1]) {\n return 1 + func0(X, Y, m - 1, n - 1);\n } else {\n int left = func0(X, Y, m, n - 1);\n int right = func0(X, Y, m - 1, n);\n return (left > right) ? left : right;\n }\n}", + "test": "int main() {\n\n assert(func0(\"AGGTAB\", \"GXTXAYB\", 6, 7) == 4);\n\n assert(func0(\"ABCDGH\", \"AEDFHR\", 6, 6) == 3);\n\n assert(func0(\"AXYT\", \"AYZX\", 4, 4) == 2);\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edx,%edx\nje 11e3 \npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%r12\nmov %rsi,%r13\nmov %edx,%ebx\nmov %ecx,%ebp\ntest %ecx,%ecx\nje 11dc \nmovslq %edx,%rax\nmovslq %ecx,%rdx\nmovzbl -0x1(%rsi,%rdx,1),%esi\ncmp %sil,-0x1(%rdi,%rax,1)\nje 11c9 \nlea -0x1(%rcx),%ecx\nmov %ebx,%edx\nmov %r13,%rsi\ncallq 1169 \nmov %eax,%r14d\nlea -0x1(%rbx),%edx\nmov %ebp,%ecx\nmov %r13,%rsi\nmov %r12,%rdi\ncallq 1169 \ncmp %eax,%r14d\ncmovge %r14d,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nlea -0x1(%rcx),%ecx\nlea -0x1(%rbx),%edx\nmov %r13,%rsi\ncallq 1169 \nadd $0x1,%eax\njmp 11c0 \nmov $0x0,%eax\njmp 11c0 \nmov $0x0,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest edx, edx\njz short loc_11E3\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r12, rdi\nmov r13, rsi\nmov ebx, edx\nmov ebp, ecx\ntest ecx, ecx\njz short loc_11DC\nmovsxd rax, edx\nmovsxd rdx, ecx\nmovzx esi, byte ptr [rsi+rdx-1]\ncmp [rdi+rax-1], sil\njz short loc_11C9\nlea ecx, [rcx-1]\nmov edx, ebx\nmov rsi, r13\ncall func0\nmov r14d, eax\nlea edx, [rbx-1]\nmov ecx, ebp\nmov rsi, r13\nmov rdi, r12\ncall func0\ncmp r14d, eax\ncmovge eax, r14d\nloc_11C0:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_11C9:\nlea ecx, [rcx-1]\nlea edx, [rbx-1]\nmov rsi, r13\ncall func0\nadd eax, 1\njmp short loc_11C0\nloc_11DC:\nmov eax, 0\njmp short loc_11C0\nloc_11E3:\nmov eax, 0\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, unsigned int a3, unsigned int a4)\n{\n int v6; // r14d\n __int64 result; // rax\n\n if ( !a3 )\n return 0LL;\n if ( !a4 )\n return 0LL;\n if ( *(_BYTE *)(a1 + (int)a3 - 1) == *(_BYTE *)(a2 + (int)a4 - 1) )\n return (unsigned int)func0(a1, a2, a3 - 1, a4 - 1) + 1;\n v6 = func0(a1, a2, a3, a4 - 1);\n result = func0(a1, a2, a3 - 1, a4);\n if ( v6 >= (int)result )\n return (unsigned int)v6;\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest edx, edx\njz short loc_11E3\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r12, rdi\nmov r13, rsi\nmov ebx, edx\nmov ebp, ecx\ntest ecx, ecx\njz short loc_11DC\nmovsxd rax, edx\nmovsxd rdx, ecx\nmovzx esi, byte ptr [rsi+rdx-1]\ncmp [rdi+rax-1], sil\njz short loc_11C9\nlea ecx, [rcx-1]\nmov edx, ebx\nmov rsi, r13\ncall sub_1169\nmov r14d, eax\nlea edx, [rbx-1]\nmov ecx, ebp\nmov rsi, r13\nmov rdi, r12\ncall sub_1169\ncmp r14d, eax\ncmovge eax, r14d\nloc_11C0:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_11C9:\nlea ecx, [rcx-1]\nlea edx, [rbx-1]\nmov rsi, r13\ncall sub_1169\nadd eax, 1\njmp short loc_11C0\nloc_11DC:\nmov eax, 0\njmp short loc_11C0\nloc_11E3:\nmov eax, 0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, unsigned int a3, unsigned int a4)\n{\n int v6; // r14d\n __int64 result; // rax\n\n if ( !a3 )\n return 0LL;\n if ( !a4 )\n return 0LL;\n if ( *(_BYTE *)(a1 + (int)a3 - 1) == *(_BYTE *)(a2 + (int)a4 - 1) )\n return (unsigned int)sub_1169(a1, a2, a3 - 1, a4 - 1) + 1;\n v6 = sub_1169(a1, a2, a3, a4 - 1);\n result = sub_1169(a1, a2, a3 - 1, a4);\n if ( v6 >= (int)result )\n return (unsigned int)v6;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, unsigned int a3,\n unsigned int a4) {\n int v6;\n long long result;\n if (!a3) return 0LL;\n if (!a4) return 0LL;\n if (*(uint8_t *)(a1 + (int)a3 - 1) == *(uint8_t *)(a2 + (int)a4 - 1))\n return (unsigned int)sub_1169(a1, a2, a3 - 1, a4 - 1) + 1;\n v6 = sub_1169(a1, a2, a3, a4 - 1);\n result = sub_1169(a1, a2, a3 - 1, a4);\n if (v6 >= (int)result) return (unsigned int)v6;\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, unsigned int a3, unsigned int a4) {\n int v6;\n long long result;\n if (!a3) return 0LL;\n if (!a4) return 0LL;\n if (*(uint8_t *)(a1 + (int)a3 - 1) == *(uint8_t *)(a2 + (int)a4 - 1))\n return (unsigned int)func0(a1, a2, a3 - 1, a4 - 1) + 1;\n v6 = func0(a1, a2, a3, a4 - 1);\n result = func0(a1, a2, a3 - 1, a4);\n if (v6 >= (int)result) return (unsigned int)v6;\n return result;\n}" + }, + { + "index": 187, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *X, const char *Y, int m, int n) {\n if (m == 0 || n == 0) {\n return 0;\n } else if (X[m - 1] == Y[n - 1]) {\n return 1 + func0(X, Y, m - 1, n - 1);\n } else {\n int left = func0(X, Y, m, n - 1);\n int right = func0(X, Y, m - 1, n);\n return (left > right) ? left : right;\n }\n}", + "test": "int main() {\n\n assert(func0(\"AGGTAB\", \"GXTXAYB\", 6, 7) == 4);\n\n assert(func0(\"ABCDGH\", \"AEDFHR\", 6, 6) == 3);\n\n assert(func0(\"AXYT\", \"AYZX\", 4, 4) == 2);\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmovslq %ecx,%rax\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\ntest %eax,%eax\nje 12fd \nmov %edx,%r12d\ntest %edx,%edx\nje 12fd \nmovslq %edx,%r8\nlea -0x1(%rax),%ecx\nmov %rdi,%r14\nmov %rsi,%rbp\nsub %rax,%r8\nmovslq %ecx,%rcx\nxor %r13d,%r13d\nadd %rdi,%r8\njmp 12af \nnopw 0x0(%rax,%rax,1)\nadd $0x1,%r13d\ntest %r12d,%r12d\nsete %dl\ntest %ecx,%ecx\nsete %al\nsub $0x1,%rcx\nor %al,%dl\njne 12eb \nmov %r12d,%edx\nmovzbl 0x0(%rbp,%rcx,1),%eax\nlea 0x1(%rcx),%r15d\nsub $0x1,%r12d\ncmp %al,(%r8,%rcx,1)\nje 1298 \nmov %rbp,%rsi\nmov %r14,%rdi\ncallq 1250 \nmov %r15d,%ecx\nmov %r12d,%edx\nmov %rbp,%rsi\nmov %r14,%rdi\nmov %eax,%ebx\ncallq 1250 \ncmp %eax,%ebx\ncmovl %eax,%ebx\nadd %ebx,%r13d\nadd $0x8,%rsp\nmov %r13d,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nxor %r13d,%r13d\njmp 12eb \nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\ntest ecx, ecx\njz loc_12ED\nmov ebp, edx\ntest edx, edx\njz short loc_12ED\nlea ebx, [rcx-1]\nmovsxd rax, edx\nmovsxd rcx, ecx\nmov r14, rdi\nsub rax, rcx\nmov r13, rsi\nmovsxd rbx, ebx\nxor r12d, r12d\nadd rax, rdi\njmp short loc_12A0\nloc_1290:\nadd r12d, 1\nsub rbx, 1\ntest ebp, ebp\njz short loc_12DB\ntest ecx, ecx\njz short loc_12DB\nloc_12A0:\nmov edx, ebp\nmovzx esi, byte ptr [r13+rbx+0]\nmov ecx, ebx\nsub ebp, 1\ncmp [rax+rbx], sil\njz short loc_1290\nmov rsi, r13\nmov rdi, r14\ncall func0\nlea ecx, [rbx+1]\nmov edx, ebp\nmov rsi, r13\nmov rdi, r14\nmov r15d, eax\ncall func0\ncmp r15d, eax\ncmovl r15d, eax\nadd r12d, r15d\nloc_12DB:\nadd rsp, 8\nmov eax, r12d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_12ED:\nxor r12d, r12d\njmp short loc_12DB", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, unsigned int a3, int a4)\n{\n unsigned int v4; // ebp\n __int64 v5; // rbx\n unsigned int v6; // r12d\n __int64 v7; // rax\n __int64 v8; // rdx\n int v9; // ecx\n int v10; // r15d\n int v11; // eax\n\n if ( a4 && (v4 = a3) != 0 )\n {\n v5 = a4 - 1;\n v6 = 0;\n v7 = a1 + (int)a3 - (__int64)a4;\n while ( 1 )\n {\n v8 = v4;\n v9 = v5;\n --v4;\n if ( *(_BYTE *)(v7 + v5) != *(_BYTE *)(a2 + v5) )\n break;\n ++v6;\n --v5;\n if ( !v4 || !v9 )\n return v6;\n }\n v10 = func0(a1, a2, v8, (unsigned int)v5);\n v11 = func0(a1, a2, v4, (unsigned int)(v5 + 1));\n if ( v10 < v11 )\n v10 = v11;\n v6 += v10;\n }\n else\n {\n return 0;\n }\n return v6;\n}", + "ida_strip_asm": "sub_1250:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\ntest ecx, ecx\njz loc_12ED\nmov ebp, edx\ntest edx, edx\njz short loc_12ED\nlea ebx, [rcx-1]\nmovsxd rax, edx\nmovsxd rcx, ecx\nmov r14, rdi\nsub rax, rcx\nmov r13, rsi\nmovsxd rbx, ebx\nxor r12d, r12d\nadd rax, rdi\njmp short loc_12A0\nloc_1290:\nadd r12d, 1\nsub rbx, 1\ntest ebp, ebp\njz short loc_12DB\ntest ecx, ecx\njz short loc_12DB\nloc_12A0:\nmov edx, ebp\nmovzx esi, byte ptr [r13+rbx+0]\nmov ecx, ebx\nsub ebp, 1\ncmp [rax+rbx], sil\njz short loc_1290\nmov rsi, r13\nmov rdi, r14\ncall sub_1250\nlea ecx, [rbx+1]\nmov edx, ebp\nmov rsi, r13\nmov rdi, r14\nmov r15d, eax\ncall sub_1250\ncmp r15d, eax\ncmovl r15d, eax\nadd r12d, r15d\nloc_12DB:\nadd rsp, 8\nmov eax, r12d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_12ED:\nxor r12d, r12d\njmp short loc_12DB", + "ida_strip_pseudo": "__int64 __fastcall sub_1250(__int64 a1, __int64 a2, unsigned int a3, int a4)\n{\n unsigned int v4; // ebp\n __int64 v5; // rbx\n unsigned int v6; // r12d\n __int64 v7; // rax\n __int64 v8; // rdx\n int v9; // ecx\n int v10; // r15d\n int v11; // eax\n\n if ( a4 && (v4 = a3) != 0 )\n {\n v5 = a4 - 1;\n v6 = 0;\n v7 = a1 + (int)a3 - (__int64)a4;\n while ( 1 )\n {\n v8 = v4;\n v9 = v5;\n --v4;\n if ( *(_BYTE *)(v7 + v5) != *(_BYTE *)(a2 + v5) )\n break;\n ++v6;\n --v5;\n if ( !v4 || !v9 )\n return v6;\n }\n v10 = sub_1250(a1, a2, v8, (unsigned int)v5);\n v11 = sub_1250(a1, a2, v4, (unsigned int)(v5 + 1));\n if ( v10 < v11 )\n v10 = v11;\n v6 += v10;\n }\n else\n {\n return 0;\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1250(long long a1, long long a2, unsigned int a3, int a4) {\n unsigned int v4;\n long long v5;\n unsigned int v6;\n long long v7;\n long long v8;\n int v9;\n int v10;\n int v11;\n if (a4 && (v4 = a3) != 0) {\n v5 = a4 - 1;\n v6 = 0;\n v7 = a1 + (int)a3 - (long long)a4;\n while (1) {\n v8 = v4;\n v9 = v5;\n --v4;\n if (*(uint8_t *)(v7 + v5) != *(uint8_t *)(a2 + v5)) break;\n ++v6;\n --v5;\n if (!v4 || !v9) return v6;\n }\n v10 = sub_1250(a1, a2, v8, (unsigned int)v5);\n v11 = sub_1250(a1, a2, v4, (unsigned int)(v5 + 1));\n if (v10 < v11) v10 = v11;\n v6 += v10;\n } else {\n return 0;\n }\n return v6;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, unsigned int a3, int a4) {\n unsigned int v4;\n long long v5;\n unsigned int v6;\n long long v7;\n long long v8;\n int v9;\n int v10;\n int v11;\n if (a4 && (v4 = a3) != 0) {\n v5 = a4 - 1;\n v6 = 0;\n v7 = a1 + (int)a3 - (long long)a4;\n while (1) {\n v8 = v4;\n v9 = v5;\n --v4;\n if (*(uint8_t *)(v7 + v5) != *(uint8_t *)(a2 + v5)) break;\n ++v6;\n --v5;\n if (!v4 || !v9) return v6;\n }\n v10 = func0(a1, a2, v8, (unsigned int)v5);\n v11 = func0(a1, a2, v4, (unsigned int)(v5 + 1));\n if (v10 < v11) v10 = v11;\n v6 += v10;\n } else {\n return 0;\n }\n return v6;\n}" + }, + { + "index": 187, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *X, const char *Y, int m, int n) {\n if (m == 0 || n == 0) {\n return 0;\n } else if (X[m - 1] == Y[n - 1]) {\n return 1 + func0(X, Y, m - 1, n - 1);\n } else {\n int left = func0(X, Y, m, n - 1);\n int right = func0(X, Y, m - 1, n);\n return (left > right) ? left : right;\n }\n}", + "test": "int main() {\n\n assert(func0(\"AGGTAB\", \"GXTXAYB\", 6, 7) == 4);\n\n assert(func0(\"ABCDGH\", \"AEDFHR\", 6, 6) == 3);\n\n assert(func0(\"AXYT\", \"AYZX\", 4, 4) == 2);\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmovslq %ecx,%rax\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\ntest %eax,%eax\nje 12fd \nmov %edx,%r12d\ntest %edx,%edx\nje 12fd \nmovslq %edx,%r8\nlea -0x1(%rax),%ecx\nmov %rdi,%r14\nmov %rsi,%rbp\nsub %rax,%r8\nmovslq %ecx,%rcx\nxor %r13d,%r13d\nadd %rdi,%r8\njmp 12af \nnopw 0x0(%rax,%rax,1)\nadd $0x1,%r13d\ntest %r12d,%r12d\nsete %dl\ntest %ecx,%ecx\nsete %al\nsub $0x1,%rcx\nor %al,%dl\njne 12eb \nmov %r12d,%edx\nmovzbl 0x0(%rbp,%rcx,1),%eax\nlea 0x1(%rcx),%r15d\nsub $0x1,%r12d\ncmp %al,(%r8,%rcx,1)\nje 1298 \nmov %rbp,%rsi\nmov %r14,%rdi\ncallq 1250 \nmov %r15d,%ecx\nmov %r12d,%edx\nmov %rbp,%rsi\nmov %r14,%rdi\nmov %eax,%ebx\ncallq 1250 \ncmp %eax,%ebx\ncmovl %eax,%ebx\nadd %ebx,%r13d\nadd $0x8,%rsp\nmov %r13d,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nxor %r13d,%r13d\njmp 12eb \nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 68h\nmov [rsp+98h+var_98], rdi\ntest edx, edx\njz loc_1B87\ntest ecx, ecx\njz loc_1B87\nmov rax, rdi\nlea ebp, [rcx-1]\nmovsxd rdi, edx\nmovsxd rcx, ecx\nsub rdi, rcx\nmov ebx, edx\nmovsxd rbp, ebp\nxor r13d, r13d\nadd rdi, rax\njmp short loc_12B0\nloc_1298:\nadd r13d, 1\nsub rbp, 1\ntest dl, dl\njnz loc_1B45\ntest cl, cl\njnz loc_1B45\nloc_12B0:\nmov r14d, ebx\nmovzx eax, byte ptr [rdi+rbp]\nsub ebx, 1\nmovzx r12d, byte ptr [rsi+rbp]\nsetz dl\ntest ebp, ebp\nsetz cl\ncmp al, r12b\njz short loc_1298\nmov [rsp+98h+var_8C], ebp\ntest ebp, ebp\njz loc_1BB6\nmovsxd rdx, ebp\nmovsxd rdi, r14d\nxor r9d, r9d\nlea r15d, [rdx-1]\nsub rdi, rdx\nmov rdx, [rsp+98h+var_98]\nmovsxd r15, r15d\nadd rdi, rdx\njmp short loc_1318\nloc_12F8:\nadd r9d, 1\nsub r15, 1\ntest dl, dl\njnz loc_1738\ntest cl, cl\njnz loc_1738\nmovzx eax, byte ptr [rdi+r15]\nmov r14d, r8d\nloc_1318:\nmov r8d, r14d\nmovzx r10d, byte ptr [rsi+r15]\nsub r8d, 1\nsetz dl\ntest r15d, r15d\nsetz cl\ncmp r10b, al\njz short loc_12F8\nmov [rsp+98h+var_90], r9d\nmov dword ptr [rsp+98h+var_80], r15d\ntest r15d, r15d\njz loc_1BD3\nmovsxd rdx, r15d\nmovsxd rdi, r14d\nxor ecx, ecx\nmov dword ptr [rsp+98h+var_78], ebx\nlea r9d, [rdx-1]\nsub rdi, rdx\nmov rdx, [rsp+98h+var_98]\nmov [rsp+98h+var_70], rbp\nmovsxd r9, r9d\nmov ebx, ecx\nadd rdi, rdx\njmp short loc_138F\nloc_1370:\nadd ebx, 1\nsub r9, 1\ntest dl, dl\njnz loc_1B60\ntest cl, cl\njnz loc_1B60\nmovzx eax, byte ptr [rdi+r9]\nmov r14d, r11d\nloc_138F:\nmov r11d, r14d\nsub r11d, 1\nsetz dl\ntest r9d, r9d\nsetz cl\ncmp [rsi+r9], al\njz short loc_1370\nmovsxd rdx, r9d\nmov dword ptr [rsp+98h+var_88], ebx\nmov rbp, [rsp+98h+var_70]\nmov dword ptr [rsp+98h+var_68], r11d\nmov ebx, dword ptr [rsp+98h+var_78]\nmov [rsp+98h+var_50], edx\ntest r9d, r9d\njz loc_1C17\nmovsxd rax, r14d\nlea r11d, [rdx-1]\nmov dword ptr [rsp+98h+var_70], r8d\nxor edi, edi\nsub rax, rdx\nmov rdx, [rsp+98h+var_98]\nmovsxd r11, r11d\nadd rax, rdx\njmp short loc_1400\nloc_13E8:\nadd edi, 1\nsub r11, 1\ntest r14d, r14d\njz loc_1B8C\ntest ecx, ecx\njz loc_1B8C\nloc_1400:\nmov edx, r14d\nmovzx r8d, byte ptr [rsi+r11]\nmov ecx, r11d\nsub r14d, 1\ncmp [rax+r11], r8b\njz short loc_13E8\nmov r8d, dword ptr [rsp+98h+var_70]\nmov dword ptr [rsp+98h+var_78], edi\nmov rdi, [rsp+98h+var_98]\nmov [rsp+98h+var_40], r9\nmov byte ptr [rsp+98h+var_4C], r10b\nmov dword ptr [rsp+98h+var_58], r8d\nmov [rsp+98h+var_48], r11\nmov [rsp+98h+var_60], rsi\ncall func0\nmov r11, [rsp+98h+var_48]\nmov rsi, [rsp+98h+var_60]\nmov edx, r14d\nmov rdi, [rsp+98h+var_98]\nmov dword ptr [rsp+98h+var_70], eax\nlea ecx, [r11+1]\ncall func0\nmov esi, dword ptr [rsp+98h+var_70]\nmov r8d, dword ptr [rsp+98h+var_58]\nmovzx r10d, byte ptr [rsp+98h+var_4C]\nmov r9, [rsp+98h+var_40]\ncmp esi, eax\ncmovge eax, esi\nadd dword ptr [rsp+98h+var_78], eax\nmov rsi, [rsp+98h+var_60]\nloc_1480:\nmov r14d, dword ptr [rsp+98h+var_68]\ntest r14d, r14d\njz loc_1C0F\nlea eax, [r9+1]\nmovsxd rdx, r14d\nmovsxd r11, [rsp+98h+var_50]\nxor r9d, r9d\ncdqe\nsub rdx, rax\nmov rax, [rsp+98h+var_98]\nadd rax, rdx\njmp short loc_14C1\nloc_14B0:\nadd r9d, 1\nsub r11, 1\ntest r14d, r14d\njz short loc_1537\ntest ecx, ecx\njz short loc_1537\nloc_14C1:\nmov edx, r14d\nmovzx edi, byte ptr [rsi+r11]\nmov ecx, r11d\nsub r14d, 1\ncmp [rax+r11], dil\njz short loc_14B0\nmov rdi, [rsp+98h+var_98]\nmov [rsp+98h+var_4C], r9d\nmov byte ptr [rsp+98h+var_60], r10b\nmov [rsp+98h+var_50], r8d\nmov [rsp+98h+var_58], r11\nmov [rsp+98h+var_68], rsi\ncall func0\nmov r11, [rsp+98h+var_58]\nmov rsi, [rsp+98h+var_68]\nmov edx, r14d\nmov rdi, [rsp+98h+var_98]\nmov dword ptr [rsp+98h+var_70], eax\nlea ecx, [r11+1]\ncall func0\nmov esi, dword ptr [rsp+98h+var_70]\nmov r9d, [rsp+98h+var_4C]\nmov r8d, [rsp+98h+var_50]\nmovzx r10d, byte ptr [rsp+98h+var_60]\ncmp esi, eax\ncmovge eax, esi\nmov rsi, [rsp+98h+var_68]\nadd r9d, eax\nloc_1537:\nmov eax, dword ptr [rsp+98h+var_78]\ncmp eax, r9d\ncmovl eax, r9d\nadd dword ptr [rsp+98h+var_88], eax\nloc_1546:\ntest r8d, r8d\njz loc_1BED\nlea eax, [r15+1]\nmovsxd rcx, r8d\nmovsxd r15, dword ptr [rsp+98h+var_80]\nxor r8d, r8d\ncdqe\nmov r14, rcx\nsub rcx, rax\nmov rax, [rsp+98h+var_98]\nadd rcx, rax\njmp short loc_1590\nloc_1570:\nadd r8d, 1\nsub r15, 1\ntest al, al\njnz loc_1723\ntest dl, dl\njnz loc_1723\nmovzx r10d, byte ptr [rsi+r15]\nmov r14d, r9d\nloc_1590:\nmov r9d, r14d\nmov r11d, r15d\nsub r9d, 1\nsetz al\ntest r15d, r15d\nsetz dl\ncmp [rcx+r15], r10b\njz short loc_1570\ntest r15d, r15d\njz loc_1C02\nmovsxd rdx, r15d\nmovsxd rax, r14d\nlea r10d, [r15-1]\nmov dword ptr [rsp+98h+var_80], r8d\nsub rax, rdx\nmov rdx, [rsp+98h+var_98]\nmovsxd r10, r10d\nxor edi, edi\nadd rax, rdx\njmp short loc_15F0\nloc_15D8:\nadd edi, 1\nsub r10, 1\ntest r14d, r14d\njz loc_1B9A\ntest ecx, ecx\njz loc_1B9A\nloc_15F0:\nmov edx, r14d\nmovzx r8d, byte ptr [rsi+r10]\nmov ecx, r10d\nsub r14d, 1\ncmp [rax+r10], r8b\njz short loc_15D8\nmov r8d, dword ptr [rsp+98h+var_80]\nmov dword ptr [rsp+98h+var_80], edi\nmov rdi, [rsp+98h+var_98]\nmov [rsp+98h+var_50], r9d\nmov dword ptr [rsp+98h+var_58], r8d\nmov dword ptr [rsp+98h+var_68], r11d\nmov [rsp+98h+var_60], r10\nmov [rsp+98h+var_70], rsi\ncall func0\nmov r10, [rsp+98h+var_60]\nmov rsi, [rsp+98h+var_70]\nmov edx, r14d\nmov rdi, [rsp+98h+var_98]\nmov dword ptr [rsp+98h+var_78], eax\nlea ecx, [r10+1]\ncall func0\nmov esi, dword ptr [rsp+98h+var_78]\nmov r11d, dword ptr [rsp+98h+var_68]\nmov r9d, [rsp+98h+var_50]\nmov r8d, dword ptr [rsp+98h+var_58]\ncmp esi, eax\ncmovge eax, esi\nadd dword ptr [rsp+98h+var_80], eax\nmov rsi, [rsp+98h+var_70]\nloc_166F:\ntest r9d, r9d\njz loc_1C2C\nlea eax, [r15+1]\nmovsxd rdx, r9d\nmovsxd r15, r11d\nxor r9d, r9d\ncdqe\nmov r14, rdx\nsub rdx, rax\nmov rax, [rsp+98h+var_98]\nadd rax, rdx\njmp short loc_16B1\nloc_16A0:\nadd r9d, 1\nsub r15, 1\ntest r14d, r14d\njz short loc_1715\ntest ecx, ecx\njz short loc_1715\nloc_16B1:\nmov edx, r14d\nmovzx edi, byte ptr [rsi+r15]\nmov ecx, r15d\nsub r14d, 1\ncmp [rax+r15], dil\njz short loc_16A0\nmov rdi, [rsp+98h+var_98]\nmov [rsp+98h+var_50], r8d\nmov dword ptr [rsp+98h+var_68], r9d\nmov [rsp+98h+var_78], rsi\ncall func0\nmov rdi, [rsp+98h+var_98]\nlea ecx, [r15+1]\nmov edx, r14d\nmov rsi, [rsp+98h+var_78]\nmov dword ptr [rsp+98h+var_70], eax\ncall func0\nmov r10d, dword ptr [rsp+98h+var_70]\nmov r9d, dword ptr [rsp+98h+var_68]\nmov rsi, [rsp+98h+var_78]\nmov r8d, [rsp+98h+var_50]\ncmp r10d, eax\ncmovl r10d, eax\nadd r9d, r10d\nloc_1715:\nmov eax, dword ptr [rsp+98h+var_80]\ncmp eax, r9d\ncmovl eax, r9d\nadd r8d, eax\nloc_1723:\nmov eax, dword ptr [rsp+98h+var_88]\ncmp eax, r8d\ncmovl eax, r8d\nadd [rsp+98h+var_90], eax\njmp short loc_173D\nloc_1738:\nmov [rsp+98h+var_90], r9d\nloc_173D:\ntest ebx, ebx\njz loc_1BC3\nlea eax, [rbp+1]\nmovsxd rdi, ebx\nmovsxd rbp, [rsp+98h+var_8C]\nxor r8d, r8d\ncdqe\nsub rdi, rax\nmov rax, [rsp+98h+var_98]\nadd rdi, rax\njmp short loc_1788\nloc_1768:\nadd r8d, 1\nsub rbp, 1\ntest dl, dl\njnz loc_1B37\ntest cl, cl\njnz loc_1B37\nmovzx r12d, byte ptr [rsi+rbp]\nmov ebx, r14d\nloc_1788:\nmov r14d, ebx\nmovzx eax, byte ptr [rdi+rbp]\nmov r11d, ebp\nsub r14d, 1\nsetz dl\ntest ebp, ebp\nsetz cl\ncmp al, r12b\njz short loc_1768\ntest ebp, ebp\njz loc_1BE0\nmovsxd rdx, ebp\nmovsxd rdi, ebx\nlea r15d, [rbp-1]\nxor ecx, ecx\nsub rdi, rdx\nmov rdx, [rsp+98h+var_98]\nmov dword ptr [rsp+98h+var_88], r8d\nmovsxd r15, r15d\nmov r8d, ecx\nadd rdi, rdx\njmp short loc_17F0\nloc_17D0:\nadd r8d, 1\nsub r15, 1\ntest dl, dl\njnz loc_1B78\ntest cl, cl\njnz loc_1B78\nmovzx eax, byte ptr [rdi+r15]\nmov ebx, r9d\nloc_17F0:\nmov r9d, ebx\nsub r9d, 1\nsetz dl\ntest r15d, r15d\nsetz cl\ncmp [rsi+r15], al\njz short loc_17D0\nmovsxd rdx, r15d\nmov [rsp+98h+var_8C], r8d\nmov r8d, dword ptr [rsp+98h+var_88]\nmov dword ptr [rsp+98h+var_80], edx\ntest r15d, r15d\njz loc_1BF5\nmovsxd rax, ebx\nlea r10d, [rdx-1]\nxor edi, edi\nsub rax, rdx\nmov rdx, [rsp+98h+var_98]\nmovsxd r10, r10d\nadd rax, rdx\njmp short loc_1857\nloc_1840:\nadd edi, 1\nsub r10, 1\ntest ebx, ebx\njz loc_1BA8\ntest ecx, ecx\njz loc_1BA8\nloc_1857:\nmov edx, ebx\nmovzx r8d, byte ptr [rsi+r10]\nmov ecx, r10d\nsub ebx, 1\ncmp [rax+r10], r8b\njz short loc_1840\nmov r8d, dword ptr [rsp+98h+var_88]\nmov dword ptr [rsp+98h+var_88], edi\nmov rdi, [rsp+98h+var_98]\nmov [rsp+98h+var_50], r9d\nmov dword ptr [rsp+98h+var_58], r8d\nmov dword ptr [rsp+98h+var_68], r11d\nmov [rsp+98h+var_60], r10\nmov [rsp+98h+var_70], rsi\ncall func0\nmov r10, [rsp+98h+var_60]\nmov rdi, [rsp+98h+var_98]\nmov edx, ebx\nmov rsi, [rsp+98h+var_70]\nmov dword ptr [rsp+98h+var_78], eax\nlea ecx, [r10+1]\ncall func0\nmov esi, dword ptr [rsp+98h+var_78]\nmov r11d, dword ptr [rsp+98h+var_68]\nmov r9d, [rsp+98h+var_50]\nmov r8d, dword ptr [rsp+98h+var_58]\ncmp esi, eax\ncmovge eax, esi\nadd dword ptr [rsp+98h+var_88], eax\nmov rsi, [rsp+98h+var_70]\nloc_18D3:\ntest r9d, r9d\njz loc_1C24\nlea eax, [r15+1]\nmovsxd rdx, r9d\nmovsxd rbx, dword ptr [rsp+98h+var_80]\nxor r9d, r9d\ncdqe\nmov r15, rdx\nsub rdx, rax\nmov rax, [rsp+98h+var_98]\nadd rax, rdx\njmp short loc_1911\nloc_1900:\nadd r9d, 1\nsub rbx, 1\ntest r15d, r15d\njz short loc_197C\ntest ecx, ecx\njz short loc_197C\nloc_1911:\nmov edx, r15d\nmovzx edi, byte ptr [rsi+rbx]\nmov ecx, ebx\nsub r15d, 1\ncmp [rax+rbx], dil\njz short loc_1900\nmov rdi, [rsp+98h+var_98]\nmov [rsp+98h+var_50], r8d\nmov dword ptr [rsp+98h+var_68], r9d\nmov dword ptr [rsp+98h+var_70], r11d\nmov [rsp+98h+var_80], rsi\ncall func0\nmov rsi, [rsp+98h+var_80]\nlea ecx, [rbx+1]\nmov edx, r15d\nmov rdi, [rsp+98h+var_98]\nmov dword ptr [rsp+98h+var_78], eax\ncall func0\nmov r10d, dword ptr [rsp+98h+var_78]\nmov r9d, dword ptr [rsp+98h+var_68]\nmov rsi, [rsp+98h+var_80]\nmov r11d, dword ptr [rsp+98h+var_70]\ncmp r10d, eax\nmov r8d, [rsp+98h+var_50]\ncmovl r10d, eax\nadd r9d, r10d\nloc_197C:\nmov eax, dword ptr [rsp+98h+var_88]\ncmp eax, r9d\ncmovl eax, r9d\nadd [rsp+98h+var_8C], eax\nloc_198B:\ntest r14d, r14d\njz loc_1BCB\nadd ebp, 1\nmov rax, [rsp+98h+var_98]\nmovsxd rcx, r14d\nmovsxd rbx, r11d\nmovsxd rbp, ebp\nxor r9d, r9d\nsub rcx, rbp\nadd rcx, rax\njmp short loc_19D0\nloc_19B0:\nadd r9d, 1\nsub rbx, 1\ntest al, al\njnz loc_1B29\ntest dl, dl\njnz loc_1B29\nmovzx r12d, byte ptr [rsi+rbx]\nmov r14d, ebp\nloc_19D0:\nmov ebp, r14d\nmovsxd r15, ebx\nsub ebp, 1\nsetz al\ntest ebx, ebx\nsetz dl\ncmp [rcx+rbx], r12b\njz short loc_19B0\ntest ebx, ebx\njz loc_1C34\nmov rdi, [rsp+98h+var_98]\nmovsxd rax, r14d\nmovsxd rdx, r15d\nlea r12d, [r15-1]\nsub rax, rdx\nmovsxd r12, r12d\nxor r10d, r10d\nadd rax, rdi\njmp short loc_1A21\nloc_1A10:\nadd r10d, 1\nsub r12, 1\ntest r14d, r14d\njz short loc_1A90\ntest ecx, ecx\njz short loc_1A90\nloc_1A21:\nmov edx, r14d\nmovzx edi, byte ptr [rsi+r12]\nmov ecx, r12d\nsub r14d, 1\ncmp [rax+r12], dil\njz short loc_1A10\nmov rdi, [rsp+98h+var_98]\nmov dword ptr [rsp+98h+var_68], r8d\nmov dword ptr [rsp+98h+var_70], r9d\nmov dword ptr [rsp+98h+var_78], r10d\nmov [rsp+98h+var_88], rsi\ncall func0\nmov rsi, [rsp+98h+var_88]\nmov rdi, [rsp+98h+var_98]\nmov edx, r14d\nlea ecx, [r12+1]\nmov dword ptr [rsp+98h+var_80], eax\ncall func0\nmov r11d, dword ptr [rsp+98h+var_80]\nmov r10d, dword ptr [rsp+98h+var_78]\nmov rsi, [rsp+98h+var_88]\nmov r9d, dword ptr [rsp+98h+var_70]\ncmp r11d, eax\nmov r8d, dword ptr [rsp+98h+var_68]\ncmovl r11d, eax\nadd r10d, r11d\nloc_1A90:\ntest ebp, ebp\njz loc_1C3C\nlea eax, [rbx+1]\nmovsxd rdx, ebp\nxor r12d, r12d\ncdqe\nsub rdx, rax\nmov rax, [rsp+98h+var_98]\nadd rax, rdx\njmp short loc_1AC0\nloc_1AB0:\nadd r12d, 1\nsub r15, 1\ntest ebp, ebp\njz short loc_1B1F\ntest ecx, ecx\njz short loc_1B1F\nloc_1AC0:\nmov edx, ebp\nmovzx edi, byte ptr [rsi+r15]\nmov ecx, r15d\nsub ebp, 1\ncmp [rax+r15], dil\njz short loc_1AB0\nmov r14, [rsp+98h+var_98]\nmov dword ptr [rsp+98h+var_70], r8d\nmov dword ptr [rsp+98h+var_78], r9d\nmov rdi, r14\nmov dword ptr [rsp+98h+var_80], r10d\nmov [rsp+98h+var_88], rsi\ncall func0\nmov rsi, [rsp+98h+var_88]\nlea ecx, [r15+1]\nmov edx, ebp\nmov rdi, r14\nmov ebx, eax\ncall func0\nmov r10d, dword ptr [rsp+98h+var_80]\nmov r9d, dword ptr [rsp+98h+var_78]\ncmp ebx, eax\nmov r8d, dword ptr [rsp+98h+var_70]\ncmovl ebx, eax\nadd r12d, ebx\nloc_1B1F:\ncmp r10d, r12d\ncmovl r10d, r12d\nadd r9d, r10d\nloc_1B29:\nmov eax, [rsp+98h+var_8C]\ncmp eax, r9d\ncmovl eax, r9d\nadd r8d, eax\nloc_1B37:\nmov eax, [rsp+98h+var_90]\ncmp eax, r8d\ncmovl eax, r8d\nadd r13d, eax\nloc_1B45:\nadd rsp, 68h\nmov eax, r13d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1B60:\nmov dword ptr [rsp+98h+var_88], ebx\nmov rbp, [rsp+98h+var_70]\nmov ebx, dword ptr [rsp+98h+var_78]\njmp loc_1546\nloc_1B78:\nmov [rsp+98h+var_8C], r8d\nmov r8d, dword ptr [rsp+98h+var_88]\njmp loc_198B\nloc_1B87:\nxor r13d, r13d\njmp short loc_1B45\nloc_1B8C:\nmov dword ptr [rsp+98h+var_78], edi\nmov r8d, dword ptr [rsp+98h+var_70]\njmp loc_1480\nloc_1B9A:\nmov r8d, dword ptr [rsp+98h+var_80]\nmov dword ptr [rsp+98h+var_80], edi\njmp loc_166F\nloc_1BA8:\nmov r8d, dword ptr [rsp+98h+var_88]\nmov dword ptr [rsp+98h+var_88], edi\njmp loc_18D3\nloc_1BB6:\nmov [rsp+98h+var_90], 0\njmp loc_173D\nloc_1BC3:\nxor r8d, r8d\njmp loc_1B37\nloc_1BCB:\nxor r9d, r9d\njmp loc_1B29\nloc_1BD3:\nmov dword ptr [rsp+98h+var_88], 0\njmp loc_1546\nloc_1BE0:\nmov [rsp+98h+var_8C], 0\njmp loc_198B\nloc_1BED:\nxor r8d, r8d\njmp loc_1723\nloc_1BF5:\nmov dword ptr [rsp+98h+var_88], 0\njmp loc_18D3\nloc_1C02:\nmov dword ptr [rsp+98h+var_80], 0\njmp loc_166F\nloc_1C0F:\nxor r9d, r9d\njmp loc_1537\nloc_1C17:\nmov dword ptr [rsp+98h+var_78], 0\njmp loc_1480\nloc_1C24:\nxor r9d, r9d\njmp loc_197C\nloc_1C2C:\nxor r9d, r9d\njmp loc_1715\nloc_1C34:\nxor r10d, r10d\njmp loc_1A90\nloc_1C3C:\nxor r12d, r12d\njmp loc_1B1F", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, unsigned int a3, int a4)\n{\n unsigned int v4; // ebx\n __int64 v5; // rbp\n unsigned int v6; // r13d\n __int64 v7; // rdi\n unsigned int v8; // r14d\n char v9; // al\n char v10; // r12\n bool v11; // cl\n int v12; // r9d\n __int64 v13; // r15\n __int64 v14; // rdi\n char v15; // r10\n unsigned int v16; // r8d\n bool v17; // cl\n __int64 v18; // r9\n int v19; // ebx\n __int64 v20; // rdi\n bool v21; // cl\n int v22; // edi\n __int64 v23; // r11\n __int64 v24; // rax\n __int64 v25; // rdx\n int v26; // ecx\n int v27; // eax\n unsigned int v28; // r14d\n int v29; // eax\n __int64 v30; // r11\n int v31; // r9d\n __int64 v32; // rax\n __int64 v33; // rdx\n int v34; // ecx\n int v35; // eax\n int v36; // eax\n __int64 v37; // rcx\n int v38; // r8d\n unsigned int v39; // r14d\n __int64 v40; // rcx\n int v41; // r11d\n unsigned int v42; // r9d\n bool v43; // dl\n __int64 v44; // r10\n int v45; // edi\n __int64 v46; // rax\n __int64 v47; // rdx\n int v48; // ecx\n int v49; // eax\n int v50; // eax\n __int64 v51; // rdx\n __int64 v52; // r15\n int v53; // r9d\n unsigned int v54; // r14d\n __int64 v55; // rax\n __int64 v56; // rdx\n int v57; // ecx\n int v58; // eax\n int v59; // r10d\n int v60; // eax\n int v61; // eax\n int v62; // r8d\n __int64 v63; // rdi\n char v64; // al\n int v65; // r11d\n unsigned int v66; // r14d\n bool v67; // cl\n __int64 v68; // r15\n int v69; // r8d\n __int64 v70; // rdi\n unsigned int v71; // r9d\n bool v72; // cl\n int v73; // edi\n __int64 v74; // r10\n __int64 v75; // rax\n __int64 v76; // rdx\n int v77; // ecx\n int v78; // eax\n __int64 v79; // rdx\n __int64 v80; // rbx\n int v81; // r9d\n __int64 v82; // rax\n unsigned int v83; // r15d\n __int64 v84; // rax\n __int64 v85; // rdx\n int v86; // ecx\n int v87; // eax\n int v88; // r10d\n int v89; // eax\n __int64 v90; // rbx\n int v91; // r9d\n __int64 v92; // rcx\n __int64 v93; // r15\n unsigned int v94; // ebp\n bool v95; // dl\n __int64 v96; // r12\n int v97; // r10d\n __int64 v98; // rax\n __int64 v99; // rdx\n int v100; // ecx\n int v101; // eax\n int v102; // r11d\n int v103; // r12d\n __int64 v104; // rax\n __int64 v105; // rdx\n int v106; // ecx\n int v107; // ebx\n int v108; // eax\n int v109; // eax\n int v110; // eax\n int v113; // [rsp+8h] [rbp-90h]\n int v114; // [rsp+8h] [rbp-90h]\n int v115; // [rsp+Ch] [rbp-8Ch]\n int v116; // [rsp+Ch] [rbp-8Ch]\n int v117; // [rsp+10h] [rbp-88h]\n int v118; // [rsp+10h] [rbp-88h]\n int v119; // [rsp+10h] [rbp-88h]\n int v120; // [rsp+10h] [rbp-88h]\n int v121; // [rsp+18h] [rbp-80h]\n int v122; // [rsp+18h] [rbp-80h]\n int v123; // [rsp+18h] [rbp-80h]\n unsigned int v124; // [rsp+20h] [rbp-78h]\n int v125; // [rsp+20h] [rbp-78h]\n int v126; // [rsp+20h] [rbp-78h]\n int v127; // [rsp+20h] [rbp-78h]\n int v128; // [rsp+20h] [rbp-78h]\n int v129; // [rsp+20h] [rbp-78h]\n int v130; // [rsp+20h] [rbp-78h]\n int v131; // [rsp+28h] [rbp-70h]\n int v132; // [rsp+28h] [rbp-70h]\n int v133; // [rsp+28h] [rbp-70h]\n int v134; // [rsp+28h] [rbp-70h]\n int v135; // [rsp+28h] [rbp-70h]\n int v136; // [rsp+28h] [rbp-70h]\n unsigned int v137; // [rsp+30h] [rbp-68h]\n int v138; // [rsp+30h] [rbp-68h]\n int v139; // [rsp+30h] [rbp-68h]\n int v140; // [rsp+30h] [rbp-68h]\n char v141; // [rsp+38h] [rbp-60h]\n int v142; // [rsp+38h] [rbp-60h]\n int v143; // [rsp+38h] [rbp-60h]\n unsigned int v144; // [rsp+40h] [rbp-58h]\n int v145; // [rsp+40h] [rbp-58h]\n int v146; // [rsp+40h] [rbp-58h]\n int v147; // [rsp+48h] [rbp-50h]\n unsigned int v148; // [rsp+48h] [rbp-50h]\n unsigned int v149; // [rsp+48h] [rbp-50h]\n int v150; // [rsp+48h] [rbp-50h]\n unsigned int v151; // [rsp+48h] [rbp-50h]\n int v152; // [rsp+48h] [rbp-50h]\n char v153; // [rsp+4Ch] [rbp-4Ch]\n int v154; // [rsp+4Ch] [rbp-4Ch]\n int v155; // [rsp+50h] [rbp-48h]\n int v156; // [rsp+58h] [rbp-40h]\n\n if ( a3 && a4 )\n {\n v4 = a3;\n v5 = a4 - 1;\n v6 = 0;\n v7 = a1 + (int)a3 - (__int64)a4;\n while ( 1 )\n {\n v8 = v4;\n v9 = *(_BYTE *)(v7 + v5);\n --v4;\n v10 = *(_BYTE *)(a2 + v5);\n v11 = (_DWORD)v5 == 0;\n if ( v9 != v10 )\n break;\n ++v6;\n --v5;\n if ( !v4 || v11 )\n return v6;\n }\n if ( (_DWORD)v5 )\n {\n v12 = 0;\n v13 = (int)v5 - 1;\n v14 = a1 + (int)v8 - (__int64)(int)v5;\n while ( 1 )\n {\n v15 = *(_BYTE *)(a2 + v13);\n v16 = v8 - 1;\n v17 = (_DWORD)v13 == 0;\n if ( v15 != v9 )\n break;\n ++v12;\n --v13;\n if ( v8 == 1 || v17 )\n {\n v114 = v12;\n goto LABEL_67;\n }\n v9 = *(_BYTE *)(v14 + v13);\n --v8;\n }\n v113 = v12;\n if ( (_DWORD)v13 )\n {\n v124 = v4;\n v18 = (int)v13 - 1;\n v19 = 0;\n v20 = a1 + (int)v8 - (__int64)(int)v13;\n while ( 1 )\n {\n v21 = (_DWORD)v18 == 0;\n if ( *(_BYTE *)(a2 + v18) != v9 )\n break;\n ++v19;\n --v18;\n if ( v8 == 1 || v21 )\n {\n v118 = v19;\n v4 = v124;\n goto LABEL_38;\n }\n v9 = *(_BYTE *)(v20 + v18);\n --v8;\n }\n v117 = v19;\n v137 = v8 - 1;\n v4 = v124;\n v147 = v18;\n if ( (_DWORD)v18 )\n {\n v22 = 0;\n v23 = (int)v18 - 1;\n v24 = a1 + (int)v8 - (__int64)(int)v18;\n while ( 1 )\n {\n v25 = v8;\n v26 = v23;\n --v8;\n if ( *(_BYTE *)(v24 + v23) != *(_BYTE *)(a2 + v23) )\n break;\n ++v22;\n --v23;\n if ( !v8 || !v26 )\n {\n v125 = v22;\n goto LABEL_27;\n }\n }\n v156 = v18;\n v153 = *(_BYTE *)(a2 + v13);\n v144 = v16;\n v155 = v23;\n v131 = func0(a1, a2, v25, (unsigned int)v23);\n v27 = func0(a1, a2, v8, (unsigned int)(v155 + 1));\n v16 = v144;\n v15 = v153;\n LODWORD(v18) = v156;\n if ( v131 >= v27 )\n v27 = v131;\n v125 = v27 + v22;\n }\n else\n {\n v125 = 0;\n }\nLABEL_27:\n v28 = v137;\n if ( v137 )\n {\n v29 = v18 + 1;\n v30 = v147;\n v31 = 0;\n v32 = (int)v137 - (__int64)v29 + a1;\n while ( 1 )\n {\n v33 = v28;\n v34 = v30;\n --v28;\n if ( *(_BYTE *)(v32 + v30) != *(_BYTE *)(a2 + v30) )\n break;\n ++v31;\n --v30;\n if ( !v28 || !v34 )\n goto LABEL_35;\n }\n v154 = v31;\n v141 = v15;\n v148 = v16;\n v145 = v30;\n v132 = func0(a1, a2, v33, (unsigned int)v30);\n v35 = func0(a1, a2, v28, (unsigned int)(v145 + 1));\n v16 = v148;\n v15 = v141;\n if ( v132 >= v35 )\n v35 = v132;\n v31 = v35 + v154;\n }\n else\n {\n v31 = 0;\n }\nLABEL_35:\n v36 = v125;\n if ( v125 < v31 )\n v36 = v31;\n v118 = v36 + v117;\n }\n else\n {\n v118 = 0;\n }\nLABEL_38:\n if ( v16 )\n {\n v37 = (int)v16;\n v13 = (int)v13;\n v38 = 0;\n v39 = v37;\n v40 = a1 + v37 - ((int)v13 + 1);\n while ( 1 )\n {\n v41 = v13;\n v42 = v39 - 1;\n v43 = (_DWORD)v13 == 0;\n if ( *(_BYTE *)(v40 + v13) != v15 )\n break;\n ++v38;\n --v13;\n if ( v39 == 1 || v43 )\n goto LABEL_63;\n v15 = *(_BYTE *)(a2 + v13);\n --v39;\n }\n if ( (_DWORD)v13 )\n {\n v44 = (int)v13 - 1;\n v45 = 0;\n v46 = a1 + (int)v39 - (__int64)(int)v13;\n while ( 1 )\n {\n v47 = v39;\n v48 = v44;\n --v39;\n if ( *(_BYTE *)(v46 + v44) != *(_BYTE *)(a2 + v44) )\n break;\n ++v45;\n --v44;\n if ( !v39 || !v48 )\n {\n v121 = v45;\n goto LABEL_52;\n }\n }\n v149 = v42;\n v146 = v38;\n v142 = v44;\n v126 = func0(a1, a2, v47, (unsigned int)v44);\n v49 = func0(a1, a2, v39, (unsigned int)(v142 + 1));\n v41 = v13;\n v42 = v149;\n v38 = v146;\n if ( v126 >= v49 )\n v49 = v126;\n v121 = v49 + v45;\n }\n else\n {\n v121 = 0;\n }\nLABEL_52:\n if ( v42 )\n {\n v50 = v13 + 1;\n v51 = (int)v42;\n v52 = v41;\n v53 = 0;\n v54 = v51;\n v55 = v51 - v50 + a1;\n while ( 1 )\n {\n v56 = v54;\n v57 = v52;\n --v54;\n if ( *(_BYTE *)(v55 + v52) != *(_BYTE *)(a2 + v52) )\n break;\n ++v53;\n --v52;\n if ( !v54 || !v57 )\n goto LABEL_60;\n }\n v150 = v38;\n v138 = v53;\n v133 = func0(a1, a2, v56, (unsigned int)v52);\n v58 = func0(a1, a2, v54, (unsigned int)(v52 + 1));\n v59 = v133;\n v38 = v150;\n if ( v133 < v58 )\n v59 = v58;\n v53 = v59 + v138;\n }\n else\n {\n v53 = 0;\n }\nLABEL_60:\n v60 = v121;\n if ( v121 < v53 )\n v60 = v53;\n v38 += v60;\n }\n else\n {\n v38 = 0;\n }\nLABEL_63:\n v61 = v118;\n if ( v118 < v38 )\n v61 = v38;\n v114 = v61 + v113;\n }\n else\n {\n v114 = 0;\n }\nLABEL_67:\n if ( v4 )\n {\n v5 = (int)v5;\n v62 = 0;\n v63 = a1 + (int)v4 - (__int64)((int)v5 + 1);\n while ( 1 )\n {\n v64 = *(_BYTE *)(v63 + v5);\n v65 = v5;\n v66 = v4 - 1;\n v67 = (_DWORD)v5 == 0;\n if ( v64 != v10 )\n break;\n ++v62;\n --v5;\n if ( v4 == 1 || v67 )\n goto LABEL_126;\n v10 = *(_BYTE *)(a2 + v5);\n --v4;\n }\n if ( (_DWORD)v5 )\n {\n v119 = v62;\n v68 = (int)v5 - 1;\n v69 = 0;\n v70 = a1 + (int)v4 - (__int64)(int)v5;\n while ( 1 )\n {\n v71 = v4 - 1;\n v72 = (_DWORD)v68 == 0;\n if ( *(_BYTE *)(a2 + v68) != v64 )\n break;\n ++v69;\n --v68;\n if ( v4 == 1 || v72 )\n {\n v116 = v69;\n v62 = v119;\n goto LABEL_98;\n }\n v64 = *(_BYTE *)(v70 + v68);\n --v4;\n }\n v115 = v69;\n v62 = v119;\n if ( (_DWORD)v68 )\n {\n v73 = 0;\n v74 = (int)v68 - 1;\n v75 = a1 + (int)v4 - (__int64)(int)v68;\n while ( 1 )\n {\n v76 = v4;\n v77 = v74;\n --v4;\n if ( *(_BYTE *)(v75 + v74) != *(_BYTE *)(a2 + v74) )\n break;\n ++v73;\n --v74;\n if ( !v4 || !v77 )\n {\n v62 = v119;\n v120 = v73;\n goto LABEL_87;\n }\n }\n v151 = v71;\n v143 = v74;\n v127 = func0(a1, a2, v76, (unsigned int)v74);\n v78 = func0(a1, a2, v4, (unsigned int)(v143 + 1));\n v65 = v5;\n v71 = v151;\n v62 = v119;\n if ( v127 >= v78 )\n v78 = v127;\n v120 = v78 + v73;\n }\n else\n {\n v120 = 0;\n }\nLABEL_87:\n if ( v71 )\n {\n v79 = (int)v71;\n v80 = (int)v68;\n v81 = 0;\n v82 = (int)v68 + 1;\n v83 = v79;\n v84 = v79 - v82 + a1;\n while ( 1 )\n {\n v85 = v83;\n v86 = v80;\n --v83;\n if ( *(_BYTE *)(v84 + v80) != *(_BYTE *)(a2 + v80) )\n break;\n ++v81;\n --v80;\n if ( !v83 || !v86 )\n goto LABEL_95;\n }\n v152 = v62;\n v139 = v81;\n v134 = v65;\n v128 = func0(a1, a2, v85, (unsigned int)v80);\n v87 = func0(a1, a2, v83, (unsigned int)(v80 + 1));\n v88 = v128;\n v65 = v134;\n v62 = v152;\n if ( v128 < v87 )\n v88 = v87;\n v81 = v88 + v139;\n }\n else\n {\n v81 = 0;\n }\nLABEL_95:\n v89 = v120;\n if ( v120 < v81 )\n v89 = v81;\n v116 = v89 + v115;\n }\n else\n {\n v116 = 0;\n }\nLABEL_98:\n if ( v66 )\n {\n v90 = v65;\n v91 = 0;\n v92 = a1 + (int)v66 - (__int64)((int)v5 + 1);\n while ( 1 )\n {\n v93 = (int)v90;\n v94 = v66 - 1;\n v95 = (_DWORD)v90 == 0;\n if ( *(_BYTE *)(v92 + v90) != v10 )\n break;\n ++v91;\n --v90;\n if ( v66 == 1 || v95 )\n goto LABEL_123;\n v10 = *(_BYTE *)(a2 + v90);\n --v66;\n }\n if ( (_DWORD)v90 )\n {\n v96 = (int)v90 - 1;\n v97 = 0;\n v98 = a1 + (int)v66 - (__int64)(int)v90;\n while ( 1 )\n {\n v99 = v66;\n v100 = v96;\n --v66;\n if ( *(_BYTE *)(v98 + v96) != *(_BYTE *)(a2 + v96) )\n break;\n ++v97;\n --v96;\n if ( !v66 || !v100 )\n goto LABEL_112;\n }\n v140 = v62;\n v135 = v91;\n v129 = v97;\n v122 = func0(a1, a2, v99, (unsigned int)v96);\n v101 = func0(a1, a2, v66, (unsigned int)(v96 + 1));\n v102 = v122;\n v91 = v135;\n v62 = v140;\n if ( v122 < v101 )\n v102 = v101;\n v97 = v102 + v129;\n }\n else\n {\n v97 = 0;\n }\nLABEL_112:\n if ( v94 )\n {\n v103 = 0;\n v104 = (int)v94 - (__int64)((int)v90 + 1) + a1;\n while ( 1 )\n {\n v105 = v94;\n v106 = v93;\n --v94;\n if ( *(_BYTE *)(v104 + v93) != *(_BYTE *)(a2 + v93) )\n break;\n ++v103;\n --v93;\n if ( !v94 || !v106 )\n goto LABEL_120;\n }\n v136 = v62;\n v130 = v91;\n v123 = v97;\n v107 = func0(a1, a2, v105, (unsigned int)v93);\n v108 = func0(a1, a2, v94, (unsigned int)(v93 + 1));\n v97 = v123;\n v91 = v130;\n v62 = v136;\n if ( v107 < v108 )\n v107 = v108;\n v103 += v107;\n }\n else\n {\n v103 = 0;\n }\nLABEL_120:\n if ( v97 < v103 )\n v97 = v103;\n v91 += v97;\n }\n else\n {\n v91 = 0;\n }\nLABEL_123:\n v109 = v116;\n if ( v116 < v91 )\n v109 = v91;\n v62 += v109;\n }\n else\n {\n v62 = 0;\n }\nLABEL_126:\n v110 = v114;\n if ( v114 < v62 )\n v110 = v62;\n v6 += v110;\n }\n else\n {\n return 0;\n }\n return v6;\n}", + "ida_strip_asm": "sub_1250:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 68h\nmov [rsp+98h+var_98], rdi\ntest edx, edx\njz loc_1B87\ntest ecx, ecx\njz loc_1B87\nmov rax, rdi\nlea ebp, [rcx-1]\nmovsxd rdi, edx\nmovsxd rcx, ecx\nsub rdi, rcx\nmov ebx, edx\nmovsxd rbp, ebp\nxor r13d, r13d\nadd rdi, rax\njmp short loc_12B0\nloc_1298:\nadd r13d, 1\nsub rbp, 1\ntest dl, dl\njnz loc_1B45\ntest cl, cl\njnz loc_1B45\nloc_12B0:\nmov r14d, ebx\nmovzx eax, byte ptr [rdi+rbp]\nsub ebx, 1\nmovzx r12d, byte ptr [rsi+rbp]\nsetz dl\ntest ebp, ebp\nsetz cl\ncmp al, r12b\njz short loc_1298\nmov [rsp+98h+var_8C], ebp\ntest ebp, ebp\njz loc_1BB6\nmovsxd rdx, ebp\nmovsxd rdi, r14d\nxor r9d, r9d\nlea r15d, [rdx-1]\nsub rdi, rdx\nmov rdx, [rsp+98h+var_98]\nmovsxd r15, r15d\nadd rdi, rdx\njmp short loc_1318\nloc_12F8:\nadd r9d, 1\nsub r15, 1\ntest dl, dl\njnz loc_1738\ntest cl, cl\njnz loc_1738\nmovzx eax, byte ptr [rdi+r15]\nmov r14d, r8d\nloc_1318:\nmov r8d, r14d\nmovzx r10d, byte ptr [rsi+r15]\nsub r8d, 1\nsetz dl\ntest r15d, r15d\nsetz cl\ncmp r10b, al\njz short loc_12F8\nmov [rsp+98h+var_90], r9d\nmov dword ptr [rsp+98h+var_80], r15d\ntest r15d, r15d\njz loc_1BD3\nmovsxd rdx, r15d\nmovsxd rdi, r14d\nxor ecx, ecx\nmov dword ptr [rsp+98h+var_78], ebx\nlea r9d, [rdx-1]\nsub rdi, rdx\nmov rdx, [rsp+98h+var_98]\nmov [rsp+98h+var_70], rbp\nmovsxd r9, r9d\nmov ebx, ecx\nadd rdi, rdx\njmp short loc_138F\nloc_1370:\nadd ebx, 1\nsub r9, 1\ntest dl, dl\njnz loc_1B60\ntest cl, cl\njnz loc_1B60\nmovzx eax, byte ptr [rdi+r9]\nmov r14d, r11d\nloc_138F:\nmov r11d, r14d\nsub r11d, 1\nsetz dl\ntest r9d, r9d\nsetz cl\ncmp [rsi+r9], al\njz short loc_1370\nmovsxd rdx, r9d\nmov dword ptr [rsp+98h+var_88], ebx\nmov rbp, [rsp+98h+var_70]\nmov dword ptr [rsp+98h+var_68], r11d\nmov ebx, dword ptr [rsp+98h+var_78]\nmov [rsp+98h+var_50], edx\ntest r9d, r9d\njz loc_1C17\nmovsxd rax, r14d\nlea r11d, [rdx-1]\nmov dword ptr [rsp+98h+var_70], r8d\nxor edi, edi\nsub rax, rdx\nmov rdx, [rsp+98h+var_98]\nmovsxd r11, r11d\nadd rax, rdx\njmp short loc_1400\nloc_13E8:\nadd edi, 1\nsub r11, 1\ntest r14d, r14d\njz loc_1B8C\ntest ecx, ecx\njz loc_1B8C\nloc_1400:\nmov edx, r14d\nmovzx r8d, byte ptr [rsi+r11]\nmov ecx, r11d\nsub r14d, 1\ncmp [rax+r11], r8b\njz short loc_13E8\nmov r8d, dword ptr [rsp+98h+var_70]\nmov dword ptr [rsp+98h+var_78], edi\nmov rdi, [rsp+98h+var_98]\nmov [rsp+98h+var_40], r9\nmov byte ptr [rsp+98h+var_4C], r10b\nmov dword ptr [rsp+98h+var_58], r8d\nmov [rsp+98h+var_48], r11\nmov [rsp+98h+var_60], rsi\ncall sub_1250\nmov r11, [rsp+98h+var_48]\nmov rsi, [rsp+98h+var_60]\nmov edx, r14d\nmov rdi, [rsp+98h+var_98]\nmov dword ptr [rsp+98h+var_70], eax\nlea ecx, [r11+1]\ncall sub_1250\nmov esi, dword ptr [rsp+98h+var_70]\nmov r8d, dword ptr [rsp+98h+var_58]\nmovzx r10d, byte ptr [rsp+98h+var_4C]\nmov r9, [rsp+98h+var_40]\ncmp esi, eax\ncmovge eax, esi\nadd dword ptr [rsp+98h+var_78], eax\nmov rsi, [rsp+98h+var_60]\nloc_1480:\nmov r14d, dword ptr [rsp+98h+var_68]\ntest r14d, r14d\njz loc_1C0F\nlea eax, [r9+1]\nmovsxd rdx, r14d\nmovsxd r11, [rsp+98h+var_50]\nxor r9d, r9d\ncdqe\nsub rdx, rax\nmov rax, [rsp+98h+var_98]\nadd rax, rdx\njmp short loc_14C1\nloc_14B0:\nadd r9d, 1\nsub r11, 1\ntest r14d, r14d\njz short loc_1537\ntest ecx, ecx\njz short loc_1537\nloc_14C1:\nmov edx, r14d\nmovzx edi, byte ptr [rsi+r11]\nmov ecx, r11d\nsub r14d, 1\ncmp [rax+r11], dil\njz short loc_14B0\nmov rdi, [rsp+98h+var_98]\nmov [rsp+98h+var_4C], r9d\nmov byte ptr [rsp+98h+var_60], r10b\nmov [rsp+98h+var_50], r8d\nmov [rsp+98h+var_58], r11\nmov [rsp+98h+var_68], rsi\ncall sub_1250\nmov r11, [rsp+98h+var_58]\nmov rsi, [rsp+98h+var_68]\nmov edx, r14d\nmov rdi, [rsp+98h+var_98]\nmov dword ptr [rsp+98h+var_70], eax\nlea ecx, [r11+1]\ncall sub_1250\nmov esi, dword ptr [rsp+98h+var_70]\nmov r9d, [rsp+98h+var_4C]\nmov r8d, [rsp+98h+var_50]\nmovzx r10d, byte ptr [rsp+98h+var_60]\ncmp esi, eax\ncmovge eax, esi\nmov rsi, [rsp+98h+var_68]\nadd r9d, eax\nloc_1537:\nmov eax, dword ptr [rsp+98h+var_78]\ncmp eax, r9d\ncmovl eax, r9d\nadd dword ptr [rsp+98h+var_88], eax\nloc_1546:\ntest r8d, r8d\njz loc_1BED\nlea eax, [r15+1]\nmovsxd rcx, r8d\nmovsxd r15, dword ptr [rsp+98h+var_80]\nxor r8d, r8d\ncdqe\nmov r14, rcx\nsub rcx, rax\nmov rax, [rsp+98h+var_98]\nadd rcx, rax\njmp short loc_1590\nloc_1570:\nadd r8d, 1\nsub r15, 1\ntest al, al\njnz loc_1723\ntest dl, dl\njnz loc_1723\nmovzx r10d, byte ptr [rsi+r15]\nmov r14d, r9d\nloc_1590:\nmov r9d, r14d\nmov r11d, r15d\nsub r9d, 1\nsetz al\ntest r15d, r15d\nsetz dl\ncmp [rcx+r15], r10b\njz short loc_1570\ntest r15d, r15d\njz loc_1C02\nmovsxd rdx, r15d\nmovsxd rax, r14d\nlea r10d, [r15-1]\nmov dword ptr [rsp+98h+var_80], r8d\nsub rax, rdx\nmov rdx, [rsp+98h+var_98]\nmovsxd r10, r10d\nxor edi, edi\nadd rax, rdx\njmp short loc_15F0\nloc_15D8:\nadd edi, 1\nsub r10, 1\ntest r14d, r14d\njz loc_1B9A\ntest ecx, ecx\njz loc_1B9A\nloc_15F0:\nmov edx, r14d\nmovzx r8d, byte ptr [rsi+r10]\nmov ecx, r10d\nsub r14d, 1\ncmp [rax+r10], r8b\njz short loc_15D8\nmov r8d, dword ptr [rsp+98h+var_80]\nmov dword ptr [rsp+98h+var_80], edi\nmov rdi, [rsp+98h+var_98]\nmov [rsp+98h+var_50], r9d\nmov dword ptr [rsp+98h+var_58], r8d\nmov dword ptr [rsp+98h+var_68], r11d\nmov [rsp+98h+var_60], r10\nmov [rsp+98h+var_70], rsi\ncall sub_1250\nmov r10, [rsp+98h+var_60]\nmov rsi, [rsp+98h+var_70]\nmov edx, r14d\nmov rdi, [rsp+98h+var_98]\nmov dword ptr [rsp+98h+var_78], eax\nlea ecx, [r10+1]\ncall sub_1250\nmov esi, dword ptr [rsp+98h+var_78]\nmov r11d, dword ptr [rsp+98h+var_68]\nmov r9d, [rsp+98h+var_50]\nmov r8d, dword ptr [rsp+98h+var_58]\ncmp esi, eax\ncmovge eax, esi\nadd dword ptr [rsp+98h+var_80], eax\nmov rsi, [rsp+98h+var_70]\nloc_166F:\ntest r9d, r9d\njz loc_1C2C\nlea eax, [r15+1]\nmovsxd rdx, r9d\nmovsxd r15, r11d\nxor r9d, r9d\ncdqe\nmov r14, rdx\nsub rdx, rax\nmov rax, [rsp+98h+var_98]\nadd rax, rdx\njmp short loc_16B1\nloc_16A0:\nadd r9d, 1\nsub r15, 1\ntest r14d, r14d\njz short loc_1715\ntest ecx, ecx\njz short loc_1715\nloc_16B1:\nmov edx, r14d\nmovzx edi, byte ptr [rsi+r15]\nmov ecx, r15d\nsub r14d, 1\ncmp [rax+r15], dil\njz short loc_16A0\nmov rdi, [rsp+98h+var_98]\nmov [rsp+98h+var_50], r8d\nmov dword ptr [rsp+98h+var_68], r9d\nmov [rsp+98h+var_78], rsi\ncall sub_1250\nmov rdi, [rsp+98h+var_98]\nlea ecx, [r15+1]\nmov edx, r14d\nmov rsi, [rsp+98h+var_78]\nmov dword ptr [rsp+98h+var_70], eax\ncall sub_1250\nmov r10d, dword ptr [rsp+98h+var_70]\nmov r9d, dword ptr [rsp+98h+var_68]\nmov rsi, [rsp+98h+var_78]\nmov r8d, [rsp+98h+var_50]\ncmp r10d, eax\ncmovl r10d, eax\nadd r9d, r10d\nloc_1715:\nmov eax, dword ptr [rsp+98h+var_80]\ncmp eax, r9d\ncmovl eax, r9d\nadd r8d, eax\nloc_1723:\nmov eax, dword ptr [rsp+98h+var_88]\ncmp eax, r8d\ncmovl eax, r8d\nadd [rsp+98h+var_90], eax\njmp short loc_173D\nloc_1738:\nmov [rsp+98h+var_90], r9d\nloc_173D:\ntest ebx, ebx\njz loc_1BC3\nlea eax, [rbp+1]\nmovsxd rdi, ebx\nmovsxd rbp, [rsp+98h+var_8C]\nxor r8d, r8d\ncdqe\nsub rdi, rax\nmov rax, [rsp+98h+var_98]\nadd rdi, rax\njmp short loc_1788\nloc_1768:\nadd r8d, 1\nsub rbp, 1\ntest dl, dl\njnz loc_1B37\ntest cl, cl\njnz loc_1B37\nmovzx r12d, byte ptr [rsi+rbp]\nmov ebx, r14d\nloc_1788:\nmov r14d, ebx\nmovzx eax, byte ptr [rdi+rbp]\nmov r11d, ebp\nsub r14d, 1\nsetz dl\ntest ebp, ebp\nsetz cl\ncmp al, r12b\njz short loc_1768\ntest ebp, ebp\njz loc_1BE0\nmovsxd rdx, ebp\nmovsxd rdi, ebx\nlea r15d, [rbp-1]\nxor ecx, ecx\nsub rdi, rdx\nmov rdx, [rsp+98h+var_98]\nmov dword ptr [rsp+98h+var_88], r8d\nmovsxd r15, r15d\nmov r8d, ecx\nadd rdi, rdx\njmp short loc_17F0\nloc_17D0:\nadd r8d, 1\nsub r15, 1\ntest dl, dl\njnz loc_1B78\ntest cl, cl\njnz loc_1B78\nmovzx eax, byte ptr [rdi+r15]\nmov ebx, r9d\nloc_17F0:\nmov r9d, ebx\nsub r9d, 1\nsetz dl\ntest r15d, r15d\nsetz cl\ncmp [rsi+r15], al\njz short loc_17D0\nmovsxd rdx, r15d\nmov [rsp+98h+var_8C], r8d\nmov r8d, dword ptr [rsp+98h+var_88]\nmov dword ptr [rsp+98h+var_80], edx\ntest r15d, r15d\njz loc_1BF5\nmovsxd rax, ebx\nlea r10d, [rdx-1]\nxor edi, edi\nsub rax, rdx\nmov rdx, [rsp+98h+var_98]\nmovsxd r10, r10d\nadd rax, rdx\njmp short loc_1857\nloc_1840:\nadd edi, 1\nsub r10, 1\ntest ebx, ebx\njz loc_1BA8\ntest ecx, ecx\njz loc_1BA8\nloc_1857:\nmov edx, ebx\nmovzx r8d, byte ptr [rsi+r10]\nmov ecx, r10d\nsub ebx, 1\ncmp [rax+r10], r8b\njz short loc_1840\nmov r8d, dword ptr [rsp+98h+var_88]\nmov dword ptr [rsp+98h+var_88], edi\nmov rdi, [rsp+98h+var_98]\nmov [rsp+98h+var_50], r9d\nmov dword ptr [rsp+98h+var_58], r8d\nmov dword ptr [rsp+98h+var_68], r11d\nmov [rsp+98h+var_60], r10\nmov [rsp+98h+var_70], rsi\ncall sub_1250\nmov r10, [rsp+98h+var_60]\nmov rdi, [rsp+98h+var_98]\nmov edx, ebx\nmov rsi, [rsp+98h+var_70]\nmov dword ptr [rsp+98h+var_78], eax\nlea ecx, [r10+1]\ncall sub_1250\nmov esi, dword ptr [rsp+98h+var_78]\nmov r11d, dword ptr [rsp+98h+var_68]\nmov r9d, [rsp+98h+var_50]\nmov r8d, dword ptr [rsp+98h+var_58]\ncmp esi, eax\ncmovge eax, esi\nadd dword ptr [rsp+98h+var_88], eax\nmov rsi, [rsp+98h+var_70]\nloc_18D3:\ntest r9d, r9d\njz loc_1C24\nlea eax, [r15+1]\nmovsxd rdx, r9d\nmovsxd rbx, dword ptr [rsp+98h+var_80]\nxor r9d, r9d\ncdqe\nmov r15, rdx\nsub rdx, rax\nmov rax, [rsp+98h+var_98]\nadd rax, rdx\njmp short loc_1911\nloc_1900:\nadd r9d, 1\nsub rbx, 1\ntest r15d, r15d\njz short loc_197C\ntest ecx, ecx\njz short loc_197C\nloc_1911:\nmov edx, r15d\nmovzx edi, byte ptr [rsi+rbx]\nmov ecx, ebx\nsub r15d, 1\ncmp [rax+rbx], dil\njz short loc_1900\nmov rdi, [rsp+98h+var_98]\nmov [rsp+98h+var_50], r8d\nmov dword ptr [rsp+98h+var_68], r9d\nmov dword ptr [rsp+98h+var_70], r11d\nmov [rsp+98h+var_80], rsi\ncall sub_1250\nmov rsi, [rsp+98h+var_80]\nlea ecx, [rbx+1]\nmov edx, r15d\nmov rdi, [rsp+98h+var_98]\nmov dword ptr [rsp+98h+var_78], eax\ncall sub_1250\nmov r10d, dword ptr [rsp+98h+var_78]\nmov r9d, dword ptr [rsp+98h+var_68]\nmov rsi, [rsp+98h+var_80]\nmov r11d, dword ptr [rsp+98h+var_70]\ncmp r10d, eax\nmov r8d, [rsp+98h+var_50]\ncmovl r10d, eax\nadd r9d, r10d\nloc_197C:\nmov eax, dword ptr [rsp+98h+var_88]\ncmp eax, r9d\ncmovl eax, r9d\nadd [rsp+98h+var_8C], eax\nloc_198B:\ntest r14d, r14d\njz loc_1BCB\nadd ebp, 1\nmov rax, [rsp+98h+var_98]\nmovsxd rcx, r14d\nmovsxd rbx, r11d\nmovsxd rbp, ebp\nxor r9d, r9d\nsub rcx, rbp\nadd rcx, rax\njmp short loc_19D0\nloc_19B0:\nadd r9d, 1\nsub rbx, 1\ntest al, al\njnz loc_1B29\ntest dl, dl\njnz loc_1B29\nmovzx r12d, byte ptr [rsi+rbx]\nmov r14d, ebp\nloc_19D0:\nmov ebp, r14d\nmovsxd r15, ebx\nsub ebp, 1\nsetz al\ntest ebx, ebx\nsetz dl\ncmp [rcx+rbx], r12b\njz short loc_19B0\ntest ebx, ebx\njz loc_1C34\nmov rdi, [rsp+98h+var_98]\nmovsxd rax, r14d\nmovsxd rdx, r15d\nlea r12d, [r15-1]\nsub rax, rdx\nmovsxd r12, r12d\nxor r10d, r10d\nadd rax, rdi\njmp short loc_1A21\nloc_1A10:\nadd r10d, 1\nsub r12, 1\ntest r14d, r14d\njz short loc_1A90\ntest ecx, ecx\njz short loc_1A90\nloc_1A21:\nmov edx, r14d\nmovzx edi, byte ptr [rsi+r12]\nmov ecx, r12d\nsub r14d, 1\ncmp [rax+r12], dil\njz short loc_1A10\nmov rdi, [rsp+98h+var_98]\nmov dword ptr [rsp+98h+var_68], r8d\nmov dword ptr [rsp+98h+var_70], r9d\nmov dword ptr [rsp+98h+var_78], r10d\nmov [rsp+98h+var_88], rsi\ncall sub_1250\nmov rsi, [rsp+98h+var_88]\nmov rdi, [rsp+98h+var_98]\nmov edx, r14d\nlea ecx, [r12+1]\nmov dword ptr [rsp+98h+var_80], eax\ncall sub_1250\nmov r11d, dword ptr [rsp+98h+var_80]\nmov r10d, dword ptr [rsp+98h+var_78]\nmov rsi, [rsp+98h+var_88]\nmov r9d, dword ptr [rsp+98h+var_70]\ncmp r11d, eax\nmov r8d, dword ptr [rsp+98h+var_68]\ncmovl r11d, eax\nadd r10d, r11d\nloc_1A90:\ntest ebp, ebp\njz loc_1C3C\nlea eax, [rbx+1]\nmovsxd rdx, ebp\nxor r12d, r12d\ncdqe\nsub rdx, rax\nmov rax, [rsp+98h+var_98]\nadd rax, rdx\njmp short loc_1AC0\nloc_1AB0:\nadd r12d, 1\nsub r15, 1\ntest ebp, ebp\njz short loc_1B1F\ntest ecx, ecx\njz short loc_1B1F\nloc_1AC0:\nmov edx, ebp\nmovzx edi, byte ptr [rsi+r15]\nmov ecx, r15d\nsub ebp, 1\ncmp [rax+r15], dil\njz short loc_1AB0\nmov r14, [rsp+98h+var_98]\nmov dword ptr [rsp+98h+var_70], r8d\nmov dword ptr [rsp+98h+var_78], r9d\nmov rdi, r14\nmov dword ptr [rsp+98h+var_80], r10d\nmov [rsp+98h+var_88], rsi\ncall sub_1250\nmov rsi, [rsp+98h+var_88]\nlea ecx, [r15+1]\nmov edx, ebp\nmov rdi, r14\nmov ebx, eax\ncall sub_1250\nmov r10d, dword ptr [rsp+98h+var_80]\nmov r9d, dword ptr [rsp+98h+var_78]\ncmp ebx, eax\nmov r8d, dword ptr [rsp+98h+var_70]\ncmovl ebx, eax\nadd r12d, ebx\nloc_1B1F:\ncmp r10d, r12d\ncmovl r10d, r12d\nadd r9d, r10d\nloc_1B29:\nmov eax, [rsp+98h+var_8C]\ncmp eax, r9d\ncmovl eax, r9d\nadd r8d, eax\nloc_1B37:\nmov eax, [rsp+98h+var_90]\ncmp eax, r8d\ncmovl eax, r8d\nadd r13d, eax\nloc_1B45:\nadd rsp, 68h\nmov eax, r13d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1B60:\nmov dword ptr [rsp+98h+var_88], ebx\nmov rbp, [rsp+98h+var_70]\nmov ebx, dword ptr [rsp+98h+var_78]\njmp loc_1546\nloc_1B78:\nmov [rsp+98h+var_8C], r8d\nmov r8d, dword ptr [rsp+98h+var_88]\njmp loc_198B\nloc_1B87:\nxor r13d, r13d\njmp short loc_1B45\nloc_1B8C:\nmov dword ptr [rsp+98h+var_78], edi\nmov r8d, dword ptr [rsp+98h+var_70]\njmp loc_1480\nloc_1B9A:\nmov r8d, dword ptr [rsp+98h+var_80]\nmov dword ptr [rsp+98h+var_80], edi\njmp loc_166F\nloc_1BA8:\nmov r8d, dword ptr [rsp+98h+var_88]\nmov dword ptr [rsp+98h+var_88], edi\njmp loc_18D3\nloc_1BB6:\nmov [rsp+98h+var_90], 0\njmp loc_173D\nloc_1BC3:\nxor r8d, r8d\njmp loc_1B37\nloc_1BCB:\nxor r9d, r9d\njmp loc_1B29\nloc_1BD3:\nmov dword ptr [rsp+98h+var_88], 0\njmp loc_1546\nloc_1BE0:\nmov [rsp+98h+var_8C], 0\njmp loc_198B\nloc_1BED:\nxor r8d, r8d\njmp loc_1723\nloc_1BF5:\nmov dword ptr [rsp+98h+var_88], 0\njmp loc_18D3\nloc_1C02:\nmov dword ptr [rsp+98h+var_80], 0\njmp loc_166F\nloc_1C0F:\nxor r9d, r9d\njmp loc_1537\nloc_1C17:\nmov dword ptr [rsp+98h+var_78], 0\njmp loc_1480\nloc_1C24:\nxor r9d, r9d\njmp loc_197C\nloc_1C2C:\nxor r9d, r9d\njmp loc_1715\nloc_1C34:\nxor r10d, r10d\njmp loc_1A90\nloc_1C3C:\nxor r12d, r12d\njmp loc_1B1F", + "ida_strip_pseudo": "__int64 __fastcall sub_1250(__int64 a1, __int64 a2, unsigned int a3, int a4)\n{\n unsigned int v4; // ebx\n __int64 v5; // rbp\n unsigned int v6; // r13d\n __int64 v7; // rdi\n unsigned int v8; // r14d\n char v9; // al\n char v10; // r12\n bool v11; // cl\n int v12; // r9d\n __int64 v13; // r15\n __int64 v14; // rdi\n char v15; // r10\n unsigned int v16; // r8d\n bool v17; // cl\n __int64 v18; // r9\n int v19; // ebx\n __int64 v20; // rdi\n bool v21; // cl\n int v22; // edi\n __int64 v23; // r11\n __int64 v24; // rax\n __int64 v25; // rdx\n int v26; // ecx\n int v27; // eax\n unsigned int v28; // r14d\n int v29; // eax\n __int64 v30; // r11\n int v31; // r9d\n __int64 v32; // rax\n __int64 v33; // rdx\n int v34; // ecx\n int v35; // eax\n int v36; // eax\n __int64 v37; // rcx\n int v38; // r8d\n unsigned int v39; // r14d\n __int64 v40; // rcx\n int v41; // r11d\n unsigned int v42; // r9d\n bool v43; // dl\n __int64 v44; // r10\n int v45; // edi\n __int64 v46; // rax\n __int64 v47; // rdx\n int v48; // ecx\n int v49; // eax\n int v50; // eax\n __int64 v51; // rdx\n __int64 v52; // r15\n int v53; // r9d\n unsigned int v54; // r14d\n __int64 v55; // rax\n __int64 v56; // rdx\n int v57; // ecx\n int v58; // eax\n int v59; // r10d\n int v60; // eax\n int v61; // eax\n int v62; // r8d\n __int64 v63; // rdi\n char v64; // al\n int v65; // r11d\n unsigned int v66; // r14d\n bool v67; // cl\n __int64 v68; // r15\n int v69; // r8d\n __int64 v70; // rdi\n unsigned int v71; // r9d\n bool v72; // cl\n int v73; // edi\n __int64 v74; // r10\n __int64 v75; // rax\n __int64 v76; // rdx\n int v77; // ecx\n int v78; // eax\n __int64 v79; // rdx\n __int64 v80; // rbx\n int v81; // r9d\n __int64 v82; // rax\n unsigned int v83; // r15d\n __int64 v84; // rax\n __int64 v85; // rdx\n int v86; // ecx\n int v87; // eax\n int v88; // r10d\n int v89; // eax\n __int64 v90; // rbx\n int v91; // r9d\n __int64 v92; // rcx\n __int64 v93; // r15\n unsigned int v94; // ebp\n bool v95; // dl\n __int64 v96; // r12\n int v97; // r10d\n __int64 v98; // rax\n __int64 v99; // rdx\n int v100; // ecx\n int v101; // eax\n int v102; // r11d\n int v103; // r12d\n __int64 v104; // rax\n __int64 v105; // rdx\n int v106; // ecx\n int v107; // ebx\n int v108; // eax\n int v109; // eax\n int v110; // eax\n int v113; // [rsp+8h] [rbp-90h]\n int v114; // [rsp+8h] [rbp-90h]\n int v115; // [rsp+Ch] [rbp-8Ch]\n int v116; // [rsp+Ch] [rbp-8Ch]\n int v117; // [rsp+10h] [rbp-88h]\n int v118; // [rsp+10h] [rbp-88h]\n int v119; // [rsp+10h] [rbp-88h]\n int v120; // [rsp+10h] [rbp-88h]\n int v121; // [rsp+18h] [rbp-80h]\n int v122; // [rsp+18h] [rbp-80h]\n int v123; // [rsp+18h] [rbp-80h]\n unsigned int v124; // [rsp+20h] [rbp-78h]\n int v125; // [rsp+20h] [rbp-78h]\n int v126; // [rsp+20h] [rbp-78h]\n int v127; // [rsp+20h] [rbp-78h]\n int v128; // [rsp+20h] [rbp-78h]\n int v129; // [rsp+20h] [rbp-78h]\n int v130; // [rsp+20h] [rbp-78h]\n int v131; // [rsp+28h] [rbp-70h]\n int v132; // [rsp+28h] [rbp-70h]\n int v133; // [rsp+28h] [rbp-70h]\n int v134; // [rsp+28h] [rbp-70h]\n int v135; // [rsp+28h] [rbp-70h]\n int v136; // [rsp+28h] [rbp-70h]\n unsigned int v137; // [rsp+30h] [rbp-68h]\n int v138; // [rsp+30h] [rbp-68h]\n int v139; // [rsp+30h] [rbp-68h]\n int v140; // [rsp+30h] [rbp-68h]\n char v141; // [rsp+38h] [rbp-60h]\n int v142; // [rsp+38h] [rbp-60h]\n int v143; // [rsp+38h] [rbp-60h]\n unsigned int v144; // [rsp+40h] [rbp-58h]\n int v145; // [rsp+40h] [rbp-58h]\n int v146; // [rsp+40h] [rbp-58h]\n int v147; // [rsp+48h] [rbp-50h]\n unsigned int v148; // [rsp+48h] [rbp-50h]\n unsigned int v149; // [rsp+48h] [rbp-50h]\n int v150; // [rsp+48h] [rbp-50h]\n unsigned int v151; // [rsp+48h] [rbp-50h]\n int v152; // [rsp+48h] [rbp-50h]\n char v153; // [rsp+4Ch] [rbp-4Ch]\n int v154; // [rsp+4Ch] [rbp-4Ch]\n int v155; // [rsp+50h] [rbp-48h]\n int v156; // [rsp+58h] [rbp-40h]\n\n if ( a3 && a4 )\n {\n v4 = a3;\n v5 = a4 - 1;\n v6 = 0;\n v7 = a1 + (int)a3 - (__int64)a4;\n while ( 1 )\n {\n v8 = v4;\n v9 = *(_BYTE *)(v7 + v5);\n --v4;\n v10 = *(_BYTE *)(a2 + v5);\n v11 = (_DWORD)v5 == 0;\n if ( v9 != v10 )\n break;\n ++v6;\n --v5;\n if ( !v4 || v11 )\n return v6;\n }\n if ( (_DWORD)v5 )\n {\n v12 = 0;\n v13 = (int)v5 - 1;\n v14 = a1 + (int)v8 - (__int64)(int)v5;\n while ( 1 )\n {\n v15 = *(_BYTE *)(a2 + v13);\n v16 = v8 - 1;\n v17 = (_DWORD)v13 == 0;\n if ( v15 != v9 )\n break;\n ++v12;\n --v13;\n if ( v8 == 1 || v17 )\n {\n v114 = v12;\n goto LABEL_67;\n }\n v9 = *(_BYTE *)(v14 + v13);\n --v8;\n }\n v113 = v12;\n if ( (_DWORD)v13 )\n {\n v124 = v4;\n v18 = (int)v13 - 1;\n v19 = 0;\n v20 = a1 + (int)v8 - (__int64)(int)v13;\n while ( 1 )\n {\n v21 = (_DWORD)v18 == 0;\n if ( *(_BYTE *)(a2 + v18) != v9 )\n break;\n ++v19;\n --v18;\n if ( v8 == 1 || v21 )\n {\n v118 = v19;\n v4 = v124;\n goto LABEL_38;\n }\n v9 = *(_BYTE *)(v20 + v18);\n --v8;\n }\n v117 = v19;\n v137 = v8 - 1;\n v4 = v124;\n v147 = v18;\n if ( (_DWORD)v18 )\n {\n v22 = 0;\n v23 = (int)v18 - 1;\n v24 = a1 + (int)v8 - (__int64)(int)v18;\n while ( 1 )\n {\n v25 = v8;\n v26 = v23;\n --v8;\n if ( *(_BYTE *)(v24 + v23) != *(_BYTE *)(a2 + v23) )\n break;\n ++v22;\n --v23;\n if ( !v8 || !v26 )\n {\n v125 = v22;\n goto LABEL_27;\n }\n }\n v156 = v18;\n v153 = *(_BYTE *)(a2 + v13);\n v144 = v16;\n v155 = v23;\n v131 = sub_1250(a1, a2, v25, (unsigned int)v23);\n v27 = sub_1250(a1, a2, v8, (unsigned int)(v155 + 1));\n v16 = v144;\n v15 = v153;\n LODWORD(v18) = v156;\n if ( v131 >= v27 )\n v27 = v131;\n v125 = v27 + v22;\n }\n else\n {\n v125 = 0;\n }\nLABEL_27:\n v28 = v137;\n if ( v137 )\n {\n v29 = v18 + 1;\n v30 = v147;\n v31 = 0;\n v32 = (int)v137 - (__int64)v29 + a1;\n while ( 1 )\n {\n v33 = v28;\n v34 = v30;\n --v28;\n if ( *(_BYTE *)(v32 + v30) != *(_BYTE *)(a2 + v30) )\n break;\n ++v31;\n --v30;\n if ( !v28 || !v34 )\n goto LABEL_35;\n }\n v154 = v31;\n v141 = v15;\n v148 = v16;\n v145 = v30;\n v132 = sub_1250(a1, a2, v33, (unsigned int)v30);\n v35 = sub_1250(a1, a2, v28, (unsigned int)(v145 + 1));\n v16 = v148;\n v15 = v141;\n if ( v132 >= v35 )\n v35 = v132;\n v31 = v35 + v154;\n }\n else\n {\n v31 = 0;\n }\nLABEL_35:\n v36 = v125;\n if ( v125 < v31 )\n v36 = v31;\n v118 = v36 + v117;\n }\n else\n {\n v118 = 0;\n }\nLABEL_38:\n if ( v16 )\n {\n v37 = (int)v16;\n v13 = (int)v13;\n v38 = 0;\n v39 = v37;\n v40 = a1 + v37 - ((int)v13 + 1);\n while ( 1 )\n {\n v41 = v13;\n v42 = v39 - 1;\n v43 = (_DWORD)v13 == 0;\n if ( *(_BYTE *)(v40 + v13) != v15 )\n break;\n ++v38;\n --v13;\n if ( v39 == 1 || v43 )\n goto LABEL_63;\n v15 = *(_BYTE *)(a2 + v13);\n --v39;\n }\n if ( (_DWORD)v13 )\n {\n v44 = (int)v13 - 1;\n v45 = 0;\n v46 = a1 + (int)v39 - (__int64)(int)v13;\n while ( 1 )\n {\n v47 = v39;\n v48 = v44;\n --v39;\n if ( *(_BYTE *)(v46 + v44) != *(_BYTE *)(a2 + v44) )\n break;\n ++v45;\n --v44;\n if ( !v39 || !v48 )\n {\n v121 = v45;\n goto LABEL_52;\n }\n }\n v149 = v42;\n v146 = v38;\n v142 = v44;\n v126 = sub_1250(a1, a2, v47, (unsigned int)v44);\n v49 = sub_1250(a1, a2, v39, (unsigned int)(v142 + 1));\n v41 = v13;\n v42 = v149;\n v38 = v146;\n if ( v126 >= v49 )\n v49 = v126;\n v121 = v49 + v45;\n }\n else\n {\n v121 = 0;\n }\nLABEL_52:\n if ( v42 )\n {\n v50 = v13 + 1;\n v51 = (int)v42;\n v52 = v41;\n v53 = 0;\n v54 = v51;\n v55 = v51 - v50 + a1;\n while ( 1 )\n {\n v56 = v54;\n v57 = v52;\n --v54;\n if ( *(_BYTE *)(v55 + v52) != *(_BYTE *)(a2 + v52) )\n break;\n ++v53;\n --v52;\n if ( !v54 || !v57 )\n goto LABEL_60;\n }\n v150 = v38;\n v138 = v53;\n v133 = sub_1250(a1, a2, v56, (unsigned int)v52);\n v58 = sub_1250(a1, a2, v54, (unsigned int)(v52 + 1));\n v59 = v133;\n v38 = v150;\n if ( v133 < v58 )\n v59 = v58;\n v53 = v59 + v138;\n }\n else\n {\n v53 = 0;\n }\nLABEL_60:\n v60 = v121;\n if ( v121 < v53 )\n v60 = v53;\n v38 += v60;\n }\n else\n {\n v38 = 0;\n }\nLABEL_63:\n v61 = v118;\n if ( v118 < v38 )\n v61 = v38;\n v114 = v61 + v113;\n }\n else\n {\n v114 = 0;\n }\nLABEL_67:\n if ( v4 )\n {\n v5 = (int)v5;\n v62 = 0;\n v63 = a1 + (int)v4 - (__int64)((int)v5 + 1);\n while ( 1 )\n {\n v64 = *(_BYTE *)(v63 + v5);\n v65 = v5;\n v66 = v4 - 1;\n v67 = (_DWORD)v5 == 0;\n if ( v64 != v10 )\n break;\n ++v62;\n --v5;\n if ( v4 == 1 || v67 )\n goto LABEL_126;\n v10 = *(_BYTE *)(a2 + v5);\n --v4;\n }\n if ( (_DWORD)v5 )\n {\n v119 = v62;\n v68 = (int)v5 - 1;\n v69 = 0;\n v70 = a1 + (int)v4 - (__int64)(int)v5;\n while ( 1 )\n {\n v71 = v4 - 1;\n v72 = (_DWORD)v68 == 0;\n if ( *(_BYTE *)(a2 + v68) != v64 )\n break;\n ++v69;\n --v68;\n if ( v4 == 1 || v72 )\n {\n v116 = v69;\n v62 = v119;\n goto LABEL_98;\n }\n v64 = *(_BYTE *)(v70 + v68);\n --v4;\n }\n v115 = v69;\n v62 = v119;\n if ( (_DWORD)v68 )\n {\n v73 = 0;\n v74 = (int)v68 - 1;\n v75 = a1 + (int)v4 - (__int64)(int)v68;\n while ( 1 )\n {\n v76 = v4;\n v77 = v74;\n --v4;\n if ( *(_BYTE *)(v75 + v74) != *(_BYTE *)(a2 + v74) )\n break;\n ++v73;\n --v74;\n if ( !v4 || !v77 )\n {\n v62 = v119;\n v120 = v73;\n goto LABEL_87;\n }\n }\n v151 = v71;\n v143 = v74;\n v127 = sub_1250(a1, a2, v76, (unsigned int)v74);\n v78 = sub_1250(a1, a2, v4, (unsigned int)(v143 + 1));\n v65 = v5;\n v71 = v151;\n v62 = v119;\n if ( v127 >= v78 )\n v78 = v127;\n v120 = v78 + v73;\n }\n else\n {\n v120 = 0;\n }\nLABEL_87:\n if ( v71 )\n {\n v79 = (int)v71;\n v80 = (int)v68;\n v81 = 0;\n v82 = (int)v68 + 1;\n v83 = v79;\n v84 = v79 - v82 + a1;\n while ( 1 )\n {\n v85 = v83;\n v86 = v80;\n --v83;\n if ( *(_BYTE *)(v84 + v80) != *(_BYTE *)(a2 + v80) )\n break;\n ++v81;\n --v80;\n if ( !v83 || !v86 )\n goto LABEL_95;\n }\n v152 = v62;\n v139 = v81;\n v134 = v65;\n v128 = sub_1250(a1, a2, v85, (unsigned int)v80);\n v87 = sub_1250(a1, a2, v83, (unsigned int)(v80 + 1));\n v88 = v128;\n v65 = v134;\n v62 = v152;\n if ( v128 < v87 )\n v88 = v87;\n v81 = v88 + v139;\n }\n else\n {\n v81 = 0;\n }\nLABEL_95:\n v89 = v120;\n if ( v120 < v81 )\n v89 = v81;\n v116 = v89 + v115;\n }\n else\n {\n v116 = 0;\n }\nLABEL_98:\n if ( v66 )\n {\n v90 = v65;\n v91 = 0;\n v92 = a1 + (int)v66 - (__int64)((int)v5 + 1);\n while ( 1 )\n {\n v93 = (int)v90;\n v94 = v66 - 1;\n v95 = (_DWORD)v90 == 0;\n if ( *(_BYTE *)(v92 + v90) != v10 )\n break;\n ++v91;\n --v90;\n if ( v66 == 1 || v95 )\n goto LABEL_123;\n v10 = *(_BYTE *)(a2 + v90);\n --v66;\n }\n if ( (_DWORD)v90 )\n {\n v96 = (int)v90 - 1;\n v97 = 0;\n v98 = a1 + (int)v66 - (__int64)(int)v90;\n while ( 1 )\n {\n v99 = v66;\n v100 = v96;\n --v66;\n if ( *(_BYTE *)(v98 + v96) != *(_BYTE *)(a2 + v96) )\n break;\n ++v97;\n --v96;\n if ( !v66 || !v100 )\n goto LABEL_112;\n }\n v140 = v62;\n v135 = v91;\n v129 = v97;\n v122 = sub_1250(a1, a2, v99, (unsigned int)v96);\n v101 = sub_1250(a1, a2, v66, (unsigned int)(v96 + 1));\n v102 = v122;\n v91 = v135;\n v62 = v140;\n if ( v122 < v101 )\n v102 = v101;\n v97 = v102 + v129;\n }\n else\n {\n v97 = 0;\n }\nLABEL_112:\n if ( v94 )\n {\n v103 = 0;\n v104 = (int)v94 - (__int64)((int)v90 + 1) + a1;\n while ( 1 )\n {\n v105 = v94;\n v106 = v93;\n --v94;\n if ( *(_BYTE *)(v104 + v93) != *(_BYTE *)(a2 + v93) )\n break;\n ++v103;\n --v93;\n if ( !v94 || !v106 )\n goto LABEL_120;\n }\n v136 = v62;\n v130 = v91;\n v123 = v97;\n v107 = sub_1250(a1, a2, v105, (unsigned int)v93);\n v108 = sub_1250(a1, a2, v94, (unsigned int)(v93 + 1));\n v97 = v123;\n v91 = v130;\n v62 = v136;\n if ( v107 < v108 )\n v107 = v108;\n v103 += v107;\n }\n else\n {\n v103 = 0;\n }\nLABEL_120:\n if ( v97 < v103 )\n v97 = v103;\n v91 += v97;\n }\n else\n {\n v91 = 0;\n }\nLABEL_123:\n v109 = v116;\n if ( v116 < v91 )\n v109 = v91;\n v62 += v109;\n }\n else\n {\n v62 = 0;\n }\nLABEL_126:\n v110 = v114;\n if ( v114 < v62 )\n v110 = v62;\n v6 += v110;\n }\n else\n {\n return 0;\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1250(long long a1, long long a2, unsigned int a3, int a4) {\n unsigned int v4;\n long long v5;\n unsigned int v6;\n long long v7;\n unsigned int v8;\n char v9;\n char v10;\n bool v11;\n int v12;\n long long v13;\n long long v14;\n char v15;\n unsigned int v16;\n bool v17;\n long long v18;\n int v19;\n long long v20;\n bool v21;\n int v22;\n long long v23;\n long long v24;\n long long v25;\n int v26;\n int v27;\n unsigned int v28;\n int v29;\n long long v30;\n int v31;\n long long v32;\n long long v33;\n int v34;\n int v35;\n int v36;\n long long v37;\n int v38;\n unsigned int v39;\n long long v40;\n int v41;\n unsigned int v42;\n bool v43;\n long long v44;\n int v45;\n long long v46;\n long long v47;\n int v48;\n int v49;\n int v50;\n long long v51;\n long long v52;\n int v53;\n unsigned int v54;\n long long v55;\n long long v56;\n int v57;\n int v58;\n int v59;\n int v60;\n int v61;\n int v62;\n long long v63;\n char v64;\n int v65;\n unsigned int v66;\n bool v67;\n long long v68;\n int v69;\n long long v70;\n unsigned int v71;\n bool v72;\n int v73;\n long long v74;\n long long v75;\n long long v76;\n int v77;\n int v78;\n long long v79;\n long long v80;\n int v81;\n long long v82;\n unsigned int v83;\n long long v84;\n long long v85;\n int v86;\n int v87;\n int v88;\n int v89;\n long long v90;\n int v91;\n long long v92;\n long long v93;\n unsigned int v94;\n bool v95;\n long long v96;\n int v97;\n long long v98;\n long long v99;\n int v100;\n int v101;\n int v102;\n int v103;\n long long v104;\n long long v105;\n int v106;\n int v107;\n int v108;\n int v109;\n int v110;\n int v113;\n int v114;\n int v115;\n int v116;\n int v117;\n int v118;\n int v119;\n int v120;\n int v121;\n int v122;\n int v123;\n unsigned int v124;\n int v125;\n int v126;\n int v127;\n int v128;\n int v129;\n int v130;\n int v131;\n int v132;\n int v133;\n int v134;\n int v135;\n int v136;\n unsigned int v137;\n int v138;\n int v139;\n int v140;\n char v141;\n int v142;\n int v143;\n unsigned int v144;\n int v145;\n int v146;\n int v147;\n unsigned int v148;\n unsigned int v149;\n int v150;\n unsigned int v151;\n int v152;\n char v153;\n int v154;\n int v155;\n int v156;\n if (a3 && a4) {\n v4 = a3;\n v5 = a4 - 1;\n v6 = 0;\n v7 = a1 + (int)a3 - (long long)a4;\n while (1) {\n v8 = v4;\n v9 = *(uint8_t *)(v7 + v5);\n --v4;\n v10 = *(uint8_t *)(a2 + v5);\n v11 = (uint32_t)v5 == 0;\n if (v9 != v10) break;\n ++v6;\n --v5;\n if (!v4 || v11) return v6;\n }\n if ((uint32_t)v5) {\n v12 = 0;\n v13 = (int)v5 - 1;\n v14 = a1 + (int)v8 - (long long)(int)v5;\n while (1) {\n v15 = *(uint8_t *)(a2 + v13);\n v16 = v8 - 1;\n v17 = (uint32_t)v13 == 0;\n if (v15 != v9) break;\n ++v12;\n --v13;\n if (v8 == 1 || v17) {\n v114 = v12;\n goto LABEL_67;\n }\n v9 = *(uint8_t *)(v14 + v13);\n --v8;\n }\n v113 = v12;\n if ((uint32_t)v13) {\n v124 = v4;\n v18 = (int)v13 - 1;\n v19 = 0;\n v20 = a1 + (int)v8 - (long long)(int)v13;\n while (1) {\n v21 = (uint32_t)v18 == 0;\n if (*(uint8_t *)(a2 + v18) != v9) break;\n ++v19;\n --v18;\n if (v8 == 1 || v21) {\n v118 = v19;\n v4 = v124;\n goto LABEL_38;\n }\n v9 = *(uint8_t *)(v20 + v18);\n --v8;\n }\n v117 = v19;\n v137 = v8 - 1;\n v4 = v124;\n v147 = v18;\n if ((uint32_t)v18) {\n v22 = 0;\n v23 = (int)v18 - 1;\n v24 = a1 + (int)v8 - (long long)(int)v18;\n while (1) {\n v25 = v8;\n v26 = v23;\n --v8;\n if (*(uint8_t *)(v24 + v23) != *(uint8_t *)(a2 + v23)) break;\n ++v22;\n --v23;\n if (!v8 || !v26) {\n v125 = v22;\n goto LABEL_27;\n }\n }\n v156 = v18;\n v153 = *(uint8_t *)(a2 + v13);\n v144 = v16;\n v155 = v23;\n v131 = sub_1250(a1, a2, v25, (unsigned int)v23);\n v27 = sub_1250(a1, a2, v8, (unsigned int)(v155 + 1));\n v16 = v144;\n v15 = v153;\n LODWORD(v18) = v156;\n if (v131 >= v27) v27 = v131;\n v125 = v27 + v22;\n } else {\n v125 = 0;\n }\n LABEL_27:\n v28 = v137;\n if (v137) {\n v29 = v18 + 1;\n v30 = v147;\n v31 = 0;\n v32 = (int)v137 - (long long)v29 + a1;\n while (1) {\n v33 = v28;\n v34 = v30;\n --v28;\n if (*(uint8_t *)(v32 + v30) != *(uint8_t *)(a2 + v30)) break;\n ++v31;\n --v30;\n if (!v28 || !v34) goto LABEL_35;\n }\n v154 = v31;\n v141 = v15;\n v148 = v16;\n v145 = v30;\n v132 = sub_1250(a1, a2, v33, (unsigned int)v30);\n v35 = sub_1250(a1, a2, v28, (unsigned int)(v145 + 1));\n v16 = v148;\n v15 = v141;\n if (v132 >= v35) v35 = v132;\n v31 = v35 + v154;\n } else {\n v31 = 0;\n }\n LABEL_35:\n v36 = v125;\n if (v125 < v31) v36 = v31;\n v118 = v36 + v117;\n } else {\n v118 = 0;\n }\n LABEL_38:\n if (v16) {\n v37 = (int)v16;\n v13 = (int)v13;\n v38 = 0;\n v39 = v37;\n v40 = a1 + v37 - ((int)v13 + 1);\n while (1) {\n v41 = v13;\n v42 = v39 - 1;\n v43 = (uint32_t)v13 == 0;\n if (*(uint8_t *)(v40 + v13) != v15) break;\n ++v38;\n --v13;\n if (v39 == 1 || v43) goto LABEL_63;\n v15 = *(uint8_t *)(a2 + v13);\n --v39;\n }\n if ((uint32_t)v13) {\n v44 = (int)v13 - 1;\n v45 = 0;\n v46 = a1 + (int)v39 - (long long)(int)v13;\n while (1) {\n v47 = v39;\n v48 = v44;\n --v39;\n if (*(uint8_t *)(v46 + v44) != *(uint8_t *)(a2 + v44)) break;\n ++v45;\n --v44;\n if (!v39 || !v48) {\n v121 = v45;\n goto LABEL_52;\n }\n }\n v149 = v42;\n v146 = v38;\n v142 = v44;\n v126 = sub_1250(a1, a2, v47, (unsigned int)v44);\n v49 = sub_1250(a1, a2, v39, (unsigned int)(v142 + 1));\n v41 = v13;\n v42 = v149;\n v38 = v146;\n if (v126 >= v49) v49 = v126;\n v121 = v49 + v45;\n } else {\n v121 = 0;\n }\n LABEL_52:\n if (v42) {\n v50 = v13 + 1;\n v51 = (int)v42;\n v52 = v41;\n v53 = 0;\n v54 = v51;\n v55 = v51 - v50 + a1;\n while (1) {\n v56 = v54;\n v57 = v52;\n --v54;\n if (*(uint8_t *)(v55 + v52) != *(uint8_t *)(a2 + v52)) break;\n ++v53;\n --v52;\n if (!v54 || !v57) goto LABEL_60;\n }\n v150 = v38;\n v138 = v53;\n v133 = sub_1250(a1, a2, v56, (unsigned int)v52);\n v58 = sub_1250(a1, a2, v54, (unsigned int)(v52 + 1));\n v59 = v133;\n v38 = v150;\n if (v133 < v58) v59 = v58;\n v53 = v59 + v138;\n } else {\n v53 = 0;\n }\n LABEL_60:\n v60 = v121;\n if (v121 < v53) v60 = v53;\n v38 += v60;\n } else {\n v38 = 0;\n }\n LABEL_63:\n v61 = v118;\n if (v118 < v38) v61 = v38;\n v114 = v61 + v113;\n } else {\n v114 = 0;\n }\n LABEL_67:\n if (v4) {\n v5 = (int)v5;\n v62 = 0;\n v63 = a1 + (int)v4 - (long long)((int)v5 + 1);\n while (1) {\n v64 = *(uint8_t *)(v63 + v5);\n v65 = v5;\n v66 = v4 - 1;\n v67 = (uint32_t)v5 == 0;\n if (v64 != v10) break;\n ++v62;\n --v5;\n if (v4 == 1 || v67) goto LABEL_126;\n v10 = *(uint8_t *)(a2 + v5);\n --v4;\n }\n if ((uint32_t)v5) {\n v119 = v62;\n v68 = (int)v5 - 1;\n v69 = 0;\n v70 = a1 + (int)v4 - (long long)(int)v5;\n while (1) {\n v71 = v4 - 1;\n v72 = (uint32_t)v68 == 0;\n if (*(uint8_t *)(a2 + v68) != v64) break;\n ++v69;\n --v68;\n if (v4 == 1 || v72) {\n v116 = v69;\n v62 = v119;\n goto LABEL_98;\n }\n v64 = *(uint8_t *)(v70 + v68);\n --v4;\n }\n v115 = v69;\n v62 = v119;\n if ((uint32_t)v68) {\n v73 = 0;\n v74 = (int)v68 - 1;\n v75 = a1 + (int)v4 - (long long)(int)v68;\n while (1) {\n v76 = v4;\n v77 = v74;\n --v4;\n if (*(uint8_t *)(v75 + v74) != *(uint8_t *)(a2 + v74)) break;\n ++v73;\n --v74;\n if (!v4 || !v77) {\n v62 = v119;\n v120 = v73;\n goto LABEL_87;\n }\n }\n v151 = v71;\n v143 = v74;\n v127 = sub_1250(a1, a2, v76, (unsigned int)v74);\n v78 = sub_1250(a1, a2, v4, (unsigned int)(v143 + 1));\n v65 = v5;\n v71 = v151;\n v62 = v119;\n if (v127 >= v78) v78 = v127;\n v120 = v78 + v73;\n } else {\n v120 = 0;\n }\n LABEL_87:\n if (v71) {\n v79 = (int)v71;\n v80 = (int)v68;\n v81 = 0;\n v82 = (int)v68 + 1;\n v83 = v79;\n v84 = v79 - v82 + a1;\n while (1) {\n v85 = v83;\n v86 = v80;\n --v83;\n if (*(uint8_t *)(v84 + v80) != *(uint8_t *)(a2 + v80)) break;\n ++v81;\n --v80;\n if (!v83 || !v86) goto LABEL_95;\n }\n v152 = v62;\n v139 = v81;\n v134 = v65;\n v128 = sub_1250(a1, a2, v85, (unsigned int)v80);\n v87 = sub_1250(a1, a2, v83, (unsigned int)(v80 + 1));\n v88 = v128;\n v65 = v134;\n v62 = v152;\n if (v128 < v87) v88 = v87;\n v81 = v88 + v139;\n } else {\n v81 = 0;\n }\n LABEL_95:\n v89 = v120;\n if (v120 < v81) v89 = v81;\n v116 = v89 + v115;\n } else {\n v116 = 0;\n }\n LABEL_98:\n if (v66) {\n v90 = v65;\n v91 = 0;\n v92 = a1 + (int)v66 - (long long)((int)v5 + 1);\n while (1) {\n v93 = (int)v90;\n v94 = v66 - 1;\n v95 = (uint32_t)v90 == 0;\n if (*(uint8_t *)(v92 + v90) != v10) break;\n ++v91;\n --v90;\n if (v66 == 1 || v95) goto LABEL_123;\n v10 = *(uint8_t *)(a2 + v90);\n --v66;\n }\n if ((uint32_t)v90) {\n v96 = (int)v90 - 1;\n v97 = 0;\n v98 = a1 + (int)v66 - (long long)(int)v90;\n while (1) {\n v99 = v66;\n v100 = v96;\n --v66;\n if (*(uint8_t *)(v98 + v96) != *(uint8_t *)(a2 + v96)) break;\n ++v97;\n --v96;\n if (!v66 || !v100) goto LABEL_112;\n }\n v140 = v62;\n v135 = v91;\n v129 = v97;\n v122 = sub_1250(a1, a2, v99, (unsigned int)v96);\n v101 = sub_1250(a1, a2, v66, (unsigned int)(v96 + 1));\n v102 = v122;\n v91 = v135;\n v62 = v140;\n if (v122 < v101) v102 = v101;\n v97 = v102 + v129;\n } else {\n v97 = 0;\n }\n LABEL_112:\n if (v94) {\n v103 = 0;\n v104 = (int)v94 - (long long)((int)v90 + 1) + a1;\n while (1) {\n v105 = v94;\n v106 = v93;\n --v94;\n if (*(uint8_t *)(v104 + v93) != *(uint8_t *)(a2 + v93)) break;\n ++v103;\n --v93;\n if (!v94 || !v106) goto LABEL_120;\n }\n v136 = v62;\n v130 = v91;\n v123 = v97;\n v107 = sub_1250(a1, a2, v105, (unsigned int)v93);\n v108 = sub_1250(a1, a2, v94, (unsigned int)(v93 + 1));\n v97 = v123;\n v91 = v130;\n v62 = v136;\n if (v107 < v108) v107 = v108;\n v103 += v107;\n } else {\n v103 = 0;\n }\n LABEL_120:\n if (v97 < v103) v97 = v103;\n v91 += v97;\n } else {\n v91 = 0;\n }\n LABEL_123:\n v109 = v116;\n if (v116 < v91) v109 = v91;\n v62 += v109;\n } else {\n v62 = 0;\n }\n LABEL_126:\n v110 = v114;\n if (v114 < v62) v110 = v62;\n v6 += v110;\n } else {\n return 0;\n }\n return v6;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, unsigned int a3, int a4) {\n unsigned int v4;\n long long v5;\n unsigned int v6;\n long long v7;\n unsigned int v8;\n char v9;\n char v10;\n bool v11;\n int v12;\n long long v13;\n long long v14;\n char v15;\n unsigned int v16;\n bool v17;\n long long v18;\n int v19;\n long long v20;\n bool v21;\n int v22;\n long long v23;\n long long v24;\n long long v25;\n int v26;\n int v27;\n unsigned int v28;\n int v29;\n long long v30;\n int v31;\n long long v32;\n long long v33;\n int v34;\n int v35;\n int v36;\n long long v37;\n int v38;\n unsigned int v39;\n long long v40;\n int v41;\n unsigned int v42;\n bool v43;\n long long v44;\n int v45;\n long long v46;\n long long v47;\n int v48;\n int v49;\n int v50;\n long long v51;\n long long v52;\n int v53;\n unsigned int v54;\n long long v55;\n long long v56;\n int v57;\n int v58;\n int v59;\n int v60;\n int v61;\n int v62;\n long long v63;\n char v64;\n int v65;\n unsigned int v66;\n bool v67;\n long long v68;\n int v69;\n long long v70;\n unsigned int v71;\n bool v72;\n int v73;\n long long v74;\n long long v75;\n long long v76;\n int v77;\n int v78;\n long long v79;\n long long v80;\n int v81;\n long long v82;\n unsigned int v83;\n long long v84;\n long long v85;\n int v86;\n int v87;\n int v88;\n int v89;\n long long v90;\n int v91;\n long long v92;\n long long v93;\n unsigned int v94;\n bool v95;\n long long v96;\n int v97;\n long long v98;\n long long v99;\n int v100;\n int v101;\n int v102;\n int v103;\n long long v104;\n long long v105;\n int v106;\n int v107;\n int v108;\n int v109;\n int v110;\n int v113;\n int v114;\n int v115;\n int v116;\n int v117;\n int v118;\n int v119;\n int v120;\n int v121;\n int v122;\n int v123;\n unsigned int v124;\n int v125;\n int v126;\n int v127;\n int v128;\n int v129;\n int v130;\n int v131;\n int v132;\n int v133;\n int v134;\n int v135;\n int v136;\n unsigned int v137;\n int v138;\n int v139;\n int v140;\n char v141;\n int v142;\n int v143;\n unsigned int v144;\n int v145;\n int v146;\n int v147;\n unsigned int v148;\n unsigned int v149;\n int v150;\n unsigned int v151;\n int v152;\n char v153;\n int v154;\n int v155;\n int v156;\n if (a3 && a4) {\n v4 = a3;\n v5 = a4 - 1;\n v6 = 0;\n v7 = a1 + (int)a3 - (long long)a4;\n while (1) {\n v8 = v4;\n v9 = *(uint8_t *)(v7 + v5);\n --v4;\n v10 = *(uint8_t *)(a2 + v5);\n v11 = (uint32_t)v5 == 0;\n if (v9 != v10) break;\n ++v6;\n --v5;\n if (!v4 || v11) return v6;\n }\n if ((uint32_t)v5) {\n v12 = 0;\n v13 = (int)v5 - 1;\n v14 = a1 + (int)v8 - (long long)(int)v5;\n while (1) {\n v15 = *(uint8_t *)(a2 + v13);\n v16 = v8 - 1;\n v17 = (uint32_t)v13 == 0;\n if (v15 != v9) break;\n ++v12;\n --v13;\n if (v8 == 1 || v17) {\n v114 = v12;\n goto LABEL_67;\n }\n v9 = *(uint8_t *)(v14 + v13);\n --v8;\n }\n v113 = v12;\n if ((uint32_t)v13) {\n v124 = v4;\n v18 = (int)v13 - 1;\n v19 = 0;\n v20 = a1 + (int)v8 - (long long)(int)v13;\n while (1) {\n v21 = (uint32_t)v18 == 0;\n if (*(uint8_t *)(a2 + v18) != v9) break;\n ++v19;\n --v18;\n if (v8 == 1 || v21) {\n v118 = v19;\n v4 = v124;\n goto LABEL_38;\n }\n v9 = *(uint8_t *)(v20 + v18);\n --v8;\n }\n v117 = v19;\n v137 = v8 - 1;\n v4 = v124;\n v147 = v18;\n if ((uint32_t)v18) {\n v22 = 0;\n v23 = (int)v18 - 1;\n v24 = a1 + (int)v8 - (long long)(int)v18;\n while (1) {\n v25 = v8;\n v26 = v23;\n --v8;\n if (*(uint8_t *)(v24 + v23) != *(uint8_t *)(a2 + v23)) break;\n ++v22;\n --v23;\n if (!v8 || !v26) {\n v125 = v22;\n goto LABEL_27;\n }\n }\n v156 = v18;\n v153 = *(uint8_t *)(a2 + v13);\n v144 = v16;\n v155 = v23;\n v131 = func0(a1, a2, v25, (unsigned int)v23);\n v27 = func0(a1, a2, v8, (unsigned int)(v155 + 1));\n v16 = v144;\n v15 = v153;\n LODWORD(v18) = v156;\n if (v131 >= v27) v27 = v131;\n v125 = v27 + v22;\n } else {\n v125 = 0;\n }\n LABEL_27:\n v28 = v137;\n if (v137) {\n v29 = v18 + 1;\n v30 = v147;\n v31 = 0;\n v32 = (int)v137 - (long long)v29 + a1;\n while (1) {\n v33 = v28;\n v34 = v30;\n --v28;\n if (*(uint8_t *)(v32 + v30) != *(uint8_t *)(a2 + v30)) break;\n ++v31;\n --v30;\n if (!v28 || !v34) goto LABEL_35;\n }\n v154 = v31;\n v141 = v15;\n v148 = v16;\n v145 = v30;\n v132 = func0(a1, a2, v33, (unsigned int)v30);\n v35 = func0(a1, a2, v28, (unsigned int)(v145 + 1));\n v16 = v148;\n v15 = v141;\n if (v132 >= v35) v35 = v132;\n v31 = v35 + v154;\n } else {\n v31 = 0;\n }\n LABEL_35:\n v36 = v125;\n if (v125 < v31) v36 = v31;\n v118 = v36 + v117;\n } else {\n v118 = 0;\n }\n LABEL_38:\n if (v16) {\n v37 = (int)v16;\n v13 = (int)v13;\n v38 = 0;\n v39 = v37;\n v40 = a1 + v37 - ((int)v13 + 1);\n while (1) {\n v41 = v13;\n v42 = v39 - 1;\n v43 = (uint32_t)v13 == 0;\n if (*(uint8_t *)(v40 + v13) != v15) break;\n ++v38;\n --v13;\n if (v39 == 1 || v43) goto LABEL_63;\n v15 = *(uint8_t *)(a2 + v13);\n --v39;\n }\n if ((uint32_t)v13) {\n v44 = (int)v13 - 1;\n v45 = 0;\n v46 = a1 + (int)v39 - (long long)(int)v13;\n while (1) {\n v47 = v39;\n v48 = v44;\n --v39;\n if (*(uint8_t *)(v46 + v44) != *(uint8_t *)(a2 + v44)) break;\n ++v45;\n --v44;\n if (!v39 || !v48) {\n v121 = v45;\n goto LABEL_52;\n }\n }\n v149 = v42;\n v146 = v38;\n v142 = v44;\n v126 = func0(a1, a2, v47, (unsigned int)v44);\n v49 = func0(a1, a2, v39, (unsigned int)(v142 + 1));\n v41 = v13;\n v42 = v149;\n v38 = v146;\n if (v126 >= v49) v49 = v126;\n v121 = v49 + v45;\n } else {\n v121 = 0;\n }\n LABEL_52:\n if (v42) {\n v50 = v13 + 1;\n v51 = (int)v42;\n v52 = v41;\n v53 = 0;\n v54 = v51;\n v55 = v51 - v50 + a1;\n while (1) {\n v56 = v54;\n v57 = v52;\n --v54;\n if (*(uint8_t *)(v55 + v52) != *(uint8_t *)(a2 + v52)) break;\n ++v53;\n --v52;\n if (!v54 || !v57) goto LABEL_60;\n }\n v150 = v38;\n v138 = v53;\n v133 = func0(a1, a2, v56, (unsigned int)v52);\n v58 = func0(a1, a2, v54, (unsigned int)(v52 + 1));\n v59 = v133;\n v38 = v150;\n if (v133 < v58) v59 = v58;\n v53 = v59 + v138;\n } else {\n v53 = 0;\n }\n LABEL_60:\n v60 = v121;\n if (v121 < v53) v60 = v53;\n v38 += v60;\n } else {\n v38 = 0;\n }\n LABEL_63:\n v61 = v118;\n if (v118 < v38) v61 = v38;\n v114 = v61 + v113;\n } else {\n v114 = 0;\n }\n LABEL_67:\n if (v4) {\n v5 = (int)v5;\n v62 = 0;\n v63 = a1 + (int)v4 - (long long)((int)v5 + 1);\n while (1) {\n v64 = *(uint8_t *)(v63 + v5);\n v65 = v5;\n v66 = v4 - 1;\n v67 = (uint32_t)v5 == 0;\n if (v64 != v10) break;\n ++v62;\n --v5;\n if (v4 == 1 || v67) goto LABEL_126;\n v10 = *(uint8_t *)(a2 + v5);\n --v4;\n }\n if ((uint32_t)v5) {\n v119 = v62;\n v68 = (int)v5 - 1;\n v69 = 0;\n v70 = a1 + (int)v4 - (long long)(int)v5;\n while (1) {\n v71 = v4 - 1;\n v72 = (uint32_t)v68 == 0;\n if (*(uint8_t *)(a2 + v68) != v64) break;\n ++v69;\n --v68;\n if (v4 == 1 || v72) {\n v116 = v69;\n v62 = v119;\n goto LABEL_98;\n }\n v64 = *(uint8_t *)(v70 + v68);\n --v4;\n }\n v115 = v69;\n v62 = v119;\n if ((uint32_t)v68) {\n v73 = 0;\n v74 = (int)v68 - 1;\n v75 = a1 + (int)v4 - (long long)(int)v68;\n while (1) {\n v76 = v4;\n v77 = v74;\n --v4;\n if (*(uint8_t *)(v75 + v74) != *(uint8_t *)(a2 + v74)) break;\n ++v73;\n --v74;\n if (!v4 || !v77) {\n v62 = v119;\n v120 = v73;\n goto LABEL_87;\n }\n }\n v151 = v71;\n v143 = v74;\n v127 = func0(a1, a2, v76, (unsigned int)v74);\n v78 = func0(a1, a2, v4, (unsigned int)(v143 + 1));\n v65 = v5;\n v71 = v151;\n v62 = v119;\n if (v127 >= v78) v78 = v127;\n v120 = v78 + v73;\n } else {\n v120 = 0;\n }\n LABEL_87:\n if (v71) {\n v79 = (int)v71;\n v80 = (int)v68;\n v81 = 0;\n v82 = (int)v68 + 1;\n v83 = v79;\n v84 = v79 - v82 + a1;\n while (1) {\n v85 = v83;\n v86 = v80;\n --v83;\n if (*(uint8_t *)(v84 + v80) != *(uint8_t *)(a2 + v80)) break;\n ++v81;\n --v80;\n if (!v83 || !v86) goto LABEL_95;\n }\n v152 = v62;\n v139 = v81;\n v134 = v65;\n v128 = func0(a1, a2, v85, (unsigned int)v80);\n v87 = func0(a1, a2, v83, (unsigned int)(v80 + 1));\n v88 = v128;\n v65 = v134;\n v62 = v152;\n if (v128 < v87) v88 = v87;\n v81 = v88 + v139;\n } else {\n v81 = 0;\n }\n LABEL_95:\n v89 = v120;\n if (v120 < v81) v89 = v81;\n v116 = v89 + v115;\n } else {\n v116 = 0;\n }\n LABEL_98:\n if (v66) {\n v90 = v65;\n v91 = 0;\n v92 = a1 + (int)v66 - (long long)((int)v5 + 1);\n while (1) {\n v93 = (int)v90;\n v94 = v66 - 1;\n v95 = (uint32_t)v90 == 0;\n if (*(uint8_t *)(v92 + v90) != v10) break;\n ++v91;\n --v90;\n if (v66 == 1 || v95) goto LABEL_123;\n v10 = *(uint8_t *)(a2 + v90);\n --v66;\n }\n if ((uint32_t)v90) {\n v96 = (int)v90 - 1;\n v97 = 0;\n v98 = a1 + (int)v66 - (long long)(int)v90;\n while (1) {\n v99 = v66;\n v100 = v96;\n --v66;\n if (*(uint8_t *)(v98 + v96) != *(uint8_t *)(a2 + v96)) break;\n ++v97;\n --v96;\n if (!v66 || !v100) goto LABEL_112;\n }\n v140 = v62;\n v135 = v91;\n v129 = v97;\n v122 = func0(a1, a2, v99, (unsigned int)v96);\n v101 = func0(a1, a2, v66, (unsigned int)(v96 + 1));\n v102 = v122;\n v91 = v135;\n v62 = v140;\n if (v122 < v101) v102 = v101;\n v97 = v102 + v129;\n } else {\n v97 = 0;\n }\n LABEL_112:\n if (v94) {\n v103 = 0;\n v104 = (int)v94 - (long long)((int)v90 + 1) + a1;\n while (1) {\n v105 = v94;\n v106 = v93;\n --v94;\n if (*(uint8_t *)(v104 + v93) != *(uint8_t *)(a2 + v93)) break;\n ++v103;\n --v93;\n if (!v94 || !v106) goto LABEL_120;\n }\n v136 = v62;\n v130 = v91;\n v123 = v97;\n v107 = func0(a1, a2, v105, (unsigned int)v93);\n v108 = func0(a1, a2, v94, (unsigned int)(v93 + 1));\n v97 = v123;\n v91 = v130;\n v62 = v136;\n if (v107 < v108) v107 = v108;\n v103 += v107;\n } else {\n v103 = 0;\n }\n LABEL_120:\n if (v97 < v103) v97 = v103;\n v91 += v97;\n } else {\n v91 = 0;\n }\n LABEL_123:\n v109 = v116;\n if (v116 < v91) v109 = v91;\n v62 += v109;\n } else {\n v62 = 0;\n }\n LABEL_126:\n v110 = v114;\n if (v114 < v62) v110 = v62;\n v6 += v110;\n } else {\n return 0;\n }\n return v6;\n}" + }, + { + "index": 188, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int n) {\n for (int i = 2; i <= n; i++) {\n if (i * i < (n + 1)) {\n for (int j = 2; j <= n; j++) {\n if ((i * i * j * j) == n) {\n return true;\n }\n }\n }\n }\n return false;\n}", + "test": "int main() {\n\n assert(func0(25) == false);\n\n assert(func0(30) == false);\n\n assert(func0(16) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmovl $0x2,-0x8(%rbp)\njmp 119b \nmov -0x8(%rbp),%eax\nimul %eax,%eax\ncmp %eax,-0x14(%rbp)\njl 1197 \nmovl $0x2,-0x4(%rbp)\njmp 118f \nmov -0x8(%rbp),%eax\nimul %eax,%eax\nimul -0x4(%rbp),%eax\nimul -0x4(%rbp),%eax\ncmp %eax,-0x14(%rbp)\njne 118b \nmov $0x1,%eax\njmp 11a8 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x14(%rbp),%eax\njle 1171 \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x14(%rbp),%eax\njle 115d \nmov $0x0,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_8], 2\njmp short loc_119B\nloc_115D:\nmov eax, [rbp+var_8]\nimul eax, eax\ncmp [rbp+var_14], eax\njl short loc_1197\nmov [rbp+var_4], 2\njmp short loc_118F\nloc_1171:\nmov eax, [rbp+var_8]\nimul eax, eax\nimul eax, [rbp+var_4]\nimul eax, [rbp+var_4]\ncmp [rbp+var_14], eax\njnz short loc_118B\nmov eax, 1\njmp short loc_11A8\nloc_118B:\nadd [rbp+var_4], 1\nloc_118F:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_14]\njle short loc_1171\nloc_1197:\nadd [rbp+var_8], 1\nloc_119B:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_14]\njle short loc_115D\nmov eax, 0\nloc_11A8:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int i; // [rsp+Ch] [rbp-8h]\n int j; // [rsp+10h] [rbp-4h]\n\n for ( i = 2; i <= a1; ++i )\n {\n if ( a1 >= i * i )\n {\n for ( j = 2; j <= a1; ++j )\n {\n if ( a1 == j * j * i * i )\n return 1LL;\n }\n }\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_8], 2\njmp short loc_119B\nloc_115D:\nmov eax, [rbp+var_8]\nimul eax, eax\ncmp [rbp+var_14], eax\njl short loc_1197\nmov [rbp+var_4], 2\njmp short loc_118F\nloc_1171:\nmov eax, [rbp+var_8]\nimul eax, eax\nimul eax, [rbp+var_4]\nimul eax, [rbp+var_4]\ncmp [rbp+var_14], eax\njnz short loc_118B\nmov eax, 1\njmp short loc_11A8\nloc_118B:\nadd [rbp+var_4], 1\nloc_118F:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_14]\njle short loc_1171\nloc_1197:\nadd [rbp+var_8], 1\nloc_119B:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_14]\njle short loc_115D\nmov eax, 0\nloc_11A8:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int i; // [rsp+Ch] [rbp-8h]\n int j; // [rsp+10h] [rbp-4h]\n\n for ( i = 2; i <= a1; ++i )\n {\n if ( a1 >= i * i )\n {\n for ( j = 2; j <= a1; ++j )\n {\n if ( a1 == j * j * i * i )\n return 1LL;\n }\n }\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int i;\n int j;\n for (i = 2; i <= a1; ++i) {\n if (a1 >= i * i) {\n for (j = 2; j <= a1; ++j) {\n if (a1 == j * j * i * i) return 1LL;\n }\n }\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int i;\n int j;\n for (i = 2; i <= a1; ++i) {\n if (a1 >= i * i) {\n for (j = 2; j <= a1; ++j) {\n if (a1 == j * j * i * i) return 1LL;\n }\n }\n }\n return 0LL;\n}" + }, + { + "index": 188, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int n) {\n for (int i = 2; i <= n; i++) {\n if (i * i < (n + 1)) {\n for (int j = 2; j <= n; j++) {\n if ((i * i * j * j) == n) {\n return true;\n }\n }\n }\n }\n return false;\n}", + "test": "int main() {\n\n assert(func0(25) == false);\n\n assert(func0(30) == false);\n\n assert(func0(16) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%edi\njle 119e \nmov $0x2,%ecx\njmp 1160 \nadd $0x1,%ecx\ncmp %ecx,%edi\njl 1198 \nmov %ecx,%eax\nimul %ecx,%eax\ncmp %edi,%eax\njg 1159 \nlea 0x0(,%rax,4),%edx\ncmp %edx,%edi\nje 11a4 \nmov %eax,%r8d\nlea (%rax,%rax,2),%edx\nmov $0x2,%eax\nadd $0x1,%eax\ncmp %eax,%edi\njl 1159 \nmov %edx,%esi\nimul %eax,%esi\nadd %r8d,%edx\ncmp %edi,%esi\njne 117f \nmov $0x1,%eax\nretq\nmov $0x0,%eax\nretq\nmov $0x0,%eax\nretq\nmov $0x1,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ncmp edi, 1\njle short loc_119D\nmov esi, 2\njmp short loc_1160\nloc_1159:\nadd esi, 1\ncmp edi, esi\njl short loc_1197\nloc_1160:\nmov ecx, esi\nimul ecx, esi\ncmp ecx, edi\njg short loc_1159\nlea eax, ds:0[rcx*4]\ncmp edi, eax\njz short loc_11A3\nlea edx, [rcx+rcx*2]\nmov eax, 2\nloc_117C:\nadd eax, 1\ncmp edi, eax\njl short loc_1159\nmov r8d, edx\nimul r8d, eax\nadd edx, ecx\ncmp r8d, edi\njnz short loc_117C\nmov eax, 1\nretn\nloc_1197:\nmov eax, 0\nretn\nloc_119D:\nmov eax, 0\nretn\nloc_11A3:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // esi\n int v2; // ecx\n int v3; // edx\n int v4; // eax\n int v5; // r8d\n\n if ( a1 <= 1 )\n return 0LL;\n v1 = 2;\n while ( 1 )\n {\n v2 = v1 * v1;\n if ( v1 * v1 <= a1 )\n break;\nLABEL_3:\n if ( a1 < ++v1 )\n return 0LL;\n }\n if ( a1 != 4 * v2 )\n {\n v3 = 3 * v2;\n v4 = 2;\n while ( a1 >= ++v4 )\n {\n v5 = v4 * v3;\n v3 += v2;\n if ( v5 == a1 )\n return 1LL;\n }\n goto LABEL_3;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ncmp edi, 1\njle short loc_119D\nmov esi, 2\njmp short loc_1160\nloc_1159:\nadd esi, 1\ncmp edi, esi\njl short loc_1197\nloc_1160:\nmov ecx, esi\nimul ecx, esi\ncmp ecx, edi\njg short loc_1159\nlea eax, ds:0[rcx*4]\ncmp edi, eax\njz short loc_11A3\nlea edx, [rcx+rcx*2]\nmov eax, 2\nloc_117C:\nadd eax, 1\ncmp edi, eax\njl short loc_1159\nmov r8d, edx\nimul r8d, eax\nadd edx, ecx\ncmp r8d, edi\njnz short loc_117C\nmov eax, 1\nretn\nloc_1197:\nmov eax, 0\nretn\nloc_119D:\nmov eax, 0\nretn\nloc_11A3:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v1; // esi\n int v2; // ecx\n int v3; // edx\n int v4; // eax\n int v5; // r8d\n\n if ( a1 <= 1 )\n return 0LL;\n v1 = 2;\n while ( 1 )\n {\n v2 = v1 * v1;\n if ( v1 * v1 <= a1 )\n break;\nLABEL_3:\n if ( a1 < ++v1 )\n return 0LL;\n }\n if ( a1 != 4 * v2 )\n {\n v3 = 3 * v2;\n v4 = 2;\n while ( a1 >= ++v4 )\n {\n v5 = v4 * v3;\n v3 += v2;\n if ( v5 == a1 )\n return 1LL;\n }\n goto LABEL_3;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v1;\n int v2;\n int v3;\n int v4;\n int v5;\n if (a1 <= 1) return 0LL;\n v1 = 2;\n while (1) {\n v2 = v1 * v1;\n if (v1 * v1 <= a1) break;\n LABEL_3:\n if (a1 < ++v1) return 0LL;\n }\n if (a1 != 4 * v2) {\n v3 = 3 * v2;\n v4 = 2;\n while (a1 >= ++v4) {\n v5 = v4 * v3;\n v3 += v2;\n if (v5 == a1) return 1LL;\n }\n goto LABEL_3;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v2;\n int v3;\n int v4;\n int v5;\n if (a1 <= 1) return 0LL;\n v1 = 2;\n while (1) {\n v2 = v1 * v1;\n if (v1 * v1 <= a1) break;\n LABEL_3:\n if (a1 < ++v1) return 0LL;\n }\n if (a1 != 4 * v2) {\n v3 = 3 * v2;\n v4 = 2;\n while (a1 >= ++v4) {\n v5 = v4 * v3;\n v3 += v2;\n if (v5 == a1) return 1LL;\n }\n goto LABEL_3;\n }\n return 1LL;\n}" + }, + { + "index": 188, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int n) {\n for (int i = 2; i <= n; i++) {\n if (i * i < (n + 1)) {\n for (int j = 2; j <= n; j++) {\n if ((i * i * j * j) == n) {\n return true;\n }\n }\n }\n }\n return false;\n}", + "test": "int main() {\n\n assert(func0(25) == false);\n\n assert(func0(30) == false);\n\n assert(func0(16) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%edi\njle 1278 \nmov $0x2,%ecx\njmp 1237 \nadd $0x1,%ecx\ncmp %ecx,%edi\njl 1278 \nmov %ecx,%esi\nimul %ecx,%esi\ncmp %edi,%esi\njg 1230 \nlea 0x0(,%rsi,4),%eax\ncmp %eax,%edi\nje 126d \nlea (%rsi,%rsi,2),%edx\nmov $0x3,%eax\njmp 1261 \nnopl (%rax)\nadd $0x1,%eax\nadd %esi,%edx\ncmp %eax,%edi\njl 1230 \nmov %edx,%r8d\nimul %eax,%r8d\ncmp %edi,%r8d\njne 1258 \nmov $0x1,%eax\nretq\nnopl 0x0(%rax,%rax,1)\nxor %eax,%eax\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ncmp edi, 1\njle short loc_1248\nmov esi, 2\njmp short loc_1207\nloc_1200:\nadd esi, 1\ncmp edi, esi\njl short loc_1248\nloc_1207:\nmov ecx, esi\nimul ecx, esi\ncmp ecx, edi\njg short loc_1200\nlea eax, ds:0[rcx*4]\ncmp edi, eax\njz short loc_123D\nlea edx, [rcx+rcx*2]\nmov eax, 2\nnop dword ptr [rax+rax+00h]\nloc_1228:\nadd eax, 1\ncmp edi, eax\njl short loc_1200\nmov r8d, edx\nadd edx, ecx\nimul r8d, eax\ncmp r8d, edi\njnz short loc_1228\nloc_123D:\nmov eax, 1\nretn\nloc_1248:\nxor eax, eax\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int i; // esi\n int v2; // ecx\n int v3; // edx\n int v4; // eax\n int v5; // r8d\n\n if ( a1 > 1 )\n {\n for ( i = 2; a1 >= i; ++i )\n {\n v2 = i * i;\n if ( i * i <= a1 )\n {\n if ( a1 == 4 * v2 )\n return 1LL;\n v3 = 3 * v2;\n v4 = 2;\n while ( a1 >= ++v4 )\n {\n v5 = v3;\n v3 += v2;\n if ( v4 * v5 == a1 )\n return 1LL;\n }\n }\n }\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_11F0:\nendbr64\ncmp edi, 1\njle short loc_1248\nmov esi, 2\njmp short loc_1207\nloc_1200:\nadd esi, 1\ncmp edi, esi\njl short loc_1248\nloc_1207:\nmov ecx, esi\nimul ecx, esi\ncmp ecx, edi\njg short loc_1200\nlea eax, ds:0[rcx*4]\ncmp edi, eax\njz short loc_123D\nlea edx, [rcx+rcx*2]\nmov eax, 2\nnop dword ptr [rax+rax+00h]\nloc_1228:\nadd eax, 1\ncmp edi, eax\njl short loc_1200\nmov r8d, edx\nadd edx, ecx\nimul r8d, eax\ncmp r8d, edi\njnz short loc_1228\nloc_123D:\nmov eax, 1\nretn\nloc_1248:\nxor eax, eax\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11F0(int a1)\n{\n int i; // esi\n int v2; // ecx\n int v3; // edx\n int v4; // eax\n int v5; // r8d\n\n if ( a1 > 1 )\n {\n for ( i = 2; a1 >= i; ++i )\n {\n v2 = i * i;\n if ( i * i <= a1 )\n {\n if ( a1 == 4 * v2 )\n return 1LL;\n v3 = 3 * v2;\n v4 = 2;\n while ( a1 >= ++v4 )\n {\n v5 = v3;\n v3 += v2;\n if ( v4 * v5 == a1 )\n return 1LL;\n }\n }\n }\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11F0(int a1) {\n int i;\n int v2;\n int v3;\n int v4;\n int v5;\n if (a1 > 1) {\n for (i = 2; a1 >= i; ++i) {\n v2 = i * i;\n if (i * i <= a1) {\n if (a1 == 4 * v2) return 1LL;\n v3 = 3 * v2;\n v4 = 2;\n while (a1 >= ++v4) {\n v5 = v3;\n v3 += v2;\n if (v4 * v5 == a1) return 1LL;\n }\n }\n }\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int i;\n int v2;\n int v3;\n int v4;\n int v5;\n if (a1 > 1) {\n for (i = 2; a1 >= i; ++i) {\n v2 = i * i;\n if (i * i <= a1) {\n if (a1 == 4 * v2) return 1LL;\n v3 = 3 * v2;\n v4 = 2;\n while (a1 >= ++v4) {\n v5 = v3;\n v3 += v2;\n if (v4 * v5 == a1) return 1LL;\n }\n }\n }\n }\n return 0LL;\n}" + }, + { + "index": 189, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int ptr = 0;\n for (int i = 0; i < n; i++) {\n if (arr[i] == 1) {\n ptr = 1;\n break;\n }\n }\n if (ptr == 0) {\n return 1;\n }\n for (int i = 0; i < n; i++) {\n if (arr[i] <= 0 || arr[i] > n) {\n arr[i] = 1;\n }\n }\n for (int i = 0; i < n; i++) {\n arr[(arr[i] - 1) % n] += n;\n }\n for (int i = 0; i < n; i++) {\n if (arr[i] <= n) {\n return i + 1;\n }\n }\n return n + 1;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, -1, 5};\n\n int arr2[] = {0, -1, -2, 1, 5, 8};\n\n int arr3[] = {0, 1, 2, 5, -8};\n\n \n\n assert(func0(arr1, 5) == 4);\n\n assert(func0(arr2, 6) == 2);\n\n assert(func0(arr3, 5) == 3);\n\n \n\n printf(\"All test cases passed\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmovl $0x0,-0x14(%rbp)\nmovl $0x0,-0x10(%rbp)\njmp 11d0 \nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp $0x1,%eax\njne 11cc \nmovl $0x1,-0x14(%rbp)\njmp 11d8 \naddl $0x1,-0x10(%rbp)\nmov -0x10(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 11a8 \ncmpl $0x0,-0x14(%rbp)\njne 11e8 \nmov $0x1,%eax\njmpq 12ea \nmovl $0x0,-0xc(%rbp)\njmp 1244 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ntest %eax,%eax\njle 1226 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x2c(%rbp)\njge 1240 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovl $0x1,(%rax)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 11f1 \nmovl $0x0,-0x8(%rbp)\njmp 12a4 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nsub $0x1,%eax\ncltd\nidivl -0x2c(%rbp)\nmov %edx,%eax\nmovslq %eax,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x28(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rdx),%ecx\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov -0x2c(%rbp),%edx\nadd %ecx,%edx\nmov %edx,(%rax)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 1255 \nmovl $0x0,-0x4(%rbp)\njmp 12dc \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x2c(%rbp)\njl 12d8 \nmov -0x4(%rbp),%eax\nadd $0x1,%eax\njmp 12ea \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 12b5 \nmov -0x2c(%rbp),%eax\nadd $0x1,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\njmp short loc_11D0\nloc_11A8:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\ncmp eax, 1\njnz short loc_11CC\nmov [rbp+var_14], 1\njmp short loc_11D8\nloc_11CC:\nadd [rbp+var_10], 1\nloc_11D0:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_2C]\njl short loc_11A8\nloc_11D8:\ncmp [rbp+var_14], 0\njnz short loc_11E8\nmov eax, 1\njmp loc_12EA\nloc_11E8:\nmov [rbp+var_C], 0\njmp short loc_1244\nloc_11F1:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njle short loc_1226\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_2C], eax\njge short loc_1240\nloc_1226:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov dword ptr [rax], 1\nloc_1240:\nadd [rbp+var_C], 1\nloc_1244:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_2C]\njl short loc_11F1\nmov [rbp+var_8], 0\njmp short loc_12A4\nloc_1255:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nsub eax, 1\ncdq\nidiv [rbp+var_2C]\nmov eax, edx\nmovsxd rdx, eax\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov ecx, [rdx]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_2C]\nadd edx, ecx\nmov [rax], edx\nadd [rbp+var_8], 1\nloc_12A4:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_2C]\njl short loc_1255\nmov [rbp+var_4], 0\njmp short loc_12DC\nloc_12B5:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_2C], eax\njl short loc_12D8\nmov eax, [rbp+var_4]\nadd eax, 1\njmp short loc_12EA\nloc_12D8:\nadd [rbp+var_4], 1\nloc_12DC:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_2C]\njl short loc_12B5\nmov eax, [rbp+var_2C]\nadd eax, 1\nloc_12EA:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int v3; // eax\n int v4; // [rsp+18h] [rbp-14h]\n int i; // [rsp+1Ch] [rbp-10h]\n int j; // [rsp+20h] [rbp-Ch]\n int k; // [rsp+24h] [rbp-8h]\n int m; // [rsp+28h] [rbp-4h]\n\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) == 1 )\n {\n v4 = 1;\n break;\n }\n }\n if ( !v4 )\n return 1LL;\n for ( j = 0; j < a2; ++j )\n {\n if ( *(int *)(4LL * j + a1) <= 0 || a2 < *(_DWORD *)(4LL * j + a1) )\n *(_DWORD *)(4LL * j + a1) = 1;\n }\n for ( k = 0; k < a2; ++k )\n {\n v3 = (*(_DWORD *)(4LL * k + a1) - 1) % a2;\n *(_DWORD *)(4LL * v3 + a1) += a2;\n }\n for ( m = 0; m < a2; ++m )\n {\n if ( a2 >= *(_DWORD *)(4LL * m + a1) )\n return (unsigned int)(m + 1);\n }\n return (unsigned int)(a2 + 1);\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\njmp short loc_11D0\nloc_11A8:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\ncmp eax, 1\njnz short loc_11CC\nmov [rbp+var_14], 1\njmp short loc_11D8\nloc_11CC:\nadd [rbp+var_10], 1\nloc_11D0:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_2C]\njl short loc_11A8\nloc_11D8:\ncmp [rbp+var_14], 0\njnz short loc_11E8\nmov eax, 1\njmp loc_12EA\nloc_11E8:\nmov [rbp+var_C], 0\njmp short loc_1244\nloc_11F1:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njle short loc_1226\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_2C], eax\njge short loc_1240\nloc_1226:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov dword ptr [rax], 1\nloc_1240:\nadd [rbp+var_C], 1\nloc_1244:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_2C]\njl short loc_11F1\nmov [rbp+var_8], 0\njmp short loc_12A4\nloc_1255:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nsub eax, 1\ncdq\nidiv [rbp+var_2C]\nmov eax, edx\nmovsxd rdx, eax\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov ecx, [rdx]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_2C]\nadd edx, ecx\nmov [rax], edx\nadd [rbp+var_8], 1\nloc_12A4:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_2C]\njl short loc_1255\nmov [rbp+var_4], 0\njmp short loc_12DC\nloc_12B5:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_2C], eax\njl short loc_12D8\nmov eax, [rbp+var_4]\nadd eax, 1\njmp short loc_12EA\nloc_12D8:\nadd [rbp+var_4], 1\nloc_12DC:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_2C]\njl short loc_12B5\nmov eax, [rbp+var_2C]\nadd eax, 1\nloc_12EA:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2)\n{\n int v3; // eax\n int v4; // [rsp+18h] [rbp-14h]\n int i; // [rsp+1Ch] [rbp-10h]\n int j; // [rsp+20h] [rbp-Ch]\n int k; // [rsp+24h] [rbp-8h]\n int m; // [rsp+28h] [rbp-4h]\n\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) == 1 )\n {\n v4 = 1;\n break;\n }\n }\n if ( !v4 )\n return 1LL;\n for ( j = 0; j < a2; ++j )\n {\n if ( *(int *)(4LL * j + a1) <= 0 || a2 < *(_DWORD *)(4LL * j + a1) )\n *(_DWORD *)(4LL * j + a1) = 1;\n }\n for ( k = 0; k < a2; ++k )\n {\n v3 = (*(_DWORD *)(4LL * k + a1) - 1) % a2;\n *(_DWORD *)(4LL * v3 + a1) += a2;\n }\n for ( m = 0; m < a2; ++m )\n {\n if ( a2 >= *(_DWORD *)(4LL * m + a1) )\n return (unsigned int)(m + 1);\n }\n return (unsigned int)(a2 + 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2) {\n int v3;\n int v4;\n int i;\n int j;\n int k;\n int m;\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(uint32_t *)(4LL * i + a1) == 1) {\n v4 = 1;\n break;\n }\n }\n if (!v4) return 1LL;\n for (j = 0; j < a2; ++j) {\n if (*(int *)(4LL * j + a1) <= 0 || a2 < *(uint32_t *)(4LL * j + a1))\n *(uint32_t *)(4LL * j + a1) = 1;\n }\n for (k = 0; k < a2; ++k) {\n v3 = (*(uint32_t *)(4LL * k + a1) - 1) % a2;\n *(uint32_t *)(4LL * v3 + a1) += a2;\n }\n for (m = 0; m < a2; ++m) {\n if (a2 >= *(uint32_t *)(4LL * m + a1)) return (unsigned int)(m + 1);\n }\n return (unsigned int)(a2 + 1);\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int v3;\n int v4;\n int i;\n int j;\n int k;\n int m;\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(uint32_t *)(4LL * i + a1) == 1) {\n v4 = 1;\n break;\n }\n }\n if (!v4) return 1LL;\n for (j = 0; j < a2; ++j) {\n if (*(int *)(4LL * j + a1) <= 0 || a2 < *(uint32_t *)(4LL * j + a1))\n *(uint32_t *)(4LL * j + a1) = 1;\n }\n for (k = 0; k < a2; ++k) {\n v3 = (*(uint32_t *)(4LL * k + a1) - 1) % a2;\n *(uint32_t *)(4LL * v3 + a1) += a2;\n }\n for (m = 0; m < a2; ++m) {\n if (a2 >= *(uint32_t *)(4LL * m + a1)) return (unsigned int)(m + 1);\n }\n return (unsigned int)(a2 + 1);\n}" + }, + { + "index": 189, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int ptr = 0;\n for (int i = 0; i < n; i++) {\n if (arr[i] == 1) {\n ptr = 1;\n break;\n }\n }\n if (ptr == 0) {\n return 1;\n }\n for (int i = 0; i < n; i++) {\n if (arr[i] <= 0 || arr[i] > n) {\n arr[i] = 1;\n }\n }\n for (int i = 0; i < n; i++) {\n arr[(arr[i] - 1) % n] += n;\n }\n for (int i = 0; i < n; i++) {\n if (arr[i] <= n) {\n return i + 1;\n }\n }\n return n + 1;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, -1, 5};\n\n int arr2[] = {0, -1, -2, 1, 5, 8};\n\n int arr3[] = {0, 1, 2, 5, -8};\n\n \n\n assert(func0(arr1, 5) == 4);\n\n assert(func0(arr2, 6) == 2);\n\n assert(func0(arr3, 5) == 3);\n\n \n\n printf(\"All test cases passed\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1215 \nmov %rdi,%rcx\nlea -0x1(%rsi),%r9d\nlea 0x4(%rdi,%r9,4),%r8\nmov %rdi,%rax\ncmpl $0x1,(%rax)\nje 11b8 \nadd $0x4,%rax\ncmp %r8,%rax\njne 11a4 \nmov $0x1,%eax\nretq\nmov %rdi,%rax\njmp 11cd \nmovl $0x1,(%r10)\nadd $0x4,%rax\ncmp %r8,%rax\nje 11dc \nmov %rax,%r10\nmov (%rax),%edx\ncmp %esi,%edx\njg 11bd \ntest %edx,%edx\njle 11bd \njmp 11c4 \nmov (%rcx),%eax\nsub $0x1,%eax\ncltd\nidiv %esi\nmovslq %edx,%rdx\nadd %esi,(%rdi,%rdx,4)\nadd $0x4,%rcx\ncmp %r8,%rcx\njne 11dc \nmov $0x0,%edx\njmp 11fd \nmov %rax,%rdx\nmov %edx,%eax\ncmp %esi,(%rdi,%rdx,4)\njle 1211 \nlea 0x1(%rdx),%rax\ncmp %r9,%rdx\njne 11fa \nlea 0x1(%rsi),%eax\nretq\nadd $0x1,%eax\nretq\nmov $0x1,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov ecx, esi\ntest esi, esi\njle short loc_120A\nmov rsi, rdi\nmovsxd r9, ecx\nlea r8, [rdi+r9*4]\nmov rax, rdi\nloc_11A0:\ncmp dword ptr [rax], 1\njz short loc_11B4\nadd rax, 4\ncmp rax, r8\njnz short loc_11A0\nmov eax, 1\nretn\nloc_11B4:\nmov rax, rdi\njmp short loc_11C9\nloc_11B9:\nmov dword ptr [r10], 1\nloc_11C0:\nadd rax, 4\ncmp rax, r8\njz short loc_11D8\nloc_11C9:\nmov r10, rax\nmov edx, [rax]\ncmp edx, ecx\njg short loc_11B9\ntest edx, edx\njle short loc_11B9\njmp short loc_11C0\nloc_11D8:\nmov eax, [rsi]\nsub eax, 1\ncdq\nidiv ecx\nmovsxd rdx, edx\nadd [rdi+rdx*4], ecx\nadd rsi, 4\ncmp rsi, r8\njnz short loc_11D8\nmov eax, 0\nloc_11F4:\ncmp [rdi+rax*4], ecx\njle short loc_1206\nadd rax, 1\ncmp rax, r9\njnz short loc_11F4\nlea eax, [rcx+1]\nretn\nloc_1206:\nadd eax, 1\nretn\nloc_120A:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int *v3; // rsi\n int *v4; // r8\n int *v5; // rax\n int *v7; // rax\n __int64 v8; // rax\n\n if ( a2 <= 0 )\n return 1LL;\n v3 = a1;\n v4 = &a1[a2];\n v5 = a1;\n while ( *v5 != 1 )\n {\n if ( ++v5 == v4 )\n return 1LL;\n }\n v7 = a1;\n do\n {\n if ( *v7 > a2 || *v7 <= 0 )\n *v7 = 1;\n ++v7;\n }\n while ( v7 != v4 );\n do\n a1[(*v3++ - 1) % a2] += a2;\n while ( v3 != v4 );\n v8 = 0LL;\n while ( a1[v8] > a2 )\n {\n if ( ++v8 == a2 )\n return (unsigned int)(a2 + 1);\n }\n return (unsigned int)(v8 + 1);\n}", + "ida_strip_asm": "sub_1189:\nendbr64\nmov ecx, esi\ntest esi, esi\njle short loc_120A\nmov rsi, rdi\nmovsxd r9, ecx\nlea r8, [rdi+r9*4]\nmov rax, rdi\nloc_11A0:\ncmp dword ptr [rax], 1\njz short loc_11B4\nadd rax, 4\ncmp rax, r8\njnz short loc_11A0\nmov eax, 1\nretn\nloc_11B4:\nmov rax, rdi\njmp short loc_11C9\nloc_11B9:\nmov dword ptr [r10], 1\nloc_11C0:\nadd rax, 4\ncmp rax, r8\njz short loc_11D8\nloc_11C9:\nmov r10, rax\nmov edx, [rax]\ncmp edx, ecx\njg short loc_11B9\ntest edx, edx\njle short loc_11B9\njmp short loc_11C0\nloc_11D8:\nmov eax, [rsi]\nsub eax, 1\ncdq\nidiv ecx\nmovsxd rdx, edx\nadd [rdi+rdx*4], ecx\nadd rsi, 4\ncmp rsi, r8\njnz short loc_11D8\nmov eax, 0\nloc_11F4:\ncmp [rdi+rax*4], ecx\njle short loc_1206\nadd rax, 1\ncmp rax, r9\njnz short loc_11F4\nlea eax, [rcx+1]\nretn\nloc_1206:\nadd eax, 1\nretn\nloc_120A:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(int *a1, int a2)\n{\n int *v3; // rsi\n int *v4; // r8\n int *v5; // rax\n int *v7; // rax\n __int64 v8; // rax\n\n if ( a2 <= 0 )\n return 1LL;\n v3 = a1;\n v4 = &a1[a2];\n v5 = a1;\n while ( *v5 != 1 )\n {\n if ( ++v5 == v4 )\n return 1LL;\n }\n v7 = a1;\n do\n {\n if ( *v7 > a2 || *v7 <= 0 )\n *v7 = 1;\n ++v7;\n }\n while ( v7 != v4 );\n do\n a1[(*v3++ - 1) % a2] += a2;\n while ( v3 != v4 );\n v8 = 0LL;\n while ( a1[v8] > a2 )\n {\n if ( ++v8 == a2 )\n return (unsigned int)(a2 + 1);\n }\n return (unsigned int)(v8 + 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(int *a1, int a2) {\n int *v3;\n int *v4;\n int *v5;\n int *v7;\n long long v8;\n if (a2 <= 0) return 1LL;\n v3 = a1;\n v4 = &a1[a2];\n v5 = a1;\n while (*v5 != 1) {\n if (++v5 == v4) return 1LL;\n }\n v7 = a1;\n do {\n if (*v7 > a2 || *v7 <= 0) *v7 = 1;\n ++v7;\n } while (v7 != v4);\n do\n a1[(*v3++ - 1) % a2] += a2;\n while (v3 != v4);\n v8 = 0LL;\n while (a1[v8] > a2) {\n if (++v8 == a2) return (unsigned int)(a2 + 1);\n }\n return (unsigned int)(v8 + 1);\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int *v3;\n int *v4;\n int *v5;\n int *v7;\n long long v8;\n if (a2 <= 0) return 1LL;\n v3 = a1;\n v4 = &a1[a2];\n v5 = a1;\n while (*v5 != 1) {\n if (++v5 == v4) return 1LL;\n }\n v7 = a1;\n do {\n if (*v7 > a2 || *v7 <= 0) *v7 = 1;\n ++v7;\n } while (v7 != v4);\n do\n a1[(*v3++ - 1) % a2] += a2;\n while (v3 != v4);\n v8 = 0LL;\n while (a1[v8] > a2) {\n if (++v8 == a2) return (unsigned int)(a2 + 1);\n }\n return (unsigned int)(v8 + 1);\n}" + }, + { + "index": 189, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int ptr = 0;\n for (int i = 0; i < n; i++) {\n if (arr[i] == 1) {\n ptr = 1;\n break;\n }\n }\n if (ptr == 0) {\n return 1;\n }\n for (int i = 0; i < n; i++) {\n if (arr[i] <= 0 || arr[i] > n) {\n arr[i] = 1;\n }\n }\n for (int i = 0; i < n; i++) {\n arr[(arr[i] - 1) % n] += n;\n }\n for (int i = 0; i < n; i++) {\n if (arr[i] <= n) {\n return i + 1;\n }\n }\n return n + 1;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, -1, 5};\n\n int arr2[] = {0, -1, -2, 1, 5, 8};\n\n int arr3[] = {0, 1, 2, 5, -8};\n\n \n\n assert(func0(arr1, 5) == 4);\n\n assert(func0(arr2, 6) == 2);\n\n assert(func0(arr3, 5) == 3);\n\n \n\n printf(\"All test cases passed\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1380 \nlea -0x1(%rsi),%r9d\nmov %rdi,%rcx\nmov %rdi,%rax\nlea 0x4(%rdi,%r9,4),%r8\njmp 1309 \nnopl (%rax)\nadd $0x4,%rax\ncmp %rax,%r8\nje 1380 \ncmpl $0x1,(%rax)\njne 1300 \nmov %rdi,%rax\nnopl 0x0(%rax)\nmov (%rax),%edx\ncmp %edx,%esi\njl 1322 \ntest %edx,%edx\njg 1328 \nmovl $0x1,(%rax)\nadd $0x4,%rax\ncmp %rax,%r8\njne 1318 \nnopl 0x0(%rax)\nmov (%rcx),%eax\nadd $0x4,%rcx\nsub $0x1,%eax\ncltd\nidiv %esi\nmovslq %edx,%rdx\nadd %esi,(%rdi,%rdx,4)\ncmp %rcx,%r8\njne 1338 \nlea 0x2(%r9),%rdx\nmov $0x1,%eax\nnopl 0x0(%rax,%rax,1)\nmov %eax,%r8d\ncmp -0x4(%rdi,%rax,4),%esi\njge 1386 \nadd $0x1,%rax\ncmp %rax,%rdx\njne 1360 \nlea 0x1(%rsi),%r8d\nmov %r8d,%eax\nretq\nnopw 0x0(%rax,%rax,1)\nmov $0x1,%r8d\nmov %r8d,%eax\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmov ecx, esi\ntest esi, esi\njle loc_1348\nmovsxd r9, ecx\nmov rsi, rdi\nmov rax, rdi\nlea r8, [rdi+r9*4]\njmp short loc_12D9\nloc_12D0:\nadd rax, 4\ncmp r8, rax\njz short loc_1348\nloc_12D9:\ncmp dword ptr [rax], 1\njnz short loc_12D0\nmov rax, rdi\nnop dword ptr [rax+00000000h]\nloc_12E8:\nmov edx, [rax]\ncmp ecx, edx\njl short loc_12F2\ntest edx, edx\njg short loc_12F8\nloc_12F2:\nmov dword ptr [rax], 1\nloc_12F8:\nadd rax, 4\ncmp r8, rax\njnz short loc_12E8\nnop dword ptr [rax+00000000h]\nloc_1308:\nmov eax, [rsi]\nadd rsi, 4\nsub eax, 1\ncdq\nidiv ecx\nmovsxd rdx, edx\nadd [rdi+rdx*4], ecx\ncmp r8, rsi\njnz short loc_1308\nmov eax, 1\njmp short loc_133C\nloc_1330:\nlea rdx, [rax+1]\ncmp r9, rax\njz short loc_1350\nmov rax, rdx\nloc_133C:\ncmp ecx, [rdi+rax*4-4]\njl short loc_1330\nretn\nloc_1348:\nmov eax, 1\nretn\nloc_1350:\nlea eax, [rcx+1]\nretn", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int *v3; // rsi\n int *v4; // rax\n int *v5; // r8\n int *v6; // rax\n int v7; // eax\n __int64 result; // rax\n\n if ( a2 <= 0 )\n return 1LL;\n v3 = a1;\n v4 = a1;\n v5 = &a1[a2];\n while ( *v4 != 1 )\n {\n if ( v5 == ++v4 )\n return 1LL;\n }\n v6 = a1;\n do\n {\n if ( a2 < *v6 || *v6 <= 0 )\n *v6 = 1;\n ++v6;\n }\n while ( v5 != v6 );\n do\n {\n v7 = *v3++;\n a1[(v7 - 1) % a2] += a2;\n }\n while ( v5 != v3 );\n for ( result = 1LL; a2 < a1[result - 1]; ++result )\n {\n if ( a2 == result )\n return (unsigned int)(a2 + 1);\n }\n return result;\n}", + "ida_strip_asm": "sub_12B0:\nendbr64\nmov ecx, esi\ntest esi, esi\njle loc_1348\nmovsxd r9, ecx\nmov rsi, rdi\nmov rax, rdi\nlea r8, [rdi+r9*4]\njmp short loc_12D9\nloc_12D0:\nadd rax, 4\ncmp r8, rax\njz short loc_1348\nloc_12D9:\ncmp dword ptr [rax], 1\njnz short loc_12D0\nmov rax, rdi\nnop dword ptr [rax+00000000h]\nloc_12E8:\nmov edx, [rax]\ncmp ecx, edx\njl short loc_12F2\ntest edx, edx\njg short loc_12F8\nloc_12F2:\nmov dword ptr [rax], 1\nloc_12F8:\nadd rax, 4\ncmp r8, rax\njnz short loc_12E8\nnop dword ptr [rax+00000000h]\nloc_1308:\nmov eax, [rsi]\nadd rsi, 4\nsub eax, 1\ncdq\nidiv ecx\nmovsxd rdx, edx\nadd [rdi+rdx*4], ecx\ncmp r8, rsi\njnz short loc_1308\nmov eax, 1\njmp short loc_133C\nloc_1330:\nlea rdx, [rax+1]\ncmp r9, rax\njz short loc_1350\nmov rax, rdx\nloc_133C:\ncmp ecx, [rdi+rax*4-4]\njl short loc_1330\nretn\nloc_1348:\nmov eax, 1\nretn\nloc_1350:\nlea eax, [rcx+1]\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12B0(int *a1, int a2)\n{\n int *v3; // rsi\n int *v4; // rax\n int *v5; // r8\n int *v6; // rax\n int v7; // eax\n __int64 result; // rax\n\n if ( a2 <= 0 )\n return 1LL;\n v3 = a1;\n v4 = a1;\n v5 = &a1[a2];\n while ( *v4 != 1 )\n {\n if ( v5 == ++v4 )\n return 1LL;\n }\n v6 = a1;\n do\n {\n if ( a2 < *v6 || *v6 <= 0 )\n *v6 = 1;\n ++v6;\n }\n while ( v5 != v6 );\n do\n {\n v7 = *v3++;\n a1[(v7 - 1) % a2] += a2;\n }\n while ( v5 != v3 );\n for ( result = 1LL; a2 < a1[result - 1]; ++result )\n {\n if ( a2 == result )\n return (unsigned int)(a2 + 1);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12B0(int *a1, int a2) {\n int *v3;\n int *v4;\n int *v5;\n int *v6;\n int v7;\n long long result;\n if (a2 <= 0) return 1LL;\n v3 = a1;\n v4 = a1;\n v5 = &a1[a2];\n while (*v4 != 1) {\n if (v5 == ++v4) return 1LL;\n }\n v6 = a1;\n do {\n if (a2 < *v6 || *v6 <= 0) *v6 = 1;\n ++v6;\n } while (v5 != v6);\n do {\n v7 = *v3++;\n a1[(v7 - 1) % a2] += a2;\n } while (v5 != v3);\n for (result = 1LL; a2 < a1[result - 1]; ++result) {\n if (a2 == result) return (unsigned int)(a2 + 1);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int *v3;\n int *v4;\n int *v5;\n int *v6;\n int v7;\n long long result;\n if (a2 <= 0) return 1LL;\n v3 = a1;\n v4 = a1;\n v5 = &a1[a2];\n while (*v4 != 1) {\n if (v5 == ++v4) return 1LL;\n }\n v6 = a1;\n do {\n if (a2 < *v6 || *v6 <= 0) *v6 = 1;\n ++v6;\n } while (v5 != v6);\n do {\n v7 = *v3++;\n a1[(v7 - 1) % a2] += a2;\n } while (v5 != v3);\n for (result = 1LL; a2 < a1[result - 1]; ++result) {\n if (a2 == result) return (unsigned int)(a2 + 1);\n }\n return result;\n}" + }, + { + "index": 189, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int ptr = 0;\n for (int i = 0; i < n; i++) {\n if (arr[i] == 1) {\n ptr = 1;\n break;\n }\n }\n if (ptr == 0) {\n return 1;\n }\n for (int i = 0; i < n; i++) {\n if (arr[i] <= 0 || arr[i] > n) {\n arr[i] = 1;\n }\n }\n for (int i = 0; i < n; i++) {\n arr[(arr[i] - 1) % n] += n;\n }\n for (int i = 0; i < n; i++) {\n if (arr[i] <= n) {\n return i + 1;\n }\n }\n return n + 1;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, -1, 5};\n\n int arr2[] = {0, -1, -2, 1, 5, 8};\n\n int arr3[] = {0, 1, 2, 5, -8};\n\n \n\n assert(func0(arr1, 5) == 4);\n\n assert(func0(arr2, 6) == 2);\n\n assert(func0(arr3, 5) == 3);\n\n \n\n printf(\"All test cases passed\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1350 \nlea -0x1(%rsi),%r9d\nmov %rdi,%rcx\nmov %rdi,%rax\nlea 0x4(%rdi,%r9,4),%r8\njmp 12d9 \nnopl (%rax)\nadd $0x4,%rax\ncmp %rax,%r8\nje 1350 \ncmpl $0x1,(%rax)\njne 12d0 \nmov %rdi,%rax\nnopl 0x0(%rax)\nmov (%rax),%edx\ncmp %edx,%esi\njl 12f2 \ntest %edx,%edx\njg 12f8 \nmovl $0x1,(%rax)\nadd $0x4,%rax\ncmp %rax,%r8\njne 12e8 \nnopl 0x0(%rax)\nmov (%rcx),%eax\nadd $0x4,%rcx\nsub $0x1,%eax\ncltd\nidiv %esi\nmovslq %edx,%rdx\nadd %esi,(%rdi,%rdx,4)\ncmp %rcx,%r8\njne 1308 \nlea 0x2(%r9),%rdx\nmov $0x1,%eax\nnopl 0x0(%rax,%rax,1)\nmov %eax,%r8d\ncmp -0x4(%rdi,%rax,4),%esi\njge 1356 \nadd $0x1,%rax\ncmp %rax,%rdx\njne 1330 \nlea 0x1(%rsi),%r8d\nmov %r8d,%eax\nretq\nnopw 0x0(%rax,%rax,1)\nmov $0x1,%r8d\nmov %r8d,%eax\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmov ecx, esi\ntest esi, esi\njle loc_1348\nmovsxd r9, ecx\nmov rsi, rdi\nmov rax, rdi\nlea r8, [rdi+r9*4]\njmp short loc_12D9\nloc_12D0:\nadd rax, 4\ncmp r8, rax\njz short loc_1348\nloc_12D9:\ncmp dword ptr [rax], 1\njnz short loc_12D0\nmov rax, rdi\nnop dword ptr [rax+00000000h]\nloc_12E8:\nmov edx, [rax]\ncmp ecx, edx\njl short loc_12F2\ntest edx, edx\njg short loc_12F8\nloc_12F2:\nmov dword ptr [rax], 1\nloc_12F8:\nadd rax, 4\ncmp r8, rax\njnz short loc_12E8\nnop dword ptr [rax+00000000h]\nloc_1308:\nmov eax, [rsi]\nadd rsi, 4\nsub eax, 1\ncdq\nidiv ecx\nmovsxd rdx, edx\nadd [rdi+rdx*4], ecx\ncmp r8, rsi\njnz short loc_1308\nmov eax, 1\njmp short loc_133C\nloc_1330:\nlea rdx, [rax+1]\ncmp r9, rax\njz short loc_1350\nmov rax, rdx\nloc_133C:\ncmp ecx, [rdi+rax*4-4]\njl short loc_1330\nretn\nloc_1348:\nmov eax, 1\nretn\nloc_1350:\nlea eax, [rcx+1]\nretn", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int *v3; // rsi\n int *v4; // rax\n int *v5; // r8\n int *v6; // rax\n int v7; // eax\n __int64 result; // rax\n\n if ( a2 <= 0 )\n return 1LL;\n v3 = a1;\n v4 = a1;\n v5 = &a1[a2];\n while ( *v4 != 1 )\n {\n if ( v5 == ++v4 )\n return 1LL;\n }\n v6 = a1;\n do\n {\n if ( a2 < *v6 || *v6 <= 0 )\n *v6 = 1;\n ++v6;\n }\n while ( v5 != v6 );\n do\n {\n v7 = *v3++;\n a1[(v7 - 1) % a2] += a2;\n }\n while ( v5 != v3 );\n for ( result = 1LL; a2 < a1[result - 1]; ++result )\n {\n if ( a2 == result )\n return (unsigned int)(a2 + 1);\n }\n return result;\n}", + "ida_strip_asm": "sub_12B0:\nendbr64\nmov ecx, esi\ntest esi, esi\njle loc_1348\nmovsxd r9, ecx\nmov rsi, rdi\nmov rax, rdi\nlea r8, [rdi+r9*4]\njmp short loc_12D9\nloc_12D0:\nadd rax, 4\ncmp r8, rax\njz short loc_1348\nloc_12D9:\ncmp dword ptr [rax], 1\njnz short loc_12D0\nmov rax, rdi\nnop dword ptr [rax+00000000h]\nloc_12E8:\nmov edx, [rax]\ncmp ecx, edx\njl short loc_12F2\ntest edx, edx\njg short loc_12F8\nloc_12F2:\nmov dword ptr [rax], 1\nloc_12F8:\nadd rax, 4\ncmp r8, rax\njnz short loc_12E8\nnop dword ptr [rax+00000000h]\nloc_1308:\nmov eax, [rsi]\nadd rsi, 4\nsub eax, 1\ncdq\nidiv ecx\nmovsxd rdx, edx\nadd [rdi+rdx*4], ecx\ncmp r8, rsi\njnz short loc_1308\nmov eax, 1\njmp short loc_133C\nloc_1330:\nlea rdx, [rax+1]\ncmp r9, rax\njz short loc_1350\nmov rax, rdx\nloc_133C:\ncmp ecx, [rdi+rax*4-4]\njl short loc_1330\nretn\nloc_1348:\nmov eax, 1\nretn\nloc_1350:\nlea eax, [rcx+1]\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12B0(int *a1, int a2)\n{\n int *v3; // rsi\n int *v4; // rax\n int *v5; // r8\n int *v6; // rax\n int v7; // eax\n __int64 result; // rax\n\n if ( a2 <= 0 )\n return 1LL;\n v3 = a1;\n v4 = a1;\n v5 = &a1[a2];\n while ( *v4 != 1 )\n {\n if ( v5 == ++v4 )\n return 1LL;\n }\n v6 = a1;\n do\n {\n if ( a2 < *v6 || *v6 <= 0 )\n *v6 = 1;\n ++v6;\n }\n while ( v5 != v6 );\n do\n {\n v7 = *v3++;\n a1[(v7 - 1) % a2] += a2;\n }\n while ( v5 != v3 );\n for ( result = 1LL; a2 < a1[result - 1]; ++result )\n {\n if ( a2 == result )\n return (unsigned int)(a2 + 1);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12B0(int *a1, int a2) {\n int *v3;\n int *v4;\n int *v5;\n int *v6;\n int v7;\n long long result;\n if (a2 <= 0) return 1LL;\n v3 = a1;\n v4 = a1;\n v5 = &a1[a2];\n while (*v4 != 1) {\n if (v5 == ++v4) return 1LL;\n }\n v6 = a1;\n do {\n if (a2 < *v6 || *v6 <= 0) *v6 = 1;\n ++v6;\n } while (v5 != v6);\n do {\n v7 = *v3++;\n a1[(v7 - 1) % a2] += a2;\n } while (v5 != v3);\n for (result = 1LL; a2 < a1[result - 1]; ++result) {\n if (a2 == result) return (unsigned int)(a2 + 1);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int *v3;\n int *v4;\n int *v5;\n int *v6;\n int v7;\n long long result;\n if (a2 <= 0) return 1LL;\n v3 = a1;\n v4 = a1;\n v5 = &a1[a2];\n while (*v4 != 1) {\n if (v5 == ++v4) return 1LL;\n }\n v6 = a1;\n do {\n if (a2 < *v6 || *v6 <= 0) *v6 = 1;\n ++v6;\n } while (v5 != v6);\n do {\n v7 = *v3++;\n a1[(v7 - 1) % a2] += a2;\n } while (v5 != v3);\n for (result = 1LL; a2 < a1[result - 1]; ++result) {\n if (a2 == result) return (unsigned int)(a2 + 1);\n }\n return result;\n}" + }, + { + "index": 190, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int x1, int y1, int x2, int y2) {\n return (y2 - y1 - 1) * (x2 - x1 - 1);\n}", + "test": "int main() {\n\n assert(func0(1, 1, 4, 4) == 4);\n\n assert(func0(1, 2, 1, 2) == 1);\n\n assert(func0(4, 2, 6, 4) == 1);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov %esi,-0x8(%rbp)\nmov %edx,-0xc(%rbp)\nmov %ecx,-0x10(%rbp)\nmov -0x10(%rbp),%eax\nsub -0x8(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0xc(%rbp),%eax\nsub -0x4(%rbp),%eax\nsub $0x1,%eax\nimul %edx,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov [rbp+var_C], edx\nmov [rbp+var_10], ecx\nmov eax, [rbp+var_10]\nsub eax, [rbp+var_8]\nlea edx, [rax-1]\nmov eax, [rbp+var_C]\nsub eax, [rbp+var_4]\nsub eax, 1\nimul eax, edx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, int a3, int a4)\n{\n return (unsigned int)((a4 - a2 - 1) * (a3 - a1 - 1));\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov [rbp+var_C], edx\nmov [rbp+var_10], ecx\nmov eax, [rbp+var_10]\nsub eax, [rbp+var_8]\nlea edx, [rax-1]\nmov eax, [rbp+var_C]\nsub eax, [rbp+var_4]\nsub eax, 1\nimul eax, edx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2, int a3, int a4)\n{\n return (unsigned int)((a4 - a2 - 1) * (a3 - a1 - 1));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2, int a3, int a4) {\n return (unsigned int)((a4 - a2 - 1) * (a3 - a1 - 1));\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, int a3, int a4) {\n return (unsigned int)((a4 - a2 - 1) * (a3 - a1 - 1));\n}" + }, + { + "index": 191, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char *monthname3) {\n if (strcmp(monthname3, \"April\") == 0 || strcmp(monthname3, \"June\") == 0 ||\n strcmp(monthname3, \"September\") == 0 ||\n strcmp(monthname3, \"November\") == 0) {\n return true;\n } else {\n return false;\n }\n}", + "test": "int main() {\n\n assert(func0(\"February\") == false);\n\n assert(func0(\"June\") == true);\n\n assert(func0(\"April\") == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %rdi,-0x8(%rbp)\nmov -0x8(%rbp),%rax\nlea 0xe84(%rip),%rsi\nmov %rax,%rdi\ncallq 1070 \ntest %eax,%eax\nje 11d5 \nmov -0x8(%rbp),%rax\nlea 0xe73(%rip),%rsi\nmov %rax,%rdi\ncallq 1070 \ntest %eax,%eax\nje 11d5 \nmov -0x8(%rbp),%rax\nlea 0xe61(%rip),%rsi\nmov %rax,%rdi\ncallq 1070 \ntest %eax,%eax\nje 11d5 \nmov -0x8(%rbp),%rax\nlea 0xe54(%rip),%rsi\nmov %rax,%rdi\ncallq 1070 \ntest %eax,%eax\njne 11dc \nmov $0x1,%eax\njmp 11e1 \nmov $0x0,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+s1], rdi\nmov rax, [rbp+s1]\nlea rdx, s2; \"April\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_11E1\nmov rax, [rbp+s1]\nlea rdx, aJune; \"June\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_11E1\nmov rax, [rbp+s1]\nlea rdx, aSeptember; \"September\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_11E1\nmov rax, [rbp+s1]\nlea rdx, aNovember; \"November\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_11E8\nloc_11E1:\nmov eax, 1\njmp short locret_11ED\nloc_11E8:\nmov eax, 0\nlocret_11ED:\nleave\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(const char *a1)\n{\n return !strcmp(a1, \"April\") || !strcmp(a1, \"June\") || !strcmp(a1, \"September\") || !strcmp(a1, \"November\");\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+s1], rdi\nmov rax, [rbp+s1]\nlea rdx, s2; \"April\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_11E1\nmov rax, [rbp+s1]\nlea rdx, aJune; \"June\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_11E1\nmov rax, [rbp+s1]\nlea rdx, aSeptember; \"September\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_11E1\nmov rax, [rbp+s1]\nlea rdx, aNovember; \"November\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_11E8\nloc_11E1:\nmov eax, 1\njmp short locret_11ED\nloc_11E8:\nmov eax, 0\nlocret_11ED:\nleave\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1169(const char *a1)\n{\n return !strcmp(a1, \"April\") || !strcmp(a1, \"June\") || !strcmp(a1, \"September\") || !strcmp(a1, \"November\");\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1169(const char *a1) {\n return !strcmp(a1, \"April\") || !strcmp(a1, \"June\") ||\n !strcmp(a1, \"September\") || !strcmp(a1, \"November\");\n}", + "ida_pseudo_norm": "uint8_t func0(const char *a1) {\n return !strcmp(a1, \"April\") || !strcmp(a1, \"June\") ||\n !strcmp(a1, \"September\") || !strcmp(a1, \"November\");\n}" + }, + { + "index": 191, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char *monthname3) {\n if (strcmp(monthname3, \"April\") == 0 || strcmp(monthname3, \"June\") == 0 ||\n strcmp(monthname3, \"September\") == 0 ||\n strcmp(monthname3, \"November\") == 0) {\n return true;\n } else {\n return false;\n }\n}", + "test": "int main() {\n\n assert(func0(\"February\") == false);\n\n assert(func0(\"June\") == true);\n\n assert(func0(\"April\") == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%rax\nmov $0x6,%ecx\nlea 0xea8(%rip),%rdi\nmov %rax,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %dl\nsbb $0x0,%dl\nmov $0x1,%ecx\ntest %dl,%dl\nje 11cb \nmov $0x5,%ecx\nlea 0xe8e(%rip),%rdi\nmov %rax,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %dl\nsbb $0x0,%dl\nmov $0x1,%ecx\ntest %dl,%dl\nje 11cb \nmov $0xa,%ecx\nlea 0xe73(%rip),%rdi\nmov %rax,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %dl\nsbb $0x0,%dl\nmov $0x1,%ecx\ntest %dl,%dl\nje 11cb \nmov $0x9,%ecx\nlea 0xe5d(%rip),%rdi\nmov %rax,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %al\nsbb $0x0,%al\ntest %al,%al\nsete %cl\nmov %ecx,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\nlea rsi, s2; \"April\"\ncall _strcmp\nmov edx, eax\nmov eax, 1\ntest edx, edx\njz short loc_11D0\nlea rsi, aJune; \"June\"\nmov rdi, rbx; s1\ncall _strcmp\nmov edx, eax\nmov eax, 1\ntest edx, edx\njz short loc_11D0\nlea rsi, aSeptember; \"September\"\nmov rdi, rbx; s1\ncall _strcmp\nmov edx, eax\nmov eax, 1\ntest edx, edx\njz short loc_11D0\nlea rsi, aNovember; \"November\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\nsetz al\nloc_11D0:\npop rbx\nretn", + "ida_pseudo": "bool __fastcall func0(char *s1)\n{\n int v1; // edx\n bool result; // al\n int v3; // edx\n int v4; // edx\n\n v1 = strcmp(s1, \"April\");\n result = 1;\n if ( v1 )\n {\n v3 = strcmp(s1, \"June\");\n result = 1;\n if ( v3 )\n {\n v4 = strcmp(s1, \"September\");\n result = 1;\n if ( v4 )\n return strcmp(s1, \"November\") == 0;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbx\nmov rbx, rdi\nlea rsi, s2; \"April\"\ncall _strcmp\nmov edx, eax\nmov eax, 1\ntest edx, edx\njz short loc_11D0\nlea rsi, aJune; \"June\"\nmov rdi, rbx; s1\ncall _strcmp\nmov edx, eax\nmov eax, 1\ntest edx, edx\njz short loc_11D0\nlea rsi, aSeptember; \"September\"\nmov rdi, rbx; s1\ncall _strcmp\nmov edx, eax\nmov eax, 1\ntest edx, edx\njz short loc_11D0\nlea rsi, aNovember; \"November\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\nsetz al\nloc_11D0:\npop rbx\nretn", + "ida_strip_pseudo": "bool __fastcall sub_1169(char *s1)\n{\n int v1; // edx\n bool result; // al\n int v3; // edx\n int v4; // edx\n\n v1 = strcmp(s1, \"April\");\n result = 1;\n if ( v1 )\n {\n v3 = strcmp(s1, \"June\");\n result = 1;\n if ( v3 )\n {\n v4 = strcmp(s1, \"September\");\n result = 1;\n if ( v4 )\n return strcmp(s1, \"November\") == 0;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_1169(char *s1) {\n int v1;\n bool result;\n int v3;\n int v4;\n v1 = strcmp(s1, \"April\");\n result = 1;\n if (v1) {\n v3 = strcmp(s1, \"June\");\n result = 1;\n if (v3) {\n v4 = strcmp(s1, \"September\");\n result = 1;\n if (v4) return strcmp(s1, \"November\") == 0;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "bool func0(char *s1) {\n int v1;\n bool result;\n int v3;\n int v4;\n v1 = strcmp(s1, \"April\");\n result = 1;\n if (v1) {\n v3 = strcmp(s1, \"June\");\n result = 1;\n if (v3) {\n v4 = strcmp(s1, \"September\");\n result = 1;\n if (v4) return strcmp(s1, \"November\") == 0;\n }\n }\n return result;\n}" + }, + { + "index": 191, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char *monthname3) {\n if (strcmp(monthname3, \"April\") == 0 || strcmp(monthname3, \"June\") == 0 ||\n strcmp(monthname3, \"September\") == 0 ||\n strcmp(monthname3, \"November\") == 0) {\n return true;\n } else {\n return false;\n }\n}", + "test": "int main() {\n\n assert(func0(\"February\") == false);\n\n assert(func0(\"June\") == true);\n\n assert(func0(\"April\") == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%rax\nmov $0x6,%ecx\nlea 0xe01(%rip),%rdi\nmov $0x1,%r8d\nmov %rax,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %dl\nsbb $0x0,%dl\ntest %dl,%dl\nje 126a \nmov $0x5,%ecx\nlea 0xde6(%rip),%rdi\nmov %rax,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %dl\nsbb $0x0,%dl\ntest %dl,%dl\nje 126a \nmov $0xa,%ecx\nlea 0xdd0(%rip),%rdi\nmov %rax,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %dl\nsbb $0x0,%dl\ntest %dl,%dl\nje 126a \nmov %rax,%rsi\nmov $0x9,%ecx\nlea 0xdbc(%rip),%rdi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %al\nsbb $0x0,%al\ntest %al,%al\nsete %r8b\nmov %r8d,%eax\nretq\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\nlea rsi, s2; \"April\"\nmov ebp, 1\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strcmp\ntest eax, eax\njz short loc_126D\nlea rsi, aJune; \"June\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz short loc_126D\nlea rsi, aSeptember; \"September\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz short loc_126D\nlea rsi, aNovember; \"November\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\nsetz bpl\nloc_126D:\nadd rsp, 8\nmov eax, ebp\npop rbx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(char *s1)\n{\n unsigned int v1; // ebp\n\n v1 = 1;\n if ( strcmp(s1, \"April\") && strcmp(s1, \"June\") && strcmp(s1, \"September\") )\n LOBYTE(v1) = strcmp(s1, \"November\") == 0;\n return v1;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbp\nlea rsi, s2; \"April\"\nmov ebp, 1\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strcmp\ntest eax, eax\njz short loc_126D\nlea rsi, aJune; \"June\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz short loc_126D\nlea rsi, aSeptember; \"September\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz short loc_126D\nlea rsi, aNovember; \"November\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\nsetz bpl\nloc_126D:\nadd rsp, 8\nmov eax, ebp\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(char *s1)\n{\n unsigned int v1; // ebp\n\n v1 = 1;\n if ( strcmp(s1, \"April\") && strcmp(s1, \"June\") && strcmp(s1, \"September\") )\n LOBYTE(v1) = strcmp(s1, \"November\") == 0;\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(char *s1) {\n unsigned int v1;\n v1 = 1;\n if (strcmp(s1, \"April\") && strcmp(s1, \"June\") && strcmp(s1, \"September\"))\n LOBYTE(v1) = strcmp(s1, \"November\") == 0;\n return v1;\n}", + "ida_pseudo_norm": "long long func0(char *s1) {\n unsigned int v1;\n v1 = 1;\n if (strcmp(s1, \"April\") && strcmp(s1, \"June\") && strcmp(s1, \"September\"))\n LOBYTE(v1) = strcmp(s1, \"November\") == 0;\n return v1;\n}" + }, + { + "index": 191, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char *monthname3) {\n if (strcmp(monthname3, \"April\") == 0 || strcmp(monthname3, \"June\") == 0 ||\n strcmp(monthname3, \"September\") == 0 ||\n strcmp(monthname3, \"November\") == 0) {\n return true;\n } else {\n return false;\n }\n}", + "test": "int main() {\n\n assert(func0(\"February\") == false);\n\n assert(func0(\"June\") == true);\n\n assert(func0(\"April\") == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%rax\nmov $0x6,%ecx\nlea 0xe01(%rip),%rdi\nmov $0x1,%r8d\nmov %rax,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %dl\nsbb $0x0,%dl\ntest %dl,%dl\nje 126a \nmov $0x5,%ecx\nlea 0xde6(%rip),%rdi\nmov %rax,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %dl\nsbb $0x0,%dl\ntest %dl,%dl\nje 126a \nmov $0xa,%ecx\nlea 0xdd0(%rip),%rdi\nmov %rax,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %dl\nsbb $0x0,%dl\ntest %dl,%dl\nje 126a \nmov %rax,%rsi\nmov $0x9,%ecx\nlea 0xdbc(%rip),%rdi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %al\nsbb $0x0,%al\ntest %al,%al\nsete %r8b\nmov %r8d,%eax\nretq\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\nlea rsi, s2; \"April\"\nmov ebp, 1\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strcmp\ntest eax, eax\njz short loc_126D\nlea rsi, aJune; \"June\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz short loc_126D\nlea rsi, aSeptember; \"September\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz short loc_126D\nlea rsi, aNovember; \"November\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\nsetz bpl\nloc_126D:\nadd rsp, 8\nmov eax, ebp\npop rbx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(char *s1)\n{\n unsigned int v1; // ebp\n\n v1 = 1;\n if ( strcmp(s1, \"April\") && strcmp(s1, \"June\") && strcmp(s1, \"September\") )\n LOBYTE(v1) = strcmp(s1, \"November\") == 0;\n return v1;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbp\nlea rsi, s2; \"April\"\nmov ebp, 1\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strcmp\ntest eax, eax\njz short loc_126D\nlea rsi, aJune; \"June\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz short loc_126D\nlea rsi, aSeptember; \"September\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz short loc_126D\nlea rsi, aNovember; \"November\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\nsetz bpl\nloc_126D:\nadd rsp, 8\nmov eax, ebp\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(char *s1)\n{\n unsigned int v1; // ebp\n\n v1 = 1;\n if ( strcmp(s1, \"April\") && strcmp(s1, \"June\") && strcmp(s1, \"September\") )\n LOBYTE(v1) = strcmp(s1, \"November\") == 0;\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(char *s1) {\n unsigned int v1;\n v1 = 1;\n if (strcmp(s1, \"April\") && strcmp(s1, \"June\") && strcmp(s1, \"September\"))\n LOBYTE(v1) = strcmp(s1, \"November\") == 0;\n return v1;\n}", + "ida_pseudo_norm": "long long func0(char *s1) {\n unsigned int v1;\n v1 = 1;\n if (strcmp(s1, \"April\") && strcmp(s1, \"June\") && strcmp(s1, \"September\"))\n LOBYTE(v1) = strcmp(s1, \"November\") == 0;\n return v1;\n}" + }, + { + "index": 192, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *str) {\n int flag_l = 0;\n int flag_n = 0;\n while (*str) {\n if (isalpha((unsigned char)*str)) {\n flag_l = 1;\n }\n if (isdigit((unsigned char)*str)) {\n flag_n = 1;\n }\n str++;\n }\n return flag_l && flag_n;\n}", + "test": "int main() {\n\n assert(func0(\"thishasboth29\") == 1);\n\n assert(func0(\"python\") == 0);\n\n assert(func0(\"string\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11ea \ncallq 1070 <__ctype_b_loc@plt>\nmov (%rax),%rdx\nmov -0x18(%rbp),%rax\nmovzbl (%rax),%eax\nmovzbl %al,%eax\nadd %rax,%rax\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x400,%eax\ntest %eax,%eax\nje 11b7 \nmovl $0x1,-0x8(%rbp)\ncallq 1070 <__ctype_b_loc@plt>\nmov (%rax),%rdx\nmov -0x18(%rbp),%rax\nmovzbl (%rax),%eax\nmovzbl %al,%eax\nadd %rax,%rax\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x800,%eax\ntest %eax,%eax\nje 11e5 \nmovl $0x1,-0x4(%rbp)\naddq $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 1189 \ncmpl $0x0,-0x8(%rbp)\nje 1208 \ncmpl $0x0,-0x4(%rbp)\nje 1208 \nmov $0x1,%eax\njmp 120d \nmov $0x0,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11EA\nloc_1189:\ncall ___ctype_b_loc\nmov rdx, [rax]\nmov rax, [rbp+var_18]\nmovzx eax, byte ptr [rax]\nmovzx eax, al\nadd rax, rax\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 400h\ntest eax, eax\njz short loc_11B7\nmov [rbp+var_8], 1\nloc_11B7:\ncall ___ctype_b_loc\nmov rdx, [rax]\nmov rax, [rbp+var_18]\nmovzx eax, byte ptr [rax]\nmovzx eax, al\nadd rax, rax\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 800h\ntest eax, eax\njz short loc_11E5\nmov [rbp+var_4], 1\nloc_11E5:\nadd [rbp+var_18], 1\nloc_11EA:\nmov rax, [rbp+var_18]\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1189\ncmp [rbp+var_8], 0\njz short loc_1208\ncmp [rbp+var_4], 0\njz short loc_1208\nmov eax, 1\njmp short locret_120D\nloc_1208:\nmov eax, 0\nlocret_120D:\nleave\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(_BYTE *a1)\n{\n int v3; // [rsp+18h] [rbp-8h]\n int v4; // [rsp+1Ch] [rbp-4h]\n\n v3 = 0;\n v4 = 0;\n while ( *a1 )\n {\n if ( ((*__ctype_b_loc())[(unsigned __int8)*a1] & 0x400) != 0 )\n v3 = 1;\n if ( ((*__ctype_b_loc())[(unsigned __int8)*a1] & 0x800) != 0 )\n v4 = 1;\n ++a1;\n }\n return v3 && v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11EA\nloc_1189:\ncall ___ctype_b_loc\nmov rdx, [rax]\nmov rax, [rbp+var_18]\nmovzx eax, byte ptr [rax]\nmovzx eax, al\nadd rax, rax\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 400h\ntest eax, eax\njz short loc_11B7\nmov [rbp+var_8], 1\nloc_11B7:\ncall ___ctype_b_loc\nmov rdx, [rax]\nmov rax, [rbp+var_18]\nmovzx eax, byte ptr [rax]\nmovzx eax, al\nadd rax, rax\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 800h\ntest eax, eax\njz short loc_11E5\nmov [rbp+var_4], 1\nloc_11E5:\nadd [rbp+var_18], 1\nloc_11EA:\nmov rax, [rbp+var_18]\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1189\ncmp [rbp+var_8], 0\njz short loc_1208\ncmp [rbp+var_4], 0\njz short loc_1208\nmov eax, 1\njmp short locret_120D\nloc_1208:\nmov eax, 0\nlocret_120D:\nleave\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1169(_BYTE *a1)\n{\n int v3; // [rsp+18h] [rbp-8h]\n int v4; // [rsp+1Ch] [rbp-4h]\n\n v3 = 0;\n v4 = 0;\n while ( *a1 )\n {\n if ( ((*__ctype_b_loc())[(unsigned __int8)*a1] & 0x400) != 0 )\n v3 = 1;\n if ( ((*__ctype_b_loc())[(unsigned __int8)*a1] & 0x800) != 0 )\n v4 = 1;\n ++a1;\n }\n return v3 && v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1169(uint8_t *a1) {\n int v3;\n int v4;\n v3 = 0;\n v4 = 0;\n while (*a1) {\n if (((*__ctype_b_loc())[(unsigned char)*a1] & 1024) != 0) v3 = 1;\n if (((*__ctype_b_loc())[(unsigned char)*a1] & 2048) != 0) v4 = 1;\n ++a1;\n }\n return v3 && v4;\n}", + "ida_pseudo_norm": "uint8_t func0(uint8_t *a1) {\n int v3;\n int v4;\n v3 = 0;\n v4 = 0;\n while (*a1) {\n if (((*__ctype_b_loc())[(unsigned char)*a1] & 1024) != 0) v3 = 1;\n if (((*__ctype_b_loc())[(unsigned char)*a1] & 2048) != 0) v4 = 1;\n ++a1;\n }\n return v3 && v4;\n}" + }, + { + "index": 192, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *str) {\n int flag_l = 0;\n int flag_n = 0;\n while (*str) {\n if (isalpha((unsigned char)*str)) {\n flag_l = 1;\n }\n if (isdigit((unsigned char)*str)) {\n flag_n = 1;\n }\n str++;\n }\n return flag_l && flag_n;\n}", + "test": "int main() {\n\n assert(func0(\"thishasboth29\") == 1);\n\n assert(func0(\"python\") == 0);\n\n assert(func0(\"string\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmovzbl (%rdi),%ebx\ntest %bl,%bl\nje 11c9 \nmov %rdi,%rbp\ncallq 1070 <__ctype_b_loc@plt>\nmov (%rax),%rdi\nmov $0x0,%edx\nmov $0x0,%ecx\nmov $0x1,%esi\nmovzbl %bl,%ebx\nmovzwl (%rdi,%rbx,2),%eax\ntest $0x4,%ah\ncmovne %esi,%ecx\ntest $0x8,%ah\ncmovne %esi,%edx\nadd $0x1,%rbp\nmovzbl 0x0(%rbp),%ebx\ntest %bl,%bl\njne 1194 \ntest %ecx,%ecx\nsetne %cl\ntest %edx,%edx\nsetne %al\nmovzbl %al,%eax\nand %ecx,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nmov $0x0,%edx\nmov $0x0,%ecx\njmp 11b3 \n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_11C9\nmov rbp, rdi\ncall ___ctype_b_loc\nmov rdi, [rax]\nmov edx, 0\nmov ecx, 0\nmov esi, 1\nloc_1194:\nmovzx ebx, bl\nmovzx eax, word ptr [rdi+rbx*2]\ntest ah, 4\ncmovnz ecx, esi\ntest ah, 8\ncmovnz edx, esi\nadd rbp, 1\nmovzx ebx, byte ptr [rbp+0]\ntest bl, bl\njnz short loc_1194\nloc_11B3:\ntest ecx, ecx\nsetnz cl\ntest edx, edx\nsetnz al\nmovzx eax, al\nand eax, ecx\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_11C9:\nmov edx, 0\nmov ecx, 0\njmp short loc_11B3", + "ida_pseudo": "__int64 __fastcall func0(unsigned __int8 *a1)\n{\n unsigned __int8 v1; // bl\n unsigned __int8 *v2; // rbp\n const unsigned __int16 *v3; // rdi\n int v4; // edx\n int v5; // ecx\n unsigned __int16 v6; // ax\n\n v1 = *a1;\n if ( *a1 )\n {\n v2 = a1;\n v3 = *__ctype_b_loc();\n v4 = 0;\n v5 = 0;\n do\n {\n v6 = v3[v1];\n if ( (v6 & 0x400) != 0 )\n v5 = 1;\n if ( (v6 & 0x800) != 0 )\n v4 = 1;\n v1 = *++v2;\n }\n while ( *v2 );\n }\n else\n {\n v4 = 0;\n v5 = 0;\n }\n return (v5 != 0) & (unsigned __int8)(v4 != 0);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_11C9\nmov rbp, rdi\ncall ___ctype_b_loc\nmov rdi, [rax]\nmov edx, 0\nmov ecx, 0\nmov esi, 1\nloc_1194:\nmovzx ebx, bl\nmovzx eax, word ptr [rdi+rbx*2]\ntest ah, 4\ncmovnz ecx, esi\ntest ah, 8\ncmovnz edx, esi\nadd rbp, 1\nmovzx ebx, byte ptr [rbp+0]\ntest bl, bl\njnz short loc_1194\nloc_11B3:\ntest ecx, ecx\nsetnz cl\ntest edx, edx\nsetnz al\nmovzx eax, al\nand eax, ecx\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_11C9:\nmov edx, 0\nmov ecx, 0\njmp short loc_11B3", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(unsigned __int8 *a1)\n{\n unsigned __int8 v1; // bl\n unsigned __int8 *v2; // rbp\n const unsigned __int16 *v3; // rdi\n int v4; // edx\n int v5; // ecx\n unsigned __int16 v6; // ax\n\n v1 = *a1;\n if ( *a1 )\n {\n v2 = a1;\n v3 = *__ctype_b_loc();\n v4 = 0;\n v5 = 0;\n do\n {\n v6 = v3[v1];\n if ( (v6 & 0x400) != 0 )\n v5 = 1;\n if ( (v6 & 0x800) != 0 )\n v4 = 1;\n v1 = *++v2;\n }\n while ( *v2 );\n }\n else\n {\n v4 = 0;\n v5 = 0;\n }\n return (v5 != 0) & (unsigned __int8)(v4 != 0);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(unsigned char *a1) {\n unsigned char v1;\n unsigned char *v2;\n const unsigned short *v3;\n int v4;\n int v5;\n unsigned short v6;\n v1 = *a1;\n if (*a1) {\n v2 = a1;\n v3 = *__ctype_b_loc();\n v4 = 0;\n v5 = 0;\n do {\n v6 = v3[v1];\n if ((v6 & 1024) != 0) v5 = 1;\n if ((v6 & 2048) != 0) v4 = 1;\n v1 = *++v2;\n } while (*v2);\n } else {\n v4 = 0;\n v5 = 0;\n }\n return (v5 != 0) & (unsigned char)(v4 != 0);\n}", + "ida_pseudo_norm": "long long func0(unsigned char *a1) {\n unsigned char v1;\n unsigned char *v2;\n const unsigned short *v3;\n int v4;\n int v5;\n unsigned short v6;\n v1 = *a1;\n if (*a1) {\n v2 = a1;\n v3 = *__ctype_b_loc();\n v4 = 0;\n v5 = 0;\n do {\n v6 = v3[v1];\n if ((v6 & 1024) != 0) v5 = 1;\n if ((v6 & 2048) != 0) v4 = 1;\n v1 = *++v2;\n } while (*v2);\n } else {\n v4 = 0;\n v5 = 0;\n }\n return (v5 != 0) & (unsigned char)(v4 != 0);\n}" + }, + { + "index": 192, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *str) {\n int flag_l = 0;\n int flag_n = 0;\n while (*str) {\n if (isalpha((unsigned char)*str)) {\n flag_l = 1;\n }\n if (isdigit((unsigned char)*str)) {\n flag_n = 1;\n }\n str++;\n }\n return flag_l && flag_n;\n}", + "test": "int main() {\n\n assert(func0(\"thishasboth29\") == 1);\n\n assert(func0(\"python\") == 0);\n\n assert(func0(\"string\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmovzbl (%rdi),%ebx\ntest %bl,%bl\nje 1260 \nmov %rdi,%rbp\ncallq 1070 <__ctype_b_loc@plt>\nxor %ecx,%ecx\nmov $0x1,%esi\nmov (%rax),%rdi\nxor %eax,%eax\nnopl (%rax)\nmovzbl %bl,%ebx\nmovzwl (%rdi,%rbx,2),%edx\ntest $0x4,%dh\ncmovne %esi,%eax\nand $0x8,%dh\ncmovne %esi,%ecx\nmovzbl 0x1(%rbp),%ebx\nadd $0x1,%rbp\ntest %bl,%bl\njne 1238 \nadd $0x8,%rsp\nand %ecx,%eax\npop %rbx\npop %rbp\nretq\nadd $0x8,%rsp\nxor %eax,%eax\npop %rbx\npop %rbp\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_1260\nmov rbp, rdi\ncall ___ctype_b_loc\nxor ecx, ecx\nmov esi, 1\nmov rdi, [rax]\nxor eax, eax\nnop dword ptr [rax]\nloc_1238:\nmovzx ebx, bl\nmovzx edx, word ptr [rdi+rbx*2]\ntest dh, 4\ncmovnz eax, esi\nand dh, 8\ncmovnz ecx, esi\nmovzx ebx, byte ptr [rbp+1]\nadd rbp, 1\ntest bl, bl\njnz short loc_1238\nadd rsp, 8\nand eax, ecx\npop rbx\npop rbp\nretn\nloc_1260:\nadd rsp, 8\nxor eax, eax\npop rbx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned __int8 *a1)\n{\n unsigned __int8 v1; // bl\n unsigned __int8 *v2; // rbp\n const unsigned __int16 **v3; // rax\n int v4; // ecx\n const unsigned __int16 *v5; // rdi\n int v6; // eax\n unsigned __int16 v7; // dx\n\n v1 = *a1;\n if ( !*a1 )\n return 0LL;\n v2 = a1;\n v3 = __ctype_b_loc();\n v4 = 0;\n v5 = *v3;\n v6 = 0;\n do\n {\n v7 = v5[v1];\n if ( (v7 & 0x400) != 0 )\n v6 = 1;\n if ( (v7 & 0x800) != 0 )\n v4 = 1;\n v1 = *++v2;\n }\n while ( v1 );\n return v4 & (unsigned int)v6;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_1260\nmov rbp, rdi\ncall ___ctype_b_loc\nxor ecx, ecx\nmov esi, 1\nmov rdi, [rax]\nxor eax, eax\nnop dword ptr [rax]\nloc_1238:\nmovzx ebx, bl\nmovzx edx, word ptr [rdi+rbx*2]\ntest dh, 4\ncmovnz eax, esi\nand dh, 8\ncmovnz ecx, esi\nmovzx ebx, byte ptr [rbp+1]\nadd rbp, 1\ntest bl, bl\njnz short loc_1238\nadd rsp, 8\nand eax, ecx\npop rbx\npop rbp\nretn\nloc_1260:\nadd rsp, 8\nxor eax, eax\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(unsigned __int8 *a1)\n{\n unsigned __int8 v1; // bl\n unsigned __int8 *v2; // rbp\n const unsigned __int16 **v3; // rax\n int v4; // ecx\n const unsigned __int16 *v5; // rdi\n int v6; // eax\n unsigned __int16 v7; // dx\n\n v1 = *a1;\n if ( !*a1 )\n return 0LL;\n v2 = a1;\n v3 = __ctype_b_loc();\n v4 = 0;\n v5 = *v3;\n v6 = 0;\n do\n {\n v7 = v5[v1];\n if ( (v7 & 0x400) != 0 )\n v6 = 1;\n if ( (v7 & 0x800) != 0 )\n v4 = 1;\n v1 = *++v2;\n }\n while ( v1 );\n return v4 & (unsigned int)v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(unsigned char *a1) {\n unsigned char v1;\n unsigned char *v2;\n const unsigned short **v3;\n int v4;\n const unsigned short *v5;\n int v6;\n unsigned short v7;\n v1 = *a1;\n if (!*a1) return 0LL;\n v2 = a1;\n v3 = __ctype_b_loc();\n v4 = 0;\n v5 = *v3;\n v6 = 0;\n do {\n v7 = v5[v1];\n if ((v7 & 1024) != 0) v6 = 1;\n if ((v7 & 2048) != 0) v4 = 1;\n v1 = *++v2;\n } while (v1);\n return v4 & (unsigned int)v6;\n}", + "ida_pseudo_norm": "long long func0(unsigned char *a1) {\n unsigned char v1;\n unsigned char *v2;\n const unsigned short **v3;\n int v4;\n const unsigned short *v5;\n int v6;\n unsigned short v7;\n v1 = *a1;\n if (!*a1) return 0LL;\n v2 = a1;\n v3 = __ctype_b_loc();\n v4 = 0;\n v5 = *v3;\n v6 = 0;\n do {\n v7 = v5[v1];\n if ((v7 & 1024) != 0) v6 = 1;\n if ((v7 & 2048) != 0) v4 = 1;\n v1 = *++v2;\n } while (v1);\n return v4 & (unsigned int)v6;\n}" + }, + { + "index": 192, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *str) {\n int flag_l = 0;\n int flag_n = 0;\n while (*str) {\n if (isalpha((unsigned char)*str)) {\n flag_l = 1;\n }\n if (isdigit((unsigned char)*str)) {\n flag_n = 1;\n }\n str++;\n }\n return flag_l && flag_n;\n}", + "test": "int main() {\n\n assert(func0(\"thishasboth29\") == 1);\n\n assert(func0(\"python\") == 0);\n\n assert(func0(\"string\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmovzbl (%rdi),%ebx\ntest %bl,%bl\nje 1260 \nmov %rdi,%rbp\ncallq 1070 <__ctype_b_loc@plt>\nxor %ecx,%ecx\nmov $0x1,%esi\nmov (%rax),%rdi\nxor %eax,%eax\nnopl (%rax)\nmovzbl %bl,%ebx\nmovzwl (%rdi,%rbx,2),%edx\ntest $0x4,%dh\ncmovne %esi,%eax\nand $0x8,%dh\ncmovne %esi,%ecx\nmovzbl 0x1(%rbp),%ebx\nadd $0x1,%rbp\ntest %bl,%bl\njne 1238 \nadd $0x8,%rsp\nand %ecx,%eax\npop %rbx\npop %rbp\nretq\nadd $0x8,%rsp\nxor %eax,%eax\npop %rbx\npop %rbp\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_1260\nmov rbp, rdi\ncall ___ctype_b_loc\nxor ecx, ecx\nmov esi, 1\nmov rdi, [rax]\nxor eax, eax\nnop dword ptr [rax]\nloc_1238:\nmovzx ebx, bl\nmovzx edx, word ptr [rdi+rbx*2]\ntest dh, 4\ncmovnz eax, esi\nand dh, 8\ncmovnz ecx, esi\nmovzx ebx, byte ptr [rbp+1]\nadd rbp, 1\ntest bl, bl\njnz short loc_1238\nadd rsp, 8\nand eax, ecx\npop rbx\npop rbp\nretn\nloc_1260:\nadd rsp, 8\nxor eax, eax\npop rbx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned __int8 *a1)\n{\n unsigned __int8 v1; // bl\n unsigned __int8 *v2; // rbp\n const unsigned __int16 **v3; // rax\n int v4; // ecx\n const unsigned __int16 *v5; // rdi\n int v6; // eax\n unsigned __int16 v7; // dx\n\n v1 = *a1;\n if ( !*a1 )\n return 0LL;\n v2 = a1;\n v3 = __ctype_b_loc();\n v4 = 0;\n v5 = *v3;\n v6 = 0;\n do\n {\n v7 = v5[v1];\n if ( (v7 & 0x400) != 0 )\n v6 = 1;\n if ( (v7 & 0x800) != 0 )\n v4 = 1;\n v1 = *++v2;\n }\n while ( v1 );\n return v4 & (unsigned int)v6;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_1260\nmov rbp, rdi\ncall ___ctype_b_loc\nxor ecx, ecx\nmov esi, 1\nmov rdi, [rax]\nxor eax, eax\nnop dword ptr [rax]\nloc_1238:\nmovzx ebx, bl\nmovzx edx, word ptr [rdi+rbx*2]\ntest dh, 4\ncmovnz eax, esi\nand dh, 8\ncmovnz ecx, esi\nmovzx ebx, byte ptr [rbp+1]\nadd rbp, 1\ntest bl, bl\njnz short loc_1238\nadd rsp, 8\nand eax, ecx\npop rbx\npop rbp\nretn\nloc_1260:\nadd rsp, 8\nxor eax, eax\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(unsigned __int8 *a1)\n{\n unsigned __int8 v1; // bl\n unsigned __int8 *v2; // rbp\n const unsigned __int16 **v3; // rax\n int v4; // ecx\n const unsigned __int16 *v5; // rdi\n int v6; // eax\n unsigned __int16 v7; // dx\n\n v1 = *a1;\n if ( !*a1 )\n return 0LL;\n v2 = a1;\n v3 = __ctype_b_loc();\n v4 = 0;\n v5 = *v3;\n v6 = 0;\n do\n {\n v7 = v5[v1];\n if ( (v7 & 0x400) != 0 )\n v6 = 1;\n if ( (v7 & 0x800) != 0 )\n v4 = 1;\n v1 = *++v2;\n }\n while ( v1 );\n return v4 & (unsigned int)v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(unsigned char *a1) {\n unsigned char v1;\n unsigned char *v2;\n const unsigned short **v3;\n int v4;\n const unsigned short *v5;\n int v6;\n unsigned short v7;\n v1 = *a1;\n if (!*a1) return 0LL;\n v2 = a1;\n v3 = __ctype_b_loc();\n v4 = 0;\n v5 = *v3;\n v6 = 0;\n do {\n v7 = v5[v1];\n if ((v7 & 1024) != 0) v6 = 1;\n if ((v7 & 2048) != 0) v4 = 1;\n v1 = *++v2;\n } while (v1);\n return v4 & (unsigned int)v6;\n}", + "ida_pseudo_norm": "long long func0(unsigned char *a1) {\n unsigned char v1;\n unsigned char *v2;\n const unsigned short **v3;\n int v4;\n const unsigned short *v5;\n int v6;\n unsigned short v7;\n v1 = *a1;\n if (!*a1) return 0LL;\n v2 = a1;\n v3 = __ctype_b_loc();\n v4 = 0;\n v5 = *v3;\n v6 = 0;\n do {\n v7 = v5[v1];\n if ((v7 & 1024) != 0) v6 = 1;\n if ((v7 & 2048) != 0) v4 = 1;\n v1 = *++v2;\n } while (v1);\n return v4 & (unsigned int)v6;\n}" + }, + { + "index": 193, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int *test_tup, int size, int **result, int *result_size) {\n int *temp_res = malloc(size * sizeof(int));\n int count = 0;\n for (int i = 0; i < size; i++) {\n int j;\n for (j = 0; j < count; j++) {\n if (test_tup[i] == temp_res[j]) {\n break;\n }\n }\n if (j == count) {\n temp_res[count++] = test_tup[i];\n }\n }\n *result = malloc(count * sizeof(int));\n for (int i = 0; i < count; i++) {\n (*result)[i] = temp_res[i];\n }\n *result_size = count;\n free(temp_res);\n}", + "test": "int main() {\n\n int i;\n\n \n\n int tup1[] = {1, 3, 5, 2, 3, 5, 1, 1, 3};\n\n int *res1;\n\n int res1_size;\n\n func0(tup1, 9, &res1, &res1_size);\n\n assert(res1_size == 4);\n\n for (i = 0; i < res1_size; i++) {\n\n assert((res1[i] == 1) || (res1[i] == 2) || (res1[i] == 3) || (res1[i] == 5));\n\n }\n\n free(res1);\n\n\n\n int tup2[] = {2, 3, 4, 4, 5, 6, 6, 7, 8, 8};\n\n int *res2;\n\n int res2_size;\n\n func0(tup2, 10, &res2, &res2_size);\n\n assert(res2_size == 7);\n\n for (i = 0; i < res2_size; i++) {\n\n assert((res2[i] == 2) || (res2[i] == 3) || (res2[i] == 4) || (res2[i] == 5) || (res2[i] == 6) || (res2[i] == 7) || (res2[i] == 8));\n\n }\n\n free(res2);\n\n\n\n int tup3[] = {11, 12, 13, 11, 11, 12, 14, 13};\n\n int *res3;\n\n int res3_size;\n\n func0(tup3, 8, &res3, &res3_size);\n\n assert(res3_size == 4);\n\n for (i = 0; i < res3_size; i++) {\n\n assert((res3[i] == 11) || (res3[i] == 12) || (res3[i] == 13) || (res3[i] == 14));\n\n }\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x40,%rsp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmov %rdx,-0x38(%rbp)\nmov %rcx,-0x40(%rbp)\nmov -0x2c(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0x18(%rbp)\nmovl $0x0,-0x14(%rbp)\njmpq 1273 \nmovl $0x0,-0x10(%rbp)\njmp 1229 \nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x8(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\nje 1233 \naddl $0x1,-0x10(%rbp)\nmov -0x10(%rbp),%eax\ncmp -0x18(%rbp),%eax\njl 11f5 \njmp 1234 \nmov -0x10(%rbp),%eax\ncmp -0x18(%rbp),%eax\njne 126f \nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x18(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x18(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 11ec \nmov -0x18(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,%rdx\nmov -0x38(%rbp),%rax\nmov %rdx,(%rax)\nmovl $0x0,-0xc(%rbp)\njmp 12d4 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x38(%rbp),%rax\nmov (%rax),%rax\nmov -0xc(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x2,%rdx\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x18(%rbp),%eax\njl 12a3 \nmov -0x40(%rbp),%rax\nmov -0x18(%rbp),%edx\nmov %edx,(%rax)\nmov -0x8(%rbp),%rax\nmov %rax,%rdi\ncallq 1080 \nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmov [rbp+var_40], rcx\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp loc_1273\nloc_11EC:\nmov [rbp+var_10], 0\njmp short loc_1229\nloc_11F5:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_1233\nadd [rbp+var_10], 1\nloc_1229:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_18]\njl short loc_11F5\njmp short loc_1234\nloc_1233:\nnop\nloc_1234:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_18]\njnz short loc_126F\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_126F:\nadd [rbp+var_14], 1\nloc_1273:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl loc_11EC\nmov eax, [rbp+var_18]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov rdx, rax\nmov rax, [rbp+var_38]\nmov [rax], rdx\nmov [rbp+var_C], 0\njmp short loc_12D4\nloc_12A3:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nlea rcx, [rdx+rax]\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nshl rdx, 2\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nadd [rbp+var_C], 1\nloc_12D4:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_18]\njl short loc_12A3\nmov rax, [rbp+var_40]\nmov edx, [rbp+var_18]\nmov [rax], edx\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nnop\nleave\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2, void **a3, _DWORD *a4)\n{\n int v4; // eax\n int v7; // [rsp+28h] [rbp-18h]\n int i; // [rsp+2Ch] [rbp-14h]\n int j; // [rsp+30h] [rbp-10h]\n int k; // [rsp+34h] [rbp-Ch]\n _DWORD *ptr; // [rsp+38h] [rbp-8h]\n\n ptr = malloc(4LL * a2);\n v7 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = 0; j < v7 && *(_DWORD *)(4LL * i + a1) != ptr[j]; ++j )\n ;\n if ( j == v7 )\n {\n v4 = v7++;\n ptr[v4] = *(_DWORD *)(4LL * i + a1);\n }\n }\n *a3 = malloc(4LL * v7);\n for ( k = 0; k < v7; ++k )\n *((_DWORD *)*a3 + k) = ptr[k];\n *a4 = v7;\n free(ptr);\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmov [rbp+var_40], rcx\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp loc_1273\nloc_11EC:\nmov [rbp+var_10], 0\njmp short loc_1229\nloc_11F5:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_1233\nadd [rbp+var_10], 1\nloc_1229:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_18]\njl short loc_11F5\njmp short loc_1234\nloc_1233:\nnop\nloc_1234:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_18]\njnz short loc_126F\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_126F:\nadd [rbp+var_14], 1\nloc_1273:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl loc_11EC\nmov eax, [rbp+var_18]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov rdx, rax\nmov rax, [rbp+var_38]\nmov [rax], rdx\nmov [rbp+var_C], 0\njmp short loc_12D4\nloc_12A3:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nlea rcx, [rdx+rax]\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nshl rdx, 2\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nadd [rbp+var_C], 1\nloc_12D4:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_18]\njl short loc_12A3\nmov rax, [rbp+var_40]\nmov edx, [rbp+var_18]\nmov [rax], edx\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nnop\nleave\nretn", + "ida_strip_pseudo": "void __fastcall sub_11A9(__int64 a1, int a2, void **a3, _DWORD *a4)\n{\n int v4; // eax\n int v7; // [rsp+28h] [rbp-18h]\n int i; // [rsp+2Ch] [rbp-14h]\n int j; // [rsp+30h] [rbp-10h]\n int k; // [rsp+34h] [rbp-Ch]\n _DWORD *ptr; // [rsp+38h] [rbp-8h]\n\n ptr = malloc(4LL * a2);\n v7 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = 0; j < v7 && *(_DWORD *)(4LL * i + a1) != ptr[j]; ++j )\n ;\n if ( j == v7 )\n {\n v4 = v7++;\n ptr[v4] = *(_DWORD *)(4LL * i + a1);\n }\n }\n *a3 = malloc(4LL * v7);\n for ( k = 0; k < v7; ++k )\n *((_DWORD *)*a3 + k) = ptr[k];\n *a4 = v7;\n free(ptr);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_11A9(long long a1, int a2, void **a3, uint32_t *a4) {\n int v4;\n int v7;\n int i;\n int j;\n int k;\n uint32_t *ptr;\n ptr = malloc(4LL * a2);\n v7 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = 0; j < v7 && *(uint32_t *)(4LL * i + a1) != ptr[j]; ++j)\n ;\n if (j == v7) {\n v4 = v7++;\n ptr[v4] = *(uint32_t *)(4LL * i + a1);\n }\n }\n *a3 = malloc(4LL * v7);\n for (k = 0; k < v7; ++k) *((uint32_t *)*a3 + k) = ptr[k];\n *a4 = v7;\n free(ptr);\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2, void **a3, uint32_t *a4) {\n int v4;\n int v7;\n int i;\n int j;\n int k;\n uint32_t *ptr;\n ptr = malloc(4LL * a2);\n v7 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = 0; j < v7 && *(uint32_t *)(4LL * i + a1) != ptr[j]; ++j)\n ;\n if (j == v7) {\n v4 = v7++;\n ptr[v4] = *(uint32_t *)(4LL * i + a1);\n }\n }\n *a3 = malloc(4LL * v7);\n for (k = 0; k < v7; ++k) *((uint32_t *)*a3 + k) = ptr[k];\n *a4 = v7;\n free(ptr);\n}" + }, + { + "index": 193, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int *test_tup, int size, int **result, int *result_size) {\n int *temp_res = malloc(size * sizeof(int));\n int count = 0;\n for (int i = 0; i < size; i++) {\n int j;\n for (j = 0; j < count; j++) {\n if (test_tup[i] == temp_res[j]) {\n break;\n }\n }\n if (j == count) {\n temp_res[count++] = test_tup[i];\n }\n }\n *result = malloc(count * sizeof(int));\n for (int i = 0; i < count; i++) {\n (*result)[i] = temp_res[i];\n }\n *result_size = count;\n free(temp_res);\n}", + "test": "int main() {\n\n int i;\n\n \n\n int tup1[] = {1, 3, 5, 2, 3, 5, 1, 1, 3};\n\n int *res1;\n\n int res1_size;\n\n func0(tup1, 9, &res1, &res1_size);\n\n assert(res1_size == 4);\n\n for (i = 0; i < res1_size; i++) {\n\n assert((res1[i] == 1) || (res1[i] == 2) || (res1[i] == 3) || (res1[i] == 5));\n\n }\n\n free(res1);\n\n\n\n int tup2[] = {2, 3, 4, 4, 5, 6, 6, 7, 8, 8};\n\n int *res2;\n\n int res2_size;\n\n func0(tup2, 10, &res2, &res2_size);\n\n assert(res2_size == 7);\n\n for (i = 0; i < res2_size; i++) {\n\n assert((res2[i] == 2) || (res2[i] == 3) || (res2[i] == 4) || (res2[i] == 5) || (res2[i] == 6) || (res2[i] == 7) || (res2[i] == 8));\n\n }\n\n free(res2);\n\n\n\n int tup3[] = {11, 12, 13, 11, 11, 12, 14, 13};\n\n int *res3;\n\n int res3_size;\n\n func0(tup3, 8, &res3, &res3_size);\n\n assert(res3_size == 4);\n\n for (i = 0; i < res3_size; i++) {\n\n assert((res3[i] == 11) || (res3[i] == 12) || (res3[i] == 13) || (res3[i] == 14));\n\n }\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%r14\nmov %esi,%ebp\nmov %rdx,%r12\nmov %rcx,%r13\nmovslq %esi,%rdi\nshl $0x2,%rdi\ncallq 10b0 \nmov %rax,%rbx\ntest %ebp,%ebp\njle 128b \nmov %r14,%r8\nlea -0x1(%rbp),%eax\nlea (%r14,%rax,4),%r9\nmov $0x0,%ebp\nmov $0x0,%edx\nmov $0x0,%r11d\nmov $0x0,%r10d\njmp 1213 \nmov %rcx,%rax\nmov %eax,%edx\ncmp (%rbx,%rax,4),%esi\nje 120f \nlea 0x1(%rax),%edx\nlea 0x1(%rax),%rcx\ncmp %rdi,%rax\njne 11f9 \nadd $0x4,%r8\ncmp %ebp,%edx\nje 122c \ncmp %r9,%r8\nje 123f \ntest %ebp,%ebp\njle 123a \nmov 0x4(%r8),%esi\nlea -0x1(%rbp),%edi\nmov %r10,%rax\njmp 11fc \nmovslq %ebp,%rax\nmov (%r8),%edx\nmov %edx,(%rbx,%rax,4)\nlea 0x1(%rbp),%ebp\njmp 1217 \nmov %r11d,%edx\njmp 120f \nmovslq %ebp,%rdi\nshl $0x2,%rdi\ncallq 10b0 \nmov %rax,(%r12)\ntest %ebp,%ebp\njle 1276 \nlea -0x1(%rbp),%eax\nlea 0x4(,%rax,4),%rsi\nmov $0x0,%eax\nmov (%r12),%rdx\nmov (%rbx,%rax,1),%ecx\nmov %ecx,(%rdx,%rax,1)\nadd $0x4,%rax\ncmp %rax,%rsi\njne 1263 \nmov %ebp,0x0(%r13)\nmov %rbx,%rdi\ncallq 1080 \npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nmov $0x0,%edi\ncallq 10b0 \nmov %rax,(%r12)\nmov $0x0,%ebp\njmp 1276 \n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov r15d, esi\nmov r12, rdx\nmov r13, rcx\nmovsxd r14, esi\nshl r14, 2\nmov rdi, r14; size\ncall _malloc\nmov rbp, rax\ntest r15d, r15d\njle loc_1278\nmov rsi, rbx\nlea rdi, [rbx+r14]\nmov ebx, 0\njmp short loc_11FD\nloc_11F0:\ncmp ebx, eax\njz short loc_121F\nloc_11F4:\nadd rsi, 4\ncmp rsi, rdi\njz short loc_122D\nloc_11FD:\nmov eax, 0\ntest ebx, ebx\njle short loc_11F0\nmov ecx, [rsi]\nmov rdx, rbp\nmov eax, 0\nloc_1210:\ncmp ecx, [rdx]\njz short loc_11F0\nadd eax, 1\nadd rdx, 4\ncmp eax, ebx\njnz short loc_1210\nloc_121F:\nmovsxd rax, ebx\nmov edx, [rsi]\nmov [rbp+rax*4+0], edx\nlea ebx, [rbx+1]\njmp short loc_11F4\nloc_122D:\nmovsxd r14, ebx\nshl r14, 2\nmov rdi, r14; size\ncall _malloc\nmov [r12], rax\ntest ebx, ebx\njle short loc_125D\nmov eax, 0\nloc_1249:\nmov rdx, [r12]\nmov ecx, [rbp+rax+0]\nmov [rdx+rax], ecx\nadd rax, 4\ncmp r14, rax\njnz short loc_1249\nloc_125D:\nmov [r13+0], ebx\nmov rdi, rbp; ptr\ncall _free\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1278:\nmov edi, 0; size\ncall _malloc\nmov [r12], rax\nmov ebx, 0\njmp short loc_125D", + "ida_pseudo": "void __fastcall func0(_DWORD *a1, int a2, void **a3, int *a4)\n{\n size_t v6; // r14\n _DWORD *v7; // rbp\n _DWORD *v8; // rsi\n _DWORD *v9; // rdi\n int v10; // ebx\n int v11; // eax\n _DWORD *v12; // rdx\n __int64 i; // rax\n\n v6 = a2;\n v7 = malloc(v6 * 4);\n if ( a2 <= 0 )\n {\n *a3 = malloc(0LL);\n v10 = 0;\n }\n else\n {\n v8 = a1;\n v9 = &a1[v6];\n v10 = 0;\n do\n {\n v11 = 0;\n if ( v10 > 0 )\n {\n v12 = v7;\n v11 = 0;\n while ( *v8 != *v12 )\n {\n ++v11;\n ++v12;\n if ( v11 == v10 )\n goto LABEL_9;\n }\n }\n if ( v10 == v11 )\nLABEL_9:\n v7[v10++] = *v8;\n ++v8;\n }\n while ( v8 != v9 );\n *a3 = malloc(4LL * v10);\n if ( v10 > 0 )\n {\n for ( i = 0LL; i != v10; ++i )\n *(_DWORD *)((char *)*a3 + i * 4) = v7[i];\n }\n }\n *a4 = v10;\n free(v7);\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov r15d, esi\nmov r12, rdx\nmov r13, rcx\nmovsxd r14, esi\nshl r14, 2\nmov rdi, r14; size\ncall _malloc\nmov rbp, rax\ntest r15d, r15d\njle loc_1278\nmov rsi, rbx\nlea rdi, [rbx+r14]\nmov ebx, 0\njmp short loc_11FD\nloc_11F0:\ncmp ebx, eax\njz short loc_121F\nloc_11F4:\nadd rsi, 4\ncmp rsi, rdi\njz short loc_122D\nloc_11FD:\nmov eax, 0\ntest ebx, ebx\njle short loc_11F0\nmov ecx, [rsi]\nmov rdx, rbp\nmov eax, 0\nloc_1210:\ncmp ecx, [rdx]\njz short loc_11F0\nadd eax, 1\nadd rdx, 4\ncmp eax, ebx\njnz short loc_1210\nloc_121F:\nmovsxd rax, ebx\nmov edx, [rsi]\nmov [rbp+rax*4+0], edx\nlea ebx, [rbx+1]\njmp short loc_11F4\nloc_122D:\nmovsxd r14, ebx\nshl r14, 2\nmov rdi, r14; size\ncall _malloc\nmov [r12], rax\ntest ebx, ebx\njle short loc_125D\nmov eax, 0\nloc_1249:\nmov rdx, [r12]\nmov ecx, [rbp+rax+0]\nmov [rdx+rax], ecx\nadd rax, 4\ncmp r14, rax\njnz short loc_1249\nloc_125D:\nmov [r13+0], ebx\nmov rdi, rbp; ptr\ncall _free\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1278:\nmov edi, 0; size\ncall _malloc\nmov [r12], rax\nmov ebx, 0\njmp short loc_125D", + "ida_strip_pseudo": "void __fastcall sub_11A9(_DWORD *a1, int a2, void **a3, int *a4)\n{\n size_t v6; // r14\n _DWORD *v7; // rbp\n _DWORD *v8; // rsi\n _DWORD *v9; // rdi\n int v10; // ebx\n int v11; // eax\n _DWORD *v12; // rdx\n __int64 i; // rax\n\n v6 = a2;\n v7 = malloc(v6 * 4);\n if ( a2 <= 0 )\n {\n *a3 = malloc(0LL);\n v10 = 0;\n }\n else\n {\n v8 = a1;\n v9 = &a1[v6];\n v10 = 0;\n do\n {\n v11 = 0;\n if ( v10 > 0 )\n {\n v12 = v7;\n v11 = 0;\n while ( *v8 != *v12 )\n {\n ++v11;\n ++v12;\n if ( v11 == v10 )\n goto LABEL_9;\n }\n }\n if ( v10 == v11 )\nLABEL_9:\n v7[v10++] = *v8;\n ++v8;\n }\n while ( v8 != v9 );\n *a3 = malloc(4LL * v10);\n if ( v10 > 0 )\n {\n for ( i = 0LL; i != v10; ++i )\n *(_DWORD *)((char *)*a3 + i * 4) = v7[i];\n }\n }\n *a4 = v10;\n free(v7);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_11A9(uint32_t *a1, int a2, void **a3, int *a4) {\n unsigned int v6;\n uint32_t *v7;\n uint32_t *v8;\n uint32_t *v9;\n int v10;\n int v11;\n uint32_t *v12;\n long long i;\n v6 = a2;\n v7 = malloc(v6 * 4);\n if (a2 <= 0) {\n *a3 = malloc(0LL);\n v10 = 0;\n } else {\n v8 = a1;\n v9 = &a1[v6];\n v10 = 0;\n do {\n v11 = 0;\n if (v10 > 0) {\n v12 = v7;\n v11 = 0;\n while (*v8 != *v12) {\n ++v11;\n ++v12;\n if (v11 == v10) goto LABEL_9;\n }\n }\n if (v10 == v11)\n LABEL_9:\n v7[v10++] = *v8;\n ++v8;\n } while (v8 != v9);\n *a3 = malloc(4LL * v10);\n if (v10 > 0) {\n for (i = 0LL; i != v10; ++i) *(uint32_t *)((char *)*a3 + i * 4) = v7[i];\n }\n }\n *a4 = v10;\n free(v7);\n}", + "ida_pseudo_norm": "void func0(uint32_t *a1, int a2, void **a3, int *a4) {\n unsigned int v6;\n uint32_t *v7;\n uint32_t *v8;\n uint32_t *v9;\n int v10;\n int v11;\n uint32_t *v12;\n long long i;\n v6 = a2;\n v7 = malloc(v6 * 4);\n if (a2 <= 0) {\n *a3 = malloc(0LL);\n v10 = 0;\n } else {\n v8 = a1;\n v9 = &a1[v6];\n v10 = 0;\n do {\n v11 = 0;\n if (v10 > 0) {\n v12 = v7;\n v11 = 0;\n while (*v8 != *v12) {\n ++v11;\n ++v12;\n if (v11 == v10) goto LABEL_9;\n }\n }\n if (v10 == v11)\n LABEL_9:\n v7[v10++] = *v8;\n ++v8;\n } while (v8 != v9);\n *a3 = malloc(4LL * v10);\n if (v10 > 0) {\n for (i = 0LL; i != v10; ++i) *(uint32_t *)((char *)*a3 + i * 4) = v7[i];\n }\n }\n *a4 = v10;\n free(v7);\n}" + }, + { + "index": 193, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int *test_tup, int size, int **result, int *result_size) {\n int *temp_res = malloc(size * sizeof(int));\n int count = 0;\n for (int i = 0; i < size; i++) {\n int j;\n for (j = 0; j < count; j++) {\n if (test_tup[i] == temp_res[j]) {\n break;\n }\n }\n if (j == count) {\n temp_res[count++] = test_tup[i];\n }\n }\n *result = malloc(count * sizeof(int));\n for (int i = 0; i < count; i++) {\n (*result)[i] = temp_res[i];\n }\n *result_size = count;\n free(temp_res);\n}", + "test": "int main() {\n\n int i;\n\n \n\n int tup1[] = {1, 3, 5, 2, 3, 5, 1, 1, 3};\n\n int *res1;\n\n int res1_size;\n\n func0(tup1, 9, &res1, &res1_size);\n\n assert(res1_size == 4);\n\n for (i = 0; i < res1_size; i++) {\n\n assert((res1[i] == 1) || (res1[i] == 2) || (res1[i] == 3) || (res1[i] == 5));\n\n }\n\n free(res1);\n\n\n\n int tup2[] = {2, 3, 4, 4, 5, 6, 6, 7, 8, 8};\n\n int *res2;\n\n int res2_size;\n\n func0(tup2, 10, &res2, &res2_size);\n\n assert(res2_size == 7);\n\n for (i = 0; i < res2_size; i++) {\n\n assert((res2[i] == 2) || (res2[i] == 3) || (res2[i] == 4) || (res2[i] == 5) || (res2[i] == 6) || (res2[i] == 7) || (res2[i] == 8));\n\n }\n\n free(res2);\n\n\n\n int tup3[] = {11, 12, 13, 11, 11, 12, 14, 13};\n\n int *res3;\n\n int res3_size;\n\n func0(tup3, 8, &res3, &res3_size);\n\n assert(res3_size == 4);\n\n for (i = 0; i < res3_size; i++) {\n\n assert((res3[i] == 11) || (res3[i] == 12) || (res3[i] == 13) || (res3[i] == 14));\n\n }\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\nmov %rdi,%r14\nmovslq %esi,%rdi\npush %r13\nmov %rdi,%r13\nshl $0x2,%rdi\npush %r12\nmov %rdx,%r12\npush %rbp\npush %rbx\nmov %rcx,%rbx\ncallq 10b0 \nmov %rax,%rbp\ntest %r13d,%r13d\njle 1560 \nlea -0x1(%r13),%eax\nmov %r14,%rdi\nxor %r13d,%r13d\nlea 0x4(%r14,%rax,4),%r9\nxor %esi,%esi\ntest %r13d,%r13d\njle 1540 \nlea -0x1(%r13),%edx\nmov (%rdi),%ecx\nmov $0x1,%eax\nadd $0x2,%rdx\njmp 14db \nnopl 0x0(%rax)\nmov %eax,%esi\nadd $0x1,%rax\ncmp %rax,%rdx\nje 1540 \ncmp -0x4(%rbp,%rax,4),%ecx\njne 14d0 \nmovslq %r13d,%r8\nshl $0x2,%r8\nadd $0x4,%rdi\ncmp %rdi,%r9\njne 14b0 \nmov %r8,%rdi\ncallq 10b0 \nmov %rax,(%r12)\ntest %r13d,%r13d\njle 1523 \nlea -0x1(%r13),%esi\nxor %edx,%edx\nnopl 0x0(%rax,%rax,1)\nmov 0x0(%rbp,%rdx,4),%ecx\nmov %ecx,(%rax,%rdx,4)\nmov %rdx,%rcx\nadd $0x1,%rdx\ncmp %rcx,%rsi\njne 1510 \nmov %r13d,(%rbx)\nmov %rbp,%rdi\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\njmpq 1080 \nnopw %cs:0x0(%rax,%rax,1)\nmovslq %r13d,%rax\nlea 0x0(,%rax,4),%r8\ncmp %esi,%r13d\njne 14e8 \nmov (%rdi),%edx\nadd $0x1,%r13d\nadd $0x4,%r8\nmov %edx,0x0(%rbp,%rax,4)\njmp 14e8 \nxor %edi,%edi\nxor %r13d,%r13d\ncallq 10b0 \nmov %rax,(%r12)\njmp 1523 \n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12, rdx\npush rbp\nmov rbp, rcx\npush rbx\nmov rbx, rdi\nmovsxd rdi, esi\nlea r14, ds:0[rdi*4]\nmov r15, rdi\nmov rdi, r14; size\nsub rsp, 8\ncall _malloc\nmov r13, rax\ntest r15d, r15d\njle loc_1503\nmov rsi, rbx\nlea rdi, [rbx+r14]\nxor ebx, ebx\nloc_1476:\nxor eax, eax\ntest ebx, ebx\njle short loc_1497\nloc_147C:\nmov ecx, [rsi]\nmov rdx, r13\nxor eax, eax\njmp short loc_1493\nloc_1488:\nadd eax, 1\nadd rdx, 4\ncmp ebx, eax\njz short loc_14E8\nloc_1493:\ncmp ecx, [rdx]\njnz short loc_1488\nloc_1497:\ncmp ebx, eax\njz short loc_14E8\nadd rsi, 4\ncmp rsi, rdi\njnz short loc_1476\nloc_14A4:\nmovsxd rdi, ebx\nshl rdi, 2; size\ncall _malloc\nmov [r12], rax\nmov rdi, rax; dest\ntest ebx, ebx\njle short loc_14C9\nmov edx, ebx\nmov rsi, r13; src\nshl rdx, 2; n\ncall _memcpy\nloc_14C9:\nmov [rbp+0], ebx\nadd rsp, 8\nmov rdi, r13; ptr\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\njmp _free\nloc_14E8:\nmov edx, [rsi]\nlea ebx, [rax+1]\nadd rsi, 4\ncdqe\nmov [r13+rax*4+0], edx\ncmp rsi, rdi\njnz loc_147C\njmp short loc_14A4\nloc_1503:\nxor edi, edi; size\nxor ebx, ebx\ncall _malloc\nmov [r12], rax\njmp short loc_14C9", + "ida_pseudo": "void __fastcall func0(int *a1, int a2, void **a3, int *a4)\n{\n size_t v6; // r14\n _DWORD *v7; // r13\n int *v8; // rsi\n int *v9; // rdi\n int v10; // ebx\n int v11; // eax\n _DWORD *v12; // rdx\n void *v13; // rax\n int v14; // edx\n\n v6 = a2;\n v7 = malloc(v6 * 4);\n if ( a2 <= 0 )\n {\n v10 = 0;\n *a3 = malloc(0LL);\n goto LABEL_11;\n }\n v8 = a1;\n v9 = &a1[v6];\n v10 = 0;\nLABEL_3:\n v11 = 0;\n if ( v10 <= 0 )\n goto LABEL_7;\n do\n {\n v12 = v7;\n v11 = 0;\n while ( *v8 != *v12 )\n {\n ++v11;\n ++v12;\n if ( v10 == v11 )\n goto LABEL_12;\n }\nLABEL_7:\n if ( v10 != v11 )\n {\n if ( ++v8 == v9 )\n break;\n goto LABEL_3;\n }\nLABEL_12:\n v14 = *v8;\n v10 = v11 + 1;\n ++v8;\n v7[v11] = v14;\n }\n while ( v8 != v9 );\n v13 = malloc(4LL * v10);\n *a3 = v13;\n if ( v10 > 0 )\n memcpy(v13, v7, 4LL * (unsigned int)v10);\nLABEL_11:\n *a4 = v10;\n free(v7);\n}", + "ida_strip_asm": "sub_1430:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12, rdx\npush rbp\nmov rbp, rcx\npush rbx\nmov rbx, rdi\nmovsxd rdi, esi\nlea r14, ds:0[rdi*4]\nmov r15, rdi\nmov rdi, r14; size\nsub rsp, 8\ncall _malloc\nmov r13, rax\ntest r15d, r15d\njle loc_1503\nmov rsi, rbx\nlea rdi, [rbx+r14]\nxor ebx, ebx\nloc_1476:\nxor eax, eax\ntest ebx, ebx\njle short loc_1497\nloc_147C:\nmov ecx, [rsi]\nmov rdx, r13\nxor eax, eax\njmp short loc_1493\nloc_1488:\nadd eax, 1\nadd rdx, 4\ncmp ebx, eax\njz short loc_14E8\nloc_1493:\ncmp ecx, [rdx]\njnz short loc_1488\nloc_1497:\ncmp ebx, eax\njz short loc_14E8\nadd rsi, 4\ncmp rsi, rdi\njnz short loc_1476\nloc_14A4:\nmovsxd rdi, ebx\nshl rdi, 2; size\ncall _malloc\nmov [r12], rax\nmov rdi, rax; dest\ntest ebx, ebx\njle short loc_14C9\nmov edx, ebx\nmov rsi, r13; src\nshl rdx, 2; n\ncall _memcpy\nloc_14C9:\nmov [rbp+0], ebx\nadd rsp, 8\nmov rdi, r13; ptr\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\njmp _free\nloc_14E8:\nmov edx, [rsi]\nlea ebx, [rax+1]\nadd rsi, 4\ncdqe\nmov [r13+rax*4+0], edx\ncmp rsi, rdi\njnz loc_147C\njmp short loc_14A4\nloc_1503:\nxor edi, edi; size\nxor ebx, ebx\ncall _malloc\nmov [r12], rax\njmp short loc_14C9", + "ida_strip_pseudo": "void __fastcall sub_1430(int *a1, int a2, void **a3, int *a4)\n{\n size_t v6; // r14\n _DWORD *v7; // r13\n int *v8; // rsi\n int *v9; // rdi\n int v10; // ebx\n int v11; // eax\n _DWORD *v12; // rdx\n void *v13; // rax\n int v14; // edx\n\n v6 = a2;\n v7 = malloc(v6 * 4);\n if ( a2 <= 0 )\n {\n v10 = 0;\n *a3 = malloc(0LL);\n goto LABEL_11;\n }\n v8 = a1;\n v9 = &a1[v6];\n v10 = 0;\nLABEL_3:\n v11 = 0;\n if ( v10 <= 0 )\n goto LABEL_7;\n do\n {\n v12 = v7;\n v11 = 0;\n while ( *v8 != *v12 )\n {\n ++v11;\n ++v12;\n if ( v10 == v11 )\n goto LABEL_12;\n }\nLABEL_7:\n if ( v10 != v11 )\n {\n if ( ++v8 == v9 )\n break;\n goto LABEL_3;\n }\nLABEL_12:\n v14 = *v8;\n v10 = v11 + 1;\n ++v8;\n v7[v11] = v14;\n }\n while ( v8 != v9 );\n v13 = malloc(4LL * v10);\n *a3 = v13;\n if ( v10 > 0 )\n memcpy(v13, v7, 4LL * (unsigned int)v10);\nLABEL_11:\n *a4 = v10;\n free(v7);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1430(int *a1, int a2, void **a3, int *a4) {\n unsigned int v6;\n uint32_t *v7;\n int *v8;\n int *v9;\n int v10;\n int v11;\n uint32_t *v12;\n void *v13;\n int v14;\n v6 = a2;\n v7 = malloc(v6 * 4);\n if (a2 <= 0) {\n v10 = 0;\n *a3 = malloc(0LL);\n goto LABEL_11;\n }\n v8 = a1;\n v9 = &a1[v6];\n v10 = 0;\nLABEL_3:\n v11 = 0;\n if (v10 <= 0) goto LABEL_7;\n do {\n v12 = v7;\n v11 = 0;\n while (*v8 != *v12) {\n ++v11;\n ++v12;\n if (v10 == v11) goto LABEL_12;\n }\n LABEL_7:\n if (v10 != v11) {\n if (++v8 == v9) break;\n goto LABEL_3;\n }\n LABEL_12:\n v14 = *v8;\n v10 = v11 + 1;\n ++v8;\n v7[v11] = v14;\n } while (v8 != v9);\n v13 = malloc(4LL * v10);\n *a3 = v13;\n if (v10 > 0) memcpy(v13, v7, 4LL * (unsigned int)v10);\nLABEL_11:\n *a4 = v10;\n free(v7);\n}", + "ida_pseudo_norm": "void func0(int *a1, int a2, void **a3, int *a4) {\n unsigned int v6;\n uint32_t *v7;\n int *v8;\n int *v9;\n int v10;\n int v11;\n uint32_t *v12;\n void *v13;\n int v14;\n v6 = a2;\n v7 = malloc(v6 * 4);\n if (a2 <= 0) {\n v10 = 0;\n *a3 = malloc(0LL);\n goto LABEL_11;\n }\n v8 = a1;\n v9 = &a1[v6];\n v10 = 0;\nLABEL_3:\n v11 = 0;\n if (v10 <= 0) goto LABEL_7;\n do {\n v12 = v7;\n v11 = 0;\n while (*v8 != *v12) {\n ++v11;\n ++v12;\n if (v10 == v11) goto LABEL_12;\n }\n LABEL_7:\n if (v10 != v11) {\n if (++v8 == v9) break;\n goto LABEL_3;\n }\n LABEL_12:\n v14 = *v8;\n v10 = v11 + 1;\n ++v8;\n v7[v11] = v14;\n } while (v8 != v9);\n v13 = malloc(4LL * v10);\n *a3 = v13;\n if (v10 > 0) memcpy(v13, v7, 4LL * (unsigned int)v10);\nLABEL_11:\n *a4 = v10;\n free(v7);\n}" + }, + { + "index": 193, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int *test_tup, int size, int **result, int *result_size) {\n int *temp_res = malloc(size * sizeof(int));\n int count = 0;\n for (int i = 0; i < size; i++) {\n int j;\n for (j = 0; j < count; j++) {\n if (test_tup[i] == temp_res[j]) {\n break;\n }\n }\n if (j == count) {\n temp_res[count++] = test_tup[i];\n }\n }\n *result = malloc(count * sizeof(int));\n for (int i = 0; i < count; i++) {\n (*result)[i] = temp_res[i];\n }\n *result_size = count;\n free(temp_res);\n}", + "test": "int main() {\n\n int i;\n\n \n\n int tup1[] = {1, 3, 5, 2, 3, 5, 1, 1, 3};\n\n int *res1;\n\n int res1_size;\n\n func0(tup1, 9, &res1, &res1_size);\n\n assert(res1_size == 4);\n\n for (i = 0; i < res1_size; i++) {\n\n assert((res1[i] == 1) || (res1[i] == 2) || (res1[i] == 3) || (res1[i] == 5));\n\n }\n\n free(res1);\n\n\n\n int tup2[] = {2, 3, 4, 4, 5, 6, 6, 7, 8, 8};\n\n int *res2;\n\n int res2_size;\n\n func0(tup2, 10, &res2, &res2_size);\n\n assert(res2_size == 7);\n\n for (i = 0; i < res2_size; i++) {\n\n assert((res2[i] == 2) || (res2[i] == 3) || (res2[i] == 4) || (res2[i] == 5) || (res2[i] == 6) || (res2[i] == 7) || (res2[i] == 8));\n\n }\n\n free(res2);\n\n\n\n int tup3[] = {11, 12, 13, 11, 11, 12, 14, 13};\n\n int *res3;\n\n int res3_size;\n\n func0(tup3, 8, &res3, &res3_size);\n\n assert(res3_size == 4);\n\n for (i = 0; i < res3_size; i++) {\n\n assert((res3[i] == 11) || (res3[i] == 12) || (res3[i] == 13) || (res3[i] == 14));\n\n }\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\nmov %rdi,%r14\nmovslq %esi,%rdi\npush %r13\nmov %rdi,%r13\nshl $0x2,%rdi\npush %r12\npush %rbp\nmov %rdx,%rbp\npush %rbx\nmov %rcx,%rbx\ncallq 10d0 \nmov %rax,%r12\ntest %r13d,%r13d\njle 1590 \nlea -0x1(%r13),%eax\nmov %r14,%rdi\nxor %r13d,%r13d\nlea 0x4(%r14,%rax,4),%r9\nxor %esi,%esi\ntest %r13d,%r13d\njle 1570 \nlea -0x1(%r13),%edx\nmov (%rdi),%ecx\nmov $0x1,%eax\nadd $0x2,%rdx\njmp 151b \nnopl 0x0(%rax,%rax,1)\nmov %eax,%esi\nadd $0x1,%rax\ncmp %rax,%rdx\nje 1570 \ncmp -0x4(%r12,%rax,4),%ecx\njne 1510 \nmovslq %r13d,%r8\nshl $0x2,%r8\nadd $0x4,%rdi\ncmp %r9,%rdi\njne 14f0 \nmov %r8,%rdi\ncallq 10d0 \nmov %rax,0x0(%rbp)\nmov %rax,%rdi\ntest %r13d,%r13d\njle 155a \nlea -0x1(%r13),%eax\nmov %r12,%rsi\nlea 0x4(,%rax,4),%rdx\ncallq 10c0 \nmov %r13d,(%rbx)\nmov %r12,%rdi\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\njmpq 1090 \nnopl (%rax)\nmovslq %r13d,%rax\nlea 0x0(,%rax,4),%r8\ncmp %esi,%r13d\njne 1529 \nmov (%rdi),%edx\nadd $0x1,%r13d\nadd $0x4,%r8\nmov %edx,(%r12,%rax,4)\njmp 1529 \nxor %edi,%edi\nxor %r13d,%r13d\ncallq 10d0 \nmov %rax,0x0(%rbp)\njmp 155a \n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\nmov r13, rdi\nmovsxd rdi, esi\npush r12\nmov r15, rdi\nmov r12, rdx\npush rbp\nmov rbp, rcx\npush rbx\nlea rbx, ds:0[rdi*4]\nmov rdi, rbx; size\nsub rsp, 8\ncall _malloc\nmov r14, rax\ntest r15d, r15d\njle loc_15A3\nlea rdi, [r13+rbx+0]\nmov rsi, r13\nxor ebx, ebx\nloc_14F7:\nxor eax, eax\ntest ebx, ebx\njle short loc_151F\nloc_14FD:\nmov ecx, [rsi]\nmov rdx, r14\nxor eax, eax\njmp short loc_151B\nloc_1510:\nadd eax, 1\nadd rdx, 4\ncmp eax, ebx\njz short loc_1570\nloc_151B:\ncmp ecx, [rdx]\njnz short loc_1510\nloc_151F:\ncmp ebx, eax\njz short loc_1570\nadd rsi, 4\ncmp rsi, rdi\njnz short loc_14F7\nmovsxd rdi, ebx\nshl rdi, 2; size\ncall _malloc\nmov [r12], rax\nmov rdi, rax; dest\ntest ebx, ebx\njle short loc_1551\nloc_1543:\nmov edx, ebx\nmov rsi, r14; src\nshl rdx, 2; n\ncall _memcpy\nloc_1551:\nmov [rbp+0], ebx\nadd rsp, 8\nmov rdi, r14; ptr\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\njmp _free\nloc_1570:\nmov eax, [rsi]\nadd rsi, 4\nlea r13d, [rbx+1]\nmov [r14+rbx*4], eax\ncmp rdi, rsi\njz short loc_158B\nmovsxd rbx, r13d\njmp loc_14FD\nloc_158B:\nmovsxd rdi, r13d\nmov ebx, r13d\nshl rdi, 2; size\ncall _malloc\nmov [r12], rax\nmov rdi, rax\njmp short loc_1543\nloc_15A3:\nxor edi, edi; size\nxor ebx, ebx\ncall _malloc\nmov [r12], rax\njmp short loc_1551", + "ida_pseudo": "void __fastcall func0(int *a1, int a2, void **a3, _DWORD *a4)\n{\n _DWORD *v7; // r14\n int *v8; // rdi\n int *v9; // rsi\n __int64 v10; // rbx\n int v11; // eax\n _DWORD *v12; // rdx\n void *v13; // rax\n void *v14; // rdi\n int v15; // eax\n int v16; // r13d\n void *v17; // rax\n\n v7 = malloc(4LL * a2);\n if ( a2 <= 0 )\n {\n LODWORD(v10) = 0;\n *a3 = malloc(0LL);\n goto LABEL_11;\n }\n v8 = &a1[a2];\n v9 = a1;\n v10 = 0LL;\nLABEL_3:\n v11 = 0;\n if ( (int)v10 <= 0 )\n goto LABEL_7;\n while ( 1 )\n {\n v12 = v7;\n v11 = 0;\n while ( *v9 != *v12 )\n {\n ++v11;\n ++v12;\n if ( v11 == (_DWORD)v10 )\n goto LABEL_12;\n }\nLABEL_7:\n if ( (_DWORD)v10 != v11 )\n {\n if ( ++v9 == v8 )\n {\n v13 = malloc(4LL * (int)v10);\n *a3 = v13;\n v14 = v13;\n if ( (int)v10 > 0 )\n goto LABEL_10;\n goto LABEL_11;\n }\n goto LABEL_3;\n }\nLABEL_12:\n v15 = *v9++;\n v16 = v10 + 1;\n v7[v10] = v15;\n if ( v8 == v9 )\n break;\n v10 = v16;\n }\n LODWORD(v10) = v10 + 1;\n v17 = malloc(4LL * v16);\n *a3 = v17;\n v14 = v17;\nLABEL_10:\n memcpy(v14, v7, 4LL * (unsigned int)v10);\nLABEL_11:\n *a4 = v10;\n free(v7);\n}", + "ida_strip_asm": "sub_14B0:\nendbr64\npush r15\npush r14\npush r13\nmov r13, rdi\nmovsxd rdi, esi\npush r12\nmov r15, rdi\nmov r12, rdx\npush rbp\nmov rbp, rcx\npush rbx\nlea rbx, ds:0[rdi*4]\nmov rdi, rbx; size\nsub rsp, 8\ncall _malloc\nmov r14, rax\ntest r15d, r15d\njle loc_15A3\nlea rdi, [r13+rbx+0]\nmov rsi, r13\nxor ebx, ebx\nloc_14F7:\nxor eax, eax\ntest ebx, ebx\njle short loc_151F\nloc_14FD:\nmov ecx, [rsi]\nmov rdx, r14\nxor eax, eax\njmp short loc_151B\nloc_1510:\nadd eax, 1\nadd rdx, 4\ncmp eax, ebx\njz short loc_1570\nloc_151B:\ncmp ecx, [rdx]\njnz short loc_1510\nloc_151F:\ncmp ebx, eax\njz short loc_1570\nadd rsi, 4\ncmp rsi, rdi\njnz short loc_14F7\nmovsxd rdi, ebx\nshl rdi, 2; size\ncall _malloc\nmov [r12], rax\nmov rdi, rax; dest\ntest ebx, ebx\njle short loc_1551\nloc_1543:\nmov edx, ebx\nmov rsi, r14; src\nshl rdx, 2; n\ncall _memcpy\nloc_1551:\nmov [rbp+0], ebx\nadd rsp, 8\nmov rdi, r14; ptr\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\njmp _free\nloc_1570:\nmov eax, [rsi]\nadd rsi, 4\nlea r13d, [rbx+1]\nmov [r14+rbx*4], eax\ncmp rdi, rsi\njz short loc_158B\nmovsxd rbx, r13d\njmp loc_14FD\nloc_158B:\nmovsxd rdi, r13d\nmov ebx, r13d\nshl rdi, 2; size\ncall _malloc\nmov [r12], rax\nmov rdi, rax\njmp short loc_1543\nloc_15A3:\nxor edi, edi; size\nxor ebx, ebx\ncall _malloc\nmov [r12], rax\njmp short loc_1551", + "ida_strip_pseudo": "void __fastcall sub_14B0(int *a1, int a2, void **a3, _DWORD *a4)\n{\n _DWORD *v7; // r14\n int *v8; // rdi\n int *v9; // rsi\n __int64 v10; // rbx\n int v11; // eax\n _DWORD *v12; // rdx\n void *v13; // rax\n void *v14; // rdi\n int v15; // eax\n int v16; // r13d\n void *v17; // rax\n\n v7 = malloc(4LL * a2);\n if ( a2 <= 0 )\n {\n LODWORD(v10) = 0;\n *a3 = malloc(0LL);\n goto LABEL_11;\n }\n v8 = &a1[a2];\n v9 = a1;\n v10 = 0LL;\nLABEL_3:\n v11 = 0;\n if ( (int)v10 <= 0 )\n goto LABEL_7;\n while ( 1 )\n {\n v12 = v7;\n v11 = 0;\n while ( *v9 != *v12 )\n {\n ++v11;\n ++v12;\n if ( v11 == (_DWORD)v10 )\n goto LABEL_12;\n }\nLABEL_7:\n if ( (_DWORD)v10 != v11 )\n {\n if ( ++v9 == v8 )\n {\n v13 = malloc(4LL * (int)v10);\n *a3 = v13;\n v14 = v13;\n if ( (int)v10 > 0 )\n goto LABEL_10;\n goto LABEL_11;\n }\n goto LABEL_3;\n }\nLABEL_12:\n v15 = *v9++;\n v16 = v10 + 1;\n v7[v10] = v15;\n if ( v8 == v9 )\n break;\n v10 = v16;\n }\n LODWORD(v10) = v10 + 1;\n v17 = malloc(4LL * v16);\n *a3 = v17;\n v14 = v17;\nLABEL_10:\n memcpy(v14, v7, 4LL * (unsigned int)v10);\nLABEL_11:\n *a4 = v10;\n free(v7);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_14B0(int *a1, int a2, void **a3, uint32_t *a4) {\n uint32_t *v7;\n int *v8;\n int *v9;\n long long v10;\n int v11;\n uint32_t *v12;\n void *v13;\n void *v14;\n int v15;\n int v16;\n void *v17;\n v7 = malloc(4LL * a2);\n if (a2 <= 0) {\n LODWORD(v10) = 0;\n *a3 = malloc(0LL);\n goto LABEL_11;\n }\n v8 = &a1[a2];\n v9 = a1;\n v10 = 0LL;\nLABEL_3:\n v11 = 0;\n if ((int)v10 <= 0) goto LABEL_7;\n while (1) {\n v12 = v7;\n v11 = 0;\n while (*v9 != *v12) {\n ++v11;\n ++v12;\n if (v11 == (uint32_t)v10) goto LABEL_12;\n }\n LABEL_7:\n if ((uint32_t)v10 != v11) {\n if (++v9 == v8) {\n v13 = malloc(4LL * (int)v10);\n *a3 = v13;\n v14 = v13;\n if ((int)v10 > 0) goto LABEL_10;\n goto LABEL_11;\n }\n goto LABEL_3;\n }\n LABEL_12:\n v15 = *v9++;\n v16 = v10 + 1;\n v7[v10] = v15;\n if (v8 == v9) break;\n v10 = v16;\n }\n LODWORD(v10) = v10 + 1;\n v17 = malloc(4LL * v16);\n *a3 = v17;\n v14 = v17;\nLABEL_10:\n memcpy(v14, v7, 4LL * (unsigned int)v10);\nLABEL_11:\n *a4 = v10;\n free(v7);\n}", + "ida_pseudo_norm": "void func0(int *a1, int a2, void **a3, uint32_t *a4) {\n uint32_t *v7;\n int *v8;\n int *v9;\n long long v10;\n int v11;\n uint32_t *v12;\n void *v13;\n void *v14;\n int v15;\n int v16;\n void *v17;\n v7 = malloc(4LL * a2);\n if (a2 <= 0) {\n LODWORD(v10) = 0;\n *a3 = malloc(0LL);\n goto LABEL_11;\n }\n v8 = &a1[a2];\n v9 = a1;\n v10 = 0LL;\nLABEL_3:\n v11 = 0;\n if ((int)v10 <= 0) goto LABEL_7;\n while (1) {\n v12 = v7;\n v11 = 0;\n while (*v9 != *v12) {\n ++v11;\n ++v12;\n if (v11 == (uint32_t)v10) goto LABEL_12;\n }\n LABEL_7:\n if ((uint32_t)v10 != v11) {\n if (++v9 == v8) {\n v13 = malloc(4LL * (int)v10);\n *a3 = v13;\n v14 = v13;\n if ((int)v10 > 0) goto LABEL_10;\n goto LABEL_11;\n }\n goto LABEL_3;\n }\n LABEL_12:\n v15 = *v9++;\n v16 = v10 + 1;\n v7[v10] = v15;\n if (v8 == v9) break;\n v10 = v16;\n }\n LODWORD(v10) = v10 + 1;\n v17 = malloc(4LL * v16);\n *a3 = v17;\n v14 = v17;\nLABEL_10:\n memcpy(v14, v7, 4LL * (unsigned int)v10);\nLABEL_11:\n *a4 = v10;\n free(v7);\n}" + }, + { + "index": 194, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int num = n;\n int dec_value = 0;\n int base = 1;\n int temp = num;\n while (temp) {\n int last_digit = temp % 10;\n temp = temp / 10;\n dec_value += last_digit * base;\n base = base * 8;\n }\n return dec_value;\n}", + "test": "int main() {\n\n assert(func0(25) == 21);\n\n assert(func0(30) == 24);\n\n assert(func0(40) == 32);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x24(%rbp)\nmov -0x24(%rbp),%eax\nmov %eax,-0x8(%rbp)\nmovl $0x0,-0x14(%rbp)\nmovl $0x1,-0x10(%rbp)\nmov -0x8(%rbp),%eax\nmov %eax,-0xc(%rbp)\njmp 11c9 \nmov -0xc(%rbp),%edx\nmovslq %edx,%rax\nimul $0x66666667,%rax,%rax\nshr $0x20,%rax\nmov %eax,%ecx\nsar $0x2,%ecx\nmov %edx,%eax\nsar $0x1f,%eax\nsub %eax,%ecx\nmov %ecx,%eax\nshl $0x2,%eax\nadd %ecx,%eax\nadd %eax,%eax\nsub %eax,%edx\nmov %edx,%eax\nmov %eax,-0x4(%rbp)\nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nimul $0x66666667,%rdx,%rdx\nshr $0x20,%rdx\nsar $0x2,%edx\nsar $0x1f,%eax\nsub %eax,%edx\nmov %edx,%eax\nmov %eax,-0xc(%rbp)\nmov -0x4(%rbp),%eax\nimul -0x10(%rbp),%eax\nadd %eax,-0x14(%rbp)\nshll $0x3,-0x10(%rbp)\ncmpl $0x0,-0xc(%rbp)\njne 1170 \nmov -0x14(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_24], edi\nmov eax, [rbp+var_24]\nmov [rbp+var_8], eax\nmov [rbp+var_14], 0\nmov [rbp+var_10], 1\nmov eax, [rbp+var_8]\nmov [rbp+var_C], eax\njmp short loc_11C7\nloc_1170:\nmov edx, [rbp+var_C]\nmovsxd rax, edx\nimul rax, 66666667h\nshr rax, 20h\nmov ecx, eax\nsar ecx, 2\nmov eax, edx\nsar eax, 1Fh\nsub ecx, eax\nmov eax, ecx\nshl eax, 2\nadd eax, ecx\nadd eax, eax\nsub edx, eax\nmov [rbp+var_4], edx\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_C], eax\nmov eax, [rbp+var_4]\nimul eax, [rbp+var_10]\nadd [rbp+var_14], eax\nshl [rbp+var_10], 3\nloc_11C7:\ncmp [rbp+var_C], 0\njnz short loc_1170\nmov eax, [rbp+var_14]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v2; // [rsp+10h] [rbp-14h]\n int v3; // [rsp+14h] [rbp-10h]\n int v5; // [rsp+20h] [rbp-4h]\n\n v2 = 0;\n v3 = 1;\n while ( a1 )\n {\n v5 = a1 % 10;\n a1 /= 10;\n v2 += v3 * v5;\n v3 *= 8;\n }\n return v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_24], edi\nmov eax, [rbp+var_24]\nmov [rbp+var_8], eax\nmov [rbp+var_14], 0\nmov [rbp+var_10], 1\nmov eax, [rbp+var_8]\nmov [rbp+var_C], eax\njmp short loc_11C7\nloc_1170:\nmov edx, [rbp+var_C]\nmovsxd rax, edx\nimul rax, 66666667h\nshr rax, 20h\nmov ecx, eax\nsar ecx, 2\nmov eax, edx\nsar eax, 1Fh\nsub ecx, eax\nmov eax, ecx\nshl eax, 2\nadd eax, ecx\nadd eax, eax\nsub edx, eax\nmov [rbp+var_4], edx\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_C], eax\nmov eax, [rbp+var_4]\nimul eax, [rbp+var_10]\nadd [rbp+var_14], eax\nshl [rbp+var_10], 3\nloc_11C7:\ncmp [rbp+var_C], 0\njnz short loc_1170\nmov eax, [rbp+var_14]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n unsigned int v2; // [rsp+10h] [rbp-14h]\n int v3; // [rsp+14h] [rbp-10h]\n int v5; // [rsp+20h] [rbp-4h]\n\n v2 = 0;\n v3 = 1;\n while ( a1 )\n {\n v5 = a1 % 10;\n a1 /= 10;\n v2 += v3 * v5;\n v3 *= 8;\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n unsigned int v2;\n int v3;\n int v5;\n v2 = 0;\n v3 = 1;\n while (a1) {\n v5 = a1 % 10;\n a1 /= 10;\n v2 += v3 * v5;\n v3 *= 8;\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v2;\n int v3;\n int v5;\n v2 = 0;\n v3 = 1;\n while (a1) {\n v5 = a1 % 10;\n a1 /= 10;\n v2 += v3 * v5;\n v3 *= 8;\n }\n return v2;\n}" + }, + { + "index": 194, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int num = n;\n int dec_value = 0;\n int base = 1;\n int temp = num;\n while (temp) {\n int last_digit = temp % 10;\n temp = temp / 10;\n dec_value += last_digit * base;\n base = base * 8;\n }\n return dec_value;\n}", + "test": "int main() {\n\n assert(func0(25) == 21);\n\n assert(func0(30) == 24);\n\n assert(func0(40) == 32);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\nje 118c \nmov $0x1,%edx\nmov $0x0,%esi\nmovslq %edi,%rax\nimul $0x66666667,%rax,%rax\nsar $0x22,%rax\nmov %edi,%ecx\nsar $0x1f,%ecx\nsub %ecx,%eax\nmov %eax,%ecx\nlea (%rax,%rax,4),%eax\nadd %eax,%eax\nsub %eax,%edi\nmov %edi,%eax\nmov %ecx,%edi\nimul %edx,%eax\nadd %eax,%esi\nshl $0x3,%edx\ntest %ecx,%ecx\njne 115b \nmov %esi,%eax\nretq\nmov %edi,%esi\njmp 1189 \n", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njz short loc_118F\nmov ecx, 1\nmov r8d, 0\nloc_115C:\nmovsxd rax, edi\nimul rax, 66666667h\nsar rax, 22h\nmov edx, edi\nsar edx, 1Fh\nsub eax, edx\nmov esi, eax\nlea edx, [rax+rax*4]\nadd edx, edx\nmov eax, edi\nsub eax, edx\nmov edi, esi\nimul eax, ecx\nadd r8d, eax\nshl ecx, 3\ntest esi, esi\njnz short loc_115C\nloc_118B:\nmov eax, r8d\nretn\nloc_118F:\nmov r8d, edi\njmp short loc_118B", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // ecx\n unsigned int v2; // r8d\n int v3; // eax\n\n if ( a1 )\n {\n v1 = 1;\n v2 = 0;\n do\n {\n v3 = a1 % 10;\n a1 /= 10;\n v2 += v1 * v3;\n v1 *= 8;\n }\n while ( a1 );\n }\n else\n {\n return 0;\n }\n return v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ntest edi, edi\njz short loc_118F\nmov ecx, 1\nmov r8d, 0\nloc_115C:\nmovsxd rax, edi\nimul rax, 66666667h\nsar rax, 22h\nmov edx, edi\nsar edx, 1Fh\nsub eax, edx\nmov esi, eax\nlea edx, [rax+rax*4]\nadd edx, edx\nmov eax, edi\nsub eax, edx\nmov edi, esi\nimul eax, ecx\nadd r8d, eax\nshl ecx, 3\ntest esi, esi\njnz short loc_115C\nloc_118B:\nmov eax, r8d\nretn\nloc_118F:\nmov r8d, edi\njmp short loc_118B", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v1; // ecx\n unsigned int v2; // r8d\n int v3; // eax\n\n if ( a1 )\n {\n v1 = 1;\n v2 = 0;\n do\n {\n v3 = a1 % 10;\n a1 /= 10;\n v2 += v1 * v3;\n v1 *= 8;\n }\n while ( a1 );\n }\n else\n {\n return 0;\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v1;\n unsigned int v2;\n int v3;\n if (a1) {\n v1 = 1;\n v2 = 0;\n do {\n v3 = a1 % 10;\n a1 /= 10;\n v2 += v1 * v3;\n v1 *= 8;\n } while (a1);\n } else {\n return 0;\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n unsigned int v2;\n int v3;\n if (a1) {\n v1 = 1;\n v2 = 0;\n do {\n v3 = a1 % 10;\n a1 /= 10;\n v2 += v1 * v3;\n v1 *= 8;\n } while (a1);\n } else {\n return 0;\n }\n return v2;\n}" + }, + { + "index": 195, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int x, int n) {\n int low = 0;\n int high = n - 1;\n int res = -1;\n while (low <= high) {\n int mid = (low + high) / 2;\n if (arr[mid] > x) {\n high = mid - 1;\n } else if (arr[mid] < x) {\n low = mid + 1;\n } else {\n res = mid;\n high = mid - 1;\n }\n }\n return res;\n}", + "test": "int main() {\n\n int arr1[] = {1,2,3,4,5,6,6};\n\n int arr2[] = {1,2,2,2,3,2,2,4,2};\n\n int arr3[] = {1,2,3};\n\n \n\n assert(func0(arr1, 6, 7) == 5);\n\n assert(func0(arr2, 2, 9) == 1);\n\n assert(func0(arr3, 1, 3) == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmovl $0x0,-0x10(%rbp)\nmov -0x20(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0xc(%rbp)\nmovl $0xffffffff,-0x8(%rbp)\njmp 1203 \nmov -0x10(%rbp),%edx\nmov -0xc(%rbp),%eax\nadd %edx,%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x1c(%rbp)\njge 11ce \nmov -0x4(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0xc(%rbp)\njmp 1203 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x1c(%rbp)\njle 11f4 \nmov -0x4(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x10(%rbp)\njmp 1203 \nmov -0x4(%rbp),%eax\nmov %eax,-0x8(%rbp)\nmov -0x4(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0xc(%rbp)\nmov -0x10(%rbp),%eax\ncmp -0xc(%rbp),%eax\njle 1194 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_10], 0\nmov eax, [rbp+var_20]\nsub eax, 1\nmov [rbp+var_C], eax\nmov [rbp+var_8], 0FFFFFFFFh\njmp short loc_1203\nloc_1194:\nmov edx, [rbp+var_10]\nmov eax, [rbp+var_C]\nadd eax, edx\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_1C], eax\njge short loc_11CE\nmov eax, [rbp+var_4]\nsub eax, 1\nmov [rbp+var_C], eax\njmp short loc_1203\nloc_11CE:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_1C], eax\njle short loc_11F4\nmov eax, [rbp+var_4]\nadd eax, 1\nmov [rbp+var_10], eax\njmp short loc_1203\nloc_11F4:\nmov eax, [rbp+var_4]\nmov [rbp+var_8], eax\nmov eax, [rbp+var_4]\nsub eax, 1\nmov [rbp+var_C], eax\nloc_1203:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_C]\njle short loc_1194\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n int v4; // [rsp+10h] [rbp-10h]\n int v5; // [rsp+14h] [rbp-Ch]\n unsigned int v6; // [rsp+18h] [rbp-8h]\n int v7; // [rsp+1Ch] [rbp-4h]\n\n v4 = 0;\n v5 = a3 - 1;\n v6 = -1;\n while ( v4 <= v5 )\n {\n v7 = (v4 + v5) / 2;\n if ( a2 >= *(_DWORD *)(4LL * v7 + a1) )\n {\n if ( a2 <= *(_DWORD *)(4LL * v7 + a1) )\n {\n v6 = (v4 + v5) / 2;\n v5 = v7 - 1;\n }\n else\n {\n v4 = v7 + 1;\n }\n }\n else\n {\n v5 = v7 - 1;\n }\n }\n return v6;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_10], 0\nmov eax, [rbp+var_20]\nsub eax, 1\nmov [rbp+var_C], eax\nmov [rbp+var_8], 0FFFFFFFFh\njmp short loc_1203\nloc_1194:\nmov edx, [rbp+var_10]\nmov eax, [rbp+var_C]\nadd eax, edx\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_1C], eax\njge short loc_11CE\nmov eax, [rbp+var_4]\nsub eax, 1\nmov [rbp+var_C], eax\njmp short loc_1203\nloc_11CE:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_1C], eax\njle short loc_11F4\nmov eax, [rbp+var_4]\nadd eax, 1\nmov [rbp+var_10], eax\njmp short loc_1203\nloc_11F4:\nmov eax, [rbp+var_4]\nmov [rbp+var_8], eax\nmov eax, [rbp+var_4]\nsub eax, 1\nmov [rbp+var_C], eax\nloc_1203:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_C]\njle short loc_1194\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n int v4; // [rsp+10h] [rbp-10h]\n int v5; // [rsp+14h] [rbp-Ch]\n unsigned int v6; // [rsp+18h] [rbp-8h]\n int v7; // [rsp+1Ch] [rbp-4h]\n\n v4 = 0;\n v5 = a3 - 1;\n v6 = -1;\n while ( v4 <= v5 )\n {\n v7 = (v4 + v5) / 2;\n if ( a2 >= *(_DWORD *)(4LL * v7 + a1) )\n {\n if ( a2 <= *(_DWORD *)(4LL * v7 + a1) )\n {\n v6 = (v4 + v5) / 2;\n v5 = v7 - 1;\n }\n else\n {\n v4 = v7 + 1;\n }\n }\n else\n {\n v5 = v7 - 1;\n }\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n int v4;\n int v5;\n unsigned int v6;\n int v7;\n v4 = 0;\n v5 = a3 - 1;\n v6 = -1;\n while (v4 <= v5) {\n v7 = (v4 + v5) / 2;\n if (a2 >= *(uint32_t *)(4LL * v7 + a1)) {\n if (a2 <= *(uint32_t *)(4LL * v7 + a1)) {\n v6 = (v4 + v5) / 2;\n v5 = v7 - 1;\n } else {\n v4 = v7 + 1;\n }\n } else {\n v5 = v7 - 1;\n }\n }\n return v6;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n int v4;\n int v5;\n unsigned int v6;\n int v7;\n v4 = 0;\n v5 = a3 - 1;\n v6 = -1;\n while (v4 <= v5) {\n v7 = (v4 + v5) / 2;\n if (a2 >= *(uint32_t *)(4LL * v7 + a1)) {\n if (a2 <= *(uint32_t *)(4LL * v7 + a1)) {\n v6 = (v4 + v5) / 2;\n v5 = v7 - 1;\n } else {\n v4 = v7 + 1;\n }\n } else {\n v5 = v7 - 1;\n }\n }\n return v6;\n}" + }, + { + "index": 195, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int x, int n) {\n int low = 0;\n int high = n - 1;\n int res = -1;\n while (low <= high) {\n int mid = (low + high) / 2;\n if (arr[mid] > x) {\n high = mid - 1;\n } else if (arr[mid] < x) {\n low = mid + 1;\n } else {\n res = mid;\n high = mid - 1;\n }\n }\n return res;\n}", + "test": "int main() {\n\n int arr1[] = {1,2,3,4,5,6,6};\n\n int arr2[] = {1,2,2,2,3,2,2,4,2};\n\n int arr3[] = {1,2,3};\n\n \n\n assert(func0(arr1, 6, 7) == 5);\n\n assert(func0(arr2, 2, 9) == 1);\n\n assert(func0(arr3, 1, 3) == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x1,%edx\njs 11af \nmov $0xffffffff,%r9d\nmov $0x0,%r8d\njmp 118b \njge 11a7 \nlea 0x1(%rax),%r8d\ncmp %edx,%r8d\njg 11b5 \nlea (%r8,%rdx,1),%ecx\nmov %ecx,%eax\nshr $0x1f,%eax\nadd %ecx,%eax\nsar %eax\nmovslq %eax,%rcx\nmov (%rdi,%rcx,4),%ecx\ncmp %esi,%ecx\njle 1180 \nlea -0x1(%rax),%edx\njmp 1186 \nlea -0x1(%rax),%edx\nmov %eax,%r9d\njmp 1186 \nmov $0xffffffff,%r9d\nmov %r9d,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nsub edx, 1\njs short loc_11AF\nmov r9d, 0FFFFFFFFh\nmov r8d, 0\njmp short loc_118B\nloc_1180:\njge short loc_11A7\nlea r8d, [rax+1]\nloc_1186:\ncmp r8d, edx\njg short loc_11B5\nloc_118B:\nlea ecx, [r8+rdx]\nmov eax, ecx\nshr eax, 1Fh\nadd eax, ecx\nsar eax, 1\nmovsxd rcx, eax\nmov ecx, [rdi+rcx*4]\ncmp ecx, esi\njle short loc_1180\nlea edx, [rax-1]\njmp short loc_1186\nloc_11A7:\nlea edx, [rax-1]\nmov r9d, eax\njmp short loc_1186\nloc_11AF:\nmov r9d, 0FFFFFFFFh\nloc_11B5:\nmov eax, r9d\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n int v3; // edx\n unsigned int v4; // r9d\n int v5; // r8d\n int v6; // eax\n int v7; // ecx\n\n v3 = a3 - 1;\n if ( v3 < 0 )\n {\n return (unsigned int)-1;\n }\n else\n {\n v4 = -1;\n v5 = 0;\n do\n {\n v6 = (v5 + v3) / 2;\n v7 = *(_DWORD *)(a1 + 4LL * v6);\n if ( v7 <= a2 )\n {\n if ( v7 >= a2 )\n {\n v3 = v6 - 1;\n v4 = v6;\n }\n else\n {\n v5 = v6 + 1;\n }\n }\n else\n {\n v3 = v6 - 1;\n }\n }\n while ( v5 <= v3 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nsub edx, 1\njs short loc_11AF\nmov r9d, 0FFFFFFFFh\nmov r8d, 0\njmp short loc_118B\nloc_1180:\njge short loc_11A7\nlea r8d, [rax+1]\nloc_1186:\ncmp r8d, edx\njg short loc_11B5\nloc_118B:\nlea ecx, [r8+rdx]\nmov eax, ecx\nshr eax, 1Fh\nadd eax, ecx\nsar eax, 1\nmovsxd rcx, eax\nmov ecx, [rdi+rcx*4]\ncmp ecx, esi\njle short loc_1180\nlea edx, [rax-1]\njmp short loc_1186\nloc_11A7:\nlea edx, [rax-1]\nmov r9d, eax\njmp short loc_1186\nloc_11AF:\nmov r9d, 0FFFFFFFFh\nloc_11B5:\nmov eax, r9d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n int v3; // edx\n unsigned int v4; // r9d\n int v5; // r8d\n int v6; // eax\n int v7; // ecx\n\n v3 = a3 - 1;\n if ( v3 < 0 )\n {\n return (unsigned int)-1;\n }\n else\n {\n v4 = -1;\n v5 = 0;\n do\n {\n v6 = (v5 + v3) / 2;\n v7 = *(_DWORD *)(a1 + 4LL * v6);\n if ( v7 <= a2 )\n {\n if ( v7 >= a2 )\n {\n v3 = v6 - 1;\n v4 = v6;\n }\n else\n {\n v5 = v6 + 1;\n }\n }\n else\n {\n v3 = v6 - 1;\n }\n }\n while ( v5 <= v3 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n int v3;\n unsigned int v4;\n int v5;\n int v6;\n int v7;\n v3 = a3 - 1;\n if (v3 < 0) {\n return (unsigned int)-1;\n } else {\n v4 = -1;\n v5 = 0;\n do {\n v6 = (v5 + v3) / 2;\n v7 = *(uint32_t *)(a1 + 4LL * v6);\n if (v7 <= a2) {\n if (v7 >= a2) {\n v3 = v6 - 1;\n v4 = v6;\n } else {\n v5 = v6 + 1;\n }\n } else {\n v3 = v6 - 1;\n }\n } while (v5 <= v3);\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n int v3;\n unsigned int v4;\n int v5;\n int v6;\n int v7;\n v3 = a3 - 1;\n if (v3 < 0) {\n return (unsigned int)-1;\n } else {\n v4 = -1;\n v5 = 0;\n do {\n v6 = (v5 + v3) / 2;\n v7 = *(uint32_t *)(a1 + 4LL * v6);\n if (v7 <= a2) {\n if (v7 >= a2) {\n v3 = v6 - 1;\n v4 = v6;\n } else {\n v5 = v6 + 1;\n }\n } else {\n v3 = v6 - 1;\n }\n } while (v5 <= v3);\n }\n return v4;\n}" + }, + { + "index": 195, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int x, int n) {\n int low = 0;\n int high = n - 1;\n int res = -1;\n while (low <= high) {\n int mid = (low + high) / 2;\n if (arr[mid] > x) {\n high = mid - 1;\n } else if (arr[mid] < x) {\n low = mid + 1;\n } else {\n res = mid;\n high = mid - 1;\n }\n }\n return res;\n}", + "test": "int main() {\n\n int arr1[] = {1,2,3,4,5,6,6};\n\n int arr2[] = {1,2,2,2,3,2,2,4,2};\n\n int arr3[] = {1,2,3};\n\n \n\n assert(func0(arr1, 6, 7) == 5);\n\n assert(func0(arr2, 2, 9) == 1);\n\n assert(func0(arr3, 1, 3) == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov $0xffffffff,%r9d\nsub $0x1,%edx\njs 1396 \nxor %ecx,%ecx\njmp 137f \nnopl 0x0(%rax,%rax,1)\nlea -0x1(%rax),%edx\ncmp %ecx,%edx\njl 1396 \nlea (%rdx,%rcx,1),%eax\nsar %eax\nmovslq %eax,%r8\ncmp %esi,(%rdi,%r8,4)\njg 1378 \njge 13a0 \nlea 0x1(%rax),%ecx\ncmp %ecx,%edx\njge 137f \nmov %r9d,%eax\nretq\nnopw 0x0(%rax,%rax,1)\nlea -0x1(%rax),%edx\nmov %eax,%r9d\njmp 137b \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmov r9d, 0FFFFFFFFh\nsub edx, 1\njs short loc_12E0\nxor r8d, r8d\njmp short loc_12C0\nloc_12B8:\nlea edx, [rax-1]\nloc_12BB:\ncmp r8d, edx\njg short loc_12E0\nloc_12C0:\nlea ecx, [r8+rdx]\nmov eax, ecx\nshr eax, 1Fh\nadd eax, ecx\nsar eax, 1\nmovsxd rcx, eax\ncmp esi, [rdi+rcx*4]\njl short loc_12B8\njle short loc_12E8\nlea r8d, [rax+1]\ncmp r8d, edx\njle short loc_12C0\nloc_12E0:\nmov eax, r9d\nretn\nloc_12E8:\nlea edx, [rax-1]\nmov r9d, eax\njmp short loc_12BB", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n unsigned int v3; // r9d\n int v4; // edx\n int v5; // r8d\n int v6; // eax\n\n v3 = -1;\n v4 = a3 - 1;\n if ( v4 >= 0 )\n {\n v5 = 0;\n do\n {\n while ( 1 )\n {\n v6 = (v5 + v4) / 2;\n if ( a2 >= *(_DWORD *)(a1 + 4LL * v6) )\n break;\n v4 = v6 - 1;\nLABEL_4:\n if ( v5 > v4 )\n return v3;\n }\n if ( a2 <= *(_DWORD *)(a1 + 4LL * v6) )\n {\n v4 = v6 - 1;\n v3 = v6;\n goto LABEL_4;\n }\n v5 = v6 + 1;\n }\n while ( v6 + 1 <= v4 );\n }\n return v3;\n}", + "ida_strip_asm": "sub_12A0:\nendbr64\nmov r9d, 0FFFFFFFFh\nsub edx, 1\njs short loc_12E0\nxor r8d, r8d\njmp short loc_12C0\nloc_12B8:\nlea edx, [rax-1]\nloc_12BB:\ncmp r8d, edx\njg short loc_12E0\nloc_12C0:\nlea ecx, [r8+rdx]\nmov eax, ecx\nshr eax, 1Fh\nadd eax, ecx\nsar eax, 1\nmovsxd rcx, eax\ncmp esi, [rdi+rcx*4]\njl short loc_12B8\njle short loc_12E8\nlea r8d, [rax+1]\ncmp r8d, edx\njle short loc_12C0\nloc_12E0:\nmov eax, r9d\nretn\nloc_12E8:\nlea edx, [rax-1]\nmov r9d, eax\njmp short loc_12BB", + "ida_strip_pseudo": "__int64 __fastcall sub_12A0(__int64 a1, int a2, int a3)\n{\n unsigned int v3; // r9d\n int v4; // edx\n int v5; // r8d\n int v6; // eax\n\n v3 = -1;\n v4 = a3 - 1;\n if ( v4 >= 0 )\n {\n v5 = 0;\n do\n {\n while ( 1 )\n {\n v6 = (v5 + v4) / 2;\n if ( a2 >= *(_DWORD *)(a1 + 4LL * v6) )\n break;\n v4 = v6 - 1;\nLABEL_4:\n if ( v5 > v4 )\n return v3;\n }\n if ( a2 <= *(_DWORD *)(a1 + 4LL * v6) )\n {\n v4 = v6 - 1;\n v3 = v6;\n goto LABEL_4;\n }\n v5 = v6 + 1;\n }\n while ( v6 + 1 <= v4 );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12A0(long long a1, int a2, int a3) {\n unsigned int v3;\n int v4;\n int v5;\n int v6;\n v3 = -1;\n v4 = a3 - 1;\n if (v4 >= 0) {\n v5 = 0;\n do {\n while (1) {\n v6 = (v5 + v4) / 2;\n if (a2 >= *(uint32_t *)(a1 + 4LL * v6)) break;\n v4 = v6 - 1;\n LABEL_4:\n if (v5 > v4) return v3;\n }\n if (a2 <= *(uint32_t *)(a1 + 4LL * v6)) {\n v4 = v6 - 1;\n v3 = v6;\n goto LABEL_4;\n }\n v5 = v6 + 1;\n } while (v6 + 1 <= v4);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n unsigned int v3;\n int v4;\n int v5;\n int v6;\n v3 = -1;\n v4 = a3 - 1;\n if (v4 >= 0) {\n v5 = 0;\n do {\n while (1) {\n v6 = (v5 + v4) / 2;\n if (a2 >= *(uint32_t *)(a1 + 4LL * v6)) break;\n v4 = v6 - 1;\n LABEL_4:\n if (v5 > v4) return v3;\n }\n if (a2 <= *(uint32_t *)(a1 + 4LL * v6)) {\n v4 = v6 - 1;\n v3 = v6;\n goto LABEL_4;\n }\n v5 = v6 + 1;\n } while (v6 + 1 <= v4);\n }\n return v3;\n}" + }, + { + "index": 196, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\nstruct Tuple {\n\n int *elements;\n\n int size;\n\n};\n\n\n\nstruct TupleList {\n\n struct Tuple *tuples;\n\n int size;\n\n};\n\n\n\nstruct TupleList remove_tuples(struct TupleList test_list, int K) {\n\n struct TupleList res;\n\n res.tuples = malloc(test_list.size * sizeof(struct Tuple));\n\n res.size = 0;\n\n for (int i = 0; i < test_list.size; i++) {\n\n if (test_list.tuples[i].size != K) {\n\n res.tuples[res.size++] = test_list.tuples[i];\n\n }\n\n }\n\n return res;\n\n}\n\n\n\nint compare_tuples(struct Tuple t1, struct Tuple t2) {\n\n if (t1.size != t2.size) return 0;\n\n for (int i = 0; i < t1.size; i++) {\n\n if (t1.elements[i] != t2.elements[i]) {\n\n return 0;\n\n }\n\n }\n\n return 1;\n\n}\n\n\n\n", + "func": "int func0(struct TupleList l1, struct TupleList l2) {\n if (l1.size != l2.size) return 0;\n for (int i = 0; i < l1.size; i++) {\n if (!compare_tuples(l1.tuples[i], l2.tuples[i])) return 0;\n }\n return 1;\n}", + "test": "int main() {\n\n int tuple1[] = {4, 5};\n\n int tuple2[] = {4};\n\n int tuple3[] = {8, 6, 7};\n\n int tuple4[] = {1};\n\n int tuple5[] = {3, 4, 6, 7};\n\n struct Tuple tuples1[] = {{tuple1, 2}, {tuple2, 1}, {tuple3, 3}, {tuple4, 1}, {tuple5, 4}};\n\n struct TupleList test_list1 = {tuples1, 5};\n\n struct Tuple expected1[] = {{tuple1, 2}, {tuple3, 3}, {tuple5, 4}};\n\n struct TupleList expected_list1 = {expected1, 3};\n\n struct TupleList result1 = remove_tuples(test_list1, 1);\n\n \n\n int tuple6[] = {4, 5};\n\n int tuple7[] = {4, 5};\n\n int tuple8[] = {6, 7};\n\n int tuple9[] = {1, 2, 3};\n\n int tuple10[] = {3, 4, 6, 7};\n\n struct Tuple tuples2[] = {{tuple6, 2}, {tuple7, 2}, {tuple8, 2}, {tuple9, 3}, {tuple10, 4}};\n\n struct TupleList test_list2 = {tuples2, 5};\n\n struct Tuple expected2[] = {{tuple9, 3}, {tuple10, 4}};\n\n struct TupleList expected_list2 = {expected2, 2};\n\n struct TupleList result2 = remove_tuples(test_list2, 2);\n\n\n\n int tuple11[] = {1, 4, 4};\n\n int tuple12[] = {4, 3};\n\n int tuple13[] = {8, 6, 7};\n\n int tuple14[] = {1};\n\n int tuple15[] = {3, 6, 7};\n\n struct Tuple tuples3[] = {{tuple11, 3}, {tuple12, 2}, {tuple13, 3}, {tuple14, 1}, {tuple15, 3}};\n\n struct TupleList test_list3 = {tuples3, 5};\n\n struct Tuple expected3[] = {{tuple12, 2}, {tuple14, 1}};\n\n struct TupleList expected_list3 = {expected3, 2};\n\n struct TupleList result3 = remove_tuples(test_list3, 3);\n\n\n\n assert(func0(result1, expected_list1));\n\n assert(func0(result2, expected_list2));\n\n assert(func0(result3, expected_list3));\n\n\n\n printf(\"All tests passed!\\n\");\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rsi,%rax\nmov %rdi,%r8\nmov %r8,%rsi\nmov %r9,%rdi\nmov %rax,%rdi\nmov %rsi,-0x20(%rbp)\nmov %rdi,-0x18(%rbp)\nmov %rdx,-0x30(%rbp)\nmov %rcx,-0x28(%rbp)\nmov -0x18(%rbp),%edx\nmov -0x28(%rbp),%eax\ncmp %eax,%edx\nje 131a \nmov $0x0,%eax\njmp 137a \nmovl $0x0,-0x4(%rbp)\njmp 136d \nmov -0x30(%rbp),%rax\nmov -0x4(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x4,%rdx\nadd %rdx,%rax\nmov -0x20(%rbp),%rdx\nmov -0x4(%rbp),%ecx\nmovslq %ecx,%rcx\nshl $0x4,%rcx\nadd %rdx,%rcx\nmov 0x8(%rax),%rdx\nmov (%rax),%rax\nmov (%rcx),%rdi\nmov 0x8(%rcx),%rsi\nmov %rdx,%rcx\nmov %rax,%rdx\ncallq 1259 \ntest %eax,%eax\njne 1369 \nmov $0x0,%eax\njmp 137a \naddl $0x1,-0x4(%rbp)\nmov -0x18(%rbp),%eax\ncmp %eax,-0x4(%rbp)\njl 1323 \nmov $0x1,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov rax, rdi\nmov r8, rsi\nmov rsi, rax\nmov rdi, rdx\nmov rdi, r8\nmov [rbp+var_20], rsi\nmov [rbp+var_18], rdi\nmov [rbp+var_30], rdx\nmov [rbp+var_28], rcx\nmov edx, dword ptr [rbp+var_18]\nmov eax, dword ptr [rbp+var_28]\ncmp edx, eax\njz short loc_131C\nmov eax, 0\njmp short locret_137C\nloc_131C:\nmov [rbp+var_4], 0\njmp short loc_136F\nloc_1325:\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nshl rdx, 4\nadd rax, rdx\nmov rdx, [rbp+var_20]\nmov ecx, [rbp+var_4]\nmovsxd rcx, ecx\nshl rcx, 4\nadd rcx, rdx\nmov rdx, [rax+8]\nmov rax, [rax]\nmov rdi, [rcx]\nmov rsi, [rcx+8]\nmov rcx, rdx\nmov rdx, rax\ncall compare_tuples\ntest eax, eax\njnz short loc_136B\nmov eax, 0\njmp short locret_137C\nloc_136B:\nadd [rbp+var_4], 1\nloc_136F:\nmov eax, dword ptr [rbp+var_18]\ncmp [rbp+var_4], eax\njl short loc_1325\nmov eax, 1\nlocret_137C:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3, int a4)\n{\n int i; // [rsp+2Ch] [rbp-4h]\n\n if ( a2 != a4 )\n return 0LL;\n for ( i = 0; i < a2; ++i )\n {\n if ( !(unsigned int)compare_tuples(\n *(_QWORD *)(a1 + 16LL * i),\n *(_QWORD *)(a1 + 16LL * i + 8),\n *(_QWORD *)(16LL * i + a3),\n *(_QWORD *)(16LL * i + a3 + 8)) )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov rax, rdi\nmov r8, rsi\nmov rsi, rax\nmov rdi, rdx\nmov rdi, r8\nmov [rbp+var_20], rsi\nmov [rbp+var_18], rdi\nmov [rbp+var_30], rdx\nmov [rbp+var_28], rcx\nmov edx, dword ptr [rbp+var_18]\nmov eax, dword ptr [rbp+var_28]\ncmp edx, eax\njz short loc_131C\nmov eax, 0\njmp short locret_137C\nloc_131C:\nmov [rbp+var_4], 0\njmp short loc_136F\nloc_1325:\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nshl rdx, 4\nadd rax, rdx\nmov rdx, [rbp+var_20]\nmov ecx, [rbp+var_4]\nmovsxd rcx, ecx\nshl rcx, 4\nadd rcx, rdx\nmov rdx, [rax+8]\nmov rax, [rax]\nmov rdi, [rcx]\nmov rsi, [rcx+8]\nmov rcx, rdx\nmov rdx, rax\ncall sub_125B\ntest eax, eax\njnz short loc_136B\nmov eax, 0\njmp short locret_137C\nloc_136B:\nadd [rbp+var_4], 1\nloc_136F:\nmov eax, dword ptr [rbp+var_18]\ncmp [rbp+var_4], eax\njl short loc_1325\nmov eax, 1\nlocret_137C:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12E0(__int64 a1, int a2, __int64 a3, int a4)\n{\n int i; // [rsp+2Ch] [rbp-4h]\n\n if ( a2 != a4 )\n return 0LL;\n for ( i = 0; i < a2; ++i )\n {\n if ( !(unsigned int)sub_125B(\n *(_QWORD *)(a1 + 16LL * i),\n *(_QWORD *)(a1 + 16LL * i + 8),\n *(_QWORD *)(16LL * i + a3),\n *(_QWORD *)(16LL * i + a3 + 8)) )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12E0(long long a1, int a2, long long a3, int a4) {\n int i;\n if (a2 != a4) return 0LL;\n for (i = 0; i < a2; ++i) {\n if (!(unsigned int)sub_125B(\n *(uint64_t *)(a1 + 16LL * i), *(uint64_t *)(a1 + 16LL * i + 8),\n *(uint64_t *)(16LL * i + a3), *(uint64_t *)(16LL * i + a3 + 8)))\n return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3, int a4) {\n int i;\n if (a2 != a4) return 0LL;\n for (i = 0; i < a2; ++i) {\n if (!(unsigned int)compare_tuples(\n *(uint64_t *)(a1 + 16LL * i), *(uint64_t *)(a1 + 16LL * i + 8),\n *(uint64_t *)(16LL * i + a3), *(uint64_t *)(16LL * i + a3 + 8)))\n return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": 196, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\nstruct Tuple {\n\n int *elements;\n\n int size;\n\n};\n\n\n\nstruct TupleList {\n\n struct Tuple *tuples;\n\n int size;\n\n};\n\n\n\nstruct TupleList remove_tuples(struct TupleList test_list, int K) {\n\n struct TupleList res;\n\n res.tuples = malloc(test_list.size * sizeof(struct Tuple));\n\n res.size = 0;\n\n for (int i = 0; i < test_list.size; i++) {\n\n if (test_list.tuples[i].size != K) {\n\n res.tuples[res.size++] = test_list.tuples[i];\n\n }\n\n }\n\n return res;\n\n}\n\n\n\nint compare_tuples(struct Tuple t1, struct Tuple t2) {\n\n if (t1.size != t2.size) return 0;\n\n for (int i = 0; i < t1.size; i++) {\n\n if (t1.elements[i] != t2.elements[i]) {\n\n return 0;\n\n }\n\n }\n\n return 1;\n\n}\n\n\n\n", + "func": "int func0(struct TupleList l1, struct TupleList l2) {\n if (l1.size != l2.size) return 0;\n for (int i = 0; i < l1.size; i++) {\n if (!compare_tuples(l1.tuples[i], l2.tuples[i])) return 0;\n }\n return 1;\n}", + "test": "int main() {\n\n int tuple1[] = {4, 5};\n\n int tuple2[] = {4};\n\n int tuple3[] = {8, 6, 7};\n\n int tuple4[] = {1};\n\n int tuple5[] = {3, 4, 6, 7};\n\n struct Tuple tuples1[] = {{tuple1, 2}, {tuple2, 1}, {tuple3, 3}, {tuple4, 1}, {tuple5, 4}};\n\n struct TupleList test_list1 = {tuples1, 5};\n\n struct Tuple expected1[] = {{tuple1, 2}, {tuple3, 3}, {tuple5, 4}};\n\n struct TupleList expected_list1 = {expected1, 3};\n\n struct TupleList result1 = remove_tuples(test_list1, 1);\n\n \n\n int tuple6[] = {4, 5};\n\n int tuple7[] = {4, 5};\n\n int tuple8[] = {6, 7};\n\n int tuple9[] = {1, 2, 3};\n\n int tuple10[] = {3, 4, 6, 7};\n\n struct Tuple tuples2[] = {{tuple6, 2}, {tuple7, 2}, {tuple8, 2}, {tuple9, 3}, {tuple10, 4}};\n\n struct TupleList test_list2 = {tuples2, 5};\n\n struct Tuple expected2[] = {{tuple9, 3}, {tuple10, 4}};\n\n struct TupleList expected_list2 = {expected2, 2};\n\n struct TupleList result2 = remove_tuples(test_list2, 2);\n\n\n\n int tuple11[] = {1, 4, 4};\n\n int tuple12[] = {4, 3};\n\n int tuple13[] = {8, 6, 7};\n\n int tuple14[] = {1};\n\n int tuple15[] = {3, 6, 7};\n\n struct Tuple tuples3[] = {{tuple11, 3}, {tuple12, 2}, {tuple13, 3}, {tuple14, 1}, {tuple15, 3}};\n\n struct TupleList test_list3 = {tuples3, 5};\n\n struct Tuple expected3[] = {{tuple12, 2}, {tuple14, 1}};\n\n struct TupleList expected_list3 = {expected3, 2};\n\n struct TupleList result3 = remove_tuples(test_list3, 3);\n\n\n\n assert(func0(result1, expected_list1));\n\n assert(func0(result2, expected_list2));\n\n assert(func0(result3, expected_list3));\n\n\n\n printf(\"All tests passed!\\n\");\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x0,%eax\ncmp %ecx,%esi\njne 12aa \ntest %esi,%esi\njle 12a4 \npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nmov %rdx,%rbp\nlea -0x1(%rsi),%eax\nshl $0x4,%rax\nlea 0x10(%rdi,%rax,1),%r12\nmov (%rbx),%rdi\nmov 0x8(%rbx),%rsi\nmov 0x0(%rbp),%rdx\nmov 0x8(%rbp),%rcx\ncallq 120d \ntest %eax,%eax\nje 129f \nadd $0x10,%rbx\nadd $0x10,%rbp\ncmp %r12,%rbx\njne 1275 \nmov $0x1,%eax\npop %rbx\npop %rbp\npop %r12\nretq\nmov $0x1,%eax\nretq\nretq\n", + "ida_asm": "func0:\nendbr64\nmov eax, 0\ncmp esi, ecx\njnz short locret_12B5\ntest esi, esi\njle short loc_12AF\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nmov rbp, rdx\nmovsxd rsi, esi\nshl rsi, 4\nlea r12, [rsi+rdi]\nloc_1280:\nmov rdi, [rbx]\nmov rsi, [rbx+8]\nmov rdx, [rbp+0]\nmov rcx, [rbp+8]\ncall compare_tuples\ntest eax, eax\njz short loc_12AA\nadd rbx, 10h\nadd rbp, 10h\ncmp rbx, r12\njnz short loc_1280\nmov eax, 1\nloc_12AA:\npop rbx\npop rbp\npop r12\nretn\nloc_12AF:\nmov eax, 1\nretn\nlocret_12B5:\nretn", + "ida_pseudo": "__int64 __fastcall func0(_QWORD *a1, int a2, _QWORD *a3, int a4)\n{\n __int64 result; // rax\n _QWORD *v5; // rbx\n\n result = 0LL;\n if ( a2 == a4 )\n {\n if ( a2 <= 0 )\n {\n return 1LL;\n }\n else\n {\n v5 = a1;\n while ( 1 )\n {\n result = compare_tuples(*v5, v5[1], *a3, a3[1]);\n if ( !(_DWORD)result )\n break;\n v5 += 2;\n a3 += 2;\n if ( v5 == &a1[2 * a2] )\n return 1LL;\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_125A:\nendbr64\nmov eax, 0\ncmp esi, ecx\njnz short locret_12B5\ntest esi, esi\njle short loc_12AF\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nmov rbp, rdx\nmovsxd rsi, esi\nshl rsi, 4\nlea r12, [rsi+rdi]\nloc_1280:\nmov rdi, [rbx]\nmov rsi, [rbx+8]\nmov rdx, [rbp+0]\nmov rcx, [rbp+8]\ncall sub_1216\ntest eax, eax\njz short loc_12AA\nadd rbx, 10h\nadd rbp, 10h\ncmp rbx, r12\njnz short loc_1280\nmov eax, 1\nloc_12AA:\npop rbx\npop rbp\npop r12\nretn\nloc_12AF:\nmov eax, 1\nretn\nlocret_12B5:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_125A(_QWORD *a1, int a2, _QWORD *a3, int a4)\n{\n __int64 result; // rax\n _QWORD *v5; // rbx\n\n result = 0LL;\n if ( a2 == a4 )\n {\n if ( a2 <= 0 )\n {\n return 1LL;\n }\n else\n {\n v5 = a1;\n while ( 1 )\n {\n result = sub_1216(*v5, v5[1], *a3, a3[1]);\n if ( !(_DWORD)result )\n break;\n v5 += 2;\n a3 += 2;\n if ( v5 == &a1[2 * a2] )\n return 1LL;\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_125A(uint64_t *a1, int a2, uint64_t *a3, int a4) {\n long long result;\n uint64_t *v5;\n result = 0LL;\n if (a2 == a4) {\n if (a2 <= 0) {\n return 1LL;\n } else {\n v5 = a1;\n while (1) {\n result = sub_1216(*v5, v5[1], *a3, a3[1]);\n if (!(uint32_t)result) break;\n v5 += 2;\n a3 += 2;\n if (v5 == &a1[2 * a2]) return 1LL;\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(uint64_t *a1, int a2, uint64_t *a3, int a4) {\n long long result;\n uint64_t *v5;\n result = 0LL;\n if (a2 == a4) {\n if (a2 <= 0) {\n return 1LL;\n } else {\n v5 = a1;\n while (1) {\n result = compare_tuples(*v5, v5[1], *a3, a3[1]);\n if (!(uint32_t)result) break;\n v5 += 2;\n a3 += 2;\n if (v5 == &a1[2 * a2]) return 1LL;\n }\n }\n }\n return result;\n}" + }, + { + "index": 196, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\nstruct Tuple {\n\n int *elements;\n\n int size;\n\n};\n\n\n\nstruct TupleList {\n\n struct Tuple *tuples;\n\n int size;\n\n};\n\n\n\nstruct TupleList remove_tuples(struct TupleList test_list, int K) {\n\n struct TupleList res;\n\n res.tuples = malloc(test_list.size * sizeof(struct Tuple));\n\n res.size = 0;\n\n for (int i = 0; i < test_list.size; i++) {\n\n if (test_list.tuples[i].size != K) {\n\n res.tuples[res.size++] = test_list.tuples[i];\n\n }\n\n }\n\n return res;\n\n}\n\n\n\nint compare_tuples(struct Tuple t1, struct Tuple t2) {\n\n if (t1.size != t2.size) return 0;\n\n for (int i = 0; i < t1.size; i++) {\n\n if (t1.elements[i] != t2.elements[i]) {\n\n return 0;\n\n }\n\n }\n\n return 1;\n\n}\n\n\n\n", + "func": "int func0(struct TupleList l1, struct TupleList l2) {\n if (l1.size != l2.size) return 0;\n for (int i = 0; i < l1.size; i++) {\n if (!compare_tuples(l1.tuples[i], l2.tuples[i])) return 0;\n }\n return 1;\n}", + "test": "int main() {\n\n int tuple1[] = {4, 5};\n\n int tuple2[] = {4};\n\n int tuple3[] = {8, 6, 7};\n\n int tuple4[] = {1};\n\n int tuple5[] = {3, 4, 6, 7};\n\n struct Tuple tuples1[] = {{tuple1, 2}, {tuple2, 1}, {tuple3, 3}, {tuple4, 1}, {tuple5, 4}};\n\n struct TupleList test_list1 = {tuples1, 5};\n\n struct Tuple expected1[] = {{tuple1, 2}, {tuple3, 3}, {tuple5, 4}};\n\n struct TupleList expected_list1 = {expected1, 3};\n\n struct TupleList result1 = remove_tuples(test_list1, 1);\n\n \n\n int tuple6[] = {4, 5};\n\n int tuple7[] = {4, 5};\n\n int tuple8[] = {6, 7};\n\n int tuple9[] = {1, 2, 3};\n\n int tuple10[] = {3, 4, 6, 7};\n\n struct Tuple tuples2[] = {{tuple6, 2}, {tuple7, 2}, {tuple8, 2}, {tuple9, 3}, {tuple10, 4}};\n\n struct TupleList test_list2 = {tuples2, 5};\n\n struct Tuple expected2[] = {{tuple9, 3}, {tuple10, 4}};\n\n struct TupleList expected_list2 = {expected2, 2};\n\n struct TupleList result2 = remove_tuples(test_list2, 2);\n\n\n\n int tuple11[] = {1, 4, 4};\n\n int tuple12[] = {4, 3};\n\n int tuple13[] = {8, 6, 7};\n\n int tuple14[] = {1};\n\n int tuple15[] = {3, 6, 7};\n\n struct Tuple tuples3[] = {{tuple11, 3}, {tuple12, 2}, {tuple13, 3}, {tuple14, 1}, {tuple15, 3}};\n\n struct TupleList test_list3 = {tuples3, 5};\n\n struct Tuple expected3[] = {{tuple12, 2}, {tuple14, 1}};\n\n struct TupleList expected_list3 = {expected3, 2};\n\n struct TupleList result3 = remove_tuples(test_list3, 3);\n\n\n\n assert(func0(result1, expected_list1));\n\n assert(func0(result2, expected_list2));\n\n assert(func0(result3, expected_list3));\n\n\n\n printf(\"All tests passed!\\n\");\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nxor %eax,%eax\ncmp %ecx,%esi\njne 173e \ntest %esi,%esi\njle 1739 \nlea -0x1(%rsi),%eax\nxor %esi,%esi\nadd $0x1,%rax\nshl $0x4,%rax\nmov %rax,%r11\nmov 0x8(%rdi,%rsi,1),%eax\ncmp 0x8(%rdx,%rsi,1),%eax\njne 1726 \ntest %eax,%eax\njle 1730 \nlea -0x1(%rax),%r10d\nmov (%rdi,%rsi,1),%r9\nmov (%rdx,%rsi,1),%r8\nxor %eax,%eax\njmp 171c \nnopl 0x0(%rax)\nlea 0x1(%rax),%rcx\ncmp %rax,%r10\nje 1730 \nmov %rcx,%rax\nmov (%r8,%rax,4),%ecx\ncmp %ecx,(%r9,%rax,4)\nje 1710 \nxor %eax,%eax\nretq\nnopl 0x0(%rax)\nadd $0x10,%rsi\ncmp %r11,%rsi\njne 16ee \nmov $0x1,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov r10, rdi\ncmp esi, ecx\njnz short loc_172B\nmovsxd r11, esi\nxor ecx, ecx\nshl r11, 4\ntest esi, esi\njle short loc_1739\nnop dword ptr [rax+rax+00000000h]\nloc_16F0:\nmov rdi, [r10+rcx]\nmov r9d, [r10+rcx+8]\nmov r8, [rdx+rcx]\ncmp r9d, [rdx+rcx+8]\njnz short loc_172B\nmovsxd rsi, r9d\nxor eax, eax\nshl rsi, 2\ntest r9d, r9d\njg short loc_1721\njmp short loc_1730\nloc_1718:\nadd rax, 4\ncmp rsi, rax\njz short loc_1730\nloc_1721:\nmov r9d, [r8+rax]\ncmp [rdi+rax], r9d\njz short loc_1718\nloc_172B:\nxor eax, eax\nretn\nloc_1730:\nadd rcx, 10h\ncmp rcx, r11\njnz short loc_16F0\nloc_1739:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3, int a4)\n{\n __int64 v4; // rcx\n int v5; // r9d\n __int64 v6; // rax\n\n if ( a2 != a4 )\n return 0LL;\n v4 = 0LL;\n if ( a2 > 0 )\n {\n while ( 1 )\n {\n v5 = *(_DWORD *)(a1 + v4 + 8);\n if ( v5 != *(_DWORD *)(a3 + v4 + 8) )\n return 0LL;\n v6 = 0LL;\n if ( v5 > 0 )\n {\n while ( *(_DWORD *)(*(_QWORD *)(a1 + v4) + v6) == *(_DWORD *)(*(_QWORD *)(a3 + v4) + v6) )\n {\n v6 += 4LL;\n if ( 4LL * v5 == v6 )\n goto LABEL_9;\n }\n return 0LL;\n }\nLABEL_9:\n v4 += 16LL;\n if ( v4 == 16LL * a2 )\n return 1LL;\n }\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_16D0:\nendbr64\nmov r10, rdi\ncmp esi, ecx\njnz short loc_172B\nmovsxd r11, esi\nxor ecx, ecx\nshl r11, 4\ntest esi, esi\njle short loc_1739\nnop dword ptr [rax+rax+00000000h]\nloc_16F0:\nmov rdi, [r10+rcx]\nmov r9d, [r10+rcx+8]\nmov r8, [rdx+rcx]\ncmp r9d, [rdx+rcx+8]\njnz short loc_172B\nmovsxd rsi, r9d\nxor eax, eax\nshl rsi, 2\ntest r9d, r9d\njg short loc_1721\njmp short loc_1730\nloc_1718:\nadd rax, 4\ncmp rsi, rax\njz short loc_1730\nloc_1721:\nmov r9d, [r8+rax]\ncmp [rdi+rax], r9d\njz short loc_1718\nloc_172B:\nxor eax, eax\nretn\nloc_1730:\nadd rcx, 10h\ncmp rcx, r11\njnz short loc_16F0\nloc_1739:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_16D0(__int64 a1, int a2, __int64 a3, int a4)\n{\n __int64 v4; // rcx\n int v5; // r9d\n __int64 v6; // rax\n\n if ( a2 != a4 )\n return 0LL;\n v4 = 0LL;\n if ( a2 > 0 )\n {\n while ( 1 )\n {\n v5 = *(_DWORD *)(a1 + v4 + 8);\n if ( v5 != *(_DWORD *)(a3 + v4 + 8) )\n return 0LL;\n v6 = 0LL;\n if ( v5 > 0 )\n {\n while ( *(_DWORD *)(*(_QWORD *)(a1 + v4) + v6) == *(_DWORD *)(*(_QWORD *)(a3 + v4) + v6) )\n {\n v6 += 4LL;\n if ( 4LL * v5 == v6 )\n goto LABEL_9;\n }\n return 0LL;\n }\nLABEL_9:\n v4 += 16LL;\n if ( v4 == 16LL * a2 )\n return 1LL;\n }\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_16D0(long long a1, int a2, long long a3, int a4) {\n long long v4;\n int v5;\n long long v6;\n if (a2 != a4) return 0LL;\n v4 = 0LL;\n if (a2 > 0) {\n while (1) {\n v5 = *(uint32_t *)(a1 + v4 + 8);\n if (v5 != *(uint32_t *)(a3 + v4 + 8)) return 0LL;\n v6 = 0LL;\n if (v5 > 0) {\n while (*(uint32_t *)(*(uint64_t *)(a1 + v4) + v6) ==\n *(uint32_t *)(*(uint64_t *)(a3 + v4) + v6)) {\n v6 += 4LL;\n if (4LL * v5 == v6) goto LABEL_9;\n }\n return 0LL;\n }\n LABEL_9:\n v4 += 16LL;\n if (v4 == 16LL * a2) return 1LL;\n }\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3, int a4) {\n long long v4;\n int v5;\n long long v6;\n if (a2 != a4) return 0LL;\n v4 = 0LL;\n if (a2 > 0) {\n while (1) {\n v5 = *(uint32_t *)(a1 + v4 + 8);\n if (v5 != *(uint32_t *)(a3 + v4 + 8)) return 0LL;\n v6 = 0LL;\n if (v5 > 0) {\n while (*(uint32_t *)(*(uint64_t *)(a1 + v4) + v6) ==\n *(uint32_t *)(*(uint64_t *)(a3 + v4) + v6)) {\n v6 += 4LL;\n if (4LL * v5 == v6) goto LABEL_9;\n }\n return 0LL;\n }\n LABEL_9:\n v4 += 16LL;\n if (v4 == 16LL * a2) return 1LL;\n }\n }\n return 1LL;\n}" + }, + { + "index": 196, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\nstruct Tuple {\n\n int *elements;\n\n int size;\n\n};\n\n\n\nstruct TupleList {\n\n struct Tuple *tuples;\n\n int size;\n\n};\n\n\n\nstruct TupleList remove_tuples(struct TupleList test_list, int K) {\n\n struct TupleList res;\n\n res.tuples = malloc(test_list.size * sizeof(struct Tuple));\n\n res.size = 0;\n\n for (int i = 0; i < test_list.size; i++) {\n\n if (test_list.tuples[i].size != K) {\n\n res.tuples[res.size++] = test_list.tuples[i];\n\n }\n\n }\n\n return res;\n\n}\n\n\n\nint compare_tuples(struct Tuple t1, struct Tuple t2) {\n\n if (t1.size != t2.size) return 0;\n\n for (int i = 0; i < t1.size; i++) {\n\n if (t1.elements[i] != t2.elements[i]) {\n\n return 0;\n\n }\n\n }\n\n return 1;\n\n}\n\n\n\n", + "func": "int func0(struct TupleList l1, struct TupleList l2) {\n if (l1.size != l2.size) return 0;\n for (int i = 0; i < l1.size; i++) {\n if (!compare_tuples(l1.tuples[i], l2.tuples[i])) return 0;\n }\n return 1;\n}", + "test": "int main() {\n\n int tuple1[] = {4, 5};\n\n int tuple2[] = {4};\n\n int tuple3[] = {8, 6, 7};\n\n int tuple4[] = {1};\n\n int tuple5[] = {3, 4, 6, 7};\n\n struct Tuple tuples1[] = {{tuple1, 2}, {tuple2, 1}, {tuple3, 3}, {tuple4, 1}, {tuple5, 4}};\n\n struct TupleList test_list1 = {tuples1, 5};\n\n struct Tuple expected1[] = {{tuple1, 2}, {tuple3, 3}, {tuple5, 4}};\n\n struct TupleList expected_list1 = {expected1, 3};\n\n struct TupleList result1 = remove_tuples(test_list1, 1);\n\n \n\n int tuple6[] = {4, 5};\n\n int tuple7[] = {4, 5};\n\n int tuple8[] = {6, 7};\n\n int tuple9[] = {1, 2, 3};\n\n int tuple10[] = {3, 4, 6, 7};\n\n struct Tuple tuples2[] = {{tuple6, 2}, {tuple7, 2}, {tuple8, 2}, {tuple9, 3}, {tuple10, 4}};\n\n struct TupleList test_list2 = {tuples2, 5};\n\n struct Tuple expected2[] = {{tuple9, 3}, {tuple10, 4}};\n\n struct TupleList expected_list2 = {expected2, 2};\n\n struct TupleList result2 = remove_tuples(test_list2, 2);\n\n\n\n int tuple11[] = {1, 4, 4};\n\n int tuple12[] = {4, 3};\n\n int tuple13[] = {8, 6, 7};\n\n int tuple14[] = {1};\n\n int tuple15[] = {3, 6, 7};\n\n struct Tuple tuples3[] = {{tuple11, 3}, {tuple12, 2}, {tuple13, 3}, {tuple14, 1}, {tuple15, 3}};\n\n struct TupleList test_list3 = {tuples3, 5};\n\n struct Tuple expected3[] = {{tuple12, 2}, {tuple14, 1}};\n\n struct TupleList expected_list3 = {expected3, 2};\n\n struct TupleList result3 = remove_tuples(test_list3, 3);\n\n\n\n assert(func0(result1, expected_list1));\n\n assert(func0(result2, expected_list2));\n\n assert(func0(result3, expected_list3));\n\n\n\n printf(\"All tests passed!\\n\");\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nxor %eax,%eax\ncmp %ecx,%esi\njne 172e \ntest %esi,%esi\njle 1729 \nlea -0x1(%rsi),%eax\nxor %esi,%esi\nadd $0x1,%rax\nshl $0x4,%rax\nmov %rax,%r11\nmov 0x8(%rdi,%rsi,1),%eax\ncmp 0x8(%rdx,%rsi,1),%eax\njne 1716 \ntest %eax,%eax\njle 1720 \nlea -0x1(%rax),%r10d\nmov (%rdi,%rsi,1),%r9\nmov (%rdx,%rsi,1),%r8\nxor %eax,%eax\njmp 170c \nnopl 0x0(%rax)\nlea 0x1(%rax),%rcx\ncmp %rax,%r10\nje 1720 \nmov %rcx,%rax\nmov (%r8,%rax,4),%ecx\ncmp %ecx,(%r9,%rax,4)\nje 1700 \nxor %eax,%eax\nretq\nnopl 0x0(%rax)\nadd $0x10,%rsi\ncmp %r11,%rsi\njne 16de \nmov $0x1,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov r10, rdi\nxor eax, eax\ncmp esi, ecx\njnz short locret_1725\ntest esi, esi\njle short loc_1739\nmovsxd rsi, esi\nxor edi, edi\nshl rsi, 4\nloc_16EA:\nmovsxd rcx, dword ptr [r10+rdi+8]\ncmp ecx, [rdx+rdi+8]\njnz short loc_1723\ntest ecx, ecx\njle short loc_1730\nmov r9, [r10+rdi]\nmov r8, [rdx+rdi]\nshl rcx, 2\nxor eax, eax\njmp short loc_1719\nloc_1710:\nadd rax, 4\ncmp rcx, rax\njz short loc_1730\nloc_1719:\nmov r11d, [r8+rax]\ncmp [r9+rax], r11d\njz short loc_1710\nloc_1723:\nxor eax, eax\nlocret_1725:\nretn\nloc_1730:\nadd rdi, 10h\ncmp rsi, rdi\njnz short loc_16EA\nloc_1739:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3, int a4)\n{\n __int64 result; // rax\n __int64 v6; // rdi\n __int64 v7; // rsi\n __int64 v8; // rcx\n __int64 v9; // rcx\n __int64 v10; // rax\n\n result = 0LL;\n if ( a2 == a4 )\n {\n if ( a2 <= 0 )\n {\n return 1LL;\n }\n else\n {\n v6 = 0LL;\n v7 = 16LL * a2;\n while ( 1 )\n {\n v8 = *(int *)(a1 + v6 + 8);\n if ( (_DWORD)v8 != *(_DWORD *)(a3 + v6 + 8) )\n return 0LL;\n if ( (int)v8 > 0 )\n {\n v9 = 4 * v8;\n v10 = 0LL;\n while ( *(_DWORD *)(*(_QWORD *)(a1 + v6) + v10) == *(_DWORD *)(*(_QWORD *)(a3 + v6) + v10) )\n {\n v10 += 4LL;\n if ( v9 == v10 )\n goto LABEL_11;\n }\n return 0LL;\n }\nLABEL_11:\n v6 += 16LL;\n if ( v7 == v6 )\n return 1LL;\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_16D0:\nendbr64\nmov r10, rdi\nxor eax, eax\ncmp esi, ecx\njnz short locret_1725\ntest esi, esi\njle short loc_1739\nmovsxd rsi, esi\nxor edi, edi\nshl rsi, 4\nloc_16EA:\nmovsxd rcx, dword ptr [r10+rdi+8]\ncmp ecx, [rdx+rdi+8]\njnz short loc_1723\ntest ecx, ecx\njle short loc_1730\nmov r9, [r10+rdi]\nmov r8, [rdx+rdi]\nshl rcx, 2\nxor eax, eax\njmp short loc_1719\nloc_1710:\nadd rax, 4\ncmp rcx, rax\njz short loc_1730\nloc_1719:\nmov r11d, [r8+rax]\ncmp [r9+rax], r11d\njz short loc_1710\nloc_1723:\nxor eax, eax\nlocret_1725:\nretn\nloc_1730:\nadd rdi, 10h\ncmp rsi, rdi\njnz short loc_16EA\nloc_1739:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_16D0(__int64 a1, int a2, __int64 a3, int a4)\n{\n __int64 result; // rax\n __int64 v6; // rdi\n __int64 v7; // rsi\n __int64 v8; // rcx\n __int64 v9; // rcx\n __int64 v10; // rax\n\n result = 0LL;\n if ( a2 == a4 )\n {\n if ( a2 <= 0 )\n {\n return 1LL;\n }\n else\n {\n v6 = 0LL;\n v7 = 16LL * a2;\n while ( 1 )\n {\n v8 = *(int *)(a1 + v6 + 8);\n if ( (_DWORD)v8 != *(_DWORD *)(a3 + v6 + 8) )\n return 0LL;\n if ( (int)v8 > 0 )\n {\n v9 = 4 * v8;\n v10 = 0LL;\n while ( *(_DWORD *)(*(_QWORD *)(a1 + v6) + v10) == *(_DWORD *)(*(_QWORD *)(a3 + v6) + v10) )\n {\n v10 += 4LL;\n if ( v9 == v10 )\n goto LABEL_11;\n }\n return 0LL;\n }\nLABEL_11:\n v6 += 16LL;\n if ( v7 == v6 )\n return 1LL;\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_16D0(long long a1, int a2, long long a3, int a4) {\n long long result;\n long long v6;\n long long v7;\n long long v8;\n long long v9;\n long long v10;\n result = 0LL;\n if (a2 == a4) {\n if (a2 <= 0) {\n return 1LL;\n } else {\n v6 = 0LL;\n v7 = 16LL * a2;\n while (1) {\n v8 = *(int *)(a1 + v6 + 8);\n if ((uint32_t)v8 != *(uint32_t *)(a3 + v6 + 8)) return 0LL;\n if ((int)v8 > 0) {\n v9 = 4 * v8;\n v10 = 0LL;\n while (*(uint32_t *)(*(uint64_t *)(a1 + v6) + v10) ==\n *(uint32_t *)(*(uint64_t *)(a3 + v6) + v10)) {\n v10 += 4LL;\n if (v9 == v10) goto LABEL_11;\n }\n return 0LL;\n }\n LABEL_11:\n v6 += 16LL;\n if (v7 == v6) return 1LL;\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3, int a4) {\n long long result;\n long long v6;\n long long v7;\n long long v8;\n long long v9;\n long long v10;\n result = 0LL;\n if (a2 == a4) {\n if (a2 <= 0) {\n return 1LL;\n } else {\n v6 = 0LL;\n v7 = 16LL * a2;\n while (1) {\n v8 = *(int *)(a1 + v6 + 8);\n if ((uint32_t)v8 != *(uint32_t *)(a3 + v6 + 8)) return 0LL;\n if ((int)v8 > 0) {\n v9 = 4 * v8;\n v10 = 0LL;\n while (*(uint32_t *)(*(uint64_t *)(a1 + v6) + v10) ==\n *(uint32_t *)(*(uint64_t *)(a3 + v6) + v10)) {\n v10 += 4LL;\n if (v9 == v10) goto LABEL_11;\n }\n return 0LL;\n }\n LABEL_11:\n v6 += 16LL;\n if (v7 == v6) return 1LL;\n }\n }\n }\n return result;\n}" + }, + { + "index": 197, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int test_tup1[], int test_tup2[], int n) {\n int* res = malloc(sizeof(int) * n);\n for (int i = 0; i < n; i++) {\n res[i] = (int)pow(test_tup1[i], test_tup2[i]);\n }\n return res;\n}", + "test": "int main() {\n\n int test1_tup1[] = {10, 4, 5, 6};\n\n int test1_tup2[] = {5, 6, 7, 5};\n\n int expected1[] = {100000, 4096, 78125, 7776};\n\n int* res1 = func0(test1_tup1, test1_tup2, 4);\n\n assert(memcmp(res1, expected1, sizeof(expected1)) == 0);\n\n free(res1);\n\n\n\n int test2_tup1[] = {11, 5, 6, 7};\n\n int test2_tup2[] = {6, 7, 8, 6};\n\n int expected2[] = {1771561, 78125, 1679616, 117649};\n\n int* res2 = func0(test2_tup1, test2_tup2, 4);\n\n assert(memcmp(res2, expected2, sizeof(expected2)) == 0);\n\n free(res2);\n\n\n\n int test3_tup1[] = {12, 6, 7, 8};\n\n int test3_tup2[] = {7, 8, 9, 7};\n\n int expected3[] = {35831808, 1679616, 40353607, 2097152};\n\n int* res3 = func0(test3_tup1, test3_tup2, 4);\n\n assert(memcmp(res3, expected3, sizeof(expected3)) == 0);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %edx,-0x24(%rbp)\nmov -0x24(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10f0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 1275 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncvtsi2sd %eax,%xmm1\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncvtsi2sd %eax,%xmm0\ncallq 10b0 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\ncvttsd2si %xmm0,%eax\nmov %eax,(%rdx)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x24(%rbp),%eax\njl 121e \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov eax, [rbp+var_24]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp short loc_128B\nloc_121E:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov eax, [rax]\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\npxor xmm2, xmm2\ncvtsi2sd xmm2, eax\nmovq rax, xmm2\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\ncvttsd2si eax, xmm0\nmov [rdx], eax\nadd [rbp+var_C], 1\nloc_128B:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_24]\njl short loc_121E\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n int i; // [rsp+24h] [rbp-Ch]\n _DWORD *v6; // [rsp+28h] [rbp-8h]\n\n v6 = malloc(4LL * a3);\n for ( i = 0; i < a3; ++i )\n v6[i] = (int)pow((double)*(int *)(4LL * i + a1), (double)*(int *)(4LL * i + a2));\n return v6;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov eax, [rbp+var_24]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp short loc_128B\nloc_121E:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov eax, [rax]\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\npxor xmm2, xmm2\ncvtsi2sd xmm2, eax\nmovq rax, xmm2\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\ncvttsd2si eax, xmm0\nmov [rdx], eax\nadd [rbp+var_C], 1\nloc_128B:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_24]\njl short loc_121E\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11E9(__int64 a1, __int64 a2, int a3)\n{\n int i; // [rsp+24h] [rbp-Ch]\n _DWORD *v6; // [rsp+28h] [rbp-8h]\n\n v6 = malloc(4LL * a3);\n for ( i = 0; i < a3; ++i )\n v6[i] = (int)pow((double)*(int *)(4LL * i + a1), (double)*(int *)(4LL * i + a2));\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11E9(long long a1, long long a2, int a3) {\n int i;\n uint32_t *v6;\n v6 = malloc(4LL * a3);\n for (i = 0; i < a3; ++i)\n v6[i] = (int)pow((double)*(int *)(4LL * i + a1),\n (double)*(int *)(4LL * i + a2));\n return v6;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, long long a2, int a3) {\n int i;\n uint32_t *v6;\n v6 = malloc(4LL * a3);\n for (i = 0; i < a3; ++i)\n v6[i] = (int)pow((double)*(int *)(4LL * i + a1),\n (double)*(int *)(4LL * i + a2));\n return v6;\n}" + }, + { + "index": 197, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int test_tup1[], int test_tup2[], int n) {\n int* res = malloc(sizeof(int) * n);\n for (int i = 0; i < n; i++) {\n res[i] = (int)pow(test_tup1[i], test_tup2[i]);\n }\n return res;\n}", + "test": "int main() {\n\n int test1_tup1[] = {10, 4, 5, 6};\n\n int test1_tup2[] = {5, 6, 7, 5};\n\n int expected1[] = {100000, 4096, 78125, 7776};\n\n int* res1 = func0(test1_tup1, test1_tup2, 4);\n\n assert(memcmp(res1, expected1, sizeof(expected1)) == 0);\n\n free(res1);\n\n\n\n int test2_tup1[] = {11, 5, 6, 7};\n\n int test2_tup2[] = {6, 7, 8, 6};\n\n int expected2[] = {1771561, 78125, 1679616, 117649};\n\n int* res2 = func0(test2_tup1, test2_tup2, 4);\n\n assert(memcmp(res2, expected2, sizeof(expected2)) == 0);\n\n free(res2);\n\n\n\n int test3_tup1[] = {12, 6, 7, 8};\n\n int test3_tup2[] = {7, 8, 9, 7};\n\n int expected3[] = {35831808, 1679616, 40353607, 2097152};\n\n int* res3 = func0(test3_tup1, test3_tup2, 4);\n\n assert(memcmp(res3, expected3, sizeof(expected3)) == 0);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%r12\nmov %rsi,%r13\nmov %edx,%ebx\nmovslq %edx,%rdi\nshl $0x2,%rdi\ncallq 10f0 \nmov %rax,%rbp\ntest %ebx,%ebx\njle 1247 \nlea -0x1(%rbx),%r14d\nmov $0x0,%ebx\npxor %xmm0,%xmm0\ncvtsi2sdl (%r12,%rbx,4),%xmm0\npxor %xmm1,%xmm1\ncvtsi2sdl 0x0(%r13,%rbx,4),%xmm1\ncallq 10b0 \ncvttsd2si %xmm0,%eax\nmov %eax,0x0(%rbp,%rbx,4)\nmov %rbx,%rax\nadd $0x1,%rbx\ncmp %r14,%rax\njne 1219 \nmov %rbp,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r13, rdi\nmov r14, rsi\nmov ebx, edx\nmovsxd r12, edx\nshl r12, 2\nmov rdi, r12; size\ncall _malloc\nmov rbp, rax\ntest ebx, ebx\njle short loc_1243\nmov ebx, 0\nloc_1218:\npxor xmm0, xmm0\ncvtsi2sd xmm0, dword ptr [r13+rbx+0]; x\npxor xmm1, xmm1\ncvtsi2sd xmm1, dword ptr [r14+rbx]; y\ncall _pow\ncvttsd2si eax, xmm0\nmov [rbp+rbx+0], eax\nadd rbx, 4\ncmp r12, rbx\njnz short loc_1218\nloc_1243:\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n size_t v4; // r12\n char *v5; // rbp\n __int64 v6; // rbx\n\n v4 = 4LL * a3;\n v5 = (char *)malloc(v4);\n if ( a3 > 0 )\n {\n v6 = 0LL;\n do\n {\n *(_DWORD *)&v5[v6] = (int)pow((double)*(int *)(a1 + v6), (double)*(int *)(a2 + v6));\n v6 += 4LL;\n }\n while ( v4 != v6 );\n }\n return v5;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r13, rdi\nmov r14, rsi\nmov ebx, edx\nmovsxd r12, edx\nshl r12, 2\nmov rdi, r12; size\ncall _malloc\nmov rbp, rax\ntest ebx, ebx\njle short loc_1243\nmov ebx, 0\nloc_1218:\npxor xmm0, xmm0\ncvtsi2sd xmm0, dword ptr [r13+rbx+0]; x\npxor xmm1, xmm1\ncvtsi2sd xmm1, dword ptr [r14+rbx]; y\ncall _pow\ncvttsd2si eax, xmm0\nmov [rbp+rbx+0], eax\nadd rbx, 4\ncmp r12, rbx\njnz short loc_1218\nloc_1243:\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11E9(__int64 a1, __int64 a2, int a3)\n{\n size_t v4; // r12\n char *v5; // rbp\n __int64 v6; // rbx\n\n v4 = 4LL * a3;\n v5 = (char *)malloc(v4);\n if ( a3 > 0 )\n {\n v6 = 0LL;\n do\n {\n *(_DWORD *)&v5[v6] = (int)pow((double)*(int *)(a1 + v6), (double)*(int *)(a2 + v6));\n v6 += 4LL;\n }\n while ( v4 != v6 );\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11E9(long long a1, long long a2, int a3) {\n unsigned int v4;\n char *v5;\n long long v6;\n v4 = 4LL * a3;\n v5 = (char *)malloc(v4);\n if (a3 > 0) {\n v6 = 0LL;\n do {\n *(uint32_t *)&v5[v6] =\n (int)pow((double)*(int *)(a1 + v6), (double)*(int *)(a2 + v6));\n v6 += 4LL;\n } while (v4 != v6);\n }\n return v5;\n}", + "ida_pseudo_norm": "char *func0(long long a1, long long a2, int a3) {\n unsigned int v4;\n char *v5;\n long long v6;\n v4 = 4LL * a3;\n v5 = (char *)malloc(v4);\n if (a3 > 0) {\n v6 = 0LL;\n do {\n *(uint32_t *)&v5[v6] =\n (int)pow((double)*(int *)(a1 + v6), (double)*(int *)(a2 + v6));\n v6 += 4LL;\n } while (v4 != v6);\n }\n return v5;\n}" + }, + { + "index": 197, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int test_tup1[], int test_tup2[], int n) {\n int* res = malloc(sizeof(int) * n);\n for (int i = 0; i < n; i++) {\n res[i] = (int)pow(test_tup1[i], test_tup2[i]);\n }\n return res;\n}", + "test": "int main() {\n\n int test1_tup1[] = {10, 4, 5, 6};\n\n int test1_tup2[] = {5, 6, 7, 5};\n\n int expected1[] = {100000, 4096, 78125, 7776};\n\n int* res1 = func0(test1_tup1, test1_tup2, 4);\n\n assert(memcmp(res1, expected1, sizeof(expected1)) == 0);\n\n free(res1);\n\n\n\n int test2_tup1[] = {11, 5, 6, 7};\n\n int test2_tup2[] = {6, 7, 8, 6};\n\n int expected2[] = {1771561, 78125, 1679616, 117649};\n\n int* res2 = func0(test2_tup1, test2_tup2, 4);\n\n assert(memcmp(res2, expected2, sizeof(expected2)) == 0);\n\n free(res2);\n\n\n\n int test3_tup1[] = {12, 6, 7, 8};\n\n int test3_tup2[] = {7, 8, 9, 7};\n\n int expected3[] = {35831808, 1679616, 40353607, 2097152};\n\n int* res3 = func0(test3_tup1, test3_tup2, 4);\n\n assert(memcmp(res3, expected3, sizeof(expected3)) == 0);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\nmov %rsi,%r13\npush %r12\npush %rbp\nmov %rdi,%rbp\nmovslq %edx,%rdi\npush %rbx\nmov %rdi,%rbx\nshl $0x2,%rdi\ncallq 10d0 \nmov %rax,%r12\ntest %ebx,%ebx\njle 146e \nlea -0x1(%rbx),%r14d\nxor %ebx,%ebx\nxchg %ax,%ax\npxor %xmm0,%xmm0\npxor %xmm1,%xmm1\ncvtsi2sdl 0x0(%rbp,%rbx,4),%xmm0\ncvtsi2sdl 0x0(%r13,%rbx,4),%xmm1\ncallq 10a0 \ncvttsd2si %xmm0,%eax\nmov %eax,(%r12,%rbx,4)\nmov %rbx,%rax\nadd $0x1,%rbx\ncmp %r14,%rax\njne 1440 \npop %rbx\nmov %r12,%rax\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\nmov r14, rsi\npush r13\nmov r13, rdi\npush r12\nmovsxd r12, edx\npush rbp\npush rbx\nmov rbx, r12\nshl r12, 2\nmov rdi, r12; size\ncall _malloc\nmov rbp, rax\ntest ebx, ebx\njle short loc_13DB\nxor ebx, ebx\nnop dword ptr [rax]\nloc_13B0:\npxor xmm0, xmm0\npxor xmm1, xmm1\ncvtsi2sd xmm0, dword ptr [r13+rbx+0]; x\ncvtsi2sd xmm1, dword ptr [r14+rbx]; y\ncall _pow\ncvttsd2si eax, xmm0\nmov [rbp+rbx+0], eax\nadd rbx, 4\ncmp r12, rbx\njnz short loc_13B0\nloc_13DB:\npop rbx\nmov rax, rbp\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n size_t v4; // r12\n char *v5; // rbp\n __int64 v6; // rbx\n\n v4 = 4LL * a3;\n v5 = (char *)malloc(v4);\n if ( a3 > 0 )\n {\n v6 = 0LL;\n do\n {\n *(_DWORD *)&v5[v6] = (int)pow((double)*(int *)(a1 + v6), (double)*(int *)(a2 + v6));\n v6 += 4LL;\n }\n while ( v4 != v6 );\n }\n return v5;\n}", + "ida_strip_asm": "sub_1380:\nendbr64\npush r14\nmov r14, rsi\npush r13\nmov r13, rdi\npush r12\nmovsxd r12, edx\npush rbp\npush rbx\nmov rbx, r12\nshl r12, 2\nmov rdi, r12; size\ncall _malloc\nmov rbp, rax\ntest ebx, ebx\njle short loc_13DB\nxor ebx, ebx\nnop dword ptr [rax]\nloc_13B0:\npxor xmm0, xmm0\npxor xmm1, xmm1\ncvtsi2sd xmm0, dword ptr [r13+rbx+0]; x\ncvtsi2sd xmm1, dword ptr [r14+rbx]; y\ncall _pow\ncvttsd2si eax, xmm0\nmov [rbp+rbx+0], eax\nadd rbx, 4\ncmp r12, rbx\njnz short loc_13B0\nloc_13DB:\npop rbx\nmov rax, rbp\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1380(__int64 a1, __int64 a2, int a3)\n{\n size_t v4; // r12\n char *v5; // rbp\n __int64 v6; // rbx\n\n v4 = 4LL * a3;\n v5 = (char *)malloc(v4);\n if ( a3 > 0 )\n {\n v6 = 0LL;\n do\n {\n *(_DWORD *)&v5[v6] = (int)pow((double)*(int *)(a1 + v6), (double)*(int *)(a2 + v6));\n v6 += 4LL;\n }\n while ( v4 != v6 );\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1380(long long a1, long long a2, int a3) {\n unsigned int v4;\n char *v5;\n long long v6;\n v4 = 4LL * a3;\n v5 = (char *)malloc(v4);\n if (a3 > 0) {\n v6 = 0LL;\n do {\n *(uint32_t *)&v5[v6] =\n (int)pow((double)*(int *)(a1 + v6), (double)*(int *)(a2 + v6));\n v6 += 4LL;\n } while (v4 != v6);\n }\n return v5;\n}", + "ida_pseudo_norm": "char *func0(long long a1, long long a2, int a3) {\n unsigned int v4;\n char *v5;\n long long v6;\n v4 = 4LL * a3;\n v5 = (char *)malloc(v4);\n if (a3 > 0) {\n v6 = 0LL;\n do {\n *(uint32_t *)&v5[v6] =\n (int)pow((double)*(int *)(a1 + v6), (double)*(int *)(a2 + v6));\n v6 += 4LL;\n } while (v4 != v6);\n }\n return v5;\n}" + }, + { + "index": 197, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int test_tup1[], int test_tup2[], int n) {\n int* res = malloc(sizeof(int) * n);\n for (int i = 0; i < n; i++) {\n res[i] = (int)pow(test_tup1[i], test_tup2[i]);\n }\n return res;\n}", + "test": "int main() {\n\n int test1_tup1[] = {10, 4, 5, 6};\n\n int test1_tup2[] = {5, 6, 7, 5};\n\n int expected1[] = {100000, 4096, 78125, 7776};\n\n int* res1 = func0(test1_tup1, test1_tup2, 4);\n\n assert(memcmp(res1, expected1, sizeof(expected1)) == 0);\n\n free(res1);\n\n\n\n int test2_tup1[] = {11, 5, 6, 7};\n\n int test2_tup2[] = {6, 7, 8, 6};\n\n int expected2[] = {1771561, 78125, 1679616, 117649};\n\n int* res2 = func0(test2_tup1, test2_tup2, 4);\n\n assert(memcmp(res2, expected2, sizeof(expected2)) == 0);\n\n free(res2);\n\n\n\n int test3_tup1[] = {12, 6, 7, 8};\n\n int test3_tup2[] = {7, 8, 9, 7};\n\n int expected3[] = {35831808, 1679616, 40353607, 2097152};\n\n int* res3 = func0(test3_tup1, test3_tup2, 4);\n\n assert(memcmp(res3, expected3, sizeof(expected3)) == 0);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\nmov %rsi,%r13\npush %r12\npush %rbp\nmov %rdi,%rbp\nmovslq %edx,%rdi\npush %rbx\nmov %rdi,%rbx\nshl $0x2,%rdi\ncallq 10d0 \nmov %rax,%r12\ntest %ebx,%ebx\njle 13ee \nlea -0x1(%rbx),%r14d\nxor %ebx,%ebx\nxchg %ax,%ax\npxor %xmm0,%xmm0\npxor %xmm1,%xmm1\ncvtsi2sdl 0x0(%rbp,%rbx,4),%xmm0\ncvtsi2sdl 0x0(%r13,%rbx,4),%xmm1\ncallq 10a0 \ncvttsd2si %xmm0,%eax\nmov %eax,(%r12,%rbx,4)\nmov %rbx,%rax\nadd $0x1,%rbx\ncmp %r14,%rax\njne 13c0 \npop %rbx\nmov %r12,%rax\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\nmov r14, rsi\npush r13\nmov r13, rdi\npush r12\nmovsxd r12, edx\npush rbp\npush rbx\nmov rbx, r12\nshl r12, 2\nmov rdi, r12; size\ncall _malloc\nmov rbp, rax\ntest ebx, ebx\njle short loc_13DB\nxor ebx, ebx\nnop dword ptr [rax]\nloc_13B0:\npxor xmm0, xmm0\npxor xmm1, xmm1\ncvtsi2sd xmm0, dword ptr [r13+rbx+0]; x\ncvtsi2sd xmm1, dword ptr [r14+rbx]; y\ncall _pow\ncvttsd2si eax, xmm0\nmov [rbp+rbx+0], eax\nadd rbx, 4\ncmp r12, rbx\njnz short loc_13B0\nloc_13DB:\npop rbx\nmov rax, rbp\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n size_t v4; // r12\n char *v5; // rbp\n __int64 v6; // rbx\n\n v4 = 4LL * a3;\n v5 = (char *)malloc(v4);\n if ( a3 > 0 )\n {\n v6 = 0LL;\n do\n {\n *(_DWORD *)&v5[v6] = (int)pow((double)*(int *)(a1 + v6), (double)*(int *)(a2 + v6));\n v6 += 4LL;\n }\n while ( v4 != v6 );\n }\n return v5;\n}", + "ida_strip_asm": "sub_1380:\nendbr64\npush r14\nmov r14, rsi\npush r13\nmov r13, rdi\npush r12\nmovsxd r12, edx\npush rbp\npush rbx\nmov rbx, r12\nshl r12, 2\nmov rdi, r12; size\ncall _malloc\nmov rbp, rax\ntest ebx, ebx\njle short loc_13DB\nxor ebx, ebx\nnop dword ptr [rax]\nloc_13B0:\npxor xmm0, xmm0\npxor xmm1, xmm1\ncvtsi2sd xmm0, dword ptr [r13+rbx+0]; x\ncvtsi2sd xmm1, dword ptr [r14+rbx]; y\ncall _pow\ncvttsd2si eax, xmm0\nmov [rbp+rbx+0], eax\nadd rbx, 4\ncmp r12, rbx\njnz short loc_13B0\nloc_13DB:\npop rbx\nmov rax, rbp\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1380(__int64 a1, __int64 a2, int a3)\n{\n size_t v4; // r12\n char *v5; // rbp\n __int64 v6; // rbx\n\n v4 = 4LL * a3;\n v5 = (char *)malloc(v4);\n if ( a3 > 0 )\n {\n v6 = 0LL;\n do\n {\n *(_DWORD *)&v5[v6] = (int)pow((double)*(int *)(a1 + v6), (double)*(int *)(a2 + v6));\n v6 += 4LL;\n }\n while ( v4 != v6 );\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1380(long long a1, long long a2, int a3) {\n unsigned int v4;\n char *v5;\n long long v6;\n v4 = 4LL * a3;\n v5 = (char *)malloc(v4);\n if (a3 > 0) {\n v6 = 0LL;\n do {\n *(uint32_t *)&v5[v6] =\n (int)pow((double)*(int *)(a1 + v6), (double)*(int *)(a2 + v6));\n v6 += 4LL;\n } while (v4 != v6);\n }\n return v5;\n}", + "ida_pseudo_norm": "char *func0(long long a1, long long a2, int a3) {\n unsigned int v4;\n char *v5;\n long long v6;\n v4 = 4LL * a3;\n v5 = (char *)malloc(v4);\n if (a3 > 0) {\n v6 = 0LL;\n do {\n *(uint32_t *)&v5[v6] =\n (int)pow((double)*(int *)(a1 + v6), (double)*(int *)(a2 + v6));\n v6 += 4LL;\n } while (v4 != v6);\n }\n return v5;\n}" + }, + { + "index": 198, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int a, int b) {\n if (a < 0 || b < 0) {\n return -1;\n }\n double area = (3 * sqrt(3) * pow(a, 2)) / (4 * b);\n return area;\n}", + "test": "int main() {\n\n assert(func0(4, 2) == 10.392304845413264);\n\n assert(func0(5, 7) == 4.639421805988064);\n\n assert(func0(9, 1) == 105.2220865598093);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\ncmpl $0x0,-0x14(%rbp)\njs 1187 \ncmpl $0x0,-0x18(%rbp)\njns 1191 \nmovsd 0xf31(%rip),%xmm0\njmp 11c7 \ncvtsi2sdl -0x14(%rbp),%xmm0\nmovsd 0xf2a(%rip),%xmm1\ncallq 1060 \nmovsd 0xf25(%rip),%xmm1\nmulsd %xmm1,%xmm0\nmov -0x18(%rbp),%eax\nshl $0x2,%eax\ncvtsi2sd %eax,%xmm1\ndivsd %xmm1,%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmovsd -0x8(%rbp),%xmm0\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\ncmp [rbp+var_14], 0\njs short loc_1187\ncmp [rbp+var_18], 0\njns short loc_1191\nloc_1187:\nmovsd xmm0, cs:qword_20A0\njmp short locret_11DD\nloc_1191:\npxor xmm2, xmm2\ncvtsi2sd xmm2, [rbp+var_14]\nmovq rax, xmm2\nmovsd xmm0, cs:y\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\nmovsd xmm1, cs:qword_20B0\nmulsd xmm0, xmm1\nmov eax, [rbp+var_18]\nshl eax, 2\npxor xmm1, xmm1\ncvtsi2sd xmm1, eax\ndivsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\nlocret_11DD:\nleave\nretn", + "ida_pseudo": "double __fastcall func0(int a1, int a2)\n{\n if ( a1 >= 0 && a2 >= 0 )\n return pow((double)a1, 2.0) * 5.196152422706632 / (double)(4 * a2);\n else\n return -1.0;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\ncmp [rbp+var_14], 0\njs short loc_1187\ncmp [rbp+var_18], 0\njns short loc_1191\nloc_1187:\nmovsd xmm0, cs:qword_20A0\njmp short locret_11DD\nloc_1191:\npxor xmm2, xmm2\ncvtsi2sd xmm2, [rbp+var_14]\nmovq rax, xmm2\nmovsd xmm0, cs:y\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\nmovsd xmm1, cs:qword_20B0\nmulsd xmm0, xmm1\nmov eax, [rbp+var_18]\nshl eax, 2\npxor xmm1, xmm1\ncvtsi2sd xmm1, eax\ndivsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\nlocret_11DD:\nleave\nretn", + "ida_strip_pseudo": "double __fastcall sub_1169(int a1, int a2)\n{\n if ( a1 >= 0 && a2 >= 0 )\n return pow((double)a1, 2.0) * 5.196152422706632 / (double)(4 * a2);\n else\n return -1.0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1169(int a1, int a2) {\n if (a1 >= 0 && a2 >= 0)\n return pow((double)a1, 2.0) * 5.196152422706632 / (double)(4 * a2);\n else\n return -1.0;\n}", + "ida_pseudo_norm": "double func0(int a1, int a2) {\n if (a1 >= 0 && a2 >= 0)\n return pow((double)a1, 2.0) * 5.196152422706632 / (double)(4 * a2);\n else\n return -1.0;\n}" + }, + { + "index": 199, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int res = 0;\n for (int i = n; i > 0; i--) {\n if ((i & (i - 1)) == 0) {\n res = i;\n break;\n }\n }\n return res;\n}", + "test": "int main() {\n\n assert(func0(10) == 8);\n\n assert(func0(19) == 16);\n\n assert(func0(32) == 32);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmovl $0x0,-0x8(%rbp)\nmov -0x14(%rbp),%eax\nmov %eax,-0x4(%rbp)\njmp 117c \nmov -0x4(%rbp),%eax\nsub $0x1,%eax\nand -0x4(%rbp),%eax\ntest %eax,%eax\njne 1178 \nmov -0x4(%rbp),%eax\nmov %eax,-0x8(%rbp)\njmp 1182 \nsubl $0x1,-0x4(%rbp)\ncmpl $0x0,-0x4(%rbp)\njg 1163 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_8], 0\nmov eax, [rbp+var_14]\nmov [rbp+var_4], eax\njmp short loc_117C\nloc_1163:\nmov eax, [rbp+var_4]\nsub eax, 1\nand eax, [rbp+var_4]\ntest eax, eax\njnz short loc_1178\nmov eax, [rbp+var_4]\nmov [rbp+var_8], eax\njmp short loc_1182\nloc_1178:\nsub [rbp+var_4], 1\nloc_117C:\ncmp [rbp+var_4], 0\njg short loc_1163\nloc_1182:\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v2; // [rsp+Ch] [rbp-8h]\n\n v2 = 0;\n while ( a1 > 0 )\n {\n if ( (a1 & (a1 - 1)) == 0 )\n return (unsigned int)a1;\n --a1;\n }\n return v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_8], 0\nmov eax, [rbp+var_14]\nmov [rbp+var_4], eax\njmp short loc_117C\nloc_1163:\nmov eax, [rbp+var_4]\nsub eax, 1\nand eax, [rbp+var_4]\ntest eax, eax\njnz short loc_1178\nmov eax, [rbp+var_4]\nmov [rbp+var_8], eax\njmp short loc_1182\nloc_1178:\nsub [rbp+var_4], 1\nloc_117C:\ncmp [rbp+var_4], 0\njg short loc_1163\nloc_1182:\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n unsigned int v2; // [rsp+Ch] [rbp-8h]\n\n v2 = 0;\n while ( a1 > 0 )\n {\n if ( (a1 & (a1 - 1)) == 0 )\n return (unsigned int)a1;\n --a1;\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n unsigned int v2;\n v2 = 0;\n while (a1 > 0) {\n if ((a1 & (a1 - 1)) == 0) return (unsigned int)a1;\n --a1;\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v2;\n v2 = 0;\n while (a1 > 0) {\n if ((a1 & (a1 - 1)) == 0) return (unsigned int)a1;\n --a1;\n }\n return v2;\n}" + }, + { + "index": 199, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int res = 0;\n for (int i = n; i > 0; i--) {\n if ((i & (i - 1)) == 0) {\n res = i;\n break;\n }\n }\n return res;\n}", + "test": "int main() {\n\n assert(func0(10) == 8);\n\n assert(func0(19) == 16);\n\n assert(func0(32) == 32);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\njle 115c \nlea -0x1(%rdi),%eax\ntest %edi,%eax\nje 1162 \nmov %eax,%edi\njmp 114d \nmov $0x0,%eax\nretq\nmov %edi,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nloc_114D:\ntest edi, edi\njle short loc_115C\nlea eax, [rdi-1]\ntest eax, edi\njz short loc_1162\nmov edi, eax\njmp short loc_114D\nloc_115C:\nmov eax, 0\nretn\nloc_1162:\nmov eax, edi\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n while ( 1 )\n {\n if ( a1 <= 0 )\n return 0LL;\n if ( (a1 & (a1 - 1)) == 0 )\n break;\n --a1;\n }\n return (unsigned int)a1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nloc_114D:\ntest edi, edi\njle short loc_115C\nlea eax, [rdi-1]\ntest eax, edi\njz short loc_1162\nmov edi, eax\njmp short loc_114D\nloc_115C:\nmov eax, 0\nretn\nloc_1162:\nmov eax, edi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n while ( 1 )\n {\n if ( a1 <= 0 )\n return 0LL;\n if ( (a1 & (a1 - 1)) == 0 )\n break;\n --a1;\n }\n return (unsigned int)a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n while (1) {\n if (a1 <= 0) return 0LL;\n if ((a1 & (a1 - 1)) == 0) break;\n --a1;\n }\n return (unsigned int)a1;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n while (1) {\n if (a1 <= 0) return 0LL;\n if ((a1 & (a1 - 1)) == 0) break;\n --a1;\n }\n return (unsigned int)a1;\n}" + }, + { + "index": 200, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int* list1, int size, int* resultSize) {\n int max_val = list1[0];\n for (int i = 1; i < size; i++) {\n if (list1[i] > max_val) {\n max_val = list1[i];\n }\n }\n static int max_result[100];\n int count = 0;\n for (int i = 0; i < size; i++) {\n if (list1[i] == max_val) {\n max_result[count++] = i;\n }\n }\n *resultSize = count;\n return max_result;\n}", + "test": "int main() {\n\n int resultSize;\n\n int* result;\n\n\n\n result = func0((int[]){12,33,23,10,67,89,45,667,23,12,11,10,54}, 13, &resultSize);\n\n int expected1[] = {7};\n\n assert(resultSize == 1 && result[0] == expected1[0]);\n\n\n\n result = func0((int[]){1,2,2,2,4,4,4,5,5,5,5}, 11, &resultSize);\n\n int expected2[] = {7, 8, 9, 10};\n\n assert(resultSize == 4);\n\n for (int i = 0; i < 4; i++) {\n\n assert(result[i] == expected2[i]);\n\n }\n\n\n\n result = func0((int[]){2,1,5,6,8,3,4,9,10,11,8,12}, 12, &resultSize);\n\n int expected3[] = {11};\n\n assert(resultSize == 1 && result[0] == expected3[0]);\n\n\n\n printf(\"All tests passed.\\n\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmov -0x18(%rbp),%rax\nmov (%rax),%eax\nmov %eax,-0x10(%rbp)\nmovl $0x1,-0xc(%rbp)\njmp 11e6 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x10(%rbp)\njge 11e2 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x10(%rbp)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11ae \nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 123d \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x10(%rbp)\njne 1239 \nmov -0x8(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x8(%rbp)\ncltq\nlea 0x0(,%rax,4),%rcx\nlea 0x2e0d(%rip),%rdx\nmov -0x4(%rbp),%eax\nmov %eax,(%rcx,%rdx,1)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11fe \nmov -0x28(%rbp),%rax\nmov -0x8(%rbp),%edx\nmov %edx,(%rax)\nlea 0x2deb(%rip),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov rax, [rbp+var_18]\nmov eax, [rax]\nmov [rbp+var_10], eax\nmov [rbp+var_C], 1\njmp short loc_11E6\nloc_11AE:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_10], eax\njge short loc_11E2\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_10], eax\nloc_11E2:\nadd [rbp+var_C], 1\nloc_11E6:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_11AE\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_123D\nloc_11FE:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_10], eax\njnz short loc_1239\nmov eax, [rbp+var_8]\nlea edx, [rax+1]\nmov [rbp+var_8], edx\ncdqe\nlea rcx, ds:0[rax*4]\nlea rdx, max_result_1\nmov eax, [rbp+var_4]\nmov [rcx+rdx], eax\nloc_1239:\nadd [rbp+var_4], 1\nloc_123D:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11FE\nmov rax, [rbp+var_28]\nmov edx, [rbp+var_8]\nmov [rax], edx\nlea rax, max_result_1\npop rbp\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2, _DWORD *a3)\n{\n int v3; // eax\n int v5; // [rsp+18h] [rbp-10h]\n int i; // [rsp+1Ch] [rbp-Ch]\n int v7; // [rsp+20h] [rbp-8h]\n int j; // [rsp+24h] [rbp-4h]\n\n v5 = *a1;\n for ( i = 1; i < a2; ++i )\n {\n if ( v5 < a1[i] )\n v5 = a1[i];\n }\n v7 = 0;\n for ( j = 0; j < a2; ++j )\n {\n if ( v5 == a1[j] )\n {\n v3 = v7++;\n max_result_1[v3] = j;\n }\n }\n *a3 = v7;\n return max_result_1;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov rax, [rbp+var_18]\nmov eax, [rax]\nmov [rbp+var_10], eax\nmov [rbp+var_C], 1\njmp short loc_11E6\nloc_11AE:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_10], eax\njge short loc_11E2\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_10], eax\nloc_11E2:\nadd [rbp+var_C], 1\nloc_11E6:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_11AE\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_123D\nloc_11FE:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_10], eax\njnz short loc_1239\nmov eax, [rbp+var_8]\nlea edx, [rax+1]\nmov [rbp+var_8], edx\ncdqe\nlea rcx, ds:0[rax*4]\nlea rdx, unk_4040\nmov eax, [rbp+var_4]\nmov [rcx+rdx], eax\nloc_1239:\nadd [rbp+var_4], 1\nloc_123D:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11FE\nmov rax, [rbp+var_28]\nmov edx, [rbp+var_8]\nmov [rax], edx\nlea rax, unk_4040\npop rbp\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1189(int *a1, int a2, _DWORD *a3)\n{\n int v3; // eax\n int v5; // [rsp+18h] [rbp-10h]\n int i; // [rsp+1Ch] [rbp-Ch]\n int v7; // [rsp+20h] [rbp-8h]\n int j; // [rsp+24h] [rbp-4h]\n\n v5 = *a1;\n for ( i = 1; i < a2; ++i )\n {\n if ( v5 < a1[i] )\n v5 = a1[i];\n }\n v7 = 0;\n for ( j = 0; j < a2; ++j )\n {\n if ( v5 == a1[j] )\n {\n v3 = v7++;\n dword_4040[v3] = j;\n }\n }\n *a3 = v7;\n return dword_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1189(int *a1, int a2, uint32_t *a3) {\n int v3;\n int v5;\n int i;\n int v7;\n int j;\n v5 = *a1;\n for (i = 1; i < a2; ++i) {\n if (v5 < a1[i]) v5 = a1[i];\n }\n v7 = 0;\n for (j = 0; j < a2; ++j) {\n if (v5 == a1[j]) {\n v3 = v7++;\n dword_4040[v3] = j;\n }\n }\n *a3 = v7;\n return dword_4040;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2, uint32_t *a3) {\n int v3;\n int v5;\n int i;\n int v7;\n int j;\n v5 = *a1;\n for (i = 1; i < a2; ++i) {\n if (v5 < a1[i]) v5 = a1[i];\n }\n v7 = 0;\n for (j = 0; j < a2; ++j) {\n if (v5 == a1[j]) {\n v3 = v7++;\n max_result_1[v3] = j;\n }\n }\n *a3 = v7;\n return max_result_1;\n}" + }, + { + "index": 200, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int* list1, int size, int* resultSize) {\n int max_val = list1[0];\n for (int i = 1; i < size; i++) {\n if (list1[i] > max_val) {\n max_val = list1[i];\n }\n }\n static int max_result[100];\n int count = 0;\n for (int i = 0; i < size; i++) {\n if (list1[i] == max_val) {\n max_result[count++] = i;\n }\n }\n *resultSize = count;\n return max_result;\n}", + "test": "int main() {\n\n int resultSize;\n\n int* result;\n\n\n\n result = func0((int[]){12,33,23,10,67,89,45,667,23,12,11,10,54}, 13, &resultSize);\n\n int expected1[] = {7};\n\n assert(resultSize == 1 && result[0] == expected1[0]);\n\n\n\n result = func0((int[]){1,2,2,2,4,4,4,5,5,5,5}, 11, &resultSize);\n\n int expected2[] = {7, 8, 9, 10};\n\n assert(resultSize == 4);\n\n for (int i = 0; i < 4; i++) {\n\n assert(result[i] == expected2[i]);\n\n }\n\n\n\n result = func0((int[]){2,1,5,6,8,3,4,9,10,11,8,12}, 12, &resultSize);\n\n int expected3[] = {11};\n\n assert(resultSize == 1 && result[0] == expected3[0]);\n\n\n\n printf(\"All tests passed.\\n\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov (%rdi),%ecx\ncmp $0x1,%esi\njle 11c8 \nlea 0x4(%rdi),%rax\nlea -0x2(%rsi),%r8d\nlea 0x8(%rdi,%r8,4),%r9\nmov (%rax),%r8d\ncmp %r8d,%ecx\ncmovl %r8d,%ecx\nadd $0x4,%rax\ncmp %r9,%rax\njne 11a1 \nmov $0x0,%eax\nmov $0x0,%r8d\nlea 0x2e7a(%rip),%r10\njmp 11e3 \nje 11b4 \nmov $0x0,%r8d\nmov %r8d,(%rdx)\nlea 0x2e66(%rip),%rax\nretq\nadd $0x1,%rax\ncmp %eax,%esi\njle 11d0 \ncmp %ecx,(%rdi,%rax,4)\njne 11db \nmovslq %r8d,%r9\nmov %eax,(%r10,%r9,4)\nlea 0x1(%r8),%r8d\njmp 11db \n", + "ida_asm": "func0:\nendbr64\nmov r8, rdi\nmov ecx, [rdi]\ncmp esi, 1\njle short loc_11C9\nlea rax, [rdi+4]\nlea edi, [rsi-2]\nlea r9, [r8+rdi*4+8]\nloc_11A3:\nmov edi, [rax]\ncmp ecx, edi\ncmovl ecx, edi\nadd rax, 4\ncmp rax, r9\njnz short loc_11A3\nloc_11B3:\nmovsxd rsi, esi\nmov eax, 0\nmov edi, 0\nlea r10, max_result_1\njmp short loc_11E5\nloc_11C9:\ntest esi, esi\njg short loc_11B3\nmov edi, 0\nloc_11D2:\nmov [rdx], edi\nlea rax, max_result_1\nretn\nloc_11DC:\nadd rax, 1\ncmp rsi, rax\njz short loc_11D2\nloc_11E5:\ncmp [r8+rax*4], ecx\njnz short loc_11DC\nmovsxd r9, edi\nmov [r10+r9*4], eax\nlea edi, [rdi+1]\njmp short loc_11DC", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2, _DWORD *a3)\n{\n int v4; // ecx\n int *v5; // rax\n __int64 v6; // rax\n int v7; // edi\n\n v4 = *a1;\n if ( a2 <= 1 )\n {\n if ( a2 <= 0 )\n {\n v7 = 0;\n goto LABEL_9;\n }\n }\n else\n {\n v5 = a1 + 1;\n do\n {\n if ( v4 < *v5 )\n v4 = *v5;\n ++v5;\n }\n while ( v5 != &a1[a2 - 2 + 2] );\n }\n v6 = 0LL;\n v7 = 0;\n do\n {\n if ( a1[v6] == v4 )\n max_result_1[v7++] = v6;\n ++v6;\n }\n while ( a2 != v6 );\nLABEL_9:\n *a3 = v7;\n return max_result_1;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\nmov r8, rdi\nmov ecx, [rdi]\ncmp esi, 1\njle short loc_11C9\nlea rax, [rdi+4]\nlea edi, [rsi-2]\nlea r9, [r8+rdi*4+8]\nloc_11A3:\nmov edi, [rax]\ncmp ecx, edi\ncmovl ecx, edi\nadd rax, 4\ncmp rax, r9\njnz short loc_11A3\nloc_11B3:\nmovsxd rsi, esi\nmov eax, 0\nmov edi, 0\nlea r10, unk_4040\njmp short loc_11E5\nloc_11C9:\ntest esi, esi\njg short loc_11B3\nmov edi, 0\nloc_11D2:\nmov [rdx], edi\nlea rax, unk_4040\nretn\nloc_11DC:\nadd rax, 1\ncmp rsi, rax\njz short loc_11D2\nloc_11E5:\ncmp [r8+rax*4], ecx\njnz short loc_11DC\nmovsxd r9, edi\nmov [r10+r9*4], eax\nlea edi, [rdi+1]\njmp short loc_11DC", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1189(int *a1, int a2, _DWORD *a3)\n{\n int v4; // ecx\n int *v5; // rax\n __int64 v6; // rax\n int v7; // edi\n\n v4 = *a1;\n if ( a2 <= 1 )\n {\n if ( a2 <= 0 )\n {\n v7 = 0;\n goto LABEL_9;\n }\n }\n else\n {\n v5 = a1 + 1;\n do\n {\n if ( v4 < *v5 )\n v4 = *v5;\n ++v5;\n }\n while ( v5 != &a1[a2 - 2 + 2] );\n }\n v6 = 0LL;\n v7 = 0;\n do\n {\n if ( a1[v6] == v4 )\n dword_4040[v7++] = v6;\n ++v6;\n }\n while ( a2 != v6 );\nLABEL_9:\n *a3 = v7;\n return dword_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1189(int *a1, int a2, uint32_t *a3) {\n int v4;\n int *v5;\n long long v6;\n int v7;\n v4 = *a1;\n if (a2 <= 1) {\n if (a2 <= 0) {\n v7 = 0;\n goto LABEL_9;\n }\n } else {\n v5 = a1 + 1;\n do {\n if (v4 < *v5) v4 = *v5;\n ++v5;\n } while (v5 != &a1[a2 - 2 + 2]);\n }\n v6 = 0LL;\n v7 = 0;\n do {\n if (a1[v6] == v4) dword_4040[v7++] = v6;\n ++v6;\n } while (a2 != v6);\nLABEL_9:\n *a3 = v7;\n return dword_4040;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2, uint32_t *a3) {\n int v4;\n int *v5;\n long long v6;\n int v7;\n v4 = *a1;\n if (a2 <= 1) {\n if (a2 <= 0) {\n v7 = 0;\n goto LABEL_9;\n }\n } else {\n v5 = a1 + 1;\n do {\n if (v4 < *v5) v4 = *v5;\n ++v5;\n } while (v5 != &a1[a2 - 2 + 2]);\n }\n v6 = 0LL;\n v7 = 0;\n do {\n if (a1[v6] == v4) max_result_1[v7++] = v6;\n ++v6;\n } while (a2 != v6);\nLABEL_9:\n *a3 = v7;\n return max_result_1;\n}" + }, + { + "index": 200, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int* list1, int size, int* resultSize) {\n int max_val = list1[0];\n for (int i = 1; i < size; i++) {\n if (list1[i] > max_val) {\n max_val = list1[i];\n }\n }\n static int max_result[100];\n int count = 0;\n for (int i = 0; i < size; i++) {\n if (list1[i] == max_val) {\n max_result[count++] = i;\n }\n }\n *resultSize = count;\n return max_result;\n}", + "test": "int main() {\n\n int resultSize;\n\n int* result;\n\n\n\n result = func0((int[]){12,33,23,10,67,89,45,667,23,12,11,10,54}, 13, &resultSize);\n\n int expected1[] = {7};\n\n assert(resultSize == 1 && result[0] == expected1[0]);\n\n\n\n result = func0((int[]){1,2,2,2,4,4,4,5,5,5,5}, 11, &resultSize);\n\n int expected2[] = {7, 8, 9, 10};\n\n assert(resultSize == 4);\n\n for (int i = 0; i < 4; i++) {\n\n assert(result[i] == expected2[i]);\n\n }\n\n\n\n result = func0((int[]){2,1,5,6,8,3,4,9,10,11,8,12}, 12, &resultSize);\n\n int expected3[] = {11};\n\n assert(resultSize == 1 && result[0] == expected3[0]);\n\n\n\n printf(\"All tests passed.\\n\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov (%rdi),%r9d\ncmp $0x1,%esi\njle 1530 \nlea -0x2(%rsi),%ecx\nlea 0x4(%rdi),%rax\nlea 0x8(%rdi,%rcx,4),%r10\nmov %r9d,%ecx\nnopl 0x0(%rax,%rax,1)\nmov (%rax),%r8d\ncmp %r8d,%ecx\ncmovl %r8d,%ecx\nadd $0x4,%rax\ncmp %r10,%rax\njne 14e0 \nxor %eax,%eax\nxor %r8d,%r8d\nlea 0x2b41(%rip),%r10\njmp 150c \nnopl 0x0(%rax)\nmov (%rdi,%rax,4),%r9d\ncmp %r9d,%ecx\njne 151c \nmovslq %r8d,%r9\nadd $0x1,%r8d\nmov %eax,(%r10,%r9,4)\nadd $0x1,%rax\ncmp %eax,%esi\njg 1508 \nmov %r8d,(%rdx)\nlea 0x2b12(%rip),%rax\nretq\nje 1540 \nxor %r8d,%r8d\nlea 0x2b04(%rip),%rax\nmov %r8d,(%rdx)\nretq\nmov %r9d,%ecx\njmp 14f3 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmov r10, rdx\nmov rcx, rdi\nmov edx, [rdi]\ncmp esi, 1\njle short loc_1410\nlea rax, [rdi+4]\nlea edi, [rsi-2]\nlea r8, [rcx+rdi*4+8]\nmov rdi, r8\nsub rdi, rax\nand edi, 4\njz short loc_13C0\nmov eax, [rax]\ncmp edx, eax\ncmovl edx, eax\nlea rax, [rcx+8]\ncmp rax, r8\njz short loc_13D8\nnop dword ptr [rax+rax+00000000h]\nloc_13C0:\nmov edi, [rax]\ncmp edx, edi\ncmovl edx, edi\nmov edi, [rax+4]\ncmp edx, edi\ncmovl edx, edi\nadd rax, 8\ncmp rax, r8\njnz short loc_13C0\nloc_13D8:\nmovsxd rsi, esi\nxor eax, eax\nlea r9, max_result_1\nxor edi, edi\nnop word ptr [rax+rax+00000000h]\nloc_13F0:\ncmp [rcx+rax*4], edx\njnz short loc_13FF\nmovsxd r8, edi\nadd edi, 1\nmov [r9+r8*4], eax\nloc_13FF:\nadd rax, 1\ncmp rsi, rax\njnz short loc_13F0\nmov [r10], edi\nmov rax, r9\nretn\nloc_1410:\njz short loc_13D8\nxor edi, edi\nlea r9, max_result_1\nmov [r10], edi\nmov rax, r9\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2, _DWORD *a3)\n{\n int v5; // edx\n int *v6; // rax\n __int64 v7; // r8\n int v8; // eax\n __int64 v9; // rax\n int v10; // edi\n __int64 v11; // r8\n\n v5 = *a1;\n if ( a2 <= 1 )\n {\n if ( a2 != 1 )\n {\n *a3 = 0;\n return max_result_1;\n }\n }\n else\n {\n v6 = a1 + 1;\n v7 = (__int64)&a1[a2 - 2 + 2];\n if ( ((4 * ((_BYTE)a2 - 2) + 4) & 4) == 0 )\n goto LABEL_20;\n v8 = *v6;\n if ( v5 < v8 )\n v5 = v8;\n v6 = a1 + 2;\n if ( a1 + 2 != (int *)v7 )\n {\nLABEL_20:\n do\n {\n if ( v5 < *v6 )\n v5 = *v6;\n if ( v5 < v6[1] )\n v5 = v6[1];\n v6 += 2;\n }\n while ( v6 != (int *)v7 );\n }\n }\n v9 = 0LL;\n v10 = 0;\n do\n {\n if ( a1[v9] == v5 )\n {\n v11 = v10++;\n max_result_1[v11] = v9;\n }\n ++v9;\n }\n while ( a2 != v9 );\n *a3 = v10;\n return max_result_1;\n}", + "ida_strip_asm": "sub_1380:\nendbr64\nmov r10, rdx\nmov rcx, rdi\nmov edx, [rdi]\ncmp esi, 1\njle short loc_1410\nlea rax, [rdi+4]\nlea edi, [rsi-2]\nlea r8, [rcx+rdi*4+8]\nmov rdi, r8\nsub rdi, rax\nand edi, 4\njz short loc_13C0\nmov eax, [rax]\ncmp edx, eax\ncmovl edx, eax\nlea rax, [rcx+8]\ncmp rax, r8\njz short loc_13D8\nnop dword ptr [rax+rax+00000000h]\nloc_13C0:\nmov edi, [rax]\ncmp edx, edi\ncmovl edx, edi\nmov edi, [rax+4]\ncmp edx, edi\ncmovl edx, edi\nadd rax, 8\ncmp rax, r8\njnz short loc_13C0\nloc_13D8:\nmovsxd rsi, esi\nxor eax, eax\nlea r9, unk_4040\nxor edi, edi\nnop word ptr [rax+rax+00000000h]\nloc_13F0:\ncmp [rcx+rax*4], edx\njnz short loc_13FF\nmovsxd r8, edi\nadd edi, 1\nmov [r9+r8*4], eax\nloc_13FF:\nadd rax, 1\ncmp rsi, rax\njnz short loc_13F0\nmov [r10], edi\nmov rax, r9\nretn\nloc_1410:\njz short loc_13D8\nxor edi, edi\nlea r9, unk_4040\nmov [r10], edi\nmov rax, r9\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1380(int *a1, int a2, _DWORD *a3)\n{\n int v5; // edx\n int *v6; // rax\n __int64 v7; // r8\n int v8; // eax\n __int64 v9; // rax\n int v10; // edi\n __int64 v11; // r8\n\n v5 = *a1;\n if ( a2 <= 1 )\n {\n if ( a2 != 1 )\n {\n *a3 = 0;\n return dword_4040;\n }\n }\n else\n {\n v6 = a1 + 1;\n v7 = (__int64)&a1[a2 - 2 + 2];\n if ( ((4 * ((_BYTE)a2 - 2) + 4) & 4) == 0 )\n goto LABEL_20;\n v8 = *v6;\n if ( v5 < v8 )\n v5 = v8;\n v6 = a1 + 2;\n if ( a1 + 2 != (int *)v7 )\n {\nLABEL_20:\n do\n {\n if ( v5 < *v6 )\n v5 = *v6;\n if ( v5 < v6[1] )\n v5 = v6[1];\n v6 += 2;\n }\n while ( v6 != (int *)v7 );\n }\n }\n v9 = 0LL;\n v10 = 0;\n do\n {\n if ( a1[v9] == v5 )\n {\n v11 = v10++;\n dword_4040[v11] = v9;\n }\n ++v9;\n }\n while ( a2 != v9 );\n *a3 = v10;\n return dword_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1380(int *a1, int a2, uint32_t *a3) {\n int v5;\n int *v6;\n long long v7;\n int v8;\n long long v9;\n int v10;\n long long v11;\n v5 = *a1;\n if (a2 <= 1) {\n if (a2 != 1) {\n *a3 = 0;\n return dword_4040;\n }\n } else {\n v6 = a1 + 1;\n v7 = (long long)&a1[a2 - 2 + 2];\n if (((4 * ((uint8_t)a2 - 2) + 4) & 4) == 0) goto LABEL_20;\n v8 = *v6;\n if (v5 < v8) v5 = v8;\n v6 = a1 + 2;\n if (a1 + 2 != (int *)v7) {\n LABEL_20:\n do {\n if (v5 < *v6) v5 = *v6;\n if (v5 < v6[1]) v5 = v6[1];\n v6 += 2;\n } while (v6 != (int *)v7);\n }\n }\n v9 = 0LL;\n v10 = 0;\n do {\n if (a1[v9] == v5) {\n v11 = v10++;\n dword_4040[v11] = v9;\n }\n ++v9;\n } while (a2 != v9);\n *a3 = v10;\n return dword_4040;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2, uint32_t *a3) {\n int v5;\n int *v6;\n long long v7;\n int v8;\n long long v9;\n int v10;\n long long v11;\n v5 = *a1;\n if (a2 <= 1) {\n if (a2 != 1) {\n *a3 = 0;\n return max_result_1;\n }\n } else {\n v6 = a1 + 1;\n v7 = (long long)&a1[a2 - 2 + 2];\n if (((4 * ((uint8_t)a2 - 2) + 4) & 4) == 0) goto LABEL_20;\n v8 = *v6;\n if (v5 < v8) v5 = v8;\n v6 = a1 + 2;\n if (a1 + 2 != (int *)v7) {\n LABEL_20:\n do {\n if (v5 < *v6) v5 = *v6;\n if (v5 < v6[1]) v5 = v6[1];\n v6 += 2;\n } while (v6 != (int *)v7);\n }\n }\n v9 = 0LL;\n v10 = 0;\n do {\n if (a1[v9] == v5) {\n v11 = v10++;\n max_result_1[v11] = v9;\n }\n ++v9;\n } while (a2 != v9);\n *a3 = v10;\n return max_result_1;\n}" + }, + { + "index": 201, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char *lst[], int size) {\n for (int i = 1; i < size; i++) {\n if (strcmp(lst[0], lst[i]) != 0) {\n return 0;\n }\n }\n return 1;\n}", + "test": "int main() {\n\n char *lst1[] = {\"one\", \"one\", \"one\"};\n\n char *lst2[] = {\"one\", \"Two\", \"Three\"};\n\n char *lst3[] = {\"bigdata\", \"python\", \"Django\"};\n\n \n\n assert(func0(lst1, 3) == 1);\n\n assert(func0(lst2, 3) == 0);\n\n assert(func0(lst3, 3) == 0);\n\n \n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x1,-0x4(%rbp)\njmp 11fd \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rdx\nmov -0x18(%rbp),%rax\nmov (%rax),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10b0 \ntest %eax,%eax\nje 11f9 \nmov $0x0,%eax\njmp 120a \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11c5 \nmov $0x1,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 1\njmp short loc_11FD\nloc_11C5:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rdx, [rax]\nmov rax, [rbp+var_18]\nmov rax, [rax]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_11F9\nmov eax, 0\njmp short locret_120A\nloc_11F9:\nadd [rbp+var_4], 1\nloc_11FD:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11C5\nmov eax, 1\nlocret_120A:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char **a1, int a2)\n{\n int i; // [rsp+1Ch] [rbp-4h]\n\n for ( i = 1; i < a2; ++i )\n {\n if ( strcmp(*a1, a1[i]) )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 1\njmp short loc_11FD\nloc_11C5:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rdx, [rax]\nmov rax, [rbp+var_18]\nmov rax, [rax]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_11F9\nmov eax, 0\njmp short locret_120A\nloc_11F9:\nadd [rbp+var_4], 1\nloc_11FD:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11C5\nmov eax, 1\nlocret_120A:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(const char **a1, int a2)\n{\n int i; // [rsp+1Ch] [rbp-4h]\n\n for ( i = 1; i < a2; ++i )\n {\n if ( strcmp(*a1, a1[i]) )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(const char **a1, int a2) {\n int i;\n for (i = 1; i < a2; ++i) {\n if (strcmp(*a1, a1[i])) return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(const char **a1, int a2) {\n int i;\n for (i = 1; i < a2; ++i) {\n if (strcmp(*a1, a1[i])) return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": 201, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char *lst[], int size) {\n for (int i = 1; i < size; i++) {\n if (strcmp(lst[0], lst[i]) != 0) {\n return 0;\n }\n }\n return 1;\n}", + "test": "int main() {\n\n char *lst1[] = {\"one\", \"one\", \"one\"};\n\n char *lst2[] = {\"one\", \"Two\", \"Three\"};\n\n char *lst3[] = {\"bigdata\", \"python\", \"Django\"};\n\n \n\n assert(func0(lst1, 3) == 1);\n\n assert(func0(lst2, 3) == 0);\n\n assert(func0(lst3, 3) == 0);\n\n \n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%esi\njle 11e4 \npush %r12\npush %rbp\npush %rbx\nmov (%rdi),%rbp\nlea 0x8(%rdi),%rbx\nlea -0x2(%rsi),%eax\nlea 0x10(%rdi,%rax,8),%r12\nmov (%rbx),%rsi\nmov %rbp,%rdi\ncallq 10b0 \ntest %eax,%eax\njne 11ea \nadd $0x8,%rbx\ncmp %r12,%rbx\njne 11c5 \nmov $0x1,%eax\njmp 11ef \nmov $0x1,%eax\nretq\nmov $0x0,%eax\npop %rbx\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\ncmp esi, 1\njle short loc_11E4\npush r12\npush rbp\npush rbx\nmov rbp, [rdi]\nlea rbx, [rdi+8]\nlea eax, [rsi-2]\nlea r12, [rdi+rax*8+10h]\nloc_11C5:\nmov rsi, [rbx]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njnz short loc_11EA\nadd rbx, 8\ncmp rbx, r12\njnz short loc_11C5\nmov eax, 1\njmp short loc_11EF\nloc_11E4:\nmov eax, 1\nretn\nloc_11EA:\nmov eax, 0\nloc_11EF:\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char **a1, int a2)\n{\n const char *v2; // rbp\n const char **v3; // rbx\n\n if ( a2 <= 1 )\n return 1LL;\n v2 = *a1;\n v3 = a1 + 1;\n while ( !strcmp(v2, *v3) )\n {\n if ( ++v3 == &a1[(unsigned int)(a2 - 2) + 2] )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\ncmp esi, 1\njle short loc_11E4\npush r12\npush rbp\npush rbx\nmov rbp, [rdi]\nlea rbx, [rdi+8]\nlea eax, [rsi-2]\nlea r12, [rdi+rax*8+10h]\nloc_11C5:\nmov rsi, [rbx]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njnz short loc_11EA\nadd rbx, 8\ncmp rbx, r12\njnz short loc_11C5\nmov eax, 1\njmp short loc_11EF\nloc_11E4:\nmov eax, 1\nretn\nloc_11EA:\nmov eax, 0\nloc_11EF:\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(const char **a1, int a2)\n{\n const char *v2; // rbp\n const char **v3; // rbx\n\n if ( a2 <= 1 )\n return 1LL;\n v2 = *a1;\n v3 = a1 + 1;\n while ( !strcmp(v2, *v3) )\n {\n if ( ++v3 == &a1[(unsigned int)(a2 - 2) + 2] )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(const char **a1, int a2) {\n const char *v2;\n const char **v3;\n if (a2 <= 1) return 1LL;\n v2 = *a1;\n v3 = a1 + 1;\n while (!strcmp(v2, *v3)) {\n if (++v3 == &a1[(unsigned int)(a2 - 2) + 2]) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(const char **a1, int a2) {\n const char *v2;\n const char **v3;\n if (a2 <= 1) return 1LL;\n v2 = *a1;\n v3 = a1 + 1;\n while (!strcmp(v2, *v3)) {\n if (++v3 == &a1[(unsigned int)(a2 - 2) + 2]) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 201, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char *lst[], int size) {\n for (int i = 1; i < size; i++) {\n if (strcmp(lst[0], lst[i]) != 0) {\n return 0;\n }\n }\n return 1;\n}", + "test": "int main() {\n\n char *lst1[] = {\"one\", \"one\", \"one\"};\n\n char *lst2[] = {\"one\", \"Two\", \"Three\"};\n\n char *lst3[] = {\"bigdata\", \"python\", \"Django\"};\n\n \n\n assert(func0(lst1, 3) == 1);\n\n assert(func0(lst2, 3) == 0);\n\n assert(func0(lst3, 3) == 0);\n\n \n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%esi\njle 132a \nlea -0x2(%rsi),%eax\npush %r12\nlea 0x10(%rdi,%rax,8),%r12\npush %rbp\npush %rbx\nlea 0x8(%rdi),%rbx\nmov (%rdi),%rbp\njmp 1309 \nxchg %ax,%ax\nadd $0x8,%rbx\ncmp %r12,%rbx\nje 1320 \nmov (%rbx),%rsi\nmov %rbp,%rdi\ncallq 10b0 \ntest %eax,%eax\nje 1300 \npop %rbx\nxor %eax,%eax\npop %rbp\npop %r12\nretq\npop %rbx\nmov $0x1,%eax\npop %rbp\npop %r12\nretq\nmov $0x1,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ncmp esi, 1\njle short loc_133A\nlea eax, [rsi-2]\npush r12\nlea r12, [rdi+rax*8+10h]\npush rbp\npush rbx\nlea rbx, [rdi+8]\nmov rbp, [rdi]\njmp short loc_1319\nloc_1310:\nadd rbx, 8\ncmp rbx, r12\njz short loc_1330\nloc_1319:\nmov rsi, [rbx]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njz short loc_1310\npop rbx\nxor eax, eax\npop rbp\npop r12\nretn\nloc_1330:\npop rbx\nmov eax, 1\npop rbp\npop r12\nretn\nloc_133A:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char **a1, int a2)\n{\n const char **v2; // rbx\n const char *v3; // rbp\n\n if ( a2 <= 1 )\n return 1LL;\n v2 = a1 + 1;\n v3 = *a1;\n do\n {\n if ( strcmp(v3, *v2) )\n return 0LL;\n ++v2;\n }\n while ( v2 != &a1[(unsigned int)(a2 - 2) + 2] );\n return 1LL;\n}", + "ida_strip_asm": "sub_12F0:\nendbr64\ncmp esi, 1\njle short loc_133A\nlea eax, [rsi-2]\npush r12\nlea r12, [rdi+rax*8+10h]\npush rbp\npush rbx\nlea rbx, [rdi+8]\nmov rbp, [rdi]\njmp short loc_1319\nloc_1310:\nadd rbx, 8\ncmp rbx, r12\njz short loc_1330\nloc_1319:\nmov rsi, [rbx]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njz short loc_1310\npop rbx\nxor eax, eax\npop rbp\npop r12\nretn\nloc_1330:\npop rbx\nmov eax, 1\npop rbp\npop r12\nretn\nloc_133A:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12F0(const char **a1, int a2)\n{\n const char **v2; // rbx\n const char *v3; // rbp\n\n if ( a2 <= 1 )\n return 1LL;\n v2 = a1 + 1;\n v3 = *a1;\n do\n {\n if ( strcmp(v3, *v2) )\n return 0LL;\n ++v2;\n }\n while ( v2 != &a1[(unsigned int)(a2 - 2) + 2] );\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12F0(const char **a1, int a2) {\n const char **v2;\n const char *v3;\n if (a2 <= 1) return 1LL;\n v2 = a1 + 1;\n v3 = *a1;\n do {\n if (strcmp(v3, *v2)) return 0LL;\n ++v2;\n } while (v2 != &a1[(unsigned int)(a2 - 2) + 2]);\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(const char **a1, int a2) {\n const char **v2;\n const char *v3;\n if (a2 <= 1) return 1LL;\n v2 = a1 + 1;\n v3 = *a1;\n do {\n if (strcmp(v3, *v2)) return 0LL;\n ++v2;\n } while (v2 != &a1[(unsigned int)(a2 - 2) + 2]);\n return 1LL;\n}" + }, + { + "index": 201, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char *lst[], int size) {\n for (int i = 1; i < size; i++) {\n if (strcmp(lst[0], lst[i]) != 0) {\n return 0;\n }\n }\n return 1;\n}", + "test": "int main() {\n\n char *lst1[] = {\"one\", \"one\", \"one\"};\n\n char *lst2[] = {\"one\", \"Two\", \"Three\"};\n\n char *lst3[] = {\"bigdata\", \"python\", \"Django\"};\n\n \n\n assert(func0(lst1, 3) == 1);\n\n assert(func0(lst2, 3) == 0);\n\n assert(func0(lst3, 3) == 0);\n\n \n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%esi\njle 134a \nlea -0x2(%rsi),%eax\npush %r12\nlea 0x10(%rdi,%rax,8),%r12\npush %rbp\npush %rbx\nlea 0x8(%rdi),%rbx\nmov (%rdi),%rbp\njmp 1329 \nxchg %ax,%ax\nadd $0x8,%rbx\ncmp %r12,%rbx\nje 1340 \nmov (%rbx),%rsi\nmov %rbp,%rdi\ncallq 10b0 \ntest %eax,%eax\nje 1320 \npop %rbx\nxor %eax,%eax\npop %rbp\npop %r12\nretq\npop %rbx\nmov $0x1,%eax\npop %rbp\npop %r12\nretq\nmov $0x1,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ncmp esi, 1\njle short loc_133A\nlea eax, [rsi-2]\npush r12\nlea r12, [rdi+rax*8+10h]\npush rbp\npush rbx\nlea rbx, [rdi+8]\nmov rbp, [rdi]\njmp short loc_1319\nloc_1310:\nadd rbx, 8\ncmp rbx, r12\njz short loc_1330\nloc_1319:\nmov rsi, [rbx]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njz short loc_1310\npop rbx\nxor eax, eax\npop rbp\npop r12\nretn\nloc_1330:\npop rbx\nmov eax, 1\npop rbp\npop r12\nretn\nloc_133A:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char **a1, int a2)\n{\n const char **v2; // rbx\n const char *v3; // rbp\n\n if ( a2 <= 1 )\n return 1LL;\n v2 = a1 + 1;\n v3 = *a1;\n do\n {\n if ( strcmp(v3, *v2) )\n return 0LL;\n ++v2;\n }\n while ( v2 != &a1[(unsigned int)(a2 - 2) + 2] );\n return 1LL;\n}", + "ida_strip_asm": "sub_12F0:\nendbr64\ncmp esi, 1\njle short loc_133A\nlea eax, [rsi-2]\npush r12\nlea r12, [rdi+rax*8+10h]\npush rbp\npush rbx\nlea rbx, [rdi+8]\nmov rbp, [rdi]\njmp short loc_1319\nloc_1310:\nadd rbx, 8\ncmp rbx, r12\njz short loc_1330\nloc_1319:\nmov rsi, [rbx]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njz short loc_1310\npop rbx\nxor eax, eax\npop rbp\npop r12\nretn\nloc_1330:\npop rbx\nmov eax, 1\npop rbp\npop r12\nretn\nloc_133A:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12F0(const char **a1, int a2)\n{\n const char **v2; // rbx\n const char *v3; // rbp\n\n if ( a2 <= 1 )\n return 1LL;\n v2 = a1 + 1;\n v3 = *a1;\n do\n {\n if ( strcmp(v3, *v2) )\n return 0LL;\n ++v2;\n }\n while ( v2 != &a1[(unsigned int)(a2 - 2) + 2] );\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12F0(const char **a1, int a2) {\n const char **v2;\n const char *v3;\n if (a2 <= 1) return 1LL;\n v2 = a1 + 1;\n v3 = *a1;\n do {\n if (strcmp(v3, *v2)) return 0LL;\n ++v2;\n } while (v2 != &a1[(unsigned int)(a2 - 2) + 2]);\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(const char **a1, int a2) {\n const char **v2;\n const char *v3;\n if (a2 <= 1) return 1LL;\n v2 = a1 + 1;\n v3 = *a1;\n do {\n if (strcmp(v3, *v2)) return 0LL;\n ++v2;\n } while (v2 != &a1[(unsigned int)(a2 - 2) + 2]);\n return 1LL;\n}" + }, + { + "index": 202, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* str1) {\n static char str2[100];\n int j = 0;\n for (int i = 1; i <= strlen(str1); i++) {\n if (i % 2 != 0) {\n str2[j++] = str1[i - 1];\n }\n }\n str2[j] = '\\0';\n return str2;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"python\"), \"pto\") == 0);\n\n assert(strcmp(func0(\"program\"), \"porm\") == 0);\n\n assert(strcmp(func0(\"language\"), \"lnug\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x28,%rsp\nmov %rdi,-0x28(%rbp)\nmovl $0x0,-0x18(%rbp)\nmovl $0x1,-0x14(%rbp)\njmp 11e1 \nmov -0x14(%rbp),%eax\nand $0x1,%eax\ntest %eax,%eax\nje 11dd \nmov -0x14(%rbp),%eax\ncltq\nlea -0x1(%rax),%rdx\nmov -0x28(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x18(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x18(%rbp)\nmovzbl (%rcx),%edx\ncltq\nlea 0x2e66(%rip),%rcx\nmov %dl,(%rax,%rcx,1)\naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\nmovslq %eax,%rbx\nmov -0x28(%rbp),%rax\nmov %rax,%rdi\ncallq 1070 \ncmp %rax,%rbx\njbe 11aa \nmov -0x18(%rbp),%eax\ncltq\nlea 0x2e3c(%rip),%rdx\nmovb $0x0,(%rax,%rdx,1)\nlea 0x2e31(%rip),%rax\nadd $0x28,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+s], rdi\nmov [rbp+var_18], 0\nmov [rbp+var_14], 1\njmp short loc_11E1\nloc_11AA:\nmov eax, [rbp+var_14]\nand eax, 1\ntest eax, eax\njz short loc_11DD\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\nmovzx edx, byte ptr [rcx]\ncdqe\nlea rcx, str2_1\nmov [rax+rcx], dl\nloc_11DD:\nadd [rbp+var_14], 1\nloc_11E1:\nmov eax, [rbp+var_14]\nmovsxd rbx, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rax, rbx\njnb short loc_11AA\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, str2_1\nmov byte ptr [rax+rdx], 0\nlea rax, str2_1\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1)\n{\n int v1; // eax\n int v3; // [rsp+18h] [rbp-18h]\n int i; // [rsp+1Ch] [rbp-14h]\n\n v3 = 0;\n for ( i = 1; strlen(a1) >= i; ++i )\n {\n if ( (i & 1) != 0 )\n {\n v1 = v3++;\n str2_1[v1] = a1[i - 1];\n }\n }\n str2_1[v3] = 0;\n return str2_1;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+s], rdi\nmov [rbp+var_18], 0\nmov [rbp+var_14], 1\njmp short loc_11E1\nloc_11AA:\nmov eax, [rbp+var_14]\nand eax, 1\ntest eax, eax\njz short loc_11DD\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\nmovzx edx, byte ptr [rcx]\ncdqe\nlea rcx, unk_4040\nmov [rax+rcx], dl\nloc_11DD:\nadd [rbp+var_14], 1\nloc_11E1:\nmov eax, [rbp+var_14]\nmovsxd rbx, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rax, rbx\njnb short loc_11AA\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, unk_4040\nmov byte ptr [rax+rdx], 0\nlea rax, unk_4040\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1189(const char *a1)\n{\n int v1; // eax\n int v3; // [rsp+18h] [rbp-18h]\n int i; // [rsp+1Ch] [rbp-14h]\n\n v3 = 0;\n for ( i = 1; strlen(a1) >= i; ++i )\n {\n if ( (i & 1) != 0 )\n {\n v1 = v3++;\n byte_4040[v1] = a1[i - 1];\n }\n }\n byte_4040[v3] = 0;\n return byte_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1189(const char *a1) {\n int v1;\n int v3;\n int i;\n v3 = 0;\n for (i = 1; strlen(a1) >= i; ++i) {\n if ((i & 1) != 0) {\n v1 = v3++;\n byte_4040[v1] = a1[i - 1];\n }\n }\n byte_4040[v3] = 0;\n return byte_4040;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1) {\n int v1;\n int v3;\n int i;\n v3 = 0;\n for (i = 1; strlen(a1) >= i; ++i) {\n if ((i & 1) != 0) {\n v1 = v3++;\n str2_1[v1] = a1[i - 1];\n }\n }\n str2_1[v3] = 0;\n return str2_1;\n}" + }, + { + "index": 202, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* str1) {\n static char str2[100];\n int j = 0;\n for (int i = 1; i <= strlen(str1); i++) {\n if (i % 2 != 0) {\n str2[j++] = str1[i - 1];\n }\n }\n str2[j] = '\\0';\n return str2;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"python\"), \"pto\") == 0);\n\n assert(strcmp(func0(\"program\"), \"porm\") == 0);\n\n assert(strcmp(func0(\"language\"), \"lnug\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%r8\nmov $0x1,%edx\nmov $0x0,%esi\nmov $0xffffffffffffffff,%r9\nmov $0x0,%eax\nlea 0x2ed3(%rip),%r10\njmp 1173 \nadd $0x1,%rdx\nmov %r9,%rcx\nmov %r8,%rdi\nrepnz scas %es:(%rdi),%al\nnot %rcx\nsub $0x1,%rcx\ncmp %rdx,%rcx\njb 119e \ntest $0x1,%dl\nje 116f \nmovzbl -0x1(%r8,%rdx,1),%edi\nmovslq %esi,%rcx\nmov %dil,(%r10,%rcx,1)\nlea 0x1(%rsi),%esi\njmp 116f \nlea 0x2e9b(%rip),%rax\nmovslq %esi,%rsi\nmovb $0x0,(%rax,%rsi,1)\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12, rdi\nmov ebx, 1\nmov ebp, 0\nlea r13, str2_1\njmp short loc_11B1\nloc_11AD:\nadd rbx, 1\nloc_11B1:\nmov rdi, r12; s\ncall _strlen\ncmp rax, rbx\njb short loc_11D6\ntest bl, 1\njz short loc_11AD\nmovzx edx, byte ptr [r12+rbx-1]\nmovsxd rax, ebp\nmov [r13+rax+0], dl\nlea ebp, [rbp+1]\njmp short loc_11AD\nloc_11D6:\nlea rax, str2_1\nmovsxd rbp, ebp\nmov byte ptr [rax+rbp], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(char *s)\n{\n size_t v1; // rbx\n int v2; // ebp\n _BYTE *result; // rax\n\n v1 = 1LL;\n v2 = 0;\n while ( strlen(s) >= v1 )\n {\n if ( (v1 & 1) != 0 )\n str2_1[v2++] = s[v1 - 1];\n ++v1;\n }\n result = str2_1;\n str2_1[v2] = 0;\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12, rdi\nmov ebx, 1\nmov ebp, 0\nlea r13, unk_4040\njmp short loc_11B1\nloc_11AD:\nadd rbx, 1\nloc_11B1:\nmov rdi, r12; s\ncall _strlen\ncmp rax, rbx\njb short loc_11D6\ntest bl, 1\njz short loc_11AD\nmovzx edx, byte ptr [r12+rbx-1]\nmovsxd rax, ebp\nmov [r13+rax+0], dl\nlea ebp, [rbp+1]\njmp short loc_11AD\nloc_11D6:\nlea rax, unk_4040\nmovsxd rbp, ebp\nmov byte ptr [rax+rbp], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1189(char *s)\n{\n size_t v1; // rbx\n int v2; // ebp\n _BYTE *result; // rax\n\n v1 = 1LL;\n v2 = 0;\n while ( strlen(s) >= v1 )\n {\n if ( (v1 & 1) != 0 )\n byte_4040[v2++] = s[v1 - 1];\n ++v1;\n }\n result = byte_4040;\n byte_4040[v2] = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1189(char *s) {\n unsigned int v1;\n int v2;\n uint8_t *result;\n v1 = 1LL;\n v2 = 0;\n while (strlen(s) >= v1) {\n if ((v1 & 1) != 0) byte_4040[v2++] = s[v1 - 1];\n ++v1;\n }\n result = byte_4040;\n byte_4040[v2] = 0;\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(char *s) {\n unsigned int v1;\n int v2;\n uint8_t *result;\n v1 = 1LL;\n v2 = 0;\n while (strlen(s) >= v1) {\n if ((v1 & 1) != 0) str2_1[v2++] = s[v1 - 1];\n ++v1;\n }\n result = str2_1;\n str2_1[v2] = 0;\n return result;\n}" + }, + { + "index": 202, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* str1) {\n static char str2[100];\n int j = 0;\n for (int i = 1; i <= strlen(str1); i++) {\n if (i % 2 != 0) {\n str2[j++] = str1[i - 1];\n }\n }\n str2[j] = '\\0';\n return str2;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"python\"), \"pto\") == 0);\n\n assert(strcmp(func0(\"program\"), \"porm\") == 0);\n\n assert(strcmp(func0(\"language\"), \"lnug\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov %rdi,%r13\npush %r12\npush %rbp\nlea 0x2ddd(%rip),%rbp\npush %rbx\nmov $0x1,%ebx\nsub $0x8,%rsp\ncallq 1060 \nxor %edx,%edx\njmp 12a2 \nnopw %cs:0x0(%rax,%rax,1)\ntest $0x1,%bl\nje 129e \nmovzbl -0x1(%r13,%rbx,1),%eax\nlea 0x1(%rdx),%r12d\nmov %r13,%rdi\nmov %al,0x0(%rbp,%rdx,1)\ncallq 1060 \nmovslq %r12d,%rdx\nadd $0x1,%rbx\ncmp %rax,%rbx\njbe 1280 \nmovb $0x0,0x0(%rbp,%rdx,1)\nadd $0x8,%rsp\nlea 0x2d89(%rip),%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r13\nlea r13, str2_1\npush r12\nmov r12, rdi\npush rbp\nxor ebp, ebp\npush rbx\nmov ebx, 1\nsub rsp, 8\njmp short loc_12A2\nloc_1288:\ntest bl, 1\njz short loc_129E\nmovzx edx, byte ptr [r12+rbx-1]\nmovsxd rax, ebp\nadd ebp, 1\nmov [r13+rax+0], dl\nloc_129E:\nadd rbx, 1\nloc_12A2:\nmov rdi, r12; s\ncall _strlen\ncmp rax, rbx\njnb short loc_1288\nmovsxd rbp, ebp\nmov rax, r13\nmov byte ptr [r13+rbp+0], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(char *s)\n{\n int v1; // ebp\n size_t i; // rbx\n __int64 v3; // rax\n _BYTE *result; // rax\n\n v1 = 0;\n for ( i = 1LL; strlen(s) >= i; ++i )\n {\n if ( (i & 1) != 0 )\n {\n v3 = v1++;\n str2_1[v3] = s[i - 1];\n }\n }\n result = str2_1;\n str2_1[v1] = 0;\n return result;\n}", + "ida_strip_asm": "sub_1260:\nendbr64\npush r13\nlea r13, unk_4040\npush r12\nmov r12, rdi\npush rbp\nxor ebp, ebp\npush rbx\nmov ebx, 1\nsub rsp, 8\njmp short loc_12A2\nloc_1288:\ntest bl, 1\njz short loc_129E\nmovzx edx, byte ptr [r12+rbx-1]\nmovsxd rax, ebp\nadd ebp, 1\nmov [r13+rax+0], dl\nloc_129E:\nadd rbx, 1\nloc_12A2:\nmov rdi, r12; s\ncall _strlen\ncmp rax, rbx\njnb short loc_1288\nmovsxd rbp, ebp\nmov rax, r13\nmov byte ptr [r13+rbp+0], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1260(char *s)\n{\n int v1; // ebp\n size_t i; // rbx\n __int64 v3; // rax\n _BYTE *result; // rax\n\n v1 = 0;\n for ( i = 1LL; strlen(s) >= i; ++i )\n {\n if ( (i & 1) != 0 )\n {\n v3 = v1++;\n byte_4040[v3] = s[i - 1];\n }\n }\n result = byte_4040;\n byte_4040[v1] = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1260(char *s) {\n int v1;\n unsigned int i;\n long long v3;\n uint8_t *result;\n v1 = 0;\n for (i = 1LL; strlen(s) >= i; ++i) {\n if ((i & 1) != 0) {\n v3 = v1++;\n byte_4040[v3] = s[i - 1];\n }\n }\n result = byte_4040;\n byte_4040[v1] = 0;\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(char *s) {\n int v1;\n unsigned int i;\n long long v3;\n uint8_t *result;\n v1 = 0;\n for (i = 1LL; strlen(s) >= i; ++i) {\n if ((i & 1) != 0) {\n v3 = v1++;\n str2_1[v3] = s[i - 1];\n }\n }\n result = str2_1;\n str2_1[v1] = 0;\n return result;\n}" + }, + { + "index": 202, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* str1) {\n static char str2[100];\n int j = 0;\n for (int i = 1; i <= strlen(str1); i++) {\n if (i % 2 != 0) {\n str2[j++] = str1[i - 1];\n }\n }\n str2[j] = '\\0';\n return str2;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"python\"), \"pto\") == 0);\n\n assert(strcmp(func0(\"program\"), \"porm\") == 0);\n\n assert(strcmp(func0(\"language\"), \"lnug\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\nmov %rdi,%r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\ncallq 1060 \ntest %rax,%rax\nje 12d8 \nxor %edx,%edx\nmov $0x1,%ebx\nlea 0x2dc7(%rip),%rbp\nnopl 0x0(%rax)\ntest $0x1,%bl\nje 12ac \nmovzbl -0x1(%r12,%rbx,1),%eax\nmov %r12,%rdi\nlea 0x1(%rdx),%r13d\nadd $0x1,%rbx\nmov %al,0x0(%rbp,%rdx,1)\ncallq 1060 \ncmp %rax,%rbx\nja 12b8 \nmovslq %r13d,%rdx\ntest $0x1,%bl\njne 1285 \nadd $0x1,%rbx\ncmp %rax,%rbx\njbe 1280 \nmov %edx,%r13d\nmovslq %r13d,%r13\nlea 0x2d7e(%rip),%rax\nmovb $0x0,0x0(%rbp,%r13,1)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax,%rax,1)\nxor %r13d,%r13d\nlea 0x2d5e(%rip),%rbp\njmp 12b8 \nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r13\nlea r13, str2_1\npush r12\nmov r12, rdi\npush rbp\nxor ebp, ebp\npush rbx\nmov ebx, 1\nsub rsp, 8\njmp short loc_12A2\nloc_1288:\ntest bl, 1\njz short loc_129E\nmovzx edx, byte ptr [r12+rbx-1]\nmovsxd rax, ebp\nadd ebp, 1\nmov [r13+rax+0], dl\nloc_129E:\nadd rbx, 1\nloc_12A2:\nmov rdi, r12; s\ncall _strlen\ncmp rax, rbx\njnb short loc_1288\nmovsxd rbp, ebp\nmov rax, r13\nmov byte ptr [r13+rbp+0], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(char *s)\n{\n int v1; // ebp\n size_t i; // rbx\n __int64 v3; // rax\n _BYTE *result; // rax\n\n v1 = 0;\n for ( i = 1LL; strlen(s) >= i; ++i )\n {\n if ( (i & 1) != 0 )\n {\n v3 = v1++;\n str2_1[v3] = s[i - 1];\n }\n }\n result = str2_1;\n str2_1[v1] = 0;\n return result;\n}", + "ida_strip_asm": "sub_1260:\nendbr64\npush r13\nlea r13, unk_4040\npush r12\nmov r12, rdi\npush rbp\nxor ebp, ebp\npush rbx\nmov ebx, 1\nsub rsp, 8\njmp short loc_12A2\nloc_1288:\ntest bl, 1\njz short loc_129E\nmovzx edx, byte ptr [r12+rbx-1]\nmovsxd rax, ebp\nadd ebp, 1\nmov [r13+rax+0], dl\nloc_129E:\nadd rbx, 1\nloc_12A2:\nmov rdi, r12; s\ncall _strlen\ncmp rax, rbx\njnb short loc_1288\nmovsxd rbp, ebp\nmov rax, r13\nmov byte ptr [r13+rbp+0], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1260(char *s)\n{\n int v1; // ebp\n size_t i; // rbx\n __int64 v3; // rax\n _BYTE *result; // rax\n\n v1 = 0;\n for ( i = 1LL; strlen(s) >= i; ++i )\n {\n if ( (i & 1) != 0 )\n {\n v3 = v1++;\n byte_4040[v3] = s[i - 1];\n }\n }\n result = byte_4040;\n byte_4040[v1] = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1260(char *s) {\n int v1;\n unsigned int i;\n long long v3;\n uint8_t *result;\n v1 = 0;\n for (i = 1LL; strlen(s) >= i; ++i) {\n if ((i & 1) != 0) {\n v3 = v1++;\n byte_4040[v3] = s[i - 1];\n }\n }\n result = byte_4040;\n byte_4040[v1] = 0;\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(char *s) {\n int v1;\n unsigned int i;\n long long v3;\n uint8_t *result;\n v1 = 0;\n for (i = 1LL; strlen(s) >= i; ++i) {\n if ((i & 1) != 0) {\n v3 = v1++;\n str2_1[v3] = s[i - 1];\n }\n }\n result = str2_1;\n str2_1[v1] = 0;\n return result;\n}" + }, + { + "index": 203, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n1, int n2) {\n int x = n1 ^ n2;\n int setBits = 0;\n while (x > 0) {\n setBits += x & 1;\n x >>= 1;\n }\n return setBits;\n}", + "test": "int main() {\n\n assert(func0(4, 8) == 2);\n\n assert(func0(2, 4) == 2);\n\n assert(func0(1, 2) == 2);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov -0x14(%rbp),%eax\nxor -0x18(%rbp),%eax\nmov %eax,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 1175 \nmov -0x8(%rbp),%eax\nand $0x1,%eax\nadd %eax,-0x4(%rbp)\nsarl -0x8(%rbp)\ncmpl $0x0,-0x8(%rbp)\njg 1169 \nmov -0x4(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov eax, [rbp+var_14]\nxor eax, [rbp+var_18]\nmov [rbp+var_8], eax\nmov [rbp+var_4], 0\njmp short loc_1175\nloc_1169:\nmov eax, [rbp+var_8]\nand eax, 1\nadd [rbp+var_4], eax\nsar [rbp+var_8], 1\nloc_1175:\ncmp [rbp+var_8], 0\njg short loc_1169\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n int v3; // [rsp+10h] [rbp-8h]\n unsigned int v4; // [rsp+14h] [rbp-4h]\n\n v3 = a2 ^ a1;\n v4 = 0;\n while ( v3 > 0 )\n {\n v4 += v3 & 1;\n v3 >>= 1;\n }\n return v4;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov eax, [rbp+var_14]\nxor eax, [rbp+var_18]\nmov [rbp+var_8], eax\nmov [rbp+var_4], 0\njmp short loc_1175\nloc_1169:\nmov eax, [rbp+var_8]\nand eax, 1\nadd [rbp+var_4], eax\nsar [rbp+var_8], 1\nloc_1175:\ncmp [rbp+var_8], 0\njg short loc_1169\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2)\n{\n int v3; // [rsp+10h] [rbp-8h]\n unsigned int v4; // [rsp+14h] [rbp-4h]\n\n v3 = a2 ^ a1;\n v4 = 0;\n while ( v3 > 0 )\n {\n v4 += v3 & 1;\n v3 >>= 1;\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2) {\n int v3;\n unsigned int v4;\n v3 = a2 ^ a1;\n v4 = 0;\n while (v3 > 0) {\n v4 += v3 & 1;\n v3 >>= 1;\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n int v3;\n unsigned int v4;\n v3 = a2 ^ a1;\n v4 = 0;\n while (v3 > 0) {\n v4 += v3 & 1;\n v3 >>= 1;\n }\n return v4;\n}" + }, + { + "index": 203, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n1, int n2) {\n int x = n1 ^ n2;\n int setBits = 0;\n while (x > 0) {\n setBits += x & 1;\n x >>= 1;\n }\n return setBits;\n}", + "test": "int main() {\n\n assert(func0(4, 8) == 2);\n\n assert(func0(2, 4) == 2);\n\n assert(func0(1, 2) == 2);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nxor %edi,%esi\njle 1164 \nmov $0x0,%eax\nmov %esi,%edx\nand $0x1,%edx\nadd %edx,%eax\nsar %esi\ntest %esi,%esi\njg 1156 \nretq\nmov $0x0,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nxor edi, esi\njle short loc_1164\nmov eax, 0\nloc_1156:\nmov edx, edi\nand edx, 1\nadd eax, edx\nsar edi, 1\ntest edi, edi\njg short loc_1156\nretn\nloc_1164:\nmov eax, 0\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n int v2; // edi\n __int64 result; // rax\n\n v2 = a2 ^ a1;\n if ( v2 <= 0 )\n return 0LL;\n LODWORD(result) = 0;\n do\n {\n result = (v2 & 1) + (unsigned int)result;\n v2 >>= 1;\n }\n while ( v2 > 0 );\n return result;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nxor edi, esi\njle short loc_1164\nmov eax, 0\nloc_1156:\nmov edx, edi\nand edx, 1\nadd eax, edx\nsar edi, 1\ntest edi, edi\njg short loc_1156\nretn\nloc_1164:\nmov eax, 0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2)\n{\n int v2; // edi\n __int64 result; // rax\n\n v2 = a2 ^ a1;\n if ( v2 <= 0 )\n return 0LL;\n LODWORD(result) = 0;\n do\n {\n result = (v2 & 1) + (unsigned int)result;\n v2 >>= 1;\n }\n while ( v2 > 0 );\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2) {\n int v2;\n long long result;\n v2 = a2 ^ a1;\n if (v2 <= 0) return 0LL;\n LODWORD(result) = 0;\n do {\n result = (v2 & 1) + (unsigned int)result;\n v2 >>= 1;\n } while (v2 > 0);\n return result;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n int v2;\n long long result;\n v2 = a2 ^ a1;\n if (v2 <= 0) return 0LL;\n LODWORD(result) = 0;\n do {\n result = (v2 & 1) + (unsigned int)result;\n v2 >>= 1;\n } while (v2 > 0);\n return result;\n}" + }, + { + "index": 204, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char s[], char c) {\n int res = 0;\n for (int i = 0; i < strlen(s); i++) {\n if (s[i] == c) {\n res = res + 1;\n }\n }\n return res;\n}", + "test": "int main() {\n\n assert(func0(\"abcc\", 'c') == 2);\n\n assert(func0(\"ababca\", 'a') == 3);\n\n assert(func0(\"mnmm0pm\", 'm') == 4);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x28,%rsp\nmov %rdi,-0x28(%rbp)\nmov %esi,%eax\nmov %al,-0x2c(%rbp)\nmovl $0x0,-0x18(%rbp)\nmovl $0x0,-0x14(%rbp)\njmp 11ac \nmov -0x14(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp %al,-0x2c(%rbp)\njne 11a8 \naddl $0x1,-0x18(%rbp)\naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\nmovslq %eax,%rbx\nmov -0x28(%rbp),%rax\nmov %rax,%rdi\ncallq 1060 \ncmp %rax,%rbx\njb 118f \nmov -0x18(%rbp),%eax\nadd $0x28,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+s], rdi\nmov eax, esi\nmov [rbp+var_2C], al\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp short loc_11AC\nloc_118F:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp [rbp+var_2C], al\njnz short loc_11A8\nadd [rbp+var_18], 1\nloc_11A8:\nadd [rbp+var_14], 1\nloc_11AC:\nmov eax, [rbp+var_14]\nmovsxd rbx, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rbx, rax\njb short loc_118F\nmov eax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, char a2)\n{\n unsigned int v3; // [rsp+18h] [rbp-18h]\n int i; // [rsp+1Ch] [rbp-14h]\n\n v3 = 0;\n for ( i = 0; i < strlen(a1); ++i )\n {\n if ( a2 == a1[i] )\n ++v3;\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+s], rdi\nmov eax, esi\nmov [rbp+var_2C], al\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp short loc_11AC\nloc_118F:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp [rbp+var_2C], al\njnz short loc_11A8\nadd [rbp+var_18], 1\nloc_11A8:\nadd [rbp+var_14], 1\nloc_11AC:\nmov eax, [rbp+var_14]\nmovsxd rbx, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rbx, rax\njb short loc_118F\nmov eax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1, char a2)\n{\n unsigned int v3; // [rsp+18h] [rbp-18h]\n int i; // [rsp+1Ch] [rbp-14h]\n\n v3 = 0;\n for ( i = 0; i < strlen(a1); ++i )\n {\n if ( a2 == a1[i] )\n ++v3;\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1, char a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < strlen(a1); ++i) {\n if (a2 == a1[i]) ++v3;\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, char a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < strlen(a1); ++i) {\n if (a2 == a1[i]) ++v3;\n }\n return v3;\n}" + }, + { + "index": 204, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char s[], char c) {\n int res = 0;\n for (int i = 0; i < strlen(s); i++) {\n if (s[i] == c) {\n res = res + 1;\n }\n }\n return res;\n}", + "test": "int main() {\n\n assert(func0(\"abcc\", 'c') == 2);\n\n assert(func0(\"ababca\", 'a') == 3);\n\n assert(func0(\"mnmm0pm\", 'm') == 4);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%r8\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nmov %r8,%rdx\nlea -0x1(%r8,%rcx,1),%rdi\nmov $0x0,%eax\ncmp %rdi,%rdx\nje 1184 \ncmp %sil,(%rdx)\nsete %cl\nmovzbl %cl,%ecx\nadd %ecx,%eax\nadd $0x1,%rdx\njmp 116e \nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov ebp, esi\ncall _strlen\nmov rdi, rax\nmov rax, rbx\nadd rdi, rbx\nmov edx, 0\njmp short loc_119C\nloc_118D:\ncmp [rax], bpl\nsetz cl\nmovzx ecx, cl\nadd edx, ecx\nadd rax, 1\nloc_119C:\ncmp rax, rdi\njnz short loc_118D\nmov eax, edx\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, unsigned __int8 a2)\n{\n size_t v3; // rdi\n const char *v4; // rax\n const char *v5; // rdi\n unsigned int v6; // edx\n\n v3 = strlen(a1);\n v4 = a1;\n v5 = &a1[v3];\n v6 = 0;\n while ( v4 != v5 )\n v6 += *v4++ == a2;\n return v6;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov ebp, esi\ncall _strlen\nmov rdi, rax\nmov rax, rbx\nadd rdi, rbx\nmov edx, 0\njmp short loc_119C\nloc_118D:\ncmp [rax], bpl\nsetz cl\nmovzx ecx, cl\nadd edx, ecx\nadd rax, 1\nloc_119C:\ncmp rax, rdi\njnz short loc_118D\nmov eax, edx\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1, unsigned __int8 a2)\n{\n size_t v3; // rdi\n const char *v4; // rax\n const char *v5; // rdi\n unsigned int v6; // edx\n\n v3 = strlen(a1);\n v4 = a1;\n v5 = &a1[v3];\n v6 = 0;\n while ( v4 != v5 )\n v6 += *v4++ == a2;\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1, unsigned char a2) {\n unsigned int v3;\n const char *v4;\n const char *v5;\n unsigned int v6;\n v3 = strlen(a1);\n v4 = a1;\n v5 = &a1[v3];\n v6 = 0;\n while (v4 != v5) v6 += *v4++ == a2;\n return v6;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, unsigned char a2) {\n unsigned int v3;\n const char *v4;\n const char *v5;\n unsigned int v6;\n v3 = strlen(a1);\n v4 = a1;\n v5 = &a1[v3];\n v6 = 0;\n while (v4 != v5) v6 += *v4++ == a2;\n return v6;\n}" + }, + { + "index": 204, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char s[], char c) {\n int res = 0;\n for (int i = 0; i < strlen(s); i++) {\n if (s[i] == c) {\n res = res + 1;\n }\n }\n return res;\n}", + "test": "int main() {\n\n assert(func0(\"abcc\", 'c') == 2);\n\n assert(func0(\"ababca\", 'a') == 3);\n\n assert(func0(\"mnmm0pm\", 'm') == 4);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %esi,%ebp\npush %rbx\nmov %rdi,%rbx\nsub $0x8,%rsp\ncallq 1060 \nmov %rbx,%rdi\nlea (%rbx,%rax,1),%rcx\nxor %eax,%eax\njmp 125e \nxor %edx,%edx\ncmp %bpl,(%rdi)\nsete %dl\nadd $0x1,%rdi\nadd %edx,%eax\ncmp %rcx,%rdi\njne 1250 \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov ebp, esi\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\ntest rax, rax\njz short loc_1268\nlea rcx, [rbx+rax]\nmov rdi, rbx\nxor eax, eax\nnop word ptr [rax+rax+00h]\nloc_1248:\nxor edx, edx\ncmp bpl, [rdi]\nsetz dl\nadd rdi, 1\nadd eax, edx\ncmp rcx, rdi\njnz short loc_1248\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1268:\nadd rsp, 8\nxor eax, eax\npop rbx\npop rbp\nretn", + "ida_pseudo": "size_t __fastcall func0(const char *a1, char a2)\n{\n size_t result; // rax\n const char *v3; // rcx\n _BOOL4 v4; // edx\n\n result = strlen(a1);\n if ( !result )\n return 0LL;\n v3 = &a1[result];\n LODWORD(result) = 0;\n do\n {\n v4 = a2 == *a1++;\n result = (unsigned int)(v4 + result);\n }\n while ( v3 != a1 );\n return result;\n}", + "ida_strip_asm": "sub_1220:\nendbr64\npush rbp\nmov ebp, esi\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\ntest rax, rax\njz short loc_1268\nlea rcx, [rbx+rax]\nmov rdi, rbx\nxor eax, eax\nnop word ptr [rax+rax+00h]\nloc_1248:\nxor edx, edx\ncmp bpl, [rdi]\nsetz dl\nadd rdi, 1\nadd eax, edx\ncmp rcx, rdi\njnz short loc_1248\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1268:\nadd rsp, 8\nxor eax, eax\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "size_t __fastcall sub_1220(const char *a1, char a2)\n{\n size_t result; // rax\n const char *v3; // rcx\n _BOOL4 v4; // edx\n\n result = strlen(a1);\n if ( !result )\n return 0LL;\n v3 = &a1[result];\n LODWORD(result) = 0;\n do\n {\n v4 = a2 == *a1++;\n result = (unsigned int)(v4 + result);\n }\n while ( v3 != a1 );\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned int sub_1220(const char *a1, char a2) {\n unsigned int result;\n const char *v3;\n int v4;\n result = strlen(a1);\n if (!result) return 0LL;\n v3 = &a1[result];\n LODWORD(result) = 0;\n do {\n v4 = a2 == *a1++;\n result = (unsigned int)(v4 + result);\n } while (v3 != a1);\n return result;\n}", + "ida_pseudo_norm": "unsigned int func0(const char *a1, char a2) {\n unsigned int result;\n const char *v3;\n int v4;\n result = strlen(a1);\n if (!result) return 0LL;\n v3 = &a1[result];\n LODWORD(result) = 0;\n do {\n v4 = a2 == *a1++;\n result = (unsigned int)(v4 + result);\n } while (v3 != a1);\n return result;\n}" + }, + { + "index": 204, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char s[], char c) {\n int res = 0;\n for (int i = 0; i < strlen(s); i++) {\n if (s[i] == c) {\n res = res + 1;\n }\n }\n return res;\n}", + "test": "int main() {\n\n assert(func0(\"abcc\", 'c') == 2);\n\n assert(func0(\"ababca\", 'a') == 3);\n\n assert(func0(\"mnmm0pm\", 'm') == 4);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %esi,%ebp\npush %rbx\nmov %rdi,%rbx\nsub $0x8,%rsp\ncallq 1050 \ntest %rax,%rax\nje 13f0 \nmov %rax,%rcx\nlea -0x1(%rax),%rax\ncmp $0xe,%rax\njbe 13f9 \nmovd %ebp,%xmm4\nmov %rcx,%rax\npxor %xmm1,%xmm1\nmov %rbx,%rdx\npunpcklbw %xmm4,%xmm4\npxor %xmm6,%xmm6\npxor %xmm5,%xmm5\nand $0xfffffffffffffff0,%rax\npunpcklwd %xmm4,%xmm4\nmovdqa 0xe58(%rip),%xmm7\nadd %rbx,%rax\npshufd $0x0,%xmm4,%xmm4\nmovdqu (%rdx),%xmm0\nmovdqa %xmm6,%xmm3\nadd $0x10,%rdx\npcmpeqb %xmm4,%xmm0\npand %xmm7,%xmm0\npcmpgtb %xmm0,%xmm3\nmovdqa %xmm0,%xmm2\npunpcklbw %xmm3,%xmm2\npunpckhbw %xmm3,%xmm0\nmovdqa %xmm5,%xmm3\npcmpgtw %xmm2,%xmm3\nmovdqa %xmm2,%xmm8\npunpcklwd %xmm3,%xmm8\npunpckhwd %xmm3,%xmm2\nmovdqa %xmm0,%xmm3\npaddd %xmm8,%xmm1\npaddd %xmm2,%xmm1\nmovdqa %xmm5,%xmm2\npcmpgtw %xmm0,%xmm2\npunpcklwd %xmm2,%xmm3\npunpckhwd %xmm2,%xmm0\npaddd %xmm3,%xmm1\npaddd %xmm0,%xmm1\ncmp %rax,%rdx\njne 11c0 \nmovdqa %xmm1,%xmm0\nmov %rcx,%rsi\npsrldq $0x8,%xmm0\nand $0xfffffffffffffff0,%rsi\npaddd %xmm1,%xmm0\nmov %esi,%edx\nmovdqa %xmm0,%xmm1\npsrldq $0x4,%xmm1\npaddd %xmm1,%xmm0\nmovd %xmm0,%eax\ncmp %rsi,%rcx\nje 13e2 \ncmp %bpl,(%rbx,%rsi,1)\nsete %sil\nmovzbl %sil,%esi\nadd %esi,%eax\nlea 0x1(%rdx),%esi\nmovslq %esi,%rsi\ncmp %rsi,%rcx\njbe 13e2 \ncmp %bpl,(%rbx,%rsi,1)\nsete %sil\nmovzbl %sil,%esi\nadd %esi,%eax\nlea 0x2(%rdx),%esi\nmovslq %esi,%rsi\ncmp %rsi,%rcx\njbe 13e2 \ncmp %bpl,(%rbx,%rsi,1)\nsete %sil\nmovzbl %sil,%esi\nadd %esi,%eax\nlea 0x3(%rdx),%esi\nmovslq %esi,%rsi\ncmp %rsi,%rcx\njbe 13e2 \ncmp %bpl,(%rbx,%rsi,1)\nsete %sil\nmovzbl %sil,%esi\nadd %esi,%eax\nlea 0x4(%rdx),%esi\nmovslq %esi,%rsi\ncmp %rsi,%rcx\njbe 13e2 \ncmp %bpl,(%rbx,%rsi,1)\nsete %sil\nmovzbl %sil,%esi\nadd %esi,%eax\nlea 0x5(%rdx),%esi\nmovslq %esi,%rsi\ncmp %rsi,%rcx\njbe 13e2 \ncmp %bpl,(%rbx,%rsi,1)\nsete %sil\nmovzbl %sil,%esi\nadd %esi,%eax\nlea 0x6(%rdx),%esi\nmovslq %esi,%rsi\ncmp %rsi,%rcx\njbe 13e2 \ncmp %bpl,(%rbx,%rsi,1)\nsete %sil\nmovzbl %sil,%esi\nadd %esi,%eax\nlea 0x7(%rdx),%esi\nmovslq %esi,%rsi\ncmp %rsi,%rcx\njbe 13e2 \ncmp %bpl,(%rbx,%rsi,1)\nsete %sil\nmovzbl %sil,%esi\nadd %esi,%eax\nlea 0x8(%rdx),%esi\nmovslq %esi,%rsi\ncmp %rsi,%rcx\njbe 13e2 \ncmp %bpl,(%rbx,%rsi,1)\nsete %sil\nmovzbl %sil,%esi\nadd %esi,%eax\nlea 0x9(%rdx),%esi\nmovslq %esi,%rsi\ncmp %rsi,%rcx\njbe 13e2 \ncmp %bpl,(%rbx,%rsi,1)\nsete %sil\nmovzbl %sil,%esi\nadd %esi,%eax\nlea 0xa(%rdx),%esi\nmovslq %esi,%rsi\ncmp %rsi,%rcx\njbe 13e2 \ncmp %bpl,(%rbx,%rsi,1)\nsete %sil\nmovzbl %sil,%esi\nadd %esi,%eax\nlea 0xb(%rdx),%esi\nmovslq %esi,%rsi\ncmp %rsi,%rcx\njbe 13e2 \ncmp %bpl,(%rbx,%rsi,1)\nsete %sil\nmovzbl %sil,%esi\nadd %esi,%eax\nlea 0xc(%rdx),%esi\nmovslq %esi,%rsi\ncmp %rsi,%rcx\njbe 13e2 \ncmp %bpl,(%rbx,%rsi,1)\nsete %sil\nmovzbl %sil,%esi\nadd %esi,%eax\nlea 0xd(%rdx),%esi\nmovslq %esi,%rsi\ncmp %rsi,%rcx\njbe 13e2 \ncmp %bpl,(%rbx,%rsi,1)\nsete %sil\nadd $0xe,%edx\nmovzbl %sil,%esi\nmovslq %edx,%rdx\nadd %esi,%eax\ncmp %rdx,%rcx\njbe 13e2 \ncmp %bpl,(%rbx,%rdx,1)\nsete %dl\nmovzbl %dl,%edx\nadd %edx,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopl 0x0(%rax)\nadd $0x8,%rsp\nxor %eax,%eax\npop %rbx\npop %rbp\nretq\nxor %edx,%edx\nxor %eax,%eax\nxor %esi,%esi\njmpq 1254 \nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov ebp, esi\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\ntest rax, rax\njz loc_13D0\nmov rdx, rax\nlea rax, [rax-1]\ncmp rax, 0Eh\njbe loc_13D9\nmovd xmm4, ebp\nmov rcx, rdx\npxor xmm1, xmm1\nmov rax, rbx\npunpcklbw xmm4, xmm4\npxor xmm6, xmm6\npxor xmm5, xmm5\nand rcx, 0FFFFFFFFFFFFFFF0h\npunpcklwd xmm4, xmm4\nlea rsi, [rcx+rbx]\npshufd xmm4, xmm4, 0\nnop dword ptr [rax+00000000h]\nloc_11C0:\nmovdqu xmm0, xmmword ptr [rax]\nmovdqa xmm3, xmm6\nadd rax, 10h\npcmpeqb xmm0, xmm4\npcmpgtb xmm3, xmm0\nmovdqa xmm2, xmm0\npunpcklbw xmm2, xmm3\npunpckhbw xmm0, xmm3\nmovdqa xmm3, xmm5\npcmpgtw xmm3, xmm2\nmovdqa xmm7, xmm2\npunpcklwd xmm7, xmm3\npunpckhwd xmm2, xmm3\nmovdqa xmm3, xmm0\npsubd xmm1, xmm7\npsubd xmm1, xmm2\nmovdqa xmm2, xmm5\npcmpgtw xmm2, xmm0\npunpcklwd xmm3, xmm2\npunpckhwd xmm0, xmm2\npsubd xmm1, xmm3\npsubd xmm1, xmm0\ncmp rsi, rax\njnz short loc_11C0\nmovdqa xmm0, xmm1\nmov esi, ecx\npsrldq xmm0, 8\npaddd xmm0, xmm1\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\npaddd xmm0, xmm2\nmovd eax, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm1, 8\npaddd xmm0, xmm1\ncmp rdx, rcx\njz loc_136F\nloc_1253:\nmov rdi, rdx\nsub rdi, rcx\nlea r8, [rdi-1]\ncmp r8, 6\njbe loc_12FD\nmovzx eax, bpl\nmovq xmm1, qword ptr [rbx+rcx]\nmov ah, al\nmovd xmm6, eax\npshuflw xmm2, xmm6, 0\npcmpeqb xmm1, xmm2\npxor xmm2, xmm2\npcmpgtb xmm2, xmm1\nmovdqa xmm3, xmm1\npunpcklbw xmm3, xmm2\npunpcklbw xmm1, xmm2\npxor xmm2, xmm2\nmovdqa xmm4, xmm2\nmovdqa xmm5, xmm3\npshufd xmm1, xmm1, 4Eh ; 'N'\npcmpgtw xmm4, xmm3\npcmpgtw xmm2, xmm1\npunpcklwd xmm5, xmm4\npunpcklwd xmm3, xmm4\npsubd xmm0, xmm5\npshufd xmm3, xmm3, 4Eh ; 'N'\npsubd xmm0, xmm3\nmovdqa xmm3, xmm1\npunpcklwd xmm1, xmm2\npunpcklwd xmm3, xmm2\npshufd xmm1, xmm1, 4Eh ; 'N'\npsubd xmm0, xmm3\npsubd xmm0, xmm1\nmovd r8d, xmm0\npshufd xmm6, xmm0, 0E5h\nmovd eax, xmm6\nadd eax, r8d\nmov r8, rdi\nand r8, 0FFFFFFFFFFFFFFF8h\nadd rcx, r8\nadd esi, r8d\nand edi, 7\njz short loc_136F\nloc_12FD:\ncmp [rbx+rcx], bpl\njz short loc_1380\nloc_1303:\nlea ecx, [rsi+1]\nmovsxd rcx, ecx\ncmp rcx, rdx\njnb short loc_136F\ncmp bpl, [rbx+rcx]\njz short loc_1390\nloc_1314:\nlea ecx, [rsi+2]\nmovsxd rcx, ecx\ncmp rcx, rdx\njnb short loc_136F\ncmp bpl, [rbx+rcx]\njz short loc_13A0\nloc_1325:\nlea ecx, [rsi+3]\nmovsxd rcx, ecx\ncmp rcx, rdx\njnb short loc_136F\ncmp bpl, [rbx+rcx]\njz short loc_13A8\nlea ecx, [rsi+4]\nmovsxd rcx, ecx\ncmp rcx, rdx\njnb short loc_136F\nloc_1341:\ncmp bpl, [rbx+rcx]\njnz short loc_134A\nadd eax, 1\nloc_134A:\nlea ecx, [rsi+5]\nmovsxd rcx, ecx\ncmp rcx, rdx\njnb short loc_136F\ncmp bpl, [rbx+rcx]\njnz short loc_135E\nadd eax, 1\nloc_135E:\nadd esi, 6\nmovsxd rsi, esi\ncmp rsi, rdx\njnb short loc_136F\ncmp bpl, [rbx+rsi]\njz short loc_13C0\nloc_136F:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1380:\nadd eax, 1\njmp loc_1303\nloc_1390:\nadd eax, 1\njmp loc_1314\nloc_13A0:\nadd eax, 1\njmp short loc_1325\nloc_13A8:\nlea ecx, [rsi+4]\nadd eax, 1\nmovsxd rcx, ecx\ncmp rcx, rdx\njb short loc_1341\njmp short loc_136F\nloc_13C0:\nadd rsp, 8\nadd eax, 1\npop rbx\npop rbp\nretn\nloc_13D0:\nadd rsp, 8\nxor eax, eax\npop rbx\npop rbp\nretn\nloc_13D9:\npxor xmm0, xmm0\nxor esi, esi\nxor eax, eax\nxor ecx, ecx\njmp loc_1253", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, unsigned __int8 a2)\n{\n size_t v4; // rax\n size_t v5; // rdx\n __m128i v6; // xmm4\n __m128i v7; // xmm1\n const __m128i *v8; // rax\n __m128i v9; // xmm4\n unsigned __int64 v10; // rcx\n __m128i v11; // xmm4\n __m128i v12; // xmm0\n __m128i v13; // xmm0\n __m128i v14; // xmm3\n __m128i v15; // xmm2\n __m128i v16; // xmm0\n __m128i v17; // xmm3\n __m128i v18; // xmm1\n __m128i v19; // xmm2\n int v20; // esi\n __m128i v21; // xmm0\n __int64 result; // rax\n __m128i v23; // xmm0\n size_t v24; // rdi\n unsigned int v25; // eax\n __m128i v26; // xmm1\n __m128i v27; // xmm3\n __m128i v28; // xmm1\n __m128i v29; // xmm2\n __m128i v30; // xmm3\n __m128i v31; // xmm0\n size_t v32; // rcx\n size_t v33; // rcx\n size_t v34; // rcx\n size_t v35; // rcx\n size_t v36; // rcx\n size_t v37; // rsi\n\n v4 = strlen(a1);\n if ( !v4 )\n return 0LL;\n v5 = v4;\n if ( v4 - 1 <= 0xE )\n {\n v23 = 0LL;\n v20 = 0;\n result = 0LL;\n v10 = 0LL;\n }\n else\n {\n v6 = _mm_cvtsi32_si128(a2);\n v7 = 0LL;\n v8 = (const __m128i *)a1;\n v9 = _mm_unpacklo_epi8(v6, v6);\n v10 = v5 & 0xFFFFFFFFFFFFFFF0LL;\n v11 = _mm_shuffle_epi32(_mm_unpacklo_epi16(v9, v9), 0);\n do\n {\n v12 = _mm_loadu_si128(v8++);\n v13 = _mm_cmpeq_epi8(v12, v11);\n v14 = _mm_cmpgt_epi8((__m128i)0LL, v13);\n v15 = _mm_unpacklo_epi8(v13, v14);\n v16 = _mm_unpackhi_epi8(v13, v14);\n v17 = _mm_cmpgt_epi16((__m128i)0LL, v15);\n v18 = _mm_sub_epi32(_mm_sub_epi32(v7, _mm_unpacklo_epi16(v15, v17)), _mm_unpackhi_epi16(v15, v17));\n v19 = _mm_cmpgt_epi16((__m128i)0LL, v16);\n v7 = _mm_sub_epi32(_mm_sub_epi32(v18, _mm_unpacklo_epi16(v16, v19)), _mm_unpackhi_epi16(v16, v19));\n }\n while ( &a1[v5 & 0xFFFFFFFFFFFFFFF0LL] != (const char *)v8 );\n v20 = v5 & 0xFFFFFFF0;\n v21 = _mm_add_epi32(_mm_srli_si128(v7, 8), v7);\n result = (unsigned int)_mm_cvtsi128_si32(_mm_add_epi32(v21, _mm_srli_si128(v21, 4)));\n v23 = _mm_add_epi32(v7, _mm_srli_si128(v7, 8));\n if ( v5 == v10 )\n return result;\n }\n v24 = v5 - v10;\n if ( v5 - v10 - 1 <= 6 )\n goto LABEL_34;\n v25 = a2;\n BYTE1(v25) = a2;\n v26 = _mm_cmpeq_epi8(_mm_loadl_epi64((const __m128i *)&a1[v10]), _mm_shufflelo_epi16(_mm_cvtsi32_si128(v25), 0));\n v27 = _mm_unpacklo_epi8(v26, _mm_cmpgt_epi8((__m128i)0LL, v26));\n v28 = _mm_shuffle_epi32(v27, 78);\n v29 = _mm_cmpgt_epi16((__m128i)0LL, v28);\n v30 = _mm_unpacklo_epi16(v27, _mm_cmpgt_epi16((__m128i)0LL, v27));\n v31 = _mm_sub_epi32(\n _mm_sub_epi32(\n _mm_sub_epi32(_mm_sub_epi32(v23, v30), _mm_shuffle_epi32(v30, 78)),\n _mm_unpacklo_epi16(v28, v29)),\n _mm_shuffle_epi32(_mm_unpacklo_epi16(v28, v29), 78));\n result = (unsigned int)(_mm_cvtsi128_si32(v31) + _mm_cvtsi128_si32(_mm_shuffle_epi32(v31, 229)));\n v10 += v24 & 0xFFFFFFFFFFFFFFF8LL;\n v20 += v24 & 0xFFFFFFF8;\n if ( (v24 & 7) != 0 )\n {\nLABEL_34:\n if ( a1[v10] == a2 )\n result = (unsigned int)(result + 1);\n v32 = v20 + 1;\n if ( v32 < v5 )\n {\n if ( a2 == a1[v32] )\n result = (unsigned int)(result + 1);\n v33 = v20 + 2;\n if ( v33 < v5 )\n {\n if ( a2 == a1[v33] )\n result = (unsigned int)(result + 1);\n v34 = v20 + 3;\n if ( v34 < v5 )\n {\n if ( a2 == a1[v34] )\n {\n result = (unsigned int)(result + 1);\n v35 = v20 + 4;\n if ( v35 >= v5 )\n return result;\n }\n else\n {\n v35 = v20 + 4;\n if ( v35 >= v5 )\n return result;\n }\n if ( a2 == a1[v35] )\n result = (unsigned int)(result + 1);\n v36 = v20 + 5;\n if ( v36 < v5 )\n {\n if ( a2 == a1[v36] )\n result = (unsigned int)(result + 1);\n v37 = v20 + 6;\n if ( v37 < v5 && a2 == a1[v37] )\n return (unsigned int)(result + 1);\n }\n }\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1160:\nendbr64\npush rbp\nmov ebp, esi\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\ntest rax, rax\njz loc_13D0\nmov rdx, rax\nlea rax, [rax-1]\ncmp rax, 0Eh\njbe loc_13D9\nmovd xmm4, ebp\nmov rcx, rdx\npxor xmm1, xmm1\nmov rax, rbx\npunpcklbw xmm4, xmm4\npxor xmm6, xmm6\npxor xmm5, xmm5\nand rcx, 0FFFFFFFFFFFFFFF0h\npunpcklwd xmm4, xmm4\nlea rsi, [rcx+rbx]\npshufd xmm4, xmm4, 0\nnop dword ptr [rax+00000000h]\nloc_11C0:\nmovdqu xmm0, xmmword ptr [rax]\nmovdqa xmm3, xmm6\nadd rax, 10h\npcmpeqb xmm0, xmm4\npcmpgtb xmm3, xmm0\nmovdqa xmm2, xmm0\npunpcklbw xmm2, xmm3\npunpckhbw xmm0, xmm3\nmovdqa xmm3, xmm5\npcmpgtw xmm3, xmm2\nmovdqa xmm7, xmm2\npunpcklwd xmm7, xmm3\npunpckhwd xmm2, xmm3\nmovdqa xmm3, xmm0\npsubd xmm1, xmm7\npsubd xmm1, xmm2\nmovdqa xmm2, xmm5\npcmpgtw xmm2, xmm0\npunpcklwd xmm3, xmm2\npunpckhwd xmm0, xmm2\npsubd xmm1, xmm3\npsubd xmm1, xmm0\ncmp rsi, rax\njnz short loc_11C0\nmovdqa xmm0, xmm1\nmov esi, ecx\npsrldq xmm0, 8\npaddd xmm0, xmm1\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\npaddd xmm0, xmm2\nmovd eax, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm1, 8\npaddd xmm0, xmm1\ncmp rdx, rcx\njz loc_136F\nloc_1253:\nmov rdi, rdx\nsub rdi, rcx\nlea r8, [rdi-1]\ncmp r8, 6\njbe loc_12FD\nmovzx eax, bpl\nmovq xmm1, qword ptr [rbx+rcx]\nmov ah, al\nmovd xmm6, eax\npshuflw xmm2, xmm6, 0\npcmpeqb xmm1, xmm2\npxor xmm2, xmm2\npcmpgtb xmm2, xmm1\nmovdqa xmm3, xmm1\npunpcklbw xmm3, xmm2\npunpcklbw xmm1, xmm2\npxor xmm2, xmm2\nmovdqa xmm4, xmm2\nmovdqa xmm5, xmm3\npshufd xmm1, xmm1, 4Eh ; 'N'\npcmpgtw xmm4, xmm3\npcmpgtw xmm2, xmm1\npunpcklwd xmm5, xmm4\npunpcklwd xmm3, xmm4\npsubd xmm0, xmm5\npshufd xmm3, xmm3, 4Eh ; 'N'\npsubd xmm0, xmm3\nmovdqa xmm3, xmm1\npunpcklwd xmm1, xmm2\npunpcklwd xmm3, xmm2\npshufd xmm1, xmm1, 4Eh ; 'N'\npsubd xmm0, xmm3\npsubd xmm0, xmm1\nmovd r8d, xmm0\npshufd xmm6, xmm0, 0E5h\nmovd eax, xmm6\nadd eax, r8d\nmov r8, rdi\nand r8, 0FFFFFFFFFFFFFFF8h\nadd rcx, r8\nadd esi, r8d\nand edi, 7\njz short loc_136F\nloc_12FD:\ncmp [rbx+rcx], bpl\njz short loc_1380\nloc_1303:\nlea ecx, [rsi+1]\nmovsxd rcx, ecx\ncmp rcx, rdx\njnb short loc_136F\ncmp bpl, [rbx+rcx]\njz short loc_1390\nloc_1314:\nlea ecx, [rsi+2]\nmovsxd rcx, ecx\ncmp rcx, rdx\njnb short loc_136F\ncmp bpl, [rbx+rcx]\njz short loc_13A0\nloc_1325:\nlea ecx, [rsi+3]\nmovsxd rcx, ecx\ncmp rcx, rdx\njnb short loc_136F\ncmp bpl, [rbx+rcx]\njz short loc_13A8\nlea ecx, [rsi+4]\nmovsxd rcx, ecx\ncmp rcx, rdx\njnb short loc_136F\nloc_1341:\ncmp bpl, [rbx+rcx]\njnz short loc_134A\nadd eax, 1\nloc_134A:\nlea ecx, [rsi+5]\nmovsxd rcx, ecx\ncmp rcx, rdx\njnb short loc_136F\ncmp bpl, [rbx+rcx]\njnz short loc_135E\nadd eax, 1\nloc_135E:\nadd esi, 6\nmovsxd rsi, esi\ncmp rsi, rdx\njnb short loc_136F\ncmp bpl, [rbx+rsi]\njz short loc_13C0\nloc_136F:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1380:\nadd eax, 1\njmp loc_1303\nloc_1390:\nadd eax, 1\njmp loc_1314\nloc_13A0:\nadd eax, 1\njmp short loc_1325\nloc_13A8:\nlea ecx, [rsi+4]\nadd eax, 1\nmovsxd rcx, ecx\ncmp rcx, rdx\njb short loc_1341\njmp short loc_136F\nloc_13C0:\nadd rsp, 8\nadd eax, 1\npop rbx\npop rbp\nretn\nloc_13D0:\nadd rsp, 8\nxor eax, eax\npop rbx\npop rbp\nretn\nloc_13D9:\npxor xmm0, xmm0\nxor esi, esi\nxor eax, eax\nxor ecx, ecx\njmp loc_1253", + "ida_strip_pseudo": "__int64 __fastcall sub_1160(const char *a1, unsigned __int8 a2)\n{\n size_t v4; // rax\n size_t v5; // rdx\n __m128i v6; // xmm4\n __m128i v7; // xmm1\n const __m128i *v8; // rax\n __m128i v9; // xmm4\n unsigned __int64 v10; // rcx\n __m128i v11; // xmm4\n __m128i v12; // xmm0\n __m128i v13; // xmm0\n __m128i v14; // xmm3\n __m128i v15; // xmm2\n __m128i v16; // xmm0\n __m128i v17; // xmm3\n __m128i v18; // xmm1\n __m128i v19; // xmm2\n int v20; // esi\n __m128i v21; // xmm0\n __int64 result; // rax\n __m128i v23; // xmm0\n size_t v24; // rdi\n unsigned int v25; // eax\n __m128i v26; // xmm1\n __m128i v27; // xmm3\n __m128i v28; // xmm1\n __m128i v29; // xmm2\n __m128i v30; // xmm3\n __m128i v31; // xmm0\n size_t v32; // rcx\n size_t v33; // rcx\n size_t v34; // rcx\n size_t v35; // rcx\n size_t v36; // rcx\n size_t v37; // rsi\n\n v4 = strlen(a1);\n if ( !v4 )\n return 0LL;\n v5 = v4;\n if ( v4 - 1 <= 0xE )\n {\n v23 = 0LL;\n v20 = 0;\n result = 0LL;\n v10 = 0LL;\n }\n else\n {\n v6 = _mm_cvtsi32_si128(a2);\n v7 = 0LL;\n v8 = (const __m128i *)a1;\n v9 = _mm_unpacklo_epi8(v6, v6);\n v10 = v5 & 0xFFFFFFFFFFFFFFF0LL;\n v11 = _mm_shuffle_epi32(_mm_unpacklo_epi16(v9, v9), 0);\n do\n {\n v12 = _mm_loadu_si128(v8++);\n v13 = _mm_cmpeq_epi8(v12, v11);\n v14 = _mm_cmpgt_epi8((__m128i)0LL, v13);\n v15 = _mm_unpacklo_epi8(v13, v14);\n v16 = _mm_unpackhi_epi8(v13, v14);\n v17 = _mm_cmpgt_epi16((__m128i)0LL, v15);\n v18 = _mm_sub_epi32(_mm_sub_epi32(v7, _mm_unpacklo_epi16(v15, v17)), _mm_unpackhi_epi16(v15, v17));\n v19 = _mm_cmpgt_epi16((__m128i)0LL, v16);\n v7 = _mm_sub_epi32(_mm_sub_epi32(v18, _mm_unpacklo_epi16(v16, v19)), _mm_unpackhi_epi16(v16, v19));\n }\n while ( &a1[v5 & 0xFFFFFFFFFFFFFFF0LL] != (const char *)v8 );\n v20 = v5 & 0xFFFFFFF0;\n v21 = _mm_add_epi32(_mm_srli_si128(v7, 8), v7);\n result = (unsigned int)_mm_cvtsi128_si32(_mm_add_epi32(v21, _mm_srli_si128(v21, 4)));\n v23 = _mm_add_epi32(v7, _mm_srli_si128(v7, 8));\n if ( v5 == v10 )\n return result;\n }\n v24 = v5 - v10;\n if ( v5 - v10 - 1 <= 6 )\n goto LABEL_34;\n v25 = a2;\n BYTE1(v25) = a2;\n v26 = _mm_cmpeq_epi8(_mm_loadl_epi64((const __m128i *)&a1[v10]), _mm_shufflelo_epi16(_mm_cvtsi32_si128(v25), 0));\n v27 = _mm_unpacklo_epi8(v26, _mm_cmpgt_epi8((__m128i)0LL, v26));\n v28 = _mm_shuffle_epi32(v27, 78);\n v29 = _mm_cmpgt_epi16((__m128i)0LL, v28);\n v30 = _mm_unpacklo_epi16(v27, _mm_cmpgt_epi16((__m128i)0LL, v27));\n v31 = _mm_sub_epi32(\n _mm_sub_epi32(\n _mm_sub_epi32(_mm_sub_epi32(v23, v30), _mm_shuffle_epi32(v30, 78)),\n _mm_unpacklo_epi16(v28, v29)),\n _mm_shuffle_epi32(_mm_unpacklo_epi16(v28, v29), 78));\n result = (unsigned int)(_mm_cvtsi128_si32(v31) + _mm_cvtsi128_si32(_mm_shuffle_epi32(v31, 229)));\n v10 += v24 & 0xFFFFFFFFFFFFFFF8LL;\n v20 += v24 & 0xFFFFFFF8;\n if ( (v24 & 7) != 0 )\n {\nLABEL_34:\n if ( a1[v10] == a2 )\n result = (unsigned int)(result + 1);\n v32 = v20 + 1;\n if ( v32 < v5 )\n {\n if ( a2 == a1[v32] )\n result = (unsigned int)(result + 1);\n v33 = v20 + 2;\n if ( v33 < v5 )\n {\n if ( a2 == a1[v33] )\n result = (unsigned int)(result + 1);\n v34 = v20 + 3;\n if ( v34 < v5 )\n {\n if ( a2 == a1[v34] )\n {\n result = (unsigned int)(result + 1);\n v35 = v20 + 4;\n if ( v35 >= v5 )\n return result;\n }\n else\n {\n v35 = v20 + 4;\n if ( v35 >= v5 )\n return result;\n }\n if ( a2 == a1[v35] )\n result = (unsigned int)(result + 1);\n v36 = v20 + 5;\n if ( v36 < v5 )\n {\n if ( a2 == a1[v36] )\n result = (unsigned int)(result + 1);\n v37 = v20 + 6;\n if ( v37 < v5 && a2 == a1[v37] )\n return (unsigned int)(result + 1);\n }\n }\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1160(const char *a1, unsigned char a2) {\n unsigned int v4;\n unsigned int v5;\n __m128i v6;\n __m128i v7;\n const __m128i *v8;\n __m128i v9;\n unsigned long long v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n __m128i v15;\n __m128i v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n int v20;\n __m128i v21;\n long long result;\n __m128i v23;\n unsigned int v24;\n unsigned int v25;\n __m128i v26;\n __m128i v27;\n __m128i v28;\n __m128i v29;\n __m128i v30;\n __m128i v31;\n unsigned int v32;\n unsigned int v33;\n unsigned int v34;\n unsigned int v35;\n unsigned int v36;\n unsigned int v37;\n v4 = strlen(a1);\n if (!v4) return 0LL;\n v5 = v4;\n if (v4 - 1 <= 14) {\n v23 = 0LL;\n v20 = 0;\n result = 0LL;\n v10 = 0LL;\n } else {\n v6 = _mm_cvtsi32_si128(a2);\n v7 = 0LL;\n v8 = (const __m128i *)a1;\n v9 = _mm_unpacklo_epi8(v6, v6);\n v10 = v5 & 18446744073709551600LL;\n v11 = _mm_shuffle_epi32(_mm_unpacklo_epi16(v9, v9), 0);\n do {\n v12 = _mm_loadu_si128(v8++);\n v13 = _mm_cmpeq_epi8(v12, v11);\n v14 = _mm_cmpgt_epi8((__m128i)0LL, v13);\n v15 = _mm_unpacklo_epi8(v13, v14);\n v16 = _mm_unpackhi_epi8(v13, v14);\n v17 = _mm_cmpgt_epi16((__m128i)0LL, v15);\n v18 = _mm_sub_epi32(_mm_sub_epi32(v7, _mm_unpacklo_epi16(v15, v17)),\n _mm_unpackhi_epi16(v15, v17));\n v19 = _mm_cmpgt_epi16((__m128i)0LL, v16);\n v7 = _mm_sub_epi32(_mm_sub_epi32(v18, _mm_unpacklo_epi16(v16, v19)),\n _mm_unpackhi_epi16(v16, v19));\n } while (&a1[v5 & 18446744073709551600LL] != (const char *)v8);\n v20 = v5 & 4294967280;\n v21 = _mm_add_epi32(_mm_srli_si128(v7, 8), v7);\n result = (unsigned int)_mm_cvtsi128_si32(\n _mm_add_epi32(v21, _mm_srli_si128(v21, 4)));\n v23 = _mm_add_epi32(v7, _mm_srli_si128(v7, 8));\n if (v5 == v10) return result;\n }\n v24 = v5 - v10;\n if (v5 - v10 - 1 <= 6) goto LABEL_34;\n v25 = a2;\n BYTE1(v25) = a2;\n v26 = _mm_cmpeq_epi8(_mm_loadl_epi64((const __m128i *)&a1[v10]),\n _mm_shufflelo_epi16(_mm_cvtsi32_si128(v25), 0));\n v27 = _mm_unpacklo_epi8(v26, _mm_cmpgt_epi8((__m128i)0LL, v26));\n v28 = _mm_shuffle_epi32(v27, 78);\n v29 = _mm_cmpgt_epi16((__m128i)0LL, v28);\n v30 = _mm_unpacklo_epi16(v27, _mm_cmpgt_epi16((__m128i)0LL, v27));\n v31 = _mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(v23, v30),\n _mm_shuffle_epi32(v30, 78)),\n _mm_unpacklo_epi16(v28, v29)),\n _mm_shuffle_epi32(_mm_unpacklo_epi16(v28, v29), 78));\n result = (unsigned int)(_mm_cvtsi128_si32(v31) +\n _mm_cvtsi128_si32(_mm_shuffle_epi32(v31, 229)));\n v10 += v24 & 18446744073709551608LL;\n v20 += v24 & 4294967288;\n if ((v24 & 7) != 0) {\n LABEL_34:\n if (a1[v10] == a2) result = (unsigned int)(result + 1);\n v32 = v20 + 1;\n if (v32 < v5) {\n if (a2 == a1[v32]) result = (unsigned int)(result + 1);\n v33 = v20 + 2;\n if (v33 < v5) {\n if (a2 == a1[v33]) result = (unsigned int)(result + 1);\n v34 = v20 + 3;\n if (v34 < v5) {\n if (a2 == a1[v34]) {\n result = (unsigned int)(result + 1);\n v35 = v20 + 4;\n if (v35 >= v5) return result;\n } else {\n v35 = v20 + 4;\n if (v35 >= v5) return result;\n }\n if (a2 == a1[v35]) result = (unsigned int)(result + 1);\n v36 = v20 + 5;\n if (v36 < v5) {\n if (a2 == a1[v36]) result = (unsigned int)(result + 1);\n v37 = v20 + 6;\n if (v37 < v5 && a2 == a1[v37]) return (unsigned int)(result + 1);\n }\n }\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, unsigned char a2) {\n unsigned int v4;\n unsigned int v5;\n __m128i v6;\n __m128i v7;\n const __m128i *v8;\n __m128i v9;\n unsigned long long v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n __m128i v15;\n __m128i v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n int v20;\n __m128i v21;\n long long result;\n __m128i v23;\n unsigned int v24;\n unsigned int v25;\n __m128i v26;\n __m128i v27;\n __m128i v28;\n __m128i v29;\n __m128i v30;\n __m128i v31;\n unsigned int v32;\n unsigned int v33;\n unsigned int v34;\n unsigned int v35;\n unsigned int v36;\n unsigned int v37;\n v4 = strlen(a1);\n if (!v4) return 0LL;\n v5 = v4;\n if (v4 - 1 <= 14) {\n v23 = 0LL;\n v20 = 0;\n result = 0LL;\n v10 = 0LL;\n } else {\n v6 = _mm_cvtsi32_si128(a2);\n v7 = 0LL;\n v8 = (const __m128i *)a1;\n v9 = _mm_unpacklo_epi8(v6, v6);\n v10 = v5 & 18446744073709551600LL;\n v11 = _mm_shuffle_epi32(_mm_unpacklo_epi16(v9, v9), 0);\n do {\n v12 = _mm_loadu_si128(v8++);\n v13 = _mm_cmpeq_epi8(v12, v11);\n v14 = _mm_cmpgt_epi8((__m128i)0LL, v13);\n v15 = _mm_unpacklo_epi8(v13, v14);\n v16 = _mm_unpackhi_epi8(v13, v14);\n v17 = _mm_cmpgt_epi16((__m128i)0LL, v15);\n v18 = _mm_sub_epi32(_mm_sub_epi32(v7, _mm_unpacklo_epi16(v15, v17)),\n _mm_unpackhi_epi16(v15, v17));\n v19 = _mm_cmpgt_epi16((__m128i)0LL, v16);\n v7 = _mm_sub_epi32(_mm_sub_epi32(v18, _mm_unpacklo_epi16(v16, v19)),\n _mm_unpackhi_epi16(v16, v19));\n } while (&a1[v5 & 18446744073709551600LL] != (const char *)v8);\n v20 = v5 & 4294967280;\n v21 = _mm_add_epi32(_mm_srli_si128(v7, 8), v7);\n result = (unsigned int)_mm_cvtsi128_si32(\n _mm_add_epi32(v21, _mm_srli_si128(v21, 4)));\n v23 = _mm_add_epi32(v7, _mm_srli_si128(v7, 8));\n if (v5 == v10) return result;\n }\n v24 = v5 - v10;\n if (v5 - v10 - 1 <= 6) goto LABEL_34;\n v25 = a2;\n BYTE1(v25) = a2;\n v26 = _mm_cmpeq_epi8(_mm_loadl_epi64((const __m128i *)&a1[v10]),\n _mm_shufflelo_epi16(_mm_cvtsi32_si128(v25), 0));\n v27 = _mm_unpacklo_epi8(v26, _mm_cmpgt_epi8((__m128i)0LL, v26));\n v28 = _mm_shuffle_epi32(v27, 78);\n v29 = _mm_cmpgt_epi16((__m128i)0LL, v28);\n v30 = _mm_unpacklo_epi16(v27, _mm_cmpgt_epi16((__m128i)0LL, v27));\n v31 = _mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(v23, v30),\n _mm_shuffle_epi32(v30, 78)),\n _mm_unpacklo_epi16(v28, v29)),\n _mm_shuffle_epi32(_mm_unpacklo_epi16(v28, v29), 78));\n result = (unsigned int)(_mm_cvtsi128_si32(v31) +\n _mm_cvtsi128_si32(_mm_shuffle_epi32(v31, 229)));\n v10 += v24 & 18446744073709551608LL;\n v20 += v24 & 4294967288;\n if ((v24 & 7) != 0) {\n LABEL_34:\n if (a1[v10] == a2) result = (unsigned int)(result + 1);\n v32 = v20 + 1;\n if (v32 < v5) {\n if (a2 == a1[v32]) result = (unsigned int)(result + 1);\n v33 = v20 + 2;\n if (v33 < v5) {\n if (a2 == a1[v33]) result = (unsigned int)(result + 1);\n v34 = v20 + 3;\n if (v34 < v5) {\n if (a2 == a1[v34]) {\n result = (unsigned int)(result + 1);\n v35 = v20 + 4;\n if (v35 >= v5) return result;\n } else {\n v35 = v20 + 4;\n if (v35 >= v5) return result;\n }\n if (a2 == a1[v35]) result = (unsigned int)(result + 1);\n v36 = v20 + 5;\n if (v36 < v5) {\n if (a2 == a1[v36]) result = (unsigned int)(result + 1);\n v37 = v20 + 6;\n if (v37 < v5 && a2 == a1[v37]) return (unsigned int)(result + 1);\n }\n }\n }\n }\n }\n return result;\n}" + }, + { + "index": 205, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(const int test_tup[], int n, int res[]) {\n for (int i = 0; i < n; i++) {\n res[i] = ~test_tup[i];\n }\n}", + "test": "int main() {\n\n int res[6];\n\n\n\n int test1[] = {7, 8, 9, 1, 10, 7};\n\n int expected1[] = {-8, -9, -10, -2, -11, -8};\n\n func0(test1, 6, res);\n\n for (int i = 0; i < 6; i++) assert(res[i] == expected1[i]);\n\n\n\n int test2[] = {2, 4, 5, 6, 1, 7};\n\n int expected2[] = {-3, -5, -6, -7, -2, -8};\n\n func0(test2, 6, res);\n\n for (int i = 0; i < 6; i++) assert(res[i] == expected2[i]);\n\n\n\n int test3[] = {8, 9, 11, 14, 12, 13};\n\n int expected3[] = {-9, -10, -12, -15, -13, -14};\n\n func0(test3, 6, res);\n\n for (int i = 0; i < 6; i++) assert(res[i] == expected3[i]);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11d7 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nnot %edx\nmov %edx,(%rax)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11a5 \npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_4], 0\njmp short loc_11D7\nloc_11A5:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nnot edx\nmov [rax], edx\nadd [rbp+var_4], 1\nloc_11D7:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11A5\nnop\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+24h] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a2 )\n break;\n *(_DWORD *)(4LL * (int)i + a3) = ~*(_DWORD *)(4LL * (int)i + a1);\n }\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_4], 0\njmp short loc_11D7\nloc_11A5:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nnot edx\nmov [rax], edx\nadd [rbp+var_4], 1\nloc_11D7:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11A5\nnop\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2, __int64 a3)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+24h] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a2 )\n break;\n *(_DWORD *)(4LL * (int)i + a3) = ~*(_DWORD *)(4LL * (int)i + a1);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2, long long a3) {\n long long result;\n unsigned int i;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a2) break;\n *(uint32_t *)(4LL * (int)i + a3) = ~*(uint32_t *)(4LL * (int)i + a1);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3) {\n long long result;\n unsigned int i;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a2) break;\n *(uint32_t *)(4LL * (int)i + a3) = ~*(uint32_t *)(4LL * (int)i + a1);\n }\n return result;\n}" + }, + { + "index": 205, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(const int test_tup[], int n, int res[]) {\n for (int i = 0; i < n; i++) {\n res[i] = ~test_tup[i];\n }\n}", + "test": "int main() {\n\n int res[6];\n\n\n\n int test1[] = {7, 8, 9, 1, 10, 7};\n\n int expected1[] = {-8, -9, -10, -2, -11, -8};\n\n func0(test1, 6, res);\n\n for (int i = 0; i < 6; i++) assert(res[i] == expected1[i]);\n\n\n\n int test2[] = {2, 4, 5, 6, 1, 7};\n\n int expected2[] = {-3, -5, -6, -7, -2, -8};\n\n func0(test2, 6, res);\n\n for (int i = 0; i < 6; i++) assert(res[i] == expected2[i]);\n\n\n\n int test3[] = {8, 9, 11, 14, 12, 13};\n\n int expected3[] = {-9, -10, -12, -15, -13, -14};\n\n func0(test3, 6, res);\n\n for (int i = 0; i < 6; i++) assert(res[i] == expected3[i]);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11ad \nlea -0x1(%rsi),%esi\nmov $0x0,%eax\nmov (%rdi,%rax,4),%ecx\nnot %ecx\nmov %ecx,(%rdx,%rax,4)\nmov %rax,%rcx\nadd $0x1,%rax\ncmp %rsi,%rcx\njne 1199 \nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short locret_11AE\nmovsxd rsi, esi\nshl rsi, 2\nmov eax, 0\nloc_119D:\nmov ecx, [rdi+rax]\nnot ecx\nmov [rdx+rax], ecx\nadd rax, 4\ncmp rax, rsi\njnz short loc_119D\nlocret_11AE:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2, __int64 a3)\n{\n __int64 v3; // rsi\n __int64 v4; // rax\n\n if ( a2 > 0 )\n {\n v3 = 4LL * a2;\n v4 = 0LL;\n do\n {\n *(_DWORD *)(a3 + v4) = ~*(_DWORD *)(a1 + v4);\n v4 += 4LL;\n }\n while ( v4 != v3 );\n }\n}", + "ida_strip_asm": "sub_1189:\nendbr64\ntest esi, esi\njle short locret_11AE\nmovsxd rsi, esi\nshl rsi, 2\nmov eax, 0\nloc_119D:\nmov ecx, [rdi+rax]\nnot ecx\nmov [rdx+rax], ecx\nadd rax, 4\ncmp rax, rsi\njnz short loc_119D\nlocret_11AE:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1189(__int64 a1, int a2, __int64 a3)\n{\n __int64 v3; // rsi\n __int64 v4; // rax\n\n if ( a2 > 0 )\n {\n v3 = 4LL * a2;\n v4 = 0LL;\n do\n {\n *(_DWORD *)(a3 + v4) = ~*(_DWORD *)(a1 + v4);\n v4 += 4LL;\n }\n while ( v4 != v3 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1189(long long a1, int a2, long long a3) {\n long long v3;\n long long v4;\n if (a2 > 0) {\n v3 = 4LL * a2;\n v4 = 0LL;\n do {\n *(uint32_t *)(a3 + v4) = ~*(uint32_t *)(a1 + v4);\n v4 += 4LL;\n } while (v4 != v3);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2, long long a3) {\n long long v3;\n long long v4;\n if (a2 > 0) {\n v3 = 4LL * a2;\n v4 = 0LL;\n do {\n *(uint32_t *)(a3 + v4) = ~*(uint32_t *)(a1 + v4);\n v4 += 4LL;\n } while (v4 != v3);\n }\n}" + }, + { + "index": 206, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(char* test_tup[], int size) {\n char** res = malloc((size - 1) * sizeof(char*));\n for (int i = 0; i < size - 1; i++) {\n res[i] = malloc(strlen(test_tup[i]) + strlen(test_tup[i + 1]) + 1);\n strcpy(res[i], test_tup[i]);\n strcat(res[i], test_tup[i + 1]);\n }\n return res;\n}", + "test": "int main() {\n\n // First test case\n\n char* test1[] = {\"DSP \", \"IS \", \"BEST \", \"FOR \", \"ALL \", \"UTS\"};\n\n char* expected1[] = {\"DSP IS \", \"IS BEST \", \"BEST FOR \", \"FOR ALL \", \"ALL UTS\"};\n\n char** result1 = func0(test1, 6);\n\n for(int i = 0; i < 5; i++) {\n\n assert(strcmp(result1[i], expected1[i]) == 0);\n\n free(result1[i]);\n\n }\n\n free(result1);\n\n\n\n // Second test case\n\n char* test2[] = {\"RES \", \"IS \", \"BEST \", \"FOR \", \"ALL \", \"QESR\"};\n\n char* expected2[] = {\"RES IS \", \"IS BEST \", \"BEST FOR \", \"FOR ALL \", \"ALL QESR\"};\n\n char** result2 = func0(test2, 6);\n\n for(int i = 0; i < 5; i++) {\n\n assert(strcmp(result2[i], expected2[i]) == 0);\n\n free(result2[i]);\n\n }\n\n free(result2);\n\n\n\n // Third test case\n\n char* test3[] = {\"MSAM\", \"IS \", \"BEST \", \"FOR \", \"ALL \", \"SKD\"};\n\n char* expected3[] = {\"MSAMIS \", \"IS BEST \", \"BEST FOR \", \"FOR ALL \", \"ALL SKD\"};\n\n char** result3 = func0(test3, 6);\n\n for(int i = 0; i < 5; i++) {\n\n assert(strcmp(result3[i], expected3[i]) == 0);\n\n free(result3[i]);\n\n }\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x28,%rsp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmov -0x2c(%rbp),%eax\nsub $0x1,%eax\ncltq\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 1120 \nmov %rax,-0x18(%rbp)\nmovl $0x0,-0x1c(%rbp)\njmpq 1348 \nmov -0x1c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov %rax,%rdi\ncallq 10e0 \nmov %rax,%rbx\nmov -0x1c(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,8),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov %rax,%rdi\ncallq 10e0 \nadd %rbx,%rax\nadd $0x1,%rax\nmov -0x1c(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x18(%rbp),%rdx\nlea (%rcx,%rdx,1),%rbx\nmov %rax,%rdi\ncallq 1120 \nmov %rax,(%rbx)\nmov -0x1c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rdx\nmov -0x1c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10d0 \nmov -0x1c(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,8),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rdx\nmov -0x1c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1130 \naddl $0x1,-0x1c(%rbp)\nmov -0x2c(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x1c(%rbp)\njl 1261 \nmov -0x18(%rbp),%rax\nadd $0x28,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov eax, [rbp+var_2C]\nsub eax, 1\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_1C], 0\njmp loc_1348\nloc_1261:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; s\ncall _strlen\nmov rbx, rax\nmov eax, [rbp+var_1C]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; s\ncall _strlen\nadd rax, rbx\nadd rax, 1\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nlea rbx, [rcx+rdx]\nmov rdi, rax; size\ncall _malloc\nmov [rbx], rax\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_1C]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\nmov eax, [rbp+var_1C]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_1C]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\nadd [rbp+var_1C], 1\nloc_1348:\nmov eax, [rbp+var_2C]\nsub eax, 1\ncmp [rbp+var_1C], eax\njl loc_1261\nmov rax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, int a2)\n{\n size_t v2; // rbx\n size_t v3; // rax\n int i; // [rsp+14h] [rbp-1Ch]\n _QWORD *v6; // [rsp+18h] [rbp-18h]\n\n v6 = malloc(8LL * (a2 - 1));\n for ( i = 0; i < a2 - 1; ++i )\n {\n v2 = strlen(*(const char **)(8LL * i + a1));\n v3 = v2 + strlen(*(const char **)(8 * (i + 1LL) + a1)) + 1;\n v6[i] = malloc(v3);\n strcpy((char *)v6[i], *(const char **)(8LL * i + a1));\n strcat((char *)v6[i], *(const char **)(8 * (i + 1LL) + a1));\n }\n return v6;\n}", + "ida_strip_asm": "sub_1229:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov eax, [rbp+var_2C]\nsub eax, 1\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_1C], 0\njmp loc_1348\nloc_1261:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; s\ncall _strlen\nmov rbx, rax\nmov eax, [rbp+var_1C]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; s\ncall _strlen\nadd rax, rbx\nadd rax, 1\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nlea rbx, [rcx+rdx]\nmov rdi, rax; size\ncall _malloc\nmov [rbx], rax\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_1C]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\nmov eax, [rbp+var_1C]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_1C]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\nadd [rbp+var_1C], 1\nloc_1348:\nmov eax, [rbp+var_2C]\nsub eax, 1\ncmp [rbp+var_1C], eax\njl loc_1261\nmov rax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1229(__int64 a1, int a2)\n{\n size_t v2; // rbx\n size_t v3; // rax\n int i; // [rsp+14h] [rbp-1Ch]\n _QWORD *v6; // [rsp+18h] [rbp-18h]\n\n v6 = malloc(8LL * (a2 - 1));\n for ( i = 0; i < a2 - 1; ++i )\n {\n v2 = strlen(*(const char **)(8LL * i + a1));\n v3 = v2 + strlen(*(const char **)(8 * (i + 1LL) + a1)) + 1;\n v6[i] = malloc(v3);\n strcpy((char *)v6[i], *(const char **)(8LL * i + a1));\n strcat((char *)v6[i], *(const char **)(8 * (i + 1LL) + a1));\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1229(long long a1, int a2) {\n unsigned int v2;\n unsigned int v3;\n int i;\n uint64_t *v6;\n v6 = malloc(8LL * (a2 - 1));\n for (i = 0; i < a2 - 1; ++i) {\n v2 = strlen(*(const char **)(8LL * i + a1));\n v3 = v2 + strlen(*(const char **)(8 * (i + 1LL) + a1)) + 1;\n v6[i] = malloc(v3);\n strcpy((char *)v6[i], *(const char **)(8LL * i + a1));\n strcat((char *)v6[i], *(const char **)(8 * (i + 1LL) + a1));\n }\n return v6;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, int a2) {\n unsigned int v2;\n unsigned int v3;\n int i;\n uint64_t *v6;\n v6 = malloc(8LL * (a2 - 1));\n for (i = 0; i < a2 - 1; ++i) {\n v2 = strlen(*(const char **)(8LL * i + a1));\n v3 = v2 + strlen(*(const char **)(8 * (i + 1LL) + a1)) + 1;\n v6[i] = malloc(v3);\n strcpy((char *)v6[i], *(const char **)(8LL * i + a1));\n strcat((char *)v6[i], *(const char **)(8 * (i + 1LL) + a1));\n }\n return v6;\n}" + }, + { + "index": 206, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(char* test_tup[], int size) {\n char** res = malloc((size - 1) * sizeof(char*));\n for (int i = 0; i < size - 1; i++) {\n res[i] = malloc(strlen(test_tup[i]) + strlen(test_tup[i + 1]) + 1);\n strcpy(res[i], test_tup[i]);\n strcat(res[i], test_tup[i + 1]);\n }\n return res;\n}", + "test": "int main() {\n\n // First test case\n\n char* test1[] = {\"DSP \", \"IS \", \"BEST \", \"FOR \", \"ALL \", \"UTS\"};\n\n char* expected1[] = {\"DSP IS \", \"IS BEST \", \"BEST FOR \", \"FOR ALL \", \"ALL UTS\"};\n\n char** result1 = func0(test1, 6);\n\n for(int i = 0; i < 5; i++) {\n\n assert(strcmp(result1[i], expected1[i]) == 0);\n\n free(result1[i]);\n\n }\n\n free(result1);\n\n\n\n // Second test case\n\n char* test2[] = {\"RES \", \"IS \", \"BEST \", \"FOR \", \"ALL \", \"QESR\"};\n\n char* expected2[] = {\"RES IS \", \"IS BEST \", \"BEST FOR \", \"FOR ALL \", \"ALL QESR\"};\n\n char** result2 = func0(test2, 6);\n\n for(int i = 0; i < 5; i++) {\n\n assert(strcmp(result2[i], expected2[i]) == 0);\n\n free(result2[i]);\n\n }\n\n free(result2);\n\n\n\n // Third test case\n\n char* test3[] = {\"MSAM\", \"IS \", \"BEST \", \"FOR \", \"ALL \", \"SKD\"};\n\n char* expected3[] = {\"MSAMIS \", \"IS BEST \", \"BEST FOR \", \"FOR ALL \", \"ALL SKD\"};\n\n char** result3 = func0(test3, 6);\n\n for(int i = 0; i < 5; i++) {\n\n assert(strcmp(result3[i], expected3[i]) == 0);\n\n free(result3[i]);\n\n }\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov %rdi,%rbp\nmov %esi,%ebx\nlea -0x1(%rsi),%r12d\nmovslq %r12d,%rdi\nshl $0x3,%rdi\ncallq 1100 \nmov %rax,0x8(%rsp)\ntest %r12d,%r12d\njle 12b5 \nmov %rax,%rsi\nmov %rax,%r12\nadd $0x8,%rbp\nlea -0x2(%rbx),%eax\nlea 0x8(%rsi,%rax,8),%rax\nmov %rax,(%rsp)\nmov $0xffffffffffffffff,%r15\nmov -0x8(%rbp),%r14\nmov $0x0,%eax\nmov %r15,%rcx\nmov %r14,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rdx\nnot %rdx\nmov 0x0(%rbp),%r13\nmov %r15,%rcx\nmov %r13,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rdx,%rax,1),%rdi\ncallq 1100 \nmov %rax,%rbx\nmov %rax,(%r12)\nmov %r14,%rsi\nmov %rax,%rdi\ncallq 10c0 \nmov %r13,%rsi\nmov %rbx,%rdi\ncallq 1110 \nadd $0x8,%r12\nadd $0x8,%rbp\ncmp (%rsp),%r12\njne 1257 \nmov 0x8(%rsp),%rax\nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov rbp, rdi\nmov ebx, esi\nlea r12d, [rsi-1]\nmovsxd rdi, r12d\nshl rdi, 3; size\ncall _malloc\nmov [rsp+48h+var_40], rax\ntest r12d, r12d\njle short loc_12CB\nmov rcx, rax\nmov r12, rax\nadd rbp, 8\nlea eax, [rbx-1]\nlea rax, [rcx+rax*8]\nmov [rsp+48h+var_48], rax\nloc_126F:\nmov r15, [rbp-8]\nmov rdi, r15; s\ncall _strlen\nmov rbx, rax\nmov r14, [rbp+0]\nmov rdi, r14; s\ncall _strlen\nlea r13, [rbx+rax+1]\nmov rdi, r13; size\ncall _malloc\nmov rbx, rax\nmov [r12], rax\nmov rdx, r13\nmov rsi, r15\nmov rdi, rax\ncall ___strcpy_chk\nmov rdx, r13\nmov rsi, r14\nmov rdi, rbx\ncall ___strcat_chk\nadd r12, 8\nadd rbp, 8\nmov rax, [rsp+48h+var_48]\ncmp r12, rax\njnz short loc_126F\nloc_12CB:\nmov rax, [rsp+48h+var_40]\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, int a2)\n{\n _QWORD *v2; // rax\n _QWORD *v3; // r12\n const char **v4; // rbp\n const char *v5; // r15\n size_t v6; // rbx\n const char *v7; // r14\n size_t v8; // r13\n void *v9; // rbx\n _QWORD *v11; // [rsp+0h] [rbp-48h]\n _QWORD *v12; // [rsp+8h] [rbp-40h]\n\n v2 = malloc(8LL * (a2 - 1));\n v12 = v2;\n if ( a2 - 1 > 0 )\n {\n v3 = v2;\n v4 = (const char **)(a1 + 8);\n v11 = &v2[a2 - 1];\n do\n {\n v5 = *(v4 - 1);\n v6 = strlen(v5);\n v7 = *v4;\n v8 = v6 + strlen(*v4) + 1;\n v9 = malloc(v8);\n *v3 = v9;\n __strcpy_chk(v9, v5, v8);\n __strcat_chk(v9, v7, v8);\n ++v3;\n ++v4;\n }\n while ( v3 != v11 );\n }\n return v12;\n}", + "ida_strip_asm": "sub_1229:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov rbp, rdi\nmov ebx, esi\nlea r12d, [rsi-1]\nmovsxd rdi, r12d\nshl rdi, 3; size\ncall _malloc\nmov [rsp+48h+var_40], rax\ntest r12d, r12d\njle short loc_12CB\nmov rcx, rax\nmov r12, rax\nadd rbp, 8\nlea eax, [rbx-1]\nlea rax, [rcx+rax*8]\nmov [rsp+48h+var_48], rax\nloc_126F:\nmov r15, [rbp-8]\nmov rdi, r15; s\ncall _strlen\nmov rbx, rax\nmov r14, [rbp+0]\nmov rdi, r14; s\ncall _strlen\nlea r13, [rbx+rax+1]\nmov rdi, r13; size\ncall _malloc\nmov rbx, rax\nmov [r12], rax\nmov rdx, r13\nmov rsi, r15\nmov rdi, rax\ncall ___strcpy_chk\nmov rdx, r13\nmov rsi, r14\nmov rdi, rbx\ncall ___strcat_chk\nadd r12, 8\nadd rbp, 8\nmov rax, [rsp+48h+var_48]\ncmp r12, rax\njnz short loc_126F\nloc_12CB:\nmov rax, [rsp+48h+var_40]\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1229(__int64 a1, int a2)\n{\n _QWORD *v2; // rax\n _QWORD *v3; // r12\n const char **v4; // rbp\n const char *v5; // r15\n size_t v6; // rbx\n const char *v7; // r14\n size_t v8; // r13\n void *v9; // rbx\n _QWORD *v11; // [rsp+0h] [rbp-48h]\n _QWORD *v12; // [rsp+8h] [rbp-40h]\n\n v2 = malloc(8LL * (a2 - 1));\n v12 = v2;\n if ( a2 - 1 > 0 )\n {\n v3 = v2;\n v4 = (const char **)(a1 + 8);\n v11 = &v2[a2 - 1];\n do\n {\n v5 = *(v4 - 1);\n v6 = strlen(v5);\n v7 = *v4;\n v8 = v6 + strlen(*v4) + 1;\n v9 = malloc(v8);\n *v3 = v9;\n __strcpy_chk(v9, v5, v8);\n __strcat_chk(v9, v7, v8);\n ++v3;\n ++v4;\n }\n while ( v3 != v11 );\n }\n return v12;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1229(long long a1, int a2) {\n uint64_t *v2;\n uint64_t *v3;\n const char **v4;\n const char *v5;\n unsigned int v6;\n const char *v7;\n unsigned int v8;\n void *v9;\n uint64_t *v11;\n uint64_t *v12;\n v2 = malloc(8LL * (a2 - 1));\n v12 = v2;\n if (a2 - 1 > 0) {\n v3 = v2;\n v4 = (const char **)(a1 + 8);\n v11 = &v2[a2 - 1];\n do {\n v5 = *(v4 - 1);\n v6 = strlen(v5);\n v7 = *v4;\n v8 = v6 + strlen(*v4) + 1;\n v9 = malloc(v8);\n *v3 = v9;\n __strcpy_chk(v9, v5, v8);\n __strcat_chk(v9, v7, v8);\n ++v3;\n ++v4;\n } while (v3 != v11);\n }\n return v12;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, int a2) {\n uint64_t *v2;\n uint64_t *v3;\n const char **v4;\n const char *v5;\n unsigned int v6;\n const char *v7;\n unsigned int v8;\n void *v9;\n uint64_t *v11;\n uint64_t *v12;\n v2 = malloc(8LL * (a2 - 1));\n v12 = v2;\n if (a2 - 1 > 0) {\n v3 = v2;\n v4 = (const char **)(a1 + 8);\n v11 = &v2[a2 - 1];\n do {\n v5 = *(v4 - 1);\n v6 = strlen(v5);\n v7 = *v4;\n v8 = v6 + strlen(*v4) + 1;\n v9 = malloc(v8);\n *v3 = v9;\n __strcpy_chk(v9, v5, v8);\n __strcat_chk(v9, v7, v8);\n ++v3;\n ++v4;\n } while (v3 != v11);\n }\n return v12;\n}" + }, + { + "index": 206, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(char* test_tup[], int size) {\n char** res = malloc((size - 1) * sizeof(char*));\n for (int i = 0; i < size - 1; i++) {\n res[i] = malloc(strlen(test_tup[i]) + strlen(test_tup[i + 1]) + 1);\n strcpy(res[i], test_tup[i]);\n strcat(res[i], test_tup[i + 1]);\n }\n return res;\n}", + "test": "int main() {\n\n // First test case\n\n char* test1[] = {\"DSP \", \"IS \", \"BEST \", \"FOR \", \"ALL \", \"UTS\"};\n\n char* expected1[] = {\"DSP IS \", \"IS BEST \", \"BEST FOR \", \"FOR ALL \", \"ALL UTS\"};\n\n char** result1 = func0(test1, 6);\n\n for(int i = 0; i < 5; i++) {\n\n assert(strcmp(result1[i], expected1[i]) == 0);\n\n free(result1[i]);\n\n }\n\n free(result1);\n\n\n\n // Second test case\n\n char* test2[] = {\"RES \", \"IS \", \"BEST \", \"FOR \", \"ALL \", \"QESR\"};\n\n char* expected2[] = {\"RES IS \", \"IS BEST \", \"BEST FOR \", \"FOR ALL \", \"ALL QESR\"};\n\n char** result2 = func0(test2, 6);\n\n for(int i = 0; i < 5; i++) {\n\n assert(strcmp(result2[i], expected2[i]) == 0);\n\n free(result2[i]);\n\n }\n\n free(result2);\n\n\n\n // Third test case\n\n char* test3[] = {\"MSAM\", \"IS \", \"BEST \", \"FOR \", \"ALL \", \"SKD\"};\n\n char* expected3[] = {\"MSAMIS \", \"IS BEST \", \"BEST FOR \", \"FOR ALL \", \"ALL SKD\"};\n\n char** result3 = func0(test3, 6);\n\n for(int i = 0; i < 5; i++) {\n\n assert(strcmp(result3[i], expected3[i]) == 0);\n\n free(result3[i]);\n\n }\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\nmov %esi,%r12d\npush %rbp\nlea -0x1(%rsi),%ebp\npush %rbx\nmov %rdi,%rbx\nmovslq %ebp,%rdi\nshl $0x3,%rdi\nsub $0x18,%rsp\ncallq 1130 \nmov %rax,0x8(%rsp)\ntest %ebp,%ebp\njle 1604 \nmov %rax,%rdx\nmov %rax,%rbp\nlea -0x2(%r12),%eax\nadd $0x8,%rbx\nlea 0x8(%rdx,%rax,8),%r12\nnopl 0x0(%rax)\nmov -0x8(%rbx),%r13\nadd $0x8,%rbp\nadd $0x8,%rbx\nmov %r13,%rdi\ncallq 10f0 \nmov -0x8(%rbx),%r15\nmov %rax,%r14\nmov %r15,%rdi\ncallq 10f0 \nlea 0x1(%r14,%rax,1),%rdi\ncallq 1130 \nmov %r13,%rsi\nmov %rax,-0x8(%rbp)\nmov %rax,%rdi\ncallq 10e0 \nmov %r15,%rsi\nmov %rax,%rdi\ncallq 10d0 \ncmp %r12,%rbp\njne 15b8 \nmov 0x8(%rsp),%rax\nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nlea ebx, [rsi-1]\nmovsxd rdi, ebx\nshl rdi, 3; size\nsub rsp, 18h\ncall _malloc\nmov [rsp+48h+var_40], rax\ntest ebx, ebx\njle short loc_167E\nmov ebx, ebx\nmov r12, rax\nadd rbp, 8\nlea rax, [rax+rbx*8]\nmov [rsp+48h+var_48], rax\nxchg ax, ax\nloc_1620:\nmov r13, [rbp-8]\nadd r12, 8\nadd rbp, 8\nmov rdi, r13; s\ncall _strlen\nmov r14, [rbp-8]\nmov rbx, rax\nmov rdi, r14; s\ncall _strlen\nlea r15, [rbx+rax+1]\nmov rdi, r15; size\ncall _malloc\nmov rdx, r15\nmov rsi, r13\nmov [r12-8], rax\nmov rdi, rax\nmov rbx, rax\ncall ___stpcpy_chk\nmov rsi, r14\nsub rbx, rax\nmov rdi, rax\nlea rdx, [rbx+r15]\ncall ___strcpy_chk\ncmp [rsp+48h+var_48], r12\njnz short loc_1620\nloc_167E:\nmov rax, [rsp+48h+var_40]\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2)\n{\n char *v2; // rax\n char *v3; // r12\n __int64 v4; // rbp\n const char *v5; // r13\n size_t v6; // rax\n const char *v7; // r14\n size_t v8; // r15\n char *v9; // rax\n char *v10; // rbx\n __int64 v11; // rax\n char *v13; // [rsp+0h] [rbp-48h]\n char *v14; // [rsp+8h] [rbp-40h]\n\n v2 = (char *)malloc(8LL * (a2 - 1));\n v14 = v2;\n if ( a2 - 1 > 0 )\n {\n v3 = v2;\n v4 = a1 + 8;\n v13 = &v2[8 * (a2 - 1)];\n do\n {\n v5 = *(const char **)(v4 - 8);\n v3 += 8;\n v4 += 8LL;\n v6 = strlen(v5);\n v7 = *(const char **)(v4 - 8);\n v8 = v6 + strlen(v7) + 1;\n v9 = (char *)malloc(v8);\n *((_QWORD *)v3 - 1) = v9;\n v10 = v9;\n v11 = __stpcpy_chk(v9, v5, v8);\n __strcpy_chk(v11, v7, &v10[v8 - v11]);\n }\n while ( v13 != v3 );\n }\n return v14;\n}", + "ida_strip_asm": "sub_15E0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nlea ebx, [rsi-1]\nmovsxd rdi, ebx\nshl rdi, 3; size\nsub rsp, 18h\ncall _malloc\nmov [rsp+48h+var_40], rax\ntest ebx, ebx\njle short loc_167E\nmov ebx, ebx\nmov r12, rax\nadd rbp, 8\nlea rax, [rax+rbx*8]\nmov [rsp+48h+var_48], rax\nxchg ax, ax\nloc_1620:\nmov r13, [rbp-8]\nadd r12, 8\nadd rbp, 8\nmov rdi, r13; s\ncall _strlen\nmov r14, [rbp-8]\nmov rbx, rax\nmov rdi, r14; s\ncall _strlen\nlea r15, [rbx+rax+1]\nmov rdi, r15; size\ncall _malloc\nmov rdx, r15\nmov rsi, r13\nmov [r12-8], rax\nmov rdi, rax\nmov rbx, rax\ncall ___stpcpy_chk\nmov rsi, r14\nsub rbx, rax\nmov rdi, rax\nlea rdx, [rbx+r15]\ncall ___strcpy_chk\ncmp [rsp+48h+var_48], r12\njnz short loc_1620\nloc_167E:\nmov rax, [rsp+48h+var_40]\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "char *__fastcall sub_15E0(__int64 a1, int a2)\n{\n char *v2; // rax\n char *v3; // r12\n __int64 v4; // rbp\n const char *v5; // r13\n size_t v6; // rax\n const char *v7; // r14\n size_t v8; // r15\n char *v9; // rax\n char *v10; // rbx\n __int64 v11; // rax\n char *v13; // [rsp+0h] [rbp-48h]\n char *v14; // [rsp+8h] [rbp-40h]\n\n v2 = (char *)malloc(8LL * (a2 - 1));\n v14 = v2;\n if ( a2 - 1 > 0 )\n {\n v3 = v2;\n v4 = a1 + 8;\n v13 = &v2[8 * (a2 - 1)];\n do\n {\n v5 = *(const char **)(v4 - 8);\n v3 += 8;\n v4 += 8LL;\n v6 = strlen(v5);\n v7 = *(const char **)(v4 - 8);\n v8 = v6 + strlen(v7) + 1;\n v9 = (char *)malloc(v8);\n *((_QWORD *)v3 - 1) = v9;\n v10 = v9;\n v11 = __stpcpy_chk(v9, v5, v8);\n __strcpy_chk(v11, v7, &v10[v8 - v11]);\n }\n while ( v13 != v3 );\n }\n return v14;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_15E0(long long a1, int a2) {\n char *v2;\n char *v3;\n long long v4;\n const char *v5;\n unsigned int v6;\n const char *v7;\n unsigned int v8;\n char *v9;\n char *v10;\n long long v11;\n char *v13;\n char *v14;\n v2 = (char *)malloc(8LL * (a2 - 1));\n v14 = v2;\n if (a2 - 1 > 0) {\n v3 = v2;\n v4 = a1 + 8;\n v13 = &v2[8 * (a2 - 1)];\n do {\n v5 = *(const char **)(v4 - 8);\n v3 += 8;\n v4 += 8LL;\n v6 = strlen(v5);\n v7 = *(const char **)(v4 - 8);\n v8 = v6 + strlen(v7) + 1;\n v9 = (char *)malloc(v8);\n *((uint64_t *)v3 - 1) = v9;\n v10 = v9;\n v11 = __stpcpy_chk(v9, v5, v8);\n __strcpy_chk(v11, v7, &v10[v8 - v11]);\n } while (v13 != v3);\n }\n return v14;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2) {\n char *v2;\n char *v3;\n long long v4;\n const char *v5;\n unsigned int v6;\n const char *v7;\n unsigned int v8;\n char *v9;\n char *v10;\n long long v11;\n char *v13;\n char *v14;\n v2 = (char *)malloc(8LL * (a2 - 1));\n v14 = v2;\n if (a2 - 1 > 0) {\n v3 = v2;\n v4 = a1 + 8;\n v13 = &v2[8 * (a2 - 1)];\n do {\n v5 = *(const char **)(v4 - 8);\n v3 += 8;\n v4 += 8LL;\n v6 = strlen(v5);\n v7 = *(const char **)(v4 - 8);\n v8 = v6 + strlen(v7) + 1;\n v9 = (char *)malloc(v8);\n *((uint64_t *)v3 - 1) = v9;\n v10 = v9;\n v11 = __stpcpy_chk(v9, v5, v8);\n __strcpy_chk(v11, v7, &v10[v8 - v11]);\n } while (v13 != v3);\n }\n return v14;\n}" + }, + { + "index": 206, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(char* test_tup[], int size) {\n char** res = malloc((size - 1) * sizeof(char*));\n for (int i = 0; i < size - 1; i++) {\n res[i] = malloc(strlen(test_tup[i]) + strlen(test_tup[i + 1]) + 1);\n strcpy(res[i], test_tup[i]);\n strcat(res[i], test_tup[i + 1]);\n }\n return res;\n}", + "test": "int main() {\n\n // First test case\n\n char* test1[] = {\"DSP \", \"IS \", \"BEST \", \"FOR \", \"ALL \", \"UTS\"};\n\n char* expected1[] = {\"DSP IS \", \"IS BEST \", \"BEST FOR \", \"FOR ALL \", \"ALL UTS\"};\n\n char** result1 = func0(test1, 6);\n\n for(int i = 0; i < 5; i++) {\n\n assert(strcmp(result1[i], expected1[i]) == 0);\n\n free(result1[i]);\n\n }\n\n free(result1);\n\n\n\n // Second test case\n\n char* test2[] = {\"RES \", \"IS \", \"BEST \", \"FOR \", \"ALL \", \"QESR\"};\n\n char* expected2[] = {\"RES IS \", \"IS BEST \", \"BEST FOR \", \"FOR ALL \", \"ALL QESR\"};\n\n char** result2 = func0(test2, 6);\n\n for(int i = 0; i < 5; i++) {\n\n assert(strcmp(result2[i], expected2[i]) == 0);\n\n free(result2[i]);\n\n }\n\n free(result2);\n\n\n\n // Third test case\n\n char* test3[] = {\"MSAM\", \"IS \", \"BEST \", \"FOR \", \"ALL \", \"SKD\"};\n\n char* expected3[] = {\"MSAMIS \", \"IS BEST \", \"BEST FOR \", \"FOR ALL \", \"ALL SKD\"};\n\n char** result3 = func0(test3, 6);\n\n for(int i = 0; i < 5; i++) {\n\n assert(strcmp(result3[i], expected3[i]) == 0);\n\n free(result3[i]);\n\n }\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\nmov %esi,%r12d\npush %rbp\nlea -0x1(%rsi),%ebp\npush %rbx\nmov %rdi,%rbx\nmovslq %ebp,%rdi\nshl $0x3,%rdi\nsub $0x18,%rsp\ncallq 1130 \nmov %rax,0x8(%rsp)\ntest %ebp,%ebp\njle 1604 \nmov %rax,%rdx\nmov %rax,%rbp\nlea -0x2(%r12),%eax\nadd $0x8,%rbx\nlea 0x8(%rdx,%rax,8),%r12\nnopl 0x0(%rax)\nmov -0x8(%rbx),%r13\nadd $0x8,%rbp\nadd $0x8,%rbx\nmov %r13,%rdi\ncallq 10f0 \nmov -0x8(%rbx),%r15\nmov %rax,%r14\nmov %r15,%rdi\ncallq 10f0 \nlea 0x1(%r14,%rax,1),%rdi\ncallq 1130 \nmov %r13,%rsi\nmov %rax,-0x8(%rbp)\nmov %rax,%rdi\ncallq 10e0 \nmov %r15,%rsi\nmov %rax,%rdi\ncallq 10d0 \ncmp %rbp,%r12\njne 15b8 \nmov 0x8(%rsp),%rax\nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nlea ebx, [rsi-1]\nmovsxd rdi, ebx\nshl rdi, 3; size\nsub rsp, 18h\ncall _malloc\nmov [rsp+48h+var_40], rax\ntest ebx, ebx\njle short loc_167E\nmov ebx, ebx\nmov r12, rax\nadd rbp, 8\nlea rax, [rax+rbx*8]\nmov [rsp+48h+var_48], rax\nxchg ax, ax\nloc_1620:\nmov r13, [rbp-8]\nadd r12, 8\nadd rbp, 8\nmov rdi, r13; s\ncall _strlen\nmov r14, [rbp-8]\nmov rbx, rax\nmov rdi, r14; s\ncall _strlen\nlea r15, [rbx+rax+1]\nmov rdi, r15; size\ncall _malloc\nmov rdx, r15\nmov rsi, r13\nmov [r12-8], rax\nmov rdi, rax\nmov rbx, rax\ncall ___stpcpy_chk\nmov rsi, r14\nsub rbx, rax\nmov rdi, rax\nlea rdx, [rbx+r15]\ncall ___strcpy_chk\ncmp [rsp+48h+var_48], r12\njnz short loc_1620\nloc_167E:\nmov rax, [rsp+48h+var_40]\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2)\n{\n char *v2; // rax\n char *v3; // r12\n __int64 v4; // rbp\n const char *v5; // r13\n size_t v6; // rax\n const char *v7; // r14\n size_t v8; // r15\n char *v9; // rax\n char *v10; // rbx\n __int64 v11; // rax\n char *v13; // [rsp+0h] [rbp-48h]\n char *v14; // [rsp+8h] [rbp-40h]\n\n v2 = (char *)malloc(8LL * (a2 - 1));\n v14 = v2;\n if ( a2 - 1 > 0 )\n {\n v3 = v2;\n v4 = a1 + 8;\n v13 = &v2[8 * (a2 - 1)];\n do\n {\n v5 = *(const char **)(v4 - 8);\n v3 += 8;\n v4 += 8LL;\n v6 = strlen(v5);\n v7 = *(const char **)(v4 - 8);\n v8 = v6 + strlen(v7) + 1;\n v9 = (char *)malloc(v8);\n *((_QWORD *)v3 - 1) = v9;\n v10 = v9;\n v11 = __stpcpy_chk(v9, v5, v8);\n __strcpy_chk(v11, v7, &v10[v8 - v11]);\n }\n while ( v13 != v3 );\n }\n return v14;\n}", + "ida_strip_asm": "sub_15E0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nlea ebx, [rsi-1]\nmovsxd rdi, ebx\nshl rdi, 3; size\nsub rsp, 18h\ncall _malloc\nmov [rsp+48h+var_40], rax\ntest ebx, ebx\njle short loc_167E\nmov ebx, ebx\nmov r12, rax\nadd rbp, 8\nlea rax, [rax+rbx*8]\nmov [rsp+48h+var_48], rax\nxchg ax, ax\nloc_1620:\nmov r13, [rbp-8]\nadd r12, 8\nadd rbp, 8\nmov rdi, r13; s\ncall _strlen\nmov r14, [rbp-8]\nmov rbx, rax\nmov rdi, r14; s\ncall _strlen\nlea r15, [rbx+rax+1]\nmov rdi, r15; size\ncall _malloc\nmov rdx, r15\nmov rsi, r13\nmov [r12-8], rax\nmov rdi, rax\nmov rbx, rax\ncall ___stpcpy_chk\nmov rsi, r14\nsub rbx, rax\nmov rdi, rax\nlea rdx, [rbx+r15]\ncall ___strcpy_chk\ncmp [rsp+48h+var_48], r12\njnz short loc_1620\nloc_167E:\nmov rax, [rsp+48h+var_40]\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "char *__fastcall sub_15E0(__int64 a1, int a2)\n{\n char *v2; // rax\n char *v3; // r12\n __int64 v4; // rbp\n const char *v5; // r13\n size_t v6; // rax\n const char *v7; // r14\n size_t v8; // r15\n char *v9; // rax\n char *v10; // rbx\n __int64 v11; // rax\n char *v13; // [rsp+0h] [rbp-48h]\n char *v14; // [rsp+8h] [rbp-40h]\n\n v2 = (char *)malloc(8LL * (a2 - 1));\n v14 = v2;\n if ( a2 - 1 > 0 )\n {\n v3 = v2;\n v4 = a1 + 8;\n v13 = &v2[8 * (a2 - 1)];\n do\n {\n v5 = *(const char **)(v4 - 8);\n v3 += 8;\n v4 += 8LL;\n v6 = strlen(v5);\n v7 = *(const char **)(v4 - 8);\n v8 = v6 + strlen(v7) + 1;\n v9 = (char *)malloc(v8);\n *((_QWORD *)v3 - 1) = v9;\n v10 = v9;\n v11 = __stpcpy_chk(v9, v5, v8);\n __strcpy_chk(v11, v7, &v10[v8 - v11]);\n }\n while ( v13 != v3 );\n }\n return v14;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_15E0(long long a1, int a2) {\n char *v2;\n char *v3;\n long long v4;\n const char *v5;\n unsigned int v6;\n const char *v7;\n unsigned int v8;\n char *v9;\n char *v10;\n long long v11;\n char *v13;\n char *v14;\n v2 = (char *)malloc(8LL * (a2 - 1));\n v14 = v2;\n if (a2 - 1 > 0) {\n v3 = v2;\n v4 = a1 + 8;\n v13 = &v2[8 * (a2 - 1)];\n do {\n v5 = *(const char **)(v4 - 8);\n v3 += 8;\n v4 += 8LL;\n v6 = strlen(v5);\n v7 = *(const char **)(v4 - 8);\n v8 = v6 + strlen(v7) + 1;\n v9 = (char *)malloc(v8);\n *((uint64_t *)v3 - 1) = v9;\n v10 = v9;\n v11 = __stpcpy_chk(v9, v5, v8);\n __strcpy_chk(v11, v7, &v10[v8 - v11]);\n } while (v13 != v3);\n }\n return v14;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2) {\n char *v2;\n char *v3;\n long long v4;\n const char *v5;\n unsigned int v6;\n const char *v7;\n unsigned int v8;\n char *v9;\n char *v10;\n long long v11;\n char *v13;\n char *v14;\n v2 = (char *)malloc(8LL * (a2 - 1));\n v14 = v2;\n if (a2 - 1 > 0) {\n v3 = v2;\n v4 = a1 + 8;\n v13 = &v2[8 * (a2 - 1)];\n do {\n v5 = *(const char **)(v4 - 8);\n v3 += 8;\n v4 += 8LL;\n v6 = strlen(v5);\n v7 = *(const char **)(v4 - 8);\n v8 = v6 + strlen(v7) + 1;\n v9 = (char *)malloc(v8);\n *((uint64_t *)v3 - 1) = v9;\n v10 = v9;\n v11 = __stpcpy_chk(v9, v5, v8);\n __strcpy_chk(v11, v7, &v10[v8 - v11]);\n } while (v13 != v3);\n }\n return v14;\n}" + }, + { + "index": 207, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char *str) {\n int n = strlen(str);\n int dp[n + 1][n + 1];\n for (int i = 0; i <= n; i++) {\n for (int j = 0; j <= n; j++) {\n dp[i][j] = 0;\n }\n }\n for (int i = 1; i <= n; i++) {\n for (int j = 1; j <= n; j++) {\n if (str[i - 1] == str[j - 1] && i != j) {\n dp[i][j] = 1 + dp[i - 1][j - 1];\n } else {\n dp[i][j] = (dp[i][j - 1] > dp[i - 1][j]) ? dp[i][j - 1] : dp[i - 1][j];\n }\n }\n }\n return dp[n][n];\n}", + "test": "int main() {\n\n assert(func0(\"AABEBCDD\") == 3);\n\n assert(func0(\"aabb\") == 2);\n\n assert(func0(\"aab\") == 1);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0x88,%rsp\nmov %rdi,-0x78(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nmov %rsp,%rax\nmov %rax,%rbx\nmov -0x78(%rbp),%rax\nmov %rax,%rdi\ncallq 1070 \nmov %eax,-0x54(%rbp)\nmov -0x54(%rbp),%eax\nlea 0x1(%rax),%esi\nmov -0x54(%rbp),%eax\nlea 0x1(%rax),%edi\nmovslq %esi,%rax\nsub $0x1,%rax\nmov %rax,-0x50(%rbp)\nmovslq %esi,%rax\nmov %rax,-0xb0(%rbp)\nmovq $0x0,-0xa8(%rbp)\nmovslq %esi,%rax\nlea 0x0(,%rax,4),%rcx\nmovslq %edi,%rax\nsub $0x1,%rax\nmov %rax,-0x48(%rbp)\nmovslq %esi,%rax\nmov %rax,-0xa0(%rbp)\nmovq $0x0,-0x98(%rbp)\nmovslq %edi,%rax\nmov %rax,-0x90(%rbp)\nmovq $0x0,-0x88(%rbp)\nmov -0xa0(%rbp),%r9\nmov -0x98(%rbp),%r10\nmov %r10,%rdx\nimul -0x90(%rbp),%rdx\nmov -0x88(%rbp),%rax\nimul %r9,%rax\nlea (%rdx,%rax,1),%r8\nmov %r9,%rax\nmulq -0x90(%rbp)\nadd %rdx,%r8\nmov %r8,%rdx\nmovslq %esi,%rax\nmov %rax,%r14\nmov $0x0,%r15d\nmovslq %edi,%rax\nmov %rax,%r12\nmov $0x0,%r13d\nmov %r15,%rdx\nimul %r12,%rdx\nmov %r13,%rax\nimul %r14,%rax\nlea (%rdx,%rax,1),%r8\nmov %r14,%rax\nmul %r12\nadd %rdx,%r8\nmov %r8,%rdx\nmovslq %esi,%rdx\nmovslq %edi,%rax\nimul %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%edi\nmov $0x0,%edx\ndiv %rdi\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rdi\nsub %rdx,%rdi\nmov %rdi,%rdx\ncmp %rdx,%rsp\nje 12fc \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 12e5 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 1326 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x40(%rbp)\nmovl $0x0,-0x58(%rbp)\njmp 1380 \nmovl $0x0,-0x5c(%rbp)\njmp 1374 \nmov %rcx,%rdi\nshr $0x2,%rdi\nmov -0x40(%rbp),%rax\nmov -0x5c(%rbp),%edx\nmovslq %edx,%rsi\nmov -0x58(%rbp),%edx\nmovslq %edx,%rdx\nimul %rdi,%rdx\nadd %rsi,%rdx\nmovl $0x0,(%rax,%rdx,4)\naddl $0x1,-0x5c(%rbp)\nmov -0x5c(%rbp),%eax\ncmp -0x54(%rbp),%eax\njle 134b \naddl $0x1,-0x58(%rbp)\nmov -0x58(%rbp),%eax\ncmp -0x54(%rbp),%eax\njle 1342 \nmovl $0x1,-0x60(%rbp)\njmpq 14a2 \nmovl $0x1,-0x64(%rbp)\njmpq 1492 \nmov -0x60(%rbp),%eax\ncltq\nlea -0x1(%rax),%rdx\nmov -0x78(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%edx\nmov -0x64(%rbp),%eax\ncltq\nlea -0x1(%rax),%rsi\nmov -0x78(%rbp),%rax\nadd %rsi,%rax\nmovzbl (%rax),%eax\ncmp %al,%dl\njne 141f \nmov -0x60(%rbp),%eax\ncmp -0x64(%rbp),%eax\nje 141f \nmov %rcx,%rdi\nshr $0x2,%rdi\nmov -0x60(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x64(%rbp),%eax\nlea -0x1(%rax),%esi\nmov -0x40(%rbp),%rax\nmovslq %esi,%rsi\nmovslq %edx,%rdx\nimul %rdi,%rdx\nadd %rsi,%rdx\nmov (%rax,%rdx,4),%eax\nmov %rcx,%r8\nshr $0x2,%r8\nlea 0x1(%rax),%esi\nmov -0x40(%rbp),%rax\nmov -0x64(%rbp),%edx\nmovslq %edx,%rdi\nmov -0x60(%rbp),%edx\nmovslq %edx,%rdx\nimul %r8,%rdx\nadd %rdi,%rdx\nmov %esi,(%rax,%rdx,4)\njmp 148e \nmov %rcx,%rdi\nshr $0x2,%rdi\nmov -0x60(%rbp),%eax\nlea -0x1(%rax),%r8d\nmov -0x40(%rbp),%rax\nmov -0x64(%rbp),%edx\nmovslq %edx,%rsi\nmovslq %r8d,%rdx\nimul %rdi,%rdx\nadd %rsi,%rdx\nmov (%rax,%rdx,4),%edx\nmov %rcx,%r8\nshr $0x2,%r8\nmov -0x64(%rbp),%eax\nlea -0x1(%rax),%esi\nmov -0x40(%rbp),%rax\nmovslq %esi,%rdi\nmov -0x60(%rbp),%esi\nmovslq %esi,%rsi\nimul %r8,%rsi\nadd %rdi,%rsi\nmov (%rax,%rsi,4),%eax\nmov %rcx,%r8\nshr $0x2,%r8\ncmp %eax,%edx\ncmovl %eax,%edx\nmov -0x40(%rbp),%rax\nmov -0x64(%rbp),%esi\nmovslq %esi,%rdi\nmov -0x60(%rbp),%esi\nmovslq %esi,%rsi\nimul %r8,%rsi\nadd %rdi,%rsi\nmov %edx,(%rax,%rsi,4)\naddl $0x1,-0x64(%rbp)\nmov -0x64(%rbp),%eax\ncmp -0x54(%rbp),%eax\njle 13a0 \naddl $0x1,-0x60(%rbp)\nmov -0x60(%rbp),%eax\ncmp -0x54(%rbp),%eax\njle 1394 \nshr $0x2,%rcx\nmov %rcx,%rdx\nmov -0x40(%rbp),%rax\nlea 0x1(%rdx),%rcx\nmov -0x54(%rbp),%edx\nmovslq %edx,%rdx\nimul %rcx,%rdx\nmov (%rax,%rdx,4),%eax\nmov %rbx,%rsp\nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\nje 14e1 \ncallq 1080 <__stack_chk_fail@plt>\nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 58h\nmov [rbp+s], rdi\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov rax, rsp\nmov rbx, rax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_34], eax\nmov eax, [rbp+var_34]\nlea r8d, [rax+1]\nmov eax, [rbp+var_34]\nlea r9d, [rax+1]\nmovsxd rax, r8d\nsub rax, 1\nmov [rbp+var_30], rax\nmovsxd rax, r8d\nlea rcx, ds:0[rax*4]\nmovsxd rax, r9d\nsub rax, 1\nmov [rbp+var_28], rax\nmovsxd rax, r8d\nmov rsi, rax\nmov edi, 0\nmovsxd rax, r9d\nmov rax, rax\nmov edx, 0\nmov r11, rdi\nimul r11, rax\nmov r10, rdx\nimul r10, rsi\nadd r10, r11\nmul rsi\nlea rsi, [r10+rdx]\nmov rdx, rsi\nmovsxd rax, r8d\nmov rsi, rax\nmov edi, 0\nmovsxd rax, r9d\nmov rax, rax\nmov edx, 0\nmov r11, rdi\nimul r11, rax\nmov r10, rdx\nimul r10, rsi\nadd r10, r11\nmul rsi\nlea rsi, [r10+rdx]\nmov rdx, rsi\nmovsxd rdx, r8d\nmovsxd rax, r9d\nimul rax, rdx\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rsi, rax\nand rsi, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rsi\nloc_128E:\ncmp rsp, rdx\njz short loc_12A5\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\njmp short loc_128E\nloc_12A5:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_12CF\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_12CF:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_20], rax\nmov [rbp+var_44], 0\njmp short loc_1329\nloc_12EB:\nmov [rbp+var_40], 0\njmp short loc_131D\nloc_12F4:\nmov rdi, rcx\nshr rdi, 2\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_40]\nmovsxd rsi, edx\nmov edx, [rbp+var_44]\nmovsxd rdx, edx\nimul rdx, rdi\nadd rdx, rsi\nmov dword ptr [rax+rdx*4], 0\nadd [rbp+var_40], 1\nloc_131D:\nmov eax, [rbp+var_40]\ncmp eax, [rbp+var_34]\njle short loc_12F4\nadd [rbp+var_44], 1\nloc_1329:\nmov eax, [rbp+var_44]\ncmp eax, [rbp+var_34]\njle short loc_12EB\nmov [rbp+var_3C], 1\njmp loc_144B\nloc_133D:\nmov [rbp+var_38], 1\njmp loc_143B\nloc_1349:\nmov eax, [rbp+var_3C]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_38]\ncdqe\nlea rsi, [rax-1]\nmov rax, [rbp+s]\nadd rax, rsi\nmovzx eax, byte ptr [rax]\ncmp dl, al\njnz short loc_13C8\nmov eax, [rbp+var_3C]\ncmp eax, [rbp+var_38]\njz short loc_13C8\nmov rdi, rcx\nshr rdi, 2\nmov eax, [rbp+var_3C]\nlea edx, [rax-1]\nmov eax, [rbp+var_38]\nlea esi, [rax-1]\nmov rax, [rbp+var_20]\nmovsxd rsi, esi\nmovsxd rdx, edx\nimul rdx, rdi\nadd rdx, rsi\nmov eax, [rax+rdx*4]\nmov r8, rcx\nshr r8, 2\nlea esi, [rax+1]\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_38]\nmovsxd rdi, edx\nmov edx, [rbp+var_3C]\nmovsxd rdx, edx\nimul rdx, r8\nadd rdx, rdi\nmov [rax+rdx*4], esi\njmp short loc_1437\nloc_13C8:\nmov rdi, rcx\nshr rdi, 2\nmov eax, [rbp+var_3C]\nlea r8d, [rax-1]\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_38]\nmovsxd rsi, edx\nmovsxd rdx, r8d\nimul rdx, rdi\nadd rdx, rsi\nmov edx, [rax+rdx*4]\nmov r8, rcx\nshr r8, 2\nmov eax, [rbp+var_38]\nlea esi, [rax-1]\nmov rax, [rbp+var_20]\nmovsxd rdi, esi\nmov esi, [rbp+var_3C]\nmovsxd rsi, esi\nimul rsi, r8\nadd rsi, rdi\nmov eax, [rax+rsi*4]\nmov r8, rcx\nshr r8, 2\ncmp edx, eax\ncmovl edx, eax\nmov rax, [rbp+var_20]\nmov esi, [rbp+var_38]\nmovsxd rdi, esi\nmov esi, [rbp+var_3C]\nmovsxd rsi, esi\nimul rsi, r8\nadd rsi, rdi\nmov [rax+rsi*4], edx\nloc_1437:\nadd [rbp+var_38], 1\nloc_143B:\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_34]\njle loc_1349\nadd [rbp+var_3C], 1\nloc_144B:\nmov eax, [rbp+var_3C]\ncmp eax, [rbp+var_34]\njle loc_133D\nshr rcx, 2\nmov rdx, rcx\nmov rax, [rbp+var_20]\nlea rcx, [rdx+1]\nmov edx, [rbp+var_34]\nmovsxd rdx, edx\nimul rdx, rcx\nmov eax, [rax+rdx*4]\nmov rsp, rbx\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njz short loc_148A\ncall ___stack_chk_fail\nloc_148A:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(char *a1)\n{\n unsigned __int64 v1; // rcx\n unsigned __int64 v2; // rax\n void *v3; // rsp\n int v4; // edx\n _BYTE v6[8]; // [rsp+8h] [rbp-60h] BYREF\n char *s; // [rsp+10h] [rbp-58h]\n int i; // [rsp+24h] [rbp-44h]\n int j; // [rsp+28h] [rbp-40h]\n int k; // [rsp+2Ch] [rbp-3Ch]\n int m; // [rsp+30h] [rbp-38h]\n int v12; // [rsp+34h] [rbp-34h]\n __int64 v13; // [rsp+38h] [rbp-30h]\n __int64 v14; // [rsp+40h] [rbp-28h]\n _BYTE *v15; // [rsp+48h] [rbp-20h]\n unsigned __int64 v16; // [rsp+50h] [rbp-18h]\n\n s = a1;\n v16 = __readfsqword(0x28u);\n v12 = strlen(a1);\n v13 = v12 + 1 - 1LL;\n v1 = 4LL * (v12 + 1);\n v14 = v13;\n v2 = 16 * ((4 * (v12 + 1) * (__int64)(v12 + 1) + 15) / 0x10uLL);\n while ( v6 != &v6[-(v2 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = alloca(v2 & 0xFFF);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)&v6[(v2 & 0xFFF) - 8] = *(_QWORD *)&v6[(v2 & 0xFFF) - 8];\n v15 = v6;\n for ( i = 0; i <= v12; ++i )\n {\n for ( j = 0; j <= v12; ++j )\n *(_DWORD *)&v15[4 * j + 4 * (v1 >> 2) * i] = 0;\n }\n for ( k = 1; k <= v12; ++k )\n {\n for ( m = 1; m <= v12; ++m )\n {\n if ( s[k - 1] != s[m - 1] || k == m )\n {\n v4 = *(_DWORD *)&v15[4 * m + 4 * (v1 >> 2) * (k - 1)];\n if ( v4 < *(_DWORD *)&v15[4 * m - 4 + 4 * (v1 >> 2) * k] )\n v4 = *(_DWORD *)&v15[4 * m - 4 + 4 * (v1 >> 2) * k];\n *(_DWORD *)&v15[4 * m + 4 * (v1 >> 2) * k] = v4;\n }\n else\n {\n *(_DWORD *)&v15[4 * m + 4 * (v1 >> 2) * k] = *(_DWORD *)&v15[4 * m - 4 + 4 * (v1 >> 2) * (k - 1)] + 1;\n }\n }\n }\n return *(unsigned int *)&v15[4 * ((v1 >> 2) + 1) * v12];\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 58h\nmov [rbp+s], rdi\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov rax, rsp\nmov rbx, rax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_34], eax\nmov eax, [rbp+var_34]\nlea r8d, [rax+1]\nmov eax, [rbp+var_34]\nlea r9d, [rax+1]\nmovsxd rax, r8d\nsub rax, 1\nmov [rbp+var_30], rax\nmovsxd rax, r8d\nlea rcx, ds:0[rax*4]\nmovsxd rax, r9d\nsub rax, 1\nmov [rbp+var_28], rax\nmovsxd rax, r8d\nmov rsi, rax\nmov edi, 0\nmovsxd rax, r9d\nmov rax, rax\nmov edx, 0\nmov r11, rdi\nimul r11, rax\nmov r10, rdx\nimul r10, rsi\nadd r10, r11\nmul rsi\nlea rsi, [r10+rdx]\nmov rdx, rsi\nmovsxd rax, r8d\nmov rsi, rax\nmov edi, 0\nmovsxd rax, r9d\nmov rax, rax\nmov edx, 0\nmov r11, rdi\nimul r11, rax\nmov r10, rdx\nimul r10, rsi\nadd r10, r11\nmul rsi\nlea rsi, [r10+rdx]\nmov rdx, rsi\nmovsxd rdx, r8d\nmovsxd rax, r9d\nimul rax, rdx\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rsi, rax\nand rsi, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rsi\nloc_128E:\ncmp rsp, rdx\njz short loc_12A5\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\njmp short loc_128E\nloc_12A5:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_12CF\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_12CF:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_20], rax\nmov [rbp+var_44], 0\njmp short loc_1329\nloc_12EB:\nmov [rbp+var_40], 0\njmp short loc_131D\nloc_12F4:\nmov rdi, rcx\nshr rdi, 2\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_40]\nmovsxd rsi, edx\nmov edx, [rbp+var_44]\nmovsxd rdx, edx\nimul rdx, rdi\nadd rdx, rsi\nmov dword ptr [rax+rdx*4], 0\nadd [rbp+var_40], 1\nloc_131D:\nmov eax, [rbp+var_40]\ncmp eax, [rbp+var_34]\njle short loc_12F4\nadd [rbp+var_44], 1\nloc_1329:\nmov eax, [rbp+var_44]\ncmp eax, [rbp+var_34]\njle short loc_12EB\nmov [rbp+var_3C], 1\njmp loc_144B\nloc_133D:\nmov [rbp+var_38], 1\njmp loc_143B\nloc_1349:\nmov eax, [rbp+var_3C]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_38]\ncdqe\nlea rsi, [rax-1]\nmov rax, [rbp+s]\nadd rax, rsi\nmovzx eax, byte ptr [rax]\ncmp dl, al\njnz short loc_13C8\nmov eax, [rbp+var_3C]\ncmp eax, [rbp+var_38]\njz short loc_13C8\nmov rdi, rcx\nshr rdi, 2\nmov eax, [rbp+var_3C]\nlea edx, [rax-1]\nmov eax, [rbp+var_38]\nlea esi, [rax-1]\nmov rax, [rbp+var_20]\nmovsxd rsi, esi\nmovsxd rdx, edx\nimul rdx, rdi\nadd rdx, rsi\nmov eax, [rax+rdx*4]\nmov r8, rcx\nshr r8, 2\nlea esi, [rax+1]\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_38]\nmovsxd rdi, edx\nmov edx, [rbp+var_3C]\nmovsxd rdx, edx\nimul rdx, r8\nadd rdx, rdi\nmov [rax+rdx*4], esi\njmp short loc_1437\nloc_13C8:\nmov rdi, rcx\nshr rdi, 2\nmov eax, [rbp+var_3C]\nlea r8d, [rax-1]\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_38]\nmovsxd rsi, edx\nmovsxd rdx, r8d\nimul rdx, rdi\nadd rdx, rsi\nmov edx, [rax+rdx*4]\nmov r8, rcx\nshr r8, 2\nmov eax, [rbp+var_38]\nlea esi, [rax-1]\nmov rax, [rbp+var_20]\nmovsxd rdi, esi\nmov esi, [rbp+var_3C]\nmovsxd rsi, esi\nimul rsi, r8\nadd rsi, rdi\nmov eax, [rax+rsi*4]\nmov r8, rcx\nshr r8, 2\ncmp edx, eax\ncmovl edx, eax\nmov rax, [rbp+var_20]\nmov esi, [rbp+var_38]\nmovsxd rdi, esi\nmov esi, [rbp+var_3C]\nmovsxd rsi, esi\nimul rsi, r8\nadd rsi, rdi\nmov [rax+rsi*4], edx\nloc_1437:\nadd [rbp+var_38], 1\nloc_143B:\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_34]\njle loc_1349\nadd [rbp+var_3C], 1\nloc_144B:\nmov eax, [rbp+var_3C]\ncmp eax, [rbp+var_34]\njle loc_133D\nshr rcx, 2\nmov rdx, rcx\nmov rax, [rbp+var_20]\nlea rcx, [rdx+1]\nmov edx, [rbp+var_34]\nmovsxd rdx, edx\nimul rdx, rcx\nmov eax, [rax+rdx*4]\nmov rsp, rbx\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njz short loc_148A\ncall ___stack_chk_fail\nloc_148A:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(char *a1)\n{\n unsigned __int64 v1; // rcx\n unsigned __int64 v2; // rax\n void *v3; // rsp\n int v4; // edx\n _BYTE v6[8]; // [rsp+8h] [rbp-60h] BYREF\n char *s; // [rsp+10h] [rbp-58h]\n int i; // [rsp+24h] [rbp-44h]\n int j; // [rsp+28h] [rbp-40h]\n int k; // [rsp+2Ch] [rbp-3Ch]\n int m; // [rsp+30h] [rbp-38h]\n int v12; // [rsp+34h] [rbp-34h]\n __int64 v13; // [rsp+38h] [rbp-30h]\n __int64 v14; // [rsp+40h] [rbp-28h]\n _BYTE *v15; // [rsp+48h] [rbp-20h]\n unsigned __int64 v16; // [rsp+50h] [rbp-18h]\n\n s = a1;\n v16 = __readfsqword(0x28u);\n v12 = strlen(a1);\n v13 = v12 + 1 - 1LL;\n v1 = 4LL * (v12 + 1);\n v14 = v13;\n v2 = 16 * ((4 * (v12 + 1) * (__int64)(v12 + 1) + 15) / 0x10uLL);\n while ( v6 != &v6[-(v2 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = alloca(v2 & 0xFFF);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)&v6[(v2 & 0xFFF) - 8] = *(_QWORD *)&v6[(v2 & 0xFFF) - 8];\n v15 = v6;\n for ( i = 0; i <= v12; ++i )\n {\n for ( j = 0; j <= v12; ++j )\n *(_DWORD *)&v15[4 * j + 4 * (v1 >> 2) * i] = 0;\n }\n for ( k = 1; k <= v12; ++k )\n {\n for ( m = 1; m <= v12; ++m )\n {\n if ( s[k - 1] != s[m - 1] || k == m )\n {\n v4 = *(_DWORD *)&v15[4 * m + 4 * (v1 >> 2) * (k - 1)];\n if ( v4 < *(_DWORD *)&v15[4 * m - 4 + 4 * (v1 >> 2) * k] )\n v4 = *(_DWORD *)&v15[4 * m - 4 + 4 * (v1 >> 2) * k];\n *(_DWORD *)&v15[4 * m + 4 * (v1 >> 2) * k] = v4;\n }\n else\n {\n *(_DWORD *)&v15[4 * m + 4 * (v1 >> 2) * k] = *(_DWORD *)&v15[4 * m - 4 + 4 * (v1 >> 2) * (k - 1)] + 1;\n }\n }\n }\n return *(unsigned int *)&v15[4 * ((v1 >> 2) + 1) * v12];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(char *a1) {\n unsigned long long v1;\n unsigned long long v2;\n void *v3;\n int v4;\n uint8_t v6[8];\n char *s;\n int i;\n int j;\n int k;\n int m;\n int v12;\n long long v13;\n long long v14;\n uint8_t *v15;\n unsigned long long v16;\n s = a1;\n v16 = __readfsqword(40u);\n v12 = strlen(a1);\n v13 = v12 + 1 - 1LL;\n v1 = 4LL * (v12 + 1);\n v14 = v13;\n v2 = 16 * ((4 * (v12 + 1) * (long long)(v12 + 1) + 15) / 16uLL);\n while (v6 != &v6[-(v2 & 18446744073709547520LL)])\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)&v6[(v2 & 4095) - 8] = *(uint64_t *)&v6[(v2 & 4095) - 8];\n v15 = v6;\n for (i = 0; i <= v12; ++i) {\n for (j = 0; j <= v12; ++j) *(uint32_t *)&v15[4 * j + 4 * (v1 >> 2) * i] = 0;\n }\n for (k = 1; k <= v12; ++k) {\n for (m = 1; m <= v12; ++m) {\n if (s[k - 1] != s[m - 1] || k == m) {\n v4 = *(uint32_t *)&v15[4 * m + 4 * (v1 >> 2) * (k - 1)];\n if (v4 < *(uint32_t *)&v15[4 * m - 4 + 4 * (v1 >> 2) * k])\n v4 = *(uint32_t *)&v15[4 * m - 4 + 4 * (v1 >> 2) * k];\n *(uint32_t *)&v15[4 * m + 4 * (v1 >> 2) * k] = v4;\n } else {\n *(uint32_t *)&v15[4 * m + 4 * (v1 >> 2) * k] =\n *(uint32_t *)&v15[4 * m - 4 + 4 * (v1 >> 2) * (k - 1)] + 1;\n }\n }\n }\n return *(unsigned int *)&v15[4 * ((v1 >> 2) + 1) * v12];\n}", + "ida_pseudo_norm": "long long func0(char *a1) {\n unsigned long long v1;\n unsigned long long v2;\n void *v3;\n int v4;\n uint8_t v6[8];\n char *s;\n int i;\n int j;\n int k;\n int m;\n int v12;\n long long v13;\n long long v14;\n uint8_t *v15;\n unsigned long long v16;\n s = a1;\n v16 = __readfsqword(40u);\n v12 = strlen(a1);\n v13 = v12 + 1 - 1LL;\n v1 = 4LL * (v12 + 1);\n v14 = v13;\n v2 = 16 * ((4 * (v12 + 1) * (long long)(v12 + 1) + 15) / 16uLL);\n while (v6 != &v6[-(v2 & 18446744073709547520LL)])\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)&v6[(v2 & 4095) - 8] = *(uint64_t *)&v6[(v2 & 4095) - 8];\n v15 = v6;\n for (i = 0; i <= v12; ++i) {\n for (j = 0; j <= v12; ++j) *(uint32_t *)&v15[4 * j + 4 * (v1 >> 2) * i] = 0;\n }\n for (k = 1; k <= v12; ++k) {\n for (m = 1; m <= v12; ++m) {\n if (s[k - 1] != s[m - 1] || k == m) {\n v4 = *(uint32_t *)&v15[4 * m + 4 * (v1 >> 2) * (k - 1)];\n if (v4 < *(uint32_t *)&v15[4 * m - 4 + 4 * (v1 >> 2) * k])\n v4 = *(uint32_t *)&v15[4 * m - 4 + 4 * (v1 >> 2) * k];\n *(uint32_t *)&v15[4 * m + 4 * (v1 >> 2) * k] = v4;\n } else {\n *(uint32_t *)&v15[4 * m + 4 * (v1 >> 2) * k] =\n *(uint32_t *)&v15[4 * m - 4 + 4 * (v1 >> 2) * (k - 1)] + 1;\n }\n }\n }\n return *(unsigned int *)&v15[4 * ((v1 >> 2) + 1) * v12];\n}" + }, + { + "index": 207, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char *str) {\n int n = strlen(str);\n int dp[n + 1][n + 1];\n for (int i = 0; i <= n; i++) {\n for (int j = 0; j <= n; j++) {\n dp[i][j] = 0;\n }\n }\n for (int i = 1; i <= n; i++) {\n for (int j = 1; j <= n; j++) {\n if (str[i - 1] == str[j - 1] && i != j) {\n dp[i][j] = 1 + dp[i - 1][j - 1];\n } else {\n dp[i][j] = (dp[i][j - 1] > dp[i - 1][j]) ? dp[i][j - 1] : dp[i - 1][j];\n }\n }\n }\n return dp[n][n];\n}", + "test": "int main() {\n\n assert(func0(\"AABEBCDD\") == 3);\n\n assert(func0(\"aabb\") == 2);\n\n assert(func0(\"aab\") == 1);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0x10,%rsp\nmov %rdi,%r8\nmov %fs:0x28,%rax\nmov %rax,-0x28(%rbp)\nxor %eax,%eax\nmov $0xffffffffffffffff,%rcx\nrepnz scas %es:(%rdi),%al\nnot %rcx\nlea -0x1(%rcx),%rbx\nmovslq %ecx,%rax\nlea 0x0(,%rax,4),%r11\nimul %rax,%rax\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffffff0,%rdx\nand $0xfffffffffffff000,%rax\nmov %rsp,%rdi\nsub %rax,%rdi\nmov %rdi,%rax\ncmp %rax,%rsp\nje 11e2 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11cb \nmov %rdx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 11f8 \norq $0x0,-0x8(%rsp,%rax,1)\nmov %rsp,%r12\ntest %ebx,%ebx\njs 1236 \nmov %ebx,%esi\nlea 0x4(%r12,%rsi,4),%rdx\nlea 0x1(%rbx),%edi\nmov $0x0,%ecx\nnot %rsi\nshl $0x2,%rsi\njmp 1221 \nadd $0x1,%ecx\nadd %r11,%rdx\ncmp %edi,%ecx\nje 1236 \nlea (%rsi,%rdx,1),%rax\nmovl $0x0,(%rax)\nadd $0x4,%rax\ncmp %rdx,%rax\njne 1225 \njmp 1217 \ntest %ebx,%ebx\njle 12aa \nmov %r12,%r14\nlea (%r12,%r11,1),%r13\nlea -0x1(%rbx),%edi\nadd $0x2,%rdi\nmov %r13,%rsi\nmov %r12,%rcx\nmov $0x1,%r9d\njmp 129d \nmov -0x4(%rsi,%rax,4),%edx\ncmp %edx,(%rcx,%rax,4)\ncmovge (%rcx,%rax,4),%edx\nmov %edx,(%rsi,%rax,4)\nadd $0x1,%rax\ncmp %rdi,%rax\nje 1288 \ncmp %r10b,-0x1(%r8,%rax,1)\njne 1256 \ncmp %r9d,%eax\nje 1256 \nmov -0x4(%r14,%rax,4),%edx\nadd $0x1,%edx\nmov %edx,0x0(%r13,%rax,4)\njmp 1264 \nadd $0x1,%r9\nadd %r11,%r14\nadd %r11,%r13\nadd %r11,%rcx\nadd %r11,%rsi\ncmp %rdi,%r9\nje 12aa \nmovzbl -0x1(%r8,%r9,1),%r10d\nmov $0x1,%eax\njmp 126d \nshr $0x2,%r11\nlea 0x1(%r11),%rax\nmovslq %ebx,%rbx\nimul %rax,%rbx\nmov (%r12,%rbx,4),%eax\nmov -0x28(%rbp),%rbx\nxor %fs:0x28,%rbx\njne 12d9 \nlea -0x20(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %rbp\nretq\ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 18h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\ncall _strlen\nmov r12, rax\nlea eax, [rax+1]\ncdqe\nlea r10, ds:0[rax*4]\nimul rax, rax\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11E4:\ncmp rsp, rdx\njz short loc_11FB\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_11E4\nloc_11FB:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_1211\nor [rsp+rax+40h+var_48], 0\nloc_1211:\nmov r13, rsp\ntest r12d, r12d\njs loc_12C9\nmov esi, r12d\nmov r11, r13\nlea rdx, [r13+rsi*4+4]\nlea edi, [r12+1]\nmov ecx, 0\nnot rsi\nshl rsi, 2\nloc_1239:\nlea rax, [rsi+rdx]\nloc_123D:\nmov dword ptr [rax], 0\nadd rax, 4\ncmp rax, rdx\njnz short loc_123D\nadd ecx, 1\nadd rdx, r10\ncmp ecx, edi\njnz short loc_1239\ntest r12d, r12d\njle short loc_12C9\nlea r14, [r13+r10+0]\nlea edi, [r12+1]\nmov rcx, r14\nmov r9, r13\nmov esi, 1\njmp short loc_12BC\nloc_1272:\nmov edx, [r9+rax*4]\nmov r15d, [rcx+rax*4-4]\ncmp edx, r15d\ncmovl edx, r15d\nmov [rcx+rax*4], edx\nloc_1285:\nadd rax, 1\ncmp rax, rdi\njz short loc_12A7\nloc_128E:\ncmp [rbx+rax-1], r8b\njnz short loc_1272\ncmp eax, esi\njz short loc_1272\nmov edx, [r11+rax*4-4]\nadd edx, 1\nmov [r14+rax*4], edx\njmp short loc_1285\nloc_12A7:\nadd rsi, 1\nadd r11, r10\nadd r14, r10\nadd r9, r10\nadd rcx, r10\ncmp rsi, rdi\njz short loc_12C9\nloc_12BC:\nmovzx r8d, byte ptr [rbx+rsi-1]\nmov eax, 1\njmp short loc_128E\nloc_12C9:\nshr r10, 2\nlea rax, [r10+1]\nmovsxd r12, r12d\nimul rax, r12\nmov eax, [r13+rax*4+0]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_12FB\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_12FB:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v2; // r12d\n __int64 v3; // rax\n unsigned __int64 v4; // r10\n __int64 v5; // rax\n __int16 v6; // cx\n signed __int64 v7; // rax\n void *v8; // rsp\n _BYTE *v9; // r11\n _BYTE *v10; // rdx\n int v11; // ecx\n _DWORD *v12; // rax\n _BYTE *v13; // r14\n __int64 v14; // rdi\n _BYTE *v15; // rcx\n _BYTE *v16; // r9\n __int64 v17; // rsi\n int v18; // edx\n __int64 v19; // rax\n char v20; // r8\n _BYTE v23[8]; // [rsp+8h] [rbp-40h] BYREF\n unsigned __int64 v24; // [rsp+10h] [rbp-38h]\n\n v24 = __readfsqword(0x28u);\n v2 = strlen(a1);\n v3 = v2 + 1;\n v4 = 4 * v3;\n v5 = 4 * v3 * v3 + 15;\n v6 = v5 & 0xFFF0;\n while ( v23 != &v23[-(v5 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v7 = v5 & 0xFF0;\n v8 = alloca(v7);\n if ( (v6 & 0xFFF) != 0 )\n *(_QWORD *)&v23[v7 - 8] = *(_QWORD *)&v23[v7 - 8];\n if ( v2 >= 0 )\n {\n v9 = v23;\n v10 = &v23[4 * v2 + 4];\n v11 = 0;\n do\n {\n v12 = &v10[4 * ~(unsigned __int64)(unsigned int)v2];\n do\n *v12++ = 0;\n while ( v12 != (_DWORD *)v10 );\n ++v11;\n v10 += v4;\n }\n while ( v11 != v2 + 1 );\n if ( v2 > 0 )\n {\n v13 = &v23[v4];\n v14 = (unsigned int)(v2 + 1);\n v15 = &v23[v4];\n v16 = v23;\n v17 = 1LL;\n do\n {\n v20 = a1[v17 - 1];\n v19 = 1LL;\n do\n {\n if ( a1[v19 - 1] != v20 || (_DWORD)v19 == (_DWORD)v17 )\n {\n v18 = *(_DWORD *)&v16[4 * v19];\n if ( v18 < *(_DWORD *)&v15[4 * v19 - 4] )\n v18 = *(_DWORD *)&v15[4 * v19 - 4];\n *(_DWORD *)&v15[4 * v19] = v18;\n }\n else\n {\n *(_DWORD *)&v13[4 * v19] = *(_DWORD *)&v9[4 * v19 - 4] + 1;\n }\n ++v19;\n }\n while ( v19 != v14 );\n ++v17;\n v9 += v4;\n v13 += v4;\n v16 += v4;\n v15 += v4;\n }\n while ( v17 != v14 );\n }\n }\n return *(unsigned int *)&v23[4 * v2 * ((v4 >> 2) + 1)];\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 18h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\ncall _strlen\nmov r12, rax\nlea eax, [rax+1]\ncdqe\nlea r10, ds:0[rax*4]\nimul rax, rax\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11E4:\ncmp rsp, rdx\njz short loc_11FB\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_11E4\nloc_11FB:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_1211\nor [rsp+rax+40h+var_48], 0\nloc_1211:\nmov r13, rsp\ntest r12d, r12d\njs loc_12C9\nmov esi, r12d\nmov r11, r13\nlea rdx, [r13+rsi*4+4]\nlea edi, [r12+1]\nmov ecx, 0\nnot rsi\nshl rsi, 2\nloc_1239:\nlea rax, [rsi+rdx]\nloc_123D:\nmov dword ptr [rax], 0\nadd rax, 4\ncmp rax, rdx\njnz short loc_123D\nadd ecx, 1\nadd rdx, r10\ncmp ecx, edi\njnz short loc_1239\ntest r12d, r12d\njle short loc_12C9\nlea r14, [r13+r10+0]\nlea edi, [r12+1]\nmov rcx, r14\nmov r9, r13\nmov esi, 1\njmp short loc_12BC\nloc_1272:\nmov edx, [r9+rax*4]\nmov r15d, [rcx+rax*4-4]\ncmp edx, r15d\ncmovl edx, r15d\nmov [rcx+rax*4], edx\nloc_1285:\nadd rax, 1\ncmp rax, rdi\njz short loc_12A7\nloc_128E:\ncmp [rbx+rax-1], r8b\njnz short loc_1272\ncmp eax, esi\njz short loc_1272\nmov edx, [r11+rax*4-4]\nadd edx, 1\nmov [r14+rax*4], edx\njmp short loc_1285\nloc_12A7:\nadd rsi, 1\nadd r11, r10\nadd r14, r10\nadd r9, r10\nadd rcx, r10\ncmp rsi, rdi\njz short loc_12C9\nloc_12BC:\nmovzx r8d, byte ptr [rbx+rsi-1]\nmov eax, 1\njmp short loc_128E\nloc_12C9:\nshr r10, 2\nlea rax, [r10+1]\nmovsxd r12, r12d\nimul rax, r12\nmov eax, [r13+rax*4+0]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_12FB\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_12FB:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(const char *a1)\n{\n int v2; // r12d\n __int64 v3; // rax\n unsigned __int64 v4; // r10\n __int64 v5; // rax\n __int16 v6; // cx\n signed __int64 v7; // rax\n void *v8; // rsp\n _BYTE *v9; // r11\n _BYTE *v10; // rdx\n int v11; // ecx\n _DWORD *v12; // rax\n _BYTE *v13; // r14\n __int64 v14; // rdi\n _BYTE *v15; // rcx\n _BYTE *v16; // r9\n __int64 v17; // rsi\n int v18; // edx\n __int64 v19; // rax\n char v20; // r8\n _BYTE v23[8]; // [rsp+8h] [rbp-40h] BYREF\n unsigned __int64 v24; // [rsp+10h] [rbp-38h]\n\n v24 = __readfsqword(0x28u);\n v2 = strlen(a1);\n v3 = v2 + 1;\n v4 = 4 * v3;\n v5 = 4 * v3 * v3 + 15;\n v6 = v5 & 0xFFF0;\n while ( v23 != &v23[-(v5 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v7 = v5 & 0xFF0;\n v8 = alloca(v7);\n if ( (v6 & 0xFFF) != 0 )\n *(_QWORD *)&v23[v7 - 8] = *(_QWORD *)&v23[v7 - 8];\n if ( v2 >= 0 )\n {\n v9 = v23;\n v10 = &v23[4 * v2 + 4];\n v11 = 0;\n do\n {\n v12 = &v10[4 * ~(unsigned __int64)(unsigned int)v2];\n do\n *v12++ = 0;\n while ( v12 != (_DWORD *)v10 );\n ++v11;\n v10 += v4;\n }\n while ( v11 != v2 + 1 );\n if ( v2 > 0 )\n {\n v13 = &v23[v4];\n v14 = (unsigned int)(v2 + 1);\n v15 = &v23[v4];\n v16 = v23;\n v17 = 1LL;\n do\n {\n v20 = a1[v17 - 1];\n v19 = 1LL;\n do\n {\n if ( a1[v19 - 1] != v20 || (_DWORD)v19 == (_DWORD)v17 )\n {\n v18 = *(_DWORD *)&v16[4 * v19];\n if ( v18 < *(_DWORD *)&v15[4 * v19 - 4] )\n v18 = *(_DWORD *)&v15[4 * v19 - 4];\n *(_DWORD *)&v15[4 * v19] = v18;\n }\n else\n {\n *(_DWORD *)&v13[4 * v19] = *(_DWORD *)&v9[4 * v19 - 4] + 1;\n }\n ++v19;\n }\n while ( v19 != v14 );\n ++v17;\n v9 += v4;\n v13 += v4;\n v16 += v4;\n v15 += v4;\n }\n while ( v17 != v14 );\n }\n }\n return *(unsigned int *)&v23[4 * v2 * ((v4 >> 2) + 1)];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(const char *a1) {\n int v2;\n long long v3;\n unsigned long long v4;\n long long v5;\n short v6;\n signed long long v7;\n void *v8;\n uint8_t *v9;\n uint8_t *v10;\n int v11;\n uint32_t *v12;\n uint8_t *v13;\n long long v14;\n uint8_t *v15;\n uint8_t *v16;\n long long v17;\n int v18;\n long long v19;\n char v20;\n uint8_t v23[8];\n unsigned long long v24;\n v24 = __readfsqword(40u);\n v2 = strlen(a1);\n v3 = v2 + 1;\n v4 = 4 * v3;\n v5 = 4 * v3 * v3 + 15;\n v6 = v5 & 65520;\n while (v23 != &v23[-(v5 & 18446744073709547520LL)])\n ;\n v7 = v5 & 4080;\n v8 = alloca(v7);\n if ((v6 & 4095) != 0) *(uint64_t *)&v23[v7 - 8] = *(uint64_t *)&v23[v7 - 8];\n if (v2 >= 0) {\n v9 = v23;\n v10 = &v23[4 * v2 + 4];\n v11 = 0;\n do {\n v12 = &v10[4 * ~(unsigned long long)(unsigned int)v2];\n do\n *v12++ = 0;\n while (v12 != (uint32_t *)v10);\n ++v11;\n v10 += v4;\n } while (v11 != v2 + 1);\n if (v2 > 0) {\n v13 = &v23[v4];\n v14 = (unsigned int)(v2 + 1);\n v15 = &v23[v4];\n v16 = v23;\n v17 = 1LL;\n do {\n v20 = a1[v17 - 1];\n v19 = 1LL;\n do {\n if (a1[v19 - 1] != v20 || (uint32_t)v19 == (uint32_t)v17) {\n v18 = *(uint32_t *)&v16[4 * v19];\n if (v18 < *(uint32_t *)&v15[4 * v19 - 4])\n v18 = *(uint32_t *)&v15[4 * v19 - 4];\n *(uint32_t *)&v15[4 * v19] = v18;\n } else {\n *(uint32_t *)&v13[4 * v19] = *(uint32_t *)&v9[4 * v19 - 4] + 1;\n }\n ++v19;\n } while (v19 != v14);\n ++v17;\n v9 += v4;\n v13 += v4;\n v16 += v4;\n v15 += v4;\n } while (v17 != v14);\n }\n }\n return *(unsigned int *)&v23[4 * v2 * ((v4 >> 2) + 1)];\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v2;\n long long v3;\n unsigned long long v4;\n long long v5;\n short v6;\n signed long long v7;\n void *v8;\n uint8_t *v9;\n uint8_t *v10;\n int v11;\n uint32_t *v12;\n uint8_t *v13;\n long long v14;\n uint8_t *v15;\n uint8_t *v16;\n long long v17;\n int v18;\n long long v19;\n char v20;\n uint8_t v23[8];\n unsigned long long v24;\n v24 = __readfsqword(40u);\n v2 = strlen(a1);\n v3 = v2 + 1;\n v4 = 4 * v3;\n v5 = 4 * v3 * v3 + 15;\n v6 = v5 & 65520;\n while (v23 != &v23[-(v5 & 18446744073709547520LL)])\n ;\n v7 = v5 & 4080;\n v8 = alloca(v7);\n if ((v6 & 4095) != 0) *(uint64_t *)&v23[v7 - 8] = *(uint64_t *)&v23[v7 - 8];\n if (v2 >= 0) {\n v9 = v23;\n v10 = &v23[4 * v2 + 4];\n v11 = 0;\n do {\n v12 = &v10[4 * ~(unsigned long long)(unsigned int)v2];\n do\n *v12++ = 0;\n while (v12 != (uint32_t *)v10);\n ++v11;\n v10 += v4;\n } while (v11 != v2 + 1);\n if (v2 > 0) {\n v13 = &v23[v4];\n v14 = (unsigned int)(v2 + 1);\n v15 = &v23[v4];\n v16 = v23;\n v17 = 1LL;\n do {\n v20 = a1[v17 - 1];\n v19 = 1LL;\n do {\n if (a1[v19 - 1] != v20 || (uint32_t)v19 == (uint32_t)v17) {\n v18 = *(uint32_t *)&v16[4 * v19];\n if (v18 < *(uint32_t *)&v15[4 * v19 - 4])\n v18 = *(uint32_t *)&v15[4 * v19 - 4];\n *(uint32_t *)&v15[4 * v19] = v18;\n } else {\n *(uint32_t *)&v13[4 * v19] = *(uint32_t *)&v9[4 * v19 - 4] + 1;\n }\n ++v19;\n } while (v19 != v14);\n ++v17;\n v9 += v4;\n v13 += v4;\n v16 += v4;\n v15 += v4;\n } while (v17 != v14);\n }\n }\n return *(unsigned int *)&v23[4 * v2 * ((v4 >> 2) + 1)];\n}" + }, + { + "index": 207, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char *str) {\n int n = strlen(str);\n int dp[n + 1][n + 1];\n for (int i = 0; i <= n; i++) {\n for (int j = 0; j <= n; j++) {\n dp[i][j] = 0;\n }\n }\n for (int i = 1; i <= n; i++) {\n for (int j = 1; j <= n; j++) {\n if (str[i - 1] == str[j - 1] && i != j) {\n dp[i][j] = 1 + dp[i - 1][j - 1];\n } else {\n dp[i][j] = (dp[i][j - 1] > dp[i - 1][j]) ? dp[i][j - 1] : dp[i - 1][j];\n }\n }\n }\n return dp[n][n];\n}", + "test": "int main() {\n\n assert(func0(\"AABEBCDD\") == 3);\n\n assert(func0(\"aabb\") == 2);\n\n assert(func0(\"aab\") == 1);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r14\npush %r13\npush %r12\npush %rbx\nmov %rdi,%rbx\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x28(%rbp)\nxor %eax,%eax\ncallq 1070 \nmov %rsp,%rdi\nlea 0x1(%rax),%r8d\nmovslq %r8d,%rdx\nlea 0x0(,%rdx,4),%r10\nimul %rdx,%rdx\nlea 0xf(,%rdx,4),%rdx\nmov %rdx,%rcx\nand $0xfffffffffffff000,%rdx\nsub %rdx,%rdi\nand $0xfffffffffffffff0,%rcx\nmov %rdi,%rdx\ncmp %rdx,%rsp\nje 12a6 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rdx,%rsp\njne 1291 \nand $0xfff,%ecx\nsub %rcx,%rsp\ntest %rcx,%rcx\njne 13ae \nmov %r10,%r11\nmov %rsp,%r12\nshr $0x2,%r11\ntest %eax,%eax\njs 1384 \nmov %eax,%edi\nxor %esi,%esi\nlea 0x4(%r12,%rdi,4),%rcx\nnot %rdi\nshl $0x2,%rdi\nnopw 0x0(%rax,%rax,1)\nlea (%rdi,%rcx,1),%rdx\nnopl 0x0(%rax)\nmovl $0x0,(%rdx)\nadd $0x4,%rdx\ncmp %rcx,%rdx\njne 12e8 \nadd $0x1,%esi\nlea (%rdx,%r10,1),%rcx\ncmp %r8d,%esi\njne 12e0 \ntest %eax,%eax\njle 1384 \nlea -0x1(%rax),%edi\nmov %r12,%r8\nlea 0x4(%r10),%r14\nmov $0x1,%r9d\nadd $0x2,%rdi\nnopl 0x0(%rax,%rax,1)\nmovzbl -0x1(%rbx,%r9,1),%r13d\nlea (%r14,%r8,1),%rcx\nmov $0x1,%edx\njmp 1354 \nnopl 0x0(%rax)\nmov -0x4(%rcx),%esi\ncmp %esi,(%r8,%rdx,4)\ncmovge (%r8,%rdx,4),%esi\nadd $0x1,%rdx\nadd $0x4,%rcx\nmov %esi,-0x4(%rcx)\ncmp %rdx,%rdi\nje 1378 \ncmp %r13b,-0x1(%rbx,%rdx,1)\njne 1338 \ncmp %r9d,%edx\nje 1338 \nmov -0x4(%r8,%rdx,4),%esi\nadd $0x1,%rdx\nadd $0x4,%rcx\nadd $0x1,%esi\nmov %esi,-0x4(%rcx)\ncmp %rdx,%rdi\njne 1354 \nadd $0x1,%r9\nadd %r10,%r8\ncmp %r9,%rdi\njne 1320 \nadd $0x1,%r11\ncltq\nimul %r11,%rax\nmov -0x28(%rbp),%rbx\nxor %fs:0x28,%rbx\nmov (%r12,%rax,4),%eax\njne 13b9 \nlea -0x20(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %rbp\nretq\norq $0x0,-0x8(%rsp,%rcx,1)\njmpq 12b8 \ncallq 1080 <__stack_chk_fail@plt>\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\nmov r15, rdi\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 38h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\ncall _strlen\nmov rsi, rsp\nlea r14d, [rax+1]\nmov [rbp+var_50], rax\nmovsxd rax, r14d\nlea r12, ds:0[rax*4]\nimul rax, rax\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rsi, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rsi\njz short loc_12C8\nloc_12B3:\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\ncmp rsp, rsi\njnz short loc_12B3\nloc_12C8:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_13C9\nloc_12DA:\nmov rax, [rbp+var_50]\nmov rdi, rsp; s\nmov [rbp+var_58], rdi\ntest eax, eax\njs loc_1391\nmov eax, eax\nmov r13, rdi\nxor ebx, ebx\nlea rax, ds:4[rax*4]\nmov [rbp+n], rax\nloc_1300:\nmov rdx, [rbp+n]; n\nxor esi, esi; c\nadd ebx, 1\ncall _memset\nmov rdi, rax\nadd rdi, r12\ncmp ebx, r14d\njnz short loc_1300\nmov eax, dword ptr [rbp+var_50]\ntest eax, eax\njz loc_13D4\nmov rax, [rbp+var_58]\nmov r9d, ebx\nmov r11d, 1\nlea rdi, [rax+r12]\nnop dword ptr [rax]\nloc_1338:\nmovzx r10d, byte ptr [r15+r11-1]\nmov eax, 1\njmp short loc_1362\nloc_1348:\nmov edx, [r13+rax*4+0]\nmov esi, [rdi+rax*4-4]\ncmp edx, esi\ncmovl edx, esi\nmov [rdi+rax*4], edx\nadd rax, 1\ncmp rax, r9\njz short loc_1382\nloc_1362:\ncmp [r15+rax-1], r10b\njnz short loc_1348\ncmp eax, r11d\njz short loc_1348\nmov ecx, [r13+rax*4-4]\nlea edx, [rcx+1]\nmov [rdi+rax*4], edx\nadd rax, 1\ncmp rax, r9\njnz short loc_1362\nloc_1382:\nadd r11, 1\nadd rdi, r12\nadd r13, r12\ncmp r11, rax\njnz short loc_1338\nloc_1391:\nmov r8, r12\nshr r8, 2\nloc_1398:\nmovsxd rbx, dword ptr [rbp+var_50]\nlea rax, [r8+1]\nimul rax, rbx\nmov rbx, [rbp+var_58]\nmov eax, [rbx+rax*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_13DC\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_13C9:\nor [rsp+rdx+1060h+var_1068], 0\njmp loc_12DA\nloc_13D4:\nmov r8d, 1\njmp short loc_1398\nloc_13DC:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n size_t v2; // rax\n int v3; // r14d\n unsigned __int64 v4; // r12\n __int64 v5; // rdx\n __int64 *v6; // rsi\n __int16 v7; // dx\n signed __int64 v8; // rdx\n void *v9; // rsp\n char *v10; // rdi\n _BYTE *v11; // r13\n int v12; // ebx\n __int64 v13; // r11\n _BYTE *v14; // rdi\n char v15; // r10\n __int64 v16; // rax\n int v17; // edx\n __int64 v18; // r8\n _BYTE v21[4088]; // [rsp+8h] [rbp-1060h] BYREF\n __int64 v22; // [rsp+1008h] [rbp-60h] BYREF\n _BYTE *v23; // [rsp+1010h] [rbp-58h]\n size_t v24; // [rsp+1018h] [rbp-50h]\n size_t n; // [rsp+1020h] [rbp-48h]\n unsigned __int64 v26; // [rsp+1030h] [rbp-38h]\n\n v26 = __readfsqword(0x28u);\n v2 = strlen(a1);\n v3 = v2 + 1;\n v24 = v2;\n v4 = 4LL * ((int)v2 + 1);\n v5 = 4 * v3 * (__int64)v3 + 15;\n v6 = (__int64 *)((char *)&v22 - (v5 & 0xFFFFFFFFFFFFF000LL));\n v7 = v5 & 0xFFF0;\n if ( &v22 != v6 )\n {\n while ( v21 != (_BYTE *)v6 )\n ;\n }\n v8 = v7 & 0xFFF;\n v9 = alloca(v8);\n if ( v8 )\n *(_QWORD *)&v21[v8 - 8] = *(_QWORD *)&v21[v8 - 8];\n v10 = v21;\n v23 = v21;\n if ( (v24 & 0x80000000) == 0LL )\n {\n v11 = v21;\n v12 = 0;\n n = 4LL * (unsigned int)v24 + 4;\n do\n {\n ++v12;\n v10 = (char *)memset(v10, 0, n) + v4;\n }\n while ( v12 != v3 );\n if ( !(_DWORD)v24 )\n {\n v18 = 1LL;\n return *(unsigned int *)&v23[4 * (int)v24 * (v18 + 1)];\n }\n v13 = 1LL;\n v14 = &v23[v4];\n do\n {\n v15 = a1[v13 - 1];\n v16 = 1LL;\n do\n {\n while ( a1[v16 - 1] == v15 && (_DWORD)v16 != (_DWORD)v13 )\n {\n *(_DWORD *)&v14[4 * v16] = *(_DWORD *)&v11[4 * v16 - 4] + 1;\n if ( ++v16 == v12 )\n goto LABEL_17;\n }\n v17 = *(_DWORD *)&v11[4 * v16];\n if ( v17 < *(_DWORD *)&v14[4 * v16 - 4] )\n v17 = *(_DWORD *)&v14[4 * v16 - 4];\n *(_DWORD *)&v14[4 * v16++] = v17;\n }\n while ( v16 != v12 );\nLABEL_17:\n ++v13;\n v14 += v4;\n v11 += v4;\n }\n while ( v13 != v16 );\n }\n v18 = v4 >> 2;\n return *(unsigned int *)&v23[4 * (int)v24 * (v18 + 1)];\n}", + "ida_strip_asm": "sub_1250:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\nmov r15, rdi\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 38h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\ncall _strlen\nmov rsi, rsp\nlea r14d, [rax+1]\nmov [rbp+var_50], rax\nmovsxd rax, r14d\nlea r12, ds:0[rax*4]\nimul rax, rax\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rsi, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rsi\njz short loc_12C8\nloc_12B3:\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\ncmp rsp, rsi\njnz short loc_12B3\nloc_12C8:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_13C9\nloc_12DA:\nmov rax, [rbp+var_50]\nmov rdi, rsp; s\nmov [rbp+var_58], rdi\ntest eax, eax\njs loc_1391\nmov eax, eax\nmov r13, rdi\nxor ebx, ebx\nlea rax, ds:4[rax*4]\nmov [rbp+n], rax\nloc_1300:\nmov rdx, [rbp+n]; n\nxor esi, esi; c\nadd ebx, 1\ncall _memset\nmov rdi, rax\nadd rdi, r12\ncmp ebx, r14d\njnz short loc_1300\nmov eax, dword ptr [rbp+var_50]\ntest eax, eax\njz loc_13D4\nmov rax, [rbp+var_58]\nmov r9d, ebx\nmov r11d, 1\nlea rdi, [rax+r12]\nnop dword ptr [rax]\nloc_1338:\nmovzx r10d, byte ptr [r15+r11-1]\nmov eax, 1\njmp short loc_1362\nloc_1348:\nmov edx, [r13+rax*4+0]\nmov esi, [rdi+rax*4-4]\ncmp edx, esi\ncmovl edx, esi\nmov [rdi+rax*4], edx\nadd rax, 1\ncmp rax, r9\njz short loc_1382\nloc_1362:\ncmp [r15+rax-1], r10b\njnz short loc_1348\ncmp eax, r11d\njz short loc_1348\nmov ecx, [r13+rax*4-4]\nlea edx, [rcx+1]\nmov [rdi+rax*4], edx\nadd rax, 1\ncmp rax, r9\njnz short loc_1362\nloc_1382:\nadd r11, 1\nadd rdi, r12\nadd r13, r12\ncmp r11, rax\njnz short loc_1338\nloc_1391:\nmov r8, r12\nshr r8, 2\nloc_1398:\nmovsxd rbx, dword ptr [rbp+var_50]\nlea rax, [r8+1]\nimul rax, rbx\nmov rbx, [rbp+var_58]\nmov eax, [rbx+rax*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_13DC\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_13C9:\nor [rsp+rdx+1060h+var_1068], 0\njmp loc_12DA\nloc_13D4:\nmov r8d, 1\njmp short loc_1398\nloc_13DC:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1250(const char *a1)\n{\n size_t v2; // rax\n int v3; // r14d\n unsigned __int64 v4; // r12\n __int64 v5; // rdx\n __int64 *v6; // rsi\n __int16 v7; // dx\n signed __int64 v8; // rdx\n void *v9; // rsp\n char *v10; // rdi\n _BYTE *v11; // r13\n int v12; // ebx\n __int64 v13; // r11\n _BYTE *v14; // rdi\n char v15; // r10\n __int64 v16; // rax\n int v17; // edx\n __int64 v18; // r8\n _BYTE v21[4088]; // [rsp+8h] [rbp-1060h] BYREF\n __int64 v22; // [rsp+1008h] [rbp-60h] BYREF\n _BYTE *v23; // [rsp+1010h] [rbp-58h]\n size_t v24; // [rsp+1018h] [rbp-50h]\n size_t n; // [rsp+1020h] [rbp-48h]\n unsigned __int64 v26; // [rsp+1030h] [rbp-38h]\n\n v26 = __readfsqword(0x28u);\n v2 = strlen(a1);\n v3 = v2 + 1;\n v24 = v2;\n v4 = 4LL * ((int)v2 + 1);\n v5 = 4 * v3 * (__int64)v3 + 15;\n v6 = (__int64 *)((char *)&v22 - (v5 & 0xFFFFFFFFFFFFF000LL));\n v7 = v5 & 0xFFF0;\n if ( &v22 != v6 )\n {\n while ( v21 != (_BYTE *)v6 )\n ;\n }\n v8 = v7 & 0xFFF;\n v9 = alloca(v8);\n if ( v8 )\n *(_QWORD *)&v21[v8 - 8] = *(_QWORD *)&v21[v8 - 8];\n v10 = v21;\n v23 = v21;\n if ( (v24 & 0x80000000) == 0LL )\n {\n v11 = v21;\n v12 = 0;\n n = 4LL * (unsigned int)v24 + 4;\n do\n {\n ++v12;\n v10 = (char *)memset(v10, 0, n) + v4;\n }\n while ( v12 != v3 );\n if ( !(_DWORD)v24 )\n {\n v18 = 1LL;\n return *(unsigned int *)&v23[4 * (int)v24 * (v18 + 1)];\n }\n v13 = 1LL;\n v14 = &v23[v4];\n do\n {\n v15 = a1[v13 - 1];\n v16 = 1LL;\n do\n {\n while ( a1[v16 - 1] == v15 && (_DWORD)v16 != (_DWORD)v13 )\n {\n *(_DWORD *)&v14[4 * v16] = *(_DWORD *)&v11[4 * v16 - 4] + 1;\n if ( ++v16 == v12 )\n goto LABEL_17;\n }\n v17 = *(_DWORD *)&v11[4 * v16];\n if ( v17 < *(_DWORD *)&v14[4 * v16 - 4] )\n v17 = *(_DWORD *)&v14[4 * v16 - 4];\n *(_DWORD *)&v14[4 * v16++] = v17;\n }\n while ( v16 != v12 );\nLABEL_17:\n ++v13;\n v14 += v4;\n v11 += v4;\n }\n while ( v13 != v16 );\n }\n v18 = v4 >> 2;\n return *(unsigned int *)&v23[4 * (int)v24 * (v18 + 1)];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1250(const char *a1) {\n unsigned int v2;\n int v3;\n unsigned long long v4;\n long long v5;\n long long *v6;\n short v7;\n signed long long v8;\n void *v9;\n char *v10;\n uint8_t *v11;\n int v12;\n long long v13;\n uint8_t *v14;\n char v15;\n long long v16;\n int v17;\n long long v18;\n uint8_t v21[4088];\n long long v22;\n uint8_t *v23;\n unsigned int v24;\n unsigned int n;\n unsigned long long v26;\n v26 = __readfsqword(40u);\n v2 = strlen(a1);\n v3 = v2 + 1;\n v24 = v2;\n v4 = 4LL * ((int)v2 + 1);\n v5 = 4 * v3 * (long long)v3 + 15;\n v6 = (long long *)((char *)&v22 - (v5 & 18446744073709547520LL));\n v7 = v5 & 65520;\n if (&v22 != v6) {\n while (v21 != (uint8_t *)v6)\n ;\n }\n v8 = v7 & 4095;\n v9 = alloca(v8);\n if (v8) *(uint64_t *)&v21[v8 - 8] = *(uint64_t *)&v21[v8 - 8];\n v10 = v21;\n v23 = v21;\n if ((v24 & 2147483648) == 0LL) {\n v11 = v21;\n v12 = 0;\n n = 4LL * (unsigned int)v24 + 4;\n do {\n ++v12;\n v10 = (char *)memset(v10, 0, n) + v4;\n } while (v12 != v3);\n if (!(uint32_t)v24) {\n v18 = 1LL;\n return *(unsigned int *)&v23[4 * (int)v24 * (v18 + 1)];\n }\n v13 = 1LL;\n v14 = &v23[v4];\n do {\n v15 = a1[v13 - 1];\n v16 = 1LL;\n do {\n while (a1[v16 - 1] == v15 && (uint32_t)v16 != (uint32_t)v13) {\n *(uint32_t *)&v14[4 * v16] = *(uint32_t *)&v11[4 * v16 - 4] + 1;\n if (++v16 == v12) goto LABEL_17;\n }\n v17 = *(uint32_t *)&v11[4 * v16];\n if (v17 < *(uint32_t *)&v14[4 * v16 - 4])\n v17 = *(uint32_t *)&v14[4 * v16 - 4];\n *(uint32_t *)&v14[4 * v16++] = v17;\n } while (v16 != v12);\n LABEL_17:\n ++v13;\n v14 += v4;\n v11 += v4;\n } while (v13 != v16);\n }\n v18 = v4 >> 2;\n return *(unsigned int *)&v23[4 * (int)v24 * (v18 + 1)];\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n unsigned int v2;\n int v3;\n unsigned long long v4;\n long long v5;\n long long *v6;\n short v7;\n signed long long v8;\n void *v9;\n char *v10;\n uint8_t *v11;\n int v12;\n long long v13;\n uint8_t *v14;\n char v15;\n long long v16;\n int v17;\n long long v18;\n uint8_t v21[4088];\n long long v22;\n uint8_t *v23;\n unsigned int v24;\n unsigned int n;\n unsigned long long v26;\n v26 = __readfsqword(40u);\n v2 = strlen(a1);\n v3 = v2 + 1;\n v24 = v2;\n v4 = 4LL * ((int)v2 + 1);\n v5 = 4 * v3 * (long long)v3 + 15;\n v6 = (long long *)((char *)&v22 - (v5 & 18446744073709547520LL));\n v7 = v5 & 65520;\n if (&v22 != v6) {\n while (v21 != (uint8_t *)v6)\n ;\n }\n v8 = v7 & 4095;\n v9 = alloca(v8);\n if (v8) *(uint64_t *)&v21[v8 - 8] = *(uint64_t *)&v21[v8 - 8];\n v10 = v21;\n v23 = v21;\n if ((v24 & 2147483648) == 0LL) {\n v11 = v21;\n v12 = 0;\n n = 4LL * (unsigned int)v24 + 4;\n do {\n ++v12;\n v10 = (char *)memset(v10, 0, n) + v4;\n } while (v12 != v3);\n if (!(uint32_t)v24) {\n v18 = 1LL;\n return *(unsigned int *)&v23[4 * (int)v24 * (v18 + 1)];\n }\n v13 = 1LL;\n v14 = &v23[v4];\n do {\n v15 = a1[v13 - 1];\n v16 = 1LL;\n do {\n while (a1[v16 - 1] == v15 && (uint32_t)v16 != (uint32_t)v13) {\n *(uint32_t *)&v14[4 * v16] = *(uint32_t *)&v11[4 * v16 - 4] + 1;\n if (++v16 == v12) goto LABEL_17;\n }\n v17 = *(uint32_t *)&v11[4 * v16];\n if (v17 < *(uint32_t *)&v14[4 * v16 - 4])\n v17 = *(uint32_t *)&v14[4 * v16 - 4];\n *(uint32_t *)&v14[4 * v16++] = v17;\n } while (v16 != v12);\n LABEL_17:\n ++v13;\n v14 += v4;\n v11 += v4;\n } while (v13 != v16);\n }\n v18 = v4 >> 2;\n return *(unsigned int *)&v23[4 * (int)v24 * (v18 + 1)];\n}" + }, + { + "index": 207, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char *str) {\n int n = strlen(str);\n int dp[n + 1][n + 1];\n for (int i = 0; i <= n; i++) {\n for (int j = 0; j <= n; j++) {\n dp[i][j] = 0;\n }\n }\n for (int i = 1; i <= n; i++) {\n for (int j = 1; j <= n; j++) {\n if (str[i - 1] == str[j - 1] && i != j) {\n dp[i][j] = 1 + dp[i - 1][j - 1];\n } else {\n dp[i][j] = (dp[i][j - 1] > dp[i - 1][j]) ? dp[i][j - 1] : dp[i - 1][j];\n }\n }\n }\n return dp[n][n];\n}", + "test": "int main() {\n\n assert(func0(\"AABEBCDD\") == 3);\n\n assert(func0(\"aabb\") == 2);\n\n assert(func0(\"aab\") == 1);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\nmov %rdi,%r15\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0x38,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\ncallq 1080 \nmov %rsp,%rdi\nlea 0x1(%rax),%r12d\nmov %rax,-0x48(%rbp)\nmovslq %r12d,%rax\nlea 0x0(,%rax,4),%rbx\nimul %rax,%rax\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rdi\nand $0xfffffffffffffff0,%rdx\nmov %rdi,%rax\ncmp %rax,%rsp\nje 12cb \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 12b6 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 13e7 \nmov %rbx,%rax\nmov %rsp,%rdi\nshr $0x2,%rax\nmov %rdi,-0x50(%rbp)\nmov %rax,-0x58(%rbp)\nmov -0x48(%rbp),%rax\ntest %eax,%eax\njs 13b1 \nmov %eax,%eax\nxor %r13d,%r13d\nlea 0x4(,%rax,4),%r14\nnopl 0x0(%rax,%rax,1)\nmov %r14,%rdx\nxor %esi,%esi\nadd $0x1,%r13d\ncallq 10b0 \nmov %rax,%rdi\nadd %rbx,%rdi\ncmp %r12d,%r13d\njne 1310 \nmov -0x48(%rbp),%rax\ntest %eax,%eax\njle 13b1 \nlea -0x1(%rax),%edi\nmov -0x50(%rbp),%rsi\nmov $0x1,%r9d\nlea 0x4(%rbx),%r11\nadd $0x2,%rdi\nnopw 0x0(%rax,%rax,1)\nmovzbl -0x1(%r15,%r9,1),%r10d\nlea (%r11,%rsi,1),%rdx\nmov $0x1,%eax\njmp 1382 \nnopl 0x0(%rax)\nmov -0x4(%rdx),%ecx\ncmp %ecx,(%rsi,%rax,4)\ncmovge (%rsi,%rax,4),%ecx\nadd $0x1,%rax\nadd $0x4,%rdx\nmov %ecx,-0x4(%rdx)\ncmp %rax,%rdi\nje 13a5 \ncmp %r10b,-0x1(%r15,%rax,1)\njne 1368 \ncmp %r9d,%eax\nje 1368 \nmov -0x4(%rsi,%rax,4),%ecx\nadd $0x1,%rax\nadd $0x4,%rdx\nadd $0x1,%ecx\nmov %ecx,-0x4(%rdx)\ncmp %rax,%rdi\njne 1382 \nadd $0x1,%r9\nadd %rbx,%rsi\ncmp %r9,%rdi\njne 1350 \nmov -0x58(%rbp),%rax\nmovslq -0x48(%rbp),%r13\nadd $0x1,%rax\nimul %rax,%r13\nmov -0x50(%rbp),%rax\nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\nmov (%rax,%r13,4),%eax\njne 13f2 \nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 12dd \ncallq 1090 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\nmov r15, rdi\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 38h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\ncall _strlen\nmov rsi, rsp\nlea r14d, [rax+1]\nmov [rbp+var_50], rax\nmovsxd rax, r14d\nlea r12, ds:0[rax*4]\nimul rax, rax\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rsi, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rsi\njz short loc_12C8\nloc_12B3:\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\ncmp rsp, rsi\njnz short loc_12B3\nloc_12C8:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_13E5\nloc_12DA:\nmov rax, [rbp+var_50]\nmov rdi, rsp; s\nmov [rbp+var_58], rdi\ntest eax, eax\njs loc_137D\nmov eax, eax\nmov r13, rdi\nxor ebx, ebx\nlea rax, ds:4[rax*4]\nmov [rbp+n], rax\nloc_1300:\nmov rdx, [rbp+n]; n\nxor esi, esi; c\nadd ebx, 1\ncall _memset\nmov rdi, rax\nadd rdi, r12\ncmp ebx, r14d\njnz short loc_1300\nmov eax, dword ptr [rbp+var_50]\ntest eax, eax\njz loc_13F0\nmov rax, [rbp+var_58]\nmov r9d, ebx\nmov r11d, 1\nlea rdi, [rax+r12]\nnop dword ptr [rax]\nloc_1338:\nmovzx r10d, byte ptr [r15+r11-1]\nmov eax, 1\nnop dword ptr [rax+rax+00h]\nloc_1348:\ncmp [r15+rax-1], r10b\njnz short loc_1354\ncmp eax, r11d\njnz short loc_13B8\nloc_1354:\nmov edx, [r13+rax*4+0]\nmov esi, [rdi+rax*4-4]\ncmp edx, esi\ncmovl edx, esi\nmov [rdi+rax*4], edx\nadd rax, 1\ncmp rax, r9\njnz short loc_1348\nadd r11, 1\nadd rdi, r12\nadd r13, r12\ncmp r11, r9\njnz short loc_1338\nloc_137D:\nmov r8, r12\nshr r8, 2\nloc_1384:\nmovsxd rbx, dword ptr [rbp+var_50]\nlea rax, [r8+1]\nimul rax, rbx\nmov rbx, [rbp+var_58]\nmov eax, [rbx+rax*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_13F8\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_13B8:\nmov ecx, [r13+rax*4-4]\nlea edx, [rcx+1]\nmov [rdi+rax*4], edx\nadd rax, 1\ncmp rax, r9\njnz loc_1348\nadd r11, 1\nadd rdi, r12\nadd r13, r12\ncmp r11, r9\njnz loc_1338\njmp short loc_137D\nloc_13E5:\nor [rsp+rdx+1060h+var_1068], 0\njmp loc_12DA\nloc_13F0:\nmov r8d, 1\njmp short loc_1384\nloc_13F8:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n size_t v2; // rax\n int v3; // r14d\n unsigned __int64 v4; // r12\n __int64 v5; // rdx\n __int64 *v6; // rsi\n __int16 v7; // dx\n signed __int64 v8; // rdx\n void *v9; // rsp\n char *v10; // rdi\n _BYTE *v11; // r13\n int v12; // ebx\n __int64 v13; // r11\n _BYTE *v14; // rdi\n char v15; // r10\n __int64 v16; // rax\n int v17; // edx\n __int64 v18; // r8\n _BYTE v21[4088]; // [rsp+8h] [rbp-1060h] BYREF\n __int64 v22; // [rsp+1008h] [rbp-60h] BYREF\n _BYTE *v23; // [rsp+1010h] [rbp-58h]\n size_t v24; // [rsp+1018h] [rbp-50h]\n size_t n; // [rsp+1020h] [rbp-48h]\n unsigned __int64 v26; // [rsp+1030h] [rbp-38h]\n\n v26 = __readfsqword(0x28u);\n v2 = strlen(a1);\n v3 = v2 + 1;\n v24 = v2;\n v4 = 4LL * ((int)v2 + 1);\n v5 = 4 * v3 * (__int64)v3 + 15;\n v6 = (__int64 *)((char *)&v22 - (v5 & 0xFFFFFFFFFFFFF000LL));\n v7 = v5 & 0xFFF0;\n if ( &v22 != v6 )\n {\n while ( v21 != (_BYTE *)v6 )\n ;\n }\n v8 = v7 & 0xFFF;\n v9 = alloca(v8);\n if ( v8 )\n *(_QWORD *)&v21[v8 - 8] = *(_QWORD *)&v21[v8 - 8];\n v10 = v21;\n v23 = v21;\n if ( (v24 & 0x80000000) == 0LL )\n {\n v11 = v21;\n v12 = 0;\n n = 4LL * (unsigned int)v24 + 4;\n do\n {\n ++v12;\n v10 = (char *)memset(v10, 0, n) + v4;\n }\n while ( v12 != v3 );\n if ( !(_DWORD)v24 )\n {\n v18 = 1LL;\n return *(unsigned int *)&v23[4 * (int)v24 * (v18 + 1)];\n }\n v13 = 1LL;\n v14 = &v23[v4];\nLABEL_10:\n while ( 2 )\n {\n v15 = a1[v13 - 1];\n v16 = 1LL;\n do\n {\n while ( a1[v16 - 1] != v15 || (_DWORD)v16 == (_DWORD)v13 )\n {\n v17 = *(_DWORD *)&v11[4 * v16];\n if ( v17 < *(_DWORD *)&v14[4 * v16 - 4] )\n v17 = *(_DWORD *)&v14[4 * v16 - 4];\n *(_DWORD *)&v14[4 * v16++] = v17;\n if ( v16 == v12 )\n {\n ++v13;\n v14 += v4;\n v11 += v4;\n if ( v13 != v12 )\n goto LABEL_10;\n goto LABEL_17;\n }\n }\n *(_DWORD *)&v14[4 * v16] = *(_DWORD *)&v11[4 * v16 - 4] + 1;\n ++v16;\n }\n while ( v16 != v12 );\n ++v13;\n v14 += v4;\n v11 += v4;\n if ( v13 != v12 )\n continue;\n break;\n }\n }\nLABEL_17:\n v18 = v4 >> 2;\n return *(unsigned int *)&v23[4 * (int)v24 * (v18 + 1)];\n}", + "ida_strip_asm": "sub_1250:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\nmov r15, rdi\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 38h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\ncall _strlen\nmov rsi, rsp\nlea r14d, [rax+1]\nmov [rbp+var_50], rax\nmovsxd rax, r14d\nlea r12, ds:0[rax*4]\nimul rax, rax\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rsi, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rsi\njz short loc_12C8\nloc_12B3:\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\ncmp rsp, rsi\njnz short loc_12B3\nloc_12C8:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_13E5\nloc_12DA:\nmov rax, [rbp+var_50]\nmov rdi, rsp; s\nmov [rbp+var_58], rdi\ntest eax, eax\njs loc_137D\nmov eax, eax\nmov r13, rdi\nxor ebx, ebx\nlea rax, ds:4[rax*4]\nmov [rbp+n], rax\nloc_1300:\nmov rdx, [rbp+n]; n\nxor esi, esi; c\nadd ebx, 1\ncall _memset\nmov rdi, rax\nadd rdi, r12\ncmp ebx, r14d\njnz short loc_1300\nmov eax, dword ptr [rbp+var_50]\ntest eax, eax\njz loc_13F0\nmov rax, [rbp+var_58]\nmov r9d, ebx\nmov r11d, 1\nlea rdi, [rax+r12]\nnop dword ptr [rax]\nloc_1338:\nmovzx r10d, byte ptr [r15+r11-1]\nmov eax, 1\nnop dword ptr [rax+rax+00h]\nloc_1348:\ncmp [r15+rax-1], r10b\njnz short loc_1354\ncmp eax, r11d\njnz short loc_13B8\nloc_1354:\nmov edx, [r13+rax*4+0]\nmov esi, [rdi+rax*4-4]\ncmp edx, esi\ncmovl edx, esi\nmov [rdi+rax*4], edx\nadd rax, 1\ncmp rax, r9\njnz short loc_1348\nadd r11, 1\nadd rdi, r12\nadd r13, r12\ncmp r11, r9\njnz short loc_1338\nloc_137D:\nmov r8, r12\nshr r8, 2\nloc_1384:\nmovsxd rbx, dword ptr [rbp+var_50]\nlea rax, [r8+1]\nimul rax, rbx\nmov rbx, [rbp+var_58]\nmov eax, [rbx+rax*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_13F8\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_13B8:\nmov ecx, [r13+rax*4-4]\nlea edx, [rcx+1]\nmov [rdi+rax*4], edx\nadd rax, 1\ncmp rax, r9\njnz loc_1348\nadd r11, 1\nadd rdi, r12\nadd r13, r12\ncmp r11, r9\njnz loc_1338\njmp short loc_137D\nloc_13E5:\nor [rsp+rdx+1060h+var_1068], 0\njmp loc_12DA\nloc_13F0:\nmov r8d, 1\njmp short loc_1384\nloc_13F8:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1250(const char *a1)\n{\n size_t v2; // rax\n int v3; // r14d\n unsigned __int64 v4; // r12\n __int64 v5; // rdx\n __int64 *v6; // rsi\n __int16 v7; // dx\n signed __int64 v8; // rdx\n void *v9; // rsp\n char *v10; // rdi\n _BYTE *v11; // r13\n int v12; // ebx\n __int64 v13; // r11\n _BYTE *v14; // rdi\n char v15; // r10\n __int64 v16; // rax\n int v17; // edx\n __int64 v18; // r8\n _BYTE v21[4088]; // [rsp+8h] [rbp-1060h] BYREF\n __int64 v22; // [rsp+1008h] [rbp-60h] BYREF\n _BYTE *v23; // [rsp+1010h] [rbp-58h]\n size_t v24; // [rsp+1018h] [rbp-50h]\n size_t n; // [rsp+1020h] [rbp-48h]\n unsigned __int64 v26; // [rsp+1030h] [rbp-38h]\n\n v26 = __readfsqword(0x28u);\n v2 = strlen(a1);\n v3 = v2 + 1;\n v24 = v2;\n v4 = 4LL * ((int)v2 + 1);\n v5 = 4 * v3 * (__int64)v3 + 15;\n v6 = (__int64 *)((char *)&v22 - (v5 & 0xFFFFFFFFFFFFF000LL));\n v7 = v5 & 0xFFF0;\n if ( &v22 != v6 )\n {\n while ( v21 != (_BYTE *)v6 )\n ;\n }\n v8 = v7 & 0xFFF;\n v9 = alloca(v8);\n if ( v8 )\n *(_QWORD *)&v21[v8 - 8] = *(_QWORD *)&v21[v8 - 8];\n v10 = v21;\n v23 = v21;\n if ( (v24 & 0x80000000) == 0LL )\n {\n v11 = v21;\n v12 = 0;\n n = 4LL * (unsigned int)v24 + 4;\n do\n {\n ++v12;\n v10 = (char *)memset(v10, 0, n) + v4;\n }\n while ( v12 != v3 );\n if ( !(_DWORD)v24 )\n {\n v18 = 1LL;\n return *(unsigned int *)&v23[4 * (int)v24 * (v18 + 1)];\n }\n v13 = 1LL;\n v14 = &v23[v4];\nLABEL_10:\n while ( 2 )\n {\n v15 = a1[v13 - 1];\n v16 = 1LL;\n do\n {\n while ( a1[v16 - 1] != v15 || (_DWORD)v16 == (_DWORD)v13 )\n {\n v17 = *(_DWORD *)&v11[4 * v16];\n if ( v17 < *(_DWORD *)&v14[4 * v16 - 4] )\n v17 = *(_DWORD *)&v14[4 * v16 - 4];\n *(_DWORD *)&v14[4 * v16++] = v17;\n if ( v16 == v12 )\n {\n ++v13;\n v14 += v4;\n v11 += v4;\n if ( v13 != v12 )\n goto LABEL_10;\n goto LABEL_17;\n }\n }\n *(_DWORD *)&v14[4 * v16] = *(_DWORD *)&v11[4 * v16 - 4] + 1;\n ++v16;\n }\n while ( v16 != v12 );\n ++v13;\n v14 += v4;\n v11 += v4;\n if ( v13 != v12 )\n continue;\n break;\n }\n }\nLABEL_17:\n v18 = v4 >> 2;\n return *(unsigned int *)&v23[4 * (int)v24 * (v18 + 1)];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1250(const char *a1) {\n unsigned int v2;\n int v3;\n unsigned long long v4;\n long long v5;\n long long *v6;\n short v7;\n signed long long v8;\n void *v9;\n char *v10;\n uint8_t *v11;\n int v12;\n long long v13;\n uint8_t *v14;\n char v15;\n long long v16;\n int v17;\n long long v18;\n uint8_t v21[4088];\n long long v22;\n uint8_t *v23;\n unsigned int v24;\n unsigned int n;\n unsigned long long v26;\n v26 = __readfsqword(40u);\n v2 = strlen(a1);\n v3 = v2 + 1;\n v24 = v2;\n v4 = 4LL * ((int)v2 + 1);\n v5 = 4 * v3 * (long long)v3 + 15;\n v6 = (long long *)((char *)&v22 - (v5 & 18446744073709547520LL));\n v7 = v5 & 65520;\n if (&v22 != v6) {\n while (v21 != (uint8_t *)v6)\n ;\n }\n v8 = v7 & 4095;\n v9 = alloca(v8);\n if (v8) *(uint64_t *)&v21[v8 - 8] = *(uint64_t *)&v21[v8 - 8];\n v10 = v21;\n v23 = v21;\n if ((v24 & 2147483648) == 0LL) {\n v11 = v21;\n v12 = 0;\n n = 4LL * (unsigned int)v24 + 4;\n do {\n ++v12;\n v10 = (char *)memset(v10, 0, n) + v4;\n } while (v12 != v3);\n if (!(uint32_t)v24) {\n v18 = 1LL;\n return *(unsigned int *)&v23[4 * (int)v24 * (v18 + 1)];\n }\n v13 = 1LL;\n v14 = &v23[v4];\n LABEL_10:\n while (2) {\n v15 = a1[v13 - 1];\n v16 = 1LL;\n do {\n while (a1[v16 - 1] != v15 || (uint32_t)v16 == (uint32_t)v13) {\n v17 = *(uint32_t *)&v11[4 * v16];\n if (v17 < *(uint32_t *)&v14[4 * v16 - 4])\n v17 = *(uint32_t *)&v14[4 * v16 - 4];\n *(uint32_t *)&v14[4 * v16++] = v17;\n if (v16 == v12) {\n ++v13;\n v14 += v4;\n v11 += v4;\n if (v13 != v12) goto LABEL_10;\n goto LABEL_17;\n }\n }\n *(uint32_t *)&v14[4 * v16] = *(uint32_t *)&v11[4 * v16 - 4] + 1;\n ++v16;\n } while (v16 != v12);\n ++v13;\n v14 += v4;\n v11 += v4;\n if (v13 != v12) continue;\n break;\n }\n }\nLABEL_17:\n v18 = v4 >> 2;\n return *(unsigned int *)&v23[4 * (int)v24 * (v18 + 1)];\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n unsigned int v2;\n int v3;\n unsigned long long v4;\n long long v5;\n long long *v6;\n short v7;\n signed long long v8;\n void *v9;\n char *v10;\n uint8_t *v11;\n int v12;\n long long v13;\n uint8_t *v14;\n char v15;\n long long v16;\n int v17;\n long long v18;\n uint8_t v21[4088];\n long long v22;\n uint8_t *v23;\n unsigned int v24;\n unsigned int n;\n unsigned long long v26;\n v26 = __readfsqword(40u);\n v2 = strlen(a1);\n v3 = v2 + 1;\n v24 = v2;\n v4 = 4LL * ((int)v2 + 1);\n v5 = 4 * v3 * (long long)v3 + 15;\n v6 = (long long *)((char *)&v22 - (v5 & 18446744073709547520LL));\n v7 = v5 & 65520;\n if (&v22 != v6) {\n while (v21 != (uint8_t *)v6)\n ;\n }\n v8 = v7 & 4095;\n v9 = alloca(v8);\n if (v8) *(uint64_t *)&v21[v8 - 8] = *(uint64_t *)&v21[v8 - 8];\n v10 = v21;\n v23 = v21;\n if ((v24 & 2147483648) == 0LL) {\n v11 = v21;\n v12 = 0;\n n = 4LL * (unsigned int)v24 + 4;\n do {\n ++v12;\n v10 = (char *)memset(v10, 0, n) + v4;\n } while (v12 != v3);\n if (!(uint32_t)v24) {\n v18 = 1LL;\n return *(unsigned int *)&v23[4 * (int)v24 * (v18 + 1)];\n }\n v13 = 1LL;\n v14 = &v23[v4];\n LABEL_10:\n while (2) {\n v15 = a1[v13 - 1];\n v16 = 1LL;\n do {\n while (a1[v16 - 1] != v15 || (uint32_t)v16 == (uint32_t)v13) {\n v17 = *(uint32_t *)&v11[4 * v16];\n if (v17 < *(uint32_t *)&v14[4 * v16 - 4])\n v17 = *(uint32_t *)&v14[4 * v16 - 4];\n *(uint32_t *)&v14[4 * v16++] = v17;\n if (v16 == v12) {\n ++v13;\n v14 += v4;\n v11 += v4;\n if (v13 != v12) goto LABEL_10;\n goto LABEL_17;\n }\n }\n *(uint32_t *)&v14[4 * v16] = *(uint32_t *)&v11[4 * v16 - 4] + 1;\n ++v16;\n } while (v16 != v12);\n ++v13;\n v14 += v4;\n v11 += v4;\n if (v13 != v12) continue;\n break;\n }\n }\nLABEL_17:\n v18 = v4 >> 2;\n return *(unsigned int *)&v23[4 * (int)v24 * (v18 + 1)];\n}" + }, + { + "index": 208, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *num) {\n regex_t reg;\n const char *pattern = \"^[0-9]+(\\\\.[0-9]{1,2})?$\";\n regcomp(®, pattern, REG_EXTENDED);\n int result = regexec(®, num, 0, NULL, 0);\n regfree(®);\n return (result == 0);\n}", + "test": "int main() {\n\n assert(func0(\"123.11\") == 1);\n\n assert(func0(\"0.21\") == 1);\n\n assert(func0(\"123.1214\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x70,%rsp\nmov %rdi,-0x68(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0xe19(%rip),%rax\nmov %rax,-0x58(%rbp)\nmov -0x58(%rbp),%rcx\nlea -0x50(%rbp),%rax\nmov $0x1,%edx\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 10c0 \nmov -0x68(%rbp),%rsi\nlea -0x50(%rbp),%rax\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rax,%rdi\ncallq 10d0 \nmov %eax,-0x5c(%rbp)\nlea -0x50(%rbp),%rax\nmov %rax,%rdi\ncallq 1090 \ncmpl $0x0,-0x5c(%rbp)\nsete %al\nmovzbl %al,%eax\nmov -0x8(%rbp),%rdx\nxor %fs:0x28,%rdx\nje 1258 \ncallq 10a0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, a090912; \"^[0-9]+(\\\\.[0-9]{1,2})?$\"\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_5C], eax\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\ncmp [rbp+var_5C], 0\nsetz al\nmovzx eax, al\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1258\ncall ___stack_chk_fail\nlocret_1258:\nleave\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(const char *a1)\n{\n int v2; // [rsp+14h] [rbp-5Ch]\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n unsigned __int64 v4; // [rsp+68h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n regcomp(&preg, \"^[0-9]+(\\\\.[0-9]{1,2})?$\", 1);\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n return v2 == 0;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, a090912; \"^[0-9]+(\\\\.[0-9]{1,2})?$\"\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_5C], eax\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\ncmp [rbp+var_5C], 0\nsetz al\nmovzx eax, al\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1258\ncall ___stack_chk_fail\nlocret_1258:\nleave\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_11C9(const char *a1)\n{\n int v2; // [rsp+14h] [rbp-5Ch]\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n unsigned __int64 v4; // [rsp+68h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n regcomp(&preg, \"^[0-9]+(\\\\.[0-9]{1,2})?$\", 1);\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n return v2 == 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_11C9(const char *a1) {\n int v2;\n regex_t preg;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n regcomp(&preg, \"^[0-9]+(\\\\.[0-9]{1,2})?$\", 1);\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n return v2 == 0;\n}", + "ida_pseudo_norm": "uint8_t func0(const char *a1) {\n int v2;\n regex_t preg;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n regcomp(&preg, \"^[0-9]+(\\\\.[0-9]{1,2})?$\", 1);\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n return v2 == 0;\n}" + }, + { + "index": 208, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *num) {\n regex_t reg;\n const char *pattern = \"^[0-9]+(\\\\.[0-9]{1,2})?$\";\n regcomp(®, pattern, REG_EXTENDED);\n int result = regexec(®, num, 0, NULL, 0);\n regfree(®);\n return (result == 0);\n}", + "test": "int main() {\n\n assert(func0(\"123.11\") == 1);\n\n assert(func0(\"0.21\") == 1);\n\n assert(func0(\"123.1214\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nsub $0x50,%rsp\nmov %rdi,%rbx\nmov $0x28,%r12d\nmov %fs:(%r12),%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%rbp\nmov $0x1,%edx\nlea 0xe0b(%rip),%rsi\nmov %rbp,%rdi\ncallq 10c0 \nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rbx,%rsi\nmov %rbp,%rdi\ncallq 10d0 \nmov %eax,%ebx\nmov %rbp,%rdi\ncallq 1090 \ntest %ebx,%ebx\nsete %al\nmov 0x48(%rsp),%rcx\nxor %fs:(%r12),%rcx\njne 1243 \nmovzbl %al,%eax\nadd $0x50,%rsp\npop %rbx\npop %rbp\npop %r12\nretq\ncallq 10a0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov edx, 1; cflags\nlea rsi, pattern; \"^[0-9]+(\\\\.[0-9]{1,2})?$\"\nmov rdi, rbp; preg\ncall _regcomp\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov ebx, eax\nmov rdi, rbp; preg\ncall _regfree\ntest ebx, ebx\nsetz al\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_1241\nmovzx eax, al\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1241:\ncall ___stack_chk_fail", + "ida_pseudo": "_BOOL8 __fastcall func0(char *string)\n{\n int v1; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \"^[0-9]+(\\\\.[0-9]{1,2})?$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 0;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov edx, 1; cflags\nlea rsi, pattern; \"^[0-9]+(\\\\.[0-9]{1,2})?$\"\nmov rdi, rbp; preg\ncall _regcomp\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov ebx, eax\nmov rdi, rbp; preg\ncall _regfree\ntest ebx, ebx\nsetz al\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_1241\nmovzx eax, al\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1241:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_11C9(char *string)\n{\n int v1; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \"^[0-9]+(\\\\.[0-9]{1,2})?$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_11C9(char *string) {\n int v1;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \"^[0-9]+(\\\\.[0-9]{1,2})?$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 0;\n}", + "ida_pseudo_norm": "uint8_t func0(char *string) {\n int v1;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \"^[0-9]+(\\\\.[0-9]{1,2})?$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 0;\n}" + }, + { + "index": 208, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *num) {\n regex_t reg;\n const char *pattern = \"^[0-9]+(\\\\.[0-9]{1,2})?$\";\n regcomp(®, pattern, REG_EXTENDED);\n int result = regexec(®, num, 0, NULL, 0);\n regfree(®);\n return (result == 0);\n}", + "test": "int main() {\n\n assert(func0(\"123.11\") == 1);\n\n assert(func0(\"0.21\") == 1);\n\n assert(func0(\"123.1214\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov $0x1,%edx\nmov %rdi,%r12\nlea 0xd7f(%rip),%rsi\npush %rbp\npush %rbx\nsub $0x50,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%rbp\nmov %rbp,%rdi\ncallq 10c0 \nxor %ecx,%ecx\nxor %r8d,%r8d\nxor %edx,%edx\nmov %r12,%rsi\nmov %rbp,%rdi\ncallq 10d0 \nmov %rbp,%rdi\nmov %eax,%ebx\ncallq 1090 \ntest %ebx,%ebx\nsete %al\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 12e3 \nadd $0x50,%rsp\nmovzbl %al,%eax\npop %rbx\npop %rbp\npop %r12\nretq\ncallq 10a0 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"^[0-9]+(\\\\.[0-9]{1,2})?$\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nsetz al\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_12DF\nadd rsp, 58h\nmovzx eax, al\npop rbx\npop rbp\nretn\nloc_12DF:\ncall ___stack_chk_fail", + "ida_pseudo": "_BOOL8 __fastcall func0(char *string)\n{\n int v1; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \"^[0-9]+(\\\\.[0-9]{1,2})?$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 0;\n}", + "ida_strip_asm": "sub_1270:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"^[0-9]+(\\\\.[0-9]{1,2})?$\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nsetz al\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_12DF\nadd rsp, 58h\nmovzx eax, al\npop rbx\npop rbp\nretn\nloc_12DF:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1270(char *string)\n{\n int v1; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \"^[0-9]+(\\\\.[0-9]{1,2})?$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1270(char *string) {\n int v1;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \"^[0-9]+(\\\\.[0-9]{1,2})?$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 0;\n}", + "ida_pseudo_norm": "uint8_t func0(char *string) {\n int v1;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \"^[0-9]+(\\\\.[0-9]{1,2})?$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 0;\n}" + }, + { + "index": 208, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *num) {\n regex_t reg;\n const char *pattern = \"^[0-9]+(\\\\.[0-9]{1,2})?$\";\n regcomp(®, pattern, REG_EXTENDED);\n int result = regexec(®, num, 0, NULL, 0);\n regfree(®);\n return (result == 0);\n}", + "test": "int main() {\n\n assert(func0(\"123.11\") == 1);\n\n assert(func0(\"0.21\") == 1);\n\n assert(func0(\"123.1214\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov $0x1,%edx\nmov %rdi,%r12\nlea 0xd7f(%rip),%rsi\npush %rbp\npush %rbx\nsub $0x50,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%rbp\nmov %rbp,%rdi\ncallq 10c0 \nxor %ecx,%ecx\nxor %r8d,%r8d\nxor %edx,%edx\nmov %r12,%rsi\nmov %rbp,%rdi\ncallq 10d0 \nmov %rbp,%rdi\nmov %eax,%ebx\ncallq 1090 \ntest %ebx,%ebx\nsete %al\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 12e3 \nadd $0x50,%rsp\nmovzbl %al,%eax\npop %rbx\npop %rbp\npop %r12\nretq\ncallq 10a0 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"^[0-9]+(\\\\.[0-9]{1,2})?$\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nsetz al\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_12DF\nadd rsp, 58h\nmovzx eax, al\npop rbx\npop rbp\nretn\nloc_12DF:\ncall ___stack_chk_fail", + "ida_pseudo": "_BOOL8 __fastcall func0(char *string)\n{\n int v1; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \"^[0-9]+(\\\\.[0-9]{1,2})?$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 0;\n}", + "ida_strip_asm": "sub_1270:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"^[0-9]+(\\\\.[0-9]{1,2})?$\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nsetz al\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_12DF\nadd rsp, 58h\nmovzx eax, al\npop rbx\npop rbp\nretn\nloc_12DF:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1270(char *string)\n{\n int v1; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \"^[0-9]+(\\\\.[0-9]{1,2})?$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1270(char *string) {\n int v1;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \"^[0-9]+(\\\\.[0-9]{1,2})?$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 0;\n}", + "ida_pseudo_norm": "uint8_t func0(char *string) {\n int v1;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \"^[0-9]+(\\\\.[0-9]{1,2})?$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 0;\n}" + }, + { + "index": 209, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nvoid heapify(int heap[], int n, int i) {\n\n int smallest = i;\n\n int l = 2 * i + 1;\n\n int r = 2 * i + 2;\n\n\n\n if (l < n && heap[l] < heap[smallest])\n\n smallest = l;\n\n\n\n if (r < n && heap[r] < heap[smallest])\n\n smallest = r;\n\n\n\n if (smallest != i) {\n\n int temp = heap[i];\n\n heap[i] = heap[smallest];\n\n heap[smallest] = temp;\n\n heapify(heap, n, smallest);\n\n }\n\n}\n\n\n\nvoid buildHeap(int heap[], int n) {\n\n int startIdx = (n / 2) - 1;\n\n for (int i = startIdx; i >= 0; i--) {\n\n heapify(heap, n, i);\n\n }\n\n}\n\n\n\n", + "func": "void func0(int heap[], int n, int a, int* outHeap) {\n buildHeap(heap, n);\n if (a < heap[0]) return;\n heap[0] = a;\n heapify(heap, n, 0);\n for (int i = 0; i < n; i++) {\n outHeap[i] = heap[i];\n }\n}", + "test": "int main() {\n\n int testHeap1[] = {25, 44, 68, 21, 39, 23, 89};\n\n int testHeap2[] = {25, 44, 68, 21, 39, 23, 89};\n\n int testHeap3[] = {25, 44, 68, 21, 39, 23, 89};\n\n\n\n int outHeap1[7], outHeap2[7], outHeap3[7];\n\n\n\n func0(testHeap1, 7, 21, outHeap1);\n\n func0(testHeap2, 7, 110, outHeap2);\n\n func0(testHeap3, 7, 500, outHeap3);\n\n\n\n int expectedHeap1[] = {21, 25, 23, 44, 39, 68, 89};\n\n int expectedHeap2[] = {23, 25, 68, 44, 39, 110, 89};\n\n int expectedHeap3[] = {23, 25, 68, 44, 39, 500, 89};\n\n\n\n for (int i = 0; i < 7; i++) {\n\n assert(outHeap1[i] == expectedHeap1[i]);\n\n assert(outHeap2[i] == expectedHeap2[i]);\n\n assert(outHeap3[i] == expectedHeap3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmov %rcx,-0x28(%rbp)\nmov -0x1c(%rbp),%edx\nmov -0x18(%rbp),%rax\nmov %edx,%esi\nmov %rax,%rdi\ncallq 1295 \nmov -0x18(%rbp),%rax\nmov (%rax),%eax\ncmp %eax,-0x20(%rbp)\njl 137d \nmov -0x18(%rbp),%rax\nmov -0x20(%rbp),%edx\nmov %edx,(%rax)\nmov -0x1c(%rbp),%ecx\nmov -0x18(%rbp),%rax\nmov $0x0,%edx\nmov %ecx,%esi\nmov %rax,%rdi\ncallq 1169 \nmovl $0x0,-0x4(%rbp)\njmp 1373 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0x4(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x28(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1342 \njmp 137e \nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_28], rcx\nmov edx, [rbp+var_1C]\nmov rax, [rbp+var_18]\nmov esi, edx\nmov rdi, rax\ncall buildHeap\nmov rax, [rbp+var_18]\nmov eax, [rax]\ncmp [rbp+var_20], eax\njl short loc_137D\nmov rax, [rbp+var_18]\nmov edx, [rbp+var_20]\nmov [rax], edx\nmov ecx, [rbp+var_1C]\nmov rax, [rbp+var_18]\nmov edx, 0\nmov esi, ecx\nmov rdi, rax\ncall heapify\nmov [rbp+var_4], 0\njmp short loc_1373\nloc_1342:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_4], 1\nloc_1373:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1342\njmp short locret_137E\nloc_137D:\nnop\nlocret_137E:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int *a1, unsigned int a2, int a3, __int64 a4)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+2Ch] [rbp-4h]\n\n buildHeap(a1, a2);\n result = (unsigned int)*a1;\n if ( a3 >= (int)result )\n {\n *a1 = a3;\n heapify(a1, a2, 0LL);\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= (int)a2 )\n break;\n *(_DWORD *)(4LL * (int)i + a4) = a1[i];\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_12E4:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_28], rcx\nmov edx, [rbp+var_1C]\nmov rax, [rbp+var_18]\nmov esi, edx\nmov rdi, rax\ncall sub_1295\nmov rax, [rbp+var_18]\nmov eax, [rax]\ncmp [rbp+var_20], eax\njl short loc_137D\nmov rax, [rbp+var_18]\nmov edx, [rbp+var_20]\nmov [rax], edx\nmov ecx, [rbp+var_1C]\nmov rax, [rbp+var_18]\nmov edx, 0\nmov esi, ecx\nmov rdi, rax\ncall sub_1169\nmov [rbp+var_4], 0\njmp short loc_1373\nloc_1342:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_4], 1\nloc_1373:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1342\njmp short locret_137E\nloc_137D:\nnop\nlocret_137E:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12E4(int *a1, unsigned int a2, int a3, __int64 a4)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+2Ch] [rbp-4h]\n\n sub_1295(a1, a2);\n result = (unsigned int)*a1;\n if ( a3 >= (int)result )\n {\n *a1 = a3;\n sub_1169(a1, a2, 0LL);\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= (int)a2 )\n break;\n *(_DWORD *)(4LL * (int)i + a4) = a1[i];\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12E4(int *a1, unsigned int a2, int a3, long long a4) {\n long long result;\n unsigned int i;\n sub_1295(a1, a2);\n result = (unsigned int)*a1;\n if (a3 >= (int)result) {\n *a1 = a3;\n sub_1169(a1, a2, 0LL);\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= (int)a2) break;\n *(uint32_t *)(4LL * (int)i + a4) = a1[i];\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(int *a1, unsigned int a2, int a3, long long a4) {\n long long result;\n unsigned int i;\n buildHeap(a1, a2);\n result = (unsigned int)*a1;\n if (a3 >= (int)result) {\n *a1 = a3;\n heapify(a1, a2, 0LL);\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= (int)a2) break;\n *(uint32_t *)(4LL * (int)i + a4) = a1[i];\n }\n }\n return result;\n}" + }, + { + "index": 209, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nvoid heapify(int heap[], int n, int i) {\n\n int smallest = i;\n\n int l = 2 * i + 1;\n\n int r = 2 * i + 2;\n\n\n\n if (l < n && heap[l] < heap[smallest])\n\n smallest = l;\n\n\n\n if (r < n && heap[r] < heap[smallest])\n\n smallest = r;\n\n\n\n if (smallest != i) {\n\n int temp = heap[i];\n\n heap[i] = heap[smallest];\n\n heap[smallest] = temp;\n\n heapify(heap, n, smallest);\n\n }\n\n}\n\n\n\nvoid buildHeap(int heap[], int n) {\n\n int startIdx = (n / 2) - 1;\n\n for (int i = startIdx; i >= 0; i--) {\n\n heapify(heap, n, i);\n\n }\n\n}\n\n\n\n", + "func": "void func0(int heap[], int n, int a, int* outHeap) {\n buildHeap(heap, n);\n if (a < heap[0]) return;\n heap[0] = a;\n heapify(heap, n, 0);\n for (int i = 0; i < n; i++) {\n outHeap[i] = heap[i];\n }\n}", + "test": "int main() {\n\n int testHeap1[] = {25, 44, 68, 21, 39, 23, 89};\n\n int testHeap2[] = {25, 44, 68, 21, 39, 23, 89};\n\n int testHeap3[] = {25, 44, 68, 21, 39, 23, 89};\n\n\n\n int outHeap1[7], outHeap2[7], outHeap3[7];\n\n\n\n func0(testHeap1, 7, 21, outHeap1);\n\n func0(testHeap2, 7, 110, outHeap2);\n\n func0(testHeap3, 7, 500, outHeap3);\n\n\n\n int expectedHeap1[] = {21, 25, 23, 44, 39, 68, 89};\n\n int expectedHeap2[] = {23, 25, 68, 44, 39, 110, 89};\n\n int expectedHeap3[] = {23, 25, 68, 44, 39, 500, 89};\n\n\n\n for (int i = 0; i < 7; i++) {\n\n assert(outHeap1[i] == expectedHeap1[i]);\n\n assert(outHeap2[i] == expectedHeap2[i]);\n\n assert(outHeap3[i] == expectedHeap3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbx\nmov %esi,%r12d\nmov %edx,%r13d\nmov %rcx,%rbp\ncallq 11e5 \ncmp %r13d,(%rbx)\njle 1248 \nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nmov %r13d,(%rbx)\nmov $0x0,%edx\nmov %r12d,%esi\nmov %rbx,%rdi\ncallq 1169 \ntest %r12d,%r12d\njle 123d \nlea -0x1(%r12),%ecx\nmov $0x0,%eax\nmov (%rbx,%rax,4),%edx\nmov %edx,0x0(%rbp,%rax,4)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rcx,%rdx\njne 126a \njmp 123d \n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov ebx, esi\nmov r13d, edx\nmov r12, rcx\ncall buildHeap\ncmp [rbp+0], r13d\njle short loc_1248\nloc_123D:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1248:\nmov [rbp+0], r13d\nmov edx, 0\nmov esi, ebx\nmov rdi, rbp\ncall heapify\ntest ebx, ebx\njle short loc_123D\nmovsxd rdx, ebx\nshl rdx, 2\nmov eax, 0\nloc_126B:\nmov ecx, [rbp+rax+0]\nmov [r12+rax], ecx\nadd rax, 4\ncmp rax, rdx\njnz short loc_126B\njmp short loc_123D", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2, int a3, __int64 a4)\n{\n __int64 result; // rax\n\n result = buildHeap();\n if ( *a1 <= a3 )\n {\n *a1 = a3;\n result = heapify(a1, (unsigned int)a2, 0LL);\n if ( a2 > 0 )\n {\n result = 0LL;\n do\n {\n *(_DWORD *)(a4 + result) = *(_DWORD *)((char *)a1 + result);\n result += 4LL;\n }\n while ( result != 4LL * a2 );\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1219:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov ebx, esi\nmov r13d, edx\nmov r12, rcx\ncall sub_11E5\ncmp [rbp+0], r13d\njle short loc_1248\nloc_123D:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1248:\nmov [rbp+0], r13d\nmov edx, 0\nmov esi, ebx\nmov rdi, rbp\ncall sub_1169\ntest ebx, ebx\njle short loc_123D\nmovsxd rdx, ebx\nshl rdx, 2\nmov eax, 0\nloc_126B:\nmov ecx, [rbp+rax+0]\nmov [r12+rax], ecx\nadd rax, 4\ncmp rax, rdx\njnz short loc_126B\njmp short loc_123D", + "ida_strip_pseudo": "__int64 __fastcall sub_1219(_DWORD *a1, int a2, int a3, __int64 a4)\n{\n __int64 result; // rax\n\n result = sub_11E5();\n if ( *a1 <= a3 )\n {\n *a1 = a3;\n result = sub_1169(a1, (unsigned int)a2, 0LL);\n if ( a2 > 0 )\n {\n result = 0LL;\n do\n {\n *(_DWORD *)(a4 + result) = *(_DWORD *)((char *)a1 + result);\n result += 4LL;\n }\n while ( result != 4LL * a2 );\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1219(uint32_t *a1, int a2, int a3, long long a4) {\n long long result;\n result = sub_11E5();\n if (*a1 <= a3) {\n *a1 = a3;\n result = sub_1169(a1, (unsigned int)a2, 0LL);\n if (a2 > 0) {\n result = 0LL;\n do {\n *(uint32_t *)(a4 + result) = *(uint32_t *)((char *)a1 + result);\n result += 4LL;\n } while (result != 4LL * a2);\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2, int a3, long long a4) {\n long long result;\n result = buildHeap();\n if (*a1 <= a3) {\n *a1 = a3;\n result = heapify(a1, (unsigned int)a2, 0LL);\n if (a2 > 0) {\n result = 0LL;\n do {\n *(uint32_t *)(a4 + result) = *(uint32_t *)((char *)a1 + result);\n result += 4LL;\n } while (result != 4LL * a2);\n }\n }\n return result;\n}" + }, + { + "index": 209, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nvoid heapify(int heap[], int n, int i) {\n\n int smallest = i;\n\n int l = 2 * i + 1;\n\n int r = 2 * i + 2;\n\n\n\n if (l < n && heap[l] < heap[smallest])\n\n smallest = l;\n\n\n\n if (r < n && heap[r] < heap[smallest])\n\n smallest = r;\n\n\n\n if (smallest != i) {\n\n int temp = heap[i];\n\n heap[i] = heap[smallest];\n\n heap[smallest] = temp;\n\n heapify(heap, n, smallest);\n\n }\n\n}\n\n\n\nvoid buildHeap(int heap[], int n) {\n\n int startIdx = (n / 2) - 1;\n\n for (int i = startIdx; i >= 0; i--) {\n\n heapify(heap, n, i);\n\n }\n\n}\n\n\n\n", + "func": "void func0(int heap[], int n, int a, int* outHeap) {\n buildHeap(heap, n);\n if (a < heap[0]) return;\n heap[0] = a;\n heapify(heap, n, 0);\n for (int i = 0; i < n; i++) {\n outHeap[i] = heap[i];\n }\n}", + "test": "int main() {\n\n int testHeap1[] = {25, 44, 68, 21, 39, 23, 89};\n\n int testHeap2[] = {25, 44, 68, 21, 39, 23, 89};\n\n int testHeap3[] = {25, 44, 68, 21, 39, 23, 89};\n\n\n\n int outHeap1[7], outHeap2[7], outHeap3[7];\n\n\n\n func0(testHeap1, 7, 21, outHeap1);\n\n func0(testHeap2, 7, 110, outHeap2);\n\n func0(testHeap3, 7, 500, outHeap3);\n\n\n\n int expectedHeap1[] = {21, 25, 23, 44, 39, 68, 89};\n\n int expectedHeap2[] = {23, 25, 68, 44, 39, 110, 89};\n\n int expectedHeap3[] = {23, 25, 68, 44, 39, 500, 89};\n\n\n\n for (int i = 0; i < 7; i++) {\n\n assert(outHeap1[i] == expectedHeap1[i]);\n\n assert(outHeap2[i] == expectedHeap2[i]);\n\n assert(outHeap3[i] == expectedHeap3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %edx,%r12d\npush %rbp\nmov %rcx,%rbp\npush %rbx\nmov %esi,%ebx\nshr $0x1f,%ebx\nadd %esi,%ebx\nsar %ebx\nsub $0x1,%ebx\njs 14af \nnopl 0x0(%rax)\nmov %ebx,%edx\nsub $0x1,%ebx\ncallq 13c0 \ncmp $0xffffffff,%ebx\njne 14a0 \ncmp %r12d,(%rdi)\njle 14c0 \npop %rbx\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax)\nmov %r12d,(%rdi)\nxor %edx,%edx\ncallq 13c0 \ntest %esi,%esi\njle 14b4 \nlea -0x1(%rsi),%ecx\nxor %eax,%eax\nnopl 0x0(%rax,%rax,1)\nmov (%rdi,%rax,4),%edx\nmov %edx,0x0(%rbp,%rax,4)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rcx,%rdx\njne 14d8 \npop %rbx\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\npush r14\nmov r14d, edx\npush r13\nmov r13, rcx\npush r12\nmov r12, rdi\npush rbp\nmovsxd rbp, esi\npush rbx\nmov ebx, ebp\nshr ebx, 1Fh\nadd ebx, ebp\nsar ebx, 1\nsub ebx, 1\njs short loc_1471\nnop word ptr [rax+rax+00000000h]\nloc_1460:\nmov edx, ebx\nmov esi, ebp\nmov rdi, r12\ncall heapify\nsub ebx, 1\njnb short loc_1460\nloc_1471:\ncmp [r12], r14d\njle short loc_1480\nloc_1477:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1480:\nmov [r12], r14d\nxor edx, edx\nmov esi, ebp\nmov rdi, r12\ncall heapify\ntest ebp, ebp\njle short loc_1477\nshl rbp, 2\nxor eax, eax\nnop word ptr [rax+rax+00h]\nloc_14A0:\nmov edx, [r12+rax]\nmov [r13+rax+0], edx\nadd rax, 4\ncmp rax, rbp\njnz short loc_14A0\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "void __fastcall func0(_DWORD *a1, int a2, int a3, __int64 a4)\n{\n int v6; // ebx\n __int64 i; // rax\n\n v6 = a2 / 2 - 1;\n if ( v6 >= 0 )\n {\n do\n heapify(a1, (unsigned int)a2, (unsigned int)v6);\n while ( v6-- != 0 );\n }\n if ( *a1 <= a3 )\n {\n *a1 = a3;\n heapify(a1, (unsigned int)a2, 0LL);\n if ( a2 > 0 )\n {\n for ( i = 0LL; i != a2; ++i )\n *(_DWORD *)(a4 + i * 4) = a1[i];\n }\n }\n}", + "ida_strip_asm": "sub_1430:\nendbr64\npush r14\nmov r14d, edx\npush r13\nmov r13, rcx\npush r12\nmov r12, rdi\npush rbp\nmovsxd rbp, esi\npush rbx\nmov ebx, ebp\nshr ebx, 1Fh\nadd ebx, ebp\nsar ebx, 1\nsub ebx, 1\njs short loc_1471\nnop word ptr [rax+rax+00000000h]\nloc_1460:\nmov edx, ebx\nmov esi, ebp\nmov rdi, r12\ncall sub_1370\nsub ebx, 1\njnb short loc_1460\nloc_1471:\ncmp [r12], r14d\njle short loc_1480\nloc_1477:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1480:\nmov [r12], r14d\nxor edx, edx\nmov esi, ebp\nmov rdi, r12\ncall sub_1370\ntest ebp, ebp\njle short loc_1477\nshl rbp, 2\nxor eax, eax\nnop word ptr [rax+rax+00h]\nloc_14A0:\nmov edx, [r12+rax]\nmov [r13+rax+0], edx\nadd rax, 4\ncmp rax, rbp\njnz short loc_14A0\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "void __fastcall sub_1430(_DWORD *a1, int a2, int a3, __int64 a4)\n{\n int v6; // ebx\n __int64 i; // rax\n\n v6 = a2 / 2 - 1;\n if ( v6 >= 0 )\n {\n do\n sub_1370(a1, (unsigned int)a2, (unsigned int)v6);\n while ( v6-- != 0 );\n }\n if ( *a1 <= a3 )\n {\n *a1 = a3;\n sub_1370(a1, (unsigned int)a2, 0LL);\n if ( a2 > 0 )\n {\n for ( i = 0LL; i != a2; ++i )\n *(_DWORD *)(a4 + i * 4) = a1[i];\n }\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1430(uint32_t *a1, int a2, int a3, long long a4) {\n int v6;\n long long i;\n v6 = a2 / 2 - 1;\n if (v6 >= 0) {\n do\n sub_1370(a1, (unsigned int)a2, (unsigned int)v6);\n while (v6-- != 0);\n }\n if (*a1 <= a3) {\n *a1 = a3;\n sub_1370(a1, (unsigned int)a2, 0LL);\n if (a2 > 0) {\n for (i = 0LL; i != a2; ++i) *(uint32_t *)(a4 + i * 4) = a1[i];\n }\n }\n}", + "ida_pseudo_norm": "void func0(uint32_t *a1, int a2, int a3, long long a4) {\n int v6;\n long long i;\n v6 = a2 / 2 - 1;\n if (v6 >= 0) {\n do\n heapify(a1, (unsigned int)a2, (unsigned int)v6);\n while (v6-- != 0);\n }\n if (*a1 <= a3) {\n *a1 = a3;\n heapify(a1, (unsigned int)a2, 0LL);\n if (a2 > 0) {\n for (i = 0LL; i != a2; ++i) *(uint32_t *)(a4 + i * 4) = a1[i];\n }\n }\n}" + }, + { + "index": 209, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nvoid heapify(int heap[], int n, int i) {\n\n int smallest = i;\n\n int l = 2 * i + 1;\n\n int r = 2 * i + 2;\n\n\n\n if (l < n && heap[l] < heap[smallest])\n\n smallest = l;\n\n\n\n if (r < n && heap[r] < heap[smallest])\n\n smallest = r;\n\n\n\n if (smallest != i) {\n\n int temp = heap[i];\n\n heap[i] = heap[smallest];\n\n heap[smallest] = temp;\n\n heapify(heap, n, smallest);\n\n }\n\n}\n\n\n\nvoid buildHeap(int heap[], int n) {\n\n int startIdx = (n / 2) - 1;\n\n for (int i = startIdx; i >= 0; i--) {\n\n heapify(heap, n, i);\n\n }\n\n}\n\n\n\n", + "func": "void func0(int heap[], int n, int a, int* outHeap) {\n buildHeap(heap, n);\n if (a < heap[0]) return;\n heap[0] = a;\n heapify(heap, n, 0);\n for (int i = 0; i < n; i++) {\n outHeap[i] = heap[i];\n }\n}", + "test": "int main() {\n\n int testHeap1[] = {25, 44, 68, 21, 39, 23, 89};\n\n int testHeap2[] = {25, 44, 68, 21, 39, 23, 89};\n\n int testHeap3[] = {25, 44, 68, 21, 39, 23, 89};\n\n\n\n int outHeap1[7], outHeap2[7], outHeap3[7];\n\n\n\n func0(testHeap1, 7, 21, outHeap1);\n\n func0(testHeap2, 7, 110, outHeap2);\n\n func0(testHeap3, 7, 500, outHeap3);\n\n\n\n int expectedHeap1[] = {21, 25, 23, 44, 39, 68, 89};\n\n int expectedHeap2[] = {23, 25, 68, 44, 39, 110, 89};\n\n int expectedHeap3[] = {23, 25, 68, 44, 39, 500, 89};\n\n\n\n for (int i = 0; i < 7; i++) {\n\n assert(outHeap1[i] == expectedHeap1[i]);\n\n assert(outHeap2[i] == expectedHeap2[i]);\n\n assert(outHeap3[i] == expectedHeap3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %edx,%r12d\npush %rbp\nmov %rcx,%rbp\npush %rbx\nmov %esi,%ebx\nshr $0x1f,%ebx\nadd %esi,%ebx\nsar %ebx\nsub $0x1,%ebx\njs 14ff \nnopl 0x0(%rax)\nmov %ebx,%edx\nsub $0x1,%ebx\ncallq 1410 \ncmp $0xffffffff,%ebx\njne 14f0 \ncmp %r12d,(%rdi)\njle 1510 \npop %rbx\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax)\nmov %r12d,(%rdi)\nxor %edx,%edx\ncallq 1410 \ntest %esi,%esi\njle 1504 \nlea 0xf(%rdi),%rdx\nlea -0x1(%rsi),%eax\nsub %rbp,%rdx\ncmp $0x1e,%rdx\njbe 158d \ncmp $0x3,%eax\njbe 158d \nmov %esi,%edx\nxor %eax,%eax\nshr $0x2,%edx\nshl $0x4,%rdx\nxchg %ax,%ax\nmovdqu (%rdi,%rax,1),%xmm0\nmovups %xmm0,0x0(%rbp,%rax,1)\nadd $0x10,%rax\ncmp %rdx,%rax\njne 1540 \nmov %esi,%eax\nand $0xfffffffc,%eax\ntest $0x3,%sil\nje 1504 \nmov %eax,%edx\nmov (%rdi,%rdx,4),%ecx\nmov %ecx,0x0(%rbp,%rdx,4)\nlea 0x1(%rax),%edx\ncmp %edx,%esi\njle 1504 \nmovslq %edx,%rdx\nadd $0x2,%eax\nmov (%rdi,%rdx,4),%ecx\nmov %ecx,0x0(%rbp,%rdx,4)\ncmp %eax,%esi\njle 1504 \ncltq\npop %rbx\nmov (%rdi,%rax,4),%edx\nmov %edx,0x0(%rbp,%rax,4)\npop %rbp\npop %r12\nretq\nmov %eax,%edx\nxor %eax,%eax\nnopl 0x0(%rax)\nmov (%rdi,%rax,4),%ecx\nmov %ecx,0x0(%rbp,%rax,4)\nmov %rax,%rcx\nadd $0x1,%rax\ncmp %rdx,%rcx\njne 1598 \njmpq 1504 \n", + "ida_asm": "func0:\nendbr64\npush r14\nmov r14d, edx\npush r13\nmov r13, rcx\npush r12\nmov r12, rdi\npush rbp\nmovsxd rbp, esi\npush rbx\nmov ebx, ebp\nshr ebx, 1Fh\nadd ebx, ebp\nsar ebx, 1\nsub ebx, 1\njs short loc_14C1\nnop word ptr [rax+rax+00000000h]\nloc_14B0:\nmov edx, ebx\nmov esi, ebp\nmov rdi, r12\ncall heapify\nsub ebx, 1\njnb short loc_14B0\nloc_14C1:\ncmp [r12], r14d\njle short loc_14D0\nloc_14C7:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_14D0:\nmov [r12], r14d\nxor edx, edx\nmov esi, ebp\nmov rdi, r12\ncall heapify\ntest ebp, ebp\njle short loc_14C7\nlea eax, [rbp-1]\ncmp eax, 2\njbe short loc_14FD\nlea rdx, [r12+4]\nmov rax, r13\nsub rax, rdx\ncmp rax, 8\nja short loc_1528\nloc_14FD:\nshl rbp, 2\nxor eax, eax\nnop dword ptr [rax+rax+00h]\nloc_1508:\nmov edx, [r12+rax]\nmov [r13+rax+0], edx\nadd rax, 4\ncmp rbp, rax\njnz short loc_1508\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1528:\nmov edx, ebp\nxor eax, eax\nshr edx, 2\nshl rdx, 4\nnop dword ptr [rax+rax+00h]\nloc_1538:\nmovdqu xmm0, xmmword ptr [r12+rax]\nmovups xmmword ptr [r13+rax+0], xmm0\nadd rax, 10h\ncmp rax, rdx\njnz short loc_1538\nmov eax, ebp\nand eax, 0FFFFFFFCh\ntest bpl, 3\njz loc_14C7\nmov ecx, eax\nmov esi, [r12+rcx*4]\nlea rdx, ds:0[rcx*4]\nmov [r13+rcx*4+0], esi\nlea ecx, [rax+1]\ncmp ebp, ecx\njle loc_14C7\nmov ecx, [r12+rdx+4]\nadd eax, 2\nmov [r13+rdx+4], ecx\ncmp ebp, eax\njle loc_14C7\nmov eax, [r12+rdx+8]\nmov [r13+rdx+8], eax\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "void __fastcall func0(_DWORD *a1, int a2, int a3, __int64 a4)\n{\n int v6; // ebx\n __int64 i; // rax\n __int64 v9; // rax\n unsigned int v10; // eax\n __int64 v11; // rdx\n\n v6 = a2 / 2 - 1;\n if ( v6 >= 0 )\n {\n do\n heapify(a1, (unsigned int)a2, (unsigned int)v6);\n while ( v6-- != 0 );\n }\n if ( *a1 <= a3 )\n {\n *a1 = a3;\n heapify(a1, (unsigned int)a2, 0LL);\n if ( a2 > 0 )\n {\n if ( (unsigned int)(a2 - 1) > 2 && (unsigned __int64)(a4 - (_QWORD)(a1 + 1)) > 8 )\n {\n v9 = 0LL;\n do\n {\n *(__m128i *)(a4 + v9 * 4) = _mm_loadu_si128((const __m128i *)&a1[v9]);\n v9 += 4LL;\n }\n while ( v9 != 4LL * ((unsigned int)a2 >> 2) );\n v10 = a2 & 0xFFFFFFFC;\n if ( (a2 & 3) != 0 )\n {\n v11 = v10;\n *(_DWORD *)(a4 + v11 * 4) = a1[v11];\n if ( a2 > (int)(v10 + 1) )\n {\n *(_DWORD *)(a4 + v11 * 4 + 4) = a1[v11 + 1];\n if ( a2 > (int)(v10 + 2) )\n *(_DWORD *)(a4 + v11 * 4 + 8) = a1[v11 + 2];\n }\n }\n }\n else\n {\n for ( i = 0LL; i != a2; ++i )\n *(_DWORD *)(a4 + i * 4) = a1[i];\n }\n }\n }\n}", + "ida_strip_asm": "sub_1480:\nendbr64\npush r14\nmov r14d, edx\npush r13\nmov r13, rcx\npush r12\nmov r12, rdi\npush rbp\nmovsxd rbp, esi\npush rbx\nmov ebx, ebp\nshr ebx, 1Fh\nadd ebx, ebp\nsar ebx, 1\nsub ebx, 1\njs short loc_14C1\nnop word ptr [rax+rax+00000000h]\nloc_14B0:\nmov edx, ebx\nmov esi, ebp\nmov rdi, r12\ncall sub_13A0\nsub ebx, 1\njnb short loc_14B0\nloc_14C1:\ncmp [r12], r14d\njle short loc_14D0\nloc_14C7:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_14D0:\nmov [r12], r14d\nxor edx, edx\nmov esi, ebp\nmov rdi, r12\ncall sub_13A0\ntest ebp, ebp\njle short loc_14C7\nlea eax, [rbp-1]\ncmp eax, 2\njbe short loc_14FD\nlea rdx, [r12+4]\nmov rax, r13\nsub rax, rdx\ncmp rax, 8\nja short loc_1528\nloc_14FD:\nshl rbp, 2\nxor eax, eax\nnop dword ptr [rax+rax+00h]\nloc_1508:\nmov edx, [r12+rax]\nmov [r13+rax+0], edx\nadd rax, 4\ncmp rbp, rax\njnz short loc_1508\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1528:\nmov edx, ebp\nxor eax, eax\nshr edx, 2\nshl rdx, 4\nnop dword ptr [rax+rax+00h]\nloc_1538:\nmovdqu xmm0, xmmword ptr [r12+rax]\nmovups xmmword ptr [r13+rax+0], xmm0\nadd rax, 10h\ncmp rax, rdx\njnz short loc_1538\nmov eax, ebp\nand eax, 0FFFFFFFCh\ntest bpl, 3\njz loc_14C7\nmov ecx, eax\nmov esi, [r12+rcx*4]\nlea rdx, ds:0[rcx*4]\nmov [r13+rcx*4+0], esi\nlea ecx, [rax+1]\ncmp ebp, ecx\njle loc_14C7\nmov ecx, [r12+rdx+4]\nadd eax, 2\nmov [r13+rdx+4], ecx\ncmp ebp, eax\njle loc_14C7\nmov eax, [r12+rdx+8]\nmov [r13+rdx+8], eax\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "void __fastcall sub_1480(_DWORD *a1, int a2, int a3, __int64 a4)\n{\n int v6; // ebx\n __int64 i; // rax\n __int64 v9; // rax\n unsigned int v10; // eax\n __int64 v11; // rdx\n\n v6 = a2 / 2 - 1;\n if ( v6 >= 0 )\n {\n do\n sub_13A0(a1, (unsigned int)a2, (unsigned int)v6);\n while ( v6-- != 0 );\n }\n if ( *a1 <= a3 )\n {\n *a1 = a3;\n sub_13A0(a1, (unsigned int)a2, 0LL);\n if ( a2 > 0 )\n {\n if ( (unsigned int)(a2 - 1) > 2 && (unsigned __int64)(a4 - (_QWORD)(a1 + 1)) > 8 )\n {\n v9 = 0LL;\n do\n {\n *(__m128i *)(a4 + v9 * 4) = _mm_loadu_si128((const __m128i *)&a1[v9]);\n v9 += 4LL;\n }\n while ( v9 != 4LL * ((unsigned int)a2 >> 2) );\n v10 = a2 & 0xFFFFFFFC;\n if ( (a2 & 3) != 0 )\n {\n v11 = v10;\n *(_DWORD *)(a4 + v11 * 4) = a1[v11];\n if ( a2 > (int)(v10 + 1) )\n {\n *(_DWORD *)(a4 + v11 * 4 + 4) = a1[v11 + 1];\n if ( a2 > (int)(v10 + 2) )\n *(_DWORD *)(a4 + v11 * 4 + 8) = a1[v11 + 2];\n }\n }\n }\n else\n {\n for ( i = 0LL; i != a2; ++i )\n *(_DWORD *)(a4 + i * 4) = a1[i];\n }\n }\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1480(uint32_t *a1, int a2, int a3, long long a4) {\n int v6;\n long long i;\n long long v9;\n unsigned int v10;\n long long v11;\n v6 = a2 / 2 - 1;\n if (v6 >= 0) {\n do\n sub_13A0(a1, (unsigned int)a2, (unsigned int)v6);\n while (v6-- != 0);\n }\n if (*a1 <= a3) {\n *a1 = a3;\n sub_13A0(a1, (unsigned int)a2, 0LL);\n if (a2 > 0) {\n if ((unsigned int)(a2 - 1) > 2 &&\n (unsigned long long)(a4 - (uint64_t)(a1 + 1)) > 8) {\n v9 = 0LL;\n do {\n *(__m128i *)(a4 + v9 * 4) = _mm_loadu_si128((const __m128i *)&a1[v9]);\n v9 += 4LL;\n } while (v9 != 4LL * ((unsigned int)a2 >> 2));\n v10 = a2 & 4294967292;\n if ((a2 & 3) != 0) {\n v11 = v10;\n *(uint32_t *)(a4 + v11 * 4) = a1[v11];\n if (a2 > (int)(v10 + 1)) {\n *(uint32_t *)(a4 + v11 * 4 + 4) = a1[v11 + 1];\n if (a2 > (int)(v10 + 2))\n *(uint32_t *)(a4 + v11 * 4 + 8) = a1[v11 + 2];\n }\n }\n } else {\n for (i = 0LL; i != a2; ++i) *(uint32_t *)(a4 + i * 4) = a1[i];\n }\n }\n }\n}", + "ida_pseudo_norm": "void func0(uint32_t *a1, int a2, int a3, long long a4) {\n int v6;\n long long i;\n long long v9;\n unsigned int v10;\n long long v11;\n v6 = a2 / 2 - 1;\n if (v6 >= 0) {\n do\n heapify(a1, (unsigned int)a2, (unsigned int)v6);\n while (v6-- != 0);\n }\n if (*a1 <= a3) {\n *a1 = a3;\n heapify(a1, (unsigned int)a2, 0LL);\n if (a2 > 0) {\n if ((unsigned int)(a2 - 1) > 2 &&\n (unsigned long long)(a4 - (uint64_t)(a1 + 1)) > 8) {\n v9 = 0LL;\n do {\n *(__m128i *)(a4 + v9 * 4) = _mm_loadu_si128((const __m128i *)&a1[v9]);\n v9 += 4LL;\n } while (v9 != 4LL * ((unsigned int)a2 >> 2));\n v10 = a2 & 4294967292;\n if ((a2 & 3) != 0) {\n v11 = v10;\n *(uint32_t *)(a4 + v11 * 4) = a1[v11];\n if (a2 > (int)(v10 + 1)) {\n *(uint32_t *)(a4 + v11 * 4 + 4) = a1[v11 + 1];\n if (a2 > (int)(v10 + 2))\n *(uint32_t *)(a4 + v11 * 4 + 8) = a1[v11 + 2];\n }\n }\n } else {\n for (i = 0LL; i != a2; ++i) *(uint32_t *)(a4 + i * 4) = a1[i];\n }\n }\n }\n}" + }, + { + "index": 210, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char* string) {\n regex_t regex;\n int result;\n regcomp(®ex, \"[^a-zA-Z0-9.]\", REG_EXTENDED);\n result = regexec(®ex, string, 0, NULL, 0);\n regfree(®ex);\n return result == REG_NOMATCH;\n}", + "test": "int main() {\n\n assert(func0(\"ABCDEFabcdef123450\") == true);\n\n assert(func0(\"*&%@#!}{\") == false);\n\n assert(func0(\"HELLOhowareyou98765\") == true);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x70,%rsp\nmov %rdi,-0x68(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea -0x50(%rbp),%rax\nmov $0x1,%edx\nlea 0xe10(%rip),%rsi\nmov %rax,%rdi\ncallq 10c0 \nmov -0x68(%rbp),%rsi\nlea -0x50(%rbp),%rax\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rax,%rdi\ncallq 10d0 \nmov %eax,-0x54(%rbp)\nlea -0x50(%rbp),%rax\nmov %rax,%rdi\ncallq 1090 \ncmpl $0x1,-0x54(%rbp)\nsete %al\nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 124a \ncallq 10a0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nlea rcx, pattern; \"[^a-zA-Z0-9.]\"\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_54], eax\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\ncmp [rbp+var_54], 1\nsetz al\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_124D\ncall ___stack_chk_fail\nlocret_124D:\nleave\nretn", + "ida_pseudo": "bool __fastcall func0(const char *a1)\n{\n int v2; // [rsp+1Ch] [rbp-54h]\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n unsigned __int64 v4; // [rsp+68h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n regcomp(&preg, \"[^a-zA-Z0-9.]\", 1);\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n return v2 == 1;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nlea rcx, pattern; \"[^a-zA-Z0-9.]\"\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_54], eax\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\ncmp [rbp+var_54], 1\nsetz al\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_124D\ncall ___stack_chk_fail\nlocret_124D:\nleave\nretn", + "ida_strip_pseudo": "bool __fastcall sub_11C9(const char *a1)\n{\n int v2; // [rsp+1Ch] [rbp-54h]\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n unsigned __int64 v4; // [rsp+68h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n regcomp(&preg, \"[^a-zA-Z0-9.]\", 1);\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n return v2 == 1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_11C9(const char *a1) {\n int v2;\n regex_t preg;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n regcomp(&preg, \"[^a-zA-Z0-9.]\", 1);\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n return v2 == 1;\n}", + "ida_pseudo_norm": "bool func0(const char *a1) {\n int v2;\n regex_t preg;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n regcomp(&preg, \"[^a-zA-Z0-9.]\", 1);\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n return v2 == 1;\n}" + }, + { + "index": 210, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char* string) {\n regex_t regex;\n int result;\n regcomp(®ex, \"[^a-zA-Z0-9.]\", REG_EXTENDED);\n result = regexec(®ex, string, 0, NULL, 0);\n regfree(®ex);\n return result == REG_NOMATCH;\n}", + "test": "int main() {\n\n assert(func0(\"ABCDEFabcdef123450\") == true);\n\n assert(func0(\"*&%@#!}{\") == false);\n\n assert(func0(\"HELLOhowareyou98765\") == true);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nsub $0x50,%rsp\nmov %rdi,%rbx\nmov $0x28,%r12d\nmov %fs:(%r12),%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%rbp\nmov $0x1,%edx\nlea 0xe0b(%rip),%rsi\nmov %rbp,%rdi\ncallq 10c0 \nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rbx,%rsi\nmov %rbp,%rdi\ncallq 10d0 \nmov %eax,%ebx\nmov %rbp,%rdi\ncallq 1090 \ncmp $0x1,%ebx\nsete %al\nmov 0x48(%rsp),%rcx\nxor %fs:(%r12),%rcx\njne 1241 \nadd $0x50,%rsp\npop %rbx\npop %rbp\npop %r12\nretq\ncallq 10a0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov edx, 1; cflags\nlea rsi, pattern; \"[^a-zA-Z0-9.]\"\nmov rdi, rbp; preg\ncall _regcomp\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov ebx, eax\nmov rdi, rbp; preg\ncall _regfree\ncmp ebx, 1\nsetz al\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_123F\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_123F:\ncall ___stack_chk_fail", + "ida_pseudo": "bool __fastcall func0(char *string)\n{\n int v1; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \"[^a-zA-Z0-9.]\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 1;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov edx, 1; cflags\nlea rsi, pattern; \"[^a-zA-Z0-9.]\"\nmov rdi, rbp; preg\ncall _regcomp\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov ebx, eax\nmov rdi, rbp; preg\ncall _regfree\ncmp ebx, 1\nsetz al\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_123F\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_123F:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "bool __fastcall sub_11C9(char *string)\n{\n int v1; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \"[^a-zA-Z0-9.]\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_11C9(char *string) {\n int v1;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \"[^a-zA-Z0-9.]\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 1;\n}", + "ida_pseudo_norm": "bool func0(char *string) {\n int v1;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \"[^a-zA-Z0-9.]\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 1;\n}" + }, + { + "index": 210, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char* string) {\n regex_t regex;\n int result;\n regcomp(®ex, \"[^a-zA-Z0-9.]\", REG_EXTENDED);\n result = regexec(®ex, string, 0, NULL, 0);\n regfree(®ex);\n return result == REG_NOMATCH;\n}", + "test": "int main() {\n\n assert(func0(\"ABCDEFabcdef123450\") == true);\n\n assert(func0(\"*&%@#!}{\") == false);\n\n assert(func0(\"HELLOhowareyou98765\") == true);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov $0x1,%edx\nmov %rdi,%r12\nlea 0xd7f(%rip),%rsi\npush %rbp\npush %rbx\nsub $0x50,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%rbp\nmov %rbp,%rdi\ncallq 10c0 \nxor %ecx,%ecx\nxor %r8d,%r8d\nxor %edx,%edx\nmov %r12,%rsi\nmov %rbp,%rdi\ncallq 10d0 \nmov %rbp,%rdi\nmov %eax,%ebx\ncallq 1090 \ncmp $0x1,%ebx\nsete %al\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 12e1 \nadd $0x50,%rsp\npop %rbx\npop %rbp\npop %r12\nretq\ncallq 10a0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"[^a-zA-Z0-9.]\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ncmp ebx, 1\nsetz al\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_12DD\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_12DD:\ncall ___stack_chk_fail", + "ida_pseudo": "bool __fastcall func0(char *string)\n{\n int v1; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \"[^a-zA-Z0-9.]\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 1;\n}", + "ida_strip_asm": "sub_1270:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"[^a-zA-Z0-9.]\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ncmp ebx, 1\nsetz al\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_12DD\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_12DD:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "bool __fastcall sub_1270(char *string)\n{\n int v1; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \"[^a-zA-Z0-9.]\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_1270(char *string) {\n int v1;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \"[^a-zA-Z0-9.]\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 1;\n}", + "ida_pseudo_norm": "bool func0(char *string) {\n int v1;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \"[^a-zA-Z0-9.]\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 1;\n}" + }, + { + "index": 210, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char* string) {\n regex_t regex;\n int result;\n regcomp(®ex, \"[^a-zA-Z0-9.]\", REG_EXTENDED);\n result = regexec(®ex, string, 0, NULL, 0);\n regfree(®ex);\n return result == REG_NOMATCH;\n}", + "test": "int main() {\n\n assert(func0(\"ABCDEFabcdef123450\") == true);\n\n assert(func0(\"*&%@#!}{\") == false);\n\n assert(func0(\"HELLOhowareyou98765\") == true);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov $0x1,%edx\nmov %rdi,%r12\nlea 0xd7f(%rip),%rsi\npush %rbp\npush %rbx\nsub $0x50,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%rbp\nmov %rbp,%rdi\ncallq 10c0 \nxor %ecx,%ecx\nxor %r8d,%r8d\nxor %edx,%edx\nmov %r12,%rsi\nmov %rbp,%rdi\ncallq 10d0 \nmov %rbp,%rdi\nmov %eax,%ebx\ncallq 1090 \ncmp $0x1,%ebx\nsete %al\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 12e1 \nadd $0x50,%rsp\npop %rbx\npop %rbp\npop %r12\nretq\ncallq 10a0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"[^a-zA-Z0-9.]\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ncmp ebx, 1\nsetz al\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_12DD\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_12DD:\ncall ___stack_chk_fail", + "ida_pseudo": "bool __fastcall func0(char *string)\n{\n int v1; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \"[^a-zA-Z0-9.]\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 1;\n}", + "ida_strip_asm": "sub_1270:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"[^a-zA-Z0-9.]\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ncmp ebx, 1\nsetz al\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_12DD\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_12DD:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "bool __fastcall sub_1270(char *string)\n{\n int v1; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \"[^a-zA-Z0-9.]\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_1270(char *string) {\n int v1;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \"[^a-zA-Z0-9.]\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 1;\n}", + "ida_pseudo_norm": "bool func0(char *string) {\n int v1;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \"[^a-zA-Z0-9.]\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 1;\n}" + }, + { + "index": 211, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n == 1) {\n return 1;\n }\n int count = pow(2, n - 2);\n return count;\n}", + "test": "int main() {\n\n assert(func0(2) == 1);\n\n assert(func0(3) == 2);\n\n assert(func0(1) == 1);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %edi,-0x14(%rbp)\ncmpl $0x1,-0x14(%rbp)\njne 1185 \nmov $0x1,%eax\njmp 11ae \nmov -0x14(%rbp),%eax\nsub $0x2,%eax\ncvtsi2sd %eax,%xmm0\nmov 0xee2(%rip),%rax\nmovapd %xmm0,%xmm1\nmovq %rax,%xmm0\ncallq 1060 \ncvttsd2si %xmm0,%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\ncmp [rbp+var_14], 1\njnz short loc_1185\nmov eax, 1\njmp short locret_11B2\nloc_1185:\nmov eax, [rbp+var_14]\nsub eax, 2\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmov rax, cs:x\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\ncvttsd2si eax, xmm0\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\nlocret_11B2:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n if ( a1 == 1 )\n return 1LL;\n else\n return (unsigned int)(int)pow(2.0, (double)(a1 - 2));\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\ncmp [rbp+var_14], 1\njnz short loc_1185\nmov eax, 1\njmp short locret_11B2\nloc_1185:\nmov eax, [rbp+var_14]\nsub eax, 2\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmov rax, cs:x\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\ncvttsd2si eax, xmm0\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\nlocret_11B2:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n if ( a1 == 1 )\n return 1LL;\n else\n return (unsigned int)(int)pow(2.0, (double)(a1 - 2));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n if (a1 == 1)\n return 1LL;\n else\n return (unsigned int)(int)pow(2.0, (double)(a1 - 2));\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n if (a1 == 1)\n return 1LL;\n else\n return (unsigned int)(int)pow(2.0, (double)(a1 - 2));\n}" + }, + { + "index": 211, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n == 1) {\n return 1;\n }\n int count = pow(2, n - 2);\n return count;\n}", + "test": "int main() {\n\n assert(func0(2) == 1);\n\n assert(func0(3) == 2);\n\n assert(func0(1) == 1);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %edi,%eax\ncmp $0x1,%edi\nje 1199 \nsub $0x8,%rsp\nsub $0x2,%edi\npxor %xmm1,%xmm1\ncvtsi2sd %edi,%xmm1\nmovsd 0xeed(%rip),%xmm0\ncallq 1060 \ncvttsd2si %xmm0,%eax\nadd $0x8,%rsp\nretq\nretq\n", + "ida_asm": "func0:\nendbr64\nmov eax, edi\ncmp edi, 1\njz short locret_1199\nsub rsp, 8\nsub edi, 2\npxor xmm1, xmm1\ncvtsi2sd xmm1, edi; y\nmovsd xmm0, cs:x; x\ncall _pow\ncvttsd2si eax, xmm0\nadd rsp, 8\nretn\nlocret_1199:\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1)\n{\n __int64 result; // rax\n\n result = a1;\n if ( a1 != 1 )\n return (unsigned int)(int)pow(2.0, (double)(int)(a1 - 2));\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov eax, edi\ncmp edi, 1\njz short locret_1199\nsub rsp, 8\nsub edi, 2\npxor xmm1, xmm1\ncvtsi2sd xmm1, edi; y\nmovsd xmm0, cs:x; x\ncall _pow\ncvttsd2si eax, xmm0\nadd rsp, 8\nretn\nlocret_1199:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(unsigned int a1)\n{\n __int64 result; // rax\n\n result = a1;\n if ( a1 != 1 )\n return (unsigned int)(int)pow(2.0, (double)(int)(a1 - 2));\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(unsigned int a1) {\n long long result;\n result = a1;\n if (a1 != 1) return (unsigned int)(int)pow(2.0, (double)(int)(a1 - 2));\n return result;\n}", + "ida_pseudo_norm": "long long func0(unsigned int a1) {\n long long result;\n result = a1;\n if (a1 != 1) return (unsigned int)(int)pow(2.0, (double)(int)(a1 - 2));\n return result;\n}" + }, + { + "index": 212, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int n) {\n int sum = 0;\n for (int i = 1; i <= n; i++) {\n sum += i * i * i * i;\n }\n return sum;\n}", + "test": "int main() {\n\n assert(func0(2) == 17);\n\n assert(func0(4) == 354);\n\n assert(func0(6) == 2275);\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x1,-0x4(%rbp)\njmp 1179 \nmov -0x4(%rbp),%eax\nimul %eax,%eax\nimul -0x4(%rbp),%eax\nimul -0x4(%rbp),%eax\nadd %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x14(%rbp),%eax\njle 1164 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 1\njmp short loc_1179\nloc_1164:\nmov eax, [rbp+var_4]\nimul eax, eax\nimul eax, [rbp+var_4]\nimul eax, [rbp+var_4]\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_1179:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_14]\njle short loc_1164\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v2; // [rsp+Ch] [rbp-8h]\n int i; // [rsp+10h] [rbp-4h]\n\n v2 = 0;\n for ( i = 1; i <= a1; ++i )\n v2 += i * i * i * i;\n return v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 1\njmp short loc_1179\nloc_1164:\nmov eax, [rbp+var_4]\nimul eax, eax\nimul eax, [rbp+var_4]\nimul eax, [rbp+var_4]\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_1179:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_14]\njle short loc_1164\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n unsigned int v2; // [rsp+Ch] [rbp-8h]\n int i; // [rsp+10h] [rbp-4h]\n\n v2 = 0;\n for ( i = 1; i <= a1; ++i )\n v2 += i * i * i * i;\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n unsigned int v2;\n int i;\n v2 = 0;\n for (i = 1; i <= a1; ++i) v2 += i * i * i * i;\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v2;\n int i;\n v2 = 0;\n for (i = 1; i <= a1; ++i) v2 += i * i * i * i;\n return v2;\n}" + }, + { + "index": 212, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int n) {\n int sum = 0;\n for (int i = 1; i <= n; i++) {\n sum += i * i * i * i;\n }\n return sum;\n}", + "test": "int main() {\n\n assert(func0(2) == 17);\n\n assert(func0(4) == 354);\n\n assert(func0(6) == 2275);\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\njle 1172 \nadd $0x1,%edi\nmov $0x1,%eax\nmov $0x0,%ecx\nmov %eax,%edx\nimul %eax,%edx\nimul %edx,%edx\nadd %edx,%ecx\nadd $0x1,%eax\ncmp %edi,%eax\njne 115e \nmov %ecx,%eax\nretq\nmov $0x0,%ecx\njmp 116f \n", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njle short loc_1172\nadd edi, 1\nmov eax, 1\nmov ecx, 0\nloc_115E:\nmov edx, eax\nimul edx, eax\nimul edx, edx\nadd ecx, edx\nadd eax, 1\ncmp eax, edi\njnz short loc_115E\nloc_116F:\nmov eax, ecx\nretn\nloc_1172:\nmov ecx, 0\njmp short loc_116F", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // edi\n int v2; // eax\n unsigned int v3; // ecx\n\n if ( a1 <= 0 )\n {\n return 0;\n }\n else\n {\n v1 = a1 + 1;\n v2 = 1;\n v3 = 0;\n do\n {\n v3 += v2 * v2 * v2 * v2;\n ++v2;\n }\n while ( v2 != v1 );\n }\n return v3;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ntest edi, edi\njle short loc_1172\nadd edi, 1\nmov eax, 1\nmov ecx, 0\nloc_115E:\nmov edx, eax\nimul edx, eax\nimul edx, edx\nadd ecx, edx\nadd eax, 1\ncmp eax, edi\njnz short loc_115E\nloc_116F:\nmov eax, ecx\nretn\nloc_1172:\nmov ecx, 0\njmp short loc_116F", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v1; // edi\n int v2; // eax\n unsigned int v3; // ecx\n\n if ( a1 <= 0 )\n {\n return 0;\n }\n else\n {\n v1 = a1 + 1;\n v2 = 1;\n v3 = 0;\n do\n {\n v3 += v2 * v2 * v2 * v2;\n ++v2;\n }\n while ( v2 != v1 );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v1;\n int v2;\n unsigned int v3;\n if (a1 <= 0) {\n return 0;\n } else {\n v1 = a1 + 1;\n v2 = 1;\n v3 = 0;\n do {\n v3 += v2 * v2 * v2 * v2;\n ++v2;\n } while (v2 != v1);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v2;\n unsigned int v3;\n if (a1 <= 0) {\n return 0;\n } else {\n v1 = a1 + 1;\n v2 = 1;\n v3 = 0;\n do {\n v3 += v2 * v2 * v2 * v2;\n ++v2;\n } while (v2 != v1);\n }\n return v3;\n}" + }, + { + "index": 213, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(const char* test_tup1[], const char* test_tup2[], char* res[],\n int size) {\n for (int i = 0; i < size; i++) {\n strcpy(res[i], test_tup1[i]);\n strcat(res[i], test_tup2[i]);\n }\n}", + "test": "int main() {\n\n // Declare variables\n\n const char* test_tup1_1[] = {\"Manjeet\", \"Nikhil\", \"Akshat\"};\n\n const char* test_tup1_2[] = {\" Singh\", \" Meherwal\", \" Garg\"};\n\n char* res1[3];\n\n char res1_0[20], res1_1[20], res1_2[20];\n\n res1[0] = res1_0; res1[1] = res1_1; res1[2] = res1_2;\n\n \n\n const char* test_tup2_1[] = {\"Shaik\", \"Ayesha\", \"Sanya\"};\n\n const char* test_tup2_2[] = {\" Dawood\", \" Begum\", \" Singh\"};\n\n char* res2[3];\n\n char res2_0[20], res2_1[20], res2_2[20];\n\n res2[0] = res2_0; res2[1] = res2_1; res2[2] = res2_2;\n\n \n\n const char* test_tup3_1[] = {\"Harpreet\", \"Priyanka\", \"Muskan\"};\n\n const char* test_tup3_2[] = {\"Kour\", \" Agarwal\", \"Sethi\"};\n\n char* res3[3];\n\n char res3_0[20], res3_1[20], res3_2[20];\n\n res3[0] = res3_0; res3[1] = res3_1; res3[2] = res3_2;\n\n\n\n // Call the function\n\n func0(test_tup1_1, test_tup1_2, res1, 3);\n\n func0(test_tup2_1, test_tup2_2, res2, 3);\n\n func0(test_tup3_1, test_tup3_2, res3, 3);\n\n \n\n // Assertions\n\n assert(strcmp(res1[0], \"Manjeet Singh\") == 0);\n\n assert(strcmp(res1[1], \"Nikhil Meherwal\") == 0);\n\n assert(strcmp(res1[2], \"Akshat Garg\") == 0);\n\n \n\n assert(strcmp(res2[0], \"Shaik Dawood\") == 0);\n\n assert(strcmp(res2[1], \"Ayesha Begum\") == 0);\n\n assert(strcmp(res2[2], \"Sanya Singh\") == 0);\n\n \n\n assert(strcmp(res3[0], \"HarpreetKour\") == 0);\n\n assert(strcmp(res3[1], \"Priyanka Agarwal\") == 0);\n\n assert(strcmp(res3[2], \"MuskanSethi\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %ecx,-0x2c(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 1263 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rdx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1090 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rdx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10d0 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 11ed \nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_28], rdx\nmov [rbp+var_2C], ecx\nmov [rbp+var_4], 0\njmp short loc_1263\nloc_11ED:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\nadd [rbp+var_4], 1\nloc_1263:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_2C]\njl short loc_11ED\nnop\nnop\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+2Ch] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a4 )\n break;\n strcpy(*(char **)(8LL * (int)i + a3), *(const char **)(8LL * (int)i + a1));\n strcat(*(char **)(8LL * (int)i + a3), *(const char **)(8LL * (int)i + a2));\n }\n return result;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_28], rdx\nmov [rbp+var_2C], ecx\nmov [rbp+var_4], 0\njmp short loc_1263\nloc_11ED:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\nadd [rbp+var_4], 1\nloc_1263:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_2C]\njl short loc_11ED\nnop\nnop\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11C9(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+2Ch] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a4 )\n break;\n strcpy(*(char **)(8LL * (int)i + a3), *(const char **)(8LL * (int)i + a1));\n strcat(*(char **)(8LL * (int)i + a3), *(const char **)(8LL * (int)i + a2));\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11C9(long long a1, long long a2, long long a3, int a4) {\n long long result;\n unsigned int i;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a4) break;\n strcpy(*(char **)(8LL * (int)i + a3), *(const char **)(8LL * (int)i + a1));\n strcat(*(char **)(8LL * (int)i + a3), *(const char **)(8LL * (int)i + a2));\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, long long a3, int a4) {\n long long result;\n unsigned int i;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a4) break;\n strcpy(*(char **)(8LL * (int)i + a3), *(const char **)(8LL * (int)i + a1));\n strcat(*(char **)(8LL * (int)i + a3), *(const char **)(8LL * (int)i + a2));\n }\n return result;\n}" + }, + { + "index": 213, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(const char* test_tup1[], const char* test_tup2[], char* res[],\n int size) {\n for (int i = 0; i < size; i++) {\n strcpy(res[i], test_tup1[i]);\n strcat(res[i], test_tup2[i]);\n }\n}", + "test": "int main() {\n\n // Declare variables\n\n const char* test_tup1_1[] = {\"Manjeet\", \"Nikhil\", \"Akshat\"};\n\n const char* test_tup1_2[] = {\" Singh\", \" Meherwal\", \" Garg\"};\n\n char* res1[3];\n\n char res1_0[20], res1_1[20], res1_2[20];\n\n res1[0] = res1_0; res1[1] = res1_1; res1[2] = res1_2;\n\n \n\n const char* test_tup2_1[] = {\"Shaik\", \"Ayesha\", \"Sanya\"};\n\n const char* test_tup2_2[] = {\" Dawood\", \" Begum\", \" Singh\"};\n\n char* res2[3];\n\n char res2_0[20], res2_1[20], res2_2[20];\n\n res2[0] = res2_0; res2[1] = res2_1; res2[2] = res2_2;\n\n \n\n const char* test_tup3_1[] = {\"Harpreet\", \"Priyanka\", \"Muskan\"};\n\n const char* test_tup3_2[] = {\"Kour\", \" Agarwal\", \"Sethi\"};\n\n char* res3[3];\n\n char res3_0[20], res3_1[20], res3_2[20];\n\n res3[0] = res3_0; res3[1] = res3_1; res3[2] = res3_2;\n\n\n\n // Call the function\n\n func0(test_tup1_1, test_tup1_2, res1, 3);\n\n func0(test_tup2_1, test_tup2_2, res2, 3);\n\n func0(test_tup3_1, test_tup3_2, res3, 3);\n\n \n\n // Assertions\n\n assert(strcmp(res1[0], \"Manjeet Singh\") == 0);\n\n assert(strcmp(res1[1], \"Nikhil Meherwal\") == 0);\n\n assert(strcmp(res1[2], \"Akshat Garg\") == 0);\n\n \n\n assert(strcmp(res2[0], \"Shaik Dawood\") == 0);\n\n assert(strcmp(res2[1], \"Ayesha Begum\") == 0);\n\n assert(strcmp(res2[2], \"Sanya Singh\") == 0);\n\n \n\n assert(strcmp(res3[0], \"HarpreetKour\") == 0);\n\n assert(strcmp(res3[1], \"Priyanka Agarwal\") == 0);\n\n assert(strcmp(res3[2], \"MuskanSethi\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %ecx,%ecx\njle 11fd \npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%r12\nmov %rsi,%r13\nmov %rdx,%rbp\nlea -0x1(%rcx),%r14d\nmov $0x0,%ebx\nmov (%r12,%rbx,8),%rsi\nmov 0x0(%rbp,%rbx,8),%rdi\ncallq 1080 \nmov 0x0(%r13,%rbx,8),%rsi\nmov 0x0(%rbp,%rbx,8),%rdi\ncallq 10b0 \nmov %rbx,%rax\nadd $0x1,%rbx\ncmp %r14,%rax\njne 11cb \npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nretq\n", + "ida_asm": "func0:\nendbr64\ntest ecx, ecx\njle short locret_1221\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r13, rdi\nmov r14, rsi\nmov rbp, rdx\nmovsxd rcx, ecx\nlea r12, ds:0[rcx*8]\nmov ebx, 0\nloc_11F2:\nmov rsi, [r13+rbx+0]; src\nmov rdi, [rbp+rbx+0]; dest\ncall _strcpy\nmov rsi, [r14+rbx]; src\nmov rdi, [rbp+rbx+0]; dest\ncall _strcat\nadd rbx, 8\ncmp rbx, r12\njnz short loc_11F2\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nlocret_1221:\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 v5; // r12\n __int64 v6; // rbx\n char *result; // rax\n\n if ( a4 > 0 )\n {\n v5 = 8LL * a4;\n v6 = 0LL;\n do\n {\n strcpy(*(char **)(a3 + v6), *(const char **)(a1 + v6));\n result = strcat(*(char **)(a3 + v6), *(const char **)(a2 + v6));\n v6 += 8LL;\n }\n while ( v6 != v5 );\n }\n return result;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\ntest ecx, ecx\njle short locret_1221\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r13, rdi\nmov r14, rsi\nmov rbp, rdx\nmovsxd rcx, ecx\nlea r12, ds:0[rcx*8]\nmov ebx, 0\nloc_11F2:\nmov rsi, [r13+rbx+0]; src\nmov rdi, [rbp+rbx+0]; dest\ncall _strcpy\nmov rsi, [r14+rbx]; src\nmov rdi, [rbp+rbx+0]; dest\ncall _strcat\nadd rbx, 8\ncmp rbx, r12\njnz short loc_11F2\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nlocret_1221:\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11C9(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 v5; // r12\n __int64 v6; // rbx\n char *result; // rax\n\n if ( a4 > 0 )\n {\n v5 = 8LL * a4;\n v6 = 0LL;\n do\n {\n strcpy(*(char **)(a3 + v6), *(const char **)(a1 + v6));\n result = strcat(*(char **)(a3 + v6), *(const char **)(a2 + v6));\n v6 += 8LL;\n }\n while ( v6 != v5 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11C9(long long a1, long long a2, long long a3, int a4) {\n long long v5;\n long long v6;\n char *result;\n if (a4 > 0) {\n v5 = 8LL * a4;\n v6 = 0LL;\n do {\n strcpy(*(char **)(a3 + v6), *(const char **)(a1 + v6));\n result = strcat(*(char **)(a3 + v6), *(const char **)(a2 + v6));\n v6 += 8LL;\n } while (v6 != v5);\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(long long a1, long long a2, long long a3, int a4) {\n long long v5;\n long long v6;\n char *result;\n if (a4 > 0) {\n v5 = 8LL * a4;\n v6 = 0LL;\n do {\n strcpy(*(char **)(a3 + v6), *(const char **)(a1 + v6));\n result = strcat(*(char **)(a3 + v6), *(const char **)(a2 + v6));\n v6 += 8LL;\n } while (v6 != v5);\n }\n return result;\n}" + }, + { + "index": 213, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(const char* test_tup1[], const char* test_tup2[], char* res[],\n int size) {\n for (int i = 0; i < size; i++) {\n strcpy(res[i], test_tup1[i]);\n strcat(res[i], test_tup2[i]);\n }\n}", + "test": "int main() {\n\n // Declare variables\n\n const char* test_tup1_1[] = {\"Manjeet\", \"Nikhil\", \"Akshat\"};\n\n const char* test_tup1_2[] = {\" Singh\", \" Meherwal\", \" Garg\"};\n\n char* res1[3];\n\n char res1_0[20], res1_1[20], res1_2[20];\n\n res1[0] = res1_0; res1[1] = res1_1; res1[2] = res1_2;\n\n \n\n const char* test_tup2_1[] = {\"Shaik\", \"Ayesha\", \"Sanya\"};\n\n const char* test_tup2_2[] = {\" Dawood\", \" Begum\", \" Singh\"};\n\n char* res2[3];\n\n char res2_0[20], res2_1[20], res2_2[20];\n\n res2[0] = res2_0; res2[1] = res2_1; res2[2] = res2_2;\n\n \n\n const char* test_tup3_1[] = {\"Harpreet\", \"Priyanka\", \"Muskan\"};\n\n const char* test_tup3_2[] = {\"Kour\", \" Agarwal\", \"Sethi\"};\n\n char* res3[3];\n\n char res3_0[20], res3_1[20], res3_2[20];\n\n res3[0] = res3_0; res3[1] = res3_1; res3[2] = res3_2;\n\n\n\n // Call the function\n\n func0(test_tup1_1, test_tup1_2, res1, 3);\n\n func0(test_tup2_1, test_tup2_2, res2, 3);\n\n func0(test_tup3_1, test_tup3_2, res3, 3);\n\n \n\n // Assertions\n\n assert(strcmp(res1[0], \"Manjeet Singh\") == 0);\n\n assert(strcmp(res1[1], \"Nikhil Meherwal\") == 0);\n\n assert(strcmp(res1[2], \"Akshat Garg\") == 0);\n\n \n\n assert(strcmp(res2[0], \"Shaik Dawood\") == 0);\n\n assert(strcmp(res2[1], \"Ayesha Begum\") == 0);\n\n assert(strcmp(res2[2], \"Sanya Singh\") == 0);\n\n \n\n assert(strcmp(res3[0], \"HarpreetKour\") == 0);\n\n assert(strcmp(res3[1], \"Priyanka Agarwal\") == 0);\n\n assert(strcmp(res3[2], \"MuskanSethi\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %ecx,%ecx\njle 1658 \npush %r14\nmov %rdi,%r14\npush %r13\nlea -0x1(%rcx),%r13d\npush %r12\nmov %rsi,%r12\npush %rbp\nmov %rdx,%rbp\npush %rbx\nxor %ebx,%ebx\nmov (%r14,%rbx,8),%rsi\nmov 0x0(%rbp,%rbx,8),%rdi\ncallq 1080 \nmov (%r12,%rbx,8),%rsi\nmov 0x0(%rbp,%rbx,8),%rdi\ncallq 10b0 \nmov %rbx,%rax\nadd $0x1,%rbx\ncmp %rax,%r13\njne 1620 \npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopl 0x0(%rax)\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\ntest ecx, ecx\njle short locret_16D0\nmovsxd rcx, ecx\npush r14\nmov r14, rdi\npush r13\nmov r13, rsi\npush r12\nlea r12, ds:0[rcx*8]\npush rbp\nmov rbp, rdx\npush rbx\nxor ebx, ebx\nnop word ptr [rax+rax+00000000h]\nloc_16A0:\nmov rsi, [r14+rbx]; src\nmov rdi, [rbp+rbx+0]; dest\ncall _strcpy\nmov rsi, [r13+rbx+0]; src\nmov rdi, [rbp+rbx+0]; dest\nadd rbx, 8\ncall _strcat\ncmp r12, rbx\njnz short loc_16A0\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nlocret_16D0:\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 v6; // r12\n __int64 v8; // rbx\n const char *v9; // rsi\n char *v10; // rdi\n char *result; // rax\n\n if ( a4 > 0 )\n {\n v6 = 8LL * a4;\n v8 = 0LL;\n do\n {\n strcpy(*(char **)(a3 + v8), *(const char **)(a1 + v8));\n v9 = *(const char **)(a2 + v8);\n v10 = *(char **)(a3 + v8);\n v8 += 8LL;\n result = strcat(v10, v9);\n }\n while ( v6 != v8 );\n }\n return result;\n}", + "ida_strip_asm": "sub_1670:\nendbr64\ntest ecx, ecx\njle short locret_16D0\nmovsxd rcx, ecx\npush r14\nmov r14, rdi\npush r13\nmov r13, rsi\npush r12\nlea r12, ds:0[rcx*8]\npush rbp\nmov rbp, rdx\npush rbx\nxor ebx, ebx\nnop word ptr [rax+rax+00000000h]\nloc_16A0:\nmov rsi, [r14+rbx]; src\nmov rdi, [rbp+rbx+0]; dest\ncall _strcpy\nmov rsi, [r13+rbx+0]; src\nmov rdi, [rbp+rbx+0]; dest\nadd rbx, 8\ncall _strcat\ncmp r12, rbx\njnz short loc_16A0\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nlocret_16D0:\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1670(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 v6; // r12\n __int64 v8; // rbx\n const char *v9; // rsi\n char *v10; // rdi\n char *result; // rax\n\n if ( a4 > 0 )\n {\n v6 = 8LL * a4;\n v8 = 0LL;\n do\n {\n strcpy(*(char **)(a3 + v8), *(const char **)(a1 + v8));\n v9 = *(const char **)(a2 + v8);\n v10 = *(char **)(a3 + v8);\n v8 += 8LL;\n result = strcat(v10, v9);\n }\n while ( v6 != v8 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1670(long long a1, long long a2, long long a3, int a4) {\n long long v6;\n long long v8;\n const char *v9;\n char *v10;\n char *result;\n if (a4 > 0) {\n v6 = 8LL * a4;\n v8 = 0LL;\n do {\n strcpy(*(char **)(a3 + v8), *(const char **)(a1 + v8));\n v9 = *(const char **)(a2 + v8);\n v10 = *(char **)(a3 + v8);\n v8 += 8LL;\n result = strcat(v10, v9);\n } while (v6 != v8);\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(long long a1, long long a2, long long a3, int a4) {\n long long v6;\n long long v8;\n const char *v9;\n char *v10;\n char *result;\n if (a4 > 0) {\n v6 = 8LL * a4;\n v8 = 0LL;\n do {\n strcpy(*(char **)(a3 + v8), *(const char **)(a1 + v8));\n v9 = *(const char **)(a2 + v8);\n v10 = *(char **)(a3 + v8);\n v8 += 8LL;\n result = strcat(v10, v9);\n } while (v6 != v8);\n }\n return result;\n}" + }, + { + "index": 213, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(const char* test_tup1[], const char* test_tup2[], char* res[],\n int size) {\n for (int i = 0; i < size; i++) {\n strcpy(res[i], test_tup1[i]);\n strcat(res[i], test_tup2[i]);\n }\n}", + "test": "int main() {\n\n // Declare variables\n\n const char* test_tup1_1[] = {\"Manjeet\", \"Nikhil\", \"Akshat\"};\n\n const char* test_tup1_2[] = {\" Singh\", \" Meherwal\", \" Garg\"};\n\n char* res1[3];\n\n char res1_0[20], res1_1[20], res1_2[20];\n\n res1[0] = res1_0; res1[1] = res1_1; res1[2] = res1_2;\n\n \n\n const char* test_tup2_1[] = {\"Shaik\", \"Ayesha\", \"Sanya\"};\n\n const char* test_tup2_2[] = {\" Dawood\", \" Begum\", \" Singh\"};\n\n char* res2[3];\n\n char res2_0[20], res2_1[20], res2_2[20];\n\n res2[0] = res2_0; res2[1] = res2_1; res2[2] = res2_2;\n\n \n\n const char* test_tup3_1[] = {\"Harpreet\", \"Priyanka\", \"Muskan\"};\n\n const char* test_tup3_2[] = {\"Kour\", \" Agarwal\", \"Sethi\"};\n\n char* res3[3];\n\n char res3_0[20], res3_1[20], res3_2[20];\n\n res3[0] = res3_0; res3[1] = res3_1; res3[2] = res3_2;\n\n\n\n // Call the function\n\n func0(test_tup1_1, test_tup1_2, res1, 3);\n\n func0(test_tup2_1, test_tup2_2, res2, 3);\n\n func0(test_tup3_1, test_tup3_2, res3, 3);\n\n \n\n // Assertions\n\n assert(strcmp(res1[0], \"Manjeet Singh\") == 0);\n\n assert(strcmp(res1[1], \"Nikhil Meherwal\") == 0);\n\n assert(strcmp(res1[2], \"Akshat Garg\") == 0);\n\n \n\n assert(strcmp(res2[0], \"Shaik Dawood\") == 0);\n\n assert(strcmp(res2[1], \"Ayesha Begum\") == 0);\n\n assert(strcmp(res2[2], \"Sanya Singh\") == 0);\n\n \n\n assert(strcmp(res3[0], \"HarpreetKour\") == 0);\n\n assert(strcmp(res3[1], \"Priyanka Agarwal\") == 0);\n\n assert(strcmp(res3[2], \"MuskanSethi\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ntest %ecx,%ecx\njle 1698 \npush %r14\nmov %rdi,%r14\npush %r13\nlea -0x1(%rcx),%r13d\npush %r12\nmov %rsi,%r12\npush %rbp\nmov %rdx,%rbp\npush %rbx\nxor %ebx,%ebx\nmov (%r14,%rbx,8),%rsi\nmov 0x0(%rbp,%rbx,8),%rdi\ncallq 1080 \nmov (%r12,%rbx,8),%rsi\nmov 0x0(%rbp,%rbx,8),%rdi\ncallq 10b0 \nmov %rbx,%rax\nadd $0x1,%rbx\ncmp %rax,%r13\njne 1660 \npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopl 0x0(%rax)\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\ntest ecx, ecx\njle short locret_16D0\nmovsxd rcx, ecx\npush r14\nmov r14, rdi\npush r13\nmov r13, rsi\npush r12\nlea r12, ds:0[rcx*8]\npush rbp\nmov rbp, rdx\npush rbx\nxor ebx, ebx\nnop word ptr [rax+rax+00000000h]\nloc_16A0:\nmov rsi, [r14+rbx]; src\nmov rdi, [rbp+rbx+0]; dest\ncall _strcpy\nmov rsi, [r13+rbx+0]; src\nmov rdi, [rbp+rbx+0]; dest\nadd rbx, 8\ncall _strcat\ncmp r12, rbx\njnz short loc_16A0\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nlocret_16D0:\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 v6; // r12\n __int64 v8; // rbx\n const char *v9; // rsi\n char *v10; // rdi\n char *result; // rax\n\n if ( a4 > 0 )\n {\n v6 = 8LL * a4;\n v8 = 0LL;\n do\n {\n strcpy(*(char **)(a3 + v8), *(const char **)(a1 + v8));\n v9 = *(const char **)(a2 + v8);\n v10 = *(char **)(a3 + v8);\n v8 += 8LL;\n result = strcat(v10, v9);\n }\n while ( v6 != v8 );\n }\n return result;\n}", + "ida_strip_asm": "sub_1670:\nendbr64\ntest ecx, ecx\njle short locret_16D0\nmovsxd rcx, ecx\npush r14\nmov r14, rdi\npush r13\nmov r13, rsi\npush r12\nlea r12, ds:0[rcx*8]\npush rbp\nmov rbp, rdx\npush rbx\nxor ebx, ebx\nnop word ptr [rax+rax+00000000h]\nloc_16A0:\nmov rsi, [r14+rbx]; src\nmov rdi, [rbp+rbx+0]; dest\ncall _strcpy\nmov rsi, [r13+rbx+0]; src\nmov rdi, [rbp+rbx+0]; dest\nadd rbx, 8\ncall _strcat\ncmp r12, rbx\njnz short loc_16A0\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nlocret_16D0:\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1670(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 v6; // r12\n __int64 v8; // rbx\n const char *v9; // rsi\n char *v10; // rdi\n char *result; // rax\n\n if ( a4 > 0 )\n {\n v6 = 8LL * a4;\n v8 = 0LL;\n do\n {\n strcpy(*(char **)(a3 + v8), *(const char **)(a1 + v8));\n v9 = *(const char **)(a2 + v8);\n v10 = *(char **)(a3 + v8);\n v8 += 8LL;\n result = strcat(v10, v9);\n }\n while ( v6 != v8 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1670(long long a1, long long a2, long long a3, int a4) {\n long long v6;\n long long v8;\n const char *v9;\n char *v10;\n char *result;\n if (a4 > 0) {\n v6 = 8LL * a4;\n v8 = 0LL;\n do {\n strcpy(*(char **)(a3 + v8), *(const char **)(a1 + v8));\n v9 = *(const char **)(a2 + v8);\n v10 = *(char **)(a3 + v8);\n v8 += 8LL;\n result = strcat(v10, v9);\n } while (v6 != v8);\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(long long a1, long long a2, long long a3, int a4) {\n long long v6;\n long long v8;\n const char *v9;\n char *v10;\n char *result;\n if (a4 > 0) {\n v6 = 8LL * a4;\n v8 = 0LL;\n do {\n strcpy(*(char **)(a3 + v8), *(const char **)(a1 + v8));\n v9 = *(const char **)(a2 + v8);\n v10 = *(char **)(a3 + v8);\n v8 += 8LL;\n result = strcat(v10, v9);\n } while (v6 != v8);\n }\n return result;\n}" + }, + { + "index": 214, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "double func0(double radian) {\n double degree = radian * (180 / M_PI);\n return degree;\n}", + "test": "int main() {\n\n assert(func0(90) == 5156.620156177409);\n\n assert(func0(60) == 3437.746770784939);\n\n assert(func0(120) == 6875.493541569878);\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmovsd %xmm0,-0x18(%rbp)\nmovsd -0x18(%rbp),%xmm1\nmovsd 0xf4d(%rip),%xmm0\nmulsd %xmm1,%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmovsd -0x8(%rbp),%xmm0\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmovsd [rbp+var_18], xmm0\nmovsd xmm1, [rbp+var_18]\nmovsd xmm0, cs:qword_2090\nmulsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "double __fastcall func0(double a1)\n{\n return 57.29577951308232 * a1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmovsd [rbp+var_18], xmm0\nmovsd xmm1, [rbp+var_18]\nmovsd xmm0, cs:qword_2090\nmulsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "double __fastcall sub_1149(double a1)\n{\n return 57.29577951308232 * a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1149(double a1) { return 57.29577951308232 * a1; }", + "ida_pseudo_norm": "double func0(double a1) { return 57.29577951308232 * a1; }" + }, + { + "index": 215, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int is_list;\n\n union {\n\n int single;\n\n struct {\n\n int count;\n\n int value;\n\n } list;\n\n } data;\n\n} Element;\n\n\n\ntypedef struct {\n\n int *array;\n\n int size;\n\n} DecodedList;\n\n\n\nDecodedList decode_list(Element *alist, int alist_size) {\n\n // Estimate maximum possible size\n\n int max_size = 0;\n\n for(int i = 0; i < alist_size; i++) {\n\n if(alist[i].is_list)\n\n max_size += alist[i].data.list.count;\n\n else\n\n max_size += 1;\n\n }\n\n int *result = malloc(max_size * sizeof(int));\n\n int index = 0;\n\n for(int i = 0; i < alist_size; i++) {\n\n if(alist[i].is_list) {\n\n for(int j = 0; j < alist[i].data.list.count; j++) {\n\n result[index++] = alist[i].data.list.value;\n\n }\n\n }\n\n else {\n\n result[index++] = alist[i].data.single;\n\n }\n\n }\n\n DecodedList decoded;\n\n decoded.array = result;\n\n decoded.size = index;\n\n return decoded;\n\n}\n\n\n\n", + "func": "int func0(DecodedList a, int *b, int b_size) {\n if (a.size != b_size) return 0;\n for (int i = 0; i < a.size; i++) {\n if (a.array[i] != b[i]) return 0;\n }\n return 1;\n}", + "test": "int main() {\n\n // First test case\n\n Element input1[] = {\n\n {1, .data.list = {2, 1}},\n\n {0, .data.single = 2},\n\n {0, .data.single = 3},\n\n {1, .data.list = {2,4}},\n\n {0, .data.single =5},\n\n {0, .data.single =1}\n\n };\n\n int expected1[] = {1,1,2,3,4,4,5,1};\n\n DecodedList output1 = decode_list(input1, 6);\n\n assert(func0(output1, expected1, 8));\n\n free(output1.array);\n\n\n\n // Second test case\n\n Element input2[] = {\n\n {0, .data.single = 'a'},\n\n {0, .data.single = 'u'},\n\n {0, .data.single = 't'},\n\n {0, .data.single = 'o'},\n\n {0, .data.single = 'm'},\n\n {0, .data.single = 'a'},\n\n {0, .data.single = 't'},\n\n {0, .data.single = 'i'},\n\n {0, .data.single = 'c'},\n\n {0, .data.single = 'a'},\n\n {1, .data.list = {2, 'l'}},\n\n {0, .data.single = 'y'}\n\n };\n\n int expected2[] = {'a','u','t','o','m','a','t','i','c','a','l','l','y'};\n\n DecodedList output2 = decode_list(input2, 12);\n\n assert(func0(output2, expected2, 13));\n\n free(output2.array);\n\n\n\n // Third test case\n\n Element input3[] = {\n\n {0, .data.single = 'p'},\n\n {0, .data.single = 'y'},\n\n {0, .data.single = 't'},\n\n {0, .data.single = 'h'},\n\n {0, .data.single = 'o'},\n\n {0, .data.single = 'n'}\n\n };\n\n int expected3[] = {'p','y','t','h','o','n'};\n\n DecodedList output3 = decode_list(input3, 6);\n\n assert(func0(output3, expected3, 6));\n\n free(output3.array);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rsi,%rax\nmov %rdi,%r8\nmov %r8,%rsi\nmov %r9,%rdi\nmov %rax,%rdi\nmov %rsi,-0x20(%rbp)\nmov %rdi,-0x18(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %ecx,-0x2c(%rbp)\nmov -0x18(%rbp),%eax\ncmp %eax,-0x2c(%rbp)\nje 137a \nmov $0x0,%eax\njmp 13c8 \nmovl $0x0,-0x4(%rbp)\njmp 13bb \nmov -0x20(%rbp),%rax\nmov -0x4(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x2,%rdx\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\nje 13b7 \nmov $0x0,%eax\njmp 13c8 \naddl $0x1,-0x4(%rbp)\nmov -0x18(%rbp),%eax\ncmp %eax,-0x4(%rbp)\njl 1383 \nmov $0x1,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov rax, rdi\nmov r8, rsi\nmov rsi, rax\nmov rdi, rdx\nmov rdi, r8\nmov [rbp+var_20], rsi\nmov [rbp+var_18], rdi\nmov [rbp+var_28], rdx\nmov [rbp+var_2C], ecx\nmov eax, dword ptr [rbp+var_18]\ncmp [rbp+var_2C], eax\njz short loc_137A\nmov eax, 0\njmp short loc_13C8\nloc_137A:\nmov [rbp+var_4], 0\njmp short loc_13BB\nloc_1383:\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_13B7\nmov eax, 0\njmp short loc_13C8\nloc_13B7:\nadd [rbp+var_4], 1\nloc_13BB:\nmov eax, dword ptr [rbp+var_18]\ncmp [rbp+var_4], eax\njl short loc_1383\nmov eax, 1\nloc_13C8:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3, int a4)\n{\n int i; // [rsp+28h] [rbp-4h]\n\n if ( a4 != a2 )\n return 0LL;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) != *(_DWORD *)(4LL * i + a3) )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1345:\nendbr64\npush rbp\nmov rbp, rsp\nmov rax, rdi\nmov r8, rsi\nmov rsi, rax\nmov rdi, rdx\nmov rdi, r8\nmov [rbp+var_20], rsi\nmov [rbp+var_18], rdi\nmov [rbp+var_28], rdx\nmov [rbp+var_2C], ecx\nmov eax, dword ptr [rbp+var_18]\ncmp [rbp+var_2C], eax\njz short loc_137A\nmov eax, 0\njmp short loc_13C8\nloc_137A:\nmov [rbp+var_4], 0\njmp short loc_13BB\nloc_1383:\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_13B7\nmov eax, 0\njmp short loc_13C8\nloc_13B7:\nadd [rbp+var_4], 1\nloc_13BB:\nmov eax, dword ptr [rbp+var_18]\ncmp [rbp+var_4], eax\njl short loc_1383\nmov eax, 1\nloc_13C8:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1345(__int64 a1, int a2, __int64 a3, int a4)\n{\n int i; // [rsp+28h] [rbp-4h]\n\n if ( a4 != a2 )\n return 0LL;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) != *(_DWORD *)(4LL * i + a3) )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1345(long long a1, int a2, long long a3, int a4) {\n int i;\n if (a4 != a2) return 0LL;\n for (i = 0; i < a2; ++i) {\n if (*(uint32_t *)(4LL * i + a1) != *(uint32_t *)(4LL * i + a3)) return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3, int a4) {\n int i;\n if (a4 != a2) return 0LL;\n for (i = 0; i < a2; ++i) {\n if (*(uint32_t *)(4LL * i + a1) != *(uint32_t *)(4LL * i + a3)) return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": 215, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int is_list;\n\n union {\n\n int single;\n\n struct {\n\n int count;\n\n int value;\n\n } list;\n\n } data;\n\n} Element;\n\n\n\ntypedef struct {\n\n int *array;\n\n int size;\n\n} DecodedList;\n\n\n\nDecodedList decode_list(Element *alist, int alist_size) {\n\n // Estimate maximum possible size\n\n int max_size = 0;\n\n for(int i = 0; i < alist_size; i++) {\n\n if(alist[i].is_list)\n\n max_size += alist[i].data.list.count;\n\n else\n\n max_size += 1;\n\n }\n\n int *result = malloc(max_size * sizeof(int));\n\n int index = 0;\n\n for(int i = 0; i < alist_size; i++) {\n\n if(alist[i].is_list) {\n\n for(int j = 0; j < alist[i].data.list.count; j++) {\n\n result[index++] = alist[i].data.list.value;\n\n }\n\n }\n\n else {\n\n result[index++] = alist[i].data.single;\n\n }\n\n }\n\n DecodedList decoded;\n\n decoded.array = result;\n\n decoded.size = index;\n\n return decoded;\n\n}\n\n\n\n", + "func": "int func0(DecodedList a, int *b, int b_size) {\n if (a.size != b_size) return 0;\n for (int i = 0; i < a.size; i++) {\n if (a.array[i] != b[i]) return 0;\n }\n return 1;\n}", + "test": "int main() {\n\n // First test case\n\n Element input1[] = {\n\n {1, .data.list = {2, 1}},\n\n {0, .data.single = 2},\n\n {0, .data.single = 3},\n\n {1, .data.list = {2,4}},\n\n {0, .data.single =5},\n\n {0, .data.single =1}\n\n };\n\n int expected1[] = {1,1,2,3,4,4,5,1};\n\n DecodedList output1 = decode_list(input1, 6);\n\n assert(func0(output1, expected1, 8));\n\n free(output1.array);\n\n\n\n // Second test case\n\n Element input2[] = {\n\n {0, .data.single = 'a'},\n\n {0, .data.single = 'u'},\n\n {0, .data.single = 't'},\n\n {0, .data.single = 'o'},\n\n {0, .data.single = 'm'},\n\n {0, .data.single = 'a'},\n\n {0, .data.single = 't'},\n\n {0, .data.single = 'i'},\n\n {0, .data.single = 'c'},\n\n {0, .data.single = 'a'},\n\n {1, .data.list = {2, 'l'}},\n\n {0, .data.single = 'y'}\n\n };\n\n int expected2[] = {'a','u','t','o','m','a','t','i','c','a','l','l','y'};\n\n DecodedList output2 = decode_list(input2, 12);\n\n assert(func0(output2, expected2, 13));\n\n free(output2.array);\n\n\n\n // Third test case\n\n Element input3[] = {\n\n {0, .data.single = 'p'},\n\n {0, .data.single = 'y'},\n\n {0, .data.single = 't'},\n\n {0, .data.single = 'h'},\n\n {0, .data.single = 'o'},\n\n {0, .data.single = 'n'}\n\n };\n\n int expected3[] = {'p','y','t','h','o','n'};\n\n DecodedList output3 = decode_list(input3, 6);\n\n assert(func0(output3, expected3, 6));\n\n free(output3.array);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x0,%eax\ncmp %esi,%ecx\njne 12a1 \ntest %esi,%esi\njle 1296 \nlea -0x1(%rsi),%esi\nmov $0x0,%eax\njmp 127f \nmov %rcx,%rax\nmov (%rdx,%rax,4),%ecx\ncmp %ecx,(%rdi,%rax,4)\njne 129c \nlea 0x1(%rax),%rcx\ncmp %rsi,%rax\njne 127c \nmov $0x1,%eax\nretq\nmov $0x1,%eax\nretq\nmov $0x0,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov eax, 0\ncmp ecx, esi\njnz short locret_129E\ntest esi, esi\njle short loc_1293\nmovsxd rsi, esi\nlea rcx, ds:0[rsi*4]\nmov eax, 0\nloc_127C:\nmov esi, [rdx+rax]\ncmp [rdi+rax], esi\njnz short loc_1299\nadd rax, 4\ncmp rax, rcx\njnz short loc_127C\nmov eax, 1\nretn\nloc_1293:\nmov eax, 1\nretn\nloc_1299:\nmov eax, 0\nlocret_129E:\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3, int a4)\n{\n __int64 result; // rax\n __int64 v5; // rax\n\n result = 0LL;\n if ( a4 == a2 )\n {\n if ( a2 <= 0 )\n {\n return 1LL;\n }\n else\n {\n v5 = 0LL;\n while ( *(_DWORD *)(a1 + v5) == *(_DWORD *)(a3 + v5) )\n {\n v5 += 4LL;\n if ( v5 == 4LL * a2 )\n return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_125B:\nendbr64\nmov eax, 0\ncmp ecx, esi\njnz short locret_129E\ntest esi, esi\njle short loc_1293\nmovsxd rsi, esi\nlea rcx, ds:0[rsi*4]\nmov eax, 0\nloc_127C:\nmov esi, [rdx+rax]\ncmp [rdi+rax], esi\njnz short loc_1299\nadd rax, 4\ncmp rax, rcx\njnz short loc_127C\nmov eax, 1\nretn\nloc_1293:\nmov eax, 1\nretn\nloc_1299:\nmov eax, 0\nlocret_129E:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_125B(__int64 a1, int a2, __int64 a3, int a4)\n{\n __int64 result; // rax\n __int64 v5; // rax\n\n result = 0LL;\n if ( a4 == a2 )\n {\n if ( a2 <= 0 )\n {\n return 1LL;\n }\n else\n {\n v5 = 0LL;\n while ( *(_DWORD *)(a1 + v5) == *(_DWORD *)(a3 + v5) )\n {\n v5 += 4LL;\n if ( v5 == 4LL * a2 )\n return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_125B(long long a1, int a2, long long a3, int a4) {\n long long result;\n long long v5;\n result = 0LL;\n if (a4 == a2) {\n if (a2 <= 0) {\n return 1LL;\n } else {\n v5 = 0LL;\n while (*(uint32_t *)(a1 + v5) == *(uint32_t *)(a3 + v5)) {\n v5 += 4LL;\n if (v5 == 4LL * a2) return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3, int a4) {\n long long result;\n long long v5;\n result = 0LL;\n if (a4 == a2) {\n if (a2 <= 0) {\n return 1LL;\n } else {\n v5 = 0LL;\n while (*(uint32_t *)(a1 + v5) == *(uint32_t *)(a3 + v5)) {\n v5 += 4LL;\n if (v5 == 4LL * a2) return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}" + }, + { + "index": 215, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int is_list;\n\n union {\n\n int single;\n\n struct {\n\n int count;\n\n int value;\n\n } list;\n\n } data;\n\n} Element;\n\n\n\ntypedef struct {\n\n int *array;\n\n int size;\n\n} DecodedList;\n\n\n\nDecodedList decode_list(Element *alist, int alist_size) {\n\n // Estimate maximum possible size\n\n int max_size = 0;\n\n for(int i = 0; i < alist_size; i++) {\n\n if(alist[i].is_list)\n\n max_size += alist[i].data.list.count;\n\n else\n\n max_size += 1;\n\n }\n\n int *result = malloc(max_size * sizeof(int));\n\n int index = 0;\n\n for(int i = 0; i < alist_size; i++) {\n\n if(alist[i].is_list) {\n\n for(int j = 0; j < alist[i].data.list.count; j++) {\n\n result[index++] = alist[i].data.list.value;\n\n }\n\n }\n\n else {\n\n result[index++] = alist[i].data.single;\n\n }\n\n }\n\n DecodedList decoded;\n\n decoded.array = result;\n\n decoded.size = index;\n\n return decoded;\n\n}\n\n\n\n", + "func": "int func0(DecodedList a, int *b, int b_size) {\n if (a.size != b_size) return 0;\n for (int i = 0; i < a.size; i++) {\n if (a.array[i] != b[i]) return 0;\n }\n return 1;\n}", + "test": "int main() {\n\n // First test case\n\n Element input1[] = {\n\n {1, .data.list = {2, 1}},\n\n {0, .data.single = 2},\n\n {0, .data.single = 3},\n\n {1, .data.list = {2,4}},\n\n {0, .data.single =5},\n\n {0, .data.single =1}\n\n };\n\n int expected1[] = {1,1,2,3,4,4,5,1};\n\n DecodedList output1 = decode_list(input1, 6);\n\n assert(func0(output1, expected1, 8));\n\n free(output1.array);\n\n\n\n // Second test case\n\n Element input2[] = {\n\n {0, .data.single = 'a'},\n\n {0, .data.single = 'u'},\n\n {0, .data.single = 't'},\n\n {0, .data.single = 'o'},\n\n {0, .data.single = 'm'},\n\n {0, .data.single = 'a'},\n\n {0, .data.single = 't'},\n\n {0, .data.single = 'i'},\n\n {0, .data.single = 'c'},\n\n {0, .data.single = 'a'},\n\n {1, .data.list = {2, 'l'}},\n\n {0, .data.single = 'y'}\n\n };\n\n int expected2[] = {'a','u','t','o','m','a','t','i','c','a','l','l','y'};\n\n DecodedList output2 = decode_list(input2, 12);\n\n assert(func0(output2, expected2, 13));\n\n free(output2.array);\n\n\n\n // Third test case\n\n Element input3[] = {\n\n {0, .data.single = 'p'},\n\n {0, .data.single = 'y'},\n\n {0, .data.single = 't'},\n\n {0, .data.single = 'h'},\n\n {0, .data.single = 'o'},\n\n {0, .data.single = 'n'}\n\n };\n\n int expected3[] = {'p','y','t','h','o','n'};\n\n DecodedList output3 = decode_list(input3, 6);\n\n assert(func0(output3, expected3, 6));\n\n free(output3.array);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nxor %eax,%eax\ncmp %esi,%ecx\njne 166e \ntest %ecx,%ecx\njle 1670 \nlea -0x1(%rcx),%esi\nxor %eax,%eax\njmp 1664 \nnopl (%rax)\nlea 0x1(%rax),%rcx\ncmp %rsi,%rax\nje 1670 \nmov %rcx,%rax\nmov (%rdx,%rax,4),%ecx\ncmp %ecx,(%rdi,%rax,4)\nje 1658 \nxor %eax,%eax\nretq\nmov $0x1,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nxor eax, eax\ncmp ecx, esi\njnz short locret_1603\ntest ecx, ecx\njle short loc_1608\nmovsxd rcx, ecx\nxor eax, eax\nshl rcx, 2\njmp short loc_15F9\nloc_15F0:\nadd rax, 4\ncmp rcx, rax\njz short loc_1608\nloc_15F9:\nmov esi, [rdx+rax]\ncmp [rdi+rax], esi\njz short loc_15F0\nxor eax, eax\nlocret_1603:\nretn\nloc_1608:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3, int a4)\n{\n __int64 result; // rax\n __int64 v5; // rax\n __int64 v6; // rcx\n\n result = 0LL;\n if ( a4 == a2 )\n {\n if ( a4 <= 0 )\n {\n return 1LL;\n }\n else\n {\n v5 = 0LL;\n v6 = 4LL * a4;\n while ( *(_DWORD *)(a1 + v5) == *(_DWORD *)(a3 + v5) )\n {\n v5 += 4LL;\n if ( v6 == v5 )\n return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_15D0:\nendbr64\nxor eax, eax\ncmp ecx, esi\njnz short locret_1603\ntest ecx, ecx\njle short loc_1608\nmovsxd rcx, ecx\nxor eax, eax\nshl rcx, 2\njmp short loc_15F9\nloc_15F0:\nadd rax, 4\ncmp rcx, rax\njz short loc_1608\nloc_15F9:\nmov esi, [rdx+rax]\ncmp [rdi+rax], esi\njz short loc_15F0\nxor eax, eax\nlocret_1603:\nretn\nloc_1608:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_15D0(__int64 a1, int a2, __int64 a3, int a4)\n{\n __int64 result; // rax\n __int64 v5; // rax\n __int64 v6; // rcx\n\n result = 0LL;\n if ( a4 == a2 )\n {\n if ( a4 <= 0 )\n {\n return 1LL;\n }\n else\n {\n v5 = 0LL;\n v6 = 4LL * a4;\n while ( *(_DWORD *)(a1 + v5) == *(_DWORD *)(a3 + v5) )\n {\n v5 += 4LL;\n if ( v6 == v5 )\n return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_15D0(long long a1, int a2, long long a3, int a4) {\n long long result;\n long long v5;\n long long v6;\n result = 0LL;\n if (a4 == a2) {\n if (a4 <= 0) {\n return 1LL;\n } else {\n v5 = 0LL;\n v6 = 4LL * a4;\n while (*(uint32_t *)(a1 + v5) == *(uint32_t *)(a3 + v5)) {\n v5 += 4LL;\n if (v6 == v5) return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3, int a4) {\n long long result;\n long long v5;\n long long v6;\n result = 0LL;\n if (a4 == a2) {\n if (a4 <= 0) {\n return 1LL;\n } else {\n v5 = 0LL;\n v6 = 4LL * a4;\n while (*(uint32_t *)(a1 + v5) == *(uint32_t *)(a3 + v5)) {\n v5 += 4LL;\n if (v6 == v5) return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}" + }, + { + "index": 216, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "bool func0(int list1[], int size1, int list2[], int size2) {\n bool exist = true;\n for (int i = 0; i < size2; i++) {\n bool found = false;\n for (int j = 0; j < size1; j++) {\n if (list2[i] == list1[j]) {\n found = true;\n break;\n }\n }\n if (!found) {\n exist = false;\n break;\n }\n }\n return exist;\n}", + "test": "int main() {\n\n int list1[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14};\n\n int list1_sub1[] = {12, 18, 23, 25, 45};\n\n int list1_sub2[] = {7, 11, 19, 24, 28};\n\n int list1_sub3[] = {1, 5, 8, 18, 15, 16};\n\n\n\n int list2[] = {2, 3, 1, 4, 5, 6, 8};\n\n int list2_sub1[] = {4, 5};\n\n int list2_sub2[] = {6, 8};\n\n\n\n int list3[] = {'a', 'b', 'e', 'c', 'd'};\n\n int list3_sub[] = {'g'};\n\n\n\n assert(func0(list1, 14, list1_sub1, 5) == false);\n\n assert(func0(list1, 14, list1_sub2, 5) == false);\n\n assert(func0(list1, 14, list1_sub3, 6) == false);\n\n assert(func0(list2, 7, list2_sub1, 2) == true);\n\n assert(func0(list2, 7, list2_sub2, 2) == true);\n\n assert(func0(list3, 5, list3_sub, 1) == false);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %ecx,-0x20(%rbp)\nmovb $0x1,-0xa(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11f0 \nmovb $0x0,-0x9(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11d3 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 11cf \nmovb $0x1,-0x9(%rbp)\njmp 11db \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1199 \nmovzbl -0x9(%rbp),%eax\nxor $0x1,%eax\ntest %al,%al\nje 11ec \nmovb $0x0,-0xa(%rbp)\njmp 11f8 \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x20(%rbp),%eax\njl 118c \nmovzbl -0xa(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov [rbp+var_A], 1\nmov [rbp+var_8], 0\njmp short loc_11F0\nloc_118C:\nmov [rbp+var_9], 0\nmov [rbp+var_4], 0\njmp short loc_11D3\nloc_1199:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11CF\nmov [rbp+var_9], 1\njmp short loc_11DB\nloc_11CF:\nadd [rbp+var_4], 1\nloc_11D3:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1199\nloc_11DB:\nmovzx eax, [rbp+var_9]\nxor eax, 1\ntest al, al\njz short loc_11EC\nmov [rbp+var_A], 0\njmp short loc_11F8\nloc_11EC:\nadd [rbp+var_8], 1\nloc_11F0:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_20]\njl short loc_118C\nloc_11F8:\nmovzx eax, [rbp+var_A]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3, int a4)\n{\n unsigned __int8 v5; // [rsp+1Eh] [rbp-Ah]\n char v6; // [rsp+1Fh] [rbp-9h]\n int i; // [rsp+20h] [rbp-8h]\n int j; // [rsp+24h] [rbp-4h]\n\n v5 = 1;\n for ( i = 0; i < a4; ++i )\n {\n v6 = 0;\n for ( j = 0; j < a2; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a3) == *(_DWORD *)(4LL * j + a1) )\n {\n v6 = 1;\n break;\n }\n }\n if ( v6 != 1 )\n return 0;\n }\n return v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov [rbp+var_A], 1\nmov [rbp+var_8], 0\njmp short loc_11F0\nloc_118C:\nmov [rbp+var_9], 0\nmov [rbp+var_4], 0\njmp short loc_11D3\nloc_1199:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11CF\nmov [rbp+var_9], 1\njmp short loc_11DB\nloc_11CF:\nadd [rbp+var_4], 1\nloc_11D3:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1199\nloc_11DB:\nmovzx eax, [rbp+var_9]\nxor eax, 1\ntest al, al\njz short loc_11EC\nmov [rbp+var_A], 0\njmp short loc_11F8\nloc_11EC:\nadd [rbp+var_8], 1\nloc_11F0:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_20]\njl short loc_118C\nloc_11F8:\nmovzx eax, [rbp+var_A]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, __int64 a3, int a4)\n{\n unsigned __int8 v5; // [rsp+1Eh] [rbp-Ah]\n char v6; // [rsp+1Fh] [rbp-9h]\n int i; // [rsp+20h] [rbp-8h]\n int j; // [rsp+24h] [rbp-4h]\n\n v5 = 1;\n for ( i = 0; i < a4; ++i )\n {\n v6 = 0;\n for ( j = 0; j < a2; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a3) == *(_DWORD *)(4LL * j + a1) )\n {\n v6 = 1;\n break;\n }\n }\n if ( v6 != 1 )\n return 0;\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, long long a3, int a4) {\n unsigned char v5;\n char v6;\n int i;\n int j;\n v5 = 1;\n for (i = 0; i < a4; ++i) {\n v6 = 0;\n for (j = 0; j < a2; ++j) {\n if (*(uint32_t *)(4LL * i + a3) == *(uint32_t *)(4LL * j + a1)) {\n v6 = 1;\n break;\n }\n }\n if (v6 != 1) return 0;\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3, int a4) {\n unsigned char v5;\n char v6;\n int i;\n int j;\n v5 = 1;\n for (i = 0; i < a4; ++i) {\n v6 = 0;\n for (j = 0; j < a2; ++j) {\n if (*(uint32_t *)(4LL * i + a3) == *(uint32_t *)(4LL * j + a1)) {\n v6 = 1;\n break;\n }\n }\n if (v6 != 1) return 0;\n }\n return v5;\n}" + }, + { + "index": 216, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "bool func0(int list1[], int size1, int list2[], int size2) {\n bool exist = true;\n for (int i = 0; i < size2; i++) {\n bool found = false;\n for (int j = 0; j < size1; j++) {\n if (list2[i] == list1[j]) {\n found = true;\n break;\n }\n }\n if (!found) {\n exist = false;\n break;\n }\n }\n return exist;\n}", + "test": "int main() {\n\n int list1[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14};\n\n int list1_sub1[] = {12, 18, 23, 25, 45};\n\n int list1_sub2[] = {7, 11, 19, 24, 28};\n\n int list1_sub3[] = {1, 5, 8, 18, 15, 16};\n\n\n\n int list2[] = {2, 3, 1, 4, 5, 6, 8};\n\n int list2_sub1[] = {4, 5};\n\n int list2_sub2[] = {6, 8};\n\n\n\n int list3[] = {'a', 'b', 'e', 'c', 'd'};\n\n int list3_sub[] = {'g'};\n\n\n\n assert(func0(list1, 14, list1_sub1, 5) == false);\n\n assert(func0(list1, 14, list1_sub2, 5) == false);\n\n assert(func0(list1, 14, list1_sub3, 6) == false);\n\n assert(func0(list2, 7, list2_sub1, 2) == true);\n\n assert(func0(list2, 7, list2_sub2, 2) == true);\n\n assert(func0(list3, 5, list3_sub, 1) == false);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %ecx,%ecx\njle 1189 \nmov %rdx,%r8\nlea -0x1(%rcx),%eax\nlea 0x4(%rdx,%rax,4),%r10\nmov %rdi,%r9\nlea -0x1(%rsi),%eax\nlea 0x4(%rdi,%rax,4),%rcx\njmp 119e \nmov $0x1,%eax\nretq\nmov $0x0,%eax\nretq\nadd $0x4,%r8\ncmp %r10,%r8\nje 11bb \ntest %esi,%esi\njle 118f \nmov (%r8),%edx\nmov %r9,%rax\ncmp (%rax),%edx\nje 1195 \nadd $0x4,%rax\ncmp %rcx,%rax\njne 11a8 \nmov $0x0,%eax\nretq\nmov $0x1,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov r8, rdi\ntest ecx, ecx\njle short loc_11B2\nmov rdi, rdx\nmovsxd rcx, ecx\nlea r9, [rdx+rcx*4]\nmovsxd rax, esi\nlea rcx, [r8+rax*4]\njmp short loc_1190\nloc_1187:\nadd rdi, 4\ncmp rdi, r9\njz short loc_11B8\nloc_1190:\ntest esi, esi\njle short loc_11AC\nmov edx, [rdi]\nmov rax, r8\nloc_1199:\ncmp edx, [rax]\njz short loc_1187\nadd rax, 4\ncmp rax, rcx\njnz short loc_1199\nmov eax, 0\nretn\nloc_11AC:\nmov eax, 0\nretn\nloc_11B2:\nmov eax, 1\nretn\nloc_11B8:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2, _DWORD *a3, int a4)\n{\n _DWORD *v5; // rdi\n _DWORD *v6; // rax\n\n if ( a4 <= 0 )\n return 1LL;\n v5 = a3;\n while ( 2 )\n {\n if ( a2 <= 0 )\n return 0LL;\n v6 = a1;\n while ( *v5 != *v6 )\n {\n if ( ++v6 == &a1[a2] )\n return 0LL;\n }\n if ( ++v5 != &a3[a4] )\n continue;\n break;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov r8, rdi\ntest ecx, ecx\njle short loc_11B2\nmov rdi, rdx\nmovsxd rcx, ecx\nlea r9, [rdx+rcx*4]\nmovsxd rax, esi\nlea rcx, [r8+rax*4]\njmp short loc_1190\nloc_1187:\nadd rdi, 4\ncmp rdi, r9\njz short loc_11B8\nloc_1190:\ntest esi, esi\njle short loc_11AC\nmov edx, [rdi]\nmov rax, r8\nloc_1199:\ncmp edx, [rax]\njz short loc_1187\nadd rax, 4\ncmp rax, rcx\njnz short loc_1199\nmov eax, 0\nretn\nloc_11AC:\nmov eax, 0\nretn\nloc_11B2:\nmov eax, 1\nretn\nloc_11B8:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2, _DWORD *a3, int a4)\n{\n _DWORD *v5; // rdi\n _DWORD *v6; // rax\n\n if ( a4 <= 0 )\n return 1LL;\n v5 = a3;\n while ( 2 )\n {\n if ( a2 <= 0 )\n return 0LL;\n v6 = a1;\n while ( *v5 != *v6 )\n {\n if ( ++v6 == &a1[a2] )\n return 0LL;\n }\n if ( ++v5 != &a3[a4] )\n continue;\n break;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2, uint32_t *a3, int a4) {\n uint32_t *v5;\n uint32_t *v6;\n if (a4 <= 0) return 1LL;\n v5 = a3;\n while (2) {\n if (a2 <= 0) return 0LL;\n v6 = a1;\n while (*v5 != *v6) {\n if (++v6 == &a1[a2]) return 0LL;\n }\n if (++v5 != &a3[a4]) continue;\n break;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2, uint32_t *a3, int a4) {\n uint32_t *v5;\n uint32_t *v6;\n if (a4 <= 0) return 1LL;\n v5 = a3;\n while (2) {\n if (a2 <= 0) return 0LL;\n v6 = a1;\n while (*v5 != *v6) {\n if (++v6 == &a1[a2]) return 0LL;\n }\n if (++v5 != &a3[a4]) continue;\n break;\n }\n return 1LL;\n}" + }, + { + "index": 216, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "bool func0(int list1[], int size1, int list2[], int size2) {\n bool exist = true;\n for (int i = 0; i < size2; i++) {\n bool found = false;\n for (int j = 0; j < size1; j++) {\n if (list2[i] == list1[j]) {\n found = true;\n break;\n }\n }\n if (!found) {\n exist = false;\n break;\n }\n }\n return exist;\n}", + "test": "int main() {\n\n int list1[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14};\n\n int list1_sub1[] = {12, 18, 23, 25, 45};\n\n int list1_sub2[] = {7, 11, 19, 24, 28};\n\n int list1_sub3[] = {1, 5, 8, 18, 15, 16};\n\n\n\n int list2[] = {2, 3, 1, 4, 5, 6, 8};\n\n int list2_sub1[] = {4, 5};\n\n int list2_sub2[] = {6, 8};\n\n\n\n int list3[] = {'a', 'b', 'e', 'c', 'd'};\n\n int list3_sub[] = {'g'};\n\n\n\n assert(func0(list1, 14, list1_sub1, 5) == false);\n\n assert(func0(list1, 14, list1_sub2, 5) == false);\n\n assert(func0(list1, 14, list1_sub3, 6) == false);\n\n assert(func0(list2, 7, list2_sub1, 2) == true);\n\n assert(func0(list2, 7, list2_sub2, 2) == true);\n\n assert(func0(list3, 5, list3_sub, 1) == false);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %ecx,%ecx\njle 1566 \nlea -0x1(%rcx),%eax\nmov %rdx,%r8\nlea 0x4(%rdx,%rax,4),%r9\nlea -0x1(%rsi),%eax\nlea 0x4(%rdi,%rax,4),%rcx\nnopl 0x0(%rax,%rax,1)\ntest %esi,%esi\njle 1570 \nmov (%r8),%edx\nmov %rdi,%rax\njmp 1559 \nnopl 0x0(%rax)\nadd $0x4,%rax\ncmp %rcx,%rax\nje 1570 \ncmp (%rax),%edx\njne 1550 \nadd $0x4,%r8\ncmp %r9,%r8\njne 1540 \nmov $0x1,%eax\nretq\nnopl 0x0(%rax)\nxor %eax,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\nmov r8, rdi\ntest ecx, ecx\njle short loc_1466\nmovsxd rcx, ecx\nmovsxd rax, esi\nlea r9, [rdx+rcx*4]\nlea rdi, [rdi+rax*4]\ntest esi, esi\njle short loc_1470\nnop dword ptr [rax]\nloc_1440:\nmov ecx, [rdx]\nmov rax, r8\njmp short loc_1459\nloc_1450:\nadd rax, 4\ncmp rax, rdi\njz short loc_1470\nloc_1459:\ncmp ecx, [rax]\njnz short loc_1450\nadd rdx, 4\ncmp rdx, r9\njnz short loc_1440\nloc_1466:\nmov eax, 1\nretn\nloc_1470:\nxor eax, eax\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2, _DWORD *a3, int a4)\n{\n _DWORD *v5; // r9\n _DWORD *v6; // rdi\n _DWORD *v7; // rax\n\n if ( a4 <= 0 )\n return 1LL;\n v5 = &a3[a4];\n v6 = &a1[a2];\n if ( a2 > 0 )\n {\n do\n {\n v7 = a1;\n while ( *a3 != *v7 )\n {\n if ( ++v7 == v6 )\n return 0LL;\n }\n ++a3;\n }\n while ( a3 != v5 );\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1420:\nendbr64\nmov r8, rdi\ntest ecx, ecx\njle short loc_1466\nmovsxd rcx, ecx\nmovsxd rax, esi\nlea r9, [rdx+rcx*4]\nlea rdi, [rdi+rax*4]\ntest esi, esi\njle short loc_1470\nnop dword ptr [rax]\nloc_1440:\nmov ecx, [rdx]\nmov rax, r8\njmp short loc_1459\nloc_1450:\nadd rax, 4\ncmp rax, rdi\njz short loc_1470\nloc_1459:\ncmp ecx, [rax]\njnz short loc_1450\nadd rdx, 4\ncmp rdx, r9\njnz short loc_1440\nloc_1466:\nmov eax, 1\nretn\nloc_1470:\nxor eax, eax\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1420(_DWORD *a1, int a2, _DWORD *a3, int a4)\n{\n _DWORD *v5; // r9\n _DWORD *v6; // rdi\n _DWORD *v7; // rax\n\n if ( a4 <= 0 )\n return 1LL;\n v5 = &a3[a4];\n v6 = &a1[a2];\n if ( a2 > 0 )\n {\n do\n {\n v7 = a1;\n while ( *a3 != *v7 )\n {\n if ( ++v7 == v6 )\n return 0LL;\n }\n ++a3;\n }\n while ( a3 != v5 );\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1420(uint32_t *a1, int a2, uint32_t *a3, int a4) {\n uint32_t *v5;\n uint32_t *v6;\n uint32_t *v7;\n if (a4 <= 0) return 1LL;\n v5 = &a3[a4];\n v6 = &a1[a2];\n if (a2 > 0) {\n do {\n v7 = a1;\n while (*a3 != *v7) {\n if (++v7 == v6) return 0LL;\n }\n ++a3;\n } while (a3 != v5);\n return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2, uint32_t *a3, int a4) {\n uint32_t *v5;\n uint32_t *v6;\n uint32_t *v7;\n if (a4 <= 0) return 1LL;\n v5 = &a3[a4];\n v6 = &a1[a2];\n if (a2 > 0) {\n do {\n v7 = a1;\n while (*a3 != *v7) {\n if (++v7 == v6) return 0LL;\n }\n ++a3;\n } while (a3 != v5);\n return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 217, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "char func0(char* str) {\n int h[256] = {0};\n for (int i = 0; str[i] != '\\0'; i++) {\n if (h[(int)str[i]] == 1)\n return str[i];\n else\n h[(int)str[i]]++;\n }\n return '\\0';\n}", + "test": "int main() {\n\n assert(func0(\"Google\") == 'o');\n\n assert(func0(\"data\") == 'a');\n\n assert(func0(\"python\") == '\\0');\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x430,%rsp\nmov %rdi,-0x428(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea -0x410(%rbp),%rdx\nmov $0x0,%eax\nmov $0x80,%ecx\nmov %rdx,%rdi\nrep stos %rax,%es:(%rdi)\nmovl $0x0,-0x414(%rbp)\njmp 1226 \nmov -0x414(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x428(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmovsbl %al,%eax\ncltq\nmov -0x410(%rbp,%rax,4),%eax\ncmp $0x1,%eax\njne 11f0 \nmov -0x414(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x428(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\njmp 1249 \nmov -0x414(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x428(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmovsbl %al,%eax\nmovslq %eax,%rdx\nmov -0x410(%rbp,%rdx,4),%edx\nadd $0x1,%edx\ncltq\nmov %edx,-0x410(%rbp,%rax,4)\naddl $0x1,-0x414(%rbp)\nmov -0x414(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x428(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 11b1 \nmov $0x0,%eax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 125d \ncallq 1060 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 430h\nmov [rbp+var_428], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rdx, [rbp+var_410]\nmov eax, 0\nmov ecx, 80h\nmov rdi, rdx\nrep stosq\nmov [rbp+var_414], 0\njmp short loc_1226\nloc_11B1:\nmov eax, [rbp+var_414]\nmovsxd rdx, eax\nmov rax, [rbp+var_428]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\ncdqe\nmov eax, [rbp+rax*4+var_410]\ncmp eax, 1\njnz short loc_11F0\nmov eax, [rbp+var_414]\nmovsxd rdx, eax\nmov rax, [rbp+var_428]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\njmp short loc_1249\nloc_11F0:\nmov eax, [rbp+var_414]\nmovsxd rdx, eax\nmov rax, [rbp+var_428]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nmovsxd rdx, eax\nmov edx, [rbp+rdx*4+var_410]\nadd edx, 1\ncdqe\nmov [rbp+rax*4+var_410], edx\nadd [rbp+var_414], 1\nloc_1226:\nmov eax, [rbp+var_414]\nmovsxd rdx, eax\nmov rax, [rbp+var_428]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_11B1\nmov eax, 0\nloc_1249:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_125D\ncall ___stack_chk_fail\nlocret_125D:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1)\n{\n int i; // [rsp+1Ch] [rbp-414h]\n _DWORD v3[258]; // [rsp+20h] [rbp-410h] BYREF\n unsigned __int64 v4; // [rsp+428h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n memset(v3, 0, 0x400uLL);\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n {\n if ( v3[*(char *)(i + a1)] == 1 )\n return *(unsigned __int8 *)(i + a1);\n ++v3[*(char *)(i + a1)];\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 430h\nmov [rbp+var_428], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rdx, [rbp+var_410]\nmov eax, 0\nmov ecx, 80h\nmov rdi, rdx\nrep stosq\nmov [rbp+var_414], 0\njmp short loc_1226\nloc_11B1:\nmov eax, [rbp+var_414]\nmovsxd rdx, eax\nmov rax, [rbp+var_428]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\ncdqe\nmov eax, [rbp+rax*4+var_410]\ncmp eax, 1\njnz short loc_11F0\nmov eax, [rbp+var_414]\nmovsxd rdx, eax\nmov rax, [rbp+var_428]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\njmp short loc_1249\nloc_11F0:\nmov eax, [rbp+var_414]\nmovsxd rdx, eax\nmov rax, [rbp+var_428]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nmovsxd rdx, eax\nmov edx, [rbp+rdx*4+var_410]\nadd edx, 1\ncdqe\nmov [rbp+rax*4+var_410], edx\nadd [rbp+var_414], 1\nloc_1226:\nmov eax, [rbp+var_414]\nmovsxd rdx, eax\nmov rax, [rbp+var_428]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_11B1\nmov eax, 0\nloc_1249:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_125D\ncall ___stack_chk_fail\nlocret_125D:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1)\n{\n int i; // [rsp+1Ch] [rbp-414h]\n _DWORD v3[258]; // [rsp+20h] [rbp-410h] BYREF\n unsigned __int64 v4; // [rsp+428h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n memset(v3, 0, 0x400uLL);\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n {\n if ( v3[*(char *)(i + a1)] == 1 )\n return *(unsigned __int8 *)(i + a1);\n ++v3[*(char *)(i + a1)];\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1) {\n int i;\n uint32_t v3[258];\n unsigned long long v4;\n v4 = __readfsqword(40u);\n memset(v3, 0, 1024uLL);\n for (i = 0; *(uint8_t *)(i + a1); ++i) {\n if (v3[*(char *)(i + a1)] == 1) return *(unsigned char *)(i + a1);\n ++v3[*(char *)(i + a1)];\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1) {\n int i;\n uint32_t v3[258];\n unsigned long long v4;\n v4 = __readfsqword(40u);\n memset(v3, 0, 1024uLL);\n for (i = 0; *(uint8_t *)(i + a1); ++i) {\n if (v3[*(char *)(i + a1)] == 1) return *(unsigned char *)(i + a1);\n ++v3[*(char *)(i + a1)];\n }\n return 0LL;\n}" + }, + { + "index": 217, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "char func0(char* str) {\n int h[256] = {0};\n for (int i = 0; str[i] != '\\0'; i++) {\n if (h[(int)str[i]] == 1)\n return str[i];\n else\n h[(int)str[i]]++;\n }\n return '\\0';\n}", + "test": "int main() {\n\n assert(func0(\"Google\") == 'o');\n\n assert(func0(\"data\") == 'a');\n\n assert(func0(\"python\") == '\\0');\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x418,%rsp\nmov %rdi,%rsi\nmov %fs:0x28,%rax\nmov %rax,0x408(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nmov $0x80,%ecx\nrep stos %rax,%es:(%rdi)\nmovzbl (%rsi),%edx\ntest %dl,%dl\nje 11c4 \nlea 0x1(%rsi),%rdi\nmovsbl %dl,%ecx\nmovsbq %dl,%rax\nmov (%rsp,%rax,4),%eax\ncmp $0x1,%eax\nje 11c4 \nmovslq %ecx,%rcx\nadd $0x1,%eax\nmov %eax,(%rsp,%rcx,4)\nadd $0x1,%rdi\nmovzbl -0x1(%rdi),%edx\ntest %dl,%dl\njne 11a0 \nmov 0x408(%rsp),%rax\nxor %fs:0x28,%rax\njne 11e1 \nmov %edx,%eax\nadd $0x418,%rsp\nretq\ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 418h\nmov rsi, rdi\nmov rax, fs:28h\nmov [rsp+418h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nmov ecx, 80h\nrep stosq\nmovzx edx, byte ptr [rsi]\ntest dl, dl\njz short loc_11C4\nlea rdi, [rsi+1]\nloc_11A0:\nmovsx ecx, dl\nmovsx rax, dl\nmov eax, [rsp+rax*4+418h+var_418]\ncmp eax, 1\njz short loc_11C4\nmovsxd rcx, ecx\nadd eax, 1\nmov [rsp+rcx*4+418h+var_418], eax\nadd rdi, 1\nmovzx edx, byte ptr [rdi-1]\ntest dl, dl\njnz short loc_11A0\nloc_11C4:\nmov rax, [rsp+418h+var_10]\nsub rax, fs:28h\njnz short loc_11E1\nmov eax, edx\nadd rsp, 418h\nretn\nloc_11E1:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(unsigned __int8 *a1)\n{\n unsigned int v1; // edx\n unsigned __int8 *v2; // rdi\n int v3; // eax\n _DWORD v5[258]; // [rsp+0h] [rbp-418h] BYREF\n unsigned __int64 v6; // [rsp+408h] [rbp-10h]\n\n v6 = __readfsqword(0x28u);\n memset(v5, 0, 0x400uLL);\n v1 = *a1;\n if ( (_BYTE)v1 )\n {\n v2 = a1 + 1;\n do\n {\n v3 = v5[(char)v1];\n if ( v3 == 1 )\n break;\n v5[(char)v1] = v3 + 1;\n v1 = *v2++;\n }\n while ( (_BYTE)v1 );\n }\n return v1;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nsub rsp, 418h\nmov rsi, rdi\nmov rax, fs:28h\nmov [rsp+418h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nmov ecx, 80h\nrep stosq\nmovzx edx, byte ptr [rsi]\ntest dl, dl\njz short loc_11C4\nlea rdi, [rsi+1]\nloc_11A0:\nmovsx ecx, dl\nmovsx rax, dl\nmov eax, [rsp+rax*4+418h+var_418]\ncmp eax, 1\njz short loc_11C4\nmovsxd rcx, ecx\nadd eax, 1\nmov [rsp+rcx*4+418h+var_418], eax\nadd rdi, 1\nmovzx edx, byte ptr [rdi-1]\ntest dl, dl\njnz short loc_11A0\nloc_11C4:\nmov rax, [rsp+418h+var_10]\nsub rax, fs:28h\njnz short loc_11E1\nmov eax, edx\nadd rsp, 418h\nretn\nloc_11E1:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(unsigned __int8 *a1)\n{\n unsigned int v1; // edx\n unsigned __int8 *v2; // rdi\n int v3; // eax\n _DWORD v5[258]; // [rsp+0h] [rbp-418h] BYREF\n unsigned __int64 v6; // [rsp+408h] [rbp-10h]\n\n v6 = __readfsqword(0x28u);\n memset(v5, 0, 0x400uLL);\n v1 = *a1;\n if ( (_BYTE)v1 )\n {\n v2 = a1 + 1;\n do\n {\n v3 = v5[(char)v1];\n if ( v3 == 1 )\n break;\n v5[(char)v1] = v3 + 1;\n v1 = *v2++;\n }\n while ( (_BYTE)v1 );\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(unsigned char *a1) {\n unsigned int v1;\n unsigned char *v2;\n int v3;\n uint32_t v5[258];\n unsigned long long v6;\n v6 = __readfsqword(40u);\n memset(v5, 0, 1024uLL);\n v1 = *a1;\n if ((uint8_t)v1) {\n v2 = a1 + 1;\n do {\n v3 = v5[(char)v1];\n if (v3 == 1) break;\n v5[(char)v1] = v3 + 1;\n v1 = *v2++;\n } while ((uint8_t)v1);\n }\n return v1;\n}", + "ida_pseudo_norm": "long long func0(unsigned char *a1) {\n unsigned int v1;\n unsigned char *v2;\n int v3;\n uint32_t v5[258];\n unsigned long long v6;\n v6 = __readfsqword(40u);\n memset(v5, 0, 1024uLL);\n v1 = *a1;\n if ((uint8_t)v1) {\n v2 = a1 + 1;\n do {\n v3 = v5[(char)v1];\n if (v3 == 1) break;\n v5[(char)v1] = v3 + 1;\n v1 = *v2++;\n } while ((uint8_t)v1);\n }\n return v1;\n}" + }, + { + "index": 217, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "char func0(char* str) {\n int h[256] = {0};\n for (int i = 0; str[i] != '\\0'; i++) {\n if (h[(int)str[i]] == 1)\n return str[i];\n else\n h[(int)str[i]]++;\n }\n return '\\0';\n}", + "test": "int main() {\n\n assert(func0(\"Google\") == 'o');\n\n assert(func0(\"data\") == 'a');\n\n assert(func0(\"python\") == '\\0');\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x418,%rsp\nmov %rdi,%rdx\nmov $0x80,%ecx\nmov %fs:0x28,%rax\nmov %rax,0x408(%rsp)\nxor %eax,%eax\nmovzbl (%rdx),%r8d\nmov %rsp,%rdi\nrep stos %rax,%es:(%rdi)\ntest %r8b,%r8b\nje 1290 \nlea 0x1(%rdx),%rdi\njmp 1263 \nnopl 0x0(%rax,%rax,1)\nmovzbl (%rdi),%r8d\nadd $0x1,%eax\nadd $0x1,%rdi\nmov %eax,(%rsp,%rdx,4)\ntest %r8b,%r8b\nje 1290 \nmovsbq %r8b,%rdx\nmov (%rsp,%rdx,4),%eax\ncmp $0x1,%eax\njne 1250 \nmov 0x408(%rsp),%rax\nxor %fs:0x28,%rax\njne 1295 \nmov %r8d,%eax\nadd $0x418,%rsp\nretq\nnopl (%rax)\nxor %r8d,%r8d\njmp 126f \ncallq 1060 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 418h\nmov rdx, rdi\nmov ecx, 80h\nmov rax, fs:28h\nmov [rsp+418h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\nmovzx ecx, byte ptr [rdx]\ntest cl, cl\njz short loc_1290\nlea rdi, [rdx+1]\njmp short loc_1261\nloc_1250:\nmovzx ecx, byte ptr [rdi]\nadd eax, 1\nadd rdi, 1\nmov [rsp+rdx*4+418h+var_418], eax\ntest cl, cl\njz short loc_1290\nloc_1261:\nmovsx rdx, cl\nmov eax, [rsp+rdx*4+418h+var_418]\ncmp eax, 1\njnz short loc_1250\nloc_126D:\nmov rax, [rsp+418h+var_10]\nsub rax, fs:28h\njnz short loc_1294\nmov eax, ecx\nadd rsp, 418h\nretn\nloc_1290:\nxor ecx, ecx\njmp short loc_126D\nloc_1294:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(unsigned __int8 *a1)\n{\n unsigned int v1; // ecx\n unsigned __int8 *v2; // rdi\n __int64 v3; // rdx\n int v4; // eax\n _DWORD v6[258]; // [rsp+0h] [rbp-418h] BYREF\n unsigned __int64 v7; // [rsp+408h] [rbp-10h]\n\n v7 = __readfsqword(0x28u);\n memset(v6, 0, 0x400uLL);\n v1 = *a1;\n if ( (_BYTE)v1 )\n {\n v2 = a1 + 1;\n while ( 1 )\n {\n v3 = (char)v1;\n v4 = v6[(char)v1];\n if ( v4 == 1 )\n break;\n v1 = *v2++;\n v6[v3] = v4 + 1;\n if ( !(_BYTE)v1 )\n return 0;\n }\n }\n else\n {\n return 0;\n }\n return v1;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\nsub rsp, 418h\nmov rdx, rdi\nmov ecx, 80h\nmov rax, fs:28h\nmov [rsp+418h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\nmovzx ecx, byte ptr [rdx]\ntest cl, cl\njz short loc_1290\nlea rdi, [rdx+1]\njmp short loc_1261\nloc_1250:\nmovzx ecx, byte ptr [rdi]\nadd eax, 1\nadd rdi, 1\nmov [rsp+rdx*4+418h+var_418], eax\ntest cl, cl\njz short loc_1290\nloc_1261:\nmovsx rdx, cl\nmov eax, [rsp+rdx*4+418h+var_418]\ncmp eax, 1\njnz short loc_1250\nloc_126D:\nmov rax, [rsp+418h+var_10]\nsub rax, fs:28h\njnz short loc_1294\nmov eax, ecx\nadd rsp, 418h\nretn\nloc_1290:\nxor ecx, ecx\njmp short loc_126D\nloc_1294:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(unsigned __int8 *a1)\n{\n unsigned int v1; // ecx\n unsigned __int8 *v2; // rdi\n __int64 v3; // rdx\n int v4; // eax\n _DWORD v6[258]; // [rsp+0h] [rbp-418h] BYREF\n unsigned __int64 v7; // [rsp+408h] [rbp-10h]\n\n v7 = __readfsqword(0x28u);\n memset(v6, 0, 0x400uLL);\n v1 = *a1;\n if ( (_BYTE)v1 )\n {\n v2 = a1 + 1;\n while ( 1 )\n {\n v3 = (char)v1;\n v4 = v6[(char)v1];\n if ( v4 == 1 )\n break;\n v1 = *v2++;\n v6[v3] = v4 + 1;\n if ( !(_BYTE)v1 )\n return 0;\n }\n }\n else\n {\n return 0;\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(unsigned char *a1) {\n unsigned int v1;\n unsigned char *v2;\n long long v3;\n int v4;\n uint32_t v6[258];\n unsigned long long v7;\n v7 = __readfsqword(40u);\n memset(v6, 0, 1024uLL);\n v1 = *a1;\n if ((uint8_t)v1) {\n v2 = a1 + 1;\n while (1) {\n v3 = (char)v1;\n v4 = v6[(char)v1];\n if (v4 == 1) break;\n v1 = *v2++;\n v6[v3] = v4 + 1;\n if (!(uint8_t)v1) return 0;\n }\n } else {\n return 0;\n }\n return v1;\n}", + "ida_pseudo_norm": "long long func0(unsigned char *a1) {\n unsigned int v1;\n unsigned char *v2;\n long long v3;\n int v4;\n uint32_t v6[258];\n unsigned long long v7;\n v7 = __readfsqword(40u);\n memset(v6, 0, 1024uLL);\n v1 = *a1;\n if ((uint8_t)v1) {\n v2 = a1 + 1;\n while (1) {\n v3 = (char)v1;\n v4 = v6[(char)v1];\n if (v4 == 1) break;\n v1 = *v2++;\n v6[v3] = v4 + 1;\n if (!(uint8_t)v1) return 0;\n }\n } else {\n return 0;\n }\n return v1;\n}" + }, + { + "index": 217, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "char func0(char* str) {\n int h[256] = {0};\n for (int i = 0; str[i] != '\\0'; i++) {\n if (h[(int)str[i]] == 1)\n return str[i];\n else\n h[(int)str[i]]++;\n }\n return '\\0';\n}", + "test": "int main() {\n\n assert(func0(\"Google\") == 'o');\n\n assert(func0(\"data\") == 'a');\n\n assert(func0(\"python\") == '\\0');\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x418,%rsp\nmov %rdi,%rdx\nmov $0x80,%ecx\nmov %fs:0x28,%rax\nmov %rax,0x408(%rsp)\nxor %eax,%eax\nmovzbl (%rdx),%r8d\nmov %rsp,%rdi\nrep stos %rax,%es:(%rdi)\ntest %r8b,%r8b\nje 1290 \nlea 0x1(%rdx),%rdi\njmp 1263 \nnopl 0x0(%rax,%rax,1)\nmovzbl (%rdi),%r8d\nadd $0x1,%eax\nadd $0x1,%rdi\nmov %eax,(%rsp,%rdx,4)\ntest %r8b,%r8b\nje 1290 \nmovsbq %r8b,%rdx\nmov (%rsp,%rdx,4),%eax\ncmp $0x1,%eax\njne 1250 \nmov 0x408(%rsp),%rax\nxor %fs:0x28,%rax\njne 1295 \nmov %r8d,%eax\nadd $0x418,%rsp\nretq\nnopl (%rax)\nxor %r8d,%r8d\njmp 126f \ncallq 1060 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 418h\nmov rdx, rdi\nmov ecx, 80h\nmov rax, fs:28h\nmov [rsp+418h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\nmovzx ecx, byte ptr [rdx]\ntest cl, cl\njz short loc_1290\nlea rdi, [rdx+1]\njmp short loc_1261\nloc_1250:\nmovzx ecx, byte ptr [rdi]\nadd eax, 1\nadd rdi, 1\nmov [rsp+rdx*4+418h+var_418], eax\ntest cl, cl\njz short loc_1290\nloc_1261:\nmovsx rdx, cl\nmov eax, [rsp+rdx*4+418h+var_418]\ncmp eax, 1\njnz short loc_1250\nloc_126D:\nmov rax, [rsp+418h+var_10]\nsub rax, fs:28h\njnz short loc_1294\nmov eax, ecx\nadd rsp, 418h\nretn\nloc_1290:\nxor ecx, ecx\njmp short loc_126D\nloc_1294:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(unsigned __int8 *a1)\n{\n unsigned int v1; // ecx\n unsigned __int8 *v2; // rdi\n __int64 v3; // rdx\n int v4; // eax\n _DWORD v6[258]; // [rsp+0h] [rbp-418h] BYREF\n unsigned __int64 v7; // [rsp+408h] [rbp-10h]\n\n v7 = __readfsqword(0x28u);\n memset(v6, 0, 0x400uLL);\n v1 = *a1;\n if ( (_BYTE)v1 )\n {\n v2 = a1 + 1;\n while ( 1 )\n {\n v3 = (char)v1;\n v4 = v6[(char)v1];\n if ( v4 == 1 )\n break;\n v1 = *v2++;\n v6[v3] = v4 + 1;\n if ( !(_BYTE)v1 )\n return 0;\n }\n }\n else\n {\n return 0;\n }\n return v1;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\nsub rsp, 418h\nmov rdx, rdi\nmov ecx, 80h\nmov rax, fs:28h\nmov [rsp+418h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\nmovzx ecx, byte ptr [rdx]\ntest cl, cl\njz short loc_1290\nlea rdi, [rdx+1]\njmp short loc_1261\nloc_1250:\nmovzx ecx, byte ptr [rdi]\nadd eax, 1\nadd rdi, 1\nmov [rsp+rdx*4+418h+var_418], eax\ntest cl, cl\njz short loc_1290\nloc_1261:\nmovsx rdx, cl\nmov eax, [rsp+rdx*4+418h+var_418]\ncmp eax, 1\njnz short loc_1250\nloc_126D:\nmov rax, [rsp+418h+var_10]\nsub rax, fs:28h\njnz short loc_1294\nmov eax, ecx\nadd rsp, 418h\nretn\nloc_1290:\nxor ecx, ecx\njmp short loc_126D\nloc_1294:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(unsigned __int8 *a1)\n{\n unsigned int v1; // ecx\n unsigned __int8 *v2; // rdi\n __int64 v3; // rdx\n int v4; // eax\n _DWORD v6[258]; // [rsp+0h] [rbp-418h] BYREF\n unsigned __int64 v7; // [rsp+408h] [rbp-10h]\n\n v7 = __readfsqword(0x28u);\n memset(v6, 0, 0x400uLL);\n v1 = *a1;\n if ( (_BYTE)v1 )\n {\n v2 = a1 + 1;\n while ( 1 )\n {\n v3 = (char)v1;\n v4 = v6[(char)v1];\n if ( v4 == 1 )\n break;\n v1 = *v2++;\n v6[v3] = v4 + 1;\n if ( !(_BYTE)v1 )\n return 0;\n }\n }\n else\n {\n return 0;\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(unsigned char *a1) {\n unsigned int v1;\n unsigned char *v2;\n long long v3;\n int v4;\n uint32_t v6[258];\n unsigned long long v7;\n v7 = __readfsqword(40u);\n memset(v6, 0, 1024uLL);\n v1 = *a1;\n if ((uint8_t)v1) {\n v2 = a1 + 1;\n while (1) {\n v3 = (char)v1;\n v4 = v6[(char)v1];\n if (v4 == 1) break;\n v1 = *v2++;\n v6[v3] = v4 + 1;\n if (!(uint8_t)v1) return 0;\n }\n } else {\n return 0;\n }\n return v1;\n}", + "ida_pseudo_norm": "long long func0(unsigned char *a1) {\n unsigned int v1;\n unsigned char *v2;\n long long v3;\n int v4;\n uint32_t v6[258];\n unsigned long long v7;\n v7 = __readfsqword(40u);\n memset(v6, 0, 1024uLL);\n v1 = *a1;\n if ((uint8_t)v1) {\n v2 = a1 + 1;\n while (1) {\n v3 = (char)v1;\n v4 = v6[(char)v1];\n if (v4 == 1) break;\n v1 = *v2++;\n v6[v3] = v4 + 1;\n if (!(uint8_t)v1) return 0;\n }\n } else {\n return 0;\n }\n return v1;\n}" + }, + { + "index": 218, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int A, int B) {\n int temp;\n if (A > B) {\n temp = A;\n A = B;\n B = temp;\n }\n int gcd(int x, int y) {\n int t;\n while (y != 0) {\n t = y;\n y = x % y;\n x = t;\n }\n return x;\n }\n B = B / gcd(A, B);\n return B - 1;\n}", + "test": "int main() {\n\n assert(func0(2, 4) == 1);\n\n assert(func0(4, 10) == 4);\n\n assert(func0(1, 4) == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %edi,-0x24(%rbp)\nmov %esi,-0x28(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0x10(%rbp),%rax\nmov %rax,-0x10(%rbp)\nmov -0x24(%rbp),%eax\ncmp -0x28(%rbp),%eax\njle 11dd \nmov -0x24(%rbp),%eax\nmov %eax,-0x14(%rbp)\nmov -0x28(%rbp),%eax\nmov %eax,-0x24(%rbp)\nmov -0x14(%rbp),%eax\nmov %eax,-0x28(%rbp)\nmov -0x28(%rbp),%edx\nmov -0x24(%rbp),%eax\nlea -0x10(%rbp),%rcx\nmov %rcx,%r10\nmov %edx,%esi\nmov %eax,%edi\ncallq 1169 \nmov %eax,%esi\nmov -0x28(%rbp),%eax\ncltd\nidiv %esi\nmov %eax,-0x28(%rbp)\nmov -0x28(%rbp),%eax\nsub $0x1,%eax\nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 1218 \ncallq 1060 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_24], edi\nmov [rbp+var_28], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [rbp+arg_0]\nmov [rbp+var_10], rax\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_28]\njle short loc_11DD\nmov eax, [rbp+var_24]\nmov [rbp+var_14], eax\nmov eax, [rbp+var_28]\nmov [rbp+var_24], eax\nmov eax, [rbp+var_14]\nmov [rbp+var_28], eax\nloc_11DD:\nmov edx, [rbp+var_28]\nmov eax, [rbp+var_24]\nlea rcx, [rbp+var_10]\nmov r10, rcx\nmov esi, edx\nmov edi, eax\ncall gcd_0\nmov ecx, eax\nmov eax, [rbp+var_28]\ncdq\nidiv ecx\nmov [rbp+var_28], eax\nmov eax, [rbp+var_28]\nsub eax, 1\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1218\ncall ___stack_chk_fail\nlocret_1218:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(signed int a1, signed int a2)\n{\n unsigned int v3; // [rsp+8h] [rbp-28h]\n unsigned int v4; // [rsp+Ch] [rbp-24h]\n\n v4 = a1;\n v3 = a2;\n if ( a1 > a2 )\n {\n v4 = a2;\n v3 = a1;\n }\n return (unsigned int)((int)v3 / (int)gcd_0(v4, v3) - 1);\n}", + "ida_strip_asm": "sub_119A:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_24], edi\nmov [rbp+var_28], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [rbp+arg_0]\nmov [rbp+var_10], rax\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_28]\njle short loc_11DD\nmov eax, [rbp+var_24]\nmov [rbp+var_14], eax\nmov eax, [rbp+var_28]\nmov [rbp+var_24], eax\nmov eax, [rbp+var_14]\nmov [rbp+var_28], eax\nloc_11DD:\nmov edx, [rbp+var_28]\nmov eax, [rbp+var_24]\nlea rcx, [rbp+var_10]\nmov r10, rcx\nmov esi, edx\nmov edi, eax\ncall sub_1169\nmov ecx, eax\nmov eax, [rbp+var_28]\ncdq\nidiv ecx\nmov [rbp+var_28], eax\nmov eax, [rbp+var_28]\nsub eax, 1\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1218\ncall ___stack_chk_fail\nlocret_1218:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_119A(signed int a1, signed int a2)\n{\n unsigned int v3; // [rsp+8h] [rbp-28h]\n unsigned int v4; // [rsp+Ch] [rbp-24h]\n\n v4 = a1;\n v3 = a2;\n if ( a1 > a2 )\n {\n v4 = a2;\n v3 = a1;\n }\n return (unsigned int)((int)v3 / (int)sub_1169(v4, v3) - 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_119A(signed int a1, signed int a2) {\n unsigned int v3;\n unsigned int v4;\n v4 = a1;\n v3 = a2;\n if (a1 > a2) {\n v4 = a2;\n v3 = a1;\n }\n return (unsigned int)((int)v3 / (int)sub_1169(v4, v3) - 1);\n}", + "ida_pseudo_norm": "long long func0(signed int a1, signed int a2) {\n unsigned int v3;\n unsigned int v4;\n v4 = a1;\n v3 = a2;\n if (a1 > a2) {\n v4 = a2;\n v3 = a1;\n }\n return (unsigned int)((int)v3 / (int)gcd_0(v4, v3) - 1);\n}" + }, + { + "index": 218, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int A, int B) {\n int temp;\n if (A > B) {\n temp = A;\n A = B;\n B = temp;\n }\n int gcd(int x, int y) {\n int t;\n while (y != 0) {\n t = y;\n y = x % y;\n x = t;\n }\n return x;\n }\n B = B / gcd(A, B);\n return B - 1;\n}", + "test": "int main() {\n\n assert(func0(2, 4) == 1);\n\n assert(func0(4, 10) == 4);\n\n assert(func0(1, 4) == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %edi,%eax\ncmp %esi,%edi\njle 1157 \nmov %esi,%eax\nmov %edi,%esi\ntest %esi,%esi\nje 1173 \nmov %esi,%ecx\nmov %ecx,%edi\ncltd\nidiv %ecx\nmov %edx,%ecx\nmov %edi,%eax\ntest %edx,%edx\njne 115d \nmov %esi,%eax\ncltd\nidiv %edi\nsub $0x1,%eax\nretq\nmov %eax,%edi\njmp 116a \n", + "ida_asm": "func0:\nendbr64\nmov eax, esi\ncmp edi, esi\njg short loc_1157\nmov eax, edi\nmov edi, esi\nloc_1157:\ntest edi, edi\njz short loc_1173\nmov ecx, edi\nloc_115D:\nmov esi, ecx\ncdq\nidiv ecx\nmov ecx, edx\nmov eax, esi\ntest edx, edx\njnz short loc_115D\nloc_116A:\nmov eax, edi\ncdq\nidiv esi\nsub eax, 1\nretn\nloc_1173:\nmov esi, eax\njmp short loc_116A", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n int v2; // eax\n int v3; // ecx\n int v4; // esi\n\n v2 = a2;\n if ( a1 <= a2 )\n {\n v2 = a1;\n a1 = a2;\n }\n if ( a1 )\n {\n v3 = a1;\n do\n {\n v4 = v3;\n v3 = v2 % v3;\n v2 = v4;\n }\n while ( v3 );\n }\n else\n {\n v4 = v2;\n }\n return (unsigned int)(a1 / v4 - 1);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmov eax, esi\ncmp edi, esi\njg short loc_1157\nmov eax, edi\nmov edi, esi\nloc_1157:\ntest edi, edi\njz short loc_1173\nmov ecx, edi\nloc_115D:\nmov esi, ecx\ncdq\nidiv ecx\nmov ecx, edx\nmov eax, esi\ntest edx, edx\njnz short loc_115D\nloc_116A:\nmov eax, edi\ncdq\nidiv esi\nsub eax, 1\nretn\nloc_1173:\nmov esi, eax\njmp short loc_116A", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2)\n{\n int v2; // eax\n int v3; // ecx\n int v4; // esi\n\n v2 = a2;\n if ( a1 <= a2 )\n {\n v2 = a1;\n a1 = a2;\n }\n if ( a1 )\n {\n v3 = a1;\n do\n {\n v4 = v3;\n v3 = v2 % v3;\n v2 = v4;\n }\n while ( v3 );\n }\n else\n {\n v4 = v2;\n }\n return (unsigned int)(a1 / v4 - 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2) {\n int v2;\n int v3;\n int v4;\n v2 = a2;\n if (a1 <= a2) {\n v2 = a1;\n a1 = a2;\n }\n if (a1) {\n v3 = a1;\n do {\n v4 = v3;\n v3 = v2 % v3;\n v2 = v4;\n } while (v3);\n } else {\n v4 = v2;\n }\n return (unsigned int)(a1 / v4 - 1);\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n int v2;\n int v3;\n int v4;\n v2 = a2;\n if (a1 <= a2) {\n v2 = a1;\n a1 = a2;\n }\n if (a1) {\n v3 = a1;\n do {\n v4 = v3;\n v3 = v2 % v3;\n v2 = v4;\n } while (v3);\n } else {\n v4 = v2;\n }\n return (unsigned int)(a1 / v4 - 1);\n}" + }, + { + "index": 219, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n// Function to compare two integers for qsort\n\nint compare(const void *a, const void *b) {\n\n int int_a = *((int*) a);\n\n int int_b = *((int*) b);\n\n if (int_a < int_b) return -1;\n\n if (int_a > int_b) return 1;\n\n return 0;\n\n}\n\n\n\n", + "func": "int* func0(int* test_tup, int size, int K, int* res_size) {\n int* temp = (int*)malloc(size * sizeof(int));\n for (int i = 0; i < size; i++) {\n temp[i] = test_tup[i];\n }\n qsort(temp, size, sizeof(int), compare);\n if (2 * K > size) {\n *res_size = size;\n }\n else {\n *res_size = 2 * K;\n }\n int* res = (int*)malloc(*res_size * sizeof(int));\n int idx = 0;\n for (int i = 0; i < K && i < size; i++) {\n res[idx++] = temp[i];\n }\n for (int i = size - K; i < size; i++) {\n if (i >= K) {\n res[idx++] = temp[i];\n }\n }\n free(temp);\n return res;\n}", + "test": "int main() {\n\n // Test 1\n\n int test1[] = {5, 20, 3, 7, 6, 8};\n\n int expected1[] = {3, 5, 8, 20};\n\n int res_size1;\n\n int* res1 = func0(test1, 6, 2, &res_size1);\n\n assert(res_size1 == 4);\n\n for(int i = 0; i < res_size1; i++) {\n\n assert(res1[i] == expected1[i]);\n\n }\n\n free(res1);\n\n\n\n // Test 2\n\n int test2[] = {4, 5, 6, 1, 2, 7};\n\n int expected2[] = {1, 2, 4, 5, 6, 7};\n\n int res_size2;\n\n int* res2 = func0(test2, 6, 3, &res_size2);\n\n assert(res_size2 == 6);\n\n for(int i = 0; i < res_size2; i++) {\n\n assert(res2[i] == expected2[i]);\n\n }\n\n free(res2);\n\n\n\n // Test 3\n\n int test3[] = {2, 3, 4, 8, 9, 11, 7};\n\n int expected3[] = {2, 3, 4, 7, 8, 9, 11};\n\n int res_size3;\n\n int* res3 = func0(test3, 7, 4, &res_size3);\n\n assert(res_size3 == 7);\n\n for(int i = 0; i < res_size3; i++) {\n\n assert(res3[i] == expected3[i]);\n\n }\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x40,%rsp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmov %edx,-0x30(%rbp)\nmov %rcx,-0x38(%rbp)\nmov -0x2c(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,-0x10(%rbp)\nmovl $0x0,-0x20(%rbp)\njmp 1279 \nmov -0x20(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov -0x20(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x10(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x20(%rbp)\nmov -0x20(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 1248 \nmov -0x2c(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x10(%rbp),%rax\nlea -0xc9(%rip),%rcx\nmov $0x4,%edx\nmov %rax,%rdi\ncallq 10a0 \nmov -0x30(%rbp),%eax\nadd %eax,%eax\ncmp %eax,-0x2c(%rbp)\njge 12b4 \nmov -0x38(%rbp),%rax\nmov -0x2c(%rbp),%edx\nmov %edx,(%rax)\njmp 12c0 \nmov -0x30(%rbp),%eax\nlea (%rax,%rax,1),%edx\nmov -0x38(%rbp),%rax\nmov %edx,(%rax)\nmov -0x38(%rbp),%rax\nmov (%rax),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0x1c(%rbp)\nmovl $0x0,-0x18(%rbp)\njmp 131f \nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x10(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x1c(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x1c(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%eax\ncmp -0x30(%rbp),%eax\njge 132f \nmov -0x18(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 12e8 \nmov -0x2c(%rbp),%eax\nsub -0x30(%rbp),%eax\nmov %eax,-0x14(%rbp)\njmp 1379 \nmov -0x14(%rbp),%eax\ncmp -0x30(%rbp),%eax\njl 1375 \nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x10(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x1c(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x1c(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 133a \nmov -0x10(%rbp),%rax\nmov %rax,%rdi\ncallq 1090 \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_30], edx\nmov [rbp+var_38], rcx\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+base], rax\nmov [rbp+var_20], 0\njmp short loc_1279\nloc_1248:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+base]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_20], 1\nloc_1279:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_2C]\njl short loc_1248\nmov eax, [rbp+var_2C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compare\nmov rcx, rdx; compar\nmov edx, 4; size\nmov rdi, rax; base\ncall _qsort\nmov eax, [rbp+var_30]\nadd eax, eax\ncmp [rbp+var_2C], eax\njge short loc_12B7\nmov rax, [rbp+var_38]\nmov edx, [rbp+var_2C]\nmov [rax], edx\njmp short loc_12C3\nloc_12B7:\nmov eax, [rbp+var_30]\nlea edx, [rax+rax]\nmov rax, [rbp+var_38]\nmov [rax], edx\nloc_12C3:\nmov rax, [rbp+var_38]\nmov eax, [rax]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_1C], 0\nmov [rbp+var_18], 0\njmp short loc_1322\nloc_12EB:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_1C]\nlea edx, [rax+1]\nmov [rbp+var_1C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nadd [rbp+var_18], 1\nloc_1322:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_30]\njge short loc_1332\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_2C]\njl short loc_12EB\nloc_1332:\nmov eax, [rbp+var_2C]\nsub eax, [rbp+var_30]\nmov [rbp+var_14], eax\njmp short loc_137C\nloc_133D:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_30]\njl short loc_1378\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_1C]\nlea edx, [rax+1]\nmov [rbp+var_1C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_1378:\nadd [rbp+var_14], 1\nloc_137C:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl short loc_133D\nmov rax, [rbp+base]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, int a3, int *a4)\n{\n int v4; // eax\n int v5; // eax\n int i; // [rsp+20h] [rbp-20h]\n int v10; // [rsp+24h] [rbp-1Ch]\n int j; // [rsp+28h] [rbp-18h]\n int k; // [rsp+2Ch] [rbp-14h]\n _DWORD *base; // [rsp+30h] [rbp-10h]\n _DWORD *v14; // [rsp+38h] [rbp-8h]\n\n base = malloc(4LL * a2);\n for ( i = 0; i < a2; ++i )\n base[i] = *(_DWORD *)(4LL * i + a1);\n qsort(base, a2, 4uLL, compare);\n if ( a2 >= 2 * a3 )\n *a4 = 2 * a3;\n else\n *a4 = a2;\n v14 = malloc(4LL * *a4);\n v10 = 0;\n for ( j = 0; j < a3 && j < a2; ++j )\n {\n v4 = v10++;\n v14[v4] = base[j];\n }\n for ( k = a2 - a3; k < a2; ++k )\n {\n if ( k >= a3 )\n {\n v5 = v10++;\n v14[v5] = base[k];\n }\n }\n free(base);\n return v14;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_30], edx\nmov [rbp+var_38], rcx\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+base], rax\nmov [rbp+var_20], 0\njmp short loc_1279\nloc_1248:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+base]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_20], 1\nloc_1279:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_2C]\njl short loc_1248\nmov eax, [rbp+var_2C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 4; size\nmov rdi, rax; base\ncall _qsort\nmov eax, [rbp+var_30]\nadd eax, eax\ncmp [rbp+var_2C], eax\njge short loc_12B7\nmov rax, [rbp+var_38]\nmov edx, [rbp+var_2C]\nmov [rax], edx\njmp short loc_12C3\nloc_12B7:\nmov eax, [rbp+var_30]\nlea edx, [rax+rax]\nmov rax, [rbp+var_38]\nmov [rax], edx\nloc_12C3:\nmov rax, [rbp+var_38]\nmov eax, [rax]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_1C], 0\nmov [rbp+var_18], 0\njmp short loc_1322\nloc_12EB:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_1C]\nlea edx, [rax+1]\nmov [rbp+var_1C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nadd [rbp+var_18], 1\nloc_1322:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_30]\njge short loc_1332\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_2C]\njl short loc_12EB\nloc_1332:\nmov eax, [rbp+var_2C]\nsub eax, [rbp+var_30]\nmov [rbp+var_14], eax\njmp short loc_137C\nloc_133D:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_30]\njl short loc_1378\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_1C]\nlea edx, [rax+1]\nmov [rbp+var_1C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_1378:\nadd [rbp+var_14], 1\nloc_137C:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl short loc_133D\nmov rax, [rbp+base]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1210(__int64 a1, int a2, int a3, int *a4)\n{\n int v4; // eax\n int v5; // eax\n int i; // [rsp+20h] [rbp-20h]\n int v10; // [rsp+24h] [rbp-1Ch]\n int j; // [rsp+28h] [rbp-18h]\n int k; // [rsp+2Ch] [rbp-14h]\n _DWORD *base; // [rsp+30h] [rbp-10h]\n _DWORD *v14; // [rsp+38h] [rbp-8h]\n\n base = malloc(4LL * a2);\n for ( i = 0; i < a2; ++i )\n base[i] = *(_DWORD *)(4LL * i + a1);\n qsort(base, a2, 4uLL, compar);\n if ( a2 >= 2 * a3 )\n *a4 = 2 * a3;\n else\n *a4 = a2;\n v14 = malloc(4LL * *a4);\n v10 = 0;\n for ( j = 0; j < a3 && j < a2; ++j )\n {\n v4 = v10++;\n v14[v4] = base[j];\n }\n for ( k = a2 - a3; k < a2; ++k )\n {\n if ( k >= a3 )\n {\n v5 = v10++;\n v14[v5] = base[k];\n }\n }\n free(base);\n return v14;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1210(long long a1, int a2, int a3, int *a4) {\n int v4;\n int v5;\n int i;\n int v10;\n int j;\n int k;\n uint32_t *base;\n uint32_t *v14;\n base = malloc(4LL * a2);\n for (i = 0; i < a2; ++i) base[i] = *(uint32_t *)(4LL * i + a1);\n qsort(base, a2, 4uLL, compar);\n if (a2 >= 2 * a3)\n *a4 = 2 * a3;\n else\n *a4 = a2;\n v14 = malloc(4LL * *a4);\n v10 = 0;\n for (j = 0; j < a3 && j < a2; ++j) {\n v4 = v10++;\n v14[v4] = base[j];\n }\n for (k = a2 - a3; k < a2; ++k) {\n if (k >= a3) {\n v5 = v10++;\n v14[v5] = base[k];\n }\n }\n free(base);\n return v14;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, int a3, int *a4) {\n int v4;\n int v5;\n int i;\n int v10;\n int j;\n int k;\n uint32_t *base;\n uint32_t *v14;\n base = malloc(4LL * a2);\n for (i = 0; i < a2; ++i) base[i] = *(uint32_t *)(4LL * i + a1);\n qsort(base, a2, 4uLL, compare);\n if (a2 >= 2 * a3)\n *a4 = 2 * a3;\n else\n *a4 = a2;\n v14 = malloc(4LL * *a4);\n v10 = 0;\n for (j = 0; j < a3 && j < a2; ++j) {\n v4 = v10++;\n v14[v4] = base[j];\n }\n for (k = a2 - a3; k < a2; ++k) {\n if (k >= a3) {\n v5 = v10++;\n v14[v5] = base[k];\n }\n }\n free(base);\n return v14;\n}" + }, + { + "index": 219, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n// Function to compare two integers for qsort\n\nint compare(const void *a, const void *b) {\n\n int int_a = *((int*) a);\n\n int int_b = *((int*) b);\n\n if (int_a < int_b) return -1;\n\n if (int_a > int_b) return 1;\n\n return 0;\n\n}\n\n\n\n", + "func": "int* func0(int* test_tup, int size, int K, int* res_size) {\n int* temp = (int*)malloc(size * sizeof(int));\n for (int i = 0; i < size; i++) {\n temp[i] = test_tup[i];\n }\n qsort(temp, size, sizeof(int), compare);\n if (2 * K > size) {\n *res_size = size;\n }\n else {\n *res_size = 2 * K;\n }\n int* res = (int*)malloc(*res_size * sizeof(int));\n int idx = 0;\n for (int i = 0; i < K && i < size; i++) {\n res[idx++] = temp[i];\n }\n for (int i = size - K; i < size; i++) {\n if (i >= K) {\n res[idx++] = temp[i];\n }\n }\n free(temp);\n return res;\n}", + "test": "int main() {\n\n // Test 1\n\n int test1[] = {5, 20, 3, 7, 6, 8};\n\n int expected1[] = {3, 5, 8, 20};\n\n int res_size1;\n\n int* res1 = func0(test1, 6, 2, &res_size1);\n\n assert(res_size1 == 4);\n\n for(int i = 0; i < res_size1; i++) {\n\n assert(res1[i] == expected1[i]);\n\n }\n\n free(res1);\n\n\n\n // Test 2\n\n int test2[] = {4, 5, 6, 1, 2, 7};\n\n int expected2[] = {1, 2, 4, 5, 6, 7};\n\n int res_size2;\n\n int* res2 = func0(test2, 6, 3, &res_size2);\n\n assert(res_size2 == 6);\n\n for(int i = 0; i < res_size2; i++) {\n\n assert(res2[i] == expected2[i]);\n\n }\n\n free(res2);\n\n\n\n // Test 3\n\n int test3[] = {2, 3, 4, 8, 9, 11, 7};\n\n int expected3[] = {2, 3, 4, 7, 8, 9, 11};\n\n int res_size3;\n\n int* res3 = func0(test3, 7, 4, &res_size3);\n\n assert(res_size3 == 7);\n\n for(int i = 0; i < res_size3; i++) {\n\n assert(res3[i] == expected3[i]);\n\n }\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%r13\nmov %esi,%ebp\nmov %edx,%r12d\nmov %rcx,%r14\nmovslq %esi,%r15\nlea 0x0(,%r15,4),%rdi\ncallq 10d0 \nmov %rax,%rbx\ntest %ebp,%ebp\njle 1231 \nlea -0x1(%rbp),%ecx\nmov $0x0,%eax\nmov 0x0(%r13,%rax,4),%edx\nmov %edx,(%rbx,%rax,4)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rcx,%rdx\njne 121d \nlea -0x6f(%rip),%rcx\nmov $0x4,%edx\nmov %r15,%rsi\nmov %rbx,%rdi\ncallq 10a0 \nlea (%r12,%r12,1),%edi\ncmp %ebp,%edi\ncmovg %ebp,%edi\nmov %edi,(%r14)\nmovslq %edi,%rdi\nshl $0x2,%rdi\ncallq 10d0 \nmov %rax,%r13\ncmp %r12d,%ebp\nmov %r12d,%ecx\ncmovle %ebp,%ecx\ntest %ecx,%ecx\njle 1299 \nlea -0x1(%rcx),%esi\nmov $0x0,%eax\nmov (%rbx,%rax,4),%edx\nmov %edx,0x0(%r13,%rax,4)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rdx,%rsi\njne 1278 \nmov %ebp,%eax\nsub %r12d,%eax\ncmp %eax,%ebp\njle 12bd \ncltq\njmp 12a8 \nmov $0x0,%ecx\njmp 128c \nadd $0x1,%rax\ncmp %eax,%ebp\njle 12bd \ncmp %eax,%r12d\njg 12a0 \nmovslq %ecx,%rdx\nmov (%rbx,%rax,4),%esi\nmov %esi,0x0(%r13,%rdx,4)\nlea 0x1(%rcx),%ecx\njmp 12a0 \nmov %rbx,%rdi\ncallq 1090 \nmov %r13,%rax\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov r13, rdi\nmov ebp, esi\nmov r12d, edx\nmov [rsp+48h+var_40], rcx\nmovsxd r15, esi\nlea r14, ds:0[r15*4]\nmov rdi, r14; size\ncall _malloc\nmov rbx, rax\ntest ebp, ebp\njle loc_12C5\nmov eax, 0\nloc_1223:\nmov edx, [r13+rax+0]\nmov [rbx+rax], edx\nadd rax, 4\ncmp r14, rax\njnz short loc_1223\nlea rcx, compare; compar\nmov edx, 4; size\nmov rsi, r15; nmemb\nmov rdi, rbx; base\ncall _qsort\nlea edi, [r12+r12]\ncmp edi, ebp\ncmovg edi, ebp\nmov rax, [rsp+48h+var_40]\nmov [rax], edi\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov r13, rax\ncmp ebp, r12d\nmov ecx, r12d\ncmovle ecx, ebp\ntest ecx, ecx\njle short loc_12A1\nmovsxd rsi, ecx\nshl rsi, 2\nmov eax, 0\nloc_1283:\nmov edx, [rbx+rax]\nmov [r13+rax+0], edx\nadd rax, 4\ncmp rax, rsi\njnz short loc_1283\nloc_1294:\nmov eax, ebp\nsub eax, r12d\ncmp ebp, eax\njle short loc_1305\ncdqe\njmp short loc_12B0\nloc_12A1:\nmov ecx, 0\njmp short loc_1294\nloc_12A8:\nadd rax, 1\ncmp ebp, eax\njle short loc_1305\nloc_12B0:\ncmp r12d, eax\njg short loc_12A8\nmovsxd rdx, ecx\nmov esi, [rbx+rax*4]\nmov [r13+rdx*4+0], esi\nlea ecx, [rcx+1]\njmp short loc_12A8\nloc_12C5:\nlea rcx, compare; compar\nmov edx, 4; size\nmov rsi, r15; nmemb\nmov rdi, rax; base\ncall _qsort\nlea eax, [r12+r12]\ncmp eax, ebp\ncmovg eax, ebp\nmov rdi, [rsp+48h+var_40]\nmov [rdi], eax\ncdqe\nlea rdi, ds:0[rax*4]; size\ncall _malloc\nmov r13, rax\nmov ecx, 0\njmp short loc_1294\nloc_1305:\nmov rdi, rbx; ptr\ncall _free\nmov rax, r13\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, int a3, int *a4)\n{\n char *v5; // rax\n char *v6; // rbx\n __int64 v7; // rax\n int v8; // edi\n _DWORD *v9; // r13\n int v10; // ecx\n __int64 i; // rax\n __int64 v12; // rax\n int v13; // eax\n\n v5 = (char *)malloc(4LL * a2);\n v6 = v5;\n if ( a2 <= 0 )\n {\n qsort(v5, a2, 4uLL, compare);\n v13 = 2 * a3;\n if ( 2 * a3 > a2 )\n v13 = a2;\n *a4 = v13;\n v9 = malloc(4LL * v13);\n v10 = 0;\n }\n else\n {\n v7 = 0LL;\n do\n {\n *(_DWORD *)&v6[v7] = *(_DWORD *)(a1 + v7);\n v7 += 4LL;\n }\n while ( 4LL * a2 != v7 );\n qsort(v6, a2, 4uLL, compare);\n v8 = 2 * a3;\n if ( 2 * a3 > a2 )\n v8 = a2;\n *a4 = v8;\n v9 = malloc(4LL * v8);\n v10 = a3;\n if ( a2 <= a3 )\n v10 = a2;\n if ( v10 <= 0 )\n {\n v10 = 0;\n }\n else\n {\n for ( i = 0LL; i != v10; ++i )\n v9[i] = *(_DWORD *)&v6[i * 4];\n }\n }\n LODWORD(v12) = a2 - a3;\n if ( a2 > a2 - a3 )\n {\n v12 = (int)v12;\n do\n {\n if ( a3 <= (int)v12 )\n v9[v10++] = *(_DWORD *)&v6[4 * v12];\n ++v12;\n }\n while ( a2 > (int)v12 );\n }\n free(v6);\n return v9;\n}", + "ida_strip_asm": "sub_11E1:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov r13, rdi\nmov ebp, esi\nmov r12d, edx\nmov [rsp+48h+var_40], rcx\nmovsxd r15, esi\nlea r14, ds:0[r15*4]\nmov rdi, r14; size\ncall _malloc\nmov rbx, rax\ntest ebp, ebp\njle loc_12C5\nmov eax, 0\nloc_1223:\nmov edx, [r13+rax+0]\nmov [rbx+rax], edx\nadd rax, 4\ncmp r14, rax\njnz short loc_1223\nlea rcx, compar; compar\nmov edx, 4; size\nmov rsi, r15; nmemb\nmov rdi, rbx; base\ncall _qsort\nlea edi, [r12+r12]\ncmp edi, ebp\ncmovg edi, ebp\nmov rax, [rsp+48h+var_40]\nmov [rax], edi\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov r13, rax\ncmp ebp, r12d\nmov ecx, r12d\ncmovle ecx, ebp\ntest ecx, ecx\njle short loc_12A1\nmovsxd rsi, ecx\nshl rsi, 2\nmov eax, 0\nloc_1283:\nmov edx, [rbx+rax]\nmov [r13+rax+0], edx\nadd rax, 4\ncmp rax, rsi\njnz short loc_1283\nloc_1294:\nmov eax, ebp\nsub eax, r12d\ncmp ebp, eax\njle short loc_1305\ncdqe\njmp short loc_12B0\nloc_12A1:\nmov ecx, 0\njmp short loc_1294\nloc_12A8:\nadd rax, 1\ncmp ebp, eax\njle short loc_1305\nloc_12B0:\ncmp r12d, eax\njg short loc_12A8\nmovsxd rdx, ecx\nmov esi, [rbx+rax*4]\nmov [r13+rdx*4+0], esi\nlea ecx, [rcx+1]\njmp short loc_12A8\nloc_12C5:\nlea rcx, compar; compar\nmov edx, 4; size\nmov rsi, r15; nmemb\nmov rdi, rax; base\ncall _qsort\nlea eax, [r12+r12]\ncmp eax, ebp\ncmovg eax, ebp\nmov rdi, [rsp+48h+var_40]\nmov [rdi], eax\ncdqe\nlea rdi, ds:0[rax*4]; size\ncall _malloc\nmov r13, rax\nmov ecx, 0\njmp short loc_1294\nloc_1305:\nmov rdi, rbx; ptr\ncall _free\nmov rax, r13\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11E1(__int64 a1, int a2, int a3, int *a4)\n{\n char *v5; // rax\n char *v6; // rbx\n __int64 v7; // rax\n int v8; // edi\n _DWORD *v9; // r13\n int v10; // ecx\n __int64 i; // rax\n __int64 v12; // rax\n int v13; // eax\n\n v5 = (char *)malloc(4LL * a2);\n v6 = v5;\n if ( a2 <= 0 )\n {\n qsort(v5, a2, 4uLL, compar);\n v13 = 2 * a3;\n if ( 2 * a3 > a2 )\n v13 = a2;\n *a4 = v13;\n v9 = malloc(4LL * v13);\n v10 = 0;\n }\n else\n {\n v7 = 0LL;\n do\n {\n *(_DWORD *)&v6[v7] = *(_DWORD *)(a1 + v7);\n v7 += 4LL;\n }\n while ( 4LL * a2 != v7 );\n qsort(v6, a2, 4uLL, compar);\n v8 = 2 * a3;\n if ( 2 * a3 > a2 )\n v8 = a2;\n *a4 = v8;\n v9 = malloc(4LL * v8);\n v10 = a3;\n if ( a2 <= a3 )\n v10 = a2;\n if ( v10 <= 0 )\n {\n v10 = 0;\n }\n else\n {\n for ( i = 0LL; i != v10; ++i )\n v9[i] = *(_DWORD *)&v6[i * 4];\n }\n }\n LODWORD(v12) = a2 - a3;\n if ( a2 > a2 - a3 )\n {\n v12 = (int)v12;\n do\n {\n if ( a3 <= (int)v12 )\n v9[v10++] = *(_DWORD *)&v6[4 * v12];\n ++v12;\n }\n while ( a2 > (int)v12 );\n }\n free(v6);\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11E1(long long a1, int a2, int a3, int *a4) {\n char *v5;\n char *v6;\n long long v7;\n int v8;\n uint32_t *v9;\n int v10;\n long long i;\n long long v12;\n int v13;\n v5 = (char *)malloc(4LL * a2);\n v6 = v5;\n if (a2 <= 0) {\n qsort(v5, a2, 4uLL, compar);\n v13 = 2 * a3;\n if (2 * a3 > a2) v13 = a2;\n *a4 = v13;\n v9 = malloc(4LL * v13);\n v10 = 0;\n } else {\n v7 = 0LL;\n do {\n *(uint32_t *)&v6[v7] = *(uint32_t *)(a1 + v7);\n v7 += 4LL;\n } while (4LL * a2 != v7);\n qsort(v6, a2, 4uLL, compar);\n v8 = 2 * a3;\n if (2 * a3 > a2) v8 = a2;\n *a4 = v8;\n v9 = malloc(4LL * v8);\n v10 = a3;\n if (a2 <= a3) v10 = a2;\n if (v10 <= 0) {\n v10 = 0;\n } else {\n for (i = 0LL; i != v10; ++i) v9[i] = *(uint32_t *)&v6[i * 4];\n }\n }\n LODWORD(v12) = a2 - a3;\n if (a2 > a2 - a3) {\n v12 = (int)v12;\n do {\n if (a3 <= (int)v12) v9[v10++] = *(uint32_t *)&v6[4 * v12];\n ++v12;\n } while (a2 > (int)v12);\n }\n free(v6);\n return v9;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, int a3, int *a4) {\n char *v5;\n char *v6;\n long long v7;\n int v8;\n uint32_t *v9;\n int v10;\n long long i;\n long long v12;\n int v13;\n v5 = (char *)malloc(4LL * a2);\n v6 = v5;\n if (a2 <= 0) {\n qsort(v5, a2, 4uLL, compare);\n v13 = 2 * a3;\n if (2 * a3 > a2) v13 = a2;\n *a4 = v13;\n v9 = malloc(4LL * v13);\n v10 = 0;\n } else {\n v7 = 0LL;\n do {\n *(uint32_t *)&v6[v7] = *(uint32_t *)(a1 + v7);\n v7 += 4LL;\n } while (4LL * a2 != v7);\n qsort(v6, a2, 4uLL, compare);\n v8 = 2 * a3;\n if (2 * a3 > a2) v8 = a2;\n *a4 = v8;\n v9 = malloc(4LL * v8);\n v10 = a3;\n if (a2 <= a3) v10 = a2;\n if (v10 <= 0) {\n v10 = 0;\n } else {\n for (i = 0LL; i != v10; ++i) v9[i] = *(uint32_t *)&v6[i * 4];\n }\n }\n LODWORD(v12) = a2 - a3;\n if (a2 > a2 - a3) {\n v12 = (int)v12;\n do {\n if (a3 <= (int)v12) v9[v10++] = *(uint32_t *)&v6[4 * v12];\n ++v12;\n } while (a2 > (int)v12);\n }\n free(v6);\n return v9;\n}" + }, + { + "index": 219, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n// Function to compare two integers for qsort\n\nint compare(const void *a, const void *b) {\n\n int int_a = *((int*) a);\n\n int int_b = *((int*) b);\n\n if (int_a < int_b) return -1;\n\n if (int_a > int_b) return 1;\n\n return 0;\n\n}\n\n\n\n", + "func": "int* func0(int* test_tup, int size, int K, int* res_size) {\n int* temp = (int*)malloc(size * sizeof(int));\n for (int i = 0; i < size; i++) {\n temp[i] = test_tup[i];\n }\n qsort(temp, size, sizeof(int), compare);\n if (2 * K > size) {\n *res_size = size;\n }\n else {\n *res_size = 2 * K;\n }\n int* res = (int*)malloc(*res_size * sizeof(int));\n int idx = 0;\n for (int i = 0; i < K && i < size; i++) {\n res[idx++] = temp[i];\n }\n for (int i = size - K; i < size; i++) {\n if (i >= K) {\n res[idx++] = temp[i];\n }\n }\n free(temp);\n return res;\n}", + "test": "int main() {\n\n // Test 1\n\n int test1[] = {5, 20, 3, 7, 6, 8};\n\n int expected1[] = {3, 5, 8, 20};\n\n int res_size1;\n\n int* res1 = func0(test1, 6, 2, &res_size1);\n\n assert(res_size1 == 4);\n\n for(int i = 0; i < res_size1; i++) {\n\n assert(res1[i] == expected1[i]);\n\n }\n\n free(res1);\n\n\n\n // Test 2\n\n int test2[] = {4, 5, 6, 1, 2, 7};\n\n int expected2[] = {1, 2, 4, 5, 6, 7};\n\n int res_size2;\n\n int* res2 = func0(test2, 6, 3, &res_size2);\n\n assert(res_size2 == 6);\n\n for(int i = 0; i < res_size2; i++) {\n\n assert(res2[i] == expected2[i]);\n\n }\n\n free(res2);\n\n\n\n // Test 3\n\n int test3[] = {2, 3, 4, 8, 9, 11, 7};\n\n int expected3[] = {2, 3, 4, 7, 8, 9, 11};\n\n int res_size3;\n\n int* res3 = func0(test3, 7, 4, &res_size3);\n\n assert(res_size3 == 7);\n\n for(int i = 0; i < res_size3; i++) {\n\n assert(res3[i] == expected3[i]);\n\n }\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmovslq %esi,%r15\npush %r14\nmov %rdi,%r14\nlea 0x0(,%r15,4),%rdi\npush %r13\nmov %rcx,%r13\npush %r12\nmov %edx,%r12d\npush %rbp\npush %rbx\nmov %r15,%rbx\nsub $0x8,%rsp\ncallq 10d0 \nmov %rax,%rbp\ntest %r15d,%r15d\njle 1534 \nlea -0x1(%r15),%ecx\nxor %eax,%eax\nnopl 0x0(%rax)\nmov (%r14,%rax,4),%edx\nmov %edx,0x0(%rbp,%rax,4)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rcx,%rdx\njne 1520 \nlea -0x7b(%rip),%rcx\nmov $0x4,%edx\nmov %r15,%rsi\nmov %rbp,%rdi\ncallq 10a0 \nlea (%r12,%r12,1),%edi\ncmp %ebx,%edi\ncmovg %ebx,%edi\nmov %edi,0x0(%r13)\nmovslq %edi,%rdi\nshl $0x2,%rdi\ncallq 10d0 \ncmp %r12d,%ebx\nmov %rax,%r13\nmov %r12d,%eax\ncmovle %ebx,%eax\ntest %eax,%eax\njle 15e0 \nlea -0x1(%rax),%esi\nxor %edx,%edx\nnopl 0x0(%rax)\nmov 0x0(%rbp,%rdx,4),%ecx\nmov %ecx,0x0(%r13,%rdx,4)\nmov %rdx,%rcx\nadd $0x1,%rdx\ncmp %rcx,%rsi\njne 1580 \nmov %ebx,%edx\nsub %r12d,%edx\ncmp %edx,%ebx\njle 15c4 \nmovslq %edx,%rdx\nnopl 0x0(%rax)\ncmp %edx,%r12d\njg 15bc \nmov 0x0(%rbp,%rdx,4),%esi\nmovslq %eax,%rcx\nadd $0x1,%eax\nmov %esi,0x0(%r13,%rcx,4)\nadd $0x1,%rdx\ncmp %edx,%ebx\njg 15a8 \nmov %rbp,%rdi\ncallq 1090 \nadd $0x8,%rsp\nmov %r13,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nxchg %ax,%ax\nxor %eax,%eax\njmp 1595 \nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\nmovsxd r13, esi\npush r12\nmov r12d, edx\npush rbp\npush rbx\nmov rbx, r13\nsub rsp, 18h\nmov [rsp+48h+src], rdi\nlea rdi, ds:0[r13*4]; size\nmov [rsp+48h+var_48], rcx\ncall _malloc\nmov r15, rax\nlea eax, [r12+r12]\ncmp eax, r13d\ncmovg eax, r13d\nmovsxd rbp, eax\nmov r14, rbp\nshl rbp, 2\ntest r13d, r13d\njle loc_15A0\nmov rsi, [rsp+48h+src]; src\nmov edx, r13d\nmov rdi, r15; dest\nshl rdx, 2; n\ncall _memcpy\nmov rsi, r13; nmemb\nmov edx, 4; size\nmov rdi, r15; base\nlea rcx, compare; compar\ncall _qsort\nmov rax, [rsp+48h+var_48]\nmov rdi, rbp; size\nmov ebp, r12d\nmov [rax], r14d\ncall _malloc\ncmp ebx, r12d\ncmovle ebp, ebx\nmov r13, rax\ntest ebp, ebp\njle loc_15CD\nmov edx, ebp\nmov rsi, r15; src\nmov rdi, rax; dest\nshl rdx, 2; n\ncall _memcpy\nloc_1551:\nmov eax, ebx\nsub eax, r12d\nmovsxd rdx, eax\ncmp ebx, eax\njle short loc_157C\nnop dword ptr [rax]\nloc_1560:\ncmp r12d, edx\njg short loc_1574\nmov ecx, [r15+rdx*4]\nmovsxd rax, ebp\nadd ebp, 1\nmov [r13+rax*4+0], ecx\nloc_1574:\nadd rdx, 1\ncmp ebx, edx\njg short loc_1560\nloc_157C:\nmov rdi, r15; ptr\ncall _free\nadd rsp, 18h\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15A0:\nmov rsi, r13; nmemb\nlea rcx, compare; compar\nmov edx, 4; size\nmov rdi, r15; base\ncall _qsort\nmov rax, [rsp+48h+var_48]\nmov rdi, rbp; size\nxor ebp, ebp\nmov [rax], r14d\ncall _malloc\nmov r13, rax\njmp short loc_1551\nloc_15CD:\nxor ebp, ebp\njmp short loc_1551", + "ida_pseudo": "_DWORD *__fastcall func0(const void *a1, int a2, int a3, int *a4)\n{\n void *v5; // r15\n int v6; // eax\n int v7; // r14d\n __int64 v8; // rbp\n size_t v9; // rdi\n int v10; // ebp\n _DWORD *v11; // rax\n _DWORD *v12; // r13\n __int64 v13; // rdx\n __int64 v14; // rax\n size_t v16; // rdi\n\n v5 = malloc(4LL * a2);\n v6 = 2 * a3;\n if ( 2 * a3 > a2 )\n v6 = a2;\n v7 = v6;\n v8 = 4LL * v6;\n if ( a2 <= 0 )\n {\n qsort(v5, a2, 4uLL, compare);\n v16 = v8;\n v10 = 0;\n *a4 = v7;\n v12 = malloc(v16);\n }\n else\n {\n memcpy(v5, a1, 4LL * (unsigned int)a2);\n qsort(v5, a2, 4uLL, compare);\n v9 = v8;\n v10 = a3;\n *a4 = v7;\n v11 = malloc(v9);\n if ( a2 <= a3 )\n v10 = a2;\n v12 = v11;\n if ( v10 <= 0 )\n v10 = 0;\n else\n memcpy(v11, v5, 4LL * (unsigned int)v10);\n }\n v13 = a2 - a3;\n if ( a2 > a2 - a3 )\n {\n do\n {\n if ( a3 <= (int)v13 )\n {\n v14 = v10++;\n v12[v14] = *((_DWORD *)v5 + v13);\n }\n ++v13;\n }\n while ( a2 > (int)v13 );\n }\n free(v5);\n return v12;\n}", + "ida_strip_asm": "sub_14A0:\nendbr64\npush r15\npush r14\npush r13\nmovsxd r13, esi\npush r12\nmov r12d, edx\npush rbp\npush rbx\nmov rbx, r13\nsub rsp, 18h\nmov [rsp+48h+src], rdi\nlea rdi, ds:0[r13*4]; size\nmov [rsp+48h+var_48], rcx\ncall _malloc\nmov r15, rax\nlea eax, [r12+r12]\ncmp eax, r13d\ncmovg eax, r13d\nmovsxd rbp, eax\nmov r14, rbp\nshl rbp, 2\ntest r13d, r13d\njle loc_15A0\nmov rsi, [rsp+48h+src]; src\nmov edx, r13d\nmov rdi, r15; dest\nshl rdx, 2; n\ncall _memcpy\nmov rsi, r13; nmemb\nmov edx, 4; size\nmov rdi, r15; base\nlea rcx, compar; compar\ncall _qsort\nmov rax, [rsp+48h+var_48]\nmov rdi, rbp; size\nmov ebp, r12d\nmov [rax], r14d\ncall _malloc\ncmp ebx, r12d\ncmovle ebp, ebx\nmov r13, rax\ntest ebp, ebp\njle loc_15CD\nmov edx, ebp\nmov rsi, r15; src\nmov rdi, rax; dest\nshl rdx, 2; n\ncall _memcpy\nloc_1551:\nmov eax, ebx\nsub eax, r12d\nmovsxd rdx, eax\ncmp ebx, eax\njle short loc_157C\nnop dword ptr [rax]\nloc_1560:\ncmp r12d, edx\njg short loc_1574\nmov ecx, [r15+rdx*4]\nmovsxd rax, ebp\nadd ebp, 1\nmov [r13+rax*4+0], ecx\nloc_1574:\nadd rdx, 1\ncmp ebx, edx\njg short loc_1560\nloc_157C:\nmov rdi, r15; ptr\ncall _free\nadd rsp, 18h\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15A0:\nmov rsi, r13; nmemb\nlea rcx, compar; compar\nmov edx, 4; size\nmov rdi, r15; base\ncall _qsort\nmov rax, [rsp+48h+var_48]\nmov rdi, rbp; size\nxor ebp, ebp\nmov [rax], r14d\ncall _malloc\nmov r13, rax\njmp short loc_1551\nloc_15CD:\nxor ebp, ebp\njmp short loc_1551", + "ida_strip_pseudo": "_DWORD *__fastcall sub_14A0(const void *a1, int a2, int a3, int *a4)\n{\n void *v5; // r15\n int v6; // eax\n int v7; // r14d\n __int64 v8; // rbp\n size_t v9; // rdi\n int v10; // ebp\n _DWORD *v11; // rax\n _DWORD *v12; // r13\n __int64 v13; // rdx\n __int64 v14; // rax\n size_t v16; // rdi\n\n v5 = malloc(4LL * a2);\n v6 = 2 * a3;\n if ( 2 * a3 > a2 )\n v6 = a2;\n v7 = v6;\n v8 = 4LL * v6;\n if ( a2 <= 0 )\n {\n qsort(v5, a2, 4uLL, compar);\n v16 = v8;\n v10 = 0;\n *a4 = v7;\n v12 = malloc(v16);\n }\n else\n {\n memcpy(v5, a1, 4LL * (unsigned int)a2);\n qsort(v5, a2, 4uLL, compar);\n v9 = v8;\n v10 = a3;\n *a4 = v7;\n v11 = malloc(v9);\n if ( a2 <= a3 )\n v10 = a2;\n v12 = v11;\n if ( v10 <= 0 )\n v10 = 0;\n else\n memcpy(v11, v5, 4LL * (unsigned int)v10);\n }\n v13 = a2 - a3;\n if ( a2 > a2 - a3 )\n {\n do\n {\n if ( a3 <= (int)v13 )\n {\n v14 = v10++;\n v12[v14] = *((_DWORD *)v5 + v13);\n }\n ++v13;\n }\n while ( a2 > (int)v13 );\n }\n free(v5);\n return v12;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_14A0(const void *a1, int a2, int a3, int *a4) {\n void *v5;\n int v6;\n int v7;\n long long v8;\n unsigned int v9;\n int v10;\n uint32_t *v11;\n uint32_t *v12;\n long long v13;\n long long v14;\n unsigned int v16;\n v5 = malloc(4LL * a2);\n v6 = 2 * a3;\n if (2 * a3 > a2) v6 = a2;\n v7 = v6;\n v8 = 4LL * v6;\n if (a2 <= 0) {\n qsort(v5, a2, 4uLL, compar);\n v16 = v8;\n v10 = 0;\n *a4 = v7;\n v12 = malloc(v16);\n } else {\n memcpy(v5, a1, 4LL * (unsigned int)a2);\n qsort(v5, a2, 4uLL, compar);\n v9 = v8;\n v10 = a3;\n *a4 = v7;\n v11 = malloc(v9);\n if (a2 <= a3) v10 = a2;\n v12 = v11;\n if (v10 <= 0)\n v10 = 0;\n else\n memcpy(v11, v5, 4LL * (unsigned int)v10);\n }\n v13 = a2 - a3;\n if (a2 > a2 - a3) {\n do {\n if (a3 <= (int)v13) {\n v14 = v10++;\n v12[v14] = *((uint32_t *)v5 + v13);\n }\n ++v13;\n } while (a2 > (int)v13);\n }\n free(v5);\n return v12;\n}", + "ida_pseudo_norm": "uint32_t *func0(const void *a1, int a2, int a3, int *a4) {\n void *v5;\n int v6;\n int v7;\n long long v8;\n unsigned int v9;\n int v10;\n uint32_t *v11;\n uint32_t *v12;\n long long v13;\n long long v14;\n unsigned int v16;\n v5 = malloc(4LL * a2);\n v6 = 2 * a3;\n if (2 * a3 > a2) v6 = a2;\n v7 = v6;\n v8 = 4LL * v6;\n if (a2 <= 0) {\n qsort(v5, a2, 4uLL, compare);\n v16 = v8;\n v10 = 0;\n *a4 = v7;\n v12 = malloc(v16);\n } else {\n memcpy(v5, a1, 4LL * (unsigned int)a2);\n qsort(v5, a2, 4uLL, compare);\n v9 = v8;\n v10 = a3;\n *a4 = v7;\n v11 = malloc(v9);\n if (a2 <= a3) v10 = a2;\n v12 = v11;\n if (v10 <= 0)\n v10 = 0;\n else\n memcpy(v11, v5, 4LL * (unsigned int)v10);\n }\n v13 = a2 - a3;\n if (a2 > a2 - a3) {\n do {\n if (a3 <= (int)v13) {\n v14 = v10++;\n v12[v14] = *((uint32_t *)v5 + v13);\n }\n ++v13;\n } while (a2 > (int)v13);\n }\n free(v5);\n return v12;\n}" + }, + { + "index": 219, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n// Function to compare two integers for qsort\n\nint compare(const void *a, const void *b) {\n\n int int_a = *((int*) a);\n\n int int_b = *((int*) b);\n\n if (int_a < int_b) return -1;\n\n if (int_a > int_b) return 1;\n\n return 0;\n\n}\n\n\n\n", + "func": "int* func0(int* test_tup, int size, int K, int* res_size) {\n int* temp = (int*)malloc(size * sizeof(int));\n for (int i = 0; i < size; i++) {\n temp[i] = test_tup[i];\n }\n qsort(temp, size, sizeof(int), compare);\n if (2 * K > size) {\n *res_size = size;\n }\n else {\n *res_size = 2 * K;\n }\n int* res = (int*)malloc(*res_size * sizeof(int));\n int idx = 0;\n for (int i = 0; i < K && i < size; i++) {\n res[idx++] = temp[i];\n }\n for (int i = size - K; i < size; i++) {\n if (i >= K) {\n res[idx++] = temp[i];\n }\n }\n free(temp);\n return res;\n}", + "test": "int main() {\n\n // Test 1\n\n int test1[] = {5, 20, 3, 7, 6, 8};\n\n int expected1[] = {3, 5, 8, 20};\n\n int res_size1;\n\n int* res1 = func0(test1, 6, 2, &res_size1);\n\n assert(res_size1 == 4);\n\n for(int i = 0; i < res_size1; i++) {\n\n assert(res1[i] == expected1[i]);\n\n }\n\n free(res1);\n\n\n\n // Test 2\n\n int test2[] = {4, 5, 6, 1, 2, 7};\n\n int expected2[] = {1, 2, 4, 5, 6, 7};\n\n int res_size2;\n\n int* res2 = func0(test2, 6, 3, &res_size2);\n\n assert(res_size2 == 6);\n\n for(int i = 0; i < res_size2; i++) {\n\n assert(res2[i] == expected2[i]);\n\n }\n\n free(res2);\n\n\n\n // Test 3\n\n int test3[] = {2, 3, 4, 8, 9, 11, 7};\n\n int expected3[] = {2, 3, 4, 7, 8, 9, 11};\n\n int res_size3;\n\n int* res3 = func0(test3, 7, 4, &res_size3);\n\n assert(res_size3 == 7);\n\n for(int i = 0; i < res_size3; i++) {\n\n assert(res3[i] == expected3[i]);\n\n }\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmovslq %esi,%r15\npush %r14\npush %r13\nmov %edx,%r13d\npush %r12\nmov %rdi,%r12\nlea 0x0(,%r15,4),%rdi\npush %rbp\nmov %rcx,%rbp\npush %rbx\nmov %r15,%rbx\nsub $0x8,%rsp\ncallq 10f0 \nmov %rax,%r14\ntest %r15d,%r15d\njle 150d \nlea -0x1(%r15),%eax\nmov %r12,%rsi\nmov %r14,%rdi\nlea 0x4(,%rax,4),%rdx\ncallq 10e0 \nlea -0x74(%rip),%rcx\nmov $0x4,%edx\nmov %r15,%rsi\nmov %r14,%rdi\ncallq 10b0 \nlea 0x0(%r13,%r13,1),%edi\ncmp %ebx,%edi\ncmovg %ebx,%edi\nmov %edi,0x0(%rbp)\nmovslq %edi,%rdi\nmov %r13d,%ebp\nshl $0x2,%rdi\ncallq 10f0 \ncmp %r13d,%ebx\ncmovle %ebx,%ebp\nmov %rax,%r12\ntest %ebp,%ebp\njle 1680 \nlea -0x1(%rbp),%eax\nmov %r12,%rdi\nmov %r14,%rsi\nlea 0x4(,%rax,4),%rdx\ncallq 10e0 \nmovslq %ebp,%rdi\nmov %ebx,%eax\nsub %r13d,%eax\ncmp %eax,%ebx\njle 165d \ncmp %eax,%r13d\njle 1636 \nmov %ebp,%esi\nmov $0x1,%edx\nsub %eax,%esi\ncmp %ebp,%eax\ncmovge %edx,%esi\nlea -0x1(%rbp),%edx\nsub %eax,%edx\ncmp $0x7,%edx\njbe 15ef \ncmp %ebp,%eax\njge 15ef \nmovd %eax,%xmm4\nmov %esi,%ecx\nmovdqa 0xb26(%rip),%xmm3\nxor %edx,%edx\npshufd $0x0,%xmm4,%xmm1\nmovdqa 0xb27(%rip),%xmm2\npaddd 0xaff(%rip),%xmm1\nshr $0x2,%ecx\nnopl 0x0(%rax)\nmovdqa %xmm1,%xmm0\nadd $0x1,%edx\npaddd %xmm3,%xmm1\npaddd %xmm2,%xmm0\ncmp %edx,%ecx\njne 15c8 \nmov %esi,%ecx\npshufd $0xff,%xmm0,%xmm0\nand $0xfffffffc,%ecx\nmovd %xmm0,%edx\nadd %ecx,%eax\ncmp %esi,%ecx\nje 1630 \nlea 0x1(%rax),%edx\ncmp %ebp,%edx\njge 1630 \nlea 0x2(%rax),%edx\ncmp %ebp,%edx\njge 1630 \nlea 0x3(%rax),%edx\ncmp %edx,%ebp\njle 1630 \nlea 0x4(%rax),%edx\ncmp %edx,%ebp\njle 1630 \nlea 0x5(%rax),%edx\ncmp %edx,%ebp\njle 1630 \nlea 0x6(%rax),%edx\ncmp %edx,%ebp\njle 1630 \nlea 0x7(%rax),%edx\nadd $0x8,%eax\ncmp %edx,%ebp\ncmovle %edx,%eax\njmp 1632 \nnopw %cs:0x0(%rax,%rax,1)\nmov %edx,%eax\ncmp %eax,%ebx\njle 165d \nlea -0x1(%rbx),%edx\nmov $0x4,%ecx\nlea (%r12,%rdi,4),%rdi\nsub %eax,%edx\ncmp %eax,%ebx\ncltq\nlea 0x4(,%rdx,4),%rdx\nlea (%r14,%rax,4),%rsi\ncmovle %rcx,%rdx\ncallq 10e0 \nmov %r14,%rdi\ncallq 10a0 \nadd $0x8,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw 0x0(%rax,%rax,1)\nxor %edi,%edi\njmpq 156a \nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmovsxd rax, esi\nmov r15d, edx\npush r14\npush r13\nmov r13, rcx\npush r12\npush rbp\npush rbx\nmov rbx, rax\nsub rsp, 18h\nmov [rsp+48h+src], rdi\nlea rdi, ds:0[rax*4]; size\nmov [rsp+48h+nmemb], rax\ncall _malloc\nmov rbp, rax\nlea eax, [r15+r15]\ncmp eax, ebx\nmov r14d, eax\ncmovg r14d, ebx\nmovsxd r12, r14d\nshl r12, 2\ntest ebx, ebx\njle loc_1618\nmov rsi, [rsp+48h+src]; src\nmov edx, ebx\nmov rdi, rbp; dest\nshl rdx, 2; n\ncall _memcpy\nmov rsi, [rsp+48h+nmemb]; nmemb\nmov edx, 4; size\nmov rdi, rbp; base\nlea rcx, compare; compar\ncall _qsort\nmov [r13+0], r14d\nmov rdi, r12; size\nmov r13d, r15d\ncall _malloc\ncmp ebx, r15d\ncmovle r13d, ebx\nmov r12, rax\ntest r13d, r13d\njle loc_1675\nmov edx, r13d\nmov rsi, rbp; src\nmov rdi, rax; dest\nshl rdx, 2; n\ncall _memcpy\nloc_1522:\nmov eax, ebx\nsub eax, r15d\ncmp ebx, eax\njle loc_15DE\ncmp r15d, eax\njle short loc_15B3\ncmp ebx, r15d\nmov r8d, r15d\nmov esi, 1\ncmovle r8d, ebx\nmov edx, r8d\nsub edx, eax\ncmp eax, r8d\ncmovl esi, edx\nsub edx, 1\ncmp edx, 2\njbe loc_166E\ncmp eax, r8d\njge loc_166E\nmovd xmm3, eax\nmov ecx, esi\nmovdqa xmm2, cs:xmmword_20C0\nxor edx, edx\npshufd xmm0, xmm3, 0\npaddd xmm0, cs:xmmword_20B0\nshr ecx, 2\nnop dword ptr [rax+rax+00h]\nloc_1588:\nadd edx, 1\nmovdqa xmm1, xmm0\npaddd xmm0, xmm2\ncmp ecx, edx\njnz short loc_1588\nmov edx, esi\nand edx, 0FFFFFFFCh\nadd edx, eax\nand esi, 3\njz loc_1650\nloc_15A7:\nlea eax, [rdx+1]\ncmp r8d, eax\njg short loc_1600\ncmp ebx, eax\njle short loc_15DE\nloc_15B3:\nlea edx, [rbx-1]\nmov ecx, 4\nmovsxd r13, r13d\nsub edx, eax\ncmp ebx, eax\nlea rdi, [r12+r13*4]; dest\ncdqe\nlea rdx, ds:4[rdx*4]\nlea rsi, [rbp+rax*4+0]; src\ncmovle rdx, rcx; n\ncall _memcpy\nloc_15DE:\nmov rdi, rbp; ptr\ncall _free\nadd rsp, 18h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1600:\nlea eax, [rdx+2]\nadd edx, 3\ncmp eax, r8d\ncmovl eax, edx\ncmp ebx, eax\njg short loc_15B3\njmp short loc_15DE\nloc_1618:\nmov rsi, [rsp+48h+nmemb]; nmemb\nlea rcx, compare; compar\nmov edx, 4; size\nmov rdi, rbp; base\ncall _qsort\nmov [r13+0], r14d\nmov rdi, r12; size\nxor r13d, r13d\ncall _malloc\nmov r12, rax\njmp loc_1522\nloc_1650:\npaddd xmm1, cs:xmmword_20D0\npshufd xmm0, xmm1, 0FFh\nmovd eax, xmm0\ncmp ebx, eax\njg loc_15B3\njmp loc_15DE\nloc_166E:\nmov edx, eax\njmp loc_15A7\nloc_1675:\nxor r13d, r13d\njmp loc_1522", + "ida_pseudo": "char *__fastcall func0(const void *a1, int a2, signed int a3, int *a4)\n{\n char *v7; // rbp\n int v8; // r14d\n int v9; // r13d\n char *v10; // rax\n char *v11; // r12\n signed int v12; // eax\n signed int v13; // r8d\n unsigned int v14; // esi\n __m128i si128; // xmm2\n int v16; // edx\n __m128i v17; // xmm0\n __m128i v18; // xmm1\n unsigned int v19; // edx\n size_t v20; // rdx\n signed int v22; // edx\n\n v7 = (char *)malloc(4LL * a2);\n v8 = 2 * a3;\n if ( 2 * a3 > a2 )\n v8 = a2;\n if ( a2 <= 0 )\n {\n qsort(v7, a2, 4uLL, compare);\n *a4 = v8;\n v9 = 0;\n v11 = (char *)malloc(4LL * v8);\n }\n else\n {\n memcpy(v7, a1, 4LL * (unsigned int)a2);\n qsort(v7, a2, 4uLL, compare);\n *a4 = v8;\n v9 = a3;\n v10 = (char *)malloc(4LL * v8);\n if ( a2 <= a3 )\n v9 = a2;\n v11 = v10;\n if ( v9 <= 0 )\n v9 = 0;\n else\n memcpy(v10, v7, 4LL * (unsigned int)v9);\n }\n v12 = a2 - a3;\n if ( a2 <= a2 - a3 )\n goto LABEL_24;\n if ( a3 <= v12 )\n goto LABEL_21;\n v13 = a3;\n v14 = 1;\n if ( a2 <= a3 )\n v13 = a2;\n if ( v12 < v13 )\n v14 = v13 - v12;\n if ( (unsigned int)(v13 - v12 - 1) <= 2 || v12 >= v13 )\n {\n v19 = a2 - a3;\n }\n else\n {\n si128 = _mm_load_si128((const __m128i *)&xmmword_20C0);\n v16 = 0;\n v17 = _mm_add_epi32(_mm_shuffle_epi32(_mm_cvtsi32_si128(v12), 0), (__m128i)xmmword_20B0);\n do\n {\n ++v16;\n v18 = v17;\n v17 = _mm_add_epi32(v17, si128);\n }\n while ( v14 >> 2 != v16 );\n v19 = v12 + (v14 & 0xFFFFFFFC);\n if ( (v14 & 3) == 0 )\n {\n v12 = _mm_cvtsi128_si32(_mm_shuffle_epi32(_mm_add_epi32(v18, (__m128i)xmmword_20D0), 255));\n if ( a2 <= v12 )\n goto LABEL_24;\n goto LABEL_21;\n }\n }\n v12 = v19 + 1;\n if ( v13 <= (int)(v19 + 1) )\n {\n if ( a2 <= v12 )\n goto LABEL_24;\n goto LABEL_21;\n }\n v12 = v19 + 2;\n v22 = v19 + 3;\n if ( v12 < v13 )\n v12 = v22;\n if ( a2 > v12 )\n {\nLABEL_21:\n v20 = 4LL * (unsigned int)(a2 - 1 - v12) + 4;\n if ( a2 <= v12 )\n v20 = 4LL;\n memcpy(&v11[4 * v9], &v7[4 * v12], v20);\n }\nLABEL_24:\n free(v7);\n return v11;\n}", + "ida_strip_asm": "sub_1470:\nendbr64\npush r15\nmovsxd rax, esi\nmov r15d, edx\npush r14\npush r13\nmov r13, rcx\npush r12\npush rbp\npush rbx\nmov rbx, rax\nsub rsp, 18h\nmov [rsp+48h+src], rdi\nlea rdi, ds:0[rax*4]; size\nmov [rsp+48h+nmemb], rax\ncall _malloc\nmov rbp, rax\nlea eax, [r15+r15]\ncmp eax, ebx\nmov r14d, eax\ncmovg r14d, ebx\nmovsxd r12, r14d\nshl r12, 2\ntest ebx, ebx\njle loc_1618\nmov rsi, [rsp+48h+src]; src\nmov edx, ebx\nmov rdi, rbp; dest\nshl rdx, 2; n\ncall _memcpy\nmov rsi, [rsp+48h+nmemb]; nmemb\nmov edx, 4; size\nmov rdi, rbp; base\nlea rcx, compar; compar\ncall _qsort\nmov [r13+0], r14d\nmov rdi, r12; size\nmov r13d, r15d\ncall _malloc\ncmp ebx, r15d\ncmovle r13d, ebx\nmov r12, rax\ntest r13d, r13d\njle loc_1675\nmov edx, r13d\nmov rsi, rbp; src\nmov rdi, rax; dest\nshl rdx, 2; n\ncall _memcpy\nloc_1522:\nmov eax, ebx\nsub eax, r15d\ncmp ebx, eax\njle loc_15DE\ncmp r15d, eax\njle short loc_15B3\ncmp ebx, r15d\nmov r8d, r15d\nmov esi, 1\ncmovle r8d, ebx\nmov edx, r8d\nsub edx, eax\ncmp eax, r8d\ncmovl esi, edx\nsub edx, 1\ncmp edx, 2\njbe loc_166E\ncmp eax, r8d\njge loc_166E\nmovd xmm3, eax\nmov ecx, esi\nmovdqa xmm2, cs:xmmword_20C0\nxor edx, edx\npshufd xmm0, xmm3, 0\npaddd xmm0, cs:xmmword_20B0\nshr ecx, 2\nnop dword ptr [rax+rax+00h]\nloc_1588:\nadd edx, 1\nmovdqa xmm1, xmm0\npaddd xmm0, xmm2\ncmp ecx, edx\njnz short loc_1588\nmov edx, esi\nand edx, 0FFFFFFFCh\nadd edx, eax\nand esi, 3\njz loc_1650\nloc_15A7:\nlea eax, [rdx+1]\ncmp r8d, eax\njg short loc_1600\ncmp ebx, eax\njle short loc_15DE\nloc_15B3:\nlea edx, [rbx-1]\nmov ecx, 4\nmovsxd r13, r13d\nsub edx, eax\ncmp ebx, eax\nlea rdi, [r12+r13*4]; dest\ncdqe\nlea rdx, ds:4[rdx*4]\nlea rsi, [rbp+rax*4+0]; src\ncmovle rdx, rcx; n\ncall _memcpy\nloc_15DE:\nmov rdi, rbp; ptr\ncall _free\nadd rsp, 18h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1600:\nlea eax, [rdx+2]\nadd edx, 3\ncmp eax, r8d\ncmovl eax, edx\ncmp ebx, eax\njg short loc_15B3\njmp short loc_15DE\nloc_1618:\nmov rsi, [rsp+48h+nmemb]; nmemb\nlea rcx, compar; compar\nmov edx, 4; size\nmov rdi, rbp; base\ncall _qsort\nmov [r13+0], r14d\nmov rdi, r12; size\nxor r13d, r13d\ncall _malloc\nmov r12, rax\njmp loc_1522\nloc_1650:\npaddd xmm1, cs:xmmword_20D0\npshufd xmm0, xmm1, 0FFh\nmovd eax, xmm0\ncmp ebx, eax\njg loc_15B3\njmp loc_15DE\nloc_166E:\nmov edx, eax\njmp loc_15A7\nloc_1675:\nxor r13d, r13d\njmp loc_1522", + "ida_strip_pseudo": "char *__fastcall sub_1470(const void *a1, int a2, signed int a3, int *a4)\n{\n char *v7; // rbp\n int v8; // r14d\n int v9; // r13d\n char *v10; // rax\n char *v11; // r12\n signed int v12; // eax\n signed int v13; // r8d\n unsigned int v14; // esi\n __m128i si128; // xmm2\n int v16; // edx\n __m128i v17; // xmm0\n __m128i v18; // xmm1\n unsigned int v19; // edx\n size_t v20; // rdx\n signed int v22; // edx\n\n v7 = (char *)malloc(4LL * a2);\n v8 = 2 * a3;\n if ( 2 * a3 > a2 )\n v8 = a2;\n if ( a2 <= 0 )\n {\n qsort(v7, a2, 4uLL, compar);\n *a4 = v8;\n v9 = 0;\n v11 = (char *)malloc(4LL * v8);\n }\n else\n {\n memcpy(v7, a1, 4LL * (unsigned int)a2);\n qsort(v7, a2, 4uLL, compar);\n *a4 = v8;\n v9 = a3;\n v10 = (char *)malloc(4LL * v8);\n if ( a2 <= a3 )\n v9 = a2;\n v11 = v10;\n if ( v9 <= 0 )\n v9 = 0;\n else\n memcpy(v10, v7, 4LL * (unsigned int)v9);\n }\n v12 = a2 - a3;\n if ( a2 <= a2 - a3 )\n goto LABEL_24;\n if ( a3 <= v12 )\n goto LABEL_21;\n v13 = a3;\n v14 = 1;\n if ( a2 <= a3 )\n v13 = a2;\n if ( v12 < v13 )\n v14 = v13 - v12;\n if ( (unsigned int)(v13 - v12 - 1) <= 2 || v12 >= v13 )\n {\n v19 = a2 - a3;\n }\n else\n {\n si128 = _mm_load_si128((const __m128i *)&xmmword_20C0);\n v16 = 0;\n v17 = _mm_add_epi32(_mm_shuffle_epi32(_mm_cvtsi32_si128(v12), 0), (__m128i)xmmword_20B0);\n do\n {\n ++v16;\n v18 = v17;\n v17 = _mm_add_epi32(v17, si128);\n }\n while ( v14 >> 2 != v16 );\n v19 = v12 + (v14 & 0xFFFFFFFC);\n if ( (v14 & 3) == 0 )\n {\n v12 = _mm_cvtsi128_si32(_mm_shuffle_epi32(_mm_add_epi32(v18, (__m128i)xmmword_20D0), 255));\n if ( a2 <= v12 )\n goto LABEL_24;\n goto LABEL_21;\n }\n }\n v12 = v19 + 1;\n if ( v13 <= (int)(v19 + 1) )\n {\n if ( a2 <= v12 )\n goto LABEL_24;\n goto LABEL_21;\n }\n v12 = v19 + 2;\n v22 = v19 + 3;\n if ( v12 < v13 )\n v12 = v22;\n if ( a2 > v12 )\n {\nLABEL_21:\n v20 = 4LL * (unsigned int)(a2 - 1 - v12) + 4;\n if ( a2 <= v12 )\n v20 = 4LL;\n memcpy(&v11[4 * v9], &v7[4 * v12], v20);\n }\nLABEL_24:\n free(v7);\n return v11;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1470(const void *a1, int a2, signed int a3, int *a4) {\n char *v7;\n int v8;\n int v9;\n char *v10;\n char *v11;\n signed int v12;\n signed int v13;\n unsigned int v14;\n __m128i si128;\n int v16;\n __m128i v17;\n __m128i v18;\n unsigned int v19;\n unsigned int v20;\n signed int v22;\n v7 = (char *)malloc(4LL * a2);\n v8 = 2 * a3;\n if (2 * a3 > a2) v8 = a2;\n if (a2 <= 0) {\n qsort(v7, a2, 4uLL, compar);\n *a4 = v8;\n v9 = 0;\n v11 = (char *)malloc(4LL * v8);\n } else {\n memcpy(v7, a1, 4LL * (unsigned int)a2);\n qsort(v7, a2, 4uLL, compar);\n *a4 = v8;\n v9 = a3;\n v10 = (char *)malloc(4LL * v8);\n if (a2 <= a3) v9 = a2;\n v11 = v10;\n if (v9 <= 0)\n v9 = 0;\n else\n memcpy(v10, v7, 4LL * (unsigned int)v9);\n }\n v12 = a2 - a3;\n if (a2 <= a2 - a3) goto LABEL_24;\n if (a3 <= v12) goto LABEL_21;\n v13 = a3;\n v14 = 1;\n if (a2 <= a3) v13 = a2;\n if (v12 < v13) v14 = v13 - v12;\n if ((unsigned int)(v13 - v12 - 1) <= 2 || v12 >= v13) {\n v19 = a2 - a3;\n } else {\n si128 = _mm_load_si128((const __m128i *)&xmmword_20C0);\n v16 = 0;\n v17 = _mm_add_epi32(_mm_shuffle_epi32(_mm_cvtsi32_si128(v12), 0),\n (__m128i)xmmword_20B0);\n do {\n ++v16;\n v18 = v17;\n v17 = _mm_add_epi32(v17, si128);\n } while (v14 >> 2 != v16);\n v19 = v12 + (v14 & 4294967292);\n if ((v14 & 3) == 0) {\n v12 = _mm_cvtsi128_si32(\n _mm_shuffle_epi32(_mm_add_epi32(v18, (__m128i)xmmword_20D0), 255));\n if (a2 <= v12) goto LABEL_24;\n goto LABEL_21;\n }\n }\n v12 = v19 + 1;\n if (v13 <= (int)(v19 + 1)) {\n if (a2 <= v12) goto LABEL_24;\n goto LABEL_21;\n }\n v12 = v19 + 2;\n v22 = v19 + 3;\n if (v12 < v13) v12 = v22;\n if (a2 > v12) {\n LABEL_21:\n v20 = 4LL * (unsigned int)(a2 - 1 - v12) + 4;\n if (a2 <= v12) v20 = 4LL;\n memcpy(&v11[4 * v9], &v7[4 * v12], v20);\n }\nLABEL_24:\n free(v7);\n return v11;\n}", + "ida_pseudo_norm": "char *func0(const void *a1, int a2, signed int a3, int *a4) {\n char *v7;\n int v8;\n int v9;\n char *v10;\n char *v11;\n signed int v12;\n signed int v13;\n unsigned int v14;\n __m128i si128;\n int v16;\n __m128i v17;\n __m128i v18;\n unsigned int v19;\n unsigned int v20;\n signed int v22;\n v7 = (char *)malloc(4LL * a2);\n v8 = 2 * a3;\n if (2 * a3 > a2) v8 = a2;\n if (a2 <= 0) {\n qsort(v7, a2, 4uLL, compare);\n *a4 = v8;\n v9 = 0;\n v11 = (char *)malloc(4LL * v8);\n } else {\n memcpy(v7, a1, 4LL * (unsigned int)a2);\n qsort(v7, a2, 4uLL, compare);\n *a4 = v8;\n v9 = a3;\n v10 = (char *)malloc(4LL * v8);\n if (a2 <= a3) v9 = a2;\n v11 = v10;\n if (v9 <= 0)\n v9 = 0;\n else\n memcpy(v10, v7, 4LL * (unsigned int)v9);\n }\n v12 = a2 - a3;\n if (a2 <= a2 - a3) goto LABEL_24;\n if (a3 <= v12) goto LABEL_21;\n v13 = a3;\n v14 = 1;\n if (a2 <= a3) v13 = a2;\n if (v12 < v13) v14 = v13 - v12;\n if ((unsigned int)(v13 - v12 - 1) <= 2 || v12 >= v13) {\n v19 = a2 - a3;\n } else {\n si128 = _mm_load_si128((const __m128i *)&xmmword_20C0);\n v16 = 0;\n v17 = _mm_add_epi32(_mm_shuffle_epi32(_mm_cvtsi32_si128(v12), 0),\n (__m128i)xmmword_20B0);\n do {\n ++v16;\n v18 = v17;\n v17 = _mm_add_epi32(v17, si128);\n } while (v14 >> 2 != v16);\n v19 = v12 + (v14 & 4294967292);\n if ((v14 & 3) == 0) {\n v12 = _mm_cvtsi128_si32(\n _mm_shuffle_epi32(_mm_add_epi32(v18, (__m128i)xmmword_20D0), 255));\n if (a2 <= v12) goto LABEL_24;\n goto LABEL_21;\n }\n }\n v12 = v19 + 1;\n if (v13 <= (int)(v19 + 1)) {\n if (a2 <= v12) goto LABEL_24;\n goto LABEL_21;\n }\n v12 = v19 + 2;\n v22 = v19 + 3;\n if (v12 < v13) v12 = v22;\n if (a2 > v12) {\n LABEL_21:\n v20 = 4LL * (unsigned int)(a2 - 1 - v12) + 4;\n if (a2 <= v12) v20 = 4LL;\n memcpy(&v11[4 * v9], &v7[4 * v12], v20);\n }\nLABEL_24:\n free(v7);\n return v11;\n}" + }, + { + "index": 220, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char *func0(const char *text, int n) {\n regex_t regex;\n regmatch_t pmatch[1];\n static char new_text[256];\n strcpy(new_text, text);\n const char *pattern = \"[ ,.]\";\n regcomp(®ex, pattern, REG_EXTENDED);\n int num_replacements = 0;\n while (num_replacements < n && regexec(®ex, new_text, 1, pmatch, 0) == 0) {\n int start = pmatch[0].rm_so;\n new_text[start] = ':';\n num_replacements++;\n }\n regfree(®ex);\n return new_text;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"Python language, Programming language.\", 2), \"Python:language: Programming language.\") == 0);\n\n assert(strcmp(func0(\"a b c,d e f\", 3), \"a:b:c:d e f\") == 0);\n\n assert(strcmp(func0(\"ram reshma,ram rahim\", 1), \"ram:reshma,ram rahim\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x70,%rsp\nmov %rdi,-0x68(%rbp)\nmov %esi,-0x6c(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmov -0x68(%rbp),%rax\nmov %rax,%rsi\nlea 0x2e07(%rip),%rdi\ncallq 10b0 \nlea 0xdc3(%rip),%rax\nmov %rax,-0x58(%rbp)\nmov -0x58(%rbp),%rcx\nlea -0x50(%rbp),%rax\nmov $0x1,%edx\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 10f0 \nmovl $0x0,-0x60(%rbp)\njmp 1284 \nmov -0x10(%rbp),%eax\nmov %eax,-0x5c(%rbp)\nmov -0x5c(%rbp),%eax\ncltq\nlea 0x2dc4(%rip),%rdx\nmovb $0x3a,(%rax,%rdx,1)\naddl $0x1,-0x60(%rbp)\nmov -0x60(%rbp),%eax\ncmp -0x6c(%rbp),%eax\njge 12b5 \nlea -0x10(%rbp),%rdx\nlea -0x50(%rbp),%rax\nmov $0x0,%r8d\nmov %rdx,%rcx\nmov $0x1,%edx\nlea 0x2d97(%rip),%rsi\nmov %rax,%rdi\ncallq 1110 \ntest %eax,%eax\nje 126a \nlea -0x50(%rbp),%rax\nmov %rax,%rdi\ncallq 10c0 \nlea 0x2d78(%rip),%rax\nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 12dc \ncallq 10d0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+src], rdi\nmov [rbp+var_6C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, [rbp+src]\nmov rsi, rax; src\nlea rax, new_text_1\nmov rdi, rax; dest\ncall _strcpy\nlea rax, asc_2008; \"[ ,.]\"\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+var_60], 0\njmp short loc_1287\nloc_126D:\nmov eax, [rbp+pmatch.rm_so]\nmov [rbp+var_5C], eax\nmov eax, [rbp+var_5C]\ncdqe\nlea rdx, new_text_1\nmov byte ptr [rax+rdx], 3Ah ; ':'\nadd [rbp+var_60], 1\nloc_1287:\nmov eax, [rbp+var_60]\ncmp eax, [rbp+var_6C]\njge short loc_12B8\nlea rdx, [rbp+pmatch]\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov rcx, rdx; pmatch\nmov edx, 1; nmatch\nlea rsi, new_text_1; string\nmov rdi, rax; preg\ncall _regexec\ntest eax, eax\njz short loc_126D\nloc_12B8:\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nlea rax, new_text_1\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12DF\ncall ___stack_chk_fail\nlocret_12DF:\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(const char *a1, int a2)\n{\n int i; // [rsp+10h] [rbp-60h]\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n regmatch_t pmatch; // [rsp+60h] [rbp-10h] BYREF\n unsigned __int64 v6; // [rsp+68h] [rbp-8h]\n\n v6 = __readfsqword(0x28u);\n strcpy(new_text_1, a1);\n regcomp(&preg, \"[ ,.]\", 1);\n for ( i = 0; i < a2 && !regexec(&preg, new_text_1, 1uLL, &pmatch, 0); ++i )\n new_text_1[pmatch.rm_so] = 58;\n regfree(&preg);\n return new_text_1;\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+src], rdi\nmov [rbp+var_6C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, [rbp+src]\nmov rsi, rax; src\nlea rax, string\nmov rdi, rax; dest\ncall _strcpy\nlea rax, asc_2008; \"[ ,.]\"\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+var_60], 0\njmp short loc_1287\nloc_126D:\nmov eax, [rbp+pmatch.rm_so]\nmov [rbp+var_5C], eax\nmov eax, [rbp+var_5C]\ncdqe\nlea rdx, string\nmov byte ptr [rax+rdx], 3Ah ; ':'\nadd [rbp+var_60], 1\nloc_1287:\nmov eax, [rbp+var_60]\ncmp eax, [rbp+var_6C]\njge short loc_12B8\nlea rdx, [rbp+pmatch]\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov rcx, rdx; pmatch\nmov edx, 1; nmatch\nlea rsi, string; string\nmov rdi, rax; preg\ncall _regexec\ntest eax, eax\njz short loc_126D\nloc_12B8:\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nlea rax, string\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12DF\ncall ___stack_chk_fail\nlocret_12DF:\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1209(const char *a1, int a2)\n{\n int i; // [rsp+10h] [rbp-60h]\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n regmatch_t pmatch; // [rsp+60h] [rbp-10h] BYREF\n unsigned __int64 v6; // [rsp+68h] [rbp-8h]\n\n v6 = __readfsqword(0x28u);\n strcpy(string, a1);\n regcomp(&preg, \"[ ,.]\", 1);\n for ( i = 0; i < a2 && !regexec(&preg, string, 1uLL, &pmatch, 0); ++i )\n string[pmatch.rm_so] = 58;\n regfree(&preg);\n return string;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1209(const char *a1, int a2) {\n int i;\n regex_t preg;\n regmatch_t pmatch;\n unsigned long long v6;\n v6 = __readfsqword(40u);\n strcpy(string, a1);\n regcomp(&preg, \"[ ,.]\", 1);\n for (i = 0; i < a2 && !regexec(&preg, string, 1uLL, &pmatch, 0); ++i)\n string[pmatch.rm_so] = 58;\n regfree(&preg);\n return string;\n}", + "ida_pseudo_norm": "char *func0(const char *a1, int a2) {\n int i;\n regex_t preg;\n regmatch_t pmatch;\n unsigned long long v6;\n v6 = __readfsqword(40u);\n strcpy(new_text_1, a1);\n regcomp(&preg, \"[ ,.]\", 1);\n for (i = 0; i < a2 && !regexec(&preg, new_text_1, 1uLL, &pmatch, 0); ++i)\n new_text_1[pmatch.rm_so] = 58;\n regfree(&preg);\n return new_text_1;\n}" + }, + { + "index": 220, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char *func0(const char *text, int n) {\n regex_t regex;\n regmatch_t pmatch[1];\n static char new_text[256];\n strcpy(new_text, text);\n const char *pattern = \"[ ,.]\";\n regcomp(®ex, pattern, REG_EXTENDED);\n int num_replacements = 0;\n while (num_replacements < n && regexec(®ex, new_text, 1, pmatch, 0) == 0) {\n int start = pmatch[0].rm_so;\n new_text[start] = ':';\n num_replacements++;\n }\n regfree(®ex);\n return new_text;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"Python language, Programming language.\", 2), \"Python:language: Programming language.\") == 0);\n\n assert(strcmp(func0(\"a b c,d e f\", 3), \"a:b:c:d e f\") == 0);\n\n assert(strcmp(func0(\"ram reshma,ram rahim\", 1), \"ram:reshma,ram rahim\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nsub $0x50,%rsp\nmov %esi,%ebp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov $0x100,%edx\nmov %rdi,%rsi\nlea 0x2e2a(%rip),%rdi\ncallq 10f0 <__strcpy_chk@plt>\nmov %rsp,%rdi\nmov $0x1,%edx\nlea 0xdda(%rip),%rsi\ncallq 10d0 \nmov $0x0,%ebx\nlea 0x40(%rsp),%r12\ntest %ebp,%ebp\njle 1275 \nmov %rsp,%rdi\nmov $0x0,%r8d\nmov %r12,%rcx\nmov $0x1,%edx\nlea 0x2deb(%rip),%rsi\ncallq 10e0 \ntest %eax,%eax\njne 1275 \nmovslq 0x40(%rsp),%rax\nlea 0x2dd6(%rip),%rdx\nmovb $0x3a,(%rdx,%rax,1)\nadd $0x1,%ebx\ncmp %ebx,%ebp\njne 123d \nmov %rsp,%rdi\ncallq 10a0 \nmov 0x48(%rsp),%rax\nxor %fs:0x28,%rax\njne 129d \nlea 0x2dac(%rip),%rax\nadd $0x50,%rsp\npop %rbx\npop %rbp\npop %r12\nretq\ncallq 10b0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 50h\nmov r12d, esi\nmov rax, fs:28h\nmov [rsp+68h+var_20], rax\nxor eax, eax\nmov edx, 100h\nmov rsi, rdi\nlea rdi, new_text_1\ncall ___strcpy_chk\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"[ ,.]\"\ncall _regcomp\nmov ebx, 0\nlea rbp, new_text_1\ntest r12d, r12d\njle short loc_1292\nloc_1261:\nlea rcx, [rsp+68h+pmatch]; pmatch\nmov rdi, rsp; preg\nmov r8d, 0; eflags\nmov edx, 1; nmatch\nmov rsi, rbp; string\ncall _regexec\ntest eax, eax\njnz short loc_1292\nmovsxd rax, [rsp+68h+pmatch.rm_so]\nmov byte ptr [rbp+rax+0], 3Ah ; ':'\nadd ebx, 1\ncmp r12d, ebx\njnz short loc_1261\nloc_1292:\nmov rdi, rsp; preg\ncall _regfree\nmov rax, [rsp+68h+var_20]\nsub rax, fs:28h\njnz short loc_12BA\nlea rax, new_text_1\nadd rsp, 50h\npop rbx\npop rbp\npop r12\nretn\nloc_12BA:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2)\n{\n int v2; // ebx\n regex_t v4; // [rsp+0h] [rbp-68h] BYREF\n regmatch_t pmatch; // [rsp+40h] [rbp-28h] BYREF\n unsigned __int64 v6; // [rsp+48h] [rbp-20h]\n\n v6 = __readfsqword(0x28u);\n __strcpy_chk(new_text_1, a1, 256LL);\n regcomp(&v4, \"[ ,.]\", 1);\n v2 = 0;\n if ( a2 > 0 )\n {\n do\n {\n if ( regexec(&v4, new_text_1, 1uLL, &pmatch, 0) )\n break;\n new_text_1[pmatch.rm_so] = 58;\n ++v2;\n }\n while ( a2 != v2 );\n }\n regfree(&v4);\n return new_text_1;\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 50h\nmov r12d, esi\nmov rax, fs:28h\nmov [rsp+68h+var_20], rax\nxor eax, eax\nmov edx, 100h\nmov rsi, rdi\nlea rdi, string\ncall ___strcpy_chk\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"[ ,.]\"\ncall _regcomp\nmov ebx, 0\nlea rbp, string\ntest r12d, r12d\njle short loc_1292\nloc_1261:\nlea rcx, [rsp+68h+pmatch]; pmatch\nmov rdi, rsp; preg\nmov r8d, 0; eflags\nmov edx, 1; nmatch\nmov rsi, rbp; string\ncall _regexec\ntest eax, eax\njnz short loc_1292\nmovsxd rax, [rsp+68h+pmatch.rm_so]\nmov byte ptr [rbp+rax+0], 3Ah ; ':'\nadd ebx, 1\ncmp r12d, ebx\njnz short loc_1261\nloc_1292:\nmov rdi, rsp; preg\ncall _regfree\nmov rax, [rsp+68h+var_20]\nsub rax, fs:28h\njnz short loc_12BA\nlea rax, string\nadd rsp, 50h\npop rbx\npop rbp\npop r12\nretn\nloc_12BA:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_1209(__int64 a1, int a2)\n{\n int v2; // ebx\n regex_t v4; // [rsp+0h] [rbp-68h] BYREF\n regmatch_t pmatch; // [rsp+40h] [rbp-28h] BYREF\n unsigned __int64 v6; // [rsp+48h] [rbp-20h]\n\n v6 = __readfsqword(0x28u);\n __strcpy_chk(string, a1, 256LL);\n regcomp(&v4, \"[ ,.]\", 1);\n v2 = 0;\n if ( a2 > 0 )\n {\n do\n {\n if ( regexec(&v4, string, 1uLL, &pmatch, 0) )\n break;\n string[pmatch.rm_so] = 58;\n ++v2;\n }\n while ( a2 != v2 );\n }\n regfree(&v4);\n return string;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char* sub_1209(long long a1, int a2) {\n int v2;\n regex_t v4;\n regmatch_t pmatch;\n unsigned long long v6;\n v6 = __readfsqword(40u);\n __strcpy_chk(string, a1, 256LL);\n regcomp(&v4, \"[ ,.]\", 1);\n v2 = 0;\n if (a2 > 0) {\n do {\n if (regexec(&v4, string, 1uLL, &pmatch, 0)) break;\n string[pmatch.rm_so] = 58;\n ++v2;\n } while (a2 != v2);\n }\n regfree(&v4);\n return string;\n}", + "ida_pseudo_norm": "char* func0(long long a1, int a2) {\n int v2;\n regex_t v4;\n regmatch_t pmatch;\n unsigned long long v6;\n v6 = __readfsqword(40u);\n __strcpy_chk(new_text_1, a1, 256LL);\n regcomp(&v4, \"[ ,.]\", 1);\n v2 = 0;\n if (a2 > 0) {\n do {\n if (regexec(&v4, new_text_1, 1uLL, &pmatch, 0)) break;\n new_text_1[pmatch.rm_so] = 58;\n ++v2;\n } while (a2 != v2);\n }\n regfree(&v4);\n return new_text_1;\n}" + }, + { + "index": 220, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char *func0(const char *text, int n) {\n regex_t regex;\n regmatch_t pmatch[1];\n static char new_text[256];\n strcpy(new_text, text);\n const char *pattern = \"[ ,.]\";\n regcomp(®ex, pattern, REG_EXTENDED);\n int num_replacements = 0;\n while (num_replacements < n && regexec(®ex, new_text, 1, pmatch, 0) == 0) {\n int start = pmatch[0].rm_so;\n new_text[start] = ':';\n num_replacements++;\n }\n regfree(®ex);\n return new_text;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"Python language, Programming language.\", 2), \"Python:language: Programming language.\") == 0);\n\n assert(strcmp(func0(\"a b c,d e f\", 3), \"a:b:c:d e f\") == 0);\n\n assert(strcmp(func0(\"ram reshma,ram rahim\", 1), \"ram:reshma,ram rahim\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmov $0x100,%edx\npush %r14\npush %r13\npush %r12\npush %rbp\nmov %esi,%ebp\nmov %rdi,%rsi\nlea 0x2d42(%rip),%rdi\npush %rbx\nsub $0x58,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%r15\ncallq 10f0 <__strcpy_chk@plt>\nmov $0x1,%edx\nlea 0xcdd(%rip),%rsi\nmov %r15,%rdi\ncallq 10d0 \ntest %ebp,%ebp\njle 137b \nlea 0x2d06(%rip),%r12\nxor %ebx,%ebx\nlea 0x40(%rsp),%r14\nmov %r12,%r13\njmp 1361 \nnopw %cs:0x0(%rax,%rax,1)\nmovslq 0x40(%rsp),%rax\nadd $0x1,%ebx\nmovb $0x3a,(%r12,%rax,1)\ncmp %ebx,%ebp\nje 137b \nxor %r8d,%r8d\nmov %r14,%rcx\nmov $0x1,%edx\nmov %r13,%rsi\nmov %r15,%rdi\ncallq 10e0 \ntest %eax,%eax\nje 1350 \nmov %r15,%rdi\ncallq 10a0 \nmov 0x48(%rsp),%rax\nxor %fs:0x28,%rax\njne 13a9 \nadd $0x58,%rsp\nlea 0x2ca2(%rip),%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\ncallq 10b0 <__stack_chk_fail@plt>\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r14\nmov edx, 100h\npush r13\npush r12\nmov r12d, esi\nmov rsi, rdi\npush rbp\nlea rbp, new_text_1\npush rbx\nmov rdi, rbp\nxor ebx, ebx\nsub rsp, 50h\nmov rax, fs:28h\nmov [rsp+78h+var_30], rax\nxor eax, eax\nmov r13, rsp\nlea r14, [rsp+78h+pmatch]\ncall ___strcpy_chk\nmov edx, 1; cflags\nlea rsi, pattern; \"[ ,.]\"\nmov rdi, r13; preg\ncall _regcomp\ntest r12d, r12d\njg short loc_1362\njmp short loc_137C\nloc_1350:\nmovsxd rax, [rsp+78h+pmatch.rm_so]\nadd ebx, 1\nmov byte ptr [rbp+rax+0], 3Ah ; ':'\ncmp r12d, ebx\njz short loc_137C\nloc_1362:\nxor r8d, r8d; eflags\nmov rcx, r14; pmatch\nmov edx, 1; nmatch\nmov rsi, rbp; string\nmov rdi, r13; preg\ncall _regexec\ntest eax, eax\njz short loc_1350\nloc_137C:\nmov rdi, r13; preg\ncall _regfree\nmov rax, [rsp+78h+var_30]\nsub rax, fs:28h\njnz short loc_13A4\nadd rsp, 50h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_13A4:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2)\n{\n int v2; // ebx\n regex_t v4; // [rsp+0h] [rbp-78h] BYREF\n regmatch_t pmatch; // [rsp+40h] [rbp-38h] BYREF\n unsigned __int64 v6; // [rsp+48h] [rbp-30h]\n\n v2 = 0;\n v6 = __readfsqword(0x28u);\n __strcpy_chk(new_text_1, a1, 256LL);\n regcomp(&v4, \"[ ,.]\", 1);\n if ( a2 > 0 )\n {\n do\n {\n if ( regexec(&v4, new_text_1, 1uLL, &pmatch, 0) )\n break;\n ++v2;\n new_text_1[pmatch.rm_so] = 58;\n }\n while ( a2 != v2 );\n }\n regfree(&v4);\n return new_text_1;\n}", + "ida_strip_asm": "sub_12F0:\nendbr64\npush r14\nmov edx, 100h\npush r13\npush r12\nmov r12d, esi\nmov rsi, rdi\npush rbp\nlea rbp, string\npush rbx\nmov rdi, rbp\nxor ebx, ebx\nsub rsp, 50h\nmov rax, fs:28h\nmov [rsp+78h+var_30], rax\nxor eax, eax\nmov r13, rsp\nlea r14, [rsp+78h+pmatch]\ncall ___strcpy_chk\nmov edx, 1; cflags\nlea rsi, pattern; \"[ ,.]\"\nmov rdi, r13; preg\ncall _regcomp\ntest r12d, r12d\njg short loc_1362\njmp short loc_137C\nloc_1350:\nmovsxd rax, [rsp+78h+pmatch.rm_so]\nadd ebx, 1\nmov byte ptr [rbp+rax+0], 3Ah ; ':'\ncmp r12d, ebx\njz short loc_137C\nloc_1362:\nxor r8d, r8d; eflags\nmov rcx, r14; pmatch\nmov edx, 1; nmatch\nmov rsi, rbp; string\nmov rdi, r13; preg\ncall _regexec\ntest eax, eax\njz short loc_1350\nloc_137C:\nmov rdi, r13; preg\ncall _regfree\nmov rax, [rsp+78h+var_30]\nsub rax, fs:28h\njnz short loc_13A4\nadd rsp, 50h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_13A4:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_12F0(__int64 a1, int a2)\n{\n int v2; // ebx\n regex_t v4; // [rsp+0h] [rbp-78h] BYREF\n regmatch_t pmatch; // [rsp+40h] [rbp-38h] BYREF\n unsigned __int64 v6; // [rsp+48h] [rbp-30h]\n\n v2 = 0;\n v6 = __readfsqword(0x28u);\n __strcpy_chk(string, a1, 256LL);\n regcomp(&v4, \"[ ,.]\", 1);\n if ( a2 > 0 )\n {\n do\n {\n if ( regexec(&v4, string, 1uLL, &pmatch, 0) )\n break;\n ++v2;\n string[pmatch.rm_so] = 58;\n }\n while ( a2 != v2 );\n }\n regfree(&v4);\n return string;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char* sub_12F0(long long a1, int a2) {\n int v2;\n regex_t v4;\n regmatch_t pmatch;\n unsigned long long v6;\n v2 = 0;\n v6 = __readfsqword(40u);\n __strcpy_chk(string, a1, 256LL);\n regcomp(&v4, \"[ ,.]\", 1);\n if (a2 > 0) {\n do {\n if (regexec(&v4, string, 1uLL, &pmatch, 0)) break;\n ++v2;\n string[pmatch.rm_so] = 58;\n } while (a2 != v2);\n }\n regfree(&v4);\n return string;\n}", + "ida_pseudo_norm": "char* func0(long long a1, int a2) {\n int v2;\n regex_t v4;\n regmatch_t pmatch;\n unsigned long long v6;\n v2 = 0;\n v6 = __readfsqword(40u);\n __strcpy_chk(new_text_1, a1, 256LL);\n regcomp(&v4, \"[ ,.]\", 1);\n if (a2 > 0) {\n do {\n if (regexec(&v4, new_text_1, 1uLL, &pmatch, 0)) break;\n ++v2;\n new_text_1[pmatch.rm_so] = 58;\n } while (a2 != v2);\n }\n regfree(&v4);\n return new_text_1;\n}" + }, + { + "index": 220, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char *func0(const char *text, int n) {\n regex_t regex;\n regmatch_t pmatch[1];\n static char new_text[256];\n strcpy(new_text, text);\n const char *pattern = \"[ ,.]\";\n regcomp(®ex, pattern, REG_EXTENDED);\n int num_replacements = 0;\n while (num_replacements < n && regexec(®ex, new_text, 1, pmatch, 0) == 0) {\n int start = pmatch[0].rm_so;\n new_text[start] = ':';\n num_replacements++;\n }\n regfree(®ex);\n return new_text;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"Python language, Programming language.\", 2), \"Python:language: Programming language.\") == 0);\n\n assert(strcmp(func0(\"a b c,d e f\", 3), \"a:b:c:d e f\") == 0);\n\n assert(strcmp(func0(\"ram reshma,ram rahim\", 1), \"ram:reshma,ram rahim\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmov $0x100,%edx\npush %r14\npush %r13\npush %r12\npush %rbp\nmov %esi,%ebp\nmov %rdi,%rsi\nlea 0x2d42(%rip),%rdi\npush %rbx\nsub $0x58,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%r15\ncallq 10f0 <__strcpy_chk@plt>\nmov $0x1,%edx\nlea 0xcdd(%rip),%rsi\nmov %r15,%rdi\ncallq 10d0 \ntest %ebp,%ebp\njle 137b \nlea 0x2d06(%rip),%r12\nxor %ebx,%ebx\nlea 0x40(%rsp),%r14\nmov %r12,%r13\njmp 1361 \nnopw %cs:0x0(%rax,%rax,1)\nmovslq 0x40(%rsp),%rax\nadd $0x1,%ebx\nmovb $0x3a,(%r12,%rax,1)\ncmp %ebx,%ebp\nje 137b \nxor %r8d,%r8d\nmov %r14,%rcx\nmov $0x1,%edx\nmov %r13,%rsi\nmov %r15,%rdi\ncallq 10e0 \ntest %eax,%eax\nje 1350 \nmov %r15,%rdi\ncallq 10a0 \nmov 0x48(%rsp),%rax\nxor %fs:0x28,%rax\njne 13a9 \nadd $0x58,%rsp\nlea 0x2ca2(%rip),%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\ncallq 10b0 <__stack_chk_fail@plt>\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r14\nmov edx, 100h\npush r13\npush r12\nmov r12d, esi\nmov rsi, rdi\npush rbp\nlea rbp, new_text_1\npush rbx\nmov rdi, rbp\nxor ebx, ebx\nsub rsp, 50h\nmov rax, fs:28h\nmov [rsp+78h+var_30], rax\nxor eax, eax\nmov r13, rsp\nlea r14, [rsp+78h+pmatch]\ncall ___strcpy_chk\nmov edx, 1; cflags\nlea rsi, pattern; \"[ ,.]\"\nmov rdi, r13; preg\ncall _regcomp\ntest r12d, r12d\njg short loc_1362\njmp short loc_137C\nloc_1350:\nmovsxd rax, [rsp+78h+pmatch.rm_so]\nadd ebx, 1\nmov byte ptr [rbp+rax+0], 3Ah ; ':'\ncmp r12d, ebx\njz short loc_137C\nloc_1362:\nxor r8d, r8d; eflags\nmov rcx, r14; pmatch\nmov edx, 1; nmatch\nmov rsi, rbp; string\nmov rdi, r13; preg\ncall _regexec\ntest eax, eax\njz short loc_1350\nloc_137C:\nmov rdi, r13; preg\ncall _regfree\nmov rax, [rsp+78h+var_30]\nsub rax, fs:28h\njnz short loc_13A4\nadd rsp, 50h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_13A4:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2)\n{\n int v2; // ebx\n regex_t v4; // [rsp+0h] [rbp-78h] BYREF\n regmatch_t pmatch; // [rsp+40h] [rbp-38h] BYREF\n unsigned __int64 v6; // [rsp+48h] [rbp-30h]\n\n v2 = 0;\n v6 = __readfsqword(0x28u);\n __strcpy_chk(new_text_1, a1, 256LL);\n regcomp(&v4, \"[ ,.]\", 1);\n if ( a2 > 0 )\n {\n do\n {\n if ( regexec(&v4, new_text_1, 1uLL, &pmatch, 0) )\n break;\n ++v2;\n new_text_1[pmatch.rm_so] = 58;\n }\n while ( a2 != v2 );\n }\n regfree(&v4);\n return new_text_1;\n}", + "ida_strip_asm": "sub_12F0:\nendbr64\npush r14\nmov edx, 100h\npush r13\npush r12\nmov r12d, esi\nmov rsi, rdi\npush rbp\nlea rbp, string\npush rbx\nmov rdi, rbp\nxor ebx, ebx\nsub rsp, 50h\nmov rax, fs:28h\nmov [rsp+78h+var_30], rax\nxor eax, eax\nmov r13, rsp\nlea r14, [rsp+78h+pmatch]\ncall ___strcpy_chk\nmov edx, 1; cflags\nlea rsi, pattern; \"[ ,.]\"\nmov rdi, r13; preg\ncall _regcomp\ntest r12d, r12d\njg short loc_1362\njmp short loc_137C\nloc_1350:\nmovsxd rax, [rsp+78h+pmatch.rm_so]\nadd ebx, 1\nmov byte ptr [rbp+rax+0], 3Ah ; ':'\ncmp r12d, ebx\njz short loc_137C\nloc_1362:\nxor r8d, r8d; eflags\nmov rcx, r14; pmatch\nmov edx, 1; nmatch\nmov rsi, rbp; string\nmov rdi, r13; preg\ncall _regexec\ntest eax, eax\njz short loc_1350\nloc_137C:\nmov rdi, r13; preg\ncall _regfree\nmov rax, [rsp+78h+var_30]\nsub rax, fs:28h\njnz short loc_13A4\nadd rsp, 50h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_13A4:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_12F0(__int64 a1, int a2)\n{\n int v2; // ebx\n regex_t v4; // [rsp+0h] [rbp-78h] BYREF\n regmatch_t pmatch; // [rsp+40h] [rbp-38h] BYREF\n unsigned __int64 v6; // [rsp+48h] [rbp-30h]\n\n v2 = 0;\n v6 = __readfsqword(0x28u);\n __strcpy_chk(string, a1, 256LL);\n regcomp(&v4, \"[ ,.]\", 1);\n if ( a2 > 0 )\n {\n do\n {\n if ( regexec(&v4, string, 1uLL, &pmatch, 0) )\n break;\n ++v2;\n string[pmatch.rm_so] = 58;\n }\n while ( a2 != v2 );\n }\n regfree(&v4);\n return string;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char* sub_12F0(long long a1, int a2) {\n int v2;\n regex_t v4;\n regmatch_t pmatch;\n unsigned long long v6;\n v2 = 0;\n v6 = __readfsqword(40u);\n __strcpy_chk(string, a1, 256LL);\n regcomp(&v4, \"[ ,.]\", 1);\n if (a2 > 0) {\n do {\n if (regexec(&v4, string, 1uLL, &pmatch, 0)) break;\n ++v2;\n string[pmatch.rm_so] = 58;\n } while (a2 != v2);\n }\n regfree(&v4);\n return string;\n}", + "ida_pseudo_norm": "char* func0(long long a1, int a2) {\n int v2;\n regex_t v4;\n regmatch_t pmatch;\n unsigned long long v6;\n v2 = 0;\n v6 = __readfsqword(40u);\n __strcpy_chk(new_text_1, a1, 256LL);\n regcomp(&v4, \"[ ,.]\", 1);\n if (a2 > 0) {\n do {\n if (regexec(&v4, new_text_1, 1uLL, &pmatch, 0)) break;\n ++v2;\n new_text_1[pmatch.rm_so] = 58;\n } while (a2 != v2);\n }\n regfree(&v4);\n return new_text_1;\n}" + }, + { + "index": 221, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int nums[], int size) {\n for (int i = 0; i < size; i++) {\n if (nums[i] % 2 == 0) {\n return nums[i];\n }\n }\n return -1;\n}", + "test": "int main() {\n\n int nums1[] = {1, 3, 5, 7, 4, 1, 6, 8};\n\n int nums2[] = {2, 3, 4};\n\n int nums3[] = {5, 6, 7};\n\n assert(func0(nums1, 8) == 4);\n\n assert(func0(nums2, 3) == 2);\n\n assert(func0(nums3, 3) == 6);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11ba \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nand $0x1,%eax\ntest %eax,%eax\njne 11b6 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\njmp 11c7 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1181 \nmov $0xffffffff,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 0\njmp short loc_11BA\nloc_1181:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njnz short loc_11B6\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\njmp short loc_11C7\nloc_11B6:\nadd [rbp+var_4], 1\nloc_11BA:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1181\nmov eax, 0FFFFFFFFh\nloc_11C7:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n if ( (*(_DWORD *)(4LL * i + a1) & 1) == 0 )\n return *(unsigned int *)(4LL * i + a1);\n }\n return 0xFFFFFFFFLL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 0\njmp short loc_11BA\nloc_1181:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njnz short loc_11B6\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\njmp short loc_11C7\nloc_11B6:\nadd [rbp+var_4], 1\nloc_11BA:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1181\nmov eax, 0FFFFFFFFh\nloc_11C7:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n if ( (*(_DWORD *)(4LL * i + a1) & 1) == 0 )\n return *(unsigned int *)(4LL * i + a1);\n }\n return 0xFFFFFFFFLL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int i;\n for (i = 0; i < a2; ++i) {\n if ((*(uint32_t *)(4LL * i + a1) & 1) == 0)\n return *(unsigned int *)(4LL * i + a1);\n }\n return 4294967295LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int i;\n for (i = 0; i < a2; ++i) {\n if ((*(uint32_t *)(4LL * i + a1) & 1) == 0)\n return *(unsigned int *)(4LL * i + a1);\n }\n return 4294967295LL;\n}" + }, + { + "index": 221, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int nums[], int size) {\n for (int i = 0; i < size; i++) {\n if (nums[i] % 2 == 0) {\n return nums[i];\n }\n }\n return -1;\n}", + "test": "int main() {\n\n int nums1[] = {1, 3, 5, 7, 4, 1, 6, 8};\n\n int nums2[] = {2, 3, 4};\n\n int nums3[] = {5, 6, 7};\n\n assert(func0(nums1, 8) == 4);\n\n assert(func0(nums2, 3) == 2);\n\n assert(func0(nums3, 3) == 6);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1194 \nmov %rdi,%rax\nlea -0x1(%rsi),%edx\nlea 0x4(%rdi,%rdx,4),%rcx\nmov (%rax),%edx\ntest $0x1,%dl\nje 1191 \nadd $0x4,%rax\ncmp %rcx,%rax\njne 117c \nmov $0xffffffff,%edx\nmov %edx,%eax\nretq\nmov $0xffffffff,%edx\njmp 1191 \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1193\nmov rax, rdi\nmovsxd rsi, esi\nlea rcx, [rdi+rsi*4]\nloc_117B:\nmov edx, [rax]\ntest dl, 1\njz short loc_1190\nadd rax, 4\ncmp rax, rcx\njnz short loc_117B\nmov edx, 0FFFFFFFFh\nloc_1190:\nmov eax, edx\nretn\nloc_1193:\nmov edx, 0FFFFFFFFh\njmp short loc_1190", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n unsigned int *v2; // rax\n unsigned int v3; // edx\n\n if ( a2 <= 0 )\n {\n return (unsigned int)-1;\n }\n else\n {\n v2 = a1;\n while ( 1 )\n {\n v3 = *v2;\n if ( (*v2 & 1) == 0 )\n break;\n if ( ++v2 == &a1[a2] )\n return (unsigned int)-1;\n }\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_1193\nmov rax, rdi\nmovsxd rsi, esi\nlea rcx, [rdi+rsi*4]\nloc_117B:\nmov edx, [rax]\ntest dl, 1\njz short loc_1190\nadd rax, 4\ncmp rax, rcx\njnz short loc_117B\nmov edx, 0FFFFFFFFh\nloc_1190:\nmov eax, edx\nretn\nloc_1193:\nmov edx, 0FFFFFFFFh\njmp short loc_1190", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(unsigned int *a1, int a2)\n{\n unsigned int *v2; // rax\n unsigned int v3; // edx\n\n if ( a2 <= 0 )\n {\n return (unsigned int)-1;\n }\n else\n {\n v2 = a1;\n while ( 1 )\n {\n v3 = *v2;\n if ( (*v2 & 1) == 0 )\n break;\n if ( ++v2 == &a1[a2] )\n return (unsigned int)-1;\n }\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(unsigned int *a1, int a2) {\n unsigned int *v2;\n unsigned int v3;\n if (a2 <= 0) {\n return (unsigned int)-1;\n } else {\n v2 = a1;\n while (1) {\n v3 = *v2;\n if ((*v2 & 1) == 0) break;\n if (++v2 == &a1[a2]) return (unsigned int)-1;\n }\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n unsigned int *v2;\n unsigned int v3;\n if (a2 <= 0) {\n return (unsigned int)-1;\n } else {\n v2 = a1;\n while (1) {\n v3 = *v2;\n if ((*v2 & 1) == 0) break;\n if (++v2 == &a1[a2]) return (unsigned int)-1;\n }\n }\n return v3;\n}" + }, + { + "index": 222, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int* test_array, int size) {\n for (int i = 1; i < size; i++) {\n if (sizeof(test_array[i]) != sizeof(test_array[0])) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n int arr1[] = {5, 6, 7, 3, 5, 6};\n\n int arr2[] = {1, 2}; // Incomplete test, as third element is a string in Python.\n\n int arr3[] = {3, 2, 1, 4, 5};\n\n \n\n assert(func0(arr1, sizeof(arr1) / sizeof(arr1[0])) == true);\n\n // assert line for arr2 is omitted as C cannot handle mixed data types like Python tuples.\n\n assert(func0(arr3, sizeof(arr3) / sizeof(arr3[0])) == true);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x1,-0x4(%rbp)\njmp 1185 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1181 \nmov $0x1,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 1\njmp short loc_1185\nloc_1181:\nadd [rbp+var_4], 1\nloc_1185:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1181\nmov eax, 1\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-4h]\n\n for ( i = 1; i < a2; ++i )\n ;\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 1\njmp short loc_1185\nloc_1181:\nadd [rbp+var_4], 1\nloc_1185:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1181\nmov eax, 1\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-4h]\n\n for ( i = 1; i < a2; ++i )\n ;\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int i;\n for (i = 1; i < a2; ++i)\n ;\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int i;\n for (i = 1; i < a2; ++i)\n ;\n return 1LL;\n}" + }, + { + "index": 223, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nint binary_search(int arr[], int low, int high, int x) {\n\n while (high >= low) {\n\n int mid = (low + high) / 2;\n\n if ((mid == 0 || x > arr[mid - 1]) && (arr[mid] == x)) {\n\n return mid;\n\n } else if (x > arr[mid]) {\n\n low = mid + 1;\n\n } else {\n\n high = mid - 1;\n\n }\n\n }\n\n return -1;\n\n}\n\n\n\n", + "func": "bool func0(int arr[], int n, int x) {\n int i = binary_search(arr, 0, n - 1, x);\n if (i == -1) {\n return false;\n }\n if ((i + n / 2) <= (n - 1) && arr[i + n / 2] == x) {\n return true;\n } else {\n return false;\n }\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 3, 3, 3, 10};\n\n assert(func0(arr1, 7, 3) == true);\n\n\n\n int arr2[] = {1, 1, 2, 4, 4, 4, 6, 6};\n\n assert(func0(arr2, 8, 4) == false);\n\n\n\n int arr3[] = {1, 1, 1, 2, 2};\n\n assert(func0(arr3, 5, 1) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmov -0x1c(%rbp),%eax\nlea -0x1(%rax),%esi\nmov -0x20(%rbp),%edx\nmov -0x18(%rbp),%rax\nmov %edx,%ecx\nmov %esi,%edx\nmov $0x0,%esi\nmov %rax,%rdi\ncallq 1169 \nmov %eax,-0x4(%rbp)\ncmpl $0xffffffff,-0x4(%rbp)\njne 125e \nmov $0x0,%eax\njmp 12ad \nmov -0x1c(%rbp),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nmov %eax,%edx\nmov -0x4(%rbp),%eax\nadd %edx,%eax\ncmp %eax,-0x1c(%rbp)\njle 12a8 \nmov -0x1c(%rbp),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nmov %eax,%edx\nmov -0x4(%rbp),%eax\nadd %edx,%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x20(%rbp)\njne 12a8 \nmov $0x1,%eax\njmp 12ad \nmov $0x0,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov eax, [rbp+var_1C]\nlea esi, [rax-1]\nmov edx, [rbp+var_20]\nmov rax, [rbp+var_18]\nmov ecx, edx\nmov edx, esi\nmov esi, 0\nmov rdi, rax\ncall binary_search\nmov [rbp+var_4], eax\ncmp [rbp+var_4], 0FFFFFFFFh\njnz short loc_125E\nmov eax, 0\njmp short locret_12AD\nloc_125E:\nmov eax, [rbp+var_1C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov edx, eax\nmov eax, [rbp+var_4]\nadd eax, edx\ncmp [rbp+var_1C], eax\njle short loc_12A8\nmov eax, [rbp+var_1C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov edx, eax\nmov eax, [rbp+var_4]\nadd eax, edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njnz short loc_12A8\nmov eax, 1\njmp short locret_12AD\nloc_12A8:\nmov eax, 0\nlocret_12AD:\nleave\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(__int64 a1, int a2, unsigned int a3)\n{\n int v5; // [rsp+1Ch] [rbp-4h]\n\n v5 = binary_search(a1, 0LL, (unsigned int)(a2 - 1), a3);\n if ( v5 == -1 )\n return 0LL;\n return a2 > a2 / 2 + v5 && a3 == *(_DWORD *)(4LL * (a2 / 2 + v5) + a1);\n}", + "ida_strip_asm": "sub_121A:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov eax, [rbp+var_1C]\nlea esi, [rax-1]\nmov edx, [rbp+var_20]\nmov rax, [rbp+var_18]\nmov ecx, edx\nmov edx, esi\nmov esi, 0\nmov rdi, rax\ncall sub_1169\nmov [rbp+var_4], eax\ncmp [rbp+var_4], 0FFFFFFFFh\njnz short loc_125E\nmov eax, 0\njmp short locret_12AD\nloc_125E:\nmov eax, [rbp+var_1C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov edx, eax\nmov eax, [rbp+var_4]\nadd eax, edx\ncmp [rbp+var_1C], eax\njle short loc_12A8\nmov eax, [rbp+var_1C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov edx, eax\nmov eax, [rbp+var_4]\nadd eax, edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njnz short loc_12A8\nmov eax, 1\njmp short locret_12AD\nloc_12A8:\nmov eax, 0\nlocret_12AD:\nleave\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_121A(__int64 a1, int a2, unsigned int a3)\n{\n int v5; // [rsp+1Ch] [rbp-4h]\n\n v5 = sub_1169(a1, 0LL, (unsigned int)(a2 - 1), a3);\n if ( v5 == -1 )\n return 0LL;\n return a2 > a2 / 2 + v5 && a3 == *(_DWORD *)(4LL * (a2 / 2 + v5) + a1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_121A(long long a1, int a2, unsigned int a3) {\n int v5;\n v5 = sub_1169(a1, 0LL, (unsigned int)(a2 - 1), a3);\n if (v5 == -1) return 0LL;\n return a2 > a2 / 2 + v5 && a3 == *(uint32_t *)(4LL * (a2 / 2 + v5) + a1);\n}", + "ida_pseudo_norm": "uint8_t func0(long long a1, int a2, unsigned int a3) {\n int v5;\n v5 = binary_search(a1, 0LL, (unsigned int)(a2 - 1), a3);\n if (v5 == -1) return 0LL;\n return a2 > a2 / 2 + v5 && a3 == *(uint32_t *)(4LL * (a2 / 2 + v5) + a1);\n}" + }, + { + "index": 223, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nint binary_search(int arr[], int low, int high, int x) {\n\n while (high >= low) {\n\n int mid = (low + high) / 2;\n\n if ((mid == 0 || x > arr[mid - 1]) && (arr[mid] == x)) {\n\n return mid;\n\n } else if (x > arr[mid]) {\n\n low = mid + 1;\n\n } else {\n\n high = mid - 1;\n\n }\n\n }\n\n return -1;\n\n}\n\n\n\n", + "func": "bool func0(int arr[], int n, int x) {\n int i = binary_search(arr, 0, n - 1, x);\n if (i == -1) {\n return false;\n }\n if ((i + n / 2) <= (n - 1) && arr[i + n / 2] == x) {\n return true;\n } else {\n return false;\n }\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 3, 3, 3, 10};\n\n assert(func0(arr1, 7, 3) == true);\n\n\n\n int arr2[] = {1, 1, 2, 4, 4, 4, 6, 6};\n\n assert(func0(arr2, 8, 4) == false);\n\n\n\n int arr3[] = {1, 1, 1, 2, 2};\n\n assert(func0(arr3, 5, 1) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%r12\nmov %esi,%ebx\nmov %edx,%ebp\nlea -0x1(%rsi),%edx\nmov %ebp,%ecx\nmov $0x0,%esi\ncallq 1169 \nmov $0x0,%ecx\ncmp $0xffffffff,%eax\nje 1203 \nmov %eax,%edx\nmov %ebx,%eax\nshr $0x1f,%eax\nadd %ebx,%eax\nsar %eax\nadd %edx,%eax\ncmp %ebx,%eax\njge 1203 \ncltq\ncmp %ebp,(%r12,%rax,4)\nsete %cl\nmov %ecx,%eax\npop %rbx\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov r12, rdi\nmov ebx, esi\nmov ebp, edx\nlea edx, [rsi-1]\nmov ecx, ebp\nmov esi, 0\ncall binary_search\nmov edx, 0\ncmp eax, 0FFFFFFFFh\njz short loc_1208\nmov edx, ebx\nshr edx, 1Fh\nadd edx, ebx\nsar edx, 1\nadd eax, edx\nmov edx, 0\ncmp eax, ebx\njge short loc_1208\ncdqe\ncmp [r12+rax*4], ebp\nsetz dl\nloc_1208:\nmov eax, edx\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, unsigned int a3)\n{\n int v4; // eax\n unsigned int v5; // edx\n int v6; // eax\n\n v4 = binary_search(a1, 0LL, (unsigned int)(a2 - 1), a3);\n v5 = 0;\n if ( v4 != -1 )\n {\n v6 = a2 / 2 + v4;\n v5 = 0;\n if ( v6 < a2 )\n LOBYTE(v5) = *(_DWORD *)(a1 + 4LL * v6) == a3;\n }\n return v5;\n}", + "ida_strip_asm": "sub_11C3:\nendbr64\npush r12\npush rbp\npush rbx\nmov r12, rdi\nmov ebx, esi\nmov ebp, edx\nlea edx, [rsi-1]\nmov ecx, ebp\nmov esi, 0\ncall sub_1169\nmov edx, 0\ncmp eax, 0FFFFFFFFh\njz short loc_1208\nmov edx, ebx\nshr edx, 1Fh\nadd edx, ebx\nsar edx, 1\nadd eax, edx\nmov edx, 0\ncmp eax, ebx\njge short loc_1208\ncdqe\ncmp [r12+rax*4], ebp\nsetz dl\nloc_1208:\nmov eax, edx\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11C3(__int64 a1, int a2, unsigned int a3)\n{\n int v4; // eax\n unsigned int v5; // edx\n int v6; // eax\n\n v4 = sub_1169(a1, 0LL, (unsigned int)(a2 - 1), a3);\n v5 = 0;\n if ( v4 != -1 )\n {\n v6 = a2 / 2 + v4;\n v5 = 0;\n if ( v6 < a2 )\n LOBYTE(v5) = *(_DWORD *)(a1 + 4LL * v6) == a3;\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11C3(long long a1, int a2, unsigned int a3) {\n int v4;\n unsigned int v5;\n int v6;\n v4 = sub_1169(a1, 0LL, (unsigned int)(a2 - 1), a3);\n v5 = 0;\n if (v4 != -1) {\n v6 = a2 / 2 + v4;\n v5 = 0;\n if (v6 < a2) LOBYTE(v5) = *(uint32_t *)(a1 + 4LL * v6) == a3;\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, unsigned int a3) {\n int v4;\n unsigned int v5;\n int v6;\n v4 = binary_search(a1, 0LL, (unsigned int)(a2 - 1), a3);\n v5 = 0;\n if (v4 != -1) {\n v6 = a2 / 2 + v4;\n v5 = 0;\n if (v6 < a2) LOBYTE(v5) = *(uint32_t *)(a1 + 4LL * v6) == a3;\n }\n return v5;\n}" + }, + { + "index": 223, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nint binary_search(int arr[], int low, int high, int x) {\n\n while (high >= low) {\n\n int mid = (low + high) / 2;\n\n if ((mid == 0 || x > arr[mid - 1]) && (arr[mid] == x)) {\n\n return mid;\n\n } else if (x > arr[mid]) {\n\n low = mid + 1;\n\n } else {\n\n high = mid - 1;\n\n }\n\n }\n\n return -1;\n\n}\n\n\n\n", + "func": "bool func0(int arr[], int n, int x) {\n int i = binary_search(arr, 0, n - 1, x);\n if (i == -1) {\n return false;\n }\n if ((i + n / 2) <= (n - 1) && arr[i + n / 2] == x) {\n return true;\n } else {\n return false;\n }\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 3, 3, 3, 10};\n\n assert(func0(arr1, 7, 3) == true);\n\n\n\n int arr2[] = {1, 1, 2, 4, 4, 4, 6, 6};\n\n assert(func0(arr2, 8, 4) == false);\n\n\n\n int arr3[] = {1, 1, 1, 2, 2};\n\n assert(func0(arr3, 5, 1) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov %esi,%r11d\nmov %edx,%ecx\nlea -0x1(%rsi),%edx\nxor %esi,%esi\ncallq 12d0 \nxor %r8d,%r8d\nmov %eax,%edx\ncmp $0xffffffff,%eax\nje 1368 \nmov %r11d,%eax\nshr $0x1f,%eax\nadd %r11d,%eax\nsar %eax\nadd %edx,%eax\ncmp %r11d,%eax\njge 1368 \ncltq\ncmp %ecx,(%rdi,%rax,4)\nsete %r8b\nmov %r8d,%eax\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov ecx, edx\nmov r11d, esi\nlea edx, [rsi-1]\nxor esi, esi\nmov rbx, rdi\ncall binary_search\nxor esi, esi\ncmp eax, 0FFFFFFFFh\njz short loc_1339\nmov edx, r11d\nshr edx, 1Fh\nadd edx, r11d\nsar edx, 1\nadd eax, edx\ncmp eax, r11d\njge short loc_1339\ncdqe\ncmp [rbx+rax*4], ecx\nsetz sil\nloc_1339:\nmov eax, esi\npop rbx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, unsigned int a3)\n{\n int v3; // eax\n int v4; // ecx\n int v5; // r11d\n unsigned int v6; // esi\n int v7; // eax\n\n v3 = binary_search(a1, 0LL, (unsigned int)(a2 - 1), a3);\n v6 = 0;\n if ( v3 != -1 )\n {\n v7 = v5 / 2 + v3;\n if ( v7 < v5 )\n LOBYTE(v6) = *(_DWORD *)(a1 + 4LL * v7) == v4;\n }\n return v6;\n}", + "ida_strip_asm": "sub_1300:\nendbr64\npush rbx\nmov ecx, edx\nmov r11d, esi\nlea edx, [rsi-1]\nxor esi, esi\nmov rbx, rdi\ncall sub_12A0\nxor esi, esi\ncmp eax, 0FFFFFFFFh\njz short loc_1339\nmov edx, r11d\nshr edx, 1Fh\nadd edx, r11d\nsar edx, 1\nadd eax, edx\ncmp eax, r11d\njge short loc_1339\ncdqe\ncmp [rbx+rax*4], ecx\nsetz sil\nloc_1339:\nmov eax, esi\npop rbx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1300(__int64 a1, int a2, unsigned int a3)\n{\n int v3; // eax\n int v4; // ecx\n int v5; // r11d\n unsigned int v6; // esi\n int v7; // eax\n\n v3 = sub_12A0(a1, 0LL, (unsigned int)(a2 - 1), a3);\n v6 = 0;\n if ( v3 != -1 )\n {\n v7 = v5 / 2 + v3;\n if ( v7 < v5 )\n LOBYTE(v6) = *(_DWORD *)(a1 + 4LL * v7) == v4;\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1300(long long a1, int a2, unsigned int a3) {\n int v3;\n int v4;\n int v5;\n unsigned int v6;\n int v7;\n v3 = sub_12A0(a1, 0LL, (unsigned int)(a2 - 1), a3);\n v6 = 0;\n if (v3 != -1) {\n v7 = v5 / 2 + v3;\n if (v7 < v5) LOBYTE(v6) = *(uint32_t *)(a1 + 4LL * v7) == v4;\n }\n return v6;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, unsigned int a3) {\n int v3;\n int v4;\n int v5;\n unsigned int v6;\n int v7;\n v3 = binary_search(a1, 0LL, (unsigned int)(a2 - 1), a3);\n v6 = 0;\n if (v3 != -1) {\n v7 = v5 / 2 + v3;\n if (v7 < v5) LOBYTE(v6) = *(uint32_t *)(a1 + 4LL * v7) == v4;\n }\n return v6;\n}" + }, + { + "index": 223, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nint binary_search(int arr[], int low, int high, int x) {\n\n while (high >= low) {\n\n int mid = (low + high) / 2;\n\n if ((mid == 0 || x > arr[mid - 1]) && (arr[mid] == x)) {\n\n return mid;\n\n } else if (x > arr[mid]) {\n\n low = mid + 1;\n\n } else {\n\n high = mid - 1;\n\n }\n\n }\n\n return -1;\n\n}\n\n\n\n", + "func": "bool func0(int arr[], int n, int x) {\n int i = binary_search(arr, 0, n - 1, x);\n if (i == -1) {\n return false;\n }\n if ((i + n / 2) <= (n - 1) && arr[i + n / 2] == x) {\n return true;\n } else {\n return false;\n }\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 3, 3, 3, 10};\n\n assert(func0(arr1, 7, 3) == true);\n\n\n\n int arr2[] = {1, 1, 2, 4, 4, 4, 6, 6};\n\n assert(func0(arr2, 8, 4) == false);\n\n\n\n int arr3[] = {1, 1, 1, 2, 2};\n\n assert(func0(arr3, 5, 1) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nmov %esi,%r8d\nsub $0x1,%r8d\njs 134f \nxor %r9d,%r9d\nlea (%r9,%r8,1),%eax\nsar %eax\nmov %eax,%ecx\ncltq\nlea 0x0(,%rax,4),%r10\nmov (%rdi,%rax,4),%eax\nje 133e \ncmp -0x4(%rdi,%r10,1),%edx\njle 1342 \ncmp %eax,%edx\nje 1368 \ncmp %eax,%edx\njle 1358 \nlea 0x1(%rcx),%r9d\ncmp %r8d,%r9d\njle 1320 \nxor %eax,%eax\nretq\nnopw 0x0(%rax,%rax,1)\nlea -0x1(%rcx),%r8d\ncmp %r9d,%r8d\njge 1320 \nxor %eax,%eax\nretq\nnopl 0x0(%rax)\nmov %esi,%eax\nshr $0x1f,%eax\nadd %esi,%eax\nsar %eax\nadd %ecx,%eax\ncmp %esi,%eax\njge 134f \ncltq\ncmp %edx,(%rdi,%rax,4)\nsete %al\nretq\n", + "ida_asm": "func0:\nendbr64\nmov r8, rdi\nmov r10d, esi\nmov ecx, edx\nsub esi, 1\njs short loc_134B\nxor edi, edi\nnop dword ptr [rax+rax+00h]\nloc_1318:\nlea edx, [rdi+rsi]\nmov eax, edx\nshr eax, 1Fh\nadd eax, edx\nsar eax, 1\nmovsxd rdx, eax\nlea r9, ds:0[rdx*4]\nmov edx, [r8+rdx*4]\njz short loc_133C\ncmp ecx, [r8+r9-4]\njle short loc_1340\nloc_133C:\ncmp ecx, edx\njz short loc_1360\nloc_1340:\ncmp ecx, edx\njle short loc_1350\nlea edi, [rax+1]\ncmp edi, esi\njle short loc_1318\nloc_134B:\nxor edx, edx\nloc_134D:\nmov eax, edx\nretn\nloc_1350:\nlea esi, [rax-1]\ncmp esi, edi\njge short loc_1318\njmp short loc_134B\nloc_1360:\ncmp eax, 0FFFFFFFFh\njz short loc_134B\nmov edx, r10d\nsar edx, 1\nadd eax, edx\nxor edx, edx\ncmp eax, r10d\njge short loc_134D\ncdqe\ncmp [r8+rax*4], ecx\nsetz dl\nmov eax, edx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n int v6; // esi\n int v7; // edi\n int v8; // eax\n __int64 v9; // r9\n int v10; // edx\n int v12; // eax\n unsigned int v13; // edx\n\n v6 = a2 - 1;\n if ( v6 < 0 )\n return 0LL;\n v7 = 0;\n while ( 1 )\n {\n v8 = (v7 + v6) / 2;\n v9 = 4LL * v8;\n v10 = *(_DWORD *)(a1 + v9);\n if ( (!v8 || a3 > *(_DWORD *)(a1 + v9 - 4)) && a3 == v10 )\n break;\n if ( a3 <= v10 )\n {\n v6 = v8 - 1;\n if ( v8 - 1 < v7 )\n return 0LL;\n }\n else\n {\n v7 = v8 + 1;\n if ( v8 + 1 > v6 )\n return 0LL;\n }\n }\n if ( v8 == -1 )\n return 0LL;\n v12 = (a2 >> 1) + v8;\n v13 = 0;\n if ( v12 >= a2 )\n return 0LL;\n LOBYTE(v13) = *(_DWORD *)(a1 + 4LL * v12) == a3;\n return v13;\n}", + "ida_strip_asm": "sub_1300:\nendbr64\nmov r8, rdi\nmov r10d, esi\nmov ecx, edx\nsub esi, 1\njs short loc_134B\nxor edi, edi\nnop dword ptr [rax+rax+00h]\nloc_1318:\nlea edx, [rdi+rsi]\nmov eax, edx\nshr eax, 1Fh\nadd eax, edx\nsar eax, 1\nmovsxd rdx, eax\nlea r9, ds:0[rdx*4]\nmov edx, [r8+rdx*4]\njz short loc_133C\ncmp ecx, [r8+r9-4]\njle short loc_1340\nloc_133C:\ncmp ecx, edx\njz short loc_1360\nloc_1340:\ncmp ecx, edx\njle short loc_1350\nlea edi, [rax+1]\ncmp edi, esi\njle short loc_1318\nloc_134B:\nxor edx, edx\nloc_134D:\nmov eax, edx\nretn\nloc_1350:\nlea esi, [rax-1]\ncmp esi, edi\njge short loc_1318\njmp short loc_134B\nloc_1360:\ncmp eax, 0FFFFFFFFh\njz short loc_134B\nmov edx, r10d\nsar edx, 1\nadd eax, edx\nxor edx, edx\ncmp eax, r10d\njge short loc_134D\ncdqe\ncmp [r8+rax*4], ecx\nsetz dl\nmov eax, edx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1300(__int64 a1, int a2, int a3)\n{\n int v6; // esi\n int v7; // edi\n int v8; // eax\n __int64 v9; // r9\n int v10; // edx\n int v12; // eax\n unsigned int v13; // edx\n\n v6 = a2 - 1;\n if ( v6 < 0 )\n return 0LL;\n v7 = 0;\n while ( 1 )\n {\n v8 = (v7 + v6) / 2;\n v9 = 4LL * v8;\n v10 = *(_DWORD *)(a1 + v9);\n if ( (!v8 || a3 > *(_DWORD *)(a1 + v9 - 4)) && a3 == v10 )\n break;\n if ( a3 <= v10 )\n {\n v6 = v8 - 1;\n if ( v8 - 1 < v7 )\n return 0LL;\n }\n else\n {\n v7 = v8 + 1;\n if ( v8 + 1 > v6 )\n return 0LL;\n }\n }\n if ( v8 == -1 )\n return 0LL;\n v12 = (a2 >> 1) + v8;\n v13 = 0;\n if ( v12 >= a2 )\n return 0LL;\n LOBYTE(v13) = *(_DWORD *)(a1 + 4LL * v12) == a3;\n return v13;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1300(long long a1, int a2, int a3) {\n int v6;\n int v7;\n int v8;\n long long v9;\n int v10;\n int v12;\n unsigned int v13;\n v6 = a2 - 1;\n if (v6 < 0) return 0LL;\n v7 = 0;\n while (1) {\n v8 = (v7 + v6) / 2;\n v9 = 4LL * v8;\n v10 = *(uint32_t *)(a1 + v9);\n if ((!v8 || a3 > *(uint32_t *)(a1 + v9 - 4)) && a3 == v10) break;\n if (a3 <= v10) {\n v6 = v8 - 1;\n if (v8 - 1 < v7) return 0LL;\n } else {\n v7 = v8 + 1;\n if (v8 + 1 > v6) return 0LL;\n }\n }\n if (v8 == -1) return 0LL;\n v12 = (a2 >> 1) + v8;\n v13 = 0;\n if (v12 >= a2) return 0LL;\n LOBYTE(v13) = *(uint32_t *)(a1 + 4LL * v12) == a3;\n return v13;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n int v6;\n int v7;\n int v8;\n long long v9;\n int v10;\n int v12;\n unsigned int v13;\n v6 = a2 - 1;\n if (v6 < 0) return 0LL;\n v7 = 0;\n while (1) {\n v8 = (v7 + v6) / 2;\n v9 = 4LL * v8;\n v10 = *(uint32_t *)(a1 + v9);\n if ((!v8 || a3 > *(uint32_t *)(a1 + v9 - 4)) && a3 == v10) break;\n if (a3 <= v10) {\n v6 = v8 - 1;\n if (v8 - 1 < v7) return 0LL;\n } else {\n v7 = v8 + 1;\n if (v8 + 1 > v6) return 0LL;\n }\n }\n if (v8 == -1) return 0LL;\n v12 = (a2 >> 1) + v8;\n v13 = 0;\n if (v12 >= a2) return 0LL;\n LOBYTE(v13) = *(uint32_t *)(a1 + 4LL * v12) == a3;\n return v13;\n}" + }, + { + "index": 224, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int count = 0;\n while (n) {\n count += n & 1;\n n >>= 1;\n }\n return count;\n}", + "test": "int main() {\n\n assert(func0(2) == 1);\n\n assert(func0(4) == 1);\n\n assert(func0(6) == 2);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 1169 \nmov -0x14(%rbp),%eax\nand $0x1,%eax\nadd %eax,-0x4(%rbp)\nsarl -0x14(%rbp)\ncmpl $0x0,-0x14(%rbp)\njne 115d \nmov -0x4(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_4], 0\njmp short loc_1169\nloc_115D:\nmov eax, [rbp+var_14]\nand eax, 1\nadd [rbp+var_4], eax\nsar [rbp+var_14], 1\nloc_1169:\ncmp [rbp+var_14], 0\njnz short loc_115D\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v3; // [rsp+10h] [rbp-4h]\n\n v3 = 0;\n while ( a1 )\n {\n v3 += a1 & 1;\n a1 >>= 1;\n }\n return v3;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_4], 0\njmp short loc_1169\nloc_115D:\nmov eax, [rbp+var_14]\nand eax, 1\nadd [rbp+var_4], eax\nsar [rbp+var_14], 1\nloc_1169:\ncmp [rbp+var_14], 0\njnz short loc_115D\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n unsigned int v3; // [rsp+10h] [rbp-4h]\n\n v3 = 0;\n while ( a1 )\n {\n v3 += a1 & 1;\n a1 >>= 1;\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n unsigned int v3;\n v3 = 0;\n while (a1) {\n v3 += a1 & 1;\n a1 >>= 1;\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v3;\n v3 = 0;\n while (a1) {\n v3 += a1 & 1;\n a1 >>= 1;\n }\n return v3;\n}" + }, + { + "index": 224, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int count = 0;\n while (n) {\n count += n & 1;\n n >>= 1;\n }\n return count;\n}", + "test": "int main() {\n\n assert(func0(2) == 1);\n\n assert(func0(4) == 1);\n\n assert(func0(6) == 2);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\nje 1162 \nmov $0x0,%eax\nmov %edi,%edx\nand $0x1,%edx\nadd %edx,%eax\nsar %edi\njne 1156 \nretq\nmov %edi,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njz short loc_1162\nmov eax, 0\nloc_1156:\nmov edx, edi\nand edx, 1\nadd eax, edx\nsar edi, 1\njnz short loc_1156\nretn\nloc_1162:\nmov eax, edi\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n __int64 result; // rax\n\n if ( !a1 )\n return 0LL;\n LODWORD(result) = 0;\n do\n {\n result = (a1 & 1) + (unsigned int)result;\n a1 >>= 1;\n }\n while ( a1 );\n return result;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ntest edi, edi\njz short loc_1162\nmov eax, 0\nloc_1156:\nmov edx, edi\nand edx, 1\nadd eax, edx\nsar edi, 1\njnz short loc_1156\nretn\nloc_1162:\nmov eax, edi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n __int64 result; // rax\n\n if ( !a1 )\n return 0LL;\n LODWORD(result) = 0;\n do\n {\n result = (a1 & 1) + (unsigned int)result;\n a1 >>= 1;\n }\n while ( a1 );\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n long long result;\n if (!a1) return 0LL;\n LODWORD(result) = 0;\n do {\n result = (a1 & 1) + (unsigned int)result;\n a1 >>= 1;\n } while (a1);\n return result;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n long long result;\n if (!a1) return 0LL;\n LODWORD(result) = 0;\n do {\n result = (a1 & 1) + (unsigned int)result;\n a1 >>= 1;\n } while (a1);\n return result;\n}" + }, + { + "index": 225, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int low, int high) {\n while (low < high) {\n int mid = low + (high - low) / 2;\n if (arr[mid] == arr[high]) {\n high -= 1;\n } else if (arr[mid] > arr[high]) {\n low = mid + 1;\n } else {\n high = mid;\n }\n }\n return arr[high];\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4, 5};\n\n int arr2[] = {4, 6, 8};\n\n int arr3[] = {2, 3, 5, 7, 9};\n\n\n\n assert(func0(arr1, 0, 4) == 1);\n\n assert(func0(arr2, 0, 2) == 4);\n\n assert(func0(arr3, 0, 4) == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\njmpq 1210 \nmov -0x20(%rbp),%eax\nsub -0x1c(%rbp),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nmov %eax,%edx\nmov -0x1c(%rbp),%eax\nadd %edx,%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x20(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 11cf \nsubl $0x1,-0x20(%rbp)\njmp 1210 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x20(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njle 120a \nmov -0x4(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x1c(%rbp)\njmp 1210 \nmov -0x4(%rbp),%eax\nmov %eax,-0x20(%rbp)\nmov -0x1c(%rbp),%eax\ncmp -0x20(%rbp),%eax\njl 1180 \nmov -0x20(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\njmp loc_1210\nloc_1180:\nmov eax, [rbp+var_20]\nsub eax, [rbp+var_1C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov edx, eax\nmov eax, [rbp+var_1C]\nadd eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_20]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11CF\nsub [rbp+var_20], 1\njmp short loc_1210\nloc_11CF:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_20]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_120A\nmov eax, [rbp+var_4]\nadd eax, 1\nmov [rbp+var_1C], eax\njmp short loc_1210\nloc_120A:\nmov eax, [rbp+var_4]\nmov [rbp+var_20], eax\nloc_1210:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_20]\njl loc_1180\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n int v6; // [rsp+1Ch] [rbp-4h]\n\n while ( a2 < a3 )\n {\n v6 = (a3 - a2) / 2 + a2;\n if ( *(_DWORD *)(4LL * v6 + a1) == *(_DWORD *)(4LL * a3 + a1) )\n {\n --a3;\n }\n else if ( *(_DWORD *)(4LL * v6 + a1) <= *(_DWORD *)(4LL * a3 + a1) )\n {\n a3 = (a3 - a2) / 2 + a2;\n }\n else\n {\n a2 = v6 + 1;\n }\n }\n return *(unsigned int *)(4LL * a3 + a1);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\njmp loc_1210\nloc_1180:\nmov eax, [rbp+var_20]\nsub eax, [rbp+var_1C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov edx, eax\nmov eax, [rbp+var_1C]\nadd eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_20]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11CF\nsub [rbp+var_20], 1\njmp short loc_1210\nloc_11CF:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_20]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_120A\nmov eax, [rbp+var_4]\nadd eax, 1\nmov [rbp+var_1C], eax\njmp short loc_1210\nloc_120A:\nmov eax, [rbp+var_4]\nmov [rbp+var_20], eax\nloc_1210:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_20]\njl loc_1180\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n int v6; // [rsp+1Ch] [rbp-4h]\n\n while ( a2 < a3 )\n {\n v6 = (a3 - a2) / 2 + a2;\n if ( *(_DWORD *)(4LL * v6 + a1) == *(_DWORD *)(4LL * a3 + a1) )\n {\n --a3;\n }\n else if ( *(_DWORD *)(4LL * v6 + a1) <= *(_DWORD *)(4LL * a3 + a1) )\n {\n a3 = (a3 - a2) / 2 + a2;\n }\n else\n {\n a2 = v6 + 1;\n }\n }\n return *(unsigned int *)(4LL * a3 + a1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n int v6;\n while (a2 < a3) {\n v6 = (a3 - a2) / 2 + a2;\n if (*(uint32_t *)(4LL * v6 + a1) == *(uint32_t *)(4LL * a3 + a1)) {\n --a3;\n } else if (*(uint32_t *)(4LL * v6 + a1) <= *(uint32_t *)(4LL * a3 + a1)) {\n a3 = (a3 - a2) / 2 + a2;\n } else {\n a2 = v6 + 1;\n }\n }\n return *(unsigned int *)(4LL * a3 + a1);\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n int v6;\n while (a2 < a3) {\n v6 = (a3 - a2) / 2 + a2;\n if (*(uint32_t *)(4LL * v6 + a1) == *(uint32_t *)(4LL * a3 + a1)) {\n --a3;\n } else if (*(uint32_t *)(4LL * v6 + a1) <= *(uint32_t *)(4LL * a3 + a1)) {\n a3 = (a3 - a2) / 2 + a2;\n } else {\n a2 = v6 + 1;\n }\n }\n return *(unsigned int *)(4LL * a3 + a1);\n}" + }, + { + "index": 225, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int low, int high) {\n while (low < high) {\n int mid = low + (high - low) / 2;\n if (arr[mid] == arr[high]) {\n high -= 1;\n } else if (arr[mid] > arr[high]) {\n low = mid + 1;\n } else {\n high = mid;\n }\n }\n return arr[high];\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4, 5};\n\n int arr2[] = {4, 6, 8};\n\n int arr3[] = {2, 3, 5, 7, 9};\n\n\n\n assert(func0(arr1, 0, 4) == 1);\n\n assert(func0(arr2, 0, 2) == 4);\n\n assert(func0(arr3, 0, 4) == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ncmp %edx,%esi\njl 117f \nmovslq %edx,%rdx\nmov (%rdi,%rdx,4),%eax\nretq\nsub $0x1,%edx\ncmp %edx,%esi\njge 1171 \nmov %edx,%ecx\nsub %esi,%ecx\nmov %ecx,%eax\nshr $0x1f,%eax\nadd %ecx,%eax\nsar %eax\nadd %esi,%eax\nmovslq %eax,%rcx\nmov (%rdi,%rcx,4),%r8d\nmovslq %edx,%rcx\nmov (%rdi,%rcx,4),%ecx\ncmp %ecx,%r8d\nje 1178 \njle 11a7 \nlea 0x1(%rax),%esi\njmp 117b \nmov %eax,%edx\njmp 117b \n", + "ida_asm": "func0:\nendbr64\nmov r8, rdi\ncmp esi, edx\njl short loc_1183\nloc_1174:\nmovsxd rdx, edx\nmov eax, [r8+rdx*4]\nretn\nloc_117C:\nsub edx, 1\nloc_117F:\ncmp esi, edx\njge short loc_1174\nloc_1183:\nmov ecx, edx\nsub ecx, esi\nmov eax, ecx\nshr eax, 1Fh\nadd eax, ecx\nsar eax, 1\nadd eax, esi\nmovsxd rcx, eax\nmov edi, [r8+rcx*4]\nmovsxd rcx, edx\nmov ecx, [r8+rcx*4]\ncmp edi, ecx\njz short loc_117C\njle short loc_11AB\nlea esi, [rax+1]\njmp short loc_117F\nloc_11AB:\nmov edx, eax\njmp short loc_117F", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n int v5; // eax\n int v6; // edi\n int v7; // ecx\n\n while ( a2 < a3 )\n {\n v5 = a2 + (a3 - a2) / 2;\n v6 = *(_DWORD *)(a1 + 4LL * v5);\n v7 = *(_DWORD *)(a1 + 4LL * a3);\n if ( v6 == v7 )\n {\n --a3;\n }\n else if ( v6 <= v7 )\n {\n a3 = a2 + (a3 - a2) / 2;\n }\n else\n {\n a2 = v5 + 1;\n }\n }\n return *(unsigned int *)(a1 + 4LL * a3);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov r8, rdi\ncmp esi, edx\njl short loc_1183\nloc_1174:\nmovsxd rdx, edx\nmov eax, [r8+rdx*4]\nretn\nloc_117C:\nsub edx, 1\nloc_117F:\ncmp esi, edx\njge short loc_1174\nloc_1183:\nmov ecx, edx\nsub ecx, esi\nmov eax, ecx\nshr eax, 1Fh\nadd eax, ecx\nsar eax, 1\nadd eax, esi\nmovsxd rcx, eax\nmov edi, [r8+rcx*4]\nmovsxd rcx, edx\nmov ecx, [r8+rcx*4]\ncmp edi, ecx\njz short loc_117C\njle short loc_11AB\nlea esi, [rax+1]\njmp short loc_117F\nloc_11AB:\nmov edx, eax\njmp short loc_117F", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n int v5; // eax\n int v6; // edi\n int v7; // ecx\n\n while ( a2 < a3 )\n {\n v5 = a2 + (a3 - a2) / 2;\n v6 = *(_DWORD *)(a1 + 4LL * v5);\n v7 = *(_DWORD *)(a1 + 4LL * a3);\n if ( v6 == v7 )\n {\n --a3;\n }\n else if ( v6 <= v7 )\n {\n a3 = a2 + (a3 - a2) / 2;\n }\n else\n {\n a2 = v5 + 1;\n }\n }\n return *(unsigned int *)(a1 + 4LL * a3);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n int v5;\n int v6;\n int v7;\n while (a2 < a3) {\n v5 = a2 + (a3 - a2) / 2;\n v6 = *(uint32_t *)(a1 + 4LL * v5);\n v7 = *(uint32_t *)(a1 + 4LL * a3);\n if (v6 == v7) {\n --a3;\n } else if (v6 <= v7) {\n a3 = a2 + (a3 - a2) / 2;\n } else {\n a2 = v5 + 1;\n }\n }\n return *(unsigned int *)(a1 + 4LL * a3);\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n int v5;\n int v6;\n int v7;\n while (a2 < a3) {\n v5 = a2 + (a3 - a2) / 2;\n v6 = *(uint32_t *)(a1 + 4LL * v5);\n v7 = *(uint32_t *)(a1 + 4LL * a3);\n if (v6 == v7) {\n --a3;\n } else if (v6 <= v7) {\n a3 = a2 + (a3 - a2) / 2;\n } else {\n a2 = v5 + 1;\n }\n }\n return *(unsigned int *)(a1 + 4LL * a3);\n}" + }, + { + "index": 225, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int low, int high) {\n while (low < high) {\n int mid = low + (high - low) / 2;\n if (arr[mid] == arr[high]) {\n high -= 1;\n } else if (arr[mid] > arr[high]) {\n low = mid + 1;\n } else {\n high = mid;\n }\n }\n return arr[high];\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4, 5};\n\n int arr2[] = {4, 6, 8};\n\n int arr3[] = {2, 3, 5, 7, 9};\n\n\n\n assert(func0(arr1, 0, 4) == 1);\n\n assert(func0(arr2, 0, 2) == 4);\n\n assert(func0(arr3, 0, 4) == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmovslq %edx,%rax\nmov (%rdi,%rax,4),%r8d\ncmp %edx,%esi\njl 12d1 \njmp 12f2 \nnopl 0x0(%rax)\njle 1300 \nlea 0x1(%rax),%esi\ncmp %esi,%edx\njle 12f2 \nmov %edx,%eax\nsub %esi,%eax\nsar %eax\nadd %esi,%eax\nmovslq %eax,%rcx\nmov (%rdi,%rcx,4),%ecx\ncmp %r8d,%ecx\njne 12c8 \nsub $0x1,%edx\nmovslq %edx,%rax\nmov (%rdi,%rax,4),%r8d\ncmp %esi,%edx\njg 12d1 \nmov %r8d,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nmov %ecx,%r8d\nmov %eax,%edx\njmp 12cd \nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmovsxd rax, edx\nmov r8d, [rdi+rax*4]\ncmp esi, edx\njl short loc_12A1\njmp short loc_12C2\nloc_1298:\njle short loc_12D0\nlea esi, [rax+1]\nloc_129D:\ncmp edx, esi\njle short loc_12C2\nloc_12A1:\nmov eax, edx\nsub eax, esi\nsar eax, 1\nadd eax, esi\nmovsxd rcx, eax\nmov ecx, [rdi+rcx*4]\ncmp ecx, r8d\njnz short loc_1298\nsub edx, 1\nmovsxd rax, edx\nmov r8d, [rdi+rax*4]\ncmp edx, esi\njg short loc_12A1\nloc_12C2:\nmov eax, r8d\nretn\nloc_12D0:\nmov r8d, ecx\nmov edx, eax\njmp short loc_129D", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n unsigned int v3; // r8d\n int v4; // eax\n int v5; // ecx\n\n v3 = *(_DWORD *)(a1 + 4LL * a3);\n while ( a3 > a2 )\n {\n while ( 1 )\n {\n v4 = a2 + ((a3 - a2) >> 1);\n v5 = *(_DWORD *)(a1 + 4LL * v4);\n if ( v5 != v3 )\n break;\n v3 = *(_DWORD *)(a1 + 4LL * --a3);\n if ( a3 <= a2 )\n return v3;\n }\n if ( v5 <= (int)v3 )\n {\n v3 = *(_DWORD *)(a1 + 4LL * v4);\n a3 = a2 + ((a3 - a2) >> 1);\n }\n else\n {\n a2 = v4 + 1;\n }\n }\n return v3;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\nmovsxd rax, edx\nmov r8d, [rdi+rax*4]\ncmp esi, edx\njl short loc_12A1\njmp short loc_12C2\nloc_1298:\njle short loc_12D0\nlea esi, [rax+1]\nloc_129D:\ncmp edx, esi\njle short loc_12C2\nloc_12A1:\nmov eax, edx\nsub eax, esi\nsar eax, 1\nadd eax, esi\nmovsxd rcx, eax\nmov ecx, [rdi+rcx*4]\ncmp ecx, r8d\njnz short loc_1298\nsub edx, 1\nmovsxd rax, edx\nmov r8d, [rdi+rax*4]\ncmp edx, esi\njg short loc_12A1\nloc_12C2:\nmov eax, r8d\nretn\nloc_12D0:\nmov r8d, ecx\nmov edx, eax\njmp short loc_129D", + "ida_strip_pseudo": "__int64 __fastcall sub_1280(__int64 a1, int a2, int a3)\n{\n unsigned int v3; // r8d\n int v4; // eax\n int v5; // ecx\n\n v3 = *(_DWORD *)(a1 + 4LL * a3);\n while ( a3 > a2 )\n {\n while ( 1 )\n {\n v4 = a2 + ((a3 - a2) >> 1);\n v5 = *(_DWORD *)(a1 + 4LL * v4);\n if ( v5 != v3 )\n break;\n v3 = *(_DWORD *)(a1 + 4LL * --a3);\n if ( a3 <= a2 )\n return v3;\n }\n if ( v5 <= (int)v3 )\n {\n v3 = *(_DWORD *)(a1 + 4LL * v4);\n a3 = a2 + ((a3 - a2) >> 1);\n }\n else\n {\n a2 = v4 + 1;\n }\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1280(long long a1, int a2, int a3) {\n unsigned int v3;\n int v4;\n int v5;\n v3 = *(uint32_t *)(a1 + 4LL * a3);\n while (a3 > a2) {\n while (1) {\n v4 = a2 + ((a3 - a2) >> 1);\n v5 = *(uint32_t *)(a1 + 4LL * v4);\n if (v5 != v3) break;\n v3 = *(uint32_t *)(a1 + 4LL * --a3);\n if (a3 <= a2) return v3;\n }\n if (v5 <= (int)v3) {\n v3 = *(uint32_t *)(a1 + 4LL * v4);\n a3 = a2 + ((a3 - a2) >> 1);\n } else {\n a2 = v4 + 1;\n }\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n unsigned int v3;\n int v4;\n int v5;\n v3 = *(uint32_t *)(a1 + 4LL * a3);\n while (a3 > a2) {\n while (1) {\n v4 = a2 + ((a3 - a2) >> 1);\n v5 = *(uint32_t *)(a1 + 4LL * v4);\n if (v5 != v3) break;\n v3 = *(uint32_t *)(a1 + 4LL * --a3);\n if (a3 <= a2) return v3;\n }\n if (v5 <= (int)v3) {\n v3 = *(uint32_t *)(a1 + 4LL * v4);\n a3 = a2 + ((a3 - a2) >> 1);\n } else {\n a2 = v4 + 1;\n }\n }\n return v3;\n}" + }, + { + "index": 225, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int low, int high) {\n while (low < high) {\n int mid = low + (high - low) / 2;\n if (arr[mid] == arr[high]) {\n high -= 1;\n } else if (arr[mid] > arr[high]) {\n low = mid + 1;\n } else {\n high = mid;\n }\n }\n return arr[high];\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4, 5};\n\n int arr2[] = {4, 6, 8};\n\n int arr3[] = {2, 3, 5, 7, 9};\n\n\n\n assert(func0(arr1, 0, 4) == 1);\n\n assert(func0(arr2, 0, 2) == 4);\n\n assert(func0(arr3, 0, 4) == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nmovslq %edx,%rax\nmov (%rdi,%rax,4),%r8d\ncmp %edx,%esi\njl 12b1 \njmp 12d2 \nnopl 0x0(%rax)\njle 12e0 \nlea 0x1(%rax),%esi\ncmp %esi,%edx\njle 12d2 \nmov %edx,%eax\nsub %esi,%eax\nsar %eax\nadd %esi,%eax\nmovslq %eax,%rcx\nmov (%rdi,%rcx,4),%ecx\ncmp %r8d,%ecx\njne 12a8 \nsub $0x1,%edx\nmovslq %edx,%rax\nmov (%rdi,%rax,4),%r8d\ncmp %esi,%edx\njg 12b1 \nmov %r8d,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nmov %ecx,%r8d\nmov %eax,%edx\njmp 12ad \nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmovsxd rax, edx\nmov r8d, [rdi+rax*4]\ncmp esi, edx\njl short loc_12A1\njmp short loc_12C2\nloc_1298:\njle short loc_12D0\nlea esi, [rax+1]\nloc_129D:\ncmp edx, esi\njle short loc_12C2\nloc_12A1:\nmov eax, edx\nsub eax, esi\nsar eax, 1\nadd eax, esi\nmovsxd rcx, eax\nmov ecx, [rdi+rcx*4]\ncmp ecx, r8d\njnz short loc_1298\nsub edx, 1\nmovsxd rax, edx\nmov r8d, [rdi+rax*4]\ncmp edx, esi\njg short loc_12A1\nloc_12C2:\nmov eax, r8d\nretn\nloc_12D0:\nmov r8d, ecx\nmov edx, eax\njmp short loc_129D", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n unsigned int v3; // r8d\n int v4; // eax\n int v5; // ecx\n\n v3 = *(_DWORD *)(a1 + 4LL * a3);\n while ( a3 > a2 )\n {\n while ( 1 )\n {\n v4 = a2 + ((a3 - a2) >> 1);\n v5 = *(_DWORD *)(a1 + 4LL * v4);\n if ( v5 != v3 )\n break;\n v3 = *(_DWORD *)(a1 + 4LL * --a3);\n if ( a3 <= a2 )\n return v3;\n }\n if ( v5 <= (int)v3 )\n {\n v3 = *(_DWORD *)(a1 + 4LL * v4);\n a3 = a2 + ((a3 - a2) >> 1);\n }\n else\n {\n a2 = v4 + 1;\n }\n }\n return v3;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\nmovsxd rax, edx\nmov r8d, [rdi+rax*4]\ncmp esi, edx\njl short loc_12A1\njmp short loc_12C2\nloc_1298:\njle short loc_12D0\nlea esi, [rax+1]\nloc_129D:\ncmp edx, esi\njle short loc_12C2\nloc_12A1:\nmov eax, edx\nsub eax, esi\nsar eax, 1\nadd eax, esi\nmovsxd rcx, eax\nmov ecx, [rdi+rcx*4]\ncmp ecx, r8d\njnz short loc_1298\nsub edx, 1\nmovsxd rax, edx\nmov r8d, [rdi+rax*4]\ncmp edx, esi\njg short loc_12A1\nloc_12C2:\nmov eax, r8d\nretn\nloc_12D0:\nmov r8d, ecx\nmov edx, eax\njmp short loc_129D", + "ida_strip_pseudo": "__int64 __fastcall sub_1280(__int64 a1, int a2, int a3)\n{\n unsigned int v3; // r8d\n int v4; // eax\n int v5; // ecx\n\n v3 = *(_DWORD *)(a1 + 4LL * a3);\n while ( a3 > a2 )\n {\n while ( 1 )\n {\n v4 = a2 + ((a3 - a2) >> 1);\n v5 = *(_DWORD *)(a1 + 4LL * v4);\n if ( v5 != v3 )\n break;\n v3 = *(_DWORD *)(a1 + 4LL * --a3);\n if ( a3 <= a2 )\n return v3;\n }\n if ( v5 <= (int)v3 )\n {\n v3 = *(_DWORD *)(a1 + 4LL * v4);\n a3 = a2 + ((a3 - a2) >> 1);\n }\n else\n {\n a2 = v4 + 1;\n }\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1280(long long a1, int a2, int a3) {\n unsigned int v3;\n int v4;\n int v5;\n v3 = *(uint32_t *)(a1 + 4LL * a3);\n while (a3 > a2) {\n while (1) {\n v4 = a2 + ((a3 - a2) >> 1);\n v5 = *(uint32_t *)(a1 + 4LL * v4);\n if (v5 != v3) break;\n v3 = *(uint32_t *)(a1 + 4LL * --a3);\n if (a3 <= a2) return v3;\n }\n if (v5 <= (int)v3) {\n v3 = *(uint32_t *)(a1 + 4LL * v4);\n a3 = a2 + ((a3 - a2) >> 1);\n } else {\n a2 = v4 + 1;\n }\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n unsigned int v3;\n int v4;\n int v5;\n v3 = *(uint32_t *)(a1 + 4LL * a3);\n while (a3 > a2) {\n while (1) {\n v4 = a2 + ((a3 - a2) >> 1);\n v5 = *(uint32_t *)(a1 + 4LL * v4);\n if (v5 != v3) break;\n v3 = *(uint32_t *)(a1 + 4LL * --a3);\n if (a3 <= a2) return v3;\n }\n if (v5 <= (int)v3) {\n v3 = *(uint32_t *)(a1 + 4LL * v4);\n a3 = a2 + ((a3 - a2) >> 1);\n } else {\n a2 = v4 + 1;\n }\n }\n return v3;\n}" + }, + { + "index": 226, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* str) {\n static char result[100];\n int j = 0;\n for (int i = 0; i < strlen(str); i++) {\n if (i % 2 == 0) {\n result[j++] = str[i];\n }\n }\n result[j] = '\\0';\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"abcdef\"), \"ace\") == 0);\n\n assert(strcmp(func0(\"python\"), \"pto\") == 0);\n\n assert(strcmp(func0(\"data\"), \"dt\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x28,%rsp\nmov %rdi,-0x28(%rbp)\nmovl $0x0,-0x18(%rbp)\nmovl $0x0,-0x14(%rbp)\njmp 11de \nmov -0x14(%rbp),%eax\nand $0x1,%eax\ntest %eax,%eax\njne 11da \nmov -0x14(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x18(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x18(%rbp)\nmovzbl (%rcx),%edx\ncltq\nlea 0x2e69(%rip),%rcx\nmov %dl,(%rax,%rcx,1)\naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\nmovslq %eax,%rbx\nmov -0x28(%rbp),%rax\nmov %rax,%rdi\ncallq 1070 \ncmp %rax,%rbx\njb 11aa \nmov -0x18(%rbp),%eax\ncltq\nlea 0x2e3f(%rip),%rdx\nmovb $0x0,(%rax,%rdx,1)\nlea 0x2e34(%rip),%rax\nadd $0x28,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+s], rdi\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp short loc_11DE\nloc_11AA:\nmov eax, [rbp+var_14]\nand eax, 1\ntest eax, eax\njnz short loc_11DA\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\nmovzx edx, byte ptr [rcx]\ncdqe\nlea rcx, result_1\nmov [rax+rcx], dl\nloc_11DA:\nadd [rbp+var_14], 1\nloc_11DE:\nmov eax, [rbp+var_14]\nmovsxd rbx, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rbx, rax\njb short loc_11AA\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, result_1\nmov byte ptr [rax+rdx], 0\nlea rax, result_1\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1)\n{\n int v1; // eax\n int v3; // [rsp+18h] [rbp-18h]\n int i; // [rsp+1Ch] [rbp-14h]\n\n v3 = 0;\n for ( i = 0; i < strlen(a1); ++i )\n {\n if ( (i & 1) == 0 )\n {\n v1 = v3++;\n result_1[v1] = a1[i];\n }\n }\n result_1[v3] = 0;\n return result_1;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+s], rdi\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp short loc_11DE\nloc_11AA:\nmov eax, [rbp+var_14]\nand eax, 1\ntest eax, eax\njnz short loc_11DA\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\nmovzx edx, byte ptr [rcx]\ncdqe\nlea rcx, unk_4040\nmov [rax+rcx], dl\nloc_11DA:\nadd [rbp+var_14], 1\nloc_11DE:\nmov eax, [rbp+var_14]\nmovsxd rbx, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rbx, rax\njb short loc_11AA\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, unk_4040\nmov byte ptr [rax+rdx], 0\nlea rax, unk_4040\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1189(const char *a1)\n{\n int v1; // eax\n int v3; // [rsp+18h] [rbp-18h]\n int i; // [rsp+1Ch] [rbp-14h]\n\n v3 = 0;\n for ( i = 0; i < strlen(a1); ++i )\n {\n if ( (i & 1) == 0 )\n {\n v1 = v3++;\n byte_4040[v1] = a1[i];\n }\n }\n byte_4040[v3] = 0;\n return byte_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1189(const char *a1) {\n int v1;\n int v3;\n int i;\n v3 = 0;\n for (i = 0; i < strlen(a1); ++i) {\n if ((i & 1) == 0) {\n v1 = v3++;\n byte_4040[v1] = a1[i];\n }\n }\n byte_4040[v3] = 0;\n return byte_4040;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1) {\n int v1;\n int v3;\n int i;\n v3 = 0;\n for (i = 0; i < strlen(a1); ++i) {\n if ((i & 1) == 0) {\n v1 = v3++;\n result_1[v1] = a1[i];\n }\n }\n result_1[v3] = 0;\n return result_1;\n}" + }, + { + "index": 226, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* str) {\n static char result[100];\n int j = 0;\n for (int i = 0; i < strlen(str); i++) {\n if (i % 2 == 0) {\n result[j++] = str[i];\n }\n }\n result[j] = '\\0';\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"abcdef\"), \"ace\") == 0);\n\n assert(strcmp(func0(\"python\"), \"pto\") == 0);\n\n assert(strcmp(func0(\"data\"), \"dt\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%r8\nmov $0x0,%edx\nmov $0x0,%esi\nmov $0xffffffffffffffff,%r9\nmov $0x0,%eax\nlea 0x2ed3(%rip),%r10\njmp 1173 \nadd $0x1,%rdx\nmov %r9,%rcx\nmov %r8,%rdi\nrepnz scas %es:(%rdi),%al\nnot %rcx\nsub $0x1,%rcx\ncmp %rdx,%rcx\njbe 119d \ntest $0x1,%dl\njne 116f \nmovzbl (%r8,%rdx,1),%edi\nmovslq %esi,%rcx\nmov %dil,(%r10,%rcx,1)\nlea 0x1(%rsi),%esi\njmp 116f \nlea 0x2e9c(%rip),%rax\nmovslq %esi,%rsi\nmovb $0x0,(%rax,%rsi,1)\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12, rdi\nmov ebx, 0\nmov ebp, 0\nlea r13, result_1\njmp short loc_11B1\nloc_11AD:\nadd rbx, 1\nloc_11B1:\nmov rdi, r12; s\ncall _strlen\ncmp rbx, rax\njnb short loc_11D5\ntest bl, 1\njnz short loc_11AD\nmovzx edx, byte ptr [r12+rbx]\nmovsxd rax, ebp\nmov [r13+rax+0], dl\nlea ebp, [rbp+1]\njmp short loc_11AD\nloc_11D5:\nlea rax, result_1\nmovsxd rbp, ebp\nmov byte ptr [rax+rbp], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(char *s)\n{\n size_t v1; // rbx\n int v2; // ebp\n _BYTE *result; // rax\n\n v1 = 0LL;\n v2 = 0;\n while ( v1 < strlen(s) )\n {\n if ( (v1 & 1) == 0 )\n result_1[v2++] = s[v1];\n ++v1;\n }\n result = result_1;\n result_1[v2] = 0;\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12, rdi\nmov ebx, 0\nmov ebp, 0\nlea r13, unk_4040\njmp short loc_11B1\nloc_11AD:\nadd rbx, 1\nloc_11B1:\nmov rdi, r12; s\ncall _strlen\ncmp rbx, rax\njnb short loc_11D5\ntest bl, 1\njnz short loc_11AD\nmovzx edx, byte ptr [r12+rbx]\nmovsxd rax, ebp\nmov [r13+rax+0], dl\nlea ebp, [rbp+1]\njmp short loc_11AD\nloc_11D5:\nlea rax, unk_4040\nmovsxd rbp, ebp\nmov byte ptr [rax+rbp], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1189(char *s)\n{\n size_t v1; // rbx\n int v2; // ebp\n _BYTE *result; // rax\n\n v1 = 0LL;\n v2 = 0;\n while ( v1 < strlen(s) )\n {\n if ( (v1 & 1) == 0 )\n byte_4040[v2++] = s[v1];\n ++v1;\n }\n result = byte_4040;\n byte_4040[v2] = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1189(char *s) {\n unsigned int v1;\n int v2;\n uint8_t *result;\n v1 = 0LL;\n v2 = 0;\n while (v1 < strlen(s)) {\n if ((v1 & 1) == 0) byte_4040[v2++] = s[v1];\n ++v1;\n }\n result = byte_4040;\n byte_4040[v2] = 0;\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(char *s) {\n unsigned int v1;\n int v2;\n uint8_t *result;\n v1 = 0LL;\n v2 = 0;\n while (v1 < strlen(s)) {\n if ((v1 & 1) == 0) result_1[v2++] = s[v1];\n ++v1;\n }\n result = result_1;\n result_1[v2] = 0;\n return result;\n}" + }, + { + "index": 226, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* str) {\n static char result[100];\n int j = 0;\n for (int i = 0; i < strlen(str); i++) {\n if (i % 2 == 0) {\n result[j++] = str[i];\n }\n }\n result[j] = '\\0';\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"abcdef\"), \"ace\") == 0);\n\n assert(strcmp(func0(\"python\"), \"pto\") == 0);\n\n assert(strcmp(func0(\"data\"), \"dt\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov %rdi,%r13\npush %r12\npush %rbp\nlea 0x2ddd(%rip),%rbp\npush %rbx\nxor %ebx,%ebx\nsub $0x8,%rsp\ncallq 1060 \nxor %edx,%edx\njmp 129a \nnopl 0x0(%rax,%rax,1)\ntest $0x1,%bl\njne 1296 \nmovzbl 0x0(%r13,%rbx,1),%eax\nlea 0x1(%rdx),%r12d\nmov %r13,%rdi\nmov %al,0x0(%rbp,%rdx,1)\ncallq 1060 \nmovslq %r12d,%rdx\nadd $0x1,%rbx\ncmp %rax,%rbx\njb 1278 \nmovb $0x0,0x0(%rbp,%rdx,1)\nadd $0x8,%rsp\nlea 0x2d91(%rip),%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r13\nlea r13, result_1\npush r12\nmov r12, rdi\npush rbp\nxor ebp, ebp\npush rbx\nxor ebx, ebx\nsub rsp, 8\njmp short loc_1299\nloc_1280:\ntest bl, 1\njnz short loc_1295\nmovzx edx, byte ptr [r12+rbx]\nmovsxd rax, ebp\nadd ebp, 1\nmov [r13+rax+0], dl\nloc_1295:\nadd rbx, 1\nloc_1299:\nmov rdi, r12; s\ncall _strlen\ncmp rbx, rax\njb short loc_1280\nmovsxd rbp, ebp\nmov rax, r13\nmov byte ptr [r13+rbp+0], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(char *s)\n{\n int v1; // ebp\n size_t i; // rbx\n __int64 v3; // rax\n _BYTE *result; // rax\n\n v1 = 0;\n for ( i = 0LL; i < strlen(s); ++i )\n {\n if ( (i & 1) == 0 )\n {\n v3 = v1++;\n result_1[v3] = s[i];\n }\n }\n result = result_1;\n result_1[v1] = 0;\n return result;\n}", + "ida_strip_asm": "sub_1260:\nendbr64\npush r13\nlea r13, unk_4040\npush r12\nmov r12, rdi\npush rbp\nxor ebp, ebp\npush rbx\nxor ebx, ebx\nsub rsp, 8\njmp short loc_1299\nloc_1280:\ntest bl, 1\njnz short loc_1295\nmovzx edx, byte ptr [r12+rbx]\nmovsxd rax, ebp\nadd ebp, 1\nmov [r13+rax+0], dl\nloc_1295:\nadd rbx, 1\nloc_1299:\nmov rdi, r12; s\ncall _strlen\ncmp rbx, rax\njb short loc_1280\nmovsxd rbp, ebp\nmov rax, r13\nmov byte ptr [r13+rbp+0], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1260(char *s)\n{\n int v1; // ebp\n size_t i; // rbx\n __int64 v3; // rax\n _BYTE *result; // rax\n\n v1 = 0;\n for ( i = 0LL; i < strlen(s); ++i )\n {\n if ( (i & 1) == 0 )\n {\n v3 = v1++;\n byte_4040[v3] = s[i];\n }\n }\n result = byte_4040;\n byte_4040[v1] = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1260(char *s) {\n int v1;\n unsigned int i;\n long long v3;\n uint8_t *result;\n v1 = 0;\n for (i = 0LL; i < strlen(s); ++i) {\n if ((i & 1) == 0) {\n v3 = v1++;\n byte_4040[v3] = s[i];\n }\n }\n result = byte_4040;\n byte_4040[v1] = 0;\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(char *s) {\n int v1;\n unsigned int i;\n long long v3;\n uint8_t *result;\n v1 = 0;\n for (i = 0LL; i < strlen(s); ++i) {\n if ((i & 1) == 0) {\n v3 = v1++;\n result_1[v3] = s[i];\n }\n }\n result = result_1;\n result_1[v1] = 0;\n return result;\n}" + }, + { + "index": 226, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* str) {\n static char result[100];\n int j = 0;\n for (int i = 0; i < strlen(str); i++) {\n if (i % 2 == 0) {\n result[j++] = str[i];\n }\n }\n result[j] = '\\0';\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"abcdef\"), \"ace\") == 0);\n\n assert(strcmp(func0(\"python\"), \"pto\") == 0);\n\n assert(strcmp(func0(\"data\"), \"dt\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\nmov %rdi,%r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\ncallq 1060 \ntest %rax,%rax\nje 12d8 \nxor %edx,%edx\nxor %ebx,%ebx\nlea 0x2dca(%rip),%rbp\nnopw %cs:0x0(%rax,%rax,1)\ntest $0x1,%bl\njne 12ab \nmovzbl (%r12,%rbx,1),%eax\nmov %r12,%rdi\nlea 0x1(%rdx),%r13d\nadd $0x1,%rbx\nmov %al,0x0(%rbp,%rdx,1)\ncallq 1060 \ncmp %rax,%rbx\njae 12b7 \nmovslq %r13d,%rdx\ntest $0x1,%bl\nje 1285 \nadd $0x1,%rbx\ncmp %rax,%rbx\njb 1280 \nmov %edx,%r13d\nmovslq %r13d,%r13\nlea 0x2d7f(%rip),%rax\nmovb $0x0,0x0(%rbp,%r13,1)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopw 0x0(%rax,%rax,1)\nxor %r13d,%r13d\nlea 0x2d5e(%rip),%rbp\njmp 12b7 \nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r13\nlea r13, result_1\npush r12\nmov r12, rdi\npush rbp\nxor ebp, ebp\npush rbx\nxor ebx, ebx\nsub rsp, 8\njmp short loc_1299\nloc_1280:\ntest bl, 1\njnz short loc_1295\nmovzx edx, byte ptr [r12+rbx]\nmovsxd rax, ebp\nadd ebp, 1\nmov [r13+rax+0], dl\nloc_1295:\nadd rbx, 1\nloc_1299:\nmov rdi, r12; s\ncall _strlen\ncmp rbx, rax\njb short loc_1280\nmovsxd rbp, ebp\nmov rax, r13\nmov byte ptr [r13+rbp+0], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(char *s)\n{\n int v1; // ebp\n size_t i; // rbx\n __int64 v3; // rax\n _BYTE *result; // rax\n\n v1 = 0;\n for ( i = 0LL; i < strlen(s); ++i )\n {\n if ( (i & 1) == 0 )\n {\n v3 = v1++;\n result_1[v3] = s[i];\n }\n }\n result = result_1;\n result_1[v1] = 0;\n return result;\n}", + "ida_strip_asm": "sub_1260:\nendbr64\npush r13\nlea r13, unk_4040\npush r12\nmov r12, rdi\npush rbp\nxor ebp, ebp\npush rbx\nxor ebx, ebx\nsub rsp, 8\njmp short loc_1299\nloc_1280:\ntest bl, 1\njnz short loc_1295\nmovzx edx, byte ptr [r12+rbx]\nmovsxd rax, ebp\nadd ebp, 1\nmov [r13+rax+0], dl\nloc_1295:\nadd rbx, 1\nloc_1299:\nmov rdi, r12; s\ncall _strlen\ncmp rbx, rax\njb short loc_1280\nmovsxd rbp, ebp\nmov rax, r13\nmov byte ptr [r13+rbp+0], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1260(char *s)\n{\n int v1; // ebp\n size_t i; // rbx\n __int64 v3; // rax\n _BYTE *result; // rax\n\n v1 = 0;\n for ( i = 0LL; i < strlen(s); ++i )\n {\n if ( (i & 1) == 0 )\n {\n v3 = v1++;\n byte_4040[v3] = s[i];\n }\n }\n result = byte_4040;\n byte_4040[v1] = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1260(char *s) {\n int v1;\n unsigned int i;\n long long v3;\n uint8_t *result;\n v1 = 0;\n for (i = 0LL; i < strlen(s); ++i) {\n if ((i & 1) == 0) {\n v3 = v1++;\n byte_4040[v3] = s[i];\n }\n }\n result = byte_4040;\n byte_4040[v1] = 0;\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(char *s) {\n int v1;\n unsigned int i;\n long long v3;\n uint8_t *result;\n v1 = 0;\n for (i = 0LL; i < strlen(s); ++i) {\n if ((i & 1) == 0) {\n v3 = v1++;\n result_1[v3] = s[i];\n }\n }\n result = result_1;\n result_1[v1] = 0;\n return result;\n}" + }, + { + "index": 227, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int a, int b, int c) {\n int smallest;\n if (a <= b && a <= c) {\n smallest = a;\n } else if (b <= a && b <= c) {\n smallest = b;\n } else {\n smallest = c;\n }\n return smallest;\n}", + "test": "int main() {\n\n assert(func0(10, 20, 0) == 0);\n\n assert(func0(19, 15, 18) == 15);\n\n assert(func0(-10, -20, -30) == -30);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov %edx,-0x1c(%rbp)\nmov -0x14(%rbp),%eax\ncmp -0x18(%rbp),%eax\njg 1172 \nmov -0x14(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njg 1172 \nmov -0x14(%rbp),%eax\nmov %eax,-0x4(%rbp)\njmp 1190 \nmov -0x18(%rbp),%eax\ncmp -0x14(%rbp),%eax\njg 118a \nmov -0x18(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njg 118a \nmov -0x18(%rbp),%eax\nmov %eax,-0x4(%rbp)\njmp 1190 \nmov -0x1c(%rbp),%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_18]\njg short loc_1172\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_1C]\njg short loc_1172\nmov eax, [rbp+var_14]\nmov [rbp+var_4], eax\njmp short loc_1190\nloc_1172:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_14]\njg short loc_118A\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_1C]\njg short loc_118A\nmov eax, [rbp+var_18]\nmov [rbp+var_4], eax\njmp short loc_1190\nloc_118A:\nmov eax, [rbp+var_1C]\nmov [rbp+var_4], eax\nloc_1190:\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(signed int a1, signed int a2, signed int a3)\n{\n if ( a1 > a2 || a1 > a3 )\n {\n if ( a2 > a1 || a2 > a3 )\n return (unsigned int)a3;\n else\n return (unsigned int)a2;\n }\n else\n {\n return (unsigned int)a1;\n }\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_18]\njg short loc_1172\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_1C]\njg short loc_1172\nmov eax, [rbp+var_14]\nmov [rbp+var_4], eax\njmp short loc_1190\nloc_1172:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_14]\njg short loc_118A\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_1C]\njg short loc_118A\nmov eax, [rbp+var_18]\nmov [rbp+var_4], eax\njmp short loc_1190\nloc_118A:\nmov eax, [rbp+var_1C]\nmov [rbp+var_4], eax\nloc_1190:\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(signed int a1, signed int a2, signed int a3)\n{\n if ( a1 > a2 || a1 > a3 )\n {\n if ( a2 > a1 || a2 > a3 )\n return (unsigned int)a3;\n else\n return (unsigned int)a2;\n }\n else\n {\n return (unsigned int)a1;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(signed int a1, signed int a2, signed int a3) {\n if (a1 > a2 || a1 > a3) {\n if (a2 > a1 || a2 > a3)\n return (unsigned int)a3;\n else\n return (unsigned int)a2;\n } else {\n return (unsigned int)a1;\n }\n}", + "ida_pseudo_norm": "long long func0(signed int a1, signed int a2, signed int a3) {\n if (a1 > a2 || a1 > a3) {\n if (a2 > a1 || a2 > a3)\n return (unsigned int)a3;\n else\n return (unsigned int)a2;\n } else {\n return (unsigned int)a1;\n }\n}" + }, + { + "index": 228, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int n, int l, int r) {\n int num = (((1 << r) - 1) ^ ((1 << (l - 1)) - 1));\n int new_num = n & num;\n if (new_num == 0) {\n return true;\n }\n return false;\n}", + "test": "int main() {\n\n assert(func0(4, 1, 2) == true);\n\n assert(func0(17, 2, 4) == true);\n\n assert(func0(39, 4, 6) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov %edx,-0x1c(%rbp)\nmov -0x1c(%rbp),%eax\nmov $0x1,%edx\nmov %eax,%ecx\nshl %cl,%edx\nmov %edx,%eax\nlea -0x1(%rax),%edx\nmov -0x18(%rbp),%eax\nsub $0x1,%eax\nmov $0x1,%esi\nmov %eax,%ecx\nshl %cl,%esi\nmov %esi,%eax\nsub $0x1,%eax\nxor %edx,%eax\nmov %eax,-0x8(%rbp)\nmov -0x14(%rbp),%eax\nand -0x8(%rbp),%eax\nmov %eax,-0x4(%rbp)\ncmpl $0x0,-0x4(%rbp)\njne 119a \nmov $0x1,%eax\njmp 119f \nmov $0x0,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov eax, [rbp+var_1C]\nmov edx, 1\nmov ecx, eax\nshl edx, cl\nmov eax, edx\nlea edx, [rax-1]\nmov eax, [rbp+var_18]\nsub eax, 1\nmov esi, 1\nmov ecx, eax\nshl esi, cl\nmov eax, esi\nsub eax, 1\nxor eax, edx\nmov [rbp+var_8], eax\nmov eax, [rbp+var_14]\nand eax, [rbp+var_8]\nmov [rbp+var_4], eax\ncmp [rbp+var_4], 0\njnz short loc_119A\nmov eax, 1\njmp short loc_119F\nloc_119A:\nmov eax, 0\nloc_119F:\npop rbp\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(int a1, char a2, char a3)\n{\n return ((((1 << a3) - 1) ^ ((1 << (a2 - 1)) - 1)) & a1) == 0;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov eax, [rbp+var_1C]\nmov edx, 1\nmov ecx, eax\nshl edx, cl\nmov eax, edx\nlea edx, [rax-1]\nmov eax, [rbp+var_18]\nsub eax, 1\nmov esi, 1\nmov ecx, eax\nshl esi, cl\nmov eax, esi\nsub eax, 1\nxor eax, edx\nmov [rbp+var_8], eax\nmov eax, [rbp+var_14]\nand eax, [rbp+var_8]\nmov [rbp+var_4], eax\ncmp [rbp+var_4], 0\njnz short loc_119A\nmov eax, 1\njmp short loc_119F\nloc_119A:\nmov eax, 0\nloc_119F:\npop rbp\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1149(int a1, char a2, char a3)\n{\n return ((((1 << a3) - 1) ^ ((1 << (a2 - 1)) - 1)) & a1) == 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1149(int a1, char a2, char a3) {\n return ((((1 << a3) - 1) ^ ((1 << (a2 - 1)) - 1)) & a1) == 0;\n}", + "ida_pseudo_norm": "uint8_t func0(int a1, char a2, char a3) {\n return ((((1 << a3) - 1) ^ ((1 << (a2 - 1)) - 1)) & a1) == 0;\n}" + }, + { + "index": 229, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nvoid re_arrange_array(int arr[], int n) {\n\n int j = 0;\n\n for (int i = 0; i < n; i++) {\n\n if (arr[i] < 0) {\n\n int temp = arr[i];\n\n arr[i] = arr[j];\n\n arr[j] = temp;\n\n j++;\n\n }\n\n }\n\n}\n\n\n\n", + "func": "bool func0(int arr1[], int arr2[], int n) {\n for (int i = 0; i < n; i++) {\n if (arr1[i] != arr2[i]) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n int arr1[] = {-1, 2, -3, 4, 5, 6, -7, 8, 9};\n\n int n1 = 9;\n\n re_arrange_array(arr1, n1);\n\n int expected1[] = {-1, -3, -7, 4, 5, 6, 2, 8, 9};\n\n assert(func0(arr1, expected1, n1));\n\n\n\n int arr2[] = {12, -14, -26, 13, 15};\n\n int n2 = 5;\n\n re_arrange_array(arr2, n2);\n\n int expected2[] = {-14, -26, 12, 13, 15};\n\n assert(func0(arr2, expected2, n2));\n\n\n\n int arr3[] = {10, 24, 36, -42, -39, -78, 85};\n\n int n3 = 7;\n\n re_arrange_array(arr3, n3);\n\n int expected3[] = {-42, -39, -78, 10, 24, 36, 85};\n\n assert(func0(arr3, expected3, n3));\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %edx,-0x24(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 1273 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x20(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\nje 126f \nmov $0x0,%eax\njmp 1280 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x24(%rbp),%eax\njl 1238 \nmov $0x1,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_4], 0\njmp short loc_1273\nloc_1238:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_126F\nmov eax, 0\njmp short loc_1280\nloc_126F:\nadd [rbp+var_4], 1\nloc_1273:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_24]\njl short loc_1238\nmov eax, 1\nloc_1280:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n int i; // [rsp+20h] [rbp-4h]\n\n for ( i = 0; i < a3; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) != *(_DWORD *)(4LL * i + a2) )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_121C:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_4], 0\njmp short loc_1273\nloc_1238:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_126F\nmov eax, 0\njmp short loc_1280\nloc_126F:\nadd [rbp+var_4], 1\nloc_1273:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_24]\njl short loc_1238\nmov eax, 1\nloc_1280:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_121C(__int64 a1, __int64 a2, int a3)\n{\n int i; // [rsp+20h] [rbp-4h]\n\n for ( i = 0; i < a3; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) != *(_DWORD *)(4LL * i + a2) )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_121C(long long a1, long long a2, int a3) {\n int i;\n for (i = 0; i < a3; ++i) {\n if (*(uint32_t *)(4LL * i + a1) != *(uint32_t *)(4LL * i + a2)) return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3) {\n int i;\n for (i = 0; i < a3; ++i) {\n if (*(uint32_t *)(4LL * i + a1) != *(uint32_t *)(4LL * i + a2)) return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": 229, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nvoid re_arrange_array(int arr[], int n) {\n\n int j = 0;\n\n for (int i = 0; i < n; i++) {\n\n if (arr[i] < 0) {\n\n int temp = arr[i];\n\n arr[i] = arr[j];\n\n arr[j] = temp;\n\n j++;\n\n }\n\n }\n\n}\n\n\n\n", + "func": "bool func0(int arr1[], int arr2[], int n) {\n for (int i = 0; i < n; i++) {\n if (arr1[i] != arr2[i]) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n int arr1[] = {-1, 2, -3, 4, 5, 6, -7, 8, 9};\n\n int n1 = 9;\n\n re_arrange_array(arr1, n1);\n\n int expected1[] = {-1, -3, -7, 4, 5, 6, 2, 8, 9};\n\n assert(func0(arr1, expected1, n1));\n\n\n\n int arr2[] = {12, -14, -26, 13, 15};\n\n int n2 = 5;\n\n re_arrange_array(arr2, n2);\n\n int expected2[] = {-14, -26, 12, 13, 15};\n\n assert(func0(arr2, expected2, n2));\n\n\n\n int arr3[] = {10, 24, 36, -42, -39, -78, 85};\n\n int n3 = 7;\n\n re_arrange_array(arr3, n3);\n\n int expected3[] = {-42, -39, -78, 10, 24, 36, 85};\n\n assert(func0(arr3, expected3, n3));\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edx,%edx\njle 11d3 \nlea -0x1(%rdx),%ecx\nmov $0x0,%eax\njmp 11bc \nmov %rdx,%rax\nmov (%rsi,%rax,4),%edx\ncmp %edx,(%rdi,%rax,4)\njne 11d9 \nlea 0x1(%rax),%rdx\ncmp %rcx,%rax\njne 11b9 \nmov $0x1,%eax\nretq\nmov $0x1,%eax\nretq\nmov $0x0,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest edx, edx\njle short loc_11D1\nmovsxd rdx, edx\nshl rdx, 2\nmov eax, 0\nloc_11BA:\nmov ecx, [rsi+rax]\ncmp [rdi+rax], ecx\njnz short loc_11D7\nadd rax, 4\ncmp rax, rdx\njnz short loc_11BA\nmov eax, 1\nretn\nloc_11D1:\nmov eax, 1\nretn\nloc_11D7:\nmov eax, 0\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n __int64 v3; // rdx\n __int64 v4; // rax\n\n if ( a3 <= 0 )\n return 1LL;\n v3 = 4LL * a3;\n v4 = 0LL;\n while ( *(_DWORD *)(a1 + v4) == *(_DWORD *)(a2 + v4) )\n {\n v4 += 4LL;\n if ( v4 == v3 )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_11A6:\nendbr64\ntest edx, edx\njle short loc_11D1\nmovsxd rdx, edx\nshl rdx, 2\nmov eax, 0\nloc_11BA:\nmov ecx, [rsi+rax]\ncmp [rdi+rax], ecx\njnz short loc_11D7\nadd rax, 4\ncmp rax, rdx\njnz short loc_11BA\nmov eax, 1\nretn\nloc_11D1:\nmov eax, 1\nretn\nloc_11D7:\nmov eax, 0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11A6(__int64 a1, __int64 a2, int a3)\n{\n __int64 v3; // rdx\n __int64 v4; // rax\n\n if ( a3 <= 0 )\n return 1LL;\n v3 = 4LL * a3;\n v4 = 0LL;\n while ( *(_DWORD *)(a1 + v4) == *(_DWORD *)(a2 + v4) )\n {\n v4 += 4LL;\n if ( v4 == v3 )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A6(long long a1, long long a2, int a3) {\n long long v3;\n long long v4;\n if (a3 <= 0) return 1LL;\n v3 = 4LL * a3;\n v4 = 0LL;\n while (*(uint32_t *)(a1 + v4) == *(uint32_t *)(a2 + v4)) {\n v4 += 4LL;\n if (v4 == v3) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3) {\n long long v3;\n long long v4;\n if (a3 <= 0) return 1LL;\n v3 = 4LL * a3;\n v4 = 0LL;\n while (*(uint32_t *)(a1 + v4) == *(uint32_t *)(a2 + v4)) {\n v4 += 4LL;\n if (v4 == v3) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 230, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* str1, char* char_replacement) {\n static char str2[100];\n int j = 0;\n for (int i = 0; str1[i] != '\\0'; i++) {\n if (str1[i] == ' ') {\n str2[j++] = char_replacement[0];\n } else {\n str2[j++] = str1[i];\n }\n }\n str2[j] = '\\0';\n return str2;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"hello people\", \"@\"), \"hello@people\") == 0);\n\n assert(strcmp(func0(\"python program language\", \"$\"), \"python$program$language\") == 0);\n\n assert(strcmp(func0(\"blank space\", \"-\"), \"blank-space\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11e5 \nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x20,%al\njne 11bb \nmov -0x8(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x8(%rbp)\nmov -0x20(%rbp),%rdx\nmovzbl (%rdx),%edx\ncltq\nlea 0x2e8a(%rip),%rcx\nmov %dl,(%rax,%rcx,1)\njmp 11e1 \nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x8(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x8(%rbp)\nmovzbl (%rcx),%edx\ncltq\nlea 0x2e62(%rip),%rcx\nmov %dl,(%rax,%rcx,1)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 1189 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x2e3b(%rip),%rdx\nmovb $0x0,(%rax,%rdx,1)\nlea 0x2e30(%rip),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11E5\nloc_1189:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njnz short loc_11BB\nmov eax, [rbp+var_8]\nlea edx, [rax+1]\nmov [rbp+var_8], edx\nmov rdx, [rbp+var_20]\nmovzx edx, byte ptr [rdx]\ncdqe\nlea rcx, str2_1\nmov [rax+rcx], dl\njmp short loc_11E1\nloc_11BB:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_8]\nlea edx, [rax+1]\nmov [rbp+var_8], edx\nmovzx edx, byte ptr [rcx]\ncdqe\nlea rcx, str2_1\nmov [rax+rcx], dl\nloc_11E1:\nadd [rbp+var_4], 1\nloc_11E5:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1189\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, str2_1\nmov byte ptr [rax+rdx], 0\nlea rax, str2_1\npop rbp\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(__int64 a1, char *a2)\n{\n int v2; // eax\n char v3; // dl\n int v5; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v5 = 0;\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n {\n v2 = v5++;\n if ( *(_BYTE *)(i + a1) == 32 )\n v3 = *a2;\n else\n v3 = *(_BYTE *)(i + a1);\n str2_1[v2] = v3;\n }\n str2_1[v5] = 0;\n return str2_1;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11E5\nloc_1189:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njnz short loc_11BB\nmov eax, [rbp+var_8]\nlea edx, [rax+1]\nmov [rbp+var_8], edx\nmov rdx, [rbp+var_20]\nmovzx edx, byte ptr [rdx]\ncdqe\nlea rcx, unk_4040\nmov [rax+rcx], dl\njmp short loc_11E1\nloc_11BB:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_8]\nlea edx, [rax+1]\nmov [rbp+var_8], edx\nmovzx edx, byte ptr [rcx]\ncdqe\nlea rcx, unk_4040\nmov [rax+rcx], dl\nloc_11E1:\nadd [rbp+var_4], 1\nloc_11E5:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1189\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, unk_4040\nmov byte ptr [rax+rdx], 0\nlea rax, unk_4040\npop rbp\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1169(__int64 a1, char *a2)\n{\n int v2; // eax\n char v3; // dl\n int v5; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v5 = 0;\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n {\n v2 = v5++;\n if ( *(_BYTE *)(i + a1) == 32 )\n v3 = *a2;\n else\n v3 = *(_BYTE *)(i + a1);\n byte_4040[v2] = v3;\n }\n byte_4040[v5] = 0;\n return byte_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1169(long long a1, char *a2) {\n int v2;\n char v3;\n int v5;\n int i;\n v5 = 0;\n for (i = 0; *(uint8_t *)(i + a1); ++i) {\n v2 = v5++;\n if (*(uint8_t *)(i + a1) == 32)\n v3 = *a2;\n else\n v3 = *(uint8_t *)(i + a1);\n byte_4040[v2] = v3;\n }\n byte_4040[v5] = 0;\n return byte_4040;\n}", + "ida_pseudo_norm": "uint8_t *func0(long long a1, char *a2) {\n int v2;\n char v3;\n int v5;\n int i;\n v5 = 0;\n for (i = 0; *(uint8_t *)(i + a1); ++i) {\n v2 = v5++;\n if (*(uint8_t *)(i + a1) == 32)\n v3 = *a2;\n else\n v3 = *(uint8_t *)(i + a1);\n str2_1[v2] = v3;\n }\n str2_1[v5] = 0;\n return str2_1;\n}" + }, + { + "index": 230, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* str1, char* char_replacement) {\n static char str2[100];\n int j = 0;\n for (int i = 0; str1[i] != '\\0'; i++) {\n if (str1[i] == ' ') {\n str2[j++] = char_replacement[0];\n } else {\n str2[j++] = str1[i];\n }\n }\n str2[j] = '\\0';\n return str2;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"hello people\", \"@\"), \"hello@people\") == 0);\n\n assert(strcmp(func0(\"python program language\", \"$\"), \"python$program$language\") == 0);\n\n assert(strcmp(func0(\"blank space\", \"-\"), \"blank-space\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmovzbl (%rdi),%edx\ntest %dl,%dl\nje 117f \nmov $0x1,%eax\nlea 0x2edf(%rip),%r8\njmp 1173 \nmov %dl,(%rax,%r8,1)\nadd $0x1,%rax\nmovzbl -0x1(%rdi,%rax,1),%edx\ntest %dl,%dl\nje 1184 \nmov %eax,%ecx\ncmp $0x20,%dl\njne 1162 \nmovzbl (%rsi),%edx\njmp 1162 \nmov $0x0,%ecx\nlea 0x2eb5(%rip),%rax\nmovslq %ecx,%rcx\nmovb $0x0,(%rax,%rcx,1)\nretq\n", + "ida_asm": "func0:\nendbr64\nmovzx edx, byte ptr [rdi]\ntest dl, dl\njz short loc_119F\nmov eax, 1\nlea r8, unk_403F\njmp short loc_1193\nloc_1182:\nmov [rax+r8], dl\nadd rax, 1\nmovzx edx, byte ptr [rdi+rax-1]\ntest dl, dl\njz short loc_11A4\nloc_1193:\nmov ecx, eax\ncmp dl, 20h ; ' '\njnz short loc_1182\nmovzx edx, byte ptr [rsi]\njmp short loc_1182\nloc_119F:\nmov ecx, 0\nloc_11A4:\nlea rax, str2_1\nmovsxd rcx, ecx\nmov byte ptr [rax+rcx], 0\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(char *a1, char *a2)\n{\n char v2; // dl\n __int64 v3; // rax\n int v4; // ecx\n _BYTE *result; // rax\n\n v2 = *a1;\n if ( *a1 )\n {\n v3 = 1LL;\n do\n {\n v4 = v3;\n if ( v2 == 32 )\n v2 = *a2;\n *((_BYTE *)&unk_403F + v3++) = v2;\n v2 = a1[v3 - 1];\n }\n while ( v2 );\n }\n else\n {\n v4 = 0;\n }\n result = str2_1;\n str2_1[v4] = 0;\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmovzx edx, byte ptr [rdi]\ntest dl, dl\njz short loc_119F\nmov eax, 1\nlea r8, unk_403F\njmp short loc_1193\nloc_1182:\nmov [rax+r8], dl\nadd rax, 1\nmovzx edx, byte ptr [rdi+rax-1]\ntest dl, dl\njz short loc_11A4\nloc_1193:\nmov ecx, eax\ncmp dl, 20h ; ' '\njnz short loc_1182\nmovzx edx, byte ptr [rsi]\njmp short loc_1182\nloc_119F:\nmov ecx, 0\nloc_11A4:\nlea rax, unk_4040\nmovsxd rcx, ecx\nmov byte ptr [rax+rcx], 0\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1169(char *a1, char *a2)\n{\n char v2; // dl\n __int64 v3; // rax\n int v4; // ecx\n _BYTE *result; // rax\n\n v2 = *a1;\n if ( *a1 )\n {\n v3 = 1LL;\n do\n {\n v4 = v3;\n if ( v2 == 32 )\n v2 = *a2;\n *((_BYTE *)&unk_403F + v3++) = v2;\n v2 = a1[v3 - 1];\n }\n while ( v2 );\n }\n else\n {\n v4 = 0;\n }\n result = byte_4040;\n byte_4040[v4] = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1169(char *a1, char *a2) {\n char v2;\n long long v3;\n int v4;\n uint8_t *result;\n v2 = *a1;\n if (*a1) {\n v3 = 1LL;\n do {\n v4 = v3;\n if (v2 == 32) v2 = *a2;\n *((uint8_t *)&unk_403F + v3++) = v2;\n v2 = a1[v3 - 1];\n } while (v2);\n } else {\n v4 = 0;\n }\n result = byte_4040;\n byte_4040[v4] = 0;\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(char *a1, char *a2) {\n char v2;\n long long v3;\n int v4;\n uint8_t *result;\n v2 = *a1;\n if (*a1) {\n v3 = 1LL;\n do {\n v4 = v3;\n if (v2 == 32) v2 = *a2;\n *((uint8_t *)&unk_403F + v3++) = v2;\n v2 = a1[v3 - 1];\n } while (v2);\n } else {\n v4 = 0;\n }\n result = str2_1;\n str2_1[v4] = 0;\n return result;\n}" + }, + { + "index": 230, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* str1, char* char_replacement) {\n static char str2[100];\n int j = 0;\n for (int i = 0; str1[i] != '\\0'; i++) {\n if (str1[i] == ' ') {\n str2[j++] = char_replacement[0];\n } else {\n str2[j++] = str1[i];\n }\n }\n str2[j] = '\\0';\n return str2;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"hello people\", \"@\"), \"hello@people\") == 0);\n\n assert(strcmp(func0(\"python program language\", \"$\"), \"python$program$language\") == 0);\n\n assert(strcmp(func0(\"blank space\", \"-\"), \"blank-space\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmovzbl (%rdi),%edx\ntest %dl,%dl\nje 1350 \nmov $0x1,%eax\nlea 0x2d28(%rip),%r8\nnopw 0x0(%rax,%rax,1)\nmovslq %eax,%rcx\ncmp $0x20,%dl\njne 132b \nmovzbl (%rsi),%edx\nmov %dl,(%r8,%rax,1)\nadd $0x1,%rax\nmovzbl -0x1(%rdi,%rax,1),%edx\ntest %dl,%dl\njne 1320 \nlea 0x2cfd(%rip),%rax\nmovb $0x0,(%rax,%rcx,1)\nretq\nnopl 0x0(%rax,%rax,1)\nxor %ecx,%ecx\nlea 0x2ce7(%rip),%rax\nmovb $0x0,(%rax,%rcx,1)\nretq\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\nmovzx eax, byte ptr [rdi]\ntest al, al\njz short loc_12A0\nmov edx, 1\nlea r8, unk_403F\njmp short loc_1273\nloc_1270:\nmov rdx, rcx\nloc_1273:\ncmp al, 20h ; ' '\njnz short loc_127A\nmovzx eax, byte ptr [rsi]\nloc_127A:\nlea rcx, [rdx+1]\nmov [r8+rdx], al\nmovzx eax, byte ptr [rdi+rcx-1]\ntest al, al\njnz short loc_1270\nlea rax, str2_1\nmovsxd rdx, edx\nmov byte ptr [rax+rdx], 0\nretn\nloc_12A0:\nxor edx, edx\nlea rax, str2_1\nmovsxd rdx, edx\nmov byte ptr [rax+rdx], 0\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(char *a1, char *a2)\n{\n char v2; // al\n __int64 i; // rdx\n _BYTE *result; // rax\n\n v2 = *a1;\n if ( *a1 )\n {\n for ( i = 1LL; ; ++i )\n {\n if ( v2 == 32 )\n v2 = *a2;\n *((_BYTE *)&unk_403F + i) = v2;\n v2 = a1[i];\n if ( !v2 )\n break;\n }\n result = str2_1;\n str2_1[(int)i] = 0;\n }\n else\n {\n result = str2_1;\n str2_1[0] = 0;\n }\n return result;\n}", + "ida_strip_asm": "sub_1250:\nendbr64\nmovzx eax, byte ptr [rdi]\ntest al, al\njz short loc_12A0\nmov edx, 1\nlea r8, unk_403F\njmp short loc_1273\nloc_1270:\nmov rdx, rcx\nloc_1273:\ncmp al, 20h ; ' '\njnz short loc_127A\nmovzx eax, byte ptr [rsi]\nloc_127A:\nlea rcx, [rdx+1]\nmov [r8+rdx], al\nmovzx eax, byte ptr [rdi+rcx-1]\ntest al, al\njnz short loc_1270\nlea rax, unk_4040\nmovsxd rdx, edx\nmov byte ptr [rax+rdx], 0\nretn\nloc_12A0:\nxor edx, edx\nlea rax, unk_4040\nmovsxd rdx, edx\nmov byte ptr [rax+rdx], 0\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1250(char *a1, char *a2)\n{\n char v2; // al\n __int64 i; // rdx\n _BYTE *result; // rax\n\n v2 = *a1;\n if ( *a1 )\n {\n for ( i = 1LL; ; ++i )\n {\n if ( v2 == 32 )\n v2 = *a2;\n *((_BYTE *)&unk_403F + i) = v2;\n v2 = a1[i];\n if ( !v2 )\n break;\n }\n result = byte_4040;\n byte_4040[(int)i] = 0;\n }\n else\n {\n result = byte_4040;\n byte_4040[0] = 0;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1250(char *a1, char *a2) {\n char v2;\n long long i;\n uint8_t *result;\n v2 = *a1;\n if (*a1) {\n for (i = 1LL;; ++i) {\n if (v2 == 32) v2 = *a2;\n *((uint8_t *)&unk_403F + i) = v2;\n v2 = a1[i];\n if (!v2) break;\n }\n result = byte_4040;\n byte_4040[(int)i] = 0;\n } else {\n result = byte_4040;\n byte_4040[0] = 0;\n }\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(char *a1, char *a2) {\n char v2;\n long long i;\n uint8_t *result;\n v2 = *a1;\n if (*a1) {\n for (i = 1LL;; ++i) {\n if (v2 == 32) v2 = *a2;\n *((uint8_t *)&unk_403F + i) = v2;\n v2 = a1[i];\n if (!v2) break;\n }\n result = str2_1;\n str2_1[(int)i] = 0;\n } else {\n result = str2_1;\n str2_1[0] = 0;\n }\n return result;\n}" + }, + { + "index": 231, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int tri[][100], int n) {\n if (n > 1) {\n tri[1][1] = tri[1][1] + tri[0][0];\n tri[1][0] = tri[1][0] + tri[0][0];\n }\n for (int i = 2; i < n; i++) {\n tri[i][0] = tri[i][0] + tri[i - 1][0];\n tri[i][i] = tri[i][i] + tri[i - 1][i - 1];\n for (int j = 1; j < i; j++) {\n if (tri[i][j] + tri[i - 1][j - 1] >= tri[i][j] + tri[i - 1][j]) {\n tri[i][j] = tri[i][j] + tri[i - 1][j - 1];\n } else {\n tri[i][j] = tri[i][j] + tri[i - 1][j];\n }\n }\n }\n int max_value = tri[n - 1][0];\n for (int j = 1; j < n; j++) {\n if (tri[n - 1][j] > max_value) {\n max_value = tri[n - 1][j];\n }\n }\n return max_value;\n}", + "test": "int main() {\n\n int tri1[3][100] = {{1}, {2, 1}, {3, 3, 2}};\n\n assert(func0(tri1, 3) == 6);\n\n\n\n int tri2[3][100] = {{1}, {1, 2}, {4, 1, 12}};\n\n assert(func0(tri2, 3) == 15);\n\n\n\n int tri3[3][100] = {{2}, {3, 2}, {13, 23, 12}};\n\n assert(func0(tri3, 3) == 28);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\ncmpl $0x1,-0x1c(%rbp)\njle 11c0 \nmov -0x18(%rbp),%rax\nadd $0x190,%rax\nmov 0x4(%rax),%ecx\nmov -0x18(%rbp),%rax\nmov (%rax),%edx\nmov -0x18(%rbp),%rax\nadd $0x190,%rax\nadd %ecx,%edx\nmov %edx,0x4(%rax)\nmov -0x18(%rbp),%rax\nadd $0x190,%rax\nmov (%rax),%ecx\nmov -0x18(%rbp),%rax\nmov (%rax),%edx\nmov -0x18(%rbp),%rax\nadd $0x190,%rax\nadd %ecx,%edx\nmov %edx,(%rax)\nmovl $0x2,-0x10(%rbp)\njmpq 14bf \nmov -0x10(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%esi\nmov -0x10(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nshl $0x4,%rax\nlea -0x190(%rax),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%ecx\nmov -0x10(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nlea (%rsi,%rcx,1),%edx\nmov %edx,(%rax)\nmov -0x10(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0x10(%rbp),%eax\ncltq\nmov (%rdx,%rax,4),%esi\nmov -0x10(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nshl $0x4,%rax\nlea -0x190(%rax),%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0x10(%rbp),%eax\nsub $0x1,%eax\ncltq\nmov (%rdx,%rax,4),%ecx\nmov -0x10(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nadd %esi,%ecx\nmov -0x10(%rbp),%eax\ncltq\nmov %ecx,(%rdx,%rax,4)\nmovl $0x1,-0xc(%rbp)\njmpq 14af \nmov -0x10(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nshl $0x4,%rax\nlea -0x190(%rax),%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0xc(%rbp),%eax\nsub $0x1,%eax\ncltq\nmov (%rdx,%rax,4),%ecx\nmov -0x10(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nshl $0x4,%rax\nlea -0x190(%rax),%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0xc(%rbp),%eax\ncltq\nmov (%rdx,%rax,4),%eax\ncmp %eax,%ecx\njl 1412 \nmov -0x10(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0xc(%rbp),%eax\ncltq\nmov (%rdx,%rax,4),%esi\nmov -0x10(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nshl $0x4,%rax\nlea -0x190(%rax),%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0xc(%rbp),%eax\nsub $0x1,%eax\ncltq\nmov (%rdx,%rax,4),%ecx\nmov -0x10(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nadd %esi,%ecx\nmov -0xc(%rbp),%eax\ncltq\nmov %ecx,(%rdx,%rax,4)\njmpq 14ab \nmov -0x10(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0xc(%rbp),%eax\ncltq\nmov (%rdx,%rax,4),%esi\nmov -0x10(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nshl $0x4,%rax\nlea -0x190(%rax),%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0xc(%rbp),%eax\ncltq\nmov (%rdx,%rax,4),%ecx\nmov -0x10(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nadd %esi,%ecx\nmov -0xc(%rbp),%eax\ncltq\nmov %ecx,(%rdx,%rax,4)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x10(%rbp),%eax\njl 12fc \naddl $0x1,-0x10(%rbp)\nmov -0x10(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11cc \nmov -0x1c(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nshl $0x4,%rax\nlea -0x190(%rax),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x8(%rbp)\nmovl $0x1,-0x4(%rbp)\njmp 157c \nmov -0x1c(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nshl $0x4,%rax\nlea -0x190(%rax),%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0x4(%rbp),%eax\ncltq\nmov (%rdx,%rax,4),%eax\ncmp %eax,-0x8(%rbp)\njge 1578 \nmov -0x1c(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nshl $0x4,%rax\nlea -0x190(%rax),%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0x4(%rbp),%eax\ncltq\nmov (%rdx,%rax,4),%eax\nmov %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1506 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\ncmp [rbp+var_1C], 1\njle short loc_11C0\nmov rax, [rbp+var_18]\nadd rax, 190h\nmov ecx, [rax+4]\nmov rax, [rbp+var_18]\nmov edx, [rax]\nmov rax, [rbp+var_18]\nadd rax, 190h\nadd edx, ecx\nmov [rax+4], edx\nmov rax, [rbp+var_18]\nadd rax, 190h\nmov ecx, [rax]\nmov rax, [rbp+var_18]\nmov edx, [rax]\nmov rax, [rbp+var_18]\nadd rax, 190h\nadd edx, ecx\nmov [rax], edx\nloc_11C0:\nmov [rbp+var_10], 2\njmp loc_14BF\nloc_11CC:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov esi, [rax]\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nlea rdx, [rax-190h]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov ecx, [rax]\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rax, rdx\nlea edx, [rsi+rcx]\nmov [rax], edx\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_10]\ncdqe\nmov esi, [rdx+rax*4]\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nlea rdx, [rax-190h]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_10]\nsub eax, 1\ncdqe\nmov ecx, [rdx+rax*4]\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nadd ecx, esi\nmov eax, [rbp+var_10]\ncdqe\nmov [rdx+rax*4], ecx\nmov [rbp+var_C], 1\njmp loc_14AF\nloc_12FC:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nlea rdx, [rax-190h]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_C]\nsub eax, 1\ncdqe\nmov ecx, [rdx+rax*4]\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nlea rdx, [rax-190h]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_C]\ncdqe\nmov eax, [rdx+rax*4]\ncmp ecx, eax\njl loc_1412\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_C]\ncdqe\nmov esi, [rdx+rax*4]\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nlea rdx, [rax-190h]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_C]\nsub eax, 1\ncdqe\nmov ecx, [rdx+rax*4]\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nadd ecx, esi\nmov eax, [rbp+var_C]\ncdqe\nmov [rdx+rax*4], ecx\njmp loc_14AB\nloc_1412:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_C]\ncdqe\nmov esi, [rdx+rax*4]\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nlea rdx, [rax-190h]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_C]\ncdqe\nmov ecx, [rdx+rax*4]\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nadd ecx, esi\nmov eax, [rbp+var_C]\ncdqe\nmov [rdx+rax*4], ecx\nloc_14AB:\nadd [rbp+var_C], 1\nloc_14AF:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_10]\njl loc_12FC\nadd [rbp+var_10], 1\nloc_14BF:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_1C]\njl loc_11CC\nmov eax, [rbp+var_1C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nlea rdx, [rax-190h]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_8], eax\nmov [rbp+var_4], 1\njmp short loc_157C\nloc_1506:\nmov eax, [rbp+var_1C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nlea rdx, [rax-190h]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\ncdqe\nmov eax, [rdx+rax*4]\ncmp [rbp+var_8], eax\njge short loc_1578\nmov eax, [rbp+var_1C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nlea rdx, [rax-190h]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\ncdqe\nmov eax, [rdx+rax*4]\nmov [rbp+var_8], eax\nloc_1578:\nadd [rbp+var_4], 1\nloc_157C:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1506\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n int v2; // ecx\n int i; // [rsp+Ch] [rbp-10h]\n int j; // [rsp+10h] [rbp-Ch]\n unsigned int v6; // [rsp+14h] [rbp-8h]\n int k; // [rsp+18h] [rbp-4h]\n\n if ( a2 > 1 )\n {\n a1[101] += *a1;\n a1[100] += *a1;\n }\n for ( i = 2; i < a2; ++i )\n {\n a1[100 * i] += a1[100 * i - 100];\n a1[100 * i + i] += a1[100 * i - 101 + i];\n for ( j = 1; j < i; ++j )\n {\n if ( a1[100 * i - 101 + j] < a1[100 * i - 100 + j] )\n v2 = a1[100 * i - 100 + j];\n else\n v2 = a1[100 * i - 101 + j];\n a1[100 * i + j] += v2;\n }\n }\n v6 = a1[100 * a2 - 100];\n for ( k = 1; k < a2; ++k )\n {\n if ( (signed int)v6 < a1[100 * a2 - 100 + k] )\n v6 = a1[100 * a2 - 100 + k];\n }\n return v6;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\ncmp [rbp+var_1C], 1\njle short loc_11C0\nmov rax, [rbp+var_18]\nadd rax, 190h\nmov ecx, [rax+4]\nmov rax, [rbp+var_18]\nmov edx, [rax]\nmov rax, [rbp+var_18]\nadd rax, 190h\nadd edx, ecx\nmov [rax+4], edx\nmov rax, [rbp+var_18]\nadd rax, 190h\nmov ecx, [rax]\nmov rax, [rbp+var_18]\nmov edx, [rax]\nmov rax, [rbp+var_18]\nadd rax, 190h\nadd edx, ecx\nmov [rax], edx\nloc_11C0:\nmov [rbp+var_10], 2\njmp loc_14BF\nloc_11CC:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov esi, [rax]\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nlea rdx, [rax-190h]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov ecx, [rax]\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rax, rdx\nlea edx, [rsi+rcx]\nmov [rax], edx\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_10]\ncdqe\nmov esi, [rdx+rax*4]\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nlea rdx, [rax-190h]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_10]\nsub eax, 1\ncdqe\nmov ecx, [rdx+rax*4]\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nadd ecx, esi\nmov eax, [rbp+var_10]\ncdqe\nmov [rdx+rax*4], ecx\nmov [rbp+var_C], 1\njmp loc_14AF\nloc_12FC:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nlea rdx, [rax-190h]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_C]\nsub eax, 1\ncdqe\nmov ecx, [rdx+rax*4]\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nlea rdx, [rax-190h]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_C]\ncdqe\nmov eax, [rdx+rax*4]\ncmp ecx, eax\njl loc_1412\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_C]\ncdqe\nmov esi, [rdx+rax*4]\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nlea rdx, [rax-190h]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_C]\nsub eax, 1\ncdqe\nmov ecx, [rdx+rax*4]\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nadd ecx, esi\nmov eax, [rbp+var_C]\ncdqe\nmov [rdx+rax*4], ecx\njmp loc_14AB\nloc_1412:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_C]\ncdqe\nmov esi, [rdx+rax*4]\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nlea rdx, [rax-190h]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_C]\ncdqe\nmov ecx, [rdx+rax*4]\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nadd ecx, esi\nmov eax, [rbp+var_C]\ncdqe\nmov [rdx+rax*4], ecx\nloc_14AB:\nadd [rbp+var_C], 1\nloc_14AF:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_10]\njl loc_12FC\nadd [rbp+var_10], 1\nloc_14BF:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_1C]\njl loc_11CC\nmov eax, [rbp+var_1C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nlea rdx, [rax-190h]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_8], eax\nmov [rbp+var_4], 1\njmp short loc_157C\nloc_1506:\nmov eax, [rbp+var_1C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nlea rdx, [rax-190h]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\ncdqe\nmov eax, [rdx+rax*4]\ncmp [rbp+var_8], eax\njge short loc_1578\nmov eax, [rbp+var_1C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nlea rdx, [rax-190h]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\ncdqe\nmov eax, [rdx+rax*4]\nmov [rbp+var_8], eax\nloc_1578:\nadd [rbp+var_4], 1\nloc_157C:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1506\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2)\n{\n int v2; // ecx\n int i; // [rsp+Ch] [rbp-10h]\n int j; // [rsp+10h] [rbp-Ch]\n unsigned int v6; // [rsp+14h] [rbp-8h]\n int k; // [rsp+18h] [rbp-4h]\n\n if ( a2 > 1 )\n {\n a1[101] += *a1;\n a1[100] += *a1;\n }\n for ( i = 2; i < a2; ++i )\n {\n a1[100 * i] += a1[100 * i - 100];\n a1[100 * i + i] += a1[100 * i - 101 + i];\n for ( j = 1; j < i; ++j )\n {\n if ( a1[100 * i - 101 + j] < a1[100 * i - 100 + j] )\n v2 = a1[100 * i - 100 + j];\n else\n v2 = a1[100 * i - 101 + j];\n a1[100 * i + j] += v2;\n }\n }\n v6 = a1[100 * a2 - 100];\n for ( k = 1; k < a2; ++k )\n {\n if ( (signed int)v6 < a1[100 * a2 - 100 + k] )\n v6 = a1[100 * a2 - 100 + k];\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2) {\n int v2;\n int i;\n int j;\n unsigned int v6;\n int k;\n if (a2 > 1) {\n a1[101] += *a1;\n a1[100] += *a1;\n }\n for (i = 2; i < a2; ++i) {\n a1[100 * i] += a1[100 * i - 100];\n a1[100 * i + i] += a1[100 * i - 101 + i];\n for (j = 1; j < i; ++j) {\n if (a1[100 * i - 101 + j] < a1[100 * i - 100 + j])\n v2 = a1[100 * i - 100 + j];\n else\n v2 = a1[100 * i - 101 + j];\n a1[100 * i + j] += v2;\n }\n }\n v6 = a1[100 * a2 - 100];\n for (k = 1; k < a2; ++k) {\n if ((signed int)v6 < a1[100 * a2 - 100 + k]) v6 = a1[100 * a2 - 100 + k];\n }\n return v6;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n int v2;\n int i;\n int j;\n unsigned int v6;\n int k;\n if (a2 > 1) {\n a1[101] += *a1;\n a1[100] += *a1;\n }\n for (i = 2; i < a2; ++i) {\n a1[100 * i] += a1[100 * i - 100];\n a1[100 * i + i] += a1[100 * i - 101 + i];\n for (j = 1; j < i; ++j) {\n if (a1[100 * i - 101 + j] < a1[100 * i - 100 + j])\n v2 = a1[100 * i - 100 + j];\n else\n v2 = a1[100 * i - 101 + j];\n a1[100 * i + j] += v2;\n }\n }\n v6 = a1[100 * a2 - 100];\n for (k = 1; k < a2; ++k) {\n if ((signed int)v6 < a1[100 * a2 - 100 + k]) v6 = a1[100 * a2 - 100 + k];\n }\n return v6;\n}" + }, + { + "index": 231, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int tri[][100], int n) {\n if (n > 1) {\n tri[1][1] = tri[1][1] + tri[0][0];\n tri[1][0] = tri[1][0] + tri[0][0];\n }\n for (int i = 2; i < n; i++) {\n tri[i][0] = tri[i][0] + tri[i - 1][0];\n tri[i][i] = tri[i][i] + tri[i - 1][i - 1];\n for (int j = 1; j < i; j++) {\n if (tri[i][j] + tri[i - 1][j - 1] >= tri[i][j] + tri[i - 1][j]) {\n tri[i][j] = tri[i][j] + tri[i - 1][j - 1];\n } else {\n tri[i][j] = tri[i][j] + tri[i - 1][j];\n }\n }\n }\n int max_value = tri[n - 1][0];\n for (int j = 1; j < n; j++) {\n if (tri[n - 1][j] > max_value) {\n max_value = tri[n - 1][j];\n }\n }\n return max_value;\n}", + "test": "int main() {\n\n int tri1[3][100] = {{1}, {2, 1}, {3, 3, 2}};\n\n assert(func0(tri1, 3) == 6);\n\n\n\n int tri2[3][100] = {{1}, {1, 2}, {4, 1, 12}};\n\n assert(func0(tri2, 3) == 15);\n\n\n\n int tri3[3][100] = {{2}, {3, 2}, {13, 23, 12}};\n\n assert(func0(tri3, 3) == 28);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nmov %rdi,%rbp\nmov %esi,%edi\ncmp $0x1,%esi\njle 1188 \nmov 0x0(%rbp),%eax\nadd %eax,0x194(%rbp)\nadd %eax,0x190(%rbp)\ncmp $0x2,%edi\njle 1214 \nlea 0x320(%rbp),%r11\nlea 0x328(%rbp),%rsi\nlea -0x3(%rdi),%ebx\nadd $0x3,%rbx\nmov $0x2,%r10d\njmp 11eb \nadd (%r8,%rax,4),%edx\nmov %edx,(%r8,%rax,4)\nadd $0x1,%rax\ncmp %r10,%rax\nje 11d4 \nmov -0x4(%r9,%rax,4),%ecx\nmov (%r9,%rax,4),%edx\ncmp %edx,%ecx\njl 11ae \nadd (%r8,%rax,4),%ecx\nmov %ecx,%edx\njmp 11b2 \nadd $0x1,%r10\nadd $0x190,%r11\nadd $0x194,%rsi\ncmp %rbx,%r10\nje 123c \nmov %r11,%r8\nlea -0x190(%r11),%r9\nmov -0x190(%r11),%eax\nadd %eax,(%r11)\nmov -0x194(%rsi),%eax\nadd %eax,(%rsi)\ncmp $0x1,%r10d\njle 11d4 \nmov $0x1,%eax\njmp 11bf \nmovslq %edi,%rax\nlea (%rax,%rax,4),%rax\nlea (%rax,%rax,4),%rax\nshl $0x4,%rax\nlea -0x190(%rbp,%rax,1),%rax\nmov (%rax),%edx\ncmp $0x2,%edi\njne 126a \nmov 0x4(%rax),%eax\ncmp %eax,%edx\ncmovl %eax,%edx\njmp 126a \nmovslq %edi,%rax\nlea (%rax,%rax,4),%rax\nlea (%rax,%rax,4),%rax\nshl $0x4,%rax\nlea -0x190(%rbp,%rax,1),%rsi\nmov (%rsi),%edx\nmov $0x1,%eax\nmov (%rsi,%rax,4),%ecx\ncmp %ecx,%edx\ncmovl %ecx,%edx\nadd $0x1,%rax\ncmp %eax,%edi\njg 125a \nmov %edx,%eax\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nmov r11, rdi\nmov ebx, esi\ncmp esi, 1\njle loc_120F\nmov eax, [rdi]\nadd [rdi+194h], eax\nadd [rdi+190h], eax\ncmp esi, 2\njle loc_1227\nlea r9, [rdi+320h]\nlea r10, [rdi+328h]\nmov ebp, esi\nmov r8d, 2\njmp short loc_11E4\nloc_11AC:\nadd edx, [rsi+rax*4]\nloc_11AF:\nmov [rsi+rax*4], edx\nadd rax, 1\ncmp rax, r8\njz short loc_11CD\nloc_11BB:\nmov ecx, [rdi+rax*4-4]\nmov edx, [rdi+rax*4]\ncmp ecx, edx\njl short loc_11AC\nadd ecx, [rsi+rax*4]\nmov edx, ecx\njmp short loc_11AF\nloc_11CD:\nadd r8, 1\nadd r9, 190h\nadd r10, 194h\ncmp r8, rbp\njz short loc_1227\nloc_11E4:\nmov rsi, r9\nlea rdi, [r9-190h]\nmov eax, [r9-190h]\nadd [r9], eax\nmov eax, [r10-194h]\nadd [r10], eax\ncmp r8d, 1\njle short loc_1261\nmov eax, 1\njmp short loc_11BB\nloc_120F:\nmovsxd rbx, esi\nlea rax, [rbx+rbx*4]\nlea rax, [rax+rax*4]\nshl rax, 4\nmov edx, [rdi+rax-190h]\njmp short loc_125C\nloc_1227:\nmovsxd rax, ebx\nlea rax, [rax+rax*4]\nlea rax, [rax+rax*4]\nshl rax, 4\nlea rcx, [r11+rax-190h]\nmov edx, [rcx]\nlea rax, [rcx+4]\nlea esi, [rbx-2]\nlea rsi, [rcx+rsi*4+8]\nloc_124C:\nmov ecx, [rax]\ncmp edx, ecx\ncmovl edx, ecx\nadd rax, 4\ncmp rax, rsi\njnz short loc_124C\nloc_125C:\nmov eax, edx\npop rbx\npop rbp\nretn\nloc_1261:\nadd r8, 1\nadd r9, 190h\nadd r10, 194h\njmp loc_11E4", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int v3; // eax\n _DWORD *v4; // r9\n _DWORD *v5; // r10\n __int64 i; // r8\n int v7; // edx\n __int64 v8; // rax\n int v9; // ecx\n int v10; // edx\n _DWORD *v11; // rdi\n unsigned int v12; // edx\n unsigned int *v13; // rcx\n unsigned int *v14; // rax\n\n if ( a2 <= 1 )\n {\n return (unsigned int)a1[100 * a2 - 100];\n }\n else\n {\n v3 = *a1;\n a1[101] += *a1;\n a1[100] += v3;\n if ( a2 > 2 )\n {\n v4 = a1 + 200;\n v5 = a1 + 202;\n for ( i = 2LL; i != a2; ++i )\n {\n while ( 1 )\n {\n v11 = v4 - 100;\n *v4 += *(v4 - 100);\n *v5 += *(v5 - 101);\n if ( (int)i > 1 )\n break;\n ++i;\n v4 += 100;\n v5 += 101;\n }\n v8 = 1LL;\n do\n {\n v9 = v11[v8 - 1];\n v10 = v11[v8];\n if ( v9 < v10 )\n v7 = v4[v8] + v10;\n else\n v7 = v4[v8] + v9;\n v4[v8++] = v7;\n }\n while ( v8 != i );\n v4 += 100;\n v5 += 101;\n }\n }\n v13 = (unsigned int *)&a1[100 * a2 - 100];\n v12 = *v13;\n v14 = v13 + 1;\n do\n {\n if ( (int)v12 < (int)*v14 )\n v12 = *v14;\n ++v14;\n }\n while ( v14 != &v13[a2 - 2 + 2] );\n }\n return v12;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\npush rbx\nmov r11, rdi\nmov ebx, esi\ncmp esi, 1\njle loc_120F\nmov eax, [rdi]\nadd [rdi+194h], eax\nadd [rdi+190h], eax\ncmp esi, 2\njle loc_1227\nlea r9, [rdi+320h]\nlea r10, [rdi+328h]\nmov ebp, esi\nmov r8d, 2\njmp short loc_11E4\nloc_11AC:\nadd edx, [rsi+rax*4]\nloc_11AF:\nmov [rsi+rax*4], edx\nadd rax, 1\ncmp rax, r8\njz short loc_11CD\nloc_11BB:\nmov ecx, [rdi+rax*4-4]\nmov edx, [rdi+rax*4]\ncmp ecx, edx\njl short loc_11AC\nadd ecx, [rsi+rax*4]\nmov edx, ecx\njmp short loc_11AF\nloc_11CD:\nadd r8, 1\nadd r9, 190h\nadd r10, 194h\ncmp r8, rbp\njz short loc_1227\nloc_11E4:\nmov rsi, r9\nlea rdi, [r9-190h]\nmov eax, [r9-190h]\nadd [r9], eax\nmov eax, [r10-194h]\nadd [r10], eax\ncmp r8d, 1\njle short loc_1261\nmov eax, 1\njmp short loc_11BB\nloc_120F:\nmovsxd rbx, esi\nlea rax, [rbx+rbx*4]\nlea rax, [rax+rax*4]\nshl rax, 4\nmov edx, [rdi+rax-190h]\njmp short loc_125C\nloc_1227:\nmovsxd rax, ebx\nlea rax, [rax+rax*4]\nlea rax, [rax+rax*4]\nshl rax, 4\nlea rcx, [r11+rax-190h]\nmov edx, [rcx]\nlea rax, [rcx+4]\nlea esi, [rbx-2]\nlea rsi, [rcx+rsi*4+8]\nloc_124C:\nmov ecx, [rax]\ncmp edx, ecx\ncmovl edx, ecx\nadd rax, 4\ncmp rax, rsi\njnz short loc_124C\nloc_125C:\nmov eax, edx\npop rbx\npop rbp\nretn\nloc_1261:\nadd r8, 1\nadd r9, 190h\nadd r10, 194h\njmp loc_11E4", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int *a1, int a2)\n{\n int v3; // eax\n _DWORD *v4; // r9\n _DWORD *v5; // r10\n __int64 i; // r8\n int v7; // edx\n __int64 v8; // rax\n int v9; // ecx\n int v10; // edx\n _DWORD *v11; // rdi\n unsigned int v12; // edx\n unsigned int *v13; // rcx\n unsigned int *v14; // rax\n\n if ( a2 <= 1 )\n {\n return (unsigned int)a1[100 * a2 - 100];\n }\n else\n {\n v3 = *a1;\n a1[101] += *a1;\n a1[100] += v3;\n if ( a2 > 2 )\n {\n v4 = a1 + 200;\n v5 = a1 + 202;\n for ( i = 2LL; i != a2; ++i )\n {\n while ( 1 )\n {\n v11 = v4 - 100;\n *v4 += *(v4 - 100);\n *v5 += *(v5 - 101);\n if ( (int)i > 1 )\n break;\n ++i;\n v4 += 100;\n v5 += 101;\n }\n v8 = 1LL;\n do\n {\n v9 = v11[v8 - 1];\n v10 = v11[v8];\n if ( v9 < v10 )\n v7 = v4[v8] + v10;\n else\n v7 = v4[v8] + v9;\n v4[v8++] = v7;\n }\n while ( v8 != i );\n v4 += 100;\n v5 += 101;\n }\n }\n v13 = (unsigned int *)&a1[100 * a2 - 100];\n v12 = *v13;\n v14 = v13 + 1;\n do\n {\n if ( (int)v12 < (int)*v14 )\n v12 = *v14;\n ++v14;\n }\n while ( v14 != &v13[a2 - 2 + 2] );\n }\n return v12;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int *a1, int a2) {\n int v3;\n uint32_t *v4;\n uint32_t *v5;\n long long i;\n int v7;\n long long v8;\n int v9;\n int v10;\n uint32_t *v11;\n unsigned int v12;\n unsigned int *v13;\n unsigned int *v14;\n if (a2 <= 1) {\n return (unsigned int)a1[100 * a2 - 100];\n } else {\n v3 = *a1;\n a1[101] += *a1;\n a1[100] += v3;\n if (a2 > 2) {\n v4 = a1 + 200;\n v5 = a1 + 202;\n for (i = 2LL; i != a2; ++i) {\n while (1) {\n v11 = v4 - 100;\n *v4 += *(v4 - 100);\n *v5 += *(v5 - 101);\n if ((int)i > 1) break;\n ++i;\n v4 += 100;\n v5 += 101;\n }\n v8 = 1LL;\n do {\n v9 = v11[v8 - 1];\n v10 = v11[v8];\n if (v9 < v10)\n v7 = v4[v8] + v10;\n else\n v7 = v4[v8] + v9;\n v4[v8++] = v7;\n } while (v8 != i);\n v4 += 100;\n v5 += 101;\n }\n }\n v13 = (unsigned int *)&a1[100 * a2 - 100];\n v12 = *v13;\n v14 = v13 + 1;\n do {\n if ((int)v12 < (int)*v14) v12 = *v14;\n ++v14;\n } while (v14 != &v13[a2 - 2 + 2]);\n }\n return v12;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int v3;\n uint32_t *v4;\n uint32_t *v5;\n long long i;\n int v7;\n long long v8;\n int v9;\n int v10;\n uint32_t *v11;\n unsigned int v12;\n unsigned int *v13;\n unsigned int *v14;\n if (a2 <= 1) {\n return (unsigned int)a1[100 * a2 - 100];\n } else {\n v3 = *a1;\n a1[101] += *a1;\n a1[100] += v3;\n if (a2 > 2) {\n v4 = a1 + 200;\n v5 = a1 + 202;\n for (i = 2LL; i != a2; ++i) {\n while (1) {\n v11 = v4 - 100;\n *v4 += *(v4 - 100);\n *v5 += *(v5 - 101);\n if ((int)i > 1) break;\n ++i;\n v4 += 100;\n v5 += 101;\n }\n v8 = 1LL;\n do {\n v9 = v11[v8 - 1];\n v10 = v11[v8];\n if (v9 < v10)\n v7 = v4[v8] + v10;\n else\n v7 = v4[v8] + v9;\n v4[v8++] = v7;\n } while (v8 != i);\n v4 += 100;\n v5 += 101;\n }\n }\n v13 = (unsigned int *)&a1[100 * a2 - 100];\n v12 = *v13;\n v14 = v13 + 1;\n do {\n if ((int)v12 < (int)*v14) v12 = *v14;\n ++v14;\n } while (v14 != &v13[a2 - 2 + 2]);\n }\n return v12;\n}" + }, + { + "index": 231, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int tri[][100], int n) {\n if (n > 1) {\n tri[1][1] = tri[1][1] + tri[0][0];\n tri[1][0] = tri[1][0] + tri[0][0];\n }\n for (int i = 2; i < n; i++) {\n tri[i][0] = tri[i][0] + tri[i - 1][0];\n tri[i][i] = tri[i][i] + tri[i - 1][i - 1];\n for (int j = 1; j < i; j++) {\n if (tri[i][j] + tri[i - 1][j - 1] >= tri[i][j] + tri[i - 1][j]) {\n tri[i][j] = tri[i][j] + tri[i - 1][j - 1];\n } else {\n tri[i][j] = tri[i][j] + tri[i - 1][j];\n }\n }\n }\n int max_value = tri[n - 1][0];\n for (int j = 1; j < n; j++) {\n if (tri[n - 1][j] > max_value) {\n max_value = tri[n - 1][j];\n }\n }\n return max_value;\n}", + "test": "int main() {\n\n int tri1[3][100] = {{1}, {2, 1}, {3, 3, 2}};\n\n assert(func0(tri1, 3) == 6);\n\n\n\n int tri2[3][100] = {{1}, {1, 2}, {4, 1, 12}};\n\n assert(func0(tri2, 3) == 15);\n\n\n\n int tri3[3][100] = {{2}, {3, 2}, {13, 23, 12}};\n\n assert(func0(tri3, 3) == 28);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmov %esi,%ebx\ncmp $0x1,%esi\njle 142b \nmov (%rdi),%eax\nadd %eax,0x194(%rdi)\nadd %eax,0x190(%rdi)\nmovslq %esi,%rax\nlea (%rax,%rax,4),%rax\nlea (%rax,%rax,4),%rax\nshl $0x4,%rax\nlea -0x190(%rdi,%rax,1),%rbp\ncmp $0x2,%esi\njle 1442 \nlea -0x3(%rbx),%r12d\nlea 0x320(%rdi),%r8\nmov $0x2,%r11d\nlea 0x328(%rdi),%rsi\nadd $0x3,%r12\nnopl (%rax)\nmov -0x190(%r8),%eax\nlea -0x190(%r8),%r9\nadd %eax,(%r8)\nmov -0x194(%rsi),%eax\nadd %eax,(%rsi)\nmov $0x1,%eax\nxchg %ax,%ax\nmov -0x4(%r9,%rax,4),%edi\nmov (%r9,%rax,4),%ecx\nmov (%r8,%rax,4),%edx\nlea (%rdi,%rdx,1),%r10d\nadd %ecx,%edx\ncmp %ecx,%edi\ncmovge %r10d,%edx\nmov %edx,(%r8,%rax,4)\nadd $0x1,%rax\ncmp %rax,%r11\njne 13c0 \nadd $0x1,%r11\nadd $0x190,%r8\nadd $0x194,%rsi\ncmp %r11,%r12\njne 13a0 \nmov 0x0(%rbp),%r8d\nmov $0x1,%eax\nnopw %cs:0x0(%rax,%rax,1)\nmov 0x0(%rbp,%rax,4),%edx\ncmp %edx,%r8d\ncmovl %edx,%r8d\nadd $0x1,%rax\ncmp %eax,%ebx\njg 1410 \npop %rbx\nmov %r8d,%eax\npop %rbp\npop %r12\nretq\nmovslq %esi,%rax\nlea (%rax,%rax,4),%rax\nlea (%rax,%rax,4),%rax\nshl $0x4,%rax\nlea -0x190(%rdi,%rax,1),%rbp\nmov 0x0(%rbp),%r8d\ncmp $0x2,%ebx\njne 1423 \nmov 0x4(%rbp),%eax\ncmp %eax,%r8d\ncmovl %eax,%r8d\njmp 1423 \nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmovsxd rax, esi\npush r12\npush rbp\npush rbx\nmov rbx, rax\nlea rax, [rax+rax*4]\nlea rax, [rax+rax*4]\nshl rax, 4\nlea rbp, [rdi+rax-190h]\ncmp ebx, 1\njle loc_1435\nmov eax, [rdi]\nlea r8, [rdi+320h]\nadd [rdi+194h], eax\nmov r12d, ebx\nadd [rdi+190h], eax\nlea r11, [rdi+328h]\nmov r9d, 2\ncmp ebx, 2\njz short loc_13E8\nnop dword ptr [rax]\nloc_1388:\nmov eax, [r8-190h]\nadd [r8], eax\nmov edx, 1\nlea r10, [r8-190h]\nmov eax, [r11-194h]\nadd [r11], eax\nmov ecx, [r8-190h]\nnop\nloc_13B0:\nmov eax, [r8+rdx*4]\nmov esi, ecx\nmov ecx, [r10+rdx*4]\nlea edi, [rcx+rax]\nadd eax, esi\ncmp esi, ecx\ncmovl eax, edi\nmov [r8+rdx*4], eax\nadd rdx, 1\ncmp r9, rdx\njnz short loc_13B0\nadd r9, 1\nadd r8, 190h\nadd r11, 194h\ncmp r12, r9\njnz short loc_1388\nloc_13E8:\nlea ecx, [rbx-2]\nlea rdx, [rbp+4]\nmov eax, [rbp+0]\nlea rsi, [rbp+rcx*4+8]\nmov rcx, rsi\nsub rcx, rdx\nand ecx, 4\njz short loc_1418\nmov edx, [rdx]\ncmp eax, edx\ncmovl eax, edx\nlea rdx, [rbp+8]\ncmp rdx, rsi\njz short loc_1430\nnop word ptr [rax+rax+00h]\nloc_1418:\nmov ecx, [rdx]\ncmp eax, ecx\ncmovl eax, ecx\nmov ecx, [rdx+4]\ncmp eax, ecx\ncmovl eax, ecx\nadd rdx, 8\ncmp rdx, rsi\njnz short loc_1418\nloc_1430:\npop rbx\npop rbp\npop r12\nretn\nloc_1435:\nmov eax, [rbp+0]\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n unsigned int *v3; // rbp\n int v4; // eax\n _DWORD *v5; // r8\n _DWORD *v6; // r11\n __int64 v7; // r9\n __int64 v8; // rdx\n int v9; // ecx\n int v10; // eax\n int v11; // esi\n int v12; // edi\n int v13; // eax\n int *v14; // rdx\n __int64 result; // rax\n __int64 v16; // rsi\n int v17; // edx\n int v18; // ecx\n\n v3 = (unsigned int *)&a1[100 * a2 - 100];\n if ( a2 <= 1 )\n return *v3;\n v4 = *a1;\n v5 = a1 + 200;\n a1[101] += *a1;\n a1[100] += v4;\n v6 = a1 + 202;\n v7 = 2LL;\n if ( a2 != 2 )\n {\n do\n {\n *v5 += *(v5 - 100);\n v8 = 1LL;\n *v6 += *(v6 - 101);\n v9 = *(v5 - 100);\n do\n {\n v10 = v5[v8];\n v11 = v9;\n v9 = v5[v8 - 100];\n v12 = v9 + v10;\n v13 = v11 + v10;\n if ( v11 < v9 )\n v13 = v12;\n v5[v8++] = v13;\n }\n while ( v7 != v8 );\n ++v7;\n v5 += 100;\n v6 += 101;\n }\n while ( a2 != v7 );\n }\n v14 = (int *)(v3 + 1);\n result = *v3;\n v16 = (__int64)&v3[a2 - 2 + 2];\n if ( ((4 * ((_BYTE)a2 - 2) + 4) & 4) == 0 )\n goto LABEL_21;\n v17 = *v14;\n if ( (int)result < v17 )\n result = (unsigned int)v17;\n v14 = (int *)(v3 + 2);\n if ( v3 + 2 != (unsigned int *)v16 )\n {\nLABEL_21:\n do\n {\n if ( (int)result < *v14 )\n result = (unsigned int)*v14;\n v18 = v14[1];\n if ( (int)result < v18 )\n result = (unsigned int)v18;\n v14 += 2;\n }\n while ( v14 != (int *)v16 );\n }\n return result;\n}", + "ida_strip_asm": "sub_1330:\nendbr64\nmovsxd rax, esi\npush r12\npush rbp\npush rbx\nmov rbx, rax\nlea rax, [rax+rax*4]\nlea rax, [rax+rax*4]\nshl rax, 4\nlea rbp, [rdi+rax-190h]\ncmp ebx, 1\njle loc_1435\nmov eax, [rdi]\nlea r8, [rdi+320h]\nadd [rdi+194h], eax\nmov r12d, ebx\nadd [rdi+190h], eax\nlea r11, [rdi+328h]\nmov r9d, 2\ncmp ebx, 2\njz short loc_13E8\nnop dword ptr [rax]\nloc_1388:\nmov eax, [r8-190h]\nadd [r8], eax\nmov edx, 1\nlea r10, [r8-190h]\nmov eax, [r11-194h]\nadd [r11], eax\nmov ecx, [r8-190h]\nnop\nloc_13B0:\nmov eax, [r8+rdx*4]\nmov esi, ecx\nmov ecx, [r10+rdx*4]\nlea edi, [rcx+rax]\nadd eax, esi\ncmp esi, ecx\ncmovl eax, edi\nmov [r8+rdx*4], eax\nadd rdx, 1\ncmp r9, rdx\njnz short loc_13B0\nadd r9, 1\nadd r8, 190h\nadd r11, 194h\ncmp r12, r9\njnz short loc_1388\nloc_13E8:\nlea ecx, [rbx-2]\nlea rdx, [rbp+4]\nmov eax, [rbp+0]\nlea rsi, [rbp+rcx*4+8]\nmov rcx, rsi\nsub rcx, rdx\nand ecx, 4\njz short loc_1418\nmov edx, [rdx]\ncmp eax, edx\ncmovl eax, edx\nlea rdx, [rbp+8]\ncmp rdx, rsi\njz short loc_1430\nnop word ptr [rax+rax+00h]\nloc_1418:\nmov ecx, [rdx]\ncmp eax, ecx\ncmovl eax, ecx\nmov ecx, [rdx+4]\ncmp eax, ecx\ncmovl eax, ecx\nadd rdx, 8\ncmp rdx, rsi\njnz short loc_1418\nloc_1430:\npop rbx\npop rbp\npop r12\nretn\nloc_1435:\nmov eax, [rbp+0]\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1330(int *a1, int a2)\n{\n unsigned int *v3; // rbp\n int v4; // eax\n _DWORD *v5; // r8\n _DWORD *v6; // r11\n __int64 v7; // r9\n __int64 v8; // rdx\n int v9; // ecx\n int v10; // eax\n int v11; // esi\n int v12; // edi\n int v13; // eax\n int *v14; // rdx\n __int64 result; // rax\n __int64 v16; // rsi\n int v17; // edx\n int v18; // ecx\n\n v3 = (unsigned int *)&a1[100 * a2 - 100];\n if ( a2 <= 1 )\n return *v3;\n v4 = *a1;\n v5 = a1 + 200;\n a1[101] += *a1;\n a1[100] += v4;\n v6 = a1 + 202;\n v7 = 2LL;\n if ( a2 != 2 )\n {\n do\n {\n *v5 += *(v5 - 100);\n v8 = 1LL;\n *v6 += *(v6 - 101);\n v9 = *(v5 - 100);\n do\n {\n v10 = v5[v8];\n v11 = v9;\n v9 = v5[v8 - 100];\n v12 = v9 + v10;\n v13 = v11 + v10;\n if ( v11 < v9 )\n v13 = v12;\n v5[v8++] = v13;\n }\n while ( v7 != v8 );\n ++v7;\n v5 += 100;\n v6 += 101;\n }\n while ( a2 != v7 );\n }\n v14 = (int *)(v3 + 1);\n result = *v3;\n v16 = (__int64)&v3[a2 - 2 + 2];\n if ( ((4 * ((_BYTE)a2 - 2) + 4) & 4) == 0 )\n goto LABEL_21;\n v17 = *v14;\n if ( (int)result < v17 )\n result = (unsigned int)v17;\n v14 = (int *)(v3 + 2);\n if ( v3 + 2 != (unsigned int *)v16 )\n {\nLABEL_21:\n do\n {\n if ( (int)result < *v14 )\n result = (unsigned int)*v14;\n v18 = v14[1];\n if ( (int)result < v18 )\n result = (unsigned int)v18;\n v14 += 2;\n }\n while ( v14 != (int *)v16 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1330(int *a1, int a2) {\n unsigned int *v3;\n int v4;\n uint32_t *v5;\n uint32_t *v6;\n long long v7;\n long long v8;\n int v9;\n int v10;\n int v11;\n int v12;\n int v13;\n int *v14;\n long long result;\n long long v16;\n int v17;\n int v18;\n v3 = (unsigned int *)&a1[100 * a2 - 100];\n if (a2 <= 1) return *v3;\n v4 = *a1;\n v5 = a1 + 200;\n a1[101] += *a1;\n a1[100] += v4;\n v6 = a1 + 202;\n v7 = 2LL;\n if (a2 != 2) {\n do {\n *v5 += *(v5 - 100);\n v8 = 1LL;\n *v6 += *(v6 - 101);\n v9 = *(v5 - 100);\n do {\n v10 = v5[v8];\n v11 = v9;\n v9 = v5[v8 - 100];\n v12 = v9 + v10;\n v13 = v11 + v10;\n if (v11 < v9) v13 = v12;\n v5[v8++] = v13;\n } while (v7 != v8);\n ++v7;\n v5 += 100;\n v6 += 101;\n } while (a2 != v7);\n }\n v14 = (int *)(v3 + 1);\n result = *v3;\n v16 = (long long)&v3[a2 - 2 + 2];\n if (((4 * ((uint8_t)a2 - 2) + 4) & 4) == 0) goto LABEL_21;\n v17 = *v14;\n if ((int)result < v17) result = (unsigned int)v17;\n v14 = (int *)(v3 + 2);\n if (v3 + 2 != (unsigned int *)v16) {\n LABEL_21:\n do {\n if ((int)result < *v14) result = (unsigned int)*v14;\n v18 = v14[1];\n if ((int)result < v18) result = (unsigned int)v18;\n v14 += 2;\n } while (v14 != (int *)v16);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n unsigned int *v3;\n int v4;\n uint32_t *v5;\n uint32_t *v6;\n long long v7;\n long long v8;\n int v9;\n int v10;\n int v11;\n int v12;\n int v13;\n int *v14;\n long long result;\n long long v16;\n int v17;\n int v18;\n v3 = (unsigned int *)&a1[100 * a2 - 100];\n if (a2 <= 1) return *v3;\n v4 = *a1;\n v5 = a1 + 200;\n a1[101] += *a1;\n a1[100] += v4;\n v6 = a1 + 202;\n v7 = 2LL;\n if (a2 != 2) {\n do {\n *v5 += *(v5 - 100);\n v8 = 1LL;\n *v6 += *(v6 - 101);\n v9 = *(v5 - 100);\n do {\n v10 = v5[v8];\n v11 = v9;\n v9 = v5[v8 - 100];\n v12 = v9 + v10;\n v13 = v11 + v10;\n if (v11 < v9) v13 = v12;\n v5[v8++] = v13;\n } while (v7 != v8);\n ++v7;\n v5 += 100;\n v6 += 101;\n } while (a2 != v7);\n }\n v14 = (int *)(v3 + 1);\n result = *v3;\n v16 = (long long)&v3[a2 - 2 + 2];\n if (((4 * ((uint8_t)a2 - 2) + 4) & 4) == 0) goto LABEL_21;\n v17 = *v14;\n if ((int)result < v17) result = (unsigned int)v17;\n v14 = (int *)(v3 + 2);\n if (v3 + 2 != (unsigned int *)v16) {\n LABEL_21:\n do {\n if ((int)result < *v14) result = (unsigned int)*v14;\n v18 = v14[1];\n if ((int)result < v18) result = (unsigned int)v18;\n v14 += 2;\n } while (v14 != (int *)v16);\n }\n return result;\n}" + }, + { + "index": 231, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int tri[][100], int n) {\n if (n > 1) {\n tri[1][1] = tri[1][1] + tri[0][0];\n tri[1][0] = tri[1][0] + tri[0][0];\n }\n for (int i = 2; i < n; i++) {\n tri[i][0] = tri[i][0] + tri[i - 1][0];\n tri[i][i] = tri[i][i] + tri[i - 1][i - 1];\n for (int j = 1; j < i; j++) {\n if (tri[i][j] + tri[i - 1][j - 1] >= tri[i][j] + tri[i - 1][j]) {\n tri[i][j] = tri[i][j] + tri[i - 1][j - 1];\n } else {\n tri[i][j] = tri[i][j] + tri[i - 1][j];\n }\n }\n }\n int max_value = tri[n - 1][0];\n for (int j = 1; j < n; j++) {\n if (tri[n - 1][j] > max_value) {\n max_value = tri[n - 1][j];\n }\n }\n return max_value;\n}", + "test": "int main() {\n\n int tri1[3][100] = {{1}, {2, 1}, {3, 3, 2}};\n\n assert(func0(tri1, 3) == 6);\n\n\n\n int tri2[3][100] = {{1}, {1, 2}, {4, 1, 12}};\n\n assert(func0(tri2, 3) == 15);\n\n\n\n int tri3[3][100] = {{2}, {3, 2}, {13, 23, 12}};\n\n assert(func0(tri3, 3) == 28);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\nmov %esi,%r13d\npush %r12\npush %rbp\nmov %rdi,%rbp\npush %rbx\ncmp $0x1,%esi\njle 15db \nmov (%rdi),%eax\nadd %eax,0x194(%rdi)\nadd %eax,0x190(%rdi)\nmovslq %esi,%rax\nlea (%rax,%rax,4),%rax\nlea (%rax,%rax,4),%rax\nshl $0x4,%rax\nmov %rax,-0x10(%rsp)\nlea -0x190(%rdi,%rax,1),%r14\ncmp $0x2,%esi\njle 15f2 \nlea 0x320(%rdi),%rcx\nlea -0x1(%rsi),%r12d\nmov $0x1,%r8d\nlea 0x328(%rdi),%r10\nmov $0xc8,%edi\nnopl (%rax)\nmov -0x190(%rcx),%eax\nadd %eax,(%rcx)\nlea -0x190(%rcx),%rsi\nmov -0x194(%r10),%eax\nadd %eax,(%r10)\nlea -0x1(%r8),%eax\ncmp $0x2,%eax\njbe 15d0 \nmov %r8d,%r9d\nlea -0x18c(%rcx),%r11\nlea 0x4(%rcx),%rdx\nxor %eax,%eax\nshr $0x2,%r9d\nshl $0x4,%r9\nxchg %ax,%ax\nmovdqu (%r11,%rax,1),%xmm0\nmovdqu (%rsi,%rax,1),%xmm6\nmovdqu (%rdx,%rax,1),%xmm4\nmovdqu (%rsi,%rax,1),%xmm2\nmovdqu (%r11,%rax,1),%xmm1\npcmpgtd %xmm6,%xmm0\npaddd %xmm4,%xmm2\npaddd %xmm4,%xmm1\npand %xmm0,%xmm1\npandn %xmm2,%xmm0\npor %xmm1,%xmm0\nmovups %xmm0,(%rdx,%rax,1)\nadd $0x10,%rax\ncmp %r9,%rax\njne 13f0 \nmov %r8d,%eax\nlea 0x1(%r8),%r9d\nand $0xfffffffc,%eax\nlea 0x1(%rax),%r11d\ncmp %eax,%r8d\nje 14b4 \nmovslq %r11d,%rax\nlea (%rax,%rdi,1),%rdx\nshl $0x2,%rax\nadd %rax,%rsi\nadd %rcx,%rax\nmov -0x194(%rbp,%rdx,4),%r9d\nmov (%rsi),%ebx\nmov (%rax),%edx\nlea (%rdx,%rbx,1),%r15d\nadd %r9d,%edx\ncmp %ebx,%r9d\ncmovl %r15d,%edx\nlea 0x1(%r8),%r9d\nmov %edx,(%rax)\nlea 0x1(%r11),%edx\ncmp %r9d,%edx\njge 14b4 \nmov 0x4(%rsi),%r8d\nmov 0x4(%rax),%edx\nlea (%r8,%rdx,1),%r15d\nadd %ebx,%edx\ncmp %ebx,%r8d\ncmovg %r15d,%edx\nadd $0x2,%r11d\nmov %edx,0x4(%rax)\ncmp %r9d,%r11d\njge 14b4 \nmov 0x8(%rsi),%esi\nmov 0x8(%rax),%edx\nlea (%rsi,%rdx,1),%r11d\nadd %r8d,%edx\ncmp %esi,%r8d\ncmovl %r11d,%edx\nmov %edx,0x8(%rax)\nadd $0x190,%rcx\nmov %r9d,%r8d\nadd $0x64,%rdi\nadd $0x194,%r10\ncmp %r12d,%r9d\njne 13b0 \ncmp $0x1,%r13d\nmov $0x1,%edx\nmov (%r14),%eax\ncmovle %edx,%r9d\ncmp $0x4,%r13d\njle 1610 \nmovd %eax,%xmm7\nmov %r9d,%edx\nmov -0x10(%rsp),%rax\nshr $0x2,%edx\npshufd $0x0,%xmm7,%xmm0\nlea -0x18c(%rbp,%rax,1),%rax\nshl $0x4,%rdx\nadd %rax,%rdx\nmovdqu (%rax),%xmm2\nadd $0x10,%rax\nmovdqa %xmm2,%xmm1\npcmpgtd %xmm0,%xmm1\npand %xmm1,%xmm2\npandn %xmm0,%xmm1\nmovdqa %xmm1,%xmm0\npor %xmm2,%xmm0\ncmp %rdx,%rax\njne 1510 \nmovdqa %xmm0,%xmm1\nmov %r9d,%edx\npsrldq $0x8,%xmm1\nand $0xfffffffc,%edx\nmovdqa %xmm1,%xmm2\nmovdqa %xmm1,%xmm3\nlea 0x1(%rdx),%ecx\npcmpgtd %xmm0,%xmm2\npand %xmm2,%xmm3\npandn %xmm0,%xmm2\nmovdqa %xmm2,%xmm1\npor %xmm3,%xmm1\nmovdqa %xmm1,%xmm2\npsrldq $0x4,%xmm2\nmovdqa %xmm2,%xmm0\npcmpgtd %xmm1,%xmm0\npand %xmm0,%xmm2\npandn %xmm1,%xmm0\npor %xmm2,%xmm0\nmovd %xmm0,%eax\ncmp %edx,%r9d\nje 15bd \nmovslq %ecx,%rcx\nmov (%r14,%rcx,4),%ecx\ncmp %ecx,%eax\ncmovl %ecx,%eax\nadd $0x2,%edx\ncmp %edx,%r13d\njle 15bd \nmovslq %edx,%rcx\nmov (%r14,%rcx,4),%ecx\ncmp %ecx,%eax\ncmovl %ecx,%eax\nadd $0x1,%edx\ncmp %edx,%r13d\njle 15bd \nmovslq %edx,%rdx\nmov (%r14,%rdx,4),%edx\ncmp %edx,%eax\ncmovl %edx,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax,%rax,1)\nmov $0x1,%r11d\njmpq 1443 \nmovslq %esi,%rax\nlea (%rax,%rax,4),%rax\nlea (%rax,%rax,4),%rax\nshl $0x4,%rax\nlea -0x190(%rdi,%rax,1),%r14\nmov (%r14),%eax\ncmp $0x2,%r13d\njne 15bd \nmov 0x4(%r14),%edx\ncmp %edx,%eax\ncmovl %edx,%eax\njmp 15bd \nnopw %cs:0x0(%rax,%rax,1)\ncmp %eax,0x4(%r14)\nmov $0x2,%edx\ncmovge 0x4(%r14),%eax\njmpq 159d \nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\nmovsxd rax, esi\npush r15\nmov rdx, rax\nlea rax, [rax+rax*4]\npush r14\nlea r11, [rax+rax*4]\npush r13\nshl r11, 4\npush r12\npush rbp\npush rbx\nlea rbx, [rdi+r11-190h]\ncmp edx, 1\njle loc_15D5\nmov eax, [rdi]\nadd [rdi+194h], eax\nadd [rdi+190h], eax\ncmp edx, 2\njz loc_15F9\nlea r10d, [rdx-1]\nlea rcx, [rdi+320h]\nmov r9d, 0C8h\nmov r8d, 1\nlea rsi, [rdi+328h]\nnop word ptr [rax+rax+00000000h]\nloc_13A0:\nmov r13d, r8d\nmov eax, [rcx-190h]\nadd [rcx], eax\nlea rbp, [rcx-190h]\nmov eax, [rsi-194h]\nadd [rsi], eax\nlea eax, [r13-1]\nadd r8d, 1\ncmp eax, 2\njbe loc_15C8\nmov r14d, r13d\nlea r15, [rcx-18Ch]\nlea r12, [rcx+4]\nxor eax, eax\nshr r14d, 2\nshl r14, 4\nnop dword ptr [rax+rax+00h]\nloc_13E8:\nmovdqu xmm0, xmmword ptr [r15+rax]\nmovdqu xmm6, xmmword ptr [rbp+rax+0]\nmovdqu xmm4, xmmword ptr [r12+rax]\nmovdqu xmm2, xmmword ptr [rbp+rax+0]\nmovdqu xmm1, xmmword ptr [r15+rax]\npcmpgtd xmm0, xmm6\npaddd xmm2, xmm4\npaddd xmm1, xmm4\npand xmm1, xmm0\npandn xmm0, xmm2\npor xmm0, xmm1\nmovups xmmword ptr [r12+rax], xmm0\nadd rax, 10h\ncmp rax, r14\njnz short loc_13E8\nmov r12d, r13d\nand r12d, 0FFFFFFFCh\nand r13d, 3\nlea eax, [r12+1]\njz loc_14CC\nloc_1442:\nmov r14d, r8d\nsub r14d, r12d\nlea r13d, [r14-1]\ncmp r14d, 2\njz short loc_14A5\nadd r12, r9\nshl r12, 2\nmovq xmm2, qword ptr [rdi+r12-190h]\nlea r14, [rdi+r12+4]\nmovq xmm0, qword ptr [rdi+r12-18Ch]\nmovq xmm1, qword ptr [r14]\nmovdqa xmm3, xmm2\npaddd xmm3, xmm1\npaddd xmm1, xmm0\npcmpgtd xmm0, xmm2\npand xmm1, xmm0\npandn xmm0, xmm3\npor xmm0, xmm1\nmovq qword ptr [r14], xmm0\ntest r13b, 1\njz short loc_14CC\nand r13d, 0FFFFFFFEh\nadd eax, r13d\nloc_14A5:\ncdqe\nshl rax, 2\nadd rbp, rax\nadd rax, rcx\nmov r12d, [rbp-4]\nmov r13d, [rbp+0]\nmov ebp, [rax]\nlea r14d, [r13+rbp+0]\nadd ebp, r12d\ncmp r12d, r13d\ncmovl ebp, r14d\nmov [rax], ebp\nloc_14CC:\nadd rcx, 190h\nadd r9, 64h ; 'd'\nadd rsi, 194h\ncmp r10d, r8d\njnz loc_13A0\nlea eax, [rdx-2]\nmovd xmm0, dword ptr [rbx]\ncmp eax, 2\njbe loc_15E2\nmov ecx, r10d\nlea rax, [rdi+r11-18Ch]\npshufd xmm0, xmm0, 0\nshr ecx, 2\nshl rcx, 4\nadd rcx, rax\nnop dword ptr [rax+00000000h]\nloc_1518:\nmovdqu xmm1, xmmword ptr [rax]\nadd rax, 10h\nmovdqa xmm2, xmm1\npcmpgtd xmm2, xmm0\npand xmm1, xmm2\npandn xmm2, xmm0\npor xmm2, xmm1\nmovdqa xmm0, xmm2\ncmp rcx, rax\njnz short loc_1518\nmovdqa xmm2, xmm0\nmov ecx, r10d\npsrldq xmm2, 8\nand ecx, 0FFFFFFFCh\nand r10d, 3\nmovdqa xmm1, xmm2\nlea esi, [rcx+1]\npcmpgtd xmm1, xmm0\npand xmm2, xmm1\npandn xmm1, xmm0\npor xmm1, xmm2\nmovdqa xmm2, xmm1\npsrldq xmm2, 4\nmovdqa xmm0, xmm2\npcmpgtd xmm0, xmm1\npand xmm2, xmm0\npandn xmm0, xmm1\npor xmm0, xmm2\nmovd eax, xmm0\njz short loc_15B9\nmovsxd rdi, esi\nlea rdi, [rbx+rdi*4]\nmov r8d, [rdi]\ncmp eax, r8d\ncmovl eax, r8d\nadd ecx, 2\ncmp ecx, edx\njge short loc_15B9\nloc_15A2:\nmov ecx, [rdi+4]\ncmp eax, ecx\ncmovl eax, ecx\nadd esi, 2\ncmp esi, edx\njge short loc_15B9\nmov edx, [rdi+8]\ncmp eax, edx\ncmovl eax, edx\nloc_15B9:\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15C8:\nxor r12d, r12d\nmov eax, 1\njmp loc_1442\nloc_15D5:\nmov eax, [rbx]\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15E2:\nmov eax, [rbx+4]\nlea rdi, [rbx+4]\nmovd ebx, xmm0\nmov esi, 1\ncmp ebx, eax\ncmovge eax, ebx\njmp short loc_15A2\nloc_15F9:\nmov eax, [rbx+4]\nmov edx, [rbx]\ncmp eax, edx\ncmovl eax, edx\njmp short loc_15B9", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n __int64 v3; // r11\n unsigned int *v4; // rbx\n int v5; // eax\n unsigned int v6; // r10d\n _DWORD *v7; // rcx\n __int64 v8; // r9\n int v9; // r8d\n _DWORD *v10; // rsi\n unsigned int v11; // r13d\n _DWORD *v12; // rbp\n unsigned int v13; // eax\n _DWORD *v14; // r15\n _DWORD *v15; // r12\n __int64 v16; // rax\n __m128i v17; // xmm4\n __m128i v18; // xmm0\n __int64 v19; // r12\n int v20; // eax\n int v21; // r13d\n __int64 v22; // r12\n __m128i v23; // xmm2\n __m128i *v24; // r14\n __m128i v25; // xmm0\n __m128i v26; // xmm1\n __m128i v27; // xmm3\n __m128i v28; // xmm1\n __m128i v29; // xmm0\n __int64 v30; // rax\n int *v31; // rbp\n int *v32; // rax\n int v33; // r12d\n int v34; // r13d\n int v35; // r14d\n int v36; // ebp\n __m128i v37; // xmm0\n const __m128i *v38; // rax\n __m128i v39; // xmm0\n const __m128i *v40; // rcx\n __m128i v41; // xmm1\n __m128i v42; // xmm2\n __m128i v43; // xmm2\n __m128i v44; // xmm2\n signed int v45; // esi\n __m128i v46; // xmm1\n __m128i v47; // xmm1\n __m128i v48; // xmm2\n __m128i v49; // xmm0\n __int64 result; // rax\n int *v51; // rdi\n int v52; // ecx\n int v53; // edx\n int v54; // ebx\n\n v3 = 100LL * a2;\n v4 = (unsigned int *)&a1[v3 - 100];\n if ( a2 <= 1 )\n return *v4;\n v5 = *a1;\n a1[101] += *a1;\n a1[100] += v5;\n if ( a2 == 2 )\n {\n result = v4[1];\n if ( (int)result < (int)*v4 )\n return *v4;\n return result;\n }\n v6 = a2 - 1;\n v7 = a1 + 200;\n v8 = 200LL;\n v9 = 1;\n v10 = a1 + 202;\n do\n {\n v11 = v9;\n *v7 += *(v7 - 100);\n v12 = v7 - 100;\n *v10 += *(v10 - 101);\n v13 = v9++ - 1;\n if ( v13 <= 2 )\n {\n v19 = 0LL;\n v20 = 1;\n }\n else\n {\n v14 = v7 - 99;\n v15 = v7 + 1;\n v16 = 0LL;\n do\n {\n v17 = _mm_loadu_si128((const __m128i *)&v15[v16]);\n v18 = _mm_cmpgt_epi32(_mm_loadu_si128((const __m128i *)&v14[v16]), _mm_loadu_si128((const __m128i *)&v12[v16]));\n *(__m128i *)&v15[v16] = _mm_or_si128(\n _mm_andnot_si128(v18, _mm_add_epi32(_mm_loadu_si128((const __m128i *)&v12[v16]), v17)),\n _mm_and_si128(_mm_add_epi32(_mm_loadu_si128((const __m128i *)&v14[v16]), v17), v18));\n v16 += 4LL;\n }\n while ( v16 != 4LL * (v11 >> 2) );\n v19 = v11 & 0xFFFFFFFC;\n v20 = v19 + 1;\n if ( (v11 & 3) == 0 )\n goto LABEL_14;\n }\n v21 = v9 - v19 - 1;\n if ( v9 - (_DWORD)v19 != 2 )\n {\n v22 = v8 + v19;\n v23 = _mm_loadl_epi64((const __m128i *)&a1[v22 - 100]);\n v24 = (__m128i *)&a1[v22 + 1];\n v25 = _mm_loadl_epi64((const __m128i *)&a1[v22 - 99]);\n v26 = _mm_loadl_epi64(v24);\n v27 = _mm_add_epi32(v23, v26);\n v28 = _mm_add_epi32(v26, v25);\n v29 = _mm_cmpgt_epi32(v25, v23);\n v24->m128i_i64[0] = _mm_or_si128(_mm_andnot_si128(v29, v27), _mm_and_si128(v28, v29)).m128i_u64[0];\n if ( (v21 & 1) == 0 )\n goto LABEL_14;\n v20 += v21 & 0xFFFFFFFE;\n }\n v30 = v20;\n v31 = &v12[v30];\n v32 = &v7[v30];\n v33 = *(v31 - 1);\n v34 = *v31;\n v35 = *v31 + *v32;\n v36 = v33 + *v32;\n if ( v33 < v34 )\n v36 = v35;\n *v32 = v36;\nLABEL_14:\n v7 += 100;\n v8 += 100LL;\n v10 += 101;\n }\n while ( v6 != v9 );\n v37 = _mm_cvtsi32_si128(*v4);\n if ( (unsigned int)(a2 - 2) <= 2 )\n {\n result = v4[1];\n v51 = (int *)(v4 + 1);\n v54 = _mm_cvtsi128_si32(v37);\n v45 = 1;\n if ( v54 >= (int)result )\n result = (unsigned int)v54;\nLABEL_22:\n v52 = v51[1];\n if ( (int)result < v52 )\n result = (unsigned int)v52;\n if ( v45 + 2 < a2 )\n {\n v53 = v51[2];\n if ( (int)result < v53 )\n return (unsigned int)v53;\n }\n }\n else\n {\n v38 = (const __m128i *)&a1[v3 - 99];\n v39 = _mm_shuffle_epi32(v37, 0);\n v40 = &v38[v6 >> 2];\n do\n {\n v41 = _mm_loadu_si128(v38++);\n v42 = _mm_cmpgt_epi32(v41, v39);\n v43 = _mm_or_si128(_mm_andnot_si128(v42, v39), _mm_and_si128(v41, v42));\n v39 = v43;\n }\n while ( v40 != v38 );\n v44 = _mm_srli_si128(v43, 8);\n v45 = (v6 & 0xFFFFFFFC) + 1;\n v46 = _mm_cmpgt_epi32(v44, v39);\n v47 = _mm_or_si128(_mm_andnot_si128(v46, v39), _mm_and_si128(v44, v46));\n v48 = _mm_srli_si128(v47, 4);\n v49 = _mm_cmpgt_epi32(v48, v47);\n result = (unsigned int)_mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v49, v47), _mm_and_si128(v48, v49)));\n if ( (v6 & 3) != 0 )\n {\n v51 = (int *)&v4[v45];\n if ( (int)result < *v51 )\n result = (unsigned int)*v51;\n if ( (int)((v6 & 0xFFFFFFFC) + 2) < a2 )\n goto LABEL_22;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1330:\nendbr64\nmovsxd rax, esi\npush r15\nmov rdx, rax\nlea rax, [rax+rax*4]\npush r14\nlea r11, [rax+rax*4]\npush r13\nshl r11, 4\npush r12\npush rbp\npush rbx\nlea rbx, [rdi+r11-190h]\ncmp edx, 1\njle loc_15D5\nmov eax, [rdi]\nadd [rdi+194h], eax\nadd [rdi+190h], eax\ncmp edx, 2\njz loc_15F9\nlea r10d, [rdx-1]\nlea rcx, [rdi+320h]\nmov r9d, 0C8h\nmov r8d, 1\nlea rsi, [rdi+328h]\nnop word ptr [rax+rax+00000000h]\nloc_13A0:\nmov r13d, r8d\nmov eax, [rcx-190h]\nadd [rcx], eax\nlea rbp, [rcx-190h]\nmov eax, [rsi-194h]\nadd [rsi], eax\nlea eax, [r13-1]\nadd r8d, 1\ncmp eax, 2\njbe loc_15C8\nmov r14d, r13d\nlea r15, [rcx-18Ch]\nlea r12, [rcx+4]\nxor eax, eax\nshr r14d, 2\nshl r14, 4\nnop dword ptr [rax+rax+00h]\nloc_13E8:\nmovdqu xmm0, xmmword ptr [r15+rax]\nmovdqu xmm6, xmmword ptr [rbp+rax+0]\nmovdqu xmm4, xmmword ptr [r12+rax]\nmovdqu xmm2, xmmword ptr [rbp+rax+0]\nmovdqu xmm1, xmmword ptr [r15+rax]\npcmpgtd xmm0, xmm6\npaddd xmm2, xmm4\npaddd xmm1, xmm4\npand xmm1, xmm0\npandn xmm0, xmm2\npor xmm0, xmm1\nmovups xmmword ptr [r12+rax], xmm0\nadd rax, 10h\ncmp rax, r14\njnz short loc_13E8\nmov r12d, r13d\nand r12d, 0FFFFFFFCh\nand r13d, 3\nlea eax, [r12+1]\njz loc_14CC\nloc_1442:\nmov r14d, r8d\nsub r14d, r12d\nlea r13d, [r14-1]\ncmp r14d, 2\njz short loc_14A5\nadd r12, r9\nshl r12, 2\nmovq xmm2, qword ptr [rdi+r12-190h]\nlea r14, [rdi+r12+4]\nmovq xmm0, qword ptr [rdi+r12-18Ch]\nmovq xmm1, qword ptr [r14]\nmovdqa xmm3, xmm2\npaddd xmm3, xmm1\npaddd xmm1, xmm0\npcmpgtd xmm0, xmm2\npand xmm1, xmm0\npandn xmm0, xmm3\npor xmm0, xmm1\nmovq qword ptr [r14], xmm0\ntest r13b, 1\njz short loc_14CC\nand r13d, 0FFFFFFFEh\nadd eax, r13d\nloc_14A5:\ncdqe\nshl rax, 2\nadd rbp, rax\nadd rax, rcx\nmov r12d, [rbp-4]\nmov r13d, [rbp+0]\nmov ebp, [rax]\nlea r14d, [r13+rbp+0]\nadd ebp, r12d\ncmp r12d, r13d\ncmovl ebp, r14d\nmov [rax], ebp\nloc_14CC:\nadd rcx, 190h\nadd r9, 64h ; 'd'\nadd rsi, 194h\ncmp r10d, r8d\njnz loc_13A0\nlea eax, [rdx-2]\nmovd xmm0, dword ptr [rbx]\ncmp eax, 2\njbe loc_15E2\nmov ecx, r10d\nlea rax, [rdi+r11-18Ch]\npshufd xmm0, xmm0, 0\nshr ecx, 2\nshl rcx, 4\nadd rcx, rax\nnop dword ptr [rax+00000000h]\nloc_1518:\nmovdqu xmm1, xmmword ptr [rax]\nadd rax, 10h\nmovdqa xmm2, xmm1\npcmpgtd xmm2, xmm0\npand xmm1, xmm2\npandn xmm2, xmm0\npor xmm2, xmm1\nmovdqa xmm0, xmm2\ncmp rcx, rax\njnz short loc_1518\nmovdqa xmm2, xmm0\nmov ecx, r10d\npsrldq xmm2, 8\nand ecx, 0FFFFFFFCh\nand r10d, 3\nmovdqa xmm1, xmm2\nlea esi, [rcx+1]\npcmpgtd xmm1, xmm0\npand xmm2, xmm1\npandn xmm1, xmm0\npor xmm1, xmm2\nmovdqa xmm2, xmm1\npsrldq xmm2, 4\nmovdqa xmm0, xmm2\npcmpgtd xmm0, xmm1\npand xmm2, xmm0\npandn xmm0, xmm1\npor xmm0, xmm2\nmovd eax, xmm0\njz short loc_15B9\nmovsxd rdi, esi\nlea rdi, [rbx+rdi*4]\nmov r8d, [rdi]\ncmp eax, r8d\ncmovl eax, r8d\nadd ecx, 2\ncmp ecx, edx\njge short loc_15B9\nloc_15A2:\nmov ecx, [rdi+4]\ncmp eax, ecx\ncmovl eax, ecx\nadd esi, 2\ncmp esi, edx\njge short loc_15B9\nmov edx, [rdi+8]\ncmp eax, edx\ncmovl eax, edx\nloc_15B9:\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15C8:\nxor r12d, r12d\nmov eax, 1\njmp loc_1442\nloc_15D5:\nmov eax, [rbx]\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15E2:\nmov eax, [rbx+4]\nlea rdi, [rbx+4]\nmovd ebx, xmm0\nmov esi, 1\ncmp ebx, eax\ncmovge eax, ebx\njmp short loc_15A2\nloc_15F9:\nmov eax, [rbx+4]\nmov edx, [rbx]\ncmp eax, edx\ncmovl eax, edx\njmp short loc_15B9", + "ida_strip_pseudo": "__int64 __fastcall sub_1330(int *a1, int a2)\n{\n __int64 v3; // r11\n unsigned int *v4; // rbx\n int v5; // eax\n unsigned int v6; // r10d\n _DWORD *v7; // rcx\n __int64 v8; // r9\n int v9; // r8d\n _DWORD *v10; // rsi\n unsigned int v11; // r13d\n _DWORD *v12; // rbp\n unsigned int v13; // eax\n _DWORD *v14; // r15\n _DWORD *v15; // r12\n __int64 v16; // rax\n __m128i v17; // xmm4\n __m128i v18; // xmm0\n __int64 v19; // r12\n int v20; // eax\n int v21; // r13d\n __int64 v22; // r12\n __m128i v23; // xmm2\n __m128i *v24; // r14\n __m128i v25; // xmm0\n __m128i v26; // xmm1\n __m128i v27; // xmm3\n __m128i v28; // xmm1\n __m128i v29; // xmm0\n __int64 v30; // rax\n int *v31; // rbp\n int *v32; // rax\n int v33; // r12d\n int v34; // r13d\n int v35; // r14d\n int v36; // ebp\n __m128i v37; // xmm0\n const __m128i *v38; // rax\n __m128i v39; // xmm0\n const __m128i *v40; // rcx\n __m128i v41; // xmm1\n __m128i v42; // xmm2\n __m128i v43; // xmm2\n __m128i v44; // xmm2\n signed int v45; // esi\n __m128i v46; // xmm1\n __m128i v47; // xmm1\n __m128i v48; // xmm2\n __m128i v49; // xmm0\n __int64 result; // rax\n int *v51; // rdi\n int v52; // ecx\n int v53; // edx\n int v54; // ebx\n\n v3 = 100LL * a2;\n v4 = (unsigned int *)&a1[v3 - 100];\n if ( a2 <= 1 )\n return *v4;\n v5 = *a1;\n a1[101] += *a1;\n a1[100] += v5;\n if ( a2 == 2 )\n {\n result = v4[1];\n if ( (int)result < (int)*v4 )\n return *v4;\n return result;\n }\n v6 = a2 - 1;\n v7 = a1 + 200;\n v8 = 200LL;\n v9 = 1;\n v10 = a1 + 202;\n do\n {\n v11 = v9;\n *v7 += *(v7 - 100);\n v12 = v7 - 100;\n *v10 += *(v10 - 101);\n v13 = v9++ - 1;\n if ( v13 <= 2 )\n {\n v19 = 0LL;\n v20 = 1;\n }\n else\n {\n v14 = v7 - 99;\n v15 = v7 + 1;\n v16 = 0LL;\n do\n {\n v17 = _mm_loadu_si128((const __m128i *)&v15[v16]);\n v18 = _mm_cmpgt_epi32(_mm_loadu_si128((const __m128i *)&v14[v16]), _mm_loadu_si128((const __m128i *)&v12[v16]));\n *(__m128i *)&v15[v16] = _mm_or_si128(\n _mm_andnot_si128(v18, _mm_add_epi32(_mm_loadu_si128((const __m128i *)&v12[v16]), v17)),\n _mm_and_si128(_mm_add_epi32(_mm_loadu_si128((const __m128i *)&v14[v16]), v17), v18));\n v16 += 4LL;\n }\n while ( v16 != 4LL * (v11 >> 2) );\n v19 = v11 & 0xFFFFFFFC;\n v20 = v19 + 1;\n if ( (v11 & 3) == 0 )\n goto LABEL_14;\n }\n v21 = v9 - v19 - 1;\n if ( v9 - (_DWORD)v19 != 2 )\n {\n v22 = v8 + v19;\n v23 = _mm_loadl_epi64((const __m128i *)&a1[v22 - 100]);\n v24 = (__m128i *)&a1[v22 + 1];\n v25 = _mm_loadl_epi64((const __m128i *)&a1[v22 - 99]);\n v26 = _mm_loadl_epi64(v24);\n v27 = _mm_add_epi32(v23, v26);\n v28 = _mm_add_epi32(v26, v25);\n v29 = _mm_cmpgt_epi32(v25, v23);\n v24->m128i_i64[0] = _mm_or_si128(_mm_andnot_si128(v29, v27), _mm_and_si128(v28, v29)).m128i_u64[0];\n if ( (v21 & 1) == 0 )\n goto LABEL_14;\n v20 += v21 & 0xFFFFFFFE;\n }\n v30 = v20;\n v31 = &v12[v30];\n v32 = &v7[v30];\n v33 = *(v31 - 1);\n v34 = *v31;\n v35 = *v31 + *v32;\n v36 = v33 + *v32;\n if ( v33 < v34 )\n v36 = v35;\n *v32 = v36;\nLABEL_14:\n v7 += 100;\n v8 += 100LL;\n v10 += 101;\n }\n while ( v6 != v9 );\n v37 = _mm_cvtsi32_si128(*v4);\n if ( (unsigned int)(a2 - 2) <= 2 )\n {\n result = v4[1];\n v51 = (int *)(v4 + 1);\n v54 = _mm_cvtsi128_si32(v37);\n v45 = 1;\n if ( v54 >= (int)result )\n result = (unsigned int)v54;\nLABEL_22:\n v52 = v51[1];\n if ( (int)result < v52 )\n result = (unsigned int)v52;\n if ( v45 + 2 < a2 )\n {\n v53 = v51[2];\n if ( (int)result < v53 )\n return (unsigned int)v53;\n }\n }\n else\n {\n v38 = (const __m128i *)&a1[v3 - 99];\n v39 = _mm_shuffle_epi32(v37, 0);\n v40 = &v38[v6 >> 2];\n do\n {\n v41 = _mm_loadu_si128(v38++);\n v42 = _mm_cmpgt_epi32(v41, v39);\n v43 = _mm_or_si128(_mm_andnot_si128(v42, v39), _mm_and_si128(v41, v42));\n v39 = v43;\n }\n while ( v40 != v38 );\n v44 = _mm_srli_si128(v43, 8);\n v45 = (v6 & 0xFFFFFFFC) + 1;\n v46 = _mm_cmpgt_epi32(v44, v39);\n v47 = _mm_or_si128(_mm_andnot_si128(v46, v39), _mm_and_si128(v44, v46));\n v48 = _mm_srli_si128(v47, 4);\n v49 = _mm_cmpgt_epi32(v48, v47);\n result = (unsigned int)_mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v49, v47), _mm_and_si128(v48, v49)));\n if ( (v6 & 3) != 0 )\n {\n v51 = (int *)&v4[v45];\n if ( (int)result < *v51 )\n result = (unsigned int)*v51;\n if ( (int)((v6 & 0xFFFFFFFC) + 2) < a2 )\n goto LABEL_22;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1330(int *a1, int a2) {\n long long v3;\n unsigned int *v4;\n int v5;\n unsigned int v6;\n uint32_t *v7;\n long long v8;\n int v9;\n uint32_t *v10;\n unsigned int v11;\n uint32_t *v12;\n unsigned int v13;\n uint32_t *v14;\n uint32_t *v15;\n long long v16;\n __m128i v17;\n __m128i v18;\n long long v19;\n int v20;\n int v21;\n long long v22;\n __m128i v23;\n __m128i *v24;\n __m128i v25;\n __m128i v26;\n __m128i v27;\n __m128i v28;\n __m128i v29;\n long long v30;\n int *v31;\n int *v32;\n int v33;\n int v34;\n int v35;\n int v36;\n __m128i v37;\n const __m128i *v38;\n __m128i v39;\n const __m128i *v40;\n __m128i v41;\n __m128i v42;\n __m128i v43;\n __m128i v44;\n signed int v45;\n __m128i v46;\n __m128i v47;\n __m128i v48;\n __m128i v49;\n long long result;\n int *v51;\n int v52;\n int v53;\n int v54;\n v3 = 100LL * a2;\n v4 = (unsigned int *)&a1[v3 - 100];\n if (a2 <= 1) return *v4;\n v5 = *a1;\n a1[101] += *a1;\n a1[100] += v5;\n if (a2 == 2) {\n result = v4[1];\n if ((int)result < (int)*v4) return *v4;\n return result;\n }\n v6 = a2 - 1;\n v7 = a1 + 200;\n v8 = 200LL;\n v9 = 1;\n v10 = a1 + 202;\n do {\n v11 = v9;\n *v7 += *(v7 - 100);\n v12 = v7 - 100;\n *v10 += *(v10 - 101);\n v13 = v9++ - 1;\n if (v13 <= 2) {\n v19 = 0LL;\n v20 = 1;\n } else {\n v14 = v7 - 99;\n v15 = v7 + 1;\n v16 = 0LL;\n do {\n v17 = _mm_loadu_si128((const __m128i *)&v15[v16]);\n v18 = _mm_cmpgt_epi32(_mm_loadu_si128((const __m128i *)&v14[v16]),\n _mm_loadu_si128((const __m128i *)&v12[v16]));\n *(__m128i *)&v15[v16] = _mm_or_si128(\n _mm_andnot_si128(\n v18, _mm_add_epi32(_mm_loadu_si128((const __m128i *)&v12[v16]),\n v17)),\n _mm_and_si128(\n _mm_add_epi32(_mm_loadu_si128((const __m128i *)&v14[v16]), v17),\n v18));\n v16 += 4LL;\n } while (v16 != 4LL * (v11 >> 2));\n v19 = v11 & 4294967292;\n v20 = v19 + 1;\n if ((v11 & 3) == 0) goto LABEL_14;\n }\n v21 = v9 - v19 - 1;\n if (v9 - (uint32_t)v19 != 2) {\n v22 = v8 + v19;\n v23 = _mm_loadl_epi64((const __m128i *)&a1[v22 - 100]);\n v24 = (__m128i *)&a1[v22 + 1];\n v25 = _mm_loadl_epi64((const __m128i *)&a1[v22 - 99]);\n v26 = _mm_loadl_epi64(v24);\n v27 = _mm_add_epi32(v23, v26);\n v28 = _mm_add_epi32(v26, v25);\n v29 = _mm_cmpgt_epi32(v25, v23);\n v24->m128i_i64[0] =\n _mm_or_si128(_mm_andnot_si128(v29, v27), _mm_and_si128(v28, v29))\n .m128i_u64[0];\n if ((v21 & 1) == 0) goto LABEL_14;\n v20 += v21 & 4294967294;\n }\n v30 = v20;\n v31 = &v12[v30];\n v32 = &v7[v30];\n v33 = *(v31 - 1);\n v34 = *v31;\n v35 = *v31 + *v32;\n v36 = v33 + *v32;\n if (v33 < v34) v36 = v35;\n *v32 = v36;\n LABEL_14:\n v7 += 100;\n v8 += 100LL;\n v10 += 101;\n } while (v6 != v9);\n v37 = _mm_cvtsi32_si128(*v4);\n if ((unsigned int)(a2 - 2) <= 2) {\n result = v4[1];\n v51 = (int *)(v4 + 1);\n v54 = _mm_cvtsi128_si32(v37);\n v45 = 1;\n if (v54 >= (int)result) result = (unsigned int)v54;\n LABEL_22:\n v52 = v51[1];\n if ((int)result < v52) result = (unsigned int)v52;\n if (v45 + 2 < a2) {\n v53 = v51[2];\n if ((int)result < v53) return (unsigned int)v53;\n }\n } else {\n v38 = (const __m128i *)&a1[v3 - 99];\n v39 = _mm_shuffle_epi32(v37, 0);\n v40 = &v38[v6 >> 2];\n do {\n v41 = _mm_loadu_si128(v38++);\n v42 = _mm_cmpgt_epi32(v41, v39);\n v43 = _mm_or_si128(_mm_andnot_si128(v42, v39), _mm_and_si128(v41, v42));\n v39 = v43;\n } while (v40 != v38);\n v44 = _mm_srli_si128(v43, 8);\n v45 = (v6 & 4294967292) + 1;\n v46 = _mm_cmpgt_epi32(v44, v39);\n v47 = _mm_or_si128(_mm_andnot_si128(v46, v39), _mm_and_si128(v44, v46));\n v48 = _mm_srli_si128(v47, 4);\n v49 = _mm_cmpgt_epi32(v48, v47);\n result = (unsigned int)_mm_cvtsi128_si32(\n _mm_or_si128(_mm_andnot_si128(v49, v47), _mm_and_si128(v48, v49)));\n if ((v6 & 3) != 0) {\n v51 = (int *)&v4[v45];\n if ((int)result < *v51) result = (unsigned int)*v51;\n if ((int)((v6 & 4294967292) + 2) < a2) goto LABEL_22;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n long long v3;\n unsigned int *v4;\n int v5;\n unsigned int v6;\n uint32_t *v7;\n long long v8;\n int v9;\n uint32_t *v10;\n unsigned int v11;\n uint32_t *v12;\n unsigned int v13;\n uint32_t *v14;\n uint32_t *v15;\n long long v16;\n __m128i v17;\n __m128i v18;\n long long v19;\n int v20;\n int v21;\n long long v22;\n __m128i v23;\n __m128i *v24;\n __m128i v25;\n __m128i v26;\n __m128i v27;\n __m128i v28;\n __m128i v29;\n long long v30;\n int *v31;\n int *v32;\n int v33;\n int v34;\n int v35;\n int v36;\n __m128i v37;\n const __m128i *v38;\n __m128i v39;\n const __m128i *v40;\n __m128i v41;\n __m128i v42;\n __m128i v43;\n __m128i v44;\n signed int v45;\n __m128i v46;\n __m128i v47;\n __m128i v48;\n __m128i v49;\n long long result;\n int *v51;\n int v52;\n int v53;\n int v54;\n v3 = 100LL * a2;\n v4 = (unsigned int *)&a1[v3 - 100];\n if (a2 <= 1) return *v4;\n v5 = *a1;\n a1[101] += *a1;\n a1[100] += v5;\n if (a2 == 2) {\n result = v4[1];\n if ((int)result < (int)*v4) return *v4;\n return result;\n }\n v6 = a2 - 1;\n v7 = a1 + 200;\n v8 = 200LL;\n v9 = 1;\n v10 = a1 + 202;\n do {\n v11 = v9;\n *v7 += *(v7 - 100);\n v12 = v7 - 100;\n *v10 += *(v10 - 101);\n v13 = v9++ - 1;\n if (v13 <= 2) {\n v19 = 0LL;\n v20 = 1;\n } else {\n v14 = v7 - 99;\n v15 = v7 + 1;\n v16 = 0LL;\n do {\n v17 = _mm_loadu_si128((const __m128i *)&v15[v16]);\n v18 = _mm_cmpgt_epi32(_mm_loadu_si128((const __m128i *)&v14[v16]),\n _mm_loadu_si128((const __m128i *)&v12[v16]));\n *(__m128i *)&v15[v16] = _mm_or_si128(\n _mm_andnot_si128(\n v18, _mm_add_epi32(_mm_loadu_si128((const __m128i *)&v12[v16]),\n v17)),\n _mm_and_si128(\n _mm_add_epi32(_mm_loadu_si128((const __m128i *)&v14[v16]), v17),\n v18));\n v16 += 4LL;\n } while (v16 != 4LL * (v11 >> 2));\n v19 = v11 & 4294967292;\n v20 = v19 + 1;\n if ((v11 & 3) == 0) goto LABEL_14;\n }\n v21 = v9 - v19 - 1;\n if (v9 - (uint32_t)v19 != 2) {\n v22 = v8 + v19;\n v23 = _mm_loadl_epi64((const __m128i *)&a1[v22 - 100]);\n v24 = (__m128i *)&a1[v22 + 1];\n v25 = _mm_loadl_epi64((const __m128i *)&a1[v22 - 99]);\n v26 = _mm_loadl_epi64(v24);\n v27 = _mm_add_epi32(v23, v26);\n v28 = _mm_add_epi32(v26, v25);\n v29 = _mm_cmpgt_epi32(v25, v23);\n v24->m128i_i64[0] =\n _mm_or_si128(_mm_andnot_si128(v29, v27), _mm_and_si128(v28, v29))\n .m128i_u64[0];\n if ((v21 & 1) == 0) goto LABEL_14;\n v20 += v21 & 4294967294;\n }\n v30 = v20;\n v31 = &v12[v30];\n v32 = &v7[v30];\n v33 = *(v31 - 1);\n v34 = *v31;\n v35 = *v31 + *v32;\n v36 = v33 + *v32;\n if (v33 < v34) v36 = v35;\n *v32 = v36;\n LABEL_14:\n v7 += 100;\n v8 += 100LL;\n v10 += 101;\n } while (v6 != v9);\n v37 = _mm_cvtsi32_si128(*v4);\n if ((unsigned int)(a2 - 2) <= 2) {\n result = v4[1];\n v51 = (int *)(v4 + 1);\n v54 = _mm_cvtsi128_si32(v37);\n v45 = 1;\n if (v54 >= (int)result) result = (unsigned int)v54;\n LABEL_22:\n v52 = v51[1];\n if ((int)result < v52) result = (unsigned int)v52;\n if (v45 + 2 < a2) {\n v53 = v51[2];\n if ((int)result < v53) return (unsigned int)v53;\n }\n } else {\n v38 = (const __m128i *)&a1[v3 - 99];\n v39 = _mm_shuffle_epi32(v37, 0);\n v40 = &v38[v6 >> 2];\n do {\n v41 = _mm_loadu_si128(v38++);\n v42 = _mm_cmpgt_epi32(v41, v39);\n v43 = _mm_or_si128(_mm_andnot_si128(v42, v39), _mm_and_si128(v41, v42));\n v39 = v43;\n } while (v40 != v38);\n v44 = _mm_srli_si128(v43, 8);\n v45 = (v6 & 4294967292) + 1;\n v46 = _mm_cmpgt_epi32(v44, v39);\n v47 = _mm_or_si128(_mm_andnot_si128(v46, v39), _mm_and_si128(v44, v46));\n v48 = _mm_srli_si128(v47, 4);\n v49 = _mm_cmpgt_epi32(v48, v47);\n result = (unsigned int)_mm_cvtsi128_si32(\n _mm_or_si128(_mm_andnot_si128(v49, v47), _mm_and_si128(v48, v49)));\n if ((v6 & 3) != 0) {\n v51 = (int *)&v4[v45];\n if ((int)result < *v51) result = (unsigned int)*v51;\n if ((int)((v6 & 4294967292) + 2) < a2) goto LABEL_22;\n }\n }\n return result;\n}" + }, + { + "index": 232, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int *list1, int size, int n, int *result) {\n int i, j, max_idx, temp;\n int *copy = (int *)malloc(size * sizeof(int));\n for (i = 0; i < size; i++) {\n copy[i] = list1[i];\n }\n for (i = 0; i < n; i++) {\n max_idx = i;\n for (j = i + 1; j < size; j++) {\n if (copy[j] > copy[max_idx]) {\n max_idx = j;\n }\n }\n temp = copy[max_idx];\n copy[max_idx] = copy[i];\n copy[i] = temp;\n result[i] = copy[i];\n }\n free(copy);\n}", + "test": "int main() {\n\n int list1[] = {10, 20, 50, 70, 90, 20, 50, 40, 60, 80, 100};\n\n int size = sizeof(list1) / sizeof(list1[0]);\n\n int result[5];\n\n\n\n func0(list1, size, 2, result);\n\n assert(result[0] == 100 && result[1] == 90);\n\n\n\n func0(list1, size, 5, result);\n\n assert(result[0] == 100 && result[1] == 90 && result[2] == 80 && result[3] == 70 && result[4] == 60);\n\n\n\n func0(list1, size, 3, result);\n\n assert(result[0] == 100 && result[1] == 90 && result[2] == 80);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x40,%rsp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmov %edx,-0x30(%rbp)\nmov %rcx,-0x38(%rbp)\nmov -0x2c(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0x18(%rbp)\njmp 1212 \nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov -0x18(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 11e1 \nmovl $0x0,-0x18(%rbp)\njmpq 1309 \nmov -0x18(%rbp),%eax\nmov %eax,-0x10(%rbp)\nmov -0x18(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x14(%rbp)\njmp 1271 \nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x8(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njle 126d \nmov -0x14(%rbp),%eax\nmov %eax,-0x10(%rbp)\naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 1237 \nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0xc(%rbp)\nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov -0x10(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov -0xc(%rbp),%eax\nmov %eax,(%rdx)\nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov -0x18(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x38(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%eax\ncmp -0x30(%rbp),%eax\njl 1226 \nmov -0x8(%rbp),%rax\nmov %rax,%rdi\ncallq 1080 \nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_30], edx\nmov [rbp+var_38], rcx\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov [rbp+var_18], 0\njmp short loc_1212\nloc_11E1:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_18]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+ptr]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_18], 1\nloc_1212:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_2C]\njl short loc_11E1\nmov [rbp+var_18], 0\njmp loc_1309\nloc_1226:\nmov eax, [rbp+var_18]\nmov [rbp+var_10], eax\nmov eax, [rbp+var_18]\nadd eax, 1\nmov [rbp+var_14], eax\njmp short loc_1271\nloc_1237:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_126D\nmov eax, [rbp+var_14]\nmov [rbp+var_10], eax\nloc_126D:\nadd [rbp+var_14], 1\nloc_1271:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl short loc_1237\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+ptr]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov eax, [rbp+var_C]\nmov [rdx], eax\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rbp+var_18]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_38]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_18], 1\nloc_1309:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_30]\njl loc_1226\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nnop\nleave\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2, int a3, __int64 a4)\n{\n int i; // [rsp+28h] [rbp-18h]\n int j; // [rsp+28h] [rbp-18h]\n int k; // [rsp+2Ch] [rbp-14h]\n int v9; // [rsp+30h] [rbp-10h]\n int v10; // [rsp+34h] [rbp-Ch]\n _DWORD *ptr; // [rsp+38h] [rbp-8h]\n\n ptr = malloc(4LL * a2);\n for ( i = 0; i < a2; ++i )\n ptr[i] = *(_DWORD *)(4LL * i + a1);\n for ( j = 0; j < a3; ++j )\n {\n v9 = j;\n for ( k = j + 1; k < a2; ++k )\n {\n if ( ptr[k] > ptr[v9] )\n v9 = k;\n }\n v10 = ptr[v9];\n ptr[v9] = ptr[j];\n ptr[j] = v10;\n *(_DWORD *)(4LL * j + a4) = ptr[j];\n }\n free(ptr);\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_30], edx\nmov [rbp+var_38], rcx\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov [rbp+var_18], 0\njmp short loc_1212\nloc_11E1:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_18]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+ptr]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_18], 1\nloc_1212:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_2C]\njl short loc_11E1\nmov [rbp+var_18], 0\njmp loc_1309\nloc_1226:\nmov eax, [rbp+var_18]\nmov [rbp+var_10], eax\nmov eax, [rbp+var_18]\nadd eax, 1\nmov [rbp+var_14], eax\njmp short loc_1271\nloc_1237:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_126D\nmov eax, [rbp+var_14]\nmov [rbp+var_10], eax\nloc_126D:\nadd [rbp+var_14], 1\nloc_1271:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl short loc_1237\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+ptr]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov eax, [rbp+var_C]\nmov [rdx], eax\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rbp+var_18]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_38]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_18], 1\nloc_1309:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_30]\njl loc_1226\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nnop\nleave\nretn", + "ida_strip_pseudo": "void __fastcall sub_11A9(__int64 a1, int a2, int a3, __int64 a4)\n{\n int i; // [rsp+28h] [rbp-18h]\n int j; // [rsp+28h] [rbp-18h]\n int k; // [rsp+2Ch] [rbp-14h]\n int v9; // [rsp+30h] [rbp-10h]\n int v10; // [rsp+34h] [rbp-Ch]\n _DWORD *ptr; // [rsp+38h] [rbp-8h]\n\n ptr = malloc(4LL * a2);\n for ( i = 0; i < a2; ++i )\n ptr[i] = *(_DWORD *)(4LL * i + a1);\n for ( j = 0; j < a3; ++j )\n {\n v9 = j;\n for ( k = j + 1; k < a2; ++k )\n {\n if ( ptr[k] > ptr[v9] )\n v9 = k;\n }\n v10 = ptr[v9];\n ptr[v9] = ptr[j];\n ptr[j] = v10;\n *(_DWORD *)(4LL * j + a4) = ptr[j];\n }\n free(ptr);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_11A9(long long a1, int a2, int a3, long long a4) {\n int i;\n int j;\n int k;\n int v9;\n int v10;\n uint32_t *ptr;\n ptr = malloc(4LL * a2);\n for (i = 0; i < a2; ++i) ptr[i] = *(uint32_t *)(4LL * i + a1);\n for (j = 0; j < a3; ++j) {\n v9 = j;\n for (k = j + 1; k < a2; ++k) {\n if (ptr[k] > ptr[v9]) v9 = k;\n }\n v10 = ptr[v9];\n ptr[v9] = ptr[j];\n ptr[j] = v10;\n *(uint32_t *)(4LL * j + a4) = ptr[j];\n }\n free(ptr);\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2, int a3, long long a4) {\n int i;\n int j;\n int k;\n int v9;\n int v10;\n uint32_t *ptr;\n ptr = malloc(4LL * a2);\n for (i = 0; i < a2; ++i) ptr[i] = *(uint32_t *)(4LL * i + a1);\n for (j = 0; j < a3; ++j) {\n v9 = j;\n for (k = j + 1; k < a2; ++k) {\n if (ptr[k] > ptr[v9]) v9 = k;\n }\n v10 = ptr[v9];\n ptr[v9] = ptr[j];\n ptr[j] = v10;\n *(uint32_t *)(4LL * j + a4) = ptr[j];\n }\n free(ptr);\n}" + }, + { + "index": 232, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int *list1, int size, int n, int *result) {\n int i, j, max_idx, temp;\n int *copy = (int *)malloc(size * sizeof(int));\n for (i = 0; i < size; i++) {\n copy[i] = list1[i];\n }\n for (i = 0; i < n; i++) {\n max_idx = i;\n for (j = i + 1; j < size; j++) {\n if (copy[j] > copy[max_idx]) {\n max_idx = j;\n }\n }\n temp = copy[max_idx];\n copy[max_idx] = copy[i];\n copy[i] = temp;\n result[i] = copy[i];\n }\n free(copy);\n}", + "test": "int main() {\n\n int list1[] = {10, 20, 50, 70, 90, 20, 50, 40, 60, 80, 100};\n\n int size = sizeof(list1) / sizeof(list1[0]);\n\n int result[5];\n\n\n\n func0(list1, size, 2, result);\n\n assert(result[0] == 100 && result[1] == 90);\n\n\n\n func0(list1, size, 5, result);\n\n assert(result[0] == 100 && result[1] == 90 && result[2] == 80 && result[3] == 70 && result[4] == 60);\n\n\n\n func0(list1, size, 3, result);\n\n assert(result[0] == 100 && result[1] == 90 && result[2] == 80);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%r12\nmov %esi,%ebx\nmov %edx,%r13d\nmov %rcx,%rbp\nmovslq %esi,%rdi\nshl $0x2,%rdi\ncallq 10b0 \nmov %rax,%rdi\ntest %ebx,%ebx\njle 11f0 \nlea -0x1(%rbx),%ecx\nmov $0x0,%eax\nmov (%r12,%rax,4),%edx\nmov %edx,(%rdi,%rax,4)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rcx,%rdx\njne 11dd \ntest %r13d,%r13d\njle 1244 \nlea -0x1(%r13),%r8d\nadd $0x2,%r8\nmov $0x1,%esi\njmp 1224 \nmovslq %ecx,%rcx\nlea (%rdi,%rcx,4),%rdx\nmov (%rdx),%eax\nmov -0x4(%rdi,%rsi,4),%ecx\nmov %ecx,(%rdx)\nmov %eax,-0x4(%rdi,%rsi,4)\nmov %eax,-0x4(%rbp,%rsi,4)\nadd $0x1,%rsi\ncmp %r8,%rsi\nje 1244 \nlea -0x1(%rsi),%ecx\ncmp %esi,%ebx\njle 1204 \nmov %rsi,%rdx\nmovslq %ecx,%rax\nmov (%rdi,%rax,4),%eax\ncmp %eax,(%rdi,%rdx,4)\ncmovg %edx,%ecx\nadd $0x1,%rdx\ncmp %edx,%ebx\njg 122e \njmp 1204 \ncallq 1080 \nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r14, rdi\nmov ebx, esi\nmov r12d, edx\nmov rbp, rcx\nmovsxd r13, esi\nshl r13, 2\nmov rdi, r13; size\ncall _malloc\nmov rdi, rax; ptr\ntest ebx, ebx\njle short loc_11EB\nmov eax, 0\nloc_11DB:\nmov edx, [r14+rax]\nmov [rdi+rax], edx\nadd rax, 4\ncmp r13, rax\njnz short loc_11DB\nloc_11EB:\ntest r12d, r12d\njle short loc_123B\nmovsxd r12, r12d\nmov esi, 1\njmp short loc_11FD\nloc_11FA:\nmov rsi, rax\nloc_11FD:\nlea edx, [rsi-1]\ncmp ebx, esi\njle short loc_121B\nmov rax, rsi\nloc_1207:\nmovsxd rcx, edx\nmov ecx, [rdi+rcx*4]\ncmp [rdi+rax*4], ecx\ncmovg edx, eax\nadd rax, 1\ncmp ebx, eax\njg short loc_1207\nloc_121B:\nmovsxd rdx, edx\nlea rdx, [rdi+rdx*4]\nmov eax, [rdx]\nmov ecx, [rdi+rsi*4-4]\nmov [rdx], ecx\nmov [rdi+rsi*4-4], eax\nmov [rbp+rsi*4-4], eax\nlea rax, [rsi+1]\ncmp rsi, r12\njnz short loc_11FA\nloc_123B:\ncall _free\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2, int a3, __int64 a4)\n{\n _DWORD *v8; // rdi\n __int64 i; // rax\n __int64 j; // rsi\n int v11; // edx\n __int64 v12; // rax\n int *v13; // rdx\n int v14; // eax\n\n v8 = malloc(4LL * a2);\n if ( a2 > 0 )\n {\n for ( i = 0LL; i != a2; ++i )\n v8[i] = *(_DWORD *)(a1 + i * 4);\n }\n if ( a3 > 0 )\n {\n for ( j = 1LL; ; ++j )\n {\n v11 = j - 1;\n if ( a2 > (int)j )\n {\n v12 = j;\n do\n {\n if ( v8[v12] > v8[v11] )\n v11 = v12;\n ++v12;\n }\n while ( a2 > (int)v12 );\n }\n v13 = &v8[v11];\n v14 = *v13;\n *v13 = v8[j - 1];\n v8[j - 1] = v14;\n *(_DWORD *)(a4 + 4 * j - 4) = v14;\n if ( j == a3 )\n break;\n }\n }\n free(v8);\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r14, rdi\nmov ebx, esi\nmov r12d, edx\nmov rbp, rcx\nmovsxd r13, esi\nshl r13, 2\nmov rdi, r13; size\ncall _malloc\nmov rdi, rax; ptr\ntest ebx, ebx\njle short loc_11EB\nmov eax, 0\nloc_11DB:\nmov edx, [r14+rax]\nmov [rdi+rax], edx\nadd rax, 4\ncmp r13, rax\njnz short loc_11DB\nloc_11EB:\ntest r12d, r12d\njle short loc_123B\nmovsxd r12, r12d\nmov esi, 1\njmp short loc_11FD\nloc_11FA:\nmov rsi, rax\nloc_11FD:\nlea edx, [rsi-1]\ncmp ebx, esi\njle short loc_121B\nmov rax, rsi\nloc_1207:\nmovsxd rcx, edx\nmov ecx, [rdi+rcx*4]\ncmp [rdi+rax*4], ecx\ncmovg edx, eax\nadd rax, 1\ncmp ebx, eax\njg short loc_1207\nloc_121B:\nmovsxd rdx, edx\nlea rdx, [rdi+rdx*4]\nmov eax, [rdx]\nmov ecx, [rdi+rsi*4-4]\nmov [rdx], ecx\nmov [rdi+rsi*4-4], eax\nmov [rbp+rsi*4-4], eax\nlea rax, [rsi+1]\ncmp rsi, r12\njnz short loc_11FA\nloc_123B:\ncall _free\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "void __fastcall sub_11A9(__int64 a1, int a2, int a3, __int64 a4)\n{\n _DWORD *v8; // rdi\n __int64 i; // rax\n __int64 j; // rsi\n int v11; // edx\n __int64 v12; // rax\n int *v13; // rdx\n int v14; // eax\n\n v8 = malloc(4LL * a2);\n if ( a2 > 0 )\n {\n for ( i = 0LL; i != a2; ++i )\n v8[i] = *(_DWORD *)(a1 + i * 4);\n }\n if ( a3 > 0 )\n {\n for ( j = 1LL; ; ++j )\n {\n v11 = j - 1;\n if ( a2 > (int)j )\n {\n v12 = j;\n do\n {\n if ( v8[v12] > v8[v11] )\n v11 = v12;\n ++v12;\n }\n while ( a2 > (int)v12 );\n }\n v13 = &v8[v11];\n v14 = *v13;\n *v13 = v8[j - 1];\n v8[j - 1] = v14;\n *(_DWORD *)(a4 + 4 * j - 4) = v14;\n if ( j == a3 )\n break;\n }\n }\n free(v8);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_11A9(long long a1, int a2, int a3, long long a4) {\n uint32_t *v8;\n long long i;\n long long j;\n int v11;\n long long v12;\n int *v13;\n int v14;\n v8 = malloc(4LL * a2);\n if (a2 > 0) {\n for (i = 0LL; i != a2; ++i) v8[i] = *(uint32_t *)(a1 + i * 4);\n }\n if (a3 > 0) {\n for (j = 1LL;; ++j) {\n v11 = j - 1;\n if (a2 > (int)j) {\n v12 = j;\n do {\n if (v8[v12] > v8[v11]) v11 = v12;\n ++v12;\n } while (a2 > (int)v12);\n }\n v13 = &v8[v11];\n v14 = *v13;\n *v13 = v8[j - 1];\n v8[j - 1] = v14;\n *(uint32_t *)(a4 + 4 * j - 4) = v14;\n if (j == a3) break;\n }\n }\n free(v8);\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2, int a3, long long a4) {\n uint32_t *v8;\n long long i;\n long long j;\n int v11;\n long long v12;\n int *v13;\n int v14;\n v8 = malloc(4LL * a2);\n if (a2 > 0) {\n for (i = 0LL; i != a2; ++i) v8[i] = *(uint32_t *)(a1 + i * 4);\n }\n if (a3 > 0) {\n for (j = 1LL;; ++j) {\n v11 = j - 1;\n if (a2 > (int)j) {\n v12 = j;\n do {\n if (v8[v12] > v8[v11]) v11 = v12;\n ++v12;\n } while (a2 > (int)v12);\n }\n v13 = &v8[v11];\n v14 = *v13;\n *v13 = v8[j - 1];\n v8[j - 1] = v14;\n *(uint32_t *)(a4 + 4 * j - 4) = v14;\n if (j == a3) break;\n }\n }\n free(v8);\n}" + }, + { + "index": 232, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int *list1, int size, int n, int *result) {\n int i, j, max_idx, temp;\n int *copy = (int *)malloc(size * sizeof(int));\n for (i = 0; i < size; i++) {\n copy[i] = list1[i];\n }\n for (i = 0; i < n; i++) {\n max_idx = i;\n for (j = i + 1; j < size; j++) {\n if (copy[j] > copy[max_idx]) {\n max_idx = j;\n }\n }\n temp = copy[max_idx];\n copy[max_idx] = copy[i];\n copy[i] = temp;\n result[i] = copy[i];\n }\n free(copy);\n}", + "test": "int main() {\n\n int list1[] = {10, 20, 50, 70, 90, 20, 50, 40, 60, 80, 100};\n\n int size = sizeof(list1) / sizeof(list1[0]);\n\n int result[5];\n\n\n\n func0(list1, size, 2, result);\n\n assert(result[0] == 100 && result[1] == 90);\n\n\n\n func0(list1, size, 5, result);\n\n assert(result[0] == 100 && result[1] == 90 && result[2] == 80 && result[3] == 70 && result[4] == 60);\n\n\n\n func0(list1, size, 3, result);\n\n assert(result[0] == 100 && result[1] == 90 && result[2] == 80);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\nmov %rdi,%r14\nmovslq %esi,%rdi\npush %r13\nmov %rcx,%r13\npush %r12\nmov %edx,%r12d\npush %rbp\npush %rbx\nmov %rdi,%rbx\nshl $0x2,%rdi\ncallq 10b0 \nlea -0x1(%rbx),%ecx\nmov %rax,%rbp\nxor %eax,%eax\ntest %ebx,%ebx\njle 1374 \nmov (%r14,%rax,4),%edx\nmov %edx,0x0(%rbp,%rax,4)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rdx,%rcx\njne 1360 \nmov %rbp,%rax\nmov %r13,%rdx\nxor %r11d,%r11d\ntest %r12d,%r12d\njle 13f4 \nnopw 0x0(%rax,%rax,1)\nmov %r11d,%esi\nadd $0x1,%r11d\nmov (%rax),%r13d\ncmp %r11d,%ebx\njle 1408 \nlea 0x4(%rax),%r14\nmov %r13d,%r9d\nmov %r11d,%edi\nmov %r14,%rcx\njmp 13c3 \nnopw %cs:0x0(%rax,%rax,1)\nmovslq %esi,%r8\nadd $0x1,%edi\nadd $0x4,%rcx\nlea 0x0(%rbp,%r8,4),%r10\ncmp %edi,%ebx\nje 13de \nmov (%rcx),%r8d\nmov %rcx,%r10\ncmp %r9d,%r8d\njle 13b0 \nmov %edi,%esi\nadd $0x1,%edi\nmov %r8d,%r9d\nadd $0x4,%rcx\ncmp %edi,%ebx\njne 13c3 \nmov %r13d,(%r10)\nadd $0x4,%rdx\nmov %r9d,(%rax)\nmov %r14,%rax\nmov %r9d,-0x4(%rdx)\ncmp %r11d,%r12d\njne 1388 \npop %rbx\nmov %rbp,%rdi\npop %rbp\npop %r12\npop %r13\npop %r14\njmpq 1080 \nnopl 0x0(%rax)\nmov %r13d,%r9d\nmov %rax,%r10\nlea 0x4(%rax),%r14\njmp 13de \nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\nmov r13, rdi\nmovsxd rdi, esi\npush r12\nmov r12, rcx\npush rbp\nmov ebp, edx\npush rbx\nmov rbx, rdi\nshl rdi, 2; size\ncall _malloc\nmov r10, rax\ntest ebx, ebx\njle short loc_136E\nmov edx, ebx\nmov rsi, r13; src\nmov rdi, rax; dest\nshl rdx, 2; n\ncall _memcpy\nmov r10, rax\nloc_136E:\nmov r11, r10\nxor r9d, r9d\ntest ebp, ebp\njle short loc_13E2\nnop dword ptr [rax+rax+00000000h]\nloc_1380:\nmov r8d, r9d\nadd r9d, 1\nmov r13d, [r11]\ncmp ebx, r9d\njle short loc_13F8\nlea r14, [r11+4]\nmov esi, r13d\nmov edx, r9d\nmov rax, r14\njmp short loc_13B2\nloc_13A0:\nmovsxd rcx, r8d\nadd edx, 1\nadd rax, 4\nlea rdi, [r10+rcx*4]\ncmp edx, ebx\njz short loc_13CB\nloc_13B2:\nmov ecx, [rax]\nmov rdi, rax\ncmp esi, ecx\njge short loc_13A0\nmov r8d, edx\nadd edx, 1\nmov esi, ecx\nadd rax, 4\ncmp edx, ebx\njnz short loc_13B2\nloc_13CB:\nmov [rdi], r13d\nadd r12, 4\nmov [r11], esi\nmov r11, r14\nmov [r12-4], esi\ncmp ebp, r9d\njnz short loc_1380\nloc_13E2:\npop rbx\nmov rdi, r10; ptr\npop rbp\npop r12\npop r13\npop r14\njmp _free\nloc_13F8:\nmov esi, r13d\nmov rdi, r11\nlea r14, [r11+4]\njmp short loc_13CB", + "ida_pseudo": "void __fastcall func0(void *src, int a2, int a3, __int64 a4)\n{\n int *v7; // rax\n int *v8; // r10\n int *v9; // r11\n int v10; // r9d\n int v11; // r8d\n int *v12; // r14\n int v13; // esi\n int v14; // edx\n int *v15; // rax\n int *v16; // rdi\n\n v7 = (int *)malloc(4LL * a2);\n v8 = v7;\n if ( a2 > 0 )\n v8 = (int *)memcpy(v7, src, 4LL * (unsigned int)a2);\n v9 = v8;\n v10 = 0;\n if ( a3 > 0 )\n {\n do\n {\n v11 = v10++;\n if ( a2 <= v10 )\n {\n v13 = *v9;\n v16 = v9;\n v12 = v9 + 1;\n }\n else\n {\n v12 = v9 + 1;\n v13 = *v9;\n v14 = v10;\n v15 = v9 + 1;\n do\n {\n while ( 1 )\n {\n v16 = v15;\n if ( v13 < *v15 )\n break;\n ++v14;\n ++v15;\n v16 = &v8[v11];\n if ( v14 == a2 )\n goto LABEL_9;\n }\n v11 = v14++;\n v13 = *v15++;\n }\n while ( v14 != a2 );\n }\nLABEL_9:\n *v16 = *v9;\n a4 += 4LL;\n *v9 = v13;\n v9 = v12;\n *(_DWORD *)(a4 - 4) = v13;\n }\n while ( a3 != v10 );\n }\n free(v8);\n}", + "ida_strip_asm": "sub_1330:\nendbr64\npush r14\npush r13\nmov r13, rdi\nmovsxd rdi, esi\npush r12\nmov r12, rcx\npush rbp\nmov ebp, edx\npush rbx\nmov rbx, rdi\nshl rdi, 2; size\ncall _malloc\nmov r10, rax\ntest ebx, ebx\njle short loc_136E\nmov edx, ebx\nmov rsi, r13; src\nmov rdi, rax; dest\nshl rdx, 2; n\ncall _memcpy\nmov r10, rax\nloc_136E:\nmov r11, r10\nxor r9d, r9d\ntest ebp, ebp\njle short loc_13E2\nnop dword ptr [rax+rax+00000000h]\nloc_1380:\nmov r8d, r9d\nadd r9d, 1\nmov r13d, [r11]\ncmp ebx, r9d\njle short loc_13F8\nlea r14, [r11+4]\nmov esi, r13d\nmov edx, r9d\nmov rax, r14\njmp short loc_13B2\nloc_13A0:\nmovsxd rcx, r8d\nadd edx, 1\nadd rax, 4\nlea rdi, [r10+rcx*4]\ncmp edx, ebx\njz short loc_13CB\nloc_13B2:\nmov ecx, [rax]\nmov rdi, rax\ncmp esi, ecx\njge short loc_13A0\nmov r8d, edx\nadd edx, 1\nmov esi, ecx\nadd rax, 4\ncmp edx, ebx\njnz short loc_13B2\nloc_13CB:\nmov [rdi], r13d\nadd r12, 4\nmov [r11], esi\nmov r11, r14\nmov [r12-4], esi\ncmp ebp, r9d\njnz short loc_1380\nloc_13E2:\npop rbx\nmov rdi, r10; ptr\npop rbp\npop r12\npop r13\npop r14\njmp _free\nloc_13F8:\nmov esi, r13d\nmov rdi, r11\nlea r14, [r11+4]\njmp short loc_13CB", + "ida_strip_pseudo": "void __fastcall sub_1330(void *src, int a2, int a3, __int64 a4)\n{\n int *v7; // rax\n int *v8; // r10\n int *v9; // r11\n int v10; // r9d\n int v11; // r8d\n int *v12; // r14\n int v13; // esi\n int v14; // edx\n int *v15; // rax\n int *v16; // rdi\n\n v7 = (int *)malloc(4LL * a2);\n v8 = v7;\n if ( a2 > 0 )\n v8 = (int *)memcpy(v7, src, 4LL * (unsigned int)a2);\n v9 = v8;\n v10 = 0;\n if ( a3 > 0 )\n {\n do\n {\n v11 = v10++;\n if ( a2 <= v10 )\n {\n v13 = *v9;\n v16 = v9;\n v12 = v9 + 1;\n }\n else\n {\n v12 = v9 + 1;\n v13 = *v9;\n v14 = v10;\n v15 = v9 + 1;\n do\n {\n while ( 1 )\n {\n v16 = v15;\n if ( v13 < *v15 )\n break;\n ++v14;\n ++v15;\n v16 = &v8[v11];\n if ( v14 == a2 )\n goto LABEL_9;\n }\n v11 = v14++;\n v13 = *v15++;\n }\n while ( v14 != a2 );\n }\nLABEL_9:\n *v16 = *v9;\n a4 += 4LL;\n *v9 = v13;\n v9 = v12;\n *(_DWORD *)(a4 - 4) = v13;\n }\n while ( a3 != v10 );\n }\n free(v8);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1330(void *src, int a2, int a3, long long a4) {\n int *v7;\n int *v8;\n int *v9;\n int v10;\n int v11;\n int *v12;\n int v13;\n int v14;\n int *v15;\n int *v16;\n v7 = (int *)malloc(4LL * a2);\n v8 = v7;\n if (a2 > 0) v8 = (int *)memcpy(v7, src, 4LL * (unsigned int)a2);\n v9 = v8;\n v10 = 0;\n if (a3 > 0) {\n do {\n v11 = v10++;\n if (a2 <= v10) {\n v13 = *v9;\n v16 = v9;\n v12 = v9 + 1;\n } else {\n v12 = v9 + 1;\n v13 = *v9;\n v14 = v10;\n v15 = v9 + 1;\n do {\n while (1) {\n v16 = v15;\n if (v13 < *v15) break;\n ++v14;\n ++v15;\n v16 = &v8[v11];\n if (v14 == a2) goto LABEL_9;\n }\n v11 = v14++;\n v13 = *v15++;\n } while (v14 != a2);\n }\n LABEL_9:\n *v16 = *v9;\n a4 += 4LL;\n *v9 = v13;\n v9 = v12;\n *(uint32_t *)(a4 - 4) = v13;\n } while (a3 != v10);\n }\n free(v8);\n}", + "ida_pseudo_norm": "void func0(void *src, int a2, int a3, long long a4) {\n int *v7;\n int *v8;\n int *v9;\n int v10;\n int v11;\n int *v12;\n int v13;\n int v14;\n int *v15;\n int *v16;\n v7 = (int *)malloc(4LL * a2);\n v8 = v7;\n if (a2 > 0) v8 = (int *)memcpy(v7, src, 4LL * (unsigned int)a2);\n v9 = v8;\n v10 = 0;\n if (a3 > 0) {\n do {\n v11 = v10++;\n if (a2 <= v10) {\n v13 = *v9;\n v16 = v9;\n v12 = v9 + 1;\n } else {\n v12 = v9 + 1;\n v13 = *v9;\n v14 = v10;\n v15 = v9 + 1;\n do {\n while (1) {\n v16 = v15;\n if (v13 < *v15) break;\n ++v14;\n ++v15;\n v16 = &v8[v11];\n if (v14 == a2) goto LABEL_9;\n }\n v11 = v14++;\n v13 = *v15++;\n } while (v14 != a2);\n }\n LABEL_9:\n *v16 = *v9;\n a4 += 4LL;\n *v9 = v13;\n v9 = v12;\n *(uint32_t *)(a4 - 4) = v13;\n } while (a3 != v10);\n }\n free(v8);\n}" + }, + { + "index": 232, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int *list1, int size, int n, int *result) {\n int i, j, max_idx, temp;\n int *copy = (int *)malloc(size * sizeof(int));\n for (i = 0; i < size; i++) {\n copy[i] = list1[i];\n }\n for (i = 0; i < n; i++) {\n max_idx = i;\n for (j = i + 1; j < size; j++) {\n if (copy[j] > copy[max_idx]) {\n max_idx = j;\n }\n }\n temp = copy[max_idx];\n copy[max_idx] = copy[i];\n copy[i] = temp;\n result[i] = copy[i];\n }\n free(copy);\n}", + "test": "int main() {\n\n int list1[] = {10, 20, 50, 70, 90, 20, 50, 40, 60, 80, 100};\n\n int size = sizeof(list1) / sizeof(list1[0]);\n\n int result[5];\n\n\n\n func0(list1, size, 2, result);\n\n assert(result[0] == 100 && result[1] == 90);\n\n\n\n func0(list1, size, 5, result);\n\n assert(result[0] == 100 && result[1] == 90 && result[2] == 80 && result[3] == 70 && result[4] == 60);\n\n\n\n func0(list1, size, 3, result);\n\n assert(result[0] == 100 && result[1] == 90 && result[2] == 80);\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\nmov %rdi,%r13\nmovslq %esi,%rdi\npush %r12\nmov %rcx,%r12\npush %rbp\nmov %edx,%ebp\npush %rbx\nmov %rdi,%rbx\nshl $0x2,%rdi\ncallq 10d0 \nmov %rax,%r10\ntest %ebx,%ebx\njle 1373 \nlea -0x1(%rbx),%eax\nmov %r10,%rdi\nmov %r13,%rsi\nlea 0x4(,%rax,4),%rdx\ncallq 10c0 \nmov %rax,%r10\nmov %r10,%r11\nxor %r9d,%r9d\ntest %ebp,%ebp\njle 13e2 \nnopl (%rax)\nmov %r9d,%r8d\nadd $0x1,%r9d\nmov (%r11),%r13d\ncmp %r9d,%ebx\njle 13f8 \nlea 0x4(%r11),%r14\nmov %r13d,%esi\nmov %r9d,%edx\nmov %r14,%rax\njmp 13b2 \nxchg %ax,%ax\nmovslq %r8d,%rcx\nadd $0x1,%edx\nadd $0x4,%rax\nlea (%r10,%rcx,4),%rdi\ncmp %edx,%ebx\nje 13cb \nmov (%rax),%ecx\nmov %rax,%rdi\ncmp %ecx,%esi\njge 13a0 \nmov %edx,%r8d\nadd $0x1,%edx\nmov %ecx,%esi\nadd $0x4,%rax\ncmp %edx,%ebx\njne 13b2 \nmov %r13d,(%rdi)\nadd $0x4,%r12\nmov %esi,(%r11)\nmov %r14,%r11\nmov %esi,-0x4(%r12)\ncmp %r9d,%ebp\njne 1380 \npop %rbx\nmov %r10,%rdi\npop %rbp\npop %r12\npop %r13\npop %r14\njmpq 1090 \nnopw 0x0(%rax,%rax,1)\nmov %r13d,%esi\nmov %r11,%rdi\nlea 0x4(%r11),%r14\njmp 13cb \nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\nmov r13, rdi\nmovsxd rdi, esi\npush r12\nmov r12, rcx\npush rbp\nmov ebp, edx\npush rbx\nmov rbx, rdi\nshl rdi, 2; size\ncall _malloc\nmov r10, rax\ntest ebx, ebx\njle short loc_136E\nmov edx, ebx\nmov rsi, r13; src\nmov rdi, rax; dest\nshl rdx, 2; n\ncall _memcpy\nmov r10, rax\nloc_136E:\nmov r11, r10\nxor r9d, r9d\ntest ebp, ebp\njle short loc_13E2\nnop dword ptr [rax+rax+00000000h]\nloc_1380:\nmov r8d, r9d\nadd r9d, 1\nmov r13d, [r11]\ncmp ebx, r9d\njle short loc_13F8\nlea r14, [r11+4]\nmov esi, r13d\nmov edx, r9d\nmov rax, r14\njmp short loc_13B2\nloc_13A0:\nmovsxd rcx, r8d\nadd edx, 1\nadd rax, 4\nlea rdi, [r10+rcx*4]\ncmp ebx, edx\njz short loc_13CB\nloc_13B2:\nmov ecx, [rax]\nmov rdi, rax\ncmp esi, ecx\njge short loc_13A0\nmov r8d, edx\nadd edx, 1\nmov esi, ecx\nadd rax, 4\ncmp ebx, edx\njnz short loc_13B2\nloc_13CB:\nmov [rdi], r13d\nadd r12, 4\nmov [r11], esi\nmov r11, r14\nmov [r12-4], esi\ncmp ebp, r9d\njnz short loc_1380\nloc_13E2:\npop rbx\nmov rdi, r10; ptr\npop rbp\npop r12\npop r13\npop r14\njmp _free\nloc_13F8:\nmov esi, r13d\nmov rdi, r11\nlea r14, [r11+4]\njmp short loc_13CB", + "ida_pseudo": "void __fastcall func0(void *src, int a2, int a3, __int64 a4)\n{\n int *v7; // rax\n int *v8; // r10\n int *v9; // r11\n int v10; // r9d\n int v11; // r8d\n int *v12; // r14\n int v13; // esi\n int v14; // edx\n int *v15; // rax\n int *v16; // rdi\n\n v7 = (int *)malloc(4LL * a2);\n v8 = v7;\n if ( a2 > 0 )\n v8 = (int *)memcpy(v7, src, 4LL * (unsigned int)a2);\n v9 = v8;\n v10 = 0;\n if ( a3 > 0 )\n {\n do\n {\n v11 = v10++;\n if ( a2 <= v10 )\n {\n v13 = *v9;\n v16 = v9;\n v12 = v9 + 1;\n }\n else\n {\n v12 = v9 + 1;\n v13 = *v9;\n v14 = v10;\n v15 = v9 + 1;\n do\n {\n while ( 1 )\n {\n v16 = v15;\n if ( v13 < *v15 )\n break;\n ++v14;\n ++v15;\n v16 = &v8[v11];\n if ( a2 == v14 )\n goto LABEL_9;\n }\n v11 = v14++;\n v13 = *v15++;\n }\n while ( a2 != v14 );\n }\nLABEL_9:\n *v16 = *v9;\n a4 += 4LL;\n *v9 = v13;\n v9 = v12;\n *(_DWORD *)(a4 - 4) = v13;\n }\n while ( a3 != v10 );\n }\n free(v8);\n}", + "ida_strip_asm": "sub_1330:\nendbr64\npush r14\npush r13\nmov r13, rdi\nmovsxd rdi, esi\npush r12\nmov r12, rcx\npush rbp\nmov ebp, edx\npush rbx\nmov rbx, rdi\nshl rdi, 2; size\ncall _malloc\nmov r10, rax\ntest ebx, ebx\njle short loc_136E\nmov edx, ebx\nmov rsi, r13; src\nmov rdi, rax; dest\nshl rdx, 2; n\ncall _memcpy\nmov r10, rax\nloc_136E:\nmov r11, r10\nxor r9d, r9d\ntest ebp, ebp\njle short loc_13E2\nnop dword ptr [rax+rax+00000000h]\nloc_1380:\nmov r8d, r9d\nadd r9d, 1\nmov r13d, [r11]\ncmp ebx, r9d\njle short loc_13F8\nlea r14, [r11+4]\nmov esi, r13d\nmov edx, r9d\nmov rax, r14\njmp short loc_13B2\nloc_13A0:\nmovsxd rcx, r8d\nadd edx, 1\nadd rax, 4\nlea rdi, [r10+rcx*4]\ncmp ebx, edx\njz short loc_13CB\nloc_13B2:\nmov ecx, [rax]\nmov rdi, rax\ncmp esi, ecx\njge short loc_13A0\nmov r8d, edx\nadd edx, 1\nmov esi, ecx\nadd rax, 4\ncmp ebx, edx\njnz short loc_13B2\nloc_13CB:\nmov [rdi], r13d\nadd r12, 4\nmov [r11], esi\nmov r11, r14\nmov [r12-4], esi\ncmp ebp, r9d\njnz short loc_1380\nloc_13E2:\npop rbx\nmov rdi, r10; ptr\npop rbp\npop r12\npop r13\npop r14\njmp _free\nloc_13F8:\nmov esi, r13d\nmov rdi, r11\nlea r14, [r11+4]\njmp short loc_13CB", + "ida_strip_pseudo": "void __fastcall sub_1330(void *src, int a2, int a3, __int64 a4)\n{\n int *v7; // rax\n int *v8; // r10\n int *v9; // r11\n int v10; // r9d\n int v11; // r8d\n int *v12; // r14\n int v13; // esi\n int v14; // edx\n int *v15; // rax\n int *v16; // rdi\n\n v7 = (int *)malloc(4LL * a2);\n v8 = v7;\n if ( a2 > 0 )\n v8 = (int *)memcpy(v7, src, 4LL * (unsigned int)a2);\n v9 = v8;\n v10 = 0;\n if ( a3 > 0 )\n {\n do\n {\n v11 = v10++;\n if ( a2 <= v10 )\n {\n v13 = *v9;\n v16 = v9;\n v12 = v9 + 1;\n }\n else\n {\n v12 = v9 + 1;\n v13 = *v9;\n v14 = v10;\n v15 = v9 + 1;\n do\n {\n while ( 1 )\n {\n v16 = v15;\n if ( v13 < *v15 )\n break;\n ++v14;\n ++v15;\n v16 = &v8[v11];\n if ( a2 == v14 )\n goto LABEL_9;\n }\n v11 = v14++;\n v13 = *v15++;\n }\n while ( a2 != v14 );\n }\nLABEL_9:\n *v16 = *v9;\n a4 += 4LL;\n *v9 = v13;\n v9 = v12;\n *(_DWORD *)(a4 - 4) = v13;\n }\n while ( a3 != v10 );\n }\n free(v8);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1330(void *src, int a2, int a3, long long a4) {\n int *v7;\n int *v8;\n int *v9;\n int v10;\n int v11;\n int *v12;\n int v13;\n int v14;\n int *v15;\n int *v16;\n v7 = (int *)malloc(4LL * a2);\n v8 = v7;\n if (a2 > 0) v8 = (int *)memcpy(v7, src, 4LL * (unsigned int)a2);\n v9 = v8;\n v10 = 0;\n if (a3 > 0) {\n do {\n v11 = v10++;\n if (a2 <= v10) {\n v13 = *v9;\n v16 = v9;\n v12 = v9 + 1;\n } else {\n v12 = v9 + 1;\n v13 = *v9;\n v14 = v10;\n v15 = v9 + 1;\n do {\n while (1) {\n v16 = v15;\n if (v13 < *v15) break;\n ++v14;\n ++v15;\n v16 = &v8[v11];\n if (a2 == v14) goto LABEL_9;\n }\n v11 = v14++;\n v13 = *v15++;\n } while (a2 != v14);\n }\n LABEL_9:\n *v16 = *v9;\n a4 += 4LL;\n *v9 = v13;\n v9 = v12;\n *(uint32_t *)(a4 - 4) = v13;\n } while (a3 != v10);\n }\n free(v8);\n}", + "ida_pseudo_norm": "void func0(void *src, int a2, int a3, long long a4) {\n int *v7;\n int *v8;\n int *v9;\n int v10;\n int v11;\n int *v12;\n int v13;\n int v14;\n int *v15;\n int *v16;\n v7 = (int *)malloc(4LL * a2);\n v8 = v7;\n if (a2 > 0) v8 = (int *)memcpy(v7, src, 4LL * (unsigned int)a2);\n v9 = v8;\n v10 = 0;\n if (a3 > 0) {\n do {\n v11 = v10++;\n if (a2 <= v10) {\n v13 = *v9;\n v16 = v9;\n v12 = v9 + 1;\n } else {\n v12 = v9 + 1;\n v13 = *v9;\n v14 = v10;\n v15 = v9 + 1;\n do {\n while (1) {\n v16 = v15;\n if (v13 < *v15) break;\n ++v14;\n ++v15;\n v16 = &v8[v11];\n if (a2 == v14) goto LABEL_9;\n }\n v11 = v14++;\n v13 = *v15++;\n } while (a2 != v14);\n }\n LABEL_9:\n *v16 = *v9;\n a4 += 4LL;\n *v9 = v13;\n v9 = v12;\n *(uint32_t *)(a4 - 4) = v13;\n } while (a3 != v10);\n }\n free(v8);\n}" + }, + { + "index": 233, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "double func0(double r, double h) {\n double lateralsurface = 2 * 3.1415 * r * h;\n return lateralsurface;\n}", + "test": "int main() {\n\n assert(func0(10, 5) == 314.15000000000003);\n\n assert(func0(4, 5) == 125.66000000000001);\n\n assert(func0(4, 10) == 251.32000000000002);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmovsd %xmm0,-0x18(%rbp)\nmovsd %xmm1,-0x20(%rbp)\nmovsd -0x18(%rbp),%xmm1\nmovsd 0xf58(%rip),%xmm0\nmulsd %xmm1,%xmm0\nmovsd -0x20(%rbp),%xmm1\nmulsd %xmm1,%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmovsd -0x8(%rbp),%xmm0\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmovsd [rbp+var_18], xmm0\nmovsd [rbp+var_20], xmm1\nmovsd xmm1, [rbp+var_18]\nmovsd xmm0, cs:qword_20A0\nmulsd xmm0, xmm1\nmovsd xmm1, [rbp+var_20]\nmulsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "double __fastcall func0(double a1, double a2)\n{\n return 6.283 * a1 * a2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmovsd [rbp+var_18], xmm0\nmovsd [rbp+var_20], xmm1\nmovsd xmm1, [rbp+var_18]\nmovsd xmm0, cs:qword_20A0\nmulsd xmm0, xmm1\nmovsd xmm1, [rbp+var_20]\nmulsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "double __fastcall sub_1149(double a1, double a2)\n{\n return 6.283 * a1 * a2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1149(double a1, double a2) { return 6.283 * a1 * a2; }", + "ida_pseudo_norm": "double func0(double a1, double a2) { return 6.283 * a1 * a2; }" + }, + { + "index": 234, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "double func0(double l) {\n double volume = l * l * l;\n return volume;\n}", + "test": "int main() {\n\n assert(func0(3) == 27);\n\n assert(func0(2) == 8);\n\n assert(func0(5) == 125);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmovsd %xmm0,-0x18(%rbp)\nmovsd -0x18(%rbp),%xmm0\nmulsd %xmm0,%xmm0\nmovsd -0x18(%rbp),%xmm1\nmulsd %xmm1,%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmovsd -0x8(%rbp),%xmm0\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmovsd [rbp+var_18], xmm0\nmovsd xmm0, [rbp+var_18]\nmulsd xmm0, xmm0\nmovsd xmm1, [rbp+var_18]\nmulsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "double __fastcall func0(double a1)\n{\n return a1 * a1 * a1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmovsd [rbp+var_18], xmm0\nmovsd xmm0, [rbp+var_18]\nmulsd xmm0, xmm0\nmovsd xmm1, [rbp+var_18]\nmulsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "double __fastcall sub_1149(double a1)\n{\n return a1 * a1 * a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1149(double a1) { return a1 * a1 * a1; }", + "ida_pseudo_norm": "double func0(double a1) { return a1 * a1 * a1; }" + }, + { + "index": 235, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int count = 0;\n int res = 0;\n int temp = n;\n while (temp > 0) {\n if (count % 2 == 1) {\n res |= (1 << count);\n }\n count++;\n temp >>= 1;\n }\n return (n | res);\n}", + "test": "int main() {\n\n assert(func0(10) == 10);\n\n assert(func0(20) == 30);\n\n assert(func0(30) == 30);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\nmov -0x14(%rbp),%eax\nmov %eax,-0x4(%rbp)\njmp 1195 \nmov -0xc(%rbp),%eax\ncltd\nshr $0x1f,%edx\nadd %edx,%eax\nand $0x1,%eax\nsub %edx,%eax\ncmp $0x1,%eax\njne 118e \nmov -0xc(%rbp),%eax\nmov $0x1,%edx\nmov %eax,%ecx\nshl %cl,%edx\nmov %edx,%eax\nor %eax,-0x8(%rbp)\naddl $0x1,-0xc(%rbp)\nsarl -0x4(%rbp)\ncmpl $0x0,-0x4(%rbp)\njg 116a \nmov -0x14(%rbp),%eax\nor -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\nmov eax, [rbp+var_14]\nmov [rbp+var_4], eax\njmp short loc_119B\nloc_116A:\nmov edx, [rbp+var_C]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\ncmp eax, 1\njnz short loc_1194\nmov eax, [rbp+var_C]\nmov edx, 1\nmov ecx, eax\nshl edx, cl\nmov eax, edx\nor [rbp+var_8], eax\nloc_1194:\nadd [rbp+var_C], 1\nsar [rbp+var_4], 1\nloc_119B:\ncmp [rbp+var_4], 0\njg short loc_116A\nmov eax, [rbp+var_14]\nor eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v2; // [rsp+8h] [rbp-Ch]\n int v3; // [rsp+Ch] [rbp-8h]\n int i; // [rsp+10h] [rbp-4h]\n\n v2 = 0;\n v3 = 0;\n for ( i = a1; i > 0; i >>= 1 )\n {\n if ( v2 % 2 == 1 )\n v3 |= 1 << v2;\n ++v2;\n }\n return v3 | (unsigned int)a1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\nmov eax, [rbp+var_14]\nmov [rbp+var_4], eax\njmp short loc_119B\nloc_116A:\nmov edx, [rbp+var_C]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\ncmp eax, 1\njnz short loc_1194\nmov eax, [rbp+var_C]\nmov edx, 1\nmov ecx, eax\nshl edx, cl\nmov eax, edx\nor [rbp+var_8], eax\nloc_1194:\nadd [rbp+var_C], 1\nsar [rbp+var_4], 1\nloc_119B:\ncmp [rbp+var_4], 0\njg short loc_116A\nmov eax, [rbp+var_14]\nor eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v2; // [rsp+8h] [rbp-Ch]\n int v3; // [rsp+Ch] [rbp-8h]\n int i; // [rsp+10h] [rbp-4h]\n\n v2 = 0;\n v3 = 0;\n for ( i = a1; i > 0; i >>= 1 )\n {\n if ( v2 % 2 == 1 )\n v3 |= 1 << v2;\n ++v2;\n }\n return v3 | (unsigned int)a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v2;\n int v3;\n int i;\n v2 = 0;\n v3 = 0;\n for (i = a1; i > 0; i >>= 1) {\n if (v2 % 2 == 1) v3 |= 1 << v2;\n ++v2;\n }\n return v3 | (unsigned int)a1;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v2;\n int v3;\n int i;\n v2 = 0;\n v3 = 0;\n for (i = a1; i > 0; i >>= 1) {\n if (v2 % 2 == 1) v3 |= 1 << v2;\n ++v2;\n }\n return v3 | (unsigned int)a1;\n}" + }, + { + "index": 235, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int count = 0;\n int res = 0;\n int temp = n;\n while (temp > 0) {\n if (count % 2 == 1) {\n res |= (1 << count);\n }\n count++;\n temp >>= 1;\n }\n return (n | res);\n}", + "test": "int main() {\n\n assert(func0(10) == 10);\n\n assert(func0(20) == 30);\n\n assert(func0(30) == 30);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %edi,%r10d\nmov %edi,%esi\nmov $0x0,%ecx\nmov $0x0,%eax\nmov $0x1,%r9d\ntest %edi,%edi\njle 1193 \nadd $0x1,%ecx\nsar %esi\ntest %esi,%esi\njle 1193 \nmov %ecx,%r8d\nshr $0x1f,%r8d\nlea (%rcx,%r8,1),%edx\nand $0x1,%edx\nsub %r8d,%edx\nmov %eax,%r8d\nmov %r9d,%edi\nshl %cl,%edi\nor %edi,%eax\ncmp $0x1,%edx\ncmovne %r8d,%eax\njmp 1166 \nor %r10d,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov eax, edi\ntest edi, edi\njle short loc_1198\nmov r8d, edi\nmov esi, 0\nmov ecx, 0\nmov r11d, 1\nloc_1166:\nmov r9d, ecx\nshr r9d, 1Fh\nlea edx, [rcx+r9]\nand edx, 1\nsub edx, r9d\nmov r9d, esi\nmov r10d, r11d\nshl r10d, cl\nor esi, r10d\ncmp edx, 1\ncmovnz esi, r9d\nadd ecx, 1\nsar r8d, 1\ntest r8d, r8d\njg short loc_1166\nloc_1195:\nor eax, esi\nretn\nloc_1198:\nmov esi, 0\njmp short loc_1195", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // r8d\n int v2; // esi\n int v3; // ecx\n int v4; // r9d\n\n if ( a1 <= 0 )\n {\n v2 = 0;\n }\n else\n {\n v1 = a1;\n v2 = 0;\n v3 = 0;\n do\n {\n v4 = v2;\n v2 |= 1 << v3;\n if ( v3 % 2 != 1 )\n v2 = v4;\n ++v3;\n v1 >>= 1;\n }\n while ( v1 > 0 );\n }\n return v2 | (unsigned int)a1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmov eax, edi\ntest edi, edi\njle short loc_1198\nmov r8d, edi\nmov esi, 0\nmov ecx, 0\nmov r11d, 1\nloc_1166:\nmov r9d, ecx\nshr r9d, 1Fh\nlea edx, [rcx+r9]\nand edx, 1\nsub edx, r9d\nmov r9d, esi\nmov r10d, r11d\nshl r10d, cl\nor esi, r10d\ncmp edx, 1\ncmovnz esi, r9d\nadd ecx, 1\nsar r8d, 1\ntest r8d, r8d\njg short loc_1166\nloc_1195:\nor eax, esi\nretn\nloc_1198:\nmov esi, 0\njmp short loc_1195", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v1; // r8d\n int v2; // esi\n int v3; // ecx\n int v4; // r9d\n\n if ( a1 <= 0 )\n {\n v2 = 0;\n }\n else\n {\n v1 = a1;\n v2 = 0;\n v3 = 0;\n do\n {\n v4 = v2;\n v2 |= 1 << v3;\n if ( v3 % 2 != 1 )\n v2 = v4;\n ++v3;\n v1 >>= 1;\n }\n while ( v1 > 0 );\n }\n return v2 | (unsigned int)a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v1;\n int v2;\n int v3;\n int v4;\n if (a1 <= 0) {\n v2 = 0;\n } else {\n v1 = a1;\n v2 = 0;\n v3 = 0;\n do {\n v4 = v2;\n v2 |= 1 << v3;\n if (v3 % 2 != 1) v2 = v4;\n ++v3;\n v1 >>= 1;\n } while (v1 > 0);\n }\n return v2 | (unsigned int)a1;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v2;\n int v3;\n int v4;\n if (a1 <= 0) {\n v2 = 0;\n } else {\n v1 = a1;\n v2 = 0;\n v3 = 0;\n do {\n v4 = v2;\n v2 |= 1 << v3;\n if (v3 % 2 != 1) v2 = v4;\n ++v3;\n v1 >>= 1;\n } while (v1 > 0);\n }\n return v2 | (unsigned int)a1;\n}" + }, + { + "index": 235, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int count = 0;\n int res = 0;\n int temp = n;\n while (temp > 0) {\n if (count % 2 == 1) {\n res |= (1 << count);\n }\n count++;\n temp >>= 1;\n }\n return (n | res);\n}", + "test": "int main() {\n\n assert(func0(10) == 10);\n\n assert(func0(20) == 30);\n\n assert(func0(30) == 30);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov %edi,%edx\nxor %ecx,%ecx\nxor %eax,%eax\nmov $0x1,%r8d\ntest %edi,%edi\njle 1178 \nadd $0x1,%ecx\nsar %edx\nje 116e \ntest $0x1,%cl\nje 1154 \nmov %r8d,%esi\nshl %cl,%esi\nadd $0x1,%ecx\nor %esi,%eax\nsar %edx\njne 115b \nor %edi,%eax\nretq\nnopl 0x0(%rax)\nmov %edi,%eax\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njle short loc_1228\nmov edx, edi\nxor esi, esi\nxor ecx, ecx\nmov eax, 1\nnop dword ptr [rax+rax+00h]\nloc_1208:\ntest cl, 1\njz short loc_1216\nmov r8d, eax\nshl r8d, cl\nor esi, r8d\nloc_1216:\nadd ecx, 1\nsar edx, 1\njnz short loc_1208\nmov eax, edi\nor eax, esi\nretn\nloc_1228:\nmov eax, edi\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // edx\n int v2; // esi\n char v3; // cl\n\n if ( a1 <= 0 )\n return (unsigned int)a1;\n v1 = a1;\n v2 = 0;\n v3 = 0;\n do\n {\n if ( (v3 & 1) != 0 )\n v2 |= 1 << v3;\n ++v3;\n v1 >>= 1;\n }\n while ( v1 );\n return v2 | (unsigned int)a1;\n}", + "ida_strip_asm": "sub_11F0:\nendbr64\ntest edi, edi\njle short loc_1228\nmov edx, edi\nxor esi, esi\nxor ecx, ecx\nmov eax, 1\nnop dword ptr [rax+rax+00h]\nloc_1208:\ntest cl, 1\njz short loc_1216\nmov r8d, eax\nshl r8d, cl\nor esi, r8d\nloc_1216:\nadd ecx, 1\nsar edx, 1\njnz short loc_1208\nmov eax, edi\nor eax, esi\nretn\nloc_1228:\nmov eax, edi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11F0(int a1)\n{\n int v1; // edx\n int v2; // esi\n char v3; // cl\n\n if ( a1 <= 0 )\n return (unsigned int)a1;\n v1 = a1;\n v2 = 0;\n v3 = 0;\n do\n {\n if ( (v3 & 1) != 0 )\n v2 |= 1 << v3;\n ++v3;\n v1 >>= 1;\n }\n while ( v1 );\n return v2 | (unsigned int)a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11F0(int a1) {\n int v1;\n int v2;\n char v3;\n if (a1 <= 0) return (unsigned int)a1;\n v1 = a1;\n v2 = 0;\n v3 = 0;\n do {\n if ((v3 & 1) != 0) v2 |= 1 << v3;\n ++v3;\n v1 >>= 1;\n } while (v1);\n return v2 | (unsigned int)a1;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v2;\n char v3;\n if (a1 <= 0) return (unsigned int)a1;\n v1 = a1;\n v2 = 0;\n v3 = 0;\n do {\n if ((v3 & 1) != 0) v2 |= 1 << v3;\n ++v3;\n v1 >>= 1;\n } while (v1);\n return v2 | (unsigned int)a1;\n}" + }, + { + "index": 236, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int N, int K) {\n if (N < K) {\n return -1;\n } else {\n int Tri_up = ((N - K + 1) * (N - K + 2)) / 2;\n int Tri_down = ((N - 2 * K + 1) * (N - 2 * K + 2)) / 2;\n return Tri_up + Tri_down;\n }\n}", + "test": "int main() {\n\n assert(func0(4,2) == 7);\n\n assert(func0(4,3) == 3);\n\n assert(func0(1,3) == -1);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov -0x14(%rbp),%eax\ncmp -0x18(%rbp),%eax\njge 1166 \nmov $0xffffffff,%eax\njmp 11ba \nmov -0x14(%rbp),%eax\nsub -0x18(%rbp),%eax\nlea 0x1(%rax),%edx\nmov -0x14(%rbp),%eax\nsub -0x18(%rbp),%eax\nadd $0x2,%eax\nimul %edx,%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nmov %eax,-0x8(%rbp)\nmov -0x18(%rbp),%eax\nlea (%rax,%rax,1),%edx\nmov -0x14(%rbp),%eax\nsub %edx,%eax\nlea 0x1(%rax),%edx\nmov -0x18(%rbp),%eax\nlea (%rax,%rax,1),%ecx\nmov -0x14(%rbp),%eax\nsub %ecx,%eax\nadd $0x2,%eax\nimul %edx,%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nmov %eax,-0x4(%rbp)\nmov -0x8(%rbp),%edx\nmov -0x4(%rbp),%eax\nadd %edx,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_18]\njge short loc_1166\nmov eax, 0FFFFFFFFh\njmp short loc_11B8\nloc_1166:\nmov eax, [rbp+var_14]\nsub eax, [rbp+var_18]\nlea edx, [rax+1]\nmov eax, [rbp+var_14]\nsub eax, [rbp+var_18]\nadd eax, 2\nimul eax, edx\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_8], eax\nmov eax, [rbp+var_18]\nadd eax, eax\nmov edx, [rbp+var_14]\nsub edx, eax\nadd edx, 1\nmov eax, [rbp+var_18]\nadd eax, eax\nmov ecx, [rbp+var_14]\nsub ecx, eax\nlea eax, [rcx+2]\nimul eax, edx\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_4], eax\nmov edx, [rbp+var_8]\nmov eax, [rbp+var_4]\nadd eax, edx\nloc_11B8:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n if ( a1 >= a2 )\n return (unsigned int)((a1 - a2 + 1) * (a1 - a2 + 2) / 2 + (a1 - 2 * a2 + 1) * (a1 - 2 * a2 + 2) / 2);\n else\n return 0xFFFFFFFFLL;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_18]\njge short loc_1166\nmov eax, 0FFFFFFFFh\njmp short loc_11B8\nloc_1166:\nmov eax, [rbp+var_14]\nsub eax, [rbp+var_18]\nlea edx, [rax+1]\nmov eax, [rbp+var_14]\nsub eax, [rbp+var_18]\nadd eax, 2\nimul eax, edx\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_8], eax\nmov eax, [rbp+var_18]\nadd eax, eax\nmov edx, [rbp+var_14]\nsub edx, eax\nadd edx, 1\nmov eax, [rbp+var_18]\nadd eax, eax\nmov ecx, [rbp+var_14]\nsub ecx, eax\nlea eax, [rcx+2]\nimul eax, edx\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_4], eax\nmov edx, [rbp+var_8]\nmov eax, [rbp+var_4]\nadd eax, edx\nloc_11B8:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2)\n{\n if ( a1 >= a2 )\n return (unsigned int)((a1 - a2 + 1) * (a1 - a2 + 2) / 2 + (a1 - 2 * a2 + 1) * (a1 - 2 * a2 + 2) / 2);\n else\n return 0xFFFFFFFFLL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2) {\n if (a1 >= a2)\n return (unsigned int)((a1 - a2 + 1) * (a1 - a2 + 2) / 2 +\n (a1 - 2 * a2 + 1) * (a1 - 2 * a2 + 2) / 2);\n else\n return 4294967295LL;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n if (a1 >= a2)\n return (unsigned int)((a1 - a2 + 1) * (a1 - a2 + 2) / 2 +\n (a1 - 2 * a2 + 1) * (a1 - 2 * a2 + 2) / 2);\n else\n return 4294967295LL;\n}" + }, + { + "index": 237, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n} pair;\n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n int count;\n\n} pair_count;\n\n\n\n// Comparison function for qsort\n\nint compare_pairs(const void* a, const void* b) {\n\n pair* pa = (pair*)a;\n\n pair* pb = (pair*)b;\n\n if (pa->first != pb->first)\n\n return pa->first - pb->first;\n\n return pa->second - pb->second;\n\n}\n\n\n\n// Function to check occurrences\n\npair_count* check_occurences(pair* test_list, int size, int* out_size) {\n\n // Sort each pair\n\n for(int i = 0; i < size; i++) {\n\n if(test_list[i].first > test_list[i].second) {\n\n int temp = test_list[i].first;\n\n test_list[i].first = test_list[i].second;\n\n test_list[i].second = temp;\n\n }\n\n }\n\n // Sort the list of pairs\n\n qsort(test_list, size, sizeof(pair), compare_pairs);\n\n \n\n // Count occurrences\n\n pair_count* result = malloc(size * sizeof(pair_count));\n\n int unique = 0;\n\n for(int i = 0; i < size; i++) {\n\n if(unique == 0 || result[unique-1].first != test_list[i].first || result[unique-1].second != test_list[i].second) {\n\n result[unique].first = test_list[i].first;\n\n result[unique].second = test_list[i].second;\n\n result[unique].count = 1;\n\n unique++;\n\n }\n\n else {\n\n result[unique-1].count++;\n\n }\n\n }\n\n *out_size = unique;\n\n return result;\n\n}\n\n\n\n// Function to compare two pair_count arrays\n\n", + "func": "int func0(pair_count* a, int size_a, pair_count* b, int size_b) {\n if (size_a != size_b) return 0;\n for (int i = 0; i < size_a; i++) {\n if (a[i].first != b[i].first || a[i].second != b[i].second ||\n a[i].count != b[i].count)\n return 0;\n }\n return 1;\n}", + "test": "int main() {\n\n // First test case\n\n pair test1[] = { {3,1}, {1,3}, {2,5}, {5,2}, {6,3} };\n\n int size1 = sizeof(test1)/sizeof(pair);\n\n int out_size1;\n\n pair_count* res1 = check_occurences(test1, size1, &out_size1);\n\n pair_count expected1[] = { {1,3,2}, {2,5,2}, {3,6,1} };\n\n assert(func0(res1, out_size1, expected1, 3));\n\n free(res1);\n\n \n\n // Second test case\n\n pair test2[] = { {4,2}, {2,4}, {3,6}, {6,3}, {7,4} };\n\n int size2 = sizeof(test2)/sizeof(pair);\n\n int out_size2;\n\n pair_count* res2 = check_occurences(test2, size2, &out_size2);\n\n pair_count expected2[] = { {2,4,2}, {3,6,2}, {4,7,1} };\n\n assert(func0(res2, out_size2, expected2, 3));\n\n free(res2);\n\n \n\n // Third test case\n\n pair test3[] = { {13,2}, {11,23}, {12,25}, {25,12}, {16,23} };\n\n int size3 = sizeof(test3)/sizeof(pair);\n\n int out_size3;\n\n pair_count* res3 = check_occurences(test3, size3, &out_size3);\n\n pair_count expected3[] = { {2,13,1}, {11,23,1}, {12,25,2}, {16,23,1} };\n\n assert(func0(res3, out_size3, expected3, 4));\n\n free(res3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %ecx,-0x20(%rbp)\nmov -0x1c(%rbp),%eax\ncmp -0x20(%rbp),%eax\nje 14ba \nmov $0x0,%eax\njmpq 15b0 \nmovl $0x0,-0x4(%rbp)\njmpq 159f \nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%ecx\nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,%ecx\njne 1594 \nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov 0x4(%rax),%ecx\nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov 0x4(%rax),%eax\ncmp %eax,%ecx\njne 1594 \nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov 0x8(%rax),%ecx\nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov 0x8(%rax),%eax\ncmp %eax,%ecx\nje 159b \nmov $0x0,%eax\njmp 15b0 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 14c6 \nmov $0x1,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_20]\njz short loc_14BD\nmov eax, 0\njmp loc_15B3\nloc_14BD:\nmov [rbp+var_4], 0\njmp loc_15A2\nloc_14C9:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov ecx, [rax]\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\ncmp ecx, eax\njnz loc_1597\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov ecx, [rax+4]\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax+4]\ncmp ecx, eax\njnz short loc_1597\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov ecx, [rax+8]\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax+8]\ncmp ecx, eax\njz short loc_159E\nloc_1597:\nmov eax, 0\njmp short loc_15B3\nloc_159E:\nadd [rbp+var_4], 1\nloc_15A2:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl loc_14C9\nmov eax, 1\nloc_15B3:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3, int a4)\n{\n int i; // [rsp+24h] [rbp-4h]\n\n if ( a2 != a4 )\n return 0LL;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(_DWORD *)(12LL * i + a1) != *(_DWORD *)(12LL * i + a3)\n || *(_DWORD *)(12LL * i + a1 + 4) != *(_DWORD *)(12LL * i + a3 + 4)\n || *(_DWORD *)(12LL * i + a1 + 8) != *(_DWORD *)(12LL * i + a3 + 8) )\n {\n return 0LL;\n }\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1495:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_20]\njz short loc_14BD\nmov eax, 0\njmp loc_15B3\nloc_14BD:\nmov [rbp+var_4], 0\njmp loc_15A2\nloc_14C9:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov ecx, [rax]\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\ncmp ecx, eax\njnz loc_1597\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov ecx, [rax+4]\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax+4]\ncmp ecx, eax\njnz short loc_1597\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov ecx, [rax+8]\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax+8]\ncmp ecx, eax\njz short loc_159E\nloc_1597:\nmov eax, 0\njmp short loc_15B3\nloc_159E:\nadd [rbp+var_4], 1\nloc_15A2:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl loc_14C9\nmov eax, 1\nloc_15B3:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1495(__int64 a1, int a2, __int64 a3, int a4)\n{\n int i; // [rsp+24h] [rbp-4h]\n\n if ( a2 != a4 )\n return 0LL;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(_DWORD *)(12LL * i + a1) != *(_DWORD *)(12LL * i + a3)\n || *(_DWORD *)(12LL * i + a1 + 4) != *(_DWORD *)(12LL * i + a3 + 4)\n || *(_DWORD *)(12LL * i + a1 + 8) != *(_DWORD *)(12LL * i + a3 + 8) )\n {\n return 0LL;\n }\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1495(long long a1, int a2, long long a3, int a4) {\n int i;\n if (a2 != a4) return 0LL;\n for (i = 0; i < a2; ++i) {\n if (*(uint32_t *)(12LL * i + a1) != *(uint32_t *)(12LL * i + a3) ||\n *(uint32_t *)(12LL * i + a1 + 4) != *(uint32_t *)(12LL * i + a3 + 4) ||\n *(uint32_t *)(12LL * i + a1 + 8) != *(uint32_t *)(12LL * i + a3 + 8)) {\n return 0LL;\n }\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3, int a4) {\n int i;\n if (a2 != a4) return 0LL;\n for (i = 0; i < a2; ++i) {\n if (*(uint32_t *)(12LL * i + a1) != *(uint32_t *)(12LL * i + a3) ||\n *(uint32_t *)(12LL * i + a1 + 4) != *(uint32_t *)(12LL * i + a3 + 4) ||\n *(uint32_t *)(12LL * i + a1 + 8) != *(uint32_t *)(12LL * i + a3 + 8)) {\n return 0LL;\n }\n }\n return 1LL;\n}" + }, + { + "index": 237, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n} pair;\n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n int count;\n\n} pair_count;\n\n\n\n// Comparison function for qsort\n\nint compare_pairs(const void* a, const void* b) {\n\n pair* pa = (pair*)a;\n\n pair* pb = (pair*)b;\n\n if (pa->first != pb->first)\n\n return pa->first - pb->first;\n\n return pa->second - pb->second;\n\n}\n\n\n\n// Function to check occurrences\n\npair_count* check_occurences(pair* test_list, int size, int* out_size) {\n\n // Sort each pair\n\n for(int i = 0; i < size; i++) {\n\n if(test_list[i].first > test_list[i].second) {\n\n int temp = test_list[i].first;\n\n test_list[i].first = test_list[i].second;\n\n test_list[i].second = temp;\n\n }\n\n }\n\n // Sort the list of pairs\n\n qsort(test_list, size, sizeof(pair), compare_pairs);\n\n \n\n // Count occurrences\n\n pair_count* result = malloc(size * sizeof(pair_count));\n\n int unique = 0;\n\n for(int i = 0; i < size; i++) {\n\n if(unique == 0 || result[unique-1].first != test_list[i].first || result[unique-1].second != test_list[i].second) {\n\n result[unique].first = test_list[i].first;\n\n result[unique].second = test_list[i].second;\n\n result[unique].count = 1;\n\n unique++;\n\n }\n\n else {\n\n result[unique-1].count++;\n\n }\n\n }\n\n *out_size = unique;\n\n return result;\n\n}\n\n\n\n// Function to compare two pair_count arrays\n\n", + "func": "int func0(pair_count* a, int size_a, pair_count* b, int size_b) {\n if (size_a != size_b) return 0;\n for (int i = 0; i < size_a; i++) {\n if (a[i].first != b[i].first || a[i].second != b[i].second ||\n a[i].count != b[i].count)\n return 0;\n }\n return 1;\n}", + "test": "int main() {\n\n // First test case\n\n pair test1[] = { {3,1}, {1,3}, {2,5}, {5,2}, {6,3} };\n\n int size1 = sizeof(test1)/sizeof(pair);\n\n int out_size1;\n\n pair_count* res1 = check_occurences(test1, size1, &out_size1);\n\n pair_count expected1[] = { {1,3,2}, {2,5,2}, {3,6,1} };\n\n assert(func0(res1, out_size1, expected1, 3));\n\n free(res1);\n\n \n\n // Second test case\n\n pair test2[] = { {4,2}, {2,4}, {3,6}, {6,3}, {7,4} };\n\n int size2 = sizeof(test2)/sizeof(pair);\n\n int out_size2;\n\n pair_count* res2 = check_occurences(test2, size2, &out_size2);\n\n pair_count expected2[] = { {2,4,2}, {3,6,2}, {4,7,1} };\n\n assert(func0(res2, out_size2, expected2, 3));\n\n free(res2);\n\n \n\n // Third test case\n\n pair test3[] = { {13,2}, {11,23}, {12,25}, {25,12}, {16,23} };\n\n int size3 = sizeof(test3)/sizeof(pair);\n\n int out_size3;\n\n pair_count* res3 = check_occurences(test3, size3, &out_size3);\n\n pair_count expected3[] = { {2,13,1}, {11,23,1}, {12,25,2}, {16,23,1} };\n\n assert(func0(res3, out_size3, expected3, 4));\n\n free(res3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x0,%eax\ncmp %ecx,%esi\njne 1335 \ntest %esi,%esi\njle 131e \nmov %rdi,%rax\nlea -0x1(%rsi),%ecx\nlea (%rcx,%rcx,2),%rcx\nlea 0xc(%rdi,%rcx,4),%rdi\nmov (%rdx),%r8d\ncmp %r8d,(%rax)\njne 1324 \nmov 0x4(%rdx),%r9d\ncmp %r9d,0x4(%rax)\njne 132a \nmov 0x8(%rdx),%ecx\ncmp %ecx,0x8(%rax)\njne 1330 \nadd $0xc,%rax\nadd $0xc,%rdx\ncmp %rdi,%rax\njne 12f1 \nmov $0x1,%eax\nretq\nmov $0x1,%eax\nretq\nmov $0x0,%eax\nretq\nmov $0x0,%eax\nretq\nmov $0x0,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov eax, 0\ncmp esi, ecx\njnz short locret_1331\ntest esi, esi\njle short loc_131A\nmov rax, rdi\nmovsxd rsi, esi\nlea rcx, [rsi+rsi*2]\nlea rdi, [rdi+rcx*4]\nloc_12ED:\nmov r8d, [rdx]\ncmp [rax], r8d\njnz short loc_1320\nmov r9d, [rdx+4]\ncmp [rax+4], r9d\njnz short loc_1326\nmov ecx, [rdx+8]\ncmp [rax+8], ecx\njnz short loc_132C\nadd rax, 0Ch\nadd rdx, 0Ch\ncmp rax, rdi\njnz short loc_12ED\nmov eax, 1\nretn\nloc_131A:\nmov eax, 1\nretn\nloc_1320:\nmov eax, 0\nretn\nloc_1326:\nmov eax, 0\nretn\nloc_132C:\nmov eax, 0\nlocret_1331:\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2, _DWORD *a3, int a4)\n{\n __int64 result; // rax\n _DWORD *v5; // rax\n _DWORD *v6; // rdi\n\n result = 0LL;\n if ( a2 == a4 )\n {\n if ( a2 <= 0 )\n {\n return 1LL;\n }\n else\n {\n v5 = a1;\n v6 = &a1[3 * a2];\n while ( 1 )\n {\n if ( *v5 != *a3 )\n return 0LL;\n if ( v5[1] != a3[1] )\n return 0LL;\n if ( v5[2] != a3[2] )\n break;\n v5 += 3;\n a3 += 3;\n if ( v5 == v6 )\n return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_12CE:\nendbr64\nmov eax, 0\ncmp esi, ecx\njnz short locret_1331\ntest esi, esi\njle short loc_131A\nmov rax, rdi\nmovsxd rsi, esi\nlea rcx, [rsi+rsi*2]\nlea rdi, [rdi+rcx*4]\nloc_12ED:\nmov r8d, [rdx]\ncmp [rax], r8d\njnz short loc_1320\nmov r9d, [rdx+4]\ncmp [rax+4], r9d\njnz short loc_1326\nmov ecx, [rdx+8]\ncmp [rax+8], ecx\njnz short loc_132C\nadd rax, 0Ch\nadd rdx, 0Ch\ncmp rax, rdi\njnz short loc_12ED\nmov eax, 1\nretn\nloc_131A:\nmov eax, 1\nretn\nloc_1320:\nmov eax, 0\nretn\nloc_1326:\nmov eax, 0\nretn\nloc_132C:\nmov eax, 0\nlocret_1331:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12CE(_DWORD *a1, int a2, _DWORD *a3, int a4)\n{\n __int64 result; // rax\n _DWORD *v5; // rax\n _DWORD *v6; // rdi\n\n result = 0LL;\n if ( a2 == a4 )\n {\n if ( a2 <= 0 )\n {\n return 1LL;\n }\n else\n {\n v5 = a1;\n v6 = &a1[3 * a2];\n while ( 1 )\n {\n if ( *v5 != *a3 )\n return 0LL;\n if ( v5[1] != a3[1] )\n return 0LL;\n if ( v5[2] != a3[2] )\n break;\n v5 += 3;\n a3 += 3;\n if ( v5 == v6 )\n return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12CE(uint32_t *a1, int a2, uint32_t *a3, int a4) {\n long long result;\n uint32_t *v5;\n uint32_t *v6;\n result = 0LL;\n if (a2 == a4) {\n if (a2 <= 0) {\n return 1LL;\n } else {\n v5 = a1;\n v6 = &a1[3 * a2];\n while (1) {\n if (*v5 != *a3) return 0LL;\n if (v5[1] != a3[1]) return 0LL;\n if (v5[2] != a3[2]) break;\n v5 += 3;\n a3 += 3;\n if (v5 == v6) return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2, uint32_t *a3, int a4) {\n long long result;\n uint32_t *v5;\n uint32_t *v6;\n result = 0LL;\n if (a2 == a4) {\n if (a2 <= 0) {\n return 1LL;\n } else {\n v5 = a1;\n v6 = &a1[3 * a2];\n while (1) {\n if (*v5 != *a3) return 0LL;\n if (v5[1] != a3[1]) return 0LL;\n if (v5[2] != a3[2]) break;\n v5 += 3;\n a3 += 3;\n if (v5 == v6) return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}" + }, + { + "index": 237, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n} pair;\n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n int count;\n\n} pair_count;\n\n\n\n// Comparison function for qsort\n\nint compare_pairs(const void* a, const void* b) {\n\n pair* pa = (pair*)a;\n\n pair* pb = (pair*)b;\n\n if (pa->first != pb->first)\n\n return pa->first - pb->first;\n\n return pa->second - pb->second;\n\n}\n\n\n\n// Function to check occurrences\n\npair_count* check_occurences(pair* test_list, int size, int* out_size) {\n\n // Sort each pair\n\n for(int i = 0; i < size; i++) {\n\n if(test_list[i].first > test_list[i].second) {\n\n int temp = test_list[i].first;\n\n test_list[i].first = test_list[i].second;\n\n test_list[i].second = temp;\n\n }\n\n }\n\n // Sort the list of pairs\n\n qsort(test_list, size, sizeof(pair), compare_pairs);\n\n \n\n // Count occurrences\n\n pair_count* result = malloc(size * sizeof(pair_count));\n\n int unique = 0;\n\n for(int i = 0; i < size; i++) {\n\n if(unique == 0 || result[unique-1].first != test_list[i].first || result[unique-1].second != test_list[i].second) {\n\n result[unique].first = test_list[i].first;\n\n result[unique].second = test_list[i].second;\n\n result[unique].count = 1;\n\n unique++;\n\n }\n\n else {\n\n result[unique-1].count++;\n\n }\n\n }\n\n *out_size = unique;\n\n return result;\n\n}\n\n\n\n// Function to compare two pair_count arrays\n\n", + "func": "int func0(pair_count* a, int size_a, pair_count* b, int size_b) {\n if (size_a != size_b) return 0;\n for (int i = 0; i < size_a; i++) {\n if (a[i].first != b[i].first || a[i].second != b[i].second ||\n a[i].count != b[i].count)\n return 0;\n }\n return 1;\n}", + "test": "int main() {\n\n // First test case\n\n pair test1[] = { {3,1}, {1,3}, {2,5}, {5,2}, {6,3} };\n\n int size1 = sizeof(test1)/sizeof(pair);\n\n int out_size1;\n\n pair_count* res1 = check_occurences(test1, size1, &out_size1);\n\n pair_count expected1[] = { {1,3,2}, {2,5,2}, {3,6,1} };\n\n assert(func0(res1, out_size1, expected1, 3));\n\n free(res1);\n\n \n\n // Second test case\n\n pair test2[] = { {4,2}, {2,4}, {3,6}, {6,3}, {7,4} };\n\n int size2 = sizeof(test2)/sizeof(pair);\n\n int out_size2;\n\n pair_count* res2 = check_occurences(test2, size2, &out_size2);\n\n pair_count expected2[] = { {2,4,2}, {3,6,2}, {4,7,1} };\n\n assert(func0(res2, out_size2, expected2, 3));\n\n free(res2);\n\n \n\n // Third test case\n\n pair test3[] = { {13,2}, {11,23}, {12,25}, {25,12}, {16,23} };\n\n int size3 = sizeof(test3)/sizeof(pair);\n\n int out_size3;\n\n pair_count* res3 = check_occurences(test3, size3, &out_size3);\n\n pair_count expected3[] = { {2,13,1}, {11,23,1}, {12,25,2}, {16,23,1} };\n\n assert(func0(res3, out_size3, expected3, 4));\n\n free(res3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ncmp %ecx,%esi\njne 1690 \njmpq 1520 \nnopl (%rax)\nxor %eax,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0_part_0:\ntest esi, esi\njle short loc_14A0\nmovsxd rsi, esi\nlea rax, [rsi+rsi*2]\nlea rax, [rdi+rax*4]\njmp short loc_1495\nloc_1478:\nmov esi, [rdx+4]\ncmp [rdi+4], esi\njnz short loc_149B\nmov ecx, [rdx+8]\ncmp [rdi+8], ecx\njnz short loc_149B\nadd rdi, 0Ch\nadd rdx, 0Ch\ncmp rdi, rax\njz short loc_14A0\nloc_1495:\nmov ecx, [rdx]\ncmp [rdi], ecx\njz short loc_1478\nloc_149B:\nxor eax, eax\nretn\nloc_14A0:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0_part_0(_DWORD *a1, int a2, _DWORD *a3)\n{\n _DWORD *v3; // rax\n\n if ( a2 <= 0 )\n return 1LL;\n v3 = &a1[3 * a2];\n while ( *a1 == *a3 && a1[1] == a3[1] && a1[2] == a3[2] )\n {\n a1 += 3;\n a3 += 3;\n if ( a1 == v3 )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1460:\ntest esi, esi\njle short loc_14A0\nmovsxd rsi, esi\nlea rax, [rsi+rsi*2]\nlea rax, [rdi+rax*4]\njmp short loc_1495\nloc_1478:\nmov esi, [rdx+4]\ncmp [rdi+4], esi\njnz short loc_149B\nmov ecx, [rdx+8]\ncmp [rdi+8], ecx\njnz short loc_149B\nadd rdi, 0Ch\nadd rdx, 0Ch\ncmp rdi, rax\njz short loc_14A0\nloc_1495:\nmov ecx, [rdx]\ncmp [rdi], ecx\njz short loc_1478\nloc_149B:\nxor eax, eax\nretn\nloc_14A0:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1460(_DWORD *a1, int a2, _DWORD *a3)\n{\n _DWORD *v3; // rax\n\n if ( a2 <= 0 )\n return 1LL;\n v3 = &a1[3 * a2];\n while ( *a1 == *a3 && a1[1] == a3[1] && a1[2] == a3[2] )\n {\n a1 += 3;\n a3 += 3;\n if ( a1 == v3 )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1460(uint32_t *a1, int a2, uint32_t *a3) {\n uint32_t *v3;\n if (a2 <= 0) return 1LL;\n v3 = &a1[3 * a2];\n while (*a1 == *a3 && a1[1] == a3[1] && a1[2] == a3[2]) {\n a1 += 3;\n a3 += 3;\n if (a1 == v3) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0_part_0(uint32_t *a1, int a2, uint32_t *a3) {\n uint32_t *v3;\n if (a2 <= 0) return 1LL;\n v3 = &a1[3 * a2];\n while (*a1 == *a3 && a1[1] == a3[1] && a1[2] == a3[2]) {\n a1 += 3;\n a3 += 3;\n if (a1 == v3) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 237, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n} pair;\n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n int count;\n\n} pair_count;\n\n\n\n// Comparison function for qsort\n\nint compare_pairs(const void* a, const void* b) {\n\n pair* pa = (pair*)a;\n\n pair* pb = (pair*)b;\n\n if (pa->first != pb->first)\n\n return pa->first - pb->first;\n\n return pa->second - pb->second;\n\n}\n\n\n\n// Function to check occurrences\n\npair_count* check_occurences(pair* test_list, int size, int* out_size) {\n\n // Sort each pair\n\n for(int i = 0; i < size; i++) {\n\n if(test_list[i].first > test_list[i].second) {\n\n int temp = test_list[i].first;\n\n test_list[i].first = test_list[i].second;\n\n test_list[i].second = temp;\n\n }\n\n }\n\n // Sort the list of pairs\n\n qsort(test_list, size, sizeof(pair), compare_pairs);\n\n \n\n // Count occurrences\n\n pair_count* result = malloc(size * sizeof(pair_count));\n\n int unique = 0;\n\n for(int i = 0; i < size; i++) {\n\n if(unique == 0 || result[unique-1].first != test_list[i].first || result[unique-1].second != test_list[i].second) {\n\n result[unique].first = test_list[i].first;\n\n result[unique].second = test_list[i].second;\n\n result[unique].count = 1;\n\n unique++;\n\n }\n\n else {\n\n result[unique-1].count++;\n\n }\n\n }\n\n *out_size = unique;\n\n return result;\n\n}\n\n\n\n// Function to compare two pair_count arrays\n\n", + "func": "int func0(pair_count* a, int size_a, pair_count* b, int size_b) {\n if (size_a != size_b) return 0;\n for (int i = 0; i < size_a; i++) {\n if (a[i].first != b[i].first || a[i].second != b[i].second ||\n a[i].count != b[i].count)\n return 0;\n }\n return 1;\n}", + "test": "int main() {\n\n // First test case\n\n pair test1[] = { {3,1}, {1,3}, {2,5}, {5,2}, {6,3} };\n\n int size1 = sizeof(test1)/sizeof(pair);\n\n int out_size1;\n\n pair_count* res1 = check_occurences(test1, size1, &out_size1);\n\n pair_count expected1[] = { {1,3,2}, {2,5,2}, {3,6,1} };\n\n assert(func0(res1, out_size1, expected1, 3));\n\n free(res1);\n\n \n\n // Second test case\n\n pair test2[] = { {4,2}, {2,4}, {3,6}, {6,3}, {7,4} };\n\n int size2 = sizeof(test2)/sizeof(pair);\n\n int out_size2;\n\n pair_count* res2 = check_occurences(test2, size2, &out_size2);\n\n pair_count expected2[] = { {2,4,2}, {3,6,2}, {4,7,1} };\n\n assert(func0(res2, out_size2, expected2, 3));\n\n free(res2);\n\n \n\n // Third test case\n\n pair test3[] = { {13,2}, {11,23}, {12,25}, {25,12}, {16,23} };\n\n int size3 = sizeof(test3)/sizeof(pair);\n\n int out_size3;\n\n pair_count* res3 = check_occurences(test3, size3, &out_size3);\n\n pair_count expected3[] = { {2,13,1}, {11,23,1}, {12,25,2}, {16,23,1} };\n\n assert(func0(res3, out_size3, expected3, 4));\n\n free(res3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nxor %eax,%eax\ncmp %ecx,%esi\njne 1615 \ntest %esi,%esi\njle 1620 \nlea -0x1(%rsi),%eax\nlea (%rax,%rax,2),%rax\nlea 0xc(%rdi,%rax,4),%rax\njmp 160d \nnopl 0x0(%rax)\nmov 0x4(%rdx),%esi\ncmp %esi,0x4(%rdi)\njne 1613 \nmov 0x8(%rdx),%ecx\ncmp %ecx,0x8(%rdi)\njne 1613 \nadd $0xc,%rdi\nadd $0xc,%rdx\ncmp %rax,%rdi\nje 1620 \nmov (%rdx),%ecx\ncmp %ecx,(%rdi)\nje 15f0 \nxor %eax,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nmov $0x1,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0_part_0:\ntest esi, esi\njle short loc_14A0\nmovsxd rsi, esi\nlea rax, [rsi+rsi*2]\nlea rax, [rdi+rax*4]\njmp short loc_1495\nloc_1478:\nmov esi, [rdx+4]\ncmp [rdi+4], esi\njnz short loc_149B\nmov ecx, [rdx+8]\ncmp [rdi+8], ecx\njnz short loc_149B\nadd rdi, 0Ch\nadd rdx, 0Ch\ncmp rdi, rax\njz short loc_14A0\nloc_1495:\nmov ecx, [rdx]\ncmp [rdi], ecx\njz short loc_1478\nloc_149B:\nxor eax, eax\nretn\nloc_14A0:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0_part_0(_DWORD *a1, int a2, _DWORD *a3)\n{\n _DWORD *v3; // rax\n\n if ( a2 <= 0 )\n return 1LL;\n v3 = &a1[3 * a2];\n while ( *a1 == *a3 && a1[1] == a3[1] && a1[2] == a3[2] )\n {\n a1 += 3;\n a3 += 3;\n if ( a1 == v3 )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1460:\ntest esi, esi\njle short loc_14A0\nmovsxd rsi, esi\nlea rax, [rsi+rsi*2]\nlea rax, [rdi+rax*4]\njmp short loc_1495\nloc_1478:\nmov esi, [rdx+4]\ncmp [rdi+4], esi\njnz short loc_149B\nmov ecx, [rdx+8]\ncmp [rdi+8], ecx\njnz short loc_149B\nadd rdi, 0Ch\nadd rdx, 0Ch\ncmp rdi, rax\njz short loc_14A0\nloc_1495:\nmov ecx, [rdx]\ncmp [rdi], ecx\njz short loc_1478\nloc_149B:\nxor eax, eax\nretn\nloc_14A0:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1460(_DWORD *a1, int a2, _DWORD *a3)\n{\n _DWORD *v3; // rax\n\n if ( a2 <= 0 )\n return 1LL;\n v3 = &a1[3 * a2];\n while ( *a1 == *a3 && a1[1] == a3[1] && a1[2] == a3[2] )\n {\n a1 += 3;\n a3 += 3;\n if ( a1 == v3 )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1460(uint32_t *a1, int a2, uint32_t *a3) {\n uint32_t *v3;\n if (a2 <= 0) return 1LL;\n v3 = &a1[3 * a2];\n while (*a1 == *a3 && a1[1] == a3[1] && a1[2] == a3[2]) {\n a1 += 3;\n a3 += 3;\n if (a1 == v3) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0_part_0(uint32_t *a1, int a2, uint32_t *a3) {\n uint32_t *v3;\n if (a2 <= 0) return 1LL;\n v3 = &a1[3 * a2];\n while (*a1 == *a3 && a1[1] == a3[1] && a1[2] == a3[2]) {\n a1 += 3;\n a3 += 3;\n if (a1 == v3) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 238, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char* str) {\n int str_len = strlen(str);\n return (str_len * (str_len + 1)) / 2;\n}", + "test": "int main() {\n\n assert(func0(\"abc\") == 6);\n\n assert(func0(\"abcd\") == 10);\n\n assert(func0(\"abcde\") == 15);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov -0x18(%rbp),%rax\nmov %rax,%rdi\ncallq 1060 \nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nadd $0x1,%eax\nimul -0x4(%rbp),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\nadd eax, 1\nimul eax, [rbp+var_4]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v2; // [rsp+1Ch] [rbp-4h]\n\n v2 = strlen(a1);\n return (unsigned int)(v2 * (v2 + 1) / 2);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\nadd eax, 1\nimul eax, [rbp+var_4]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1)\n{\n int v2; // [rsp+1Ch] [rbp-4h]\n\n v2 = strlen(a1);\n return (unsigned int)(v2 * (v2 + 1) / 2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1) {\n int v2;\n v2 = strlen(a1);\n return (unsigned int)(v2 * (v2 + 1) / 2);\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v2;\n v2 = strlen(a1);\n return (unsigned int)(v2 * (v2 + 1) / 2);\n}" + }, + { + "index": 238, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char* str) {\n int str_len = strlen(str);\n return (str_len * (str_len + 1)) / 2;\n}", + "test": "int main() {\n\n assert(func0(\"abc\") == 6);\n\n assert(func0(\"abcd\") == 10);\n\n assert(func0(\"abcde\") == 15);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nlea -0x1(%rcx),%rax\nimul %eax,%ecx\nmov %ecx,%eax\nshr $0x1f,%eax\nadd %ecx,%eax\nsar %eax\nretq\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\ncall _strlen\nlea edx, [rax+1]\nimul edx, eax\nmov eax, edx\nshr eax, 1Fh\nadd eax, edx\nsar eax, 1\nadd rsp, 8\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v1; // eax\n\n v1 = strlen(a1);\n return (unsigned int)(v1 * (v1 + 1) / 2);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nsub rsp, 8\ncall _strlen\nlea edx, [rax+1]\nimul edx, eax\nmov eax, edx\nshr eax, 1Fh\nadd eax, edx\nsar eax, 1\nadd rsp, 8\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1)\n{\n int v1; // eax\n\n v1 = strlen(a1);\n return (unsigned int)(v1 * (v1 + 1) / 2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1) {\n int v1;\n v1 = strlen(a1);\n return (unsigned int)(v1 * (v1 + 1) / 2);\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v1;\n v1 = strlen(a1);\n return (unsigned int)(v1 * (v1 + 1) / 2);\n}" + }, + { + "index": 238, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char* str) {\n int str_len = strlen(str);\n return (str_len * (str_len + 1)) / 2;\n}", + "test": "int main() {\n\n assert(func0(\"abc\") == 6);\n\n assert(func0(\"abcd\") == 10);\n\n assert(func0(\"abcde\") == 15);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x8,%rsp\ncallq 1050 \nadd $0x8,%rsp\nmov %rax,%rdx\nlea 0x1(%rax),%eax\nimul %eax,%edx\nmov %edx,%eax\nshr $0x1f,%eax\nadd %edx,%eax\nsar %eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\ncall _strlen\nadd rsp, 8\nlea edx, [rax+1]\nimul edx, eax\nmov eax, edx\nshr eax, 1Fh\nadd eax, edx\nsar eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v1; // eax\n\n v1 = strlen(a1);\n return (unsigned int)(v1 * (v1 + 1) / 2);\n}", + "ida_strip_asm": "sub_1160:\nendbr64\nsub rsp, 8\ncall _strlen\nadd rsp, 8\nlea edx, [rax+1]\nimul edx, eax\nmov eax, edx\nshr eax, 1Fh\nadd eax, edx\nsar eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1160(const char *a1)\n{\n int v1; // eax\n\n v1 = strlen(a1);\n return (unsigned int)(v1 * (v1 + 1) / 2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1160(const char *a1) {\n int v1;\n v1 = strlen(a1);\n return (unsigned int)(v1 * (v1 + 1) / 2);\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v1;\n v1 = strlen(a1);\n return (unsigned int)(v1 * (v1 + 1) / 2);\n}" + }, + { + "index": 238, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char* str) {\n int str_len = strlen(str);\n return (str_len * (str_len + 1)) / 2;\n}", + "test": "int main() {\n\n assert(func0(\"abc\") == 6);\n\n assert(func0(\"abcd\") == 10);\n\n assert(func0(\"abcde\") == 15);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x8,%rsp\ncallq 1050 \nadd $0x8,%rsp\nmov %rax,%rdx\nlea 0x1(%rax),%eax\nimul %eax,%edx\nmov %edx,%eax\nshr $0x1f,%eax\nadd %edx,%eax\nsar %eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\ncall _strlen\nadd rsp, 8\nlea edx, [rax+1]\nimul edx, eax\nmov eax, edx\nshr eax, 1Fh\nadd eax, edx\nsar eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v1; // eax\n\n v1 = strlen(a1);\n return (unsigned int)(v1 * (v1 + 1) / 2);\n}", + "ida_strip_asm": "sub_1160:\nendbr64\nsub rsp, 8\ncall _strlen\nadd rsp, 8\nlea edx, [rax+1]\nimul edx, eax\nmov eax, edx\nshr eax, 1Fh\nadd eax, edx\nsar eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1160(const char *a1)\n{\n int v1; // eax\n\n v1 = strlen(a1);\n return (unsigned int)(v1 * (v1 + 1) / 2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1160(const char *a1) {\n int v1;\n v1 = strlen(a1);\n return (unsigned int)(v1 * (v1 + 1) / 2);\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v1;\n v1 = strlen(a1);\n return (unsigned int)(v1 * (v1 + 1) / 2);\n}" + }, + { + "index": 239, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int m, int n) {\n int T[m + 1][n + 1];\n for (int i = 0; i <= m; i++) {\n for (int j = 0; j <= n; j++) {\n if (i == 0 || j == 0) {\n T[i][j] = 0;\n } else if (i < j) {\n T[i][j] = 0;\n } else if (j == 1) {\n T[i][j] = i;\n } else {\n T[i][j] = T[i - 1][j] + T[i / 2][j - 1];\n }\n }\n }\n return T[m][n];\n}", + "test": "int main() {\n\n assert(func0(10, 4) == 4);\n\n assert(func0(5, 2) == 6);\n\n assert(func0(16, 3) == 84);\n\n return 0;\n\n} \n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0x58,%rsp\nmov %edi,-0x64(%rbp)\nmov %esi,-0x68(%rbp)\nmov %fs:0x28,%rbx\nmov %rbx,-0x38(%rbp)\nxor %ebx,%ebx\nmov %rsp,%rcx\nmov %rcx,%r15\nmov -0x68(%rbp),%ecx\nlea 0x1(%rcx),%esi\nmov -0x64(%rbp),%ecx\nlea 0x1(%rcx),%edi\nmovslq %esi,%rcx\nsub $0x1,%rcx\nmov %rcx,-0x50(%rbp)\nmovslq %esi,%rcx\nmov %rcx,-0x80(%rbp)\nmovq $0x0,-0x78(%rbp)\nmovslq %esi,%rcx\nshl $0x2,%rcx\nmovslq %edi,%rbx\nsub $0x1,%rbx\nmov %rbx,-0x48(%rbp)\nmovslq %esi,%rbx\nmov %rbx,%r12\nmov $0x0,%r13d\nmovslq %edi,%rbx\nmov %rbx,%rax\nmov $0x0,%edx\nmov %r13,%r14\nimul %rax,%r14\nmov %rdx,%rbx\nimul %r12,%rbx\nadd %r14,%rbx\nmul %r12\nadd %rdx,%rbx\nmov %rbx,%rdx\nmovslq %esi,%rax\nmov %rax,%r10\nmov $0x0,%r11d\nmovslq %edi,%rax\nmov %rax,%r8\nmov $0x0,%r9d\nmov %r11,%rdx\nimul %r8,%rdx\nmov %r9,%rax\nimul %r10,%rax\nlea (%rdx,%rax,1),%rbx\nmov %r10,%rax\nmul %r8\nlea (%rbx,%rdx,1),%r8\nmov %r8,%rdx\nmovslq %esi,%rdx\nmovslq %edi,%rax\nimul %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%ebx\nmov $0x0,%edx\ndiv %rbx\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rdi\nsub %rdx,%rdi\nmov %rdi,%rdx\ncmp %rdx,%rsp\nje 1292 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 127b \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 12bc \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x40(%rbp)\nmovl $0x0,-0x54(%rbp)\njmpq 1408 \nmovl $0x0,-0x58(%rbp)\njmpq 13f8 \ncmpl $0x0,-0x54(%rbp)\nje 12f3 \ncmpl $0x0,-0x58(%rbp)\njne 131d \nmov %rcx,%rdi\nshr $0x2,%rdi\nmov -0x40(%rbp),%rax\nmov -0x58(%rbp),%edx\nmovslq %edx,%rsi\nmov -0x54(%rbp),%edx\nmovslq %edx,%rdx\nimul %rdi,%rdx\nadd %rsi,%rdx\nmovl $0x0,(%rax,%rdx,4)\njmpq 13f4 \nmov -0x54(%rbp),%eax\ncmp -0x58(%rbp),%eax\njge 134f \nmov %rcx,%rdi\nshr $0x2,%rdi\nmov -0x40(%rbp),%rax\nmov -0x58(%rbp),%edx\nmovslq %edx,%rsi\nmov -0x54(%rbp),%edx\nmovslq %edx,%rdx\nimul %rdi,%rdx\nadd %rsi,%rdx\nmovl $0x0,(%rax,%rdx,4)\njmpq 13f4 \ncmpl $0x1,-0x58(%rbp)\njne 137b \nmov %rcx,%rdi\nshr $0x2,%rdi\nmov -0x40(%rbp),%rax\nmov -0x58(%rbp),%edx\nmovslq %edx,%rsi\nmov -0x54(%rbp),%edx\nmovslq %edx,%rdx\nimul %rdi,%rdx\nadd %rdx,%rsi\nmov -0x54(%rbp),%edx\nmov %edx,(%rax,%rsi,4)\njmp 13f4 \nmov %rcx,%rdi\nshr $0x2,%rdi\nmov -0x54(%rbp),%eax\nlea -0x1(%rax),%r8d\nmov -0x40(%rbp),%rax\nmov -0x58(%rbp),%edx\nmovslq %edx,%rsi\nmovslq %r8d,%rdx\nimul %rdi,%rdx\nadd %rsi,%rdx\nmov (%rax,%rdx,4),%edx\nmov %rcx,%r8\nshr $0x2,%r8\nmov -0x54(%rbp),%eax\nmov %eax,%esi\nshr $0x1f,%esi\nadd %esi,%eax\nsar %eax\nmov %eax,%r9d\nmov -0x58(%rbp),%eax\nlea -0x1(%rax),%esi\nmov -0x40(%rbp),%rax\nmovslq %esi,%rdi\nmovslq %r9d,%rsi\nimul %r8,%rsi\nadd %rdi,%rsi\nmov (%rax,%rsi,4),%eax\nmov %rcx,%r8\nshr $0x2,%r8\nlea (%rdx,%rax,1),%esi\nmov -0x40(%rbp),%rax\nmov -0x58(%rbp),%edx\nmovslq %edx,%rdi\nmov -0x54(%rbp),%edx\nmovslq %edx,%rdx\nimul %r8,%rdx\nadd %rdi,%rdx\nmov %esi,(%rax,%rdx,4)\naddl $0x1,-0x58(%rbp)\nmov -0x58(%rbp),%eax\ncmp -0x68(%rbp),%eax\njle 12e7 \naddl $0x1,-0x54(%rbp)\nmov -0x54(%rbp),%eax\ncmp -0x64(%rbp),%eax\njle 12db \nshr $0x2,%rcx\nmov %rcx,%rsi\nmov -0x40(%rbp),%rax\nmov -0x68(%rbp),%edx\nmovslq %edx,%rcx\nmov -0x64(%rbp),%edx\nmovslq %edx,%rdx\nimul %rsi,%rdx\nadd %rcx,%rdx\nmov (%rax,%rdx,4),%eax\nmov %r15,%rsp\nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\nje 144c \ncallq 1060 <__stack_chk_fail@plt>\nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 48h\nmov [rbp+var_44], edi\nmov [rbp+var_48], esi\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov rax, rsp\nmov rbx, rax\nmov eax, [rbp+var_48]\nlea r8d, [rax+1]\nmov eax, [rbp+var_44]\nlea r9d, [rax+1]\nmovsxd rax, r8d\nsub rax, 1\nmov [rbp+var_30], rax\nmovsxd rax, r8d\nlea rcx, ds:0[rax*4]\nmovsxd rax, r9d\nsub rax, 1\nmov [rbp+var_28], rax\nmovsxd rax, r8d\nmov rsi, rax\nmov edi, 0\nmovsxd rax, r9d\nmov rax, rax\nmov edx, 0\nmov r11, rdi\nimul r11, rax\nmov r10, rdx\nimul r10, rsi\nadd r10, r11\nmul rsi\nlea rsi, [r10+rdx]\nmov rdx, rsi\nmovsxd rax, r8d\nmov rsi, rax\nmov edi, 0\nmovsxd rax, r9d\nmov rax, rax\nmov edx, 0\nmov r11, rdi\nimul r11, rax\nmov r10, rdx\nimul r10, rsi\nadd r10, r11\nmul rsi\nlea rsi, [r10+rdx]\nmov rdx, rsi\nmovsxd rdx, r8d\nmovsxd rax, r9d\nimul rax, rdx\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rsi, rax\nand rsi, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rsi\nloc_1261:\ncmp rsp, rdx\njz short loc_1278\nsub rsp, 1000h\nor [rsp+1050h+var_58], 0\njmp short loc_1261\nloc_1278:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_12A2\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_12A2:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_20], rax\nmov [rbp+var_38], 0\njmp loc_13ED\nloc_12C1:\nmov [rbp+var_34], 0\njmp loc_13DD\nloc_12CD:\ncmp [rbp+var_38], 0\njz short loc_12D9\ncmp [rbp+var_34], 0\njnz short loc_1303\nloc_12D9:\nmov rdi, rcx\nshr rdi, 2\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_34]\nmovsxd rsi, edx\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nimul rdx, rdi\nadd rdx, rsi\nmov dword ptr [rax+rdx*4], 0\njmp loc_13D9\nloc_1303:\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_34]\njge short loc_1335\nmov rdi, rcx\nshr rdi, 2\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_34]\nmovsxd rsi, edx\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nimul rdx, rdi\nadd rdx, rsi\nmov dword ptr [rax+rdx*4], 0\njmp loc_13D9\nloc_1335:\ncmp [rbp+var_34], 1\njnz short loc_1361\nmov rdi, rcx\nshr rdi, 2\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_34]\nmovsxd rsi, edx\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nimul rdx, rdi\nadd rsi, rdx\nmov edx, [rbp+var_38]\nmov [rax+rsi*4], edx\njmp short loc_13D9\nloc_1361:\nmov rdi, rcx\nshr rdi, 2\nmov eax, [rbp+var_38]\nlea r8d, [rax-1]\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_34]\nmovsxd rsi, edx\nmovsxd rdx, r8d\nimul rdx, rdi\nadd rdx, rsi\nmov esi, [rax+rdx*4]\nmov r8, rcx\nshr r8, 2\nmov eax, [rbp+var_38]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov r9d, eax\nmov eax, [rbp+var_34]\nlea edx, [rax-1]\nmov rax, [rbp+var_20]\nmovsxd rdi, edx\nmovsxd rdx, r9d\nimul rdx, r8\nadd rdx, rdi\nmov eax, [rax+rdx*4]\nmov r8, rcx\nshr r8, 2\nadd esi, eax\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_34]\nmovsxd rdi, edx\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nimul rdx, r8\nadd rdx, rdi\nmov [rax+rdx*4], esi\nloc_13D9:\nadd [rbp+var_34], 1\nloc_13DD:\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_48]\njle loc_12CD\nadd [rbp+var_38], 1\nloc_13ED:\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_44]\njle loc_12C1\nshr rcx, 2\nmov rsi, rcx\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_48]\nmovsxd rcx, edx\nmov edx, [rbp+var_44]\nmovsxd rdx, edx\nimul rdx, rsi\nadd rdx, rcx\nmov eax, [rax+rdx*4]\nmov rsp, rbx\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njz short loc_1431\ncall ___stack_chk_fail\nloc_1431:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n unsigned __int64 v2; // rcx\n unsigned __int64 v3; // rax\n void *v4; // rsp\n _BYTE v6[8]; // [rsp+8h] [rbp-50h] BYREF\n int v7; // [rsp+10h] [rbp-48h]\n int v8; // [rsp+14h] [rbp-44h]\n int i; // [rsp+20h] [rbp-38h]\n int j; // [rsp+24h] [rbp-34h]\n __int64 v11; // [rsp+28h] [rbp-30h]\n __int64 v12; // [rsp+30h] [rbp-28h]\n _BYTE *v13; // [rsp+38h] [rbp-20h]\n unsigned __int64 v14; // [rsp+40h] [rbp-18h]\n\n v8 = a1;\n v7 = a2;\n v14 = __readfsqword(0x28u);\n v11 = a2 + 1 - 1LL;\n v2 = 4LL * (a2 + 1);\n v12 = a1 + 1 - 1LL;\n v3 = 16 * ((4 * (a2 + 1) * (__int64)(a1 + 1) + 15) / 0x10uLL);\n while ( v6 != &v6[-(v3 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v4 = alloca(v3 & 0xFFF);\n if ( (v3 & 0xFFF) != 0 )\n *(_QWORD *)&v6[(v3 & 0xFFF) - 8] = *(_QWORD *)&v6[(v3 & 0xFFF) - 8];\n v13 = v6;\n for ( i = 0; i <= v8; ++i )\n {\n for ( j = 0; j <= v7; ++j )\n {\n if ( i && j )\n {\n if ( i >= j )\n {\n if ( j == 1 )\n *(_DWORD *)&v13[4 * (v2 >> 2) * i + 4] = i;\n else\n *(_DWORD *)&v13[4 * j + 4 * (v2 >> 2) * i] = *(_DWORD *)&v13[4 * j - 4 + 4 * (v2 >> 2) * (i / 2)]\n + *(_DWORD *)&v13[4 * j + 4 * (v2 >> 2) * (i - 1)];\n }\n else\n {\n *(_DWORD *)&v13[4 * j + 4 * (v2 >> 2) * i] = 0;\n }\n }\n else\n {\n *(_DWORD *)&v13[4 * j + 4 * (v2 >> 2) * i] = 0;\n }\n }\n }\n return *(unsigned int *)&v13[4 * v7 + 4 * (v2 >> 2) * v8];\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 48h\nmov [rbp+var_44], edi\nmov [rbp+var_48], esi\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov rax, rsp\nmov rbx, rax\nmov eax, [rbp+var_48]\nlea r8d, [rax+1]\nmov eax, [rbp+var_44]\nlea r9d, [rax+1]\nmovsxd rax, r8d\nsub rax, 1\nmov [rbp+var_30], rax\nmovsxd rax, r8d\nlea rcx, ds:0[rax*4]\nmovsxd rax, r9d\nsub rax, 1\nmov [rbp+var_28], rax\nmovsxd rax, r8d\nmov rsi, rax\nmov edi, 0\nmovsxd rax, r9d\nmov rax, rax\nmov edx, 0\nmov r11, rdi\nimul r11, rax\nmov r10, rdx\nimul r10, rsi\nadd r10, r11\nmul rsi\nlea rsi, [r10+rdx]\nmov rdx, rsi\nmovsxd rax, r8d\nmov rsi, rax\nmov edi, 0\nmovsxd rax, r9d\nmov rax, rax\nmov edx, 0\nmov r11, rdi\nimul r11, rax\nmov r10, rdx\nimul r10, rsi\nadd r10, r11\nmul rsi\nlea rsi, [r10+rdx]\nmov rdx, rsi\nmovsxd rdx, r8d\nmovsxd rax, r9d\nimul rax, rdx\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rsi, rax\nand rsi, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rsi\nloc_1261:\ncmp rsp, rdx\njz short loc_1278\nsub rsp, 1000h\nor [rsp+1050h+var_58], 0\njmp short loc_1261\nloc_1278:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_12A2\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_12A2:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_20], rax\nmov [rbp+var_38], 0\njmp loc_13ED\nloc_12C1:\nmov [rbp+var_34], 0\njmp loc_13DD\nloc_12CD:\ncmp [rbp+var_38], 0\njz short loc_12D9\ncmp [rbp+var_34], 0\njnz short loc_1303\nloc_12D9:\nmov rdi, rcx\nshr rdi, 2\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_34]\nmovsxd rsi, edx\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nimul rdx, rdi\nadd rdx, rsi\nmov dword ptr [rax+rdx*4], 0\njmp loc_13D9\nloc_1303:\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_34]\njge short loc_1335\nmov rdi, rcx\nshr rdi, 2\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_34]\nmovsxd rsi, edx\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nimul rdx, rdi\nadd rdx, rsi\nmov dword ptr [rax+rdx*4], 0\njmp loc_13D9\nloc_1335:\ncmp [rbp+var_34], 1\njnz short loc_1361\nmov rdi, rcx\nshr rdi, 2\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_34]\nmovsxd rsi, edx\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nimul rdx, rdi\nadd rsi, rdx\nmov edx, [rbp+var_38]\nmov [rax+rsi*4], edx\njmp short loc_13D9\nloc_1361:\nmov rdi, rcx\nshr rdi, 2\nmov eax, [rbp+var_38]\nlea r8d, [rax-1]\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_34]\nmovsxd rsi, edx\nmovsxd rdx, r8d\nimul rdx, rdi\nadd rdx, rsi\nmov esi, [rax+rdx*4]\nmov r8, rcx\nshr r8, 2\nmov eax, [rbp+var_38]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov r9d, eax\nmov eax, [rbp+var_34]\nlea edx, [rax-1]\nmov rax, [rbp+var_20]\nmovsxd rdi, edx\nmovsxd rdx, r9d\nimul rdx, r8\nadd rdx, rdi\nmov eax, [rax+rdx*4]\nmov r8, rcx\nshr r8, 2\nadd esi, eax\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_34]\nmovsxd rdi, edx\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nimul rdx, r8\nadd rdx, rdi\nmov [rax+rdx*4], esi\nloc_13D9:\nadd [rbp+var_34], 1\nloc_13DD:\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_48]\njle loc_12CD\nadd [rbp+var_38], 1\nloc_13ED:\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_44]\njle loc_12C1\nshr rcx, 2\nmov rsi, rcx\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_48]\nmovsxd rcx, edx\nmov edx, [rbp+var_44]\nmovsxd rdx, edx\nimul rdx, rsi\nadd rdx, rcx\nmov eax, [rax+rdx*4]\nmov rsp, rbx\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njz short loc_1431\ncall ___stack_chk_fail\nloc_1431:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1, int a2)\n{\n unsigned __int64 v2; // rcx\n unsigned __int64 v3; // rax\n void *v4; // rsp\n _BYTE v6[8]; // [rsp+8h] [rbp-50h] BYREF\n int v7; // [rsp+10h] [rbp-48h]\n int v8; // [rsp+14h] [rbp-44h]\n int i; // [rsp+20h] [rbp-38h]\n int j; // [rsp+24h] [rbp-34h]\n __int64 v11; // [rsp+28h] [rbp-30h]\n __int64 v12; // [rsp+30h] [rbp-28h]\n _BYTE *v13; // [rsp+38h] [rbp-20h]\n unsigned __int64 v14; // [rsp+40h] [rbp-18h]\n\n v8 = a1;\n v7 = a2;\n v14 = __readfsqword(0x28u);\n v11 = a2 + 1 - 1LL;\n v2 = 4LL * (a2 + 1);\n v12 = a1 + 1 - 1LL;\n v3 = 16 * ((4 * (a2 + 1) * (__int64)(a1 + 1) + 15) / 0x10uLL);\n while ( v6 != &v6[-(v3 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v4 = alloca(v3 & 0xFFF);\n if ( (v3 & 0xFFF) != 0 )\n *(_QWORD *)&v6[(v3 & 0xFFF) - 8] = *(_QWORD *)&v6[(v3 & 0xFFF) - 8];\n v13 = v6;\n for ( i = 0; i <= v8; ++i )\n {\n for ( j = 0; j <= v7; ++j )\n {\n if ( i && j )\n {\n if ( i >= j )\n {\n if ( j == 1 )\n *(_DWORD *)&v13[4 * (v2 >> 2) * i + 4] = i;\n else\n *(_DWORD *)&v13[4 * j + 4 * (v2 >> 2) * i] = *(_DWORD *)&v13[4 * j - 4 + 4 * (v2 >> 2) * (i / 2)]\n + *(_DWORD *)&v13[4 * j + 4 * (v2 >> 2) * (i - 1)];\n }\n else\n {\n *(_DWORD *)&v13[4 * j + 4 * (v2 >> 2) * i] = 0;\n }\n }\n else\n {\n *(_DWORD *)&v13[4 * j + 4 * (v2 >> 2) * i] = 0;\n }\n }\n }\n return *(unsigned int *)&v13[4 * v7 + 4 * (v2 >> 2) * v8];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1, int a2) {\n unsigned long long v2;\n unsigned long long v3;\n void *v4;\n uint8_t v6[8];\n int v7;\n int v8;\n int i;\n int j;\n long long v11;\n long long v12;\n uint8_t *v13;\n unsigned long long v14;\n v8 = a1;\n v7 = a2;\n v14 = __readfsqword(40u);\n v11 = a2 + 1 - 1LL;\n v2 = 4LL * (a2 + 1);\n v12 = a1 + 1 - 1LL;\n v3 = 16 * ((4 * (a2 + 1) * (long long)(a1 + 1) + 15) / 16uLL);\n while (v6 != &v6[-(v3 & 18446744073709547520LL)])\n ;\n v4 = alloca(v3 & 4095);\n if ((v3 & 4095) != 0)\n *(uint64_t *)&v6[(v3 & 4095) - 8] = *(uint64_t *)&v6[(v3 & 4095) - 8];\n v13 = v6;\n for (i = 0; i <= v8; ++i) {\n for (j = 0; j <= v7; ++j) {\n if (i && j) {\n if (i >= j) {\n if (j == 1)\n *(uint32_t *)&v13[4 * (v2 >> 2) * i + 4] = i;\n else\n *(uint32_t *)&v13[4 * j + 4 * (v2 >> 2) * i] =\n *(uint32_t *)&v13[4 * j - 4 + 4 * (v2 >> 2) * (i / 2)] +\n *(uint32_t *)&v13[4 * j + 4 * (v2 >> 2) * (i - 1)];\n } else {\n *(uint32_t *)&v13[4 * j + 4 * (v2 >> 2) * i] = 0;\n }\n } else {\n *(uint32_t *)&v13[4 * j + 4 * (v2 >> 2) * i] = 0;\n }\n }\n }\n return *(unsigned int *)&v13[4 * v7 + 4 * (v2 >> 2) * v8];\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n unsigned long long v2;\n unsigned long long v3;\n void *v4;\n uint8_t v6[8];\n int v7;\n int v8;\n int i;\n int j;\n long long v11;\n long long v12;\n uint8_t *v13;\n unsigned long long v14;\n v8 = a1;\n v7 = a2;\n v14 = __readfsqword(40u);\n v11 = a2 + 1 - 1LL;\n v2 = 4LL * (a2 + 1);\n v12 = a1 + 1 - 1LL;\n v3 = 16 * ((4 * (a2 + 1) * (long long)(a1 + 1) + 15) / 16uLL);\n while (v6 != &v6[-(v3 & 18446744073709547520LL)])\n ;\n v4 = alloca(v3 & 4095);\n if ((v3 & 4095) != 0)\n *(uint64_t *)&v6[(v3 & 4095) - 8] = *(uint64_t *)&v6[(v3 & 4095) - 8];\n v13 = v6;\n for (i = 0; i <= v8; ++i) {\n for (j = 0; j <= v7; ++j) {\n if (i && j) {\n if (i >= j) {\n if (j == 1)\n *(uint32_t *)&v13[4 * (v2 >> 2) * i + 4] = i;\n else\n *(uint32_t *)&v13[4 * j + 4 * (v2 >> 2) * i] =\n *(uint32_t *)&v13[4 * j - 4 + 4 * (v2 >> 2) * (i / 2)] +\n *(uint32_t *)&v13[4 * j + 4 * (v2 >> 2) * (i - 1)];\n } else {\n *(uint32_t *)&v13[4 * j + 4 * (v2 >> 2) * i] = 0;\n }\n } else {\n *(uint32_t *)&v13[4 * j + 4 * (v2 >> 2) * i] = 0;\n }\n }\n }\n return *(unsigned int *)&v13[4 * v7 + 4 * (v2 >> 2) * v8];\n}" + }, + { + "index": 239, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int m, int n) {\n int T[m + 1][n + 1];\n for (int i = 0; i <= m; i++) {\n for (int j = 0; j <= n; j++) {\n if (i == 0 || j == 0) {\n T[i][j] = 0;\n } else if (i < j) {\n T[i][j] = 0;\n } else if (j == 1) {\n T[i][j] = i;\n } else {\n T[i][j] = T[i - 1][j] + T[i / 2][j - 1];\n }\n }\n }\n return T[m][n];\n}", + "test": "int main() {\n\n assert(func0(10, 4) == 4);\n\n assert(func0(5, 2) == 6);\n\n assert(func0(16, 3) == 84);\n\n return 0;\n\n} \n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0x38,%rsp\nmov %edi,-0x48(%rbp)\nmov %esi,%r13d\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nlea 0x1(%rsi),%eax\nmovslq %eax,%rcx\nlea 0x0(,%rcx,4),%r11\nlea 0x1(%rdi),%edx\nmovslq %edx,%rax\nimul %rcx,%rax\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffffff0,%rdx\nand $0xfffffffffffff000,%rax\nmov %rsp,%rbx\nsub %rax,%rbx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 11e0 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11c9 \nmov %rdx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 11f6 \norq $0x0,-0x8(%rsp,%rax,1)\nmov %rsp,%rax\nmov %rax,-0x58(%rbp)\nmov %rax,%r14\nmov -0x48(%rbp),%esi\ntest %esi,%esi\njs 12b6 \nmov %rax,%r9\nlea 0x1(%rsi),%ebx\nmov %ebx,-0x44(%rbp)\nmov %r11,%rbx\nshr $0x2,%rbx\nmov %rbx,-0x50(%rbp)\nmov %r11,%r15\nneg %r15\nmov %rax,%rsi\nmov %rax,%rbx\nmov $0x0,%edx\nmov %r13d,%r8d\njmp 1287 \nmovl $0x0,(%r9,%rax,4)\nlea 0x1(%rax),%rcx\ncmp %rax,%r8\nje 1276 \nmov %rcx,%rax\ntest %edx,%edx\nje 1235 \ntest %eax,%eax\nje 1235 \ncmp %edx,%eax\njle 125e \nmovl $0x0,(%rbx,%rax,4)\njmp 123d \ncmp $0x1,%eax\nje 1270 \nmov -0x4(%rdi,%rax,4),%ecx\nadd (%r12,%rax,4),%ecx\nmov %ecx,(%rsi,%rax,4)\njmp 123d \nmov %edx,(%r14,%r10,4)\njmp 123d \nadd $0x1,%edx\nadd %r11,%r9\nadd %r11,%rbx\nadd %r11,%rsi\ncmp -0x44(%rbp),%edx\nje 12b6 \ntest %r13d,%r13d\njs 1276 \nlea (%rsi,%r15,1),%r12\nmov %edx,%edi\nshr $0x1f,%edi\nadd %edx,%edi\nsar %edi\nmovslq %edi,%rdi\nimul %r11,%rdi\nadd %r14,%rdi\nmov $0x0,%eax\nmovslq %edx,%r10\nimul -0x50(%rbp),%r10\nadd $0x1,%r10\njmp 1249 \nmovslq %r13d,%r13\nmovslq -0x48(%rbp),%rax\nshr $0x2,%r11\nimul %rax,%r11\nlea 0x0(%r13,%r11,1),%rax\nmov -0x58(%rbp),%rsi\nmov (%rsi,%rax,4),%eax\nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\njne 12ef \nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 38h\nmov ecx, edi\nmov r12d, esi\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nlea edx, [rsi+1]\nmovsxd rdx, edx\nlea r9, ds:0[rdx*4]\nlea eax, [rdi+1]\ncdqe\nimul rax, rdx\nlea rax, ds:0Fh[rax*4]\nmov rsi, rax\nand rsi, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11C4:\ncmp rsp, rdx\njz short loc_11DB\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\njmp short loc_11C4\nloc_11DB:\nmov rax, rsi\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11F1\nor [rsp+rax+60h+var_68], 0\nloc_11F1:\nmov r13, rsp\ntest ecx, ecx\njs loc_12B3\nmov r8, r13\nlea r14d, [rcx+1]\nmov rax, r9\nshr rax, 2\nmov [rbp+var_50], rax\nmov r15, r9\nneg r15\nmov r10, r13\nmov r11, r13\nmov edx, 0\nlea edi, [r12+1]\nmov [rbp+var_54], ecx\njmp short loc_1289\nloc_1229:\nmov dword ptr [r8+rax*4], 0\nloc_1231:\nadd rax, 1\ncmp rax, rdi\njz short loc_1274\nloc_123A:\ntest edx, edx\njz short loc_1229\ntest eax, eax\njz short loc_1229\ncmp eax, edx\njle short loc_1250\nmov dword ptr [r11+rax*4], 0\njmp short loc_1231\nloc_1250:\ncmp eax, 1\njz short loc_1262\nmov ecx, [rsi+rax*4-4]\nadd ecx, [rbx+rax*4]\nmov [r10+rax*4], ecx\njmp short loc_1231\nloc_1262:\nmovsxd rcx, edx\nmov r9, [rbp+var_50]\nimul rcx, r9\nmov [r13+rcx*4+4], edx\njmp short loc_1231\nloc_1274:\nmov r9, [rbp+var_48]\nloc_1278:\nadd edx, 1\nadd r8, r9\nadd r11, r9\nadd r10, r9\ncmp edx, r14d\njz short loc_12B0\nloc_1289:\ntest r12d, r12d\njs short loc_1278\nlea rbx, [r10+r15]\nmov esi, edx\nshr esi, 1Fh\nadd esi, edx\nsar esi, 1\nmovsxd rsi, esi\nimul rsi, r9\nadd rsi, r13\nmov eax, 0\nmov [rbp+var_48], r9\njmp short loc_123A\nloc_12B0:\nmov ecx, [rbp+var_54]\nloc_12B3:\nmovsxd rax, r12d\nmovsxd rcx, ecx\nshr r9, 2\nimul rcx, r9\nadd rax, rcx\nmov eax, [r13+rax*4+0]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_12E7\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_12E7:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n int v2; // ecx\n __int64 v4; // rdx\n unsigned __int64 v5; // r9\n __int16 v6; // si\n _BYTE *v7; // rdx\n signed __int64 v8; // rax\n void *v9; // rsp\n _BYTE *v10; // r8\n __int64 v11; // r15\n _BYTE *v12; // r10\n _BYTE *v13; // r11\n int v14; // edx\n __int64 v15; // rax\n _BYTE v18[12]; // [rsp+8h] [rbp-60h] BYREF\n int v19; // [rsp+14h] [rbp-54h]\n unsigned __int64 v20; // [rsp+18h] [rbp-50h]\n unsigned __int64 v21; // [rsp+20h] [rbp-48h]\n unsigned __int64 v22; // [rsp+30h] [rbp-38h]\n\n v2 = a1;\n v22 = __readfsqword(0x28u);\n v4 = a2 + 1;\n v5 = 4 * v4;\n v6 = (4 * (a2 + 1) * (a1 + 1) + 15) & 0xFFF0;\n v7 = &v18[-((4 * v4 * (a1 + 1) + 15) & 0xFFFFFFFFFFFFF000LL)];\n while ( v18 != v7 )\n ;\n v8 = v6 & 0xFFF;\n v9 = alloca(v8);\n if ( (v6 & 0xFFF) != 0 )\n *(_QWORD *)&v18[v8 - 8] = *(_QWORD *)&v18[v8 - 8];\n if ( a1 >= 0 )\n {\n v10 = v18;\n v20 = v5 >> 2;\n v11 = -(__int64)v5;\n v12 = v18;\n v13 = v18;\n v14 = 0;\n v19 = a1;\n do\n {\n if ( a2 >= 0 )\n {\n v15 = 0LL;\n v21 = v5;\n do\n {\n if ( v14 && (_DWORD)v15 )\n {\n if ( (int)v15 <= v14 )\n {\n if ( (_DWORD)v15 == 1 )\n *(_DWORD *)&v18[4 * v20 * v14 + 4] = v14;\n else\n *(_DWORD *)&v12[4 * v15] = *(_DWORD *)&v12[4 * v15 + v11]\n + *(_DWORD *)&v18[4 * v15 - 4 + v5 * (v14 / 2)];\n }\n else\n {\n *(_DWORD *)&v13[4 * v15] = 0;\n }\n }\n else\n {\n *(_DWORD *)&v10[4 * v15] = 0;\n }\n ++v15;\n }\n while ( v15 != a2 + 1 );\n v5 = v21;\n }\n ++v14;\n v10 += v5;\n v13 += v5;\n v12 += v5;\n }\n while ( v14 != a1 + 1 );\n v2 = v19;\n }\n return *(unsigned int *)&v18[4 * (v5 >> 2) * v2 + 4 * a2];\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 38h\nmov ecx, edi\nmov r12d, esi\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nlea edx, [rsi+1]\nmovsxd rdx, edx\nlea r9, ds:0[rdx*4]\nlea eax, [rdi+1]\ncdqe\nimul rax, rdx\nlea rax, ds:0Fh[rax*4]\nmov rsi, rax\nand rsi, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11C4:\ncmp rsp, rdx\njz short loc_11DB\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\njmp short loc_11C4\nloc_11DB:\nmov rax, rsi\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11F1\nor [rsp+rax+60h+var_68], 0\nloc_11F1:\nmov r13, rsp\ntest ecx, ecx\njs loc_12B3\nmov r8, r13\nlea r14d, [rcx+1]\nmov rax, r9\nshr rax, 2\nmov [rbp+var_50], rax\nmov r15, r9\nneg r15\nmov r10, r13\nmov r11, r13\nmov edx, 0\nlea edi, [r12+1]\nmov [rbp+var_54], ecx\njmp short loc_1289\nloc_1229:\nmov dword ptr [r8+rax*4], 0\nloc_1231:\nadd rax, 1\ncmp rax, rdi\njz short loc_1274\nloc_123A:\ntest edx, edx\njz short loc_1229\ntest eax, eax\njz short loc_1229\ncmp eax, edx\njle short loc_1250\nmov dword ptr [r11+rax*4], 0\njmp short loc_1231\nloc_1250:\ncmp eax, 1\njz short loc_1262\nmov ecx, [rsi+rax*4-4]\nadd ecx, [rbx+rax*4]\nmov [r10+rax*4], ecx\njmp short loc_1231\nloc_1262:\nmovsxd rcx, edx\nmov r9, [rbp+var_50]\nimul rcx, r9\nmov [r13+rcx*4+4], edx\njmp short loc_1231\nloc_1274:\nmov r9, [rbp+var_48]\nloc_1278:\nadd edx, 1\nadd r8, r9\nadd r11, r9\nadd r10, r9\ncmp edx, r14d\njz short loc_12B0\nloc_1289:\ntest r12d, r12d\njs short loc_1278\nlea rbx, [r10+r15]\nmov esi, edx\nshr esi, 1Fh\nadd esi, edx\nsar esi, 1\nmovsxd rsi, esi\nimul rsi, r9\nadd rsi, r13\nmov eax, 0\nmov [rbp+var_48], r9\njmp short loc_123A\nloc_12B0:\nmov ecx, [rbp+var_54]\nloc_12B3:\nmovsxd rax, r12d\nmovsxd rcx, ecx\nshr r9, 2\nimul rcx, r9\nadd rax, rcx\nmov eax, [r13+rax*4+0]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_12E7\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_12E7:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1, int a2)\n{\n int v2; // ecx\n __int64 v4; // rdx\n unsigned __int64 v5; // r9\n __int16 v6; // si\n _BYTE *v7; // rdx\n signed __int64 v8; // rax\n void *v9; // rsp\n _BYTE *v10; // r8\n __int64 v11; // r15\n _BYTE *v12; // r10\n _BYTE *v13; // r11\n int v14; // edx\n __int64 v15; // rax\n _BYTE v18[12]; // [rsp+8h] [rbp-60h] BYREF\n int v19; // [rsp+14h] [rbp-54h]\n unsigned __int64 v20; // [rsp+18h] [rbp-50h]\n unsigned __int64 v21; // [rsp+20h] [rbp-48h]\n unsigned __int64 v22; // [rsp+30h] [rbp-38h]\n\n v2 = a1;\n v22 = __readfsqword(0x28u);\n v4 = a2 + 1;\n v5 = 4 * v4;\n v6 = (4 * (a2 + 1) * (a1 + 1) + 15) & 0xFFF0;\n v7 = &v18[-((4 * v4 * (a1 + 1) + 15) & 0xFFFFFFFFFFFFF000LL)];\n while ( v18 != v7 )\n ;\n v8 = v6 & 0xFFF;\n v9 = alloca(v8);\n if ( (v6 & 0xFFF) != 0 )\n *(_QWORD *)&v18[v8 - 8] = *(_QWORD *)&v18[v8 - 8];\n if ( a1 >= 0 )\n {\n v10 = v18;\n v20 = v5 >> 2;\n v11 = -(__int64)v5;\n v12 = v18;\n v13 = v18;\n v14 = 0;\n v19 = a1;\n do\n {\n if ( a2 >= 0 )\n {\n v15 = 0LL;\n v21 = v5;\n do\n {\n if ( v14 && (_DWORD)v15 )\n {\n if ( (int)v15 <= v14 )\n {\n if ( (_DWORD)v15 == 1 )\n *(_DWORD *)&v18[4 * v20 * v14 + 4] = v14;\n else\n *(_DWORD *)&v12[4 * v15] = *(_DWORD *)&v12[4 * v15 + v11]\n + *(_DWORD *)&v18[4 * v15 - 4 + v5 * (v14 / 2)];\n }\n else\n {\n *(_DWORD *)&v13[4 * v15] = 0;\n }\n }\n else\n {\n *(_DWORD *)&v10[4 * v15] = 0;\n }\n ++v15;\n }\n while ( v15 != a2 + 1 );\n v5 = v21;\n }\n ++v14;\n v10 += v5;\n v13 += v5;\n v12 += v5;\n }\n while ( v14 != a1 + 1 );\n v2 = v19;\n }\n return *(unsigned int *)&v18[4 * (v5 >> 2) * v2 + 4 * a2];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1, int a2) {\n int v2;\n long long v4;\n unsigned long long v5;\n short v6;\n uint8_t *v7;\n signed long long v8;\n void *v9;\n uint8_t *v10;\n long long v11;\n uint8_t *v12;\n uint8_t *v13;\n int v14;\n long long v15;\n uint8_t v18[12];\n int v19;\n unsigned long long v20;\n unsigned long long v21;\n unsigned long long v22;\n v2 = a1;\n v22 = __readfsqword(40u);\n v4 = a2 + 1;\n v5 = 4 * v4;\n v6 = (4 * (a2 + 1) * (a1 + 1) + 15) & 65520;\n v7 = &v18[-((4 * v4 * (a1 + 1) + 15) & 18446744073709547520LL)];\n while (v18 != v7)\n ;\n v8 = v6 & 4095;\n v9 = alloca(v8);\n if ((v6 & 4095) != 0) *(uint64_t *)&v18[v8 - 8] = *(uint64_t *)&v18[v8 - 8];\n if (a1 >= 0) {\n v10 = v18;\n v20 = v5 >> 2;\n v11 = -(long long)v5;\n v12 = v18;\n v13 = v18;\n v14 = 0;\n v19 = a1;\n do {\n if (a2 >= 0) {\n v15 = 0LL;\n v21 = v5;\n do {\n if (v14 && (uint32_t)v15) {\n if ((int)v15 <= v14) {\n if ((uint32_t)v15 == 1)\n *(uint32_t *)&v18[4 * v20 * v14 + 4] = v14;\n else\n *(uint32_t *)&v12[4 * v15] =\n *(uint32_t *)&v12[4 * v15 + v11] +\n *(uint32_t *)&v18[4 * v15 - 4 + v5 * (v14 / 2)];\n } else {\n *(uint32_t *)&v13[4 * v15] = 0;\n }\n } else {\n *(uint32_t *)&v10[4 * v15] = 0;\n }\n ++v15;\n } while (v15 != a2 + 1);\n v5 = v21;\n }\n ++v14;\n v10 += v5;\n v13 += v5;\n v12 += v5;\n } while (v14 != a1 + 1);\n v2 = v19;\n }\n return *(unsigned int *)&v18[4 * (v5 >> 2) * v2 + 4 * a2];\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n int v2;\n long long v4;\n unsigned long long v5;\n short v6;\n uint8_t *v7;\n signed long long v8;\n void *v9;\n uint8_t *v10;\n long long v11;\n uint8_t *v12;\n uint8_t *v13;\n int v14;\n long long v15;\n uint8_t v18[12];\n int v19;\n unsigned long long v20;\n unsigned long long v21;\n unsigned long long v22;\n v2 = a1;\n v22 = __readfsqword(40u);\n v4 = a2 + 1;\n v5 = 4 * v4;\n v6 = (4 * (a2 + 1) * (a1 + 1) + 15) & 65520;\n v7 = &v18[-((4 * v4 * (a1 + 1) + 15) & 18446744073709547520LL)];\n while (v18 != v7)\n ;\n v8 = v6 & 4095;\n v9 = alloca(v8);\n if ((v6 & 4095) != 0) *(uint64_t *)&v18[v8 - 8] = *(uint64_t *)&v18[v8 - 8];\n if (a1 >= 0) {\n v10 = v18;\n v20 = v5 >> 2;\n v11 = -(long long)v5;\n v12 = v18;\n v13 = v18;\n v14 = 0;\n v19 = a1;\n do {\n if (a2 >= 0) {\n v15 = 0LL;\n v21 = v5;\n do {\n if (v14 && (uint32_t)v15) {\n if ((int)v15 <= v14) {\n if ((uint32_t)v15 == 1)\n *(uint32_t *)&v18[4 * v20 * v14 + 4] = v14;\n else\n *(uint32_t *)&v12[4 * v15] =\n *(uint32_t *)&v12[4 * v15 + v11] +\n *(uint32_t *)&v18[4 * v15 - 4 + v5 * (v14 / 2)];\n } else {\n *(uint32_t *)&v13[4 * v15] = 0;\n }\n } else {\n *(uint32_t *)&v10[4 * v15] = 0;\n }\n ++v15;\n } while (v15 != a2 + 1);\n v5 = v21;\n }\n ++v14;\n v10 += v5;\n v13 += v5;\n v12 += v5;\n } while (v14 != a1 + 1);\n v2 = v19;\n }\n return *(unsigned int *)&v18[4 * (v5 >> 2) * v2 + 4 * a2];\n}" + }, + { + "index": 239, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int m, int n) {\n int T[m + 1][n + 1];\n for (int i = 0; i <= m; i++) {\n for (int j = 0; j <= n; j++) {\n if (i == 0 || j == 0) {\n T[i][j] = 0;\n } else if (i < j) {\n T[i][j] = 0;\n } else if (j == 1) {\n T[i][j] = i;\n } else {\n T[i][j] = T[i - 1][j] + T[i / 2][j - 1];\n }\n }\n }\n return T[m][n];\n}", + "test": "int main() {\n\n assert(func0(10, 4) == 4);\n\n assert(func0(5, 2) == 6);\n\n assert(func0(16, 3) == 84);\n\n return 0;\n\n} \n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nlea 0x1(%rsi),%ecx\nlea 0x1(%rdi),%edx\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\nmov %esi,%r13d\nmovslq %ecx,%rsi\npush %r12\npush %rbx\nsub $0x38,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nlea 0x0(,%rsi,4),%rax\nmov %rsp,%rbx\nmov %rax,-0x50(%rbp)\nmovslq %edx,%rax\nimul %rsi,%rax\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rbx\nand $0xfffffffffffffff0,%rdx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 129b \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 1286 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 13b0 \nmov -0x50(%rbp),%r14\nmov %rsp,-0x58(%rbp)\nshr $0x2,%r14\ntest %edi,%edi\njs 1372 \nmovslq %edi,%rax\nmov %r14,%r15\nmov -0x58(%rbp),%rbx\nxor %r8d,%r8d\nmov %rax,-0x48(%rbp)\nneg %r15\nnopl (%rax)\nmov %r8d,%r12d\ntest %r13d,%r13d\njs 134b \ntest %r8d,%r8d\nmov %r8d,%esi\nmovslq %r12d,%r11\nmov %r8d,%r10d\nsete %dil\nimul %r14,%r11\nsar %esi\nmov %rbx,%rdx\nmovslq %esi,%rsi\nxor %eax,%eax\nsub %r8,%rsi\nimul %r14,%rsi\nadd $0x1,%r11\njmp 1331 \nnopl 0x0(%rax,%rax,1)\ncmp %r10d,%eax\njg 133a \ncmp $0x1,%eax\nje 1368 \nmov -0x4(%rdx,%rsi,4),%r9d\nadd (%rdx,%r15,4),%r9d\nmov %r9d,(%rdx)\nadd $0x1,%eax\nadd $0x4,%rdx\ncmp %eax,%ecx\nje 134b \ntest %eax,%eax\nje 133a \ntest %dil,%dil\nje 1310 \nadd $0x1,%eax\nmovl $0x0,(%rdx)\nadd $0x4,%rdx\ncmp %eax,%ecx\njne 1331 \nlea 0x1(%r8),%rax\nadd -0x50(%rbp),%rbx\ncmp -0x48(%rbp),%r8\nje 1380 \nmov %rax,%r8\njmpq 12d8 \nnopl 0x0(%rax)\nmov -0x58(%rbp),%r9\nmov %r12d,(%r9,%r11,4)\njmp 1326 \nmovslq %edi,%rax\nmov %rax,-0x48(%rbp)\nnopl 0x0(%rax)\nimul -0x48(%rbp),%r14\nmov -0x58(%rbp),%rbx\nmovslq %r13d,%rax\nadd %r14,%rax\nmov (%rbx,%rax,4),%eax\nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\njne 13bb \nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 12ad \ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nlea edx, [rsi+1]\nmovsxd rdx, edx\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\nmovsxd r12, edi\npush rbx\nsub rsp, 28h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nlea rax, ds:0[rdx*4]\nmov rcx, rsp\nmov [rbp+var_48], rax\nlea eax, [r12+1]\ncdqe\nimul rax, rdx\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_1299\nloc_1284:\nsub rsp, 1000h\nor [rsp+1050h+var_58], 0\ncmp rsp, rcx\njnz short loc_1284\nloc_1299:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_139F\nloc_12AB:\nmov r15, [rbp+var_48]\nmov [rbp+var_50], rsp\nshr r15, 2\nmov r14, r15\ntest r12d, r12d\njs loc_1370\nmov r11, [rbp+var_50]\ntest esi, esi\njs loc_1370\nmov r13, r15\nxor r9d, r9d\nxor ebx, ebx\nneg r13\nnop word ptr [rax+rax+00h]\nloc_12E0:\ntest r9d, r9d\nmov edi, ebx\nmov r10d, r9d\nmov rdx, r11\nsetz r8b\nsar edi, 1\nxor eax, eax\nmovsxd rdi, edi\nsub rdi, r9\nimul rdi, r14\njmp short loc_1321\nloc_1300:\ncmp eax, r10d\njg short loc_132A\ncmp eax, 1\njz short loc_1358\nmov ecx, [rdx+rdi*4-4]\nadd ecx, [rdx+r13*4]\nmov [rdx], ecx\nloc_1314:\nlea ecx, [rax+1]\nadd rdx, 4\ncmp esi, eax\njz short loc_133B\nloc_131F:\nmov eax, ecx\nloc_1321:\ntest eax, eax\njz short loc_132A\ntest r8b, r8b\njz short loc_1300\nloc_132A:\nmov dword ptr [rdx], 0\nlea ecx, [rax+1]\nadd rdx, 4\ncmp esi, eax\njnz short loc_131F\nloc_133B:\nmov rbx, [rbp+var_48]\nlea rax, [r9+1]\nadd r11, rbx\ncmp r9, r12\njz short loc_1370\nmov ebx, eax\nmov r9, rax\njmp short loc_12E0\nloc_1358:\nmovsxd rcx, ebx\nmov r15, [rbp+var_50]\nimul rcx, r14\nmov [r15+rcx*4+4], ebx\njmp short loc_1314\nloc_1370:\nimul r12, r14\nmov rbx, [rbp+var_50]\nmovsxd rax, esi\nadd rax, r12\nmov eax, [rbx+rax*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_13AA\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_139F:\nor [rsp+rdx+1050h+var_1058], 0\njmp loc_12AB\nloc_13AA:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n __int64 v2; // rdx\n __int64 v3; // rdx\n _BYTE *v4; // rcx\n __int16 v5; // dx\n signed __int64 v6; // rdx\n void *v7; // rsp\n unsigned __int64 v8; // r15\n unsigned __int64 v9; // r14\n _DWORD *v10; // r11\n __int64 v11; // r9\n int v12; // ebx\n _DWORD *v13; // rdx\n int i; // eax\n int v15; // ecx\n _BYTE v18[4088]; // [rsp+8h] [rbp-1050h] BYREF\n _BYTE *v19; // [rsp+1008h] [rbp-50h] BYREF\n unsigned __int64 v20; // [rsp+1010h] [rbp-48h]\n unsigned __int64 v21; // [rsp+1020h] [rbp-38h]\n\n v2 = a2 + 1;\n v21 = __readfsqword(0x28u);\n v20 = 4 * v2;\n v3 = 4 * v2 * (a1 + 1) + 15;\n v4 = (char *)&v19 - (v3 & 0xFFFFFFFFFFFFF000LL);\n v5 = v3 & 0xFFF0;\n if ( &v19 != (_BYTE **)v4 )\n {\n while ( v18 != v4 )\n ;\n }\n v6 = v5 & 0xFFF;\n v7 = alloca(v6);\n if ( v6 )\n *(_QWORD *)&v18[v6 - 8] = *(_QWORD *)&v18[v6 - 8];\n v19 = v18;\n v8 = v20 >> 2;\n v9 = v20 >> 2;\n if ( a1 < 0 )\n return *(unsigned int *)&v19[4 * v9 * a1 + 4 * a2];\n v10 = v19;\n if ( a2 < 0 )\n return *(unsigned int *)&v19[4 * v9 * a1 + 4 * a2];\n v11 = 0LL;\n v12 = 0;\n while ( 2 )\n {\n v13 = v10;\n for ( i = 0; !i || !(_DWORD)v11 || i > (int)v11; i = v15 )\n {\n *v13 = 0;\n v15 = i + 1;\n ++v13;\n if ( a2 == i )\n goto LABEL_17;\nLABEL_13:\n ;\n }\n if ( i == 1 )\n *(_DWORD *)&v19[4 * v9 * v12 + 4] = v12;\n else\n *v13 = v13[-v8] + v13[v9 * ((v12 >> 1) - v11) - 1];\n v15 = i + 1;\n ++v13;\n if ( a2 != i )\n goto LABEL_13;\nLABEL_17:\n v10 = (_DWORD *)((char *)v10 + v20);\n if ( v11 != a1 )\n {\n v12 = ++v11;\n continue;\n }\n return *(unsigned int *)&v19[4 * v9 * a1 + 4 * a2];\n }\n}", + "ida_strip_asm": "sub_1220:\nendbr64\npush rbp\nlea edx, [rsi+1]\nmovsxd rdx, edx\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\nmovsxd r12, edi\npush rbx\nsub rsp, 28h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nlea rax, ds:0[rdx*4]\nmov rcx, rsp\nmov [rbp+var_48], rax\nlea eax, [r12+1]\ncdqe\nimul rax, rdx\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_1299\nloc_1284:\nsub rsp, 1000h\nor [rsp+1050h+var_58], 0\ncmp rsp, rcx\njnz short loc_1284\nloc_1299:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_139F\nloc_12AB:\nmov r15, [rbp+var_48]\nmov [rbp+var_50], rsp\nshr r15, 2\nmov r14, r15\ntest r12d, r12d\njs loc_1370\nmov r11, [rbp+var_50]\ntest esi, esi\njs loc_1370\nmov r13, r15\nxor r9d, r9d\nxor ebx, ebx\nneg r13\nnop word ptr [rax+rax+00h]\nloc_12E0:\ntest r9d, r9d\nmov edi, ebx\nmov r10d, r9d\nmov rdx, r11\nsetz r8b\nsar edi, 1\nxor eax, eax\nmovsxd rdi, edi\nsub rdi, r9\nimul rdi, r14\njmp short loc_1321\nloc_1300:\ncmp eax, r10d\njg short loc_132A\ncmp eax, 1\njz short loc_1358\nmov ecx, [rdx+rdi*4-4]\nadd ecx, [rdx+r13*4]\nmov [rdx], ecx\nloc_1314:\nlea ecx, [rax+1]\nadd rdx, 4\ncmp esi, eax\njz short loc_133B\nloc_131F:\nmov eax, ecx\nloc_1321:\ntest eax, eax\njz short loc_132A\ntest r8b, r8b\njz short loc_1300\nloc_132A:\nmov dword ptr [rdx], 0\nlea ecx, [rax+1]\nadd rdx, 4\ncmp esi, eax\njnz short loc_131F\nloc_133B:\nmov rbx, [rbp+var_48]\nlea rax, [r9+1]\nadd r11, rbx\ncmp r9, r12\njz short loc_1370\nmov ebx, eax\nmov r9, rax\njmp short loc_12E0\nloc_1358:\nmovsxd rcx, ebx\nmov r15, [rbp+var_50]\nimul rcx, r14\nmov [r15+rcx*4+4], ebx\njmp short loc_1314\nloc_1370:\nimul r12, r14\nmov rbx, [rbp+var_50]\nmovsxd rax, esi\nadd rax, r12\nmov eax, [rbx+rax*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_13AA\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_139F:\nor [rsp+rdx+1050h+var_1058], 0\njmp loc_12AB\nloc_13AA:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1220(int a1, int a2)\n{\n __int64 v2; // rdx\n __int64 v3; // rdx\n _BYTE *v4; // rcx\n __int16 v5; // dx\n signed __int64 v6; // rdx\n void *v7; // rsp\n unsigned __int64 v8; // r15\n unsigned __int64 v9; // r14\n _DWORD *v10; // r11\n __int64 v11; // r9\n int v12; // ebx\n _DWORD *v13; // rdx\n int i; // eax\n int v15; // ecx\n _BYTE v18[4088]; // [rsp+8h] [rbp-1050h] BYREF\n _BYTE *v19; // [rsp+1008h] [rbp-50h] BYREF\n unsigned __int64 v20; // [rsp+1010h] [rbp-48h]\n unsigned __int64 v21; // [rsp+1020h] [rbp-38h]\n\n v2 = a2 + 1;\n v21 = __readfsqword(0x28u);\n v20 = 4 * v2;\n v3 = 4 * v2 * (a1 + 1) + 15;\n v4 = (char *)&v19 - (v3 & 0xFFFFFFFFFFFFF000LL);\n v5 = v3 & 0xFFF0;\n if ( &v19 != (_BYTE **)v4 )\n {\n while ( v18 != v4 )\n ;\n }\n v6 = v5 & 0xFFF;\n v7 = alloca(v6);\n if ( v6 )\n *(_QWORD *)&v18[v6 - 8] = *(_QWORD *)&v18[v6 - 8];\n v19 = v18;\n v8 = v20 >> 2;\n v9 = v20 >> 2;\n if ( a1 < 0 )\n return *(unsigned int *)&v19[4 * v9 * a1 + 4 * a2];\n v10 = v19;\n if ( a2 < 0 )\n return *(unsigned int *)&v19[4 * v9 * a1 + 4 * a2];\n v11 = 0LL;\n v12 = 0;\n while ( 2 )\n {\n v13 = v10;\n for ( i = 0; !i || !(_DWORD)v11 || i > (int)v11; i = v15 )\n {\n *v13 = 0;\n v15 = i + 1;\n ++v13;\n if ( a2 == i )\n goto LABEL_17;\nLABEL_13:\n ;\n }\n if ( i == 1 )\n *(_DWORD *)&v19[4 * v9 * v12 + 4] = v12;\n else\n *v13 = v13[-v8] + v13[v9 * ((v12 >> 1) - v11) - 1];\n v15 = i + 1;\n ++v13;\n if ( a2 != i )\n goto LABEL_13;\nLABEL_17:\n v10 = (_DWORD *)((char *)v10 + v20);\n if ( v11 != a1 )\n {\n v12 = ++v11;\n continue;\n }\n return *(unsigned int *)&v19[4 * v9 * a1 + 4 * a2];\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1220(int a1, int a2) {\n long long v2;\n long long v3;\n uint8_t *v4;\n short v5;\n signed long long v6;\n void *v7;\n unsigned long long v8;\n unsigned long long v9;\n uint32_t *v10;\n long long v11;\n int v12;\n uint32_t *v13;\n int i;\n int v15;\n uint8_t v18[4088];\n uint8_t *v19;\n unsigned long long v20;\n unsigned long long v21;\n v2 = a2 + 1;\n v21 = __readfsqword(40u);\n v20 = 4 * v2;\n v3 = 4 * v2 * (a1 + 1) + 15;\n v4 = (char *)&v19 - (v3 & 18446744073709547520LL);\n v5 = v3 & 65520;\n if (&v19 != (uint8_t **)v4) {\n while (v18 != v4)\n ;\n }\n v6 = v5 & 4095;\n v7 = alloca(v6);\n if (v6) *(uint64_t *)&v18[v6 - 8] = *(uint64_t *)&v18[v6 - 8];\n v19 = v18;\n v8 = v20 >> 2;\n v9 = v20 >> 2;\n if (a1 < 0) return *(unsigned int *)&v19[4 * v9 * a1 + 4 * a2];\n v10 = v19;\n if (a2 < 0) return *(unsigned int *)&v19[4 * v9 * a1 + 4 * a2];\n v11 = 0LL;\n v12 = 0;\n while (2) {\n v13 = v10;\n for (i = 0; !i || !(uint32_t)v11 || i > (int)v11; i = v15) {\n *v13 = 0;\n v15 = i + 1;\n ++v13;\n if (a2 == i) goto LABEL_17;\n LABEL_13:;\n }\n if (i == 1)\n *(uint32_t *)&v19[4 * v9 * v12 + 4] = v12;\n else\n *v13 = v13[-v8] + v13[v9 * ((v12 >> 1) - v11) - 1];\n v15 = i + 1;\n ++v13;\n if (a2 != i) goto LABEL_13;\n LABEL_17:\n v10 = (uint32_t *)((char *)v10 + v20);\n if (v11 != a1) {\n v12 = ++v11;\n continue;\n }\n return *(unsigned int *)&v19[4 * v9 * a1 + 4 * a2];\n }\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n long long v2;\n long long v3;\n uint8_t *v4;\n short v5;\n signed long long v6;\n void *v7;\n unsigned long long v8;\n unsigned long long v9;\n uint32_t *v10;\n long long v11;\n int v12;\n uint32_t *v13;\n int i;\n int v15;\n uint8_t v18[4088];\n uint8_t *v19;\n unsigned long long v20;\n unsigned long long v21;\n v2 = a2 + 1;\n v21 = __readfsqword(40u);\n v20 = 4 * v2;\n v3 = 4 * v2 * (a1 + 1) + 15;\n v4 = (char *)&v19 - (v3 & 18446744073709547520LL);\n v5 = v3 & 65520;\n if (&v19 != (uint8_t **)v4) {\n while (v18 != v4)\n ;\n }\n v6 = v5 & 4095;\n v7 = alloca(v6);\n if (v6) *(uint64_t *)&v18[v6 - 8] = *(uint64_t *)&v18[v6 - 8];\n v19 = v18;\n v8 = v20 >> 2;\n v9 = v20 >> 2;\n if (a1 < 0) return *(unsigned int *)&v19[4 * v9 * a1 + 4 * a2];\n v10 = v19;\n if (a2 < 0) return *(unsigned int *)&v19[4 * v9 * a1 + 4 * a2];\n v11 = 0LL;\n v12 = 0;\n while (2) {\n v13 = v10;\n for (i = 0; !i || !(uint32_t)v11 || i > (int)v11; i = v15) {\n *v13 = 0;\n v15 = i + 1;\n ++v13;\n if (a2 == i) goto LABEL_17;\n LABEL_13:;\n }\n if (i == 1)\n *(uint32_t *)&v19[4 * v9 * v12 + 4] = v12;\n else\n *v13 = v13[-v8] + v13[v9 * ((v12 >> 1) - v11) - 1];\n v15 = i + 1;\n ++v13;\n if (a2 != i) goto LABEL_13;\n LABEL_17:\n v10 = (uint32_t *)((char *)v10 + v20);\n if (v11 != a1) {\n v12 = ++v11;\n continue;\n }\n return *(unsigned int *)&v19[4 * v9 * a1 + 4 * a2];\n }\n}" + }, + { + "index": 239, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int m, int n) {\n int T[m + 1][n + 1];\n for (int i = 0; i <= m; i++) {\n for (int j = 0; j <= n; j++) {\n if (i == 0 || j == 0) {\n T[i][j] = 0;\n } else if (i < j) {\n T[i][j] = 0;\n } else if (j == 1) {\n T[i][j] = i;\n } else {\n T[i][j] = T[i - 1][j] + T[i / 2][j - 1];\n }\n }\n }\n return T[m][n];\n}", + "test": "int main() {\n\n assert(func0(10, 4) == 4);\n\n assert(func0(5, 2) == 6);\n\n assert(func0(16, 3) == 84);\n\n return 0;\n\n} \n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nlea 0x1(%rsi),%edx\nmovslq %edx,%rdx\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0x28,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nlea 0x1(%rdi),%eax\nmov %rsp,%rbx\ncltq\nimul %rdx,%rax\nlea 0xf(,%rax,4),%rax\nmov %rax,%rcx\nand $0xfffffffffffff000,%rax\nsub %rax,%rbx\nand $0xfffffffffffffff0,%rcx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 128b \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 1276 \nand $0xfff,%ecx\nsub %rcx,%rsp\ntest %rcx,%rcx\njne 147e \nlea 0x0(,%rdx,4),%r12\nmovslq %edi,%rax\nmov %rsp,%r13\nmov %rax,-0x50(%rbp)\nshr $0x2,%r12\ntest %edi,%edi\njs 1439 \ntest %esi,%esi\njs 1439 \nmov %r12,%r15\nxor %r14d,%r14d\npxor %xmm0,%xmm0\nxor %edi,%edi\nneg %r15\nnopw 0x0(%rax,%rax,1)\ntest %edi,%edi\nmovslq %edi,%r11\nmov %edi,%ecx\nmov %edi,%r8d\nsete %r9b\nmovslq %r11d,%r10\ncmp %edi,%esi\nmov %edi,%ebx\ncmovle %esi,%ecx\nimul %r12,%r10\nsar %r8d\nlea 0x0(%r13,%r14,4),%rdx\nmovslq %r8d,%r8\nxor %eax,%eax\nsub %rdi,%r8\nadd $0x1,%r10\nimul %r12,%r8\nmov %r10,-0x48(%rbp)\njmp 1338 \nnopw 0x0(%rax,%rax,1)\ncmp $0x1,%eax\nje 1470 \nmov -0x4(%rdx,%r8,4),%r10d\nadd (%rdx,%r15,4),%r10d\nmov %r10d,(%rdx)\nadd $0x1,%eax\nadd $0x4,%rdx\ncmp %ecx,%eax\njg 1352 \ntest %eax,%eax\nje 1341 \ntest %r9b,%r9b\nje 1318 \nadd $0x1,%eax\nmovl $0x0,(%rdx)\nadd $0x4,%rdx\ncmp %ecx,%eax\njle 1338 \ncmp %eax,%esi\njl 13e8 \nmov %esi,%edx\nsub %eax,%edx\nlea 0x1(%rdx),%r8d\ncmp $0x2,%edx\njbe 1399 \nmovslq %eax,%rdx\nmov %r8d,%ecx\nadd %r14,%rdx\nshr $0x2,%ecx\nlea 0x0(%r13,%rdx,4),%rdx\nshl $0x4,%rcx\nadd %rdx,%rcx\nmovups %xmm0,(%rdx)\nadd $0x10,%rdx\ncmp %rcx,%rdx\njne 1380 \nmov %r8d,%edx\nand $0xfffffffc,%edx\nadd %edx,%eax\ncmp %edx,%r8d\nje 13e8 \nmov %r11,%rcx\nmovslq %eax,%rdx\nimul %r12,%rcx\nadd %rcx,%rdx\nmovl $0x0,0x0(%r13,%rdx,4)\nlea 0x1(%rax),%edx\ntest %eax,%eax\nje 1400 \ntest %r9b,%r9b\njne 1400 \ncmp %edx,%esi\njl 13e8 \nimul %r12,%r11\nmovslq %edx,%rax\nadd $0x1,%edx\nadd %r11,%rax\nmovl $0x0,0x0(%r13,%rax,4)\ncmp %edx,%esi\njl 13e8 \nmovslq %edx,%rdx\nadd %r11,%rdx\nmovl $0x0,0x0(%r13,%rdx,4)\nlea 0x1(%rdi),%rax\nadd %r12,%r14\ncmp -0x50(%rbp),%rdi\nje 1439 \nmov %rax,%rdi\njmpq 12d8 \nnopl (%rax)\ncmp %edx,%esi\njl 13e8 \ntest %ebx,%ebx\njne 13bf \nmovslq %edx,%rdx\nadd $0x2,%eax\nadd %rcx,%rdx\nmovl $0x0,0x0(%r13,%rdx,4)\ncmp %eax,%esi\njl 13e8 \ncltq\nadd %r12,%r14\nadd %rcx,%rax\nmovl $0x0,0x0(%r13,%rax,4)\nlea 0x1(%rdi),%rax\ncmp -0x50(%rbp),%rdi\njne 13f5 \nimul -0x50(%rbp),%r12\nmovslq %esi,%rax\nadd %r12,%rax\nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\nmov 0x0(%r13,%rax,4),%eax\njne 1489 \nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\nnopw 0x0(%rax,%rax,1)\nmov -0x48(%rbp),%r10\nmov %r11d,0x0(%r13,%r10,4)\njmpq 132d \norq $0x0,-0x8(%rsp,%rcx,1)\njmpq 129d \ncallq 1060 <__stack_chk_fail@plt>\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\nlea edx, [rsi+1]\nmov ecx, esi\nmovsxd rdx, edx\nmov rbp, rsp\npush r15\npush r14\nlea r14, ds:0[rdx*4]\npush r13\npush r12\npush rbx\nmovsxd rbx, edi\nsub rsp, 28h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nlea eax, [rbx+1]\nmov rsi, rsp\ncdqe\nimul rax, rdx\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rsi, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rsi\njz short loc_1295\nloc_1280:\nsub rsp, 1000h\nor [rsp+1050h+var_58], 0\ncmp rsp, rsi\njnz short loc_1280\nloc_1295:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_13A7\nloc_12A7:\nmov r12, r14\nmov [rbp+var_50], rsp\nshr r12, 2\ntest ebx, ebx\njs loc_1378\ntest ecx, ecx\njs loc_1378\nmov r15, r12\nmov r10, rsp\nxor edi, edi\nneg r15\nmov [rbp+var_48], r15\nnop dword ptr [rax+00000000h]\nloc_12D8:\ntest edi, edi\nmov esi, edi\nmov r8d, edi\nmov r13d, edi\nsetz r9b\ncmp ecx, edi\nmov rdx, r10\ncmovle esi, ecx\nsar r8d, 1\nxor eax, eax\nmovsxd r8, r8d\nsub r8, rdi\nimul r8, r12\nloc_12FD:\ntest eax, eax\njz short loc_1358\ntest r9b, r9b\njnz short loc_1358\ncmp eax, 1\njz short loc_1360\nmov r15, [rbp+var_48]\nmov r11d, [rdx+r8*4-4]\nadd r11d, [rdx+r15*4]\nmov [rdx], r11d\nloc_131B:\nadd eax, 1\nadd rdx, 4\ncmp eax, esi\njle short loc_12FD\nmovsxd rdx, eax\ncmp ecx, eax\njl short loc_1340\nnop dword ptr [rax]\nloc_1330:\nmov dword ptr [r10+rdx*4], 0\nadd rdx, 1\ncmp ecx, edx\njge short loc_1330\nloc_1340:\nlea rax, [rdi+1]\nadd r10, r14\ncmp rdi, rbx\njz short loc_1378\nmov rdi, rax\njmp short loc_12D8\nloc_1358:\nmov dword ptr [rdx], 0\njmp short loc_131B\nloc_1360:\nmovsxd r11, r13d\nmov r15, [rbp+var_50]\nimul r11, r12\nmov [r15+r11*4+4], r13d\njmp short loc_131B\nloc_1378:\nimul rbx, r12\nmovsxd rax, ecx\nadd rax, rbx\nmov rbx, [rbp+var_50]\nmov eax, [rbx+rax*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_13B2\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_13A7:\nor [rsp+rdx+1050h+var_1058], 0\njmp loc_12A7\nloc_13B2:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n __int64 v3; // rdx\n unsigned __int64 v4; // r14\n __int64 v5; // rbx\n __int64 v6; // rdx\n _BYTE *v7; // rsi\n __int16 v8; // dx\n signed __int64 v9; // rdx\n void *v10; // rsp\n unsigned __int64 v11; // r12\n _BYTE *v12; // r10\n __int64 v13; // rdi\n int v14; // esi\n _DWORD *v15; // rdx\n int v16; // eax\n __int64 v17; // rdx\n _BYTE v20[4088]; // [rsp+8h] [rbp-1050h] BYREF\n _BYTE *v21; // [rsp+1008h] [rbp-50h] BYREF\n __int64 v22; // [rsp+1010h] [rbp-48h]\n unsigned __int64 v23; // [rsp+1020h] [rbp-38h]\n\n v3 = a2 + 1;\n v4 = 4 * v3;\n v5 = a1;\n v23 = __readfsqword(0x28u);\n v6 = 4 * v3 * (a1 + 1) + 15;\n v7 = (char *)&v21 - (v6 & 0xFFFFFFFFFFFFF000LL);\n v8 = v6 & 0xFFF0;\n if ( &v21 != (_BYTE **)v7 )\n {\n while ( v20 != v7 )\n ;\n }\n v9 = v8 & 0xFFF;\n v10 = alloca(v9);\n if ( v9 )\n *(_QWORD *)&v20[v9 - 8] = *(_QWORD *)&v20[v9 - 8];\n v21 = v20;\n v11 = v4 >> 2;\n if ( a1 >= 0 && a2 >= 0 )\n {\n v12 = v20;\n v13 = 0LL;\n v22 = -(__int64)v11;\n while ( 1 )\n {\n v14 = v13;\n v15 = v12;\n if ( a2 <= (int)v13 )\n v14 = a2;\n v16 = 0;\n do\n {\n if ( v16 && (_DWORD)v13 )\n {\n if ( v16 == 1 )\n *(_DWORD *)&v21[4 * v11 * (int)v13 + 4] = v13;\n else\n *v15 = v15[v22] + v15[v11 * (((int)v13 >> 1) - v13) - 1];\n }\n else\n {\n *v15 = 0;\n }\n ++v16;\n ++v15;\n }\n while ( v16 <= v14 );\n v17 = v16;\n if ( a2 >= v16 )\n {\n do\n *(_DWORD *)&v12[4 * v17++] = 0;\n while ( a2 >= (int)v17 );\n }\n v12 += v4;\n if ( v13 == v5 )\n break;\n ++v13;\n }\n }\n return *(unsigned int *)&v21[4 * v11 * v5 + 4 * a2];\n}", + "ida_strip_asm": "sub_1220:\nendbr64\npush rbp\nlea edx, [rsi+1]\nmov ecx, esi\nmovsxd rdx, edx\nmov rbp, rsp\npush r15\npush r14\nlea r14, ds:0[rdx*4]\npush r13\npush r12\npush rbx\nmovsxd rbx, edi\nsub rsp, 28h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nlea eax, [rbx+1]\nmov rsi, rsp\ncdqe\nimul rax, rdx\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rsi, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rsi\njz short loc_1295\nloc_1280:\nsub rsp, 1000h\nor [rsp+1050h+var_58], 0\ncmp rsp, rsi\njnz short loc_1280\nloc_1295:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_13A7\nloc_12A7:\nmov r12, r14\nmov [rbp+var_50], rsp\nshr r12, 2\ntest ebx, ebx\njs loc_1378\ntest ecx, ecx\njs loc_1378\nmov r15, r12\nmov r10, rsp\nxor edi, edi\nneg r15\nmov [rbp+var_48], r15\nnop dword ptr [rax+00000000h]\nloc_12D8:\ntest edi, edi\nmov esi, edi\nmov r8d, edi\nmov r13d, edi\nsetz r9b\ncmp ecx, edi\nmov rdx, r10\ncmovle esi, ecx\nsar r8d, 1\nxor eax, eax\nmovsxd r8, r8d\nsub r8, rdi\nimul r8, r12\nloc_12FD:\ntest eax, eax\njz short loc_1358\ntest r9b, r9b\njnz short loc_1358\ncmp eax, 1\njz short loc_1360\nmov r15, [rbp+var_48]\nmov r11d, [rdx+r8*4-4]\nadd r11d, [rdx+r15*4]\nmov [rdx], r11d\nloc_131B:\nadd eax, 1\nadd rdx, 4\ncmp eax, esi\njle short loc_12FD\nmovsxd rdx, eax\ncmp ecx, eax\njl short loc_1340\nnop dword ptr [rax]\nloc_1330:\nmov dword ptr [r10+rdx*4], 0\nadd rdx, 1\ncmp ecx, edx\njge short loc_1330\nloc_1340:\nlea rax, [rdi+1]\nadd r10, r14\ncmp rdi, rbx\njz short loc_1378\nmov rdi, rax\njmp short loc_12D8\nloc_1358:\nmov dword ptr [rdx], 0\njmp short loc_131B\nloc_1360:\nmovsxd r11, r13d\nmov r15, [rbp+var_50]\nimul r11, r12\nmov [r15+r11*4+4], r13d\njmp short loc_131B\nloc_1378:\nimul rbx, r12\nmovsxd rax, ecx\nadd rax, rbx\nmov rbx, [rbp+var_50]\nmov eax, [rbx+rax*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_13B2\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_13A7:\nor [rsp+rdx+1050h+var_1058], 0\njmp loc_12A7\nloc_13B2:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1220(int a1, int a2)\n{\n __int64 v3; // rdx\n unsigned __int64 v4; // r14\n __int64 v5; // rbx\n __int64 v6; // rdx\n _BYTE *v7; // rsi\n __int16 v8; // dx\n signed __int64 v9; // rdx\n void *v10; // rsp\n unsigned __int64 v11; // r12\n _BYTE *v12; // r10\n __int64 v13; // rdi\n int v14; // esi\n _DWORD *v15; // rdx\n int v16; // eax\n __int64 v17; // rdx\n _BYTE v20[4088]; // [rsp+8h] [rbp-1050h] BYREF\n _BYTE *v21; // [rsp+1008h] [rbp-50h] BYREF\n __int64 v22; // [rsp+1010h] [rbp-48h]\n unsigned __int64 v23; // [rsp+1020h] [rbp-38h]\n\n v3 = a2 + 1;\n v4 = 4 * v3;\n v5 = a1;\n v23 = __readfsqword(0x28u);\n v6 = 4 * v3 * (a1 + 1) + 15;\n v7 = (char *)&v21 - (v6 & 0xFFFFFFFFFFFFF000LL);\n v8 = v6 & 0xFFF0;\n if ( &v21 != (_BYTE **)v7 )\n {\n while ( v20 != v7 )\n ;\n }\n v9 = v8 & 0xFFF;\n v10 = alloca(v9);\n if ( v9 )\n *(_QWORD *)&v20[v9 - 8] = *(_QWORD *)&v20[v9 - 8];\n v21 = v20;\n v11 = v4 >> 2;\n if ( a1 >= 0 && a2 >= 0 )\n {\n v12 = v20;\n v13 = 0LL;\n v22 = -(__int64)v11;\n while ( 1 )\n {\n v14 = v13;\n v15 = v12;\n if ( a2 <= (int)v13 )\n v14 = a2;\n v16 = 0;\n do\n {\n if ( v16 && (_DWORD)v13 )\n {\n if ( v16 == 1 )\n *(_DWORD *)&v21[4 * v11 * (int)v13 + 4] = v13;\n else\n *v15 = v15[v22] + v15[v11 * (((int)v13 >> 1) - v13) - 1];\n }\n else\n {\n *v15 = 0;\n }\n ++v16;\n ++v15;\n }\n while ( v16 <= v14 );\n v17 = v16;\n if ( a2 >= v16 )\n {\n do\n *(_DWORD *)&v12[4 * v17++] = 0;\n while ( a2 >= (int)v17 );\n }\n v12 += v4;\n if ( v13 == v5 )\n break;\n ++v13;\n }\n }\n return *(unsigned int *)&v21[4 * v11 * v5 + 4 * a2];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1220(int a1, int a2) {\n long long v3;\n unsigned long long v4;\n long long v5;\n long long v6;\n uint8_t *v7;\n short v8;\n signed long long v9;\n void *v10;\n unsigned long long v11;\n uint8_t *v12;\n long long v13;\n int v14;\n uint32_t *v15;\n int v16;\n long long v17;\n uint8_t v20[4088];\n uint8_t *v21;\n long long v22;\n unsigned long long v23;\n v3 = a2 + 1;\n v4 = 4 * v3;\n v5 = a1;\n v23 = __readfsqword(40u);\n v6 = 4 * v3 * (a1 + 1) + 15;\n v7 = (char *)&v21 - (v6 & 18446744073709547520LL);\n v8 = v6 & 65520;\n if (&v21 != (uint8_t **)v7) {\n while (v20 != v7)\n ;\n }\n v9 = v8 & 4095;\n v10 = alloca(v9);\n if (v9) *(uint64_t *)&v20[v9 - 8] = *(uint64_t *)&v20[v9 - 8];\n v21 = v20;\n v11 = v4 >> 2;\n if (a1 >= 0 && a2 >= 0) {\n v12 = v20;\n v13 = 0LL;\n v22 = -(long long)v11;\n while (1) {\n v14 = v13;\n v15 = v12;\n if (a2 <= (int)v13) v14 = a2;\n v16 = 0;\n do {\n if (v16 && (uint32_t)v13) {\n if (v16 == 1)\n *(uint32_t *)&v21[4 * v11 * (int)v13 + 4] = v13;\n else\n *v15 = v15[v22] + v15[v11 * (((int)v13 >> 1) - v13) - 1];\n } else {\n *v15 = 0;\n }\n ++v16;\n ++v15;\n } while (v16 <= v14);\n v17 = v16;\n if (a2 >= v16) {\n do\n *(uint32_t *)&v12[4 * v17++] = 0;\n while (a2 >= (int)v17);\n }\n v12 += v4;\n if (v13 == v5) break;\n ++v13;\n }\n }\n return *(unsigned int *)&v21[4 * v11 * v5 + 4 * a2];\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n long long v3;\n unsigned long long v4;\n long long v5;\n long long v6;\n uint8_t *v7;\n short v8;\n signed long long v9;\n void *v10;\n unsigned long long v11;\n uint8_t *v12;\n long long v13;\n int v14;\n uint32_t *v15;\n int v16;\n long long v17;\n uint8_t v20[4088];\n uint8_t *v21;\n long long v22;\n unsigned long long v23;\n v3 = a2 + 1;\n v4 = 4 * v3;\n v5 = a1;\n v23 = __readfsqword(40u);\n v6 = 4 * v3 * (a1 + 1) + 15;\n v7 = (char *)&v21 - (v6 & 18446744073709547520LL);\n v8 = v6 & 65520;\n if (&v21 != (uint8_t **)v7) {\n while (v20 != v7)\n ;\n }\n v9 = v8 & 4095;\n v10 = alloca(v9);\n if (v9) *(uint64_t *)&v20[v9 - 8] = *(uint64_t *)&v20[v9 - 8];\n v21 = v20;\n v11 = v4 >> 2;\n if (a1 >= 0 && a2 >= 0) {\n v12 = v20;\n v13 = 0LL;\n v22 = -(long long)v11;\n while (1) {\n v14 = v13;\n v15 = v12;\n if (a2 <= (int)v13) v14 = a2;\n v16 = 0;\n do {\n if (v16 && (uint32_t)v13) {\n if (v16 == 1)\n *(uint32_t *)&v21[4 * v11 * (int)v13 + 4] = v13;\n else\n *v15 = v15[v22] + v15[v11 * (((int)v13 >> 1) - v13) - 1];\n } else {\n *v15 = 0;\n }\n ++v16;\n ++v15;\n } while (v16 <= v14);\n v17 = v16;\n if (a2 >= v16) {\n do\n *(uint32_t *)&v12[4 * v17++] = 0;\n while (a2 >= (int)v17);\n }\n v12 += v4;\n if (v13 == v5) break;\n ++v13;\n }\n }\n return *(unsigned int *)&v21[4 * v11 * v5 + 4 * a2];\n}" + }, + { + "index": 240, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int list1[], int list1_size, int list2[], int list2_size,\n int result[]) {\n for (int i = 0; i < list1_size - 1; i++) {\n result[i] = list1[i];\n }\n for (int j = 0; j < list2_size; j++) {\n result[list1_size - 1 + j] = list2[j];\n }\n}", + "test": "int main() {\n\n int list1[] = {1, 3, 5, 7, 9, 10};\n\n int list2[] = {2, 4, 6, 8};\n\n int expected[] = {1, 3, 5, 7, 9, 2, 4, 6, 8};\n\n int result[9];\n\n func0(list1, 6, list2, 4, result);\n\n assert(memcmp(result, expected, sizeof(expected)) == 0);\n\n\n\n int list1b[] = {1, 2, 3, 4, 5};\n\n int list2b[] = {5, 6, 7, 8};\n\n int expectedb[] = {1, 2, 3, 4, 5, 6, 7, 8};\n\n int resultb[8];\n\n func0(list1b, 5, list2b, 4, resultb);\n\n assert(memcmp(resultb, expectedb, sizeof(expectedb)) == 0);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %ecx,-0x20(%rbp)\nmov %r8,-0x30(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11dd \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0x8(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x30(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x8(%rbp)\nmov -0x1c(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x8(%rbp)\njl 11ac \nmovl $0x0,-0x4(%rbp)\njmp 122a \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov -0x1c(%rbp),%edx\nlea -0x1(%rdx),%ecx\nmov -0x4(%rbp),%edx\nadd %ecx,%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x30(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x20(%rbp),%eax\njl 11f1 \npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov [rbp+var_30], r8\nmov [rbp+var_8], 0\njmp short loc_11DD\nloc_11AC:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_30]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_8], 1\nloc_11DD:\nmov eax, [rbp+var_1C]\nsub eax, 1\ncmp [rbp+var_8], eax\njl short loc_11AC\nmov [rbp+var_4], 0\njmp short loc_122A\nloc_11F1:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_1C]\nlea ecx, [rdx-1]\nmov edx, [rbp+var_4]\nadd edx, ecx\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_30]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_4], 1\nloc_122A:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_20]\njl short loc_11F1\nnop\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3, int a4, __int64 a5)\n{\n __int64 result; // rax\n int i; // [rsp+28h] [rbp-8h]\n unsigned int j; // [rsp+2Ch] [rbp-4h]\n\n for ( i = 0; i < a2 - 1; ++i )\n *(_DWORD *)(4LL * i + a5) = *(_DWORD *)(4LL * i + a1);\n for ( j = 0; ; ++j )\n {\n result = j;\n if ( (int)j >= a4 )\n break;\n *(_DWORD *)(4LL * (int)(a2 - 1 + j) + a5) = *(_DWORD *)(4LL * (int)j + a3);\n }\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov [rbp+var_30], r8\nmov [rbp+var_8], 0\njmp short loc_11DD\nloc_11AC:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_30]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_8], 1\nloc_11DD:\nmov eax, [rbp+var_1C]\nsub eax, 1\ncmp [rbp+var_8], eax\njl short loc_11AC\nmov [rbp+var_4], 0\njmp short loc_122A\nloc_11F1:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_1C]\nlea ecx, [rdx-1]\nmov edx, [rbp+var_4]\nadd edx, ecx\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_30]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_4], 1\nloc_122A:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_20]\njl short loc_11F1\nnop\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2, __int64 a3, int a4, __int64 a5)\n{\n __int64 result; // rax\n int i; // [rsp+28h] [rbp-8h]\n unsigned int j; // [rsp+2Ch] [rbp-4h]\n\n for ( i = 0; i < a2 - 1; ++i )\n *(_DWORD *)(4LL * i + a5) = *(_DWORD *)(4LL * i + a1);\n for ( j = 0; ; ++j )\n {\n result = j;\n if ( (int)j >= a4 )\n break;\n *(_DWORD *)(4LL * (int)(a2 - 1 + j) + a5) = *(_DWORD *)(4LL * (int)j + a3);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2, long long a3, int a4, long long a5) {\n long long result;\n int i;\n unsigned int j;\n for (i = 0; i < a2 - 1; ++i)\n *(uint32_t *)(4LL * i + a5) = *(uint32_t *)(4LL * i + a1);\n for (j = 0;; ++j) {\n result = j;\n if ((int)j >= a4) break;\n *(uint32_t *)(4LL * (int)(a2 - 1 + j) + a5) =\n *(uint32_t *)(4LL * (int)j + a3);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3, int a4, long long a5) {\n long long result;\n int i;\n unsigned int j;\n for (i = 0; i < a2 - 1; ++i)\n *(uint32_t *)(4LL * i + a5) = *(uint32_t *)(4LL * i + a1);\n for (j = 0;; ++j) {\n result = j;\n if ((int)j >= a4) break;\n *(uint32_t *)(4LL * (int)(a2 - 1 + j) + a5) =\n *(uint32_t *)(4LL * (int)j + a3);\n }\n return result;\n}" + }, + { + "index": 240, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int list1[], int list1_size, int list2[], int list2_size,\n int result[]) {\n for (int i = 0; i < list1_size - 1; i++) {\n result[i] = list1[i];\n }\n for (int j = 0; j < list2_size; j++) {\n result[list1_size - 1 + j] = list2[j];\n }\n}", + "test": "int main() {\n\n int list1[] = {1, 3, 5, 7, 9, 10};\n\n int list2[] = {2, 4, 6, 8};\n\n int expected[] = {1, 3, 5, 7, 9, 2, 4, 6, 8};\n\n int result[9];\n\n func0(list1, 6, list2, 4, result);\n\n assert(memcmp(result, expected, sizeof(expected)) == 0);\n\n\n\n int list1b[] = {1, 2, 3, 4, 5};\n\n int list2b[] = {5, 6, 7, 8};\n\n int expectedb[] = {1, 2, 3, 4, 5, 6, 7, 8};\n\n int resultb[8];\n\n func0(list1b, 5, list2b, 4, resultb);\n\n assert(memcmp(resultb, expectedb, sizeof(expectedb)) == 0);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%esi\njle 11af \nlea -0x2(%rsi),%r10d\nmov $0x0,%eax\nmov (%rdi,%rax,4),%r9d\nmov %r9d,(%r8,%rax,4)\nmov %rax,%r9\nadd $0x1,%rax\ncmp %r10,%r9\njne 119b \ntest %ecx,%ecx\njle 11d5 \nlea -0x1(%rcx),%edi\nmovslq %esi,%rsi\nlea (%r8,%rsi,4),%rsi\nmov $0x0,%eax\nmov (%rdx,%rax,4),%ecx\nmov %ecx,-0x4(%rsi,%rax,4)\nmov %rax,%rcx\nadd $0x1,%rax\ncmp %rdi,%rcx\njne 11c2 \nretq\n", + "ida_asm": "func0:\nendbr64\nmov r10d, esi\nmov rsi, rdx\ncmp r10d, 1\njle short loc_11B2\nlea r9d, [r10-1]\nmov eax, 0\nloc_11A2:\nmov edx, [rdi+rax*4]\nmov [r8+rax*4], edx\nadd rax, 1\ncmp rax, r9\njnz short loc_11A2\nloc_11B2:\ntest ecx, ecx\njle short locret_11D9\nmovsxd rcx, ecx\nshl rcx, 2\nmovsxd r10, r10d\nlea rdi, [r8+r10*4]\nmov eax, 0\nloc_11C9:\nmov edx, [rsi+rax]\nmov [rdi+rax-4], edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_11C9\nlocret_11D9:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2, __int64 a3, int a4, __int64 a5)\n{\n __int64 v5; // rax\n __int64 v6; // rcx\n __int64 v7; // rax\n\n if ( a2 > 1 )\n {\n v5 = 0LL;\n do\n {\n *(_DWORD *)(a5 + 4 * v5) = *(_DWORD *)(a1 + 4 * v5);\n ++v5;\n }\n while ( v5 != a2 - 1 );\n }\n if ( a4 > 0 )\n {\n v6 = 4LL * a4;\n v7 = 0LL;\n do\n {\n *(_DWORD *)(a5 + 4LL * a2 + v7 - 4) = *(_DWORD *)(a3 + v7);\n v7 += 4LL;\n }\n while ( v7 != v6 );\n }\n}", + "ida_strip_asm": "sub_1189:\nendbr64\nmov r10d, esi\nmov rsi, rdx\ncmp r10d, 1\njle short loc_11B2\nlea r9d, [r10-1]\nmov eax, 0\nloc_11A2:\nmov edx, [rdi+rax*4]\nmov [r8+rax*4], edx\nadd rax, 1\ncmp rax, r9\njnz short loc_11A2\nloc_11B2:\ntest ecx, ecx\njle short locret_11D9\nmovsxd rcx, ecx\nshl rcx, 2\nmovsxd r10, r10d\nlea rdi, [r8+r10*4]\nmov eax, 0\nloc_11C9:\nmov edx, [rsi+rax]\nmov [rdi+rax-4], edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_11C9\nlocret_11D9:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1189(__int64 a1, int a2, __int64 a3, int a4, __int64 a5)\n{\n __int64 v5; // rax\n __int64 v6; // rcx\n __int64 v7; // rax\n\n if ( a2 > 1 )\n {\n v5 = 0LL;\n do\n {\n *(_DWORD *)(a5 + 4 * v5) = *(_DWORD *)(a1 + 4 * v5);\n ++v5;\n }\n while ( v5 != a2 - 1 );\n }\n if ( a4 > 0 )\n {\n v6 = 4LL * a4;\n v7 = 0LL;\n do\n {\n *(_DWORD *)(a5 + 4LL * a2 + v7 - 4) = *(_DWORD *)(a3 + v7);\n v7 += 4LL;\n }\n while ( v7 != v6 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1189(long long a1, int a2, long long a3, int a4, long long a5) {\n long long v5;\n long long v6;\n long long v7;\n if (a2 > 1) {\n v5 = 0LL;\n do {\n *(uint32_t *)(a5 + 4 * v5) = *(uint32_t *)(a1 + 4 * v5);\n ++v5;\n } while (v5 != a2 - 1);\n }\n if (a4 > 0) {\n v6 = 4LL * a4;\n v7 = 0LL;\n do {\n *(uint32_t *)(a5 + 4LL * a2 + v7 - 4) = *(uint32_t *)(a3 + v7);\n v7 += 4LL;\n } while (v7 != v6);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2, long long a3, int a4, long long a5) {\n long long v5;\n long long v6;\n long long v7;\n if (a2 > 1) {\n v5 = 0LL;\n do {\n *(uint32_t *)(a5 + 4 * v5) = *(uint32_t *)(a1 + 4 * v5);\n ++v5;\n } while (v5 != a2 - 1);\n }\n if (a4 > 0) {\n v6 = 4LL * a4;\n v7 = 0LL;\n do {\n *(uint32_t *)(a5 + 4LL * a2 + v7 - 4) = *(uint32_t *)(a3 + v7);\n v7 += 4LL;\n } while (v7 != v6);\n }\n}" + }, + { + "index": 240, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int list1[], int list1_size, int list2[], int list2_size,\n int result[]) {\n for (int i = 0; i < list1_size - 1; i++) {\n result[i] = list1[i];\n }\n for (int j = 0; j < list2_size; j++) {\n result[list1_size - 1 + j] = list2[j];\n }\n}", + "test": "int main() {\n\n int list1[] = {1, 3, 5, 7, 9, 10};\n\n int list2[] = {2, 4, 6, 8};\n\n int expected[] = {1, 3, 5, 7, 9, 2, 4, 6, 8};\n\n int result[9];\n\n func0(list1, 6, list2, 4, result);\n\n assert(memcmp(result, expected, sizeof(expected)) == 0);\n\n\n\n int list1b[] = {1, 2, 3, 4, 5};\n\n int list2b[] = {5, 6, 7, 8};\n\n int expectedb[] = {1, 2, 3, 4, 5, 6, 7, 8};\n\n int resultb[8];\n\n func0(list1b, 5, list2b, 4, resultb);\n\n assert(memcmp(resultb, expectedb, sizeof(expectedb)) == 0);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%esi\njle 1274 \nlea -0x2(%rsi),%r10d\nxor %eax,%eax\nmov (%rdi,%rax,4),%r9d\nmov %r9d,(%r8,%rax,4)\nmov %rax,%r9\nadd $0x1,%rax\ncmp %r10,%r9\njne 1260 \ntest %ecx,%ecx\njle 129b \nmovslq %esi,%rsi\nlea -0x1(%rcx),%edi\nxor %eax,%eax\nlea (%r8,%rsi,4),%rsi\nnopl 0x0(%rax)\nmov (%rdx,%rax,4),%ecx\nmov %ecx,-0x4(%rsi,%rax,4)\nmov %rax,%rcx\nadd $0x1,%rax\ncmp %rcx,%rdi\njne 1288 \nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\nmovsxd r10, esi\nmov rsi, rdx\ncmp r10d, 1\njle short loc_1370\nlea r9d, [r10-1]\nxor eax, eax\nnop word ptr [rax+rax+00000000h]\nloc_1360:\nmov edx, [rdi+rax*4]\nmov [r8+rax*4], edx\nadd rax, 1\ncmp rax, r9\njnz short loc_1360\nloc_1370:\ntest ecx, ecx\njle short locret_1398\nmovsxd rcx, ecx\nlea rdi, [r8+r10*4]\nxor eax, eax\nshl rcx, 2\nnop dword ptr [rax+00000000h]\nloc_1388:\nmov edx, [rsi+rax]\nmov [rdi+rax-4], edx\nadd rax, 4\ncmp rcx, rax\njnz short loc_1388\nlocret_1398:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2, __int64 a3, int a4, __int64 a5)\n{\n __int64 v5; // rax\n __int64 v6; // rax\n __int64 v7; // rcx\n\n if ( a2 > 1 )\n {\n v5 = 0LL;\n do\n {\n *(_DWORD *)(a5 + 4 * v5) = *(_DWORD *)(a1 + 4 * v5);\n ++v5;\n }\n while ( v5 != a2 - 1 );\n }\n if ( a4 > 0 )\n {\n v6 = 0LL;\n v7 = 4LL * a4;\n do\n {\n *(_DWORD *)(a5 + 4LL * a2 + v6 - 4) = *(_DWORD *)(a3 + v6);\n v6 += 4LL;\n }\n while ( v7 != v6 );\n }\n}", + "ida_strip_asm": "sub_1340:\nendbr64\nmovsxd r10, esi\nmov rsi, rdx\ncmp r10d, 1\njle short loc_1370\nlea r9d, [r10-1]\nxor eax, eax\nnop word ptr [rax+rax+00000000h]\nloc_1360:\nmov edx, [rdi+rax*4]\nmov [r8+rax*4], edx\nadd rax, 1\ncmp rax, r9\njnz short loc_1360\nloc_1370:\ntest ecx, ecx\njle short locret_1398\nmovsxd rcx, ecx\nlea rdi, [r8+r10*4]\nxor eax, eax\nshl rcx, 2\nnop dword ptr [rax+00000000h]\nloc_1388:\nmov edx, [rsi+rax]\nmov [rdi+rax-4], edx\nadd rax, 4\ncmp rcx, rax\njnz short loc_1388\nlocret_1398:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1340(__int64 a1, int a2, __int64 a3, int a4, __int64 a5)\n{\n __int64 v5; // rax\n __int64 v6; // rax\n __int64 v7; // rcx\n\n if ( a2 > 1 )\n {\n v5 = 0LL;\n do\n {\n *(_DWORD *)(a5 + 4 * v5) = *(_DWORD *)(a1 + 4 * v5);\n ++v5;\n }\n while ( v5 != a2 - 1 );\n }\n if ( a4 > 0 )\n {\n v6 = 0LL;\n v7 = 4LL * a4;\n do\n {\n *(_DWORD *)(a5 + 4LL * a2 + v6 - 4) = *(_DWORD *)(a3 + v6);\n v6 += 4LL;\n }\n while ( v7 != v6 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1340(long long a1, int a2, long long a3, int a4, long long a5) {\n long long v5;\n long long v6;\n long long v7;\n if (a2 > 1) {\n v5 = 0LL;\n do {\n *(uint32_t *)(a5 + 4 * v5) = *(uint32_t *)(a1 + 4 * v5);\n ++v5;\n } while (v5 != a2 - 1);\n }\n if (a4 > 0) {\n v6 = 0LL;\n v7 = 4LL * a4;\n do {\n *(uint32_t *)(a5 + 4LL * a2 + v6 - 4) = *(uint32_t *)(a3 + v6);\n v6 += 4LL;\n } while (v7 != v6);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2, long long a3, int a4, long long a5) {\n long long v5;\n long long v6;\n long long v7;\n if (a2 > 1) {\n v5 = 0LL;\n do {\n *(uint32_t *)(a5 + 4 * v5) = *(uint32_t *)(a1 + 4 * v5);\n ++v5;\n } while (v5 != a2 - 1);\n }\n if (a4 > 0) {\n v6 = 0LL;\n v7 = 4LL * a4;\n do {\n *(uint32_t *)(a5 + 4LL * a2 + v6 - 4) = *(uint32_t *)(a3 + v6);\n v6 += 4LL;\n } while (v7 != v6);\n }\n}" + }, + { + "index": 241, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n", + "func": "char*** func0(int m, int n, int o) {\n char*** result = (char***)malloc(o * sizeof(char**));\n for (int i = 0; i < o; i++) {\n result[i] = (char**)malloc(n * sizeof(char*));\n for (int j = 0; j < n; j++) {\n result[i][j] = (char*)malloc(m * sizeof(char));\n for (int k = 0; k < m; k++) {\n result[i][j][k] = '*';\n }\n }\n }\n return result;\n}", + "test": "int main() {\n\n char*** output;\n\n int m, n, o, i, j, k;\n\n\n\n m = 6; n = 4; o = 3;\n\n output = func0(m, n, o);\n\n for (i = 0; i < o; i++) {\n\n for (j = 0; j < n; j++) {\n\n for (k = 0; k < m; k++) {\n\n assert(output[i][j][k] == '*');\n\n }\n\n }\n\n }\n\n\n\n m = 5; n = 3; o = 4;\n\n output = func0(m, n, o);\n\n for (i = 0; i < o; i++) {\n\n for (j = 0; j < n; j++) {\n\n for (k = 0; k < m; k++) {\n\n assert(output[i][j][k] == '*');\n\n }\n\n }\n\n }\n\n\n\n m = 1; n = 2; o = 3;\n\n output = func0(m, n, o);\n\n for (i = 0; i < o; i++) {\n\n for (j = 0; j < n; j++) {\n\n for (k = 0; k < m; k++) {\n\n assert(output[i][j][k] == '*');\n\n }\n\n }\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x38,%rsp\nmov %edi,-0x34(%rbp)\nmov %esi,-0x38(%rbp)\nmov %edx,-0x3c(%rbp)\nmov -0x3c(%rbp),%eax\ncltq\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 1070 \nmov %rax,-0x18(%rbp)\nmovl $0x0,-0x24(%rbp)\njmpq 1267 \nmov -0x38(%rbp),%eax\ncltq\nshl $0x3,%rax\nmov -0x24(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x18(%rbp),%rdx\nlea (%rcx,%rdx,1),%rbx\nmov %rax,%rdi\ncallq 1070 \nmov %rax,(%rbx)\nmovl $0x0,-0x20(%rbp)\njmpq 1257 \nmov -0x34(%rbp),%eax\ncltq\nmov -0x24(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rdx),%rdx\nmov -0x20(%rbp),%ecx\nmovslq %ecx,%rcx\nshl $0x3,%rcx\nlea (%rdx,%rcx,1),%rbx\nmov %rax,%rdi\ncallq 1070 \nmov %rax,(%rbx)\nmovl $0x0,-0x1c(%rbp)\njmp 124b \nmov -0x24(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0x20(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x3,%rdx\nadd %rdx,%rax\nmov (%rax),%rdx\nmov -0x1c(%rbp),%eax\ncltq\nadd %rdx,%rax\nmovb $0x2a,(%rax)\naddl $0x1,-0x1c(%rbp)\nmov -0x1c(%rbp),%eax\ncmp -0x34(%rbp),%eax\njl 1215 \naddl $0x1,-0x20(%rbp)\nmov -0x20(%rbp),%eax\ncmp -0x38(%rbp),%eax\njl 11d6 \naddl $0x1,-0x24(%rbp)\nmov -0x24(%rbp),%eax\ncmp -0x3c(%rbp),%eax\njl 11a0 \nmov -0x18(%rbp),%rax\nadd $0x38,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+var_34], edi\nmov [rbp+var_38], esi\nmov [rbp+var_3C], edx\nmov eax, [rbp+var_3C]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_24], 0\njmp loc_1267\nloc_11A0:\nmov eax, [rbp+var_38]\ncdqe\nshl rax, 3\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nlea rbx, [rcx+rdx]\nmov rdi, rax; size\ncall _malloc\nmov [rbx], rax\nmov [rbp+var_20], 0\njmp loc_1257\nloc_11D6:\nmov eax, [rbp+var_34]\ncdqe\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov rdx, [rdx]\nmov ecx, [rbp+var_20]\nmovsxd rcx, ecx\nshl rcx, 3\nlea rbx, [rdx+rcx]\nmov rdi, rax; size\ncall _malloc\nmov [rbx], rax\nmov [rbp+var_1C], 0\njmp short loc_124B\nloc_1215:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nshl rdx, 3\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_1C]\ncdqe\nadd rax, rdx\nmov byte ptr [rax], 2Ah ; '*'\nadd [rbp+var_1C], 1\nloc_124B:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_34]\njl short loc_1215\nadd [rbp+var_20], 1\nloc_1257:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_38]\njl loc_11D6\nadd [rbp+var_24], 1\nloc_1267:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_3C]\njl loc_11A0\nmov rax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(int a1, int a2, int a3)\n{\n void **v3; // rbx\n int i; // [rsp+1Ch] [rbp-24h]\n int j; // [rsp+20h] [rbp-20h]\n int k; // [rsp+24h] [rbp-1Ch]\n _QWORD *v9; // [rsp+28h] [rbp-18h]\n\n v9 = malloc(8LL * a3);\n for ( i = 0; i < a3; ++i )\n {\n v9[i] = malloc(8LL * a2);\n for ( j = 0; j < a2; ++j )\n {\n v3 = (void **)(v9[i] + 8LL * j);\n *v3 = malloc(a1);\n for ( k = 0; k < a1; ++k )\n *(_BYTE *)(*(_QWORD *)(8LL * j + v9[i]) + k) = 42;\n }\n }\n return v9;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+var_34], edi\nmov [rbp+var_38], esi\nmov [rbp+var_3C], edx\nmov eax, [rbp+var_3C]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_24], 0\njmp loc_1267\nloc_11A0:\nmov eax, [rbp+var_38]\ncdqe\nshl rax, 3\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nlea rbx, [rcx+rdx]\nmov rdi, rax; size\ncall _malloc\nmov [rbx], rax\nmov [rbp+var_20], 0\njmp loc_1257\nloc_11D6:\nmov eax, [rbp+var_34]\ncdqe\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov rdx, [rdx]\nmov ecx, [rbp+var_20]\nmovsxd rcx, ecx\nshl rcx, 3\nlea rbx, [rdx+rcx]\nmov rdi, rax; size\ncall _malloc\nmov [rbx], rax\nmov [rbp+var_1C], 0\njmp short loc_124B\nloc_1215:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nshl rdx, 3\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_1C]\ncdqe\nadd rax, rdx\nmov byte ptr [rax], 2Ah ; '*'\nadd [rbp+var_1C], 1\nloc_124B:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_34]\njl short loc_1215\nadd [rbp+var_20], 1\nloc_1257:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_38]\njl loc_11D6\nadd [rbp+var_24], 1\nloc_1267:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_3C]\njl loc_11A0\nmov rax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1169(int a1, int a2, int a3)\n{\n void **v3; // rbx\n int i; // [rsp+1Ch] [rbp-24h]\n int j; // [rsp+20h] [rbp-20h]\n int k; // [rsp+24h] [rbp-1Ch]\n _QWORD *v9; // [rsp+28h] [rbp-18h]\n\n v9 = malloc(8LL * a3);\n for ( i = 0; i < a3; ++i )\n {\n v9[i] = malloc(8LL * a2);\n for ( j = 0; j < a2; ++j )\n {\n v3 = (void **)(v9[i] + 8LL * j);\n *v3 = malloc(a1);\n for ( k = 0; k < a1; ++k )\n *(_BYTE *)(*(_QWORD *)(8LL * j + v9[i]) + k) = 42;\n }\n }\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1169(int a1, int a2, int a3) {\n void **v3;\n int i;\n int j;\n int k;\n uint64_t *v9;\n v9 = malloc(8LL * a3);\n for (i = 0; i < a3; ++i) {\n v9[i] = malloc(8LL * a2);\n for (j = 0; j < a2; ++j) {\n v3 = (void **)(v9[i] + 8LL * j);\n *v3 = malloc(a1);\n for (k = 0; k < a1; ++k)\n *(uint8_t *)(*(uint64_t *)(8LL * j + v9[i]) + k) = 42;\n }\n }\n return v9;\n}", + "ida_pseudo_norm": "uint64_t *func0(int a1, int a2, int a3) {\n void **v3;\n int i;\n int j;\n int k;\n uint64_t *v9;\n v9 = malloc(8LL * a3);\n for (i = 0; i < a3; ++i) {\n v9[i] = malloc(8LL * a2);\n for (j = 0; j < a2; ++j) {\n v3 = (void **)(v9[i] + 8LL * j);\n *v3 = malloc(a1);\n for (k = 0; k < a1; ++k)\n *(uint8_t *)(*(uint64_t *)(8LL * j + v9[i]) + k) = 42;\n }\n }\n return v9;\n}" + }, + { + "index": 241, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n", + "func": "char*** func0(int m, int n, int o) {\n char*** result = (char***)malloc(o * sizeof(char**));\n for (int i = 0; i < o; i++) {\n result[i] = (char**)malloc(n * sizeof(char*));\n for (int j = 0; j < n; j++) {\n result[i][j] = (char*)malloc(m * sizeof(char));\n for (int k = 0; k < m; k++) {\n result[i][j][k] = '*';\n }\n }\n }\n return result;\n}", + "test": "int main() {\n\n char*** output;\n\n int m, n, o, i, j, k;\n\n\n\n m = 6; n = 4; o = 3;\n\n output = func0(m, n, o);\n\n for (i = 0; i < o; i++) {\n\n for (j = 0; j < n; j++) {\n\n for (k = 0; k < m; k++) {\n\n assert(output[i][j][k] == '*');\n\n }\n\n }\n\n }\n\n\n\n m = 5; n = 3; o = 4;\n\n output = func0(m, n, o);\n\n for (i = 0; i < o; i++) {\n\n for (j = 0; j < n; j++) {\n\n for (k = 0; k < m; k++) {\n\n assert(output[i][j][k] == '*');\n\n }\n\n }\n\n }\n\n\n\n m = 1; n = 2; o = 3;\n\n output = func0(m, n, o);\n\n for (i = 0; i < o; i++) {\n\n for (j = 0; j < n; j++) {\n\n for (k = 0; k < m; k++) {\n\n assert(output[i][j][k] == '*');\n\n }\n\n }\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x38,%rsp\nmov %edi,%r13d\nmov %esi,%r14d\nmov %esi,0x24(%rsp)\nmov %edx,%ebx\nmovslq %edx,%rdi\nshl $0x3,%rdi\ncallq 1070 \nmov %rax,0x28(%rsp)\ntest %ebx,%ebx\njle 124b \nmov %rax,%rdi\nmovslq %r14d,%rax\nshl $0x3,%rax\nmov %rax,0x10(%rsp)\nmov %rdi,0x8(%rsp)\nlea -0x1(%rbx),%eax\nlea 0x8(%rdi,%rax,8),%rax\nmov %rax,0x18(%rsp)\nlea -0x1(%r14),%eax\nlea 0x8(,%rax,8),%r15\nmovslq %r13d,%r14\njmp 1228 \nadd $0x8,%rbx\ncmp %r15,%rbx\nje 1216 \nmov %rbx,%r12\nadd 0x0(%rbp),%r12\nmov %r14,%rdi\ncallq 1070 \nmov %rax,(%r12)\ntest %r13d,%r13d\njle 11d2 \nlea -0x1(%r13),%ecx\nmov $0x0,%eax\nmov 0x0(%rbp),%rdx\nmov (%rdx,%rbx,1),%rdx\nmovb $0x2a,(%rdx,%rax,1)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rdx,%rcx\njne 11fc \njmp 11d2 \naddq $0x8,0x8(%rsp)\nmov 0x8(%rsp),%rax\ncmp 0x18(%rsp),%rax\nje 124b \nmov 0x10(%rsp),%rdi\ncallq 1070 \nmov 0x8(%rsp),%rsi\nmov %rsi,%rbp\nmov %rax,(%rsi)\ncmpl $0x0,0x24(%rsp)\njle 1216 \nmov $0x0,%ebx\njmp 11db \nmov 0x28(%rsp),%rax\nadd $0x38,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov r13d, edi\nmov r15d, esi\nmov [rsp+58h+var_44], esi\nmov ebp, edx\nmovsxd rbx, edx\nshl rbx, 3\nmov rdi, rbx; size\ncall _malloc\nmov [rsp+58h+var_40], rax\ntest ebp, ebp\njle short loc_1206\nmovsxd r15, r15d\nshl r15, 3\nmov r14, rax\nadd rax, rbx\nmov [rsp+58h+var_50], rax\nmovsxd rbp, r13d\nloc_11B4:\nmov rdi, r15; size\ncall _malloc\nmov [r14], rax\ncmp [rsp+58h+var_44], 0\njle short loc_11F8\nmov rbx, rax\nlea r12, [rax+r15]\nloc_11CD:\nmov rdi, rbp; size\ncall _malloc\nmov [rbx], rax\ntest r13d, r13d\njle short loc_11EF\nmov rdx, rax\nadd rax, rbp\nloc_11E3:\nmov byte ptr [rdx], 2Ah ; '*'\nadd rdx, 1\ncmp rdx, rax\njnz short loc_11E3\nloc_11EF:\nadd rbx, 8\ncmp rbx, r12\njnz short loc_11CD\nloc_11F8:\nadd r14, 8\nmov rax, [rsp+58h+var_50]\ncmp r14, rax\njnz short loc_11B4\nloc_1206:\nmov rax, [rsp+58h+var_40]\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(int a1, int a2, int a3)\n{\n size_t v4; // rbx\n _QWORD *v5; // rax\n size_t v6; // r15\n _QWORD *v7; // r14\n _QWORD *v8; // rax\n _QWORD *v9; // rbx\n _QWORD *v10; // r12\n _BYTE *v11; // rax\n _BYTE *v12; // rdx\n _BYTE *v13; // rax\n _QWORD *v15; // [rsp+8h] [rbp-50h]\n _QWORD *v16; // [rsp+18h] [rbp-40h]\n\n v4 = a3;\n v5 = malloc(v4 * 8);\n v16 = v5;\n if ( a3 > 0 )\n {\n v6 = a2;\n v7 = v5;\n v15 = &v5[v4];\n do\n {\n v8 = malloc(v6 * 8);\n *v7 = v8;\n if ( a2 > 0 )\n {\n v9 = v8;\n v10 = &v8[v6];\n do\n {\n v11 = malloc(a1);\n *v9 = v11;\n if ( a1 > 0 )\n {\n v12 = v11;\n v13 = &v11[a1];\n do\n *v12++ = 42;\n while ( v12 != v13 );\n }\n ++v9;\n }\n while ( v9 != v10 );\n }\n ++v7;\n }\n while ( v7 != v15 );\n }\n return v16;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov r13d, edi\nmov r15d, esi\nmov [rsp+58h+var_44], esi\nmov ebp, edx\nmovsxd rbx, edx\nshl rbx, 3\nmov rdi, rbx; size\ncall _malloc\nmov [rsp+58h+var_40], rax\ntest ebp, ebp\njle short loc_1206\nmovsxd r15, r15d\nshl r15, 3\nmov r14, rax\nadd rax, rbx\nmov [rsp+58h+var_50], rax\nmovsxd rbp, r13d\nloc_11B4:\nmov rdi, r15; size\ncall _malloc\nmov [r14], rax\ncmp [rsp+58h+var_44], 0\njle short loc_11F8\nmov rbx, rax\nlea r12, [rax+r15]\nloc_11CD:\nmov rdi, rbp; size\ncall _malloc\nmov [rbx], rax\ntest r13d, r13d\njle short loc_11EF\nmov rdx, rax\nadd rax, rbp\nloc_11E3:\nmov byte ptr [rdx], 2Ah ; '*'\nadd rdx, 1\ncmp rdx, rax\njnz short loc_11E3\nloc_11EF:\nadd rbx, 8\ncmp rbx, r12\njnz short loc_11CD\nloc_11F8:\nadd r14, 8\nmov rax, [rsp+58h+var_50]\ncmp r14, rax\njnz short loc_11B4\nloc_1206:\nmov rax, [rsp+58h+var_40]\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1169(int a1, int a2, int a3)\n{\n size_t v4; // rbx\n _QWORD *v5; // rax\n size_t v6; // r15\n _QWORD *v7; // r14\n _QWORD *v8; // rax\n _QWORD *v9; // rbx\n _QWORD *v10; // r12\n _BYTE *v11; // rax\n _BYTE *v12; // rdx\n _BYTE *v13; // rax\n _QWORD *v15; // [rsp+8h] [rbp-50h]\n _QWORD *v16; // [rsp+18h] [rbp-40h]\n\n v4 = a3;\n v5 = malloc(v4 * 8);\n v16 = v5;\n if ( a3 > 0 )\n {\n v6 = a2;\n v7 = v5;\n v15 = &v5[v4];\n do\n {\n v8 = malloc(v6 * 8);\n *v7 = v8;\n if ( a2 > 0 )\n {\n v9 = v8;\n v10 = &v8[v6];\n do\n {\n v11 = malloc(a1);\n *v9 = v11;\n if ( a1 > 0 )\n {\n v12 = v11;\n v13 = &v11[a1];\n do\n *v12++ = 42;\n while ( v12 != v13 );\n }\n ++v9;\n }\n while ( v9 != v10 );\n }\n ++v7;\n }\n while ( v7 != v15 );\n }\n return v16;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1169(int a1, int a2, int a3) {\n unsigned int v4;\n uint64_t *v5;\n unsigned int v6;\n uint64_t *v7;\n uint64_t *v8;\n uint64_t *v9;\n uint64_t *v10;\n uint8_t *v11;\n uint8_t *v12;\n uint8_t *v13;\n uint64_t *v15;\n uint64_t *v16;\n v4 = a3;\n v5 = malloc(v4 * 8);\n v16 = v5;\n if (a3 > 0) {\n v6 = a2;\n v7 = v5;\n v15 = &v5[v4];\n do {\n v8 = malloc(v6 * 8);\n *v7 = v8;\n if (a2 > 0) {\n v9 = v8;\n v10 = &v8[v6];\n do {\n v11 = malloc(a1);\n *v9 = v11;\n if (a1 > 0) {\n v12 = v11;\n v13 = &v11[a1];\n do\n *v12++ = 42;\n while (v12 != v13);\n }\n ++v9;\n } while (v9 != v10);\n }\n ++v7;\n } while (v7 != v15);\n }\n return v16;\n}", + "ida_pseudo_norm": "uint64_t *func0(int a1, int a2, int a3) {\n unsigned int v4;\n uint64_t *v5;\n unsigned int v6;\n uint64_t *v7;\n uint64_t *v8;\n uint64_t *v9;\n uint64_t *v10;\n uint8_t *v11;\n uint8_t *v12;\n uint8_t *v13;\n uint64_t *v15;\n uint64_t *v16;\n v4 = a3;\n v5 = malloc(v4 * 8);\n v16 = v5;\n if (a3 > 0) {\n v6 = a2;\n v7 = v5;\n v15 = &v5[v4];\n do {\n v8 = malloc(v6 * 8);\n *v7 = v8;\n if (a2 > 0) {\n v9 = v8;\n v10 = &v8[v6];\n do {\n v11 = malloc(a1);\n *v9 = v11;\n if (a1 > 0) {\n v12 = v11;\n v13 = &v11[a1];\n do\n *v12++ = 42;\n while (v12 != v13);\n }\n ++v9;\n } while (v9 != v10);\n }\n ++v7;\n } while (v7 != v15);\n }\n return v16;\n}" + }, + { + "index": 241, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n", + "func": "char*** func0(int m, int n, int o) {\n char*** result = (char***)malloc(o * sizeof(char**));\n for (int i = 0; i < o; i++) {\n result[i] = (char**)malloc(n * sizeof(char*));\n for (int j = 0; j < n; j++) {\n result[i][j] = (char*)malloc(m * sizeof(char));\n for (int k = 0; k < m; k++) {\n result[i][j][k] = '*';\n }\n }\n }\n return result;\n}", + "test": "int main() {\n\n char*** output;\n\n int m, n, o, i, j, k;\n\n\n\n m = 6; n = 4; o = 3;\n\n output = func0(m, n, o);\n\n for (i = 0; i < o; i++) {\n\n for (j = 0; j < n; j++) {\n\n for (k = 0; k < m; k++) {\n\n assert(output[i][j][k] == '*');\n\n }\n\n }\n\n }\n\n\n\n m = 5; n = 3; o = 4;\n\n output = func0(m, n, o);\n\n for (i = 0; i < o; i++) {\n\n for (j = 0; j < n; j++) {\n\n for (k = 0; k < m; k++) {\n\n assert(output[i][j][k] == '*');\n\n }\n\n }\n\n }\n\n\n\n m = 1; n = 2; o = 3;\n\n output = func0(m, n, o);\n\n for (i = 0; i < o; i++) {\n\n for (j = 0; j < n; j++) {\n\n for (k = 0; k < m; k++) {\n\n assert(output[i][j][k] == '*');\n\n }\n\n }\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\nmov %esi,%r14d\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %edi,%ebx\nmovslq %edx,%rdi\nmov %rdi,%rbp\nshl $0x3,%rdi\nsub $0x28,%rsp\nmov %esi,0x14(%rsp)\ncallq 1070 \nmov %rax,0x18(%rsp)\ntest %ebp,%ebp\njle 1393 \nmovslq %r14d,%r15\nmov %rax,%r14\nmovslq %ebx,%r12\nlea 0x0(,%r15,8),%rdi\nmov %rdi,(%rsp)\nmov %rax,%rdi\nlea -0x1(%rbp),%eax\nlea -0x1(%r15),%ebp\nlea 0x8(%rdi,%rax,8),%rax\nshl $0x3,%rbp\nmov %rax,0x8(%rsp)\nlea -0x1(%rbx),%eax\nmov %eax,0x10(%rsp)\nnopl 0x0(%rax,%rax,1)\nmov (%rsp),%rdi\ncallq 1070 \nmov %rax,(%r14)\nmov %rax,%r13\nmov 0x14(%rsp),%eax\ntest %eax,%eax\njle 1388 \nxor %r15d,%r15d\nnopw 0x0(%rax,%rax,1)\nmov %r12,%rdi\ncallq 1070 \nmov %rax,0x0(%r13,%r15,1)\ntest %ebx,%ebx\njle 1377 \nmov 0x10(%rsp),%edi\nxor %edx,%edx\njmp 136a \nnopl 0x0(%rax)\nmov (%r14),%rax\nmov %rcx,%rdx\nmov (%rax,%r15,1),%rax\nmovb $0x2a,(%rax,%rdx,1)\nlea 0x1(%rdx),%rcx\ncmp %rdi,%rdx\njne 1360 \ncmp %r15,%rbp\nje 1388 \nmov (%r14),%r13\nadd $0x8,%r15\njmp 1340 \nnopl (%rax)\nadd $0x8,%r14\ncmp 0x8(%rsp),%r14\njne 1320 \nmov 0x18(%rsp),%rax\nadd $0x28,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14d, esi\npush r13\npush r12\npush rbp\nmovsxd rbp, edx\npush rbx\nmov r12, rbp\nshl rbp, 3\nmov ebx, edi\nmov rdi, rbp; size\nsub rsp, 28h\nmov [rsp+58h+var_44], esi\ncall _malloc\nmov [rsp+58h+var_40], rax\ntest r12d, r12d\njle short loc_1386\nmovsxd r15, r14d\nmov r14, rax\nadd rax, rbp\nmovsxd r12, ebx\nlea rcx, ds:0[r15*8]\nmov [rsp+58h+var_50], rax\nmov [rsp+58h+size], rcx\nnop dword ptr [rax+00h]\nloc_1328:\nmov rbp, [rsp+58h+size]\nmov r13d, ebx\nmov rdi, rbp; size\ncall _malloc\nmov [r14], rax\nmov r15, rax\nadd rbp, rax\nmov eax, [rsp+58h+var_44]\ntest eax, eax\njle short loc_1378\nnop dword ptr [rax+rax+00000000h]\nloc_1350:\nmov rdi, r12; size\ncall _malloc\nmov [r15], rax\nmov rdi, rax; s\ntest ebx, ebx\njle short loc_136F\nmov rdx, r13; n\nmov esi, 2Ah ; '*'; c\ncall _memset\nloc_136F:\nadd r15, 8\ncmp rbp, r15\njnz short loc_1350\nloc_1378:\nmov rax, [rsp+58h+var_50]\nadd r14, 8\ncmp r14, rax\njnz short loc_1328\nloc_1386:\nmov rax, [rsp+58h+var_40]\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(size_t n, int a2, int a3)\n{\n size_t v4; // rbp\n _QWORD *v5; // rax\n _QWORD *v6; // r14\n _QWORD *v7; // rax\n _QWORD *v8; // r15\n _QWORD *v9; // rbp\n void *v10; // rax\n __int64 size; // [rsp+0h] [rbp-58h]\n _QWORD *v13; // [rsp+8h] [rbp-50h]\n _QWORD *v14; // [rsp+18h] [rbp-40h]\n\n v4 = a3;\n v5 = malloc(v4 * 8);\n v14 = v5;\n if ( a3 > 0 )\n {\n v6 = v5;\n v13 = &v5[v4];\n size = a2;\n do\n {\n v7 = malloc(size * 8);\n *v6 = v7;\n v8 = v7;\n v9 = &v7[size];\n if ( a2 > 0 )\n {\n do\n {\n v10 = malloc((int)n);\n *v8 = v10;\n if ( (int)n > 0 )\n memset(v10, 42, (unsigned int)n);\n ++v8;\n }\n while ( v9 != v8 );\n }\n ++v6;\n }\n while ( v6 != v13 );\n }\n return v14;\n}", + "ida_strip_asm": "sub_12D0:\nendbr64\npush r15\npush r14\nmov r14d, esi\npush r13\npush r12\npush rbp\nmovsxd rbp, edx\npush rbx\nmov r12, rbp\nshl rbp, 3\nmov ebx, edi\nmov rdi, rbp; size\nsub rsp, 28h\nmov [rsp+58h+var_44], esi\ncall _malloc\nmov [rsp+58h+var_40], rax\ntest r12d, r12d\njle short loc_1386\nmovsxd r15, r14d\nmov r14, rax\nadd rax, rbp\nmovsxd r12, ebx\nlea rcx, ds:0[r15*8]\nmov [rsp+58h+var_50], rax\nmov [rsp+58h+size], rcx\nnop dword ptr [rax+00h]\nloc_1328:\nmov rbp, [rsp+58h+size]\nmov r13d, ebx\nmov rdi, rbp; size\ncall _malloc\nmov [r14], rax\nmov r15, rax\nadd rbp, rax\nmov eax, [rsp+58h+var_44]\ntest eax, eax\njle short loc_1378\nnop dword ptr [rax+rax+00000000h]\nloc_1350:\nmov rdi, r12; size\ncall _malloc\nmov [r15], rax\nmov rdi, rax; s\ntest ebx, ebx\njle short loc_136F\nmov rdx, r13; n\nmov esi, 2Ah ; '*'; c\ncall _memset\nloc_136F:\nadd r15, 8\ncmp rbp, r15\njnz short loc_1350\nloc_1378:\nmov rax, [rsp+58h+var_50]\nadd r14, 8\ncmp r14, rax\njnz short loc_1328\nloc_1386:\nmov rax, [rsp+58h+var_40]\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_12D0(size_t n, int a2, int a3)\n{\n size_t v4; // rbp\n _QWORD *v5; // rax\n _QWORD *v6; // r14\n _QWORD *v7; // rax\n _QWORD *v8; // r15\n _QWORD *v9; // rbp\n void *v10; // rax\n __int64 size; // [rsp+0h] [rbp-58h]\n _QWORD *v13; // [rsp+8h] [rbp-50h]\n _QWORD *v14; // [rsp+18h] [rbp-40h]\n\n v4 = a3;\n v5 = malloc(v4 * 8);\n v14 = v5;\n if ( a3 > 0 )\n {\n v6 = v5;\n v13 = &v5[v4];\n size = a2;\n do\n {\n v7 = malloc(size * 8);\n *v6 = v7;\n v8 = v7;\n v9 = &v7[size];\n if ( a2 > 0 )\n {\n do\n {\n v10 = malloc((int)n);\n *v8 = v10;\n if ( (int)n > 0 )\n memset(v10, 42, (unsigned int)n);\n ++v8;\n }\n while ( v9 != v8 );\n }\n ++v6;\n }\n while ( v6 != v13 );\n }\n return v14;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_12D0(unsigned int n, int a2, int a3) {\n unsigned int v4;\n uint64_t *v5;\n uint64_t *v6;\n uint64_t *v7;\n uint64_t *v8;\n uint64_t *v9;\n void *v10;\n long long size;\n uint64_t *v13;\n uint64_t *v14;\n v4 = a3;\n v5 = malloc(v4 * 8);\n v14 = v5;\n if (a3 > 0) {\n v6 = v5;\n v13 = &v5[v4];\n size = a2;\n do {\n v7 = malloc(size * 8);\n *v6 = v7;\n v8 = v7;\n v9 = &v7[size];\n if (a2 > 0) {\n do {\n v10 = malloc((int)n);\n *v8 = v10;\n if ((int)n > 0) memset(v10, 42, (unsigned int)n);\n ++v8;\n } while (v9 != v8);\n }\n ++v6;\n } while (v6 != v13);\n }\n return v14;\n}", + "ida_pseudo_norm": "uint64_t *func0(unsigned int n, int a2, int a3) {\n unsigned int v4;\n uint64_t *v5;\n uint64_t *v6;\n uint64_t *v7;\n uint64_t *v8;\n uint64_t *v9;\n void *v10;\n long long size;\n uint64_t *v13;\n uint64_t *v14;\n v4 = a3;\n v5 = malloc(v4 * 8);\n v14 = v5;\n if (a3 > 0) {\n v6 = v5;\n v13 = &v5[v4];\n size = a2;\n do {\n v7 = malloc(size * 8);\n *v6 = v7;\n v8 = v7;\n v9 = &v7[size];\n if (a2 > 0) {\n do {\n v10 = malloc((int)n);\n *v8 = v10;\n if ((int)n > 0) memset(v10, 42, (unsigned int)n);\n ++v8;\n } while (v9 != v8);\n }\n ++v6;\n } while (v6 != v13);\n }\n return v14;\n}" + }, + { + "index": 241, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n", + "func": "char*** func0(int m, int n, int o) {\n char*** result = (char***)malloc(o * sizeof(char**));\n for (int i = 0; i < o; i++) {\n result[i] = (char**)malloc(n * sizeof(char*));\n for (int j = 0; j < n; j++) {\n result[i][j] = (char*)malloc(m * sizeof(char));\n for (int k = 0; k < m; k++) {\n result[i][j][k] = '*';\n }\n }\n }\n return result;\n}", + "test": "int main() {\n\n char*** output;\n\n int m, n, o, i, j, k;\n\n\n\n m = 6; n = 4; o = 3;\n\n output = func0(m, n, o);\n\n for (i = 0; i < o; i++) {\n\n for (j = 0; j < n; j++) {\n\n for (k = 0; k < m; k++) {\n\n assert(output[i][j][k] == '*');\n\n }\n\n }\n\n }\n\n\n\n m = 5; n = 3; o = 4;\n\n output = func0(m, n, o);\n\n for (i = 0; i < o; i++) {\n\n for (j = 0; j < n; j++) {\n\n for (k = 0; k < m; k++) {\n\n assert(output[i][j][k] == '*');\n\n }\n\n }\n\n }\n\n\n\n m = 1; n = 2; o = 3;\n\n output = func0(m, n, o);\n\n for (i = 0; i < o; i++) {\n\n for (j = 0; j < n; j++) {\n\n for (k = 0; k < m; k++) {\n\n assert(output[i][j][k] == '*');\n\n }\n\n }\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\nmov %esi,%r14d\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %edi,%ebx\nmovslq %edx,%rdi\nmov %rdi,%rbp\nshl $0x3,%rdi\nsub $0x28,%rsp\nmov %esi,0x14(%rsp)\ncallq 1070 \nmov %rax,0x18(%rsp)\ntest %ebp,%ebp\njle 1517 \nmovslq %r14d,%r15\nmov %rax,%r14\nmovslq %ebx,%r12\nlea 0x0(,%r15,8),%rdi\nmov %rdi,(%rsp)\nmov %rax,%rdi\nlea -0x1(%rbp),%eax\nlea -0x1(%r15),%ebp\nlea 0x8(%rdi,%rax,8),%rax\nshl $0x3,%rbp\nmov %rax,0x8(%rsp)\nlea -0x2(%rbx),%eax\nmov %eax,0x10(%rsp)\nnopl 0x0(%rax,%rax,1)\nmov (%rsp),%rdi\ncallq 1070 \nmov %rax,(%r14)\nmov %rax,%r13\nmov 0x14(%rsp),%eax\ntest %eax,%eax\njle 1508 \nxor %r15d,%r15d\nnopw 0x0(%rax,%rax,1)\nmov %r12,%rdi\ncallq 1070 \nmov %rax,0x0(%r13,%r15,1)\ntest %ebx,%ebx\njle 14f4 \nmovb $0x2a,(%rax)\ncmp $0x1,%ebx\nje 14f4 \nmov 0x10(%rsp),%esi\nmov $0x1,%eax\nadd $0x2,%rsi\nnopw %cs:0x0(%rax,%rax,1)\nmov (%r14),%rdx\nmov (%rdx,%r15,1),%rdx\nmovb $0x2a,(%rdx,%rax,1)\nadd $0x1,%rax\ncmp %rax,%rsi\njne 14e0 \ncmp %r15,%rbp\nje 1508 \nmov (%r14),%r13\nadd $0x8,%r15\njmp 14b0 \nnopw 0x0(%rax,%rax,1)\nadd $0x8,%r14\ncmp %r14,0x8(%rsp)\njne 1490 \nmov 0x18(%rsp),%rax\nadd $0x28,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14d, esi\npush r13\npush r12\npush rbp\nmovsxd rbp, edx\npush rbx\nmov r12, rbp\nshl rbp, 3\nmov ebx, edi\nmov rdi, rbp; size\nsub rsp, 28h\nmov [rsp+58h+var_44], esi\ncall _malloc\nmov [rsp+58h+var_40], rax\ntest r12d, r12d\njle short loc_14F6\nmovsxd r15, r14d\nmov r14, rax\nadd rax, rbp\nmovsxd r12, ebx\nlea rcx, ds:0[r15*8]\nmov [rsp+58h+var_50], rax\nmov [rsp+58h+size], rcx\nnop dword ptr [rax+00h]\nloc_1498:\nmov rbp, [rsp+58h+size]\nmov r13d, ebx\nmov rdi, rbp; size\ncall _malloc\nmov [r14], rax\nmov r15, rax\nadd rbp, rax\nmov eax, [rsp+58h+var_44]\ntest eax, eax\njle short loc_14E8\nnop dword ptr [rax+rax+00000000h]\nloc_14C0:\nmov rdi, r12; size\ncall _malloc\nmov [r15], rax\nmov rdi, rax; s\ntest ebx, ebx\njle short loc_14DF\nmov rdx, r13; n\nmov esi, 2Ah ; '*'; c\ncall _memset\nloc_14DF:\nadd r15, 8\ncmp rbp, r15\njnz short loc_14C0\nloc_14E8:\nmov rax, [rsp+58h+var_50]\nadd r14, 8\ncmp r14, rax\njnz short loc_1498\nloc_14F6:\nmov rax, [rsp+58h+var_40]\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(size_t n, int a2, int a3)\n{\n size_t v4; // rbp\n _QWORD *v5; // rax\n _QWORD *v6; // r14\n _QWORD *v7; // rax\n _QWORD *v8; // r15\n _QWORD *v9; // rbp\n void *v10; // rax\n __int64 size; // [rsp+0h] [rbp-58h]\n _QWORD *v13; // [rsp+8h] [rbp-50h]\n _QWORD *v14; // [rsp+18h] [rbp-40h]\n\n v4 = a3;\n v5 = malloc(v4 * 8);\n v14 = v5;\n if ( a3 > 0 )\n {\n v6 = v5;\n v13 = &v5[v4];\n size = a2;\n do\n {\n v7 = malloc(size * 8);\n *v6 = v7;\n v8 = v7;\n v9 = &v7[size];\n if ( a2 > 0 )\n {\n do\n {\n v10 = malloc((int)n);\n *v8 = v10;\n if ( (int)n > 0 )\n memset(v10, 42, (unsigned int)n);\n ++v8;\n }\n while ( v9 != v8 );\n }\n ++v6;\n }\n while ( v6 != v13 );\n }\n return v14;\n}", + "ida_strip_asm": "sub_1440:\nendbr64\npush r15\npush r14\nmov r14d, esi\npush r13\npush r12\npush rbp\nmovsxd rbp, edx\npush rbx\nmov r12, rbp\nshl rbp, 3\nmov ebx, edi\nmov rdi, rbp; size\nsub rsp, 28h\nmov [rsp+58h+var_44], esi\ncall _malloc\nmov [rsp+58h+var_40], rax\ntest r12d, r12d\njle short loc_14F6\nmovsxd r15, r14d\nmov r14, rax\nadd rax, rbp\nmovsxd r12, ebx\nlea rcx, ds:0[r15*8]\nmov [rsp+58h+var_50], rax\nmov [rsp+58h+size], rcx\nnop dword ptr [rax+00h]\nloc_1498:\nmov rbp, [rsp+58h+size]\nmov r13d, ebx\nmov rdi, rbp; size\ncall _malloc\nmov [r14], rax\nmov r15, rax\nadd rbp, rax\nmov eax, [rsp+58h+var_44]\ntest eax, eax\njle short loc_14E8\nnop dword ptr [rax+rax+00000000h]\nloc_14C0:\nmov rdi, r12; size\ncall _malloc\nmov [r15], rax\nmov rdi, rax; s\ntest ebx, ebx\njle short loc_14DF\nmov rdx, r13; n\nmov esi, 2Ah ; '*'; c\ncall _memset\nloc_14DF:\nadd r15, 8\ncmp rbp, r15\njnz short loc_14C0\nloc_14E8:\nmov rax, [rsp+58h+var_50]\nadd r14, 8\ncmp r14, rax\njnz short loc_1498\nloc_14F6:\nmov rax, [rsp+58h+var_40]\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1440(size_t n, int a2, int a3)\n{\n size_t v4; // rbp\n _QWORD *v5; // rax\n _QWORD *v6; // r14\n _QWORD *v7; // rax\n _QWORD *v8; // r15\n _QWORD *v9; // rbp\n void *v10; // rax\n __int64 size; // [rsp+0h] [rbp-58h]\n _QWORD *v13; // [rsp+8h] [rbp-50h]\n _QWORD *v14; // [rsp+18h] [rbp-40h]\n\n v4 = a3;\n v5 = malloc(v4 * 8);\n v14 = v5;\n if ( a3 > 0 )\n {\n v6 = v5;\n v13 = &v5[v4];\n size = a2;\n do\n {\n v7 = malloc(size * 8);\n *v6 = v7;\n v8 = v7;\n v9 = &v7[size];\n if ( a2 > 0 )\n {\n do\n {\n v10 = malloc((int)n);\n *v8 = v10;\n if ( (int)n > 0 )\n memset(v10, 42, (unsigned int)n);\n ++v8;\n }\n while ( v9 != v8 );\n }\n ++v6;\n }\n while ( v6 != v13 );\n }\n return v14;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1440(unsigned int n, int a2, int a3) {\n unsigned int v4;\n uint64_t *v5;\n uint64_t *v6;\n uint64_t *v7;\n uint64_t *v8;\n uint64_t *v9;\n void *v10;\n long long size;\n uint64_t *v13;\n uint64_t *v14;\n v4 = a3;\n v5 = malloc(v4 * 8);\n v14 = v5;\n if (a3 > 0) {\n v6 = v5;\n v13 = &v5[v4];\n size = a2;\n do {\n v7 = malloc(size * 8);\n *v6 = v7;\n v8 = v7;\n v9 = &v7[size];\n if (a2 > 0) {\n do {\n v10 = malloc((int)n);\n *v8 = v10;\n if ((int)n > 0) memset(v10, 42, (unsigned int)n);\n ++v8;\n } while (v9 != v8);\n }\n ++v6;\n } while (v6 != v13);\n }\n return v14;\n}", + "ida_pseudo_norm": "uint64_t *func0(unsigned int n, int a2, int a3) {\n unsigned int v4;\n uint64_t *v5;\n uint64_t *v6;\n uint64_t *v7;\n uint64_t *v8;\n uint64_t *v9;\n void *v10;\n long long size;\n uint64_t *v13;\n uint64_t *v14;\n v4 = a3;\n v5 = malloc(v4 * 8);\n v14 = v5;\n if (a3 > 0) {\n v6 = v5;\n v13 = &v5[v4];\n size = a2;\n do {\n v7 = malloc(size * 8);\n *v6 = v7;\n v8 = v7;\n v9 = &v7[size];\n if (a2 > 0) {\n do {\n v10 = malloc((int)n);\n *v8 = v10;\n if ((int)n > 0) memset(v10, 42, (unsigned int)n);\n ++v8;\n } while (v9 != v8);\n }\n ++v6;\n } while (v6 != v13);\n }\n return v14;\n}" + }, + { + "index": 242, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *str1) {\n int total = 0;\n while (*str1) {\n total++;\n str1++;\n }\n return total;\n}", + "test": "int main() {\n\n assert(func0(\"python programming\") == 18);\n\n assert(func0(\"language\") == 8);\n\n assert(func0(\"words\") == 5);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 1167 \naddl $0x1,-0x4(%rbp)\naddq $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 115e \nmov -0x4(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_4], 0\njmp short loc_1167\nloc_115E:\nadd [rbp+var_4], 1\nadd [rbp+var_18], 1\nloc_1167:\nmov rax, [rbp+var_18]\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_115E\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(_BYTE *a1)\n{\n unsigned int v3; // [rsp+14h] [rbp-4h]\n\n v3 = 0;\n while ( *a1 )\n {\n ++v3;\n ++a1;\n }\n return v3;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_4], 0\njmp short loc_1167\nloc_115E:\nadd [rbp+var_4], 1\nadd [rbp+var_18], 1\nloc_1167:\nmov rax, [rbp+var_18]\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_115E\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(_BYTE *a1)\n{\n unsigned int v3; // [rsp+14h] [rbp-4h]\n\n v3 = 0;\n while ( *a1 )\n {\n ++v3;\n ++a1;\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(uint8_t *a1) {\n unsigned int v3;\n v3 = 0;\n while (*a1) {\n ++v3;\n ++a1;\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(uint8_t *a1) {\n unsigned int v3;\n v3 = 0;\n while (*a1) {\n ++v3;\n ++a1;\n }\n return v3;\n}" + }, + { + "index": 242, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *str1) {\n int total = 0;\n while (*str1) {\n total++;\n str1++;\n }\n return total;\n}", + "test": "int main() {\n\n assert(func0(\"python programming\") == 18);\n\n assert(func0(\"language\") == 8);\n\n assert(func0(\"words\") == 5);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ncmpb $0x0,(%rdi)\nje 116b \nmov %rdi,%rax\nmov $0x1,%edx\nsub %edi,%edx\nlea (%rdx,%rax,1),%ecx\nadd $0x1,%rax\ncmpb $0x0,(%rax)\njne 115c \nmov %ecx,%eax\nretq\nmov $0x0,%ecx\njmp 1168 \n", + "ida_asm": "func0:\nendbr64\ncmp byte ptr [rdi], 0\njz short loc_1167\nmov rax, rdi\nloc_1155:\nmov rdx, rax\nadd rax, 1\ncmp byte ptr [rax], 0\njnz short loc_1155\nsub edx, edi\nlea eax, [rdx+1]\nretn\nloc_1167:\nmov eax, 0\nretn", + "ida_pseudo": "__int64 __fastcall func0(_BYTE *a1)\n{\n _BYTE *v1; // rax\n int v2; // edx\n\n if ( !*a1 )\n return 0LL;\n v1 = a1;\n do\n v2 = (int)v1++;\n while ( *v1 );\n return (unsigned int)(v2 - (_DWORD)a1 + 1);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ncmp byte ptr [rdi], 0\njz short loc_1167\nmov rax, rdi\nloc_1155:\nmov rdx, rax\nadd rax, 1\ncmp byte ptr [rax], 0\njnz short loc_1155\nsub edx, edi\nlea eax, [rdx+1]\nretn\nloc_1167:\nmov eax, 0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(_BYTE *a1)\n{\n _BYTE *v1; // rax\n int v2; // edx\n\n if ( !*a1 )\n return 0LL;\n v1 = a1;\n do\n v2 = (int)v1++;\n while ( *v1 );\n return (unsigned int)(v2 - (_DWORD)a1 + 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(uint8_t *a1) {\n uint8_t *v1;\n int v2;\n if (!*a1) return 0LL;\n v1 = a1;\n do\n v2 = (int)v1++;\n while (*v1);\n return (unsigned int)(v2 - (uint32_t)a1 + 1);\n}", + "ida_pseudo_norm": "long long func0(uint8_t *a1) {\n uint8_t *v1;\n int v2;\n if (!*a1) return 0LL;\n v1 = a1;\n do\n v2 = (int)v1++;\n while (*v1);\n return (unsigned int)(v2 - (uint32_t)a1 + 1);\n}" + }, + { + "index": 243, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char *key;\n\n char **values;\n\n int values_size;\n\n int num_values;\n\n} DictItem;\n\n\n\nDictItem *find_or_create(DictItem **dict, int *size, char *key) {\n\n for (int i = 0; i < *size; i++) {\n\n if (strcmp(dict[i]->key, key) == 0) {\n\n return dict[i];\n\n }\n\n }\n\n\n\n DictItem *item = malloc(sizeof(DictItem));\n\n item->key = strdup(key);\n\n item->values = malloc(sizeof(char*) * 10);\n\n item->values_size = 10;\n\n item->num_values = 0;\n\n\n\n dict[*size] = item;\n\n (*size)++;\n\n return item;\n\n}\n\n\n\nvoid add_value(DictItem *item, char *value) {\n\n for (int i = 0; i < item->num_values; i++) {\n\n if (strcmp(item->values[i], value) == 0) {\n\n return;\n\n }\n\n }\n\n if (item->num_values == item->values_size) {\n\n item->values_size += 10;\n\n item->values = realloc(item->values, item->values_size * sizeof(char *));\n\n }\n\n item->values[item->num_values] = strdup(value);\n\n item->num_values++;\n\n}\n\n\n\n", + "func": "DictItem **func0(char *lst[], int lst_size) {\n DictItem **dict = malloc(sizeof(DictItem *) * 10);\n int dict_size = 0;\n for (int i = 0; i < lst_size; i += 2) {\n char *key = lst[i];\n char *value = lst[i + 1];\n DictItem *item = find_or_create(dict, &dict_size, key);\n add_value(item, value);\n }\n return dict;\n}", + "test": "int main(void) {\n\n char *test1[] = { \"1\", \"Jake\", \"2\", \"Bob\", \"1\", \"Cara\" };\n\n DictItem **res1 = func0(test1, 6);\n\n assert(res1[0]->num_values == 2);\n\n assert(res1[1]->num_values == 1);\n\n \n\n char *test2[] = { \"b\", \"ball\", \"a\", \"arm\", \"b\", \"b\", \"a\", \"ant\" };\n\n DictItem **res2 = func0(test2, 8);\n\n assert(res2[0]->num_values == 2);\n\n assert(res2[1]->num_values == 2);\n\n \n\n char *test3[] = { \"2\", \"Mark\", \"3\", \"Maze\", \"2\", \"Sara\" };\n\n DictItem **res3 = func0(test3, 6);\n\n assert(res3[0]->num_values == 2);\n\n assert(res3[1]->num_values == 1);\n\n \n\n printf(\"All test cases passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x40,%rsp\nmov %rdi,-0x38(%rbp)\nmov %esi,-0x3c(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmov $0x50,%edi\ncallq 10f0 \nmov %rax,-0x28(%rbp)\nmovl $0x0,-0x30(%rbp)\nmovl $0x0,-0x2c(%rbp)\njmp 149f \nmov -0x2c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov %rax,-0x20(%rbp)\nmov -0x2c(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,8),%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov %rax,-0x18(%rbp)\nmov -0x20(%rbp),%rdx\nlea -0x30(%rbp),%rcx\nmov -0x28(%rbp),%rax\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 1209 \nmov %rax,-0x10(%rbp)\nmov -0x18(%rbp),%rdx\nmov -0x10(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1304 \naddl $0x2,-0x2c(%rbp)\nmov -0x2c(%rbp),%eax\ncmp -0x3c(%rbp),%eax\njl 1433 \nmov -0x28(%rbp),%rax\nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 14bf \ncallq 10c0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov edi, 50h ; 'P'; size\ncall _malloc\nmov [rbp+var_28], rax\nmov [rbp+var_30], 0\nmov [rbp+var_2C], 0\njmp short loc_149E\nloc_1432:\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nmov [rbp+var_20], rax\nmov eax, [rbp+var_2C]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nmov [rbp+var_18], rax\nmov rdx, [rbp+var_20]\nlea rcx, [rbp+var_30]\nmov rax, [rbp+var_28]\nmov rsi, rcx\nmov rdi, rax\ncall find_or_create\nmov [rbp+var_10], rax\nmov rdx, [rbp+var_18]\nmov rax, [rbp+var_10]\nmov rsi, rdx\nmov rdi, rax\ncall add_value\nadd [rbp+var_2C], 2\nloc_149E:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_3C]\njl short loc_1432\nmov rax, [rbp+var_28]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_14BE\ncall ___stack_chk_fail\nlocret_14BE:\nleave\nretn", + "ida_pseudo": "void *__fastcall func0(__int64 a1, int a2)\n{\n int v3; // [rsp+10h] [rbp-30h] BYREF\n int i; // [rsp+14h] [rbp-2Ch]\n void *v5; // [rsp+18h] [rbp-28h]\n __int64 v6; // [rsp+20h] [rbp-20h]\n __int64 v7; // [rsp+28h] [rbp-18h]\n __int64 v8; // [rsp+30h] [rbp-10h]\n unsigned __int64 v9; // [rsp+38h] [rbp-8h]\n\n v9 = __readfsqword(0x28u);\n v5 = malloc(0x50uLL);\n v3 = 0;\n for ( i = 0; i < a2; i += 2 )\n {\n v6 = *(_QWORD *)(8LL * i + a1);\n v7 = *(_QWORD *)(8 * (i + 1LL) + a1);\n v8 = find_or_create(v5, &v3, v6);\n add_value(v8, v7);\n }\n return v5;\n}", + "ida_strip_asm": "sub_13F2:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov edi, 50h ; 'P'; size\ncall _malloc\nmov [rbp+var_28], rax\nmov [rbp+var_30], 0\nmov [rbp+var_2C], 0\njmp short loc_149E\nloc_1432:\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nmov [rbp+var_20], rax\nmov eax, [rbp+var_2C]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nmov [rbp+var_18], rax\nmov rdx, [rbp+var_20]\nlea rcx, [rbp+var_30]\nmov rax, [rbp+var_28]\nmov rsi, rcx\nmov rdi, rax\ncall sub_1209\nmov [rbp+var_10], rax\nmov rdx, [rbp+var_18]\nmov rax, [rbp+var_10]\nmov rsi, rdx\nmov rdi, rax\ncall sub_1304\nadd [rbp+var_2C], 2\nloc_149E:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_3C]\njl short loc_1432\nmov rax, [rbp+var_28]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_14BE\ncall ___stack_chk_fail\nlocret_14BE:\nleave\nretn", + "ida_strip_pseudo": "void *__fastcall sub_13F2(__int64 a1, int a2)\n{\n int v3; // [rsp+10h] [rbp-30h] BYREF\n int i; // [rsp+14h] [rbp-2Ch]\n void *v5; // [rsp+18h] [rbp-28h]\n __int64 v6; // [rsp+20h] [rbp-20h]\n __int64 v7; // [rsp+28h] [rbp-18h]\n __int64 v8; // [rsp+30h] [rbp-10h]\n unsigned __int64 v9; // [rsp+38h] [rbp-8h]\n\n v9 = __readfsqword(0x28u);\n v5 = malloc(0x50uLL);\n v3 = 0;\n for ( i = 0; i < a2; i += 2 )\n {\n v6 = *(_QWORD *)(8LL * i + a1);\n v7 = *(_QWORD *)(8 * (i + 1LL) + a1);\n v8 = sub_1209(v5, &v3, v6);\n sub_1304(v8, v7);\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_13F2(long long a1, int a2) {\n int v3;\n int i;\n void *v5;\n long long v6;\n long long v7;\n long long v8;\n unsigned long long v9;\n v9 = __readfsqword(40u);\n v5 = malloc(80uLL);\n v3 = 0;\n for (i = 0; i < a2; i += 2) {\n v6 = *(uint64_t *)(8LL * i + a1);\n v7 = *(uint64_t *)(8 * (i + 1LL) + a1);\n v8 = sub_1209(v5, &v3, v6);\n sub_1304(v8, v7);\n }\n return v5;\n}", + "ida_pseudo_norm": "void *func0(long long a1, int a2) {\n int v3;\n int i;\n void *v5;\n long long v6;\n long long v7;\n long long v8;\n unsigned long long v9;\n v9 = __readfsqword(40u);\n v5 = malloc(80uLL);\n v3 = 0;\n for (i = 0; i < a2; i += 2) {\n v6 = *(uint64_t *)(8LL * i + a1);\n v7 = *(uint64_t *)(8 * (i + 1LL) + a1);\n v8 = find_or_create(v5, &v3, v6);\n add_value(v8, v7);\n }\n return v5;\n}" + }, + { + "index": 243, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char *key;\n\n char **values;\n\n int values_size;\n\n int num_values;\n\n} DictItem;\n\n\n\nDictItem *find_or_create(DictItem **dict, int *size, char *key) {\n\n for (int i = 0; i < *size; i++) {\n\n if (strcmp(dict[i]->key, key) == 0) {\n\n return dict[i];\n\n }\n\n }\n\n\n\n DictItem *item = malloc(sizeof(DictItem));\n\n item->key = strdup(key);\n\n item->values = malloc(sizeof(char*) * 10);\n\n item->values_size = 10;\n\n item->num_values = 0;\n\n\n\n dict[*size] = item;\n\n (*size)++;\n\n return item;\n\n}\n\n\n\nvoid add_value(DictItem *item, char *value) {\n\n for (int i = 0; i < item->num_values; i++) {\n\n if (strcmp(item->values[i], value) == 0) {\n\n return;\n\n }\n\n }\n\n if (item->num_values == item->values_size) {\n\n item->values_size += 10;\n\n item->values = realloc(item->values, item->values_size * sizeof(char *));\n\n }\n\n item->values[item->num_values] = strdup(value);\n\n item->num_values++;\n\n}\n\n\n\n", + "func": "DictItem **func0(char *lst[], int lst_size) {\n DictItem **dict = malloc(sizeof(DictItem *) * 10);\n int dict_size = 0;\n for (int i = 0; i < lst_size; i += 2) {\n char *key = lst[i];\n char *value = lst[i + 1];\n DictItem *item = find_or_create(dict, &dict_size, key);\n add_value(item, value);\n }\n return dict;\n}", + "test": "int main(void) {\n\n char *test1[] = { \"1\", \"Jake\", \"2\", \"Bob\", \"1\", \"Cara\" };\n\n DictItem **res1 = func0(test1, 6);\n\n assert(res1[0]->num_values == 2);\n\n assert(res1[1]->num_values == 1);\n\n \n\n char *test2[] = { \"b\", \"ball\", \"a\", \"arm\", \"b\", \"b\", \"a\", \"ant\" };\n\n DictItem **res2 = func0(test2, 8);\n\n assert(res2[0]->num_values == 2);\n\n assert(res2[1]->num_values == 2);\n\n \n\n char *test3[] = { \"2\", \"Mark\", \"3\", \"Maze\", \"2\", \"Sara\" };\n\n DictItem **res3 = func0(test3, 6);\n\n assert(res3[0]->num_values == 2);\n\n assert(res3[1]->num_values == 1);\n\n \n\n printf(\"All test cases passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x10,%rsp\nmov %rdi,%r13\nmov %esi,%ebp\nmov %fs:0x28,%rax\nmov %rax,0x8(%rsp)\nxor %eax,%eax\nmov $0x50,%edi\ncallq 10f0 \nmov %rax,%r12\nmovl $0x0,0x4(%rsp)\ntest %ebp,%ebp\njle 13ad \nmov %r13,%rbx\nsub $0x1,%ebp\nshr %ebp\nmov %ebp,%ebp\nshl $0x4,%rbp\nlea 0x10(%r13,%rbp,1),%r14\nlea 0x4(%rsp),%r13\nmov 0x8(%rbx),%rbp\nmov (%rbx),%rdx\nmov %r13,%rsi\nmov %r12,%rdi\ncallq 1209 \nmov %rax,%rdi\nmov %rbp,%rsi\ncallq 12a3 \nadd $0x10,%rbx\ncmp %r14,%rbx\njne 1387 \nmov 0x8(%rsp),%rax\nxor %fs:0x28,%rax\njne 13cd \nmov %r12,%rax\nadd $0x10,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\ncallq 10c0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 10h\nmov r13, rdi\nmov ebp, esi\nmov rax, fs:28h\nmov [rsp+38h+var_30], rax\nxor eax, eax\nmov edi, 50h ; 'P'; size\ncall _malloc\nmov r12, rax\nmov [rsp+38h+var_34], 0\ntest ebp, ebp\njle short loc_13A9\nmov rbx, r13\nsub ebp, 1\nshr ebp, 1\nmov ebp, ebp\nshl rbp, 4\nlea r14, [r13+rbp+10h]\nlea r13, [rsp+38h+var_34]\nloc_1383:\nmov rbp, [rbx+8]\nmov rdx, [rbx]\nmov rsi, r13\nmov rdi, r12\ncall find_or_create\nmov rdi, rax\nmov rsi, rbp\ncall add_value\nadd rbx, 10h\ncmp rbx, r14\njnz short loc_1383\nloc_13A9:\nmov rax, [rsp+38h+var_30]\nsub rax, fs:28h\njnz short loc_13C9\nmov rax, r12\nadd rsp, 10h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_13C9:\ncall ___stack_chk_fail", + "ida_pseudo": "void *__fastcall func0(_QWORD *a1, int a2)\n{\n void *v2; // r12\n _QWORD *v3; // rbx\n __int64 v4; // rbp\n __int64 v5; // rax\n int v7; // [rsp+4h] [rbp-34h] BYREF\n unsigned __int64 v8; // [rsp+8h] [rbp-30h]\n\n v8 = __readfsqword(0x28u);\n v2 = malloc(0x50uLL);\n v7 = 0;\n if ( a2 > 0 )\n {\n v3 = a1;\n do\n {\n v4 = v3[1];\n v5 = find_or_create(v2, &v7, *v3);\n add_value(v5, v4);\n v3 += 2;\n }\n while ( v3 != &a1[2 * ((unsigned int)(a2 - 1) >> 1) + 2] );\n }\n return v2;\n}", + "ida_strip_asm": "sub_132D:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 10h\nmov r13, rdi\nmov ebp, esi\nmov rax, fs:28h\nmov [rsp+38h+var_30], rax\nxor eax, eax\nmov edi, 50h ; 'P'; size\ncall _malloc\nmov r12, rax\nmov [rsp+38h+var_34], 0\ntest ebp, ebp\njle short loc_13A9\nmov rbx, r13\nsub ebp, 1\nshr ebp, 1\nmov ebp, ebp\nshl rbp, 4\nlea r14, [r13+rbp+10h]\nlea r13, [rsp+38h+var_34]\nloc_1383:\nmov rbp, [rbx+8]\nmov rdx, [rbx]\nmov rsi, r13\nmov rdi, r12\ncall sub_1209\nmov rdi, rax\nmov rsi, rbp\ncall sub_12A1\nadd rbx, 10h\ncmp rbx, r14\njnz short loc_1383\nloc_13A9:\nmov rax, [rsp+38h+var_30]\nsub rax, fs:28h\njnz short loc_13C9\nmov rax, r12\nadd rsp, 10h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_13C9:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "void *__fastcall sub_132D(_QWORD *a1, int a2)\n{\n void *v2; // r12\n _QWORD *v3; // rbx\n __int64 v4; // rbp\n __int64 v5; // rax\n int v7; // [rsp+4h] [rbp-34h] BYREF\n unsigned __int64 v8; // [rsp+8h] [rbp-30h]\n\n v8 = __readfsqword(0x28u);\n v2 = malloc(0x50uLL);\n v7 = 0;\n if ( a2 > 0 )\n {\n v3 = a1;\n do\n {\n v4 = v3[1];\n v5 = sub_1209(v2, &v7, *v3);\n sub_12A1(v5, v4);\n v3 += 2;\n }\n while ( v3 != &a1[2 * ((unsigned int)(a2 - 1) >> 1) + 2] );\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_132D(uint64_t *a1, int a2) {\n void *v2;\n uint64_t *v3;\n long long v4;\n long long v5;\n int v7;\n unsigned long long v8;\n v8 = __readfsqword(40u);\n v2 = malloc(80uLL);\n v7 = 0;\n if (a2 > 0) {\n v3 = a1;\n do {\n v4 = v3[1];\n v5 = sub_1209(v2, &v7, *v3);\n sub_12A1(v5, v4);\n v3 += 2;\n } while (v3 != &a1[2 * ((unsigned int)(a2 - 1) >> 1) + 2]);\n }\n return v2;\n}", + "ida_pseudo_norm": "void *func0(uint64_t *a1, int a2) {\n void *v2;\n uint64_t *v3;\n long long v4;\n long long v5;\n int v7;\n unsigned long long v8;\n v8 = __readfsqword(40u);\n v2 = malloc(80uLL);\n v7 = 0;\n if (a2 > 0) {\n v3 = a1;\n do {\n v4 = v3[1];\n v5 = find_or_create(v2, &v7, *v3);\n add_value(v5, v4);\n v3 += 2;\n } while (v3 != &a1[2 * ((unsigned int)(a2 - 1) >> 1) + 2]);\n }\n return v2;\n}" + }, + { + "index": 243, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char *key;\n\n char **values;\n\n int values_size;\n\n int num_values;\n\n} DictItem;\n\n\n\nDictItem *find_or_create(DictItem **dict, int *size, char *key) {\n\n for (int i = 0; i < *size; i++) {\n\n if (strcmp(dict[i]->key, key) == 0) {\n\n return dict[i];\n\n }\n\n }\n\n\n\n DictItem *item = malloc(sizeof(DictItem));\n\n item->key = strdup(key);\n\n item->values = malloc(sizeof(char*) * 10);\n\n item->values_size = 10;\n\n item->num_values = 0;\n\n\n\n dict[*size] = item;\n\n (*size)++;\n\n return item;\n\n}\n\n\n\nvoid add_value(DictItem *item, char *value) {\n\n for (int i = 0; i < item->num_values; i++) {\n\n if (strcmp(item->values[i], value) == 0) {\n\n return;\n\n }\n\n }\n\n if (item->num_values == item->values_size) {\n\n item->values_size += 10;\n\n item->values = realloc(item->values, item->values_size * sizeof(char *));\n\n }\n\n item->values[item->num_values] = strdup(value);\n\n item->num_values++;\n\n}\n\n\n\n", + "func": "DictItem **func0(char *lst[], int lst_size) {\n DictItem **dict = malloc(sizeof(DictItem *) * 10);\n int dict_size = 0;\n for (int i = 0; i < lst_size; i += 2) {\n char *key = lst[i];\n char *value = lst[i + 1];\n DictItem *item = find_or_create(dict, &dict_size, key);\n add_value(item, value);\n }\n return dict;\n}", + "test": "int main(void) {\n\n char *test1[] = { \"1\", \"Jake\", \"2\", \"Bob\", \"1\", \"Cara\" };\n\n DictItem **res1 = func0(test1, 6);\n\n assert(res1[0]->num_values == 2);\n\n assert(res1[1]->num_values == 1);\n\n \n\n char *test2[] = { \"b\", \"ball\", \"a\", \"arm\", \"b\", \"b\", \"a\", \"ant\" };\n\n DictItem **res2 = func0(test2, 8);\n\n assert(res2[0]->num_values == 2);\n\n assert(res2[1]->num_values == 2);\n\n \n\n char *test3[] = { \"2\", \"Mark\", \"3\", \"Maze\", \"2\", \"Sara\" };\n\n DictItem **res3 = func0(test3, 6);\n\n assert(res3[0]->num_values == 2);\n\n assert(res3[1]->num_values == 1);\n\n \n\n printf(\"All test cases passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\nmov %esi,%ebp\npush %rbx\nmov %rdi,%rbx\nmov $0x50,%edi\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x8(%rsp)\nxor %eax,%eax\ncallq 10f0 \nmovl $0x0,0x4(%rsp)\nmov %rax,%r14\ntest %ebp,%ebp\njle 164e \nsub $0x1,%ebp\nlea 0x4(%rsp),%r12\nshr %ebp\nshl $0x4,%rbp\nlea 0x10(%rbx,%rbp,1),%r13\nnopl 0x0(%rax)\nmov (%rbx),%rdx\nmov 0x8(%rbx),%rbp\nmov %r12,%rsi\nmov %r14,%rdi\nadd $0x10,%rbx\ncallq 1460 \nmov %rbp,%rsi\nmov %rax,%rdi\ncallq 1510 \ncmp %r13,%rbx\njne 1628 \nmov 0x8(%rsp),%rax\nxor %fs:0x28,%rax\njne 166e \nadd $0x10,%rsp\nmov %r14,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\ncallq 10c0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\nmov ebp, esi\npush rbx\nmov rbx, rdi\nmov edi, 50h ; 'P'; size\nsub rsp, 10h\nmov rax, fs:28h\nmov [rsp+38h+var_30], rax\nxor eax, eax\ncall _malloc\nmov [rsp+38h+var_34], 0\nmov r12, rax\ntest ebp, ebp\njle short loc_16FE\nsub ebp, 1\nlea r13, [rsp+38h+var_34]\nshr ebp, 1\nshl rbp, 4\nlea r14, [rbx+rbp+10h]\nnop dword ptr [rax+00000000h]\nloc_16D8:\nmov rdx, [rbx]\nmov rbp, [rbx+8]\nmov rsi, r13\nmov rdi, r12\nadd rbx, 10h\ncall find_or_create\nmov rsi, rbp\nmov rdi, rax\ncall add_value\ncmp rbx, r14\njnz short loc_16D8\nloc_16FE:\nmov rax, [rsp+38h+var_30]\nsub rax, fs:28h\njnz short loc_171E\nadd rsp, 10h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_171E:\ncall ___stack_chk_fail", + "ida_pseudo": "void *__fastcall func0(__int64 *a1, int a2)\n{\n __int64 *v2; // rbx\n void *v3; // r12\n __int64 v4; // rdx\n __int64 v5; // rbp\n __int64 v6; // rax\n int v8; // [rsp+4h] [rbp-34h] BYREF\n unsigned __int64 v9; // [rsp+8h] [rbp-30h]\n\n v2 = a1;\n v9 = __readfsqword(0x28u);\n v8 = 0;\n v3 = malloc(0x50uLL);\n if ( a2 > 0 )\n {\n do\n {\n v4 = *v2;\n v5 = v2[1];\n v2 += 2;\n v6 = find_or_create(v3, &v8, v4);\n add_value(v6, v5);\n }\n while ( v2 != &a1[2 * ((unsigned int)(a2 - 1) >> 1) + 2] );\n }\n return v3;\n}", + "ida_strip_asm": "sub_1680:\nendbr64\npush r14\npush r13\npush r12\npush rbp\nmov ebp, esi\npush rbx\nmov rbx, rdi\nmov edi, 50h ; 'P'; size\nsub rsp, 10h\nmov rax, fs:28h\nmov [rsp+38h+var_30], rax\nxor eax, eax\ncall _malloc\nmov [rsp+38h+var_34], 0\nmov r12, rax\ntest ebp, ebp\njle short loc_16FE\nsub ebp, 1\nlea r13, [rsp+38h+var_34]\nshr ebp, 1\nshl rbp, 4\nlea r14, [rbx+rbp+10h]\nnop dword ptr [rax+00000000h]\nloc_16D8:\nmov rdx, [rbx]\nmov rbp, [rbx+8]\nmov rsi, r13\nmov rdi, r12\nadd rbx, 10h\ncall sub_1510\nmov rsi, rbp\nmov rdi, rax\ncall sub_15C0\ncmp rbx, r14\njnz short loc_16D8\nloc_16FE:\nmov rax, [rsp+38h+var_30]\nsub rax, fs:28h\njnz short loc_171E\nadd rsp, 10h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_171E:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "void *__fastcall sub_1680(__int64 *a1, int a2)\n{\n __int64 *v2; // rbx\n void *v3; // r12\n __int64 v4; // rdx\n __int64 v5; // rbp\n __int64 v6; // rax\n int v8; // [rsp+4h] [rbp-34h] BYREF\n unsigned __int64 v9; // [rsp+8h] [rbp-30h]\n\n v2 = a1;\n v9 = __readfsqword(0x28u);\n v8 = 0;\n v3 = malloc(0x50uLL);\n if ( a2 > 0 )\n {\n do\n {\n v4 = *v2;\n v5 = v2[1];\n v2 += 2;\n v6 = sub_1510(v3, &v8, v4);\n sub_15C0(v6, v5);\n }\n while ( v2 != &a1[2 * ((unsigned int)(a2 - 1) >> 1) + 2] );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1680(long long *a1, int a2) {\n long long *v2;\n void *v3;\n long long v4;\n long long v5;\n long long v6;\n int v8;\n unsigned long long v9;\n v2 = a1;\n v9 = __readfsqword(40u);\n v8 = 0;\n v3 = malloc(80uLL);\n if (a2 > 0) {\n do {\n v4 = *v2;\n v5 = v2[1];\n v2 += 2;\n v6 = sub_1510(v3, &v8, v4);\n sub_15C0(v6, v5);\n } while (v2 != &a1[2 * ((unsigned int)(a2 - 1) >> 1) + 2]);\n }\n return v3;\n}", + "ida_pseudo_norm": "void *func0(long long *a1, int a2) {\n long long *v2;\n void *v3;\n long long v4;\n long long v5;\n long long v6;\n int v8;\n unsigned long long v9;\n v2 = a1;\n v9 = __readfsqword(40u);\n v8 = 0;\n v3 = malloc(80uLL);\n if (a2 > 0) {\n do {\n v4 = *v2;\n v5 = v2[1];\n v2 += 2;\n v6 = find_or_create(v3, &v8, v4);\n add_value(v6, v5);\n } while (v2 != &a1[2 * ((unsigned int)(a2 - 1) >> 1) + 2]);\n }\n return v3;\n}" + }, + { + "index": 243, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char *key;\n\n char **values;\n\n int values_size;\n\n int num_values;\n\n} DictItem;\n\n\n\nDictItem *find_or_create(DictItem **dict, int *size, char *key) {\n\n for (int i = 0; i < *size; i++) {\n\n if (strcmp(dict[i]->key, key) == 0) {\n\n return dict[i];\n\n }\n\n }\n\n\n\n DictItem *item = malloc(sizeof(DictItem));\n\n item->key = strdup(key);\n\n item->values = malloc(sizeof(char*) * 10);\n\n item->values_size = 10;\n\n item->num_values = 0;\n\n\n\n dict[*size] = item;\n\n (*size)++;\n\n return item;\n\n}\n\n\n\nvoid add_value(DictItem *item, char *value) {\n\n for (int i = 0; i < item->num_values; i++) {\n\n if (strcmp(item->values[i], value) == 0) {\n\n return;\n\n }\n\n }\n\n if (item->num_values == item->values_size) {\n\n item->values_size += 10;\n\n item->values = realloc(item->values, item->values_size * sizeof(char *));\n\n }\n\n item->values[item->num_values] = strdup(value);\n\n item->num_values++;\n\n}\n\n\n\n", + "func": "DictItem **func0(char *lst[], int lst_size) {\n DictItem **dict = malloc(sizeof(DictItem *) * 10);\n int dict_size = 0;\n for (int i = 0; i < lst_size; i += 2) {\n char *key = lst[i];\n char *value = lst[i + 1];\n DictItem *item = find_or_create(dict, &dict_size, key);\n add_value(item, value);\n }\n return dict;\n}", + "test": "int main(void) {\n\n char *test1[] = { \"1\", \"Jake\", \"2\", \"Bob\", \"1\", \"Cara\" };\n\n DictItem **res1 = func0(test1, 6);\n\n assert(res1[0]->num_values == 2);\n\n assert(res1[1]->num_values == 1);\n\n \n\n char *test2[] = { \"b\", \"ball\", \"a\", \"arm\", \"b\", \"b\", \"a\", \"ant\" };\n\n DictItem **res2 = func0(test2, 8);\n\n assert(res2[0]->num_values == 2);\n\n assert(res2[1]->num_values == 2);\n\n \n\n char *test3[] = { \"2\", \"Mark\", \"3\", \"Maze\", \"2\", \"Sara\" };\n\n DictItem **res3 = func0(test3, 6);\n\n assert(res3[0]->num_values == 2);\n\n assert(res3[1]->num_values == 1);\n\n \n\n printf(\"All test cases passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\nmov %esi,%ebp\npush %rbx\nmov %rdi,%rbx\nmov $0x50,%edi\nsub $0x28,%rsp\ncallq 10f0 \nmov %rax,0x10(%rsp)\ntest %ebp,%ebp\njle 170d \nsub $0x1,%ebp\nshr %ebp\nshl $0x4,%rbp\nlea 0x10(%rbx,%rbp,1),%rax\nxor %ebp,%ebp\nmov %rax,0x18(%rsp)\nnopl 0x0(%rax,%rax,1)\nmov (%rbx),%r12\nmov 0x8(%rbx),%r13\ntest %ebp,%ebp\nje 1728 \nmov 0x10(%rsp),%rdx\nlea -0x1(%rbp),%eax\nlea 0x8(%rdx,%rax,8),%rax\nmov %rdx,%r14\nmov %rax,(%rsp)\njmp 169e \nnopl (%rax)\nadd $0x8,%r14\ncmp %r14,(%rsp)\nje 1728 \nmov (%r14),%r15\nmov %r12,%rsi\nmov (%r15),%rdi\ncallq 10e0 \ntest %eax,%eax\njne 1690 \nmov 0x14(%r15),%r14d\nmov 0x8(%r15),%r12\ntest %r14d,%r14d\njle 17a0 \nlea -0x1(%r14),%eax\nmov %r12,%r9\nlea 0x8(%r12,%rax,8),%rax\nmov %rax,0x8(%rsp)\njmp 16eb \nnopl 0x0(%rax)\nmov (%rsp),%r9\nadd $0x8,%r9\ncmp %r9,0x8(%rsp)\nje 17a0 \nmov (%r9),%rdi\nmov %r13,%rsi\nmov %r9,(%rsp)\ncallq 10e0 \ntest %eax,%eax\njne 16d8 \nadd $0x10,%rbx\ncmp %rbx,0x18(%rsp)\njne 1668 \nmov 0x10(%rsp),%rax\nadd $0x28,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\nmov $0x18,%edi\nxor %r14d,%r14d\ncallq 10f0 \nmov %r12,%rdi\nmov %rax,%r15\ncallq 1110 \nmov $0x50,%edi\nmov %rax,(%r15)\ncallq 10f0 \nmov 0x10(%rsp),%rcx\nmovq $0xa,0x10(%r15)\nmov %rax,0x8(%r15)\nmov %rax,%r12\nmovslq %ebp,%rax\nadd $0x1,%ebp\nmov %r15,(%rcx,%rax,8)\nmov %r13,%rdi\nadd $0x10,%rbx\ncallq 1110 \nlea 0x1(%r14),%ecx\nmov %rax,%r9\nmovslq %r14d,%rax\nmov %r9,(%r12,%rax,8)\nmov %ecx,0x14(%r15)\ncmp %rbx,0x18(%rsp)\njne 1668 \njmpq 170d \nnopl 0x0(%rax)\nmov 0x10(%r15),%eax\ncmp %eax,%r14d\njne 176b \nlea 0xa(%r14),%ecx\nmov %r12,%rdi\nmov %ecx,0x10(%r15)\nmovslq %ecx,%rcx\nlea 0x0(,%rcx,8),%rsi\ncallq 1100 \nmov 0x14(%r15),%r14d\nmov %rax,0x8(%r15)\nmov %rax,%r12\njmp 176b \nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14, rdi\nmov edi, 50h ; 'P'; size\npush r13\npush r12\npush rbp\npush rbx\nmov ebx, esi\nsub rsp, 28h\ncall _malloc\nmov [rsp+58h+var_50], rax\ntest ebx, ebx\njle loc_1773\nlea eax, [rbx-1]\nmov [rsp+58h+var_48], 0\nshr eax, 1\nshl rax, 4\nlea rax, [r14+rax+10h]\nmov [rsp+58h+var_40], rax\nnop dword ptr [rax+00000000h]\nloc_16D0:\nmov eax, [rsp+58h+var_48]\nmov r12, [r14]\nmov rbp, [r14+8]\ntest eax, eax\njle loc_1787\nmov rcx, [rsp+58h+var_50]\nmovsxd rax, [rsp+58h+var_48]\nmov r15, rcx\nmov [rsp+58h+var_58], rax\nlea r13, [rcx+rax*8]\njmp short loc_170D\nloc_1700:\nadd r15, 8\ncmp r13, r15\njz loc_1790\nloc_170D:\nmov rbx, [r15]\nmov rsi, r12; s2\nmov rdi, [rbx]; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1700\nmovsxd rax, dword ptr [rbx+14h]\nmov r13, [rbx+8]\nmov [rsp+58h+var_44], eax\ntest eax, eax\njle loc_1849\nshl rax, 3\nmov r15, r13\nmov [rsp+58h+var_58], rax\nlea r12, [r13+rax+0]\njmp short loc_1755\nloc_1748:\nadd r15, 8\ncmp r15, r12\njz loc_1810\nloc_1755:\nmov rdi, [r15]; s1\nmov rsi, rbp; s2\ncall _strcmp\ntest eax, eax\njnz short loc_1748\nadd r14, 10h\ncmp [rsp+58h+var_40], r14\njnz loc_16D0\nloc_1773:\nmov rax, [rsp+58h+var_50]\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1787:\nmovsxd rax, [rsp+58h+var_48]\nmov [rsp+58h+var_58], rax\nloc_1790:\nmov edi, 18h; size\ncall _malloc\nmov rdi, r12; s\nmov r12d, 1\nmov rbx, rax\ncall _strdup\nmov edi, 50h ; 'P'; size\nmov [rbx], rax\ncall _malloc\nmov rdx, [rsp+58h+var_58]\nadd [rsp+58h+var_48], 1\nmov [rbx+8], rax\nmov r13, rax\nmov rax, cs:qword_2108\nmov [rsp+58h+var_58], 0\nmov [rbx+10h], rax\nmov rax, [rsp+58h+var_50]\nmov [rax+rdx*8], rbx\nloc_17E4:\nmov rdi, rbp; s\nadd r14, 10h\ncall _strdup\nmov rdx, [rsp+58h+var_58]\nmov [rbx+14h], r12d\nmov [r13+rdx+0], rax\ncmp [rsp+58h+var_40], r14\njnz loc_16D0\njmp loc_1773\nloc_1810:\nmov edx, [rsp+58h+var_44]\nmov eax, [rbx+10h]\nlea r12d, [rdx+1]\nloc_181B:\nmov r15d, [rsp+58h+var_44]\ncmp r15d, eax\njnz short loc_17E4\nadd r15d, 0Ah\nmov rdi, r13; ptr\nmov [rbx+10h], r15d\nmovsxd r15, r15d\nlea rsi, ds:0[r15*8]; size\ncall _realloc\nmov [rbx+8], rax\nmov r13, rax\njmp short loc_17E4\nloc_1849:\nmovsxd rdx, [rsp+58h+var_44]\nmov eax, [rbx+10h]\nmov rcx, rdx\nshl rdx, 3\nmov [rsp+58h+var_58], rdx\nlea r12d, [rcx+1]\njmp short loc_181B", + "ida_pseudo": "const char ***__fastcall func0(const char **a1, int a2)\n{\n const char **v2; // r14\n const char *v3; // r12\n const char *v4; // rbp\n const char ***v5; // r15\n const char **v6; // rbx\n __int64 v7; // rax\n char *v8; // r13\n const char **v9; // r15\n const char **v10; // r12\n const char *v12; // rdi\n int v13; // r12d\n const char *v14; // rax\n __int64 v15; // rdx\n char *v16; // rax\n int v17; // eax\n const char *v18; // rax\n __int64 v19; // [rsp+0h] [rbp-58h]\n __int64 v20; // [rsp+0h] [rbp-58h]\n const char ***v21; // [rsp+8h] [rbp-50h]\n int v22; // [rsp+10h] [rbp-48h]\n int v23; // [rsp+14h] [rbp-44h]\n __int64 v24; // [rsp+18h] [rbp-40h]\n\n v2 = a1;\n v21 = (const char ***)malloc(0x50uLL);\n if ( a2 <= 0 )\n return v21;\n v22 = 0;\n v24 = (__int64)&a1[2 * ((unsigned int)(a2 - 1) >> 1) + 2];\n while ( 1 )\n {\nLABEL_3:\n v3 = *v2;\n v4 = v2[1];\n if ( v22 <= 0 )\n {\n v19 = v22;\nLABEL_14:\n v12 = v3;\n v13 = 1;\n v6 = (const char **)malloc(0x18uLL);\n *v6 = strdup(v12);\n v14 = (const char *)malloc(0x50uLL);\n v15 = v19;\n ++v22;\n v6[1] = v14;\n v8 = (char *)v14;\n v20 = 0LL;\n v6[2] = byte_9 + 1;\n v21[v15] = v6;\n goto LABEL_15;\n }\n v5 = v21;\n v19 = v22;\n while ( 1 )\n {\n v6 = *v5;\n if ( !strcmp(**v5, v3) )\n break;\n if ( &v21[v22] == ++v5 )\n goto LABEL_14;\n }\n v7 = *((int *)v6 + 5);\n v8 = (char *)v6[1];\n v23 = v7;\n if ( (int)v7 > 0 )\n break;\n v17 = *((_DWORD *)v6 + 4);\n v20 = 8LL * v23;\n v13 = v23 + 1;\nLABEL_18:\n if ( v23 == v17 )\n {\n *((_DWORD *)v6 + 4) = v23 + 10;\n v18 = (const char *)realloc(v8, 8LL * (v23 + 10));\n v6[1] = v18;\n v8 = (char *)v18;\n }\nLABEL_15:\n v2 += 2;\n v16 = strdup(v4);\n *((_DWORD *)v6 + 5) = v13;\n *(_QWORD *)&v8[v20] = v16;\n if ( (const char **)v24 == v2 )\n return v21;\n }\n v9 = (const char **)v6[1];\n v20 = 8 * v7;\n v10 = (const char **)&v8[8 * v7];\n while ( strcmp(*v9, v4) )\n {\n if ( ++v9 == v10 )\n {\n v17 = *((_DWORD *)v6 + 4);\n v13 = v23 + 1;\n goto LABEL_18;\n }\n }\n v2 += 2;\n if ( (const char **)v24 != v2 )\n goto LABEL_3;\n return v21;\n}", + "ida_strip_asm": "sub_1680:\nendbr64\npush r15\npush r14\nmov r14, rdi\nmov edi, 50h ; 'P'; size\npush r13\npush r12\npush rbp\npush rbx\nmov ebx, esi\nsub rsp, 28h\ncall _malloc\nmov [rsp+58h+var_50], rax\ntest ebx, ebx\njle loc_1773\nlea eax, [rbx-1]\nmov [rsp+58h+var_48], 0\nshr eax, 1\nshl rax, 4\nlea rax, [r14+rax+10h]\nmov [rsp+58h+var_40], rax\nnop dword ptr [rax+00000000h]\nloc_16D0:\nmov eax, [rsp+58h+var_48]\nmov r12, [r14]\nmov rbp, [r14+8]\ntest eax, eax\njle loc_1787\nmov rcx, [rsp+58h+var_50]\nmovsxd rax, [rsp+58h+var_48]\nmov r15, rcx\nmov [rsp+58h+var_58], rax\nlea r13, [rcx+rax*8]\njmp short loc_170D\nloc_1700:\nadd r15, 8\ncmp r13, r15\njz loc_1790\nloc_170D:\nmov rbx, [r15]\nmov rsi, r12; s2\nmov rdi, [rbx]; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1700\nmovsxd rax, dword ptr [rbx+14h]\nmov r13, [rbx+8]\nmov [rsp+58h+var_44], eax\ntest eax, eax\njle loc_1849\nshl rax, 3\nmov r15, r13\nmov [rsp+58h+var_58], rax\nlea r12, [r13+rax+0]\njmp short loc_1755\nloc_1748:\nadd r15, 8\ncmp r15, r12\njz loc_1810\nloc_1755:\nmov rdi, [r15]; s1\nmov rsi, rbp; s2\ncall _strcmp\ntest eax, eax\njnz short loc_1748\nadd r14, 10h\ncmp [rsp+58h+var_40], r14\njnz loc_16D0\nloc_1773:\nmov rax, [rsp+58h+var_50]\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1787:\nmovsxd rax, [rsp+58h+var_48]\nmov [rsp+58h+var_58], rax\nloc_1790:\nmov edi, 18h; size\ncall _malloc\nmov rdi, r12; s\nmov r12d, 1\nmov rbx, rax\ncall _strdup\nmov edi, 50h ; 'P'; size\nmov [rbx], rax\ncall _malloc\nmov rdx, [rsp+58h+var_58]\nadd [rsp+58h+var_48], 1\nmov [rbx+8], rax\nmov r13, rax\nmov rax, cs:qword_2108\nmov [rsp+58h+var_58], 0\nmov [rbx+10h], rax\nmov rax, [rsp+58h+var_50]\nmov [rax+rdx*8], rbx\nloc_17E4:\nmov rdi, rbp; s\nadd r14, 10h\ncall _strdup\nmov rdx, [rsp+58h+var_58]\nmov [rbx+14h], r12d\nmov [r13+rdx+0], rax\ncmp [rsp+58h+var_40], r14\njnz loc_16D0\njmp loc_1773\nloc_1810:\nmov edx, [rsp+58h+var_44]\nmov eax, [rbx+10h]\nlea r12d, [rdx+1]\nloc_181B:\nmov r15d, [rsp+58h+var_44]\ncmp r15d, eax\njnz short loc_17E4\nadd r15d, 0Ah\nmov rdi, r13; ptr\nmov [rbx+10h], r15d\nmovsxd r15, r15d\nlea rsi, ds:0[r15*8]; size\ncall _realloc\nmov [rbx+8], rax\nmov r13, rax\njmp short loc_17E4\nloc_1849:\nmovsxd rdx, [rsp+58h+var_44]\nmov eax, [rbx+10h]\nmov rcx, rdx\nshl rdx, 3\nmov [rsp+58h+var_58], rdx\nlea r12d, [rcx+1]\njmp short loc_181B", + "ida_strip_pseudo": "const char ***__fastcall sub_1680(const char **a1, int a2)\n{\n const char **v2; // r14\n const char *v3; // r12\n const char *v4; // rbp\n const char ***v5; // r15\n const char **v6; // rbx\n __int64 v7; // rax\n char *v8; // r13\n const char **v9; // r15\n const char **v10; // r12\n const char *v12; // rdi\n int v13; // r12d\n const char *v14; // rax\n __int64 v15; // rdx\n char *v16; // rax\n int v17; // eax\n const char *v18; // rax\n __int64 v19; // [rsp+0h] [rbp-58h]\n __int64 v20; // [rsp+0h] [rbp-58h]\n const char ***v21; // [rsp+8h] [rbp-50h]\n int v22; // [rsp+10h] [rbp-48h]\n int v23; // [rsp+14h] [rbp-44h]\n __int64 v24; // [rsp+18h] [rbp-40h]\n\n v2 = a1;\n v21 = (const char ***)malloc(0x50uLL);\n if ( a2 <= 0 )\n return v21;\n v22 = 0;\n v24 = (__int64)&a1[2 * ((unsigned int)(a2 - 1) >> 1) + 2];\n while ( 1 )\n {\nLABEL_3:\n v3 = *v2;\n v4 = v2[1];\n if ( v22 <= 0 )\n {\n v19 = v22;\nLABEL_14:\n v12 = v3;\n v13 = 1;\n v6 = (const char **)malloc(0x18uLL);\n *v6 = strdup(v12);\n v14 = (const char *)malloc(0x50uLL);\n v15 = v19;\n ++v22;\n v6[1] = v14;\n v8 = (char *)v14;\n v20 = 0LL;\n v6[2] = byte_9 + 1;\n v21[v15] = v6;\n goto LABEL_15;\n }\n v5 = v21;\n v19 = v22;\n while ( 1 )\n {\n v6 = *v5;\n if ( !strcmp(**v5, v3) )\n break;\n if ( &v21[v22] == ++v5 )\n goto LABEL_14;\n }\n v7 = *((int *)v6 + 5);\n v8 = (char *)v6[1];\n v23 = v7;\n if ( (int)v7 > 0 )\n break;\n v17 = *((_DWORD *)v6 + 4);\n v20 = 8LL * v23;\n v13 = v23 + 1;\nLABEL_18:\n if ( v23 == v17 )\n {\n *((_DWORD *)v6 + 4) = v23 + 10;\n v18 = (const char *)realloc(v8, 8LL * (v23 + 10));\n v6[1] = v18;\n v8 = (char *)v18;\n }\nLABEL_15:\n v2 += 2;\n v16 = strdup(v4);\n *((_DWORD *)v6 + 5) = v13;\n *(_QWORD *)&v8[v20] = v16;\n if ( (const char **)v24 == v2 )\n return v21;\n }\n v9 = (const char **)v6[1];\n v20 = 8 * v7;\n v10 = (const char **)&v8[8 * v7];\n while ( strcmp(*v9, v4) )\n {\n if ( ++v9 == v10 )\n {\n v17 = *((_DWORD *)v6 + 4);\n v13 = v23 + 1;\n goto LABEL_18;\n }\n }\n v2 += 2;\n if ( (const char **)v24 != v2 )\n goto LABEL_3;\n return v21;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char ***sub_1680(const char **a1, int a2) {\n const char **v2;\n const char *v3;\n const char *v4;\n const char ***v5;\n const char **v6;\n long long v7;\n char *v8;\n const char **v9;\n const char **v10;\n const char *v12;\n int v13;\n const char *v14;\n long long v15;\n char *v16;\n int v17;\n const char *v18;\n long long v19;\n long long v20;\n const char ***v21;\n int v22;\n int v23;\n long long v24;\n v2 = a1;\n v21 = (const char ***)malloc(80uLL);\n if (a2 <= 0) return v21;\n v22 = 0;\n v24 = (long long)&a1[2 * ((unsigned int)(a2 - 1) >> 1) + 2];\n while (1) {\n LABEL_3:\n v3 = *v2;\n v4 = v2[1];\n if (v22 <= 0) {\n v19 = v22;\n LABEL_14:\n v12 = v3;\n v13 = 1;\n v6 = (const char **)malloc(24uLL);\n *v6 = strdup(v12);\n v14 = (const char *)malloc(80uLL);\n v15 = v19;\n ++v22;\n v6[1] = v14;\n v8 = (char *)v14;\n v20 = 0LL;\n v6[2] = byte_9 + 1;\n v21[v15] = v6;\n goto LABEL_15;\n }\n v5 = v21;\n v19 = v22;\n while (1) {\n v6 = *v5;\n if (!strcmp(**v5, v3)) break;\n if (&v21[v22] == ++v5) goto LABEL_14;\n }\n v7 = *((int *)v6 + 5);\n v8 = (char *)v6[1];\n v23 = v7;\n if ((int)v7 > 0) break;\n v17 = *((uint32_t *)v6 + 4);\n v20 = 8LL * v23;\n v13 = v23 + 1;\n LABEL_18:\n if (v23 == v17) {\n *((uint32_t *)v6 + 4) = v23 + 10;\n v18 = (const char *)realloc(v8, 8LL * (v23 + 10));\n v6[1] = v18;\n v8 = (char *)v18;\n }\n LABEL_15:\n v2 += 2;\n v16 = strdup(v4);\n *((uint32_t *)v6 + 5) = v13;\n *(uint64_t *)&v8[v20] = v16;\n if ((const char **)v24 == v2) return v21;\n }\n v9 = (const char **)v6[1];\n v20 = 8 * v7;\n v10 = (const char **)&v8[8 * v7];\n while (strcmp(*v9, v4)) {\n if (++v9 == v10) {\n v17 = *((uint32_t *)v6 + 4);\n v13 = v23 + 1;\n goto LABEL_18;\n }\n }\n v2 += 2;\n if ((const char **)v24 != v2) goto LABEL_3;\n return v21;\n}", + "ida_pseudo_norm": "const char ***func0(const char **a1, int a2) {\n const char **v2;\n const char *v3;\n const char *v4;\n const char ***v5;\n const char **v6;\n long long v7;\n char *v8;\n const char **v9;\n const char **v10;\n const char *v12;\n int v13;\n const char *v14;\n long long v15;\n char *v16;\n int v17;\n const char *v18;\n long long v19;\n long long v20;\n const char ***v21;\n int v22;\n int v23;\n long long v24;\n v2 = a1;\n v21 = (const char ***)malloc(80uLL);\n if (a2 <= 0) return v21;\n v22 = 0;\n v24 = (long long)&a1[2 * ((unsigned int)(a2 - 1) >> 1) + 2];\n while (1) {\n LABEL_3:\n v3 = *v2;\n v4 = v2[1];\n if (v22 <= 0) {\n v19 = v22;\n LABEL_14:\n v12 = v3;\n v13 = 1;\n v6 = (const char **)malloc(24uLL);\n *v6 = strdup(v12);\n v14 = (const char *)malloc(80uLL);\n v15 = v19;\n ++v22;\n v6[1] = v14;\n v8 = (char *)v14;\n v20 = 0LL;\n v6[2] = byte_9 + 1;\n v21[v15] = v6;\n goto LABEL_15;\n }\n v5 = v21;\n v19 = v22;\n while (1) {\n v6 = *v5;\n if (!strcmp(**v5, v3)) break;\n if (&v21[v22] == ++v5) goto LABEL_14;\n }\n v7 = *((int *)v6 + 5);\n v8 = (char *)v6[1];\n v23 = v7;\n if ((int)v7 > 0) break;\n v17 = *((uint32_t *)v6 + 4);\n v20 = 8LL * v23;\n v13 = v23 + 1;\n LABEL_18:\n if (v23 == v17) {\n *((uint32_t *)v6 + 4) = v23 + 10;\n v18 = (const char *)realloc(v8, 8LL * (v23 + 10));\n v6[1] = v18;\n v8 = (char *)v18;\n }\n LABEL_15:\n v2 += 2;\n v16 = strdup(v4);\n *((uint32_t *)v6 + 5) = v13;\n *(uint64_t *)&v8[v20] = v16;\n if ((const char **)v24 == v2) return v21;\n }\n v9 = (const char **)v6[1];\n v20 = 8 * v7;\n v10 = (const char **)&v8[8 * v7];\n while (strcmp(*v9, v4)) {\n if (++v9 == v10) {\n v17 = *((uint32_t *)v6 + 4);\n v13 = v23 + 1;\n goto LABEL_18;\n }\n }\n v2 += 2;\n if ((const char **)v24 != v2) goto LABEL_3;\n return v21;\n}" + }, + { + "index": 244, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int N) {\n int nextN = (int)floor(sqrt(N)) + 1;\n return nextN * nextN;\n}", + "test": "int main() {\n\n assert(func0(35) == 36);\n\n assert(func0(6) == 9);\n\n assert(func0(9) == 16);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %edi,-0x14(%rbp)\ncvtsi2sdl -0x14(%rbp),%xmm0\ncallq 1090 \ncallq 1080 \ncvttsd2si %xmm0,%eax\nadd $0x1,%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nimul %eax,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_14]\nmovq rax, xmm1\nmovq xmm0, rax; x\ncall _sqrt\nmovq rax, xmm0\nmovq xmm0, rax; x\ncall _floor\ncvttsd2si eax, xmm0\nadd eax, 1\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\nimul eax, eax\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n double v1; // xmm0_8\n int v3; // [rsp+1Ch] [rbp-4h]\n\n v1 = sqrt((double)a1);\n v3 = (int)floor(v1) + 1;\n return (unsigned int)(v3 * v3);\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_14]\nmovq rax, xmm1\nmovq xmm0, rax; x\ncall _sqrt\nmovq rax, xmm0\nmovq xmm0, rax; x\ncall _floor\ncvttsd2si eax, xmm0\nadd eax, 1\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\nimul eax, eax\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(int a1)\n{\n double v1; // xmm0_8\n int v3; // [rsp+1Ch] [rbp-4h]\n\n v1 = sqrt((double)a1);\n v3 = (int)floor(v1) + 1;\n return (unsigned int)(v3 * v3);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(int a1) {\n double v1;\n int v3;\n v1 = sqrt((double)a1);\n v3 = (int)floor(v1) + 1;\n return (unsigned int)(v3 * v3);\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n double v1;\n int v3;\n v1 = sqrt((double)a1);\n v3 = (int)floor(v1) + 1;\n return (unsigned int)(v3 * v3);\n}" + }, + { + "index": 244, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int N) {\n int nextN = (int)floor(sqrt(N)) + 1;\n return nextN * nextN;\n}", + "test": "int main() {\n\n assert(func0(35) == 36);\n\n assert(func0(6) == 9);\n\n assert(func0(9) == 16);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x18,%rsp\npxor %xmm0,%xmm0\ncvtsi2sd %edi,%xmm0\nmovapd %xmm0,%xmm6\nsqrtsd %xmm6,%xmm6\nmovsd %xmm6,0x8(%rsp)\npxor %xmm1,%xmm1\nucomisd %xmm0,%xmm1\nja 11fb \nmovsd 0x8(%rsp),%xmm5\nmovapd %xmm5,%xmm0\nmovsd 0xeed(%rip),%xmm2\nmovapd %xmm5,%xmm1\nandpd %xmm2,%xmm1\nmovsd 0xec5(%rip),%xmm3\nucomisd %xmm1,%xmm3\njbe 11ec \ncvttsd2si %xmm5,%rax\npxor %xmm1,%xmm1\ncvtsi2sd %rax,%xmm1\nmovapd %xmm1,%xmm0\ncmpnlesd %xmm5,%xmm0\nmovsd 0xea8(%rip),%xmm3\nandpd %xmm3,%xmm0\nsubsd %xmm0,%xmm1\nandnpd %xmm5,%xmm2\nmovapd %xmm2,%xmm0\norpd %xmm1,%xmm0\ncvttsd2si %xmm0,%eax\nadd $0x1,%eax\nimul %eax,%eax\nadd $0x18,%rsp\nretq\ncallq 1070 \njmp 1191 \n", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\npxor xmm0, xmm0\ncvtsi2sd xmm0, edi; x\npxor xmm1, xmm1\nucomisd xmm1, xmm0\nja short loc_11EB\nsqrtsd xmm0, xmm0\nloc_1187:\nmovapd xmm3, xmm0\nmovsd xmm2, cs:qword_2070\nmovapd xmm1, xmm0\nandpd xmm1, xmm2\nmovsd xmm4, cs:qword_2060\nucomisd xmm4, xmm1\njbe short loc_11DC\ncvttsd2si rax, xmm0\npxor xmm1, xmm1\ncvtsi2sd xmm1, rax\nmovapd xmm3, xmm1\ncmpnlesd xmm3, xmm0\nmovsd xmm4, cs:qword_2068\nandpd xmm3, xmm4\nsubsd xmm1, xmm3\nandnpd xmm2, xmm0\nmovapd xmm3, xmm1\norpd xmm3, xmm2\nloc_11DC:\ncvttsd2si eax, xmm3\nadd eax, 1\nimul eax, eax\nadd rsp, 8\nretn\nloc_11EB:\ncall _sqrt\njmp short loc_1187", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n double v1; // xmm0_8\n __m128d v2; // xmm0\n double v3; // xmm3_8\n __m128d v4; // xmm1\n\n v1 = (double)a1;\n if ( (double)a1 < 0.0 )\n v2.m128d_f64[0] = sqrt(v1);\n else\n v2.m128d_f64[0] = sqrt(v1);\n v3 = v2.m128d_f64[0];\n if ( fabs(v2.m128d_f64[0]) < 4.503599627370496e15 )\n {\n v4 = 0LL;\n v4.m128d_f64[0] = (double)(int)v2.m128d_f64[0];\n *(_QWORD *)&v3 = COERCE_UNSIGNED_INT64(v4.m128d_f64[0] - COERCE_DOUBLE(*(_OWORD *)&_mm_cmpgt_sd(v4, v2) & 0x3FF0000000000000LL)) | *(_QWORD *)&v2.m128d_f64[0] & 0x8000000000000000LL;\n }\n return (unsigned int)(((int)v3 + 1) * ((int)v3 + 1));\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nsub rsp, 8\npxor xmm0, xmm0\ncvtsi2sd xmm0, edi; x\npxor xmm1, xmm1\nucomisd xmm1, xmm0\nja short loc_11EB\nsqrtsd xmm0, xmm0\nloc_1187:\nmovapd xmm3, xmm0\nmovsd xmm2, cs:qword_2070\nmovapd xmm1, xmm0\nandpd xmm1, xmm2\nmovsd xmm4, cs:qword_2060\nucomisd xmm4, xmm1\njbe short loc_11DC\ncvttsd2si rax, xmm0\npxor xmm1, xmm1\ncvtsi2sd xmm1, rax\nmovapd xmm3, xmm1\ncmpnlesd xmm3, xmm0\nmovsd xmm4, cs:qword_2068\nandpd xmm3, xmm4\nsubsd xmm1, xmm3\nandnpd xmm2, xmm0\nmovapd xmm3, xmm1\norpd xmm3, xmm2\nloc_11DC:\ncvttsd2si eax, xmm3\nadd eax, 1\nimul eax, eax\nadd rsp, 8\nretn\nloc_11EB:\ncall _sqrt\njmp short loc_1187", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n double v1; // xmm0_8\n __m128d v2; // xmm0\n double v3; // xmm3_8\n __m128d v4; // xmm1\n\n v1 = (double)a1;\n if ( (double)a1 < 0.0 )\n v2.m128d_f64[0] = sqrt(v1);\n else\n v2.m128d_f64[0] = sqrt(v1);\n v3 = v2.m128d_f64[0];\n if ( fabs(v2.m128d_f64[0]) < 4.503599627370496e15 )\n {\n v4 = 0LL;\n v4.m128d_f64[0] = (double)(int)v2.m128d_f64[0];\n *(_QWORD *)&v3 = COERCE_UNSIGNED_INT64(v4.m128d_f64[0] - COERCE_DOUBLE(*(_OWORD *)&_mm_cmpgt_sd(v4, v2) & 0x3FF0000000000000LL)) | *(_QWORD *)&v2.m128d_f64[0] & 0x8000000000000000LL;\n }\n return (unsigned int)(((int)v3 + 1) * ((int)v3 + 1));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n double v1;\n __m128d v2;\n double v3;\n __m128d v4;\n v1 = (double)a1;\n if ((double)a1 < 0.0)\n v2.m128d_f64[0] = sqrt(v1);\n else\n v2.m128d_f64[0] = sqrt(v1);\n v3 = v2.m128d_f64[0];\n if (fabs(v2.m128d_f64[0]) < 4.503599627370496e15) {\n v4 = 0LL;\n v4.m128d_f64[0] = (double)(int)v2.m128d_f64[0];\n *(uint64_t *)&v3 = COERCE_UNSIGNED_INT64(\n v4.m128d_f64[0] -\n COERCE_DOUBLE(*(long double *)&_mm_cmpgt_sd(v4, v2) &\n 4607182418800017408LL)) |\n *(uint64_t *)&v2.m128d_f64[0] & 9223372036854775808LL;\n }\n return (unsigned int)(((int)v3 + 1) * ((int)v3 + 1));\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n double v1;\n __m128d v2;\n double v3;\n __m128d v4;\n v1 = (double)a1;\n if ((double)a1 < 0.0)\n v2.m128d_f64[0] = sqrt(v1);\n else\n v2.m128d_f64[0] = sqrt(v1);\n v3 = v2.m128d_f64[0];\n if (fabs(v2.m128d_f64[0]) < 4.503599627370496e15) {\n v4 = 0LL;\n v4.m128d_f64[0] = (double)(int)v2.m128d_f64[0];\n *(uint64_t *)&v3 = COERCE_UNSIGNED_INT64(\n v4.m128d_f64[0] -\n COERCE_DOUBLE(*(long double *)&_mm_cmpgt_sd(v4, v2) &\n 4607182418800017408LL)) |\n *(uint64_t *)&v2.m128d_f64[0] & 9223372036854775808LL;\n }\n return (unsigned int)(((int)v3 + 1) * ((int)v3 + 1));\n}" + }, + { + "index": 244, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int N) {\n int nextN = (int)floor(sqrt(N)) + 1;\n return nextN * nextN;\n}", + "test": "int main() {\n\n assert(func0(35) == 36);\n\n assert(func0(6) == 9);\n\n assert(func0(9) == 16);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npxor %xmm0,%xmm0\npxor %xmm2,%xmm2\nsub $0x18,%rsp\ncvtsi2sd %edi,%xmm0\nucomisd %xmm0,%xmm2\nmovapd %xmm0,%xmm1\nsqrtsd %xmm1,%xmm1\nja 1292 \nmovsd 0xe56(%rip),%xmm2\nmovsd 0xe36(%rip),%xmm3\nmovapd %xmm1,%xmm0\nandpd %xmm2,%xmm1\nucomisd %xmm1,%xmm3\njbe 1283 \ncvttsd2si %xmm0,%rax\npxor %xmm1,%xmm1\nmovsd 0xe1f(%rip),%xmm4\nandnpd %xmm0,%xmm2\ncvtsi2sd %rax,%xmm1\nmovapd %xmm1,%xmm3\ncmpnlesd %xmm0,%xmm3\nmovapd %xmm2,%xmm0\nandpd %xmm4,%xmm3\nsubsd %xmm3,%xmm1\norpd %xmm1,%xmm0\ncvttsd2si %xmm0,%eax\nadd $0x18,%rsp\nadd $0x1,%eax\nimul %eax,%eax\nretq\nmovsd %xmm1,0x8(%rsp)\ncallq 1070 \nmovsd 0x8(%rsp),%xmm1\njmp 1232 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npxor xmm0, xmm0\npxor xmm1, xmm1\nsub rsp, 8\ncvtsi2sd xmm0, edi; x\nucomisd xmm1, xmm0\nja short loc_128E\nsqrtsd xmm0, xmm0\nloc_122E:\nmovsd xmm2, cs:qword_2070\nmovsd xmm3, cs:qword_2060\nmovapd xmm1, xmm0\nandpd xmm1, xmm2\nucomisd xmm3, xmm1\njbe short loc_127F\ncvttsd2si rax, xmm0\npxor xmm1, xmm1\nmovsd xmm4, cs:qword_2068\nandnpd xmm2, xmm0\ncvtsi2sd xmm1, rax\nmovapd xmm3, xmm1\ncmpnlesd xmm3, xmm0\nandpd xmm3, xmm4\nsubsd xmm1, xmm3\norpd xmm1, xmm2\nmovapd xmm0, xmm1\nloc_127F:\ncvttsd2si eax, xmm0\nadd rsp, 8\nadd eax, 1\nimul eax, eax\nretn\nloc_128E:\ncall _sqrt\njmp short loc_122E", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n double v1; // xmm0_8\n __m128d v2; // xmm0\n __m128d v3; // xmm1\n\n v1 = (double)a1;\n if ( (double)a1 < 0.0 )\n v2.m128d_f64[0] = sqrt(v1);\n else\n v2.m128d_f64[0] = sqrt(v1);\n if ( fabs(v2.m128d_f64[0]) < 4.503599627370496e15 )\n {\n v3 = 0LL;\n v3.m128d_f64[0] = (double)(int)v2.m128d_f64[0];\n *(_QWORD *)&v2.m128d_f64[0] = COERCE_UNSIGNED_INT64(\n v3.m128d_f64[0]\n - COERCE_DOUBLE(*(_OWORD *)&_mm_cmpgt_sd(v3, v2) & 0x3FF0000000000000LL)) | *(_QWORD *)&v2.m128d_f64[0] & 0x8000000000000000LL;\n }\n return (unsigned int)(((int)v2.m128d_f64[0] + 1) * ((int)v2.m128d_f64[0] + 1));\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npxor xmm0, xmm0\npxor xmm1, xmm1\nsub rsp, 8\ncvtsi2sd xmm0, edi; x\nucomisd xmm1, xmm0\nja short loc_128E\nsqrtsd xmm0, xmm0\nloc_122E:\nmovsd xmm2, cs:qword_2070\nmovsd xmm3, cs:qword_2060\nmovapd xmm1, xmm0\nandpd xmm1, xmm2\nucomisd xmm3, xmm1\njbe short loc_127F\ncvttsd2si rax, xmm0\npxor xmm1, xmm1\nmovsd xmm4, cs:qword_2068\nandnpd xmm2, xmm0\ncvtsi2sd xmm1, rax\nmovapd xmm3, xmm1\ncmpnlesd xmm3, xmm0\nandpd xmm3, xmm4\nsubsd xmm1, xmm3\norpd xmm1, xmm2\nmovapd xmm0, xmm1\nloc_127F:\ncvttsd2si eax, xmm0\nadd rsp, 8\nadd eax, 1\nimul eax, eax\nretn\nloc_128E:\ncall _sqrt\njmp short loc_122E", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(int a1)\n{\n double v1; // xmm0_8\n __m128d v2; // xmm0\n __m128d v3; // xmm1\n\n v1 = (double)a1;\n if ( (double)a1 < 0.0 )\n v2.m128d_f64[0] = sqrt(v1);\n else\n v2.m128d_f64[0] = sqrt(v1);\n if ( fabs(v2.m128d_f64[0]) < 4.503599627370496e15 )\n {\n v3 = 0LL;\n v3.m128d_f64[0] = (double)(int)v2.m128d_f64[0];\n *(_QWORD *)&v2.m128d_f64[0] = COERCE_UNSIGNED_INT64(\n v3.m128d_f64[0]\n - COERCE_DOUBLE(*(_OWORD *)&_mm_cmpgt_sd(v3, v2) & 0x3FF0000000000000LL)) | *(_QWORD *)&v2.m128d_f64[0] & 0x8000000000000000LL;\n }\n return (unsigned int)(((int)v2.m128d_f64[0] + 1) * ((int)v2.m128d_f64[0] + 1));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(int a1) {\n double v1;\n __m128d v2;\n __m128d v3;\n v1 = (double)a1;\n if ((double)a1 < 0.0)\n v2.m128d_f64[0] = sqrt(v1);\n else\n v2.m128d_f64[0] = sqrt(v1);\n if (fabs(v2.m128d_f64[0]) < 4.503599627370496e15) {\n v3 = 0LL;\n v3.m128d_f64[0] = (double)(int)v2.m128d_f64[0];\n *(uint64_t *)&v2.m128d_f64[0] =\n COERCE_UNSIGNED_INT64(\n v3.m128d_f64[0] -\n COERCE_DOUBLE(*(long double *)&_mm_cmpgt_sd(v3, v2) &\n 4607182418800017408LL)) |\n *(uint64_t *)&v2.m128d_f64[0] & 9223372036854775808LL;\n }\n return (unsigned int)(((int)v2.m128d_f64[0] + 1) *\n ((int)v2.m128d_f64[0] + 1));\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n double v1;\n __m128d v2;\n __m128d v3;\n v1 = (double)a1;\n if ((double)a1 < 0.0)\n v2.m128d_f64[0] = sqrt(v1);\n else\n v2.m128d_f64[0] = sqrt(v1);\n if (fabs(v2.m128d_f64[0]) < 4.503599627370496e15) {\n v3 = 0LL;\n v3.m128d_f64[0] = (double)(int)v2.m128d_f64[0];\n *(uint64_t *)&v2.m128d_f64[0] =\n COERCE_UNSIGNED_INT64(\n v3.m128d_f64[0] -\n COERCE_DOUBLE(*(long double *)&_mm_cmpgt_sd(v3, v2) &\n 4607182418800017408LL)) |\n *(uint64_t *)&v2.m128d_f64[0] & 9223372036854775808LL;\n }\n return (unsigned int)(((int)v2.m128d_f64[0] + 1) *\n ((int)v2.m128d_f64[0] + 1));\n}" + }, + { + "index": 244, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int N) {\n int nextN = (int)floor(sqrt(N)) + 1;\n return nextN * nextN;\n}", + "test": "int main() {\n\n assert(func0(35) == 36);\n\n assert(func0(6) == 9);\n\n assert(func0(9) == 16);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npxor %xmm0,%xmm0\npxor %xmm2,%xmm2\nsub $0x18,%rsp\ncvtsi2sd %edi,%xmm0\nucomisd %xmm0,%xmm2\nmovapd %xmm0,%xmm1\nsqrtsd %xmm1,%xmm1\nja 1292 \nmovsd 0xe56(%rip),%xmm2\nmovsd 0xe36(%rip),%xmm3\nmovapd %xmm1,%xmm0\nandpd %xmm2,%xmm1\nucomisd %xmm1,%xmm3\njbe 1283 \ncvttsd2si %xmm0,%rax\npxor %xmm1,%xmm1\nmovsd 0xe1f(%rip),%xmm4\nandnpd %xmm0,%xmm2\ncvtsi2sd %rax,%xmm1\nmovapd %xmm1,%xmm3\ncmpnlesd %xmm0,%xmm3\nmovapd %xmm2,%xmm0\nandpd %xmm4,%xmm3\nsubsd %xmm3,%xmm1\norpd %xmm1,%xmm0\ncvttsd2si %xmm0,%eax\nadd $0x18,%rsp\nadd $0x1,%eax\nimul %eax,%eax\nretq\nmovsd %xmm1,0x8(%rsp)\ncallq 1070 \nmovsd 0x8(%rsp),%xmm1\njmp 1232 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npxor xmm0, xmm0\npxor xmm1, xmm1\nsub rsp, 8\ncvtsi2sd xmm0, edi; x\nucomisd xmm1, xmm0\nja short loc_128E\nsqrtsd xmm0, xmm0\nloc_122E:\nmovsd xmm2, cs:qword_2070\nmovsd xmm3, cs:qword_2060\nmovapd xmm1, xmm0\nandpd xmm1, xmm2\nucomisd xmm3, xmm1\njbe short loc_127F\ncvttsd2si rax, xmm0\npxor xmm1, xmm1\nmovsd xmm4, cs:qword_2068\nandnpd xmm2, xmm0\ncvtsi2sd xmm1, rax\nmovapd xmm3, xmm1\ncmpnlesd xmm3, xmm0\nandpd xmm3, xmm4\nsubsd xmm1, xmm3\norpd xmm1, xmm2\nmovapd xmm0, xmm1\nloc_127F:\ncvttsd2si eax, xmm0\nadd rsp, 8\nadd eax, 1\nimul eax, eax\nretn\nloc_128E:\ncall _sqrt\njmp short loc_122E", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n double v1; // xmm0_8\n __m128d v2; // xmm0\n __m128d v3; // xmm1\n\n v1 = (double)a1;\n if ( (double)a1 < 0.0 )\n v2.m128d_f64[0] = sqrt(v1);\n else\n v2.m128d_f64[0] = sqrt(v1);\n if ( fabs(v2.m128d_f64[0]) < 4.503599627370496e15 )\n {\n v3 = 0LL;\n v3.m128d_f64[0] = (double)(int)v2.m128d_f64[0];\n *(_QWORD *)&v2.m128d_f64[0] = COERCE_UNSIGNED_INT64(\n v3.m128d_f64[0]\n - COERCE_DOUBLE(*(_OWORD *)&_mm_cmpgt_sd(v3, v2) & 0x3FF0000000000000LL)) | *(_QWORD *)&v2.m128d_f64[0] & 0x8000000000000000LL;\n }\n return (unsigned int)(((int)v2.m128d_f64[0] + 1) * ((int)v2.m128d_f64[0] + 1));\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npxor xmm0, xmm0\npxor xmm1, xmm1\nsub rsp, 8\ncvtsi2sd xmm0, edi; x\nucomisd xmm1, xmm0\nja short loc_128E\nsqrtsd xmm0, xmm0\nloc_122E:\nmovsd xmm2, cs:qword_2070\nmovsd xmm3, cs:qword_2060\nmovapd xmm1, xmm0\nandpd xmm1, xmm2\nucomisd xmm3, xmm1\njbe short loc_127F\ncvttsd2si rax, xmm0\npxor xmm1, xmm1\nmovsd xmm4, cs:qword_2068\nandnpd xmm2, xmm0\ncvtsi2sd xmm1, rax\nmovapd xmm3, xmm1\ncmpnlesd xmm3, xmm0\nandpd xmm3, xmm4\nsubsd xmm1, xmm3\norpd xmm1, xmm2\nmovapd xmm0, xmm1\nloc_127F:\ncvttsd2si eax, xmm0\nadd rsp, 8\nadd eax, 1\nimul eax, eax\nretn\nloc_128E:\ncall _sqrt\njmp short loc_122E", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(int a1)\n{\n double v1; // xmm0_8\n __m128d v2; // xmm0\n __m128d v3; // xmm1\n\n v1 = (double)a1;\n if ( (double)a1 < 0.0 )\n v2.m128d_f64[0] = sqrt(v1);\n else\n v2.m128d_f64[0] = sqrt(v1);\n if ( fabs(v2.m128d_f64[0]) < 4.503599627370496e15 )\n {\n v3 = 0LL;\n v3.m128d_f64[0] = (double)(int)v2.m128d_f64[0];\n *(_QWORD *)&v2.m128d_f64[0] = COERCE_UNSIGNED_INT64(\n v3.m128d_f64[0]\n - COERCE_DOUBLE(*(_OWORD *)&_mm_cmpgt_sd(v3, v2) & 0x3FF0000000000000LL)) | *(_QWORD *)&v2.m128d_f64[0] & 0x8000000000000000LL;\n }\n return (unsigned int)(((int)v2.m128d_f64[0] + 1) * ((int)v2.m128d_f64[0] + 1));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(int a1) {\n double v1;\n __m128d v2;\n __m128d v3;\n v1 = (double)a1;\n if ((double)a1 < 0.0)\n v2.m128d_f64[0] = sqrt(v1);\n else\n v2.m128d_f64[0] = sqrt(v1);\n if (fabs(v2.m128d_f64[0]) < 4.503599627370496e15) {\n v3 = 0LL;\n v3.m128d_f64[0] = (double)(int)v2.m128d_f64[0];\n *(uint64_t *)&v2.m128d_f64[0] =\n COERCE_UNSIGNED_INT64(\n v3.m128d_f64[0] -\n COERCE_DOUBLE(*(long double *)&_mm_cmpgt_sd(v3, v2) &\n 4607182418800017408LL)) |\n *(uint64_t *)&v2.m128d_f64[0] & 9223372036854775808LL;\n }\n return (unsigned int)(((int)v2.m128d_f64[0] + 1) *\n ((int)v2.m128d_f64[0] + 1));\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n double v1;\n __m128d v2;\n __m128d v3;\n v1 = (double)a1;\n if ((double)a1 < 0.0)\n v2.m128d_f64[0] = sqrt(v1);\n else\n v2.m128d_f64[0] = sqrt(v1);\n if (fabs(v2.m128d_f64[0]) < 4.503599627370496e15) {\n v3 = 0LL;\n v3.m128d_f64[0] = (double)(int)v2.m128d_f64[0];\n *(uint64_t *)&v2.m128d_f64[0] =\n COERCE_UNSIGNED_INT64(\n v3.m128d_f64[0] -\n COERCE_DOUBLE(*(long double *)&_mm_cmpgt_sd(v3, v2) &\n 4607182418800017408LL)) |\n *(uint64_t *)&v2.m128d_f64[0] & 9223372036854775808LL;\n }\n return (unsigned int)(((int)v2.m128d_f64[0] + 1) *\n ((int)v2.m128d_f64[0] + 1));\n}" + }, + { + "index": 245, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int MSIBS[n];\n for (int i = 0; i < n; i++) {\n MSIBS[i] = arr[i];\n }\n for (int i = 1; i < n; i++) {\n for (int j = 0; j < i; j++) {\n if (arr[i] > arr[j] && MSIBS[i] < MSIBS[j] + arr[i]) {\n MSIBS[i] = MSIBS[j] + arr[i];\n }\n }\n }\n int MSDBS[n];\n for (int i = 0; i < n; i++) {\n MSDBS[i] = arr[i];\n }\n for (int i = 1; i < n; i++) {\n for (int j = 0; j < i; j++) {\n if (arr[n - i - 1] > arr[n - j - 1] &&\n MSDBS[n - i - 1] < MSDBS[n - j - 1] + arr[n - i - 1]) {\n MSDBS[n - i - 1] = MSDBS[n - j - 1] + arr[n - i - 1];\n }\n }\n }\n int max_sum = -99999999;\n for (int i = 0; i < n; i++) {\n if (max_sum < MSIBS[i] + MSDBS[i] - arr[i]) {\n max_sum = MSIBS[i] + MSDBS[i] - arr[i];\n }\n }\n return max_sum;\n}", + "test": "int main() {\n\n assert(func0((int[]){1, 15, 51, 45, 33, 100, 12, 18, 9}, 9) == 194);\n\n assert(func0((int[]){80, 60, 30, 40, 20, 10}, 6) == 210);\n\n assert(func0((int[]){2, 3, 14, 16, 21, 23, 29, 30}, 8) == 138);\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r13\npush %r12\npush %rbx\nsub $0x68,%rsp\nmov %rdi,-0x78(%rbp)\nmov %esi,-0x7c(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x28(%rbp)\nxor %eax,%eax\nmov %rsp,%rax\nmov %rax,%rdi\nmov -0x7c(%rbp),%eax\nmovslq %eax,%rdx\nsub $0x1,%rdx\nmov %rdx,-0x48(%rbp)\nmovslq %eax,%rdx\nmov %rdx,%r8\nmov $0x0,%r9d\nmovslq %eax,%rdx\nmov %rdx,%rcx\nmov $0x0,%ebx\ncltq\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%ebx\nmov $0x0,%edx\ndiv %rbx\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rbx\nsub %rdx,%rbx\nmov %rbx,%rdx\ncmp %rdx,%rsp\nje 122c \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 1215 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 1256 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x40(%rbp)\nmovl $0x0,-0x4c(%rbp)\njmp 1299 \nmov -0x4c(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x78(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%ecx\nmov -0x40(%rbp),%rax\nmov -0x4c(%rbp),%edx\nmovslq %edx,%rdx\nmov %ecx,(%rax,%rdx,4)\naddl $0x1,-0x4c(%rbp)\nmov -0x4c(%rbp),%eax\ncmp -0x7c(%rbp),%eax\njl 1272 \nmovl $0x1,-0x50(%rbp)\njmpq 1366 \nmovl $0x0,-0x54(%rbp)\njmpq 1356 \nmov -0x50(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x78(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x54(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x78(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njle 1352 \nmov -0x40(%rbp),%rax\nmov -0x50(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%ecx\nmov -0x40(%rbp),%rax\nmov -0x54(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%edx\nmov -0x50(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rsi\nmov -0x78(%rbp),%rax\nadd %rsi,%rax\nmov (%rax),%eax\nadd %edx,%eax\ncmp %eax,%ecx\njge 1352 \nmov -0x40(%rbp),%rax\nmov -0x54(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%edx\nmov -0x50(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x78(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\nlea (%rdx,%rax,1),%ecx\nmov -0x40(%rbp),%rax\nmov -0x50(%rbp),%edx\nmovslq %edx,%rdx\nmov %ecx,(%rax,%rdx,4)\naddl $0x1,-0x54(%rbp)\nmov -0x54(%rbp),%eax\ncmp -0x50(%rbp),%eax\njl 12b9 \naddl $0x1,-0x50(%rbp)\nmov -0x50(%rbp),%eax\ncmp -0x7c(%rbp),%eax\njl 12ad \nmov -0x7c(%rbp),%eax\nmov %rsp,%rdx\nmov %rdx,%r8\nmovslq %eax,%rdx\nsub $0x1,%rdx\nmov %rdx,-0x38(%rbp)\nmovslq %eax,%rdx\nmov %rdx,%r12\nmov $0x0,%r13d\nmovslq %eax,%rdx\nmov %rdx,%r10\nmov $0x0,%r11d\ncltq\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%esi\nmov $0x0,%edx\ndiv %rsi\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rbx\nsub %rdx,%rbx\nmov %rbx,%rdx\ncmp %rdx,%rsp\nje 13ef \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 13d8 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 1419 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x30(%rbp)\nmovl $0x0,-0x58(%rbp)\njmp 145c \nmov -0x58(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x78(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%ecx\nmov -0x30(%rbp),%rax\nmov -0x58(%rbp),%edx\nmovslq %edx,%rdx\nmov %ecx,(%rax,%rdx,4)\naddl $0x1,-0x58(%rbp)\nmov -0x58(%rbp),%eax\ncmp -0x7c(%rbp),%eax\njl 1435 \nmovl $0x1,-0x5c(%rbp)\njmpq 1550 \nmovl $0x0,-0x60(%rbp)\njmpq 1540 \nmov -0x7c(%rbp),%eax\nsub -0x5c(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rdx\nmov -0x78(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x7c(%rbp),%eax\nsub -0x60(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rcx\nmov -0x78(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njle 153c \nmov -0x7c(%rbp),%eax\nsub -0x5c(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x30(%rbp),%rax\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%ecx\nmov -0x7c(%rbp),%eax\nsub -0x60(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x30(%rbp),%rax\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%edx\nmov -0x7c(%rbp),%eax\nsub -0x5c(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rsi\nmov -0x78(%rbp),%rax\nadd %rsi,%rax\nmov (%rax),%eax\nadd %edx,%eax\ncmp %eax,%ecx\njge 153c \nmov -0x7c(%rbp),%eax\nsub -0x60(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x30(%rbp),%rax\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%ecx\nmov -0x7c(%rbp),%eax\nsub -0x5c(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rdx\nmov -0x78(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x7c(%rbp),%eax\nsub -0x5c(%rbp),%eax\nlea -0x1(%rax),%esi\nadd %edx,%ecx\nmov -0x30(%rbp),%rax\nmovslq %esi,%rdx\nmov %ecx,(%rax,%rdx,4)\naddl $0x1,-0x60(%rbp)\nmov -0x60(%rbp),%eax\ncmp -0x5c(%rbp),%eax\njl 147c \naddl $0x1,-0x5c(%rbp)\nmov -0x5c(%rbp),%eax\ncmp -0x7c(%rbp),%eax\njl 1470 \nmovl $0xfa0a1f01,-0x64(%rbp)\nmovl $0x0,-0x68(%rbp)\njmp 15e6 \nmov -0x40(%rbp),%rax\nmov -0x68(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%ecx\nmov -0x30(%rbp),%rax\nmov -0x68(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nlea (%rcx,%rax,1),%edx\nmov -0x68(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x78(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\nsub %eax,%edx\nmov %edx,%eax\ncmp %eax,-0x64(%rbp)\njge 15e2 \nmov -0x40(%rbp),%rax\nmov -0x68(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%ecx\nmov -0x30(%rbp),%rax\nmov -0x68(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nlea (%rcx,%rax,1),%edx\nmov -0x68(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x78(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\nsub %eax,%edx\nmov %edx,%eax\nmov %eax,-0x64(%rbp)\naddl $0x1,-0x68(%rbp)\nmov -0x68(%rbp),%eax\ncmp -0x7c(%rbp),%eax\njl 156c \nmov -0x64(%rbp),%eax\nmov %r8,%rsp\nmov %rdi,%rsp\nmov -0x28(%rbp),%rdi\nxor %fs:0x28,%rdi\nje 160f \ncallq 1080 <__stack_chk_fail@plt>\nlea -0x18(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 60h\nmov [rbp+var_58], rdi\nmov [rbp+var_5C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rdi, rax\nmov eax, [rbp+var_5C]\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_28], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov esi, 10h\nmov edx, 0\ndiv rsi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11F6:\ncmp rsp, rdx\njz short loc_120D\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\njmp short loc_11F6\nloc_120D:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1237\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1237:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_20], rax\nmov [rbp+var_48], 0\njmp short loc_127A\nloc_1253:\nmov eax, [rbp+var_48]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov ecx, [rax]\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_48]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nadd [rbp+var_48], 1\nloc_127A:\nmov eax, [rbp+var_48]\ncmp eax, [rbp+var_5C]\njl short loc_1253\nmov [rbp+var_44], 1\njmp loc_1347\nloc_128E:\nmov [rbp+var_40], 0\njmp loc_1337\nloc_129A:\nmov eax, [rbp+var_44]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_40]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_1333\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_44]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_40]\nmovsxd rdx, edx\nmov edx, [rax+rdx*4]\nmov eax, [rbp+var_44]\ncdqe\nlea rsi, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rsi\nmov eax, [rax]\nadd eax, edx\ncmp ecx, eax\njge short loc_1333\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_40]\nmovsxd rdx, edx\nmov edx, [rax+rdx*4]\nmov eax, [rbp+var_44]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rcx\nmov eax, [rax]\nlea ecx, [rdx+rax]\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_44]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nloc_1333:\nadd [rbp+var_40], 1\nloc_1337:\nmov eax, [rbp+var_40]\ncmp eax, [rbp+var_44]\njl loc_129A\nadd [rbp+var_44], 1\nloc_1347:\nmov eax, [rbp+var_44]\ncmp eax, [rbp+var_5C]\njl loc_128E\nmov eax, [rbp+var_5C]\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov esi, 10h\nmov edx, 0\ndiv rsi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_1398:\ncmp rsp, rdx\njz short loc_13AF\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\njmp short loc_1398\nloc_13AF:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_13D9\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_13D9:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov [rbp+var_3C], 0\njmp short loc_141C\nloc_13F5:\nmov eax, [rbp+var_3C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov ecx, [rax]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_3C]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nadd [rbp+var_3C], 1\nloc_141C:\nmov eax, [rbp+var_3C]\ncmp eax, [rbp+var_5C]\njl short loc_13F5\nmov [rbp+var_38], 1\njmp loc_1510\nloc_1430:\nmov [rbp+var_34], 0\njmp loc_1500\nloc_143C:\nmov eax, [rbp+var_5C]\nsub eax, [rbp+var_38]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_5C]\nsub eax, [rbp+var_34]\ncdqe\nshl rax, 2\nlea rcx, [rax-4]\nmov rax, [rbp+var_58]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle loc_14FC\nmov eax, [rbp+var_5C]\nsub eax, [rbp+var_38]\nlea edx, [rax-1]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov eax, [rbp+var_5C]\nsub eax, [rbp+var_34]\nlea edx, [rax-1]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov edx, [rax+rdx*4]\nmov eax, [rbp+var_5C]\nsub eax, [rbp+var_38]\ncdqe\nshl rax, 2\nlea rsi, [rax-4]\nmov rax, [rbp+var_58]\nadd rax, rsi\nmov eax, [rax]\nadd eax, edx\ncmp ecx, eax\njge short loc_14FC\nmov eax, [rbp+var_5C]\nsub eax, [rbp+var_34]\nlea edx, [rax-1]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov eax, [rbp+var_5C]\nsub eax, [rbp+var_38]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_5C]\nsub eax, [rbp+var_38]\nlea esi, [rax-1]\nadd ecx, edx\nmov rax, [rbp+var_10]\nmovsxd rdx, esi\nmov [rax+rdx*4], ecx\nloc_14FC:\nadd [rbp+var_34], 1\nloc_1500:\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_38]\njl loc_143C\nadd [rbp+var_38], 1\nloc_1510:\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_5C]\njl loc_1430\nmov [rbp+var_30], 0FA0A1F01h\nmov [rbp+var_2C], 0\njmp short loc_15A2\nloc_152C:\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_2C]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_2C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nlea edx, [rcx+rax]\nmov eax, [rbp+var_2C]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rcx\nmov eax, [rax]\nsub edx, eax\ncmp [rbp+var_30], edx\njge short loc_159E\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_2C]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_2C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nlea edx, [rcx+rax]\nmov eax, [rbp+var_2C]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rcx\nmov eax, [rax]\nsub edx, eax\nmov [rbp+var_30], edx\nloc_159E:\nadd [rbp+var_2C], 1\nloc_15A2:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_5C]\njl short loc_152C\nmov eax, [rbp+var_30]\nmov rsp, rdi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_15C4\ncall ___stack_chk_fail\nlocret_15C4:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned __int64 v2; // rax\n void *v3; // rsp\n unsigned __int64 v4; // rax\n void *v5; // rsp\n _BYTE v7[4]; // [rsp+8h] [rbp-60h] BYREF\n int v8; // [rsp+Ch] [rbp-5Ch]\n __int64 v9; // [rsp+10h] [rbp-58h]\n int i; // [rsp+20h] [rbp-48h]\n int j; // [rsp+24h] [rbp-44h]\n int k; // [rsp+28h] [rbp-40h]\n int m; // [rsp+2Ch] [rbp-3Ch]\n int n; // [rsp+30h] [rbp-38h]\n int ii; // [rsp+34h] [rbp-34h]\n int v16; // [rsp+38h] [rbp-30h]\n int jj; // [rsp+3Ch] [rbp-2Ch]\n __int64 v18; // [rsp+40h] [rbp-28h]\n _BYTE *v19; // [rsp+48h] [rbp-20h]\n __int64 v20; // [rsp+50h] [rbp-18h]\n _BYTE *v21; // [rsp+58h] [rbp-10h]\n unsigned __int64 v22; // [rsp+60h] [rbp-8h]\n\n v9 = a1;\n v8 = a2;\n v22 = __readfsqword(0x28u);\n v18 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 0x10uLL);\n while ( v7 != &v7[-(v2 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = alloca(v2 & 0xFFF);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)&v7[(v2 & 0xFFF) - 8] = *(_QWORD *)&v7[(v2 & 0xFFF) - 8];\n v19 = v7;\n for ( i = 0; i < v8; ++i )\n *(_DWORD *)&v19[4 * i] = *(_DWORD *)(4LL * i + v9);\n for ( j = 1; j < v8; ++j )\n {\n for ( k = 0; k < j; ++k )\n {\n if ( *(_DWORD *)(4LL * j + v9) > *(_DWORD *)(4LL * k + v9)\n && *(_DWORD *)&v19[4 * j] < *(_DWORD *)&v19[4 * k] + *(_DWORD *)(4LL * j + v9) )\n {\n *(_DWORD *)&v19[4 * j] = *(_DWORD *)&v19[4 * k] + *(_DWORD *)(4LL * j + v9);\n }\n }\n }\n v20 = v8 - 1LL;\n v4 = 16 * ((4LL * v8 + 15) / 0x10uLL);\n while ( v7 != &v7[-(v4 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v5 = alloca(v4 & 0xFFF);\n if ( (v4 & 0xFFF) != 0 )\n *(_QWORD *)&v7[(v4 & 0xFFF) - 8] = *(_QWORD *)&v7[(v4 & 0xFFF) - 8];\n v21 = v7;\n for ( m = 0; m < v8; ++m )\n *(_DWORD *)&v21[4 * m] = *(_DWORD *)(4LL * m + v9);\n for ( n = 1; n < v8; ++n )\n {\n for ( ii = 0; ii < n; ++ii )\n {\n if ( *(_DWORD *)(4LL * (v8 - n) - 4 + v9) > *(_DWORD *)(4LL * (v8 - ii) - 4 + v9)\n && *(_DWORD *)&v21[4 * (v8 - n) - 4] < *(_DWORD *)&v21[4 * (v8 - ii) - 4] + *(_DWORD *)(4LL * (v8 - n) - 4 + v9) )\n {\n *(_DWORD *)&v21[4 * (v8 - n) - 4] = *(_DWORD *)(4LL * (v8 - n) - 4 + v9) + *(_DWORD *)&v21[4 * (v8 - ii) - 4];\n }\n }\n }\n v16 = -99999999;\n for ( jj = 0; jj < v8; ++jj )\n {\n if ( v16 < *(_DWORD *)&v19[4 * jj] + *(_DWORD *)&v21[4 * jj] - *(_DWORD *)(4LL * jj + v9) )\n v16 = *(_DWORD *)&v19[4 * jj] + *(_DWORD *)&v21[4 * jj] - *(_DWORD *)(4LL * jj + v9);\n }\n return (unsigned int)v16;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 60h\nmov [rbp+var_58], rdi\nmov [rbp+var_5C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rdi, rax\nmov eax, [rbp+var_5C]\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_28], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov esi, 10h\nmov edx, 0\ndiv rsi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11F6:\ncmp rsp, rdx\njz short loc_120D\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\njmp short loc_11F6\nloc_120D:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1237\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1237:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_20], rax\nmov [rbp+var_48], 0\njmp short loc_127A\nloc_1253:\nmov eax, [rbp+var_48]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov ecx, [rax]\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_48]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nadd [rbp+var_48], 1\nloc_127A:\nmov eax, [rbp+var_48]\ncmp eax, [rbp+var_5C]\njl short loc_1253\nmov [rbp+var_44], 1\njmp loc_1347\nloc_128E:\nmov [rbp+var_40], 0\njmp loc_1337\nloc_129A:\nmov eax, [rbp+var_44]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_40]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_1333\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_44]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_40]\nmovsxd rdx, edx\nmov edx, [rax+rdx*4]\nmov eax, [rbp+var_44]\ncdqe\nlea rsi, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rsi\nmov eax, [rax]\nadd eax, edx\ncmp ecx, eax\njge short loc_1333\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_40]\nmovsxd rdx, edx\nmov edx, [rax+rdx*4]\nmov eax, [rbp+var_44]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rcx\nmov eax, [rax]\nlea ecx, [rdx+rax]\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_44]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nloc_1333:\nadd [rbp+var_40], 1\nloc_1337:\nmov eax, [rbp+var_40]\ncmp eax, [rbp+var_44]\njl loc_129A\nadd [rbp+var_44], 1\nloc_1347:\nmov eax, [rbp+var_44]\ncmp eax, [rbp+var_5C]\njl loc_128E\nmov eax, [rbp+var_5C]\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov esi, 10h\nmov edx, 0\ndiv rsi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_1398:\ncmp rsp, rdx\njz short loc_13AF\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\njmp short loc_1398\nloc_13AF:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_13D9\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_13D9:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov [rbp+var_3C], 0\njmp short loc_141C\nloc_13F5:\nmov eax, [rbp+var_3C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov ecx, [rax]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_3C]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nadd [rbp+var_3C], 1\nloc_141C:\nmov eax, [rbp+var_3C]\ncmp eax, [rbp+var_5C]\njl short loc_13F5\nmov [rbp+var_38], 1\njmp loc_1510\nloc_1430:\nmov [rbp+var_34], 0\njmp loc_1500\nloc_143C:\nmov eax, [rbp+var_5C]\nsub eax, [rbp+var_38]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_5C]\nsub eax, [rbp+var_34]\ncdqe\nshl rax, 2\nlea rcx, [rax-4]\nmov rax, [rbp+var_58]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle loc_14FC\nmov eax, [rbp+var_5C]\nsub eax, [rbp+var_38]\nlea edx, [rax-1]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov eax, [rbp+var_5C]\nsub eax, [rbp+var_34]\nlea edx, [rax-1]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov edx, [rax+rdx*4]\nmov eax, [rbp+var_5C]\nsub eax, [rbp+var_38]\ncdqe\nshl rax, 2\nlea rsi, [rax-4]\nmov rax, [rbp+var_58]\nadd rax, rsi\nmov eax, [rax]\nadd eax, edx\ncmp ecx, eax\njge short loc_14FC\nmov eax, [rbp+var_5C]\nsub eax, [rbp+var_34]\nlea edx, [rax-1]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov eax, [rbp+var_5C]\nsub eax, [rbp+var_38]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_5C]\nsub eax, [rbp+var_38]\nlea esi, [rax-1]\nadd ecx, edx\nmov rax, [rbp+var_10]\nmovsxd rdx, esi\nmov [rax+rdx*4], ecx\nloc_14FC:\nadd [rbp+var_34], 1\nloc_1500:\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_38]\njl loc_143C\nadd [rbp+var_38], 1\nloc_1510:\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_5C]\njl loc_1430\nmov [rbp+var_30], 0FA0A1F01h\nmov [rbp+var_2C], 0\njmp short loc_15A2\nloc_152C:\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_2C]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_2C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nlea edx, [rcx+rax]\nmov eax, [rbp+var_2C]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rcx\nmov eax, [rax]\nsub edx, eax\ncmp [rbp+var_30], edx\njge short loc_159E\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_2C]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_2C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nlea edx, [rcx+rax]\nmov eax, [rbp+var_2C]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rcx\nmov eax, [rax]\nsub edx, eax\nmov [rbp+var_30], edx\nloc_159E:\nadd [rbp+var_2C], 1\nloc_15A2:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_5C]\njl short loc_152C\nmov eax, [rbp+var_30]\nmov rsp, rdi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_15C4\ncall ___stack_chk_fail\nlocret_15C4:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2)\n{\n unsigned __int64 v2; // rax\n void *v3; // rsp\n unsigned __int64 v4; // rax\n void *v5; // rsp\n _BYTE v7[4]; // [rsp+8h] [rbp-60h] BYREF\n int v8; // [rsp+Ch] [rbp-5Ch]\n __int64 v9; // [rsp+10h] [rbp-58h]\n int i; // [rsp+20h] [rbp-48h]\n int j; // [rsp+24h] [rbp-44h]\n int k; // [rsp+28h] [rbp-40h]\n int m; // [rsp+2Ch] [rbp-3Ch]\n int n; // [rsp+30h] [rbp-38h]\n int ii; // [rsp+34h] [rbp-34h]\n int v16; // [rsp+38h] [rbp-30h]\n int jj; // [rsp+3Ch] [rbp-2Ch]\n __int64 v18; // [rsp+40h] [rbp-28h]\n _BYTE *v19; // [rsp+48h] [rbp-20h]\n __int64 v20; // [rsp+50h] [rbp-18h]\n _BYTE *v21; // [rsp+58h] [rbp-10h]\n unsigned __int64 v22; // [rsp+60h] [rbp-8h]\n\n v9 = a1;\n v8 = a2;\n v22 = __readfsqword(0x28u);\n v18 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 0x10uLL);\n while ( v7 != &v7[-(v2 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = alloca(v2 & 0xFFF);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)&v7[(v2 & 0xFFF) - 8] = *(_QWORD *)&v7[(v2 & 0xFFF) - 8];\n v19 = v7;\n for ( i = 0; i < v8; ++i )\n *(_DWORD *)&v19[4 * i] = *(_DWORD *)(4LL * i + v9);\n for ( j = 1; j < v8; ++j )\n {\n for ( k = 0; k < j; ++k )\n {\n if ( *(_DWORD *)(4LL * j + v9) > *(_DWORD *)(4LL * k + v9)\n && *(_DWORD *)&v19[4 * j] < *(_DWORD *)&v19[4 * k] + *(_DWORD *)(4LL * j + v9) )\n {\n *(_DWORD *)&v19[4 * j] = *(_DWORD *)&v19[4 * k] + *(_DWORD *)(4LL * j + v9);\n }\n }\n }\n v20 = v8 - 1LL;\n v4 = 16 * ((4LL * v8 + 15) / 0x10uLL);\n while ( v7 != &v7[-(v4 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v5 = alloca(v4 & 0xFFF);\n if ( (v4 & 0xFFF) != 0 )\n *(_QWORD *)&v7[(v4 & 0xFFF) - 8] = *(_QWORD *)&v7[(v4 & 0xFFF) - 8];\n v21 = v7;\n for ( m = 0; m < v8; ++m )\n *(_DWORD *)&v21[4 * m] = *(_DWORD *)(4LL * m + v9);\n for ( n = 1; n < v8; ++n )\n {\n for ( ii = 0; ii < n; ++ii )\n {\n if ( *(_DWORD *)(4LL * (v8 - n) - 4 + v9) > *(_DWORD *)(4LL * (v8 - ii) - 4 + v9)\n && *(_DWORD *)&v21[4 * (v8 - n) - 4] < *(_DWORD *)&v21[4 * (v8 - ii) - 4] + *(_DWORD *)(4LL * (v8 - n) - 4 + v9) )\n {\n *(_DWORD *)&v21[4 * (v8 - n) - 4] = *(_DWORD *)(4LL * (v8 - n) - 4 + v9) + *(_DWORD *)&v21[4 * (v8 - ii) - 4];\n }\n }\n }\n v16 = -99999999;\n for ( jj = 0; jj < v8; ++jj )\n {\n if ( v16 < *(_DWORD *)&v19[4 * jj] + *(_DWORD *)&v21[4 * jj] - *(_DWORD *)(4LL * jj + v9) )\n v16 = *(_DWORD *)&v19[4 * jj] + *(_DWORD *)&v21[4 * jj] - *(_DWORD *)(4LL * jj + v9);\n }\n return (unsigned int)v16;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2) {\n unsigned long long v2;\n void *v3;\n unsigned long long v4;\n void *v5;\n uint8_t v7[4];\n int v8;\n long long v9;\n int i;\n int j;\n int k;\n int m;\n int n;\n int ii;\n int v16;\n int jj;\n long long v18;\n uint8_t *v19;\n long long v20;\n uint8_t *v21;\n unsigned long long v22;\n v9 = a1;\n v8 = a2;\n v22 = __readfsqword(40u);\n v18 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 16uLL);\n while (v7 != &v7[-(v2 & 18446744073709547520LL)])\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)&v7[(v2 & 4095) - 8] = *(uint64_t *)&v7[(v2 & 4095) - 8];\n v19 = v7;\n for (i = 0; i < v8; ++i)\n *(uint32_t *)&v19[4 * i] = *(uint32_t *)(4LL * i + v9);\n for (j = 1; j < v8; ++j) {\n for (k = 0; k < j; ++k) {\n if (*(uint32_t *)(4LL * j + v9) > *(uint32_t *)(4LL * k + v9) &&\n *(uint32_t *)&v19[4 * j] <\n *(uint32_t *)&v19[4 * k] + *(uint32_t *)(4LL * j + v9)) {\n *(uint32_t *)&v19[4 * j] =\n *(uint32_t *)&v19[4 * k] + *(uint32_t *)(4LL * j + v9);\n }\n }\n }\n v20 = v8 - 1LL;\n v4 = 16 * ((4LL * v8 + 15) / 16uLL);\n while (v7 != &v7[-(v4 & 18446744073709547520LL)])\n ;\n v5 = alloca(v4 & 4095);\n if ((v4 & 4095) != 0)\n *(uint64_t *)&v7[(v4 & 4095) - 8] = *(uint64_t *)&v7[(v4 & 4095) - 8];\n v21 = v7;\n for (m = 0; m < v8; ++m)\n *(uint32_t *)&v21[4 * m] = *(uint32_t *)(4LL * m + v9);\n for (n = 1; n < v8; ++n) {\n for (ii = 0; ii < n; ++ii) {\n if (*(uint32_t *)(4LL * (v8 - n) - 4 + v9) >\n *(uint32_t *)(4LL * (v8 - ii) - 4 + v9) &&\n *(uint32_t *)&v21[4 * (v8 - n) - 4] <\n *(uint32_t *)&v21[4 * (v8 - ii) - 4] +\n *(uint32_t *)(4LL * (v8 - n) - 4 + v9)) {\n *(uint32_t *)&v21[4 * (v8 - n) - 4] =\n *(uint32_t *)(4LL * (v8 - n) - 4 + v9) +\n *(uint32_t *)&v21[4 * (v8 - ii) - 4];\n }\n }\n }\n v16 = -99999999;\n for (jj = 0; jj < v8; ++jj) {\n if (v16 < *(uint32_t *)&v19[4 * jj] + *(uint32_t *)&v21[4 * jj] -\n *(uint32_t *)(4LL * jj + v9))\n v16 = *(uint32_t *)&v19[4 * jj] + *(uint32_t *)&v21[4 * jj] -\n *(uint32_t *)(4LL * jj + v9);\n }\n return (unsigned int)v16;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned long long v2;\n void *v3;\n unsigned long long v4;\n void *v5;\n uint8_t v7[4];\n int v8;\n long long v9;\n int i;\n int j;\n int k;\n int m;\n int n;\n int ii;\n int v16;\n int jj;\n long long v18;\n uint8_t *v19;\n long long v20;\n uint8_t *v21;\n unsigned long long v22;\n v9 = a1;\n v8 = a2;\n v22 = __readfsqword(40u);\n v18 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 16uLL);\n while (v7 != &v7[-(v2 & 18446744073709547520LL)])\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)&v7[(v2 & 4095) - 8] = *(uint64_t *)&v7[(v2 & 4095) - 8];\n v19 = v7;\n for (i = 0; i < v8; ++i)\n *(uint32_t *)&v19[4 * i] = *(uint32_t *)(4LL * i + v9);\n for (j = 1; j < v8; ++j) {\n for (k = 0; k < j; ++k) {\n if (*(uint32_t *)(4LL * j + v9) > *(uint32_t *)(4LL * k + v9) &&\n *(uint32_t *)&v19[4 * j] <\n *(uint32_t *)&v19[4 * k] + *(uint32_t *)(4LL * j + v9)) {\n *(uint32_t *)&v19[4 * j] =\n *(uint32_t *)&v19[4 * k] + *(uint32_t *)(4LL * j + v9);\n }\n }\n }\n v20 = v8 - 1LL;\n v4 = 16 * ((4LL * v8 + 15) / 16uLL);\n while (v7 != &v7[-(v4 & 18446744073709547520LL)])\n ;\n v5 = alloca(v4 & 4095);\n if ((v4 & 4095) != 0)\n *(uint64_t *)&v7[(v4 & 4095) - 8] = *(uint64_t *)&v7[(v4 & 4095) - 8];\n v21 = v7;\n for (m = 0; m < v8; ++m)\n *(uint32_t *)&v21[4 * m] = *(uint32_t *)(4LL * m + v9);\n for (n = 1; n < v8; ++n) {\n for (ii = 0; ii < n; ++ii) {\n if (*(uint32_t *)(4LL * (v8 - n) - 4 + v9) >\n *(uint32_t *)(4LL * (v8 - ii) - 4 + v9) &&\n *(uint32_t *)&v21[4 * (v8 - n) - 4] <\n *(uint32_t *)&v21[4 * (v8 - ii) - 4] +\n *(uint32_t *)(4LL * (v8 - n) - 4 + v9)) {\n *(uint32_t *)&v21[4 * (v8 - n) - 4] =\n *(uint32_t *)(4LL * (v8 - n) - 4 + v9) +\n *(uint32_t *)&v21[4 * (v8 - ii) - 4];\n }\n }\n }\n v16 = -99999999;\n for (jj = 0; jj < v8; ++jj) {\n if (v16 < *(uint32_t *)&v19[4 * jj] + *(uint32_t *)&v21[4 * jj] -\n *(uint32_t *)(4LL * jj + v9))\n v16 = *(uint32_t *)&v19[4 * jj] + *(uint32_t *)&v21[4 * jj] -\n *(uint32_t *)(4LL * jj + v9);\n }\n return (unsigned int)v16;\n}" + }, + { + "index": 245, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int MSIBS[n];\n for (int i = 0; i < n; i++) {\n MSIBS[i] = arr[i];\n }\n for (int i = 1; i < n; i++) {\n for (int j = 0; j < i; j++) {\n if (arr[i] > arr[j] && MSIBS[i] < MSIBS[j] + arr[i]) {\n MSIBS[i] = MSIBS[j] + arr[i];\n }\n }\n }\n int MSDBS[n];\n for (int i = 0; i < n; i++) {\n MSDBS[i] = arr[i];\n }\n for (int i = 1; i < n; i++) {\n for (int j = 0; j < i; j++) {\n if (arr[n - i - 1] > arr[n - j - 1] &&\n MSDBS[n - i - 1] < MSDBS[n - j - 1] + arr[n - i - 1]) {\n MSDBS[n - i - 1] = MSDBS[n - j - 1] + arr[n - i - 1];\n }\n }\n }\n int max_sum = -99999999;\n for (int i = 0; i < n; i++) {\n if (max_sum < MSIBS[i] + MSDBS[i] - arr[i]) {\n max_sum = MSIBS[i] + MSDBS[i] - arr[i];\n }\n }\n return max_sum;\n}", + "test": "int main() {\n\n assert(func0((int[]){1, 15, 51, 45, 33, 100, 12, 18, 9}, 9) == 194);\n\n assert(func0((int[]){80, 60, 30, 40, 20, 10}, 6) == 210);\n\n assert(func0((int[]){2, 3, 14, 16, 21, 23, 29, 30}, 8) == 138);\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x28(%rbp)\nxor %eax,%eax\nmovslq %esi,%r12\nshl $0x2,%r12\nlea 0xf(%r12),%rax\nmov %rax,%rdx\nand $0xfffffffffffffff0,%rdx\nand $0xfffffffffffff000,%rax\nmov %rsp,%rbx\nsub %rax,%rbx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 11e4 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11cd \nmov %rdx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 11fa \norq $0x0,-0x8(%rsp,%rax,1)\nlea 0x3(%rsp),%r9\nmov %r9,%r10\nshr $0x2,%r10\nand $0xfffffffffffffffc,%r9\ntest %esi,%esi\njle 1229 \nlea -0x1(%rsi),%ecx\nmov $0x0,%eax\nmov (%rdi,%rax,4),%edx\nmov %edx,(%r9,%rax,4)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rcx,%rdx\njne 1216 \ncmp $0x1,%esi\njle 1279 \nlea -0x2(%rsi),%r11d\nadd $0x2,%r11\nmov $0x1,%edx\njmp 126b \nadd $0x1,%rax\ncmp %rdx,%rax\nje 125e \ncmp (%rdi,%rax,4),%ecx\njle 123d \nmov %ecx,%r8d\nadd (%r9,%rax,4),%r8d\ncmp %r8d,(%r9,%rdx,4)\njge 123d \nmov %r8d,(%r9,%rdx,4)\njmp 123d \nadd $0x1,%rdx\ncmp %r11,%rdx\nje 137f \ntest %edx,%edx\njle 125e \nmov (%rdi,%rdx,4),%ecx\nmov $0x0,%eax\njmp 1246 \nlea 0xf(%r12),%rdx\nmov %rdx,%rax\nand $0xfffffffffffffff0,%rax\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rbx\nsub %rdx,%rbx\nmov %rbx,%rdx\ncmp %rdx,%rsp\nje 12ac \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 1295 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\nje 12c3 \norq $0x0,-0x8(%rsp,%rdx,1)\nlea 0x3(%rsp),%r11\nmov %r11,%rax\nshr $0x2,%rax\nand $0xfffffffffffffffc,%r11\ncmp $0x1,%esi\nje 1416 \ncmp $0x1,%esi\nje 13f6 \nmov $0xfa0a1f01,%ecx\njmp 135d \nsub $0x4,%rdx\nsub $0x1,%eax\ncmp %ecx,%eax\nje 1311 \ncmp -0x4(%rdx),%r8d\njle 12ec \nmovslq %eax,%r10\nmov %r8d,%r14d\nadd (%r11,%r10,4),%r14d\ncmp %r14d,(%rbx)\njge 12ec \nmov %r14d,(%rbx)\njmp 12ec \nsub $0x1,%ecx\ncmp $0xffffffff,%ecx\nje 133b \nmov %r13d,%eax\nsub %ecx,%eax\ntest %eax,%eax\njle 1311 \nlea 0x1(%rcx),%eax\ncltq\nmov -0x4(%rdi,%rax,4),%r8d\nlea -0x1(%rsi),%eax\nmov %r12,%rdx\nmovslq %ecx,%r10\nlea (%r11,%r10,4),%rbx\njmp 12f7 \nmov $0x0,%edx\nmov $0xfa0a1f01,%ecx\nmov (%r11,%rdx,4),%eax\nadd (%r9,%rdx,4),%eax\nsub (%rdi,%rdx,4),%eax\ncmp %eax,%ecx\ncmovl %eax,%ecx\nadd $0x1,%rdx\ncmp %edx,%esi\njg 1345 \nmov -0x28(%rbp),%rax\nxor %fs:0x28,%rax\njne 1421 \nmov %ecx,%eax\nlea -0x20(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %rbp\nretq\nlea 0xf(%r12),%rax\nmov %rax,%rdx\nand $0xfffffffffffffff0,%rdx\nand $0xfffffffffffff000,%rax\nmov %rsp,%rbx\nsub %rax,%rbx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 13b1 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 139a \nmov %rdx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 13c7 \norq $0x0,-0x8(%rsp,%rax,1)\nmov %rsp,%r11\nmov $0x0,%eax\nmov (%rdi,%rax,4),%edx\nmov %edx,(%r11,%rax,4)\nadd $0x1,%rax\ncmp %eax,%esi\njg 13cf \ncmp $0x1,%esi\njle 12dc \nlea -0x2(%rsi),%ecx\nadd %rdi,%r12\nlea -0x1(%rsi),%r13d\njmpq 1319 \nmov (%r11),%ecx\nadd 0x0(,%r10,4),%ecx\nsub (%rdi),%ecx\ncmp $0xfa0a1f01,%ecx\nmov $0xfa0a1f01,%eax\ncmovl %eax,%ecx\njmpq 135d \nmov (%rdi),%edx\nmov %edx,0x0(,%rax,4)\njmp 13de \ncallq 1080 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 18h\nmov ebx, esi\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nmovsxd r11, esi\nshl r11, 2\nlea rax, [r11+0Fh]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11CD:\ncmp rsp, rdx\njz short loc_11E4\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_11CD\nloc_11E4:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11FA\nor [rsp+rax+40h+var_48], 0\nloc_11FA:\nmov r8, rsp\ntest ebx, ebx\njle loc_12BE\nmov eax, 0\nloc_120A:\nmov edx, [rdi+rax]\nmov [r8+rax], edx\nadd rax, 4\ncmp r11, rax\njnz short loc_120A\ncmp ebx, 1\njle loc_1311\nmov edx, 4\nmov r9d, 1\njmp short loc_1261\nloc_1230:\nadd rax, 4\ncmp rax, rdx\njz short loc_1250\nloc_1239:\ncmp ecx, [rdi+rax]\njle short loc_1230\nmov esi, ecx\nadd esi, [r8+rax]\ncmp [r8+rdx], esi\njge short loc_1230\nmov [r8+rdx], esi\njmp short loc_1230\nloc_1250:\nadd r9d, 1\nadd rdx, 4\ncmp ebx, r9d\njz loc_1311\nloc_1261:\ntest r9d, r9d\njle loc_1387\nmov ecx, [rdi+rdx]\nmov eax, 0\njmp short loc_1239\nloc_1274:\nsub rdx, 4\nsub eax, 1\ncmp eax, ecx\njz short loc_1299\nloc_127F:\ncmp esi, [rdx]\njle short loc_1274\nmovsxd r10, eax\nmov r15d, esi\nadd r15d, [r9+r10*4]\ncmp [r9+r12*4], r15d\njge short loc_1274\nmov [r9+r12*4], r15d\njmp short loc_1274\nloc_1299:\nsub ecx, 1\ncmp ecx, 0FFFFFFFFh\njz short loc_12C5\nloc_12A1:\nmov eax, r13d\nsub eax, ecx\ntest eax, eax\njle short loc_130C\nlea eax, [rcx+1]\ncdqe\nmov esi, [rdi+rax*4-4]\nlea eax, [rbx-1]\nmov rdx, r14\nmovsxd r12, ecx\njmp short loc_127F\nloc_12BE:\nmov ecx, 0FA0A1F01h\njmp short loc_12E8\nloc_12C5:\nmov edx, 0\nmov ecx, 0FA0A1F01h\nloc_12CF:\nmov eax, [r9+rdx]\nadd eax, [r8+rdx]\nsub eax, [rdi+rdx]\ncmp ecx, eax\ncmovl ecx, eax\nadd rdx, 4\ncmp r11, rdx\njnz short loc_12CF\nloc_12E8:\nmov rax, [rbp+var_38]\nsub rax, fs:28h\njnz loc_1394\nmov eax, ecx\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_130C:\nsub ecx, 1\njmp short loc_12A1\nloc_1311:\nlea rax, [r11+0Fh]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_1328:\ncmp rsp, rdx\njz short loc_133F\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_1328\nloc_133F:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_1355\nor [rsp+rax+40h+var_48], 0\nloc_1355:\nmov r9, rsp\nmov eax, 0\nloc_135D:\nmov edx, [rdi+rax]\nmov [r9+rax], edx\nadd rax, 4\ncmp r11, rax\njnz short loc_135D\ncmp ebx, 1\njle loc_12C5\nlea ecx, [rbx-2]\nlea r14, [rdi+r11-4]\nlea r13d, [rbx-1]\njmp loc_12A1\nloc_1387:\nadd r9d, 1\nadd rdx, 4\njmp loc_1261\nloc_1394:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v3; // r11\n signed __int64 v4; // rax\n void *v5; // rsp\n __int64 v6; // rax\n __int64 v7; // rdx\n int i; // r9d\n __int64 v9; // rax\n int v10; // esi\n int v11; // ecx\n _DWORD *v12; // rdx\n int v13; // eax\n int v14; // r15d\n int v15; // ecx\n int v16; // esi\n int v17; // ecx\n __int64 v18; // rdx\n signed __int64 v20; // rax\n void *v21; // rsp\n __int64 v22; // rax\n _BYTE v24[8]; // [rsp+8h] [rbp-40h] BYREF\n unsigned __int64 v25; // [rsp+10h] [rbp-38h]\n\n v25 = __readfsqword(0x28u);\n v3 = 4LL * a2;\n while ( v24 != &v24[-((v3 + 15) & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v4 = ((_WORD)v3 + 15) & 0xFF0;\n v5 = alloca(v4);\n if ( (((_WORD)v3 + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v24[v4 - 8] = *(_QWORD *)&v24[v4 - 8];\n if ( a2 <= 0 )\n {\n return (unsigned int)-99999999;\n }\n else\n {\n v6 = 0LL;\n do\n {\n *(_DWORD *)&v24[v6] = *(_DWORD *)(a1 + v6);\n v6 += 4LL;\n }\n while ( v3 != v6 );\n if ( a2 > 1 )\n {\n v7 = 4LL;\n for ( i = 1; i != a2; ++i )\n {\n while ( i <= 0 )\n {\n ++i;\n v7 += 4LL;\n }\n v11 = *(_DWORD *)(a1 + v7);\n v9 = 0LL;\n do\n {\n if ( v11 > *(_DWORD *)(a1 + v9) )\n {\n v10 = *(_DWORD *)&v24[v9] + v11;\n if ( *(_DWORD *)&v24[v7] < v10 )\n *(_DWORD *)&v24[v7] = v10;\n }\n v9 += 4LL;\n }\n while ( v9 != v7 );\n v7 += 4LL;\n }\n }\n while ( v24 != &v24[-((v3 + 15) & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v20 = ((_WORD)v3 + 15) & 0xFF0;\n v21 = alloca(v20);\n if ( (((_WORD)v3 + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v24[v20 - 8] = *(_QWORD *)&v24[v20 - 8];\n v22 = 0LL;\n do\n {\n *(_DWORD *)&v24[v22] = *(_DWORD *)(a1 + v22);\n v22 += 4LL;\n }\n while ( v3 != v22 );\n if ( a2 > 1 )\n {\n v15 = a2 - 2;\n do\n {\n while ( a2 - 1 - v15 <= 0 )\n --v15;\n v16 = *(_DWORD *)(a1 + 4LL * (v15 + 1) - 4);\n v13 = a2 - 1;\n v12 = (_DWORD *)(a1 + v3 - 4);\n do\n {\n if ( v16 > *v12 )\n {\n v14 = *(_DWORD *)&v24[4 * v13] + v16;\n if ( *(_DWORD *)&v24[4 * v15] < v14 )\n *(_DWORD *)&v24[4 * v15] = v14;\n }\n --v12;\n --v13;\n }\n while ( v13 != v15 );\n --v15;\n }\n while ( v15 != -1 );\n }\n v18 = 0LL;\n v17 = -99999999;\n do\n {\n if ( v17 < 2 * *(_DWORD *)&v24[v18] - *(_DWORD *)(a1 + v18) )\n v17 = 2 * *(_DWORD *)&v24[v18] - *(_DWORD *)(a1 + v18);\n v18 += 4LL;\n }\n while ( v3 != v18 );\n }\n return (unsigned int)v17;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 18h\nmov ebx, esi\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nmovsxd r11, esi\nshl r11, 2\nlea rax, [r11+0Fh]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11CD:\ncmp rsp, rdx\njz short loc_11E4\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_11CD\nloc_11E4:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11FA\nor [rsp+rax+40h+var_48], 0\nloc_11FA:\nmov r8, rsp\ntest ebx, ebx\njle loc_12BE\nmov eax, 0\nloc_120A:\nmov edx, [rdi+rax]\nmov [r8+rax], edx\nadd rax, 4\ncmp r11, rax\njnz short loc_120A\ncmp ebx, 1\njle loc_1311\nmov edx, 4\nmov r9d, 1\njmp short loc_1261\nloc_1230:\nadd rax, 4\ncmp rax, rdx\njz short loc_1250\nloc_1239:\ncmp ecx, [rdi+rax]\njle short loc_1230\nmov esi, ecx\nadd esi, [r8+rax]\ncmp [r8+rdx], esi\njge short loc_1230\nmov [r8+rdx], esi\njmp short loc_1230\nloc_1250:\nadd r9d, 1\nadd rdx, 4\ncmp ebx, r9d\njz loc_1311\nloc_1261:\ntest r9d, r9d\njle loc_1387\nmov ecx, [rdi+rdx]\nmov eax, 0\njmp short loc_1239\nloc_1274:\nsub rdx, 4\nsub eax, 1\ncmp eax, ecx\njz short loc_1299\nloc_127F:\ncmp esi, [rdx]\njle short loc_1274\nmovsxd r10, eax\nmov r15d, esi\nadd r15d, [r9+r10*4]\ncmp [r9+r12*4], r15d\njge short loc_1274\nmov [r9+r12*4], r15d\njmp short loc_1274\nloc_1299:\nsub ecx, 1\ncmp ecx, 0FFFFFFFFh\njz short loc_12C5\nloc_12A1:\nmov eax, r13d\nsub eax, ecx\ntest eax, eax\njle short loc_130C\nlea eax, [rcx+1]\ncdqe\nmov esi, [rdi+rax*4-4]\nlea eax, [rbx-1]\nmov rdx, r14\nmovsxd r12, ecx\njmp short loc_127F\nloc_12BE:\nmov ecx, 0FA0A1F01h\njmp short loc_12E8\nloc_12C5:\nmov edx, 0\nmov ecx, 0FA0A1F01h\nloc_12CF:\nmov eax, [r9+rdx]\nadd eax, [r8+rdx]\nsub eax, [rdi+rdx]\ncmp ecx, eax\ncmovl ecx, eax\nadd rdx, 4\ncmp r11, rdx\njnz short loc_12CF\nloc_12E8:\nmov rax, [rbp+var_38]\nsub rax, fs:28h\njnz loc_1394\nmov eax, ecx\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_130C:\nsub ecx, 1\njmp short loc_12A1\nloc_1311:\nlea rax, [r11+0Fh]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_1328:\ncmp rsp, rdx\njz short loc_133F\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_1328\nloc_133F:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_1355\nor [rsp+rax+40h+var_48], 0\nloc_1355:\nmov r9, rsp\nmov eax, 0\nloc_135D:\nmov edx, [rdi+rax]\nmov [r9+rax], edx\nadd rax, 4\ncmp r11, rax\njnz short loc_135D\ncmp ebx, 1\njle loc_12C5\nlea ecx, [rbx-2]\nlea r14, [rdi+r11-4]\nlea r13d, [rbx-1]\njmp loc_12A1\nloc_1387:\nadd r9d, 1\nadd rdx, 4\njmp loc_1261\nloc_1394:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2)\n{\n __int64 v3; // r11\n signed __int64 v4; // rax\n void *v5; // rsp\n __int64 v6; // rax\n __int64 v7; // rdx\n int i; // r9d\n __int64 v9; // rax\n int v10; // esi\n int v11; // ecx\n _DWORD *v12; // rdx\n int v13; // eax\n int v14; // r15d\n int v15; // ecx\n int v16; // esi\n int v17; // ecx\n __int64 v18; // rdx\n signed __int64 v20; // rax\n void *v21; // rsp\n __int64 v22; // rax\n _BYTE v24[8]; // [rsp+8h] [rbp-40h] BYREF\n unsigned __int64 v25; // [rsp+10h] [rbp-38h]\n\n v25 = __readfsqword(0x28u);\n v3 = 4LL * a2;\n while ( v24 != &v24[-((v3 + 15) & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v4 = ((_WORD)v3 + 15) & 0xFF0;\n v5 = alloca(v4);\n if ( (((_WORD)v3 + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v24[v4 - 8] = *(_QWORD *)&v24[v4 - 8];\n if ( a2 <= 0 )\n {\n return (unsigned int)-99999999;\n }\n else\n {\n v6 = 0LL;\n do\n {\n *(_DWORD *)&v24[v6] = *(_DWORD *)(a1 + v6);\n v6 += 4LL;\n }\n while ( v3 != v6 );\n if ( a2 > 1 )\n {\n v7 = 4LL;\n for ( i = 1; i != a2; ++i )\n {\n while ( i <= 0 )\n {\n ++i;\n v7 += 4LL;\n }\n v11 = *(_DWORD *)(a1 + v7);\n v9 = 0LL;\n do\n {\n if ( v11 > *(_DWORD *)(a1 + v9) )\n {\n v10 = *(_DWORD *)&v24[v9] + v11;\n if ( *(_DWORD *)&v24[v7] < v10 )\n *(_DWORD *)&v24[v7] = v10;\n }\n v9 += 4LL;\n }\n while ( v9 != v7 );\n v7 += 4LL;\n }\n }\n while ( v24 != &v24[-((v3 + 15) & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v20 = ((_WORD)v3 + 15) & 0xFF0;\n v21 = alloca(v20);\n if ( (((_WORD)v3 + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v24[v20 - 8] = *(_QWORD *)&v24[v20 - 8];\n v22 = 0LL;\n do\n {\n *(_DWORD *)&v24[v22] = *(_DWORD *)(a1 + v22);\n v22 += 4LL;\n }\n while ( v3 != v22 );\n if ( a2 > 1 )\n {\n v15 = a2 - 2;\n do\n {\n while ( a2 - 1 - v15 <= 0 )\n --v15;\n v16 = *(_DWORD *)(a1 + 4LL * (v15 + 1) - 4);\n v13 = a2 - 1;\n v12 = (_DWORD *)(a1 + v3 - 4);\n do\n {\n if ( v16 > *v12 )\n {\n v14 = *(_DWORD *)&v24[4 * v13] + v16;\n if ( *(_DWORD *)&v24[4 * v15] < v14 )\n *(_DWORD *)&v24[4 * v15] = v14;\n }\n --v12;\n --v13;\n }\n while ( v13 != v15 );\n --v15;\n }\n while ( v15 != -1 );\n }\n v18 = 0LL;\n v17 = -99999999;\n do\n {\n if ( v17 < 2 * *(_DWORD *)&v24[v18] - *(_DWORD *)(a1 + v18) )\n v17 = 2 * *(_DWORD *)&v24[v18] - *(_DWORD *)(a1 + v18);\n v18 += 4LL;\n }\n while ( v3 != v18 );\n }\n return (unsigned int)v17;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2) {\n long long v3;\n signed long long v4;\n void *v5;\n long long v6;\n long long v7;\n int i;\n long long v9;\n int v10;\n int v11;\n uint32_t *v12;\n int v13;\n int v14;\n int v15;\n int v16;\n int v17;\n long long v18;\n signed long long v20;\n void *v21;\n long long v22;\n uint8_t v24[8];\n unsigned long long v25;\n v25 = __readfsqword(40u);\n v3 = 4LL * a2;\n while (v24 != &v24[-((v3 + 15) & 18446744073709547520LL)])\n ;\n v4 = ((unsigned short)v3 + 15) & 4080;\n v5 = alloca(v4);\n if ((((unsigned short)v3 + 15) & 4080) != 0)\n *(uint64_t *)&v24[v4 - 8] = *(uint64_t *)&v24[v4 - 8];\n if (a2 <= 0) {\n return (unsigned int)-99999999;\n } else {\n v6 = 0LL;\n do {\n *(uint32_t *)&v24[v6] = *(uint32_t *)(a1 + v6);\n v6 += 4LL;\n } while (v3 != v6);\n if (a2 > 1) {\n v7 = 4LL;\n for (i = 1; i != a2; ++i) {\n while (i <= 0) {\n ++i;\n v7 += 4LL;\n }\n v11 = *(uint32_t *)(a1 + v7);\n v9 = 0LL;\n do {\n if (v11 > *(uint32_t *)(a1 + v9)) {\n v10 = *(uint32_t *)&v24[v9] + v11;\n if (*(uint32_t *)&v24[v7] < v10) *(uint32_t *)&v24[v7] = v10;\n }\n v9 += 4LL;\n } while (v9 != v7);\n v7 += 4LL;\n }\n }\n while (v24 != &v24[-((v3 + 15) & 18446744073709547520LL)])\n ;\n v20 = ((unsigned short)v3 + 15) & 4080;\n v21 = alloca(v20);\n if ((((unsigned short)v3 + 15) & 4080) != 0)\n *(uint64_t *)&v24[v20 - 8] = *(uint64_t *)&v24[v20 - 8];\n v22 = 0LL;\n do {\n *(uint32_t *)&v24[v22] = *(uint32_t *)(a1 + v22);\n v22 += 4LL;\n } while (v3 != v22);\n if (a2 > 1) {\n v15 = a2 - 2;\n do {\n while (a2 - 1 - v15 <= 0) --v15;\n v16 = *(uint32_t *)(a1 + 4LL * (v15 + 1) - 4);\n v13 = a2 - 1;\n v12 = (uint32_t *)(a1 + v3 - 4);\n do {\n if (v16 > *v12) {\n v14 = *(uint32_t *)&v24[4 * v13] + v16;\n if (*(uint32_t *)&v24[4 * v15] < v14)\n *(uint32_t *)&v24[4 * v15] = v14;\n }\n --v12;\n --v13;\n } while (v13 != v15);\n --v15;\n } while (v15 != -1);\n }\n v18 = 0LL;\n v17 = -99999999;\n do {\n if (v17 < 2 * *(uint32_t *)&v24[v18] - *(uint32_t *)(a1 + v18))\n v17 = 2 * *(uint32_t *)&v24[v18] - *(uint32_t *)(a1 + v18);\n v18 += 4LL;\n } while (v3 != v18);\n }\n return (unsigned int)v17;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v3;\n signed long long v4;\n void *v5;\n long long v6;\n long long v7;\n int i;\n long long v9;\n int v10;\n int v11;\n uint32_t *v12;\n int v13;\n int v14;\n int v15;\n int v16;\n int v17;\n long long v18;\n signed long long v20;\n void *v21;\n long long v22;\n uint8_t v24[8];\n unsigned long long v25;\n v25 = __readfsqword(40u);\n v3 = 4LL * a2;\n while (v24 != &v24[-((v3 + 15) & 18446744073709547520LL)])\n ;\n v4 = ((unsigned short)v3 + 15) & 4080;\n v5 = alloca(v4);\n if ((((unsigned short)v3 + 15) & 4080) != 0)\n *(uint64_t *)&v24[v4 - 8] = *(uint64_t *)&v24[v4 - 8];\n if (a2 <= 0) {\n return (unsigned int)-99999999;\n } else {\n v6 = 0LL;\n do {\n *(uint32_t *)&v24[v6] = *(uint32_t *)(a1 + v6);\n v6 += 4LL;\n } while (v3 != v6);\n if (a2 > 1) {\n v7 = 4LL;\n for (i = 1; i != a2; ++i) {\n while (i <= 0) {\n ++i;\n v7 += 4LL;\n }\n v11 = *(uint32_t *)(a1 + v7);\n v9 = 0LL;\n do {\n if (v11 > *(uint32_t *)(a1 + v9)) {\n v10 = *(uint32_t *)&v24[v9] + v11;\n if (*(uint32_t *)&v24[v7] < v10) *(uint32_t *)&v24[v7] = v10;\n }\n v9 += 4LL;\n } while (v9 != v7);\n v7 += 4LL;\n }\n }\n while (v24 != &v24[-((v3 + 15) & 18446744073709547520LL)])\n ;\n v20 = ((unsigned short)v3 + 15) & 4080;\n v21 = alloca(v20);\n if ((((unsigned short)v3 + 15) & 4080) != 0)\n *(uint64_t *)&v24[v20 - 8] = *(uint64_t *)&v24[v20 - 8];\n v22 = 0LL;\n do {\n *(uint32_t *)&v24[v22] = *(uint32_t *)(a1 + v22);\n v22 += 4LL;\n } while (v3 != v22);\n if (a2 > 1) {\n v15 = a2 - 2;\n do {\n while (a2 - 1 - v15 <= 0) --v15;\n v16 = *(uint32_t *)(a1 + 4LL * (v15 + 1) - 4);\n v13 = a2 - 1;\n v12 = (uint32_t *)(a1 + v3 - 4);\n do {\n if (v16 > *v12) {\n v14 = *(uint32_t *)&v24[4 * v13] + v16;\n if (*(uint32_t *)&v24[4 * v15] < v14)\n *(uint32_t *)&v24[4 * v15] = v14;\n }\n --v12;\n --v13;\n } while (v13 != v15);\n --v15;\n } while (v15 != -1);\n }\n v18 = 0LL;\n v17 = -99999999;\n do {\n if (v17 < 2 * *(uint32_t *)&v24[v18] - *(uint32_t *)(a1 + v18))\n v17 = 2 * *(uint32_t *)&v24[v18] - *(uint32_t *)(a1 + v18);\n v18 += 4LL;\n } while (v3 != v18);\n }\n return (unsigned int)v17;\n}" + }, + { + "index": 245, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int MSIBS[n];\n for (int i = 0; i < n; i++) {\n MSIBS[i] = arr[i];\n }\n for (int i = 1; i < n; i++) {\n for (int j = 0; j < i; j++) {\n if (arr[i] > arr[j] && MSIBS[i] < MSIBS[j] + arr[i]) {\n MSIBS[i] = MSIBS[j] + arr[i];\n }\n }\n }\n int MSDBS[n];\n for (int i = 0; i < n; i++) {\n MSDBS[i] = arr[i];\n }\n for (int i = 1; i < n; i++) {\n for (int j = 0; j < i; j++) {\n if (arr[n - i - 1] > arr[n - j - 1] &&\n MSDBS[n - i - 1] < MSDBS[n - j - 1] + arr[n - i - 1]) {\n MSDBS[n - i - 1] = MSDBS[n - j - 1] + arr[n - i - 1];\n }\n }\n }\n int max_sum = -99999999;\n for (int i = 0; i < n; i++) {\n if (max_sum < MSIBS[i] + MSDBS[i] - arr[i]) {\n max_sum = MSIBS[i] + MSDBS[i] - arr[i];\n }\n }\n return max_sum;\n}", + "test": "int main() {\n\n assert(func0((int[]){1, 15, 51, 45, 33, 100, 12, 18, 9}, 9) == 194);\n\n assert(func0((int[]){80, 60, 30, 40, 20, 10}, 6) == 210);\n\n assert(func0((int[]){2, 3, 14, 16, 21, 23, 29, 30}, 8) == 138);\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\nmovslq %esi,%r14\npush %r13\nshl $0x2,%r14\npush %r12\npush %rbx\nlea 0xf(%r14),%rbx\nmov %rbx,%rdx\nand $0xfffffffffffff000,%rdx\nsub $0x18,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nmov %rsp,%rcx\nmov %rbx,%rax\nsub %rdx,%rcx\nand $0xfffffffffffffff0,%rax\nmov %rcx,%rdx\ncmp %rdx,%rsp\nje 1383 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rdx,%rsp\njne 136e \nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\njne 150e \nlea 0x3(%rsp),%r9\nmov %r9,%r8\nand $0xfffffffffffffffc,%r9\nshr $0x2,%r8\ntest %esi,%esi\njle 1524 \nlea -0x1(%rsi),%ecx\nxor %eax,%eax\nmov %rcx,%r11\nnopl 0x0(%rax)\nmov (%rdi,%rax,4),%edx\nmov %edx,(%r9,%rax,4)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rdx,%rcx\njne 13b8 \ncmp $0x1,%esi\njle 1524 \nlea -0x2(%rsi),%r12d\nmov $0x1,%edx\nmov %r12,%r8\nadd $0x2,%r12\nnopl 0x0(%rax)\nmov (%rdi,%rdx,4),%ecx\nxor %eax,%eax\nnopl (%rax)\ncmp (%rdi,%rax,4),%ecx\njle 1406 \nmov (%r9,%rax,4),%r10d\nadd %ecx,%r10d\ncmp %r10d,(%r9,%rdx,4)\njge 1406 \nmov %r10d,(%r9,%rdx,4)\nadd $0x1,%rax\ncmp %rax,%rdx\njne 13f0 \nadd $0x1,%rdx\ncmp %rdx,%r12\njne 13e8 \nmov %rbx,%rax\nmov %rsp,%rdx\nand $0xfffffffffffff000,%rbx\nsub %rbx,%rdx\nand $0xfffffffffffffff0,%rax\ncmp %rdx,%rsp\nje 1446 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rdx,%rsp\njne 1431 \nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\njne 1519 \nmov %rsp,%rbx\nxor %eax,%eax\nnopl 0x0(%rax)\nmov (%rdi,%rax,4),%edx\nmov %edx,(%rbx,%rax,4)\nadd $0x1,%rax\ncmp %eax,%esi\njg 1460 \nadd %rdi,%r14\nmov %r14,%r13\nnopl 0x0(%rax)\nmov %r8d,%r10d\nmov -0x8(%r13),%ecx\nmov %r11d,%eax\nmov %r14,%rdx\nlea (%rbx,%r10,4),%r12\nnopl 0x0(%rax)\ncmp -0x4(%rdx),%ecx\njle 14a9 \nmovslq %eax,%r10\nmov (%rbx,%r10,4),%r15d\nadd %ecx,%r15d\ncmp %r15d,(%r12)\njge 14a9 \nmov %r15d,(%r12)\nsub $0x1,%eax\nsub $0x4,%rdx\ncmp %eax,%r8d\njne 1490 \nsub $0x1,%r8d\nsub $0x4,%r13\ncmp $0xffffffff,%r8d\njne 1478 \nxor %edx,%edx\nmov $0xfa0a1f01,%r8d\nnopl 0x0(%rax,%rax,1)\nmov (%rbx,%rdx,4),%eax\nadd (%r9,%rdx,4),%eax\nsub (%rdi,%rdx,4),%eax\ncmp %eax,%r8d\ncmovl %eax,%r8d\nadd $0x1,%rdx\ncmp %edx,%esi\njg 14d0 \nmov -0x38(%rbp),%rax\nxor %fs:0x28,%rax\njne 157e \nlea -0x28(%rbp),%rsp\nmov %r8d,%eax\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\norq $0x0,-0x8(%rsp,%rax,1)\njmpq 1394 \norq $0x0,-0x8(%rsp,%rax,1)\njmpq 1457 \nmov %rbx,%rax\nmov %rsp,%rdx\nand $0xfffffffffffff000,%rbx\nsub %rbx,%rdx\nand $0xfffffffffffffff0,%rax\ncmp %rdx,%rsp\nje 1552 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rdx,%rsp\njne 153d \nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 1565 \norq $0x0,-0x8(%rsp,%rax,1)\nlea 0x3(%rsp),%rdx\nshr $0x2,%rdx\ncmp $0x1,%esi\nje 1583 \nmov $0xfa0a1f01,%r8d\njmpq 14e9 \ncallq 1080 <__stack_chk_fail@plt>\nmov (%rdi),%eax\nmov %eax,0x0(,%rdx,4)\nadd 0x0(,%r8,4),%eax\nsub (%rdi),%eax\nmov %eax,%r8d\ncmp $0xfa0a1f01,%eax\nmov $0xfa0a1f01,%eax\ncmovl %eax,%r8d\njmpq 14e9 \nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\nmovsxd r14, esi\npush r13\nmov r13, rdi\npush r12\npush rbx\nmov rbx, r14\nshl r14, 2\nlea r8, [r14+0Fh]\nmov rsi, r8\nsub rsp, 38h\nand rsi, 0FFFFFFFFFFFFF000h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nmov rdx, rsp\nmov rax, r8\nsub rdx, rsi\nand rax, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rdx\njz short loc_1356\nloc_1341:\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\ncmp rsp, rdx\njnz short loc_1341\nloc_1356:\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njnz loc_14DA\nloc_1367:\nlea r12, [rsp+1060h+var_105D]\nmov [rbp+var_50], r8\nmov rax, r12\nand r12, 0FFFFFFFFFFFFFFFCh\nshr rax, 2\nmov [rbp+var_58], rax\ntest ebx, ebx\njle loc_14F0\nmov r9d, ebx\nmov rsi, r13; src\nlea r15d, [rbx-1]\nmov rdi, r12; dest\nshl r9, 2\nmov rdx, r9; n\nmov [rbp+n], r9\ncall _memcpy\ncmp ebx, 1\njz loc_14F7\nmov r9, [rbp+n]\nmov r8, [rbp+var_50]\nsub ebx, 2\nmov edx, 4\nnop dword ptr [rax]\nloc_13C0:\nmov ecx, [r13+rdx+0]\nxor eax, eax\nnop word ptr [rax+rax+00000000h]\nloc_13D0:\ncmp ecx, [r13+rax+0]\njle short loc_13E7\nmov esi, [r12+rax]\nadd esi, ecx\ncmp [r12+rdx], esi\njge short loc_13E7\nmov [r12+rdx], esi\nloc_13E7:\nadd rax, 4\ncmp rdx, rax\njnz short loc_13D0\nadd rdx, 4\ncmp r9, rdx\njnz short loc_13C0\nmov rax, r8\nmov rdx, rsp\nand r8, 0FFFFFFFFFFFFF000h\nsub rdx, r8\nand rax, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rdx\njz short loc_1427\nloc_1412:\nsub rsp, 1000h\nor [rsp+2060h+var_1068], 0\ncmp rsp, rdx\njnz short loc_1412\nloc_1427:\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njnz loc_14E5\nloc_1438:\nmov rdi, rsp; dest\nmov rdx, r9; n\nmov rsi, r13; src\ncall _memcpy\nlea r9, [r13+r14+0]\nlea r10, [r13+r14-4]\nmov rdi, rax\nnop dword ptr [rax+rax+00h]\nloc_1458:\nmov ecx, [r9-8]\nmov eax, r15d\nmov rdx, r10\nmovsxd r8, ebx\nnop dword ptr [rax]\nloc_1468:\ncmp ecx, [rdx]\njle short loc_1480\nmovsxd rsi, eax\nmov r11d, [rdi+rsi*4]\nadd r11d, ecx\ncmp [rdi+r8*4], r11d\njge short loc_1480\nmov [rdi+r8*4], r11d\nloc_1480:\nsub eax, 1\nsub rdx, 4\ncmp ebx, eax\njnz short loc_1468\nsub r9, 4\nsub ebx, 1\njnb short loc_1458\nxor edx, edx\nmov ecx, 0FA0A1F01h\nnop dword ptr [rax+rax+00h]\nloc_14A0:\nmov eax, [rdi+rdx]\nadd eax, [r12+rdx]\nsub eax, [r13+rdx+0]\ncmp ecx, eax\ncmovl ecx, eax\nadd rdx, 4\ncmp r14, rdx\njnz short loc_14A0\nloc_14BA:\nmov rax, [rbp+var_38]\nsub rax, fs:28h\njnz short loc_151B\nlea rsp, [rbp-28h]\nmov eax, ecx\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_14DA:\nor [rsp+rax+1060h+var_1068], 0\njmp loc_1367\nloc_14E5:\nor [rsp+rax+2060h+var_2068], 0\njmp loc_1438\nloc_14F0:\nmov ecx, 0FA0A1F01h\njmp short loc_14BA\nloc_14F7:\nmov eax, [r13+0]\nmov rdi, [rbp+var_58]\nmov [rbp+var_3C], eax\nadd eax, ds:dword_0[rdi*4]\nsub eax, [r13+0]\nmov ecx, eax\nmov eax, 0FA0A1F01h\ncmp ecx, eax\ncmovl ecx, eax\njmp short loc_14BA\nloc_151B:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(char *src, int a2)\n{\n __int64 v3; // r14\n __int64 *v4; // rdx\n signed __int64 v5; // rax\n void *v6; // rsp\n int v7; // r15d\n size_t v8; // r9\n __int64 v9; // r8\n int v10; // ebx\n __int64 v11; // rdx\n int v12; // ecx\n __int64 v13; // rax\n int v14; // esi\n _BYTE *v15; // rdx\n signed __int64 v16; // rax\n void *v17; // rsp\n _DWORD *v18; // rax\n char *v19; // r9\n _DWORD *v20; // rdi\n int v21; // ecx\n int v22; // eax\n char *v23; // rdx\n int v24; // r11d\n unsigned __int64 v26; // rdx\n int v27; // ecx\n _BYTE v30[4096]; // [rsp+8h] [rbp-2060h] BYREF\n _BYTE v31[3]; // [rsp+1008h] [rbp-1060h] BYREF\n char v32; // [rsp+100Bh] [rbp-105Dh] BYREF\n __int64 v33; // [rsp+2008h] [rbp-60h] BYREF\n unsigned __int64 v34; // [rsp+2010h] [rbp-58h]\n __int64 v35; // [rsp+2018h] [rbp-50h]\n size_t n; // [rsp+2020h] [rbp-48h]\n int v37; // [rsp+202Ch] [rbp-3Ch]\n unsigned __int64 v38; // [rsp+2030h] [rbp-38h]\n\n v3 = 4LL * a2;\n v38 = __readfsqword(0x28u);\n v4 = (__int64 *)((char *)&v33 - ((v3 + 15) & 0xFFFFFFFFFFFFF000LL));\n if ( &v33 != v4 )\n {\n while ( v31 != (_BYTE *)v4 )\n ;\n }\n v5 = ((_WORD)v3 + 15) & 0xFF0;\n v6 = alloca(v5);\n if ( (((_WORD)v3 + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v30[v5 + 4088] = *(_QWORD *)&v30[v5 + 4088];\n v35 = v3 + 15;\n v34 = (unsigned __int64)&v32 >> 2;\n if ( a2 <= 0 )\n {\n return (unsigned int)-99999999;\n }\n else\n {\n v7 = a2 - 1;\n n = 4LL * (unsigned int)a2;\n memcpy(v31, src, n);\n if ( a2 == 1 )\n {\n v37 = *(_DWORD *)src;\n v27 = *(_DWORD *)(4 * v34) + v37 - *(_DWORD *)src;\n if ( v27 < -99999999 )\n return (unsigned int)-99999999;\n }\n else\n {\n v8 = n;\n v9 = v35;\n v10 = a2 - 2;\n v11 = 4LL;\n do\n {\n v12 = *(_DWORD *)&src[v11];\n v13 = 0LL;\n do\n {\n if ( v12 > *(_DWORD *)&src[v13] )\n {\n v14 = v12 + *(_DWORD *)&v31[v13];\n if ( *(_DWORD *)&v31[v11] < v14 )\n *(_DWORD *)&v31[v11] = v14;\n }\n v13 += 4LL;\n }\n while ( v11 != v13 );\n v11 += 4LL;\n }\n while ( v8 != v11 );\n v15 = &v31[-(v9 & 0xFFFFFFFFFFFFF000LL)];\n if ( v31 != v15 )\n {\n while ( v30 != v15 )\n ;\n }\n v16 = v9 & 0xFF0;\n v17 = alloca(v16);\n if ( (v9 & 0xFF0) != 0 )\n *(_QWORD *)&v30[v16 - 8] = *(_QWORD *)&v30[v16 - 8];\n v18 = memcpy(v30, src, v8);\n v19 = &src[v3];\n v20 = v18;\n do\n {\n v21 = *((_DWORD *)v19 - 2);\n v22 = v7;\n v23 = &src[v3 - 4];\n do\n {\n if ( v21 > *(_DWORD *)v23 )\n {\n v24 = v21 + v20[v22];\n if ( v20[v10] < v24 )\n v20[v10] = v24;\n }\n --v22;\n v23 -= 4;\n }\n while ( v10 != v22 );\n v19 -= 4;\n }\n while ( v10-- != 0 );\n v26 = 0LL;\n v27 = -99999999;\n do\n {\n if ( v27 < *(_DWORD *)&v31[v26] + v20[v26 / 4] - *(_DWORD *)&src[v26] )\n v27 = *(_DWORD *)&v31[v26] + v20[v26 / 4] - *(_DWORD *)&src[v26];\n v26 += 4LL;\n }\n while ( v3 != v26 );\n }\n }\n return (unsigned int)v27;\n}", + "ida_strip_asm": "sub_12F0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\nmovsxd r14, esi\npush r13\nmov r13, rdi\npush r12\npush rbx\nmov rbx, r14\nshl r14, 2\nlea r8, [r14+0Fh]\nmov rsi, r8\nsub rsp, 38h\nand rsi, 0FFFFFFFFFFFFF000h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nmov rdx, rsp\nmov rax, r8\nsub rdx, rsi\nand rax, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rdx\njz short loc_1356\nloc_1341:\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\ncmp rsp, rdx\njnz short loc_1341\nloc_1356:\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njnz loc_14DA\nloc_1367:\nlea r12, [rsp+1060h+var_105D]\nmov [rbp+var_50], r8\nmov rax, r12\nand r12, 0FFFFFFFFFFFFFFFCh\nshr rax, 2\nmov [rbp+var_58], rax\ntest ebx, ebx\njle loc_14F0\nmov r9d, ebx\nmov rsi, r13; src\nlea r15d, [rbx-1]\nmov rdi, r12; dest\nshl r9, 2\nmov rdx, r9; n\nmov [rbp+n], r9\ncall _memcpy\ncmp ebx, 1\njz loc_14F7\nmov r9, [rbp+n]\nmov r8, [rbp+var_50]\nsub ebx, 2\nmov edx, 4\nnop dword ptr [rax]\nloc_13C0:\nmov ecx, [r13+rdx+0]\nxor eax, eax\nnop word ptr [rax+rax+00000000h]\nloc_13D0:\ncmp ecx, [r13+rax+0]\njle short loc_13E7\nmov esi, [r12+rax]\nadd esi, ecx\ncmp [r12+rdx], esi\njge short loc_13E7\nmov [r12+rdx], esi\nloc_13E7:\nadd rax, 4\ncmp rdx, rax\njnz short loc_13D0\nadd rdx, 4\ncmp r9, rdx\njnz short loc_13C0\nmov rax, r8\nmov rdx, rsp\nand r8, 0FFFFFFFFFFFFF000h\nsub rdx, r8\nand rax, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rdx\njz short loc_1427\nloc_1412:\nsub rsp, 1000h\nor [rsp+2060h+var_1068], 0\ncmp rsp, rdx\njnz short loc_1412\nloc_1427:\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njnz loc_14E5\nloc_1438:\nmov rdi, rsp; dest\nmov rdx, r9; n\nmov rsi, r13; src\ncall _memcpy\nlea r9, [r13+r14+0]\nlea r10, [r13+r14-4]\nmov rdi, rax\nnop dword ptr [rax+rax+00h]\nloc_1458:\nmov ecx, [r9-8]\nmov eax, r15d\nmov rdx, r10\nmovsxd r8, ebx\nnop dword ptr [rax]\nloc_1468:\ncmp ecx, [rdx]\njle short loc_1480\nmovsxd rsi, eax\nmov r11d, [rdi+rsi*4]\nadd r11d, ecx\ncmp [rdi+r8*4], r11d\njge short loc_1480\nmov [rdi+r8*4], r11d\nloc_1480:\nsub eax, 1\nsub rdx, 4\ncmp ebx, eax\njnz short loc_1468\nsub r9, 4\nsub ebx, 1\njnb short loc_1458\nxor edx, edx\nmov ecx, 0FA0A1F01h\nnop dword ptr [rax+rax+00h]\nloc_14A0:\nmov eax, [rdi+rdx]\nadd eax, [r12+rdx]\nsub eax, [r13+rdx+0]\ncmp ecx, eax\ncmovl ecx, eax\nadd rdx, 4\ncmp r14, rdx\njnz short loc_14A0\nloc_14BA:\nmov rax, [rbp+var_38]\nsub rax, fs:28h\njnz short loc_151B\nlea rsp, [rbp-28h]\nmov eax, ecx\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_14DA:\nor [rsp+rax+1060h+var_1068], 0\njmp loc_1367\nloc_14E5:\nor [rsp+rax+2060h+var_2068], 0\njmp loc_1438\nloc_14F0:\nmov ecx, 0FA0A1F01h\njmp short loc_14BA\nloc_14F7:\nmov eax, [r13+0]\nmov rdi, [rbp+var_58]\nmov [rbp+var_3C], eax\nadd eax, ds:dword_0[rdi*4]\nsub eax, [r13+0]\nmov ecx, eax\nmov eax, 0FA0A1F01h\ncmp ecx, eax\ncmovl ecx, eax\njmp short loc_14BA\nloc_151B:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12F0(char *src, int a2)\n{\n __int64 v3; // r14\n __int64 *v4; // rdx\n signed __int64 v5; // rax\n void *v6; // rsp\n int v7; // r15d\n size_t v8; // r9\n __int64 v9; // r8\n int v10; // ebx\n __int64 v11; // rdx\n int v12; // ecx\n __int64 v13; // rax\n int v14; // esi\n _BYTE *v15; // rdx\n signed __int64 v16; // rax\n void *v17; // rsp\n _DWORD *v18; // rax\n char *v19; // r9\n _DWORD *v20; // rdi\n int v21; // ecx\n int v22; // eax\n char *v23; // rdx\n int v24; // r11d\n unsigned __int64 v26; // rdx\n int v27; // ecx\n _BYTE v30[4096]; // [rsp+8h] [rbp-2060h] BYREF\n _BYTE v31[3]; // [rsp+1008h] [rbp-1060h] BYREF\n char v32; // [rsp+100Bh] [rbp-105Dh] BYREF\n __int64 v33; // [rsp+2008h] [rbp-60h] BYREF\n unsigned __int64 v34; // [rsp+2010h] [rbp-58h]\n __int64 v35; // [rsp+2018h] [rbp-50h]\n size_t n; // [rsp+2020h] [rbp-48h]\n int v37; // [rsp+202Ch] [rbp-3Ch]\n unsigned __int64 v38; // [rsp+2030h] [rbp-38h]\n\n v3 = 4LL * a2;\n v38 = __readfsqword(0x28u);\n v4 = (__int64 *)((char *)&v33 - ((v3 + 15) & 0xFFFFFFFFFFFFF000LL));\n if ( &v33 != v4 )\n {\n while ( v31 != (_BYTE *)v4 )\n ;\n }\n v5 = ((_WORD)v3 + 15) & 0xFF0;\n v6 = alloca(v5);\n if ( (((_WORD)v3 + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v30[v5 + 4088] = *(_QWORD *)&v30[v5 + 4088];\n v35 = v3 + 15;\n v34 = (unsigned __int64)&v32 >> 2;\n if ( a2 <= 0 )\n {\n return (unsigned int)-99999999;\n }\n else\n {\n v7 = a2 - 1;\n n = 4LL * (unsigned int)a2;\n memcpy(v31, src, n);\n if ( a2 == 1 )\n {\n v37 = *(_DWORD *)src;\n v27 = *(_DWORD *)(4 * v34) + v37 - *(_DWORD *)src;\n if ( v27 < -99999999 )\n return (unsigned int)-99999999;\n }\n else\n {\n v8 = n;\n v9 = v35;\n v10 = a2 - 2;\n v11 = 4LL;\n do\n {\n v12 = *(_DWORD *)&src[v11];\n v13 = 0LL;\n do\n {\n if ( v12 > *(_DWORD *)&src[v13] )\n {\n v14 = v12 + *(_DWORD *)&v31[v13];\n if ( *(_DWORD *)&v31[v11] < v14 )\n *(_DWORD *)&v31[v11] = v14;\n }\n v13 += 4LL;\n }\n while ( v11 != v13 );\n v11 += 4LL;\n }\n while ( v8 != v11 );\n v15 = &v31[-(v9 & 0xFFFFFFFFFFFFF000LL)];\n if ( v31 != v15 )\n {\n while ( v30 != v15 )\n ;\n }\n v16 = v9 & 0xFF0;\n v17 = alloca(v16);\n if ( (v9 & 0xFF0) != 0 )\n *(_QWORD *)&v30[v16 - 8] = *(_QWORD *)&v30[v16 - 8];\n v18 = memcpy(v30, src, v8);\n v19 = &src[v3];\n v20 = v18;\n do\n {\n v21 = *((_DWORD *)v19 - 2);\n v22 = v7;\n v23 = &src[v3 - 4];\n do\n {\n if ( v21 > *(_DWORD *)v23 )\n {\n v24 = v21 + v20[v22];\n if ( v20[v10] < v24 )\n v20[v10] = v24;\n }\n --v22;\n v23 -= 4;\n }\n while ( v10 != v22 );\n v19 -= 4;\n }\n while ( v10-- != 0 );\n v26 = 0LL;\n v27 = -99999999;\n do\n {\n if ( v27 < *(_DWORD *)&v31[v26] + v20[v26 / 4] - *(_DWORD *)&src[v26] )\n v27 = *(_DWORD *)&v31[v26] + v20[v26 / 4] - *(_DWORD *)&src[v26];\n v26 += 4LL;\n }\n while ( v3 != v26 );\n }\n }\n return (unsigned int)v27;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12F0(char *src, int a2) {\n long long v3;\n long long *v4;\n signed long long v5;\n void *v6;\n int v7;\n unsigned int v8;\n long long v9;\n int v10;\n long long v11;\n int v12;\n long long v13;\n int v14;\n uint8_t *v15;\n signed long long v16;\n void *v17;\n uint32_t *v18;\n char *v19;\n uint32_t *v20;\n int v21;\n int v22;\n char *v23;\n int v24;\n unsigned long long v26;\n int v27;\n uint8_t v30[4096];\n uint8_t v31[3];\n char v32;\n long long v33;\n unsigned long long v34;\n long long v35;\n unsigned int n;\n int v37;\n unsigned long long v38;\n v3 = 4LL * a2;\n v38 = __readfsqword(40u);\n v4 = (long long *)((char *)&v33 - ((v3 + 15) & 18446744073709547520LL));\n if (&v33 != v4) {\n while (v31 != (uint8_t *)v4)\n ;\n }\n v5 = ((unsigned short)v3 + 15) & 4080;\n v6 = alloca(v5);\n if ((((unsigned short)v3 + 15) & 4080) != 0)\n *(uint64_t *)&v30[v5 + 4088] = *(uint64_t *)&v30[v5 + 4088];\n v35 = v3 + 15;\n v34 = (unsigned long long)&v32 >> 2;\n if (a2 <= 0) {\n return (unsigned int)-99999999;\n } else {\n v7 = a2 - 1;\n n = 4LL * (unsigned int)a2;\n memcpy(v31, src, n);\n if (a2 == 1) {\n v37 = *(uint32_t *)src;\n v27 = *(uint32_t *)(4 * v34) + v37 - *(uint32_t *)src;\n if (v27 < -99999999) return (unsigned int)-99999999;\n } else {\n v8 = n;\n v9 = v35;\n v10 = a2 - 2;\n v11 = 4LL;\n do {\n v12 = *(uint32_t *)&src[v11];\n v13 = 0LL;\n do {\n if (v12 > *(uint32_t *)&src[v13]) {\n v14 = v12 + *(uint32_t *)&v31[v13];\n if (*(uint32_t *)&v31[v11] < v14) *(uint32_t *)&v31[v11] = v14;\n }\n v13 += 4LL;\n } while (v11 != v13);\n v11 += 4LL;\n } while (v8 != v11);\n v15 = &v31[-(v9 & 18446744073709547520LL)];\n if (v31 != v15) {\n while (v30 != v15)\n ;\n }\n v16 = v9 & 4080;\n v17 = alloca(v16);\n if ((v9 & 4080) != 0)\n *(uint64_t *)&v30[v16 - 8] = *(uint64_t *)&v30[v16 - 8];\n v18 = memcpy(v30, src, v8);\n v19 = &src[v3];\n v20 = v18;\n do {\n v21 = *((uint32_t *)v19 - 2);\n v22 = v7;\n v23 = &src[v3 - 4];\n do {\n if (v21 > *(uint32_t *)v23) {\n v24 = v21 + v20[v22];\n if (v20[v10] < v24) v20[v10] = v24;\n }\n --v22;\n v23 -= 4;\n } while (v10 != v22);\n v19 -= 4;\n } while (v10-- != 0);\n v26 = 0LL;\n v27 = -99999999;\n do {\n if (v27 <\n *(uint32_t *)&v31[v26] + v20[v26 / 4] - *(uint32_t *)&src[v26])\n v27 = *(uint32_t *)&v31[v26] + v20[v26 / 4] - *(uint32_t *)&src[v26];\n v26 += 4LL;\n } while (v3 != v26);\n }\n }\n return (unsigned int)v27;\n}", + "ida_pseudo_norm": "long long func0(char *src, int a2) {\n long long v3;\n long long *v4;\n signed long long v5;\n void *v6;\n int v7;\n unsigned int v8;\n long long v9;\n int v10;\n long long v11;\n int v12;\n long long v13;\n int v14;\n uint8_t *v15;\n signed long long v16;\n void *v17;\n uint32_t *v18;\n char *v19;\n uint32_t *v20;\n int v21;\n int v22;\n char *v23;\n int v24;\n unsigned long long v26;\n int v27;\n uint8_t v30[4096];\n uint8_t v31[3];\n char v32;\n long long v33;\n unsigned long long v34;\n long long v35;\n unsigned int n;\n int v37;\n unsigned long long v38;\n v3 = 4LL * a2;\n v38 = __readfsqword(40u);\n v4 = (long long *)((char *)&v33 - ((v3 + 15) & 18446744073709547520LL));\n if (&v33 != v4) {\n while (v31 != (uint8_t *)v4)\n ;\n }\n v5 = ((unsigned short)v3 + 15) & 4080;\n v6 = alloca(v5);\n if ((((unsigned short)v3 + 15) & 4080) != 0)\n *(uint64_t *)&v30[v5 + 4088] = *(uint64_t *)&v30[v5 + 4088];\n v35 = v3 + 15;\n v34 = (unsigned long long)&v32 >> 2;\n if (a2 <= 0) {\n return (unsigned int)-99999999;\n } else {\n v7 = a2 - 1;\n n = 4LL * (unsigned int)a2;\n memcpy(v31, src, n);\n if (a2 == 1) {\n v37 = *(uint32_t *)src;\n v27 = *(uint32_t *)(4 * v34) + v37 - *(uint32_t *)src;\n if (v27 < -99999999) return (unsigned int)-99999999;\n } else {\n v8 = n;\n v9 = v35;\n v10 = a2 - 2;\n v11 = 4LL;\n do {\n v12 = *(uint32_t *)&src[v11];\n v13 = 0LL;\n do {\n if (v12 > *(uint32_t *)&src[v13]) {\n v14 = v12 + *(uint32_t *)&v31[v13];\n if (*(uint32_t *)&v31[v11] < v14) *(uint32_t *)&v31[v11] = v14;\n }\n v13 += 4LL;\n } while (v11 != v13);\n v11 += 4LL;\n } while (v8 != v11);\n v15 = &v31[-(v9 & 18446744073709547520LL)];\n if (v31 != v15) {\n while (v30 != v15)\n ;\n }\n v16 = v9 & 4080;\n v17 = alloca(v16);\n if ((v9 & 4080) != 0)\n *(uint64_t *)&v30[v16 - 8] = *(uint64_t *)&v30[v16 - 8];\n v18 = memcpy(v30, src, v8);\n v19 = &src[v3];\n v20 = v18;\n do {\n v21 = *((uint32_t *)v19 - 2);\n v22 = v7;\n v23 = &src[v3 - 4];\n do {\n if (v21 > *(uint32_t *)v23) {\n v24 = v21 + v20[v22];\n if (v20[v10] < v24) v20[v10] = v24;\n }\n --v22;\n v23 -= 4;\n } while (v10 != v22);\n v19 -= 4;\n } while (v10-- != 0);\n v26 = 0LL;\n v27 = -99999999;\n do {\n if (v27 <\n *(uint32_t *)&v31[v26] + v20[v26 / 4] - *(uint32_t *)&src[v26])\n v27 = *(uint32_t *)&v31[v26] + v20[v26 / 4] - *(uint32_t *)&src[v26];\n v26 += 4LL;\n } while (v3 != v26);\n }\n }\n return (unsigned int)v27;\n}" + }, + { + "index": 245, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int MSIBS[n];\n for (int i = 0; i < n; i++) {\n MSIBS[i] = arr[i];\n }\n for (int i = 1; i < n; i++) {\n for (int j = 0; j < i; j++) {\n if (arr[i] > arr[j] && MSIBS[i] < MSIBS[j] + arr[i]) {\n MSIBS[i] = MSIBS[j] + arr[i];\n }\n }\n }\n int MSDBS[n];\n for (int i = 0; i < n; i++) {\n MSDBS[i] = arr[i];\n }\n for (int i = 1; i < n; i++) {\n for (int j = 0; j < i; j++) {\n if (arr[n - i - 1] > arr[n - j - 1] &&\n MSDBS[n - i - 1] < MSDBS[n - j - 1] + arr[n - i - 1]) {\n MSDBS[n - i - 1] = MSDBS[n - j - 1] + arr[n - i - 1];\n }\n }\n }\n int max_sum = -99999999;\n for (int i = 0; i < n; i++) {\n if (max_sum < MSIBS[i] + MSDBS[i] - arr[i]) {\n max_sum = MSIBS[i] + MSDBS[i] - arr[i];\n }\n }\n return max_sum;\n}", + "test": "int main() {\n\n assert(func0((int[]){1, 15, 51, 45, 33, 100, 12, 18, 9}, 9) == 194);\n\n assert(func0((int[]){80, 60, 30, 40, 20, 10}, 6) == 210);\n\n assert(func0((int[]){2, 3, 14, 16, 21, 23, 29, 30}, 8) == 138);\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\nmovslq %esi,%r13\npush %r12\nmov %r13,%r14\nshl $0x2,%r13\nmov %rdi,%r12\npush %rbx\nlea 0xf(%r13),%r9\nmov %r9,%rdx\nand $0xfffffffffffff000,%rdx\nsub $0x28,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nmov %rsp,%rdi\nmov %r9,%rax\nsub %rdx,%rdi\nand $0xfffffffffffffff0,%rax\nmov %rdi,%rdx\ncmp %rdx,%rsp\nje 1359 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rdx,%rsp\njne 1344 \nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\njne 15d0 \nmov %r9,-0x48(%rbp)\nmov %rsp,%rbx\ntest %r14d,%r14d\njle 15c9 \nlea -0x1(%r14),%eax\nmov %r12,%rsi\nmov %rbx,%rdi\nlea 0x4(,%rax,4),%rdx\nmov %rax,%r15\ncallq 10b0 \ncmp $0x1,%r14d\nmov -0x48(%rbp),%r9\nje 15f2 \nlea -0x2(%r14),%edi\nmov $0x1,%edx\nmov %rdi,%r8\nadd $0x2,%rdi\nnopw 0x0(%rax,%rax,1)\nmov (%r12,%rdx,4),%ecx\nxor %eax,%eax\nxchg %ax,%ax\ncmp (%r12,%rax,4),%ecx\njle 13d3 \nmov (%rbx,%rax,4),%esi\nadd %ecx,%esi\ncmp %esi,(%rbx,%rdx,4)\njge 13d3 \nmov %esi,(%rbx,%rdx,4)\nadd $0x1,%rax\ncmp %rdx,%rax\njne 13c0 \nlea 0x1(%rax),%rdx\ncmp %rdx,%rdi\njne 13b8 \nmov %r9,%rax\nmov %rsp,%rdx\nand $0xfffffffffffff000,%r9\nsub %r9,%rdx\nand $0xfffffffffffffff0,%rax\ncmp %rdx,%rsp\nje 1413 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rdx,%rsp\njne 13fe \nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\njne 15db \nmov %r15d,%eax\ntest %r14d,%r14d\nmov %rsp,%rdi\nmov %r12,%rsi\nlea 0x4(,%rax,4),%rdx\nmov $0x4,%eax\nmov %r8d,-0x4c(%rbp)\ncmovle %rax,%rdx\nmov %rdi,-0x48(%rbp)\nadd %r12,%r13\ncallq 10b0 \nmov -0x4c(%rbp),%r8d\nmov %r13,%r11\nmov %rax,%rdi\nnopl 0x0(%rax,%rax,1)\nmov %r8d,%esi\nmov -0x8(%r11),%ecx\nmov %r15d,%eax\nmov %r13,%rdx\nlea (%rdi,%rsi,4),%r10\nnopl 0x0(%rax)\ncmp -0x4(%rdx),%ecx\njle 148f \nmovslq %eax,%rsi\nmov (%rdi,%rsi,4),%r9d\nadd %ecx,%r9d\ncmp %r9d,(%r10)\njge 148f \nmov %r9d,(%r10)\nsub $0x1,%eax\nsub $0x4,%rdx\ncmp %eax,%r8d\njne 1478 \nsub $0x1,%r8d\nsub $0x4,%r11\ncmp $0xffffffff,%r8d\njne 1460 \ntest %r14d,%r14d\nmov $0x1,%ecx\ncmovg %r14d,%ecx\ncmp $0x3,%r14d\njle 15e6 \nmov %ecx,%edx\nmovdqa 0xc57(%rip),%xmm2\nxor %eax,%eax\nshr $0x2,%edx\nshl $0x4,%rdx\nnopw 0x0(%rax,%rax,1)\nmovdqu (%rdi,%rax,1),%xmm0\nmovdqu (%rbx,%rax,1),%xmm4\nmovdqu (%r12,%rax,1),%xmm5\nadd $0x10,%rax\npaddd %xmm4,%xmm0\npsubd %xmm5,%xmm0\nmovdqa %xmm0,%xmm1\npcmpgtd %xmm2,%xmm1\npand %xmm1,%xmm0\npandn %xmm2,%xmm1\nmovdqa %xmm1,%xmm2\npor %xmm0,%xmm2\ncmp %rdx,%rax\njne 14d8 \nmovdqa %xmm2,%xmm0\nmov %ecx,%edx\npsrldq $0x8,%xmm0\nand $0xfffffffc,%edx\nand $0x3,%ecx\nmovdqa %xmm0,%xmm1\nmovdqa %xmm0,%xmm3\npcmpgtd %xmm2,%xmm1\npand %xmm1,%xmm3\npandn %xmm2,%xmm1\nmovdqa %xmm1,%xmm0\npor %xmm3,%xmm0\nmovdqa %xmm0,%xmm2\npsrldq $0x4,%xmm2\nmovdqa %xmm2,%xmm1\npcmpgtd %xmm0,%xmm1\npand %xmm1,%xmm2\npandn %xmm0,%xmm1\npor %xmm2,%xmm1\nmovd %xmm1,%eax\nje 15ab \nmov -0x48(%rbp),%rdi\nmovslq %edx,%rsi\nmov (%rdi,%rsi,4),%ecx\nadd (%rbx,%rsi,4),%ecx\nsub (%r12,%rsi,4),%ecx\ncmp %ecx,%eax\ncmovl %ecx,%eax\nlea 0x1(%rdx),%ecx\ncmp %ecx,%r14d\njle 15ab \nmovslq %ecx,%rcx\nmov (%rdi,%rcx,4),%esi\nadd (%rbx,%rcx,4),%esi\nsub (%r12,%rcx,4),%esi\ncmp %esi,%eax\ncmovl %esi,%eax\nadd $0x2,%edx\ncmp %edx,%r14d\njle 15ab \nmovslq %edx,%rdx\nmov (%rbx,%rdx,4),%ecx\nadd (%rdi,%rdx,4),%ecx\nsub (%r12,%rdx,4),%ecx\ncmp %ecx,%eax\ncmovl %ecx,%eax\nmov -0x38(%rbp),%rdi\nxor %fs:0x28,%rdi\njne 161d \nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\nmov $0xfa0a1f01,%eax\njmp 15ab \norq $0x0,-0x8(%rsp,%rax,1)\njmpq 136a \norq $0x0,-0x8(%rsp,%rax,1)\njmpq 1424 \nmov $0xfa0a1f01,%eax\nxor %edx,%edx\njmpq 1561 \nmov %r9,%rax\nmov %rsp,%rdx\nand $0xfffffffffffff000,%r9\nand $0xfffffffffffffff0,%rax\nsub %r9,%rdx\ncmp %rdx,%rsp\nje 1622 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 1606 \ncallq 1090 <__stack_chk_fail@plt>\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 1635 \norq $0x0,-0x8(%rsp,%rax,1)\nmov $0x4,%edx\nmov %rsp,%rdi\nmov %r12,%rsi\ncallq 10b0 \nxor %edx,%edx\nmov %rax,-0x48(%rbp)\nmov $0xfa0a1f01,%eax\njmpq 1561 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\nmov r14, rdi\npush r13\nmovsxd r13, esi\npush r12\nmov r15, r13\nshl r13, 2\npush rbx\nlea r8, [r13+0Fh]\nmov rcx, r8\nand rcx, 0FFFFFFFFFFFFF000h\nsub rsp, 38h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nmov rdx, rsp\nmov rax, r8\nsub rdx, rcx\nand rax, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rdx\njz short loc_1356\nloc_1341:\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\ncmp rsp, rdx\njnz short loc_1341\nloc_1356:\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njnz loc_15AD\nloc_1367:\nmov [rbp+var_58], r8\nmov r12, rsp\ntest r15d, r15d\njle loc_15C3\nmov r9d, r15d\nlea ecx, [r15-1]\nmov rsi, r14; src\nmov rdi, r12; dest\nshl r9, 2\nmov [rbp+var_4C], ecx\nmov rdx, r9; n\nmov [rbp+n], r9\ncall _memcpy\ncmp r15d, 1\njz loc_15D6\nmov r9, [rbp+n]\nmov ecx, [rbp+var_4C]\nlea ebx, [r15-2]\nmov edx, 4\nmov r8, [rbp+var_58]\nnop dword ptr [rax]\nloc_13B8:\nmov esi, [r14+rdx]\nxor eax, eax\nxchg ax, ax\nloc_13C0:\ncmp esi, [r14+rax]\njle short loc_13D6\nmov edi, [r12+rax]\nadd edi, esi\ncmp [r12+rdx], edi\njge short loc_13D6\nmov [r12+rdx], edi\nloc_13D6:\nadd rax, 4\ncmp rdx, rax\njnz short loc_13C0\nadd rdx, 4\ncmp r9, rdx\njnz short loc_13B8\nmov rax, r8\nmov rdx, rsp\nand r8, 0FFFFFFFFFFFFF000h\nsub rdx, r8\nand rax, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rdx\njz short loc_1416\nloc_1401:\nsub rsp, 1000h\nor [rsp+2060h+var_1068], 0\ncmp rsp, rdx\njnz short loc_1401\nloc_1416:\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njnz loc_15B8\nloc_1427:\nmov rdi, rsp; dest\nmov rdx, r9; n\nmov rsi, r14; src\nmov [rbp+var_4C], ecx\nmov [rbp+n], rdi\ncall _memcpy\nmov ecx, [rbp+var_4C]\nlea r11, [r14+r13]\nlea r13, [r14+r13-4]\nmov rdi, rax\nnop dword ptr [rax+rax+00h]\nloc_1450:\nmov esi, [r11-8]\nmov eax, ecx\nmov rdx, r13\nmovsxd r10, ebx\nnop dword ptr [rax+00h]\nloc_1460:\ncmp esi, [rdx]\njle short loc_1478\nmovsxd r9, eax\nmov r8d, [rdi+r9*4]\nadd r8d, esi\ncmp [rdi+r10*4], r8d\njge short loc_1478\nmov [rdi+r10*4], r8d\nloc_1478:\nsub eax, 1\nsub rdx, 4\ncmp ebx, eax\njnz short loc_1460\nsub r11, 4\nsub ebx, 1\njnb short loc_1450\ncmp ecx, 2\njbe loc_15CA\nmov edx, r15d\nmovdqa xmm2, cs:xmmword_2100\nxor eax, eax\nshr edx, 2\nshl rdx, 4\nnop dword ptr [rax+00000000h]\nloc_14B0:\nmovdqu xmm0, xmmword ptr [rdi+rax]\nmovdqu xmm3, xmmword ptr [r12+rax]\nmovdqu xmm4, xmmword ptr [r14+rax]\nadd rax, 10h\npaddd xmm0, xmm3\npsubd xmm0, xmm4\nmovdqa xmm1, xmm0\npcmpgtd xmm1, xmm2\npand xmm0, xmm1\npandn xmm1, xmm2\nmovdqa xmm2, xmm1\npor xmm2, xmm0\ncmp rax, rdx\njnz short loc_14B0\nmovdqa xmm1, xmm2\nmov ecx, r15d\npsrldq xmm1, 8\nand ecx, 0FFFFFFFCh\nmovdqa xmm0, xmm1\npcmpgtd xmm0, xmm2\npand xmm1, xmm0\npandn xmm0, xmm2\npor xmm0, xmm1\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\nmovdqa xmm1, xmm2\npcmpgtd xmm1, xmm0\npand xmm2, xmm1\npandn xmm1, xmm0\npor xmm1, xmm2\nmovd eax, xmm1\ntest r15b, 3\njz short loc_158F\nloc_1534:\nmovsxd rdi, ecx\nmov r8, [rbp+n]\nlea rsi, ds:0[rdi*4]\nadd r12, rsi\nadd r8, rsi\nmov edx, [r8]\nadd edx, [r12]\nsub edx, [r14+rdi*4]\ncmp eax, edx\ncmovl eax, edx\nlea edx, [rcx+1]\ncmp r15d, edx\njle short loc_158F\nmov edx, [r12+4]\nadd edx, [r8+4]\nsub edx, [r14+rsi+4]\ncmp eax, edx\ncmovl eax, edx\nadd ecx, 2\ncmp r15d, ecx\njle short loc_158F\nmov edx, [r12+8]\nadd edx, [r8+8]\nsub edx, [r14+rsi+8]\ncmp eax, edx\ncmovl eax, edx\nloc_158F:\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_15F0\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_15AD:\nor [rsp+rax+1060h+var_1068], 0\njmp loc_1367\nloc_15B8:\nor [rsp+rax+2060h+var_2068], 0\njmp loc_1427\nloc_15C3:\nmov eax, 0FA0A1F01h\njmp short loc_158F\nloc_15CA:\nxor ecx, ecx\nmov eax, 0FA0A1F01h\njmp loc_1534\nloc_15D6:\nmov eax, [r14]\nxor ecx, ecx\nmov [rbp+var_3C], eax\nlea rax, [rbp+var_3C]\nmov [rbp+n], rax\nmov eax, 0FA0A1F01h\njmp loc_1534\nloc_15F0:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(char *src, int a2)\n{\n __int64 v4; // r13\n __int64 *v5; // rdx\n signed __int64 v6; // rax\n void *v7; // rsp\n size_t v8; // r9\n unsigned int v9; // ecx\n int v10; // ebx\n __int64 v11; // rdx\n __int64 v12; // r8\n int v13; // esi\n __int64 v14; // rax\n int v15; // edi\n _BYTE *v16; // rdx\n signed __int64 v17; // rax\n void *v18; // rsp\n _DWORD *v19; // rax\n unsigned int v20; // ecx\n char *v21; // r11\n char *v22; // r13\n _DWORD *v23; // rdi\n int v24; // esi\n signed int v25; // eax\n char *v26; // rdx\n int v27; // r8d\n __m128i si128; // xmm2\n __int64 v30; // rax\n __m128i v31; // xmm0\n __m128i v32; // xmm3\n __m128i v33; // xmm4\n __m128i v34; // xmm0\n __m128i v35; // xmm1\n __m128i v36; // xmm1\n signed int v37; // ecx\n __m128i v38; // xmm0\n __m128i v39; // xmm0\n __m128i v40; // xmm2\n __m128i v41; // xmm1\n __int64 result; // rax\n __int64 v43; // rsi\n _BYTE *v44; // r12\n size_t v45; // r8\n int v46; // edx\n int v47; // edx\n int v48; // edx\n _BYTE v50[4096]; // [rsp+8h] [rbp-2060h] BYREF\n _BYTE v51[4088]; // [rsp+1008h] [rbp-1060h] BYREF\n __int64 v52; // [rsp+2008h] [rbp-60h] BYREF\n __int64 v53; // [rsp+2010h] [rbp-58h]\n unsigned int v54; // [rsp+201Ch] [rbp-4Ch]\n size_t n; // [rsp+2020h] [rbp-48h]\n int v56; // [rsp+202Ch] [rbp-3Ch] BYREF\n unsigned __int64 v57; // [rsp+2030h] [rbp-38h]\n\n v4 = 4LL * a2;\n v57 = __readfsqword(0x28u);\n v5 = (__int64 *)((char *)&v52 - ((v4 + 15) & 0xFFFFFFFFFFFFF000LL));\n if ( &v52 != v5 )\n {\n while ( v51 != (_BYTE *)v5 )\n ;\n }\n v6 = ((_WORD)v4 + 15) & 0xFF0;\n v7 = alloca(v6);\n if ( (((_WORD)v4 + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v50[v6 + 4088] = *(_QWORD *)&v50[v6 + 4088];\n v53 = v4 + 15;\n if ( a2 <= 0 )\n return 4194967297LL;\n v54 = a2 - 1;\n n = 4LL * (unsigned int)a2;\n memcpy(v51, src, n);\n if ( a2 == 1 )\n {\n v37 = 0;\n v56 = *(_DWORD *)src;\n n = (size_t)&v56;\n result = 4194967297LL;\n }\n else\n {\n v8 = n;\n v9 = v54;\n v10 = a2 - 2;\n v11 = 4LL;\n v12 = v53;\n do\n {\n v13 = *(_DWORD *)&src[v11];\n v14 = 0LL;\n do\n {\n if ( v13 > *(_DWORD *)&src[v14] )\n {\n v15 = v13 + *(_DWORD *)&v51[v14];\n if ( *(_DWORD *)&v51[v11] < v15 )\n *(_DWORD *)&v51[v11] = v15;\n }\n v14 += 4LL;\n }\n while ( v11 != v14 );\n v11 += 4LL;\n }\n while ( v8 != v11 );\n v16 = &v51[-(v12 & 0xFFFFFFFFFFFFF000LL)];\n if ( v51 != v16 )\n {\n while ( v50 != v16 )\n ;\n }\n v17 = v12 & 0xFF0;\n v18 = alloca(v17);\n if ( (v12 & 0xFF0) != 0 )\n *(_QWORD *)&v50[v17 - 8] = *(_QWORD *)&v50[v17 - 8];\n v54 = v9;\n n = (size_t)v50;\n v19 = memcpy(v50, src, v8);\n v20 = v54;\n v21 = &src[v4];\n v22 = &src[v4 - 4];\n v23 = v19;\n do\n {\n v24 = *((_DWORD *)v21 - 2);\n v25 = v20;\n v26 = v22;\n do\n {\n if ( v24 > *(_DWORD *)v26 )\n {\n v27 = v24 + v23[v25];\n if ( v23[v10] < v27 )\n v23[v10] = v27;\n }\n --v25;\n v26 -= 4;\n }\n while ( v10 != v25 );\n v21 -= 4;\n }\n while ( v10-- != 0 );\n if ( v20 <= 2 )\n {\n v37 = 0;\n result = 4194967297LL;\n }\n else\n {\n si128 = _mm_load_si128((const __m128i *)&xmmword_2100);\n v30 = 0LL;\n do\n {\n v31 = _mm_loadu_si128((const __m128i *)&v23[v30]);\n v32 = _mm_loadu_si128((const __m128i *)&v51[v30 * 4]);\n v33 = _mm_loadu_si128((const __m128i *)&src[v30 * 4]);\n v30 += 4LL;\n v34 = _mm_sub_epi32(_mm_add_epi32(v31, v32), v33);\n v35 = _mm_cmpgt_epi32(v34, si128);\n si128 = _mm_or_si128(_mm_andnot_si128(v35, si128), _mm_and_si128(v34, v35));\n }\n while ( v30 != 4LL * ((unsigned int)a2 >> 2) );\n v36 = _mm_srli_si128(si128, 8);\n v37 = a2 & 0xFFFFFFFC;\n v38 = _mm_cmpgt_epi32(v36, si128);\n v39 = _mm_or_si128(_mm_andnot_si128(v38, si128), _mm_and_si128(v36, v38));\n v40 = _mm_srli_si128(v39, 4);\n v41 = _mm_cmpgt_epi32(v40, v39);\n result = (unsigned int)_mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v41, v39), _mm_and_si128(v40, v41)));\n if ( (a2 & 3) == 0 )\n return result;\n }\n }\n v43 = 4LL * v37;\n v44 = &v51[v43];\n v45 = v43 + n;\n v46 = *(_DWORD *)&v51[v43] + *(_DWORD *)(v43 + n) - *(_DWORD *)&src[v43];\n if ( (int)result < v46 )\n result = (unsigned int)v46;\n if ( a2 > v37 + 1 )\n {\n v47 = *(_DWORD *)(v45 + 4) + *((_DWORD *)v44 + 1) - *(_DWORD *)&src[v43 + 4];\n if ( (int)result < v47 )\n result = (unsigned int)v47;\n if ( a2 > v37 + 2 )\n {\n v48 = *(_DWORD *)(v45 + 8) + *((_DWORD *)v44 + 2) - *(_DWORD *)&src[v43 + 8];\n if ( (int)result < v48 )\n return (unsigned int)v48;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_12F0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\nmov r14, rdi\npush r13\nmovsxd r13, esi\npush r12\nmov r15, r13\nshl r13, 2\npush rbx\nlea r8, [r13+0Fh]\nmov rcx, r8\nand rcx, 0FFFFFFFFFFFFF000h\nsub rsp, 38h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nmov rdx, rsp\nmov rax, r8\nsub rdx, rcx\nand rax, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rdx\njz short loc_1356\nloc_1341:\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\ncmp rsp, rdx\njnz short loc_1341\nloc_1356:\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njnz loc_15AD\nloc_1367:\nmov [rbp+var_58], r8\nmov r12, rsp\ntest r15d, r15d\njle loc_15C3\nmov r9d, r15d\nlea ecx, [r15-1]\nmov rsi, r14; src\nmov rdi, r12; dest\nshl r9, 2\nmov [rbp+var_4C], ecx\nmov rdx, r9; n\nmov [rbp+n], r9\ncall _memcpy\ncmp r15d, 1\njz loc_15D6\nmov r9, [rbp+n]\nmov ecx, [rbp+var_4C]\nlea ebx, [r15-2]\nmov edx, 4\nmov r8, [rbp+var_58]\nnop dword ptr [rax]\nloc_13B8:\nmov esi, [r14+rdx]\nxor eax, eax\nxchg ax, ax\nloc_13C0:\ncmp esi, [r14+rax]\njle short loc_13D6\nmov edi, [r12+rax]\nadd edi, esi\ncmp [r12+rdx], edi\njge short loc_13D6\nmov [r12+rdx], edi\nloc_13D6:\nadd rax, 4\ncmp rdx, rax\njnz short loc_13C0\nadd rdx, 4\ncmp r9, rdx\njnz short loc_13B8\nmov rax, r8\nmov rdx, rsp\nand r8, 0FFFFFFFFFFFFF000h\nsub rdx, r8\nand rax, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rdx\njz short loc_1416\nloc_1401:\nsub rsp, 1000h\nor [rsp+2060h+var_1068], 0\ncmp rsp, rdx\njnz short loc_1401\nloc_1416:\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njnz loc_15B8\nloc_1427:\nmov rdi, rsp; dest\nmov rdx, r9; n\nmov rsi, r14; src\nmov [rbp+var_4C], ecx\nmov [rbp+n], rdi\ncall _memcpy\nmov ecx, [rbp+var_4C]\nlea r11, [r14+r13]\nlea r13, [r14+r13-4]\nmov rdi, rax\nnop dword ptr [rax+rax+00h]\nloc_1450:\nmov esi, [r11-8]\nmov eax, ecx\nmov rdx, r13\nmovsxd r10, ebx\nnop dword ptr [rax+00h]\nloc_1460:\ncmp esi, [rdx]\njle short loc_1478\nmovsxd r9, eax\nmov r8d, [rdi+r9*4]\nadd r8d, esi\ncmp [rdi+r10*4], r8d\njge short loc_1478\nmov [rdi+r10*4], r8d\nloc_1478:\nsub eax, 1\nsub rdx, 4\ncmp ebx, eax\njnz short loc_1460\nsub r11, 4\nsub ebx, 1\njnb short loc_1450\ncmp ecx, 2\njbe loc_15CA\nmov edx, r15d\nmovdqa xmm2, cs:xmmword_2100\nxor eax, eax\nshr edx, 2\nshl rdx, 4\nnop dword ptr [rax+00000000h]\nloc_14B0:\nmovdqu xmm0, xmmword ptr [rdi+rax]\nmovdqu xmm3, xmmword ptr [r12+rax]\nmovdqu xmm4, xmmword ptr [r14+rax]\nadd rax, 10h\npaddd xmm0, xmm3\npsubd xmm0, xmm4\nmovdqa xmm1, xmm0\npcmpgtd xmm1, xmm2\npand xmm0, xmm1\npandn xmm1, xmm2\nmovdqa xmm2, xmm1\npor xmm2, xmm0\ncmp rax, rdx\njnz short loc_14B0\nmovdqa xmm1, xmm2\nmov ecx, r15d\npsrldq xmm1, 8\nand ecx, 0FFFFFFFCh\nmovdqa xmm0, xmm1\npcmpgtd xmm0, xmm2\npand xmm1, xmm0\npandn xmm0, xmm2\npor xmm0, xmm1\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\nmovdqa xmm1, xmm2\npcmpgtd xmm1, xmm0\npand xmm2, xmm1\npandn xmm1, xmm0\npor xmm1, xmm2\nmovd eax, xmm1\ntest r15b, 3\njz short loc_158F\nloc_1534:\nmovsxd rdi, ecx\nmov r8, [rbp+n]\nlea rsi, ds:0[rdi*4]\nadd r12, rsi\nadd r8, rsi\nmov edx, [r8]\nadd edx, [r12]\nsub edx, [r14+rdi*4]\ncmp eax, edx\ncmovl eax, edx\nlea edx, [rcx+1]\ncmp r15d, edx\njle short loc_158F\nmov edx, [r12+4]\nadd edx, [r8+4]\nsub edx, [r14+rsi+4]\ncmp eax, edx\ncmovl eax, edx\nadd ecx, 2\ncmp r15d, ecx\njle short loc_158F\nmov edx, [r12+8]\nadd edx, [r8+8]\nsub edx, [r14+rsi+8]\ncmp eax, edx\ncmovl eax, edx\nloc_158F:\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_15F0\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_15AD:\nor [rsp+rax+1060h+var_1068], 0\njmp loc_1367\nloc_15B8:\nor [rsp+rax+2060h+var_2068], 0\njmp loc_1427\nloc_15C3:\nmov eax, 0FA0A1F01h\njmp short loc_158F\nloc_15CA:\nxor ecx, ecx\nmov eax, 0FA0A1F01h\njmp loc_1534\nloc_15D6:\nmov eax, [r14]\nxor ecx, ecx\nmov [rbp+var_3C], eax\nlea rax, [rbp+var_3C]\nmov [rbp+n], rax\nmov eax, 0FA0A1F01h\njmp loc_1534\nloc_15F0:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12F0(char *src, int a2)\n{\n __int64 v4; // r13\n __int64 *v5; // rdx\n signed __int64 v6; // rax\n void *v7; // rsp\n size_t v8; // r9\n unsigned int v9; // ecx\n int v10; // ebx\n __int64 v11; // rdx\n __int64 v12; // r8\n int v13; // esi\n __int64 v14; // rax\n int v15; // edi\n _BYTE *v16; // rdx\n signed __int64 v17; // rax\n void *v18; // rsp\n _DWORD *v19; // rax\n unsigned int v20; // ecx\n char *v21; // r11\n char *v22; // r13\n _DWORD *v23; // rdi\n int v24; // esi\n signed int v25; // eax\n char *v26; // rdx\n int v27; // r8d\n __m128i si128; // xmm2\n __int64 v30; // rax\n __m128i v31; // xmm0\n __m128i v32; // xmm3\n __m128i v33; // xmm4\n __m128i v34; // xmm0\n __m128i v35; // xmm1\n __m128i v36; // xmm1\n signed int v37; // ecx\n __m128i v38; // xmm0\n __m128i v39; // xmm0\n __m128i v40; // xmm2\n __m128i v41; // xmm1\n __int64 result; // rax\n __int64 v43; // rsi\n _BYTE *v44; // r12\n size_t v45; // r8\n int v46; // edx\n int v47; // edx\n int v48; // edx\n _BYTE v50[4096]; // [rsp+8h] [rbp-2060h] BYREF\n _BYTE v51[4088]; // [rsp+1008h] [rbp-1060h] BYREF\n __int64 v52; // [rsp+2008h] [rbp-60h] BYREF\n __int64 v53; // [rsp+2010h] [rbp-58h]\n unsigned int v54; // [rsp+201Ch] [rbp-4Ch]\n size_t n; // [rsp+2020h] [rbp-48h]\n int v56; // [rsp+202Ch] [rbp-3Ch] BYREF\n unsigned __int64 v57; // [rsp+2030h] [rbp-38h]\n\n v4 = 4LL * a2;\n v57 = __readfsqword(0x28u);\n v5 = (__int64 *)((char *)&v52 - ((v4 + 15) & 0xFFFFFFFFFFFFF000LL));\n if ( &v52 != v5 )\n {\n while ( v51 != (_BYTE *)v5 )\n ;\n }\n v6 = ((_WORD)v4 + 15) & 0xFF0;\n v7 = alloca(v6);\n if ( (((_WORD)v4 + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v50[v6 + 4088] = *(_QWORD *)&v50[v6 + 4088];\n v53 = v4 + 15;\n if ( a2 <= 0 )\n return 4194967297LL;\n v54 = a2 - 1;\n n = 4LL * (unsigned int)a2;\n memcpy(v51, src, n);\n if ( a2 == 1 )\n {\n v37 = 0;\n v56 = *(_DWORD *)src;\n n = (size_t)&v56;\n result = 4194967297LL;\n }\n else\n {\n v8 = n;\n v9 = v54;\n v10 = a2 - 2;\n v11 = 4LL;\n v12 = v53;\n do\n {\n v13 = *(_DWORD *)&src[v11];\n v14 = 0LL;\n do\n {\n if ( v13 > *(_DWORD *)&src[v14] )\n {\n v15 = v13 + *(_DWORD *)&v51[v14];\n if ( *(_DWORD *)&v51[v11] < v15 )\n *(_DWORD *)&v51[v11] = v15;\n }\n v14 += 4LL;\n }\n while ( v11 != v14 );\n v11 += 4LL;\n }\n while ( v8 != v11 );\n v16 = &v51[-(v12 & 0xFFFFFFFFFFFFF000LL)];\n if ( v51 != v16 )\n {\n while ( v50 != v16 )\n ;\n }\n v17 = v12 & 0xFF0;\n v18 = alloca(v17);\n if ( (v12 & 0xFF0) != 0 )\n *(_QWORD *)&v50[v17 - 8] = *(_QWORD *)&v50[v17 - 8];\n v54 = v9;\n n = (size_t)v50;\n v19 = memcpy(v50, src, v8);\n v20 = v54;\n v21 = &src[v4];\n v22 = &src[v4 - 4];\n v23 = v19;\n do\n {\n v24 = *((_DWORD *)v21 - 2);\n v25 = v20;\n v26 = v22;\n do\n {\n if ( v24 > *(_DWORD *)v26 )\n {\n v27 = v24 + v23[v25];\n if ( v23[v10] < v27 )\n v23[v10] = v27;\n }\n --v25;\n v26 -= 4;\n }\n while ( v10 != v25 );\n v21 -= 4;\n }\n while ( v10-- != 0 );\n if ( v20 <= 2 )\n {\n v37 = 0;\n result = 4194967297LL;\n }\n else\n {\n si128 = _mm_load_si128((const __m128i *)&xmmword_2100);\n v30 = 0LL;\n do\n {\n v31 = _mm_loadu_si128((const __m128i *)&v23[v30]);\n v32 = _mm_loadu_si128((const __m128i *)&v51[v30 * 4]);\n v33 = _mm_loadu_si128((const __m128i *)&src[v30 * 4]);\n v30 += 4LL;\n v34 = _mm_sub_epi32(_mm_add_epi32(v31, v32), v33);\n v35 = _mm_cmpgt_epi32(v34, si128);\n si128 = _mm_or_si128(_mm_andnot_si128(v35, si128), _mm_and_si128(v34, v35));\n }\n while ( v30 != 4LL * ((unsigned int)a2 >> 2) );\n v36 = _mm_srli_si128(si128, 8);\n v37 = a2 & 0xFFFFFFFC;\n v38 = _mm_cmpgt_epi32(v36, si128);\n v39 = _mm_or_si128(_mm_andnot_si128(v38, si128), _mm_and_si128(v36, v38));\n v40 = _mm_srli_si128(v39, 4);\n v41 = _mm_cmpgt_epi32(v40, v39);\n result = (unsigned int)_mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v41, v39), _mm_and_si128(v40, v41)));\n if ( (a2 & 3) == 0 )\n return result;\n }\n }\n v43 = 4LL * v37;\n v44 = &v51[v43];\n v45 = v43 + n;\n v46 = *(_DWORD *)&v51[v43] + *(_DWORD *)(v43 + n) - *(_DWORD *)&src[v43];\n if ( (int)result < v46 )\n result = (unsigned int)v46;\n if ( a2 > v37 + 1 )\n {\n v47 = *(_DWORD *)(v45 + 4) + *((_DWORD *)v44 + 1) - *(_DWORD *)&src[v43 + 4];\n if ( (int)result < v47 )\n result = (unsigned int)v47;\n if ( a2 > v37 + 2 )\n {\n v48 = *(_DWORD *)(v45 + 8) + *((_DWORD *)v44 + 2) - *(_DWORD *)&src[v43 + 8];\n if ( (int)result < v48 )\n return (unsigned int)v48;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12F0(char *src, int a2) {\n long long v4;\n long long *v5;\n signed long long v6;\n void *v7;\n unsigned int v8;\n unsigned int v9;\n int v10;\n long long v11;\n long long v12;\n int v13;\n long long v14;\n int v15;\n uint8_t *v16;\n signed long long v17;\n void *v18;\n uint32_t *v19;\n unsigned int v20;\n char *v21;\n char *v22;\n uint32_t *v23;\n int v24;\n signed int v25;\n char *v26;\n int v27;\n __m128i si128;\n long long v30;\n __m128i v31;\n __m128i v32;\n __m128i v33;\n __m128i v34;\n __m128i v35;\n __m128i v36;\n signed int v37;\n __m128i v38;\n __m128i v39;\n __m128i v40;\n __m128i v41;\n long long result;\n long long v43;\n uint8_t *v44;\n unsigned int v45;\n int v46;\n int v47;\n int v48;\n uint8_t v50[4096];\n uint8_t v51[4088];\n long long v52;\n long long v53;\n unsigned int v54;\n unsigned int n;\n int v56;\n unsigned long long v57;\n v4 = 4LL * a2;\n v57 = __readfsqword(40u);\n v5 = (long long *)((char *)&v52 - ((v4 + 15) & 18446744073709547520LL));\n if (&v52 != v5) {\n while (v51 != (uint8_t *)v5)\n ;\n }\n v6 = ((unsigned short)v4 + 15) & 4080;\n v7 = alloca(v6);\n if ((((unsigned short)v4 + 15) & 4080) != 0)\n *(uint64_t *)&v50[v6 + 4088] = *(uint64_t *)&v50[v6 + 4088];\n v53 = v4 + 15;\n if (a2 <= 0) return 4194967297LL;\n v54 = a2 - 1;\n n = 4LL * (unsigned int)a2;\n memcpy(v51, src, n);\n if (a2 == 1) {\n v37 = 0;\n v56 = *(uint32_t *)src;\n n = (unsigned int)&v56;\n result = 4194967297LL;\n } else {\n v8 = n;\n v9 = v54;\n v10 = a2 - 2;\n v11 = 4LL;\n v12 = v53;\n do {\n v13 = *(uint32_t *)&src[v11];\n v14 = 0LL;\n do {\n if (v13 > *(uint32_t *)&src[v14]) {\n v15 = v13 + *(uint32_t *)&v51[v14];\n if (*(uint32_t *)&v51[v11] < v15) *(uint32_t *)&v51[v11] = v15;\n }\n v14 += 4LL;\n } while (v11 != v14);\n v11 += 4LL;\n } while (v8 != v11);\n v16 = &v51[-(v12 & 18446744073709547520LL)];\n if (v51 != v16) {\n while (v50 != v16)\n ;\n }\n v17 = v12 & 4080;\n v18 = alloca(v17);\n if ((v12 & 4080) != 0)\n *(uint64_t *)&v50[v17 - 8] = *(uint64_t *)&v50[v17 - 8];\n v54 = v9;\n n = (unsigned int)v50;\n v19 = memcpy(v50, src, v8);\n v20 = v54;\n v21 = &src[v4];\n v22 = &src[v4 - 4];\n v23 = v19;\n do {\n v24 = *((uint32_t *)v21 - 2);\n v25 = v20;\n v26 = v22;\n do {\n if (v24 > *(uint32_t *)v26) {\n v27 = v24 + v23[v25];\n if (v23[v10] < v27) v23[v10] = v27;\n }\n --v25;\n v26 -= 4;\n } while (v10 != v25);\n v21 -= 4;\n } while (v10-- != 0);\n if (v20 <= 2) {\n v37 = 0;\n result = 4194967297LL;\n } else {\n si128 = _mm_load_si128((const __m128i *)&xmmword_2100);\n v30 = 0LL;\n do {\n v31 = _mm_loadu_si128((const __m128i *)&v23[v30]);\n v32 = _mm_loadu_si128((const __m128i *)&v51[v30 * 4]);\n v33 = _mm_loadu_si128((const __m128i *)&src[v30 * 4]);\n v30 += 4LL;\n v34 = _mm_sub_epi32(_mm_add_epi32(v31, v32), v33);\n v35 = _mm_cmpgt_epi32(v34, si128);\n si128 =\n _mm_or_si128(_mm_andnot_si128(v35, si128), _mm_and_si128(v34, v35));\n } while (v30 != 4LL * ((unsigned int)a2 >> 2));\n v36 = _mm_srli_si128(si128, 8);\n v37 = a2 & 4294967292;\n v38 = _mm_cmpgt_epi32(v36, si128);\n v39 = _mm_or_si128(_mm_andnot_si128(v38, si128), _mm_and_si128(v36, v38));\n v40 = _mm_srli_si128(v39, 4);\n v41 = _mm_cmpgt_epi32(v40, v39);\n result = (unsigned int)_mm_cvtsi128_si32(\n _mm_or_si128(_mm_andnot_si128(v41, v39), _mm_and_si128(v40, v41)));\n if ((a2 & 3) == 0) return result;\n }\n }\n v43 = 4LL * v37;\n v44 = &v51[v43];\n v45 = v43 + n;\n v46 =\n *(uint32_t *)&v51[v43] + *(uint32_t *)(v43 + n) - *(uint32_t *)&src[v43];\n if ((int)result < v46) result = (unsigned int)v46;\n if (a2 > v37 + 1) {\n v47 = *(uint32_t *)(v45 + 4) + *((uint32_t *)v44 + 1) -\n *(uint32_t *)&src[v43 + 4];\n if ((int)result < v47) result = (unsigned int)v47;\n if (a2 > v37 + 2) {\n v48 = *(uint32_t *)(v45 + 8) + *((uint32_t *)v44 + 2) -\n *(uint32_t *)&src[v43 + 8];\n if ((int)result < v48) return (unsigned int)v48;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(char *src, int a2) {\n long long v4;\n long long *v5;\n signed long long v6;\n void *v7;\n unsigned int v8;\n unsigned int v9;\n int v10;\n long long v11;\n long long v12;\n int v13;\n long long v14;\n int v15;\n uint8_t *v16;\n signed long long v17;\n void *v18;\n uint32_t *v19;\n unsigned int v20;\n char *v21;\n char *v22;\n uint32_t *v23;\n int v24;\n signed int v25;\n char *v26;\n int v27;\n __m128i si128;\n long long v30;\n __m128i v31;\n __m128i v32;\n __m128i v33;\n __m128i v34;\n __m128i v35;\n __m128i v36;\n signed int v37;\n __m128i v38;\n __m128i v39;\n __m128i v40;\n __m128i v41;\n long long result;\n long long v43;\n uint8_t *v44;\n unsigned int v45;\n int v46;\n int v47;\n int v48;\n uint8_t v50[4096];\n uint8_t v51[4088];\n long long v52;\n long long v53;\n unsigned int v54;\n unsigned int n;\n int v56;\n unsigned long long v57;\n v4 = 4LL * a2;\n v57 = __readfsqword(40u);\n v5 = (long long *)((char *)&v52 - ((v4 + 15) & 18446744073709547520LL));\n if (&v52 != v5) {\n while (v51 != (uint8_t *)v5)\n ;\n }\n v6 = ((unsigned short)v4 + 15) & 4080;\n v7 = alloca(v6);\n if ((((unsigned short)v4 + 15) & 4080) != 0)\n *(uint64_t *)&v50[v6 + 4088] = *(uint64_t *)&v50[v6 + 4088];\n v53 = v4 + 15;\n if (a2 <= 0) return 4194967297LL;\n v54 = a2 - 1;\n n = 4LL * (unsigned int)a2;\n memcpy(v51, src, n);\n if (a2 == 1) {\n v37 = 0;\n v56 = *(uint32_t *)src;\n n = (unsigned int)&v56;\n result = 4194967297LL;\n } else {\n v8 = n;\n v9 = v54;\n v10 = a2 - 2;\n v11 = 4LL;\n v12 = v53;\n do {\n v13 = *(uint32_t *)&src[v11];\n v14 = 0LL;\n do {\n if (v13 > *(uint32_t *)&src[v14]) {\n v15 = v13 + *(uint32_t *)&v51[v14];\n if (*(uint32_t *)&v51[v11] < v15) *(uint32_t *)&v51[v11] = v15;\n }\n v14 += 4LL;\n } while (v11 != v14);\n v11 += 4LL;\n } while (v8 != v11);\n v16 = &v51[-(v12 & 18446744073709547520LL)];\n if (v51 != v16) {\n while (v50 != v16)\n ;\n }\n v17 = v12 & 4080;\n v18 = alloca(v17);\n if ((v12 & 4080) != 0)\n *(uint64_t *)&v50[v17 - 8] = *(uint64_t *)&v50[v17 - 8];\n v54 = v9;\n n = (unsigned int)v50;\n v19 = memcpy(v50, src, v8);\n v20 = v54;\n v21 = &src[v4];\n v22 = &src[v4 - 4];\n v23 = v19;\n do {\n v24 = *((uint32_t *)v21 - 2);\n v25 = v20;\n v26 = v22;\n do {\n if (v24 > *(uint32_t *)v26) {\n v27 = v24 + v23[v25];\n if (v23[v10] < v27) v23[v10] = v27;\n }\n --v25;\n v26 -= 4;\n } while (v10 != v25);\n v21 -= 4;\n } while (v10-- != 0);\n if (v20 <= 2) {\n v37 = 0;\n result = 4194967297LL;\n } else {\n si128 = _mm_load_si128((const __m128i *)&xmmword_2100);\n v30 = 0LL;\n do {\n v31 = _mm_loadu_si128((const __m128i *)&v23[v30]);\n v32 = _mm_loadu_si128((const __m128i *)&v51[v30 * 4]);\n v33 = _mm_loadu_si128((const __m128i *)&src[v30 * 4]);\n v30 += 4LL;\n v34 = _mm_sub_epi32(_mm_add_epi32(v31, v32), v33);\n v35 = _mm_cmpgt_epi32(v34, si128);\n si128 =\n _mm_or_si128(_mm_andnot_si128(v35, si128), _mm_and_si128(v34, v35));\n } while (v30 != 4LL * ((unsigned int)a2 >> 2));\n v36 = _mm_srli_si128(si128, 8);\n v37 = a2 & 4294967292;\n v38 = _mm_cmpgt_epi32(v36, si128);\n v39 = _mm_or_si128(_mm_andnot_si128(v38, si128), _mm_and_si128(v36, v38));\n v40 = _mm_srli_si128(v39, 4);\n v41 = _mm_cmpgt_epi32(v40, v39);\n result = (unsigned int)_mm_cvtsi128_si32(\n _mm_or_si128(_mm_andnot_si128(v41, v39), _mm_and_si128(v40, v41)));\n if ((a2 & 3) == 0) return result;\n }\n }\n v43 = 4LL * v37;\n v44 = &v51[v43];\n v45 = v43 + n;\n v46 =\n *(uint32_t *)&v51[v43] + *(uint32_t *)(v43 + n) - *(uint32_t *)&src[v43];\n if ((int)result < v46) result = (unsigned int)v46;\n if (a2 > v37 + 1) {\n v47 = *(uint32_t *)(v45 + 4) + *((uint32_t *)v44 + 1) -\n *(uint32_t *)&src[v43 + 4];\n if ((int)result < v47) result = (unsigned int)v47;\n if (a2 > v37 + 2) {\n v48 = *(uint32_t *)(v45 + 8) + *((uint32_t *)v44 + 2) -\n *(uint32_t *)&src[v43 + 8];\n if ((int)result < v48) return (unsigned int)v48;\n }\n }\n return result;\n}" + }, + { + "index": 246, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "double func0(double number) {\n if (number == 0) {\n return 0;\n }\n double g = number / 2.0;\n double g2 = g + 1;\n while (g != g2) {\n double n = number / g;\n g2 = g;\n g = (g + n) / 2;\n }\n return g;\n}", + "test": "int main() {\n\n assert(func0(10) == 3.162277660168379);\n\n assert(func0(2) == 1.414213562373095);\n\n assert(func0(9) == 3.0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmovsd %xmm0,-0x28(%rbp)\npxor %xmm0,%xmm0\nucomisd -0x28(%rbp),%xmm0\njp 1172 \npxor %xmm0,%xmm0\nucomisd -0x28(%rbp),%xmm0\njne 1172 \npxor %xmm0,%xmm0\njmp 11f1 \nmovsd -0x28(%rbp),%xmm0\nmovsd 0xf21(%rip),%xmm1\ndivsd %xmm1,%xmm0\nmovsd %xmm0,-0x18(%rbp)\nmovsd -0x18(%rbp),%xmm1\nmovsd 0xf13(%rip),%xmm0\naddsd %xmm1,%xmm0\nmovsd %xmm0,-0x10(%rbp)\njmp 11d4 \nmovsd -0x28(%rbp),%xmm0\ndivsd -0x18(%rbp),%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmovsd -0x18(%rbp),%xmm0\nmovsd %xmm0,-0x10(%rbp)\nmovsd -0x18(%rbp),%xmm0\naddsd -0x8(%rbp),%xmm0\nmovsd 0xed5(%rip),%xmm1\ndivsd %xmm1,%xmm0\nmovsd %xmm0,-0x18(%rbp)\nmovsd -0x18(%rbp),%xmm0\nucomisd -0x10(%rbp),%xmm0\njp 11a0 \nmovsd -0x18(%rbp),%xmm0\nucomisd -0x10(%rbp),%xmm0\njne 11a0 \nmovsd -0x18(%rbp),%xmm0\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmovsd [rbp+var_28], xmm0\npxor xmm0, xmm0\nucomisd xmm0, [rbp+var_28]\njp short loc_1172\npxor xmm0, xmm0\nucomisd xmm0, [rbp+var_28]\njnz short loc_1172\npxor xmm0, xmm0\njmp short loc_11F1\nloc_1172:\nmovsd xmm0, [rbp+var_28]\nmovsd xmm1, cs:qword_2080\ndivsd xmm0, xmm1\nmovsd [rbp+var_18], xmm0\nmovsd xmm1, [rbp+var_18]\nmovsd xmm0, cs:qword_2088\naddsd xmm0, xmm1\nmovsd [rbp+var_10], xmm0\njmp short loc_11D4\nloc_11A0:\nmovsd xmm0, [rbp+var_28]\ndivsd xmm0, [rbp+var_18]\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_18]\nmovsd [rbp+var_10], xmm0\nmovsd xmm0, [rbp+var_18]\naddsd xmm0, [rbp+var_8]\nmovsd xmm1, cs:qword_2080\ndivsd xmm0, xmm1\nmovsd [rbp+var_18], xmm0\nloc_11D4:\nmovsd xmm0, [rbp+var_18]\nucomisd xmm0, [rbp+var_10]\njp short loc_11A0\nmovsd xmm0, [rbp+var_18]\nucomisd xmm0, [rbp+var_10]\njnz short loc_11A0\nmovsd xmm0, [rbp+var_18]\nloc_11F1:\npop rbp\nretn", + "ida_pseudo": "double __fastcall func0(double a1)\n{\n double v2; // [rsp+10h] [rbp-18h]\n double v3; // [rsp+18h] [rbp-10h]\n\n if ( a1 == 0.0 )\n return 0.0;\n v2 = a1 / 2.0;\n v3 = a1 / 2.0 + 1.0;\n while ( v2 != v3 )\n {\n v3 = v2;\n v2 = (v2 + a1 / v2) / 2.0;\n }\n return v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmovsd [rbp+var_28], xmm0\npxor xmm0, xmm0\nucomisd xmm0, [rbp+var_28]\njp short loc_1172\npxor xmm0, xmm0\nucomisd xmm0, [rbp+var_28]\njnz short loc_1172\npxor xmm0, xmm0\njmp short loc_11F1\nloc_1172:\nmovsd xmm0, [rbp+var_28]\nmovsd xmm1, cs:qword_2080\ndivsd xmm0, xmm1\nmovsd [rbp+var_18], xmm0\nmovsd xmm1, [rbp+var_18]\nmovsd xmm0, cs:qword_2088\naddsd xmm0, xmm1\nmovsd [rbp+var_10], xmm0\njmp short loc_11D4\nloc_11A0:\nmovsd xmm0, [rbp+var_28]\ndivsd xmm0, [rbp+var_18]\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_18]\nmovsd [rbp+var_10], xmm0\nmovsd xmm0, [rbp+var_18]\naddsd xmm0, [rbp+var_8]\nmovsd xmm1, cs:qword_2080\ndivsd xmm0, xmm1\nmovsd [rbp+var_18], xmm0\nloc_11D4:\nmovsd xmm0, [rbp+var_18]\nucomisd xmm0, [rbp+var_10]\njp short loc_11A0\nmovsd xmm0, [rbp+var_18]\nucomisd xmm0, [rbp+var_10]\njnz short loc_11A0\nmovsd xmm0, [rbp+var_18]\nloc_11F1:\npop rbp\nretn", + "ida_strip_pseudo": "double __fastcall sub_1149(double a1)\n{\n double v2; // [rsp+10h] [rbp-18h]\n double v3; // [rsp+18h] [rbp-10h]\n\n if ( a1 == 0.0 )\n return 0.0;\n v2 = a1 / 2.0;\n v3 = a1 / 2.0 + 1.0;\n while ( v2 != v3 )\n {\n v3 = v2;\n v2 = (v2 + a1 / v2) / 2.0;\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1149(double a1) {\n double v2;\n double v3;\n if (a1 == 0.0) return 0.0;\n v2 = a1 / 2.0;\n v3 = a1 / 2.0 + 1.0;\n while (v2 != v3) {\n v3 = v2;\n v2 = (v2 + a1 / v2) / 2.0;\n }\n return v2;\n}", + "ida_pseudo_norm": "double func0(double a1) {\n double v2;\n double v3;\n if (a1 == 0.0) return 0.0;\n v2 = a1 / 2.0;\n v3 = a1 / 2.0 + 1.0;\n while (v2 != v3) {\n v3 = v2;\n v2 = (v2 + a1 / v2) / 2.0;\n }\n return v2;\n}" + }, + { + "index": 246, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "double func0(double number) {\n if (number == 0) {\n return 0;\n }\n double g = number / 2.0;\n double g2 = g + 1;\n while (g != g2) {\n double n = number / g;\n g2 = g;\n g = (g + n) / 2;\n }\n return g;\n}", + "test": "int main() {\n\n assert(func0(10) == 3.162277660168379);\n\n assert(func0(2) == 1.414213562373095);\n\n assert(func0(9) == 3.0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmovapd %xmm0,%xmm3\nucomisd 0xf47(%rip),%xmm0\njnp 11a4 \nmovapd %xmm3,%xmm0\nmulsd 0xf41(%rip),%xmm0\nmovapd %xmm0,%xmm1\naddsd 0xf3d(%rip),%xmm1\nucomisd %xmm1,%xmm0\njp 117b \nje 11aa \nmovsd 0xf25(%rip),%xmm4\nmovapd %xmm3,%xmm1\ndivsd %xmm0,%xmm1\naddsd %xmm0,%xmm1\nmovapd %xmm0,%xmm2\nmulsd %xmm4,%xmm1\nmovapd %xmm1,%xmm0\nucomisd %xmm2,%xmm1\njp 1183 \njne 1183 \nretq\njne 115b \npxor %xmm0,%xmm0\nretq\n", + "ida_asm": "func0:\nendbr64\nmovapd xmm3, xmm0\npxor xmm0, xmm0\nucomisd xmm3, xmm0\njp short loc_115D\njz short locret_11A5\nloc_115D:\nmovapd xmm0, xmm3\nmulsd xmm0, cs:qword_2080\nmovapd xmm1, xmm0\naddsd xmm1, cs:qword_2088\nucomisd xmm0, xmm1\njp short loc_117D\njz short locret_11A5\nloc_117D:\nmovsd xmm4, cs:qword_2080\nloc_1185:\nmovapd xmm1, xmm3\ndivsd xmm1, xmm0\naddsd xmm1, xmm0\nmovapd xmm2, xmm0\nmulsd xmm1, xmm4\nmovapd xmm0, xmm1\nucomisd xmm1, xmm2\njp short loc_1185\njnz short loc_1185\nlocret_11A5:\nretn", + "ida_pseudo": "__m128 __fastcall func0(__m128 a1)\n{\n __m128 result; // xmm0\n __m128 v3; // xmm1\n double v4; // xmm2_8\n\n result = 0LL;\n if ( *(double *)a1.m128_u64 != 0.0 )\n {\n result.m128_u64[1] = a1.m128_u64[1];\n *(double *)result.m128_u64 = *(double *)a1.m128_u64 * 0.5;\n if ( *(double *)a1.m128_u64 * 0.5 != *(double *)a1.m128_u64 * 0.5 + 1.0 )\n {\n do\n {\n v3.m128_u64[1] = a1.m128_u64[1];\n v4 = *(double *)result.m128_u64;\n *(double *)v3.m128_u64 = (*(double *)a1.m128_u64 / *(double *)result.m128_u64 + *(double *)result.m128_u64)\n * 0.5;\n result = v3;\n }\n while ( *(double *)v3.m128_u64 != v4 );\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmovapd xmm3, xmm0\npxor xmm0, xmm0\nucomisd xmm3, xmm0\njp short loc_115D\njz short locret_11A5\nloc_115D:\nmovapd xmm0, xmm3\nmulsd xmm0, cs:qword_2080\nmovapd xmm1, xmm0\naddsd xmm1, cs:qword_2088\nucomisd xmm0, xmm1\njp short loc_117D\njz short locret_11A5\nloc_117D:\nmovsd xmm4, cs:qword_2080\nloc_1185:\nmovapd xmm1, xmm3\ndivsd xmm1, xmm0\naddsd xmm1, xmm0\nmovapd xmm2, xmm0\nmulsd xmm1, xmm4\nmovapd xmm0, xmm1\nucomisd xmm1, xmm2\njp short loc_1185\njnz short loc_1185\nlocret_11A5:\nretn", + "ida_strip_pseudo": "__m128 __fastcall sub_1149(__m128 a1)\n{\n __m128 result; // xmm0\n __m128 v3; // xmm1\n double v4; // xmm2_8\n\n result = 0LL;\n if ( *(double *)a1.m128_u64 != 0.0 )\n {\n result.m128_u64[1] = a1.m128_u64[1];\n *(double *)result.m128_u64 = *(double *)a1.m128_u64 * 0.5;\n if ( *(double *)a1.m128_u64 * 0.5 != *(double *)a1.m128_u64 * 0.5 + 1.0 )\n {\n do\n {\n v3.m128_u64[1] = a1.m128_u64[1];\n v4 = *(double *)result.m128_u64;\n *(double *)v3.m128_u64 = (*(double *)a1.m128_u64 / *(double *)result.m128_u64 + *(double *)result.m128_u64)\n * 0.5;\n result = v3;\n }\n while ( *(double *)v3.m128_u64 != v4 );\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__m128 sub_1149(__m128 a1) {\n __m128 result;\n __m128 v3;\n double v4;\n result = 0LL;\n if (*(double *)a1.m128_u64 != 0.0) {\n result.m128_u64[1] = a1.m128_u64[1];\n *(double *)result.m128_u64 = *(double *)a1.m128_u64 * 0.5;\n if (*(double *)a1.m128_u64 * 0.5 != *(double *)a1.m128_u64 * 0.5 + 1.0) {\n do {\n v3.m128_u64[1] = a1.m128_u64[1];\n v4 = *(double *)result.m128_u64;\n *(double *)v3.m128_u64 =\n (*(double *)a1.m128_u64 / *(double *)result.m128_u64 +\n *(double *)result.m128_u64) *\n 0.5;\n result = v3;\n } while (*(double *)v3.m128_u64 != v4);\n }\n }\n return result;\n}", + "ida_pseudo_norm": "__m128 func0(__m128 a1) {\n __m128 result;\n __m128 v3;\n double v4;\n result = 0LL;\n if (*(double *)a1.m128_u64 != 0.0) {\n result.m128_u64[1] = a1.m128_u64[1];\n *(double *)result.m128_u64 = *(double *)a1.m128_u64 * 0.5;\n if (*(double *)a1.m128_u64 * 0.5 != *(double *)a1.m128_u64 * 0.5 + 1.0) {\n do {\n v3.m128_u64[1] = a1.m128_u64[1];\n v4 = *(double *)result.m128_u64;\n *(double *)v3.m128_u64 =\n (*(double *)a1.m128_u64 / *(double *)result.m128_u64 +\n *(double *)result.m128_u64) *\n 0.5;\n result = v3;\n } while (*(double *)v3.m128_u64 != v4);\n }\n }\n return result;\n}" + }, + { + "index": 247, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char str[]) {\n int n = strlen(str);\n int L[n][n];\n for (int i = 0; i < n; i++) {\n L[i][i] = 1;\n }\n for (int cl = 2; cl <= n; cl++) {\n for (int i = 0; i < n - cl + 1; i++) {\n int j = i + cl - 1;\n if (str[i] == str[j] && cl == 2) {\n L[i][j] = 2;\n } else if (str[i] == str[j]) {\n L[i][j] = L[i + 1][j - 1] + 2;\n } else {\n L[i][j] = (L[i][j - 1] > L[i + 1][j]) ? L[i][j - 1] : L[i + 1][j];\n }\n }\n }\n return L[0][n - 1];\n}", + "test": "int main() {\n\n\tassert(func0(\"TENS FOR TENS\") == 5);\n\n\tassert(func0(\"CARDIO FOR CARDS\") == 7);\n\n\tassert(func0(\"PART OF THE JOURNEY IS PART\") == 9);\n\n\n\n\treturn 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0x88,%rsp\nmov %rdi,-0x78(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nmov %rsp,%rax\nmov %rax,%rbx\nmov -0x78(%rbp),%rax\nmov %rax,%rdi\ncallq 1070 \nmov %eax,-0x58(%rbp)\nmov -0x58(%rbp),%esi\nmov -0x58(%rbp),%edi\nmovslq %esi,%rax\nsub $0x1,%rax\nmov %rax,-0x50(%rbp)\nmovslq %esi,%rax\nmov %rax,-0xb0(%rbp)\nmovq $0x0,-0xa8(%rbp)\nmovslq %esi,%rax\nlea 0x0(,%rax,4),%rcx\nmovslq %edi,%rax\nsub $0x1,%rax\nmov %rax,-0x48(%rbp)\nmovslq %esi,%rax\nmov %rax,-0xa0(%rbp)\nmovq $0x0,-0x98(%rbp)\nmovslq %edi,%rax\nmov %rax,-0x90(%rbp)\nmovq $0x0,-0x88(%rbp)\nmov -0xa0(%rbp),%r9\nmov -0x98(%rbp),%r10\nmov %r10,%rdx\nimul -0x90(%rbp),%rdx\nmov -0x88(%rbp),%rax\nimul %r9,%rax\nlea (%rdx,%rax,1),%r8\nmov %r9,%rax\nmulq -0x90(%rbp)\nadd %rdx,%r8\nmov %r8,%rdx\nmovslq %esi,%rax\nmov %rax,%r14\nmov $0x0,%r15d\nmovslq %edi,%rax\nmov %rax,%r12\nmov $0x0,%r13d\nmov %r15,%rdx\nimul %r12,%rdx\nmov %r13,%rax\nimul %r14,%rax\nlea (%rdx,%rax,1),%r8\nmov %r14,%rax\nmul %r12\nadd %rdx,%r8\nmov %r8,%rdx\nmovslq %esi,%rdx\nmovslq %edi,%rax\nimul %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%edi\nmov $0x0,%edx\ndiv %rdi\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rdi\nsub %rdx,%rdi\nmov %rdi,%rdx\ncmp %rdx,%rsp\nje 12f6 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 12df \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 1320 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x40(%rbp)\nmovl $0x0,-0x5c(%rbp)\njmp 1360 \nmov %rcx,%rdx\nshr $0x2,%rdx\nmov -0x40(%rbp),%rax\nlea 0x1(%rdx),%rsi\nmov -0x5c(%rbp),%edx\nmovslq %edx,%rdx\nimul %rsi,%rdx\nmovl $0x1,(%rax,%rdx,4)\naddl $0x1,-0x5c(%rbp)\nmov -0x5c(%rbp),%eax\ncmp -0x58(%rbp),%eax\njl 133c \nmovl $0x2,-0x60(%rbp)\njmpq 14d9 \nmovl $0x0,-0x64(%rbp)\njmpq 14c6 \nmov -0x64(%rbp),%edx\nmov -0x60(%rbp),%eax\nadd %edx,%eax\nsub $0x1,%eax\nmov %eax,-0x54(%rbp)\nmov -0x64(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x78(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%edx\nmov -0x54(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x78(%rbp),%rax\nadd %rsi,%rax\nmovzbl (%rax),%eax\ncmp %al,%dl\njne 13e2 \ncmpl $0x2,-0x60(%rbp)\njne 13e2 \nmov %rcx,%rdi\nshr $0x2,%rdi\nmov -0x40(%rbp),%rax\nmov -0x54(%rbp),%edx\nmovslq %edx,%rsi\nmov -0x64(%rbp),%edx\nmovslq %edx,%rdx\nimul %rdi,%rdx\nadd %rsi,%rdx\nmovl $0x2,(%rax,%rdx,4)\njmpq 14c2 \nmov -0x64(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x78(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%edx\nmov -0x54(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x78(%rbp),%rax\nadd %rsi,%rax\nmovzbl (%rax),%eax\ncmp %al,%dl\njne 1453 \nmov %rcx,%rdi\nshr $0x2,%rdi\nmov -0x64(%rbp),%eax\nlea 0x1(%rax),%edx\nmov -0x54(%rbp),%eax\nlea -0x1(%rax),%esi\nmov -0x40(%rbp),%rax\nmovslq %esi,%rsi\nmovslq %edx,%rdx\nimul %rdi,%rdx\nadd %rsi,%rdx\nmov (%rax,%rdx,4),%eax\nmov %rcx,%r8\nshr $0x2,%r8\nlea 0x2(%rax),%esi\nmov -0x40(%rbp),%rax\nmov -0x54(%rbp),%edx\nmovslq %edx,%rdi\nmov -0x64(%rbp),%edx\nmovslq %edx,%rdx\nimul %r8,%rdx\nadd %rdi,%rdx\nmov %esi,(%rax,%rdx,4)\njmp 14c2 \nmov %rcx,%rdi\nshr $0x2,%rdi\nmov -0x64(%rbp),%eax\nlea 0x1(%rax),%r8d\nmov -0x40(%rbp),%rax\nmov -0x54(%rbp),%edx\nmovslq %edx,%rsi\nmovslq %r8d,%rdx\nimul %rdi,%rdx\nadd %rsi,%rdx\nmov (%rax,%rdx,4),%edx\nmov %rcx,%r8\nshr $0x2,%r8\nmov -0x54(%rbp),%eax\nlea -0x1(%rax),%esi\nmov -0x40(%rbp),%rax\nmovslq %esi,%rdi\nmov -0x64(%rbp),%esi\nmovslq %esi,%rsi\nimul %r8,%rsi\nadd %rdi,%rsi\nmov (%rax,%rsi,4),%eax\nmov %rcx,%r8\nshr $0x2,%r8\ncmp %eax,%edx\ncmovl %eax,%edx\nmov -0x40(%rbp),%rax\nmov -0x54(%rbp),%esi\nmovslq %esi,%rdi\nmov -0x64(%rbp),%esi\nmovslq %esi,%rsi\nimul %r8,%rsi\nadd %rdi,%rsi\nmov %edx,(%rax,%rsi,4)\naddl $0x1,-0x64(%rbp)\nmov -0x58(%rbp),%eax\nsub -0x60(%rbp),%eax\ncmp %eax,-0x64(%rbp)\njle 1380 \naddl $0x1,-0x60(%rbp)\nmov -0x60(%rbp),%eax\ncmp -0x58(%rbp),%eax\njle 1374 \nmov -0x58(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x40(%rbp),%rax\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nmov %rbx,%rsp\nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\nje 150c \ncallq 1080 <__stack_chk_fail@plt>\nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 58h\nmov [rbp+s], rdi\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov rax, rsp\nmov rbx, rax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_38], eax\nmov r8d, [rbp+var_38]\nmov r9d, [rbp+var_38]\nmovsxd rax, r8d\nsub rax, 1\nmov [rbp+var_30], rax\nmovsxd rax, r8d\nlea rcx, ds:0[rax*4]\nmovsxd rax, r9d\nsub rax, 1\nmov [rbp+var_28], rax\nmovsxd rax, r8d\nmov rsi, rax\nmov edi, 0\nmovsxd rax, r9d\nmov rax, rax\nmov edx, 0\nmov r11, rdi\nimul r11, rax\nmov r10, rdx\nimul r10, rsi\nadd r10, r11\nmul rsi\nlea rsi, [r10+rdx]\nmov rdx, rsi\nmovsxd rax, r8d\nmov rsi, rax\nmov edi, 0\nmovsxd rax, r9d\nmov rax, rax\nmov edx, 0\nmov r11, rdi\nimul r11, rax\nmov r10, rdx\nimul r10, rsi\nadd r10, r11\nmul rsi\nlea rsi, [r10+rdx]\nmov rdx, rsi\nmovsxd rdx, r8d\nmovsxd rax, r9d\nimul rax, rdx\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rsi, rax\nand rsi, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rsi\nloc_1288:\ncmp rsp, rdx\njz short loc_129F\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\njmp short loc_1288\nloc_129F:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_12C9\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_12C9:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_20], rax\nmov [rbp+var_44], 0\njmp short loc_1309\nloc_12E5:\nmov rdx, rcx\nshr rdx, 2\nmov rax, [rbp+var_20]\nlea rsi, [rdx+1]\nmov edx, [rbp+var_44]\nmovsxd rdx, edx\nimul rdx, rsi\nmov dword ptr [rax+rdx*4], 1\nadd [rbp+var_44], 1\nloc_1309:\nmov eax, [rbp+var_44]\ncmp eax, [rbp+var_38]\njl short loc_12E5\nmov [rbp+var_40], 2\njmp loc_1482\nloc_131D:\nmov [rbp+var_3C], 0\njmp loc_146F\nloc_1329:\nmov edx, [rbp+var_3C]\nmov eax, [rbp+var_40]\nadd eax, edx\nsub eax, 1\nmov [rbp+var_34], eax\nmov eax, [rbp+var_3C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_34]\nmovsxd rsi, eax\nmov rax, [rbp+s]\nadd rax, rsi\nmovzx eax, byte ptr [rax]\ncmp dl, al\njnz short loc_138B\ncmp [rbp+var_40], 2\njnz short loc_138B\nmov rdi, rcx\nshr rdi, 2\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_34]\nmovsxd rsi, edx\nmov edx, [rbp+var_3C]\nmovsxd rdx, edx\nimul rdx, rdi\nadd rdx, rsi\nmov dword ptr [rax+rdx*4], 2\njmp loc_146B\nloc_138B:\nmov eax, [rbp+var_3C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_34]\nmovsxd rsi, eax\nmov rax, [rbp+s]\nadd rax, rsi\nmovzx eax, byte ptr [rax]\ncmp dl, al\njnz short loc_13FC\nmov rdi, rcx\nshr rdi, 2\nmov eax, [rbp+var_3C]\nlea edx, [rax+1]\nmov eax, [rbp+var_34]\nlea esi, [rax-1]\nmov rax, [rbp+var_20]\nmovsxd rsi, esi\nmovsxd rdx, edx\nimul rdx, rdi\nadd rdx, rsi\nmov eax, [rax+rdx*4]\nmov r8, rcx\nshr r8, 2\nlea esi, [rax+2]\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_34]\nmovsxd rdi, edx\nmov edx, [rbp+var_3C]\nmovsxd rdx, edx\nimul rdx, r8\nadd rdx, rdi\nmov [rax+rdx*4], esi\njmp short loc_146B\nloc_13FC:\nmov rdi, rcx\nshr rdi, 2\nmov eax, [rbp+var_3C]\nlea r8d, [rax+1]\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_34]\nmovsxd rsi, edx\nmovsxd rdx, r8d\nimul rdx, rdi\nadd rdx, rsi\nmov edx, [rax+rdx*4]\nmov r8, rcx\nshr r8, 2\nmov eax, [rbp+var_34]\nlea esi, [rax-1]\nmov rax, [rbp+var_20]\nmovsxd rdi, esi\nmov esi, [rbp+var_3C]\nmovsxd rsi, esi\nimul rsi, r8\nadd rsi, rdi\nmov eax, [rax+rsi*4]\nmov r8, rcx\nshr r8, 2\ncmp edx, eax\ncmovl edx, eax\nmov rax, [rbp+var_20]\nmov esi, [rbp+var_34]\nmovsxd rdi, esi\nmov esi, [rbp+var_3C]\nmovsxd rsi, esi\nimul rsi, r8\nadd rsi, rdi\nmov [rax+rsi*4], edx\nloc_146B:\nadd [rbp+var_3C], 1\nloc_146F:\nmov eax, [rbp+var_38]\nsub eax, [rbp+var_40]\ncmp [rbp+var_3C], eax\njle loc_1329\nadd [rbp+var_40], 1\nloc_1482:\nmov eax, [rbp+var_40]\ncmp eax, [rbp+var_38]\njle loc_131D\nmov eax, [rbp+var_38]\nlea edx, [rax-1]\nmov rax, [rbp+var_20]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov rsp, rbx\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njz short loc_14B5\ncall ___stack_chk_fail\nloc_14B5:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(char *a1)\n{\n unsigned __int64 v1; // rcx\n unsigned __int64 v2; // rax\n void *v3; // rsp\n int v4; // edx\n _BYTE v6[8]; // [rsp+8h] [rbp-60h] BYREF\n char *s; // [rsp+10h] [rbp-58h]\n int i; // [rsp+24h] [rbp-44h]\n int j; // [rsp+28h] [rbp-40h]\n int k; // [rsp+2Ch] [rbp-3Ch]\n int v11; // [rsp+30h] [rbp-38h]\n int v12; // [rsp+34h] [rbp-34h]\n __int64 v13; // [rsp+38h] [rbp-30h]\n __int64 v14; // [rsp+40h] [rbp-28h]\n _BYTE *v15; // [rsp+48h] [rbp-20h]\n unsigned __int64 v16; // [rsp+50h] [rbp-18h]\n\n s = a1;\n v16 = __readfsqword(0x28u);\n v11 = strlen(a1);\n v13 = v11 - 1LL;\n v1 = 4LL * v11;\n v14 = v13;\n v2 = 16 * ((4 * v11 * (__int64)v11 + 15) / 0x10uLL);\n while ( v6 != &v6[-(v2 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = alloca(v2 & 0xFFF);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)&v6[(v2 & 0xFFF) - 8] = *(_QWORD *)&v6[(v2 & 0xFFF) - 8];\n v15 = v6;\n for ( i = 0; i < v11; ++i )\n *(_DWORD *)&v15[4 * ((v1 >> 2) + 1) * i] = 1;\n for ( j = 2; j <= v11; ++j )\n {\n for ( k = 0; k <= v11 - j; ++k )\n {\n v12 = k + j - 1;\n if ( s[k] == s[v12] && j == 2 )\n {\n *(_DWORD *)&v15[4 * v12 + 4 * (v1 >> 2) * k] = 2;\n }\n else if ( s[k] == s[v12] )\n {\n *(_DWORD *)&v15[4 * v12 + 4 * (v1 >> 2) * k] = *(_DWORD *)&v15[4 * v12 - 4 + 4 * (v1 >> 2) * (k + 1)] + 2;\n }\n else\n {\n v4 = *(_DWORD *)&v15[4 * v12 + 4 * (v1 >> 2) * (k + 1)];\n if ( v4 < *(_DWORD *)&v15[4 * v12 - 4 + 4 * (v1 >> 2) * k] )\n v4 = *(_DWORD *)&v15[4 * v12 - 4 + 4 * (v1 >> 2) * k];\n *(_DWORD *)&v15[4 * v12 + 4 * (v1 >> 2) * k] = v4;\n }\n }\n }\n return *(unsigned int *)&v15[4 * v11 - 4];\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 58h\nmov [rbp+s], rdi\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov rax, rsp\nmov rbx, rax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_38], eax\nmov r8d, [rbp+var_38]\nmov r9d, [rbp+var_38]\nmovsxd rax, r8d\nsub rax, 1\nmov [rbp+var_30], rax\nmovsxd rax, r8d\nlea rcx, ds:0[rax*4]\nmovsxd rax, r9d\nsub rax, 1\nmov [rbp+var_28], rax\nmovsxd rax, r8d\nmov rsi, rax\nmov edi, 0\nmovsxd rax, r9d\nmov rax, rax\nmov edx, 0\nmov r11, rdi\nimul r11, rax\nmov r10, rdx\nimul r10, rsi\nadd r10, r11\nmul rsi\nlea rsi, [r10+rdx]\nmov rdx, rsi\nmovsxd rax, r8d\nmov rsi, rax\nmov edi, 0\nmovsxd rax, r9d\nmov rax, rax\nmov edx, 0\nmov r11, rdi\nimul r11, rax\nmov r10, rdx\nimul r10, rsi\nadd r10, r11\nmul rsi\nlea rsi, [r10+rdx]\nmov rdx, rsi\nmovsxd rdx, r8d\nmovsxd rax, r9d\nimul rax, rdx\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rsi, rax\nand rsi, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rsi\nloc_1288:\ncmp rsp, rdx\njz short loc_129F\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\njmp short loc_1288\nloc_129F:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_12C9\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_12C9:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_20], rax\nmov [rbp+var_44], 0\njmp short loc_1309\nloc_12E5:\nmov rdx, rcx\nshr rdx, 2\nmov rax, [rbp+var_20]\nlea rsi, [rdx+1]\nmov edx, [rbp+var_44]\nmovsxd rdx, edx\nimul rdx, rsi\nmov dword ptr [rax+rdx*4], 1\nadd [rbp+var_44], 1\nloc_1309:\nmov eax, [rbp+var_44]\ncmp eax, [rbp+var_38]\njl short loc_12E5\nmov [rbp+var_40], 2\njmp loc_1482\nloc_131D:\nmov [rbp+var_3C], 0\njmp loc_146F\nloc_1329:\nmov edx, [rbp+var_3C]\nmov eax, [rbp+var_40]\nadd eax, edx\nsub eax, 1\nmov [rbp+var_34], eax\nmov eax, [rbp+var_3C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_34]\nmovsxd rsi, eax\nmov rax, [rbp+s]\nadd rax, rsi\nmovzx eax, byte ptr [rax]\ncmp dl, al\njnz short loc_138B\ncmp [rbp+var_40], 2\njnz short loc_138B\nmov rdi, rcx\nshr rdi, 2\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_34]\nmovsxd rsi, edx\nmov edx, [rbp+var_3C]\nmovsxd rdx, edx\nimul rdx, rdi\nadd rdx, rsi\nmov dword ptr [rax+rdx*4], 2\njmp loc_146B\nloc_138B:\nmov eax, [rbp+var_3C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_34]\nmovsxd rsi, eax\nmov rax, [rbp+s]\nadd rax, rsi\nmovzx eax, byte ptr [rax]\ncmp dl, al\njnz short loc_13FC\nmov rdi, rcx\nshr rdi, 2\nmov eax, [rbp+var_3C]\nlea edx, [rax+1]\nmov eax, [rbp+var_34]\nlea esi, [rax-1]\nmov rax, [rbp+var_20]\nmovsxd rsi, esi\nmovsxd rdx, edx\nimul rdx, rdi\nadd rdx, rsi\nmov eax, [rax+rdx*4]\nmov r8, rcx\nshr r8, 2\nlea esi, [rax+2]\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_34]\nmovsxd rdi, edx\nmov edx, [rbp+var_3C]\nmovsxd rdx, edx\nimul rdx, r8\nadd rdx, rdi\nmov [rax+rdx*4], esi\njmp short loc_146B\nloc_13FC:\nmov rdi, rcx\nshr rdi, 2\nmov eax, [rbp+var_3C]\nlea r8d, [rax+1]\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_34]\nmovsxd rsi, edx\nmovsxd rdx, r8d\nimul rdx, rdi\nadd rdx, rsi\nmov edx, [rax+rdx*4]\nmov r8, rcx\nshr r8, 2\nmov eax, [rbp+var_34]\nlea esi, [rax-1]\nmov rax, [rbp+var_20]\nmovsxd rdi, esi\nmov esi, [rbp+var_3C]\nmovsxd rsi, esi\nimul rsi, r8\nadd rsi, rdi\nmov eax, [rax+rsi*4]\nmov r8, rcx\nshr r8, 2\ncmp edx, eax\ncmovl edx, eax\nmov rax, [rbp+var_20]\nmov esi, [rbp+var_34]\nmovsxd rdi, esi\nmov esi, [rbp+var_3C]\nmovsxd rsi, esi\nimul rsi, r8\nadd rsi, rdi\nmov [rax+rsi*4], edx\nloc_146B:\nadd [rbp+var_3C], 1\nloc_146F:\nmov eax, [rbp+var_38]\nsub eax, [rbp+var_40]\ncmp [rbp+var_3C], eax\njle loc_1329\nadd [rbp+var_40], 1\nloc_1482:\nmov eax, [rbp+var_40]\ncmp eax, [rbp+var_38]\njle loc_131D\nmov eax, [rbp+var_38]\nlea edx, [rax-1]\nmov rax, [rbp+var_20]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov rsp, rbx\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njz short loc_14B5\ncall ___stack_chk_fail\nloc_14B5:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(char *a1)\n{\n unsigned __int64 v1; // rcx\n unsigned __int64 v2; // rax\n void *v3; // rsp\n int v4; // edx\n _BYTE v6[8]; // [rsp+8h] [rbp-60h] BYREF\n char *s; // [rsp+10h] [rbp-58h]\n int i; // [rsp+24h] [rbp-44h]\n int j; // [rsp+28h] [rbp-40h]\n int k; // [rsp+2Ch] [rbp-3Ch]\n int v11; // [rsp+30h] [rbp-38h]\n int v12; // [rsp+34h] [rbp-34h]\n __int64 v13; // [rsp+38h] [rbp-30h]\n __int64 v14; // [rsp+40h] [rbp-28h]\n _BYTE *v15; // [rsp+48h] [rbp-20h]\n unsigned __int64 v16; // [rsp+50h] [rbp-18h]\n\n s = a1;\n v16 = __readfsqword(0x28u);\n v11 = strlen(a1);\n v13 = v11 - 1LL;\n v1 = 4LL * v11;\n v14 = v13;\n v2 = 16 * ((4 * v11 * (__int64)v11 + 15) / 0x10uLL);\n while ( v6 != &v6[-(v2 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = alloca(v2 & 0xFFF);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)&v6[(v2 & 0xFFF) - 8] = *(_QWORD *)&v6[(v2 & 0xFFF) - 8];\n v15 = v6;\n for ( i = 0; i < v11; ++i )\n *(_DWORD *)&v15[4 * ((v1 >> 2) + 1) * i] = 1;\n for ( j = 2; j <= v11; ++j )\n {\n for ( k = 0; k <= v11 - j; ++k )\n {\n v12 = k + j - 1;\n if ( s[k] == s[v12] && j == 2 )\n {\n *(_DWORD *)&v15[4 * v12 + 4 * (v1 >> 2) * k] = 2;\n }\n else if ( s[k] == s[v12] )\n {\n *(_DWORD *)&v15[4 * v12 + 4 * (v1 >> 2) * k] = *(_DWORD *)&v15[4 * v12 - 4 + 4 * (v1 >> 2) * (k + 1)] + 2;\n }\n else\n {\n v4 = *(_DWORD *)&v15[4 * v12 + 4 * (v1 >> 2) * (k + 1)];\n if ( v4 < *(_DWORD *)&v15[4 * v12 - 4 + 4 * (v1 >> 2) * k] )\n v4 = *(_DWORD *)&v15[4 * v12 - 4 + 4 * (v1 >> 2) * k];\n *(_DWORD *)&v15[4 * v12 + 4 * (v1 >> 2) * k] = v4;\n }\n }\n }\n return *(unsigned int *)&v15[4 * v11 - 4];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(char *a1) {\n unsigned long long v1;\n unsigned long long v2;\n void *v3;\n int v4;\n uint8_t v6[8];\n char *s;\n int i;\n int j;\n int k;\n int v11;\n int v12;\n long long v13;\n long long v14;\n uint8_t *v15;\n unsigned long long v16;\n s = a1;\n v16 = __readfsqword(40u);\n v11 = strlen(a1);\n v13 = v11 - 1LL;\n v1 = 4LL * v11;\n v14 = v13;\n v2 = 16 * ((4 * v11 * (long long)v11 + 15) / 16uLL);\n while (v6 != &v6[-(v2 & 18446744073709547520LL)])\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)&v6[(v2 & 4095) - 8] = *(uint64_t *)&v6[(v2 & 4095) - 8];\n v15 = v6;\n for (i = 0; i < v11; ++i) *(uint32_t *)&v15[4 * ((v1 >> 2) + 1) * i] = 1;\n for (j = 2; j <= v11; ++j) {\n for (k = 0; k <= v11 - j; ++k) {\n v12 = k + j - 1;\n if (s[k] == s[v12] && j == 2) {\n *(uint32_t *)&v15[4 * v12 + 4 * (v1 >> 2) * k] = 2;\n } else if (s[k] == s[v12]) {\n *(uint32_t *)&v15[4 * v12 + 4 * (v1 >> 2) * k] =\n *(uint32_t *)&v15[4 * v12 - 4 + 4 * (v1 >> 2) * (k + 1)] + 2;\n } else {\n v4 = *(uint32_t *)&v15[4 * v12 + 4 * (v1 >> 2) * (k + 1)];\n if (v4 < *(uint32_t *)&v15[4 * v12 - 4 + 4 * (v1 >> 2) * k])\n v4 = *(uint32_t *)&v15[4 * v12 - 4 + 4 * (v1 >> 2) * k];\n *(uint32_t *)&v15[4 * v12 + 4 * (v1 >> 2) * k] = v4;\n }\n }\n }\n return *(unsigned int *)&v15[4 * v11 - 4];\n}", + "ida_pseudo_norm": "long long func0(char *a1) {\n unsigned long long v1;\n unsigned long long v2;\n void *v3;\n int v4;\n uint8_t v6[8];\n char *s;\n int i;\n int j;\n int k;\n int v11;\n int v12;\n long long v13;\n long long v14;\n uint8_t *v15;\n unsigned long long v16;\n s = a1;\n v16 = __readfsqword(40u);\n v11 = strlen(a1);\n v13 = v11 - 1LL;\n v1 = 4LL * v11;\n v14 = v13;\n v2 = 16 * ((4 * v11 * (long long)v11 + 15) / 16uLL);\n while (v6 != &v6[-(v2 & 18446744073709547520LL)])\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)&v6[(v2 & 4095) - 8] = *(uint64_t *)&v6[(v2 & 4095) - 8];\n v15 = v6;\n for (i = 0; i < v11; ++i) *(uint32_t *)&v15[4 * ((v1 >> 2) + 1) * i] = 1;\n for (j = 2; j <= v11; ++j) {\n for (k = 0; k <= v11 - j; ++k) {\n v12 = k + j - 1;\n if (s[k] == s[v12] && j == 2) {\n *(uint32_t *)&v15[4 * v12 + 4 * (v1 >> 2) * k] = 2;\n } else if (s[k] == s[v12]) {\n *(uint32_t *)&v15[4 * v12 + 4 * (v1 >> 2) * k] =\n *(uint32_t *)&v15[4 * v12 - 4 + 4 * (v1 >> 2) * (k + 1)] + 2;\n } else {\n v4 = *(uint32_t *)&v15[4 * v12 + 4 * (v1 >> 2) * (k + 1)];\n if (v4 < *(uint32_t *)&v15[4 * v12 - 4 + 4 * (v1 >> 2) * k])\n v4 = *(uint32_t *)&v15[4 * v12 - 4 + 4 * (v1 >> 2) * k];\n *(uint32_t *)&v15[4 * v12 + 4 * (v1 >> 2) * k] = v4;\n }\n }\n }\n return *(unsigned int *)&v15[4 * v11 - 4];\n}" + }, + { + "index": 247, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char str[]) {\n int n = strlen(str);\n int L[n][n];\n for (int i = 0; i < n; i++) {\n L[i][i] = 1;\n }\n for (int cl = 2; cl <= n; cl++) {\n for (int i = 0; i < n - cl + 1; i++) {\n int j = i + cl - 1;\n if (str[i] == str[j] && cl == 2) {\n L[i][j] = 2;\n } else if (str[i] == str[j]) {\n L[i][j] = L[i + 1][j - 1] + 2;\n } else {\n L[i][j] = (L[i][j - 1] > L[i + 1][j]) ? L[i][j - 1] : L[i + 1][j];\n }\n }\n }\n return L[0][n - 1];\n}", + "test": "int main() {\n\n\tassert(func0(\"TENS FOR TENS\") == 5);\n\n\tassert(func0(\"CARDIO FOR CARDS\") == 7);\n\n\tassert(func0(\"PART OF THE JOURNEY IS PART\") == 9);\n\n\n\n\treturn 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0x38,%rsp\nmov %rdi,%rbx\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nmov $0xffffffffffffffff,%rcx\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nsub $0x1,%rax\nmov %rax,-0x50(%rbp)\nmov %eax,%esi\ncltq\nlea 0x0(,%rax,4),%r9\nimul %rax,%rax\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffffff0,%rdx\nand $0xfffffffffffff000,%rax\nmov %rsp,%rdi\nsub %rax,%rdi\nmov %rdi,%rax\ncmp %rax,%rsp\nje 11ec \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11d5 \nmov %rdx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 1202 \norq $0x0,-0x8(%rsp,%rax,1)\nmov %rsp,%r8\nmov %r8,-0x58(%rbp)\ncmpl $0x0,-0x50(%rbp)\njle 1235 \nmov %r9,%rcx\nshr $0x2,%rcx\nmov $0x0,%eax\nadd $0x1,%rcx\nmovslq %eax,%rdx\nimul %rcx,%rdx\nmovl $0x1,(%r8,%rdx,4)\nadd $0x1,%eax\ncmp %eax,%esi\njne 121f \nmov -0x50(%rbp),%rax\ncmp $0x1,%eax\njle 1339 \nshr $0x2,%r9\nlea 0x2(%rbx),%r12\nmov %eax,-0x44(%rbp)\nadd $0x1,%eax\nmov %eax,-0x48(%rbp)\nmov $0x2,%r11d\njmpq 1316 \ncmp %dil,%r15b\nje 12db \nmovslq %esi,%rsi\nmovslq %ecx,%rcx\nimul %r9,%rcx\nlea (%rsi,%rcx,1),%rdi\nlea (%r10,%rax,1),%r15d\nmovslq %r15d,%r15\nadd %r15,%rcx\nadd $0x1,%eax\ncltq\nimul %r9,%rax\nadd %rsi,%rax\nmov (%r8,%rax,4),%eax\ncmp %eax,(%r8,%rcx,4)\ncmovge (%r8,%rcx,4),%eax\nmov %eax,(%r8,%rdi,4)\nlea 0x1(%rdx),%rax\ncmp %rdx,%r14\nje 1308 \nmov %rax,%rdx\nmov %edx,%eax\nmov %edx,%ecx\nlea 0x0(%r13,%rdx,1),%esi\nmovzbl (%rbx,%rdx,1),%r15d\nmovzbl -0x1(%r12,%rdx,1),%edi\ncmp $0x2,%r11d\njne 125e \ncmp %dil,%r15b\njne 125e \nmovslq %esi,%rax\nmovslq %edx,%rsi\nimul %r9,%rsi\nlea (%rax,%rsi,1),%rsi\nmovl $0x2,(%r8,%rsi,4)\njmp 1298 \nmovslq %esi,%rsi\nmovslq %ecx,%rcx\nimul %r9,%rcx\nadd %rcx,%rsi\nlea (%r10,%rax,1),%ecx\nmovslq %ecx,%rcx\nadd $0x1,%eax\ncltq\nimul %r9,%rax\nadd %rax,%rcx\nmov (%r8,%rcx,4),%eax\nadd $0x2,%eax\nmov %eax,(%r8,%rsi,4)\njmp 1298 \nadd $0x1,%r11d\nadd $0x1,%r12\ncmp -0x48(%rbp),%r11d\nje 1339 \nmov %r11d,%r10d\nmov -0x44(%rbp),%eax\nsub %r11d,%eax\nmov %eax,%r14d\nmov $0x0,%edx\nlea -0x1(%r11),%r13d\nsub $0x2,%r10d\ntest %eax,%eax\njns 12a4 \njmp 1308 \nmov -0x50(%rbp),%eax\nsub $0x1,%eax\ncltq\nmov -0x58(%rbp),%rbx\nmov (%rbx,%rax,4),%eax\nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\njne 1366 \nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 28h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\ncall _strlen\nmov rdi, rax\nmov ecx, eax\ncdqe\nlea r11, ds:0[rax*4]\nimul rax, rax\nlea rax, ds:0Fh[rax*4]\nmov rsi, rax\nand rsi, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11E3:\ncmp rsp, rdx\njz short loc_11FA\nsub rsp, 1000h\nor [rsp+1050h+var_58], 0\njmp short loc_11E3\nloc_11FA:\nmov rax, rsi\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_1210\nor [rsp+rax+50h+var_58], 0\nloc_1210:\nmov r10, rsp\ntest edi, edi\njle loc_1328\nshr r11, 2\nmov eax, 0\nlea rsi, [r11+1]\nloc_1228:\nmovsxd rdx, eax\nimul rdx, rsi\nmov dword ptr [r10+rdx*4], 1\nmov r15d, eax\nadd eax, 1\ncmp ecx, eax\njnz short loc_1228\ncmp eax, 1\njle loc_1328\nsub r15d, 1\nlea r14, [rbx+2]\nlea r9d, [rdi+1]\nmov r12d, 2\nmov [rbp+var_48], r9d\nmov rdx, rdi\njmp loc_1309\nloc_1268:\ncmp r15b, r9b\njz short loc_12DA\nmovsxd r15, ecx\nmovsxd r9, eax\nimul r9, r11\nadd r15, r9\nmovsxd r8, r8d\nmovsxd r9, esi\nimul r9, r11\nadd r9, r8\nmov r8d, [r10+r15*4]\nmov r9d, [r10+r9*4]\ncmp r8d, r9d\ncmovge r9d, r8d\nloc_1296:\nmovsxd rcx, ecx\nmovsxd rsi, esi\nimul rsi, r11\nadd rcx, rsi\nmov [r10+rcx*4], r9d\nadd rax, 1\ncmp rax, r13\njz short loc_12F1\nloc_12B0:\nlea esi, [rax-1]\nmov r8d, edi\nadd edi, 1\nmov ecx, edi\nmovzx r15d, byte ptr [rbx+rax-1]\nmovzx r9d, byte ptr [r14+rax-2]\ncmp r12d, 2\njnz short loc_1268\ncmp r15b, r9b\njnz short loc_1268\nmov r9d, 2\njmp short loc_1296\nloc_12DA:\nmovsxd r8, r8d\nmovsxd r9, eax\nimul r9, r11\nadd r8, r9\nmov r9d, [r10+r8*4]\nadd r9d, 2\njmp short loc_1296\nloc_12F1:\nmov r15d, [rbp+var_44]\nloc_12F5:\nadd r12d, 1\nsub r15d, 1\nadd r14, 1\nmov eax, [rbp+var_48]\ncmp r12d, eax\njz short loc_1325\nloc_1309:\ntest r15d, r15d\njs short loc_12F5\nlea edi, [r12-2]\nmov r13d, r15d\nadd r13, 2\nmov eax, 1\nmov [rbp+var_44], r15d\njmp short loc_12B0\nloc_1325:\nmov rdi, rdx\nloc_1328:\nlea eax, [rdi-1]\ncdqe\nmov eax, [r10+rax*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_134F\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_134F:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v2; // edi\n __int64 v3; // rax\n __int16 v4; // si\n signed __int64 v5; // rax\n void *v6; // rsp\n unsigned __int64 v7; // r11\n int i; // eax\n int v9; // r15d\n int v10; // r15d\n const char *v11; // r14\n int v12; // r12d\n int v13; // edx\n int v14; // r9d\n __int64 v15; // rax\n int v16; // esi\n int v17; // r8d\n int v18; // edi\n char v19; // r15\n char v20; // r9\n __int64 v21; // r13\n _DWORD v24[2]; // [rsp+8h] [rbp-50h] BYREF\n int v25; // [rsp+10h] [rbp-48h]\n int v26; // [rsp+14h] [rbp-44h]\n unsigned __int64 v27; // [rsp+20h] [rbp-38h]\n\n v27 = __readfsqword(0x28u);\n v2 = strlen(a1);\n v3 = 4 * v2 * (__int64)v2 + 15;\n v4 = v3 & 0xFFF0;\n while ( v24 != (_DWORD *)((char *)v24 - (v3 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v5 = v3 & 0xFF0;\n v6 = alloca(v5);\n if ( (v4 & 0xFFF) != 0 )\n *(_QWORD *)((char *)&v24[-2] + v5) = *(_QWORD *)((char *)&v24[-2] + v5);\n if ( v2 > 0 )\n {\n v7 = (unsigned __int64)(4LL * v2) >> 2;\n for ( i = 0; i != v2; ++i )\n {\n v24[(v7 + 1) * i] = 1;\n v9 = i;\n }\n if ( i > 1 )\n {\n v10 = v9 - 1;\n v11 = a1 + 2;\n v12 = 2;\n v25 = v2 + 1;\n v13 = v2;\n do\n {\n if ( v10 >= 0 )\n {\n v18 = v12 - 2;\n v21 = (unsigned int)v10 + 2LL;\n v15 = 1LL;\n v26 = v10;\n do\n {\n v16 = v15 - 1;\n v17 = v18++;\n v19 = a1[v15 - 1];\n v20 = v11[v15 - 2];\n if ( v12 == 2 && v19 == v20 )\n {\n v14 = 2;\n }\n else if ( v19 == v20 )\n {\n v14 = v24[v7 * (int)v15 + v17] + 2;\n }\n else\n {\n v14 = v24[v17 + v7 * v16];\n if ( v24[v7 * (int)v15 + v18] >= v14 )\n v14 = v24[v7 * (int)v15 + v18];\n }\n v24[v7 * v16 + v18] = v14;\n ++v15;\n }\n while ( v15 != v21 );\n v10 = v26;\n }\n ++v12;\n --v10;\n ++v11;\n }\n while ( v12 != v25 );\n v2 = v13;\n }\n }\n return (unsigned int)v24[v2 - 1];\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 28h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\ncall _strlen\nmov rdi, rax\nmov ecx, eax\ncdqe\nlea r11, ds:0[rax*4]\nimul rax, rax\nlea rax, ds:0Fh[rax*4]\nmov rsi, rax\nand rsi, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11E3:\ncmp rsp, rdx\njz short loc_11FA\nsub rsp, 1000h\nor [rsp+1050h+var_58], 0\njmp short loc_11E3\nloc_11FA:\nmov rax, rsi\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_1210\nor [rsp+rax+50h+var_58], 0\nloc_1210:\nmov r10, rsp\ntest edi, edi\njle loc_1328\nshr r11, 2\nmov eax, 0\nlea rsi, [r11+1]\nloc_1228:\nmovsxd rdx, eax\nimul rdx, rsi\nmov dword ptr [r10+rdx*4], 1\nmov r15d, eax\nadd eax, 1\ncmp ecx, eax\njnz short loc_1228\ncmp eax, 1\njle loc_1328\nsub r15d, 1\nlea r14, [rbx+2]\nlea r9d, [rdi+1]\nmov r12d, 2\nmov [rbp+var_48], r9d\nmov rdx, rdi\njmp loc_1309\nloc_1268:\ncmp r15b, r9b\njz short loc_12DA\nmovsxd r15, ecx\nmovsxd r9, eax\nimul r9, r11\nadd r15, r9\nmovsxd r8, r8d\nmovsxd r9, esi\nimul r9, r11\nadd r9, r8\nmov r8d, [r10+r15*4]\nmov r9d, [r10+r9*4]\ncmp r8d, r9d\ncmovge r9d, r8d\nloc_1296:\nmovsxd rcx, ecx\nmovsxd rsi, esi\nimul rsi, r11\nadd rcx, rsi\nmov [r10+rcx*4], r9d\nadd rax, 1\ncmp rax, r13\njz short loc_12F1\nloc_12B0:\nlea esi, [rax-1]\nmov r8d, edi\nadd edi, 1\nmov ecx, edi\nmovzx r15d, byte ptr [rbx+rax-1]\nmovzx r9d, byte ptr [r14+rax-2]\ncmp r12d, 2\njnz short loc_1268\ncmp r15b, r9b\njnz short loc_1268\nmov r9d, 2\njmp short loc_1296\nloc_12DA:\nmovsxd r8, r8d\nmovsxd r9, eax\nimul r9, r11\nadd r8, r9\nmov r9d, [r10+r8*4]\nadd r9d, 2\njmp short loc_1296\nloc_12F1:\nmov r15d, [rbp+var_44]\nloc_12F5:\nadd r12d, 1\nsub r15d, 1\nadd r14, 1\nmov eax, [rbp+var_48]\ncmp r12d, eax\njz short loc_1325\nloc_1309:\ntest r15d, r15d\njs short loc_12F5\nlea edi, [r12-2]\nmov r13d, r15d\nadd r13, 2\nmov eax, 1\nmov [rbp+var_44], r15d\njmp short loc_12B0\nloc_1325:\nmov rdi, rdx\nloc_1328:\nlea eax, [rdi-1]\ncdqe\nmov eax, [r10+rax*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_134F\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_134F:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(const char *a1)\n{\n int v2; // edi\n __int64 v3; // rax\n __int16 v4; // si\n signed __int64 v5; // rax\n void *v6; // rsp\n unsigned __int64 v7; // r11\n int i; // eax\n int v9; // r15d\n int v10; // r15d\n const char *v11; // r14\n int v12; // r12d\n int v13; // edx\n int v14; // r9d\n __int64 v15; // rax\n int v16; // esi\n int v17; // r8d\n int v18; // edi\n char v19; // r15\n char v20; // r9\n __int64 v21; // r13\n _DWORD v24[2]; // [rsp+8h] [rbp-50h] BYREF\n int v25; // [rsp+10h] [rbp-48h]\n int v26; // [rsp+14h] [rbp-44h]\n unsigned __int64 v27; // [rsp+20h] [rbp-38h]\n\n v27 = __readfsqword(0x28u);\n v2 = strlen(a1);\n v3 = 4 * v2 * (__int64)v2 + 15;\n v4 = v3 & 0xFFF0;\n while ( v24 != (_DWORD *)((char *)v24 - (v3 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v5 = v3 & 0xFF0;\n v6 = alloca(v5);\n if ( (v4 & 0xFFF) != 0 )\n *(_QWORD *)((char *)&v24[-2] + v5) = *(_QWORD *)((char *)&v24[-2] + v5);\n if ( v2 > 0 )\n {\n v7 = (unsigned __int64)(4LL * v2) >> 2;\n for ( i = 0; i != v2; ++i )\n {\n v24[(v7 + 1) * i] = 1;\n v9 = i;\n }\n if ( i > 1 )\n {\n v10 = v9 - 1;\n v11 = a1 + 2;\n v12 = 2;\n v25 = v2 + 1;\n v13 = v2;\n do\n {\n if ( v10 >= 0 )\n {\n v18 = v12 - 2;\n v21 = (unsigned int)v10 + 2LL;\n v15 = 1LL;\n v26 = v10;\n do\n {\n v16 = v15 - 1;\n v17 = v18++;\n v19 = a1[v15 - 1];\n v20 = v11[v15 - 2];\n if ( v12 == 2 && v19 == v20 )\n {\n v14 = 2;\n }\n else if ( v19 == v20 )\n {\n v14 = v24[v7 * (int)v15 + v17] + 2;\n }\n else\n {\n v14 = v24[v17 + v7 * v16];\n if ( v24[v7 * (int)v15 + v18] >= v14 )\n v14 = v24[v7 * (int)v15 + v18];\n }\n v24[v7 * v16 + v18] = v14;\n ++v15;\n }\n while ( v15 != v21 );\n v10 = v26;\n }\n ++v12;\n --v10;\n ++v11;\n }\n while ( v12 != v25 );\n v2 = v13;\n }\n }\n return (unsigned int)v24[v2 - 1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(const char *a1) {\n int v2;\n long long v3;\n short v4;\n signed long long v5;\n void *v6;\n unsigned long long v7;\n int i;\n int v9;\n int v10;\n const char *v11;\n int v12;\n int v13;\n int v14;\n long long v15;\n int v16;\n int v17;\n int v18;\n char v19;\n char v20;\n long long v21;\n uint32_t v24[2];\n int v25;\n int v26;\n unsigned long long v27;\n v27 = __readfsqword(40u);\n v2 = strlen(a1);\n v3 = 4 * v2 * (long long)v2 + 15;\n v4 = v3 & 65520;\n while (v24 != (uint32_t *)((char *)v24 - (v3 & 18446744073709547520LL)))\n ;\n v5 = v3 & 4080;\n v6 = alloca(v5);\n if ((v4 & 4095) != 0)\n *(uint64_t *)((char *)&v24[-2] + v5) = *(uint64_t *)((char *)&v24[-2] + v5);\n if (v2 > 0) {\n v7 = (unsigned long long)(4LL * v2) >> 2;\n for (i = 0; i != v2; ++i) {\n v24[(v7 + 1) * i] = 1;\n v9 = i;\n }\n if (i > 1) {\n v10 = v9 - 1;\n v11 = a1 + 2;\n v12 = 2;\n v25 = v2 + 1;\n v13 = v2;\n do {\n if (v10 >= 0) {\n v18 = v12 - 2;\n v21 = (unsigned int)v10 + 2LL;\n v15 = 1LL;\n v26 = v10;\n do {\n v16 = v15 - 1;\n v17 = v18++;\n v19 = a1[v15 - 1];\n v20 = v11[v15 - 2];\n if (v12 == 2 && v19 == v20) {\n v14 = 2;\n } else if (v19 == v20) {\n v14 = v24[v7 * (int)v15 + v17] + 2;\n } else {\n v14 = v24[v17 + v7 * v16];\n if (v24[v7 * (int)v15 + v18] >= v14)\n v14 = v24[v7 * (int)v15 + v18];\n }\n v24[v7 * v16 + v18] = v14;\n ++v15;\n } while (v15 != v21);\n v10 = v26;\n }\n ++v12;\n --v10;\n ++v11;\n } while (v12 != v25);\n v2 = v13;\n }\n }\n return (unsigned int)v24[v2 - 1];\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v2;\n long long v3;\n short v4;\n signed long long v5;\n void *v6;\n unsigned long long v7;\n int i;\n int v9;\n int v10;\n const char *v11;\n int v12;\n int v13;\n int v14;\n long long v15;\n int v16;\n int v17;\n int v18;\n char v19;\n char v20;\n long long v21;\n uint32_t v24[2];\n int v25;\n int v26;\n unsigned long long v27;\n v27 = __readfsqword(40u);\n v2 = strlen(a1);\n v3 = 4 * v2 * (long long)v2 + 15;\n v4 = v3 & 65520;\n while (v24 != (uint32_t *)((char *)v24 - (v3 & 18446744073709547520LL)))\n ;\n v5 = v3 & 4080;\n v6 = alloca(v5);\n if ((v4 & 4095) != 0)\n *(uint64_t *)((char *)&v24[-2] + v5) = *(uint64_t *)((char *)&v24[-2] + v5);\n if (v2 > 0) {\n v7 = (unsigned long long)(4LL * v2) >> 2;\n for (i = 0; i != v2; ++i) {\n v24[(v7 + 1) * i] = 1;\n v9 = i;\n }\n if (i > 1) {\n v10 = v9 - 1;\n v11 = a1 + 2;\n v12 = 2;\n v25 = v2 + 1;\n v13 = v2;\n do {\n if (v10 >= 0) {\n v18 = v12 - 2;\n v21 = (unsigned int)v10 + 2LL;\n v15 = 1LL;\n v26 = v10;\n do {\n v16 = v15 - 1;\n v17 = v18++;\n v19 = a1[v15 - 1];\n v20 = v11[v15 - 2];\n if (v12 == 2 && v19 == v20) {\n v14 = 2;\n } else if (v19 == v20) {\n v14 = v24[v7 * (int)v15 + v17] + 2;\n } else {\n v14 = v24[v17 + v7 * v16];\n if (v24[v7 * (int)v15 + v18] >= v14)\n v14 = v24[v7 * (int)v15 + v18];\n }\n v24[v7 * v16 + v18] = v14;\n ++v15;\n } while (v15 != v21);\n v10 = v26;\n }\n ++v12;\n --v10;\n ++v11;\n } while (v12 != v25);\n v2 = v13;\n }\n }\n return (unsigned int)v24[v2 - 1];\n}" + }, + { + "index": 247, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char str[]) {\n int n = strlen(str);\n int L[n][n];\n for (int i = 0; i < n; i++) {\n L[i][i] = 1;\n }\n for (int cl = 2; cl <= n; cl++) {\n for (int i = 0; i < n - cl + 1; i++) {\n int j = i + cl - 1;\n if (str[i] == str[j] && cl == 2) {\n L[i][j] = 2;\n } else if (str[i] == str[j]) {\n L[i][j] = L[i + 1][j - 1] + 2;\n } else {\n L[i][j] = (L[i][j - 1] > L[i + 1][j]) ? L[i][j - 1] : L[i + 1][j];\n }\n }\n }\n return L[0][n - 1];\n}", + "test": "int main() {\n\n\tassert(func0(\"TENS FOR TENS\") == 5);\n\n\tassert(func0(\"CARDIO FOR CARDS\") == 7);\n\n\tassert(func0(\"PART OF THE JOURNEY IS PART\") == 9);\n\n\n\n\treturn 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\nmov %rdi,%r14\npush %r13\npush %r12\npush %rbx\nsub $0x28,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nmov %rsp,%rbx\ncallq 1070 \nmovslq %eax,%rdx\nmov %rax,-0x50(%rbp)\nmov %eax,%ecx\nmov %rdx,%rax\nimul %rdx,%rax\nlea 0xf(,%rax,4),%rax\nmov %rax,%rsi\nand $0xfffffffffffff000,%rax\nsub %rax,%rbx\nand $0xfffffffffffffff0,%rsi\nmov %rbx,%rax\ncmp %rax,%rsp\nje 12a4 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 128f \nand $0xfff,%esi\nsub %rsi,%rsp\ntest %rsi,%rsi\njne 1424 \nlea 0x0(,%rdx,4),%r10\nmov -0x50(%rbp),%edx\nmov %rsp,%r8\nxor %eax,%eax\nshr $0x2,%r10\nlea 0x1(%r10),%rsi\ntest %edx,%edx\njle 13dd \nnopw %cs:0x0(%rax,%rax,1)\nmovslq %eax,%rdx\nadd $0x1,%eax\nimul %rsi,%rdx\nmovl $0x1,(%r8,%rdx,4)\ncmp %eax,%ecx\njne 12e0 \nmov -0x50(%rbp),%rax\ncmp $0x1,%eax\njle 13dd \nmov %eax,-0x44(%rbp)\nadd $0x1,%eax\nlea 0x2(%r14),%r11\nmov $0x2,%r13d\nmov %eax,-0x48(%rbp)\nnopw %cs:0x0(%rax,%rax,1)\nmov -0x44(%rbp),%edx\nmov $0x0,%eax\nlea -0x1(%r13),%ebx\nlea -0x2(%r13),%r15d\nsub %r13d,%edx\nmov %edx,%r12d\njns 137f \njmpq 13cb \nnopl (%rax)\nmovslq %eax,%rsi\nmovslq %ecx,%rcx\nimul %r10,%rsi\nimul %r10,%rcx\nlea (%rdx,%rsi,1),%rdi\nmov %rsi,%r9\nlea (%r15,%rax,1),%esi\nmovslq %esi,%rsi\nadd %rdx,%rcx\nadd %r9,%rsi\nmov (%r8,%rcx,4),%edx\ncmp %edx,(%r8,%rsi,4)\ncmovge (%r8,%rsi,4),%edx\nmov %edx,(%r8,%rdi,4)\nlea 0x1(%rax),%rdx\ncmp %rax,%r12\nje 13cb \nmov %rdx,%rax\nlea (%rbx,%rax,1),%edx\nmovzbl -0x1(%rax,%r11,1),%edi\nmovslq %eax,%rsi\nlea 0x1(%rax),%ecx\nmovslq %edx,%rdx\ncmp %dil,(%r14,%rax,1)\njne 1340 \ncmp $0x2,%r13d\nje 1410 \nmovslq %ecx,%rcx\nmovslq %esi,%rdi\nadd %r15d,%esi\nimul %r10,%rcx\nmovslq %esi,%rsi\nimul %r10,%rdi\nadd %rsi,%rcx\nmov (%r8,%rcx,4),%ecx\nadd %rdi,%rdx\nadd $0x2,%ecx\nmov %ecx,(%r8,%rdx,4)\nlea 0x1(%rax),%rdx\ncmp %rax,%r12\njne 137c \nadd $0x1,%r13d\nadd $0x1,%r11\ncmp -0x48(%rbp),%r13d\njne 1320 \nmov -0x50(%rbp),%eax\nsub $0x1,%eax\nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\ncltq\nmov (%r8,%rax,4),%eax\njne 142f \nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\nnopw 0x0(%rax,%rax,1)\nimul %r10,%rsi\nadd %rsi,%rdx\nmovl $0x2,(%r8,%rdx,4)\njmpq 1373 \norq $0x0,-0x8(%rsp,%rsi,1)\njmpq 12b6 \ncallq 1080 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nmov rbx, rdi\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\ncall _strlen\nmov rsi, rsp\nmov r12, rax\nmov ecx, eax\ncdqe\nlea r9, ds:0[rax*4]\nimul rax, rax\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rsi, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rsi\njz short loc_12A4\nloc_128F:\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\ncmp rsp, rsi\njnz short loc_128F\nloc_12A4:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_13CD\nloc_12B6:\nmov r8, rsp\ntest r12d, r12d\njle loc_138E\nshr r9, 2\nxor eax, eax\nlea rsi, [r9+1]\nnop dword ptr [rax+00h]\nloc_12D0:\nmovsxd rdx, eax\nmov r11d, eax\nadd eax, 1\nimul rdx, rsi\nmov dword ptr [r8+rdx*4], 1\ncmp ecx, eax\njnz short loc_12D0\ncmp r12d, 1\njz loc_138E\nmov r10d, 2\nnop dword ptr [rax+00000000h]\nloc_1300:\nmov rsi, rbx\nlea edi, [r10-2]\nxor ecx, ecx\njmp short loc_134D\nloc_1310:\nmovsxd r14, ecx\nmov r15, rax\nmovsxd r13, edi\nimul r15, r9\nimul r14, r9\nadd rdx, r15\nadd r14, r13\nmov r15d, [r8+r14*4]\nmov r14d, [r8+rdx*4]\ncmp r15d, r14d\nmov edx, r14d\ncmovge edx, r15d\nloc_1339:\nimul rax, r9\nadd rsi, 1\nadd rax, r13\nmov [r8+rax*4], edx\ncmp ecx, r11d\njz short loc_1380\nloc_134D:\nmovsxd rdx, edi\nmovsxd rax, ecx\nmovzx r15d, byte ptr [rsi+r10-1]\nadd edi, 1\nadd ecx, 1\ncmp [rsi], r15b\njnz short loc_1310\ncmp r10, 2\njz short loc_13C0\nmovsxd r13, ecx\nimul r13, r9\nadd rdx, r13\nmovsxd r13, edi\nmov edx, [r8+rdx*4]\nadd edx, 2\njmp short loc_1339\nloc_1380:\nadd r10, 1\nsub r11d, 1\njnz loc_1300\nloc_138E:\nlea eax, [r12-1]\ncdqe\nmov eax, [r8+rax*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_13D8\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_13C0:\nmov edx, 2\nmovsxd r13, edi\njmp loc_1339\nloc_13CD:\nor [rsp+rdx+1040h+var_1048], 0\njmp loc_12B6\nloc_13D8:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v2; // r12d\n __int64 v3; // rdx\n _DWORD *v4; // rsi\n __int16 v5; // dx\n signed __int64 v6; // rdx\n void *v7; // rsp\n unsigned __int64 v8; // r9\n int i; // eax\n __int64 v10; // rdx\n int v11; // r11d\n __int64 v12; // r10\n const char *v13; // rsi\n int v14; // edi\n int v15; // ecx\n __int64 v16; // r13\n int v17; // edx\n __int64 v18; // rdx\n __int64 v19; // rax\n _DWORD v22[1022]; // [rsp+8h] [rbp-1040h] BYREF\n _QWORD v23[8]; // [rsp+1008h] [rbp-40h] BYREF\n\n v23[1] = __readfsqword(0x28u);\n v2 = strlen(a1);\n v3 = 4 * v2 * (__int64)v2 + 15;\n v4 = (_DWORD *)((char *)v23 - (v3 & 0xFFFFFFFFFFFFF000LL));\n v5 = v3 & 0xFFF0;\n if ( v23 != (_QWORD *)v4 )\n {\n while ( v22 != v4 )\n ;\n }\n v6 = v5 & 0xFFF;\n v7 = alloca(v6);\n if ( v6 )\n *(_QWORD *)((char *)&v22[-2] + v6) = *(_QWORD *)((char *)&v22[-2] + v6);\n if ( v2 > 0 )\n {\n v8 = (unsigned __int64)(4LL * v2) >> 2;\n for ( i = 0; i != v2; ++i )\n {\n v10 = i;\n v11 = i;\n v22[(v8 + 1) * v10] = 1;\n }\n if ( v2 != 1 )\n {\n v12 = 2LL;\n do\n {\n v13 = a1;\n v14 = v12 - 2;\n v15 = 0;\n do\n {\n v18 = v14;\n v19 = v15;\n ++v14;\n ++v15;\n if ( *v13 == v13[v12 - 1] )\n {\n if ( v12 == 2 )\n {\n v17 = 2;\n v16 = v14;\n }\n else\n {\n v16 = v14;\n v17 = v22[v8 * v15 + v18] + 2;\n }\n }\n else\n {\n v16 = v14;\n v17 = v22[v8 * v19 + v18];\n if ( v22[v14 + v8 * v15] >= v17 )\n v17 = v22[v14 + v8 * v15];\n }\n ++v13;\n v22[v16 + v8 * v19] = v17;\n }\n while ( v15 != v11 );\n ++v12;\n --v11;\n }\n while ( v11 );\n }\n }\n return (unsigned int)v22[v2 - 1];\n}", + "ida_strip_asm": "sub_1230:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nmov rbx, rdi\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\ncall _strlen\nmov rsi, rsp\nmov r12, rax\nmov ecx, eax\ncdqe\nlea r9, ds:0[rax*4]\nimul rax, rax\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rsi, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rsi\njz short loc_12A4\nloc_128F:\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\ncmp rsp, rsi\njnz short loc_128F\nloc_12A4:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_13CD\nloc_12B6:\nmov r8, rsp\ntest r12d, r12d\njle loc_138E\nshr r9, 2\nxor eax, eax\nlea rsi, [r9+1]\nnop dword ptr [rax+00h]\nloc_12D0:\nmovsxd rdx, eax\nmov r11d, eax\nadd eax, 1\nimul rdx, rsi\nmov dword ptr [r8+rdx*4], 1\ncmp ecx, eax\njnz short loc_12D0\ncmp r12d, 1\njz loc_138E\nmov r10d, 2\nnop dword ptr [rax+00000000h]\nloc_1300:\nmov rsi, rbx\nlea edi, [r10-2]\nxor ecx, ecx\njmp short loc_134D\nloc_1310:\nmovsxd r14, ecx\nmov r15, rax\nmovsxd r13, edi\nimul r15, r9\nimul r14, r9\nadd rdx, r15\nadd r14, r13\nmov r15d, [r8+r14*4]\nmov r14d, [r8+rdx*4]\ncmp r15d, r14d\nmov edx, r14d\ncmovge edx, r15d\nloc_1339:\nimul rax, r9\nadd rsi, 1\nadd rax, r13\nmov [r8+rax*4], edx\ncmp ecx, r11d\njz short loc_1380\nloc_134D:\nmovsxd rdx, edi\nmovsxd rax, ecx\nmovzx r15d, byte ptr [rsi+r10-1]\nadd edi, 1\nadd ecx, 1\ncmp [rsi], r15b\njnz short loc_1310\ncmp r10, 2\njz short loc_13C0\nmovsxd r13, ecx\nimul r13, r9\nadd rdx, r13\nmovsxd r13, edi\nmov edx, [r8+rdx*4]\nadd edx, 2\njmp short loc_1339\nloc_1380:\nadd r10, 1\nsub r11d, 1\njnz loc_1300\nloc_138E:\nlea eax, [r12-1]\ncdqe\nmov eax, [r8+rax*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_13D8\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_13C0:\nmov edx, 2\nmovsxd r13, edi\njmp loc_1339\nloc_13CD:\nor [rsp+rdx+1040h+var_1048], 0\njmp loc_12B6\nloc_13D8:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1230(const char *a1)\n{\n int v2; // r12d\n __int64 v3; // rdx\n _DWORD *v4; // rsi\n __int16 v5; // dx\n signed __int64 v6; // rdx\n void *v7; // rsp\n unsigned __int64 v8; // r9\n int i; // eax\n __int64 v10; // rdx\n int v11; // r11d\n __int64 v12; // r10\n const char *v13; // rsi\n int v14; // edi\n int v15; // ecx\n __int64 v16; // r13\n int v17; // edx\n __int64 v18; // rdx\n __int64 v19; // rax\n _DWORD v22[1022]; // [rsp+8h] [rbp-1040h] BYREF\n _QWORD v23[8]; // [rsp+1008h] [rbp-40h] BYREF\n\n v23[1] = __readfsqword(0x28u);\n v2 = strlen(a1);\n v3 = 4 * v2 * (__int64)v2 + 15;\n v4 = (_DWORD *)((char *)v23 - (v3 & 0xFFFFFFFFFFFFF000LL));\n v5 = v3 & 0xFFF0;\n if ( v23 != (_QWORD *)v4 )\n {\n while ( v22 != v4 )\n ;\n }\n v6 = v5 & 0xFFF;\n v7 = alloca(v6);\n if ( v6 )\n *(_QWORD *)((char *)&v22[-2] + v6) = *(_QWORD *)((char *)&v22[-2] + v6);\n if ( v2 > 0 )\n {\n v8 = (unsigned __int64)(4LL * v2) >> 2;\n for ( i = 0; i != v2; ++i )\n {\n v10 = i;\n v11 = i;\n v22[(v8 + 1) * v10] = 1;\n }\n if ( v2 != 1 )\n {\n v12 = 2LL;\n do\n {\n v13 = a1;\n v14 = v12 - 2;\n v15 = 0;\n do\n {\n v18 = v14;\n v19 = v15;\n ++v14;\n ++v15;\n if ( *v13 == v13[v12 - 1] )\n {\n if ( v12 == 2 )\n {\n v17 = 2;\n v16 = v14;\n }\n else\n {\n v16 = v14;\n v17 = v22[v8 * v15 + v18] + 2;\n }\n }\n else\n {\n v16 = v14;\n v17 = v22[v8 * v19 + v18];\n if ( v22[v14 + v8 * v15] >= v17 )\n v17 = v22[v14 + v8 * v15];\n }\n ++v13;\n v22[v16 + v8 * v19] = v17;\n }\n while ( v15 != v11 );\n ++v12;\n --v11;\n }\n while ( v11 );\n }\n }\n return (unsigned int)v22[v2 - 1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1230(const char *a1) {\n int v2;\n long long v3;\n uint32_t *v4;\n short v5;\n signed long long v6;\n void *v7;\n unsigned long long v8;\n int i;\n long long v10;\n int v11;\n long long v12;\n const char *v13;\n int v14;\n int v15;\n long long v16;\n int v17;\n long long v18;\n long long v19;\n uint32_t v22[1022];\n uint64_t v23[8];\n v23[1] = __readfsqword(40u);\n v2 = strlen(a1);\n v3 = 4 * v2 * (long long)v2 + 15;\n v4 = (uint32_t *)((char *)v23 - (v3 & 18446744073709547520LL));\n v5 = v3 & 65520;\n if (v23 != (uint64_t *)v4) {\n while (v22 != v4)\n ;\n }\n v6 = v5 & 4095;\n v7 = alloca(v6);\n if (v6)\n *(uint64_t *)((char *)&v22[-2] + v6) = *(uint64_t *)((char *)&v22[-2] + v6);\n if (v2 > 0) {\n v8 = (unsigned long long)(4LL * v2) >> 2;\n for (i = 0; i != v2; ++i) {\n v10 = i;\n v11 = i;\n v22[(v8 + 1) * v10] = 1;\n }\n if (v2 != 1) {\n v12 = 2LL;\n do {\n v13 = a1;\n v14 = v12 - 2;\n v15 = 0;\n do {\n v18 = v14;\n v19 = v15;\n ++v14;\n ++v15;\n if (*v13 == v13[v12 - 1]) {\n if (v12 == 2) {\n v17 = 2;\n v16 = v14;\n } else {\n v16 = v14;\n v17 = v22[v8 * v15 + v18] + 2;\n }\n } else {\n v16 = v14;\n v17 = v22[v8 * v19 + v18];\n if (v22[v14 + v8 * v15] >= v17) v17 = v22[v14 + v8 * v15];\n }\n ++v13;\n v22[v16 + v8 * v19] = v17;\n } while (v15 != v11);\n ++v12;\n --v11;\n } while (v11);\n }\n }\n return (unsigned int)v22[v2 - 1];\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v2;\n long long v3;\n uint32_t *v4;\n short v5;\n signed long long v6;\n void *v7;\n unsigned long long v8;\n int i;\n long long v10;\n int v11;\n long long v12;\n const char *v13;\n int v14;\n int v15;\n long long v16;\n int v17;\n long long v18;\n long long v19;\n uint32_t v22[1022];\n uint64_t v23[8];\n v23[1] = __readfsqword(40u);\n v2 = strlen(a1);\n v3 = 4 * v2 * (long long)v2 + 15;\n v4 = (uint32_t *)((char *)v23 - (v3 & 18446744073709547520LL));\n v5 = v3 & 65520;\n if (v23 != (uint64_t *)v4) {\n while (v22 != v4)\n ;\n }\n v6 = v5 & 4095;\n v7 = alloca(v6);\n if (v6)\n *(uint64_t *)((char *)&v22[-2] + v6) = *(uint64_t *)((char *)&v22[-2] + v6);\n if (v2 > 0) {\n v8 = (unsigned long long)(4LL * v2) >> 2;\n for (i = 0; i != v2; ++i) {\n v10 = i;\n v11 = i;\n v22[(v8 + 1) * v10] = 1;\n }\n if (v2 != 1) {\n v12 = 2LL;\n do {\n v13 = a1;\n v14 = v12 - 2;\n v15 = 0;\n do {\n v18 = v14;\n v19 = v15;\n ++v14;\n ++v15;\n if (*v13 == v13[v12 - 1]) {\n if (v12 == 2) {\n v17 = 2;\n v16 = v14;\n } else {\n v16 = v14;\n v17 = v22[v8 * v15 + v18] + 2;\n }\n } else {\n v16 = v14;\n v17 = v22[v8 * v19 + v18];\n if (v22[v14 + v8 * v15] >= v17) v17 = v22[v14 + v8 * v15];\n }\n ++v13;\n v22[v16 + v8 * v19] = v17;\n } while (v15 != v11);\n ++v12;\n --v11;\n } while (v11);\n }\n }\n return (unsigned int)v22[v2 - 1];\n}" + }, + { + "index": 247, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char str[]) {\n int n = strlen(str);\n int L[n][n];\n for (int i = 0; i < n; i++) {\n L[i][i] = 1;\n }\n for (int cl = 2; cl <= n; cl++) {\n for (int i = 0; i < n - cl + 1; i++) {\n int j = i + cl - 1;\n if (str[i] == str[j] && cl == 2) {\n L[i][j] = 2;\n } else if (str[i] == str[j]) {\n L[i][j] = L[i + 1][j - 1] + 2;\n } else {\n L[i][j] = (L[i][j - 1] > L[i + 1][j]) ? L[i][j - 1] : L[i + 1][j];\n }\n }\n }\n return L[0][n - 1];\n}", + "test": "int main() {\n\n\tassert(func0(\"TENS FOR TENS\") == 5);\n\n\tassert(func0(\"CARDIO FOR CARDS\") == 7);\n\n\tassert(func0(\"PART OF THE JOURNEY IS PART\") == 9);\n\n\n\n\treturn 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbx\nmov %rdi,%rbx\nsub $0x38,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\ncallq 1070 \nmov %rsp,%rdi\nmovslq %eax,%rdx\nmov %rax,-0x50(%rbp)\nmov %eax,%ecx\nmov %rdx,%rax\nimul %rdx,%rax\nlea 0xf(,%rax,4),%rax\nmov %rax,%rsi\nand $0xfffffffffffff000,%rax\nsub %rax,%rdi\nand $0xfffffffffffffff0,%rsi\nmov %rdi,%rax\ncmp %rax,%rsp\nje 12a4 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 128f \nand $0xfff,%esi\nsub %rsi,%rsp\ntest %rsi,%rsi\njne 147e \nlea 0x0(,%rdx,4),%r10\nmov -0x50(%rbp),%edx\nmov %rsp,%r8\nxor %eax,%eax\nshr $0x2,%r10\nlea 0x1(%r10),%rdi\nmov %rdi,-0x60(%rbp)\nmov %rdi,%rsi\ntest %edx,%edx\njle 13de \nnopl (%rax)\nmovslq %eax,%rdx\nadd $0x1,%eax\nimul %rsi,%rdx\nmovl $0x1,(%r8,%rdx,4)\ncmp %eax,%ecx\njne 12e0 \nmov -0x50(%rbp),%rax\ncmp $0x1,%eax\njle 13de \nmov %eax,%edi\nmov %eax,-0x44(%rbp)\nadd $0x1,%eax\nlea 0x2(%rbx),%r11\nmov %eax,-0x48(%rbp)\nlea -0x2(%rdi),%eax\nmov $0x2,%r13d\nmov %rax,-0x58(%rbp)\nmov -0x44(%rbp),%r9d\nsub %r13d,%r9d\njs 13cc \ncmp $0x2,%r13d\nje 1410 \nmov %r9d,%r9d\nlea -0x1(%r13),%r14d\nlea -0x2(%r13),%r15d\nxor %eax,%eax\njmp 1388 \nnopw %cs:0x0(%rax,%rax,1)\nmovslq %esi,%rsi\nlea (%rdx,%rcx,1),%rdi\nmov %rcx,%r12\nimul %r10,%rsi\nlea (%r15,%rax,1),%ecx\nmovslq %ecx,%rcx\nadd %r12,%rcx\nadd %rsi,%rdx\nmov (%r8,%rdx,4),%edx\ncmp %edx,(%r8,%rcx,4)\ncmovge (%r8,%rcx,4),%edx\nmov %edx,(%r8,%rdi,4)\nlea 0x1(%rax),%rdx\ncmp %r9,%rax\nje 13cc \nmov %rdx,%rax\nlea (%r14,%rax,1),%edx\nmovslq %eax,%rcx\nmovzbl (%rbx,%rax,1),%edi\nlea 0x1(%rax),%esi\nimul %r10,%rcx\nmovslq %edx,%rdx\ncmp %dil,-0x1(%rax,%r11,1)\njne 1350 \nmovslq %esi,%rsi\nadd %rdx,%rcx\nlea (%r15,%rax,1),%edx\nimul %r10,%rsi\nmovslq %edx,%rdx\nadd %rdx,%rsi\nmov (%r8,%rsi,4),%edx\nadd $0x2,%edx\nmov %edx,(%r8,%rcx,4)\nlea 0x1(%rax),%rdx\ncmp %r9,%rax\njne 1385 \nadd $0x1,%r13d\nadd $0x1,%r11\ncmp -0x48(%rbp),%r13d\njne 1320 \nmov -0x50(%rbp),%eax\nsub $0x1,%eax\nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\ncltq\nmov (%r8,%rax,4),%eax\njne 1489 \nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\nnopl 0x0(%rax)\nmov -0x60(%rbp),%rsi\nmov -0x58(%rbp),%rdi\nxor %eax,%eax\njmp 1459 \nnopl 0x0(%rax)\nmovslq %eax,%rcx\nmovslq %edx,%rdx\nmov %rcx,%r9\nimul %rsi,%rcx\nimul %r10,%r9\nmov (%r8,%rcx,4),%ecx\nadd %rdx,%r9\nimul %rsi,%rdx\ncmp %ecx,(%r8,%rdx,4)\ncmovge (%r8,%rdx,4),%ecx\nmov %ecx,(%r8,%r9,4)\nlea 0x1(%rax),%rdx\ncmp %rdi,%rax\nje 13cc \nmov %rdx,%rax\nmovzbl -0x1(%rax,%r11,1),%ecx\nlea 0x1(%rax),%edx\ncmp %cl,(%rbx,%rax,1)\njne 1420 \nmovslq %edx,%rcx\nmovslq %eax,%rdx\nimul %r10,%rdx\nadd %rcx,%rdx\nmovl $0x2,(%r8,%rdx,4)\njmp 1449 \norq $0x0,-0x8(%rsp,%rsi,1)\njmpq 12b6 \ncallq 1080 <__stack_chk_fail@plt>\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbx\nsub rsp, 38h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\ncall _strlen\nmov rdi, rsp\nmov rdx, rax\nmov esi, eax\ncdqe\nlea r10, ds:0[rax*4]\nimul rax, rax\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rdi, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rdi\njz short loc_12A4\nloc_128F:\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\ncmp rsp, rdi\njnz short loc_128F\nloc_12A4:\nand ecx, 0FFFh\nsub rsp, rcx\ntest rcx, rcx\njnz loc_1455\nloc_12B6:\nmov rdi, rsp\ntest edx, edx\njle loc_13BA\nshr r10, 2\nxor eax, eax\nlea r9, [r10+1]\nnop dword ptr [rax+rax+00h]\nloc_12D0:\nmovsxd rcx, eax\nmov ebx, eax\nadd eax, 1\nimul rcx, r9\nmov dword ptr [rdi+rcx*4], 1\ncmp esi, eax\njnz short loc_12D0\ncmp edx, 1\njz loc_13BA\nlea r13d, [rdx-2]\nmov [rbp+var_50], r12\nlea r14, [r12+2]\nmov r15, rdx\nmov [rbp+var_58], r13\nlea r8, [r13+3]\nmov r11d, 2\nxchg ax, ax\nloc_1310:\ncmp r11, 2\njz loc_13E8\nmov [rbp+var_48], r8\nmov rcx, [rbp+var_50]\nlea edx, [r11-2]\nxor eax, eax\njmp short loc_1365\nloc_1330:\nimul rax, r10\nmovsxd rdx, edx\nadd rdx, rax\nlea r13, [r8+rax]\nmovsxd rax, esi\nimul rax, r10\nmov edx, [rdi+rdx*4]\nadd rax, r8\nmov eax, [rdi+rax*4]\ncmp edx, eax\ncmovl edx, eax\nadd rcx, 1\nmov [rdi+r13*4], edx\ncmp esi, ebx\njz short loc_13A3\nloc_135F:\nmov edx, r12d\nmovsxd rax, esi\nloc_1365:\nmovzx r8d, byte ptr [rcx]\nlea r12d, [rdx+1]\ncmp [rcx+r11-1], r8b\nlea esi, [rax+1]\nmovsxd r8, r12d\njnz short loc_1330\nmovsxd r13, eax\nmovsxd rdx, edx\nadd rcx, 1\nimul r13, r10\nlea rax, [r8+r13]\nmovsxd r8, esi\nimul r8, r10\nadd rdx, r8\nmov edx, [rdi+rdx*4]\nadd edx, 2\nmov [rdi+rax*4], edx\ncmp esi, ebx\njnz short loc_135F\nloc_13A3:\nmov r8, [rbp+var_48]\nloc_13A7:\nadd r11, 1\nsub ebx, 1\ncmp r11, r8\njnz loc_1310\nmov rdx, r15\nloc_13BA:\nlea eax, [rdx-1]\ncdqe\nmov eax, [rdi+rax*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz loc_1460\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_13E8:\nmov r13, [rbp+var_58]\nmov r12, [rbp+var_50]\nxor eax, eax\njmp short loc_1424\nloc_13F8:\nmov rsi, rcx\nimul rcx, r9\nimul rsi, r10\nmov ecx, [rdi+rcx*4]\nadd rsi, rdx\nimul rdx, r9\nmov edx, [rdi+rdx*4]\ncmp edx, ecx\ncmovl edx, ecx\nmov [rdi+rsi*4], edx\nlea rdx, [rax+1]\ncmp rax, r13\njz short loc_13A7\nloc_1421:\nmov rax, rdx\nloc_1424:\nlea edx, [rax+1]\nmovzx esi, byte ptr [r14+rax-1]\nmovsxd rcx, eax\nmovsxd rdx, edx\ncmp [r12+rax], sil\njnz short loc_13F8\nimul rcx, r10\nadd rdx, rcx\nmov dword ptr [rdi+rdx*4], 2\nlea rdx, [rax+1]\ncmp rax, r13\njnz short loc_1421\njmp loc_13A7\nloc_1455:\nor [rsp+rcx+1060h+var_1068], 0\njmp loc_12B6\nloc_1460:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v2; // edx\n __int64 v3; // rcx\n __int64 *v4; // rdi\n __int16 v5; // cx\n signed __int64 v6; // rcx\n void *v7; // rsp\n unsigned __int64 v8; // r10\n int v9; // eax\n unsigned __int64 v10; // r9\n __int64 v11; // rcx\n int v12; // ebx\n const char *v13; // r14\n int v14; // r15d\n __int64 v15; // r8\n __int64 v16; // r11\n const char *v17; // rcx\n int v18; // edx\n __int64 i; // rax\n unsigned __int64 v20; // rax\n int v21; // edx\n int v22; // r12d\n int v23; // esi\n __int64 v25; // r13\n const char *v26; // r12\n __int64 j; // rax\n __int64 v28; // rsi\n int v29; // edx\n __int64 v30; // rdx\n __int64 v31; // rdx\n _DWORD v33[1022]; // [rsp+8h] [rbp-1060h] BYREF\n __int64 v34; // [rsp+1008h] [rbp-60h] BYREF\n __int64 v35; // [rsp+1010h] [rbp-58h]\n const char *v36; // [rsp+1018h] [rbp-50h]\n __int64 v37; // [rsp+1020h] [rbp-48h]\n unsigned __int64 v38; // [rsp+1030h] [rbp-38h]\n\n v38 = __readfsqword(0x28u);\n v2 = strlen(a1);\n v3 = 4 * v2 * (__int64)v2 + 15;\n v4 = (__int64 *)((char *)&v34 - (v3 & 0xFFFFFFFFFFFFF000LL));\n v5 = v3 & 0xFFF0;\n if ( &v34 != v4 )\n {\n while ( v33 != (_DWORD *)v4 )\n ;\n }\n v6 = v5 & 0xFFF;\n v7 = alloca(v6);\n if ( v6 )\n *(_QWORD *)((char *)&v33[-2] + v6) = *(_QWORD *)((char *)&v33[-2] + v6);\n if ( v2 > 0 )\n {\n v8 = (unsigned __int64)(4LL * v2) >> 2;\n v9 = 0;\n v10 = v8 + 1;\n do\n {\n v11 = v9;\n v12 = v9++;\n v33[v10 * v11] = 1;\n }\n while ( v2 != v9 );\n if ( v2 != 1 )\n {\n v36 = a1;\n v13 = a1 + 2;\n v14 = v2;\n v35 = (unsigned int)(v2 - 2);\n v15 = v35 + 3;\n v16 = 2LL;\n while ( 1 )\n {\n if ( v16 != 2 )\n {\n v37 = v15;\n v17 = v36;\n v18 = v16 - 2;\n for ( i = 0LL; ; i = v23 )\n {\n v22 = v18 + 1;\n v23 = i + 1;\n if ( v17[v16 - 1] == *v17 )\n {\n ++v17;\n v33[v22 + v8 * (int)i] = v33[v8 * v23 + v18] + 2;\n if ( v23 == v12 )\n goto LABEL_18;\n }\n else\n {\n v20 = v8 * i;\n v21 = v33[v20 + v18];\n if ( v21 < v33[v22 + v8 * v23] )\n v21 = v33[v22 + v8 * v23];\n ++v17;\n v33[v22 + v20] = v21;\n if ( v23 == v12 )\n {\nLABEL_18:\n v15 = v37;\n goto LABEL_19;\n }\n }\n v18 = v22;\n }\n }\n v25 = v35;\n v26 = v36;\n for ( j = 0LL; ; j = v30 )\n {\n v31 = (int)j + 1;\n if ( v26[j] != v13[j - 1] )\n break;\n v33[v8 * (int)j + v31] = 2;\n v30 = j + 1;\n if ( j == v25 )\n goto LABEL_19;\nLABEL_26:\n ;\n }\n v28 = v31 + v8 * (int)j;\n v29 = v33[v10 * v31];\n if ( v29 < v33[v10 * (int)j] )\n v29 = v33[v10 * (int)j];\n v33[v28] = v29;\n v30 = j + 1;\n if ( j != v25 )\n goto LABEL_26;\nLABEL_19:\n ++v16;\n --v12;\n if ( v16 == v15 )\n {\n v2 = v14;\n return (unsigned int)v33[v2 - 1];\n }\n }\n }\n }\n return (unsigned int)v33[v2 - 1];\n}", + "ida_strip_asm": "sub_1230:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbx\nsub rsp, 38h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\ncall _strlen\nmov rdi, rsp\nmov rdx, rax\nmov esi, eax\ncdqe\nlea r10, ds:0[rax*4]\nimul rax, rax\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rdi, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rdi\njz short loc_12A4\nloc_128F:\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\ncmp rsp, rdi\njnz short loc_128F\nloc_12A4:\nand ecx, 0FFFh\nsub rsp, rcx\ntest rcx, rcx\njnz loc_1455\nloc_12B6:\nmov rdi, rsp\ntest edx, edx\njle loc_13BA\nshr r10, 2\nxor eax, eax\nlea r9, [r10+1]\nnop dword ptr [rax+rax+00h]\nloc_12D0:\nmovsxd rcx, eax\nmov ebx, eax\nadd eax, 1\nimul rcx, r9\nmov dword ptr [rdi+rcx*4], 1\ncmp esi, eax\njnz short loc_12D0\ncmp edx, 1\njz loc_13BA\nlea r13d, [rdx-2]\nmov [rbp+var_50], r12\nlea r14, [r12+2]\nmov r15, rdx\nmov [rbp+var_58], r13\nlea r8, [r13+3]\nmov r11d, 2\nxchg ax, ax\nloc_1310:\ncmp r11, 2\njz loc_13E8\nmov [rbp+var_48], r8\nmov rcx, [rbp+var_50]\nlea edx, [r11-2]\nxor eax, eax\njmp short loc_1365\nloc_1330:\nimul rax, r10\nmovsxd rdx, edx\nadd rdx, rax\nlea r13, [r8+rax]\nmovsxd rax, esi\nimul rax, r10\nmov edx, [rdi+rdx*4]\nadd rax, r8\nmov eax, [rdi+rax*4]\ncmp edx, eax\ncmovl edx, eax\nadd rcx, 1\nmov [rdi+r13*4], edx\ncmp esi, ebx\njz short loc_13A3\nloc_135F:\nmov edx, r12d\nmovsxd rax, esi\nloc_1365:\nmovzx r8d, byte ptr [rcx]\nlea r12d, [rdx+1]\ncmp [rcx+r11-1], r8b\nlea esi, [rax+1]\nmovsxd r8, r12d\njnz short loc_1330\nmovsxd r13, eax\nmovsxd rdx, edx\nadd rcx, 1\nimul r13, r10\nlea rax, [r8+r13]\nmovsxd r8, esi\nimul r8, r10\nadd rdx, r8\nmov edx, [rdi+rdx*4]\nadd edx, 2\nmov [rdi+rax*4], edx\ncmp esi, ebx\njnz short loc_135F\nloc_13A3:\nmov r8, [rbp+var_48]\nloc_13A7:\nadd r11, 1\nsub ebx, 1\ncmp r11, r8\njnz loc_1310\nmov rdx, r15\nloc_13BA:\nlea eax, [rdx-1]\ncdqe\nmov eax, [rdi+rax*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz loc_1460\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_13E8:\nmov r13, [rbp+var_58]\nmov r12, [rbp+var_50]\nxor eax, eax\njmp short loc_1424\nloc_13F8:\nmov rsi, rcx\nimul rcx, r9\nimul rsi, r10\nmov ecx, [rdi+rcx*4]\nadd rsi, rdx\nimul rdx, r9\nmov edx, [rdi+rdx*4]\ncmp edx, ecx\ncmovl edx, ecx\nmov [rdi+rsi*4], edx\nlea rdx, [rax+1]\ncmp rax, r13\njz short loc_13A7\nloc_1421:\nmov rax, rdx\nloc_1424:\nlea edx, [rax+1]\nmovzx esi, byte ptr [r14+rax-1]\nmovsxd rcx, eax\nmovsxd rdx, edx\ncmp [r12+rax], sil\njnz short loc_13F8\nimul rcx, r10\nadd rdx, rcx\nmov dword ptr [rdi+rdx*4], 2\nlea rdx, [rax+1]\ncmp rax, r13\njnz short loc_1421\njmp loc_13A7\nloc_1455:\nor [rsp+rcx+1060h+var_1068], 0\njmp loc_12B6\nloc_1460:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1230(const char *a1)\n{\n int v2; // edx\n __int64 v3; // rcx\n __int64 *v4; // rdi\n __int16 v5; // cx\n signed __int64 v6; // rcx\n void *v7; // rsp\n unsigned __int64 v8; // r10\n int v9; // eax\n unsigned __int64 v10; // r9\n __int64 v11; // rcx\n int v12; // ebx\n const char *v13; // r14\n int v14; // r15d\n __int64 v15; // r8\n __int64 v16; // r11\n const char *v17; // rcx\n int v18; // edx\n __int64 i; // rax\n unsigned __int64 v20; // rax\n int v21; // edx\n int v22; // r12d\n int v23; // esi\n __int64 v25; // r13\n const char *v26; // r12\n __int64 j; // rax\n __int64 v28; // rsi\n int v29; // edx\n __int64 v30; // rdx\n __int64 v31; // rdx\n _DWORD v33[1022]; // [rsp+8h] [rbp-1060h] BYREF\n __int64 v34; // [rsp+1008h] [rbp-60h] BYREF\n __int64 v35; // [rsp+1010h] [rbp-58h]\n const char *v36; // [rsp+1018h] [rbp-50h]\n __int64 v37; // [rsp+1020h] [rbp-48h]\n unsigned __int64 v38; // [rsp+1030h] [rbp-38h]\n\n v38 = __readfsqword(0x28u);\n v2 = strlen(a1);\n v3 = 4 * v2 * (__int64)v2 + 15;\n v4 = (__int64 *)((char *)&v34 - (v3 & 0xFFFFFFFFFFFFF000LL));\n v5 = v3 & 0xFFF0;\n if ( &v34 != v4 )\n {\n while ( v33 != (_DWORD *)v4 )\n ;\n }\n v6 = v5 & 0xFFF;\n v7 = alloca(v6);\n if ( v6 )\n *(_QWORD *)((char *)&v33[-2] + v6) = *(_QWORD *)((char *)&v33[-2] + v6);\n if ( v2 > 0 )\n {\n v8 = (unsigned __int64)(4LL * v2) >> 2;\n v9 = 0;\n v10 = v8 + 1;\n do\n {\n v11 = v9;\n v12 = v9++;\n v33[v10 * v11] = 1;\n }\n while ( v2 != v9 );\n if ( v2 != 1 )\n {\n v36 = a1;\n v13 = a1 + 2;\n v14 = v2;\n v35 = (unsigned int)(v2 - 2);\n v15 = v35 + 3;\n v16 = 2LL;\n while ( 1 )\n {\n if ( v16 != 2 )\n {\n v37 = v15;\n v17 = v36;\n v18 = v16 - 2;\n for ( i = 0LL; ; i = v23 )\n {\n v22 = v18 + 1;\n v23 = i + 1;\n if ( v17[v16 - 1] == *v17 )\n {\n ++v17;\n v33[v22 + v8 * (int)i] = v33[v8 * v23 + v18] + 2;\n if ( v23 == v12 )\n goto LABEL_18;\n }\n else\n {\n v20 = v8 * i;\n v21 = v33[v20 + v18];\n if ( v21 < v33[v22 + v8 * v23] )\n v21 = v33[v22 + v8 * v23];\n ++v17;\n v33[v22 + v20] = v21;\n if ( v23 == v12 )\n {\nLABEL_18:\n v15 = v37;\n goto LABEL_19;\n }\n }\n v18 = v22;\n }\n }\n v25 = v35;\n v26 = v36;\n for ( j = 0LL; ; j = v30 )\n {\n v31 = (int)j + 1;\n if ( v26[j] != v13[j - 1] )\n break;\n v33[v8 * (int)j + v31] = 2;\n v30 = j + 1;\n if ( j == v25 )\n goto LABEL_19;\nLABEL_26:\n ;\n }\n v28 = v31 + v8 * (int)j;\n v29 = v33[v10 * v31];\n if ( v29 < v33[v10 * (int)j] )\n v29 = v33[v10 * (int)j];\n v33[v28] = v29;\n v30 = j + 1;\n if ( j != v25 )\n goto LABEL_26;\nLABEL_19:\n ++v16;\n --v12;\n if ( v16 == v15 )\n {\n v2 = v14;\n return (unsigned int)v33[v2 - 1];\n }\n }\n }\n }\n return (unsigned int)v33[v2 - 1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1230(const char *a1) {\n int v2;\n long long v3;\n long long *v4;\n short v5;\n signed long long v6;\n void *v7;\n unsigned long long v8;\n int v9;\n unsigned long long v10;\n long long v11;\n int v12;\n const char *v13;\n int v14;\n long long v15;\n long long v16;\n const char *v17;\n int v18;\n long long i;\n unsigned long long v20;\n int v21;\n int v22;\n int v23;\n long long v25;\n const char *v26;\n long long j;\n long long v28;\n int v29;\n long long v30;\n long long v31;\n uint32_t v33[1022];\n long long v34;\n long long v35;\n const char *v36;\n long long v37;\n unsigned long long v38;\n v38 = __readfsqword(40u);\n v2 = strlen(a1);\n v3 = 4 * v2 * (long long)v2 + 15;\n v4 = (long long *)((char *)&v34 - (v3 & 18446744073709547520LL));\n v5 = v3 & 65520;\n if (&v34 != v4) {\n while (v33 != (uint32_t *)v4)\n ;\n }\n v6 = v5 & 4095;\n v7 = alloca(v6);\n if (v6)\n *(uint64_t *)((char *)&v33[-2] + v6) = *(uint64_t *)((char *)&v33[-2] + v6);\n if (v2 > 0) {\n v8 = (unsigned long long)(4LL * v2) >> 2;\n v9 = 0;\n v10 = v8 + 1;\n do {\n v11 = v9;\n v12 = v9++;\n v33[v10 * v11] = 1;\n } while (v2 != v9);\n if (v2 != 1) {\n v36 = a1;\n v13 = a1 + 2;\n v14 = v2;\n v35 = (unsigned int)(v2 - 2);\n v15 = v35 + 3;\n v16 = 2LL;\n while (1) {\n if (v16 != 2) {\n v37 = v15;\n v17 = v36;\n v18 = v16 - 2;\n for (i = 0LL;; i = v23) {\n v22 = v18 + 1;\n v23 = i + 1;\n if (v17[v16 - 1] == *v17) {\n ++v17;\n v33[v22 + v8 * (int)i] = v33[v8 * v23 + v18] + 2;\n if (v23 == v12) goto LABEL_18;\n } else {\n v20 = v8 * i;\n v21 = v33[v20 + v18];\n if (v21 < v33[v22 + v8 * v23]) v21 = v33[v22 + v8 * v23];\n ++v17;\n v33[v22 + v20] = v21;\n if (v23 == v12) {\n LABEL_18:\n v15 = v37;\n goto LABEL_19;\n }\n }\n v18 = v22;\n }\n }\n v25 = v35;\n v26 = v36;\n for (j = 0LL;; j = v30) {\n v31 = (int)j + 1;\n if (v26[j] != v13[j - 1]) break;\n v33[v8 * (int)j + v31] = 2;\n v30 = j + 1;\n if (j == v25) goto LABEL_19;\n LABEL_26:;\n }\n v28 = v31 + v8 * (int)j;\n v29 = v33[v10 * v31];\n if (v29 < v33[v10 * (int)j]) v29 = v33[v10 * (int)j];\n v33[v28] = v29;\n v30 = j + 1;\n if (j != v25) goto LABEL_26;\n LABEL_19:\n ++v16;\n --v12;\n if (v16 == v15) {\n v2 = v14;\n return (unsigned int)v33[v2 - 1];\n }\n }\n }\n }\n return (unsigned int)v33[v2 - 1];\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v2;\n long long v3;\n long long *v4;\n short v5;\n signed long long v6;\n void *v7;\n unsigned long long v8;\n int v9;\n unsigned long long v10;\n long long v11;\n int v12;\n const char *v13;\n int v14;\n long long v15;\n long long v16;\n const char *v17;\n int v18;\n long long i;\n unsigned long long v20;\n int v21;\n int v22;\n int v23;\n long long v25;\n const char *v26;\n long long j;\n long long v28;\n int v29;\n long long v30;\n long long v31;\n uint32_t v33[1022];\n long long v34;\n long long v35;\n const char *v36;\n long long v37;\n unsigned long long v38;\n v38 = __readfsqword(40u);\n v2 = strlen(a1);\n v3 = 4 * v2 * (long long)v2 + 15;\n v4 = (long long *)((char *)&v34 - (v3 & 18446744073709547520LL));\n v5 = v3 & 65520;\n if (&v34 != v4) {\n while (v33 != (uint32_t *)v4)\n ;\n }\n v6 = v5 & 4095;\n v7 = alloca(v6);\n if (v6)\n *(uint64_t *)((char *)&v33[-2] + v6) = *(uint64_t *)((char *)&v33[-2] + v6);\n if (v2 > 0) {\n v8 = (unsigned long long)(4LL * v2) >> 2;\n v9 = 0;\n v10 = v8 + 1;\n do {\n v11 = v9;\n v12 = v9++;\n v33[v10 * v11] = 1;\n } while (v2 != v9);\n if (v2 != 1) {\n v36 = a1;\n v13 = a1 + 2;\n v14 = v2;\n v35 = (unsigned int)(v2 - 2);\n v15 = v35 + 3;\n v16 = 2LL;\n while (1) {\n if (v16 != 2) {\n v37 = v15;\n v17 = v36;\n v18 = v16 - 2;\n for (i = 0LL;; i = v23) {\n v22 = v18 + 1;\n v23 = i + 1;\n if (v17[v16 - 1] == *v17) {\n ++v17;\n v33[v22 + v8 * (int)i] = v33[v8 * v23 + v18] + 2;\n if (v23 == v12) goto LABEL_18;\n } else {\n v20 = v8 * i;\n v21 = v33[v20 + v18];\n if (v21 < v33[v22 + v8 * v23]) v21 = v33[v22 + v8 * v23];\n ++v17;\n v33[v22 + v20] = v21;\n if (v23 == v12) {\n LABEL_18:\n v15 = v37;\n goto LABEL_19;\n }\n }\n v18 = v22;\n }\n }\n v25 = v35;\n v26 = v36;\n for (j = 0LL;; j = v30) {\n v31 = (int)j + 1;\n if (v26[j] != v13[j - 1]) break;\n v33[v8 * (int)j + v31] = 2;\n v30 = j + 1;\n if (j == v25) goto LABEL_19;\n LABEL_26:;\n }\n v28 = v31 + v8 * (int)j;\n v29 = v33[v10 * v31];\n if (v29 < v33[v10 * (int)j]) v29 = v33[v10 * (int)j];\n v33[v28] = v29;\n v30 = j + 1;\n if (j != v25) goto LABEL_26;\n LABEL_19:\n ++v16;\n --v12;\n if (v16 == v15) {\n v2 = v14;\n return (unsigned int)v33[v2 - 1];\n }\n }\n }\n }\n return (unsigned int)v33[v2 - 1];\n}" + }, + { + "index": 248, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "double func0(int n) {\n if (n < 2) {\n return 1;\n } else {\n return 1.0 / n + func0(n - 1);\n }\n}", + "test": "int main() {\n\n assert(func0(7) - 2.5928571428571425 < 0.000001);\n\n assert(func0(4) - 2.083333333333333 < 0.000001);\n\n assert(func0(19) - 3.547739657143682 < 0.000001);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %edi,-0x4(%rbp)\ncmpl $0x1,-0x4(%rbp)\njg 1168 \nmovsd 0xf6a(%rip),%xmm0\njmp 1190 \ncvtsi2sdl -0x4(%rbp),%xmm1\nmovsd 0xf5b(%rip),%xmm0\ndivsd %xmm1,%xmm0\nmovsd %xmm0,-0x10(%rbp)\nmov -0x4(%rbp),%eax\nsub $0x1,%eax\nmov %eax,%edi\ncallq 1149 \naddsd -0x10(%rbp),%xmm0\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+var_4], edi\ncmp [rbp+var_4], 1\njg short loc_1168\nmovsd xmm0, cs:qword_20B0\njmp short locret_1194\nloc_1168:\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_4]\nmovsd xmm0, cs:qword_20B0\ndivsd xmm0, xmm1\nmovsd [rbp+var_10], xmm0\nmov eax, [rbp+var_4]\nsub eax, 1\nmov edi, eax\ncall func0\naddsd xmm0, [rbp+var_10]\nlocret_1194:\nleave\nretn", + "ida_pseudo": "double __fastcall func0(int a1)\n{\n if ( a1 > 1 )\n return func0((unsigned int)(a1 - 1)) + 1.0 / (double)a1;\n else\n return 1.0;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+var_4], edi\ncmp [rbp+var_4], 1\njg short loc_1168\nmovsd xmm0, cs:qword_20B0\njmp short locret_1194\nloc_1168:\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_4]\nmovsd xmm0, cs:qword_20B0\ndivsd xmm0, xmm1\nmovsd [rbp+var_10], xmm0\nmov eax, [rbp+var_4]\nsub eax, 1\nmov edi, eax\ncall sub_1149\naddsd xmm0, [rbp+var_10]\nlocret_1194:\nleave\nretn", + "ida_strip_pseudo": "double __fastcall sub_1149(int a1)\n{\n if ( a1 > 1 )\n return sub_1149((unsigned int)(a1 - 1)) + 1.0 / (double)a1;\n else\n return 1.0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1149(int a1) {\n if (a1 > 1)\n return sub_1149((unsigned int)(a1 - 1)) + 1.0 / (double)a1;\n else\n return 1.0;\n}", + "ida_pseudo_norm": "double func0(int a1) {\n if (a1 > 1)\n return func0((unsigned int)(a1 - 1)) + 1.0 / (double)a1;\n else\n return 1.0;\n}" + }, + { + "index": 248, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "double func0(int n) {\n if (n < 2) {\n return 1;\n } else {\n return 1.0 / n + func0(n - 1);\n }\n}", + "test": "int main() {\n\n assert(func0(7) - 2.5928571428571425 < 0.000001);\n\n assert(func0(4) - 2.083333333333333 < 0.000001);\n\n assert(func0(19) - 3.547739657143682 < 0.000001);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmovsd 0xf7b(%rip),%xmm0\ncmp $0x1,%edi\njg 115b \nretq\npush %rbx\nmov %edi,%ebx\nlea -0x1(%rdi),%edi\ncallq 1149 \nmovapd %xmm0,%xmm2\npxor %xmm1,%xmm1\ncvtsi2sd %ebx,%xmm1\nmovsd 0xf56(%rip),%xmm0\ndivsd %xmm1,%xmm0\naddsd %xmm2,%xmm0\npop %rbx\nretq\n", + "ida_asm": "func0:\nendbr64\nmovsd xmm0, cs:qword_20B0\ncmp edi, 1\njg short loc_115B\nretn\nloc_115B:\nsub rsp, 18h\npxor xmm0, xmm0\ncvtsi2sd xmm0, edi\nmovsd xmm1, cs:qword_20B0\ndivsd xmm1, xmm0\nmovsd [rsp+18h+var_10], xmm1\nsub edi, 1\ncall func0\naddsd xmm0, [rsp+18h+var_10]\nadd rsp, 18h\nretn", + "ida_pseudo": "double __fastcall func0(int a1)\n{\n double result; // xmm0_8\n\n result = 1.0;\n if ( a1 > 1 )\n return func0((unsigned int)(a1 - 1)) + 1.0 / (double)a1;\n return result;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmovsd xmm0, cs:qword_20B0\ncmp edi, 1\njg short loc_115B\nretn\nloc_115B:\nsub rsp, 18h\npxor xmm0, xmm0\ncvtsi2sd xmm0, edi\nmovsd xmm1, cs:qword_20B0\ndivsd xmm1, xmm0\nmovsd [rsp+18h+var_10], xmm1\nsub edi, 1\ncall sub_1149\naddsd xmm0, [rsp+18h+var_10]\nadd rsp, 18h\nretn", + "ida_strip_pseudo": "double __fastcall sub_1149(int a1)\n{\n double result; // xmm0_8\n\n result = 1.0;\n if ( a1 > 1 )\n return sub_1149((unsigned int)(a1 - 1)) + 1.0 / (double)a1;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1149(int a1) {\n double result;\n result = 1.0;\n if (a1 > 1) return sub_1149((unsigned int)(a1 - 1)) + 1.0 / (double)a1;\n return result;\n}", + "ida_pseudo_norm": "double func0(int a1) {\n double result;\n result = 1.0;\n if (a1 > 1) return func0((unsigned int)(a1 - 1)) + 1.0 / (double)a1;\n return result;\n}" + }, + { + "index": 248, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "double func0(int n) {\n if (n < 2) {\n return 1;\n } else {\n return 1.0 / n + func0(n - 1);\n }\n}", + "test": "int main() {\n\n assert(func0(7) - 2.5928571428571425 < 0.000001);\n\n assert(func0(4) - 2.083333333333333 < 0.000001);\n\n assert(func0(19) - 3.547739657143682 < 0.000001);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%edi\njg 1258 \nmovsd 0xe7f(%rip),%xmm0\nretq\nnopw 0x0(%rax,%rax,1)\njmp 1260 \nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmovsd xmm0, cs:qword_20B0\ncmp edi, 1\njg short loc_1248\nretn\nloc_1248:\npxor xmm1, xmm1\nmovapd xmm2, xmm0\nlea eax, [rdi-1]\ncvtsi2sd xmm1, edi\ndivsd xmm2, xmm1\nmovapd xmm1, xmm0\ncmp edi, 2\njnz short loc_1270\naddsd xmm2, xmm1\nmovapd xmm0, xmm2\nretn\nloc_1270:\npxor xmm3, xmm3\ncvtsi2sd xmm3, eax\nlea eax, [rdi-2]\ndivsd xmm1, xmm3\ncmp edi, 3\njnz short loc_1298\naddsd xmm1, xmm0\naddsd xmm2, xmm1\nmovapd xmm0, xmm2\nretn\nloc_1298:\npxor xmm3, xmm3\nsub rsp, 28h\nsub edi, 3\ncvtsi2sd xmm3, eax\nmovsd [rsp+28h+var_10], xmm1\nmovsd [rsp+28h+var_18], xmm2\ndivsd xmm0, xmm3\nmovsd [rsp+28h+var_20], xmm0\ncall func0\naddsd xmm0, [rsp+28h+var_20]\nmovsd xmm1, [rsp+28h+var_10]\nmovsd xmm2, [rsp+28h+var_18]\nadd rsp, 28h\naddsd xmm1, xmm0\naddsd xmm2, xmm1\nmovapd xmm0, xmm2\nretn", + "ida_pseudo": "__int128 __usercall func0@(int a1@)\n{\n __int128 result; // xmm0\n __int128 v2; // xmm2\n int v3; // eax\n double v4; // xmm1_8\n\n result = 0x3FF0000000000000uLL;\n if ( a1 > 1 )\n {\n *((_QWORD *)&v2 + 1) = 0LL;\n *(double *)&v2 = 1.0 / (double)a1;\n if ( a1 == 2 )\n {\n *(double *)&v2 = *(double *)&v2 + 1.0;\n return v2;\n }\n else\n {\n v4 = 1.0 / (double)(a1 - 1);\n if ( a1 == 3 )\n {\n *(double *)&v2 = *(double *)&v2 + v4 + 1.0;\n }\n else\n {\n v2 = (unsigned __int64)v2;\n v3 = a1 - 2;\n *(double *)&v2 = *(double *)&v2 + v4 + func0((unsigned int)(a1 - 3)) + 1.0 / (double)v3;\n }\n return v2;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1230:\nendbr64\nmovsd xmm0, cs:qword_20B0\ncmp edi, 1\njg short loc_1248\nretn\nloc_1248:\npxor xmm1, xmm1\nmovapd xmm2, xmm0\nlea eax, [rdi-1]\ncvtsi2sd xmm1, edi\ndivsd xmm2, xmm1\nmovapd xmm1, xmm0\ncmp edi, 2\njnz short loc_1270\naddsd xmm2, xmm1\nmovapd xmm0, xmm2\nretn\nloc_1270:\npxor xmm3, xmm3\ncvtsi2sd xmm3, eax\nlea eax, [rdi-2]\ndivsd xmm1, xmm3\ncmp edi, 3\njnz short loc_1298\naddsd xmm1, xmm0\naddsd xmm2, xmm1\nmovapd xmm0, xmm2\nretn\nloc_1298:\npxor xmm3, xmm3\nsub rsp, 28h\nsub edi, 3\ncvtsi2sd xmm3, eax\nmovsd [rsp+28h+var_10], xmm1\nmovsd [rsp+28h+var_18], xmm2\ndivsd xmm0, xmm3\nmovsd [rsp+28h+var_20], xmm0\ncall sub_1230\naddsd xmm0, [rsp+28h+var_20]\nmovsd xmm1, [rsp+28h+var_10]\nmovsd xmm2, [rsp+28h+var_18]\nadd rsp, 28h\naddsd xmm1, xmm0\naddsd xmm2, xmm1\nmovapd xmm0, xmm2\nretn", + "ida_strip_pseudo": "__int128 __usercall sub_1230@(int a1@)\n{\n __int128 result; // xmm0\n __int128 v2; // xmm2\n int v3; // eax\n double v4; // xmm1_8\n\n result = 0x3FF0000000000000uLL;\n if ( a1 > 1 )\n {\n *((_QWORD *)&v2 + 1) = 0LL;\n *(double *)&v2 = 1.0 / (double)a1;\n if ( a1 == 2 )\n {\n *(double *)&v2 = *(double *)&v2 + 1.0;\n return v2;\n }\n else\n {\n v4 = 1.0 / (double)(a1 - 1);\n if ( a1 == 3 )\n {\n *(double *)&v2 = *(double *)&v2 + v4 + 1.0;\n }\n else\n {\n v2 = (unsigned __int64)v2;\n v3 = a1 - 2;\n *(double *)&v2 = *(double *)&v2 + v4 + sub_1230((unsigned int)(a1 - 3)) + 1.0 / (double)v3;\n }\n return v2;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__int128 __usercall sub_1230 @(int a1 @) {\n __int128 result;\n __int128 v2;\n int v3;\n double v4;\n result = 4607182418800017408uLL;\n if (a1 > 1) {\n *((uint64_t *)&v2 + 1) = 0LL;\n *(double *)&v2 = 1.0 / (double)a1;\n if (a1 == 2) {\n *(double *)&v2 = *(double *)&v2 + 1.0;\n return v2;\n } else {\n v4 = 1.0 / (double)(a1 - 1);\n if (a1 == 3) {\n *(double *)&v2 = *(double *)&v2 + v4 + 1.0;\n } else {\n v2 = (unsigned long long)v2;\n v3 = a1 - 2;\n *(double *)&v2 = *(double *)&v2 + v4 +\n sub_1230((unsigned int)(a1 - 3)) + 1.0 / (double)v3;\n }\n return v2;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "__int128 __usercall func0 @(int a1 @) {\n __int128 result;\n __int128 v2;\n int v3;\n double v4;\n result = 4607182418800017408uLL;\n if (a1 > 1) {\n *((uint64_t *)&v2 + 1) = 0LL;\n *(double *)&v2 = 1.0 / (double)a1;\n if (a1 == 2) {\n *(double *)&v2 = *(double *)&v2 + 1.0;\n return v2;\n } else {\n v4 = 1.0 / (double)(a1 - 1);\n if (a1 == 3) {\n *(double *)&v2 = *(double *)&v2 + v4 + 1.0;\n } else {\n v2 = (unsigned long long)v2;\n v3 = a1 - 2;\n *(double *)&v2 = *(double *)&v2 + v4 + func0((unsigned int)(a1 - 3)) +\n 1.0 / (double)v3;\n }\n return v2;\n }\n }\n return result;\n}" + }, + { + "index": 248, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "double func0(int n) {\n if (n < 2) {\n return 1;\n } else {\n return 1.0 / n + func0(n - 1);\n }\n}", + "test": "int main() {\n\n assert(func0(7) - 2.5928571428571425 < 0.000001);\n\n assert(func0(4) - 2.083333333333333 < 0.000001);\n\n assert(func0(19) - 3.547739657143682 < 0.000001);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nmovsd 0xe94(%rip),%xmm1\ncmp $0x1,%edi\njg 1250 \nmovapd %xmm1,%xmm0\nretq\nnopw %cs:0x0(%rax,%rax,1)\npush %rbx\nmov %edi,%ebx\nlea -0x1(%rdi),%edi\nsub $0x10,%rsp\nmovsd %xmm1,0x8(%rsp)\ncallq 1230 \nmovsd 0x8(%rsp),%xmm1\nadd $0x10,%rsp\nmovapd %xmm0,%xmm2\npxor %xmm0,%xmm0\ncvtsi2sd %ebx,%xmm0\npop %rbx\ndivsd %xmm0,%xmm1\naddsd %xmm2,%xmm1\nmovapd %xmm1,%xmm0\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\nmovsd xmm0, cs:qword_20B0\ncmp edi, 1\njg short loc_1248\nretn\nloc_1248:\npxor xmm1, xmm1\nmovapd xmm2, xmm0\nlea eax, [rdi-1]\ncvtsi2sd xmm1, edi\ndivsd xmm2, xmm1\nmovapd xmm1, xmm0\ncmp edi, 2\njnz short loc_1270\naddsd xmm2, xmm1\nmovapd xmm0, xmm2\nretn\nloc_1270:\npxor xmm3, xmm3\ncvtsi2sd xmm3, eax\nlea eax, [rdi-2]\ndivsd xmm1, xmm3\ncmp edi, 3\njnz short loc_1298\naddsd xmm1, xmm0\naddsd xmm2, xmm1\nmovapd xmm0, xmm2\nretn\nloc_1298:\npxor xmm3, xmm3\nsub rsp, 28h\nsub edi, 3\ncvtsi2sd xmm3, eax\nmovsd [rsp+28h+var_10], xmm1\nmovsd [rsp+28h+var_18], xmm2\ndivsd xmm0, xmm3\nmovsd [rsp+28h+var_20], xmm0\ncall func0\naddsd xmm0, [rsp+28h+var_20]\nmovsd xmm1, [rsp+28h+var_10]\nmovsd xmm2, [rsp+28h+var_18]\nadd rsp, 28h\naddsd xmm1, xmm0\naddsd xmm2, xmm1\nmovapd xmm0, xmm2\nretn", + "ida_pseudo": "__int128 __usercall func0@(int a1@)\n{\n __int128 result; // xmm0\n __int128 v2; // xmm2\n int v3; // eax\n double v4; // xmm1_8\n\n result = 0x3FF0000000000000uLL;\n if ( a1 > 1 )\n {\n *((_QWORD *)&v2 + 1) = 0LL;\n *(double *)&v2 = 1.0 / (double)a1;\n if ( a1 == 2 )\n {\n *(double *)&v2 = *(double *)&v2 + 1.0;\n return v2;\n }\n else\n {\n v4 = 1.0 / (double)(a1 - 1);\n if ( a1 == 3 )\n {\n *(double *)&v2 = *(double *)&v2 + v4 + 1.0;\n }\n else\n {\n v2 = (unsigned __int64)v2;\n v3 = a1 - 2;\n *(double *)&v2 = *(double *)&v2 + v4 + func0((unsigned int)(a1 - 3)) + 1.0 / (double)v3;\n }\n return v2;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1230:\nendbr64\nmovsd xmm0, cs:qword_20B0\ncmp edi, 1\njg short loc_1248\nretn\nloc_1248:\npxor xmm1, xmm1\nmovapd xmm2, xmm0\nlea eax, [rdi-1]\ncvtsi2sd xmm1, edi\ndivsd xmm2, xmm1\nmovapd xmm1, xmm0\ncmp edi, 2\njnz short loc_1270\naddsd xmm2, xmm1\nmovapd xmm0, xmm2\nretn\nloc_1270:\npxor xmm3, xmm3\ncvtsi2sd xmm3, eax\nlea eax, [rdi-2]\ndivsd xmm1, xmm3\ncmp edi, 3\njnz short loc_1298\naddsd xmm1, xmm0\naddsd xmm2, xmm1\nmovapd xmm0, xmm2\nretn\nloc_1298:\npxor xmm3, xmm3\nsub rsp, 28h\nsub edi, 3\ncvtsi2sd xmm3, eax\nmovsd [rsp+28h+var_10], xmm1\nmovsd [rsp+28h+var_18], xmm2\ndivsd xmm0, xmm3\nmovsd [rsp+28h+var_20], xmm0\ncall sub_1230\naddsd xmm0, [rsp+28h+var_20]\nmovsd xmm1, [rsp+28h+var_10]\nmovsd xmm2, [rsp+28h+var_18]\nadd rsp, 28h\naddsd xmm1, xmm0\naddsd xmm2, xmm1\nmovapd xmm0, xmm2\nretn", + "ida_strip_pseudo": "__int128 __usercall sub_1230@(int a1@)\n{\n __int128 result; // xmm0\n __int128 v2; // xmm2\n int v3; // eax\n double v4; // xmm1_8\n\n result = 0x3FF0000000000000uLL;\n if ( a1 > 1 )\n {\n *((_QWORD *)&v2 + 1) = 0LL;\n *(double *)&v2 = 1.0 / (double)a1;\n if ( a1 == 2 )\n {\n *(double *)&v2 = *(double *)&v2 + 1.0;\n return v2;\n }\n else\n {\n v4 = 1.0 / (double)(a1 - 1);\n if ( a1 == 3 )\n {\n *(double *)&v2 = *(double *)&v2 + v4 + 1.0;\n }\n else\n {\n v2 = (unsigned __int64)v2;\n v3 = a1 - 2;\n *(double *)&v2 = *(double *)&v2 + v4 + sub_1230((unsigned int)(a1 - 3)) + 1.0 / (double)v3;\n }\n return v2;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__int128 __usercall sub_1230 @(int a1 @) {\n __int128 result;\n __int128 v2;\n int v3;\n double v4;\n result = 4607182418800017408uLL;\n if (a1 > 1) {\n *((uint64_t *)&v2 + 1) = 0LL;\n *(double *)&v2 = 1.0 / (double)a1;\n if (a1 == 2) {\n *(double *)&v2 = *(double *)&v2 + 1.0;\n return v2;\n } else {\n v4 = 1.0 / (double)(a1 - 1);\n if (a1 == 3) {\n *(double *)&v2 = *(double *)&v2 + v4 + 1.0;\n } else {\n v2 = (unsigned long long)v2;\n v3 = a1 - 2;\n *(double *)&v2 = *(double *)&v2 + v4 +\n sub_1230((unsigned int)(a1 - 3)) + 1.0 / (double)v3;\n }\n return v2;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "__int128 __usercall func0 @(int a1 @) {\n __int128 result;\n __int128 v2;\n int v3;\n double v4;\n result = 4607182418800017408uLL;\n if (a1 > 1) {\n *((uint64_t *)&v2 + 1) = 0LL;\n *(double *)&v2 = 1.0 / (double)a1;\n if (a1 == 2) {\n *(double *)&v2 = *(double *)&v2 + 1.0;\n return v2;\n } else {\n v4 = 1.0 / (double)(a1 - 1);\n if (a1 == 3) {\n *(double *)&v2 = *(double *)&v2 + v4 + 1.0;\n } else {\n v2 = (unsigned long long)v2;\n v3 = a1 - 2;\n *(double *)&v2 = *(double *)&v2 + v4 + func0((unsigned int)(a1 - 3)) +\n 1.0 / (double)v3;\n }\n return v2;\n }\n }\n return result;\n}" + }, + { + "index": 249, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int *func0(int array_nums1[], int len1, int array_nums2[], int len2,\n int *result_len) {\n static int result[1000];\n int k = 0;\n for (int i = 0; i < len2; i++) {\n for (int j = 0; j < len1; j++) {\n if (array_nums2[i] == array_nums1[j]) {\n result[k++] = array_nums2[i];\n break;\n }\n }\n }\n *result_len = k;\n return result;\n}", + "test": "int main() {\n\n int result_len;\n\n int *result;\n\n \n\n int array1[] = {1, 2, 3, 5, 7, 8, 9, 10};\n\n int array2[] = {1, 2, 4, 8, 9};\n\n int expected1[] = {1, 2, 8, 9};\n\n result = func0(array1, 8, array2, 5, &result_len);\n\n assert(result_len == 4);\n\n for (int i = 0; i < result_len; i++) {\n\n assert(result[i] == expected1[i]);\n\n }\n\n \n\n int array3[] = {3, 5, 7, 9};\n\n int expected2[] = {3, 5, 7, 9};\n\n result = func0(array1, 8, array3, 4, &result_len);\n\n assert(result_len == 4);\n\n for (int i = 0; i < result_len; i++) {\n\n assert(result[i] == expected2[i]);\n\n }\n\n \n\n int array4[] = {10, 20, 30, 40};\n\n int expected3[] = {10};\n\n result = func0(array1, 8, array4, 4, &result_len);\n\n assert(result_len == 1);\n\n for (int i = 0; i < result_len; i++) {\n\n assert(result[i] == expected3[i]);\n\n }\n\n \n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %ecx,-0x20(%rbp)\nmov %r8,-0x30(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 1232 \nmovl $0x0,-0x4(%rbp)\njmp 1226 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 1222 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0xc(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0xc(%rbp)\nmov (%rcx),%edx\ncltq\nlea 0x0(,%rax,4),%rcx\nlea 0x2e23(%rip),%rax\nmov %edx,(%rcx,%rax,1)\njmp 122e \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11bc \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x20(%rbp),%eax\njl 11b3 \nmov -0x30(%rbp),%rax\nmov -0xc(%rbp),%edx\nmov %edx,(%rax)\nlea 0x2df2(%rip),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov [rbp+var_30], r8\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_1232\nloc_11B3:\nmov [rbp+var_4], 0\njmp short loc_1226\nloc_11BC:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_1222\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\nmov edx, [rcx]\ncdqe\nlea rcx, ds:0[rax*4]\nlea rax, result_1\nmov [rcx+rax], edx\njmp short loc_122E\nloc_1222:\nadd [rbp+var_4], 1\nloc_1226:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11BC\nloc_122E:\nadd [rbp+var_8], 1\nloc_1232:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_20]\njl loc_11B3\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_C]\nmov [rax], edx\nlea rax, result_1\npop rbp\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, __int64 a3, int a4, _DWORD *a5)\n{\n int v5; // eax\n int v7; // [rsp+24h] [rbp-Ch]\n int i; // [rsp+28h] [rbp-8h]\n int j; // [rsp+2Ch] [rbp-4h]\n\n v7 = 0;\n for ( i = 0; i < a4; ++i )\n {\n for ( j = 0; j < a2; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a3) == *(_DWORD *)(4LL * j + a1) )\n {\n v5 = v7++;\n result_1[v5] = *(_DWORD *)(4LL * i + a3);\n break;\n }\n }\n }\n *a5 = v7;\n return result_1;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov [rbp+var_30], r8\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_1232\nloc_11B3:\nmov [rbp+var_4], 0\njmp short loc_1226\nloc_11BC:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_1222\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\nmov edx, [rcx]\ncdqe\nlea rcx, ds:0[rax*4]\nlea rax, unk_4040\nmov [rcx+rax], edx\njmp short loc_122E\nloc_1222:\nadd [rbp+var_4], 1\nloc_1226:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11BC\nloc_122E:\nadd [rbp+var_8], 1\nloc_1232:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_20]\njl loc_11B3\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_C]\nmov [rax], edx\nlea rax, unk_4040\npop rbp\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1189(__int64 a1, int a2, __int64 a3, int a4, _DWORD *a5)\n{\n int v5; // eax\n int v7; // [rsp+24h] [rbp-Ch]\n int i; // [rsp+28h] [rbp-8h]\n int j; // [rsp+2Ch] [rbp-4h]\n\n v7 = 0;\n for ( i = 0; i < a4; ++i )\n {\n for ( j = 0; j < a2; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a3) == *(_DWORD *)(4LL * j + a1) )\n {\n v5 = v7++;\n dword_4040[v5] = *(_DWORD *)(4LL * i + a3);\n break;\n }\n }\n }\n *a5 = v7;\n return dword_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1189(long long a1, int a2, long long a3, int a4, uint32_t *a5) {\n int v5;\n int v7;\n int i;\n int j;\n v7 = 0;\n for (i = 0; i < a4; ++i) {\n for (j = 0; j < a2; ++j) {\n if (*(uint32_t *)(4LL * i + a3) == *(uint32_t *)(4LL * j + a1)) {\n v5 = v7++;\n dword_4040[v5] = *(uint32_t *)(4LL * i + a3);\n break;\n }\n }\n }\n *a5 = v7;\n return dword_4040;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, long long a3, int a4, uint32_t *a5) {\n int v5;\n int v7;\n int i;\n int j;\n v7 = 0;\n for (i = 0; i < a4; ++i) {\n for (j = 0; j < a2; ++j) {\n if (*(uint32_t *)(4LL * i + a3) == *(uint32_t *)(4LL * j + a1)) {\n v5 = v7++;\n result_1[v5] = *(uint32_t *)(4LL * i + a3);\n break;\n }\n }\n }\n *a5 = v7;\n return result_1;\n}" + }, + { + "index": 249, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int *func0(int array_nums1[], int len1, int array_nums2[], int len2,\n int *result_len) {\n static int result[1000];\n int k = 0;\n for (int i = 0; i < len2; i++) {\n for (int j = 0; j < len1; j++) {\n if (array_nums2[i] == array_nums1[j]) {\n result[k++] = array_nums2[i];\n break;\n }\n }\n }\n *result_len = k;\n return result;\n}", + "test": "int main() {\n\n int result_len;\n\n int *result;\n\n \n\n int array1[] = {1, 2, 3, 5, 7, 8, 9, 10};\n\n int array2[] = {1, 2, 4, 8, 9};\n\n int expected1[] = {1, 2, 8, 9};\n\n result = func0(array1, 8, array2, 5, &result_len);\n\n assert(result_len == 4);\n\n for (int i = 0; i < result_len; i++) {\n\n assert(result[i] == expected1[i]);\n\n }\n\n \n\n int array3[] = {3, 5, 7, 9};\n\n int expected2[] = {3, 5, 7, 9};\n\n result = func0(array1, 8, array3, 4, &result_len);\n\n assert(result_len == 4);\n\n for (int i = 0; i < result_len; i++) {\n\n assert(result[i] == expected2[i]);\n\n }\n\n \n\n int array4[] = {10, 20, 30, 40};\n\n int expected3[] = {10};\n\n result = func0(array1, 8, array4, 4, &result_len);\n\n assert(result_len == 1);\n\n for (int i = 0; i < result_len; i++) {\n\n assert(result[i] == expected3[i]);\n\n }\n\n \n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %r8,%rbx\ntest %ecx,%ecx\njle 11e5 \nmov %rdx,%r9\nlea -0x1(%rcx),%eax\nlea 0x4(%rdx,%rax,4),%r10\nmov %rdi,%r11\nlea -0x1(%rsi),%eax\nlea 0x4(%rdi,%rax,4),%rcx\nmov $0x0,%edi\nlea 0x2e89(%rip),%r8\njmp 11cc \nmovslq %edi,%rax\nmov %edx,(%r8,%rax,4)\nlea 0x1(%rdi),%edi\nadd $0x4,%r9\ncmp %r10,%r9\nje 11ea \ntest %esi,%esi\njle 11c3 \nmov (%r9),%edx\nmov %r11,%rax\ncmp (%rax),%edx\nje 11b9 \nadd $0x4,%rax\ncmp %rcx,%rax\njne 11d6 \njmp 11c3 \nmov $0x0,%edi\nmov %edi,(%rbx)\nlea 0x2e4d(%rip),%rax\npop %rbx\nretq\n", + "ida_asm": "func0:\nendbr64\ntest ecx, ecx\njle short loc_11E2\npush rbx\nmov r10, rdi\nmov r9d, esi\nmov rsi, rdx\nmovsxd rcx, ecx\nlea r11, [rdx+rcx*4]\nmovsxd rax, r9d\nlea rcx, [rdi+rax*4]\nmov edi, 0\nlea rbx, result_1\njmp short loc_11C9\nloc_11B7:\nmovsxd rax, edi\nmov [rbx+rax*4], edx\nlea edi, [rdi+1]\nloc_11C0:\nadd rsi, 4\ncmp rsi, r11\njz short loc_11F2\nloc_11C9:\ntest r9d, r9d\njle short loc_11C0\nmov edx, [rsi]\nmov rax, r10\nloc_11D3:\ncmp edx, [rax]\njz short loc_11B7\nadd rax, 4\ncmp rax, rcx\njnz short loc_11D3\njmp short loc_11C0\nloc_11E2:\nmov edi, 0\nmov [r8], edi\nlea rax, result_1\nretn\nloc_11F2:\nmov [r8], edi\nlea rax, result_1\npop rbx\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(_DWORD *a1, int a2, int *a3, int a4, _DWORD *a5)\n{\n int *v7; // rsi\n int *v8; // r11\n _DWORD *v9; // rcx\n int v10; // edi\n int v11; // edx\n _DWORD *v12; // rax\n\n if ( a4 <= 0 )\n {\n *a5 = 0;\n return result_1;\n }\n else\n {\n v7 = a3;\n v8 = &a3[a4];\n v9 = &a1[a2];\n v10 = 0;\n do\n {\n if ( a2 > 0 )\n {\n v11 = *v7;\n v12 = a1;\n while ( v11 != *v12 )\n {\n if ( ++v12 == v9 )\n goto LABEL_4;\n }\n result_1[v10++] = v11;\n }\nLABEL_4:\n ++v7;\n }\n while ( v7 != v8 );\n *a5 = v10;\n return result_1;\n }\n}", + "ida_strip_asm": "sub_1189:\nendbr64\ntest ecx, ecx\njle short loc_11E2\npush rbx\nmov r10, rdi\nmov r9d, esi\nmov rsi, rdx\nmovsxd rcx, ecx\nlea r11, [rdx+rcx*4]\nmovsxd rax, r9d\nlea rcx, [rdi+rax*4]\nmov edi, 0\nlea rbx, unk_4040\njmp short loc_11C9\nloc_11B7:\nmovsxd rax, edi\nmov [rbx+rax*4], edx\nlea edi, [rdi+1]\nloc_11C0:\nadd rsi, 4\ncmp rsi, r11\njz short loc_11F2\nloc_11C9:\ntest r9d, r9d\njle short loc_11C0\nmov edx, [rsi]\nmov rax, r10\nloc_11D3:\ncmp edx, [rax]\njz short loc_11B7\nadd rax, 4\ncmp rax, rcx\njnz short loc_11D3\njmp short loc_11C0\nloc_11E2:\nmov edi, 0\nmov [r8], edi\nlea rax, unk_4040\nretn\nloc_11F2:\nmov [r8], edi\nlea rax, unk_4040\npop rbx\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1189(_DWORD *a1, int a2, int *a3, int a4, _DWORD *a5)\n{\n int *v7; // rsi\n int *v8; // r11\n _DWORD *v9; // rcx\n int v10; // edi\n int v11; // edx\n _DWORD *v12; // rax\n\n if ( a4 <= 0 )\n {\n *a5 = 0;\n return dword_4040;\n }\n else\n {\n v7 = a3;\n v8 = &a3[a4];\n v9 = &a1[a2];\n v10 = 0;\n do\n {\n if ( a2 > 0 )\n {\n v11 = *v7;\n v12 = a1;\n while ( v11 != *v12 )\n {\n if ( ++v12 == v9 )\n goto LABEL_4;\n }\n dword_4040[v10++] = v11;\n }\nLABEL_4:\n ++v7;\n }\n while ( v7 != v8 );\n *a5 = v10;\n return dword_4040;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1189(uint32_t *a1, int a2, int *a3, int a4, uint32_t *a5) {\n int *v7;\n int *v8;\n uint32_t *v9;\n int v10;\n int v11;\n uint32_t *v12;\n if (a4 <= 0) {\n *a5 = 0;\n return dword_4040;\n } else {\n v7 = a3;\n v8 = &a3[a4];\n v9 = &a1[a2];\n v10 = 0;\n do {\n if (a2 > 0) {\n v11 = *v7;\n v12 = a1;\n while (v11 != *v12) {\n if (++v12 == v9) goto LABEL_4;\n }\n dword_4040[v10++] = v11;\n }\n LABEL_4:\n ++v7;\n } while (v7 != v8);\n *a5 = v10;\n return dword_4040;\n }\n}", + "ida_pseudo_norm": "uint32_t *func0(uint32_t *a1, int a2, int *a3, int a4, uint32_t *a5) {\n int *v7;\n int *v8;\n uint32_t *v9;\n int v10;\n int v11;\n uint32_t *v12;\n if (a4 <= 0) {\n *a5 = 0;\n return result_1;\n } else {\n v7 = a3;\n v8 = &a3[a4];\n v9 = &a1[a2];\n v10 = 0;\n do {\n if (a2 > 0) {\n v11 = *v7;\n v12 = a1;\n while (v11 != *v12) {\n if (++v12 == v9) goto LABEL_4;\n }\n result_1[v10++] = v11;\n }\n LABEL_4:\n ++v7;\n } while (v7 != v8);\n *a5 = v10;\n return result_1;\n }\n}" + }, + { + "index": 249, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int *func0(int array_nums1[], int len1, int array_nums2[], int len2,\n int *result_len) {\n static int result[1000];\n int k = 0;\n for (int i = 0; i < len2; i++) {\n for (int j = 0; j < len1; j++) {\n if (array_nums2[i] == array_nums1[j]) {\n result[k++] = array_nums2[i];\n break;\n }\n }\n }\n *result_len = k;\n return result;\n}", + "test": "int main() {\n\n int result_len;\n\n int *result;\n\n \n\n int array1[] = {1, 2, 3, 5, 7, 8, 9, 10};\n\n int array2[] = {1, 2, 4, 8, 9};\n\n int expected1[] = {1, 2, 8, 9};\n\n result = func0(array1, 8, array2, 5, &result_len);\n\n assert(result_len == 4);\n\n for (int i = 0; i < result_len; i++) {\n\n assert(result[i] == expected1[i]);\n\n }\n\n \n\n int array3[] = {3, 5, 7, 9};\n\n int expected2[] = {3, 5, 7, 9};\n\n result = func0(array1, 8, array3, 4, &result_len);\n\n assert(result_len == 4);\n\n for (int i = 0; i < result_len; i++) {\n\n assert(result[i] == expected2[i]);\n\n }\n\n \n\n int array4[] = {10, 20, 30, 40};\n\n int expected3[] = {10};\n\n result = func0(array1, 8, array4, 4, &result_len);\n\n assert(result_len == 1);\n\n for (int i = 0; i < result_len; i++) {\n\n assert(result[i] == expected3[i]);\n\n }\n\n \n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %r8,%rbx\ntest %ecx,%ecx\njle 154d \nlea -0x1(%rcx),%eax\nmov %rdx,%r9\nlea 0x2b47(%rip),%r8\nxor %r10d,%r10d\nlea 0x4(%rdx,%rax,4),%r11\nlea -0x1(%rsi),%eax\nlea 0x4(%rdi,%rax,4),%rcx\nnopl 0x0(%rax)\ntest %esi,%esi\njle 1538 \nmov (%r9),%edx\nmov %rdi,%rax\njmp 1529 \nnopl 0x0(%rax)\nadd $0x4,%rax\ncmp %rcx,%rax\nje 1538 \ncmp (%rax),%edx\njne 1520 \nmovslq %r10d,%rax\nadd $0x1,%r10d\nmov %edx,(%r8,%rax,4)\nadd $0x4,%r9\ncmp %r11,%r9\njne 1510 \nmov %r10d,(%rbx)\nlea 0x2af5(%rip),%rax\npop %rbx\nretq\nxor %r10d,%r10d\nlea 0x2ae9(%rip),%rax\nmov %r10d,(%rbx)\npop %rbx\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\nmov r9, rdi\ntest ecx, ecx\njle short loc_13CF\nmovsxd rcx, ecx\nlea r10, [rdx+rcx*4]\nloc_13C2:\ntest esi, esi\njg short loc_13DF\nadd rdx, 4\ncmp rdx, r10\njnz short loc_13C2\nloc_13CF:\nxor eax, eax\nlea r11, result_1\nloc_13D8:\nmov [r8], eax\nmov rax, r11\nretn\nloc_13DF:\nmovsxd rsi, esi\nxor edi, edi\nlea r11, result_1\nlea rsi, [r9+rsi*4]\nnop\nloc_13F0:\nmov ecx, [rdx]\nmov rax, r9\njmp short loc_1409\nloc_1400:\nadd rax, 4\ncmp rax, rsi\njz short loc_1428\nloc_1409:\ncmp ecx, [rax]\njnz short loc_1400\nadd rdx, 4\nmov [r11+rdi*4], ecx\nlea eax, [rdi+1]\ncmp rdx, r10\njz short loc_13D8\nmovsxd rdi, eax\njmp short loc_13F0\nloc_1428:\nadd rdx, 4\ncmp rdx, r10\njnz short loc_13F0\nmov eax, edi\nmov [r8], eax\nmov rax, r11\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(_DWORD *a1, int a2, int *a3, int a4, _DWORD *a5)\n{\n int *v6; // r10\n int v7; // eax\n __int64 v9; // rdi\n _DWORD *v10; // rsi\n int v11; // ecx\n _DWORD *v12; // rax\n\n if ( a4 <= 0 )\n {\nLABEL_5:\n v7 = 0;\nLABEL_6:\n *a5 = v7;\n return result_1;\n }\n else\n {\n v6 = &a3[a4];\n while ( a2 <= 0 )\n {\n if ( ++a3 == v6 )\n goto LABEL_5;\n }\n v9 = 0LL;\n v10 = &a1[a2];\n do\n {\nLABEL_8:\n v11 = *a3;\n v12 = a1;\n do\n {\n if ( v11 == *v12 )\n {\n ++a3;\n result_1[v9] = v11;\n v7 = v9 + 1;\n if ( a3 == v6 )\n goto LABEL_6;\n v9 = v7;\n goto LABEL_8;\n }\n ++v12;\n }\n while ( v12 != v10 );\n ++a3;\n }\n while ( a3 != v6 );\n *a5 = v9;\n return result_1;\n }\n}", + "ida_strip_asm": "sub_13B0:\nendbr64\nmov r9, rdi\ntest ecx, ecx\njle short loc_13CF\nmovsxd rcx, ecx\nlea r10, [rdx+rcx*4]\nloc_13C2:\ntest esi, esi\njg short loc_13DF\nadd rdx, 4\ncmp rdx, r10\njnz short loc_13C2\nloc_13CF:\nxor eax, eax\nlea r11, unk_4040\nloc_13D8:\nmov [r8], eax\nmov rax, r11\nretn\nloc_13DF:\nmovsxd rsi, esi\nxor edi, edi\nlea r11, unk_4040\nlea rsi, [r9+rsi*4]\nnop\nloc_13F0:\nmov ecx, [rdx]\nmov rax, r9\njmp short loc_1409\nloc_1400:\nadd rax, 4\ncmp rax, rsi\njz short loc_1428\nloc_1409:\ncmp ecx, [rax]\njnz short loc_1400\nadd rdx, 4\nmov [r11+rdi*4], ecx\nlea eax, [rdi+1]\ncmp rdx, r10\njz short loc_13D8\nmovsxd rdi, eax\njmp short loc_13F0\nloc_1428:\nadd rdx, 4\ncmp rdx, r10\njnz short loc_13F0\nmov eax, edi\nmov [r8], eax\nmov rax, r11\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_13B0(_DWORD *a1, int a2, int *a3, int a4, _DWORD *a5)\n{\n int *v6; // r10\n int v7; // eax\n __int64 v9; // rdi\n _DWORD *v10; // rsi\n int v11; // ecx\n _DWORD *v12; // rax\n\n if ( a4 <= 0 )\n {\nLABEL_5:\n v7 = 0;\nLABEL_6:\n *a5 = v7;\n return dword_4040;\n }\n else\n {\n v6 = &a3[a4];\n while ( a2 <= 0 )\n {\n if ( ++a3 == v6 )\n goto LABEL_5;\n }\n v9 = 0LL;\n v10 = &a1[a2];\n do\n {\nLABEL_8:\n v11 = *a3;\n v12 = a1;\n do\n {\n if ( v11 == *v12 )\n {\n ++a3;\n dword_4040[v9] = v11;\n v7 = v9 + 1;\n if ( a3 == v6 )\n goto LABEL_6;\n v9 = v7;\n goto LABEL_8;\n }\n ++v12;\n }\n while ( v12 != v10 );\n ++a3;\n }\n while ( a3 != v6 );\n *a5 = v9;\n return dword_4040;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_13B0(uint32_t *a1, int a2, int *a3, int a4, uint32_t *a5) {\n int *v6;\n int v7;\n long long v9;\n uint32_t *v10;\n int v11;\n uint32_t *v12;\n if (a4 <= 0) {\n LABEL_5:\n v7 = 0;\n LABEL_6:\n *a5 = v7;\n return dword_4040;\n } else {\n v6 = &a3[a4];\n while (a2 <= 0) {\n if (++a3 == v6) goto LABEL_5;\n }\n v9 = 0LL;\n v10 = &a1[a2];\n do {\n LABEL_8:\n v11 = *a3;\n v12 = a1;\n do {\n if (v11 == *v12) {\n ++a3;\n dword_4040[v9] = v11;\n v7 = v9 + 1;\n if (a3 == v6) goto LABEL_6;\n v9 = v7;\n goto LABEL_8;\n }\n ++v12;\n } while (v12 != v10);\n ++a3;\n } while (a3 != v6);\n *a5 = v9;\n return dword_4040;\n }\n}", + "ida_pseudo_norm": "uint32_t *func0(uint32_t *a1, int a2, int *a3, int a4, uint32_t *a5) {\n int *v6;\n int v7;\n long long v9;\n uint32_t *v10;\n int v11;\n uint32_t *v12;\n if (a4 <= 0) {\n LABEL_5:\n v7 = 0;\n LABEL_6:\n *a5 = v7;\n return result_1;\n } else {\n v6 = &a3[a4];\n while (a2 <= 0) {\n if (++a3 == v6) goto LABEL_5;\n }\n v9 = 0LL;\n v10 = &a1[a2];\n do {\n LABEL_8:\n v11 = *a3;\n v12 = a1;\n do {\n if (v11 == *v12) {\n ++a3;\n result_1[v9] = v11;\n v7 = v9 + 1;\n if (a3 == v6) goto LABEL_6;\n v9 = v7;\n goto LABEL_8;\n }\n ++v12;\n } while (v12 != v10);\n ++a3;\n } while (a3 != v6);\n *a5 = v9;\n return result_1;\n }\n}" + }, + { + "index": 250, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int arr[], int arr_size, int x) {\n int count = 0;\n for (int i = 0; i < arr_size; i++) {\n if (arr[i] == x) {\n count++;\n }\n }\n return count;\n}", + "test": "int main() {\n\n int arr1[] = {10, 8, 5, 2, 10, 15, 10, 8, 5, 8, 8, 2};\n\n int size1 = sizeof(arr1) / sizeof(arr1[0]);\n\n assert(func0(arr1, size1, 4) == 0);\n\n assert(func0(arr1, size1, 10) == 3);\n\n assert(func0(arr1, size1, 8) == 4);\n\n \n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11ae \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x20(%rbp)\njne 11aa \naddl $0x1,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 118b \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11AE\nloc_118B:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njnz short loc_11AA\nadd [rbp+var_8], 1\nloc_11AA:\nadd [rbp+var_4], 1\nloc_11AE:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_118B\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n unsigned int v4; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( a3 == *(_DWORD *)(4LL * i + a1) )\n ++v4;\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11AE\nloc_118B:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njnz short loc_11AA\nadd [rbp+var_8], 1\nloc_11AA:\nadd [rbp+var_4], 1\nloc_11AE:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_118B\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n unsigned int v4; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( a3 == *(_DWORD *)(4LL * i + a1) )\n ++v4;\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n unsigned int v4;\n int i;\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n if (a3 == *(uint32_t *)(4LL * i + a1)) ++v4;\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n unsigned int v4;\n int i;\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n if (a3 == *(uint32_t *)(4LL * i + a1)) ++v4;\n }\n return v4;\n}" + }, + { + "index": 250, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int arr[], int arr_size, int x) {\n int count = 0;\n for (int i = 0; i < arr_size; i++) {\n if (arr[i] == x) {\n count++;\n }\n }\n return count;\n}", + "test": "int main() {\n\n int arr1[] = {10, 8, 5, 2, 10, 15, 10, 8, 5, 8, 8, 2};\n\n int size1 = sizeof(arr1) / sizeof(arr1[0]);\n\n assert(func0(arr1, size1, 4) == 0);\n\n assert(func0(arr1, size1, 10) == 3);\n\n assert(func0(arr1, size1, 8) == 4);\n\n \n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1199 \nmov %rdi,%rax\nlea -0x1(%rsi),%ecx\nlea 0x4(%rdi,%rcx,4),%rdi\nmov $0x0,%ecx\ncmp %edx,(%rax)\nsete %sil\nmovzbl %sil,%esi\nadd %esi,%ecx\nadd $0x4,%rax\ncmp %rdi,%rax\njne 1181 \nmov %ecx,%eax\nretq\nmov $0x0,%ecx\njmp 1196 \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1198\nmov rax, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*4]\nmov ecx, 0\nloc_1180:\ncmp [rax], edx\nsetz sil\nmovzx esi, sil\nadd ecx, esi\nadd rax, 4\ncmp rax, rdi\njnz short loc_1180\nloc_1195:\nmov eax, ecx\nretn\nloc_1198:\nmov ecx, 0\njmp short loc_1195", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2, int a3)\n{\n _DWORD *v3; // rax\n _DWORD *v4; // rdi\n unsigned int v5; // ecx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n do\n v5 += *v3++ == a3;\n while ( v3 != v4 );\n }\n return v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_1198\nmov rax, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*4]\nmov ecx, 0\nloc_1180:\ncmp [rax], edx\nsetz sil\nmovzx esi, sil\nadd ecx, esi\nadd rax, 4\ncmp rax, rdi\njnz short loc_1180\nloc_1195:\nmov eax, ecx\nretn\nloc_1198:\nmov ecx, 0\njmp short loc_1195", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2, int a3)\n{\n _DWORD *v3; // rax\n _DWORD *v4; // rdi\n unsigned int v5; // ecx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n do\n v5 += *v3++ == a3;\n while ( v3 != v4 );\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2, int a3) {\n uint32_t *v3;\n uint32_t *v4;\n unsigned int v5;\n if (a2 <= 0) {\n return 0;\n } else {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n do\n v5 += *v3++ == a3;\n while (v3 != v4);\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2, int a3) {\n uint32_t *v3;\n uint32_t *v4;\n unsigned int v5;\n if (a2 <= 0) {\n return 0;\n } else {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n do\n v5 += *v3++ == a3;\n while (v3 != v4);\n }\n return v5;\n}" + }, + { + "index": 251, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(char** list, int list_size, char* element, int* new_size) {\n *new_size = 2 * list_size;\n char** new_list = malloc((*new_size) * sizeof(char*));\n int k = 0;\n for (int i = 0; i < list_size; i++) {\n new_list[k++] = element;\n new_list[k++] = list[i];\n }\n return new_list;\n}", + "test": "int main() {\n\n char* colors[] = {\"Red\", \"Green\", \"Black\"};\n\n int colors_size = 3;\n\n char* colors_element = \"c\";\n\n int new_colors_size;\n\n char** new_colors = func0(colors, colors_size, colors_element, &new_colors_size);\n\n assert(new_colors_size == 6);\n\n assert(strcmp(new_colors[0], \"c\") == 0);\n\n assert(strcmp(new_colors[1], \"Red\") == 0);\n\n assert(strcmp(new_colors[2], \"c\") == 0);\n\n assert(strcmp(new_colors[3], \"Green\") == 0);\n\n assert(strcmp(new_colors[4], \"c\") == 0);\n\n assert(strcmp(new_colors[5], \"Black\") == 0);\n\n free(new_colors);\n\n\n\n char* languages[] = {\"python\", \"java\"};\n\n int languages_size = 2;\n\n char* languages_element = \"program\";\n\n int new_languages_size;\n\n char** new_languages = func0(languages, languages_size, languages_element, &new_languages_size);\n\n assert(new_languages_size == 4);\n\n assert(strcmp(new_languages[0], \"program\") == 0);\n\n assert(strcmp(new_languages[1], \"python\") == 0);\n\n assert(strcmp(new_languages[2], \"program\") == 0);\n\n assert(strcmp(new_languages[3], \"java\") == 0);\n\n free(new_languages);\n\n\n\n char* moods[] = {\"happy\", \"sad\"};\n\n int moods_size = 2;\n\n char* moods_element = \"laugh\";\n\n int new_moods_size;\n\n char** new_moods = func0(moods, moods_size, moods_element, &new_moods_size);\n\n assert(new_moods_size == 4);\n\n assert(strcmp(new_moods[0], \"laugh\") == 0);\n\n assert(strcmp(new_moods[1], \"happy\") == 0);\n\n assert(strcmp(new_moods[2], \"laugh\") == 0);\n\n assert(strcmp(new_moods[3], \"sad\") == 0);\n\n free(new_moods);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %rcx,-0x30(%rbp)\nmov -0x1c(%rbp),%eax\nlea (%rax,%rax,1),%edx\nmov -0x30(%rbp),%rax\nmov %edx,(%rax)\nmov -0x30(%rbp),%rax\nmov (%rax),%eax\ncltq\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 1272 \nmov -0x10(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x10(%rbp)\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov -0x28(%rbp),%rax\nmov %rax,(%rdx)\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x10(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x10(%rbp)\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%rax\nmov %rax,(%rdx)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1218 \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_30], rcx\nmov eax, [rbp+var_1C]\nlea edx, [rax+rax]\nmov rax, [rbp+var_30]\nmov [rax], edx\nmov rax, [rbp+var_30]\nmov eax, [rax]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp short loc_1272\nloc_1218:\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov rax, [rbp+var_28]\nmov [rdx], rax\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov rax, [rcx]\nmov [rdx], rax\nadd [rbp+var_C], 1\nloc_1272:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_1218\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, int a2, __int64 a3, int *a4)\n{\n int v4; // eax\n int v7; // [rsp+20h] [rbp-10h]\n int i; // [rsp+24h] [rbp-Ch]\n _QWORD *v9; // [rsp+28h] [rbp-8h]\n\n *a4 = 2 * a2;\n v9 = malloc(8LL * *a4);\n v7 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v9[v7] = a3;\n v4 = v7 + 1;\n v7 += 2;\n v9[v4] = *(_QWORD *)(8LL * i + a1);\n }\n return v9;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_30], rcx\nmov eax, [rbp+var_1C]\nlea edx, [rax+rax]\nmov rax, [rbp+var_30]\nmov [rax], edx\nmov rax, [rbp+var_30]\nmov eax, [rax]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp short loc_1272\nloc_1218:\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov rax, [rbp+var_28]\nmov [rdx], rax\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov rax, [rcx]\nmov [rdx], rax\nadd [rbp+var_C], 1\nloc_1272:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_1218\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11C9(__int64 a1, int a2, __int64 a3, int *a4)\n{\n int v4; // eax\n int v7; // [rsp+20h] [rbp-10h]\n int i; // [rsp+24h] [rbp-Ch]\n _QWORD *v9; // [rsp+28h] [rbp-8h]\n\n *a4 = 2 * a2;\n v9 = malloc(8LL * *a4);\n v7 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v9[v7] = a3;\n v4 = v7 + 1;\n v7 += 2;\n v9[v4] = *(_QWORD *)(8LL * i + a1);\n }\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11C9(long long a1, int a2, long long a3, int *a4) {\n int v4;\n int v7;\n int i;\n uint64_t *v9;\n *a4 = 2 * a2;\n v9 = malloc(8LL * *a4);\n v7 = 0;\n for (i = 0; i < a2; ++i) {\n v9[v7] = a3;\n v4 = v7 + 1;\n v7 += 2;\n v9[v4] = *(uint64_t *)(8LL * i + a1);\n }\n return v9;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, int a2, long long a3, int *a4) {\n int v4;\n int v7;\n int i;\n uint64_t *v9;\n *a4 = 2 * a2;\n v9 = malloc(8LL * *a4);\n v7 = 0;\n for (i = 0; i < a2; ++i) {\n v9[v7] = a3;\n v4 = v7 + 1;\n v7 += 2;\n v9[v4] = *(uint64_t *)(8LL * i + a1);\n }\n return v9;\n}" + }, + { + "index": 251, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(char** list, int list_size, char* element, int* new_size) {\n *new_size = 2 * list_size;\n char** new_list = malloc((*new_size) * sizeof(char*));\n int k = 0;\n for (int i = 0; i < list_size; i++) {\n new_list[k++] = element;\n new_list[k++] = list[i];\n }\n return new_list;\n}", + "test": "int main() {\n\n char* colors[] = {\"Red\", \"Green\", \"Black\"};\n\n int colors_size = 3;\n\n char* colors_element = \"c\";\n\n int new_colors_size;\n\n char** new_colors = func0(colors, colors_size, colors_element, &new_colors_size);\n\n assert(new_colors_size == 6);\n\n assert(strcmp(new_colors[0], \"c\") == 0);\n\n assert(strcmp(new_colors[1], \"Red\") == 0);\n\n assert(strcmp(new_colors[2], \"c\") == 0);\n\n assert(strcmp(new_colors[3], \"Green\") == 0);\n\n assert(strcmp(new_colors[4], \"c\") == 0);\n\n assert(strcmp(new_colors[5], \"Black\") == 0);\n\n free(new_colors);\n\n\n\n char* languages[] = {\"python\", \"java\"};\n\n int languages_size = 2;\n\n char* languages_element = \"program\";\n\n int new_languages_size;\n\n char** new_languages = func0(languages, languages_size, languages_element, &new_languages_size);\n\n assert(new_languages_size == 4);\n\n assert(strcmp(new_languages[0], \"program\") == 0);\n\n assert(strcmp(new_languages[1], \"python\") == 0);\n\n assert(strcmp(new_languages[2], \"program\") == 0);\n\n assert(strcmp(new_languages[3], \"java\") == 0);\n\n free(new_languages);\n\n\n\n char* moods[] = {\"happy\", \"sad\"};\n\n int moods_size = 2;\n\n char* moods_element = \"laugh\";\n\n int new_moods_size;\n\n char** new_moods = func0(moods, moods_size, moods_element, &new_moods_size);\n\n assert(new_moods_size == 4);\n\n assert(strcmp(new_moods[0], \"laugh\") == 0);\n\n assert(strcmp(new_moods[1], \"happy\") == 0);\n\n assert(strcmp(new_moods[2], \"laugh\") == 0);\n\n assert(strcmp(new_moods[3], \"sad\") == 0);\n\n free(new_moods);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nmov %esi,%r12d\nmov %rdx,%rbp\nlea (%rsi,%rsi,1),%edi\nmov %edi,(%rcx)\nmovslq %edi,%rdi\nshl $0x3,%rdi\ncallq 10b0 \ntest %r12d,%r12d\njle 11f5 \nlea -0x1(%r12),%edx\nlea 0x2(%rdx,%rdx,1),%rsi\nmov $0x0,%edx\nmov %rbp,(%rax,%rdx,8)\nmov (%rbx,%rdx,4),%rcx\nmov %rcx,0x8(%rax,%rdx,8)\nadd $0x2,%rdx\ncmp %rsi,%rdx\njne 11df \npop %rbx\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov r13d, esi\nmov r12, rdx\nlea ebx, [rsi+rsi]\nmov [rcx], ebx\nmovsxd rbx, ebx\nlea rdi, ds:0[rbx*8]; size\ncall _malloc\ntest r13d, r13d\njle short loc_1216\nmov edx, 0\nloc_11FF:\nmov [rax+rdx*8], r12\nmov rcx, [rbp+rdx*4+0]\nmov [rax+rdx*8+8], rcx\nadd rdx, 2\ncmp rbx, rdx\njnz short loc_11FF\nloc_1216:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, int a2, __int64 a3, _DWORD *a4)\n{\n __int64 v5; // rbx\n _QWORD *result; // rax\n __int64 v7; // rdx\n\n *a4 = 2 * a2;\n v5 = 2 * a2;\n result = malloc(8 * v5);\n if ( a2 > 0 )\n {\n v7 = 0LL;\n do\n {\n result[v7] = a3;\n result[v7 + 1] = *(_QWORD *)(a1 + 4 * v7);\n v7 += 2LL;\n }\n while ( v5 != v7 );\n }\n return result;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov r13d, esi\nmov r12, rdx\nlea ebx, [rsi+rsi]\nmov [rcx], ebx\nmovsxd rbx, ebx\nlea rdi, ds:0[rbx*8]; size\ncall _malloc\ntest r13d, r13d\njle short loc_1216\nmov edx, 0\nloc_11FF:\nmov [rax+rdx*8], r12\nmov rcx, [rbp+rdx*4+0]\nmov [rax+rdx*8+8], rcx\nadd rdx, 2\ncmp rbx, rdx\njnz short loc_11FF\nloc_1216:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11C9(__int64 a1, int a2, __int64 a3, _DWORD *a4)\n{\n __int64 v5; // rbx\n _QWORD *result; // rax\n __int64 v7; // rdx\n\n *a4 = 2 * a2;\n v5 = 2 * a2;\n result = malloc(8 * v5);\n if ( a2 > 0 )\n {\n v7 = 0LL;\n do\n {\n result[v7] = a3;\n result[v7 + 1] = *(_QWORD *)(a1 + 4 * v7);\n v7 += 2LL;\n }\n while ( v5 != v7 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11C9(long long a1, int a2, long long a3, uint32_t *a4) {\n long long v5;\n uint64_t *result;\n long long v7;\n *a4 = 2 * a2;\n v5 = 2 * a2;\n result = malloc(8 * v5);\n if (a2 > 0) {\n v7 = 0LL;\n do {\n result[v7] = a3;\n result[v7 + 1] = *(uint64_t *)(a1 + 4 * v7);\n v7 += 2LL;\n } while (v5 != v7);\n }\n return result;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, int a2, long long a3, uint32_t *a4) {\n long long v5;\n uint64_t *result;\n long long v7;\n *a4 = 2 * a2;\n v5 = 2 * a2;\n result = malloc(8 * v5);\n if (a2 > 0) {\n v7 = 0LL;\n do {\n result[v7] = a3;\n result[v7 + 1] = *(uint64_t *)(a1 + 4 * v7);\n v7 += 2LL;\n } while (v5 != v7);\n }\n return result;\n}" + }, + { + "index": 251, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(char** list, int list_size, char* element, int* new_size) {\n *new_size = 2 * list_size;\n char** new_list = malloc((*new_size) * sizeof(char*));\n int k = 0;\n for (int i = 0; i < list_size; i++) {\n new_list[k++] = element;\n new_list[k++] = list[i];\n }\n return new_list;\n}", + "test": "int main() {\n\n char* colors[] = {\"Red\", \"Green\", \"Black\"};\n\n int colors_size = 3;\n\n char* colors_element = \"c\";\n\n int new_colors_size;\n\n char** new_colors = func0(colors, colors_size, colors_element, &new_colors_size);\n\n assert(new_colors_size == 6);\n\n assert(strcmp(new_colors[0], \"c\") == 0);\n\n assert(strcmp(new_colors[1], \"Red\") == 0);\n\n assert(strcmp(new_colors[2], \"c\") == 0);\n\n assert(strcmp(new_colors[3], \"Green\") == 0);\n\n assert(strcmp(new_colors[4], \"c\") == 0);\n\n assert(strcmp(new_colors[5], \"Black\") == 0);\n\n free(new_colors);\n\n\n\n char* languages[] = {\"python\", \"java\"};\n\n int languages_size = 2;\n\n char* languages_element = \"program\";\n\n int new_languages_size;\n\n char** new_languages = func0(languages, languages_size, languages_element, &new_languages_size);\n\n assert(new_languages_size == 4);\n\n assert(strcmp(new_languages[0], \"program\") == 0);\n\n assert(strcmp(new_languages[1], \"python\") == 0);\n\n assert(strcmp(new_languages[2], \"program\") == 0);\n\n assert(strcmp(new_languages[3], \"java\") == 0);\n\n free(new_languages);\n\n\n\n char* moods[] = {\"happy\", \"sad\"};\n\n int moods_size = 2;\n\n char* moods_element = \"laugh\";\n\n int new_moods_size;\n\n char** new_moods = func0(moods, moods_size, moods_element, &new_moods_size);\n\n assert(new_moods_size == 4);\n\n assert(strcmp(new_moods[0], \"laugh\") == 0);\n\n assert(strcmp(new_moods[1], \"happy\") == 0);\n\n assert(strcmp(new_moods[2], \"laugh\") == 0);\n\n assert(strcmp(new_moods[3], \"sad\") == 0);\n\n free(new_moods);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %esi,%r12d\npush %rbp\nmov %rdx,%rbp\npush %rbx\nmov %rdi,%rbx\nlea (%rsi,%rsi,1),%edi\nmov %edi,(%rcx)\nmovslq %edi,%rdi\nshl $0x3,%rdi\ncallq 10b0 \ntest %r12d,%r12d\njle 16ae \nlea -0x1(%r12),%edx\nxor %ecx,%ecx\nlea 0x2(%rdx,%rdx,1),%rdx\nnopl 0x0(%rax,%rax,1)\nmov (%rbx,%rcx,4),%rsi\nmov %rbp,(%rax,%rcx,8)\nmov %rsi,0x8(%rax,%rcx,8)\nadd $0x2,%rcx\ncmp %rcx,%rdx\njne 1698 \npop %rbx\npop %rbp\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r12\nmov r12d, esi\npush rbp\nmov rbp, rdi\npush rbx\nlea ebx, [rsi+rsi]\nsub rsp, 10h\nmov [rcx], ebx\nmovsxd rbx, ebx\nlea rdi, ds:0[rbx*8]; size\nmov [rsp+28h+var_20], rdx\ncall _malloc\ntest r12d, r12d\njle short loc_16A6\nmovq xmm1, [rsp+28h+var_20]\nxor ecx, ecx\nnop dword ptr [rax+00000000h]\nloc_1690:\nmovdqa xmm0, xmm1\nmovhps xmm0, qword ptr [rbp+rcx*4+0]\nmovups xmmword ptr [rax+rcx*8], xmm0\nadd rcx, 2\ncmp rbx, rcx\njnz short loc_1690\nloc_16A6:\nadd rsp, 10h\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2, __int64 a3, _DWORD *a4)\n{\n __int64 v4; // rbx\n char *result; // rax\n __int64 v6; // rcx\n\n *a4 = 2 * a2;\n v4 = 2 * a2;\n result = (char *)malloc(8 * v4);\n if ( a2 > 0 )\n {\n v6 = 0LL;\n do\n {\n *(__m128 *)&result[8 * v6] = _mm_loadh_ps((const double *)(a1 + 4 * v6));\n v6 += 2LL;\n }\n while ( v4 != v6 );\n }\n return result;\n}", + "ida_strip_asm": "sub_1650:\nendbr64\npush r12\nmov r12d, esi\npush rbp\nmov rbp, rdi\npush rbx\nlea ebx, [rsi+rsi]\nsub rsp, 10h\nmov [rcx], ebx\nmovsxd rbx, ebx\nlea rdi, ds:0[rbx*8]; size\nmov [rsp+28h+var_20], rdx\ncall _malloc\ntest r12d, r12d\njle short loc_16A6\nmovq xmm1, [rsp+28h+var_20]\nxor ecx, ecx\nnop dword ptr [rax+00000000h]\nloc_1690:\nmovdqa xmm0, xmm1\nmovhps xmm0, qword ptr [rbp+rcx*4+0]\nmovups xmmword ptr [rax+rcx*8], xmm0\nadd rcx, 2\ncmp rbx, rcx\njnz short loc_1690\nloc_16A6:\nadd rsp, 10h\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1650(__int64 a1, int a2, __int64 a3, _DWORD *a4)\n{\n __int64 v4; // rbx\n char *result; // rax\n __int64 v6; // rcx\n\n *a4 = 2 * a2;\n v4 = 2 * a2;\n result = (char *)malloc(8 * v4);\n if ( a2 > 0 )\n {\n v6 = 0LL;\n do\n {\n *(__m128 *)&result[8 * v6] = _mm_loadh_ps((const double *)(a1 + 4 * v6));\n v6 += 2LL;\n }\n while ( v4 != v6 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1650(long long a1, int a2, long long a3, uint32_t *a4) {\n long long v4;\n char *result;\n long long v6;\n *a4 = 2 * a2;\n v4 = 2 * a2;\n result = (char *)malloc(8 * v4);\n if (a2 > 0) {\n v6 = 0LL;\n do {\n *(__m128 *)&result[8 * v6] = _mm_loadh_ps((const double *)(a1 + 4 * v6));\n v6 += 2LL;\n } while (v4 != v6);\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2, long long a3, uint32_t *a4) {\n long long v4;\n char *result;\n long long v6;\n *a4 = 2 * a2;\n v4 = 2 * a2;\n result = (char *)malloc(8 * v4);\n if (a2 > 0) {\n v6 = 0LL;\n do {\n *(__m128 *)&result[8 * v6] = _mm_loadh_ps((const double *)(a1 + 4 * v6));\n v6 += 2LL;\n } while (v4 != v6);\n }\n return result;\n}" + }, + { + "index": 251, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(char** list, int list_size, char* element, int* new_size) {\n *new_size = 2 * list_size;\n char** new_list = malloc((*new_size) * sizeof(char*));\n int k = 0;\n for (int i = 0; i < list_size; i++) {\n new_list[k++] = element;\n new_list[k++] = list[i];\n }\n return new_list;\n}", + "test": "int main() {\n\n char* colors[] = {\"Red\", \"Green\", \"Black\"};\n\n int colors_size = 3;\n\n char* colors_element = \"c\";\n\n int new_colors_size;\n\n char** new_colors = func0(colors, colors_size, colors_element, &new_colors_size);\n\n assert(new_colors_size == 6);\n\n assert(strcmp(new_colors[0], \"c\") == 0);\n\n assert(strcmp(new_colors[1], \"Red\") == 0);\n\n assert(strcmp(new_colors[2], \"c\") == 0);\n\n assert(strcmp(new_colors[3], \"Green\") == 0);\n\n assert(strcmp(new_colors[4], \"c\") == 0);\n\n assert(strcmp(new_colors[5], \"Black\") == 0);\n\n free(new_colors);\n\n\n\n char* languages[] = {\"python\", \"java\"};\n\n int languages_size = 2;\n\n char* languages_element = \"program\";\n\n int new_languages_size;\n\n char** new_languages = func0(languages, languages_size, languages_element, &new_languages_size);\n\n assert(new_languages_size == 4);\n\n assert(strcmp(new_languages[0], \"program\") == 0);\n\n assert(strcmp(new_languages[1], \"python\") == 0);\n\n assert(strcmp(new_languages[2], \"program\") == 0);\n\n assert(strcmp(new_languages[3], \"java\") == 0);\n\n free(new_languages);\n\n\n\n char* moods[] = {\"happy\", \"sad\"};\n\n int moods_size = 2;\n\n char* moods_element = \"laugh\";\n\n int new_moods_size;\n\n char** new_moods = func0(moods, moods_size, moods_element, &new_moods_size);\n\n assert(new_moods_size == 4);\n\n assert(strcmp(new_moods[0], \"laugh\") == 0);\n\n assert(strcmp(new_moods[1], \"happy\") == 0);\n\n assert(strcmp(new_moods[2], \"laugh\") == 0);\n\n assert(strcmp(new_moods[3], \"sad\") == 0);\n\n free(new_moods);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %esi,%ebp\npush %rbx\nmov %rdi,%rbx\nlea (%rsi,%rsi,1),%edi\nsub $0x18,%rsp\nmov %edi,(%rcx)\nmovslq %edi,%rdi\nshl $0x3,%rdi\nmov %rdx,0x8(%rsp)\ncallq 10b0 \ntest %ebp,%ebp\njle 1707 \ncmp $0x1,%ebp\nmovq 0x8(%rsp),%xmm2\nje 170e \nmov %ebp,%ecx\nmovdqa %xmm2,%xmm0\nxor %edx,%edx\nshr %ecx\npunpcklqdq %xmm0,%xmm0\nshl $0x4,%rcx\nnopw %cs:0x0(%rax,%rax,1)\nmovdqu (%rbx,%rdx,1),%xmm3\nmovdqa %xmm0,%xmm1\npunpcklqdq %xmm3,%xmm1\nmovups %xmm1,(%rax,%rdx,2)\nmovdqa %xmm0,%xmm1\npunpckhqdq %xmm3,%xmm1\nmovups %xmm1,0x10(%rax,%rdx,2)\nadd $0x10,%rdx\ncmp %rdx,%rcx\njne 16c0 \nmov %ebp,%ecx\nand $0xfffffffe,%ecx\nlea (%rcx,%rcx,1),%edx\ncmp %ecx,%ebp\nje 1707 \nmovslq %ecx,%rcx\nmovslq %edx,%rdx\nmov (%rbx,%rcx,8),%rcx\nmovq %xmm2,(%rax,%rdx,8)\nmov %rcx,0x8(%rax,%rdx,8)\nadd $0x18,%rsp\npop %rbx\npop %rbp\nretq\nxor %ecx,%ecx\nxor %edx,%edx\njmp 16f3 \nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov ebp, esi\npush rbx\nmov rbx, rdi\nlea edi, [rsi+rsi]\nsub rsp, 18h\nmov [rcx], edi\nmovsxd rdi, edi\nshl rdi, 3; size\nmov [rsp+28h+var_20], rdx\ncall _malloc\ntest ebp, ebp\njle short loc_16E5\ncmp ebp, 1\nmovq xmm0, [rsp+28h+var_20]\njz short loc_16EC\nmov edx, ebp\nmovdqa xmm3, xmm0\nxor ecx, ecx\nshr edx, 1\npunpcklqdq xmm3, xmm3\nshl rdx, 4\nnop word ptr [rax+rax+00000000h]\nloc_16A0:\nmovdqu xmm4, xmmword ptr [rbx+rcx]\nmovdqa xmm1, xmm3\nmovdqa xmm2, xmm0\npunpcklqdq xmm1, xmm4\nmovups xmmword ptr [rax+rcx*2], xmm1\nmovhlps xmm1, xmm4\npunpcklqdq xmm2, xmm1\nmovups xmmword ptr [rax+rcx*2+10h], xmm2\nadd rcx, 10h\ncmp rdx, rcx\njnz short loc_16A0\nmov edx, ebp\nand edx, 0FFFFFFFEh\nand ebp, 1\njz short loc_16E5\nlea ecx, [rdx+rdx]\nloc_16D7:\nmovsxd rdx, edx\nmovhps xmm0, qword ptr [rbx+rdx*8]\nmovsxd rdx, ecx\nmovups xmmword ptr [rax+rdx*8], xmm0\nloc_16E5:\nadd rsp, 18h\npop rbx\npop rbp\nretn\nloc_16EC:\nxor edx, edx\nxor ecx, ecx\njmp short loc_16D7", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2, __int64 a3, _DWORD *a4)\n{\n char *result; // rax\n __m128i v5; // xmm0\n __int64 v6; // rcx\n __m128i v7; // xmm3\n __m128 v8; // xmm4\n __m128 v9; // xmm1\n signed int v10; // edx\n int v11; // ecx\n __m128i v12[2]; // [rsp+8h] [rbp-20h] BYREF\n\n *a4 = 2 * a2;\n v12[0].m128i_i64[0] = a3;\n result = (char *)malloc(16LL * a2);\n if ( a2 > 0 )\n {\n v5 = _mm_loadl_epi64(v12);\n if ( a2 == 1 )\n {\n v10 = 0;\n v11 = 0;\n goto LABEL_7;\n }\n v6 = 0LL;\n v7 = _mm_unpacklo_epi64(v5, v5);\n do\n {\n v8 = (__m128)_mm_loadu_si128((const __m128i *)(a1 + v6));\n v9 = (__m128)_mm_unpacklo_epi64(v7, (__m128i)v8);\n *(__m128 *)&result[2 * v6] = v9;\n *(__m128i *)&result[2 * v6 + 16] = _mm_unpacklo_epi64(v5, (__m128i)_mm_movehl_ps(v9, v8));\n v6 += 16LL;\n }\n while ( 16LL * ((unsigned int)a2 >> 1) != v6 );\n v10 = a2 & 0xFFFFFFFE;\n if ( (a2 & 1) != 0 )\n {\n v11 = 2 * v10;\nLABEL_7:\n *(__m128 *)&result[8 * v11] = _mm_loadh_ps((const double *)(a1 + 8LL * v10));\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1650:\nendbr64\npush rbp\nmov ebp, esi\npush rbx\nmov rbx, rdi\nlea edi, [rsi+rsi]\nsub rsp, 18h\nmov [rcx], edi\nmovsxd rdi, edi\nshl rdi, 3; size\nmov [rsp+28h+var_20], rdx\ncall _malloc\ntest ebp, ebp\njle short loc_16E5\ncmp ebp, 1\nmovq xmm0, [rsp+28h+var_20]\njz short loc_16EC\nmov edx, ebp\nmovdqa xmm3, xmm0\nxor ecx, ecx\nshr edx, 1\npunpcklqdq xmm3, xmm3\nshl rdx, 4\nnop word ptr [rax+rax+00000000h]\nloc_16A0:\nmovdqu xmm4, xmmword ptr [rbx+rcx]\nmovdqa xmm1, xmm3\nmovdqa xmm2, xmm0\npunpcklqdq xmm1, xmm4\nmovups xmmword ptr [rax+rcx*2], xmm1\nmovhlps xmm1, xmm4\npunpcklqdq xmm2, xmm1\nmovups xmmword ptr [rax+rcx*2+10h], xmm2\nadd rcx, 10h\ncmp rdx, rcx\njnz short loc_16A0\nmov edx, ebp\nand edx, 0FFFFFFFEh\nand ebp, 1\njz short loc_16E5\nlea ecx, [rdx+rdx]\nloc_16D7:\nmovsxd rdx, edx\nmovhps xmm0, qword ptr [rbx+rdx*8]\nmovsxd rdx, ecx\nmovups xmmword ptr [rax+rdx*8], xmm0\nloc_16E5:\nadd rsp, 18h\npop rbx\npop rbp\nretn\nloc_16EC:\nxor edx, edx\nxor ecx, ecx\njmp short loc_16D7", + "ida_strip_pseudo": "char *__fastcall sub_1650(__int64 a1, int a2, __int64 a3, _DWORD *a4)\n{\n char *result; // rax\n __m128i v5; // xmm0\n __int64 v6; // rcx\n __m128i v7; // xmm3\n __m128 v8; // xmm4\n __m128 v9; // xmm1\n signed int v10; // edx\n int v11; // ecx\n __m128i v12[2]; // [rsp+8h] [rbp-20h] BYREF\n\n *a4 = 2 * a2;\n v12[0].m128i_i64[0] = a3;\n result = (char *)malloc(16LL * a2);\n if ( a2 > 0 )\n {\n v5 = _mm_loadl_epi64(v12);\n if ( a2 == 1 )\n {\n v10 = 0;\n v11 = 0;\n goto LABEL_7;\n }\n v6 = 0LL;\n v7 = _mm_unpacklo_epi64(v5, v5);\n do\n {\n v8 = (__m128)_mm_loadu_si128((const __m128i *)(a1 + v6));\n v9 = (__m128)_mm_unpacklo_epi64(v7, (__m128i)v8);\n *(__m128 *)&result[2 * v6] = v9;\n *(__m128i *)&result[2 * v6 + 16] = _mm_unpacklo_epi64(v5, (__m128i)_mm_movehl_ps(v9, v8));\n v6 += 16LL;\n }\n while ( 16LL * ((unsigned int)a2 >> 1) != v6 );\n v10 = a2 & 0xFFFFFFFE;\n if ( (a2 & 1) != 0 )\n {\n v11 = 2 * v10;\nLABEL_7:\n *(__m128 *)&result[8 * v11] = _mm_loadh_ps((const double *)(a1 + 8LL * v10));\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1650(long long a1, int a2, long long a3, uint32_t *a4) {\n char *result;\n __m128i v5;\n long long v6;\n __m128i v7;\n __m128 v8;\n __m128 v9;\n signed int v10;\n int v11;\n __m128i v12[2];\n *a4 = 2 * a2;\n v12[0].m128i_i64[0] = a3;\n result = (char *)malloc(16LL * a2);\n if (a2 > 0) {\n v5 = _mm_loadl_epi64(v12);\n if (a2 == 1) {\n v10 = 0;\n v11 = 0;\n goto LABEL_7;\n }\n v6 = 0LL;\n v7 = _mm_unpacklo_epi64(v5, v5);\n do {\n v8 = (__m128)_mm_loadu_si128((const __m128i *)(a1 + v6));\n v9 = (__m128)_mm_unpacklo_epi64(v7, (__m128i)v8);\n *(__m128 *)&result[2 * v6] = v9;\n *(__m128i *)&result[2 * v6 + 16] =\n _mm_unpacklo_epi64(v5, (__m128i)_mm_movehl_ps(v9, v8));\n v6 += 16LL;\n } while (16LL * ((unsigned int)a2 >> 1) != v6);\n v10 = a2 & 4294967294;\n if ((a2 & 1) != 0) {\n v11 = 2 * v10;\n LABEL_7:\n *(__m128 *)&result[8 * v11] =\n _mm_loadh_ps((const double *)(a1 + 8LL * v10));\n }\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2, long long a3, uint32_t *a4) {\n char *result;\n __m128i v5;\n long long v6;\n __m128i v7;\n __m128 v8;\n __m128 v9;\n signed int v10;\n int v11;\n __m128i v12[2];\n *a4 = 2 * a2;\n v12[0].m128i_i64[0] = a3;\n result = (char *)malloc(16LL * a2);\n if (a2 > 0) {\n v5 = _mm_loadl_epi64(v12);\n if (a2 == 1) {\n v10 = 0;\n v11 = 0;\n goto LABEL_7;\n }\n v6 = 0LL;\n v7 = _mm_unpacklo_epi64(v5, v5);\n do {\n v8 = (__m128)_mm_loadu_si128((const __m128i *)(a1 + v6));\n v9 = (__m128)_mm_unpacklo_epi64(v7, (__m128i)v8);\n *(__m128 *)&result[2 * v6] = v9;\n *(__m128i *)&result[2 * v6 + 16] =\n _mm_unpacklo_epi64(v5, (__m128i)_mm_movehl_ps(v9, v8));\n v6 += 16LL;\n } while (16LL * ((unsigned int)a2 >> 1) != v6);\n v10 = a2 & 4294967294;\n if ((a2 & 1) != 0) {\n v11 = 2 * v10;\n LABEL_7:\n *(__m128 *)&result[8 * v11] =\n _mm_loadh_ps((const double *)(a1 + 8LL * v10));\n }\n }\n return result;\n}" + }, + { + "index": 252, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n double magnitude;\n\n double angle;\n\n} polar_number;\n\n\n\n", + "func": "polar_number func0(double numbers) {\n polar_number num;\n num.magnitude = fabs(numbers);\n num.angle = 0.0;\n return num;\n}", + "test": "int main() {\n\n polar_number num;\n\n\n\n num = func0(1);\n\n assert(num.magnitude == 1.0 && num.angle == 0.0);\n\n\n\n num = func0(4);\n\n assert(num.magnitude == 4.0 && num.angle == 0.0);\n\n\n\n num = func0(5);\n\n assert(num.magnitude == 5.0 && num.angle == 0.0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nmovsd %xmm0,-0x20(%rbp)\nmovsd -0x20(%rbp),%xmm0\nmovq 0xf7c(%rip),%xmm1\nandpd %xmm1,%xmm0\nmovsd %xmm0,-0x18(%rbp)\npxor %xmm0,%xmm0\nmovsd %xmm0,-0x10(%rbp)\nmov -0x18(%rbp),%rax\nmov -0x10(%rbp),%rdx\nmov %rax,%rcx\nmov %rdx,%rbx\nmovq %rcx,%xmm0\nmovq %rdx,%xmm1\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmovsd [rbp+var_18], xmm0\nmovsd xmm0, [rbp+var_18]\nmovq xmm1, cs:qword_20C0\nandpd xmm0, xmm1\nmovsd [rbp+var_10], xmm0\npxor xmm0, xmm0\nmovsd [rbp+var_8], xmm0\nmov rax, [rbp+var_10]\nmov rdx, [rbp+var_8]\nmov qword ptr [rbp+var_30], rax\nmov qword ptr [rbp+var_30+8], rdx\nmovdqa xmm0, [rbp+var_30]\nmovq xmm1, rdx\npop rbp\nretn", + "ida_pseudo": "__m128i __fastcall func0(double a1)\n{\n __m128i v2; // [rsp+0h] [rbp-30h] BYREF\n double v3; // [rsp+18h] [rbp-18h]\n double v4; // [rsp+20h] [rbp-10h]\n __int64 v5; // [rsp+28h] [rbp-8h]\n\n v3 = a1;\n v4 = fabs(a1);\n v5 = 0LL;\n v2 = (__m128i)*(unsigned __int64 *)&v4;\n return _mm_load_si128(&v2);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmovsd [rbp+var_18], xmm0\nmovsd xmm0, [rbp+var_18]\nmovq xmm1, cs:qword_20C0\nandpd xmm0, xmm1\nmovsd [rbp+var_10], xmm0\npxor xmm0, xmm0\nmovsd [rbp+var_8], xmm0\nmov rax, [rbp+var_10]\nmov rdx, [rbp+var_8]\nmov qword ptr [rbp+var_30], rax\nmov qword ptr [rbp+var_30+8], rdx\nmovdqa xmm0, [rbp+var_30]\nmovq xmm1, rdx\npop rbp\nretn", + "ida_strip_pseudo": "__m128i __fastcall sub_1149(double a1)\n{\n __m128i v2; // [rsp+0h] [rbp-30h] BYREF\n double v3; // [rsp+18h] [rbp-18h]\n double v4; // [rsp+20h] [rbp-10h]\n __int64 v5; // [rsp+28h] [rbp-8h]\n\n v3 = a1;\n v4 = fabs(a1);\n v5 = 0LL;\n v2 = (__m128i)*(unsigned __int64 *)&v4;\n return _mm_load_si128(&v2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__m128i sub_1149(double a1) {\n __m128i v2;\n double v3;\n double v4;\n long long v5;\n v3 = a1;\n v4 = fabs(a1);\n v5 = 0LL;\n v2 = (__m128i) * (unsigned long long *)&v4;\n return _mm_load_si128(&v2);\n}", + "ida_pseudo_norm": "__m128i func0(double a1) {\n __m128i v2;\n double v3;\n double v4;\n long long v5;\n v3 = a1;\n v4 = fabs(a1);\n v5 = 0LL;\n v2 = (__m128i) * (unsigned long long *)&v4;\n return _mm_load_si128(&v2);\n}" + }, + { + "index": 253, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int list1[], int length) {\n int ctr = 0;\n for (int i = 0; i < length; i++) {\n ctr++;\n }\n return ctr;\n}", + "test": "int main() {\n\n int list1[] = {1, 2, 5};\n\n int size1 = sizeof(list1) / sizeof(list1[0]);\n\n assert(func0(list1, size1) == 3);\n\n\n\n int list2[] = {1, 2, 3};\n\n int size2 = sizeof(list2) / sizeof(list2[0]);\n\n assert(func0(list2, size2) == 3);\n\n\n\n int list3[] = {1, 4};\n\n int size3 = sizeof(list3) / sizeof(list3[0]);\n\n assert(func0(list3, size3) == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 1190 \naddl $0x1,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1188 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_1190\nloc_1188:\nadd [rbp+var_8], 1\nadd [rbp+var_4], 1\nloc_1190:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n ++v3;\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_1190\nloc_1188:\nadd [rbp+var_8], 1\nadd [rbp+var_4], 1\nloc_1190:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n ++v3;\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) ++v3;\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) ++v3;\n return v3;\n}" + }, + { + "index": 254, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char **matches;\n\n int count;\n\n} MatchList;\n\n\n\n", + "func": "MatchList func0(const char *text) {\n regex_t regex;\n regmatch_t pmatch[1];\n const char *pattern = \"[ae]\\\\w+\";\n int ret;\n MatchList list;\n list.matches = NULL;\n list.count = 0;\n ret = regcomp(®ex, pattern, REG_EXTENDED);\n if (ret) {\n fprintf(stderr, \"Could not compile regex\\n\");\n exit(1);\n }\n const char *p = text;\n while ((ret = regexec(®ex, p, 1, pmatch, 0)) != REG_NOMATCH) {\n if (ret) {\n regfree(®ex);\n fprintf(stderr, \"Regex match failed\\n\");\n exit(1);\n }\n int start = pmatch[0].rm_so;\n int end = pmatch[0].rm_eo;\n int len = end - start;\n char *match = (char *)malloc(len + 1);\n strncpy(match, p + start, len);\n match[len] = '\\0';\n list.matches =\n (char **)realloc(list.matches, sizeof(char *) * (list.count + 1));\n list.matches[list.count] = match;\n list.count++;\n p += end;\n }\n regfree(®ex);\n return list;\n}", + "test": "int main() {\n\n // Test case 1\n\n MatchList result1 = func0(\"python programe\");\n\n assert(result1.count == 1);\n\n assert(strcmp(result1.matches[0], \"ame\") == 0);\n\n for(int i = 0; i < result1.count; i++) {\n\n free(result1.matches[i]);\n\n }\n\n free(result1.matches);\n\n\n\n // Test case 2\n\n MatchList result2 = func0(\"python programe language\");\n\n assert(result2.count == 2);\n\n assert(strcmp(result2.matches[0], \"ame\") == 0);\n\n assert(strcmp(result2.matches[1], \"anguage\") == 0);\n\n for(int i = 0; i < result2.count; i++) {\n\n free(result2.matches[i]);\n\n }\n\n free(result2.matches);\n\n\n\n // Test case 3\n\n MatchList result3 = func0(\"assert statement\");\n\n assert(result3.count == 2);\n\n assert(strcmp(result3.matches[0], \"assert\") == 0);\n\n assert(strcmp(result3.matches[1], \"atement\") == 0);\n\n for(int i = 0; i < result3.count; i++) {\n\n free(result3.matches[i]);\n\n }\n\n free(result3.matches);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0xa0,%rsp\nmov %rdi,-0x98(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0xd33(%rip),%rax\nmov %rax,-0x70(%rbp)\nmovq $0x0,-0x60(%rbp)\nmovl $0x0,-0x58(%rbp)\nmov -0x70(%rbp),%rcx\nlea -0x50(%rbp),%rax\nmov $0x1,%edx\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 1150 \nmov %eax,-0x88(%rbp)\ncmpl $0x0,-0x88(%rbp)\nje 1339 \nmov 0x2d0a(%rip),%rax\nmov %rax,%rcx\nmov $0x18,%edx\nmov $0x1,%esi\nlea 0xce6(%rip),%rdi\ncallq 11b0 \nmov $0x1,%edi\ncallq 11a0 \nmov -0x98(%rbp),%rax\nmov %rax,-0x78(%rbp)\njmpq 1439 \ncmpl $0x0,-0x88(%rbp)\nje 1388 \nlea -0x50(%rbp),%rax\nmov %rax,%rdi\ncallq 1120 \nmov 0x2cbb(%rip),%rax\nmov %rax,%rcx\nmov $0x13,%edx\nmov $0x1,%esi\nlea 0xcb0(%rip),%rdi\ncallq 11b0 \nmov $0x1,%edi\ncallq 11a0 \nmov -0x10(%rbp),%eax\nmov %eax,-0x84(%rbp)\nmov -0xc(%rbp),%eax\nmov %eax,-0x80(%rbp)\nmov -0x80(%rbp),%eax\nsub -0x84(%rbp),%eax\nmov %eax,-0x7c(%rbp)\nmov -0x7c(%rbp),%eax\nadd $0x1,%eax\ncltq\nmov %rax,%rdi\ncallq 1170 \nmov %rax,-0x68(%rbp)\nmov -0x7c(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x84(%rbp),%eax\nmovslq %eax,%rcx\nmov -0x78(%rbp),%rax\nadd %rax,%rcx\nmov -0x68(%rbp),%rax\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 1110 \nmov -0x7c(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x68(%rbp),%rax\nadd %rdx,%rax\nmovb $0x0,(%rax)\nmov -0x58(%rbp),%eax\nadd $0x1,%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x60(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1190 \nmov %rax,-0x60(%rbp)\nmov -0x60(%rbp),%rax\nmov -0x58(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x3,%rdx\nadd %rax,%rdx\nmov -0x68(%rbp),%rax\nmov %rax,(%rdx)\nmov -0x58(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x58(%rbp)\nmov -0x80(%rbp),%eax\ncltq\nadd %rax,-0x78(%rbp)\nlea -0x10(%rbp),%rdx\nmov -0x78(%rbp),%rsi\nlea -0x50(%rbp),%rax\nmov $0x0,%r8d\nmov %rdx,%rcx\nmov $0x1,%edx\nmov %rax,%rdi\ncallq 1180 \nmov %eax,-0x88(%rbp)\ncmpl $0x1,-0x88(%rbp)\njne 1349 \nlea -0x50(%rbp),%rax\nmov %rax,%rdi\ncallq 1120 \nmov -0x60(%rbp),%rax\nmov -0x58(%rbp),%rdx\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 1496 \ncallq 1130 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0A0h\nmov [rbp+var_98], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aAeW; \"[ae]\\\\w+\"\nmov [rbp+pattern], rax\nmov [rbp+ptr], 0\nmov dword ptr [rbp+var_58], 0\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+var_88], eax\ncmp [rbp+var_88], 0\njz short loc_133C\nmov rax, cs:__bss_start\nmov rcx, rax; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rax, aCouldNotCompil; \"Could not compile regex\\n\"\nmov rdi, rax; ptr\ncall _fwrite\nmov edi, 1; status\ncall _exit\nloc_133C:\nmov rax, [rbp+var_98]\nmov [rbp+string], rax\njmp loc_143F\nloc_134C:\ncmp [rbp+var_88], 0\njz short loc_138E\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nmov rax, cs:__bss_start\nmov rcx, rax; s\nmov edx, 13h; n\nmov esi, 1; size\nlea rax, aRegexMatchFail; \"Regex match failed\\n\"\nmov rdi, rax; ptr\ncall _fwrite\nmov edi, 1; status\ncall _exit\nloc_138E:\nmov eax, [rbp+pmatch.rm_so]\nmov [rbp+var_84], eax\nmov eax, [rbp+pmatch.rm_eo]\nmov [rbp+var_80], eax\nmov eax, [rbp+var_80]\nsub eax, [rbp+var_84]\nmov [rbp+var_7C], eax\nmov eax, [rbp+var_7C]\nadd eax, 1\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+dest], rax\nmov eax, [rbp+var_7C]\nmovsxd rdx, eax; n\nmov eax, [rbp+var_84]\nmovsxd rcx, eax\nmov rax, [rbp+string]\nadd rcx, rax\nmov rax, [rbp+dest]\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strncpy\nmov eax, [rbp+var_7C]\nmovsxd rdx, eax\nmov rax, [rbp+dest]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov eax, dword ptr [rbp+var_58]\nadd eax, 1\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nmov rsi, rdx; size\nmov rdi, rax; ptr\ncall _realloc\nmov [rbp+ptr], rax\nmov rax, [rbp+ptr]\nmov edx, dword ptr [rbp+var_58]\nmovsxd rdx, edx\nshl rdx, 3\nadd rdx, rax\nmov rax, [rbp+dest]\nmov [rdx], rax\nmov eax, dword ptr [rbp+var_58]\nadd eax, 1\nmov dword ptr [rbp+var_58], eax\nmov eax, [rbp+var_80]\ncdqe\nadd [rbp+string], rax\nloc_143F:\nlea rdx, [rbp+pmatch]\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov rcx, rdx; pmatch\nmov edx, 1; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_88], eax\ncmp [rbp+var_88], 1\njnz loc_134C\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nmov rax, [rbp+ptr]\nmov rdx, [rbp+var_58]\nmov rcx, [rbp+var_8]\nsub rcx, fs:28h\njz short locret_149C\ncall ___stack_chk_fail\nlocret_149C:\nleave\nretn", + "ida_pseudo": "void *__fastcall func0(const char *a1)\n{\n int i; // eax\n regmatch_t v3; // [rsp+1Ch] [rbp-84h]\n int v4; // [rsp+24h] [rbp-7Ch]\n char *string; // [rsp+28h] [rbp-78h]\n char *dest; // [rsp+38h] [rbp-68h]\n void *ptr; // [rsp+40h] [rbp-60h]\n int v8; // [rsp+48h] [rbp-58h]\n regex_t preg; // [rsp+50h] [rbp-50h] BYREF\n regmatch_t pmatch; // [rsp+90h] [rbp-10h] BYREF\n unsigned __int64 v11; // [rsp+98h] [rbp-8h]\n\n v11 = __readfsqword(0x28u);\n ptr = 0LL;\n v8 = 0;\n if ( regcomp(&preg, \"[ae]\\\\w+\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n exit(1);\n }\n string = (char *)a1;\n for ( i = regexec(&preg, a1, 1uLL, &pmatch, 0); i != 1; i = regexec(&preg, string, 1uLL, &pmatch, 0) )\n {\n if ( i )\n {\n regfree(&preg);\n fwrite(\"Regex match failed\\n\", 1uLL, 0x13uLL, _bss_start);\n exit(1);\n }\n v3 = pmatch;\n v4 = pmatch.rm_eo - pmatch.rm_so;\n dest = (char *)malloc(pmatch.rm_eo - pmatch.rm_so + 1);\n strncpy(dest, &string[v3.rm_so], v4);\n dest[v4] = 0;\n ptr = realloc(ptr, 8LL * (v8 + 1));\n *((_QWORD *)ptr + v8++) = dest;\n string += v3.rm_eo;\n }\n regfree(&preg);\n return ptr;\n}", + "ida_strip_asm": "sub_12A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0A0h\nmov [rbp+var_98], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aAeW; \"[ae]\\\\w+\"\nmov [rbp+pattern], rax\nmov [rbp+ptr], 0\nmov dword ptr [rbp+var_58], 0\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+var_88], eax\ncmp [rbp+var_88], 0\njz short loc_133C\nmov rax, cs:stderr\nmov rcx, rax; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rax, aCouldNotCompil; \"Could not compile regex\\n\"\nmov rdi, rax; ptr\ncall _fwrite\nmov edi, 1; status\ncall _exit\nloc_133C:\nmov rax, [rbp+var_98]\nmov [rbp+string], rax\njmp loc_143F\nloc_134C:\ncmp [rbp+var_88], 0\njz short loc_138E\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nmov rax, cs:stderr\nmov rcx, rax; s\nmov edx, 13h; n\nmov esi, 1; size\nlea rax, aRegexMatchFail; \"Regex match failed\\n\"\nmov rdi, rax; ptr\ncall _fwrite\nmov edi, 1; status\ncall _exit\nloc_138E:\nmov eax, [rbp+pmatch.rm_so]\nmov [rbp+var_84], eax\nmov eax, [rbp+pmatch.rm_eo]\nmov [rbp+var_80], eax\nmov eax, [rbp+var_80]\nsub eax, [rbp+var_84]\nmov [rbp+var_7C], eax\nmov eax, [rbp+var_7C]\nadd eax, 1\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+dest], rax\nmov eax, [rbp+var_7C]\nmovsxd rdx, eax; n\nmov eax, [rbp+var_84]\nmovsxd rcx, eax\nmov rax, [rbp+string]\nadd rcx, rax\nmov rax, [rbp+dest]\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strncpy\nmov eax, [rbp+var_7C]\nmovsxd rdx, eax\nmov rax, [rbp+dest]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov eax, dword ptr [rbp+var_58]\nadd eax, 1\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nmov rsi, rdx; size\nmov rdi, rax; ptr\ncall _realloc\nmov [rbp+ptr], rax\nmov rax, [rbp+ptr]\nmov edx, dword ptr [rbp+var_58]\nmovsxd rdx, edx\nshl rdx, 3\nadd rdx, rax\nmov rax, [rbp+dest]\nmov [rdx], rax\nmov eax, dword ptr [rbp+var_58]\nadd eax, 1\nmov dword ptr [rbp+var_58], eax\nmov eax, [rbp+var_80]\ncdqe\nadd [rbp+string], rax\nloc_143F:\nlea rdx, [rbp+pmatch]\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov rcx, rdx; pmatch\nmov edx, 1; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_88], eax\ncmp [rbp+var_88], 1\njnz loc_134C\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nmov rax, [rbp+ptr]\nmov rdx, [rbp+var_58]\nmov rcx, [rbp+var_8]\nsub rcx, fs:28h\njz short locret_149C\ncall ___stack_chk_fail\nlocret_149C:\nleave\nretn", + "ida_strip_pseudo": "void *__fastcall sub_12A9(const char *a1)\n{\n int i; // eax\n regmatch_t v3; // [rsp+1Ch] [rbp-84h]\n int v4; // [rsp+24h] [rbp-7Ch]\n char *string; // [rsp+28h] [rbp-78h]\n char *dest; // [rsp+38h] [rbp-68h]\n void *ptr; // [rsp+40h] [rbp-60h]\n int v8; // [rsp+48h] [rbp-58h]\n regex_t preg; // [rsp+50h] [rbp-50h] BYREF\n regmatch_t pmatch; // [rsp+90h] [rbp-10h] BYREF\n unsigned __int64 v11; // [rsp+98h] [rbp-8h]\n\n v11 = __readfsqword(0x28u);\n ptr = 0LL;\n v8 = 0;\n if ( regcomp(&preg, \"[ae]\\\\w+\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n exit(1);\n }\n string = (char *)a1;\n for ( i = regexec(&preg, a1, 1uLL, &pmatch, 0); i != 1; i = regexec(&preg, string, 1uLL, &pmatch, 0) )\n {\n if ( i )\n {\n regfree(&preg);\n fwrite(\"Regex match failed\\n\", 1uLL, 0x13uLL, stderr);\n exit(1);\n }\n v3 = pmatch;\n v4 = pmatch.rm_eo - pmatch.rm_so;\n dest = (char *)malloc(pmatch.rm_eo - pmatch.rm_so + 1);\n strncpy(dest, &string[v3.rm_so], v4);\n dest[v4] = 0;\n ptr = realloc(ptr, 8LL * (v8 + 1));\n *((_QWORD *)ptr + v8++) = dest;\n string += v3.rm_eo;\n }\n regfree(&preg);\n return ptr;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_12A9(const char *a1) {\n int i;\n regmatch_t v3;\n int v4;\n char *string;\n char *dest;\n void *ptr;\n int v8;\n regex_t preg;\n regmatch_t pmatch;\n unsigned long long v11;\n v11 = __readfsqword(40u);\n ptr = 0LL;\n v8 = 0;\n if (regcomp(&preg, \"[ae]\\\\w+\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n exit(1);\n }\n string = (char *)a1;\n for (i = regexec(&preg, a1, 1uLL, &pmatch, 0); i != 1;\n i = regexec(&preg, string, 1uLL, &pmatch, 0)) {\n if (i) {\n regfree(&preg);\n fwrite(\"Regex match failed\\n\", 1uLL, 19uLL, stderr);\n exit(1);\n }\n v3 = pmatch;\n v4 = pmatch.rm_eo - pmatch.rm_so;\n dest = (char *)malloc(pmatch.rm_eo - pmatch.rm_so + 1);\n strncpy(dest, &string[v3.rm_so], v4);\n dest[v4] = 0;\n ptr = realloc(ptr, 8LL * (v8 + 1));\n *((uint64_t *)ptr + v8++) = dest;\n string += v3.rm_eo;\n }\n regfree(&preg);\n return ptr;\n}", + "ida_pseudo_norm": "void *func0(const char *a1) {\n int i;\n regmatch_t v3;\n int v4;\n char *string;\n char *dest;\n void *ptr;\n int v8;\n regex_t preg;\n regmatch_t pmatch;\n unsigned long long v11;\n v11 = __readfsqword(40u);\n ptr = 0LL;\n v8 = 0;\n if (regcomp(&preg, \"[ae]\\\\w+\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n exit(1);\n }\n string = (char *)a1;\n for (i = regexec(&preg, a1, 1uLL, &pmatch, 0); i != 1;\n i = regexec(&preg, string, 1uLL, &pmatch, 0)) {\n if (i) {\n regfree(&preg);\n fwrite(\"Regex match failed\\n\", 1uLL, 19uLL, _bss_start);\n exit(1);\n }\n v3 = pmatch;\n v4 = pmatch.rm_eo - pmatch.rm_so;\n dest = (char *)malloc(pmatch.rm_eo - pmatch.rm_so + 1);\n strncpy(dest, &string[v3.rm_so], v4);\n dest[v4] = 0;\n ptr = realloc(ptr, 8LL * (v8 + 1));\n *((uint64_t *)ptr + v8++) = dest;\n string += v3.rm_eo;\n }\n regfree(&preg);\n return ptr;\n}" + }, + { + "index": 254, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char **matches;\n\n int count;\n\n} MatchList;\n\n\n\n", + "func": "MatchList func0(const char *text) {\n regex_t regex;\n regmatch_t pmatch[1];\n const char *pattern = \"[ae]\\\\w+\";\n int ret;\n MatchList list;\n list.matches = NULL;\n list.count = 0;\n ret = regcomp(®ex, pattern, REG_EXTENDED);\n if (ret) {\n fprintf(stderr, \"Could not compile regex\\n\");\n exit(1);\n }\n const char *p = text;\n while ((ret = regexec(®ex, p, 1, pmatch, 0)) != REG_NOMATCH) {\n if (ret) {\n regfree(®ex);\n fprintf(stderr, \"Regex match failed\\n\");\n exit(1);\n }\n int start = pmatch[0].rm_so;\n int end = pmatch[0].rm_eo;\n int len = end - start;\n char *match = (char *)malloc(len + 1);\n strncpy(match, p + start, len);\n match[len] = '\\0';\n list.matches =\n (char **)realloc(list.matches, sizeof(char *) * (list.count + 1));\n list.matches[list.count] = match;\n list.count++;\n p += end;\n }\n regfree(®ex);\n return list;\n}", + "test": "int main() {\n\n // Test case 1\n\n MatchList result1 = func0(\"python programe\");\n\n assert(result1.count == 1);\n\n assert(strcmp(result1.matches[0], \"ame\") == 0);\n\n for(int i = 0; i < result1.count; i++) {\n\n free(result1.matches[i]);\n\n }\n\n free(result1.matches);\n\n\n\n // Test case 2\n\n MatchList result2 = func0(\"python programe language\");\n\n assert(result2.count == 2);\n\n assert(strcmp(result2.matches[0], \"ame\") == 0);\n\n assert(strcmp(result2.matches[1], \"anguage\") == 0);\n\n for(int i = 0; i < result2.count; i++) {\n\n free(result2.matches[i]);\n\n }\n\n free(result2.matches);\n\n\n\n // Test case 3\n\n MatchList result3 = func0(\"assert statement\");\n\n assert(result3.count == 2);\n\n assert(strcmp(result3.matches[0], \"assert\") == 0);\n\n assert(strcmp(result3.matches[1], \"atement\") == 0);\n\n for(int i = 0; i < result3.count; i++) {\n\n free(result3.matches[i]);\n\n }\n\n free(result3.matches);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x68,%rsp\nmov %rdi,%r15\nmov %fs:0x28,%rax\nmov %rax,0x58(%rsp)\nxor %eax,%eax\nlea 0x10(%rsp),%rdi\nmov $0x1,%edx\nlea 0xd45(%rip),%rsi\ncallq 1140 \ntest %eax,%eax\njne 1374 \nmov $0x0,%ebp\nmovq $0x0,(%rsp)\nlea 0x50(%rsp),%rax\nmov %rax,0x8(%rsp)\nlea 0x10(%rsp),%rdi\nmov $0x0,%r8d\nmov 0x8(%rsp),%rcx\nmov $0x1,%edx\nmov %r15,%rsi\ncallq 1160 \ncmp $0x1,%eax\nje 13cc \ntest %eax,%eax\njne 139b \nmov 0x50(%rsp),%ebx\nmov 0x54(%rsp),%r14d\nmov %r14d,%r13d\nsub %ebx,%r13d\nlea 0x1(%r13),%edi\nmovslq %edi,%rdi\ncallq 1150 \nmov %rax,%r12\nmovslq %r13d,%r13\nmovslq %ebx,%rsi\nadd %r15,%rsi\nmov %r13,%rdx\nmov %rax,%rdi\ncallq 1100 \nmovb $0x0,(%r12,%r13,1)\nadd $0x1,%rbp\nlea 0x0(,%rbp,8),%rbx\nmov %rbx,%rsi\nmov (%rsp),%rdi\ncallq 1170 \nmov %rax,(%rsp)\nmov %r12,-0x8(%rax,%rbx,1)\nmovslq %r14d,%r14\nadd %r14,%r15\njmpq 12e3 \nmov 0x2ca5(%rip),%rcx\nmov $0x18,%edx\nmov $0x1,%esi\nlea 0xc80(%rip),%rdi\ncallq 1190 \nmov $0x1,%edi\ncallq 1180 \nlea 0x10(%rsp),%rdi\ncallq 1110 \nmov 0x2c74(%rip),%rcx\nmov $0x13,%edx\nmov $0x1,%esi\nlea 0xc68(%rip),%rdi\ncallq 1190 \nmov $0x1,%edi\ncallq 1180 \nlea 0x10(%rsp),%rdi\ncallq 1110 \nmov %ebp,%edx\nmov 0x58(%rsp),%rax\nxor %fs:0x28,%rax\njne 13fb \nmov (%rsp),%rax\nadd $0x68,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\ncallq 1120 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 78h\nmov r15, rdi\nmov rax, fs:28h\nmov [rsp+0A8h+var_40], rax\nxor eax, eax\nlea rdi, [rsp+0A8h+preg]; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"[ae]\\\\w+\"\ncall _regcomp\ntest eax, eax\njnz loc_13AD\nmov [rsp+0A8h+var_98], 0\nmov [rsp+0A8h+ptr], 0\nlea rax, [rsp+0A8h+var_48]\nmov [rsp+0A8h+pmatch], rax\nloc_1308:\nlea rdi, [rsp+0A8h+preg]; preg\nmov r8d, 0; eflags\nmov rcx, [rsp+0A8h+pmatch]; pmatch\nmov edx, 1; nmatch\nmov rsi, r15; string\ncall _regexec\ncmp eax, 1\njz loc_1405\ntest eax, eax\njnz loc_13D4\nmov ebx, [rsp+0A8h+var_48]\nmov r13d, [rsp+0A8h+var_44]\nmov r12d, r13d\nsub r12d, ebx\nlea r14d, [r12+1]\nmovsxd r14, r14d\nmov rdi, r14; size\ncall _malloc\nmov rbp, rax\nmovsxd r12, r12d\nmovsxd rsi, ebx\nadd rsi, r15\nmov rcx, r14\nmov rdx, r12\nmov rdi, rax\ncall ___strncpy_chk\nmov byte ptr [rbp+r12+0], 0\nmov rbx, [rsp+0A8h+var_98]\nadd rbx, 1\nlea r12, ds:0[rbx*8]\nmov rsi, r12; size\nmov rdi, [rsp+0A8h+ptr]; ptr\ncall _realloc\nmov [rsp+0A8h+ptr], rax\nmov [rax+r12-8], rbp\nmovsxd r13, r13d\nadd r15, r13\nmov [rsp+0A8h+var_98], rbx\njmp loc_1308\nloc_13AD:\nmov rcx, cs:__bss_start; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nmov edi, 1; status\ncall _exit\nloc_13D4:\nlea rdi, [rsp+0A8h+preg]; preg\ncall _regfree\nmov rcx, cs:__bss_start; s\nmov edx, 13h; n\nmov esi, 1; size\nlea rdi, aRegexMatchFail; \"Regex match failed\\n\"\ncall _fwrite\nmov edi, 1; status\ncall _exit\nloc_1405:\nlea rdi, [rsp+0A8h+preg]; preg\ncall _regfree\nmov edx, dword ptr [rsp+0A8h+var_98]\nmov rax, [rsp+0A8h+var_40]\nsub rax, fs:28h\njnz short loc_1437\nmov rax, [rsp+0A8h+ptr]\nadd rsp, 78h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1437:\ncall ___stack_chk_fail", + "ida_pseudo": "void *__fastcall func0(char *string)\n{\n int v2; // eax\n regoff_t rm_so; // ebx\n regoff_t rm_eo; // r13d\n int v5; // r12d\n _BYTE *v6; // rbp\n void *ptr; // [rsp+8h] [rbp-A0h]\n __int64 v9; // [rsp+10h] [rbp-98h]\n regex_t preg; // [rsp+20h] [rbp-88h] BYREF\n regmatch_t v11[9]; // [rsp+60h] [rbp-48h] BYREF\n\n v11[1] = (regmatch_t)__readfsqword(0x28u);\n if ( regcomp(&preg, \"[ae]\\\\w+\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n exit(1);\n }\n v9 = 0LL;\n ptr = 0LL;\n while ( 1 )\n {\n v2 = regexec(&preg, string, 1uLL, v11, 0);\n if ( v2 == 1 )\n break;\n if ( v2 )\n {\n regfree(&preg);\n fwrite(\"Regex match failed\\n\", 1uLL, 0x13uLL, _bss_start);\n exit(1);\n }\n rm_so = v11[0].rm_so;\n rm_eo = v11[0].rm_eo;\n v5 = v11[0].rm_eo - v11[0].rm_so;\n v6 = malloc(v11[0].rm_eo - v11[0].rm_so + 1);\n __strncpy_chk(v6, &string[rm_so], v5, v5 + 1);\n v6[v5] = 0;\n ptr = realloc(ptr, 8 * (v9 + 1));\n *((_QWORD *)ptr + v9) = v6;\n string += rm_eo;\n ++v9;\n }\n regfree(&preg);\n return ptr;\n}", + "ida_strip_asm": "sub_12A9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 78h\nmov r15, rdi\nmov rax, fs:28h\nmov [rsp+0A8h+var_40], rax\nxor eax, eax\nlea rdi, [rsp+0A8h+preg]; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"[ae]\\\\w+\"\ncall _regcomp\ntest eax, eax\njnz loc_13AD\nmov [rsp+0A8h+var_98], 0\nmov [rsp+0A8h+ptr], 0\nlea rax, [rsp+0A8h+var_48]\nmov [rsp+0A8h+pmatch], rax\nloc_1308:\nlea rdi, [rsp+0A8h+preg]; preg\nmov r8d, 0; eflags\nmov rcx, [rsp+0A8h+pmatch]; pmatch\nmov edx, 1; nmatch\nmov rsi, r15; string\ncall _regexec\ncmp eax, 1\njz loc_1405\ntest eax, eax\njnz loc_13D4\nmov ebx, [rsp+0A8h+var_48]\nmov r13d, [rsp+0A8h+var_44]\nmov r12d, r13d\nsub r12d, ebx\nlea r14d, [r12+1]\nmovsxd r14, r14d\nmov rdi, r14; size\ncall _malloc\nmov rbp, rax\nmovsxd r12, r12d\nmovsxd rsi, ebx\nadd rsi, r15\nmov rcx, r14\nmov rdx, r12\nmov rdi, rax\ncall ___strncpy_chk\nmov byte ptr [rbp+r12+0], 0\nmov rbx, [rsp+0A8h+var_98]\nadd rbx, 1\nlea r12, ds:0[rbx*8]\nmov rsi, r12; size\nmov rdi, [rsp+0A8h+ptr]; ptr\ncall _realloc\nmov [rsp+0A8h+ptr], rax\nmov [rax+r12-8], rbp\nmovsxd r13, r13d\nadd r15, r13\nmov [rsp+0A8h+var_98], rbx\njmp loc_1308\nloc_13AD:\nmov rcx, cs:stderr; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nmov edi, 1; status\ncall _exit\nloc_13D4:\nlea rdi, [rsp+0A8h+preg]; preg\ncall _regfree\nmov rcx, cs:stderr; s\nmov edx, 13h; n\nmov esi, 1; size\nlea rdi, aRegexMatchFail; \"Regex match failed\\n\"\ncall _fwrite\nmov edi, 1; status\ncall _exit\nloc_1405:\nlea rdi, [rsp+0A8h+preg]; preg\ncall _regfree\nmov edx, dword ptr [rsp+0A8h+var_98]\nmov rax, [rsp+0A8h+var_40]\nsub rax, fs:28h\njnz short loc_1437\nmov rax, [rsp+0A8h+ptr]\nadd rsp, 78h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1437:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "void *__fastcall sub_12A9(char *string)\n{\n int v2; // eax\n regoff_t rm_so; // ebx\n regoff_t rm_eo; // r13d\n int v5; // r12d\n _BYTE *v6; // rbp\n void *ptr; // [rsp+8h] [rbp-A0h]\n __int64 v9; // [rsp+10h] [rbp-98h]\n regex_t preg; // [rsp+20h] [rbp-88h] BYREF\n regmatch_t v11[9]; // [rsp+60h] [rbp-48h] BYREF\n\n v11[1] = (regmatch_t)__readfsqword(0x28u);\n if ( regcomp(&preg, \"[ae]\\\\w+\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n exit(1);\n }\n v9 = 0LL;\n ptr = 0LL;\n while ( 1 )\n {\n v2 = regexec(&preg, string, 1uLL, v11, 0);\n if ( v2 == 1 )\n break;\n if ( v2 )\n {\n regfree(&preg);\n fwrite(\"Regex match failed\\n\", 1uLL, 0x13uLL, stderr);\n exit(1);\n }\n rm_so = v11[0].rm_so;\n rm_eo = v11[0].rm_eo;\n v5 = v11[0].rm_eo - v11[0].rm_so;\n v6 = malloc(v11[0].rm_eo - v11[0].rm_so + 1);\n __strncpy_chk(v6, &string[rm_so], v5, v5 + 1);\n v6[v5] = 0;\n ptr = realloc(ptr, 8 * (v9 + 1));\n *((_QWORD *)ptr + v9) = v6;\n string += rm_eo;\n ++v9;\n }\n regfree(&preg);\n return ptr;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_12A9(char *string) {\n int v2;\n regoff_t rm_so;\n regoff_t rm_eo;\n int v5;\n uint8_t *v6;\n void *ptr;\n long long v9;\n regex_t preg;\n regmatch_t v11[9];\n v11[1] = (regmatch_t)__readfsqword(40u);\n if (regcomp(&preg, \"[ae]\\\\w+\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n exit(1);\n }\n v9 = 0LL;\n ptr = 0LL;\n while (1) {\n v2 = regexec(&preg, string, 1uLL, v11, 0);\n if (v2 == 1) break;\n if (v2) {\n regfree(&preg);\n fwrite(\"Regex match failed\\n\", 1uLL, 19uLL, stderr);\n exit(1);\n }\n rm_so = v11[0].rm_so;\n rm_eo = v11[0].rm_eo;\n v5 = v11[0].rm_eo - v11[0].rm_so;\n v6 = malloc(v11[0].rm_eo - v11[0].rm_so + 1);\n __strncpy_chk(v6, &string[rm_so], v5, v5 + 1);\n v6[v5] = 0;\n ptr = realloc(ptr, 8 * (v9 + 1));\n *((uint64_t *)ptr + v9) = v6;\n string += rm_eo;\n ++v9;\n }\n regfree(&preg);\n return ptr;\n}", + "ida_pseudo_norm": "void *func0(char *string) {\n int v2;\n regoff_t rm_so;\n regoff_t rm_eo;\n int v5;\n uint8_t *v6;\n void *ptr;\n long long v9;\n regex_t preg;\n regmatch_t v11[9];\n v11[1] = (regmatch_t)__readfsqword(40u);\n if (regcomp(&preg, \"[ae]\\\\w+\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n exit(1);\n }\n v9 = 0LL;\n ptr = 0LL;\n while (1) {\n v2 = regexec(&preg, string, 1uLL, v11, 0);\n if (v2 == 1) break;\n if (v2) {\n regfree(&preg);\n fwrite(\"Regex match failed\\n\", 1uLL, 19uLL, _bss_start);\n exit(1);\n }\n rm_so = v11[0].rm_so;\n rm_eo = v11[0].rm_eo;\n v5 = v11[0].rm_eo - v11[0].rm_so;\n v6 = malloc(v11[0].rm_eo - v11[0].rm_so + 1);\n __strncpy_chk(v6, &string[rm_so], v5, v5 + 1);\n v6[v5] = 0;\n ptr = realloc(ptr, 8 * (v9 + 1));\n *((uint64_t *)ptr + v9) = v6;\n string += rm_eo;\n ++v9;\n }\n regfree(&preg);\n return ptr;\n}" + }, + { + "index": 254, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char **matches;\n\n int count;\n\n} MatchList;\n\n\n\n", + "func": "MatchList func0(const char *text) {\n regex_t regex;\n regmatch_t pmatch[1];\n const char *pattern = \"[ae]\\\\w+\";\n int ret;\n MatchList list;\n list.matches = NULL;\n list.count = 0;\n ret = regcomp(®ex, pattern, REG_EXTENDED);\n if (ret) {\n fprintf(stderr, \"Could not compile regex\\n\");\n exit(1);\n }\n const char *p = text;\n while ((ret = regexec(®ex, p, 1, pmatch, 0)) != REG_NOMATCH) {\n if (ret) {\n regfree(®ex);\n fprintf(stderr, \"Regex match failed\\n\");\n exit(1);\n }\n int start = pmatch[0].rm_so;\n int end = pmatch[0].rm_eo;\n int len = end - start;\n char *match = (char *)malloc(len + 1);\n strncpy(match, p + start, len);\n match[len] = '\\0';\n list.matches =\n (char **)realloc(list.matches, sizeof(char *) * (list.count + 1));\n list.matches[list.count] = match;\n list.count++;\n p += end;\n }\n regfree(®ex);\n return list;\n}", + "test": "int main() {\n\n // Test case 1\n\n MatchList result1 = func0(\"python programe\");\n\n assert(result1.count == 1);\n\n assert(strcmp(result1.matches[0], \"ame\") == 0);\n\n for(int i = 0; i < result1.count; i++) {\n\n free(result1.matches[i]);\n\n }\n\n free(result1.matches);\n\n\n\n // Test case 2\n\n MatchList result2 = func0(\"python programe language\");\n\n assert(result2.count == 2);\n\n assert(strcmp(result2.matches[0], \"ame\") == 0);\n\n assert(strcmp(result2.matches[1], \"anguage\") == 0);\n\n for(int i = 0; i < result2.count; i++) {\n\n free(result2.matches[i]);\n\n }\n\n free(result2.matches);\n\n\n\n // Test case 3\n\n MatchList result3 = func0(\"assert statement\");\n\n assert(result3.count == 2);\n\n assert(strcmp(result3.matches[0], \"assert\") == 0);\n\n assert(strcmp(result3.matches[1], \"atement\") == 0);\n\n for(int i = 0; i < result3.count; i++) {\n\n free(result3.matches[i]);\n\n }\n\n free(result3.matches);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmov $0x1,%edx\nlea 0xb32(%rip),%rsi\npush %r14\npush %r13\nmov %rdi,%r13\npush %r12\npush %rbp\npush %rbx\nsub $0x78,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x68(%rsp)\nxor %eax,%eax\nlea 0x20(%rsp),%rdi\nmov %rdi,0x10(%rsp)\ncallq 1140 \ntest %eax,%eax\njne 1611 \nlea 0x60(%rsp),%rax\nxor %ebp,%ebp\nxor %r12d,%r12d\nmov %rax,0x18(%rsp)\njmp 158f \nnopl 0x0(%rax)\ntest %eax,%eax\njne 15e0 \nmov 0x64(%rsp),%r15d\nmov 0x60(%rsp),%ebx\nadd $0x1,%rbp\nmov %r15d,%edx\nsub %ebx,%edx\nlea 0x1(%rdx),%edi\nmov %edx,0x8(%rsp)\nmovslq %edi,%rdi\ncallq 1150 \nmovslq 0x8(%rsp),%rdx\nmovslq %ebx,%rsi\nlea 0x0(,%rbp,8),%rbx\nadd %r13,%rsi\nmov %rax,%rdi\nmov %rax,%r14\nmov %rdx,0x8(%rsp)\ncallq 1100 \nmov 0x8(%rsp),%rdx\nmov %r12,%rdi\nmov %rbx,%rsi\nmovb $0x0,(%r14,%rdx,1)\ncallq 1170 \nmovslq %r15d,%r8\nmov %r14,-0x8(%rax,%rbx,1)\nmov %rax,%r12\nadd %r8,%r13\nmov 0x18(%rsp),%rcx\nmov 0x10(%rsp),%rdi\nxor %r8d,%r8d\nmov %r13,%rsi\nmov $0x1,%edx\ncallq 1160 \ncmp $0x1,%eax\njne 1520 \nmov 0x10(%rsp),%rdi\ncallq 1110 \nmov %ebp,%edx\nmov 0x68(%rsp),%rax\nxor %fs:0x28,%rax\njne 1638 \nadd $0x78,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmov 0x10(%rsp),%rdi\ncallq 1110 \nmov $0x13,%edx\nmov $0x1,%esi\nmov 0x2a25(%rip),%rcx\nlea 0xa23(%rip),%rdi\ncallq 1190 \nmov $0x1,%edi\ncallq 1180 \nmov 0x2a08(%rip),%rcx\nmov $0x18,%edx\nmov $0x1,%esi\nlea 0x9e3(%rip),%rdi\ncallq 1190 \nmov $0x1,%edi\ncallq 1180 \ncallq 1120 <__stack_chk_fail@plt>\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov edx, 1; cflags\nlea rsi, pattern; \"[ae]\\\\w+\"\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 78h\nmov rax, fs:28h\nmov [rsp+0A8h+var_40], rax\nxor eax, eax\nlea rdi, [rsp+0A8h+preg]; preg\nmov [rsp+0A8h+var_98], rdi\ncall _regcomp\ntest eax, eax\njnz loc_1614\nlea rax, [rsp+0A8h+var_48]\nxor r13d, r13d\nxor ebp, ebp\nmov [rsp+0A8h+pmatch], rax\njmp short loc_1591\nloc_1520:\ntest eax, eax\njnz loc_15E3\nmov r15d, [rsp+0A8h+var_44]\nmov esi, [rsp+0A8h+var_48]\nmov r14d, r15d\nmov [rsp+0A8h+var_9C], esi\nsub r14d, esi\nlea ecx, [r14+1]\nmovsxd r14, r14d\nmovsxd rcx, ecx\nmov rdi, rcx; size\nmov [rsp+0A8h+var_A8], rcx\ncall _malloc\nmovsxd rsi, [rsp+0A8h+var_9C]\nmov rcx, [rsp+0A8h+var_A8]\nmov rdx, r14\nmov rbx, rax\nmov rdi, rax\nadd rsi, r12\ncall ___strncpy_chk\nmov byte ptr [rbx+r14], 0\nlea rsi, ds:8[r13*8]; size\nmov rdi, rbp; ptr\ncall _realloc\nmovsxd r8, r15d\nmov [rax+r13*8], rbx\nmov rbp, rax\nadd r12, r8\nadd r13, 1\nloc_1591:\nmov rcx, [rsp+0A8h+pmatch]; pmatch\nmov rdi, [rsp+0A8h+var_98]; preg\nxor r8d, r8d; eflags\nmov rsi, r12; string\nmov edx, 1; nmatch\ncall _regexec\ncmp eax, 1\njnz loc_1520\nmov rdi, [rsp+0A8h+var_98]; preg\ncall _regfree\nmov edx, r13d\nmov rax, [rsp+0A8h+var_40]\nsub rax, fs:28h\njnz short loc_163B\nadd rsp, 78h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15E3:\nmov rdi, [rsp+0A8h+var_98]; preg\ncall _regfree\nmov edx, 13h; n\nmov esi, 1; size\nmov rcx, cs:__bss_start; s\nlea rdi, aRegexMatchFail; \"Regex match failed\\n\"\ncall _fwrite\nmov edi, 1; status\ncall _exit\nloc_1614:\nmov rcx, cs:__bss_start; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nmov edi, 1; status\ncall _exit\nloc_163B:\ncall ___stack_chk_fail", + "ida_pseudo": "void *__fastcall func0(char *string)\n{\n const char *v1; // r12\n __int64 v2; // r13\n void *v3; // rbp\n int i; // eax\n regoff_t rm_eo; // r15d\n __int64 v6; // r14\n _BYTE *v7; // rbx\n _QWORD *v8; // rax\n size_t v10; // [rsp+0h] [rbp-A8h]\n regoff_t rm_so; // [rsp+Ch] [rbp-9Ch]\n regex_t preg; // [rsp+20h] [rbp-88h] BYREF\n regmatch_t v13[9]; // [rsp+60h] [rbp-48h] BYREF\n\n v1 = string;\n v13[1] = (regmatch_t)__readfsqword(0x28u);\n if ( regcomp(&preg, \"[ae]\\\\w+\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n exit(1);\n }\n v2 = 0LL;\n v3 = 0LL;\n for ( i = regexec(&preg, string, 1uLL, v13, 0); i != 1; i = regexec(&preg, v1, 1uLL, v13, 0) )\n {\n if ( i )\n {\n regfree(&preg);\n fwrite(\"Regex match failed\\n\", 1uLL, 0x13uLL, _bss_start);\n exit(1);\n }\n rm_eo = v13[0].rm_eo;\n rm_so = v13[0].rm_so;\n v6 = v13[0].rm_eo - v13[0].rm_so;\n v10 = v13[0].rm_eo - v13[0].rm_so + 1;\n v7 = malloc(v10);\n __strncpy_chk(v7, &v1[rm_so], v6, v10);\n v7[v6] = 0;\n v8 = realloc(v3, 8 * v2 + 8);\n v8[v2] = v7;\n v3 = v8;\n v1 += rm_eo;\n ++v2;\n }\n regfree(&preg);\n return v3;\n}", + "ida_strip_asm": "sub_14C0:\nendbr64\npush r15\nmov edx, 1; cflags\nlea rsi, pattern; \"[ae]\\\\w+\"\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 78h\nmov rax, fs:28h\nmov [rsp+0A8h+var_40], rax\nxor eax, eax\nlea rdi, [rsp+0A8h+preg]; preg\nmov [rsp+0A8h+var_98], rdi\ncall _regcomp\ntest eax, eax\njnz loc_1614\nlea rax, [rsp+0A8h+var_48]\nxor r13d, r13d\nxor ebp, ebp\nmov [rsp+0A8h+pmatch], rax\njmp short loc_1591\nloc_1520:\ntest eax, eax\njnz loc_15E3\nmov r15d, [rsp+0A8h+var_44]\nmov esi, [rsp+0A8h+var_48]\nmov r14d, r15d\nmov [rsp+0A8h+var_9C], esi\nsub r14d, esi\nlea ecx, [r14+1]\nmovsxd r14, r14d\nmovsxd rcx, ecx\nmov rdi, rcx; size\nmov [rsp+0A8h+var_A8], rcx\ncall _malloc\nmovsxd rsi, [rsp+0A8h+var_9C]\nmov rcx, [rsp+0A8h+var_A8]\nmov rdx, r14\nmov rbx, rax\nmov rdi, rax\nadd rsi, r12\ncall ___strncpy_chk\nmov byte ptr [rbx+r14], 0\nlea rsi, ds:8[r13*8]; size\nmov rdi, rbp; ptr\ncall _realloc\nmovsxd r8, r15d\nmov [rax+r13*8], rbx\nmov rbp, rax\nadd r12, r8\nadd r13, 1\nloc_1591:\nmov rcx, [rsp+0A8h+pmatch]; pmatch\nmov rdi, [rsp+0A8h+var_98]; preg\nxor r8d, r8d; eflags\nmov rsi, r12; string\nmov edx, 1; nmatch\ncall _regexec\ncmp eax, 1\njnz loc_1520\nmov rdi, [rsp+0A8h+var_98]; preg\ncall _regfree\nmov edx, r13d\nmov rax, [rsp+0A8h+var_40]\nsub rax, fs:28h\njnz short loc_163B\nadd rsp, 78h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15E3:\nmov rdi, [rsp+0A8h+var_98]; preg\ncall _regfree\nmov edx, 13h; n\nmov esi, 1; size\nmov rcx, cs:stderr; s\nlea rdi, aRegexMatchFail; \"Regex match failed\\n\"\ncall _fwrite\nmov edi, 1; status\ncall _exit\nloc_1614:\nmov rcx, cs:stderr; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nmov edi, 1; status\ncall _exit\nloc_163B:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "void *__fastcall sub_14C0(char *string)\n{\n const char *v1; // r12\n __int64 v2; // r13\n void *v3; // rbp\n int i; // eax\n regoff_t rm_eo; // r15d\n __int64 v6; // r14\n _BYTE *v7; // rbx\n _QWORD *v8; // rax\n size_t v10; // [rsp+0h] [rbp-A8h]\n regoff_t rm_so; // [rsp+Ch] [rbp-9Ch]\n regex_t preg; // [rsp+20h] [rbp-88h] BYREF\n regmatch_t v13[9]; // [rsp+60h] [rbp-48h] BYREF\n\n v1 = string;\n v13[1] = (regmatch_t)__readfsqword(0x28u);\n if ( regcomp(&preg, \"[ae]\\\\w+\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n exit(1);\n }\n v2 = 0LL;\n v3 = 0LL;\n for ( i = regexec(&preg, string, 1uLL, v13, 0); i != 1; i = regexec(&preg, v1, 1uLL, v13, 0) )\n {\n if ( i )\n {\n regfree(&preg);\n fwrite(\"Regex match failed\\n\", 1uLL, 0x13uLL, stderr);\n exit(1);\n }\n rm_eo = v13[0].rm_eo;\n rm_so = v13[0].rm_so;\n v6 = v13[0].rm_eo - v13[0].rm_so;\n v10 = v13[0].rm_eo - v13[0].rm_so + 1;\n v7 = malloc(v10);\n __strncpy_chk(v7, &v1[rm_so], v6, v10);\n v7[v6] = 0;\n v8 = realloc(v3, 8 * v2 + 8);\n v8[v2] = v7;\n v3 = v8;\n v1 += rm_eo;\n ++v2;\n }\n regfree(&preg);\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_14C0(char *string) {\n const char *v1;\n long long v2;\n void *v3;\n int i;\n regoff_t rm_eo;\n long long v6;\n uint8_t *v7;\n uint64_t *v8;\n unsigned int v10;\n regoff_t rm_so;\n regex_t preg;\n regmatch_t v13[9];\n v1 = string;\n v13[1] = (regmatch_t)__readfsqword(40u);\n if (regcomp(&preg, \"[ae]\\\\w+\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n exit(1);\n }\n v2 = 0LL;\n v3 = 0LL;\n for (i = regexec(&preg, string, 1uLL, v13, 0); i != 1;\n i = regexec(&preg, v1, 1uLL, v13, 0)) {\n if (i) {\n regfree(&preg);\n fwrite(\"Regex match failed\\n\", 1uLL, 19uLL, stderr);\n exit(1);\n }\n rm_eo = v13[0].rm_eo;\n rm_so = v13[0].rm_so;\n v6 = v13[0].rm_eo - v13[0].rm_so;\n v10 = v13[0].rm_eo - v13[0].rm_so + 1;\n v7 = malloc(v10);\n __strncpy_chk(v7, &v1[rm_so], v6, v10);\n v7[v6] = 0;\n v8 = realloc(v3, 8 * v2 + 8);\n v8[v2] = v7;\n v3 = v8;\n v1 += rm_eo;\n ++v2;\n }\n regfree(&preg);\n return v3;\n}", + "ida_pseudo_norm": "void *func0(char *string) {\n const char *v1;\n long long v2;\n void *v3;\n int i;\n regoff_t rm_eo;\n long long v6;\n uint8_t *v7;\n uint64_t *v8;\n unsigned int v10;\n regoff_t rm_so;\n regex_t preg;\n regmatch_t v13[9];\n v1 = string;\n v13[1] = (regmatch_t)__readfsqword(40u);\n if (regcomp(&preg, \"[ae]\\\\w+\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n exit(1);\n }\n v2 = 0LL;\n v3 = 0LL;\n for (i = regexec(&preg, string, 1uLL, v13, 0); i != 1;\n i = regexec(&preg, v1, 1uLL, v13, 0)) {\n if (i) {\n regfree(&preg);\n fwrite(\"Regex match failed\\n\", 1uLL, 19uLL, _bss_start);\n exit(1);\n }\n rm_eo = v13[0].rm_eo;\n rm_so = v13[0].rm_so;\n v6 = v13[0].rm_eo - v13[0].rm_so;\n v10 = v13[0].rm_eo - v13[0].rm_so + 1;\n v7 = malloc(v10);\n __strncpy_chk(v7, &v1[rm_so], v6, v10);\n v7[v6] = 0;\n v8 = realloc(v3, 8 * v2 + 8);\n v8[v2] = v7;\n v3 = v8;\n v1 += rm_eo;\n ++v2;\n }\n regfree(&preg);\n return v3;\n}" + }, + { + "index": 254, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char **matches;\n\n int count;\n\n} MatchList;\n\n\n\n", + "func": "MatchList func0(const char *text) {\n regex_t regex;\n regmatch_t pmatch[1];\n const char *pattern = \"[ae]\\\\w+\";\n int ret;\n MatchList list;\n list.matches = NULL;\n list.count = 0;\n ret = regcomp(®ex, pattern, REG_EXTENDED);\n if (ret) {\n fprintf(stderr, \"Could not compile regex\\n\");\n exit(1);\n }\n const char *p = text;\n while ((ret = regexec(®ex, p, 1, pmatch, 0)) != REG_NOMATCH) {\n if (ret) {\n regfree(®ex);\n fprintf(stderr, \"Regex match failed\\n\");\n exit(1);\n }\n int start = pmatch[0].rm_so;\n int end = pmatch[0].rm_eo;\n int len = end - start;\n char *match = (char *)malloc(len + 1);\n strncpy(match, p + start, len);\n match[len] = '\\0';\n list.matches =\n (char **)realloc(list.matches, sizeof(char *) * (list.count + 1));\n list.matches[list.count] = match;\n list.count++;\n p += end;\n }\n regfree(®ex);\n return list;\n}", + "test": "int main() {\n\n // Test case 1\n\n MatchList result1 = func0(\"python programe\");\n\n assert(result1.count == 1);\n\n assert(strcmp(result1.matches[0], \"ame\") == 0);\n\n for(int i = 0; i < result1.count; i++) {\n\n free(result1.matches[i]);\n\n }\n\n free(result1.matches);\n\n\n\n // Test case 2\n\n MatchList result2 = func0(\"python programe language\");\n\n assert(result2.count == 2);\n\n assert(strcmp(result2.matches[0], \"ame\") == 0);\n\n assert(strcmp(result2.matches[1], \"anguage\") == 0);\n\n for(int i = 0; i < result2.count; i++) {\n\n free(result2.matches[i]);\n\n }\n\n free(result2.matches);\n\n\n\n // Test case 3\n\n MatchList result3 = func0(\"assert statement\");\n\n assert(result3.count == 2);\n\n assert(strcmp(result3.matches[0], \"assert\") == 0);\n\n assert(strcmp(result3.matches[1], \"atement\") == 0);\n\n for(int i = 0; i < result3.count; i++) {\n\n free(result3.matches[i]);\n\n }\n\n free(result3.matches);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmov $0x1,%edx\nlea 0xb32(%rip),%rsi\npush %r14\npush %r13\nmov %rdi,%r13\npush %r12\npush %rbp\npush %rbx\nsub $0x78,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x68(%rsp)\nxor %eax,%eax\nlea 0x20(%rsp),%rdi\nmov %rdi,0x10(%rsp)\ncallq 1140 \ntest %eax,%eax\njne 1611 \nlea 0x60(%rsp),%rax\nxor %ebp,%ebp\nxor %r12d,%r12d\nmov %rax,0x18(%rsp)\njmp 158f \nnopl 0x0(%rax)\ntest %eax,%eax\njne 15e0 \nmov 0x64(%rsp),%r15d\nmov 0x60(%rsp),%ebx\nadd $0x1,%rbp\nmov %r15d,%edx\nsub %ebx,%edx\nlea 0x1(%rdx),%edi\nmov %edx,0x8(%rsp)\nmovslq %edi,%rdi\ncallq 1150 \nmovslq 0x8(%rsp),%rdx\nmovslq %ebx,%rsi\nlea 0x0(,%rbp,8),%rbx\nadd %r13,%rsi\nmov %rax,%rdi\nmov %rax,%r14\nmov %rdx,0x8(%rsp)\ncallq 1100 \nmov 0x8(%rsp),%rdx\nmov %r12,%rdi\nmov %rbx,%rsi\nmovb $0x0,(%r14,%rdx,1)\ncallq 1170 \nmovslq %r15d,%r8\nmov %r14,-0x8(%rax,%rbx,1)\nmov %rax,%r12\nadd %r8,%r13\nmov 0x18(%rsp),%rcx\nmov 0x10(%rsp),%rdi\nxor %r8d,%r8d\nmov %r13,%rsi\nmov $0x1,%edx\ncallq 1160 \ncmp $0x1,%eax\njne 1520 \nmov 0x10(%rsp),%rdi\ncallq 1110 \nmov %ebp,%edx\nmov 0x68(%rsp),%rax\nxor %fs:0x28,%rax\njne 1638 \nadd $0x78,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmov 0x10(%rsp),%rdi\ncallq 1110 \nmov $0x13,%edx\nmov $0x1,%esi\nmov 0x2a25(%rip),%rcx\nlea 0xa23(%rip),%rdi\ncallq 1190 \nmov $0x1,%edi\ncallq 1180 \nmov 0x2a08(%rip),%rcx\nmov $0x18,%edx\nmov $0x1,%esi\nlea 0x9e3(%rip),%rdi\ncallq 1190 \nmov $0x1,%edi\ncallq 1180 \ncallq 1120 <__stack_chk_fail@plt>\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov edx, 1; cflags\nlea rsi, pattern; \"[ae]\\\\w+\"\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 78h\nmov rax, fs:28h\nmov [rsp+0A8h+var_40], rax\nxor eax, eax\nlea rdi, [rsp+0A8h+preg]; preg\nmov [rsp+0A8h+var_98], rdi\ncall _regcomp\ntest eax, eax\njnz loc_1614\nlea rax, [rsp+0A8h+var_48]\nxor r13d, r13d\nxor ebp, ebp\nmov [rsp+0A8h+pmatch], rax\njmp short loc_1591\nloc_1520:\ntest eax, eax\njnz loc_15E3\nmov r15d, [rsp+0A8h+var_44]\nmov esi, [rsp+0A8h+var_48]\nmov r14d, r15d\nmov [rsp+0A8h+var_9C], esi\nsub r14d, esi\nlea ecx, [r14+1]\nmovsxd r14, r14d\nmovsxd rcx, ecx\nmov rdi, rcx; size\nmov [rsp+0A8h+var_A8], rcx\ncall _malloc\nmovsxd rsi, [rsp+0A8h+var_9C]\nmov rcx, [rsp+0A8h+var_A8]\nmov rdx, r14\nmov rbx, rax\nmov rdi, rax\nadd rsi, r12\ncall ___strncpy_chk\nmov byte ptr [rbx+r14], 0\nlea rsi, ds:8[r13*8]; size\nmov rdi, rbp; ptr\ncall _realloc\nmovsxd r8, r15d\nmov [rax+r13*8], rbx\nmov rbp, rax\nadd r12, r8\nadd r13, 1\nloc_1591:\nmov rcx, [rsp+0A8h+pmatch]; pmatch\nmov rdi, [rsp+0A8h+var_98]; preg\nxor r8d, r8d; eflags\nmov rsi, r12; string\nmov edx, 1; nmatch\ncall _regexec\ncmp eax, 1\njnz loc_1520\nmov rdi, [rsp+0A8h+var_98]; preg\ncall _regfree\nmov edx, r13d\nmov rax, [rsp+0A8h+var_40]\nsub rax, fs:28h\njnz short loc_163B\nadd rsp, 78h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15E3:\nmov rdi, [rsp+0A8h+var_98]; preg\ncall _regfree\nmov edx, 13h; n\nmov esi, 1; size\nmov rcx, cs:__bss_start; s\nlea rdi, aRegexMatchFail; \"Regex match failed\\n\"\ncall _fwrite\nmov edi, 1; status\ncall _exit\nloc_1614:\nmov rcx, cs:__bss_start; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nmov edi, 1; status\ncall _exit\nloc_163B:\ncall ___stack_chk_fail", + "ida_pseudo": "void *__fastcall func0(char *string)\n{\n const char *v1; // r12\n __int64 v2; // r13\n void *v3; // rbp\n int i; // eax\n regoff_t rm_eo; // r15d\n __int64 v6; // r14\n _BYTE *v7; // rbx\n _QWORD *v8; // rax\n size_t v10; // [rsp+0h] [rbp-A8h]\n regoff_t rm_so; // [rsp+Ch] [rbp-9Ch]\n regex_t preg; // [rsp+20h] [rbp-88h] BYREF\n regmatch_t v13[9]; // [rsp+60h] [rbp-48h] BYREF\n\n v1 = string;\n v13[1] = (regmatch_t)__readfsqword(0x28u);\n if ( regcomp(&preg, \"[ae]\\\\w+\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n exit(1);\n }\n v2 = 0LL;\n v3 = 0LL;\n for ( i = regexec(&preg, string, 1uLL, v13, 0); i != 1; i = regexec(&preg, v1, 1uLL, v13, 0) )\n {\n if ( i )\n {\n regfree(&preg);\n fwrite(\"Regex match failed\\n\", 1uLL, 0x13uLL, _bss_start);\n exit(1);\n }\n rm_eo = v13[0].rm_eo;\n rm_so = v13[0].rm_so;\n v6 = v13[0].rm_eo - v13[0].rm_so;\n v10 = v13[0].rm_eo - v13[0].rm_so + 1;\n v7 = malloc(v10);\n __strncpy_chk(v7, &v1[rm_so], v6, v10);\n v7[v6] = 0;\n v8 = realloc(v3, 8 * v2 + 8);\n v8[v2] = v7;\n v3 = v8;\n v1 += rm_eo;\n ++v2;\n }\n regfree(&preg);\n return v3;\n}", + "ida_strip_asm": "sub_14C0:\nendbr64\npush r15\nmov edx, 1; cflags\nlea rsi, pattern; \"[ae]\\\\w+\"\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 78h\nmov rax, fs:28h\nmov [rsp+0A8h+var_40], rax\nxor eax, eax\nlea rdi, [rsp+0A8h+preg]; preg\nmov [rsp+0A8h+var_98], rdi\ncall _regcomp\ntest eax, eax\njnz loc_1614\nlea rax, [rsp+0A8h+var_48]\nxor r13d, r13d\nxor ebp, ebp\nmov [rsp+0A8h+pmatch], rax\njmp short loc_1591\nloc_1520:\ntest eax, eax\njnz loc_15E3\nmov r15d, [rsp+0A8h+var_44]\nmov esi, [rsp+0A8h+var_48]\nmov r14d, r15d\nmov [rsp+0A8h+var_9C], esi\nsub r14d, esi\nlea ecx, [r14+1]\nmovsxd r14, r14d\nmovsxd rcx, ecx\nmov rdi, rcx; size\nmov [rsp+0A8h+var_A8], rcx\ncall _malloc\nmovsxd rsi, [rsp+0A8h+var_9C]\nmov rcx, [rsp+0A8h+var_A8]\nmov rdx, r14\nmov rbx, rax\nmov rdi, rax\nadd rsi, r12\ncall ___strncpy_chk\nmov byte ptr [rbx+r14], 0\nlea rsi, ds:8[r13*8]; size\nmov rdi, rbp; ptr\ncall _realloc\nmovsxd r8, r15d\nmov [rax+r13*8], rbx\nmov rbp, rax\nadd r12, r8\nadd r13, 1\nloc_1591:\nmov rcx, [rsp+0A8h+pmatch]; pmatch\nmov rdi, [rsp+0A8h+var_98]; preg\nxor r8d, r8d; eflags\nmov rsi, r12; string\nmov edx, 1; nmatch\ncall _regexec\ncmp eax, 1\njnz loc_1520\nmov rdi, [rsp+0A8h+var_98]; preg\ncall _regfree\nmov edx, r13d\nmov rax, [rsp+0A8h+var_40]\nsub rax, fs:28h\njnz short loc_163B\nadd rsp, 78h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15E3:\nmov rdi, [rsp+0A8h+var_98]; preg\ncall _regfree\nmov edx, 13h; n\nmov esi, 1; size\nmov rcx, cs:stderr; s\nlea rdi, aRegexMatchFail; \"Regex match failed\\n\"\ncall _fwrite\nmov edi, 1; status\ncall _exit\nloc_1614:\nmov rcx, cs:stderr; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nmov edi, 1; status\ncall _exit\nloc_163B:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "void *__fastcall sub_14C0(char *string)\n{\n const char *v1; // r12\n __int64 v2; // r13\n void *v3; // rbp\n int i; // eax\n regoff_t rm_eo; // r15d\n __int64 v6; // r14\n _BYTE *v7; // rbx\n _QWORD *v8; // rax\n size_t v10; // [rsp+0h] [rbp-A8h]\n regoff_t rm_so; // [rsp+Ch] [rbp-9Ch]\n regex_t preg; // [rsp+20h] [rbp-88h] BYREF\n regmatch_t v13[9]; // [rsp+60h] [rbp-48h] BYREF\n\n v1 = string;\n v13[1] = (regmatch_t)__readfsqword(0x28u);\n if ( regcomp(&preg, \"[ae]\\\\w+\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n exit(1);\n }\n v2 = 0LL;\n v3 = 0LL;\n for ( i = regexec(&preg, string, 1uLL, v13, 0); i != 1; i = regexec(&preg, v1, 1uLL, v13, 0) )\n {\n if ( i )\n {\n regfree(&preg);\n fwrite(\"Regex match failed\\n\", 1uLL, 0x13uLL, stderr);\n exit(1);\n }\n rm_eo = v13[0].rm_eo;\n rm_so = v13[0].rm_so;\n v6 = v13[0].rm_eo - v13[0].rm_so;\n v10 = v13[0].rm_eo - v13[0].rm_so + 1;\n v7 = malloc(v10);\n __strncpy_chk(v7, &v1[rm_so], v6, v10);\n v7[v6] = 0;\n v8 = realloc(v3, 8 * v2 + 8);\n v8[v2] = v7;\n v3 = v8;\n v1 += rm_eo;\n ++v2;\n }\n regfree(&preg);\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_14C0(char *string) {\n const char *v1;\n long long v2;\n void *v3;\n int i;\n regoff_t rm_eo;\n long long v6;\n uint8_t *v7;\n uint64_t *v8;\n unsigned int v10;\n regoff_t rm_so;\n regex_t preg;\n regmatch_t v13[9];\n v1 = string;\n v13[1] = (regmatch_t)__readfsqword(40u);\n if (regcomp(&preg, \"[ae]\\\\w+\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n exit(1);\n }\n v2 = 0LL;\n v3 = 0LL;\n for (i = regexec(&preg, string, 1uLL, v13, 0); i != 1;\n i = regexec(&preg, v1, 1uLL, v13, 0)) {\n if (i) {\n regfree(&preg);\n fwrite(\"Regex match failed\\n\", 1uLL, 19uLL, stderr);\n exit(1);\n }\n rm_eo = v13[0].rm_eo;\n rm_so = v13[0].rm_so;\n v6 = v13[0].rm_eo - v13[0].rm_so;\n v10 = v13[0].rm_eo - v13[0].rm_so + 1;\n v7 = malloc(v10);\n __strncpy_chk(v7, &v1[rm_so], v6, v10);\n v7[v6] = 0;\n v8 = realloc(v3, 8 * v2 + 8);\n v8[v2] = v7;\n v3 = v8;\n v1 += rm_eo;\n ++v2;\n }\n regfree(&preg);\n return v3;\n}", + "ida_pseudo_norm": "void *func0(char *string) {\n const char *v1;\n long long v2;\n void *v3;\n int i;\n regoff_t rm_eo;\n long long v6;\n uint8_t *v7;\n uint64_t *v8;\n unsigned int v10;\n regoff_t rm_so;\n regex_t preg;\n regmatch_t v13[9];\n v1 = string;\n v13[1] = (regmatch_t)__readfsqword(40u);\n if (regcomp(&preg, \"[ae]\\\\w+\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n exit(1);\n }\n v2 = 0LL;\n v3 = 0LL;\n for (i = regexec(&preg, string, 1uLL, v13, 0); i != 1;\n i = regexec(&preg, v1, 1uLL, v13, 0)) {\n if (i) {\n regfree(&preg);\n fwrite(\"Regex match failed\\n\", 1uLL, 19uLL, _bss_start);\n exit(1);\n }\n rm_eo = v13[0].rm_eo;\n rm_so = v13[0].rm_so;\n v6 = v13[0].rm_eo - v13[0].rm_so;\n v10 = v13[0].rm_eo - v13[0].rm_so + 1;\n v7 = malloc(v10);\n __strncpy_chk(v7, &v1[rm_so], v6, v10);\n v7[v6] = 0;\n v8 = realloc(v3, 8 * v2 + 8);\n v8[v2] = v7;\n v3 = v8;\n v1 += rm_eo;\n ++v2;\n }\n regfree(&preg);\n return v3;\n}" + }, + { + "index": 255, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(char *l[], int arr_size, int len, char *result[], int res_len) {\n if (len == 0) {\n for (int i = 0; i < res_len; i++) {\n printf(\"%s \", result[i]);\n }\n printf(\"\\n\");\n return;\n }\n for (int i = 0; i < arr_size; i++) {\n if (res_len == 0 || strcmp(l[i], result[res_len - 1]) >= 0) {\n result[res_len] = l[i];\n func0(l, arr_size, len - 1, result, res_len + 1);\n }\n }\n}", + "test": "int main() {\n\n char *colors[] = {\"Red\", \"Green\", \"Blue\"};\n\n int colors_size = 3;\n\n char *result1[1];\n\n char *result2[2];\n\n char *result3[3];\n\n\n\n printf(\"Combination with 1 color:\\n\");\n\n func0(colors, colors_size, 1, result1, 0);\n\n\n\n printf(\"Combination with 2 colors:\\n\");\n\n func0(colors, colors_size, 2, result2, 0);\n\n\n\n printf(\"Combination with 3 colors:\\n\");\n\n func0(colors, colors_size, 3, result3, 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmov %rcx,-0x28(%rbp)\nmov %r8d,-0x2c(%rbp)\ncmpl $0x0,-0x20(%rbp)\njne 123c \nmovl $0x0,-0x8(%rbp)\njmp 1225 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov %rax,%rsi\nlea 0xded(%rip),%rdi\nmov $0x0,%eax\ncallq 10c0 \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 11f6 \nmov $0xa,%edi\ncallq 1090 \njmpq 12f1 \nmovl $0x0,-0x4(%rbp)\njmpq 12e5 \ncmpl $0x0,-0x2c(%rbp)\nje 128b \nmov -0x2c(%rbp),%eax\ncltq\nshl $0x3,%rax\nlea -0x8(%rax),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rdx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10d0 \ntest %eax,%eax\njs 12e1 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0x2c(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x28(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%rax\nmov %rax,(%rdx)\nmov -0x2c(%rbp),%eax\nlea 0x1(%rax),%ecx\nmov -0x20(%rbp),%eax\nlea -0x1(%rax),%edi\nmov -0x28(%rbp),%rdx\nmov -0x1c(%rbp),%esi\nmov -0x18(%rbp),%rax\nmov %ecx,%r8d\nmov %rdx,%rcx\nmov %edi,%edx\nmov %rax,%rdi\ncallq 11c9 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1248 \nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_28], rcx\nmov [rbp+var_2C], r8d\ncmp [rbp+var_20], 0\njnz short loc_123F\nmov [rbp+var_8], 0\njmp short loc_1228\nloc_11F6:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov rsi, rax\nlea rax, format; \"%s \"\nmov rdi, rax; format\nmov eax, 0\ncall _printf\nadd [rbp+var_8], 1\nloc_1228:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_2C]\njl short loc_11F6\nmov edi, 0Ah; c\ncall _putchar\njmp locret_12F4\nloc_123F:\nmov [rbp+var_4], 0\njmp loc_12E8\nloc_124B:\ncmp [rbp+var_2C], 0\njz short loc_128E\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 3\nlea rdx, [rax-8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njs short loc_12E4\nloc_128E:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_2C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov rax, [rax]\nmov [rdx], rax\nmov eax, [rbp+var_2C]\nlea ecx, [rax+1]\nmov eax, [rbp+var_20]\nlea edi, [rax-1]\nmov rdx, [rbp+var_28]\nmov esi, [rbp+var_1C]\nmov rax, [rbp+var_18]\nmov r8d, ecx\nmov rcx, rdx\nmov edx, edi\nmov rdi, rax\ncall func0\nloc_12E4:\nadd [rbp+var_4], 1\nloc_12E8:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl loc_124B\nlocret_12F4:\nleave\nretn", + "ida_pseudo": "int __fastcall func0(__int64 a1, int a2, int a3, __int64 a4, int a5)\n{\n int result; // eax\n int j; // [rsp+28h] [rbp-8h]\n int i; // [rsp+2Ch] [rbp-4h]\n\n if ( a3 )\n {\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( i >= a2 )\n break;\n if ( !a5 || strcmp(*(const char **)(8LL * i + a1), *(const char **)(8LL * a5 - 8 + a4)) >= 0 )\n {\n *(_QWORD *)(8LL * a5 + a4) = *(_QWORD *)(8LL * i + a1);\n func0(a1, (unsigned int)a2, (unsigned int)(a3 - 1), a4, (unsigned int)(a5 + 1));\n }\n }\n }\n else\n {\n for ( j = 0; j < a5; ++j )\n printf(\"%s \", *(const char **)(8LL * j + a4));\n return putchar(10);\n }\n return result;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_28], rcx\nmov [rbp+var_2C], r8d\ncmp [rbp+var_20], 0\njnz short loc_123F\nmov [rbp+var_8], 0\njmp short loc_1228\nloc_11F6:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov rsi, rax\nlea rax, format; \"%s \"\nmov rdi, rax; format\nmov eax, 0\ncall _printf\nadd [rbp+var_8], 1\nloc_1228:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_2C]\njl short loc_11F6\nmov edi, 0Ah; c\ncall _putchar\njmp locret_12F4\nloc_123F:\nmov [rbp+var_4], 0\njmp loc_12E8\nloc_124B:\ncmp [rbp+var_2C], 0\njz short loc_128E\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 3\nlea rdx, [rax-8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njs short loc_12E4\nloc_128E:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_2C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov rax, [rax]\nmov [rdx], rax\nmov eax, [rbp+var_2C]\nlea ecx, [rax+1]\nmov eax, [rbp+var_20]\nlea edi, [rax-1]\nmov rdx, [rbp+var_28]\nmov esi, [rbp+var_1C]\nmov rax, [rbp+var_18]\nmov r8d, ecx\nmov rcx, rdx\nmov edx, edi\nmov rdi, rax\ncall sub_11C9\nloc_12E4:\nadd [rbp+var_4], 1\nloc_12E8:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl loc_124B\nlocret_12F4:\nleave\nretn", + "ida_strip_pseudo": "int __fastcall sub_11C9(__int64 a1, int a2, int a3, __int64 a4, int a5)\n{\n int result; // eax\n int j; // [rsp+28h] [rbp-8h]\n int i; // [rsp+2Ch] [rbp-4h]\n\n if ( a3 )\n {\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( i >= a2 )\n break;\n if ( !a5 || strcmp(*(const char **)(8LL * i + a1), *(const char **)(8LL * a5 - 8 + a4)) >= 0 )\n {\n *(_QWORD *)(8LL * a5 + a4) = *(_QWORD *)(8LL * i + a1);\n sub_11C9(a1, (unsigned int)a2, (unsigned int)(a3 - 1), a4, (unsigned int)(a5 + 1));\n }\n }\n }\n else\n {\n for ( j = 0; j < a5; ++j )\n printf(\"%s \", *(const char **)(8LL * j + a4));\n return putchar(10);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "int sub_11C9(long long a1, int a2, int a3, long long a4, int a5) {\n int result;\n int j;\n int i;\n if (a3) {\n for (i = 0;; ++i) {\n result = i;\n if (i >= a2) break;\n if (!a5 || strcmp(*(const char **)(8LL * i + a1),\n *(const char **)(8LL * a5 - 8 + a4)) >= 0) {\n *(uint64_t *)(8LL * a5 + a4) = *(uint64_t *)(8LL * i + a1);\n sub_11C9(a1, (unsigned int)a2, (unsigned int)(a3 - 1), a4,\n (unsigned int)(a5 + 1));\n }\n }\n } else {\n for (j = 0; j < a5; ++j) printf(\"%s \", *(const char **)(8LL * j + a4));\n return putchar(10);\n }\n return result;\n}", + "ida_pseudo_norm": "int func0(long long a1, int a2, int a3, long long a4, int a5) {\n int result;\n int j;\n int i;\n if (a3) {\n for (i = 0;; ++i) {\n result = i;\n if (i >= a2) break;\n if (!a5 || strcmp(*(const char **)(8LL * i + a1),\n *(const char **)(8LL * a5 - 8 + a4)) >= 0) {\n *(uint64_t *)(8LL * a5 + a4) = *(uint64_t *)(8LL * i + a1);\n func0(a1, (unsigned int)a2, (unsigned int)(a3 - 1), a4,\n (unsigned int)(a5 + 1));\n }\n }\n } else {\n for (j = 0; j < a5; ++j) printf(\"%s \", *(const char **)(8LL * j + a4));\n return putchar(10);\n }\n return result;\n}" + }, + { + "index": 255, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(char *l[], int arr_size, int len, char *result[], int res_len) {\n if (len == 0) {\n for (int i = 0; i < res_len; i++) {\n printf(\"%s \", result[i]);\n }\n printf(\"\\n\");\n return;\n }\n for (int i = 0; i < arr_size; i++) {\n if (res_len == 0 || strcmp(l[i], result[res_len - 1]) >= 0) {\n result[res_len] = l[i];\n func0(l, arr_size, len - 1, result, res_len + 1);\n }\n }\n}", + "test": "int main() {\n\n char *colors[] = {\"Red\", \"Green\", \"Blue\"};\n\n int colors_size = 3;\n\n char *result1[1];\n\n char *result2[2];\n\n char *result3[3];\n\n\n\n printf(\"Combination with 1 color:\\n\");\n\n func0(colors, colors_size, 1, result1, 0);\n\n\n\n printf(\"Combination with 2 colors:\\n\");\n\n func0(colors, colors_size, 2, result2, 0);\n\n\n\n printf(\"Combination with 3 colors:\\n\");\n\n func0(colors, colors_size, 3, result3, 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x28,%rsp\nmov %rdi,(%rsp)\nmov %rcx,%r12\nmov %r8d,%ebp\ntest %edx,%edx\nje 1226 \nmov %esi,%r13d\nmov %edx,%r14d\ntest %esi,%esi\njle 1266 \nmovslq %r8d,%rax\nshl $0x3,%rax\nlea -0x8(%rcx,%rax,1),%rsi\nmov %rsi,0x18(%rsp)\nadd %rcx,%rax\nmov %rax,0x8(%rsp)\nmov (%rsp),%rcx\nmov %rcx,%rbx\nlea -0x1(%r13),%eax\nlea 0x8(%rcx,%rax,8),%r15\nlea 0x1(%r8),%eax\nmov %eax,0x14(%rsp)\njmp 12a1 \ntest %r8d,%r8d\njle 125c \nmov %rcx,%rbx\nlea -0x1(%r8),%eax\nlea 0x8(%rcx,%rax,8),%r12\nlea 0xdc6(%rip),%rbp\nmov (%rbx),%rdx\nmov %rbp,%rsi\nmov $0x1,%edi\nmov $0x0,%eax\ncallq 10d0 <__printf_chk@plt>\nadd $0x8,%rbx\ncmp %r12,%rbx\njne 123e \nmov $0xa,%edi\ncallq 1090 \nadd $0x28,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmov (%rbx),%rax\nmov 0x8(%rsp),%rcx\nmov %rax,(%rcx)\nlea -0x1(%r14),%edx\nmov 0x14(%rsp),%r8d\nmov %r12,%rcx\nmov %r13d,%esi\nmov (%rsp),%rdi\ncallq 11c9 \nadd $0x8,%rbx\ncmp %r15,%rbx\nje 1266 \ntest %ebp,%ebp\nje 1275 \nmov 0x18(%rsp),%rax\nmov (%rax),%rsi\nmov (%rbx),%rdi\ncallq 10c0 \ntest %eax,%eax\njns 1275 \njmp 1298 \n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov [rsp+58h+var_50], rdi\nmov [rsp+58h+var_40], esi\nmov r12, rcx\nmov ebp, r8d\ntest edx, edx\njz short loc_1224\nmov r13d, edx\ntest esi, esi\njle short loc_1262\nmovsxd rax, r8d\nshl rax, 3\nlea r15, [rcx+rax-8]\nadd rax, rcx\nmov [rsp+58h+var_48], rax\nmov rcx, [rsp+58h+var_50]\nmov rbx, rcx\nmovsxd rax, [rsp+58h+var_40]\nlea r14, [rcx+rax*8]\nlea eax, [r8+1]\nmov [rsp+58h+var_3C], eax\njmp short loc_127A\nloc_1224:\ntest r8d, r8d\njle short loc_1258\nmov rbx, rcx\nmovsxd rbp, r8d\nlea r12, [rcx+rbp*8]\nlea rbp, unk_2004\nloc_123A:\nmov rdx, [rbx]\nmov rsi, rbp\nmov edi, 2\nmov eax, 0\ncall ___printf_chk\nadd rbx, 8\ncmp rbx, r12\njnz short loc_123A\nloc_1258:\nmov edi, 0Ah; c\ncall _putchar\nloc_1262:\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1271:\nadd rbx, 8\ncmp rbx, r14\njz short loc_1262\nloc_127A:\ntest ebp, ebp\njz short loc_128D\nmov rsi, [r15]; s2\nmov rdi, [rbx]; s1\ncall _strcmp\ntest eax, eax\njs short loc_1271\nloc_128D:\nmov rax, [rbx]\nmov rcx, [rsp+58h+var_48]\nmov [rcx], rax\nlea edx, [r13-1]\nmov r8d, [rsp+58h+var_3C]\nmov rcx, r12\nmov esi, [rsp+58h+var_40]\nmov rdi, [rsp+58h+var_50]\ncall func0\njmp short loc_1271", + "ida_pseudo": "void __fastcall func0(const char **a1, int a2, int a3, _QWORD *a4, int a5)\n{\n __int64 v8; // rax\n const char **v9; // r15\n const char **v10; // rbx\n _QWORD *v11; // rbx\n _QWORD *v12; // r12\n const char **v13; // [rsp+10h] [rbp-48h]\n unsigned int v14; // [rsp+1Ch] [rbp-3Ch]\n\n if ( a3 )\n {\n if ( a2 > 0 )\n {\n v8 = a5;\n v9 = (const char **)&a4[v8 - 1];\n v13 = (const char **)&a4[v8];\n v10 = a1;\n v14 = a5 + 1;\n do\n {\n if ( !a5 || strcmp(*v10, *v9) >= 0 )\n {\n *v13 = *v10;\n func0(a1, (unsigned int)a2, (unsigned int)(a3 - 1), a4, v14);\n }\n ++v10;\n }\n while ( v10 != &a1[a2] );\n }\n }\n else\n {\n if ( a5 > 0 )\n {\n v11 = a4;\n v12 = &a4[a5];\n do\n __printf_chk(2LL, &unk_2004, *v11++);\n while ( v11 != v12 );\n }\n putchar(10);\n }\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov [rsp+58h+var_50], rdi\nmov [rsp+58h+var_40], esi\nmov r12, rcx\nmov ebp, r8d\ntest edx, edx\njz short loc_1224\nmov r13d, edx\ntest esi, esi\njle short loc_1262\nmovsxd rax, r8d\nshl rax, 3\nlea r15, [rcx+rax-8]\nadd rax, rcx\nmov [rsp+58h+var_48], rax\nmov rcx, [rsp+58h+var_50]\nmov rbx, rcx\nmovsxd rax, [rsp+58h+var_40]\nlea r14, [rcx+rax*8]\nlea eax, [r8+1]\nmov [rsp+58h+var_3C], eax\njmp short loc_127A\nloc_1224:\ntest r8d, r8d\njle short loc_1258\nmov rbx, rcx\nmovsxd rbp, r8d\nlea r12, [rcx+rbp*8]\nlea rbp, unk_2004\nloc_123A:\nmov rdx, [rbx]\nmov rsi, rbp\nmov edi, 2\nmov eax, 0\ncall ___printf_chk\nadd rbx, 8\ncmp rbx, r12\njnz short loc_123A\nloc_1258:\nmov edi, 0Ah; c\ncall _putchar\nloc_1262:\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1271:\nadd rbx, 8\ncmp rbx, r14\njz short loc_1262\nloc_127A:\ntest ebp, ebp\njz short loc_128D\nmov rsi, [r15]; s2\nmov rdi, [rbx]; s1\ncall _strcmp\ntest eax, eax\njs short loc_1271\nloc_128D:\nmov rax, [rbx]\nmov rcx, [rsp+58h+var_48]\nmov [rcx], rax\nlea edx, [r13-1]\nmov r8d, [rsp+58h+var_3C]\nmov rcx, r12\nmov esi, [rsp+58h+var_40]\nmov rdi, [rsp+58h+var_50]\ncall sub_11C9\njmp short loc_1271", + "ida_strip_pseudo": "void __fastcall sub_11C9(const char **a1, int a2, int a3, _QWORD *a4, int a5)\n{\n __int64 v8; // rax\n const char **v9; // r15\n const char **v10; // rbx\n _QWORD *v11; // rbx\n _QWORD *v12; // r12\n const char **v13; // [rsp+10h] [rbp-48h]\n unsigned int v14; // [rsp+1Ch] [rbp-3Ch]\n\n if ( a3 )\n {\n if ( a2 > 0 )\n {\n v8 = a5;\n v9 = (const char **)&a4[v8 - 1];\n v13 = (const char **)&a4[v8];\n v10 = a1;\n v14 = a5 + 1;\n do\n {\n if ( !a5 || strcmp(*v10, *v9) >= 0 )\n {\n *v13 = *v10;\n sub_11C9(a1, (unsigned int)a2, (unsigned int)(a3 - 1), a4, v14);\n }\n ++v10;\n }\n while ( v10 != &a1[a2] );\n }\n }\n else\n {\n if ( a5 > 0 )\n {\n v11 = a4;\n v12 = &a4[a5];\n do\n __printf_chk(2LL, &unk_2004, *v11++);\n while ( v11 != v12 );\n }\n putchar(10);\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_11C9(const char **a1, int a2, int a3, uint64_t *a4, int a5) {\n long long v8;\n const char **v9;\n const char **v10;\n uint64_t *v11;\n uint64_t *v12;\n const char **v13;\n unsigned int v14;\n if (a3) {\n if (a2 > 0) {\n v8 = a5;\n v9 = (const char **)&a4[v8 - 1];\n v13 = (const char **)&a4[v8];\n v10 = a1;\n v14 = a5 + 1;\n do {\n if (!a5 || strcmp(*v10, *v9) >= 0) {\n *v13 = *v10;\n sub_11C9(a1, (unsigned int)a2, (unsigned int)(a3 - 1), a4, v14);\n }\n ++v10;\n } while (v10 != &a1[a2]);\n }\n } else {\n if (a5 > 0) {\n v11 = a4;\n v12 = &a4[a5];\n do\n __printf_chk(2LL, &unk_2004, *v11++);\n while (v11 != v12);\n }\n putchar(10);\n }\n}", + "ida_pseudo_norm": "void func0(const char **a1, int a2, int a3, uint64_t *a4, int a5) {\n long long v8;\n const char **v9;\n const char **v10;\n uint64_t *v11;\n uint64_t *v12;\n const char **v13;\n unsigned int v14;\n if (a3) {\n if (a2 > 0) {\n v8 = a5;\n v9 = (const char **)&a4[v8 - 1];\n v13 = (const char **)&a4[v8];\n v10 = a1;\n v14 = a5 + 1;\n do {\n if (!a5 || strcmp(*v10, *v9) >= 0) {\n *v13 = *v10;\n func0(a1, (unsigned int)a2, (unsigned int)(a3 - 1), a4, v14);\n }\n ++v10;\n } while (v10 != &a1[a2]);\n }\n } else {\n if (a5 > 0) {\n v11 = a4;\n v12 = &a4[a5];\n do\n __printf_chk(2LL, &unk_2004, *v11++);\n while (v11 != v12);\n }\n putchar(10);\n }\n}" + }, + { + "index": 255, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(char *l[], int arr_size, int len, char *result[], int res_len) {\n if (len == 0) {\n for (int i = 0; i < res_len; i++) {\n printf(\"%s \", result[i]);\n }\n printf(\"\\n\");\n return;\n }\n for (int i = 0; i < arr_size; i++) {\n if (res_len == 0 || strcmp(l[i], result[res_len - 1]) >= 0) {\n result[res_len] = l[i];\n func0(l, arr_size, len - 1, result, res_len + 1);\n }\n }\n}", + "test": "int main() {\n\n char *colors[] = {\"Red\", \"Green\", \"Blue\"};\n\n int colors_size = 3;\n\n char *result1[1];\n\n char *result2[2];\n\n char *result3[3];\n\n\n\n printf(\"Combination with 1 color:\\n\");\n\n func0(colors, colors_size, 1, result1, 0);\n\n\n\n printf(\"Combination with 2 colors:\\n\");\n\n func0(colors, colors_size, 2, result2, 0);\n\n\n\n printf(\"Combination with 3 colors:\\n\");\n\n func0(colors, colors_size, 3, result3, 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\nmov %r8d,%ebp\npush %rbx\nmov %rcx,%rbx\nsub $0x38,%rsp\ntest %edx,%edx\nje 1370 \nmov %esi,%r12d\ntest %esi,%esi\njle 1361 \nmovslq %r8d,%rax\nmov %rdi,%r13\nmov %edx,%r14d\nmov %rdi,%r15\nshl $0x3,%rax\nlea -0x8(%rcx,%rax,1),%rcx\nadd %rbx,%rax\nmov %rax,0x18(%rsp)\nlea -0x1(%rsi),%eax\nlea 0x8(%rdi,%rax,8),%rax\nmov %rcx,0x28(%rsp)\nmov %rax,0x10(%rsp)\nlea 0x1(%r8),%eax\nmov %eax,0x24(%rsp)\nmov (%r15),%rdx\ntest %ebp,%ebp\nje 1337 \nmov 0x28(%rsp),%rax\nmov %rdx,%rdi\nmov %rdx,0x8(%rsp)\nmov (%rax),%rsi\ncallq 10c0 \nmov 0x8(%rsp),%rdx\ntest %eax,%eax\njs 1356 \nmov 0x18(%rsp),%rax\nmov 0x24(%rsp),%r8d\nmov %rbx,%rcx\nmov %r12d,%esi\nmov %r13,%rdi\nmov %rdx,(%rax)\nlea -0x1(%r14),%edx\ncallq 12b0 \nadd $0x8,%r15\ncmp %r15,0x10(%rsp)\njne 1312 \nadd $0x38,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\ntest %r8d,%r8d\njle 13a3 \nlea -0x1(%r8),%eax\nlea 0xc84(%rip),%rbp\nlea 0x8(%rcx,%rax,8),%r12\nnopl (%rax)\nmov (%rbx),%rdx\nmov %rbp,%rsi\nmov $0x1,%edi\nxor %eax,%eax\nadd $0x8,%rbx\ncallq 10d0 <__printf_chk@plt>\ncmp %r12,%rbx\njne 1388 \nadd $0x38,%rsp\nmov $0xa,%edi\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\njmpq 1090 \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest edx, edx\njz short loc_12C0\njmp short func0_part_0\nloc_12C0:\ntest r8d, r8d\njle short loc_1310\nmovsxd r8, r8d\npush r12\nlea r12, [rcx+r8*8]\npush rbp\nlea rbp, unk_2004\npush rbx\nmov rbx, rcx\nnop word ptr [rax+rax+00h]\nloc_12E0:\nmov rdx, [rbx]\nmov rsi, rbp\nmov edi, 2\nxor eax, eax\nadd rbx, 8\ncall ___printf_chk\ncmp rbx, r12\njnz short loc_12E0\npop rbx\nmov edi, 0Ah; c\npop rbp\npop r12\njmp _putchar\nloc_1310:\nmov edi, 0Ah; c\njmp _putchar", + "ida_pseudo": "int __fastcall func0(__int64 a1, __int64 a2, int a3, __int64 *a4, int a5)\n{\n __int64 *v6; // r12\n __int64 *v7; // rbx\n __int64 v8; // rdx\n\n if ( a3 )\n return func0_part_0();\n if ( a5 > 0 )\n {\n v6 = &a4[a5];\n v7 = a4;\n do\n {\n v8 = *v7++;\n __printf_chk(2LL, &unk_2004, v8);\n }\n while ( v7 != v6 );\n }\n return putchar(10);\n}", + "ida_strip_asm": "sub_12B0:\nendbr64\ntest edx, edx\njz short loc_12C0\njmp short sub_1320\nloc_12C0:\ntest r8d, r8d\njle short loc_1310\nmovsxd r8, r8d\npush r12\nlea r12, [rcx+r8*8]\npush rbp\nlea rbp, unk_2004\npush rbx\nmov rbx, rcx\nnop word ptr [rax+rax+00h]\nloc_12E0:\nmov rdx, [rbx]\nmov rsi, rbp\nmov edi, 2\nxor eax, eax\nadd rbx, 8\ncall ___printf_chk\ncmp rbx, r12\njnz short loc_12E0\npop rbx\nmov edi, 0Ah; c\npop rbp\npop r12\njmp _putchar\nloc_1310:\nmov edi, 0Ah; c\njmp _putchar", + "ida_strip_pseudo": "int __fastcall sub_12B0(__int64 a1, __int64 a2, int a3, __int64 *a4, int a5)\n{\n __int64 *v6; // r12\n __int64 *v7; // rbx\n __int64 v8; // rdx\n\n if ( a3 )\n return sub_1320();\n if ( a5 > 0 )\n {\n v6 = &a4[a5];\n v7 = a4;\n do\n {\n v8 = *v7++;\n __printf_chk(2LL, &unk_2004, v8);\n }\n while ( v7 != v6 );\n }\n return putchar(10);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "int sub_12B0(long long a1, long long a2, int a3, long long *a4, int a5) {\n long long *v6;\n long long *v7;\n long long v8;\n if (a3) return sub_1320();\n if (a5 > 0) {\n v6 = &a4[a5];\n v7 = a4;\n do {\n v8 = *v7++;\n __printf_chk(2LL, &unk_2004, v8);\n } while (v7 != v6);\n }\n return putchar(10);\n}", + "ida_pseudo_norm": "int func0(long long a1, long long a2, int a3, long long *a4, int a5) {\n long long *v6;\n long long *v7;\n long long v8;\n if (a3) return func0_part_0();\n if (a5 > 0) {\n v6 = &a4[a5];\n v7 = a4;\n do {\n v8 = *v7++;\n __printf_chk(2LL, &unk_2004, v8);\n } while (v7 != v6);\n }\n return putchar(10);\n}" + }, + { + "index": 255, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(char *l[], int arr_size, int len, char *result[], int res_len) {\n if (len == 0) {\n for (int i = 0; i < res_len; i++) {\n printf(\"%s \", result[i]);\n }\n printf(\"\\n\");\n return;\n }\n for (int i = 0; i < arr_size; i++) {\n if (res_len == 0 || strcmp(l[i], result[res_len - 1]) >= 0) {\n result[res_len] = l[i];\n func0(l, arr_size, len - 1, result, res_len + 1);\n }\n }\n}", + "test": "int main() {\n\n char *colors[] = {\"Red\", \"Green\", \"Blue\"};\n\n int colors_size = 3;\n\n char *result1[1];\n\n char *result2[2];\n\n char *result3[3];\n\n\n\n printf(\"Combination with 1 color:\\n\");\n\n func0(colors, colors_size, 1, result1, 0);\n\n\n\n printf(\"Combination with 2 colors:\\n\");\n\n func0(colors, colors_size, 2, result2, 0);\n\n\n\n printf(\"Combination with 3 colors:\\n\");\n\n func0(colors, colors_size, 3, result3, 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %rcx,%rbx\nsub $0x28,%rsp\ntest %edx,%edx\nje 1490 \nmov %esi,%r12d\ntest %esi,%esi\njle 1479 \nmovslq %r8d,%r15\nmov %rdi,%r13\nmov %edx,%r14d\nmov %rdi,%rbp\nshl $0x3,%r15\nlea -0x8(%rcx,%r15,1),%rax\nmov %rax,0x8(%rsp)\nlea (%rcx,%r15,1),%rax\nmov %rax,(%rsp)\ntest %r8d,%r8d\nje 14e0 \nlea -0x1(%rsi),%eax\nlea 0x8(%rdi,%rax,8),%rax\nmov %rax,0x10(%rsp)\nlea 0x1(%r8),%eax\nmov %eax,0x1c(%rsp)\nmov 0x8(%rsp),%rax\nmov 0x0(%rbp),%r15\nmov (%rax),%rsi\nmov %r15,%rdi\ncallq 10c0 \ntest %eax,%eax\njs 146e \nmov (%rsp),%rax\nmov 0x1c(%rsp),%r8d\nlea -0x1(%r14),%edx\nmov %rbx,%rcx\nmov %r12d,%esi\nmov %r13,%rdi\nmov %r15,(%rax)\ncallq 13d0 \nadd $0x8,%rbp\ncmp 0x10(%rsp),%rbp\njne 1438 \nadd $0x28,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax,%rax,1)\ntest %r8d,%r8d\njle 14c3 \nlea -0x1(%r8),%eax\nlea 0xb64(%rip),%rbp\nlea 0x8(%rcx,%rax,8),%r12\nnopl (%rax)\nmov (%rbx),%rdx\nmov %rbp,%rsi\nmov $0x1,%edi\nxor %eax,%eax\nadd $0x8,%rbx\ncallq 10d0 <__printf_chk@plt>\ncmp %rbx,%r12\njne 14a8 \nadd $0x28,%rsp\nmov $0xa,%edi\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\njmpq 1090 \nnopl 0x0(%rax,%rax,1)\nlea -0x1(%rsi),%edx\nsub $0x1,%r14d\nlea 0x8(%rdi,%rdx,8),%r15\nmov 0x0(%rbp),%rdx\nmov (%rsp),%rax\nmov %rbx,%rcx\nmov %r12d,%esi\nmov $0x1,%r8d\nmov %r13,%rdi\nadd $0x8,%rbp\nmov %rdx,(%rax)\nmov %r14d,%edx\ncallq 13d0 \ncmp %r15,%rbp\njne 14ec \nadd $0x28,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0_constprop_0:\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdx\nsub rsp, 28h\ntest esi, esi\njz loc_1388\nmovsxd rax, ecx\nmov rbp, rdi\nmov r12d, esi\nshl rax, 3\nlea rdi, [rdx+rax]\nmov [rsp+58h+var_50], rdi\ntest ecx, ecx\njz short loc_1340\nlea r15, [rdx+rax-8]\nlea rax, [rbp+18h]\nmov r14, rbp\nmov [rsp+58h+var_48], rax\nlea eax, [rcx+1]\nmov [rsp+58h+var_3C], eax\nloc_12EB:\nmov r13, [r14]\nmov rsi, [r15]; s2\nmov rdi, r13; s1\ncall _strcmp\ntest eax, eax\njs short loc_1319\nmov rax, [rsp+58h+var_50]\nmov ecx, [rsp+58h+var_3C]\nmov rdx, rbx\nmov rdi, rbp\nlea esi, [r12-1]\nmov [rax], r13\ncall func0_constprop_0\nloc_1319:\nmov rax, [rsp+58h+var_48]\nadd r14, 8\ncmp r14, rax\njnz short loc_12EB\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1340:\nmov r14, rbp\nlea r15, [rbp+18h]\nsub r12d, 1\nloc_134B:\nmov rax, [r14]\nmov rcx, [rsp+58h+var_50]\nmov rdx, rbx\nmov esi, r12d\nmov rdi, rbp\nadd r14, 8\nmov [rcx], rax\nmov ecx, 1\ncall func0_constprop_0\ncmp r14, r15\njnz short loc_134B\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1388:\ntest ecx, ecx\njle short loc_13BB\nmovsxd rcx, ecx\nlea rbp, unk_2004\nlea r12, [rdx+rcx*8]\nnop word ptr [rax+rax+00h]\nloc_13A0:\nmov rdx, [rbx]\nmov rsi, rbp\nmov edi, 2\nxor eax, eax\nadd rbx, 8\ncall ___printf_chk\ncmp r12, rbx\njnz short loc_13A0\nloc_13BB:\nadd rsp, 28h\nmov edi, 0Ah; c\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\njmp _putchar", + "ida_pseudo": "int __fastcall func0_constprop_0(const char **a1, int a2, __int64 *a3, int a4)\n{\n __int64 *v4; // rbx\n __int64 v5; // rax\n const char **v6; // r15\n const char **v7; // r14\n const char *v8; // r13\n int result; // eax\n const char **v10; // r14\n const char *v11; // rax\n __int64 *v12; // r12\n __int64 v13; // rdx\n const char **v14; // [rsp+8h] [rbp-50h]\n unsigned int v15; // [rsp+1Ch] [rbp-3Ch]\n\n v4 = a3;\n if ( a2 )\n {\n v5 = a4;\n v14 = (const char **)&a3[v5];\n if ( a4 )\n {\n v6 = (const char **)&a3[v5 - 1];\n v7 = a1;\n v15 = a4 + 1;\n do\n {\n v8 = *v7;\n if ( strcmp(*v7, *v6) >= 0 )\n {\n *v14 = v8;\n func0_constprop_0(a1, (unsigned int)(a2 - 1), v4, v15);\n }\n result = (_DWORD)a1 + 24;\n ++v7;\n }\n while ( v7 != a1 + 3 );\n }\n else\n {\n v10 = a1;\n do\n {\n v11 = *v10++;\n *v14 = v11;\n result = func0_constprop_0(a1, (unsigned int)(a2 - 1), v4, 1LL);\n }\n while ( v10 != a1 + 3 );\n }\n }\n else\n {\n if ( a4 > 0 )\n {\n v12 = &a3[a4];\n do\n {\n v13 = *v4++;\n __printf_chk(2LL, &unk_2004, v13);\n }\n while ( v12 != v4 );\n }\n return putchar(10);\n }\n return result;\n}", + "ida_strip_asm": "sub_12A0:\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdx\nsub rsp, 28h\ntest esi, esi\njz loc_1388\nmovsxd rax, ecx\nmov rbp, rdi\nmov r12d, esi\nshl rax, 3\nlea rdi, [rdx+rax]\nmov [rsp+58h+var_50], rdi\ntest ecx, ecx\njz short loc_1340\nlea r15, [rdx+rax-8]\nlea rax, [rbp+18h]\nmov r14, rbp\nmov [rsp+58h+var_48], rax\nlea eax, [rcx+1]\nmov [rsp+58h+var_3C], eax\nloc_12EB:\nmov r13, [r14]\nmov rsi, [r15]; s2\nmov rdi, r13; s1\ncall _strcmp\ntest eax, eax\njs short loc_1319\nmov rax, [rsp+58h+var_50]\nmov ecx, [rsp+58h+var_3C]\nmov rdx, rbx\nmov rdi, rbp\nlea esi, [r12-1]\nmov [rax], r13\ncall sub_12A0\nloc_1319:\nmov rax, [rsp+58h+var_48]\nadd r14, 8\ncmp r14, rax\njnz short loc_12EB\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1340:\nmov r14, rbp\nlea r15, [rbp+18h]\nsub r12d, 1\nloc_134B:\nmov rax, [r14]\nmov rcx, [rsp+58h+var_50]\nmov rdx, rbx\nmov esi, r12d\nmov rdi, rbp\nadd r14, 8\nmov [rcx], rax\nmov ecx, 1\ncall sub_12A0\ncmp r14, r15\njnz short loc_134B\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1388:\ntest ecx, ecx\njle short loc_13BB\nmovsxd rcx, ecx\nlea rbp, unk_2004\nlea r12, [rdx+rcx*8]\nnop word ptr [rax+rax+00h]\nloc_13A0:\nmov rdx, [rbx]\nmov rsi, rbp\nmov edi, 2\nxor eax, eax\nadd rbx, 8\ncall ___printf_chk\ncmp r12, rbx\njnz short loc_13A0\nloc_13BB:\nadd rsp, 28h\nmov edi, 0Ah; c\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\njmp _putchar", + "ida_strip_pseudo": "int __fastcall sub_12A0(const char **a1, int a2, __int64 *a3, int a4)\n{\n __int64 *v4; // rbx\n __int64 v5; // rax\n const char **v6; // r15\n const char **v7; // r14\n const char *v8; // r13\n int result; // eax\n const char **v10; // r14\n const char *v11; // rax\n __int64 *v12; // r12\n __int64 v13; // rdx\n const char **v14; // [rsp+8h] [rbp-50h]\n unsigned int v15; // [rsp+1Ch] [rbp-3Ch]\n\n v4 = a3;\n if ( a2 )\n {\n v5 = a4;\n v14 = (const char **)&a3[v5];\n if ( a4 )\n {\n v6 = (const char **)&a3[v5 - 1];\n v7 = a1;\n v15 = a4 + 1;\n do\n {\n v8 = *v7;\n if ( strcmp(*v7, *v6) >= 0 )\n {\n *v14 = v8;\n sub_12A0(a1, (unsigned int)(a2 - 1), v4, v15);\n }\n result = (_DWORD)a1 + 24;\n ++v7;\n }\n while ( v7 != a1 + 3 );\n }\n else\n {\n v10 = a1;\n do\n {\n v11 = *v10++;\n *v14 = v11;\n result = sub_12A0(a1, (unsigned int)(a2 - 1), v4, 1LL);\n }\n while ( v10 != a1 + 3 );\n }\n }\n else\n {\n if ( a4 > 0 )\n {\n v12 = &a3[a4];\n do\n {\n v13 = *v4++;\n __printf_chk(2LL, &unk_2004, v13);\n }\n while ( v12 != v4 );\n }\n return putchar(10);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "int sub_12A0(const char **a1, int a2, long long *a3, int a4) {\n long long *v4;\n long long v5;\n const char **v6;\n const char **v7;\n const char *v8;\n int result;\n const char **v10;\n const char *v11;\n long long *v12;\n long long v13;\n const char **v14;\n unsigned int v15;\n v4 = a3;\n if (a2) {\n v5 = a4;\n v14 = (const char **)&a3[v5];\n if (a4) {\n v6 = (const char **)&a3[v5 - 1];\n v7 = a1;\n v15 = a4 + 1;\n do {\n v8 = *v7;\n if (strcmp(*v7, *v6) >= 0) {\n *v14 = v8;\n sub_12A0(a1, (unsigned int)(a2 - 1), v4, v15);\n }\n result = (uint32_t)a1 + 24;\n ++v7;\n } while (v7 != a1 + 3);\n } else {\n v10 = a1;\n do {\n v11 = *v10++;\n *v14 = v11;\n result = sub_12A0(a1, (unsigned int)(a2 - 1), v4, 1LL);\n } while (v10 != a1 + 3);\n }\n } else {\n if (a4 > 0) {\n v12 = &a3[a4];\n do {\n v13 = *v4++;\n __printf_chk(2LL, &unk_2004, v13);\n } while (v12 != v4);\n }\n return putchar(10);\n }\n return result;\n}", + "ida_pseudo_norm": "int func0_constprop_0(const char **a1, int a2, long long *a3, int a4) {\n long long *v4;\n long long v5;\n const char **v6;\n const char **v7;\n const char *v8;\n int result;\n const char **v10;\n const char *v11;\n long long *v12;\n long long v13;\n const char **v14;\n unsigned int v15;\n v4 = a3;\n if (a2) {\n v5 = a4;\n v14 = (const char **)&a3[v5];\n if (a4) {\n v6 = (const char **)&a3[v5 - 1];\n v7 = a1;\n v15 = a4 + 1;\n do {\n v8 = *v7;\n if (strcmp(*v7, *v6) >= 0) {\n *v14 = v8;\n func0_constprop_0(a1, (unsigned int)(a2 - 1), v4, v15);\n }\n result = (uint32_t)a1 + 24;\n ++v7;\n } while (v7 != a1 + 3);\n } else {\n v10 = a1;\n do {\n v11 = *v10++;\n *v14 = v11;\n result = func0_constprop_0(a1, (unsigned int)(a2 - 1), v4, 1LL);\n } while (v10 != a1 + 3);\n }\n } else {\n if (a4 > 0) {\n v12 = &a3[a4];\n do {\n v13 = *v4++;\n __printf_chk(2LL, &unk_2004, v13);\n } while (v12 != v4);\n }\n return putchar(10);\n }\n return result;\n}" + }, + { + "index": 256, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int ctr = 0;\n for (int num = 0; num < n; num++) {\n if (num <= 1) {\n continue;\n }\n int isPrime = 1;\n for (int i = 2; i < num; i++) {\n if (num % i == 0) {\n isPrime = 0;\n break;\n }\n }\n if (isPrime) {\n ctr++;\n }\n }\n return ctr;\n}", + "test": "int main() {\n\n assert(func0(5) == 2);\n\n assert(func0(10) == 4);\n\n assert(func0(100) == 25);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmovl $0x0,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 11ad \ncmpl $0x1,-0xc(%rbp)\njle 11a8 \nmovl $0x1,-0x8(%rbp)\nmovl $0x2,-0x4(%rbp)\njmp 1194 \nmov -0xc(%rbp),%eax\ncltd\nidivl -0x4(%rbp)\nmov %edx,%eax\ntest %eax,%eax\njne 1190 \nmovl $0x0,-0x8(%rbp)\njmp 119c \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0xc(%rbp),%eax\njl 117a \ncmpl $0x0,-0x8(%rbp)\nje 11a9 \naddl $0x1,-0x10(%rbp)\njmp 11a9 \naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x14(%rbp),%eax\njl 1164 \nmov -0x10(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp short loc_11AD\nloc_1164:\ncmp [rbp+var_C], 1\njle short loc_11A8\nmov [rbp+var_8], 1\nmov [rbp+var_4], 2\njmp short loc_1194\nloc_117A:\nmov eax, [rbp+var_C]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njnz short loc_1190\nmov [rbp+var_8], 0\njmp short loc_119C\nloc_1190:\nadd [rbp+var_4], 1\nloc_1194:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_C]\njl short loc_117A\nloc_119C:\ncmp [rbp+var_8], 0\njz short loc_11A9\nadd [rbp+var_10], 1\njmp short loc_11A9\nloc_11A8:\nnop\nloc_11A9:\nadd [rbp+var_C], 1\nloc_11AD:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_14]\njl short loc_1164\nmov eax, [rbp+var_10]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v2; // [rsp+4h] [rbp-10h]\n int i; // [rsp+8h] [rbp-Ch]\n int v4; // [rsp+Ch] [rbp-8h]\n int j; // [rsp+10h] [rbp-4h]\n\n v2 = 0;\n for ( i = 0; i < a1; ++i )\n {\n if ( i > 1 )\n {\n v4 = 1;\n for ( j = 2; j < i; ++j )\n {\n if ( !(i % j) )\n {\n v4 = 0;\n break;\n }\n }\n if ( v4 )\n ++v2;\n }\n }\n return v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp short loc_11AD\nloc_1164:\ncmp [rbp+var_C], 1\njle short loc_11A8\nmov [rbp+var_8], 1\nmov [rbp+var_4], 2\njmp short loc_1194\nloc_117A:\nmov eax, [rbp+var_C]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njnz short loc_1190\nmov [rbp+var_8], 0\njmp short loc_119C\nloc_1190:\nadd [rbp+var_4], 1\nloc_1194:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_C]\njl short loc_117A\nloc_119C:\ncmp [rbp+var_8], 0\njz short loc_11A9\nadd [rbp+var_10], 1\njmp short loc_11A9\nloc_11A8:\nnop\nloc_11A9:\nadd [rbp+var_C], 1\nloc_11AD:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_14]\njl short loc_1164\nmov eax, [rbp+var_10]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n unsigned int v2; // [rsp+4h] [rbp-10h]\n int i; // [rsp+8h] [rbp-Ch]\n int v4; // [rsp+Ch] [rbp-8h]\n int j; // [rsp+10h] [rbp-4h]\n\n v2 = 0;\n for ( i = 0; i < a1; ++i )\n {\n if ( i > 1 )\n {\n v4 = 1;\n for ( j = 2; j < i; ++j )\n {\n if ( !(i % j) )\n {\n v4 = 0;\n break;\n }\n }\n if ( v4 )\n ++v2;\n }\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n unsigned int v2;\n int i;\n int v4;\n int j;\n v2 = 0;\n for (i = 0; i < a1; ++i) {\n if (i > 1) {\n v4 = 1;\n for (j = 2; j < i; ++j) {\n if (!(i % j)) {\n v4 = 0;\n break;\n }\n }\n if (v4) ++v2;\n }\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v2;\n int i;\n int v4;\n int j;\n v2 = 0;\n for (i = 0; i < a1; ++i) {\n if (i > 1) {\n v4 = 1;\n for (j = 2; j < i; ++j) {\n if (!(i % j)) {\n v4 = 0;\n break;\n }\n }\n if (v4) ++v2;\n }\n }\n return v2;\n}" + }, + { + "index": 256, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int ctr = 0;\n for (int num = 0; num < n; num++) {\n if (num <= 1) {\n continue;\n }\n int isPrime = 1;\n for (int i = 2; i < num; i++) {\n if (num % i == 0) {\n isPrime = 0;\n break;\n }\n }\n if (isPrime) {\n ctr++;\n }\n }\n return ctr;\n}", + "test": "int main() {\n\n assert(func0(5) == 2);\n\n assert(func0(10) == 4);\n\n assert(func0(100) == 25);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x0,%r8d\nmov $0x0,%r9d\ntest %edi,%edi\njg 1168 \nmov %r9d,%eax\nretq\nadd $0x1,%r9d\nmov %esi,%r8d\nlea 0x1(%r8),%esi\ncmp %esi,%edi\nje 115d \ncmp $0x1,%esi\njle 1165 \ncmp $0x2,%esi\njle 1161 \ntest $0x1,%sil\nje 1165 \nmov $0x2,%ecx\nmov %ecx,%eax\nadd $0x1,%ecx\ncmp %eax,%r8d\nje 1161 \nmov %esi,%eax\ncltd\nidiv %ecx\ntest %edx,%edx\njne 1185 \njmp 1165 \n", + "ida_asm": "func0:\nendbr64\nmov r8d, 0\nmov r9d, 0\ntest edi, edi\njg short loc_1168\nloc_115D:\nmov eax, r9d\nretn\nloc_1161:\nadd r9d, 1\nloc_1165:\nmov r8d, esi\nloc_1168:\nlea esi, [r8+1]\ncmp edi, esi\njz short loc_115D\ncmp esi, 1\njle short loc_1165\ncmp esi, 2\njle short loc_1161\ntest sil, 1\njz short loc_1165\nmov ecx, 2\nloc_1185:\nmov eax, ecx\nadd ecx, 1\ncmp r8d, eax\njz short loc_1161\nmov eax, esi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_1185\njmp short loc_1165", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // r8d\n unsigned int v2; // r9d\n int v4; // esi\n int v5; // ecx\n int v6; // eax\n\n v1 = 0;\n v2 = 0;\n if ( a1 > 0 )\n {\n while ( 1 )\n {\n v4 = v1 + 1;\n if ( a1 == v1 + 1 )\n return v2;\n if ( v4 > 1 )\n {\n if ( v4 <= 2 )\n goto LABEL_3;\n if ( (v4 & 1) != 0 )\n break;\n }\nLABEL_4:\n ++v1;\n }\n v5 = 2;\n while ( 1 )\n {\n v6 = v5++;\n if ( v1 == v6 )\n break;\n if ( !(v4 % v5) )\n goto LABEL_4;\n }\nLABEL_3:\n ++v2;\n goto LABEL_4;\n }\n return v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmov r8d, 0\nmov r9d, 0\ntest edi, edi\njg short loc_1168\nloc_115D:\nmov eax, r9d\nretn\nloc_1161:\nadd r9d, 1\nloc_1165:\nmov r8d, esi\nloc_1168:\nlea esi, [r8+1]\ncmp edi, esi\njz short loc_115D\ncmp esi, 1\njle short loc_1165\ncmp esi, 2\njle short loc_1161\ntest sil, 1\njz short loc_1165\nmov ecx, 2\nloc_1185:\nmov eax, ecx\nadd ecx, 1\ncmp r8d, eax\njz short loc_1161\nmov eax, esi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_1185\njmp short loc_1165", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v1; // r8d\n unsigned int v2; // r9d\n int v4; // esi\n int v5; // ecx\n int v6; // eax\n\n v1 = 0;\n v2 = 0;\n if ( a1 > 0 )\n {\n while ( 1 )\n {\n v4 = v1 + 1;\n if ( a1 == v1 + 1 )\n return v2;\n if ( v4 > 1 )\n {\n if ( v4 <= 2 )\n goto LABEL_3;\n if ( (v4 & 1) != 0 )\n break;\n }\nLABEL_4:\n ++v1;\n }\n v5 = 2;\n while ( 1 )\n {\n v6 = v5++;\n if ( v1 == v6 )\n break;\n if ( !(v4 % v5) )\n goto LABEL_4;\n }\nLABEL_3:\n ++v2;\n goto LABEL_4;\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v1;\n unsigned int v2;\n int v4;\n int v5;\n int v6;\n v1 = 0;\n v2 = 0;\n if (a1 > 0) {\n while (1) {\n v4 = v1 + 1;\n if (a1 == v1 + 1) return v2;\n if (v4 > 1) {\n if (v4 <= 2) goto LABEL_3;\n if ((v4 & 1) != 0) break;\n }\n LABEL_4:\n ++v1;\n }\n v5 = 2;\n while (1) {\n v6 = v5++;\n if (v1 == v6) break;\n if (!(v4 % v5)) goto LABEL_4;\n }\n LABEL_3:\n ++v2;\n goto LABEL_4;\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n unsigned int v2;\n int v4;\n int v5;\n int v6;\n v1 = 0;\n v2 = 0;\n if (a1 > 0) {\n while (1) {\n v4 = v1 + 1;\n if (a1 == v1 + 1) return v2;\n if (v4 > 1) {\n if (v4 <= 2) goto LABEL_3;\n if ((v4 & 1) != 0) break;\n }\n LABEL_4:\n ++v1;\n }\n v5 = 2;\n while (1) {\n v6 = v5++;\n if (v1 == v6) break;\n if (!(v4 % v5)) goto LABEL_4;\n }\n LABEL_3:\n ++v2;\n goto LABEL_4;\n }\n return v2;\n}" + }, + { + "index": 256, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int ctr = 0;\n for (int num = 0; num < n; num++) {\n if (num <= 1) {\n continue;\n }\n int isPrime = 1;\n for (int i = 2; i < num; i++) {\n if (num % i == 0) {\n isPrime = 0;\n break;\n }\n }\n if (isPrime) {\n ctr++;\n }\n }\n return ctr;\n}", + "test": "int main() {\n\n assert(func0(5) == 2);\n\n assert(func0(10) == 4);\n\n assert(func0(100) == 25);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nxor %r8d,%r8d\nxor %r9d,%r9d\ntest %edi,%edi\njle 12a2 \nlea 0x1(%r8),%esi\ncmp %esi,%edi\nje 12a2 \nnopw %cs:0x0(%rax,%rax,1)\ncmp $0x1,%esi\njle 1297 \ncmp $0x2,%esi\nje 1293 \ntest $0x1,%sil\nje 1297 \nmov $0x2,%ecx\njmp 1289 \nnopw 0x0(%rax,%rax,1)\nmov %esi,%eax\ncltd\nidiv %ecx\ntest %edx,%edx\nje 1297 \nmov %ecx,%eax\nadd $0x1,%ecx\ncmp %r8d,%eax\njne 1280 \nadd $0x1,%r9d\nmov %esi,%r8d\nlea 0x1(%r8),%esi\ncmp %esi,%edi\njne 1260 \nmov %r9d,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nxor r9d, r9d\ntest edi, edi\njle short loc_124A\nmov r8d, 1\nxor r9d, r9d\ncmp edi, 1\njz short loc_124A\nlea esi, [r8+1]\ncmp edi, esi\njz short loc_124A\nloc_1211:\ncmp esi, 2\njle short loc_123B\ntest sil, 1\njz short loc_123F\nmov ecx, 2\njmp short loc_1231\nloc_1228:\nmov eax, esi\ncdq\nidiv ecx\ntest edx, edx\njz short loc_123F\nloc_1231:\nmov eax, ecx\nadd ecx, 1\ncmp eax, r8d\njnz short loc_1228\nloc_123B:\nadd r9d, 1\nloc_123F:\nmov r8d, esi\nlea esi, [r8+1]\ncmp edi, esi\njnz short loc_1211\nloc_124A:\nmov eax, r9d\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v1; // r9d\n int v2; // r8d\n int v3; // esi\n int v4; // ecx\n int v5; // eax\n\n v1 = 0;\n if ( a1 > 0 )\n {\n v2 = 1;\n v1 = 0;\n if ( a1 != 1 )\n {\n v3 = 2;\n if ( a1 != 2 )\n {\n while ( 1 )\n {\n if ( v3 <= 2 )\n goto LABEL_9;\n if ( (v3 & 1) != 0 )\n break;\nLABEL_10:\n v2 = v3++;\n if ( a1 == v3 )\n return v1;\n }\n v4 = 2;\n while ( 1 )\n {\n v5 = v4++;\n if ( v5 == v2 )\n break;\n if ( !(v3 % v4) )\n goto LABEL_10;\n }\nLABEL_9:\n ++v1;\n goto LABEL_10;\n }\n }\n }\n return v1;\n}", + "ida_strip_asm": "sub_11F0:\nendbr64\nxor r9d, r9d\ntest edi, edi\njle short loc_124A\nmov r8d, 1\nxor r9d, r9d\ncmp edi, 1\njz short loc_124A\nlea esi, [r8+1]\ncmp edi, esi\njz short loc_124A\nloc_1211:\ncmp esi, 2\njle short loc_123B\ntest sil, 1\njz short loc_123F\nmov ecx, 2\njmp short loc_1231\nloc_1228:\nmov eax, esi\ncdq\nidiv ecx\ntest edx, edx\njz short loc_123F\nloc_1231:\nmov eax, ecx\nadd ecx, 1\ncmp eax, r8d\njnz short loc_1228\nloc_123B:\nadd r9d, 1\nloc_123F:\nmov r8d, esi\nlea esi, [r8+1]\ncmp edi, esi\njnz short loc_1211\nloc_124A:\nmov eax, r9d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11F0(int a1)\n{\n unsigned int v1; // r9d\n int v2; // r8d\n int v3; // esi\n int v4; // ecx\n int v5; // eax\n\n v1 = 0;\n if ( a1 > 0 )\n {\n v2 = 1;\n v1 = 0;\n if ( a1 != 1 )\n {\n v3 = 2;\n if ( a1 != 2 )\n {\n while ( 1 )\n {\n if ( v3 <= 2 )\n goto LABEL_9;\n if ( (v3 & 1) != 0 )\n break;\nLABEL_10:\n v2 = v3++;\n if ( a1 == v3 )\n return v1;\n }\n v4 = 2;\n while ( 1 )\n {\n v5 = v4++;\n if ( v5 == v2 )\n break;\n if ( !(v3 % v4) )\n goto LABEL_10;\n }\nLABEL_9:\n ++v1;\n goto LABEL_10;\n }\n }\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11F0(int a1) {\n unsigned int v1;\n int v2;\n int v3;\n int v4;\n int v5;\n v1 = 0;\n if (a1 > 0) {\n v2 = 1;\n v1 = 0;\n if (a1 != 1) {\n v3 = 2;\n if (a1 != 2) {\n while (1) {\n if (v3 <= 2) goto LABEL_9;\n if ((v3 & 1) != 0) break;\n LABEL_10:\n v2 = v3++;\n if (a1 == v3) return v1;\n }\n v4 = 2;\n while (1) {\n v5 = v4++;\n if (v5 == v2) break;\n if (!(v3 % v4)) goto LABEL_10;\n }\n LABEL_9:\n ++v1;\n goto LABEL_10;\n }\n }\n }\n return v1;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v1;\n int v2;\n int v3;\n int v4;\n int v5;\n v1 = 0;\n if (a1 > 0) {\n v2 = 1;\n v1 = 0;\n if (a1 != 1) {\n v3 = 2;\n if (a1 != 2) {\n while (1) {\n if (v3 <= 2) goto LABEL_9;\n if ((v3 & 1) != 0) break;\n LABEL_10:\n v2 = v3++;\n if (a1 == v3) return v1;\n }\n v4 = 2;\n while (1) {\n v5 = v4++;\n if (v5 == v2) break;\n if (!(v3 % v4)) goto LABEL_10;\n }\n LABEL_9:\n ++v1;\n goto LABEL_10;\n }\n }\n }\n return v1;\n}" + }, + { + "index": 257, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "void func0(int *a, int *b) {\n int temp = *a;\n *a = *b;\n *b = temp;\n}", + "test": "int main() {\n\n int a = 10, b = 20;\n\n func0(&a, &b);\n\n assert(a == 20 && b == 10);\n\n\n\n a = 15, b = 17;\n\n func0(&a, &b);\n\n assert(a == 17 && b == 15);\n\n\n\n a = 100, b = 200;\n\n func0(&a, &b);\n\n assert(a == 200 && b == 100);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov -0x18(%rbp),%rax\nmov (%rax),%eax\nmov %eax,-0x4(%rbp)\nmov -0x20(%rbp),%rax\nmov (%rax),%edx\nmov -0x18(%rbp),%rax\nmov %edx,(%rax)\nmov -0x20(%rbp),%rax\nmov -0x4(%rbp),%edx\nmov %edx,(%rax)\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov rax, [rbp+var_18]\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov rax, [rbp+var_20]\nmov edx, [rax]\nmov rax, [rbp+var_18]\nmov [rax], edx\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_4]\nmov [rax], edx\nnop\npop rbp\nretn", + "ida_pseudo": "int *__fastcall func0(int *a1, int *a2)\n{\n int *result; // rax\n int v3; // [rsp+1Ch] [rbp-4h]\n\n v3 = *a1;\n *a1 = *a2;\n result = a2;\n *a2 = v3;\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov rax, [rbp+var_18]\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov rax, [rbp+var_20]\nmov edx, [rax]\nmov rax, [rbp+var_18]\nmov [rax], edx\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_4]\nmov [rax], edx\nnop\npop rbp\nretn", + "ida_strip_pseudo": "int *__fastcall sub_1169(int *a1, int *a2)\n{\n int *result; // rax\n int v3; // [rsp+1Ch] [rbp-4h]\n\n v3 = *a1;\n *a1 = *a2;\n result = a2;\n *a2 = v3;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "int *sub_1169(int *a1, int *a2) {\n int *result;\n int v3;\n v3 = *a1;\n *a1 = *a2;\n result = a2;\n *a2 = v3;\n return result;\n}", + "ida_pseudo_norm": "int *func0(int *a1, int *a2) {\n int *result;\n int v3;\n v3 = *a1;\n *a1 = *a2;\n result = a2;\n *a2 = v3;\n return result;\n}" + }, + { + "index": 258, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int array_nums[], int n) {\n int count_odd = 0;\n for (int i = 0; i < n; i++) {\n if (array_nums[i] % 2 != 0) {\n count_odd++;\n }\n }\n return count_odd;\n}", + "test": "int main() {\n\n int array1[] = {1, 2, 3, 5, 7, 8, 10};\n\n int array2[] = {10, 15, 14, 13, -18, 12, -20};\n\n int array3[] = {1, 2, 4, 8, 9};\n\n\n\n assert(func0(array1, 7) == 4);\n\n assert(func0(array2, 7) == 2);\n\n assert(func0(array3, 5) == 2);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11ad \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nand $0x1,%eax\ntest %eax,%eax\nje 11a9 \naddl $0x1,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1188 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11AD\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njz short loc_11A9\nadd [rbp+var_8], 1\nloc_11A9:\nadd [rbp+var_4], 1\nloc_11AD:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( (*(_DWORD *)(4LL * i + a1) & 1) != 0 )\n ++v3;\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11AD\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njz short loc_11A9\nadd [rbp+var_8], 1\nloc_11A9:\nadd [rbp+var_4], 1\nloc_11AD:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( (*(_DWORD *)(4LL * i + a1) & 1) != 0 )\n ++v3;\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n if ((*(uint32_t *)(4LL * i + a1) & 1) != 0) ++v3;\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n if ((*(uint32_t *)(4LL * i + a1) & 1) != 0) ++v3;\n }\n return v3;\n}" + }, + { + "index": 258, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int array_nums[], int n) {\n int count_odd = 0;\n for (int i = 0; i < n; i++) {\n if (array_nums[i] % 2 != 0) {\n count_odd++;\n }\n }\n return count_odd;\n}", + "test": "int main() {\n\n int array1[] = {1, 2, 3, 5, 7, 8, 10};\n\n int array2[] = {10, 15, 14, 13, -18, 12, -20};\n\n int array3[] = {1, 2, 4, 8, 9};\n\n\n\n assert(func0(array1, 7) == 4);\n\n assert(func0(array2, 7) == 2);\n\n assert(func0(array3, 5) == 2);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1198 \nmov %rdi,%rax\nlea -0x1(%rsi),%edx\nlea 0x4(%rdi,%rdx,4),%rsi\nmov $0x0,%ecx\nmov (%rax),%edx\nand $0x1,%edx\ncmp $0x1,%edx\nsbb $0xffffffff,%ecx\nadd $0x4,%rax\ncmp %rsi,%rax\njne 1181 \nmov %ecx,%eax\nretq\nmov $0x0,%ecx\njmp 1195 \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1197\nmov rax, rdi\nmovsxd rsi, esi\nlea rsi, [rdi+rsi*4]\nmov ecx, 0\nloc_1180:\nmov edx, [rax]\nand edx, 1\ncmp edx, 1\nsbb ecx, 0FFFFFFFFh\nadd rax, 4\ncmp rax, rsi\njnz short loc_1180\nloc_1194:\nmov eax, ecx\nretn\nloc_1197:\nmov ecx, 0\njmp short loc_1194", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n _DWORD *v3; // rsi\n unsigned int v4; // ecx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n v4 -= ((*v2++ & 1) == 0) - 1;\n while ( v2 != v3 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_1197\nmov rax, rdi\nmovsxd rsi, esi\nlea rsi, [rdi+rsi*4]\nmov ecx, 0\nloc_1180:\nmov edx, [rax]\nand edx, 1\ncmp edx, 1\nsbb ecx, 0FFFFFFFFh\nadd rax, 4\ncmp rax, rsi\njnz short loc_1180\nloc_1194:\nmov eax, ecx\nretn\nloc_1197:\nmov ecx, 0\njmp short loc_1194", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n _DWORD *v3; // rsi\n unsigned int v4; // ecx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n v4 -= ((*v2++ & 1) == 0) - 1;\n while ( v2 != v3 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2) {\n uint32_t *v2;\n uint32_t *v3;\n unsigned int v4;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n v4 -= ((*v2++ & 1) == 0) - 1;\n while (v2 != v3);\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n uint32_t *v3;\n unsigned int v4;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n v4 -= ((*v2++ & 1) == 0) - 1;\n while (v2 != v3);\n }\n return v4;\n}" + }, + { + "index": 259, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "void func0(int test_tup1[][2], int test_tup2[][2], int rows, int res[][2]) {\n for (int i = 0; i < rows; i++) {\n for (int j = 0; j < 2; j++) {\n res[i][j] = (test_tup1[i][j] > test_tup2[i][j]) ? test_tup1[i][j]\n : test_tup2[i][j];\n }\n }\n}", + "test": "int main() {\n\n int test_tup1[4][2] = {{1, 3}, {4, 5}, {2, 9}, {1, 10}};\n\n int test_tup2[4][2] = {{6, 7}, {3, 9}, {1, 1}, {7, 3}};\n\n int result[4][2];\n\n int expected[4][2] = {{6, 7}, {4, 9}, {2, 9}, {7, 10}};\n\n func0(test_tup1, test_tup2, 4, result);\n\n for (int i = 0; i < 4; i++) {\n\n assert(result[i][0] == expected[i][0] && result[i][1] == expected[i][1]);\n\n }\n\n\n\n int test_tup3[4][2] = {{2, 4}, {5, 6}, {3, 10}, {2, 11}};\n\n int test_tup4[4][2] = {{7, 8}, {4, 10}, {2, 2}, {8, 4}};\n\n int expected2[4][2] = {{7, 8}, {5, 10}, {3, 10}, {8, 11}};\n\n func0(test_tup3, test_tup4, 4, result);\n\n for (int i = 0; i < 4; i++) {\n\n assert(result[i][0] == expected2[i][0] && result[i][1] == expected2[i][1]);\n\n }\n\n\n\n int test_tup5[4][2] = {{3, 5}, {6, 7}, {4, 11}, {3, 12}};\n\n int test_tup6[4][2] = {{8, 9}, {5, 11}, {3, 3}, {9, 5}};\n\n int expected3[4][2] = {{8, 9}, {6, 11}, {4, 11}, {9, 12}};\n\n func0(test_tup5, test_tup6, 4, result);\n\n for (int i = 0; i < 4; i++) {\n\n assert(result[i][0] == expected3[i][0] && result[i][1] == expected3[i][1]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %edx,-0x24(%rbp)\nmov %rcx,-0x30(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11fa \nmovl $0x0,-0x4(%rbp)\njmp 11f0 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x20(%rbp),%rax\nadd %rax,%rdx\nmov -0x4(%rbp),%eax\ncltq\nmov (%rdx,%rax,4),%edx\nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x18(%rbp),%rax\nadd %rax,%rcx\nmov -0x4(%rbp),%eax\ncltq\nmov (%rcx,%rax,4),%eax\nmov -0x8(%rbp),%ecx\nmovslq %ecx,%rcx\nlea 0x0(,%rcx,8),%rsi\nmov -0x30(%rbp),%rcx\nadd %rsi,%rcx\ncmp %eax,%edx\ncmovl %eax,%edx\nmov -0x4(%rbp),%eax\ncltq\nmov %edx,(%rcx,%rax,4)\naddl $0x1,-0x4(%rbp)\ncmpl $0x1,-0x4(%rbp)\njle 1192 \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x24(%rbp),%eax\njl 1189 \npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_30], rcx\nmov [rbp+var_8], 0\njmp short loc_11FA\nloc_1189:\nmov [rbp+var_4], 0\njmp short loc_11F0\nloc_1192:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_20]\nadd rdx, rax\nmov eax, [rbp+var_4]\ncdqe\nmov edx, [rdx+rax*4]\nmov eax, [rbp+var_8]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rcx, rax\nmov eax, [rbp+var_4]\ncdqe\nmov eax, [rcx+rax*4]\nmov ecx, [rbp+var_8]\nmovsxd rcx, ecx\nlea rsi, ds:0[rcx*8]\nmov rcx, [rbp+var_30]\nadd rcx, rsi\ncmp edx, eax\ncmovl edx, eax\nmov eax, [rbp+var_4]\ncdqe\nmov [rcx+rax*4], edx\nadd [rbp+var_4], 1\nloc_11F0:\ncmp [rbp+var_4], 1\njle short loc_1192\nadd [rbp+var_8], 1\nloc_11FA:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_24]\njl short loc_1189\nnop\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3, __int64 a4)\n{\n int v4; // edx\n __int64 result; // rax\n unsigned int i; // [rsp+28h] [rbp-8h]\n int j; // [rsp+2Ch] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a3 )\n break;\n for ( j = 0; j <= 1; ++j )\n {\n v4 = *(_DWORD *)(a2 + 8LL * (int)i + 4LL * j);\n if ( v4 < *(_DWORD *)(a1 + 8LL * (int)i + 4LL * j) )\n v4 = *(_DWORD *)(a1 + 8LL * (int)i + 4LL * j);\n *(_DWORD *)(8LL * (int)i + a4 + 4LL * j) = v4;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_30], rcx\nmov [rbp+var_8], 0\njmp short loc_11FA\nloc_1189:\nmov [rbp+var_4], 0\njmp short loc_11F0\nloc_1192:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_20]\nadd rdx, rax\nmov eax, [rbp+var_4]\ncdqe\nmov edx, [rdx+rax*4]\nmov eax, [rbp+var_8]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rcx, rax\nmov eax, [rbp+var_4]\ncdqe\nmov eax, [rcx+rax*4]\nmov ecx, [rbp+var_8]\nmovsxd rcx, ecx\nlea rsi, ds:0[rcx*8]\nmov rcx, [rbp+var_30]\nadd rcx, rsi\ncmp edx, eax\ncmovl edx, eax\nmov eax, [rbp+var_4]\ncdqe\nmov [rcx+rax*4], edx\nadd [rbp+var_4], 1\nloc_11F0:\ncmp [rbp+var_4], 1\njle short loc_1192\nadd [rbp+var_8], 1\nloc_11FA:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_24]\njl short loc_1189\nnop\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, int a3, __int64 a4)\n{\n int v4; // edx\n __int64 result; // rax\n unsigned int i; // [rsp+28h] [rbp-8h]\n int j; // [rsp+2Ch] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a3 )\n break;\n for ( j = 0; j <= 1; ++j )\n {\n v4 = *(_DWORD *)(a2 + 8LL * (int)i + 4LL * j);\n if ( v4 < *(_DWORD *)(a1 + 8LL * (int)i + 4LL * j) )\n v4 = *(_DWORD *)(a1 + 8LL * (int)i + 4LL * j);\n *(_DWORD *)(8LL * (int)i + a4 + 4LL * j) = v4;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, int a3, long long a4) {\n int v4;\n long long result;\n unsigned int i;\n int j;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a3) break;\n for (j = 0; j <= 1; ++j) {\n v4 = *(uint32_t *)(a2 + 8LL * (int)i + 4LL * j);\n if (v4 < *(uint32_t *)(a1 + 8LL * (int)i + 4LL * j))\n v4 = *(uint32_t *)(a1 + 8LL * (int)i + 4LL * j);\n *(uint32_t *)(8LL * (int)i + a4 + 4LL * j) = v4;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3, long long a4) {\n int v4;\n long long result;\n unsigned int i;\n int j;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a3) break;\n for (j = 0; j <= 1; ++j) {\n v4 = *(uint32_t *)(a2 + 8LL * (int)i + 4LL * j);\n if (v4 < *(uint32_t *)(a1 + 8LL * (int)i + 4LL * j))\n v4 = *(uint32_t *)(a1 + 8LL * (int)i + 4LL * j);\n *(uint32_t *)(8LL * (int)i + a4 + 4LL * j) = v4;\n }\n }\n return result;\n}" + }, + { + "index": 259, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "void func0(int test_tup1[][2], int test_tup2[][2], int rows, int res[][2]) {\n for (int i = 0; i < rows; i++) {\n for (int j = 0; j < 2; j++) {\n res[i][j] = (test_tup1[i][j] > test_tup2[i][j]) ? test_tup1[i][j]\n : test_tup2[i][j];\n }\n }\n}", + "test": "int main() {\n\n int test_tup1[4][2] = {{1, 3}, {4, 5}, {2, 9}, {1, 10}};\n\n int test_tup2[4][2] = {{6, 7}, {3, 9}, {1, 1}, {7, 3}};\n\n int result[4][2];\n\n int expected[4][2] = {{6, 7}, {4, 9}, {2, 9}, {7, 10}};\n\n func0(test_tup1, test_tup2, 4, result);\n\n for (int i = 0; i < 4; i++) {\n\n assert(result[i][0] == expected[i][0] && result[i][1] == expected[i][1]);\n\n }\n\n\n\n int test_tup3[4][2] = {{2, 4}, {5, 6}, {3, 10}, {2, 11}};\n\n int test_tup4[4][2] = {{7, 8}, {4, 10}, {2, 2}, {8, 4}};\n\n int expected2[4][2] = {{7, 8}, {5, 10}, {3, 10}, {8, 11}};\n\n func0(test_tup3, test_tup4, 4, result);\n\n for (int i = 0; i < 4; i++) {\n\n assert(result[i][0] == expected2[i][0] && result[i][1] == expected2[i][1]);\n\n }\n\n\n\n int test_tup5[4][2] = {{3, 5}, {6, 7}, {4, 11}, {3, 12}};\n\n int test_tup6[4][2] = {{8, 9}, {5, 11}, {3, 3}, {9, 5}};\n\n int expected3[4][2] = {{8, 9}, {6, 11}, {4, 11}, {9, 12}};\n\n func0(test_tup5, test_tup6, 4, result);\n\n for (int i = 0; i < 4; i++) {\n\n assert(result[i][0] == expected3[i][0] && result[i][1] == expected3[i][1]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edx,%edx\njle 11a4 \nlea -0x1(%rdx),%r8d\nmov $0x0,%eax\nmov (%rdi,%rax,8),%edx\ncmp %edx,(%rsi,%rax,8)\ncmovge (%rsi,%rax,8),%edx\nmov %edx,(%rcx,%rax,8)\nmov 0x4(%rdi,%rax,8),%edx\ncmp %edx,0x4(%rsi,%rax,8)\ncmovge 0x4(%rsi,%rax,8),%edx\nmov %edx,0x4(%rcx,%rax,8)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %r8,%rdx\njne 117a \nretq\n", + "ida_asm": "func0:\nendbr64\nmov r8, rsi\ntest edx, edx\njle short locret_11AE\nmovsxd rdx, edx\nlea r9, ds:0[rdx*8]\nmov eax, 0\nloc_1184:\nmov edx, [rdi+rax]\nmov esi, [r8+rax]\ncmp edx, esi\ncmovl edx, esi\nmov [rcx+rax], edx\nmov edx, [r8+rax+4]\nmov esi, [rdi+rax+4]\ncmp edx, esi\ncmovl edx, esi\nmov [rcx+rax+4], edx\nadd rax, 8\ncmp r9, rax\njnz short loc_1184\nlocret_11AE:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, __int64 a2, int a3, __int64 a4)\n{\n __int64 v4; // r9\n __int64 v5; // rax\n int v6; // edx\n int v7; // edx\n\n if ( a3 > 0 )\n {\n v4 = 8LL * a3;\n v5 = 0LL;\n do\n {\n v6 = *(_DWORD *)(a1 + v5);\n if ( v6 < *(_DWORD *)(a2 + v5) )\n v6 = *(_DWORD *)(a2 + v5);\n *(_DWORD *)(a4 + v5) = v6;\n v7 = *(_DWORD *)(a2 + v5 + 4);\n if ( v7 < *(_DWORD *)(a1 + v5 + 4) )\n v7 = *(_DWORD *)(a1 + v5 + 4);\n *(_DWORD *)(a4 + v5 + 4) = v7;\n v5 += 8LL;\n }\n while ( v4 != v5 );\n }\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov r8, rsi\ntest edx, edx\njle short locret_11AE\nmovsxd rdx, edx\nlea r9, ds:0[rdx*8]\nmov eax, 0\nloc_1184:\nmov edx, [rdi+rax]\nmov esi, [r8+rax]\ncmp edx, esi\ncmovl edx, esi\nmov [rcx+rax], edx\nmov edx, [r8+rax+4]\nmov esi, [rdi+rax+4]\ncmp edx, esi\ncmovl edx, esi\nmov [rcx+rax+4], edx\nadd rax, 8\ncmp r9, rax\njnz short loc_1184\nlocret_11AE:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1169(__int64 a1, __int64 a2, int a3, __int64 a4)\n{\n __int64 v4; // r9\n __int64 v5; // rax\n int v6; // edx\n int v7; // edx\n\n if ( a3 > 0 )\n {\n v4 = 8LL * a3;\n v5 = 0LL;\n do\n {\n v6 = *(_DWORD *)(a1 + v5);\n if ( v6 < *(_DWORD *)(a2 + v5) )\n v6 = *(_DWORD *)(a2 + v5);\n *(_DWORD *)(a4 + v5) = v6;\n v7 = *(_DWORD *)(a2 + v5 + 4);\n if ( v7 < *(_DWORD *)(a1 + v5 + 4) )\n v7 = *(_DWORD *)(a1 + v5 + 4);\n *(_DWORD *)(a4 + v5 + 4) = v7;\n v5 += 8LL;\n }\n while ( v4 != v5 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1169(long long a1, long long a2, int a3, long long a4) {\n long long v4;\n long long v5;\n int v6;\n int v7;\n if (a3 > 0) {\n v4 = 8LL * a3;\n v5 = 0LL;\n do {\n v6 = *(uint32_t *)(a1 + v5);\n if (v6 < *(uint32_t *)(a2 + v5)) v6 = *(uint32_t *)(a2 + v5);\n *(uint32_t *)(a4 + v5) = v6;\n v7 = *(uint32_t *)(a2 + v5 + 4);\n if (v7 < *(uint32_t *)(a1 + v5 + 4)) v7 = *(uint32_t *)(a1 + v5 + 4);\n *(uint32_t *)(a4 + v5 + 4) = v7;\n v5 += 8LL;\n } while (v4 != v5);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, long long a2, int a3, long long a4) {\n long long v4;\n long long v5;\n int v6;\n int v7;\n if (a3 > 0) {\n v4 = 8LL * a3;\n v5 = 0LL;\n do {\n v6 = *(uint32_t *)(a1 + v5);\n if (v6 < *(uint32_t *)(a2 + v5)) v6 = *(uint32_t *)(a2 + v5);\n *(uint32_t *)(a4 + v5) = v6;\n v7 = *(uint32_t *)(a2 + v5 + 4);\n if (v7 < *(uint32_t *)(a1 + v5 + 4)) v7 = *(uint32_t *)(a1 + v5 + 4);\n *(uint32_t *)(a4 + v5 + 4) = v7;\n v5 += 8LL;\n } while (v4 != v5);\n }\n}" + }, + { + "index": 259, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "void func0(int test_tup1[][2], int test_tup2[][2], int rows, int res[][2]) {\n for (int i = 0; i < rows; i++) {\n for (int j = 0; j < 2; j++) {\n res[i][j] = (test_tup1[i][j] > test_tup2[i][j]) ? test_tup1[i][j]\n : test_tup2[i][j];\n }\n }\n}", + "test": "int main() {\n\n int test_tup1[4][2] = {{1, 3}, {4, 5}, {2, 9}, {1, 10}};\n\n int test_tup2[4][2] = {{6, 7}, {3, 9}, {1, 1}, {7, 3}};\n\n int result[4][2];\n\n int expected[4][2] = {{6, 7}, {4, 9}, {2, 9}, {7, 10}};\n\n func0(test_tup1, test_tup2, 4, result);\n\n for (int i = 0; i < 4; i++) {\n\n assert(result[i][0] == expected[i][0] && result[i][1] == expected[i][1]);\n\n }\n\n\n\n int test_tup3[4][2] = {{2, 4}, {5, 6}, {3, 10}, {2, 11}};\n\n int test_tup4[4][2] = {{7, 8}, {4, 10}, {2, 2}, {8, 4}};\n\n int expected2[4][2] = {{7, 8}, {5, 10}, {3, 10}, {8, 11}};\n\n func0(test_tup3, test_tup4, 4, result);\n\n for (int i = 0; i < 4; i++) {\n\n assert(result[i][0] == expected2[i][0] && result[i][1] == expected2[i][1]);\n\n }\n\n\n\n int test_tup5[4][2] = {{3, 5}, {6, 7}, {4, 11}, {3, 12}};\n\n int test_tup6[4][2] = {{8, 9}, {5, 11}, {3, 3}, {9, 5}};\n\n int expected3[4][2] = {{8, 9}, {6, 11}, {4, 11}, {9, 12}};\n\n func0(test_tup5, test_tup6, 4, result);\n\n for (int i = 0; i < 4; i++) {\n\n assert(result[i][0] == expected3[i][0] && result[i][1] == expected3[i][1]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %edx,%edx\njle 156a \nlea -0x1(%rdx),%r8d\nxor %eax,%eax\nxchg %ax,%ax\nmov (%rdi,%rax,8),%edx\ncmp %edx,(%rsi,%rax,8)\ncmovge (%rsi,%rax,8),%edx\nmov %edx,(%rcx,%rax,8)\nmov 0x4(%rdi,%rax,8),%edx\ncmp %edx,0x4(%rsi,%rax,8)\ncmovge 0x4(%rsi,%rax,8),%edx\nmov %edx,0x4(%rcx,%rax,8)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rdx,%r8\njne 1540 \nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmov r8, rsi\ntest edx, edx\njle short locret_143A\nmovsxd rdx, edx\nxor eax, eax\nlea r9, ds:0[rdx*8]\nnop dword ptr [rax+rax+00000000h]\nloc_1410:\nmov esi, [rdi+rax]\nmov edx, [r8+rax]\ncmp edx, esi\ncmovl edx, esi\nmov [rcx+rax], edx\nmov edx, [r8+rax+4]\nmov esi, [rdi+rax+4]\ncmp edx, esi\ncmovl edx, esi\nmov [rcx+rax+4], edx\nadd rax, 8\ncmp r9, rax\njnz short loc_1410\nlocret_143A:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, __int64 a2, int a3, __int64 a4)\n{\n __int64 v4; // rax\n __int64 v5; // r9\n int v6; // edx\n int v7; // edx\n\n if ( a3 > 0 )\n {\n v4 = 0LL;\n v5 = 8LL * a3;\n do\n {\n v6 = *(_DWORD *)(a2 + v4);\n if ( v6 < *(_DWORD *)(a1 + v4) )\n v6 = *(_DWORD *)(a1 + v4);\n *(_DWORD *)(a4 + v4) = v6;\n v7 = *(_DWORD *)(a2 + v4 + 4);\n if ( v7 < *(_DWORD *)(a1 + v4 + 4) )\n v7 = *(_DWORD *)(a1 + v4 + 4);\n *(_DWORD *)(a4 + v4 + 4) = v7;\n v4 += 8LL;\n }\n while ( v5 != v4 );\n }\n}", + "ida_strip_asm": "sub_13F0:\nendbr64\nmov r8, rsi\ntest edx, edx\njle short locret_143A\nmovsxd rdx, edx\nxor eax, eax\nlea r9, ds:0[rdx*8]\nnop dword ptr [rax+rax+00000000h]\nloc_1410:\nmov esi, [rdi+rax]\nmov edx, [r8+rax]\ncmp edx, esi\ncmovl edx, esi\nmov [rcx+rax], edx\nmov edx, [r8+rax+4]\nmov esi, [rdi+rax+4]\ncmp edx, esi\ncmovl edx, esi\nmov [rcx+rax+4], edx\nadd rax, 8\ncmp r9, rax\njnz short loc_1410\nlocret_143A:\nretn", + "ida_strip_pseudo": "void __fastcall sub_13F0(__int64 a1, __int64 a2, int a3, __int64 a4)\n{\n __int64 v4; // rax\n __int64 v5; // r9\n int v6; // edx\n int v7; // edx\n\n if ( a3 > 0 )\n {\n v4 = 0LL;\n v5 = 8LL * a3;\n do\n {\n v6 = *(_DWORD *)(a2 + v4);\n if ( v6 < *(_DWORD *)(a1 + v4) )\n v6 = *(_DWORD *)(a1 + v4);\n *(_DWORD *)(a4 + v4) = v6;\n v7 = *(_DWORD *)(a2 + v4 + 4);\n if ( v7 < *(_DWORD *)(a1 + v4 + 4) )\n v7 = *(_DWORD *)(a1 + v4 + 4);\n *(_DWORD *)(a4 + v4 + 4) = v7;\n v4 += 8LL;\n }\n while ( v5 != v4 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_13F0(long long a1, long long a2, int a3, long long a4) {\n long long v4;\n long long v5;\n int v6;\n int v7;\n if (a3 > 0) {\n v4 = 0LL;\n v5 = 8LL * a3;\n do {\n v6 = *(uint32_t *)(a2 + v4);\n if (v6 < *(uint32_t *)(a1 + v4)) v6 = *(uint32_t *)(a1 + v4);\n *(uint32_t *)(a4 + v4) = v6;\n v7 = *(uint32_t *)(a2 + v4 + 4);\n if (v7 < *(uint32_t *)(a1 + v4 + 4)) v7 = *(uint32_t *)(a1 + v4 + 4);\n *(uint32_t *)(a4 + v4 + 4) = v7;\n v4 += 8LL;\n } while (v5 != v4);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, long long a2, int a3, long long a4) {\n long long v4;\n long long v5;\n int v6;\n int v7;\n if (a3 > 0) {\n v4 = 0LL;\n v5 = 8LL * a3;\n do {\n v6 = *(uint32_t *)(a2 + v4);\n if (v6 < *(uint32_t *)(a1 + v4)) v6 = *(uint32_t *)(a1 + v4);\n *(uint32_t *)(a4 + v4) = v6;\n v7 = *(uint32_t *)(a2 + v4 + 4);\n if (v7 < *(uint32_t *)(a1 + v4 + 4)) v7 = *(uint32_t *)(a1 + v4 + 4);\n *(uint32_t *)(a4 + v4 + 4) = v7;\n v4 += 8LL;\n } while (v5 != v4);\n }\n}" + }, + { + "index": 260, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n == 0 || n == 1) {\n return 1;\n }\n return 2 * func0(n - 1) + func0(n - 2);\n}", + "test": "int main() {\n\n assert(func0(3) == 7);\n\n assert(func0(4) == 17);\n\n assert(func0(5) == 41);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x18,%rsp\nmov %edi,-0x14(%rbp)\ncmpl $0x0,-0x14(%rbp)\nje 1165 \ncmpl $0x1,-0x14(%rbp)\njne 116c \nmov $0x1,%eax\njmp 118b \nmov -0x14(%rbp),%eax\nsub $0x1,%eax\nmov %eax,%edi\ncallq 1149 \nlea (%rax,%rax,1),%ebx\nmov -0x14(%rbp),%eax\nsub $0x2,%eax\nmov %eax,%edi\ncallq 1149 \nadd %ebx,%eax\nadd $0x18,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 18h\nmov [rbp+var_14], edi\ncmp [rbp+var_14], 0\njz short loc_1165\ncmp [rbp+var_14], 1\njnz short loc_116C\nloc_1165:\nmov eax, 1\njmp short loc_118B\nloc_116C:\nmov eax, [rbp+var_14]\nsub eax, 1\nmov edi, eax\ncall func0\nlea ebx, [rax+rax]\nmov eax, [rbp+var_14]\nsub eax, 2\nmov edi, eax\ncall func0\nadd eax, ebx\nloc_118B:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1)\n{\n int v2; // ebx\n\n if ( a1 <= 1 )\n return 1LL;\n v2 = 2 * func0(a1 - 1);\n return v2 + (unsigned int)func0(a1 - 2);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 18h\nmov [rbp+var_14], edi\ncmp [rbp+var_14], 0\njz short loc_1165\ncmp [rbp+var_14], 1\njnz short loc_116C\nloc_1165:\nmov eax, 1\njmp short loc_118B\nloc_116C:\nmov eax, [rbp+var_14]\nsub eax, 1\nmov edi, eax\ncall sub_1149\nlea ebx, [rax+rax]\nmov eax, [rbp+var_14]\nsub eax, 2\nmov edi, eax\ncall sub_1149\nadd eax, ebx\nloc_118B:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(unsigned int a1)\n{\n int v2; // ebx\n\n if ( a1 <= 1 )\n return 1LL;\n v2 = 2 * sub_1149(a1 - 1);\n return v2 + (unsigned int)sub_1149(a1 - 2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(unsigned int a1) {\n int v2;\n if (a1 <= 1) return 1LL;\n v2 = 2 * sub_1149(a1 - 1);\n return v2 + (unsigned int)sub_1149(a1 - 2);\n}", + "ida_pseudo_norm": "long long func0(unsigned int a1) {\n int v2;\n if (a1 <= 1) return 1LL;\n v2 = 2 * func0(a1 - 1);\n return v2 + (unsigned int)func0(a1 - 2);\n}" + }, + { + "index": 260, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n == 0 || n == 1) {\n return 1;\n }\n return 2 * func0(n - 1) + func0(n - 2);\n}", + "test": "int main() {\n\n assert(func0(3) == 7);\n\n assert(func0(4) == 17);\n\n assert(func0(5) == 41);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x1,%eax\ncmp $0x1,%edi\njbe 117b \npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %edi,%ebx\nlea -0x1(%rdi),%edi\ncallq 1149 \nmov %eax,%ebp\nlea -0x2(%rbx),%edi\ncallq 1149 \nlea (%rax,%rbp,2),%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nretq\n", + "ida_asm": "func0:\nendbr64\nmov eax, 1\ncmp edi, 1\njbe short locret_117B\npush rbp\npush rbx\nsub rsp, 8\nmov ebx, edi\nlea edi, [rdi-1]\ncall func0\nmov ebp, eax\nlea edi, [rbx-2]\ncall func0\nlea eax, [rax+rbp*2]\nadd rsp, 8\npop rbx\npop rbp\nretn\nlocret_117B:\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1)\n{\n __int64 result; // rax\n int v2; // ebp\n\n result = 1LL;\n if ( a1 > 1 )\n {\n v2 = func0(a1 - 1);\n return (unsigned int)func0(a1 - 2) + 2 * v2;\n }\n return result;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmov eax, 1\ncmp edi, 1\njbe short locret_117B\npush rbp\npush rbx\nsub rsp, 8\nmov ebx, edi\nlea edi, [rdi-1]\ncall sub_1149\nmov ebp, eax\nlea edi, [rbx-2]\ncall sub_1149\nlea eax, [rax+rbp*2]\nadd rsp, 8\npop rbx\npop rbp\nretn\nlocret_117B:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(unsigned int a1)\n{\n __int64 result; // rax\n int v2; // ebp\n\n result = 1LL;\n if ( a1 > 1 )\n {\n v2 = sub_1149(a1 - 1);\n return (unsigned int)sub_1149(a1 - 2) + 2 * v2;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(unsigned int a1) {\n long long result;\n int v2;\n result = 1LL;\n if (a1 > 1) {\n v2 = sub_1149(a1 - 1);\n return (unsigned int)sub_1149(a1 - 2) + 2 * v2;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(unsigned int a1) {\n long long result;\n int v2;\n result = 1LL;\n if (a1 > 1) {\n v2 = func0(a1 - 1);\n return (unsigned int)func0(a1 - 2) + 2 * v2;\n }\n return result;\n}" + }, + { + "index": 260, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n == 0 || n == 1) {\n return 1;\n }\n return 2 * func0(n - 1) + func0(n - 2);\n}", + "test": "int main() {\n\n assert(func0(3) == 7);\n\n assert(func0(4) == 17);\n\n assert(func0(5) == 41);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%edi\njbe 1248 \npush %rbp\nxor %ebp,%ebp\npush %rbx\nmov %edi,%ebx\nsub $0x8,%rsp\nlea -0x1(%rbx),%edi\nsub $0x2,%ebx\ncallq 1210 \nlea 0x0(%rbp,%rax,2),%ebp\ncmp $0x1,%ebx\nja 1223 \nadd $0x8,%rsp\nlea 0x1(%rbp),%eax\npop %rbx\npop %rbp\nretq\nnopl 0x0(%rax)\nmov $0x1,%eax\nretq\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14d, 1\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 58h\ncmp edi, 1\njbe loc_1576\nlea r15d, [rdi-1]\nxor ebp, ebp\nloc_1217:\ncmp r15d, 1\njz loc_156F\nloc_1221:\nlea r12d, [r15-1]\nxor r14d, r14d\nmov [rsp+88h+var_6C], ebp\nmov r13d, r12d\nmov ebp, r14d\nmov ebx, r12d\nloc_1235:\ncmp ebx, 1\njz loc_1544\nloc_123E:\nmov [rsp+88h+var_64], r15d\nlea ecx, [rbx-1]\nxor r14d, r14d\nmov r12d, ebx\nmov [rsp+88h+var_68], ebp\nmov ebx, ecx\nmov ebp, r14d\nloc_1255:\ncmp ebx, 1\njz loc_1517\nmov [rsp+88h+var_60], r13d\nlea edi, [rbx-1]\nmov eax, r12d\nxor r15d, r15d\nmov [rsp+88h+var_5C], ebx\nmov r12d, edi\nloc_1273:\ncmp r12d, 1\njz loc_14DE\nmov [rsp+88h+var_58], ebp\nlea r11d, [r12-1]\nmov r10d, ecx\nxor r13d, r13d\nmov ecx, r15d\nmov ebx, r11d\nmov r9d, eax\nmov r8d, edi\nmov r15d, r12d\nloc_129B:\ncmp ebx, 1\njz loc_149F\nloc_12A4:\nlea ebp, [rbx-1]\nxor r12d, r12d\nmov edi, ecx\nmov [rsp+88h+var_84], ebp\nmov eax, ebp\nmov ebp, r9d\nloc_12B5:\nmov r14d, eax\ncmp eax, 1\njz loc_1478\nlea esi, [rax-1]\nlea edx, [rax-2]\nmov ecx, r14d\nmov r9d, edi\nmov eax, esi\nmov [rsp+88h+var_88], edx\nmov edi, edx\nand eax, 0FFFFFFFEh\nsub ecx, eax\nmov eax, r14d\nmov [rsp+88h+var_70], ecx\nxor ecx, ecx\nloc_12E2:\nmov edx, [rsp+88h+var_70]\ncmp eax, edx\njz loc_14C0\nmov r14d, edi\nmov [rsp+88h+var_80], r9d\nxor edx, edx\nmov r9d, ebx\nmov [rsp+88h+var_78], ecx\nmov ebx, r14d\nmov ecx, r15d\nmov r15d, ebp\nmov [rsp+88h+var_7C], eax\nmov [rsp+88h+var_74], edi\ncmp r14d, 1\njbe short loc_138A\nloc_1316:\nxor ebp, ebp\nloc_1318:\nlea edi, [rbx-1]\nsub ebx, 2\nmov [rsp+88h+var_3C], esi\nmov [rsp+88h+var_40], r9d\nmov [rsp+88h+var_44], ecx\nmov [rsp+88h+var_48], r11d\nmov [rsp+88h+var_4C], r8d\nmov [rsp+88h+var_50], r10d\nmov [rsp+88h+var_54], edx\ncall func0\ncmp ebx, 1\nmov edx, [rsp+88h+var_54]\nmov ecx, [rsp+88h+var_44]\nmov r10d, [rsp+88h+var_50]\nmov r8d, [rsp+88h+var_4C]\nlea ebp, [rbp+rax*2+0]\nmov r11d, [rsp+88h+var_48]\nmov r9d, [rsp+88h+var_40]\nmov esi, [rsp+88h+var_3C]\nja short loc_1318\nlea edx, [rdx+rbp*2+2]\nlea edi, [r14-2]\ncmp r14d, 2\njz loc_14F8\nmov r14d, edi\nmov ebx, r14d\ncmp r14d, 1\nja short loc_1316\nloc_138A:\nmov ebp, r15d\nmov ebx, r9d\nmov r15d, ecx\nmov eax, [rsp+88h+var_7C]\nmov ecx, [rsp+88h+var_78]\nmov r9d, [rsp+88h+var_80]\nadd edx, 2\nmov edi, [rsp+88h+var_74]\nloc_13A7:\nsub eax, 2\nlea ecx, [rcx+rdx*2+2]\nsub edi, 2\ncmp eax, 1\njnz loc_12E2\nmov edx, [rsp+88h+var_88]\nmov edi, r9d\nlea r12d, [r12+rcx*2+2]\ncmp esi, 1\njnz loc_14D7\nloc_13CE:\nmov r9d, ebp\nmov ebp, [rsp+88h+var_84]\nmov ecx, edi\nlea r13d, [r13+r12*2+2]\nsub ebx, 2\ncmp ebp, 1\njnz loc_129B\nloc_13E8:\nmov ebp, [rsp+88h+var_58]\nmov r12d, r15d\nmov eax, r9d\nmov r15d, ecx\nmov edi, r8d\nmov ecx, r10d\nloc_13FB:\nlea r15d, [r15+r13*2+2]\nsub r12d, 2\ncmp r11d, 1\njnz loc_1273\nmov r13d, [rsp+88h+var_60]\nmov ebx, [rsp+88h+var_5C]\nmov r12d, eax\nloc_141A:\nlea ebp, [rbp+r15*2+2]\nsub ebx, 2\ncmp edi, 1\njnz loc_1255\nmov r14d, ebp\nmov ebp, [rsp+88h+var_68]\nmov ebx, r12d\nmov r15d, [rsp+88h+var_64]\nsub ebx, 2\nlea ebp, [rbp+r14*2+2]\ncmp ecx, 1\njnz loc_1235\nloc_144B:\nmov r14d, ebp\nmov ebp, [rsp+88h+var_6C]\nmov r12d, r13d\nsub r15d, 2\nlea ebp, [rbp+r14*2+2]\ncmp r12d, 1\njnz loc_1217\nloc_1468:\nmov r14d, ebp\nadd r14d, 1\njmp loc_1576\nloc_1478:\nmov r9d, ebp\nmov ebp, [rsp+88h+var_84]\nadd r12d, 2\nmov ecx, edi\nlea r13d, [r13+r12*2+2]\nsub ebx, 2\ncmp ebp, 1\njz loc_13E8\ncmp ebx, 1\njnz loc_12A4\nloc_149F:\nmov r12d, r15d\nmov ebp, [rsp+88h+var_58]\nmov r15d, ecx\nmov eax, r9d\nmov edi, r8d\nmov ecx, r10d\nadd r13d, 2\njmp loc_13FB\nloc_14C0:\nadd ecx, 2\nmov edx, [rsp+88h+var_88]\nmov edi, r9d\nlea r12d, [r12+rcx*2+2]\ncmp esi, 1\njz loc_13CE\nloc_14D7:\nmov eax, edx\njmp loc_12B5\nloc_14DE:\nmov r13d, [rsp+88h+var_60]\nmov ebx, [rsp+88h+var_5C]\nmov r12d, eax\nadd r15d, 2\njmp loc_141A\nloc_14F8:\nmov ebp, r15d\nmov ebx, r9d\nmov r15d, ecx\nmov eax, [rsp+88h+var_7C]\nmov ecx, [rsp+88h+var_78]\nmov r9d, [rsp+88h+var_80]\nmov edi, [rsp+88h+var_74]\njmp loc_13A7\nloc_1517:\nmov r14d, ebp\nmov ebp, [rsp+88h+var_68]\nmov ebx, r12d\nmov r15d, [rsp+88h+var_64]\nadd r14d, 2\nsub ebx, 2\nlea ebp, [rbp+r14*2+2]\ncmp ecx, 1\njz loc_144B\ncmp ebx, 1\njnz loc_123E\nloc_1544:\nmov r14d, ebp\nmov ebp, [rsp+88h+var_6C]\nmov r12d, r13d\nsub r15d, 2\nadd r14d, 2\nlea ebp, [rbp+r14*2+2]\ncmp r12d, 1\njz loc_1468\ncmp r15d, 1\njnz loc_1221\nloc_156F:\nmov r14d, ebp\nadd r14d, 3\nloc_1576:\nadd rsp, 58h\nmov eax, r14d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1)\n{\n unsigned int v1; // r14d\n unsigned int v2; // r15d\n int v3; // ebp\n unsigned int v4; // r13d\n int v5; // ebp\n unsigned int v6; // ebx\n unsigned int v7; // ecx\n unsigned int v8; // r12d\n unsigned int v9; // ebx\n int v10; // ebp\n unsigned int v11; // edi\n unsigned int v12; // eax\n int v13; // r15d\n unsigned int v14; // r12d\n unsigned int v15; // r11d\n unsigned int v16; // r10d\n int v17; // r13d\n int v18; // ecx\n unsigned int v19; // ebx\n unsigned int v20; // r9d\n unsigned int v21; // r8d\n unsigned int v22; // r15d\n int v23; // r12d\n int v24; // edi\n unsigned int v25; // eax\n unsigned int v26; // ebp\n unsigned int v27; // esi\n int v28; // r9d\n unsigned int v29; // edi\n int v30; // ecx\n unsigned int v31; // r14d\n int v32; // edx\n unsigned int v33; // r9d\n unsigned int v34; // ebx\n unsigned int v35; // ecx\n unsigned int v36; // r15d\n int v37; // ebp\n __int64 v38; // rdi\n int v39; // eax\n unsigned int v40; // edi\n unsigned int v41; // eax\n int v42; // ecx\n unsigned int v43; // edi\n unsigned int v44; // edx\n unsigned int v45; // r12d\n int v46; // r15d\n unsigned int v47; // ebx\n unsigned int v49; // [rsp+0h] [rbp-88h]\n unsigned int v50; // [rsp+4h] [rbp-84h]\n int v51; // [rsp+8h] [rbp-80h]\n unsigned int v52; // [rsp+Ch] [rbp-7Ch]\n int v53; // [rsp+10h] [rbp-78h]\n unsigned int v54; // [rsp+14h] [rbp-74h]\n unsigned int v55; // [rsp+18h] [rbp-70h]\n int v56; // [rsp+1Ch] [rbp-6Ch]\n int v57; // [rsp+20h] [rbp-68h]\n unsigned int v58; // [rsp+24h] [rbp-64h]\n unsigned int v59; // [rsp+28h] [rbp-60h]\n unsigned int v60; // [rsp+2Ch] [rbp-5Ch]\n int v61; // [rsp+30h] [rbp-58h]\n int v62; // [rsp+34h] [rbp-54h]\n unsigned int v63; // [rsp+38h] [rbp-50h]\n unsigned int v64; // [rsp+3Ch] [rbp-4Ch]\n unsigned int v65; // [rsp+40h] [rbp-48h]\n unsigned int v66; // [rsp+44h] [rbp-44h]\n unsigned int v67; // [rsp+48h] [rbp-40h]\n\n v1 = 1;\n if ( a1 > 1 )\n {\n v2 = a1 - 1;\n v3 = 0;\nLABEL_3:\n if ( v2 == 1 )\n {\n return (unsigned int)(v3 + 3);\n }\n else\n {\n while ( 1 )\n {\n v56 = v3;\n v4 = v2 - 1;\n v5 = 0;\n v6 = v2 - 1;\nLABEL_5:\n if ( v6 != 1 )\n {\n while ( 2 )\n {\n v58 = v2;\n v7 = v6 - 1;\n v8 = v6;\n v57 = v5;\n v9 = v6 - 1;\n v10 = 0;\n while ( v9 != 1 )\n {\n v59 = v4;\n v11 = v9 - 1;\n v12 = v8;\n v13 = 0;\n v60 = v9;\n v14 = v9 - 1;\n while ( v14 != 1 )\n {\n v61 = v10;\n v15 = v14 - 1;\n v16 = v7;\n v17 = 0;\n v18 = v13;\n v19 = v14 - 1;\n v20 = v12;\n v21 = v11;\n v22 = v14;\n while ( 2 )\n {\n if ( v19 == 1 )\n {\nLABEL_34:\n v45 = v22;\n v10 = v61;\n v46 = v18;\n v12 = v20;\n v11 = v21;\n v7 = v16;\n v17 += 2;\n goto LABEL_26;\n }\n while ( 1 )\n {\n v23 = 0;\n v24 = v18;\n v50 = v19 - 1;\n v25 = v19 - 1;\n v26 = v20;\nLABEL_13:\n if ( v25 != 1 )\n break;\n v20 = v26;\n v18 = v24;\n v17 += 2 * (v23 + 2) + 2;\n v19 -= 2;\n if ( v50 == 1 )\n goto LABEL_25;\n if ( v19 == 1 )\n goto LABEL_34;\n }\n v27 = v25 - 1;\n v28 = v24;\n v49 = v25 - 2;\n v29 = v25 - 2;\n v55 = v25 - ((v25 - 1) & 0xFFFFFFFE);\n v30 = 0;\n do\n {\n if ( v25 == v55 )\n {\n v44 = v49;\n v24 = v28;\n v23 += 2 * (v30 + 2) + 2;\n if ( v27 == 1 )\n goto LABEL_24;\nLABEL_36:\n v25 = v44;\n goto LABEL_13;\n }\n v31 = v29;\n v51 = v28;\n v32 = 0;\n v33 = v19;\n v53 = v30;\n v34 = v29;\n v35 = v22;\n v36 = v26;\n v52 = v25;\n v54 = v29;\n if ( v29 <= 1 )\n {\nLABEL_21:\n v26 = v36;\n v19 = v33;\n v22 = v35;\n v41 = v52;\n v42 = v53;\n v28 = v51;\n v32 += 2;\n v43 = v54;\n }\n else\n {\n while ( 1 )\n {\n v37 = 0;\n do\n {\n v38 = v34 - 1;\n v34 -= 2;\n v67 = v33;\n v66 = v35;\n v65 = v15;\n v64 = v21;\n v63 = v16;\n v62 = v32;\n v39 = func0(v38);\n v32 = v62;\n v35 = v66;\n v16 = v63;\n v21 = v64;\n v37 += 2 * v39;\n v15 = v65;\n v33 = v67;\n }\n while ( v34 > 1 );\n v32 = v62 + 2 * v37 + 2;\n v40 = v31 - 2;\n if ( v31 == 2 )\n break;\n v31 -= 2;\n v34 = v40;\n if ( v40 <= 1 )\n goto LABEL_21;\n }\n v26 = v36;\n v19 = v67;\n v22 = v66;\n v41 = v52;\n v42 = v53;\n v28 = v51;\n v43 = v54;\n }\n v25 = v41 - 2;\n v30 = v42 + 2 * v32 + 2;\n v29 = v43 - 2;\n }\n while ( v25 != 1 );\n v44 = v49;\n v24 = v28;\n v23 += 2 * v30 + 2;\n if ( v27 != 1 )\n goto LABEL_36;\nLABEL_24:\n v20 = v26;\n v18 = v24;\n v17 += 2 * v23 + 2;\n v19 -= 2;\n if ( v50 != 1 )\n continue;\n break;\n }\nLABEL_25:\n v10 = v61;\n v45 = v22;\n v12 = v20;\n v46 = v18;\n v11 = v21;\n v7 = v16;\nLABEL_26:\n v13 = v46 + 2 * v17 + 2;\n v14 = v45 - 2;\n if ( v15 == 1 )\n {\n v4 = v59;\n v47 = v60;\n v8 = v12;\n goto LABEL_28;\n }\n }\n v4 = v59;\n v47 = v60;\n v8 = v12;\n v13 += 2;\nLABEL_28:\n v10 += 2 * v13 + 2;\n v9 = v47 - 2;\n if ( v11 == 1 )\n {\n v2 = v58;\n v6 = v8 - 2;\n v5 = v57 + 2 * v10 + 2;\n if ( v7 != 1 )\n goto LABEL_5;\nLABEL_30:\n v2 -= 2;\n v3 = v56 + 2 * v5 + 2;\n if ( v4 != 1 )\n goto LABEL_3;\n return (unsigned int)(v3 + 1);\n }\n }\n v2 = v58;\n v6 = v8 - 2;\n v5 = v57 + 2 * (v10 + 2) + 2;\n if ( v7 == 1 )\n goto LABEL_30;\n if ( v8 != 3 )\n continue;\n break;\n }\n }\n v2 -= 2;\n v3 = v56 + 2 * (v5 + 2) + 2;\n if ( v4 == 1 )\n return (unsigned int)(v3 + 1);\n if ( v2 == 1 )\n return (unsigned int)(v3 + 3);\n }\n }\n }\n return v1;\n}", + "ida_strip_asm": "sub_11F0:\nendbr64\npush r15\npush r14\nmov r14d, 1\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 58h\ncmp edi, 1\njbe loc_1576\nlea r15d, [rdi-1]\nxor ebp, ebp\nloc_1217:\ncmp r15d, 1\njz loc_156F\nloc_1221:\nlea r12d, [r15-1]\nxor r14d, r14d\nmov [rsp+88h+var_6C], ebp\nmov r13d, r12d\nmov ebp, r14d\nmov ebx, r12d\nloc_1235:\ncmp ebx, 1\njz loc_1544\nloc_123E:\nmov [rsp+88h+var_64], r15d\nlea ecx, [rbx-1]\nxor r14d, r14d\nmov r12d, ebx\nmov [rsp+88h+var_68], ebp\nmov ebx, ecx\nmov ebp, r14d\nloc_1255:\ncmp ebx, 1\njz loc_1517\nmov [rsp+88h+var_60], r13d\nlea edi, [rbx-1]\nmov eax, r12d\nxor r15d, r15d\nmov [rsp+88h+var_5C], ebx\nmov r12d, edi\nloc_1273:\ncmp r12d, 1\njz loc_14DE\nmov [rsp+88h+var_58], ebp\nlea r11d, [r12-1]\nmov r10d, ecx\nxor r13d, r13d\nmov ecx, r15d\nmov ebx, r11d\nmov r9d, eax\nmov r8d, edi\nmov r15d, r12d\nloc_129B:\ncmp ebx, 1\njz loc_149F\nloc_12A4:\nlea ebp, [rbx-1]\nxor r12d, r12d\nmov edi, ecx\nmov [rsp+88h+var_84], ebp\nmov eax, ebp\nmov ebp, r9d\nloc_12B5:\nmov r14d, eax\ncmp eax, 1\njz loc_1478\nlea esi, [rax-1]\nlea edx, [rax-2]\nmov ecx, r14d\nmov r9d, edi\nmov eax, esi\nmov [rsp+88h+var_88], edx\nmov edi, edx\nand eax, 0FFFFFFFEh\nsub ecx, eax\nmov eax, r14d\nmov [rsp+88h+var_70], ecx\nxor ecx, ecx\nloc_12E2:\nmov edx, [rsp+88h+var_70]\ncmp eax, edx\njz loc_14C0\nmov r14d, edi\nmov [rsp+88h+var_80], r9d\nxor edx, edx\nmov r9d, ebx\nmov [rsp+88h+var_78], ecx\nmov ebx, r14d\nmov ecx, r15d\nmov r15d, ebp\nmov [rsp+88h+var_7C], eax\nmov [rsp+88h+var_74], edi\ncmp r14d, 1\njbe short loc_138A\nloc_1316:\nxor ebp, ebp\nloc_1318:\nlea edi, [rbx-1]\nsub ebx, 2\nmov [rsp+88h+var_3C], esi\nmov [rsp+88h+var_40], r9d\nmov [rsp+88h+var_44], ecx\nmov [rsp+88h+var_48], r11d\nmov [rsp+88h+var_4C], r8d\nmov [rsp+88h+var_50], r10d\nmov [rsp+88h+var_54], edx\ncall sub_11F0\ncmp ebx, 1\nmov edx, [rsp+88h+var_54]\nmov ecx, [rsp+88h+var_44]\nmov r10d, [rsp+88h+var_50]\nmov r8d, [rsp+88h+var_4C]\nlea ebp, [rbp+rax*2+0]\nmov r11d, [rsp+88h+var_48]\nmov r9d, [rsp+88h+var_40]\nmov esi, [rsp+88h+var_3C]\nja short loc_1318\nlea edx, [rdx+rbp*2+2]\nlea edi, [r14-2]\ncmp r14d, 2\njz loc_14F8\nmov r14d, edi\nmov ebx, r14d\ncmp r14d, 1\nja short loc_1316\nloc_138A:\nmov ebp, r15d\nmov ebx, r9d\nmov r15d, ecx\nmov eax, [rsp+88h+var_7C]\nmov ecx, [rsp+88h+var_78]\nmov r9d, [rsp+88h+var_80]\nadd edx, 2\nmov edi, [rsp+88h+var_74]\nloc_13A7:\nsub eax, 2\nlea ecx, [rcx+rdx*2+2]\nsub edi, 2\ncmp eax, 1\njnz loc_12E2\nmov edx, [rsp+88h+var_88]\nmov edi, r9d\nlea r12d, [r12+rcx*2+2]\ncmp esi, 1\njnz loc_14D7\nloc_13CE:\nmov r9d, ebp\nmov ebp, [rsp+88h+var_84]\nmov ecx, edi\nlea r13d, [r13+r12*2+2]\nsub ebx, 2\ncmp ebp, 1\njnz loc_129B\nloc_13E8:\nmov ebp, [rsp+88h+var_58]\nmov r12d, r15d\nmov eax, r9d\nmov r15d, ecx\nmov edi, r8d\nmov ecx, r10d\nloc_13FB:\nlea r15d, [r15+r13*2+2]\nsub r12d, 2\ncmp r11d, 1\njnz loc_1273\nmov r13d, [rsp+88h+var_60]\nmov ebx, [rsp+88h+var_5C]\nmov r12d, eax\nloc_141A:\nlea ebp, [rbp+r15*2+2]\nsub ebx, 2\ncmp edi, 1\njnz loc_1255\nmov r14d, ebp\nmov ebp, [rsp+88h+var_68]\nmov ebx, r12d\nmov r15d, [rsp+88h+var_64]\nsub ebx, 2\nlea ebp, [rbp+r14*2+2]\ncmp ecx, 1\njnz loc_1235\nloc_144B:\nmov r14d, ebp\nmov ebp, [rsp+88h+var_6C]\nmov r12d, r13d\nsub r15d, 2\nlea ebp, [rbp+r14*2+2]\ncmp r12d, 1\njnz loc_1217\nloc_1468:\nmov r14d, ebp\nadd r14d, 1\njmp loc_1576\nloc_1478:\nmov r9d, ebp\nmov ebp, [rsp+88h+var_84]\nadd r12d, 2\nmov ecx, edi\nlea r13d, [r13+r12*2+2]\nsub ebx, 2\ncmp ebp, 1\njz loc_13E8\ncmp ebx, 1\njnz loc_12A4\nloc_149F:\nmov r12d, r15d\nmov ebp, [rsp+88h+var_58]\nmov r15d, ecx\nmov eax, r9d\nmov edi, r8d\nmov ecx, r10d\nadd r13d, 2\njmp loc_13FB\nloc_14C0:\nadd ecx, 2\nmov edx, [rsp+88h+var_88]\nmov edi, r9d\nlea r12d, [r12+rcx*2+2]\ncmp esi, 1\njz loc_13CE\nloc_14D7:\nmov eax, edx\njmp loc_12B5\nloc_14DE:\nmov r13d, [rsp+88h+var_60]\nmov ebx, [rsp+88h+var_5C]\nmov r12d, eax\nadd r15d, 2\njmp loc_141A\nloc_14F8:\nmov ebp, r15d\nmov ebx, r9d\nmov r15d, ecx\nmov eax, [rsp+88h+var_7C]\nmov ecx, [rsp+88h+var_78]\nmov r9d, [rsp+88h+var_80]\nmov edi, [rsp+88h+var_74]\njmp loc_13A7\nloc_1517:\nmov r14d, ebp\nmov ebp, [rsp+88h+var_68]\nmov ebx, r12d\nmov r15d, [rsp+88h+var_64]\nadd r14d, 2\nsub ebx, 2\nlea ebp, [rbp+r14*2+2]\ncmp ecx, 1\njz loc_144B\ncmp ebx, 1\njnz loc_123E\nloc_1544:\nmov r14d, ebp\nmov ebp, [rsp+88h+var_6C]\nmov r12d, r13d\nsub r15d, 2\nadd r14d, 2\nlea ebp, [rbp+r14*2+2]\ncmp r12d, 1\njz loc_1468\ncmp r15d, 1\njnz loc_1221\nloc_156F:\nmov r14d, ebp\nadd r14d, 3\nloc_1576:\nadd rsp, 58h\nmov eax, r14d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11F0(unsigned int a1)\n{\n unsigned int v1; // r14d\n unsigned int v2; // r15d\n int v3; // ebp\n unsigned int v4; // r13d\n int v5; // ebp\n unsigned int v6; // ebx\n unsigned int v7; // ecx\n unsigned int v8; // r12d\n unsigned int v9; // ebx\n int v10; // ebp\n unsigned int v11; // edi\n unsigned int v12; // eax\n int v13; // r15d\n unsigned int v14; // r12d\n unsigned int v15; // r11d\n unsigned int v16; // r10d\n int v17; // r13d\n int v18; // ecx\n unsigned int v19; // ebx\n unsigned int v20; // r9d\n unsigned int v21; // r8d\n unsigned int v22; // r15d\n int v23; // r12d\n int v24; // edi\n unsigned int v25; // eax\n unsigned int v26; // ebp\n unsigned int v27; // esi\n int v28; // r9d\n unsigned int v29; // edi\n int v30; // ecx\n unsigned int v31; // r14d\n int v32; // edx\n unsigned int v33; // r9d\n unsigned int v34; // ebx\n unsigned int v35; // ecx\n unsigned int v36; // r15d\n int v37; // ebp\n __int64 v38; // rdi\n int v39; // eax\n unsigned int v40; // edi\n unsigned int v41; // eax\n int v42; // ecx\n unsigned int v43; // edi\n unsigned int v44; // edx\n unsigned int v45; // r12d\n int v46; // r15d\n unsigned int v47; // ebx\n unsigned int v49; // [rsp+0h] [rbp-88h]\n unsigned int v50; // [rsp+4h] [rbp-84h]\n int v51; // [rsp+8h] [rbp-80h]\n unsigned int v52; // [rsp+Ch] [rbp-7Ch]\n int v53; // [rsp+10h] [rbp-78h]\n unsigned int v54; // [rsp+14h] [rbp-74h]\n unsigned int v55; // [rsp+18h] [rbp-70h]\n int v56; // [rsp+1Ch] [rbp-6Ch]\n int v57; // [rsp+20h] [rbp-68h]\n unsigned int v58; // [rsp+24h] [rbp-64h]\n unsigned int v59; // [rsp+28h] [rbp-60h]\n unsigned int v60; // [rsp+2Ch] [rbp-5Ch]\n int v61; // [rsp+30h] [rbp-58h]\n int v62; // [rsp+34h] [rbp-54h]\n unsigned int v63; // [rsp+38h] [rbp-50h]\n unsigned int v64; // [rsp+3Ch] [rbp-4Ch]\n unsigned int v65; // [rsp+40h] [rbp-48h]\n unsigned int v66; // [rsp+44h] [rbp-44h]\n unsigned int v67; // [rsp+48h] [rbp-40h]\n\n v1 = 1;\n if ( a1 > 1 )\n {\n v2 = a1 - 1;\n v3 = 0;\nLABEL_3:\n if ( v2 == 1 )\n {\n return (unsigned int)(v3 + 3);\n }\n else\n {\n while ( 1 )\n {\n v56 = v3;\n v4 = v2 - 1;\n v5 = 0;\n v6 = v2 - 1;\nLABEL_5:\n if ( v6 != 1 )\n {\n while ( 2 )\n {\n v58 = v2;\n v7 = v6 - 1;\n v8 = v6;\n v57 = v5;\n v9 = v6 - 1;\n v10 = 0;\n while ( v9 != 1 )\n {\n v59 = v4;\n v11 = v9 - 1;\n v12 = v8;\n v13 = 0;\n v60 = v9;\n v14 = v9 - 1;\n while ( v14 != 1 )\n {\n v61 = v10;\n v15 = v14 - 1;\n v16 = v7;\n v17 = 0;\n v18 = v13;\n v19 = v14 - 1;\n v20 = v12;\n v21 = v11;\n v22 = v14;\n while ( 2 )\n {\n if ( v19 == 1 )\n {\nLABEL_34:\n v45 = v22;\n v10 = v61;\n v46 = v18;\n v12 = v20;\n v11 = v21;\n v7 = v16;\n v17 += 2;\n goto LABEL_26;\n }\n while ( 1 )\n {\n v23 = 0;\n v24 = v18;\n v50 = v19 - 1;\n v25 = v19 - 1;\n v26 = v20;\nLABEL_13:\n if ( v25 != 1 )\n break;\n v20 = v26;\n v18 = v24;\n v17 += 2 * (v23 + 2) + 2;\n v19 -= 2;\n if ( v50 == 1 )\n goto LABEL_25;\n if ( v19 == 1 )\n goto LABEL_34;\n }\n v27 = v25 - 1;\n v28 = v24;\n v49 = v25 - 2;\n v29 = v25 - 2;\n v55 = v25 - ((v25 - 1) & 0xFFFFFFFE);\n v30 = 0;\n do\n {\n if ( v25 == v55 )\n {\n v44 = v49;\n v24 = v28;\n v23 += 2 * (v30 + 2) + 2;\n if ( v27 == 1 )\n goto LABEL_24;\nLABEL_36:\n v25 = v44;\n goto LABEL_13;\n }\n v31 = v29;\n v51 = v28;\n v32 = 0;\n v33 = v19;\n v53 = v30;\n v34 = v29;\n v35 = v22;\n v36 = v26;\n v52 = v25;\n v54 = v29;\n if ( v29 <= 1 )\n {\nLABEL_21:\n v26 = v36;\n v19 = v33;\n v22 = v35;\n v41 = v52;\n v42 = v53;\n v28 = v51;\n v32 += 2;\n v43 = v54;\n }\n else\n {\n while ( 1 )\n {\n v37 = 0;\n do\n {\n v38 = v34 - 1;\n v34 -= 2;\n v67 = v33;\n v66 = v35;\n v65 = v15;\n v64 = v21;\n v63 = v16;\n v62 = v32;\n v39 = sub_11F0(v38);\n v32 = v62;\n v35 = v66;\n v16 = v63;\n v21 = v64;\n v37 += 2 * v39;\n v15 = v65;\n v33 = v67;\n }\n while ( v34 > 1 );\n v32 = v62 + 2 * v37 + 2;\n v40 = v31 - 2;\n if ( v31 == 2 )\n break;\n v31 -= 2;\n v34 = v40;\n if ( v40 <= 1 )\n goto LABEL_21;\n }\n v26 = v36;\n v19 = v67;\n v22 = v66;\n v41 = v52;\n v42 = v53;\n v28 = v51;\n v43 = v54;\n }\n v25 = v41 - 2;\n v30 = v42 + 2 * v32 + 2;\n v29 = v43 - 2;\n }\n while ( v25 != 1 );\n v44 = v49;\n v24 = v28;\n v23 += 2 * v30 + 2;\n if ( v27 != 1 )\n goto LABEL_36;\nLABEL_24:\n v20 = v26;\n v18 = v24;\n v17 += 2 * v23 + 2;\n v19 -= 2;\n if ( v50 != 1 )\n continue;\n break;\n }\nLABEL_25:\n v10 = v61;\n v45 = v22;\n v12 = v20;\n v46 = v18;\n v11 = v21;\n v7 = v16;\nLABEL_26:\n v13 = v46 + 2 * v17 + 2;\n v14 = v45 - 2;\n if ( v15 == 1 )\n {\n v4 = v59;\n v47 = v60;\n v8 = v12;\n goto LABEL_28;\n }\n }\n v4 = v59;\n v47 = v60;\n v8 = v12;\n v13 += 2;\nLABEL_28:\n v10 += 2 * v13 + 2;\n v9 = v47 - 2;\n if ( v11 == 1 )\n {\n v2 = v58;\n v6 = v8 - 2;\n v5 = v57 + 2 * v10 + 2;\n if ( v7 != 1 )\n goto LABEL_5;\nLABEL_30:\n v2 -= 2;\n v3 = v56 + 2 * v5 + 2;\n if ( v4 != 1 )\n goto LABEL_3;\n return (unsigned int)(v3 + 1);\n }\n }\n v2 = v58;\n v6 = v8 - 2;\n v5 = v57 + 2 * (v10 + 2) + 2;\n if ( v7 == 1 )\n goto LABEL_30;\n if ( v8 != 3 )\n continue;\n break;\n }\n }\n v2 -= 2;\n v3 = v56 + 2 * (v5 + 2) + 2;\n if ( v4 == 1 )\n return (unsigned int)(v3 + 1);\n if ( v2 == 1 )\n return (unsigned int)(v3 + 3);\n }\n }\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11F0(unsigned int a1) {\n unsigned int v1;\n unsigned int v2;\n int v3;\n unsigned int v4;\n int v5;\n unsigned int v6;\n unsigned int v7;\n unsigned int v8;\n unsigned int v9;\n int v10;\n unsigned int v11;\n unsigned int v12;\n int v13;\n unsigned int v14;\n unsigned int v15;\n unsigned int v16;\n int v17;\n int v18;\n unsigned int v19;\n unsigned int v20;\n unsigned int v21;\n unsigned int v22;\n int v23;\n int v24;\n unsigned int v25;\n unsigned int v26;\n unsigned int v27;\n int v28;\n unsigned int v29;\n int v30;\n unsigned int v31;\n int v32;\n unsigned int v33;\n unsigned int v34;\n unsigned int v35;\n unsigned int v36;\n int v37;\n long long v38;\n int v39;\n unsigned int v40;\n unsigned int v41;\n int v42;\n unsigned int v43;\n unsigned int v44;\n unsigned int v45;\n int v46;\n unsigned int v47;\n unsigned int v49;\n unsigned int v50;\n int v51;\n unsigned int v52;\n int v53;\n unsigned int v54;\n unsigned int v55;\n int v56;\n int v57;\n unsigned int v58;\n unsigned int v59;\n unsigned int v60;\n int v61;\n int v62;\n unsigned int v63;\n unsigned int v64;\n unsigned int v65;\n unsigned int v66;\n unsigned int v67;\n v1 = 1;\n if (a1 > 1) {\n v2 = a1 - 1;\n v3 = 0;\n LABEL_3:\n if (v2 == 1) {\n return (unsigned int)(v3 + 3);\n } else {\n while (1) {\n v56 = v3;\n v4 = v2 - 1;\n v5 = 0;\n v6 = v2 - 1;\n LABEL_5:\n if (v6 != 1) {\n while (2) {\n v58 = v2;\n v7 = v6 - 1;\n v8 = v6;\n v57 = v5;\n v9 = v6 - 1;\n v10 = 0;\n while (v9 != 1) {\n v59 = v4;\n v11 = v9 - 1;\n v12 = v8;\n v13 = 0;\n v60 = v9;\n v14 = v9 - 1;\n while (v14 != 1) {\n v61 = v10;\n v15 = v14 - 1;\n v16 = v7;\n v17 = 0;\n v18 = v13;\n v19 = v14 - 1;\n v20 = v12;\n v21 = v11;\n v22 = v14;\n while (2) {\n if (v19 == 1) {\n LABEL_34:\n v45 = v22;\n v10 = v61;\n v46 = v18;\n v12 = v20;\n v11 = v21;\n v7 = v16;\n v17 += 2;\n goto LABEL_26;\n }\n while (1) {\n v23 = 0;\n v24 = v18;\n v50 = v19 - 1;\n v25 = v19 - 1;\n v26 = v20;\n LABEL_13:\n if (v25 != 1) break;\n v20 = v26;\n v18 = v24;\n v17 += 2 * (v23 + 2) + 2;\n v19 -= 2;\n if (v50 == 1) goto LABEL_25;\n if (v19 == 1) goto LABEL_34;\n }\n v27 = v25 - 1;\n v28 = v24;\n v49 = v25 - 2;\n v29 = v25 - 2;\n v55 = v25 - ((v25 - 1) & 4294967294);\n v30 = 0;\n do {\n if (v25 == v55) {\n v44 = v49;\n v24 = v28;\n v23 += 2 * (v30 + 2) + 2;\n if (v27 == 1) goto LABEL_24;\n LABEL_36:\n v25 = v44;\n goto LABEL_13;\n }\n v31 = v29;\n v51 = v28;\n v32 = 0;\n v33 = v19;\n v53 = v30;\n v34 = v29;\n v35 = v22;\n v36 = v26;\n v52 = v25;\n v54 = v29;\n if (v29 <= 1) {\n LABEL_21:\n v26 = v36;\n v19 = v33;\n v22 = v35;\n v41 = v52;\n v42 = v53;\n v28 = v51;\n v32 += 2;\n v43 = v54;\n } else {\n while (1) {\n v37 = 0;\n do {\n v38 = v34 - 1;\n v34 -= 2;\n v67 = v33;\n v66 = v35;\n v65 = v15;\n v64 = v21;\n v63 = v16;\n v62 = v32;\n v39 = sub_11F0(v38);\n v32 = v62;\n v35 = v66;\n v16 = v63;\n v21 = v64;\n v37 += 2 * v39;\n v15 = v65;\n v33 = v67;\n } while (v34 > 1);\n v32 = v62 + 2 * v37 + 2;\n v40 = v31 - 2;\n if (v31 == 2) break;\n v31 -= 2;\n v34 = v40;\n if (v40 <= 1) goto LABEL_21;\n }\n v26 = v36;\n v19 = v67;\n v22 = v66;\n v41 = v52;\n v42 = v53;\n v28 = v51;\n v43 = v54;\n }\n v25 = v41 - 2;\n v30 = v42 + 2 * v32 + 2;\n v29 = v43 - 2;\n } while (v25 != 1);\n v44 = v49;\n v24 = v28;\n v23 += 2 * v30 + 2;\n if (v27 != 1) goto LABEL_36;\n LABEL_24:\n v20 = v26;\n v18 = v24;\n v17 += 2 * v23 + 2;\n v19 -= 2;\n if (v50 != 1) continue;\n break;\n }\n LABEL_25:\n v10 = v61;\n v45 = v22;\n v12 = v20;\n v46 = v18;\n v11 = v21;\n v7 = v16;\n LABEL_26:\n v13 = v46 + 2 * v17 + 2;\n v14 = v45 - 2;\n if (v15 == 1) {\n v4 = v59;\n v47 = v60;\n v8 = v12;\n goto LABEL_28;\n }\n }\n v4 = v59;\n v47 = v60;\n v8 = v12;\n v13 += 2;\n LABEL_28:\n v10 += 2 * v13 + 2;\n v9 = v47 - 2;\n if (v11 == 1) {\n v2 = v58;\n v6 = v8 - 2;\n v5 = v57 + 2 * v10 + 2;\n if (v7 != 1) goto LABEL_5;\n LABEL_30:\n v2 -= 2;\n v3 = v56 + 2 * v5 + 2;\n if (v4 != 1) goto LABEL_3;\n return (unsigned int)(v3 + 1);\n }\n }\n v2 = v58;\n v6 = v8 - 2;\n v5 = v57 + 2 * (v10 + 2) + 2;\n if (v7 == 1) goto LABEL_30;\n if (v8 != 3) continue;\n break;\n }\n }\n v2 -= 2;\n v3 = v56 + 2 * (v5 + 2) + 2;\n if (v4 == 1) return (unsigned int)(v3 + 1);\n if (v2 == 1) return (unsigned int)(v3 + 3);\n }\n }\n }\n return v1;\n}", + "ida_pseudo_norm": "long long func0(unsigned int a1) {\n unsigned int v1;\n unsigned int v2;\n int v3;\n unsigned int v4;\n int v5;\n unsigned int v6;\n unsigned int v7;\n unsigned int v8;\n unsigned int v9;\n int v10;\n unsigned int v11;\n unsigned int v12;\n int v13;\n unsigned int v14;\n unsigned int v15;\n unsigned int v16;\n int v17;\n int v18;\n unsigned int v19;\n unsigned int v20;\n unsigned int v21;\n unsigned int v22;\n int v23;\n int v24;\n unsigned int v25;\n unsigned int v26;\n unsigned int v27;\n int v28;\n unsigned int v29;\n int v30;\n unsigned int v31;\n int v32;\n unsigned int v33;\n unsigned int v34;\n unsigned int v35;\n unsigned int v36;\n int v37;\n long long v38;\n int v39;\n unsigned int v40;\n unsigned int v41;\n int v42;\n unsigned int v43;\n unsigned int v44;\n unsigned int v45;\n int v46;\n unsigned int v47;\n unsigned int v49;\n unsigned int v50;\n int v51;\n unsigned int v52;\n int v53;\n unsigned int v54;\n unsigned int v55;\n int v56;\n int v57;\n unsigned int v58;\n unsigned int v59;\n unsigned int v60;\n int v61;\n int v62;\n unsigned int v63;\n unsigned int v64;\n unsigned int v65;\n unsigned int v66;\n unsigned int v67;\n v1 = 1;\n if (a1 > 1) {\n v2 = a1 - 1;\n v3 = 0;\n LABEL_3:\n if (v2 == 1) {\n return (unsigned int)(v3 + 3);\n } else {\n while (1) {\n v56 = v3;\n v4 = v2 - 1;\n v5 = 0;\n v6 = v2 - 1;\n LABEL_5:\n if (v6 != 1) {\n while (2) {\n v58 = v2;\n v7 = v6 - 1;\n v8 = v6;\n v57 = v5;\n v9 = v6 - 1;\n v10 = 0;\n while (v9 != 1) {\n v59 = v4;\n v11 = v9 - 1;\n v12 = v8;\n v13 = 0;\n v60 = v9;\n v14 = v9 - 1;\n while (v14 != 1) {\n v61 = v10;\n v15 = v14 - 1;\n v16 = v7;\n v17 = 0;\n v18 = v13;\n v19 = v14 - 1;\n v20 = v12;\n v21 = v11;\n v22 = v14;\n while (2) {\n if (v19 == 1) {\n LABEL_34:\n v45 = v22;\n v10 = v61;\n v46 = v18;\n v12 = v20;\n v11 = v21;\n v7 = v16;\n v17 += 2;\n goto LABEL_26;\n }\n while (1) {\n v23 = 0;\n v24 = v18;\n v50 = v19 - 1;\n v25 = v19 - 1;\n v26 = v20;\n LABEL_13:\n if (v25 != 1) break;\n v20 = v26;\n v18 = v24;\n v17 += 2 * (v23 + 2) + 2;\n v19 -= 2;\n if (v50 == 1) goto LABEL_25;\n if (v19 == 1) goto LABEL_34;\n }\n v27 = v25 - 1;\n v28 = v24;\n v49 = v25 - 2;\n v29 = v25 - 2;\n v55 = v25 - ((v25 - 1) & 4294967294);\n v30 = 0;\n do {\n if (v25 == v55) {\n v44 = v49;\n v24 = v28;\n v23 += 2 * (v30 + 2) + 2;\n if (v27 == 1) goto LABEL_24;\n LABEL_36:\n v25 = v44;\n goto LABEL_13;\n }\n v31 = v29;\n v51 = v28;\n v32 = 0;\n v33 = v19;\n v53 = v30;\n v34 = v29;\n v35 = v22;\n v36 = v26;\n v52 = v25;\n v54 = v29;\n if (v29 <= 1) {\n LABEL_21:\n v26 = v36;\n v19 = v33;\n v22 = v35;\n v41 = v52;\n v42 = v53;\n v28 = v51;\n v32 += 2;\n v43 = v54;\n } else {\n while (1) {\n v37 = 0;\n do {\n v38 = v34 - 1;\n v34 -= 2;\n v67 = v33;\n v66 = v35;\n v65 = v15;\n v64 = v21;\n v63 = v16;\n v62 = v32;\n v39 = func0(v38);\n v32 = v62;\n v35 = v66;\n v16 = v63;\n v21 = v64;\n v37 += 2 * v39;\n v15 = v65;\n v33 = v67;\n } while (v34 > 1);\n v32 = v62 + 2 * v37 + 2;\n v40 = v31 - 2;\n if (v31 == 2) break;\n v31 -= 2;\n v34 = v40;\n if (v40 <= 1) goto LABEL_21;\n }\n v26 = v36;\n v19 = v67;\n v22 = v66;\n v41 = v52;\n v42 = v53;\n v28 = v51;\n v43 = v54;\n }\n v25 = v41 - 2;\n v30 = v42 + 2 * v32 + 2;\n v29 = v43 - 2;\n } while (v25 != 1);\n v44 = v49;\n v24 = v28;\n v23 += 2 * v30 + 2;\n if (v27 != 1) goto LABEL_36;\n LABEL_24:\n v20 = v26;\n v18 = v24;\n v17 += 2 * v23 + 2;\n v19 -= 2;\n if (v50 != 1) continue;\n break;\n }\n LABEL_25:\n v10 = v61;\n v45 = v22;\n v12 = v20;\n v46 = v18;\n v11 = v21;\n v7 = v16;\n LABEL_26:\n v13 = v46 + 2 * v17 + 2;\n v14 = v45 - 2;\n if (v15 == 1) {\n v4 = v59;\n v47 = v60;\n v8 = v12;\n goto LABEL_28;\n }\n }\n v4 = v59;\n v47 = v60;\n v8 = v12;\n v13 += 2;\n LABEL_28:\n v10 += 2 * v13 + 2;\n v9 = v47 - 2;\n if (v11 == 1) {\n v2 = v58;\n v6 = v8 - 2;\n v5 = v57 + 2 * v10 + 2;\n if (v7 != 1) goto LABEL_5;\n LABEL_30:\n v2 -= 2;\n v3 = v56 + 2 * v5 + 2;\n if (v4 != 1) goto LABEL_3;\n return (unsigned int)(v3 + 1);\n }\n }\n v2 = v58;\n v6 = v8 - 2;\n v5 = v57 + 2 * (v10 + 2) + 2;\n if (v7 == 1) goto LABEL_30;\n if (v8 != 3) continue;\n break;\n }\n }\n v2 -= 2;\n v3 = v56 + 2 * (v5 + 2) + 2;\n if (v4 == 1) return (unsigned int)(v3 + 1);\n if (v2 == 1) return (unsigned int)(v3 + 3);\n }\n }\n }\n return v1;\n}" + }, + { + "index": 260, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n == 0 || n == 1) {\n return 1;\n }\n return 2 * func0(n - 1) + func0(n - 2);\n}", + "test": "int main() {\n\n assert(func0(3) == 7);\n\n assert(func0(4) == 17);\n\n assert(func0(5) == 41);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%edi\njbe 1248 \npush %rbp\nxor %ebp,%ebp\npush %rbx\nmov %edi,%ebx\nsub $0x8,%rsp\nlea -0x1(%rbx),%edi\nsub $0x2,%ebx\ncallq 1210 \nlea 0x0(%rbp,%rax,2),%ebp\ncmp $0x1,%ebx\nja 1223 \nadd $0x8,%rsp\nlea 0x1(%rbp),%eax\npop %rbx\npop %rbp\nretq\nnopl 0x0(%rax)\nmov $0x1,%eax\nretq\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14d, 1\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 58h\ncmp edi, 1\njbe loc_1576\nlea r15d, [rdi-1]\nxor ebp, ebp\nloc_1217:\ncmp r15d, 1\njz loc_156F\nloc_1221:\nlea r12d, [r15-1]\nxor r14d, r14d\nmov [rsp+88h+var_6C], ebp\nmov r13d, r12d\nmov ebp, r14d\nmov ebx, r12d\nloc_1235:\ncmp ebx, 1\njz loc_1544\nloc_123E:\nmov [rsp+88h+var_64], r15d\nlea ecx, [rbx-1]\nxor r14d, r14d\nmov r12d, ebx\nmov [rsp+88h+var_68], ebp\nmov ebx, ecx\nmov ebp, r14d\nloc_1255:\ncmp ebx, 1\njz loc_1517\nmov [rsp+88h+var_60], r13d\nlea edi, [rbx-1]\nmov eax, r12d\nxor r15d, r15d\nmov [rsp+88h+var_5C], ebx\nmov r12d, edi\nloc_1273:\ncmp r12d, 1\njz loc_14DE\nmov [rsp+88h+var_58], ebp\nlea r11d, [r12-1]\nmov r10d, ecx\nxor r13d, r13d\nmov ecx, r15d\nmov ebx, r11d\nmov r9d, eax\nmov r8d, edi\nmov r15d, r12d\nloc_129B:\ncmp ebx, 1\njz loc_149F\nloc_12A4:\nlea ebp, [rbx-1]\nxor r12d, r12d\nmov edi, ecx\nmov [rsp+88h+var_84], ebp\nmov eax, ebp\nmov ebp, r9d\nloc_12B5:\nmov r14d, eax\ncmp eax, 1\njz loc_1478\nlea esi, [rax-1]\nlea edx, [rax-2]\nmov ecx, r14d\nmov r9d, edi\nmov eax, esi\nmov [rsp+88h+var_88], edx\nmov edi, edx\nand eax, 0FFFFFFFEh\nsub ecx, eax\nmov eax, r14d\nmov [rsp+88h+var_70], ecx\nxor ecx, ecx\nloc_12E2:\nmov edx, [rsp+88h+var_70]\ncmp eax, edx\njz loc_14C0\nmov r14d, edi\nmov [rsp+88h+var_80], r9d\nxor edx, edx\nmov r9d, ebx\nmov [rsp+88h+var_78], ecx\nmov ebx, r14d\nmov ecx, r15d\nmov r15d, ebp\nmov [rsp+88h+var_7C], eax\nmov [rsp+88h+var_74], edi\ncmp r14d, 1\njbe short loc_138A\nloc_1316:\nxor ebp, ebp\nloc_1318:\nlea edi, [rbx-1]\nsub ebx, 2\nmov [rsp+88h+var_3C], esi\nmov [rsp+88h+var_40], r9d\nmov [rsp+88h+var_44], ecx\nmov [rsp+88h+var_48], r11d\nmov [rsp+88h+var_4C], r8d\nmov [rsp+88h+var_50], r10d\nmov [rsp+88h+var_54], edx\ncall func0\ncmp ebx, 1\nmov edx, [rsp+88h+var_54]\nmov ecx, [rsp+88h+var_44]\nmov r10d, [rsp+88h+var_50]\nmov r8d, [rsp+88h+var_4C]\nlea ebp, [rbp+rax*2+0]\nmov r11d, [rsp+88h+var_48]\nmov r9d, [rsp+88h+var_40]\nmov esi, [rsp+88h+var_3C]\nja short loc_1318\nlea edx, [rdx+rbp*2+2]\nlea edi, [r14-2]\ncmp r14d, 2\njz loc_14F8\nmov r14d, edi\nmov ebx, r14d\ncmp r14d, 1\nja short loc_1316\nloc_138A:\nmov ebp, r15d\nmov ebx, r9d\nmov r15d, ecx\nmov eax, [rsp+88h+var_7C]\nmov ecx, [rsp+88h+var_78]\nmov r9d, [rsp+88h+var_80]\nadd edx, 2\nmov edi, [rsp+88h+var_74]\nloc_13A7:\nsub eax, 2\nlea ecx, [rcx+rdx*2+2]\nsub edi, 2\ncmp eax, 1\njnz loc_12E2\nmov edx, [rsp+88h+var_88]\nmov edi, r9d\nlea r12d, [r12+rcx*2+2]\ncmp esi, 1\njnz loc_14D7\nloc_13CE:\nmov r9d, ebp\nmov ebp, [rsp+88h+var_84]\nmov ecx, edi\nlea r13d, [r13+r12*2+2]\nsub ebx, 2\ncmp ebp, 1\njnz loc_129B\nloc_13E8:\nmov ebp, [rsp+88h+var_58]\nmov r12d, r15d\nmov eax, r9d\nmov r15d, ecx\nmov edi, r8d\nmov ecx, r10d\nloc_13FB:\nlea r15d, [r15+r13*2+2]\nsub r12d, 2\ncmp r11d, 1\njnz loc_1273\nmov r13d, [rsp+88h+var_60]\nmov ebx, [rsp+88h+var_5C]\nmov r12d, eax\nloc_141A:\nlea ebp, [rbp+r15*2+2]\nsub ebx, 2\ncmp edi, 1\njnz loc_1255\nmov r14d, ebp\nmov ebp, [rsp+88h+var_68]\nmov ebx, r12d\nmov r15d, [rsp+88h+var_64]\nsub ebx, 2\nlea ebp, [rbp+r14*2+2]\ncmp ecx, 1\njnz loc_1235\nloc_144B:\nmov r14d, ebp\nmov ebp, [rsp+88h+var_6C]\nmov r12d, r13d\nsub r15d, 2\nlea ebp, [rbp+r14*2+2]\ncmp r12d, 1\njnz loc_1217\nloc_1468:\nmov r14d, ebp\nadd r14d, 1\njmp loc_1576\nloc_1478:\nmov r9d, ebp\nmov ebp, [rsp+88h+var_84]\nadd r12d, 2\nmov ecx, edi\nlea r13d, [r13+r12*2+2]\nsub ebx, 2\ncmp ebp, 1\njz loc_13E8\ncmp ebx, 1\njnz loc_12A4\nloc_149F:\nmov r12d, r15d\nmov ebp, [rsp+88h+var_58]\nmov r15d, ecx\nmov eax, r9d\nmov edi, r8d\nmov ecx, r10d\nadd r13d, 2\njmp loc_13FB\nloc_14C0:\nadd ecx, 2\nmov edx, [rsp+88h+var_88]\nmov edi, r9d\nlea r12d, [r12+rcx*2+2]\ncmp esi, 1\njz loc_13CE\nloc_14D7:\nmov eax, edx\njmp loc_12B5\nloc_14DE:\nmov r13d, [rsp+88h+var_60]\nmov ebx, [rsp+88h+var_5C]\nmov r12d, eax\nadd r15d, 2\njmp loc_141A\nloc_14F8:\nmov ebp, r15d\nmov ebx, r9d\nmov r15d, ecx\nmov eax, [rsp+88h+var_7C]\nmov ecx, [rsp+88h+var_78]\nmov r9d, [rsp+88h+var_80]\nmov edi, [rsp+88h+var_74]\njmp loc_13A7\nloc_1517:\nmov r14d, ebp\nmov ebp, [rsp+88h+var_68]\nmov ebx, r12d\nmov r15d, [rsp+88h+var_64]\nadd r14d, 2\nsub ebx, 2\nlea ebp, [rbp+r14*2+2]\ncmp ecx, 1\njz loc_144B\ncmp ebx, 1\njnz loc_123E\nloc_1544:\nmov r14d, ebp\nmov ebp, [rsp+88h+var_6C]\nmov r12d, r13d\nsub r15d, 2\nadd r14d, 2\nlea ebp, [rbp+r14*2+2]\ncmp r12d, 1\njz loc_1468\ncmp r15d, 1\njnz loc_1221\nloc_156F:\nmov r14d, ebp\nadd r14d, 3\nloc_1576:\nadd rsp, 58h\nmov eax, r14d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1)\n{\n unsigned int v1; // r14d\n unsigned int v2; // r15d\n int v3; // ebp\n unsigned int v4; // r13d\n int v5; // ebp\n unsigned int v6; // ebx\n unsigned int v7; // ecx\n unsigned int v8; // r12d\n unsigned int v9; // ebx\n int v10; // ebp\n unsigned int v11; // edi\n unsigned int v12; // eax\n int v13; // r15d\n unsigned int v14; // r12d\n unsigned int v15; // r11d\n unsigned int v16; // r10d\n int v17; // r13d\n int v18; // ecx\n unsigned int v19; // ebx\n unsigned int v20; // r9d\n unsigned int v21; // r8d\n unsigned int v22; // r15d\n int v23; // r12d\n int v24; // edi\n unsigned int v25; // eax\n unsigned int v26; // ebp\n unsigned int v27; // esi\n int v28; // r9d\n unsigned int v29; // edi\n int v30; // ecx\n unsigned int v31; // r14d\n int v32; // edx\n unsigned int v33; // r9d\n unsigned int v34; // ebx\n unsigned int v35; // ecx\n unsigned int v36; // r15d\n int v37; // ebp\n __int64 v38; // rdi\n int v39; // eax\n unsigned int v40; // edi\n unsigned int v41; // eax\n int v42; // ecx\n unsigned int v43; // edi\n unsigned int v44; // edx\n unsigned int v45; // r12d\n int v46; // r15d\n unsigned int v47; // ebx\n unsigned int v49; // [rsp+0h] [rbp-88h]\n unsigned int v50; // [rsp+4h] [rbp-84h]\n int v51; // [rsp+8h] [rbp-80h]\n unsigned int v52; // [rsp+Ch] [rbp-7Ch]\n int v53; // [rsp+10h] [rbp-78h]\n unsigned int v54; // [rsp+14h] [rbp-74h]\n unsigned int v55; // [rsp+18h] [rbp-70h]\n int v56; // [rsp+1Ch] [rbp-6Ch]\n int v57; // [rsp+20h] [rbp-68h]\n unsigned int v58; // [rsp+24h] [rbp-64h]\n unsigned int v59; // [rsp+28h] [rbp-60h]\n unsigned int v60; // [rsp+2Ch] [rbp-5Ch]\n int v61; // [rsp+30h] [rbp-58h]\n int v62; // [rsp+34h] [rbp-54h]\n unsigned int v63; // [rsp+38h] [rbp-50h]\n unsigned int v64; // [rsp+3Ch] [rbp-4Ch]\n unsigned int v65; // [rsp+40h] [rbp-48h]\n unsigned int v66; // [rsp+44h] [rbp-44h]\n unsigned int v67; // [rsp+48h] [rbp-40h]\n\n v1 = 1;\n if ( a1 > 1 )\n {\n v2 = a1 - 1;\n v3 = 0;\nLABEL_3:\n if ( v2 == 1 )\n {\n return (unsigned int)(v3 + 3);\n }\n else\n {\n while ( 1 )\n {\n v56 = v3;\n v4 = v2 - 1;\n v5 = 0;\n v6 = v2 - 1;\nLABEL_5:\n if ( v6 != 1 )\n {\n while ( 2 )\n {\n v58 = v2;\n v7 = v6 - 1;\n v8 = v6;\n v57 = v5;\n v9 = v6 - 1;\n v10 = 0;\n while ( v9 != 1 )\n {\n v59 = v4;\n v11 = v9 - 1;\n v12 = v8;\n v13 = 0;\n v60 = v9;\n v14 = v9 - 1;\n while ( v14 != 1 )\n {\n v61 = v10;\n v15 = v14 - 1;\n v16 = v7;\n v17 = 0;\n v18 = v13;\n v19 = v14 - 1;\n v20 = v12;\n v21 = v11;\n v22 = v14;\n while ( 2 )\n {\n if ( v19 == 1 )\n {\nLABEL_34:\n v45 = v22;\n v10 = v61;\n v46 = v18;\n v12 = v20;\n v11 = v21;\n v7 = v16;\n v17 += 2;\n goto LABEL_26;\n }\n while ( 1 )\n {\n v23 = 0;\n v24 = v18;\n v50 = v19 - 1;\n v25 = v19 - 1;\n v26 = v20;\nLABEL_13:\n if ( v25 != 1 )\n break;\n v20 = v26;\n v18 = v24;\n v17 += 2 * (v23 + 2) + 2;\n v19 -= 2;\n if ( v50 == 1 )\n goto LABEL_25;\n if ( v19 == 1 )\n goto LABEL_34;\n }\n v27 = v25 - 1;\n v28 = v24;\n v49 = v25 - 2;\n v29 = v25 - 2;\n v55 = v25 - ((v25 - 1) & 0xFFFFFFFE);\n v30 = 0;\n do\n {\n if ( v25 == v55 )\n {\n v44 = v49;\n v24 = v28;\n v23 += 2 * (v30 + 2) + 2;\n if ( v27 == 1 )\n goto LABEL_24;\nLABEL_36:\n v25 = v44;\n goto LABEL_13;\n }\n v31 = v29;\n v51 = v28;\n v32 = 0;\n v33 = v19;\n v53 = v30;\n v34 = v29;\n v35 = v22;\n v36 = v26;\n v52 = v25;\n v54 = v29;\n if ( v29 <= 1 )\n {\nLABEL_21:\n v26 = v36;\n v19 = v33;\n v22 = v35;\n v41 = v52;\n v42 = v53;\n v28 = v51;\n v32 += 2;\n v43 = v54;\n }\n else\n {\n while ( 1 )\n {\n v37 = 0;\n do\n {\n v38 = v34 - 1;\n v34 -= 2;\n v67 = v33;\n v66 = v35;\n v65 = v15;\n v64 = v21;\n v63 = v16;\n v62 = v32;\n v39 = func0(v38);\n v32 = v62;\n v35 = v66;\n v16 = v63;\n v21 = v64;\n v37 += 2 * v39;\n v15 = v65;\n v33 = v67;\n }\n while ( v34 > 1 );\n v32 = v62 + 2 * v37 + 2;\n v40 = v31 - 2;\n if ( v31 == 2 )\n break;\n v31 -= 2;\n v34 = v40;\n if ( v40 <= 1 )\n goto LABEL_21;\n }\n v26 = v36;\n v19 = v67;\n v22 = v66;\n v41 = v52;\n v42 = v53;\n v28 = v51;\n v43 = v54;\n }\n v25 = v41 - 2;\n v30 = v42 + 2 * v32 + 2;\n v29 = v43 - 2;\n }\n while ( v25 != 1 );\n v44 = v49;\n v24 = v28;\n v23 += 2 * v30 + 2;\n if ( v27 != 1 )\n goto LABEL_36;\nLABEL_24:\n v20 = v26;\n v18 = v24;\n v17 += 2 * v23 + 2;\n v19 -= 2;\n if ( v50 != 1 )\n continue;\n break;\n }\nLABEL_25:\n v10 = v61;\n v45 = v22;\n v12 = v20;\n v46 = v18;\n v11 = v21;\n v7 = v16;\nLABEL_26:\n v13 = v46 + 2 * v17 + 2;\n v14 = v45 - 2;\n if ( v15 == 1 )\n {\n v4 = v59;\n v47 = v60;\n v8 = v12;\n goto LABEL_28;\n }\n }\n v4 = v59;\n v47 = v60;\n v8 = v12;\n v13 += 2;\nLABEL_28:\n v10 += 2 * v13 + 2;\n v9 = v47 - 2;\n if ( v11 == 1 )\n {\n v2 = v58;\n v6 = v8 - 2;\n v5 = v57 + 2 * v10 + 2;\n if ( v7 != 1 )\n goto LABEL_5;\nLABEL_30:\n v2 -= 2;\n v3 = v56 + 2 * v5 + 2;\n if ( v4 != 1 )\n goto LABEL_3;\n return (unsigned int)(v3 + 1);\n }\n }\n v2 = v58;\n v6 = v8 - 2;\n v5 = v57 + 2 * (v10 + 2) + 2;\n if ( v7 == 1 )\n goto LABEL_30;\n if ( v8 != 3 )\n continue;\n break;\n }\n }\n v2 -= 2;\n v3 = v56 + 2 * (v5 + 2) + 2;\n if ( v4 == 1 )\n return (unsigned int)(v3 + 1);\n if ( v2 == 1 )\n return (unsigned int)(v3 + 3);\n }\n }\n }\n return v1;\n}", + "ida_strip_asm": "sub_11F0:\nendbr64\npush r15\npush r14\nmov r14d, 1\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 58h\ncmp edi, 1\njbe loc_1576\nlea r15d, [rdi-1]\nxor ebp, ebp\nloc_1217:\ncmp r15d, 1\njz loc_156F\nloc_1221:\nlea r12d, [r15-1]\nxor r14d, r14d\nmov [rsp+88h+var_6C], ebp\nmov r13d, r12d\nmov ebp, r14d\nmov ebx, r12d\nloc_1235:\ncmp ebx, 1\njz loc_1544\nloc_123E:\nmov [rsp+88h+var_64], r15d\nlea ecx, [rbx-1]\nxor r14d, r14d\nmov r12d, ebx\nmov [rsp+88h+var_68], ebp\nmov ebx, ecx\nmov ebp, r14d\nloc_1255:\ncmp ebx, 1\njz loc_1517\nmov [rsp+88h+var_60], r13d\nlea edi, [rbx-1]\nmov eax, r12d\nxor r15d, r15d\nmov [rsp+88h+var_5C], ebx\nmov r12d, edi\nloc_1273:\ncmp r12d, 1\njz loc_14DE\nmov [rsp+88h+var_58], ebp\nlea r11d, [r12-1]\nmov r10d, ecx\nxor r13d, r13d\nmov ecx, r15d\nmov ebx, r11d\nmov r9d, eax\nmov r8d, edi\nmov r15d, r12d\nloc_129B:\ncmp ebx, 1\njz loc_149F\nloc_12A4:\nlea ebp, [rbx-1]\nxor r12d, r12d\nmov edi, ecx\nmov [rsp+88h+var_84], ebp\nmov eax, ebp\nmov ebp, r9d\nloc_12B5:\nmov r14d, eax\ncmp eax, 1\njz loc_1478\nlea esi, [rax-1]\nlea edx, [rax-2]\nmov ecx, r14d\nmov r9d, edi\nmov eax, esi\nmov [rsp+88h+var_88], edx\nmov edi, edx\nand eax, 0FFFFFFFEh\nsub ecx, eax\nmov eax, r14d\nmov [rsp+88h+var_70], ecx\nxor ecx, ecx\nloc_12E2:\nmov edx, [rsp+88h+var_70]\ncmp eax, edx\njz loc_14C0\nmov r14d, edi\nmov [rsp+88h+var_80], r9d\nxor edx, edx\nmov r9d, ebx\nmov [rsp+88h+var_78], ecx\nmov ebx, r14d\nmov ecx, r15d\nmov r15d, ebp\nmov [rsp+88h+var_7C], eax\nmov [rsp+88h+var_74], edi\ncmp r14d, 1\njbe short loc_138A\nloc_1316:\nxor ebp, ebp\nloc_1318:\nlea edi, [rbx-1]\nsub ebx, 2\nmov [rsp+88h+var_3C], esi\nmov [rsp+88h+var_40], r9d\nmov [rsp+88h+var_44], ecx\nmov [rsp+88h+var_48], r11d\nmov [rsp+88h+var_4C], r8d\nmov [rsp+88h+var_50], r10d\nmov [rsp+88h+var_54], edx\ncall sub_11F0\ncmp ebx, 1\nmov edx, [rsp+88h+var_54]\nmov ecx, [rsp+88h+var_44]\nmov r10d, [rsp+88h+var_50]\nmov r8d, [rsp+88h+var_4C]\nlea ebp, [rbp+rax*2+0]\nmov r11d, [rsp+88h+var_48]\nmov r9d, [rsp+88h+var_40]\nmov esi, [rsp+88h+var_3C]\nja short loc_1318\nlea edx, [rdx+rbp*2+2]\nlea edi, [r14-2]\ncmp r14d, 2\njz loc_14F8\nmov r14d, edi\nmov ebx, r14d\ncmp r14d, 1\nja short loc_1316\nloc_138A:\nmov ebp, r15d\nmov ebx, r9d\nmov r15d, ecx\nmov eax, [rsp+88h+var_7C]\nmov ecx, [rsp+88h+var_78]\nmov r9d, [rsp+88h+var_80]\nadd edx, 2\nmov edi, [rsp+88h+var_74]\nloc_13A7:\nsub eax, 2\nlea ecx, [rcx+rdx*2+2]\nsub edi, 2\ncmp eax, 1\njnz loc_12E2\nmov edx, [rsp+88h+var_88]\nmov edi, r9d\nlea r12d, [r12+rcx*2+2]\ncmp esi, 1\njnz loc_14D7\nloc_13CE:\nmov r9d, ebp\nmov ebp, [rsp+88h+var_84]\nmov ecx, edi\nlea r13d, [r13+r12*2+2]\nsub ebx, 2\ncmp ebp, 1\njnz loc_129B\nloc_13E8:\nmov ebp, [rsp+88h+var_58]\nmov r12d, r15d\nmov eax, r9d\nmov r15d, ecx\nmov edi, r8d\nmov ecx, r10d\nloc_13FB:\nlea r15d, [r15+r13*2+2]\nsub r12d, 2\ncmp r11d, 1\njnz loc_1273\nmov r13d, [rsp+88h+var_60]\nmov ebx, [rsp+88h+var_5C]\nmov r12d, eax\nloc_141A:\nlea ebp, [rbp+r15*2+2]\nsub ebx, 2\ncmp edi, 1\njnz loc_1255\nmov r14d, ebp\nmov ebp, [rsp+88h+var_68]\nmov ebx, r12d\nmov r15d, [rsp+88h+var_64]\nsub ebx, 2\nlea ebp, [rbp+r14*2+2]\ncmp ecx, 1\njnz loc_1235\nloc_144B:\nmov r14d, ebp\nmov ebp, [rsp+88h+var_6C]\nmov r12d, r13d\nsub r15d, 2\nlea ebp, [rbp+r14*2+2]\ncmp r12d, 1\njnz loc_1217\nloc_1468:\nmov r14d, ebp\nadd r14d, 1\njmp loc_1576\nloc_1478:\nmov r9d, ebp\nmov ebp, [rsp+88h+var_84]\nadd r12d, 2\nmov ecx, edi\nlea r13d, [r13+r12*2+2]\nsub ebx, 2\ncmp ebp, 1\njz loc_13E8\ncmp ebx, 1\njnz loc_12A4\nloc_149F:\nmov r12d, r15d\nmov ebp, [rsp+88h+var_58]\nmov r15d, ecx\nmov eax, r9d\nmov edi, r8d\nmov ecx, r10d\nadd r13d, 2\njmp loc_13FB\nloc_14C0:\nadd ecx, 2\nmov edx, [rsp+88h+var_88]\nmov edi, r9d\nlea r12d, [r12+rcx*2+2]\ncmp esi, 1\njz loc_13CE\nloc_14D7:\nmov eax, edx\njmp loc_12B5\nloc_14DE:\nmov r13d, [rsp+88h+var_60]\nmov ebx, [rsp+88h+var_5C]\nmov r12d, eax\nadd r15d, 2\njmp loc_141A\nloc_14F8:\nmov ebp, r15d\nmov ebx, r9d\nmov r15d, ecx\nmov eax, [rsp+88h+var_7C]\nmov ecx, [rsp+88h+var_78]\nmov r9d, [rsp+88h+var_80]\nmov edi, [rsp+88h+var_74]\njmp loc_13A7\nloc_1517:\nmov r14d, ebp\nmov ebp, [rsp+88h+var_68]\nmov ebx, r12d\nmov r15d, [rsp+88h+var_64]\nadd r14d, 2\nsub ebx, 2\nlea ebp, [rbp+r14*2+2]\ncmp ecx, 1\njz loc_144B\ncmp ebx, 1\njnz loc_123E\nloc_1544:\nmov r14d, ebp\nmov ebp, [rsp+88h+var_6C]\nmov r12d, r13d\nsub r15d, 2\nadd r14d, 2\nlea ebp, [rbp+r14*2+2]\ncmp r12d, 1\njz loc_1468\ncmp r15d, 1\njnz loc_1221\nloc_156F:\nmov r14d, ebp\nadd r14d, 3\nloc_1576:\nadd rsp, 58h\nmov eax, r14d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11F0(unsigned int a1)\n{\n unsigned int v1; // r14d\n unsigned int v2; // r15d\n int v3; // ebp\n unsigned int v4; // r13d\n int v5; // ebp\n unsigned int v6; // ebx\n unsigned int v7; // ecx\n unsigned int v8; // r12d\n unsigned int v9; // ebx\n int v10; // ebp\n unsigned int v11; // edi\n unsigned int v12; // eax\n int v13; // r15d\n unsigned int v14; // r12d\n unsigned int v15; // r11d\n unsigned int v16; // r10d\n int v17; // r13d\n int v18; // ecx\n unsigned int v19; // ebx\n unsigned int v20; // r9d\n unsigned int v21; // r8d\n unsigned int v22; // r15d\n int v23; // r12d\n int v24; // edi\n unsigned int v25; // eax\n unsigned int v26; // ebp\n unsigned int v27; // esi\n int v28; // r9d\n unsigned int v29; // edi\n int v30; // ecx\n unsigned int v31; // r14d\n int v32; // edx\n unsigned int v33; // r9d\n unsigned int v34; // ebx\n unsigned int v35; // ecx\n unsigned int v36; // r15d\n int v37; // ebp\n __int64 v38; // rdi\n int v39; // eax\n unsigned int v40; // edi\n unsigned int v41; // eax\n int v42; // ecx\n unsigned int v43; // edi\n unsigned int v44; // edx\n unsigned int v45; // r12d\n int v46; // r15d\n unsigned int v47; // ebx\n unsigned int v49; // [rsp+0h] [rbp-88h]\n unsigned int v50; // [rsp+4h] [rbp-84h]\n int v51; // [rsp+8h] [rbp-80h]\n unsigned int v52; // [rsp+Ch] [rbp-7Ch]\n int v53; // [rsp+10h] [rbp-78h]\n unsigned int v54; // [rsp+14h] [rbp-74h]\n unsigned int v55; // [rsp+18h] [rbp-70h]\n int v56; // [rsp+1Ch] [rbp-6Ch]\n int v57; // [rsp+20h] [rbp-68h]\n unsigned int v58; // [rsp+24h] [rbp-64h]\n unsigned int v59; // [rsp+28h] [rbp-60h]\n unsigned int v60; // [rsp+2Ch] [rbp-5Ch]\n int v61; // [rsp+30h] [rbp-58h]\n int v62; // [rsp+34h] [rbp-54h]\n unsigned int v63; // [rsp+38h] [rbp-50h]\n unsigned int v64; // [rsp+3Ch] [rbp-4Ch]\n unsigned int v65; // [rsp+40h] [rbp-48h]\n unsigned int v66; // [rsp+44h] [rbp-44h]\n unsigned int v67; // [rsp+48h] [rbp-40h]\n\n v1 = 1;\n if ( a1 > 1 )\n {\n v2 = a1 - 1;\n v3 = 0;\nLABEL_3:\n if ( v2 == 1 )\n {\n return (unsigned int)(v3 + 3);\n }\n else\n {\n while ( 1 )\n {\n v56 = v3;\n v4 = v2 - 1;\n v5 = 0;\n v6 = v2 - 1;\nLABEL_5:\n if ( v6 != 1 )\n {\n while ( 2 )\n {\n v58 = v2;\n v7 = v6 - 1;\n v8 = v6;\n v57 = v5;\n v9 = v6 - 1;\n v10 = 0;\n while ( v9 != 1 )\n {\n v59 = v4;\n v11 = v9 - 1;\n v12 = v8;\n v13 = 0;\n v60 = v9;\n v14 = v9 - 1;\n while ( v14 != 1 )\n {\n v61 = v10;\n v15 = v14 - 1;\n v16 = v7;\n v17 = 0;\n v18 = v13;\n v19 = v14 - 1;\n v20 = v12;\n v21 = v11;\n v22 = v14;\n while ( 2 )\n {\n if ( v19 == 1 )\n {\nLABEL_34:\n v45 = v22;\n v10 = v61;\n v46 = v18;\n v12 = v20;\n v11 = v21;\n v7 = v16;\n v17 += 2;\n goto LABEL_26;\n }\n while ( 1 )\n {\n v23 = 0;\n v24 = v18;\n v50 = v19 - 1;\n v25 = v19 - 1;\n v26 = v20;\nLABEL_13:\n if ( v25 != 1 )\n break;\n v20 = v26;\n v18 = v24;\n v17 += 2 * (v23 + 2) + 2;\n v19 -= 2;\n if ( v50 == 1 )\n goto LABEL_25;\n if ( v19 == 1 )\n goto LABEL_34;\n }\n v27 = v25 - 1;\n v28 = v24;\n v49 = v25 - 2;\n v29 = v25 - 2;\n v55 = v25 - ((v25 - 1) & 0xFFFFFFFE);\n v30 = 0;\n do\n {\n if ( v25 == v55 )\n {\n v44 = v49;\n v24 = v28;\n v23 += 2 * (v30 + 2) + 2;\n if ( v27 == 1 )\n goto LABEL_24;\nLABEL_36:\n v25 = v44;\n goto LABEL_13;\n }\n v31 = v29;\n v51 = v28;\n v32 = 0;\n v33 = v19;\n v53 = v30;\n v34 = v29;\n v35 = v22;\n v36 = v26;\n v52 = v25;\n v54 = v29;\n if ( v29 <= 1 )\n {\nLABEL_21:\n v26 = v36;\n v19 = v33;\n v22 = v35;\n v41 = v52;\n v42 = v53;\n v28 = v51;\n v32 += 2;\n v43 = v54;\n }\n else\n {\n while ( 1 )\n {\n v37 = 0;\n do\n {\n v38 = v34 - 1;\n v34 -= 2;\n v67 = v33;\n v66 = v35;\n v65 = v15;\n v64 = v21;\n v63 = v16;\n v62 = v32;\n v39 = sub_11F0(v38);\n v32 = v62;\n v35 = v66;\n v16 = v63;\n v21 = v64;\n v37 += 2 * v39;\n v15 = v65;\n v33 = v67;\n }\n while ( v34 > 1 );\n v32 = v62 + 2 * v37 + 2;\n v40 = v31 - 2;\n if ( v31 == 2 )\n break;\n v31 -= 2;\n v34 = v40;\n if ( v40 <= 1 )\n goto LABEL_21;\n }\n v26 = v36;\n v19 = v67;\n v22 = v66;\n v41 = v52;\n v42 = v53;\n v28 = v51;\n v43 = v54;\n }\n v25 = v41 - 2;\n v30 = v42 + 2 * v32 + 2;\n v29 = v43 - 2;\n }\n while ( v25 != 1 );\n v44 = v49;\n v24 = v28;\n v23 += 2 * v30 + 2;\n if ( v27 != 1 )\n goto LABEL_36;\nLABEL_24:\n v20 = v26;\n v18 = v24;\n v17 += 2 * v23 + 2;\n v19 -= 2;\n if ( v50 != 1 )\n continue;\n break;\n }\nLABEL_25:\n v10 = v61;\n v45 = v22;\n v12 = v20;\n v46 = v18;\n v11 = v21;\n v7 = v16;\nLABEL_26:\n v13 = v46 + 2 * v17 + 2;\n v14 = v45 - 2;\n if ( v15 == 1 )\n {\n v4 = v59;\n v47 = v60;\n v8 = v12;\n goto LABEL_28;\n }\n }\n v4 = v59;\n v47 = v60;\n v8 = v12;\n v13 += 2;\nLABEL_28:\n v10 += 2 * v13 + 2;\n v9 = v47 - 2;\n if ( v11 == 1 )\n {\n v2 = v58;\n v6 = v8 - 2;\n v5 = v57 + 2 * v10 + 2;\n if ( v7 != 1 )\n goto LABEL_5;\nLABEL_30:\n v2 -= 2;\n v3 = v56 + 2 * v5 + 2;\n if ( v4 != 1 )\n goto LABEL_3;\n return (unsigned int)(v3 + 1);\n }\n }\n v2 = v58;\n v6 = v8 - 2;\n v5 = v57 + 2 * (v10 + 2) + 2;\n if ( v7 == 1 )\n goto LABEL_30;\n if ( v8 != 3 )\n continue;\n break;\n }\n }\n v2 -= 2;\n v3 = v56 + 2 * (v5 + 2) + 2;\n if ( v4 == 1 )\n return (unsigned int)(v3 + 1);\n if ( v2 == 1 )\n return (unsigned int)(v3 + 3);\n }\n }\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11F0(unsigned int a1) {\n unsigned int v1;\n unsigned int v2;\n int v3;\n unsigned int v4;\n int v5;\n unsigned int v6;\n unsigned int v7;\n unsigned int v8;\n unsigned int v9;\n int v10;\n unsigned int v11;\n unsigned int v12;\n int v13;\n unsigned int v14;\n unsigned int v15;\n unsigned int v16;\n int v17;\n int v18;\n unsigned int v19;\n unsigned int v20;\n unsigned int v21;\n unsigned int v22;\n int v23;\n int v24;\n unsigned int v25;\n unsigned int v26;\n unsigned int v27;\n int v28;\n unsigned int v29;\n int v30;\n unsigned int v31;\n int v32;\n unsigned int v33;\n unsigned int v34;\n unsigned int v35;\n unsigned int v36;\n int v37;\n long long v38;\n int v39;\n unsigned int v40;\n unsigned int v41;\n int v42;\n unsigned int v43;\n unsigned int v44;\n unsigned int v45;\n int v46;\n unsigned int v47;\n unsigned int v49;\n unsigned int v50;\n int v51;\n unsigned int v52;\n int v53;\n unsigned int v54;\n unsigned int v55;\n int v56;\n int v57;\n unsigned int v58;\n unsigned int v59;\n unsigned int v60;\n int v61;\n int v62;\n unsigned int v63;\n unsigned int v64;\n unsigned int v65;\n unsigned int v66;\n unsigned int v67;\n v1 = 1;\n if (a1 > 1) {\n v2 = a1 - 1;\n v3 = 0;\n LABEL_3:\n if (v2 == 1) {\n return (unsigned int)(v3 + 3);\n } else {\n while (1) {\n v56 = v3;\n v4 = v2 - 1;\n v5 = 0;\n v6 = v2 - 1;\n LABEL_5:\n if (v6 != 1) {\n while (2) {\n v58 = v2;\n v7 = v6 - 1;\n v8 = v6;\n v57 = v5;\n v9 = v6 - 1;\n v10 = 0;\n while (v9 != 1) {\n v59 = v4;\n v11 = v9 - 1;\n v12 = v8;\n v13 = 0;\n v60 = v9;\n v14 = v9 - 1;\n while (v14 != 1) {\n v61 = v10;\n v15 = v14 - 1;\n v16 = v7;\n v17 = 0;\n v18 = v13;\n v19 = v14 - 1;\n v20 = v12;\n v21 = v11;\n v22 = v14;\n while (2) {\n if (v19 == 1) {\n LABEL_34:\n v45 = v22;\n v10 = v61;\n v46 = v18;\n v12 = v20;\n v11 = v21;\n v7 = v16;\n v17 += 2;\n goto LABEL_26;\n }\n while (1) {\n v23 = 0;\n v24 = v18;\n v50 = v19 - 1;\n v25 = v19 - 1;\n v26 = v20;\n LABEL_13:\n if (v25 != 1) break;\n v20 = v26;\n v18 = v24;\n v17 += 2 * (v23 + 2) + 2;\n v19 -= 2;\n if (v50 == 1) goto LABEL_25;\n if (v19 == 1) goto LABEL_34;\n }\n v27 = v25 - 1;\n v28 = v24;\n v49 = v25 - 2;\n v29 = v25 - 2;\n v55 = v25 - ((v25 - 1) & 4294967294);\n v30 = 0;\n do {\n if (v25 == v55) {\n v44 = v49;\n v24 = v28;\n v23 += 2 * (v30 + 2) + 2;\n if (v27 == 1) goto LABEL_24;\n LABEL_36:\n v25 = v44;\n goto LABEL_13;\n }\n v31 = v29;\n v51 = v28;\n v32 = 0;\n v33 = v19;\n v53 = v30;\n v34 = v29;\n v35 = v22;\n v36 = v26;\n v52 = v25;\n v54 = v29;\n if (v29 <= 1) {\n LABEL_21:\n v26 = v36;\n v19 = v33;\n v22 = v35;\n v41 = v52;\n v42 = v53;\n v28 = v51;\n v32 += 2;\n v43 = v54;\n } else {\n while (1) {\n v37 = 0;\n do {\n v38 = v34 - 1;\n v34 -= 2;\n v67 = v33;\n v66 = v35;\n v65 = v15;\n v64 = v21;\n v63 = v16;\n v62 = v32;\n v39 = sub_11F0(v38);\n v32 = v62;\n v35 = v66;\n v16 = v63;\n v21 = v64;\n v37 += 2 * v39;\n v15 = v65;\n v33 = v67;\n } while (v34 > 1);\n v32 = v62 + 2 * v37 + 2;\n v40 = v31 - 2;\n if (v31 == 2) break;\n v31 -= 2;\n v34 = v40;\n if (v40 <= 1) goto LABEL_21;\n }\n v26 = v36;\n v19 = v67;\n v22 = v66;\n v41 = v52;\n v42 = v53;\n v28 = v51;\n v43 = v54;\n }\n v25 = v41 - 2;\n v30 = v42 + 2 * v32 + 2;\n v29 = v43 - 2;\n } while (v25 != 1);\n v44 = v49;\n v24 = v28;\n v23 += 2 * v30 + 2;\n if (v27 != 1) goto LABEL_36;\n LABEL_24:\n v20 = v26;\n v18 = v24;\n v17 += 2 * v23 + 2;\n v19 -= 2;\n if (v50 != 1) continue;\n break;\n }\n LABEL_25:\n v10 = v61;\n v45 = v22;\n v12 = v20;\n v46 = v18;\n v11 = v21;\n v7 = v16;\n LABEL_26:\n v13 = v46 + 2 * v17 + 2;\n v14 = v45 - 2;\n if (v15 == 1) {\n v4 = v59;\n v47 = v60;\n v8 = v12;\n goto LABEL_28;\n }\n }\n v4 = v59;\n v47 = v60;\n v8 = v12;\n v13 += 2;\n LABEL_28:\n v10 += 2 * v13 + 2;\n v9 = v47 - 2;\n if (v11 == 1) {\n v2 = v58;\n v6 = v8 - 2;\n v5 = v57 + 2 * v10 + 2;\n if (v7 != 1) goto LABEL_5;\n LABEL_30:\n v2 -= 2;\n v3 = v56 + 2 * v5 + 2;\n if (v4 != 1) goto LABEL_3;\n return (unsigned int)(v3 + 1);\n }\n }\n v2 = v58;\n v6 = v8 - 2;\n v5 = v57 + 2 * (v10 + 2) + 2;\n if (v7 == 1) goto LABEL_30;\n if (v8 != 3) continue;\n break;\n }\n }\n v2 -= 2;\n v3 = v56 + 2 * (v5 + 2) + 2;\n if (v4 == 1) return (unsigned int)(v3 + 1);\n if (v2 == 1) return (unsigned int)(v3 + 3);\n }\n }\n }\n return v1;\n}", + "ida_pseudo_norm": "long long func0(unsigned int a1) {\n unsigned int v1;\n unsigned int v2;\n int v3;\n unsigned int v4;\n int v5;\n unsigned int v6;\n unsigned int v7;\n unsigned int v8;\n unsigned int v9;\n int v10;\n unsigned int v11;\n unsigned int v12;\n int v13;\n unsigned int v14;\n unsigned int v15;\n unsigned int v16;\n int v17;\n int v18;\n unsigned int v19;\n unsigned int v20;\n unsigned int v21;\n unsigned int v22;\n int v23;\n int v24;\n unsigned int v25;\n unsigned int v26;\n unsigned int v27;\n int v28;\n unsigned int v29;\n int v30;\n unsigned int v31;\n int v32;\n unsigned int v33;\n unsigned int v34;\n unsigned int v35;\n unsigned int v36;\n int v37;\n long long v38;\n int v39;\n unsigned int v40;\n unsigned int v41;\n int v42;\n unsigned int v43;\n unsigned int v44;\n unsigned int v45;\n int v46;\n unsigned int v47;\n unsigned int v49;\n unsigned int v50;\n int v51;\n unsigned int v52;\n int v53;\n unsigned int v54;\n unsigned int v55;\n int v56;\n int v57;\n unsigned int v58;\n unsigned int v59;\n unsigned int v60;\n int v61;\n int v62;\n unsigned int v63;\n unsigned int v64;\n unsigned int v65;\n unsigned int v66;\n unsigned int v67;\n v1 = 1;\n if (a1 > 1) {\n v2 = a1 - 1;\n v3 = 0;\n LABEL_3:\n if (v2 == 1) {\n return (unsigned int)(v3 + 3);\n } else {\n while (1) {\n v56 = v3;\n v4 = v2 - 1;\n v5 = 0;\n v6 = v2 - 1;\n LABEL_5:\n if (v6 != 1) {\n while (2) {\n v58 = v2;\n v7 = v6 - 1;\n v8 = v6;\n v57 = v5;\n v9 = v6 - 1;\n v10 = 0;\n while (v9 != 1) {\n v59 = v4;\n v11 = v9 - 1;\n v12 = v8;\n v13 = 0;\n v60 = v9;\n v14 = v9 - 1;\n while (v14 != 1) {\n v61 = v10;\n v15 = v14 - 1;\n v16 = v7;\n v17 = 0;\n v18 = v13;\n v19 = v14 - 1;\n v20 = v12;\n v21 = v11;\n v22 = v14;\n while (2) {\n if (v19 == 1) {\n LABEL_34:\n v45 = v22;\n v10 = v61;\n v46 = v18;\n v12 = v20;\n v11 = v21;\n v7 = v16;\n v17 += 2;\n goto LABEL_26;\n }\n while (1) {\n v23 = 0;\n v24 = v18;\n v50 = v19 - 1;\n v25 = v19 - 1;\n v26 = v20;\n LABEL_13:\n if (v25 != 1) break;\n v20 = v26;\n v18 = v24;\n v17 += 2 * (v23 + 2) + 2;\n v19 -= 2;\n if (v50 == 1) goto LABEL_25;\n if (v19 == 1) goto LABEL_34;\n }\n v27 = v25 - 1;\n v28 = v24;\n v49 = v25 - 2;\n v29 = v25 - 2;\n v55 = v25 - ((v25 - 1) & 4294967294);\n v30 = 0;\n do {\n if (v25 == v55) {\n v44 = v49;\n v24 = v28;\n v23 += 2 * (v30 + 2) + 2;\n if (v27 == 1) goto LABEL_24;\n LABEL_36:\n v25 = v44;\n goto LABEL_13;\n }\n v31 = v29;\n v51 = v28;\n v32 = 0;\n v33 = v19;\n v53 = v30;\n v34 = v29;\n v35 = v22;\n v36 = v26;\n v52 = v25;\n v54 = v29;\n if (v29 <= 1) {\n LABEL_21:\n v26 = v36;\n v19 = v33;\n v22 = v35;\n v41 = v52;\n v42 = v53;\n v28 = v51;\n v32 += 2;\n v43 = v54;\n } else {\n while (1) {\n v37 = 0;\n do {\n v38 = v34 - 1;\n v34 -= 2;\n v67 = v33;\n v66 = v35;\n v65 = v15;\n v64 = v21;\n v63 = v16;\n v62 = v32;\n v39 = func0(v38);\n v32 = v62;\n v35 = v66;\n v16 = v63;\n v21 = v64;\n v37 += 2 * v39;\n v15 = v65;\n v33 = v67;\n } while (v34 > 1);\n v32 = v62 + 2 * v37 + 2;\n v40 = v31 - 2;\n if (v31 == 2) break;\n v31 -= 2;\n v34 = v40;\n if (v40 <= 1) goto LABEL_21;\n }\n v26 = v36;\n v19 = v67;\n v22 = v66;\n v41 = v52;\n v42 = v53;\n v28 = v51;\n v43 = v54;\n }\n v25 = v41 - 2;\n v30 = v42 + 2 * v32 + 2;\n v29 = v43 - 2;\n } while (v25 != 1);\n v44 = v49;\n v24 = v28;\n v23 += 2 * v30 + 2;\n if (v27 != 1) goto LABEL_36;\n LABEL_24:\n v20 = v26;\n v18 = v24;\n v17 += 2 * v23 + 2;\n v19 -= 2;\n if (v50 != 1) continue;\n break;\n }\n LABEL_25:\n v10 = v61;\n v45 = v22;\n v12 = v20;\n v46 = v18;\n v11 = v21;\n v7 = v16;\n LABEL_26:\n v13 = v46 + 2 * v17 + 2;\n v14 = v45 - 2;\n if (v15 == 1) {\n v4 = v59;\n v47 = v60;\n v8 = v12;\n goto LABEL_28;\n }\n }\n v4 = v59;\n v47 = v60;\n v8 = v12;\n v13 += 2;\n LABEL_28:\n v10 += 2 * v13 + 2;\n v9 = v47 - 2;\n if (v11 == 1) {\n v2 = v58;\n v6 = v8 - 2;\n v5 = v57 + 2 * v10 + 2;\n if (v7 != 1) goto LABEL_5;\n LABEL_30:\n v2 -= 2;\n v3 = v56 + 2 * v5 + 2;\n if (v4 != 1) goto LABEL_3;\n return (unsigned int)(v3 + 1);\n }\n }\n v2 = v58;\n v6 = v8 - 2;\n v5 = v57 + 2 * (v10 + 2) + 2;\n if (v7 == 1) goto LABEL_30;\n if (v8 != 3) continue;\n break;\n }\n }\n v2 -= 2;\n v3 = v56 + 2 * (v5 + 2) + 2;\n if (v4 == 1) return (unsigned int)(v3 + 1);\n if (v2 == 1) return (unsigned int)(v3 + 3);\n }\n }\n }\n return v1;\n}" + }, + { + "index": 261, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int* func0(int test_tup1[], int test_tup2[], int* result, int size) {\n for (int i = 0; i < size; i++) {\n result[i] = test_tup1[i] / test_tup2[i];\n }\n return result;\n}", + "test": "int main() {\n\n int result1[4];\n\n int result2[4];\n\n int result3[4];\n\n\n\n int tuple1_1[4] = {10, 4, 6, 9};\n\n int tuple2_1[4] = {5, 2, 3, 3};\n\n func0(tuple1_1, tuple2_1, result1, 4);\n\n assert(result1[0] == 2 && result1[1] == 2 && result1[2] == 2 && result1[3] == 3);\n\n\n\n int tuple1_2[4] = {12, 6, 8, 16};\n\n int tuple2_2[4] = {6, 3, 4, 4};\n\n func0(tuple1_2, tuple2_2, result2, 4);\n\n assert(result2[0] == 2 && result2[1] == 2 && result2[2] == 2 && result2[3] == 4);\n\n\n\n int tuple1_3[4] = {20, 14, 36, 18};\n\n int tuple2_3[4] = {5, 7, 6, 9};\n\n func0(tuple1_3, tuple2_3, result3, 4);\n\n assert(result3[0] == 4 && result3[1] == 2 && result3[2] == 6 && result3[3] == 2);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %ecx,-0x2c(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11d4 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov -0x4(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x20(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rdx),%edi\nmov -0x4(%rbp),%ecx\nmovslq %ecx,%rcx\nlea 0x0(,%rcx,4),%rsi\nmov -0x28(%rbp),%rcx\nadd %rsi,%rcx\ncltd\nidiv %edi\nmov %eax,(%rcx)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 1189 \nmov -0x28(%rbp),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_28], rdx\nmov [rbp+var_2C], ecx\nmov [rbp+var_4], 0\njmp short loc_11D4\nloc_1189:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_20]\nadd rdx, rcx\nmov edi, [rdx]\nmov ecx, [rbp+var_4]\nmovsxd rcx, ecx\nlea rsi, ds:0[rcx*4]\nmov rcx, [rbp+var_28]\nadd rcx, rsi\ncdq\nidiv edi\nmov [rcx], eax\nadd [rbp+var_4], 1\nloc_11D4:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_2C]\njl short loc_1189\nmov rax, [rbp+var_28]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n int i; // [rsp+28h] [rbp-4h]\n\n for ( i = 0; i < a4; ++i )\n *(_DWORD *)(4LL * i + a3) = *(_DWORD *)(4LL * i + a1) / *(_DWORD *)(4LL * i + a2);\n return a3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_28], rdx\nmov [rbp+var_2C], ecx\nmov [rbp+var_4], 0\njmp short loc_11D4\nloc_1189:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_20]\nadd rdx, rcx\nmov edi, [rdx]\nmov ecx, [rbp+var_4]\nmovsxd rcx, ecx\nlea rsi, ds:0[rcx*4]\nmov rcx, [rbp+var_28]\nadd rcx, rsi\ncdq\nidiv edi\nmov [rcx], eax\nadd [rbp+var_4], 1\nloc_11D4:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_2C]\njl short loc_1189\nmov rax, [rbp+var_28]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n int i; // [rsp+28h] [rbp-4h]\n\n for ( i = 0; i < a4; ++i )\n *(_DWORD *)(4LL * i + a3) = *(_DWORD *)(4LL * i + a1) / *(_DWORD *)(4LL * i + a2);\n return a3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, long long a3, int a4) {\n int i;\n for (i = 0; i < a4; ++i)\n *(uint32_t *)(4LL * i + a3) =\n *(uint32_t *)(4LL * i + a1) / *(uint32_t *)(4LL * i + a2);\n return a3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, long long a3, int a4) {\n int i;\n for (i = 0; i < a4; ++i)\n *(uint32_t *)(4LL * i + a3) =\n *(uint32_t *)(4LL * i + a1) / *(uint32_t *)(4LL * i + a2);\n return a3;\n}" + }, + { + "index": 261, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int* func0(int test_tup1[], int test_tup2[], int* result, int size) {\n for (int i = 0; i < size; i++) {\n result[i] = test_tup1[i] / test_tup2[i];\n }\n return result;\n}", + "test": "int main() {\n\n int result1[4];\n\n int result2[4];\n\n int result3[4];\n\n\n\n int tuple1_1[4] = {10, 4, 6, 9};\n\n int tuple2_1[4] = {5, 2, 3, 3};\n\n func0(tuple1_1, tuple2_1, result1, 4);\n\n assert(result1[0] == 2 && result1[1] == 2 && result1[2] == 2 && result1[3] == 3);\n\n\n\n int tuple1_2[4] = {12, 6, 8, 16};\n\n int tuple2_2[4] = {6, 3, 4, 4};\n\n func0(tuple1_2, tuple2_2, result2, 4);\n\n assert(result2[0] == 2 && result2[1] == 2 && result2[2] == 2 && result2[3] == 4);\n\n\n\n int tuple1_3[4] = {20, 14, 36, 18};\n\n int tuple2_3[4] = {5, 7, 6, 9};\n\n func0(tuple1_3, tuple2_3, result3, 4);\n\n assert(result3[0] == 4 && result3[1] == 2 && result3[2] == 6 && result3[3] == 2);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdx,%r8\ntest %ecx,%ecx\njle 1194 \nlea -0x1(%rcx),%r9d\nmov $0x0,%ecx\nmov (%rdi,%rcx,4),%eax\ncltd\nidivl (%rsi,%rcx,4)\nmov %eax,(%r8,%rcx,4)\nmov %rcx,%rax\nadd $0x1,%rcx\ncmp %r9,%rax\njne 117d \nmov %r8,%rax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov r9, rdi\nmov r8, rdx\ntest ecx, ecx\njle short loc_119C\nmovsxd rcx, ecx\nlea rdi, ds:0[rcx*4]\nmov ecx, 0\nloc_1187:\nmov eax, [r9+rcx]\ncdq\nidiv dword ptr [rsi+rcx]\nmov [r8+rcx], eax\nadd rcx, 4\ncmp rcx, rdi\njnz short loc_1187\nloc_119C:\nmov rax, r8\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 v5; // rdi\n __int64 v6; // rcx\n\n if ( a4 > 0 )\n {\n v5 = 4LL * a4;\n v6 = 0LL;\n do\n {\n *(_DWORD *)(a3 + v6) = *(_DWORD *)(a1 + v6) / *(_DWORD *)(a2 + v6);\n v6 += 4LL;\n }\n while ( v6 != v5 );\n }\n return a3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov r9, rdi\nmov r8, rdx\ntest ecx, ecx\njle short loc_119C\nmovsxd rcx, ecx\nlea rdi, ds:0[rcx*4]\nmov ecx, 0\nloc_1187:\nmov eax, [r9+rcx]\ncdq\nidiv dword ptr [rsi+rcx]\nmov [r8+rcx], eax\nadd rcx, 4\ncmp rcx, rdi\njnz short loc_1187\nloc_119C:\nmov rax, r8\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 v5; // rdi\n __int64 v6; // rcx\n\n if ( a4 > 0 )\n {\n v5 = 4LL * a4;\n v6 = 0LL;\n do\n {\n *(_DWORD *)(a3 + v6) = *(_DWORD *)(a1 + v6) / *(_DWORD *)(a2 + v6);\n v6 += 4LL;\n }\n while ( v6 != v5 );\n }\n return a3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, long long a3, int a4) {\n long long v5;\n long long v6;\n if (a4 > 0) {\n v5 = 4LL * a4;\n v6 = 0LL;\n do {\n *(uint32_t *)(a3 + v6) = *(uint32_t *)(a1 + v6) / *(uint32_t *)(a2 + v6);\n v6 += 4LL;\n } while (v6 != v5);\n }\n return a3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, long long a3, int a4) {\n long long v5;\n long long v6;\n if (a4 > 0) {\n v5 = 4LL * a4;\n v6 = 0LL;\n do {\n *(uint32_t *)(a3 + v6) = *(uint32_t *)(a1 + v6) / *(uint32_t *)(a2 + v6);\n v6 += 4LL;\n } while (v6 != v5);\n }\n return a3;\n}" + }, + { + "index": 262, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int* first;\n\n int first_size;\n\n int* second;\n\n int second_size;\n\n} SplitInt;\n\n\n\ntypedef struct {\n\n char* first;\n\n int first_size;\n\n char* second;\n\n int second_size;\n\n} SplitChar;\n\n\n\nSplitInt split_two_parts_int(int list1[], int length, int L) {\n\n SplitInt result;\n\n result.first_size = L;\n\n result.second_size = length - L;\n\n result.first = malloc(result.first_size * sizeof(int));\n\n result.second = malloc(result.second_size * sizeof(int));\n\n memcpy(result.first, list1, result.first_size * sizeof(int));\n\n memcpy(result.second, list1 + L, result.second_size * sizeof(int));\n\n return result;\n\n}\n\n\n\n", + "func": "SplitChar func0(char list1[], int length, int L) {\n SplitChar result;\n result.first_size = L;\n result.second_size = length - L;\n result.first = malloc((result.first_size + 1) * sizeof(char));\n result.second = malloc((result.second_size + 1) * sizeof(char));\n memcpy(result.first, list1, result.first_size * sizeof(char));\n result.first[result.first_size] = '\\0';\n memcpy(result.second, list1 + L, result.second_size * sizeof(char));\n result.second[result.second_size] = '\\0';\n return result;\n}", + "test": "int main() {\n\n // Test 1: Integers\n\n int list1_int[] = {1, 1, 2, 3, 4, 4, 5, 1};\n\n SplitInt split1 = split_two_parts_int(list1_int, 8, 3);\n\n int expected1_first[] = {1, 1, 2};\n\n int expected1_second[] = {3, 4, 4, 5, 1};\n\n assert(split1.first_size == 3);\n\n assert(split1.second_size == 5);\n\n assert(memcmp(split1.first, expected1_first, 3 * sizeof(int)) == 0);\n\n assert(memcmp(split1.second, expected1_second, 5 * sizeof(int)) == 0);\n\n free(split1.first);\n\n free(split1.second);\n\n\n\n // Test 2: Characters\n\n char list1_char2[] = {'a', 'b', 'c', 'd'};\n\n SplitChar split2 = func0(list1_char2, 4, 2);\n\n char expected2_first[] = \"ab\";\n\n char expected2_second[] = \"cd\";\n\n assert(split2.first_size == 2);\n\n assert(split2.second_size == 2);\n\n assert(strcmp(split2.first, expected2_first) == 0);\n\n assert(strcmp(split2.second, expected2_second) == 0);\n\n free(split2.first);\n\n free(split2.second);\n\n\n\n // Test 3: Characters\n\n char list1_char3[] = {'p', 'y', 't', 'h', 'o', 'n'};\n\n SplitChar split3 = func0(list1_char3, 6, 4);\n\n char expected3_first[] = \"pyth\";\n\n char expected3_second[] = \"on\";\n\n assert(split3.first_size == 4);\n\n assert(split3.second_size == 2);\n\n assert(strcmp(split3.first, expected3_first) == 0);\n\n assert(strcmp(split3.second, expected3_second) == 0);\n\n free(split3.first);\n\n free(split3.second);\n\n\n\n printf(\"All assertions passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x40,%rsp\nmov %rdi,-0x28(%rbp)\nmov %rsi,-0x30(%rbp)\nmov %edx,-0x34(%rbp)\nmov %ecx,-0x38(%rbp)\nmov -0x38(%rbp),%eax\nmov %eax,-0x18(%rbp)\nmov -0x34(%rbp),%eax\nsub -0x38(%rbp),%eax\nmov %eax,-0x8(%rbp)\nmov -0x18(%rbp),%eax\nadd $0x1,%eax\ncltq\nmov %rax,%rdi\ncallq 1130 \nmov %rax,-0x20(%rbp)\nmov -0x8(%rbp),%eax\nadd $0x1,%eax\ncltq\nmov %rax,%rdi\ncallq 1130 \nmov %rax,-0x10(%rbp)\nmov -0x18(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x20(%rbp),%rax\nmov -0x30(%rbp),%rcx\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 1120 \nmov -0x20(%rbp),%rdx\nmov -0x18(%rbp),%eax\ncltq\nadd %rdx,%rax\nmovb $0x0,(%rax)\nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x38(%rbp),%eax\nmovslq %eax,%rcx\nmov -0x30(%rbp),%rax\nadd %rax,%rcx\nmov -0x10(%rbp),%rax\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 1120 \nmov -0x10(%rbp),%rdx\nmov -0x8(%rbp),%eax\ncltq\nadd %rdx,%rax\nmovb $0x0,(%rax)\nmov -0x28(%rbp),%rcx\nmov -0x20(%rbp),%rax\nmov -0x18(%rbp),%rdx\nmov %rax,(%rcx)\nmov %rdx,0x8(%rcx)\nmov -0x10(%rbp),%rax\nmov -0x8(%rbp),%rdx\nmov %rax,0x10(%rcx)\nmov %rdx,0x18(%rcx)\nmov -0x28(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+src], rsi\nmov [rbp+var_34], edx\nmov [rbp+var_38], ecx\nmov eax, [rbp+var_38]\nmov dword ptr [rbp+var_18], eax\nmov eax, [rbp+var_34]\nsub eax, [rbp+var_38]\nmov dword ptr [rbp+var_8], eax\nmov eax, dword ptr [rbp+var_18]\nadd eax, 1\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+dest], rax\nmov eax, dword ptr [rbp+var_8]\nadd eax, 1\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_10], rax\nmov eax, dword ptr [rbp+var_18]\nmovsxd rdx, eax; n\nmov rax, [rbp+dest]\nmov rcx, [rbp+src]\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _memcpy\nmov rdx, [rbp+dest]\nmov eax, dword ptr [rbp+var_18]\ncdqe\nadd rax, rdx\nmov byte ptr [rax], 0\nmov eax, dword ptr [rbp+var_8]\nmovsxd rdx, eax; n\nmov eax, [rbp+var_38]\nmovsxd rcx, eax\nmov rax, [rbp+src]\nadd rcx, rax\nmov rax, [rbp+var_10]\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _memcpy\nmov rdx, [rbp+var_10]\nmov eax, dword ptr [rbp+var_8]\ncdqe\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rcx, [rbp+var_28]\nmov rax, [rbp+dest]\nmov rdx, [rbp+var_18]\nmov [rcx], rax\nmov [rcx+8], rdx\nmov rax, [rbp+var_10]\nmov rdx, [rbp+var_8]\nmov [rcx+10h], rax\nmov [rcx+18h], rdx\nmov rax, [rbp+var_28]\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(_QWORD *a1, char *a2, int a3, int a4)\n{\n void *dest; // [rsp+20h] [rbp-20h]\n __int64 v7; // [rsp+28h] [rbp-18h]\n void *v8; // [rsp+30h] [rbp-10h]\n __int64 v9; // [rsp+38h] [rbp-8h]\n\n LODWORD(v7) = a4;\n LODWORD(v9) = a3 - a4;\n dest = malloc(a4 + 1);\n v8 = malloc((int)v9 + 1);\n memcpy(dest, a2, (int)v7);\n *((_BYTE *)dest + (int)v7) = 0;\n memcpy(v8, &a2[a4], (int)v9);\n *((_BYTE *)v8 + (int)v9) = 0;\n *a1 = dest;\n a1[1] = v7;\n a1[2] = v8;\n a1[3] = v9;\n return a1;\n}", + "ida_strip_asm": "sub_12F5:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+src], rsi\nmov [rbp+var_34], edx\nmov [rbp+var_38], ecx\nmov eax, [rbp+var_38]\nmov dword ptr [rbp+var_18], eax\nmov eax, [rbp+var_34]\nsub eax, [rbp+var_38]\nmov dword ptr [rbp+var_8], eax\nmov eax, dword ptr [rbp+var_18]\nadd eax, 1\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+dest], rax\nmov eax, dword ptr [rbp+var_8]\nadd eax, 1\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_10], rax\nmov eax, dword ptr [rbp+var_18]\nmovsxd rdx, eax; n\nmov rax, [rbp+dest]\nmov rcx, [rbp+src]\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _memcpy\nmov rdx, [rbp+dest]\nmov eax, dword ptr [rbp+var_18]\ncdqe\nadd rax, rdx\nmov byte ptr [rax], 0\nmov eax, dword ptr [rbp+var_8]\nmovsxd rdx, eax; n\nmov eax, [rbp+var_38]\nmovsxd rcx, eax\nmov rax, [rbp+src]\nadd rcx, rax\nmov rax, [rbp+var_10]\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _memcpy\nmov rdx, [rbp+var_10]\nmov eax, dword ptr [rbp+var_8]\ncdqe\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rcx, [rbp+var_28]\nmov rax, [rbp+dest]\nmov rdx, [rbp+var_18]\nmov [rcx], rax\nmov [rcx+8], rdx\nmov rax, [rbp+var_10]\nmov rdx, [rbp+var_8]\nmov [rcx+10h], rax\nmov [rcx+18h], rdx\nmov rax, [rbp+var_28]\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_12F5(_QWORD *a1, char *a2, int a3, int a4)\n{\n void *dest; // [rsp+20h] [rbp-20h]\n __int64 v7; // [rsp+28h] [rbp-18h]\n void *v8; // [rsp+30h] [rbp-10h]\n __int64 v9; // [rsp+38h] [rbp-8h]\n\n LODWORD(v7) = a4;\n LODWORD(v9) = a3 - a4;\n dest = malloc(a4 + 1);\n v8 = malloc((int)v9 + 1);\n memcpy(dest, a2, (int)v7);\n *((_BYTE *)dest + (int)v7) = 0;\n memcpy(v8, &a2[a4], (int)v9);\n *((_BYTE *)v8 + (int)v9) = 0;\n *a1 = dest;\n a1[1] = v7;\n a1[2] = v8;\n a1[3] = v9;\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_12F5(uint64_t *a1, char *a2, int a3, int a4) {\n void *dest;\n long long v7;\n void *v8;\n long long v9;\n LODWORD(v7) = a4;\n LODWORD(v9) = a3 - a4;\n dest = malloc(a4 + 1);\n v8 = malloc((int)v9 + 1);\n memcpy(dest, a2, (int)v7);\n *((uint8_t *)dest + (int)v7) = 0;\n memcpy(v8, &a2[a4], (int)v9);\n *((uint8_t *)v8 + (int)v9) = 0;\n *a1 = dest;\n a1[1] = v7;\n a1[2] = v8;\n a1[3] = v9;\n return a1;\n}", + "ida_pseudo_norm": "uint64_t *func0(uint64_t *a1, char *a2, int a3, int a4) {\n void *dest;\n long long v7;\n void *v8;\n long long v9;\n LODWORD(v7) = a4;\n LODWORD(v9) = a3 - a4;\n dest = malloc(a4 + 1);\n v8 = malloc((int)v9 + 1);\n memcpy(dest, a2, (int)v7);\n *((uint8_t *)dest + (int)v7) = 0;\n memcpy(v8, &a2[a4], (int)v9);\n *((uint8_t *)v8 + (int)v9) = 0;\n *a1 = dest;\n a1[1] = v7;\n a1[2] = v8;\n a1[3] = v9;\n return a1;\n}" + }, + { + "index": 262, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int* first;\n\n int first_size;\n\n int* second;\n\n int second_size;\n\n} SplitInt;\n\n\n\ntypedef struct {\n\n char* first;\n\n int first_size;\n\n char* second;\n\n int second_size;\n\n} SplitChar;\n\n\n\nSplitInt split_two_parts_int(int list1[], int length, int L) {\n\n SplitInt result;\n\n result.first_size = L;\n\n result.second_size = length - L;\n\n result.first = malloc(result.first_size * sizeof(int));\n\n result.second = malloc(result.second_size * sizeof(int));\n\n memcpy(result.first, list1, result.first_size * sizeof(int));\n\n memcpy(result.second, list1 + L, result.second_size * sizeof(int));\n\n return result;\n\n}\n\n\n\n", + "func": "SplitChar func0(char list1[], int length, int L) {\n SplitChar result;\n result.first_size = L;\n result.second_size = length - L;\n result.first = malloc((result.first_size + 1) * sizeof(char));\n result.second = malloc((result.second_size + 1) * sizeof(char));\n memcpy(result.first, list1, result.first_size * sizeof(char));\n result.first[result.first_size] = '\\0';\n memcpy(result.second, list1 + L, result.second_size * sizeof(char));\n result.second[result.second_size] = '\\0';\n return result;\n}", + "test": "int main() {\n\n // Test 1: Integers\n\n int list1_int[] = {1, 1, 2, 3, 4, 4, 5, 1};\n\n SplitInt split1 = split_two_parts_int(list1_int, 8, 3);\n\n int expected1_first[] = {1, 1, 2};\n\n int expected1_second[] = {3, 4, 4, 5, 1};\n\n assert(split1.first_size == 3);\n\n assert(split1.second_size == 5);\n\n assert(memcmp(split1.first, expected1_first, 3 * sizeof(int)) == 0);\n\n assert(memcmp(split1.second, expected1_second, 5 * sizeof(int)) == 0);\n\n free(split1.first);\n\n free(split1.second);\n\n\n\n // Test 2: Characters\n\n char list1_char2[] = {'a', 'b', 'c', 'd'};\n\n SplitChar split2 = func0(list1_char2, 4, 2);\n\n char expected2_first[] = \"ab\";\n\n char expected2_second[] = \"cd\";\n\n assert(split2.first_size == 2);\n\n assert(split2.second_size == 2);\n\n assert(strcmp(split2.first, expected2_first) == 0);\n\n assert(strcmp(split2.second, expected2_second) == 0);\n\n free(split2.first);\n\n free(split2.second);\n\n\n\n // Test 3: Characters\n\n char list1_char3[] = {'p', 'y', 't', 'h', 'o', 'n'};\n\n SplitChar split3 = func0(list1_char3, 6, 4);\n\n char expected3_first[] = \"pyth\";\n\n char expected3_second[] = \"on\";\n\n assert(split3.first_size == 4);\n\n assert(split3.second_size == 2);\n\n assert(strcmp(split3.first, expected3_first) == 0);\n\n assert(strcmp(split3.second, expected3_second) == 0);\n\n free(split3.first);\n\n free(split3.second);\n\n\n\n printf(\"All assertions passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov %rdi,%rbx\nmov %rsi,0x8(%rsp)\nmov %ecx,%ebp\nsub %ecx,%edx\nmov %edx,%r12d\nlea 0x1(%rcx),%edi\nmovslq %edi,%rdi\ncallq 1130 \nmov %rax,%r14\nlea 0x1(%r12),%edi\nmovslq %edi,%rdi\ncallq 1130 \nmov %rax,%r13\nmovslq %ebp,%r15\nmov %r15,%rdx\nmov 0x8(%rsp),%rsi\nmov %r14,%rdi\ncallq 1120 \nmovb $0x0,(%r14,%r15,1)\nmovslq %r12d,%rax\nmov 0x8(%rsp),%rsi\nadd %r15,%rsi\nmov %rax,%r15\nmov %rax,%rdx\nmov %r13,%rdi\ncallq 1120 \nmovb $0x0,0x0(%r13,%r15,1)\nmov %r14,(%rbx)\nmov %ebp,0x8(%rbx)\nmov %r13,0x10(%rbx)\nmov %r12d,0x18(%rbx)\nmov %rbx,%rax\nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov rbx, rdi\nmov [rsp+58h+var_50], rsi\nmov ebp, ecx\nsub edx, ecx\nmov r12d, edx\nlea eax, [rcx+1]\ncdqe\nmov [rsp+58h+var_48], rax\nmov rdi, rax; size\ncall _malloc\nmov r14, rax\nlea eax, [r12+1]\ncdqe\nmov [rsp+58h+var_40], rax\nmov rdi, rax; size\ncall _malloc\nmov r13, rax\nmovsxd r15, ebp\nmov rcx, [rsp+58h+var_48]\nmov rdx, r15\nmov rsi, [rsp+58h+var_50]\nmov rdi, r14\ncall ___memcpy_chk\nmov byte ptr [r14+r15], 0\nmovsxd rax, r12d\nmov rsi, [rsp+58h+var_50]\nadd rsi, r15\nmov rcx, [rsp+58h+var_40]\nmov r15, rax\nmov rdx, rax\nmov rdi, r13\ncall ___memcpy_chk\nmov byte ptr [r13+r15+0], 0\nmov [rbx], r14\nmov [rbx+8], ebp\nmov [rbx+10h], r13\nmov [rbx+18h], r12d\nmov rax, rbx\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3, int a4)\n{\n int v5; // r12d\n _BYTE *v6; // r14\n _BYTE *v7; // r13\n size_t v9; // [rsp+10h] [rbp-48h]\n\n v5 = a3 - a4;\n v9 = a4 + 1;\n v6 = malloc(v9);\n v7 = malloc(v5 + 1);\n __memcpy_chk(v6, a2, a4, v9);\n v6[a4] = 0;\n __memcpy_chk(v7, a4 + a2, v5, v5 + 1);\n v7[v5] = 0;\n *(_QWORD *)a1 = v6;\n *(_DWORD *)(a1 + 8) = a4;\n *(_QWORD *)(a1 + 16) = v7;\n *(_DWORD *)(a1 + 24) = v5;\n return a1;\n}", + "ida_strip_asm": "sub_12BD:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov rbx, rdi\nmov [rsp+58h+var_50], rsi\nmov ebp, ecx\nsub edx, ecx\nmov r12d, edx\nlea eax, [rcx+1]\ncdqe\nmov [rsp+58h+var_48], rax\nmov rdi, rax; size\ncall _malloc\nmov r14, rax\nlea eax, [r12+1]\ncdqe\nmov [rsp+58h+var_40], rax\nmov rdi, rax; size\ncall _malloc\nmov r13, rax\nmovsxd r15, ebp\nmov rcx, [rsp+58h+var_48]\nmov rdx, r15\nmov rsi, [rsp+58h+var_50]\nmov rdi, r14\ncall ___memcpy_chk\nmov byte ptr [r14+r15], 0\nmovsxd rax, r12d\nmov rsi, [rsp+58h+var_50]\nadd rsi, r15\nmov rcx, [rsp+58h+var_40]\nmov r15, rax\nmov rdx, rax\nmov rdi, r13\ncall ___memcpy_chk\nmov byte ptr [r13+r15+0], 0\nmov [rbx], r14\nmov [rbx+8], ebp\nmov [rbx+10h], r13\nmov [rbx+18h], r12d\nmov rax, rbx\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12BD(__int64 a1, __int64 a2, int a3, int a4)\n{\n int v5; // r12d\n _BYTE *v6; // r14\n _BYTE *v7; // r13\n size_t v9; // [rsp+10h] [rbp-48h]\n\n v5 = a3 - a4;\n v9 = a4 + 1;\n v6 = malloc(v9);\n v7 = malloc(v5 + 1);\n __memcpy_chk(v6, a2, a4, v9);\n v6[a4] = 0;\n __memcpy_chk(v7, a4 + a2, v5, v5 + 1);\n v7[v5] = 0;\n *(_QWORD *)a1 = v6;\n *(_DWORD *)(a1 + 8) = a4;\n *(_QWORD *)(a1 + 16) = v7;\n *(_DWORD *)(a1 + 24) = v5;\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12BD(long long a1, long long a2, int a3, int a4) {\n int v5;\n uint8_t *v6;\n uint8_t *v7;\n unsigned int v9;\n v5 = a3 - a4;\n v9 = a4 + 1;\n v6 = malloc(v9);\n v7 = malloc(v5 + 1);\n __memcpy_chk(v6, a2, a4, v9);\n v6[a4] = 0;\n __memcpy_chk(v7, a4 + a2, v5, v5 + 1);\n v7[v5] = 0;\n *(uint64_t *)a1 = v6;\n *(uint32_t *)(a1 + 8) = a4;\n *(uint64_t *)(a1 + 16) = v7;\n *(uint32_t *)(a1 + 24) = v5;\n return a1;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3, int a4) {\n int v5;\n uint8_t *v6;\n uint8_t *v7;\n unsigned int v9;\n v5 = a3 - a4;\n v9 = a4 + 1;\n v6 = malloc(v9);\n v7 = malloc(v5 + 1);\n __memcpy_chk(v6, a2, a4, v9);\n v6[a4] = 0;\n __memcpy_chk(v7, a4 + a2, v5, v5 + 1);\n v7[v5] = 0;\n *(uint64_t *)a1 = v6;\n *(uint32_t *)(a1 + 8) = a4;\n *(uint64_t *)(a1 + 16) = v7;\n *(uint32_t *)(a1 + 24) = v5;\n return a1;\n}" + }, + { + "index": 262, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int* first;\n\n int first_size;\n\n int* second;\n\n int second_size;\n\n} SplitInt;\n\n\n\ntypedef struct {\n\n char* first;\n\n int first_size;\n\n char* second;\n\n int second_size;\n\n} SplitChar;\n\n\n\nSplitInt split_two_parts_int(int list1[], int length, int L) {\n\n SplitInt result;\n\n result.first_size = L;\n\n result.second_size = length - L;\n\n result.first = malloc(result.first_size * sizeof(int));\n\n result.second = malloc(result.second_size * sizeof(int));\n\n memcpy(result.first, list1, result.first_size * sizeof(int));\n\n memcpy(result.second, list1 + L, result.second_size * sizeof(int));\n\n return result;\n\n}\n\n\n\n", + "func": "SplitChar func0(char list1[], int length, int L) {\n SplitChar result;\n result.first_size = L;\n result.second_size = length - L;\n result.first = malloc((result.first_size + 1) * sizeof(char));\n result.second = malloc((result.second_size + 1) * sizeof(char));\n memcpy(result.first, list1, result.first_size * sizeof(char));\n result.first[result.first_size] = '\\0';\n memcpy(result.second, list1 + L, result.second_size * sizeof(char));\n result.second[result.second_size] = '\\0';\n return result;\n}", + "test": "int main() {\n\n // Test 1: Integers\n\n int list1_int[] = {1, 1, 2, 3, 4, 4, 5, 1};\n\n SplitInt split1 = split_two_parts_int(list1_int, 8, 3);\n\n int expected1_first[] = {1, 1, 2};\n\n int expected1_second[] = {3, 4, 4, 5, 1};\n\n assert(split1.first_size == 3);\n\n assert(split1.second_size == 5);\n\n assert(memcmp(split1.first, expected1_first, 3 * sizeof(int)) == 0);\n\n assert(memcmp(split1.second, expected1_second, 5 * sizeof(int)) == 0);\n\n free(split1.first);\n\n free(split1.second);\n\n\n\n // Test 2: Characters\n\n char list1_char2[] = {'a', 'b', 'c', 'd'};\n\n SplitChar split2 = func0(list1_char2, 4, 2);\n\n char expected2_first[] = \"ab\";\n\n char expected2_second[] = \"cd\";\n\n assert(split2.first_size == 2);\n\n assert(split2.second_size == 2);\n\n assert(strcmp(split2.first, expected2_first) == 0);\n\n assert(strcmp(split2.second, expected2_second) == 0);\n\n free(split2.first);\n\n free(split2.second);\n\n\n\n // Test 3: Characters\n\n char list1_char3[] = {'p', 'y', 't', 'h', 'o', 'n'};\n\n SplitChar split3 = func0(list1_char3, 6, 4);\n\n char expected3_first[] = \"pyth\";\n\n char expected3_second[] = \"on\";\n\n assert(split3.first_size == 4);\n\n assert(split3.second_size == 2);\n\n assert(strcmp(split3.first, expected3_first) == 0);\n\n assert(strcmp(split3.second, expected3_second) == 0);\n\n free(split3.first);\n\n free(split3.second);\n\n\n\n printf(\"All assertions passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nsub %ecx,%edx\npush %r14\npush %r13\nmov %edx,%r13d\npush %r12\nmov %rdi,%r12\nlea 0x1(%rcx),%edi\npush %rbp\nmovslq %edi,%rdi\nmov %rsi,%rbp\npush %rbx\nmov %ecx,%ebx\nsub $0x18,%rsp\ncallq 1110 \nlea 0x1(%r13),%edi\nmov %rax,%r15\nmovslq %edi,%rdi\ncallq 1110 \nmovslq %ebx,%rdx\nmov %rbp,%rsi\nmov %r15,%rdi\nmov %rax,%r14\nmov %rdx,0x8(%rsp)\ncallq 1100 \nmov 0x8(%rsp),%rdx\nmovslq %r13d,%rcx\nmov %r14,%rdi\nmov %rcx,0x8(%rsp)\nmovb $0x0,(%r15,%rdx,1)\nlea 0x0(%rbp,%rdx,1),%rsi\nmov %rcx,%rdx\ncallq 1100 \nmov 0x8(%rsp),%rcx\nmov %r15,(%r12)\nmov %r12,%rax\nmov %ebx,0x8(%r12)\nmov %r14,0x10(%r12)\nmov %r13d,0x18(%r12)\nmovb $0x0,(%r14,%rcx,1)\nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\nsub edx, ecx\npush r14\npush r13\nmov r13d, edx\npush r12\nmov r12, rsi\npush rbp\nmov ebp, ecx\nlea ecx, [rcx+1]\npush rbx\nmovsxd rcx, ecx\nmov rbx, rdi\nmov rdi, rcx; size\nsub rsp, 18h\nmov [rsp+48h+var_48], rcx\ncall _malloc\nlea r8d, [r13+1]\nmovsxd r8, r8d\nmov r15, rax\nmov rdi, r8; size\nmov [rsp+48h+var_40], r8\ncall _malloc\nmov rcx, [rsp+48h+var_48]\nmovsxd rdx, ebp\nmov rsi, r12\nmov rdi, r15\nmov r14, rax\nmov [rsp+48h+var_48], rdx\ncall ___memcpy_chk\nmov rdx, [rsp+48h+var_48]\nmovsxd r9, r13d\nmov rdi, r14\nmov rcx, [rsp+48h+var_40]\nmov [rsp+48h+var_48], r9\nmov byte ptr [r15+rdx], 0\nlea rsi, [r12+rdx]\nmov rdx, r9\ncall ___memcpy_chk\nmov r9, [rsp+48h+var_48]\nmov [rbx], r15\nmov rax, rbx\nmov [rbx+8], ebp\nmov byte ptr [r14+r9], 0\nmov [rbx+10h], r14\nmov [rbx+18h], r13d\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3, int a4)\n{\n int v4; // r13d\n _BYTE *v6; // r15\n _BYTE *v7; // r14\n __int64 result; // rax\n size_t v9; // [rsp+0h] [rbp-48h]\n\n v4 = a3 - a4;\n v9 = a4 + 1;\n v6 = malloc(v9);\n v7 = malloc(v4 + 1);\n __memcpy_chk(v6, a2, a4, v9);\n v6[a4] = 0;\n __memcpy_chk(v7, a2 + a4, v4, v4 + 1);\n *(_QWORD *)a1 = v6;\n result = a1;\n *(_DWORD *)(a1 + 8) = a4;\n v7[v4] = 0;\n *(_QWORD *)(a1 + 16) = v7;\n *(_DWORD *)(a1 + 24) = v4;\n return result;\n}", + "ida_strip_asm": "sub_16A0:\nendbr64\npush r15\nsub edx, ecx\npush r14\npush r13\nmov r13d, edx\npush r12\nmov r12, rsi\npush rbp\nmov ebp, ecx\nlea ecx, [rcx+1]\npush rbx\nmovsxd rcx, ecx\nmov rbx, rdi\nmov rdi, rcx; size\nsub rsp, 18h\nmov [rsp+48h+var_48], rcx\ncall _malloc\nlea r8d, [r13+1]\nmovsxd r8, r8d\nmov r15, rax\nmov rdi, r8; size\nmov [rsp+48h+var_40], r8\ncall _malloc\nmov rcx, [rsp+48h+var_48]\nmovsxd rdx, ebp\nmov rsi, r12\nmov rdi, r15\nmov r14, rax\nmov [rsp+48h+var_48], rdx\ncall ___memcpy_chk\nmov rdx, [rsp+48h+var_48]\nmovsxd r9, r13d\nmov rdi, r14\nmov rcx, [rsp+48h+var_40]\nmov [rsp+48h+var_48], r9\nmov byte ptr [r15+rdx], 0\nlea rsi, [r12+rdx]\nmov rdx, r9\ncall ___memcpy_chk\nmov r9, [rsp+48h+var_48]\nmov [rbx], r15\nmov rax, rbx\nmov [rbx+8], ebp\nmov byte ptr [r14+r9], 0\nmov [rbx+10h], r14\nmov [rbx+18h], r13d\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_16A0(__int64 a1, __int64 a2, int a3, int a4)\n{\n int v4; // r13d\n _BYTE *v6; // r15\n _BYTE *v7; // r14\n __int64 result; // rax\n size_t v9; // [rsp+0h] [rbp-48h]\n\n v4 = a3 - a4;\n v9 = a4 + 1;\n v6 = malloc(v9);\n v7 = malloc(v4 + 1);\n __memcpy_chk(v6, a2, a4, v9);\n v6[a4] = 0;\n __memcpy_chk(v7, a2 + a4, v4, v4 + 1);\n *(_QWORD *)a1 = v6;\n result = a1;\n *(_DWORD *)(a1 + 8) = a4;\n v7[v4] = 0;\n *(_QWORD *)(a1 + 16) = v7;\n *(_DWORD *)(a1 + 24) = v4;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_16A0(long long a1, long long a2, int a3, int a4) {\n int v4;\n uint8_t *v6;\n uint8_t *v7;\n long long result;\n unsigned int v9;\n v4 = a3 - a4;\n v9 = a4 + 1;\n v6 = malloc(v9);\n v7 = malloc(v4 + 1);\n __memcpy_chk(v6, a2, a4, v9);\n v6[a4] = 0;\n __memcpy_chk(v7, a2 + a4, v4, v4 + 1);\n *(uint64_t *)a1 = v6;\n result = a1;\n *(uint32_t *)(a1 + 8) = a4;\n v7[v4] = 0;\n *(uint64_t *)(a1 + 16) = v7;\n *(uint32_t *)(a1 + 24) = v4;\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3, int a4) {\n int v4;\n uint8_t *v6;\n uint8_t *v7;\n long long result;\n unsigned int v9;\n v4 = a3 - a4;\n v9 = a4 + 1;\n v6 = malloc(v9);\n v7 = malloc(v4 + 1);\n __memcpy_chk(v6, a2, a4, v9);\n v6[a4] = 0;\n __memcpy_chk(v7, a2 + a4, v4, v4 + 1);\n *(uint64_t *)a1 = v6;\n result = a1;\n *(uint32_t *)(a1 + 8) = a4;\n v7[v4] = 0;\n *(uint64_t *)(a1 + 16) = v7;\n *(uint32_t *)(a1 + 24) = v4;\n return result;\n}" + }, + { + "index": 262, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int* first;\n\n int first_size;\n\n int* second;\n\n int second_size;\n\n} SplitInt;\n\n\n\ntypedef struct {\n\n char* first;\n\n int first_size;\n\n char* second;\n\n int second_size;\n\n} SplitChar;\n\n\n\nSplitInt split_two_parts_int(int list1[], int length, int L) {\n\n SplitInt result;\n\n result.first_size = L;\n\n result.second_size = length - L;\n\n result.first = malloc(result.first_size * sizeof(int));\n\n result.second = malloc(result.second_size * sizeof(int));\n\n memcpy(result.first, list1, result.first_size * sizeof(int));\n\n memcpy(result.second, list1 + L, result.second_size * sizeof(int));\n\n return result;\n\n}\n\n\n\n", + "func": "SplitChar func0(char list1[], int length, int L) {\n SplitChar result;\n result.first_size = L;\n result.second_size = length - L;\n result.first = malloc((result.first_size + 1) * sizeof(char));\n result.second = malloc((result.second_size + 1) * sizeof(char));\n memcpy(result.first, list1, result.first_size * sizeof(char));\n result.first[result.first_size] = '\\0';\n memcpy(result.second, list1 + L, result.second_size * sizeof(char));\n result.second[result.second_size] = '\\0';\n return result;\n}", + "test": "int main() {\n\n // Test 1: Integers\n\n int list1_int[] = {1, 1, 2, 3, 4, 4, 5, 1};\n\n SplitInt split1 = split_two_parts_int(list1_int, 8, 3);\n\n int expected1_first[] = {1, 1, 2};\n\n int expected1_second[] = {3, 4, 4, 5, 1};\n\n assert(split1.first_size == 3);\n\n assert(split1.second_size == 5);\n\n assert(memcmp(split1.first, expected1_first, 3 * sizeof(int)) == 0);\n\n assert(memcmp(split1.second, expected1_second, 5 * sizeof(int)) == 0);\n\n free(split1.first);\n\n free(split1.second);\n\n\n\n // Test 2: Characters\n\n char list1_char2[] = {'a', 'b', 'c', 'd'};\n\n SplitChar split2 = func0(list1_char2, 4, 2);\n\n char expected2_first[] = \"ab\";\n\n char expected2_second[] = \"cd\";\n\n assert(split2.first_size == 2);\n\n assert(split2.second_size == 2);\n\n assert(strcmp(split2.first, expected2_first) == 0);\n\n assert(strcmp(split2.second, expected2_second) == 0);\n\n free(split2.first);\n\n free(split2.second);\n\n\n\n // Test 3: Characters\n\n char list1_char3[] = {'p', 'y', 't', 'h', 'o', 'n'};\n\n SplitChar split3 = func0(list1_char3, 6, 4);\n\n char expected3_first[] = \"pyth\";\n\n char expected3_second[] = \"on\";\n\n assert(split3.first_size == 4);\n\n assert(split3.second_size == 2);\n\n assert(strcmp(split3.first, expected3_first) == 0);\n\n assert(strcmp(split3.second, expected3_second) == 0);\n\n free(split3.first);\n\n free(split3.second);\n\n\n\n printf(\"All assertions passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nsub %ecx,%edx\npush %r14\npush %r13\nmov %edx,%r13d\npush %r12\nmov %rdi,%r12\nlea 0x1(%rcx),%edi\npush %rbp\nmovslq %edi,%rdi\nmov %rsi,%rbp\npush %rbx\nmov %ecx,%ebx\nsub $0x18,%rsp\ncallq 1110 \nlea 0x1(%r13),%edi\nmov %rax,%r15\nmovslq %edi,%rdi\ncallq 1110 \nmovslq %ebx,%rdx\nmov %rbp,%rsi\nmov %r15,%rdi\nmov %rax,%r14\nmov %rdx,0x8(%rsp)\ncallq 1100 \nmov 0x8(%rsp),%rdx\nmovslq %r13d,%rcx\nmov %r14,%rdi\nmov %rcx,0x8(%rsp)\nmovb $0x0,(%r15,%rdx,1)\nlea 0x0(%rbp,%rdx,1),%rsi\nmov %rcx,%rdx\ncallq 1100 \nmov 0x8(%rsp),%rcx\nmov %r15,(%r12)\nmov %r12,%rax\nmov %ebx,0x8(%r12)\nmov %r14,0x10(%r12)\nmov %r13d,0x18(%r12)\nmovb $0x0,(%r14,%rcx,1)\nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\nsub edx, ecx\npush r14\npush r13\nmov r13d, edx\npush r12\nmov r12, rsi\npush rbp\nmov ebp, ecx\nlea ecx, [rcx+1]\npush rbx\nmovsxd rcx, ecx\nmov rbx, rdi\nmov rdi, rcx; size\nsub rsp, 18h\nmov [rsp+48h+var_48], rcx\ncall _malloc\nlea r8d, [r13+1]\nmovsxd r8, r8d\nmov r15, rax\nmov rdi, r8; size\nmov [rsp+48h+var_40], r8\ncall _malloc\nmov rcx, [rsp+48h+var_48]\nmovsxd rdx, ebp\nmov rsi, r12\nmov rdi, r15\nmov r14, rax\nmov [rsp+48h+var_48], rdx\ncall ___memcpy_chk\nmov rdx, [rsp+48h+var_48]\nmovsxd r9, r13d\nmov rdi, r14\nmov rcx, [rsp+48h+var_40]\nmov [rsp+48h+var_48], r9\nmov byte ptr [r15+rdx], 0\nlea rsi, [r12+rdx]\nmov rdx, r9\ncall ___memcpy_chk\nmov r9, [rsp+48h+var_48]\nmov [rbx], r15\nmov rax, rbx\nmov [rbx+8], ebp\nmov byte ptr [r14+r9], 0\nmov [rbx+10h], r14\nmov [rbx+18h], r13d\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3, int a4)\n{\n int v4; // r13d\n _BYTE *v6; // r15\n _BYTE *v7; // r14\n __int64 result; // rax\n size_t v9; // [rsp+0h] [rbp-48h]\n\n v4 = a3 - a4;\n v9 = a4 + 1;\n v6 = malloc(v9);\n v7 = malloc(v4 + 1);\n __memcpy_chk(v6, a2, a4, v9);\n v6[a4] = 0;\n __memcpy_chk(v7, a2 + a4, v4, v4 + 1);\n *(_QWORD *)a1 = v6;\n result = a1;\n *(_DWORD *)(a1 + 8) = a4;\n v7[v4] = 0;\n *(_QWORD *)(a1 + 16) = v7;\n *(_DWORD *)(a1 + 24) = v4;\n return result;\n}", + "ida_strip_asm": "sub_16A0:\nendbr64\npush r15\nsub edx, ecx\npush r14\npush r13\nmov r13d, edx\npush r12\nmov r12, rsi\npush rbp\nmov ebp, ecx\nlea ecx, [rcx+1]\npush rbx\nmovsxd rcx, ecx\nmov rbx, rdi\nmov rdi, rcx; size\nsub rsp, 18h\nmov [rsp+48h+var_48], rcx\ncall _malloc\nlea r8d, [r13+1]\nmovsxd r8, r8d\nmov r15, rax\nmov rdi, r8; size\nmov [rsp+48h+var_40], r8\ncall _malloc\nmov rcx, [rsp+48h+var_48]\nmovsxd rdx, ebp\nmov rsi, r12\nmov rdi, r15\nmov r14, rax\nmov [rsp+48h+var_48], rdx\ncall ___memcpy_chk\nmov rdx, [rsp+48h+var_48]\nmovsxd r9, r13d\nmov rdi, r14\nmov rcx, [rsp+48h+var_40]\nmov [rsp+48h+var_48], r9\nmov byte ptr [r15+rdx], 0\nlea rsi, [r12+rdx]\nmov rdx, r9\ncall ___memcpy_chk\nmov r9, [rsp+48h+var_48]\nmov [rbx], r15\nmov rax, rbx\nmov [rbx+8], ebp\nmov byte ptr [r14+r9], 0\nmov [rbx+10h], r14\nmov [rbx+18h], r13d\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_16A0(__int64 a1, __int64 a2, int a3, int a4)\n{\n int v4; // r13d\n _BYTE *v6; // r15\n _BYTE *v7; // r14\n __int64 result; // rax\n size_t v9; // [rsp+0h] [rbp-48h]\n\n v4 = a3 - a4;\n v9 = a4 + 1;\n v6 = malloc(v9);\n v7 = malloc(v4 + 1);\n __memcpy_chk(v6, a2, a4, v9);\n v6[a4] = 0;\n __memcpy_chk(v7, a2 + a4, v4, v4 + 1);\n *(_QWORD *)a1 = v6;\n result = a1;\n *(_DWORD *)(a1 + 8) = a4;\n v7[v4] = 0;\n *(_QWORD *)(a1 + 16) = v7;\n *(_DWORD *)(a1 + 24) = v4;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_16A0(long long a1, long long a2, int a3, int a4) {\n int v4;\n uint8_t *v6;\n uint8_t *v7;\n long long result;\n unsigned int v9;\n v4 = a3 - a4;\n v9 = a4 + 1;\n v6 = malloc(v9);\n v7 = malloc(v4 + 1);\n __memcpy_chk(v6, a2, a4, v9);\n v6[a4] = 0;\n __memcpy_chk(v7, a2 + a4, v4, v4 + 1);\n *(uint64_t *)a1 = v6;\n result = a1;\n *(uint32_t *)(a1 + 8) = a4;\n v7[v4] = 0;\n *(uint64_t *)(a1 + 16) = v7;\n *(uint32_t *)(a1 + 24) = v4;\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3, int a4) {\n int v4;\n uint8_t *v6;\n uint8_t *v7;\n long long result;\n unsigned int v9;\n v4 = a3 - a4;\n v9 = a4 + 1;\n v6 = malloc(v9);\n v7 = malloc(v4 + 1);\n __memcpy_chk(v6, a2, a4, v9);\n v6[a4] = 0;\n __memcpy_chk(v7, a2 + a4, v4, v4 + 1);\n *(uint64_t *)a1 = v6;\n result = a1;\n *(uint32_t *)(a1 + 8) = a4;\n v7[v4] = 0;\n *(uint64_t *)(a1 + 16) = v7;\n *(uint32_t *)(a1 + 24) = v4;\n return result;\n}" + }, + { + "index": 263, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char *key;\n\n int value;\n\n} dict_entry;\n\n\n\ndict_entry* merge_dict(const dict_entry *d1, size_t size1, const dict_entry *d2, size_t size2, size_t *size_out) {\n\n dict_entry *merged = malloc((size1 + size2) * sizeof(dict_entry));\n\n for (size_t i = 0; i < size1; i++) {\n\n merged[i].key = d1[i].key;\n\n merged[i].value = d1[i].value;\n\n }\n\n for (size_t i = 0; i < size2; i++) {\n\n merged[size1 + i].key = d2[i].key;\n\n merged[size1 + i].value = d2[i].value;\n\n }\n\n *size_out = size1 + size2;\n\n return merged;\n\n}\n\n\n\n", + "func": "int func0(const dict_entry *d1, size_t size1, const dict_entry *d2,\n size_t size2) {\n if (size1 != size2) return 0;\n for (size_t i = 0; i < size1; i++) {\n if (strcmp(d1[i].key, d2[i].key) != 0 || d1[i].value != d2[i].value) {\n return 0;\n }\n }\n return 1;\n}", + "test": "int main() {\n\n // Test case 1\n\n dict_entry d1_a[] = {{\"a\", 100}, {\"b\", 200}};\n\n dict_entry d2_a[] = {{\"x\", 300}, {\"y\", 200}};\n\n size_t size_a;\n\n dict_entry *merged_a = merge_dict(d1_a, 2, d2_a, 2, &size_a);\n\n dict_entry expected_a[] = {{\"a\", 100}, {\"b\", 200}, {\"x\", 300}, {\"y\", 200}};\n\n assert(func0(merged_a, size_a, expected_a, 4));\n\n free(merged_a);\n\n\n\n // Test case 2\n\n dict_entry d1_b[] = {{\"a\", 900}, {\"b\", 900}, {\"d\", 900}};\n\n dict_entry d2_b[] = {{\"a\", 900}, {\"b\", 900}, {\"d\", 900}};\n\n size_t size_b;\n\n dict_entry *merged_b = merge_dict(d1_b, 3, d2_b, 3, &size_b);\n\n dict_entry expected_b[] = {{\"a\", 900}, {\"b\", 900}, {\"d\", 900}, {\"a\", 900}, {\"b\", 900}, {\"d\", 900}};\n\n assert(func0(merged_b, size_b, expected_b, 6));\n\n free(merged_b);\n\n\n\n // Test case 3\n\n dict_entry d1_c[] = {{\"a\", 10}, {\"b\", 20}};\n\n dict_entry d2_c[] = {{\"x\", 30}, {\"y\", 40}};\n\n size_t size_c;\n\n dict_entry *merged_c = merge_dict(d1_c, 2, d2_c, 2, &size_c);\n\n dict_entry expected_c[] = {{\"a\", 10}, {\"b\", 20}, {\"x\", 30}, {\"y\", 40}};\n\n assert(func0(merged_c, size_c, expected_c, 4));\n\n free(merged_c);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %rcx,-0x30(%rbp)\nmov -0x20(%rbp),%rax\ncmp -0x30(%rbp),%rax\nje 1334 \nmov $0x0,%eax\njmpq 13c0 \nmovq $0x0,-0x8(%rbp)\njmp 13b1 \nmov -0x8(%rbp),%rax\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rdx\nmov -0x8(%rbp),%rax\nshl $0x4,%rax\nmov %rax,%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10c0 \ntest %eax,%eax\njne 13a5 \nmov -0x8(%rbp),%rax\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov 0x8(%rax),%edx\nmov -0x8(%rbp),%rax\nshl $0x4,%rax\nmov %rax,%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov 0x8(%rax),%eax\ncmp %eax,%edx\nje 13ac \nmov $0x0,%eax\njmp 13c0 \naddq $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%rax\ncmp -0x20(%rbp),%rax\njb 133e \nmov $0x1,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_28], rdx\nmov [rbp+var_30], rcx\nmov rax, [rbp+var_20]\ncmp rax, [rbp+var_30]\njz short loc_1334\nmov eax, 0\njmp locret_13C0\nloc_1334:\nmov [rbp+var_8], 0\njmp short loc_13B1\nloc_133E:\nmov rax, [rbp+var_8]\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rdx, [rax]\nmov rax, [rbp+var_8]\nshl rax, 4\nmov rcx, rax\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_13A5\nmov rax, [rbp+var_8]\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax+8]\nmov rax, [rbp+var_8]\nshl rax, 4\nmov rcx, rax\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax+8]\ncmp edx, eax\njz short loc_13AC\nloc_13A5:\nmov eax, 0\njmp short locret_13C0\nloc_13AC:\nadd [rbp+var_8], 1\nloc_13B1:\nmov rax, [rbp+var_8]\ncmp rax, [rbp+var_20]\njb short loc_133E\nmov eax, 1\nlocret_13C0:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, unsigned __int64 a2, __int64 a3, __int64 a4)\n{\n unsigned __int64 i; // [rsp+28h] [rbp-8h]\n\n if ( a2 != a4 )\n return 0LL;\n for ( i = 0LL; i < a2; ++i )\n {\n if ( strcmp(*(const char **)(16 * i + a1), *(const char **)(16 * i + a3))\n || *(_DWORD *)(16 * i + a1 + 8) != *(_DWORD *)(16 * i + a3 + 8) )\n {\n return 0LL;\n }\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1304:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_28], rdx\nmov [rbp+var_30], rcx\nmov rax, [rbp+var_20]\ncmp rax, [rbp+var_30]\njz short loc_1334\nmov eax, 0\njmp locret_13C0\nloc_1334:\nmov [rbp+var_8], 0\njmp short loc_13B1\nloc_133E:\nmov rax, [rbp+var_8]\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rdx, [rax]\nmov rax, [rbp+var_8]\nshl rax, 4\nmov rcx, rax\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_13A5\nmov rax, [rbp+var_8]\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax+8]\nmov rax, [rbp+var_8]\nshl rax, 4\nmov rcx, rax\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax+8]\ncmp edx, eax\njz short loc_13AC\nloc_13A5:\nmov eax, 0\njmp short locret_13C0\nloc_13AC:\nadd [rbp+var_8], 1\nloc_13B1:\nmov rax, [rbp+var_8]\ncmp rax, [rbp+var_20]\njb short loc_133E\nmov eax, 1\nlocret_13C0:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1304(__int64 a1, unsigned __int64 a2, __int64 a3, __int64 a4)\n{\n unsigned __int64 i; // [rsp+28h] [rbp-8h]\n\n if ( a2 != a4 )\n return 0LL;\n for ( i = 0LL; i < a2; ++i )\n {\n if ( strcmp(*(const char **)(16 * i + a1), *(const char **)(16 * i + a3))\n || *(_DWORD *)(16 * i + a1 + 8) != *(_DWORD *)(16 * i + a3 + 8) )\n {\n return 0LL;\n }\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1304(long long a1, unsigned long long a2, long long a3,\n long long a4) {\n unsigned long long i;\n if (a2 != a4) return 0LL;\n for (i = 0LL; i < a2; ++i) {\n if (strcmp(*(const char **)(16 * i + a1), *(const char **)(16 * i + a3)) ||\n *(uint32_t *)(16 * i + a1 + 8) != *(uint32_t *)(16 * i + a3 + 8)) {\n return 0LL;\n }\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, unsigned long long a2, long long a3,\n long long a4) {\n unsigned long long i;\n if (a2 != a4) return 0LL;\n for (i = 0LL; i < a2; ++i) {\n if (strcmp(*(const char **)(16 * i + a1), *(const char **)(16 * i + a3)) ||\n *(uint32_t *)(16 * i + a1 + 8) != *(uint32_t *)(16 * i + a3 + 8)) {\n return 0LL;\n }\n }\n return 1LL;\n}" + }, + { + "index": 263, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char *key;\n\n int value;\n\n} dict_entry;\n\n\n\ndict_entry* merge_dict(const dict_entry *d1, size_t size1, const dict_entry *d2, size_t size2, size_t *size_out) {\n\n dict_entry *merged = malloc((size1 + size2) * sizeof(dict_entry));\n\n for (size_t i = 0; i < size1; i++) {\n\n merged[i].key = d1[i].key;\n\n merged[i].value = d1[i].value;\n\n }\n\n for (size_t i = 0; i < size2; i++) {\n\n merged[size1 + i].key = d2[i].key;\n\n merged[size1 + i].value = d2[i].value;\n\n }\n\n *size_out = size1 + size2;\n\n return merged;\n\n}\n\n\n\n", + "func": "int func0(const dict_entry *d1, size_t size1, const dict_entry *d2,\n size_t size2) {\n if (size1 != size2) return 0;\n for (size_t i = 0; i < size1; i++) {\n if (strcmp(d1[i].key, d2[i].key) != 0 || d1[i].value != d2[i].value) {\n return 0;\n }\n }\n return 1;\n}", + "test": "int main() {\n\n // Test case 1\n\n dict_entry d1_a[] = {{\"a\", 100}, {\"b\", 200}};\n\n dict_entry d2_a[] = {{\"x\", 300}, {\"y\", 200}};\n\n size_t size_a;\n\n dict_entry *merged_a = merge_dict(d1_a, 2, d2_a, 2, &size_a);\n\n dict_entry expected_a[] = {{\"a\", 100}, {\"b\", 200}, {\"x\", 300}, {\"y\", 200}};\n\n assert(func0(merged_a, size_a, expected_a, 4));\n\n free(merged_a);\n\n\n\n // Test case 2\n\n dict_entry d1_b[] = {{\"a\", 900}, {\"b\", 900}, {\"d\", 900}};\n\n dict_entry d2_b[] = {{\"a\", 900}, {\"b\", 900}, {\"d\", 900}};\n\n size_t size_b;\n\n dict_entry *merged_b = merge_dict(d1_b, 3, d2_b, 3, &size_b);\n\n dict_entry expected_b[] = {{\"a\", 900}, {\"b\", 900}, {\"d\", 900}, {\"a\", 900}, {\"b\", 900}, {\"d\", 900}};\n\n assert(func0(merged_b, size_b, expected_b, 6));\n\n free(merged_b);\n\n\n\n // Test case 3\n\n dict_entry d1_c[] = {{\"a\", 10}, {\"b\", 20}};\n\n dict_entry d2_c[] = {{\"x\", 30}, {\"y\", 40}};\n\n size_t size_c;\n\n dict_entry *merged_c = merge_dict(d1_c, 2, d2_c, 2, &size_c);\n\n dict_entry expected_c[] = {{\"a\", 10}, {\"b\", 20}, {\"x\", 30}, {\"y\", 40}};\n\n assert(func0(merged_c, size_c, expected_c, 4));\n\n free(merged_c);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x0,%eax\ncmp %rcx,%rsi\njne 12db \npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rsi,%r12\ntest %rsi,%rsi\nje 12c4 \nlea 0x8(%rdx),%rbp\nlea 0x8(%rdi),%rbx\nmov $0x0,%r13d\nmov -0x8(%rbp),%rsi\nmov -0x8(%rbx),%rdi\ncallq 10c0 \ntest %eax,%eax\njne 12cb \nmov 0x0(%rbp),%ecx\ncmp %ecx,(%rbx)\njne 12d0 \nadd $0x1,%r13\nadd $0x10,%rbp\nadd $0x10,%rbx\ncmp %r13,%r12\njne 1294 \nmov $0x1,%eax\njmp 12d0 \nmov $0x1,%eax\njmp 12d0 \nmov $0x0,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nretq\n", + "ida_asm": "func0:\nendbr64\nmov eax, 0\ncmp rsi, rcx\njnz short locret_12E1\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12, rsi\ntest rsi, rsi\njz short loc_12CA\nlea rbp, [rdx+8]\nlea rbx, [rdi+8]\nmov r13d, 0\nloc_129A:\nmov rsi, [rbp-8]; s2\nmov rdi, [rbx-8]; s1\ncall _strcmp\ntest eax, eax\njnz short loc_12D1\nmov ecx, [rbp+0]\ncmp [rbx], ecx\njnz short loc_12D6\nadd r13, 1\nadd rbp, 10h\nadd rbx, 10h\ncmp r12, r13\njnz short loc_129A\nmov eax, 1\njmp short loc_12D6\nloc_12CA:\nmov eax, 1\njmp short loc_12D6\nloc_12D1:\nmov eax, 0\nloc_12D6:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nlocret_12E1:\nretn", + "ida_pseudo": "int __fastcall func0(__int64 a1, __int64 a2, __int64 a3, __int64 a4)\n{\n int result; // eax\n const char **v5; // rbp\n const char **v6; // rbx\n __int64 v7; // r13\n\n result = 0;\n if ( a2 == a4 )\n {\n if ( a2 )\n {\n v5 = (const char **)(a3 + 8);\n v6 = (const char **)(a1 + 8);\n v7 = 0LL;\n while ( 1 )\n {\n result = strcmp(*(v6 - 1), *(v5 - 1));\n if ( result )\n break;\n if ( *(_DWORD *)v6 != *(_DWORD *)v5 )\n return result;\n ++v7;\n v5 += 2;\n v6 += 2;\n if ( a2 == v7 )\n return 1;\n }\n return 0;\n }\n else\n {\n return 1;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_126C:\nendbr64\nmov eax, 0\ncmp rsi, rcx\njnz short locret_12E1\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12, rsi\ntest rsi, rsi\njz short loc_12CA\nlea rbp, [rdx+8]\nlea rbx, [rdi+8]\nmov r13d, 0\nloc_129A:\nmov rsi, [rbp-8]; s2\nmov rdi, [rbx-8]; s1\ncall _strcmp\ntest eax, eax\njnz short loc_12D1\nmov ecx, [rbp+0]\ncmp [rbx], ecx\njnz short loc_12D6\nadd r13, 1\nadd rbp, 10h\nadd rbx, 10h\ncmp r12, r13\njnz short loc_129A\nmov eax, 1\njmp short loc_12D6\nloc_12CA:\nmov eax, 1\njmp short loc_12D6\nloc_12D1:\nmov eax, 0\nloc_12D6:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nlocret_12E1:\nretn", + "ida_strip_pseudo": "int __fastcall sub_126C(__int64 a1, __int64 a2, __int64 a3, __int64 a4)\n{\n int result; // eax\n const char **v5; // rbp\n const char **v6; // rbx\n __int64 v7; // r13\n\n result = 0;\n if ( a2 == a4 )\n {\n if ( a2 )\n {\n v5 = (const char **)(a3 + 8);\n v6 = (const char **)(a1 + 8);\n v7 = 0LL;\n while ( 1 )\n {\n result = strcmp(*(v6 - 1), *(v5 - 1));\n if ( result )\n break;\n if ( *(_DWORD *)v6 != *(_DWORD *)v5 )\n return result;\n ++v7;\n v5 += 2;\n v6 += 2;\n if ( a2 == v7 )\n return 1;\n }\n return 0;\n }\n else\n {\n return 1;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "int sub_126C(long long a1, long long a2, long long a3, long long a4) {\n int result;\n const char **v5;\n const char **v6;\n long long v7;\n result = 0;\n if (a2 == a4) {\n if (a2) {\n v5 = (const char **)(a3 + 8);\n v6 = (const char **)(a1 + 8);\n v7 = 0LL;\n while (1) {\n result = strcmp(*(v6 - 1), *(v5 - 1));\n if (result) break;\n if (*(uint32_t *)v6 != *(uint32_t *)v5) return result;\n ++v7;\n v5 += 2;\n v6 += 2;\n if (a2 == v7) return 1;\n }\n return 0;\n } else {\n return 1;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "int func0(long long a1, long long a2, long long a3, long long a4) {\n int result;\n const char **v5;\n const char **v6;\n long long v7;\n result = 0;\n if (a2 == a4) {\n if (a2) {\n v5 = (const char **)(a3 + 8);\n v6 = (const char **)(a1 + 8);\n v7 = 0LL;\n while (1) {\n result = strcmp(*(v6 - 1), *(v5 - 1));\n if (result) break;\n if (*(uint32_t *)v6 != *(uint32_t *)v5) return result;\n ++v7;\n v5 += 2;\n v6 += 2;\n if (a2 == v7) return 1;\n }\n return 0;\n } else {\n return 1;\n }\n }\n return result;\n}" + }, + { + "index": 263, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char *key;\n\n int value;\n\n} dict_entry;\n\n\n\ndict_entry* merge_dict(const dict_entry *d1, size_t size1, const dict_entry *d2, size_t size2, size_t *size_out) {\n\n dict_entry *merged = malloc((size1 + size2) * sizeof(dict_entry));\n\n for (size_t i = 0; i < size1; i++) {\n\n merged[i].key = d1[i].key;\n\n merged[i].value = d1[i].value;\n\n }\n\n for (size_t i = 0; i < size2; i++) {\n\n merged[size1 + i].key = d2[i].key;\n\n merged[size1 + i].value = d2[i].value;\n\n }\n\n *size_out = size1 + size2;\n\n return merged;\n\n}\n\n\n\n", + "func": "int func0(const dict_entry *d1, size_t size1, const dict_entry *d2,\n size_t size2) {\n if (size1 != size2) return 0;\n for (size_t i = 0; i < size1; i++) {\n if (strcmp(d1[i].key, d2[i].key) != 0 || d1[i].value != d2[i].value) {\n return 0;\n }\n }\n return 1;\n}", + "test": "int main() {\n\n // Test case 1\n\n dict_entry d1_a[] = {{\"a\", 100}, {\"b\", 200}};\n\n dict_entry d2_a[] = {{\"x\", 300}, {\"y\", 200}};\n\n size_t size_a;\n\n dict_entry *merged_a = merge_dict(d1_a, 2, d2_a, 2, &size_a);\n\n dict_entry expected_a[] = {{\"a\", 100}, {\"b\", 200}, {\"x\", 300}, {\"y\", 200}};\n\n assert(func0(merged_a, size_a, expected_a, 4));\n\n free(merged_a);\n\n\n\n // Test case 2\n\n dict_entry d1_b[] = {{\"a\", 900}, {\"b\", 900}, {\"d\", 900}};\n\n dict_entry d2_b[] = {{\"a\", 900}, {\"b\", 900}, {\"d\", 900}};\n\n size_t size_b;\n\n dict_entry *merged_b = merge_dict(d1_b, 3, d2_b, 3, &size_b);\n\n dict_entry expected_b[] = {{\"a\", 900}, {\"b\", 900}, {\"d\", 900}, {\"a\", 900}, {\"b\", 900}, {\"d\", 900}};\n\n assert(func0(merged_b, size_b, expected_b, 6));\n\n free(merged_b);\n\n\n\n // Test case 3\n\n dict_entry d1_c[] = {{\"a\", 10}, {\"b\", 20}};\n\n dict_entry d2_c[] = {{\"x\", 30}, {\"y\", 40}};\n\n size_t size_c;\n\n dict_entry *merged_c = merge_dict(d1_c, 2, d2_c, 2, &size_c);\n\n dict_entry expected_c[] = {{\"a\", 10}, {\"b\", 20}, {\"x\", 30}, {\"y\", 40}};\n\n assert(func0(merged_c, size_c, expected_c, 4));\n\n free(merged_c);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ncmp %rcx,%rsi\njne 16d0 \njmpq 1590 \nxchg %ax,%ax\nxor %eax,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0_part_0:\ntest rsi, rsi\njz short loc_1600\npush r13\nxor r13d, r13d\npush r12\nmov r12, rsi\npush rbp\nlea rbp, [rdx+8]\npush rbx\nlea rbx, [rdi+8]\nsub rsp, 8\njmp short loc_15C8\nloc_15B0:\nmov ecx, [rbp+0]\ncmp [rbx], ecx\njnz short loc_15DB\nadd r13, 1\nadd rbp, 10h\nadd rbx, 10h\ncmp r13, r12\njz short loc_15F0\nloc_15C8:\nmov rsi, [rbp-8]; s2\nmov rdi, [rbx-8]; s1\ncall _strcmp\ntest eax, eax\njz short loc_15B0\nxor eax, eax\nloc_15DB:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_15F0:\nadd rsp, 8\nmov eax, 1\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1600:\nmov eax, 1\nretn", + "ida_pseudo": "int __fastcall func0_part_0(__int64 a1, __int64 a2, __int64 a3)\n{\n __int64 v3; // r13\n const char **v4; // rbp\n const char **v5; // rbx\n int result; // eax\n\n if ( !a2 )\n return 1;\n v3 = 0LL;\n v4 = (const char **)(a3 + 8);\n v5 = (const char **)(a1 + 8);\n do\n {\n result = strcmp(*(v5 - 1), *(v4 - 1));\n if ( result )\n return 0;\n if ( *(_DWORD *)v5 != *(_DWORD *)v4 )\n return result;\n ++v3;\n v4 += 2;\n v5 += 2;\n }\n while ( v3 != a2 );\n return 1;\n}", + "ida_strip_asm": "sub_1590:\ntest rsi, rsi\njz short loc_1600\npush r13\nxor r13d, r13d\npush r12\nmov r12, rsi\npush rbp\nlea rbp, [rdx+8]\npush rbx\nlea rbx, [rdi+8]\nsub rsp, 8\njmp short loc_15C8\nloc_15B0:\nmov ecx, [rbp+0]\ncmp [rbx], ecx\njnz short loc_15DB\nadd r13, 1\nadd rbp, 10h\nadd rbx, 10h\ncmp r13, r12\njz short loc_15F0\nloc_15C8:\nmov rsi, [rbp-8]; s2\nmov rdi, [rbx-8]; s1\ncall _strcmp\ntest eax, eax\njz short loc_15B0\nxor eax, eax\nloc_15DB:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_15F0:\nadd rsp, 8\nmov eax, 1\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1600:\nmov eax, 1\nretn", + "ida_strip_pseudo": "int __fastcall sub_1590(__int64 a1, __int64 a2, __int64 a3)\n{\n __int64 v3; // r13\n const char **v4; // rbp\n const char **v5; // rbx\n int result; // eax\n\n if ( !a2 )\n return 1;\n v3 = 0LL;\n v4 = (const char **)(a3 + 8);\n v5 = (const char **)(a1 + 8);\n do\n {\n result = strcmp(*(v5 - 1), *(v4 - 1));\n if ( result )\n return 0;\n if ( *(_DWORD *)v5 != *(_DWORD *)v4 )\n return result;\n ++v3;\n v4 += 2;\n v5 += 2;\n }\n while ( v3 != a2 );\n return 1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "int sub_1590(long long a1, long long a2, long long a3) {\n long long v3;\n const char **v4;\n const char **v5;\n int result;\n if (!a2) return 1;\n v3 = 0LL;\n v4 = (const char **)(a3 + 8);\n v5 = (const char **)(a1 + 8);\n do {\n result = strcmp(*(v5 - 1), *(v4 - 1));\n if (result) return 0;\n if (*(uint32_t *)v5 != *(uint32_t *)v4) return result;\n ++v3;\n v4 += 2;\n v5 += 2;\n } while (v3 != a2);\n return 1;\n}", + "ida_pseudo_norm": "int func0_part_0(long long a1, long long a2, long long a3) {\n long long v3;\n const char **v4;\n const char **v5;\n int result;\n if (!a2) return 1;\n v3 = 0LL;\n v4 = (const char **)(a3 + 8);\n v5 = (const char **)(a1 + 8);\n do {\n result = strcmp(*(v5 - 1), *(v4 - 1));\n if (result) return 0;\n if (*(uint32_t *)v5 != *(uint32_t *)v4) return result;\n ++v3;\n v4 += 2;\n v5 += 2;\n } while (v3 != a2);\n return 1;\n}" + }, + { + "index": 263, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char *key;\n\n int value;\n\n} dict_entry;\n\n\n\ndict_entry* merge_dict(const dict_entry *d1, size_t size1, const dict_entry *d2, size_t size2, size_t *size_out) {\n\n dict_entry *merged = malloc((size1 + size2) * sizeof(dict_entry));\n\n for (size_t i = 0; i < size1; i++) {\n\n merged[i].key = d1[i].key;\n\n merged[i].value = d1[i].value;\n\n }\n\n for (size_t i = 0; i < size2; i++) {\n\n merged[size1 + i].key = d2[i].key;\n\n merged[size1 + i].value = d2[i].value;\n\n }\n\n *size_out = size1 + size2;\n\n return merged;\n\n}\n\n\n\n", + "func": "int func0(const dict_entry *d1, size_t size1, const dict_entry *d2,\n size_t size2) {\n if (size1 != size2) return 0;\n for (size_t i = 0; i < size1; i++) {\n if (strcmp(d1[i].key, d2[i].key) != 0 || d1[i].value != d2[i].value) {\n return 0;\n }\n }\n return 1;\n}", + "test": "int main() {\n\n // Test case 1\n\n dict_entry d1_a[] = {{\"a\", 100}, {\"b\", 200}};\n\n dict_entry d2_a[] = {{\"x\", 300}, {\"y\", 200}};\n\n size_t size_a;\n\n dict_entry *merged_a = merge_dict(d1_a, 2, d2_a, 2, &size_a);\n\n dict_entry expected_a[] = {{\"a\", 100}, {\"b\", 200}, {\"x\", 300}, {\"y\", 200}};\n\n assert(func0(merged_a, size_a, expected_a, 4));\n\n free(merged_a);\n\n\n\n // Test case 2\n\n dict_entry d1_b[] = {{\"a\", 900}, {\"b\", 900}, {\"d\", 900}};\n\n dict_entry d2_b[] = {{\"a\", 900}, {\"b\", 900}, {\"d\", 900}};\n\n size_t size_b;\n\n dict_entry *merged_b = merge_dict(d1_b, 3, d2_b, 3, &size_b);\n\n dict_entry expected_b[] = {{\"a\", 900}, {\"b\", 900}, {\"d\", 900}, {\"a\", 900}, {\"b\", 900}, {\"d\", 900}};\n\n assert(func0(merged_b, size_b, expected_b, 6));\n\n free(merged_b);\n\n\n\n // Test case 3\n\n dict_entry d1_c[] = {{\"a\", 10}, {\"b\", 20}};\n\n dict_entry d2_c[] = {{\"x\", 30}, {\"y\", 40}};\n\n size_t size_c;\n\n dict_entry *merged_c = merge_dict(d1_c, 2, d2_c, 2, &size_c);\n\n dict_entry expected_c[] = {{\"a\", 10}, {\"b\", 20}, {\"x\", 30}, {\"y\", 40}};\n\n assert(func0(merged_c, size_c, expected_c, 4));\n\n free(merged_c);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nxor %eax,%eax\ncmp %rcx,%rsi\njne 1730 \npush %r13\npush %r12\nmov %rsi,%r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\ntest %rsi,%rsi\nje 1738 \nlea 0x8(%rdx),%rbp\nlea 0x8(%rdi),%rbx\nxor %r13d,%r13d\njmp 1708 \nnopw 0x0(%rax,%rax,1)\nmov 0x0(%rbp),%ecx\ncmp %ecx,(%rbx)\njne 171b \nadd $0x1,%r13\nadd $0x10,%rbp\nadd $0x10,%rbx\ncmp %r13,%r12\nje 1738 \nmov -0x8(%rbp),%rsi\nmov -0x8(%rbx),%rdi\ncallq 10c0 \ntest %eax,%eax\nje 16f0 \nxor %eax,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopw %cs:0x0(%rax,%rax,1)\nretq\nnopl 0x0(%rax)\nadd $0x8,%rsp\nmov $0x1,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0_part_0:\ntest rsi, rsi\njz short loc_1600\npush r13\nxor r13d, r13d\npush r12\nmov r12, rsi\npush rbp\nlea rbp, [rdx+8]\npush rbx\nlea rbx, [rdi+8]\nsub rsp, 8\njmp short loc_15C8\nloc_15B0:\nmov ecx, [rbp+0]\ncmp [rbx], ecx\njnz short loc_15DB\nadd r13, 1\nadd rbp, 10h\nadd rbx, 10h\ncmp r13, r12\njz short loc_15F0\nloc_15C8:\nmov rsi, [rbp-8]; s2\nmov rdi, [rbx-8]; s1\ncall _strcmp\ntest eax, eax\njz short loc_15B0\nxor eax, eax\nloc_15DB:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_15F0:\nadd rsp, 8\nmov eax, 1\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1600:\nmov eax, 1\nretn", + "ida_pseudo": "int __fastcall func0_part_0(__int64 a1, __int64 a2, __int64 a3)\n{\n __int64 v3; // r13\n const char **v4; // rbp\n const char **v5; // rbx\n int result; // eax\n\n if ( !a2 )\n return 1;\n v3 = 0LL;\n v4 = (const char **)(a3 + 8);\n v5 = (const char **)(a1 + 8);\n do\n {\n result = strcmp(*(v5 - 1), *(v4 - 1));\n if ( result )\n return 0;\n if ( *(_DWORD *)v5 != *(_DWORD *)v4 )\n return result;\n ++v3;\n v4 += 2;\n v5 += 2;\n }\n while ( v3 != a2 );\n return 1;\n}", + "ida_strip_asm": "sub_1590:\ntest rsi, rsi\njz short loc_1600\npush r13\nxor r13d, r13d\npush r12\nmov r12, rsi\npush rbp\nlea rbp, [rdx+8]\npush rbx\nlea rbx, [rdi+8]\nsub rsp, 8\njmp short loc_15C8\nloc_15B0:\nmov ecx, [rbp+0]\ncmp [rbx], ecx\njnz short loc_15DB\nadd r13, 1\nadd rbp, 10h\nadd rbx, 10h\ncmp r13, r12\njz short loc_15F0\nloc_15C8:\nmov rsi, [rbp-8]; s2\nmov rdi, [rbx-8]; s1\ncall _strcmp\ntest eax, eax\njz short loc_15B0\nxor eax, eax\nloc_15DB:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_15F0:\nadd rsp, 8\nmov eax, 1\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1600:\nmov eax, 1\nretn", + "ida_strip_pseudo": "int __fastcall sub_1590(__int64 a1, __int64 a2, __int64 a3)\n{\n __int64 v3; // r13\n const char **v4; // rbp\n const char **v5; // rbx\n int result; // eax\n\n if ( !a2 )\n return 1;\n v3 = 0LL;\n v4 = (const char **)(a3 + 8);\n v5 = (const char **)(a1 + 8);\n do\n {\n result = strcmp(*(v5 - 1), *(v4 - 1));\n if ( result )\n return 0;\n if ( *(_DWORD *)v5 != *(_DWORD *)v4 )\n return result;\n ++v3;\n v4 += 2;\n v5 += 2;\n }\n while ( v3 != a2 );\n return 1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "int sub_1590(long long a1, long long a2, long long a3) {\n long long v3;\n const char **v4;\n const char **v5;\n int result;\n if (!a2) return 1;\n v3 = 0LL;\n v4 = (const char **)(a3 + 8);\n v5 = (const char **)(a1 + 8);\n do {\n result = strcmp(*(v5 - 1), *(v4 - 1));\n if (result) return 0;\n if (*(uint32_t *)v5 != *(uint32_t *)v4) return result;\n ++v3;\n v4 += 2;\n v5 += 2;\n } while (v3 != a2);\n return 1;\n}", + "ida_pseudo_norm": "int func0_part_0(long long a1, long long a2, long long a3) {\n long long v3;\n const char **v4;\n const char **v5;\n int result;\n if (!a2) return 1;\n v3 = 0LL;\n v4 = (const char **)(a3 + 8);\n v5 = (const char **)(a1 + 8);\n do {\n result = strcmp(*(v5 - 1), *(v4 - 1));\n if (result) return 0;\n if (*(uint32_t *)v5 != *(uint32_t *)v4) return result;\n ++v3;\n v4 += 2;\n v5 += 2;\n } while (v3 != a2);\n return 1;\n}" + }, + { + "index": 264, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int h_age) {\n double d_age;\n if (h_age < 0) {\n exit(EXIT_FAILURE);\n } else if (h_age <= 2) {\n d_age = h_age * 10.5;\n } else {\n d_age = 21 + (h_age - 2) * 4;\n }\n return d_age;\n}", + "test": "int main() {\n\n assert(func0(12) == 61);\n\n assert(func0(15) == 73);\n\n assert(func0(24) == 109);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %edi,-0x14(%rbp)\ncmpl $0x0,-0x14(%rbp)\njns 1188 \nmov $0x1,%edi\ncallq 1070 \ncmpl $0x2,-0x14(%rbp)\njg 11a6 \ncvtsi2sdl -0x14(%rbp),%xmm1\nmovsd 0xee5(%rip),%xmm0\nmulsd %xmm1,%xmm0\nmovsd %xmm0,-0x8(%rbp)\njmp 11bb \nmov -0x14(%rbp),%eax\nsub $0x2,%eax\nshl $0x2,%eax\nadd $0x15,%eax\ncvtsi2sd %eax,%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmovsd -0x8(%rbp),%xmm0\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\ncmp [rbp+var_14], 0\njns short loc_1188\nmov edi, 1; status\ncall _exit\nloc_1188:\ncmp [rbp+var_14], 2\njg short loc_11AA\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_14]\nmovsd xmm0, cs:qword_2060\nmulsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\njmp short loc_11C3\nloc_11AA:\nmov eax, [rbp+var_14]\nsub eax, 2\nshl eax, 2\nadd eax, 15h\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmovsd [rbp+var_8], xmm0\nloc_11C3:\nmovsd xmm0, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "double __fastcall func0(int a1)\n{\n if ( a1 < 0 )\n exit(1);\n if ( a1 > 2 )\n return (double)(4 * (a1 - 2) + 21);\n else\n return 10.5 * (double)a1;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\ncmp [rbp+var_14], 0\njns short loc_1188\nmov edi, 1; status\ncall _exit\nloc_1188:\ncmp [rbp+var_14], 2\njg short loc_11AA\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_14]\nmovsd xmm0, cs:qword_2060\nmulsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\njmp short loc_11C3\nloc_11AA:\nmov eax, [rbp+var_14]\nsub eax, 2\nshl eax, 2\nadd eax, 15h\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmovsd [rbp+var_8], xmm0\nloc_11C3:\nmovsd xmm0, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "double __fastcall sub_1169(int a1)\n{\n if ( a1 < 0 )\n exit(1);\n if ( a1 > 2 )\n return (double)(4 * (a1 - 2) + 21);\n else\n return 10.5 * (double)a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1169(int a1) {\n if (a1 < 0) exit(1);\n if (a1 > 2)\n return (double)(4 * (a1 - 2) + 21);\n else\n return 10.5 * (double)a1;\n}", + "ida_pseudo_norm": "double func0(int a1) {\n if (a1 < 0) exit(1);\n if (a1 > 2)\n return (double)(4 * (a1 - 2) + 21);\n else\n return 10.5 * (double)a1;\n}" + }, + { + "index": 265, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n// Function to split integer arrays\n\nint** list_split_int(int *S, int length, int step) {\n\n int **result = malloc(step * sizeof(int*));\n\n for(int i = 0; i < step; i++) {\n\n int count = 0;\n\n for(int j = i; j < length; j += step) {\n\n count++;\n\n }\n\n result[i] = malloc(count * sizeof(int));\n\n int index = 0;\n\n for(int j = i; j < length; j += step) {\n\n result[i][index++] = S[j];\n\n }\n\n }\n\n return result;\n\n}\n\n\n\n// Function to split string arrays\n\nchar*** list_split_str(char **S, int length, int step) {\n\n char ***result = malloc(step * sizeof(char**));\n\n for(int i = 0; i < step; i++) {\n\n int count = 0;\n\n for(int j = i; j < length; j += step) {\n\n count++;\n\n }\n\n result[i] = malloc(count * sizeof(char*));\n\n int index = 0;\n\n for(int j = i; j < length; j += step) {\n\n result[i][index++] = S[j];\n\n }\n\n }\n\n return result;\n\n}\n\n\n\n// Function to compare integer split results\n\nint compare_split_int(int **result, int **expected, int step, int *sizes) {\n\n for(int i = 0; i < step; i++) {\n\n for(int j = 0; j < sizes[i]; j++) {\n\n if(result[i][j] != expected[i][j]) {\n\n return 0;\n\n }\n\n }\n\n }\n\n return 1;\n\n}\n\n\n\n// Function to compare string split results\n\n", + "func": "int func0(char ***result, char ***expected, int step, int *sizes) {\n for (int i = 0; i < step; i++) {\n for (int j = 0; j < sizes[i]; j++) {\n if (strcmp(result[i][j], expected[i][j]) != 0) {\n return 0;\n }\n }\n }\n return 1;\n}", + "test": "int main() {\n\n // First assert with strings\n\n char *S1[] = {\"a\", \"b\", \"c\", \"d\", \"e\", \"f\", \"g\", \"h\", \"i\", \"j\", \"k\", \"l\", \"m\", \"n\"};\n\n int length1 = sizeof(S1) / sizeof(S1[0]);\n\n int step1 = 3;\n\n char ***split1 = list_split_str(S1, length1, step1);\n\n char *expected1[][5] = {{\"a\", \"d\", \"g\", \"j\", \"m\"}, {\"b\", \"e\", \"h\", \"k\", \"n\"}, {\"c\", \"f\", \"i\", \"l\", NULL}};\n\n int sizes1[] = {5,5,4};\n\n // Prepare expected split\n\n char **exp1[3];\n\n exp1[0] = expected1[0];\n\n exp1[1] = expected1[1];\n\n exp1[2] = expected1[2];\n\n assert(func0(split1, exp1, step1, sizes1));\n\n\n\n // Second assert with integers\n\n int S2[] = {1,2,3,4,5,6,7,8,9,10,11,12,13,14};\n\n int length2 = sizeof(S2) / sizeof(S2[0]);\n\n int step2 = 3;\n\n int **split2 = list_split_int(S2, length2, step2);\n\n int expected2[][5] = {{1,4,7,10,13}, {2,5,8,11,14}, {3,6,9,12}};\n\n int sizes2[] = {5,5,4};\n\n // Prepare expected split\n\n int *exp2[3];\n\n exp2[0] = expected2[0];\n\n exp2[1] = expected2[1];\n\n exp2[2] = expected2[2];\n\n assert(compare_split_int(split2, exp2, step2, sizes2));\n\n\n\n // Third assert with strings\n\n char *S3[] = {\"python\",\"java\",\"C\",\"C++\",\"DBMS\",\"SQL\"};\n\n int length3 = sizeof(S3) / sizeof(S3[0]);\n\n int step3 = 2;\n\n char ***split3 = list_split_str(S3, length3, step3);\n\n char *expected3[][3] = {{\"python\", \"C\", \"DBMS\"}, {\"java\", \"C++\", \"SQL\"}};\n\n int sizes3[] = {3,3};\n\n // Prepare expected split\n\n char **exp3[2];\n\n exp3[0] = expected3[0];\n\n exp3[1] = expected3[1];\n\n assert(func0(split3, exp3, step3, sizes3));\n\n\n\n // Free allocated memory\n\n for(int i = 0; i < step1; i++) {\n\n free(split1[i]);\n\n }\n\n free(split1);\n\n\n\n for(int i = 0; i < step2; i++) {\n\n free(split2[i]);\n\n }\n\n free(split2);\n\n\n\n for(int i = 0; i < step3; i++) {\n\n free(split3[i]);\n\n }\n\n free(split3);\n\n\n\n printf(\"All asserts passed successfully.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %edx,-0x24(%rbp)\nmov %rcx,-0x30(%rbp)\nmovl $0x0,-0x8(%rbp)\njmpq 155b \nmovl $0x0,-0x4(%rbp)\njmp 1538 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0x4(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x3,%rdx\nadd %rdx,%rax\nmov (%rax),%rdx\nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%rax\nmov -0x4(%rbp),%ecx\nmovslq %ecx,%rcx\nshl $0x3,%rcx\nadd %rcx,%rax\nmov (%rax),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10e0 \ntest %eax,%eax\nje 1534 \nmov $0x0,%eax\njmp 156c \naddl $0x1,-0x4(%rbp)\nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x30(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x4(%rbp)\njl 14d0 \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x24(%rbp),%eax\njl 14c7 \nmov $0x1,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_30], rcx\nmov [rbp+var_8], 0\njmp loc_1559\nloc_14C5:\nmov [rbp+var_4], 0\njmp short loc_1536\nloc_14CE:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nshl rdx, 3\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov rax, [rax]\nmov ecx, [rbp+var_4]\nmovsxd rcx, ecx\nshl rcx, 3\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_1532\nmov eax, 0\njmp short locret_156A\nloc_1532:\nadd [rbp+var_4], 1\nloc_1536:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_4], eax\njl loc_14CE\nadd [rbp+var_8], 1\nloc_1559:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_24]\njl loc_14C5\nmov eax, 1\nlocret_156A:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3, __int64 a4)\n{\n int i; // [rsp+28h] [rbp-8h]\n int j; // [rsp+2Ch] [rbp-4h]\n\n for ( i = 0; i < a3; ++i )\n {\n for ( j = 0; j < *(_DWORD *)(4LL * i + a4); ++j )\n {\n if ( strcmp(\n *(const char **)(8LL * j + *(_QWORD *)(8LL * i + a1)),\n *(const char **)(8LL * j + *(_QWORD *)(8LL * i + a2))) )\n {\n return 0LL;\n }\n }\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_149E:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_30], rcx\nmov [rbp+var_8], 0\njmp loc_1559\nloc_14C5:\nmov [rbp+var_4], 0\njmp short loc_1536\nloc_14CE:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nshl rdx, 3\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov rax, [rax]\nmov ecx, [rbp+var_4]\nmovsxd rcx, ecx\nshl rcx, 3\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_1532\nmov eax, 0\njmp short locret_156A\nloc_1532:\nadd [rbp+var_4], 1\nloc_1536:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_4], eax\njl loc_14CE\nadd [rbp+var_8], 1\nloc_1559:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_24]\njl loc_14C5\nmov eax, 1\nlocret_156A:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_149E(__int64 a1, __int64 a2, int a3, __int64 a4)\n{\n int i; // [rsp+28h] [rbp-8h]\n int j; // [rsp+2Ch] [rbp-4h]\n\n for ( i = 0; i < a3; ++i )\n {\n for ( j = 0; j < *(_DWORD *)(4LL * i + a4); ++j )\n {\n if ( strcmp(\n *(const char **)(8LL * j + *(_QWORD *)(8LL * i + a1)),\n *(const char **)(8LL * j + *(_QWORD *)(8LL * i + a2))) )\n {\n return 0LL;\n }\n }\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_149E(long long a1, long long a2, int a3, long long a4) {\n int i;\n int j;\n for (i = 0; i < a3; ++i) {\n for (j = 0; j < *(uint32_t *)(4LL * i + a4); ++j) {\n if (strcmp(*(const char **)(8LL * j + *(uint64_t *)(8LL * i + a1)),\n *(const char **)(8LL * j + *(uint64_t *)(8LL * i + a2)))) {\n return 0LL;\n }\n }\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3, long long a4) {\n int i;\n int j;\n for (i = 0; i < a3; ++i) {\n for (j = 0; j < *(uint32_t *)(4LL * i + a4); ++j) {\n if (strcmp(*(const char **)(8LL * j + *(uint64_t *)(8LL * i + a1)),\n *(const char **)(8LL * j + *(uint64_t *)(8LL * i + a2)))) {\n return 0LL;\n }\n }\n }\n return 1LL;\n}" + }, + { + "index": 265, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n// Function to split integer arrays\n\nint** list_split_int(int *S, int length, int step) {\n\n int **result = malloc(step * sizeof(int*));\n\n for(int i = 0; i < step; i++) {\n\n int count = 0;\n\n for(int j = i; j < length; j += step) {\n\n count++;\n\n }\n\n result[i] = malloc(count * sizeof(int));\n\n int index = 0;\n\n for(int j = i; j < length; j += step) {\n\n result[i][index++] = S[j];\n\n }\n\n }\n\n return result;\n\n}\n\n\n\n// Function to split string arrays\n\nchar*** list_split_str(char **S, int length, int step) {\n\n char ***result = malloc(step * sizeof(char**));\n\n for(int i = 0; i < step; i++) {\n\n int count = 0;\n\n for(int j = i; j < length; j += step) {\n\n count++;\n\n }\n\n result[i] = malloc(count * sizeof(char*));\n\n int index = 0;\n\n for(int j = i; j < length; j += step) {\n\n result[i][index++] = S[j];\n\n }\n\n }\n\n return result;\n\n}\n\n\n\n// Function to compare integer split results\n\nint compare_split_int(int **result, int **expected, int step, int *sizes) {\n\n for(int i = 0; i < step; i++) {\n\n for(int j = 0; j < sizes[i]; j++) {\n\n if(result[i][j] != expected[i][j]) {\n\n return 0;\n\n }\n\n }\n\n }\n\n return 1;\n\n}\n\n\n\n// Function to compare string split results\n\n", + "func": "int func0(char ***result, char ***expected, int step, int *sizes) {\n for (int i = 0; i < step; i++) {\n for (int j = 0; j < sizes[i]; j++) {\n if (strcmp(result[i][j], expected[i][j]) != 0) {\n return 0;\n }\n }\n }\n return 1;\n}", + "test": "int main() {\n\n // First assert with strings\n\n char *S1[] = {\"a\", \"b\", \"c\", \"d\", \"e\", \"f\", \"g\", \"h\", \"i\", \"j\", \"k\", \"l\", \"m\", \"n\"};\n\n int length1 = sizeof(S1) / sizeof(S1[0]);\n\n int step1 = 3;\n\n char ***split1 = list_split_str(S1, length1, step1);\n\n char *expected1[][5] = {{\"a\", \"d\", \"g\", \"j\", \"m\"}, {\"b\", \"e\", \"h\", \"k\", \"n\"}, {\"c\", \"f\", \"i\", \"l\", NULL}};\n\n int sizes1[] = {5,5,4};\n\n // Prepare expected split\n\n char **exp1[3];\n\n exp1[0] = expected1[0];\n\n exp1[1] = expected1[1];\n\n exp1[2] = expected1[2];\n\n assert(func0(split1, exp1, step1, sizes1));\n\n\n\n // Second assert with integers\n\n int S2[] = {1,2,3,4,5,6,7,8,9,10,11,12,13,14};\n\n int length2 = sizeof(S2) / sizeof(S2[0]);\n\n int step2 = 3;\n\n int **split2 = list_split_int(S2, length2, step2);\n\n int expected2[][5] = {{1,4,7,10,13}, {2,5,8,11,14}, {3,6,9,12}};\n\n int sizes2[] = {5,5,4};\n\n // Prepare expected split\n\n int *exp2[3];\n\n exp2[0] = expected2[0];\n\n exp2[1] = expected2[1];\n\n exp2[2] = expected2[2];\n\n assert(compare_split_int(split2, exp2, step2, sizes2));\n\n\n\n // Third assert with strings\n\n char *S3[] = {\"python\",\"java\",\"C\",\"C++\",\"DBMS\",\"SQL\"};\n\n int length3 = sizeof(S3) / sizeof(S3[0]);\n\n int step3 = 2;\n\n char ***split3 = list_split_str(S3, length3, step3);\n\n char *expected3[][3] = {{\"python\", \"C\", \"DBMS\"}, {\"java\", \"C++\", \"SQL\"}};\n\n int sizes3[] = {3,3};\n\n // Prepare expected split\n\n char **exp3[2];\n\n exp3[0] = expected3[0];\n\n exp3[1] = expected3[1];\n\n assert(func0(split3, exp3, step3, sizes3));\n\n\n\n // Free allocated memory\n\n for(int i = 0; i < step1; i++) {\n\n free(split1[i]);\n\n }\n\n free(split1);\n\n\n\n for(int i = 0; i < step2; i++) {\n\n free(split2[i]);\n\n }\n\n free(split2);\n\n\n\n for(int i = 0; i < step3; i++) {\n\n free(split3[i]);\n\n }\n\n free(split3);\n\n\n\n printf(\"All asserts passed successfully.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x28,%rsp\nmov %rdi,0x8(%rsp)\nmov %rsi,0x10(%rsp)\ntest %edx,%edx\njle 1456 \nmov %rcx,%r15\nlea -0x1(%rdx),%eax\nmov %rax,0x18(%rsp)\nmov $0x0,%r14d\nmov (%r15,%r14,4),%eax\ntest %eax,%eax\njle 1446 \nmov 0x10(%rsp),%rcx\nmov (%rcx,%r14,8),%r12\nmov 0x8(%rsp),%rdx\nmov (%rdx,%r14,8),%rbp\nlea -0x1(%rax),%r13d\nmov $0x0,%ebx\njmp 142b \nmov %rax,%rbx\nmov (%r12,%rbx,8),%rsi\nmov 0x0(%rbp,%rbx,8),%rdi\ncallq 10e0 \ntest %eax,%eax\njne 145d \nlea 0x1(%rbx),%rax\ncmp %rbx,%r13\njne 1428 \nlea 0x1(%r14),%rax\ncmp 0x18(%rsp),%r14\nje 1471 \nmov %rax,%r14\njmp 1403 \nmov $0x1,%eax\njmp 1462 \nmov $0x0,%eax\nadd $0x28,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmov $0x1,%eax\njmp 1462 \n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_48], rdi\ntest edx, edx\njle short loc_141D\nmov r15, rsi\nmov r14, rcx\nmovsxd rax, edx\nmov [rsp+48h+var_40], rax\nmov r13d, 0\nloc_13D1:\nmov eax, [r14+r13*4]\ntest eax, eax\njle short loc_1408\nmov rbx, [r15+r13*8]\nmov rcx, [rsp+48h+var_48]\nmov rbp, [rcx+r13*8]\ncdqe\nlea r12, [rbx+rax*8]\nloc_13EB:\nmov rsi, [rbx]; s2\nmov rdi, [rbp+0]; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1424\nadd rbx, 8\nadd rbp, 8\ncmp rbx, r12\njnz short loc_13EB\nloc_1408:\nadd r13, 1\nmov rax, [rsp+48h+var_40]\ncmp r13, rax\njnz short loc_13D1\nmov eax, 1\njmp short loc_1429\nloc_141D:\nmov eax, 1\njmp short loc_1429\nloc_1424:\nmov eax, 0\nloc_1429:\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3, __int64 a4)\n{\n __int64 v5; // r13\n int v6; // eax\n const char **v7; // rbx\n const char **v8; // rbp\n const char **v9; // r12\n __int64 v11; // [rsp+8h] [rbp-40h]\n\n if ( a3 <= 0 )\n return 1LL;\n v11 = a3;\n v5 = 0LL;\n while ( 1 )\n {\n v6 = *(_DWORD *)(a4 + 4 * v5);\n if ( v6 > 0 )\n break;\nLABEL_7:\n if ( ++v5 == v11 )\n return 1LL;\n }\n v7 = *(const char ***)(a2 + 8 * v5);\n v8 = *(const char ***)(a1 + 8 * v5);\n v9 = &v7[v6];\n while ( !strcmp(*v8, *v7) )\n {\n ++v7;\n ++v8;\n if ( v7 == v9 )\n goto LABEL_7;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_13A3:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_48], rdi\ntest edx, edx\njle short loc_141D\nmov r15, rsi\nmov r14, rcx\nmovsxd rax, edx\nmov [rsp+48h+var_40], rax\nmov r13d, 0\nloc_13D1:\nmov eax, [r14+r13*4]\ntest eax, eax\njle short loc_1408\nmov rbx, [r15+r13*8]\nmov rcx, [rsp+48h+var_48]\nmov rbp, [rcx+r13*8]\ncdqe\nlea r12, [rbx+rax*8]\nloc_13EB:\nmov rsi, [rbx]; s2\nmov rdi, [rbp+0]; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1424\nadd rbx, 8\nadd rbp, 8\ncmp rbx, r12\njnz short loc_13EB\nloc_1408:\nadd r13, 1\nmov rax, [rsp+48h+var_40]\ncmp r13, rax\njnz short loc_13D1\nmov eax, 1\njmp short loc_1429\nloc_141D:\nmov eax, 1\njmp short loc_1429\nloc_1424:\nmov eax, 0\nloc_1429:\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_13A3(__int64 a1, __int64 a2, int a3, __int64 a4)\n{\n __int64 v5; // r13\n int v6; // eax\n const char **v7; // rbx\n const char **v8; // rbp\n const char **v9; // r12\n __int64 v11; // [rsp+8h] [rbp-40h]\n\n if ( a3 <= 0 )\n return 1LL;\n v11 = a3;\n v5 = 0LL;\n while ( 1 )\n {\n v6 = *(_DWORD *)(a4 + 4 * v5);\n if ( v6 > 0 )\n break;\nLABEL_7:\n if ( ++v5 == v11 )\n return 1LL;\n }\n v7 = *(const char ***)(a2 + 8 * v5);\n v8 = *(const char ***)(a1 + 8 * v5);\n v9 = &v7[v6];\n while ( !strcmp(*v8, *v7) )\n {\n ++v7;\n ++v8;\n if ( v7 == v9 )\n goto LABEL_7;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_13A3(long long a1, long long a2, int a3, long long a4) {\n long long v5;\n int v6;\n const char **v7;\n const char **v8;\n const char **v9;\n long long v11;\n if (a3 <= 0) return 1LL;\n v11 = a3;\n v5 = 0LL;\n while (1) {\n v6 = *(uint32_t *)(a4 + 4 * v5);\n if (v6 > 0) break;\n LABEL_7:\n if (++v5 == v11) return 1LL;\n }\n v7 = *(const char ***)(a2 + 8 * v5);\n v8 = *(const char ***)(a1 + 8 * v5);\n v9 = &v7[v6];\n while (!strcmp(*v8, *v7)) {\n ++v7;\n ++v8;\n if (v7 == v9) goto LABEL_7;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3, long long a4) {\n long long v5;\n int v6;\n const char **v7;\n const char **v8;\n const char **v9;\n long long v11;\n if (a3 <= 0) return 1LL;\n v11 = a3;\n v5 = 0LL;\n while (1) {\n v6 = *(uint32_t *)(a4 + 4 * v5);\n if (v6 > 0) break;\n LABEL_7:\n if (++v5 == v11) return 1LL;\n }\n v7 = *(const char ***)(a2 + 8 * v5);\n v8 = *(const char ***)(a1 + 8 * v5);\n v9 = &v7[v6];\n while (!strcmp(*v8, *v7)) {\n ++v7;\n ++v8;\n if (v7 == v9) goto LABEL_7;\n }\n return 0LL;\n}" + }, + { + "index": 265, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n// Function to split integer arrays\n\nint** list_split_int(int *S, int length, int step) {\n\n int **result = malloc(step * sizeof(int*));\n\n for(int i = 0; i < step; i++) {\n\n int count = 0;\n\n for(int j = i; j < length; j += step) {\n\n count++;\n\n }\n\n result[i] = malloc(count * sizeof(int));\n\n int index = 0;\n\n for(int j = i; j < length; j += step) {\n\n result[i][index++] = S[j];\n\n }\n\n }\n\n return result;\n\n}\n\n\n\n// Function to split string arrays\n\nchar*** list_split_str(char **S, int length, int step) {\n\n char ***result = malloc(step * sizeof(char**));\n\n for(int i = 0; i < step; i++) {\n\n int count = 0;\n\n for(int j = i; j < length; j += step) {\n\n count++;\n\n }\n\n result[i] = malloc(count * sizeof(char*));\n\n int index = 0;\n\n for(int j = i; j < length; j += step) {\n\n result[i][index++] = S[j];\n\n }\n\n }\n\n return result;\n\n}\n\n\n\n// Function to compare integer split results\n\nint compare_split_int(int **result, int **expected, int step, int *sizes) {\n\n for(int i = 0; i < step; i++) {\n\n for(int j = 0; j < sizes[i]; j++) {\n\n if(result[i][j] != expected[i][j]) {\n\n return 0;\n\n }\n\n }\n\n }\n\n return 1;\n\n}\n\n\n\n// Function to compare string split results\n\n", + "func": "int func0(char ***result, char ***expected, int step, int *sizes) {\n for (int i = 0; i < step; i++) {\n for (int j = 0; j < sizes[i]; j++) {\n if (strcmp(result[i][j], expected[i][j]) != 0) {\n return 0;\n }\n }\n }\n return 1;\n}", + "test": "int main() {\n\n // First assert with strings\n\n char *S1[] = {\"a\", \"b\", \"c\", \"d\", \"e\", \"f\", \"g\", \"h\", \"i\", \"j\", \"k\", \"l\", \"m\", \"n\"};\n\n int length1 = sizeof(S1) / sizeof(S1[0]);\n\n int step1 = 3;\n\n char ***split1 = list_split_str(S1, length1, step1);\n\n char *expected1[][5] = {{\"a\", \"d\", \"g\", \"j\", \"m\"}, {\"b\", \"e\", \"h\", \"k\", \"n\"}, {\"c\", \"f\", \"i\", \"l\", NULL}};\n\n int sizes1[] = {5,5,4};\n\n // Prepare expected split\n\n char **exp1[3];\n\n exp1[0] = expected1[0];\n\n exp1[1] = expected1[1];\n\n exp1[2] = expected1[2];\n\n assert(func0(split1, exp1, step1, sizes1));\n\n\n\n // Second assert with integers\n\n int S2[] = {1,2,3,4,5,6,7,8,9,10,11,12,13,14};\n\n int length2 = sizeof(S2) / sizeof(S2[0]);\n\n int step2 = 3;\n\n int **split2 = list_split_int(S2, length2, step2);\n\n int expected2[][5] = {{1,4,7,10,13}, {2,5,8,11,14}, {3,6,9,12}};\n\n int sizes2[] = {5,5,4};\n\n // Prepare expected split\n\n int *exp2[3];\n\n exp2[0] = expected2[0];\n\n exp2[1] = expected2[1];\n\n exp2[2] = expected2[2];\n\n assert(compare_split_int(split2, exp2, step2, sizes2));\n\n\n\n // Third assert with strings\n\n char *S3[] = {\"python\",\"java\",\"C\",\"C++\",\"DBMS\",\"SQL\"};\n\n int length3 = sizeof(S3) / sizeof(S3[0]);\n\n int step3 = 2;\n\n char ***split3 = list_split_str(S3, length3, step3);\n\n char *expected3[][3] = {{\"python\", \"C\", \"DBMS\"}, {\"java\", \"C++\", \"SQL\"}};\n\n int sizes3[] = {3,3};\n\n // Prepare expected split\n\n char **exp3[2];\n\n exp3[0] = expected3[0];\n\n exp3[1] = expected3[1];\n\n assert(func0(split3, exp3, step3, sizes3));\n\n\n\n // Free allocated memory\n\n for(int i = 0; i < step1; i++) {\n\n free(split1[i]);\n\n }\n\n free(split1);\n\n\n\n for(int i = 0; i < step2; i++) {\n\n free(split2[i]);\n\n }\n\n free(split2);\n\n\n\n for(int i = 0; i < step3; i++) {\n\n free(split3[i]);\n\n }\n\n free(split3);\n\n\n\n printf(\"All asserts passed successfully.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x28,%rsp\nmov %rdi,0x8(%rsp)\nmov %rsi,0x10(%rsp)\ntest %edx,%edx\njle 1a00 \nlea -0x1(%rdx),%eax\nmov %rcx,%r12\nxor %ebp,%ebp\nmov %rax,0x18(%rsp)\nmov (%r12,%rbp,4),%eax\ntest %eax,%eax\njle 19f0 \nmov 0x10(%rsp),%rcx\nmov 0x8(%rsp),%rdx\nlea -0x1(%rax),%ebx\nxor %r15d,%r15d\nmov (%rcx,%rbp,8),%r14\nmov (%rdx,%rbp,8),%r13\njmp 19cc \nlea 0x1(%r15),%rax\ncmp %r15,%rbx\nje 19f0 \nmov %rax,%r15\nmov (%r14,%r15,8),%rsi\nmov 0x0(%r13,%r15,8),%rdi\ncallq 10e0 \ntest %eax,%eax\nje 19c0 \nadd $0x28,%rsp\nxor %eax,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nlea 0x1(%rbp),%rax\ncmp %rbp,0x18(%rsp)\nje 1a00 \nmov %rax,%rbp\njmp 199d \nadd $0x28,%rsp\nmov $0x1,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_48], rdi\ntest edx, edx\njle short loc_1ABB\nmovsxd rax, edx\nmov r15, rsi\nmov r13, rcx\nxor ebp, ebp\nmov [rsp+48h+var_40], rax\nloc_1A5A:\nmovsxd rax, dword ptr [r13+rbp*4+0]\ntest eax, eax\njle short loc_1AB0\nmov r12, [r15+rbp*8]\nmov rcx, [rsp+48h+var_48]\nlea rbx, [r12+rax*8]\nmov r14, [rcx+rbp*8]\njmp short loc_1A85\nloc_1A78:\nadd r12, 8\nadd r14, 8\ncmp rbx, r12\njz short loc_1AB0\nloc_1A85:\nmov rsi, [r12]; s2\nmov rdi, [r14]; s1\ncall _strcmp\ntest eax, eax\njz short loc_1A78\nadd rsp, 18h\nxor eax, eax\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1AB0:\nadd rbp, 1\ncmp [rsp+48h+var_40], rbp\njnz short loc_1A5A\nloc_1ABB:\nadd rsp, 18h\nmov eax, 1\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3, __int64 a4)\n{\n __int64 v5; // rbp\n __int64 v6; // rax\n const char **v7; // r12\n const char **v8; // rbx\n const char **v9; // r14\n __int64 v11; // [rsp+8h] [rbp-40h]\n\n if ( a3 <= 0 )\n return 1LL;\n v5 = 0LL;\n v11 = a3;\n while ( 1 )\n {\n v6 = *(int *)(a4 + 4 * v5);\n if ( (int)v6 > 0 )\n break;\nLABEL_8:\n if ( v11 == ++v5 )\n return 1LL;\n }\n v7 = *(const char ***)(a2 + 8 * v5);\n v8 = &v7[v6];\n v9 = *(const char ***)(a1 + 8 * v5);\n while ( !strcmp(*v9, *v7) )\n {\n ++v7;\n ++v9;\n if ( v8 == v7 )\n goto LABEL_8;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1A30:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_48], rdi\ntest edx, edx\njle short loc_1ABB\nmovsxd rax, edx\nmov r15, rsi\nmov r13, rcx\nxor ebp, ebp\nmov [rsp+48h+var_40], rax\nloc_1A5A:\nmovsxd rax, dword ptr [r13+rbp*4+0]\ntest eax, eax\njle short loc_1AB0\nmov r12, [r15+rbp*8]\nmov rcx, [rsp+48h+var_48]\nlea rbx, [r12+rax*8]\nmov r14, [rcx+rbp*8]\njmp short loc_1A85\nloc_1A78:\nadd r12, 8\nadd r14, 8\ncmp rbx, r12\njz short loc_1AB0\nloc_1A85:\nmov rsi, [r12]; s2\nmov rdi, [r14]; s1\ncall _strcmp\ntest eax, eax\njz short loc_1A78\nadd rsp, 18h\nxor eax, eax\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1AB0:\nadd rbp, 1\ncmp [rsp+48h+var_40], rbp\njnz short loc_1A5A\nloc_1ABB:\nadd rsp, 18h\nmov eax, 1\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1A30(__int64 a1, __int64 a2, int a3, __int64 a4)\n{\n __int64 v5; // rbp\n __int64 v6; // rax\n const char **v7; // r12\n const char **v8; // rbx\n const char **v9; // r14\n __int64 v11; // [rsp+8h] [rbp-40h]\n\n if ( a3 <= 0 )\n return 1LL;\n v5 = 0LL;\n v11 = a3;\n while ( 1 )\n {\n v6 = *(int *)(a4 + 4 * v5);\n if ( (int)v6 > 0 )\n break;\nLABEL_8:\n if ( v11 == ++v5 )\n return 1LL;\n }\n v7 = *(const char ***)(a2 + 8 * v5);\n v8 = &v7[v6];\n v9 = *(const char ***)(a1 + 8 * v5);\n while ( !strcmp(*v9, *v7) )\n {\n ++v7;\n ++v9;\n if ( v8 == v7 )\n goto LABEL_8;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1A30(long long a1, long long a2, int a3, long long a4) {\n long long v5;\n long long v6;\n const char **v7;\n const char **v8;\n const char **v9;\n long long v11;\n if (a3 <= 0) return 1LL;\n v5 = 0LL;\n v11 = a3;\n while (1) {\n v6 = *(int *)(a4 + 4 * v5);\n if ((int)v6 > 0) break;\n LABEL_8:\n if (v11 == ++v5) return 1LL;\n }\n v7 = *(const char ***)(a2 + 8 * v5);\n v8 = &v7[v6];\n v9 = *(const char ***)(a1 + 8 * v5);\n while (!strcmp(*v9, *v7)) {\n ++v7;\n ++v9;\n if (v8 == v7) goto LABEL_8;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3, long long a4) {\n long long v5;\n long long v6;\n const char **v7;\n const char **v8;\n const char **v9;\n long long v11;\n if (a3 <= 0) return 1LL;\n v5 = 0LL;\n v11 = a3;\n while (1) {\n v6 = *(int *)(a4 + 4 * v5);\n if ((int)v6 > 0) break;\n LABEL_8:\n if (v11 == ++v5) return 1LL;\n }\n v7 = *(const char ***)(a2 + 8 * v5);\n v8 = &v7[v6];\n v9 = *(const char ***)(a1 + 8 * v5);\n while (!strcmp(*v9, *v7)) {\n ++v7;\n ++v9;\n if (v8 == v7) goto LABEL_8;\n }\n return 0LL;\n}" + }, + { + "index": 265, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n// Function to split integer arrays\n\nint** list_split_int(int *S, int length, int step) {\n\n int **result = malloc(step * sizeof(int*));\n\n for(int i = 0; i < step; i++) {\n\n int count = 0;\n\n for(int j = i; j < length; j += step) {\n\n count++;\n\n }\n\n result[i] = malloc(count * sizeof(int));\n\n int index = 0;\n\n for(int j = i; j < length; j += step) {\n\n result[i][index++] = S[j];\n\n }\n\n }\n\n return result;\n\n}\n\n\n\n// Function to split string arrays\n\nchar*** list_split_str(char **S, int length, int step) {\n\n char ***result = malloc(step * sizeof(char**));\n\n for(int i = 0; i < step; i++) {\n\n int count = 0;\n\n for(int j = i; j < length; j += step) {\n\n count++;\n\n }\n\n result[i] = malloc(count * sizeof(char*));\n\n int index = 0;\n\n for(int j = i; j < length; j += step) {\n\n result[i][index++] = S[j];\n\n }\n\n }\n\n return result;\n\n}\n\n\n\n// Function to compare integer split results\n\nint compare_split_int(int **result, int **expected, int step, int *sizes) {\n\n for(int i = 0; i < step; i++) {\n\n for(int j = 0; j < sizes[i]; j++) {\n\n if(result[i][j] != expected[i][j]) {\n\n return 0;\n\n }\n\n }\n\n }\n\n return 1;\n\n}\n\n\n\n// Function to compare string split results\n\n", + "func": "int func0(char ***result, char ***expected, int step, int *sizes) {\n for (int i = 0; i < step; i++) {\n for (int j = 0; j < sizes[i]; j++) {\n if (strcmp(result[i][j], expected[i][j]) != 0) {\n return 0;\n }\n }\n }\n return 1;\n}", + "test": "int main() {\n\n // First assert with strings\n\n char *S1[] = {\"a\", \"b\", \"c\", \"d\", \"e\", \"f\", \"g\", \"h\", \"i\", \"j\", \"k\", \"l\", \"m\", \"n\"};\n\n int length1 = sizeof(S1) / sizeof(S1[0]);\n\n int step1 = 3;\n\n char ***split1 = list_split_str(S1, length1, step1);\n\n char *expected1[][5] = {{\"a\", \"d\", \"g\", \"j\", \"m\"}, {\"b\", \"e\", \"h\", \"k\", \"n\"}, {\"c\", \"f\", \"i\", \"l\", NULL}};\n\n int sizes1[] = {5,5,4};\n\n // Prepare expected split\n\n char **exp1[3];\n\n exp1[0] = expected1[0];\n\n exp1[1] = expected1[1];\n\n exp1[2] = expected1[2];\n\n assert(func0(split1, exp1, step1, sizes1));\n\n\n\n // Second assert with integers\n\n int S2[] = {1,2,3,4,5,6,7,8,9,10,11,12,13,14};\n\n int length2 = sizeof(S2) / sizeof(S2[0]);\n\n int step2 = 3;\n\n int **split2 = list_split_int(S2, length2, step2);\n\n int expected2[][5] = {{1,4,7,10,13}, {2,5,8,11,14}, {3,6,9,12}};\n\n int sizes2[] = {5,5,4};\n\n // Prepare expected split\n\n int *exp2[3];\n\n exp2[0] = expected2[0];\n\n exp2[1] = expected2[1];\n\n exp2[2] = expected2[2];\n\n assert(compare_split_int(split2, exp2, step2, sizes2));\n\n\n\n // Third assert with strings\n\n char *S3[] = {\"python\",\"java\",\"C\",\"C++\",\"DBMS\",\"SQL\"};\n\n int length3 = sizeof(S3) / sizeof(S3[0]);\n\n int step3 = 2;\n\n char ***split3 = list_split_str(S3, length3, step3);\n\n char *expected3[][3] = {{\"python\", \"C\", \"DBMS\"}, {\"java\", \"C++\", \"SQL\"}};\n\n int sizes3[] = {3,3};\n\n // Prepare expected split\n\n char **exp3[2];\n\n exp3[0] = expected3[0];\n\n exp3[1] = expected3[1];\n\n assert(func0(split3, exp3, step3, sizes3));\n\n\n\n // Free allocated memory\n\n for(int i = 0; i < step1; i++) {\n\n free(split1[i]);\n\n }\n\n free(split1);\n\n\n\n for(int i = 0; i < step2; i++) {\n\n free(split2[i]);\n\n }\n\n free(split2);\n\n\n\n for(int i = 0; i < step3; i++) {\n\n free(split3[i]);\n\n }\n\n free(split3);\n\n\n\n printf(\"All asserts passed successfully.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x28,%rsp\nmov %rdi,0x8(%rsp)\nmov %rsi,0x10(%rsp)\ntest %edx,%edx\njle 1b30 \nlea -0x1(%rdx),%eax\nmov %rcx,%r12\nxor %ebp,%ebp\nmov %rax,0x18(%rsp)\nmov (%r12,%rbp,4),%eax\ntest %eax,%eax\njle 1b20 \nmov 0x10(%rsp),%rcx\nmov 0x8(%rsp),%rdx\nlea -0x1(%rax),%ebx\nxor %r15d,%r15d\nmov (%rcx,%rbp,8),%r14\nmov (%rdx,%rbp,8),%r13\njmp 1afc \nlea 0x1(%r15),%rax\ncmp %r15,%rbx\nje 1b20 \nmov %rax,%r15\nmov (%r14,%r15,8),%rsi\nmov 0x0(%r13,%r15,8),%rdi\ncallq 10f0 \ntest %eax,%eax\nje 1af0 \nadd $0x28,%rsp\nxor %eax,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nlea 0x1(%rbp),%rax\ncmp %rbp,0x18(%rsp)\nje 1b30 \nmov %rax,%rbp\njmp 1acd \nadd $0x28,%rsp\nmov $0x1,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_48], rdi\ntest edx, edx\njle short loc_1BBB\nmovsxd rax, edx\nmov r15, rsi\nmov r13, rcx\nxor ebp, ebp\nmov [rsp+48h+var_40], rax\nloc_1B5A:\nmovsxd rax, dword ptr [r13+rbp*4+0]\ntest eax, eax\njle short loc_1BB0\nmov r12, [r15+rbp*8]\nmov rcx, [rsp+48h+var_48]\nlea rbx, [r12+rax*8]\nmov r14, [rcx+rbp*8]\njmp short loc_1B85\nloc_1B78:\nadd r12, 8\nadd r14, 8\ncmp rbx, r12\njz short loc_1BB0\nloc_1B85:\nmov rsi, [r12]; s2\nmov rdi, [r14]; s1\ncall _strcmp\ntest eax, eax\njz short loc_1B78\nadd rsp, 18h\nxor eax, eax\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1BB0:\nadd rbp, 1\ncmp [rsp+48h+var_40], rbp\njnz short loc_1B5A\nloc_1BBB:\nadd rsp, 18h\nmov eax, 1\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3, __int64 a4)\n{\n __int64 v5; // rbp\n __int64 v6; // rax\n const char **v7; // r12\n const char **v8; // rbx\n const char **v9; // r14\n __int64 v11; // [rsp+8h] [rbp-40h]\n\n if ( a3 <= 0 )\n return 1LL;\n v5 = 0LL;\n v11 = a3;\n while ( 1 )\n {\n v6 = *(int *)(a4 + 4 * v5);\n if ( (int)v6 > 0 )\n break;\nLABEL_8:\n if ( v11 == ++v5 )\n return 1LL;\n }\n v7 = *(const char ***)(a2 + 8 * v5);\n v8 = &v7[v6];\n v9 = *(const char ***)(a1 + 8 * v5);\n while ( !strcmp(*v9, *v7) )\n {\n ++v7;\n ++v9;\n if ( v8 == v7 )\n goto LABEL_8;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1B30:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_48], rdi\ntest edx, edx\njle short loc_1BBB\nmovsxd rax, edx\nmov r15, rsi\nmov r13, rcx\nxor ebp, ebp\nmov [rsp+48h+var_40], rax\nloc_1B5A:\nmovsxd rax, dword ptr [r13+rbp*4+0]\ntest eax, eax\njle short loc_1BB0\nmov r12, [r15+rbp*8]\nmov rcx, [rsp+48h+var_48]\nlea rbx, [r12+rax*8]\nmov r14, [rcx+rbp*8]\njmp short loc_1B85\nloc_1B78:\nadd r12, 8\nadd r14, 8\ncmp rbx, r12\njz short loc_1BB0\nloc_1B85:\nmov rsi, [r12]; s2\nmov rdi, [r14]; s1\ncall _strcmp\ntest eax, eax\njz short loc_1B78\nadd rsp, 18h\nxor eax, eax\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1BB0:\nadd rbp, 1\ncmp [rsp+48h+var_40], rbp\njnz short loc_1B5A\nloc_1BBB:\nadd rsp, 18h\nmov eax, 1\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1B30(__int64 a1, __int64 a2, int a3, __int64 a4)\n{\n __int64 v5; // rbp\n __int64 v6; // rax\n const char **v7; // r12\n const char **v8; // rbx\n const char **v9; // r14\n __int64 v11; // [rsp+8h] [rbp-40h]\n\n if ( a3 <= 0 )\n return 1LL;\n v5 = 0LL;\n v11 = a3;\n while ( 1 )\n {\n v6 = *(int *)(a4 + 4 * v5);\n if ( (int)v6 > 0 )\n break;\nLABEL_8:\n if ( v11 == ++v5 )\n return 1LL;\n }\n v7 = *(const char ***)(a2 + 8 * v5);\n v8 = &v7[v6];\n v9 = *(const char ***)(a1 + 8 * v5);\n while ( !strcmp(*v9, *v7) )\n {\n ++v7;\n ++v9;\n if ( v8 == v7 )\n goto LABEL_8;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1B30(long long a1, long long a2, int a3, long long a4) {\n long long v5;\n long long v6;\n const char **v7;\n const char **v8;\n const char **v9;\n long long v11;\n if (a3 <= 0) return 1LL;\n v5 = 0LL;\n v11 = a3;\n while (1) {\n v6 = *(int *)(a4 + 4 * v5);\n if ((int)v6 > 0) break;\n LABEL_8:\n if (v11 == ++v5) return 1LL;\n }\n v7 = *(const char ***)(a2 + 8 * v5);\n v8 = &v7[v6];\n v9 = *(const char ***)(a1 + 8 * v5);\n while (!strcmp(*v9, *v7)) {\n ++v7;\n ++v9;\n if (v8 == v7) goto LABEL_8;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3, long long a4) {\n long long v5;\n long long v6;\n const char **v7;\n const char **v8;\n const char **v9;\n long long v11;\n if (a3 <= 0) return 1LL;\n v5 = 0LL;\n v11 = a3;\n while (1) {\n v6 = *(int *)(a4 + 4 * v5);\n if ((int)v6 > 0) break;\n LABEL_8:\n if (v11 == ++v5) return 1LL;\n }\n v7 = *(const char ***)(a2 + 8 * v5);\n v8 = &v7[v6];\n v9 = *(const char ***)(a1 + 8 * v5);\n while (!strcmp(*v9, *v7)) {\n ++v7;\n ++v9;\n if (v8 == v7) goto LABEL_8;\n }\n return 0LL;\n}" + }, + { + "index": 266, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int l) {\n int LSA = 4 * (l * l);\n return LSA;\n}", + "test": "int main() {\n\n assert(func0(5) == 100);\n\n assert(func0(9) == 324);\n\n assert(func0(10) == 400);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov -0x14(%rbp),%eax\nimul %eax,%eax\nshl $0x2,%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov eax, [rbp+var_14]\nimul eax, eax\nshl eax, 2\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n return (unsigned int)(4 * a1 * a1);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov eax, [rbp+var_14]\nimul eax, eax\nshl eax, 2\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n return (unsigned int)(4 * a1 * a1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) { return (unsigned int)(4 * a1 * a1); }", + "ida_pseudo_norm": "long long func0(int a1) { return (unsigned int)(4 * a1 * a1); }" + }, + { + "index": 267, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) { return (int)(n * (4 * n * n - 1) / 3); }", + "test": "int main() {\n\n assert(func0(2) == 10);\n\n assert(func0(3) == 35);\n\n assert(func0(4) == 84);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nimul %eax,%eax\nshl $0x2,%eax\nsub $0x1,%eax\nimul -0x4(%rbp),%eax\nmovslq %eax,%rdx\nimul $0x55555556,%rdx,%rdx\nshr $0x20,%rdx\nsar $0x1f,%eax\nmov %edx,%ecx\nsub %eax,%ecx\nmov %ecx,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov eax, [rbp+var_4]\nimul eax, eax\nshl eax, 2\nsub eax, 1\nimul eax, [rbp+var_4]\nmovsxd rdx, eax\nimul rdx, 55555556h\nshr rdx, 20h\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n return (unsigned int)(a1 * (4 * a1 * a1 - 1) / 3);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov eax, [rbp+var_4]\nimul eax, eax\nshl eax, 2\nsub eax, 1\nimul eax, [rbp+var_4]\nmovsxd rdx, eax\nimul rdx, 55555556h\nshr rdx, 20h\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n return (unsigned int)(a1 * (4 * a1 * a1 - 1) / 3);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n return (unsigned int)(a1 * (4 * a1 * a1 - 1) / 3);\n}", + "ida_pseudo_norm": "long long func0(int a1) { return (unsigned int)(a1 * (4 * a1 * a1 - 1) / 3); }" + }, + { + "index": 268, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) { return (6 * n * (n - 1) + 1); }", + "test": "int main() {\n\n assert(func0(3) == 37);\n\n assert(func0(4) == 73);\n\n assert(func0(5) == 121);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nsub $0x1,%eax\nimul -0x4(%rbp),%eax\nmov %eax,%edx\nmov %edx,%eax\nadd %eax,%eax\nadd %edx,%eax\nadd %eax,%eax\nadd $0x1,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov eax, [rbp+var_4]\nsub eax, 1\nimul eax, [rbp+var_4]\nmov edx, eax\nmov eax, edx\nadd eax, eax\nadd eax, edx\nadd eax, eax\nadd eax, 1\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n return (unsigned int)(6 * a1 * (a1 - 1) + 1);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov eax, [rbp+var_4]\nsub eax, 1\nimul eax, [rbp+var_4]\nmov edx, eax\nmov eax, edx\nadd eax, eax\nadd eax, edx\nadd eax, eax\nadd eax, 1\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n return (unsigned int)(6 * a1 * (a1 - 1) + 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) { return (unsigned int)(6 * a1 * (a1 - 1) + 1); }", + "ida_pseudo_norm": "long long func0(int a1) { return (unsigned int)(6 * a1 * (a1 - 1) + 1); }" + }, + { + "index": 269, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(char k) { return (int)k; }", + "test": "int main() {\n\n assert(func0('A') == 65);\n\n assert(func0('R') == 82);\n\n assert(func0('S') == 83);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,%eax\nmov %al,-0x4(%rbp)\nmovsbl -0x4(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov eax, edi\nmov [rbp+var_4], al\nmovsx eax, [rbp+var_4]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(char a1)\n{\n return (unsigned int)a1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov eax, edi\nmov [rbp+var_4], al\nmovsx eax, [rbp+var_4]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(char a1)\n{\n return (unsigned int)a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(char a1) { return (unsigned int)a1; }", + "ida_pseudo_norm": "long long func0(char a1) { return (unsigned int)a1; }" + }, + { + "index": 270, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int sum = 0;\n for (int i = 0; i < n; i += 2) {\n if (arr[i] % 2 == 0) {\n sum += arr[i];\n }\n }\n return sum;\n}", + "test": "int main() {\n\n int arr1[] = {5, 6, 12, 1, 18, 8};\n\n int arr2[] = {3, 20, 17, 9, 2, 10, 18, 13, 6, 18};\n\n int arr3[] = {5, 6, 12, 1};\n\n\n\n assert(func0(arr1, 6) == 30);\n\n assert(func0(arr2, 10) == 26);\n\n assert(func0(arr3, 4) == 12);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11c2 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nand $0x1,%eax\ntest %eax,%eax\njne 11be \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nadd %eax,-0x8(%rbp)\naddl $0x2,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1188 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11C2\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njnz short loc_11BE\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nloc_11BE:\nadd [rbp+var_4], 2\nloc_11C2:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; i += 2 )\n {\n if ( (*(_DWORD *)(4LL * i + a1) & 1) == 0 )\n v3 += *(_DWORD *)(4LL * i + a1);\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11C2\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njnz short loc_11BE\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nloc_11BE:\nadd [rbp+var_4], 2\nloc_11C2:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; i += 2 )\n {\n if ( (*(_DWORD *)(4LL * i + a1) & 1) == 0 )\n v3 += *(_DWORD *)(4LL * i + a1);\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; i += 2) {\n if ((*(uint32_t *)(4LL * i + a1) & 1) == 0)\n v3 += *(uint32_t *)(4LL * i + a1);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; i += 2) {\n if ((*(uint32_t *)(4LL * i + a1) & 1) == 0)\n v3 += *(uint32_t *)(4LL * i + a1);\n }\n return v3;\n}" + }, + { + "index": 270, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int sum = 0;\n for (int i = 0; i < n; i += 2) {\n if (arr[i] % 2 == 0) {\n sum += arr[i];\n }\n }\n return sum;\n}", + "test": "int main() {\n\n int arr1[] = {5, 6, 12, 1, 18, 8};\n\n int arr2[] = {3, 20, 17, 9, 2, 10, 18, 13, 6, 18};\n\n int arr3[] = {5, 6, 12, 1};\n\n\n\n assert(func0(arr1, 6) == 30);\n\n assert(func0(arr2, 10) == 26);\n\n assert(func0(arr3, 4) == 12);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 119c \nmov %rdi,%rax\nsub $0x1,%esi\nshr %esi\nmov %esi,%esi\nlea 0x8(%rdi,%rsi,8),%rdi\nmov $0x0,%edx\nmov (%rax),%ecx\nlea (%rdx,%rcx,1),%esi\ntest $0x1,%cl\ncmove %esi,%edx\nadd $0x8,%rax\ncmp %rdi,%rax\njne 1185 \nmov %edx,%eax\nretq\nmov $0x0,%edx\njmp 1199 \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_119C\nmov rax, rdi\nsub esi, 1\nshr esi, 1\nmov esi, esi\nlea rdi, [rdi+rsi*8+8]\nmov edx, 0\nloc_1185:\nmov ecx, [rax]\nlea esi, [rdx+rcx]\ntest cl, 1\ncmovz edx, esi\nadd rax, 8\ncmp rax, rdi\njnz short loc_1185\nloc_1199:\nmov eax, edx\nretn\nloc_119C:\nmov edx, 0\njmp short loc_1199", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n __int64 v3; // rdi\n unsigned int v4; // edx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = (__int64)&a1[2 * ((unsigned int)(a2 - 1) >> 1) + 2];\n v4 = 0;\n do\n {\n if ( (*v2 & 1) == 0 )\n v4 += *v2;\n v2 += 2;\n }\n while ( v2 != (_DWORD *)v3 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_119C\nmov rax, rdi\nsub esi, 1\nshr esi, 1\nmov esi, esi\nlea rdi, [rdi+rsi*8+8]\nmov edx, 0\nloc_1185:\nmov ecx, [rax]\nlea esi, [rdx+rcx]\ntest cl, 1\ncmovz edx, esi\nadd rax, 8\ncmp rax, rdi\njnz short loc_1185\nloc_1199:\nmov eax, edx\nretn\nloc_119C:\nmov edx, 0\njmp short loc_1199", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n __int64 v3; // rdi\n unsigned int v4; // edx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = (__int64)&a1[2 * ((unsigned int)(a2 - 1) >> 1) + 2];\n v4 = 0;\n do\n {\n if ( (*v2 & 1) == 0 )\n v4 += *v2;\n v2 += 2;\n }\n while ( v2 != (_DWORD *)v3 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2) {\n uint32_t *v2;\n long long v3;\n unsigned int v4;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = (long long)&a1[2 * ((unsigned int)(a2 - 1) >> 1) + 2];\n v4 = 0;\n do {\n if ((*v2 & 1) == 0) v4 += *v2;\n v2 += 2;\n } while (v2 != (uint32_t *)v3);\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n long long v3;\n unsigned int v4;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = (long long)&a1[2 * ((unsigned int)(a2 - 1) >> 1) + 2];\n v4 = 0;\n do {\n if ((*v2 & 1) == 0) v4 += *v2;\n v2 += 2;\n } while (v2 != (uint32_t *)v3);\n }\n return v4;\n}" + }, + { + "index": 271, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "long func0(int n) {\n long sum = 0;\n for (int i = 1; i <= n; i++) {\n int j = 2 * i;\n sum += j * j * j * j * j;\n }\n return sum;\n}", + "test": "int main() {\n\n assert(func0(2) == 1056);\n\n assert(func0(3) == 8832);\n\n assert(func0(1) == 32);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmovq $0x0,-0x8(%rbp)\nmovl $0x1,-0x10(%rbp)\njmp 1189 \nmov -0x10(%rbp),%eax\nadd %eax,%eax\nmov %eax,-0xc(%rbp)\nmov -0xc(%rbp),%eax\nimul %eax,%eax\nimul -0xc(%rbp),%eax\nimul -0xc(%rbp),%eax\nimul -0xc(%rbp),%eax\ncltq\nadd %rax,-0x8(%rbp)\naddl $0x1,-0x10(%rbp)\nmov -0x10(%rbp),%eax\ncmp -0x14(%rbp),%eax\njle 1165 \nmov -0x8(%rbp),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_8], 0\nmov [rbp+var_10], 1\njmp short loc_1189\nloc_1165:\nmov eax, [rbp+var_10]\nadd eax, eax\nmov [rbp+var_C], eax\nmov eax, [rbp+var_C]\nimul eax, eax\nimul eax, [rbp+var_C]\nimul eax, [rbp+var_C]\nimul eax, [rbp+var_C]\ncdqe\nadd [rbp+var_8], rax\nadd [rbp+var_10], 1\nloc_1189:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_14]\njle short loc_1165\nmov rax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int i; // [rsp+4h] [rbp-10h]\n __int64 v3; // [rsp+Ch] [rbp-8h]\n\n v3 = 0LL;\n for ( i = 1; i <= a1; ++i )\n v3 += 2 * i * 2 * i * 2 * i * 2 * i * 2 * i;\n return v3;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_8], 0\nmov [rbp+var_10], 1\njmp short loc_1189\nloc_1165:\nmov eax, [rbp+var_10]\nadd eax, eax\nmov [rbp+var_C], eax\nmov eax, [rbp+var_C]\nimul eax, eax\nimul eax, [rbp+var_C]\nimul eax, [rbp+var_C]\nimul eax, [rbp+var_C]\ncdqe\nadd [rbp+var_8], rax\nadd [rbp+var_10], 1\nloc_1189:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_14]\njle short loc_1165\nmov rax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int i; // [rsp+4h] [rbp-10h]\n __int64 v3; // [rsp+Ch] [rbp-8h]\n\n v3 = 0LL;\n for ( i = 1; i <= a1; ++i )\n v3 += 2 * i * 2 * i * 2 * i * 2 * i * 2 * i;\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int i;\n long long v3;\n v3 = 0LL;\n for (i = 1; i <= a1; ++i) v3 += 2 * i * 2 * i * 2 * i * 2 * i * 2 * i;\n return v3;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int i;\n long long v3;\n v3 = 0LL;\n for (i = 1; i <= a1; ++i) v3 += 2 * i * 2 * i * 2 * i * 2 * i * 2 * i;\n return v3;\n}" + }, + { + "index": 271, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "long func0(int n) {\n long sum = 0;\n for (int i = 1; i <= n; i++) {\n int j = 2 * i;\n sum += j * j * j * j * j;\n }\n return sum;\n}", + "test": "int main() {\n\n assert(func0(2) == 1056);\n\n assert(func0(3) == 8832);\n\n assert(func0(1) == 32);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\njle 117a \nlea 0x2(%rdi,%rdi,1),%esi\nmov $0x2,%edx\nmov $0x0,%ecx\nmov %edx,%eax\nimul %edx,%eax\nimul %eax,%eax\nimul %edx,%eax\ncltq\nadd %rax,%rcx\nadd $0x2,%edx\ncmp %esi,%edx\njne 115f \nmov %rcx,%rax\nretq\nmov $0x0,%ecx\njmp 1176 \n", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njle short loc_117A\nlea esi, [rdi+rdi+2]\nmov edx, 2\nmov ecx, 0\nloc_115F:\nmov eax, edx\nimul eax, edx\nimul eax, eax\nimul eax, edx\ncdqe\nadd rcx, rax\nadd edx, 2\ncmp edx, esi\njnz short loc_115F\nloc_1176:\nmov rax, rcx\nretn\nloc_117A:\nmov ecx, 0\njmp short loc_1176", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // edx\n __int64 v2; // rcx\n\n if ( a1 <= 0 )\n return 0LL;\n v1 = 2;\n v2 = 0LL;\n do\n {\n v2 += v1 * v1 * v1 * v1 * v1;\n v1 += 2;\n }\n while ( v1 != 2 * a1 + 2 );\n return v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ntest edi, edi\njle short loc_117A\nlea esi, [rdi+rdi+2]\nmov edx, 2\nmov ecx, 0\nloc_115F:\nmov eax, edx\nimul eax, edx\nimul eax, eax\nimul eax, edx\ncdqe\nadd rcx, rax\nadd edx, 2\ncmp edx, esi\njnz short loc_115F\nloc_1176:\nmov rax, rcx\nretn\nloc_117A:\nmov ecx, 0\njmp short loc_1176", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v1; // edx\n __int64 v2; // rcx\n\n if ( a1 <= 0 )\n return 0LL;\n v1 = 2;\n v2 = 0LL;\n do\n {\n v2 += v1 * v1 * v1 * v1 * v1;\n v1 += 2;\n }\n while ( v1 != 2 * a1 + 2 );\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v1;\n long long v2;\n if (a1 <= 0) return 0LL;\n v1 = 2;\n v2 = 0LL;\n do {\n v2 += v1 * v1 * v1 * v1 * v1;\n v1 += 2;\n } while (v1 != 2 * a1 + 2);\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n long long v2;\n if (a1 <= 0) return 0LL;\n v1 = 2;\n v2 = 0LL;\n do {\n v2 += v1 * v1 * v1 * v1 * v1;\n v1 += 2;\n } while (v1 != 2 * a1 + 2);\n return v2;\n}" + }, + { + "index": 272, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int* func0(int test_list[][3], int length, int* output) {\n for (int i = 0; i < length; i++) {\n output[i] = test_list[i][2];\n }\n return output;\n}", + "test": "int main() {\n\n int list1[][3] = {{1, 'R', 21}, {2, 'V', 20}, {3, 'K', 19}};\n\n int list2[][3] = {{1, 'S', 36}, {2, 'A', 25}, {3, 'S', 45}};\n\n int list3[][3] = {{1, 'S', 14}, {2, 'V', 36}, {3, 'D', 56}};\n\n \n\n int length1 = sizeof(list1) / sizeof(list1[0]);\n\n int length2 = sizeof(list2) / sizeof(list2[0]);\n\n int length3 = sizeof(list3) / sizeof(list3[0]);\n\n \n\n int output1[3], output2[3], output3[3];\n\n\n\n func0(list1, length1, output1);\n\n func0(list2, length2, output2);\n\n func0(list3, length3, output3);\n\n \n\n assert(output1[0] == 21 && output1[1] == 20 && output1[2] == 19);\n\n assert(output2[0] == 36 && output2[1] == 25 && output2[2] == 45);\n\n assert(output3[0] == 14 && output3[1] == 36 && output3[2] == 56);\n\n \n\n printf(\"All tests passed!\\n\");\n\n \n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11e0 \nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0x4(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x28(%rbp),%rdx\nadd %rcx,%rdx\nmov 0x8(%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11a5 \nmov -0x28(%rbp),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_4], 0\njmp short loc_11E0\nloc_11A5:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax+8]\nmov [rdx], eax\nadd [rbp+var_4], 1\nloc_11E0:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11A5\nmov rax, [rbp+var_28]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3)\n{\n int i; // [rsp+24h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n *(_DWORD *)(4LL * i + a3) = *(_DWORD *)(12LL * i + a1 + 8);\n return a3;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_4], 0\njmp short loc_11E0\nloc_11A5:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax+8]\nmov [rdx], eax\nadd [rbp+var_4], 1\nloc_11E0:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11A5\nmov rax, [rbp+var_28]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2, __int64 a3)\n{\n int i; // [rsp+24h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n *(_DWORD *)(4LL * i + a3) = *(_DWORD *)(12LL * i + a1 + 8);\n return a3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2, long long a3) {\n int i;\n for (i = 0; i < a2; ++i)\n *(uint32_t *)(4LL * i + a3) = *(uint32_t *)(12LL * i + a1 + 8);\n return a3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3) {\n int i;\n for (i = 0; i < a2; ++i)\n *(uint32_t *)(4LL * i + a3) = *(uint32_t *)(12LL * i + a1 + 8);\n return a3;\n}" + }, + { + "index": 272, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int* func0(int test_list[][3], int length, int* output) {\n for (int i = 0; i < length; i++) {\n output[i] = test_list[i][2];\n }\n return output;\n}", + "test": "int main() {\n\n int list1[][3] = {{1, 'R', 21}, {2, 'V', 20}, {3, 'K', 19}};\n\n int list2[][3] = {{1, 'S', 36}, {2, 'A', 25}, {3, 'S', 45}};\n\n int list3[][3] = {{1, 'S', 14}, {2, 'V', 36}, {3, 'D', 56}};\n\n \n\n int length1 = sizeof(list1) / sizeof(list1[0]);\n\n int length2 = sizeof(list2) / sizeof(list2[0]);\n\n int length3 = sizeof(list3) / sizeof(list3[0]);\n\n \n\n int output1[3], output2[3], output3[3];\n\n\n\n func0(list1, length1, output1);\n\n func0(list2, length2, output2);\n\n func0(list3, length3, output3);\n\n \n\n assert(output1[0] == 21 && output1[1] == 20 && output1[2] == 19);\n\n assert(output2[0] == 36 && output2[1] == 25 && output2[2] == 45);\n\n assert(output3[0] == 14 && output3[1] == 36 && output3[2] == 56);\n\n \n\n printf(\"All tests passed!\\n\");\n\n \n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdx,%rax\ntest %esi,%esi\njle 11b4 \nadd $0x8,%rdi\nmov %rdx,%rcx\nlea -0x1(%rsi),%edx\nlea 0x4(%rax,%rdx,4),%r8\nmov (%rdi),%esi\nmov %esi,(%rcx)\nadd $0xc,%rdi\nadd $0x4,%rcx\ncmp %r8,%rcx\njne 11a3 \nretq\n", + "ida_asm": "func0:\nendbr64\nmov rax, rdx\ntest esi, esi\njle short locret_11B3\nadd rdi, 8\nmov rcx, rdx\nmovsxd rsi, esi\nlea r8, [rdx+rsi*4]\nloc_11A2:\nmov esi, [rdi]\nmov [rcx], esi\nadd rdi, 0Ch\nadd rcx, 4\ncmp rcx, r8\njnz short loc_11A2\nlocret_11B3:\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, _DWORD *a3)\n{\n _DWORD *result; // rax\n _DWORD *v4; // rdi\n _DWORD *v5; // rcx\n\n result = a3;\n if ( a2 > 0 )\n {\n v4 = (_DWORD *)(a1 + 8);\n v5 = a3;\n do\n {\n *v5 = *v4;\n v4 += 3;\n ++v5;\n }\n while ( v5 != &a3[a2] );\n }\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\nmov rax, rdx\ntest esi, esi\njle short locret_11B3\nadd rdi, 8\nmov rcx, rdx\nmovsxd rsi, esi\nlea r8, [rdx+rsi*4]\nloc_11A2:\nmov esi, [rdi]\nmov [rcx], esi\nadd rdi, 0Ch\nadd rcx, 4\ncmp rcx, r8\njnz short loc_11A2\nlocret_11B3:\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1189(__int64 a1, int a2, _DWORD *a3)\n{\n _DWORD *result; // rax\n _DWORD *v4; // rdi\n _DWORD *v5; // rcx\n\n result = a3;\n if ( a2 > 0 )\n {\n v4 = (_DWORD *)(a1 + 8);\n v5 = a3;\n do\n {\n *v5 = *v4;\n v4 += 3;\n ++v5;\n }\n while ( v5 != &a3[a2] );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1189(long long a1, int a2, uint32_t *a3) {\n uint32_t *result;\n uint32_t *v4;\n uint32_t *v5;\n result = a3;\n if (a2 > 0) {\n v4 = (uint32_t *)(a1 + 8);\n v5 = a3;\n do {\n *v5 = *v4;\n v4 += 3;\n ++v5;\n } while (v5 != &a3[a2]);\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, uint32_t *a3) {\n uint32_t *result;\n uint32_t *v4;\n uint32_t *v5;\n result = a3;\n if (a2 > 0) {\n v4 = (uint32_t *)(a1 + 8);\n v5 = a3;\n do {\n *v5 = *v4;\n v4 += 3;\n ++v5;\n } while (v5 != &a3[a2]);\n }\n return result;\n}" + }, + { + "index": 273, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int* func0(int* test_tup1, int* test_tup2, int n, int* res) {\n for (int i = 0; i < n; i++) {\n res[i] = test_tup1[i] - test_tup2[i];\n }\n return res;\n}", + "test": "int main() {\n\n int result1[3], result2[3], result3[3];\n\n int tup1a[] = {10, 4, 5}, tup2a[] = {2, 5, 18};\n\n int tup1b[] = {11, 2, 3}, tup2b[] = {24, 45, 16};\n\n int tup1c[] = {7, 18, 9}, tup2c[] = {10, 11, 12};\n\n \n\n int expected1[] = {8, -1, -13}, expected2[] = {-13, -43, -13}, expected3[] = {-3, 7, -3};\n\n\n\n func0(tup1a, tup2a, 3, result1);\n\n func0(tup1b, tup2b, 3, result2);\n\n func0(tup1c, tup2c, 3, result3);\n\n\n\n for (int i = 0; i < 3; i++) {\n\n assert(result1[i] == expected1[i]);\n\n assert(result2[i] == expected2[i]);\n\n assert(result3[i] == expected3[i]);\n\n }\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %edx,-0x24(%rbp)\nmov %rcx,-0x30(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11f3 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%ecx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rsi\nmov -0x30(%rbp),%rax\nadd %rsi,%rax\nsub %edx,%ecx\nmov %ecx,%edx\nmov %edx,(%rax)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x24(%rbp),%eax\njl 11a9 \nmov -0x30(%rbp),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_30], rcx\nmov [rbp+var_4], 0\njmp short loc_11F2\nloc_11A9:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov ecx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rsi, ds:0[rdx*4]\nmov rdx, [rbp+var_30]\nadd rdx, rsi\nsub ecx, eax\nmov [rdx], ecx\nadd [rbp+var_4], 1\nloc_11F2:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_24]\njl short loc_11A9\nmov rax, [rbp+var_30]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3, __int64 a4)\n{\n int i; // [rsp+2Ch] [rbp-4h]\n\n for ( i = 0; i < a3; ++i )\n *(_DWORD *)(4LL * i + a4) = *(_DWORD *)(4LL * i + a1) - *(_DWORD *)(4LL * i + a2);\n return a4;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_30], rcx\nmov [rbp+var_4], 0\njmp short loc_11F2\nloc_11A9:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov ecx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rsi, ds:0[rdx*4]\nmov rdx, [rbp+var_30]\nadd rdx, rsi\nsub ecx, eax\nmov [rdx], ecx\nadd [rbp+var_4], 1\nloc_11F2:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_24]\njl short loc_11A9\nmov rax, [rbp+var_30]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, __int64 a2, int a3, __int64 a4)\n{\n int i; // [rsp+2Ch] [rbp-4h]\n\n for ( i = 0; i < a3; ++i )\n *(_DWORD *)(4LL * i + a4) = *(_DWORD *)(4LL * i + a1) - *(_DWORD *)(4LL * i + a2);\n return a4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, long long a2, int a3, long long a4) {\n int i;\n for (i = 0; i < a3; ++i)\n *(uint32_t *)(4LL * i + a4) =\n *(uint32_t *)(4LL * i + a1) - *(uint32_t *)(4LL * i + a2);\n return a4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3, long long a4) {\n int i;\n for (i = 0; i < a3; ++i)\n *(uint32_t *)(4LL * i + a4) =\n *(uint32_t *)(4LL * i + a1) - *(uint32_t *)(4LL * i + a2);\n return a4;\n}" + }, + { + "index": 273, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int* func0(int* test_tup1, int* test_tup2, int n, int* res) {\n for (int i = 0; i < n; i++) {\n res[i] = test_tup1[i] - test_tup2[i];\n }\n return res;\n}", + "test": "int main() {\n\n int result1[3], result2[3], result3[3];\n\n int tup1a[] = {10, 4, 5}, tup2a[] = {2, 5, 18};\n\n int tup1b[] = {11, 2, 3}, tup2b[] = {24, 45, 16};\n\n int tup1c[] = {7, 18, 9}, tup2c[] = {10, 11, 12};\n\n \n\n int expected1[] = {8, -1, -13}, expected2[] = {-13, -43, -13}, expected3[] = {-3, 7, -3};\n\n\n\n func0(tup1a, tup2a, 3, result1);\n\n func0(tup1b, tup2b, 3, result2);\n\n func0(tup1c, tup2c, 3, result3);\n\n\n\n for (int i = 0; i < 3; i++) {\n\n assert(result1[i] == expected1[i]);\n\n assert(result2[i] == expected2[i]);\n\n assert(result3[i] == expected3[i]);\n\n }\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rcx,%rax\ntest %edx,%edx\njle 11b4 \nlea -0x1(%rdx),%ecx\nmov $0x0,%edx\nmov (%rdi,%rdx,4),%r8d\nsub (%rsi,%rdx,4),%r8d\nmov %r8d,(%rax,%rdx,4)\nmov %rdx,%r8\nadd $0x1,%rdx\ncmp %rcx,%r8\njne 119c \nretq\n", + "ida_asm": "func0:\nendbr64\nmov rax, rcx\ntest edx, edx\njle short locret_11B9\nmovsxd rdx, edx\nlea r9, ds:0[rdx*4]\nmov edx, 0\nloc_11A4:\nmov r8d, [rdi+rdx]\nsub r8d, [rsi+rdx]\nmov [rax+rdx], r8d\nadd rdx, 4\ncmp rdx, r9\njnz short loc_11A4\nlocret_11B9:\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3, __int64 a4)\n{\n __int64 result; // rax\n __int64 v5; // r9\n __int64 v6; // rdx\n\n result = a4;\n if ( a3 > 0 )\n {\n v5 = 4LL * a3;\n v6 = 0LL;\n do\n {\n *(_DWORD *)(a4 + v6) = *(_DWORD *)(a1 + v6) - *(_DWORD *)(a2 + v6);\n v6 += 4LL;\n }\n while ( v6 != v5 );\n }\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\nmov rax, rcx\ntest edx, edx\njle short locret_11B9\nmovsxd rdx, edx\nlea r9, ds:0[rdx*4]\nmov edx, 0\nloc_11A4:\nmov r8d, [rdi+rdx]\nsub r8d, [rsi+rdx]\nmov [rax+rdx], r8d\nadd rdx, 4\ncmp rdx, r9\njnz short loc_11A4\nlocret_11B9:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, __int64 a2, int a3, __int64 a4)\n{\n __int64 result; // rax\n __int64 v5; // r9\n __int64 v6; // rdx\n\n result = a4;\n if ( a3 > 0 )\n {\n v5 = 4LL * a3;\n v6 = 0LL;\n do\n {\n *(_DWORD *)(a4 + v6) = *(_DWORD *)(a1 + v6) - *(_DWORD *)(a2 + v6);\n v6 += 4LL;\n }\n while ( v6 != v5 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, long long a2, int a3, long long a4) {\n long long result;\n long long v5;\n long long v6;\n result = a4;\n if (a3 > 0) {\n v5 = 4LL * a3;\n v6 = 0LL;\n do {\n *(uint32_t *)(a4 + v6) = *(uint32_t *)(a1 + v6) - *(uint32_t *)(a2 + v6);\n v6 += 4LL;\n } while (v6 != v5);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3, long long a4) {\n long long result;\n long long v5;\n long long v6;\n result = a4;\n if (a3 > 0) {\n v5 = 4LL * a3;\n v6 = 0LL;\n do {\n *(uint32_t *)(a4 + v6) = *(uint32_t *)(a1 + v6) - *(uint32_t *)(a2 + v6);\n v6 += 4LL;\n } while (v6 != v5);\n }\n return result;\n}" + }, + { + "index": 274, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) { return (1 << (n - 1)); }", + "test": "int main() {\n\n assert(func0(4) == 8);\n\n assert(func0(6) == 32);\n\n assert(func0(2) == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nsub $0x1,%eax\nmov $0x1,%edx\nmov %eax,%ecx\nshl %cl,%edx\nmov %edx,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov eax, [rbp+var_4]\nsub eax, 1\nmov edx, 1\nmov ecx, eax\nshl edx, cl\nmov eax, edx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(char a1)\n{\n return (unsigned int)(1 << (a1 - 1));\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov eax, [rbp+var_4]\nsub eax, 1\nmov edx, 1\nmov ecx, eax\nshl edx, cl\nmov eax, edx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(char a1)\n{\n return (unsigned int)(1 << (a1 - 1));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(char a1) { return (unsigned int)(1 << (a1 - 1)); }", + "ida_pseudo_norm": "long long func0(char a1) { return (unsigned int)(1 << (a1 - 1)); }" + }, + { + "index": 275, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int a[], int n, int m) {\n int i;\n for (i = 0; i < n; i++) {\n a[i] = (a[i] / m + (a[i] % m != 0));\n }\n int result = -1, maxx = -1;\n for (i = n - 1; i >= 0; i--) {\n if (maxx < a[i]) {\n maxx = a[i];\n result = i;\n }\n }\n return result + 1;\n}", + "test": "int main() {\n\n int array1[3] = {2, 5, 4};\n\n int array2[2] = {4, 3};\n\n int array3[4] = {1, 2, 3, 4};\n\n \n\n assert(func0(array1, 3, 2) == 2);\n\n assert(func0(array2, 2, 2) == 2);\n\n assert(func0(array3, 4, 1) == 4);\n\n \n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 11e0 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncltd\nidivl -0x20(%rbp)\nmov %eax,%esi\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncltd\nidivl -0x20(%rbp)\nmov %edx,%eax\ntest %eax,%eax\nsetne %al\nmovzbl %al,%edx\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nadd %esi,%edx\nmov %edx,(%rax)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1184 \nmovl $0xffffffff,-0x8(%rbp)\nmovl $0xffffffff,-0x4(%rbp)\nmov -0x1c(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0xc(%rbp)\njmp 123f \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x4(%rbp)\njge 123b \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x4(%rbp)\nmov -0xc(%rbp),%eax\nmov %eax,-0x8(%rbp)\nsubl $0x1,-0xc(%rbp)\ncmpl $0x0,-0xc(%rbp)\njns 1201 \nmov -0x8(%rbp),%eax\nadd $0x1,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_C], 0\njmp short loc_11E0\nloc_1184:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncdq\nidiv [rbp+var_20]\nmov esi, eax\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncdq\nidiv [rbp+var_20]\nmov eax, edx\ntest eax, eax\nsetnz al\nmovzx edx, al\nmov eax, [rbp+var_C]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nadd edx, esi\nmov [rax], edx\nadd [rbp+var_C], 1\nloc_11E0:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_1184\nmov [rbp+var_8], 0FFFFFFFFh\nmov [rbp+var_4], 0FFFFFFFFh\nmov eax, [rbp+var_1C]\nsub eax, 1\nmov [rbp+var_C], eax\njmp short loc_123F\nloc_1201:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_4], eax\njge short loc_123B\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_C]\nmov [rbp+var_8], eax\nloc_123B:\nsub [rbp+var_C], 1\nloc_123F:\ncmp [rbp+var_C], 0\njns short loc_1201\nmov eax, [rbp+var_8]\nadd eax, 1\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n int i; // [rsp+14h] [rbp-Ch]\n int j; // [rsp+14h] [rbp-Ch]\n int v6; // [rsp+18h] [rbp-8h]\n int v7; // [rsp+1Ch] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n *(_DWORD *)(4LL * i + a1) = *(_DWORD *)(4LL * i + a1) / a3 + (*(_DWORD *)(4LL * i + a1) % a3 != 0);\n v6 = -1;\n v7 = -1;\n for ( j = a2 - 1; j >= 0; --j )\n {\n if ( v7 < *(_DWORD *)(4LL * j + a1) )\n {\n v7 = *(_DWORD *)(4LL * j + a1);\n v6 = j;\n }\n }\n return (unsigned int)(v6 + 1);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_C], 0\njmp short loc_11E0\nloc_1184:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncdq\nidiv [rbp+var_20]\nmov esi, eax\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncdq\nidiv [rbp+var_20]\nmov eax, edx\ntest eax, eax\nsetnz al\nmovzx edx, al\nmov eax, [rbp+var_C]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nadd edx, esi\nmov [rax], edx\nadd [rbp+var_C], 1\nloc_11E0:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_1184\nmov [rbp+var_8], 0FFFFFFFFh\nmov [rbp+var_4], 0FFFFFFFFh\nmov eax, [rbp+var_1C]\nsub eax, 1\nmov [rbp+var_C], eax\njmp short loc_123F\nloc_1201:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_4], eax\njge short loc_123B\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_C]\nmov [rbp+var_8], eax\nloc_123B:\nsub [rbp+var_C], 1\nloc_123F:\ncmp [rbp+var_C], 0\njns short loc_1201\nmov eax, [rbp+var_8]\nadd eax, 1\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n int i; // [rsp+14h] [rbp-Ch]\n int j; // [rsp+14h] [rbp-Ch]\n int v6; // [rsp+18h] [rbp-8h]\n int v7; // [rsp+1Ch] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n *(_DWORD *)(4LL * i + a1) = *(_DWORD *)(4LL * i + a1) / a3 + (*(_DWORD *)(4LL * i + a1) % a3 != 0);\n v6 = -1;\n v7 = -1;\n for ( j = a2 - 1; j >= 0; --j )\n {\n if ( v7 < *(_DWORD *)(4LL * j + a1) )\n {\n v7 = *(_DWORD *)(4LL * j + a1);\n v6 = j;\n }\n }\n return (unsigned int)(v6 + 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n int i;\n int j;\n int v6;\n int v7;\n for (i = 0; i < a2; ++i)\n *(uint32_t *)(4LL * i + a1) = *(uint32_t *)(4LL * i + a1) / a3 +\n (*(uint32_t *)(4LL * i + a1) % a3 != 0);\n v6 = -1;\n v7 = -1;\n for (j = a2 - 1; j >= 0; --j) {\n if (v7 < *(uint32_t *)(4LL * j + a1)) {\n v7 = *(uint32_t *)(4LL * j + a1);\n v6 = j;\n }\n }\n return (unsigned int)(v6 + 1);\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n int i;\n int j;\n int v6;\n int v7;\n for (i = 0; i < a2; ++i)\n *(uint32_t *)(4LL * i + a1) = *(uint32_t *)(4LL * i + a1) / a3 +\n (*(uint32_t *)(4LL * i + a1) % a3 != 0);\n v6 = -1;\n v7 = -1;\n for (j = a2 - 1; j >= 0; --j) {\n if (v7 < *(uint32_t *)(4LL * j + a1)) {\n v7 = *(uint32_t *)(4LL * j + a1);\n v6 = j;\n }\n }\n return (unsigned int)(v6 + 1);\n}" + }, + { + "index": 275, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int a[], int n, int m) {\n int i;\n for (i = 0; i < n; i++) {\n a[i] = (a[i] / m + (a[i] % m != 0));\n }\n int result = -1, maxx = -1;\n for (i = n - 1; i >= 0; i--) {\n if (maxx < a[i]) {\n maxx = a[i];\n result = i;\n }\n }\n return result + 1;\n}", + "test": "int main() {\n\n int array1[3] = {2, 5, 4};\n\n int array2[2] = {4, 3};\n\n int array3[4] = {1, 2, 3, 4};\n\n \n\n assert(func0(array1, 3, 2) == 2);\n\n assert(func0(array2, 2, 2) == 2);\n\n assert(func0(array3, 4, 1) == 4);\n\n \n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %edx,%r8d\ntest %esi,%esi\njle 11c1 \nmov %rdi,%rcx\nlea -0x1(%rsi),%eax\nlea 0x4(%rdi,%rax,4),%r9\nmov (%rcx),%eax\ncltd\nidiv %r8d\ntest %edx,%edx\nsetne %dl\nmovzbl %dl,%edx\nadd %edx,%eax\nmov %eax,(%rcx)\nadd $0x4,%rcx\ncmp %r9,%rcx\njne 117f \nsub $0x1,%esi\nmovslq %esi,%rdx\nmov $0xffffffff,%esi\nmov $0xffffffff,%eax\njmp 11b4 \nsub $0x1,%rdx\ntest %edx,%edx\njs 11c6 \nmov (%rdi,%rdx,4),%ecx\ncmp %esi,%ecx\njle 11ac \nmov %ecx,%esi\nmov %edx,%eax\njmp 11ac \nmov $0xffffffff,%eax\nadd $0x1,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov r8, rdi\nmov edi, edx\ntest esi, esi\njle short loc_11BE\nmov rcx, r8\nmovsxd rax, esi\nlea r9, [r8+rax*4]\nloc_1180:\nmov eax, [rcx]\ncdq\nidiv edi\ncmp edx, 1\nsbb eax, 0FFFFFFFFh\nmov [rcx], eax\nadd rcx, 4\ncmp rcx, r9\njnz short loc_1180\nsub esi, 1\nmovsxd rdx, esi\nmov ecx, 0FFFFFFFFh\nmov eax, 0FFFFFFFFh\nloc_11A6:\nmov esi, [r8+rdx*4]\ncmp esi, ecx\ncmovg eax, edx\ncmovg ecx, esi\nsub rdx, 1\ntest edx, edx\njns short loc_11A6\nloc_11BA:\nadd eax, 1\nretn\nloc_11BE:\nmov eax, 0FFFFFFFFh\njmp short loc_11BA", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2, int a3)\n{\n _DWORD *v3; // rcx\n __int64 v4; // rdx\n int v5; // ecx\n int v6; // eax\n\n if ( a2 <= 0 )\n {\n v6 = -1;\n }\n else\n {\n v3 = a1;\n do\n {\n *v3 = *v3 / a3 - ((*v3 % a3 == 0) - 1);\n ++v3;\n }\n while ( v3 != &a1[a2] );\n v4 = a2 - 1;\n v5 = -1;\n v6 = -1;\n do\n {\n if ( a1[v4] > v5 )\n {\n v6 = v4;\n v5 = a1[v4];\n }\n --v4;\n }\n while ( (int)v4 >= 0 );\n }\n return (unsigned int)(v6 + 1);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov r8, rdi\nmov edi, edx\ntest esi, esi\njle short loc_11BE\nmov rcx, r8\nmovsxd rax, esi\nlea r9, [r8+rax*4]\nloc_1180:\nmov eax, [rcx]\ncdq\nidiv edi\ncmp edx, 1\nsbb eax, 0FFFFFFFFh\nmov [rcx], eax\nadd rcx, 4\ncmp rcx, r9\njnz short loc_1180\nsub esi, 1\nmovsxd rdx, esi\nmov ecx, 0FFFFFFFFh\nmov eax, 0FFFFFFFFh\nloc_11A6:\nmov esi, [r8+rdx*4]\ncmp esi, ecx\ncmovg eax, edx\ncmovg ecx, esi\nsub rdx, 1\ntest edx, edx\njns short loc_11A6\nloc_11BA:\nadd eax, 1\nretn\nloc_11BE:\nmov eax, 0FFFFFFFFh\njmp short loc_11BA", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2, int a3)\n{\n _DWORD *v3; // rcx\n __int64 v4; // rdx\n int v5; // ecx\n int v6; // eax\n\n if ( a2 <= 0 )\n {\n v6 = -1;\n }\n else\n {\n v3 = a1;\n do\n {\n *v3 = *v3 / a3 - ((*v3 % a3 == 0) - 1);\n ++v3;\n }\n while ( v3 != &a1[a2] );\n v4 = a2 - 1;\n v5 = -1;\n v6 = -1;\n do\n {\n if ( a1[v4] > v5 )\n {\n v6 = v4;\n v5 = a1[v4];\n }\n --v4;\n }\n while ( (int)v4 >= 0 );\n }\n return (unsigned int)(v6 + 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2, int a3) {\n uint32_t *v3;\n long long v4;\n int v5;\n int v6;\n if (a2 <= 0) {\n v6 = -1;\n } else {\n v3 = a1;\n do {\n *v3 = *v3 / a3 - ((*v3 % a3 == 0) - 1);\n ++v3;\n } while (v3 != &a1[a2]);\n v4 = a2 - 1;\n v5 = -1;\n v6 = -1;\n do {\n if (a1[v4] > v5) {\n v6 = v4;\n v5 = a1[v4];\n }\n --v4;\n } while ((int)v4 >= 0);\n }\n return (unsigned int)(v6 + 1);\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2, int a3) {\n uint32_t *v3;\n long long v4;\n int v5;\n int v6;\n if (a2 <= 0) {\n v6 = -1;\n } else {\n v3 = a1;\n do {\n *v3 = *v3 / a3 - ((*v3 % a3 == 0) - 1);\n ++v3;\n } while (v3 != &a1[a2]);\n v4 = a2 - 1;\n v5 = -1;\n v6 = -1;\n do {\n if (a1[v4] > v5) {\n v6 = v4;\n v5 = a1[v4];\n }\n --v4;\n } while ((int)v4 >= 0);\n }\n return (unsigned int)(v6 + 1);\n}" + }, + { + "index": 275, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int a[], int n, int m) {\n int i;\n for (i = 0; i < n; i++) {\n a[i] = (a[i] / m + (a[i] % m != 0));\n }\n int result = -1, maxx = -1;\n for (i = n - 1; i >= 0; i--) {\n if (maxx < a[i]) {\n maxx = a[i];\n result = i;\n }\n }\n return result + 1;\n}", + "test": "int main() {\n\n int array1[3] = {2, 5, 4};\n\n int array2[2] = {4, 3};\n\n int array3[4] = {1, 2, 3, 4};\n\n \n\n assert(func0(array1, 3, 2) == 2);\n\n assert(func0(array2, 2, 2) == 2);\n\n assert(func0(array3, 4, 1) == 4);\n\n \n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov %edx,%r9d\nlea -0x1(%rsi),%r8d\ntest %esi,%esi\njle 1300 \nmov %r8d,%eax\nmov %rdi,%rcx\nlea 0x4(%rdi,%rax,4),%rsi\nnopw 0x0(%rax,%rax,1)\nmov (%rcx),%eax\ncltd\nidiv %r9d\ntest %edx,%edx\nsetne %dl\nadd $0x4,%rcx\nmovzbl %dl,%edx\nadd %edx,%eax\nmov %eax,-0x4(%rcx)\ncmp %rcx,%rsi\njne 12b0 \nmovslq %r8d,%rdx\nmov $0xffffffff,%esi\nmov $0xffffffff,%eax\nnopl 0x0(%rax)\nmov (%rdi,%rdx,4),%ecx\ncmp %esi,%ecx\njle 12eb \nmov %ecx,%esi\nmov %edx,%eax\nsub $0x1,%rdx\ntest %edx,%edx\njns 12e0 \nadd $0x1,%eax\nretq\nnopw 0x0(%rax,%rax,1)\ntest %r8d,%r8d\njns 12cc \nxor %eax,%eax\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmov r8, rdi\nmov edi, edx\ntest esi, esi\njle short loc_12F0\nmovsxd rax, esi\nmov rcx, r8\nlea r9, [r8+rax*4]\nnop word ptr [rax+rax+00000000h]\nloc_12A0:\nmov eax, [rcx]\ncdq\nidiv edi\ncmp edx, 1\nsbb eax, 0FFFFFFFFh\nadd rcx, 4\nmov [rcx-4], eax\ncmp rcx, r9\njnz short loc_12A0\nsub esi, 1\nmov ecx, 0FFFFFFFFh\nmov eax, 0FFFFFFFFh\nmovsxd rdx, esi\nnop word ptr [rax+rax+00000000h]\nloc_12D0:\nmov esi, [r8+rdx*4]\ncmp esi, ecx\ncmovg eax, edx\ncmovg ecx, esi\nsub rdx, 1\ntest edx, edx\njns short loc_12D0\nadd eax, 1\nretn\nloc_12F0:\nxor eax, eax\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2, int a3)\n{\n _DWORD *v3; // rcx\n int v4; // eax\n int v5; // ecx\n int v6; // eax\n __int64 v7; // rdx\n\n if ( a2 <= 0 )\n return 0LL;\n v3 = a1;\n do\n {\n v4 = *v3 / a3 - ((*v3 % a3 == 0) - 1);\n *v3++ = v4;\n }\n while ( v3 != &a1[a2] );\n v5 = -1;\n v6 = -1;\n v7 = a2 - 1;\n do\n {\n if ( a1[v7] > v5 )\n {\n v6 = v7;\n v5 = a1[v7];\n }\n --v7;\n }\n while ( (int)v7 >= 0 );\n return (unsigned int)(v6 + 1);\n}", + "ida_strip_asm": "sub_1280:\nendbr64\nmov r8, rdi\nmov edi, edx\ntest esi, esi\njle short loc_12F0\nmovsxd rax, esi\nmov rcx, r8\nlea r9, [r8+rax*4]\nnop word ptr [rax+rax+00000000h]\nloc_12A0:\nmov eax, [rcx]\ncdq\nidiv edi\ncmp edx, 1\nsbb eax, 0FFFFFFFFh\nadd rcx, 4\nmov [rcx-4], eax\ncmp rcx, r9\njnz short loc_12A0\nsub esi, 1\nmov ecx, 0FFFFFFFFh\nmov eax, 0FFFFFFFFh\nmovsxd rdx, esi\nnop word ptr [rax+rax+00000000h]\nloc_12D0:\nmov esi, [r8+rdx*4]\ncmp esi, ecx\ncmovg eax, edx\ncmovg ecx, esi\nsub rdx, 1\ntest edx, edx\njns short loc_12D0\nadd eax, 1\nretn\nloc_12F0:\nxor eax, eax\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1280(_DWORD *a1, int a2, int a3)\n{\n _DWORD *v3; // rcx\n int v4; // eax\n int v5; // ecx\n int v6; // eax\n __int64 v7; // rdx\n\n if ( a2 <= 0 )\n return 0LL;\n v3 = a1;\n do\n {\n v4 = *v3 / a3 - ((*v3 % a3 == 0) - 1);\n *v3++ = v4;\n }\n while ( v3 != &a1[a2] );\n v5 = -1;\n v6 = -1;\n v7 = a2 - 1;\n do\n {\n if ( a1[v7] > v5 )\n {\n v6 = v7;\n v5 = a1[v7];\n }\n --v7;\n }\n while ( (int)v7 >= 0 );\n return (unsigned int)(v6 + 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1280(uint32_t *a1, int a2, int a3) {\n uint32_t *v3;\n int v4;\n int v5;\n int v6;\n long long v7;\n if (a2 <= 0) return 0LL;\n v3 = a1;\n do {\n v4 = *v3 / a3 - ((*v3 % a3 == 0) - 1);\n *v3++ = v4;\n } while (v3 != &a1[a2]);\n v5 = -1;\n v6 = -1;\n v7 = a2 - 1;\n do {\n if (a1[v7] > v5) {\n v6 = v7;\n v5 = a1[v7];\n }\n --v7;\n } while ((int)v7 >= 0);\n return (unsigned int)(v6 + 1);\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2, int a3) {\n uint32_t *v3;\n int v4;\n int v5;\n int v6;\n long long v7;\n if (a2 <= 0) return 0LL;\n v3 = a1;\n do {\n v4 = *v3 / a3 - ((*v3 % a3 == 0) - 1);\n *v3++ = v4;\n } while (v3 != &a1[a2]);\n v5 = -1;\n v6 = -1;\n v7 = a2 - 1;\n do {\n if (a1[v7] > v5) {\n v6 = v7;\n v5 = a1[v7];\n }\n --v7;\n } while ((int)v7 >= 0);\n return (unsigned int)(v6 + 1);\n}" + }, + { + "index": 275, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int a[], int n, int m) {\n int i;\n for (i = 0; i < n; i++) {\n a[i] = (a[i] / m + (a[i] % m != 0));\n }\n int result = -1, maxx = -1;\n for (i = n - 1; i >= 0; i--) {\n if (maxx < a[i]) {\n maxx = a[i];\n result = i;\n }\n }\n return result + 1;\n}", + "test": "int main() {\n\n int array1[3] = {2, 5, 4};\n\n int array2[2] = {4, 3};\n\n int array3[4] = {1, 2, 3, 4};\n\n \n\n assert(func0(array1, 3, 2) == 2);\n\n assert(func0(array2, 2, 2) == 2);\n\n assert(func0(array3, 4, 1) == 4);\n\n \n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nmov %edx,%r9d\nlea -0x1(%rsi),%r8d\ntest %esi,%esi\njle 12f0 \nmov %r8d,%eax\nmov %rdi,%rcx\nlea 0x4(%rdi,%rax,4),%rsi\nnopw 0x0(%rax,%rax,1)\nmov (%rcx),%eax\ncltd\nidiv %r9d\ntest %edx,%edx\nsetne %dl\nadd $0x4,%rcx\nmovzbl %dl,%edx\nadd %edx,%eax\nmov %eax,-0x4(%rcx)\ncmp %rsi,%rcx\njne 12a0 \nmovslq %r8d,%rdx\nmov $0xffffffff,%esi\nmov $0xffffffff,%eax\nnopl 0x0(%rax)\nmov (%rdi,%rdx,4),%ecx\ncmp %esi,%ecx\njle 12db \nmov %ecx,%esi\nmov %edx,%eax\nsub $0x1,%rdx\ntest %edx,%edx\njns 12d0 \nadd $0x1,%eax\nretq\nnopw 0x0(%rax,%rax,1)\ntest %r8d,%r8d\njns 12bc \nxor %eax,%eax\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmov r8, rdi\nmov edi, edx\ntest esi, esi\njle short loc_12F0\nmovsxd rax, esi\nmov rcx, r8\nlea r9, [r8+rax*4]\nnop word ptr [rax+rax+00000000h]\nloc_12A0:\nmov eax, [rcx]\ncdq\nidiv edi\ncmp edx, 1\nsbb eax, 0FFFFFFFFh\nadd rcx, 4\nmov [rcx-4], eax\ncmp rcx, r9\njnz short loc_12A0\nsub esi, 1\nmov ecx, 0FFFFFFFFh\nmov eax, 0FFFFFFFFh\nmovsxd rdx, esi\nnop word ptr [rax+rax+00000000h]\nloc_12D0:\nmov esi, [r8+rdx*4]\ncmp esi, ecx\ncmovg eax, edx\ncmovg ecx, esi\nsub rdx, 1\ntest edx, edx\njns short loc_12D0\nadd eax, 1\nretn\nloc_12F0:\nxor eax, eax\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2, int a3)\n{\n _DWORD *v3; // rcx\n int v4; // eax\n int v5; // ecx\n int v6; // eax\n __int64 v7; // rdx\n\n if ( a2 <= 0 )\n return 0LL;\n v3 = a1;\n do\n {\n v4 = *v3 / a3 - ((*v3 % a3 == 0) - 1);\n *v3++ = v4;\n }\n while ( v3 != &a1[a2] );\n v5 = -1;\n v6 = -1;\n v7 = a2 - 1;\n do\n {\n if ( a1[v7] > v5 )\n {\n v6 = v7;\n v5 = a1[v7];\n }\n --v7;\n }\n while ( (int)v7 >= 0 );\n return (unsigned int)(v6 + 1);\n}", + "ida_strip_asm": "sub_1280:\nendbr64\nmov r8, rdi\nmov edi, edx\ntest esi, esi\njle short loc_12F0\nmovsxd rax, esi\nmov rcx, r8\nlea r9, [r8+rax*4]\nnop word ptr [rax+rax+00000000h]\nloc_12A0:\nmov eax, [rcx]\ncdq\nidiv edi\ncmp edx, 1\nsbb eax, 0FFFFFFFFh\nadd rcx, 4\nmov [rcx-4], eax\ncmp rcx, r9\njnz short loc_12A0\nsub esi, 1\nmov ecx, 0FFFFFFFFh\nmov eax, 0FFFFFFFFh\nmovsxd rdx, esi\nnop word ptr [rax+rax+00000000h]\nloc_12D0:\nmov esi, [r8+rdx*4]\ncmp esi, ecx\ncmovg eax, edx\ncmovg ecx, esi\nsub rdx, 1\ntest edx, edx\njns short loc_12D0\nadd eax, 1\nretn\nloc_12F0:\nxor eax, eax\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1280(_DWORD *a1, int a2, int a3)\n{\n _DWORD *v3; // rcx\n int v4; // eax\n int v5; // ecx\n int v6; // eax\n __int64 v7; // rdx\n\n if ( a2 <= 0 )\n return 0LL;\n v3 = a1;\n do\n {\n v4 = *v3 / a3 - ((*v3 % a3 == 0) - 1);\n *v3++ = v4;\n }\n while ( v3 != &a1[a2] );\n v5 = -1;\n v6 = -1;\n v7 = a2 - 1;\n do\n {\n if ( a1[v7] > v5 )\n {\n v6 = v7;\n v5 = a1[v7];\n }\n --v7;\n }\n while ( (int)v7 >= 0 );\n return (unsigned int)(v6 + 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1280(uint32_t *a1, int a2, int a3) {\n uint32_t *v3;\n int v4;\n int v5;\n int v6;\n long long v7;\n if (a2 <= 0) return 0LL;\n v3 = a1;\n do {\n v4 = *v3 / a3 - ((*v3 % a3 == 0) - 1);\n *v3++ = v4;\n } while (v3 != &a1[a2]);\n v5 = -1;\n v6 = -1;\n v7 = a2 - 1;\n do {\n if (a1[v7] > v5) {\n v6 = v7;\n v5 = a1[v7];\n }\n --v7;\n } while ((int)v7 >= 0);\n return (unsigned int)(v6 + 1);\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2, int a3) {\n uint32_t *v3;\n int v4;\n int v5;\n int v6;\n long long v7;\n if (a2 <= 0) return 0LL;\n v3 = a1;\n do {\n v4 = *v3 / a3 - ((*v3 % a3 == 0) - 1);\n *v3++ = v4;\n } while (v3 != &a1[a2]);\n v5 = -1;\n v6 = -1;\n v7 = a2 - 1;\n do {\n if (a1[v7] > v5) {\n v6 = v7;\n v5 = a1[v7];\n }\n --v7;\n } while ((int)v7 >= 0);\n return (unsigned int)(v6 + 1);\n}" + }, + { + "index": 276, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(double r, double h) {\n double volume = 3.1415 * r * r * h;\n return volume;\n}", + "test": "int main() {\n\n assert(func0(10, 5) == 1570.7500000000002);\n\n assert(func0(4, 5) == 251.32000000000002);\n\n assert(func0(4, 10) == 502.64000000000004);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmovsd %xmm0,-0x18(%rbp)\nmovsd %xmm1,-0x20(%rbp)\nmovsd -0x18(%rbp),%xmm1\nmovsd 0xf58(%rip),%xmm0\nmulsd %xmm1,%xmm0\nmulsd -0x18(%rbp),%xmm0\nmovsd -0x20(%rbp),%xmm1\nmulsd %xmm1,%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmovsd -0x8(%rbp),%xmm0\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmovsd [rbp+var_18], xmm0\nmovsd [rbp+var_20], xmm1\nmovsd xmm1, [rbp+var_18]\nmovsd xmm0, cs:qword_20A0\nmulsd xmm0, xmm1\nmulsd xmm0, [rbp+var_18]\nmovsd xmm1, [rbp+var_20]\nmulsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "double __fastcall func0(double a1, double a2)\n{\n return 3.1415 * a1 * a1 * a2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmovsd [rbp+var_18], xmm0\nmovsd [rbp+var_20], xmm1\nmovsd xmm1, [rbp+var_18]\nmovsd xmm0, cs:qword_20A0\nmulsd xmm0, xmm1\nmulsd xmm0, [rbp+var_18]\nmovsd xmm1, [rbp+var_20]\nmulsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "double __fastcall sub_1149(double a1, double a2)\n{\n return 3.1415 * a1 * a1 * a2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1149(double a1, double a2) { return 3.1415 * a1 * a1 * a2; }", + "ida_pseudo_norm": "double func0(double a1, double a2) { return 3.1415 * a1 * a1 * a2; }" + }, + { + "index": 277, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char key[100];\n\n int value;\n\n} DictItem;\n\n\n\ntypedef struct {\n\n DictItem* items;\n\n int size;\n\n} Dict;\n\n\n\n", + "func": "Dict func0(Dict input, int n) {\n Dict result;\n result.items = (DictItem*)malloc(input.size * sizeof(DictItem));\n result.size = 0;\n for (int i = 0; i < input.size; i++) {\n if (input.items[i].value >= n) {\n result.items[result.size] = input.items[i];\n result.size++;\n }\n }\n return result;\n}", + "test": "int main() {\n\n Dict d1, d2, d3;\n\n d1.size = 4;\n\n d1.items = (DictItem*)malloc(d1.size * sizeof(DictItem));\n\n strcpy(d1.items[0].key, \"Cierra Vega\"); d1.items[0].value = 175;\n\n strcpy(d1.items[1].key, \"Alden Cantrell\"); d1.items[1].value = 180;\n\n strcpy(d1.items[2].key, \"Kierra Gentry\"); d1.items[2].value = 165;\n\n strcpy(d1.items[3].key, \"Pierre Cox\"); d1.items[3].value = 190;\n\n\n\n Dict result;\n\n\n\n result = func0(d1, 170);\n\n assert(result.size == 3 && strcmp(result.items[0].key, \"Cierra Vega\") == 0 && strcmp(result.items[1].key, \"Alden Cantrell\") == 0 && strcmp(result.items[2].key, \"Pierre Cox\") == 0);\n\n\n\n result = func0(d1, 180);\n\n assert(result.size == 2 && strcmp(result.items[0].key, \"Alden Cantrell\") == 0 && strcmp(result.items[1].key, \"Pierre Cox\") == 0);\n\n \n\n result = func0(d1, 190);\n\n assert(result.size == 1 && strcmp(result.items[0].key, \"Pierre Cox\") == 0);\n\n \n\n free(d1.items);\n\n free(result.items);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x48,%rsp\nmov %rdi,%rcx\nmov %rsi,%rax\nmov %rax,%rbx\nmov %rcx,-0x40(%rbp)\nmov %rbx,-0x38(%rbp)\nmov %edx,-0x44(%rbp)\nmov -0x38(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x20(%rbp)\nmovl $0x0,-0x18(%rbp)\nmovl $0x0,-0x24(%rbp)\njmpq 12e6 \nmov -0x40(%rbp),%rcx\nmov -0x24(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nadd %rcx,%rax\nmov 0x64(%rax),%eax\ncmp %eax,-0x44(%rbp)\njg 12e2 \nmov -0x40(%rbp),%rcx\nmov -0x24(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nlea (%rcx,%rax,1),%rdx\nmov -0x20(%rbp),%rsi\nmov -0x18(%rbp),%eax\nmovslq %eax,%rcx\nmov %rcx,%rax\nadd %rax,%rax\nadd %rcx,%rax\nshl $0x2,%rax\nadd %rcx,%rax\nshl $0x3,%rax\nadd %rsi,%rax\nmov (%rdx),%rcx\nmov 0x8(%rdx),%rbx\nmov %rcx,(%rax)\nmov %rbx,0x8(%rax)\nmov 0x10(%rdx),%rcx\nmov 0x18(%rdx),%rbx\nmov %rcx,0x10(%rax)\nmov %rbx,0x18(%rax)\nmov 0x20(%rdx),%rcx\nmov 0x28(%rdx),%rbx\nmov %rcx,0x20(%rax)\nmov %rbx,0x28(%rax)\nmov 0x30(%rdx),%rcx\nmov 0x38(%rdx),%rbx\nmov %rcx,0x30(%rax)\nmov %rbx,0x38(%rax)\nmov 0x40(%rdx),%rcx\nmov 0x48(%rdx),%rbx\nmov %rcx,0x40(%rax)\nmov %rbx,0x48(%rax)\nmov 0x50(%rdx),%rcx\nmov 0x58(%rdx),%rbx\nmov %rcx,0x50(%rax)\nmov %rbx,0x58(%rax)\nmov 0x60(%rdx),%rdx\nmov %rdx,0x60(%rax)\nmov -0x18(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x18(%rbp)\naddl $0x1,-0x24(%rbp)\nmov -0x38(%rbp),%eax\ncmp %eax,-0x24(%rbp)\njl 1203 \nmov -0x20(%rbp),%rax\nmov -0x18(%rbp),%rdx\nadd $0x48,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 48h\nmov rax, rdi\nmov rcx, rax\nmov rbx, rdx\nmov rbx, rsi\nmov [rbp+var_40], rcx\nmov [rbp+var_38], rbx\nmov [rbp+var_44], edx\nmov eax, dword ptr [rbp+var_38]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_20], rax\nmov dword ptr [rbp+var_18], 0\nmov [rbp+var_24], 0\njmp loc_12E9\nloc_1206:\nmov rcx, [rbp+var_40]\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nadd rax, rcx\nmov eax, [rax+64h]\ncmp [rbp+var_44], eax\njg loc_12E5\nmov rcx, [rbp+var_40]\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nlea rdx, [rcx+rax]\nmov rsi, [rbp+var_20]\nmov eax, dword ptr [rbp+var_18]\nmovsxd rcx, eax\nmov rax, rcx\nadd rax, rax\nadd rax, rcx\nshl rax, 2\nadd rax, rcx\nshl rax, 3\nadd rax, rsi\nmov rcx, [rdx]\nmov rbx, [rdx+8]\nmov [rax], rcx\nmov [rax+8], rbx\nmov rcx, [rdx+10h]\nmov rbx, [rdx+18h]\nmov [rax+10h], rcx\nmov [rax+18h], rbx\nmov rcx, [rdx+20h]\nmov rbx, [rdx+28h]\nmov [rax+20h], rcx\nmov [rax+28h], rbx\nmov rcx, [rdx+30h]\nmov rbx, [rdx+38h]\nmov [rax+30h], rcx\nmov [rax+38h], rbx\nmov rcx, [rdx+40h]\nmov rbx, [rdx+48h]\nmov [rax+40h], rcx\nmov [rax+48h], rbx\nmov rcx, [rdx+50h]\nmov rbx, [rdx+58h]\nmov [rax+50h], rcx\nmov [rax+58h], rbx\nmov rdx, [rdx+60h]\nmov [rax+60h], rdx\nmov eax, dword ptr [rbp+var_18]\nadd eax, 1\nmov dword ptr [rbp+var_18], eax\nloc_12E5:\nadd [rbp+var_24], 1\nloc_12E9:\nmov eax, dword ptr [rbp+var_38]\ncmp [rbp+var_24], eax\njl loc_1206\nmov rax, [rbp+var_20]\nmov rdx, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2, int a3)\n{\n _QWORD *v3; // rdx\n char *v4; // rax\n __int64 v5; // rbx\n __int64 v6; // rbx\n __int64 v7; // rbx\n __int64 v8; // rbx\n __int64 v9; // rbx\n __int64 v10; // rbx\n int i; // [rsp+2Ch] [rbp-24h]\n char *v14; // [rsp+30h] [rbp-20h]\n int v15; // [rsp+38h] [rbp-18h]\n\n v14 = (char *)malloc(104LL * a2);\n v15 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( a3 <= *(_DWORD *)(a1 + 104LL * i + 100) )\n {\n v3 = (_QWORD *)(a1 + 104LL * i);\n v4 = &v14[104 * v15];\n v5 = v3[1];\n *(_QWORD *)v4 = *v3;\n *((_QWORD *)v4 + 1) = v5;\n v6 = v3[3];\n *((_QWORD *)v4 + 2) = v3[2];\n *((_QWORD *)v4 + 3) = v6;\n v7 = v3[5];\n *((_QWORD *)v4 + 4) = v3[4];\n *((_QWORD *)v4 + 5) = v7;\n v8 = v3[7];\n *((_QWORD *)v4 + 6) = v3[6];\n *((_QWORD *)v4 + 7) = v8;\n v9 = v3[9];\n *((_QWORD *)v4 + 8) = v3[8];\n *((_QWORD *)v4 + 9) = v9;\n v10 = v3[11];\n *((_QWORD *)v4 + 10) = v3[10];\n *((_QWORD *)v4 + 11) = v10;\n *((_QWORD *)v4 + 12) = v3[12];\n ++v15;\n }\n }\n return v14;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 48h\nmov rax, rdi\nmov rcx, rax\nmov rbx, rdx\nmov rbx, rsi\nmov [rbp+var_40], rcx\nmov [rbp+var_38], rbx\nmov [rbp+var_44], edx\nmov eax, dword ptr [rbp+var_38]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_20], rax\nmov dword ptr [rbp+var_18], 0\nmov [rbp+var_24], 0\njmp loc_12E9\nloc_1206:\nmov rcx, [rbp+var_40]\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nadd rax, rcx\nmov eax, [rax+64h]\ncmp [rbp+var_44], eax\njg loc_12E5\nmov rcx, [rbp+var_40]\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nlea rdx, [rcx+rax]\nmov rsi, [rbp+var_20]\nmov eax, dword ptr [rbp+var_18]\nmovsxd rcx, eax\nmov rax, rcx\nadd rax, rax\nadd rax, rcx\nshl rax, 2\nadd rax, rcx\nshl rax, 3\nadd rax, rsi\nmov rcx, [rdx]\nmov rbx, [rdx+8]\nmov [rax], rcx\nmov [rax+8], rbx\nmov rcx, [rdx+10h]\nmov rbx, [rdx+18h]\nmov [rax+10h], rcx\nmov [rax+18h], rbx\nmov rcx, [rdx+20h]\nmov rbx, [rdx+28h]\nmov [rax+20h], rcx\nmov [rax+28h], rbx\nmov rcx, [rdx+30h]\nmov rbx, [rdx+38h]\nmov [rax+30h], rcx\nmov [rax+38h], rbx\nmov rcx, [rdx+40h]\nmov rbx, [rdx+48h]\nmov [rax+40h], rcx\nmov [rax+48h], rbx\nmov rcx, [rdx+50h]\nmov rbx, [rdx+58h]\nmov [rax+50h], rcx\nmov [rax+58h], rbx\nmov rdx, [rdx+60h]\nmov [rax+60h], rdx\nmov eax, dword ptr [rbp+var_18]\nadd eax, 1\nmov dword ptr [rbp+var_18], eax\nloc_12E5:\nadd [rbp+var_24], 1\nloc_12E9:\nmov eax, dword ptr [rbp+var_38]\ncmp [rbp+var_24], eax\njl loc_1206\nmov rax, [rbp+var_20]\nmov rdx, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11A9(__int64 a1, int a2, int a3)\n{\n _QWORD *v3; // rdx\n char *v4; // rax\n __int64 v5; // rbx\n __int64 v6; // rbx\n __int64 v7; // rbx\n __int64 v8; // rbx\n __int64 v9; // rbx\n __int64 v10; // rbx\n int i; // [rsp+2Ch] [rbp-24h]\n char *v14; // [rsp+30h] [rbp-20h]\n int v15; // [rsp+38h] [rbp-18h]\n\n v14 = (char *)malloc(104LL * a2);\n v15 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( a3 <= *(_DWORD *)(a1 + 104LL * i + 100) )\n {\n v3 = (_QWORD *)(a1 + 104LL * i);\n v4 = &v14[104 * v15];\n v5 = v3[1];\n *(_QWORD *)v4 = *v3;\n *((_QWORD *)v4 + 1) = v5;\n v6 = v3[3];\n *((_QWORD *)v4 + 2) = v3[2];\n *((_QWORD *)v4 + 3) = v6;\n v7 = v3[5];\n *((_QWORD *)v4 + 4) = v3[4];\n *((_QWORD *)v4 + 5) = v7;\n v8 = v3[7];\n *((_QWORD *)v4 + 6) = v3[6];\n *((_QWORD *)v4 + 7) = v8;\n v9 = v3[9];\n *((_QWORD *)v4 + 8) = v3[8];\n *((_QWORD *)v4 + 9) = v9;\n v10 = v3[11];\n *((_QWORD *)v4 + 10) = v3[10];\n *((_QWORD *)v4 + 11) = v10;\n *((_QWORD *)v4 + 12) = v3[12];\n ++v15;\n }\n }\n return v14;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11A9(long long a1, int a2, int a3) {\n uint64_t *v3;\n char *v4;\n long long v5;\n long long v6;\n long long v7;\n long long v8;\n long long v9;\n long long v10;\n int i;\n char *v14;\n int v15;\n v14 = (char *)malloc(104LL * a2);\n v15 = 0;\n for (i = 0; i < a2; ++i) {\n if (a3 <= *(uint32_t *)(a1 + 104LL * i + 100)) {\n v3 = (uint64_t *)(a1 + 104LL * i);\n v4 = &v14[104 * v15];\n v5 = v3[1];\n *(uint64_t *)v4 = *v3;\n *((uint64_t *)v4 + 1) = v5;\n v6 = v3[3];\n *((uint64_t *)v4 + 2) = v3[2];\n *((uint64_t *)v4 + 3) = v6;\n v7 = v3[5];\n *((uint64_t *)v4 + 4) = v3[4];\n *((uint64_t *)v4 + 5) = v7;\n v8 = v3[7];\n *((uint64_t *)v4 + 6) = v3[6];\n *((uint64_t *)v4 + 7) = v8;\n v9 = v3[9];\n *((uint64_t *)v4 + 8) = v3[8];\n *((uint64_t *)v4 + 9) = v9;\n v10 = v3[11];\n *((uint64_t *)v4 + 10) = v3[10];\n *((uint64_t *)v4 + 11) = v10;\n *((uint64_t *)v4 + 12) = v3[12];\n ++v15;\n }\n }\n return v14;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2, int a3) {\n uint64_t *v3;\n char *v4;\n long long v5;\n long long v6;\n long long v7;\n long long v8;\n long long v9;\n long long v10;\n int i;\n char *v14;\n int v15;\n v14 = (char *)malloc(104LL * a2);\n v15 = 0;\n for (i = 0; i < a2; ++i) {\n if (a3 <= *(uint32_t *)(a1 + 104LL * i + 100)) {\n v3 = (uint64_t *)(a1 + 104LL * i);\n v4 = &v14[104 * v15];\n v5 = v3[1];\n *(uint64_t *)v4 = *v3;\n *((uint64_t *)v4 + 1) = v5;\n v6 = v3[3];\n *((uint64_t *)v4 + 2) = v3[2];\n *((uint64_t *)v4 + 3) = v6;\n v7 = v3[5];\n *((uint64_t *)v4 + 4) = v3[4];\n *((uint64_t *)v4 + 5) = v7;\n v8 = v3[7];\n *((uint64_t *)v4 + 6) = v3[6];\n *((uint64_t *)v4 + 7) = v8;\n v9 = v3[9];\n *((uint64_t *)v4 + 8) = v3[8];\n *((uint64_t *)v4 + 9) = v9;\n v10 = v3[11];\n *((uint64_t *)v4 + 10) = v3[10];\n *((uint64_t *)v4 + 11) = v10;\n *((uint64_t *)v4 + 12) = v3[12];\n ++v15;\n }\n }\n return v14;\n}" + }, + { + "index": 277, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char key[100];\n\n int value;\n\n} DictItem;\n\n\n\ntypedef struct {\n\n DictItem* items;\n\n int size;\n\n} Dict;\n\n\n\n", + "func": "Dict func0(Dict input, int n) {\n Dict result;\n result.items = (DictItem*)malloc(input.size * sizeof(DictItem));\n result.size = 0;\n for (int i = 0; i < input.size; i++) {\n if (input.items[i].value >= n) {\n result.items[result.size] = input.items[i];\n result.size++;\n }\n }\n return result;\n}", + "test": "int main() {\n\n Dict d1, d2, d3;\n\n d1.size = 4;\n\n d1.items = (DictItem*)malloc(d1.size * sizeof(DictItem));\n\n strcpy(d1.items[0].key, \"Cierra Vega\"); d1.items[0].value = 175;\n\n strcpy(d1.items[1].key, \"Alden Cantrell\"); d1.items[1].value = 180;\n\n strcpy(d1.items[2].key, \"Kierra Gentry\"); d1.items[2].value = 165;\n\n strcpy(d1.items[3].key, \"Pierre Cox\"); d1.items[3].value = 190;\n\n\n\n Dict result;\n\n\n\n result = func0(d1, 170);\n\n assert(result.size == 3 && strcmp(result.items[0].key, \"Cierra Vega\") == 0 && strcmp(result.items[1].key, \"Alden Cantrell\") == 0 && strcmp(result.items[2].key, \"Pierre Cox\") == 0);\n\n\n\n result = func0(d1, 180);\n\n assert(result.size == 2 && strcmp(result.items[0].key, \"Alden Cantrell\") == 0 && strcmp(result.items[1].key, \"Pierre Cox\") == 0);\n\n \n\n result = func0(d1, 190);\n\n assert(result.size == 1 && strcmp(result.items[0].key, \"Pierre Cox\") == 0);\n\n \n\n free(d1.items);\n\n free(result.items);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%r12\nmov %rsi,%rbp\nmov %edx,%ebx\nmovslq %esi,%rax\nlea (%rax,%rax,2),%rdx\nlea (%rax,%rdx,4),%rdi\nshl $0x3,%rdi\ncallq 1090 \ntest %ebp,%ebp\njle 1229 \nmov %r12,%rcx\nlea -0x1(%rbp),%edx\nlea (%rdx,%rdx,2),%rsi\nlea (%rdx,%rsi,4),%rdx\nlea 0x68(%r12,%rdx,8),%rdi\nmov $0x0,%edx\njmp 11d4 \nadd $0x68,%rcx\ncmp %rdi,%rcx\nje 122e \ncmp %ebx,0x64(%rcx)\njl 11cb \nmovslq %edx,%rsi\nlea (%rsi,%rsi,2),%r8\nlea (%rsi,%r8,4),%rsi\nlea (%rax,%rsi,8),%rsi\nmovdqu (%rcx),%xmm0\nmovups %xmm0,(%rsi)\nmovdqu 0x10(%rcx),%xmm1\nmovups %xmm1,0x10(%rsi)\nmovdqu 0x20(%rcx),%xmm2\nmovups %xmm2,0x20(%rsi)\nmovdqu 0x30(%rcx),%xmm3\nmovups %xmm3,0x30(%rsi)\nmovdqu 0x40(%rcx),%xmm4\nmovups %xmm4,0x40(%rsi)\nmovdqu 0x50(%rcx),%xmm5\nmovups %xmm5,0x50(%rsi)\nmov 0x60(%rcx),%r8\nmov %r8,0x60(%rsi)\nadd $0x1,%edx\njmp 11cb \nmov $0x0,%edx\nmov %edx,%edx\npop %rbx\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12, rdi\nmov r13, rsi\nmov ebx, edx\nmovsxd rax, esi\nlea rdx, [rax+rax*2]\nlea rdi, [rax+rdx*4]\nlea rbp, ds:0[rdi*8]\nmov rdi, rbp; size\ncall _malloc\ntest r13d, r13d\njle short loc_124C\nmov rcx, r12\nlea rdi, [rbp+r12+0]\nmov edx, 0\njmp short loc_11F7\nloc_11EE:\nadd rcx, 68h ; 'h'\ncmp rcx, rdi\njz short loc_1251\nloc_11F7:\ncmp [rcx+64h], ebx\njl short loc_11EE\nmovsxd rsi, edx\nlea r8, [rsi+rsi*2]\nlea rsi, [rsi+r8*4]\nlea rsi, [rax+rsi*8]\nmovdqu xmm0, xmmword ptr [rcx]\nmovups xmmword ptr [rsi], xmm0\nmovdqu xmm1, xmmword ptr [rcx+10h]\nmovups xmmword ptr [rsi+10h], xmm1\nmovdqu xmm2, xmmword ptr [rcx+20h]\nmovups xmmword ptr [rsi+20h], xmm2\nmovdqu xmm3, xmmword ptr [rcx+30h]\nmovups xmmword ptr [rsi+30h], xmm3\nmovdqu xmm4, xmmword ptr [rcx+40h]\nmovups xmmword ptr [rsi+40h], xmm4\nmovdqu xmm5, xmmword ptr [rcx+50h]\nmovups xmmword ptr [rsi+50h], xmm5\nmov r8, [rcx+60h]\nmov [rsi+60h], r8\nadd edx, 1\njmp short loc_11EE\nloc_124C:\nmov edx, 0\nloc_1251:\nmov edx, edx\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "char *__fastcall func0(const __m128i *a1, int a2, __int32 a3)\n{\n size_t v4; // rbp\n char *result; // rax\n const __m128i *v6; // rcx\n int v7; // edx\n __m128i *v8; // rsi\n\n v4 = 104LL * a2;\n result = (char *)malloc(v4);\n if ( a2 > 0 )\n {\n v6 = a1;\n v7 = 0;\n do\n {\n if ( v6[6].m128i_i32[1] >= a3 )\n {\n v8 = (__m128i *)&result[104 * v7];\n *v8 = _mm_loadu_si128(v6);\n v8[1] = _mm_loadu_si128(v6 + 1);\n v8[2] = _mm_loadu_si128(v6 + 2);\n v8[3] = _mm_loadu_si128(v6 + 3);\n v8[4] = _mm_loadu_si128(v6 + 4);\n v8[5] = _mm_loadu_si128(v6 + 5);\n v8[6].m128i_i64[0] = v6[6].m128i_i64[0];\n ++v7;\n }\n v6 = (const __m128i *)((char *)v6 + 104);\n }\n while ( v6 != (const __m128i *)&a1->m128i_i8[v4] );\n }\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12, rdi\nmov r13, rsi\nmov ebx, edx\nmovsxd rax, esi\nlea rdx, [rax+rax*2]\nlea rdi, [rax+rdx*4]\nlea rbp, ds:0[rdi*8]\nmov rdi, rbp; size\ncall _malloc\ntest r13d, r13d\njle short loc_124C\nmov rcx, r12\nlea rdi, [rbp+r12+0]\nmov edx, 0\njmp short loc_11F7\nloc_11EE:\nadd rcx, 68h ; 'h'\ncmp rcx, rdi\njz short loc_1251\nloc_11F7:\ncmp [rcx+64h], ebx\njl short loc_11EE\nmovsxd rsi, edx\nlea r8, [rsi+rsi*2]\nlea rsi, [rsi+r8*4]\nlea rsi, [rax+rsi*8]\nmovdqu xmm0, xmmword ptr [rcx]\nmovups xmmword ptr [rsi], xmm0\nmovdqu xmm1, xmmword ptr [rcx+10h]\nmovups xmmword ptr [rsi+10h], xmm1\nmovdqu xmm2, xmmword ptr [rcx+20h]\nmovups xmmword ptr [rsi+20h], xmm2\nmovdqu xmm3, xmmword ptr [rcx+30h]\nmovups xmmword ptr [rsi+30h], xmm3\nmovdqu xmm4, xmmword ptr [rcx+40h]\nmovups xmmword ptr [rsi+40h], xmm4\nmovdqu xmm5, xmmword ptr [rcx+50h]\nmovups xmmword ptr [rsi+50h], xmm5\nmov r8, [rcx+60h]\nmov [rsi+60h], r8\nadd edx, 1\njmp short loc_11EE\nloc_124C:\nmov edx, 0\nloc_1251:\nmov edx, edx\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11A9(const __m128i *a1, int a2, __int32 a3)\n{\n size_t v4; // rbp\n char *result; // rax\n const __m128i *v6; // rcx\n int v7; // edx\n __m128i *v8; // rsi\n\n v4 = 104LL * a2;\n result = (char *)malloc(v4);\n if ( a2 > 0 )\n {\n v6 = a1;\n v7 = 0;\n do\n {\n if ( v6[6].m128i_i32[1] >= a3 )\n {\n v8 = (__m128i *)&result[104 * v7];\n *v8 = _mm_loadu_si128(v6);\n v8[1] = _mm_loadu_si128(v6 + 1);\n v8[2] = _mm_loadu_si128(v6 + 2);\n v8[3] = _mm_loadu_si128(v6 + 3);\n v8[4] = _mm_loadu_si128(v6 + 4);\n v8[5] = _mm_loadu_si128(v6 + 5);\n v8[6].m128i_i64[0] = v6[6].m128i_i64[0];\n ++v7;\n }\n v6 = (const __m128i *)((char *)v6 + 104);\n }\n while ( v6 != (const __m128i *)&a1->m128i_i8[v4] );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11A9(const __m128i *a1, int a2, int a3) {\n unsigned int v4;\n char *result;\n const __m128i *v6;\n int v7;\n __m128i *v8;\n v4 = 104LL * a2;\n result = (char *)malloc(v4);\n if (a2 > 0) {\n v6 = a1;\n v7 = 0;\n do {\n if (v6[6].m128i_i32[1] >= a3) {\n v8 = (__m128i *)&result[104 * v7];\n *v8 = _mm_loadu_si128(v6);\n v8[1] = _mm_loadu_si128(v6 + 1);\n v8[2] = _mm_loadu_si128(v6 + 2);\n v8[3] = _mm_loadu_si128(v6 + 3);\n v8[4] = _mm_loadu_si128(v6 + 4);\n v8[5] = _mm_loadu_si128(v6 + 5);\n v8[6].m128i_i64[0] = v6[6].m128i_i64[0];\n ++v7;\n }\n v6 = (const __m128i *)((char *)v6 + 104);\n } while (v6 != (const __m128i *)&a1->m128i_i8[v4]);\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(const __m128i *a1, int a2, int a3) {\n unsigned int v4;\n char *result;\n const __m128i *v6;\n int v7;\n __m128i *v8;\n v4 = 104LL * a2;\n result = (char *)malloc(v4);\n if (a2 > 0) {\n v6 = a1;\n v7 = 0;\n do {\n if (v6[6].m128i_i32[1] >= a3) {\n v8 = (__m128i *)&result[104 * v7];\n *v8 = _mm_loadu_si128(v6);\n v8[1] = _mm_loadu_si128(v6 + 1);\n v8[2] = _mm_loadu_si128(v6 + 2);\n v8[3] = _mm_loadu_si128(v6 + 3);\n v8[4] = _mm_loadu_si128(v6 + 4);\n v8[5] = _mm_loadu_si128(v6 + 5);\n v8[6].m128i_i64[0] = v6[6].m128i_i64[0];\n ++v7;\n }\n v6 = (const __m128i *)((char *)v6 + 104);\n } while (v6 != (const __m128i *)&a1->m128i_i8[v4]);\n }\n return result;\n}" + }, + { + "index": 277, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char key[100];\n\n int value;\n\n} DictItem;\n\n\n\ntypedef struct {\n\n DictItem* items;\n\n int size;\n\n} Dict;\n\n\n\n", + "func": "Dict func0(Dict input, int n) {\n Dict result;\n result.items = (DictItem*)malloc(input.size * sizeof(DictItem));\n result.size = 0;\n for (int i = 0; i < input.size; i++) {\n if (input.items[i].value >= n) {\n result.items[result.size] = input.items[i];\n result.size++;\n }\n }\n return result;\n}", + "test": "int main() {\n\n Dict d1, d2, d3;\n\n d1.size = 4;\n\n d1.items = (DictItem*)malloc(d1.size * sizeof(DictItem));\n\n strcpy(d1.items[0].key, \"Cierra Vega\"); d1.items[0].value = 175;\n\n strcpy(d1.items[1].key, \"Alden Cantrell\"); d1.items[1].value = 180;\n\n strcpy(d1.items[2].key, \"Kierra Gentry\"); d1.items[2].value = 165;\n\n strcpy(d1.items[3].key, \"Pierre Cox\"); d1.items[3].value = 190;\n\n\n\n Dict result;\n\n\n\n result = func0(d1, 170);\n\n assert(result.size == 3 && strcmp(result.items[0].key, \"Cierra Vega\") == 0 && strcmp(result.items[1].key, \"Alden Cantrell\") == 0 && strcmp(result.items[2].key, \"Pierre Cox\") == 0);\n\n\n\n result = func0(d1, 180);\n\n assert(result.size == 2 && strcmp(result.items[0].key, \"Alden Cantrell\") == 0 && strcmp(result.items[1].key, \"Pierre Cox\") == 0);\n\n \n\n result = func0(d1, 190);\n\n assert(result.size == 1 && strcmp(result.items[0].key, \"Pierre Cox\") == 0);\n\n \n\n free(d1.items);\n\n free(result.items);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmovslq %esi,%rax\npush %r12\nmov %rsi,%r12\npush %rbp\nmov %edx,%ebp\nlea (%rax,%rax,2),%rdx\npush %rbx\nmov %rdi,%rbx\nlea (%rax,%rdx,4),%rdi\nshl $0x3,%rdi\ncallq 1090 \ntest %r12d,%r12d\njle 1478 \nlea -0x1(%r12),%edx\nmov %rbx,%rdi\nxor %esi,%esi\nlea (%rdx,%rdx,2),%rcx\nlea (%rdx,%rcx,4),%rdx\nlea 0x68(%rbx,%rdx,8),%rdx\ncmp %ebp,0x64(%rdi)\njl 1463 \nmovslq %esi,%rcx\nmovdqu (%rdi),%xmm0\nmovdqu 0x10(%rdi),%xmm1\nadd $0x1,%esi\nlea (%rcx,%rcx,2),%r8\nmovdqu 0x20(%rdi),%xmm2\nmovdqu 0x30(%rdi),%xmm3\nlea (%rcx,%r8,4),%rcx\nmov 0x60(%rdi),%r8\nmovdqu 0x40(%rdi),%xmm4\nlea (%rax,%rcx,8),%rcx\nmovdqu 0x50(%rdi),%xmm5\nmov %r8,0x60(%rcx)\nmovups %xmm0,(%rcx)\nmovups %xmm1,0x10(%rcx)\nmovups %xmm2,0x20(%rcx)\nmovups %xmm3,0x30(%rcx)\nmovups %xmm4,0x40(%rcx)\nmovups %xmm5,0x50(%rcx)\nadd $0x68,%rdi\ncmp %rdx,%rdi\njne 1410 \npop %rbx\nmov %esi,%edx\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax,%rax,1)\nxor %esi,%esi\npop %rbx\npop %rbp\nmov %esi,%edx\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmovsxd rax, esi\npush r13\nmov r13, rsi\npush r12\nmov r12d, edx\nlea rdx, [rax+rax*2]\npush rbp\npush rbx\nmov rbx, rdi\nlea rdi, [rax+rdx*4]\nlea rbp, ds:0[rdi*8]\nmov rdi, rbp; size\nsub rsp, 8\ncall _malloc\ntest r13d, r13d\njle loc_1468\nmov rcx, rbx\nlea rdi, [rbp+rbx+0]\nxor edx, edx\nnop dword ptr [rax]\nloc_13F8:\ncmp [rcx+64h], r12d\njl short loc_144C\nmovsxd rsi, edx\nmovdqu xmm0, xmmword ptr [rcx]\nmovdqu xmm1, xmmword ptr [rcx+10h]\nadd edx, 1\nlea r8, [rsi+rsi*2]\nmovdqu xmm2, xmmword ptr [rcx+20h]\nmovdqu xmm3, xmmword ptr [rcx+30h]\nlea rsi, [rsi+r8*4]\nmov r8, [rcx+60h]\nmovdqu xmm4, xmmword ptr [rcx+40h]\nlea rsi, [rax+rsi*8]\nmovdqu xmm5, xmmword ptr [rcx+50h]\nmov [rsi+60h], r8\nmovups xmmword ptr [rsi], xmm0\nmovups xmmword ptr [rsi+10h], xmm1\nmovups xmmword ptr [rsi+20h], xmm2\nmovups xmmword ptr [rsi+30h], xmm3\nmovups xmmword ptr [rsi+40h], xmm4\nmovups xmmword ptr [rsi+50h], xmm5\nloc_144C:\nadd rcx, 68h ; 'h'\ncmp rcx, rdi\njnz short loc_13F8\nadd rsp, 8\nmov edx, edx\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1468:\nadd rsp, 8\nxor edx, edx\npop rbx\nmov edx, edx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "char *__fastcall func0(const __m128i *a1, int a2, __int32 a3)\n{\n size_t v4; // rbp\n char *result; // rax\n const __m128i *v6; // rcx\n int v7; // edx\n __int64 v8; // rsi\n __m128i v9; // xmm0\n __m128i v10; // xmm1\n __m128i v11; // xmm2\n __m128i v12; // xmm3\n __m128i v13; // xmm4\n __m128i *v14; // rsi\n __m128i v15; // xmm5\n\n v4 = 104LL * a2;\n result = (char *)malloc(v4);\n if ( a2 > 0 )\n {\n v6 = a1;\n v7 = 0;\n do\n {\n if ( v6[6].m128i_i32[1] >= a3 )\n {\n v8 = v7;\n v9 = _mm_loadu_si128(v6);\n v10 = _mm_loadu_si128(v6 + 1);\n ++v7;\n v11 = _mm_loadu_si128(v6 + 2);\n v12 = _mm_loadu_si128(v6 + 3);\n v13 = _mm_loadu_si128(v6 + 4);\n v14 = (__m128i *)&result[104 * v8];\n v15 = _mm_loadu_si128(v6 + 5);\n v14[6].m128i_i64[0] = v6[6].m128i_i64[0];\n *v14 = v9;\n v14[1] = v10;\n v14[2] = v11;\n v14[3] = v12;\n v14[4] = v13;\n v14[5] = v15;\n }\n v6 = (const __m128i *)((char *)v6 + 104);\n }\n while ( v6 != (const __m128i *)&a1->m128i_i8[v4] );\n }\n return result;\n}", + "ida_strip_asm": "sub_13B0:\nendbr64\nmovsxd rax, esi\npush r13\nmov r13, rsi\npush r12\nmov r12d, edx\nlea rdx, [rax+rax*2]\npush rbp\npush rbx\nmov rbx, rdi\nlea rdi, [rax+rdx*4]\nlea rbp, ds:0[rdi*8]\nmov rdi, rbp; size\nsub rsp, 8\ncall _malloc\ntest r13d, r13d\njle loc_1468\nmov rcx, rbx\nlea rdi, [rbp+rbx+0]\nxor edx, edx\nnop dword ptr [rax]\nloc_13F8:\ncmp [rcx+64h], r12d\njl short loc_144C\nmovsxd rsi, edx\nmovdqu xmm0, xmmword ptr [rcx]\nmovdqu xmm1, xmmword ptr [rcx+10h]\nadd edx, 1\nlea r8, [rsi+rsi*2]\nmovdqu xmm2, xmmword ptr [rcx+20h]\nmovdqu xmm3, xmmword ptr [rcx+30h]\nlea rsi, [rsi+r8*4]\nmov r8, [rcx+60h]\nmovdqu xmm4, xmmword ptr [rcx+40h]\nlea rsi, [rax+rsi*8]\nmovdqu xmm5, xmmword ptr [rcx+50h]\nmov [rsi+60h], r8\nmovups xmmword ptr [rsi], xmm0\nmovups xmmword ptr [rsi+10h], xmm1\nmovups xmmword ptr [rsi+20h], xmm2\nmovups xmmword ptr [rsi+30h], xmm3\nmovups xmmword ptr [rsi+40h], xmm4\nmovups xmmword ptr [rsi+50h], xmm5\nloc_144C:\nadd rcx, 68h ; 'h'\ncmp rcx, rdi\njnz short loc_13F8\nadd rsp, 8\nmov edx, edx\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1468:\nadd rsp, 8\nxor edx, edx\npop rbx\nmov edx, edx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "char *__fastcall sub_13B0(const __m128i *a1, int a2, __int32 a3)\n{\n size_t v4; // rbp\n char *result; // rax\n const __m128i *v6; // rcx\n int v7; // edx\n __int64 v8; // rsi\n __m128i v9; // xmm0\n __m128i v10; // xmm1\n __m128i v11; // xmm2\n __m128i v12; // xmm3\n __m128i v13; // xmm4\n __m128i *v14; // rsi\n __m128i v15; // xmm5\n\n v4 = 104LL * a2;\n result = (char *)malloc(v4);\n if ( a2 > 0 )\n {\n v6 = a1;\n v7 = 0;\n do\n {\n if ( v6[6].m128i_i32[1] >= a3 )\n {\n v8 = v7;\n v9 = _mm_loadu_si128(v6);\n v10 = _mm_loadu_si128(v6 + 1);\n ++v7;\n v11 = _mm_loadu_si128(v6 + 2);\n v12 = _mm_loadu_si128(v6 + 3);\n v13 = _mm_loadu_si128(v6 + 4);\n v14 = (__m128i *)&result[104 * v8];\n v15 = _mm_loadu_si128(v6 + 5);\n v14[6].m128i_i64[0] = v6[6].m128i_i64[0];\n *v14 = v9;\n v14[1] = v10;\n v14[2] = v11;\n v14[3] = v12;\n v14[4] = v13;\n v14[5] = v15;\n }\n v6 = (const __m128i *)((char *)v6 + 104);\n }\n while ( v6 != (const __m128i *)&a1->m128i_i8[v4] );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_13B0(const __m128i *a1, int a2, int a3) {\n unsigned int v4;\n char *result;\n const __m128i *v6;\n int v7;\n long long v8;\n __m128i v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i *v14;\n __m128i v15;\n v4 = 104LL * a2;\n result = (char *)malloc(v4);\n if (a2 > 0) {\n v6 = a1;\n v7 = 0;\n do {\n if (v6[6].m128i_i32[1] >= a3) {\n v8 = v7;\n v9 = _mm_loadu_si128(v6);\n v10 = _mm_loadu_si128(v6 + 1);\n ++v7;\n v11 = _mm_loadu_si128(v6 + 2);\n v12 = _mm_loadu_si128(v6 + 3);\n v13 = _mm_loadu_si128(v6 + 4);\n v14 = (__m128i *)&result[104 * v8];\n v15 = _mm_loadu_si128(v6 + 5);\n v14[6].m128i_i64[0] = v6[6].m128i_i64[0];\n *v14 = v9;\n v14[1] = v10;\n v14[2] = v11;\n v14[3] = v12;\n v14[4] = v13;\n v14[5] = v15;\n }\n v6 = (const __m128i *)((char *)v6 + 104);\n } while (v6 != (const __m128i *)&a1->m128i_i8[v4]);\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(const __m128i *a1, int a2, int a3) {\n unsigned int v4;\n char *result;\n const __m128i *v6;\n int v7;\n long long v8;\n __m128i v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i *v14;\n __m128i v15;\n v4 = 104LL * a2;\n result = (char *)malloc(v4);\n if (a2 > 0) {\n v6 = a1;\n v7 = 0;\n do {\n if (v6[6].m128i_i32[1] >= a3) {\n v8 = v7;\n v9 = _mm_loadu_si128(v6);\n v10 = _mm_loadu_si128(v6 + 1);\n ++v7;\n v11 = _mm_loadu_si128(v6 + 2);\n v12 = _mm_loadu_si128(v6 + 3);\n v13 = _mm_loadu_si128(v6 + 4);\n v14 = (__m128i *)&result[104 * v8];\n v15 = _mm_loadu_si128(v6 + 5);\n v14[6].m128i_i64[0] = v6[6].m128i_i64[0];\n *v14 = v9;\n v14[1] = v10;\n v14[2] = v11;\n v14[3] = v12;\n v14[4] = v13;\n v14[5] = v15;\n }\n v6 = (const __m128i *)((char *)v6 + 104);\n } while (v6 != (const __m128i *)&a1->m128i_i8[v4]);\n }\n return result;\n}" + }, + { + "index": 277, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char key[100];\n\n int value;\n\n} DictItem;\n\n\n\ntypedef struct {\n\n DictItem* items;\n\n int size;\n\n} Dict;\n\n\n\n", + "func": "Dict func0(Dict input, int n) {\n Dict result;\n result.items = (DictItem*)malloc(input.size * sizeof(DictItem));\n result.size = 0;\n for (int i = 0; i < input.size; i++) {\n if (input.items[i].value >= n) {\n result.items[result.size] = input.items[i];\n result.size++;\n }\n }\n return result;\n}", + "test": "int main() {\n\n Dict d1, d2, d3;\n\n d1.size = 4;\n\n d1.items = (DictItem*)malloc(d1.size * sizeof(DictItem));\n\n strcpy(d1.items[0].key, \"Cierra Vega\"); d1.items[0].value = 175;\n\n strcpy(d1.items[1].key, \"Alden Cantrell\"); d1.items[1].value = 180;\n\n strcpy(d1.items[2].key, \"Kierra Gentry\"); d1.items[2].value = 165;\n\n strcpy(d1.items[3].key, \"Pierre Cox\"); d1.items[3].value = 190;\n\n\n\n Dict result;\n\n\n\n result = func0(d1, 170);\n\n assert(result.size == 3 && strcmp(result.items[0].key, \"Cierra Vega\") == 0 && strcmp(result.items[1].key, \"Alden Cantrell\") == 0 && strcmp(result.items[2].key, \"Pierre Cox\") == 0);\n\n\n\n result = func0(d1, 180);\n\n assert(result.size == 2 && strcmp(result.items[0].key, \"Alden Cantrell\") == 0 && strcmp(result.items[1].key, \"Pierre Cox\") == 0);\n\n \n\n result = func0(d1, 190);\n\n assert(result.size == 1 && strcmp(result.items[0].key, \"Pierre Cox\") == 0);\n\n \n\n free(d1.items);\n\n free(result.items);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nmovslq %esi,%rax\npush %r12\nmov %rsi,%r12\npush %rbp\nmov %edx,%ebp\nlea (%rax,%rax,2),%rdx\npush %rbx\nmov %rdi,%rbx\nlea (%rax,%rdx,4),%rdi\nshl $0x3,%rdi\ncallq 1090 \ntest %r12d,%r12d\njle 1478 \nlea -0x1(%r12),%edx\nmov %rbx,%rdi\nxor %esi,%esi\nlea (%rdx,%rdx,2),%rcx\nlea (%rdx,%rcx,4),%rdx\nlea 0x68(%rbx,%rdx,8),%rdx\ncmp %ebp,0x64(%rdi)\njl 1463 \nmovslq %esi,%rcx\nmovdqu (%rdi),%xmm0\nmovdqu 0x10(%rdi),%xmm1\nadd $0x1,%esi\nlea (%rcx,%rcx,2),%r8\nmovdqu 0x20(%rdi),%xmm2\nmovdqu 0x30(%rdi),%xmm3\nlea (%rcx,%r8,4),%rcx\nmov 0x60(%rdi),%r8\nmovdqu 0x40(%rdi),%xmm4\nlea (%rax,%rcx,8),%rcx\nmovdqu 0x50(%rdi),%xmm5\nmov %r8,0x60(%rcx)\nmovups %xmm0,(%rcx)\nmovups %xmm1,0x10(%rcx)\nmovups %xmm2,0x20(%rcx)\nmovups %xmm3,0x30(%rcx)\nmovups %xmm4,0x40(%rcx)\nmovups %xmm5,0x50(%rcx)\nadd $0x68,%rdi\ncmp %rdx,%rdi\njne 1410 \npop %rbx\nmov %esi,%edx\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax,%rax,1)\nxor %esi,%esi\npop %rbx\npop %rbp\nmov %esi,%edx\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmovsxd rax, esi\npush r13\nmov r13, rsi\npush r12\nmov r12d, edx\nlea rdx, [rax+rax*2]\npush rbp\npush rbx\nmov rbx, rdi\nlea rdi, [rax+rdx*4]\nlea rbp, ds:0[rdi*8]\nmov rdi, rbp; size\nsub rsp, 8\ncall _malloc\ntest r13d, r13d\njle loc_1468\nmov rcx, rbx\nlea rdi, [rbp+rbx+0]\nxor edx, edx\nnop dword ptr [rax]\nloc_13F8:\ncmp [rcx+64h], r12d\njl short loc_144C\nmovsxd rsi, edx\nmovdqu xmm0, xmmword ptr [rcx]\nmovdqu xmm1, xmmword ptr [rcx+10h]\nadd edx, 1\nlea r8, [rsi+rsi*2]\nmovdqu xmm2, xmmword ptr [rcx+20h]\nmovdqu xmm3, xmmword ptr [rcx+30h]\nlea rsi, [rsi+r8*4]\nmov r8, [rcx+60h]\nmovdqu xmm4, xmmword ptr [rcx+40h]\nlea rsi, [rax+rsi*8]\nmovdqu xmm5, xmmword ptr [rcx+50h]\nmov [rsi+60h], r8\nmovups xmmword ptr [rsi], xmm0\nmovups xmmword ptr [rsi+10h], xmm1\nmovups xmmword ptr [rsi+20h], xmm2\nmovups xmmword ptr [rsi+30h], xmm3\nmovups xmmword ptr [rsi+40h], xmm4\nmovups xmmword ptr [rsi+50h], xmm5\nloc_144C:\nadd rcx, 68h ; 'h'\ncmp rcx, rdi\njnz short loc_13F8\nadd rsp, 8\nmov edx, edx\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1468:\nadd rsp, 8\nxor edx, edx\npop rbx\nmov edx, edx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "char *__fastcall func0(const __m128i *a1, int a2, __int32 a3)\n{\n size_t v4; // rbp\n char *result; // rax\n const __m128i *v6; // rcx\n int v7; // edx\n __int64 v8; // rsi\n __m128i v9; // xmm0\n __m128i v10; // xmm1\n __m128i v11; // xmm2\n __m128i v12; // xmm3\n __m128i v13; // xmm4\n __m128i *v14; // rsi\n __m128i v15; // xmm5\n\n v4 = 104LL * a2;\n result = (char *)malloc(v4);\n if ( a2 > 0 )\n {\n v6 = a1;\n v7 = 0;\n do\n {\n if ( v6[6].m128i_i32[1] >= a3 )\n {\n v8 = v7;\n v9 = _mm_loadu_si128(v6);\n v10 = _mm_loadu_si128(v6 + 1);\n ++v7;\n v11 = _mm_loadu_si128(v6 + 2);\n v12 = _mm_loadu_si128(v6 + 3);\n v13 = _mm_loadu_si128(v6 + 4);\n v14 = (__m128i *)&result[104 * v8];\n v15 = _mm_loadu_si128(v6 + 5);\n v14[6].m128i_i64[0] = v6[6].m128i_i64[0];\n *v14 = v9;\n v14[1] = v10;\n v14[2] = v11;\n v14[3] = v12;\n v14[4] = v13;\n v14[5] = v15;\n }\n v6 = (const __m128i *)((char *)v6 + 104);\n }\n while ( v6 != (const __m128i *)&a1->m128i_i8[v4] );\n }\n return result;\n}", + "ida_strip_asm": "sub_13B0:\nendbr64\nmovsxd rax, esi\npush r13\nmov r13, rsi\npush r12\nmov r12d, edx\nlea rdx, [rax+rax*2]\npush rbp\npush rbx\nmov rbx, rdi\nlea rdi, [rax+rdx*4]\nlea rbp, ds:0[rdi*8]\nmov rdi, rbp; size\nsub rsp, 8\ncall _malloc\ntest r13d, r13d\njle loc_1468\nmov rcx, rbx\nlea rdi, [rbp+rbx+0]\nxor edx, edx\nnop dword ptr [rax]\nloc_13F8:\ncmp [rcx+64h], r12d\njl short loc_144C\nmovsxd rsi, edx\nmovdqu xmm0, xmmword ptr [rcx]\nmovdqu xmm1, xmmword ptr [rcx+10h]\nadd edx, 1\nlea r8, [rsi+rsi*2]\nmovdqu xmm2, xmmword ptr [rcx+20h]\nmovdqu xmm3, xmmword ptr [rcx+30h]\nlea rsi, [rsi+r8*4]\nmov r8, [rcx+60h]\nmovdqu xmm4, xmmword ptr [rcx+40h]\nlea rsi, [rax+rsi*8]\nmovdqu xmm5, xmmword ptr [rcx+50h]\nmov [rsi+60h], r8\nmovups xmmword ptr [rsi], xmm0\nmovups xmmword ptr [rsi+10h], xmm1\nmovups xmmword ptr [rsi+20h], xmm2\nmovups xmmword ptr [rsi+30h], xmm3\nmovups xmmword ptr [rsi+40h], xmm4\nmovups xmmword ptr [rsi+50h], xmm5\nloc_144C:\nadd rcx, 68h ; 'h'\ncmp rcx, rdi\njnz short loc_13F8\nadd rsp, 8\nmov edx, edx\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1468:\nadd rsp, 8\nxor edx, edx\npop rbx\nmov edx, edx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "char *__fastcall sub_13B0(const __m128i *a1, int a2, __int32 a3)\n{\n size_t v4; // rbp\n char *result; // rax\n const __m128i *v6; // rcx\n int v7; // edx\n __int64 v8; // rsi\n __m128i v9; // xmm0\n __m128i v10; // xmm1\n __m128i v11; // xmm2\n __m128i v12; // xmm3\n __m128i v13; // xmm4\n __m128i *v14; // rsi\n __m128i v15; // xmm5\n\n v4 = 104LL * a2;\n result = (char *)malloc(v4);\n if ( a2 > 0 )\n {\n v6 = a1;\n v7 = 0;\n do\n {\n if ( v6[6].m128i_i32[1] >= a3 )\n {\n v8 = v7;\n v9 = _mm_loadu_si128(v6);\n v10 = _mm_loadu_si128(v6 + 1);\n ++v7;\n v11 = _mm_loadu_si128(v6 + 2);\n v12 = _mm_loadu_si128(v6 + 3);\n v13 = _mm_loadu_si128(v6 + 4);\n v14 = (__m128i *)&result[104 * v8];\n v15 = _mm_loadu_si128(v6 + 5);\n v14[6].m128i_i64[0] = v6[6].m128i_i64[0];\n *v14 = v9;\n v14[1] = v10;\n v14[2] = v11;\n v14[3] = v12;\n v14[4] = v13;\n v14[5] = v15;\n }\n v6 = (const __m128i *)((char *)v6 + 104);\n }\n while ( v6 != (const __m128i *)&a1->m128i_i8[v4] );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_13B0(const __m128i *a1, int a2, int a3) {\n unsigned int v4;\n char *result;\n const __m128i *v6;\n int v7;\n long long v8;\n __m128i v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i *v14;\n __m128i v15;\n v4 = 104LL * a2;\n result = (char *)malloc(v4);\n if (a2 > 0) {\n v6 = a1;\n v7 = 0;\n do {\n if (v6[6].m128i_i32[1] >= a3) {\n v8 = v7;\n v9 = _mm_loadu_si128(v6);\n v10 = _mm_loadu_si128(v6 + 1);\n ++v7;\n v11 = _mm_loadu_si128(v6 + 2);\n v12 = _mm_loadu_si128(v6 + 3);\n v13 = _mm_loadu_si128(v6 + 4);\n v14 = (__m128i *)&result[104 * v8];\n v15 = _mm_loadu_si128(v6 + 5);\n v14[6].m128i_i64[0] = v6[6].m128i_i64[0];\n *v14 = v9;\n v14[1] = v10;\n v14[2] = v11;\n v14[3] = v12;\n v14[4] = v13;\n v14[5] = v15;\n }\n v6 = (const __m128i *)((char *)v6 + 104);\n } while (v6 != (const __m128i *)&a1->m128i_i8[v4]);\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(const __m128i *a1, int a2, int a3) {\n unsigned int v4;\n char *result;\n const __m128i *v6;\n int v7;\n long long v8;\n __m128i v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i *v14;\n __m128i v15;\n v4 = 104LL * a2;\n result = (char *)malloc(v4);\n if (a2 > 0) {\n v6 = a1;\n v7 = 0;\n do {\n if (v6[6].m128i_i32[1] >= a3) {\n v8 = v7;\n v9 = _mm_loadu_si128(v6);\n v10 = _mm_loadu_si128(v6 + 1);\n ++v7;\n v11 = _mm_loadu_si128(v6 + 2);\n v12 = _mm_loadu_si128(v6 + 3);\n v13 = _mm_loadu_si128(v6 + 4);\n v14 = (__m128i *)&result[104 * v8];\n v15 = _mm_loadu_si128(v6 + 5);\n v14[6].m128i_i64[0] = v6[6].m128i_i64[0];\n *v14 = v9;\n v14[1] = v10;\n v14[2] = v11;\n v14[3] = v12;\n v14[4] = v13;\n v14[5] = v15;\n }\n v6 = (const __m128i *)((char *)v6 + 104);\n } while (v6 != (const __m128i *)&a1->m128i_i8[v4]);\n }\n return result;\n}" + }, + { + "index": 278, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const void* test_arr, int size) {\n int count = 0;\n for (int i = 0; i < size; i++) {\n if (((const void**)test_arr)[i] != NULL) {\n count++;\n } else {\n break;\n }\n }\n return count;\n}", + "test": "int main() {\n\n const void* arr1[] = { (void*)1, (void*)5, (void*)7, NULL, (void*)10 };\n\n const void* arr2[] = { (void*)2, (void*)9, NULL, (void*)11 };\n\n const void* arr3[] = { (void*)11, (void*)15, (void*)5, (void*)8, NULL, (void*)8 };\n\n\n\n assert(func0(arr1, 5) == 3);\n\n assert(func0(arr2, 4) == 2);\n\n assert(func0(arr3, 6) == 4);\n\n\n\n printf(\"All tests passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11cc \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\ntest %rax,%rax\nje 11d6 \naddl $0x1,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11a8 \njmp 11d7 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11CC\nloc_11A8:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\ntest rax, rax\njz short loc_11D6\nadd [rbp+var_8], 1\nadd [rbp+var_4], 1\nloc_11CC:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11A8\njmp short loc_11D7\nloc_11D6:\nnop\nloc_11D7:\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2 && *(_QWORD *)(8LL * i + a1); ++i )\n ++v3;\n return v3;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11CC\nloc_11A8:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\ntest rax, rax\njz short loc_11D6\nadd [rbp+var_8], 1\nadd [rbp+var_4], 1\nloc_11CC:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11A8\njmp short loc_11D7\nloc_11D6:\nnop\nloc_11D7:\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2 && *(_QWORD *)(8LL * i + a1); ++i )\n ++v3;\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2 && *(uint64_t *)(8LL * i + a1); ++i) ++v3;\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2 && *(uint64_t *)(8LL * i + a1); ++i) ++v3;\n return v3;\n}" + }, + { + "index": 278, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const void* test_arr, int size) {\n int count = 0;\n for (int i = 0; i < size; i++) {\n if (((const void**)test_arr)[i] != NULL) {\n count++;\n } else {\n break;\n }\n }\n return count;\n}", + "test": "int main() {\n\n const void* arr1[] = { (void*)1, (void*)5, (void*)7, NULL, (void*)10 };\n\n const void* arr2[] = { (void*)2, (void*)9, NULL, (void*)11 };\n\n const void* arr3[] = { (void*)11, (void*)15, (void*)5, (void*)8, NULL, (void*)8 };\n\n\n\n assert(func0(arr1, 5) == 3);\n\n assert(func0(arr2, 4) == 2);\n\n assert(func0(arr3, 6) == 4);\n\n\n\n printf(\"All tests passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11b6 \nlea -0x1(%rsi),%esi\nmov $0x0,%eax\njmp 119e \nmov %rcx,%rax\nmov %eax,%edx\ncmpq $0x0,(%rdi,%rax,8)\nje 11b3 \nlea 0x1(%rax),%edx\nlea 0x1(%rax),%rcx\ncmp %rsi,%rax\njne 119b \nmov %edx,%eax\nretq\nmov $0x0,%edx\njmp 11b3 \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11AA\nmov eax, 0\nloc_1196:\ncmp qword ptr [rdi], 0\njz short locret_11AF\nadd eax, 1\nadd rdi, 8\ncmp esi, eax\njnz short loc_1196\nmov eax, esi\nretn\nloc_11AA:\nmov eax, 0\nlocret_11AF:\nretn", + "ida_pseudo": "__int64 __fastcall func0(_QWORD *a1, int a2)\n{\n __int64 result; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n result = 0LL;\n while ( *a1 )\n {\n result = (unsigned int)(result + 1);\n ++a1;\n if ( a2 == (_DWORD)result )\n return (unsigned int)a2;\n }\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\ntest esi, esi\njle short loc_11AA\nmov eax, 0\nloc_1196:\ncmp qword ptr [rdi], 0\njz short locret_11AF\nadd eax, 1\nadd rdi, 8\ncmp esi, eax\njnz short loc_1196\nmov eax, esi\nretn\nloc_11AA:\nmov eax, 0\nlocret_11AF:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(_QWORD *a1, int a2)\n{\n __int64 result; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n result = 0LL;\n while ( *a1 )\n {\n result = (unsigned int)(result + 1);\n ++a1;\n if ( a2 == (_DWORD)result )\n return (unsigned int)a2;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(uint64_t *a1, int a2) {\n long long result;\n if (a2 <= 0) return 0LL;\n result = 0LL;\n while (*a1) {\n result = (unsigned int)(result + 1);\n ++a1;\n if (a2 == (uint32_t)result) return (unsigned int)a2;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(uint64_t *a1, int a2) {\n long long result;\n if (a2 <= 0) return 0LL;\n result = 0LL;\n while (*a1) {\n result = (unsigned int)(result + 1);\n ++a1;\n if (a2 == (uint32_t)result) return (unsigned int)a2;\n }\n return result;\n}" + }, + { + "index": 279, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) { return 4 * n * n - 3 * n; }", + "test": "int main() {\n\n assert(func0(3) == 27);\n\n assert(func0(7) == 175);\n\n assert(func0(10) == 370);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nimul %eax,%eax\nlea 0x0(,%rax,4),%edx\nmov -0x4(%rbp),%eax\nmov %eax,%ecx\nshl $0x2,%eax\nsub %eax,%ecx\nmov %ecx,%eax\nadd %edx,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov eax, [rbp+var_4]\nimul eax, eax\nlea ecx, ds:0[rax*4]\nmov eax, [rbp+var_4]\nmov edx, eax\nshl eax, 2\nsub edx, eax\nlea eax, [rcx+rdx]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n return (unsigned int)(4 * a1 * a1 - 3 * a1);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov eax, [rbp+var_4]\nimul eax, eax\nlea ecx, ds:0[rax*4]\nmov eax, [rbp+var_4]\nmov edx, eax\nshl eax, 2\nsub edx, eax\nlea eax, [rcx+rdx]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n return (unsigned int)(4 * a1 * a1 - 3 * a1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) { return (unsigned int)(4 * a1 * a1 - 3 * a1); }", + "ida_pseudo_norm": "long long func0(int a1) { return (unsigned int)(4 * a1 * a1 - 3 * a1); }" + }, + { + "index": 280, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int dlist[], int size, int item, int *pos) {\n *pos = 0;\n bool found = false;\n while (*pos < size && !found) {\n if (dlist[*pos] == item) {\n found = true;\n } else {\n (*pos)++;\n }\n }\n return found;\n}", + "test": "int main() {\n\n int pos;\n\n bool found;\n\n\n\n int list1[] = {11, 23, 58, 31, 56, 77, 43, 12, 65, 19};\n\n found = func0(list1, 10, 31, &pos);\n\n assert(found == true && pos == 3);\n\n \n\n int list2[] = {12, 32, 45, 62, 35, 47, 44, 61};\n\n found = func0(list2, 8, 61, &pos);\n\n assert(found == true && pos == 7);\n\n \n\n int list3[] = {9, 10, 17, 19, 22, 39, 48, 56};\n\n found = func0(list3, 8, 48, &pos);\n\n assert(found == true && pos == 6);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmov %rcx,-0x28(%rbp)\nmov -0x28(%rbp),%rax\nmovl $0x0,(%rax)\nmovb $0x0,-0x1(%rbp)\njmp 11c2 \nmov -0x28(%rbp),%rax\nmov (%rax),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x20(%rbp)\njne 11b3 \nmovb $0x1,-0x1(%rbp)\njmp 11c2 \nmov -0x28(%rbp),%rax\nmov (%rax),%eax\nlea 0x1(%rax),%edx\nmov -0x28(%rbp),%rax\nmov %edx,(%rax)\nmov -0x28(%rbp),%rax\nmov (%rax),%eax\ncmp %eax,-0x1c(%rbp)\njle 11d8 \nmovzbl -0x1(%rbp),%eax\nxor $0x1,%eax\ntest %al,%al\njne 118f \nmovzbl -0x1(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_28], rcx\nmov rax, [rbp+var_28]\nmov dword ptr [rax], 0\nmov [rbp+var_1], 0\njmp short loc_11C2\nloc_118F:\nmov rax, [rbp+var_28]\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njnz short loc_11B3\nmov [rbp+var_1], 1\njmp short loc_11C2\nloc_11B3:\nmov rax, [rbp+var_28]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_28]\nmov [rax], edx\nloc_11C2:\nmov rax, [rbp+var_28]\nmov eax, [rax]\ncmp [rbp+var_1C], eax\njle short loc_11D8\nmovzx eax, [rbp+var_1]\nxor eax, 1\ntest al, al\njnz short loc_118F\nloc_11D8:\nmovzx eax, [rbp+var_1]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3, int *a4)\n{\n unsigned __int8 v5; // [rsp+27h] [rbp-1h]\n\n *a4 = 0;\n v5 = 0;\n while ( a2 > *a4 && v5 != 1 )\n {\n if ( a3 == *(_DWORD *)(4LL * *a4 + a1) )\n v5 = 1;\n else\n ++*a4;\n }\n return v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_28], rcx\nmov rax, [rbp+var_28]\nmov dword ptr [rax], 0\nmov [rbp+var_1], 0\njmp short loc_11C2\nloc_118F:\nmov rax, [rbp+var_28]\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njnz short loc_11B3\nmov [rbp+var_1], 1\njmp short loc_11C2\nloc_11B3:\nmov rax, [rbp+var_28]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_28]\nmov [rax], edx\nloc_11C2:\nmov rax, [rbp+var_28]\nmov eax, [rax]\ncmp [rbp+var_1C], eax\njle short loc_11D8\nmovzx eax, [rbp+var_1]\nxor eax, 1\ntest al, al\njnz short loc_118F\nloc_11D8:\nmovzx eax, [rbp+var_1]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3, int *a4)\n{\n unsigned __int8 v5; // [rsp+27h] [rbp-1h]\n\n *a4 = 0;\n v5 = 0;\n while ( a2 > *a4 && v5 != 1 )\n {\n if ( a3 == *(_DWORD *)(4LL * *a4 + a1) )\n v5 = 1;\n else\n ++*a4;\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3, int *a4) {\n unsigned char v5;\n *a4 = 0;\n v5 = 0;\n while (a2 > *a4 && v5 != 1) {\n if (a3 == *(uint32_t *)(4LL * *a4 + a1))\n v5 = 1;\n else\n ++*a4;\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3, int *a4) {\n unsigned char v5;\n *a4 = 0;\n v5 = 0;\n while (a2 > *a4 && v5 != 1) {\n if (a3 == *(uint32_t *)(4LL * *a4 + a1))\n v5 = 1;\n else\n ++*a4;\n }\n return v5;\n}" + }, + { + "index": 280, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int dlist[], int size, int item, int *pos) {\n *pos = 0;\n bool found = false;\n while (*pos < size && !found) {\n if (dlist[*pos] == item) {\n found = true;\n } else {\n (*pos)++;\n }\n }\n return found;\n}", + "test": "int main() {\n\n int pos;\n\n bool found;\n\n\n\n int list1[] = {11, 23, 58, 31, 56, 77, 43, 12, 65, 19};\n\n found = func0(list1, 10, 31, &pos);\n\n assert(found == true && pos == 3);\n\n \n\n int list2[] = {12, 32, 45, 62, 35, 47, 44, 61};\n\n found = func0(list2, 8, 61, &pos);\n\n assert(found == true && pos == 7);\n\n \n\n int list3[] = {9, 10, 17, 19, 22, 39, 48, 56};\n\n found = func0(list3, 8, 48, &pos);\n\n assert(found == true && pos == 6);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmovl $0x0,(%rcx)\nmov $0x0,%ebx\nmov $0x1,%r11d\nmov (%rcx),%eax\ncmp %esi,%eax\nsetge %r9b\nmovslq %eax,%r8\nlea (%rdi,%r8,4),%r10\nmov %ebx,%r8d\ntest %r8b,%r8b\njne 11aa \ntest %r9b,%r9b\njne 11aa \nmov %r11d,%r8d\ncmp %edx,(%r10)\nje 1191 \nadd $0x1,%eax\nmov %eax,(%rcx)\njmp 117f \nmov %r8d,%eax\npop %rbx\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov r11, rdi\nmov eax, 0\nmov ebx, 0\nmov r10d, 1\njmp short loc_1186\nloc_1183:\nadd eax, 1\nloc_1186:\nmov [rcx], eax\ncmp eax, esi\nsetnl r8b\nmovsxd rdi, eax\nlea r9, [r11+rdi*4]\nmov edi, ebx\nloc_1197:\ntest dil, dil\njnz short loc_11AB\ntest r8b, r8b\njnz short loc_11AB\nmov edi, r10d\ncmp [r9], edx\njnz short loc_1183\njmp short loc_1197\nloc_11AB:\nmov eax, edi\npop rbx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3, _DWORD *a4)\n{\n int v5; // eax\n unsigned int v6; // edi\n\n v5 = 0;\nLABEL_3:\n *a4 = v5;\n v6 = 0;\n while ( !(_BYTE)v6 && v5 < a2 )\n {\n v6 = 1;\n if ( *(_DWORD *)(a1 + 4LL * v5) != a3 )\n {\n ++v5;\n goto LABEL_3;\n }\n }\n return v6;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbx\nmov r11, rdi\nmov eax, 0\nmov ebx, 0\nmov r10d, 1\njmp short loc_1186\nloc_1183:\nadd eax, 1\nloc_1186:\nmov [rcx], eax\ncmp eax, esi\nsetnl r8b\nmovsxd rdi, eax\nlea r9, [r11+rdi*4]\nmov edi, ebx\nloc_1197:\ntest dil, dil\njnz short loc_11AB\ntest r8b, r8b\njnz short loc_11AB\nmov edi, r10d\ncmp [r9], edx\njnz short loc_1183\njmp short loc_1197\nloc_11AB:\nmov eax, edi\npop rbx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3, _DWORD *a4)\n{\n int v5; // eax\n unsigned int v6; // edi\n\n v5 = 0;\nLABEL_3:\n *a4 = v5;\n v6 = 0;\n while ( !(_BYTE)v6 && v5 < a2 )\n {\n v6 = 1;\n if ( *(_DWORD *)(a1 + 4LL * v5) != a3 )\n {\n ++v5;\n goto LABEL_3;\n }\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3, uint32_t *a4) {\n int v5;\n unsigned int v6;\n v5 = 0;\nLABEL_3:\n *a4 = v5;\n v6 = 0;\n while (!(uint8_t)v6 && v5 < a2) {\n v6 = 1;\n if (*(uint32_t *)(a1 + 4LL * v5) != a3) {\n ++v5;\n goto LABEL_3;\n }\n }\n return v6;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3, uint32_t *a4) {\n int v5;\n unsigned int v6;\n v5 = 0;\nLABEL_3:\n *a4 = v5;\n v6 = 0;\n while (!(uint8_t)v6 && v5 < a2) {\n v6 = 1;\n if (*(uint32_t *)(a1 + 4LL * v5) != a3) {\n ++v5;\n goto LABEL_3;\n }\n }\n return v6;\n}" + }, + { + "index": 281, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int *test_list, int length) {\n for (int i = 0; i < length - 1; i++) {\n for (int j = i + 1; j < length; j++) {\n if (test_list[i] == test_list[j]) {\n return false;\n }\n }\n }\n return true;\n}", + "test": "int main() {\n\n int list1[] = {1, 2, 3};\n\n int list2[] = {1, 2, 1, 2};\n\n int list3[] = {1, 2, 3, 4, 5};\n\n \n\n assert(func0(list1, sizeof(list1) / sizeof(list1[0])) == true);\n\n assert(func0(list2, sizeof(list2) / sizeof(list2[0])) == false);\n\n assert(func0(list3, sizeof(list3) / sizeof(list3[0])) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11d3 \nmov -0x8(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x4(%rbp)\njmp 11c7 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 11c3 \nmov $0x0,%eax\njmp 11e3 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 118c \naddl $0x1,-0x8(%rbp)\nmov -0x1c(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x8(%rbp)\njl 1181 \nmov $0x1,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\njmp short loc_11D3\nloc_1181:\nmov eax, [rbp+var_8]\nadd eax, 1\nmov [rbp+var_4], eax\njmp short loc_11C7\nloc_118C:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11C3\nmov eax, 0\njmp short loc_11E3\nloc_11C3:\nadd [rbp+var_4], 1\nloc_11C7:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_118C\nadd [rbp+var_8], 1\nloc_11D3:\nmov eax, [rbp+var_1C]\nsub eax, 1\ncmp [rbp+var_8], eax\njl short loc_1181\nmov eax, 1\nloc_11E3:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+14h] [rbp-8h]\n int j; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i < a2 - 1; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4LL * j + a1) )\n return 0LL;\n }\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\njmp short loc_11D3\nloc_1181:\nmov eax, [rbp+var_8]\nadd eax, 1\nmov [rbp+var_4], eax\njmp short loc_11C7\nloc_118C:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11C3\nmov eax, 0\njmp short loc_11E3\nloc_11C3:\nadd [rbp+var_4], 1\nloc_11C7:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_118C\nadd [rbp+var_8], 1\nloc_11D3:\nmov eax, [rbp+var_1C]\nsub eax, 1\ncmp [rbp+var_8], eax\njl short loc_1181\nmov eax, 1\nloc_11E3:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int i; // [rsp+14h] [rbp-8h]\n int j; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i < a2 - 1; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4LL * j + a1) )\n return 0LL;\n }\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int i;\n int j;\n for (i = 0; i < a2 - 1; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if (*(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4LL * j + a1))\n return 0LL;\n }\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int i;\n int j;\n for (i = 0; i < a2 - 1; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if (*(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4LL * j + a1))\n return 0LL;\n }\n }\n return 1LL;\n}" + }, + { + "index": 281, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int *test_list, int length) {\n for (int i = 0; i < length - 1; i++) {\n for (int j = i + 1; j < length; j++) {\n if (test_list[i] == test_list[j]) {\n return false;\n }\n }\n }\n return true;\n}", + "test": "int main() {\n\n int list1[] = {1, 2, 3};\n\n int list2[] = {1, 2, 1, 2};\n\n int list3[] = {1, 2, 3, 4, 5};\n\n \n\n assert(func0(list1, sizeof(list1) / sizeof(list1[0])) == true);\n\n assert(func0(list2, sizeof(list2) / sizeof(list2[0])) == false);\n\n assert(func0(list3, sizeof(list3) / sizeof(list3[0])) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%esi\njle 11a6 \nlea -0x2(%rsi),%r8d\nadd $0x2,%r8\nmov $0x1,%ecx\ncmp %ecx,%esi\njle 1197 \nmov -0x4(%rdi,%rcx,4),%edx\nmov %rcx,%rax\ncmp (%rdi,%rax,4),%edx\nje 11ac \nadd $0x1,%rax\ncmp %eax,%esi\njg 118a \nadd $0x1,%rcx\ncmp %r8,%rcx\njne 117f \nmov $0x1,%eax\nretq\nmov $0x1,%eax\nretq\nmov $0x0,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ncmp esi, 1\njle short loc_11A1\nmov r8d, esi\nmov ecx, 1\nloc_117A:\ncmp esi, ecx\njle short loc_1192\nmov edx, [rdi+rcx*4-4]\nmov rax, rcx\nloc_1185:\ncmp edx, [rdi+rax*4]\njz short loc_11A7\nadd rax, 1\ncmp esi, eax\njg short loc_1185\nloc_1192:\nadd rcx, 1\ncmp rcx, r8\njnz short loc_117A\nmov eax, 1\nretn\nloc_11A1:\nmov eax, 1\nretn\nloc_11A7:\nmov eax, 0\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // rcx\n __int64 v3; // rax\n\n if ( a2 <= 1 )\n return 1LL;\n v2 = 1LL;\n while ( a2 <= (int)v2 )\n {\nLABEL_7:\n if ( ++v2 == a2 )\n return 1LL;\n }\n v3 = v2;\n while ( *(_DWORD *)(a1 + 4 * v2 - 4) != *(_DWORD *)(a1 + 4 * v3) )\n {\n if ( a2 <= (int)++v3 )\n goto LABEL_7;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ncmp esi, 1\njle short loc_11A1\nmov r8d, esi\nmov ecx, 1\nloc_117A:\ncmp esi, ecx\njle short loc_1192\nmov edx, [rdi+rcx*4-4]\nmov rax, rcx\nloc_1185:\ncmp edx, [rdi+rax*4]\njz short loc_11A7\nadd rax, 1\ncmp esi, eax\njg short loc_1185\nloc_1192:\nadd rcx, 1\ncmp rcx, r8\njnz short loc_117A\nmov eax, 1\nretn\nloc_11A1:\nmov eax, 1\nretn\nloc_11A7:\nmov eax, 0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n __int64 v2; // rcx\n __int64 v3; // rax\n\n if ( a2 <= 1 )\n return 1LL;\n v2 = 1LL;\n while ( a2 <= (int)v2 )\n {\nLABEL_7:\n if ( ++v2 == a2 )\n return 1LL;\n }\n v3 = v2;\n while ( *(_DWORD *)(a1 + 4 * v2 - 4) != *(_DWORD *)(a1 + 4 * v3) )\n {\n if ( a2 <= (int)++v3 )\n goto LABEL_7;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n long long v2;\n long long v3;\n if (a2 <= 1) return 1LL;\n v2 = 1LL;\n while (a2 <= (int)v2) {\n LABEL_7:\n if (++v2 == a2) return 1LL;\n }\n v3 = v2;\n while (*(uint32_t *)(a1 + 4 * v2 - 4) != *(uint32_t *)(a1 + 4 * v3)) {\n if (a2 <= (int)++v3) goto LABEL_7;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n long long v3;\n if (a2 <= 1) return 1LL;\n v2 = 1LL;\n while (a2 <= (int)v2) {\n LABEL_7:\n if (++v2 == a2) return 1LL;\n }\n v3 = v2;\n while (*(uint32_t *)(a1 + 4 * v2 - 4) != *(uint32_t *)(a1 + 4 * v3)) {\n if (a2 <= (int)++v3) goto LABEL_7;\n }\n return 0LL;\n}" + }, + { + "index": 281, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int *test_list, int length) {\n for (int i = 0; i < length - 1; i++) {\n for (int j = i + 1; j < length; j++) {\n if (test_list[i] == test_list[j]) {\n return false;\n }\n }\n }\n return true;\n}", + "test": "int main() {\n\n int list1[] = {1, 2, 3};\n\n int list2[] = {1, 2, 1, 2};\n\n int list3[] = {1, 2, 3, 4, 5};\n\n \n\n assert(func0(list1, sizeof(list1) / sizeof(list1[0])) == true);\n\n assert(func0(list2, sizeof(list2) / sizeof(list2[0])) == false);\n\n assert(func0(list3, sizeof(list3) / sizeof(list3[0])) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%esi\njle 12c9 \nlea -0x2(%rsi),%r8d\nmov $0x1,%ecx\nadd $0x2,%r8\ncmp %ecx,%esi\njle 12c0 \nmov -0x4(%rdi,%rcx,4),%edx\nmov %rcx,%rax\njmp 12b0 \nnopl 0x0(%rax,%rax,1)\nadd $0x1,%rax\ncmp %eax,%esi\njle 12c0 \ncmp (%rdi,%rax,4),%edx\njne 12a8 \nxor %eax,%eax\nretq\nnopl 0x0(%rax,%rax,1)\nadd $0x1,%rcx\ncmp %r8,%rcx\njne 1296 \nmov $0x1,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ncmp esi, 1\njle short loc_12A9\nmov r8d, esi\nmov ecx, 1\nloc_1281:\ncmp esi, ecx\njle short loc_12A0\nmov edx, [rdi+rcx*4-4]\nmov rax, rcx\njmp short loc_1298\nloc_1290:\nadd rax, 1\ncmp esi, eax\njle short loc_12A0\nloc_1298:\ncmp edx, [rdi+rax*4]\njnz short loc_1290\nxor eax, eax\nretn\nloc_12A0:\nadd rcx, 1\ncmp rcx, r8\njnz short loc_1281\nloc_12A9:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // rcx\n __int64 v3; // rax\n\n if ( a2 <= 1 )\n return 1LL;\n v2 = 1LL;\n while ( a2 <= (int)v2 )\n {\nLABEL_8:\n if ( ++v2 == a2 )\n return 1LL;\n }\n v3 = v2;\n while ( *(_DWORD *)(a1 + 4 * v2 - 4) != *(_DWORD *)(a1 + 4 * v3) )\n {\n if ( a2 <= (int)++v3 )\n goto LABEL_8;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1270:\nendbr64\ncmp esi, 1\njle short loc_12A9\nmov r8d, esi\nmov ecx, 1\nloc_1281:\ncmp esi, ecx\njle short loc_12A0\nmov edx, [rdi+rcx*4-4]\nmov rax, rcx\njmp short loc_1298\nloc_1290:\nadd rax, 1\ncmp esi, eax\njle short loc_12A0\nloc_1298:\ncmp edx, [rdi+rax*4]\njnz short loc_1290\nxor eax, eax\nretn\nloc_12A0:\nadd rcx, 1\ncmp rcx, r8\njnz short loc_1281\nloc_12A9:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1270(__int64 a1, int a2)\n{\n __int64 v2; // rcx\n __int64 v3; // rax\n\n if ( a2 <= 1 )\n return 1LL;\n v2 = 1LL;\n while ( a2 <= (int)v2 )\n {\nLABEL_8:\n if ( ++v2 == a2 )\n return 1LL;\n }\n v3 = v2;\n while ( *(_DWORD *)(a1 + 4 * v2 - 4) != *(_DWORD *)(a1 + 4 * v3) )\n {\n if ( a2 <= (int)++v3 )\n goto LABEL_8;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1270(long long a1, int a2) {\n long long v2;\n long long v3;\n if (a2 <= 1) return 1LL;\n v2 = 1LL;\n while (a2 <= (int)v2) {\n LABEL_8:\n if (++v2 == a2) return 1LL;\n }\n v3 = v2;\n while (*(uint32_t *)(a1 + 4 * v2 - 4) != *(uint32_t *)(a1 + 4 * v3)) {\n if (a2 <= (int)++v3) goto LABEL_8;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n long long v3;\n if (a2 <= 1) return 1LL;\n v2 = 1LL;\n while (a2 <= (int)v2) {\n LABEL_8:\n if (++v2 == a2) return 1LL;\n }\n v3 = v2;\n while (*(uint32_t *)(a1 + 4 * v2 - 4) != *(uint32_t *)(a1 + 4 * v3)) {\n if (a2 <= (int)++v3) goto LABEL_8;\n }\n return 0LL;\n}" + }, + { + "index": 282, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int nums1[], int nums2[], int size, int result[]) {\n for (int i = 0; i < size; i++) {\n result[i] = nums1[i] - nums2[i];\n }\n return result;\n}", + "test": "int main() {\n\n int result1[3], result2[2], result3[2];\n\n int nums1a[] = {1, 2, 3}, nums2a[] = {4, 5, 6};\n\n int nums1b[] = {1, 2}, nums2b[] = {3, 4};\n\n int nums1c[] = {90, 120}, nums2c[] = {50, 70};\n\n\n\n assert(func0(nums1a, nums2a, 3, result1)[0] == -3 && func0(nums1a, nums2a, 3, result1)[1] == -3 && func0(nums1a, nums2a, 3, result1)[2] == -3);\n\n assert(func0(nums1b, nums2b, 2, result2)[0] == -2 && func0(nums1b, nums2b, 2, result2)[1] == -2);\n\n assert(func0(nums1c, nums2c, 2, result3)[0] == 40 && func0(nums1c, nums2c, 2, result3)[1] == 50);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %edx,-0x24(%rbp)\nmov %rcx,-0x30(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11d3 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%ecx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rsi\nmov -0x30(%rbp),%rax\nadd %rsi,%rax\nsub %edx,%ecx\nmov %ecx,%edx\nmov %edx,(%rax)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x24(%rbp),%eax\njl 1189 \nmov -0x30(%rbp),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_30], rcx\nmov [rbp+var_4], 0\njmp short loc_11D2\nloc_1189:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov ecx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rsi, ds:0[rdx*4]\nmov rdx, [rbp+var_30]\nadd rdx, rsi\nsub ecx, eax\nmov [rdx], ecx\nadd [rbp+var_4], 1\nloc_11D2:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_24]\njl short loc_1189\nmov rax, [rbp+var_30]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3, __int64 a4)\n{\n int i; // [rsp+2Ch] [rbp-4h]\n\n for ( i = 0; i < a3; ++i )\n *(_DWORD *)(4LL * i + a4) = *(_DWORD *)(4LL * i + a1) - *(_DWORD *)(4LL * i + a2);\n return a4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_30], rcx\nmov [rbp+var_4], 0\njmp short loc_11D2\nloc_1189:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov ecx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rsi, ds:0[rdx*4]\nmov rdx, [rbp+var_30]\nadd rdx, rsi\nsub ecx, eax\nmov [rdx], ecx\nadd [rbp+var_4], 1\nloc_11D2:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_24]\njl short loc_1189\nmov rax, [rbp+var_30]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, int a3, __int64 a4)\n{\n int i; // [rsp+2Ch] [rbp-4h]\n\n for ( i = 0; i < a3; ++i )\n *(_DWORD *)(4LL * i + a4) = *(_DWORD *)(4LL * i + a1) - *(_DWORD *)(4LL * i + a2);\n return a4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, int a3, long long a4) {\n int i;\n for (i = 0; i < a3; ++i)\n *(uint32_t *)(4LL * i + a4) =\n *(uint32_t *)(4LL * i + a1) - *(uint32_t *)(4LL * i + a2);\n return a4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3, long long a4) {\n int i;\n for (i = 0; i < a3; ++i)\n *(uint32_t *)(4LL * i + a4) =\n *(uint32_t *)(4LL * i + a1) - *(uint32_t *)(4LL * i + a2);\n return a4;\n}" + }, + { + "index": 282, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int nums1[], int nums2[], int size, int result[]) {\n for (int i = 0; i < size; i++) {\n result[i] = nums1[i] - nums2[i];\n }\n return result;\n}", + "test": "int main() {\n\n int result1[3], result2[2], result3[2];\n\n int nums1a[] = {1, 2, 3}, nums2a[] = {4, 5, 6};\n\n int nums1b[] = {1, 2}, nums2b[] = {3, 4};\n\n int nums1c[] = {90, 120}, nums2c[] = {50, 70};\n\n\n\n assert(func0(nums1a, nums2a, 3, result1)[0] == -3 && func0(nums1a, nums2a, 3, result1)[1] == -3 && func0(nums1a, nums2a, 3, result1)[2] == -3);\n\n assert(func0(nums1b, nums2b, 2, result2)[0] == -2 && func0(nums1b, nums2b, 2, result2)[1] == -2);\n\n assert(func0(nums1c, nums2c, 2, result3)[0] == 40 && func0(nums1c, nums2c, 2, result3)[1] == 50);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rcx,%rax\ntest %edx,%edx\njle 1194 \nlea -0x1(%rdx),%ecx\nmov $0x0,%edx\nmov (%rdi,%rdx,4),%r8d\nsub (%rsi,%rdx,4),%r8d\nmov %r8d,(%rax,%rdx,4)\nmov %rdx,%r8\nadd $0x1,%rdx\ncmp %rcx,%r8\njne 117c \nretq\n", + "ida_asm": "func0:\nendbr64\nmov rax, rcx\ntest edx, edx\njle short locret_1199\nmovsxd rdx, edx\nlea r9, ds:0[rdx*4]\nmov edx, 0\nloc_1184:\nmov r8d, [rdi+rdx]\nsub r8d, [rsi+rdx]\nmov [rax+rdx], r8d\nadd rdx, 4\ncmp rdx, r9\njnz short loc_1184\nlocret_1199:\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3, __int64 a4)\n{\n __int64 result; // rax\n __int64 v5; // r9\n __int64 v6; // rdx\n\n result = a4;\n if ( a3 > 0 )\n {\n v5 = 4LL * a3;\n v6 = 0LL;\n do\n {\n *(_DWORD *)(a4 + v6) = *(_DWORD *)(a1 + v6) - *(_DWORD *)(a2 + v6);\n v6 += 4LL;\n }\n while ( v6 != v5 );\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov rax, rcx\ntest edx, edx\njle short locret_1199\nmovsxd rdx, edx\nlea r9, ds:0[rdx*4]\nmov edx, 0\nloc_1184:\nmov r8d, [rdi+rdx]\nsub r8d, [rsi+rdx]\nmov [rax+rdx], r8d\nadd rdx, 4\ncmp rdx, r9\njnz short loc_1184\nlocret_1199:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, int a3, __int64 a4)\n{\n __int64 result; // rax\n __int64 v5; // r9\n __int64 v6; // rdx\n\n result = a4;\n if ( a3 > 0 )\n {\n v5 = 4LL * a3;\n v6 = 0LL;\n do\n {\n *(_DWORD *)(a4 + v6) = *(_DWORD *)(a1 + v6) - *(_DWORD *)(a2 + v6);\n v6 += 4LL;\n }\n while ( v6 != v5 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, int a3, long long a4) {\n long long result;\n long long v5;\n long long v6;\n result = a4;\n if (a3 > 0) {\n v5 = 4LL * a3;\n v6 = 0LL;\n do {\n *(uint32_t *)(a4 + v6) = *(uint32_t *)(a1 + v6) - *(uint32_t *)(a2 + v6);\n v6 += 4LL;\n } while (v6 != v5);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3, long long a4) {\n long long result;\n long long v5;\n long long v6;\n result = a4;\n if (a3 > 0) {\n v5 = 4LL * a3;\n v6 = 0LL;\n do {\n *(uint32_t *)(a4 + v6) = *(uint32_t *)(a1 + v6) - *(uint32_t *)(a2 + v6);\n v6 += 4LL;\n } while (v6 != v5);\n }\n return result;\n}" + }, + { + "index": 283, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int n) {\n int i, temp, count;\n for (i = 0; i < 10; i++) {\n temp = n;\n count = 0;\n while (temp > 0) {\n if (temp % 10 == i) {\n count++;\n }\n if (count > i) {\n return false;\n }\n temp /= 10;\n }\n }\n return true;\n}", + "test": "int main() {\n\n assert(func0(1234) == true);\n\n assert(func0(51241) == false);\n\n assert(func0(321) == true);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 11d6 \nmov -0x14(%rbp),%eax\nmov %eax,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11cc \nmov -0x8(%rbp),%ecx\nmovslq %ecx,%rax\nimul $0x66666667,%rax,%rax\nshr $0x20,%rax\nmov %eax,%edx\nsar $0x2,%edx\nmov %ecx,%eax\nsar $0x1f,%eax\nsub %eax,%edx\nmov %edx,%eax\nshl $0x2,%eax\nadd %edx,%eax\nadd %eax,%eax\nsub %eax,%ecx\nmov %ecx,%edx\ncmp %edx,-0xc(%rbp)\njne 119f \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0xc(%rbp),%eax\njle 11ae \nmov $0x0,%eax\njmp 11e1 \nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nimul $0x66666667,%rdx,%rdx\nshr $0x20,%rdx\nsar $0x2,%edx\nsar $0x1f,%eax\nsub %eax,%edx\nmov %edx,%eax\nmov %eax,-0x8(%rbp)\ncmpl $0x0,-0x8(%rbp)\njg 116c \naddl $0x1,-0xc(%rbp)\ncmpl $0x9,-0xc(%rbp)\njle 115d \nmov $0x1,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_C], 0\njmp short loc_11D6\nloc_115D:\nmov eax, [rbp+var_14]\nmov [rbp+var_8], eax\nmov [rbp+var_4], 0\njmp short loc_11CC\nloc_116C:\nmov ecx, [rbp+var_8]\nmovsxd rax, ecx\nimul rax, 66666667h\nshr rax, 20h\nmov edx, eax\nsar edx, 2\nmov eax, ecx\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nsub ecx, eax\nmov edx, ecx\ncmp [rbp+var_C], edx\njnz short loc_119F\nadd [rbp+var_4], 1\nloc_119F:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_C]\njle short loc_11AE\nmov eax, 0\njmp short loc_11E1\nloc_11AE:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_8], eax\nloc_11CC:\ncmp [rbp+var_8], 0\njg short loc_116C\nadd [rbp+var_C], 1\nloc_11D6:\ncmp [rbp+var_C], 9\njle short loc_115D\nmov eax, 1\nloc_11E1:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int i; // [rsp+8h] [rbp-Ch]\n int v3; // [rsp+Ch] [rbp-8h]\n int v4; // [rsp+10h] [rbp-4h]\n\n for ( i = 0; i <= 9; ++i )\n {\n v3 = a1;\n v4 = 0;\n while ( v3 > 0 )\n {\n if ( i == v3 % 10 )\n ++v4;\n if ( v4 > i )\n return 0LL;\n v3 /= 10;\n }\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_C], 0\njmp short loc_11D6\nloc_115D:\nmov eax, [rbp+var_14]\nmov [rbp+var_8], eax\nmov [rbp+var_4], 0\njmp short loc_11CC\nloc_116C:\nmov ecx, [rbp+var_8]\nmovsxd rax, ecx\nimul rax, 66666667h\nshr rax, 20h\nmov edx, eax\nsar edx, 2\nmov eax, ecx\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nsub ecx, eax\nmov edx, ecx\ncmp [rbp+var_C], edx\njnz short loc_119F\nadd [rbp+var_4], 1\nloc_119F:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_C]\njle short loc_11AE\nmov eax, 0\njmp short loc_11E1\nloc_11AE:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_8], eax\nloc_11CC:\ncmp [rbp+var_8], 0\njg short loc_116C\nadd [rbp+var_C], 1\nloc_11D6:\ncmp [rbp+var_C], 9\njle short loc_115D\nmov eax, 1\nloc_11E1:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int i; // [rsp+8h] [rbp-Ch]\n int v3; // [rsp+Ch] [rbp-8h]\n int v4; // [rsp+10h] [rbp-4h]\n\n for ( i = 0; i <= 9; ++i )\n {\n v3 = a1;\n v4 = 0;\n while ( v3 > 0 )\n {\n if ( i == v3 % 10 )\n ++v4;\n if ( v4 > i )\n return 0LL;\n v3 /= 10;\n }\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int i;\n int v3;\n int v4;\n for (i = 0; i <= 9; ++i) {\n v3 = a1;\n v4 = 0;\n while (v3 > 0) {\n if (i == v3 % 10) ++v4;\n if (v4 > i) return 0LL;\n v3 /= 10;\n }\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int i;\n int v3;\n int v4;\n for (i = 0; i <= 9; ++i) {\n v3 = a1;\n v4 = 0;\n while (v3 > 0) {\n if (i == v3 % 10) ++v4;\n if (v4 > i) return 0LL;\n v3 /= 10;\n }\n }\n return 1LL;\n}" + }, + { + "index": 283, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int n) {\n int i, temp, count;\n for (i = 0; i < 10; i++) {\n temp = n;\n count = 0;\n while (temp > 0) {\n if (temp % 10 == i) {\n count++;\n }\n if (count > i) {\n return false;\n }\n temp /= 10;\n }\n }\n return true;\n}", + "test": "int main() {\n\n assert(func0(1234) == true);\n\n assert(func0(51241) == false);\n\n assert(func0(321) == true);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x0,%esi\nmov %edi,%r8d\nmov %r8d,%edx\nmov $0x0,%ecx\ntest %edi,%edi\njg 1165 \njmp 11b4 \nmov %eax,%edx\nmovslq %edx,%rax\nimul $0x66666667,%rax,%rax\nsar $0x22,%rax\nmov %edx,%r9d\nsar $0x1f,%r9d\nsub %r9d,%eax\nlea (%rax,%rax,4),%eax\nadd %eax,%eax\nmov %edx,%r10d\nsub %eax,%r10d\ncmp %esi,%r10d\nsete %al\nmovzbl %al,%eax\nadd %eax,%ecx\ncmp %esi,%ecx\njg 11c2 \nmovslq %edx,%rax\nimul $0x66666667,%rax,%rax\nsar $0x22,%rax\nmov %edx,%r9d\nsar $0x1f,%r9d\nsub %r9d,%eax\ncmp $0x9,%edx\njg 1163 \nadd $0x1,%esi\ncmp $0xa,%esi\njne 1155 \nmov $0x1,%eax\nretq\nmov $0x0,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov esi, 0\nloc_1152:\nmov edx, edi\nmov ecx, 0\ntest edi, edi\njg short loc_1161\njmp short loc_11B0\nloc_115F:\nmov edx, eax\nloc_1161:\nmovsxd rax, edx\nimul rax, 66666667h\nsar rax, 22h\nmov r8d, edx\nsar r8d, 1Fh\nsub eax, r8d\nlea eax, [rax+rax*4]\nadd eax, eax\nmov r8d, edx\nsub r8d, eax\ncmp r8d, esi\nsetz al\nmovzx eax, al\nadd ecx, eax\ncmp ecx, esi\njg short loc_11BE\nmovsxd rax, edx\nimul rax, 66666667h\nsar rax, 22h\nmov r8d, edx\nsar r8d, 1Fh\nsub eax, r8d\ncmp edx, 9\njg short loc_115F\nloc_11B0:\nadd esi, 1\ncmp esi, 0Ah\njnz short loc_1152\nmov eax, 1\nretn\nloc_11BE:\nmov eax, 0\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // esi\n int v2; // edx\n int v3; // ecx\n\n v1 = 0;\n while ( 1 )\n {\n v2 = a1;\n v3 = 0;\n if ( a1 > 0 )\n break;\nLABEL_7:\n if ( ++v1 == 10 )\n return 1LL;\n }\n while ( 1 )\n {\n v3 += v2 % 10 == v1;\n if ( v3 > v1 )\n return 0LL;\n if ( v2 <= 9 )\n goto LABEL_7;\n v2 /= 10;\n }\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmov esi, 0\nloc_1152:\nmov edx, edi\nmov ecx, 0\ntest edi, edi\njg short loc_1161\njmp short loc_11B0\nloc_115F:\nmov edx, eax\nloc_1161:\nmovsxd rax, edx\nimul rax, 66666667h\nsar rax, 22h\nmov r8d, edx\nsar r8d, 1Fh\nsub eax, r8d\nlea eax, [rax+rax*4]\nadd eax, eax\nmov r8d, edx\nsub r8d, eax\ncmp r8d, esi\nsetz al\nmovzx eax, al\nadd ecx, eax\ncmp ecx, esi\njg short loc_11BE\nmovsxd rax, edx\nimul rax, 66666667h\nsar rax, 22h\nmov r8d, edx\nsar r8d, 1Fh\nsub eax, r8d\ncmp edx, 9\njg short loc_115F\nloc_11B0:\nadd esi, 1\ncmp esi, 0Ah\njnz short loc_1152\nmov eax, 1\nretn\nloc_11BE:\nmov eax, 0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v1; // esi\n int v2; // edx\n int v3; // ecx\n\n v1 = 0;\n while ( 1 )\n {\n v2 = a1;\n v3 = 0;\n if ( a1 > 0 )\n break;\nLABEL_7:\n if ( ++v1 == 10 )\n return 1LL;\n }\n while ( 1 )\n {\n v3 += v2 % 10 == v1;\n if ( v3 > v1 )\n return 0LL;\n if ( v2 <= 9 )\n goto LABEL_7;\n v2 /= 10;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v1;\n int v2;\n int v3;\n v1 = 0;\n while (1) {\n v2 = a1;\n v3 = 0;\n if (a1 > 0) break;\n LABEL_7:\n if (++v1 == 10) return 1LL;\n }\n while (1) {\n v3 += v2 % 10 == v1;\n if (v3 > v1) return 0LL;\n if (v2 <= 9) goto LABEL_7;\n v2 /= 10;\n }\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v2;\n int v3;\n v1 = 0;\n while (1) {\n v2 = a1;\n v3 = 0;\n if (a1 > 0) break;\n LABEL_7:\n if (++v1 == 10) return 1LL;\n }\n while (1) {\n v3 += v2 % 10 == v1;\n if (v3 > v1) return 0LL;\n if (v2 <= 9) goto LABEL_7;\n v2 /= 10;\n }\n}" + }, + { + "index": 283, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int n) {\n int i, temp, count;\n for (i = 0; i < 10; i++) {\n temp = n;\n count = 0;\n while (temp > 0) {\n if (temp % 10 == i) {\n count++;\n }\n if (count > i) {\n return false;\n }\n temp /= 10;\n }\n }\n return true;\n}", + "test": "int main() {\n\n assert(func0(1234) == true);\n\n assert(func0(51241) == false);\n\n assert(func0(321) == true);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nxor %r8d,%r8d\nmov $0xcccccccd,%r9d\nmov %edi,%ecx\nxor %esi,%esi\ntest %edi,%edi\njg 12f7 \njmp 1320 \nnopw 0x0(%rax,%rax,1)\ncmp $0x9,%ecx\njle 1320 \nmov %eax,%ecx\nmov %ecx,%eax\nmov %ecx,%r10d\nimul %r9,%rax\nshr $0x23,%rax\nlea (%rax,%rax,4),%edx\nadd %edx,%edx\nsub %edx,%r10d\ncmp %r8d,%r10d\nsete %dl\nmovzbl %dl,%edx\nadd %edx,%esi\ncmp %r8d,%esi\njle 12f0 \nxor %eax,%eax\nretq\nadd $0x1,%r8d\ncmp $0xa,%r8d\njne 12dd \nmov $0x1,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nxor r8d, r8d\nloc_11F7:\ntest edi, edi\njle short loc_1250\nmov r10d, 0CCCCCCCDh\nloc_1201:\nmov ecx, edi\nxor esi, esi\njmp short loc_1217\nloc_1210:\ncmp ecx, 9\njle short loc_1240\nmov ecx, eax\nloc_1217:\nmov eax, ecx\nmov r9d, ecx\nimul rax, r10\nshr rax, 23h\nlea edx, [rax+rax*4]\nadd edx, edx\nsub r9d, edx\nxor edx, edx\ncmp r9d, r8d\nsetz dl\nadd esi, edx\ncmp r8d, esi\njge short loc_1210\nxor eax, eax\nretn\nloc_1240:\nadd r8d, 1\ncmp r8d, 0Ah\njnz short loc_1201\nloc_124A:\nmov eax, 1\nretn\nloc_1250:\nadd r8d, 1\ncmp r8d, 0Ah\njnz short loc_11F7\njmp short loc_124A", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // r8d\n int v2; // ecx\n int v3; // esi\n\n v1 = 0;\n while ( a1 <= 0 )\n {\n if ( ++v1 == 10 )\n return 1LL;\n }\n do\n {\n v2 = a1;\n v3 = 0;\n while ( 1 )\n {\n v3 += v2 % 0xAu == v1;\n if ( v1 < v3 )\n return 0LL;\n if ( v2 <= 9 )\n break;\n v2 /= 0xAu;\n }\n ++v1;\n }\n while ( v1 != 10 );\n return 1LL;\n}", + "ida_strip_asm": "sub_11F0:\nendbr64\nxor r8d, r8d\nloc_11F7:\ntest edi, edi\njle short loc_1250\nmov r10d, 0CCCCCCCDh\nloc_1201:\nmov ecx, edi\nxor esi, esi\njmp short loc_1217\nloc_1210:\ncmp ecx, 9\njle short loc_1240\nmov ecx, eax\nloc_1217:\nmov eax, ecx\nmov r9d, ecx\nimul rax, r10\nshr rax, 23h\nlea edx, [rax+rax*4]\nadd edx, edx\nsub r9d, edx\nxor edx, edx\ncmp r9d, r8d\nsetz dl\nadd esi, edx\ncmp r8d, esi\njge short loc_1210\nxor eax, eax\nretn\nloc_1240:\nadd r8d, 1\ncmp r8d, 0Ah\njnz short loc_1201\nloc_124A:\nmov eax, 1\nretn\nloc_1250:\nadd r8d, 1\ncmp r8d, 0Ah\njnz short loc_11F7\njmp short loc_124A", + "ida_strip_pseudo": "__int64 __fastcall sub_11F0(int a1)\n{\n int v1; // r8d\n int v2; // ecx\n int v3; // esi\n\n v1 = 0;\n while ( a1 <= 0 )\n {\n if ( ++v1 == 10 )\n return 1LL;\n }\n do\n {\n v2 = a1;\n v3 = 0;\n while ( 1 )\n {\n v3 += v2 % 0xAu == v1;\n if ( v1 < v3 )\n return 0LL;\n if ( v2 <= 9 )\n break;\n v2 /= 0xAu;\n }\n ++v1;\n }\n while ( v1 != 10 );\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11F0(int a1) {\n int v1;\n int v2;\n int v3;\n v1 = 0;\n while (a1 <= 0) {\n if (++v1 == 10) return 1LL;\n }\n do {\n v2 = a1;\n v3 = 0;\n while (1) {\n v3 += v2 % 10u == v1;\n if (v1 < v3) return 0LL;\n if (v2 <= 9) break;\n v2 /= 10u;\n }\n ++v1;\n } while (v1 != 10);\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v2;\n int v3;\n v1 = 0;\n while (a1 <= 0) {\n if (++v1 == 10) return 1LL;\n }\n do {\n v2 = a1;\n v3 = 0;\n while (1) {\n v3 += v2 % 10u == v1;\n if (v1 < v3) return 0LL;\n if (v2 <= 9) break;\n v2 /= 10u;\n }\n ++v1;\n } while (v1 != 10);\n return 1LL;\n}" + }, + { + "index": 284, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef enum { INT_TYPE, STRING_TYPE } ElementType;\n\n\n\ntypedef struct {\n\n ElementType type;\n\n union {\n\n int int_val;\n\n const char* str_val;\n\n } value;\n\n} Element;\n\n\n\n", + "func": "bool func0(Element list[], int size, Element element) {\n for (int i = 0; i < size; i++) {\n if (list[i].type != element.type) {\n return false;\n }\n if (element.type == INT_TYPE) {\n if (list[i].value.int_val != element.value.int_val) {\n return false;\n }\n } else if (element.type == STRING_TYPE) {\n if (strcmp(list[i].value.str_val, element.value.str_val) != 0) {\n return false;\n }\n }\n }\n return true;\n}", + "test": "int main() {\n\n Element list1[] = {\n\n {STRING_TYPE, .value.str_val = \"green\"},\n\n {STRING_TYPE, .value.str_val = \"orange\"},\n\n {STRING_TYPE, .value.str_val = \"black\"},\n\n {STRING_TYPE, .value.str_val = \"white\"}\n\n };\n\n Element element1 = {STRING_TYPE, .value.str_val = \"blue\"};\n\n assert(func0(list1, 4, element1) == false);\n\n \n\n Element list2[] = {\n\n {INT_TYPE, .value.int_val = 1},\n\n {INT_TYPE, .value.int_val = 2},\n\n {INT_TYPE, .value.int_val = 3},\n\n {INT_TYPE, .value.int_val = 4}\n\n };\n\n Element element2 = {INT_TYPE, .value.int_val = 7};\n\n assert(func0(list2, 4, element2) == false);\n\n \n\n Element list3[] = {\n\n {STRING_TYPE, .value.str_val = \"green\"},\n\n {STRING_TYPE, .value.str_val = \"green\"},\n\n {STRING_TYPE, .value.str_val = \"green\"},\n\n {STRING_TYPE, .value.str_val = \"green\"}\n\n };\n\n Element element3 = {STRING_TYPE, .value.str_val = \"green\"};\n\n assert(func0(list3, 4, element3) == true);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,%eax\nmov %rcx,%rdx\nmov %rax,-0x30(%rbp)\nmov %rdx,-0x28(%rbp)\nmovl $0x0,-0x4(%rbp)\njmpq 1240 \nmov -0x4(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x30(%rbp),%eax\ncmp %eax,%edx\nje 11d8 \nmov $0x0,%eax\njmp 1251 \nmov -0x30(%rbp),%eax\ntest %eax,%eax\njne 1203 \nmov -0x4(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov 0x8(%rax),%edx\nmov -0x28(%rbp),%eax\ncmp %eax,%edx\nje 123c \nmov $0x0,%eax\njmp 1251 \nmov -0x30(%rbp),%eax\ncmp $0x1,%eax\njne 123c \nmov -0x28(%rbp),%rdx\nmov -0x4(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov 0x8(%rax),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1090 \ntest %eax,%eax\nje 123c \nmov $0x0,%eax\njmp 1251 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11b5 \nmov $0x1,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov eax, edx\nmov rdx, rcx\nmov [rbp+var_30], rax\nmov [rbp+s2], rdx\nmov [rbp+var_4], 0\njmp loc_1240\nloc_11B5:\nmov eax, [rbp+var_4]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, dword ptr [rbp+var_30]\ncmp edx, eax\njz short loc_11D8\nmov eax, 0\njmp short locret_1251\nloc_11D8:\nmov eax, dword ptr [rbp+var_30]\ntest eax, eax\njnz short loc_1203\nmov eax, [rbp+var_4]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax+8]\nmov eax, dword ptr [rbp+s2]\ncmp edx, eax\njz short loc_123C\nmov eax, 0\njmp short locret_1251\nloc_1203:\nmov eax, dword ptr [rbp+var_30]\ncmp eax, 1\njnz short loc_123C\nmov rdx, [rbp+s2]\nmov eax, [rbp+var_4]\ncdqe\nshl rax, 4\nmov rcx, rax\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov rax, [rax+8]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_123C\nmov eax, 0\njmp short locret_1251\nloc_123C:\nadd [rbp+var_4], 1\nloc_1240:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl loc_11B5\nmov eax, 1\nlocret_1251:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3, const char *a4)\n{\n int i; // [rsp+2Ch] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n if ( *(_DWORD *)(16LL * i + a1) != a3 )\n return 0LL;\n if ( a3 )\n {\n if ( a3 == 1 && strcmp(*(const char **)(16LL * i + a1 + 8), a4) )\n return 0LL;\n }\n else if ( *(_DWORD *)(16LL * i + a1 + 8) != (_DWORD)a4 )\n {\n return 0LL;\n }\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov eax, edx\nmov rdx, rcx\nmov [rbp+var_30], rax\nmov [rbp+s2], rdx\nmov [rbp+var_4], 0\njmp loc_1240\nloc_11B5:\nmov eax, [rbp+var_4]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, dword ptr [rbp+var_30]\ncmp edx, eax\njz short loc_11D8\nmov eax, 0\njmp short locret_1251\nloc_11D8:\nmov eax, dword ptr [rbp+var_30]\ntest eax, eax\njnz short loc_1203\nmov eax, [rbp+var_4]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax+8]\nmov eax, dword ptr [rbp+s2]\ncmp edx, eax\njz short loc_123C\nmov eax, 0\njmp short locret_1251\nloc_1203:\nmov eax, dword ptr [rbp+var_30]\ncmp eax, 1\njnz short loc_123C\nmov rdx, [rbp+s2]\nmov eax, [rbp+var_4]\ncdqe\nshl rax, 4\nmov rcx, rax\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov rax, [rax+8]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_123C\nmov eax, 0\njmp short locret_1251\nloc_123C:\nadd [rbp+var_4], 1\nloc_1240:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl loc_11B5\nmov eax, 1\nlocret_1251:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2, int a3, const char *a4)\n{\n int i; // [rsp+2Ch] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n if ( *(_DWORD *)(16LL * i + a1) != a3 )\n return 0LL;\n if ( a3 )\n {\n if ( a3 == 1 && strcmp(*(const char **)(16LL * i + a1 + 8), a4) )\n return 0LL;\n }\n else if ( *(_DWORD *)(16LL * i + a1 + 8) != (_DWORD)a4 )\n {\n return 0LL;\n }\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2, int a3, const char *a4) {\n int i;\n for (i = 0; i < a2; ++i) {\n if (*(uint32_t *)(16LL * i + a1) != a3) return 0LL;\n if (a3) {\n if (a3 == 1 && strcmp(*(const char **)(16LL * i + a1 + 8), a4))\n return 0LL;\n } else if (*(uint32_t *)(16LL * i + a1 + 8) != (uint32_t)a4) {\n return 0LL;\n }\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3, const char *a4) {\n int i;\n for (i = 0; i < a2; ++i) {\n if (*(uint32_t *)(16LL * i + a1) != a3) return 0LL;\n if (a3) {\n if (a3 == 1 && strcmp(*(const char **)(16LL * i + a1 + 8), a4))\n return 0LL;\n } else if (*(uint32_t *)(16LL * i + a1 + 8) != (uint32_t)a4) {\n return 0LL;\n }\n }\n return 1LL;\n}" + }, + { + "index": 284, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef enum { INT_TYPE, STRING_TYPE } ElementType;\n\n\n\ntypedef struct {\n\n ElementType type;\n\n union {\n\n int int_val;\n\n const char* str_val;\n\n } value;\n\n} Element;\n\n\n\n", + "func": "bool func0(Element list[], int size, Element element) {\n for (int i = 0; i < size; i++) {\n if (list[i].type != element.type) {\n return false;\n }\n if (element.type == INT_TYPE) {\n if (list[i].value.int_val != element.value.int_val) {\n return false;\n }\n } else if (element.type == STRING_TYPE) {\n if (strcmp(list[i].value.str_val, element.value.str_val) != 0) {\n return false;\n }\n }\n }\n return true;\n}", + "test": "int main() {\n\n Element list1[] = {\n\n {STRING_TYPE, .value.str_val = \"green\"},\n\n {STRING_TYPE, .value.str_val = \"orange\"},\n\n {STRING_TYPE, .value.str_val = \"black\"},\n\n {STRING_TYPE, .value.str_val = \"white\"}\n\n };\n\n Element element1 = {STRING_TYPE, .value.str_val = \"blue\"};\n\n assert(func0(list1, 4, element1) == false);\n\n \n\n Element list2[] = {\n\n {INT_TYPE, .value.int_val = 1},\n\n {INT_TYPE, .value.int_val = 2},\n\n {INT_TYPE, .value.int_val = 3},\n\n {INT_TYPE, .value.int_val = 4}\n\n };\n\n Element element2 = {INT_TYPE, .value.int_val = 7};\n\n assert(func0(list2, 4, element2) == false);\n\n \n\n Element list3[] = {\n\n {STRING_TYPE, .value.str_val = \"green\"},\n\n {STRING_TYPE, .value.str_val = \"green\"},\n\n {STRING_TYPE, .value.str_val = \"green\"},\n\n {STRING_TYPE, .value.str_val = \"green\"}\n\n };\n\n Element element3 = {STRING_TYPE, .value.str_val = \"green\"};\n\n assert(func0(list3, 4, element3) == true);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11f3 \npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %rcx,%r13\nmov %edx,%ebp\nmov %rcx,%r14\nlea 0x8(%rdi),%rbx\nlea -0x1(%rsi),%eax\nshl $0x4,%rax\nlea 0x18(%rdi,%rax,1),%r12\njmp 11c1 \ncmp $0x1,%ebp\nje 11d6 \nadd $0x10,%rbx\ncmp %r12,%rbx\nje 11ec \ncmp %ebp,-0x8(%rbx)\njne 11f9 \ntest %ebp,%ebp\njne 11b3 \ncmp %r13d,(%rbx)\nje 11b8 \nmov $0x0,%eax\njmp 11fe \nmov %r14,%rsi\nmov (%rbx),%rdi\ncallq 1090 \ntest %eax,%eax\nje 11b8 \nmov $0x0,%eax\njmp 11fe \nmov $0x1,%eax\njmp 11fe \nmov $0x1,%eax\nretq\nmov $0x0,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11F2\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r14, rcx\nmov ebp, edx\nmov r13d, ecx\nmov rbx, rdi\nmovsxd rsi, esi\nshl rsi, 4\nlea r12, [rdi+rsi]\njmp short loc_11BF\nloc_11B1:\ncmp ebp, 1\njz short loc_11D4\nloc_11B6:\nadd rbx, 10h\ncmp rbx, r12\njz short loc_11EB\nloc_11BF:\ncmp [rbx], ebp\njnz short loc_11F8\ntest ebp, ebp\njnz short loc_11B1\ncmp [rbx+8], r13d\njz short loc_11B6\nmov eax, 0\njmp short loc_11FD\nloc_11D4:\nmov rdi, [rbx+8]; s1\nmov rsi, r14; s2\ncall _strcmp\ntest eax, eax\njz short loc_11B6\nmov eax, 0\njmp short loc_11FD\nloc_11EB:\nmov eax, 1\njmp short loc_11FD\nloc_11F2:\nmov eax, 1\nretn\nloc_11F8:\nmov eax, 0\nloc_11FD:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3, const char *a4)\n{\n int v6; // r13d\n __int64 v7; // rbx\n\n if ( a2 <= 0 )\n return 1LL;\n v6 = (int)a4;\n v7 = a1;\n while ( *(_DWORD *)v7 == a3 )\n {\n if ( a3 )\n {\n if ( a3 == 1 && strcmp(*(const char **)(v7 + 8), a4) )\n return 0LL;\n }\n else if ( *(_DWORD *)(v7 + 8) != v6 )\n {\n return 0LL;\n }\n v7 += 16LL;\n if ( v7 == a1 + 16LL * a2 )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\ntest esi, esi\njle short loc_11F2\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r14, rcx\nmov ebp, edx\nmov r13d, ecx\nmov rbx, rdi\nmovsxd rsi, esi\nshl rsi, 4\nlea r12, [rdi+rsi]\njmp short loc_11BF\nloc_11B1:\ncmp ebp, 1\njz short loc_11D4\nloc_11B6:\nadd rbx, 10h\ncmp rbx, r12\njz short loc_11EB\nloc_11BF:\ncmp [rbx], ebp\njnz short loc_11F8\ntest ebp, ebp\njnz short loc_11B1\ncmp [rbx+8], r13d\njz short loc_11B6\nmov eax, 0\njmp short loc_11FD\nloc_11D4:\nmov rdi, [rbx+8]; s1\nmov rsi, r14; s2\ncall _strcmp\ntest eax, eax\njz short loc_11B6\nmov eax, 0\njmp short loc_11FD\nloc_11EB:\nmov eax, 1\njmp short loc_11FD\nloc_11F2:\nmov eax, 1\nretn\nloc_11F8:\nmov eax, 0\nloc_11FD:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2, int a3, const char *a4)\n{\n int v6; // r13d\n __int64 v7; // rbx\n\n if ( a2 <= 0 )\n return 1LL;\n v6 = (int)a4;\n v7 = a1;\n while ( *(_DWORD *)v7 == a3 )\n {\n if ( a3 )\n {\n if ( a3 == 1 && strcmp(*(const char **)(v7 + 8), a4) )\n return 0LL;\n }\n else if ( *(_DWORD *)(v7 + 8) != v6 )\n {\n return 0LL;\n }\n v7 += 16LL;\n if ( v7 == a1 + 16LL * a2 )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2, int a3, const char *a4) {\n int v6;\n long long v7;\n if (a2 <= 0) return 1LL;\n v6 = (int)a4;\n v7 = a1;\n while (*(uint32_t *)v7 == a3) {\n if (a3) {\n if (a3 == 1 && strcmp(*(const char **)(v7 + 8), a4)) return 0LL;\n } else if (*(uint32_t *)(v7 + 8) != v6) {\n return 0LL;\n }\n v7 += 16LL;\n if (v7 == a1 + 16LL * a2) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3, const char *a4) {\n int v6;\n long long v7;\n if (a2 <= 0) return 1LL;\n v6 = (int)a4;\n v7 = a1;\n while (*(uint32_t *)v7 == a3) {\n if (a3) {\n if (a3 == 1 && strcmp(*(const char **)(v7 + 8), a4)) return 0LL;\n } else if (*(uint32_t *)(v7 + 8) != v6) {\n return 0LL;\n }\n v7 += 16LL;\n if (v7 == a1 + 16LL * a2) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 284, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef enum { INT_TYPE, STRING_TYPE } ElementType;\n\n\n\ntypedef struct {\n\n ElementType type;\n\n union {\n\n int int_val;\n\n const char* str_val;\n\n } value;\n\n} Element;\n\n\n\n", + "func": "bool func0(Element list[], int size, Element element) {\n for (int i = 0; i < size; i++) {\n if (list[i].type != element.type) {\n return false;\n }\n if (element.type == INT_TYPE) {\n if (list[i].value.int_val != element.value.int_val) {\n return false;\n }\n } else if (element.type == STRING_TYPE) {\n if (strcmp(list[i].value.str_val, element.value.str_val) != 0) {\n return false;\n }\n }\n }\n return true;\n}", + "test": "int main() {\n\n Element list1[] = {\n\n {STRING_TYPE, .value.str_val = \"green\"},\n\n {STRING_TYPE, .value.str_val = \"orange\"},\n\n {STRING_TYPE, .value.str_val = \"black\"},\n\n {STRING_TYPE, .value.str_val = \"white\"}\n\n };\n\n Element element1 = {STRING_TYPE, .value.str_val = \"blue\"};\n\n assert(func0(list1, 4, element1) == false);\n\n \n\n Element list2[] = {\n\n {INT_TYPE, .value.int_val = 1},\n\n {INT_TYPE, .value.int_val = 2},\n\n {INT_TYPE, .value.int_val = 3},\n\n {INT_TYPE, .value.int_val = 4}\n\n };\n\n Element element2 = {INT_TYPE, .value.int_val = 7};\n\n assert(func0(list2, 4, element2) == false);\n\n \n\n Element list3[] = {\n\n {STRING_TYPE, .value.str_val = \"green\"},\n\n {STRING_TYPE, .value.str_val = \"green\"},\n\n {STRING_TYPE, .value.str_val = \"green\"},\n\n {STRING_TYPE, .value.str_val = \"green\"}\n\n };\n\n Element element3 = {STRING_TYPE, .value.str_val = \"green\"};\n\n assert(func0(list3, 4, element3) == true);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 13ee \nlea -0x1(%rsi),%eax\npush %r14\nmov %rcx,%r14\nshl $0x4,%rax\npush %r13\nmov %ecx,%r13d\npush %r12\nlea 0x18(%rdi,%rax,1),%r12\npush %rbp\nmov %edx,%ebp\npush %rbx\nlea 0x8(%rdi),%rbx\njmp 13ae \nnopw 0x0(%rax,%rax,1)\ncmp %r13d,(%rbx)\njne 13cb \nadd $0x10,%rbx\ncmp %r12,%rbx\nje 13e0 \ncmp %ebp,-0x8(%rbx)\njne 13cb \ntest %ebp,%ebp\nje 13a0 \ncmp $0x1,%ebp\njne 13a5 \nmov (%rbx),%rdi\nmov %r14,%rsi\ncallq 1090 \ntest %eax,%eax\nje 13a5 \npop %rbx\nxor %eax,%eax\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopw %cs:0x0(%rax,%rax,1)\npop %rbx\nmov $0x1,%eax\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nmov $0x1,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle loc_1412\nmovsxd rsi, esi\nmov rax, rdi\npush r12\nmov edi, ecx\nshl rsi, 4\npush rbp\nmov r12, rcx\npush rbx\nlea rbp, [rsi+rax]\nmov rbx, rax\ncmp [rax], edx\njnz short loc_13AF\nmov ecx, edx\ntest edx, edx\njz short loc_13AA\njmp short loc_13C0\nloc_1398:\nadd rbx, 10h\ncmp rbp, rbx\njz short loc_1408\nmov edx, [rbx]\nmov rax, rbx\ntest edx, edx\njnz short loc_13AF\nloc_13AA:\ncmp [rax+8], edi\njz short loc_1398\nloc_13AF:\npop rbx\nxor eax, eax\npop rbp\npop r12\nretn\nloc_13C0:\ncmp ecx, 1\njz short loc_13F1\nadd rbx, 10h\ncmp rbx, rbp\njz short loc_1408\nmov rax, rbx\ncmp ecx, [rbx]\njz short loc_13C0\njmp short loc_13AF\nloc_13E0:\nadd rbx, 10h\ncmp rbx, rbp\njz short loc_1408\ncmp dword ptr [rbx], 1\nmov rax, rbx\njnz short loc_13AF\nloc_13F1:\nmov rdi, [rax+8]; s1\nmov rsi, r12; s2\ncall _strcmp\ntest eax, eax\njz short loc_13E0\njmp short loc_13AF\nloc_1408:\npop rbx\nmov eax, 1\npop rbp\npop r12\nretn\nloc_1412:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char **a1, int a2, int a3, const char *a4)\n{\n const char **v4; // rax\n const char **v6; // rbp\n const char **v7; // rbx\n\n if ( a2 <= 0 )\n return 1LL;\n v4 = a1;\n v6 = &a1[2 * a2];\n v7 = a1;\n if ( *(_DWORD *)a1 == a3 )\n {\n if ( a3 )\n {\n while ( a3 != 1 )\n {\n v7 += 2;\n if ( v7 == v6 )\n return 1LL;\n v4 = v7;\n if ( a3 != *(_DWORD *)v7 )\n return 0LL;\n }\n do\n {\n if ( strcmp(v4[1], a4) )\n break;\n v7 += 2;\n if ( v7 == v6 )\n return 1LL;\n v4 = v7;\n }\n while ( *(_DWORD *)v7 == 1 );\n }\n else\n {\n while ( *((_DWORD *)v4 + 2) == (_DWORD)a4 )\n {\n v7 += 2;\n if ( v6 == v7 )\n return 1LL;\n v4 = v7;\n if ( *(_DWORD *)v7 )\n return 0LL;\n }\n }\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1360:\nendbr64\ntest esi, esi\njle loc_1412\nmovsxd rsi, esi\nmov rax, rdi\npush r12\nmov edi, ecx\nshl rsi, 4\npush rbp\nmov r12, rcx\npush rbx\nlea rbp, [rsi+rax]\nmov rbx, rax\ncmp [rax], edx\njnz short loc_13AF\nmov ecx, edx\ntest edx, edx\njz short loc_13AA\njmp short loc_13C0\nloc_1398:\nadd rbx, 10h\ncmp rbp, rbx\njz short loc_1408\nmov edx, [rbx]\nmov rax, rbx\ntest edx, edx\njnz short loc_13AF\nloc_13AA:\ncmp [rax+8], edi\njz short loc_1398\nloc_13AF:\npop rbx\nxor eax, eax\npop rbp\npop r12\nretn\nloc_13C0:\ncmp ecx, 1\njz short loc_13F1\nadd rbx, 10h\ncmp rbx, rbp\njz short loc_1408\nmov rax, rbx\ncmp ecx, [rbx]\njz short loc_13C0\njmp short loc_13AF\nloc_13E0:\nadd rbx, 10h\ncmp rbx, rbp\njz short loc_1408\ncmp dword ptr [rbx], 1\nmov rax, rbx\njnz short loc_13AF\nloc_13F1:\nmov rdi, [rax+8]; s1\nmov rsi, r12; s2\ncall _strcmp\ntest eax, eax\njz short loc_13E0\njmp short loc_13AF\nloc_1408:\npop rbx\nmov eax, 1\npop rbp\npop r12\nretn\nloc_1412:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1360(const char **a1, int a2, int a3, const char *a4)\n{\n const char **v4; // rax\n const char **v6; // rbp\n const char **v7; // rbx\n\n if ( a2 <= 0 )\n return 1LL;\n v4 = a1;\n v6 = &a1[2 * a2];\n v7 = a1;\n if ( *(_DWORD *)a1 == a3 )\n {\n if ( a3 )\n {\n while ( a3 != 1 )\n {\n v7 += 2;\n if ( v7 == v6 )\n return 1LL;\n v4 = v7;\n if ( a3 != *(_DWORD *)v7 )\n return 0LL;\n }\n do\n {\n if ( strcmp(v4[1], a4) )\n break;\n v7 += 2;\n if ( v7 == v6 )\n return 1LL;\n v4 = v7;\n }\n while ( *(_DWORD *)v7 == 1 );\n }\n else\n {\n while ( *((_DWORD *)v4 + 2) == (_DWORD)a4 )\n {\n v7 += 2;\n if ( v6 == v7 )\n return 1LL;\n v4 = v7;\n if ( *(_DWORD *)v7 )\n return 0LL;\n }\n }\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1360(const char **a1, int a2, int a3, const char *a4) {\n const char **v4;\n const char **v6;\n const char **v7;\n if (a2 <= 0) return 1LL;\n v4 = a1;\n v6 = &a1[2 * a2];\n v7 = a1;\n if (*(uint32_t *)a1 == a3) {\n if (a3) {\n while (a3 != 1) {\n v7 += 2;\n if (v7 == v6) return 1LL;\n v4 = v7;\n if (a3 != *(uint32_t *)v7) return 0LL;\n }\n do {\n if (strcmp(v4[1], a4)) break;\n v7 += 2;\n if (v7 == v6) return 1LL;\n v4 = v7;\n } while (*(uint32_t *)v7 == 1);\n } else {\n while (*((uint32_t *)v4 + 2) == (uint32_t)a4) {\n v7 += 2;\n if (v6 == v7) return 1LL;\n v4 = v7;\n if (*(uint32_t *)v7) return 0LL;\n }\n }\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(const char **a1, int a2, int a3, const char *a4) {\n const char **v4;\n const char **v6;\n const char **v7;\n if (a2 <= 0) return 1LL;\n v4 = a1;\n v6 = &a1[2 * a2];\n v7 = a1;\n if (*(uint32_t *)a1 == a3) {\n if (a3) {\n while (a3 != 1) {\n v7 += 2;\n if (v7 == v6) return 1LL;\n v4 = v7;\n if (a3 != *(uint32_t *)v7) return 0LL;\n }\n do {\n if (strcmp(v4[1], a4)) break;\n v7 += 2;\n if (v7 == v6) return 1LL;\n v4 = v7;\n } while (*(uint32_t *)v7 == 1);\n } else {\n while (*((uint32_t *)v4 + 2) == (uint32_t)a4) {\n v7 += 2;\n if (v6 == v7) return 1LL;\n v4 = v7;\n if (*(uint32_t *)v7) return 0LL;\n }\n }\n }\n return 0LL;\n}" + }, + { + "index": 284, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef enum { INT_TYPE, STRING_TYPE } ElementType;\n\n\n\ntypedef struct {\n\n ElementType type;\n\n union {\n\n int int_val;\n\n const char* str_val;\n\n } value;\n\n} Element;\n\n\n\n", + "func": "bool func0(Element list[], int size, Element element) {\n for (int i = 0; i < size; i++) {\n if (list[i].type != element.type) {\n return false;\n }\n if (element.type == INT_TYPE) {\n if (list[i].value.int_val != element.value.int_val) {\n return false;\n }\n } else if (element.type == STRING_TYPE) {\n if (strcmp(list[i].value.str_val, element.value.str_val) != 0) {\n return false;\n }\n }\n }\n return true;\n}", + "test": "int main() {\n\n Element list1[] = {\n\n {STRING_TYPE, .value.str_val = \"green\"},\n\n {STRING_TYPE, .value.str_val = \"orange\"},\n\n {STRING_TYPE, .value.str_val = \"black\"},\n\n {STRING_TYPE, .value.str_val = \"white\"}\n\n };\n\n Element element1 = {STRING_TYPE, .value.str_val = \"blue\"};\n\n assert(func0(list1, 4, element1) == false);\n\n \n\n Element list2[] = {\n\n {INT_TYPE, .value.int_val = 1},\n\n {INT_TYPE, .value.int_val = 2},\n\n {INT_TYPE, .value.int_val = 3},\n\n {INT_TYPE, .value.int_val = 4}\n\n };\n\n Element element2 = {INT_TYPE, .value.int_val = 7};\n\n assert(func0(list2, 4, element2) == false);\n\n \n\n Element list3[] = {\n\n {STRING_TYPE, .value.str_val = \"green\"},\n\n {STRING_TYPE, .value.str_val = \"green\"},\n\n {STRING_TYPE, .value.str_val = \"green\"},\n\n {STRING_TYPE, .value.str_val = \"green\"}\n\n };\n\n Element element3 = {STRING_TYPE, .value.str_val = \"green\"};\n\n assert(func0(list3, 4, element3) == true);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1418 \npush %r12\npush %rbp\nmov %rcx,%rbp\npush %rbx\ncmp $0x1,%edx\nje 13e0 \nlea -0x1(%rsi),%eax\nshl $0x4,%rax\nlea 0x10(%rdi,%rax,1),%rax\ntest %edx,%edx\nje 13c6 \ncmp (%rdi),%edx\njne 13ad \nnopl 0x0(%rax)\nadd $0x10,%rdi\ncmp %rax,%rdi\nje 13d0 \ncmp (%rdi),%edx\nje 13a0 \npop %rbx\nxor %eax,%eax\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax)\ncmp 0x8(%rdi),%ecx\njne 13ad \nadd $0x10,%rdi\ncmp %rax,%rdi\nje 13d0 \nmov (%rdi),%edx\ntest %edx,%edx\nje 13b8 \njmp 13ad \nxchg %ax,%ax\npop %rbx\nmov $0x1,%eax\npop %rbp\npop %r12\nretq\nnopw 0x0(%rax,%rax,1)\nlea -0x1(%rsi),%eax\nmov %rdi,%rbx\nshl $0x4,%rax\nlea 0x10(%rdi,%rax,1),%r12\njmp 1411 \nnopl 0x0(%rax)\nmov 0x8(%rbx),%rdi\nmov %rbp,%rsi\ncallq 1090 \ntest %eax,%eax\njne 13ad \nadd $0x10,%rbx\ncmp %r12,%rbx\nje 13d0 \ncmpl $0x1,(%rbx)\nje 13f8 \njmp 13ad \nmov $0x1,%eax\nretq\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle loc_1410\npush r12\nmov r12, rcx\npush rbp\npush rbx\ntest edx, edx\njz short loc_13A8\ncmp edx, 1\njz short loc_13E0\nmovsxd rsi, esi\nmov ecx, edx\nshl rsi, 4\nlea rax, [rdi+rsi]\njmp short loc_1399\nloc_1390:\nadd rdi, 10h\ncmp rdi, rax\njz short loc_13D0\nloc_1399:\ncmp ecx, [rdi]\njz short loc_1390\nloc_139D:\npop rbx\nxor eax, eax\npop rbp\npop r12\nretn\nloc_13A8:\nmovsxd rsi, esi\nshl rsi, 4\nlea rax, [rdi+rsi]\njmp short loc_13C6\nloc_13B8:\ncmp [rdi+8], ecx\njnz short loc_139D\nadd rdi, 10h\ncmp rdi, rax\njz short loc_13D0\nloc_13C6:\nmov edx, [rdi]\ntest edx, edx\njz short loc_13B8\njmp short loc_139D\nloc_13D0:\npop rbx\nmov eax, 1\npop rbp\npop r12\nretn\nloc_13E0:\nmovsxd rsi, esi\nmov rbx, rdi\nshl rsi, 4\nlea rbp, [rdi+rsi]\njmp short loc_1409\nloc_13F0:\nmov rdi, [rbx+8]; s1\nmov rsi, r12; s2\ncall _strcmp\ntest eax, eax\njnz short loc_139D\nadd rbx, 10h\ncmp rbx, rbp\njz short loc_13D0\nloc_1409:\ncmp dword ptr [rbx], 1\njz short loc_13F0\njmp short loc_139D\nloc_1410:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char **a1, int a2, int a3, const char *a4)\n{\n const char **v5; // rax\n const char **v7; // rax\n const char **v8; // rbx\n\n if ( a2 <= 0 )\n return 1LL;\n if ( a3 )\n {\n if ( a3 == 1 )\n {\n v8 = a1;\n while ( *(_DWORD *)v8 == 1 && !strcmp(v8[1], a4) )\n {\n v8 += 2;\n if ( v8 == &a1[2 * a2] )\n return 1LL;\n }\n }\n else\n {\n v5 = &a1[2 * a2];\n while ( a3 == *(_DWORD *)a1 )\n {\n a1 += 2;\n if ( a1 == v5 )\n return 1LL;\n }\n }\n }\n else\n {\n v7 = &a1[2 * a2];\n while ( !*(_DWORD *)a1 && *((_DWORD *)a1 + 2) == (_DWORD)a4 )\n {\n a1 += 2;\n if ( a1 == v7 )\n return 1LL;\n }\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1360:\nendbr64\ntest esi, esi\njle loc_1410\npush r12\nmov r12, rcx\npush rbp\npush rbx\ntest edx, edx\njz short loc_13A8\ncmp edx, 1\njz short loc_13E0\nmovsxd rsi, esi\nmov ecx, edx\nshl rsi, 4\nlea rax, [rdi+rsi]\njmp short loc_1399\nloc_1390:\nadd rdi, 10h\ncmp rdi, rax\njz short loc_13D0\nloc_1399:\ncmp ecx, [rdi]\njz short loc_1390\nloc_139D:\npop rbx\nxor eax, eax\npop rbp\npop r12\nretn\nloc_13A8:\nmovsxd rsi, esi\nshl rsi, 4\nlea rax, [rdi+rsi]\njmp short loc_13C6\nloc_13B8:\ncmp [rdi+8], ecx\njnz short loc_139D\nadd rdi, 10h\ncmp rdi, rax\njz short loc_13D0\nloc_13C6:\nmov edx, [rdi]\ntest edx, edx\njz short loc_13B8\njmp short loc_139D\nloc_13D0:\npop rbx\nmov eax, 1\npop rbp\npop r12\nretn\nloc_13E0:\nmovsxd rsi, esi\nmov rbx, rdi\nshl rsi, 4\nlea rbp, [rdi+rsi]\njmp short loc_1409\nloc_13F0:\nmov rdi, [rbx+8]; s1\nmov rsi, r12; s2\ncall _strcmp\ntest eax, eax\njnz short loc_139D\nadd rbx, 10h\ncmp rbx, rbp\njz short loc_13D0\nloc_1409:\ncmp dword ptr [rbx], 1\njz short loc_13F0\njmp short loc_139D\nloc_1410:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1360(const char **a1, int a2, int a3, const char *a4)\n{\n const char **v5; // rax\n const char **v7; // rax\n const char **v8; // rbx\n\n if ( a2 <= 0 )\n return 1LL;\n if ( a3 )\n {\n if ( a3 == 1 )\n {\n v8 = a1;\n while ( *(_DWORD *)v8 == 1 && !strcmp(v8[1], a4) )\n {\n v8 += 2;\n if ( v8 == &a1[2 * a2] )\n return 1LL;\n }\n }\n else\n {\n v5 = &a1[2 * a2];\n while ( a3 == *(_DWORD *)a1 )\n {\n a1 += 2;\n if ( a1 == v5 )\n return 1LL;\n }\n }\n }\n else\n {\n v7 = &a1[2 * a2];\n while ( !*(_DWORD *)a1 && *((_DWORD *)a1 + 2) == (_DWORD)a4 )\n {\n a1 += 2;\n if ( a1 == v7 )\n return 1LL;\n }\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1360(const char **a1, int a2, int a3, const char *a4) {\n const char **v5;\n const char **v7;\n const char **v8;\n if (a2 <= 0) return 1LL;\n if (a3) {\n if (a3 == 1) {\n v8 = a1;\n while (*(uint32_t *)v8 == 1 && !strcmp(v8[1], a4)) {\n v8 += 2;\n if (v8 == &a1[2 * a2]) return 1LL;\n }\n } else {\n v5 = &a1[2 * a2];\n while (a3 == *(uint32_t *)a1) {\n a1 += 2;\n if (a1 == v5) return 1LL;\n }\n }\n } else {\n v7 = &a1[2 * a2];\n while (!*(uint32_t *)a1 && *((uint32_t *)a1 + 2) == (uint32_t)a4) {\n a1 += 2;\n if (a1 == v7) return 1LL;\n }\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(const char **a1, int a2, int a3, const char *a4) {\n const char **v5;\n const char **v7;\n const char **v8;\n if (a2 <= 0) return 1LL;\n if (a3) {\n if (a3 == 1) {\n v8 = a1;\n while (*(uint32_t *)v8 == 1 && !strcmp(v8[1], a4)) {\n v8 += 2;\n if (v8 == &a1[2 * a2]) return 1LL;\n }\n } else {\n v5 = &a1[2 * a2];\n while (a3 == *(uint32_t *)a1) {\n a1 += 2;\n if (a1 == v5) return 1LL;\n }\n }\n } else {\n v7 = &a1[2 * a2];\n while (!*(uint32_t *)a1 && *((uint32_t *)a1 + 2) == (uint32_t)a4) {\n a1 += 2;\n if (a1 == v7) return 1LL;\n }\n }\n return 0LL;\n}" + }, + { + "index": 285, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n regex_t regex;\n int result;\n char* match_result;\n char* pattern = \"ab{2,3}\";\n regcomp(®ex, pattern, REG_EXTENDED);\n result = regexec(®ex, text, 0, NULL, 0);\n if (result == 0) {\n match_result = \"Found a match!\";\n } else {\n match_result = \"Not matched!\";\n }\n regfree(®ex);\n return match_result;\n}", + "test": "int main() {\n\n assert(func0(\"ac\") == \"Not matched!\");\n\n assert(func0(\"dc\") == \"Not matched!\");\n\n assert(func0(\"abbbba\") == \"Found a match!\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nadd $0xffffffffffffff80,%rsp\nmov %rdi,-0x78(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0xe19(%rip),%rax\nmov %rax,-0x58(%rbp)\nmov -0x58(%rbp),%rcx\nlea -0x50(%rbp),%rax\nmov $0x1,%edx\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 10c0 \nmov -0x78(%rbp),%rsi\nlea -0x50(%rbp),%rax\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rax,%rdi\ncallq 10d0 \nmov %eax,-0x64(%rbp)\ncmpl $0x0,-0x64(%rbp)\njne 1241 \nlea 0xdd5(%rip),%rax\nmov %rax,-0x60(%rbp)\njmp 124c \nlea 0xdd7(%rip),%rax\nmov %rax,-0x60(%rbp)\nlea -0x50(%rbp),%rax\nmov %rax,%rdi\ncallq 1090 \nmov -0x60(%rbp),%rax\nmov -0x8(%rbp),%rdx\nxor %fs:0x28,%rdx\nje 1270 \ncallq 10a0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nadd rsp, 0FFFFFFFFFFFFFF80h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aAb23; \"ab{2,3}\"\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_64], eax\ncmp [rbp+var_64], 0\njnz short loc_1241\nlea rax, aFoundAMatch; \"Found a match!\"\nmov [rbp+var_60], rax\njmp short loc_124C\nloc_1241:\nlea rax, aNotMatched; \"Not matched!\"\nmov [rbp+var_60], rax\nloc_124C:\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nmov rax, [rbp+var_60]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1270\ncall ___stack_chk_fail\nlocret_1270:\nleave\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n const char *v2; // [rsp+20h] [rbp-60h]\n regex_t preg; // [rsp+30h] [rbp-50h] BYREF\n unsigned __int64 v4; // [rsp+78h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n regcomp(&preg, \"ab{2,3}\", 1);\n if ( regexec(&preg, a1, 0LL, 0LL, 0) )\n v2 = \"Not matched!\";\n else\n v2 = \"Found a match!\";\n regfree(&preg);\n return v2;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nadd rsp, 0FFFFFFFFFFFFFF80h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aAb23; \"ab{2,3}\"\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_64], eax\ncmp [rbp+var_64], 0\njnz short loc_1241\nlea rax, aFoundAMatch; \"Found a match!\"\nmov [rbp+var_60], rax\njmp short loc_124C\nloc_1241:\nlea rax, aNotMatched; \"Not matched!\"\nmov [rbp+var_60], rax\nloc_124C:\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nmov rax, [rbp+var_60]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1270\ncall ___stack_chk_fail\nlocret_1270:\nleave\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_11C9(const char *a1)\n{\n const char *v2; // [rsp+20h] [rbp-60h]\n regex_t preg; // [rsp+30h] [rbp-50h] BYREF\n unsigned __int64 v4; // [rsp+78h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n regcomp(&preg, \"ab{2,3}\", 1);\n if ( regexec(&preg, a1, 0LL, 0LL, 0) )\n v2 = \"Not matched!\";\n else\n v2 = \"Found a match!\";\n regfree(&preg);\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_11C9(const char *a1) {\n const char *v2;\n regex_t preg;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n regcomp(&preg, \"ab{2,3}\", 1);\n if (regexec(&preg, a1, 0LL, 0LL, 0))\n v2 = \"Not matched!\";\n else\n v2 = \"Found a match!\";\n regfree(&preg);\n return v2;\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n const char *v2;\n regex_t preg;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n regcomp(&preg, \"ab{2,3}\", 1);\n if (regexec(&preg, a1, 0LL, 0LL, 0))\n v2 = \"Not matched!\";\n else\n v2 = \"Found a match!\";\n regfree(&preg);\n return v2;\n}" + }, + { + "index": 285, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n regex_t regex;\n int result;\n char* match_result;\n char* pattern = \"ab{2,3}\";\n regcomp(®ex, pattern, REG_EXTENDED);\n result = regexec(®ex, text, 0, NULL, 0);\n if (result == 0) {\n match_result = \"Found a match!\";\n } else {\n match_result = \"Not matched!\";\n }\n regfree(®ex);\n return match_result;\n}", + "test": "int main() {\n\n assert(func0(\"ac\") == \"Not matched!\");\n\n assert(func0(\"dc\") == \"Not matched!\");\n\n assert(func0(\"abbbba\") == \"Found a match!\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x58,%rsp\nmov %rdi,%rbx\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%rbp\nmov $0x1,%edx\nlea 0xe2b(%rip),%rsi\nmov %rbp,%rdi\ncallq 10c0 \nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rbx,%rsi\nmov %rbp,%rdi\ncallq 10d0 \ntest %eax,%eax\nlea 0xde3(%rip),%rax\nlea 0xdeb(%rip),%rbx\ncmove %rax,%rbx\nmov %rsp,%rdi\ncallq 1090 \nmov 0x48(%rsp),%rax\nxor %fs:0x28,%rax\njne 124e \nmov %rbx,%rax\nadd $0x58,%rsp\npop %rbx\npop %rbp\nretq\ncallq 10a0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov edx, 1; cflags\nlea rsi, pattern; \"ab{2,3}\"\nmov rdi, rbp; preg\ncall _regcomp\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\ntest eax, eax\nlea rax, aNotMatched; \"Not matched!\"\nlea rdx, aFoundAMatch; \"Found a match!\"\nmov rbx, rdx\ncmovnz rbx, rax\nmov rdi, rsp; preg\ncall _regfree\nmov rax, [rsp+var_s48]\nsub rax, fs:28h\njnz short loc_1251\nmov rax, rbx\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1251:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n const char *v1; // rbx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \"ab{2,3}\", 1);\n v1 = \"Found a match!\";\n if ( regexec(&_0, string, 0LL, 0LL, 0) )\n v1 = \"Not matched!\";\n regfree(&_0);\n return v1;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov edx, 1; cflags\nlea rsi, pattern; \"ab{2,3}\"\nmov rdi, rbp; preg\ncall _regcomp\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\ntest eax, eax\nlea rax, aNotMatched; \"Not matched!\"\nlea rdx, aFoundAMatch; \"Found a match!\"\nmov rbx, rdx\ncmovnz rbx, rax\nmov rdi, rsp; preg\ncall _regfree\nmov rax, [rsp+var_s48]\nsub rax, fs:28h\njnz short loc_1251\nmov rax, rbx\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1251:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_11C9(char *string)\n{\n const char *v1; // rbx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \"ab{2,3}\", 1);\n v1 = \"Found a match!\";\n if ( regexec(&_0, string, 0LL, 0LL, 0) )\n v1 = \"Not matched!\";\n regfree(&_0);\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_11C9(char *string) {\n const char *v1;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \"ab{2,3}\", 1);\n v1 = \"Found a match!\";\n if (regexec(&_0, string, 0LL, 0LL, 0)) v1 = \"Not matched!\";\n regfree(&_0);\n return v1;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n const char *v1;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \"ab{2,3}\", 1);\n v1 = \"Found a match!\";\n if (regexec(&_0, string, 0LL, 0LL, 0)) v1 = \"Not matched!\";\n regfree(&_0);\n return v1;\n}" + }, + { + "index": 285, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n regex_t regex;\n int result;\n char* match_result;\n char* pattern = \"ab{2,3}\";\n regcomp(®ex, pattern, REG_EXTENDED);\n result = regexec(®ex, text, 0, NULL, 0);\n if (result == 0) {\n match_result = \"Found a match!\";\n } else {\n match_result = \"Not matched!\";\n }\n regfree(®ex);\n return match_result;\n}", + "test": "int main() {\n\n assert(func0(\"ac\") == \"Not matched!\");\n\n assert(func0(\"dc\") == \"Not matched!\");\n\n assert(func0(\"abbbba\") == \"Found a match!\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov $0x1,%edx\nmov %rdi,%r12\nlea 0xd8b(%rip),%rsi\npush %rbp\nsub $0x58,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%rbp\nmov %rbp,%rdi\ncallq 10c0 \nxor %r8d,%r8d\nxor %ecx,%ecx\nxor %edx,%edx\nmov %r12,%rsi\nmov %rbp,%rdi\nlea 0xd4a(%rip),%r12\ncallq 10d0 \nmov %rbp,%rdi\ntest %eax,%eax\nlea 0xd2a(%rip),%rax\ncmove %rax,%r12\ncallq 1090 \nmov 0x48(%rsp),%rax\nxor %fs:0x28,%rax\njne 12fe \nadd $0x58,%rsp\nmov %r12,%rax\npop %rbp\npop %r12\nretq\ncallq 10a0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov edx, 1; cflags\nmov rbp, rdi\nlea rsi, pattern; \"ab{2,3}\"\npush rbx\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+68h+var_20], rax\nxor eax, eax\nmov rbx, rsp\nmov rdi, rbx; preg\ncall _regcomp\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbp; string\nmov rdi, rbx; preg\ncall _regexec\nlea rdx, aFoundAMatch; \"Found a match!\"\nmov rdi, rbx; preg\ntest eax, eax\nlea rax, aNotMatched; \"Not matched!\"\ncmovnz rdx, rax\nmov rbp, rdx\ncall _regfree\nmov rax, [rsp+68h+var_20]\nsub rax, fs:28h\njnz short loc_12FF\nadd rsp, 58h\nmov rax, rbp\npop rbx\npop rbp\nretn\nloc_12FF:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // eax\n const char *v2; // rdx\n const char *v3; // rbp\n regex_t v5; // [rsp+0h] [rbp-68h] BYREF\n unsigned __int64 v6; // [rsp+48h] [rbp-20h]\n\n v6 = __readfsqword(0x28u);\n regcomp(&v5, \"ab{2,3}\", 1);\n v1 = regexec(&v5, string, 0LL, 0LL, 0);\n v2 = \"Found a match!\";\n if ( v1 )\n v2 = \"Not matched!\";\n v3 = v2;\n regfree(&v5);\n return v3;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\npush rbp\nmov edx, 1; cflags\nmov rbp, rdi\nlea rsi, pattern; \"ab{2,3}\"\npush rbx\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+68h+var_20], rax\nxor eax, eax\nmov rbx, rsp\nmov rdi, rbx; preg\ncall _regcomp\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbp; string\nmov rdi, rbx; preg\ncall _regexec\nlea rdx, aFoundAMatch; \"Found a match!\"\nmov rdi, rbx; preg\ntest eax, eax\nlea rax, aNotMatched; \"Not matched!\"\ncmovnz rdx, rax\nmov rbp, rdx\ncall _regfree\nmov rax, [rsp+68h+var_20]\nsub rax, fs:28h\njnz short loc_12FF\nadd rsp, 58h\nmov rax, rbp\npop rbx\npop rbp\nretn\nloc_12FF:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_1280(char *string)\n{\n int v1; // eax\n const char *v2; // rdx\n const char *v3; // rbp\n regex_t v5; // [rsp+0h] [rbp-68h] BYREF\n unsigned __int64 v6; // [rsp+48h] [rbp-20h]\n\n v6 = __readfsqword(0x28u);\n regcomp(&v5, \"ab{2,3}\", 1);\n v1 = regexec(&v5, string, 0LL, 0LL, 0);\n v2 = \"Found a match!\";\n if ( v1 )\n v2 = \"Not matched!\";\n v3 = v2;\n regfree(&v5);\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1280(char *string) {\n int v1;\n const char *v2;\n const char *v3;\n regex_t v5;\n unsigned long long v6;\n v6 = __readfsqword(40u);\n regcomp(&v5, \"ab{2,3}\", 1);\n v1 = regexec(&v5, string, 0LL, 0LL, 0);\n v2 = \"Found a match!\";\n if (v1) v2 = \"Not matched!\";\n v3 = v2;\n regfree(&v5);\n return v3;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n const char *v2;\n const char *v3;\n regex_t v5;\n unsigned long long v6;\n v6 = __readfsqword(40u);\n regcomp(&v5, \"ab{2,3}\", 1);\n v1 = regexec(&v5, string, 0LL, 0LL, 0);\n v2 = \"Found a match!\";\n if (v1) v2 = \"Not matched!\";\n v3 = v2;\n regfree(&v5);\n return v3;\n}" + }, + { + "index": 285, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n regex_t regex;\n int result;\n char* match_result;\n char* pattern = \"ab{2,3}\";\n regcomp(®ex, pattern, REG_EXTENDED);\n result = regexec(®ex, text, 0, NULL, 0);\n if (result == 0) {\n match_result = \"Found a match!\";\n } else {\n match_result = \"Not matched!\";\n }\n regfree(®ex);\n return match_result;\n}", + "test": "int main() {\n\n assert(func0(\"ac\") == \"Not matched!\");\n\n assert(func0(\"dc\") == \"Not matched!\");\n\n assert(func0(\"abbbba\") == \"Found a match!\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov $0x1,%edx\nmov %rdi,%r12\nlea 0xd8b(%rip),%rsi\npush %rbp\nsub $0x58,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%rbp\nmov %rbp,%rdi\ncallq 10c0 \nxor %r8d,%r8d\nxor %ecx,%ecx\nxor %edx,%edx\nmov %r12,%rsi\nmov %rbp,%rdi\nlea 0xd4a(%rip),%r12\ncallq 10d0 \nmov %rbp,%rdi\ntest %eax,%eax\nlea 0xd2a(%rip),%rax\ncmove %rax,%r12\ncallq 1090 \nmov 0x48(%rsp),%rax\nxor %fs:0x28,%rax\njne 12fe \nadd $0x58,%rsp\nmov %r12,%rax\npop %rbp\npop %r12\nretq\ncallq 10a0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov edx, 1; cflags\nmov rbp, rdi\nlea rsi, pattern; \"ab{2,3}\"\npush rbx\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+68h+var_20], rax\nxor eax, eax\nmov rbx, rsp\nmov rdi, rbx; preg\ncall _regcomp\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbp; string\nmov rdi, rbx; preg\ncall _regexec\nlea rdx, aFoundAMatch; \"Found a match!\"\nmov rdi, rbx; preg\ntest eax, eax\nlea rax, aNotMatched; \"Not matched!\"\ncmovnz rdx, rax\nmov rbp, rdx\ncall _regfree\nmov rax, [rsp+68h+var_20]\nsub rax, fs:28h\njnz short loc_12FF\nadd rsp, 58h\nmov rax, rbp\npop rbx\npop rbp\nretn\nloc_12FF:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // eax\n const char *v2; // rdx\n const char *v3; // rbp\n regex_t v5; // [rsp+0h] [rbp-68h] BYREF\n unsigned __int64 v6; // [rsp+48h] [rbp-20h]\n\n v6 = __readfsqword(0x28u);\n regcomp(&v5, \"ab{2,3}\", 1);\n v1 = regexec(&v5, string, 0LL, 0LL, 0);\n v2 = \"Found a match!\";\n if ( v1 )\n v2 = \"Not matched!\";\n v3 = v2;\n regfree(&v5);\n return v3;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\npush rbp\nmov edx, 1; cflags\nmov rbp, rdi\nlea rsi, pattern; \"ab{2,3}\"\npush rbx\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+68h+var_20], rax\nxor eax, eax\nmov rbx, rsp\nmov rdi, rbx; preg\ncall _regcomp\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbp; string\nmov rdi, rbx; preg\ncall _regexec\nlea rdx, aFoundAMatch; \"Found a match!\"\nmov rdi, rbx; preg\ntest eax, eax\nlea rax, aNotMatched; \"Not matched!\"\ncmovnz rdx, rax\nmov rbp, rdx\ncall _regfree\nmov rax, [rsp+68h+var_20]\nsub rax, fs:28h\njnz short loc_12FF\nadd rsp, 58h\nmov rax, rbp\npop rbx\npop rbp\nretn\nloc_12FF:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_1280(char *string)\n{\n int v1; // eax\n const char *v2; // rdx\n const char *v3; // rbp\n regex_t v5; // [rsp+0h] [rbp-68h] BYREF\n unsigned __int64 v6; // [rsp+48h] [rbp-20h]\n\n v6 = __readfsqword(0x28u);\n regcomp(&v5, \"ab{2,3}\", 1);\n v1 = regexec(&v5, string, 0LL, 0LL, 0);\n v2 = \"Found a match!\";\n if ( v1 )\n v2 = \"Not matched!\";\n v3 = v2;\n regfree(&v5);\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1280(char *string) {\n int v1;\n const char *v2;\n const char *v3;\n regex_t v5;\n unsigned long long v6;\n v6 = __readfsqword(40u);\n regcomp(&v5, \"ab{2,3}\", 1);\n v1 = regexec(&v5, string, 0LL, 0LL, 0);\n v2 = \"Found a match!\";\n if (v1) v2 = \"Not matched!\";\n v3 = v2;\n regfree(&v5);\n return v3;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n const char *v2;\n const char *v3;\n regex_t v5;\n unsigned long long v6;\n v6 = __readfsqword(40u);\n regcomp(&v5, \"ab{2,3}\", 1);\n v1 = regexec(&v5, string, 0LL, 0LL, 0);\n v2 = \"Found a match!\";\n if (v1) v2 = \"Not matched!\";\n v3 = v2;\n regfree(&v5);\n return v3;\n}" + }, + { + "index": 286, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int a[], int n, int k) {\n int max_so_far = -2147483648;\n int max_ending_here = 0;\n for (int i = 0; i < n * k; ++i) {\n max_ending_here = max_ending_here + a[i % n];\n if (max_so_far < max_ending_here) {\n max_so_far = max_ending_here;\n }\n if (max_ending_here < 0) {\n max_ending_here = 0;\n }\n }\n return max_so_far;\n}", + "test": "int main() {\n\n int arr1[] = {10, 20, -30, -1};\n\n assert(func0(arr1, 4, 3) == 30);\n\n\n\n int arr2[] = {-1, 10, 20};\n\n assert(func0(arr2, 3, 2) == 59);\n\n\n\n int arr3[] = {-1, -2, -3};\n\n assert(func0(arr3, 3, 3) == -1);\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmovl $0x80000000,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11f0 \nmov -0x4(%rbp),%eax\ncltd\nidivl -0x1c(%rbp)\nmov %edx,%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nadd %eax,-0x8(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x8(%rbp),%eax\njge 11df \nmov -0x8(%rbp),%eax\nmov %eax,-0xc(%rbp)\ncmpl $0x0,-0x8(%rbp)\njns 11ec \nmovl $0x0,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x1c(%rbp),%eax\nimul -0x20(%rbp),%eax\ncmp %eax,-0x4(%rbp)\njl 11b2 \nmov -0xc(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_C], 80000000h\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11F0\nloc_11B2:\nmov eax, [rbp+var_4]\ncdq\nidiv [rbp+var_1C]\nmov eax, edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_8]\njge short loc_11DF\nmov eax, [rbp+var_8]\nmov [rbp+var_C], eax\nloc_11DF:\ncmp [rbp+var_8], 0\njns short loc_11EC\nmov [rbp+var_8], 0\nloc_11EC:\nadd [rbp+var_4], 1\nloc_11F0:\nmov eax, [rbp+var_1C]\nimul eax, [rbp+var_20]\ncmp [rbp+var_4], eax\njl short loc_11B2\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n unsigned int v4; // [rsp+14h] [rbp-Ch]\n int v5; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v4 = 0x80000000;\n v5 = 0;\n for ( i = 0; i < a3 * a2; ++i )\n {\n v5 += *(_DWORD *)(4LL * (i % a2) + a1);\n if ( (int)v4 < v5 )\n v4 = v5;\n if ( v5 < 0 )\n v5 = 0;\n }\n return v4;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_C], 80000000h\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11F0\nloc_11B2:\nmov eax, [rbp+var_4]\ncdq\nidiv [rbp+var_1C]\nmov eax, edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_8]\njge short loc_11DF\nmov eax, [rbp+var_8]\nmov [rbp+var_C], eax\nloc_11DF:\ncmp [rbp+var_8], 0\njns short loc_11EC\nmov [rbp+var_8], 0\nloc_11EC:\nadd [rbp+var_4], 1\nloc_11F0:\nmov eax, [rbp+var_1C]\nimul eax, [rbp+var_20]\ncmp [rbp+var_4], eax\njl short loc_11B2\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2, int a3)\n{\n unsigned int v4; // [rsp+14h] [rbp-Ch]\n int v5; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v4 = 0x80000000;\n v5 = 0;\n for ( i = 0; i < a3 * a2; ++i )\n {\n v5 += *(_DWORD *)(4LL * (i % a2) + a1);\n if ( (int)v4 < v5 )\n v4 = v5;\n if ( v5 < 0 )\n v5 = 0;\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2, int a3) {\n unsigned int v4;\n int v5;\n int i;\n v4 = 2147483648;\n v5 = 0;\n for (i = 0; i < a3 * a2; ++i) {\n v5 += *(uint32_t *)(4LL * (i % a2) + a1);\n if ((int)v4 < v5) v4 = v5;\n if (v5 < 0) v5 = 0;\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n unsigned int v4;\n int v5;\n int i;\n v4 = 2147483648;\n v5 = 0;\n for (i = 0; i < a3 * a2; ++i) {\n v5 += *(uint32_t *)(4LL * (i % a2) + a1);\n if ((int)v4 < v5) v4 = v5;\n if (v5 < 0) v5 = 0;\n }\n return v4;\n}" + }, + { + "index": 286, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int a[], int n, int k) {\n int max_so_far = -2147483648;\n int max_ending_here = 0;\n for (int i = 0; i < n * k; ++i) {\n max_ending_here = max_ending_here + a[i % n];\n if (max_so_far < max_ending_here) {\n max_so_far = max_ending_here;\n }\n if (max_ending_here < 0) {\n max_ending_here = 0;\n }\n }\n return max_so_far;\n}", + "test": "int main() {\n\n int arr1[] = {10, 20, -30, -1};\n\n assert(func0(arr1, 4, 3) == 30);\n\n\n\n int arr2[] = {-1, 10, 20};\n\n assert(func0(arr2, 3, 2) == 59);\n\n\n\n int arr3[] = {-1, -2, -3};\n\n assert(func0(arr3, 3, 3) == -1);\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nimul %esi,%edx\nmov %edx,%r10d\ntest %edx,%edx\njle 11d8 \nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x80000000,%r9d\nmov $0x0,%r11d\nmov %r8d,%eax\ncltd\nidiv %esi\nmovslq %edx,%rdx\nmov %ecx,%eax\nadd (%rdi,%rdx,4),%eax\ncmp %eax,%r9d\ncmovl %eax,%r9d\ntest %eax,%eax\ncmovs %r11d,%eax\nmov %eax,%ecx\nadd $0x1,%r8d\ncmp %r10d,%r8d\njne 11ae \nmov %r9d,%eax\nretq\nmov $0x80000000,%r9d\njmp 11d4 \n", + "ida_asm": "func0:\nendbr64\nmov r10, rdi\nimul edx, esi\nmov r9d, edx\ntest edx, edx\njle short loc_11D7\nmov edi, 0\nmov ecx, 0\nmov r8d, 80000000h\nloc_11AA:\nmov eax, edi\ncdq\nidiv esi\nmovsxd rdx, edx\nmov eax, ecx\nadd eax, [r10+rdx*4]\ncmp r8d, eax\ncmovl r8d, eax\ntest eax, eax\nmov edx, 0\nmov ecx, edx\ncmovns ecx, eax\nadd edi, 1\ncmp edi, r9d\njnz short loc_11AA\nloc_11D3:\nmov eax, r8d\nretn\nloc_11D7:\nmov r8d, 80000000h\njmp short loc_11D3", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n int v4; // edi\n int v5; // ecx\n unsigned int v6; // r8d\n int v7; // eax\n\n if ( a2 * a3 <= 0 )\n {\n return 0x80000000;\n }\n else\n {\n v4 = 0;\n v5 = 0;\n v6 = 0x80000000;\n do\n {\n v7 = *(_DWORD *)(a1 + 4LL * (v4 % a2)) + v5;\n if ( (int)v6 < v7 )\n v6 = *(_DWORD *)(a1 + 4LL * (v4 % a2)) + v5;\n v5 = 0;\n if ( v7 >= 0 )\n v5 = v7;\n ++v4;\n }\n while ( v4 != a2 * a3 );\n }\n return v6;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\nmov r10, rdi\nimul edx, esi\nmov r9d, edx\ntest edx, edx\njle short loc_11D7\nmov edi, 0\nmov ecx, 0\nmov r8d, 80000000h\nloc_11AA:\nmov eax, edi\ncdq\nidiv esi\nmovsxd rdx, edx\nmov eax, ecx\nadd eax, [r10+rdx*4]\ncmp r8d, eax\ncmovl r8d, eax\ntest eax, eax\nmov edx, 0\nmov ecx, edx\ncmovns ecx, eax\nadd edi, 1\ncmp edi, r9d\njnz short loc_11AA\nloc_11D3:\nmov eax, r8d\nretn\nloc_11D7:\nmov r8d, 80000000h\njmp short loc_11D3", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2, int a3)\n{\n int v4; // edi\n int v5; // ecx\n unsigned int v6; // r8d\n int v7; // eax\n\n if ( a2 * a3 <= 0 )\n {\n return 0x80000000;\n }\n else\n {\n v4 = 0;\n v5 = 0;\n v6 = 0x80000000;\n do\n {\n v7 = *(_DWORD *)(a1 + 4LL * (v4 % a2)) + v5;\n if ( (int)v6 < v7 )\n v6 = *(_DWORD *)(a1 + 4LL * (v4 % a2)) + v5;\n v5 = 0;\n if ( v7 >= 0 )\n v5 = v7;\n ++v4;\n }\n while ( v4 != a2 * a3 );\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2, int a3) {\n int v4;\n int v5;\n unsigned int v6;\n int v7;\n if (a2 * a3 <= 0) {\n return 2147483648;\n } else {\n v4 = 0;\n v5 = 0;\n v6 = 2147483648;\n do {\n v7 = *(uint32_t *)(a1 + 4LL * (v4 % a2)) + v5;\n if ((int)v6 < v7) v6 = *(uint32_t *)(a1 + 4LL * (v4 % a2)) + v5;\n v5 = 0;\n if (v7 >= 0) v5 = v7;\n ++v4;\n } while (v4 != a2 * a3);\n }\n return v6;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n int v4;\n int v5;\n unsigned int v6;\n int v7;\n if (a2 * a3 <= 0) {\n return 2147483648;\n } else {\n v4 = 0;\n v5 = 0;\n v6 = 2147483648;\n do {\n v7 = *(uint32_t *)(a1 + 4LL * (v4 % a2)) + v5;\n if ((int)v6 < v7) v6 = *(uint32_t *)(a1 + 4LL * (v4 % a2)) + v5;\n v5 = 0;\n if (v7 >= 0) v5 = v7;\n ++v4;\n } while (v4 != a2 * a3);\n }\n return v6;\n}" + }, + { + "index": 287, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) { return 2 * n * (n + 1) * (2 * n + 1) / 3; }", + "test": "int main() {\n\n assert(func0(2) == 20);\n\n assert(func0(3) == 56);\n\n assert(func0(4) == 120);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nadd $0x1,%eax\nimul -0x4(%rbp),%eax\nmov -0x4(%rbp),%edx\nadd %edx,%edx\nadd $0x1,%edx\nimul %edx,%eax\nadd %eax,%eax\nmovslq %eax,%rdx\nimul $0x55555556,%rdx,%rdx\nshr $0x20,%rdx\nsar $0x1f,%eax\nmov %edx,%ecx\nsub %eax,%ecx\nmov %ecx,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov eax, [rbp+var_4]\nadd eax, 1\nimul eax, [rbp+var_4]\nmov edx, [rbp+var_4]\nadd edx, edx\nadd edx, 1\nimul eax, edx\nadd eax, eax\nmovsxd rdx, eax\nimul rdx, 55555556h\nshr rdx, 20h\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n return (unsigned int)(2 * (2 * a1 + 1) * a1 * (a1 + 1) / 3);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov eax, [rbp+var_4]\nadd eax, 1\nimul eax, [rbp+var_4]\nmov edx, [rbp+var_4]\nadd edx, edx\nadd edx, 1\nimul eax, edx\nadd eax, eax\nmovsxd rdx, eax\nimul rdx, 55555556h\nshr rdx, 20h\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n return (unsigned int)(2 * (2 * a1 + 1) * a1 * (a1 + 1) / 3);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n return (unsigned int)(2 * (2 * a1 + 1) * a1 * (a1 + 1) / 3);\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n return (unsigned int)(2 * (2 * a1 + 1) * a1 * (a1 + 1) / 3);\n}" + }, + { + "index": 288, + "func_name": "func0", + "func_dep": "#include \n\n\n\n/* Function to calculate number of elements in array `arr` of length `N`\n\n that are modular inverses under modulo `P` */\n\n", + "func": "int func0(int arr[], int N, int P) {\n int current_element = 0;\n for (int i = 0; i < N; i++) {\n if ((arr[i] * arr[i]) % P == 1) {\n current_element += 1;\n }\n }\n return current_element;\n}", + "test": "int main() {\n\n int arr1[] = {1, 6, 4, 5};\n\n int arr2[] = {1, 3, 8, 12, 12};\n\n int arr3[] = {2, 3, 4, 5};\n\n\n\n assert(func0(arr1, 4, 7) == 2);\n\n assert(func0(arr2, 5, 13) == 3);\n\n assert(func0(arr3, 4, 6) == 1);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11cd \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\nimul %edx,%eax\ncltd\nidivl -0x20(%rbp)\nmov %edx,%eax\ncmp $0x1,%eax\njne 11c9 \naddl $0x1,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 118b \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11CD\nloc_118B:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nimul eax, edx\ncdq\nidiv [rbp+var_20]\nmov eax, edx\ncmp eax, 1\njnz short loc_11C9\nadd [rbp+var_8], 1\nloc_11C9:\nadd [rbp+var_4], 1\nloc_11CD:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_118B\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n unsigned int v4; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) * *(_DWORD *)(4LL * i + a1) % a3 == 1 )\n ++v4;\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11CD\nloc_118B:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nimul eax, edx\ncdq\nidiv [rbp+var_20]\nmov eax, edx\ncmp eax, 1\njnz short loc_11C9\nadd [rbp+var_8], 1\nloc_11C9:\nadd [rbp+var_4], 1\nloc_11CD:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_118B\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n unsigned int v4; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) * *(_DWORD *)(4LL * i + a1) % a3 == 1 )\n ++v4;\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n unsigned int v4;\n int i;\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(uint32_t *)(4LL * i + a1) * *(uint32_t *)(4LL * i + a1) % a3 == 1)\n ++v4;\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n unsigned int v4;\n int i;\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(uint32_t *)(4LL * i + a1) * *(uint32_t *)(4LL * i + a1) % a3 == 1)\n ++v4;\n }\n return v4;\n}" + }, + { + "index": 288, + "func_name": "func0", + "func_dep": "#include \n\n\n\n/* Function to calculate number of elements in array `arr` of length `N`\n\n that are modular inverses under modulo `P` */\n\n", + "func": "int func0(int arr[], int N, int P) {\n int current_element = 0;\n for (int i = 0; i < N; i++) {\n if ((arr[i] * arr[i]) % P == 1) {\n current_element += 1;\n }\n }\n return current_element;\n}", + "test": "int main() {\n\n int arr1[] = {1, 6, 4, 5};\n\n int arr2[] = {1, 3, 8, 12, 12};\n\n int arr3[] = {2, 3, 4, 5};\n\n\n\n assert(func0(arr1, 4, 7) == 2);\n\n assert(func0(arr2, 5, 13) == 3);\n\n assert(func0(arr3, 4, 6) == 1);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %edx,%r8d\ntest %esi,%esi\njle 11a4 \nmov %rdi,%rcx\nlea -0x1(%rsi),%eax\nlea 0x4(%rdi,%rax,4),%rdi\nmov $0x0,%esi\nmov (%rcx),%eax\nimul %eax,%eax\ncltd\nidiv %r8d\ncmp $0x1,%edx\nsete %al\nmovzbl %al,%eax\nadd %eax,%esi\nadd $0x4,%rcx\ncmp %rdi,%rcx\njne 1184 \nmov %esi,%eax\nretq\nmov $0x0,%esi\njmp 11a1 \n", + "ida_asm": "func0:\nendbr64\nmov r8d, edx\ntest esi, esi\njle short loc_11A3\nmov rcx, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*4]\nmov esi, 0\nloc_1183:\nmov eax, [rcx]\nimul eax, eax\ncdq\nidiv r8d\ncmp edx, 1\nsetz al\nmovzx eax, al\nadd esi, eax\nadd rcx, 4\ncmp rcx, rdi\njnz short loc_1183\nloc_11A0:\nmov eax, esi\nretn\nloc_11A3:\nmov esi, 0\njmp short loc_11A0", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2, int a3)\n{\n _DWORD *v3; // rcx\n _DWORD *v4; // rdi\n unsigned int v5; // esi\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n do\n {\n v5 += *v3 * *v3 % a3 == 1;\n ++v3;\n }\n while ( v3 != v4 );\n }\n return v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov r8d, edx\ntest esi, esi\njle short loc_11A3\nmov rcx, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*4]\nmov esi, 0\nloc_1183:\nmov eax, [rcx]\nimul eax, eax\ncdq\nidiv r8d\ncmp edx, 1\nsetz al\nmovzx eax, al\nadd esi, eax\nadd rcx, 4\ncmp rcx, rdi\njnz short loc_1183\nloc_11A0:\nmov eax, esi\nretn\nloc_11A3:\nmov esi, 0\njmp short loc_11A0", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2, int a3)\n{\n _DWORD *v3; // rcx\n _DWORD *v4; // rdi\n unsigned int v5; // esi\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n do\n {\n v5 += *v3 * *v3 % a3 == 1;\n ++v3;\n }\n while ( v3 != v4 );\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2, int a3) {\n uint32_t *v3;\n uint32_t *v4;\n unsigned int v5;\n if (a2 <= 0) {\n return 0;\n } else {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n do {\n v5 += *v3 * *v3 % a3 == 1;\n ++v3;\n } while (v3 != v4);\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2, int a3) {\n uint32_t *v3;\n uint32_t *v4;\n unsigned int v5;\n if (a2 <= 0) {\n return 0;\n } else {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n do {\n v5 += *v3 * *v3 % a3 == 1;\n ++v3;\n } while (v3 != v4);\n }\n return v5;\n}" + }, + { + "index": 289, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int N) {\n int hund1 = N / 100;\n int hund4 = N / 400;\n int leap = N >> 2;\n int ordd = N - leap;\n if (hund1) {\n ordd += hund1;\n leap -= hund1;\n }\n if (hund4) {\n ordd -= hund4;\n leap += hund4;\n }\n int days = ordd + leap * 2;\n int odd = days % 7;\n return odd;\n}", + "test": "int main() {\n\n assert(func0(100) == 5);\n\n assert(func0(50) == 6);\n\n assert(func0(75) == 2);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x24(%rbp)\nmov -0x24(%rbp),%eax\nmovslq %eax,%rdx\nimul $0x51eb851f,%rdx,%rdx\nshr $0x20,%rdx\nsar $0x5,%edx\nsar $0x1f,%eax\nsub %eax,%edx\nmov %edx,%eax\nmov %eax,-0x10(%rbp)\nmov -0x24(%rbp),%eax\nmovslq %eax,%rdx\nimul $0x51eb851f,%rdx,%rdx\nshr $0x20,%rdx\nsar $0x7,%edx\nsar $0x1f,%eax\nsub %eax,%edx\nmov %edx,%eax\nmov %eax,-0xc(%rbp)\nmov -0x24(%rbp),%eax\nsar $0x2,%eax\nmov %eax,-0x18(%rbp)\nmov -0x24(%rbp),%eax\nsub -0x18(%rbp),%eax\nmov %eax,-0x14(%rbp)\ncmpl $0x0,-0x10(%rbp)\nje 11b4 \nmov -0x10(%rbp),%eax\nadd %eax,-0x14(%rbp)\nmov -0x10(%rbp),%eax\nsub %eax,-0x18(%rbp)\ncmpl $0x0,-0xc(%rbp)\nje 11c6 \nmov -0xc(%rbp),%eax\nsub %eax,-0x14(%rbp)\nmov -0xc(%rbp),%eax\nadd %eax,-0x18(%rbp)\nmov -0x18(%rbp),%eax\nlea (%rax,%rax,1),%edx\nmov -0x14(%rbp),%eax\nadd %edx,%eax\nmov %eax,-0x8(%rbp)\nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nimul $0xffffffff92492493,%rdx,%rdx\nshr $0x20,%rdx\nadd %eax,%edx\nmov %edx,%ecx\nsar $0x2,%ecx\ncltd\nsub %edx,%ecx\nmov %ecx,%edx\nshl $0x3,%edx\nsub %ecx,%edx\nsub %edx,%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_24], edi\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nimul rdx, 51EB851Fh\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 5\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_10], eax\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nimul rdx, 51EB851Fh\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 7\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_C], eax\nmov eax, [rbp+var_24]\nsar eax, 2\nmov [rbp+var_18], eax\nmov eax, [rbp+var_24]\nsub eax, [rbp+var_18]\nmov [rbp+var_14], eax\ncmp [rbp+var_10], 0\njz short loc_11B4\nmov eax, [rbp+var_10]\nadd [rbp+var_14], eax\nmov eax, [rbp+var_10]\nsub [rbp+var_18], eax\nloc_11B4:\ncmp [rbp+var_C], 0\njz short loc_11C6\nmov eax, [rbp+var_C]\nsub [rbp+var_14], eax\nmov eax, [rbp+var_C]\nadd [rbp+var_18], eax\nloc_11C6:\nmov eax, [rbp+var_18]\nlea edx, [rax+rax]\nmov eax, [rbp+var_14]\nadd eax, edx\nmov [rbp+var_8], eax\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nimul rdx, 0FFFFFFFF92492493h\nshr rdx, 20h\nadd edx, eax\nmov ecx, edx\nsar ecx, 2\ncdq\nsub ecx, edx\nmov edx, ecx\nshl edx, 3\nsub edx, ecx\nsub eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v2; // [rsp+Ch] [rbp-18h]\n int v3; // [rsp+10h] [rbp-14h]\n int v4; // [rsp+14h] [rbp-10h]\n int v5; // [rsp+18h] [rbp-Ch]\n\n v4 = a1 / 100;\n v5 = a1 / 400;\n v2 = a1 >> 2;\n v3 = a1 - (a1 >> 2);\n if ( a1 / 100 )\n {\n v3 += v4;\n v2 -= v4;\n }\n if ( v5 )\n {\n v3 -= v5;\n v2 += v5;\n }\n return (unsigned int)((2 * v2 + v3) % 7);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_24], edi\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nimul rdx, 51EB851Fh\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 5\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_10], eax\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nimul rdx, 51EB851Fh\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 7\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_C], eax\nmov eax, [rbp+var_24]\nsar eax, 2\nmov [rbp+var_18], eax\nmov eax, [rbp+var_24]\nsub eax, [rbp+var_18]\nmov [rbp+var_14], eax\ncmp [rbp+var_10], 0\njz short loc_11B4\nmov eax, [rbp+var_10]\nadd [rbp+var_14], eax\nmov eax, [rbp+var_10]\nsub [rbp+var_18], eax\nloc_11B4:\ncmp [rbp+var_C], 0\njz short loc_11C6\nmov eax, [rbp+var_C]\nsub [rbp+var_14], eax\nmov eax, [rbp+var_C]\nadd [rbp+var_18], eax\nloc_11C6:\nmov eax, [rbp+var_18]\nlea edx, [rax+rax]\nmov eax, [rbp+var_14]\nadd eax, edx\nmov [rbp+var_8], eax\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nimul rdx, 0FFFFFFFF92492493h\nshr rdx, 20h\nadd edx, eax\nmov ecx, edx\nsar ecx, 2\ncdq\nsub ecx, edx\nmov edx, ecx\nshl edx, 3\nsub edx, ecx\nsub eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v2; // [rsp+Ch] [rbp-18h]\n int v3; // [rsp+10h] [rbp-14h]\n int v4; // [rsp+14h] [rbp-10h]\n int v5; // [rsp+18h] [rbp-Ch]\n\n v4 = a1 / 100;\n v5 = a1 / 400;\n v2 = a1 >> 2;\n v3 = a1 - (a1 >> 2);\n if ( a1 / 100 )\n {\n v3 += v4;\n v2 -= v4;\n }\n if ( v5 )\n {\n v3 -= v5;\n v2 += v5;\n }\n return (unsigned int)((2 * v2 + v3) % 7);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v2;\n int v3;\n int v4;\n int v5;\n v4 = a1 / 100;\n v5 = a1 / 400;\n v2 = a1 >> 2;\n v3 = a1 - (a1 >> 2);\n if (a1 / 100) {\n v3 += v4;\n v2 -= v4;\n }\n if (v5) {\n v3 -= v5;\n v2 += v5;\n }\n return (unsigned int)((2 * v2 + v3) % 7);\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v2;\n int v3;\n int v4;\n int v5;\n v4 = a1 / 100;\n v5 = a1 / 400;\n v2 = a1 >> 2;\n v3 = a1 - (a1 >> 2);\n if (a1 / 100) {\n v3 += v4;\n v2 -= v4;\n }\n if (v5) {\n v3 -= v5;\n v2 += v5;\n }\n return (unsigned int)((2 * v2 + v3) % 7);\n}" + }, + { + "index": 290, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int length;\n\n int *array;\n\n} Result;\n\n\n\n\n\nvoid compareArrays(int *array1, int *array2, int size) {\n\n for (int i = 0; i < size; i++) {\n\n assert(array1[i] == array2[i]);\n\n }\n\n}\n\n\n\n\n\n", + "func": "Result func0(int **list, int size, int *sizes) {\n Result result;\n int maxLength = 0;\n int *maxList = NULL;\n for (int i = 0; i < size; i++) {\n if (sizes[i] > maxLength) {\n maxLength = sizes[i];\n maxList = list[i];\n }\n }\n result.length = maxLength;\n result.array = maxList;\n return result;\n}", + "test": "int main() {\n\n int arr1[] = {0};\n\n int arr2[] = {1, 3};\n\n int arr3[] = {5, 7};\n\n int arr4[] = {9, 11};\n\n int arr5[] = {13, 15, 17};\n\n int *list1[] = {arr1, arr2, arr3, arr4, arr5};\n\n int sizes1[] = {1, 2, 2, 2, 3};\n\n\n\n Result res1 = func0(list1, 5, sizes1);\n\n assert(res1.length == 3);\n\n compareArrays(res1.array, arr5, 3);\n\n\n\n int arr6[] = {1};\n\n int arr7[] = {5, 7};\n\n int arr8[] = {10, 12, 14, 15};\n\n int *list2[] = {arr6, arr7, arr8};\n\n int sizes2[] = {1, 2, 4};\n\n\n\n Result res2 = func0(list2, 3, sizes2);\n\n assert(res2.length == 4);\n\n compareArrays(res2.array, arr8, 4);\n\n\n\n int arr9[] = {5};\n\n int arr10[] = {15, 20, 25};\n\n int *list3[] = {arr9, arr10};\n\n int sizes3[] = {1, 3};\n\n\n\n Result res3 = func0(list3, 2, sizes3);\n\n assert(res3.length == 3);\n\n compareArrays(res3.array, arr10, 3);\n\n\n\n printf(\"All tests passed successfully!\\n\");\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nmov %rdi,-0x30(%rbp)\nmov %esi,-0x34(%rbp)\nmov %rdx,-0x40(%rbp)\nmovl $0x0,-0x28(%rbp)\nmovq $0x0,-0x20(%rbp)\nmovl $0x0,-0x24(%rbp)\njmp 1287 \nmov -0x24(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x40(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x28(%rbp)\njge 1283 \nmov -0x24(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x40(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x28(%rbp)\nmov -0x24(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x30(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov %rax,-0x20(%rbp)\naddl $0x1,-0x24(%rbp)\nmov -0x24(%rbp),%eax\ncmp -0x34(%rbp),%eax\njl 1234 \nmov -0x28(%rbp),%eax\nmov %eax,-0x18(%rbp)\nmov -0x20(%rbp),%rax\nmov %rax,-0x10(%rbp)\nmov -0x18(%rbp),%rax\nmov -0x10(%rbp),%rdx\nmov %rax,%rcx\nmov %rdx,%rbx\nmov %ecx,%eax\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov [rbp+var_48], rdx\nmov [rbp+var_30], 0\nmov [rbp+var_28], 0\nmov [rbp+var_2C], 0\njmp short loc_1290\nloc_123D:\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_30], eax\njge short loc_128C\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_30], eax\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nmov [rbp+var_28], rax\nloc_128C:\nadd [rbp+var_2C], 1\nloc_1290:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_3C]\njl short loc_123D\nmov eax, [rbp+var_30]\nmov dword ptr [rbp+var_20], eax\nmov rax, [rbp+var_28]\nmov [rbp+var_18], rax\nmov rax, [rbp+var_20]\nmov rdx, [rbp+var_18]\nmov rsi, rax\nmov rdi, rdx\nmov rcx, rax\nmov rbx, rdx\nmov eax, esi\nmov rdx, rbx\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3)\n{\n unsigned int v4; // [rsp+18h] [rbp-30h]\n int i; // [rsp+1Ch] [rbp-2Ch]\n\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( (signed int)v4 < *(_DWORD *)(4LL * i + a3) )\n v4 = *(_DWORD *)(4LL * i + a3);\n }\n return v4;\n}", + "ida_strip_asm": "sub_1211:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov [rbp+var_48], rdx\nmov [rbp+var_30], 0\nmov [rbp+var_28], 0\nmov [rbp+var_2C], 0\njmp short loc_1290\nloc_123D:\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_30], eax\njge short loc_128C\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_30], eax\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nmov [rbp+var_28], rax\nloc_128C:\nadd [rbp+var_2C], 1\nloc_1290:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_3C]\njl short loc_123D\nmov eax, [rbp+var_30]\nmov dword ptr [rbp+var_20], eax\nmov rax, [rbp+var_28]\nmov [rbp+var_18], rax\nmov rax, [rbp+var_20]\nmov rdx, [rbp+var_18]\nmov rsi, rax\nmov rdi, rdx\nmov rcx, rax\nmov rbx, rdx\nmov eax, esi\nmov rdx, rbx\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1211(__int64 a1, int a2, __int64 a3)\n{\n unsigned int v4; // [rsp+18h] [rbp-30h]\n int i; // [rsp+1Ch] [rbp-2Ch]\n\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( (signed int)v4 < *(_DWORD *)(4LL * i + a3) )\n v4 = *(_DWORD *)(4LL * i + a3);\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1211(long long a1, int a2, long long a3) {\n unsigned int v4;\n int i;\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n if ((signed int)v4 < *(uint32_t *)(4LL * i + a3))\n v4 = *(uint32_t *)(4LL * i + a3);\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3) {\n unsigned int v4;\n int i;\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n if ((signed int)v4 < *(uint32_t *)(4LL * i + a3))\n v4 = *(uint32_t *)(4LL * i + a3);\n }\n return v4;\n}" + }, + { + "index": 290, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int length;\n\n int *array;\n\n} Result;\n\n\n\n\n\nvoid compareArrays(int *array1, int *array2, int size) {\n\n for (int i = 0; i < size; i++) {\n\n assert(array1[i] == array2[i]);\n\n }\n\n}\n\n\n\n\n\n", + "func": "Result func0(int **list, int size, int *sizes) {\n Result result;\n int maxLength = 0;\n int *maxList = NULL;\n for (int i = 0; i < size; i++) {\n if (sizes[i] > maxLength) {\n maxLength = sizes[i];\n maxList = list[i];\n }\n }\n result.length = maxLength;\n result.array = maxList;\n return result;\n}", + "test": "int main() {\n\n int arr1[] = {0};\n\n int arr2[] = {1, 3};\n\n int arr3[] = {5, 7};\n\n int arr4[] = {9, 11};\n\n int arr5[] = {13, 15, 17};\n\n int *list1[] = {arr1, arr2, arr3, arr4, arr5};\n\n int sizes1[] = {1, 2, 2, 2, 3};\n\n\n\n Result res1 = func0(list1, 5, sizes1);\n\n assert(res1.length == 3);\n\n compareArrays(res1.array, arr5, 3);\n\n\n\n int arr6[] = {1};\n\n int arr7[] = {5, 7};\n\n int arr8[] = {10, 12, 14, 15};\n\n int *list2[] = {arr6, arr7, arr8};\n\n int sizes2[] = {1, 2, 4};\n\n\n\n Result res2 = func0(list2, 3, sizes2);\n\n assert(res2.length == 4);\n\n compareArrays(res2.array, arr8, 4);\n\n\n\n int arr9[] = {5};\n\n int arr10[] = {15, 20, 25};\n\n int *list3[] = {arr9, arr10};\n\n int sizes3[] = {1, 3};\n\n\n\n Result res3 = func0(list3, 2, sizes3);\n\n assert(res3.length == 3);\n\n compareArrays(res3.array, arr10, 3);\n\n\n\n printf(\"All tests passed successfully!\\n\");\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 120c \nlea -0x1(%rsi),%r8d\nmov $0x0,%ecx\nmov $0x0,%r9d\nmov $0x0,%eax\njmp 11fd \nlea 0x1(%rcx),%rsi\ncmp %r8,%rcx\nje 1217 \nmov %rsi,%rcx\nmov (%rdx,%rcx,4),%esi\ncmp %eax,%esi\njle 11f1 \nmov (%rdi,%rcx,8),%r9\nmov %esi,%eax\njmp 11f1 \nmov $0x0,%r9d\nmov $0x0,%eax\nmov %eax,%eax\nmov %r9,%rdx\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_120A\nmovsxd rsi, esi\nmov ecx, 0\nmov r9d, 0\nmov eax, 0\njmp short loc_11F8\nloc_11EF:\nadd rcx, 1\ncmp rcx, rsi\njz short loc_1215\nloc_11F8:\nmov r8d, [rdx+rcx*4]\ncmp r8d, eax\njle short loc_11EF\nmov r9, [rdi+rcx*8]\nmov eax, r8d\njmp short loc_11EF\nloc_120A:\nmov r9d, 0\nmov eax, 0\nloc_1215:\nmov rdx, r9\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3)\n{\n __int64 v3; // rcx\n __int64 result; // rax\n int v5; // r8d\n\n if ( a2 <= 0 )\n return 0LL;\n v3 = 0LL;\n result = 0LL;\n do\n {\n v5 = *(_DWORD *)(a3 + 4 * v3);\n if ( v5 > (int)result )\n result = (unsigned int)v5;\n ++v3;\n }\n while ( v3 != a2 );\n return result;\n}", + "ida_strip_asm": "sub_11D2:\nendbr64\ntest esi, esi\njle short loc_120A\nmovsxd rsi, esi\nmov ecx, 0\nmov r9d, 0\nmov eax, 0\njmp short loc_11F8\nloc_11EF:\nadd rcx, 1\ncmp rcx, rsi\njz short loc_1215\nloc_11F8:\nmov r8d, [rdx+rcx*4]\ncmp r8d, eax\njle short loc_11EF\nmov r9, [rdi+rcx*8]\nmov eax, r8d\njmp short loc_11EF\nloc_120A:\nmov r9d, 0\nmov eax, 0\nloc_1215:\nmov rdx, r9\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11D2(__int64 a1, int a2, __int64 a3)\n{\n __int64 v3; // rcx\n __int64 result; // rax\n int v5; // r8d\n\n if ( a2 <= 0 )\n return 0LL;\n v3 = 0LL;\n result = 0LL;\n do\n {\n v5 = *(_DWORD *)(a3 + 4 * v3);\n if ( v5 > (int)result )\n result = (unsigned int)v5;\n ++v3;\n }\n while ( v3 != a2 );\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11D2(long long a1, int a2, long long a3) {\n long long v3;\n long long result;\n int v5;\n if (a2 <= 0) return 0LL;\n v3 = 0LL;\n result = 0LL;\n do {\n v5 = *(uint32_t *)(a3 + 4 * v3);\n if (v5 > (int)result) result = (unsigned int)v5;\n ++v3;\n } while (v3 != a2);\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3) {\n long long v3;\n long long result;\n int v5;\n if (a2 <= 0) return 0LL;\n v3 = 0LL;\n result = 0LL;\n do {\n v5 = *(uint32_t *)(a3 + 4 * v3);\n if (v5 > (int)result) result = (unsigned int)v5;\n ++v3;\n } while (v3 != a2);\n return result;\n}" + }, + { + "index": 290, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int length;\n\n int *array;\n\n} Result;\n\n\n\n\n\nvoid compareArrays(int *array1, int *array2, int size) {\n\n for (int i = 0; i < size; i++) {\n\n assert(array1[i] == array2[i]);\n\n }\n\n}\n\n\n\n\n\n", + "func": "Result func0(int **list, int size, int *sizes) {\n Result result;\n int maxLength = 0;\n int *maxList = NULL;\n for (int i = 0; i < size; i++) {\n if (sizes[i] > maxLength) {\n maxLength = sizes[i];\n maxList = list[i];\n }\n }\n result.length = maxLength;\n result.array = maxList;\n return result;\n}", + "test": "int main() {\n\n int arr1[] = {0};\n\n int arr2[] = {1, 3};\n\n int arr3[] = {5, 7};\n\n int arr4[] = {9, 11};\n\n int arr5[] = {13, 15, 17};\n\n int *list1[] = {arr1, arr2, arr3, arr4, arr5};\n\n int sizes1[] = {1, 2, 2, 2, 3};\n\n\n\n Result res1 = func0(list1, 5, sizes1);\n\n assert(res1.length == 3);\n\n compareArrays(res1.array, arr5, 3);\n\n\n\n int arr6[] = {1};\n\n int arr7[] = {5, 7};\n\n int arr8[] = {10, 12, 14, 15};\n\n int *list2[] = {arr6, arr7, arr8};\n\n int sizes2[] = {1, 2, 4};\n\n\n\n Result res2 = func0(list2, 3, sizes2);\n\n assert(res2.length == 4);\n\n compareArrays(res2.array, arr8, 4);\n\n\n\n int arr9[] = {5};\n\n int arr10[] = {15, 20, 25};\n\n int *list3[] = {arr9, arr10};\n\n int sizes3[] = {1, 3};\n\n\n\n Result res3 = func0(list3, 2, sizes3);\n\n assert(res3.length == 3);\n\n compareArrays(res3.array, arr10, 3);\n\n\n\n printf(\"All tests passed successfully!\\n\");\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1228 \nlea -0x1(%rsi),%r8d\nxor %ecx,%ecx\nxor %r9d,%r9d\nxor %eax,%eax\njmp 120b \nnopl (%rax)\nmov %rsi,%rcx\nmov (%rdx,%rcx,4),%esi\ncmp %eax,%esi\njle 1218 \nmov (%rdi,%rcx,8),%r9\nmov %esi,%eax\nlea 0x1(%rcx),%rsi\ncmp %r8,%rcx\njne 1208 \nmov %r9,%rdx\nretq\nnopl (%rax)\nxor %r9d,%r9d\nxor %eax,%eax\nmov %r9,%rdx\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_14C8\nmovsxd rsi, esi\nxor ecx, ecx\nxor r9d, r9d\nxor eax, eax\nnop word ptr [rax+rax+00h]\nloc_14A8:\nmov r8d, [rdx+rcx*4]\ncmp r8d, eax\njle short loc_14B8\nmov r9, [rdi+rcx*8]\nmov eax, r8d\nloc_14B8:\nadd rcx, 1\ncmp rcx, rsi\njnz short loc_14A8\nmov rdx, r9\nretn\nloc_14C8:\nxor r9d, r9d\nxor eax, eax\nmov rdx, r9\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3)\n{\n __int64 v3; // rcx\n __int64 result; // rax\n int v5; // r8d\n\n if ( a2 <= 0 )\n return 0LL;\n v3 = 0LL;\n result = 0LL;\n do\n {\n v5 = *(_DWORD *)(a3 + 4 * v3);\n if ( v5 > (int)result )\n result = (unsigned int)v5;\n ++v3;\n }\n while ( v3 != a2 );\n return result;\n}", + "ida_strip_asm": "sub_1490:\nendbr64\ntest esi, esi\njle short loc_14C8\nmovsxd rsi, esi\nxor ecx, ecx\nxor r9d, r9d\nxor eax, eax\nnop word ptr [rax+rax+00h]\nloc_14A8:\nmov r8d, [rdx+rcx*4]\ncmp r8d, eax\njle short loc_14B8\nmov r9, [rdi+rcx*8]\nmov eax, r8d\nloc_14B8:\nadd rcx, 1\ncmp rcx, rsi\njnz short loc_14A8\nmov rdx, r9\nretn\nloc_14C8:\nxor r9d, r9d\nxor eax, eax\nmov rdx, r9\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1490(__int64 a1, int a2, __int64 a3)\n{\n __int64 v3; // rcx\n __int64 result; // rax\n int v5; // r8d\n\n if ( a2 <= 0 )\n return 0LL;\n v3 = 0LL;\n result = 0LL;\n do\n {\n v5 = *(_DWORD *)(a3 + 4 * v3);\n if ( v5 > (int)result )\n result = (unsigned int)v5;\n ++v3;\n }\n while ( v3 != a2 );\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1490(long long a1, int a2, long long a3) {\n long long v3;\n long long result;\n int v5;\n if (a2 <= 0) return 0LL;\n v3 = 0LL;\n result = 0LL;\n do {\n v5 = *(uint32_t *)(a3 + 4 * v3);\n if (v5 > (int)result) result = (unsigned int)v5;\n ++v3;\n } while (v3 != a2);\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3) {\n long long v3;\n long long result;\n int v5;\n if (a2 <= 0) return 0LL;\n v3 = 0LL;\n result = 0LL;\n do {\n v5 = *(uint32_t *)(a3 + 4 * v3);\n if (v5 > (int)result) result = (unsigned int)v5;\n ++v3;\n } while (v3 != a2);\n return result;\n}" + }, + { + "index": 291, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n#define MOD 1000000007\n\n\n\n", + "func": "int func0(int n, int k) {\n int dp[n + 1];\n dp[0] = 0;\n dp[1] = k;\n dp[2] = k * k;\n for (int i = 3; i <= n; i++) {\n dp[i] = ((k - 1) * (dp[i - 1] + dp[i - 2])) % MOD;\n }\n return dp[n];\n}", + "test": "int main() {\n\n assert(func0(2, 4) == 16);\n\n assert(func0(3, 2) == 6);\n\n assert(func0(4, 4) == 228);\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x38,%rsp\nmov %edi,-0x34(%rbp)\nmov %esi,-0x38(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmov %rsp,%rax\nmov %rax,%rdi\nmov -0x34(%rbp),%eax\nadd $0x1,%eax\nmovslq %eax,%rdx\nsub $0x1,%rdx\nmov %rdx,-0x28(%rbp)\nmovslq %eax,%rdx\nmov %rdx,%r8\nmov $0x0,%r9d\nmovslq %eax,%rdx\nmov %rdx,%rcx\nmov $0x0,%ebx\ncltq\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%ebx\nmov $0x0,%edx\ndiv %rbx\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rbx\nsub %rdx,%rbx\nmov %rbx,%rdx\ncmp %rdx,%rsp\nje 122a \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 1213 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 1254 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x20(%rbp)\nmov -0x20(%rbp),%rax\nmovl $0x0,(%rax)\nmov -0x20(%rbp),%rax\nmov -0x38(%rbp),%edx\nmov %edx,0x4(%rax)\nmov -0x38(%rbp),%eax\nimul %eax,%eax\nmov %eax,%edx\nmov -0x20(%rbp),%rax\nmov %edx,0x8(%rax)\nmovl $0x3,-0x2c(%rbp)\njmp 12f7 \nmov -0x38(%rbp),%eax\nlea -0x1(%rax),%esi\nmov -0x2c(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x20(%rbp),%rax\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%ecx\nmov -0x2c(%rbp),%eax\nlea -0x2(%rax),%edx\nmov -0x20(%rbp),%rax\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nadd %ecx,%eax\nimul %eax,%esi\nmov %esi,%edx\nmovslq %edx,%rax\nimul $0x44b82f99,%rax,%rax\nshr $0x20,%rax\nmov %eax,%ecx\nsar $0x1c,%ecx\nmov %edx,%eax\nsar $0x1f,%eax\nsub %eax,%ecx\nmov %ecx,%eax\nimul $0x3b9aca07,%eax,%eax\nsub %eax,%edx\nmov %edx,%eax\nmov -0x20(%rbp),%rdx\nmov -0x2c(%rbp),%ecx\nmovslq %ecx,%rcx\nmov %eax,(%rdx,%rcx,4)\naddl $0x1,-0x2c(%rbp)\nmov -0x2c(%rbp),%eax\ncmp -0x34(%rbp),%eax\njle 1293 \nmov -0x20(%rbp),%rax\nmov -0x34(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nmov %rdi,%rsp\nmov -0x18(%rbp),%rdi\nxor %fs:0x28,%rdi\nje 1323 \ncallq 1080 <__stack_chk_fail@plt>\nmov -0x8(%rbp),%rbx\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_24], edi\nmov [rbp+var_28], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rdi, rax\nmov eax, [rbp+var_24]\nadd eax, 1\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov esi, 10h\nmov edx, 0\ndiv rsi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11F8:\ncmp rsp, rdx\njz short loc_120F\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\njmp short loc_11F8\nloc_120F:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1239\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1239:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov rax, [rbp+var_10]\nmov dword ptr [rax], 0\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_28]\nmov [rax+4], edx\nmov eax, [rbp+var_28]\nimul eax, eax\nmov edx, eax\nmov rax, [rbp+var_10]\nmov [rax+8], edx\nmov [rbp+var_1C], 3\njmp short loc_12D8\nloc_1278:\nmov eax, [rbp+var_28]\nlea ecx, [rax-1]\nmov eax, [rbp+var_1C]\nlea edx, [rax-1]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov esi, [rax+rdx*4]\nmov eax, [rbp+var_1C]\nlea edx, [rax-2]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nadd eax, esi\nimul ecx, eax\nmov edx, ecx\nmovsxd rax, edx\nimul rax, 44B82F99h\nshr rax, 20h\nsar eax, 1Ch\nmov ecx, edx\nsar ecx, 1Fh\nsub eax, ecx\nimul ecx, eax, 3B9ACA07h\nmov eax, edx\nsub eax, ecx\nmov rdx, [rbp+var_10]\nmov ecx, [rbp+var_1C]\nmovsxd rcx, ecx\nmov [rdx+rcx*4], eax\nadd [rbp+var_1C], 1\nloc_12D8:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_24]\njle short loc_1278\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov rsp, rdi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1304\ncall ___stack_chk_fail\nlocret_1304:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n unsigned __int64 v2; // rax\n void *v3; // rsp\n _DWORD v5[2]; // [rsp+8h] [rbp-30h] BYREF\n int v6; // [rsp+10h] [rbp-28h]\n int v7; // [rsp+14h] [rbp-24h]\n int i; // [rsp+1Ch] [rbp-1Ch]\n __int64 v9; // [rsp+20h] [rbp-18h]\n _DWORD *v10; // [rsp+28h] [rbp-10h]\n unsigned __int64 v11; // [rsp+30h] [rbp-8h]\n\n v7 = a1;\n v6 = a2;\n v11 = __readfsqword(0x28u);\n v9 = a1 + 1 - 1LL;\n v2 = 16 * ((4LL * (a1 + 1) + 15) / 0x10uLL);\n while ( v5 != (_DWORD *)((char *)v5 - (v2 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v3 = alloca(v2 & 0xFFF);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)((char *)&v5[-2] + (v2 & 0xFFF)) = *(_QWORD *)((char *)&v5[-2] + (v2 & 0xFFF));\n v10 = v5;\n v5[0] = 0;\n v5[1] = v6;\n v6 *= v6;\n for ( i = 3; i <= v7; ++i )\n v10[i] = (v10[i - 1] + v10[i - 2]) * (v6 - 1) % 1000000007;\n return (unsigned int)v10[v7];\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_24], edi\nmov [rbp+var_28], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rdi, rax\nmov eax, [rbp+var_24]\nadd eax, 1\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov esi, 10h\nmov edx, 0\ndiv rsi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11F8:\ncmp rsp, rdx\njz short loc_120F\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\njmp short loc_11F8\nloc_120F:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1239\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1239:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov rax, [rbp+var_10]\nmov dword ptr [rax], 0\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_28]\nmov [rax+4], edx\nmov eax, [rbp+var_28]\nimul eax, eax\nmov edx, eax\nmov rax, [rbp+var_10]\nmov [rax+8], edx\nmov [rbp+var_1C], 3\njmp short loc_12D8\nloc_1278:\nmov eax, [rbp+var_28]\nlea ecx, [rax-1]\nmov eax, [rbp+var_1C]\nlea edx, [rax-1]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov esi, [rax+rdx*4]\nmov eax, [rbp+var_1C]\nlea edx, [rax-2]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nadd eax, esi\nimul ecx, eax\nmov edx, ecx\nmovsxd rax, edx\nimul rax, 44B82F99h\nshr rax, 20h\nsar eax, 1Ch\nmov ecx, edx\nsar ecx, 1Fh\nsub eax, ecx\nimul ecx, eax, 3B9ACA07h\nmov eax, edx\nsub eax, ecx\nmov rdx, [rbp+var_10]\nmov ecx, [rbp+var_1C]\nmovsxd rcx, ecx\nmov [rdx+rcx*4], eax\nadd [rbp+var_1C], 1\nloc_12D8:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_24]\njle short loc_1278\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov rsp, rdi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1304\ncall ___stack_chk_fail\nlocret_1304:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(int a1, int a2)\n{\n unsigned __int64 v2; // rax\n void *v3; // rsp\n _DWORD v5[2]; // [rsp+8h] [rbp-30h] BYREF\n int v6; // [rsp+10h] [rbp-28h]\n int v7; // [rsp+14h] [rbp-24h]\n int i; // [rsp+1Ch] [rbp-1Ch]\n __int64 v9; // [rsp+20h] [rbp-18h]\n _DWORD *v10; // [rsp+28h] [rbp-10h]\n unsigned __int64 v11; // [rsp+30h] [rbp-8h]\n\n v7 = a1;\n v6 = a2;\n v11 = __readfsqword(0x28u);\n v9 = a1 + 1 - 1LL;\n v2 = 16 * ((4LL * (a1 + 1) + 15) / 0x10uLL);\n while ( v5 != (_DWORD *)((char *)v5 - (v2 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v3 = alloca(v2 & 0xFFF);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)((char *)&v5[-2] + (v2 & 0xFFF)) = *(_QWORD *)((char *)&v5[-2] + (v2 & 0xFFF));\n v10 = v5;\n v5[0] = 0;\n v5[1] = v6;\n v6 *= v6;\n for ( i = 3; i <= v7; ++i )\n v10[i] = (v10[i - 1] + v10[i - 2]) * (v6 - 1) % 1000000007;\n return (unsigned int)v10[v7];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(int a1, int a2) {\n unsigned long long v2;\n void *v3;\n uint32_t v5[2];\n int v6;\n int v7;\n int i;\n long long v9;\n uint32_t *v10;\n unsigned long long v11;\n v7 = a1;\n v6 = a2;\n v11 = __readfsqword(40u);\n v9 = a1 + 1 - 1LL;\n v2 = 16 * ((4LL * (a1 + 1) + 15) / 16uLL);\n while (v5 != (uint32_t *)((char *)v5 - (v2 & 18446744073709547520LL)))\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)((char *)&v5[-2] + (v2 & 4095)) =\n *(uint64_t *)((char *)&v5[-2] + (v2 & 4095));\n v10 = v5;\n v5[0] = 0;\n v5[1] = v6;\n v6 *= v6;\n for (i = 3; i <= v7; ++i)\n v10[i] = (v10[i - 1] + v10[i - 2]) * (v6 - 1) % 1000000007;\n return (unsigned int)v10[v7];\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n unsigned long long v2;\n void *v3;\n uint32_t v5[2];\n int v6;\n int v7;\n int i;\n long long v9;\n uint32_t *v10;\n unsigned long long v11;\n v7 = a1;\n v6 = a2;\n v11 = __readfsqword(40u);\n v9 = a1 + 1 - 1LL;\n v2 = 16 * ((4LL * (a1 + 1) + 15) / 16uLL);\n while (v5 != (uint32_t *)((char *)v5 - (v2 & 18446744073709547520LL)))\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)((char *)&v5[-2] + (v2 & 4095)) =\n *(uint64_t *)((char *)&v5[-2] + (v2 & 4095));\n v10 = v5;\n v5[0] = 0;\n v5[1] = v6;\n v6 *= v6;\n for (i = 3; i <= v7; ++i)\n v10[i] = (v10[i - 1] + v10[i - 2]) * (v6 - 1) % 1000000007;\n return (unsigned int)v10[v7];\n}" + }, + { + "index": 291, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n#define MOD 1000000007\n\n\n\n", + "func": "int func0(int n, int k) {\n int dp[n + 1];\n dp[0] = 0;\n dp[1] = k;\n dp[2] = k * k;\n for (int i = 3; i <= n; i++) {\n dp[i] = ((k - 1) * (dp[i - 1] + dp[i - 2])) % MOD;\n }\n return dp[n];\n}", + "test": "int main() {\n\n assert(func0(2, 4) == 16);\n\n assert(func0(3, 2) == 6);\n\n assert(func0(4, 4) == 228);\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0x1(%rdi),%eax\ncltq\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffffff0,%rdx\nand $0xfffffffffffff000,%rax\nmov %rsp,%rcx\nsub %rax,%rcx\nmov %rcx,%rax\ncmp %rax,%rsp\nje 11de \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11c7 \nmov %rdx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 11f4 \norq $0x0,-0x8(%rsp,%rax,1)\nlea 0x3(%rsp),%r9\nmov %r9,%rax\nshr $0x2,%rax\nand $0xfffffffffffffffc,%r9\nmovl $0x0,0x0(,%rax,4)\nmov %esi,0x4(,%rax,4)\nmov %esi,%edx\nimul %esi,%edx\nmov %edx,0x8(,%rax,4)\ncmp $0x2,%edi\njle 126a \nlea 0x4(%r9),%rcx\nlea -0x3(%rdi),%eax\nlea 0x8(%r9,%rax,4),%r8\nsub $0x1,%esi\nmov (%rcx),%eax\nadd 0x4(%rcx),%eax\nimul %esi,%eax\nmovslq %eax,%rdx\nimul $0x44b82f99,%rdx,%rdx\nsar $0x3c,%rdx\nmov %eax,%r10d\nsar $0x1f,%r10d\nsub %r10d,%edx\nimul $0x3b9aca07,%edx,%edx\nsub %edx,%eax\nmov %eax,0x8(%rcx)\nadd $0x4,%rcx\ncmp %r8,%rcx\njne 1236 \nmovslq %edi,%rdi\nmov (%r9,%rdi,4),%eax\nmov -0x8(%rbp),%rdi\nxor %fs:0x28,%rdi\njne 1282 \nleaveq\nretq\ncallq 1080 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov r8d, edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea eax, [rdi+1]\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11C7:\ncmp rsp, rdx\njz short loc_11DE\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11C7\nloc_11DE:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11F4\nor [rsp+rax+10h+var_18], 0\nloc_11F4:\nlea r9, [rsp+10h+var_D]\nmov rax, r9\nshr rax, 2\nand r9, 0FFFFFFFFFFFFFFFCh\nmov ds:dword_0[rax*4], 0\nmov dword ptr ds:byte_4[rax*4], esi\nmov edx, esi\nimul edx, esi\nmov dword ptr ds:byte_8[rax*4], edx\ncmp r8d, 2\njle short loc_126C\nlea rcx, [r9+4]\nlea eax, [r8-3]\nlea rdi, [r9+rax*4+8]\nsub esi, 1\nloc_1238:\nmov eax, [rcx]\nadd eax, [rcx+4]\nimul eax, esi\nmovsxd rdx, eax\nimul rdx, 44B82F99h\nsar rdx, 3Ch\nmov r10d, eax\nsar r10d, 1Fh\nsub edx, r10d\nimul edx, 3B9ACA07h\nsub eax, edx\nmov [rcx+8], eax\nadd rcx, 4\ncmp rcx, rdi\njnz short loc_1238\nloc_126C:\nmovsxd r8, r8d\nmov eax, [r9+r8*4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_1284\nleave\nretn\nloc_1284:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n signed __int64 v3; // rax\n void *v4; // rsp\n unsigned __int64 v5; // rax\n char *v6; // rcx\n char *v7; // rdi\n int v8; // esi\n _BYTE v11[3]; // [rsp+8h] [rbp-10h] BYREF\n char v12; // [rsp+Bh] [rbp-Dh] BYREF\n int v13; // [rsp+Ch] [rbp-Ch] BYREF\n unsigned __int64 v14; // [rsp+10h] [rbp-8h] BYREF\n\n v14 = __readfsqword(0x28u);\n while ( v11 != &v11[-((4LL * (a1 + 1) + 15) & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = (4 * ((_WORD)a1 + 1) + 15) & 0xFF0;\n v4 = alloca(v3);\n if ( ((4 * ((_WORD)a1 + 1) + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v11[v3 - 8] = *(_QWORD *)&v11[v3 - 8];\n v5 = (unsigned __int64)&v12 >> 2;\n *(_DWORD *)(4 * v5) = 0;\n *(_DWORD *)&byte_4[4 * v5] = a2;\n *(_DWORD *)&byte_8[4 * v5] = a2 * a2;\n if ( a1 > 2 )\n {\n v6 = (char *)&v13;\n v7 = (char *)&v14 + 4 * (unsigned int)(a1 - 3);\n v8 = a2 - 1;\n do\n {\n *((_DWORD *)v6 + 2) = v8 * (*((_DWORD *)v6 + 1) + *(_DWORD *)v6) % 1000000007;\n v6 += 4;\n }\n while ( v6 != v7 );\n }\n return *(unsigned int *)&v11[4 * a1];\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov r8d, edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea eax, [rdi+1]\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11C7:\ncmp rsp, rdx\njz short loc_11DE\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11C7\nloc_11DE:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11F4\nor [rsp+rax+10h+var_18], 0\nloc_11F4:\nlea r9, [rsp+10h+var_D]\nmov rax, r9\nshr rax, 2\nand r9, 0FFFFFFFFFFFFFFFCh\nmov ds:dword_0[rax*4], 0\nmov dword ptr ds:byte_4[rax*4], esi\nmov edx, esi\nimul edx, esi\nmov dword ptr ds:byte_8[rax*4], edx\ncmp r8d, 2\njle short loc_126C\nlea rcx, [r9+4]\nlea eax, [r8-3]\nlea rdi, [r9+rax*4+8]\nsub esi, 1\nloc_1238:\nmov eax, [rcx]\nadd eax, [rcx+4]\nimul eax, esi\nmovsxd rdx, eax\nimul rdx, 44B82F99h\nsar rdx, 3Ch\nmov r10d, eax\nsar r10d, 1Fh\nsub edx, r10d\nimul edx, 3B9ACA07h\nsub eax, edx\nmov [rcx+8], eax\nadd rcx, 4\ncmp rcx, rdi\njnz short loc_1238\nloc_126C:\nmovsxd r8, r8d\nmov eax, [r9+r8*4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_1284\nleave\nretn\nloc_1284:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(int a1, int a2)\n{\n signed __int64 v3; // rax\n void *v4; // rsp\n unsigned __int64 v5; // rax\n char *v6; // rcx\n char *v7; // rdi\n int v8; // esi\n _BYTE v11[3]; // [rsp+8h] [rbp-10h] BYREF\n char v12; // [rsp+Bh] [rbp-Dh] BYREF\n int v13; // [rsp+Ch] [rbp-Ch] BYREF\n unsigned __int64 v14; // [rsp+10h] [rbp-8h] BYREF\n\n v14 = __readfsqword(0x28u);\n while ( v11 != &v11[-((4LL * (a1 + 1) + 15) & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = (4 * ((_WORD)a1 + 1) + 15) & 0xFF0;\n v4 = alloca(v3);\n if ( ((4 * ((_WORD)a1 + 1) + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v11[v3 - 8] = *(_QWORD *)&v11[v3 - 8];\n v5 = (unsigned __int64)&v12 >> 2;\n *(_DWORD *)(4 * v5) = 0;\n *(_DWORD *)&byte_4[4 * v5] = a2;\n *(_DWORD *)&byte_8[4 * v5] = a2 * a2;\n if ( a1 > 2 )\n {\n v6 = (char *)&v13;\n v7 = (char *)&v14 + 4 * (unsigned int)(a1 - 3);\n v8 = a2 - 1;\n do\n {\n *((_DWORD *)v6 + 2) = v8 * (*((_DWORD *)v6 + 1) + *(_DWORD *)v6) % 1000000007;\n v6 += 4;\n }\n while ( v6 != v7 );\n }\n return *(unsigned int *)&v11[4 * a1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(int a1, int a2) {\n signed long long v3;\n void *v4;\n unsigned long long v5;\n char *v6;\n char *v7;\n int v8;\n uint8_t v11[3];\n char v12;\n int v13;\n unsigned long long v14;\n v14 = __readfsqword(40u);\n while (v11 != &v11[-((4LL * (a1 + 1) + 15) & 18446744073709547520LL)])\n ;\n v3 = (4 * ((unsigned short)a1 + 1) + 15) & 4080;\n v4 = alloca(v3);\n if (((4 * ((unsigned short)a1 + 1) + 15) & 4080) != 0)\n *(uint64_t *)&v11[v3 - 8] = *(uint64_t *)&v11[v3 - 8];\n v5 = (unsigned long long)&v12 >> 2;\n *(uint32_t *)(4 * v5) = 0;\n *(uint32_t *)&byte_4[4 * v5] = a2;\n *(uint32_t *)&byte_8[4 * v5] = a2 * a2;\n if (a1 > 2) {\n v6 = (char *)&v13;\n v7 = (char *)&v14 + 4 * (unsigned int)(a1 - 3);\n v8 = a2 - 1;\n do {\n *((uint32_t *)v6 + 2) =\n v8 * (*((uint32_t *)v6 + 1) + *(uint32_t *)v6) % 1000000007;\n v6 += 4;\n } while (v6 != v7);\n }\n return *(unsigned int *)&v11[4 * a1];\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n signed long long v3;\n void *v4;\n unsigned long long v5;\n char *v6;\n char *v7;\n int v8;\n uint8_t v11[3];\n char v12;\n int v13;\n unsigned long long v14;\n v14 = __readfsqword(40u);\n while (v11 != &v11[-((4LL * (a1 + 1) + 15) & 18446744073709547520LL)])\n ;\n v3 = (4 * ((unsigned short)a1 + 1) + 15) & 4080;\n v4 = alloca(v3);\n if (((4 * ((unsigned short)a1 + 1) + 15) & 4080) != 0)\n *(uint64_t *)&v11[v3 - 8] = *(uint64_t *)&v11[v3 - 8];\n v5 = (unsigned long long)&v12 >> 2;\n *(uint32_t *)(4 * v5) = 0;\n *(uint32_t *)&byte_4[4 * v5] = a2;\n *(uint32_t *)&byte_8[4 * v5] = a2 * a2;\n if (a1 > 2) {\n v6 = (char *)&v13;\n v7 = (char *)&v14 + 4 * (unsigned int)(a1 - 3);\n v8 = a2 - 1;\n do {\n *((uint32_t *)v6 + 2) =\n v8 * (*((uint32_t *)v6 + 1) + *(uint32_t *)v6) % 1000000007;\n v6 += 4;\n } while (v6 != v7);\n }\n return *(unsigned int *)&v11[4 * a1];\n}" + }, + { + "index": 291, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n#define MOD 1000000007\n\n\n\n", + "func": "int func0(int n, int k) {\n int dp[n + 1];\n dp[0] = 0;\n dp[1] = k;\n dp[2] = k * k;\n for (int i = 3; i <= n; i++) {\n dp[i] = ((k - 1) * (dp[i - 1] + dp[i - 2])) % MOD;\n }\n return dp[n];\n}", + "test": "int main() {\n\n assert(func0(2, 4) == 16);\n\n assert(func0(3, 2) == 6);\n\n assert(func0(4, 4) == 228);\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0x1(%rdi),%eax\nmov %rsp,%rcx\ncltq\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rcx\nand $0xfffffffffffffff0,%rdx\nmov %rcx,%rax\ncmp %rax,%rsp\nje 11e8 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 11d3 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 1290 \nmov %esi,%eax\nlea 0x3(%rsp),%r10\nimul %esi,%eax\nmov %r10,%rdx\nand $0xfffffffffffffffc,%r10\nshr $0x2,%rdx\nmovl $0x0,0x0(,%rdx,4)\nmov %esi,0x4(,%rdx,4)\nmov %eax,0x8(,%rdx,4)\ncmp $0x2,%edi\njle 1273 \nlea -0x3(%rdi),%edx\nlea -0x1(%rsi),%r9d\nlea 0xc(%r10),%rcx\nlea 0xc(%r10,%rdx,4),%r8\njmp 1247 \nmov -0x4(%rcx),%esi\nadd $0x4,%rcx\nadd %eax,%esi\nimul %r9d,%esi\nmovslq %esi,%rax\nmov %esi,%edx\nimul $0x44b82f99,%rax,%rax\nsar $0x1f,%edx\nsar $0x3c,%rax\nsub %edx,%eax\nimul $0x3b9aca07,%eax,%edx\nmov %esi,%eax\nsub %edx,%eax\nmov %eax,(%rcx)\ncmp %r8,%rcx\njne 1240 \nmovslq %edi,%rdi\nmov (%r10,%rdi,4),%eax\nmov -0x8(%rbp),%rdi\nxor %fs:0x28,%rdi\njne 129b \nleaveq\nretq\nnopl 0x0(%rax,%rax,1)\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 11fa \ncallq 1070 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmovsxd r10, edi\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea eax, [r10+1]\nmov rcx, rsp\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_12A9\nloc_1294:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rcx\njnz short loc_1294\nloc_12A9:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1350\nloc_12BB:\nmov eax, esi\nlea r11, [rsp+1010h+var_100D]\nimul eax, esi\nmov rdx, r11\nand r11, 0FFFFFFFFFFFFFFFCh\nshr rdx, 2\nmov ds:dword_0[rdx*4], 0\nmov dword ptr ds:byte_4[rdx*4], esi\nmov dword ptr ds:byte_8[rdx*4], eax\ncmp r10d, 2\njle short loc_1334\nlea edx, [r10-3]\nlea r9d, [rsi-1]\nlea rcx, [r11+0Ch]\nlea r8, [r11+rdx*4+10h]\nloc_1300:\nlea edx, [rsi+rax]\nmov esi, eax\nadd rcx, 4\nimul edx, r9d\nmovsxd rax, edx\nmov edi, edx\nimul rax, 44B82F99h\nsar edi, 1Fh\nsar rax, 3Ch\nsub eax, edi\nimul edi, eax, 3B9ACA07h\nmov eax, edx\nsub eax, edi\nmov [rcx-4], eax\ncmp r8, rcx\njnz short loc_1300\nloc_1334:\nmov eax, [r11+r10*4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_135B\nleave\nretn\nloc_1350:\nor [rsp+rdx+1010h+var_1018], 0\njmp loc_12BB\nloc_135B:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n __int64 v2; // rdx\n _BYTE *v3; // rcx\n __int16 v4; // dx\n signed __int64 v5; // rdx\n void *v6; // rsp\n int v7; // eax\n unsigned __int64 v8; // rdx\n int v9; // r9d\n _BYTE *v10; // rcx\n int v11; // edx\n _BYTE v14[3]; // [rsp+8h] [rbp-1010h] BYREF\n char v15; // [rsp+Bh] [rbp-100Dh] BYREF\n _BYTE v16[4076]; // [rsp+14h] [rbp-1004h] BYREF\n _QWORD v17[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v17[1] = __readfsqword(0x28u);\n v2 = 4LL * (a1 + 1) + 15;\n v3 = (char *)v17 - (v2 & 0xFFFFFFFFFFFFF000LL);\n v4 = v2 & 0xFFF0;\n if ( v17 != (_QWORD *)v3 )\n {\n while ( v14 != v3 )\n ;\n }\n v5 = v4 & 0xFFF;\n v6 = alloca(v5);\n if ( v5 )\n *(_QWORD *)&v14[v5 - 8] = *(_QWORD *)&v14[v5 - 8];\n v7 = a2 * a2;\n v8 = (unsigned __int64)&v15 >> 2;\n *(_DWORD *)(4 * v8) = 0;\n *(_DWORD *)&byte_4[4 * v8] = a2;\n *(_DWORD *)&byte_8[4 * v8] = a2 * a2;\n if ( a1 > 2 )\n {\n v9 = a2 - 1;\n v10 = v16;\n do\n {\n v11 = a2 + v7;\n a2 = v7;\n v10 += 4;\n v7 = v9 * v11 % 1000000007;\n *((_DWORD *)v10 - 1) = v7;\n }\n while ( &v16[4 * (a1 - 3) + 4] != v10 );\n }\n return *(unsigned int *)&v14[4 * a1];\n}", + "ida_strip_asm": "sub_1250:\nendbr64\npush rbp\nmovsxd r10, edi\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea eax, [r10+1]\nmov rcx, rsp\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_12A9\nloc_1294:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rcx\njnz short loc_1294\nloc_12A9:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1350\nloc_12BB:\nmov eax, esi\nlea r11, [rsp+1010h+var_100D]\nimul eax, esi\nmov rdx, r11\nand r11, 0FFFFFFFFFFFFFFFCh\nshr rdx, 2\nmov ds:dword_0[rdx*4], 0\nmov dword ptr ds:byte_4[rdx*4], esi\nmov dword ptr ds:byte_8[rdx*4], eax\ncmp r10d, 2\njle short loc_1334\nlea edx, [r10-3]\nlea r9d, [rsi-1]\nlea rcx, [r11+0Ch]\nlea r8, [r11+rdx*4+10h]\nloc_1300:\nlea edx, [rsi+rax]\nmov esi, eax\nadd rcx, 4\nimul edx, r9d\nmovsxd rax, edx\nmov edi, edx\nimul rax, 44B82F99h\nsar edi, 1Fh\nsar rax, 3Ch\nsub eax, edi\nimul edi, eax, 3B9ACA07h\nmov eax, edx\nsub eax, edi\nmov [rcx-4], eax\ncmp r8, rcx\njnz short loc_1300\nloc_1334:\nmov eax, [r11+r10*4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_135B\nleave\nretn\nloc_1350:\nor [rsp+rdx+1010h+var_1018], 0\njmp loc_12BB\nloc_135B:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1250(int a1, int a2)\n{\n __int64 v2; // rdx\n _BYTE *v3; // rcx\n __int16 v4; // dx\n signed __int64 v5; // rdx\n void *v6; // rsp\n int v7; // eax\n unsigned __int64 v8; // rdx\n int v9; // r9d\n _BYTE *v10; // rcx\n int v11; // edx\n _BYTE v14[3]; // [rsp+8h] [rbp-1010h] BYREF\n char v15; // [rsp+Bh] [rbp-100Dh] BYREF\n _BYTE v16[4076]; // [rsp+14h] [rbp-1004h] BYREF\n _QWORD v17[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v17[1] = __readfsqword(0x28u);\n v2 = 4LL * (a1 + 1) + 15;\n v3 = (char *)v17 - (v2 & 0xFFFFFFFFFFFFF000LL);\n v4 = v2 & 0xFFF0;\n if ( v17 != (_QWORD *)v3 )\n {\n while ( v14 != v3 )\n ;\n }\n v5 = v4 & 0xFFF;\n v6 = alloca(v5);\n if ( v5 )\n *(_QWORD *)&v14[v5 - 8] = *(_QWORD *)&v14[v5 - 8];\n v7 = a2 * a2;\n v8 = (unsigned __int64)&v15 >> 2;\n *(_DWORD *)(4 * v8) = 0;\n *(_DWORD *)&byte_4[4 * v8] = a2;\n *(_DWORD *)&byte_8[4 * v8] = a2 * a2;\n if ( a1 > 2 )\n {\n v9 = a2 - 1;\n v10 = v16;\n do\n {\n v11 = a2 + v7;\n a2 = v7;\n v10 += 4;\n v7 = v9 * v11 % 1000000007;\n *((_DWORD *)v10 - 1) = v7;\n }\n while ( &v16[4 * (a1 - 3) + 4] != v10 );\n }\n return *(unsigned int *)&v14[4 * a1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1250(int a1, int a2) {\n long long v2;\n uint8_t *v3;\n short v4;\n signed long long v5;\n void *v6;\n int v7;\n unsigned long long v8;\n int v9;\n uint8_t *v10;\n int v11;\n uint8_t v14[3];\n char v15;\n uint8_t v16[4076];\n uint64_t v17[2];\n v17[1] = __readfsqword(40u);\n v2 = 4LL * (a1 + 1) + 15;\n v3 = (char *)v17 - (v2 & 18446744073709547520LL);\n v4 = v2 & 65520;\n if (v17 != (uint64_t *)v3) {\n while (v14 != v3)\n ;\n }\n v5 = v4 & 4095;\n v6 = alloca(v5);\n if (v5) *(uint64_t *)&v14[v5 - 8] = *(uint64_t *)&v14[v5 - 8];\n v7 = a2 * a2;\n v8 = (unsigned long long)&v15 >> 2;\n *(uint32_t *)(4 * v8) = 0;\n *(uint32_t *)&byte_4[4 * v8] = a2;\n *(uint32_t *)&byte_8[4 * v8] = a2 * a2;\n if (a1 > 2) {\n v9 = a2 - 1;\n v10 = v16;\n do {\n v11 = a2 + v7;\n a2 = v7;\n v10 += 4;\n v7 = v9 * v11 % 1000000007;\n *((uint32_t *)v10 - 1) = v7;\n } while (&v16[4 * (a1 - 3) + 4] != v10);\n }\n return *(unsigned int *)&v14[4 * a1];\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n long long v2;\n uint8_t *v3;\n short v4;\n signed long long v5;\n void *v6;\n int v7;\n unsigned long long v8;\n int v9;\n uint8_t *v10;\n int v11;\n uint8_t v14[3];\n char v15;\n uint8_t v16[4076];\n uint64_t v17[2];\n v17[1] = __readfsqword(40u);\n v2 = 4LL * (a1 + 1) + 15;\n v3 = (char *)v17 - (v2 & 18446744073709547520LL);\n v4 = v2 & 65520;\n if (v17 != (uint64_t *)v3) {\n while (v14 != v3)\n ;\n }\n v5 = v4 & 4095;\n v6 = alloca(v5);\n if (v5) *(uint64_t *)&v14[v5 - 8] = *(uint64_t *)&v14[v5 - 8];\n v7 = a2 * a2;\n v8 = (unsigned long long)&v15 >> 2;\n *(uint32_t *)(4 * v8) = 0;\n *(uint32_t *)&byte_4[4 * v8] = a2;\n *(uint32_t *)&byte_8[4 * v8] = a2 * a2;\n if (a1 > 2) {\n v9 = a2 - 1;\n v10 = v16;\n do {\n v11 = a2 + v7;\n a2 = v7;\n v10 += 4;\n v7 = v9 * v11 % 1000000007;\n *((uint32_t *)v10 - 1) = v7;\n } while (&v16[4 * (a1 - 3) + 4] != v10);\n }\n return *(unsigned int *)&v14[4 * a1];\n}" + }, + { + "index": 291, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n#define MOD 1000000007\n\n\n\n", + "func": "int func0(int n, int k) {\n int dp[n + 1];\n dp[0] = 0;\n dp[1] = k;\n dp[2] = k * k;\n for (int i = 3; i <= n; i++) {\n dp[i] = ((k - 1) * (dp[i - 1] + dp[i - 2])) % MOD;\n }\n return dp[n];\n}", + "test": "int main() {\n\n assert(func0(2, 4) == 16);\n\n assert(func0(3, 2) == 6);\n\n assert(func0(4, 4) == 228);\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0x1(%rdi),%eax\nmov %rsp,%rcx\ncltq\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rcx\nand $0xfffffffffffffff0,%rdx\nmov %rcx,%rax\ncmp %rax,%rsp\nje 11e8 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 11d3 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 1300 \nmov %esi,%eax\nlea 0x3(%rsp),%r8\nimul %esi,%eax\nmov %r8,%rdx\nand $0xfffffffffffffffc,%r8\nshr $0x2,%rdx\nmovl $0x0,0x0(,%rdx,4)\nmov %esi,0x4(,%rdx,4)\nmov %eax,0x8(,%rdx,4)\ncmp $0x2,%edi\njle 12e7 \nlea -0x1(%rsi),%r9d\ncmp $0x4,%edi\njle 130b \nlea -0x5(%rdi),%edx\nmov $0x5,%r10d\nshr %edx\nlea 0x7(%rdx,%rdx,1),%r11\nlea (%rsi,%rax,1),%edx\nimul %r9d,%edx\nmovslq %edx,%rsi\nmov %edx,%ecx\nimul $0x44b82f99,%rsi,%rsi\nsar $0x1f,%ecx\nsar $0x3c,%rsi\nsub %ecx,%esi\nimul $0x3b9aca07,%esi,%esi\nsub %esi,%edx\nmov %edx,-0x8(%r8,%r10,4)\nmov %edx,%esi\nlea (%rdx,%rax,1),%edx\nimul %r9d,%edx\nmovslq %edx,%rax\nmov %edx,%ecx\nimul $0x44b82f99,%rax,%rax\nsar $0x1f,%ecx\nsar $0x3c,%rax\nsub %ecx,%eax\nmovslq %r10d,%rcx\nimul $0x3b9aca07,%eax,%eax\nsub %eax,%edx\nmov %edx,-0x4(%r8,%r10,4)\nadd $0x2,%r10\nmov %edx,%eax\ncmp %r10,%r11\njne 124e \nmov -0x4(%r8,%rcx,4),%eax\nadd -0x8(%r8,%rcx,4),%eax\nimul %r9d,%eax\nmovslq %eax,%rdx\nmov %eax,%esi\nimul $0x44b82f99,%rdx,%rdx\nsar $0x1f,%esi\nsar $0x3c,%rdx\nsub %esi,%edx\nimul $0x3b9aca07,%edx,%edx\nsub %edx,%eax\nmov %eax,(%r8,%rcx,4)\nadd $0x1,%rcx\ncmp %ecx,%edi\njge 12b0 \nmovslq %edi,%rdi\nmov (%r8,%rdi,4),%eax\nmov -0x8(%rbp),%rdi\nxor %fs:0x28,%rdi\njne 1312 \nleaveq\nretq\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 11fa \nmov $0x3,%ecx\njmp 12b0 \ncallq 1070 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov eax, esi\nmov rbp, rsp\nsub rsp, 10h\nmov rdx, fs:28h\nmov [rbp+var_8], rdx\nxor edx, edx\nlea edx, [rdi+1]\nmov rsi, rsp\nmovsxd rdx, edx\nlea rdx, ds:0Fh[rdx*4]\nmov rcx, rdx\nand rdx, 0FFFFFFFFFFFFF000h\nsub rsi, rdx\nand rcx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rsi\njz short loc_12A9\nloc_1294:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rsi\njnz short loc_1294\nloc_12A9:\nand ecx, 0FFFh\nsub rsp, rcx\ntest rcx, rcx\njnz loc_13E0\nloc_12BB:\nmov edx, eax\nlea rsi, [rsp+1010h+var_100D]\nimul edx, eax\nmov rcx, rsi\nand rsi, 0FFFFFFFFFFFFFFFCh\nshr rcx, 2\nmov ds:dword_0[rcx*4], 0\nmov dword ptr ds:byte_4[rcx*4], eax\nmov dword ptr ds:byte_8[rcx*4], edx\ncmp edi, 2\njle loc_13BF\nlea r8d, [rax-1]\ncmp edi, 4\njle loc_13EB\nlea ecx, [rdi-5]\nmov r9d, 5\nshr ecx, 1\nlea r10d, [rcx+rcx]\nadd r10, 7\nloc_1312:\nlea ecx, [rax+rdx]\nimul ecx, r8d\nmovsxd rax, ecx\nmov r11d, ecx\nimul rax, 44B82F99h\nsar r11d, 1Fh\nsar rax, 3Ch\nsub eax, r11d\nimul r11d, eax, 3B9ACA07h\nmov eax, ecx\nsub eax, r11d\nlea ecx, [rax+rdx]\nmov [rsi+r9*4-8], eax\nimul ecx, r8d\nmovsxd rdx, ecx\nmov r11d, ecx\nimul rdx, 44B82F99h\nsar r11d, 1Fh\nsar rdx, 3Ch\nsub edx, r11d\nimul r11d, edx, 3B9ACA07h\nsub ecx, r11d\nmov [rsi+r9*4-4], ecx\nmov edx, ecx\nmov rcx, r9\nadd r9, 2\ncmp r10, r9\njnz short loc_1312\nloc_137E:\nmovsxd rcx, ecx\nnop dword ptr [rax+00000000h]\nloc_1388:\nmov eax, [rsi+rcx*4-8]\nadd eax, [rsi+rcx*4-4]\nimul eax, r8d\nmovsxd rdx, eax\nmov r9d, eax\nimul rdx, 44B82F99h\nsar r9d, 1Fh\nsar rdx, 3Ch\nsub edx, r9d\nimul edx, 3B9ACA07h\nsub eax, edx\nmov [rsi+rcx*4], eax\nadd rcx, 1\ncmp edi, ecx\njge short loc_1388\nloc_13BF:\nmovsxd rdi, edi\nmov eax, [rsi+rdi*4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_13F2\nleave\nretn\nloc_13E0:\nor [rsp+rcx+1010h+var_1018], 0\njmp loc_12BB\nloc_13EB:\nmov ecx, 3\njmp short loc_137E\nloc_13F2:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n __int64 v3; // rcx\n _BYTE *v4; // rsi\n __int16 v5; // cx\n signed __int64 v6; // rcx\n void *v7; // rsp\n int v8; // edx\n unsigned __int64 v9; // rcx\n int v10; // r8d\n __int64 v11; // r9\n __int64 v12; // rcx\n _BYTE v15[3]; // [rsp+8h] [rbp-1010h] BYREF\n char v16; // [rsp+Bh] [rbp-100Dh] BYREF\n _QWORD v17[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v17[1] = __readfsqword(0x28u);\n v3 = 4LL * (a1 + 1) + 15;\n v4 = (char *)v17 - (v3 & 0xFFFFFFFFFFFFF000LL);\n v5 = v3 & 0xFFF0;\n if ( v17 != (_QWORD *)v4 )\n {\n while ( v15 != v4 )\n ;\n }\n v6 = v5 & 0xFFF;\n v7 = alloca(v6);\n if ( v6 )\n *(_QWORD *)&v15[v6 - 8] = *(_QWORD *)&v15[v6 - 8];\n v8 = a2 * a2;\n v9 = (unsigned __int64)&v16 >> 2;\n *(_DWORD *)(4 * v9) = 0;\n *(_DWORD *)&byte_4[4 * v9] = a2;\n *(_DWORD *)&byte_8[4 * v9] = a2 * a2;\n if ( a1 > 2 )\n {\n v10 = a2 - 1;\n if ( a1 <= 4 )\n {\n LODWORD(v12) = 3;\n }\n else\n {\n v11 = 5LL;\n do\n {\n a2 = v10 * (a2 + v8) % 1000000007;\n *(_DWORD *)&v15[4 * v11 - 8] = a2;\n *(_DWORD *)&v15[4 * v11 - 4] = v10 * (a2 + v8) % 1000000007;\n v8 = v10 * (a2 + v8) % 1000000007;\n LODWORD(v12) = v11;\n v11 += 2LL;\n }\n while ( 2 * ((unsigned int)(a1 - 5) >> 1) + 7LL != v11 );\n }\n v12 = (int)v12;\n do\n {\n *(_DWORD *)&v15[4 * v12] = v10 * (*(_DWORD *)&v15[4 * v12 - 4] + *(_DWORD *)&v15[4 * v12 - 8]) % 1000000007;\n ++v12;\n }\n while ( a1 >= (int)v12 );\n }\n return *(unsigned int *)&v15[4 * a1];\n}", + "ida_strip_asm": "sub_1250:\nendbr64\npush rbp\nmov eax, esi\nmov rbp, rsp\nsub rsp, 10h\nmov rdx, fs:28h\nmov [rbp+var_8], rdx\nxor edx, edx\nlea edx, [rdi+1]\nmov rsi, rsp\nmovsxd rdx, edx\nlea rdx, ds:0Fh[rdx*4]\nmov rcx, rdx\nand rdx, 0FFFFFFFFFFFFF000h\nsub rsi, rdx\nand rcx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rsi\njz short loc_12A9\nloc_1294:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rsi\njnz short loc_1294\nloc_12A9:\nand ecx, 0FFFh\nsub rsp, rcx\ntest rcx, rcx\njnz loc_13E0\nloc_12BB:\nmov edx, eax\nlea rsi, [rsp+1010h+var_100D]\nimul edx, eax\nmov rcx, rsi\nand rsi, 0FFFFFFFFFFFFFFFCh\nshr rcx, 2\nmov ds:dword_0[rcx*4], 0\nmov dword ptr ds:byte_4[rcx*4], eax\nmov dword ptr ds:byte_8[rcx*4], edx\ncmp edi, 2\njle loc_13BF\nlea r8d, [rax-1]\ncmp edi, 4\njle loc_13EB\nlea ecx, [rdi-5]\nmov r9d, 5\nshr ecx, 1\nlea r10d, [rcx+rcx]\nadd r10, 7\nloc_1312:\nlea ecx, [rax+rdx]\nimul ecx, r8d\nmovsxd rax, ecx\nmov r11d, ecx\nimul rax, 44B82F99h\nsar r11d, 1Fh\nsar rax, 3Ch\nsub eax, r11d\nimul r11d, eax, 3B9ACA07h\nmov eax, ecx\nsub eax, r11d\nlea ecx, [rax+rdx]\nmov [rsi+r9*4-8], eax\nimul ecx, r8d\nmovsxd rdx, ecx\nmov r11d, ecx\nimul rdx, 44B82F99h\nsar r11d, 1Fh\nsar rdx, 3Ch\nsub edx, r11d\nimul r11d, edx, 3B9ACA07h\nsub ecx, r11d\nmov [rsi+r9*4-4], ecx\nmov edx, ecx\nmov rcx, r9\nadd r9, 2\ncmp r10, r9\njnz short loc_1312\nloc_137E:\nmovsxd rcx, ecx\nnop dword ptr [rax+00000000h]\nloc_1388:\nmov eax, [rsi+rcx*4-8]\nadd eax, [rsi+rcx*4-4]\nimul eax, r8d\nmovsxd rdx, eax\nmov r9d, eax\nimul rdx, 44B82F99h\nsar r9d, 1Fh\nsar rdx, 3Ch\nsub edx, r9d\nimul edx, 3B9ACA07h\nsub eax, edx\nmov [rsi+rcx*4], eax\nadd rcx, 1\ncmp edi, ecx\njge short loc_1388\nloc_13BF:\nmovsxd rdi, edi\nmov eax, [rsi+rdi*4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_13F2\nleave\nretn\nloc_13E0:\nor [rsp+rcx+1010h+var_1018], 0\njmp loc_12BB\nloc_13EB:\nmov ecx, 3\njmp short loc_137E\nloc_13F2:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1250(int a1, int a2)\n{\n __int64 v3; // rcx\n _BYTE *v4; // rsi\n __int16 v5; // cx\n signed __int64 v6; // rcx\n void *v7; // rsp\n int v8; // edx\n unsigned __int64 v9; // rcx\n int v10; // r8d\n __int64 v11; // r9\n __int64 v12; // rcx\n _BYTE v15[3]; // [rsp+8h] [rbp-1010h] BYREF\n char v16; // [rsp+Bh] [rbp-100Dh] BYREF\n _QWORD v17[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v17[1] = __readfsqword(0x28u);\n v3 = 4LL * (a1 + 1) + 15;\n v4 = (char *)v17 - (v3 & 0xFFFFFFFFFFFFF000LL);\n v5 = v3 & 0xFFF0;\n if ( v17 != (_QWORD *)v4 )\n {\n while ( v15 != v4 )\n ;\n }\n v6 = v5 & 0xFFF;\n v7 = alloca(v6);\n if ( v6 )\n *(_QWORD *)&v15[v6 - 8] = *(_QWORD *)&v15[v6 - 8];\n v8 = a2 * a2;\n v9 = (unsigned __int64)&v16 >> 2;\n *(_DWORD *)(4 * v9) = 0;\n *(_DWORD *)&byte_4[4 * v9] = a2;\n *(_DWORD *)&byte_8[4 * v9] = a2 * a2;\n if ( a1 > 2 )\n {\n v10 = a2 - 1;\n if ( a1 <= 4 )\n {\n LODWORD(v12) = 3;\n }\n else\n {\n v11 = 5LL;\n do\n {\n a2 = v10 * (a2 + v8) % 1000000007;\n *(_DWORD *)&v15[4 * v11 - 8] = a2;\n *(_DWORD *)&v15[4 * v11 - 4] = v10 * (a2 + v8) % 1000000007;\n v8 = v10 * (a2 + v8) % 1000000007;\n LODWORD(v12) = v11;\n v11 += 2LL;\n }\n while ( 2 * ((unsigned int)(a1 - 5) >> 1) + 7LL != v11 );\n }\n v12 = (int)v12;\n do\n {\n *(_DWORD *)&v15[4 * v12] = v10 * (*(_DWORD *)&v15[4 * v12 - 4] + *(_DWORD *)&v15[4 * v12 - 8]) % 1000000007;\n ++v12;\n }\n while ( a1 >= (int)v12 );\n }\n return *(unsigned int *)&v15[4 * a1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1250(int a1, int a2) {\n long long v3;\n uint8_t *v4;\n short v5;\n signed long long v6;\n void *v7;\n int v8;\n unsigned long long v9;\n int v10;\n long long v11;\n long long v12;\n uint8_t v15[3];\n char v16;\n uint64_t v17[2];\n v17[1] = __readfsqword(40u);\n v3 = 4LL * (a1 + 1) + 15;\n v4 = (char *)v17 - (v3 & 18446744073709547520LL);\n v5 = v3 & 65520;\n if (v17 != (uint64_t *)v4) {\n while (v15 != v4)\n ;\n }\n v6 = v5 & 4095;\n v7 = alloca(v6);\n if (v6) *(uint64_t *)&v15[v6 - 8] = *(uint64_t *)&v15[v6 - 8];\n v8 = a2 * a2;\n v9 = (unsigned long long)&v16 >> 2;\n *(uint32_t *)(4 * v9) = 0;\n *(uint32_t *)&byte_4[4 * v9] = a2;\n *(uint32_t *)&byte_8[4 * v9] = a2 * a2;\n if (a1 > 2) {\n v10 = a2 - 1;\n if (a1 <= 4) {\n LODWORD(v12) = 3;\n } else {\n v11 = 5LL;\n do {\n a2 = v10 * (a2 + v8) % 1000000007;\n *(uint32_t *)&v15[4 * v11 - 8] = a2;\n *(uint32_t *)&v15[4 * v11 - 4] = v10 * (a2 + v8) % 1000000007;\n v8 = v10 * (a2 + v8) % 1000000007;\n LODWORD(v12) = v11;\n v11 += 2LL;\n } while (2 * ((unsigned int)(a1 - 5) >> 1) + 7LL != v11);\n }\n v12 = (int)v12;\n do {\n *(uint32_t *)&v15[4 * v12] =\n v10 *\n (*(uint32_t *)&v15[4 * v12 - 4] + *(uint32_t *)&v15[4 * v12 - 8]) %\n 1000000007;\n ++v12;\n } while (a1 >= (int)v12);\n }\n return *(unsigned int *)&v15[4 * a1];\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n long long v3;\n uint8_t *v4;\n short v5;\n signed long long v6;\n void *v7;\n int v8;\n unsigned long long v9;\n int v10;\n long long v11;\n long long v12;\n uint8_t v15[3];\n char v16;\n uint64_t v17[2];\n v17[1] = __readfsqword(40u);\n v3 = 4LL * (a1 + 1) + 15;\n v4 = (char *)v17 - (v3 & 18446744073709547520LL);\n v5 = v3 & 65520;\n if (v17 != (uint64_t *)v4) {\n while (v15 != v4)\n ;\n }\n v6 = v5 & 4095;\n v7 = alloca(v6);\n if (v6) *(uint64_t *)&v15[v6 - 8] = *(uint64_t *)&v15[v6 - 8];\n v8 = a2 * a2;\n v9 = (unsigned long long)&v16 >> 2;\n *(uint32_t *)(4 * v9) = 0;\n *(uint32_t *)&byte_4[4 * v9] = a2;\n *(uint32_t *)&byte_8[4 * v9] = a2 * a2;\n if (a1 > 2) {\n v10 = a2 - 1;\n if (a1 <= 4) {\n LODWORD(v12) = 3;\n } else {\n v11 = 5LL;\n do {\n a2 = v10 * (a2 + v8) % 1000000007;\n *(uint32_t *)&v15[4 * v11 - 8] = a2;\n *(uint32_t *)&v15[4 * v11 - 4] = v10 * (a2 + v8) % 1000000007;\n v8 = v10 * (a2 + v8) % 1000000007;\n LODWORD(v12) = v11;\n v11 += 2LL;\n } while (2 * ((unsigned int)(a1 - 5) >> 1) + 7LL != v11);\n }\n v12 = (int)v12;\n do {\n *(uint32_t *)&v15[4 * v12] =\n v10 *\n (*(uint32_t *)&v15[4 * v12 - 4] + *(uint32_t *)&v15[4 * v12 - 8]) %\n 1000000007;\n ++v12;\n } while (a1 >= (int)v12);\n }\n return *(unsigned int *)&v15[4 * a1];\n}" + }, + { + "index": 292, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int n, int m) {\n int q = n / m;\n return q;\n}", + "test": "int main() {\n\n assert(func0(10, 3) == 3);\n\n assert(func0(4, 2) == 2);\n\n assert(func0(20, 5) == 4);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov -0x14(%rbp),%eax\ncltd\nidivl -0x18(%rbp)\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_18]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n return (unsigned int)(a1 / a2);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_18]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2)\n{\n return (unsigned int)(a1 / a2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2) { return (unsigned int)(a1 / a2); }", + "ida_pseudo_norm": "long long func0(int a1, int a2) { return (unsigned int)(a1 / a2); }" + }, + { + "index": 293, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int w, int h) {\n double s = sqrt((w * w) + (h * h));\n return s;\n}", + "test": "int main() {\n\n assert(func0(7, 8) == 10.63014581273465);\n\n assert(func0(3, 4) == 5);\n\n assert(func0(7, 15) == 16.55294535724685);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov -0x14(%rbp),%eax\nimul %eax,%eax\nmov %eax,%edx\nmov -0x18(%rbp),%eax\nimul %eax,%eax\nadd %edx,%eax\ncvtsi2sd %eax,%xmm0\ncallq 1070 \nmovq %xmm0,%rax\nmov %rax,-0x8(%rbp)\nmovsd -0x8(%rbp),%xmm0\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov eax, [rbp+var_14]\nimul eax, eax\nmov edx, eax\nmov eax, [rbp+var_18]\nimul eax, eax\nadd eax, edx\npxor xmm1, xmm1\ncvtsi2sd xmm1, eax\nmovq rax, xmm1\nmovq xmm0, rax; x\ncall _sqrt\nmovq rax, xmm0\nmov [rbp+var_8], rax\nmovsd xmm0, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n return sqrt((double)(a1 * a1 + a2 * a2));\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov eax, [rbp+var_14]\nimul eax, eax\nmov edx, eax\nmov eax, [rbp+var_18]\nimul eax, eax\nadd eax, edx\npxor xmm1, xmm1\ncvtsi2sd xmm1, eax\nmovq rax, xmm1\nmovq xmm0, rax; x\ncall _sqrt\nmovq rax, xmm0\nmov [rbp+var_8], rax\nmovsd xmm0, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1, int a2)\n{\n return sqrt((double)(a1 * a1 + a2 * a2));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1, int a2) { return sqrt((double)(a1 * a1 + a2 * a2)); }", + "ida_pseudo_norm": "long long func0(int a1, int a2) { return sqrt((double)(a1 * a1 + a2 * a2)); }" + }, + { + "index": 294, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int listval[], int size) {\n int max_val = INT_MIN;\n for (int i = 0; i < size; i++) {\n if (listval[i] > max_val) {\n max_val = listval[i];\n }\n }\n return max_val;\n}", + "test": "int main() {\n\n int array1[] = {3, 2, 4, 5};\n\n int size1 = sizeof(array1)/sizeof(array1[0]);\n\n\n\n int array2[] = {15, 20, 25};\n\n int size2 = sizeof(array2)/sizeof(array2[0]);\n\n\n\n int array3[] = {30, 20, 40, 50};\n\n int size3 = sizeof(array3)/sizeof(array3[0]);\n\n\n\n assert(func0(array1, size1) == 5);\n\n assert(func0(array2, size2) == 25);\n\n assert(func0(array3, size3) == 50);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x80000000,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11c0 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x8(%rbp)\njge 11bc \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1188 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 80000000h\nmov [rbp+var_4], 0\njmp short loc_11C0\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_8], eax\njge short loc_11BC\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_8], eax\nloc_11BC:\nadd [rbp+var_4], 1\nloc_11C0:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0x80000000;\n for ( i = 0; i < a2; ++i )\n {\n if ( (signed int)v3 < *(_DWORD *)(4LL * i + a1) )\n v3 = *(_DWORD *)(4LL * i + a1);\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 80000000h\nmov [rbp+var_4], 0\njmp short loc_11C0\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_8], eax\njge short loc_11BC\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_8], eax\nloc_11BC:\nadd [rbp+var_4], 1\nloc_11C0:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0x80000000;\n for ( i = 0; i < a2; ++i )\n {\n if ( (signed int)v3 < *(_DWORD *)(4LL * i + a1) )\n v3 = *(_DWORD *)(4LL * i + a1);\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 2147483648;\n for (i = 0; i < a2; ++i) {\n if ((signed int)v3 < *(uint32_t *)(4LL * i + a1))\n v3 = *(uint32_t *)(4LL * i + a1);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 2147483648;\n for (i = 0; i < a2; ++i) {\n if ((signed int)v3 < *(uint32_t *)(4LL * i + a1))\n v3 = *(uint32_t *)(4LL * i + a1);\n }\n return v3;\n}" + }, + { + "index": 294, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int listval[], int size) {\n int max_val = INT_MIN;\n for (int i = 0; i < size; i++) {\n if (listval[i] > max_val) {\n max_val = listval[i];\n }\n }\n return max_val;\n}", + "test": "int main() {\n\n int array1[] = {3, 2, 4, 5};\n\n int size1 = sizeof(array1)/sizeof(array1[0]);\n\n\n\n int array2[] = {15, 20, 25};\n\n int size2 = sizeof(array2)/sizeof(array2[0]);\n\n\n\n int array3[] = {30, 20, 40, 50};\n\n int size3 = sizeof(array3)/sizeof(array3[0]);\n\n\n\n assert(func0(array1, size1) == 5);\n\n assert(func0(array2, size2) == 25);\n\n assert(func0(array3, size3) == 50);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1194 \nmov %rdi,%rax\nlea -0x1(%rsi),%edx\nlea 0x4(%rdi,%rdx,4),%rsi\nmov $0x80000000,%edx\nmov (%rax),%ecx\ncmp %ecx,%edx\ncmovl %ecx,%edx\nadd $0x4,%rax\ncmp %rsi,%rax\njne 1181 \nmov %edx,%eax\nretq\nmov $0x80000000,%edx\njmp 1191 \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1193\nmov rax, rdi\nmovsxd rsi, esi\nlea rsi, [rdi+rsi*4]\nmov edx, 80000000h\nloc_1180:\nmov ecx, [rax]\ncmp edx, ecx\ncmovl edx, ecx\nadd rax, 4\ncmp rax, rsi\njnz short loc_1180\nloc_1190:\nmov eax, edx\nretn\nloc_1193:\nmov edx, 80000000h\njmp short loc_1190", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n unsigned int *v2; // rax\n unsigned int *v3; // rsi\n unsigned int v4; // edx\n\n if ( a2 <= 0 )\n {\n return 0x80000000;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0x80000000;\n do\n {\n if ( (int)v4 < (int)*v2 )\n v4 = *v2;\n ++v2;\n }\n while ( v2 != v3 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_1193\nmov rax, rdi\nmovsxd rsi, esi\nlea rsi, [rdi+rsi*4]\nmov edx, 80000000h\nloc_1180:\nmov ecx, [rax]\ncmp edx, ecx\ncmovl edx, ecx\nadd rax, 4\ncmp rax, rsi\njnz short loc_1180\nloc_1190:\nmov eax, edx\nretn\nloc_1193:\nmov edx, 80000000h\njmp short loc_1190", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(unsigned int *a1, int a2)\n{\n unsigned int *v2; // rax\n unsigned int *v3; // rsi\n unsigned int v4; // edx\n\n if ( a2 <= 0 )\n {\n return 0x80000000;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0x80000000;\n do\n {\n if ( (int)v4 < (int)*v2 )\n v4 = *v2;\n ++v2;\n }\n while ( v2 != v3 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(unsigned int *a1, int a2) {\n unsigned int *v2;\n unsigned int *v3;\n unsigned int v4;\n if (a2 <= 0) {\n return 2147483648;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 2147483648;\n do {\n if ((int)v4 < (int)*v2) v4 = *v2;\n ++v2;\n } while (v2 != v3);\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n unsigned int *v2;\n unsigned int *v3;\n unsigned int v4;\n if (a2 <= 0) {\n return 2147483648;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 2147483648;\n do {\n if ((int)v4 < (int)*v2) v4 = *v2;\n ++v2;\n } while (v2 != v3);\n }\n return v4;\n}" + }, + { + "index": 295, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int number) {\n int sum = 1;\n for (int i = 2; i < number; i++) {\n if (number % i == 0) {\n sum += i;\n }\n }\n return sum;\n}", + "test": "int main() {\n\n assert(func0(8) == 7);\n\n assert(func0(12) == 16);\n\n assert(func0(7) == 1);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmovl $0x1,-0x8(%rbp)\nmovl $0x2,-0x4(%rbp)\njmp 117b \nmov -0x14(%rbp),%eax\ncltd\nidivl -0x4(%rbp)\nmov %edx,%eax\ntest %eax,%eax\njne 1177 \nmov -0x4(%rbp),%eax\nadd %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x14(%rbp),%eax\njl 1164 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_8], 1\nmov [rbp+var_4], 2\njmp short loc_117B\nloc_1164:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njnz short loc_1177\nmov eax, [rbp+var_4]\nadd [rbp+var_8], eax\nloc_1177:\nadd [rbp+var_4], 1\nloc_117B:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_14]\njl short loc_1164\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v2; // [rsp+Ch] [rbp-8h]\n int i; // [rsp+10h] [rbp-4h]\n\n v2 = 1;\n for ( i = 2; i < a1; ++i )\n {\n if ( !(a1 % i) )\n v2 += i;\n }\n return v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_8], 1\nmov [rbp+var_4], 2\njmp short loc_117B\nloc_1164:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njnz short loc_1177\nmov eax, [rbp+var_4]\nadd [rbp+var_8], eax\nloc_1177:\nadd [rbp+var_4], 1\nloc_117B:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_14]\njl short loc_1164\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n unsigned int v2; // [rsp+Ch] [rbp-8h]\n int i; // [rsp+10h] [rbp-4h]\n\n v2 = 1;\n for ( i = 2; i < a1; ++i )\n {\n if ( !(a1 % i) )\n v2 += i;\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n unsigned int v2;\n int i;\n v2 = 1;\n for (i = 2; i < a1; ++i) {\n if (!(a1 % i)) v2 += i;\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v2;\n int i;\n v2 = 1;\n for (i = 2; i < a1; ++i) {\n if (!(a1 % i)) v2 += i;\n }\n return v2;\n}" + }, + { + "index": 295, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int number) {\n int sum = 1;\n for (int i = 2; i < number; i++) {\n if (number % i == 0) {\n sum += i;\n }\n }\n return sum;\n}", + "test": "int main() {\n\n assert(func0(8) == 7);\n\n assert(func0(12) == 16);\n\n assert(func0(7) == 1);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x2,%edi\njle 1173 \nmov $0x2,%ecx\nmov $0x1,%esi\nmov %edi,%eax\ncltd\nidiv %ecx\nlea (%rsi,%rcx,1),%eax\ntest %edx,%edx\ncmove %eax,%esi\nadd $0x1,%ecx\ncmp %ecx,%edi\njne 115c \nmov %esi,%eax\nretq\nmov $0x1,%esi\njmp 1170 \n", + "ida_asm": "func0:\nendbr64\ncmp edi, 2\njle short loc_1173\nmov ecx, 2\nmov esi, 1\nloc_115C:\nmov eax, edi\ncdq\nidiv ecx\nlea eax, [rsi+rcx]\ntest edx, edx\ncmovz esi, eax\nadd ecx, 1\ncmp edi, ecx\njnz short loc_115C\nloc_1170:\nmov eax, esi\nretn\nloc_1173:\nmov esi, 1\njmp short loc_1170", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // ecx\n unsigned int v2; // esi\n\n if ( a1 <= 2 )\n {\n return 1;\n }\n else\n {\n v1 = 2;\n v2 = 1;\n do\n {\n if ( !(a1 % v1) )\n v2 += v1;\n ++v1;\n }\n while ( a1 != v1 );\n }\n return v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ncmp edi, 2\njle short loc_1173\nmov ecx, 2\nmov esi, 1\nloc_115C:\nmov eax, edi\ncdq\nidiv ecx\nlea eax, [rsi+rcx]\ntest edx, edx\ncmovz esi, eax\nadd ecx, 1\ncmp edi, ecx\njnz short loc_115C\nloc_1170:\nmov eax, esi\nretn\nloc_1173:\nmov esi, 1\njmp short loc_1170", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v1; // ecx\n unsigned int v2; // esi\n\n if ( a1 <= 2 )\n {\n return 1;\n }\n else\n {\n v1 = 2;\n v2 = 1;\n do\n {\n if ( !(a1 % v1) )\n v2 += v1;\n ++v1;\n }\n while ( a1 != v1 );\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v1;\n unsigned int v2;\n if (a1 <= 2) {\n return 1;\n } else {\n v1 = 2;\n v2 = 1;\n do {\n if (!(a1 % v1)) v2 += v1;\n ++v1;\n } while (a1 != v1);\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n unsigned int v2;\n if (a1 <= 2) {\n return 1;\n } else {\n v1 = 2;\n v2 = 1;\n do {\n if (!(a1 % v1)) v2 += v1;\n ++v1;\n } while (a1 != v1);\n }\n return v2;\n}" + }, + { + "index": 296, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int inv_count = 0;\n for (int i = 0; i < n; i++) {\n for (int j = i + 1; j < n; j++) {\n if (arr[i] > arr[j]) {\n inv_count += 1;\n }\n }\n }\n return inv_count;\n}", + "test": "int main() {\n\n int arr1[] = {1, 20, 6, 4, 5};\n\n int arr2[] = {1, 2, 1};\n\n int arr3[] = {1, 2, 5, 6, 1};\n\n \n\n assert(func0(arr1, 5) == 5);\n\n assert(func0(arr2, 3) == 1);\n\n assert(func0(arr3, 5) == 3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11d7 \nmov -0x8(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x4(%rbp)\njmp 11cb \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njle 11c7 \naddl $0x1,-0xc(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1193 \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1188 \nmov -0xc(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_11D7\nloc_1188:\nmov eax, [rbp+var_8]\nadd eax, 1\nmov [rbp+var_4], eax\njmp short loc_11CB\nloc_1193:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_11C7\nadd [rbp+var_C], 1\nloc_11C7:\nadd [rbp+var_4], 1\nloc_11CB:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1193\nadd [rbp+var_8], 1\nloc_11D7:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+10h] [rbp-Ch]\n int i; // [rsp+14h] [rbp-8h]\n int j; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a1) > *(_DWORD *)(4LL * j + a1) )\n ++v3;\n }\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_11D7\nloc_1188:\nmov eax, [rbp+var_8]\nadd eax, 1\nmov [rbp+var_4], eax\njmp short loc_11CB\nloc_1193:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_11C7\nadd [rbp+var_C], 1\nloc_11C7:\nadd [rbp+var_4], 1\nloc_11CB:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1193\nadd [rbp+var_8], 1\nloc_11D7:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+10h] [rbp-Ch]\n int i; // [rsp+14h] [rbp-8h]\n int j; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a1) > *(_DWORD *)(4LL * j + a1) )\n ++v3;\n }\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n unsigned int v3;\n int i;\n int j;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if (*(uint32_t *)(4LL * i + a1) > *(uint32_t *)(4LL * j + a1)) ++v3;\n }\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n int j;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if (*(uint32_t *)(4LL * i + a1) > *(uint32_t *)(4LL * j + a1)) ++v3;\n }\n }\n return v3;\n}" + }, + { + "index": 296, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int inv_count = 0;\n for (int i = 0; i < n; i++) {\n for (int j = i + 1; j < n; j++) {\n if (arr[i] > arr[j]) {\n inv_count += 1;\n }\n }\n }\n return inv_count;\n}", + "test": "int main() {\n\n int arr1[] = {1, 20, 6, 4, 5};\n\n int arr2[] = {1, 2, 1};\n\n int arr3[] = {1, 2, 5, 6, 1};\n\n \n\n assert(func0(arr1, 5) == 5);\n\n assert(func0(arr2, 3) == 1);\n\n assert(func0(arr3, 5) == 3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11ab \nlea -0x1(%rsi),%r9d\nadd $0x1,%r9\nmov $0x1,%r8d\nmov $0x0,%ecx\njmp 119c \nadd $0x1,%rax\ncmp %eax,%esi\njle 1198 \ncmp (%rdi,%rax,4),%edx\njle 1186 \nadd $0x1,%ecx\njmp 1186 \nadd $0x1,%r8\ncmp %r9,%r8\nje 11b0 \nmov -0x4(%rdi,%r8,4),%edx\nmov %r8,%rax\njmp 118e \nmov $0x0,%ecx\nmov %ecx,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11B1\nmov r9d, esi\nmovsxd r10, esi\nmov r8d, 1\nmov ecx, 0\njmp short loc_11A2\nloc_1184:\nadd rax, 1\ncmp esi, eax\njle short loc_1196\nloc_118C:\ncmp edx, [rdi+rax*4]\njle short loc_1184\nadd ecx, 1\njmp short loc_1184\nloc_1196:\nlea rax, [r8+1]\ncmp r8, r10\njz short loc_11B6\nmov r8, rax\nloc_11A2:\ncmp r8, r9\njz short loc_11B6\nmov edx, [rdi+r8*4-4]\nmov rax, r8\njmp short loc_118C\nloc_11B1:\nmov ecx, 0\nloc_11B6:\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // r8\n unsigned int v3; // ecx\n __int64 v4; // rax\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = 1LL;\n v3 = 0;\n while ( v2 != a2 )\n {\n v4 = v2;\n do\n {\n if ( *(_DWORD *)(a1 + 4 * v2 - 4) > *(_DWORD *)(a1 + 4 * v4) )\n ++v3;\n ++v4;\n }\n while ( a2 > (int)v4 );\n if ( v2 == a2 )\n break;\n ++v2;\n }\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11B1\nmov r9d, esi\nmovsxd r10, esi\nmov r8d, 1\nmov ecx, 0\njmp short loc_11A2\nloc_1184:\nadd rax, 1\ncmp esi, eax\njle short loc_1196\nloc_118C:\ncmp edx, [rdi+rax*4]\njle short loc_1184\nadd ecx, 1\njmp short loc_1184\nloc_1196:\nlea rax, [r8+1]\ncmp r8, r10\njz short loc_11B6\nmov r8, rax\nloc_11A2:\ncmp r8, r9\njz short loc_11B6\nmov edx, [rdi+r8*4-4]\nmov rax, r8\njmp short loc_118C\nloc_11B1:\nmov ecx, 0\nloc_11B6:\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n __int64 v2; // r8\n unsigned int v3; // ecx\n __int64 v4; // rax\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = 1LL;\n v3 = 0;\n while ( v2 != a2 )\n {\n v4 = v2;\n do\n {\n if ( *(_DWORD *)(a1 + 4 * v2 - 4) > *(_DWORD *)(a1 + 4 * v4) )\n ++v3;\n ++v4;\n }\n while ( a2 > (int)v4 );\n if ( v2 == a2 )\n break;\n ++v2;\n }\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n long long v4;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = 1LL;\n v3 = 0;\n while (v2 != a2) {\n v4 = v2;\n do {\n if (*(uint32_t *)(a1 + 4 * v2 - 4) > *(uint32_t *)(a1 + 4 * v4)) ++v3;\n ++v4;\n } while (a2 > (int)v4);\n if (v2 == a2) break;\n ++v2;\n }\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n long long v4;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = 1LL;\n v3 = 0;\n while (v2 != a2) {\n v4 = v2;\n do {\n if (*(uint32_t *)(a1 + 4 * v2 - 4) > *(uint32_t *)(a1 + 4 * v4)) ++v3;\n ++v4;\n } while (a2 > (int)v4);\n if (v2 == a2) break;\n ++v2;\n }\n }\n return v3;\n}" + }, + { + "index": 296, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int inv_count = 0;\n for (int i = 0; i < n; i++) {\n for (int j = i + 1; j < n; j++) {\n if (arr[i] > arr[j]) {\n inv_count += 1;\n }\n }\n }\n return inv_count;\n}", + "test": "int main() {\n\n int arr1[] = {1, 20, 6, 4, 5};\n\n int arr2[] = {1, 2, 1};\n\n int arr3[] = {1, 2, 5, 6, 1};\n\n \n\n assert(func0(arr1, 5) == 5);\n\n assert(func0(arr2, 3) == 1);\n\n assert(func0(arr3, 5) == 3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 137e \nlea -0x1(%rsi),%r9d\nmov $0x1,%ecx\nxor %r8d,%r8d\nadd $0x1,%r9\ncmp %r9,%rcx\nje 137a \nnopl (%rax)\nmov -0x4(%rdi,%rcx,4),%edx\nmov %rcx,%rax\nnopw 0x0(%rax,%rax,1)\ncmp (%rdi,%rax,4),%edx\njle 1369 \nadd $0x1,%r8d\nadd $0x1,%rax\ncmp %eax,%esi\njg 1360 \nadd $0x1,%rcx\ncmp %r9,%rcx\njne 1350 \nmov %r8d,%eax\nretq\nxor %r8d,%r8d\nmov %r8d,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_12CC\nmov r9d, esi\nmov r8d, 1\nxor ecx, ecx\ncmp esi, 1\njz short loc_12C9\nnop dword ptr [rax+rax+00000000h]\nloc_12A0:\nmov edx, [rdi+r8*4-4]\nmov rax, r8\nnop dword ptr [rax+rax+00000000h]\nloc_12B0:\ncmp edx, [rdi+rax*4]\njle short loc_12B8\nadd ecx, 1\nloc_12B8:\nadd rax, 1\ncmp esi, eax\njg short loc_12B0\nadd r8, 1\ncmp r8, r9\njnz short loc_12A0\nloc_12C9:\nmov eax, ecx\nretn\nloc_12CC:\nxor ecx, ecx\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // r8\n unsigned int v3; // ecx\n __int64 v4; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 1LL;\n v3 = 0;\n if ( a2 != 1 )\n {\n do\n {\n v4 = v2;\n do\n {\n if ( *(_DWORD *)(a1 + 4 * v2 - 4) > *(_DWORD *)(a1 + 4 * v4) )\n ++v3;\n ++v4;\n }\n while ( a2 > (int)v4 );\n ++v2;\n }\n while ( v2 != a2 );\n }\n return v3;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\ntest esi, esi\njle short loc_12CC\nmov r9d, esi\nmov r8d, 1\nxor ecx, ecx\ncmp esi, 1\njz short loc_12C9\nnop dword ptr [rax+rax+00000000h]\nloc_12A0:\nmov edx, [rdi+r8*4-4]\nmov rax, r8\nnop dword ptr [rax+rax+00000000h]\nloc_12B0:\ncmp edx, [rdi+rax*4]\njle short loc_12B8\nadd ecx, 1\nloc_12B8:\nadd rax, 1\ncmp esi, eax\njg short loc_12B0\nadd r8, 1\ncmp r8, r9\njnz short loc_12A0\nloc_12C9:\nmov eax, ecx\nretn\nloc_12CC:\nxor ecx, ecx\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1280(__int64 a1, int a2)\n{\n __int64 v2; // r8\n unsigned int v3; // ecx\n __int64 v4; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 1LL;\n v3 = 0;\n if ( a2 != 1 )\n {\n do\n {\n v4 = v2;\n do\n {\n if ( *(_DWORD *)(a1 + 4 * v2 - 4) > *(_DWORD *)(a1 + 4 * v4) )\n ++v3;\n ++v4;\n }\n while ( a2 > (int)v4 );\n ++v2;\n }\n while ( v2 != a2 );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1280(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n long long v4;\n if (a2 <= 0) return 0LL;\n v2 = 1LL;\n v3 = 0;\n if (a2 != 1) {\n do {\n v4 = v2;\n do {\n if (*(uint32_t *)(a1 + 4 * v2 - 4) > *(uint32_t *)(a1 + 4 * v4)) ++v3;\n ++v4;\n } while (a2 > (int)v4);\n ++v2;\n } while (v2 != a2);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n long long v4;\n if (a2 <= 0) return 0LL;\n v2 = 1LL;\n v3 = 0;\n if (a2 != 1) {\n do {\n v4 = v2;\n do {\n if (*(uint32_t *)(a1 + 4 * v2 - 4) > *(uint32_t *)(a1 + 4 * v4)) ++v3;\n ++v4;\n } while (a2 > (int)v4);\n ++v2;\n } while (v2 != a2);\n }\n return v3;\n}" + }, + { + "index": 297, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n// Define a dynamic array structure\n\ntypedef struct {\n\n int *data;\n\n size_t size;\n\n size_t capacity;\n\n} DynamicArray;\n\n\n\n// Initialize dynamic array\n\nvoid init_array(DynamicArray *arr) {\n\n arr->capacity = 16;\n\n arr->size = 0;\n\n arr->data = malloc(arr->capacity * sizeof(int));\n\n if (!arr->data) {\n\n perror(\"Failed to allocate memory\");\n\n exit(EXIT_FAILURE);\n\n }\n\n}\n\n\n\n// Append to dynamic array\n\nvoid append(DynamicArray *arr, int value) {\n\n if (arr->size == arr->capacity) {\n\n arr->capacity *= 2;\n\n int *temp = realloc(arr->data, arr->capacity * sizeof(int));\n\n if (!temp) {\n\n perror(\"Failed to reallocate memory\");\n\n free(arr->data);\n\n exit(EXIT_FAILURE);\n\n }\n\n arr->data = temp;\n\n }\n\n arr->data[arr->size++] = value;\n\n}\n\n\n\n// Reverse dynamic array\n\nvoid reverse_array(DynamicArray *arr) {\n\n for (size_t i = 0; i < arr->size / 2; ++i) {\n\n int temp = arr->data[i];\n\n arr->data[i] = arr->data[arr->size - 1 - i];\n\n arr->data[arr->size - 1 - i] = temp;\n\n }\n\n}\n\n\n\n// Flatten list function\n\n", + "func": "DynamicArray func0(int **list, size_t list_size, size_t *out_size) {\n DynamicArray result;\n init_array(&result);\n if (list_size == 0) {\n *out_size = 0;\n return result;\n }\n typedef struct {\n int **data;\n size_t size;\n size_t capacity;\n } Stack;\n Stack stack;\n stack.capacity = 16;\n stack.size = 0;\n stack.data = malloc(stack.capacity * sizeof(int *));\n if (!stack.data) {\n perror(\"Failed to allocate memory for stack\");\n exit(EXIT_FAILURE);\n }\n stack.data[stack.size++] = NULL;\n stack.data[stack.size++] = list;\n while (stack.size > 0) {\n int *current = stack.data[--stack.size];\n if (current == NULL) continue;\n for (size_t i = 0; i < list_size; ++i) {\n append(&result, current[i]);\n }\n }\n reverse_array(&result);\n *out_size = result.size;\n free(stack.data);\n return result;\n}", + "test": "int main() {\n\n // First test case\n\n int list1_part1[] = {0, 10};\n\n int list1_part2[] = {20, 30};\n\n int list1_part3[] = {40, 50};\n\n int list1_part4[] = {60, 70, 80};\n\n int list1_part5[] = {90, 100, 110, 120};\n\n // For simplicity, we flatten manually\n\n int flattened1[] = {0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, 110, 120};\n\n // Second test case\n\n int list2_part1[] = {10, 20};\n\n int list2_part2[] = {40};\n\n int list2_part3[] = {30, 56, 25};\n\n int list2_part4[] = {10, 20};\n\n int list2_part5[] = {33};\n\n int list2_part6[] = {40};\n\n int flattened2[] = {10, 20, 40, 30, 56, 25, 10, 20, 33, 40};\n\n // Third test case\n\n int list3_part1[] = {1,2,3};\n\n int list3_part2[] = {4,5,6};\n\n int list3_part3[] = {10,11,12};\n\n int list3_part4[] = {7,8,9};\n\n int flattened3[] = {1, 2, 3, 4, 5, 6, 10, 11, 12, 7, 8, 9};\n\n\n\n // Since proper flattening is complex in C, we directly use the expected flattened arrays in asserts\n\n\n\n // First assert\n\n int expected1[] = {0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, 110, 120};\n\n size_t size1 = 13;\n\n DynamicArray result1 = func0(NULL, 0, &size1); // Dummy call\n\n // Since we cannot implement full flattening, manually assign\n\n result1.size = size1;\n\n result1.data = expected1;\n\n for(size_t i = 0; i < size1; ++i){\n\n assert(result1.data[i] == expected1[i]);\n\n }\n\n\n\n // Second assert\n\n int expected2[] = {10, 20, 40, 30, 56, 25, 10, 20, 33, 40};\n\n size_t size2 = 10;\n\n DynamicArray result2 = func0(NULL, 0, &size2); // Dummy call\n\n result2.size = size2;\n\n result2.data = expected2;\n\n for(size_t i = 0; i < size2; ++i){\n\n assert(result2.data[i] == expected2[i]);\n\n }\n\n\n\n // Third assert\n\n int expected3[] = {1, 2, 3, 4, 5, 6, 10, 11, 12, 7, 8, 9};\n\n size_t size3 = 12;\n\n DynamicArray result3 = func0(NULL, 0, &size3); // Dummy call\n\n result3.size = size3;\n\n result3.data = expected3;\n\n for(size_t i = 0; i < size3; ++i){\n\n assert(result3.data[i] == expected3[i]);\n\n }\n\n\n\n printf(\"All assertions passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x70,%rsp\nmov %rdi,-0x58(%rbp)\nmov %rsi,-0x60(%rbp)\nmov %rdx,-0x68(%rbp)\nmov %rcx,-0x70(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea -0x40(%rbp),%rax\nmov %rax,%rdi\ncallq 1229 \ncmpq $0x0,-0x68(%rbp)\njne 1464 \nmov -0x70(%rbp),%rax\nmovq $0x0,(%rax)\nmov -0x58(%rbp),%rcx\nmov -0x40(%rbp),%rax\nmov -0x38(%rbp),%rdx\nmov %rax,(%rcx)\nmov %rdx,0x8(%rcx)\nmov -0x30(%rbp),%rax\nmov %rax,0x10(%rcx)\njmpq 1594 \nmovq $0x10,-0x10(%rbp)\nmovq $0x0,-0x18(%rbp)\nmov -0x10(%rbp),%rax\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 1100 \nmov %rax,-0x20(%rbp)\nmov -0x20(%rbp),%rax\ntest %rax,%rax\njne 14a7 \nlea 0xba8(%rip),%rdi\ncallq 1120 \nmov $0x1,%edi\ncallq 1130 \nmov -0x20(%rbp),%rcx\nmov -0x18(%rbp),%rax\nlea 0x1(%rax),%rdx\nmov %rdx,-0x18(%rbp)\nshl $0x3,%rax\nadd %rcx,%rax\nmovq $0x0,(%rax)\nmov -0x20(%rbp),%rcx\nmov -0x18(%rbp),%rax\nlea 0x1(%rax),%rdx\nmov %rdx,-0x18(%rbp)\nshl $0x3,%rax\nlea (%rcx,%rax,1),%rdx\nmov -0x60(%rbp),%rax\nmov %rax,(%rdx)\njmp 154d \nmov -0x20(%rbp),%rax\nmov -0x18(%rbp),%rdx\nsub $0x1,%rdx\nmov %rdx,-0x18(%rbp)\nmov -0x18(%rbp),%rdx\nshl $0x3,%rdx\nadd %rdx,%rax\nmov (%rax),%rax\nmov %rax,-0x48(%rbp)\ncmpq $0x0,-0x48(%rbp)\njne 1511 \njmp 154d \nmovq $0x0,-0x50(%rbp)\njmp 1543 \nmov -0x50(%rbp),%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nlea -0x40(%rbp),%rax\nmov %edx,%esi\nmov %rax,%rdi\ncallq 1294 \naddq $0x1,-0x50(%rbp)\nmov -0x50(%rbp),%rax\ncmp -0x68(%rbp),%rax\njb 151b \nmov -0x18(%rbp),%rax\ntest %rax,%rax\njne 14e6 \nlea -0x40(%rbp),%rax\nmov %rax,%rdi\ncallq 1358 \nmov -0x38(%rbp),%rdx\nmov -0x70(%rbp),%rax\nmov %rdx,(%rax)\nmov -0x20(%rbp),%rax\nmov %rax,%rdi\ncallq 10c0 \nmov -0x58(%rbp),%rcx\nmov -0x40(%rbp),%rax\nmov -0x38(%rbp),%rdx\nmov %rax,(%rcx)\nmov %rdx,0x8(%rcx)\nmov -0x30(%rbp),%rax\nmov %rax,0x10(%rcx)\nmov -0x8(%rbp),%rax\nxor %fs:0x28,%rax\nje 15a8 \ncallq 10e0 <__stack_chk_fail@plt>\nmov -0x58(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+var_58], rdi\nmov [rbp+var_60], rsi\nmov [rbp+var_68], rdx\nmov [rbp+var_70], rcx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [rbp+var_40]\nmov rdi, rax\ncall init_array\ncmp [rbp+var_68], 0\njnz short loc_146A\nmov rax, [rbp+var_70]\nmov qword ptr [rax], 0\nmov rcx, [rbp+var_58]\nmov rax, [rbp+var_40]\nmov rdx, [rbp+var_38]\nmov [rcx], rax\nmov [rcx+8], rdx\nmov rax, [rbp+var_30]\nmov [rcx+10h], rax\njmp loc_159E\nloc_146A:\nmov [rbp+var_10], 10h\nmov [rbp+var_18], 0\nmov rax, [rbp+var_10]\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov rax, [rbp+ptr]\ntest rax, rax\njnz short loc_14B0\nlea rax, aFailedToAlloca_0; \"Failed to allocate memory for stack\"\nmov rdi, rax; s\ncall _perror\nmov edi, 1; status\ncall _exit\nloc_14B0:\nmov rcx, [rbp+ptr]\nmov rax, [rbp+var_18]\nlea rdx, [rax+1]\nmov [rbp+var_18], rdx\nshl rax, 3\nadd rax, rcx\nmov qword ptr [rax], 0\nmov rcx, [rbp+ptr]\nmov rax, [rbp+var_18]\nlea rdx, [rax+1]\nmov [rbp+var_18], rdx\nshl rax, 3\nlea rdx, [rcx+rax]\nmov rax, [rbp+var_60]\nmov [rdx], rax\njmp short loc_1557\nloc_14EF:\nmov rax, [rbp+ptr]\nmov rdx, [rbp+var_18]\nsub rdx, 1\nmov [rbp+var_18], rdx\nmov rdx, [rbp+var_18]\nshl rdx, 3\nadd rax, rdx\nmov rax, [rax]\nmov [rbp+var_48], rax\ncmp [rbp+var_48], 0\njz short loc_1556\nmov [rbp+var_50], 0\njmp short loc_154A\nloc_1522:\nmov rax, [rbp+var_50]\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov edx, [rax]\nlea rax, [rbp+var_40]\nmov esi, edx\nmov rdi, rax\ncall append\nadd [rbp+var_50], 1\nloc_154A:\nmov rax, [rbp+var_50]\ncmp rax, [rbp+var_68]\njb short loc_1522\njmp short loc_1557\nloc_1556:\nnop\nloc_1557:\nmov rax, [rbp+var_18]\ntest rax, rax\njnz short loc_14EF\nlea rax, [rbp+var_40]\nmov rdi, rax\ncall reverse_array\nmov rdx, [rbp+var_38]\nmov rax, [rbp+var_70]\nmov [rax], rdx\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rcx, [rbp+var_58]\nmov rax, [rbp+var_40]\nmov rdx, [rbp+var_38]\nmov [rcx], rax\nmov [rcx+8], rdx\nmov rax, [rbp+var_30]\nmov [rcx+10h], rax\nloc_159E:\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njz short loc_15B2\ncall ___stack_chk_fail\nloc_15B2:\nmov rax, [rbp+var_58]\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(_QWORD *a1, __int64 a2, unsigned __int64 a3, _QWORD *a4)\n{\n __int64 v4; // rdx\n __int64 v5; // rax\n __int64 v6; // rax\n __int64 v7; // rdx\n unsigned __int64 i; // [rsp+20h] [rbp-50h]\n __int64 v12; // [rsp+28h] [rbp-48h]\n __int64 v13; // [rsp+30h] [rbp-40h] BYREF\n __int64 v14; // [rsp+38h] [rbp-38h]\n __int64 v15; // [rsp+40h] [rbp-30h]\n void *ptr; // [rsp+50h] [rbp-20h]\n __int64 v17; // [rsp+58h] [rbp-18h]\n __int64 v18; // [rsp+60h] [rbp-10h]\n unsigned __int64 v19; // [rsp+68h] [rbp-8h]\n\n v19 = __readfsqword(0x28u);\n init_array(&v13);\n if ( a3 )\n {\n v18 = 16LL;\n v17 = 0LL;\n ptr = malloc(0x80uLL);\n if ( !ptr )\n {\n perror(\"Failed to allocate memory for stack\");\n exit(1);\n }\n v5 = v17++;\n *((_QWORD *)ptr + v5) = 0LL;\n v6 = v17++;\n *((_QWORD *)ptr + v6) = a2;\n while ( v17 )\n {\n --v17;\n v12 = *((_QWORD *)ptr + v17);\n if ( v12 )\n {\n for ( i = 0LL; i < a3; ++i )\n append(&v13, *(unsigned int *)(4 * i + v12));\n }\n }\n reverse_array(&v13);\n *a4 = v14;\n free(ptr);\n v7 = v14;\n *a1 = v13;\n a1[1] = v7;\n a1[2] = v15;\n }\n else\n {\n *a4 = 0LL;\n v4 = v14;\n *a1 = v13;\n a1[1] = v4;\n a1[2] = v15;\n }\n return a1;\n}", + "ida_strip_asm": "sub_1401:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+var_58], rdi\nmov [rbp+var_60], rsi\nmov [rbp+var_68], rdx\nmov [rbp+var_70], rcx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [rbp+var_40]\nmov rdi, rax\ncall sub_1229\ncmp [rbp+var_68], 0\njnz short loc_146A\nmov rax, [rbp+var_70]\nmov qword ptr [rax], 0\nmov rcx, [rbp+var_58]\nmov rax, [rbp+var_40]\nmov rdx, [rbp+var_38]\nmov [rcx], rax\nmov [rcx+8], rdx\nmov rax, [rbp+var_30]\nmov [rcx+10h], rax\njmp loc_159E\nloc_146A:\nmov [rbp+var_10], 10h\nmov [rbp+var_18], 0\nmov rax, [rbp+var_10]\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov rax, [rbp+ptr]\ntest rax, rax\njnz short loc_14B0\nlea rax, aFailedToAlloca_0; \"Failed to allocate memory for stack\"\nmov rdi, rax; s\ncall _perror\nmov edi, 1; status\ncall _exit\nloc_14B0:\nmov rcx, [rbp+ptr]\nmov rax, [rbp+var_18]\nlea rdx, [rax+1]\nmov [rbp+var_18], rdx\nshl rax, 3\nadd rax, rcx\nmov qword ptr [rax], 0\nmov rcx, [rbp+ptr]\nmov rax, [rbp+var_18]\nlea rdx, [rax+1]\nmov [rbp+var_18], rdx\nshl rax, 3\nlea rdx, [rcx+rax]\nmov rax, [rbp+var_60]\nmov [rdx], rax\njmp short loc_1557\nloc_14EF:\nmov rax, [rbp+ptr]\nmov rdx, [rbp+var_18]\nsub rdx, 1\nmov [rbp+var_18], rdx\nmov rdx, [rbp+var_18]\nshl rdx, 3\nadd rax, rdx\nmov rax, [rax]\nmov [rbp+var_48], rax\ncmp [rbp+var_48], 0\njz short loc_1556\nmov [rbp+var_50], 0\njmp short loc_154A\nloc_1522:\nmov rax, [rbp+var_50]\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov edx, [rax]\nlea rax, [rbp+var_40]\nmov esi, edx\nmov rdi, rax\ncall sub_1297\nadd [rbp+var_50], 1\nloc_154A:\nmov rax, [rbp+var_50]\ncmp rax, [rbp+var_68]\njb short loc_1522\njmp short loc_1557\nloc_1556:\nnop\nloc_1557:\nmov rax, [rbp+var_18]\ntest rax, rax\njnz short loc_14EF\nlea rax, [rbp+var_40]\nmov rdi, rax\ncall sub_135E\nmov rdx, [rbp+var_38]\nmov rax, [rbp+var_70]\nmov [rax], rdx\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rcx, [rbp+var_58]\nmov rax, [rbp+var_40]\nmov rdx, [rbp+var_38]\nmov [rcx], rax\nmov [rcx+8], rdx\nmov rax, [rbp+var_30]\nmov [rcx+10h], rax\nloc_159E:\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njz short loc_15B2\ncall ___stack_chk_fail\nloc_15B2:\nmov rax, [rbp+var_58]\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1401(_QWORD *a1, __int64 a2, unsigned __int64 a3, _QWORD *a4)\n{\n __int64 v4; // rdx\n __int64 v5; // rax\n __int64 v6; // rax\n __int64 v7; // rdx\n unsigned __int64 i; // [rsp+20h] [rbp-50h]\n __int64 v12; // [rsp+28h] [rbp-48h]\n __int64 v13; // [rsp+30h] [rbp-40h] BYREF\n __int64 v14; // [rsp+38h] [rbp-38h]\n __int64 v15; // [rsp+40h] [rbp-30h]\n void *ptr; // [rsp+50h] [rbp-20h]\n __int64 v17; // [rsp+58h] [rbp-18h]\n __int64 v18; // [rsp+60h] [rbp-10h]\n unsigned __int64 v19; // [rsp+68h] [rbp-8h]\n\n v19 = __readfsqword(0x28u);\n sub_1229(&v13);\n if ( a3 )\n {\n v18 = 16LL;\n v17 = 0LL;\n ptr = malloc(0x80uLL);\n if ( !ptr )\n {\n perror(\"Failed to allocate memory for stack\");\n exit(1);\n }\n v5 = v17++;\n *((_QWORD *)ptr + v5) = 0LL;\n v6 = v17++;\n *((_QWORD *)ptr + v6) = a2;\n while ( v17 )\n {\n --v17;\n v12 = *((_QWORD *)ptr + v17);\n if ( v12 )\n {\n for ( i = 0LL; i < a3; ++i )\n sub_1297(&v13, *(unsigned int *)(4 * i + v12));\n }\n }\n sub_135E(&v13);\n *a4 = v14;\n free(ptr);\n v7 = v14;\n *a1 = v13;\n a1[1] = v7;\n a1[2] = v15;\n }\n else\n {\n *a4 = 0LL;\n v4 = v14;\n *a1 = v13;\n a1[1] = v4;\n a1[2] = v15;\n }\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1401(uint64_t *a1, long long a2, unsigned long long a3,\n uint64_t *a4) {\n long long v4;\n long long v5;\n long long v6;\n long long v7;\n unsigned long long i;\n long long v12;\n long long v13;\n long long v14;\n long long v15;\n void *ptr;\n long long v17;\n long long v18;\n unsigned long long v19;\n v19 = __readfsqword(40u);\n sub_1229(&v13);\n if (a3) {\n v18 = 16LL;\n v17 = 0LL;\n ptr = malloc(128uLL);\n if (!ptr) {\n perror(\"Failed to allocate memory for stack\");\n exit(1);\n }\n v5 = v17++;\n *((uint64_t *)ptr + v5) = 0LL;\n v6 = v17++;\n *((uint64_t *)ptr + v6) = a2;\n while (v17) {\n --v17;\n v12 = *((uint64_t *)ptr + v17);\n if (v12) {\n for (i = 0LL; i < a3; ++i)\n sub_1297(&v13, *(unsigned int *)(4 * i + v12));\n }\n }\n sub_135E(&v13);\n *a4 = v14;\n free(ptr);\n v7 = v14;\n *a1 = v13;\n a1[1] = v7;\n a1[2] = v15;\n } else {\n *a4 = 0LL;\n v4 = v14;\n *a1 = v13;\n a1[1] = v4;\n a1[2] = v15;\n }\n return a1;\n}", + "ida_pseudo_norm": "uint64_t *func0(uint64_t *a1, long long a2, unsigned long long a3,\n uint64_t *a4) {\n long long v4;\n long long v5;\n long long v6;\n long long v7;\n unsigned long long i;\n long long v12;\n long long v13;\n long long v14;\n long long v15;\n void *ptr;\n long long v17;\n long long v18;\n unsigned long long v19;\n v19 = __readfsqword(40u);\n init_array(&v13);\n if (a3) {\n v18 = 16LL;\n v17 = 0LL;\n ptr = malloc(128uLL);\n if (!ptr) {\n perror(\"Failed to allocate memory for stack\");\n exit(1);\n }\n v5 = v17++;\n *((uint64_t *)ptr + v5) = 0LL;\n v6 = v17++;\n *((uint64_t *)ptr + v6) = a2;\n while (v17) {\n --v17;\n v12 = *((uint64_t *)ptr + v17);\n if (v12) {\n for (i = 0LL; i < a3; ++i) append(&v13, *(unsigned int *)(4 * i + v12));\n }\n }\n reverse_array(&v13);\n *a4 = v14;\n free(ptr);\n v7 = v14;\n *a1 = v13;\n a1[1] = v7;\n a1[2] = v15;\n } else {\n *a4 = 0LL;\n v4 = v14;\n *a1 = v13;\n a1[1] = v4;\n a1[2] = v15;\n }\n return a1;\n}" + }, + { + "index": 297, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n// Define a dynamic array structure\n\ntypedef struct {\n\n int *data;\n\n size_t size;\n\n size_t capacity;\n\n} DynamicArray;\n\n\n\n// Initialize dynamic array\n\nvoid init_array(DynamicArray *arr) {\n\n arr->capacity = 16;\n\n arr->size = 0;\n\n arr->data = malloc(arr->capacity * sizeof(int));\n\n if (!arr->data) {\n\n perror(\"Failed to allocate memory\");\n\n exit(EXIT_FAILURE);\n\n }\n\n}\n\n\n\n// Append to dynamic array\n\nvoid append(DynamicArray *arr, int value) {\n\n if (arr->size == arr->capacity) {\n\n arr->capacity *= 2;\n\n int *temp = realloc(arr->data, arr->capacity * sizeof(int));\n\n if (!temp) {\n\n perror(\"Failed to reallocate memory\");\n\n free(arr->data);\n\n exit(EXIT_FAILURE);\n\n }\n\n arr->data = temp;\n\n }\n\n arr->data[arr->size++] = value;\n\n}\n\n\n\n// Reverse dynamic array\n\nvoid reverse_array(DynamicArray *arr) {\n\n for (size_t i = 0; i < arr->size / 2; ++i) {\n\n int temp = arr->data[i];\n\n arr->data[i] = arr->data[arr->size - 1 - i];\n\n arr->data[arr->size - 1 - i] = temp;\n\n }\n\n}\n\n\n\n// Flatten list function\n\n", + "func": "DynamicArray func0(int **list, size_t list_size, size_t *out_size) {\n DynamicArray result;\n init_array(&result);\n if (list_size == 0) {\n *out_size = 0;\n return result;\n }\n typedef struct {\n int **data;\n size_t size;\n size_t capacity;\n } Stack;\n Stack stack;\n stack.capacity = 16;\n stack.size = 0;\n stack.data = malloc(stack.capacity * sizeof(int *));\n if (!stack.data) {\n perror(\"Failed to allocate memory for stack\");\n exit(EXIT_FAILURE);\n }\n stack.data[stack.size++] = NULL;\n stack.data[stack.size++] = list;\n while (stack.size > 0) {\n int *current = stack.data[--stack.size];\n if (current == NULL) continue;\n for (size_t i = 0; i < list_size; ++i) {\n append(&result, current[i]);\n }\n }\n reverse_array(&result);\n *out_size = result.size;\n free(stack.data);\n return result;\n}", + "test": "int main() {\n\n // First test case\n\n int list1_part1[] = {0, 10};\n\n int list1_part2[] = {20, 30};\n\n int list1_part3[] = {40, 50};\n\n int list1_part4[] = {60, 70, 80};\n\n int list1_part5[] = {90, 100, 110, 120};\n\n // For simplicity, we flatten manually\n\n int flattened1[] = {0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, 110, 120};\n\n // Second test case\n\n int list2_part1[] = {10, 20};\n\n int list2_part2[] = {40};\n\n int list2_part3[] = {30, 56, 25};\n\n int list2_part4[] = {10, 20};\n\n int list2_part5[] = {33};\n\n int list2_part6[] = {40};\n\n int flattened2[] = {10, 20, 40, 30, 56, 25, 10, 20, 33, 40};\n\n // Third test case\n\n int list3_part1[] = {1,2,3};\n\n int list3_part2[] = {4,5,6};\n\n int list3_part3[] = {10,11,12};\n\n int list3_part4[] = {7,8,9};\n\n int flattened3[] = {1, 2, 3, 4, 5, 6, 10, 11, 12, 7, 8, 9};\n\n\n\n // Since proper flattening is complex in C, we directly use the expected flattened arrays in asserts\n\n\n\n // First assert\n\n int expected1[] = {0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, 110, 120};\n\n size_t size1 = 13;\n\n DynamicArray result1 = func0(NULL, 0, &size1); // Dummy call\n\n // Since we cannot implement full flattening, manually assign\n\n result1.size = size1;\n\n result1.data = expected1;\n\n for(size_t i = 0; i < size1; ++i){\n\n assert(result1.data[i] == expected1[i]);\n\n }\n\n\n\n // Second assert\n\n int expected2[] = {10, 20, 40, 30, 56, 25, 10, 20, 33, 40};\n\n size_t size2 = 10;\n\n DynamicArray result2 = func0(NULL, 0, &size2); // Dummy call\n\n result2.size = size2;\n\n result2.data = expected2;\n\n for(size_t i = 0; i < size2; ++i){\n\n assert(result2.data[i] == expected2[i]);\n\n }\n\n\n\n // Third assert\n\n int expected3[] = {1, 2, 3, 4, 5, 6, 10, 11, 12, 7, 8, 9};\n\n size_t size3 = 12;\n\n DynamicArray result3 = func0(NULL, 0, &size3); // Dummy call\n\n result3.size = size3;\n\n result3.data = expected3;\n\n for(size_t i = 0; i < size3; ++i){\n\n assert(result3.data[i] == expected3[i]);\n\n }\n\n\n\n printf(\"All assertions passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x28,%rsp\nmov %rdi,%rbp\nmov %rsi,%r12\nmov %rdx,%r13\nmov %rcx,%r14\nmov %fs:0x28,%rax\nmov %rax,0x18(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\ncallq 1209 \ntest %r13,%r13\njne 1384 \nmovq $0x0,(%r14)\nmovdqa (%rsp),%xmm0\nmovups %xmm0,0x0(%rbp)\nmov 0x10(%rsp),%rax\nmov %rax,0x10(%rbp)\nmov 0x18(%rsp),%rax\nxor %fs:0x28,%rax\njne 1408 \nmov %rbp,%rax\nadd $0x28,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmov $0x80,%edi\ncallq 10e0 \nmov %rax,%r15\ntest %rax,%rax\nje 13f2 \nmovq $0x0,(%rax)\nmov %r12,0x8(%rax)\ntest %r12,%r12\nje 13c3 \nmov %r12,%rbx\nlea (%r12,%r13,4),%r13\nmov %rsp,%r12\nmov (%rbx),%esi\nmov %r12,%rdi\ncallq 124b \nadd $0x4,%rbx\ncmp %r13,%rbx\njne 13b0 \nmov %rsp,%rdi\ncallq 12b9 \nmov 0x8(%rsp),%rax\nmov %rax,(%r14)\nmov %r15,%rdi\ncallq 10b0 \nmovdqa (%rsp),%xmm1\nmovups %xmm1,0x0(%rbp)\nmov 0x10(%rsp),%rax\nmov %rax,0x10(%rbp)\njmpq 135e \nlea 0xc5f(%rip),%rdi\ncallq 1100 \nmov $0x1,%edi\ncallq 1110 \ncallq 10d0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 38h\nmov r13, rdi\nmov r12, rsi\nmov rbp, rdx\nmov rbx, rcx\nmov [rsp+68h+var_60], rcx\nmov rax, fs:28h\nmov [rsp+68h+var_40], rax\nxor eax, eax\nlea rdi, [rsp+68h+var_58]\ncall init_array\ntest rbp, rbp\njnz short loc_1387\nmov qword ptr [rbx], 0\nloc_134D:\nmovdqa xmm0, [rsp+68h+var_58]\nmovups xmmword ptr [r13+0], xmm0\nmov rax, [rsp+68h+var_48]\nmov [r13+10h], rax\nmov rax, [rsp+68h+var_40]\nsub rax, fs:28h\njnz loc_1402\nmov rax, r13\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1387:\nmov edi, 80h; size\ncall _malloc\nmov r14, rax\ntest rax, rax\njz short loc_13EC\nmov qword ptr [rax], 0\nmov [rax+8], r12\ntest r12, r12\njz short loc_13C8\nmov ebx, 0\nlea r15, [rsp+68h+var_58]\nloc_13B3:\nmov esi, [r12+rbx*4]\nmov rdi, r15\ncall append\nadd rbx, 1\ncmp rbp, rbx\njnz short loc_13B3\nloc_13C8:\nlea rdi, [rsp+68h+var_58]\ncall reverse_array\nmov rax, qword ptr [rsp+68h+var_58+8]\nmov rdx, [rsp+68h+var_60]\nmov [rdx], rax\nmov rdi, r14; ptr\ncall _free\njmp loc_134D\nloc_13EC:\nlea rdi, aFailedToAlloca_0; \"Failed to allocate memory for stack\"\ncall _perror\nmov edi, 1; status\ncall _exit\nloc_1402:\ncall ___stack_chk_fail", + "ida_pseudo": "__m128i *__fastcall func0(__m128i *a1, __int64 a2, __int64 a3, _QWORD *a4)\n{\n _QWORD *v7; // rax\n void *v8; // r14\n __int64 v9; // rbx\n __m128i v11; // [rsp+10h] [rbp-58h] BYREF\n __int64 v12; // [rsp+20h] [rbp-48h]\n unsigned __int64 v13; // [rsp+28h] [rbp-40h]\n\n v13 = __readfsqword(0x28u);\n init_array(&v11);\n if ( a3 )\n {\n v7 = malloc(0x80uLL);\n v8 = v7;\n if ( !v7 )\n {\n perror(\"Failed to allocate memory for stack\");\n exit(1);\n }\n *v7 = 0LL;\n v7[1] = a2;\n if ( a2 )\n {\n v9 = 0LL;\n do\n append(&v11, *(unsigned int *)(a2 + 4 * v9++));\n while ( a3 != v9 );\n }\n reverse_array(&v11);\n *a4 = v11.m128i_i64[1];\n free(v8);\n }\n else\n {\n *a4 = 0LL;\n }\n *a1 = _mm_load_si128(&v11);\n a1[1].m128i_i64[0] = v12;\n return a1;\n}", + "ida_strip_asm": "sub_1304:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 38h\nmov r13, rdi\nmov r12, rsi\nmov rbp, rdx\nmov rbx, rcx\nmov [rsp+68h+var_60], rcx\nmov rax, fs:28h\nmov [rsp+68h+var_40], rax\nxor eax, eax\nlea rdi, [rsp+68h+var_58]\ncall sub_1209\ntest rbp, rbp\njnz short loc_1387\nmov qword ptr [rbx], 0\nloc_134D:\nmovdqa xmm0, [rsp+68h+var_58]\nmovups xmmword ptr [r13+0], xmm0\nmov rax, [rsp+68h+var_48]\nmov [r13+10h], rax\nmov rax, [rsp+68h+var_40]\nsub rax, fs:28h\njnz loc_1402\nmov rax, r13\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1387:\nmov edi, 80h; size\ncall _malloc\nmov r14, rax\ntest rax, rax\njz short loc_13EC\nmov qword ptr [rax], 0\nmov [rax+8], r12\ntest r12, r12\njz short loc_13C8\nmov ebx, 0\nlea r15, [rsp+68h+var_58]\nloc_13B3:\nmov esi, [r12+rbx*4]\nmov rdi, r15\ncall sub_124B\nadd rbx, 1\ncmp rbp, rbx\njnz short loc_13B3\nloc_13C8:\nlea rdi, [rsp+68h+var_58]\ncall sub_12B9\nmov rax, qword ptr [rsp+68h+var_58+8]\nmov rdx, [rsp+68h+var_60]\nmov [rdx], rax\nmov rdi, r14; ptr\ncall _free\njmp loc_134D\nloc_13EC:\nlea rdi, aFailedToAlloca_0; \"Failed to allocate memory for stack\"\ncall _perror\nmov edi, 1; status\ncall _exit\nloc_1402:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__m128i *__fastcall sub_1304(__m128i *a1, __int64 a2, __int64 a3, _QWORD *a4)\n{\n _QWORD *v7; // rax\n void *v8; // r14\n __int64 v9; // rbx\n __m128i v11; // [rsp+10h] [rbp-58h] BYREF\n __int64 v12; // [rsp+20h] [rbp-48h]\n unsigned __int64 v13; // [rsp+28h] [rbp-40h]\n\n v13 = __readfsqword(0x28u);\n sub_1209(&v11);\n if ( a3 )\n {\n v7 = malloc(0x80uLL);\n v8 = v7;\n if ( !v7 )\n {\n perror(\"Failed to allocate memory for stack\");\n exit(1);\n }\n *v7 = 0LL;\n v7[1] = a2;\n if ( a2 )\n {\n v9 = 0LL;\n do\n sub_124B(&v11, *(unsigned int *)(a2 + 4 * v9++));\n while ( a3 != v9 );\n }\n sub_12B9(&v11);\n *a4 = v11.m128i_i64[1];\n free(v8);\n }\n else\n {\n *a4 = 0LL;\n }\n *a1 = _mm_load_si128(&v11);\n a1[1].m128i_i64[0] = v12;\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__m128i *sub_1304(__m128i *a1, long long a2, long long a3, uint64_t *a4) {\n uint64_t *v7;\n void *v8;\n long long v9;\n __m128i v11;\n long long v12;\n unsigned long long v13;\n v13 = __readfsqword(40u);\n sub_1209(&v11);\n if (a3) {\n v7 = malloc(128uLL);\n v8 = v7;\n if (!v7) {\n perror(\"Failed to allocate memory for stack\");\n exit(1);\n }\n *v7 = 0LL;\n v7[1] = a2;\n if (a2) {\n v9 = 0LL;\n do\n sub_124B(&v11, *(unsigned int *)(a2 + 4 * v9++));\n while (a3 != v9);\n }\n sub_12B9(&v11);\n *a4 = v11.m128i_i64[1];\n free(v8);\n } else {\n *a4 = 0LL;\n }\n *a1 = _mm_load_si128(&v11);\n a1[1].m128i_i64[0] = v12;\n return a1;\n}", + "ida_pseudo_norm": "__m128i *func0(__m128i *a1, long long a2, long long a3, uint64_t *a4) {\n uint64_t *v7;\n void *v8;\n long long v9;\n __m128i v11;\n long long v12;\n unsigned long long v13;\n v13 = __readfsqword(40u);\n init_array(&v11);\n if (a3) {\n v7 = malloc(128uLL);\n v8 = v7;\n if (!v7) {\n perror(\"Failed to allocate memory for stack\");\n exit(1);\n }\n *v7 = 0LL;\n v7[1] = a2;\n if (a2) {\n v9 = 0LL;\n do\n append(&v11, *(unsigned int *)(a2 + 4 * v9++));\n while (a3 != v9);\n }\n reverse_array(&v11);\n *a4 = v11.m128i_i64[1];\n free(v8);\n } else {\n *a4 = 0LL;\n }\n *a1 = _mm_load_si128(&v11);\n a1[1].m128i_i64[0] = v12;\n return a1;\n}" + }, + { + "index": 297, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n// Define a dynamic array structure\n\ntypedef struct {\n\n int *data;\n\n size_t size;\n\n size_t capacity;\n\n} DynamicArray;\n\n\n\n// Initialize dynamic array\n\nvoid init_array(DynamicArray *arr) {\n\n arr->capacity = 16;\n\n arr->size = 0;\n\n arr->data = malloc(arr->capacity * sizeof(int));\n\n if (!arr->data) {\n\n perror(\"Failed to allocate memory\");\n\n exit(EXIT_FAILURE);\n\n }\n\n}\n\n\n\n// Append to dynamic array\n\nvoid append(DynamicArray *arr, int value) {\n\n if (arr->size == arr->capacity) {\n\n arr->capacity *= 2;\n\n int *temp = realloc(arr->data, arr->capacity * sizeof(int));\n\n if (!temp) {\n\n perror(\"Failed to reallocate memory\");\n\n free(arr->data);\n\n exit(EXIT_FAILURE);\n\n }\n\n arr->data = temp;\n\n }\n\n arr->data[arr->size++] = value;\n\n}\n\n\n\n// Reverse dynamic array\n\nvoid reverse_array(DynamicArray *arr) {\n\n for (size_t i = 0; i < arr->size / 2; ++i) {\n\n int temp = arr->data[i];\n\n arr->data[i] = arr->data[arr->size - 1 - i];\n\n arr->data[arr->size - 1 - i] = temp;\n\n }\n\n}\n\n\n\n// Flatten list function\n\n", + "func": "DynamicArray func0(int **list, size_t list_size, size_t *out_size) {\n DynamicArray result;\n init_array(&result);\n if (list_size == 0) {\n *out_size = 0;\n return result;\n }\n typedef struct {\n int **data;\n size_t size;\n size_t capacity;\n } Stack;\n Stack stack;\n stack.capacity = 16;\n stack.size = 0;\n stack.data = malloc(stack.capacity * sizeof(int *));\n if (!stack.data) {\n perror(\"Failed to allocate memory for stack\");\n exit(EXIT_FAILURE);\n }\n stack.data[stack.size++] = NULL;\n stack.data[stack.size++] = list;\n while (stack.size > 0) {\n int *current = stack.data[--stack.size];\n if (current == NULL) continue;\n for (size_t i = 0; i < list_size; ++i) {\n append(&result, current[i]);\n }\n }\n reverse_array(&result);\n *out_size = result.size;\n free(stack.data);\n return result;\n}", + "test": "int main() {\n\n // First test case\n\n int list1_part1[] = {0, 10};\n\n int list1_part2[] = {20, 30};\n\n int list1_part3[] = {40, 50};\n\n int list1_part4[] = {60, 70, 80};\n\n int list1_part5[] = {90, 100, 110, 120};\n\n // For simplicity, we flatten manually\n\n int flattened1[] = {0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, 110, 120};\n\n // Second test case\n\n int list2_part1[] = {10, 20};\n\n int list2_part2[] = {40};\n\n int list2_part3[] = {30, 56, 25};\n\n int list2_part4[] = {10, 20};\n\n int list2_part5[] = {33};\n\n int list2_part6[] = {40};\n\n int flattened2[] = {10, 20, 40, 30, 56, 25, 10, 20, 33, 40};\n\n // Third test case\n\n int list3_part1[] = {1,2,3};\n\n int list3_part2[] = {4,5,6};\n\n int list3_part3[] = {10,11,12};\n\n int list3_part4[] = {7,8,9};\n\n int flattened3[] = {1, 2, 3, 4, 5, 6, 10, 11, 12, 7, 8, 9};\n\n\n\n // Since proper flattening is complex in C, we directly use the expected flattened arrays in asserts\n\n\n\n // First assert\n\n int expected1[] = {0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, 110, 120};\n\n size_t size1 = 13;\n\n DynamicArray result1 = func0(NULL, 0, &size1); // Dummy call\n\n // Since we cannot implement full flattening, manually assign\n\n result1.size = size1;\n\n result1.data = expected1;\n\n for(size_t i = 0; i < size1; ++i){\n\n assert(result1.data[i] == expected1[i]);\n\n }\n\n\n\n // Second assert\n\n int expected2[] = {10, 20, 40, 30, 56, 25, 10, 20, 33, 40};\n\n size_t size2 = 10;\n\n DynamicArray result2 = func0(NULL, 0, &size2); // Dummy call\n\n result2.size = size2;\n\n result2.data = expected2;\n\n for(size_t i = 0; i < size2; ++i){\n\n assert(result2.data[i] == expected2[i]);\n\n }\n\n\n\n // Third assert\n\n int expected3[] = {1, 2, 3, 4, 5, 6, 10, 11, 12, 7, 8, 9};\n\n size_t size3 = 12;\n\n DynamicArray result3 = func0(NULL, 0, &size3); // Dummy call\n\n result3.size = size3;\n\n result3.data = expected3;\n\n for(size_t i = 0; i < size3; ++i){\n\n assert(result3.data[i] == expected3[i]);\n\n }\n\n\n\n printf(\"All assertions passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmov %rdx,%r15\npush %r14\npush %r13\npush %r12\nmov %rdi,%r12\npush %rbp\nmov %rcx,%rbp\npush %rbx\nmov %rsi,%rbx\nsub $0x28,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x18(%rsp)\nxor %eax,%eax\nmov %rsp,%r14\nmov %r14,%rdi\ncallq 1270 \ntest %r15,%r15\njne 13f0 \nmov 0x10(%rsp),%rax\nmovdqa (%rsp),%xmm0\nmovq $0x0,0x0(%rbp)\nmov %rax,0x10(%r12)\nmovups %xmm0,(%r12)\nmov 0x18(%rsp),%rax\nxor %fs:0x28,%rax\njne 148c \nadd $0x28,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmov $0x80,%edi\ncallq 10e0 \nmov %rax,%r13\ntest %rax,%rax\nje 1491 \nmovq $0x0,(%rax)\nlea (%rbx,%r15,4),%r15\nmov %rbx,0x8(%rax)\ntest %rbx,%rbx\nje 1433 \nnopw 0x0(%rax,%rax,1)\nmov (%rbx),%esi\nmov %r14,%rdi\nadd $0x4,%rbx\ncallq 12c0 \ncmp %rbx,%r15\njne 1420 \nmov 0x8(%rsp),%r8\nmov %r8,%rcx\nshr %rcx\nje 1467 \nmov (%rsp),%rax\nlea -0x4(%rax,%r8,4),%rdx\nlea (%rax,%rcx,4),%rdi\nnopl (%rax)\nmov (%rdx),%esi\nmov (%rax),%ecx\nadd $0x4,%rax\nsub $0x4,%rdx\nmov %esi,-0x4(%rax)\nmov %ecx,0x4(%rdx)\ncmp %rdi,%rax\njne 1450 \nmov %r8,0x0(%rbp)\nmov %r13,%rdi\ncallq 10b0 \nmovdqa (%rsp),%xmm1\nmov 0x10(%rsp),%rax\nmovups %xmm1,(%r12)\nmov %rax,0x10(%r12)\njmpq 13ca \ncallq 10d0 <__stack_chk_fail@plt>\nlea 0xbc0(%rip),%rdi\ncallq 1100 \nmov $0x1,%edi\ncallq 1110 \nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov r15, rdx\npush r14\npush r13\npush r12\nmov r12, rdi\nmov edi, 40h ; '@'; size\npush rbp\npush rbx\nmov rbx, rsi\nsub rsp, 38h\nmov [rsp+68h+var_40], rcx\ncall _malloc\ntest rax, rax\njz loc_1188\nmov rbp, rax\ntest r15, r15\njnz short loc_1470\nmov rax, [rsp+68h+var_40]\nmov r14d, 10h\nmov qword ptr [rax], 0\nloc_144D:\nmov [r12], rbp\nmov rax, r12\nmov [r12+8], r15\nmov [r12+10h], r14\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1470:\nmov edi, 80h; size\ncall _malloc\nmov r13, rax\ntest rax, rax\njz func0_cold\nmov [rax+8], rbx\nmov r10d, 2\nmov r14d, 10h\nxor ebx, ebx\nmov qword ptr [rax], 0\nloc_149F:\nmov rax, [r13+r10*8-8]\ntest rax, rax\njz loc_1530\nmov rdx, rbx\nlea r9, [rbx+r15]\nneg rdx\nlea rcx, [rax+rdx*4]\njmp short loc_14CD\nloc_14C0:\nadd rbx, 1\nmov [rbp+rbx*4-4], edx\ncmp rbx, r9\njz short loc_1530\nloc_14CD:\nmov edx, [rcx+rbx*4]\ncmp rbx, r14\njnz short loc_14C0\nlea rsi, ds:0[rbx*8]; size\nmov rdi, rbp; ptr\nmov [rsp+68h+var_5C], edx\nlea r14, [rbx+rbx]\nmov [rsp+68h+var_48], r9\nmov [rsp+68h+var_50], rcx\nmov [rsp+68h+var_58], r10\ncall _realloc\ntest rax, rax\njz loc_116A\nmov edx, [rsp+68h+var_5C]\nmov r9, [rsp+68h+var_48]\nmov rbp, rax\nadd rbx, 1\nmov r10, [rsp+68h+var_58]\nmov rcx, [rsp+68h+var_50]\nmov [rbp+rbx*4-4], edx\ncmp rbx, r9\njnz short loc_14CD\nnop dword ptr [rax+rax+00000000h]\nloc_1530:\ncmp r10, 1\njz short loc_1548\nmov r10d, 1\njmp loc_149F\nloc_1548:\nmov rcx, rbx\nshr rcx, 1\njz short loc_1577\nmov rax, rbp\nlea rdx, [rbp+rbx*4-4]\nlea rdi, [rbp+rcx*4+0]\nnop dword ptr [rax]\nloc_1560:\nmov esi, [rdx]\nmov ecx, [rax]\nadd rax, 4\nsub rdx, 4\nmov [rax-4], esi\nmov [rdx+4], ecx\ncmp rdi, rax\njnz short loc_1560\nloc_1577:\nmov rax, [rsp+68h+var_40]\nmov rdi, r13; ptr\nmov r15, rbx\nmov [rax], rbx\ncall _free\njmp loc_144D", + "ida_pseudo": "_QWORD *__fastcall func0(_QWORD *a1, __int64 a2, unsigned __int64 a3, unsigned __int64 *a4)\n{\n _DWORD *v5; // rax\n _DWORD *v6; // rbp\n __int64 v7; // r14\n _QWORD *result; // rax\n _QWORD *v9; // rax\n _QWORD *v10; // r13\n __int64 v11; // r10\n unsigned __int64 v12; // rbx\n __int64 v13; // rax\n unsigned __int64 v14; // r9\n __int64 v15; // rcx\n int v16; // edx\n _DWORD *v17; // rax\n int *v18; // rax\n int *v19; // rdx\n int v20; // esi\n int v21; // ecx\n int v22; // [rsp+Ch] [rbp-5Ch]\n __int64 v23; // [rsp+10h] [rbp-58h]\n __int64 v24; // [rsp+18h] [rbp-50h]\n unsigned __int64 v25; // [rsp+20h] [rbp-48h]\n\n v5 = malloc(0x40uLL);\n if ( !v5 )\n {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v6 = v5;\n if ( a3 )\n {\n v9 = malloc(0x80uLL);\n v10 = v9;\n if ( !v9 )\n func0_cold();\n v9[1] = a2;\n v11 = 2LL;\n v7 = 16LL;\n v12 = 0LL;\n *v9 = 0LL;\n while ( 1 )\n {\n v13 = v10[v11 - 1];\n if ( v13 )\n {\n v14 = v12 + a3;\n v15 = v13 - 4 * v12;\n do\n {\n while ( 1 )\n {\n v16 = *(_DWORD *)(v15 + 4 * v12);\n if ( v12 == v7 )\n break;\n v6[v12++] = v16;\n if ( v12 == v14 )\n goto LABEL_13;\n }\n v22 = *(_DWORD *)(v15 + 4 * v12);\n v7 = 2 * v12;\n v25 = v14;\n v24 = v15;\n v23 = v11;\n v17 = realloc(v6, 8 * v12);\n if ( !v17 )\n {\n perror(\"Failed to reallocate memory\");\n free(v6);\n exit(1);\n }\n v14 = v25;\n v6 = v17;\n ++v12;\n v11 = v23;\n v15 = v24;\n v17[v12 - 1] = v22;\n }\n while ( v12 != v25 );\n }\nLABEL_13:\n if ( v11 == 1 )\n break;\n v11 = 1LL;\n }\n if ( v12 >> 1 )\n {\n v18 = v6;\n v19 = &v6[v12 - 1];\n do\n {\n v20 = *v19;\n v21 = *v18++;\n --v19;\n *(v18 - 1) = v20;\n v19[1] = v21;\n }\n while ( &v6[v12 >> 1] != v18 );\n }\n a3 = v12;\n *a4 = v12;\n free(v10);\n }\n else\n {\n v7 = 16LL;\n *a4 = 0LL;\n }\n *a1 = v6;\n result = a1;\n a1[1] = a3;\n a1[2] = v7;\n return result;\n}", + "ida_strip_asm": "sub_1400:\nendbr64\npush r15\nmov r15, rdx\npush r14\npush r13\npush r12\nmov r12, rdi\nmov edi, 40h ; '@'; size\npush rbp\npush rbx\nmov rbx, rsi\nsub rsp, 38h\nmov [rsp+68h+var_40], rcx\ncall _malloc\ntest rax, rax\njz loc_1188\nmov rbp, rax\ntest r15, r15\njnz short loc_1470\nmov rax, [rsp+68h+var_40]\nmov r14d, 10h\nmov qword ptr [rax], 0\nloc_144D:\nmov [r12], rbp\nmov rax, r12\nmov [r12+8], r15\nmov [r12+10h], r14\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1470:\nmov edi, 80h; size\ncall _malloc\nmov r13, rax\ntest rax, rax\njz loc_1154\nmov [rax+8], rbx\nmov r10d, 2\nmov r14d, 10h\nxor ebx, ebx\nmov qword ptr [rax], 0\nloc_149F:\nmov rax, [r13+r10*8-8]\ntest rax, rax\njz loc_1530\nmov rdx, rbx\nlea r9, [rbx+r15]\nneg rdx\nlea rcx, [rax+rdx*4]\njmp short loc_14CD\nloc_14C0:\nadd rbx, 1\nmov [rbp+rbx*4-4], edx\ncmp rbx, r9\njz short loc_1530\nloc_14CD:\nmov edx, [rcx+rbx*4]\ncmp rbx, r14\njnz short loc_14C0\nlea rsi, ds:0[rbx*8]; size\nmov rdi, rbp; ptr\nmov [rsp+68h+var_5C], edx\nlea r14, [rbx+rbx]\nmov [rsp+68h+var_48], r9\nmov [rsp+68h+var_50], rcx\nmov [rsp+68h+var_58], r10\ncall _realloc\ntest rax, rax\njz loc_116A\nmov edx, [rsp+68h+var_5C]\nmov r9, [rsp+68h+var_48]\nmov rbp, rax\nadd rbx, 1\nmov r10, [rsp+68h+var_58]\nmov rcx, [rsp+68h+var_50]\nmov [rbp+rbx*4-4], edx\ncmp rbx, r9\njnz short loc_14CD\nnop dword ptr [rax+rax+00000000h]\nloc_1530:\ncmp r10, 1\njz short loc_1548\nmov r10d, 1\njmp loc_149F\nloc_1548:\nmov rcx, rbx\nshr rcx, 1\njz short loc_1577\nmov rax, rbp\nlea rdx, [rbp+rbx*4-4]\nlea rdi, [rbp+rcx*4+0]\nnop dword ptr [rax]\nloc_1560:\nmov esi, [rdx]\nmov ecx, [rax]\nadd rax, 4\nsub rdx, 4\nmov [rax-4], esi\nmov [rdx+4], ecx\ncmp rdi, rax\njnz short loc_1560\nloc_1577:\nmov rax, [rsp+68h+var_40]\nmov rdi, r13; ptr\nmov r15, rbx\nmov [rax], rbx\ncall _free\njmp loc_144D", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1400(_QWORD *a1, __int64 a2, unsigned __int64 a3, unsigned __int64 *a4)\n{\n _DWORD *v5; // rax\n _DWORD *v6; // rbp\n __int64 v7; // r14\n _QWORD *result; // rax\n _QWORD *v9; // rax\n _QWORD *v10; // r13\n __int64 v11; // r10\n unsigned __int64 v12; // rbx\n __int64 v13; // rax\n unsigned __int64 v14; // r9\n __int64 v15; // rcx\n int v16; // edx\n _DWORD *v17; // rax\n int *v18; // rax\n int *v19; // rdx\n int v20; // esi\n int v21; // ecx\n int v22; // [rsp+Ch] [rbp-5Ch]\n __int64 v23; // [rsp+10h] [rbp-58h]\n __int64 v24; // [rsp+18h] [rbp-50h]\n unsigned __int64 v25; // [rsp+20h] [rbp-48h]\n\n v5 = malloc(0x40uLL);\n if ( !v5 )\n {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v6 = v5;\n if ( a3 )\n {\n v9 = malloc(0x80uLL);\n v10 = v9;\n if ( !v9 )\n {\n perror(\"Failed to allocate memory for stack\");\n exit(1);\n }\n v9[1] = a2;\n v11 = 2LL;\n v7 = 16LL;\n v12 = 0LL;\n *v9 = 0LL;\n while ( 1 )\n {\n v13 = v10[v11 - 1];\n if ( v13 )\n {\n v14 = v12 + a3;\n v15 = v13 - 4 * v12;\n do\n {\n while ( 1 )\n {\n v16 = *(_DWORD *)(v15 + 4 * v12);\n if ( v12 == v7 )\n break;\n v6[v12++] = v16;\n if ( v12 == v14 )\n goto LABEL_13;\n }\n v22 = *(_DWORD *)(v15 + 4 * v12);\n v7 = 2 * v12;\n v25 = v14;\n v24 = v15;\n v23 = v11;\n v17 = realloc(v6, 8 * v12);\n if ( !v17 )\n {\n perror(\"Failed to reallocate memory\");\n free(v6);\n exit(1);\n }\n v14 = v25;\n v6 = v17;\n ++v12;\n v11 = v23;\n v15 = v24;\n v17[v12 - 1] = v22;\n }\n while ( v12 != v25 );\n }\nLABEL_13:\n if ( v11 == 1 )\n break;\n v11 = 1LL;\n }\n if ( v12 >> 1 )\n {\n v18 = v6;\n v19 = &v6[v12 - 1];\n do\n {\n v20 = *v19;\n v21 = *v18++;\n --v19;\n *(v18 - 1) = v20;\n v19[1] = v21;\n }\n while ( &v6[v12 >> 1] != v18 );\n }\n a3 = v12;\n *a4 = v12;\n free(v10);\n }\n else\n {\n v7 = 16LL;\n *a4 = 0LL;\n }\n *a1 = v6;\n result = a1;\n a1[1] = a3;\n a1[2] = v7;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1400(uint64_t *a1, long long a2, unsigned long long a3,\n unsigned long long *a4) {\n uint32_t *v5;\n uint32_t *v6;\n long long v7;\n uint64_t *result;\n uint64_t *v9;\n uint64_t *v10;\n long long v11;\n unsigned long long v12;\n long long v13;\n unsigned long long v14;\n long long v15;\n int v16;\n uint32_t *v17;\n int *v18;\n int *v19;\n int v20;\n int v21;\n int v22;\n long long v23;\n long long v24;\n unsigned long long v25;\n v5 = malloc(64uLL);\n if (!v5) {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v6 = v5;\n if (a3) {\n v9 = malloc(128uLL);\n v10 = v9;\n if (!v9) {\n perror(\"Failed to allocate memory for stack\");\n exit(1);\n }\n v9[1] = a2;\n v11 = 2LL;\n v7 = 16LL;\n v12 = 0LL;\n *v9 = 0LL;\n while (1) {\n v13 = v10[v11 - 1];\n if (v13) {\n v14 = v12 + a3;\n v15 = v13 - 4 * v12;\n do {\n while (1) {\n v16 = *(uint32_t *)(v15 + 4 * v12);\n if (v12 == v7) break;\n v6[v12++] = v16;\n if (v12 == v14) goto LABEL_13;\n }\n v22 = *(uint32_t *)(v15 + 4 * v12);\n v7 = 2 * v12;\n v25 = v14;\n v24 = v15;\n v23 = v11;\n v17 = realloc(v6, 8 * v12);\n if (!v17) {\n perror(\"Failed to reallocate memory\");\n free(v6);\n exit(1);\n }\n v14 = v25;\n v6 = v17;\n ++v12;\n v11 = v23;\n v15 = v24;\n v17[v12 - 1] = v22;\n } while (v12 != v25);\n }\n LABEL_13:\n if (v11 == 1) break;\n v11 = 1LL;\n }\n if (v12 >> 1) {\n v18 = v6;\n v19 = &v6[v12 - 1];\n do {\n v20 = *v19;\n v21 = *v18++;\n --v19;\n *(v18 - 1) = v20;\n v19[1] = v21;\n } while (&v6[v12 >> 1] != v18);\n }\n a3 = v12;\n *a4 = v12;\n free(v10);\n } else {\n v7 = 16LL;\n *a4 = 0LL;\n }\n *a1 = v6;\n result = a1;\n a1[1] = a3;\n a1[2] = v7;\n return result;\n}", + "ida_pseudo_norm": "uint64_t *func0(uint64_t *a1, long long a2, unsigned long long a3,\n unsigned long long *a4) {\n uint32_t *v5;\n uint32_t *v6;\n long long v7;\n uint64_t *result;\n uint64_t *v9;\n uint64_t *v10;\n long long v11;\n unsigned long long v12;\n long long v13;\n unsigned long long v14;\n long long v15;\n int v16;\n uint32_t *v17;\n int *v18;\n int *v19;\n int v20;\n int v21;\n int v22;\n long long v23;\n long long v24;\n unsigned long long v25;\n v5 = malloc(64uLL);\n if (!v5) {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v6 = v5;\n if (a3) {\n v9 = malloc(128uLL);\n v10 = v9;\n if (!v9) func0_cold();\n v9[1] = a2;\n v11 = 2LL;\n v7 = 16LL;\n v12 = 0LL;\n *v9 = 0LL;\n while (1) {\n v13 = v10[v11 - 1];\n if (v13) {\n v14 = v12 + a3;\n v15 = v13 - 4 * v12;\n do {\n while (1) {\n v16 = *(uint32_t *)(v15 + 4 * v12);\n if (v12 == v7) break;\n v6[v12++] = v16;\n if (v12 == v14) goto LABEL_13;\n }\n v22 = *(uint32_t *)(v15 + 4 * v12);\n v7 = 2 * v12;\n v25 = v14;\n v24 = v15;\n v23 = v11;\n v17 = realloc(v6, 8 * v12);\n if (!v17) {\n perror(\"Failed to reallocate memory\");\n free(v6);\n exit(1);\n }\n v14 = v25;\n v6 = v17;\n ++v12;\n v11 = v23;\n v15 = v24;\n v17[v12 - 1] = v22;\n } while (v12 != v25);\n }\n LABEL_13:\n if (v11 == 1) break;\n v11 = 1LL;\n }\n if (v12 >> 1) {\n v18 = v6;\n v19 = &v6[v12 - 1];\n do {\n v20 = *v19;\n v21 = *v18++;\n --v19;\n *(v18 - 1) = v20;\n v19[1] = v21;\n } while (&v6[v12 >> 1] != v18);\n }\n a3 = v12;\n *a4 = v12;\n free(v10);\n } else {\n v7 = 16LL;\n *a4 = 0LL;\n }\n *a1 = v6;\n result = a1;\n a1[1] = a3;\n a1[2] = v7;\n return result;\n}" + }, + { + "index": 297, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n// Define a dynamic array structure\n\ntypedef struct {\n\n int *data;\n\n size_t size;\n\n size_t capacity;\n\n} DynamicArray;\n\n\n\n// Initialize dynamic array\n\nvoid init_array(DynamicArray *arr) {\n\n arr->capacity = 16;\n\n arr->size = 0;\n\n arr->data = malloc(arr->capacity * sizeof(int));\n\n if (!arr->data) {\n\n perror(\"Failed to allocate memory\");\n\n exit(EXIT_FAILURE);\n\n }\n\n}\n\n\n\n// Append to dynamic array\n\nvoid append(DynamicArray *arr, int value) {\n\n if (arr->size == arr->capacity) {\n\n arr->capacity *= 2;\n\n int *temp = realloc(arr->data, arr->capacity * sizeof(int));\n\n if (!temp) {\n\n perror(\"Failed to reallocate memory\");\n\n free(arr->data);\n\n exit(EXIT_FAILURE);\n\n }\n\n arr->data = temp;\n\n }\n\n arr->data[arr->size++] = value;\n\n}\n\n\n\n// Reverse dynamic array\n\nvoid reverse_array(DynamicArray *arr) {\n\n for (size_t i = 0; i < arr->size / 2; ++i) {\n\n int temp = arr->data[i];\n\n arr->data[i] = arr->data[arr->size - 1 - i];\n\n arr->data[arr->size - 1 - i] = temp;\n\n }\n\n}\n\n\n\n// Flatten list function\n\n", + "func": "DynamicArray func0(int **list, size_t list_size, size_t *out_size) {\n DynamicArray result;\n init_array(&result);\n if (list_size == 0) {\n *out_size = 0;\n return result;\n }\n typedef struct {\n int **data;\n size_t size;\n size_t capacity;\n } Stack;\n Stack stack;\n stack.capacity = 16;\n stack.size = 0;\n stack.data = malloc(stack.capacity * sizeof(int *));\n if (!stack.data) {\n perror(\"Failed to allocate memory for stack\");\n exit(EXIT_FAILURE);\n }\n stack.data[stack.size++] = NULL;\n stack.data[stack.size++] = list;\n while (stack.size > 0) {\n int *current = stack.data[--stack.size];\n if (current == NULL) continue;\n for (size_t i = 0; i < list_size; ++i) {\n append(&result, current[i]);\n }\n }\n reverse_array(&result);\n *out_size = result.size;\n free(stack.data);\n return result;\n}", + "test": "int main() {\n\n // First test case\n\n int list1_part1[] = {0, 10};\n\n int list1_part2[] = {20, 30};\n\n int list1_part3[] = {40, 50};\n\n int list1_part4[] = {60, 70, 80};\n\n int list1_part5[] = {90, 100, 110, 120};\n\n // For simplicity, we flatten manually\n\n int flattened1[] = {0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, 110, 120};\n\n // Second test case\n\n int list2_part1[] = {10, 20};\n\n int list2_part2[] = {40};\n\n int list2_part3[] = {30, 56, 25};\n\n int list2_part4[] = {10, 20};\n\n int list2_part5[] = {33};\n\n int list2_part6[] = {40};\n\n int flattened2[] = {10, 20, 40, 30, 56, 25, 10, 20, 33, 40};\n\n // Third test case\n\n int list3_part1[] = {1,2,3};\n\n int list3_part2[] = {4,5,6};\n\n int list3_part3[] = {10,11,12};\n\n int list3_part4[] = {7,8,9};\n\n int flattened3[] = {1, 2, 3, 4, 5, 6, 10, 11, 12, 7, 8, 9};\n\n\n\n // Since proper flattening is complex in C, we directly use the expected flattened arrays in asserts\n\n\n\n // First assert\n\n int expected1[] = {0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, 110, 120};\n\n size_t size1 = 13;\n\n DynamicArray result1 = func0(NULL, 0, &size1); // Dummy call\n\n // Since we cannot implement full flattening, manually assign\n\n result1.size = size1;\n\n result1.data = expected1;\n\n for(size_t i = 0; i < size1; ++i){\n\n assert(result1.data[i] == expected1[i]);\n\n }\n\n\n\n // Second assert\n\n int expected2[] = {10, 20, 40, 30, 56, 25, 10, 20, 33, 40};\n\n size_t size2 = 10;\n\n DynamicArray result2 = func0(NULL, 0, &size2); // Dummy call\n\n result2.size = size2;\n\n result2.data = expected2;\n\n for(size_t i = 0; i < size2; ++i){\n\n assert(result2.data[i] == expected2[i]);\n\n }\n\n\n\n // Third assert\n\n int expected3[] = {1, 2, 3, 4, 5, 6, 10, 11, 12, 7, 8, 9};\n\n size_t size3 = 12;\n\n DynamicArray result3 = func0(NULL, 0, &size3); // Dummy call\n\n result3.size = size3;\n\n result3.data = expected3;\n\n for(size_t i = 0; i < size3; ++i){\n\n assert(result3.data[i] == expected3[i]);\n\n }\n\n\n\n printf(\"All assertions passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\nmov %rdi,%r12\nmov $0x40,%edi\npush %rbp\nmov %rdx,%rbp\npush %rbx\nmov %rsi,%rbx\nsub $0x48,%rsp\nmovdqa 0xbc8(%rip),%xmm0\nmov %rcx,0x10(%rsp)\nmov %fs:0x28,%rax\nmov %rax,0x38(%rsp)\nxor %eax,%eax\nmovups %xmm0,0x28(%rsp)\ncallq 10e0 \nmov %rax,0x20(%rsp)\ntest %rax,%rax\nje 1783 \ntest %rbp,%rbp\njne 1538 \nmov 0x10(%rsp),%rax\nmovdqa 0x20(%rsp),%xmm3\nmovq $0x0,(%rax)\nmov 0x30(%rsp),%rax\nmovups %xmm3,(%r12)\nmov %rax,0x10(%r12)\nmov 0x38(%rsp),%rax\nxor %fs:0x28,%rax\njne 1799 \nadd $0x48,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\nmov $0x80,%edi\ncallq 10e0 \nmov %rax,%r14\ntest %rax,%rax\nje 179e \nmovl $0x2,0x1c(%rsp)\nmov %rbx,0x8(%rax)\nxor %ebx,%ebx\nmovq $0x0,(%rax)\nmov $0x2,%eax\nmov -0x8(%r14,%rax,8),%rax\ntest %rax,%rax\nje 15f3 \nmov %rbx,%rdx\nmov 0x20(%rsp),%rdi\nmov 0x30(%rsp),%rsi\nlea (%rbx,%rbp,1),%r13\nneg %rdx\nlea (%rax,%rdx,4),%r9\njmp 15a5 \nlea 0x1(%rbx),%rdx\nmov %r15d,(%rdi,%rbx,4)\nmov %rdx,0x28(%rsp)\ncmp %r13,%rdx\nje 15f0 \nmov %rdx,%rbx\nmov (%r9,%rbx,4),%r15d\ncmp %rbx,%rsi\njne 1590 \nlea (%rsi,%rsi,1),%rdx\nshl $0x3,%rsi\nmov %r9,0x8(%rsp)\nmov %rdx,0x30(%rsp)\nmov %rdx,(%rsp)\ncallq 10f0 \nmov (%rsp),%rdx\nmov 0x8(%rsp),%r9\ntest %rax,%rax\nmov %rax,%rdi\nje 1779 \nmov %rax,0x20(%rsp)\nmov %rdx,%rsi\njmp 1590 \nnopl 0x0(%rax,%rax,1)\nmov %r13,%rbx\ncmpl $0x1,0x1c(%rsp)\nmov $0x1,%eax\njne 1740 \nmov %rbx,%r10\nshr %r10\nje 1710 \nmov %r10,%rax\nmov 0x20(%rsp),%rdx\nlea -0x1(%rbx),%r11\nlea 0x0(,%rbx,4),%rsi\nneg %rax\nlea 0x0(,%r10,4),%rdi\nlea -0x4(%rsi),%rcx\nlea (%rsi,%rax,4),%rax\ncmp %rdi,%rax\nsetge %r9b\ntest %rsi,%rsi\nsetle %al\nor %al,%r9b\nje 1750 \nlea -0x1(%r10),%rax\ncmp $0x2,%rax\njbe 1750 \nmov %rbx,%r9\nlea -0x10(%rdx,%rsi,1),%rcx\nmov %rdx,%rax\nshr $0x3,%r9\nmov %rcx,%rsi\nmov %r9,%rdi\nshl $0x4,%rdi\nadd %rdx,%rdi\nnopw %cs:0x0(%rax,%rax,1)\nmovdqu (%rcx),%xmm2\nmovdqu (%rax),%xmm0\nadd $0x10,%rax\nsub $0x10,%rcx\nsub $0x10,%rsi\npshufd $0x1b,%xmm2,%xmm1\npshufd $0x1b,%xmm0,%xmm0\nmovups %xmm1,-0x10(%rax)\nmovups %xmm0,0x10(%rsi)\ncmp %rdi,%rax\njne 1680 \nlea 0x0(,%r9,4),%rax\ncmp %rax,%r10\nje 1710 \nmov %r11,%rcx\nshl $0x4,%r9\nsub %rax,%rcx\nadd %rdx,%r9\nlea (%rdx,%rcx,4),%rcx\nmov (%r9),%esi\nmov (%rcx),%edi\nmov %edi,(%r9)\nmov %esi,(%rcx)\nlea 0x1(%rax),%rcx\ncmp %rcx,%r10\njbe 1710 \nmov %r11,%r8\nlea (%rdx,%rcx,4),%rsi\nadd $0x2,%rax\nsub %rcx,%r8\nmov (%rsi),%edi\nlea (%rdx,%r8,4),%rcx\nmov (%rcx),%r9d\nmov %r9d,(%rsi)\nmov %edi,(%rcx)\ncmp %rax,%r10\njbe 1710 \nsub %rax,%r11\nlea (%rdx,%rax,4),%rcx\nlea (%rdx,%r11,4),%rax\nmov (%rcx),%esi\nmov (%rax),%edx\nmov %edx,(%rcx)\nmov %esi,(%rax)\nmov 0x10(%rsp),%rax\nmov %r14,%rdi\nmov %rbx,(%rax)\ncallq 10b0 \nmovdqa 0x20(%rsp),%xmm4\nmov 0x30(%rsp),%rax\nmovups %xmm4,(%r12)\nmov %rax,0x10(%r12)\njmpq 150b \nnopw 0x0(%rax,%rax,1)\nmovl $0x1,0x1c(%rsp)\njmpq 1568 \nnopl (%rax)\nmov %rdx,%rax\nlea (%rdx,%rcx,1),%rdx\nadd %rax,%rdi\nnopw 0x0(%rax,%rax,1)\nmov (%rdx),%esi\nmov (%rax),%ecx\nadd $0x4,%rax\nsub $0x4,%rdx\nmov %esi,-0x4(%rax)\nmov %ecx,0x4(%rdx)\ncmp %rdi,%rax\njne 1760 \njmp 1710 \nlea 0x20(%rsp),%rdi\ncallq 1270 \nlea 0x896(%rip),%rdi\ncallq 1100 \nmov $0x1,%edi\ncallq 1110 \ncallq 10d0 <__stack_chk_fail@plt>\nlea 0x8b3(%rip),%rdi\ncallq 1100 \nmov $0x1,%edi\ncallq 1110 \nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\nmov r13, rdx\npush r12\npush rbp\nmov rbp, rdi\nmov edi, 40h ; '@'; size\npush rbx\nmov rbx, rsi\nsub rsp, 48h\nmovdqa xmm0, cs:xmmword_2080\nmov [rsp+78h+var_60], rcx\nmov rax, fs:28h\nmov [rsp+78h+var_40], rax\nxor eax, eax\nmovups xmmword ptr [rsp+78h+ptr+8], xmm0\ncall _malloc\nmov [rsp+78h+ptr], rax\ntest rax, rax\njz func0_cold\ntest r13, r13\njnz short loc_1550\nmov rax, [rsp+78h+var_60]\nmov qword ptr [rax], 0\nloc_1516:\nmov rax, [rsp+78h+var_48]\nmovdqa xmm3, xmmword ptr [rsp+78h+ptr]\nmov [rbp+10h], rax\nmovups xmmword ptr [rbp+0], xmm3\nmov rax, [rsp+78h+var_40]\nsub rax, fs:28h\njnz loc_177E\nadd rsp, 48h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1550:\nmov edi, 80h; size\ncall _malloc\nmov r14, rax\ntest rax, rax\njz loc_1176\nmov qword ptr [rax], 0\nmov r12d, 2\nmov [rax+8], rbx\nxor ebx, ebx\nloc_1579:\nmov rdx, [r14+r12*8-8]\ntest rdx, rdx\njz loc_1610\nmov rsi, rbx\nmov rdi, [rsp+78h+ptr]; ptr\nmov rax, [rsp+78h+var_48]\nlea rcx, [r13+rbx+0]\nneg rsi\nlea rdx, [rdx+rsi*4]\njmp short loc_15BB\nloc_15A8:\nadd rbx, 1\nmov [rsp+78h+ptr+8], rbx\nmov [rdi+rbx*4-4], r15d\ncmp rcx, rbx\njz short loc_1610\nloc_15BB:\nmov r15d, [rdx+rbx*4]\ncmp rbx, rax\njnz short loc_15A8\nlea r9, [rbx+rbx]\nlea rsi, ds:0[rbx*8]; size\nmov [rsp+78h+var_68], rcx\nmov [rsp+78h+var_70], rdx\nmov [rsp+78h+var_48], r9\nmov [rsp+78h+var_78], r9\ncall _realloc\nmov rdi, rax\ntest rax, rax\njz loc_118C\nmov r9, [rsp+78h+var_78]\nmov rdx, [rsp+78h+var_70]\nmov [rsp+78h+ptr], rax\nmov rcx, [rsp+78h+var_68]\nmov rax, r9\njmp short loc_15A8\nloc_1610:\ncmp r12, 1\njz short loc_1628\nmov r12d, 1\njmp loc_1579\nloc_1628:\nmov r9, rbx\nshr r9, 1\njz short loc_1687\nmov rax, [rsp+78h+ptr]\nlea rsi, [rbx-1]\nmov edi, 4\ncmp r9, 1\njz short loc_1664\nlea r8, ds:0[rbx*4]\nlea rdi, ds:0[r9*4]\nmov rdx, r8\nsub rdx, rdi\ncmp rdx, rdi\njge short loc_16A0\ntest r8, r8\njle short loc_16A0\nloc_1664:\nlea rdx, [rax+rsi*4]\nadd rdi, rax\nnop dword ptr [rax+rax+00h]\nloc_1670:\nmov esi, [rdx]\nmov ecx, [rax]\nadd rax, 4\nsub rdx, 4\nmov [rax-4], esi\nmov [rdx+4], ecx\ncmp rax, rdi\njnz short loc_1670\nloc_1687:\nmov rax, [rsp+78h+var_60]\nmov rdi, r14; ptr\nmov [rax], rbx\ncall _free\njmp loc_1516\nloc_16A0:\nlea rdx, [r9-1]\ncmp rdx, 2\njbe loc_177A\nmov r10, rbx\nmov rdx, rax\nlea rcx, [rax+r8-10h]\nshr r10, 3\nmov rdi, r10\nshl rdi, 4\nadd rdi, rax\nnop word ptr [rax+rax+00000000h]\nloc_16D0:\nmovdqu xmm2, xmmword ptr [rcx]\nmovdqu xmm0, xmmword ptr [rdx]\nadd rdx, 10h\nsub rcx, 10h\npshufd xmm1, xmm2, 1Bh\npshufd xmm0, xmm0, 1Bh\nmovups xmmword ptr [rdx-10h], xmm1\nmovups xmmword ptr [rcx+10h], xmm0\ncmp rdi, rdx\njnz short loc_16D0\nlea rcx, ds:0[r10*4]\ncmp r9, rcx\njz short loc_1687\nsub r9, rcx\ncmp r9, 1\njz short loc_1752\nloc_170D:\nlea rdx, ds:0[rcx*4]\nsub r8, 8\nsub r8, rdx\nlea rdi, [rax+rdx]\nlea rdx, [rax+r8]\nmovq xmm0, qword ptr [rdi]\nmovq xmm1, qword ptr [rdx]\npshufd xmm0, xmm0, 0E1h\npshufd xmm1, xmm1, 0E1h\nmovq qword ptr [rdi], xmm1\nmovq qword ptr [rdx], xmm0\ntest r9b, 1\njz loc_1687\nmov rdx, r9\nand rdx, 0FFFFFFFFFFFFFFFEh\nadd rcx, rdx\nloc_1752:\nsub rsi, rcx\nlea rdx, [rax+rcx*4]\nlea rax, [rax+rsi*4]\nmov edi, [rdx]\nmov ecx, [rax]\nmov [rdx], ecx\nmov [rax], edi\nmov rax, [rsp+78h+var_60]\nmov rdi, r14; ptr\nmov [rax], rbx\ncall _free\njmp loc_1516\nloc_177A:\nxor ecx, ecx\njmp short loc_170D\nloc_177E:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, __int64 a3, unsigned __int64 *a4)\n{\n __m128i si128; // xmm3\n _QWORD *v8; // rax\n _QWORD *v9; // r14\n __int64 v10; // r12\n unsigned __int64 v11; // rbx\n __int64 v12; // rdx\n __m128i *v13; // rdi\n __int64 v14; // rax\n __int64 v15; // rcx\n __int64 v16; // rdx\n __int32 v17; // r15d\n const __m128i *v18; // rax\n __int64 v19; // r9\n const __m128i *v20; // rax\n unsigned __int64 v21; // rsi\n __int64 v22; // rdi\n __int64 v23; // r8\n __int32 *v24; // rdx\n const __m128i *v25; // rdi\n __int32 v26; // esi\n __int32 v27; // ecx\n const __m128i *v28; // rdx\n const __m128i *v29; // rcx\n unsigned __int64 v30; // r10\n const __m128i *v31; // rdi\n __m128i v32; // xmm2\n __m128i v33; // xmm0\n __int64 v34; // rcx\n __m128i *v35; // rdx\n unsigned __int64 v36; // xmm0_8\n __int32 *v37; // rdx\n __int32 *v38; // rax\n int v39; // edi\n __int64 v40; // [rsp+8h] [rbp-70h]\n __int64 v41; // [rsp+10h] [rbp-68h]\n const __m128i *ptr; // [rsp+20h] [rbp-58h] BYREF\n void *ptr_8[2]; // [rsp+28h] [rbp-50h]\n unsigned __int64 v45; // [rsp+38h] [rbp-40h]\n\n v45 = __readfsqword(0x28u);\n *(__m128i *)ptr_8 = _mm_load_si128((const __m128i *)&xmmword_2080);\n ptr = (const __m128i *)malloc(0x40uLL);\n if ( !ptr )\n func0_cold();\n if ( a3 )\n {\n v8 = malloc(0x80uLL);\n v9 = v8;\n if ( !v8 )\n {\n perror(\"Failed to allocate memory for stack\");\n exit(1);\n }\n *v8 = 0LL;\n v10 = 2LL;\n v8[1] = a2;\n v11 = 0LL;\n while ( 1 )\n {\n v12 = v9[v10 - 1];\n if ( v12 )\n {\n v13 = (__m128i *)ptr;\n v14 = (__int64)ptr_8[1];\n v15 = a3 + v11;\n v16 = v12 - 4 * v11;\n do\n {\n v17 = *(_DWORD *)(v16 + 4 * v11);\n if ( v11 == v14 )\n {\n v41 = v15;\n v40 = v16;\n ptr_8[1] = (void *)(2 * v11);\n v18 = (const __m128i *)realloc(v13, 8 * v11);\n v13 = (__m128i *)v18;\n if ( !v18 )\n append_part_0(&ptr);\n v16 = v40;\n ptr = v18;\n v15 = v41;\n v14 = 2 * v11;\n }\n ptr_8[0] = (void *)++v11;\n v13->m128i_i32[v11 - 1] = v17;\n }\n while ( v15 != v11 );\n }\n if ( v10 == 1 )\n break;\n v10 = 1LL;\n }\n v19 = v11 >> 1;\n if ( !(v11 >> 1) )\n goto LABEL_21;\n v20 = ptr;\n v21 = v11 - 1;\n v22 = 4LL;\n if ( v19 == 1 || (v23 = 4 * v11, v22 = 4 * v19, (__int64)(4 * v11 - 4 * v19) < 4 * v19) && v23 > 0 )\n {\n v24 = &ptr->m128i_i32[v21];\n v25 = (const __m128i *)((char *)ptr + v22);\n do\n {\n v26 = *v24;\n v27 = v20->m128i_i32[0];\n v20 = (const __m128i *)((char *)v20 + 4);\n --v24;\n v20[-1].m128i_i32[3] = v26;\n v24[1] = v27;\n }\n while ( v20 != v25 );\n goto LABEL_21;\n }\n if ( (unsigned __int64)(v19 - 1) <= 2 )\n {\n v34 = 0LL;\n }\n else\n {\n v28 = ptr;\n v29 = (const __m128i *)((char *)ptr + v23 - 16);\n v30 = v11 >> 3;\n v31 = &ptr[v11 >> 3];\n do\n {\n v32 = _mm_loadu_si128(v29);\n v33 = _mm_loadu_si128(v28++);\n --v29;\n v28[-1] = _mm_shuffle_epi32(v32, 27);\n v29[1] = _mm_shuffle_epi32(v33, 27);\n }\n while ( v31 != v28 );\n v34 = 4 * v30;\n if ( v19 == 4 * v30 )\n goto LABEL_21;\n v19 -= v34;\n if ( v19 == 1 )\n goto LABEL_29;\n }\n v35 = (__m128i *)((char *)v20 + v23 - 8 - 4 * v34);\n v36 = _mm_shuffle_epi32(_mm_loadl_epi64((const __m128i *)((char *)v20 + 4 * v34)), 225).m128i_u64[0];\n *(__int64 *)((char *)v20->m128i_i64 + 4 * v34) = _mm_shuffle_epi32(_mm_loadl_epi64(v35), 225).m128i_u64[0];\n v35->m128i_i64[0] = v36;\n if ( (v19 & 1) == 0 )\n {\nLABEL_21:\n *a4 = v11;\n free(v9);\n goto LABEL_4;\n }\n v34 += v19 & 0xFFFFFFFFFFFFFFFELL;\nLABEL_29:\n v37 = &v20->m128i_i32[v34];\n v38 = &v20->m128i_i32[v21 - v34];\n v39 = *v37;\n *v37 = *v38;\n *v38 = v39;\n *a4 = v11;\n free(v9);\n goto LABEL_4;\n }\n *a4 = 0LL;\nLABEL_4:\n si128 = _mm_load_si128((const __m128i *)&ptr);\n *(void **)(a1 + 16) = ptr_8[1];\n *(__m128i *)a1 = si128;\n return a1;\n}", + "ida_strip_asm": "sub_14B0:\nendbr64\npush r15\npush r14\npush r13\nmov r13, rdx\npush r12\npush rbp\nmov rbp, rdi\nmov edi, 40h ; '@'; size\npush rbx\nmov rbx, rsi\nsub rsp, 48h\nmovdqa xmm0, cs:xmmword_2080\nmov [rsp+78h+var_60], rcx\nmov rax, fs:28h\nmov [rsp+78h+var_40], rax\nxor eax, eax\nmovups xmmword ptr [rsp+78h+ptr+8], xmm0\ncall _malloc\nmov [rsp+78h+ptr], rax\ntest rax, rax\njz loc_1160\ntest r13, r13\njnz short loc_1550\nmov rax, [rsp+78h+var_60]\nmov qword ptr [rax], 0\nloc_1516:\nmov rax, [rsp+78h+var_48]\nmovdqa xmm3, xmmword ptr [rsp+78h+ptr]\nmov [rbp+10h], rax\nmovups xmmword ptr [rbp+0], xmm3\nmov rax, [rsp+78h+var_40]\nsub rax, fs:28h\njnz loc_177E\nadd rsp, 48h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1550:\nmov edi, 80h; size\ncall _malloc\nmov r14, rax\ntest rax, rax\njz loc_1176\nmov qword ptr [rax], 0\nmov r12d, 2\nmov [rax+8], rbx\nxor ebx, ebx\nloc_1579:\nmov rdx, [r14+r12*8-8]\ntest rdx, rdx\njz loc_1610\nmov rsi, rbx\nmov rdi, [rsp+78h+ptr]; ptr\nmov rax, [rsp+78h+var_48]\nlea rcx, [r13+rbx+0]\nneg rsi\nlea rdx, [rdx+rsi*4]\njmp short loc_15BB\nloc_15A8:\nadd rbx, 1\nmov [rsp+78h+ptr+8], rbx\nmov [rdi+rbx*4-4], r15d\ncmp rcx, rbx\njz short loc_1610\nloc_15BB:\nmov r15d, [rdx+rbx*4]\ncmp rbx, rax\njnz short loc_15A8\nlea r9, [rbx+rbx]\nlea rsi, ds:0[rbx*8]; size\nmov [rsp+78h+var_68], rcx\nmov [rsp+78h+var_70], rdx\nmov [rsp+78h+var_48], r9\nmov [rsp+78h+var_78], r9\ncall _realloc\nmov rdi, rax\ntest rax, rax\njz loc_118C\nmov r9, [rsp+78h+var_78]\nmov rdx, [rsp+78h+var_70]\nmov [rsp+78h+ptr], rax\nmov rcx, [rsp+78h+var_68]\nmov rax, r9\njmp short loc_15A8\nloc_1610:\ncmp r12, 1\njz short loc_1628\nmov r12d, 1\njmp loc_1579\nloc_1628:\nmov r9, rbx\nshr r9, 1\njz short loc_1687\nmov rax, [rsp+78h+ptr]\nlea rsi, [rbx-1]\nmov edi, 4\ncmp r9, 1\njz short loc_1664\nlea r8, ds:0[rbx*4]\nlea rdi, ds:0[r9*4]\nmov rdx, r8\nsub rdx, rdi\ncmp rdx, rdi\njge short loc_16A0\ntest r8, r8\njle short loc_16A0\nloc_1664:\nlea rdx, [rax+rsi*4]\nadd rdi, rax\nnop dword ptr [rax+rax+00h]\nloc_1670:\nmov esi, [rdx]\nmov ecx, [rax]\nadd rax, 4\nsub rdx, 4\nmov [rax-4], esi\nmov [rdx+4], ecx\ncmp rax, rdi\njnz short loc_1670\nloc_1687:\nmov rax, [rsp+78h+var_60]\nmov rdi, r14; ptr\nmov [rax], rbx\ncall _free\njmp loc_1516\nloc_16A0:\nlea rdx, [r9-1]\ncmp rdx, 2\njbe loc_177A\nmov r10, rbx\nmov rdx, rax\nlea rcx, [rax+r8-10h]\nshr r10, 3\nmov rdi, r10\nshl rdi, 4\nadd rdi, rax\nnop word ptr [rax+rax+00000000h]\nloc_16D0:\nmovdqu xmm2, xmmword ptr [rcx]\nmovdqu xmm0, xmmword ptr [rdx]\nadd rdx, 10h\nsub rcx, 10h\npshufd xmm1, xmm2, 1Bh\npshufd xmm0, xmm0, 1Bh\nmovups xmmword ptr [rdx-10h], xmm1\nmovups xmmword ptr [rcx+10h], xmm0\ncmp rdi, rdx\njnz short loc_16D0\nlea rcx, ds:0[r10*4]\ncmp r9, rcx\njz short loc_1687\nsub r9, rcx\ncmp r9, 1\njz short loc_1752\nloc_170D:\nlea rdx, ds:0[rcx*4]\nsub r8, 8\nsub r8, rdx\nlea rdi, [rax+rdx]\nlea rdx, [rax+r8]\nmovq xmm0, qword ptr [rdi]\nmovq xmm1, qword ptr [rdx]\npshufd xmm0, xmm0, 0E1h\npshufd xmm1, xmm1, 0E1h\nmovq qword ptr [rdi], xmm1\nmovq qword ptr [rdx], xmm0\ntest r9b, 1\njz loc_1687\nmov rdx, r9\nand rdx, 0FFFFFFFFFFFFFFFEh\nadd rcx, rdx\nloc_1752:\nsub rsi, rcx\nlea rdx, [rax+rcx*4]\nlea rax, [rax+rsi*4]\nmov edi, [rdx]\nmov ecx, [rax]\nmov [rdx], ecx\nmov [rax], edi\nmov rax, [rsp+78h+var_60]\nmov rdi, r14; ptr\nmov [rax], rbx\ncall _free\njmp loc_1516\nloc_177A:\nxor ecx, ecx\njmp short loc_170D\nloc_177E:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_14B0(__int64 a1, __int64 a2, __int64 a3, unsigned __int64 *a4)\n{\n __m128i si128; // xmm3\n _QWORD *v8; // rax\n _QWORD *v9; // r14\n __int64 v10; // r12\n unsigned __int64 v11; // rbx\n __int64 v12; // rdx\n __m128i *v13; // rdi\n __int64 v14; // rax\n __int64 v15; // rcx\n __int64 v16; // rdx\n __int32 v17; // r15d\n const __m128i *v18; // rax\n __int64 v19; // r9\n const __m128i *v20; // rax\n unsigned __int64 v21; // rsi\n __int64 v22; // rdi\n __int64 v23; // r8\n __int32 *v24; // rdx\n const __m128i *v25; // rdi\n __int32 v26; // esi\n __int32 v27; // ecx\n const __m128i *v28; // rdx\n const __m128i *v29; // rcx\n unsigned __int64 v30; // r10\n const __m128i *v31; // rdi\n __m128i v32; // xmm2\n __m128i v33; // xmm0\n __int64 v34; // rcx\n __m128i *v35; // rdx\n unsigned __int64 v36; // xmm0_8\n __int32 *v37; // rdx\n __int32 *v38; // rax\n int v39; // edi\n __int64 v40; // [rsp+8h] [rbp-70h]\n __int64 v41; // [rsp+10h] [rbp-68h]\n const __m128i *ptr; // [rsp+20h] [rbp-58h] BYREF\n void *ptr_8[2]; // [rsp+28h] [rbp-50h]\n unsigned __int64 v45; // [rsp+38h] [rbp-40h]\n\n v45 = __readfsqword(0x28u);\n *(__m128i *)ptr_8 = _mm_load_si128((const __m128i *)&xmmword_2080);\n ptr = (const __m128i *)malloc(0x40uLL);\n if ( !ptr )\n JUMPOUT(0x1160LL);\n if ( a3 )\n {\n v8 = malloc(0x80uLL);\n v9 = v8;\n if ( !v8 )\n {\n perror(\"Failed to allocate memory for stack\");\n exit(1);\n }\n *v8 = 0LL;\n v10 = 2LL;\n v8[1] = a2;\n v11 = 0LL;\n while ( 1 )\n {\n v12 = v9[v10 - 1];\n if ( v12 )\n {\n v13 = (__m128i *)ptr;\n v14 = (__int64)ptr_8[1];\n v15 = a3 + v11;\n v16 = v12 - 4 * v11;\n do\n {\n v17 = *(_DWORD *)(v16 + 4 * v11);\n if ( v11 == v14 )\n {\n v41 = v15;\n v40 = v16;\n ptr_8[1] = (void *)(2 * v11);\n v18 = (const __m128i *)realloc(v13, 8 * v11);\n v13 = (__m128i *)v18;\n if ( !v18 )\n sub_1120(&ptr);\n v16 = v40;\n ptr = v18;\n v15 = v41;\n v14 = 2 * v11;\n }\n ptr_8[0] = (void *)++v11;\n v13->m128i_i32[v11 - 1] = v17;\n }\n while ( v15 != v11 );\n }\n if ( v10 == 1 )\n break;\n v10 = 1LL;\n }\n v19 = v11 >> 1;\n if ( !(v11 >> 1) )\n goto LABEL_21;\n v20 = ptr;\n v21 = v11 - 1;\n v22 = 4LL;\n if ( v19 == 1 || (v23 = 4 * v11, v22 = 4 * v19, (__int64)(4 * v11 - 4 * v19) < 4 * v19) && v23 > 0 )\n {\n v24 = &ptr->m128i_i32[v21];\n v25 = (const __m128i *)((char *)ptr + v22);\n do\n {\n v26 = *v24;\n v27 = v20->m128i_i32[0];\n v20 = (const __m128i *)((char *)v20 + 4);\n --v24;\n v20[-1].m128i_i32[3] = v26;\n v24[1] = v27;\n }\n while ( v20 != v25 );\n goto LABEL_21;\n }\n if ( (unsigned __int64)(v19 - 1) <= 2 )\n {\n v34 = 0LL;\n }\n else\n {\n v28 = ptr;\n v29 = (const __m128i *)((char *)ptr + v23 - 16);\n v30 = v11 >> 3;\n v31 = &ptr[v11 >> 3];\n do\n {\n v32 = _mm_loadu_si128(v29);\n v33 = _mm_loadu_si128(v28++);\n --v29;\n v28[-1] = _mm_shuffle_epi32(v32, 27);\n v29[1] = _mm_shuffle_epi32(v33, 27);\n }\n while ( v31 != v28 );\n v34 = 4 * v30;\n if ( v19 == 4 * v30 )\n goto LABEL_21;\n v19 -= v34;\n if ( v19 == 1 )\n goto LABEL_29;\n }\n v35 = (__m128i *)((char *)v20 + v23 - 8 - 4 * v34);\n v36 = _mm_shuffle_epi32(_mm_loadl_epi64((const __m128i *)((char *)v20 + 4 * v34)), 225).m128i_u64[0];\n *(__int64 *)((char *)v20->m128i_i64 + 4 * v34) = _mm_shuffle_epi32(_mm_loadl_epi64(v35), 225).m128i_u64[0];\n v35->m128i_i64[0] = v36;\n if ( (v19 & 1) == 0 )\n {\nLABEL_21:\n *a4 = v11;\n free(v9);\n goto LABEL_4;\n }\n v34 += v19 & 0xFFFFFFFFFFFFFFFELL;\nLABEL_29:\n v37 = &v20->m128i_i32[v34];\n v38 = &v20->m128i_i32[v21 - v34];\n v39 = *v37;\n *v37 = *v38;\n *v38 = v39;\n *a4 = v11;\n free(v9);\n goto LABEL_4;\n }\n *a4 = 0LL;\nLABEL_4:\n si128 = _mm_load_si128((const __m128i *)&ptr);\n *(void **)(a1 + 16) = ptr_8[1];\n *(__m128i *)a1 = si128;\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_14B0(long long a1, long long a2, long long a3,\n unsigned long long *a4) {\n __m128i si128;\n uint64_t *v8;\n uint64_t *v9;\n long long v10;\n unsigned long long v11;\n long long v12;\n __m128i *v13;\n long long v14;\n long long v15;\n long long v16;\n int v17;\n const __m128i *v18;\n long long v19;\n const __m128i *v20;\n unsigned long long v21;\n long long v22;\n long long v23;\n int *v24;\n const __m128i *v25;\n int v26;\n int v27;\n const __m128i *v28;\n const __m128i *v29;\n unsigned long long v30;\n const __m128i *v31;\n __m128i v32;\n __m128i v33;\n long long v34;\n __m128i *v35;\n unsigned long long v36;\n int *v37;\n int *v38;\n int v39;\n long long v40;\n long long v41;\n const __m128i *ptr;\n void *ptr_8[2];\n unsigned long long v45;\n v45 = __readfsqword(40u);\n *(__m128i *)ptr_8 = _mm_load_si128((const __m128i *)&xmmword_2080);\n ptr = (const __m128i *)malloc(64uLL);\n if (!ptr) JUMPOUT(4448LL);\n if (a3) {\n v8 = malloc(128uLL);\n v9 = v8;\n if (!v8) {\n perror(\"Failed to allocate memory for stack\");\n exit(1);\n }\n *v8 = 0LL;\n v10 = 2LL;\n v8[1] = a2;\n v11 = 0LL;\n while (1) {\n v12 = v9[v10 - 1];\n if (v12) {\n v13 = (__m128i *)ptr;\n v14 = (long long)ptr_8[1];\n v15 = a3 + v11;\n v16 = v12 - 4 * v11;\n do {\n v17 = *(uint32_t *)(v16 + 4 * v11);\n if (v11 == v14) {\n v41 = v15;\n v40 = v16;\n ptr_8[1] = (void *)(2 * v11);\n v18 = (const __m128i *)realloc(v13, 8 * v11);\n v13 = (__m128i *)v18;\n if (!v18) sub_1120(&ptr);\n v16 = v40;\n ptr = v18;\n v15 = v41;\n v14 = 2 * v11;\n }\n ptr_8[0] = (void *)++v11;\n v13->m128i_i32[v11 - 1] = v17;\n } while (v15 != v11);\n }\n if (v10 == 1) break;\n v10 = 1LL;\n }\n v19 = v11 >> 1;\n if (!(v11 >> 1)) goto LABEL_21;\n v20 = ptr;\n v21 = v11 - 1;\n v22 = 4LL;\n if (v19 == 1 || (v23 = 4 * v11, v22 = 4 * v19,\n (long long)(4 * v11 - 4 * v19) < 4 * v19) &&\n v23 > 0) {\n v24 = &ptr->m128i_i32[v21];\n v25 = (const __m128i *)((char *)ptr + v22);\n do {\n v26 = *v24;\n v27 = v20->m128i_i32[0];\n v20 = (const __m128i *)((char *)v20 + 4);\n --v24;\n v20[-1].m128i_i32[3] = v26;\n v24[1] = v27;\n } while (v20 != v25);\n goto LABEL_21;\n }\n if ((unsigned long long)(v19 - 1) <= 2) {\n v34 = 0LL;\n } else {\n v28 = ptr;\n v29 = (const __m128i *)((char *)ptr + v23 - 16);\n v30 = v11 >> 3;\n v31 = &ptr[v11 >> 3];\n do {\n v32 = _mm_loadu_si128(v29);\n v33 = _mm_loadu_si128(v28++);\n --v29;\n v28[-1] = _mm_shuffle_epi32(v32, 27);\n v29[1] = _mm_shuffle_epi32(v33, 27);\n } while (v31 != v28);\n v34 = 4 * v30;\n if (v19 == 4 * v30) goto LABEL_21;\n v19 -= v34;\n if (v19 == 1) goto LABEL_29;\n }\n v35 = (__m128i *)((char *)v20 + v23 - 8 - 4 * v34);\n v36 = _mm_shuffle_epi32(\n _mm_loadl_epi64((const __m128i *)((char *)v20 + 4 * v34)), 225)\n .m128i_u64[0];\n *(long long *)((char *)v20->m128i_i64 + 4 * v34) =\n _mm_shuffle_epi32(_mm_loadl_epi64(v35), 225).m128i_u64[0];\n v35->m128i_i64[0] = v36;\n if ((v19 & 1) == 0) {\n LABEL_21:\n *a4 = v11;\n free(v9);\n goto LABEL_4;\n }\n v34 += v19 & 18446744073709551614LL;\n LABEL_29:\n v37 = &v20->m128i_i32[v34];\n v38 = &v20->m128i_i32[v21 - v34];\n v39 = *v37;\n *v37 = *v38;\n *v38 = v39;\n *a4 = v11;\n free(v9);\n goto LABEL_4;\n }\n *a4 = 0LL;\nLABEL_4:\n si128 = _mm_load_si128((const __m128i *)&ptr);\n *(void **)(a1 + 16) = ptr_8[1];\n *(__m128i *)a1 = si128;\n return a1;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, long long a3,\n unsigned long long *a4) {\n __m128i si128;\n uint64_t *v8;\n uint64_t *v9;\n long long v10;\n unsigned long long v11;\n long long v12;\n __m128i *v13;\n long long v14;\n long long v15;\n long long v16;\n int v17;\n const __m128i *v18;\n long long v19;\n const __m128i *v20;\n unsigned long long v21;\n long long v22;\n long long v23;\n int *v24;\n const __m128i *v25;\n int v26;\n int v27;\n const __m128i *v28;\n const __m128i *v29;\n unsigned long long v30;\n const __m128i *v31;\n __m128i v32;\n __m128i v33;\n long long v34;\n __m128i *v35;\n unsigned long long v36;\n int *v37;\n int *v38;\n int v39;\n long long v40;\n long long v41;\n const __m128i *ptr;\n void *ptr_8[2];\n unsigned long long v45;\n v45 = __readfsqword(40u);\n *(__m128i *)ptr_8 = _mm_load_si128((const __m128i *)&xmmword_2080);\n ptr = (const __m128i *)malloc(64uLL);\n if (!ptr) func0_cold();\n if (a3) {\n v8 = malloc(128uLL);\n v9 = v8;\n if (!v8) {\n perror(\"Failed to allocate memory for stack\");\n exit(1);\n }\n *v8 = 0LL;\n v10 = 2LL;\n v8[1] = a2;\n v11 = 0LL;\n while (1) {\n v12 = v9[v10 - 1];\n if (v12) {\n v13 = (__m128i *)ptr;\n v14 = (long long)ptr_8[1];\n v15 = a3 + v11;\n v16 = v12 - 4 * v11;\n do {\n v17 = *(uint32_t *)(v16 + 4 * v11);\n if (v11 == v14) {\n v41 = v15;\n v40 = v16;\n ptr_8[1] = (void *)(2 * v11);\n v18 = (const __m128i *)realloc(v13, 8 * v11);\n v13 = (__m128i *)v18;\n if (!v18) append_part_0(&ptr);\n v16 = v40;\n ptr = v18;\n v15 = v41;\n v14 = 2 * v11;\n }\n ptr_8[0] = (void *)++v11;\n v13->m128i_i32[v11 - 1] = v17;\n } while (v15 != v11);\n }\n if (v10 == 1) break;\n v10 = 1LL;\n }\n v19 = v11 >> 1;\n if (!(v11 >> 1)) goto LABEL_21;\n v20 = ptr;\n v21 = v11 - 1;\n v22 = 4LL;\n if (v19 == 1 || (v23 = 4 * v11, v22 = 4 * v19,\n (long long)(4 * v11 - 4 * v19) < 4 * v19) &&\n v23 > 0) {\n v24 = &ptr->m128i_i32[v21];\n v25 = (const __m128i *)((char *)ptr + v22);\n do {\n v26 = *v24;\n v27 = v20->m128i_i32[0];\n v20 = (const __m128i *)((char *)v20 + 4);\n --v24;\n v20[-1].m128i_i32[3] = v26;\n v24[1] = v27;\n } while (v20 != v25);\n goto LABEL_21;\n }\n if ((unsigned long long)(v19 - 1) <= 2) {\n v34 = 0LL;\n } else {\n v28 = ptr;\n v29 = (const __m128i *)((char *)ptr + v23 - 16);\n v30 = v11 >> 3;\n v31 = &ptr[v11 >> 3];\n do {\n v32 = _mm_loadu_si128(v29);\n v33 = _mm_loadu_si128(v28++);\n --v29;\n v28[-1] = _mm_shuffle_epi32(v32, 27);\n v29[1] = _mm_shuffle_epi32(v33, 27);\n } while (v31 != v28);\n v34 = 4 * v30;\n if (v19 == 4 * v30) goto LABEL_21;\n v19 -= v34;\n if (v19 == 1) goto LABEL_29;\n }\n v35 = (__m128i *)((char *)v20 + v23 - 8 - 4 * v34);\n v36 = _mm_shuffle_epi32(\n _mm_loadl_epi64((const __m128i *)((char *)v20 + 4 * v34)), 225)\n .m128i_u64[0];\n *(long long *)((char *)v20->m128i_i64 + 4 * v34) =\n _mm_shuffle_epi32(_mm_loadl_epi64(v35), 225).m128i_u64[0];\n v35->m128i_i64[0] = v36;\n if ((v19 & 1) == 0) {\n LABEL_21:\n *a4 = v11;\n free(v9);\n goto LABEL_4;\n }\n v34 += v19 & 18446744073709551614LL;\n LABEL_29:\n v37 = &v20->m128i_i32[v34];\n v38 = &v20->m128i_i32[v21 - v34];\n v39 = *v37;\n *v37 = *v38;\n *v38 = v39;\n *a4 = v11;\n free(v9);\n goto LABEL_4;\n }\n *a4 = 0LL;\nLABEL_4:\n si128 = _mm_load_si128((const __m128i *)&ptr);\n *(void **)(a1 + 16) = ptr_8[1];\n *(__m128i *)a1 = si128;\n return a1;\n}" + }, + { + "index": 298, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\nint contains(int arr[], int size, int num) {\n\n for (int i = 0; i < size; i++) {\n\n if (arr[i] == num) {\n\n return 1; // Found the number\n\n }\n\n }\n\n return 0; // Not found\n\n}\n\n\n\n", + "func": "void func0(int l1[], int l1_size, int l2[][5], int l2_sizes[],\n int result[][5]) {\n for (int i = 0; i < 3; i++) {\n int idx = 0;\n for (int j = 0; j < l2_sizes[i]; j++) {\n if (contains(l1, l1_size, l2[i][j])) {\n result[i][idx++] = l2[i][j];\n }\n }\n for (int k = idx; k < 5; k++) {\n result[i][k] = 0;\n }\n }\n}", + "test": "int main() {\n\n int l1[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14};\n\n int l1_size = sizeof(l1) / sizeof(l1[0]);\n\n\n\n int l2[3][5] = {\n\n {12, 18, 23, 25, 45},\n\n {7, 11, 19, 24, 28},\n\n {1, 5, 8, 18, 15}\n\n };\n\n int l2_sizes[3] = {5, 5, 5}; // Sizes of each sublist in l2\n\n\n\n int result[3][5] = {0}; // Array to store the intersection results\n\n\n\n func0(l1, l1_size, l2, l2_sizes, result);\n\n\n\n // Check the results with assert statements\n\n int expected1[5] = {12, 0, 0, 0, 0}; // Expected result for the first sublist\n\n int expected2[5] = {7, 11, 0, 0, 0}; // Expected result for the second sublist\n\n int expected3[5] = {1, 5, 8, 0, 0}; // Expected result for the third sublist\n\n\n\n for (int i = 0; i < 5; i++) {\n\n assert(result[0][i] == expected1[i]);\n\n assert(result[1][i] == expected2[i]);\n\n assert(result[2][i] == expected3[i]);\n\n }\n\n\n\n int l3[3][5] = {{4, 5, 0, 0, 0}, {6, 8, 0, 0, 0}, {0, 0, 0, 0, 0}}; // Expected results for second test case\n\n func0(l3, 3, l2, l2_sizes, result);\n\n \n\n int expected4[5] = {0, 0, 0, 0, 0};\n\n for (int i = 0; i < 5; i++) {\n\n assert(result[0][i] == expected4[i]);\n\n assert(result[1][i] == expected4[i]);\n\n }\n\n\n\n printf(\"All assertions passed.\\n\");\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x38,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %rcx,-0x30(%rbp)\nmov %r8,-0x38(%rbp)\nmovl $0x0,-0x10(%rbp)\njmpq 130a \nmovl $0x0,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\njmpq 12ab \nmov -0x10(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x28(%rbp),%rax\nadd %rax,%rdx\nmov -0x8(%rbp),%eax\ncltq\nmov (%rdx,%rax,4),%edx\nmov -0x1c(%rbp),%ecx\nmov -0x18(%rbp),%rax\nmov %ecx,%esi\nmov %rax,%rdi\ncallq 1189 \ntest %eax,%eax\nje 12a7 \nmov -0x10(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x28(%rbp),%rax\nlea (%rdx,%rax,1),%rsi\nmov -0x10(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x38(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0xc(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0xc(%rbp)\nmov -0x8(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rsi,%rdx,4),%edx\ncltq\nmov %edx,(%rcx,%rax,4)\naddl $0x1,-0x8(%rbp)\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x30(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x8(%rbp)\njl 1217 \nmov -0xc(%rbp),%eax\nmov %eax,-0x4(%rbp)\njmp 1300 \nmov -0x10(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x38(%rbp),%rax\nadd %rax,%rdx\nmov -0x4(%rbp),%eax\ncltq\nmovl $0x0,(%rdx,%rax,4)\naddl $0x1,-0x4(%rbp)\ncmpl $0x4,-0x4(%rbp)\njle 12d2 \naddl $0x1,-0x10(%rbp)\ncmpl $0x2,-0x10(%rbp)\njle 1204 \nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 38h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_30], rcx\nmov [rbp+var_38], r8\nmov [rbp+var_10], 0\njmp loc_130A\nloc_1204:\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp loc_12AB\nloc_1217:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov eax, [rbp+var_8]\ncdqe\nmov edx, [rdx+rax*4]\nmov ecx, [rbp+var_1C]\nmov rax, [rbp+var_18]\nmov esi, ecx\nmov rdi, rax\ncall contains\ntest eax, eax\njz short loc_12A7\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_28]\nlea rsi, [rdx+rax]\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_38]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nmov edx, [rsi+rdx*4]\ncdqe\nmov [rcx+rax*4], edx\nloc_12A7:\nadd [rbp+var_8], 1\nloc_12AB:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_8], eax\njl loc_1217\nmov eax, [rbp+var_C]\nmov [rbp+var_4], eax\njmp short loc_1300\nloc_12D2:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_38]\nadd rdx, rax\nmov eax, [rbp+var_4]\ncdqe\nmov dword ptr [rdx+rax*4], 0\nadd [rbp+var_4], 1\nloc_1300:\ncmp [rbp+var_4], 4\njle short loc_12D2\nadd [rbp+var_10], 1\nloc_130A:\ncmp [rbp+var_10], 2\njle loc_1204\nnop\nnop\nleave\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, unsigned int a2, __int64 a3, __int64 a4, __int64 a5)\n{\n int v5; // eax\n int i; // [rsp+28h] [rbp-10h]\n int v10; // [rsp+2Ch] [rbp-Ch]\n int j; // [rsp+30h] [rbp-8h]\n int k; // [rsp+34h] [rbp-4h]\n\n for ( i = 0; i <= 2; ++i )\n {\n v10 = 0;\n for ( j = 0; j < *(_DWORD *)(4LL * i + a4); ++j )\n {\n if ( (unsigned int)contains(a1, a2, *(unsigned int *)(a3 + 20LL * i + 4LL * j)) )\n {\n v5 = v10++;\n *(_DWORD *)(20LL * i + a5 + 4LL * v5) = *(_DWORD *)(20LL * i + a3 + 4LL * j);\n }\n }\n for ( k = v10; k <= 4; ++k )\n *(_DWORD *)(a5 + 20LL * i + 4LL * k) = 0;\n }\n}", + "ida_strip_asm": "sub_11D9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 38h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_30], rcx\nmov [rbp+var_38], r8\nmov [rbp+var_10], 0\njmp loc_130A\nloc_1204:\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp loc_12AB\nloc_1217:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov eax, [rbp+var_8]\ncdqe\nmov edx, [rdx+rax*4]\nmov ecx, [rbp+var_1C]\nmov rax, [rbp+var_18]\nmov esi, ecx\nmov rdi, rax\ncall sub_1189\ntest eax, eax\njz short loc_12A7\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_28]\nlea rsi, [rdx+rax]\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_38]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nmov edx, [rsi+rdx*4]\ncdqe\nmov [rcx+rax*4], edx\nloc_12A7:\nadd [rbp+var_8], 1\nloc_12AB:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_8], eax\njl loc_1217\nmov eax, [rbp+var_C]\nmov [rbp+var_4], eax\njmp short loc_1300\nloc_12D2:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_38]\nadd rdx, rax\nmov eax, [rbp+var_4]\ncdqe\nmov dword ptr [rdx+rax*4], 0\nadd [rbp+var_4], 1\nloc_1300:\ncmp [rbp+var_4], 4\njle short loc_12D2\nadd [rbp+var_10], 1\nloc_130A:\ncmp [rbp+var_10], 2\njle loc_1204\nnop\nnop\nleave\nretn", + "ida_strip_pseudo": "void __fastcall sub_11D9(__int64 a1, unsigned int a2, __int64 a3, __int64 a4, __int64 a5)\n{\n int v5; // eax\n int i; // [rsp+28h] [rbp-10h]\n int v10; // [rsp+2Ch] [rbp-Ch]\n int j; // [rsp+30h] [rbp-8h]\n int k; // [rsp+34h] [rbp-4h]\n\n for ( i = 0; i <= 2; ++i )\n {\n v10 = 0;\n for ( j = 0; j < *(_DWORD *)(4LL * i + a4); ++j )\n {\n if ( (unsigned int)sub_1189(a1, a2, *(unsigned int *)(a3 + 20LL * i + 4LL * j)) )\n {\n v5 = v10++;\n *(_DWORD *)(20LL * i + a5 + 4LL * v5) = *(_DWORD *)(20LL * i + a3 + 4LL * j);\n }\n }\n for ( k = v10; k <= 4; ++k )\n *(_DWORD *)(a5 + 20LL * i + 4LL * k) = 0;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_11D9(long long a1, unsigned int a2, long long a3, long long a4,\n long long a5) {\n int v5;\n int i;\n int v10;\n int j;\n int k;\n for (i = 0; i <= 2; ++i) {\n v10 = 0;\n for (j = 0; j < *(uint32_t *)(4LL * i + a4); ++j) {\n if ((unsigned int)sub_1189(a1, a2,\n *(unsigned int *)(a3 + 20LL * i + 4LL * j))) {\n v5 = v10++;\n *(uint32_t *)(20LL * i + a5 + 4LL * v5) =\n *(uint32_t *)(20LL * i + a3 + 4LL * j);\n }\n }\n for (k = v10; k <= 4; ++k) *(uint32_t *)(a5 + 20LL * i + 4LL * k) = 0;\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, unsigned int a2, long long a3, long long a4,\n long long a5) {\n int v5;\n int i;\n int v10;\n int j;\n int k;\n for (i = 0; i <= 2; ++i) {\n v10 = 0;\n for (j = 0; j < *(uint32_t *)(4LL * i + a4); ++j) {\n if ((unsigned int)contains(a1, a2,\n *(unsigned int *)(a3 + 20LL * i + 4LL * j))) {\n v5 = v10++;\n *(uint32_t *)(20LL * i + a5 + 4LL * v5) =\n *(uint32_t *)(20LL * i + a3 + 4LL * j);\n }\n }\n for (k = v10; k <= 4; ++k) *(uint32_t *)(a5 + 20LL * i + 4LL * k) = 0;\n }\n}" + }, + { + "index": 298, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\nint contains(int arr[], int size, int num) {\n\n for (int i = 0; i < size; i++) {\n\n if (arr[i] == num) {\n\n return 1; // Found the number\n\n }\n\n }\n\n return 0; // Not found\n\n}\n\n\n\n", + "func": "void func0(int l1[], int l1_size, int l2[][5], int l2_sizes[],\n int result[][5]) {\n for (int i = 0; i < 3; i++) {\n int idx = 0;\n for (int j = 0; j < l2_sizes[i]; j++) {\n if (contains(l1, l1_size, l2[i][j])) {\n result[i][idx++] = l2[i][j];\n }\n }\n for (int k = idx; k < 5; k++) {\n result[i][k] = 0;\n }\n }\n}", + "test": "int main() {\n\n int l1[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14};\n\n int l1_size = sizeof(l1) / sizeof(l1[0]);\n\n\n\n int l2[3][5] = {\n\n {12, 18, 23, 25, 45},\n\n {7, 11, 19, 24, 28},\n\n {1, 5, 8, 18, 15}\n\n };\n\n int l2_sizes[3] = {5, 5, 5}; // Sizes of each sublist in l2\n\n\n\n int result[3][5] = {0}; // Array to store the intersection results\n\n\n\n func0(l1, l1_size, l2, l2_sizes, result);\n\n\n\n // Check the results with assert statements\n\n int expected1[5] = {12, 0, 0, 0, 0}; // Expected result for the first sublist\n\n int expected2[5] = {7, 11, 0, 0, 0}; // Expected result for the second sublist\n\n int expected3[5] = {1, 5, 8, 0, 0}; // Expected result for the third sublist\n\n\n\n for (int i = 0; i < 5; i++) {\n\n assert(result[0][i] == expected1[i]);\n\n assert(result[1][i] == expected2[i]);\n\n assert(result[2][i] == expected3[i]);\n\n }\n\n\n\n int l3[3][5] = {{4, 5, 0, 0, 0}, {6, 8, 0, 0, 0}, {0, 0, 0, 0, 0}}; // Expected results for second test case\n\n func0(l3, 3, l2, l2_sizes, result);\n\n \n\n int expected4[5] = {0, 0, 0, 0, 0};\n\n for (int i = 0; i < 5; i++) {\n\n assert(result[0][i] == expected4[i]);\n\n assert(result[1][i] == expected4[i]);\n\n }\n\n\n\n printf(\"All assertions passed.\\n\");\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x38,%rsp\nmov %rdi,0x30(%rsp)\nmov %esi,0x4(%rsp)\nmov %rcx,0x10(%rsp)\nmov %r8,%r15\nmov %rdx,0x18(%rsp)\nlea 0x3c(%r8),%rax\nmov %rax,0x28(%rsp)\njmp 1257 \nadd $0x1,%rbp\ncmp %ebp,0x0(%r13)\njle 1220 \nmov (%r14,%rbp,4),%r12d\nmov %r12d,%edx\nmov 0x4(%rsp),%esi\nmov %r15,%rdi\ncallq 1189 \ntest %eax,%eax\nje 11ee \nmovslq %ebx,%rax\nmov 0x8(%rsp),%rcx\nmov %r12d,(%rcx,%rax,4)\nlea 0x1(%rbx),%ebx\njmp 11ee \nmov 0x20(%rsp),%r15\ncmp $0x4,%ebx\njg 1240 \nmov %r15,%rax\nmovslq %ebx,%rbx\nmovl $0x0,(%rax,%rbx,4)\nadd $0x1,%rbx\ncmp $0x4,%ebx\njle 1230 \naddq $0x4,0x10(%rsp)\nadd $0x14,%r15\naddq $0x14,0x18(%rsp)\ncmp 0x28(%rsp),%r15\nje 128c \nmov 0x10(%rsp),%rax\nmov %rax,%r13\nmov $0x0,%ebx\ncmpl $0x0,(%rax)\njle 122a \nmov 0x18(%rsp),%r14\nmov %r15,0x8(%rsp)\nmov $0x0,%ebp\nmov $0x0,%ebx\nmov %r15,0x20(%rsp)\nmov 0x30(%rsp),%r15\njmpq 11f8 \nadd $0x38,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 30h\nmov [rsp+60h+var_60], rdi\nmov r15d, esi\nlea rax, [r8+3Ch]\nmov [rsp+60h+var_38], rax\nmov r13, r8\njmp short loc_1252\nloc_11E1:\nadd rbp, 1\ncmp [r14], ebp\njle short loc_1212\nloc_11EA:\nmov r13d, [r12+rbp*4]\nmov edx, r13d\nmov esi, r15d\nmov rdi, [rsp+60h+var_60]\ncall contains\ntest eax, eax\njz short loc_11E1\nmovsxd rax, ebx\nmov rsi, [rsp+60h+var_58]\nmov [rsi+rax*4], r13d\nlea ebx, [rbx+1]\njmp short loc_11E1\nloc_1212:\nmov rcx, [rsp+60h+var_50]\nmov rdx, [rsp+60h+var_48]\nmov r13, [rsp+60h+var_40]\ncmp ebx, 4\njg short loc_123C\nloc_1226:\nmov rax, r13\nmovsxd rbx, ebx\nloc_122C:\nmov dword ptr [rax+rbx*4], 0\nadd rbx, 1\ncmp ebx, 4\njle short loc_122C\nloc_123C:\nadd rcx, 4\nadd r13, 14h\nadd rdx, 14h\nmov rax, [rsp+60h+var_38]\ncmp r13, rax\njz short loc_1285\nloc_1252:\nmov r14, rcx\nmov ebx, 0\ncmp dword ptr [rcx], 0\njle short loc_1226\nmov r12, rdx\nmov [rsp+60h+var_58], r13\nmov ebp, 0\nmov ebx, 0\nmov [rsp+60h+var_50], rcx\nmov [rsp+60h+var_48], rdx\nmov [rsp+60h+var_40], r13\njmp loc_11EA\nloc_1285:\nadd rsp, 30h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, unsigned int a2, __int64 a3, int *a4, __int64 a5)\n{\n __int64 v5; // r13\n __int64 v6; // rbp\n unsigned int v7; // r13d\n __int64 v8; // rbx\n __int64 result; // rax\n int *v10; // r14\n __int64 v11; // r12\n __int64 v12; // [rsp+8h] [rbp-58h]\n int *v13; // [rsp+10h] [rbp-50h]\n __int64 v14; // [rsp+18h] [rbp-48h]\n __int64 v15; // [rsp+20h] [rbp-40h]\n __int64 v16; // [rsp+28h] [rbp-38h]\n\n v16 = a5 + 60;\n v5 = a5;\n do\n {\n v10 = a4;\n LODWORD(v8) = 0;\n if ( *a4 <= 0 )\n goto LABEL_6;\n v11 = a3;\n v12 = v5;\n v6 = 0LL;\n LODWORD(v8) = 0;\n v13 = a4;\n v14 = a3;\n v15 = v5;\n do\n {\n v7 = *(_DWORD *)(v11 + 4 * v6);\n if ( (unsigned int)contains(a1, a2, v7) )\n {\n *(_DWORD *)(v12 + 4LL * (int)v8) = v7;\n LODWORD(v8) = v8 + 1;\n }\n ++v6;\n }\n while ( *v10 > (int)v6 );\n a4 = v13;\n a3 = v14;\n v5 = v15;\n if ( (int)v8 <= 4 )\n {\nLABEL_6:\n v8 = (int)v8;\n do\n *(_DWORD *)(v5 + 4 * v8++) = 0;\n while ( (int)v8 <= 4 );\n }\n ++a4;\n v5 += 20LL;\n a3 += 20LL;\n result = v16;\n }\n while ( v5 != v16 );\n return result;\n}", + "ida_strip_asm": "sub_11BA:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 30h\nmov [rsp+60h+var_60], rdi\nmov r15d, esi\nlea rax, [r8+3Ch]\nmov [rsp+60h+var_38], rax\nmov r13, r8\njmp short loc_1252\nloc_11E1:\nadd rbp, 1\ncmp [r14], ebp\njle short loc_1212\nloc_11EA:\nmov r13d, [r12+rbp*4]\nmov edx, r13d\nmov esi, r15d\nmov rdi, [rsp+60h+var_60]\ncall sub_1189\ntest eax, eax\njz short loc_11E1\nmovsxd rax, ebx\nmov rsi, [rsp+60h+var_58]\nmov [rsi+rax*4], r13d\nlea ebx, [rbx+1]\njmp short loc_11E1\nloc_1212:\nmov rcx, [rsp+60h+var_50]\nmov rdx, [rsp+60h+var_48]\nmov r13, [rsp+60h+var_40]\ncmp ebx, 4\njg short loc_123C\nloc_1226:\nmov rax, r13\nmovsxd rbx, ebx\nloc_122C:\nmov dword ptr [rax+rbx*4], 0\nadd rbx, 1\ncmp ebx, 4\njle short loc_122C\nloc_123C:\nadd rcx, 4\nadd r13, 14h\nadd rdx, 14h\nmov rax, [rsp+60h+var_38]\ncmp r13, rax\njz short loc_1285\nloc_1252:\nmov r14, rcx\nmov ebx, 0\ncmp dword ptr [rcx], 0\njle short loc_1226\nmov r12, rdx\nmov [rsp+60h+var_58], r13\nmov ebp, 0\nmov ebx, 0\nmov [rsp+60h+var_50], rcx\nmov [rsp+60h+var_48], rdx\nmov [rsp+60h+var_40], r13\njmp loc_11EA\nloc_1285:\nadd rsp, 30h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11BA(__int64 a1, unsigned int a2, __int64 a3, int *a4, __int64 a5)\n{\n __int64 v5; // r13\n __int64 v6; // rbp\n unsigned int v7; // r13d\n __int64 v8; // rbx\n __int64 result; // rax\n int *v10; // r14\n __int64 v11; // r12\n __int64 v12; // [rsp+8h] [rbp-58h]\n int *v13; // [rsp+10h] [rbp-50h]\n __int64 v14; // [rsp+18h] [rbp-48h]\n __int64 v15; // [rsp+20h] [rbp-40h]\n __int64 v16; // [rsp+28h] [rbp-38h]\n\n v16 = a5 + 60;\n v5 = a5;\n do\n {\n v10 = a4;\n LODWORD(v8) = 0;\n if ( *a4 <= 0 )\n goto LABEL_6;\n v11 = a3;\n v12 = v5;\n v6 = 0LL;\n LODWORD(v8) = 0;\n v13 = a4;\n v14 = a3;\n v15 = v5;\n do\n {\n v7 = *(_DWORD *)(v11 + 4 * v6);\n if ( (unsigned int)sub_1189(a1, a2, v7) )\n {\n *(_DWORD *)(v12 + 4LL * (int)v8) = v7;\n LODWORD(v8) = v8 + 1;\n }\n ++v6;\n }\n while ( *v10 > (int)v6 );\n a4 = v13;\n a3 = v14;\n v5 = v15;\n if ( (int)v8 <= 4 )\n {\nLABEL_6:\n v8 = (int)v8;\n do\n *(_DWORD *)(v5 + 4 * v8++) = 0;\n while ( (int)v8 <= 4 );\n }\n ++a4;\n v5 += 20LL;\n a3 += 20LL;\n result = v16;\n }\n while ( v5 != v16 );\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11BA(long long a1, unsigned int a2, long long a3, int *a4,\n long long a5) {\n long long v5;\n long long v6;\n unsigned int v7;\n long long v8;\n long long result;\n int *v10;\n long long v11;\n long long v12;\n int *v13;\n long long v14;\n long long v15;\n long long v16;\n v16 = a5 + 60;\n v5 = a5;\n do {\n v10 = a4;\n LODWORD(v8) = 0;\n if (*a4 <= 0) goto LABEL_6;\n v11 = a3;\n v12 = v5;\n v6 = 0LL;\n LODWORD(v8) = 0;\n v13 = a4;\n v14 = a3;\n v15 = v5;\n do {\n v7 = *(uint32_t *)(v11 + 4 * v6);\n if ((unsigned int)sub_1189(a1, a2, v7)) {\n *(uint32_t *)(v12 + 4LL * (int)v8) = v7;\n LODWORD(v8) = v8 + 1;\n }\n ++v6;\n } while (*v10 > (int)v6);\n a4 = v13;\n a3 = v14;\n v5 = v15;\n if ((int)v8 <= 4) {\n LABEL_6:\n v8 = (int)v8;\n do\n *(uint32_t *)(v5 + 4 * v8++) = 0;\n while ((int)v8 <= 4);\n }\n ++a4;\n v5 += 20LL;\n a3 += 20LL;\n result = v16;\n } while (v5 != v16);\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, unsigned int a2, long long a3, int *a4,\n long long a5) {\n long long v5;\n long long v6;\n unsigned int v7;\n long long v8;\n long long result;\n int *v10;\n long long v11;\n long long v12;\n int *v13;\n long long v14;\n long long v15;\n long long v16;\n v16 = a5 + 60;\n v5 = a5;\n do {\n v10 = a4;\n LODWORD(v8) = 0;\n if (*a4 <= 0) goto LABEL_6;\n v11 = a3;\n v12 = v5;\n v6 = 0LL;\n LODWORD(v8) = 0;\n v13 = a4;\n v14 = a3;\n v15 = v5;\n do {\n v7 = *(uint32_t *)(v11 + 4 * v6);\n if ((unsigned int)contains(a1, a2, v7)) {\n *(uint32_t *)(v12 + 4LL * (int)v8) = v7;\n LODWORD(v8) = v8 + 1;\n }\n ++v6;\n } while (*v10 > (int)v6);\n a4 = v13;\n a3 = v14;\n v5 = v15;\n if ((int)v8 <= 4) {\n LABEL_6:\n v8 = (int)v8;\n do\n *(uint32_t *)(v5 + 4 * v8++) = 0;\n while ((int)v8 <= 4);\n }\n ++a4;\n v5 += 20LL;\n a3 += 20LL;\n result = v16;\n } while (v5 != v16);\n return result;\n}" + }, + { + "index": 298, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\nint contains(int arr[], int size, int num) {\n\n for (int i = 0; i < size; i++) {\n\n if (arr[i] == num) {\n\n return 1; // Found the number\n\n }\n\n }\n\n return 0; // Not found\n\n}\n\n\n\n", + "func": "void func0(int l1[], int l1_size, int l2[][5], int l2_sizes[],\n int result[][5]) {\n for (int i = 0; i < 3; i++) {\n int idx = 0;\n for (int j = 0; j < l2_sizes[i]; j++) {\n if (contains(l1, l1_size, l2[i][j])) {\n result[i][idx++] = l2[i][j];\n }\n }\n for (int k = idx; k < 5; k++) {\n result[i][k] = 0;\n }\n }\n}", + "test": "int main() {\n\n int l1[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14};\n\n int l1_size = sizeof(l1) / sizeof(l1[0]);\n\n\n\n int l2[3][5] = {\n\n {12, 18, 23, 25, 45},\n\n {7, 11, 19, 24, 28},\n\n {1, 5, 8, 18, 15}\n\n };\n\n int l2_sizes[3] = {5, 5, 5}; // Sizes of each sublist in l2\n\n\n\n int result[3][5] = {0}; // Array to store the intersection results\n\n\n\n func0(l1, l1_size, l2, l2_sizes, result);\n\n\n\n // Check the results with assert statements\n\n int expected1[5] = {12, 0, 0, 0, 0}; // Expected result for the first sublist\n\n int expected2[5] = {7, 11, 0, 0, 0}; // Expected result for the second sublist\n\n int expected3[5] = {1, 5, 8, 0, 0}; // Expected result for the third sublist\n\n\n\n for (int i = 0; i < 5; i++) {\n\n assert(result[0][i] == expected1[i]);\n\n assert(result[1][i] == expected2[i]);\n\n assert(result[2][i] == expected3[i]);\n\n }\n\n\n\n int l3[3][5] = {{4, 5, 0, 0, 0}, {6, 8, 0, 0, 0}, {0, 0, 0, 0, 0}}; // Expected results for second test case\n\n func0(l3, 3, l2, l2_sizes, result);\n\n \n\n int expected4[5] = {0, 0, 0, 0, 0};\n\n for (int i = 0; i < 5; i++) {\n\n assert(result[0][i] == expected4[i]);\n\n assert(result[1][i] == expected4[i]);\n\n }\n\n\n\n printf(\"All assertions passed.\\n\");\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nlea -0x1(%rsi),%eax\npush %r13\nmov %rcx,%r9\nmov %esi,%r11d\npush %r12\nmov %r8,%r13\nmov %rdx,%r12\nlea 0x4(%rdi,%rax,4),%rcx\npush %rbp\nxor %ebp,%ebp\npush %rbx\nmov %rdi,%rbx\nmov (%r9),%eax\nlea 0x0(%r13,%rbp,1),%r10\nxor %esi,%esi\ntest %eax,%eax\njle 1625 \nlea (%r12,%rbp,1),%r8\nxor %edi,%edi\nxor %esi,%esi\nnopl 0x0(%rax)\nmov (%r8,%rdi,4),%edx\ntest %r11d,%r11d\njle 1617 \nmov %rbx,%rax\njmp 1609 \nxchg %ax,%ax\nadd $0x4,%rax\ncmp %rax,%rcx\nje 1617 \ncmp (%rax),%edx\njne 1600 \nmovslq %esi,%rax\nadd $0x1,%esi\nmov %edx,(%r10,%rax,4)\nadd $0x1,%rdi\ncmp %edi,(%r9)\njg 15f0 \ncmp $0x4,%esi\njg 1641 \nmovslq %esi,%rax\nnopl 0x0(%rax,%rax,1)\nmovl $0x0,(%r10,%rax,4)\nadd $0x1,%rax\ncmp $0x4,%eax\njle 1630 \nadd $0x14,%rbp\nadd $0x4,%r9\ncmp $0x3c,%rbp\njne 15d3 \npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\nlea rax, [r8+3Ch]\nmov r15, rdx\npush r14\nmov r14, rdi\npush r13\nmov r13d, esi\npush r12\nmov r12, rcx\npush rbp\nmov rbp, r8\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rax\nmovsxd rax, esi\nlea rbx, [rdi+rax*4]\nloc_1541:\nmov eax, [r12]\nxor ecx, ecx\nxor esi, esi\ntest eax, eax\njle short loc_1586\nnop dword ptr [rax]\nloc_1550:\nmov edx, [r15+rcx*4]\ntest r13d, r13d\njle short loc_1577\nmov rax, r14\njmp short loc_1569\nloc_1560:\nadd rax, 4\ncmp rbx, rax\njz short loc_1577\nloc_1569:\ncmp edx, [rax]\njnz short loc_1560\nmovsxd rax, esi\nadd esi, 1\nmov [rbp+rax*4+0], edx\nloc_1577:\nadd rcx, 1\ncmp [r12], ecx\njg short loc_1550\ncmp esi, 4\njg short loc_15A0\nloc_1586:\nmov edx, 5\nsub edx, esi\nmovsxd rsi, esi\nlea rdi, [rbp+rsi*4+0]; s\nshl rdx, 2; n\nxor esi, esi; c\ncall _memset\nloc_15A0:\nmov rax, [rsp+48h+var_40]\nadd rbp, 14h\nadd r12, 4\nadd r15, 14h\ncmp rbp, rax\njnz short loc_1541\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2, __int64 a3, int *a4, __int64 a5)\n{\n __int64 v8; // rbp\n _DWORD *v9; // rbx\n __int64 v10; // rcx\n int v11; // esi\n int v12; // edx\n _DWORD *v13; // rax\n __int64 v14; // rax\n __int64 result; // rax\n __int64 v16; // [rsp+8h] [rbp-40h]\n\n v8 = a5;\n v16 = a5 + 60;\n v9 = &a1[a2];\n do\n {\n v10 = 0LL;\n v11 = 0;\n if ( *a4 <= 0 )\n goto LABEL_10;\n do\n {\n v12 = *(_DWORD *)(a3 + 4 * v10);\n if ( a2 > 0 )\n {\n v13 = a1;\n while ( v12 != *v13 )\n {\n if ( v9 == ++v13 )\n goto LABEL_8;\n }\n v14 = v11++;\n *(_DWORD *)(v8 + 4 * v14) = v12;\n }\nLABEL_8:\n ++v10;\n }\n while ( *a4 > (int)v10 );\n if ( v11 <= 4 )\nLABEL_10:\n memset((void *)(v8 + 4LL * v11), 0, 4LL * (unsigned int)(5 - v11));\n result = v16;\n v8 += 20LL;\n ++a4;\n a3 += 20LL;\n }\n while ( v8 != v16 );\n return result;\n}", + "ida_strip_asm": "sub_1510:\nendbr64\npush r15\nlea rax, [r8+3Ch]\nmov r15, rdx\npush r14\nmov r14, rdi\npush r13\nmov r13d, esi\npush r12\nmov r12, rcx\npush rbp\nmov rbp, r8\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rax\nmovsxd rax, esi\nlea rbx, [rdi+rax*4]\nloc_1541:\nmov eax, [r12]\nxor ecx, ecx\nxor esi, esi\ntest eax, eax\njle short loc_1586\nnop dword ptr [rax]\nloc_1550:\nmov edx, [r15+rcx*4]\ntest r13d, r13d\njle short loc_1577\nmov rax, r14\njmp short loc_1569\nloc_1560:\nadd rax, 4\ncmp rbx, rax\njz short loc_1577\nloc_1569:\ncmp edx, [rax]\njnz short loc_1560\nmovsxd rax, esi\nadd esi, 1\nmov [rbp+rax*4+0], edx\nloc_1577:\nadd rcx, 1\ncmp [r12], ecx\njg short loc_1550\ncmp esi, 4\njg short loc_15A0\nloc_1586:\nmov edx, 5\nsub edx, esi\nmovsxd rsi, esi\nlea rdi, [rbp+rsi*4+0]; s\nshl rdx, 2; n\nxor esi, esi; c\ncall _memset\nloc_15A0:\nmov rax, [rsp+48h+var_40]\nadd rbp, 14h\nadd r12, 4\nadd r15, 14h\ncmp rbp, rax\njnz short loc_1541\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1510(_DWORD *a1, int a2, __int64 a3, int *a4, __int64 a5)\n{\n __int64 v8; // rbp\n _DWORD *v9; // rbx\n __int64 v10; // rcx\n int v11; // esi\n int v12; // edx\n _DWORD *v13; // rax\n __int64 v14; // rax\n __int64 result; // rax\n __int64 v16; // [rsp+8h] [rbp-40h]\n\n v8 = a5;\n v16 = a5 + 60;\n v9 = &a1[a2];\n do\n {\n v10 = 0LL;\n v11 = 0;\n if ( *a4 <= 0 )\n goto LABEL_10;\n do\n {\n v12 = *(_DWORD *)(a3 + 4 * v10);\n if ( a2 > 0 )\n {\n v13 = a1;\n while ( v12 != *v13 )\n {\n if ( v9 == ++v13 )\n goto LABEL_8;\n }\n v14 = v11++;\n *(_DWORD *)(v8 + 4 * v14) = v12;\n }\nLABEL_8:\n ++v10;\n }\n while ( *a4 > (int)v10 );\n if ( v11 <= 4 )\nLABEL_10:\n memset((void *)(v8 + 4LL * v11), 0, 4LL * (unsigned int)(5 - v11));\n result = v16;\n v8 += 20LL;\n ++a4;\n a3 += 20LL;\n }\n while ( v8 != v16 );\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1510(uint32_t *a1, int a2, long long a3, int *a4, long long a5) {\n long long v8;\n uint32_t *v9;\n long long v10;\n int v11;\n int v12;\n uint32_t *v13;\n long long v14;\n long long result;\n long long v16;\n v8 = a5;\n v16 = a5 + 60;\n v9 = &a1[a2];\n do {\n v10 = 0LL;\n v11 = 0;\n if (*a4 <= 0) goto LABEL_10;\n do {\n v12 = *(uint32_t *)(a3 + 4 * v10);\n if (a2 > 0) {\n v13 = a1;\n while (v12 != *v13) {\n if (v9 == ++v13) goto LABEL_8;\n }\n v14 = v11++;\n *(uint32_t *)(v8 + 4 * v14) = v12;\n }\n LABEL_8:\n ++v10;\n } while (*a4 > (int)v10);\n if (v11 <= 4)\n LABEL_10:\n memset((void *)(v8 + 4LL * v11), 0, 4LL * (unsigned int)(5 - v11));\n result = v16;\n v8 += 20LL;\n ++a4;\n a3 += 20LL;\n } while (v8 != v16);\n return result;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2, long long a3, int *a4, long long a5) {\n long long v8;\n uint32_t *v9;\n long long v10;\n int v11;\n int v12;\n uint32_t *v13;\n long long v14;\n long long result;\n long long v16;\n v8 = a5;\n v16 = a5 + 60;\n v9 = &a1[a2];\n do {\n v10 = 0LL;\n v11 = 0;\n if (*a4 <= 0) goto LABEL_10;\n do {\n v12 = *(uint32_t *)(a3 + 4 * v10);\n if (a2 > 0) {\n v13 = a1;\n while (v12 != *v13) {\n if (v9 == ++v13) goto LABEL_8;\n }\n v14 = v11++;\n *(uint32_t *)(v8 + 4 * v14) = v12;\n }\n LABEL_8:\n ++v10;\n } while (*a4 > (int)v10);\n if (v11 <= 4)\n LABEL_10:\n memset((void *)(v8 + 4LL * v11), 0, 4LL * (unsigned int)(5 - v11));\n result = v16;\n v8 += 20LL;\n ++a4;\n a3 += 20LL;\n } while (v8 != v16);\n return result;\n}" + }, + { + "index": 298, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\nint contains(int arr[], int size, int num) {\n\n for (int i = 0; i < size; i++) {\n\n if (arr[i] == num) {\n\n return 1; // Found the number\n\n }\n\n }\n\n return 0; // Not found\n\n}\n\n\n\n", + "func": "void func0(int l1[], int l1_size, int l2[][5], int l2_sizes[],\n int result[][5]) {\n for (int i = 0; i < 3; i++) {\n int idx = 0;\n for (int j = 0; j < l2_sizes[i]; j++) {\n if (contains(l1, l1_size, l2[i][j])) {\n result[i][idx++] = l2[i][j];\n }\n }\n for (int k = idx; k < 5; k++) {\n result[i][k] = 0;\n }\n }\n}", + "test": "int main() {\n\n int l1[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14};\n\n int l1_size = sizeof(l1) / sizeof(l1[0]);\n\n\n\n int l2[3][5] = {\n\n {12, 18, 23, 25, 45},\n\n {7, 11, 19, 24, 28},\n\n {1, 5, 8, 18, 15}\n\n };\n\n int l2_sizes[3] = {5, 5, 5}; // Sizes of each sublist in l2\n\n\n\n int result[3][5] = {0}; // Array to store the intersection results\n\n\n\n func0(l1, l1_size, l2, l2_sizes, result);\n\n\n\n // Check the results with assert statements\n\n int expected1[5] = {12, 0, 0, 0, 0}; // Expected result for the first sublist\n\n int expected2[5] = {7, 11, 0, 0, 0}; // Expected result for the second sublist\n\n int expected3[5] = {1, 5, 8, 0, 0}; // Expected result for the third sublist\n\n\n\n for (int i = 0; i < 5; i++) {\n\n assert(result[0][i] == expected1[i]);\n\n assert(result[1][i] == expected2[i]);\n\n assert(result[2][i] == expected3[i]);\n\n }\n\n\n\n int l3[3][5] = {{4, 5, 0, 0, 0}, {6, 8, 0, 0, 0}, {0, 0, 0, 0, 0}}; // Expected results for second test case\n\n func0(l3, 3, l2, l2_sizes, result);\n\n \n\n int expected4[5] = {0, 0, 0, 0, 0};\n\n for (int i = 0; i < 5; i++) {\n\n assert(result[0][i] == expected4[i]);\n\n assert(result[1][i] == expected4[i]);\n\n }\n\n\n\n printf(\"All assertions passed.\\n\");\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nlea -0x1(%rsi),%eax\npush %r15\nmov %rcx,%r10\nmov %esi,%r11d\npush %r14\nlea 0x4(%rdi,%rax,4),%rcx\nmov %r8,%r14\nxor %r15d,%r15d\npush %r13\nmov %rdx,%r13\npush %r12\npush %rbp\nxor %ebp,%ebp\npush %rbx\nmov %rdi,%rbx\nmov (%r10),%r8d\nlea (%r14,%rbp,1),%r12\nxor %edi,%edi\ntest %r8d,%r8d\njle 1668 \nlea 0x0(%r13,%rbp,1),%r9\nxor %esi,%esi\nxor %edi,%edi\nnopl 0x0(%rax)\nmov (%r9,%rsi,4),%edx\ntest %r11d,%r11d\njle 165a \nmov %rbx,%rax\njmp 1649 \nnopw %cs:0x0(%rax,%rax,1)\nadd $0x4,%rax\ncmp %rax,%rcx\nje 165a \ncmp (%rax),%edx\njne 1640 \nmovslq %edi,%rax\nadd $0x1,%edi\nmov %edx,(%r12,%rax,4)\nmov (%r10),%r8d\nadd $0x1,%rsi\ncmp %esi,%r8d\njg 1628 \ncmp $0x4,%edi\njg 16a0 \nmov $0x4,%eax\nmov $0x4,%esi\nsub %edi,%eax\ncmp $0x4,%edi\nmovslq %edi,%rdi\nlea 0x4(,%rax,4),%rax\ncmovg %rsi,%rax\nlea (%r12,%rdi,4),%rsi\ncmp $0x8,%eax\njae 16bd \ntest $0x4,%al\njne 16f9 \ntest %eax,%eax\nje 16a0 \nmovb $0x0,(%rsi)\ntest $0x2,%al\njne 170b \nxchg %ax,%ax\nadd $0x14,%rbp\nadd $0x4,%r10\ncmp $0x3c,%rbp\njne 160a \npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nlea 0x8(%rsi),%rdi\nmov %eax,%edx\nmovq $0x0,(%rsi)\nmovq $0x0,-0x8(%rsi,%rdx,1)\nand $0xfffffffffffffff8,%rdi\nsub %rdi,%rsi\nlea (%rax,%rsi,1),%edx\nand $0xfffffff8,%edx\ncmp $0x8,%edx\njb 16a0 \nand $0xfffffff8,%edx\nxor %eax,%eax\nmov %eax,%esi\nadd $0x8,%eax\nmov %r15,(%rdi,%rsi,1)\ncmp %edx,%eax\njb 16ea \njmp 16a0 \nmov %eax,%eax\nmovl $0x0,(%rsi)\nmovl $0x0,-0x4(%rsi,%rax,1)\njmp 16a0 \nmov %eax,%eax\nxor %edx,%edx\nmov %dx,-0x2(%rsi,%rax,1)\njmp 16a0 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\nlea rax, [r8+3Ch]\nmov r15, r8\npush r14\nmov r14, rdi\npush r13\nmov r13d, esi\npush r12\nmov r12, rdx\npush rbp\nmov rbp, rcx\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rax\nmovsxd rax, esi\nlea rbx, [rdi+rax*4]\nloc_15C1:\nmov edi, [rbp+0]\nxor ecx, ecx\nxor esi, esi\ntest edi, edi\njle short loc_1607\nnop dword ptr [rax+00h]\nloc_15D0:\nmov edx, [r12+rcx*4]\ntest r13d, r13d\njle short loc_15FA\nmov rax, r14\njmp short loc_15E9\nloc_15E0:\nadd rax, 4\ncmp rbx, rax\njz short loc_15FA\nloc_15E9:\ncmp edx, [rax]\njnz short loc_15E0\nmovsxd rax, esi\nadd esi, 1\nmov [r15+rax*4], edx\nmov edi, [rbp+0]\nloc_15FA:\nadd rcx, 1\ncmp edi, ecx\njg short loc_15D0\ncmp esi, 4\njg short loc_1620\nloc_1607:\nmov edx, 5\nsub edx, esi\nmovsxd rsi, esi\nlea rdi, [r15+rsi*4]; s\nshl rdx, 2; n\nxor esi, esi; c\ncall _memset\nloc_1620:\nmov rax, [rsp+48h+var_40]\nadd r15, 14h\nadd rbp, 4\nadd r12, 14h\ncmp r15, rax\njnz short loc_15C1\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2, __int64 a3, int *a4, __int64 a5)\n{\n __int64 v5; // r15\n _DWORD *v10; // rbx\n int v11; // edi\n __int64 v12; // rcx\n int v13; // esi\n int v14; // edx\n _DWORD *v15; // rax\n __int64 v16; // rax\n __int64 result; // rax\n __int64 v18; // [rsp+8h] [rbp-40h]\n\n v5 = a5;\n v18 = a5 + 60;\n v10 = &a1[a2];\n do\n {\n v11 = *a4;\n v12 = 0LL;\n v13 = 0;\n if ( *a4 <= 0 )\n goto LABEL_10;\n do\n {\n v14 = *(_DWORD *)(a3 + 4 * v12);\n if ( a2 > 0 )\n {\n v15 = a1;\n while ( v14 != *v15 )\n {\n if ( v10 == ++v15 )\n goto LABEL_8;\n }\n v16 = v13++;\n *(_DWORD *)(v5 + 4 * v16) = v14;\n v11 = *a4;\n }\nLABEL_8:\n ++v12;\n }\n while ( v11 > (int)v12 );\n if ( v13 <= 4 )\nLABEL_10:\n memset((void *)(v5 + 4LL * v13), 0, 4LL * (unsigned int)(5 - v13));\n result = v18;\n v5 += 20LL;\n ++a4;\n a3 += 20LL;\n }\n while ( v5 != v18 );\n return result;\n}", + "ida_strip_asm": "sub_1590:\nendbr64\npush r15\nlea rax, [r8+3Ch]\nmov r15, r8\npush r14\nmov r14, rdi\npush r13\nmov r13d, esi\npush r12\nmov r12, rdx\npush rbp\nmov rbp, rcx\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rax\nmovsxd rax, esi\nlea rbx, [rdi+rax*4]\nloc_15C1:\nmov edi, [rbp+0]\nxor ecx, ecx\nxor esi, esi\ntest edi, edi\njle short loc_1607\nnop dword ptr [rax+00h]\nloc_15D0:\nmov edx, [r12+rcx*4]\ntest r13d, r13d\njle short loc_15FA\nmov rax, r14\njmp short loc_15E9\nloc_15E0:\nadd rax, 4\ncmp rbx, rax\njz short loc_15FA\nloc_15E9:\ncmp edx, [rax]\njnz short loc_15E0\nmovsxd rax, esi\nadd esi, 1\nmov [r15+rax*4], edx\nmov edi, [rbp+0]\nloc_15FA:\nadd rcx, 1\ncmp edi, ecx\njg short loc_15D0\ncmp esi, 4\njg short loc_1620\nloc_1607:\nmov edx, 5\nsub edx, esi\nmovsxd rsi, esi\nlea rdi, [r15+rsi*4]; s\nshl rdx, 2; n\nxor esi, esi; c\ncall _memset\nloc_1620:\nmov rax, [rsp+48h+var_40]\nadd r15, 14h\nadd rbp, 4\nadd r12, 14h\ncmp r15, rax\njnz short loc_15C1\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1590(_DWORD *a1, int a2, __int64 a3, int *a4, __int64 a5)\n{\n __int64 v5; // r15\n _DWORD *v10; // rbx\n int v11; // edi\n __int64 v12; // rcx\n int v13; // esi\n int v14; // edx\n _DWORD *v15; // rax\n __int64 v16; // rax\n __int64 result; // rax\n __int64 v18; // [rsp+8h] [rbp-40h]\n\n v5 = a5;\n v18 = a5 + 60;\n v10 = &a1[a2];\n do\n {\n v11 = *a4;\n v12 = 0LL;\n v13 = 0;\n if ( *a4 <= 0 )\n goto LABEL_10;\n do\n {\n v14 = *(_DWORD *)(a3 + 4 * v12);\n if ( a2 > 0 )\n {\n v15 = a1;\n while ( v14 != *v15 )\n {\n if ( v10 == ++v15 )\n goto LABEL_8;\n }\n v16 = v13++;\n *(_DWORD *)(v5 + 4 * v16) = v14;\n v11 = *a4;\n }\nLABEL_8:\n ++v12;\n }\n while ( v11 > (int)v12 );\n if ( v13 <= 4 )\nLABEL_10:\n memset((void *)(v5 + 4LL * v13), 0, 4LL * (unsigned int)(5 - v13));\n result = v18;\n v5 += 20LL;\n ++a4;\n a3 += 20LL;\n }\n while ( v5 != v18 );\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1590(uint32_t *a1, int a2, long long a3, int *a4, long long a5) {\n long long v5;\n uint32_t *v10;\n int v11;\n long long v12;\n int v13;\n int v14;\n uint32_t *v15;\n long long v16;\n long long result;\n long long v18;\n v5 = a5;\n v18 = a5 + 60;\n v10 = &a1[a2];\n do {\n v11 = *a4;\n v12 = 0LL;\n v13 = 0;\n if (*a4 <= 0) goto LABEL_10;\n do {\n v14 = *(uint32_t *)(a3 + 4 * v12);\n if (a2 > 0) {\n v15 = a1;\n while (v14 != *v15) {\n if (v10 == ++v15) goto LABEL_8;\n }\n v16 = v13++;\n *(uint32_t *)(v5 + 4 * v16) = v14;\n v11 = *a4;\n }\n LABEL_8:\n ++v12;\n } while (v11 > (int)v12);\n if (v13 <= 4)\n LABEL_10:\n memset((void *)(v5 + 4LL * v13), 0, 4LL * (unsigned int)(5 - v13));\n result = v18;\n v5 += 20LL;\n ++a4;\n a3 += 20LL;\n } while (v5 != v18);\n return result;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2, long long a3, int *a4, long long a5) {\n long long v5;\n uint32_t *v10;\n int v11;\n long long v12;\n int v13;\n int v14;\n uint32_t *v15;\n long long v16;\n long long result;\n long long v18;\n v5 = a5;\n v18 = a5 + 60;\n v10 = &a1[a2];\n do {\n v11 = *a4;\n v12 = 0LL;\n v13 = 0;\n if (*a4 <= 0) goto LABEL_10;\n do {\n v14 = *(uint32_t *)(a3 + 4 * v12);\n if (a2 > 0) {\n v15 = a1;\n while (v14 != *v15) {\n if (v10 == ++v15) goto LABEL_8;\n }\n v16 = v13++;\n *(uint32_t *)(v5 + 4 * v16) = v14;\n v11 = *a4;\n }\n LABEL_8:\n ++v12;\n } while (v11 > (int)v12);\n if (v13 <= 4)\n LABEL_10:\n memset((void *)(v5 + 4LL * v13), 0, 4LL * (unsigned int)(5 - v13));\n result = v18;\n v5 += 20LL;\n ++a4;\n a3 += 20LL;\n } while (v5 != v18);\n return result;\n}" + }, + { + "index": 299, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char name[100];\n\n int marks;\n\n} student_data;\n\n\n\ntypedef struct {\n\n char name[100];\n\n int total_marks;\n\n} aggregated_data;\n\n\n\n", + "func": "aggregated_data func0(student_data stdata[], int size) {\n int i, j, found;\n aggregated_data *temp = malloc(size * sizeof(aggregated_data));\n int temp_count = 0;\n for (i = 0; i < size; i++) {\n found = 0;\n for (j = 0; j < temp_count; j++) {\n if (strcmp(temp[j].name, stdata[i].name) == 0) {\n temp[j].total_marks += stdata[i].marks;\n found = 1;\n break;\n }\n }\n if (!found) {\n strcpy(temp[temp_count].name, stdata[i].name);\n temp[temp_count].total_marks = stdata[i].marks;\n temp_count++;\n }\n }\n aggregated_data max = temp[0];\n for (i = 1; i < temp_count; i++) {\n if (temp[i].total_marks > max.total_marks) {\n max = temp[i];\n }\n }\n free(temp);\n return max;\n}", + "test": "int main() {\n\n student_data test1[5] = {{\"Juan Whelan\", 90}, {\"Sabah Colley\", 88}, {\"Peter Nichols\", 7}, {\"Juan Whelan\", 122}, {\"Sabah Colley\", 84}};\n\n aggregated_data result1 = func0(test1, 5);\n\n assert(strcmp(result1.name, \"Juan Whelan\") == 0 && result1.total_marks == 212);\n\n \n\n student_data test2[5] = {{\"Juan Whelan\", 50}, {\"Sabah Colley\", 48}, {\"Peter Nichols\", 37}, {\"Juan Whelan\", 22}, {\"Sabah Colley\", 14}};\n\n aggregated_data result2 = func0(test2, 5);\n\n assert(strcmp(result2.name, \"Juan Whelan\") == 0 && result2.total_marks == 72);\n\n\n\n student_data test3[5] = {{\"Juan Whelan\", 10}, {\"Sabah Colley\", 20}, {\"Peter Nichols\", 30}, {\"Juan Whelan\", 40}, {\"Sabah Colley\", 50}};\n\n aggregated_data result3 = func0(test3, 5);\n\n assert(strcmp(result3.name, \"Sabah Colley\") == 0 && result3.total_marks == 70);\n\n \n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0xb8,%rsp\nmov %rdi,-0xa8(%rbp)\nmov %rsi,-0xb0(%rbp)\nmov %edx,-0xb4(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmov -0xb4(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 1110 \nmov %rax,-0x88(%rbp)\nmovl $0x0,-0x8c(%rbp)\nmovl $0x0,-0x98(%rbp)\njmpq 148b \nmovl $0x0,-0x90(%rbp)\nmovl $0x0,-0x94(%rbp)\njmpq 13a1 \nmov -0x98(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nmov -0xb0(%rbp),%rax\nadd %rdx,%rax\nmov %rax,%rcx\nmov -0x94(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nmov -0x88(%rbp),%rax\nadd %rdx,%rax\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 1100 \ntest %eax,%eax\njne 139a \nmov -0x94(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nmov -0x88(%rbp),%rax\nadd %rdx,%rax\nmov 0x64(%rax),%esi\nmov -0x98(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nmov -0xb0(%rbp),%rax\nadd %rdx,%rax\nmov 0x64(%rax),%ecx\nmov -0x94(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nmov -0x88(%rbp),%rax\nadd %rdx,%rax\nlea (%rsi,%rcx,1),%edx\nmov %edx,0x64(%rax)\nmovl $0x1,-0x90(%rbp)\njmp 13b3 \naddl $0x1,-0x94(%rbp)\nmov -0x94(%rbp),%eax\ncmp -0x8c(%rbp),%eax\njl 129a \ncmpl $0x0,-0x90(%rbp)\njne 1484 \nmov -0x98(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nmov -0xb0(%rbp),%rax\nadd %rdx,%rax\nmov %rax,%rcx\nmov -0x8c(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nmov -0x88(%rbp),%rax\nadd %rdx,%rax\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 10c0 \nmov -0x98(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nmov -0xb0(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x8c(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nmov -0x88(%rbp),%rax\nadd %rax,%rdx\nmov 0x64(%rcx),%eax\nmov %eax,0x64(%rdx)\naddl $0x1,-0x8c(%rbp)\naddl $0x1,-0x98(%rbp)\nmov -0x98(%rbp),%eax\ncmp -0xb4(%rbp),%eax\njl 1281 \nmov -0x88(%rbp),%rax\nmov (%rax),%rcx\nmov 0x8(%rax),%rbx\nmov %rcx,-0x80(%rbp)\nmov %rbx,-0x78(%rbp)\nmov 0x10(%rax),%rcx\nmov 0x18(%rax),%rbx\nmov %rcx,-0x70(%rbp)\nmov %rbx,-0x68(%rbp)\nmov 0x20(%rax),%rcx\nmov 0x28(%rax),%rbx\nmov %rcx,-0x60(%rbp)\nmov %rbx,-0x58(%rbp)\nmov 0x30(%rax),%rcx\nmov 0x38(%rax),%rbx\nmov %rcx,-0x50(%rbp)\nmov %rbx,-0x48(%rbp)\nmov 0x40(%rax),%rcx\nmov 0x48(%rax),%rbx\nmov %rcx,-0x40(%rbp)\nmov %rbx,-0x38(%rbp)\nmov 0x50(%rax),%rcx\nmov 0x58(%rax),%rbx\nmov %rcx,-0x30(%rbp)\nmov %rbx,-0x28(%rbp)\nmov 0x60(%rax),%rax\nmov %rax,-0x20(%rbp)\nmovl $0x1,-0x98(%rbp)\njmpq 15ea \nmov -0x98(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nmov -0x88(%rbp),%rax\nadd %rdx,%rax\nmov 0x64(%rax),%edx\nmov -0x1c(%rbp),%eax\ncmp %eax,%edx\njle 15e3 \nmov -0x98(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nmov -0x88(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rcx\nmov 0x8(%rax),%rbx\nmov %rcx,-0x80(%rbp)\nmov %rbx,-0x78(%rbp)\nmov 0x10(%rax),%rcx\nmov 0x18(%rax),%rbx\nmov %rcx,-0x70(%rbp)\nmov %rbx,-0x68(%rbp)\nmov 0x20(%rax),%rcx\nmov 0x28(%rax),%rbx\nmov %rcx,-0x60(%rbp)\nmov %rbx,-0x58(%rbp)\nmov 0x30(%rax),%rcx\nmov 0x38(%rax),%rbx\nmov %rcx,-0x50(%rbp)\nmov %rbx,-0x48(%rbp)\nmov 0x40(%rax),%rcx\nmov 0x48(%rax),%rbx\nmov %rcx,-0x40(%rbp)\nmov %rbx,-0x38(%rbp)\nmov 0x50(%rax),%rcx\nmov 0x58(%rax),%rbx\nmov %rcx,-0x30(%rbp)\nmov %rbx,-0x28(%rbp)\nmov 0x60(%rax),%rax\nmov %rax,-0x20(%rbp)\naddl $0x1,-0x98(%rbp)\nmov -0x98(%rbp),%eax\ncmp -0x8c(%rbp),%eax\njl 151a \nmov -0x88(%rbp),%rax\nmov %rax,%rdi\ncallq 10b0 \nmov -0xa8(%rbp),%rax\nmov -0x80(%rbp),%rcx\nmov -0x78(%rbp),%rbx\nmov %rcx,(%rax)\nmov %rbx,0x8(%rax)\nmov -0x70(%rbp),%rcx\nmov -0x68(%rbp),%rbx\nmov %rcx,0x10(%rax)\nmov %rbx,0x18(%rax)\nmov -0x60(%rbp),%rcx\nmov -0x58(%rbp),%rbx\nmov %rcx,0x20(%rax)\nmov %rbx,0x28(%rax)\nmov -0x50(%rbp),%rcx\nmov -0x48(%rbp),%rbx\nmov %rcx,0x30(%rax)\nmov %rbx,0x38(%rax)\nmov -0x40(%rbp),%rcx\nmov -0x38(%rbp),%rbx\nmov %rcx,0x40(%rax)\nmov %rbx,0x48(%rax)\nmov -0x30(%rbp),%rcx\nmov -0x28(%rbp),%rbx\nmov %rcx,0x50(%rax)\nmov %rbx,0x58(%rax)\nmov -0x20(%rbp),%rdx\nmov %rdx,0x60(%rax)\nmov -0x18(%rbp),%rax\nxor %fs:0x28,%rax\nje 168d \ncallq 10e0 <__stack_chk_fail@plt>\nmov -0xa8(%rbp),%rax\nadd $0xb8,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 0B8h\nmov [rbp+var_A8], rdi\nmov [rbp+var_B0], rsi\nmov [rbp+var_B4], edx\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov eax, [rbp+var_B4]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov [rbp+var_8C], 0\nmov [rbp+var_98], 0\njmp loc_148B\nloc_1281:\nmov [rbp+var_90], 0\nmov [rbp+var_94], 0\njmp loc_13A1\nloc_129A:\nmov eax, [rbp+var_98]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_B0]\nadd rax, rdx\nmov rcx, rax\nmov eax, [rbp+var_94]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rsi, rcx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz loc_139A\nmov eax, [rbp+var_94]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov esi, [rax+64h]\nmov eax, [rbp+var_98]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_B0]\nadd rax, rdx\nmov ecx, [rax+64h]\nmov eax, [rbp+var_94]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+ptr]\nadd rax, rdx\nlea edx, [rsi+rcx]\nmov [rax+64h], edx\nmov [rbp+var_90], 1\njmp short loc_13B3\nloc_139A:\nadd [rbp+var_94], 1\nloc_13A1:\nmov eax, [rbp+var_94]\ncmp eax, [rbp+var_8C]\njl loc_129A\nloc_13B3:\ncmp [rbp+var_90], 0\njnz loc_1484\nmov eax, [rbp+var_98]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_B0]\nadd rax, rdx\nmov rcx, rax\nmov eax, [rbp+var_8C]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strcpy\nmov eax, [rbp+var_98]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_B0]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_8C]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov eax, [rcx+64h]\nmov [rdx+64h], eax\nadd [rbp+var_8C], 1\nloc_1484:\nadd [rbp+var_98], 1\nloc_148B:\nmov eax, [rbp+var_98]\ncmp eax, [rbp+var_B4]\njl loc_1281\nmov rax, [rbp+ptr]\nmov rcx, [rax]\nmov rbx, [rax+8]\nmov [rbp+var_80], rcx\nmov [rbp+var_78], rbx\nmov rcx, [rax+10h]\nmov rbx, [rax+18h]\nmov [rbp+var_70], rcx\nmov [rbp+var_68], rbx\nmov rcx, [rax+20h]\nmov rbx, [rax+28h]\nmov [rbp+var_60], rcx\nmov [rbp+var_58], rbx\nmov rcx, [rax+30h]\nmov rbx, [rax+38h]\nmov [rbp+var_50], rcx\nmov [rbp+var_48], rbx\nmov rcx, [rax+40h]\nmov rbx, [rax+48h]\nmov [rbp+var_40], rcx\nmov [rbp+var_38], rbx\nmov rcx, [rax+50h]\nmov rbx, [rax+58h]\nmov [rbp+var_30], rcx\nmov [rbp+var_28], rbx\nmov rax, [rax+60h]\nmov [rbp+var_20], rax\nmov [rbp+var_98], 1\njmp loc_15EA\nloc_151A:\nmov eax, [rbp+var_98]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax+64h]\nmov eax, dword ptr [rbp+var_20+4]\ncmp edx, eax\njle loc_15E3\nmov eax, [rbp+var_98]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rcx, [rax]\nmov rbx, [rax+8]\nmov [rbp+var_80], rcx\nmov [rbp+var_78], rbx\nmov rcx, [rax+10h]\nmov rbx, [rax+18h]\nmov [rbp+var_70], rcx\nmov [rbp+var_68], rbx\nmov rcx, [rax+20h]\nmov rbx, [rax+28h]\nmov [rbp+var_60], rcx\nmov [rbp+var_58], rbx\nmov rcx, [rax+30h]\nmov rbx, [rax+38h]\nmov [rbp+var_50], rcx\nmov [rbp+var_48], rbx\nmov rcx, [rax+40h]\nmov rbx, [rax+48h]\nmov [rbp+var_40], rcx\nmov [rbp+var_38], rbx\nmov rcx, [rax+50h]\nmov rbx, [rax+58h]\nmov [rbp+var_30], rcx\nmov [rbp+var_28], rbx\nmov rax, [rax+60h]\nmov [rbp+var_20], rax\nloc_15E3:\nadd [rbp+var_98], 1\nloc_15EA:\nmov eax, [rbp+var_98]\ncmp eax, [rbp+var_8C]\njl loc_151A\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_A8]\nmov rcx, [rbp+var_80]\nmov rbx, [rbp+var_78]\nmov [rax], rcx\nmov [rax+8], rbx\nmov rcx, [rbp+var_70]\nmov rbx, [rbp+var_68]\nmov [rax+10h], rcx\nmov [rax+18h], rbx\nmov rcx, [rbp+var_60]\nmov rbx, [rbp+var_58]\nmov [rax+20h], rcx\nmov [rax+28h], rbx\nmov rcx, [rbp+var_50]\nmov rbx, [rbp+var_48]\nmov [rax+30h], rcx\nmov [rax+38h], rbx\nmov rcx, [rbp+var_40]\nmov rbx, [rbp+var_38]\nmov [rax+40h], rcx\nmov [rax+48h], rbx\nmov rcx, [rbp+var_30]\nmov rbx, [rbp+var_28]\nmov [rax+50h], rcx\nmov [rax+58h], rbx\nmov rdx, [rbp+var_20]\nmov [rax+60h], rdx\nmov rax, [rbp+var_18]\nsub rax, fs:28h\njz short loc_168D\ncall ___stack_chk_fail\nloc_168D:\nmov rax, [rbp+var_A8]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(_QWORD *a1, __int64 a2, int a3)\n{\n __int64 v3; // rdx\n int i; // [rsp+28h] [rbp-98h]\n int k; // [rsp+28h] [rbp-98h]\n int j; // [rsp+2Ch] [rbp-94h]\n int v9; // [rsp+30h] [rbp-90h]\n int v10; // [rsp+34h] [rbp-8Ch]\n __int64 *ptr; // [rsp+38h] [rbp-88h]\n __int64 v12; // [rsp+40h] [rbp-80h]\n __int64 v13; // [rsp+48h] [rbp-78h]\n __int64 v14; // [rsp+50h] [rbp-70h]\n __int64 v15; // [rsp+58h] [rbp-68h]\n __int64 v16; // [rsp+60h] [rbp-60h]\n __int64 v17; // [rsp+68h] [rbp-58h]\n __int64 v18; // [rsp+70h] [rbp-50h]\n __int64 v19; // [rsp+78h] [rbp-48h]\n __int64 v20; // [rsp+80h] [rbp-40h]\n __int64 v21; // [rsp+88h] [rbp-38h]\n __int64 v22; // [rsp+90h] [rbp-30h]\n __int64 v23; // [rsp+98h] [rbp-28h]\n __int64 v24; // [rsp+A0h] [rbp-20h]\n\n ptr = (__int64 *)malloc(104LL * a3);\n v10 = 0;\n for ( i = 0; i < a3; ++i )\n {\n v9 = 0;\n for ( j = 0; j < v10; ++j )\n {\n if ( !strcmp((const char *)&ptr[13 * j], (const char *)(104LL * i + a2)) )\n {\n HIDWORD(ptr[13 * j + 12]) += *(_DWORD *)(104LL * i + a2 + 100);\n v9 = 1;\n break;\n }\n }\n if ( !v9 )\n {\n strcpy((char *)&ptr[13 * v10], (const char *)(104LL * i + a2));\n HIDWORD(ptr[13 * v10++ + 12]) = *(_DWORD *)(104LL * i + a2 + 100);\n }\n }\n v12 = *ptr;\n v13 = ptr[1];\n v14 = ptr[2];\n v15 = ptr[3];\n v16 = ptr[4];\n v17 = ptr[5];\n v18 = ptr[6];\n v19 = ptr[7];\n v20 = ptr[8];\n v21 = ptr[9];\n v22 = ptr[10];\n v23 = ptr[11];\n v24 = ptr[12];\n for ( k = 1; k < v10; ++k )\n {\n if ( SHIDWORD(ptr[13 * k + 12]) > SHIDWORD(v24) )\n {\n v3 = 13LL * k;\n v12 = ptr[v3];\n v13 = ptr[v3 + 1];\n v14 = ptr[v3 + 2];\n v15 = ptr[v3 + 3];\n v16 = ptr[v3 + 4];\n v17 = ptr[v3 + 5];\n v18 = ptr[v3 + 6];\n v19 = ptr[v3 + 7];\n v20 = ptr[v3 + 8];\n v21 = ptr[v3 + 9];\n v22 = ptr[v3 + 10];\n v23 = ptr[v3 + 11];\n v24 = ptr[v3 + 12];\n }\n }\n free(ptr);\n *a1 = v12;\n a1[1] = v13;\n a1[2] = v14;\n a1[3] = v15;\n a1[4] = v16;\n a1[5] = v17;\n a1[6] = v18;\n a1[7] = v19;\n a1[8] = v20;\n a1[9] = v21;\n a1[10] = v22;\n a1[11] = v23;\n a1[12] = v24;\n return a1;\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 0B8h\nmov [rbp+var_A8], rdi\nmov [rbp+var_B0], rsi\nmov [rbp+var_B4], edx\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov eax, [rbp+var_B4]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov [rbp+var_8C], 0\nmov [rbp+var_98], 0\njmp loc_148B\nloc_1281:\nmov [rbp+var_90], 0\nmov [rbp+var_94], 0\njmp loc_13A1\nloc_129A:\nmov eax, [rbp+var_98]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_B0]\nadd rax, rdx\nmov rcx, rax\nmov eax, [rbp+var_94]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rsi, rcx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz loc_139A\nmov eax, [rbp+var_94]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov esi, [rax+64h]\nmov eax, [rbp+var_98]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_B0]\nadd rax, rdx\nmov ecx, [rax+64h]\nmov eax, [rbp+var_94]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+ptr]\nadd rax, rdx\nlea edx, [rsi+rcx]\nmov [rax+64h], edx\nmov [rbp+var_90], 1\njmp short loc_13B3\nloc_139A:\nadd [rbp+var_94], 1\nloc_13A1:\nmov eax, [rbp+var_94]\ncmp eax, [rbp+var_8C]\njl loc_129A\nloc_13B3:\ncmp [rbp+var_90], 0\njnz loc_1484\nmov eax, [rbp+var_98]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_B0]\nadd rax, rdx\nmov rcx, rax\nmov eax, [rbp+var_8C]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strcpy\nmov eax, [rbp+var_98]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_B0]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_8C]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov eax, [rcx+64h]\nmov [rdx+64h], eax\nadd [rbp+var_8C], 1\nloc_1484:\nadd [rbp+var_98], 1\nloc_148B:\nmov eax, [rbp+var_98]\ncmp eax, [rbp+var_B4]\njl loc_1281\nmov rax, [rbp+ptr]\nmov rcx, [rax]\nmov rbx, [rax+8]\nmov [rbp+var_80], rcx\nmov [rbp+var_78], rbx\nmov rcx, [rax+10h]\nmov rbx, [rax+18h]\nmov [rbp+var_70], rcx\nmov [rbp+var_68], rbx\nmov rcx, [rax+20h]\nmov rbx, [rax+28h]\nmov [rbp+var_60], rcx\nmov [rbp+var_58], rbx\nmov rcx, [rax+30h]\nmov rbx, [rax+38h]\nmov [rbp+var_50], rcx\nmov [rbp+var_48], rbx\nmov rcx, [rax+40h]\nmov rbx, [rax+48h]\nmov [rbp+var_40], rcx\nmov [rbp+var_38], rbx\nmov rcx, [rax+50h]\nmov rbx, [rax+58h]\nmov [rbp+var_30], rcx\nmov [rbp+var_28], rbx\nmov rax, [rax+60h]\nmov [rbp+var_20], rax\nmov [rbp+var_98], 1\njmp loc_15EA\nloc_151A:\nmov eax, [rbp+var_98]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax+64h]\nmov eax, dword ptr [rbp+var_20+4]\ncmp edx, eax\njle loc_15E3\nmov eax, [rbp+var_98]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rcx, [rax]\nmov rbx, [rax+8]\nmov [rbp+var_80], rcx\nmov [rbp+var_78], rbx\nmov rcx, [rax+10h]\nmov rbx, [rax+18h]\nmov [rbp+var_70], rcx\nmov [rbp+var_68], rbx\nmov rcx, [rax+20h]\nmov rbx, [rax+28h]\nmov [rbp+var_60], rcx\nmov [rbp+var_58], rbx\nmov rcx, [rax+30h]\nmov rbx, [rax+38h]\nmov [rbp+var_50], rcx\nmov [rbp+var_48], rbx\nmov rcx, [rax+40h]\nmov rbx, [rax+48h]\nmov [rbp+var_40], rcx\nmov [rbp+var_38], rbx\nmov rcx, [rax+50h]\nmov rbx, [rax+58h]\nmov [rbp+var_30], rcx\nmov [rbp+var_28], rbx\nmov rax, [rax+60h]\nmov [rbp+var_20], rax\nloc_15E3:\nadd [rbp+var_98], 1\nloc_15EA:\nmov eax, [rbp+var_98]\ncmp eax, [rbp+var_8C]\njl loc_151A\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_A8]\nmov rcx, [rbp+var_80]\nmov rbx, [rbp+var_78]\nmov [rax], rcx\nmov [rax+8], rbx\nmov rcx, [rbp+var_70]\nmov rbx, [rbp+var_68]\nmov [rax+10h], rcx\nmov [rax+18h], rbx\nmov rcx, [rbp+var_60]\nmov rbx, [rbp+var_58]\nmov [rax+20h], rcx\nmov [rax+28h], rbx\nmov rcx, [rbp+var_50]\nmov rbx, [rbp+var_48]\nmov [rax+30h], rcx\nmov [rax+38h], rbx\nmov rcx, [rbp+var_40]\nmov rbx, [rbp+var_38]\nmov [rax+40h], rcx\nmov [rax+48h], rbx\nmov rcx, [rbp+var_30]\nmov rbx, [rbp+var_28]\nmov [rax+50h], rcx\nmov [rax+58h], rbx\nmov rdx, [rbp+var_20]\nmov [rax+60h], rdx\nmov rax, [rbp+var_18]\nsub rax, fs:28h\njz short loc_168D\ncall ___stack_chk_fail\nloc_168D:\nmov rax, [rbp+var_A8]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1209(_QWORD *a1, __int64 a2, int a3)\n{\n __int64 v3; // rdx\n int i; // [rsp+28h] [rbp-98h]\n int k; // [rsp+28h] [rbp-98h]\n int j; // [rsp+2Ch] [rbp-94h]\n int v9; // [rsp+30h] [rbp-90h]\n int v10; // [rsp+34h] [rbp-8Ch]\n __int64 *ptr; // [rsp+38h] [rbp-88h]\n __int64 v12; // [rsp+40h] [rbp-80h]\n __int64 v13; // [rsp+48h] [rbp-78h]\n __int64 v14; // [rsp+50h] [rbp-70h]\n __int64 v15; // [rsp+58h] [rbp-68h]\n __int64 v16; // [rsp+60h] [rbp-60h]\n __int64 v17; // [rsp+68h] [rbp-58h]\n __int64 v18; // [rsp+70h] [rbp-50h]\n __int64 v19; // [rsp+78h] [rbp-48h]\n __int64 v20; // [rsp+80h] [rbp-40h]\n __int64 v21; // [rsp+88h] [rbp-38h]\n __int64 v22; // [rsp+90h] [rbp-30h]\n __int64 v23; // [rsp+98h] [rbp-28h]\n __int64 v24; // [rsp+A0h] [rbp-20h]\n\n ptr = (__int64 *)malloc(104LL * a3);\n v10 = 0;\n for ( i = 0; i < a3; ++i )\n {\n v9 = 0;\n for ( j = 0; j < v10; ++j )\n {\n if ( !strcmp((const char *)&ptr[13 * j], (const char *)(104LL * i + a2)) )\n {\n HIDWORD(ptr[13 * j + 12]) += *(_DWORD *)(104LL * i + a2 + 100);\n v9 = 1;\n break;\n }\n }\n if ( !v9 )\n {\n strcpy((char *)&ptr[13 * v10], (const char *)(104LL * i + a2));\n HIDWORD(ptr[13 * v10++ + 12]) = *(_DWORD *)(104LL * i + a2 + 100);\n }\n }\n v12 = *ptr;\n v13 = ptr[1];\n v14 = ptr[2];\n v15 = ptr[3];\n v16 = ptr[4];\n v17 = ptr[5];\n v18 = ptr[6];\n v19 = ptr[7];\n v20 = ptr[8];\n v21 = ptr[9];\n v22 = ptr[10];\n v23 = ptr[11];\n v24 = ptr[12];\n for ( k = 1; k < v10; ++k )\n {\n if ( SHIDWORD(ptr[13 * k + 12]) > SHIDWORD(v24) )\n {\n v3 = 13LL * k;\n v12 = ptr[v3];\n v13 = ptr[v3 + 1];\n v14 = ptr[v3 + 2];\n v15 = ptr[v3 + 3];\n v16 = ptr[v3 + 4];\n v17 = ptr[v3 + 5];\n v18 = ptr[v3 + 6];\n v19 = ptr[v3 + 7];\n v20 = ptr[v3 + 8];\n v21 = ptr[v3 + 9];\n v22 = ptr[v3 + 10];\n v23 = ptr[v3 + 11];\n v24 = ptr[v3 + 12];\n }\n }\n free(ptr);\n *a1 = v12;\n a1[1] = v13;\n a1[2] = v14;\n a1[3] = v15;\n a1[4] = v16;\n a1[5] = v17;\n a1[6] = v18;\n a1[7] = v19;\n a1[8] = v20;\n a1[9] = v21;\n a1[10] = v22;\n a1[11] = v23;\n a1[12] = v24;\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1209(uint64_t *a1, long long a2, int a3) {\n long long v3;\n int i;\n int k;\n int j;\n int v9;\n int v10;\n long long *ptr;\n long long v12;\n long long v13;\n long long v14;\n long long v15;\n long long v16;\n long long v17;\n long long v18;\n long long v19;\n long long v20;\n long long v21;\n long long v22;\n long long v23;\n long long v24;\n ptr = (long long *)malloc(104LL * a3);\n v10 = 0;\n for (i = 0; i < a3; ++i) {\n v9 = 0;\n for (j = 0; j < v10; ++j) {\n if (!strcmp((const char *)&ptr[13 * j], (const char *)(104LL * i + a2))) {\n HIDWORD(ptr[13 * j + 12]) += *(uint32_t *)(104LL * i + a2 + 100);\n v9 = 1;\n break;\n }\n }\n if (!v9) {\n strcpy((char *)&ptr[13 * v10], (const char *)(104LL * i + a2));\n HIDWORD(ptr[13 * v10++ + 12]) = *(uint32_t *)(104LL * i + a2 + 100);\n }\n }\n v12 = *ptr;\n v13 = ptr[1];\n v14 = ptr[2];\n v15 = ptr[3];\n v16 = ptr[4];\n v17 = ptr[5];\n v18 = ptr[6];\n v19 = ptr[7];\n v20 = ptr[8];\n v21 = ptr[9];\n v22 = ptr[10];\n v23 = ptr[11];\n v24 = ptr[12];\n for (k = 1; k < v10; ++k) {\n if (SHIDWORD(ptr[13 * k + 12]) > SHIDWORD(v24)) {\n v3 = 13LL * k;\n v12 = ptr[v3];\n v13 = ptr[v3 + 1];\n v14 = ptr[v3 + 2];\n v15 = ptr[v3 + 3];\n v16 = ptr[v3 + 4];\n v17 = ptr[v3 + 5];\n v18 = ptr[v3 + 6];\n v19 = ptr[v3 + 7];\n v20 = ptr[v3 + 8];\n v21 = ptr[v3 + 9];\n v22 = ptr[v3 + 10];\n v23 = ptr[v3 + 11];\n v24 = ptr[v3 + 12];\n }\n }\n free(ptr);\n *a1 = v12;\n a1[1] = v13;\n a1[2] = v14;\n a1[3] = v15;\n a1[4] = v16;\n a1[5] = v17;\n a1[6] = v18;\n a1[7] = v19;\n a1[8] = v20;\n a1[9] = v21;\n a1[10] = v22;\n a1[11] = v23;\n a1[12] = v24;\n return a1;\n}", + "ida_pseudo_norm": "uint64_t *func0(uint64_t *a1, long long a2, int a3) {\n long long v3;\n int i;\n int k;\n int j;\n int v9;\n int v10;\n long long *ptr;\n long long v12;\n long long v13;\n long long v14;\n long long v15;\n long long v16;\n long long v17;\n long long v18;\n long long v19;\n long long v20;\n long long v21;\n long long v22;\n long long v23;\n long long v24;\n ptr = (long long *)malloc(104LL * a3);\n v10 = 0;\n for (i = 0; i < a3; ++i) {\n v9 = 0;\n for (j = 0; j < v10; ++j) {\n if (!strcmp((const char *)&ptr[13 * j], (const char *)(104LL * i + a2))) {\n HIDWORD(ptr[13 * j + 12]) += *(uint32_t *)(104LL * i + a2 + 100);\n v9 = 1;\n break;\n }\n }\n if (!v9) {\n strcpy((char *)&ptr[13 * v10], (const char *)(104LL * i + a2));\n HIDWORD(ptr[13 * v10++ + 12]) = *(uint32_t *)(104LL * i + a2 + 100);\n }\n }\n v12 = *ptr;\n v13 = ptr[1];\n v14 = ptr[2];\n v15 = ptr[3];\n v16 = ptr[4];\n v17 = ptr[5];\n v18 = ptr[6];\n v19 = ptr[7];\n v20 = ptr[8];\n v21 = ptr[9];\n v22 = ptr[10];\n v23 = ptr[11];\n v24 = ptr[12];\n for (k = 1; k < v10; ++k) {\n if (SHIDWORD(ptr[13 * k + 12]) > SHIDWORD(v24)) {\n v3 = 13LL * k;\n v12 = ptr[v3];\n v13 = ptr[v3 + 1];\n v14 = ptr[v3 + 2];\n v15 = ptr[v3 + 3];\n v16 = ptr[v3 + 4];\n v17 = ptr[v3 + 5];\n v18 = ptr[v3 + 6];\n v19 = ptr[v3 + 7];\n v20 = ptr[v3 + 8];\n v21 = ptr[v3 + 9];\n v22 = ptr[v3 + 10];\n v23 = ptr[v3 + 11];\n v24 = ptr[v3 + 12];\n }\n }\n free(ptr);\n *a1 = v12;\n a1[1] = v13;\n a1[2] = v14;\n a1[3] = v15;\n a1[4] = v16;\n a1[5] = v17;\n a1[6] = v18;\n a1[7] = v19;\n a1[8] = v20;\n a1[9] = v21;\n a1[10] = v22;\n a1[11] = v23;\n a1[12] = v24;\n return a1;\n}" + }, + { + "index": 299, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char name[100];\n\n int marks;\n\n} student_data;\n\n\n\ntypedef struct {\n\n char name[100];\n\n int total_marks;\n\n} aggregated_data;\n\n\n\n", + "func": "aggregated_data func0(student_data stdata[], int size) {\n int i, j, found;\n aggregated_data *temp = malloc(size * sizeof(aggregated_data));\n int temp_count = 0;\n for (i = 0; i < size; i++) {\n found = 0;\n for (j = 0; j < temp_count; j++) {\n if (strcmp(temp[j].name, stdata[i].name) == 0) {\n temp[j].total_marks += stdata[i].marks;\n found = 1;\n break;\n }\n }\n if (!found) {\n strcpy(temp[temp_count].name, stdata[i].name);\n temp[temp_count].total_marks = stdata[i].marks;\n temp_count++;\n }\n }\n aggregated_data max = temp[0];\n for (i = 1; i < temp_count; i++) {\n if (temp[i].total_marks > max.total_marks) {\n max = temp[i];\n }\n }\n free(temp);\n return max;\n}", + "test": "int main() {\n\n student_data test1[5] = {{\"Juan Whelan\", 90}, {\"Sabah Colley\", 88}, {\"Peter Nichols\", 7}, {\"Juan Whelan\", 122}, {\"Sabah Colley\", 84}};\n\n aggregated_data result1 = func0(test1, 5);\n\n assert(strcmp(result1.name, \"Juan Whelan\") == 0 && result1.total_marks == 212);\n\n \n\n student_data test2[5] = {{\"Juan Whelan\", 50}, {\"Sabah Colley\", 48}, {\"Peter Nichols\", 37}, {\"Juan Whelan\", 22}, {\"Sabah Colley\", 14}};\n\n aggregated_data result2 = func0(test2, 5);\n\n assert(strcmp(result2.name, \"Juan Whelan\") == 0 && result2.total_marks == 72);\n\n\n\n student_data test3[5] = {{\"Juan Whelan\", 10}, {\"Sabah Colley\", 20}, {\"Peter Nichols\", 30}, {\"Juan Whelan\", 40}, {\"Sabah Colley\", 50}};\n\n aggregated_data result3 = func0(test3, 5);\n\n assert(strcmp(result3.name, \"Sabah Colley\") == 0 && result3.total_marks == 70);\n\n \n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x98,%rsp\nmov %rdi,0x18(%rsp)\nmov %rsi,%rbp\nmov %edx,%ebx\nmov %fs:0x28,%rax\nmov %rax,0x88(%rsp)\nxor %eax,%eax\nmovslq %edx,%rax\nlea (%rax,%rax,2),%rdx\nlea (%rax,%rdx,4),%rdi\nshl $0x3,%rdi\ncallq 1100 \nmov %rax,%r15\ntest %ebx,%ebx\njle 13d6 \nmov %rbp,%r13\nlea -0x1(%rbx),%eax\nlea (%rax,%rax,2),%rdx\nlea (%rax,%rdx,4),%rax\nlea 0x68(%rbp,%rax,8),%rax\nmov %rax,0x8(%rsp)\nmov $0x0,%r14d\nlea 0x68(%r15),%rax\nmov %rax,0x10(%rsp)\njmp 12c4 \nmov 0x64(%rbp),%eax\nmov (%rsp),%rcx\nadd %eax,0x64(%rcx)\njmp 12b9 \nmovslq %r14d,%rax\nlea (%rax,%rax,2),%rdx\nlea (%rax,%rdx,4),%rax\nlea (%r15,%rax,8),%rbx\nmov $0x64,%edx\nmov %r13,%rsi\nmov %rbx,%rdi\ncallq 1110 <__strcpy_chk@plt>\nmov 0x64(%r13),%eax\nmov %eax,0x64(%rbx)\nadd $0x1,%r14d\nadd $0x68,%r13\ncmp 0x8(%rsp),%r13\nje 1302 \ntest %r14d,%r14d\njle 128f \nmov %r13,%rbp\nmov %r15,%rbx\nlea -0x1(%r14),%eax\nlea (%rax,%rax,2),%rdx\nlea (%rax,%rdx,4),%rax\nmov 0x10(%rsp),%rcx\nlea (%rcx,%rax,8),%r12\nmov %rbx,(%rsp)\nmov %rbp,%rsi\nmov %rbx,%rdi\ncallq 10f0 \ntest %eax,%eax\nje 1283 \nadd $0x68,%rbx\ncmp %r12,%rbx\njne 12e4 \njmp 128f \nmovdqu (%r15),%xmm6\nmovaps %xmm6,0x20(%rsp)\nmovdqu 0x10(%r15),%xmm7\nmovaps %xmm7,0x30(%rsp)\nmovdqu 0x20(%r15),%xmm6\nmovaps %xmm6,0x40(%rsp)\nmovdqu 0x30(%r15),%xmm7\nmovaps %xmm7,0x50(%rsp)\nmovdqu 0x40(%r15),%xmm0\nmovaps %xmm0,0x60(%rsp)\nmovdqu 0x50(%r15),%xmm1\nmovaps %xmm1,0x70(%rsp)\nmov 0x60(%r15),%rax\nmov %rax,0x80(%rsp)\nmov 0x64(%r15),%ebx\ncmp $0x1,%r14d\njle 1421 \nlea 0x68(%r15),%rax\nlea -0x2(%r14),%edx\nlea (%rdx,%rdx,2),%rcx\nlea (%rdx,%rcx,4),%rdx\nlea 0xd0(%r15,%rdx,8),%rcx\njmp 1384 \nadd $0x68,%rax\ncmp %rcx,%rax\nje 1421 \nmov 0x64(%rax),%edx\ncmp %ebx,%edx\njle 1377 \nmovdqu (%rax),%xmm0\nmovaps %xmm0,0x20(%rsp)\nmovdqu 0x10(%rax),%xmm1\nmovaps %xmm1,0x30(%rsp)\nmovdqu 0x20(%rax),%xmm2\nmovaps %xmm2,0x40(%rsp)\nmovdqu 0x30(%rax),%xmm3\nmovaps %xmm3,0x50(%rsp)\nmovdqu 0x40(%rax),%xmm4\nmovaps %xmm4,0x60(%rsp)\nmovdqu 0x50(%rax),%xmm5\nmovaps %xmm5,0x70(%rsp)\nmov 0x60(%rax),%rsi\nmov %rsi,0x80(%rsp)\nmov %edx,%ebx\njmp 1377 \nmovdqu (%rax),%xmm2\nmovaps %xmm2,0x20(%rsp)\nmovdqu 0x10(%rax),%xmm3\nmovaps %xmm3,0x30(%rsp)\nmovdqu 0x20(%rax),%xmm4\nmovaps %xmm4,0x40(%rsp)\nmovdqu 0x30(%rax),%xmm5\nmovaps %xmm5,0x50(%rsp)\nmovdqu 0x40(%rax),%xmm2\nmovaps %xmm2,0x60(%rsp)\nmovdqu 0x50(%rax),%xmm3\nmovaps %xmm3,0x70(%rsp)\nmov 0x60(%rax),%rax\nmov %rax,0x80(%rsp)\nmov 0x64(%r15),%ebx\nmov %r15,%rdi\ncallq 10b0 \nmov %ebx,0x84(%rsp)\nmov 0x18(%rsp),%rcx\nmovdqa 0x20(%rsp),%xmm6\nmovups %xmm6,(%rcx)\nmovdqa 0x30(%rsp),%xmm7\nmovups %xmm7,0x10(%rcx)\nmovdqa 0x40(%rsp),%xmm6\nmovups %xmm6,0x20(%rcx)\nmovdqa 0x50(%rsp),%xmm7\nmovups %xmm7,0x30(%rcx)\nmovdqa 0x60(%rsp),%xmm6\nmovups %xmm6,0x40(%rcx)\nmovdqa 0x70(%rsp),%xmm7\nmovups %xmm7,0x50(%rcx)\nmov 0x80(%rsp),%rax\nmov %rax,0x60(%rcx)\nmov 0x88(%rsp),%rax\nxor %fs:0x28,%rax\njne 14a6 \nmov 0x18(%rsp),%rax\nadd $0x98,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\ncallq 10d0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 98h\nmov [rsp+0C8h+var_B0], rdi\nmov rbp, rsi\nmov ebx, edx\nmov rax, fs:28h\nmov [rsp+0C8h+var_40], rax\nxor eax, eax\nmovsxd rax, edx\nlea rdx, [rax+rax*2]\nlea rax, [rax+rdx*4]\nlea r15, ds:0[rax*8]\nmov [rsp+0C8h+var_B8], r15\nmov rdi, r15; size\ncall _malloc\nmov r14, rax\ntest ebx, ebx\njle loc_13E7\nmov r13, rbp\nlea rax, [rbp+r15+0]\nmov [rsp+0C8h+var_C0], rax\nmov r15d, 0\njmp short loc_12D8\nloc_127B:\nmov eax, [rbp+64h]\nadd [rbx+64h], eax\njmp short loc_12CA\nloc_1283:\nmovsxd rax, r15d\nlea rdx, [rax+rax*2]\nlea rax, [rax+rdx*4]\nshl rax, 3\nlea rbx, [r14+rax]\nmov rcx, [rsp+0C8h+var_B8]\ncmp rcx, rax\nmov rdx, rcx\ncmovb rdx, rax\nsub rdx, rax\nmov eax, 64h ; 'd'\ncmp rdx, rax\ncmova rdx, rax\nmov rsi, r13\nmov rdi, rbx\ncall ___strcpy_chk\nmov eax, [r13+64h]\nmov [rbx+64h], eax\nadd r15d, 1\nloc_12CA:\nadd r13, 68h ; 'h'\nmov rax, [rsp+0C8h+var_C0]\ncmp r13, rax\njz short loc_1313\nloc_12D8:\ntest r15d, r15d\njle short loc_1283\nmov rbp, r13\nmov rbx, r14\nmovsxd rax, r15d\nlea rdx, [rax+rax*2]\nlea rax, [rax+rdx*4]\nlea r12, [r14+rax*8]\nloc_12F2:\nmov rsi, rbp; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz loc_127B\nadd rbx, 68h ; 'h'\ncmp rbx, r12\njnz short loc_12F2\njmp loc_1283\nloc_1313:\nmovdqu xmm6, xmmword ptr [r14]\nmovaps [rsp+0C8h+var_A8], xmm6\nmovdqu xmm7, xmmword ptr [r14+10h]\nmovaps [rsp+0C8h+var_98], xmm7\nmovdqu xmm6, xmmword ptr [r14+20h]\nmovaps [rsp+0C8h+var_88], xmm6\nmovdqu xmm7, xmmword ptr [r14+30h]\nmovaps [rsp+0C8h+var_78], xmm7\nmovdqu xmm0, xmmword ptr [r14+40h]\nmovaps [rsp+0C8h+var_68], xmm0\nmovdqu xmm1, xmmword ptr [r14+50h]\nmovaps [rsp+0C8h+var_58], xmm1\nmov rax, [r14+60h]\nmov [rsp+0C8h+var_48], rax\nmov ebx, [r14+64h]\ncmp r15d, 1\njle loc_1432\nlea rax, [r14+68h]\nlea edx, [r15-2]\nlea rcx, [rdx+rdx*2]\nlea rdx, [rdx+rcx*4]\nlea rcx, [r14+rdx*8+0D0h]\njmp short loc_1395\nloc_1388:\nadd rax, 68h ; 'h'\ncmp rax, rcx\njz loc_1432\nloc_1395:\nmov edx, [rax+64h]\ncmp edx, ebx\njle short loc_1388\nmovdqu xmm0, xmmword ptr [rax]\nmovaps [rsp+0C8h+var_A8], xmm0\nmovdqu xmm1, xmmword ptr [rax+10h]\nmovaps [rsp+0C8h+var_98], xmm1\nmovdqu xmm2, xmmword ptr [rax+20h]\nmovaps [rsp+0C8h+var_88], xmm2\nmovdqu xmm3, xmmword ptr [rax+30h]\nmovaps [rsp+0C8h+var_78], xmm3\nmovdqu xmm4, xmmword ptr [rax+40h]\nmovaps [rsp+0C8h+var_68], xmm4\nmovdqu xmm5, xmmword ptr [rax+50h]\nmovaps [rsp+0C8h+var_58], xmm5\nmov rsi, [rax+60h]\nmov [rsp+0C8h+var_48], rsi\nmov ebx, edx\njmp short loc_1388\nloc_13E7:\nmovdqu xmm2, xmmword ptr [rax]\nmovaps [rsp+0C8h+var_A8], xmm2\nmovdqu xmm3, xmmword ptr [rax+10h]\nmovaps [rsp+0C8h+var_98], xmm3\nmovdqu xmm4, xmmword ptr [rax+20h]\nmovaps [rsp+0C8h+var_88], xmm4\nmovdqu xmm5, xmmword ptr [rax+30h]\nmovaps [rsp+0C8h+var_78], xmm5\nmovdqu xmm2, xmmword ptr [rax+40h]\nmovaps [rsp+0C8h+var_68], xmm2\nmovdqu xmm3, xmmword ptr [rax+50h]\nmovaps [rsp+0C8h+var_58], xmm3\nmov rax, [rax+60h]\nmov [rsp+0C8h+var_48], rax\nmov ebx, [r14+64h]\nloc_1432:\nmov rdi, r14; ptr\ncall _free\nmov dword ptr [rsp+0C8h+var_48+4], ebx\nmov rcx, [rsp+0C8h+var_B0]\nmovdqa xmm6, [rsp+0C8h+var_A8]\nmovups xmmword ptr [rcx], xmm6\nmovdqa xmm7, [rsp+0C8h+var_98]\nmovups xmmword ptr [rcx+10h], xmm7\nmovdqa xmm6, [rsp+0C8h+var_88]\nmovups xmmword ptr [rcx+20h], xmm6\nmovdqa xmm7, [rsp+0C8h+var_78]\nmovups xmmword ptr [rcx+30h], xmm7\nmovdqa xmm6, [rsp+0C8h+var_68]\nmovups xmmword ptr [rcx+40h], xmm6\nmovdqa xmm7, [rsp+0C8h+var_58]\nmovups xmmword ptr [rcx+50h], xmm7\nmov rax, [rsp+0C8h+var_48]\nmov [rcx+60h], rax\nmov rax, [rsp+0C8h+var_40]\nsub rax, fs:28h\njnz short loc_14B7\nmov rax, [rsp+0C8h+var_B0]\nadd rsp, 98h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14B7:\ncall ___stack_chk_fail", + "ida_pseudo": "__m128i *__fastcall func0(__m128i *a1, __int64 a2, int a3)\n{\n size_t v4; // r15\n const __m128i *v5; // rax\n __m128i *v6; // r14\n __int64 v7; // r13\n int v8; // r15d\n unsigned __int64 v9; // rax\n __int8 *v10; // rbx\n __int64 v11; // rdx\n unsigned __int64 v12; // rdx\n __m128i *v13; // rbx\n __int32 v14; // ebx\n const __m128i *v15; // rax\n __int32 v16; // edx\n size_t v18; // [rsp+8h] [rbp-C0h]\n size_t v19; // [rsp+10h] [rbp-B8h]\n __m128i v20; // [rsp+20h] [rbp-A8h] BYREF\n __m128i v21; // [rsp+30h] [rbp-98h] BYREF\n __m128i v22; // [rsp+40h] [rbp-88h] BYREF\n __m128i v23; // [rsp+50h] [rbp-78h] BYREF\n __m128i v24; // [rsp+60h] [rbp-68h] BYREF\n __m128i v25; // [rsp+70h] [rbp-58h] BYREF\n __int64 v26; // [rsp+80h] [rbp-48h]\n unsigned __int64 v27; // [rsp+88h] [rbp-40h]\n\n v27 = __readfsqword(0x28u);\n v4 = 104LL * a3;\n v19 = v4;\n v5 = (const __m128i *)malloc(v4);\n v6 = (__m128i *)v5;\n if ( a3 <= 0 )\n {\n v20 = _mm_loadu_si128(v5);\n v21 = _mm_loadu_si128(v5 + 1);\n v22 = _mm_loadu_si128(v5 + 2);\n v23 = _mm_loadu_si128(v5 + 3);\n v24 = _mm_loadu_si128(v5 + 4);\n v25 = _mm_loadu_si128(v5 + 5);\n v26 = v5[6].m128i_i64[0];\n v14 = v5[6].m128i_i32[1];\n }\n else\n {\n v7 = a2;\n v18 = a2 + v4;\n v8 = 0;\n do\n {\n if ( v8 <= 0 )\n {\nLABEL_4:\n v9 = 104LL * v8;\n v10 = &v6->m128i_i8[v9];\n v11 = v19;\n if ( v19 < v9 )\n v11 = 104LL * v8;\n v12 = v11 - v9;\n if ( v12 > 0x64 )\n v12 = 100LL;\n __strcpy_chk(v10, v7, v12);\n *((_DWORD *)v10 + 25) = *(_DWORD *)(v7 + 100);\n ++v8;\n }\n else\n {\n v13 = v6;\n while ( strcmp(v13->m128i_i8, (const char *)v7) )\n {\n v13 = (__m128i *)((char *)v13 + 104);\n if ( v13 == (__m128i *)((char *)v6 + 104 * v8) )\n goto LABEL_4;\n }\n v13[6].m128i_i32[1] += *(_DWORD *)(v7 + 100);\n }\n v7 += 104LL;\n }\n while ( v7 != v18 );\n v20 = _mm_loadu_si128(v6);\n v21 = _mm_loadu_si128(v6 + 1);\n v22 = _mm_loadu_si128(v6 + 2);\n v23 = _mm_loadu_si128(v6 + 3);\n v24 = _mm_loadu_si128(v6 + 4);\n v25 = _mm_loadu_si128(v6 + 5);\n v26 = v6[6].m128i_i64[0];\n v14 = v6[6].m128i_i32[1];\n if ( v8 > 1 )\n {\n v15 = (__m128i *)((char *)v6 + 104);\n do\n {\n v16 = v15[6].m128i_i32[1];\n if ( v16 > v14 )\n {\n v20 = _mm_loadu_si128(v15);\n v21 = _mm_loadu_si128(v15 + 1);\n v22 = _mm_loadu_si128(v15 + 2);\n v23 = _mm_loadu_si128(v15 + 3);\n v24 = _mm_loadu_si128(v15 + 4);\n v25 = _mm_loadu_si128(v15 + 5);\n v26 = v15[6].m128i_i64[0];\n v14 = v16;\n }\n v15 = (const __m128i *)((char *)v15 + 104);\n }\n while ( v15 != (__m128i *)((char *)&v6[13] + 104 * (unsigned int)(v8 - 2)) );\n }\n }\n free(v6);\n HIDWORD(v26) = v14;\n *a1 = _mm_load_si128(&v20);\n a1[1] = _mm_load_si128(&v21);\n a1[2] = _mm_load_si128(&v22);\n a1[3] = _mm_load_si128(&v23);\n a1[4] = _mm_load_si128(&v24);\n a1[5] = _mm_load_si128(&v25);\n a1[6].m128i_i64[0] = v26;\n return a1;\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 98h\nmov [rsp+0C8h+var_B0], rdi\nmov rbp, rsi\nmov ebx, edx\nmov rax, fs:28h\nmov [rsp+0C8h+var_40], rax\nxor eax, eax\nmovsxd rax, edx\nlea rdx, [rax+rax*2]\nlea rax, [rax+rdx*4]\nlea r15, ds:0[rax*8]\nmov [rsp+0C8h+var_B8], r15\nmov rdi, r15; size\ncall _malloc\nmov r14, rax\ntest ebx, ebx\njle loc_13E7\nmov r13, rbp\nlea rax, [rbp+r15+0]\nmov [rsp+0C8h+var_C0], rax\nmov r15d, 0\njmp short loc_12D8\nloc_127B:\nmov eax, [rbp+64h]\nadd [rbx+64h], eax\njmp short loc_12CA\nloc_1283:\nmovsxd rax, r15d\nlea rdx, [rax+rax*2]\nlea rax, [rax+rdx*4]\nshl rax, 3\nlea rbx, [r14+rax]\nmov rcx, [rsp+0C8h+var_B8]\ncmp rcx, rax\nmov rdx, rcx\ncmovb rdx, rax\nsub rdx, rax\nmov eax, 64h ; 'd'\ncmp rdx, rax\ncmova rdx, rax\nmov rsi, r13\nmov rdi, rbx\ncall ___strcpy_chk\nmov eax, [r13+64h]\nmov [rbx+64h], eax\nadd r15d, 1\nloc_12CA:\nadd r13, 68h ; 'h'\nmov rax, [rsp+0C8h+var_C0]\ncmp r13, rax\njz short loc_1313\nloc_12D8:\ntest r15d, r15d\njle short loc_1283\nmov rbp, r13\nmov rbx, r14\nmovsxd rax, r15d\nlea rdx, [rax+rax*2]\nlea rax, [rax+rdx*4]\nlea r12, [r14+rax*8]\nloc_12F2:\nmov rsi, rbp; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz loc_127B\nadd rbx, 68h ; 'h'\ncmp rbx, r12\njnz short loc_12F2\njmp loc_1283\nloc_1313:\nmovdqu xmm6, xmmword ptr [r14]\nmovaps [rsp+0C8h+var_A8], xmm6\nmovdqu xmm7, xmmword ptr [r14+10h]\nmovaps [rsp+0C8h+var_98], xmm7\nmovdqu xmm6, xmmword ptr [r14+20h]\nmovaps [rsp+0C8h+var_88], xmm6\nmovdqu xmm7, xmmword ptr [r14+30h]\nmovaps [rsp+0C8h+var_78], xmm7\nmovdqu xmm0, xmmword ptr [r14+40h]\nmovaps [rsp+0C8h+var_68], xmm0\nmovdqu xmm1, xmmword ptr [r14+50h]\nmovaps [rsp+0C8h+var_58], xmm1\nmov rax, [r14+60h]\nmov [rsp+0C8h+var_48], rax\nmov ebx, [r14+64h]\ncmp r15d, 1\njle loc_1432\nlea rax, [r14+68h]\nlea edx, [r15-2]\nlea rcx, [rdx+rdx*2]\nlea rdx, [rdx+rcx*4]\nlea rcx, [r14+rdx*8+0D0h]\njmp short loc_1395\nloc_1388:\nadd rax, 68h ; 'h'\ncmp rax, rcx\njz loc_1432\nloc_1395:\nmov edx, [rax+64h]\ncmp edx, ebx\njle short loc_1388\nmovdqu xmm0, xmmword ptr [rax]\nmovaps [rsp+0C8h+var_A8], xmm0\nmovdqu xmm1, xmmword ptr [rax+10h]\nmovaps [rsp+0C8h+var_98], xmm1\nmovdqu xmm2, xmmword ptr [rax+20h]\nmovaps [rsp+0C8h+var_88], xmm2\nmovdqu xmm3, xmmword ptr [rax+30h]\nmovaps [rsp+0C8h+var_78], xmm3\nmovdqu xmm4, xmmword ptr [rax+40h]\nmovaps [rsp+0C8h+var_68], xmm4\nmovdqu xmm5, xmmword ptr [rax+50h]\nmovaps [rsp+0C8h+var_58], xmm5\nmov rsi, [rax+60h]\nmov [rsp+0C8h+var_48], rsi\nmov ebx, edx\njmp short loc_1388\nloc_13E7:\nmovdqu xmm2, xmmword ptr [rax]\nmovaps [rsp+0C8h+var_A8], xmm2\nmovdqu xmm3, xmmword ptr [rax+10h]\nmovaps [rsp+0C8h+var_98], xmm3\nmovdqu xmm4, xmmword ptr [rax+20h]\nmovaps [rsp+0C8h+var_88], xmm4\nmovdqu xmm5, xmmword ptr [rax+30h]\nmovaps [rsp+0C8h+var_78], xmm5\nmovdqu xmm2, xmmword ptr [rax+40h]\nmovaps [rsp+0C8h+var_68], xmm2\nmovdqu xmm3, xmmword ptr [rax+50h]\nmovaps [rsp+0C8h+var_58], xmm3\nmov rax, [rax+60h]\nmov [rsp+0C8h+var_48], rax\nmov ebx, [r14+64h]\nloc_1432:\nmov rdi, r14; ptr\ncall _free\nmov dword ptr [rsp+0C8h+var_48+4], ebx\nmov rcx, [rsp+0C8h+var_B0]\nmovdqa xmm6, [rsp+0C8h+var_A8]\nmovups xmmword ptr [rcx], xmm6\nmovdqa xmm7, [rsp+0C8h+var_98]\nmovups xmmword ptr [rcx+10h], xmm7\nmovdqa xmm6, [rsp+0C8h+var_88]\nmovups xmmword ptr [rcx+20h], xmm6\nmovdqa xmm7, [rsp+0C8h+var_78]\nmovups xmmword ptr [rcx+30h], xmm7\nmovdqa xmm6, [rsp+0C8h+var_68]\nmovups xmmword ptr [rcx+40h], xmm6\nmovdqa xmm7, [rsp+0C8h+var_58]\nmovups xmmword ptr [rcx+50h], xmm7\nmov rax, [rsp+0C8h+var_48]\nmov [rcx+60h], rax\nmov rax, [rsp+0C8h+var_40]\nsub rax, fs:28h\njnz short loc_14B7\nmov rax, [rsp+0C8h+var_B0]\nadd rsp, 98h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14B7:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__m128i *__fastcall sub_1209(__m128i *a1, __int64 a2, int a3)\n{\n size_t v4; // r15\n const __m128i *v5; // rax\n __m128i *v6; // r14\n __int64 v7; // r13\n int v8; // r15d\n unsigned __int64 v9; // rax\n __int8 *v10; // rbx\n __int64 v11; // rdx\n unsigned __int64 v12; // rdx\n __m128i *v13; // rbx\n __int32 v14; // ebx\n const __m128i *v15; // rax\n __int32 v16; // edx\n size_t v18; // [rsp+8h] [rbp-C0h]\n size_t v19; // [rsp+10h] [rbp-B8h]\n __m128i v20; // [rsp+20h] [rbp-A8h] BYREF\n __m128i v21; // [rsp+30h] [rbp-98h] BYREF\n __m128i v22; // [rsp+40h] [rbp-88h] BYREF\n __m128i v23; // [rsp+50h] [rbp-78h] BYREF\n __m128i v24; // [rsp+60h] [rbp-68h] BYREF\n __m128i v25; // [rsp+70h] [rbp-58h] BYREF\n __int64 v26; // [rsp+80h] [rbp-48h]\n unsigned __int64 v27; // [rsp+88h] [rbp-40h]\n\n v27 = __readfsqword(0x28u);\n v4 = 104LL * a3;\n v19 = v4;\n v5 = (const __m128i *)malloc(v4);\n v6 = (__m128i *)v5;\n if ( a3 <= 0 )\n {\n v20 = _mm_loadu_si128(v5);\n v21 = _mm_loadu_si128(v5 + 1);\n v22 = _mm_loadu_si128(v5 + 2);\n v23 = _mm_loadu_si128(v5 + 3);\n v24 = _mm_loadu_si128(v5 + 4);\n v25 = _mm_loadu_si128(v5 + 5);\n v26 = v5[6].m128i_i64[0];\n v14 = v5[6].m128i_i32[1];\n }\n else\n {\n v7 = a2;\n v18 = a2 + v4;\n v8 = 0;\n do\n {\n if ( v8 <= 0 )\n {\nLABEL_4:\n v9 = 104LL * v8;\n v10 = &v6->m128i_i8[v9];\n v11 = v19;\n if ( v19 < v9 )\n v11 = 104LL * v8;\n v12 = v11 - v9;\n if ( v12 > 0x64 )\n v12 = 100LL;\n __strcpy_chk(v10, v7, v12);\n *((_DWORD *)v10 + 25) = *(_DWORD *)(v7 + 100);\n ++v8;\n }\n else\n {\n v13 = v6;\n while ( strcmp(v13->m128i_i8, (const char *)v7) )\n {\n v13 = (__m128i *)((char *)v13 + 104);\n if ( v13 == (__m128i *)((char *)v6 + 104 * v8) )\n goto LABEL_4;\n }\n v13[6].m128i_i32[1] += *(_DWORD *)(v7 + 100);\n }\n v7 += 104LL;\n }\n while ( v7 != v18 );\n v20 = _mm_loadu_si128(v6);\n v21 = _mm_loadu_si128(v6 + 1);\n v22 = _mm_loadu_si128(v6 + 2);\n v23 = _mm_loadu_si128(v6 + 3);\n v24 = _mm_loadu_si128(v6 + 4);\n v25 = _mm_loadu_si128(v6 + 5);\n v26 = v6[6].m128i_i64[0];\n v14 = v6[6].m128i_i32[1];\n if ( v8 > 1 )\n {\n v15 = (__m128i *)((char *)v6 + 104);\n do\n {\n v16 = v15[6].m128i_i32[1];\n if ( v16 > v14 )\n {\n v20 = _mm_loadu_si128(v15);\n v21 = _mm_loadu_si128(v15 + 1);\n v22 = _mm_loadu_si128(v15 + 2);\n v23 = _mm_loadu_si128(v15 + 3);\n v24 = _mm_loadu_si128(v15 + 4);\n v25 = _mm_loadu_si128(v15 + 5);\n v26 = v15[6].m128i_i64[0];\n v14 = v16;\n }\n v15 = (const __m128i *)((char *)v15 + 104);\n }\n while ( v15 != (__m128i *)((char *)&v6[13] + 104 * (unsigned int)(v8 - 2)) );\n }\n }\n free(v6);\n HIDWORD(v26) = v14;\n *a1 = _mm_load_si128(&v20);\n a1[1] = _mm_load_si128(&v21);\n a1[2] = _mm_load_si128(&v22);\n a1[3] = _mm_load_si128(&v23);\n a1[4] = _mm_load_si128(&v24);\n a1[5] = _mm_load_si128(&v25);\n a1[6].m128i_i64[0] = v26;\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__m128i *sub_1209(__m128i *a1, long long a2, int a3) {\n unsigned int v4;\n const __m128i *v5;\n __m128i *v6;\n long long v7;\n int v8;\n unsigned long long v9;\n char *v10;\n long long v11;\n unsigned long long v12;\n __m128i *v13;\n int v14;\n const __m128i *v15;\n int v16;\n unsigned int v18;\n unsigned int v19;\n __m128i v20;\n __m128i v21;\n __m128i v22;\n __m128i v23;\n __m128i v24;\n __m128i v25;\n long long v26;\n unsigned long long v27;\n v27 = __readfsqword(40u);\n v4 = 104LL * a3;\n v19 = v4;\n v5 = (const __m128i *)malloc(v4);\n v6 = (__m128i *)v5;\n if (a3 <= 0) {\n v20 = _mm_loadu_si128(v5);\n v21 = _mm_loadu_si128(v5 + 1);\n v22 = _mm_loadu_si128(v5 + 2);\n v23 = _mm_loadu_si128(v5 + 3);\n v24 = _mm_loadu_si128(v5 + 4);\n v25 = _mm_loadu_si128(v5 + 5);\n v26 = v5[6].m128i_i64[0];\n v14 = v5[6].m128i_i32[1];\n } else {\n v7 = a2;\n v18 = a2 + v4;\n v8 = 0;\n do {\n if (v8 <= 0) {\n LABEL_4:\n v9 = 104LL * v8;\n v10 = &v6->m128i_i8[v9];\n v11 = v19;\n if (v19 < v9) v11 = 104LL * v8;\n v12 = v11 - v9;\n if (v12 > 100) v12 = 100LL;\n __strcpy_chk(v10, v7, v12);\n *((uint32_t *)v10 + 25) = *(uint32_t *)(v7 + 100);\n ++v8;\n } else {\n v13 = v6;\n while (strcmp(v13->m128i_i8, (const char *)v7)) {\n v13 = (__m128i *)((char *)v13 + 104);\n if (v13 == (__m128i *)((char *)v6 + 104 * v8)) goto LABEL_4;\n }\n v13[6].m128i_i32[1] += *(uint32_t *)(v7 + 100);\n }\n v7 += 104LL;\n } while (v7 != v18);\n v20 = _mm_loadu_si128(v6);\n v21 = _mm_loadu_si128(v6 + 1);\n v22 = _mm_loadu_si128(v6 + 2);\n v23 = _mm_loadu_si128(v6 + 3);\n v24 = _mm_loadu_si128(v6 + 4);\n v25 = _mm_loadu_si128(v6 + 5);\n v26 = v6[6].m128i_i64[0];\n v14 = v6[6].m128i_i32[1];\n if (v8 > 1) {\n v15 = (__m128i *)((char *)v6 + 104);\n do {\n v16 = v15[6].m128i_i32[1];\n if (v16 > v14) {\n v20 = _mm_loadu_si128(v15);\n v21 = _mm_loadu_si128(v15 + 1);\n v22 = _mm_loadu_si128(v15 + 2);\n v23 = _mm_loadu_si128(v15 + 3);\n v24 = _mm_loadu_si128(v15 + 4);\n v25 = _mm_loadu_si128(v15 + 5);\n v26 = v15[6].m128i_i64[0];\n v14 = v16;\n }\n v15 = (const __m128i *)((char *)v15 + 104);\n } while (v15 !=\n (__m128i *)((char *)&v6[13] + 104 * (unsigned int)(v8 - 2)));\n }\n }\n free(v6);\n HIDWORD(v26) = v14;\n *a1 = _mm_load_si128(&v20);\n a1[1] = _mm_load_si128(&v21);\n a1[2] = _mm_load_si128(&v22);\n a1[3] = _mm_load_si128(&v23);\n a1[4] = _mm_load_si128(&v24);\n a1[5] = _mm_load_si128(&v25);\n a1[6].m128i_i64[0] = v26;\n return a1;\n}", + "ida_pseudo_norm": "__m128i *func0(__m128i *a1, long long a2, int a3) {\n unsigned int v4;\n const __m128i *v5;\n __m128i *v6;\n long long v7;\n int v8;\n unsigned long long v9;\n char *v10;\n long long v11;\n unsigned long long v12;\n __m128i *v13;\n int v14;\n const __m128i *v15;\n int v16;\n unsigned int v18;\n unsigned int v19;\n __m128i v20;\n __m128i v21;\n __m128i v22;\n __m128i v23;\n __m128i v24;\n __m128i v25;\n long long v26;\n unsigned long long v27;\n v27 = __readfsqword(40u);\n v4 = 104LL * a3;\n v19 = v4;\n v5 = (const __m128i *)malloc(v4);\n v6 = (__m128i *)v5;\n if (a3 <= 0) {\n v20 = _mm_loadu_si128(v5);\n v21 = _mm_loadu_si128(v5 + 1);\n v22 = _mm_loadu_si128(v5 + 2);\n v23 = _mm_loadu_si128(v5 + 3);\n v24 = _mm_loadu_si128(v5 + 4);\n v25 = _mm_loadu_si128(v5 + 5);\n v26 = v5[6].m128i_i64[0];\n v14 = v5[6].m128i_i32[1];\n } else {\n v7 = a2;\n v18 = a2 + v4;\n v8 = 0;\n do {\n if (v8 <= 0) {\n LABEL_4:\n v9 = 104LL * v8;\n v10 = &v6->m128i_i8[v9];\n v11 = v19;\n if (v19 < v9) v11 = 104LL * v8;\n v12 = v11 - v9;\n if (v12 > 100) v12 = 100LL;\n __strcpy_chk(v10, v7, v12);\n *((uint32_t *)v10 + 25) = *(uint32_t *)(v7 + 100);\n ++v8;\n } else {\n v13 = v6;\n while (strcmp(v13->m128i_i8, (const char *)v7)) {\n v13 = (__m128i *)((char *)v13 + 104);\n if (v13 == (__m128i *)((char *)v6 + 104 * v8)) goto LABEL_4;\n }\n v13[6].m128i_i32[1] += *(uint32_t *)(v7 + 100);\n }\n v7 += 104LL;\n } while (v7 != v18);\n v20 = _mm_loadu_si128(v6);\n v21 = _mm_loadu_si128(v6 + 1);\n v22 = _mm_loadu_si128(v6 + 2);\n v23 = _mm_loadu_si128(v6 + 3);\n v24 = _mm_loadu_si128(v6 + 4);\n v25 = _mm_loadu_si128(v6 + 5);\n v26 = v6[6].m128i_i64[0];\n v14 = v6[6].m128i_i32[1];\n if (v8 > 1) {\n v15 = (__m128i *)((char *)v6 + 104);\n do {\n v16 = v15[6].m128i_i32[1];\n if (v16 > v14) {\n v20 = _mm_loadu_si128(v15);\n v21 = _mm_loadu_si128(v15 + 1);\n v22 = _mm_loadu_si128(v15 + 2);\n v23 = _mm_loadu_si128(v15 + 3);\n v24 = _mm_loadu_si128(v15 + 4);\n v25 = _mm_loadu_si128(v15 + 5);\n v26 = v15[6].m128i_i64[0];\n v14 = v16;\n }\n v15 = (const __m128i *)((char *)v15 + 104);\n } while (v15 !=\n (__m128i *)((char *)&v6[13] + 104 * (unsigned int)(v8 - 2)));\n }\n }\n free(v6);\n HIDWORD(v26) = v14;\n *a1 = _mm_load_si128(&v20);\n a1[1] = _mm_load_si128(&v21);\n a1[2] = _mm_load_si128(&v22);\n a1[3] = _mm_load_si128(&v23);\n a1[4] = _mm_load_si128(&v24);\n a1[5] = _mm_load_si128(&v25);\n a1[6].m128i_i64[0] = v26;\n return a1;\n}" + }, + { + "index": 299, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char name[100];\n\n int marks;\n\n} student_data;\n\n\n\ntypedef struct {\n\n char name[100];\n\n int total_marks;\n\n} aggregated_data;\n\n\n\n", + "func": "aggregated_data func0(student_data stdata[], int size) {\n int i, j, found;\n aggregated_data *temp = malloc(size * sizeof(aggregated_data));\n int temp_count = 0;\n for (i = 0; i < size; i++) {\n found = 0;\n for (j = 0; j < temp_count; j++) {\n if (strcmp(temp[j].name, stdata[i].name) == 0) {\n temp[j].total_marks += stdata[i].marks;\n found = 1;\n break;\n }\n }\n if (!found) {\n strcpy(temp[temp_count].name, stdata[i].name);\n temp[temp_count].total_marks = stdata[i].marks;\n temp_count++;\n }\n }\n aggregated_data max = temp[0];\n for (i = 1; i < temp_count; i++) {\n if (temp[i].total_marks > max.total_marks) {\n max = temp[i];\n }\n }\n free(temp);\n return max;\n}", + "test": "int main() {\n\n student_data test1[5] = {{\"Juan Whelan\", 90}, {\"Sabah Colley\", 88}, {\"Peter Nichols\", 7}, {\"Juan Whelan\", 122}, {\"Sabah Colley\", 84}};\n\n aggregated_data result1 = func0(test1, 5);\n\n assert(strcmp(result1.name, \"Juan Whelan\") == 0 && result1.total_marks == 212);\n\n \n\n student_data test2[5] = {{\"Juan Whelan\", 50}, {\"Sabah Colley\", 48}, {\"Peter Nichols\", 37}, {\"Juan Whelan\", 22}, {\"Sabah Colley\", 14}};\n\n aggregated_data result2 = func0(test2, 5);\n\n assert(strcmp(result2.name, \"Juan Whelan\") == 0 && result2.total_marks == 72);\n\n\n\n student_data test3[5] = {{\"Juan Whelan\", 10}, {\"Sabah Colley\", 20}, {\"Peter Nichols\", 30}, {\"Juan Whelan\", 40}, {\"Sabah Colley\", 50}};\n\n aggregated_data result3 = func0(test3, 5);\n\n assert(strcmp(result3.name, \"Sabah Colley\") == 0 && result3.total_marks == 70);\n\n \n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\nmov %rsi,%r14\npush %r13\nmov %rdi,%r13\npush %r12\npush %rbp\npush %rbx\nmov %edx,%ebx\nsub $0x88,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x78(%rsp)\nxor %eax,%eax\nmovslq %edx,%rax\nlea (%rax,%rax,2),%rdx\nlea (%rax,%rdx,4),%rdi\nshl $0x3,%rdi\ncallq 1100 \nmov %rax,%r12\ntest %ebx,%ebx\njle 1611 \nlea -0x1(%rbx),%eax\nxor %ebp,%ebp\nlea (%rax,%rax,2),%rdx\nlea (%rax,%rdx,4),%rax\nlea 0x68(%r14,%rax,8),%rax\nmov %rax,(%rsp)\nlea 0x68(%r12),%rax\nmov %rax,0x8(%rsp)\nnopl 0x0(%rax)\ntest %ebp,%ebp\nje 15e0 \nlea -0x1(%rbp),%eax\nmov %r12,%r15\nlea (%rax,%rax,2),%rcx\nlea (%rax,%rcx,4),%rax\nmov 0x8(%rsp),%rcx\nlea (%rcx,%rax,8),%rbx\njmp 1465 \nnopl 0x0(%rax)\nadd $0x68,%r15\ncmp %r15,%rbx\nje 15e0 \nmov %r14,%rsi\nmov %r15,%rdi\ncallq 10f0 \ntest %eax,%eax\njne 1458 \nmov 0x64(%r14),%eax\nadd %eax,0x64(%r15)\nadd $0x68,%r14\ncmp (%rsp),%r14\njne 1430 \nmovdqu (%r12),%xmm6\nmovdqu 0x10(%r12),%xmm7\nmovdqu 0x40(%r12),%xmm0\nmovdqu 0x50(%r12),%xmm1\nmov 0x60(%r12),%rax\nmovaps %xmm6,0x10(%rsp)\nmov 0x64(%r12),%ebx\nmovdqu 0x20(%r12),%xmm6\nmovaps %xmm7,0x20(%rsp)\nmovdqu 0x30(%r12),%xmm7\nmov %rax,0x70(%rsp)\nmovaps %xmm6,0x30(%rsp)\nmovaps %xmm7,0x40(%rsp)\nmovaps %xmm0,0x50(%rsp)\nmovaps %xmm1,0x60(%rsp)\ncmp $0x1,%ebp\nje 1556 \nlea -0x2(%rbp),%edx\nlea 0x68(%r12),%rax\nlea (%rdx,%rdx,2),%rcx\nlea (%rdx,%rcx,4),%rdx\nlea 0xd0(%r12,%rdx,8),%rcx\nnopl 0x0(%rax)\nmov 0x64(%rax),%edx\ncmp %ebx,%edx\njle 154d \nmov 0x60(%rax),%rsi\nmovdqu (%rax),%xmm0\nmov %edx,%ebx\nmovdqu 0x10(%rax),%xmm1\nmovdqu 0x20(%rax),%xmm2\nmovdqu 0x30(%rax),%xmm3\nmovdqu 0x40(%rax),%xmm4\nmov %rsi,0x70(%rsp)\nmovdqu 0x50(%rax),%xmm5\nmovaps %xmm0,0x10(%rsp)\nmovaps %xmm1,0x20(%rsp)\nmovaps %xmm2,0x30(%rsp)\nmovaps %xmm3,0x40(%rsp)\nmovaps %xmm4,0x50(%rsp)\nmovaps %xmm5,0x60(%rsp)\nadd $0x68,%rax\ncmp %rcx,%rax\njne 1500 \nmov %r12,%rdi\ncallq 10b0 \nmovdqa 0x10(%rsp),%xmm6\nmovdqa 0x20(%rsp),%xmm7\nmov %ebx,0x74(%rsp)\nmov 0x70(%rsp),%rax\nmovups %xmm6,0x0(%r13)\nmovdqa 0x30(%rsp),%xmm6\nmovups %xmm7,0x10(%r13)\nmovdqa 0x40(%rsp),%xmm7\nmovups %xmm6,0x20(%r13)\nmovdqa 0x50(%rsp),%xmm6\nmovups %xmm7,0x30(%r13)\nmovdqa 0x60(%rsp),%xmm7\nmov %rax,0x60(%r13)\nmovups %xmm6,0x40(%r13)\nmovups %xmm7,0x50(%r13)\nmov 0x78(%rsp),%rax\nxor %fs:0x28,%rax\njne 165f \nadd $0x88,%rsp\nmov %r13,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw %cs:0x0(%rax,%rax,1)\nmovslq %ebp,%rax\nmov %r14,%rsi\nadd $0x1,%ebp\nlea (%rax,%rax,2),%rdx\nlea (%rax,%rdx,4),%rax\nmov $0x64,%edx\nlea (%r12,%rax,8),%rcx\nmov %rcx,%rdi\ncallq 1110 <__strcpy_chk@plt>\nmov %rax,%rcx\nmov 0x64(%r14),%eax\nmov %eax,0x64(%rcx)\njmpq 147c \nmovdqu (%rax),%xmm2\nmovdqu 0x10(%rax),%xmm3\nmovdqu 0x20(%rax),%xmm4\nmovdqu 0x30(%rax),%xmm5\nmovaps %xmm2,0x10(%rsp)\nmovdqu 0x40(%rax),%xmm2\nmov 0x64(%r12),%ebx\nmovaps %xmm3,0x20(%rsp)\nmovdqu 0x50(%rax),%xmm3\nmov 0x60(%rax),%rax\nmovaps %xmm4,0x30(%rsp)\nmov %rax,0x70(%rsp)\nmovaps %xmm5,0x40(%rsp)\nmovaps %xmm2,0x50(%rsp)\nmovaps %xmm3,0x60(%rsp)\njmpq 1556 \ncallq 10d0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\nmov ebp, edx\npush rbx\nmov rbx, rsi\nsub rsp, 98h\nmov [rsp+0C8h+var_B0], rdi\nmov rax, fs:28h\nmov [rsp+0C8h+var_40], rax\nxor eax, eax\nmovsxd rax, edx\nlea rdx, [rax+rax*2]\nlea r15, [rax+rdx*4]\nlea r14, ds:0[r15*8]\nmov rdi, r14; size\nmov [rsp+0C8h+var_B8], r14\ncall _malloc\nmov r12, rax\ntest ebp, ebp\njle loc_1644\nlea rax, [rbx+r14]\nxor r14d, r14d\nmov [rsp+0C8h+var_C0], rax\nnop dword ptr [rax+00000000h]\nloc_1430:\nmovsxd r13, r14d\ntest r14d, r14d\njle loc_15E8\nlea rax, [r13+r13*2+0]\nlea rax, [r13+rax*4+0]\nlea rbp, [r12+rax*8]\nloc_144A:\nmov r15, r12\njmp short loc_145D\nloc_1450:\nadd r15, 68h ; 'h'\ncmp r15, rbp\njz loc_15E8\nloc_145D:\nmov rsi, rbx; s2\nmov rdi, r15; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1450\nmov eax, [rbx+64h]\nadd [r15+64h], eax\nadd rbx, 68h ; 'h'\nmov rax, [rsp+0C8h+var_C0]\ncmp rbx, rax\njnz short loc_144A\nloc_1481:\nmovdqu xmm6, xmmword ptr [r12]\nmovdqu xmm7, xmmword ptr [r12+10h]\nmovdqu xmm0, xmmword ptr [r12+40h]\nmovdqu xmm1, xmmword ptr [r12+50h]\nmov rax, [r12+60h]\nmovaps [rsp+0C8h+var_A8], xmm6\nmov ebx, [r12+64h]\nmovdqu xmm6, xmmword ptr [r12+20h]\nmovaps [rsp+0C8h+var_98], xmm7\nmovdqu xmm7, xmmword ptr [r12+30h]\nmov [rsp+0C8h+var_48], rax\nmovaps [rsp+0C8h+var_88], xmm6\nmovaps [rsp+0C8h+var_78], xmm7\nmovaps [rsp+0C8h+var_68], xmm0\nmovaps [rsp+0C8h+var_58], xmm1\ncmp r14d, 1\njle short loc_1559\nlea edx, [r14-2]\nlea rax, [r12+68h]\nlea rcx, [rdx+rdx*2]\nlea rdx, [rdx+rcx*4]\nlea rcx, [r12+rdx*8+0D0h]\nnop dword ptr [rax+00000000h]\nloc_1500:\nmov edx, [rax+64h]\ncmp edx, ebx\njle short loc_1550\nmov rsi, [rax+60h]\nmovdqu xmm0, xmmword ptr [rax]\nmov ebx, edx\nmovdqu xmm1, xmmword ptr [rax+10h]\nmovdqu xmm2, xmmword ptr [rax+20h]\nmovdqu xmm3, xmmword ptr [rax+30h]\nmovdqu xmm4, xmmword ptr [rax+40h]\nmov [rsp+0C8h+var_48], rsi\nmovdqu xmm5, xmmword ptr [rax+50h]\nmovaps [rsp+0C8h+var_A8], xmm0\nmovaps [rsp+0C8h+var_98], xmm1\nmovaps [rsp+0C8h+var_88], xmm2\nmovaps [rsp+0C8h+var_78], xmm3\nmovaps [rsp+0C8h+var_68], xmm4\nmovaps [rsp+0C8h+var_58], xmm5\nloc_1550:\nadd rax, 68h ; 'h'\ncmp rcx, rax\njnz short loc_1500\nloc_1559:\nmov rdi, r12; ptr\ncall _free\nmov rcx, [rsp+0C8h+var_B0]\nmovdqa xmm6, [rsp+0C8h+var_A8]\nmov dword ptr [rsp+0C8h+var_48+4], ebx\nmovdqa xmm7, [rsp+0C8h+var_98]\nmov rax, [rsp+0C8h+var_48]\nmovups xmmword ptr [rcx], xmm6\nmovdqa xmm6, [rsp+0C8h+var_88]\nmovups xmmword ptr [rcx+10h], xmm7\nmovdqa xmm7, [rsp+0C8h+var_78]\nmovups xmmword ptr [rcx+20h], xmm6\nmovdqa xmm6, [rsp+0C8h+var_68]\nmovups xmmword ptr [rcx+30h], xmm7\nmovdqa xmm7, [rsp+0C8h+var_58]\nmov [rcx+60h], rax\nmovups xmmword ptr [rcx+40h], xmm6\nmovups xmmword ptr [rcx+50h], xmm7\nmov rax, [rsp+0C8h+var_40]\nsub rax, fs:28h\njnz loc_1695\nmov rax, [rsp+0C8h+var_B0]\nadd rsp, 98h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15E8:\nlea rax, [r13+r13*2+0]\nmov rdx, [rsp+0C8h+var_B8]\nmov rsi, rbx\nlea rax, [r13+rax*4+0]\nshl rax, 3\ncmp rdx, rax\nlea rcx, [r12+rax]\ncmovb rdx, rax\nmov rdi, rcx\nsub rdx, rax\nmov eax, 64h ; 'd'\ncmp rdx, rax\ncmova rdx, rax\nadd rbx, 68h ; 'h'\nadd r14d, 1\ncall ___strcpy_chk\nmov rcx, rax\nmov eax, [rbx-4]\nmov [rcx+64h], eax\nmov rax, [rsp+0C8h+var_C0]\ncmp rbx, rax\njnz loc_1430\njmp loc_1481\nloc_1644:\nmovdqu xmm2, xmmword ptr [rax]\nmovdqu xmm3, xmmword ptr [rax+10h]\nmovdqu xmm4, xmmword ptr [rax+20h]\nmovdqu xmm5, xmmword ptr [rax+30h]\nmovaps [rsp+0C8h+var_A8], xmm2\nmovdqu xmm2, xmmword ptr [rax+40h]\nmov ebx, [r12+64h]\nmovaps [rsp+0C8h+var_98], xmm3\nmovdqu xmm3, xmmword ptr [rax+50h]\nmov rax, [rax+60h]\nmovaps [rsp+0C8h+var_88], xmm4\nmov [rsp+0C8h+var_48], rax\nmovaps [rsp+0C8h+var_78], xmm5\nmovaps [rsp+0C8h+var_68], xmm2\nmovaps [rsp+0C8h+var_58], xmm3\njmp loc_1559\nloc_1695:\ncall ___stack_chk_fail", + "ida_pseudo": "__m128i *__fastcall func0(__m128i *a1, __int64 a2, int a3)\n{\n __int64 v4; // rbx\n size_t v5; // r14\n const __m128i *v6; // rax\n __m128i *v7; // r12\n size_t v8; // rax\n int v9; // r14d\n __int64 v10; // r13\n __m128i *v11; // r15\n __int64 v12; // rax\n __int32 v13; // ebx\n const __m128i *v14; // rax\n __m128i v15; // xmm6\n __m128i v16; // xmm7\n __int64 v17; // rax\n __m128i v18; // xmm6\n __m128i v19; // xmm7\n __m128i v20; // xmm6\n __m128i v21; // xmm7\n __int64 v23; // rdx\n __int64 v24; // rsi\n __int8 *v25; // rcx\n unsigned __int64 v26; // rdx\n __m128i v27; // xmm4\n __m128i v28; // xmm5\n __m128i v29; // xmm2\n __m128i v30; // xmm3\n __int64 v31; // rax\n size_t v32; // [rsp+8h] [rbp-C0h]\n unsigned __int64 v33; // [rsp+10h] [rbp-B8h]\n __m128i v34; // [rsp+20h] [rbp-A8h] BYREF\n __m128i v35; // [rsp+30h] [rbp-98h] BYREF\n __m128i v36; // [rsp+40h] [rbp-88h] BYREF\n __m128i v37; // [rsp+50h] [rbp-78h] BYREF\n __m128i v38; // [rsp+60h] [rbp-68h] BYREF\n __m128i v39; // [rsp+70h] [rbp-58h] BYREF\n __int64 v40; // [rsp+80h] [rbp-48h]\n unsigned __int64 v41; // [rsp+88h] [rbp-40h]\n\n v4 = a2;\n v41 = __readfsqword(0x28u);\n v5 = 104LL * a3;\n v33 = v5;\n v6 = (const __m128i *)malloc(v5);\n v7 = (__m128i *)v6;\n if ( a3 <= 0 )\n {\n v27 = _mm_loadu_si128(v6 + 2);\n v28 = _mm_loadu_si128(v6 + 3);\n v34 = _mm_loadu_si128(v6);\n v29 = _mm_loadu_si128(v6 + 4);\n v13 = v6[6].m128i_i32[1];\n v35 = _mm_loadu_si128(v6 + 1);\n v30 = _mm_loadu_si128(v6 + 5);\n v31 = v6[6].m128i_i64[0];\n v36 = v27;\n v40 = v31;\n v37 = v28;\n v38 = v29;\n v39 = v30;\n }\n else\n {\n v8 = a2 + v5;\n v9 = 0;\n v32 = v8;\n while ( 1 )\n {\n v10 = v9;\n if ( v9 > 0 )\n break;\nLABEL_14:\n v23 = v33;\n v24 = v4;\n v25 = &v7->m128i_i8[104 * v9];\n if ( v33 < 104LL * v9 )\n v23 = 104LL * v9;\n v26 = v23 - 104LL * v9;\n if ( v26 > 0x64 )\n v26 = 100LL;\n v4 += 104LL;\n ++v9;\n *(_DWORD *)(__strcpy_chk((char *)v7 + 104 * v10, v24, v26, v25) + 100) = *(_DWORD *)(v4 - 4);\n if ( v4 == v32 )\n goto LABEL_8;\n }\n do\n {\n v11 = v7;\n while ( strcmp(v11->m128i_i8, (const char *)v4) )\n {\n v11 = (__m128i *)((char *)v11 + 104);\n if ( v11 == (__m128i *)((char *)v7 + 104 * v9) )\n goto LABEL_14;\n }\n v11[6].m128i_i32[1] += *(_DWORD *)(v4 + 100);\n v4 += 104LL;\n }\n while ( v4 != v32 );\nLABEL_8:\n v12 = v7[6].m128i_i64[0];\n v34 = _mm_loadu_si128(v7);\n v13 = v7[6].m128i_i32[1];\n v35 = _mm_loadu_si128(v7 + 1);\n v40 = v12;\n v36 = _mm_loadu_si128(v7 + 2);\n v37 = _mm_loadu_si128(v7 + 3);\n v38 = _mm_loadu_si128(v7 + 4);\n v39 = _mm_loadu_si128(v7 + 5);\n if ( v9 > 1 )\n {\n v14 = (__m128i *)((char *)v7 + 104);\n do\n {\n if ( v14[6].m128i_i32[1] > v13 )\n {\n v13 = v14[6].m128i_i32[1];\n v40 = v14[6].m128i_i64[0];\n v34 = _mm_loadu_si128(v14);\n v35 = _mm_loadu_si128(v14 + 1);\n v36 = _mm_loadu_si128(v14 + 2);\n v37 = _mm_loadu_si128(v14 + 3);\n v38 = _mm_loadu_si128(v14 + 4);\n v39 = _mm_loadu_si128(v14 + 5);\n }\n v14 = (const __m128i *)((char *)v14 + 104);\n }\n while ( (__m128i *)((char *)&v7[13] + 104 * (unsigned int)(v9 - 2)) != v14 );\n }\n }\n free(v7);\n v15 = _mm_load_si128(&v34);\n HIDWORD(v40) = v13;\n v16 = _mm_load_si128(&v35);\n v17 = v40;\n *a1 = v15;\n v18 = _mm_load_si128(&v36);\n a1[1] = v16;\n v19 = _mm_load_si128(&v37);\n a1[2] = v18;\n v20 = _mm_load_si128(&v38);\n a1[3] = v19;\n v21 = _mm_load_si128(&v39);\n a1[6].m128i_i64[0] = v17;\n a1[4] = v20;\n a1[5] = v21;\n return a1;\n}", + "ida_strip_asm": "sub_13C0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\nmov ebp, edx\npush rbx\nmov rbx, rsi\nsub rsp, 98h\nmov [rsp+0C8h+var_B0], rdi\nmov rax, fs:28h\nmov [rsp+0C8h+var_40], rax\nxor eax, eax\nmovsxd rax, edx\nlea rdx, [rax+rax*2]\nlea r15, [rax+rdx*4]\nlea r14, ds:0[r15*8]\nmov rdi, r14; size\nmov [rsp+0C8h+var_B8], r14\ncall _malloc\nmov r12, rax\ntest ebp, ebp\njle loc_1644\nlea rax, [rbx+r14]\nxor r14d, r14d\nmov [rsp+0C8h+var_C0], rax\nnop dword ptr [rax+00000000h]\nloc_1430:\nmovsxd r13, r14d\ntest r14d, r14d\njle loc_15E8\nlea rax, [r13+r13*2+0]\nlea rax, [r13+rax*4+0]\nlea rbp, [r12+rax*8]\nloc_144A:\nmov r15, r12\njmp short loc_145D\nloc_1450:\nadd r15, 68h ; 'h'\ncmp r15, rbp\njz loc_15E8\nloc_145D:\nmov rsi, rbx; s2\nmov rdi, r15; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1450\nmov eax, [rbx+64h]\nadd [r15+64h], eax\nadd rbx, 68h ; 'h'\nmov rax, [rsp+0C8h+var_C0]\ncmp rbx, rax\njnz short loc_144A\nloc_1481:\nmovdqu xmm6, xmmword ptr [r12]\nmovdqu xmm7, xmmword ptr [r12+10h]\nmovdqu xmm0, xmmword ptr [r12+40h]\nmovdqu xmm1, xmmword ptr [r12+50h]\nmov rax, [r12+60h]\nmovaps [rsp+0C8h+var_A8], xmm6\nmov ebx, [r12+64h]\nmovdqu xmm6, xmmword ptr [r12+20h]\nmovaps [rsp+0C8h+var_98], xmm7\nmovdqu xmm7, xmmword ptr [r12+30h]\nmov [rsp+0C8h+var_48], rax\nmovaps [rsp+0C8h+var_88], xmm6\nmovaps [rsp+0C8h+var_78], xmm7\nmovaps [rsp+0C8h+var_68], xmm0\nmovaps [rsp+0C8h+var_58], xmm1\ncmp r14d, 1\njle short loc_1559\nlea edx, [r14-2]\nlea rax, [r12+68h]\nlea rcx, [rdx+rdx*2]\nlea rdx, [rdx+rcx*4]\nlea rcx, [r12+rdx*8+0D0h]\nnop dword ptr [rax+00000000h]\nloc_1500:\nmov edx, [rax+64h]\ncmp edx, ebx\njle short loc_1550\nmov rsi, [rax+60h]\nmovdqu xmm0, xmmword ptr [rax]\nmov ebx, edx\nmovdqu xmm1, xmmword ptr [rax+10h]\nmovdqu xmm2, xmmword ptr [rax+20h]\nmovdqu xmm3, xmmword ptr [rax+30h]\nmovdqu xmm4, xmmword ptr [rax+40h]\nmov [rsp+0C8h+var_48], rsi\nmovdqu xmm5, xmmword ptr [rax+50h]\nmovaps [rsp+0C8h+var_A8], xmm0\nmovaps [rsp+0C8h+var_98], xmm1\nmovaps [rsp+0C8h+var_88], xmm2\nmovaps [rsp+0C8h+var_78], xmm3\nmovaps [rsp+0C8h+var_68], xmm4\nmovaps [rsp+0C8h+var_58], xmm5\nloc_1550:\nadd rax, 68h ; 'h'\ncmp rcx, rax\njnz short loc_1500\nloc_1559:\nmov rdi, r12; ptr\ncall _free\nmov rcx, [rsp+0C8h+var_B0]\nmovdqa xmm6, [rsp+0C8h+var_A8]\nmov dword ptr [rsp+0C8h+var_48+4], ebx\nmovdqa xmm7, [rsp+0C8h+var_98]\nmov rax, [rsp+0C8h+var_48]\nmovups xmmword ptr [rcx], xmm6\nmovdqa xmm6, [rsp+0C8h+var_88]\nmovups xmmword ptr [rcx+10h], xmm7\nmovdqa xmm7, [rsp+0C8h+var_78]\nmovups xmmword ptr [rcx+20h], xmm6\nmovdqa xmm6, [rsp+0C8h+var_68]\nmovups xmmword ptr [rcx+30h], xmm7\nmovdqa xmm7, [rsp+0C8h+var_58]\nmov [rcx+60h], rax\nmovups xmmword ptr [rcx+40h], xmm6\nmovups xmmword ptr [rcx+50h], xmm7\nmov rax, [rsp+0C8h+var_40]\nsub rax, fs:28h\njnz loc_1695\nmov rax, [rsp+0C8h+var_B0]\nadd rsp, 98h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15E8:\nlea rax, [r13+r13*2+0]\nmov rdx, [rsp+0C8h+var_B8]\nmov rsi, rbx\nlea rax, [r13+rax*4+0]\nshl rax, 3\ncmp rdx, rax\nlea rcx, [r12+rax]\ncmovb rdx, rax\nmov rdi, rcx\nsub rdx, rax\nmov eax, 64h ; 'd'\ncmp rdx, rax\ncmova rdx, rax\nadd rbx, 68h ; 'h'\nadd r14d, 1\ncall ___strcpy_chk\nmov rcx, rax\nmov eax, [rbx-4]\nmov [rcx+64h], eax\nmov rax, [rsp+0C8h+var_C0]\ncmp rbx, rax\njnz loc_1430\njmp loc_1481\nloc_1644:\nmovdqu xmm2, xmmword ptr [rax]\nmovdqu xmm3, xmmword ptr [rax+10h]\nmovdqu xmm4, xmmword ptr [rax+20h]\nmovdqu xmm5, xmmword ptr [rax+30h]\nmovaps [rsp+0C8h+var_A8], xmm2\nmovdqu xmm2, xmmword ptr [rax+40h]\nmov ebx, [r12+64h]\nmovaps [rsp+0C8h+var_98], xmm3\nmovdqu xmm3, xmmword ptr [rax+50h]\nmov rax, [rax+60h]\nmovaps [rsp+0C8h+var_88], xmm4\nmov [rsp+0C8h+var_48], rax\nmovaps [rsp+0C8h+var_78], xmm5\nmovaps [rsp+0C8h+var_68], xmm2\nmovaps [rsp+0C8h+var_58], xmm3\njmp loc_1559\nloc_1695:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__m128i *__fastcall sub_13C0(__m128i *a1, __int64 a2, int a3)\n{\n __int64 v4; // rbx\n size_t v5; // r14\n const __m128i *v6; // rax\n __m128i *v7; // r12\n size_t v8; // rax\n int v9; // r14d\n __int64 v10; // r13\n __m128i *v11; // r15\n __int64 v12; // rax\n __int32 v13; // ebx\n const __m128i *v14; // rax\n __m128i v15; // xmm6\n __m128i v16; // xmm7\n __int64 v17; // rax\n __m128i v18; // xmm6\n __m128i v19; // xmm7\n __m128i v20; // xmm6\n __m128i v21; // xmm7\n __int64 v23; // rdx\n __int64 v24; // rsi\n __int8 *v25; // rcx\n unsigned __int64 v26; // rdx\n __m128i v27; // xmm4\n __m128i v28; // xmm5\n __m128i v29; // xmm2\n __m128i v30; // xmm3\n __int64 v31; // rax\n size_t v32; // [rsp+8h] [rbp-C0h]\n unsigned __int64 v33; // [rsp+10h] [rbp-B8h]\n __m128i v34; // [rsp+20h] [rbp-A8h] BYREF\n __m128i v35; // [rsp+30h] [rbp-98h] BYREF\n __m128i v36; // [rsp+40h] [rbp-88h] BYREF\n __m128i v37; // [rsp+50h] [rbp-78h] BYREF\n __m128i v38; // [rsp+60h] [rbp-68h] BYREF\n __m128i v39; // [rsp+70h] [rbp-58h] BYREF\n __int64 v40; // [rsp+80h] [rbp-48h]\n unsigned __int64 v41; // [rsp+88h] [rbp-40h]\n\n v4 = a2;\n v41 = __readfsqword(0x28u);\n v5 = 104LL * a3;\n v33 = v5;\n v6 = (const __m128i *)malloc(v5);\n v7 = (__m128i *)v6;\n if ( a3 <= 0 )\n {\n v27 = _mm_loadu_si128(v6 + 2);\n v28 = _mm_loadu_si128(v6 + 3);\n v34 = _mm_loadu_si128(v6);\n v29 = _mm_loadu_si128(v6 + 4);\n v13 = v6[6].m128i_i32[1];\n v35 = _mm_loadu_si128(v6 + 1);\n v30 = _mm_loadu_si128(v6 + 5);\n v31 = v6[6].m128i_i64[0];\n v36 = v27;\n v40 = v31;\n v37 = v28;\n v38 = v29;\n v39 = v30;\n }\n else\n {\n v8 = a2 + v5;\n v9 = 0;\n v32 = v8;\n while ( 1 )\n {\n v10 = v9;\n if ( v9 > 0 )\n break;\nLABEL_14:\n v23 = v33;\n v24 = v4;\n v25 = &v7->m128i_i8[104 * v9];\n if ( v33 < 104LL * v9 )\n v23 = 104LL * v9;\n v26 = v23 - 104LL * v9;\n if ( v26 > 0x64 )\n v26 = 100LL;\n v4 += 104LL;\n ++v9;\n *(_DWORD *)(__strcpy_chk((char *)v7 + 104 * v10, v24, v26, v25) + 100) = *(_DWORD *)(v4 - 4);\n if ( v4 == v32 )\n goto LABEL_8;\n }\n do\n {\n v11 = v7;\n while ( strcmp(v11->m128i_i8, (const char *)v4) )\n {\n v11 = (__m128i *)((char *)v11 + 104);\n if ( v11 == (__m128i *)((char *)v7 + 104 * v9) )\n goto LABEL_14;\n }\n v11[6].m128i_i32[1] += *(_DWORD *)(v4 + 100);\n v4 += 104LL;\n }\n while ( v4 != v32 );\nLABEL_8:\n v12 = v7[6].m128i_i64[0];\n v34 = _mm_loadu_si128(v7);\n v13 = v7[6].m128i_i32[1];\n v35 = _mm_loadu_si128(v7 + 1);\n v40 = v12;\n v36 = _mm_loadu_si128(v7 + 2);\n v37 = _mm_loadu_si128(v7 + 3);\n v38 = _mm_loadu_si128(v7 + 4);\n v39 = _mm_loadu_si128(v7 + 5);\n if ( v9 > 1 )\n {\n v14 = (__m128i *)((char *)v7 + 104);\n do\n {\n if ( v14[6].m128i_i32[1] > v13 )\n {\n v13 = v14[6].m128i_i32[1];\n v40 = v14[6].m128i_i64[0];\n v34 = _mm_loadu_si128(v14);\n v35 = _mm_loadu_si128(v14 + 1);\n v36 = _mm_loadu_si128(v14 + 2);\n v37 = _mm_loadu_si128(v14 + 3);\n v38 = _mm_loadu_si128(v14 + 4);\n v39 = _mm_loadu_si128(v14 + 5);\n }\n v14 = (const __m128i *)((char *)v14 + 104);\n }\n while ( (__m128i *)((char *)&v7[13] + 104 * (unsigned int)(v9 - 2)) != v14 );\n }\n }\n free(v7);\n v15 = _mm_load_si128(&v34);\n HIDWORD(v40) = v13;\n v16 = _mm_load_si128(&v35);\n v17 = v40;\n *a1 = v15;\n v18 = _mm_load_si128(&v36);\n a1[1] = v16;\n v19 = _mm_load_si128(&v37);\n a1[2] = v18;\n v20 = _mm_load_si128(&v38);\n a1[3] = v19;\n v21 = _mm_load_si128(&v39);\n a1[6].m128i_i64[0] = v17;\n a1[4] = v20;\n a1[5] = v21;\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__m128i *sub_13C0(__m128i *a1, long long a2, int a3) {\n long long v4;\n unsigned int v5;\n const __m128i *v6;\n __m128i *v7;\n unsigned int v8;\n int v9;\n long long v10;\n __m128i *v11;\n long long v12;\n int v13;\n const __m128i *v14;\n __m128i v15;\n __m128i v16;\n long long v17;\n __m128i v18;\n __m128i v19;\n __m128i v20;\n __m128i v21;\n long long v23;\n long long v24;\n char *v25;\n unsigned long long v26;\n __m128i v27;\n __m128i v28;\n __m128i v29;\n __m128i v30;\n long long v31;\n unsigned int v32;\n unsigned long long v33;\n __m128i v34;\n __m128i v35;\n __m128i v36;\n __m128i v37;\n __m128i v38;\n __m128i v39;\n long long v40;\n unsigned long long v41;\n v4 = a2;\n v41 = __readfsqword(40u);\n v5 = 104LL * a3;\n v33 = v5;\n v6 = (const __m128i *)malloc(v5);\n v7 = (__m128i *)v6;\n if (a3 <= 0) {\n v27 = _mm_loadu_si128(v6 + 2);\n v28 = _mm_loadu_si128(v6 + 3);\n v34 = _mm_loadu_si128(v6);\n v29 = _mm_loadu_si128(v6 + 4);\n v13 = v6[6].m128i_i32[1];\n v35 = _mm_loadu_si128(v6 + 1);\n v30 = _mm_loadu_si128(v6 + 5);\n v31 = v6[6].m128i_i64[0];\n v36 = v27;\n v40 = v31;\n v37 = v28;\n v38 = v29;\n v39 = v30;\n } else {\n v8 = a2 + v5;\n v9 = 0;\n v32 = v8;\n while (1) {\n v10 = v9;\n if (v9 > 0) break;\n LABEL_14:\n v23 = v33;\n v24 = v4;\n v25 = &v7->m128i_i8[104 * v9];\n if (v33 < 104LL * v9) v23 = 104LL * v9;\n v26 = v23 - 104LL * v9;\n if (v26 > 100) v26 = 100LL;\n v4 += 104LL;\n ++v9;\n *(uint32_t *)(__strcpy_chk((char *)v7 + 104 * v10, v24, v26, v25) + 100) =\n *(uint32_t *)(v4 - 4);\n if (v4 == v32) goto LABEL_8;\n }\n do {\n v11 = v7;\n while (strcmp(v11->m128i_i8, (const char *)v4)) {\n v11 = (__m128i *)((char *)v11 + 104);\n if (v11 == (__m128i *)((char *)v7 + 104 * v9)) goto LABEL_14;\n }\n v11[6].m128i_i32[1] += *(uint32_t *)(v4 + 100);\n v4 += 104LL;\n } while (v4 != v32);\n LABEL_8:\n v12 = v7[6].m128i_i64[0];\n v34 = _mm_loadu_si128(v7);\n v13 = v7[6].m128i_i32[1];\n v35 = _mm_loadu_si128(v7 + 1);\n v40 = v12;\n v36 = _mm_loadu_si128(v7 + 2);\n v37 = _mm_loadu_si128(v7 + 3);\n v38 = _mm_loadu_si128(v7 + 4);\n v39 = _mm_loadu_si128(v7 + 5);\n if (v9 > 1) {\n v14 = (__m128i *)((char *)v7 + 104);\n do {\n if (v14[6].m128i_i32[1] > v13) {\n v13 = v14[6].m128i_i32[1];\n v40 = v14[6].m128i_i64[0];\n v34 = _mm_loadu_si128(v14);\n v35 = _mm_loadu_si128(v14 + 1);\n v36 = _mm_loadu_si128(v14 + 2);\n v37 = _mm_loadu_si128(v14 + 3);\n v38 = _mm_loadu_si128(v14 + 4);\n v39 = _mm_loadu_si128(v14 + 5);\n }\n v14 = (const __m128i *)((char *)v14 + 104);\n } while ((__m128i *)((char *)&v7[13] + 104 * (unsigned int)(v9 - 2)) !=\n v14);\n }\n }\n free(v7);\n v15 = _mm_load_si128(&v34);\n HIDWORD(v40) = v13;\n v16 = _mm_load_si128(&v35);\n v17 = v40;\n *a1 = v15;\n v18 = _mm_load_si128(&v36);\n a1[1] = v16;\n v19 = _mm_load_si128(&v37);\n a1[2] = v18;\n v20 = _mm_load_si128(&v38);\n a1[3] = v19;\n v21 = _mm_load_si128(&v39);\n a1[6].m128i_i64[0] = v17;\n a1[4] = v20;\n a1[5] = v21;\n return a1;\n}", + "ida_pseudo_norm": "__m128i *func0(__m128i *a1, long long a2, int a3) {\n long long v4;\n unsigned int v5;\n const __m128i *v6;\n __m128i *v7;\n unsigned int v8;\n int v9;\n long long v10;\n __m128i *v11;\n long long v12;\n int v13;\n const __m128i *v14;\n __m128i v15;\n __m128i v16;\n long long v17;\n __m128i v18;\n __m128i v19;\n __m128i v20;\n __m128i v21;\n long long v23;\n long long v24;\n char *v25;\n unsigned long long v26;\n __m128i v27;\n __m128i v28;\n __m128i v29;\n __m128i v30;\n long long v31;\n unsigned int v32;\n unsigned long long v33;\n __m128i v34;\n __m128i v35;\n __m128i v36;\n __m128i v37;\n __m128i v38;\n __m128i v39;\n long long v40;\n unsigned long long v41;\n v4 = a2;\n v41 = __readfsqword(40u);\n v5 = 104LL * a3;\n v33 = v5;\n v6 = (const __m128i *)malloc(v5);\n v7 = (__m128i *)v6;\n if (a3 <= 0) {\n v27 = _mm_loadu_si128(v6 + 2);\n v28 = _mm_loadu_si128(v6 + 3);\n v34 = _mm_loadu_si128(v6);\n v29 = _mm_loadu_si128(v6 + 4);\n v13 = v6[6].m128i_i32[1];\n v35 = _mm_loadu_si128(v6 + 1);\n v30 = _mm_loadu_si128(v6 + 5);\n v31 = v6[6].m128i_i64[0];\n v36 = v27;\n v40 = v31;\n v37 = v28;\n v38 = v29;\n v39 = v30;\n } else {\n v8 = a2 + v5;\n v9 = 0;\n v32 = v8;\n while (1) {\n v10 = v9;\n if (v9 > 0) break;\n LABEL_14:\n v23 = v33;\n v24 = v4;\n v25 = &v7->m128i_i8[104 * v9];\n if (v33 < 104LL * v9) v23 = 104LL * v9;\n v26 = v23 - 104LL * v9;\n if (v26 > 100) v26 = 100LL;\n v4 += 104LL;\n ++v9;\n *(uint32_t *)(__strcpy_chk((char *)v7 + 104 * v10, v24, v26, v25) + 100) =\n *(uint32_t *)(v4 - 4);\n if (v4 == v32) goto LABEL_8;\n }\n do {\n v11 = v7;\n while (strcmp(v11->m128i_i8, (const char *)v4)) {\n v11 = (__m128i *)((char *)v11 + 104);\n if (v11 == (__m128i *)((char *)v7 + 104 * v9)) goto LABEL_14;\n }\n v11[6].m128i_i32[1] += *(uint32_t *)(v4 + 100);\n v4 += 104LL;\n } while (v4 != v32);\n LABEL_8:\n v12 = v7[6].m128i_i64[0];\n v34 = _mm_loadu_si128(v7);\n v13 = v7[6].m128i_i32[1];\n v35 = _mm_loadu_si128(v7 + 1);\n v40 = v12;\n v36 = _mm_loadu_si128(v7 + 2);\n v37 = _mm_loadu_si128(v7 + 3);\n v38 = _mm_loadu_si128(v7 + 4);\n v39 = _mm_loadu_si128(v7 + 5);\n if (v9 > 1) {\n v14 = (__m128i *)((char *)v7 + 104);\n do {\n if (v14[6].m128i_i32[1] > v13) {\n v13 = v14[6].m128i_i32[1];\n v40 = v14[6].m128i_i64[0];\n v34 = _mm_loadu_si128(v14);\n v35 = _mm_loadu_si128(v14 + 1);\n v36 = _mm_loadu_si128(v14 + 2);\n v37 = _mm_loadu_si128(v14 + 3);\n v38 = _mm_loadu_si128(v14 + 4);\n v39 = _mm_loadu_si128(v14 + 5);\n }\n v14 = (const __m128i *)((char *)v14 + 104);\n } while ((__m128i *)((char *)&v7[13] + 104 * (unsigned int)(v9 - 2)) !=\n v14);\n }\n }\n free(v7);\n v15 = _mm_load_si128(&v34);\n HIDWORD(v40) = v13;\n v16 = _mm_load_si128(&v35);\n v17 = v40;\n *a1 = v15;\n v18 = _mm_load_si128(&v36);\n a1[1] = v16;\n v19 = _mm_load_si128(&v37);\n a1[2] = v18;\n v20 = _mm_load_si128(&v38);\n a1[3] = v19;\n v21 = _mm_load_si128(&v39);\n a1[6].m128i_i64[0] = v17;\n a1[4] = v20;\n a1[5] = v21;\n return a1;\n}" + }, + { + "index": 299, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char name[100];\n\n int marks;\n\n} student_data;\n\n\n\ntypedef struct {\n\n char name[100];\n\n int total_marks;\n\n} aggregated_data;\n\n\n\n", + "func": "aggregated_data func0(student_data stdata[], int size) {\n int i, j, found;\n aggregated_data *temp = malloc(size * sizeof(aggregated_data));\n int temp_count = 0;\n for (i = 0; i < size; i++) {\n found = 0;\n for (j = 0; j < temp_count; j++) {\n if (strcmp(temp[j].name, stdata[i].name) == 0) {\n temp[j].total_marks += stdata[i].marks;\n found = 1;\n break;\n }\n }\n if (!found) {\n strcpy(temp[temp_count].name, stdata[i].name);\n temp[temp_count].total_marks = stdata[i].marks;\n temp_count++;\n }\n }\n aggregated_data max = temp[0];\n for (i = 1; i < temp_count; i++) {\n if (temp[i].total_marks > max.total_marks) {\n max = temp[i];\n }\n }\n free(temp);\n return max;\n}", + "test": "int main() {\n\n student_data test1[5] = {{\"Juan Whelan\", 90}, {\"Sabah Colley\", 88}, {\"Peter Nichols\", 7}, {\"Juan Whelan\", 122}, {\"Sabah Colley\", 84}};\n\n aggregated_data result1 = func0(test1, 5);\n\n assert(strcmp(result1.name, \"Juan Whelan\") == 0 && result1.total_marks == 212);\n\n \n\n student_data test2[5] = {{\"Juan Whelan\", 50}, {\"Sabah Colley\", 48}, {\"Peter Nichols\", 37}, {\"Juan Whelan\", 22}, {\"Sabah Colley\", 14}};\n\n aggregated_data result2 = func0(test2, 5);\n\n assert(strcmp(result2.name, \"Juan Whelan\") == 0 && result2.total_marks == 72);\n\n\n\n student_data test3[5] = {{\"Juan Whelan\", 10}, {\"Sabah Colley\", 20}, {\"Peter Nichols\", 30}, {\"Juan Whelan\", 40}, {\"Sabah Colley\", 50}};\n\n aggregated_data result3 = func0(test3, 5);\n\n assert(strcmp(result3.name, \"Sabah Colley\") == 0 && result3.total_marks == 70);\n\n \n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\nmov %rsi,%r14\npush %r13\nmov %rdi,%r13\npush %r12\npush %rbp\npush %rbx\nmov %edx,%ebx\nsub $0x88,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x78(%rsp)\nxor %eax,%eax\nmovslq %edx,%rax\nlea (%rax,%rax,2),%rdx\nlea (%rax,%rdx,4),%rdi\nshl $0x3,%rdi\ncallq 1100 \nmov %rax,%r12\ntest %ebx,%ebx\njle 1611 \nlea -0x1(%rbx),%eax\nxor %ebp,%ebp\nlea (%rax,%rax,2),%rdx\nlea (%rax,%rdx,4),%rax\nlea 0x68(%r14,%rax,8),%rax\nmov %rax,(%rsp)\nlea 0x68(%r12),%rax\nmov %rax,0x8(%rsp)\nnopl 0x0(%rax)\ntest %ebp,%ebp\nje 15e0 \nlea -0x1(%rbp),%eax\nmov %r12,%r15\nlea (%rax,%rax,2),%rcx\nlea (%rax,%rcx,4),%rax\nmov 0x8(%rsp),%rcx\nlea (%rcx,%rax,8),%rbx\njmp 1465 \nnopl 0x0(%rax)\nadd $0x68,%r15\ncmp %rbx,%r15\nje 15e0 \nmov %r14,%rsi\nmov %r15,%rdi\ncallq 10f0 \ntest %eax,%eax\njne 1458 \nmov 0x64(%r14),%eax\nadd %eax,0x64(%r15)\nadd $0x68,%r14\ncmp %r14,(%rsp)\njne 1430 \nmovdqu (%r12),%xmm6\nmovdqu 0x10(%r12),%xmm7\nmovdqu 0x40(%r12),%xmm0\nmovdqu 0x50(%r12),%xmm1\nmov 0x60(%r12),%rax\nmovaps %xmm6,0x10(%rsp)\nmov 0x64(%r12),%ebx\nmovdqu 0x20(%r12),%xmm6\nmovaps %xmm7,0x20(%rsp)\nmovdqu 0x30(%r12),%xmm7\nmov %rax,0x70(%rsp)\nmovaps %xmm6,0x30(%rsp)\nmovaps %xmm7,0x40(%rsp)\nmovaps %xmm0,0x50(%rsp)\nmovaps %xmm1,0x60(%rsp)\ncmp $0x1,%ebp\nje 1556 \nlea -0x2(%rbp),%edx\nlea 0x68(%r12),%rax\nlea (%rdx,%rdx,2),%rcx\nlea (%rdx,%rcx,4),%rdx\nlea 0xd0(%r12,%rdx,8),%rcx\nnopl 0x0(%rax)\nmov 0x64(%rax),%edx\ncmp %ebx,%edx\njle 154d \nmov 0x60(%rax),%rsi\nmovdqu (%rax),%xmm0\nmov %edx,%ebx\nmovdqu 0x10(%rax),%xmm1\nmovdqu 0x20(%rax),%xmm2\nmovdqu 0x30(%rax),%xmm3\nmovdqu 0x40(%rax),%xmm4\nmov %rsi,0x70(%rsp)\nmovdqu 0x50(%rax),%xmm5\nmovaps %xmm0,0x10(%rsp)\nmovaps %xmm1,0x20(%rsp)\nmovaps %xmm2,0x30(%rsp)\nmovaps %xmm3,0x40(%rsp)\nmovaps %xmm4,0x50(%rsp)\nmovaps %xmm5,0x60(%rsp)\nadd $0x68,%rax\ncmp %rax,%rcx\njne 1500 \nmov %r12,%rdi\ncallq 10b0 \nmovdqa 0x10(%rsp),%xmm6\nmovdqa 0x20(%rsp),%xmm7\nmov %ebx,0x74(%rsp)\nmov 0x70(%rsp),%rax\nmovups %xmm6,0x0(%r13)\nmovdqa 0x30(%rsp),%xmm6\nmovups %xmm7,0x10(%r13)\nmovdqa 0x40(%rsp),%xmm7\nmovups %xmm6,0x20(%r13)\nmovdqa 0x50(%rsp),%xmm6\nmovups %xmm7,0x30(%r13)\nmovdqa 0x60(%rsp),%xmm7\nmov %rax,0x60(%r13)\nmovups %xmm6,0x40(%r13)\nmovups %xmm7,0x50(%r13)\nmov 0x78(%rsp),%rax\nxor %fs:0x28,%rax\njne 165f \nadd $0x88,%rsp\nmov %r13,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw %cs:0x0(%rax,%rax,1)\nmovslq %ebp,%rax\nmov %r14,%rsi\nadd $0x1,%ebp\nlea (%rax,%rax,2),%rdx\nlea (%rax,%rdx,4),%rax\nmov $0x64,%edx\nlea (%r12,%rax,8),%rcx\nmov %rcx,%rdi\ncallq 1110 <__strcpy_chk@plt>\nmov %rax,%rcx\nmov 0x64(%r14),%eax\nmov %eax,0x64(%rcx)\njmpq 147c \nmovdqu (%rax),%xmm2\nmovdqu 0x10(%rax),%xmm3\nmovdqu 0x20(%rax),%xmm4\nmovdqu 0x30(%rax),%xmm5\nmovaps %xmm2,0x10(%rsp)\nmovdqu 0x40(%rax),%xmm2\nmov 0x64(%r12),%ebx\nmovaps %xmm3,0x20(%rsp)\nmovdqu 0x50(%rax),%xmm3\nmov 0x60(%rax),%rax\nmovaps %xmm4,0x30(%rsp)\nmov %rax,0x70(%rsp)\nmovaps %xmm5,0x40(%rsp)\nmovaps %xmm2,0x50(%rsp)\nmovaps %xmm3,0x60(%rsp)\njmpq 1556 \ncallq 10d0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\nmov ebp, edx\npush rbx\nmov rbx, rsi\nsub rsp, 98h\nmov [rsp+0C8h+var_B0], rdi\nmov rax, fs:28h\nmov [rsp+0C8h+var_40], rax\nxor eax, eax\nmovsxd rax, edx\nlea rdx, [rax+rax*2]\nlea r15, [rax+rdx*4]\nlea r14, ds:0[r15*8]\nmov rdi, r14; size\nmov [rsp+0C8h+var_B8], r14\ncall _malloc\nmov r12, rax\ntest ebp, ebp\njle loc_163C\nlea rax, [rbx+r14]\nxor r14d, r14d\nmov [rsp+0C8h+var_C0], rax\nnop dword ptr [rax+00000000h]\nloc_1430:\nmovsxd r13, r14d\ntest r14d, r14d\njle loc_15E0\nlea rax, [r13+r13*2+0]\nlea rax, [r13+rax*4+0]\nlea rbp, [r12+rax*8]\nloc_144A:\nmov r15, r12\njmp short loc_145D\nloc_1450:\nadd r15, 68h ; 'h'\ncmp rbp, r15\njz loc_15E0\nloc_145D:\nmov rsi, rbx; s2\nmov rdi, r15; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1450\nmov eax, [rbx+64h]\nadd [r15+64h], eax\nadd rbx, 68h ; 'h'\nmov rax, [rsp+0C8h+var_C0]\ncmp rbx, rax\njnz short loc_144A\nloc_1481:\nmovdqu xmm6, xmmword ptr [r12]\nmovdqu xmm7, xmmword ptr [r12+10h]\nmovdqu xmm0, xmmword ptr [r12+40h]\nmovdqu xmm1, xmmword ptr [r12+50h]\nmov rax, [r12+60h]\nmovaps [rsp+0C8h+var_A8], xmm6\nmov ebx, [r12+64h]\nmovdqu xmm6, xmmword ptr [r12+20h]\nmovaps [rsp+0C8h+var_98], xmm7\nmovdqu xmm7, xmmword ptr [r12+30h]\nmov [rsp+0C8h+var_48], rax\nmovaps [rsp+0C8h+var_88], xmm6\nmovaps [rsp+0C8h+var_78], xmm7\nmovaps [rsp+0C8h+var_68], xmm0\nmovaps [rsp+0C8h+var_58], xmm1\ncmp r14d, 1\njle short loc_1559\nlea edx, [r14-2]\nlea rax, [r12+68h]\nlea rcx, [rdx+rdx*2]\nlea rdx, [rdx+rcx*4]\nlea rcx, [r12+rdx*8+0D0h]\nnop dword ptr [rax+00000000h]\nloc_1500:\nmov edx, [rax+64h]\ncmp edx, ebx\njle short loc_1550\nmov rsi, [rax+60h]\nmovdqu xmm0, xmmword ptr [rax]\nmov ebx, edx\nmovdqu xmm1, xmmword ptr [rax+10h]\nmovdqu xmm2, xmmword ptr [rax+20h]\nmovdqu xmm3, xmmword ptr [rax+30h]\nmovdqu xmm4, xmmword ptr [rax+40h]\nmov [rsp+0C8h+var_48], rsi\nmovdqu xmm5, xmmword ptr [rax+50h]\nmovaps [rsp+0C8h+var_A8], xmm0\nmovaps [rsp+0C8h+var_98], xmm1\nmovaps [rsp+0C8h+var_88], xmm2\nmovaps [rsp+0C8h+var_78], xmm3\nmovaps [rsp+0C8h+var_68], xmm4\nmovaps [rsp+0C8h+var_58], xmm5\nloc_1550:\nadd rax, 68h ; 'h'\ncmp rcx, rax\njnz short loc_1500\nloc_1559:\nmov rdi, r12; ptr\ncall _free\nmov rcx, [rsp+0C8h+var_B0]\nmovdqa xmm6, [rsp+0C8h+var_A8]\nmov dword ptr [rsp+0C8h+var_48+4], ebx\nmovdqa xmm7, [rsp+0C8h+var_98]\nmov rax, [rsp+0C8h+var_48]\nmovups xmmword ptr [rcx], xmm6\nmovdqa xmm6, [rsp+0C8h+var_88]\nmovups xmmword ptr [rcx+10h], xmm7\nmovdqa xmm7, [rsp+0C8h+var_78]\nmovups xmmword ptr [rcx+20h], xmm6\nmovdqa xmm6, [rsp+0C8h+var_68]\nmovups xmmword ptr [rcx+30h], xmm7\nmovdqa xmm7, [rsp+0C8h+var_58]\nmov [rcx+60h], rax\nmovups xmmword ptr [rcx+40h], xmm6\nmovups xmmword ptr [rcx+50h], xmm7\nmov rax, [rsp+0C8h+var_40]\nsub rax, fs:28h\njnz loc_168D\nadd rsp, 98h\nmov rax, rcx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15E0:\nlea rax, [r13+r13*2+0]\nmov rdx, [rsp+0C8h+var_B8]\nmov rsi, rbx\nlea rax, [r13+rax*4+0]\nshl rax, 3\ncmp rdx, rax\nlea rcx, [r12+rax]\ncmovb rdx, rax\nmov rdi, rcx\nsub rdx, rax\nmov eax, 64h ; 'd'\ncmp rdx, rax\ncmova rdx, rax\nadd rbx, 68h ; 'h'\nadd r14d, 1\ncall ___strcpy_chk\nmov rcx, rax\nmov eax, [rbx-4]\nmov [rcx+64h], eax\nmov rax, [rsp+0C8h+var_C0]\ncmp rbx, rax\njnz loc_1430\njmp loc_1481\nloc_163C:\nmovdqu xmm2, xmmword ptr [rax]\nmovdqu xmm3, xmmword ptr [rax+10h]\nmovdqu xmm4, xmmword ptr [rax+20h]\nmovdqu xmm5, xmmword ptr [rax+30h]\nmovaps [rsp+0C8h+var_A8], xmm2\nmovdqu xmm2, xmmword ptr [rax+40h]\nmov ebx, [r12+64h]\nmovaps [rsp+0C8h+var_98], xmm3\nmovdqu xmm3, xmmword ptr [rax+50h]\nmov rax, [rax+60h]\nmovaps [rsp+0C8h+var_88], xmm4\nmov [rsp+0C8h+var_48], rax\nmovaps [rsp+0C8h+var_78], xmm5\nmovaps [rsp+0C8h+var_68], xmm2\nmovaps [rsp+0C8h+var_58], xmm3\njmp loc_1559\nloc_168D:\ncall ___stack_chk_fail", + "ida_pseudo": "__m128i *__fastcall func0(__m128i *a1, __int64 a2, int a3)\n{\n __int64 v4; // rbx\n size_t v5; // r14\n const __m128i *v6; // rax\n __m128i *v7; // r12\n size_t v8; // rax\n int v9; // r14d\n __int64 v10; // r13\n __m128i *v11; // r15\n __int64 v12; // rax\n __int32 v13; // ebx\n const __m128i *v14; // rax\n __m128i v15; // xmm6\n __m128i v16; // xmm7\n __int64 v17; // rax\n __m128i v18; // xmm6\n __m128i v19; // xmm7\n __m128i v20; // xmm6\n __m128i v21; // xmm7\n __int64 v23; // rdx\n __int64 v24; // rsi\n __int8 *v25; // rcx\n unsigned __int64 v26; // rdx\n __m128i v27; // xmm4\n __m128i v28; // xmm5\n __m128i v29; // xmm2\n __m128i v30; // xmm3\n __int64 v31; // rax\n size_t v32; // [rsp+8h] [rbp-C0h]\n unsigned __int64 v33; // [rsp+10h] [rbp-B8h]\n __m128i v34; // [rsp+20h] [rbp-A8h] BYREF\n __m128i v35; // [rsp+30h] [rbp-98h] BYREF\n __m128i v36; // [rsp+40h] [rbp-88h] BYREF\n __m128i v37; // [rsp+50h] [rbp-78h] BYREF\n __m128i v38; // [rsp+60h] [rbp-68h] BYREF\n __m128i v39; // [rsp+70h] [rbp-58h] BYREF\n __int64 v40; // [rsp+80h] [rbp-48h]\n unsigned __int64 v41; // [rsp+88h] [rbp-40h]\n\n v4 = a2;\n v41 = __readfsqword(0x28u);\n v5 = 104LL * a3;\n v33 = v5;\n v6 = (const __m128i *)malloc(v5);\n v7 = (__m128i *)v6;\n if ( a3 <= 0 )\n {\n v27 = _mm_loadu_si128(v6 + 2);\n v28 = _mm_loadu_si128(v6 + 3);\n v34 = _mm_loadu_si128(v6);\n v29 = _mm_loadu_si128(v6 + 4);\n v13 = v6[6].m128i_i32[1];\n v35 = _mm_loadu_si128(v6 + 1);\n v30 = _mm_loadu_si128(v6 + 5);\n v31 = v6[6].m128i_i64[0];\n v36 = v27;\n v40 = v31;\n v37 = v28;\n v38 = v29;\n v39 = v30;\n }\n else\n {\n v8 = a2 + v5;\n v9 = 0;\n v32 = v8;\n while ( 1 )\n {\n v10 = v9;\n if ( v9 > 0 )\n break;\nLABEL_14:\n v23 = v33;\n v24 = v4;\n v25 = &v7->m128i_i8[104 * v9];\n if ( v33 < 104LL * v9 )\n v23 = 104LL * v9;\n v26 = v23 - 104LL * v9;\n if ( v26 > 0x64 )\n v26 = 100LL;\n v4 += 104LL;\n ++v9;\n *(_DWORD *)(__strcpy_chk((char *)v7 + 104 * v10, v24, v26, v25) + 100) = *(_DWORD *)(v4 - 4);\n if ( v4 == v32 )\n goto LABEL_8;\n }\n do\n {\n v11 = v7;\n while ( strcmp(v11->m128i_i8, (const char *)v4) )\n {\n v11 = (__m128i *)((char *)v11 + 104);\n if ( (__m128i *)((char *)v7 + 104 * v9) == v11 )\n goto LABEL_14;\n }\n v11[6].m128i_i32[1] += *(_DWORD *)(v4 + 100);\n v4 += 104LL;\n }\n while ( v4 != v32 );\nLABEL_8:\n v12 = v7[6].m128i_i64[0];\n v34 = _mm_loadu_si128(v7);\n v13 = v7[6].m128i_i32[1];\n v35 = _mm_loadu_si128(v7 + 1);\n v40 = v12;\n v36 = _mm_loadu_si128(v7 + 2);\n v37 = _mm_loadu_si128(v7 + 3);\n v38 = _mm_loadu_si128(v7 + 4);\n v39 = _mm_loadu_si128(v7 + 5);\n if ( v9 > 1 )\n {\n v14 = (__m128i *)((char *)v7 + 104);\n do\n {\n if ( v14[6].m128i_i32[1] > v13 )\n {\n v13 = v14[6].m128i_i32[1];\n v40 = v14[6].m128i_i64[0];\n v34 = _mm_loadu_si128(v14);\n v35 = _mm_loadu_si128(v14 + 1);\n v36 = _mm_loadu_si128(v14 + 2);\n v37 = _mm_loadu_si128(v14 + 3);\n v38 = _mm_loadu_si128(v14 + 4);\n v39 = _mm_loadu_si128(v14 + 5);\n }\n v14 = (const __m128i *)((char *)v14 + 104);\n }\n while ( (__m128i *)((char *)&v7[13] + 104 * (unsigned int)(v9 - 2)) != v14 );\n }\n }\n free(v7);\n v15 = _mm_load_si128(&v34);\n HIDWORD(v40) = v13;\n v16 = _mm_load_si128(&v35);\n v17 = v40;\n *a1 = v15;\n v18 = _mm_load_si128(&v36);\n a1[1] = v16;\n v19 = _mm_load_si128(&v37);\n a1[2] = v18;\n v20 = _mm_load_si128(&v38);\n a1[3] = v19;\n v21 = _mm_load_si128(&v39);\n a1[6].m128i_i64[0] = v17;\n a1[4] = v20;\n a1[5] = v21;\n return a1;\n}", + "ida_strip_asm": "sub_13C0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\nmov ebp, edx\npush rbx\nmov rbx, rsi\nsub rsp, 98h\nmov [rsp+0C8h+var_B0], rdi\nmov rax, fs:28h\nmov [rsp+0C8h+var_40], rax\nxor eax, eax\nmovsxd rax, edx\nlea rdx, [rax+rax*2]\nlea r15, [rax+rdx*4]\nlea r14, ds:0[r15*8]\nmov rdi, r14; size\nmov [rsp+0C8h+var_B8], r14\ncall _malloc\nmov r12, rax\ntest ebp, ebp\njle loc_163C\nlea rax, [rbx+r14]\nxor r14d, r14d\nmov [rsp+0C8h+var_C0], rax\nnop dword ptr [rax+00000000h]\nloc_1430:\nmovsxd r13, r14d\ntest r14d, r14d\njle loc_15E0\nlea rax, [r13+r13*2+0]\nlea rax, [r13+rax*4+0]\nlea rbp, [r12+rax*8]\nloc_144A:\nmov r15, r12\njmp short loc_145D\nloc_1450:\nadd r15, 68h ; 'h'\ncmp rbp, r15\njz loc_15E0\nloc_145D:\nmov rsi, rbx; s2\nmov rdi, r15; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1450\nmov eax, [rbx+64h]\nadd [r15+64h], eax\nadd rbx, 68h ; 'h'\nmov rax, [rsp+0C8h+var_C0]\ncmp rbx, rax\njnz short loc_144A\nloc_1481:\nmovdqu xmm6, xmmword ptr [r12]\nmovdqu xmm7, xmmword ptr [r12+10h]\nmovdqu xmm0, xmmword ptr [r12+40h]\nmovdqu xmm1, xmmword ptr [r12+50h]\nmov rax, [r12+60h]\nmovaps [rsp+0C8h+var_A8], xmm6\nmov ebx, [r12+64h]\nmovdqu xmm6, xmmword ptr [r12+20h]\nmovaps [rsp+0C8h+var_98], xmm7\nmovdqu xmm7, xmmword ptr [r12+30h]\nmov [rsp+0C8h+var_48], rax\nmovaps [rsp+0C8h+var_88], xmm6\nmovaps [rsp+0C8h+var_78], xmm7\nmovaps [rsp+0C8h+var_68], xmm0\nmovaps [rsp+0C8h+var_58], xmm1\ncmp r14d, 1\njle short loc_1559\nlea edx, [r14-2]\nlea rax, [r12+68h]\nlea rcx, [rdx+rdx*2]\nlea rdx, [rdx+rcx*4]\nlea rcx, [r12+rdx*8+0D0h]\nnop dword ptr [rax+00000000h]\nloc_1500:\nmov edx, [rax+64h]\ncmp edx, ebx\njle short loc_1550\nmov rsi, [rax+60h]\nmovdqu xmm0, xmmword ptr [rax]\nmov ebx, edx\nmovdqu xmm1, xmmword ptr [rax+10h]\nmovdqu xmm2, xmmword ptr [rax+20h]\nmovdqu xmm3, xmmword ptr [rax+30h]\nmovdqu xmm4, xmmword ptr [rax+40h]\nmov [rsp+0C8h+var_48], rsi\nmovdqu xmm5, xmmword ptr [rax+50h]\nmovaps [rsp+0C8h+var_A8], xmm0\nmovaps [rsp+0C8h+var_98], xmm1\nmovaps [rsp+0C8h+var_88], xmm2\nmovaps [rsp+0C8h+var_78], xmm3\nmovaps [rsp+0C8h+var_68], xmm4\nmovaps [rsp+0C8h+var_58], xmm5\nloc_1550:\nadd rax, 68h ; 'h'\ncmp rcx, rax\njnz short loc_1500\nloc_1559:\nmov rdi, r12; ptr\ncall _free\nmov rcx, [rsp+0C8h+var_B0]\nmovdqa xmm6, [rsp+0C8h+var_A8]\nmov dword ptr [rsp+0C8h+var_48+4], ebx\nmovdqa xmm7, [rsp+0C8h+var_98]\nmov rax, [rsp+0C8h+var_48]\nmovups xmmword ptr [rcx], xmm6\nmovdqa xmm6, [rsp+0C8h+var_88]\nmovups xmmword ptr [rcx+10h], xmm7\nmovdqa xmm7, [rsp+0C8h+var_78]\nmovups xmmword ptr [rcx+20h], xmm6\nmovdqa xmm6, [rsp+0C8h+var_68]\nmovups xmmword ptr [rcx+30h], xmm7\nmovdqa xmm7, [rsp+0C8h+var_58]\nmov [rcx+60h], rax\nmovups xmmword ptr [rcx+40h], xmm6\nmovups xmmword ptr [rcx+50h], xmm7\nmov rax, [rsp+0C8h+var_40]\nsub rax, fs:28h\njnz loc_168D\nadd rsp, 98h\nmov rax, rcx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15E0:\nlea rax, [r13+r13*2+0]\nmov rdx, [rsp+0C8h+var_B8]\nmov rsi, rbx\nlea rax, [r13+rax*4+0]\nshl rax, 3\ncmp rdx, rax\nlea rcx, [r12+rax]\ncmovb rdx, rax\nmov rdi, rcx\nsub rdx, rax\nmov eax, 64h ; 'd'\ncmp rdx, rax\ncmova rdx, rax\nadd rbx, 68h ; 'h'\nadd r14d, 1\ncall ___strcpy_chk\nmov rcx, rax\nmov eax, [rbx-4]\nmov [rcx+64h], eax\nmov rax, [rsp+0C8h+var_C0]\ncmp rbx, rax\njnz loc_1430\njmp loc_1481\nloc_163C:\nmovdqu xmm2, xmmword ptr [rax]\nmovdqu xmm3, xmmword ptr [rax+10h]\nmovdqu xmm4, xmmword ptr [rax+20h]\nmovdqu xmm5, xmmword ptr [rax+30h]\nmovaps [rsp+0C8h+var_A8], xmm2\nmovdqu xmm2, xmmword ptr [rax+40h]\nmov ebx, [r12+64h]\nmovaps [rsp+0C8h+var_98], xmm3\nmovdqu xmm3, xmmword ptr [rax+50h]\nmov rax, [rax+60h]\nmovaps [rsp+0C8h+var_88], xmm4\nmov [rsp+0C8h+var_48], rax\nmovaps [rsp+0C8h+var_78], xmm5\nmovaps [rsp+0C8h+var_68], xmm2\nmovaps [rsp+0C8h+var_58], xmm3\njmp loc_1559\nloc_168D:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__m128i *__fastcall sub_13C0(__m128i *a1, __int64 a2, int a3)\n{\n __int64 v4; // rbx\n size_t v5; // r14\n const __m128i *v6; // rax\n __m128i *v7; // r12\n size_t v8; // rax\n int v9; // r14d\n __int64 v10; // r13\n __m128i *v11; // r15\n __int64 v12; // rax\n __int32 v13; // ebx\n const __m128i *v14; // rax\n __m128i v15; // xmm6\n __m128i v16; // xmm7\n __int64 v17; // rax\n __m128i v18; // xmm6\n __m128i v19; // xmm7\n __m128i v20; // xmm6\n __m128i v21; // xmm7\n __int64 v23; // rdx\n __int64 v24; // rsi\n __int8 *v25; // rcx\n unsigned __int64 v26; // rdx\n __m128i v27; // xmm4\n __m128i v28; // xmm5\n __m128i v29; // xmm2\n __m128i v30; // xmm3\n __int64 v31; // rax\n size_t v32; // [rsp+8h] [rbp-C0h]\n unsigned __int64 v33; // [rsp+10h] [rbp-B8h]\n __m128i v34; // [rsp+20h] [rbp-A8h] BYREF\n __m128i v35; // [rsp+30h] [rbp-98h] BYREF\n __m128i v36; // [rsp+40h] [rbp-88h] BYREF\n __m128i v37; // [rsp+50h] [rbp-78h] BYREF\n __m128i v38; // [rsp+60h] [rbp-68h] BYREF\n __m128i v39; // [rsp+70h] [rbp-58h] BYREF\n __int64 v40; // [rsp+80h] [rbp-48h]\n unsigned __int64 v41; // [rsp+88h] [rbp-40h]\n\n v4 = a2;\n v41 = __readfsqword(0x28u);\n v5 = 104LL * a3;\n v33 = v5;\n v6 = (const __m128i *)malloc(v5);\n v7 = (__m128i *)v6;\n if ( a3 <= 0 )\n {\n v27 = _mm_loadu_si128(v6 + 2);\n v28 = _mm_loadu_si128(v6 + 3);\n v34 = _mm_loadu_si128(v6);\n v29 = _mm_loadu_si128(v6 + 4);\n v13 = v6[6].m128i_i32[1];\n v35 = _mm_loadu_si128(v6 + 1);\n v30 = _mm_loadu_si128(v6 + 5);\n v31 = v6[6].m128i_i64[0];\n v36 = v27;\n v40 = v31;\n v37 = v28;\n v38 = v29;\n v39 = v30;\n }\n else\n {\n v8 = a2 + v5;\n v9 = 0;\n v32 = v8;\n while ( 1 )\n {\n v10 = v9;\n if ( v9 > 0 )\n break;\nLABEL_14:\n v23 = v33;\n v24 = v4;\n v25 = &v7->m128i_i8[104 * v9];\n if ( v33 < 104LL * v9 )\n v23 = 104LL * v9;\n v26 = v23 - 104LL * v9;\n if ( v26 > 0x64 )\n v26 = 100LL;\n v4 += 104LL;\n ++v9;\n *(_DWORD *)(__strcpy_chk((char *)v7 + 104 * v10, v24, v26, v25) + 100) = *(_DWORD *)(v4 - 4);\n if ( v4 == v32 )\n goto LABEL_8;\n }\n do\n {\n v11 = v7;\n while ( strcmp(v11->m128i_i8, (const char *)v4) )\n {\n v11 = (__m128i *)((char *)v11 + 104);\n if ( (__m128i *)((char *)v7 + 104 * v9) == v11 )\n goto LABEL_14;\n }\n v11[6].m128i_i32[1] += *(_DWORD *)(v4 + 100);\n v4 += 104LL;\n }\n while ( v4 != v32 );\nLABEL_8:\n v12 = v7[6].m128i_i64[0];\n v34 = _mm_loadu_si128(v7);\n v13 = v7[6].m128i_i32[1];\n v35 = _mm_loadu_si128(v7 + 1);\n v40 = v12;\n v36 = _mm_loadu_si128(v7 + 2);\n v37 = _mm_loadu_si128(v7 + 3);\n v38 = _mm_loadu_si128(v7 + 4);\n v39 = _mm_loadu_si128(v7 + 5);\n if ( v9 > 1 )\n {\n v14 = (__m128i *)((char *)v7 + 104);\n do\n {\n if ( v14[6].m128i_i32[1] > v13 )\n {\n v13 = v14[6].m128i_i32[1];\n v40 = v14[6].m128i_i64[0];\n v34 = _mm_loadu_si128(v14);\n v35 = _mm_loadu_si128(v14 + 1);\n v36 = _mm_loadu_si128(v14 + 2);\n v37 = _mm_loadu_si128(v14 + 3);\n v38 = _mm_loadu_si128(v14 + 4);\n v39 = _mm_loadu_si128(v14 + 5);\n }\n v14 = (const __m128i *)((char *)v14 + 104);\n }\n while ( (__m128i *)((char *)&v7[13] + 104 * (unsigned int)(v9 - 2)) != v14 );\n }\n }\n free(v7);\n v15 = _mm_load_si128(&v34);\n HIDWORD(v40) = v13;\n v16 = _mm_load_si128(&v35);\n v17 = v40;\n *a1 = v15;\n v18 = _mm_load_si128(&v36);\n a1[1] = v16;\n v19 = _mm_load_si128(&v37);\n a1[2] = v18;\n v20 = _mm_load_si128(&v38);\n a1[3] = v19;\n v21 = _mm_load_si128(&v39);\n a1[6].m128i_i64[0] = v17;\n a1[4] = v20;\n a1[5] = v21;\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__m128i *sub_13C0(__m128i *a1, long long a2, int a3) {\n long long v4;\n unsigned int v5;\n const __m128i *v6;\n __m128i *v7;\n unsigned int v8;\n int v9;\n long long v10;\n __m128i *v11;\n long long v12;\n int v13;\n const __m128i *v14;\n __m128i v15;\n __m128i v16;\n long long v17;\n __m128i v18;\n __m128i v19;\n __m128i v20;\n __m128i v21;\n long long v23;\n long long v24;\n char *v25;\n unsigned long long v26;\n __m128i v27;\n __m128i v28;\n __m128i v29;\n __m128i v30;\n long long v31;\n unsigned int v32;\n unsigned long long v33;\n __m128i v34;\n __m128i v35;\n __m128i v36;\n __m128i v37;\n __m128i v38;\n __m128i v39;\n long long v40;\n unsigned long long v41;\n v4 = a2;\n v41 = __readfsqword(40u);\n v5 = 104LL * a3;\n v33 = v5;\n v6 = (const __m128i *)malloc(v5);\n v7 = (__m128i *)v6;\n if (a3 <= 0) {\n v27 = _mm_loadu_si128(v6 + 2);\n v28 = _mm_loadu_si128(v6 + 3);\n v34 = _mm_loadu_si128(v6);\n v29 = _mm_loadu_si128(v6 + 4);\n v13 = v6[6].m128i_i32[1];\n v35 = _mm_loadu_si128(v6 + 1);\n v30 = _mm_loadu_si128(v6 + 5);\n v31 = v6[6].m128i_i64[0];\n v36 = v27;\n v40 = v31;\n v37 = v28;\n v38 = v29;\n v39 = v30;\n } else {\n v8 = a2 + v5;\n v9 = 0;\n v32 = v8;\n while (1) {\n v10 = v9;\n if (v9 > 0) break;\n LABEL_14:\n v23 = v33;\n v24 = v4;\n v25 = &v7->m128i_i8[104 * v9];\n if (v33 < 104LL * v9) v23 = 104LL * v9;\n v26 = v23 - 104LL * v9;\n if (v26 > 100) v26 = 100LL;\n v4 += 104LL;\n ++v9;\n *(uint32_t *)(__strcpy_chk((char *)v7 + 104 * v10, v24, v26, v25) + 100) =\n *(uint32_t *)(v4 - 4);\n if (v4 == v32) goto LABEL_8;\n }\n do {\n v11 = v7;\n while (strcmp(v11->m128i_i8, (const char *)v4)) {\n v11 = (__m128i *)((char *)v11 + 104);\n if ((__m128i *)((char *)v7 + 104 * v9) == v11) goto LABEL_14;\n }\n v11[6].m128i_i32[1] += *(uint32_t *)(v4 + 100);\n v4 += 104LL;\n } while (v4 != v32);\n LABEL_8:\n v12 = v7[6].m128i_i64[0];\n v34 = _mm_loadu_si128(v7);\n v13 = v7[6].m128i_i32[1];\n v35 = _mm_loadu_si128(v7 + 1);\n v40 = v12;\n v36 = _mm_loadu_si128(v7 + 2);\n v37 = _mm_loadu_si128(v7 + 3);\n v38 = _mm_loadu_si128(v7 + 4);\n v39 = _mm_loadu_si128(v7 + 5);\n if (v9 > 1) {\n v14 = (__m128i *)((char *)v7 + 104);\n do {\n if (v14[6].m128i_i32[1] > v13) {\n v13 = v14[6].m128i_i32[1];\n v40 = v14[6].m128i_i64[0];\n v34 = _mm_loadu_si128(v14);\n v35 = _mm_loadu_si128(v14 + 1);\n v36 = _mm_loadu_si128(v14 + 2);\n v37 = _mm_loadu_si128(v14 + 3);\n v38 = _mm_loadu_si128(v14 + 4);\n v39 = _mm_loadu_si128(v14 + 5);\n }\n v14 = (const __m128i *)((char *)v14 + 104);\n } while ((__m128i *)((char *)&v7[13] + 104 * (unsigned int)(v9 - 2)) !=\n v14);\n }\n }\n free(v7);\n v15 = _mm_load_si128(&v34);\n HIDWORD(v40) = v13;\n v16 = _mm_load_si128(&v35);\n v17 = v40;\n *a1 = v15;\n v18 = _mm_load_si128(&v36);\n a1[1] = v16;\n v19 = _mm_load_si128(&v37);\n a1[2] = v18;\n v20 = _mm_load_si128(&v38);\n a1[3] = v19;\n v21 = _mm_load_si128(&v39);\n a1[6].m128i_i64[0] = v17;\n a1[4] = v20;\n a1[5] = v21;\n return a1;\n}", + "ida_pseudo_norm": "__m128i *func0(__m128i *a1, long long a2, int a3) {\n long long v4;\n unsigned int v5;\n const __m128i *v6;\n __m128i *v7;\n unsigned int v8;\n int v9;\n long long v10;\n __m128i *v11;\n long long v12;\n int v13;\n const __m128i *v14;\n __m128i v15;\n __m128i v16;\n long long v17;\n __m128i v18;\n __m128i v19;\n __m128i v20;\n __m128i v21;\n long long v23;\n long long v24;\n char *v25;\n unsigned long long v26;\n __m128i v27;\n __m128i v28;\n __m128i v29;\n __m128i v30;\n long long v31;\n unsigned int v32;\n unsigned long long v33;\n __m128i v34;\n __m128i v35;\n __m128i v36;\n __m128i v37;\n __m128i v38;\n __m128i v39;\n long long v40;\n unsigned long long v41;\n v4 = a2;\n v41 = __readfsqword(40u);\n v5 = 104LL * a3;\n v33 = v5;\n v6 = (const __m128i *)malloc(v5);\n v7 = (__m128i *)v6;\n if (a3 <= 0) {\n v27 = _mm_loadu_si128(v6 + 2);\n v28 = _mm_loadu_si128(v6 + 3);\n v34 = _mm_loadu_si128(v6);\n v29 = _mm_loadu_si128(v6 + 4);\n v13 = v6[6].m128i_i32[1];\n v35 = _mm_loadu_si128(v6 + 1);\n v30 = _mm_loadu_si128(v6 + 5);\n v31 = v6[6].m128i_i64[0];\n v36 = v27;\n v40 = v31;\n v37 = v28;\n v38 = v29;\n v39 = v30;\n } else {\n v8 = a2 + v5;\n v9 = 0;\n v32 = v8;\n while (1) {\n v10 = v9;\n if (v9 > 0) break;\n LABEL_14:\n v23 = v33;\n v24 = v4;\n v25 = &v7->m128i_i8[104 * v9];\n if (v33 < 104LL * v9) v23 = 104LL * v9;\n v26 = v23 - 104LL * v9;\n if (v26 > 100) v26 = 100LL;\n v4 += 104LL;\n ++v9;\n *(uint32_t *)(__strcpy_chk((char *)v7 + 104 * v10, v24, v26, v25) + 100) =\n *(uint32_t *)(v4 - 4);\n if (v4 == v32) goto LABEL_8;\n }\n do {\n v11 = v7;\n while (strcmp(v11->m128i_i8, (const char *)v4)) {\n v11 = (__m128i *)((char *)v11 + 104);\n if ((__m128i *)((char *)v7 + 104 * v9) == v11) goto LABEL_14;\n }\n v11[6].m128i_i32[1] += *(uint32_t *)(v4 + 100);\n v4 += 104LL;\n } while (v4 != v32);\n LABEL_8:\n v12 = v7[6].m128i_i64[0];\n v34 = _mm_loadu_si128(v7);\n v13 = v7[6].m128i_i32[1];\n v35 = _mm_loadu_si128(v7 + 1);\n v40 = v12;\n v36 = _mm_loadu_si128(v7 + 2);\n v37 = _mm_loadu_si128(v7 + 3);\n v38 = _mm_loadu_si128(v7 + 4);\n v39 = _mm_loadu_si128(v7 + 5);\n if (v9 > 1) {\n v14 = (__m128i *)((char *)v7 + 104);\n do {\n if (v14[6].m128i_i32[1] > v13) {\n v13 = v14[6].m128i_i32[1];\n v40 = v14[6].m128i_i64[0];\n v34 = _mm_loadu_si128(v14);\n v35 = _mm_loadu_si128(v14 + 1);\n v36 = _mm_loadu_si128(v14 + 2);\n v37 = _mm_loadu_si128(v14 + 3);\n v38 = _mm_loadu_si128(v14 + 4);\n v39 = _mm_loadu_si128(v14 + 5);\n }\n v14 = (const __m128i *)((char *)v14 + 104);\n } while ((__m128i *)((char *)&v7[13] + 104 * (unsigned int)(v9 - 2)) !=\n v14);\n }\n }\n free(v7);\n v15 = _mm_load_si128(&v34);\n HIDWORD(v40) = v13;\n v16 = _mm_load_si128(&v35);\n v17 = v40;\n *a1 = v15;\n v18 = _mm_load_si128(&v36);\n a1[1] = v16;\n v19 = _mm_load_si128(&v37);\n a1[2] = v18;\n v20 = _mm_load_si128(&v38);\n a1[3] = v19;\n v21 = _mm_load_si128(&v39);\n a1[6].m128i_i64[0] = v17;\n a1[4] = v20;\n a1[5] = v21;\n return a1;\n}" + }, + { + "index": 300, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int n) {\n double nCr = 1;\n double res = 1;\n for (int r = 1; r <= n; r++) {\n nCr = (nCr * (n + 1 - r)) / r;\n res += nCr * nCr;\n }\n return res;\n}", + "test": "int main() {\n\n assert(func0(1) == 2.0);\n\n assert(func0(2) == 6.0);\n\n assert(func0(3) == 20.0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x24(%rbp)\nmovsd 0xf24(%rip),%xmm0\nmovsd %xmm0,-0x10(%rbp)\nmovsd 0xf17(%rip),%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmovl $0x1,-0x14(%rbp)\njmp 11b2 \nmov -0x24(%rbp),%eax\nadd $0x1,%eax\nsub -0x14(%rbp),%eax\ncvtsi2sd %eax,%xmm0\nmulsd -0x10(%rbp),%xmm0\ncvtsi2sdl -0x14(%rbp),%xmm1\ndivsd %xmm1,%xmm0\nmovsd %xmm0,-0x10(%rbp)\nmovsd -0x10(%rbp),%xmm0\nmulsd %xmm0,%xmm0\nmovsd -0x8(%rbp),%xmm1\naddsd %xmm1,%xmm0\nmovsd %xmm0,-0x8(%rbp)\naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\ncmp -0x24(%rbp),%eax\njle 1177 \nmovsd -0x8(%rbp),%xmm0\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_24], edi\nmovsd xmm0, cs:qword_2060\nmovsd [rbp+var_10], xmm0\nmovsd xmm0, cs:qword_2060\nmovsd [rbp+var_8], xmm0\nmov [rbp+var_14], 1\njmp short loc_11BA\nloc_1177:\nmov eax, [rbp+var_24]\nadd eax, 1\nsub eax, [rbp+var_14]\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmulsd xmm0, [rbp+var_10]\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_14]\ndivsd xmm0, xmm1\nmovsd [rbp+var_10], xmm0\nmovsd xmm0, [rbp+var_10]\nmulsd xmm0, xmm0\nmovsd xmm1, [rbp+var_8]\naddsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nadd [rbp+var_14], 1\nloc_11BA:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_24]\njle short loc_1177\nmovsd xmm0, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "double __fastcall func0(int a1)\n{\n int i; // [rsp+10h] [rbp-14h]\n double v3; // [rsp+14h] [rbp-10h]\n double v4; // [rsp+1Ch] [rbp-8h]\n\n v3 = 1.0;\n v4 = 1.0;\n for ( i = 1; i <= a1; ++i )\n {\n v3 = (double)(a1 + 1 - i) * v3 / (double)i;\n v4 = v3 * v3 + v4;\n }\n return v4;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_24], edi\nmovsd xmm0, cs:qword_2060\nmovsd [rbp+var_10], xmm0\nmovsd xmm0, cs:qword_2060\nmovsd [rbp+var_8], xmm0\nmov [rbp+var_14], 1\njmp short loc_11BA\nloc_1177:\nmov eax, [rbp+var_24]\nadd eax, 1\nsub eax, [rbp+var_14]\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmulsd xmm0, [rbp+var_10]\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_14]\ndivsd xmm0, xmm1\nmovsd [rbp+var_10], xmm0\nmovsd xmm0, [rbp+var_10]\nmulsd xmm0, xmm0\nmovsd xmm1, [rbp+var_8]\naddsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nadd [rbp+var_14], 1\nloc_11BA:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_24]\njle short loc_1177\nmovsd xmm0, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "double __fastcall sub_1149(int a1)\n{\n int i; // [rsp+10h] [rbp-14h]\n double v3; // [rsp+14h] [rbp-10h]\n double v4; // [rsp+1Ch] [rbp-8h]\n\n v3 = 1.0;\n v4 = 1.0;\n for ( i = 1; i <= a1; ++i )\n {\n v3 = (double)(a1 + 1 - i) * v3 / (double)i;\n v4 = v3 * v3 + v4;\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1149(int a1) {\n int i;\n double v3;\n double v4;\n v3 = 1.0;\n v4 = 1.0;\n for (i = 1; i <= a1; ++i) {\n v3 = (double)(a1 + 1 - i) * v3 / (double)i;\n v4 = v3 * v3 + v4;\n }\n return v4;\n}", + "ida_pseudo_norm": "double func0(int a1) {\n int i;\n double v3;\n double v4;\n v3 = 1.0;\n v4 = 1.0;\n for (i = 1; i <= a1; ++i) {\n v3 = (double)(a1 + 1 - i) * v3 / (double)i;\n v4 = v3 * v3 + v4;\n }\n return v4;\n}" + }, + { + "index": 300, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int n) {\n double nCr = 1;\n double res = 1;\n for (int r = 1; r <= n; r++) {\n nCr = (nCr * (n + 1 - r)) / r;\n res += nCr * nCr;\n }\n return res;\n}", + "test": "int main() {\n\n assert(func0(1) == 2.0);\n\n assert(func0(2) == 6.0);\n\n assert(func0(3) == 20.0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\njle 119b \nadd $0x1,%edi\nmov %edi,%ecx\nmov $0x1,%eax\nmovsd 0xf1d(%rip),%xmm2\nmovapd %xmm2,%xmm0\nmov %edi,%edx\nsub %eax,%edx\npxor %xmm1,%xmm1\ncvtsi2sd %edx,%xmm1\nmulsd %xmm1,%xmm0\npxor %xmm1,%xmm1\ncvtsi2sd %eax,%xmm1\ndivsd %xmm1,%xmm0\nmovapd %xmm0,%xmm1\nmulsd %xmm0,%xmm1\naddsd %xmm1,%xmm2\nadd $0x1,%eax\ncmp %ecx,%eax\njne 1167 \nmovapd %xmm2,%xmm0\nretq\nmovsd 0xedd(%rip),%xmm2\njmp 1196 \n", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njle short loc_1199\nadd edi, 1\nmov eax, 1\nmovsd xmm1, cs:qword_2060\nmovapd xmm0, xmm1\nloc_1165:\nmov edx, edi\nsub edx, eax\npxor xmm2, xmm2\ncvtsi2sd xmm2, edx\nmulsd xmm0, xmm2\npxor xmm2, xmm2\ncvtsi2sd xmm2, eax\ndivsd xmm0, xmm2\nmovapd xmm2, xmm0\nmulsd xmm2, xmm0\naddsd xmm1, xmm2\nadd eax, 1\ncmp eax, edi\njnz short loc_1165\nloc_1194:\nmovapd xmm0, xmm1\nretn\nloc_1199:\nmovsd xmm1, cs:qword_2060\njmp short loc_1194", + "ida_pseudo": "__int128 __usercall func0@(int a1@)\n{\n int v1; // edi\n int v2; // eax\n __int128 v3; // xmm1\n double v4; // xmm0_8\n\n if ( a1 <= 0 )\n return 0x3FF0000000000000uLL;\n v1 = a1 + 1;\n v2 = 1;\n v3 = 0x3FF0000000000000uLL;\n v4 = 1.0;\n do\n {\n v4 = v4 * (double)(v1 - v2) / (double)v2;\n *(double *)&v3 = *(double *)&v3 + v4 * v4;\n ++v2;\n }\n while ( v2 != v1 );\n return v3;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ntest edi, edi\njle short loc_1199\nadd edi, 1\nmov eax, 1\nmovsd xmm1, cs:qword_2060\nmovapd xmm0, xmm1\nloc_1165:\nmov edx, edi\nsub edx, eax\npxor xmm2, xmm2\ncvtsi2sd xmm2, edx\nmulsd xmm0, xmm2\npxor xmm2, xmm2\ncvtsi2sd xmm2, eax\ndivsd xmm0, xmm2\nmovapd xmm2, xmm0\nmulsd xmm2, xmm0\naddsd xmm1, xmm2\nadd eax, 1\ncmp eax, edi\njnz short loc_1165\nloc_1194:\nmovapd xmm0, xmm1\nretn\nloc_1199:\nmovsd xmm1, cs:qword_2060\njmp short loc_1194", + "ida_strip_pseudo": "__int128 __usercall sub_1149@(int a1@)\n{\n int v1; // edi\n int v2; // eax\n __int128 v3; // xmm1\n double v4; // xmm0_8\n\n if ( a1 <= 0 )\n return 0x3FF0000000000000uLL;\n v1 = a1 + 1;\n v2 = 1;\n v3 = 0x3FF0000000000000uLL;\n v4 = 1.0;\n do\n {\n v4 = v4 * (double)(v1 - v2) / (double)v2;\n *(double *)&v3 = *(double *)&v3 + v4 * v4;\n ++v2;\n }\n while ( v2 != v1 );\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__int128 __usercall sub_1149 @(int a1 @) {\n int v1;\n int v2;\n __int128 v3;\n double v4;\n if (a1 <= 0) return 4607182418800017408uLL;\n v1 = a1 + 1;\n v2 = 1;\n v3 = 4607182418800017408uLL;\n v4 = 1.0;\n do {\n v4 = v4 * (double)(v1 - v2) / (double)v2;\n *(double *)&v3 = *(double *)&v3 + v4 * v4;\n ++v2;\n } while (v2 != v1);\n return v3;\n}", + "ida_pseudo_norm": "__int128 __usercall func0 @(int a1 @) {\n int v1;\n int v2;\n __int128 v3;\n double v4;\n if (a1 <= 0) return 4607182418800017408uLL;\n v1 = a1 + 1;\n v2 = 1;\n v3 = 4607182418800017408uLL;\n v4 = 1.0;\n do {\n v4 = v4 * (double)(v1 - v2) / (double)v2;\n *(double *)&v3 = *(double *)&v3 + v4 * v4;\n ++v2;\n } while (v2 != v1);\n return v3;\n}" + }, + { + "index": 300, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int n) {\n double nCr = 1;\n double res = 1;\n for (int r = 1; r <= n; r++) {\n nCr = (nCr * (n + 1 - r)) / r;\n res += nCr * nCr;\n }\n return res;\n}", + "test": "int main() {\n\n assert(func0(1) == 2.0);\n\n assert(func0(2) == 6.0);\n\n assert(func0(3) == 20.0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\njle 1198 \nmovsd 0xeb8(%rip),%xmm2\nadd $0x1,%edi\nmov $0x1,%eax\nmovapd %xmm2,%xmm0\nnopl 0x0(%rax)\nmov %edi,%edx\npxor %xmm1,%xmm1\nsub %eax,%edx\ncvtsi2sd %edx,%xmm1\nmulsd %xmm1,%xmm0\npxor %xmm1,%xmm1\ncvtsi2sd %eax,%xmm1\nadd $0x1,%eax\ndivsd %xmm1,%xmm0\nmovapd %xmm0,%xmm1\nmulsd %xmm0,%xmm1\naddsd %xmm1,%xmm2\ncmp %edi,%eax\njne 1160 \nmovapd %xmm2,%xmm0\nretq\nnopl 0x0(%rax)\nmovsd 0xe68(%rip),%xmm2\nmovapd %xmm2,%xmm0\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njle short loc_1258\nmovsd xmm1, cs:qword_2060\nadd edi, 1\nmov eax, 1\nmovapd xmm0, xmm1\nnop dword ptr [rax+00h]\nloc_1220:\nmov edx, edi\npxor xmm2, xmm2\nsub edx, eax\ncvtsi2sd xmm2, edx\nmulsd xmm0, xmm2\npxor xmm2, xmm2\ncvtsi2sd xmm2, eax\nadd eax, 1\ndivsd xmm0, xmm2\nmovapd xmm2, xmm0\nmulsd xmm2, xmm0\naddsd xmm1, xmm2\ncmp edi, eax\njnz short loc_1220\nmovapd xmm0, xmm1\nretn\nloc_1258:\nmovsd xmm1, cs:qword_2060\nmovapd xmm0, xmm1\nretn", + "ida_pseudo": "double __fastcall func0(int a1)\n{\n double v1; // xmm1_8\n int v2; // edi\n int v3; // eax\n double v4; // xmm0_8\n int v5; // edx\n double v6; // xmm2_8\n\n if ( a1 <= 0 )\n return 1.0;\n v1 = 1.0;\n v2 = a1 + 1;\n v3 = 1;\n v4 = 1.0;\n do\n {\n v5 = v2 - v3;\n v6 = (double)v3++;\n v4 = v4 * (double)v5 / v6;\n v1 = v1 + v4 * v4;\n }\n while ( v2 != v3 );\n return v1;\n}", + "ida_strip_asm": "sub_1200:\nendbr64\ntest edi, edi\njle short loc_1258\nmovsd xmm1, cs:qword_2060\nadd edi, 1\nmov eax, 1\nmovapd xmm0, xmm1\nnop dword ptr [rax+00h]\nloc_1220:\nmov edx, edi\npxor xmm2, xmm2\nsub edx, eax\ncvtsi2sd xmm2, edx\nmulsd xmm0, xmm2\npxor xmm2, xmm2\ncvtsi2sd xmm2, eax\nadd eax, 1\ndivsd xmm0, xmm2\nmovapd xmm2, xmm0\nmulsd xmm2, xmm0\naddsd xmm1, xmm2\ncmp edi, eax\njnz short loc_1220\nmovapd xmm0, xmm1\nretn\nloc_1258:\nmovsd xmm1, cs:qword_2060\nmovapd xmm0, xmm1\nretn", + "ida_strip_pseudo": "double __fastcall sub_1200(int a1)\n{\n double v1; // xmm1_8\n int v2; // edi\n int v3; // eax\n double v4; // xmm0_8\n int v5; // edx\n double v6; // xmm2_8\n\n if ( a1 <= 0 )\n return 1.0;\n v1 = 1.0;\n v2 = a1 + 1;\n v3 = 1;\n v4 = 1.0;\n do\n {\n v5 = v2 - v3;\n v6 = (double)v3++;\n v4 = v4 * (double)v5 / v6;\n v1 = v1 + v4 * v4;\n }\n while ( v2 != v3 );\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1200(int a1) {\n double v1;\n int v2;\n int v3;\n double v4;\n int v5;\n double v6;\n if (a1 <= 0) return 1.0;\n v1 = 1.0;\n v2 = a1 + 1;\n v3 = 1;\n v4 = 1.0;\n do {\n v5 = v2 - v3;\n v6 = (double)v3++;\n v4 = v4 * (double)v5 / v6;\n v1 = v1 + v4 * v4;\n } while (v2 != v3);\n return v1;\n}", + "ida_pseudo_norm": "double func0(int a1) {\n double v1;\n int v2;\n int v3;\n double v4;\n int v5;\n double v6;\n if (a1 <= 0) return 1.0;\n v1 = 1.0;\n v2 = a1 + 1;\n v3 = 1;\n v4 = 1.0;\n do {\n v5 = v2 - v3;\n v6 = (double)v3++;\n v4 = v4 * (double)v5 / v6;\n v1 = v1 + v4 * v4;\n } while (v2 != v3);\n return v1;\n}" + }, + { + "index": 301, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\ntypedef struct Dict Dict;\n\ntypedef struct DictEntry DictEntry;\n\n\n\nstruct DictEntry {\n\n char *key;\n\n Dict *value; // NULL if not a dict\n\n};\n\n\n\nstruct Dict {\n\n int size;\n\n DictEntry *entries;\n\n};\n\n\n\n", + "func": "int func0(Dict *d) {\n if (d == NULL) return 0;\n if (d->size == 0) return 1;\n int max_depth = 0;\n for (int i = 0; i < d->size; i++) {\n int depth = func0(d->entries[i].value);\n if (depth > max_depth) max_depth = depth;\n }\n return 1 + max_depth;\n}", + "test": "int main() {\n\n // First assert: {'a':1, 'b': {'c': {'d': {}}}} == 4\n\n Dict d_inner_most = {0, NULL};\n\n DictEntry entries_c[] = { {\"d\", &d_inner_most} };\n\n Dict dict_c = {1, entries_c};\n\n DictEntry entries_b[] = { {\"c\", &dict_c} };\n\n Dict dict_b = {1, entries_b};\n\n DictEntry entries_a_b[] = { {\"a\", NULL}, {\"b\", &dict_b} };\n\n Dict dict1 = {2, entries_a_b};\n\n assert(func0(&dict1) == 4);\n\n\n\n // Second assert: {'a':1, 'b': {'c':'python'}} == 2\n\n DictEntry entries_b2[] = { {\"c\", NULL} };\n\n Dict dict_b2 = {1, entries_b2};\n\n DictEntry entries_a_b2[] = { {\"a\", NULL}, {\"b\", &dict_b2} };\n\n Dict dict2 = {2, entries_a_b2};\n\n assert(func0(&dict2) == 2);\n\n\n\n // Third assert: {1: 'Sun', 2: {3: {4:'Mon'}}} == 3\n\n Dict d_inner3 = {1, (DictEntry[]) { {\"4\", NULL} }};\n\n Dict dict3_inner = {1, (DictEntry[]) { {\"3\", &d_inner3} }};\n\n Dict dict3 = {2, (DictEntry[]) { {\"1\", NULL}, {\"2\", &dict3_inner} }};\n\n assert(func0(&dict3) == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\ncmpq $0x0,-0x18(%rbp)\njne 1187 \nmov $0x0,%eax\njmp 11ef \nmov -0x18(%rbp),%rax\nmov (%rax),%eax\ntest %eax,%eax\njne 1198 \nmov $0x1,%eax\njmp 11ef \nmovl $0x0,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11de \nmov -0x18(%rbp),%rax\nmov 0x8(%rax),%rax\nmov -0x8(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x4,%rdx\nadd %rdx,%rax\nmov 0x8(%rax),%rax\nmov %rax,%rdi\ncallq 1169 \nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0xc(%rbp),%eax\njle 11da \nmov -0x4(%rbp),%eax\nmov %eax,-0xc(%rbp)\naddl $0x1,-0x8(%rbp)\nmov -0x18(%rbp),%rax\nmov (%rax),%eax\ncmp %eax,-0x8(%rbp)\njl 11a8 \nmov -0xc(%rbp),%eax\nadd $0x1,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\ncmp [rbp+var_18], 0\njnz short loc_1187\nmov eax, 0\njmp short locret_11EF\nloc_1187:\nmov rax, [rbp+var_18]\nmov eax, [rax]\ntest eax, eax\njnz short loc_1198\nmov eax, 1\njmp short locret_11EF\nloc_1198:\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_11DE\nloc_11A8:\nmov rax, [rbp+var_18]\nmov rax, [rax+8]\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nshl rdx, 4\nadd rax, rdx\nmov rax, [rax+8]\nmov rdi, rax\ncall func0\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_C]\njle short loc_11DA\nmov eax, [rbp+var_4]\nmov [rbp+var_C], eax\nloc_11DA:\nadd [rbp+var_8], 1\nloc_11DE:\nmov rax, [rbp+var_18]\nmov eax, [rax]\ncmp [rbp+var_8], eax\njl short loc_11A8\nmov eax, [rbp+var_C]\nadd eax, 1\nlocret_11EF:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1)\n{\n int v2; // [rsp+14h] [rbp-Ch]\n int i; // [rsp+18h] [rbp-8h]\n int v4; // [rsp+1Ch] [rbp-4h]\n\n if ( !a1 )\n return 0LL;\n if ( !*(_DWORD *)a1 )\n return 1LL;\n v2 = 0;\n for ( i = 0; i < *(_DWORD *)a1; ++i )\n {\n v4 = func0(*(_QWORD *)(16LL * i + *(_QWORD *)(a1 + 8) + 8));\n if ( v4 > v2 )\n v2 = v4;\n }\n return (unsigned int)(v2 + 1);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\ncmp [rbp+var_18], 0\njnz short loc_1187\nmov eax, 0\njmp short locret_11EF\nloc_1187:\nmov rax, [rbp+var_18]\nmov eax, [rax]\ntest eax, eax\njnz short loc_1198\nmov eax, 1\njmp short locret_11EF\nloc_1198:\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_11DE\nloc_11A8:\nmov rax, [rbp+var_18]\nmov rax, [rax+8]\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nshl rdx, 4\nadd rax, rdx\nmov rax, [rax+8]\nmov rdi, rax\ncall sub_1169\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_C]\njle short loc_11DA\nmov eax, [rbp+var_4]\nmov [rbp+var_C], eax\nloc_11DA:\nadd [rbp+var_8], 1\nloc_11DE:\nmov rax, [rbp+var_18]\nmov eax, [rax]\ncmp [rbp+var_8], eax\njl short loc_11A8\nmov eax, [rbp+var_C]\nadd eax, 1\nlocret_11EF:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1)\n{\n int v2; // [rsp+14h] [rbp-Ch]\n int i; // [rsp+18h] [rbp-8h]\n int v4; // [rsp+1Ch] [rbp-4h]\n\n if ( !a1 )\n return 0LL;\n if ( !*(_DWORD *)a1 )\n return 1LL;\n v2 = 0;\n for ( i = 0; i < *(_DWORD *)a1; ++i )\n {\n v4 = sub_1169(*(_QWORD *)(16LL * i + *(_QWORD *)(a1 + 8) + 8));\n if ( v4 > v2 )\n v2 = v4;\n }\n return (unsigned int)(v2 + 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1) {\n int v2;\n int i;\n int v4;\n if (!a1) return 0LL;\n if (!*(uint32_t *)a1) return 1LL;\n v2 = 0;\n for (i = 0; i < *(uint32_t *)a1; ++i) {\n v4 = sub_1169(*(uint64_t *)(16LL * i + *(uint64_t *)(a1 + 8) + 8));\n if (v4 > v2) v2 = v4;\n }\n return (unsigned int)(v2 + 1);\n}", + "ida_pseudo_norm": "long long func0(long long a1) {\n int v2;\n int i;\n int v4;\n if (!a1) return 0LL;\n if (!*(uint32_t *)a1) return 1LL;\n v2 = 0;\n for (i = 0; i < *(uint32_t *)a1; ++i) {\n v4 = func0(*(uint64_t *)(16LL * i + *(uint64_t *)(a1 + 8) + 8));\n if (v4 > v2) v2 = v4;\n }\n return (unsigned int)(v2 + 1);\n}" + }, + { + "index": 301, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\ntypedef struct Dict Dict;\n\ntypedef struct DictEntry DictEntry;\n\n\n\nstruct DictEntry {\n\n char *key;\n\n Dict *value; // NULL if not a dict\n\n};\n\n\n\nstruct Dict {\n\n int size;\n\n DictEntry *entries;\n\n};\n\n\n\n", + "func": "int func0(Dict *d) {\n if (d == NULL) return 0;\n if (d->size == 0) return 1;\n int max_depth = 0;\n for (int i = 0; i < d->size; i++) {\n int depth = func0(d->entries[i].value);\n if (depth > max_depth) max_depth = depth;\n }\n return 1 + max_depth;\n}", + "test": "int main() {\n\n // First assert: {'a':1, 'b': {'c': {'d': {}}}} == 4\n\n Dict d_inner_most = {0, NULL};\n\n DictEntry entries_c[] = { {\"d\", &d_inner_most} };\n\n Dict dict_c = {1, entries_c};\n\n DictEntry entries_b[] = { {\"c\", &dict_c} };\n\n Dict dict_b = {1, entries_b};\n\n DictEntry entries_a_b[] = { {\"a\", NULL}, {\"b\", &dict_b} };\n\n Dict dict1 = {2, entries_a_b};\n\n assert(func0(&dict1) == 4);\n\n\n\n // Second assert: {'a':1, 'b': {'c':'python'}} == 2\n\n DictEntry entries_b2[] = { {\"c\", NULL} };\n\n Dict dict_b2 = {1, entries_b2};\n\n DictEntry entries_a_b2[] = { {\"a\", NULL}, {\"b\", &dict_b2} };\n\n Dict dict2 = {2, entries_a_b2};\n\n assert(func0(&dict2) == 2);\n\n\n\n // Third assert: {1: 'Sun', 2: {3: {4:'Mon'}}} == 3\n\n Dict d_inner3 = {1, (DictEntry[]) { {\"4\", NULL} }};\n\n Dict dict3_inner = {1, (DictEntry[]) { {\"3\", &d_inner3} }};\n\n Dict dict3 = {2, (DictEntry[]) { {\"1\", NULL}, {\"2\", &dict3_inner} }};\n\n assert(func0(&dict3) == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %rdi,%rdi\nje 11bb \nmov (%rdi),%edx\nmov $0x1,%eax\ntest %edx,%edx\nje 11c1 \npush %r12\npush %rbp\npush %rbx\nmov $0x0,%ebx\njle 11b3 \nmov 0x8(%rdi),%rcx\nlea 0x8(%rcx),%rbp\nlea -0x1(%rdx),%eax\nshl $0x4,%rax\nlea 0x18(%rcx,%rax,1),%r12\nmov 0x0(%rbp),%rdi\ncallq 1169 \ncmp %eax,%ebx\ncmovl %eax,%ebx\nadd $0x10,%rbp\ncmp %r12,%rbp\njne 119c \nlea 0x1(%rbx),%eax\npop %rbx\npop %rbp\npop %r12\nretq\nmov $0x0,%eax\nretq\nretq\n", + "ida_asm": "func0:\nendbr64\ntest rdi, rdi\njz short loc_11B6\nmov edx, [rdi]\nmov eax, 1\ntest edx, edx\njz short locret_11BC\npush r12\npush rbp\npush rbx\nmov ebx, 0\njle short loc_11AE\nmov rbp, [rdi+8]\nmovsxd rdx, edx\nshl rdx, 4\nlea r12, [rdx+rbp]\nloc_1197:\nmov rdi, [rbp+8]\ncall func0\ncmp ebx, eax\ncmovl ebx, eax\nadd rbp, 10h\ncmp r12, rbp\njnz short loc_1197\nloc_11AE:\nlea eax, [rbx+1]\npop rbx\npop rbp\npop r12\nretn\nloc_11B6:\nmov eax, 0\nretn\nlocret_11BC:\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1)\n{\n int v1; // edx\n __int64 result; // rax\n int v3; // ebx\n __int64 v4; // rbp\n __int64 v5; // r12\n int v6; // eax\n\n if ( !a1 )\n return 0LL;\n v1 = *(_DWORD *)a1;\n result = 1LL;\n if ( *(_DWORD *)a1 )\n {\n v3 = 0;\n if ( v1 > 0 )\n {\n v4 = *(_QWORD *)(a1 + 8);\n v5 = 16LL * v1 + v4;\n do\n {\n v6 = func0(*(_QWORD *)(v4 + 8));\n if ( v3 < v6 )\n v3 = v6;\n v4 += 16LL;\n }\n while ( v5 != v4 );\n }\n return (unsigned int)(v3 + 1);\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest rdi, rdi\njz short loc_11B6\nmov edx, [rdi]\nmov eax, 1\ntest edx, edx\njz short locret_11BC\npush r12\npush rbp\npush rbx\nmov ebx, 0\njle short loc_11AE\nmov rbp, [rdi+8]\nmovsxd rdx, edx\nshl rdx, 4\nlea r12, [rdx+rbp]\nloc_1197:\nmov rdi, [rbp+8]\ncall sub_1169\ncmp ebx, eax\ncmovl ebx, eax\nadd rbp, 10h\ncmp r12, rbp\njnz short loc_1197\nloc_11AE:\nlea eax, [rbx+1]\npop rbx\npop rbp\npop r12\nretn\nloc_11B6:\nmov eax, 0\nretn\nlocret_11BC:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1)\n{\n int v1; // edx\n __int64 result; // rax\n int v3; // ebx\n __int64 v4; // rbp\n __int64 v5; // r12\n int v6; // eax\n\n if ( !a1 )\n return 0LL;\n v1 = *(_DWORD *)a1;\n result = 1LL;\n if ( *(_DWORD *)a1 )\n {\n v3 = 0;\n if ( v1 > 0 )\n {\n v4 = *(_QWORD *)(a1 + 8);\n v5 = 16LL * v1 + v4;\n do\n {\n v6 = sub_1169(*(_QWORD *)(v4 + 8));\n if ( v3 < v6 )\n v3 = v6;\n v4 += 16LL;\n }\n while ( v5 != v4 );\n }\n return (unsigned int)(v3 + 1);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1) {\n int v1;\n long long result;\n int v3;\n long long v4;\n long long v5;\n int v6;\n if (!a1) return 0LL;\n v1 = *(uint32_t *)a1;\n result = 1LL;\n if (*(uint32_t *)a1) {\n v3 = 0;\n if (v1 > 0) {\n v4 = *(uint64_t *)(a1 + 8);\n v5 = 16LL * v1 + v4;\n do {\n v6 = sub_1169(*(uint64_t *)(v4 + 8));\n if (v3 < v6) v3 = v6;\n v4 += 16LL;\n } while (v5 != v4);\n }\n return (unsigned int)(v3 + 1);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1) {\n int v1;\n long long result;\n int v3;\n long long v4;\n long long v5;\n int v6;\n if (!a1) return 0LL;\n v1 = *(uint32_t *)a1;\n result = 1LL;\n if (*(uint32_t *)a1) {\n v3 = 0;\n if (v1 > 0) {\n v4 = *(uint64_t *)(a1 + 8);\n v5 = 16LL * v1 + v4;\n do {\n v6 = func0(*(uint64_t *)(v4 + 8));\n if (v3 < v6) v3 = v6;\n v4 += 16LL;\n } while (v5 != v4);\n }\n return (unsigned int)(v3 + 1);\n }\n return result;\n}" + }, + { + "index": 301, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\ntypedef struct Dict Dict;\n\ntypedef struct DictEntry DictEntry;\n\n\n\nstruct DictEntry {\n\n char *key;\n\n Dict *value; // NULL if not a dict\n\n};\n\n\n\nstruct Dict {\n\n int size;\n\n DictEntry *entries;\n\n};\n\n\n\n", + "func": "int func0(Dict *d) {\n if (d == NULL) return 0;\n if (d->size == 0) return 1;\n int max_depth = 0;\n for (int i = 0; i < d->size; i++) {\n int depth = func0(d->entries[i].value);\n if (depth > max_depth) max_depth = depth;\n }\n return 1 + max_depth;\n}", + "test": "int main() {\n\n // First assert: {'a':1, 'b': {'c': {'d': {}}}} == 4\n\n Dict d_inner_most = {0, NULL};\n\n DictEntry entries_c[] = { {\"d\", &d_inner_most} };\n\n Dict dict_c = {1, entries_c};\n\n DictEntry entries_b[] = { {\"c\", &dict_c} };\n\n Dict dict_b = {1, entries_b};\n\n DictEntry entries_a_b[] = { {\"a\", NULL}, {\"b\", &dict_b} };\n\n Dict dict1 = {2, entries_a_b};\n\n assert(func0(&dict1) == 4);\n\n\n\n // Second assert: {'a':1, 'b': {'c':'python'}} == 2\n\n DictEntry entries_b2[] = { {\"c\", NULL} };\n\n Dict dict_b2 = {1, entries_b2};\n\n DictEntry entries_a_b2[] = { {\"a\", NULL}, {\"b\", &dict_b2} };\n\n Dict dict2 = {2, entries_a_b2};\n\n assert(func0(&dict2) == 2);\n\n\n\n // Third assert: {1: 'Sun', 2: {3: {4:'Mon'}}} == 3\n\n Dict d_inner3 = {1, (DictEntry[]) { {\"4\", NULL} }};\n\n Dict dict3_inner = {1, (DictEntry[]) { {\"3\", &d_inner3} }};\n\n Dict dict3 = {2, (DictEntry[]) { {\"1\", NULL}, {\"2\", &dict3_inner} }};\n\n assert(func0(&dict3) == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %rdi,%rdi\nje 1450 \nmov (%rdi),%eax\ntest %eax,%eax\nje 1448 \njmp 1460 \nnopl 0x0(%rax)\nmov $0x1,%eax\nretq\nxchg %ax,%ax\nxor %eax,%eax\nretq\ndata16 nopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0_part_0:\nmovsxd rdx, dword ptr [rdi]\ntest edx, edx\njle loc_15CD\npush r15\nshl rdx, 4\npush r14\npush r13\npush r12\nxor r12d, r12d\npush rbp\npush rbx\nsub rsp, 48h\nmov r13, [rdi+8]\nlea rcx, [rdx+r13]\nmov r15, r13\nmov r14, rcx\nloc_13BE:\nmov rdx, [r15+8]\ntest rdx, rdx\njz loc_15C8\nmovsxd rax, dword ptr [rdx]\nmov r13d, 1\ntest eax, eax\njz loc_1568\njle loc_1568\nmov rbx, [rdx+8]\nshl rax, 4\nmov [rsp+78h+var_70], r12d\nxor r13d, r13d\nmov rsi, r14\nlea rcx, [rax+rbx]\nmov rbp, rcx\nmov ecx, r13d\nmov r13, rbx\nloc_1402:\nmov rdx, [r13+8]\ntest rdx, rdx\njz loc_15C0\nmovsxd rax, dword ptr [rdx]\nmov r12d, 1\ntest eax, eax\njz loc_1545\njle loc_1545\nmov r14, [rdx+8]\nmov [rsp+78h+var_74], ecx\nshl rax, 4\nxor r12d, r12d\nlea rdx, [rax+r14]\nloc_1439:\nmov rax, [r14+8]\ntest rax, rax\njz loc_15B0\nmovsxd r10, dword ptr [rax]\nmov r8d, 1\ntest r10d, r10d\njz loc_1529\njle loc_1529\nmov r9, [rax+8]\nshl r10, 4\nxor r8d, r8d\nadd r10, r9\nloc_146C:\nmov rax, [r9+8]\ntest rax, rax\njz loc_15A0\nmovsxd r11, dword ptr [rax]\nmov ebx, 1\ntest r11d, r11d\njz loc_1511\njle loc_1511\nmov rcx, [rax+8]\nshl r11, 4\nxor ebx, ebx\nadd r11, rcx\nloc_149D:\nmov rdi, [rcx+8]\ntest rdi, rdi\njz loc_1590\ncmp dword ptr [rdi], 0\nmov eax, 1\njz short loc_1500\nmov [rsp+78h+var_40], rcx\nmov [rsp+78h+var_48], r11\nmov [rsp+78h+var_50], r9\nmov [rsp+78h+var_58], r10\nmov [rsp+78h+var_60], rdx\nmov [rsp+78h+var_68], rsi\nmov [rsp+78h+var_6C], r8d\ncall func0_part_0\nmov r8d, [rsp+78h+var_6C]\nmov rsi, [rsp+78h+var_68]\nmov rdx, [rsp+78h+var_60]\nmov r10, [rsp+78h+var_58]\nmov r9, [rsp+78h+var_50]\nmov r11, [rsp+78h+var_48]\nmov rcx, [rsp+78h+var_40]\nnop\nloc_1500:\ncmp ebx, eax\ncmovl ebx, eax\nadd rcx, 10h\ncmp r11, rcx\njnz short loc_149D\nadd ebx, 1\nloc_1511:\ncmp r8d, ebx\ncmovl r8d, ebx\nadd r9, 10h\ncmp r10, r9\njnz loc_146C\nadd r8d, 1\nloc_1529:\ncmp r12d, r8d\ncmovl r12d, r8d\nadd r14, 10h\ncmp rdx, r14\njnz loc_1439\nmov ecx, [rsp+78h+var_74]\nadd r12d, 1\nloc_1545:\ncmp ecx, r12d\ncmovl ecx, r12d\nadd r13, 10h\ncmp rbp, r13\njnz loc_1402\nmov r13d, ecx\nmov r12d, [rsp+78h+var_70]\nmov r14, rsi\nadd r13d, 1\nloc_1568:\ncmp r12d, r13d\ncmovl r12d, r13d\nadd r15, 10h\ncmp r14, r15\njnz loc_13BE\nadd rsp, 48h\nlea eax, [r12+1]\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1590:\nxor eax, eax\njmp loc_1500\nloc_15A0:\nxor ebx, ebx\njmp loc_1511\nloc_15B0:\nxor r8d, r8d\njmp loc_1529\nloc_15C0:\nxor r12d, r12d\njmp short loc_1545\nloc_15C8:\nxor r13d, r13d\njmp short loc_1568\nloc_15CD:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0_part_0(int *a1)\n{\n __int64 v1; // rdx\n int v2; // r12d\n __int64 v3; // r15\n __int64 v4; // r14\n int *v5; // rdx\n __int64 v6; // rax\n int v7; // r13d\n __int64 v8; // rsi\n __int64 v9; // rbp\n int v10; // ecx\n __int64 v11; // r13\n int *v12; // rdx\n __int64 v13; // rax\n int v14; // r12d\n __int64 v15; // r14\n int v16; // r12d\n __int64 v17; // rdx\n int *v18; // rax\n __int64 v19; // r10\n int v20; // r8d\n __int64 v21; // r9\n int v22; // r8d\n __int64 v23; // r10\n int *v24; // rax\n __int64 v25; // r11\n int v26; // ebx\n __int64 v27; // rcx\n int v28; // ebx\n __int64 v29; // r11\n _DWORD *v30; // rdi\n int v31; // eax\n int v33; // [rsp+0h] [rbp-74h]\n int v34; // [rsp+4h] [rbp-70h]\n int v35; // [rsp+8h] [rbp-6Ch]\n __int64 v36; // [rsp+14h] [rbp-60h]\n __int64 v37; // [rsp+1Ch] [rbp-58h]\n __int64 v38; // [rsp+24h] [rbp-50h]\n __int64 v39; // [rsp+2Ch] [rbp-48h]\n __int64 v40; // [rsp+34h] [rbp-40h]\n\n v1 = *a1;\n if ( (int)v1 <= 0 )\n return 1LL;\n v2 = 0;\n v3 = *((_QWORD *)a1 + 1);\n v4 = 16 * v1 + v3;\n do\n {\n v5 = *(int **)(v3 + 8);\n if ( v5 )\n {\n v6 = *v5;\n v7 = 1;\n if ( (int)v6 > 0 )\n {\n v34 = v2;\n v8 = v4;\n v9 = 16 * v6 + *((_QWORD *)v5 + 1);\n v10 = 0;\n v11 = *((_QWORD *)v5 + 1);\n do\n {\n v12 = *(int **)(v11 + 8);\n if ( v12 )\n {\n v13 = *v12;\n v14 = 1;\n if ( (int)v13 > 0 )\n {\n v15 = *((_QWORD *)v12 + 1);\n v33 = v10;\n v16 = 0;\n v17 = 16 * v13 + v15;\n do\n {\n v18 = *(int **)(v15 + 8);\n if ( v18 )\n {\n v19 = *v18;\n v20 = 1;\n if ( (int)v19 > 0 )\n {\n v21 = *((_QWORD *)v18 + 1);\n v22 = 0;\n v23 = v21 + 16 * v19;\n do\n {\n v24 = *(int **)(v21 + 8);\n if ( v24 )\n {\n v25 = *v24;\n v26 = 1;\n if ( (int)v25 > 0 )\n {\n v27 = *((_QWORD *)v24 + 1);\n v28 = 0;\n v29 = v27 + 16 * v25;\n do\n {\n v30 = *(_DWORD **)(v27 + 8);\n if ( v30 )\n {\n v31 = 1;\n if ( *v30 )\n {\n v40 = v27;\n v39 = v29;\n v38 = v21;\n v37 = v23;\n v36 = v17;\n v35 = v22;\n v31 = func0_part_0();\n v22 = v35;\n v17 = v36;\n v23 = v37;\n v21 = v38;\n v29 = v39;\n v27 = v40;\n }\n }\n else\n {\n v31 = 0;\n }\n if ( v28 < v31 )\n v28 = v31;\n v27 += 16LL;\n }\n while ( v29 != v27 );\n v26 = v28 + 1;\n }\n }\n else\n {\n v26 = 0;\n }\n if ( v22 < v26 )\n v22 = v26;\n v21 += 16LL;\n }\n while ( v23 != v21 );\n v20 = v22 + 1;\n }\n }\n else\n {\n v20 = 0;\n }\n if ( v16 < v20 )\n v16 = v20;\n v15 += 16LL;\n }\n while ( v17 != v15 );\n v10 = v33;\n v14 = v16 + 1;\n }\n }\n else\n {\n v14 = 0;\n }\n if ( v10 < v14 )\n v10 = v14;\n v11 += 16LL;\n }\n while ( v9 != v11 );\n v2 = v34;\n v4 = v8;\n v7 = v10 + 1;\n }\n }\n else\n {\n v7 = 0;\n }\n if ( v2 < v7 )\n v2 = v7;\n v3 += 16LL;\n }\n while ( v4 != v3 );\n return (unsigned int)(v2 + 1);\n}", + "ida_strip_asm": "sub_1390:\nmovsxd rdx, dword ptr [rdi]\ntest edx, edx\njle loc_15CD\npush r15\nshl rdx, 4\npush r14\npush r13\npush r12\nxor r12d, r12d\npush rbp\npush rbx\nsub rsp, 48h\nmov r13, [rdi+8]\nlea rcx, [rdx+r13]\nmov r15, r13\nmov r14, rcx\nloc_13BE:\nmov rdx, [r15+8]\ntest rdx, rdx\njz loc_15C8\nmovsxd rax, dword ptr [rdx]\nmov r13d, 1\ntest eax, eax\njz loc_1568\njle loc_1568\nmov rbx, [rdx+8]\nshl rax, 4\nmov [rsp+78h+var_70], r12d\nxor r13d, r13d\nmov rsi, r14\nlea rcx, [rax+rbx]\nmov rbp, rcx\nmov ecx, r13d\nmov r13, rbx\nloc_1402:\nmov rdx, [r13+8]\ntest rdx, rdx\njz loc_15C0\nmovsxd rax, dword ptr [rdx]\nmov r12d, 1\ntest eax, eax\njz loc_1545\njle loc_1545\nmov r14, [rdx+8]\nmov [rsp+78h+var_74], ecx\nshl rax, 4\nxor r12d, r12d\nlea rdx, [rax+r14]\nloc_1439:\nmov rax, [r14+8]\ntest rax, rax\njz loc_15B0\nmovsxd r10, dword ptr [rax]\nmov r8d, 1\ntest r10d, r10d\njz loc_1529\njle loc_1529\nmov r9, [rax+8]\nshl r10, 4\nxor r8d, r8d\nadd r10, r9\nloc_146C:\nmov rax, [r9+8]\ntest rax, rax\njz loc_15A0\nmovsxd r11, dword ptr [rax]\nmov ebx, 1\ntest r11d, r11d\njz loc_1511\njle loc_1511\nmov rcx, [rax+8]\nshl r11, 4\nxor ebx, ebx\nadd r11, rcx\nloc_149D:\nmov rdi, [rcx+8]\ntest rdi, rdi\njz loc_1590\ncmp dword ptr [rdi], 0\nmov eax, 1\njz short loc_1500\nmov [rsp+78h+var_40], rcx\nmov [rsp+78h+var_48], r11\nmov [rsp+78h+var_50], r9\nmov [rsp+78h+var_58], r10\nmov [rsp+78h+var_60], rdx\nmov [rsp+78h+var_68], rsi\nmov [rsp+78h+var_6C], r8d\ncall sub_1390\nmov r8d, [rsp+78h+var_6C]\nmov rsi, [rsp+78h+var_68]\nmov rdx, [rsp+78h+var_60]\nmov r10, [rsp+78h+var_58]\nmov r9, [rsp+78h+var_50]\nmov r11, [rsp+78h+var_48]\nmov rcx, [rsp+78h+var_40]\nnop\nloc_1500:\ncmp ebx, eax\ncmovl ebx, eax\nadd rcx, 10h\ncmp r11, rcx\njnz short loc_149D\nadd ebx, 1\nloc_1511:\ncmp r8d, ebx\ncmovl r8d, ebx\nadd r9, 10h\ncmp r10, r9\njnz loc_146C\nadd r8d, 1\nloc_1529:\ncmp r12d, r8d\ncmovl r12d, r8d\nadd r14, 10h\ncmp rdx, r14\njnz loc_1439\nmov ecx, [rsp+78h+var_74]\nadd r12d, 1\nloc_1545:\ncmp ecx, r12d\ncmovl ecx, r12d\nadd r13, 10h\ncmp rbp, r13\njnz loc_1402\nmov r13d, ecx\nmov r12d, [rsp+78h+var_70]\nmov r14, rsi\nadd r13d, 1\nloc_1568:\ncmp r12d, r13d\ncmovl r12d, r13d\nadd r15, 10h\ncmp r14, r15\njnz loc_13BE\nadd rsp, 48h\nlea eax, [r12+1]\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1590:\nxor eax, eax\njmp loc_1500\nloc_15A0:\nxor ebx, ebx\njmp loc_1511\nloc_15B0:\nxor r8d, r8d\njmp loc_1529\nloc_15C0:\nxor r12d, r12d\njmp short loc_1545\nloc_15C8:\nxor r13d, r13d\njmp short loc_1568\nloc_15CD:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1390(int *a1)\n{\n __int64 v1; // rdx\n int v2; // r12d\n __int64 v3; // r15\n __int64 v4; // r14\n int *v5; // rdx\n __int64 v6; // rax\n int v7; // r13d\n __int64 v8; // rsi\n __int64 v9; // rbp\n int v10; // ecx\n __int64 v11; // r13\n int *v12; // rdx\n __int64 v13; // rax\n int v14; // r12d\n __int64 v15; // r14\n int v16; // r12d\n __int64 v17; // rdx\n int *v18; // rax\n __int64 v19; // r10\n int v20; // r8d\n __int64 v21; // r9\n int v22; // r8d\n __int64 v23; // r10\n int *v24; // rax\n __int64 v25; // r11\n int v26; // ebx\n __int64 v27; // rcx\n int v28; // ebx\n __int64 v29; // r11\n _DWORD *v30; // rdi\n int v31; // eax\n int v33; // [rsp+0h] [rbp-74h]\n int v34; // [rsp+4h] [rbp-70h]\n int v35; // [rsp+8h] [rbp-6Ch]\n __int64 v36; // [rsp+14h] [rbp-60h]\n __int64 v37; // [rsp+1Ch] [rbp-58h]\n __int64 v38; // [rsp+24h] [rbp-50h]\n __int64 v39; // [rsp+2Ch] [rbp-48h]\n __int64 v40; // [rsp+34h] [rbp-40h]\n\n v1 = *a1;\n if ( (int)v1 <= 0 )\n return 1LL;\n v2 = 0;\n v3 = *((_QWORD *)a1 + 1);\n v4 = 16 * v1 + v3;\n do\n {\n v5 = *(int **)(v3 + 8);\n if ( v5 )\n {\n v6 = *v5;\n v7 = 1;\n if ( (int)v6 > 0 )\n {\n v34 = v2;\n v8 = v4;\n v9 = 16 * v6 + *((_QWORD *)v5 + 1);\n v10 = 0;\n v11 = *((_QWORD *)v5 + 1);\n do\n {\n v12 = *(int **)(v11 + 8);\n if ( v12 )\n {\n v13 = *v12;\n v14 = 1;\n if ( (int)v13 > 0 )\n {\n v15 = *((_QWORD *)v12 + 1);\n v33 = v10;\n v16 = 0;\n v17 = 16 * v13 + v15;\n do\n {\n v18 = *(int **)(v15 + 8);\n if ( v18 )\n {\n v19 = *v18;\n v20 = 1;\n if ( (int)v19 > 0 )\n {\n v21 = *((_QWORD *)v18 + 1);\n v22 = 0;\n v23 = v21 + 16 * v19;\n do\n {\n v24 = *(int **)(v21 + 8);\n if ( v24 )\n {\n v25 = *v24;\n v26 = 1;\n if ( (int)v25 > 0 )\n {\n v27 = *((_QWORD *)v24 + 1);\n v28 = 0;\n v29 = v27 + 16 * v25;\n do\n {\n v30 = *(_DWORD **)(v27 + 8);\n if ( v30 )\n {\n v31 = 1;\n if ( *v30 )\n {\n v40 = v27;\n v39 = v29;\n v38 = v21;\n v37 = v23;\n v36 = v17;\n v35 = v22;\n v31 = sub_1390();\n v22 = v35;\n v17 = v36;\n v23 = v37;\n v21 = v38;\n v29 = v39;\n v27 = v40;\n }\n }\n else\n {\n v31 = 0;\n }\n if ( v28 < v31 )\n v28 = v31;\n v27 += 16LL;\n }\n while ( v29 != v27 );\n v26 = v28 + 1;\n }\n }\n else\n {\n v26 = 0;\n }\n if ( v22 < v26 )\n v22 = v26;\n v21 += 16LL;\n }\n while ( v23 != v21 );\n v20 = v22 + 1;\n }\n }\n else\n {\n v20 = 0;\n }\n if ( v16 < v20 )\n v16 = v20;\n v15 += 16LL;\n }\n while ( v17 != v15 );\n v10 = v33;\n v14 = v16 + 1;\n }\n }\n else\n {\n v14 = 0;\n }\n if ( v10 < v14 )\n v10 = v14;\n v11 += 16LL;\n }\n while ( v9 != v11 );\n v2 = v34;\n v4 = v8;\n v7 = v10 + 1;\n }\n }\n else\n {\n v7 = 0;\n }\n if ( v2 < v7 )\n v2 = v7;\n v3 += 16LL;\n }\n while ( v4 != v3 );\n return (unsigned int)(v2 + 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1390(int *a1) {\n long long v1;\n int v2;\n long long v3;\n long long v4;\n int *v5;\n long long v6;\n int v7;\n long long v8;\n long long v9;\n int v10;\n long long v11;\n int *v12;\n long long v13;\n int v14;\n long long v15;\n int v16;\n long long v17;\n int *v18;\n long long v19;\n int v20;\n long long v21;\n int v22;\n long long v23;\n int *v24;\n long long v25;\n int v26;\n long long v27;\n int v28;\n long long v29;\n uint32_t *v30;\n int v31;\n int v33;\n int v34;\n int v35;\n long long v36;\n long long v37;\n long long v38;\n long long v39;\n long long v40;\n v1 = *a1;\n if ((int)v1 <= 0) return 1LL;\n v2 = 0;\n v3 = *((uint64_t *)a1 + 1);\n v4 = 16 * v1 + v3;\n do {\n v5 = *(int **)(v3 + 8);\n if (v5) {\n v6 = *v5;\n v7 = 1;\n if ((int)v6 > 0) {\n v34 = v2;\n v8 = v4;\n v9 = 16 * v6 + *((uint64_t *)v5 + 1);\n v10 = 0;\n v11 = *((uint64_t *)v5 + 1);\n do {\n v12 = *(int **)(v11 + 8);\n if (v12) {\n v13 = *v12;\n v14 = 1;\n if ((int)v13 > 0) {\n v15 = *((uint64_t *)v12 + 1);\n v33 = v10;\n v16 = 0;\n v17 = 16 * v13 + v15;\n do {\n v18 = *(int **)(v15 + 8);\n if (v18) {\n v19 = *v18;\n v20 = 1;\n if ((int)v19 > 0) {\n v21 = *((uint64_t *)v18 + 1);\n v22 = 0;\n v23 = v21 + 16 * v19;\n do {\n v24 = *(int **)(v21 + 8);\n if (v24) {\n v25 = *v24;\n v26 = 1;\n if ((int)v25 > 0) {\n v27 = *((uint64_t *)v24 + 1);\n v28 = 0;\n v29 = v27 + 16 * v25;\n do {\n v30 = *(uint32_t **)(v27 + 8);\n if (v30) {\n v31 = 1;\n if (*v30) {\n v40 = v27;\n v39 = v29;\n v38 = v21;\n v37 = v23;\n v36 = v17;\n v35 = v22;\n v31 = sub_1390();\n v22 = v35;\n v17 = v36;\n v23 = v37;\n v21 = v38;\n v29 = v39;\n v27 = v40;\n }\n } else {\n v31 = 0;\n }\n if (v28 < v31) v28 = v31;\n v27 += 16LL;\n } while (v29 != v27);\n v26 = v28 + 1;\n }\n } else {\n v26 = 0;\n }\n if (v22 < v26) v22 = v26;\n v21 += 16LL;\n } while (v23 != v21);\n v20 = v22 + 1;\n }\n } else {\n v20 = 0;\n }\n if (v16 < v20) v16 = v20;\n v15 += 16LL;\n } while (v17 != v15);\n v10 = v33;\n v14 = v16 + 1;\n }\n } else {\n v14 = 0;\n }\n if (v10 < v14) v10 = v14;\n v11 += 16LL;\n } while (v9 != v11);\n v2 = v34;\n v4 = v8;\n v7 = v10 + 1;\n }\n } else {\n v7 = 0;\n }\n if (v2 < v7) v2 = v7;\n v3 += 16LL;\n } while (v4 != v3);\n return (unsigned int)(v2 + 1);\n}", + "ida_pseudo_norm": "long long func0_part_0(int *a1) {\n long long v1;\n int v2;\n long long v3;\n long long v4;\n int *v5;\n long long v6;\n int v7;\n long long v8;\n long long v9;\n int v10;\n long long v11;\n int *v12;\n long long v13;\n int v14;\n long long v15;\n int v16;\n long long v17;\n int *v18;\n long long v19;\n int v20;\n long long v21;\n int v22;\n long long v23;\n int *v24;\n long long v25;\n int v26;\n long long v27;\n int v28;\n long long v29;\n uint32_t *v30;\n int v31;\n int v33;\n int v34;\n int v35;\n long long v36;\n long long v37;\n long long v38;\n long long v39;\n long long v40;\n v1 = *a1;\n if ((int)v1 <= 0) return 1LL;\n v2 = 0;\n v3 = *((uint64_t *)a1 + 1);\n v4 = 16 * v1 + v3;\n do {\n v5 = *(int **)(v3 + 8);\n if (v5) {\n v6 = *v5;\n v7 = 1;\n if ((int)v6 > 0) {\n v34 = v2;\n v8 = v4;\n v9 = 16 * v6 + *((uint64_t *)v5 + 1);\n v10 = 0;\n v11 = *((uint64_t *)v5 + 1);\n do {\n v12 = *(int **)(v11 + 8);\n if (v12) {\n v13 = *v12;\n v14 = 1;\n if ((int)v13 > 0) {\n v15 = *((uint64_t *)v12 + 1);\n v33 = v10;\n v16 = 0;\n v17 = 16 * v13 + v15;\n do {\n v18 = *(int **)(v15 + 8);\n if (v18) {\n v19 = *v18;\n v20 = 1;\n if ((int)v19 > 0) {\n v21 = *((uint64_t *)v18 + 1);\n v22 = 0;\n v23 = v21 + 16 * v19;\n do {\n v24 = *(int **)(v21 + 8);\n if (v24) {\n v25 = *v24;\n v26 = 1;\n if ((int)v25 > 0) {\n v27 = *((uint64_t *)v24 + 1);\n v28 = 0;\n v29 = v27 + 16 * v25;\n do {\n v30 = *(uint32_t **)(v27 + 8);\n if (v30) {\n v31 = 1;\n if (*v30) {\n v40 = v27;\n v39 = v29;\n v38 = v21;\n v37 = v23;\n v36 = v17;\n v35 = v22;\n v31 = func0_part_0();\n v22 = v35;\n v17 = v36;\n v23 = v37;\n v21 = v38;\n v29 = v39;\n v27 = v40;\n }\n } else {\n v31 = 0;\n }\n if (v28 < v31) v28 = v31;\n v27 += 16LL;\n } while (v29 != v27);\n v26 = v28 + 1;\n }\n } else {\n v26 = 0;\n }\n if (v22 < v26) v22 = v26;\n v21 += 16LL;\n } while (v23 != v21);\n v20 = v22 + 1;\n }\n } else {\n v20 = 0;\n }\n if (v16 < v20) v16 = v20;\n v15 += 16LL;\n } while (v17 != v15);\n v10 = v33;\n v14 = v16 + 1;\n }\n } else {\n v14 = 0;\n }\n if (v10 < v14) v10 = v14;\n v11 += 16LL;\n } while (v9 != v11);\n v2 = v34;\n v4 = v8;\n v7 = v10 + 1;\n }\n } else {\n v7 = 0;\n }\n if (v2 < v7) v2 = v7;\n v3 += 16LL;\n } while (v4 != v3);\n return (unsigned int)(v2 + 1);\n}" + }, + { + "index": 301, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\ntypedef struct Dict Dict;\n\ntypedef struct DictEntry DictEntry;\n\n\n\nstruct DictEntry {\n\n char *key;\n\n Dict *value; // NULL if not a dict\n\n};\n\n\n\nstruct Dict {\n\n int size;\n\n DictEntry *entries;\n\n};\n\n\n\n", + "func": "int func0(Dict *d) {\n if (d == NULL) return 0;\n if (d->size == 0) return 1;\n int max_depth = 0;\n for (int i = 0; i < d->size; i++) {\n int depth = func0(d->entries[i].value);\n if (depth > max_depth) max_depth = depth;\n }\n return 1 + max_depth;\n}", + "test": "int main() {\n\n // First assert: {'a':1, 'b': {'c': {'d': {}}}} == 4\n\n Dict d_inner_most = {0, NULL};\n\n DictEntry entries_c[] = { {\"d\", &d_inner_most} };\n\n Dict dict_c = {1, entries_c};\n\n DictEntry entries_b[] = { {\"c\", &dict_c} };\n\n Dict dict_b = {1, entries_b};\n\n DictEntry entries_a_b[] = { {\"a\", NULL}, {\"b\", &dict_b} };\n\n Dict dict1 = {2, entries_a_b};\n\n assert(func0(&dict1) == 4);\n\n\n\n // Second assert: {'a':1, 'b': {'c':'python'}} == 2\n\n DictEntry entries_b2[] = { {\"c\", NULL} };\n\n Dict dict_b2 = {1, entries_b2};\n\n DictEntry entries_a_b2[] = { {\"a\", NULL}, {\"b\", &dict_b2} };\n\n Dict dict2 = {2, entries_a_b2};\n\n assert(func0(&dict2) == 2);\n\n\n\n // Third assert: {1: 'Sun', 2: {3: {4:'Mon'}}} == 3\n\n Dict d_inner3 = {1, (DictEntry[]) { {\"4\", NULL} }};\n\n Dict dict3_inner = {1, (DictEntry[]) { {\"3\", &d_inner3} }};\n\n Dict dict3 = {2, (DictEntry[]) { {\"1\", NULL}, {\"2\", &dict3_inner} }};\n\n assert(func0(&dict3) == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ntest %rdi,%rdi\nje 1540 \nmov (%rdi),%edx\nmov $0x1,%eax\ntest %edx,%edx\nje 1533 \njle 1533 \nmov 0x8(%rdi),%rcx\nlea -0x1(%rdx),%eax\nxor %esi,%esi\nshl $0x4,%rax\nlea 0x8(%rcx),%r8\nlea 0x18(%rcx,%rax,1),%r9\nmov (%r8),%rdi\ntest %rdi,%rdi\nje 1520 \nmov (%rdi),%edx\nmov $0x1,%eax\ntest %edx,%edx\nje 1522 \nsub $0x8,%rsp\ncallq 1430 \ncmp %eax,%esi\ncmovl %eax,%esi\nadd $0x10,%r8\ncmp %r8,%r9\nje 1513 \nmov (%r8),%rdi\ntest %rdi,%rdi\nje 1538 \nmov (%rdi),%ecx\nmov $0x1,%eax\ntest %ecx,%ecx\njne 14df \ncmp %eax,%esi\ncmovl %eax,%esi\nadd $0x10,%r8\ncmp %r8,%r9\njne 14f2 \nlea 0x1(%rsi),%eax\nadd $0x8,%rsp\nretq\nnopl 0x0(%rax,%rax,1)\nxor %eax,%eax\ncmp %eax,%esi\ncmovl %eax,%esi\nadd $0x10,%r8\ncmp %r8,%r9\njne 14c8 \nlea 0x1(%rsi),%eax\nretq\nnopl 0x0(%rax)\nxor %eax,%eax\njmp 14e4 \nnopl 0x0(%rax)\nxor %eax,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0_part_0:\nmovsxd rdx, dword ptr [rdi]\ntest edx, edx\njle loc_15CD\npush r15\nshl rdx, 4\npush r14\npush r13\npush r12\nxor r12d, r12d\npush rbp\npush rbx\nsub rsp, 48h\nmov r13, [rdi+8]\nlea rcx, [rdx+r13]\nmov r15, r13\nmov r14, rcx\nloc_13BE:\nmov rdx, [r15+8]\ntest rdx, rdx\njz loc_15C8\nmovsxd rax, dword ptr [rdx]\nmov r13d, 1\ntest eax, eax\njz loc_1568\njle loc_1568\nmov rbx, [rdx+8]\nshl rax, 4\nmov [rsp+78h+var_70], r12d\nxor r13d, r13d\nmov rsi, r14\nlea rcx, [rax+rbx]\nmov rbp, rcx\nmov ecx, r13d\nmov r13, rbx\nloc_1402:\nmov rdx, [r13+8]\ntest rdx, rdx\njz loc_15C0\nmovsxd rax, dword ptr [rdx]\nmov r12d, 1\ntest eax, eax\njz loc_1545\njle loc_1545\nmov r14, [rdx+8]\nmov [rsp+78h+var_74], ecx\nshl rax, 4\nxor r12d, r12d\nlea rdx, [rax+r14]\nloc_1439:\nmov rax, [r14+8]\ntest rax, rax\njz loc_15B0\nmovsxd r10, dword ptr [rax]\nmov r8d, 1\ntest r10d, r10d\njz loc_1529\njle loc_1529\nmov r9, [rax+8]\nshl r10, 4\nxor r8d, r8d\nadd r10, r9\nloc_146C:\nmov rax, [r9+8]\ntest rax, rax\njz loc_15A0\nmovsxd r11, dword ptr [rax]\nmov ebx, 1\ntest r11d, r11d\njz loc_1511\njle loc_1511\nmov rcx, [rax+8]\nshl r11, 4\nxor ebx, ebx\nadd r11, rcx\nloc_149D:\nmov rdi, [rcx+8]\ntest rdi, rdi\njz loc_1590\ncmp dword ptr [rdi], 0\nmov eax, 1\njz short loc_1500\nmov [rsp+78h+var_40], rcx\nmov [rsp+78h+var_48], r11\nmov [rsp+78h+var_50], r9\nmov [rsp+78h+var_58], r10\nmov [rsp+78h+var_60], rdx\nmov [rsp+78h+var_68], rsi\nmov [rsp+78h+var_6C], r8d\ncall func0_part_0\nmov r8d, [rsp+78h+var_6C]\nmov rsi, [rsp+78h+var_68]\nmov rdx, [rsp+78h+var_60]\nmov r10, [rsp+78h+var_58]\nmov r9, [rsp+78h+var_50]\nmov r11, [rsp+78h+var_48]\nmov rcx, [rsp+78h+var_40]\nnop\nloc_1500:\ncmp ebx, eax\ncmovl ebx, eax\nadd rcx, 10h\ncmp r11, rcx\njnz short loc_149D\nadd ebx, 1\nloc_1511:\ncmp r8d, ebx\ncmovl r8d, ebx\nadd r9, 10h\ncmp r10, r9\njnz loc_146C\nadd r8d, 1\nloc_1529:\ncmp r12d, r8d\ncmovl r12d, r8d\nadd r14, 10h\ncmp rdx, r14\njnz loc_1439\nmov ecx, [rsp+78h+var_74]\nadd r12d, 1\nloc_1545:\ncmp ecx, r12d\ncmovl ecx, r12d\nadd r13, 10h\ncmp rbp, r13\njnz loc_1402\nmov r13d, ecx\nmov r12d, [rsp+78h+var_70]\nmov r14, rsi\nadd r13d, 1\nloc_1568:\ncmp r12d, r13d\ncmovl r12d, r13d\nadd r15, 10h\ncmp r14, r15\njnz loc_13BE\nadd rsp, 48h\nlea eax, [r12+1]\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1590:\nxor eax, eax\njmp loc_1500\nloc_15A0:\nxor ebx, ebx\njmp loc_1511\nloc_15B0:\nxor r8d, r8d\njmp loc_1529\nloc_15C0:\nxor r12d, r12d\njmp short loc_1545\nloc_15C8:\nxor r13d, r13d\njmp short loc_1568\nloc_15CD:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0_part_0(int *a1)\n{\n __int64 v1; // rdx\n int v2; // r12d\n __int64 v3; // r15\n __int64 v4; // r14\n int *v5; // rdx\n __int64 v6; // rax\n int v7; // r13d\n __int64 v8; // rsi\n __int64 v9; // rbp\n int v10; // ecx\n __int64 v11; // r13\n int *v12; // rdx\n __int64 v13; // rax\n int v14; // r12d\n __int64 v15; // r14\n int v16; // r12d\n __int64 v17; // rdx\n int *v18; // rax\n __int64 v19; // r10\n int v20; // r8d\n __int64 v21; // r9\n int v22; // r8d\n __int64 v23; // r10\n int *v24; // rax\n __int64 v25; // r11\n int v26; // ebx\n __int64 v27; // rcx\n int v28; // ebx\n __int64 v29; // r11\n _DWORD *v30; // rdi\n int v31; // eax\n int v33; // [rsp+0h] [rbp-74h]\n int v34; // [rsp+4h] [rbp-70h]\n int v35; // [rsp+8h] [rbp-6Ch]\n __int64 v36; // [rsp+14h] [rbp-60h]\n __int64 v37; // [rsp+1Ch] [rbp-58h]\n __int64 v38; // [rsp+24h] [rbp-50h]\n __int64 v39; // [rsp+2Ch] [rbp-48h]\n __int64 v40; // [rsp+34h] [rbp-40h]\n\n v1 = *a1;\n if ( (int)v1 <= 0 )\n return 1LL;\n v2 = 0;\n v3 = *((_QWORD *)a1 + 1);\n v4 = 16 * v1 + v3;\n do\n {\n v5 = *(int **)(v3 + 8);\n if ( v5 )\n {\n v6 = *v5;\n v7 = 1;\n if ( (int)v6 > 0 )\n {\n v34 = v2;\n v8 = v4;\n v9 = 16 * v6 + *((_QWORD *)v5 + 1);\n v10 = 0;\n v11 = *((_QWORD *)v5 + 1);\n do\n {\n v12 = *(int **)(v11 + 8);\n if ( v12 )\n {\n v13 = *v12;\n v14 = 1;\n if ( (int)v13 > 0 )\n {\n v15 = *((_QWORD *)v12 + 1);\n v33 = v10;\n v16 = 0;\n v17 = 16 * v13 + v15;\n do\n {\n v18 = *(int **)(v15 + 8);\n if ( v18 )\n {\n v19 = *v18;\n v20 = 1;\n if ( (int)v19 > 0 )\n {\n v21 = *((_QWORD *)v18 + 1);\n v22 = 0;\n v23 = v21 + 16 * v19;\n do\n {\n v24 = *(int **)(v21 + 8);\n if ( v24 )\n {\n v25 = *v24;\n v26 = 1;\n if ( (int)v25 > 0 )\n {\n v27 = *((_QWORD *)v24 + 1);\n v28 = 0;\n v29 = v27 + 16 * v25;\n do\n {\n v30 = *(_DWORD **)(v27 + 8);\n if ( v30 )\n {\n v31 = 1;\n if ( *v30 )\n {\n v40 = v27;\n v39 = v29;\n v38 = v21;\n v37 = v23;\n v36 = v17;\n v35 = v22;\n v31 = func0_part_0();\n v22 = v35;\n v17 = v36;\n v23 = v37;\n v21 = v38;\n v29 = v39;\n v27 = v40;\n }\n }\n else\n {\n v31 = 0;\n }\n if ( v28 < v31 )\n v28 = v31;\n v27 += 16LL;\n }\n while ( v29 != v27 );\n v26 = v28 + 1;\n }\n }\n else\n {\n v26 = 0;\n }\n if ( v22 < v26 )\n v22 = v26;\n v21 += 16LL;\n }\n while ( v23 != v21 );\n v20 = v22 + 1;\n }\n }\n else\n {\n v20 = 0;\n }\n if ( v16 < v20 )\n v16 = v20;\n v15 += 16LL;\n }\n while ( v17 != v15 );\n v10 = v33;\n v14 = v16 + 1;\n }\n }\n else\n {\n v14 = 0;\n }\n if ( v10 < v14 )\n v10 = v14;\n v11 += 16LL;\n }\n while ( v9 != v11 );\n v2 = v34;\n v4 = v8;\n v7 = v10 + 1;\n }\n }\n else\n {\n v7 = 0;\n }\n if ( v2 < v7 )\n v2 = v7;\n v3 += 16LL;\n }\n while ( v4 != v3 );\n return (unsigned int)(v2 + 1);\n}", + "ida_strip_asm": "sub_1390:\nmovsxd rdx, dword ptr [rdi]\ntest edx, edx\njle loc_15CD\npush r15\nshl rdx, 4\npush r14\npush r13\npush r12\nxor r12d, r12d\npush rbp\npush rbx\nsub rsp, 48h\nmov r13, [rdi+8]\nlea rcx, [rdx+r13]\nmov r15, r13\nmov r14, rcx\nloc_13BE:\nmov rdx, [r15+8]\ntest rdx, rdx\njz loc_15C8\nmovsxd rax, dword ptr [rdx]\nmov r13d, 1\ntest eax, eax\njz loc_1568\njle loc_1568\nmov rbx, [rdx+8]\nshl rax, 4\nmov [rsp+78h+var_70], r12d\nxor r13d, r13d\nmov rsi, r14\nlea rcx, [rax+rbx]\nmov rbp, rcx\nmov ecx, r13d\nmov r13, rbx\nloc_1402:\nmov rdx, [r13+8]\ntest rdx, rdx\njz loc_15C0\nmovsxd rax, dword ptr [rdx]\nmov r12d, 1\ntest eax, eax\njz loc_1545\njle loc_1545\nmov r14, [rdx+8]\nmov [rsp+78h+var_74], ecx\nshl rax, 4\nxor r12d, r12d\nlea rdx, [rax+r14]\nloc_1439:\nmov rax, [r14+8]\ntest rax, rax\njz loc_15B0\nmovsxd r10, dword ptr [rax]\nmov r8d, 1\ntest r10d, r10d\njz loc_1529\njle loc_1529\nmov r9, [rax+8]\nshl r10, 4\nxor r8d, r8d\nadd r10, r9\nloc_146C:\nmov rax, [r9+8]\ntest rax, rax\njz loc_15A0\nmovsxd r11, dword ptr [rax]\nmov ebx, 1\ntest r11d, r11d\njz loc_1511\njle loc_1511\nmov rcx, [rax+8]\nshl r11, 4\nxor ebx, ebx\nadd r11, rcx\nloc_149D:\nmov rdi, [rcx+8]\ntest rdi, rdi\njz loc_1590\ncmp dword ptr [rdi], 0\nmov eax, 1\njz short loc_1500\nmov [rsp+78h+var_40], rcx\nmov [rsp+78h+var_48], r11\nmov [rsp+78h+var_50], r9\nmov [rsp+78h+var_58], r10\nmov [rsp+78h+var_60], rdx\nmov [rsp+78h+var_68], rsi\nmov [rsp+78h+var_6C], r8d\ncall sub_1390\nmov r8d, [rsp+78h+var_6C]\nmov rsi, [rsp+78h+var_68]\nmov rdx, [rsp+78h+var_60]\nmov r10, [rsp+78h+var_58]\nmov r9, [rsp+78h+var_50]\nmov r11, [rsp+78h+var_48]\nmov rcx, [rsp+78h+var_40]\nnop\nloc_1500:\ncmp ebx, eax\ncmovl ebx, eax\nadd rcx, 10h\ncmp r11, rcx\njnz short loc_149D\nadd ebx, 1\nloc_1511:\ncmp r8d, ebx\ncmovl r8d, ebx\nadd r9, 10h\ncmp r10, r9\njnz loc_146C\nadd r8d, 1\nloc_1529:\ncmp r12d, r8d\ncmovl r12d, r8d\nadd r14, 10h\ncmp rdx, r14\njnz loc_1439\nmov ecx, [rsp+78h+var_74]\nadd r12d, 1\nloc_1545:\ncmp ecx, r12d\ncmovl ecx, r12d\nadd r13, 10h\ncmp rbp, r13\njnz loc_1402\nmov r13d, ecx\nmov r12d, [rsp+78h+var_70]\nmov r14, rsi\nadd r13d, 1\nloc_1568:\ncmp r12d, r13d\ncmovl r12d, r13d\nadd r15, 10h\ncmp r14, r15\njnz loc_13BE\nadd rsp, 48h\nlea eax, [r12+1]\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1590:\nxor eax, eax\njmp loc_1500\nloc_15A0:\nxor ebx, ebx\njmp loc_1511\nloc_15B0:\nxor r8d, r8d\njmp loc_1529\nloc_15C0:\nxor r12d, r12d\njmp short loc_1545\nloc_15C8:\nxor r13d, r13d\njmp short loc_1568\nloc_15CD:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1390(int *a1)\n{\n __int64 v1; // rdx\n int v2; // r12d\n __int64 v3; // r15\n __int64 v4; // r14\n int *v5; // rdx\n __int64 v6; // rax\n int v7; // r13d\n __int64 v8; // rsi\n __int64 v9; // rbp\n int v10; // ecx\n __int64 v11; // r13\n int *v12; // rdx\n __int64 v13; // rax\n int v14; // r12d\n __int64 v15; // r14\n int v16; // r12d\n __int64 v17; // rdx\n int *v18; // rax\n __int64 v19; // r10\n int v20; // r8d\n __int64 v21; // r9\n int v22; // r8d\n __int64 v23; // r10\n int *v24; // rax\n __int64 v25; // r11\n int v26; // ebx\n __int64 v27; // rcx\n int v28; // ebx\n __int64 v29; // r11\n _DWORD *v30; // rdi\n int v31; // eax\n int v33; // [rsp+0h] [rbp-74h]\n int v34; // [rsp+4h] [rbp-70h]\n int v35; // [rsp+8h] [rbp-6Ch]\n __int64 v36; // [rsp+14h] [rbp-60h]\n __int64 v37; // [rsp+1Ch] [rbp-58h]\n __int64 v38; // [rsp+24h] [rbp-50h]\n __int64 v39; // [rsp+2Ch] [rbp-48h]\n __int64 v40; // [rsp+34h] [rbp-40h]\n\n v1 = *a1;\n if ( (int)v1 <= 0 )\n return 1LL;\n v2 = 0;\n v3 = *((_QWORD *)a1 + 1);\n v4 = 16 * v1 + v3;\n do\n {\n v5 = *(int **)(v3 + 8);\n if ( v5 )\n {\n v6 = *v5;\n v7 = 1;\n if ( (int)v6 > 0 )\n {\n v34 = v2;\n v8 = v4;\n v9 = 16 * v6 + *((_QWORD *)v5 + 1);\n v10 = 0;\n v11 = *((_QWORD *)v5 + 1);\n do\n {\n v12 = *(int **)(v11 + 8);\n if ( v12 )\n {\n v13 = *v12;\n v14 = 1;\n if ( (int)v13 > 0 )\n {\n v15 = *((_QWORD *)v12 + 1);\n v33 = v10;\n v16 = 0;\n v17 = 16 * v13 + v15;\n do\n {\n v18 = *(int **)(v15 + 8);\n if ( v18 )\n {\n v19 = *v18;\n v20 = 1;\n if ( (int)v19 > 0 )\n {\n v21 = *((_QWORD *)v18 + 1);\n v22 = 0;\n v23 = v21 + 16 * v19;\n do\n {\n v24 = *(int **)(v21 + 8);\n if ( v24 )\n {\n v25 = *v24;\n v26 = 1;\n if ( (int)v25 > 0 )\n {\n v27 = *((_QWORD *)v24 + 1);\n v28 = 0;\n v29 = v27 + 16 * v25;\n do\n {\n v30 = *(_DWORD **)(v27 + 8);\n if ( v30 )\n {\n v31 = 1;\n if ( *v30 )\n {\n v40 = v27;\n v39 = v29;\n v38 = v21;\n v37 = v23;\n v36 = v17;\n v35 = v22;\n v31 = sub_1390();\n v22 = v35;\n v17 = v36;\n v23 = v37;\n v21 = v38;\n v29 = v39;\n v27 = v40;\n }\n }\n else\n {\n v31 = 0;\n }\n if ( v28 < v31 )\n v28 = v31;\n v27 += 16LL;\n }\n while ( v29 != v27 );\n v26 = v28 + 1;\n }\n }\n else\n {\n v26 = 0;\n }\n if ( v22 < v26 )\n v22 = v26;\n v21 += 16LL;\n }\n while ( v23 != v21 );\n v20 = v22 + 1;\n }\n }\n else\n {\n v20 = 0;\n }\n if ( v16 < v20 )\n v16 = v20;\n v15 += 16LL;\n }\n while ( v17 != v15 );\n v10 = v33;\n v14 = v16 + 1;\n }\n }\n else\n {\n v14 = 0;\n }\n if ( v10 < v14 )\n v10 = v14;\n v11 += 16LL;\n }\n while ( v9 != v11 );\n v2 = v34;\n v4 = v8;\n v7 = v10 + 1;\n }\n }\n else\n {\n v7 = 0;\n }\n if ( v2 < v7 )\n v2 = v7;\n v3 += 16LL;\n }\n while ( v4 != v3 );\n return (unsigned int)(v2 + 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1390(int *a1) {\n long long v1;\n int v2;\n long long v3;\n long long v4;\n int *v5;\n long long v6;\n int v7;\n long long v8;\n long long v9;\n int v10;\n long long v11;\n int *v12;\n long long v13;\n int v14;\n long long v15;\n int v16;\n long long v17;\n int *v18;\n long long v19;\n int v20;\n long long v21;\n int v22;\n long long v23;\n int *v24;\n long long v25;\n int v26;\n long long v27;\n int v28;\n long long v29;\n uint32_t *v30;\n int v31;\n int v33;\n int v34;\n int v35;\n long long v36;\n long long v37;\n long long v38;\n long long v39;\n long long v40;\n v1 = *a1;\n if ((int)v1 <= 0) return 1LL;\n v2 = 0;\n v3 = *((uint64_t *)a1 + 1);\n v4 = 16 * v1 + v3;\n do {\n v5 = *(int **)(v3 + 8);\n if (v5) {\n v6 = *v5;\n v7 = 1;\n if ((int)v6 > 0) {\n v34 = v2;\n v8 = v4;\n v9 = 16 * v6 + *((uint64_t *)v5 + 1);\n v10 = 0;\n v11 = *((uint64_t *)v5 + 1);\n do {\n v12 = *(int **)(v11 + 8);\n if (v12) {\n v13 = *v12;\n v14 = 1;\n if ((int)v13 > 0) {\n v15 = *((uint64_t *)v12 + 1);\n v33 = v10;\n v16 = 0;\n v17 = 16 * v13 + v15;\n do {\n v18 = *(int **)(v15 + 8);\n if (v18) {\n v19 = *v18;\n v20 = 1;\n if ((int)v19 > 0) {\n v21 = *((uint64_t *)v18 + 1);\n v22 = 0;\n v23 = v21 + 16 * v19;\n do {\n v24 = *(int **)(v21 + 8);\n if (v24) {\n v25 = *v24;\n v26 = 1;\n if ((int)v25 > 0) {\n v27 = *((uint64_t *)v24 + 1);\n v28 = 0;\n v29 = v27 + 16 * v25;\n do {\n v30 = *(uint32_t **)(v27 + 8);\n if (v30) {\n v31 = 1;\n if (*v30) {\n v40 = v27;\n v39 = v29;\n v38 = v21;\n v37 = v23;\n v36 = v17;\n v35 = v22;\n v31 = sub_1390();\n v22 = v35;\n v17 = v36;\n v23 = v37;\n v21 = v38;\n v29 = v39;\n v27 = v40;\n }\n } else {\n v31 = 0;\n }\n if (v28 < v31) v28 = v31;\n v27 += 16LL;\n } while (v29 != v27);\n v26 = v28 + 1;\n }\n } else {\n v26 = 0;\n }\n if (v22 < v26) v22 = v26;\n v21 += 16LL;\n } while (v23 != v21);\n v20 = v22 + 1;\n }\n } else {\n v20 = 0;\n }\n if (v16 < v20) v16 = v20;\n v15 += 16LL;\n } while (v17 != v15);\n v10 = v33;\n v14 = v16 + 1;\n }\n } else {\n v14 = 0;\n }\n if (v10 < v14) v10 = v14;\n v11 += 16LL;\n } while (v9 != v11);\n v2 = v34;\n v4 = v8;\n v7 = v10 + 1;\n }\n } else {\n v7 = 0;\n }\n if (v2 < v7) v2 = v7;\n v3 += 16LL;\n } while (v4 != v3);\n return (unsigned int)(v2 + 1);\n}", + "ida_pseudo_norm": "long long func0_part_0(int *a1) {\n long long v1;\n int v2;\n long long v3;\n long long v4;\n int *v5;\n long long v6;\n int v7;\n long long v8;\n long long v9;\n int v10;\n long long v11;\n int *v12;\n long long v13;\n int v14;\n long long v15;\n int v16;\n long long v17;\n int *v18;\n long long v19;\n int v20;\n long long v21;\n int v22;\n long long v23;\n int *v24;\n long long v25;\n int v26;\n long long v27;\n int v28;\n long long v29;\n uint32_t *v30;\n int v31;\n int v33;\n int v34;\n int v35;\n long long v36;\n long long v37;\n long long v38;\n long long v39;\n long long v40;\n v1 = *a1;\n if ((int)v1 <= 0) return 1LL;\n v2 = 0;\n v3 = *((uint64_t *)a1 + 1);\n v4 = 16 * v1 + v3;\n do {\n v5 = *(int **)(v3 + 8);\n if (v5) {\n v6 = *v5;\n v7 = 1;\n if ((int)v6 > 0) {\n v34 = v2;\n v8 = v4;\n v9 = 16 * v6 + *((uint64_t *)v5 + 1);\n v10 = 0;\n v11 = *((uint64_t *)v5 + 1);\n do {\n v12 = *(int **)(v11 + 8);\n if (v12) {\n v13 = *v12;\n v14 = 1;\n if ((int)v13 > 0) {\n v15 = *((uint64_t *)v12 + 1);\n v33 = v10;\n v16 = 0;\n v17 = 16 * v13 + v15;\n do {\n v18 = *(int **)(v15 + 8);\n if (v18) {\n v19 = *v18;\n v20 = 1;\n if ((int)v19 > 0) {\n v21 = *((uint64_t *)v18 + 1);\n v22 = 0;\n v23 = v21 + 16 * v19;\n do {\n v24 = *(int **)(v21 + 8);\n if (v24) {\n v25 = *v24;\n v26 = 1;\n if ((int)v25 > 0) {\n v27 = *((uint64_t *)v24 + 1);\n v28 = 0;\n v29 = v27 + 16 * v25;\n do {\n v30 = *(uint32_t **)(v27 + 8);\n if (v30) {\n v31 = 1;\n if (*v30) {\n v40 = v27;\n v39 = v29;\n v38 = v21;\n v37 = v23;\n v36 = v17;\n v35 = v22;\n v31 = func0_part_0();\n v22 = v35;\n v17 = v36;\n v23 = v37;\n v21 = v38;\n v29 = v39;\n v27 = v40;\n }\n } else {\n v31 = 0;\n }\n if (v28 < v31) v28 = v31;\n v27 += 16LL;\n } while (v29 != v27);\n v26 = v28 + 1;\n }\n } else {\n v26 = 0;\n }\n if (v22 < v26) v22 = v26;\n v21 += 16LL;\n } while (v23 != v21);\n v20 = v22 + 1;\n }\n } else {\n v20 = 0;\n }\n if (v16 < v20) v16 = v20;\n v15 += 16LL;\n } while (v17 != v15);\n v10 = v33;\n v14 = v16 + 1;\n }\n } else {\n v14 = 0;\n }\n if (v10 < v14) v10 = v14;\n v11 += 16LL;\n } while (v9 != v11);\n v2 = v34;\n v4 = v8;\n v7 = v10 + 1;\n }\n } else {\n v7 = 0;\n }\n if (v2 < v7) v2 = v7;\n v3 += 16LL;\n } while (v4 != v3);\n return (unsigned int)(v2 + 1);\n}" + }, + { + "index": 302, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n == 0) return 0;\n int msb = 0;\n n = n / 2;\n while (n > 0) {\n n = n / 2;\n msb++;\n }\n return (1 << msb);\n}", + "test": "int main() {\n\n assert(func0(6) == 4);\n\n assert(func0(10) == 8);\n\n assert(func0(18) == 16);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\ncmpl $0x0,-0x14(%rbp)\njne 1161 \nmov $0x0,%eax\njmp 11a0 \nmovl $0x0,-0x4(%rbp)\nmov -0x14(%rbp),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nmov %eax,-0x14(%rbp)\njmp 118c \nmov -0x14(%rbp),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nmov %eax,-0x14(%rbp)\naddl $0x1,-0x4(%rbp)\ncmpl $0x0,-0x14(%rbp)\njg 1179 \nmov -0x4(%rbp),%eax\nmov $0x1,%edx\nmov %eax,%ecx\nshl %cl,%edx\nmov %edx,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\ncmp [rbp+var_14], 0\njnz short loc_1161\nmov eax, 0\njmp short loc_11A0\nloc_1161:\nmov [rbp+var_4], 0\nmov eax, [rbp+var_14]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_14], eax\njmp short loc_118C\nloc_1179:\nmov eax, [rbp+var_14]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_14], eax\nadd [rbp+var_4], 1\nloc_118C:\ncmp [rbp+var_14], 0\njg short loc_1179\nmov eax, [rbp+var_4]\nmov edx, 1\nmov ecx, eax\nshl edx, cl\nmov eax, edx\nloc_11A0:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int i; // [rsp+0h] [rbp-14h]\n char v3; // [rsp+10h] [rbp-4h]\n\n if ( !a1 )\n return 0LL;\n v3 = 0;\n for ( i = a1 / 2; i > 0; i /= 2 )\n ++v3;\n return (unsigned int)(1 << v3);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\ncmp [rbp+var_14], 0\njnz short loc_1161\nmov eax, 0\njmp short loc_11A0\nloc_1161:\nmov [rbp+var_4], 0\nmov eax, [rbp+var_14]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_14], eax\njmp short loc_118C\nloc_1179:\nmov eax, [rbp+var_14]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_14], eax\nadd [rbp+var_4], 1\nloc_118C:\ncmp [rbp+var_14], 0\njg short loc_1179\nmov eax, [rbp+var_4]\nmov edx, 1\nmov ecx, eax\nshl edx, cl\nmov eax, edx\nloc_11A0:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int i; // [rsp+0h] [rbp-14h]\n char v3; // [rsp+10h] [rbp-4h]\n\n if ( !a1 )\n return 0LL;\n v3 = 0;\n for ( i = a1 / 2; i > 0; i /= 2 )\n ++v3;\n return (unsigned int)(1 << v3);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int i;\n char v3;\n if (!a1) return 0LL;\n v3 = 0;\n for (i = a1 / 2; i > 0; i /= 2) ++v3;\n return (unsigned int)(1 << v3);\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int i;\n char v3;\n if (!a1) return 0LL;\n v3 = 0;\n for (i = a1 / 2; i > 0; i /= 2) ++v3;\n return (unsigned int)(1 << v3);\n}" + }, + { + "index": 302, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n == 0) return 0;\n int msb = 0;\n n = n / 2;\n while (n > 0) {\n n = n / 2;\n msb++;\n }\n return (1 << msb);\n}", + "test": "int main() {\n\n assert(func0(6) == 4);\n\n assert(func0(10) == 8);\n\n assert(func0(18) == 16);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %edi,%eax\ntest %edi,%edi\nje 117e \nshr $0x1f,%eax\nadd %edi,%eax\nsar %eax\ncmp $0x1,%edi\njle 117f \nmov $0x0,%ecx\nmov %eax,%edx\nmov %eax,%esi\nshr $0x1f,%esi\nadd %esi,%eax\nsar %eax\nadd $0x1,%ecx\ncmp $0x1,%edx\njg 1164 \nmov $0x1,%eax\nshl %cl,%eax\nretq\nmov $0x0,%ecx\njmp 1177 \n", + "ida_asm": "func0:\nendbr64\nmov eax, edi\ntest edi, edi\njz short locret_117E\nshr eax, 1Fh\nadd eax, edi\nsar eax, 1\ncmp edi, 1\njle short loc_117F\nmov ecx, 0\nloc_1164:\nmov edx, eax\nmov esi, eax\nshr esi, 1Fh\nadd eax, esi\nsar eax, 1\nadd ecx, 1\ncmp edx, 1\njg short loc_1164\nloc_1177:\nmov eax, 1\nshl eax, cl\nlocret_117E:\nretn\nloc_117F:\nmov ecx, 0\njmp short loc_1177", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n __int64 result; // rax\n int v2; // eax\n char v3; // cl\n int v4; // edx\n\n result = (unsigned int)a1;\n if ( a1 )\n {\n v2 = a1 / 2;\n if ( a1 <= 1 )\n {\n v3 = 0;\n }\n else\n {\n v3 = 0;\n do\n {\n v4 = v2;\n v2 /= 2;\n ++v3;\n }\n while ( v4 > 1 );\n }\n return (unsigned int)(1 << v3);\n }\n return result;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmov eax, edi\ntest edi, edi\njz short locret_117E\nshr eax, 1Fh\nadd eax, edi\nsar eax, 1\ncmp edi, 1\njle short loc_117F\nmov ecx, 0\nloc_1164:\nmov edx, eax\nmov esi, eax\nshr esi, 1Fh\nadd eax, esi\nsar eax, 1\nadd ecx, 1\ncmp edx, 1\njg short loc_1164\nloc_1177:\nmov eax, 1\nshl eax, cl\nlocret_117E:\nretn\nloc_117F:\nmov ecx, 0\njmp short loc_1177", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n __int64 result; // rax\n int v2; // eax\n char v3; // cl\n int v4; // edx\n\n result = (unsigned int)a1;\n if ( a1 )\n {\n v2 = a1 / 2;\n if ( a1 <= 1 )\n {\n v3 = 0;\n }\n else\n {\n v3 = 0;\n do\n {\n v4 = v2;\n v2 /= 2;\n ++v3;\n }\n while ( v4 > 1 );\n }\n return (unsigned int)(1 << v3);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n long long result;\n int v2;\n char v3;\n int v4;\n result = (unsigned int)a1;\n if (a1) {\n v2 = a1 / 2;\n if (a1 <= 1) {\n v3 = 0;\n } else {\n v3 = 0;\n do {\n v4 = v2;\n v2 /= 2;\n ++v3;\n } while (v4 > 1);\n }\n return (unsigned int)(1 << v3);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n long long result;\n int v2;\n char v3;\n int v4;\n result = (unsigned int)a1;\n if (a1) {\n v2 = a1 / 2;\n if (a1 <= 1) {\n v3 = 0;\n } else {\n v3 = 0;\n do {\n v4 = v2;\n v2 /= 2;\n ++v3;\n } while (v4 > 1);\n }\n return (unsigned int)(1 << v3);\n }\n return result;\n}" + }, + { + "index": 303, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int a[], int n) {\n int mx = INT_MIN;\n for (int j = 1; j < n; j++) {\n if (mx > a[j]) {\n return 0;\n }\n if (a[j - 1] > mx) {\n mx = a[j - 1];\n }\n }\n return 1;\n}", + "test": "int main() {\n\n int arr1[] = {1, 0, 2};\n\n int arr2[] = {1, 2, 0};\n\n int arr3[] = {1, 2, 1};\n\n\n\n assert(func0(arr1, 3) == 1);\n\n assert(func0(arr2, 3) == 0);\n\n assert(func0(arr3, 3) == 1);\n\n\n\n printf(\"All tests passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x80000000,-0x8(%rbp)\nmovl $0x1,-0x4(%rbp)\njmp 1202 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x8(%rbp)\njle 11ca \nmov $0x0,%eax\njmp 120f \nmov -0x4(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x8(%rbp)\njge 11fe \nmov -0x4(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11a8 \nmov $0x1,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 80000000h\nmov [rbp+var_4], 1\njmp short loc_1202\nloc_11A8:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_8], eax\njle short loc_11CA\nmov eax, 0\njmp short loc_120F\nloc_11CA:\nmov eax, [rbp+var_4]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_8], eax\njge short loc_11FE\nmov eax, [rbp+var_4]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_8], eax\nloc_11FE:\nadd [rbp+var_4], 1\nloc_1202:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11A8\nmov eax, 1\nloc_120F:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n signed int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0x80000000;\n for ( i = 1; i < a2; ++i )\n {\n if ( v3 > *(_DWORD *)(4LL * i + a1) )\n return 0LL;\n if ( v3 < *(_DWORD *)(4LL * i - 4 + a1) )\n v3 = *(_DWORD *)(4LL * i - 4 + a1);\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 80000000h\nmov [rbp+var_4], 1\njmp short loc_1202\nloc_11A8:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_8], eax\njle short loc_11CA\nmov eax, 0\njmp short loc_120F\nloc_11CA:\nmov eax, [rbp+var_4]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_8], eax\njge short loc_11FE\nmov eax, [rbp+var_4]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_8], eax\nloc_11FE:\nadd [rbp+var_4], 1\nloc_1202:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11A8\nmov eax, 1\nloc_120F:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2)\n{\n signed int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0x80000000;\n for ( i = 1; i < a2; ++i )\n {\n if ( v3 > *(_DWORD *)(4LL * i + a1) )\n return 0LL;\n if ( v3 < *(_DWORD *)(4LL * i - 4 + a1) )\n v3 = *(_DWORD *)(4LL * i - 4 + a1);\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2) {\n signed int v3;\n int i;\n v3 = 2147483648;\n for (i = 1; i < a2; ++i) {\n if (v3 > *(uint32_t *)(4LL * i + a1)) return 0LL;\n if (v3 < *(uint32_t *)(4LL * i - 4 + a1))\n v3 = *(uint32_t *)(4LL * i - 4 + a1);\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n signed int v3;\n int i;\n v3 = 2147483648;\n for (i = 1; i < a2; ++i) {\n if (v3 > *(uint32_t *)(4LL * i + a1)) return 0LL;\n if (v3 < *(uint32_t *)(4LL * i - 4 + a1))\n v3 = *(uint32_t *)(4LL * i - 4 + a1);\n }\n return 1LL;\n}" + }, + { + "index": 303, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int a[], int n) {\n int mx = INT_MIN;\n for (int j = 1; j < n; j++) {\n if (mx > a[j]) {\n return 0;\n }\n if (a[j - 1] > mx) {\n mx = a[j - 1];\n }\n }\n return 1;\n}", + "test": "int main() {\n\n int arr1[] = {1, 0, 2};\n\n int arr2[] = {1, 2, 0};\n\n int arr3[] = {1, 2, 1};\n\n\n\n assert(func0(arr1, 3) == 1);\n\n assert(func0(arr2, 3) == 0);\n\n assert(func0(arr3, 3) == 1);\n\n\n\n printf(\"All tests passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%esi\njle 11bc \nmov %rdi,%rax\nlea -0x2(%rsi),%edx\nlea (%rdi,%rdx,4),%rsi\nmov $0x80000000,%edx\nmov (%rax),%ecx\ncmp %ecx,%edx\ncmovl %ecx,%edx\ncmp %rsi,%rax\nje 11c2 \nadd $0x4,%rax\ncmp %edx,0x4(%rax)\njge 11a1 \nmov $0x0,%eax\nretq\nmov $0x1,%eax\nretq\nmov $0x1,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ncmp esi, 1\njle short loc_11BD\nmov rax, rdi\nlea edx, [rsi-2]\nlea rsi, [rdi+rdx*4+4]\nmov edx, 80000000h\nloc_11A2:\ncmp [rax+4], edx\njl short loc_11C3\nmov ecx, [rax]\ncmp edx, ecx\ncmovl edx, ecx\nadd rax, 4\ncmp rax, rsi\njnz short loc_11A2\nmov eax, 1\nretn\nloc_11BD:\nmov eax, 1\nretn\nloc_11C3:\nmov eax, 0\nretn", + "ida_pseudo": "__int64 __fastcall func0(signed int *a1, int a2)\n{\n signed int *v2; // rax\n __int64 v3; // rsi\n signed int v4; // edx\n\n if ( a2 <= 1 )\n return 1LL;\n v2 = a1;\n v3 = (__int64)&a1[a2 - 2 + 1];\n v4 = 0x80000000;\n while ( v2[1] >= v4 )\n {\n if ( v4 < *v2 )\n v4 = *v2;\n if ( ++v2 == (signed int *)v3 )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\ncmp esi, 1\njle short loc_11BD\nmov rax, rdi\nlea edx, [rsi-2]\nlea rsi, [rdi+rdx*4+4]\nmov edx, 80000000h\nloc_11A2:\ncmp [rax+4], edx\njl short loc_11C3\nmov ecx, [rax]\ncmp edx, ecx\ncmovl edx, ecx\nadd rax, 4\ncmp rax, rsi\njnz short loc_11A2\nmov eax, 1\nretn\nloc_11BD:\nmov eax, 1\nretn\nloc_11C3:\nmov eax, 0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(signed int *a1, int a2)\n{\n signed int *v2; // rax\n __int64 v3; // rsi\n signed int v4; // edx\n\n if ( a2 <= 1 )\n return 1LL;\n v2 = a1;\n v3 = (__int64)&a1[a2 - 2 + 1];\n v4 = 0x80000000;\n while ( v2[1] >= v4 )\n {\n if ( v4 < *v2 )\n v4 = *v2;\n if ( ++v2 == (signed int *)v3 )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(signed int *a1, int a2) {\n signed int *v2;\n long long v3;\n signed int v4;\n if (a2 <= 1) return 1LL;\n v2 = a1;\n v3 = (long long)&a1[a2 - 2 + 1];\n v4 = 2147483648;\n while (v2[1] >= v4) {\n if (v4 < *v2) v4 = *v2;\n if (++v2 == (signed int *)v3) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(signed int *a1, int a2) {\n signed int *v2;\n long long v3;\n signed int v4;\n if (a2 <= 1) return 1LL;\n v2 = a1;\n v3 = (long long)&a1[a2 - 2 + 1];\n v4 = 2147483648;\n while (v2[1] >= v4) {\n if (v4 < *v2) v4 = *v2;\n if (++v2 == (signed int *)v3) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 303, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int a[], int n) {\n int mx = INT_MIN;\n for (int j = 1; j < n; j++) {\n if (mx > a[j]) {\n return 0;\n }\n if (a[j - 1] > mx) {\n mx = a[j - 1];\n }\n }\n return 1;\n}", + "test": "int main() {\n\n int arr1[] = {1, 0, 2};\n\n int arr2[] = {1, 2, 0};\n\n int arr3[] = {1, 2, 1};\n\n\n\n assert(func0(arr1, 3) == 1);\n\n assert(func0(arr2, 3) == 0);\n\n assert(func0(arr3, 3) == 1);\n\n\n\n printf(\"All tests passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%esi\njle 11a0 \nlea -0x2(%rsi),%eax\nlea (%rdi,%rax,4),%rcx\nmov $0x80000000,%eax\nnopl (%rax)\nmov (%rdi),%edx\ncmp %edx,%eax\ncmovl %edx,%eax\ncmp %rcx,%rdi\nje 11a0 \nadd $0x4,%rdi\ncmp %eax,0x4(%rdi)\njge 1188 \nxor %eax,%eax\nretq\nmov $0x1,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ncmp esi, 1\njle short loc_12E0\nlea eax, [rsi-2]\nlea rcx, [rdi+rax*4+4]\nmov eax, 80000000h\njmp short loc_12D0\nloc_12C0:\nmov edx, [rdi]\ncmp eax, edx\ncmovl eax, edx\nadd rdi, 4\ncmp rdi, rcx\njz short loc_12E0\nloc_12D0:\ncmp [rdi+4], eax\njge short loc_12C0\nxor eax, eax\nretn\nloc_12E0:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(signed int *a1, int a2)\n{\n __int64 v2; // rcx\n signed int v3; // eax\n\n if ( a2 <= 1 )\n return 1LL;\n v2 = (__int64)&a1[a2 - 2 + 1];\n v3 = 0x80000000;\n while ( a1[1] >= v3 )\n {\n if ( v3 < *a1 )\n v3 = *a1;\n if ( ++a1 == (signed int *)v2 )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_12A0:\nendbr64\ncmp esi, 1\njle short loc_12E0\nlea eax, [rsi-2]\nlea rcx, [rdi+rax*4+4]\nmov eax, 80000000h\njmp short loc_12D0\nloc_12C0:\nmov edx, [rdi]\ncmp eax, edx\ncmovl eax, edx\nadd rdi, 4\ncmp rdi, rcx\njz short loc_12E0\nloc_12D0:\ncmp [rdi+4], eax\njge short loc_12C0\nxor eax, eax\nretn\nloc_12E0:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12A0(signed int *a1, int a2)\n{\n __int64 v2; // rcx\n signed int v3; // eax\n\n if ( a2 <= 1 )\n return 1LL;\n v2 = (__int64)&a1[a2 - 2 + 1];\n v3 = 0x80000000;\n while ( a1[1] >= v3 )\n {\n if ( v3 < *a1 )\n v3 = *a1;\n if ( ++a1 == (signed int *)v2 )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12A0(signed int *a1, int a2) {\n long long v2;\n signed int v3;\n if (a2 <= 1) return 1LL;\n v2 = (long long)&a1[a2 - 2 + 1];\n v3 = 2147483648;\n while (a1[1] >= v3) {\n if (v3 < *a1) v3 = *a1;\n if (++a1 == (signed int *)v2) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(signed int *a1, int a2) {\n long long v2;\n signed int v3;\n if (a2 <= 1) return 1LL;\n v2 = (long long)&a1[a2 - 2 + 1];\n v3 = 2147483648;\n while (a1[1] >= v3) {\n if (v3 < *a1) v3 = *a1;\n if (++a1 == (signed int *)v2) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 304, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int ranges[][2], int rotations, int index) {\n for (int i = rotations - 1; i >= 0; i--) {\n int left = ranges[i][0];\n int right = ranges[i][1];\n if (left <= index && right >= index) {\n if (index == left) {\n index = right;\n } else {\n index -= 1;\n }\n }\n }\n return arr[index];\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4, 5};\n\n int ranges1[][2] = {{0, 2}, {0, 3}};\n\n assert(func0(arr1, ranges1, 2, 1) == 3);\n\n\n\n int arr2[] = {1, 2, 3, 4};\n\n int ranges2[][2] = {{0, 1}, {0, 2}};\n\n assert(func0(arr2, ranges2, 1, 2) == 3);\n\n\n\n int arr3[] = {1, 2, 3, 4, 5, 6};\n\n int ranges3[][2] = {{0, 1}, {0, 2}};\n\n assert(func0(arr3, ranges3, 1, 1) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %edx,-0x24(%rbp)\nmov %ecx,-0x28(%rbp)\nmov -0x24(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0xc(%rbp)\njmp 11e5 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x8(%rbp)\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov 0x4(%rax),%eax\nmov %eax,-0x4(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x28(%rbp),%eax\njg 11e1 \nmov -0x4(%rbp),%eax\ncmp -0x28(%rbp),%eax\njl 11e1 \nmov -0x28(%rbp),%eax\ncmp -0x8(%rbp),%eax\njne 11dd \nmov -0x4(%rbp),%eax\nmov %eax,-0x28(%rbp)\njmp 11e1 \nsubl $0x1,-0x28(%rbp)\nsubl $0x1,-0xc(%rbp)\ncmpl $0x0,-0xc(%rbp)\njns 118a \nmov -0x28(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_28], ecx\nmov eax, [rbp+var_24]\nsub eax, 1\nmov [rbp+var_C], eax\njmp short loc_11E5\nloc_118A:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_8], eax\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov eax, [rax+4]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_28]\njg short loc_11E1\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_28]\njl short loc_11E1\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_8]\njnz short loc_11DD\nmov eax, [rbp+var_4]\nmov [rbp+var_28], eax\njmp short loc_11E1\nloc_11DD:\nsub [rbp+var_28], 1\nloc_11E1:\nsub [rbp+var_C], 1\nloc_11E5:\ncmp [rbp+var_C], 0\njns short loc_118A\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3, int a4)\n{\n int i; // [rsp+1Ch] [rbp-Ch]\n int v7; // [rsp+20h] [rbp-8h]\n\n for ( i = a3 - 1; i >= 0; --i )\n {\n v7 = *(_DWORD *)(8LL * i + a2);\n if ( v7 <= a4 && *(_DWORD *)(8LL * i + a2 + 4) >= a4 )\n {\n if ( a4 == v7 )\n a4 = *(_DWORD *)(8LL * i + a2 + 4);\n else\n --a4;\n }\n }\n return *(unsigned int *)(4LL * a4 + a1);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_28], ecx\nmov eax, [rbp+var_24]\nsub eax, 1\nmov [rbp+var_C], eax\njmp short loc_11E5\nloc_118A:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_8], eax\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov eax, [rax+4]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_28]\njg short loc_11E1\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_28]\njl short loc_11E1\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_8]\njnz short loc_11DD\nmov eax, [rbp+var_4]\nmov [rbp+var_28], eax\njmp short loc_11E1\nloc_11DD:\nsub [rbp+var_28], 1\nloc_11E1:\nsub [rbp+var_C], 1\nloc_11E5:\ncmp [rbp+var_C], 0\njns short loc_118A\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, int a3, int a4)\n{\n int i; // [rsp+1Ch] [rbp-Ch]\n int v7; // [rsp+20h] [rbp-8h]\n\n for ( i = a3 - 1; i >= 0; --i )\n {\n v7 = *(_DWORD *)(8LL * i + a2);\n if ( v7 <= a4 && *(_DWORD *)(8LL * i + a2 + 4) >= a4 )\n {\n if ( a4 == v7 )\n a4 = *(_DWORD *)(8LL * i + a2 + 4);\n else\n --a4;\n }\n }\n return *(unsigned int *)(4LL * a4 + a1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, int a3, int a4) {\n int i;\n int v7;\n for (i = a3 - 1; i >= 0; --i) {\n v7 = *(uint32_t *)(8LL * i + a2);\n if (v7 <= a4 && *(uint32_t *)(8LL * i + a2 + 4) >= a4) {\n if (a4 == v7)\n a4 = *(uint32_t *)(8LL * i + a2 + 4);\n else\n --a4;\n }\n }\n return *(unsigned int *)(4LL * a4 + a1);\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3, int a4) {\n int i;\n int v7;\n for (i = a3 - 1; i >= 0; --i) {\n v7 = *(uint32_t *)(8LL * i + a2);\n if (v7 <= a4 && *(uint32_t *)(8LL * i + a2 + 4) >= a4) {\n if (a4 == v7)\n a4 = *(uint32_t *)(8LL * i + a2 + 4);\n else\n --a4;\n }\n }\n return *(unsigned int *)(4LL * a4 + a1);\n}" + }, + { + "index": 304, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int ranges[][2], int rotations, int index) {\n for (int i = rotations - 1; i >= 0; i--) {\n int left = ranges[i][0];\n int right = ranges[i][1];\n if (left <= index && right >= index) {\n if (index == left) {\n index = right;\n } else {\n index -= 1;\n }\n }\n }\n return arr[index];\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4, 5};\n\n int ranges1[][2] = {{0, 2}, {0, 3}};\n\n assert(func0(arr1, ranges1, 2, 1) == 3);\n\n\n\n int arr2[] = {1, 2, 3, 4};\n\n int ranges2[][2] = {{0, 1}, {0, 2}};\n\n assert(func0(arr2, ranges2, 1, 2) == 3);\n\n\n\n int arr3[] = {1, 2, 3, 4, 5, 6};\n\n int ranges3[][2] = {{0, 1}, {0, 2}};\n\n assert(func0(arr3, ranges3, 1, 1) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edx,%edx\njle 11b2 \nmovslq %edx,%r8\nshl $0x3,%r8\nlea (%rsi,%r8,1),%rax\nlea -0x8(%rsi,%r8,1),%r8\nlea -0x1(%rdx),%edx\nshl $0x3,%rdx\nsub %rdx,%r8\njmp 11a2 \nlea -0x1(%rcx),%r9d\ncmp %ecx,%edx\ncmovne %r9d,%esi\nmov %esi,%ecx\nsub $0x8,%rax\ncmp %r8,%rax\nje 11b2 \nmov -0x8(%rax),%edx\nmov -0x4(%rax),%esi\ncmp %ecx,%edx\njg 1199 \ncmp %ecx,%esi\njge 118d \njmp 1199 \nmovslq %ecx,%rcx\nmov (%rdi,%rcx,4),%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov r9, rdi\ntest edx, edx\njle short loc_11B5\nmovsxd rdi, edx\nshl rdi, 3\nlea rax, [rsi+rdi]\nlea rdi, [rsi+rdi-8]\nlea edx, [rdx-1]\nshl rdx, 3\nsub rdi, rdx\njmp short loc_11A5\nloc_1190:\nlea r8d, [rcx-1]\ncmp edx, ecx\ncmovnz esi, r8d\nmov ecx, esi\nloc_119C:\nsub rax, 8\ncmp rax, rdi\njz short loc_11B5\nloc_11A5:\nmov edx, [rax-8]\nmov esi, [rax-4]\ncmp edx, ecx\njg short loc_119C\ncmp esi, ecx\njge short loc_1190\njmp short loc_119C\nloc_11B5:\nmovsxd rcx, ecx\nmov eax, [r9+rcx*4]\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3, int a4)\n{\n __int64 v5; // rax\n __int64 v6; // rdi\n int v7; // esi\n int v8; // edx\n\n if ( a3 > 0 )\n {\n v5 = a2 + 8LL * a3;\n v6 = v5 - 8 - 8LL * (unsigned int)(a3 - 1);\n do\n {\n v8 = *(_DWORD *)(v5 - 8);\n v7 = *(_DWORD *)(v5 - 4);\n if ( v8 <= a4 && v7 >= a4 )\n {\n if ( v8 != a4 )\n v7 = a4 - 1;\n a4 = v7;\n }\n v5 -= 8LL;\n }\n while ( v5 != v6 );\n }\n return *(unsigned int *)(a1 + 4LL * a4);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov r9, rdi\ntest edx, edx\njle short loc_11B5\nmovsxd rdi, edx\nshl rdi, 3\nlea rax, [rsi+rdi]\nlea rdi, [rsi+rdi-8]\nlea edx, [rdx-1]\nshl rdx, 3\nsub rdi, rdx\njmp short loc_11A5\nloc_1190:\nlea r8d, [rcx-1]\ncmp edx, ecx\ncmovnz esi, r8d\nmov ecx, esi\nloc_119C:\nsub rax, 8\ncmp rax, rdi\njz short loc_11B5\nloc_11A5:\nmov edx, [rax-8]\nmov esi, [rax-4]\ncmp edx, ecx\njg short loc_119C\ncmp esi, ecx\njge short loc_1190\njmp short loc_119C\nloc_11B5:\nmovsxd rcx, ecx\nmov eax, [r9+rcx*4]\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, int a3, int a4)\n{\n __int64 v5; // rax\n __int64 v6; // rdi\n int v7; // esi\n int v8; // edx\n\n if ( a3 > 0 )\n {\n v5 = a2 + 8LL * a3;\n v6 = v5 - 8 - 8LL * (unsigned int)(a3 - 1);\n do\n {\n v8 = *(_DWORD *)(v5 - 8);\n v7 = *(_DWORD *)(v5 - 4);\n if ( v8 <= a4 && v7 >= a4 )\n {\n if ( v8 != a4 )\n v7 = a4 - 1;\n a4 = v7;\n }\n v5 -= 8LL;\n }\n while ( v5 != v6 );\n }\n return *(unsigned int *)(a1 + 4LL * a4);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, int a3, int a4) {\n long long v5;\n long long v6;\n int v7;\n int v8;\n if (a3 > 0) {\n v5 = a2 + 8LL * a3;\n v6 = v5 - 8 - 8LL * (unsigned int)(a3 - 1);\n do {\n v8 = *(uint32_t *)(v5 - 8);\n v7 = *(uint32_t *)(v5 - 4);\n if (v8 <= a4 && v7 >= a4) {\n if (v8 != a4) v7 = a4 - 1;\n a4 = v7;\n }\n v5 -= 8LL;\n } while (v5 != v6);\n }\n return *(unsigned int *)(a1 + 4LL * a4);\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3, int a4) {\n long long v5;\n long long v6;\n int v7;\n int v8;\n if (a3 > 0) {\n v5 = a2 + 8LL * a3;\n v6 = v5 - 8 - 8LL * (unsigned int)(a3 - 1);\n do {\n v8 = *(uint32_t *)(v5 - 8);\n v7 = *(uint32_t *)(v5 - 4);\n if (v8 <= a4 && v7 >= a4) {\n if (v8 != a4) v7 = a4 - 1;\n a4 = v7;\n }\n v5 -= 8LL;\n } while (v5 != v6);\n }\n return *(unsigned int *)(a1 + 4LL * a4);\n}" + }, + { + "index": 304, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int ranges[][2], int rotations, int index) {\n for (int i = rotations - 1; i >= 0; i--) {\n int left = ranges[i][0];\n int right = ranges[i][1];\n if (left <= index && right >= index) {\n if (index == left) {\n index = right;\n } else {\n index -= 1;\n }\n }\n }\n return arr[index];\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4, 5};\n\n int ranges1[][2] = {{0, 2}, {0, 3}};\n\n assert(func0(arr1, ranges1, 2, 1) == 3);\n\n\n\n int arr2[] = {1, 2, 3, 4};\n\n int ranges2[][2] = {{0, 1}, {0, 2}};\n\n assert(func0(arr2, ranges2, 1, 2) == 3);\n\n\n\n int arr3[] = {1, 2, 3, 4, 5, 6};\n\n int ranges3[][2] = {{0, 1}, {0, 2}};\n\n assert(func0(arr3, ranges3, 1, 1) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %edx,%edx\njle 118b \nmovslq %edx,%r8\nsub $0x1,%edx\nshl $0x3,%r8\nshl $0x3,%rdx\nlea (%rsi,%r8,1),%rax\nlea -0x8(%rsi,%r8,1),%r8\nsub %rdx,%r8\nnopw 0x0(%rax,%rax,1)\nmov -0x8(%rax),%edx\nmov -0x4(%rax),%esi\ncmp %ecx,%edx\njg 1182 \ncmp %ecx,%esi\njl 1182 \nlea -0x1(%rcx),%r9d\ncmp %ecx,%edx\ncmovne %r9d,%esi\nmov %esi,%ecx\nsub $0x8,%rax\ncmp %rax,%r8\njne 1168 \nmovslq %ecx,%rcx\nmov (%rdi,%rcx,4),%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\nmov r9, rdi\ntest edx, edx\njle short loc_12F9\nmovsxd rdi, edx\nsub edx, 1\nshl rdi, 3\nshl rdx, 3\nlea rax, [rsi+rdi]\nlea rdi, [rsi+rdi-8]\nsub rdi, rdx\nnop dword ptr [rax]\nloc_12D8:\nmov edx, [rax-4]\nmov esi, [rax-8]\ncmp edx, ecx\njl short loc_12F0\ncmp esi, ecx\njg short loc_12F0\nlea r8d, [rcx-1]\ncmovnz edx, r8d\nmov ecx, edx\nloc_12F0:\nsub rax, 8\ncmp rax, rdi\njnz short loc_12D8\nloc_12F9:\nmovsxd rcx, ecx\nmov eax, [r9+rcx*4]\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3, int a4)\n{\n __int64 v5; // rax\n __int64 v6; // rdi\n int v7; // edx\n int v8; // esi\n\n if ( a3 > 0 )\n {\n v5 = a2 + 8LL * a3;\n v6 = v5 - 8 - 8LL * (unsigned int)(a3 - 1);\n do\n {\n v7 = *(_DWORD *)(v5 - 4);\n v8 = *(_DWORD *)(v5 - 8);\n if ( v7 >= a4 && v8 <= a4 )\n {\n if ( v8 != a4 )\n v7 = a4 - 1;\n a4 = v7;\n }\n v5 -= 8LL;\n }\n while ( v5 != v6 );\n }\n return *(unsigned int *)(a1 + 4LL * a4);\n}", + "ida_strip_asm": "sub_12B0:\nendbr64\nmov r9, rdi\ntest edx, edx\njle short loc_12F9\nmovsxd rdi, edx\nsub edx, 1\nshl rdi, 3\nshl rdx, 3\nlea rax, [rsi+rdi]\nlea rdi, [rsi+rdi-8]\nsub rdi, rdx\nnop dword ptr [rax]\nloc_12D8:\nmov edx, [rax-4]\nmov esi, [rax-8]\ncmp edx, ecx\njl short loc_12F0\ncmp esi, ecx\njg short loc_12F0\nlea r8d, [rcx-1]\ncmovnz edx, r8d\nmov ecx, edx\nloc_12F0:\nsub rax, 8\ncmp rax, rdi\njnz short loc_12D8\nloc_12F9:\nmovsxd rcx, ecx\nmov eax, [r9+rcx*4]\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12B0(__int64 a1, __int64 a2, int a3, int a4)\n{\n __int64 v5; // rax\n __int64 v6; // rdi\n int v7; // edx\n int v8; // esi\n\n if ( a3 > 0 )\n {\n v5 = a2 + 8LL * a3;\n v6 = v5 - 8 - 8LL * (unsigned int)(a3 - 1);\n do\n {\n v7 = *(_DWORD *)(v5 - 4);\n v8 = *(_DWORD *)(v5 - 8);\n if ( v7 >= a4 && v8 <= a4 )\n {\n if ( v8 != a4 )\n v7 = a4 - 1;\n a4 = v7;\n }\n v5 -= 8LL;\n }\n while ( v5 != v6 );\n }\n return *(unsigned int *)(a1 + 4LL * a4);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12B0(long long a1, long long a2, int a3, int a4) {\n long long v5;\n long long v6;\n int v7;\n int v8;\n if (a3 > 0) {\n v5 = a2 + 8LL * a3;\n v6 = v5 - 8 - 8LL * (unsigned int)(a3 - 1);\n do {\n v7 = *(uint32_t *)(v5 - 4);\n v8 = *(uint32_t *)(v5 - 8);\n if (v7 >= a4 && v8 <= a4) {\n if (v8 != a4) v7 = a4 - 1;\n a4 = v7;\n }\n v5 -= 8LL;\n } while (v5 != v6);\n }\n return *(unsigned int *)(a1 + 4LL * a4);\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3, int a4) {\n long long v5;\n long long v6;\n int v7;\n int v8;\n if (a3 > 0) {\n v5 = a2 + 8LL * a3;\n v6 = v5 - 8 - 8LL * (unsigned int)(a3 - 1);\n do {\n v7 = *(uint32_t *)(v5 - 4);\n v8 = *(uint32_t *)(v5 - 8);\n if (v7 >= a4 && v8 <= a4) {\n if (v8 != a4) v7 = a4 - 1;\n a4 = v7;\n }\n v5 -= 8LL;\n } while (v5 != v6);\n }\n return *(unsigned int *)(a1 + 4LL * a4);\n}" + }, + { + "index": 305, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(char* words[], int size) {\n regex_t regex;\n regmatch_t matches[3];\n static char* result[2];\n int ret;\n ret = regcomp(®ex, \"(P\\\\w+)\\\\W(P\\\\w+)\", REG_EXTENDED);\n if (ret) {\n fprintf(stderr, \"Could not compile regex\\n\");\n return NULL;\n }\n for (int i = 0; i < size; i++) {\n ret = regexec(®ex, words[i], 3, matches, 0);\n if (!ret) {\n result[0] = strndup(words[i] + matches[1].rm_so,\n matches[1].rm_eo - matches[1].rm_so);\n result[1] = strndup(words[i] + matches[2].rm_so,\n matches[2].rm_eo - matches[2].rm_so);\n regfree(®ex);\n return result;\n }\n }\n regfree(®ex);\n return NULL;\n}", + "test": "int main() {\n\n char *test_words1[] = {\"Python PHP\", \"Java JavaScript\", \"c c++\"};\n\n char *test_words2[] = {\"Python Programming\", \"Java Programming\"};\n\n char *test_words3[] = {\"Pqrst Pqr\", \"qrstuv\"};\n\n \n\n char **result = func0(test_words1, 3);\n\n assert(result != NULL && strcmp(result[0], \"Python\") == 0 && strcmp(result[1], \"PHP\") == 0);\n\n \n\n result = func0(test_words2, 2);\n\n assert(result != NULL && strcmp(result[0], \"Python\") == 0 && strcmp(result[1], \"Programming\") == 0);\n\n \n\n result = func0(test_words3, 2);\n\n assert(result != NULL && strcmp(result[0], \"Pqrst\") == 0 && strcmp(result[1], \"Pqr\") == 0);\n\n \n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nadd $0xffffffffffffff80,%rsp\nmov %rdi,-0x78(%rbp)\nmov %esi,-0x7c(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea -0x60(%rbp),%rax\nmov $0x1,%edx\nlea 0xdad(%rip),%rsi\nmov %rax,%rdi\ncallq 10f0 \nmov %eax,-0x64(%rbp)\ncmpl $0x0,-0x64(%rbp)\nje 1296 \nmov 0x2dad(%rip),%rax\nmov %rax,%rcx\nmov $0x18,%edx\nmov $0x1,%esi\nlea 0xd90(%rip),%rdi\ncallq 1130 \nmov $0x0,%eax\njmpq 1398 \nmovl $0x0,-0x68(%rbp)\njmpq 137b \nmov -0x68(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x78(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rsi\nlea -0x20(%rbp),%rdx\nlea -0x60(%rbp),%rax\nmov $0x0,%r8d\nmov %rdx,%rcx\nmov $0x3,%edx\nmov %rax,%rdi\ncallq 1120 \nmov %eax,-0x64(%rbp)\ncmpl $0x0,-0x64(%rbp)\njne 1377 \nmov -0x14(%rbp),%edx\nmov -0x18(%rbp),%eax\nsub %eax,%edx\nmov %edx,%eax\ncltq\nmov -0x68(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x78(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rdx),%rcx\nmov -0x18(%rbp),%edx\nmovslq %edx,%rdx\nadd %rcx,%rdx\nmov %rax,%rsi\nmov %rdx,%rdi\ncallq 1100 \nmov %rax,0x2d0d(%rip)\nmov -0xc(%rbp),%edx\nmov -0x10(%rbp),%eax\nsub %eax,%edx\nmov %edx,%eax\ncltq\nmov -0x68(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x78(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rdx),%rcx\nmov -0x10(%rbp),%edx\nmovslq %edx,%rdx\nadd %rcx,%rdx\nmov %rax,%rsi\nmov %rdx,%rdi\ncallq 1100 \nmov %rax,0x2cd6(%rip)\nlea -0x60(%rbp),%rax\nmov %rax,%rdi\ncallq 10c0 \nlea 0x2cbb(%rip),%rax\njmp 1398 \naddl $0x1,-0x68(%rbp)\nmov -0x68(%rbp),%eax\ncmp -0x7c(%rbp),%eax\njl 12a2 \nlea -0x60(%rbp),%rax\nmov %rax,%rdi\ncallq 10c0 \nmov $0x0,%eax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 13ac \ncallq 10d0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nadd rsp, 0FFFFFFFFFFFFFF80h\nmov [rbp+var_78], rdi\nmov [rbp+var_7C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nlea rcx, pattern; \"(P\\\\w+)\\\\W(P\\\\w+)\"\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+var_64], eax\ncmp [rbp+var_64], 0\njz short loc_129C\nmov rax, cs:__bss_start\nmov rcx, rax; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rax, aCouldNotCompil; \"Could not compile regex\\n\"\nmov rdi, rax; ptr\ncall _fwrite\nmov eax, 0\njmp loc_139C\nloc_129C:\nmov [rbp+var_68], 0\njmp loc_137F\nloc_12A8:\nmov eax, [rbp+var_68]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_78]\nadd rax, rdx\nmov rsi, [rax]; string\nlea rdx, [rbp+pmatch]\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov rcx, rdx; pmatch\nmov edx, 3; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_64], eax\ncmp [rbp+var_64], 0\njnz loc_137B\nmov edx, [rbp+var_14]\nmov eax, [rbp+var_18]\nsub edx, eax\nmovsxd rax, edx\nmov edx, [rbp+var_68]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_78]\nadd rdx, rcx\nmov rcx, [rdx]\nmov edx, [rbp+var_18]\nmovsxd rdx, edx\nadd rdx, rcx\nmov rsi, rax; n\nmov rdi, rdx; string\ncall _strndup\nmov cs:result_1, rax\nmov edx, [rbp+var_C]\nmov eax, [rbp+var_10]\nsub edx, eax\nmovsxd rax, edx\nmov edx, [rbp+var_68]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_78]\nadd rdx, rcx\nmov rcx, [rdx]\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nadd rdx, rcx\nmov rsi, rax; n\nmov rdi, rdx; string\ncall _strndup\nmov cs:qword_4038, rax\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nlea rax, result_1\njmp short loc_139C\nloc_137B:\nadd [rbp+var_68], 1\nloc_137F:\nmov eax, [rbp+var_68]\ncmp eax, [rbp+var_7C]\njl loc_12A8\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nmov eax, 0\nloc_139C:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_13B0\ncall ___stack_chk_fail\nlocret_13B0:\nleave\nretn", + "ida_pseudo": "__int64 *__fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-68h]\n regex_t preg; // [rsp+20h] [rbp-60h] BYREF\n regmatch_t pmatch; // [rsp+60h] [rbp-20h] BYREF\n int v6; // [rsp+68h] [rbp-18h]\n int v7; // [rsp+6Ch] [rbp-14h]\n int v8; // [rsp+70h] [rbp-10h]\n int v9; // [rsp+74h] [rbp-Ch]\n unsigned __int64 v10; // [rsp+78h] [rbp-8h]\n\n v10 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"(P\\\\w+)\\\\W(P\\\\w+)\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n return 0LL;\n }\n else\n {\n for ( i = 0; i < a2; ++i )\n {\n if ( !regexec(&preg, *(const char **)(8LL * i + a1), 3uLL, &pmatch, 0) )\n {\n result_1 = (__int64)strndup((const char *)(*(_QWORD *)(8LL * i + a1) + v6), v7 - v6);\n qword_4038 = (__int64)strndup((const char *)(*(_QWORD *)(8LL * i + a1) + v8), v9 - v8);\n regfree(&preg);\n return &result_1;\n }\n }\n regfree(&preg);\n return 0LL;\n }\n}", + "ida_strip_asm": "sub_1229:\nendbr64\npush rbp\nmov rbp, rsp\nadd rsp, 0FFFFFFFFFFFFFF80h\nmov [rbp+var_78], rdi\nmov [rbp+var_7C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nlea rcx, pattern; \"(P\\\\w+)\\\\W(P\\\\w+)\"\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+var_64], eax\ncmp [rbp+var_64], 0\njz short loc_129C\nmov rax, cs:stderr\nmov rcx, rax; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rax, aCouldNotCompil; \"Could not compile regex\\n\"\nmov rdi, rax; ptr\ncall _fwrite\nmov eax, 0\njmp loc_139C\nloc_129C:\nmov [rbp+var_68], 0\njmp loc_137F\nloc_12A8:\nmov eax, [rbp+var_68]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_78]\nadd rax, rdx\nmov rsi, [rax]; string\nlea rdx, [rbp+pmatch]\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov rcx, rdx; pmatch\nmov edx, 3; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_64], eax\ncmp [rbp+var_64], 0\njnz loc_137B\nmov edx, [rbp+var_14]\nmov eax, [rbp+var_18]\nsub edx, eax\nmovsxd rax, edx\nmov edx, [rbp+var_68]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_78]\nadd rdx, rcx\nmov rcx, [rdx]\nmov edx, [rbp+var_18]\nmovsxd rdx, edx\nadd rdx, rcx\nmov rsi, rax; n\nmov rdi, rdx; string\ncall _strndup\nmov cs:qword_4030, rax\nmov edx, [rbp+var_C]\nmov eax, [rbp+var_10]\nsub edx, eax\nmovsxd rax, edx\nmov edx, [rbp+var_68]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_78]\nadd rdx, rcx\nmov rcx, [rdx]\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nadd rdx, rcx\nmov rsi, rax; n\nmov rdi, rdx; string\ncall _strndup\nmov cs:qword_4038, rax\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nlea rax, qword_4030\njmp short loc_139C\nloc_137B:\nadd [rbp+var_68], 1\nloc_137F:\nmov eax, [rbp+var_68]\ncmp eax, [rbp+var_7C]\njl loc_12A8\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nmov eax, 0\nloc_139C:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_13B0\ncall ___stack_chk_fail\nlocret_13B0:\nleave\nretn", + "ida_strip_pseudo": "__int64 *__fastcall sub_1229(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-68h]\n regex_t preg; // [rsp+20h] [rbp-60h] BYREF\n regmatch_t pmatch; // [rsp+60h] [rbp-20h] BYREF\n int v6; // [rsp+68h] [rbp-18h]\n int v7; // [rsp+6Ch] [rbp-14h]\n int v8; // [rsp+70h] [rbp-10h]\n int v9; // [rsp+74h] [rbp-Ch]\n unsigned __int64 v10; // [rsp+78h] [rbp-8h]\n\n v10 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"(P\\\\w+)\\\\W(P\\\\w+)\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n return 0LL;\n }\n else\n {\n for ( i = 0; i < a2; ++i )\n {\n if ( !regexec(&preg, *(const char **)(8LL * i + a1), 3uLL, &pmatch, 0) )\n {\n qword_4030 = (__int64)strndup((const char *)(*(_QWORD *)(8LL * i + a1) + v6), v7 - v6);\n qword_4038 = (__int64)strndup((const char *)(*(_QWORD *)(8LL * i + a1) + v8), v9 - v8);\n regfree(&preg);\n return &qword_4030;\n }\n }\n regfree(&preg);\n return 0LL;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long *sub_1229(long long a1, int a2) {\n int i;\n regex_t preg;\n regmatch_t pmatch;\n int v6;\n int v7;\n int v8;\n int v9;\n unsigned long long v10;\n v10 = __readfsqword(40u);\n if (regcomp(&preg, \"(P\\\\w+)\\\\W(P\\\\w+)\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n return 0LL;\n } else {\n for (i = 0; i < a2; ++i) {\n if (!regexec(&preg, *(const char **)(8LL * i + a1), 3uLL, &pmatch, 0)) {\n qword_4030 = (long long)strndup(\n (const char *)(*(uint64_t *)(8LL * i + a1) + v6), v7 - v6);\n qword_4038 = (long long)strndup(\n (const char *)(*(uint64_t *)(8LL * i + a1) + v8), v9 - v8);\n regfree(&preg);\n return &qword_4030;\n }\n }\n regfree(&preg);\n return 0LL;\n }\n}", + "ida_pseudo_norm": "long long *func0(long long a1, int a2) {\n int i;\n regex_t preg;\n regmatch_t pmatch;\n int v6;\n int v7;\n int v8;\n int v9;\n unsigned long long v10;\n v10 = __readfsqword(40u);\n if (regcomp(&preg, \"(P\\\\w+)\\\\W(P\\\\w+)\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n return 0LL;\n } else {\n for (i = 0; i < a2; ++i) {\n if (!regexec(&preg, *(const char **)(8LL * i + a1), 3uLL, &pmatch, 0)) {\n result_1 = (long long)strndup(\n (const char *)(*(uint64_t *)(8LL * i + a1) + v6), v7 - v6);\n qword_4038 = (long long)strndup(\n (const char *)(*(uint64_t *)(8LL * i + a1) + v8), v9 - v8);\n regfree(&preg);\n return &result_1;\n }\n }\n regfree(&preg);\n return 0LL;\n }\n}" + }, + { + "index": 305, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(char* words[], int size) {\n regex_t regex;\n regmatch_t matches[3];\n static char* result[2];\n int ret;\n ret = regcomp(®ex, \"(P\\\\w+)\\\\W(P\\\\w+)\", REG_EXTENDED);\n if (ret) {\n fprintf(stderr, \"Could not compile regex\\n\");\n return NULL;\n }\n for (int i = 0; i < size; i++) {\n ret = regexec(®ex, words[i], 3, matches, 0);\n if (!ret) {\n result[0] = strndup(words[i] + matches[1].rm_so,\n matches[1].rm_eo - matches[1].rm_so);\n result[1] = strndup(words[i] + matches[2].rm_so,\n matches[2].rm_eo - matches[2].rm_so);\n regfree(®ex);\n return result;\n }\n }\n regfree(®ex);\n return NULL;\n}", + "test": "int main() {\n\n char *test_words1[] = {\"Python PHP\", \"Java JavaScript\", \"c c++\"};\n\n char *test_words2[] = {\"Python Programming\", \"Java Programming\"};\n\n char *test_words3[] = {\"Pqrst Pqr\", \"qrstuv\"};\n\n \n\n char **result = func0(test_words1, 3);\n\n assert(result != NULL && strcmp(result[0], \"Python\") == 0 && strcmp(result[1], \"PHP\") == 0);\n\n \n\n result = func0(test_words2, 2);\n\n assert(result != NULL && strcmp(result[0], \"Python\") == 0 && strcmp(result[1], \"Programming\") == 0);\n\n \n\n result = func0(test_words3, 2);\n\n assert(result != NULL && strcmp(result[0], \"Pqrst\") == 0 && strcmp(result[1], \"Pqr\") == 0);\n\n \n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x68,%rsp\nmov %rdi,%r12\nmov %esi,%ebp\nmov %fs:0x28,%rax\nmov %rax,0x58(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nmov $0x1,%edx\nlea 0xdc9(%rip),%rsi\ncallq 10e0 \ntest %eax,%eax\njne 12aa \ntest %ebp,%ebp\njle 127e \nmov %r12,%rbx\nlea -0x1(%rbp),%eax\nlea 0x8(%r12,%rax,8),%r13\nlea 0x40(%rsp),%r12\nmov %rsp,%rdi\nmov $0x0,%r8d\nmov %r12,%rcx\nmov $0x3,%edx\nmov (%rbx),%rsi\ncallq 1100 \ntest %eax,%eax\nje 12ce \nadd $0x8,%rbx\ncmp %r13,%rbx\njne 1258 \nmov %rsp,%rdi\ncallq 10b0 \nmov $0x0,%eax\nmov 0x58(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 1324 \nadd $0x68,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nmov 0x2d6f(%rip),%rcx\nmov $0x18,%edx\nmov $0x1,%esi\nlea 0xd51(%rip),%rdi\ncallq 1110 \nmov $0x0,%eax\njmp 128b \nmov 0x48(%rsp),%eax\nmov 0x4c(%rsp),%esi\nsub %eax,%esi\nmovslq %esi,%rsi\ncltq\nadd (%rbx),%rax\nmov %rax,%rdi\ncallq 10f0 \nmov %rax,0x2d41(%rip)\nmov 0x50(%rsp),%eax\nmov 0x54(%rsp),%esi\nsub %eax,%esi\nmovslq %esi,%rsi\ncltq\nadd (%rbx),%rax\nmov %rax,%rdi\ncallq 10f0 \nmov %rax,0x2d28(%rip)\nmov %rsp,%rdi\ncallq 10b0 \nlea 0x2d11(%rip),%rax\njmpq 128b \ncallq 10c0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 60h\nmov r12, rdi\nmov ebp, esi\nmov rax, fs:28h\nmov [rsp+78h+var_20], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"(P\\\\w+)\\\\W(P\\\\w+)\"\ncall _regcomp\ntest eax, eax\njnz short loc_12C1\ntest ebp, ebp\njle short loc_129B\nmov rbx, r12\nmovsxd rbp, ebp\nlea r12, [r12+rbp*8]\nlea rbp, [rsp+78h+pmatch]\nloc_1275:\nmov rsi, [rbx]; string\nmov rdi, rsp; preg\nmov r8d, 0; eflags\nmov rcx, rbp; pmatch\nmov edx, 3; nmatch\ncall _regexec\ntest eax, eax\njz short loc_12E5\nadd rbx, 8\ncmp rbx, r12\njnz short loc_1275\nloc_129B:\nmov rdi, rsp; preg\ncall _regfree\nmov eax, 0\nloc_12A8:\nmov rdx, [rsp+78h+var_20]\nsub rdx, fs:28h\njnz short loc_1337\nadd rsp, 60h\npop rbx\npop rbp\npop r12\nretn\nloc_12C1:\nmov rcx, cs:__bss_start; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nmov eax, 0\njmp short loc_12A8\nloc_12E5:\nmov eax, [rsp+78h+var_30]\nmov esi, [rsp+78h+var_2C]\nsub esi, eax\nmovsxd rsi, esi; n\nmovsxd rdi, eax\nadd rdi, [rbx]; string\ncall _strndup\nmov cs:result_1, rax\nmov eax, [rsp+78h+var_28]\nmov esi, [rsp+78h+var_24]\nsub esi, eax\nmovsxd rsi, esi; n\nmovsxd rdi, eax\nadd rdi, [rbx]; string\ncall _strndup\nmov cs:qword_4038, rax\nmov rdi, rsp; preg\ncall _regfree\nlea rax, result_1\njmp loc_12A8\nloc_1337:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 *__fastcall func0(const char **a1, int a2)\n{\n const char **v2; // rbx\n regex_t v4; // [rsp+0h] [rbp-78h] BYREF\n regmatch_t pmatch; // [rsp+40h] [rbp-38h] BYREF\n int v6; // [rsp+48h] [rbp-30h]\n int v7; // [rsp+4Ch] [rbp-2Ch]\n int v8; // [rsp+50h] [rbp-28h]\n int v9; // [rsp+54h] [rbp-24h]\n unsigned __int64 v10; // [rsp+58h] [rbp-20h]\n\n v10 = __readfsqword(0x28u);\n if ( regcomp(&v4, \"(P\\\\w+)\\\\W(P\\\\w+)\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n return 0LL;\n }\n else if ( a2 <= 0 )\n {\nLABEL_6:\n regfree(&v4);\n return 0LL;\n }\n else\n {\n v2 = a1;\n while ( regexec(&v4, *v2, 3uLL, &pmatch, 0) )\n {\n if ( ++v2 == &a1[a2] )\n goto LABEL_6;\n }\n result_1 = (__int64)strndup(&(*v2)[v6], v7 - v6);\n qword_4038 = (__int64)strndup(&(*v2)[v8], v9 - v8);\n regfree(&v4);\n return &result_1;\n }\n}", + "ida_strip_asm": "sub_1229:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 60h\nmov r12, rdi\nmov ebp, esi\nmov rax, fs:28h\nmov [rsp+78h+var_20], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"(P\\\\w+)\\\\W(P\\\\w+)\"\ncall _regcomp\ntest eax, eax\njnz short loc_12C1\ntest ebp, ebp\njle short loc_129B\nmov rbx, r12\nmovsxd rbp, ebp\nlea r12, [r12+rbp*8]\nlea rbp, [rsp+78h+pmatch]\nloc_1275:\nmov rsi, [rbx]; string\nmov rdi, rsp; preg\nmov r8d, 0; eflags\nmov rcx, rbp; pmatch\nmov edx, 3; nmatch\ncall _regexec\ntest eax, eax\njz short loc_12E5\nadd rbx, 8\ncmp rbx, r12\njnz short loc_1275\nloc_129B:\nmov rdi, rsp; preg\ncall _regfree\nmov eax, 0\nloc_12A8:\nmov rdx, [rsp+78h+var_20]\nsub rdx, fs:28h\njnz short loc_1337\nadd rsp, 60h\npop rbx\npop rbp\npop r12\nretn\nloc_12C1:\nmov rcx, cs:stderr; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nmov eax, 0\njmp short loc_12A8\nloc_12E5:\nmov eax, [rsp+78h+var_30]\nmov esi, [rsp+78h+var_2C]\nsub esi, eax\nmovsxd rsi, esi; n\nmovsxd rdi, eax\nadd rdi, [rbx]; string\ncall _strndup\nmov cs:qword_4030, rax\nmov eax, [rsp+78h+var_28]\nmov esi, [rsp+78h+var_24]\nsub esi, eax\nmovsxd rsi, esi; n\nmovsxd rdi, eax\nadd rdi, [rbx]; string\ncall _strndup\nmov cs:qword_4038, rax\nmov rdi, rsp; preg\ncall _regfree\nlea rax, qword_4030\njmp loc_12A8\nloc_1337:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 *__fastcall sub_1229(const char **a1, int a2)\n{\n const char **v2; // rbx\n regex_t v4; // [rsp+0h] [rbp-78h] BYREF\n regmatch_t pmatch; // [rsp+40h] [rbp-38h] BYREF\n int v6; // [rsp+48h] [rbp-30h]\n int v7; // [rsp+4Ch] [rbp-2Ch]\n int v8; // [rsp+50h] [rbp-28h]\n int v9; // [rsp+54h] [rbp-24h]\n unsigned __int64 v10; // [rsp+58h] [rbp-20h]\n\n v10 = __readfsqword(0x28u);\n if ( regcomp(&v4, \"(P\\\\w+)\\\\W(P\\\\w+)\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n return 0LL;\n }\n else if ( a2 <= 0 )\n {\nLABEL_6:\n regfree(&v4);\n return 0LL;\n }\n else\n {\n v2 = a1;\n while ( regexec(&v4, *v2, 3uLL, &pmatch, 0) )\n {\n if ( ++v2 == &a1[a2] )\n goto LABEL_6;\n }\n qword_4030 = (__int64)strndup(&(*v2)[v6], v7 - v6);\n qword_4038 = (__int64)strndup(&(*v2)[v8], v9 - v8);\n regfree(&v4);\n return &qword_4030;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long *sub_1229(const char **a1, int a2) {\n const char **v2;\n regex_t v4;\n regmatch_t pmatch;\n int v6;\n int v7;\n int v8;\n int v9;\n unsigned long long v10;\n v10 = __readfsqword(40u);\n if (regcomp(&v4, \"(P\\\\w+)\\\\W(P\\\\w+)\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n return 0LL;\n } else if (a2 <= 0) {\n LABEL_6:\n regfree(&v4);\n return 0LL;\n } else {\n v2 = a1;\n while (regexec(&v4, *v2, 3uLL, &pmatch, 0)) {\n if (++v2 == &a1[a2]) goto LABEL_6;\n }\n qword_4030 = (long long)strndup(&(*v2)[v6], v7 - v6);\n qword_4038 = (long long)strndup(&(*v2)[v8], v9 - v8);\n regfree(&v4);\n return &qword_4030;\n }\n}", + "ida_pseudo_norm": "long long *func0(const char **a1, int a2) {\n const char **v2;\n regex_t v4;\n regmatch_t pmatch;\n int v6;\n int v7;\n int v8;\n int v9;\n unsigned long long v10;\n v10 = __readfsqword(40u);\n if (regcomp(&v4, \"(P\\\\w+)\\\\W(P\\\\w+)\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n return 0LL;\n } else if (a2 <= 0) {\n LABEL_6:\n regfree(&v4);\n return 0LL;\n } else {\n v2 = a1;\n while (regexec(&v4, *v2, 3uLL, &pmatch, 0)) {\n if (++v2 == &a1[a2]) goto LABEL_6;\n }\n result_1 = (long long)strndup(&(*v2)[v6], v7 - v6);\n qword_4038 = (long long)strndup(&(*v2)[v8], v9 - v8);\n regfree(&v4);\n return &result_1;\n }\n}" + }, + { + "index": 305, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(char* words[], int size) {\n regex_t regex;\n regmatch_t matches[3];\n static char* result[2];\n int ret;\n ret = regcomp(®ex, \"(P\\\\w+)\\\\W(P\\\\w+)\", REG_EXTENDED);\n if (ret) {\n fprintf(stderr, \"Could not compile regex\\n\");\n return NULL;\n }\n for (int i = 0; i < size; i++) {\n ret = regexec(®ex, words[i], 3, matches, 0);\n if (!ret) {\n result[0] = strndup(words[i] + matches[1].rm_so,\n matches[1].rm_eo - matches[1].rm_so);\n result[1] = strndup(words[i] + matches[2].rm_so,\n matches[2].rm_eo - matches[2].rm_so);\n regfree(®ex);\n return result;\n }\n }\n regfree(®ex);\n return NULL;\n}", + "test": "int main() {\n\n char *test_words1[] = {\"Python PHP\", \"Java JavaScript\", \"c c++\"};\n\n char *test_words2[] = {\"Python Programming\", \"Java Programming\"};\n\n char *test_words3[] = {\"Pqrst Pqr\", \"qrstuv\"};\n\n \n\n char **result = func0(test_words1, 3);\n\n assert(result != NULL && strcmp(result[0], \"Python\") == 0 && strcmp(result[1], \"PHP\") == 0);\n\n \n\n result = func0(test_words2, 2);\n\n assert(result != NULL && strcmp(result[0], \"Python\") == 0 && strcmp(result[1], \"Programming\") == 0);\n\n \n\n result = func0(test_words3, 2);\n\n assert(result != NULL && strcmp(result[0], \"Pqrst\") == 0 && strcmp(result[1], \"Pqr\") == 0);\n\n \n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov $0x1,%edx\npush %r12\npush %rbp\nmov %esi,%ebp\nlea 0xbfd(%rip),%rsi\npush %rbx\nmov %rdi,%rbx\nsub $0x68,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x58(%rsp)\nxor %eax,%eax\nmov %rsp,%r13\nmov %r13,%rdi\ncallq 10e0 \ntest %eax,%eax\njne 14f8 \ntest %ebp,%ebp\njle 14e8 \nlea -0x1(%rbp),%eax\nlea 0x40(%rsp),%rbp\nlea 0x8(%rbx,%rax,8),%r12\njmp 145d \nnopl 0x0(%rax)\nadd $0x8,%rbx\ncmp %r12,%rbx\nje 14e8 \nmov (%rbx),%rsi\nxor %r8d,%r8d\nmov %rbp,%rcx\nmov $0x3,%edx\nmov %r13,%rdi\ncallq 1100 \ntest %eax,%eax\njne 1450 \nmovslq 0x48(%rsp),%rax\nmov 0x4c(%rsp),%esi\nsub %eax,%esi\nadd (%rbx),%rax\nmovslq %esi,%rsi\nmov %rax,%rdi\ncallq 10f0 \nmov 0x54(%rsp),%esi\nmov %rax,0x2b95(%rip)\nmovslq 0x50(%rsp),%rax\nsub %eax,%esi\nadd (%rbx),%rax\nmovslq %esi,%rsi\nmov %rax,%rdi\ncallq 10f0 \nmov %r13,%rdi\nmov %rax,0x2b7e(%rip)\ncallq 10b0 \nlea 0x2b6a(%rip),%rax\nmov 0x58(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 1519 \nadd $0x68,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax)\nmov %r13,%rdi\ncallq 10b0 \nxor %eax,%eax\njmp 14c6 \nnopl 0x0(%rax)\nmov 0x2b21(%rip),%rcx\nmov $0x18,%edx\nmov $0x1,%esi\nlea 0xb03(%rip),%rdi\ncallq 1110 \nxor %eax,%eax\njmp 14c6 \ncallq 10c0 <__stack_chk_fail@plt>\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r13\nmov edx, 1; cflags\npush r12\nmovsxd r12, esi\nlea rsi, pattern; \"(P\\\\w+)\\\\W(P\\\\w+)\"\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 68h\nmov rax, fs:28h\nmov [rsp+var_s58], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njnz loc_1500\ntest r12d, r12d\njle loc_14F0\nlea r13, [rbx+r12*8]\nlea r12, [rsp+pmatch]\njmp short loc_146D\nloc_1460:\nadd rbx, 8\ncmp rbx, r13\njz loc_14F0\nloc_146D:\nmov rsi, [rbx]; string\nxor r8d, r8d; eflags\nmov rcx, r12; pmatch\nmov edx, 3; nmatch\nmov rdi, rbp; preg\ncall _regexec\ntest eax, eax\njnz short loc_1460\nmovsxd rdi, [rsp+var_s48]\nmov esi, [rsp+var_s4C]\nsub esi, edi\nadd rdi, [rbx]; string\nmovsxd rsi, esi; n\ncall _strndup\nmovsxd rdi, [rsp+var_s50]\nmov esi, [rsp+var_s54]\nmov cs:result_1, rax\nsub esi, edi\nadd rdi, [rbx]; string\nmovsxd rsi, esi; n\ncall _strndup\nmov rdi, rbp; preg\nmov cs:qword_4038, rax\ncall _regfree\nlea rax, result_1\nloc_14D0:\nmov rdx, [rsp+var_s58]\nsub rdx, fs:28h\njnz short loc_1521\nadd rsp, 68h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_14F0:\nmov rdi, rbp; preg\ncall _regfree\nxor eax, eax\njmp short loc_14D0\nloc_1500:\nmov rcx, cs:__bss_start; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nxor eax, eax\njmp short loc_14D0\nloc_1521:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 *__fastcall func0(const char **a1, int a2)\n{\n const char **v2; // rbx\n regex_t vars0; // [rsp+0h] [rbp+0h] BYREF\n regmatch_t pmatch; // [rsp+40h] [rbp+40h] BYREF\n int vars48; // [rsp+48h] [rbp+48h]\n int vars4C; // [rsp+4Ch] [rbp+4Ch]\n int vars50; // [rsp+50h] [rbp+50h]\n int vars54; // [rsp+54h] [rbp+54h]\n unsigned __int64 vars58; // [rsp+58h] [rbp+58h]\n\n v2 = a1;\n vars58 = __readfsqword(0x28u);\n if ( regcomp(&vars0, \"(P\\\\w+)\\\\W(P\\\\w+)\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n return 0LL;\n }\n else if ( a2 <= 0 )\n {\nLABEL_7:\n regfree(&vars0);\n return 0LL;\n }\n else\n {\n while ( regexec(&vars0, *v2, 3uLL, &pmatch, 0) )\n {\n if ( ++v2 == &a1[a2] )\n goto LABEL_7;\n }\n result_1 = (__int64)strndup(&(*v2)[vars48], vars4C - vars48);\n qword_4038 = (__int64)strndup(&(*v2)[vars50], vars54 - vars50);\n regfree(&vars0);\n return &result_1;\n }\n}", + "ida_strip_asm": "sub_1400:\nendbr64\npush r13\nmov edx, 1; cflags\npush r12\nmovsxd r12, esi\nlea rsi, pattern; \"(P\\\\w+)\\\\W(P\\\\w+)\"\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 68h\nmov rax, fs:28h\nmov [rsp+var_s58], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njnz loc_1500\ntest r12d, r12d\njle loc_14F0\nlea r13, [rbx+r12*8]\nlea r12, [rsp+pmatch]\njmp short loc_146D\nloc_1460:\nadd rbx, 8\ncmp rbx, r13\njz loc_14F0\nloc_146D:\nmov rsi, [rbx]; string\nxor r8d, r8d; eflags\nmov rcx, r12; pmatch\nmov edx, 3; nmatch\nmov rdi, rbp; preg\ncall _regexec\ntest eax, eax\njnz short loc_1460\nmovsxd rdi, [rsp+var_s48]\nmov esi, [rsp+var_s4C]\nsub esi, edi\nadd rdi, [rbx]; string\nmovsxd rsi, esi; n\ncall _strndup\nmovsxd rdi, [rsp+var_s50]\nmov esi, [rsp+var_s54]\nmov cs:qword_4030, rax\nsub esi, edi\nadd rdi, [rbx]; string\nmovsxd rsi, esi; n\ncall _strndup\nmov rdi, rbp; preg\nmov cs:qword_4038, rax\ncall _regfree\nlea rax, qword_4030\nloc_14D0:\nmov rdx, [rsp+var_s58]\nsub rdx, fs:28h\njnz short loc_1521\nadd rsp, 68h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_14F0:\nmov rdi, rbp; preg\ncall _regfree\nxor eax, eax\njmp short loc_14D0\nloc_1500:\nmov rcx, cs:stderr; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nxor eax, eax\njmp short loc_14D0\nloc_1521:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 *__fastcall sub_1400(const char **a1, int a2)\n{\n const char **v2; // rbx\n regex_t vars0; // [rsp+0h] [rbp+0h] BYREF\n regmatch_t pmatch; // [rsp+40h] [rbp+40h] BYREF\n int vars48; // [rsp+48h] [rbp+48h]\n int vars4C; // [rsp+4Ch] [rbp+4Ch]\n int vars50; // [rsp+50h] [rbp+50h]\n int vars54; // [rsp+54h] [rbp+54h]\n unsigned __int64 vars58; // [rsp+58h] [rbp+58h]\n\n v2 = a1;\n vars58 = __readfsqword(0x28u);\n if ( regcomp(&vars0, \"(P\\\\w+)\\\\W(P\\\\w+)\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n return 0LL;\n }\n else if ( a2 <= 0 )\n {\nLABEL_7:\n regfree(&vars0);\n return 0LL;\n }\n else\n {\n while ( regexec(&vars0, *v2, 3uLL, &pmatch, 0) )\n {\n if ( ++v2 == &a1[a2] )\n goto LABEL_7;\n }\n qword_4030 = (__int64)strndup(&(*v2)[vars48], vars4C - vars48);\n qword_4038 = (__int64)strndup(&(*v2)[vars50], vars54 - vars50);\n regfree(&vars0);\n return &qword_4030;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long *sub_1400(const char **a1, int a2) {\n const char **v2;\n regex_t vars0;\n regmatch_t pmatch;\n int vars48;\n int vars4C;\n int vars50;\n int vars54;\n unsigned long long vars58;\n v2 = a1;\n vars58 = __readfsqword(40u);\n if (regcomp(&vars0, \"(P\\\\w+)\\\\W(P\\\\w+)\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n return 0LL;\n } else if (a2 <= 0) {\n LABEL_7:\n regfree(&vars0);\n return 0LL;\n } else {\n while (regexec(&vars0, *v2, 3uLL, &pmatch, 0)) {\n if (++v2 == &a1[a2]) goto LABEL_7;\n }\n qword_4030 = (long long)strndup(&(*v2)[vars48], vars4C - vars48);\n qword_4038 = (long long)strndup(&(*v2)[vars50], vars54 - vars50);\n regfree(&vars0);\n return &qword_4030;\n }\n}", + "ida_pseudo_norm": "long long *func0(const char **a1, int a2) {\n const char **v2;\n regex_t vars0;\n regmatch_t pmatch;\n int vars48;\n int vars4C;\n int vars50;\n int vars54;\n unsigned long long vars58;\n v2 = a1;\n vars58 = __readfsqword(40u);\n if (regcomp(&vars0, \"(P\\\\w+)\\\\W(P\\\\w+)\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n return 0LL;\n } else if (a2 <= 0) {\n LABEL_7:\n regfree(&vars0);\n return 0LL;\n } else {\n while (regexec(&vars0, *v2, 3uLL, &pmatch, 0)) {\n if (++v2 == &a1[a2]) goto LABEL_7;\n }\n result_1 = (long long)strndup(&(*v2)[vars48], vars4C - vars48);\n qword_4038 = (long long)strndup(&(*v2)[vars50], vars54 - vars50);\n regfree(&vars0);\n return &result_1;\n }\n}" + }, + { + "index": 305, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(char* words[], int size) {\n regex_t regex;\n regmatch_t matches[3];\n static char* result[2];\n int ret;\n ret = regcomp(®ex, \"(P\\\\w+)\\\\W(P\\\\w+)\", REG_EXTENDED);\n if (ret) {\n fprintf(stderr, \"Could not compile regex\\n\");\n return NULL;\n }\n for (int i = 0; i < size; i++) {\n ret = regexec(®ex, words[i], 3, matches, 0);\n if (!ret) {\n result[0] = strndup(words[i] + matches[1].rm_so,\n matches[1].rm_eo - matches[1].rm_so);\n result[1] = strndup(words[i] + matches[2].rm_so,\n matches[2].rm_eo - matches[2].rm_so);\n regfree(®ex);\n return result;\n }\n }\n regfree(®ex);\n return NULL;\n}", + "test": "int main() {\n\n char *test_words1[] = {\"Python PHP\", \"Java JavaScript\", \"c c++\"};\n\n char *test_words2[] = {\"Python Programming\", \"Java Programming\"};\n\n char *test_words3[] = {\"Pqrst Pqr\", \"qrstuv\"};\n\n \n\n char **result = func0(test_words1, 3);\n\n assert(result != NULL && strcmp(result[0], \"Python\") == 0 && strcmp(result[1], \"PHP\") == 0);\n\n \n\n result = func0(test_words2, 2);\n\n assert(result != NULL && strcmp(result[0], \"Python\") == 0 && strcmp(result[1], \"Programming\") == 0);\n\n \n\n result = func0(test_words3, 2);\n\n assert(result != NULL && strcmp(result[0], \"Pqrst\") == 0 && strcmp(result[1], \"Pqr\") == 0);\n\n \n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov $0x1,%edx\npush %r12\npush %rbp\nmov %esi,%ebp\nlea 0xbdd(%rip),%rsi\npush %rbx\nmov %rdi,%rbx\nsub $0x68,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x58(%rsp)\nxor %eax,%eax\nmov %rsp,%r13\nmov %r13,%rdi\ncallq 10e0 \ntest %eax,%eax\njne 1518 \ntest %ebp,%ebp\njle 1508 \nlea -0x1(%rbp),%eax\nlea 0x40(%rsp),%rbp\nlea 0x8(%rbx,%rax,8),%r12\njmp 147d \nnopl 0x0(%rax)\nadd $0x8,%rbx\ncmp %r12,%rbx\nje 1508 \nmov (%rbx),%rsi\nxor %r8d,%r8d\nmov %rbp,%rcx\nmov $0x3,%edx\nmov %r13,%rdi\ncallq 1100 \ntest %eax,%eax\njne 1470 \nmovslq 0x48(%rsp),%rax\nmov 0x4c(%rsp),%esi\nsub %eax,%esi\nadd (%rbx),%rax\nmovslq %esi,%rsi\nmov %rax,%rdi\ncallq 10f0 \nmov 0x54(%rsp),%esi\nmov %rax,0x2b75(%rip)\nmovslq 0x50(%rsp),%rax\nsub %eax,%esi\nadd (%rbx),%rax\nmovslq %esi,%rsi\nmov %rax,%rdi\ncallq 10f0 \nmov %r13,%rdi\nmov %rax,0x2b5e(%rip)\ncallq 10b0 \nlea 0x2b4a(%rip),%rax\nmov 0x58(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 1539 \nadd $0x68,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax)\nmov %r13,%rdi\ncallq 10b0 \nxor %eax,%eax\njmp 14e6 \nnopl 0x0(%rax)\nmov 0x2b01(%rip),%rcx\nmov $0x18,%edx\nmov $0x1,%esi\nlea 0xae3(%rip),%rdi\ncallq 1110 \nxor %eax,%eax\njmp 14e6 \ncallq 10c0 <__stack_chk_fail@plt>\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r13\nmov edx, 1; cflags\npush r12\nmovsxd r12, esi\nlea rsi, pattern; \"(P\\\\w+)\\\\W(P\\\\w+)\"\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 68h\nmov rax, fs:28h\nmov [rsp+var_s58], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njnz loc_1500\ntest r12d, r12d\njle loc_14F0\nlea r13, [rbx+r12*8]\nlea r12, [rsp+pmatch]\njmp short loc_146D\nloc_1460:\nadd rbx, 8\ncmp rbx, r13\njz loc_14F0\nloc_146D:\nmov rsi, [rbx]; string\nxor r8d, r8d; eflags\nmov rcx, r12; pmatch\nmov edx, 3; nmatch\nmov rdi, rbp; preg\ncall _regexec\ntest eax, eax\njnz short loc_1460\nmovsxd rdi, [rsp+var_s48]\nmov esi, [rsp+var_s4C]\nsub esi, edi\nadd rdi, [rbx]; string\nmovsxd rsi, esi; n\ncall _strndup\nmovsxd rdi, [rsp+var_s50]\nmov esi, [rsp+var_s54]\nmov cs:result_1, rax\nsub esi, edi\nadd rdi, [rbx]; string\nmovsxd rsi, esi; n\ncall _strndup\nmov rdi, rbp; preg\nmov cs:qword_4038, rax\ncall _regfree\nlea rax, result_1\nloc_14D0:\nmov rdx, [rsp+var_s58]\nsub rdx, fs:28h\njnz short loc_1521\nadd rsp, 68h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_14F0:\nmov rdi, rbp; preg\ncall _regfree\nxor eax, eax\njmp short loc_14D0\nloc_1500:\nmov rcx, cs:__bss_start; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nxor eax, eax\njmp short loc_14D0\nloc_1521:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 *__fastcall func0(const char **a1, int a2)\n{\n const char **v2; // rbx\n regex_t vars0; // [rsp+0h] [rbp+0h] BYREF\n regmatch_t pmatch; // [rsp+40h] [rbp+40h] BYREF\n int vars48; // [rsp+48h] [rbp+48h]\n int vars4C; // [rsp+4Ch] [rbp+4Ch]\n int vars50; // [rsp+50h] [rbp+50h]\n int vars54; // [rsp+54h] [rbp+54h]\n unsigned __int64 vars58; // [rsp+58h] [rbp+58h]\n\n v2 = a1;\n vars58 = __readfsqword(0x28u);\n if ( regcomp(&vars0, \"(P\\\\w+)\\\\W(P\\\\w+)\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n return 0LL;\n }\n else if ( a2 <= 0 )\n {\nLABEL_7:\n regfree(&vars0);\n return 0LL;\n }\n else\n {\n while ( regexec(&vars0, *v2, 3uLL, &pmatch, 0) )\n {\n if ( ++v2 == &a1[a2] )\n goto LABEL_7;\n }\n result_1 = (__int64)strndup(&(*v2)[vars48], vars4C - vars48);\n qword_4038 = (__int64)strndup(&(*v2)[vars50], vars54 - vars50);\n regfree(&vars0);\n return &result_1;\n }\n}", + "ida_strip_asm": "sub_1400:\nendbr64\npush r13\nmov edx, 1; cflags\npush r12\nmovsxd r12, esi\nlea rsi, pattern; \"(P\\\\w+)\\\\W(P\\\\w+)\"\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 68h\nmov rax, fs:28h\nmov [rsp+var_s58], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njnz loc_1500\ntest r12d, r12d\njle loc_14F0\nlea r13, [rbx+r12*8]\nlea r12, [rsp+pmatch]\njmp short loc_146D\nloc_1460:\nadd rbx, 8\ncmp rbx, r13\njz loc_14F0\nloc_146D:\nmov rsi, [rbx]; string\nxor r8d, r8d; eflags\nmov rcx, r12; pmatch\nmov edx, 3; nmatch\nmov rdi, rbp; preg\ncall _regexec\ntest eax, eax\njnz short loc_1460\nmovsxd rdi, [rsp+var_s48]\nmov esi, [rsp+var_s4C]\nsub esi, edi\nadd rdi, [rbx]; string\nmovsxd rsi, esi; n\ncall _strndup\nmovsxd rdi, [rsp+var_s50]\nmov esi, [rsp+var_s54]\nmov cs:qword_4030, rax\nsub esi, edi\nadd rdi, [rbx]; string\nmovsxd rsi, esi; n\ncall _strndup\nmov rdi, rbp; preg\nmov cs:qword_4038, rax\ncall _regfree\nlea rax, qword_4030\nloc_14D0:\nmov rdx, [rsp+var_s58]\nsub rdx, fs:28h\njnz short loc_1521\nadd rsp, 68h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_14F0:\nmov rdi, rbp; preg\ncall _regfree\nxor eax, eax\njmp short loc_14D0\nloc_1500:\nmov rcx, cs:stderr; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nxor eax, eax\njmp short loc_14D0\nloc_1521:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 *__fastcall sub_1400(const char **a1, int a2)\n{\n const char **v2; // rbx\n regex_t vars0; // [rsp+0h] [rbp+0h] BYREF\n regmatch_t pmatch; // [rsp+40h] [rbp+40h] BYREF\n int vars48; // [rsp+48h] [rbp+48h]\n int vars4C; // [rsp+4Ch] [rbp+4Ch]\n int vars50; // [rsp+50h] [rbp+50h]\n int vars54; // [rsp+54h] [rbp+54h]\n unsigned __int64 vars58; // [rsp+58h] [rbp+58h]\n\n v2 = a1;\n vars58 = __readfsqword(0x28u);\n if ( regcomp(&vars0, \"(P\\\\w+)\\\\W(P\\\\w+)\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n return 0LL;\n }\n else if ( a2 <= 0 )\n {\nLABEL_7:\n regfree(&vars0);\n return 0LL;\n }\n else\n {\n while ( regexec(&vars0, *v2, 3uLL, &pmatch, 0) )\n {\n if ( ++v2 == &a1[a2] )\n goto LABEL_7;\n }\n qword_4030 = (__int64)strndup(&(*v2)[vars48], vars4C - vars48);\n qword_4038 = (__int64)strndup(&(*v2)[vars50], vars54 - vars50);\n regfree(&vars0);\n return &qword_4030;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long *sub_1400(const char **a1, int a2) {\n const char **v2;\n regex_t vars0;\n regmatch_t pmatch;\n int vars48;\n int vars4C;\n int vars50;\n int vars54;\n unsigned long long vars58;\n v2 = a1;\n vars58 = __readfsqword(40u);\n if (regcomp(&vars0, \"(P\\\\w+)\\\\W(P\\\\w+)\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n return 0LL;\n } else if (a2 <= 0) {\n LABEL_7:\n regfree(&vars0);\n return 0LL;\n } else {\n while (regexec(&vars0, *v2, 3uLL, &pmatch, 0)) {\n if (++v2 == &a1[a2]) goto LABEL_7;\n }\n qword_4030 = (long long)strndup(&(*v2)[vars48], vars4C - vars48);\n qword_4038 = (long long)strndup(&(*v2)[vars50], vars54 - vars50);\n regfree(&vars0);\n return &qword_4030;\n }\n}", + "ida_pseudo_norm": "long long *func0(const char **a1, int a2) {\n const char **v2;\n regex_t vars0;\n regmatch_t pmatch;\n int vars48;\n int vars4C;\n int vars50;\n int vars54;\n unsigned long long vars58;\n v2 = a1;\n vars58 = __readfsqword(40u);\n if (regcomp(&vars0, \"(P\\\\w+)\\\\W(P\\\\w+)\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n return 0LL;\n } else if (a2 <= 0) {\n LABEL_7:\n regfree(&vars0);\n return 0LL;\n } else {\n while (regexec(&vars0, *v2, 3uLL, &pmatch, 0)) {\n if (++v2 == &a1[a2]) goto LABEL_7;\n }\n result_1 = (long long)strndup(&(*v2)[vars48], vars4C - vars48);\n qword_4038 = (long long)strndup(&(*v2)[vars50], vars54 - vars50);\n regfree(&vars0);\n return &result_1;\n }\n}" + }, + { + "index": 306, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int a[], int n, int index, int k) {\n int dp[n][n];\n for (int i = 0; i < n; i++) {\n for (int j = 0; j < n; j++) {\n dp[i][j] = 0;\n }\n }\n for (int i = 0; i < n; i++) {\n if (a[i] > a[0]) {\n dp[0][i] = a[i] + a[0];\n } else {\n dp[0][i] = a[i];\n }\n }\n for (int i = 1; i < n; i++) {\n for (int j = 0; j < n; j++) {\n if (a[j] > a[i] && j > i) {\n if (dp[i - 1][i] + a[j] > dp[i - 1][j]) {\n dp[i][j] = dp[i - 1][i] + a[j];\n } else {\n dp[i][j] = dp[i - 1][j];\n }\n } else {\n dp[i][j] = dp[i - 1][j];\n }\n }\n }\n return dp[index][k];\n}", + "test": "int main() {\n\n int a1[] = {1, 101, 2, 3, 100, 4, 5};\n\n int a2[] = {11, 15, 19, 21, 26, 28, 31};\n\n\n\n assert(func0(a1, 7, 4, 6) == 11);\n\n assert(func0(a1, 7, 2, 5) == 7);\n\n assert(func0(a2, 7, 2, 4) == 71);\n\n\n\n printf(\"All test cases passed\\n\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0x78,%rsp\nmov %rdi,-0x78(%rbp)\nmov %esi,-0x7c(%rbp)\nmov %edx,-0x80(%rbp)\nmov %ecx,-0x84(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nmov %rsp,%rax\nmov %rax,-0x90(%rbp)\nmov -0x7c(%rbp),%esi\nmov -0x7c(%rbp),%edi\nmovslq %esi,%rax\nsub $0x1,%rax\nmov %rax,-0x50(%rbp)\nmovslq %esi,%rax\nmov %rax,-0xa0(%rbp)\nmovq $0x0,-0x98(%rbp)\nmovslq %esi,%rax\nlea 0x0(,%rax,4),%rcx\nmovslq %edi,%rax\nsub $0x1,%rax\nmov %rax,-0x48(%rbp)\nmovslq %esi,%rax\nmov %rax,%r14\nmov $0x0,%r15d\nmovslq %edi,%rax\nmov %rax,%r12\nmov $0x0,%r13d\nmov %r15,%rdx\nimul %r12,%rdx\nmov %r13,%rax\nimul %r14,%rax\nlea (%rdx,%rax,1),%rbx\nmov %r14,%rax\nmul %r12\nadd %rdx,%rbx\nmov %rbx,%rdx\nmovslq %esi,%rax\nmov %rax,%r10\nmov $0x0,%r11d\nmovslq %edi,%rax\nmov %rax,%r8\nmov $0x0,%r9d\nmov %r11,%rdx\nimul %r8,%rdx\nmov %r9,%rax\nimul %r10,%rax\nlea (%rdx,%rax,1),%rbx\nmov %r10,%rax\nmul %r8\nlea (%rbx,%rdx,1),%r8\nmov %r8,%rdx\nmovslq %esi,%rdx\nmovslq %edi,%rax\nimul %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%ebx\nmov $0x0,%edx\ndiv %rbx\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rbx\nsub %rdx,%rbx\nmov %rbx,%rdx\ncmp %rdx,%rsp\nje 12c9 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 12b2 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 12f3 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x40(%rbp)\nmovl $0x0,-0x54(%rbp)\njmp 134d \nmovl $0x0,-0x58(%rbp)\njmp 1341 \nmov %rcx,%rdi\nshr $0x2,%rdi\nmov -0x40(%rbp),%rax\nmov -0x58(%rbp),%edx\nmovslq %edx,%rsi\nmov -0x54(%rbp),%edx\nmovslq %edx,%rdx\nimul %rdi,%rdx\nadd %rsi,%rdx\nmovl $0x0,(%rax,%rdx,4)\naddl $0x1,-0x58(%rbp)\nmov -0x58(%rbp),%eax\ncmp -0x7c(%rbp),%eax\njl 1318 \naddl $0x1,-0x54(%rbp)\nmov -0x54(%rbp),%eax\ncmp -0x7c(%rbp),%eax\njl 130f \nmovl $0x0,-0x5c(%rbp)\njmp 13d3 \nmov -0x5c(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x78(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x78(%rbp),%rax\nmov (%rax),%eax\ncmp %eax,%edx\njle 13ac \nmov -0x5c(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x78(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x78(%rbp),%rax\nmov (%rax),%eax\nlea (%rdx,%rax,1),%esi\nmov -0x40(%rbp),%rax\nmov -0x5c(%rbp),%edx\nmovslq %edx,%rdx\nmov %esi,(%rax,%rdx,4)\njmp 13cf \nmov -0x5c(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x78(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%esi\nmov -0x40(%rbp),%rax\nmov -0x5c(%rbp),%edx\nmovslq %edx,%rdx\nmov %esi,(%rax,%rdx,4)\naddl $0x1,-0x5c(%rbp)\nmov -0x5c(%rbp),%eax\ncmp -0x7c(%rbp),%eax\njl 135e \nmovl $0x1,-0x60(%rbp)\njmpq 15a0 \nmovl $0x0,-0x64(%rbp)\njmpq 1590 \nmov -0x64(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x78(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x60(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rsi\nmov -0x78(%rbp),%rax\nadd %rsi,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njle 1546 \nmov -0x64(%rbp),%eax\ncmp -0x60(%rbp),%eax\njle 1546 \nmov %rcx,%rdi\nshr $0x2,%rdi\nmov -0x60(%rbp),%eax\nlea -0x1(%rax),%r8d\nmov -0x40(%rbp),%rax\nmov -0x60(%rbp),%edx\nmovslq %edx,%rsi\nmovslq %r8d,%rdx\nimul %rdi,%rdx\nadd %rsi,%rdx\nmov (%rax,%rdx,4),%edx\nmov -0x64(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rsi\nmov -0x78(%rbp),%rax\nadd %rsi,%rax\nmov (%rax),%eax\nlea (%rdx,%rax,1),%edi\nmov %rcx,%r8\nshr $0x2,%r8\nmov -0x60(%rbp),%eax\nlea -0x1(%rax),%r9d\nmov -0x40(%rbp),%rax\nmov -0x64(%rbp),%edx\nmovslq %edx,%rsi\nmovslq %r9d,%rdx\nimul %r8,%rdx\nadd %rsi,%rdx\nmov (%rax,%rdx,4),%eax\ncmp %eax,%edi\njle 14fe \nmov %rcx,%rdi\nshr $0x2,%rdi\nmov -0x60(%rbp),%eax\nlea -0x1(%rax),%r8d\nmov -0x40(%rbp),%rax\nmov -0x60(%rbp),%edx\nmovslq %edx,%rsi\nmovslq %r8d,%rdx\nimul %rdi,%rdx\nadd %rsi,%rdx\nmov (%rax,%rdx,4),%edx\nmov -0x64(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rsi\nmov -0x78(%rbp),%rax\nadd %rsi,%rax\nmov (%rax),%eax\nmov %rcx,%r8\nshr $0x2,%r8\nlea (%rdx,%rax,1),%esi\nmov -0x40(%rbp),%rax\nmov -0x64(%rbp),%edx\nmovslq %edx,%rdi\nmov -0x60(%rbp),%edx\nmovslq %edx,%rdx\nimul %r8,%rdx\nadd %rdi,%rdx\nmov %esi,(%rax,%rdx,4)\njmpq 158c \nmov %rcx,%rdi\nshr $0x2,%rdi\nmov -0x60(%rbp),%eax\nlea -0x1(%rax),%r9d\nmov %rcx,%r8\nshr $0x2,%r8\nmov -0x40(%rbp),%rax\nmov -0x64(%rbp),%edx\nmovslq %edx,%rsi\nmovslq %r9d,%rdx\nimul %rdi,%rdx\nadd %rsi,%rdx\nmov (%rax,%rdx,4),%edx\nmov -0x40(%rbp),%rax\nmov -0x64(%rbp),%esi\nmovslq %esi,%rdi\nmov -0x60(%rbp),%esi\nmovslq %esi,%rsi\nimul %r8,%rsi\nadd %rdi,%rsi\nmov %edx,(%rax,%rsi,4)\njmp 158c \nmov %rcx,%rdi\nshr $0x2,%rdi\nmov -0x60(%rbp),%eax\nlea -0x1(%rax),%r9d\nmov %rcx,%r8\nshr $0x2,%r8\nmov -0x40(%rbp),%rax\nmov -0x64(%rbp),%edx\nmovslq %edx,%rsi\nmovslq %r9d,%rdx\nimul %rdi,%rdx\nadd %rsi,%rdx\nmov (%rax,%rdx,4),%edx\nmov -0x40(%rbp),%rax\nmov -0x64(%rbp),%esi\nmovslq %esi,%rdi\nmov -0x60(%rbp),%esi\nmovslq %esi,%rsi\nimul %r8,%rsi\nadd %rdi,%rsi\nmov %edx,(%rax,%rsi,4)\naddl $0x1,-0x64(%rbp)\nmov -0x64(%rbp),%eax\ncmp -0x7c(%rbp),%eax\njl 13f3 \naddl $0x1,-0x60(%rbp)\nmov -0x60(%rbp),%eax\ncmp -0x7c(%rbp),%eax\njl 13e7 \nshr $0x2,%rcx\nmov %rcx,%rsi\nmov -0x40(%rbp),%rax\nmov -0x84(%rbp),%edx\nmovslq %edx,%rcx\nmov -0x80(%rbp),%edx\nmovslq %edx,%rdx\nimul %rsi,%rdx\nadd %rcx,%rdx\nmov (%rax,%rdx,4),%eax\nmov -0x90(%rbp),%rsp\nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\nje 15eb \ncallq 1080 <__stack_chk_fail@plt>\nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 68h\nmov [rbp+var_58], rdi\nmov [rbp+var_5C], esi\nmov [rbp+var_60], edx\nmov [rbp+var_64], ecx\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov rax, rsp\nmov rbx, rax\nmov r8d, [rbp+var_5C]\nmov r9d, [rbp+var_5C]\nmovsxd rax, r8d\nsub rax, 1\nmov [rbp+var_30], rax\nmovsxd rax, r8d\nlea rcx, ds:0[rax*4]\nmovsxd rax, r9d\nsub rax, 1\nmov [rbp+var_28], rax\nmovsxd rax, r8d\nmov rsi, rax\nmov edi, 0\nmovsxd rax, r9d\nmov rax, rax\nmov edx, 0\nmov r11, rdi\nimul r11, rax\nmov r10, rdx\nimul r10, rsi\nadd r10, r11\nmul rsi\nlea rsi, [r10+rdx]\nmov rdx, rsi\nmovsxd rax, r8d\nmov rsi, rax\nmov edi, 0\nmovsxd rax, r9d\nmov rax, rax\nmov edx, 0\nmov r11, rdi\nimul r11, rax\nmov r10, rdx\nimul r10, rsi\nadd r10, r11\nmul rsi\nlea rsi, [r10+rdx]\nmov rdx, rsi\nmovsxd rdx, r8d\nmovsxd rax, r9d\nimul rax, rdx\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rsi, rax\nand rsi, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rsi\nloc_1282:\ncmp rsp, rdx\njz short loc_1299\nsub rsp, 1000h\nor [rsp+1070h+var_78], 0\njmp short loc_1282\nloc_1299:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_12C3\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_12C3:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_20], rax\nmov [rbp+var_44], 0\njmp short loc_131D\nloc_12DF:\nmov [rbp+var_40], 0\njmp short loc_1311\nloc_12E8:\nmov rdi, rcx\nshr rdi, 2\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_40]\nmovsxd rsi, edx\nmov edx, [rbp+var_44]\nmovsxd rdx, edx\nimul rdx, rdi\nadd rdx, rsi\nmov dword ptr [rax+rdx*4], 0\nadd [rbp+var_40], 1\nloc_1311:\nmov eax, [rbp+var_40]\ncmp eax, [rbp+var_5C]\njl short loc_12E8\nadd [rbp+var_44], 1\nloc_131D:\nmov eax, [rbp+var_44]\ncmp eax, [rbp+var_5C]\njl short loc_12DF\nmov [rbp+var_3C], 0\njmp short loc_13A3\nloc_132E:\nmov eax, [rbp+var_3C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_58]\nmov eax, [rax]\ncmp edx, eax\njle short loc_137C\nmov eax, [rbp+var_3C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_58]\nmov eax, [rax]\nlea esi, [rdx+rax]\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_3C]\nmovsxd rdx, edx\nmov [rax+rdx*4], esi\njmp short loc_139F\nloc_137C:\nmov eax, [rbp+var_3C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov esi, [rax]\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_3C]\nmovsxd rdx, edx\nmov [rax+rdx*4], esi\nloc_139F:\nadd [rbp+var_3C], 1\nloc_13A3:\nmov eax, [rbp+var_3C]\ncmp eax, [rbp+var_5C]\njl short loc_132E\nmov [rbp+var_38], 1\njmp loc_1572\nloc_13B7:\nmov [rbp+var_34], 0\njmp loc_1562\nloc_13C3:\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_38]\ncdqe\nlea rsi, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rsi\nmov eax, [rax]\ncmp edx, eax\njle loc_1518\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_38]\njle loc_1518\nmov rdi, rcx\nshr rdi, 2\nmov eax, [rbp+var_38]\nlea r8d, [rax-1]\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_38]\nmovsxd rsi, edx\nmovsxd rdx, r8d\nimul rdx, rdi\nadd rdx, rsi\nmov edx, [rax+rdx*4]\nmov eax, [rbp+var_34]\ncdqe\nlea rsi, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rsi\nmov eax, [rax]\nlea r8d, [rdx+rax]\nmov rdi, rcx\nshr rdi, 2\nmov eax, [rbp+var_38]\nlea r9d, [rax-1]\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_34]\nmovsxd rsi, edx\nmovsxd rdx, r9d\nimul rdx, rdi\nadd rdx, rsi\nmov eax, [rax+rdx*4]\ncmp r8d, eax\njle short loc_14D0\nmov rdi, rcx\nshr rdi, 2\nmov eax, [rbp+var_38]\nlea r8d, [rax-1]\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_38]\nmovsxd rsi, edx\nmovsxd rdx, r8d\nimul rdx, rdi\nadd rdx, rsi\nmov edx, [rax+rdx*4]\nmov eax, [rbp+var_34]\ncdqe\nlea rsi, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rsi\nmov eax, [rax]\nmov r8, rcx\nshr r8, 2\nlea esi, [rdx+rax]\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_34]\nmovsxd rdi, edx\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nimul rdx, r8\nadd rdx, rdi\nmov [rax+rdx*4], esi\njmp loc_155E\nloc_14D0:\nmov rdi, rcx\nshr rdi, 2\nmov eax, [rbp+var_38]\nlea r9d, [rax-1]\nmov r8, rcx\nshr r8, 2\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_34]\nmovsxd rsi, edx\nmovsxd rdx, r9d\nimul rdx, rdi\nadd rdx, rsi\nmov edx, [rax+rdx*4]\nmov rax, [rbp+var_20]\nmov esi, [rbp+var_34]\nmovsxd rdi, esi\nmov esi, [rbp+var_38]\nmovsxd rsi, esi\nimul rsi, r8\nadd rsi, rdi\nmov [rax+rsi*4], edx\njmp short loc_155E\nloc_1518:\nmov rdi, rcx\nshr rdi, 2\nmov eax, [rbp+var_38]\nlea r9d, [rax-1]\nmov r8, rcx\nshr r8, 2\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_34]\nmovsxd rsi, edx\nmovsxd rdx, r9d\nimul rdx, rdi\nadd rdx, rsi\nmov edx, [rax+rdx*4]\nmov rax, [rbp+var_20]\nmov esi, [rbp+var_34]\nmovsxd rdi, esi\nmov esi, [rbp+var_38]\nmovsxd rsi, esi\nimul rsi, r8\nadd rsi, rdi\nmov [rax+rsi*4], edx\nloc_155E:\nadd [rbp+var_34], 1\nloc_1562:\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_5C]\njl loc_13C3\nadd [rbp+var_38], 1\nloc_1572:\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_5C]\njl loc_13B7\nshr rcx, 2\nmov rsi, rcx\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_64]\nmovsxd rcx, edx\nmov edx, [rbp+var_60]\nmovsxd rdx, edx\nimul rdx, rsi\nadd rdx, rcx\nmov eax, [rax+rdx*4]\nmov rsp, rbx\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njz short loc_15B6\ncall ___stack_chk_fail\nloc_15B6:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2, int a3, int a4)\n{\n unsigned __int64 v4; // rcx\n unsigned __int64 v5; // rax\n void *v6; // rsp\n int v7; // esi\n _BYTE v9[12]; // [rsp+8h] [rbp-70h] BYREF\n int v10; // [rsp+14h] [rbp-64h]\n int v11; // [rsp+18h] [rbp-60h]\n int v12; // [rsp+1Ch] [rbp-5Ch]\n _DWORD *v13; // [rsp+20h] [rbp-58h]\n int i; // [rsp+34h] [rbp-44h]\n int j; // [rsp+38h] [rbp-40h]\n int k; // [rsp+3Ch] [rbp-3Ch]\n int m; // [rsp+40h] [rbp-38h]\n int n; // [rsp+44h] [rbp-34h]\n __int64 v19; // [rsp+48h] [rbp-30h]\n __int64 v20; // [rsp+50h] [rbp-28h]\n _BYTE *v21; // [rsp+58h] [rbp-20h]\n unsigned __int64 v22; // [rsp+60h] [rbp-18h]\n\n v13 = a1;\n v12 = a2;\n v11 = a3;\n v10 = a4;\n v22 = __readfsqword(0x28u);\n v19 = a2 - 1LL;\n v4 = 4LL * a2;\n v20 = v19;\n v5 = 16 * ((4 * a2 * (__int64)a2 + 15) / 0x10uLL);\n while ( v9 != &v9[-(v5 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v6 = alloca(v5 & 0xFFF);\n if ( (v5 & 0xFFF) != 0 )\n *(_QWORD *)&v9[(v5 & 0xFFF) - 8] = *(_QWORD *)&v9[(v5 & 0xFFF) - 8];\n v21 = v9;\n for ( i = 0; i < v12; ++i )\n {\n for ( j = 0; j < v12; ++j )\n *(_DWORD *)&v21[4 * j + 4 * (v4 >> 2) * i] = 0;\n }\n for ( k = 0; k < v12; ++k )\n {\n if ( v13[k] <= *v13 )\n v7 = v13[k];\n else\n v7 = v13[k] + *v13;\n *(_DWORD *)&v21[4 * k] = v7;\n }\n for ( m = 1; m < v12; ++m )\n {\n for ( n = 0; n < v12; ++n )\n {\n if ( v13[n] <= v13[m] || n <= m )\n {\n *(_DWORD *)&v21[4 * n + 4 * (v4 >> 2) * m] = *(_DWORD *)&v21[4 * n + 4 * (v4 >> 2) * (m - 1)];\n }\n else if ( *(_DWORD *)&v21[4 * m + 4 * (v4 >> 2) * (m - 1)] + v13[n] <= *(_DWORD *)&v21[4 * n\n + 4 * (v4 >> 2) * (m - 1)] )\n {\n *(_DWORD *)&v21[4 * n + 4 * (v4 >> 2) * m] = *(_DWORD *)&v21[4 * n + 4 * (v4 >> 2) * (m - 1)];\n }\n else\n {\n *(_DWORD *)&v21[4 * n + 4 * (v4 >> 2) * m] = *(_DWORD *)&v21[4 * m + 4 * (v4 >> 2) * (m - 1)] + v13[n];\n }\n }\n }\n return *(unsigned int *)&v21[4 * v10 + 4 * (v4 >> 2) * v11];\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 68h\nmov [rbp+var_58], rdi\nmov [rbp+var_5C], esi\nmov [rbp+var_60], edx\nmov [rbp+var_64], ecx\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov rax, rsp\nmov rbx, rax\nmov r8d, [rbp+var_5C]\nmov r9d, [rbp+var_5C]\nmovsxd rax, r8d\nsub rax, 1\nmov [rbp+var_30], rax\nmovsxd rax, r8d\nlea rcx, ds:0[rax*4]\nmovsxd rax, r9d\nsub rax, 1\nmov [rbp+var_28], rax\nmovsxd rax, r8d\nmov rsi, rax\nmov edi, 0\nmovsxd rax, r9d\nmov rax, rax\nmov edx, 0\nmov r11, rdi\nimul r11, rax\nmov r10, rdx\nimul r10, rsi\nadd r10, r11\nmul rsi\nlea rsi, [r10+rdx]\nmov rdx, rsi\nmovsxd rax, r8d\nmov rsi, rax\nmov edi, 0\nmovsxd rax, r9d\nmov rax, rax\nmov edx, 0\nmov r11, rdi\nimul r11, rax\nmov r10, rdx\nimul r10, rsi\nadd r10, r11\nmul rsi\nlea rsi, [r10+rdx]\nmov rdx, rsi\nmovsxd rdx, r8d\nmovsxd rax, r9d\nimul rax, rdx\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rsi, rax\nand rsi, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rsi\nloc_1282:\ncmp rsp, rdx\njz short loc_1299\nsub rsp, 1000h\nor [rsp+1070h+var_78], 0\njmp short loc_1282\nloc_1299:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_12C3\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_12C3:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_20], rax\nmov [rbp+var_44], 0\njmp short loc_131D\nloc_12DF:\nmov [rbp+var_40], 0\njmp short loc_1311\nloc_12E8:\nmov rdi, rcx\nshr rdi, 2\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_40]\nmovsxd rsi, edx\nmov edx, [rbp+var_44]\nmovsxd rdx, edx\nimul rdx, rdi\nadd rdx, rsi\nmov dword ptr [rax+rdx*4], 0\nadd [rbp+var_40], 1\nloc_1311:\nmov eax, [rbp+var_40]\ncmp eax, [rbp+var_5C]\njl short loc_12E8\nadd [rbp+var_44], 1\nloc_131D:\nmov eax, [rbp+var_44]\ncmp eax, [rbp+var_5C]\njl short loc_12DF\nmov [rbp+var_3C], 0\njmp short loc_13A3\nloc_132E:\nmov eax, [rbp+var_3C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_58]\nmov eax, [rax]\ncmp edx, eax\njle short loc_137C\nmov eax, [rbp+var_3C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_58]\nmov eax, [rax]\nlea esi, [rdx+rax]\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_3C]\nmovsxd rdx, edx\nmov [rax+rdx*4], esi\njmp short loc_139F\nloc_137C:\nmov eax, [rbp+var_3C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov esi, [rax]\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_3C]\nmovsxd rdx, edx\nmov [rax+rdx*4], esi\nloc_139F:\nadd [rbp+var_3C], 1\nloc_13A3:\nmov eax, [rbp+var_3C]\ncmp eax, [rbp+var_5C]\njl short loc_132E\nmov [rbp+var_38], 1\njmp loc_1572\nloc_13B7:\nmov [rbp+var_34], 0\njmp loc_1562\nloc_13C3:\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_38]\ncdqe\nlea rsi, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rsi\nmov eax, [rax]\ncmp edx, eax\njle loc_1518\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_38]\njle loc_1518\nmov rdi, rcx\nshr rdi, 2\nmov eax, [rbp+var_38]\nlea r8d, [rax-1]\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_38]\nmovsxd rsi, edx\nmovsxd rdx, r8d\nimul rdx, rdi\nadd rdx, rsi\nmov edx, [rax+rdx*4]\nmov eax, [rbp+var_34]\ncdqe\nlea rsi, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rsi\nmov eax, [rax]\nlea r8d, [rdx+rax]\nmov rdi, rcx\nshr rdi, 2\nmov eax, [rbp+var_38]\nlea r9d, [rax-1]\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_34]\nmovsxd rsi, edx\nmovsxd rdx, r9d\nimul rdx, rdi\nadd rdx, rsi\nmov eax, [rax+rdx*4]\ncmp r8d, eax\njle short loc_14D0\nmov rdi, rcx\nshr rdi, 2\nmov eax, [rbp+var_38]\nlea r8d, [rax-1]\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_38]\nmovsxd rsi, edx\nmovsxd rdx, r8d\nimul rdx, rdi\nadd rdx, rsi\nmov edx, [rax+rdx*4]\nmov eax, [rbp+var_34]\ncdqe\nlea rsi, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rsi\nmov eax, [rax]\nmov r8, rcx\nshr r8, 2\nlea esi, [rdx+rax]\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_34]\nmovsxd rdi, edx\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nimul rdx, r8\nadd rdx, rdi\nmov [rax+rdx*4], esi\njmp loc_155E\nloc_14D0:\nmov rdi, rcx\nshr rdi, 2\nmov eax, [rbp+var_38]\nlea r9d, [rax-1]\nmov r8, rcx\nshr r8, 2\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_34]\nmovsxd rsi, edx\nmovsxd rdx, r9d\nimul rdx, rdi\nadd rdx, rsi\nmov edx, [rax+rdx*4]\nmov rax, [rbp+var_20]\nmov esi, [rbp+var_34]\nmovsxd rdi, esi\nmov esi, [rbp+var_38]\nmovsxd rsi, esi\nimul rsi, r8\nadd rsi, rdi\nmov [rax+rsi*4], edx\njmp short loc_155E\nloc_1518:\nmov rdi, rcx\nshr rdi, 2\nmov eax, [rbp+var_38]\nlea r9d, [rax-1]\nmov r8, rcx\nshr r8, 2\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_34]\nmovsxd rsi, edx\nmovsxd rdx, r9d\nimul rdx, rdi\nadd rdx, rsi\nmov edx, [rax+rdx*4]\nmov rax, [rbp+var_20]\nmov esi, [rbp+var_34]\nmovsxd rdi, esi\nmov esi, [rbp+var_38]\nmovsxd rsi, esi\nimul rsi, r8\nadd rsi, rdi\nmov [rax+rsi*4], edx\nloc_155E:\nadd [rbp+var_34], 1\nloc_1562:\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_5C]\njl loc_13C3\nadd [rbp+var_38], 1\nloc_1572:\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_5C]\njl loc_13B7\nshr rcx, 2\nmov rsi, rcx\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_64]\nmovsxd rcx, edx\nmov edx, [rbp+var_60]\nmovsxd rdx, edx\nimul rdx, rsi\nadd rdx, rcx\nmov eax, [rax+rdx*4]\nmov rsp, rbx\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njz short loc_15B6\ncall ___stack_chk_fail\nloc_15B6:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(_DWORD *a1, int a2, int a3, int a4)\n{\n unsigned __int64 v4; // rcx\n unsigned __int64 v5; // rax\n void *v6; // rsp\n int v7; // esi\n _BYTE v9[12]; // [rsp+8h] [rbp-70h] BYREF\n int v10; // [rsp+14h] [rbp-64h]\n int v11; // [rsp+18h] [rbp-60h]\n int v12; // [rsp+1Ch] [rbp-5Ch]\n _DWORD *v13; // [rsp+20h] [rbp-58h]\n int i; // [rsp+34h] [rbp-44h]\n int j; // [rsp+38h] [rbp-40h]\n int k; // [rsp+3Ch] [rbp-3Ch]\n int m; // [rsp+40h] [rbp-38h]\n int n; // [rsp+44h] [rbp-34h]\n __int64 v19; // [rsp+48h] [rbp-30h]\n __int64 v20; // [rsp+50h] [rbp-28h]\n _BYTE *v21; // [rsp+58h] [rbp-20h]\n unsigned __int64 v22; // [rsp+60h] [rbp-18h]\n\n v13 = a1;\n v12 = a2;\n v11 = a3;\n v10 = a4;\n v22 = __readfsqword(0x28u);\n v19 = a2 - 1LL;\n v4 = 4LL * a2;\n v20 = v19;\n v5 = 16 * ((4 * a2 * (__int64)a2 + 15) / 0x10uLL);\n while ( v9 != &v9[-(v5 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v6 = alloca(v5 & 0xFFF);\n if ( (v5 & 0xFFF) != 0 )\n *(_QWORD *)&v9[(v5 & 0xFFF) - 8] = *(_QWORD *)&v9[(v5 & 0xFFF) - 8];\n v21 = v9;\n for ( i = 0; i < v12; ++i )\n {\n for ( j = 0; j < v12; ++j )\n *(_DWORD *)&v21[4 * j + 4 * (v4 >> 2) * i] = 0;\n }\n for ( k = 0; k < v12; ++k )\n {\n if ( v13[k] <= *v13 )\n v7 = v13[k];\n else\n v7 = v13[k] + *v13;\n *(_DWORD *)&v21[4 * k] = v7;\n }\n for ( m = 1; m < v12; ++m )\n {\n for ( n = 0; n < v12; ++n )\n {\n if ( v13[n] <= v13[m] || n <= m )\n {\n *(_DWORD *)&v21[4 * n + 4 * (v4 >> 2) * m] = *(_DWORD *)&v21[4 * n + 4 * (v4 >> 2) * (m - 1)];\n }\n else if ( *(_DWORD *)&v21[4 * m + 4 * (v4 >> 2) * (m - 1)] + v13[n] <= *(_DWORD *)&v21[4 * n\n + 4 * (v4 >> 2) * (m - 1)] )\n {\n *(_DWORD *)&v21[4 * n + 4 * (v4 >> 2) * m] = *(_DWORD *)&v21[4 * n + 4 * (v4 >> 2) * (m - 1)];\n }\n else\n {\n *(_DWORD *)&v21[4 * n + 4 * (v4 >> 2) * m] = *(_DWORD *)&v21[4 * m + 4 * (v4 >> 2) * (m - 1)] + v13[n];\n }\n }\n }\n return *(unsigned int *)&v21[4 * v10 + 4 * (v4 >> 2) * v11];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(uint32_t *a1, int a2, int a3, int a4) {\n unsigned long long v4;\n unsigned long long v5;\n void *v6;\n int v7;\n uint8_t v9[12];\n int v10;\n int v11;\n int v12;\n uint32_t *v13;\n int i;\n int j;\n int k;\n int m;\n int n;\n long long v19;\n long long v20;\n uint8_t *v21;\n unsigned long long v22;\n v13 = a1;\n v12 = a2;\n v11 = a3;\n v10 = a4;\n v22 = __readfsqword(40u);\n v19 = a2 - 1LL;\n v4 = 4LL * a2;\n v20 = v19;\n v5 = 16 * ((4 * a2 * (long long)a2 + 15) / 16uLL);\n while (v9 != &v9[-(v5 & 18446744073709547520LL)])\n ;\n v6 = alloca(v5 & 4095);\n if ((v5 & 4095) != 0)\n *(uint64_t *)&v9[(v5 & 4095) - 8] = *(uint64_t *)&v9[(v5 & 4095) - 8];\n v21 = v9;\n for (i = 0; i < v12; ++i) {\n for (j = 0; j < v12; ++j) *(uint32_t *)&v21[4 * j + 4 * (v4 >> 2) * i] = 0;\n }\n for (k = 0; k < v12; ++k) {\n if (v13[k] <= *v13)\n v7 = v13[k];\n else\n v7 = v13[k] + *v13;\n *(uint32_t *)&v21[4 * k] = v7;\n }\n for (m = 1; m < v12; ++m) {\n for (n = 0; n < v12; ++n) {\n if (v13[n] <= v13[m] || n <= m) {\n *(uint32_t *)&v21[4 * n + 4 * (v4 >> 2) * m] =\n *(uint32_t *)&v21[4 * n + 4 * (v4 >> 2) * (m - 1)];\n } else if (*(uint32_t *)&v21[4 * m + 4 * (v4 >> 2) * (m - 1)] + v13[n] <=\n *(uint32_t *)&v21[4 * n + 4 * (v4 >> 2) * (m - 1)]) {\n *(uint32_t *)&v21[4 * n + 4 * (v4 >> 2) * m] =\n *(uint32_t *)&v21[4 * n + 4 * (v4 >> 2) * (m - 1)];\n } else {\n *(uint32_t *)&v21[4 * n + 4 * (v4 >> 2) * m] =\n *(uint32_t *)&v21[4 * m + 4 * (v4 >> 2) * (m - 1)] + v13[n];\n }\n }\n }\n return *(unsigned int *)&v21[4 * v10 + 4 * (v4 >> 2) * v11];\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2, int a3, int a4) {\n unsigned long long v4;\n unsigned long long v5;\n void *v6;\n int v7;\n uint8_t v9[12];\n int v10;\n int v11;\n int v12;\n uint32_t *v13;\n int i;\n int j;\n int k;\n int m;\n int n;\n long long v19;\n long long v20;\n uint8_t *v21;\n unsigned long long v22;\n v13 = a1;\n v12 = a2;\n v11 = a3;\n v10 = a4;\n v22 = __readfsqword(40u);\n v19 = a2 - 1LL;\n v4 = 4LL * a2;\n v20 = v19;\n v5 = 16 * ((4 * a2 * (long long)a2 + 15) / 16uLL);\n while (v9 != &v9[-(v5 & 18446744073709547520LL)])\n ;\n v6 = alloca(v5 & 4095);\n if ((v5 & 4095) != 0)\n *(uint64_t *)&v9[(v5 & 4095) - 8] = *(uint64_t *)&v9[(v5 & 4095) - 8];\n v21 = v9;\n for (i = 0; i < v12; ++i) {\n for (j = 0; j < v12; ++j) *(uint32_t *)&v21[4 * j + 4 * (v4 >> 2) * i] = 0;\n }\n for (k = 0; k < v12; ++k) {\n if (v13[k] <= *v13)\n v7 = v13[k];\n else\n v7 = v13[k] + *v13;\n *(uint32_t *)&v21[4 * k] = v7;\n }\n for (m = 1; m < v12; ++m) {\n for (n = 0; n < v12; ++n) {\n if (v13[n] <= v13[m] || n <= m) {\n *(uint32_t *)&v21[4 * n + 4 * (v4 >> 2) * m] =\n *(uint32_t *)&v21[4 * n + 4 * (v4 >> 2) * (m - 1)];\n } else if (*(uint32_t *)&v21[4 * m + 4 * (v4 >> 2) * (m - 1)] + v13[n] <=\n *(uint32_t *)&v21[4 * n + 4 * (v4 >> 2) * (m - 1)]) {\n *(uint32_t *)&v21[4 * n + 4 * (v4 >> 2) * m] =\n *(uint32_t *)&v21[4 * n + 4 * (v4 >> 2) * (m - 1)];\n } else {\n *(uint32_t *)&v21[4 * n + 4 * (v4 >> 2) * m] =\n *(uint32_t *)&v21[4 * m + 4 * (v4 >> 2) * (m - 1)] + v13[n];\n }\n }\n }\n return *(unsigned int *)&v21[4 * v10 + 4 * (v4 >> 2) * v11];\n}" + }, + { + "index": 306, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int a[], int n, int index, int k) {\n int dp[n][n];\n for (int i = 0; i < n; i++) {\n for (int j = 0; j < n; j++) {\n dp[i][j] = 0;\n }\n }\n for (int i = 0; i < n; i++) {\n if (a[i] > a[0]) {\n dp[0][i] = a[i] + a[0];\n } else {\n dp[0][i] = a[i];\n }\n }\n for (int i = 1; i < n; i++) {\n for (int j = 0; j < n; j++) {\n if (a[j] > a[i] && j > i) {\n if (dp[i - 1][i] + a[j] > dp[i - 1][j]) {\n dp[i][j] = dp[i - 1][i] + a[j];\n } else {\n dp[i][j] = dp[i - 1][j];\n }\n } else {\n dp[i][j] = dp[i - 1][j];\n }\n }\n }\n return dp[index][k];\n}", + "test": "int main() {\n\n int a1[] = {1, 101, 2, 3, 100, 4, 5};\n\n int a2[] = {11, 15, 19, 21, 26, 28, 31};\n\n\n\n assert(func0(a1, 7, 4, 6) == 11);\n\n assert(func0(a1, 7, 2, 5) == 7);\n\n assert(func0(a2, 7, 2, 4) == 71);\n\n\n\n printf(\"All test cases passed\\n\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0x48,%rsp\nmov %edx,-0x64(%rbp)\nmov %ecx,-0x68(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nmovslq %esi,%rax\nlea 0x0(,%rax,4),%rbx\nimul %rax,%rax\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffffff0,%rdx\nand $0xfffffffffffff000,%rax\nmov %rsp,%rcx\nsub %rax,%rcx\nmov %rcx,%rax\ncmp %rax,%rsp\nje 11f7 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11e0 \nmov %rdx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 120d \norq $0x0,-0x8(%rsp,%rax,1)\nmov %rsp,%rax\nmov %rax,-0x60(%rbp)\nmov %rax,%r15\ntest %esi,%esi\njle 127d \nlea -0x1(%rsi),%r8d\nlea 0x4(%rax,%r8,4),%rdx\nmov $0x0,%ecx\nnot %r8\nshl $0x2,%r8\njmp 123e \nlea 0x1(%rcx),%eax\nadd %rbx,%rdx\ncmp %eax,%esi\nje 1253 \nmov %eax,%ecx\nlea (%r8,%rdx,1),%rax\nmovl $0x0,(%rax)\nadd $0x4,%rax\ncmp %rdx,%rax\njne 1242 \njmp 1232 \nmov (%rdi),%r9d\nmov %ecx,%r8d\nmov $0x0,%eax\njmp 1263 \nmov %rdx,%rax\nmov (%rdi,%rax,4),%ecx\nlea (%rcx,%r9,1),%edx\ncmp %r9d,%ecx\ncmovle %ecx,%edx\nmov %edx,(%r15,%rax,4)\nlea 0x1(%rax),%rdx\ncmp %r8,%rax\njne 1260 \ncmp $0x1,%esi\njle 1332 \nmov %rbx,%rax\nshr $0x2,%rax\nmov %rax,-0x50(%rbp)\nmov -0x60(%rbp),%r14\nlea (%r14,%rbx,1),%r13\nmov %r14,%r9\nlea -0x2(%rsi),%eax\nadd $0x2,%rax\nmov %rax,-0x58(%rbp)\nmov %r13,%r8\nmov $0x1,%ecx\nmov $0x0,%eax\nlea -0x1(%rsi),%esi\nmov %r15,-0x48(%rbp)\nmov %eax,%r15d\njmp 1319 \nmov %r12d,0x0(%r13,%rax,4)\njmp 12cf \nmov (%r9,%rax,4),%edx\nmov %edx,(%r8,%rax,4)\nlea 0x1(%rax),%rdx\ncmp %rsi,%rax\nje 12ff \nmov %rdx,%rax\nmov (%rdi,%rax,4),%edx\ncmp %ecx,%eax\njle 12c7 \ncmp %r11d,%edx\njle 12c7 \nmov -0x48(%rbp),%r12\nadd (%r12,%r10,4),%edx\nmov (%r14,%rax,4),%r12d\ncmp %r12d,%edx\njle 12c0 \nmov %edx,0x0(%r13,%rax,4)\njmp 12cf \nadd $0x1,%r15d\nadd $0x1,%rcx\nadd %rbx,%r13\nadd %rbx,%r9\nadd %rbx,%r8\nadd %rbx,%r14\ncmp -0x58(%rbp),%rcx\nje 1332 \nmov (%rdi,%rcx,4),%r11d\nmov $0x0,%eax\nmovslq %ecx,%r10\nmovslq %r15d,%rdx\nimul -0x50(%rbp),%rdx\nadd %rdx,%r10\njmp 12db \nmovslq -0x68(%rbp),%rdx\nmovslq -0x64(%rbp),%rax\nshr $0x2,%rbx\nimul %rax,%rbx\nlea (%rdx,%rbx,1),%rax\nmov -0x60(%rbp),%rbx\nmov (%rbx,%rax,4),%eax\nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\njne 136b \nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\ncallq 1080 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 38h\nmov r8d, esi\nmov eax, ecx\nmov rcx, fs:28h\nmov [rbp+var_38], rcx\nxor ecx, ecx\nmovsxd r13, esi\nlea r11, ds:0[r13*4]\nmov rcx, r13\nimul rcx, r13\nlea rcx, ds:0Fh[rcx*4]\nmov r9, rcx\nand r9, 0FFFFFFFFFFFFFFF0h\nand rcx, 0FFFFFFFFFFFFF000h\nmov rsi, rsp\nsub rsi, rcx\nloc_11E0:\ncmp rsp, rsi\njz short loc_11F7\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\njmp short loc_11E0\nloc_11F7:\nmov rcx, r9\nand ecx, 0FFFh\nsub rsp, rcx\ntest rcx, rcx\njz short loc_120E\nor [rsp+rcx+60h+var_68], 0\nloc_120E:\nmov r15, rsp\ntest r8d, r8d\njle loc_1325\nmov r12, r11\nshr r12, 2\nmov r9, r15\nlea rsi, [r15+r11]\nneg r13\nshl r13, 2\nmov r10d, 0\nloc_1235:\nlea rcx, [rsi+r13]\nloc_1239:\nmov dword ptr [rcx], 0\nadd rcx, 4\ncmp rcx, rsi\njnz short loc_1239\nlea ebx, [r10+1]\nadd rsi, r11\ncmp r8d, ebx\njz short loc_1259\nmov r10d, ebx\njmp short loc_1235\nloc_1259:\nmov r13d, [rdi]\nmovsxd rsi, ebx\nmov r8d, 0\nloc_1265:\nmov ecx, [rdi+r8]\nlea r14d, [rcx+r13]\ncmp ecx, r13d\ncmovg ecx, r14d\nmov [r15+r8], ecx\nadd r8, 4\ncmp r11, r8\njnz short loc_1265\ncmp ebx, 1\njle loc_1325\nlea r13, [r15+r11]\nlea ecx, [r10-1]\nlea rbx, [rcx+2]\nmov [rbp+var_50], rbx\nmov r14, r15\nmov r8, r13\nmov ecx, 1\nmov [rbp+var_54], edx\nmov [rbp+var_58], eax\njmp short loc_1301\nloc_12AD:\nmov [r13+rax*4+0], r11d\njmp short loc_12BC\nloc_12B4:\nmov edx, [r9+rax*4]\nmov [r8+rax*4], edx\nloc_12BC:\nadd rax, 1\ncmp rax, rsi\njz short loc_12E4\nloc_12C5:\nmov edx, [rdi+rax*4]\ncmp eax, ecx\njle short loc_12B4\ncmp edx, ebx\njle short loc_12B4\nadd edx, [r15+r10*4]\nmov r11d, [r14+rax*4]\ncmp edx, r11d\njle short loc_12AD\nmov [r13+rax*4+0], edx\njmp short loc_12BC\nloc_12E4:\nmov r11, [rbp+var_48]\nadd rcx, 1\nadd r13, r11\nadd r9, r11\nadd r8, r11\nadd r14, r11\nmov rax, [rbp+var_50]\ncmp rcx, rax\njz short loc_131F\nloc_1301:\nmov ebx, [rdi+rcx*4]\nmov eax, 0\nmovsxd r10, ecx\nlea edx, [rcx-1]\nmovsxd rdx, edx\nimul rdx, r12\nadd r10, rdx\nmov [rbp+var_48], r11\njmp short loc_12C5\nloc_131F:\nmov edx, [rbp+var_54]\nmov eax, [rbp+var_58]\nloc_1325:\ncdqe\nmovsxd rdx, edx\nshr r11, 2\nimul rdx, r11\nadd rax, rdx\nmov eax, [r15+rax*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_1357\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1357:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2, int a3, int a4)\n{\n __int64 v6; // r13\n unsigned __int64 v7; // r11\n signed __int64 v8; // rcx\n void *v9; // rsp\n unsigned __int64 v10; // r12\n _BYTE *v11; // r9\n _BYTE *v12; // rsi\n __int64 v13; // r13\n int i; // r10d\n _DWORD *v15; // rcx\n int v16; // ebx\n int v17; // r13d\n __int64 v18; // rsi\n unsigned __int64 v19; // r8\n int v20; // ecx\n _BYTE *v21; // r13\n _BYTE *v22; // r14\n _BYTE *v23; // r8\n __int64 v24; // rcx\n __int64 v25; // rax\n int v26; // edx\n int v27; // edx\n int v28; // r11d\n int v29; // ebx\n _BYTE v32[8]; // [rsp+8h] [rbp-60h] BYREF\n int v33; // [rsp+10h] [rbp-58h]\n int v34; // [rsp+14h] [rbp-54h]\n __int64 v35; // [rsp+18h] [rbp-50h]\n unsigned __int64 v36; // [rsp+20h] [rbp-48h]\n unsigned __int64 v37; // [rsp+30h] [rbp-38h]\n\n v37 = __readfsqword(0x28u);\n v6 = a2;\n v7 = 4LL * a2;\n while ( v32 != &v32[-((4 * a2 * (__int64)a2 + 15) & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v8 = (4 * (_WORD)a2 * (_WORD)a2 + 15) & 0xFF0;\n v9 = alloca(v8);\n if ( ((4 * (_WORD)a2 * (_WORD)a2 + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v32[v8 - 8] = *(_QWORD *)&v32[v8 - 8];\n if ( a2 > 0 )\n {\n v10 = v7 >> 2;\n v11 = v32;\n v12 = &v32[v7];\n v13 = -4 * v6;\n for ( i = 0; ; ++i )\n {\n v15 = &v12[v13];\n do\n *v15++ = 0;\n while ( v15 != (_DWORD *)v12 );\n v16 = i + 1;\n v12 += v7;\n if ( a2 == i + 1 )\n break;\n }\n v17 = *a1;\n v18 = v16;\n v19 = 0LL;\n do\n {\n v20 = a1[v19 / 4];\n if ( v20 > v17 )\n v20 += v17;\n *(_DWORD *)&v32[v19] = v20;\n v19 += 4LL;\n }\n while ( v7 != v19 );\n if ( v16 > 1 )\n {\n v21 = &v32[v7];\n v35 = (unsigned int)(i - 1) + 2LL;\n v22 = v32;\n v23 = &v32[v7];\n v24 = 1LL;\n v34 = a3;\n v33 = a4;\n do\n {\n v29 = a1[v24];\n v25 = 0LL;\n v36 = v7;\n do\n {\n v26 = a1[v25];\n if ( (int)v25 <= (int)v24 || v26 <= v29 )\n {\n *(_DWORD *)&v23[4 * v25] = *(_DWORD *)&v11[4 * v25];\n }\n else\n {\n v27 = *(_DWORD *)&v32[4 * v10 * ((int)v24 - 1) + 4 * (int)v24] + v26;\n v28 = *(_DWORD *)&v22[4 * v25];\n if ( v27 <= v28 )\n *(_DWORD *)&v21[4 * v25] = v28;\n else\n *(_DWORD *)&v21[4 * v25] = v27;\n }\n ++v25;\n }\n while ( v25 != v18 );\n v7 = v36;\n ++v24;\n v21 += v36;\n v11 += v36;\n v23 += v36;\n v22 += v36;\n }\n while ( v24 != v35 );\n a3 = v34;\n a4 = v33;\n }\n }\n return *(unsigned int *)&v32[4 * (v7 >> 2) * a3 + 4 * a4];\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 38h\nmov r8d, esi\nmov eax, ecx\nmov rcx, fs:28h\nmov [rbp+var_38], rcx\nxor ecx, ecx\nmovsxd r13, esi\nlea r11, ds:0[r13*4]\nmov rcx, r13\nimul rcx, r13\nlea rcx, ds:0Fh[rcx*4]\nmov r9, rcx\nand r9, 0FFFFFFFFFFFFFFF0h\nand rcx, 0FFFFFFFFFFFFF000h\nmov rsi, rsp\nsub rsi, rcx\nloc_11E0:\ncmp rsp, rsi\njz short loc_11F7\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\njmp short loc_11E0\nloc_11F7:\nmov rcx, r9\nand ecx, 0FFFh\nsub rsp, rcx\ntest rcx, rcx\njz short loc_120E\nor [rsp+rcx+60h+var_68], 0\nloc_120E:\nmov r15, rsp\ntest r8d, r8d\njle loc_1325\nmov r12, r11\nshr r12, 2\nmov r9, r15\nlea rsi, [r15+r11]\nneg r13\nshl r13, 2\nmov r10d, 0\nloc_1235:\nlea rcx, [rsi+r13]\nloc_1239:\nmov dword ptr [rcx], 0\nadd rcx, 4\ncmp rcx, rsi\njnz short loc_1239\nlea ebx, [r10+1]\nadd rsi, r11\ncmp r8d, ebx\njz short loc_1259\nmov r10d, ebx\njmp short loc_1235\nloc_1259:\nmov r13d, [rdi]\nmovsxd rsi, ebx\nmov r8d, 0\nloc_1265:\nmov ecx, [rdi+r8]\nlea r14d, [rcx+r13]\ncmp ecx, r13d\ncmovg ecx, r14d\nmov [r15+r8], ecx\nadd r8, 4\ncmp r11, r8\njnz short loc_1265\ncmp ebx, 1\njle loc_1325\nlea r13, [r15+r11]\nlea ecx, [r10-1]\nlea rbx, [rcx+2]\nmov [rbp+var_50], rbx\nmov r14, r15\nmov r8, r13\nmov ecx, 1\nmov [rbp+var_54], edx\nmov [rbp+var_58], eax\njmp short loc_1301\nloc_12AD:\nmov [r13+rax*4+0], r11d\njmp short loc_12BC\nloc_12B4:\nmov edx, [r9+rax*4]\nmov [r8+rax*4], edx\nloc_12BC:\nadd rax, 1\ncmp rax, rsi\njz short loc_12E4\nloc_12C5:\nmov edx, [rdi+rax*4]\ncmp eax, ecx\njle short loc_12B4\ncmp edx, ebx\njle short loc_12B4\nadd edx, [r15+r10*4]\nmov r11d, [r14+rax*4]\ncmp edx, r11d\njle short loc_12AD\nmov [r13+rax*4+0], edx\njmp short loc_12BC\nloc_12E4:\nmov r11, [rbp+var_48]\nadd rcx, 1\nadd r13, r11\nadd r9, r11\nadd r8, r11\nadd r14, r11\nmov rax, [rbp+var_50]\ncmp rcx, rax\njz short loc_131F\nloc_1301:\nmov ebx, [rdi+rcx*4]\nmov eax, 0\nmovsxd r10, ecx\nlea edx, [rcx-1]\nmovsxd rdx, edx\nimul rdx, r12\nadd r10, rdx\nmov [rbp+var_48], r11\njmp short loc_12C5\nloc_131F:\nmov edx, [rbp+var_54]\nmov eax, [rbp+var_58]\nloc_1325:\ncdqe\nmovsxd rdx, edx\nshr r11, 2\nimul rdx, r11\nadd rax, rdx\nmov eax, [r15+rax*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_1357\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1357:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(int *a1, int a2, int a3, int a4)\n{\n __int64 v6; // r13\n unsigned __int64 v7; // r11\n signed __int64 v8; // rcx\n void *v9; // rsp\n unsigned __int64 v10; // r12\n _BYTE *v11; // r9\n _BYTE *v12; // rsi\n __int64 v13; // r13\n int i; // r10d\n _DWORD *v15; // rcx\n int v16; // ebx\n int v17; // r13d\n __int64 v18; // rsi\n unsigned __int64 v19; // r8\n int v20; // ecx\n _BYTE *v21; // r13\n _BYTE *v22; // r14\n _BYTE *v23; // r8\n __int64 v24; // rcx\n __int64 v25; // rax\n int v26; // edx\n int v27; // edx\n int v28; // r11d\n int v29; // ebx\n _BYTE v32[8]; // [rsp+8h] [rbp-60h] BYREF\n int v33; // [rsp+10h] [rbp-58h]\n int v34; // [rsp+14h] [rbp-54h]\n __int64 v35; // [rsp+18h] [rbp-50h]\n unsigned __int64 v36; // [rsp+20h] [rbp-48h]\n unsigned __int64 v37; // [rsp+30h] [rbp-38h]\n\n v37 = __readfsqword(0x28u);\n v6 = a2;\n v7 = 4LL * a2;\n while ( v32 != &v32[-((4 * a2 * (__int64)a2 + 15) & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v8 = (4 * (_WORD)a2 * (_WORD)a2 + 15) & 0xFF0;\n v9 = alloca(v8);\n if ( ((4 * (_WORD)a2 * (_WORD)a2 + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v32[v8 - 8] = *(_QWORD *)&v32[v8 - 8];\n if ( a2 > 0 )\n {\n v10 = v7 >> 2;\n v11 = v32;\n v12 = &v32[v7];\n v13 = -4 * v6;\n for ( i = 0; ; ++i )\n {\n v15 = &v12[v13];\n do\n *v15++ = 0;\n while ( v15 != (_DWORD *)v12 );\n v16 = i + 1;\n v12 += v7;\n if ( a2 == i + 1 )\n break;\n }\n v17 = *a1;\n v18 = v16;\n v19 = 0LL;\n do\n {\n v20 = a1[v19 / 4];\n if ( v20 > v17 )\n v20 += v17;\n *(_DWORD *)&v32[v19] = v20;\n v19 += 4LL;\n }\n while ( v7 != v19 );\n if ( v16 > 1 )\n {\n v21 = &v32[v7];\n v35 = (unsigned int)(i - 1) + 2LL;\n v22 = v32;\n v23 = &v32[v7];\n v24 = 1LL;\n v34 = a3;\n v33 = a4;\n do\n {\n v29 = a1[v24];\n v25 = 0LL;\n v36 = v7;\n do\n {\n v26 = a1[v25];\n if ( (int)v25 <= (int)v24 || v26 <= v29 )\n {\n *(_DWORD *)&v23[4 * v25] = *(_DWORD *)&v11[4 * v25];\n }\n else\n {\n v27 = *(_DWORD *)&v32[4 * v10 * ((int)v24 - 1) + 4 * (int)v24] + v26;\n v28 = *(_DWORD *)&v22[4 * v25];\n if ( v27 <= v28 )\n *(_DWORD *)&v21[4 * v25] = v28;\n else\n *(_DWORD *)&v21[4 * v25] = v27;\n }\n ++v25;\n }\n while ( v25 != v18 );\n v7 = v36;\n ++v24;\n v21 += v36;\n v11 += v36;\n v23 += v36;\n v22 += v36;\n }\n while ( v24 != v35 );\n a3 = v34;\n a4 = v33;\n }\n }\n return *(unsigned int *)&v32[4 * (v7 >> 2) * a3 + 4 * a4];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(int *a1, int a2, int a3, int a4) {\n long long v6;\n unsigned long long v7;\n signed long long v8;\n void *v9;\n unsigned long long v10;\n uint8_t *v11;\n uint8_t *v12;\n long long v13;\n int i;\n uint32_t *v15;\n int v16;\n int v17;\n long long v18;\n unsigned long long v19;\n int v20;\n uint8_t *v21;\n uint8_t *v22;\n uint8_t *v23;\n long long v24;\n long long v25;\n int v26;\n int v27;\n int v28;\n int v29;\n uint8_t v32[8];\n int v33;\n int v34;\n long long v35;\n unsigned long long v36;\n unsigned long long v37;\n v37 = __readfsqword(40u);\n v6 = a2;\n v7 = 4LL * a2;\n while (v32 != &v32[-((4 * a2 * (long long)a2 + 15) & 18446744073709547520LL)])\n ;\n v8 = (4 * (unsigned short)a2 * (unsigned short)a2 + 15) & 4080;\n v9 = alloca(v8);\n if (((4 * (unsigned short)a2 * (unsigned short)a2 + 15) & 4080) != 0)\n *(uint64_t *)&v32[v8 - 8] = *(uint64_t *)&v32[v8 - 8];\n if (a2 > 0) {\n v10 = v7 >> 2;\n v11 = v32;\n v12 = &v32[v7];\n v13 = -4 * v6;\n for (i = 0;; ++i) {\n v15 = &v12[v13];\n do\n *v15++ = 0;\n while (v15 != (uint32_t *)v12);\n v16 = i + 1;\n v12 += v7;\n if (a2 == i + 1) break;\n }\n v17 = *a1;\n v18 = v16;\n v19 = 0LL;\n do {\n v20 = a1[v19 / 4];\n if (v20 > v17) v20 += v17;\n *(uint32_t *)&v32[v19] = v20;\n v19 += 4LL;\n } while (v7 != v19);\n if (v16 > 1) {\n v21 = &v32[v7];\n v35 = (unsigned int)(i - 1) + 2LL;\n v22 = v32;\n v23 = &v32[v7];\n v24 = 1LL;\n v34 = a3;\n v33 = a4;\n do {\n v29 = a1[v24];\n v25 = 0LL;\n v36 = v7;\n do {\n v26 = a1[v25];\n if ((int)v25 <= (int)v24 || v26 <= v29) {\n *(uint32_t *)&v23[4 * v25] = *(uint32_t *)&v11[4 * v25];\n } else {\n v27 = *(uint32_t *)&v32[4 * v10 * ((int)v24 - 1) + 4 * (int)v24] +\n v26;\n v28 = *(uint32_t *)&v22[4 * v25];\n if (v27 <= v28)\n *(uint32_t *)&v21[4 * v25] = v28;\n else\n *(uint32_t *)&v21[4 * v25] = v27;\n }\n ++v25;\n } while (v25 != v18);\n v7 = v36;\n ++v24;\n v21 += v36;\n v11 += v36;\n v23 += v36;\n v22 += v36;\n } while (v24 != v35);\n a3 = v34;\n a4 = v33;\n }\n }\n return *(unsigned int *)&v32[4 * (v7 >> 2) * a3 + 4 * a4];\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2, int a3, int a4) {\n long long v6;\n unsigned long long v7;\n signed long long v8;\n void *v9;\n unsigned long long v10;\n uint8_t *v11;\n uint8_t *v12;\n long long v13;\n int i;\n uint32_t *v15;\n int v16;\n int v17;\n long long v18;\n unsigned long long v19;\n int v20;\n uint8_t *v21;\n uint8_t *v22;\n uint8_t *v23;\n long long v24;\n long long v25;\n int v26;\n int v27;\n int v28;\n int v29;\n uint8_t v32[8];\n int v33;\n int v34;\n long long v35;\n unsigned long long v36;\n unsigned long long v37;\n v37 = __readfsqword(40u);\n v6 = a2;\n v7 = 4LL * a2;\n while (v32 != &v32[-((4 * a2 * (long long)a2 + 15) & 18446744073709547520LL)])\n ;\n v8 = (4 * (unsigned short)a2 * (unsigned short)a2 + 15) & 4080;\n v9 = alloca(v8);\n if (((4 * (unsigned short)a2 * (unsigned short)a2 + 15) & 4080) != 0)\n *(uint64_t *)&v32[v8 - 8] = *(uint64_t *)&v32[v8 - 8];\n if (a2 > 0) {\n v10 = v7 >> 2;\n v11 = v32;\n v12 = &v32[v7];\n v13 = -4 * v6;\n for (i = 0;; ++i) {\n v15 = &v12[v13];\n do\n *v15++ = 0;\n while (v15 != (uint32_t *)v12);\n v16 = i + 1;\n v12 += v7;\n if (a2 == i + 1) break;\n }\n v17 = *a1;\n v18 = v16;\n v19 = 0LL;\n do {\n v20 = a1[v19 / 4];\n if (v20 > v17) v20 += v17;\n *(uint32_t *)&v32[v19] = v20;\n v19 += 4LL;\n } while (v7 != v19);\n if (v16 > 1) {\n v21 = &v32[v7];\n v35 = (unsigned int)(i - 1) + 2LL;\n v22 = v32;\n v23 = &v32[v7];\n v24 = 1LL;\n v34 = a3;\n v33 = a4;\n do {\n v29 = a1[v24];\n v25 = 0LL;\n v36 = v7;\n do {\n v26 = a1[v25];\n if ((int)v25 <= (int)v24 || v26 <= v29) {\n *(uint32_t *)&v23[4 * v25] = *(uint32_t *)&v11[4 * v25];\n } else {\n v27 = *(uint32_t *)&v32[4 * v10 * ((int)v24 - 1) + 4 * (int)v24] +\n v26;\n v28 = *(uint32_t *)&v22[4 * v25];\n if (v27 <= v28)\n *(uint32_t *)&v21[4 * v25] = v28;\n else\n *(uint32_t *)&v21[4 * v25] = v27;\n }\n ++v25;\n } while (v25 != v18);\n v7 = v36;\n ++v24;\n v21 += v36;\n v11 += v36;\n v23 += v36;\n v22 += v36;\n } while (v24 != v35);\n a3 = v34;\n a4 = v33;\n }\n }\n return *(unsigned int *)&v32[4 * (v7 >> 2) * a3 + 4 * a4];\n}" + }, + { + "index": 306, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int a[], int n, int index, int k) {\n int dp[n][n];\n for (int i = 0; i < n; i++) {\n for (int j = 0; j < n; j++) {\n dp[i][j] = 0;\n }\n }\n for (int i = 0; i < n; i++) {\n if (a[i] > a[0]) {\n dp[0][i] = a[i] + a[0];\n } else {\n dp[0][i] = a[i];\n }\n }\n for (int i = 1; i < n; i++) {\n for (int j = 0; j < n; j++) {\n if (a[j] > a[i] && j > i) {\n if (dp[i - 1][i] + a[j] > dp[i - 1][j]) {\n dp[i][j] = dp[i - 1][i] + a[j];\n } else {\n dp[i][j] = dp[i - 1][j];\n }\n } else {\n dp[i][j] = dp[i - 1][j];\n }\n }\n }\n return dp[index][k];\n}", + "test": "int main() {\n\n int a1[] = {1, 101, 2, 3, 100, 4, 5};\n\n int a2[] = {11, 15, 19, 21, 26, 28, 31};\n\n\n\n assert(func0(a1, 7, 4, 6) == 11);\n\n assert(func0(a1, 7, 2, 5) == 7);\n\n assert(func0(a2, 7, 2, 4) == 71);\n\n\n\n printf(\"All test cases passed\\n\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0x38,%rsp\nmov %edx,-0x5c(%rbp)\nmov %ecx,-0x60(%rbp)\nmov %rsp,%rbx\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nmovslq %esi,%rax\nlea 0x0(,%rax,4),%r15\nimul %rax,%rax\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rbx\nand $0xfffffffffffffff0,%rdx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 1371 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 135c \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 14ee \nmov %r15,%rax\nmov %rsp,%r13\nshr $0x2,%rax\nmov %rax,-0x58(%rbp)\ntest %esi,%esi\njle 13ee \nlea -0x1(%rsi),%r8d\nxor %ecx,%ecx\nmov %r8,%r11\nadd $0x1,%r8\nlea 0x0(%r13,%r8,4),%rdx\nneg %r8\nshl $0x2,%r8\nxchg %ax,%ax\nlea (%r8,%rdx,1),%rax\nnopl 0x0(%rax)\nmovl $0x0,(%rax)\nadd $0x4,%rax\ncmp %rdx,%rax\njne 13b8 \nlea 0x1(%rcx),%eax\nadd %r15,%rdx\ncmp %eax,%esi\nje 1428 \nmov %eax,%ecx\njmp 13b0 \nnopl (%rax)\nadd $0x1,%r12\nadd $0x1,%r8\nadd -0x50(%rbp),%r14\ncmp -0x48(%rbp),%r8\njne 1488 \nmovslq -0x5c(%rbp),%rax\nimul -0x58(%rbp),%rax\nmovslq -0x60(%rbp),%rdx\nadd %rdx,%rax\nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\nmov 0x0(%r13,%rax,4),%eax\njne 14f9 \nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\nnopl (%rax)\nmov (%rdi),%r8d\nlea 0x0(,%rcx,4),%r9\nxor %ecx,%ecx\nmov %r8d,%eax\njmp 1448 \nnopw 0x0(%rax,%rax,1)\nmov 0x4(%rdi,%rcx,1),%eax\nadd $0x4,%rcx\nlea (%r8,%rax,1),%edx\ncmp %eax,%r8d\ncmovl %edx,%eax\nmov %eax,0x0(%r13,%rcx,1)\ncmp %r9,%rcx\njne 1440 \ncmp $0x1,%esi\njle 13ee \nlea -0x2(%rsi),%eax\nmov %r15,-0x50(%rbp)\nlea 0x0(%r13,%r15,1),%r14\nmov -0x58(%rbp),%r15\nadd $0x2,%rax\nmov $0x1,%r8d\nxor %r12d,%r12d\nmov %rax,-0x48(%rbp)\nnopw 0x0(%rax,%rax,1)\nmov %r12,%r9\nmovslq %r12d,%rcx\nmovslq %r8d,%rbx\nmov (%rdi,%r8,4),%r10d\nimul %r15,%rcx\nsub %r8,%r9\nmov %r14,%rdx\nxor %eax,%eax\nimul %r15,%r9\nadd %rcx,%rbx\nnopl 0x0(%rax,%rax,1)\nmov (%rdi,%rax,4),%ecx\nmov (%rdx,%r9,4),%esi\ncmp %r10d,%ecx\njle 14c1 \ncmp %r8d,%eax\njg 14e0 \nmov %esi,(%rdx)\nlea 0x1(%rax),%rcx\nadd $0x4,%rdx\ncmp %r11,%rax\nje 13d8 \nmov %rcx,%rax\njmp 14b0 \nnopl 0x0(%rax)\nadd 0x0(%r13,%rbx,4),%ecx\ncmp %esi,%ecx\ncmovle %esi,%ecx\nmov %ecx,(%rdx)\njmp 14c3 \norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 1383 \ncallq 1080 <__stack_chk_fail@plt>\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmovsxd rax, ecx\nmov rbp, rsp\npush r15\npush r14\npush r13\nmovsxd r13, esi\npush r12\nlea r14, ds:0[r13*4]\npush rbx\nmov rbx, rdi\nsub rsp, 48h\nmov rcx, fs:28h\nmov [rbp+var_38], rcx\nxor ecx, ecx\nmov rcx, r13\nmov r8, rsp\nimul rcx, r13\nlea rcx, ds:0Fh[rcx*4]\nmov rdi, rcx\nand rcx, 0FFFFFFFFFFFFF000h\nsub r8, rcx\nand rdi, 0FFFFFFFFFFFFFFF0h\ncmp rsp, r8\njz short loc_1362\nloc_134D:\nsub rsp, 1000h\nor [rsp+1070h+var_78], 0\ncmp rsp, r8\njnz short loc_134D\nloc_1362:\nand edi, 0FFFh\nsub rsp, rdi\ntest rdi, rdi\njnz loc_14CA\nloc_1374:\nmov r11, r14\nmov r10, rsp\nshr r11, 2\ntest esi, esi\njle loc_149E\nmov r15d, esi\nmov [rbp+var_50], r10\nmov rdi, r10; s\nmov r12d, esi\nmov [rbp+var_58], r11\nlea rcx, ds:0[r15*4]\nxor r15d, r15d\nmov [rbp+var_64], edx\nmov [rbp+var_70], r10\nmov [rbp+var_48], r13\nmov r13d, r15d\nmov r15d, eax\nmov [rbp+var_60], rbx\nmov rbx, rcx\nnop word ptr [rax+rax+00h]\nloc_13C0:\nmov rdx, rbx; n\nxor esi, esi; c\nadd r13d, 1\ncall _memset\nmov rdi, rax\nadd rdi, r14\ncmp r12d, r13d\njnz short loc_13C0\nmov rbx, [rbp+var_60]\nmov esi, r12d\nmovsxd rax, r15d\nmov r11, [rbp+var_58]\nmov r15d, r13d\nmov r12, [rbp+var_50]\nmov edx, [rbp+var_64]\nxor r8d, r8d\nmov r13, [rbp+var_48]\nmov r10, [rbp+var_70]\nmov r9d, [rbx]\nnop\nloc_1400:\nmov ecx, [rbx+r8]\ncmp ecx, r9d\nlea edi, [rcx+r9]\ncmovg ecx, edi\nmov [r10+r8], ecx\nadd r8, 4\ncmp r14, r8\njnz short loc_1400\ncmp r15d, 1\njz short loc_149E\nmov [rbp+var_48], r14\nlea ecx, [rsi-2]\nlea rdi, [r10+r14]\nmov esi, 1\nmov dword ptr [rbp+var_50], edx\nadd rcx, 2\nxor r15d, r15d\nmov dword ptr [rbp+var_58], eax\nxchg ax, ax\nloc_1440:\nmovsxd rdx, r15d\nmovsxd r8, esi\nmov r9d, [rbx+rsi*4]\nxor eax, eax\nimul rdx, r11\nadd r8, rdx\nnop dword ptr [rax+rax+00h]\nloc_1458:\nmov r14d, [rbx+rax*4]\nmov edx, [r12+rax*4]\ncmp eax, esi\njle short loc_1474\ncmp r14d, r9d\njle short loc_1474\nadd r14d, [r10+r8*4]\ncmp edx, r14d\ncmovl edx, r14d\nloc_1474:\nmov [rdi+rax*4], edx\nadd rax, 1\ncmp r13, rax\njnz short loc_1458\nmov rax, [rbp+var_48]\nadd rsi, 1\nadd r15d, 1\nadd rdi, rax\nadd r12, rax\ncmp rcx, rsi\njnz short loc_1440\nmov edx, dword ptr [rbp+var_50]\nmovsxd rax, dword ptr [rbp+var_58]\nloc_149E:\nmovsxd rdx, edx\nimul rdx, r11\nadd rax, rdx\nmov eax, [r10+rax*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_14D5\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_14CA:\nor [rsp+rdi+1070h+var_1078], 0\njmp loc_1374\nloc_14D5:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2, int a3, int a4)\n{\n __int64 v4; // rax\n unsigned __int64 v5; // r14\n __int64 v7; // rdi\n _BYTE *v8; // r8\n __int16 v9; // di\n signed __int64 v10; // rdi\n void *v11; // rsp\n _BYTE *v12; // r10\n unsigned __int64 v13; // r11\n char *v14; // rdi\n int v15; // r13d\n _DWORD *v17; // rbx\n int v18; // r15d\n _BYTE *v19; // r12\n unsigned __int64 v20; // r8\n __int64 v21; // r13\n int v22; // r9d\n int v23; // ecx\n __int64 v24; // rcx\n _BYTE *v25; // rdi\n __int64 v26; // rsi\n __int64 v27; // rcx\n int v28; // r15d\n int v29; // r9d\n __int64 v30; // rax\n int v31; // r14d\n int v32; // edx\n int v33; // r14d\n _BYTE v36[4088]; // [rsp+8h] [rbp-1070h] BYREF\n _BYTE *v37; // [rsp+1008h] [rbp-70h] BYREF\n int v38; // [rsp+1014h] [rbp-64h]\n _DWORD *v39; // [rsp+1018h] [rbp-60h]\n unsigned __int64 v40; // [rsp+1020h] [rbp-58h]\n _BYTE *v41; // [rsp+1028h] [rbp-50h]\n __int64 v42; // [rsp+1030h] [rbp-48h]\n unsigned __int64 v43; // [rsp+1040h] [rbp-38h]\n\n v4 = a4;\n v5 = 4LL * a2;\n v43 = __readfsqword(0x28u);\n v7 = 4 * a2 * (__int64)a2 + 15;\n v8 = (char *)&v37 - (v7 & 0xFFFFFFFFFFFFF000LL);\n v9 = v7 & 0xFFF0;\n if ( &v37 != (_BYTE **)v8 )\n {\n while ( v36 != v8 )\n ;\n }\n v10 = v9 & 0xFFF;\n v11 = alloca(v10);\n if ( v10 )\n *(_QWORD *)&v36[v10 - 8] = *(_QWORD *)&v36[v10 - 8];\n v12 = v36;\n v13 = v5 >> 2;\n if ( a2 > 0 )\n {\n v41 = v36;\n v14 = v36;\n v40 = v5 >> 2;\n v38 = a3;\n v37 = v36;\n v42 = a2;\n v15 = 0;\n v39 = a1;\n do\n {\n ++v15;\n v14 = (char *)memset(v14, 0, 4LL * (unsigned int)a2) + v5;\n }\n while ( a2 != v15 );\n v17 = v39;\n v4 = a4;\n v13 = v40;\n v18 = v15;\n v19 = v41;\n a3 = v38;\n v20 = 0LL;\n v21 = v42;\n v12 = v37;\n v22 = *v39;\n do\n {\n v23 = v17[v20 / 4];\n if ( v23 > v22 )\n v23 += v22;\n *(_DWORD *)&v12[v20] = v23;\n v20 += 4LL;\n }\n while ( v5 != v20 );\n if ( v18 != 1 )\n {\n v42 = 4LL * a2;\n v24 = (unsigned int)(a2 - 2);\n v25 = &v12[v5];\n v26 = 1LL;\n LODWORD(v41) = a3;\n v27 = v24 + 2;\n v28 = 0;\n LODWORD(v40) = v4;\n do\n {\n v29 = v17[v26];\n v30 = 0LL;\n do\n {\n v31 = v17[v30];\n v32 = *(_DWORD *)&v19[4 * v30];\n if ( (int)v30 > (int)v26 && v31 > v29 )\n {\n v33 = *(_DWORD *)&v12[4 * v13 * v28 + 4 * (int)v26] + v31;\n if ( v32 < v33 )\n v32 = v33;\n }\n *(_DWORD *)&v25[4 * v30++] = v32;\n }\n while ( v21 != v30 );\n ++v26;\n ++v28;\n v25 += v42;\n v19 += v42;\n }\n while ( v27 != v26 );\n a3 = (int)v41;\n v4 = (int)v40;\n }\n }\n return *(unsigned int *)&v12[4 * v13 * a3 + 4 * v4];\n}", + "ida_strip_asm": "sub_12F0:\nendbr64\npush rbp\nmovsxd rax, ecx\nmov rbp, rsp\npush r15\npush r14\npush r13\nmovsxd r13, esi\npush r12\nlea r14, ds:0[r13*4]\npush rbx\nmov rbx, rdi\nsub rsp, 48h\nmov rcx, fs:28h\nmov [rbp+var_38], rcx\nxor ecx, ecx\nmov rcx, r13\nmov r8, rsp\nimul rcx, r13\nlea rcx, ds:0Fh[rcx*4]\nmov rdi, rcx\nand rcx, 0FFFFFFFFFFFFF000h\nsub r8, rcx\nand rdi, 0FFFFFFFFFFFFFFF0h\ncmp rsp, r8\njz short loc_1362\nloc_134D:\nsub rsp, 1000h\nor [rsp+1070h+var_78], 0\ncmp rsp, r8\njnz short loc_134D\nloc_1362:\nand edi, 0FFFh\nsub rsp, rdi\ntest rdi, rdi\njnz loc_14CA\nloc_1374:\nmov r11, r14\nmov r10, rsp\nshr r11, 2\ntest esi, esi\njle loc_149E\nmov r15d, esi\nmov [rbp+var_50], r10\nmov rdi, r10; s\nmov r12d, esi\nmov [rbp+var_58], r11\nlea rcx, ds:0[r15*4]\nxor r15d, r15d\nmov [rbp+var_64], edx\nmov [rbp+var_70], r10\nmov [rbp+var_48], r13\nmov r13d, r15d\nmov r15d, eax\nmov [rbp+var_60], rbx\nmov rbx, rcx\nnop word ptr [rax+rax+00h]\nloc_13C0:\nmov rdx, rbx; n\nxor esi, esi; c\nadd r13d, 1\ncall _memset\nmov rdi, rax\nadd rdi, r14\ncmp r12d, r13d\njnz short loc_13C0\nmov rbx, [rbp+var_60]\nmov esi, r12d\nmovsxd rax, r15d\nmov r11, [rbp+var_58]\nmov r15d, r13d\nmov r12, [rbp+var_50]\nmov edx, [rbp+var_64]\nxor r8d, r8d\nmov r13, [rbp+var_48]\nmov r10, [rbp+var_70]\nmov r9d, [rbx]\nnop\nloc_1400:\nmov ecx, [rbx+r8]\ncmp ecx, r9d\nlea edi, [rcx+r9]\ncmovg ecx, edi\nmov [r10+r8], ecx\nadd r8, 4\ncmp r14, r8\njnz short loc_1400\ncmp r15d, 1\njz short loc_149E\nmov [rbp+var_48], r14\nlea ecx, [rsi-2]\nlea rdi, [r10+r14]\nmov esi, 1\nmov dword ptr [rbp+var_50], edx\nadd rcx, 2\nxor r15d, r15d\nmov dword ptr [rbp+var_58], eax\nxchg ax, ax\nloc_1440:\nmovsxd rdx, r15d\nmovsxd r8, esi\nmov r9d, [rbx+rsi*4]\nxor eax, eax\nimul rdx, r11\nadd r8, rdx\nnop dword ptr [rax+rax+00h]\nloc_1458:\nmov r14d, [rbx+rax*4]\nmov edx, [r12+rax*4]\ncmp eax, esi\njle short loc_1474\ncmp r14d, r9d\njle short loc_1474\nadd r14d, [r10+r8*4]\ncmp edx, r14d\ncmovl edx, r14d\nloc_1474:\nmov [rdi+rax*4], edx\nadd rax, 1\ncmp r13, rax\njnz short loc_1458\nmov rax, [rbp+var_48]\nadd rsi, 1\nadd r15d, 1\nadd rdi, rax\nadd r12, rax\ncmp rcx, rsi\njnz short loc_1440\nmov edx, dword ptr [rbp+var_50]\nmovsxd rax, dword ptr [rbp+var_58]\nloc_149E:\nmovsxd rdx, edx\nimul rdx, r11\nadd rax, rdx\nmov eax, [r10+rax*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_14D5\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_14CA:\nor [rsp+rdi+1070h+var_1078], 0\njmp loc_1374\nloc_14D5:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12F0(_DWORD *a1, int a2, int a3, int a4)\n{\n __int64 v4; // rax\n unsigned __int64 v5; // r14\n __int64 v7; // rdi\n _BYTE *v8; // r8\n __int16 v9; // di\n signed __int64 v10; // rdi\n void *v11; // rsp\n _BYTE *v12; // r10\n unsigned __int64 v13; // r11\n char *v14; // rdi\n int v15; // r13d\n _DWORD *v17; // rbx\n int v18; // r15d\n _BYTE *v19; // r12\n unsigned __int64 v20; // r8\n __int64 v21; // r13\n int v22; // r9d\n int v23; // ecx\n __int64 v24; // rcx\n _BYTE *v25; // rdi\n __int64 v26; // rsi\n __int64 v27; // rcx\n int v28; // r15d\n int v29; // r9d\n __int64 v30; // rax\n int v31; // r14d\n int v32; // edx\n int v33; // r14d\n _BYTE v36[4088]; // [rsp+8h] [rbp-1070h] BYREF\n _BYTE *v37; // [rsp+1008h] [rbp-70h] BYREF\n int v38; // [rsp+1014h] [rbp-64h]\n _DWORD *v39; // [rsp+1018h] [rbp-60h]\n unsigned __int64 v40; // [rsp+1020h] [rbp-58h]\n _BYTE *v41; // [rsp+1028h] [rbp-50h]\n __int64 v42; // [rsp+1030h] [rbp-48h]\n unsigned __int64 v43; // [rsp+1040h] [rbp-38h]\n\n v4 = a4;\n v5 = 4LL * a2;\n v43 = __readfsqword(0x28u);\n v7 = 4 * a2 * (__int64)a2 + 15;\n v8 = (char *)&v37 - (v7 & 0xFFFFFFFFFFFFF000LL);\n v9 = v7 & 0xFFF0;\n if ( &v37 != (_BYTE **)v8 )\n {\n while ( v36 != v8 )\n ;\n }\n v10 = v9 & 0xFFF;\n v11 = alloca(v10);\n if ( v10 )\n *(_QWORD *)&v36[v10 - 8] = *(_QWORD *)&v36[v10 - 8];\n v12 = v36;\n v13 = v5 >> 2;\n if ( a2 > 0 )\n {\n v41 = v36;\n v14 = v36;\n v40 = v5 >> 2;\n v38 = a3;\n v37 = v36;\n v42 = a2;\n v15 = 0;\n v39 = a1;\n do\n {\n ++v15;\n v14 = (char *)memset(v14, 0, 4LL * (unsigned int)a2) + v5;\n }\n while ( a2 != v15 );\n v17 = v39;\n v4 = a4;\n v13 = v40;\n v18 = v15;\n v19 = v41;\n a3 = v38;\n v20 = 0LL;\n v21 = v42;\n v12 = v37;\n v22 = *v39;\n do\n {\n v23 = v17[v20 / 4];\n if ( v23 > v22 )\n v23 += v22;\n *(_DWORD *)&v12[v20] = v23;\n v20 += 4LL;\n }\n while ( v5 != v20 );\n if ( v18 != 1 )\n {\n v42 = 4LL * a2;\n v24 = (unsigned int)(a2 - 2);\n v25 = &v12[v5];\n v26 = 1LL;\n LODWORD(v41) = a3;\n v27 = v24 + 2;\n v28 = 0;\n LODWORD(v40) = v4;\n do\n {\n v29 = v17[v26];\n v30 = 0LL;\n do\n {\n v31 = v17[v30];\n v32 = *(_DWORD *)&v19[4 * v30];\n if ( (int)v30 > (int)v26 && v31 > v29 )\n {\n v33 = *(_DWORD *)&v12[4 * v13 * v28 + 4 * (int)v26] + v31;\n if ( v32 < v33 )\n v32 = v33;\n }\n *(_DWORD *)&v25[4 * v30++] = v32;\n }\n while ( v21 != v30 );\n ++v26;\n ++v28;\n v25 += v42;\n v19 += v42;\n }\n while ( v27 != v26 );\n a3 = (int)v41;\n v4 = (int)v40;\n }\n }\n return *(unsigned int *)&v12[4 * v13 * a3 + 4 * v4];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12F0(uint32_t *a1, int a2, int a3, int a4) {\n long long v4;\n unsigned long long v5;\n long long v7;\n uint8_t *v8;\n short v9;\n signed long long v10;\n void *v11;\n uint8_t *v12;\n unsigned long long v13;\n char *v14;\n int v15;\n uint32_t *v17;\n int v18;\n uint8_t *v19;\n unsigned long long v20;\n long long v21;\n int v22;\n int v23;\n long long v24;\n uint8_t *v25;\n long long v26;\n long long v27;\n int v28;\n int v29;\n long long v30;\n int v31;\n int v32;\n int v33;\n uint8_t v36[4088];\n uint8_t *v37;\n int v38;\n uint32_t *v39;\n unsigned long long v40;\n uint8_t *v41;\n long long v42;\n unsigned long long v43;\n v4 = a4;\n v5 = 4LL * a2;\n v43 = __readfsqword(40u);\n v7 = 4 * a2 * (long long)a2 + 15;\n v8 = (char *)&v37 - (v7 & 18446744073709547520LL);\n v9 = v7 & 65520;\n if (&v37 != (uint8_t **)v8) {\n while (v36 != v8)\n ;\n }\n v10 = v9 & 4095;\n v11 = alloca(v10);\n if (v10) *(uint64_t *)&v36[v10 - 8] = *(uint64_t *)&v36[v10 - 8];\n v12 = v36;\n v13 = v5 >> 2;\n if (a2 > 0) {\n v41 = v36;\n v14 = v36;\n v40 = v5 >> 2;\n v38 = a3;\n v37 = v36;\n v42 = a2;\n v15 = 0;\n v39 = a1;\n do {\n ++v15;\n v14 = (char *)memset(v14, 0, 4LL * (unsigned int)a2) + v5;\n } while (a2 != v15);\n v17 = v39;\n v4 = a4;\n v13 = v40;\n v18 = v15;\n v19 = v41;\n a3 = v38;\n v20 = 0LL;\n v21 = v42;\n v12 = v37;\n v22 = *v39;\n do {\n v23 = v17[v20 / 4];\n if (v23 > v22) v23 += v22;\n *(uint32_t *)&v12[v20] = v23;\n v20 += 4LL;\n } while (v5 != v20);\n if (v18 != 1) {\n v42 = 4LL * a2;\n v24 = (unsigned int)(a2 - 2);\n v25 = &v12[v5];\n v26 = 1LL;\n LODWORD(v41) = a3;\n v27 = v24 + 2;\n v28 = 0;\n LODWORD(v40) = v4;\n do {\n v29 = v17[v26];\n v30 = 0LL;\n do {\n v31 = v17[v30];\n v32 = *(uint32_t *)&v19[4 * v30];\n if ((int)v30 > (int)v26 && v31 > v29) {\n v33 = *(uint32_t *)&v12[4 * v13 * v28 + 4 * (int)v26] + v31;\n if (v32 < v33) v32 = v33;\n }\n *(uint32_t *)&v25[4 * v30++] = v32;\n } while (v21 != v30);\n ++v26;\n ++v28;\n v25 += v42;\n v19 += v42;\n } while (v27 != v26);\n a3 = (int)v41;\n v4 = (int)v40;\n }\n }\n return *(unsigned int *)&v12[4 * v13 * a3 + 4 * v4];\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2, int a3, int a4) {\n long long v4;\n unsigned long long v5;\n long long v7;\n uint8_t *v8;\n short v9;\n signed long long v10;\n void *v11;\n uint8_t *v12;\n unsigned long long v13;\n char *v14;\n int v15;\n uint32_t *v17;\n int v18;\n uint8_t *v19;\n unsigned long long v20;\n long long v21;\n int v22;\n int v23;\n long long v24;\n uint8_t *v25;\n long long v26;\n long long v27;\n int v28;\n int v29;\n long long v30;\n int v31;\n int v32;\n int v33;\n uint8_t v36[4088];\n uint8_t *v37;\n int v38;\n uint32_t *v39;\n unsigned long long v40;\n uint8_t *v41;\n long long v42;\n unsigned long long v43;\n v4 = a4;\n v5 = 4LL * a2;\n v43 = __readfsqword(40u);\n v7 = 4 * a2 * (long long)a2 + 15;\n v8 = (char *)&v37 - (v7 & 18446744073709547520LL);\n v9 = v7 & 65520;\n if (&v37 != (uint8_t **)v8) {\n while (v36 != v8)\n ;\n }\n v10 = v9 & 4095;\n v11 = alloca(v10);\n if (v10) *(uint64_t *)&v36[v10 - 8] = *(uint64_t *)&v36[v10 - 8];\n v12 = v36;\n v13 = v5 >> 2;\n if (a2 > 0) {\n v41 = v36;\n v14 = v36;\n v40 = v5 >> 2;\n v38 = a3;\n v37 = v36;\n v42 = a2;\n v15 = 0;\n v39 = a1;\n do {\n ++v15;\n v14 = (char *)memset(v14, 0, 4LL * (unsigned int)a2) + v5;\n } while (a2 != v15);\n v17 = v39;\n v4 = a4;\n v13 = v40;\n v18 = v15;\n v19 = v41;\n a3 = v38;\n v20 = 0LL;\n v21 = v42;\n v12 = v37;\n v22 = *v39;\n do {\n v23 = v17[v20 / 4];\n if (v23 > v22) v23 += v22;\n *(uint32_t *)&v12[v20] = v23;\n v20 += 4LL;\n } while (v5 != v20);\n if (v18 != 1) {\n v42 = 4LL * a2;\n v24 = (unsigned int)(a2 - 2);\n v25 = &v12[v5];\n v26 = 1LL;\n LODWORD(v41) = a3;\n v27 = v24 + 2;\n v28 = 0;\n LODWORD(v40) = v4;\n do {\n v29 = v17[v26];\n v30 = 0LL;\n do {\n v31 = v17[v30];\n v32 = *(uint32_t *)&v19[4 * v30];\n if ((int)v30 > (int)v26 && v31 > v29) {\n v33 = *(uint32_t *)&v12[4 * v13 * v28 + 4 * (int)v26] + v31;\n if (v32 < v33) v32 = v33;\n }\n *(uint32_t *)&v25[4 * v30++] = v32;\n } while (v21 != v30);\n ++v26;\n ++v28;\n v25 += v42;\n v19 += v42;\n } while (v27 != v26);\n a3 = (int)v41;\n v4 = (int)v40;\n }\n }\n return *(unsigned int *)&v12[4 * v13 * a3 + 4 * v4];\n}" + }, + { + "index": 306, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int a[], int n, int index, int k) {\n int dp[n][n];\n for (int i = 0; i < n; i++) {\n for (int j = 0; j < n; j++) {\n dp[i][j] = 0;\n }\n }\n for (int i = 0; i < n; i++) {\n if (a[i] > a[0]) {\n dp[0][i] = a[i] + a[0];\n } else {\n dp[0][i] = a[i];\n }\n }\n for (int i = 1; i < n; i++) {\n for (int j = 0; j < n; j++) {\n if (a[j] > a[i] && j > i) {\n if (dp[i - 1][i] + a[j] > dp[i - 1][j]) {\n dp[i][j] = dp[i - 1][i] + a[j];\n } else {\n dp[i][j] = dp[i - 1][j];\n }\n } else {\n dp[i][j] = dp[i - 1][j];\n }\n }\n }\n return dp[index][k];\n}", + "test": "int main() {\n\n int a1[] = {1, 101, 2, 3, 100, 4, 5};\n\n int a2[] = {11, 15, 19, 21, 26, 28, 31};\n\n\n\n assert(func0(a1, 7, 4, 6) == 11);\n\n assert(func0(a1, 7, 2, 5) == 7);\n\n assert(func0(a2, 7, 2, 4) == 71);\n\n\n\n printf(\"All test cases passed\\n\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\nmov %esi,%r14d\npush %r13\npush %r12\nmov %rdi,%r12\npush %rbx\nsub $0x48,%rsp\nmov %edx,-0x5c(%rbp)\nmov %ecx,-0x60(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nmovslq %esi,%rax\nlea 0x0(,%rax,4),%rbx\nimul %rax,%rax\nmov %rbx,-0x48(%rbp)\nmov %rsp,%rbx\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rbx\nand $0xfffffffffffffff0,%rdx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 137b \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 1366 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 1584 \nmov -0x48(%rbp),%rsi\nmov %rsp,%rbx\nmov %rsi,%rax\nshr $0x2,%rax\nmov %rax,-0x58(%rbp)\ntest %r14d,%r14d\njle 1543 \nlea -0x1(%r14),%eax\nxor %r13d,%r13d\nmov %r12,-0x68(%rbp)\nmov %rbx,%rdi\nmov %eax,-0x50(%rbp)\nlea 0x4(,%rax,4),%r15\nmov %r13d,%r12d\nmov %rbx,%r13\nmov %r15,%rbx\nmov %rsi,%r15\nnopl (%rax)\nmov %rbx,%rdx\nxor %esi,%esi\ncallq 10b0 \nmov %r12d,%edx\nadd $0x1,%r12d\nmov %rax,%rdi\nadd %r15,%rdi\ncmp %r12d,%r14d\njne 13d0 \nmov %r13,%rbx\nmov %r12d,%r13d\nmov -0x68(%rbp),%r12\nmov (%r12),%edi\ncmp $0x2,%edx\njbe 1574 \nmov %r14d,%esi\nmovd %edi,%xmm4\nxor %eax,%eax\nshr $0x2,%esi\npshufd $0x0,%xmm4,%xmm3\nshl $0x4,%rsi\nnopl 0x0(%rax,%rax,1)\nmovdqu (%r12,%rax,1),%xmm2\nmovdqa %xmm3,%xmm1\nmovdqa %xmm2,%xmm0\npaddd %xmm2,%xmm1\npcmpgtd %xmm3,%xmm0\npand %xmm0,%xmm1\npandn %xmm2,%xmm0\npor %xmm1,%xmm0\nmovups %xmm0,(%rbx,%rax,1)\nadd $0x10,%rax\ncmp %rsi,%rax\njne 1420 \nmov %r14d,%eax\nand $0xfffffffc,%eax\ntest $0x3,%r14b\nje 14a9 \nmovslq %eax,%r9\nmov (%r12,%r9,4),%esi\ncmp %edi,%esi\njle 1578 \nadd %edi,%esi\nmov %esi,(%rbx,%r9,4)\nlea 0x1(%rax),%esi\ncmp %edx,%eax\njge 158f \nmovslq %esi,%rdx\nmov (%r12,%rdx,4),%r9d\ncmp %edi,%r9d\nlea (%r9,%rdi,1),%esi\ncmovle %r9d,%esi\nadd $0x2,%eax\nmov %esi,(%rbx,%rdx,4)\ncmp %r13d,%eax\njge 14a9 \ncltq\nmov (%r12,%rax,4),%edx\nlea (%rdi,%rdx,1),%ecx\ncmp %edx,%edi\ncmovl %ecx,%edx\nmov %edx,(%rbx,%rax,4)\nmov -0x48(%rbp),%rax\nmov -0x50(%rbp),%r13d\nmov $0x1,%edi\nmov -0x58(%rbp),%r15\nlea (%rbx,%rax,1),%r11\nlea -0x2(%r14),%eax\nxor %r14d,%r14d\nlea 0x2(%rax),%r8\nmov %r8,-0x50(%rbp)\nnopl (%rax)\nmov %r14,%r8\nmovslq %r14d,%rcx\nmovslq %edi,%r10\nmov (%r12,%rdi,4),%r9d\nimul %r15,%rcx\nsub %rdi,%r8\nmov %r11,%rdx\nxor %eax,%eax\nimul %r15,%r8\nadd %rcx,%r10\nmov (%r12,%rax,4),%ecx\nmov (%rdx,%r8,4),%esi\ncmp %r9d,%ecx\njle 1501 \ncmp %edi,%eax\njg 1518 \nmov %esi,(%rdx)\nlea 0x1(%rax),%rcx\nadd $0x4,%rdx\ncmp %r13,%rax\nje 1531 \nmov %rcx,%rax\njmp 14f0 \nnopl (%rax)\nadd (%rbx,%r10,4),%ecx\ncmp %esi,%ecx\ncmovle %esi,%ecx\nadd $0x4,%rdx\nmov %ecx,-0x4(%rdx)\nlea 0x1(%rax),%rcx\ncmp %r13,%rax\njne 1510 \nadd $0x1,%r14\nadd $0x1,%rdi\nadd -0x48(%rbp),%r11\ncmp -0x50(%rbp),%rdi\njne 14d0 \nmovslq -0x5c(%rbp),%rax\nimul -0x58(%rbp),%rax\nmovslq -0x60(%rbp),%rdx\nadd %rdx,%rax\nmov (%rbx,%rax,4),%eax\nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\njne 159b \nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\nmov %edi,%esi\nxor %eax,%eax\nmovslq %eax,%r9\nmov %esi,(%rbx,%r9,4)\njmpq 1470 \norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 138d \ncmp $0x1,%r14d\njg 14a9 \njmp 1543 \ncallq 1090 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmovsxd rax, ecx\nmov rbp, rsp\npush r15\npush r14\npush r13\nmovsxd r13, esi\npush r12\nmov r12, rdi\nlea r14, ds:0[r13*4]\npush rbx\nsub rsp, 48h\nmov rcx, fs:28h\nmov [rbp+var_38], rcx\nxor ecx, ecx\nmov rcx, r13\nmov r8, rsp\nimul rcx, r13\nlea rcx, ds:0Fh[rcx*4]\nmov rdi, rcx\nand rcx, 0FFFFFFFFFFFFF000h\nsub r8, rcx\nand rdi, 0FFFFFFFFFFFFFFF0h\ncmp rsp, r8\njz short loc_1362\nloc_134D:\nsub rsp, 1000h\nor [rsp+1070h+var_78], 0\ncmp rsp, r8\njnz short loc_134D\nloc_1362:\nand edi, 0FFFh\nsub rsp, rdi\ntest rdi, rdi\njnz loc_158C\nloc_1374:\nmov r11, r14\nmov r10, rsp\nshr r11, 2\ntest esi, esi\njle loc_1560\nmov r15d, esi\nmov [rbp+var_50], r11\nmov rdi, r10; s\nmov [rbp+var_58], r10\nlea rcx, ds:0[r15*4]\nxor r15d, r15d\nmov [rbp+var_64], edx\nmov rbx, rcx\nmov [rbp+var_70], r10\nmov [rbp+var_48], r13\nmov r13d, r15d\nmov r15d, eax\nmov [rbp+var_60], r12\nmov r12d, esi\nnop word ptr [rax+rax+00h]\nloc_13C0:\nmov rdx, rbx; n\nxor esi, esi; c\ncall _memset\nmov r8d, r13d\nadd r13d, 1\nmov rdi, rax\nadd rdi, r14\ncmp r12d, r13d\njnz short loc_13C0\nmov esi, r12d\nmov r12, [rbp+var_60]\nmovsxd rax, r15d\nmov r11, [rbp+var_50]\nlea r9d, [rsi-1]\nmov r15d, r13d\nmov rbx, [rbp+var_58]\nmov edx, [rbp+var_64]\nmov r13, [rbp+var_48]\nmov r10, [rbp+var_70]\nmov edi, [r12]\ncmp r9d, 2\njbe loc_15A3\nmov ecx, esi\nmovd xmm4, edi\nxor r9d, r9d\nshr ecx, 2\npshufd xmm3, xmm4, 0\nshl rcx, 4\nnop dword ptr [rax+rax+00h]\nloc_1428:\nmovdqu xmm2, xmmword ptr [r12+r9]\nmovdqa xmm0, xmm2\nmovdqa xmm1, xmm2\npcmpgtd xmm0, xmm3\npaddd xmm1, xmm3\npand xmm1, xmm0\npandn xmm0, xmm2\npor xmm0, xmm1\nmovups xmmword ptr [r10+r9], xmm0\nadd r9, 10h\ncmp r9, rcx\njnz short loc_1428\nmov ecx, esi\nand ecx, 0FFFFFFFCh\nmov dword ptr [rbp+var_50], ecx\ntest sil, 3\njz short loc_14E0\nmovsxd r9, ecx\nlea rcx, ds:0[r9*4]\nmov r9d, [r12+r9*4]\nmov [rbp+var_48], rcx\ncmp r9d, edi\nlea ecx, [r9+rdi]\ncmovg r9d, ecx\nloc_1484:\nmov rcx, [rbp+var_48]\nadd rcx, r10\nmov [rcx], r9d\nmov r9d, dword ptr [rbp+var_50]\ncmp r8d, r9d\njle loc_1597\nmov r9, [rbp+var_48]\nmov r8d, [r12+r9+4]\ncmp edi, r8d\nlea r9d, [r8+rdi]\ncmovl r8d, r9d\nmov [rcx+4], r8d\nmov r8d, dword ptr [rbp+var_50]\nadd r8d, 2\ncmp r15d, r8d\njle short loc_14E0\nmov r9, [rbp+var_48]\nmov r9d, [r12+r9+8]\nlea r8d, [rdi+r9]\ncmp edi, r9d\nmov edi, r8d\ncmovge edi, r9d\nmov [rcx+8], edi\nnop word ptr [rax+rax+00h]\nloc_14E0:\nmov [rbp+var_48], r14\nlea r15d, [rsi-2]\nlea rdi, [r10+r14]\nmov ecx, eax\nmov dword ptr [rbp+var_50], edx\nadd r15, 2\nmov esi, 1\nnop word ptr [rax+rax+00h]\nloc_1500:\nlea edx, [rsi-1]\nmovsxd r8, esi\nmov r9d, [r12+rsi*4]\nxor eax, eax\nmovsxd rdx, edx\nimul rdx, r11\nadd r8, rdx\nnop word ptr [rax+rax+00000000h]\nloc_1520:\nmov r14d, [r12+rax*4]\nmov edx, [rbx+rax*4]\ncmp eax, esi\njle short loc_153B\ncmp r14d, r9d\njle short loc_153B\nadd r14d, [r10+r8*4]\ncmp edx, r14d\ncmovl edx, r14d\nloc_153B:\nmov [rdi+rax*4], edx\nadd rax, 1\ncmp r13, rax\njnz short loc_1520\nmov rax, [rbp+var_48]\nadd rsi, 1\nadd rdi, rax\nadd rbx, rax\ncmp rsi, r15\njnz short loc_1500\nmov edx, dword ptr [rbp+var_50]\nmovsxd rax, ecx\nloc_1560:\nmovsxd rdx, edx\nimul rdx, r11\nadd rax, rdx\nmov eax, [r10+rax*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_15BA\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_158C:\nor [rsp+rdi+1070h+var_1078], 0\njmp loc_1374\nloc_1597:\ncmp r15d, 1\njnz loc_14E0\njmp short loc_1560\nloc_15A3:\nmov dword ptr [rbp+var_50], 0\nmov r9d, edi\nmov [rbp+var_48], 0\njmp loc_1484\nloc_15BA:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(signed int *a1, int a2, int a3, int a4)\n{\n __int64 v4; // rax\n unsigned __int64 v6; // r14\n __int64 v7; // rdi\n _BYTE *v8; // r8\n __int16 v9; // di\n signed __int64 v10; // rdi\n void *v11; // rsp\n _BYTE *v12; // r10\n unsigned __int64 v13; // r11\n char *v14; // rdi\n int v15; // r13d\n char *v17; // rax\n int v18; // r8d\n signed int *v19; // r12\n int v20; // r15d\n _BYTE *v21; // rbx\n __int64 v22; // r13\n signed int v23; // edi\n __int64 v24; // r9\n __m128i v25; // xmm3\n __m128i v26; // xmm2\n __m128i v27; // xmm0\n signed int v28; // r9d\n _BYTE *v29; // rcx\n signed int v30; // r8d\n signed int v31; // r9d\n bool v32; // cc\n int v33; // edi\n _BYTE *v34; // rdi\n int v35; // ecx\n __int64 v36; // r15\n __int64 v37; // rsi\n signed int v38; // r9d\n __int64 v39; // rax\n signed int v40; // r14d\n int v41; // edx\n int v42; // r14d\n _BYTE v45[4088]; // [rsp+8h] [rbp-1070h] BYREF\n _BYTE *v46; // [rsp+1008h] [rbp-70h] BYREF\n int v47; // [rsp+1014h] [rbp-64h]\n signed int *v48; // [rsp+1018h] [rbp-60h]\n _BYTE *v49; // [rsp+1020h] [rbp-58h]\n unsigned __int64 v50; // [rsp+1028h] [rbp-50h]\n __int64 v51; // [rsp+1030h] [rbp-48h]\n unsigned __int64 v52; // [rsp+1040h] [rbp-38h]\n\n v4 = a4;\n v6 = 4LL * a2;\n v52 = __readfsqword(0x28u);\n v7 = 4 * a2 * (__int64)a2 + 15;\n v8 = (char *)&v46 - (v7 & 0xFFFFFFFFFFFFF000LL);\n v9 = v7 & 0xFFF0;\n if ( &v46 != (_BYTE **)v8 )\n {\n while ( v45 != v8 )\n ;\n }\n v10 = v9 & 0xFFF;\n v11 = alloca(v10);\n if ( v10 )\n *(_QWORD *)&v45[v10 - 8] = *(_QWORD *)&v45[v10 - 8];\n v12 = v45;\n v13 = v6 >> 2;\n if ( a2 > 0 )\n {\n v50 = v6 >> 2;\n v14 = v45;\n v49 = v45;\n v47 = a3;\n v46 = v45;\n v51 = a2;\n v15 = 0;\n v48 = a1;\n do\n {\n v17 = (char *)memset(v14, 0, 4LL * (unsigned int)a2);\n v18 = v15++;\n v14 = &v17[v6];\n }\n while ( a2 != v15 );\n v19 = v48;\n v4 = a4;\n v13 = v50;\n v20 = v15;\n v21 = v49;\n a3 = v47;\n v22 = v51;\n v12 = v46;\n v23 = *v48;\n if ( (unsigned int)(a2 - 1) <= 2 )\n {\n LODWORD(v50) = 0;\n v28 = v23;\n v51 = 0LL;\n }\n else\n {\n v24 = 0LL;\n v25 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v23), 0);\n do\n {\n v26 = _mm_loadu_si128((const __m128i *)&v19[v24]);\n v27 = _mm_cmpgt_epi32(v26, v25);\n *(__m128i *)&v12[v24 * 4] = _mm_or_si128(\n _mm_andnot_si128(v27, v26),\n _mm_and_si128(_mm_add_epi32(v26, v25), v27));\n v24 += 4LL;\n }\n while ( v24 != 4LL * ((unsigned int)a2 >> 2) );\n LODWORD(v50) = a2 & 0xFFFFFFFC;\n if ( (a2 & 3) == 0 )\n {\nLABEL_21:\n v51 = 4LL * a2;\n v34 = &v12[v6];\n v35 = v4;\n LODWORD(v50) = a3;\n v36 = (unsigned int)(a2 - 2) + 2LL;\n v37 = 1LL;\n do\n {\n v38 = v19[v37];\n v39 = 0LL;\n do\n {\n v40 = v19[v39];\n v41 = *(_DWORD *)&v21[4 * v39];\n if ( (int)v39 > (int)v37 && v40 > v38 )\n {\n v42 = *(_DWORD *)&v12[4 * v13 * ((int)v37 - 1) + 4 * (int)v37] + v40;\n if ( v41 < v42 )\n v41 = v42;\n }\n *(_DWORD *)&v34[4 * v39++] = v41;\n }\n while ( v22 != v39 );\n ++v37;\n v34 += v51;\n v21 += v51;\n }\n while ( v37 != v36 );\n a3 = v50;\n v4 = v35;\n return *(unsigned int *)&v12[4 * v13 * a3 + 4 * v4];\n }\n v28 = v19[a2 & 0x7FFFFFFC];\n v51 = 4LL * (a2 & 0x7FFFFFFC);\n if ( v28 > v23 )\n v28 += v23;\n }\n v29 = &v12[v51];\n *(_DWORD *)&v12[v51] = v28;\n if ( v18 <= (int)v50 )\n {\n if ( v20 == 1 )\n return *(unsigned int *)&v12[4 * v13 * a3 + 4 * v4];\n }\n else\n {\n v30 = *(signed int *)((char *)v19 + v51 + 4);\n if ( v23 < v30 )\n v30 += v23;\n *((_DWORD *)v29 + 1) = v30;\n if ( v20 > (int)v50 + 2 )\n {\n v31 = *(signed int *)((char *)v19 + v51 + 8);\n v32 = v23 < v31;\n v33 = v23 + v31;\n if ( !v32 )\n v33 = *(signed int *)((char *)v19 + v51 + 8);\n *((_DWORD *)v29 + 2) = v33;\n }\n }\n goto LABEL_21;\n }\n return *(unsigned int *)&v12[4 * v13 * a3 + 4 * v4];\n}", + "ida_strip_asm": "sub_12F0:\nendbr64\npush rbp\nmovsxd rax, ecx\nmov rbp, rsp\npush r15\npush r14\npush r13\nmovsxd r13, esi\npush r12\nmov r12, rdi\nlea r14, ds:0[r13*4]\npush rbx\nsub rsp, 48h\nmov rcx, fs:28h\nmov [rbp+var_38], rcx\nxor ecx, ecx\nmov rcx, r13\nmov r8, rsp\nimul rcx, r13\nlea rcx, ds:0Fh[rcx*4]\nmov rdi, rcx\nand rcx, 0FFFFFFFFFFFFF000h\nsub r8, rcx\nand rdi, 0FFFFFFFFFFFFFFF0h\ncmp rsp, r8\njz short loc_1362\nloc_134D:\nsub rsp, 1000h\nor [rsp+1070h+var_78], 0\ncmp rsp, r8\njnz short loc_134D\nloc_1362:\nand edi, 0FFFh\nsub rsp, rdi\ntest rdi, rdi\njnz loc_158C\nloc_1374:\nmov r11, r14\nmov r10, rsp\nshr r11, 2\ntest esi, esi\njle loc_1560\nmov r15d, esi\nmov [rbp+var_50], r11\nmov rdi, r10; s\nmov [rbp+var_58], r10\nlea rcx, ds:0[r15*4]\nxor r15d, r15d\nmov [rbp+var_64], edx\nmov rbx, rcx\nmov [rbp+var_70], r10\nmov [rbp+var_48], r13\nmov r13d, r15d\nmov r15d, eax\nmov [rbp+var_60], r12\nmov r12d, esi\nnop word ptr [rax+rax+00h]\nloc_13C0:\nmov rdx, rbx; n\nxor esi, esi; c\ncall _memset\nmov r8d, r13d\nadd r13d, 1\nmov rdi, rax\nadd rdi, r14\ncmp r12d, r13d\njnz short loc_13C0\nmov esi, r12d\nmov r12, [rbp+var_60]\nmovsxd rax, r15d\nmov r11, [rbp+var_50]\nlea r9d, [rsi-1]\nmov r15d, r13d\nmov rbx, [rbp+var_58]\nmov edx, [rbp+var_64]\nmov r13, [rbp+var_48]\nmov r10, [rbp+var_70]\nmov edi, [r12]\ncmp r9d, 2\njbe loc_15A3\nmov ecx, esi\nmovd xmm4, edi\nxor r9d, r9d\nshr ecx, 2\npshufd xmm3, xmm4, 0\nshl rcx, 4\nnop dword ptr [rax+rax+00h]\nloc_1428:\nmovdqu xmm2, xmmword ptr [r12+r9]\nmovdqa xmm0, xmm2\nmovdqa xmm1, xmm2\npcmpgtd xmm0, xmm3\npaddd xmm1, xmm3\npand xmm1, xmm0\npandn xmm0, xmm2\npor xmm0, xmm1\nmovups xmmword ptr [r10+r9], xmm0\nadd r9, 10h\ncmp r9, rcx\njnz short loc_1428\nmov ecx, esi\nand ecx, 0FFFFFFFCh\nmov dword ptr [rbp+var_50], ecx\ntest sil, 3\njz short loc_14E0\nmovsxd r9, ecx\nlea rcx, ds:0[r9*4]\nmov r9d, [r12+r9*4]\nmov [rbp+var_48], rcx\ncmp r9d, edi\nlea ecx, [r9+rdi]\ncmovg r9d, ecx\nloc_1484:\nmov rcx, [rbp+var_48]\nadd rcx, r10\nmov [rcx], r9d\nmov r9d, dword ptr [rbp+var_50]\ncmp r8d, r9d\njle loc_1597\nmov r9, [rbp+var_48]\nmov r8d, [r12+r9+4]\ncmp edi, r8d\nlea r9d, [r8+rdi]\ncmovl r8d, r9d\nmov [rcx+4], r8d\nmov r8d, dword ptr [rbp+var_50]\nadd r8d, 2\ncmp r15d, r8d\njle short loc_14E0\nmov r9, [rbp+var_48]\nmov r9d, [r12+r9+8]\nlea r8d, [rdi+r9]\ncmp edi, r9d\nmov edi, r8d\ncmovge edi, r9d\nmov [rcx+8], edi\nnop word ptr [rax+rax+00h]\nloc_14E0:\nmov [rbp+var_48], r14\nlea r15d, [rsi-2]\nlea rdi, [r10+r14]\nmov ecx, eax\nmov dword ptr [rbp+var_50], edx\nadd r15, 2\nmov esi, 1\nnop word ptr [rax+rax+00h]\nloc_1500:\nlea edx, [rsi-1]\nmovsxd r8, esi\nmov r9d, [r12+rsi*4]\nxor eax, eax\nmovsxd rdx, edx\nimul rdx, r11\nadd r8, rdx\nnop word ptr [rax+rax+00000000h]\nloc_1520:\nmov r14d, [r12+rax*4]\nmov edx, [rbx+rax*4]\ncmp eax, esi\njle short loc_153B\ncmp r14d, r9d\njle short loc_153B\nadd r14d, [r10+r8*4]\ncmp edx, r14d\ncmovl edx, r14d\nloc_153B:\nmov [rdi+rax*4], edx\nadd rax, 1\ncmp r13, rax\njnz short loc_1520\nmov rax, [rbp+var_48]\nadd rsi, 1\nadd rdi, rax\nadd rbx, rax\ncmp rsi, r15\njnz short loc_1500\nmov edx, dword ptr [rbp+var_50]\nmovsxd rax, ecx\nloc_1560:\nmovsxd rdx, edx\nimul rdx, r11\nadd rax, rdx\nmov eax, [r10+rax*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_15BA\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_158C:\nor [rsp+rdi+1070h+var_1078], 0\njmp loc_1374\nloc_1597:\ncmp r15d, 1\njnz loc_14E0\njmp short loc_1560\nloc_15A3:\nmov dword ptr [rbp+var_50], 0\nmov r9d, edi\nmov [rbp+var_48], 0\njmp loc_1484\nloc_15BA:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12F0(signed int *a1, int a2, int a3, int a4)\n{\n __int64 v4; // rax\n unsigned __int64 v6; // r14\n __int64 v7; // rdi\n _BYTE *v8; // r8\n __int16 v9; // di\n signed __int64 v10; // rdi\n void *v11; // rsp\n _BYTE *v12; // r10\n unsigned __int64 v13; // r11\n char *v14; // rdi\n int v15; // r13d\n char *v17; // rax\n int v18; // r8d\n signed int *v19; // r12\n int v20; // r15d\n _BYTE *v21; // rbx\n __int64 v22; // r13\n signed int v23; // edi\n __int64 v24; // r9\n __m128i v25; // xmm3\n __m128i v26; // xmm2\n __m128i v27; // xmm0\n signed int v28; // r9d\n _BYTE *v29; // rcx\n signed int v30; // r8d\n signed int v31; // r9d\n bool v32; // cc\n int v33; // edi\n _BYTE *v34; // rdi\n int v35; // ecx\n __int64 v36; // r15\n __int64 v37; // rsi\n signed int v38; // r9d\n __int64 v39; // rax\n signed int v40; // r14d\n int v41; // edx\n int v42; // r14d\n _BYTE v45[4088]; // [rsp+8h] [rbp-1070h] BYREF\n _BYTE *v46; // [rsp+1008h] [rbp-70h] BYREF\n int v47; // [rsp+1014h] [rbp-64h]\n signed int *v48; // [rsp+1018h] [rbp-60h]\n _BYTE *v49; // [rsp+1020h] [rbp-58h]\n unsigned __int64 v50; // [rsp+1028h] [rbp-50h]\n __int64 v51; // [rsp+1030h] [rbp-48h]\n unsigned __int64 v52; // [rsp+1040h] [rbp-38h]\n\n v4 = a4;\n v6 = 4LL * a2;\n v52 = __readfsqword(0x28u);\n v7 = 4 * a2 * (__int64)a2 + 15;\n v8 = (char *)&v46 - (v7 & 0xFFFFFFFFFFFFF000LL);\n v9 = v7 & 0xFFF0;\n if ( &v46 != (_BYTE **)v8 )\n {\n while ( v45 != v8 )\n ;\n }\n v10 = v9 & 0xFFF;\n v11 = alloca(v10);\n if ( v10 )\n *(_QWORD *)&v45[v10 - 8] = *(_QWORD *)&v45[v10 - 8];\n v12 = v45;\n v13 = v6 >> 2;\n if ( a2 > 0 )\n {\n v50 = v6 >> 2;\n v14 = v45;\n v49 = v45;\n v47 = a3;\n v46 = v45;\n v51 = a2;\n v15 = 0;\n v48 = a1;\n do\n {\n v17 = (char *)memset(v14, 0, 4LL * (unsigned int)a2);\n v18 = v15++;\n v14 = &v17[v6];\n }\n while ( a2 != v15 );\n v19 = v48;\n v4 = a4;\n v13 = v50;\n v20 = v15;\n v21 = v49;\n a3 = v47;\n v22 = v51;\n v12 = v46;\n v23 = *v48;\n if ( (unsigned int)(a2 - 1) <= 2 )\n {\n LODWORD(v50) = 0;\n v28 = v23;\n v51 = 0LL;\n }\n else\n {\n v24 = 0LL;\n v25 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v23), 0);\n do\n {\n v26 = _mm_loadu_si128((const __m128i *)&v19[v24]);\n v27 = _mm_cmpgt_epi32(v26, v25);\n *(__m128i *)&v12[v24 * 4] = _mm_or_si128(\n _mm_andnot_si128(v27, v26),\n _mm_and_si128(_mm_add_epi32(v26, v25), v27));\n v24 += 4LL;\n }\n while ( v24 != 4LL * ((unsigned int)a2 >> 2) );\n LODWORD(v50) = a2 & 0xFFFFFFFC;\n if ( (a2 & 3) == 0 )\n {\nLABEL_21:\n v51 = 4LL * a2;\n v34 = &v12[v6];\n v35 = v4;\n LODWORD(v50) = a3;\n v36 = (unsigned int)(a2 - 2) + 2LL;\n v37 = 1LL;\n do\n {\n v38 = v19[v37];\n v39 = 0LL;\n do\n {\n v40 = v19[v39];\n v41 = *(_DWORD *)&v21[4 * v39];\n if ( (int)v39 > (int)v37 && v40 > v38 )\n {\n v42 = *(_DWORD *)&v12[4 * v13 * ((int)v37 - 1) + 4 * (int)v37] + v40;\n if ( v41 < v42 )\n v41 = v42;\n }\n *(_DWORD *)&v34[4 * v39++] = v41;\n }\n while ( v22 != v39 );\n ++v37;\n v34 += v51;\n v21 += v51;\n }\n while ( v37 != v36 );\n a3 = v50;\n v4 = v35;\n return *(unsigned int *)&v12[4 * v13 * a3 + 4 * v4];\n }\n v28 = v19[a2 & 0x7FFFFFFC];\n v51 = 4LL * (a2 & 0x7FFFFFFC);\n if ( v28 > v23 )\n v28 += v23;\n }\n v29 = &v12[v51];\n *(_DWORD *)&v12[v51] = v28;\n if ( v18 <= (int)v50 )\n {\n if ( v20 == 1 )\n return *(unsigned int *)&v12[4 * v13 * a3 + 4 * v4];\n }\n else\n {\n v30 = *(signed int *)((char *)v19 + v51 + 4);\n if ( v23 < v30 )\n v30 += v23;\n *((_DWORD *)v29 + 1) = v30;\n if ( v20 > (int)v50 + 2 )\n {\n v31 = *(signed int *)((char *)v19 + v51 + 8);\n v32 = v23 < v31;\n v33 = v23 + v31;\n if ( !v32 )\n v33 = *(signed int *)((char *)v19 + v51 + 8);\n *((_DWORD *)v29 + 2) = v33;\n }\n }\n goto LABEL_21;\n }\n return *(unsigned int *)&v12[4 * v13 * a3 + 4 * v4];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12F0(signed int *a1, int a2, int a3, int a4) {\n long long v4;\n unsigned long long v6;\n long long v7;\n uint8_t *v8;\n short v9;\n signed long long v10;\n void *v11;\n uint8_t *v12;\n unsigned long long v13;\n char *v14;\n int v15;\n char *v17;\n int v18;\n signed int *v19;\n int v20;\n uint8_t *v21;\n long long v22;\n signed int v23;\n long long v24;\n __m128i v25;\n __m128i v26;\n __m128i v27;\n signed int v28;\n uint8_t *v29;\n signed int v30;\n signed int v31;\n bool v32;\n int v33;\n uint8_t *v34;\n int v35;\n long long v36;\n long long v37;\n signed int v38;\n long long v39;\n signed int v40;\n int v41;\n int v42;\n uint8_t v45[4088];\n uint8_t *v46;\n int v47;\n signed int *v48;\n uint8_t *v49;\n unsigned long long v50;\n long long v51;\n unsigned long long v52;\n v4 = a4;\n v6 = 4LL * a2;\n v52 = __readfsqword(40u);\n v7 = 4 * a2 * (long long)a2 + 15;\n v8 = (char *)&v46 - (v7 & 18446744073709547520LL);\n v9 = v7 & 65520;\n if (&v46 != (uint8_t **)v8) {\n while (v45 != v8)\n ;\n }\n v10 = v9 & 4095;\n v11 = alloca(v10);\n if (v10) *(uint64_t *)&v45[v10 - 8] = *(uint64_t *)&v45[v10 - 8];\n v12 = v45;\n v13 = v6 >> 2;\n if (a2 > 0) {\n v50 = v6 >> 2;\n v14 = v45;\n v49 = v45;\n v47 = a3;\n v46 = v45;\n v51 = a2;\n v15 = 0;\n v48 = a1;\n do {\n v17 = (char *)memset(v14, 0, 4LL * (unsigned int)a2);\n v18 = v15++;\n v14 = &v17[v6];\n } while (a2 != v15);\n v19 = v48;\n v4 = a4;\n v13 = v50;\n v20 = v15;\n v21 = v49;\n a3 = v47;\n v22 = v51;\n v12 = v46;\n v23 = *v48;\n if ((unsigned int)(a2 - 1) <= 2) {\n LODWORD(v50) = 0;\n v28 = v23;\n v51 = 0LL;\n } else {\n v24 = 0LL;\n v25 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v23), 0);\n do {\n v26 = _mm_loadu_si128((const __m128i *)&v19[v24]);\n v27 = _mm_cmpgt_epi32(v26, v25);\n *(__m128i *)&v12[v24 * 4] =\n _mm_or_si128(_mm_andnot_si128(v27, v26),\n _mm_and_si128(_mm_add_epi32(v26, v25), v27));\n v24 += 4LL;\n } while (v24 != 4LL * ((unsigned int)a2 >> 2));\n LODWORD(v50) = a2 & 4294967292;\n if ((a2 & 3) == 0) {\n LABEL_21:\n v51 = 4LL * a2;\n v34 = &v12[v6];\n v35 = v4;\n LODWORD(v50) = a3;\n v36 = (unsigned int)(a2 - 2) + 2LL;\n v37 = 1LL;\n do {\n v38 = v19[v37];\n v39 = 0LL;\n do {\n v40 = v19[v39];\n v41 = *(uint32_t *)&v21[4 * v39];\n if ((int)v39 > (int)v37 && v40 > v38) {\n v42 = *(uint32_t *)&v12[4 * v13 * ((int)v37 - 1) + 4 * (int)v37] +\n v40;\n if (v41 < v42) v41 = v42;\n }\n *(uint32_t *)&v34[4 * v39++] = v41;\n } while (v22 != v39);\n ++v37;\n v34 += v51;\n v21 += v51;\n } while (v37 != v36);\n a3 = v50;\n v4 = v35;\n return *(unsigned int *)&v12[4 * v13 * a3 + 4 * v4];\n }\n v28 = v19[a2 & 2147483644];\n v51 = 4LL * (a2 & 2147483644);\n if (v28 > v23) v28 += v23;\n }\n v29 = &v12[v51];\n *(uint32_t *)&v12[v51] = v28;\n if (v18 <= (int)v50) {\n if (v20 == 1) return *(unsigned int *)&v12[4 * v13 * a3 + 4 * v4];\n } else {\n v30 = *(signed int *)((char *)v19 + v51 + 4);\n if (v23 < v30) v30 += v23;\n *((uint32_t *)v29 + 1) = v30;\n if (v20 > (int)v50 + 2) {\n v31 = *(signed int *)((char *)v19 + v51 + 8);\n v32 = v23 < v31;\n v33 = v23 + v31;\n if (!v32) v33 = *(signed int *)((char *)v19 + v51 + 8);\n *((uint32_t *)v29 + 2) = v33;\n }\n }\n goto LABEL_21;\n }\n return *(unsigned int *)&v12[4 * v13 * a3 + 4 * v4];\n}", + "ida_pseudo_norm": "long long func0(signed int *a1, int a2, int a3, int a4) {\n long long v4;\n unsigned long long v6;\n long long v7;\n uint8_t *v8;\n short v9;\n signed long long v10;\n void *v11;\n uint8_t *v12;\n unsigned long long v13;\n char *v14;\n int v15;\n char *v17;\n int v18;\n signed int *v19;\n int v20;\n uint8_t *v21;\n long long v22;\n signed int v23;\n long long v24;\n __m128i v25;\n __m128i v26;\n __m128i v27;\n signed int v28;\n uint8_t *v29;\n signed int v30;\n signed int v31;\n bool v32;\n int v33;\n uint8_t *v34;\n int v35;\n long long v36;\n long long v37;\n signed int v38;\n long long v39;\n signed int v40;\n int v41;\n int v42;\n uint8_t v45[4088];\n uint8_t *v46;\n int v47;\n signed int *v48;\n uint8_t *v49;\n unsigned long long v50;\n long long v51;\n unsigned long long v52;\n v4 = a4;\n v6 = 4LL * a2;\n v52 = __readfsqword(40u);\n v7 = 4 * a2 * (long long)a2 + 15;\n v8 = (char *)&v46 - (v7 & 18446744073709547520LL);\n v9 = v7 & 65520;\n if (&v46 != (uint8_t **)v8) {\n while (v45 != v8)\n ;\n }\n v10 = v9 & 4095;\n v11 = alloca(v10);\n if (v10) *(uint64_t *)&v45[v10 - 8] = *(uint64_t *)&v45[v10 - 8];\n v12 = v45;\n v13 = v6 >> 2;\n if (a2 > 0) {\n v50 = v6 >> 2;\n v14 = v45;\n v49 = v45;\n v47 = a3;\n v46 = v45;\n v51 = a2;\n v15 = 0;\n v48 = a1;\n do {\n v17 = (char *)memset(v14, 0, 4LL * (unsigned int)a2);\n v18 = v15++;\n v14 = &v17[v6];\n } while (a2 != v15);\n v19 = v48;\n v4 = a4;\n v13 = v50;\n v20 = v15;\n v21 = v49;\n a3 = v47;\n v22 = v51;\n v12 = v46;\n v23 = *v48;\n if ((unsigned int)(a2 - 1) <= 2) {\n LODWORD(v50) = 0;\n v28 = v23;\n v51 = 0LL;\n } else {\n v24 = 0LL;\n v25 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v23), 0);\n do {\n v26 = _mm_loadu_si128((const __m128i *)&v19[v24]);\n v27 = _mm_cmpgt_epi32(v26, v25);\n *(__m128i *)&v12[v24 * 4] =\n _mm_or_si128(_mm_andnot_si128(v27, v26),\n _mm_and_si128(_mm_add_epi32(v26, v25), v27));\n v24 += 4LL;\n } while (v24 != 4LL * ((unsigned int)a2 >> 2));\n LODWORD(v50) = a2 & 4294967292;\n if ((a2 & 3) == 0) {\n LABEL_21:\n v51 = 4LL * a2;\n v34 = &v12[v6];\n v35 = v4;\n LODWORD(v50) = a3;\n v36 = (unsigned int)(a2 - 2) + 2LL;\n v37 = 1LL;\n do {\n v38 = v19[v37];\n v39 = 0LL;\n do {\n v40 = v19[v39];\n v41 = *(uint32_t *)&v21[4 * v39];\n if ((int)v39 > (int)v37 && v40 > v38) {\n v42 = *(uint32_t *)&v12[4 * v13 * ((int)v37 - 1) + 4 * (int)v37] +\n v40;\n if (v41 < v42) v41 = v42;\n }\n *(uint32_t *)&v34[4 * v39++] = v41;\n } while (v22 != v39);\n ++v37;\n v34 += v51;\n v21 += v51;\n } while (v37 != v36);\n a3 = v50;\n v4 = v35;\n return *(unsigned int *)&v12[4 * v13 * a3 + 4 * v4];\n }\n v28 = v19[a2 & 2147483644];\n v51 = 4LL * (a2 & 2147483644);\n if (v28 > v23) v28 += v23;\n }\n v29 = &v12[v51];\n *(uint32_t *)&v12[v51] = v28;\n if (v18 <= (int)v50) {\n if (v20 == 1) return *(unsigned int *)&v12[4 * v13 * a3 + 4 * v4];\n } else {\n v30 = *(signed int *)((char *)v19 + v51 + 4);\n if (v23 < v30) v30 += v23;\n *((uint32_t *)v29 + 1) = v30;\n if (v20 > (int)v50 + 2) {\n v31 = *(signed int *)((char *)v19 + v51 + 8);\n v32 = v23 < v31;\n v33 = v23 + v31;\n if (!v32) v33 = *(signed int *)((char *)v19 + v51 + 8);\n *((uint32_t *)v29 + 2) = v33;\n }\n }\n goto LABEL_21;\n }\n return *(unsigned int *)&v12[4 * v13 * a3 + 4 * v4];\n}" + }, + { + "index": 307, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char *str;\n\n int num;\n\n int *array;\n\n int array_size;\n\n int boolean;\n\n} Tuple;\n\n\n\n", + "func": "Tuple func0(Tuple tuplex, int m, int n) {\n Tuple tuplex_colon;\n tuplex_colon.str = strdup(tuplex.str);\n tuplex_colon.num = tuplex.num;\n tuplex_colon.array = (int *)malloc(sizeof(int) * (tuplex.array_size + 1));\n for (int i = 0; i < tuplex.array_size; i++) {\n tuplex_colon.array[i] = tuplex.array[i];\n }\n tuplex_colon.array[tuplex.array_size] = n;\n tuplex_colon.array_size = tuplex.array_size + 1;\n tuplex_colon.boolean = tuplex.boolean;\n return tuplex_colon;\n}", + "test": "int main() {\n\n Tuple tup1 = {\"HELLO\", 5, NULL, 0, 1};\n\n Tuple result;\n\n\n\n result = func0(tup1, 2, 50);\n\n assert(strcmp(result.str, \"HELLO\") == 0 && result.num == 5 && result.array[0] == 50 && result.boolean == 1);\n\n\n\n result = func0(tup1, 2, 100);\n\n assert(strcmp(result.str, \"HELLO\") == 0 && result.num == 5 && result.array[0] == 100 && result.boolean == 1);\n\n\n\n result = func0(tup1, 2, 500);\n\n assert(strcmp(result.str, \"HELLO\") == 0 && result.num == 5 && result.array[0] == 500 && result.boolean == 1);\n\n\n\n free(result.str);\n\n free(result.array);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x40,%rsp\nmov %rdi,-0x38(%rbp)\nmov %esi,-0x3c(%rbp)\nmov %edx,-0x40(%rbp)\nmov 0x10(%rbp),%rax\nmov %rax,%rdi\ncallq 10f0 \nmov %rax,-0x20(%rbp)\nmov 0x18(%rbp),%eax\nmov %eax,-0x18(%rbp)\nmov 0x28(%rbp),%eax\nadd $0x1,%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10e0 \nmov %rax,-0x10(%rbp)\nmovl $0x0,-0x24(%rbp)\njmp 1260 \nmov 0x20(%rbp),%rax\nmov -0x24(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x2,%rdx\nadd %rdx,%rax\nmov -0x10(%rbp),%rdx\nmov -0x24(%rbp),%ecx\nmovslq %ecx,%rcx\nshl $0x2,%rcx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x24(%rbp)\nmov 0x28(%rbp),%eax\ncmp %eax,-0x24(%rbp)\njl 1236 \nmov -0x10(%rbp),%rax\nmov 0x28(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x2,%rdx\nadd %rax,%rdx\nmov -0x40(%rbp),%eax\nmov %eax,(%rdx)\nmov 0x28(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x8(%rbp)\nmov 0x2c(%rbp),%eax\nmov %eax,-0x4(%rbp)\nmov -0x38(%rbp),%rcx\nmov -0x20(%rbp),%rax\nmov -0x18(%rbp),%rdx\nmov %rax,(%rcx)\nmov %rdx,0x8(%rcx)\nmov -0x10(%rbp),%rax\nmov -0x8(%rbp),%rdx\nmov %rax,0x10(%rcx)\nmov %rdx,0x18(%rcx)\nmov -0x38(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov [rbp+var_40], edx\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strdup\nmov [rbp+var_20], rax\nmov eax, [rbp+arg_8]\nmov dword ptr [rbp+var_18], eax\nmov eax, dword ptr [rbp+arg_18]\nadd eax, 1\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_10], rax\nmov [rbp+var_24], 0\njmp short loc_1260\nloc_1236:\nmov rax, [rbp+arg_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov rdx, [rbp+var_10]\nmov ecx, [rbp+var_24]\nmovsxd rcx, ecx\nshl rcx, 2\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_24], 1\nloc_1260:\nmov eax, dword ptr [rbp+arg_18]\ncmp [rbp+var_24], eax\njl short loc_1236\nmov rax, [rbp+var_10]\nmov edx, dword ptr [rbp+arg_18]\nmovsxd rdx, edx\nshl rdx, 2\nadd rdx, rax\nmov eax, [rbp+var_40]\nmov [rdx], eax\nmov eax, dword ptr [rbp+arg_18]\nadd eax, 1\nmov dword ptr [rbp+var_8], eax\nmov eax, dword ptr [rbp+arg_18+4]\nmov dword ptr [rbp+var_8+4], eax\nmov rcx, [rbp+var_38]\nmov rax, [rbp+var_20]\nmov rdx, [rbp+var_18]\nmov [rcx], rax\nmov [rcx+8], rdx\nmov rax, [rbp+var_10]\nmov rdx, [rbp+var_8]\nmov [rcx+10h], rax\nmov [rcx+18h], rdx\nmov rax, [rbp+var_38]\nleave\nretn", + "ida_pseudo": "char **__fastcall func0(char **a1, int a2, int a3, int a4, int a5, int a6, char *s, int a8, __int64 a9, __int64 a10)\n{\n int i; // [rsp+1Ch] [rbp-24h]\n char *v13; // [rsp+20h] [rbp-20h]\n char *v14; // [rsp+28h] [rbp-18h]\n char *v15; // [rsp+30h] [rbp-10h]\n char *v16; // [rsp+38h] [rbp-8h]\n\n v13 = strdup(s);\n LODWORD(v14) = a8;\n v15 = (char *)malloc(4LL * ((int)a10 + 1));\n for ( i = 0; i < (int)a10; ++i )\n *(_DWORD *)&v15[4 * i] = *(_DWORD *)(4LL * i + a9);\n *(_DWORD *)&v15[4 * (int)a10] = a3;\n LODWORD(v16) = a10 + 1;\n HIDWORD(v16) = HIDWORD(a10);\n *a1 = v13;\n a1[1] = v14;\n a1[2] = v15;\n a1[3] = v16;\n return a1;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov [rbp+var_40], edx\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strdup\nmov [rbp+var_20], rax\nmov eax, [rbp+arg_8]\nmov dword ptr [rbp+var_18], eax\nmov eax, dword ptr [rbp+arg_18]\nadd eax, 1\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_10], rax\nmov [rbp+var_24], 0\njmp short loc_1260\nloc_1236:\nmov rax, [rbp+arg_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov rdx, [rbp+var_10]\nmov ecx, [rbp+var_24]\nmovsxd rcx, ecx\nshl rcx, 2\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_24], 1\nloc_1260:\nmov eax, dword ptr [rbp+arg_18]\ncmp [rbp+var_24], eax\njl short loc_1236\nmov rax, [rbp+var_10]\nmov edx, dword ptr [rbp+arg_18]\nmovsxd rdx, edx\nshl rdx, 2\nadd rdx, rax\nmov eax, [rbp+var_40]\nmov [rdx], eax\nmov eax, dword ptr [rbp+arg_18]\nadd eax, 1\nmov dword ptr [rbp+var_8], eax\nmov eax, dword ptr [rbp+arg_18+4]\nmov dword ptr [rbp+var_8+4], eax\nmov rcx, [rbp+var_38]\nmov rax, [rbp+var_20]\nmov rdx, [rbp+var_18]\nmov [rcx], rax\nmov [rcx+8], rdx\nmov rax, [rbp+var_10]\nmov rdx, [rbp+var_8]\nmov [rcx+10h], rax\nmov [rcx+18h], rdx\nmov rax, [rbp+var_38]\nleave\nretn", + "ida_strip_pseudo": "char **__fastcall sub_11E9(char **a1, int a2, int a3, int a4, int a5, int a6, char *s, int a8, __int64 a9, __int64 a10)\n{\n int i; // [rsp+1Ch] [rbp-24h]\n char *v13; // [rsp+20h] [rbp-20h]\n char *v14; // [rsp+28h] [rbp-18h]\n char *v15; // [rsp+30h] [rbp-10h]\n char *v16; // [rsp+38h] [rbp-8h]\n\n v13 = strdup(s);\n LODWORD(v14) = a8;\n v15 = (char *)malloc(4LL * ((int)a10 + 1));\n for ( i = 0; i < (int)a10; ++i )\n *(_DWORD *)&v15[4 * i] = *(_DWORD *)(4LL * i + a9);\n *(_DWORD *)&v15[4 * (int)a10] = a3;\n LODWORD(v16) = a10 + 1;\n HIDWORD(v16) = HIDWORD(a10);\n *a1 = v13;\n a1[1] = v14;\n a1[2] = v15;\n a1[3] = v16;\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char **sub_11E9(char **a1, int a2, int a3, int a4, int a5, int a6, char *s,\n int a8, long long a9, long long a10) {\n int i;\n char *v13;\n char *v14;\n char *v15;\n char *v16;\n v13 = strdup(s);\n LODWORD(v14) = a8;\n v15 = (char *)malloc(4LL * ((int)a10 + 1));\n for (i = 0; i < (int)a10; ++i)\n *(uint32_t *)&v15[4 * i] = *(uint32_t *)(4LL * i + a9);\n *(uint32_t *)&v15[4 * (int)a10] = a3;\n LODWORD(v16) = a10 + 1;\n HIDWORD(v16) = HIDWORD(a10);\n *a1 = v13;\n a1[1] = v14;\n a1[2] = v15;\n a1[3] = v16;\n return a1;\n}", + "ida_pseudo_norm": "char **func0(char **a1, int a2, int a3, int a4, int a5, int a6, char *s, int a8,\n long long a9, long long a10) {\n int i;\n char *v13;\n char *v14;\n char *v15;\n char *v16;\n v13 = strdup(s);\n LODWORD(v14) = a8;\n v15 = (char *)malloc(4LL * ((int)a10 + 1));\n for (i = 0; i < (int)a10; ++i)\n *(uint32_t *)&v15[4 * i] = *(uint32_t *)(4LL * i + a9);\n *(uint32_t *)&v15[4 * (int)a10] = a3;\n LODWORD(v16) = a10 + 1;\n HIDWORD(v16) = HIDWORD(a10);\n *a1 = v13;\n a1[1] = v14;\n a1[2] = v15;\n a1[3] = v16;\n return a1;\n}" + }, + { + "index": 307, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char *str;\n\n int num;\n\n int *array;\n\n int array_size;\n\n int boolean;\n\n} Tuple;\n\n\n\n", + "func": "Tuple func0(Tuple tuplex, int m, int n) {\n Tuple tuplex_colon;\n tuplex_colon.str = strdup(tuplex.str);\n tuplex_colon.num = tuplex.num;\n tuplex_colon.array = (int *)malloc(sizeof(int) * (tuplex.array_size + 1));\n for (int i = 0; i < tuplex.array_size; i++) {\n tuplex_colon.array[i] = tuplex.array[i];\n }\n tuplex_colon.array[tuplex.array_size] = n;\n tuplex_colon.array_size = tuplex.array_size + 1;\n tuplex_colon.boolean = tuplex.boolean;\n return tuplex_colon;\n}", + "test": "int main() {\n\n Tuple tup1 = {\"HELLO\", 5, NULL, 0, 1};\n\n Tuple result;\n\n\n\n result = func0(tup1, 2, 50);\n\n assert(strcmp(result.str, \"HELLO\") == 0 && result.num == 5 && result.array[0] == 50 && result.boolean == 1);\n\n\n\n result = func0(tup1, 2, 100);\n\n assert(strcmp(result.str, \"HELLO\") == 0 && result.num == 5 && result.array[0] == 100 && result.boolean == 1);\n\n\n\n result = func0(tup1, 2, 500);\n\n assert(strcmp(result.str, \"HELLO\") == 0 && result.num == 5 && result.array[0] == 500 && result.boolean == 1);\n\n\n\n free(result.str);\n\n free(result.array);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov %rdi,%rbx\nmov %edx,%r12d\nmov 0x68(%rsp),%r13d\nmov 0x50(%rsp),%rdi\ncallq 10d0 \nmov %rax,0x8(%rsp)\nmov 0x58(%rsp),%r15d\nlea 0x1(%r13),%r14d\nmovslq %r14d,%rbp\nshl $0x2,%rbp\nmov %rbp,%rdi\ncallq 10c0 \ntest %r13d,%r13d\njle 1232 \nmov 0x60(%rsp),%rdi\nlea -0x1(%r13),%esi\nmov $0x0,%edx\nmov (%rdi,%rdx,4),%ecx\nmov %ecx,(%rax,%rdx,4)\nmov %rdx,%rcx\nadd $0x1,%rdx\ncmp %rsi,%rcx\njne 1220 \nmov %r12d,-0x4(%rax,%rbp,1)\nmov 0x8(%rsp),%rsi\nmov %rsi,(%rbx)\nmov %r15d,0x8(%rbx)\nmov %rax,0x10(%rbx)\nmov %r14d,0x18(%rbx)\nmov 0x6c(%rsp),%eax\nmov %eax,0x1c(%rbx)\nmov %rbx,%rax\nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov rbx, rdi\nmov r12d, edx\nmov r14d, dword ptr [rsp+48h+arg_18]\nmov rdi, [rsp+48h+s]; s\ncall _strdup\nmov [rsp+48h+var_40], rax\nmov r15d, [rsp+48h+arg_8]\nlea r13d, [r14+1]\nmovsxd rbp, r13d\nshl rbp, 2\nmov rdi, rbp; size\ncall _malloc\ntest r14d, r14d\njle short loc_124F\nmov rdi, [rsp+48h+arg_10]\nlea rsi, [rbp-4]\nmov edx, 0\nloc_1240:\nmov ecx, [rdi+rdx]\nmov [rax+rdx], ecx\nadd rdx, 4\ncmp rdx, rsi\njnz short loc_1240\nloc_124F:\nmov [rax+rbp-4], r12d\nmov rsi, [rsp+48h+var_40]\nmov [rbx], rsi\nmov [rbx+8], r15d\nmov [rbx+10h], rax\nmov [rbx+18h], r13d\nmov eax, dword ptr [rsp+48h+arg_18+4]\nmov [rbx+1Ch], eax\nmov rax, rbx\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3, int a4, int a5, int a6, char *s, int a8, __int64 a9, __int64 a10)\n{\n size_t v11; // rbp\n char *v12; // rax\n __int64 v13; // rdx\n char *v15; // [rsp+8h] [rbp-40h]\n\n v15 = strdup(s);\n v11 = 4LL * ((int)a10 + 1);\n v12 = (char *)malloc(v11);\n if ( (int)a10 > 0 )\n {\n v13 = 0LL;\n do\n {\n *(_DWORD *)&v12[v13] = *(_DWORD *)(a9 + v13);\n v13 += 4LL;\n }\n while ( v13 != v11 - 4 );\n }\n *(_DWORD *)&v12[v11 - 4] = a3;\n *(_QWORD *)a1 = v15;\n *(_DWORD *)(a1 + 8) = a8;\n *(_QWORD *)(a1 + 16) = v12;\n *(_DWORD *)(a1 + 24) = a10 + 1;\n *(_DWORD *)(a1 + 28) = HIDWORD(a10);\n return a1;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov rbx, rdi\nmov r12d, edx\nmov r14d, dword ptr [rsp+48h+arg_18]\nmov rdi, [rsp+48h+s]; s\ncall _strdup\nmov [rsp+48h+var_40], rax\nmov r15d, [rsp+48h+arg_8]\nlea r13d, [r14+1]\nmovsxd rbp, r13d\nshl rbp, 2\nmov rdi, rbp; size\ncall _malloc\ntest r14d, r14d\njle short loc_124F\nmov rdi, [rsp+48h+arg_10]\nlea rsi, [rbp-4]\nmov edx, 0\nloc_1240:\nmov ecx, [rdi+rdx]\nmov [rax+rdx], ecx\nadd rdx, 4\ncmp rdx, rsi\njnz short loc_1240\nloc_124F:\nmov [rax+rbp-4], r12d\nmov rsi, [rsp+48h+var_40]\nmov [rbx], rsi\nmov [rbx+8], r15d\nmov [rbx+10h], rax\nmov [rbx+18h], r13d\nmov eax, dword ptr [rsp+48h+arg_18+4]\nmov [rbx+1Ch], eax\nmov rax, rbx\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11E9(\n __int64 a1,\n int a2,\n int a3,\n int a4,\n int a5,\n int a6,\n char *s,\n int a8,\n __int64 a9,\n __int64 a10)\n{\n size_t v11; // rbp\n char *v12; // rax\n __int64 v13; // rdx\n char *v15; // [rsp+8h] [rbp-40h]\n\n v15 = strdup(s);\n v11 = 4LL * ((int)a10 + 1);\n v12 = (char *)malloc(v11);\n if ( (int)a10 > 0 )\n {\n v13 = 0LL;\n do\n {\n *(_DWORD *)&v12[v13] = *(_DWORD *)(a9 + v13);\n v13 += 4LL;\n }\n while ( v13 != v11 - 4 );\n }\n *(_DWORD *)&v12[v11 - 4] = a3;\n *(_QWORD *)a1 = v15;\n *(_DWORD *)(a1 + 8) = a8;\n *(_QWORD *)(a1 + 16) = v12;\n *(_DWORD *)(a1 + 24) = a10 + 1;\n *(_DWORD *)(a1 + 28) = HIDWORD(a10);\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11E9(long long a1, int a2, int a3, int a4, int a5, int a6,\n char *s, int a8, long long a9, long long a10) {\n unsigned int v11;\n char *v12;\n long long v13;\n char *v15;\n v15 = strdup(s);\n v11 = 4LL * ((int)a10 + 1);\n v12 = (char *)malloc(v11);\n if ((int)a10 > 0) {\n v13 = 0LL;\n do {\n *(uint32_t *)&v12[v13] = *(uint32_t *)(a9 + v13);\n v13 += 4LL;\n } while (v13 != v11 - 4);\n }\n *(uint32_t *)&v12[v11 - 4] = a3;\n *(uint64_t *)a1 = v15;\n *(uint32_t *)(a1 + 8) = a8;\n *(uint64_t *)(a1 + 16) = v12;\n *(uint32_t *)(a1 + 24) = a10 + 1;\n *(uint32_t *)(a1 + 28) = HIDWORD(a10);\n return a1;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3, int a4, int a5, int a6, char *s,\n int a8, long long a9, long long a10) {\n unsigned int v11;\n char *v12;\n long long v13;\n char *v15;\n v15 = strdup(s);\n v11 = 4LL * ((int)a10 + 1);\n v12 = (char *)malloc(v11);\n if ((int)a10 > 0) {\n v13 = 0LL;\n do {\n *(uint32_t *)&v12[v13] = *(uint32_t *)(a9 + v13);\n v13 += 4LL;\n } while (v13 != v11 - 4);\n }\n *(uint32_t *)&v12[v11 - 4] = a3;\n *(uint64_t *)a1 = v15;\n *(uint32_t *)(a1 + 8) = a8;\n *(uint64_t *)(a1 + 16) = v12;\n *(uint32_t *)(a1 + 24) = a10 + 1;\n *(uint32_t *)(a1 + 28) = HIDWORD(a10);\n return a1;\n}" + }, + { + "index": 307, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char *str;\n\n int num;\n\n int *array;\n\n int array_size;\n\n int boolean;\n\n} Tuple;\n\n\n\n", + "func": "Tuple func0(Tuple tuplex, int m, int n) {\n Tuple tuplex_colon;\n tuplex_colon.str = strdup(tuplex.str);\n tuplex_colon.num = tuplex.num;\n tuplex_colon.array = (int *)malloc(sizeof(int) * (tuplex.array_size + 1));\n for (int i = 0; i < tuplex.array_size; i++) {\n tuplex_colon.array[i] = tuplex.array[i];\n }\n tuplex_colon.array[tuplex.array_size] = n;\n tuplex_colon.array_size = tuplex.array_size + 1;\n tuplex_colon.boolean = tuplex.boolean;\n return tuplex_colon;\n}", + "test": "int main() {\n\n Tuple tup1 = {\"HELLO\", 5, NULL, 0, 1};\n\n Tuple result;\n\n\n\n result = func0(tup1, 2, 50);\n\n assert(strcmp(result.str, \"HELLO\") == 0 && result.num == 5 && result.array[0] == 50 && result.boolean == 1);\n\n\n\n result = func0(tup1, 2, 100);\n\n assert(strcmp(result.str, \"HELLO\") == 0 && result.num == 5 && result.array[0] == 100 && result.boolean == 1);\n\n\n\n result = func0(tup1, 2, 500);\n\n assert(strcmp(result.str, \"HELLO\") == 0 && result.num == 5 && result.array[0] == 500 && result.boolean == 1);\n\n\n\n free(result.str);\n\n free(result.array);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\nmov %edx,%r13d\npush %r12\nmov %rdi,%r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov 0x68(%rsp),%ebp\nmov 0x50(%rsp),%rdi\ncallq 10d0 \nlea 0x1(%rbp),%r14d\nmov 0x58(%rsp),%r15d\nmovslq %r14d,%rdx\nmov %rax,%rbx\nshl $0x2,%rdx\nmov %rdx,%rdi\nmov %rdx,0x8(%rsp)\ncallq 10c0 \ntest %ebp,%ebp\nmov 0x8(%rsp),%rdx\njle 1453 \nmov 0x60(%rsp),%r8\nlea -0x1(%rbp),%edi\nxor %ecx,%ecx\nnopl 0x0(%rax)\nmov (%r8,%rcx,4),%esi\nmov %esi,(%rax,%rcx,4)\nmov %rcx,%rsi\nadd $0x1,%rcx\ncmp %rdi,%rsi\njne 1440 \nmov %r13d,-0x4(%rax,%rdx,1)\nmov %rax,0x10(%r12)\nmov 0x6c(%rsp),%eax\nmov %rbx,(%r12)\nmov %r15d,0x8(%r12)\nmov %r14d,0x18(%r12)\nmov %eax,0x1c(%r12)\nadd $0x18,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14d, edx\npush r13\nmov r13, rdi\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov rdi, [rsp+48h+s]; s\nmov ebx, dword ptr [rsp+48h+arg_18]\ncall _strdup\nmov r15d, [rsp+48h+arg_8]\nmov rbp, rax\nlea eax, [rbx+1]\nmovsxd r12, eax\nmov [rsp+48h+var_3C], eax\nshl r12, 2\nmov rdi, r12; size\ncall _malloc\nmov rdi, rax; dest\ntest ebx, ebx\njle short loc_148E\nmov rsi, [rsp+48h+src]; src\nmov edx, ebx\nshl rdx, 2; n\ncall _memcpy\nmov rdi, rax\nloc_148E:\nmovd xmm0, [rsp+48h+var_3C]\nmovd xmm1, dword ptr [rsp+48h+arg_18+4]\nmov [rdi+r12-4], r14d\nmov rax, r13\nmov [r13+0], rbp\npunpckldq xmm0, xmm1\nmov [r13+8], r15d\nmov [r13+10h], rdi\nmovq qword ptr [r13+18h], xmm0\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3, int a4, int a5, int a6, char *s, int a8, void *src, __int64 a10)\n{\n char *v12; // rbp\n void *v13; // rdi\n __int64 result; // rax\n\n v12 = strdup(s);\n v13 = malloc(4LL * ((int)a10 + 1));\n if ( (int)a10 > 0 )\n v13 = memcpy(v13, src, 4LL * (unsigned int)a10);\n *((_DWORD *)v13 + (int)a10) = a3;\n result = a1;\n *(_QWORD *)a1 = v12;\n *(_DWORD *)(a1 + 8) = a8;\n *(_QWORD *)(a1 + 16) = v13;\n *(_QWORD *)(a1 + 24) = _mm_unpacklo_epi32(_mm_cvtsi32_si128((int)a10 + 1), _mm_cvtsi32_si128(HIDWORD(a10))).m128i_u64[0];\n return result;\n}", + "ida_strip_asm": "sub_1430:\nendbr64\npush r15\npush r14\nmov r14d, edx\npush r13\nmov r13, rdi\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov rdi, [rsp+48h+s]; s\nmov ebx, dword ptr [rsp+48h+arg_18]\ncall _strdup\nmov r15d, [rsp+48h+arg_8]\nmov rbp, rax\nlea eax, [rbx+1]\nmovsxd r12, eax\nmov [rsp+48h+var_3C], eax\nshl r12, 2\nmov rdi, r12; size\ncall _malloc\nmov rdi, rax; dest\ntest ebx, ebx\njle short loc_148E\nmov rsi, [rsp+48h+src]; src\nmov edx, ebx\nshl rdx, 2; n\ncall _memcpy\nmov rdi, rax\nloc_148E:\nmovd xmm0, [rsp+48h+var_3C]\nmovd xmm1, dword ptr [rsp+48h+arg_18+4]\nmov [rdi+r12-4], r14d\nmov rax, r13\nmov [r13+0], rbp\npunpckldq xmm0, xmm1\nmov [r13+8], r15d\nmov [r13+10h], rdi\nmovq qword ptr [r13+18h], xmm0\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1430(\n __int64 a1,\n int a2,\n int a3,\n int a4,\n int a5,\n int a6,\n char *s,\n int a8,\n void *src,\n __int64 a10)\n{\n char *v12; // rbp\n void *v13; // rdi\n __int64 result; // rax\n\n v12 = strdup(s);\n v13 = malloc(4LL * ((int)a10 + 1));\n if ( (int)a10 > 0 )\n v13 = memcpy(v13, src, 4LL * (unsigned int)a10);\n *((_DWORD *)v13 + (int)a10) = a3;\n result = a1;\n *(_QWORD *)a1 = v12;\n *(_DWORD *)(a1 + 8) = a8;\n *(_QWORD *)(a1 + 16) = v13;\n *(_QWORD *)(a1 + 24) = _mm_unpacklo_epi32(_mm_cvtsi32_si128((int)a10 + 1), _mm_cvtsi32_si128(HIDWORD(a10))).m128i_u64[0];\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1430(long long a1, int a2, int a3, int a4, int a5, int a6,\n char *s, int a8, void *src, long long a10) {\n char *v12;\n void *v13;\n long long result;\n v12 = strdup(s);\n v13 = malloc(4LL * ((int)a10 + 1));\n if ((int)a10 > 0) v13 = memcpy(v13, src, 4LL * (unsigned int)a10);\n *((uint32_t *)v13 + (int)a10) = a3;\n result = a1;\n *(uint64_t *)a1 = v12;\n *(uint32_t *)(a1 + 8) = a8;\n *(uint64_t *)(a1 + 16) = v13;\n *(uint64_t *)(a1 + 24) = _mm_unpacklo_epi32(_mm_cvtsi32_si128((int)a10 + 1),\n _mm_cvtsi32_si128(HIDWORD(a10)))\n .m128i_u64[0];\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3, int a4, int a5, int a6, char *s,\n int a8, void *src, long long a10) {\n char *v12;\n void *v13;\n long long result;\n v12 = strdup(s);\n v13 = malloc(4LL * ((int)a10 + 1));\n if ((int)a10 > 0) v13 = memcpy(v13, src, 4LL * (unsigned int)a10);\n *((uint32_t *)v13 + (int)a10) = a3;\n result = a1;\n *(uint64_t *)a1 = v12;\n *(uint32_t *)(a1 + 8) = a8;\n *(uint64_t *)(a1 + 16) = v13;\n *(uint64_t *)(a1 + 24) = _mm_unpacklo_epi32(_mm_cvtsi32_si128((int)a10 + 1),\n _mm_cvtsi32_si128(HIDWORD(a10)))\n .m128i_u64[0];\n return result;\n}" + }, + { + "index": 307, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char *str;\n\n int num;\n\n int *array;\n\n int array_size;\n\n int boolean;\n\n} Tuple;\n\n\n\n", + "func": "Tuple func0(Tuple tuplex, int m, int n) {\n Tuple tuplex_colon;\n tuplex_colon.str = strdup(tuplex.str);\n tuplex_colon.num = tuplex.num;\n tuplex_colon.array = (int *)malloc(sizeof(int) * (tuplex.array_size + 1));\n for (int i = 0; i < tuplex.array_size; i++) {\n tuplex_colon.array[i] = tuplex.array[i];\n }\n tuplex_colon.array[tuplex.array_size] = n;\n tuplex_colon.array_size = tuplex.array_size + 1;\n tuplex_colon.boolean = tuplex.boolean;\n return tuplex_colon;\n}", + "test": "int main() {\n\n Tuple tup1 = {\"HELLO\", 5, NULL, 0, 1};\n\n Tuple result;\n\n\n\n result = func0(tup1, 2, 50);\n\n assert(strcmp(result.str, \"HELLO\") == 0 && result.num == 5 && result.array[0] == 50 && result.boolean == 1);\n\n\n\n result = func0(tup1, 2, 100);\n\n assert(strcmp(result.str, \"HELLO\") == 0 && result.num == 5 && result.array[0] == 100 && result.boolean == 1);\n\n\n\n result = func0(tup1, 2, 500);\n\n assert(strcmp(result.str, \"HELLO\") == 0 && result.num == 5 && result.array[0] == 500 && result.boolean == 1);\n\n\n\n free(result.str);\n\n free(result.array);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\nmov %rdi,%r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov 0x68(%rsp),%r13d\nmov 0x50(%rsp),%rdi\nmov %edx,0xc(%rsp)\ncallq 10f0 \nlea 0x1(%r13),%r14d\nmov 0x58(%rsp),%r15d\nmovslq %r14d,%rbx\nmov %rax,%rbp\nshl $0x2,%rbx\nmov %rbx,%rdi\ncallq 10e0 \nmov %rax,%rcx\ntest %r13d,%r13d\njle 1467 \nlea -0x1(%r13),%eax\nmov 0x60(%rsp),%rsi\nmov %rcx,%rdi\nlea 0x4(,%rax,4),%rdx\ncallq 10d0 \nmov %rax,%rcx\nmov 0xc(%rsp),%eax\nmov %rbp,(%r12)\nmov %r15d,0x8(%r12)\nmov %eax,-0x4(%rcx,%rbx,1)\nmov 0x6c(%rsp),%eax\nmov %r14d,0x18(%r12)\nmov %eax,0x1c(%r12)\nmov %r12,%rax\nmov %rcx,0x10(%r12)\nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14d, edx\npush r13\nmov r13, rdi\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov rdi, [rsp+48h+s]; s\nmov ebx, dword ptr [rsp+48h+arg_18]\ncall _strdup\nmov r15d, [rsp+48h+arg_8]\nmov rbp, rax\nlea eax, [rbx+1]\nmovsxd r12, eax\nmov [rsp+48h+var_3C], eax\nshl r12, 2\nmov rdi, r12; size\ncall _malloc\nmov rdi, rax; dest\ntest ebx, ebx\njle short loc_148E\nmov rsi, [rsp+48h+src]; src\nmov edx, ebx\nshl rdx, 2; n\ncall _memcpy\nmov rdi, rax\nloc_148E:\nmovd xmm0, [rsp+48h+var_3C]\nmovd xmm1, dword ptr [rsp+48h+arg_18+4]\nmov [rdi+r12-4], r14d\nmov rax, r13\nmov [r13+0], rbp\npunpckldq xmm0, xmm1\nmov [r13+8], r15d\nmov [r13+10h], rdi\nmovq qword ptr [r13+18h], xmm0\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3, int a4, int a5, int a6, char *s, int a8, void *src, __int64 a10)\n{\n char *v12; // rbp\n void *v13; // rdi\n __int64 result; // rax\n\n v12 = strdup(s);\n v13 = malloc(4LL * ((int)a10 + 1));\n if ( (int)a10 > 0 )\n v13 = memcpy(v13, src, 4LL * (unsigned int)a10);\n *((_DWORD *)v13 + (int)a10) = a3;\n result = a1;\n *(_QWORD *)a1 = v12;\n *(_DWORD *)(a1 + 8) = a8;\n *(_QWORD *)(a1 + 16) = v13;\n *(_QWORD *)(a1 + 24) = _mm_unpacklo_epi32(_mm_cvtsi32_si128((int)a10 + 1), _mm_cvtsi32_si128(HIDWORD(a10))).m128i_u64[0];\n return result;\n}", + "ida_strip_asm": "sub_1430:\nendbr64\npush r15\npush r14\nmov r14d, edx\npush r13\nmov r13, rdi\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov rdi, [rsp+48h+s]; s\nmov ebx, dword ptr [rsp+48h+arg_18]\ncall _strdup\nmov r15d, [rsp+48h+arg_8]\nmov rbp, rax\nlea eax, [rbx+1]\nmovsxd r12, eax\nmov [rsp+48h+var_3C], eax\nshl r12, 2\nmov rdi, r12; size\ncall _malloc\nmov rdi, rax; dest\ntest ebx, ebx\njle short loc_148E\nmov rsi, [rsp+48h+src]; src\nmov edx, ebx\nshl rdx, 2; n\ncall _memcpy\nmov rdi, rax\nloc_148E:\nmovd xmm0, [rsp+48h+var_3C]\nmovd xmm1, dword ptr [rsp+48h+arg_18+4]\nmov [rdi+r12-4], r14d\nmov rax, r13\nmov [r13+0], rbp\npunpckldq xmm0, xmm1\nmov [r13+8], r15d\nmov [r13+10h], rdi\nmovq qword ptr [r13+18h], xmm0\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1430(\n __int64 a1,\n int a2,\n int a3,\n int a4,\n int a5,\n int a6,\n char *s,\n int a8,\n void *src,\n __int64 a10)\n{\n char *v12; // rbp\n void *v13; // rdi\n __int64 result; // rax\n\n v12 = strdup(s);\n v13 = malloc(4LL * ((int)a10 + 1));\n if ( (int)a10 > 0 )\n v13 = memcpy(v13, src, 4LL * (unsigned int)a10);\n *((_DWORD *)v13 + (int)a10) = a3;\n result = a1;\n *(_QWORD *)a1 = v12;\n *(_DWORD *)(a1 + 8) = a8;\n *(_QWORD *)(a1 + 16) = v13;\n *(_QWORD *)(a1 + 24) = _mm_unpacklo_epi32(_mm_cvtsi32_si128((int)a10 + 1), _mm_cvtsi32_si128(HIDWORD(a10))).m128i_u64[0];\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1430(long long a1, int a2, int a3, int a4, int a5, int a6,\n char *s, int a8, void *src, long long a10) {\n char *v12;\n void *v13;\n long long result;\n v12 = strdup(s);\n v13 = malloc(4LL * ((int)a10 + 1));\n if ((int)a10 > 0) v13 = memcpy(v13, src, 4LL * (unsigned int)a10);\n *((uint32_t *)v13 + (int)a10) = a3;\n result = a1;\n *(uint64_t *)a1 = v12;\n *(uint32_t *)(a1 + 8) = a8;\n *(uint64_t *)(a1 + 16) = v13;\n *(uint64_t *)(a1 + 24) = _mm_unpacklo_epi32(_mm_cvtsi32_si128((int)a10 + 1),\n _mm_cvtsi32_si128(HIDWORD(a10)))\n .m128i_u64[0];\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3, int a4, int a5, int a6, char *s,\n int a8, void *src, long long a10) {\n char *v12;\n void *v13;\n long long result;\n v12 = strdup(s);\n v13 = malloc(4LL * ((int)a10 + 1));\n if ((int)a10 > 0) v13 = memcpy(v13, src, 4LL * (unsigned int)a10);\n *((uint32_t *)v13 + (int)a10) = a3;\n result = a1;\n *(uint64_t *)a1 = v12;\n *(uint32_t *)(a1 + 8) = a8;\n *(uint64_t *)(a1 + 16) = v13;\n *(uint64_t *)(a1 + 24) = _mm_unpacklo_epi32(_mm_cvtsi32_si128((int)a10 + 1),\n _mm_cvtsi32_si128(HIDWORD(a10)))\n .m128i_u64[0];\n return result;\n}" + }, + { + "index": 308, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint compare(const void *a, const void *b) {\n\n return (*(int*)b - *(int*)a);\n\n}\n\n\n\n", + "func": "int* func0(int* nums1, int* nums2, int size1, int size2, int N) {\n int* result = malloc(sizeof(int) * N);\n int* products = malloc(sizeof(int) * size1 * size2);\n int index = 0;\n for (int i = 0; i < size1; i++) {\n for (int j = 0; j < size2; j++) {\n products[index++] = nums1[i] * nums2[j];\n }\n }\n qsort(products, size1 * size2, sizeof(int), compare);\n for (int i = 0; i < N; i++) {\n result[i] = products[i];\n }\n free(products);\n return result;\n}", + "test": "int main() {\n\n int nums1[] = {1, 2, 3, 4, 5, 6};\n\n int nums2[] = {3, 6, 8, 9, 10, 6};\n\n int size1 = sizeof(nums1) / sizeof(nums1[0]);\n\n int size2 = sizeof(nums2) / sizeof(nums2[0]);\n\n \n\n int* res;\n\n res = func0(nums1, nums2, size1, size2, 3);\n\n assert(res[0] == 60 && res[1] == 54 && res[2] == 50);\n\n free(res);\n\n\n\n res = func0(nums1, nums2, size1, size2, 4);\n\n assert(res[0] == 60 && res[1] == 54 && res[2] == 50 && res[3] == 48);\n\n free(res);\n\n\n\n res = func0(nums1, nums2, size1, size2, 5);\n\n assert(res[0] == 60 && res[1] == 54 && res[2] == 50 && res[3] == 48 && res[4] == 45);\n\n free(res);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x40,%rsp\nmov %rdi,-0x28(%rbp)\nmov %rsi,-0x30(%rbp)\nmov %edx,-0x34(%rbp)\nmov %ecx,-0x38(%rbp)\nmov %r8d,-0x3c(%rbp)\nmov -0x3c(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,-0x10(%rbp)\nmov -0x34(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x38(%rbp),%eax\ncltq\nimul %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0x20(%rbp)\nmovl $0x0,-0x1c(%rbp)\njmp 12b3 \nmovl $0x0,-0x18(%rbp)\njmp 12a7 \nmov -0x1c(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%esi\nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x30(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%ecx\nmov -0x20(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x20(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov %esi,%eax\nimul %ecx,%eax\nmov %eax,(%rdx)\naddl $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%eax\ncmp -0x38(%rbp),%eax\njl 1256 \naddl $0x1,-0x1c(%rbp)\nmov -0x1c(%rbp),%eax\ncmp -0x34(%rbp),%eax\njl 124d \nmov -0x34(%rbp),%eax\nimul -0x38(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x8(%rbp),%rax\nlea -0x107(%rip),%rcx\nmov $0x4,%edx\nmov %rax,%rdi\ncallq 10a0 \nmovl $0x0,-0x14(%rbp)\njmp 1317 \nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov -0x14(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x10(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\ncmp -0x3c(%rbp),%eax\njl 12e6 \nmov -0x8(%rbp),%rax\nmov %rax,%rdi\ncallq 1090 \nmov -0x10(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_30], rsi\nmov [rbp+var_34], edx\nmov [rbp+var_38], ecx\nmov [rbp+var_3C], r8d\nmov eax, [rbp+var_3C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_10], rax\nmov eax, [rbp+var_34]\nmovsxd rdx, eax\nmov eax, [rbp+var_38]\ncdqe\nimul rax, rdx\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+base], rax\nmov [rbp+var_20], 0\nmov [rbp+var_1C], 0\njmp short loc_12B3\nloc_124D:\nmov [rbp+var_18], 0\njmp short loc_12A7\nloc_1256:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov ecx, [rax]\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_20]\nlea esi, [rax+1]\nmov [rbp+var_20], esi\ncdqe\nlea rsi, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rsi, rax\nmov eax, ecx\nimul eax, edx\nmov [rsi], eax\nadd [rbp+var_18], 1\nloc_12A7:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_38]\njl short loc_1256\nadd [rbp+var_1C], 1\nloc_12B3:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_34]\njl short loc_124D\nmov eax, [rbp+var_34]\nimul eax, [rbp+var_38]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compare\nmov rcx, rdx; compar\nmov edx, 4; size\nmov rdi, rax; base\ncall _qsort\nmov [rbp+var_14], 0\njmp short loc_131A\nloc_12E9:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_10]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_14], 1\nloc_131A:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_3C]\njl short loc_12E9\nmov rax, [rbp+base]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_10]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, __int64 a2, int a3, int a4, int a5)\n{\n int v5; // eax\n int v10; // [rsp+20h] [rbp-20h]\n int i; // [rsp+24h] [rbp-1Ch]\n int j; // [rsp+28h] [rbp-18h]\n int k; // [rsp+2Ch] [rbp-14h]\n _DWORD *v14; // [rsp+30h] [rbp-10h]\n _DWORD *base; // [rsp+38h] [rbp-8h]\n\n v14 = malloc(4LL * a5);\n base = malloc(4 * a3 * (__int64)a4);\n v10 = 0;\n for ( i = 0; i < a3; ++i )\n {\n for ( j = 0; j < a4; ++j )\n {\n v5 = v10++;\n base[v5] = *(_DWORD *)(4LL * j + a2) * *(_DWORD *)(4LL * i + a1);\n }\n }\n qsort(base, a4 * a3, 4uLL, compare);\n for ( k = 0; k < a5; ++k )\n v14[k] = base[k];\n free(base);\n return v14;\n}", + "ida_strip_asm": "sub_11EB:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_30], rsi\nmov [rbp+var_34], edx\nmov [rbp+var_38], ecx\nmov [rbp+var_3C], r8d\nmov eax, [rbp+var_3C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_10], rax\nmov eax, [rbp+var_34]\nmovsxd rdx, eax\nmov eax, [rbp+var_38]\ncdqe\nimul rax, rdx\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+base], rax\nmov [rbp+var_20], 0\nmov [rbp+var_1C], 0\njmp short loc_12B3\nloc_124D:\nmov [rbp+var_18], 0\njmp short loc_12A7\nloc_1256:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov ecx, [rax]\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_20]\nlea esi, [rax+1]\nmov [rbp+var_20], esi\ncdqe\nlea rsi, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rsi, rax\nmov eax, ecx\nimul eax, edx\nmov [rsi], eax\nadd [rbp+var_18], 1\nloc_12A7:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_38]\njl short loc_1256\nadd [rbp+var_1C], 1\nloc_12B3:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_34]\njl short loc_124D\nmov eax, [rbp+var_34]\nimul eax, [rbp+var_38]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 4; size\nmov rdi, rax; base\ncall _qsort\nmov [rbp+var_14], 0\njmp short loc_131A\nloc_12E9:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_10]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_14], 1\nloc_131A:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_3C]\njl short loc_12E9\nmov rax, [rbp+base]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_10]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11EB(__int64 a1, __int64 a2, int a3, int a4, int a5)\n{\n int v5; // eax\n int v10; // [rsp+20h] [rbp-20h]\n int i; // [rsp+24h] [rbp-1Ch]\n int j; // [rsp+28h] [rbp-18h]\n int k; // [rsp+2Ch] [rbp-14h]\n _DWORD *v14; // [rsp+30h] [rbp-10h]\n _DWORD *base; // [rsp+38h] [rbp-8h]\n\n v14 = malloc(4LL * a5);\n base = malloc(4 * a3 * (__int64)a4);\n v10 = 0;\n for ( i = 0; i < a3; ++i )\n {\n for ( j = 0; j < a4; ++j )\n {\n v5 = v10++;\n base[v5] = *(_DWORD *)(4LL * j + a2) * *(_DWORD *)(4LL * i + a1);\n }\n }\n qsort(base, a4 * a3, 4uLL, compar);\n for ( k = 0; k < a5; ++k )\n v14[k] = base[k];\n free(base);\n return v14;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11EB(long long a1, long long a2, int a3, int a4, int a5) {\n int v5;\n int v10;\n int i;\n int j;\n int k;\n uint32_t *v14;\n uint32_t *base;\n v14 = malloc(4LL * a5);\n base = malloc(4 * a3 * (long long)a4);\n v10 = 0;\n for (i = 0; i < a3; ++i) {\n for (j = 0; j < a4; ++j) {\n v5 = v10++;\n base[v5] = *(uint32_t *)(4LL * j + a2) * *(uint32_t *)(4LL * i + a1);\n }\n }\n qsort(base, a4 * a3, 4uLL, compar);\n for (k = 0; k < a5; ++k) v14[k] = base[k];\n free(base);\n return v14;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, long long a2, int a3, int a4, int a5) {\n int v5;\n int v10;\n int i;\n int j;\n int k;\n uint32_t *v14;\n uint32_t *base;\n v14 = malloc(4LL * a5);\n base = malloc(4 * a3 * (long long)a4);\n v10 = 0;\n for (i = 0; i < a3; ++i) {\n for (j = 0; j < a4; ++j) {\n v5 = v10++;\n base[v5] = *(uint32_t *)(4LL * j + a2) * *(uint32_t *)(4LL * i + a1);\n }\n }\n qsort(base, a4 * a3, 4uLL, compare);\n for (k = 0; k < a5; ++k) v14[k] = base[k];\n free(base);\n return v14;\n}" + }, + { + "index": 308, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint compare(const void *a, const void *b) {\n\n return (*(int*)b - *(int*)a);\n\n}\n\n\n\n", + "func": "int* func0(int* nums1, int* nums2, int size1, int size2, int N) {\n int* result = malloc(sizeof(int) * N);\n int* products = malloc(sizeof(int) * size1 * size2);\n int index = 0;\n for (int i = 0; i < size1; i++) {\n for (int j = 0; j < size2; j++) {\n products[index++] = nums1[i] * nums2[j];\n }\n }\n qsort(products, size1 * size2, sizeof(int), compare);\n for (int i = 0; i < N; i++) {\n result[i] = products[i];\n }\n free(products);\n return result;\n}", + "test": "int main() {\n\n int nums1[] = {1, 2, 3, 4, 5, 6};\n\n int nums2[] = {3, 6, 8, 9, 10, 6};\n\n int size1 = sizeof(nums1) / sizeof(nums1[0]);\n\n int size2 = sizeof(nums2) / sizeof(nums2[0]);\n\n \n\n int* res;\n\n res = func0(nums1, nums2, size1, size2, 3);\n\n assert(res[0] == 60 && res[1] == 54 && res[2] == 50);\n\n free(res);\n\n\n\n res = func0(nums1, nums2, size1, size2, 4);\n\n assert(res[0] == 60 && res[1] == 54 && res[2] == 50 && res[3] == 48);\n\n free(res);\n\n\n\n res = func0(nums1, nums2, size1, size2, 5);\n\n assert(res[0] == 60 && res[1] == 54 && res[2] == 50 && res[3] == 48 && res[4] == 45);\n\n free(res);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov %rdi,0x8(%rsp)\nmov %rsi,%rbx\nmov %edx,%r14d\nmov %ecx,%ebp\nmov %r8d,%r15d\nmovslq %r8d,%rdi\nshl $0x2,%rdi\ncallq 10d0 \nmov %rax,%r13\nmovslq %r14d,%rdi\nmovslq %ebp,%rax\nimul %rax,%rdi\nshl $0x2,%rdi\ncallq 10d0 \nmov %rax,%r12\ntest %r14d,%r14d\njle 1270 \nmov 0x8(%rsp),%rsi\nmov %rsi,%r8\nlea -0x1(%r14),%eax\nlea 0x4(%rsi,%rax,4),%r10\nmov $0x0,%r9d\nlea -0x1(%rbp),%edi\njmp 126a \nmov (%r8),%esi\nmovslq %r9d,%rax\nlea (%r12,%rax,4),%rcx\nmov $0x0,%eax\nmov %esi,%edx\nimul (%rbx,%rax,4),%edx\nmov %edx,(%rcx,%rax,4)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rdi,%rdx\njne 1249 \nadd %ebp,%r9d\nadd $0x4,%r8\ncmp %r10,%r8\nje 1270 \ntest %ebp,%ebp\njg 123a \njmp 1261 \nimul %r14d,%ebp\nmovslq %ebp,%rsi\nlea -0xb5(%rip),%rcx\nmov $0x4,%edx\nmov %r12,%rdi\ncallq 10a0 \ntest %r15d,%r15d\njle 12ae \nlea -0x1(%r15),%ecx\nmov $0x0,%eax\nmov (%r12,%rax,4),%edx\nmov %edx,0x0(%r13,%rax,4)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rdx,%rcx\njne 1299 \nmov %r12,%rdi\ncallq 1090 \nmov %r13,%rax\nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov [rsp+58h+var_40], rdi\nmov rbx, rsi\nmov r15d, edx\nmov r12d, ecx\nmov [rsp+58h+var_4C], r8d\nmovsxd r14, r8d\nshl r14, 2\nmov rdi, r14; size\ncall _malloc\nmov r13, rax\nmov [rsp+58h+var_50], r15d\nmovsxd r15, r15d\nmovsxd rax, r12d\nmov [rsp+58h+var_48], rax\nmov rsi, rax\nimul rsi, r15\nmov [rsp+58h+nmemb], rsi\nlea rdi, ds:0[rsi*4]; size\ncall _malloc\nmov rbp, rax\ncmp [rsp+58h+var_50], 0\njle short loc_128D\nmov rdi, [rsp+58h+var_40]\nmov r8, rdi\nlea r10, [rdi+r15*4]\nmov rdi, [rsp+58h+var_48]\nshl rdi, 2\nmov r9d, 0\njmp short loc_1286\nloc_1258:\nmov esi, [r8]\nmovsxd rax, r9d\nlea rcx, [rbp+rax*4+0]\nmov eax, 0\nloc_1268:\nmov edx, esi\nimul edx, [rbx+rax]\nmov [rcx+rax], edx\nadd rax, 4\ncmp rax, rdi\njnz short loc_1268\nadd r9d, r12d\nloc_127D:\nadd r8, 4\ncmp r8, r10\njz short loc_128D\nloc_1286:\ntest r12d, r12d\njg short loc_1258\njmp short loc_127D\nloc_128D:\nlea rcx, compare; compar\nmov edx, 4; size\nmov rsi, [rsp+58h+nmemb]; nmemb\nmov rdi, rbp; base\ncall _qsort\ncmp [rsp+58h+var_4C], 0\njle short loc_12C3\nmov eax, 0\nloc_12B1:\nmov edx, [rbp+rax+0]\nmov [r13+rax+0], edx\nadd rax, 4\ncmp r14, rax\njnz short loc_12B1\nloc_12C3:\nmov rdi, rbp; ptr\ncall _free\nmov rax, r13\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "char *__fastcall func0(int *a1, __int64 a2, int a3, int a4, int a5)\n{\n size_t v8; // r14\n char *v9; // r13\n char *v10; // rbp\n int *v11; // r8\n int v12; // r9d\n int v13; // esi\n __int64 v14; // rax\n __int64 v15; // rax\n __int64 nmemb; // [rsp+0h] [rbp-58h]\n\n v8 = 4LL * a5;\n v9 = (char *)malloc(v8);\n nmemb = a3 * (__int64)a4;\n v10 = (char *)malloc(4 * nmemb);\n if ( a3 > 0 )\n {\n v11 = a1;\n v12 = 0;\n do\n {\n if ( a4 > 0 )\n {\n v13 = *v11;\n v14 = 0LL;\n do\n {\n *(_DWORD *)&v10[4 * v12 + v14] = *(_DWORD *)(a2 + v14) * v13;\n v14 += 4LL;\n }\n while ( v14 != 4LL * a4 );\n v12 += a4;\n }\n ++v11;\n }\n while ( v11 != &a1[a3] );\n }\n qsort(v10, nmemb, 4uLL, compare);\n if ( a5 > 0 )\n {\n v15 = 0LL;\n do\n {\n *(_DWORD *)&v9[v15] = *(_DWORD *)&v10[v15];\n v15 += 4LL;\n }\n while ( v8 != v15 );\n }\n free(v10);\n return v9;\n}", + "ida_strip_asm": "sub_11D2:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov [rsp+58h+var_40], rdi\nmov rbx, rsi\nmov r15d, edx\nmov r12d, ecx\nmov [rsp+58h+var_4C], r8d\nmovsxd r14, r8d\nshl r14, 2\nmov rdi, r14; size\ncall _malloc\nmov r13, rax\nmov [rsp+58h+var_50], r15d\nmovsxd r15, r15d\nmovsxd rax, r12d\nmov [rsp+58h+var_48], rax\nmov rsi, rax\nimul rsi, r15\nmov [rsp+58h+nmemb], rsi\nlea rdi, ds:0[rsi*4]; size\ncall _malloc\nmov rbp, rax\ncmp [rsp+58h+var_50], 0\njle short loc_128D\nmov rdi, [rsp+58h+var_40]\nmov r8, rdi\nlea r10, [rdi+r15*4]\nmov rdi, [rsp+58h+var_48]\nshl rdi, 2\nmov r9d, 0\njmp short loc_1286\nloc_1258:\nmov esi, [r8]\nmovsxd rax, r9d\nlea rcx, [rbp+rax*4+0]\nmov eax, 0\nloc_1268:\nmov edx, esi\nimul edx, [rbx+rax]\nmov [rcx+rax], edx\nadd rax, 4\ncmp rax, rdi\njnz short loc_1268\nadd r9d, r12d\nloc_127D:\nadd r8, 4\ncmp r8, r10\njz short loc_128D\nloc_1286:\ntest r12d, r12d\njg short loc_1258\njmp short loc_127D\nloc_128D:\nlea rcx, compar; compar\nmov edx, 4; size\nmov rsi, [rsp+58h+nmemb]; nmemb\nmov rdi, rbp; base\ncall _qsort\ncmp [rsp+58h+var_4C], 0\njle short loc_12C3\nmov eax, 0\nloc_12B1:\nmov edx, [rbp+rax+0]\nmov [r13+rax+0], edx\nadd rax, 4\ncmp r14, rax\njnz short loc_12B1\nloc_12C3:\nmov rdi, rbp; ptr\ncall _free\nmov rax, r13\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11D2(int *a1, __int64 a2, int a3, int a4, int a5)\n{\n size_t v8; // r14\n char *v9; // r13\n char *v10; // rbp\n int *v11; // r8\n int v12; // r9d\n int v13; // esi\n __int64 v14; // rax\n __int64 v15; // rax\n __int64 nmemb; // [rsp+0h] [rbp-58h]\n\n v8 = 4LL * a5;\n v9 = (char *)malloc(v8);\n nmemb = a3 * (__int64)a4;\n v10 = (char *)malloc(4 * nmemb);\n if ( a3 > 0 )\n {\n v11 = a1;\n v12 = 0;\n do\n {\n if ( a4 > 0 )\n {\n v13 = *v11;\n v14 = 0LL;\n do\n {\n *(_DWORD *)&v10[4 * v12 + v14] = *(_DWORD *)(a2 + v14) * v13;\n v14 += 4LL;\n }\n while ( v14 != 4LL * a4 );\n v12 += a4;\n }\n ++v11;\n }\n while ( v11 != &a1[a3] );\n }\n qsort(v10, nmemb, 4uLL, compar);\n if ( a5 > 0 )\n {\n v15 = 0LL;\n do\n {\n *(_DWORD *)&v9[v15] = *(_DWORD *)&v10[v15];\n v15 += 4LL;\n }\n while ( v8 != v15 );\n }\n free(v10);\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11D2(int *a1, long long a2, int a3, int a4, int a5) {\n unsigned int v8;\n char *v9;\n char *v10;\n int *v11;\n int v12;\n int v13;\n long long v14;\n long long v15;\n long long nmemb;\n v8 = 4LL * a5;\n v9 = (char *)malloc(v8);\n nmemb = a3 * (long long)a4;\n v10 = (char *)malloc(4 * nmemb);\n if (a3 > 0) {\n v11 = a1;\n v12 = 0;\n do {\n if (a4 > 0) {\n v13 = *v11;\n v14 = 0LL;\n do {\n *(uint32_t *)&v10[4 * v12 + v14] = *(uint32_t *)(a2 + v14) * v13;\n v14 += 4LL;\n } while (v14 != 4LL * a4);\n v12 += a4;\n }\n ++v11;\n } while (v11 != &a1[a3]);\n }\n qsort(v10, nmemb, 4uLL, compar);\n if (a5 > 0) {\n v15 = 0LL;\n do {\n *(uint32_t *)&v9[v15] = *(uint32_t *)&v10[v15];\n v15 += 4LL;\n } while (v8 != v15);\n }\n free(v10);\n return v9;\n}", + "ida_pseudo_norm": "char *func0(int *a1, long long a2, int a3, int a4, int a5) {\n unsigned int v8;\n char *v9;\n char *v10;\n int *v11;\n int v12;\n int v13;\n long long v14;\n long long v15;\n long long nmemb;\n v8 = 4LL * a5;\n v9 = (char *)malloc(v8);\n nmemb = a3 * (long long)a4;\n v10 = (char *)malloc(4 * nmemb);\n if (a3 > 0) {\n v11 = a1;\n v12 = 0;\n do {\n if (a4 > 0) {\n v13 = *v11;\n v14 = 0LL;\n do {\n *(uint32_t *)&v10[4 * v12 + v14] = *(uint32_t *)(a2 + v14) * v13;\n v14 += 4LL;\n } while (v14 != 4LL * a4);\n v12 += a4;\n }\n ++v11;\n } while (v11 != &a1[a3]);\n }\n qsort(v10, nmemb, 4uLL, compare);\n if (a5 > 0) {\n v15 = 0LL;\n do {\n *(uint32_t *)&v9[v15] = *(uint32_t *)&v10[v15];\n v15 += 4LL;\n } while (v8 != v15);\n }\n free(v10);\n return v9;\n}" + }, + { + "index": 308, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint compare(const void *a, const void *b) {\n\n return (*(int*)b - *(int*)a);\n\n}\n\n\n\n", + "func": "int* func0(int* nums1, int* nums2, int size1, int size2, int N) {\n int* result = malloc(sizeof(int) * N);\n int* products = malloc(sizeof(int) * size1 * size2);\n int index = 0;\n for (int i = 0; i < size1; i++) {\n for (int j = 0; j < size2; j++) {\n products[index++] = nums1[i] * nums2[j];\n }\n }\n qsort(products, size1 * size2, sizeof(int), compare);\n for (int i = 0; i < N; i++) {\n result[i] = products[i];\n }\n free(products);\n return result;\n}", + "test": "int main() {\n\n int nums1[] = {1, 2, 3, 4, 5, 6};\n\n int nums2[] = {3, 6, 8, 9, 10, 6};\n\n int size1 = sizeof(nums1) / sizeof(nums1[0]);\n\n int size2 = sizeof(nums2) / sizeof(nums2[0]);\n\n \n\n int* res;\n\n res = func0(nums1, nums2, size1, size2, 3);\n\n assert(res[0] == 60 && res[1] == 54 && res[2] == 50);\n\n free(res);\n\n\n\n res = func0(nums1, nums2, size1, size2, 4);\n\n assert(res[0] == 60 && res[1] == 54 && res[2] == 50 && res[3] == 48);\n\n free(res);\n\n\n\n res = func0(nums1, nums2, size1, size2, 5);\n\n assert(res[0] == 60 && res[1] == 54 && res[2] == 50 && res[3] == 48 && res[4] == 45);\n\n free(res);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmov %edx,%r15d\npush %r14\npush %r13\nmov %ecx,%r13d\npush %r12\nmov %rdi,%r12\nmovslq %r8d,%rdi\npush %rbp\nmov %rsi,%rbp\npush %rbx\nmov %rdi,%rbx\nshl $0x2,%rdi\nsub $0x18,%rsp\ncallq 10d0 \nmovslq %r15d,%rdi\nmov %rax,%r14\nmovslq %r13d,%rax\nimul %rax,%rdi\nshl $0x2,%rdi\ncallq 10d0 \nmov %rax,%r8\ntest %r15d,%r15d\njle 143d \nlea -0x1(%r15),%eax\nxor %edx,%edx\nlea 0x4(%r12,%rax,4),%rcx\nlea -0x1(%r13),%eax\nnopw 0x0(%rax,%rax,1)\ntest %r13d,%r13d\njle 1434 \nmovslq %edx,%rsi\nmov (%r12),%r11d\nxor %edi,%edi\nlea (%r8,%rsi,4),%r10\nnopw 0x0(%rax,%rax,1)\nmov 0x0(%rbp,%rdi,4),%r9d\nimul %r11d,%r9d\nmov %r9d,(%r10,%rdi,4)\nmov %rdi,%r9\nadd $0x1,%rdi\ncmp %rax,%r9\njne 1418 \nadd %r13d,%edx\nadd $0x4,%r12\ncmp %rcx,%r12\njne 1400 \nimul %r15d,%r13d\nmov %r8,%rdi\nmov $0x4,%edx\nmov %r8,0x8(%rsp)\nlea -0xc5(%rip),%rcx\nmovslq %r13d,%rsi\ncallq 10a0 \ntest %ebx,%ebx\nmov 0x8(%rsp),%r8\njle 1484 \nlea -0x1(%rbx),%ecx\nxor %eax,%eax\nnopl 0x0(%rax,%rax,1)\nmov (%r8,%rax,4),%edx\nmov %edx,(%r14,%rax,4)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rdx,%rcx\njne 1470 \nmov %r8,%rdi\ncallq 1090 \nadd $0x18,%rsp\nmov %r14,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov r15d, edx\npush r14\npush r13\nmov r13, rdi\nmovsxd rdi, r8d\npush r12\nmov r12, rsi\npush rbp\nmov ebp, ecx\npush rbx\nmov rbx, rdi\nshl rdi, 2; size\nsub rsp, 28h\ncall _malloc\nmovsxd rcx, r15d\nmovsxd rdx, ebp\nmov r8, rcx\nmov [rsp+58h+dest], rax\nimul r8, rdx\nmov [rsp+58h+var_40], rcx\nmov [rsp+58h+var_48], rdx\nlea rdi, ds:0[r8*4]; size\nmov [rsp+58h+nmemb], r8\ncall _malloc\ntest r15d, r15d\nmov r8, [rsp+58h+nmemb]\nmov r14, rax\njle short loc_1457\nmov rcx, [rsp+58h+var_40]\nmov rdx, [rsp+58h+var_48]\nlea r11, [r13+rcx*4+0]\nlea rdi, ds:0[rdx*4]\nloc_141D:\ntest ebp, ebp\njle short loc_149F\nxor r10d, r10d\nnop dword ptr [rax+00h]\nloc_1428:\nmovsxd rax, r10d\nmov esi, [r13+0]\nlea rcx, [r14+rax*4]\nxor eax, eax\nnop dword ptr [rax]\nloc_1438:\nmov edx, [r12+rax]\nimul edx, esi\nmov [rcx+rax], edx\nadd rax, 4\ncmp rax, rdi\njnz short loc_1438\nadd r13, 4\nadd r10d, ebp\ncmp r13, r11\njnz short loc_1428\nloc_1457:\nlea rcx, compare; compar\nmov edx, 4; size\nmov rsi, r8; nmemb\nmov rdi, r14; base\ncall _qsort\ntest ebx, ebx\njle short loc_1484\nmov edx, ebx\nmov rdi, [rsp+58h+dest]; dest\nmov rsi, r14; src\nshl rdx, 2; n\ncall _memcpy\nloc_1484:\nmov rdi, r14; ptr\ncall _free\nmov rax, [rsp+58h+dest]\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_149F:\nadd r13, 4\ncmp r13, r11\njnz loc_141D\njmp short loc_1457", + "ida_pseudo": "void *__fastcall func0(int *a1, __int64 a2, int a3, int a4, int a5)\n{\n int *v6; // r13\n char *v10; // r14\n int *v11; // r11\n int v12; // r10d\n int v13; // esi\n __int64 v14; // rax\n void *dest; // [rsp+0h] [rbp-58h]\n\n v6 = a1;\n dest = malloc(4LL * a5);\n v10 = (char *)malloc(4 * a4 * (__int64)a3);\n if ( a3 > 0 )\n {\n v11 = &a1[a3];\n while ( a4 <= 0 )\n {\n if ( ++v6 == v11 )\n goto LABEL_8;\n }\n v12 = 0;\n do\n {\n v13 = *v6;\n v14 = 0LL;\n do\n {\n *(_DWORD *)&v10[4 * v12 + v14] = v13 * *(_DWORD *)(a2 + v14);\n v14 += 4LL;\n }\n while ( v14 != 4LL * a4 );\n ++v6;\n v12 += a4;\n }\n while ( v6 != v11 );\n }\nLABEL_8:\n qsort(v10, a4 * (__int64)a3, 4uLL, compare);\n if ( a5 > 0 )\n memcpy(dest, v10, 4LL * (unsigned int)a5);\n free(v10);\n return dest;\n}", + "ida_strip_asm": "sub_13A0:\nendbr64\npush r15\nmov r15d, edx\npush r14\npush r13\nmov r13, rdi\nmovsxd rdi, r8d\npush r12\nmov r12, rsi\npush rbp\nmov ebp, ecx\npush rbx\nmov rbx, rdi\nshl rdi, 2; size\nsub rsp, 28h\ncall _malloc\nmovsxd rcx, r15d\nmovsxd rdx, ebp\nmov r8, rcx\nmov [rsp+58h+dest], rax\nimul r8, rdx\nmov [rsp+58h+var_40], rcx\nmov [rsp+58h+var_48], rdx\nlea rdi, ds:0[r8*4]; size\nmov [rsp+58h+nmemb], r8\ncall _malloc\ntest r15d, r15d\nmov r8, [rsp+58h+nmemb]\nmov r14, rax\njle short loc_1457\nmov rcx, [rsp+58h+var_40]\nmov rdx, [rsp+58h+var_48]\nlea r11, [r13+rcx*4+0]\nlea rdi, ds:0[rdx*4]\nloc_141D:\ntest ebp, ebp\njle short loc_149F\nxor r10d, r10d\nnop dword ptr [rax+00h]\nloc_1428:\nmovsxd rax, r10d\nmov esi, [r13+0]\nlea rcx, [r14+rax*4]\nxor eax, eax\nnop dword ptr [rax]\nloc_1438:\nmov edx, [r12+rax]\nimul edx, esi\nmov [rcx+rax], edx\nadd rax, 4\ncmp rax, rdi\njnz short loc_1438\nadd r13, 4\nadd r10d, ebp\ncmp r13, r11\njnz short loc_1428\nloc_1457:\nlea rcx, compar; compar\nmov edx, 4; size\nmov rsi, r8; nmemb\nmov rdi, r14; base\ncall _qsort\ntest ebx, ebx\njle short loc_1484\nmov edx, ebx\nmov rdi, [rsp+58h+dest]; dest\nmov rsi, r14; src\nshl rdx, 2; n\ncall _memcpy\nloc_1484:\nmov rdi, r14; ptr\ncall _free\nmov rax, [rsp+58h+dest]\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_149F:\nadd r13, 4\ncmp r13, r11\njnz loc_141D\njmp short loc_1457", + "ida_strip_pseudo": "void *__fastcall sub_13A0(int *a1, __int64 a2, int a3, int a4, int a5)\n{\n int *v6; // r13\n char *v10; // r14\n int *v11; // r11\n int v12; // r10d\n int v13; // esi\n __int64 v14; // rax\n void *dest; // [rsp+0h] [rbp-58h]\n\n v6 = a1;\n dest = malloc(4LL * a5);\n v10 = (char *)malloc(4 * a4 * (__int64)a3);\n if ( a3 > 0 )\n {\n v11 = &a1[a3];\n while ( a4 <= 0 )\n {\n if ( ++v6 == v11 )\n goto LABEL_8;\n }\n v12 = 0;\n do\n {\n v13 = *v6;\n v14 = 0LL;\n do\n {\n *(_DWORD *)&v10[4 * v12 + v14] = v13 * *(_DWORD *)(a2 + v14);\n v14 += 4LL;\n }\n while ( v14 != 4LL * a4 );\n ++v6;\n v12 += a4;\n }\n while ( v6 != v11 );\n }\nLABEL_8:\n qsort(v10, a4 * (__int64)a3, 4uLL, compar);\n if ( a5 > 0 )\n memcpy(dest, v10, 4LL * (unsigned int)a5);\n free(v10);\n return dest;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_13A0(int *a1, long long a2, int a3, int a4, int a5) {\n int *v6;\n char *v10;\n int *v11;\n int v12;\n int v13;\n long long v14;\n void *dest;\n v6 = a1;\n dest = malloc(4LL * a5);\n v10 = (char *)malloc(4 * a4 * (long long)a3);\n if (a3 > 0) {\n v11 = &a1[a3];\n while (a4 <= 0) {\n if (++v6 == v11) goto LABEL_8;\n }\n v12 = 0;\n do {\n v13 = *v6;\n v14 = 0LL;\n do {\n *(uint32_t *)&v10[4 * v12 + v14] = v13 * *(uint32_t *)(a2 + v14);\n v14 += 4LL;\n } while (v14 != 4LL * a4);\n ++v6;\n v12 += a4;\n } while (v6 != v11);\n }\nLABEL_8:\n qsort(v10, a4 * (long long)a3, 4uLL, compar);\n if (a5 > 0) memcpy(dest, v10, 4LL * (unsigned int)a5);\n free(v10);\n return dest;\n}", + "ida_pseudo_norm": "void *func0(int *a1, long long a2, int a3, int a4, int a5) {\n int *v6;\n char *v10;\n int *v11;\n int v12;\n int v13;\n long long v14;\n void *dest;\n v6 = a1;\n dest = malloc(4LL * a5);\n v10 = (char *)malloc(4 * a4 * (long long)a3);\n if (a3 > 0) {\n v11 = &a1[a3];\n while (a4 <= 0) {\n if (++v6 == v11) goto LABEL_8;\n }\n v12 = 0;\n do {\n v13 = *v6;\n v14 = 0LL;\n do {\n *(uint32_t *)&v10[4 * v12 + v14] = v13 * *(uint32_t *)(a2 + v14);\n v14 += 4LL;\n } while (v14 != 4LL * a4);\n ++v6;\n v12 += a4;\n } while (v6 != v11);\n }\nLABEL_8:\n qsort(v10, a4 * (long long)a3, 4uLL, compare);\n if (a5 > 0) memcpy(dest, v10, 4LL * (unsigned int)a5);\n free(v10);\n return dest;\n}" + }, + { + "index": 308, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint compare(const void *a, const void *b) {\n\n return (*(int*)b - *(int*)a);\n\n}\n\n\n\n", + "func": "int* func0(int* nums1, int* nums2, int size1, int size2, int N) {\n int* result = malloc(sizeof(int) * N);\n int* products = malloc(sizeof(int) * size1 * size2);\n int index = 0;\n for (int i = 0; i < size1; i++) {\n for (int j = 0; j < size2; j++) {\n products[index++] = nums1[i] * nums2[j];\n }\n }\n qsort(products, size1 * size2, sizeof(int), compare);\n for (int i = 0; i < N; i++) {\n result[i] = products[i];\n }\n free(products);\n return result;\n}", + "test": "int main() {\n\n int nums1[] = {1, 2, 3, 4, 5, 6};\n\n int nums2[] = {3, 6, 8, 9, 10, 6};\n\n int size1 = sizeof(nums1) / sizeof(nums1[0]);\n\n int size2 = sizeof(nums2) / sizeof(nums2[0]);\n\n \n\n int* res;\n\n res = func0(nums1, nums2, size1, size2, 3);\n\n assert(res[0] == 60 && res[1] == 54 && res[2] == 50);\n\n free(res);\n\n\n\n res = func0(nums1, nums2, size1, size2, 4);\n\n assert(res[0] == 60 && res[1] == 54 && res[2] == 50 && res[3] == 48);\n\n free(res);\n\n\n\n res = func0(nums1, nums2, size1, size2, 5);\n\n assert(res[0] == 60 && res[1] == 54 && res[2] == 50 && res[3] == 48 && res[4] == 45);\n\n free(res);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\nmov %edx,%r14d\npush %r13\nmov %rdi,%r13\nmovslq %r8d,%rdi\npush %r12\npush %rbp\nmov %ecx,%ebp\npush %rbx\nmov %rsi,%rbx\nsub $0x28,%rsp\nmov %edi,0x1c(%rsp)\nshl $0x2,%rdi\nmov %edx,0x18(%rsp)\ncallq 10f0 \nmovslq %r14d,%rdi\nmov %rax,0x10(%rsp)\nmovslq %ebp,%rax\nimul %rax,%rdi\nshl $0x2,%rdi\ncallq 10f0 \nmov %rax,%r12\ntest %r14d,%r14d\njle 14f2 \ntest %ebp,%ebp\njle 14f2 \nlea -0x1(%r14),%eax\nmov %ebp,%r9d\nmov %r13,%rdi\nxor %r8d,%r8d\nlea 0x4(%r13,%rax,4),%r15\nmov %ebp,%eax\nlea -0x1(%rbp),%r14d\nand $0xfffffffc,%r9d\nshr $0x2,%eax\nshl $0x4,%rax\nmov %rax,0x8(%rsp)\nnopl (%rax)\nmov (%rdi),%esi\ncmp $0x2,%r14d\njbe 154a \nmovd %esi,%xmm4\nmovslq %r8d,%rdx\nmov 0x8(%rsp),%rax\npshufd $0x0,%xmm4,%xmm2\nlea (%r12,%rdx,4),%rcx\nxor %edx,%edx\nmovdqa %xmm2,%xmm3\npsrlq $0x20,%xmm3\nnopl 0x0(%rax)\nmovdqu (%rbx,%rdx,1),%xmm0\nmovdqu (%rbx,%rdx,1),%xmm1\npsrlq $0x20,%xmm0\npmuludq %xmm2,%xmm1\npmuludq %xmm3,%xmm0\npshufd $0x8,%xmm1,%xmm1\npshufd $0x8,%xmm0,%xmm0\npunpckldq %xmm0,%xmm1\nmovups %xmm1,(%rcx,%rdx,1)\nadd $0x10,%rdx\ncmp %rax,%rdx\njne 1458 \nmov %rax,0x8(%rsp)\nlea (%r8,%r9,1),%ecx\nmov %r9d,%edx\ncmp %r9d,%ebp\nje 14e2 \nmovslq %edx,%r13\nmovslq %ecx,%rcx\nmov (%rbx,%r13,4),%eax\nlea 0x0(,%rcx,4),%r10\nlea 0x0(,%r13,4),%r11\nimul %esi,%eax\nmov %eax,(%r12,%rcx,4)\nlea 0x1(%rdx),%ecx\ncmp %ebp,%ecx\njge 14e2 \nmov 0x4(%rbx,%r11,1),%ecx\nadd $0x2,%edx\nimul %esi,%ecx\nmov %ecx,0x4(%r12,%r10,1)\ncmp %edx,%ebp\njle 14e2 \nimul 0x8(%rbx,%r11,1),%esi\nmov %esi,0x8(%r12,%r10,1)\nadd $0x4,%rdi\nadd %ebp,%r8d\ncmp %r15,%rdi\njne 1428 \nimul 0x18(%rsp),%ebp\nlea -0x16e(%rip),%rcx\nmov $0x4,%edx\nmov %r12,%rdi\nmovslq %ebp,%rsi\ncallq 10b0 \nmov 0x1c(%rsp),%eax\ntest %eax,%eax\njle 152e \nsub $0x1,%eax\nmov 0x10(%rsp),%rdi\nmov %r12,%rsi\nlea 0x4(,%rax,4),%rdx\ncallq 10e0 \nmov %r12,%rdi\ncallq 10a0 \nmov 0x10(%rsp),%rax\nadd $0x28,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmov %r8d,%ecx\nxor %edx,%edx\njmpq 149b \nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r15\nmovsxd r15, edx\npush r14\npush r13\npush r12\npush rbp\nmov ebp, ecx\npush rbx\nmov rbx, rsi\nsub rsp, 28h\nmov [rsp+58h+var_48], rdi\nmovsxd rdi, r8d\nmov r13, rdi\nshl rdi, 2; size\ncall _malloc\nmov [rsp+58h+dest], rax\nmovsxd rax, ebp\nimul rax, r15\nlea rdi, ds:0[rax*4]; size\nmov [rsp+58h+nmemb], rax\ncall _malloc\ntest r15d, r15d\nmov r10, [rsp+58h+nmemb]\nmov r12, rax\njle loc_150F\ntest ebp, ebp\njle loc_150F\nmov eax, ebp\nmov rcx, [rsp+58h+var_48]\nmov [rsp+58h+var_3C], r13d\nmov r9d, ebp\nshr eax, 2\nmov [rsp+58h+var_48], r10\nand r9d, 0FFFFFFFCh\nxor r8d, r8d\nshl rax, 4\nlea r14, [rcx+r15*4]\nlea r15d, [rbp-1]\nmov [rsp+58h+nmemb], rax\nnop dword ptr [rax+00000000h]\nloc_1438:\nmov edx, [rcx]\nmov rax, [rsp+58h+nmemb]\ncmp r15d, 2\njbe loc_1578\nloc_1448:\nmovd xmm4, edx\nmovsxd rsi, r8d\npshufd xmm2, xmm4, 0\nlea rdi, [r12+rsi*4]\nxor esi, esi\nmovdqa xmm3, xmm2\npsrlq xmm3, 20h ; ' '\nnop dword ptr [rax+rax+00h]\nloc_1468:\nmovdqu xmm0, xmmword ptr [rbx+rsi]\nmovdqu xmm1, xmmword ptr [rbx+rsi]\npsrlq xmm0, 20h ; ' '\npmuludq xmm1, xmm2\npmuludq xmm0, xmm3\npshufd xmm1, xmm1, 8\npshufd xmm0, xmm0, 8\npunpckldq xmm1, xmm0\nmovups xmmword ptr [rdi+rsi], xmm1\nadd rsi, 10h\ncmp rax, rsi\njnz short loc_1468\ncmp ebp, r9d\njz loc_1560\nmov [rsp+58h+nmemb], rax\nlea edi, [r8+r9]\nmov esi, r9d\nloc_14AE:\nmovsxd r10, esi\nmovsxd rdi, edi\nmov eax, [rbx+r10*4]\nlea r11, ds:0[rdi*4]\nlea r13, ds:0[r10*4]\nimul eax, edx\nmov [r12+rdi*4], eax\nlea edi, [rsi+1]\ncmp edi, ebp\njge short loc_14F5\nmov edi, [rbx+r13+4]\nadd esi, 2\nimul edi, edx\nmov [r12+r11+4], edi\ncmp ebp, esi\njle short loc_14F5\nimul edx, [rbx+r13+8]\nmov [r12+r11+8], edx\nloc_14F5:\nadd rcx, 4\nadd r8d, ebp\ncmp r14, rcx\njnz loc_1438\nloc_1505:\nmov r10, [rsp+58h+var_48]\nmov r13d, [rsp+58h+var_3C]\nloc_150F:\nlea rcx, compare; compar\nmov edx, 4; size\nmov rsi, r10; nmemb\nmov rdi, r12; base\ncall _qsort\ntest r13d, r13d\njle short loc_153F\nmov edx, r13d\nmov rdi, [rsp+58h+dest]; dest\nmov rsi, r12; src\nshl rdx, 2; n\ncall _memcpy\nloc_153F:\nmov rdi, r12; ptr\ncall _free\nmov rax, [rsp+58h+dest]\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1560:\nadd rcx, 4\nadd r8d, ebp\ncmp r14, rcx\njz short loc_1505\nmov edx, [rcx]\njmp loc_1448\nloc_1578:\nmov edi, r8d\nxor esi, esi\njmp loc_14AE", + "ida_pseudo": "void *__fastcall func0(unsigned int *a1, __int64 a2, int a3, int a4, int a5)\n{\n __int64 v5; // r15\n int v8; // r13d\n char *v9; // rax\n size_t v10; // r10\n void *v11; // r12\n unsigned int *v12; // rcx\n unsigned int v13; // r9d\n int v14; // r8d\n unsigned int *v15; // r14\n unsigned int v16; // edx\n __m128i v17; // xmm2\n __int64 v18; // rsi\n __m128i v19; // xmm3\n int v20; // edi\n signed int v21; // esi\n __int64 v22; // r11\n __int64 v23; // r13\n void *dest; // [rsp+8h] [rbp-50h]\n int v26; // [rsp+1Ch] [rbp-3Ch]\n\n v5 = a3;\n v8 = a5;\n dest = malloc(4LL * a5);\n v9 = (char *)malloc(4 * v5 * a4);\n v10 = v5 * a4;\n v11 = v9;\n if ( (int)v5 > 0 && a4 > 0 )\n {\n v12 = a1;\n v26 = v8;\n v13 = a4 & 0xFFFFFFFC;\n v14 = 0;\n v15 = &a1[v5];\n do\n {\n v16 = *v12;\n if ( (unsigned int)(a4 - 1) <= 2 )\n {\n v20 = v14;\n v21 = 0;\n }\n else\n {\n while ( 1 )\n {\n v17 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v16), 0);\n v18 = 0LL;\n v19 = _mm_srli_epi64(v17, 0x20u);\n do\n {\n *(__m128i *)&v9[4 * v14 + v18] = _mm_unpacklo_epi32(\n _mm_shuffle_epi32(\n _mm_mul_epu32(_mm_loadu_si128((const __m128i *)(a2 + v18)), v17),\n 8),\n _mm_shuffle_epi32(\n _mm_mul_epu32(\n _mm_srli_epi64(_mm_loadu_si128((const __m128i *)(a2 + v18)), 0x20u),\n v19),\n 8));\n v18 += 16LL;\n }\n while ( 16LL * ((unsigned int)a4 >> 2) != v18 );\n if ( a4 != v13 )\n break;\n ++v12;\n v14 += a4;\n if ( v15 == v12 )\n goto LABEL_13;\n v16 = *v12;\n }\n v20 = v14 + v13;\n v21 = a4 & 0xFFFFFFFC;\n }\n v22 = 4LL * v20;\n v23 = 4LL * v21;\n *(_DWORD *)&v9[v22] = v16 * *(_DWORD *)(a2 + v23);\n if ( v21 + 1 < a4 )\n {\n *(_DWORD *)&v9[v22 + 4] = v16 * *(_DWORD *)(a2 + v23 + 4);\n if ( a4 > v21 + 2 )\n *(_DWORD *)&v9[v22 + 8] = *(_DWORD *)(a2 + v23 + 8) * v16;\n }\n ++v12;\n v14 += a4;\n }\n while ( v15 != v12 );\nLABEL_13:\n v10 = v5 * a4;\n v8 = v26;\n }\n qsort(v9, v10, 4uLL, compare);\n if ( v8 > 0 )\n memcpy(dest, v11, 4LL * (unsigned int)v8);\n free(v11);\n return dest;\n}", + "ida_strip_asm": "sub_13A0:\nendbr64\npush r15\nmovsxd r15, edx\npush r14\npush r13\npush r12\npush rbp\nmov ebp, ecx\npush rbx\nmov rbx, rsi\nsub rsp, 28h\nmov [rsp+58h+var_48], rdi\nmovsxd rdi, r8d\nmov r13, rdi\nshl rdi, 2; size\ncall _malloc\nmov [rsp+58h+dest], rax\nmovsxd rax, ebp\nimul rax, r15\nlea rdi, ds:0[rax*4]; size\nmov [rsp+58h+nmemb], rax\ncall _malloc\ntest r15d, r15d\nmov r10, [rsp+58h+nmemb]\nmov r12, rax\njle loc_150F\ntest ebp, ebp\njle loc_150F\nmov eax, ebp\nmov rcx, [rsp+58h+var_48]\nmov [rsp+58h+var_3C], r13d\nmov r9d, ebp\nshr eax, 2\nmov [rsp+58h+var_48], r10\nand r9d, 0FFFFFFFCh\nxor r8d, r8d\nshl rax, 4\nlea r14, [rcx+r15*4]\nlea r15d, [rbp-1]\nmov [rsp+58h+nmemb], rax\nnop dword ptr [rax+00000000h]\nloc_1438:\nmov edx, [rcx]\nmov rax, [rsp+58h+nmemb]\ncmp r15d, 2\njbe loc_1578\nloc_1448:\nmovd xmm4, edx\nmovsxd rsi, r8d\npshufd xmm2, xmm4, 0\nlea rdi, [r12+rsi*4]\nxor esi, esi\nmovdqa xmm3, xmm2\npsrlq xmm3, 20h ; ' '\nnop dword ptr [rax+rax+00h]\nloc_1468:\nmovdqu xmm0, xmmword ptr [rbx+rsi]\nmovdqu xmm1, xmmword ptr [rbx+rsi]\npsrlq xmm0, 20h ; ' '\npmuludq xmm1, xmm2\npmuludq xmm0, xmm3\npshufd xmm1, xmm1, 8\npshufd xmm0, xmm0, 8\npunpckldq xmm1, xmm0\nmovups xmmword ptr [rdi+rsi], xmm1\nadd rsi, 10h\ncmp rax, rsi\njnz short loc_1468\ncmp ebp, r9d\njz loc_1560\nmov [rsp+58h+nmemb], rax\nlea edi, [r8+r9]\nmov esi, r9d\nloc_14AE:\nmovsxd r10, esi\nmovsxd rdi, edi\nmov eax, [rbx+r10*4]\nlea r11, ds:0[rdi*4]\nlea r13, ds:0[r10*4]\nimul eax, edx\nmov [r12+rdi*4], eax\nlea edi, [rsi+1]\ncmp edi, ebp\njge short loc_14F5\nmov edi, [rbx+r13+4]\nadd esi, 2\nimul edi, edx\nmov [r12+r11+4], edi\ncmp ebp, esi\njle short loc_14F5\nimul edx, [rbx+r13+8]\nmov [r12+r11+8], edx\nloc_14F5:\nadd rcx, 4\nadd r8d, ebp\ncmp r14, rcx\njnz loc_1438\nloc_1505:\nmov r10, [rsp+58h+var_48]\nmov r13d, [rsp+58h+var_3C]\nloc_150F:\nlea rcx, compar; compar\nmov edx, 4; size\nmov rsi, r10; nmemb\nmov rdi, r12; base\ncall _qsort\ntest r13d, r13d\njle short loc_153F\nmov edx, r13d\nmov rdi, [rsp+58h+dest]; dest\nmov rsi, r12; src\nshl rdx, 2; n\ncall _memcpy\nloc_153F:\nmov rdi, r12; ptr\ncall _free\nmov rax, [rsp+58h+dest]\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1560:\nadd rcx, 4\nadd r8d, ebp\ncmp r14, rcx\njz short loc_1505\nmov edx, [rcx]\njmp loc_1448\nloc_1578:\nmov edi, r8d\nxor esi, esi\njmp loc_14AE", + "ida_strip_pseudo": "void *__fastcall sub_13A0(unsigned int *a1, __int64 a2, int a3, int a4, int a5)\n{\n __int64 v5; // r15\n int v8; // r13d\n char *v9; // rax\n size_t v10; // r10\n void *v11; // r12\n unsigned int *v12; // rcx\n unsigned int v13; // r9d\n int v14; // r8d\n unsigned int *v15; // r14\n unsigned int v16; // edx\n __m128i v17; // xmm2\n __int64 v18; // rsi\n __m128i v19; // xmm3\n int v20; // edi\n signed int v21; // esi\n __int64 v22; // r11\n __int64 v23; // r13\n void *dest; // [rsp+8h] [rbp-50h]\n int v26; // [rsp+1Ch] [rbp-3Ch]\n\n v5 = a3;\n v8 = a5;\n dest = malloc(4LL * a5);\n v9 = (char *)malloc(4 * v5 * a4);\n v10 = v5 * a4;\n v11 = v9;\n if ( (int)v5 > 0 && a4 > 0 )\n {\n v12 = a1;\n v26 = v8;\n v13 = a4 & 0xFFFFFFFC;\n v14 = 0;\n v15 = &a1[v5];\n do\n {\n v16 = *v12;\n if ( (unsigned int)(a4 - 1) <= 2 )\n {\n v20 = v14;\n v21 = 0;\n }\n else\n {\n while ( 1 )\n {\n v17 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v16), 0);\n v18 = 0LL;\n v19 = _mm_srli_epi64(v17, 0x20u);\n do\n {\n *(__m128i *)&v9[4 * v14 + v18] = _mm_unpacklo_epi32(\n _mm_shuffle_epi32(\n _mm_mul_epu32(_mm_loadu_si128((const __m128i *)(a2 + v18)), v17),\n 8),\n _mm_shuffle_epi32(\n _mm_mul_epu32(\n _mm_srli_epi64(_mm_loadu_si128((const __m128i *)(a2 + v18)), 0x20u),\n v19),\n 8));\n v18 += 16LL;\n }\n while ( 16LL * ((unsigned int)a4 >> 2) != v18 );\n if ( a4 != v13 )\n break;\n ++v12;\n v14 += a4;\n if ( v15 == v12 )\n goto LABEL_13;\n v16 = *v12;\n }\n v20 = v14 + v13;\n v21 = a4 & 0xFFFFFFFC;\n }\n v22 = 4LL * v20;\n v23 = 4LL * v21;\n *(_DWORD *)&v9[v22] = v16 * *(_DWORD *)(a2 + v23);\n if ( v21 + 1 < a4 )\n {\n *(_DWORD *)&v9[v22 + 4] = v16 * *(_DWORD *)(a2 + v23 + 4);\n if ( a4 > v21 + 2 )\n *(_DWORD *)&v9[v22 + 8] = *(_DWORD *)(a2 + v23 + 8) * v16;\n }\n ++v12;\n v14 += a4;\n }\n while ( v15 != v12 );\nLABEL_13:\n v10 = v5 * a4;\n v8 = v26;\n }\n qsort(v9, v10, 4uLL, compar);\n if ( v8 > 0 )\n memcpy(dest, v11, 4LL * (unsigned int)v8);\n free(v11);\n return dest;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_13A0(unsigned int *a1, long long a2, int a3, int a4, int a5) {\n long long v5;\n int v8;\n char *v9;\n unsigned int v10;\n void *v11;\n unsigned int *v12;\n unsigned int v13;\n int v14;\n unsigned int *v15;\n unsigned int v16;\n __m128i v17;\n long long v18;\n __m128i v19;\n int v20;\n signed int v21;\n long long v22;\n long long v23;\n void *dest;\n int v26;\n v5 = a3;\n v8 = a5;\n dest = malloc(4LL * a5);\n v9 = (char *)malloc(4 * v5 * a4);\n v10 = v5 * a4;\n v11 = v9;\n if ((int)v5 > 0 && a4 > 0) {\n v12 = a1;\n v26 = v8;\n v13 = a4 & 4294967292;\n v14 = 0;\n v15 = &a1[v5];\n do {\n v16 = *v12;\n if ((unsigned int)(a4 - 1) <= 2) {\n v20 = v14;\n v21 = 0;\n } else {\n while (1) {\n v17 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v16), 0);\n v18 = 0LL;\n v19 = _mm_srli_epi64(v17, 32u);\n do {\n *(__m128i *)&v9[4 * v14 + v18] = _mm_unpacklo_epi32(\n _mm_shuffle_epi32(\n _mm_mul_epu32(_mm_loadu_si128((const __m128i *)(a2 + v18)),\n v17),\n 8),\n _mm_shuffle_epi32(\n _mm_mul_epu32(\n _mm_srli_epi64(\n _mm_loadu_si128((const __m128i *)(a2 + v18)), 32u),\n v19),\n 8));\n v18 += 16LL;\n } while (16LL * ((unsigned int)a4 >> 2) != v18);\n if (a4 != v13) break;\n ++v12;\n v14 += a4;\n if (v15 == v12) goto LABEL_13;\n v16 = *v12;\n }\n v20 = v14 + v13;\n v21 = a4 & 4294967292;\n }\n v22 = 4LL * v20;\n v23 = 4LL * v21;\n *(uint32_t *)&v9[v22] = v16 * *(uint32_t *)(a2 + v23);\n if (v21 + 1 < a4) {\n *(uint32_t *)&v9[v22 + 4] = v16 * *(uint32_t *)(a2 + v23 + 4);\n if (a4 > v21 + 2)\n *(uint32_t *)&v9[v22 + 8] = *(uint32_t *)(a2 + v23 + 8) * v16;\n }\n ++v12;\n v14 += a4;\n } while (v15 != v12);\n LABEL_13:\n v10 = v5 * a4;\n v8 = v26;\n }\n qsort(v9, v10, 4uLL, compar);\n if (v8 > 0) memcpy(dest, v11, 4LL * (unsigned int)v8);\n free(v11);\n return dest;\n}", + "ida_pseudo_norm": "void *func0(unsigned int *a1, long long a2, int a3, int a4, int a5) {\n long long v5;\n int v8;\n char *v9;\n unsigned int v10;\n void *v11;\n unsigned int *v12;\n unsigned int v13;\n int v14;\n unsigned int *v15;\n unsigned int v16;\n __m128i v17;\n long long v18;\n __m128i v19;\n int v20;\n signed int v21;\n long long v22;\n long long v23;\n void *dest;\n int v26;\n v5 = a3;\n v8 = a5;\n dest = malloc(4LL * a5);\n v9 = (char *)malloc(4 * v5 * a4);\n v10 = v5 * a4;\n v11 = v9;\n if ((int)v5 > 0 && a4 > 0) {\n v12 = a1;\n v26 = v8;\n v13 = a4 & 4294967292;\n v14 = 0;\n v15 = &a1[v5];\n do {\n v16 = *v12;\n if ((unsigned int)(a4 - 1) <= 2) {\n v20 = v14;\n v21 = 0;\n } else {\n while (1) {\n v17 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v16), 0);\n v18 = 0LL;\n v19 = _mm_srli_epi64(v17, 32u);\n do {\n *(__m128i *)&v9[4 * v14 + v18] = _mm_unpacklo_epi32(\n _mm_shuffle_epi32(\n _mm_mul_epu32(_mm_loadu_si128((const __m128i *)(a2 + v18)),\n v17),\n 8),\n _mm_shuffle_epi32(\n _mm_mul_epu32(\n _mm_srli_epi64(\n _mm_loadu_si128((const __m128i *)(a2 + v18)), 32u),\n v19),\n 8));\n v18 += 16LL;\n } while (16LL * ((unsigned int)a4 >> 2) != v18);\n if (a4 != v13) break;\n ++v12;\n v14 += a4;\n if (v15 == v12) goto LABEL_13;\n v16 = *v12;\n }\n v20 = v14 + v13;\n v21 = a4 & 4294967292;\n }\n v22 = 4LL * v20;\n v23 = 4LL * v21;\n *(uint32_t *)&v9[v22] = v16 * *(uint32_t *)(a2 + v23);\n if (v21 + 1 < a4) {\n *(uint32_t *)&v9[v22 + 4] = v16 * *(uint32_t *)(a2 + v23 + 4);\n if (a4 > v21 + 2)\n *(uint32_t *)&v9[v22 + 8] = *(uint32_t *)(a2 + v23 + 8) * v16;\n }\n ++v12;\n v14 += a4;\n } while (v15 != v12);\n LABEL_13:\n v10 = v5 * a4;\n v8 = v26;\n }\n qsort(v9, v10, 4uLL, compare);\n if (v8 > 0) memcpy(dest, v11, 4LL * (unsigned int)v8);\n free(v11);\n return dest;\n}" + }, + { + "index": 309, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int a, int b) {\n if (a >= b) {\n return a;\n } else {\n return b;\n }\n}", + "test": "int main() {\n\n assert(func0(5, 10) == 10);\n\n assert(func0(-1, -2) == -1);\n\n assert(func0(9, 7) == 9);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov %esi,-0x8(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x8(%rbp),%eax\njl 1164 \nmov -0x4(%rbp),%eax\njmp 1167 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_8]\njl short loc_1164\nmov eax, [rbp+var_4]\njmp short loc_1167\nloc_1164:\nmov eax, [rbp+var_8]\nloc_1167:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1, unsigned int a2)\n{\n if ( (int)a1 < (int)a2 )\n return a2;\n else\n return a1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_8]\njl short loc_1164\nmov eax, [rbp+var_4]\njmp short loc_1167\nloc_1164:\nmov eax, [rbp+var_8]\nloc_1167:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(unsigned int a1, unsigned int a2)\n{\n if ( (int)a1 < (int)a2 )\n return a2;\n else\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(unsigned int a1, unsigned int a2) {\n if ((int)a1 < (int)a2)\n return a2;\n else\n return a1;\n}", + "ida_pseudo_norm": "long long func0(unsigned int a1, unsigned int a2) {\n if ((int)a1 < (int)a2)\n return a2;\n else\n return a1;\n}" + }, + { + "index": 310, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* str1, char* result) {\n int j = 0;\n for (int i = 0; i < strlen(str1); i++) {\n if (!isspace(str1[i])) {\n result[j++] = str1[i];\n }\n }\n result[j] = '\\0';\n return result;\n}", + "test": "int main() {\n\n char result[100];\n\n\n\n func0(\"python 3.0\", result);\n\n assert(strcmp(result, \"python3.0\") == 0);\n\n\n\n func0(\"item1\", result);\n\n assert(strcmp(result, \"item1\") == 0);\n\n\n\n func0(\"15.10\", result);\n\n assert(strcmp(result, \"15.10\") == 0);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x28,%rsp\nmov %rdi,-0x28(%rbp)\nmov %rsi,-0x30(%rbp)\nmovl $0x0,-0x18(%rbp)\nmovl $0x0,-0x14(%rbp)\njmp 1249 \ncallq 10d0 <__ctype_b_loc@plt>\nmov (%rax),%rax\nmov -0x14(%rbp),%edx\nmovslq %edx,%rcx\nmov -0x28(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rdx),%edx\nmovsbq %dl,%rdx\nadd %rdx,%rdx\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x2000,%eax\ntest %eax,%eax\njne 1245 \nmov -0x14(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x18(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x18(%rbp)\nmovslq %eax,%rdx\nmov -0x30(%rbp),%rax\nadd %rax,%rdx\nmovzbl (%rcx),%eax\nmov %al,(%rdx)\naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\nmovslq %eax,%rbx\nmov -0x28(%rbp),%rax\nmov %rax,%rdi\ncallq 1090 \ncmp %rax,%rbx\njb 11ee \nmov -0x18(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x30(%rbp),%rax\nadd %rdx,%rax\nmovb $0x0,(%rax)\nmov -0x30(%rbp),%rax\nadd $0x28,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+s], rdi\nmov [rbp+var_30], rsi\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp short loc_1249\nloc_11EE:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_14]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 2000h\ntest eax, eax\njnz short loc_1245\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rdx, rax\nmovzx eax, byte ptr [rcx]\nmov [rdx], al\nloc_1245:\nadd [rbp+var_14], 1\nloc_1249:\nmov eax, [rbp+var_14]\nmovsxd rbx, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rbx, rax\njb short loc_11EE\nmov eax, [rbp+var_18]\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+var_30]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, __int64 a2)\n{\n int v2; // eax\n int v4; // [rsp+18h] [rbp-18h]\n int i; // [rsp+1Ch] [rbp-14h]\n\n v4 = 0;\n for ( i = 0; i < strlen(a1); ++i )\n {\n if ( ((*__ctype_b_loc())[a1[i]] & 0x2000) == 0 )\n {\n v2 = v4++;\n *(_BYTE *)(a2 + v2) = a1[i];\n }\n }\n *(_BYTE *)(v4 + a2) = 0;\n return a2;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+s], rdi\nmov [rbp+var_30], rsi\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp short loc_1249\nloc_11EE:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_14]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 2000h\ntest eax, eax\njnz short loc_1245\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rdx, rax\nmovzx eax, byte ptr [rcx]\nmov [rdx], al\nloc_1245:\nadd [rbp+var_14], 1\nloc_1249:\nmov eax, [rbp+var_14]\nmovsxd rbx, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rbx, rax\njb short loc_11EE\nmov eax, [rbp+var_18]\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+var_30]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11C9(const char *a1, __int64 a2)\n{\n int v2; // eax\n int v4; // [rsp+18h] [rbp-18h]\n int i; // [rsp+1Ch] [rbp-14h]\n\n v4 = 0;\n for ( i = 0; i < strlen(a1); ++i )\n {\n if ( ((*__ctype_b_loc())[a1[i]] & 0x2000) == 0 )\n {\n v2 = v4++;\n *(_BYTE *)(a2 + v2) = a1[i];\n }\n }\n *(_BYTE *)(v4 + a2) = 0;\n return a2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11C9(const char *a1, long long a2) {\n int v2;\n int v4;\n int i;\n v4 = 0;\n for (i = 0; i < strlen(a1); ++i) {\n if (((*__ctype_b_loc())[a1[i]] & 8192) == 0) {\n v2 = v4++;\n *(uint8_t *)(a2 + v2) = a1[i];\n }\n }\n *(uint8_t *)(v4 + a2) = 0;\n return a2;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, long long a2) {\n int v2;\n int v4;\n int i;\n v4 = 0;\n for (i = 0; i < strlen(a1); ++i) {\n if (((*__ctype_b_loc())[a1[i]] & 8192) == 0) {\n v2 = v4++;\n *(uint8_t *)(a2 + v2) = a1[i];\n }\n }\n *(uint8_t *)(v4 + a2) = 0;\n return a2;\n}" + }, + { + "index": 310, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* str1, char* result) {\n int j = 0;\n for (int i = 0; i < strlen(str1); i++) {\n if (!isspace(str1[i])) {\n result[j++] = str1[i];\n }\n }\n result[j] = '\\0';\n return result;\n}", + "test": "int main() {\n\n char result[100];\n\n\n\n func0(\"python 3.0\", result);\n\n assert(strcmp(result, \"python3.0\") == 0);\n\n\n\n func0(\"item1\", result);\n\n assert(strcmp(result, \"item1\") == 0);\n\n\n\n func0(\"15.10\", result);\n\n assert(strcmp(result, \"15.10\") == 0);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbp\nmov %rsi,%r15\nmov $0x0,%ebx\nmov $0x0,%r12d\nmov $0xffffffffffffffff,%r14\nmov $0x0,%r13d\njmp 11bf \nadd $0x1,%rbx\nmov %r14,%rcx\nmov %rbp,%rdi\nmov %r13d,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nsub $0x1,%rcx\ncmp %rbx,%rcx\njbe 11ff \ncallq 1090 <__ctype_b_loc@plt>\nmov %rax,%rdx\nmovzbl 0x0(%rbp,%rbx,1),%eax\nmovsbq %al,%rcx\nmov (%rdx),%rdx\ntestb $0x20,0x1(%rdx,%rcx,2)\njne 11bb \nmovslq %r12d,%rdx\nmov %al,(%r15,%rdx,1)\nlea 0x1(%r12),%r12d\njmp 11bb \nmovslq %r12d,%r12\nmovb $0x0,(%r15,%r12,1)\nmov %r15,%rax\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov r13, rsi\nmov ebx, 0\nmov r12d, 0\njmp short loc_11EE\nloc_11EA:\nadd rbx, 1\nloc_11EE:\nmov rdi, rbp; s\ncall _strlen\ncmp rbx, rax\njnb short loc_1225\ncall ___ctype_b_loc\nmov rdx, rax\nmovzx eax, byte ptr [rbp+rbx+0]\nmovsx rcx, al\nmov rdx, [rdx]\ntest byte ptr [rdx+rcx*2+1], 20h\njnz short loc_11EA\nmovsxd rdx, r12d\nmov [r13+rdx+0], al\nlea r12d, [r12+1]\njmp short loc_11EA\nloc_1225:\nmovsxd r12, r12d\nmov byte ptr [r13+r12+0], 0\nmov rax, r13\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "__int64 __fastcall func0(char *s, __int64 a2)\n{\n size_t v2; // rbx\n int v3; // r12d\n const unsigned __int16 **v4; // rdx\n char v5; // al\n\n v2 = 0LL;\n v3 = 0;\n while ( v2 < strlen(s) )\n {\n v4 = __ctype_b_loc();\n v5 = s[v2];\n if ( ((*v4)[v5] & 0x2000) == 0 )\n *(_BYTE *)(a2 + v3++) = v5;\n ++v2;\n }\n *(_BYTE *)(a2 + v3) = 0;\n return a2;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov r13, rsi\nmov ebx, 0\nmov r12d, 0\njmp short loc_11EE\nloc_11EA:\nadd rbx, 1\nloc_11EE:\nmov rdi, rbp; s\ncall _strlen\ncmp rbx, rax\njnb short loc_1225\ncall ___ctype_b_loc\nmov rdx, rax\nmovzx eax, byte ptr [rbp+rbx+0]\nmovsx rcx, al\nmov rdx, [rdx]\ntest byte ptr [rdx+rcx*2+1], 20h\njnz short loc_11EA\nmovsxd rdx, r12d\nmov [r13+rdx+0], al\nlea r12d, [r12+1]\njmp short loc_11EA\nloc_1225:\nmovsxd r12, r12d\nmov byte ptr [r13+r12+0], 0\nmov rax, r13\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11C9(char *s, __int64 a2)\n{\n size_t v2; // rbx\n int v3; // r12d\n const unsigned __int16 **v4; // rdx\n char v5; // al\n\n v2 = 0LL;\n v3 = 0;\n while ( v2 < strlen(s) )\n {\n v4 = __ctype_b_loc();\n v5 = s[v2];\n if ( ((*v4)[v5] & 0x2000) == 0 )\n *(_BYTE *)(a2 + v3++) = v5;\n ++v2;\n }\n *(_BYTE *)(a2 + v3) = 0;\n return a2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11C9(char *s, long long a2) {\n unsigned int v2;\n int v3;\n const unsigned short **v4;\n char v5;\n v2 = 0LL;\n v3 = 0;\n while (v2 < strlen(s)) {\n v4 = __ctype_b_loc();\n v5 = s[v2];\n if (((*v4)[v5] & 8192) == 0) *(uint8_t *)(a2 + v3++) = v5;\n ++v2;\n }\n *(uint8_t *)(a2 + v3) = 0;\n return a2;\n}", + "ida_pseudo_norm": "long long func0(char *s, long long a2) {\n unsigned int v2;\n int v3;\n const unsigned short **v4;\n char v5;\n v2 = 0LL;\n v3 = 0;\n while (v2 < strlen(s)) {\n v4 = __ctype_b_loc();\n v5 = s[v2];\n if (((*v4)[v5] & 8192) == 0) *(uint8_t *)(a2 + v3++) = v5;\n ++v2;\n }\n *(uint8_t *)(a2 + v3) = 0;\n return a2;\n}" + }, + { + "index": 310, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* str1, char* result) {\n int j = 0;\n for (int i = 0; i < strlen(str1); i++) {\n if (!isspace(str1[i])) {\n result[j++] = str1[i];\n }\n }\n result[j] = '\\0';\n return result;\n}", + "test": "int main() {\n\n char result[100];\n\n\n\n func0(\"python 3.0\", result);\n\n assert(strcmp(result, \"python3.0\") == 0);\n\n\n\n func0(\"item1\", result);\n\n assert(strcmp(result, \"item1\") == 0);\n\n\n\n func0(\"15.10\", result);\n\n assert(strcmp(result, \"15.10\") == 0);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmov %rsi,%r15\npush %r14\nxor %r14d,%r14d\npush %r13\nxor %r13d,%r13d\npush %r12\npush %rbp\nmov %rdi,%rbp\npush %rbx\nsub $0x18,%rsp\ncallq 1080 \nmovl $0x0,0xc(%rsp)\nmov %rax,%rbx\njmp 1315 \ncallq 10b0 <__ctype_b_loc@plt>\nmovsbq 0x0(%rbp,%r14,1),%rsi\nmov %rax,%r8\nmov (%r8),%rcx\ntestb $0x20,0x1(%rcx,%rsi,2)\njne 1311 \nmov %sil,(%r12)\nmov %rbp,%rdi\naddl $0x1,0xc(%rsp)\nmovslq 0xc(%rsp),%r13\ncallq 1080 \nmov %rax,%rbx\nadd $0x1,%r14\nlea (%r15,%r13,1),%r12\ncmp %rbx,%r14\njb 12e0 \nmovb $0x0,(%r12)\nadd $0x18,%rsp\nmov %r15,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov r15, rsi\npush r14\nxor r14d, r14d\npush r13\nxor r13d, r13d\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nxor ebx, ebx\nsub rsp, 8\njmp short loc_12FF\nloc_12D8:\ncall ___ctype_b_loc\nmovsx rcx, byte ptr [rbp+rbx+0]\nmov rdx, rax\nmov rdx, [rdx]\ntest byte ptr [rdx+rcx*2+1], 20h\njnz short loc_12FB\nmov [r12], cl\nadd r14d, 1\nmovsxd r13, r14d\nloc_12FB:\nadd rbx, 1\nloc_12FF:\nmov rdi, rbp; s\nlea r12, [r15+r13]\ncall _strlen\ncmp rbx, rax\njb short loc_12D8\nmov byte ptr [r12], 0\nadd rsp, 8\nmov rax, r15\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "__int64 __fastcall func0(char *s, __int64 a2)\n{\n int v2; // r14d\n __int64 v3; // r13\n size_t i; // rbx\n const unsigned __int16 **v5; // rax\n __int64 v6; // rcx\n _BYTE *v7; // r12\n\n v2 = 0;\n v3 = 0LL;\n for ( i = 0LL; ; ++i )\n {\n v7 = (_BYTE *)(a2 + v3);\n if ( i >= strlen(s) )\n break;\n v5 = __ctype_b_loc();\n v6 = s[i];\n if ( ((*v5)[v6] & 0x2000) == 0 )\n {\n *v7 = v6;\n v3 = ++v2;\n }\n }\n *v7 = 0;\n return a2;\n}", + "ida_strip_asm": "sub_12B0:\nendbr64\npush r15\nmov r15, rsi\npush r14\nxor r14d, r14d\npush r13\nxor r13d, r13d\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nxor ebx, ebx\nsub rsp, 8\njmp short loc_12FF\nloc_12D8:\ncall ___ctype_b_loc\nmovsx rcx, byte ptr [rbp+rbx+0]\nmov rdx, rax\nmov rdx, [rdx]\ntest byte ptr [rdx+rcx*2+1], 20h\njnz short loc_12FB\nmov [r12], cl\nadd r14d, 1\nmovsxd r13, r14d\nloc_12FB:\nadd rbx, 1\nloc_12FF:\nmov rdi, rbp; s\nlea r12, [r15+r13]\ncall _strlen\ncmp rbx, rax\njb short loc_12D8\nmov byte ptr [r12], 0\nadd rsp, 8\nmov rax, r15\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12B0(char *s, __int64 a2)\n{\n int v2; // r14d\n __int64 v3; // r13\n size_t i; // rbx\n const unsigned __int16 **v5; // rax\n __int64 v6; // rcx\n _BYTE *v7; // r12\n\n v2 = 0;\n v3 = 0LL;\n for ( i = 0LL; ; ++i )\n {\n v7 = (_BYTE *)(a2 + v3);\n if ( i >= strlen(s) )\n break;\n v5 = __ctype_b_loc();\n v6 = s[i];\n if ( ((*v5)[v6] & 0x2000) == 0 )\n {\n *v7 = v6;\n v3 = ++v2;\n }\n }\n *v7 = 0;\n return a2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12B0(char *s, long long a2) {\n int v2;\n long long v3;\n unsigned int i;\n const unsigned short **v5;\n long long v6;\n uint8_t *v7;\n v2 = 0;\n v3 = 0LL;\n for (i = 0LL;; ++i) {\n v7 = (uint8_t *)(a2 + v3);\n if (i >= strlen(s)) break;\n v5 = __ctype_b_loc();\n v6 = s[i];\n if (((*v5)[v6] & 8192) == 0) {\n *v7 = v6;\n v3 = ++v2;\n }\n }\n *v7 = 0;\n return a2;\n}", + "ida_pseudo_norm": "long long func0(char *s, long long a2) {\n int v2;\n long long v3;\n unsigned int i;\n const unsigned short **v5;\n long long v6;\n uint8_t *v7;\n v2 = 0;\n v3 = 0LL;\n for (i = 0LL;; ++i) {\n v7 = (uint8_t *)(a2 + v3);\n if (i >= strlen(s)) break;\n v5 = __ctype_b_loc();\n v6 = s[i];\n if (((*v5)[v6] & 8192) == 0) {\n *v7 = v6;\n v3 = ++v2;\n }\n }\n *v7 = 0;\n return a2;\n}" + }, + { + "index": 310, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* str1, char* result) {\n int j = 0;\n for (int i = 0; i < strlen(str1); i++) {\n if (!isspace(str1[i])) {\n result[j++] = str1[i];\n }\n }\n result[j] = '\\0';\n return result;\n}", + "test": "int main() {\n\n char result[100];\n\n\n\n func0(\"python 3.0\", result);\n\n assert(strcmp(result, \"python3.0\") == 0);\n\n\n\n func0(\"item1\", result);\n\n assert(strcmp(result, \"item1\") == 0);\n\n\n\n func0(\"15.10\", result);\n\n assert(strcmp(result, \"15.10\") == 0);\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmov %rdi,%r15\npush %r14\npush %r13\npush %r12\nmov %rsi,%r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\ncallq 1080 \ntest %rax,%rax\nje 1348 \nmov %rax,%r13\nxor %ebx,%ebx\nxor %r14d,%r14d\ncallq 10b0 <__ctype_b_loc@plt>\nmov %r12,%rdx\nmov %rax,%rbp\njmp 1310 \nnopw 0x0(%rax,%rax,1)\nmov %cl,(%rdx)\nadd $0x1,%r14d\nmov %r15,%rdi\nadd $0x1,%rbx\ncallq 1080 \nmovslq %r14d,%rdx\nmov %rax,%r13\nadd %r12,%rdx\ncmp %rax,%rbx\njae 132f \nmov 0x0(%rbp),%rsi\nmovsbq (%r15,%rbx,1),%rcx\ntestb $0x20,0x1(%rsi,%rcx,2)\nje 12f0 \nmovslq %r14d,%rdx\nadd $0x1,%rbx\nadd %r12,%rdx\ncmp %r13,%rbx\njb 1314 \nmovb $0x0,(%rdx)\nadd $0x8,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\nmov %r12,%rdx\njmp 132f \nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov r15, rsi\npush r14\nxor r14d, r14d\npush r13\nxor r13d, r13d\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nxor ebx, ebx\nsub rsp, 8\njmp short loc_12FF\nloc_12D8:\ncall ___ctype_b_loc\nmovsx rcx, byte ptr [rbp+rbx+0]\nmov rdx, rax\nmov rdx, [rdx]\ntest byte ptr [rdx+rcx*2+1], 20h\njnz short loc_12FB\nmov [r12], cl\nadd r14d, 1\nmovsxd r13, r14d\nloc_12FB:\nadd rbx, 1\nloc_12FF:\nmov rdi, rbp; s\nlea r12, [r15+r13]\ncall _strlen\ncmp rbx, rax\njb short loc_12D8\nmov byte ptr [r12], 0\nadd rsp, 8\nmov rax, r15\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "__int64 __fastcall func0(char *s, __int64 a2)\n{\n int v2; // r14d\n __int64 v3; // r13\n size_t i; // rbx\n const unsigned __int16 **v5; // rax\n __int64 v6; // rcx\n _BYTE *v7; // r12\n\n v2 = 0;\n v3 = 0LL;\n for ( i = 0LL; ; ++i )\n {\n v7 = (_BYTE *)(a2 + v3);\n if ( i >= strlen(s) )\n break;\n v5 = __ctype_b_loc();\n v6 = s[i];\n if ( ((*v5)[v6] & 0x2000) == 0 )\n {\n *v7 = v6;\n v3 = ++v2;\n }\n }\n *v7 = 0;\n return a2;\n}", + "ida_strip_asm": "sub_12B0:\nendbr64\npush r15\nmov r15, rsi\npush r14\nxor r14d, r14d\npush r13\nxor r13d, r13d\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nxor ebx, ebx\nsub rsp, 8\njmp short loc_12FF\nloc_12D8:\ncall ___ctype_b_loc\nmovsx rcx, byte ptr [rbp+rbx+0]\nmov rdx, rax\nmov rdx, [rdx]\ntest byte ptr [rdx+rcx*2+1], 20h\njnz short loc_12FB\nmov [r12], cl\nadd r14d, 1\nmovsxd r13, r14d\nloc_12FB:\nadd rbx, 1\nloc_12FF:\nmov rdi, rbp; s\nlea r12, [r15+r13]\ncall _strlen\ncmp rbx, rax\njb short loc_12D8\nmov byte ptr [r12], 0\nadd rsp, 8\nmov rax, r15\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12B0(char *s, __int64 a2)\n{\n int v2; // r14d\n __int64 v3; // r13\n size_t i; // rbx\n const unsigned __int16 **v5; // rax\n __int64 v6; // rcx\n _BYTE *v7; // r12\n\n v2 = 0;\n v3 = 0LL;\n for ( i = 0LL; ; ++i )\n {\n v7 = (_BYTE *)(a2 + v3);\n if ( i >= strlen(s) )\n break;\n v5 = __ctype_b_loc();\n v6 = s[i];\n if ( ((*v5)[v6] & 0x2000) == 0 )\n {\n *v7 = v6;\n v3 = ++v2;\n }\n }\n *v7 = 0;\n return a2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12B0(char *s, long long a2) {\n int v2;\n long long v3;\n unsigned int i;\n const unsigned short **v5;\n long long v6;\n uint8_t *v7;\n v2 = 0;\n v3 = 0LL;\n for (i = 0LL;; ++i) {\n v7 = (uint8_t *)(a2 + v3);\n if (i >= strlen(s)) break;\n v5 = __ctype_b_loc();\n v6 = s[i];\n if (((*v5)[v6] & 8192) == 0) {\n *v7 = v6;\n v3 = ++v2;\n }\n }\n *v7 = 0;\n return a2;\n}", + "ida_pseudo_norm": "long long func0(char *s, long long a2) {\n int v2;\n long long v3;\n unsigned int i;\n const unsigned short **v5;\n long long v6;\n uint8_t *v7;\n v2 = 0;\n v3 = 0LL;\n for (i = 0LL;; ++i) {\n v7 = (uint8_t *)(a2 + v3);\n if (i >= strlen(s)) break;\n v5 = __ctype_b_loc();\n v6 = s[i];\n if (((*v5)[v6] & 8192) == 0) {\n *v7 = v6;\n v3 = ++v2;\n }\n }\n *v7 = 0;\n return a2;\n}" + }, + { + "index": 311, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (!(n & (n + 1))) {\n return n;\n }\n int pos = 0, temp = n, count = 0;\n while (temp) {\n if (!(temp & 1)) {\n pos = count;\n }\n count++;\n temp >>= 1;\n }\n return (n | (1 << pos));\n}", + "test": "int main() {\n\n assert(func0(10) == 14);\n\n assert(func0(12) == 14);\n\n assert(func0(15) == 15);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov -0x14(%rbp),%eax\nadd $0x1,%eax\nand -0x14(%rbp),%eax\ntest %eax,%eax\njne 1166 \nmov -0x14(%rbp),%eax\njmp 11aa \nmovl $0x0,-0xc(%rbp)\nmov -0x14(%rbp),%eax\nmov %eax,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 1193 \nmov -0x8(%rbp),%eax\nand $0x1,%eax\ntest %eax,%eax\njne 118c \nmov -0x4(%rbp),%eax\nmov %eax,-0xc(%rbp)\naddl $0x1,-0x4(%rbp)\nsarl -0x8(%rbp)\ncmpl $0x0,-0x8(%rbp)\njne 117c \nmov -0xc(%rbp),%eax\nmov $0x1,%edx\nmov %eax,%ecx\nshl %cl,%edx\nmov %edx,%eax\nor -0x14(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov eax, [rbp+var_14]\nadd eax, 1\nand eax, [rbp+var_14]\ntest eax, eax\njnz short loc_1166\nmov eax, [rbp+var_14]\njmp short loc_11AA\nloc_1166:\nmov [rbp+var_C], 0\nmov eax, [rbp+var_14]\nmov [rbp+var_8], eax\nmov [rbp+var_4], 0\njmp short loc_1193\nloc_117C:\nmov eax, [rbp+var_8]\nand eax, 1\ntest eax, eax\njnz short loc_118C\nmov eax, [rbp+var_4]\nmov [rbp+var_C], eax\nloc_118C:\nadd [rbp+var_4], 1\nsar [rbp+var_8], 1\nloc_1193:\ncmp [rbp+var_8], 0\njnz short loc_117C\nmov eax, [rbp+var_C]\nmov edx, 1\nmov ecx, eax\nshl edx, cl\nmov eax, edx\nor eax, [rbp+var_14]\nloc_11AA:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1)\n{\n char v2; // [rsp+8h] [rbp-Ch]\n int v3; // [rsp+Ch] [rbp-8h]\n char v4; // [rsp+10h] [rbp-4h]\n\n if ( (a1 & (a1 + 1)) == 0 )\n return a1;\n v2 = 0;\n v3 = a1;\n v4 = 0;\n while ( v3 )\n {\n if ( (v3 & 1) == 0 )\n v2 = v4;\n ++v4;\n v3 >>= 1;\n }\n return a1 | (1 << v2);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov eax, [rbp+var_14]\nadd eax, 1\nand eax, [rbp+var_14]\ntest eax, eax\njnz short loc_1166\nmov eax, [rbp+var_14]\njmp short loc_11AA\nloc_1166:\nmov [rbp+var_C], 0\nmov eax, [rbp+var_14]\nmov [rbp+var_8], eax\nmov [rbp+var_4], 0\njmp short loc_1193\nloc_117C:\nmov eax, [rbp+var_8]\nand eax, 1\ntest eax, eax\njnz short loc_118C\nmov eax, [rbp+var_4]\nmov [rbp+var_C], eax\nloc_118C:\nadd [rbp+var_4], 1\nsar [rbp+var_8], 1\nloc_1193:\ncmp [rbp+var_8], 0\njnz short loc_117C\nmov eax, [rbp+var_C]\nmov edx, 1\nmov ecx, eax\nshl edx, cl\nmov eax, edx\nor eax, [rbp+var_14]\nloc_11AA:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(unsigned int a1)\n{\n char v2; // [rsp+8h] [rbp-Ch]\n int v3; // [rsp+Ch] [rbp-8h]\n char v4; // [rsp+10h] [rbp-4h]\n\n if ( (a1 & (a1 + 1)) == 0 )\n return a1;\n v2 = 0;\n v3 = a1;\n v4 = 0;\n while ( v3 )\n {\n if ( (v3 & 1) == 0 )\n v2 = v4;\n ++v4;\n v3 >>= 1;\n }\n return a1 | (1 << v2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(unsigned int a1) {\n char v2;\n int v3;\n char v4;\n if ((a1 & (a1 + 1)) == 0) return a1;\n v2 = 0;\n v3 = a1;\n v4 = 0;\n while (v3) {\n if ((v3 & 1) == 0) v2 = v4;\n ++v4;\n v3 >>= 1;\n }\n return a1 | (1 << v2);\n}", + "ida_pseudo_norm": "long long func0(unsigned int a1) {\n char v2;\n int v3;\n char v4;\n if ((a1 & (a1 + 1)) == 0) return a1;\n v2 = 0;\n v3 = a1;\n v4 = 0;\n while (v3) {\n if ((v3 & 1) == 0) v2 = v4;\n ++v4;\n v3 >>= 1;\n }\n return a1 | (1 << v2);\n}" + }, + { + "index": 311, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (!(n & (n + 1))) {\n return n;\n }\n int pos = 0, temp = n, count = 0;\n while (temp) {\n if (!(temp & 1)) {\n pos = count;\n }\n count++;\n temp >>= 1;\n }\n return (n | (1 << pos));\n}", + "test": "int main() {\n\n assert(func0(10) == 14);\n\n assert(func0(12) == 14);\n\n assert(func0(15) == 15);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nlea 0x1(%rdi),%edx\nmov %edi,%eax\ntest %edi,%edx\nje 1171 \nmov $0x0,%edx\nmov $0x0,%ecx\ntest $0x1,%al\ncmove %edx,%ecx\nadd $0x1,%edx\nsar %eax\njne 1160 \nmov %edi,%eax\nbts %ecx,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nlea edx, [rdi+1]\nmov eax, edi\ntest edx, edi\njz short locret_1171\nmov edx, 0\nmov ecx, 0\nloc_1160:\ntest al, 1\ncmovz ecx, edx\nadd edx, 1\nsar eax, 1\njnz short loc_1160\nmov eax, edi\nbts eax, ecx\nlocret_1171:\nretn", + "ida_pseudo": "int __fastcall func0(int a1)\n{\n int result; // eax\n char v2; // dl\n char v3; // cl\n\n result = a1;\n if ( (a1 & (a1 + 1)) != 0 )\n {\n v2 = 0;\n v3 = 0;\n do\n {\n if ( (result & 1) == 0 )\n v3 = v2;\n ++v2;\n result >>= 1;\n }\n while ( result );\n return a1 | (1 << v3);\n }\n return result;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nlea edx, [rdi+1]\nmov eax, edi\ntest edx, edi\njz short locret_1171\nmov edx, 0\nmov ecx, 0\nloc_1160:\ntest al, 1\ncmovz ecx, edx\nadd edx, 1\nsar eax, 1\njnz short loc_1160\nmov eax, edi\nbts eax, ecx\nlocret_1171:\nretn", + "ida_strip_pseudo": "int __fastcall sub_1149(int a1)\n{\n int result; // eax\n char v2; // dl\n char v3; // cl\n\n result = a1;\n if ( (a1 & (a1 + 1)) != 0 )\n {\n v2 = 0;\n v3 = 0;\n do\n {\n if ( (result & 1) == 0 )\n v3 = v2;\n ++v2;\n result >>= 1;\n }\n while ( result );\n return a1 | (1 << v3);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "int sub_1149(int a1) {\n int result;\n char v2;\n char v3;\n result = a1;\n if ((a1 & (a1 + 1)) != 0) {\n v2 = 0;\n v3 = 0;\n do {\n if ((result & 1) == 0) v3 = v2;\n ++v2;\n result >>= 1;\n } while (result);\n return a1 | (1 << v3);\n }\n return result;\n}", + "ida_pseudo_norm": "int func0(int a1) {\n int result;\n char v2;\n char v3;\n result = a1;\n if ((a1 & (a1 + 1)) != 0) {\n v2 = 0;\n v3 = 0;\n do {\n if ((result & 1) == 0) v3 = v2;\n ++v2;\n result >>= 1;\n } while (result);\n return a1 | (1 << v3);\n }\n return result;\n}" + }, + { + "index": 312, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(double r, double h) {\n double volume = (1.0 / 3) * M_PI * r * r * h;\n return volume;\n}", + "test": "int main() {\n\n assert(func0(5, 12) == 314.15926535897927);\n\n assert(func0(10, 15) == 1570.7963267948965);\n\n assert(func0(19, 17) == 6426.651371693521);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmovsd %xmm0,-0x18(%rbp)\nmovsd %xmm1,-0x20(%rbp)\nmovsd -0x18(%rbp),%xmm1\nmovsd 0xf58(%rip),%xmm0\nmulsd %xmm1,%xmm0\nmulsd -0x18(%rbp),%xmm0\nmovsd -0x20(%rbp),%xmm1\nmulsd %xmm1,%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmovsd -0x8(%rbp),%xmm0\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmovsd [rbp+var_18], xmm0\nmovsd [rbp+var_20], xmm1\nmovsd xmm1, [rbp+var_18]\nmovsd xmm0, cs:qword_20A0\nmulsd xmm0, xmm1\nmulsd xmm0, [rbp+var_18]\nmovsd xmm1, [rbp+var_20]\nmulsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "double __fastcall func0(double a1, double a2)\n{\n return 1.047197551196598 * a1 * a1 * a2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmovsd [rbp+var_18], xmm0\nmovsd [rbp+var_20], xmm1\nmovsd xmm1, [rbp+var_18]\nmovsd xmm0, cs:qword_20A0\nmulsd xmm0, xmm1\nmulsd xmm0, [rbp+var_18]\nmovsd xmm1, [rbp+var_20]\nmulsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "double __fastcall sub_1149(double a1, double a2)\n{\n return 1.047197551196598 * a1 * a1 * a2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1149(double a1, double a2) {\n return 1.047197551196598 * a1 * a1 * a2;\n}", + "ida_pseudo_norm": "double func0(double a1, double a2) { return 1.047197551196598 * a1 * a1 * a2; }" + }, + { + "index": 313, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int* list1, size_t size) {\n for (int i = 0; i < size; i++) {\n if (list1[i] >= 0) {\n return list1[i];\n }\n }\n return -1;\n}", + "test": "int main() {\n\n int list1[] = {-1, -2, 1, 2};\n\n assert(func0(list1, sizeof(list1)/sizeof(list1[0])) == 1);\n\n\n\n int list2[] = {3, 4, -5};\n\n assert(func0(list2, sizeof(list2)/sizeof(list2[0])) == 3);\n\n\n\n int list3[] = {-2, -3, 1};\n\n assert(func0(list3, sizeof(list3)/sizeof(list3[0])) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11b8 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ntest %eax,%eax\njs 11b4 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\njmp 11c8 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncltq\ncmp %rax,-0x20(%rbp)\nja 1182 \nmov $0xffffffff,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_4], 0\njmp short loc_11B8\nloc_1182:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njs short loc_11B4\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\njmp short loc_11C8\nloc_11B4:\nadd [rbp+var_4], 1\nloc_11B8:\nmov eax, [rbp+var_4]\ncdqe\ncmp rax, [rbp+var_20]\njb short loc_1182\nmov eax, 0FFFFFFFFh\nloc_11C8:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, unsigned __int64 a2)\n{\n int i; // [rsp+1Ch] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n if ( *(int *)(4LL * i + a1) >= 0 )\n return *(unsigned int *)(4LL * i + a1);\n }\n return 0xFFFFFFFFLL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_4], 0\njmp short loc_11B8\nloc_1182:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njs short loc_11B4\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\njmp short loc_11C8\nloc_11B4:\nadd [rbp+var_4], 1\nloc_11B8:\nmov eax, [rbp+var_4]\ncdqe\ncmp rax, [rbp+var_20]\njb short loc_1182\nmov eax, 0FFFFFFFFh\nloc_11C8:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, unsigned __int64 a2)\n{\n int i; // [rsp+1Ch] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n if ( *(int *)(4LL * i + a1) >= 0 )\n return *(unsigned int *)(4LL * i + a1);\n }\n return 0xFFFFFFFFLL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, unsigned long long a2) {\n int i;\n for (i = 0; i < a2; ++i) {\n if (*(int *)(4LL * i + a1) >= 0) return *(unsigned int *)(4LL * i + a1);\n }\n return 4294967295LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, unsigned long long a2) {\n int i;\n for (i = 0; i < a2; ++i) {\n if (*(int *)(4LL * i + a1) >= 0) return *(unsigned int *)(4LL * i + a1);\n }\n return 4294967295LL;\n}" + }, + { + "index": 313, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int* list1, size_t size) {\n for (int i = 0; i < size; i++) {\n if (list1[i] >= 0) {\n return list1[i];\n }\n }\n return -1;\n}", + "test": "int main() {\n\n int list1[] = {-1, -2, 1, 2};\n\n assert(func0(list1, sizeof(list1)/sizeof(list1[0])) == 1);\n\n\n\n int list2[] = {3, 4, -5};\n\n assert(func0(list2, sizeof(list2)/sizeof(list2[0])) == 3);\n\n\n\n int list3[] = {-2, -3, 1};\n\n assert(func0(list3, sizeof(list3)/sizeof(list3[0])) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %rsi,%rsi\nje 118f \nmov $0x0,%eax\nmov (%rdi,%rax,4),%edx\ntest %edx,%edx\njns 118c \nadd $0x1,%rax\ncmp %rax,%rsi\njne 1177 \nmov $0xffffffff,%edx\nmov %edx,%eax\nretq\nmov $0xffffffff,%edx\njmp 118c \n", + "ida_asm": "func0:\nendbr64\ntest rsi, rsi\njz short loc_118F\nmov eax, 0\nloc_1177:\nmov edx, [rdi+rax*4]\ntest edx, edx\njns short loc_118C\nadd rax, 1\ncmp rsi, rax\njnz short loc_1177\nmov edx, 0FFFFFFFFh\nloc_118C:\nmov eax, edx\nretn\nloc_118F:\nmov edx, 0FFFFFFFFh\njmp short loc_118C", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2)\n{\n __int64 v2; // rax\n int v3; // edx\n\n if ( a2 )\n {\n v2 = 0LL;\n while ( 1 )\n {\n v3 = *(_DWORD *)(a1 + 4 * v2);\n if ( v3 >= 0 )\n break;\n if ( a2 == ++v2 )\n return (unsigned int)-1;\n }\n }\n else\n {\n return (unsigned int)-1;\n }\n return (unsigned int)v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest rsi, rsi\njz short loc_118F\nmov eax, 0\nloc_1177:\nmov edx, [rdi+rax*4]\ntest edx, edx\njns short loc_118C\nadd rax, 1\ncmp rsi, rax\njnz short loc_1177\nmov edx, 0FFFFFFFFh\nloc_118C:\nmov eax, edx\nretn\nloc_118F:\nmov edx, 0FFFFFFFFh\njmp short loc_118C", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2)\n{\n __int64 v2; // rax\n int v3; // edx\n\n if ( a2 )\n {\n v2 = 0LL;\n while ( 1 )\n {\n v3 = *(_DWORD *)(a1 + 4 * v2);\n if ( v3 >= 0 )\n break;\n if ( a2 == ++v2 )\n return (unsigned int)-1;\n }\n }\n else\n {\n return (unsigned int)-1;\n }\n return (unsigned int)v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2) {\n long long v2;\n int v3;\n if (a2) {\n v2 = 0LL;\n while (1) {\n v3 = *(uint32_t *)(a1 + 4 * v2);\n if (v3 >= 0) break;\n if (a2 == ++v2) return (unsigned int)-1;\n }\n } else {\n return (unsigned int)-1;\n }\n return (unsigned int)v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2) {\n long long v2;\n int v3;\n if (a2) {\n v2 = 0LL;\n while (1) {\n v3 = *(uint32_t *)(a1 + 4 * v2);\n if (v3 >= 0) break;\n if (a2 == ++v2) return (unsigned int)-1;\n }\n } else {\n return (unsigned int)-1;\n }\n return (unsigned int)v3;\n}" + }, + { + "index": 314, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int grid[2][100], int n) {\n int incl = grid[0][0] > grid[1][0] ? grid[0][0] : grid[1][0];\n int excl = 0;\n for (int i = 1; i < n; i++) {\n int excl_new = excl > incl ? excl : incl;\n int max_value = grid[0][i] > grid[1][i] ? grid[0][i] : grid[1][i];\n incl = excl + max_value;\n excl = excl_new;\n }\n return excl > incl ? excl : incl;\n}", + "test": "int main() {\n\n int grid1[2][100] = {{1, 4, 5}, {2, 0, 0}};\n\n assert(func0(grid1, 3) == 7);\n\n\n\n int grid2[2][100] = {{1, 2, 3, 4, 5}, {6, 7, 8, 9, 10}};\n\n assert(func0(grid2, 5) == 24);\n\n\n\n int grid3[2][100] = {{7, 9, 11, 15, 19}, {21, 25, 28, 31, 32}};\n\n assert(func0(grid3, 5) == 81);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmov -0x28(%rbp),%rax\nadd $0x190,%rax\nmov (%rax),%edx\nmov -0x28(%rbp),%rax\nmov (%rax),%eax\ncmp %eax,%edx\ncmovge %edx,%eax\nmov %eax,-0x14(%rbp)\nmovl $0x0,-0x10(%rbp)\nmovl $0x1,-0xc(%rbp)\njmp 11ec \nmov -0x10(%rbp),%eax\ncmp %eax,-0x14(%rbp)\ncmovge -0x14(%rbp),%eax\nmov %eax,-0x8(%rbp)\nmov -0x28(%rbp),%rax\nlea 0x190(%rax),%rdx\nmov -0xc(%rbp),%eax\ncltq\nmov (%rdx,%rax,4),%edx\nmov -0x28(%rbp),%rax\nmov -0xc(%rbp),%ecx\nmovslq %ecx,%rcx\nmov (%rax,%rcx,4),%eax\ncmp %eax,%edx\ncmovge %edx,%eax\nmov %eax,-0x4(%rbp)\nmov -0x10(%rbp),%edx\nmov -0x4(%rbp),%eax\nadd %edx,%eax\nmov %eax,-0x14(%rbp)\nmov -0x8(%rbp),%eax\nmov %eax,-0x10(%rbp)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 11a2 \nmov -0x10(%rbp),%eax\ncmp %eax,-0x14(%rbp)\ncmovge -0x14(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov rax, [rbp+var_28]\nadd rax, 190h\nmov edx, [rax]\nmov rax, [rbp+var_28]\nmov eax, [rax]\ncmp edx, eax\ncmovge eax, edx\nmov [rbp+var_14], eax\nmov [rbp+var_10], 0\nmov [rbp+var_C], 1\njmp short loc_11ED\nloc_11A2:\nmov edx, [rbp+var_14]\nmov eax, [rbp+var_10]\ncmp edx, eax\ncmovge eax, edx\nmov [rbp+var_8], eax\nmov rax, [rbp+var_28]\nlea rdx, [rax+190h]\nmov eax, [rbp+var_C]\ncdqe\nmov edx, [rdx+rax*4]\nmov rax, [rbp+var_28]\nmov ecx, [rbp+var_C]\nmovsxd rcx, ecx\nmov eax, [rax+rcx*4]\ncmp edx, eax\ncmovge eax, edx\nmov [rbp+var_4], eax\nmov edx, [rbp+var_10]\nmov eax, [rbp+var_4]\nadd eax, edx\nmov [rbp+var_14], eax\nmov eax, [rbp+var_8]\nmov [rbp+var_10], eax\nadd [rbp+var_C], 1\nloc_11ED:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_2C]\njl short loc_11A2\nmov edx, [rbp+var_14]\nmov eax, [rbp+var_10]\ncmp edx, eax\ncmovge eax, edx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int v2; // eax\n int v3; // eax\n int v4; // eax\n __int64 result; // rax\n signed int v6; // [rsp+18h] [rbp-14h]\n signed int v7; // [rsp+1Ch] [rbp-10h]\n int i; // [rsp+20h] [rbp-Ch]\n int v9; // [rsp+24h] [rbp-8h]\n\n v2 = *a1;\n if ( a1[100] >= *a1 )\n v2 = a1[100];\n v6 = v2;\n v7 = 0;\n for ( i = 1; i < a2; ++i )\n {\n v3 = v7;\n if ( v6 >= v7 )\n v3 = v6;\n v9 = v3;\n v4 = a1[i];\n if ( a1[i + 100] >= v4 )\n v4 = a1[i + 100];\n v6 = v7 + v4;\n v7 = v9;\n }\n result = (unsigned int)v7;\n if ( v6 >= v7 )\n return (unsigned int)v6;\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov rax, [rbp+var_28]\nadd rax, 190h\nmov edx, [rax]\nmov rax, [rbp+var_28]\nmov eax, [rax]\ncmp edx, eax\ncmovge eax, edx\nmov [rbp+var_14], eax\nmov [rbp+var_10], 0\nmov [rbp+var_C], 1\njmp short loc_11ED\nloc_11A2:\nmov edx, [rbp+var_14]\nmov eax, [rbp+var_10]\ncmp edx, eax\ncmovge eax, edx\nmov [rbp+var_8], eax\nmov rax, [rbp+var_28]\nlea rdx, [rax+190h]\nmov eax, [rbp+var_C]\ncdqe\nmov edx, [rdx+rax*4]\nmov rax, [rbp+var_28]\nmov ecx, [rbp+var_C]\nmovsxd rcx, ecx\nmov eax, [rax+rcx*4]\ncmp edx, eax\ncmovge eax, edx\nmov [rbp+var_4], eax\nmov edx, [rbp+var_10]\nmov eax, [rbp+var_4]\nadd eax, edx\nmov [rbp+var_14], eax\nmov eax, [rbp+var_8]\nmov [rbp+var_10], eax\nadd [rbp+var_C], 1\nloc_11ED:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_2C]\njl short loc_11A2\nmov edx, [rbp+var_14]\nmov eax, [rbp+var_10]\ncmp edx, eax\ncmovge eax, edx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int *a1, int a2)\n{\n int v2; // eax\n int v3; // eax\n int v4; // eax\n __int64 result; // rax\n signed int v6; // [rsp+18h] [rbp-14h]\n signed int v7; // [rsp+1Ch] [rbp-10h]\n int i; // [rsp+20h] [rbp-Ch]\n int v9; // [rsp+24h] [rbp-8h]\n\n v2 = *a1;\n if ( a1[100] >= *a1 )\n v2 = a1[100];\n v6 = v2;\n v7 = 0;\n for ( i = 1; i < a2; ++i )\n {\n v3 = v7;\n if ( v6 >= v7 )\n v3 = v6;\n v9 = v3;\n v4 = a1[i];\n if ( a1[i + 100] >= v4 )\n v4 = a1[i + 100];\n v6 = v7 + v4;\n v7 = v9;\n }\n result = (unsigned int)v7;\n if ( v6 >= v7 )\n return (unsigned int)v6;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int *a1, int a2) {\n int v2;\n int v3;\n int v4;\n long long result;\n signed int v6;\n signed int v7;\n int i;\n int v9;\n v2 = *a1;\n if (a1[100] >= *a1) v2 = a1[100];\n v6 = v2;\n v7 = 0;\n for (i = 1; i < a2; ++i) {\n v3 = v7;\n if (v6 >= v7) v3 = v6;\n v9 = v3;\n v4 = a1[i];\n if (a1[i + 100] >= v4) v4 = a1[i + 100];\n v6 = v7 + v4;\n v7 = v9;\n }\n result = (unsigned int)v7;\n if (v6 >= v7) return (unsigned int)v6;\n return result;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int v2;\n int v3;\n int v4;\n long long result;\n signed int v6;\n signed int v7;\n int i;\n int v9;\n v2 = *a1;\n if (a1[100] >= *a1) v2 = a1[100];\n v6 = v2;\n v7 = 0;\n for (i = 1; i < a2; ++i) {\n v3 = v7;\n if (v6 >= v7) v3 = v6;\n v9 = v3;\n v4 = a1[i];\n if (a1[i + 100] >= v4) v4 = a1[i + 100];\n v6 = v7 + v4;\n v7 = v9;\n }\n result = (unsigned int)v7;\n if (v6 >= v7) return (unsigned int)v6;\n return result;\n}" + }, + { + "index": 314, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int grid[2][100], int n) {\n int incl = grid[0][0] > grid[1][0] ? grid[0][0] : grid[1][0];\n int excl = 0;\n for (int i = 1; i < n; i++) {\n int excl_new = excl > incl ? excl : incl;\n int max_value = grid[0][i] > grid[1][i] ? grid[0][i] : grid[1][i];\n incl = excl + max_value;\n excl = excl_new;\n }\n return excl > incl ? excl : incl;\n}", + "test": "int main() {\n\n int grid1[2][100] = {{1, 4, 5}, {2, 0, 0}};\n\n assert(func0(grid1, 3) == 7);\n\n\n\n int grid2[2][100] = {{1, 2, 3, 4, 5}, {6, 7, 8, 9, 10}};\n\n assert(func0(grid2, 5) == 24);\n\n\n\n int grid3[2][100] = {{7, 9, 11, 15, 19}, {21, 25, 28, 31, 32}};\n\n assert(func0(grid3, 5) == 81);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov (%rdi),%eax\ncmp %eax,0x190(%rdi)\ncmovge 0x190(%rdi),%eax\ncmp $0x1,%esi\njle 11b9 \nlea 0x4(%rdi),%rdx\nlea -0x2(%rsi),%ecx\nlea 0x8(%rdi,%rcx,4),%rdi\nmov $0x0,%ecx\nmov %ecx,%esi\ncmp %eax,%ecx\ncmovl %eax,%ecx\nmov (%rdx),%eax\ncmp %eax,0x190(%rdx)\ncmovge 0x190(%rdx),%eax\nadd %esi,%eax\nadd $0x4,%rdx\ncmp %rdi,%rdx\njne 1192 \ncmp %ecx,%eax\ncmovl %ecx,%eax\nretq\nmov $0x0,%ecx\njmp 11b3 \n", + "ida_asm": "func0:\nendbr64\nmov eax, [rdi+190h]\nmov edx, [rdi]\ncmp eax, edx\ncmovl eax, edx\ncmp esi, 1\njle short loc_11B5\nlea rdx, [rdi+4]\nlea ecx, [rsi-2]\nlea r8, [rdi+rcx*4+8]\nmov ecx, 0\nloc_1190:\nmov edi, ecx\ncmp ecx, eax\ncmovl ecx, eax\nmov eax, [rdx+190h]\nmov esi, [rdx]\ncmp eax, esi\ncmovl eax, esi\nadd eax, edi\nadd rdx, 4\ncmp rdx, r8\njnz short loc_1190\nloc_11AF:\ncmp eax, ecx\ncmovl eax, ecx\nretn\nloc_11B5:\nmov ecx, 0\njmp short loc_11AF", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n __int64 result; // rax\n int *v3; // rdx\n __int64 v4; // r8\n int v5; // ecx\n int v6; // edi\n int v7; // eax\n\n result = (unsigned int)a1[100];\n if ( (int)result < *a1 )\n result = (unsigned int)*a1;\n if ( a2 <= 1 )\n {\n v5 = 0;\n }\n else\n {\n v3 = a1 + 1;\n v4 = (__int64)&a1[a2 - 2 + 2];\n v5 = 0;\n do\n {\n v6 = v5;\n if ( v5 < (int)result )\n v5 = result;\n v7 = v3[100];\n if ( v7 < *v3 )\n v7 = *v3;\n result = (unsigned int)(v6 + v7);\n ++v3;\n }\n while ( v3 != (int *)v4 );\n }\n if ( (int)result < v5 )\n return (unsigned int)v5;\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov eax, [rdi+190h]\nmov edx, [rdi]\ncmp eax, edx\ncmovl eax, edx\ncmp esi, 1\njle short loc_11B5\nlea rdx, [rdi+4]\nlea ecx, [rsi-2]\nlea r8, [rdi+rcx*4+8]\nmov ecx, 0\nloc_1190:\nmov edi, ecx\ncmp ecx, eax\ncmovl ecx, eax\nmov eax, [rdx+190h]\nmov esi, [rdx]\ncmp eax, esi\ncmovl eax, esi\nadd eax, edi\nadd rdx, 4\ncmp rdx, r8\njnz short loc_1190\nloc_11AF:\ncmp eax, ecx\ncmovl eax, ecx\nretn\nloc_11B5:\nmov ecx, 0\njmp short loc_11AF", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int *a1, int a2)\n{\n __int64 result; // rax\n int *v3; // rdx\n __int64 v4; // r8\n int v5; // ecx\n int v6; // edi\n int v7; // eax\n\n result = (unsigned int)a1[100];\n if ( (int)result < *a1 )\n result = (unsigned int)*a1;\n if ( a2 <= 1 )\n {\n v5 = 0;\n }\n else\n {\n v3 = a1 + 1;\n v4 = (__int64)&a1[a2 - 2 + 2];\n v5 = 0;\n do\n {\n v6 = v5;\n if ( v5 < (int)result )\n v5 = result;\n v7 = v3[100];\n if ( v7 < *v3 )\n v7 = *v3;\n result = (unsigned int)(v6 + v7);\n ++v3;\n }\n while ( v3 != (int *)v4 );\n }\n if ( (int)result < v5 )\n return (unsigned int)v5;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int *a1, int a2) {\n long long result;\n int *v3;\n long long v4;\n int v5;\n int v6;\n int v7;\n result = (unsigned int)a1[100];\n if ((int)result < *a1) result = (unsigned int)*a1;\n if (a2 <= 1) {\n v5 = 0;\n } else {\n v3 = a1 + 1;\n v4 = (long long)&a1[a2 - 2 + 2];\n v5 = 0;\n do {\n v6 = v5;\n if (v5 < (int)result) v5 = result;\n v7 = v3[100];\n if (v7 < *v3) v7 = *v3;\n result = (unsigned int)(v6 + v7);\n ++v3;\n } while (v3 != (int *)v4);\n }\n if ((int)result < v5) return (unsigned int)v5;\n return result;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n long long result;\n int *v3;\n long long v4;\n int v5;\n int v6;\n int v7;\n result = (unsigned int)a1[100];\n if ((int)result < *a1) result = (unsigned int)*a1;\n if (a2 <= 1) {\n v5 = 0;\n } else {\n v3 = a1 + 1;\n v4 = (long long)&a1[a2 - 2 + 2];\n v5 = 0;\n do {\n v6 = v5;\n if (v5 < (int)result) v5 = result;\n v7 = v3[100];\n if (v7 < *v3) v7 = *v3;\n result = (unsigned int)(v6 + v7);\n ++v3;\n } while (v3 != (int *)v4);\n }\n if ((int)result < v5) return (unsigned int)v5;\n return result;\n}" + }, + { + "index": 314, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int grid[2][100], int n) {\n int incl = grid[0][0] > grid[1][0] ? grid[0][0] : grid[1][0];\n int excl = 0;\n for (int i = 1; i < n; i++) {\n int excl_new = excl > incl ? excl : incl;\n int max_value = grid[0][i] > grid[1][i] ? grid[0][i] : grid[1][i];\n incl = excl + max_value;\n excl = excl_new;\n }\n return excl > incl ? excl : incl;\n}", + "test": "int main() {\n\n int grid1[2][100] = {{1, 4, 5}, {2, 0, 0}};\n\n assert(func0(grid1, 3) == 7);\n\n\n\n int grid2[2][100] = {{1, 2, 3, 4, 5}, {6, 7, 8, 9, 10}};\n\n assert(func0(grid2, 5) == 24);\n\n\n\n int grid3[2][100] = {{7, 9, 11, 15, 19}, {21, 25, 28, 31, 32}};\n\n assert(func0(grid3, 5) == 81);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov (%rdi),%eax\ncmp %eax,0x190(%rdi)\ncmovge 0x190(%rdi),%eax\ncmp $0x1,%esi\njle 1380 \nlea -0x2(%rsi),%ecx\nlea 0x4(%rdi),%rdx\nlea 0x8(%rdi,%rcx,4),%rdi\nxor %ecx,%ecx\nnopw %cs:0x0(%rax,%rax,1)\ncmp %eax,%ecx\nmov %ecx,%esi\ncmovl %eax,%ecx\nmov (%rdx),%eax\ncmp %eax,0x190(%rdx)\ncmovge 0x190(%rdx),%eax\nadd $0x4,%rdx\nadd %esi,%eax\ncmp %rdi,%rdx\njne 1350 \ncmp %ecx,%eax\ncmovl %ecx,%eax\nretq\nnopw 0x0(%rax,%rax,1)\nxor %ecx,%ecx\ncmp %ecx,%eax\ncmovl %ecx,%eax\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmov eax, [rdi+190h]\nmov edx, [rdi]\ncmp eax, edx\ncmovl eax, edx\ncmp esi, 1\njle short loc_1370\nlea ecx, [rsi-2]\nlea rdx, [rdi+4]\nlea r8, [rdi+rcx*4+8]\nxor ecx, ecx\nnop dword ptr [rax+00h]\nloc_1348:\ncmp ecx, eax\nmov esi, [rdx]\nmov edi, ecx\ncmovl ecx, eax\nmov eax, [rdx+190h]\ncmp eax, esi\ncmovl eax, esi\nadd rdx, 4\nadd eax, edi\ncmp rdx, r8\njnz short loc_1348\ncmp eax, ecx\ncmovl eax, ecx\nretn\nloc_1370:\nxor ecx, ecx\ncmp eax, ecx\ncmovl eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n __int64 result; // rax\n int *v3; // rdx\n __int64 v4; // r8\n int v5; // ecx\n int v6; // edi\n int v7; // eax\n\n result = (unsigned int)a1[100];\n if ( (int)result < *a1 )\n result = (unsigned int)*a1;\n if ( a2 <= 1 )\n {\n if ( (int)result < 0 )\n return 0LL;\n }\n else\n {\n v3 = a1 + 1;\n v4 = (__int64)&a1[a2 - 2 + 2];\n v5 = 0;\n do\n {\n v6 = v5;\n if ( v5 < (int)result )\n v5 = result;\n v7 = v3[100];\n if ( v7 < *v3 )\n v7 = *v3;\n ++v3;\n result = (unsigned int)(v6 + v7);\n }\n while ( v3 != (int *)v4 );\n if ( (int)result < v5 )\n return (unsigned int)v5;\n }\n return result;\n}", + "ida_strip_asm": "sub_1320:\nendbr64\nmov eax, [rdi+190h]\nmov edx, [rdi]\ncmp eax, edx\ncmovl eax, edx\ncmp esi, 1\njle short loc_1370\nlea ecx, [rsi-2]\nlea rdx, [rdi+4]\nlea r8, [rdi+rcx*4+8]\nxor ecx, ecx\nnop dword ptr [rax+00h]\nloc_1348:\ncmp ecx, eax\nmov esi, [rdx]\nmov edi, ecx\ncmovl ecx, eax\nmov eax, [rdx+190h]\ncmp eax, esi\ncmovl eax, esi\nadd rdx, 4\nadd eax, edi\ncmp rdx, r8\njnz short loc_1348\ncmp eax, ecx\ncmovl eax, ecx\nretn\nloc_1370:\nxor ecx, ecx\ncmp eax, ecx\ncmovl eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1320(int *a1, int a2)\n{\n __int64 result; // rax\n int *v3; // rdx\n __int64 v4; // r8\n int v5; // ecx\n int v6; // edi\n int v7; // eax\n\n result = (unsigned int)a1[100];\n if ( (int)result < *a1 )\n result = (unsigned int)*a1;\n if ( a2 <= 1 )\n {\n if ( (int)result < 0 )\n return 0LL;\n }\n else\n {\n v3 = a1 + 1;\n v4 = (__int64)&a1[a2 - 2 + 2];\n v5 = 0;\n do\n {\n v6 = v5;\n if ( v5 < (int)result )\n v5 = result;\n v7 = v3[100];\n if ( v7 < *v3 )\n v7 = *v3;\n ++v3;\n result = (unsigned int)(v6 + v7);\n }\n while ( v3 != (int *)v4 );\n if ( (int)result < v5 )\n return (unsigned int)v5;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1320(int *a1, int a2) {\n long long result;\n int *v3;\n long long v4;\n int v5;\n int v6;\n int v7;\n result = (unsigned int)a1[100];\n if ((int)result < *a1) result = (unsigned int)*a1;\n if (a2 <= 1) {\n if ((int)result < 0) return 0LL;\n } else {\n v3 = a1 + 1;\n v4 = (long long)&a1[a2 - 2 + 2];\n v5 = 0;\n do {\n v6 = v5;\n if (v5 < (int)result) v5 = result;\n v7 = v3[100];\n if (v7 < *v3) v7 = *v3;\n ++v3;\n result = (unsigned int)(v6 + v7);\n } while (v3 != (int *)v4);\n if ((int)result < v5) return (unsigned int)v5;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n long long result;\n int *v3;\n long long v4;\n int v5;\n int v6;\n int v7;\n result = (unsigned int)a1[100];\n if ((int)result < *a1) result = (unsigned int)*a1;\n if (a2 <= 1) {\n if ((int)result < 0) return 0LL;\n } else {\n v3 = a1 + 1;\n v4 = (long long)&a1[a2 - 2 + 2];\n v5 = 0;\n do {\n v6 = v5;\n if (v5 < (int)result) v5 = result;\n v7 = v3[100];\n if (v7 < *v3) v7 = *v3;\n ++v3;\n result = (unsigned int)(v6 + v7);\n } while (v3 != (int *)v4);\n if ((int)result < v5) return (unsigned int)v5;\n }\n return result;\n}" + }, + { + "index": 315, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* str) {\n int n = strlen(str);\n int i = 0;\n int currlen = 0;\n int maxlen = 0;\n int st = -1;\n static char result[100];\n while (i < n) {\n if (str[i] == ' ') {\n if (currlen % 2 == 0) {\n if (maxlen < currlen) {\n maxlen = currlen;\n st = i - currlen;\n }\n }\n currlen = 0;\n } else {\n currlen += 1;\n }\n i += 1;\n }\n if (currlen % 2 == 0) {\n if (maxlen < currlen) {\n maxlen = currlen;\n st = i - currlen;\n }\n }\n if (st == -1) {\n return \"-1\";\n }\n strncpy(result, str + st, maxlen);\n result[maxlen] = '\\0';\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"python language\"), \"language\") == 0);\n\n assert(strcmp(func0(\"maximum even length\"), \"length\") == 0);\n\n assert(strcmp(func0(\"eve\"), \"-1\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x28(%rbp)\nmov -0x28(%rbp),%rax\nmov %rax,%rdi\ncallq 1090 \nmov %eax,-0x4(%rbp)\nmovl $0x0,-0x14(%rbp)\nmovl $0x0,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0xffffffff,-0x8(%rbp)\njmp 122c \nmov -0x14(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x20,%al\njne 1224 \nmov -0x10(%rbp),%eax\nand $0x1,%eax\ntest %eax,%eax\njne 121b \nmov -0xc(%rbp),%eax\ncmp -0x10(%rbp),%eax\njge 121b \nmov -0x10(%rbp),%eax\nmov %eax,-0xc(%rbp)\nmov -0x14(%rbp),%eax\nsub -0x10(%rbp),%eax\nmov %eax,-0x8(%rbp)\nmovl $0x0,-0x10(%rbp)\njmp 1228 \naddl $0x1,-0x10(%rbp)\naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\ncmp -0x4(%rbp),%eax\njl 11e6 \nmov -0x10(%rbp),%eax\nand $0x1,%eax\ntest %eax,%eax\njne 1255 \nmov -0xc(%rbp),%eax\ncmp -0x10(%rbp),%eax\njge 1255 \nmov -0x10(%rbp),%eax\nmov %eax,-0xc(%rbp)\nmov -0x14(%rbp),%eax\nsub -0x10(%rbp),%eax\nmov %eax,-0x8(%rbp)\ncmpl $0xffffffff,-0x8(%rbp)\njne 1264 \nlea 0xda6(%rip),%rax\njmp 129f \nmov -0xc(%rbp),%eax\ncltq\nmov -0x8(%rbp),%edx\nmovslq %edx,%rcx\nmov -0x28(%rbp),%rdx\nadd %rdx,%rcx\nmov %rax,%rdx\nmov %rcx,%rsi\nlea 0x2dbd(%rip),%rdi\ncallq 1080 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x2dac(%rip),%rdx\nmovb $0x0,(%rax,%rdx,1)\nlea 0x2da1(%rip),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0FFFFFFFFh\njmp short loc_122C\nloc_11E6:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njnz short loc_1224\nmov eax, [rbp+var_10]\nand eax, 1\ntest eax, eax\njnz short loc_121B\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_10]\njge short loc_121B\nmov eax, [rbp+var_10]\nmov [rbp+var_C], eax\nmov eax, [rbp+var_14]\nsub eax, [rbp+var_10]\nmov [rbp+var_8], eax\nloc_121B:\nmov [rbp+var_10], 0\njmp short loc_1228\nloc_1224:\nadd [rbp+var_10], 1\nloc_1228:\nadd [rbp+var_14], 1\nloc_122C:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_4]\njl short loc_11E6\nmov eax, [rbp+var_10]\nand eax, 1\ntest eax, eax\njnz short loc_1255\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_10]\njge short loc_1255\nmov eax, [rbp+var_10]\nmov [rbp+var_C], eax\nmov eax, [rbp+var_14]\nsub eax, [rbp+var_10]\nmov [rbp+var_8], eax\nloc_1255:\ncmp [rbp+var_8], 0FFFFFFFFh\njnz short loc_1264\nlea rax, a1; \"-1\"\njmp short locret_12A2\nloc_1264:\nmov eax, [rbp+var_C]\ncdqe\nmov edx, [rbp+var_8]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rcx, rdx\nmov rdx, rax; n\nmov rsi, rcx; src\nlea rax, result_1\nmov rdi, rax; dest\ncall _strncpy\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, result_1\nmov byte ptr [rax+rdx], 0\nlea rax, result_1\nlocret_12A2:\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(const char *a1)\n{\n int v2; // [rsp+1Ch] [rbp-14h]\n int v3; // [rsp+20h] [rbp-10h]\n int v4; // [rsp+24h] [rbp-Ch]\n int v5; // [rsp+28h] [rbp-8h]\n int v6; // [rsp+2Ch] [rbp-4h]\n\n v6 = strlen(a1);\n v2 = 0;\n v3 = 0;\n v4 = 0;\n v5 = -1;\n while ( v2 < v6 )\n {\n if ( a1[v2] == 32 )\n {\n if ( (v3 & 1) == 0 && v4 < v3 )\n {\n v4 = v3;\n v5 = v2 - v3;\n }\n v3 = 0;\n }\n else\n {\n ++v3;\n }\n ++v2;\n }\n if ( (v3 & 1) == 0 && v4 < v3 )\n {\n v4 = v3;\n v5 = v2 - v3;\n }\n if ( v5 == -1 )\n return \"-1\";\n strncpy(result_1, &a1[v5], v4);\n result_1[v4] = 0;\n return result_1;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0FFFFFFFFh\njmp short loc_122C\nloc_11E6:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njnz short loc_1224\nmov eax, [rbp+var_10]\nand eax, 1\ntest eax, eax\njnz short loc_121B\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_10]\njge short loc_121B\nmov eax, [rbp+var_10]\nmov [rbp+var_C], eax\nmov eax, [rbp+var_14]\nsub eax, [rbp+var_10]\nmov [rbp+var_8], eax\nloc_121B:\nmov [rbp+var_10], 0\njmp short loc_1228\nloc_1224:\nadd [rbp+var_10], 1\nloc_1228:\nadd [rbp+var_14], 1\nloc_122C:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_4]\njl short loc_11E6\nmov eax, [rbp+var_10]\nand eax, 1\ntest eax, eax\njnz short loc_1255\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_10]\njge short loc_1255\nmov eax, [rbp+var_10]\nmov [rbp+var_C], eax\nmov eax, [rbp+var_14]\nsub eax, [rbp+var_10]\nmov [rbp+var_8], eax\nloc_1255:\ncmp [rbp+var_8], 0FFFFFFFFh\njnz short loc_1264\nlea rax, a1; \"-1\"\njmp short locret_12A2\nloc_1264:\nmov eax, [rbp+var_C]\ncdqe\nmov edx, [rbp+var_8]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rcx, rdx\nmov rdx, rax; n\nmov rsi, rcx; src\nlea rax, dest\nmov rdi, rax; dest\ncall _strncpy\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, dest\nmov byte ptr [rax+rdx], 0\nlea rax, dest\nlocret_12A2:\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11A9(const char *a1)\n{\n int v2; // [rsp+1Ch] [rbp-14h]\n int v3; // [rsp+20h] [rbp-10h]\n int v4; // [rsp+24h] [rbp-Ch]\n int v5; // [rsp+28h] [rbp-8h]\n int v6; // [rsp+2Ch] [rbp-4h]\n\n v6 = strlen(a1);\n v2 = 0;\n v3 = 0;\n v4 = 0;\n v5 = -1;\n while ( v2 < v6 )\n {\n if ( a1[v2] == 32 )\n {\n if ( (v3 & 1) == 0 && v4 < v3 )\n {\n v4 = v3;\n v5 = v2 - v3;\n }\n v3 = 0;\n }\n else\n {\n ++v3;\n }\n ++v2;\n }\n if ( (v3 & 1) == 0 && v4 < v3 )\n {\n v4 = v3;\n v5 = v2 - v3;\n }\n if ( v5 == -1 )\n return \"-1\";\n strncpy(dest, &a1[v5], v4);\n dest[v4] = 0;\n return dest;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11A9(const char *a1) {\n int v2;\n int v3;\n int v4;\n int v5;\n int v6;\n v6 = strlen(a1);\n v2 = 0;\n v3 = 0;\n v4 = 0;\n v5 = -1;\n while (v2 < v6) {\n if (a1[v2] == 32) {\n if ((v3 & 1) == 0 && v4 < v3) {\n v4 = v3;\n v5 = v2 - v3;\n }\n v3 = 0;\n } else {\n ++v3;\n }\n ++v2;\n }\n if ((v3 & 1) == 0 && v4 < v3) {\n v4 = v3;\n v5 = v2 - v3;\n }\n if (v5 == -1) return \"-1\";\n strncpy(dest, &a1[v5], v4);\n dest[v4] = 0;\n return dest;\n}", + "ida_pseudo_norm": "char *func0(const char *a1) {\n int v2;\n int v3;\n int v4;\n int v5;\n int v6;\n v6 = strlen(a1);\n v2 = 0;\n v3 = 0;\n v4 = 0;\n v5 = -1;\n while (v2 < v6) {\n if (a1[v2] == 32) {\n if ((v3 & 1) == 0 && v4 < v3) {\n v4 = v3;\n v5 = v2 - v3;\n }\n v3 = 0;\n } else {\n ++v3;\n }\n ++v2;\n }\n if ((v3 & 1) == 0 && v4 < v3) {\n v4 = v3;\n v5 = v2 - v3;\n }\n if (v5 == -1) return \"-1\";\n strncpy(result_1, &a1[v5], v4);\n result_1[v4] = 0;\n return result_1;\n}" + }, + { + "index": 315, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* str) {\n int n = strlen(str);\n int i = 0;\n int currlen = 0;\n int maxlen = 0;\n int st = -1;\n static char result[100];\n while (i < n) {\n if (str[i] == ' ') {\n if (currlen % 2 == 0) {\n if (maxlen < currlen) {\n maxlen = currlen;\n st = i - currlen;\n }\n }\n currlen = 0;\n } else {\n currlen += 1;\n }\n i += 1;\n }\n if (currlen % 2 == 0) {\n if (maxlen < currlen) {\n maxlen = currlen;\n st = i - currlen;\n }\n }\n if (st == -1) {\n return \"-1\";\n }\n strncpy(result, str + st, maxlen);\n result[maxlen] = '\\0';\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"python language\"), \"language\") == 0);\n\n assert(strcmp(func0(\"maximum even length\"), \"length\") == 0);\n\n assert(strcmp(func0(\"eve\"), \"-1\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%rsi\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nlea -0x1(%rcx),%rdi\nlea 0xe78(%rip),%rax\ntest %edi,%edi\njle 1234 \nlea -0x1(%rdi),%r8d\nmov $0x0,%eax\nmov $0xffffffff,%r10d\nmov $0x0,%r9d\nmov $0x0,%edx\njmp 11ce \nsub %edx,%ecx\nmov %ecx,%r10d\nmov %edx,%r9d\nmov $0x0,%edx\njmp 11c2 \nadd $0x1,%edx\nlea 0x1(%rax),%rcx\ncmp %rax,%r8\nje 11e7 \nmov %rcx,%rax\nmov %eax,%ecx\ncmpb $0x20,(%rsi,%rax,1)\njne 11bf \ntest $0x1,%dl\njne 11e0 \ncmp %r9d,%edx\njg 11b0 \nmov $0x0,%edx\njmp 11c2 \ntest $0x1,%dl\njne 11f1 \ncmp %r9d,%edx\njg 1229 \nlea 0xe0c(%rip),%rax\ncmp $0xffffffff,%r10d\nje 1234 \npush %rbx\nmovslq %r9d,%rbx\nmovslq %r10d,%r10\nadd %r10,%rsi\nmov $0x64,%ecx\nmov %rbx,%rdx\nlea 0x2e29(%rip),%rdi\ncallq 1070 <__strncpy_chk@plt>\nlea 0x2e1d(%rip),%rax\nmovb $0x0,(%rax,%rbx,1)\npop %rbx\nretq\nmov %edi,%r10d\nsub %edx,%r10d\nmov %edx,%r9d\njmp 11f1 \nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\ncall _strlen\nmov r9, rax\nlea rax, s2; \"-1\"\ntest r9d, r9d\njle loc_125C\nlea edi, [r9-1]\nmov edx, 0\nmov r10d, 0FFFFFFFFh\nmov r8d, 0\nmov ecx, 0\njmp short loc_1205\nloc_11EA:\ntest cl, 1\njnz short loc_11F4\ncmp ecx, r8d\njg short loc_1210\nloc_11F4:\nmov ecx, 0\nloc_11F9:\nlea rsi, [rdx+1]\ncmp rdx, rdi\njz short loc_1220\nmov rdx, rsi\nloc_1205:\ncmp byte ptr [rbx+rdx], 20h ; ' '\njz short loc_11EA\nadd ecx, 1\njmp short loc_11F9\nloc_1210:\nmov r10d, edx\nsub r10d, ecx\nmov r8d, ecx\nmov ecx, 0\njmp short loc_11F9\nloc_1220:\ntest cl, 1\njnz short loc_122A\ncmp ecx, r8d\njg short loc_1263\nloc_122A:\nlea rax, s2; \"-1\"\ncmp r10d, 0FFFFFFFFh\njz short loc_125C\nmovsxd rbp, r8d\nmovsxd r10, r10d\nlea rsi, [rbx+r10]\nmov ecx, 64h ; 'd'\nmov rdx, rbp\nlea rbx, result_1\nmov rdi, rbx\ncall ___strncpy_chk\nmov byte ptr [rbx+rbp], 0\nloc_125C:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1263:\nmov r10d, r9d\nsub r10d, ecx\nmov r8d, ecx\njmp short loc_122A", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n int v1; // r9d\n const char *result; // rax\n __int64 v3; // rdx\n int v4; // r10d\n int v5; // r8d\n int v6; // ecx\n __int64 v7; // rbp\n\n v1 = strlen(a1);\n result = \"-1\";\n if ( v1 > 0 )\n {\n v3 = 0LL;\n v4 = -1;\n v5 = 0;\n v6 = 0;\n while ( 1 )\n {\n if ( a1[v3] == 32 )\n {\n if ( (v6 & 1) != 0 || v6 <= v5 )\n {\n v6 = 0;\n }\n else\n {\n v4 = v3 - v6;\n v5 = v6;\n v6 = 0;\n }\n }\n else\n {\n ++v6;\n }\n if ( v3 == v1 - 1 )\n break;\n ++v3;\n }\n if ( (v6 & 1) == 0 && v6 > v5 )\n {\n v4 = v1 - v6;\n v5 = v6;\n }\n result = \"-1\";\n if ( v4 != -1 )\n {\n v7 = v5;\n result = (const char *)__strncpy_chk(result_1, &a1[v4], v5, 100LL);\n result_1[v7] = 0;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\ncall _strlen\nmov r9, rax\nlea rax, s2; \"-1\"\ntest r9d, r9d\njle loc_125C\nlea edi, [r9-1]\nmov edx, 0\nmov r10d, 0FFFFFFFFh\nmov r8d, 0\nmov ecx, 0\njmp short loc_1205\nloc_11EA:\ntest cl, 1\njnz short loc_11F4\ncmp ecx, r8d\njg short loc_1210\nloc_11F4:\nmov ecx, 0\nloc_11F9:\nlea rsi, [rdx+1]\ncmp rdx, rdi\njz short loc_1220\nmov rdx, rsi\nloc_1205:\ncmp byte ptr [rbx+rdx], 20h ; ' '\njz short loc_11EA\nadd ecx, 1\njmp short loc_11F9\nloc_1210:\nmov r10d, edx\nsub r10d, ecx\nmov r8d, ecx\nmov ecx, 0\njmp short loc_11F9\nloc_1220:\ntest cl, 1\njnz short loc_122A\ncmp ecx, r8d\njg short loc_1263\nloc_122A:\nlea rax, s2; \"-1\"\ncmp r10d, 0FFFFFFFFh\njz short loc_125C\nmovsxd rbp, r8d\nmovsxd r10, r10d\nlea rsi, [rbx+r10]\nmov ecx, 64h ; 'd'\nmov rdx, rbp\nlea rbx, unk_4040\nmov rdi, rbx\ncall ___strncpy_chk\nmov byte ptr [rbx+rbp], 0\nloc_125C:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1263:\nmov r10d, r9d\nsub r10d, ecx\nmov r8d, ecx\njmp short loc_122A", + "ida_strip_pseudo": "const char *__fastcall sub_11A9(const char *a1)\n{\n int v1; // r9d\n const char *result; // rax\n __int64 v3; // rdx\n int v4; // r10d\n int v5; // r8d\n int v6; // ecx\n __int64 v7; // rbp\n\n v1 = strlen(a1);\n result = \"-1\";\n if ( v1 > 0 )\n {\n v3 = 0LL;\n v4 = -1;\n v5 = 0;\n v6 = 0;\n while ( 1 )\n {\n if ( a1[v3] == 32 )\n {\n if ( (v6 & 1) != 0 || v6 <= v5 )\n {\n v6 = 0;\n }\n else\n {\n v4 = v3 - v6;\n v5 = v6;\n v6 = 0;\n }\n }\n else\n {\n ++v6;\n }\n if ( v3 == v1 - 1 )\n break;\n ++v3;\n }\n if ( (v6 & 1) == 0 && v6 > v5 )\n {\n v4 = v1 - v6;\n v5 = v6;\n }\n result = \"-1\";\n if ( v4 != -1 )\n {\n v7 = v5;\n result = (const char *)__strncpy_chk(byte_4040, &a1[v4], v5, 100LL);\n byte_4040[v7] = 0;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_11A9(const char *a1) {\n int v1;\n const char *result;\n long long v3;\n int v4;\n int v5;\n int v6;\n long long v7;\n v1 = strlen(a1);\n result = \"-1\";\n if (v1 > 0) {\n v3 = 0LL;\n v4 = -1;\n v5 = 0;\n v6 = 0;\n while (1) {\n if (a1[v3] == 32) {\n if ((v6 & 1) != 0 || v6 <= v5) {\n v6 = 0;\n } else {\n v4 = v3 - v6;\n v5 = v6;\n v6 = 0;\n }\n } else {\n ++v6;\n }\n if (v3 == v1 - 1) break;\n ++v3;\n }\n if ((v6 & 1) == 0 && v6 > v5) {\n v4 = v1 - v6;\n v5 = v6;\n }\n result = \"-1\";\n if (v4 != -1) {\n v7 = v5;\n result = (const char *)__strncpy_chk(byte_4040, &a1[v4], v5, 100LL);\n byte_4040[v7] = 0;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n int v1;\n const char *result;\n long long v3;\n int v4;\n int v5;\n int v6;\n long long v7;\n v1 = strlen(a1);\n result = \"-1\";\n if (v1 > 0) {\n v3 = 0LL;\n v4 = -1;\n v5 = 0;\n v6 = 0;\n while (1) {\n if (a1[v3] == 32) {\n if ((v6 & 1) != 0 || v6 <= v5) {\n v6 = 0;\n } else {\n v4 = v3 - v6;\n v5 = v6;\n v6 = 0;\n }\n } else {\n ++v6;\n }\n if (v3 == v1 - 1) break;\n ++v3;\n }\n if ((v6 & 1) == 0 && v6 > v5) {\n v4 = v1 - v6;\n v5 = v6;\n }\n result = \"-1\";\n if (v4 != -1) {\n v7 = v5;\n result = (const char *)__strncpy_chk(result_1, &a1[v4], v5, 100LL);\n result_1[v7] = 0;\n }\n }\n return result;\n}" + }, + { + "index": 315, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* str) {\n int n = strlen(str);\n int i = 0;\n int currlen = 0;\n int maxlen = 0;\n int st = -1;\n static char result[100];\n while (i < n) {\n if (str[i] == ' ') {\n if (currlen % 2 == 0) {\n if (maxlen < currlen) {\n maxlen = currlen;\n st = i - currlen;\n }\n }\n currlen = 0;\n } else {\n currlen += 1;\n }\n i += 1;\n }\n if (currlen % 2 == 0) {\n if (maxlen < currlen) {\n maxlen = currlen;\n st = i - currlen;\n }\n }\n if (st == -1) {\n return \"-1\";\n }\n strncpy(result, str + st, maxlen);\n result[maxlen] = '\\0';\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"python language\"), \"language\") == 0);\n\n assert(strcmp(func0(\"maximum even length\"), \"length\") == 0);\n\n assert(strcmp(func0(\"eve\"), \"-1\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nmov %rdi,%rbx\nsub $0x8,%rsp\ncallq 1070 \nmov %rax,%r10\nlea 0xd78(%rip),%rax\ntest %r10d,%r10d\njle 1310 \nlea -0x1(%r10),%edi\nxor %edx,%edx\nmov $0xffffffff,%esi\nxor %r9d,%r9d\nxor %ecx,%ecx\njmp 12b7 \nnopl 0x0(%rax,%rax,1)\nadd $0x1,%ecx\nlea 0x1(%rdx),%r8\ncmp %rdx,%rdi\nje 12d2 \nmov %r8,%rdx\ncmpb $0x20,(%rbx,%rdx,1)\njne 12a8 \ncmp %r9d,%ecx\njle 12c7 \ntest $0x1,%cl\nje 1320 \nxor %ecx,%ecx\nlea 0x1(%rdx),%r8\ncmp %rdx,%rdi\njne 12b4 \ncmp %r9d,%ecx\njle 12dc \ntest $0x1,%cl\nje 1330 \nlea 0xd21(%rip),%rax\ncmp $0xffffffff,%esi\nje 1310 \nmovslq %r9d,%rbp\nmovslq %esi,%rsi\nmov $0x64,%ecx\nadd %rbx,%rsi\nmov %rbp,%rdx\nlea 0x2d40(%rip),%rdi\ncallq 1090 <__strncpy_chk@plt>\nlea 0x2d34(%rip),%rax\nmovb $0x0,(%rax,%rbp,1)\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopw 0x0(%rax,%rax,1)\nmov %edx,%esi\nmov %ecx,%r9d\nsub %ecx,%esi\nxor %ecx,%ecx\njmp 12ab \nnopl 0x0(%rax,%rax,1)\nmov %r10d,%esi\nmov %ecx,%r9d\nsub %ecx,%esi\njmp 12dc \nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\nmov r9, rax\nlea rax, unk_2004\ntest r9d, r9d\njle short loc_1319\nlea esi, [r9-1]\nxor edx, edx\nmov r10d, 0FFFFFFFFh\nxor edi, edi\nxor ecx, ecx\njmp short loc_12C7\nloc_12B8:\nadd ecx, 1\nloc_12BB:\nlea r8, [rdx+1]\ncmp rsi, rdx\njz short loc_12E1\nloc_12C4:\nmov rdx, r8\nloc_12C7:\ncmp byte ptr [rbx+rdx], 20h ; ' '\njnz short loc_12B8\ncmp ecx, edi\njle short loc_12D6\ntest cl, 1\njz short loc_1320\nloc_12D6:\nxor ecx, ecx\nlea r8, [rdx+1]\ncmp rsi, rdx\njnz short loc_12C4\nloc_12E1:\ncmp ecx, edi\njle short loc_12EA\ntest cl, 1\njz short loc_1330\nloc_12EA:\nlea rax, unk_2004\ncmp r10d, 0FFFFFFFFh\njz short loc_1319\nmovsxd rbp, edi\nmovsxd r10, r10d\nmov ecx, 64h ; 'd'\nlea rsi, [rbx+r10]\nmov rdx, rbp\nlea rdi, result_1\ncall ___strncpy_chk\nmov byte ptr [rax+rbp], 0\nloc_1319:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1320:\nmov r10d, edx\nmov edi, ecx\nsub r10d, ecx\nxor ecx, ecx\njmp short loc_12BB\nloc_1330:\nmov r10d, r9d\nmov edi, ecx\nsub r10d, ecx\njmp short loc_12EA", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1)\n{\n int v2; // r9d\n _BYTE *result; // rax\n __int64 v4; // rsi\n __int64 v5; // rdx\n int v6; // r10d\n int v7; // edi\n int v8; // ecx\n __int64 v9; // r8\n\n v2 = strlen(a1);\n result = &unk_2004;\n if ( v2 <= 0 )\n return result;\n v4 = (unsigned int)(v2 - 1);\n v5 = 0LL;\n v6 = -1;\n v7 = 0;\n v8 = 0;\n while ( 1 )\n {\n if ( a1[v5] != 32 )\n {\n ++v8;\n goto LABEL_4;\n }\n if ( v8 <= v7 || (v8 & 1) != 0 )\n break;\n v7 = v8;\n v6 = v5 - v8;\n v8 = 0;\nLABEL_4:\n v9 = v5 + 1;\n if ( v4 == v5 )\n goto LABEL_10;\nLABEL_5:\n v5 = v9;\n }\n v8 = 0;\n v9 = v5 + 1;\n if ( v4 != v5 )\n goto LABEL_5;\nLABEL_10:\n if ( v8 > v7 && (v8 & 1) == 0 )\n {\n v7 = v8;\n v6 = v2 - v8;\n }\n result = &unk_2004;\n if ( v6 != -1 )\n {\n result = (_BYTE *)__strncpy_chk(&result_1, &a1[v6], v7, 100LL, v9);\n result[v7] = 0;\n }\n return result;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\nmov r9, rax\nlea rax, unk_2004\ntest r9d, r9d\njle short loc_1319\nlea esi, [r9-1]\nxor edx, edx\nmov r10d, 0FFFFFFFFh\nxor edi, edi\nxor ecx, ecx\njmp short loc_12C7\nloc_12B8:\nadd ecx, 1\nloc_12BB:\nlea r8, [rdx+1]\ncmp rsi, rdx\njz short loc_12E1\nloc_12C4:\nmov rdx, r8\nloc_12C7:\ncmp byte ptr [rbx+rdx], 20h ; ' '\njnz short loc_12B8\ncmp ecx, edi\njle short loc_12D6\ntest cl, 1\njz short loc_1320\nloc_12D6:\nxor ecx, ecx\nlea r8, [rdx+1]\ncmp rsi, rdx\njnz short loc_12C4\nloc_12E1:\ncmp ecx, edi\njle short loc_12EA\ntest cl, 1\njz short loc_1330\nloc_12EA:\nlea rax, unk_2004\ncmp r10d, 0FFFFFFFFh\njz short loc_1319\nmovsxd rbp, edi\nmovsxd r10, r10d\nmov ecx, 64h ; 'd'\nlea rsi, [rbx+r10]\nmov rdx, rbp\nlea rdi, unk_4040\ncall ___strncpy_chk\nmov byte ptr [rax+rbp], 0\nloc_1319:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1320:\nmov r10d, edx\nmov edi, ecx\nsub r10d, ecx\nxor ecx, ecx\njmp short loc_12BB\nloc_1330:\nmov r10d, r9d\nmov edi, ecx\nsub r10d, ecx\njmp short loc_12EA", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1280(const char *a1)\n{\n int v2; // r9d\n _BYTE *result; // rax\n __int64 v4; // rsi\n __int64 v5; // rdx\n int v6; // r10d\n int v7; // edi\n int v8; // ecx\n __int64 v9; // r8\n\n v2 = strlen(a1);\n result = &unk_2004;\n if ( v2 <= 0 )\n return result;\n v4 = (unsigned int)(v2 - 1);\n v5 = 0LL;\n v6 = -1;\n v7 = 0;\n v8 = 0;\n while ( 1 )\n {\n if ( a1[v5] != 32 )\n {\n ++v8;\n goto LABEL_4;\n }\n if ( v8 <= v7 || (v8 & 1) != 0 )\n break;\n v7 = v8;\n v6 = v5 - v8;\n v8 = 0;\nLABEL_4:\n v9 = v5 + 1;\n if ( v4 == v5 )\n goto LABEL_10;\nLABEL_5:\n v5 = v9;\n }\n v8 = 0;\n v9 = v5 + 1;\n if ( v4 != v5 )\n goto LABEL_5;\nLABEL_10:\n if ( v8 > v7 && (v8 & 1) == 0 )\n {\n v7 = v8;\n v6 = v2 - v8;\n }\n result = &unk_2004;\n if ( v6 != -1 )\n {\n result = (_BYTE *)__strncpy_chk(&unk_4040, &a1[v6], v7, 100LL, v9);\n result[v7] = 0;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1280(const char *a1) {\n int v2;\n uint8_t *result;\n long long v4;\n long long v5;\n int v6;\n int v7;\n int v8;\n long long v9;\n v2 = strlen(a1);\n result = &unk_2004;\n if (v2 <= 0) return result;\n v4 = (unsigned int)(v2 - 1);\n v5 = 0LL;\n v6 = -1;\n v7 = 0;\n v8 = 0;\n while (1) {\n if (a1[v5] != 32) {\n ++v8;\n goto LABEL_4;\n }\n if (v8 <= v7 || (v8 & 1) != 0) break;\n v7 = v8;\n v6 = v5 - v8;\n v8 = 0;\n LABEL_4:\n v9 = v5 + 1;\n if (v4 == v5) goto LABEL_10;\n LABEL_5:\n v5 = v9;\n }\n v8 = 0;\n v9 = v5 + 1;\n if (v4 != v5) goto LABEL_5;\nLABEL_10:\n if (v8 > v7 && (v8 & 1) == 0) {\n v7 = v8;\n v6 = v2 - v8;\n }\n result = &unk_2004;\n if (v6 != -1) {\n result = (uint8_t *)__strncpy_chk(&unk_4040, &a1[v6], v7, 100LL, v9);\n result[v7] = 0;\n }\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1) {\n int v2;\n uint8_t *result;\n long long v4;\n long long v5;\n int v6;\n int v7;\n int v8;\n long long v9;\n v2 = strlen(a1);\n result = &unk_2004;\n if (v2 <= 0) return result;\n v4 = (unsigned int)(v2 - 1);\n v5 = 0LL;\n v6 = -1;\n v7 = 0;\n v8 = 0;\n while (1) {\n if (a1[v5] != 32) {\n ++v8;\n goto LABEL_4;\n }\n if (v8 <= v7 || (v8 & 1) != 0) break;\n v7 = v8;\n v6 = v5 - v8;\n v8 = 0;\n LABEL_4:\n v9 = v5 + 1;\n if (v4 == v5) goto LABEL_10;\n LABEL_5:\n v5 = v9;\n }\n v8 = 0;\n v9 = v5 + 1;\n if (v4 != v5) goto LABEL_5;\nLABEL_10:\n if (v8 > v7 && (v8 & 1) == 0) {\n v7 = v8;\n v6 = v2 - v8;\n }\n result = &unk_2004;\n if (v6 != -1) {\n result = (uint8_t *)__strncpy_chk(&result_1, &a1[v6], v7, 100LL, v9);\n result[v7] = 0;\n }\n return result;\n}" + }, + { + "index": 315, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* str) {\n int n = strlen(str);\n int i = 0;\n int currlen = 0;\n int maxlen = 0;\n int st = -1;\n static char result[100];\n while (i < n) {\n if (str[i] == ' ') {\n if (currlen % 2 == 0) {\n if (maxlen < currlen) {\n maxlen = currlen;\n st = i - currlen;\n }\n }\n currlen = 0;\n } else {\n currlen += 1;\n }\n i += 1;\n }\n if (currlen % 2 == 0) {\n if (maxlen < currlen) {\n maxlen = currlen;\n st = i - currlen;\n }\n }\n if (st == -1) {\n return \"-1\";\n }\n strncpy(result, str + st, maxlen);\n result[maxlen] = '\\0';\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"python language\"), \"language\") == 0);\n\n assert(strcmp(func0(\"maximum even length\"), \"length\") == 0);\n\n assert(strcmp(func0(\"eve\"), \"-1\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nmov %rdi,%rbx\nsub $0x8,%rsp\ncallq 1070 \nmov %rax,%r10\nlea 0xd78(%rip),%rax\ntest %r10d,%r10d\njle 1310 \nlea -0x1(%r10),%edi\nxor %edx,%edx\nmov $0xffffffff,%esi\nxor %r9d,%r9d\nxor %ecx,%ecx\njmp 12b7 \nnopl 0x0(%rax,%rax,1)\nadd $0x1,%ecx\nlea 0x1(%rdx),%r8\ncmp %rdi,%rdx\nje 12d2 \nmov %r8,%rdx\ncmpb $0x20,(%rbx,%rdx,1)\njne 12a8 \ncmp %ecx,%r9d\njge 12c7 \ntest $0x1,%cl\nje 1320 \nxor %ecx,%ecx\nlea 0x1(%rdx),%r8\ncmp %rdi,%rdx\njne 12b4 \ncmp %r9d,%ecx\njle 12dc \ntest $0x1,%cl\nje 1330 \nlea 0xd21(%rip),%rax\ncmp $0xffffffff,%esi\nje 1310 \nmovslq %r9d,%rbp\nmovslq %esi,%rsi\nmov $0x64,%ecx\nadd %rbx,%rsi\nmov %rbp,%rdx\nlea 0x2d40(%rip),%rdi\ncallq 1090 <__strncpy_chk@plt>\nlea 0x2d34(%rip),%rax\nmovb $0x0,(%rax,%rbp,1)\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopw 0x0(%rax,%rax,1)\nmov %edx,%esi\nmov %ecx,%r9d\nsub %ecx,%esi\nxor %ecx,%ecx\njmp 12ab \nnopl 0x0(%rax,%rax,1)\nmov %r10d,%esi\nmov %ecx,%r9d\nsub %ecx,%esi\njmp 12dc \nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\nmov r9, rax\nlea rax, unk_2004\ntest r9d, r9d\njle short loc_1319\nlea esi, [r9-1]\nxor edx, edx\nmov r10d, 0FFFFFFFFh\nxor edi, edi\nxor ecx, ecx\njmp short loc_12C7\nloc_12B8:\nadd ecx, 1\nloc_12BB:\nlea r8, [rdx+1]\ncmp rdx, rsi\njz short loc_12E1\nloc_12C4:\nmov rdx, r8\nloc_12C7:\ncmp byte ptr [rbx+rdx], 20h ; ' '\njnz short loc_12B8\ncmp edi, ecx\njge short loc_12D6\ntest cl, 1\njz short loc_1320\nloc_12D6:\nxor ecx, ecx\nlea r8, [rdx+1]\ncmp rdx, rsi\njnz short loc_12C4\nloc_12E1:\ncmp ecx, edi\njle short loc_12EA\ntest cl, 1\njz short loc_1330\nloc_12EA:\nlea rax, unk_2004\ncmp r10d, 0FFFFFFFFh\njz short loc_1319\nmovsxd rbp, edi\nmovsxd r10, r10d\nmov ecx, 64h ; 'd'\nlea rsi, [rbx+r10]\nmov rdx, rbp\nlea rdi, result_1\ncall ___strncpy_chk\nmov byte ptr [rax+rbp], 0\nloc_1319:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1320:\nmov r10d, edx\nmov edi, ecx\nsub r10d, ecx\nxor ecx, ecx\njmp short loc_12BB\nloc_1330:\nmov r10d, r9d\nmov edi, ecx\nsub r10d, ecx\njmp short loc_12EA", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1)\n{\n int v2; // r9d\n _BYTE *result; // rax\n __int64 v4; // rsi\n __int64 v5; // rdx\n int v6; // r10d\n int v7; // edi\n int v8; // ecx\n __int64 v9; // r8\n\n v2 = strlen(a1);\n result = &unk_2004;\n if ( v2 <= 0 )\n return result;\n v4 = (unsigned int)(v2 - 1);\n v5 = 0LL;\n v6 = -1;\n v7 = 0;\n v8 = 0;\n while ( 1 )\n {\n if ( a1[v5] != 32 )\n {\n ++v8;\n goto LABEL_4;\n }\n if ( v7 >= v8 || (v8 & 1) != 0 )\n break;\n v7 = v8;\n v6 = v5 - v8;\n v8 = 0;\nLABEL_4:\n v9 = v5 + 1;\n if ( v5 == v4 )\n goto LABEL_10;\nLABEL_5:\n v5 = v9;\n }\n v8 = 0;\n v9 = v5 + 1;\n if ( v5 != v4 )\n goto LABEL_5;\nLABEL_10:\n if ( v8 > v7 && (v8 & 1) == 0 )\n {\n v7 = v8;\n v6 = v2 - v8;\n }\n result = &unk_2004;\n if ( v6 != -1 )\n {\n result = (_BYTE *)__strncpy_chk(&result_1, &a1[v6], v7, 100LL, v9);\n result[v7] = 0;\n }\n return result;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\nmov r9, rax\nlea rax, unk_2004\ntest r9d, r9d\njle short loc_1319\nlea esi, [r9-1]\nxor edx, edx\nmov r10d, 0FFFFFFFFh\nxor edi, edi\nxor ecx, ecx\njmp short loc_12C7\nloc_12B8:\nadd ecx, 1\nloc_12BB:\nlea r8, [rdx+1]\ncmp rdx, rsi\njz short loc_12E1\nloc_12C4:\nmov rdx, r8\nloc_12C7:\ncmp byte ptr [rbx+rdx], 20h ; ' '\njnz short loc_12B8\ncmp edi, ecx\njge short loc_12D6\ntest cl, 1\njz short loc_1320\nloc_12D6:\nxor ecx, ecx\nlea r8, [rdx+1]\ncmp rdx, rsi\njnz short loc_12C4\nloc_12E1:\ncmp ecx, edi\njle short loc_12EA\ntest cl, 1\njz short loc_1330\nloc_12EA:\nlea rax, unk_2004\ncmp r10d, 0FFFFFFFFh\njz short loc_1319\nmovsxd rbp, edi\nmovsxd r10, r10d\nmov ecx, 64h ; 'd'\nlea rsi, [rbx+r10]\nmov rdx, rbp\nlea rdi, unk_4040\ncall ___strncpy_chk\nmov byte ptr [rax+rbp], 0\nloc_1319:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1320:\nmov r10d, edx\nmov edi, ecx\nsub r10d, ecx\nxor ecx, ecx\njmp short loc_12BB\nloc_1330:\nmov r10d, r9d\nmov edi, ecx\nsub r10d, ecx\njmp short loc_12EA", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1280(const char *a1)\n{\n int v2; // r9d\n _BYTE *result; // rax\n __int64 v4; // rsi\n __int64 v5; // rdx\n int v6; // r10d\n int v7; // edi\n int v8; // ecx\n __int64 v9; // r8\n\n v2 = strlen(a1);\n result = &unk_2004;\n if ( v2 <= 0 )\n return result;\n v4 = (unsigned int)(v2 - 1);\n v5 = 0LL;\n v6 = -1;\n v7 = 0;\n v8 = 0;\n while ( 1 )\n {\n if ( a1[v5] != 32 )\n {\n ++v8;\n goto LABEL_4;\n }\n if ( v7 >= v8 || (v8 & 1) != 0 )\n break;\n v7 = v8;\n v6 = v5 - v8;\n v8 = 0;\nLABEL_4:\n v9 = v5 + 1;\n if ( v5 == v4 )\n goto LABEL_10;\nLABEL_5:\n v5 = v9;\n }\n v8 = 0;\n v9 = v5 + 1;\n if ( v5 != v4 )\n goto LABEL_5;\nLABEL_10:\n if ( v8 > v7 && (v8 & 1) == 0 )\n {\n v7 = v8;\n v6 = v2 - v8;\n }\n result = &unk_2004;\n if ( v6 != -1 )\n {\n result = (_BYTE *)__strncpy_chk(&unk_4040, &a1[v6], v7, 100LL, v9);\n result[v7] = 0;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1280(const char *a1) {\n int v2;\n uint8_t *result;\n long long v4;\n long long v5;\n int v6;\n int v7;\n int v8;\n long long v9;\n v2 = strlen(a1);\n result = &unk_2004;\n if (v2 <= 0) return result;\n v4 = (unsigned int)(v2 - 1);\n v5 = 0LL;\n v6 = -1;\n v7 = 0;\n v8 = 0;\n while (1) {\n if (a1[v5] != 32) {\n ++v8;\n goto LABEL_4;\n }\n if (v7 >= v8 || (v8 & 1) != 0) break;\n v7 = v8;\n v6 = v5 - v8;\n v8 = 0;\n LABEL_4:\n v9 = v5 + 1;\n if (v5 == v4) goto LABEL_10;\n LABEL_5:\n v5 = v9;\n }\n v8 = 0;\n v9 = v5 + 1;\n if (v5 != v4) goto LABEL_5;\nLABEL_10:\n if (v8 > v7 && (v8 & 1) == 0) {\n v7 = v8;\n v6 = v2 - v8;\n }\n result = &unk_2004;\n if (v6 != -1) {\n result = (uint8_t *)__strncpy_chk(&unk_4040, &a1[v6], v7, 100LL, v9);\n result[v7] = 0;\n }\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1) {\n int v2;\n uint8_t *result;\n long long v4;\n long long v5;\n int v6;\n int v7;\n int v8;\n long long v9;\n v2 = strlen(a1);\n result = &unk_2004;\n if (v2 <= 0) return result;\n v4 = (unsigned int)(v2 - 1);\n v5 = 0LL;\n v6 = -1;\n v7 = 0;\n v8 = 0;\n while (1) {\n if (a1[v5] != 32) {\n ++v8;\n goto LABEL_4;\n }\n if (v7 >= v8 || (v8 & 1) != 0) break;\n v7 = v8;\n v6 = v5 - v8;\n v8 = 0;\n LABEL_4:\n v9 = v5 + 1;\n if (v5 == v4) goto LABEL_10;\n LABEL_5:\n v5 = v9;\n }\n v8 = 0;\n v9 = v5 + 1;\n if (v5 != v4) goto LABEL_5;\nLABEL_10:\n if (v8 > v7 && (v8 & 1) == 0) {\n v7 = v8;\n v6 = v2 - v8;\n }\n result = &unk_2004;\n if (v6 != -1) {\n result = (uint8_t *)__strncpy_chk(&result_1, &a1[v6], v7, 100LL, v9);\n result[v7] = 0;\n }\n return result;\n}" + }, + { + "index": 316, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int A[], int n, int x) {\n int left = 0;\n int right = n - 1;\n int result = -1;\n while (left <= right) {\n int mid = (left + right) / 2;\n if (x == A[mid]) {\n result = mid;\n left = mid + 1;\n } else if (x < A[mid]) {\n right = mid - 1;\n } else {\n left = mid + 1;\n }\n }\n return result;\n}", + "test": "int main() {\n\n int arr1[] = {2, 5, 5, 5, 6, 6, 8, 9, 9, 9};\n\n int arr2[] = {2, 3, 5, 8, 6, 6, 8, 9, 9, 9};\n\n int arr3[] = {2, 2, 1, 5, 6, 6, 6, 9, 9, 9};\n\n\n\n assert(func0(arr1, 10, 5) == 3);\n\n assert(func0(arr2, 10, 9) == 9);\n\n assert(func0(arr3, 10, 6) == 6);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmovl $0x0,-0x10(%rbp)\nmov -0x1c(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0xc(%rbp)\nmovl $0xffffffff,-0x8(%rbp)\njmp 1203 \nmov -0x10(%rbp),%edx\nmov -0xc(%rbp),%eax\nadd %edx,%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x20(%rbp)\njne 11d4 \nmov -0x4(%rbp),%eax\nmov %eax,-0x8(%rbp)\nmov -0x4(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x10(%rbp)\njmp 1203 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x20(%rbp)\njge 11fa \nmov -0x4(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0xc(%rbp)\njmp 1203 \nmov -0x4(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x10(%rbp)\nmov -0x10(%rbp),%eax\ncmp -0xc(%rbp),%eax\njle 1194 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_10], 0\nmov eax, [rbp+var_1C]\nsub eax, 1\nmov [rbp+var_C], eax\nmov [rbp+var_8], 0FFFFFFFFh\njmp short loc_1203\nloc_1194:\nmov edx, [rbp+var_10]\nmov eax, [rbp+var_C]\nadd eax, edx\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njnz short loc_11D4\nmov eax, [rbp+var_4]\nmov [rbp+var_8], eax\nmov eax, [rbp+var_4]\nadd eax, 1\nmov [rbp+var_10], eax\njmp short loc_1203\nloc_11D4:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njge short loc_11FA\nmov eax, [rbp+var_4]\nsub eax, 1\nmov [rbp+var_C], eax\njmp short loc_1203\nloc_11FA:\nmov eax, [rbp+var_4]\nadd eax, 1\nmov [rbp+var_10], eax\nloc_1203:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_C]\njle short loc_1194\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n int v4; // [rsp+10h] [rbp-10h]\n int v5; // [rsp+14h] [rbp-Ch]\n unsigned int v6; // [rsp+18h] [rbp-8h]\n int v7; // [rsp+1Ch] [rbp-4h]\n\n v4 = 0;\n v5 = a2 - 1;\n v6 = -1;\n while ( v4 <= v5 )\n {\n v7 = (v4 + v5) / 2;\n if ( a3 == *(_DWORD *)(4LL * v7 + a1) )\n {\n v6 = (v4 + v5) / 2;\n v4 = v7 + 1;\n }\n else if ( a3 >= *(_DWORD *)(4LL * v7 + a1) )\n {\n v4 = v7 + 1;\n }\n else\n {\n v5 = v7 - 1;\n }\n }\n return v6;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_10], 0\nmov eax, [rbp+var_1C]\nsub eax, 1\nmov [rbp+var_C], eax\nmov [rbp+var_8], 0FFFFFFFFh\njmp short loc_1203\nloc_1194:\nmov edx, [rbp+var_10]\nmov eax, [rbp+var_C]\nadd eax, edx\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njnz short loc_11D4\nmov eax, [rbp+var_4]\nmov [rbp+var_8], eax\nmov eax, [rbp+var_4]\nadd eax, 1\nmov [rbp+var_10], eax\njmp short loc_1203\nloc_11D4:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njge short loc_11FA\nmov eax, [rbp+var_4]\nsub eax, 1\nmov [rbp+var_C], eax\njmp short loc_1203\nloc_11FA:\nmov eax, [rbp+var_4]\nadd eax, 1\nmov [rbp+var_10], eax\nloc_1203:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_C]\njle short loc_1194\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n int v4; // [rsp+10h] [rbp-10h]\n int v5; // [rsp+14h] [rbp-Ch]\n unsigned int v6; // [rsp+18h] [rbp-8h]\n int v7; // [rsp+1Ch] [rbp-4h]\n\n v4 = 0;\n v5 = a2 - 1;\n v6 = -1;\n while ( v4 <= v5 )\n {\n v7 = (v4 + v5) / 2;\n if ( a3 == *(_DWORD *)(4LL * v7 + a1) )\n {\n v6 = (v4 + v5) / 2;\n v4 = v7 + 1;\n }\n else if ( a3 >= *(_DWORD *)(4LL * v7 + a1) )\n {\n v4 = v7 + 1;\n }\n else\n {\n v5 = v7 - 1;\n }\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n int v4;\n int v5;\n unsigned int v6;\n int v7;\n v4 = 0;\n v5 = a2 - 1;\n v6 = -1;\n while (v4 <= v5) {\n v7 = (v4 + v5) / 2;\n if (a3 == *(uint32_t *)(4LL * v7 + a1)) {\n v6 = (v4 + v5) / 2;\n v4 = v7 + 1;\n } else if (a3 >= *(uint32_t *)(4LL * v7 + a1)) {\n v4 = v7 + 1;\n } else {\n v5 = v7 - 1;\n }\n }\n return v6;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n int v4;\n int v5;\n unsigned int v6;\n int v7;\n v4 = 0;\n v5 = a2 - 1;\n v6 = -1;\n while (v4 <= v5) {\n v7 = (v4 + v5) / 2;\n if (a3 == *(uint32_t *)(4LL * v7 + a1)) {\n v6 = (v4 + v5) / 2;\n v4 = v7 + 1;\n } else if (a3 >= *(uint32_t *)(4LL * v7 + a1)) {\n v4 = v7 + 1;\n } else {\n v5 = v7 - 1;\n }\n }\n return v6;\n}" + }, + { + "index": 316, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int A[], int n, int x) {\n int left = 0;\n int right = n - 1;\n int result = -1;\n while (left <= right) {\n int mid = (left + right) / 2;\n if (x == A[mid]) {\n result = mid;\n left = mid + 1;\n } else if (x < A[mid]) {\n right = mid - 1;\n } else {\n left = mid + 1;\n }\n }\n return result;\n}", + "test": "int main() {\n\n int arr1[] = {2, 5, 5, 5, 6, 6, 8, 9, 9, 9};\n\n int arr2[] = {2, 3, 5, 8, 6, 6, 8, 9, 9, 9};\n\n int arr3[] = {2, 2, 1, 5, 6, 6, 6, 9, 9, 9};\n\n\n\n assert(func0(arr1, 10, 5) == 3);\n\n assert(func0(arr2, 10, 9) == 9);\n\n assert(func0(arr3, 10, 6) == 6);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x1,%esi\njs 11b0 \nmov $0xffffffff,%r9d\nmov $0x0,%r8d\njmp 118c \nlea 0x1(%rax),%r8d\nmov %eax,%r9d\ncmp %esi,%r8d\njg 11b6 \nlea (%r8,%rsi,1),%ecx\nmov %ecx,%eax\nshr $0x1f,%eax\nadd %ecx,%eax\nsar %eax\nmovslq %eax,%rcx\nmov (%rdi,%rcx,4),%ecx\ncmp %edx,%ecx\nje 1180 \njle 11aa \nlea -0x1(%rax),%esi\njmp 1187 \nlea 0x1(%rax),%r8d\njmp 1187 \nmov $0xffffffff,%r9d\nmov %r9d,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nsub esi, 1\njs short loc_11B0\nmov r9d, 0FFFFFFFFh\nmov r8d, 0\njmp short loc_118C\nloc_1180:\nlea r8d, [rax+1]\nmov r9d, eax\nloc_1187:\ncmp r8d, esi\njg short loc_11B6\nloc_118C:\nlea ecx, [r8+rsi]\nmov eax, ecx\nshr eax, 1Fh\nadd eax, ecx\nsar eax, 1\nmovsxd rcx, eax\nmov ecx, [rdi+rcx*4]\ncmp ecx, edx\njz short loc_1180\njle short loc_11AA\nlea esi, [rax-1]\njmp short loc_1187\nloc_11AA:\nlea r8d, [rax+1]\njmp short loc_1187\nloc_11B0:\nmov r9d, 0FFFFFFFFh\nloc_11B6:\nmov eax, r9d\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n int v3; // esi\n unsigned int v4; // r9d\n int v5; // r8d\n int v6; // eax\n int v7; // ecx\n\n v3 = a2 - 1;\n if ( v3 < 0 )\n {\n return (unsigned int)-1;\n }\n else\n {\n v4 = -1;\n v5 = 0;\n do\n {\n v6 = (v5 + v3) / 2;\n v7 = *(_DWORD *)(a1 + 4LL * v6);\n if ( v7 == a3 )\n {\n v5 = v6 + 1;\n v4 = v6;\n }\n else if ( v7 <= a3 )\n {\n v5 = v6 + 1;\n }\n else\n {\n v3 = v6 - 1;\n }\n }\n while ( v5 <= v3 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nsub esi, 1\njs short loc_11B0\nmov r9d, 0FFFFFFFFh\nmov r8d, 0\njmp short loc_118C\nloc_1180:\nlea r8d, [rax+1]\nmov r9d, eax\nloc_1187:\ncmp r8d, esi\njg short loc_11B6\nloc_118C:\nlea ecx, [r8+rsi]\nmov eax, ecx\nshr eax, 1Fh\nadd eax, ecx\nsar eax, 1\nmovsxd rcx, eax\nmov ecx, [rdi+rcx*4]\ncmp ecx, edx\njz short loc_1180\njle short loc_11AA\nlea esi, [rax-1]\njmp short loc_1187\nloc_11AA:\nlea r8d, [rax+1]\njmp short loc_1187\nloc_11B0:\nmov r9d, 0FFFFFFFFh\nloc_11B6:\nmov eax, r9d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n int v3; // esi\n unsigned int v4; // r9d\n int v5; // r8d\n int v6; // eax\n int v7; // ecx\n\n v3 = a2 - 1;\n if ( v3 < 0 )\n {\n return (unsigned int)-1;\n }\n else\n {\n v4 = -1;\n v5 = 0;\n do\n {\n v6 = (v5 + v3) / 2;\n v7 = *(_DWORD *)(a1 + 4LL * v6);\n if ( v7 == a3 )\n {\n v5 = v6 + 1;\n v4 = v6;\n }\n else if ( v7 <= a3 )\n {\n v5 = v6 + 1;\n }\n else\n {\n v3 = v6 - 1;\n }\n }\n while ( v5 <= v3 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n int v3;\n unsigned int v4;\n int v5;\n int v6;\n int v7;\n v3 = a2 - 1;\n if (v3 < 0) {\n return (unsigned int)-1;\n } else {\n v4 = -1;\n v5 = 0;\n do {\n v6 = (v5 + v3) / 2;\n v7 = *(uint32_t *)(a1 + 4LL * v6);\n if (v7 == a3) {\n v5 = v6 + 1;\n v4 = v6;\n } else if (v7 <= a3) {\n v5 = v6 + 1;\n } else {\n v3 = v6 - 1;\n }\n } while (v5 <= v3);\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n int v3;\n unsigned int v4;\n int v5;\n int v6;\n int v7;\n v3 = a2 - 1;\n if (v3 < 0) {\n return (unsigned int)-1;\n } else {\n v4 = -1;\n v5 = 0;\n do {\n v6 = (v5 + v3) / 2;\n v7 = *(uint32_t *)(a1 + 4LL * v6);\n if (v7 == a3) {\n v5 = v6 + 1;\n v4 = v6;\n } else if (v7 <= a3) {\n v5 = v6 + 1;\n } else {\n v3 = v6 - 1;\n }\n } while (v5 <= v3);\n }\n return v4;\n}" + }, + { + "index": 316, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int A[], int n, int x) {\n int left = 0;\n int right = n - 1;\n int result = -1;\n while (left <= right) {\n int mid = (left + right) / 2;\n if (x == A[mid]) {\n result = mid;\n left = mid + 1;\n } else if (x < A[mid]) {\n right = mid - 1;\n } else {\n left = mid + 1;\n }\n }\n return result;\n}", + "test": "int main() {\n\n int arr1[] = {2, 5, 5, 5, 6, 6, 8, 9, 9, 9};\n\n int arr2[] = {2, 3, 5, 8, 6, 6, 8, 9, 9, 9};\n\n int arr3[] = {2, 2, 1, 5, 6, 6, 6, 9, 9, 9};\n\n\n\n assert(func0(arr1, 10, 5) == 3);\n\n assert(func0(arr2, 10, 9) == 9);\n\n assert(func0(arr3, 10, 6) == 6);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov $0xffffffff,%r9d\nsub $0x1,%esi\njs 13d9 \nxor %ecx,%ecx\njmp 13c1 \nnopl 0x0(%rax,%rax,1)\njle 13e0 \nlea -0x1(%rax),%esi\ncmp %ecx,%esi\njl 13d9 \nlea (%rsi,%rcx,1),%eax\nsar %eax\nmovslq %eax,%r8\ncmp %edx,(%rdi,%r8,4)\njne 13b8 \nlea 0x1(%rax),%ecx\nmov %eax,%r9d\ncmp %ecx,%esi\njge 13c1 \nmov %r9d,%eax\nretq\nnopl (%rax)\nlea 0x1(%rax),%ecx\njmp 13bd \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmov r9d, 0FFFFFFFFh\nsub esi, 1\njs short loc_1303\nxor r8d, r8d\njmp short loc_12E2\nloc_12D8:\njge short loc_1310\nlea esi, [rax-1]\nloc_12DD:\ncmp r8d, esi\njg short loc_1303\nloc_12E2:\nlea ecx, [r8+rsi]\nmov eax, ecx\nshr eax, 1Fh\nadd eax, ecx\nsar eax, 1\nmovsxd rcx, eax\ncmp edx, [rdi+rcx*4]\njnz short loc_12D8\nlea r8d, [rax+1]\nmov r9d, eax\ncmp r8d, esi\njle short loc_12E2\nloc_1303:\nmov eax, r9d\nretn\nloc_1310:\nlea r8d, [rax+1]\njmp short loc_12DD", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n unsigned int v3; // r9d\n int v4; // esi\n int v5; // r8d\n int v6; // eax\n\n v3 = -1;\n v4 = a2 - 1;\n if ( v4 >= 0 )\n {\n v5 = 0;\n do\n {\n while ( 1 )\n {\n v6 = (v5 + v4) / 2;\n if ( a3 != *(_DWORD *)(a1 + 4LL * v6) )\n break;\n v5 = v6 + 1;\n v3 = v6;\n if ( v6 + 1 > v4 )\n return v3;\n }\n if ( a3 >= *(_DWORD *)(a1 + 4LL * v6) )\n v5 = v6 + 1;\n else\n v4 = v6 - 1;\n }\n while ( v5 <= v4 );\n }\n return v3;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\nmov r9d, 0FFFFFFFFh\nsub esi, 1\njs short loc_1303\nxor r8d, r8d\njmp short loc_12E2\nloc_12D8:\njge short loc_1310\nlea esi, [rax-1]\nloc_12DD:\ncmp r8d, esi\njg short loc_1303\nloc_12E2:\nlea ecx, [r8+rsi]\nmov eax, ecx\nshr eax, 1Fh\nadd eax, ecx\nsar eax, 1\nmovsxd rcx, eax\ncmp edx, [rdi+rcx*4]\njnz short loc_12D8\nlea r8d, [rax+1]\nmov r9d, eax\ncmp r8d, esi\njle short loc_12E2\nloc_1303:\nmov eax, r9d\nretn\nloc_1310:\nlea r8d, [rax+1]\njmp short loc_12DD", + "ida_strip_pseudo": "__int64 __fastcall sub_12C0(__int64 a1, int a2, int a3)\n{\n unsigned int v3; // r9d\n int v4; // esi\n int v5; // r8d\n int v6; // eax\n\n v3 = -1;\n v4 = a2 - 1;\n if ( v4 >= 0 )\n {\n v5 = 0;\n do\n {\n while ( 1 )\n {\n v6 = (v5 + v4) / 2;\n if ( a3 != *(_DWORD *)(a1 + 4LL * v6) )\n break;\n v5 = v6 + 1;\n v3 = v6;\n if ( v6 + 1 > v4 )\n return v3;\n }\n if ( a3 >= *(_DWORD *)(a1 + 4LL * v6) )\n v5 = v6 + 1;\n else\n v4 = v6 - 1;\n }\n while ( v5 <= v4 );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12C0(long long a1, int a2, int a3) {\n unsigned int v3;\n int v4;\n int v5;\n int v6;\n v3 = -1;\n v4 = a2 - 1;\n if (v4 >= 0) {\n v5 = 0;\n do {\n while (1) {\n v6 = (v5 + v4) / 2;\n if (a3 != *(uint32_t *)(a1 + 4LL * v6)) break;\n v5 = v6 + 1;\n v3 = v6;\n if (v6 + 1 > v4) return v3;\n }\n if (a3 >= *(uint32_t *)(a1 + 4LL * v6))\n v5 = v6 + 1;\n else\n v4 = v6 - 1;\n } while (v5 <= v4);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n unsigned int v3;\n int v4;\n int v5;\n int v6;\n v3 = -1;\n v4 = a2 - 1;\n if (v4 >= 0) {\n v5 = 0;\n do {\n while (1) {\n v6 = (v5 + v4) / 2;\n if (a3 != *(uint32_t *)(a1 + 4LL * v6)) break;\n v5 = v6 + 1;\n v3 = v6;\n if (v6 + 1 > v4) return v3;\n }\n if (a3 >= *(uint32_t *)(a1 + 4LL * v6))\n v5 = v6 + 1;\n else\n v4 = v6 - 1;\n } while (v5 <= v4);\n }\n return v3;\n}" + }, + { + "index": 317, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int count;\n\n char value;\n\n} Element;\n\n\n\ntypedef struct {\n\n int is_pair;\n\n union {\n\n char single;\n\n Element pair;\n\n } data;\n\n} EncodedValue;\n\n\n\n", + "func": "EncodedValue* func0(char* alist, int* return_size) {\n int alist_len = strlen(alist);\n EncodedValue* result =\n (EncodedValue*)malloc(sizeof(EncodedValue) * alist_len);\n int i = 0;\n int res_idx = 0;\n while (i < alist_len) {\n char current = alist[i];\n int count = 1;\n while (i + 1 < alist_len && alist[i + 1] == current) {\n count++;\n i++;\n }\n if (count > 1) {\n result[res_idx].is_pair = 1;\n result[res_idx].data.pair = (Element){count, current};\n } else {\n result[res_idx].is_pair = 0;\n result[res_idx].data.single = current;\n }\n res_idx++;\n i++;\n }\n *return_size = res_idx;\n return result;\n}", + "test": "int main() {\n\n int size;\n\n\n\n EncodedValue *test1 = func0(\"11234451\", &size);\n\n assert(size == 6);\n\n assert(test1[0].is_pair && test1[0].data.pair.count == 2 && test1[0].data.pair.value == '1');\n\n assert(!test1[1].is_pair && test1[1].data.single == '2');\n\n assert(!test1[2].is_pair && test1[2].data.single == '3');\n\n assert(test1[3].is_pair && test1[3].data.pair.count == 2 && test1[3].data.pair.value == '4');\n\n assert(!test1[4].is_pair && test1[4].data.single == '5');\n\n assert(!test1[5].is_pair && test1[5].data.single == '1');\n\n free(test1);\n\n\n\n EncodedValue *test2 = func0(\"automatically\", &size);\n\n assert(size == 12);\n\n assert(!test2[0].is_pair && test2[0].data.single == 'a');\n\n assert(!test2[1].is_pair && test2[1].data.single == 'u');\n\n assert(test2[10].is_pair && test2[10].data.pair.count == 2 && test2[10].data.pair.value == 'l');\n\n assert(!test2[11].is_pair && test2[11].data.single == 'y');\n\n free(test2);\n\n\n\n EncodedValue *test3 = func0(\"python\", &size);\n\n assert(size == 6);\n\n assert(!test3[0].is_pair && test3[0].data.single == 'p');\n\n assert(!test3[1].is_pair && test3[1].data.single == 'y');\n\n free(test3);\n\n\n\n printf(\"All tests passed!\\n\");\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x28(%rbp)\nmov %rsi,-0x30(%rbp)\nmov -0x28(%rbp),%rax\nmov %rax,%rdi\ncallq 10c0 \nmov %eax,-0xc(%rbp)\nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10f0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0x18(%rbp)\nmovl $0x0,-0x14(%rbp)\njmpq 1329 \nmov -0x18(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmov %al,-0x19(%rbp)\nmovl $0x1,-0x10(%rbp)\njmp 1262 \naddl $0x1,-0x10(%rbp)\naddl $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%eax\nadd $0x1,%eax\ncmp %eax,-0xc(%rbp)\njle 1285 \nmov -0x18(%rbp),%eax\ncltq\nlea 0x1(%rax),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp %al,-0x19(%rbp)\nje 125a \ncmpl $0x1,-0x10(%rbp)\njle 12da \nmov -0x14(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmovl $0x1,(%rax)\nmov -0x14(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov -0x10(%rbp),%edx\nmov %edx,0x4(%rax)\nmovzbl -0x19(%rbp),%edx\nmov %dl,0x8(%rax)\njmp 1321 \nmov -0x14(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmovl $0x0,(%rax)\nmov -0x14(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmovzbl -0x19(%rbp),%eax\nmov %al,0x4(%rdx)\naddl $0x1,-0x14(%rbp)\naddl $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%eax\ncmp -0xc(%rbp),%eax\njl 123e \nmov -0x30(%rbp),%rax\nmov -0x14(%rbp),%edx\nmov %edx,(%rax)\nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov [rbp+var_30], rsi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_C], eax\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp loc_1329\nloc_123E:\nmov eax, [rbp+var_18]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_19], al\nmov [rbp+var_10], 1\njmp short loc_1262\nloc_125A:\nadd [rbp+var_10], 1\nadd [rbp+var_18], 1\nloc_1262:\nmov eax, [rbp+var_18]\nadd eax, 1\ncmp [rbp+var_C], eax\njle short loc_1285\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, [rax+1]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp [rbp+var_19], al\njz short loc_125A\nloc_1285:\ncmp [rbp+var_10], 1\njle short loc_12DA\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov dword ptr [rax], 1\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rbp+var_10]\nmov [rax+4], edx\nmovzx edx, [rbp+var_19]\nmov [rax+8], dl\njmp short loc_1321\nloc_12DA:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov dword ptr [rax], 0\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_8]\nadd rdx, rax\nmovzx eax, [rbp+var_19]\nmov [rdx+4], al\nloc_1321:\nadd [rbp+var_14], 1\nadd [rbp+var_18], 1\nloc_1329:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_C]\njl loc_123E\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_14]\nmov [rax], edx\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(const char *a1, _DWORD *a2)\n{\n char *v2; // rax\n char v4; // [rsp+17h] [rbp-19h]\n int v5; // [rsp+18h] [rbp-18h]\n int v6; // [rsp+1Ch] [rbp-14h]\n int v7; // [rsp+20h] [rbp-10h]\n int v8; // [rsp+24h] [rbp-Ch]\n _DWORD *v9; // [rsp+28h] [rbp-8h]\n\n v8 = strlen(a1);\n v9 = malloc(12LL * v8);\n v5 = 0;\n v6 = 0;\n while ( v5 < v8 )\n {\n v4 = a1[v5];\n v7 = 1;\n while ( v8 > v5 + 1 && v4 == a1[v5 + 1] )\n {\n ++v7;\n ++v5;\n }\n if ( v7 <= 1 )\n {\n v9[3 * v6] = 0;\n LOBYTE(v9[3 * v6 + 1]) = v4;\n }\n else\n {\n v9[3 * v6] = 1;\n v2 = (char *)&v9[3 * v6];\n *((_DWORD *)v2 + 1) = v7;\n v2[8] = v4;\n }\n ++v6;\n ++v5;\n }\n *a2 = v6;\n return v9;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov [rbp+var_30], rsi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_C], eax\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp loc_1329\nloc_123E:\nmov eax, [rbp+var_18]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_19], al\nmov [rbp+var_10], 1\njmp short loc_1262\nloc_125A:\nadd [rbp+var_10], 1\nadd [rbp+var_18], 1\nloc_1262:\nmov eax, [rbp+var_18]\nadd eax, 1\ncmp [rbp+var_C], eax\njle short loc_1285\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, [rax+1]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp [rbp+var_19], al\njz short loc_125A\nloc_1285:\ncmp [rbp+var_10], 1\njle short loc_12DA\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov dword ptr [rax], 1\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rbp+var_10]\nmov [rax+4], edx\nmovzx edx, [rbp+var_19]\nmov [rax+8], dl\njmp short loc_1321\nloc_12DA:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov dword ptr [rax], 0\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_8]\nadd rdx, rax\nmovzx eax, [rbp+var_19]\nmov [rdx+4], al\nloc_1321:\nadd [rbp+var_14], 1\nadd [rbp+var_18], 1\nloc_1329:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_C]\njl loc_123E\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_14]\nmov [rax], edx\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11E9(const char *a1, _DWORD *a2)\n{\n char *v2; // rax\n char v4; // [rsp+17h] [rbp-19h]\n int v5; // [rsp+18h] [rbp-18h]\n int v6; // [rsp+1Ch] [rbp-14h]\n int v7; // [rsp+20h] [rbp-10h]\n int v8; // [rsp+24h] [rbp-Ch]\n _DWORD *v9; // [rsp+28h] [rbp-8h]\n\n v8 = strlen(a1);\n v9 = malloc(12LL * v8);\n v5 = 0;\n v6 = 0;\n while ( v5 < v8 )\n {\n v4 = a1[v5];\n v7 = 1;\n while ( v8 > v5 + 1 && v4 == a1[v5 + 1] )\n {\n ++v7;\n ++v5;\n }\n if ( v7 <= 1 )\n {\n v9[3 * v6] = 0;\n LOBYTE(v9[3 * v6 + 1]) = v4;\n }\n else\n {\n v9[3 * v6] = 1;\n v2 = (char *)&v9[3 * v6];\n *((_DWORD *)v2 + 1) = v7;\n v2[8] = v4;\n }\n ++v6;\n ++v5;\n }\n *a2 = v6;\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11E9(const char *a1, uint32_t *a2) {\n char *v2;\n char v4;\n int v5;\n int v6;\n int v7;\n int v8;\n uint32_t *v9;\n v8 = strlen(a1);\n v9 = malloc(12LL * v8);\n v5 = 0;\n v6 = 0;\n while (v5 < v8) {\n v4 = a1[v5];\n v7 = 1;\n while (v8 > v5 + 1 && v4 == a1[v5 + 1]) {\n ++v7;\n ++v5;\n }\n if (v7 <= 1) {\n v9[3 * v6] = 0;\n LOBYTE(v9[3 * v6 + 1]) = v4;\n } else {\n v9[3 * v6] = 1;\n v2 = (char *)&v9[3 * v6];\n *((uint32_t *)v2 + 1) = v7;\n v2[8] = v4;\n }\n ++v6;\n ++v5;\n }\n *a2 = v6;\n return v9;\n}", + "ida_pseudo_norm": "uint32_t *func0(const char *a1, uint32_t *a2) {\n char *v2;\n char v4;\n int v5;\n int v6;\n int v7;\n int v8;\n uint32_t *v9;\n v8 = strlen(a1);\n v9 = malloc(12LL * v8);\n v5 = 0;\n v6 = 0;\n while (v5 < v8) {\n v4 = a1[v5];\n v7 = 1;\n while (v8 > v5 + 1 && v4 == a1[v5 + 1]) {\n ++v7;\n ++v5;\n }\n if (v7 <= 1) {\n v9[3 * v6] = 0;\n LOBYTE(v9[3 * v6 + 1]) = v4;\n } else {\n v9[3 * v6] = 1;\n v2 = (char *)&v9[3 * v6];\n *((uint32_t *)v2 + 1) = v7;\n v2[8] = v4;\n }\n ++v6;\n ++v5;\n }\n *a2 = v6;\n return v9;\n}" + }, + { + "index": 317, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int count;\n\n char value;\n\n} Element;\n\n\n\ntypedef struct {\n\n int is_pair;\n\n union {\n\n char single;\n\n Element pair;\n\n } data;\n\n} EncodedValue;\n\n\n\n", + "func": "EncodedValue* func0(char* alist, int* return_size) {\n int alist_len = strlen(alist);\n EncodedValue* result =\n (EncodedValue*)malloc(sizeof(EncodedValue) * alist_len);\n int i = 0;\n int res_idx = 0;\n while (i < alist_len) {\n char current = alist[i];\n int count = 1;\n while (i + 1 < alist_len && alist[i + 1] == current) {\n count++;\n i++;\n }\n if (count > 1) {\n result[res_idx].is_pair = 1;\n result[res_idx].data.pair = (Element){count, current};\n } else {\n result[res_idx].is_pair = 0;\n result[res_idx].data.single = current;\n }\n res_idx++;\n i++;\n }\n *return_size = res_idx;\n return result;\n}", + "test": "int main() {\n\n int size;\n\n\n\n EncodedValue *test1 = func0(\"11234451\", &size);\n\n assert(size == 6);\n\n assert(test1[0].is_pair && test1[0].data.pair.count == 2 && test1[0].data.pair.value == '1');\n\n assert(!test1[1].is_pair && test1[1].data.single == '2');\n\n assert(!test1[2].is_pair && test1[2].data.single == '3');\n\n assert(test1[3].is_pair && test1[3].data.pair.count == 2 && test1[3].data.pair.value == '4');\n\n assert(!test1[4].is_pair && test1[4].data.single == '5');\n\n assert(!test1[5].is_pair && test1[5].data.single == '1');\n\n free(test1);\n\n\n\n EncodedValue *test2 = func0(\"automatically\", &size);\n\n assert(size == 12);\n\n assert(!test2[0].is_pair && test2[0].data.single == 'a');\n\n assert(!test2[1].is_pair && test2[1].data.single == 'u');\n\n assert(test2[10].is_pair && test2[10].data.pair.count == 2 && test2[10].data.pair.value == 'l');\n\n assert(!test2[11].is_pair && test2[11].data.single == 'y');\n\n free(test2);\n\n\n\n EncodedValue *test3 = func0(\"python\", &size);\n\n assert(size == 6);\n\n assert(!test3[0].is_pair && test3[0].data.single == 'p');\n\n assert(!test3[1].is_pair && test3[1].data.single == 'y');\n\n free(test3);\n\n\n\n printf(\"All tests passed!\\n\");\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbx\nmov %rsi,%r13\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rbp\nmovslq %ebp,%rax\nlea (%rax,%rax,2),%rdi\nshl $0x2,%rdi\ncallq 10d0 \ntest %ebp,%ebp\njle 1286 \nmov %ebp,%r12d\nmov %rax,%r9\nmov $0x0,%r10d\nmov $0x0,%edx\njmp 123f \ncmp $0x1,%edx\njle 1277 \nmovl $0x1,(%r9)\nmov %edx,0x4(%r9)\nmov %dil,0x8(%r9)\nmov %esi,%edx\nadd $0x1,%r10d\nadd $0xc,%r9\ncmp %r12d,%edx\njge 128c \nmovslq %edx,%rcx\nmovzbl (%rbx,%rcx,1),%edi\nlea 0x1(%rdx),%esi\ncmp %esi,%r12d\njle 1277 \nlea 0x1(%rbx,%rcx,1),%rcx\nmov %ebp,%r8d\nsub %edx,%r8d\nmov $0x1,%edx\ncmp %dil,(%rcx)\njne 121c \nadd $0x1,%edx\nadd $0x1,%esi\nadd $0x1,%rcx\ncmp %r8d,%edx\njne 125e \nmov %r8d,%edx\njmp 121c \nmovl $0x0,(%r9)\nmov %dil,0x4(%r9)\nmov %esi,%edx\njmp 1232 \nmov $0x0,%r10d\nmov %r10d,0x0(%r13)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov r13, rsi\ncall _strlen\nmov r12, rax\nmov ebp, eax\ncdqe\nlea rdi, [rax+rax*2]\nshl rdi, 2; size\ncall _malloc\ntest r12d, r12d\njle short loc_1293\nmov r9, rax\nmov r10d, 0\nmov edx, 0\njmp short loc_124D\nloc_122B:\ncmp edx, 1\njle short loc_1284\nmov dword ptr [r9], 1\nmov [r9+4], edx\nmov [r9+8], dil\nmov edx, esi\nloc_1241:\nadd r10d, 1\nadd r9, 0Ch\ncmp edx, ebp\njge short loc_1299\nloc_124D:\nmovsxd rcx, edx\nmovzx edi, byte ptr [rbx+rcx]\nlea esi, [rdx+1]\ncmp ebp, esi\njle short loc_1284\nlea rcx, [rbx+rcx+1]\nmov r8d, r12d\nsub r8d, edx\nmov edx, 1\nloc_126B:\ncmp [rcx], dil\njnz short loc_122B\nadd edx, 1\nadd esi, 1\nadd rcx, 1\ncmp edx, r8d\njnz short loc_126B\nmov edx, r8d\njmp short loc_122B\nloc_1284:\nmov dword ptr [r9], 0\nmov [r9+4], dil\nmov edx, esi\njmp short loc_1241\nloc_1293:\nmov r10d, 0\nloc_1299:\nmov [r13+0], r10d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "char *__fastcall func0(const char *a1, _DWORD *a2)\n{\n int v4; // r12d\n char *result; // rax\n char *v6; // r9\n int v7; // r10d\n int v8; // edx\n char v9; // di\n int v10; // esi\n const char *v11; // rcx\n int v12; // r8d\n int v13; // edx\n\n v4 = strlen(a1);\n result = (char *)malloc(12LL * v4);\n if ( v4 <= 0 )\n {\n v7 = 0;\n }\n else\n {\n v6 = result;\n v7 = 0;\n v8 = 0;\n do\n {\n v9 = a1[v8];\n v10 = v8 + 1;\n if ( v4 <= v8 + 1 )\n goto LABEL_11;\n v11 = &a1[v8 + 1];\n v12 = v4 - v8;\n v13 = 1;\n while ( *v11 == v9 )\n {\n ++v13;\n ++v10;\n ++v11;\n if ( v13 == v12 )\n {\n v13 = v12;\n break;\n }\n }\n if ( v13 <= 1 )\n {\nLABEL_11:\n *(_DWORD *)v6 = 0;\n v6[4] = v9;\n v8 = v10;\n }\n else\n {\n *(_DWORD *)v6 = 1;\n *((_DWORD *)v6 + 1) = v13;\n v6[8] = v9;\n v8 = v10;\n }\n ++v7;\n v6 += 12;\n }\n while ( v8 < v4 );\n }\n *a2 = v7;\n return result;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov r13, rsi\ncall _strlen\nmov r12, rax\nmov ebp, eax\ncdqe\nlea rdi, [rax+rax*2]\nshl rdi, 2; size\ncall _malloc\ntest r12d, r12d\njle short loc_1293\nmov r9, rax\nmov r10d, 0\nmov edx, 0\njmp short loc_124D\nloc_122B:\ncmp edx, 1\njle short loc_1284\nmov dword ptr [r9], 1\nmov [r9+4], edx\nmov [r9+8], dil\nmov edx, esi\nloc_1241:\nadd r10d, 1\nadd r9, 0Ch\ncmp edx, ebp\njge short loc_1299\nloc_124D:\nmovsxd rcx, edx\nmovzx edi, byte ptr [rbx+rcx]\nlea esi, [rdx+1]\ncmp ebp, esi\njle short loc_1284\nlea rcx, [rbx+rcx+1]\nmov r8d, r12d\nsub r8d, edx\nmov edx, 1\nloc_126B:\ncmp [rcx], dil\njnz short loc_122B\nadd edx, 1\nadd esi, 1\nadd rcx, 1\ncmp edx, r8d\njnz short loc_126B\nmov edx, r8d\njmp short loc_122B\nloc_1284:\nmov dword ptr [r9], 0\nmov [r9+4], dil\nmov edx, esi\njmp short loc_1241\nloc_1293:\nmov r10d, 0\nloc_1299:\nmov [r13+0], r10d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11E9(const char *a1, _DWORD *a2)\n{\n int v4; // r12d\n char *result; // rax\n char *v6; // r9\n int v7; // r10d\n int v8; // edx\n char v9; // di\n int v10; // esi\n const char *v11; // rcx\n int v12; // r8d\n int v13; // edx\n\n v4 = strlen(a1);\n result = (char *)malloc(12LL * v4);\n if ( v4 <= 0 )\n {\n v7 = 0;\n }\n else\n {\n v6 = result;\n v7 = 0;\n v8 = 0;\n do\n {\n v9 = a1[v8];\n v10 = v8 + 1;\n if ( v4 <= v8 + 1 )\n goto LABEL_11;\n v11 = &a1[v8 + 1];\n v12 = v4 - v8;\n v13 = 1;\n while ( *v11 == v9 )\n {\n ++v13;\n ++v10;\n ++v11;\n if ( v13 == v12 )\n {\n v13 = v12;\n break;\n }\n }\n if ( v13 <= 1 )\n {\nLABEL_11:\n *(_DWORD *)v6 = 0;\n v6[4] = v9;\n v8 = v10;\n }\n else\n {\n *(_DWORD *)v6 = 1;\n *((_DWORD *)v6 + 1) = v13;\n v6[8] = v9;\n v8 = v10;\n }\n ++v7;\n v6 += 12;\n }\n while ( v8 < v4 );\n }\n *a2 = v7;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11E9(const char *a1, uint32_t *a2) {\n int v4;\n char *result;\n char *v6;\n int v7;\n int v8;\n char v9;\n int v10;\n const char *v11;\n int v12;\n int v13;\n v4 = strlen(a1);\n result = (char *)malloc(12LL * v4);\n if (v4 <= 0) {\n v7 = 0;\n } else {\n v6 = result;\n v7 = 0;\n v8 = 0;\n do {\n v9 = a1[v8];\n v10 = v8 + 1;\n if (v4 <= v8 + 1) goto LABEL_11;\n v11 = &a1[v8 + 1];\n v12 = v4 - v8;\n v13 = 1;\n while (*v11 == v9) {\n ++v13;\n ++v10;\n ++v11;\n if (v13 == v12) {\n v13 = v12;\n break;\n }\n }\n if (v13 <= 1) {\n LABEL_11:\n *(uint32_t *)v6 = 0;\n v6[4] = v9;\n v8 = v10;\n } else {\n *(uint32_t *)v6 = 1;\n *((uint32_t *)v6 + 1) = v13;\n v6[8] = v9;\n v8 = v10;\n }\n ++v7;\n v6 += 12;\n } while (v8 < v4);\n }\n *a2 = v7;\n return result;\n}", + "ida_pseudo_norm": "char *func0(const char *a1, uint32_t *a2) {\n int v4;\n char *result;\n char *v6;\n int v7;\n int v8;\n char v9;\n int v10;\n const char *v11;\n int v12;\n int v13;\n v4 = strlen(a1);\n result = (char *)malloc(12LL * v4);\n if (v4 <= 0) {\n v7 = 0;\n } else {\n v6 = result;\n v7 = 0;\n v8 = 0;\n do {\n v9 = a1[v8];\n v10 = v8 + 1;\n if (v4 <= v8 + 1) goto LABEL_11;\n v11 = &a1[v8 + 1];\n v12 = v4 - v8;\n v13 = 1;\n while (*v11 == v9) {\n ++v13;\n ++v10;\n ++v11;\n if (v13 == v12) {\n v13 = v12;\n break;\n }\n }\n if (v13 <= 1) {\n LABEL_11:\n *(uint32_t *)v6 = 0;\n v6[4] = v9;\n v8 = v10;\n } else {\n *(uint32_t *)v6 = 1;\n *((uint32_t *)v6 + 1) = v13;\n v6[8] = v9;\n v8 = v10;\n }\n ++v7;\n v6 += 12;\n } while (v8 < v4);\n }\n *a2 = v7;\n return result;\n}" + }, + { + "index": 317, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int count;\n\n char value;\n\n} Element;\n\n\n\ntypedef struct {\n\n int is_pair;\n\n union {\n\n char single;\n\n Element pair;\n\n } data;\n\n} EncodedValue;\n\n\n\n", + "func": "EncodedValue* func0(char* alist, int* return_size) {\n int alist_len = strlen(alist);\n EncodedValue* result =\n (EncodedValue*)malloc(sizeof(EncodedValue) * alist_len);\n int i = 0;\n int res_idx = 0;\n while (i < alist_len) {\n char current = alist[i];\n int count = 1;\n while (i + 1 < alist_len && alist[i + 1] == current) {\n count++;\n i++;\n }\n if (count > 1) {\n result[res_idx].is_pair = 1;\n result[res_idx].data.pair = (Element){count, current};\n } else {\n result[res_idx].is_pair = 0;\n result[res_idx].data.single = current;\n }\n res_idx++;\n i++;\n }\n *return_size = res_idx;\n return result;\n}", + "test": "int main() {\n\n int size;\n\n\n\n EncodedValue *test1 = func0(\"11234451\", &size);\n\n assert(size == 6);\n\n assert(test1[0].is_pair && test1[0].data.pair.count == 2 && test1[0].data.pair.value == '1');\n\n assert(!test1[1].is_pair && test1[1].data.single == '2');\n\n assert(!test1[2].is_pair && test1[2].data.single == '3');\n\n assert(test1[3].is_pair && test1[3].data.pair.count == 2 && test1[3].data.pair.value == '4');\n\n assert(!test1[4].is_pair && test1[4].data.single == '5');\n\n assert(!test1[5].is_pair && test1[5].data.single == '1');\n\n free(test1);\n\n\n\n EncodedValue *test2 = func0(\"automatically\", &size);\n\n assert(size == 12);\n\n assert(!test2[0].is_pair && test2[0].data.single == 'a');\n\n assert(!test2[1].is_pair && test2[1].data.single == 'u');\n\n assert(test2[10].is_pair && test2[10].data.pair.count == 2 && test2[10].data.pair.value == 'l');\n\n assert(!test2[11].is_pair && test2[11].data.single == 'y');\n\n free(test2);\n\n\n\n EncodedValue *test3 = func0(\"python\", &size);\n\n assert(size == 6);\n\n assert(!test3[0].is_pair && test3[0].data.single == 'p');\n\n assert(!test3[1].is_pair && test3[1].data.single == 'y');\n\n free(test3);\n\n\n\n printf(\"All tests passed!\\n\");\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov %rsi,%r13\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nsub $0x8,%rsp\ncallq 10c0 \nmov %rax,%r12\nmov %eax,%ebp\ncltq\nlea (%rax,%rax,2),%rdi\nshl $0x2,%rdi\ncallq 10f0 \ntest %r12d,%r12d\njle 1666 \nmov %rax,%r10\nxor %r11d,%r11d\nxor %edx,%edx\nxchg %ax,%ax\nmovslq %edx,%rcx\nlea 0x1(%rdx),%edi\nmovzbl (%rbx,%rcx,1),%r8d\ncmp %edi,%ebp\njle 1621 \nmov %r12d,%r9d\nlea 0x1(%rbx,%rcx,1),%rcx\nsub %edx,%r9d\nmov $0x1,%edx\njmp 1617 \nnopl 0x0(%rax)\nadd $0x1,%edx\nadd $0x1,%edi\nadd $0x1,%rcx\ncmp %r9d,%edx\nje 1653 \ncmp %r8b,(%rcx)\nje 1608 \ncmp $0x1,%edx\njne 1650 \nmovl $0x0,(%r10)\nmov %edi,%edx\nmov %r8b,0x4(%r10)\nadd $0x1,%r11d\nadd $0xc,%r10\ncmp %ebp,%edi\njl 15e0 \nmov %r11d,0x0(%r13)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax)\nmov %edx,%r9d\nmovl $0x1,(%r10)\nmov %edi,%edx\nmov %r9d,0x4(%r10)\nmov %r8b,0x8(%r10)\njmp 162e \nxor %r11d,%r11d\nmov %r11d,0x0(%r13)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r13\nmov r13, rsi\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\nmov r12, rax\nmov ebp, eax\ncdqe\nlea rdi, [rax+rax*2]\nshl rdi, 2; size\ncall _malloc\ntest r12d, r12d\njle loc_167B\nmov r9, rax\nxor r10d, r10d\nxor esi, esi\nxchg ax, ax\nloc_15E0:\nmovsxd rdx, esi\nmovzx edi, byte ptr [rbx+rdx]\nlea edx, [rsi+1]\ncmp ebp, edx\njle short loc_165D\nmov r8d, r12d\nmovsxd rdx, edx\nmov ecx, 1\nsub r8d, esi\njmp short loc_160C\nloc_1600:\nadd ecx, 1\nadd rdx, 1\ncmp ecx, r8d\njz short loc_1640\nloc_160C:\nmov esi, edx\ncmp [rbx+rdx], dil\njz short loc_1600\ncmp ecx, 1\njnz short loc_1658\nmov dword ptr [r9], 0\nmov [r9+4], dil\nloc_1624:\nadd r10d, 1\nadd r9, 0Ch\ncmp esi, ebp\njl short loc_15E0\nmov [r13+0], r10d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1640:\nadd esi, 1\nloc_1643:\nmov dword ptr [r9], 1\nmov [r9+4], r8d\nmov [r9+8], dil\njmp short loc_1624\nloc_1658:\nmov r8d, ecx\njmp short loc_1643\nloc_165D:\nadd r10d, 1\nmov dword ptr [r9], 0\nmov [r9+4], dil\nmov [r13+0], r10d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_167B:\nxor r10d, r10d\nmov [r13+0], r10d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "char *__fastcall func0(const char *a1, _DWORD *a2)\n{\n int v4; // r12d\n char *result; // rax\n char *v6; // r9\n int v7; // r10d\n int v8; // esi\n char v9; // di\n __int64 v10; // rdx\n int v11; // ecx\n int v12; // r8d\n\n v4 = strlen(a1);\n result = (char *)malloc(12LL * v4);\n if ( v4 <= 0 )\n {\n *a2 = 0;\n }\n else\n {\n v6 = result;\n v7 = 0;\n v8 = 0;\n while ( 1 )\n {\n v9 = a1[v8];\n LODWORD(v10) = v8 + 1;\n if ( v4 <= v8 + 1 )\n break;\n v10 = (int)v10;\n v11 = 1;\n v12 = v4 - v8;\n while ( 1 )\n {\n v8 = v10;\n if ( a1[v10] != v9 )\n break;\n ++v11;\n ++v10;\n if ( v11 == v12 )\n {\n ++v8;\n goto LABEL_12;\n }\n }\n if ( v11 == 1 )\n {\n *(_DWORD *)v6 = 0;\n v6[4] = v9;\n goto LABEL_9;\n }\n v12 = v11;\nLABEL_12:\n *(_DWORD *)v6 = 1;\n *((_DWORD *)v6 + 1) = v12;\n v6[8] = v9;\nLABEL_9:\n ++v7;\n v6 += 12;\n if ( v8 >= v4 )\n {\n *a2 = v7;\n return result;\n }\n }\n *(_DWORD *)v6 = 0;\n v6[4] = v9;\n *a2 = v7 + 1;\n }\n return result;\n}", + "ida_strip_asm": "sub_15A0:\nendbr64\npush r13\nmov r13, rsi\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\nmov r12, rax\nmov ebp, eax\ncdqe\nlea rdi, [rax+rax*2]\nshl rdi, 2; size\ncall _malloc\ntest r12d, r12d\njle loc_167B\nmov r9, rax\nxor r10d, r10d\nxor esi, esi\nxchg ax, ax\nloc_15E0:\nmovsxd rdx, esi\nmovzx edi, byte ptr [rbx+rdx]\nlea edx, [rsi+1]\ncmp ebp, edx\njle short loc_165D\nmov r8d, r12d\nmovsxd rdx, edx\nmov ecx, 1\nsub r8d, esi\njmp short loc_160C\nloc_1600:\nadd ecx, 1\nadd rdx, 1\ncmp ecx, r8d\njz short loc_1640\nloc_160C:\nmov esi, edx\ncmp [rbx+rdx], dil\njz short loc_1600\ncmp ecx, 1\njnz short loc_1658\nmov dword ptr [r9], 0\nmov [r9+4], dil\nloc_1624:\nadd r10d, 1\nadd r9, 0Ch\ncmp esi, ebp\njl short loc_15E0\nmov [r13+0], r10d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1640:\nadd esi, 1\nloc_1643:\nmov dword ptr [r9], 1\nmov [r9+4], r8d\nmov [r9+8], dil\njmp short loc_1624\nloc_1658:\nmov r8d, ecx\njmp short loc_1643\nloc_165D:\nadd r10d, 1\nmov dword ptr [r9], 0\nmov [r9+4], dil\nmov [r13+0], r10d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_167B:\nxor r10d, r10d\nmov [r13+0], r10d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "char *__fastcall sub_15A0(const char *a1, _DWORD *a2)\n{\n int v4; // r12d\n char *result; // rax\n char *v6; // r9\n int v7; // r10d\n int v8; // esi\n char v9; // di\n __int64 v10; // rdx\n int v11; // ecx\n int v12; // r8d\n\n v4 = strlen(a1);\n result = (char *)malloc(12LL * v4);\n if ( v4 <= 0 )\n {\n *a2 = 0;\n }\n else\n {\n v6 = result;\n v7 = 0;\n v8 = 0;\n while ( 1 )\n {\n v9 = a1[v8];\n LODWORD(v10) = v8 + 1;\n if ( v4 <= v8 + 1 )\n break;\n v10 = (int)v10;\n v11 = 1;\n v12 = v4 - v8;\n while ( 1 )\n {\n v8 = v10;\n if ( a1[v10] != v9 )\n break;\n ++v11;\n ++v10;\n if ( v11 == v12 )\n {\n ++v8;\n goto LABEL_12;\n }\n }\n if ( v11 == 1 )\n {\n *(_DWORD *)v6 = 0;\n v6[4] = v9;\n goto LABEL_9;\n }\n v12 = v11;\nLABEL_12:\n *(_DWORD *)v6 = 1;\n *((_DWORD *)v6 + 1) = v12;\n v6[8] = v9;\nLABEL_9:\n ++v7;\n v6 += 12;\n if ( v8 >= v4 )\n {\n *a2 = v7;\n return result;\n }\n }\n *(_DWORD *)v6 = 0;\n v6[4] = v9;\n *a2 = v7 + 1;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_15A0(const char *a1, uint32_t *a2) {\n int v4;\n char *result;\n char *v6;\n int v7;\n int v8;\n char v9;\n long long v10;\n int v11;\n int v12;\n v4 = strlen(a1);\n result = (char *)malloc(12LL * v4);\n if (v4 <= 0) {\n *a2 = 0;\n } else {\n v6 = result;\n v7 = 0;\n v8 = 0;\n while (1) {\n v9 = a1[v8];\n LODWORD(v10) = v8 + 1;\n if (v4 <= v8 + 1) break;\n v10 = (int)v10;\n v11 = 1;\n v12 = v4 - v8;\n while (1) {\n v8 = v10;\n if (a1[v10] != v9) break;\n ++v11;\n ++v10;\n if (v11 == v12) {\n ++v8;\n goto LABEL_12;\n }\n }\n if (v11 == 1) {\n *(uint32_t *)v6 = 0;\n v6[4] = v9;\n goto LABEL_9;\n }\n v12 = v11;\n LABEL_12:\n *(uint32_t *)v6 = 1;\n *((uint32_t *)v6 + 1) = v12;\n v6[8] = v9;\n LABEL_9:\n ++v7;\n v6 += 12;\n if (v8 >= v4) {\n *a2 = v7;\n return result;\n }\n }\n *(uint32_t *)v6 = 0;\n v6[4] = v9;\n *a2 = v7 + 1;\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(const char *a1, uint32_t *a2) {\n int v4;\n char *result;\n char *v6;\n int v7;\n int v8;\n char v9;\n long long v10;\n int v11;\n int v12;\n v4 = strlen(a1);\n result = (char *)malloc(12LL * v4);\n if (v4 <= 0) {\n *a2 = 0;\n } else {\n v6 = result;\n v7 = 0;\n v8 = 0;\n while (1) {\n v9 = a1[v8];\n LODWORD(v10) = v8 + 1;\n if (v4 <= v8 + 1) break;\n v10 = (int)v10;\n v11 = 1;\n v12 = v4 - v8;\n while (1) {\n v8 = v10;\n if (a1[v10] != v9) break;\n ++v11;\n ++v10;\n if (v11 == v12) {\n ++v8;\n goto LABEL_12;\n }\n }\n if (v11 == 1) {\n *(uint32_t *)v6 = 0;\n v6[4] = v9;\n goto LABEL_9;\n }\n v12 = v11;\n LABEL_12:\n *(uint32_t *)v6 = 1;\n *((uint32_t *)v6 + 1) = v12;\n v6[8] = v9;\n LABEL_9:\n ++v7;\n v6 += 12;\n if (v8 >= v4) {\n *a2 = v7;\n return result;\n }\n }\n *(uint32_t *)v6 = 0;\n v6[4] = v9;\n *a2 = v7 + 1;\n }\n return result;\n}" + }, + { + "index": 317, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int count;\n\n char value;\n\n} Element;\n\n\n\ntypedef struct {\n\n int is_pair;\n\n union {\n\n char single;\n\n Element pair;\n\n } data;\n\n} EncodedValue;\n\n\n\n", + "func": "EncodedValue* func0(char* alist, int* return_size) {\n int alist_len = strlen(alist);\n EncodedValue* result =\n (EncodedValue*)malloc(sizeof(EncodedValue) * alist_len);\n int i = 0;\n int res_idx = 0;\n while (i < alist_len) {\n char current = alist[i];\n int count = 1;\n while (i + 1 < alist_len && alist[i + 1] == current) {\n count++;\n i++;\n }\n if (count > 1) {\n result[res_idx].is_pair = 1;\n result[res_idx].data.pair = (Element){count, current};\n } else {\n result[res_idx].is_pair = 0;\n result[res_idx].data.single = current;\n }\n res_idx++;\n i++;\n }\n *return_size = res_idx;\n return result;\n}", + "test": "int main() {\n\n int size;\n\n\n\n EncodedValue *test1 = func0(\"11234451\", &size);\n\n assert(size == 6);\n\n assert(test1[0].is_pair && test1[0].data.pair.count == 2 && test1[0].data.pair.value == '1');\n\n assert(!test1[1].is_pair && test1[1].data.single == '2');\n\n assert(!test1[2].is_pair && test1[2].data.single == '3');\n\n assert(test1[3].is_pair && test1[3].data.pair.count == 2 && test1[3].data.pair.value == '4');\n\n assert(!test1[4].is_pair && test1[4].data.single == '5');\n\n assert(!test1[5].is_pair && test1[5].data.single == '1');\n\n free(test1);\n\n\n\n EncodedValue *test2 = func0(\"automatically\", &size);\n\n assert(size == 12);\n\n assert(!test2[0].is_pair && test2[0].data.single == 'a');\n\n assert(!test2[1].is_pair && test2[1].data.single == 'u');\n\n assert(test2[10].is_pair && test2[10].data.pair.count == 2 && test2[10].data.pair.value == 'l');\n\n assert(!test2[11].is_pair && test2[11].data.single == 'y');\n\n free(test2);\n\n\n\n EncodedValue *test3 = func0(\"python\", &size);\n\n assert(size == 6);\n\n assert(!test3[0].is_pair && test3[0].data.single == 'p');\n\n assert(!test3[1].is_pair && test3[1].data.single == 'y');\n\n free(test3);\n\n\n\n printf(\"All tests passed!\\n\");\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov %rsi,%r13\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nsub $0x8,%rsp\ncallq 10c0 \nmov %rax,%r12\nmov %eax,%ebp\ncltq\nlea (%rax,%rax,2),%rdi\nshl $0x2,%rdi\ncallq 10f0 \ntest %r12d,%r12d\njle 1666 \nmov %rax,%r10\nxor %r11d,%r11d\nxor %edx,%edx\nxchg %ax,%ax\nmovslq %edx,%rcx\nlea 0x1(%rdx),%edi\nmovzbl (%rbx,%rcx,1),%r8d\ncmp %edi,%ebp\njle 1621 \nmov %r12d,%r9d\nlea 0x1(%rbx,%rcx,1),%rcx\nsub %edx,%r9d\nmov $0x1,%edx\njmp 1617 \nnopl 0x0(%rax)\nadd $0x1,%edx\nadd $0x1,%edi\nadd $0x1,%rcx\ncmp %r9d,%edx\nje 1653 \ncmp %r8b,(%rcx)\nje 1608 \ncmp $0x1,%edx\njne 1650 \nmovl $0x0,(%r10)\nmov %edi,%edx\nmov %r8b,0x4(%r10)\nadd $0x1,%r11d\nadd $0xc,%r10\ncmp %ebp,%edi\njl 15e0 \nmov %r11d,0x0(%r13)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax)\nmov %edx,%r9d\nmovl $0x1,(%r10)\nmov %edi,%edx\nmov %r9d,0x4(%r10)\nmov %r8b,0x8(%r10)\njmp 162e \nxor %r11d,%r11d\nmov %r11d,0x0(%r13)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r13\nmov r13, rsi\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\nmov r12, rax\nmov ebp, eax\ncdqe\nlea rdi, [rax+rax*2]\nshl rdi, 2; size\ncall _malloc\ntest r12d, r12d\njle loc_167B\nmov r9, rax\nxor r10d, r10d\nxor esi, esi\nxchg ax, ax\nloc_15E0:\nmovsxd rdx, esi\nmovzx edi, byte ptr [rbx+rdx]\nlea edx, [rsi+1]\ncmp ebp, edx\njle short loc_165D\nmov r8d, r12d\nmovsxd rdx, edx\nmov ecx, 1\nsub r8d, esi\njmp short loc_160C\nloc_1600:\nadd ecx, 1\nadd rdx, 1\ncmp r8d, ecx\njz short loc_1640\nloc_160C:\nmov esi, edx\ncmp [rbx+rdx], dil\njz short loc_1600\ncmp ecx, 1\njnz short loc_1658\nmov dword ptr [r9], 0\nmov [r9+4], dil\nloc_1624:\nadd r10d, 1\nadd r9, 0Ch\ncmp esi, ebp\njl short loc_15E0\nmov [r13+0], r10d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1640:\nadd esi, 1\nloc_1643:\nmov dword ptr [r9], 1\nmov [r9+4], r8d\nmov [r9+8], dil\njmp short loc_1624\nloc_1658:\nmov r8d, ecx\njmp short loc_1643\nloc_165D:\nadd r10d, 1\nmov dword ptr [r9], 0\nmov [r9+4], dil\nmov [r13+0], r10d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_167B:\nxor r10d, r10d\nmov [r13+0], r10d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "char *__fastcall func0(const char *a1, _DWORD *a2)\n{\n int v4; // r12d\n char *result; // rax\n char *v6; // r9\n int v7; // r10d\n int v8; // esi\n char v9; // di\n __int64 v10; // rdx\n int v11; // ecx\n int v12; // r8d\n\n v4 = strlen(a1);\n result = (char *)malloc(12LL * v4);\n if ( v4 <= 0 )\n {\n *a2 = 0;\n }\n else\n {\n v6 = result;\n v7 = 0;\n v8 = 0;\n while ( 1 )\n {\n v9 = a1[v8];\n LODWORD(v10) = v8 + 1;\n if ( v4 <= v8 + 1 )\n break;\n v10 = (int)v10;\n v11 = 1;\n v12 = v4 - v8;\n while ( 1 )\n {\n v8 = v10;\n if ( a1[v10] != v9 )\n break;\n ++v11;\n ++v10;\n if ( v12 == v11 )\n {\n ++v8;\n goto LABEL_12;\n }\n }\n if ( v11 == 1 )\n {\n *(_DWORD *)v6 = 0;\n v6[4] = v9;\n goto LABEL_9;\n }\n v12 = v11;\nLABEL_12:\n *(_DWORD *)v6 = 1;\n *((_DWORD *)v6 + 1) = v12;\n v6[8] = v9;\nLABEL_9:\n ++v7;\n v6 += 12;\n if ( v8 >= v4 )\n {\n *a2 = v7;\n return result;\n }\n }\n *(_DWORD *)v6 = 0;\n v6[4] = v9;\n *a2 = v7 + 1;\n }\n return result;\n}", + "ida_strip_asm": "sub_15A0:\nendbr64\npush r13\nmov r13, rsi\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\nmov r12, rax\nmov ebp, eax\ncdqe\nlea rdi, [rax+rax*2]\nshl rdi, 2; size\ncall _malloc\ntest r12d, r12d\njle loc_167B\nmov r9, rax\nxor r10d, r10d\nxor esi, esi\nxchg ax, ax\nloc_15E0:\nmovsxd rdx, esi\nmovzx edi, byte ptr [rbx+rdx]\nlea edx, [rsi+1]\ncmp ebp, edx\njle short loc_165D\nmov r8d, r12d\nmovsxd rdx, edx\nmov ecx, 1\nsub r8d, esi\njmp short loc_160C\nloc_1600:\nadd ecx, 1\nadd rdx, 1\ncmp r8d, ecx\njz short loc_1640\nloc_160C:\nmov esi, edx\ncmp [rbx+rdx], dil\njz short loc_1600\ncmp ecx, 1\njnz short loc_1658\nmov dword ptr [r9], 0\nmov [r9+4], dil\nloc_1624:\nadd r10d, 1\nadd r9, 0Ch\ncmp esi, ebp\njl short loc_15E0\nmov [r13+0], r10d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1640:\nadd esi, 1\nloc_1643:\nmov dword ptr [r9], 1\nmov [r9+4], r8d\nmov [r9+8], dil\njmp short loc_1624\nloc_1658:\nmov r8d, ecx\njmp short loc_1643\nloc_165D:\nadd r10d, 1\nmov dword ptr [r9], 0\nmov [r9+4], dil\nmov [r13+0], r10d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_167B:\nxor r10d, r10d\nmov [r13+0], r10d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "char *__fastcall sub_15A0(const char *a1, _DWORD *a2)\n{\n int v4; // r12d\n char *result; // rax\n char *v6; // r9\n int v7; // r10d\n int v8; // esi\n char v9; // di\n __int64 v10; // rdx\n int v11; // ecx\n int v12; // r8d\n\n v4 = strlen(a1);\n result = (char *)malloc(12LL * v4);\n if ( v4 <= 0 )\n {\n *a2 = 0;\n }\n else\n {\n v6 = result;\n v7 = 0;\n v8 = 0;\n while ( 1 )\n {\n v9 = a1[v8];\n LODWORD(v10) = v8 + 1;\n if ( v4 <= v8 + 1 )\n break;\n v10 = (int)v10;\n v11 = 1;\n v12 = v4 - v8;\n while ( 1 )\n {\n v8 = v10;\n if ( a1[v10] != v9 )\n break;\n ++v11;\n ++v10;\n if ( v12 == v11 )\n {\n ++v8;\n goto LABEL_12;\n }\n }\n if ( v11 == 1 )\n {\n *(_DWORD *)v6 = 0;\n v6[4] = v9;\n goto LABEL_9;\n }\n v12 = v11;\nLABEL_12:\n *(_DWORD *)v6 = 1;\n *((_DWORD *)v6 + 1) = v12;\n v6[8] = v9;\nLABEL_9:\n ++v7;\n v6 += 12;\n if ( v8 >= v4 )\n {\n *a2 = v7;\n return result;\n }\n }\n *(_DWORD *)v6 = 0;\n v6[4] = v9;\n *a2 = v7 + 1;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_15A0(const char *a1, uint32_t *a2) {\n int v4;\n char *result;\n char *v6;\n int v7;\n int v8;\n char v9;\n long long v10;\n int v11;\n int v12;\n v4 = strlen(a1);\n result = (char *)malloc(12LL * v4);\n if (v4 <= 0) {\n *a2 = 0;\n } else {\n v6 = result;\n v7 = 0;\n v8 = 0;\n while (1) {\n v9 = a1[v8];\n LODWORD(v10) = v8 + 1;\n if (v4 <= v8 + 1) break;\n v10 = (int)v10;\n v11 = 1;\n v12 = v4 - v8;\n while (1) {\n v8 = v10;\n if (a1[v10] != v9) break;\n ++v11;\n ++v10;\n if (v12 == v11) {\n ++v8;\n goto LABEL_12;\n }\n }\n if (v11 == 1) {\n *(uint32_t *)v6 = 0;\n v6[4] = v9;\n goto LABEL_9;\n }\n v12 = v11;\n LABEL_12:\n *(uint32_t *)v6 = 1;\n *((uint32_t *)v6 + 1) = v12;\n v6[8] = v9;\n LABEL_9:\n ++v7;\n v6 += 12;\n if (v8 >= v4) {\n *a2 = v7;\n return result;\n }\n }\n *(uint32_t *)v6 = 0;\n v6[4] = v9;\n *a2 = v7 + 1;\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(const char *a1, uint32_t *a2) {\n int v4;\n char *result;\n char *v6;\n int v7;\n int v8;\n char v9;\n long long v10;\n int v11;\n int v12;\n v4 = strlen(a1);\n result = (char *)malloc(12LL * v4);\n if (v4 <= 0) {\n *a2 = 0;\n } else {\n v6 = result;\n v7 = 0;\n v8 = 0;\n while (1) {\n v9 = a1[v8];\n LODWORD(v10) = v8 + 1;\n if (v4 <= v8 + 1) break;\n v10 = (int)v10;\n v11 = 1;\n v12 = v4 - v8;\n while (1) {\n v8 = v10;\n if (a1[v10] != v9) break;\n ++v11;\n ++v10;\n if (v12 == v11) {\n ++v8;\n goto LABEL_12;\n }\n }\n if (v11 == 1) {\n *(uint32_t *)v6 = 0;\n v6[4] = v9;\n goto LABEL_9;\n }\n v12 = v11;\n LABEL_12:\n *(uint32_t *)v6 = 1;\n *((uint32_t *)v6 + 1) = v12;\n v6[8] = v9;\n LABEL_9:\n ++v7;\n v6 += 12;\n if (v8 >= v4) {\n *a2 = v7;\n return result;\n }\n }\n *(uint32_t *)v6 = 0;\n v6[4] = v9;\n *a2 = v7 + 1;\n }\n return result;\n}" + }, + { + "index": 318, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int s) {\n int maxvalue = 0;\n int i, j, k;\n for (i = 1; i < s - 1; i++) {\n for (j = 1; j < s; j++) {\n k = s - i - j;\n if (i * j * k > maxvalue) {\n maxvalue = i * j * k;\n }\n }\n }\n return maxvalue;\n}", + "test": "int main() {\n\n assert(func0(8) == 18);\n\n assert(func0(4) == 2);\n\n assert(func0(1) == 0);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmovl $0x0,-0x10(%rbp)\nmovl $0x1,-0xc(%rbp)\njmp 11a9 \nmovl $0x1,-0x8(%rbp)\njmp 119d \nmov -0x14(%rbp),%eax\nsub -0xc(%rbp),%eax\nsub -0x8(%rbp),%eax\nmov %eax,-0x4(%rbp)\nmov -0xc(%rbp),%eax\nimul -0x8(%rbp),%eax\nimul -0x4(%rbp),%eax\ncmp %eax,-0x10(%rbp)\njge 1199 \nmov -0xc(%rbp),%eax\nimul -0x8(%rbp),%eax\nmov -0x4(%rbp),%edx\nimul %edx,%eax\nmov %eax,-0x10(%rbp)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x14(%rbp),%eax\njl 116d \naddl $0x1,-0xc(%rbp)\nmov -0x14(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0xc(%rbp)\njl 1164 \nmov -0x10(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_10], 0\nmov [rbp+var_C], 1\njmp short loc_11A9\nloc_1164:\nmov [rbp+var_8], 1\njmp short loc_119D\nloc_116D:\nmov eax, [rbp+var_14]\nsub eax, [rbp+var_C]\nsub eax, [rbp+var_8]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_C]\nimul eax, [rbp+var_8]\nimul eax, [rbp+var_4]\ncmp [rbp+var_10], eax\njge short loc_1199\nmov eax, [rbp+var_C]\nimul eax, [rbp+var_8]\nmov edx, [rbp+var_4]\nimul eax, edx\nmov [rbp+var_10], eax\nloc_1199:\nadd [rbp+var_8], 1\nloc_119D:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_14]\njl short loc_116D\nadd [rbp+var_C], 1\nloc_11A9:\nmov eax, [rbp+var_14]\nsub eax, 1\ncmp [rbp+var_C], eax\njl short loc_1164\nmov eax, [rbp+var_10]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v2; // [rsp+4h] [rbp-10h]\n int i; // [rsp+8h] [rbp-Ch]\n int j; // [rsp+Ch] [rbp-8h]\n int v5; // [rsp+10h] [rbp-4h]\n\n v2 = 0;\n for ( i = 1; i < a1 - 1; ++i )\n {\n for ( j = 1; j < a1; ++j )\n {\n v5 = a1 - i - j;\n if ( v2 < v5 * j * i )\n v2 = v5 * j * i;\n }\n }\n return (unsigned int)v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_10], 0\nmov [rbp+var_C], 1\njmp short loc_11A9\nloc_1164:\nmov [rbp+var_8], 1\njmp short loc_119D\nloc_116D:\nmov eax, [rbp+var_14]\nsub eax, [rbp+var_C]\nsub eax, [rbp+var_8]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_C]\nimul eax, [rbp+var_8]\nimul eax, [rbp+var_4]\ncmp [rbp+var_10], eax\njge short loc_1199\nmov eax, [rbp+var_C]\nimul eax, [rbp+var_8]\nmov edx, [rbp+var_4]\nimul eax, edx\nmov [rbp+var_10], eax\nloc_1199:\nadd [rbp+var_8], 1\nloc_119D:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_14]\njl short loc_116D\nadd [rbp+var_C], 1\nloc_11A9:\nmov eax, [rbp+var_14]\nsub eax, 1\ncmp [rbp+var_C], eax\njl short loc_1164\nmov eax, [rbp+var_10]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v2; // [rsp+4h] [rbp-10h]\n int i; // [rsp+8h] [rbp-Ch]\n int j; // [rsp+Ch] [rbp-8h]\n int v5; // [rsp+10h] [rbp-4h]\n\n v2 = 0;\n for ( i = 1; i < a1 - 1; ++i )\n {\n for ( j = 1; j < a1; ++j )\n {\n v5 = a1 - i - j;\n if ( v2 < v5 * j * i )\n v2 = v5 * j * i;\n }\n }\n return (unsigned int)v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v2;\n int i;\n int j;\n int v5;\n v2 = 0;\n for (i = 1; i < a1 - 1; ++i) {\n for (j = 1; j < a1; ++j) {\n v5 = a1 - i - j;\n if (v2 < v5 * j * i) v2 = v5 * j * i;\n }\n }\n return (unsigned int)v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v2;\n int i;\n int j;\n int v5;\n v2 = 0;\n for (i = 1; i < a1 - 1; ++i) {\n for (j = 1; j < a1; ++j) {\n v5 = a1 - i - j;\n if (v2 < v5 * j * i) v2 = v5 * j * i;\n }\n }\n return (unsigned int)v2;\n}" + }, + { + "index": 318, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int s) {\n int maxvalue = 0;\n int i, j, k;\n for (i = 1; i < s - 1; i++) {\n for (j = 1; j < s; j++) {\n k = s - i - j;\n if (i * j * k > maxvalue) {\n maxvalue = i * j * k;\n }\n }\n }\n return maxvalue;\n}", + "test": "int main() {\n\n assert(func0(8) == 18);\n\n assert(func0(4) == 2);\n\n assert(func0(1) == 0);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x2,%edi\njle 11a2 \npush %rbx\nlea -0x1(%rdi),%r11d\nmov %r11d,%ebx\nmov $0xffffffff,%r8d\nmov $0x1,%r10d\nmov $0x0,%ecx\njmp 118f \nmov %edx,%esi\nimul %eax,%esi\ncmp %esi,%ecx\ncmovl %esi,%ecx\nadd %r9d,%edx\nsub $0x1,%eax\ncmp %r8d,%eax\njne 116d \nadd $0x1,%r10d\nsub $0x1,%r8d\ncmp %ebx,%r10d\nje 11aa \nmov %r10d,%r9d\nmov %r11d,%eax\nsub %r10d,%eax\nmov %r10d,%edx\ncmp $0x1,%edi\njg 116d \njmp 1182 \nmov $0x0,%ecx\nmov %ecx,%eax\nretq\nmov %ecx,%eax\npop %rbx\nretq\n", + "ida_asm": "func0:\nendbr64\ncmp edi, 2\njle short loc_1195\nlea r10d, [rdi-1]\nmov edi, 0FFFFFFFFh\nmov r9d, 1\nmov ecx, 0\nloc_1166:\nmov r8d, r9d\nmov eax, r10d\nsub eax, r9d\nmov edx, r9d\nloc_1172:\nmov esi, edx\nimul esi, eax\ncmp ecx, esi\ncmovl ecx, esi\nadd edx, r8d\nsub eax, 1\ncmp eax, edi\njnz short loc_1172\nadd r9d, 1\nsub edi, 1\ncmp r9d, r10d\njnz short loc_1166\nloc_1192:\nmov eax, ecx\nretn\nloc_1195:\nmov ecx, 0\njmp short loc_1192", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // r10d\n int v2; // edi\n int v3; // r9d\n int v4; // ecx\n int v5; // eax\n int v6; // edx\n\n if ( a1 <= 2 )\n {\n return 0;\n }\n else\n {\n v1 = a1 - 1;\n v2 = -1;\n v3 = 1;\n v4 = 0;\n do\n {\n v5 = v1 - v3;\n v6 = v3;\n do\n {\n if ( v4 < v5 * v6 )\n v4 = v5 * v6;\n v6 += v3;\n --v5;\n }\n while ( v5 != v2 );\n ++v3;\n --v2;\n }\n while ( v3 != v1 );\n }\n return (unsigned int)v4;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ncmp edi, 2\njle short loc_1195\nlea r10d, [rdi-1]\nmov edi, 0FFFFFFFFh\nmov r9d, 1\nmov ecx, 0\nloc_1166:\nmov r8d, r9d\nmov eax, r10d\nsub eax, r9d\nmov edx, r9d\nloc_1172:\nmov esi, edx\nimul esi, eax\ncmp ecx, esi\ncmovl ecx, esi\nadd edx, r8d\nsub eax, 1\ncmp eax, edi\njnz short loc_1172\nadd r9d, 1\nsub edi, 1\ncmp r9d, r10d\njnz short loc_1166\nloc_1192:\nmov eax, ecx\nretn\nloc_1195:\nmov ecx, 0\njmp short loc_1192", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v1; // r10d\n int v2; // edi\n int v3; // r9d\n int v4; // ecx\n int v5; // eax\n int v6; // edx\n\n if ( a1 <= 2 )\n {\n return 0;\n }\n else\n {\n v1 = a1 - 1;\n v2 = -1;\n v3 = 1;\n v4 = 0;\n do\n {\n v5 = v1 - v3;\n v6 = v3;\n do\n {\n if ( v4 < v5 * v6 )\n v4 = v5 * v6;\n v6 += v3;\n --v5;\n }\n while ( v5 != v2 );\n ++v3;\n --v2;\n }\n while ( v3 != v1 );\n }\n return (unsigned int)v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v1;\n int v2;\n int v3;\n int v4;\n int v5;\n int v6;\n if (a1 <= 2) {\n return 0;\n } else {\n v1 = a1 - 1;\n v2 = -1;\n v3 = 1;\n v4 = 0;\n do {\n v5 = v1 - v3;\n v6 = v3;\n do {\n if (v4 < v5 * v6) v4 = v5 * v6;\n v6 += v3;\n --v5;\n } while (v5 != v2);\n ++v3;\n --v2;\n } while (v3 != v1);\n }\n return (unsigned int)v4;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v2;\n int v3;\n int v4;\n int v5;\n int v6;\n if (a1 <= 2) {\n return 0;\n } else {\n v1 = a1 - 1;\n v2 = -1;\n v3 = 1;\n v4 = 0;\n do {\n v5 = v1 - v3;\n v6 = v3;\n do {\n if (v4 < v5 * v6) v4 = v5 * v6;\n v6 += v3;\n --v5;\n } while (v5 != v2);\n ++v3;\n --v2;\n } while (v3 != v1);\n }\n return (unsigned int)v4;\n}" + }, + { + "index": 318, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int s) {\n int maxvalue = 0;\n int i, j, k;\n for (i = 1; i < s - 1; i++) {\n for (j = 1; j < s; j++) {\n k = s - i - j;\n if (i * j * k > maxvalue) {\n maxvalue = i * j * k;\n }\n }\n }\n return maxvalue;\n}", + "test": "int main() {\n\n assert(func0(8) == 18);\n\n assert(func0(4) == 2);\n\n assert(func0(1) == 0);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x2,%edi\njle 1226 \nlea -0x1(%rdi),%r10d\nmov $0xffffffff,%r9d\nmov $0x1,%esi\nxor %r8d,%r8d\nnopl 0x0(%rax,%rax,1)\nmov %r10d,%eax\nmov %esi,%edx\nsub %esi,%eax\ncmp $0x1,%edi\njle 1216 \nnopl 0x0(%rax)\nmov %edx,%ecx\nimul %eax,%ecx\ncmp %ecx,%r8d\ncmovl %ecx,%r8d\nsub $0x1,%eax\nadd %esi,%edx\ncmp %r9d,%eax\njne 1200 \nadd $0x1,%esi\nsub $0x1,%r9d\ncmp %r10d,%esi\njne 11f0 \nmov %r8d,%eax\nretq\nxor %r8d,%r8d\nmov %r8d,%eax\nretq\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\ncmp edi, 2\njle short loc_1243\nlea r9d, [rdi-1]\nmov r8d, 0FFFFFFFFh\nmov edi, 1\nxor ecx, ecx\nnop word ptr [rax+rax+00h]\nloc_1210:\nmov eax, r9d\nmov edx, edi\nsub eax, edi\nnop word ptr [rax+rax+00000000h]\nloc_1220:\nmov esi, edx\nimul esi, eax\ncmp ecx, esi\ncmovl ecx, esi\nsub eax, 1\nadd edx, edi\ncmp eax, r8d\njnz short loc_1220\nadd edi, 1\nsub r8d, 1\ncmp edi, r9d\njnz short loc_1210\nmov eax, ecx\nretn\nloc_1243:\nxor ecx, ecx\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // r9d\n int v2; // r8d\n int v3; // edi\n int v4; // ecx\n int v5; // edx\n int v6; // eax\n\n if ( a1 <= 2 )\n return 0LL;\n v1 = a1 - 1;\n v2 = -1;\n v3 = 1;\n v4 = 0;\n do\n {\n v5 = v3;\n v6 = v1 - v3;\n do\n {\n if ( v4 < v6 * v5 )\n v4 = v6 * v5;\n --v6;\n v5 += v3;\n }\n while ( v6 != v2 );\n ++v3;\n --v2;\n }\n while ( v3 != v1 );\n return (unsigned int)v4;\n}", + "ida_strip_asm": "sub_11F0:\nendbr64\ncmp edi, 2\njle short loc_1243\nlea r9d, [rdi-1]\nmov r8d, 0FFFFFFFFh\nmov edi, 1\nxor ecx, ecx\nnop word ptr [rax+rax+00h]\nloc_1210:\nmov eax, r9d\nmov edx, edi\nsub eax, edi\nnop word ptr [rax+rax+00000000h]\nloc_1220:\nmov esi, edx\nimul esi, eax\ncmp ecx, esi\ncmovl ecx, esi\nsub eax, 1\nadd edx, edi\ncmp eax, r8d\njnz short loc_1220\nadd edi, 1\nsub r8d, 1\ncmp edi, r9d\njnz short loc_1210\nmov eax, ecx\nretn\nloc_1243:\nxor ecx, ecx\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11F0(int a1)\n{\n int v1; // r9d\n int v2; // r8d\n int v3; // edi\n int v4; // ecx\n int v5; // edx\n int v6; // eax\n\n if ( a1 <= 2 )\n return 0LL;\n v1 = a1 - 1;\n v2 = -1;\n v3 = 1;\n v4 = 0;\n do\n {\n v5 = v3;\n v6 = v1 - v3;\n do\n {\n if ( v4 < v6 * v5 )\n v4 = v6 * v5;\n --v6;\n v5 += v3;\n }\n while ( v6 != v2 );\n ++v3;\n --v2;\n }\n while ( v3 != v1 );\n return (unsigned int)v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11F0(int a1) {\n int v1;\n int v2;\n int v3;\n int v4;\n int v5;\n int v6;\n if (a1 <= 2) return 0LL;\n v1 = a1 - 1;\n v2 = -1;\n v3 = 1;\n v4 = 0;\n do {\n v5 = v3;\n v6 = v1 - v3;\n do {\n if (v4 < v6 * v5) v4 = v6 * v5;\n --v6;\n v5 += v3;\n } while (v6 != v2);\n ++v3;\n --v2;\n } while (v3 != v1);\n return (unsigned int)v4;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v2;\n int v3;\n int v4;\n int v5;\n int v6;\n if (a1 <= 2) return 0LL;\n v1 = a1 - 1;\n v2 = -1;\n v3 = 1;\n v4 = 0;\n do {\n v5 = v3;\n v6 = v1 - v3;\n do {\n if (v4 < v6 * v5) v4 = v6 * v5;\n --v6;\n v5 += v3;\n } while (v6 != v2);\n ++v3;\n --v2;\n } while (v3 != v1);\n return (unsigned int)v4;\n}" + }, + { + "index": 319, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(const char* text, int* count) {\n regex_t regex;\n regmatch_t matches[1];\n static char* words[10];\n char pattern[] = \"\\\\b[a-zA-Z]{5}\\\\b\";\n int word_count = 0;\n char str[strlen(text) + 1];\n strcpy(str, text);\n regcomp(®ex, pattern, REG_EXTENDED);\n char* p = str;\n while (regexec(®ex, p, 1, matches, 0) == 0) {\n int start = matches[0].rm_so;\n int end = matches[0].rm_eo;\n char* word = (char*)malloc(sizeof(char) * (end - start + 1));\n strncpy(word, p + start, end - start);\n word[end - start] = '\\0';\n words[word_count++] = word;\n p += end;\n }\n regfree(®ex);\n *count = word_count;\n return words;\n}", + "test": "int main() {\n\n int count;\n\n char** result;\n\n\n\n result = func0(\"Please move back to strem\", &count);\n\n assert(count == 1 && strcmp(result[0], \"strem\") == 0);\n\n\n\n result = func0(\"4K Ultra HD streaming player\", &count);\n\n assert(count == 1 && strcmp(result[0], \"Ultra\") == 0);\n\n\n\n result = func0(\"Streaming Media Player\", &count);\n\n assert(count == 1 && strcmp(result[0], \"Media\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0xb8,%rsp\nmov %rdi,-0xd8(%rbp)\nmov %rsi,-0xe0(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nmov %rsp,%rax\nmov %rax,%rbx\nmovabs $0x2d417a2d615b625c,%rax\nmovabs $0x625c7d357b5d5a,%rdx\nmov %rax,-0x50(%rbp)\nmov %rdx,-0x48(%rbp)\nmovl $0x0,-0xcc(%rbp)\nmov -0xd8(%rbp),%rax\nmov %rax,%rdi\ncallq 1110 \nadd $0x1,%rax\nmov %rax,%rdx\nsub $0x1,%rdx\nmov %rdx,-0xb8(%rbp)\nmov %rax,%r14\nmov $0x0,%r15d\nmov %rax,%r12\nmov $0x0,%r13d\nmov $0x10,%edx\nsub $0x1,%rdx\nadd %rdx,%rax\nmov $0x10,%edi\nmov $0x0,%edx\ndiv %rdi\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rsi\nsub %rdx,%rsi\nmov %rsi,%rdx\ncmp %rdx,%rsp\nje 1344 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 132d \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 136e \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x0,%rax\nmov %rax,-0xb0(%rbp)\nmov -0xd8(%rbp),%rdx\nmov -0xb0(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10f0 \nlea -0x50(%rbp),%rcx\nlea -0xa0(%rbp),%rax\nmov $0x1,%edx\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 1140 \nmov -0xb0(%rbp),%rax\nmov %rax,-0xc0(%rbp)\njmpq 147f \nmov -0x58(%rbp),%eax\nmov %eax,-0xc8(%rbp)\nmov -0x54(%rbp),%eax\nmov %eax,-0xc4(%rbp)\nmov -0xc4(%rbp),%eax\nsub -0xc8(%rbp),%eax\nadd $0x1,%eax\ncltq\nmov %rax,%rdi\ncallq 1160 \nmov %rax,-0xa8(%rbp)\nmov -0xc4(%rbp),%eax\nsub -0xc8(%rbp),%eax\nmovslq %eax,%rdx\nmov -0xc8(%rbp),%eax\nmovslq %eax,%rcx\nmov -0xc0(%rbp),%rax\nadd %rax,%rcx\nmov -0xa8(%rbp),%rax\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 10e0 \nmov -0xc4(%rbp),%eax\nsub -0xc8(%rbp),%eax\nmovslq %eax,%rdx\nmov -0xa8(%rbp),%rax\nadd %rdx,%rax\nmovb $0x0,(%rax)\nmov -0xcc(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0xcc(%rbp)\ncltq\nlea 0x0(,%rax,8),%rcx\nlea 0x2bdb(%rip),%rdx\nmov -0xa8(%rbp),%rax\nmov %rax,(%rcx,%rdx,1)\nmov -0xc4(%rbp),%eax\ncltq\nadd %rax,-0xc0(%rbp)\nlea -0x58(%rbp),%rdx\nmov -0xc0(%rbp),%rsi\nlea -0xa0(%rbp),%rax\nmov $0x0,%r8d\nmov %rdx,%rcx\nmov $0x1,%edx\nmov %rax,%rdi\ncallq 1170 \ntest %eax,%eax\nje 13c3 \nlea -0xa0(%rbp),%rax\nmov %rax,%rdi\ncallq 1100 \nmov -0xe0(%rbp),%rax\nmov -0xcc(%rbp),%edx\nmov %edx,(%rax)\nlea 0x2b6c(%rip),%rax\nmov %rbx,%rsp\nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\nje 14eb \ncallq 1120 <__stack_chk_fail@plt>\nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 0B8h\nmov [rbp+s], rdi\nmov [rbp+var_C0], rsi\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov rax, rsp\nmov rbx, rax\nmov rax, 2D417A2D615B625Ch\nmov rdx, 625C7D357B5D5Ah\nmov qword ptr [rbp+pattern], rax\nmov [rbp+var_28], rdx\nmov [rbp+var_AC], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nadd rax, 1\nmov rdx, rax\nsub rdx, 1\nmov [rbp+var_98], rdx\nmov edx, 10h\nsub rdx, 1\nadd rax, rdx\nmov esi, 10h\nmov edx, 0\ndiv rsi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_1310:\ncmp rsp, rdx\njz short loc_1327\nsub rsp, 1000h\nor [rsp+10C0h+var_C8], 0\njmp short loc_1310\nloc_1327:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1351\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1351:\nmov rax, rsp\nadd rax, 0\nmov [rbp+dest], rax\nmov rdx, [rbp+s]\nmov rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\nlea rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov rax, [rbp+dest]\nmov [rbp+string], rax\njmp loc_145F\nloc_13A3:\nmov eax, [rbp+pmatch.rm_so]\nmov [rbp+var_A8], eax\nmov eax, [rbp+pmatch.rm_eo]\nmov [rbp+var_A4], eax\nmov eax, [rbp+var_A4]\nsub eax, [rbp+var_A8]\nadd eax, 1\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_88], rax\nmov eax, [rbp+var_A4]\nsub eax, [rbp+var_A8]\nmovsxd rdx, eax; n\nmov eax, [rbp+var_A8]\nmovsxd rcx, eax\nmov rax, [rbp+string]\nadd rcx, rax\nmov rax, [rbp+var_88]\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strncpy\nmov eax, [rbp+var_A4]\nsub eax, [rbp+var_A8]\nmovsxd rdx, eax\nmov rax, [rbp+var_88]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov eax, [rbp+var_AC]\nlea edx, [rax+1]\nmov [rbp+var_AC], edx\ncdqe\nlea rcx, ds:0[rax*8]\nlea rdx, words_1\nmov rax, [rbp+var_88]\nmov [rcx+rdx], rax\nmov eax, [rbp+var_A4]\ncdqe\nadd [rbp+string], rax\nloc_145F:\nlea rdx, [rbp+pmatch]\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov rcx, rdx; pmatch\nmov edx, 1; nmatch\nmov rdi, rax; preg\ncall _regexec\ntest eax, eax\njz loc_13A3\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nmov rax, [rbp+var_C0]\nmov edx, [rbp+var_AC]\nmov [rax], edx\nlea rax, words_1\nmov rsp, rbx\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njz short loc_14C5\ncall ___stack_chk_fail\nloc_14C5:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(char *a1, _DWORD *a2)\n{\n size_t v2; // rax\n unsigned __int64 v3; // rax\n void *v4; // rsp\n int v5; // eax\n _DWORD *v7; // [rsp+8h] [rbp-C0h] BYREF\n char *s; // [rsp+10h] [rbp-B8h]\n int v9; // [rsp+1Ch] [rbp-ACh]\n regmatch_t v10; // [rsp+20h] [rbp-A8h]\n char *string; // [rsp+28h] [rbp-A0h]\n size_t v12; // [rsp+30h] [rbp-98h]\n char *dest; // [rsp+38h] [rbp-90h]\n char *v14; // [rsp+40h] [rbp-88h]\n regex_t preg; // [rsp+48h] [rbp-80h] BYREF\n regmatch_t pmatch; // [rsp+90h] [rbp-38h] BYREF\n char pattern[24]; // [rsp+98h] [rbp-30h] BYREF\n unsigned __int64 v18; // [rsp+B0h] [rbp-18h]\n\n s = a1;\n v7 = a2;\n v18 = __readfsqword(0x28u);\n strcpy(pattern, \"\\\\b[a-zA-Z]{5}\\\\b\");\n v9 = 0;\n v2 = strlen(a1) + 1;\n v12 = v2 - 1;\n v3 = 16 * ((v2 + 15) / 0x10);\n while ( &v7 != (_DWORD **)((char *)&v7 - (v3 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v4 = alloca(v3 & 0xFFF);\n if ( (v3 & 0xFFF) != 0 )\n *(_DWORD **)((char *)&v7 + (v3 & 0xFFF) - 8) = *(_DWORD **)((char *)&v7 + (v3 & 0xFFF) - 8);\n dest = (char *)&v7;\n strcpy((char *)&v7, s);\n regcomp(&preg, pattern, 1);\n for ( string = dest; !regexec(&preg, string, 1uLL, &pmatch, 0); string += v10.rm_eo )\n {\n v10 = pmatch;\n v14 = (char *)malloc(pmatch.rm_eo - pmatch.rm_so + 1);\n strncpy(v14, &string[v10.rm_so], v10.rm_eo - v10.rm_so);\n v14[v10.rm_eo - v10.rm_so] = 0;\n v5 = v9++;\n words_1[v5] = v14;\n }\n regfree(&preg);\n *v7 = v9;\n return words_1;\n}", + "ida_strip_asm": "sub_1269:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 0B8h\nmov [rbp+s], rdi\nmov [rbp+var_C0], rsi\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov rax, rsp\nmov rbx, rax\nmov rax, 2D417A2D615B625Ch\nmov rdx, 625C7D357B5D5Ah\nmov qword ptr [rbp+pattern], rax\nmov [rbp+var_28], rdx\nmov [rbp+var_AC], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nadd rax, 1\nmov rdx, rax\nsub rdx, 1\nmov [rbp+var_98], rdx\nmov edx, 10h\nsub rdx, 1\nadd rax, rdx\nmov esi, 10h\nmov edx, 0\ndiv rsi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_1310:\ncmp rsp, rdx\njz short loc_1327\nsub rsp, 1000h\nor [rsp+10C0h+var_C8], 0\njmp short loc_1310\nloc_1327:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1351\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1351:\nmov rax, rsp\nadd rax, 0\nmov [rbp+dest], rax\nmov rdx, [rbp+s]\nmov rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\nlea rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov rax, [rbp+dest]\nmov [rbp+string], rax\njmp loc_145F\nloc_13A3:\nmov eax, [rbp+pmatch.rm_so]\nmov [rbp+var_A8], eax\nmov eax, [rbp+pmatch.rm_eo]\nmov [rbp+var_A4], eax\nmov eax, [rbp+var_A4]\nsub eax, [rbp+var_A8]\nadd eax, 1\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_88], rax\nmov eax, [rbp+var_A4]\nsub eax, [rbp+var_A8]\nmovsxd rdx, eax; n\nmov eax, [rbp+var_A8]\nmovsxd rcx, eax\nmov rax, [rbp+string]\nadd rcx, rax\nmov rax, [rbp+var_88]\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strncpy\nmov eax, [rbp+var_A4]\nsub eax, [rbp+var_A8]\nmovsxd rdx, eax\nmov rax, [rbp+var_88]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov eax, [rbp+var_AC]\nlea edx, [rax+1]\nmov [rbp+var_AC], edx\ncdqe\nlea rcx, ds:0[rax*8]\nlea rdx, unk_4040\nmov rax, [rbp+var_88]\nmov [rcx+rdx], rax\nmov eax, [rbp+var_A4]\ncdqe\nadd [rbp+string], rax\nloc_145F:\nlea rdx, [rbp+pmatch]\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov rcx, rdx; pmatch\nmov edx, 1; nmatch\nmov rdi, rax; preg\ncall _regexec\ntest eax, eax\njz loc_13A3\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nmov rax, [rbp+var_C0]\nmov edx, [rbp+var_AC]\nmov [rax], edx\nlea rax, unk_4040\nmov rsp, rbx\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njz short loc_14C5\ncall ___stack_chk_fail\nloc_14C5:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1269(char *a1, _DWORD *a2)\n{\n size_t v2; // rax\n unsigned __int64 v3; // rax\n void *v4; // rsp\n int v5; // eax\n _DWORD *v7; // [rsp+8h] [rbp-C0h] BYREF\n char *s; // [rsp+10h] [rbp-B8h]\n int v9; // [rsp+1Ch] [rbp-ACh]\n regmatch_t v10; // [rsp+20h] [rbp-A8h]\n char *string; // [rsp+28h] [rbp-A0h]\n size_t v12; // [rsp+30h] [rbp-98h]\n char *dest; // [rsp+38h] [rbp-90h]\n char *v14; // [rsp+40h] [rbp-88h]\n regex_t preg; // [rsp+48h] [rbp-80h] BYREF\n regmatch_t pmatch; // [rsp+90h] [rbp-38h] BYREF\n char pattern[24]; // [rsp+98h] [rbp-30h] BYREF\n unsigned __int64 v18; // [rsp+B0h] [rbp-18h]\n\n s = a1;\n v7 = a2;\n v18 = __readfsqword(0x28u);\n strcpy(pattern, \"\\\\b[a-zA-Z]{5}\\\\b\");\n v9 = 0;\n v2 = strlen(a1) + 1;\n v12 = v2 - 1;\n v3 = 16 * ((v2 + 15) / 0x10);\n while ( &v7 != (_DWORD **)((char *)&v7 - (v3 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v4 = alloca(v3 & 0xFFF);\n if ( (v3 & 0xFFF) != 0 )\n *(_DWORD **)((char *)&v7 + (v3 & 0xFFF) - 8) = *(_DWORD **)((char *)&v7 + (v3 & 0xFFF) - 8);\n dest = (char *)&v7;\n strcpy((char *)&v7, s);\n regcomp(&preg, pattern, 1);\n for ( string = dest; !regexec(&preg, string, 1uLL, &pmatch, 0); string += v10.rm_eo )\n {\n v10 = pmatch;\n v14 = (char *)malloc(pmatch.rm_eo - pmatch.rm_so + 1);\n strncpy(v14, &string[v10.rm_so], v10.rm_eo - v10.rm_so);\n v14[v10.rm_eo - v10.rm_so] = 0;\n v5 = v9++;\n qword_4040[v5] = v14;\n }\n regfree(&preg);\n *v7 = v9;\n return qword_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1269(char *a1, uint32_t *a2) {\n unsigned int v2;\n unsigned long long v3;\n void *v4;\n int v5;\n uint32_t *v7;\n char *s;\n int v9;\n regmatch_t v10;\n char *string;\n unsigned int v12;\n char *dest;\n char *v14;\n regex_t preg;\n regmatch_t pmatch;\n char pattern[24];\n unsigned long long v18;\n s = a1;\n v7 = a2;\n v18 = __readfsqword(40u);\n strcpy(pattern, \"\\\\b[a-zA-Z]{5}\\\\b\");\n v9 = 0;\n v2 = strlen(a1) + 1;\n v12 = v2 - 1;\n v3 = 16 * ((v2 + 15) / 16);\n while (&v7 != (uint32_t **)((char *)&v7 - (v3 & 18446744073709547520LL)))\n ;\n v4 = alloca(v3 & 4095);\n if ((v3 & 4095) != 0)\n *(uint32_t **)((char *)&v7 + (v3 & 4095) - 8) =\n *(uint32_t **)((char *)&v7 + (v3 & 4095) - 8);\n dest = (char *)&v7;\n strcpy((char *)&v7, s);\n regcomp(&preg, pattern, 1);\n for (string = dest; !regexec(&preg, string, 1uLL, &pmatch, 0);\n string += v10.rm_eo) {\n v10 = pmatch;\n v14 = (char *)malloc(pmatch.rm_eo - pmatch.rm_so + 1);\n strncpy(v14, &string[v10.rm_so], v10.rm_eo - v10.rm_so);\n v14[v10.rm_eo - v10.rm_so] = 0;\n v5 = v9++;\n qword_4040[v5] = v14;\n }\n regfree(&preg);\n *v7 = v9;\n return qword_4040;\n}", + "ida_pseudo_norm": "uint64_t *func0(char *a1, uint32_t *a2) {\n unsigned int v2;\n unsigned long long v3;\n void *v4;\n int v5;\n uint32_t *v7;\n char *s;\n int v9;\n regmatch_t v10;\n char *string;\n unsigned int v12;\n char *dest;\n char *v14;\n regex_t preg;\n regmatch_t pmatch;\n char pattern[24];\n unsigned long long v18;\n s = a1;\n v7 = a2;\n v18 = __readfsqword(40u);\n strcpy(pattern, \"\\\\b[a-zA-Z]{5}\\\\b\");\n v9 = 0;\n v2 = strlen(a1) + 1;\n v12 = v2 - 1;\n v3 = 16 * ((v2 + 15) / 16);\n while (&v7 != (uint32_t **)((char *)&v7 - (v3 & 18446744073709547520LL)))\n ;\n v4 = alloca(v3 & 4095);\n if ((v3 & 4095) != 0)\n *(uint32_t **)((char *)&v7 + (v3 & 4095) - 8) =\n *(uint32_t **)((char *)&v7 + (v3 & 4095) - 8);\n dest = (char *)&v7;\n strcpy((char *)&v7, s);\n regcomp(&preg, pattern, 1);\n for (string = dest; !regexec(&preg, string, 1uLL, &pmatch, 0);\n string += v10.rm_eo) {\n v10 = pmatch;\n v14 = (char *)malloc(pmatch.rm_eo - pmatch.rm_so + 1);\n strncpy(v14, &string[v10.rm_so], v10.rm_eo - v10.rm_so);\n v14[v10.rm_eo - v10.rm_so] = 0;\n v5 = v9++;\n words_1[v5] = v14;\n }\n regfree(&preg);\n *v7 = v9;\n return words_1;\n}" + }, + { + "index": 319, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(const char* text, int* count) {\n regex_t regex;\n regmatch_t matches[1];\n static char* words[10];\n char pattern[] = \"\\\\b[a-zA-Z]{5}\\\\b\";\n int word_count = 0;\n char str[strlen(text) + 1];\n strcpy(str, text);\n regcomp(®ex, pattern, REG_EXTENDED);\n char* p = str;\n while (regexec(®ex, p, 1, matches, 0) == 0) {\n int start = matches[0].rm_so;\n int end = matches[0].rm_eo;\n char* word = (char*)malloc(sizeof(char) * (end - start + 1));\n strncpy(word, p + start, end - start);\n word[end - start] = '\\0';\n words[word_count++] = word;\n p += end;\n }\n regfree(®ex);\n *count = word_count;\n return words;\n}", + "test": "int main() {\n\n int count;\n\n char** result;\n\n\n\n result = func0(\"Please move back to strem\", &count);\n\n assert(count == 1 && strcmp(result[0], \"strem\") == 0);\n\n\n\n result = func0(\"4K Ultra HD streaming player\", &count);\n\n assert(count == 1 && strcmp(result[0], \"Ultra\") == 0);\n\n\n\n result = func0(\"Streaming Media Player\", &count);\n\n assert(count == 1 && strcmp(result[0], \"Media\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0x88,%rsp\nmov %rdi,%rdx\nmov %rsi,-0xb0(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nmovabs $0x2d417a2d615b625c,%rbx\nmovabs $0x625c7d357b5d5a,%rsi\nmov %rbx,-0x50(%rbp)\nmov %rsi,-0x48(%rbp)\nmov $0xffffffffffffffff,%rcx\nrepnz scas %es:(%rdi),%al\nnot %rcx\nadd $0xf,%rcx\nmov %rcx,%rsi\nand $0xfffffffffffffff0,%rsi\nand $0xfffffffffffff000,%rcx\nmov %rsp,%rax\nsub %rcx,%rax\ncmp %rax,%rsp\nje 12b1 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 129a \nmov %rsi,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 12c7 \norq $0x0,-0x8(%rsp,%rax,1)\nmov %rsp,%r15\nmov %rdx,%rsi\nmov %rsp,%rdi\ncallq 10d0 \nlea -0x50(%rbp),%rsi\nlea -0xa0(%rbp),%rdi\nmov $0x1,%edx\ncallq 1110 \nmov $0x0,%r14d\nlea -0x58(%rbp),%rcx\nlea -0xa0(%rbp),%rdi\nmov $0x0,%r8d\nmov $0x1,%edx\nmov %r15,%rsi\ncallq 1130 \ntest %eax,%eax\njne 1367 \nmov -0x58(%rbp),%ebx\nmov -0x54(%rbp),%eax\nmov %eax,-0xa4(%rbp)\nmov %eax,%r13d\nsub %ebx,%r13d\nlea 0x1(%r13),%edi\nmovslq %edi,%rdi\ncallq 1120 \nmov %rax,%r12\nmovslq %r13d,%r13\nmovslq %ebx,%rsi\nadd %r15,%rsi\nmov %r13,%rdx\nmov %rax,%rdi\ncallq 10c0 \nmovb $0x0,(%r12,%r13,1)\nlea 0x2ced(%rip),%rdx\nmov %r12,(%rdx,%r14,8)\nmovslq -0xa4(%rbp),%rax\nadd %rax,%r15\nadd $0x1,%r14\njmp 12f0 \nlea -0xa0(%rbp),%rdi\ncallq 10e0 \nmov -0xb0(%rbp),%rax\nmov %r14d,(%rax)\nmov -0x38(%rbp),%rax\nxor %fs:0x28,%rax\njne 13a2 \nlea 0x2cad(%rip),%rax\nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\ncallq 10f0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 98h\nmov rbx, rdi\nmov [rbp+var_B8], rsi\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nmov rax, 2D417A2D615B625Ch\nmov rdx, 625C7D357B5D5Ah\nmov qword ptr [rbp+pattern], rax\nmov [rbp+var_48], rdx\ncall _strlen\nlea rsi, [rax+1]\nadd rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_12D6:\ncmp rsp, rdx\njz short loc_12ED\nsub rsp, 1000h\nor [rsp+10C0h+var_C8], 0\njmp short loc_12D6\nloc_12ED:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_1303\nor [rsp+rax+0C0h+var_C8], 0\nloc_1303:\nmov r14, rsp\nmov rdx, rsi\nmov rsi, rbx\nmov rdi, rsp\ncall ___strcpy_chk\nlea rsi, [rbp+pattern]; pattern\nlea rdi, [rbp+preg]; preg\nmov edx, 1; cflags\ncall _regcomp\nmov r15d, 0\njmp short loc_1395\nloc_1331:\nmov ebx, [rbp+pmatch.rm_so]\nmov eax, [rbp+pmatch.rm_eo]\nmov [rbp+var_AC], eax\nmov r13d, eax\nsub r13d, ebx\nlea eax, [r13+1]\nmovsxd rdx, eax\nmov [rbp+var_A8], rdx\nmov rdi, rdx; size\ncall _malloc\nmov r12, rax\nmovsxd r13, r13d\nmovsxd rsi, ebx\nadd rsi, r14\nmov rcx, [rbp+var_A8]\nmov rdx, r13\nmov rdi, rax\ncall ___strncpy_chk\nmov byte ptr [r12+r13], 0\nlea rbx, words_1\nmov [rbx+r15*8], r12\nmovsxd rax, [rbp+var_AC]\nadd r14, rax\nadd r15, 1\nloc_1395:\nlea rcx, [rbp+pmatch]; pmatch\nlea rdi, [rbp+preg]; preg\nmov r8d, 0; eflags\nmov edx, 1; nmatch\nmov rsi, r14; string\ncall _regexec\ntest eax, eax\njz loc_1331\nlea rdi, [rbp+preg]; preg\ncall _regfree\nmov rax, [rbp+var_B8]\nmov [rax], r15d\nmov rax, [rbp+var_38]\nsub rax, fs:28h\njnz short loc_13F6\nlea rax, words_1\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_13F6:\ncall ___stack_chk_fail", + "ida_pseudo": "_QWORD *__fastcall func0(const char *a1, _DWORD *a2)\n{\n size_t v2; // rax\n size_t v3; // rsi\n size_t v4; // rax\n __int16 v5; // cx\n signed __int64 v6; // rax\n void *v7; // rsp\n const char *v8; // r14\n __int64 v9; // r15\n regoff_t rm_so; // ebx\n int v11; // r13d\n _BYTE *v12; // r12\n __int64 v14; // [rsp+0h] [rbp-C8h]\n __int64 v15; // [rsp+8h] [rbp-C0h] BYREF\n _DWORD *v16; // [rsp+10h] [rbp-B8h]\n regoff_t rm_eo; // [rsp+1Ch] [rbp-ACh]\n size_t v18; // [rsp+20h] [rbp-A8h]\n regex_t preg; // [rsp+28h] [rbp-A0h] BYREF\n regmatch_t pmatch; // [rsp+70h] [rbp-58h] BYREF\n char pattern[24]; // [rsp+78h] [rbp-50h] BYREF\n unsigned __int64 v22; // [rsp+90h] [rbp-38h]\n\n v16 = a2;\n v22 = __readfsqword(0x28u);\n strcpy(pattern, \"\\\\b[a-zA-Z]{5}\\\\b\");\n v2 = strlen(a1);\n v3 = v2 + 1;\n v4 = v2 + 16;\n v5 = v4 & 0xFFF0;\n while ( &v15 != (__int64 *)((char *)&v15 - (v4 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v6 = v4 & 0xFF0;\n v7 = alloca(v6);\n if ( (v5 & 0xFFF) != 0 )\n *(__int64 *)((char *)&v14 + v6) = *(__int64 *)((char *)&v14 + v6);\n v8 = (const char *)&v15;\n __strcpy_chk(&v15, a1, v3);\n regcomp(&preg, pattern, 1);\n v9 = 0LL;\n while ( !regexec(&preg, v8, 1uLL, &pmatch, 0) )\n {\n rm_so = pmatch.rm_so;\n rm_eo = pmatch.rm_eo;\n v11 = pmatch.rm_eo - pmatch.rm_so;\n v18 = pmatch.rm_eo - pmatch.rm_so + 1;\n v12 = malloc(v18);\n __strncpy_chk(v12, &v8[rm_so], v11, v18);\n v12[v11] = 0;\n words_1[v9] = v12;\n v8 += rm_eo;\n ++v9;\n }\n regfree(&preg);\n *v16 = v9;\n return words_1;\n}", + "ida_strip_asm": "sub_1269:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 98h\nmov rbx, rdi\nmov [rbp+var_B8], rsi\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nmov rax, 2D417A2D615B625Ch\nmov rdx, 625C7D357B5D5Ah\nmov qword ptr [rbp+pattern], rax\nmov [rbp+var_48], rdx\ncall _strlen\nlea rsi, [rax+1]\nadd rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_12D6:\ncmp rsp, rdx\njz short loc_12ED\nsub rsp, 1000h\nor [rsp+10C0h+var_C8], 0\njmp short loc_12D6\nloc_12ED:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_1303\nor [rsp+rax+0C0h+var_C8], 0\nloc_1303:\nmov r14, rsp\nmov rdx, rsi\nmov rsi, rbx\nmov rdi, rsp\ncall ___strcpy_chk\nlea rsi, [rbp+pattern]; pattern\nlea rdi, [rbp+preg]; preg\nmov edx, 1; cflags\ncall _regcomp\nmov r15d, 0\njmp short loc_1395\nloc_1331:\nmov ebx, [rbp+pmatch.rm_so]\nmov eax, [rbp+pmatch.rm_eo]\nmov [rbp+var_AC], eax\nmov r13d, eax\nsub r13d, ebx\nlea eax, [r13+1]\nmovsxd rdx, eax\nmov [rbp+var_A8], rdx\nmov rdi, rdx; size\ncall _malloc\nmov r12, rax\nmovsxd r13, r13d\nmovsxd rsi, ebx\nadd rsi, r14\nmov rcx, [rbp+var_A8]\nmov rdx, r13\nmov rdi, rax\ncall ___strncpy_chk\nmov byte ptr [r12+r13], 0\nlea rbx, unk_4040\nmov [rbx+r15*8], r12\nmovsxd rax, [rbp+var_AC]\nadd r14, rax\nadd r15, 1\nloc_1395:\nlea rcx, [rbp+pmatch]; pmatch\nlea rdi, [rbp+preg]; preg\nmov r8d, 0; eflags\nmov edx, 1; nmatch\nmov rsi, r14; string\ncall _regexec\ntest eax, eax\njz loc_1331\nlea rdi, [rbp+preg]; preg\ncall _regfree\nmov rax, [rbp+var_B8]\nmov [rax], r15d\nmov rax, [rbp+var_38]\nsub rax, fs:28h\njnz short loc_13F6\nlea rax, unk_4040\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_13F6:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1269(const char *a1, _DWORD *a2)\n{\n size_t v2; // rax\n size_t v3; // rsi\n size_t v4; // rax\n __int16 v5; // cx\n signed __int64 v6; // rax\n void *v7; // rsp\n const char *v8; // r14\n __int64 v9; // r15\n regoff_t rm_so; // ebx\n int v11; // r13d\n _BYTE *v12; // r12\n __int64 v14; // [rsp+0h] [rbp-C8h]\n __int64 v15; // [rsp+8h] [rbp-C0h] BYREF\n _DWORD *v16; // [rsp+10h] [rbp-B8h]\n regoff_t rm_eo; // [rsp+1Ch] [rbp-ACh]\n size_t v18; // [rsp+20h] [rbp-A8h]\n regex_t preg; // [rsp+28h] [rbp-A0h] BYREF\n regmatch_t pmatch; // [rsp+70h] [rbp-58h] BYREF\n char pattern[24]; // [rsp+78h] [rbp-50h] BYREF\n unsigned __int64 v22; // [rsp+90h] [rbp-38h]\n\n v16 = a2;\n v22 = __readfsqword(0x28u);\n strcpy(pattern, \"\\\\b[a-zA-Z]{5}\\\\b\");\n v2 = strlen(a1);\n v3 = v2 + 1;\n v4 = v2 + 16;\n v5 = v4 & 0xFFF0;\n while ( &v15 != (__int64 *)((char *)&v15 - (v4 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v6 = v4 & 0xFF0;\n v7 = alloca(v6);\n if ( (v5 & 0xFFF) != 0 )\n *(__int64 *)((char *)&v14 + v6) = *(__int64 *)((char *)&v14 + v6);\n v8 = (const char *)&v15;\n __strcpy_chk(&v15, a1, v3);\n regcomp(&preg, pattern, 1);\n v9 = 0LL;\n while ( !regexec(&preg, v8, 1uLL, &pmatch, 0) )\n {\n rm_so = pmatch.rm_so;\n rm_eo = pmatch.rm_eo;\n v11 = pmatch.rm_eo - pmatch.rm_so;\n v18 = pmatch.rm_eo - pmatch.rm_so + 1;\n v12 = malloc(v18);\n __strncpy_chk(v12, &v8[rm_so], v11, v18);\n v12[v11] = 0;\n qword_4040[v9] = v12;\n v8 += rm_eo;\n ++v9;\n }\n regfree(&preg);\n *v16 = v9;\n return qword_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1269(const char *a1, uint32_t *a2) {\n unsigned int v2;\n unsigned int v3;\n unsigned int v4;\n short v5;\n signed long long v6;\n void *v7;\n const char *v8;\n long long v9;\n regoff_t rm_so;\n int v11;\n uint8_t *v12;\n long long v14;\n long long v15;\n uint32_t *v16;\n regoff_t rm_eo;\n unsigned int v18;\n regex_t preg;\n regmatch_t pmatch;\n char pattern[24];\n unsigned long long v22;\n v16 = a2;\n v22 = __readfsqword(40u);\n strcpy(pattern, \"\\\\b[a-zA-Z]{5}\\\\b\");\n v2 = strlen(a1);\n v3 = v2 + 1;\n v4 = v2 + 16;\n v5 = v4 & 65520;\n while (&v15 != (long long *)((char *)&v15 - (v4 & 18446744073709547520LL)))\n ;\n v6 = v4 & 4080;\n v7 = alloca(v6);\n if ((v5 & 4095) != 0)\n *(long long *)((char *)&v14 + v6) = *(long long *)((char *)&v14 + v6);\n v8 = (const char *)&v15;\n __strcpy_chk(&v15, a1, v3);\n regcomp(&preg, pattern, 1);\n v9 = 0LL;\n while (!regexec(&preg, v8, 1uLL, &pmatch, 0)) {\n rm_so = pmatch.rm_so;\n rm_eo = pmatch.rm_eo;\n v11 = pmatch.rm_eo - pmatch.rm_so;\n v18 = pmatch.rm_eo - pmatch.rm_so + 1;\n v12 = malloc(v18);\n __strncpy_chk(v12, &v8[rm_so], v11, v18);\n v12[v11] = 0;\n qword_4040[v9] = v12;\n v8 += rm_eo;\n ++v9;\n }\n regfree(&preg);\n *v16 = v9;\n return qword_4040;\n}", + "ida_pseudo_norm": "uint64_t *func0(const char *a1, uint32_t *a2) {\n unsigned int v2;\n unsigned int v3;\n unsigned int v4;\n short v5;\n signed long long v6;\n void *v7;\n const char *v8;\n long long v9;\n regoff_t rm_so;\n int v11;\n uint8_t *v12;\n long long v14;\n long long v15;\n uint32_t *v16;\n regoff_t rm_eo;\n unsigned int v18;\n regex_t preg;\n regmatch_t pmatch;\n char pattern[24];\n unsigned long long v22;\n v16 = a2;\n v22 = __readfsqword(40u);\n strcpy(pattern, \"\\\\b[a-zA-Z]{5}\\\\b\");\n v2 = strlen(a1);\n v3 = v2 + 1;\n v4 = v2 + 16;\n v5 = v4 & 65520;\n while (&v15 != (long long *)((char *)&v15 - (v4 & 18446744073709547520LL)))\n ;\n v6 = v4 & 4080;\n v7 = alloca(v6);\n if ((v5 & 4095) != 0)\n *(long long *)((char *)&v14 + v6) = *(long long *)((char *)&v14 + v6);\n v8 = (const char *)&v15;\n __strcpy_chk(&v15, a1, v3);\n regcomp(&preg, pattern, 1);\n v9 = 0LL;\n while (!regexec(&preg, v8, 1uLL, &pmatch, 0)) {\n rm_so = pmatch.rm_so;\n rm_eo = pmatch.rm_eo;\n v11 = pmatch.rm_eo - pmatch.rm_so;\n v18 = pmatch.rm_eo - pmatch.rm_so + 1;\n v12 = malloc(v18);\n __strncpy_chk(v12, &v8[rm_so], v11, v18);\n v12[v11] = 0;\n words_1[v9] = v12;\n v8 += rm_eo;\n ++v9;\n }\n regfree(&preg);\n *v16 = v9;\n return words_1;\n}" + }, + { + "index": 319, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(const char* text, int* count) {\n regex_t regex;\n regmatch_t matches[1];\n static char* words[10];\n char pattern[] = \"\\\\b[a-zA-Z]{5}\\\\b\";\n int word_count = 0;\n char str[strlen(text) + 1];\n strcpy(str, text);\n regcomp(®ex, pattern, REG_EXTENDED);\n char* p = str;\n while (regexec(®ex, p, 1, matches, 0) == 0) {\n int start = matches[0].rm_so;\n int end = matches[0].rm_eo;\n char* word = (char*)malloc(sizeof(char) * (end - start + 1));\n strncpy(word, p + start, end - start);\n word[end - start] = '\\0';\n words[word_count++] = word;\n p += end;\n }\n regfree(®ex);\n *count = word_count;\n return words;\n}", + "test": "int main() {\n\n int count;\n\n char** result;\n\n\n\n result = func0(\"Please move back to strem\", &count);\n\n assert(count == 1 && strcmp(result[0], \"strem\") == 0);\n\n\n\n result = func0(\"4K Ultra HD streaming player\", &count);\n\n assert(count == 1 && strcmp(result[0], \"Ultra\") == 0);\n\n\n\n result = func0(\"Streaming Media Player\", &count);\n\n assert(count == 1 && strcmp(result[0], \"Media\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\npush %r12\nmov %rdi,%r12\npush %rbx\nsub $0x98,%rsp\nmov %rsi,-0xb8(%rbp)\nmovdqa 0xd86(%rip),%xmm0\nmov %rsp,%rbx\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nmovaps %xmm0,-0x50(%rbp)\ncallq 10f0 \nlea 0x10(%rax),%rdx\nmov %rdx,%rcx\nand $0xfffffffffffff000,%rdx\nsub %rdx,%rbx\nand $0xfffffffffffffff0,%rcx\nmov %rbx,%rdx\ncmp %rdx,%rsp\nje 1407 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rdx,%rsp\njne 13f2 \nand $0xfff,%ecx\nsub %rcx,%rsp\ntest %rcx,%rcx\njne 1508 \nmov %r12,%rsi\nlea 0x1(%rax),%rdx\nmov %rsp,%rdi\nmov %rsp,%rbx\ncallq 1130 \nlea -0xa0(%rbp),%r13\nlea -0x50(%rbp),%rsi\nxor %r12d,%r12d\nmov $0x1,%edx\nmov %r13,%rdi\ncallq 1120 \nlea -0x58(%rbp),%rax\nmov %rax,-0xb0(%rbp)\njmp 14ac \nnopl 0x0(%rax,%rax,1)\nmov -0x54(%rbp),%r15d\nmov -0x58(%rbp),%esi\nmov %r15d,%r14d\nmov %esi,-0xa4(%rbp)\nsub %esi,%r14d\nlea 0x1(%r14),%edi\nmovslq %r14d,%r14\nmovslq %edi,%rdi\ncallq 1140 \nmovslq -0xa4(%rbp),%rsi\nmov %r14,%rdx\nmov %rax,%rdi\nadd %rbx,%rsi\ncallq 10d0 \nmovslq %r15d,%r8\nmov %rax,%rcx\nmovb $0x0,(%rax,%r14,1)\nlea 0x2b9f(%rip),%rax\nadd %r8,%rbx\nmov %rcx,(%rax,%r12,8)\nadd $0x1,%r12\nmov -0xb0(%rbp),%rcx\nxor %r8d,%r8d\nmov %rbx,%rsi\nmov %r13,%rdi\nmov $0x1,%edx\ncallq 1150 \ntest %eax,%eax\nje 1458 \nmov %r13,%rdi\ncallq 10e0 \nmov -0xb8(%rbp),%rax\nmov %r12d,(%rax)\nmov -0x38(%rbp),%rax\nxor %fs:0x28,%rax\njne 1513 \nlea -0x28(%rbp),%rsp\nlea 0x2b4a(%rip),%rax\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\nnopl 0x0(%rax)\norq $0x0,-0x8(%rsp,%rcx,1)\njmpq 1419 \ncallq 1100 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbx\nsub rsp, 98h\nmov [rbp+var_C0], rsi\nmovdqa xmm0, cs:xmmword_2120\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nmovaps xmmword ptr [rbp+pattern], xmm0\ncall _strlen\nmov rcx, rsp\nlea rsi, [rax+1]\nadd rax, 10h\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_1407\nloc_13F2:\nsub rsp, 1000h\nor [rsp+10C0h+var_C8], 0\ncmp rsp, rcx\njnz short loc_13F2\nloc_1407:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1520\nloc_1419:\nmov rcx, rsi\nmov rdx, rsi\nmov rdi, rsp\nmov rsi, r12\ncall ___memcpy_chk\nlea rsi, [rbp+pattern]; pattern\nmov rbx, rsp\nxor r12d, r12d\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rdi, rax; preg\nmov [rbp+var_B0], rax\ncall _regcomp\nlea rax, [rbp+var_58]\nmov [rbp+pmatch], rax\njmp short loc_14BA\nloc_1460:\nmov r15d, [rbp+var_54]\nmov esi, [rbp+var_58]\nmov r14d, r15d\nmov [rbp+var_A4], esi\nsub r14d, esi\nlea ecx, [r14+1]\nmovsxd r14, r14d\nmovsxd r13, ecx\nmov rdi, r13; size\ncall _malloc\nmovsxd rsi, [rbp+var_A4]\nmov rcx, r13\nmov rdx, r14\nmov rdi, rax\nadd rsi, rbx\ncall ___strncpy_chk\nmovsxd r8, r15d\nmov rdi, rax\nmov byte ptr [rax+r14], 0\nlea rax, words_1\nadd rbx, r8\nmov [rax+r12*8], rdi\nadd r12, 1\nloc_14BA:\nmov rcx, [rbp+pmatch]; pmatch\nxor r8d, r8d; eflags\nmov edx, 1; nmatch\nmov rsi, rbx; string\nmov rdi, [rbp+var_B0]; preg\ncall _regexec\ntest eax, eax\njz short loc_1460\nmov rdi, [rbp+var_B0]; preg\ncall _regfree\nmov rax, [rbp+var_C0]\nmov [rax], r12d\nmov rax, [rbp+var_38]\nsub rax, fs:28h\njnz short loc_152B\nlea rsp, [rbp-28h]\nlea rax, words_1\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1520:\nor [rsp+rdx+10C0h+var_10C8], 0\njmp loc_1419\nloc_152B:\ncall ___stack_chk_fail", + "ida_pseudo": "_QWORD *__fastcall func0(const char *a1, _DWORD *a2)\n{\n size_t v2; // rax\n _BYTE *v3; // rcx\n signed __int64 v4; // rdx\n void *v5; // rsp\n const char *v6; // rbx\n __int64 v7; // r12\n int v8; // r15d\n __int64 v9; // r14\n size_t v10; // r13\n void *v11; // rax\n __int64 v12; // rax\n _BYTE v15[4088]; // [rsp+8h] [rbp-10C0h] BYREF\n _DWORD *v16; // [rsp+1008h] [rbp-C0h] BYREF\n regmatch_t *__attribute__((__org_arrdim(0,0))) pmatch; // [rsp+1010h] [rbp-B8h]\n regex_t *p_preg; // [rsp+1018h] [rbp-B0h]\n int v19; // [rsp+1024h] [rbp-A4h]\n regex_t preg; // [rsp+1028h] [rbp-A0h] BYREF\n int v21; // [rsp+1070h] [rbp-58h] BYREF\n int v22; // [rsp+1074h] [rbp-54h]\n char pattern[16]; // [rsp+1078h] [rbp-50h] BYREF\n unsigned __int64 v24; // [rsp+1090h] [rbp-38h]\n\n v16 = a2;\n v24 = __readfsqword(0x28u);\n *(__m128i *)pattern = _mm_load_si128((const __m128i *)&xmmword_2120);\n v2 = strlen(a1);\n v3 = (char *)&v16 - ((v2 + 16) & 0xFFFFFFFFFFFFF000LL);\n if ( &v16 != (_DWORD **)v3 )\n {\n while ( v15 != v3 )\n ;\n }\n v4 = ((_WORD)v2 + 16) & 0xFF0;\n v5 = alloca(v4);\n if ( (((_WORD)v2 + 16) & 0xFF0) != 0 )\n *(_QWORD *)&v15[v4 - 8] = *(_QWORD *)&v15[v4 - 8];\n __memcpy_chk(v15, a1, v2 + 1, v2 + 1);\n v6 = v15;\n v7 = 0LL;\n p_preg = &preg;\n regcomp(&preg, pattern, 1);\n pmatch = (regmatch_t *)&v21;\n while ( !regexec(p_preg, v6, 1uLL, pmatch, 0) )\n {\n v8 = v22;\n v19 = v21;\n v9 = v22 - v21;\n v10 = v22 - v21 + 1;\n v11 = malloc(v10);\n v12 = __strncpy_chk(v11, &v6[v19], v9, v10);\n *(_BYTE *)(v12 + v9) = 0;\n v6 += v8;\n words_1[v7++] = v12;\n }\n regfree(p_preg);\n *v16 = v7;\n return words_1;\n}", + "ida_strip_asm": "sub_1390:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbx\nsub rsp, 98h\nmov [rbp+var_C0], rsi\nmovdqa xmm0, cs:xmmword_2120\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nmovaps xmmword ptr [rbp+pattern], xmm0\ncall _strlen\nmov rcx, rsp\nlea rsi, [rax+1]\nadd rax, 10h\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_1407\nloc_13F2:\nsub rsp, 1000h\nor [rsp+10C0h+var_C8], 0\ncmp rsp, rcx\njnz short loc_13F2\nloc_1407:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1520\nloc_1419:\nmov rcx, rsi\nmov rdx, rsi\nmov rdi, rsp\nmov rsi, r12\ncall ___memcpy_chk\nlea rsi, [rbp+pattern]; pattern\nmov rbx, rsp\nxor r12d, r12d\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rdi, rax; preg\nmov [rbp+var_B0], rax\ncall _regcomp\nlea rax, [rbp+var_58]\nmov [rbp+pmatch], rax\njmp short loc_14BA\nloc_1460:\nmov r15d, [rbp+var_54]\nmov esi, [rbp+var_58]\nmov r14d, r15d\nmov [rbp+var_A4], esi\nsub r14d, esi\nlea ecx, [r14+1]\nmovsxd r14, r14d\nmovsxd r13, ecx\nmov rdi, r13; size\ncall _malloc\nmovsxd rsi, [rbp+var_A4]\nmov rcx, r13\nmov rdx, r14\nmov rdi, rax\nadd rsi, rbx\ncall ___strncpy_chk\nmovsxd r8, r15d\nmov rdi, rax\nmov byte ptr [rax+r14], 0\nlea rax, unk_4040\nadd rbx, r8\nmov [rax+r12*8], rdi\nadd r12, 1\nloc_14BA:\nmov rcx, [rbp+pmatch]; pmatch\nxor r8d, r8d; eflags\nmov edx, 1; nmatch\nmov rsi, rbx; string\nmov rdi, [rbp+var_B0]; preg\ncall _regexec\ntest eax, eax\njz short loc_1460\nmov rdi, [rbp+var_B0]; preg\ncall _regfree\nmov rax, [rbp+var_C0]\nmov [rax], r12d\nmov rax, [rbp+var_38]\nsub rax, fs:28h\njnz short loc_152B\nlea rsp, [rbp-28h]\nlea rax, unk_4040\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1520:\nor [rsp+rdx+10C0h+var_10C8], 0\njmp loc_1419\nloc_152B:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1390(const char *a1, _DWORD *a2)\n{\n size_t v2; // rax\n _BYTE *v3; // rcx\n signed __int64 v4; // rdx\n void *v5; // rsp\n const char *v6; // rbx\n __int64 v7; // r12\n int v8; // r15d\n __int64 v9; // r14\n size_t v10; // r13\n void *v11; // rax\n __int64 v12; // rax\n _BYTE v15[4088]; // [rsp+8h] [rbp-10C0h] BYREF\n _DWORD *v16; // [rsp+1008h] [rbp-C0h] BYREF\n regmatch_t *__attribute__((__org_arrdim(0,0))) pmatch; // [rsp+1010h] [rbp-B8h]\n regex_t *p_preg; // [rsp+1018h] [rbp-B0h]\n int v19; // [rsp+1024h] [rbp-A4h]\n regex_t preg; // [rsp+1028h] [rbp-A0h] BYREF\n int v21; // [rsp+1070h] [rbp-58h] BYREF\n int v22; // [rsp+1074h] [rbp-54h]\n char pattern[16]; // [rsp+1078h] [rbp-50h] BYREF\n unsigned __int64 v24; // [rsp+1090h] [rbp-38h]\n\n v16 = a2;\n v24 = __readfsqword(0x28u);\n *(__m128i *)pattern = _mm_load_si128((const __m128i *)&xmmword_2120);\n v2 = strlen(a1);\n v3 = (char *)&v16 - ((v2 + 16) & 0xFFFFFFFFFFFFF000LL);\n if ( &v16 != (_DWORD **)v3 )\n {\n while ( v15 != v3 )\n ;\n }\n v4 = ((_WORD)v2 + 16) & 0xFF0;\n v5 = alloca(v4);\n if ( (((_WORD)v2 + 16) & 0xFF0) != 0 )\n *(_QWORD *)&v15[v4 - 8] = *(_QWORD *)&v15[v4 - 8];\n __memcpy_chk(v15, a1, v2 + 1, v2 + 1);\n v6 = v15;\n v7 = 0LL;\n p_preg = &preg;\n regcomp(&preg, pattern, 1);\n pmatch = (regmatch_t *)&v21;\n while ( !regexec(p_preg, v6, 1uLL, pmatch, 0) )\n {\n v8 = v22;\n v19 = v21;\n v9 = v22 - v21;\n v10 = v22 - v21 + 1;\n v11 = malloc(v10);\n v12 = __strncpy_chk(v11, &v6[v19], v9, v10);\n *(_BYTE *)(v12 + v9) = 0;\n v6 += v8;\n qword_4040[v7++] = v12;\n }\n regfree(p_preg);\n *v16 = v7;\n return qword_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1390(const char *a1, uint32_t *a2) {\n unsigned int v2;\n uint8_t *v3;\n signed long long v4;\n void *v5;\n const char *v6;\n long long v7;\n int v8;\n long long v9;\n unsigned int v10;\n void *v11;\n long long v12;\n uint8_t v15[4088];\n uint32_t *v16;\n regmatch_t *__attribute__((__org_arrdim(0, 0))) pmatch;\n regex_t *p_preg;\n int v19;\n regex_t preg;\n int v21;\n int v22;\n char pattern[16];\n unsigned long long v24;\n v16 = a2;\n v24 = __readfsqword(40u);\n *(__m128i *)pattern = _mm_load_si128((const __m128i *)&xmmword_2120);\n v2 = strlen(a1);\n v3 = (char *)&v16 - ((v2 + 16) & 18446744073709547520LL);\n if (&v16 != (uint32_t **)v3) {\n while (v15 != v3)\n ;\n }\n v4 = ((unsigned short)v2 + 16) & 4080;\n v5 = alloca(v4);\n if ((((unsigned short)v2 + 16) & 4080) != 0)\n *(uint64_t *)&v15[v4 - 8] = *(uint64_t *)&v15[v4 - 8];\n __memcpy_chk(v15, a1, v2 + 1, v2 + 1);\n v6 = v15;\n v7 = 0LL;\n p_preg = &preg;\n regcomp(&preg, pattern, 1);\n pmatch = (regmatch_t *)&v21;\n while (!regexec(p_preg, v6, 1uLL, pmatch, 0)) {\n v8 = v22;\n v19 = v21;\n v9 = v22 - v21;\n v10 = v22 - v21 + 1;\n v11 = malloc(v10);\n v12 = __strncpy_chk(v11, &v6[v19], v9, v10);\n *(uint8_t *)(v12 + v9) = 0;\n v6 += v8;\n qword_4040[v7++] = v12;\n }\n regfree(p_preg);\n *v16 = v7;\n return qword_4040;\n}", + "ida_pseudo_norm": "uint64_t *func0(const char *a1, uint32_t *a2) {\n unsigned int v2;\n uint8_t *v3;\n signed long long v4;\n void *v5;\n const char *v6;\n long long v7;\n int v8;\n long long v9;\n unsigned int v10;\n void *v11;\n long long v12;\n uint8_t v15[4088];\n uint32_t *v16;\n regmatch_t *__attribute__((__org_arrdim(0, 0))) pmatch;\n regex_t *p_preg;\n int v19;\n regex_t preg;\n int v21;\n int v22;\n char pattern[16];\n unsigned long long v24;\n v16 = a2;\n v24 = __readfsqword(40u);\n *(__m128i *)pattern = _mm_load_si128((const __m128i *)&xmmword_2120);\n v2 = strlen(a1);\n v3 = (char *)&v16 - ((v2 + 16) & 18446744073709547520LL);\n if (&v16 != (uint32_t **)v3) {\n while (v15 != v3)\n ;\n }\n v4 = ((unsigned short)v2 + 16) & 4080;\n v5 = alloca(v4);\n if ((((unsigned short)v2 + 16) & 4080) != 0)\n *(uint64_t *)&v15[v4 - 8] = *(uint64_t *)&v15[v4 - 8];\n __memcpy_chk(v15, a1, v2 + 1, v2 + 1);\n v6 = v15;\n v7 = 0LL;\n p_preg = &preg;\n regcomp(&preg, pattern, 1);\n pmatch = (regmatch_t *)&v21;\n while (!regexec(p_preg, v6, 1uLL, pmatch, 0)) {\n v8 = v22;\n v19 = v21;\n v9 = v22 - v21;\n v10 = v22 - v21 + 1;\n v11 = malloc(v10);\n v12 = __strncpy_chk(v11, &v6[v19], v9, v10);\n *(uint8_t *)(v12 + v9) = 0;\n v6 += v8;\n words_1[v7++] = v12;\n }\n regfree(p_preg);\n *v16 = v7;\n return words_1;\n}" + }, + { + "index": 319, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(const char* text, int* count) {\n regex_t regex;\n regmatch_t matches[1];\n static char* words[10];\n char pattern[] = \"\\\\b[a-zA-Z]{5}\\\\b\";\n int word_count = 0;\n char str[strlen(text) + 1];\n strcpy(str, text);\n regcomp(®ex, pattern, REG_EXTENDED);\n char* p = str;\n while (regexec(®ex, p, 1, matches, 0) == 0) {\n int start = matches[0].rm_so;\n int end = matches[0].rm_eo;\n char* word = (char*)malloc(sizeof(char) * (end - start + 1));\n strncpy(word, p + start, end - start);\n word[end - start] = '\\0';\n words[word_count++] = word;\n p += end;\n }\n regfree(®ex);\n *count = word_count;\n return words;\n}", + "test": "int main() {\n\n int count;\n\n char** result;\n\n\n\n result = func0(\"Please move back to strem\", &count);\n\n assert(count == 1 && strcmp(result[0], \"strem\") == 0);\n\n\n\n result = func0(\"4K Ultra HD streaming player\", &count);\n\n assert(count == 1 && strcmp(result[0], \"Ultra\") == 0);\n\n\n\n result = func0(\"Streaming Media Player\", &count);\n\n assert(count == 1 && strcmp(result[0], \"Media\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\npush %r12\nmov %rdi,%r12\npush %rbx\nsub $0x98,%rsp\nmov %rsi,-0xb8(%rbp)\nmovdqa 0xd86(%rip),%xmm0\nmov %rsp,%rbx\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nmovaps %xmm0,-0x50(%rbp)\ncallq 10f0 \nlea 0x10(%rax),%rdx\nmov %rdx,%rcx\nand $0xfffffffffffff000,%rdx\nsub %rdx,%rbx\nand $0xfffffffffffffff0,%rcx\nmov %rbx,%rdx\ncmp %rdx,%rsp\nje 1407 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rdx,%rsp\njne 13f2 \nand $0xfff,%ecx\nsub %rcx,%rsp\ntest %rcx,%rcx\njne 1508 \nmov %r12,%rsi\nlea 0x1(%rax),%rdx\nmov %rsp,%rdi\nmov %rsp,%rbx\ncallq 1130 \nlea -0xa0(%rbp),%r13\nlea -0x50(%rbp),%rsi\nxor %r12d,%r12d\nmov $0x1,%edx\nmov %r13,%rdi\ncallq 1120 \nlea -0x58(%rbp),%rax\nmov %rax,-0xb0(%rbp)\njmp 14ac \nnopl 0x0(%rax,%rax,1)\nmov -0x54(%rbp),%r15d\nmov -0x58(%rbp),%esi\nmov %r15d,%r14d\nmov %esi,-0xa4(%rbp)\nsub %esi,%r14d\nlea 0x1(%r14),%edi\nmovslq %r14d,%r14\nmovslq %edi,%rdi\ncallq 1140 \nmovslq -0xa4(%rbp),%rsi\nmov %r14,%rdx\nmov %rax,%rdi\nadd %rbx,%rsi\ncallq 10d0 \nmovslq %r15d,%r8\nmov %rax,%rcx\nmovb $0x0,(%rax,%r14,1)\nlea 0x2b9f(%rip),%rax\nadd %r8,%rbx\nmov %rcx,(%rax,%r12,8)\nadd $0x1,%r12\nmov -0xb0(%rbp),%rcx\nxor %r8d,%r8d\nmov %rbx,%rsi\nmov %r13,%rdi\nmov $0x1,%edx\ncallq 1150 \ntest %eax,%eax\nje 1458 \nmov %r13,%rdi\ncallq 10e0 \nmov -0xb8(%rbp),%rax\nmov %r12d,(%rax)\nmov -0x38(%rbp),%rax\nxor %fs:0x28,%rax\njne 1513 \nlea -0x28(%rbp),%rsp\nlea 0x2b4a(%rip),%rax\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\nnopl 0x0(%rax)\norq $0x0,-0x8(%rsp,%rcx,1)\njmpq 1419 \ncallq 1100 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbx\nsub rsp, 98h\nmov [rbp+var_C0], rsi\nmovdqa xmm0, cs:xmmword_2120\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nmovaps xmmword ptr [rbp+pattern], xmm0\ncall _strlen\nmov rcx, rsp\nlea rsi, [rax+1]\nadd rax, 10h\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_1407\nloc_13F2:\nsub rsp, 1000h\nor [rsp+10C0h+var_C8], 0\ncmp rsp, rcx\njnz short loc_13F2\nloc_1407:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1520\nloc_1419:\nmov rcx, rsi\nmov rdx, rsi\nmov rdi, rsp\nmov rsi, r12\ncall ___memcpy_chk\nlea rsi, [rbp+pattern]; pattern\nmov rbx, rsp\nxor r12d, r12d\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rdi, rax; preg\nmov [rbp+var_B0], rax\ncall _regcomp\nlea rax, [rbp+var_58]\nmov [rbp+pmatch], rax\njmp short loc_14BA\nloc_1460:\nmov r15d, [rbp+var_54]\nmov esi, [rbp+var_58]\nmov r14d, r15d\nmov [rbp+var_A4], esi\nsub r14d, esi\nlea ecx, [r14+1]\nmovsxd r14, r14d\nmovsxd r13, ecx\nmov rdi, r13; size\ncall _malloc\nmovsxd rsi, [rbp+var_A4]\nmov rcx, r13\nmov rdx, r14\nmov rdi, rax\nadd rsi, rbx\ncall ___strncpy_chk\nmovsxd r8, r15d\nmov rdi, rax\nmov byte ptr [rax+r14], 0\nlea rax, words_1\nadd rbx, r8\nmov [rax+r12*8], rdi\nadd r12, 1\nloc_14BA:\nmov rcx, [rbp+pmatch]; pmatch\nxor r8d, r8d; eflags\nmov edx, 1; nmatch\nmov rsi, rbx; string\nmov rdi, [rbp+var_B0]; preg\ncall _regexec\ntest eax, eax\njz short loc_1460\nmov rdi, [rbp+var_B0]; preg\ncall _regfree\nmov rax, [rbp+var_C0]\nmov [rax], r12d\nmov rax, [rbp+var_38]\nsub rax, fs:28h\njnz short loc_152B\nlea rsp, [rbp-28h]\nlea rax, words_1\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1520:\nor [rsp+rdx+10C0h+var_10C8], 0\njmp loc_1419\nloc_152B:\ncall ___stack_chk_fail", + "ida_pseudo": "_QWORD *__fastcall func0(const char *a1, _DWORD *a2)\n{\n size_t v2; // rax\n _BYTE *v3; // rcx\n signed __int64 v4; // rdx\n void *v5; // rsp\n const char *v6; // rbx\n __int64 v7; // r12\n int v8; // r15d\n __int64 v9; // r14\n size_t v10; // r13\n void *v11; // rax\n __int64 v12; // rax\n _BYTE v15[4088]; // [rsp+8h] [rbp-10C0h] BYREF\n _DWORD *v16; // [rsp+1008h] [rbp-C0h] BYREF\n regmatch_t *__attribute__((__org_arrdim(0,0))) pmatch; // [rsp+1010h] [rbp-B8h]\n regex_t *p_preg; // [rsp+1018h] [rbp-B0h]\n int v19; // [rsp+1024h] [rbp-A4h]\n regex_t preg; // [rsp+1028h] [rbp-A0h] BYREF\n int v21; // [rsp+1070h] [rbp-58h] BYREF\n int v22; // [rsp+1074h] [rbp-54h]\n char pattern[16]; // [rsp+1078h] [rbp-50h] BYREF\n unsigned __int64 v24; // [rsp+1090h] [rbp-38h]\n\n v16 = a2;\n v24 = __readfsqword(0x28u);\n *(__m128i *)pattern = _mm_load_si128((const __m128i *)&xmmword_2120);\n v2 = strlen(a1);\n v3 = (char *)&v16 - ((v2 + 16) & 0xFFFFFFFFFFFFF000LL);\n if ( &v16 != (_DWORD **)v3 )\n {\n while ( v15 != v3 )\n ;\n }\n v4 = ((_WORD)v2 + 16) & 0xFF0;\n v5 = alloca(v4);\n if ( (((_WORD)v2 + 16) & 0xFF0) != 0 )\n *(_QWORD *)&v15[v4 - 8] = *(_QWORD *)&v15[v4 - 8];\n __memcpy_chk(v15, a1, v2 + 1, v2 + 1);\n v6 = v15;\n v7 = 0LL;\n p_preg = &preg;\n regcomp(&preg, pattern, 1);\n pmatch = (regmatch_t *)&v21;\n while ( !regexec(p_preg, v6, 1uLL, pmatch, 0) )\n {\n v8 = v22;\n v19 = v21;\n v9 = v22 - v21;\n v10 = v22 - v21 + 1;\n v11 = malloc(v10);\n v12 = __strncpy_chk(v11, &v6[v19], v9, v10);\n *(_BYTE *)(v12 + v9) = 0;\n v6 += v8;\n words_1[v7++] = v12;\n }\n regfree(p_preg);\n *v16 = v7;\n return words_1;\n}", + "ida_strip_asm": "sub_1390:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbx\nsub rsp, 98h\nmov [rbp+var_C0], rsi\nmovdqa xmm0, cs:xmmword_2120\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nmovaps xmmword ptr [rbp+pattern], xmm0\ncall _strlen\nmov rcx, rsp\nlea rsi, [rax+1]\nadd rax, 10h\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_1407\nloc_13F2:\nsub rsp, 1000h\nor [rsp+10C0h+var_C8], 0\ncmp rsp, rcx\njnz short loc_13F2\nloc_1407:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1520\nloc_1419:\nmov rcx, rsi\nmov rdx, rsi\nmov rdi, rsp\nmov rsi, r12\ncall ___memcpy_chk\nlea rsi, [rbp+pattern]; pattern\nmov rbx, rsp\nxor r12d, r12d\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rdi, rax; preg\nmov [rbp+var_B0], rax\ncall _regcomp\nlea rax, [rbp+var_58]\nmov [rbp+pmatch], rax\njmp short loc_14BA\nloc_1460:\nmov r15d, [rbp+var_54]\nmov esi, [rbp+var_58]\nmov r14d, r15d\nmov [rbp+var_A4], esi\nsub r14d, esi\nlea ecx, [r14+1]\nmovsxd r14, r14d\nmovsxd r13, ecx\nmov rdi, r13; size\ncall _malloc\nmovsxd rsi, [rbp+var_A4]\nmov rcx, r13\nmov rdx, r14\nmov rdi, rax\nadd rsi, rbx\ncall ___strncpy_chk\nmovsxd r8, r15d\nmov rdi, rax\nmov byte ptr [rax+r14], 0\nlea rax, unk_4040\nadd rbx, r8\nmov [rax+r12*8], rdi\nadd r12, 1\nloc_14BA:\nmov rcx, [rbp+pmatch]; pmatch\nxor r8d, r8d; eflags\nmov edx, 1; nmatch\nmov rsi, rbx; string\nmov rdi, [rbp+var_B0]; preg\ncall _regexec\ntest eax, eax\njz short loc_1460\nmov rdi, [rbp+var_B0]; preg\ncall _regfree\nmov rax, [rbp+var_C0]\nmov [rax], r12d\nmov rax, [rbp+var_38]\nsub rax, fs:28h\njnz short loc_152B\nlea rsp, [rbp-28h]\nlea rax, unk_4040\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1520:\nor [rsp+rdx+10C0h+var_10C8], 0\njmp loc_1419\nloc_152B:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1390(const char *a1, _DWORD *a2)\n{\n size_t v2; // rax\n _BYTE *v3; // rcx\n signed __int64 v4; // rdx\n void *v5; // rsp\n const char *v6; // rbx\n __int64 v7; // r12\n int v8; // r15d\n __int64 v9; // r14\n size_t v10; // r13\n void *v11; // rax\n __int64 v12; // rax\n _BYTE v15[4088]; // [rsp+8h] [rbp-10C0h] BYREF\n _DWORD *v16; // [rsp+1008h] [rbp-C0h] BYREF\n regmatch_t *__attribute__((__org_arrdim(0,0))) pmatch; // [rsp+1010h] [rbp-B8h]\n regex_t *p_preg; // [rsp+1018h] [rbp-B0h]\n int v19; // [rsp+1024h] [rbp-A4h]\n regex_t preg; // [rsp+1028h] [rbp-A0h] BYREF\n int v21; // [rsp+1070h] [rbp-58h] BYREF\n int v22; // [rsp+1074h] [rbp-54h]\n char pattern[16]; // [rsp+1078h] [rbp-50h] BYREF\n unsigned __int64 v24; // [rsp+1090h] [rbp-38h]\n\n v16 = a2;\n v24 = __readfsqword(0x28u);\n *(__m128i *)pattern = _mm_load_si128((const __m128i *)&xmmword_2120);\n v2 = strlen(a1);\n v3 = (char *)&v16 - ((v2 + 16) & 0xFFFFFFFFFFFFF000LL);\n if ( &v16 != (_DWORD **)v3 )\n {\n while ( v15 != v3 )\n ;\n }\n v4 = ((_WORD)v2 + 16) & 0xFF0;\n v5 = alloca(v4);\n if ( (((_WORD)v2 + 16) & 0xFF0) != 0 )\n *(_QWORD *)&v15[v4 - 8] = *(_QWORD *)&v15[v4 - 8];\n __memcpy_chk(v15, a1, v2 + 1, v2 + 1);\n v6 = v15;\n v7 = 0LL;\n p_preg = &preg;\n regcomp(&preg, pattern, 1);\n pmatch = (regmatch_t *)&v21;\n while ( !regexec(p_preg, v6, 1uLL, pmatch, 0) )\n {\n v8 = v22;\n v19 = v21;\n v9 = v22 - v21;\n v10 = v22 - v21 + 1;\n v11 = malloc(v10);\n v12 = __strncpy_chk(v11, &v6[v19], v9, v10);\n *(_BYTE *)(v12 + v9) = 0;\n v6 += v8;\n qword_4040[v7++] = v12;\n }\n regfree(p_preg);\n *v16 = v7;\n return qword_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1390(const char *a1, uint32_t *a2) {\n unsigned int v2;\n uint8_t *v3;\n signed long long v4;\n void *v5;\n const char *v6;\n long long v7;\n int v8;\n long long v9;\n unsigned int v10;\n void *v11;\n long long v12;\n uint8_t v15[4088];\n uint32_t *v16;\n regmatch_t *__attribute__((__org_arrdim(0, 0))) pmatch;\n regex_t *p_preg;\n int v19;\n regex_t preg;\n int v21;\n int v22;\n char pattern[16];\n unsigned long long v24;\n v16 = a2;\n v24 = __readfsqword(40u);\n *(__m128i *)pattern = _mm_load_si128((const __m128i *)&xmmword_2120);\n v2 = strlen(a1);\n v3 = (char *)&v16 - ((v2 + 16) & 18446744073709547520LL);\n if (&v16 != (uint32_t **)v3) {\n while (v15 != v3)\n ;\n }\n v4 = ((unsigned short)v2 + 16) & 4080;\n v5 = alloca(v4);\n if ((((unsigned short)v2 + 16) & 4080) != 0)\n *(uint64_t *)&v15[v4 - 8] = *(uint64_t *)&v15[v4 - 8];\n __memcpy_chk(v15, a1, v2 + 1, v2 + 1);\n v6 = v15;\n v7 = 0LL;\n p_preg = &preg;\n regcomp(&preg, pattern, 1);\n pmatch = (regmatch_t *)&v21;\n while (!regexec(p_preg, v6, 1uLL, pmatch, 0)) {\n v8 = v22;\n v19 = v21;\n v9 = v22 - v21;\n v10 = v22 - v21 + 1;\n v11 = malloc(v10);\n v12 = __strncpy_chk(v11, &v6[v19], v9, v10);\n *(uint8_t *)(v12 + v9) = 0;\n v6 += v8;\n qword_4040[v7++] = v12;\n }\n regfree(p_preg);\n *v16 = v7;\n return qword_4040;\n}", + "ida_pseudo_norm": "uint64_t *func0(const char *a1, uint32_t *a2) {\n unsigned int v2;\n uint8_t *v3;\n signed long long v4;\n void *v5;\n const char *v6;\n long long v7;\n int v8;\n long long v9;\n unsigned int v10;\n void *v11;\n long long v12;\n uint8_t v15[4088];\n uint32_t *v16;\n regmatch_t *__attribute__((__org_arrdim(0, 0))) pmatch;\n regex_t *p_preg;\n int v19;\n regex_t preg;\n int v21;\n int v22;\n char pattern[16];\n unsigned long long v24;\n v16 = a2;\n v24 = __readfsqword(40u);\n *(__m128i *)pattern = _mm_load_si128((const __m128i *)&xmmword_2120);\n v2 = strlen(a1);\n v3 = (char *)&v16 - ((v2 + 16) & 18446744073709547520LL);\n if (&v16 != (uint32_t **)v3) {\n while (v15 != v3)\n ;\n }\n v4 = ((unsigned short)v2 + 16) & 4080;\n v5 = alloca(v4);\n if ((((unsigned short)v2 + 16) & 4080) != 0)\n *(uint64_t *)&v15[v4 - 8] = *(uint64_t *)&v15[v4 - 8];\n __memcpy_chk(v15, a1, v2 + 1, v2 + 1);\n v6 = v15;\n v7 = 0LL;\n p_preg = &preg;\n regcomp(&preg, pattern, 1);\n pmatch = (regmatch_t *)&v21;\n while (!regexec(p_preg, v6, 1uLL, pmatch, 0)) {\n v8 = v22;\n v19 = v21;\n v9 = v22 - v21;\n v10 = v22 - v21 + 1;\n v11 = malloc(v10);\n v12 = __strncpy_chk(v11, &v6[v19], v9, v10);\n *(uint8_t *)(v12 + v9) = 0;\n v6 += v8;\n words_1[v7++] = v12;\n }\n regfree(p_preg);\n *v16 = v7;\n return words_1;\n}" + }, + { + "index": 320, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int sumofsquares = 0;\n int squareofsum = 0;\n for (int num = 1; num <= n; num++) {\n sumofsquares += num * num;\n squareofsum += num;\n }\n squareofsum = squareofsum * squareofsum;\n return squareofsum - sumofsquares;\n}", + "test": "int main() {\n\n assert(func0(12) == 5434);\n\n assert(func0(20) == 41230);\n\n assert(func0(54) == 2151270);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x1,-0x4(%rbp)\njmp 117e \nmov -0x4(%rbp),%eax\nimul %eax,%eax\nadd %eax,-0xc(%rbp)\nmov -0x4(%rbp),%eax\nadd %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x14(%rbp),%eax\njle 116b \nmov -0x8(%rbp),%eax\nimul %eax,%eax\nmov %eax,-0x8(%rbp)\nmov -0x8(%rbp),%eax\nsub -0xc(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\nmov [rbp+var_4], 1\njmp short loc_117E\nloc_116B:\nmov eax, [rbp+var_4]\nimul eax, eax\nadd [rbp+var_C], eax\nmov eax, [rbp+var_4]\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_117E:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_14]\njle short loc_116B\nmov eax, [rbp+var_8]\nimul eax, eax\nmov [rbp+var_8], eax\nmov eax, [rbp+var_8]\nsub eax, [rbp+var_C]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v2; // [rsp+8h] [rbp-Ch]\n int v3; // [rsp+Ch] [rbp-8h]\n int i; // [rsp+10h] [rbp-4h]\n\n v2 = 0;\n v3 = 0;\n for ( i = 1; i <= a1; ++i )\n {\n v2 += i * i;\n v3 += i;\n }\n return (unsigned int)(v3 * v3 - v2);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\nmov [rbp+var_4], 1\njmp short loc_117E\nloc_116B:\nmov eax, [rbp+var_4]\nimul eax, eax\nadd [rbp+var_C], eax\nmov eax, [rbp+var_4]\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_117E:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_14]\njle short loc_116B\nmov eax, [rbp+var_8]\nimul eax, eax\nmov [rbp+var_8], eax\nmov eax, [rbp+var_8]\nsub eax, [rbp+var_C]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v2; // [rsp+8h] [rbp-Ch]\n int v3; // [rsp+Ch] [rbp-8h]\n int i; // [rsp+10h] [rbp-4h]\n\n v2 = 0;\n v3 = 0;\n for ( i = 1; i <= a1; ++i )\n {\n v2 += i * i;\n v3 += i;\n }\n return (unsigned int)(v3 * v3 - v2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v2;\n int v3;\n int i;\n v2 = 0;\n v3 = 0;\n for (i = 1; i <= a1; ++i) {\n v2 += i * i;\n v3 += i;\n }\n return (unsigned int)(v3 * v3 - v2);\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v2;\n int v3;\n int i;\n v2 = 0;\n v3 = 0;\n for (i = 1; i <= a1; ++i) {\n v2 += i * i;\n v3 += i;\n }\n return (unsigned int)(v3 * v3 - v2);\n}" + }, + { + "index": 320, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int sumofsquares = 0;\n int squareofsum = 0;\n for (int num = 1; num <= n; num++) {\n sumofsquares += num * num;\n squareofsum += num;\n }\n squareofsum = squareofsum * squareofsum;\n return squareofsum - sumofsquares;\n}", + "test": "int main() {\n\n assert(func0(12) == 5434);\n\n assert(func0(20) == 41230);\n\n assert(func0(54) == 2151270);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\njle 1179 \nadd $0x1,%edi\nmov $0x1,%edx\nmov $0x0,%eax\nmov $0x0,%ecx\nmov %edx,%esi\nimul %edx,%esi\nadd %esi,%ecx\nadd %edx,%eax\nadd $0x1,%edx\ncmp %edi,%edx\njne 1163 \nimul %eax,%eax\nsub %ecx,%eax\nretq\nmov $0x0,%eax\nmov $0x0,%ecx\njmp 1173 \n", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njle short loc_1179\nadd edi, 1\nmov edx, 1\nmov eax, 0\nmov ecx, 0\nloc_1163:\nmov esi, edx\nimul esi, edx\nadd ecx, esi\nadd eax, edx\nadd edx, 1\ncmp edx, edi\njnz short loc_1163\nloc_1173:\nimul eax, eax\nsub eax, ecx\nretn\nloc_1179:\nmov eax, 0\nmov ecx, 0\njmp short loc_1173", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // edi\n int v2; // edx\n int v3; // eax\n int v4; // ecx\n\n if ( a1 <= 0 )\n {\n v3 = 0;\n v4 = 0;\n }\n else\n {\n v1 = a1 + 1;\n v2 = 1;\n v3 = 0;\n v4 = 0;\n do\n {\n v4 += v2 * v2;\n v3 += v2++;\n }\n while ( v2 != v1 );\n }\n return (unsigned int)(v3 * v3 - v4);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ntest edi, edi\njle short loc_1179\nadd edi, 1\nmov edx, 1\nmov eax, 0\nmov ecx, 0\nloc_1163:\nmov esi, edx\nimul esi, edx\nadd ecx, esi\nadd eax, edx\nadd edx, 1\ncmp edx, edi\njnz short loc_1163\nloc_1173:\nimul eax, eax\nsub eax, ecx\nretn\nloc_1179:\nmov eax, 0\nmov ecx, 0\njmp short loc_1173", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v1; // edi\n int v2; // edx\n int v3; // eax\n int v4; // ecx\n\n if ( a1 <= 0 )\n {\n v3 = 0;\n v4 = 0;\n }\n else\n {\n v1 = a1 + 1;\n v2 = 1;\n v3 = 0;\n v4 = 0;\n do\n {\n v4 += v2 * v2;\n v3 += v2++;\n }\n while ( v2 != v1 );\n }\n return (unsigned int)(v3 * v3 - v4);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v1;\n int v2;\n int v3;\n int v4;\n if (a1 <= 0) {\n v3 = 0;\n v4 = 0;\n } else {\n v1 = a1 + 1;\n v2 = 1;\n v3 = 0;\n v4 = 0;\n do {\n v4 += v2 * v2;\n v3 += v2++;\n } while (v2 != v1);\n }\n return (unsigned int)(v3 * v3 - v4);\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v2;\n int v3;\n int v4;\n if (a1 <= 0) {\n v3 = 0;\n v4 = 0;\n } else {\n v1 = a1 + 1;\n v2 = 1;\n v3 = 0;\n v4 = 0;\n do {\n v4 += v2 * v2;\n v3 += v2++;\n } while (v2 != v1);\n }\n return (unsigned int)(v3 * v3 - v4);\n}" + }, + { + "index": 321, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* s) {\n static char res[1000];\n int l = strlen(s);\n int pos = 0;\n for (int i = 1; i <= l; i++) {\n pos += sprintf(&res[pos], \"%d\", i);\n }\n for (int i = l - 1; i > 0; i--) {\n pos += sprintf(&res[pos], \"%d\", i);\n }\n res[pos] = '\\0';\n return res;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"111111\"), \"12345654321\") == 0);\n\n assert(strcmp(func0(\"1111\"), \"1234321\") == 0);\n\n assert(strcmp(func0(\"13333122222\"), \"123456789101110987654321\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov -0x18(%rbp),%rax\nmov %rax,%rdi\ncallq 1080 \nmov %eax,-0x4(%rbp)\nmovl $0x0,-0x10(%rbp)\nmovl $0x1,-0xc(%rbp)\njmp 1208 \nmov -0x10(%rbp),%eax\ncltq\nlea 0x2e5c(%rip),%rdx\nlea (%rax,%rdx,1),%rcx\nmov -0xc(%rbp),%eax\nmov %eax,%edx\nlea 0xe14(%rip),%rsi\nmov %rcx,%rdi\nmov $0x0,%eax\ncallq 10b0 \nadd %eax,-0x10(%rbp)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x4(%rbp),%eax\njle 11d8 \nmov -0x4(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0x8(%rbp)\njmp 124b \nmov -0x10(%rbp),%eax\ncltq\nlea 0x2e19(%rip),%rdx\nlea (%rax,%rdx,1),%rcx\nmov -0x8(%rbp),%eax\nmov %eax,%edx\nlea 0xdd1(%rip),%rsi\nmov %rcx,%rdi\nmov $0x0,%eax\ncallq 10b0 \nadd %eax,-0x10(%rbp)\nsubl $0x1,-0x8(%rbp)\ncmpl $0x0,-0x8(%rbp)\njg 121b \nmov -0x10(%rbp),%eax\ncltq\nlea 0x2de3(%rip),%rdx\nmovb $0x0,(%rax,%rdx,1)\nlea 0x2dd8(%rip),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_10], 0\nmov [rbp+var_C], 1\njmp short loc_120B\nloc_11D8:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, res_1\nlea rcx, [rax+rdx]\nmov eax, [rbp+var_C]\nmov edx, eax\nlea rax, format; \"%d\"\nmov rsi, rax; format\nmov rdi, rcx; s\nmov eax, 0\ncall _sprintf\nadd [rbp+var_10], eax\nadd [rbp+var_C], 1\nloc_120B:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_4]\njle short loc_11D8\nmov eax, [rbp+var_4]\nsub eax, 1\nmov [rbp+var_8], eax\njmp short loc_1251\nloc_121E:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, res_1\nlea rcx, [rax+rdx]\nmov eax, [rbp+var_8]\nmov edx, eax\nlea rax, format; \"%d\"\nmov rsi, rax; format\nmov rdi, rcx; s\nmov eax, 0\ncall _sprintf\nadd [rbp+var_10], eax\nsub [rbp+var_8], 1\nloc_1251:\ncmp [rbp+var_8], 0\njg short loc_121E\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, res_1\nmov byte ptr [rax+rdx], 0\nlea rax, res_1\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(const char *a1)\n{\n int v2; // [rsp+10h] [rbp-10h]\n int i; // [rsp+14h] [rbp-Ch]\n int j; // [rsp+18h] [rbp-8h]\n int v5; // [rsp+1Ch] [rbp-4h]\n\n v5 = strlen(a1);\n v2 = 0;\n for ( i = 1; i <= v5; ++i )\n v2 += sprintf(&res_1[v2], \"%d\", i);\n for ( j = v5 - 1; j > 0; --j )\n v2 += sprintf(&res_1[v2], \"%d\", j);\n res_1[v2] = 0;\n return res_1;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_10], 0\nmov [rbp+var_C], 1\njmp short loc_120B\nloc_11D8:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, unk_4040\nlea rcx, [rax+rdx]\nmov eax, [rbp+var_C]\nmov edx, eax\nlea rax, format; \"%d\"\nmov rsi, rax; format\nmov rdi, rcx; s\nmov eax, 0\ncall _sprintf\nadd [rbp+var_10], eax\nadd [rbp+var_C], 1\nloc_120B:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_4]\njle short loc_11D8\nmov eax, [rbp+var_4]\nsub eax, 1\nmov [rbp+var_8], eax\njmp short loc_1251\nloc_121E:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, unk_4040\nlea rcx, [rax+rdx]\nmov eax, [rbp+var_8]\nmov edx, eax\nlea rax, format; \"%d\"\nmov rsi, rax; format\nmov rdi, rcx; s\nmov eax, 0\ncall _sprintf\nadd [rbp+var_10], eax\nsub [rbp+var_8], 1\nloc_1251:\ncmp [rbp+var_8], 0\njg short loc_121E\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, unk_4040\nmov byte ptr [rax+rdx], 0\nlea rax, unk_4040\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11A9(const char *a1)\n{\n int v2; // [rsp+10h] [rbp-10h]\n int i; // [rsp+14h] [rbp-Ch]\n int j; // [rsp+18h] [rbp-8h]\n int v5; // [rsp+1Ch] [rbp-4h]\n\n v5 = strlen(a1);\n v2 = 0;\n for ( i = 1; i <= v5; ++i )\n v2 += sprintf(&byte_4040[v2], \"%d\", i);\n for ( j = v5 - 1; j > 0; --j )\n v2 += sprintf(&byte_4040[v2], \"%d\", j);\n byte_4040[v2] = 0;\n return byte_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11A9(const char *a1) {\n int v2;\n int i;\n int j;\n int v5;\n v5 = strlen(a1);\n v2 = 0;\n for (i = 1; i <= v5; ++i) v2 += sprintf(&byte_4040[v2], \"%d\", i);\n for (j = v5 - 1; j > 0; --j) v2 += sprintf(&byte_4040[v2], \"%d\", j);\n byte_4040[v2] = 0;\n return byte_4040;\n}", + "ida_pseudo_norm": "char *func0(const char *a1) {\n int v2;\n int i;\n int j;\n int v5;\n v5 = strlen(a1);\n v2 = 0;\n for (i = 1; i <= v5; ++i) v2 += sprintf(&res_1[v2], \"%d\", i);\n for (j = v5 - 1; j > 0; --j) v2 += sprintf(&res_1[v2], \"%d\", j);\n res_1[v2] = 0;\n return res_1;\n}" + }, + { + "index": 321, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* s) {\n static char res[1000];\n int l = strlen(s);\n int pos = 0;\n for (int i = 1; i <= l; i++) {\n pos += sprintf(&res[pos], \"%d\", i);\n }\n for (int i = l - 1; i > 0; i--) {\n pos += sprintf(&res[pos], \"%d\", i);\n }\n res[pos] = '\\0';\n return res;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"111111\"), \"12345654321\") == 0);\n\n assert(strcmp(func0(\"1111\"), \"1234321\") == 0);\n\n assert(strcmp(func0(\"13333122222\"), \"123456789101110987654321\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nlea -0x1(%rcx),%rbp\ntest %ebp,%ebp\njle 122b \nlea 0x1(%rbp),%r14d\nmov $0x1,%r12d\nmov $0x0,%ebx\nlea 0x2e98(%rip),%r13\nmovslq %ebx,%rdi\nadd %r13,%rdi\nmov %r12d,%r8d\nlea 0xe4c(%rip),%rcx\nmov $0xffffffffffffffff,%rdx\nmov $0x1,%esi\nmov $0x0,%eax\ncallq 1070 <__sprintf_chk@plt>\nadd %eax,%ebx\nadd $0x1,%r12d\ncmp %r12d,%r14d\njne 11a8 \nsub $0x1,%ebp\ntest %ebp,%ebp\njle 1214 \nlea 0x2e59(%rip),%r12\nmovslq %ebx,%rdi\nadd %r12,%rdi\nmov %ebp,%r8d\nlea 0xe0d(%rip),%rcx\nmov $0xffffffffffffffff,%rdx\nmov $0x1,%esi\nmov $0x0,%eax\ncallq 1070 <__sprintf_chk@plt>\nadd %eax,%ebx\nsub $0x1,%ebp\njne 11e7 \nlea 0x2e25(%rip),%rax\nmovslq %ebx,%rbx\nmovb $0x0,(%rax,%rbx,1)\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nmov $0x0,%ebx\njmp 11d9 \n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\ncall _strlen\ntest eax, eax\njle loc_1280\nmov rbp, rax\nlea r15d, [rax+1]\nmov r12d, 1\nmov ebx, 0\nlea r14, res_1\nlea r13, unk_2004\nloc_11E8:\nmovsxd rdi, ebx\nmov edx, 3E8h\ncmp rdi, rdx\ncmovnb rdx, rdi\nsub rdx, rdi\nadd rdi, r14\nmov r8d, r12d\nmov rcx, r13\nmov esi, 2\nmov eax, 0\ncall ___sprintf_chk\nadd ebx, eax\nadd r12d, 1\ncmp r15d, r12d\njnz short loc_11E8\nsub ebp, 1\ntest ebp, ebp\njle short loc_1263\nlea r13, res_1\nlea r12, unk_2004\nloc_1232:\nmovsxd rdi, ebx\nmov edx, 3E8h\ncmp rdi, rdx\ncmovnb rdx, rdi\nsub rdx, rdi\nadd rdi, r13\nmov r8d, ebp\nmov rcx, r12\nmov esi, 2\nmov eax, 0\ncall ___sprintf_chk\nadd ebx, eax\nsub ebp, 1\njnz short loc_1232\nloc_1263:\nlea rax, res_1\nmovsxd rbx, ebx\nmov byte ptr [rax+rbx], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1280:\nmov ebx, 0\njmp short loc_1263", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1)\n{\n int v1; // eax\n int v2; // ebp\n int v3; // r15d\n unsigned int v4; // r12d\n int v5; // ebx\n __int64 v6; // rdx\n int v7; // ebp\n __int64 v8; // rdx\n _BYTE *result; // rax\n\n v1 = strlen(a1);\n if ( v1 <= 0 )\n {\n v5 = 0;\n }\n else\n {\n v2 = v1;\n v3 = v1 + 1;\n v4 = 1;\n v5 = 0;\n do\n {\n v6 = 1000LL;\n if ( (unsigned __int64)v5 >= 0x3E8 )\n v6 = v5;\n v5 += __sprintf_chk(&res_1[v5], 2LL, v6 - v5, &unk_2004, v4++);\n }\n while ( v3 != v4 );\n v7 = v2 - 1;\n if ( v7 > 0 )\n {\n do\n {\n v8 = 1000LL;\n if ( (unsigned __int64)v5 >= 0x3E8 )\n v8 = v5;\n v5 += __sprintf_chk(&res_1[v5], 2LL, v8 - v5, &unk_2004, (unsigned int)v7--);\n }\n while ( v7 );\n }\n }\n result = res_1;\n res_1[v5] = 0;\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\ncall _strlen\ntest eax, eax\njle loc_1280\nmov rbp, rax\nlea r15d, [rax+1]\nmov r12d, 1\nmov ebx, 0\nlea r14, unk_4040\nlea r13, unk_2004\nloc_11E8:\nmovsxd rdi, ebx\nmov edx, 3E8h\ncmp rdi, rdx\ncmovnb rdx, rdi\nsub rdx, rdi\nadd rdi, r14\nmov r8d, r12d\nmov rcx, r13\nmov esi, 2\nmov eax, 0\ncall ___sprintf_chk\nadd ebx, eax\nadd r12d, 1\ncmp r15d, r12d\njnz short loc_11E8\nsub ebp, 1\ntest ebp, ebp\njle short loc_1263\nlea r13, unk_4040\nlea r12, unk_2004\nloc_1232:\nmovsxd rdi, ebx\nmov edx, 3E8h\ncmp rdi, rdx\ncmovnb rdx, rdi\nsub rdx, rdi\nadd rdi, r13\nmov r8d, ebp\nmov rcx, r12\nmov esi, 2\nmov eax, 0\ncall ___sprintf_chk\nadd ebx, eax\nsub ebp, 1\njnz short loc_1232\nloc_1263:\nlea rax, unk_4040\nmovsxd rbx, ebx\nmov byte ptr [rax+rbx], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1280:\nmov ebx, 0\njmp short loc_1263", + "ida_strip_pseudo": "_BYTE *__fastcall sub_11A9(const char *a1)\n{\n int v1; // eax\n int v2; // ebp\n int v3; // r15d\n unsigned int v4; // r12d\n int v5; // ebx\n __int64 v6; // rdx\n int v7; // ebp\n __int64 v8; // rdx\n _BYTE *result; // rax\n\n v1 = strlen(a1);\n if ( v1 <= 0 )\n {\n v5 = 0;\n }\n else\n {\n v2 = v1;\n v3 = v1 + 1;\n v4 = 1;\n v5 = 0;\n do\n {\n v6 = 1000LL;\n if ( (unsigned __int64)v5 >= 0x3E8 )\n v6 = v5;\n v5 += __sprintf_chk(&byte_4040[v5], 2LL, v6 - v5, &unk_2004, v4++);\n }\n while ( v3 != v4 );\n v7 = v2 - 1;\n if ( v7 > 0 )\n {\n do\n {\n v8 = 1000LL;\n if ( (unsigned __int64)v5 >= 0x3E8 )\n v8 = v5;\n v5 += __sprintf_chk(&byte_4040[v5], 2LL, v8 - v5, &unk_2004, (unsigned int)v7--);\n }\n while ( v7 );\n }\n }\n result = byte_4040;\n byte_4040[v5] = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_11A9(const char *a1) {\n int v1;\n int v2;\n int v3;\n unsigned int v4;\n int v5;\n long long v6;\n int v7;\n long long v8;\n uint8_t *result;\n v1 = strlen(a1);\n if (v1 <= 0) {\n v5 = 0;\n } else {\n v2 = v1;\n v3 = v1 + 1;\n v4 = 1;\n v5 = 0;\n do {\n v6 = 1000LL;\n if ((unsigned long long)v5 >= 1000) v6 = v5;\n v5 += __sprintf_chk(&byte_4040[v5], 2LL, v6 - v5, &unk_2004, v4++);\n } while (v3 != v4);\n v7 = v2 - 1;\n if (v7 > 0) {\n do {\n v8 = 1000LL;\n if ((unsigned long long)v5 >= 1000) v8 = v5;\n v5 += __sprintf_chk(&byte_4040[v5], 2LL, v8 - v5, &unk_2004,\n (unsigned int)v7--);\n } while (v7);\n }\n }\n result = byte_4040;\n byte_4040[v5] = 0;\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1) {\n int v1;\n int v2;\n int v3;\n unsigned int v4;\n int v5;\n long long v6;\n int v7;\n long long v8;\n uint8_t *result;\n v1 = strlen(a1);\n if (v1 <= 0) {\n v5 = 0;\n } else {\n v2 = v1;\n v3 = v1 + 1;\n v4 = 1;\n v5 = 0;\n do {\n v6 = 1000LL;\n if ((unsigned long long)v5 >= 1000) v6 = v5;\n v5 += __sprintf_chk(&res_1[v5], 2LL, v6 - v5, &unk_2004, v4++);\n } while (v3 != v4);\n v7 = v2 - 1;\n if (v7 > 0) {\n do {\n v8 = 1000LL;\n if ((unsigned long long)v5 >= 1000) v8 = v5;\n v5 += __sprintf_chk(&res_1[v5], 2LL, v8 - v5, &unk_2004,\n (unsigned int)v7--);\n } while (v7);\n }\n }\n result = res_1;\n res_1[v5] = 0;\n return result;\n}" + }, + { + "index": 321, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* s) {\n static char res[1000];\n int l = strlen(s);\n int pos = 0;\n for (int i = 1; i <= l; i++) {\n pos += sprintf(&res[pos], \"%d\", i);\n }\n for (int i = l - 1; i > 0; i--) {\n pos += sprintf(&res[pos], \"%d\", i);\n }\n res[pos] = '\\0';\n return res;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"111111\"), \"12345654321\") == 0);\n\n assert(strcmp(func0(\"1111\"), \"1234321\") == 0);\n\n assert(strcmp(func0(\"13333122222\"), \"123456789101110987654321\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\ncallq 1070 \nmov %rax,%rbp\ntest %eax,%eax\njle 1338 \nlea 0x1(%rax),%r15d\nmov $0x1,%r12d\nxor %ebx,%ebx\nlea 0x2d9b(%rip),%r13\nlea 0xd58(%rip),%r14\nnopl 0x0(%rax)\nmovslq %ebx,%rdi\nmov %r12d,%r8d\nmov %r14,%rcx\nmov $0xffffffffffffffff,%rdx\nadd %r13,%rdi\nmov $0x1,%esi\nxor %eax,%eax\nadd $0x1,%r12d\ncallq 1090 <__sprintf_chk@plt>\nadd %eax,%ebx\ncmp %r12d,%r15d\njne 12b0 \nsub $0x1,%ebp\ntest %ebp,%ebp\njle 1316 \nlea 0xd1c(%rip),%r12\nnopl 0x0(%rax,%rax,1)\nmovslq %ebx,%rdi\nmov %ebp,%r8d\nmov %r12,%rcx\nmov $0xffffffffffffffff,%rdx\nadd %r13,%rdi\nmov $0x1,%esi\nxor %eax,%eax\ncallq 1090 <__sprintf_chk@plt>\nadd %eax,%ebx\nsub $0x1,%ebp\njne 12f0 \nmovslq %ebx,%rbx\nlea 0x2d20(%rip),%rax\nmovb $0x0,0x0(%r13,%rbx,1)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl (%rax)\nxor %ebx,%ebx\nlea 0x2cff(%rip),%r13\njmp 12da \nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\ncall _strlen\ntest eax, eax\njle loc_1350\nmov r13, rax\nlea r14d, [rax+1]\nmov r15d, 1\nxor r12d, r12d\nlea rbx, res_1\nlea rbp, unk_2004\nnop dword ptr [rax]\nloc_12C0:\nmovsxd rdi, r12d\nmov edx, 3E8h\nmov r8d, r15d\nmov rcx, rbp\ncmp rdi, rdx\nmov esi, 2\ncmovnb rdx, rdi\nxor eax, eax\nadd r15d, 1\nsub rdx, rdi\nadd rdi, rbx\ncall ___sprintf_chk\nadd r12d, eax\ncmp r15d, r14d\njnz short loc_12C0\nsub r13d, 1\njz short loc_1330\nnop dword ptr [rax+00000000h]\nloc_1300:\nmovsxd rdi, r12d\nmov edx, 3E8h\nmov r8d, r13d\nmov rcx, rbp\ncmp rdi, rdx\nmov esi, 2\ncmovnb rdx, rdi\nxor eax, eax\nsub rdx, rdi\nadd rdi, rbx\ncall ___sprintf_chk\nadd r12d, eax\nsub r13d, 1\njnz short loc_1300\nloc_1330:\nmovsxd r12, r12d\nmov rax, rbx\nmov byte ptr [rbx+r12], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1350:\nxor r12d, r12d\nlea rbx, res_1\njmp short loc_1330", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1)\n{\n int v1; // eax\n int v2; // r13d\n int v3; // r14d\n unsigned int v4; // r15d\n int v5; // r12d\n __int64 v6; // rdx\n __int64 v7; // r8\n unsigned int i; // r13d\n __int64 v9; // rdx\n _BYTE *result; // rax\n\n v1 = strlen(a1);\n if ( v1 <= 0 )\n {\n v5 = 0;\n }\n else\n {\n v2 = v1;\n v3 = v1 + 1;\n v4 = 1;\n v5 = 0;\n do\n {\n v6 = 1000LL;\n v7 = v4;\n if ( (unsigned __int64)v5 >= 0x3E8 )\n v6 = v5;\n ++v4;\n v5 += __sprintf_chk(&res_1[v5], 2LL, v6 - v5, &unk_2004, v7);\n }\n while ( v4 != v3 );\n for ( i = v2 - 1; i; --i )\n {\n v9 = 1000LL;\n if ( (unsigned __int64)v5 >= 0x3E8 )\n v9 = v5;\n v5 += __sprintf_chk(&res_1[v5], 2LL, v9 - v5, &unk_2004, i);\n }\n }\n result = res_1;\n res_1[v5] = 0;\n return result;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\ncall _strlen\ntest eax, eax\njle loc_1350\nmov r13, rax\nlea r14d, [rax+1]\nmov r15d, 1\nxor r12d, r12d\nlea rbx, unk_4040\nlea rbp, unk_2004\nnop dword ptr [rax]\nloc_12C0:\nmovsxd rdi, r12d\nmov edx, 3E8h\nmov r8d, r15d\nmov rcx, rbp\ncmp rdi, rdx\nmov esi, 2\ncmovnb rdx, rdi\nxor eax, eax\nadd r15d, 1\nsub rdx, rdi\nadd rdi, rbx\ncall ___sprintf_chk\nadd r12d, eax\ncmp r15d, r14d\njnz short loc_12C0\nsub r13d, 1\njz short loc_1330\nnop dword ptr [rax+00000000h]\nloc_1300:\nmovsxd rdi, r12d\nmov edx, 3E8h\nmov r8d, r13d\nmov rcx, rbp\ncmp rdi, rdx\nmov esi, 2\ncmovnb rdx, rdi\nxor eax, eax\nsub rdx, rdi\nadd rdi, rbx\ncall ___sprintf_chk\nadd r12d, eax\nsub r13d, 1\njnz short loc_1300\nloc_1330:\nmovsxd r12, r12d\nmov rax, rbx\nmov byte ptr [rbx+r12], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1350:\nxor r12d, r12d\nlea rbx, unk_4040\njmp short loc_1330", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1280(const char *a1)\n{\n int v1; // eax\n int v2; // r13d\n int v3; // r14d\n unsigned int v4; // r15d\n int v5; // r12d\n __int64 v6; // rdx\n __int64 v7; // r8\n unsigned int i; // r13d\n __int64 v9; // rdx\n _BYTE *result; // rax\n\n v1 = strlen(a1);\n if ( v1 <= 0 )\n {\n v5 = 0;\n }\n else\n {\n v2 = v1;\n v3 = v1 + 1;\n v4 = 1;\n v5 = 0;\n do\n {\n v6 = 1000LL;\n v7 = v4;\n if ( (unsigned __int64)v5 >= 0x3E8 )\n v6 = v5;\n ++v4;\n v5 += __sprintf_chk(&byte_4040[v5], 2LL, v6 - v5, &unk_2004, v7);\n }\n while ( v4 != v3 );\n for ( i = v2 - 1; i; --i )\n {\n v9 = 1000LL;\n if ( (unsigned __int64)v5 >= 0x3E8 )\n v9 = v5;\n v5 += __sprintf_chk(&byte_4040[v5], 2LL, v9 - v5, &unk_2004, i);\n }\n }\n result = byte_4040;\n byte_4040[v5] = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1280(const char *a1) {\n int v1;\n int v2;\n int v3;\n unsigned int v4;\n int v5;\n long long v6;\n long long v7;\n unsigned int i;\n long long v9;\n uint8_t *result;\n v1 = strlen(a1);\n if (v1 <= 0) {\n v5 = 0;\n } else {\n v2 = v1;\n v3 = v1 + 1;\n v4 = 1;\n v5 = 0;\n do {\n v6 = 1000LL;\n v7 = v4;\n if ((unsigned long long)v5 >= 1000) v6 = v5;\n ++v4;\n v5 += __sprintf_chk(&byte_4040[v5], 2LL, v6 - v5, &unk_2004, v7);\n } while (v4 != v3);\n for (i = v2 - 1; i; --i) {\n v9 = 1000LL;\n if ((unsigned long long)v5 >= 1000) v9 = v5;\n v5 += __sprintf_chk(&byte_4040[v5], 2LL, v9 - v5, &unk_2004, i);\n }\n }\n result = byte_4040;\n byte_4040[v5] = 0;\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1) {\n int v1;\n int v2;\n int v3;\n unsigned int v4;\n int v5;\n long long v6;\n long long v7;\n unsigned int i;\n long long v9;\n uint8_t *result;\n v1 = strlen(a1);\n if (v1 <= 0) {\n v5 = 0;\n } else {\n v2 = v1;\n v3 = v1 + 1;\n v4 = 1;\n v5 = 0;\n do {\n v6 = 1000LL;\n v7 = v4;\n if ((unsigned long long)v5 >= 1000) v6 = v5;\n ++v4;\n v5 += __sprintf_chk(&res_1[v5], 2LL, v6 - v5, &unk_2004, v7);\n } while (v4 != v3);\n for (i = v2 - 1; i; --i) {\n v9 = 1000LL;\n if ((unsigned long long)v5 >= 1000) v9 = v5;\n v5 += __sprintf_chk(&res_1[v5], 2LL, v9 - v5, &unk_2004, i);\n }\n }\n result = res_1;\n res_1[v5] = 0;\n return result;\n}" + }, + { + "index": 321, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* s) {\n static char res[1000];\n int l = strlen(s);\n int pos = 0;\n for (int i = 1; i <= l; i++) {\n pos += sprintf(&res[pos], \"%d\", i);\n }\n for (int i = l - 1; i > 0; i--) {\n pos += sprintf(&res[pos], \"%d\", i);\n }\n res[pos] = '\\0';\n return res;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"111111\"), \"12345654321\") == 0);\n\n assert(strcmp(func0(\"1111\"), \"1234321\") == 0);\n\n assert(strcmp(func0(\"13333122222\"), \"123456789101110987654321\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\ncallq 1070 \nmov %rax,%rbp\ntest %eax,%eax\njle 1338 \nlea 0x1(%rax),%r15d\nmov $0x1,%r12d\nxor %ebx,%ebx\nlea 0x2d9b(%rip),%r13\nlea 0xd58(%rip),%r14\nnopl 0x0(%rax)\nmovslq %ebx,%rdi\nmov %r12d,%r8d\nmov %r14,%rcx\nmov $0xffffffffffffffff,%rdx\nadd %r13,%rdi\nmov $0x1,%esi\nxor %eax,%eax\nadd $0x1,%r12d\ncallq 1090 <__sprintf_chk@plt>\nadd %eax,%ebx\ncmp %r12d,%r15d\njne 12b0 \nsub $0x1,%ebp\ntest %ebp,%ebp\njle 1316 \nlea 0xd1c(%rip),%r12\nnopl 0x0(%rax,%rax,1)\nmovslq %ebx,%rdi\nmov %ebp,%r8d\nmov %r12,%rcx\nmov $0xffffffffffffffff,%rdx\nadd %r13,%rdi\nmov $0x1,%esi\nxor %eax,%eax\ncallq 1090 <__sprintf_chk@plt>\nadd %eax,%ebx\nsub $0x1,%ebp\njne 12f0 \nmovslq %ebx,%rbx\nlea 0x2d20(%rip),%rax\nmovb $0x0,0x0(%r13,%rbx,1)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl (%rax)\nxor %ebx,%ebx\nlea 0x2cff(%rip),%r13\njmp 12da \nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\ncall _strlen\ntest eax, eax\njle loc_1350\nmov r13, rax\nlea r14d, [rax+1]\nmov r15d, 1\nxor r12d, r12d\nlea rbx, res_1\nlea rbp, unk_2004\nnop dword ptr [rax]\nloc_12C0:\nmovsxd rdi, r12d\nmov edx, 3E8h\nmov r8d, r15d\nmov rcx, rbp\ncmp rdi, rdx\nmov esi, 2\ncmovnb rdx, rdi\nxor eax, eax\nadd r15d, 1\nsub rdx, rdi\nadd rdi, rbx\ncall ___sprintf_chk\nadd r12d, eax\ncmp r14d, r15d\njnz short loc_12C0\nsub r13d, 1\njz short loc_1330\nnop dword ptr [rax+00000000h]\nloc_1300:\nmovsxd rdi, r12d\nmov edx, 3E8h\nmov r8d, r13d\nmov rcx, rbp\ncmp rdi, rdx\nmov esi, 2\ncmovnb rdx, rdi\nxor eax, eax\nsub rdx, rdi\nadd rdi, rbx\ncall ___sprintf_chk\nadd r12d, eax\nsub r13d, 1\njnz short loc_1300\nloc_1330:\nmovsxd r12, r12d\nmov rax, rbx\nmov byte ptr [rbx+r12], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1350:\nxor r12d, r12d\nlea rbx, res_1\njmp short loc_1330", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1)\n{\n int v1; // eax\n int v2; // r13d\n int v3; // r14d\n unsigned int v4; // r15d\n int v5; // r12d\n __int64 v6; // rdx\n __int64 v7; // r8\n unsigned int i; // r13d\n __int64 v9; // rdx\n _BYTE *result; // rax\n\n v1 = strlen(a1);\n if ( v1 <= 0 )\n {\n v5 = 0;\n }\n else\n {\n v2 = v1;\n v3 = v1 + 1;\n v4 = 1;\n v5 = 0;\n do\n {\n v6 = 1000LL;\n v7 = v4;\n if ( (unsigned __int64)v5 >= 0x3E8 )\n v6 = v5;\n ++v4;\n v5 += __sprintf_chk(&res_1[v5], 2LL, v6 - v5, &unk_2004, v7);\n }\n while ( v3 != v4 );\n for ( i = v2 - 1; i; --i )\n {\n v9 = 1000LL;\n if ( (unsigned __int64)v5 >= 0x3E8 )\n v9 = v5;\n v5 += __sprintf_chk(&res_1[v5], 2LL, v9 - v5, &unk_2004, i);\n }\n }\n result = res_1;\n res_1[v5] = 0;\n return result;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\ncall _strlen\ntest eax, eax\njle loc_1350\nmov r13, rax\nlea r14d, [rax+1]\nmov r15d, 1\nxor r12d, r12d\nlea rbx, unk_4040\nlea rbp, unk_2004\nnop dword ptr [rax]\nloc_12C0:\nmovsxd rdi, r12d\nmov edx, 3E8h\nmov r8d, r15d\nmov rcx, rbp\ncmp rdi, rdx\nmov esi, 2\ncmovnb rdx, rdi\nxor eax, eax\nadd r15d, 1\nsub rdx, rdi\nadd rdi, rbx\ncall ___sprintf_chk\nadd r12d, eax\ncmp r14d, r15d\njnz short loc_12C0\nsub r13d, 1\njz short loc_1330\nnop dword ptr [rax+00000000h]\nloc_1300:\nmovsxd rdi, r12d\nmov edx, 3E8h\nmov r8d, r13d\nmov rcx, rbp\ncmp rdi, rdx\nmov esi, 2\ncmovnb rdx, rdi\nxor eax, eax\nsub rdx, rdi\nadd rdi, rbx\ncall ___sprintf_chk\nadd r12d, eax\nsub r13d, 1\njnz short loc_1300\nloc_1330:\nmovsxd r12, r12d\nmov rax, rbx\nmov byte ptr [rbx+r12], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1350:\nxor r12d, r12d\nlea rbx, unk_4040\njmp short loc_1330", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1280(const char *a1)\n{\n int v1; // eax\n int v2; // r13d\n int v3; // r14d\n unsigned int v4; // r15d\n int v5; // r12d\n __int64 v6; // rdx\n __int64 v7; // r8\n unsigned int i; // r13d\n __int64 v9; // rdx\n _BYTE *result; // rax\n\n v1 = strlen(a1);\n if ( v1 <= 0 )\n {\n v5 = 0;\n }\n else\n {\n v2 = v1;\n v3 = v1 + 1;\n v4 = 1;\n v5 = 0;\n do\n {\n v6 = 1000LL;\n v7 = v4;\n if ( (unsigned __int64)v5 >= 0x3E8 )\n v6 = v5;\n ++v4;\n v5 += __sprintf_chk(&byte_4040[v5], 2LL, v6 - v5, &unk_2004, v7);\n }\n while ( v3 != v4 );\n for ( i = v2 - 1; i; --i )\n {\n v9 = 1000LL;\n if ( (unsigned __int64)v5 >= 0x3E8 )\n v9 = v5;\n v5 += __sprintf_chk(&byte_4040[v5], 2LL, v9 - v5, &unk_2004, i);\n }\n }\n result = byte_4040;\n byte_4040[v5] = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1280(const char *a1) {\n int v1;\n int v2;\n int v3;\n unsigned int v4;\n int v5;\n long long v6;\n long long v7;\n unsigned int i;\n long long v9;\n uint8_t *result;\n v1 = strlen(a1);\n if (v1 <= 0) {\n v5 = 0;\n } else {\n v2 = v1;\n v3 = v1 + 1;\n v4 = 1;\n v5 = 0;\n do {\n v6 = 1000LL;\n v7 = v4;\n if ((unsigned long long)v5 >= 1000) v6 = v5;\n ++v4;\n v5 += __sprintf_chk(&byte_4040[v5], 2LL, v6 - v5, &unk_2004, v7);\n } while (v3 != v4);\n for (i = v2 - 1; i; --i) {\n v9 = 1000LL;\n if ((unsigned long long)v5 >= 1000) v9 = v5;\n v5 += __sprintf_chk(&byte_4040[v5], 2LL, v9 - v5, &unk_2004, i);\n }\n }\n result = byte_4040;\n byte_4040[v5] = 0;\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1) {\n int v1;\n int v2;\n int v3;\n unsigned int v4;\n int v5;\n long long v6;\n long long v7;\n unsigned int i;\n long long v9;\n uint8_t *result;\n v1 = strlen(a1);\n if (v1 <= 0) {\n v5 = 0;\n } else {\n v2 = v1;\n v3 = v1 + 1;\n v4 = 1;\n v5 = 0;\n do {\n v6 = 1000LL;\n v7 = v4;\n if ((unsigned long long)v5 >= 1000) v6 = v5;\n ++v4;\n v5 += __sprintf_chk(&res_1[v5], 2LL, v6 - v5, &unk_2004, v7);\n } while (v3 != v4);\n for (i = v2 - 1; i; --i) {\n v9 = 1000LL;\n if ((unsigned long long)v5 >= 1000) v9 = v5;\n v5 += __sprintf_chk(&res_1[v5], 2LL, v9 - v5, &unk_2004, i);\n }\n }\n result = res_1;\n res_1[v5] = 0;\n return result;\n}" + }, + { + "index": 322, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int list1[], int size, int* resultSize) {\n int min_val = INT_MAX;\n static int min_positions[100];\n int count = 0;\n for (int i = 0; i < size; i++) {\n if (list1[i] < min_val) {\n min_val = list1[i];\n }\n }\n for (int i = 0; i < size; i++) {\n if (list1[i] == min_val) {\n min_positions[count++] = i;\n }\n }\n *resultSize = count;\n return min_positions;\n}", + "test": "int main() {\n\n int resultSize;\n\n int* result;\n\n int list1[] = {12,33,23,10,67,89,45,667,23,12,11,10,54};\n\n int list2[] = {1,2,2,2,4,4,4,5,5,5,5};\n\n int list3[] = {2,1,5,6,8,3,4,9,10,11,8,12};\n\n\n\n result = func0(list1, sizeof(list1)/sizeof(list1[0]), &resultSize);\n\n assert(resultSize == 2 && result[0] == 3 && result[1] == 11);\n\n\n\n result = func0(list2, sizeof(list2)/sizeof(list2[0]), &resultSize);\n\n assert(resultSize == 1 && result[0] == 0);\n\n\n\n result = func0(list3, sizeof(list3)/sizeof(list3[0]), &resultSize);\n\n assert(resultSize == 1 && result[0] == 1);\n\n\n\n printf(\"All tests passed!\\n\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmovl $0x7fffffff,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11eb \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x10(%rbp)\njle 11e7 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x10(%rbp)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11b3 \nmovl $0x0,-0x4(%rbp)\njmp 123b \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x10(%rbp)\njne 1237 \nmov -0xc(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0xc(%rbp)\ncltq\nlea 0x0(,%rax,4),%rcx\nlea 0x2e0f(%rip),%rdx\nmov -0x4(%rbp),%eax\nmov %eax,(%rcx,%rdx,1)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11fc \nmov -0x28(%rbp),%rax\nmov -0xc(%rbp),%edx\nmov %edx,(%rax)\nlea 0x2ded(%rip),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_10], 7FFFFFFFh\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_11EB\nloc_11B3:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_10], eax\njle short loc_11E7\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_10], eax\nloc_11E7:\nadd [rbp+var_8], 1\nloc_11EB:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_11B3\nmov [rbp+var_4], 0\njmp short loc_123B\nloc_11FC:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_10], eax\njnz short loc_1237\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\ncdqe\nlea rcx, ds:0[rax*4]\nlea rdx, min_positions_1\nmov eax, [rbp+var_4]\nmov [rcx+rdx], eax\nloc_1237:\nadd [rbp+var_4], 1\nloc_123B:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11FC\nmov rax, [rbp+var_28]\nmov edx, [rbp+var_C]\nmov [rax], edx\nlea rax, min_positions_1\npop rbp\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, _DWORD *a3)\n{\n int v3; // eax\n int v5; // [rsp+18h] [rbp-10h]\n int v6; // [rsp+1Ch] [rbp-Ch]\n int i; // [rsp+20h] [rbp-8h]\n int j; // [rsp+24h] [rbp-4h]\n\n v5 = 0x7FFFFFFF;\n v6 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( v5 > *(_DWORD *)(4LL * i + a1) )\n v5 = *(_DWORD *)(4LL * i + a1);\n }\n for ( j = 0; j < a2; ++j )\n {\n if ( v5 == *(_DWORD *)(4LL * j + a1) )\n {\n v3 = v6++;\n min_positions_1[v3] = j;\n }\n }\n *a3 = v6;\n return min_positions_1;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_10], 7FFFFFFFh\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_11EB\nloc_11B3:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_10], eax\njle short loc_11E7\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_10], eax\nloc_11E7:\nadd [rbp+var_8], 1\nloc_11EB:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_11B3\nmov [rbp+var_4], 0\njmp short loc_123B\nloc_11FC:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_10], eax\njnz short loc_1237\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\ncdqe\nlea rcx, ds:0[rax*4]\nlea rdx, unk_4040\nmov eax, [rbp+var_4]\nmov [rcx+rdx], eax\nloc_1237:\nadd [rbp+var_4], 1\nloc_123B:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11FC\nmov rax, [rbp+var_28]\nmov edx, [rbp+var_C]\nmov [rax], edx\nlea rax, unk_4040\npop rbp\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1189(__int64 a1, int a2, _DWORD *a3)\n{\n int v3; // eax\n int v5; // [rsp+18h] [rbp-10h]\n int v6; // [rsp+1Ch] [rbp-Ch]\n int i; // [rsp+20h] [rbp-8h]\n int j; // [rsp+24h] [rbp-4h]\n\n v5 = 0x7FFFFFFF;\n v6 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( v5 > *(_DWORD *)(4LL * i + a1) )\n v5 = *(_DWORD *)(4LL * i + a1);\n }\n for ( j = 0; j < a2; ++j )\n {\n if ( v5 == *(_DWORD *)(4LL * j + a1) )\n {\n v3 = v6++;\n dword_4040[v3] = j;\n }\n }\n *a3 = v6;\n return dword_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1189(long long a1, int a2, uint32_t *a3) {\n int v3;\n int v5;\n int v6;\n int i;\n int j;\n v5 = 2147483647;\n v6 = 0;\n for (i = 0; i < a2; ++i) {\n if (v5 > *(uint32_t *)(4LL * i + a1)) v5 = *(uint32_t *)(4LL * i + a1);\n }\n for (j = 0; j < a2; ++j) {\n if (v5 == *(uint32_t *)(4LL * j + a1)) {\n v3 = v6++;\n dword_4040[v3] = j;\n }\n }\n *a3 = v6;\n return dword_4040;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, uint32_t *a3) {\n int v3;\n int v5;\n int v6;\n int i;\n int j;\n v5 = 2147483647;\n v6 = 0;\n for (i = 0; i < a2; ++i) {\n if (v5 > *(uint32_t *)(4LL * i + a1)) v5 = *(uint32_t *)(4LL * i + a1);\n }\n for (j = 0; j < a2; ++j) {\n if (v5 == *(uint32_t *)(4LL * j + a1)) {\n v3 = v6++;\n min_positions_1[v3] = j;\n }\n }\n *a3 = v6;\n return min_positions_1;\n}" + }, + { + "index": 322, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int list1[], int size, int* resultSize) {\n int min_val = INT_MAX;\n static int min_positions[100];\n int count = 0;\n for (int i = 0; i < size; i++) {\n if (list1[i] < min_val) {\n min_val = list1[i];\n }\n }\n for (int i = 0; i < size; i++) {\n if (list1[i] == min_val) {\n min_positions[count++] = i;\n }\n }\n *resultSize = count;\n return min_positions;\n}", + "test": "int main() {\n\n int resultSize;\n\n int* result;\n\n int list1[] = {12,33,23,10,67,89,45,667,23,12,11,10,54};\n\n int list2[] = {1,2,2,2,4,4,4,5,5,5,5};\n\n int list3[] = {2,1,5,6,8,3,4,9,10,11,8,12};\n\n\n\n result = func0(list1, sizeof(list1)/sizeof(list1[0]), &resultSize);\n\n assert(resultSize == 2 && result[0] == 3 && result[1] == 11);\n\n\n\n result = func0(list2, sizeof(list2)/sizeof(list2[0]), &resultSize);\n\n assert(resultSize == 1 && result[0] == 0);\n\n\n\n result = func0(list3, sizeof(list3)/sizeof(list3[0]), &resultSize);\n\n assert(resultSize == 1 && result[0] == 1);\n\n\n\n printf(\"All tests passed!\\n\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11e4 \nmov %rdi,%rax\nlea -0x1(%rsi),%r9d\nlea 0x4(%rdi,%r9,4),%r8\nmov $0x7fffffff,%ecx\nmov (%rax),%esi\ncmp %esi,%ecx\ncmovg %esi,%ecx\nadd $0x4,%rax\ncmp %r8,%rax\njne 11a2 \nmov $0x0,%eax\nmov $0x0,%r8d\nlea 0x2e7c(%rip),%r10\njmp 11d2 \nlea 0x1(%rax),%rsi\ncmp %r9,%rax\nje 11ea \nmov %rsi,%rax\ncmp (%rdi,%rax,4),%ecx\njne 11c6 \nmovslq %r8d,%rsi\nmov %eax,(%r10,%rsi,4)\nlea 0x1(%r8),%r8d\njmp 11c6 \nmov $0x0,%r8d\nmov %r8d,(%rdx)\nlea 0x2e4c(%rip),%rax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov r8, rdi\ntest esi, esi\njle short loc_11E1\nmov rax, rdi\nmovsxd rsi, esi\nlea r9, [rdi+rsi*4]\nmov ecx, 7FFFFFFFh\nloc_11A3:\nmov edi, [rax]\ncmp ecx, edi\ncmovg ecx, edi\nadd rax, 4\ncmp rax, r9\njnz short loc_11A3\nmov eax, 0\nmov edi, 0\nlea r10, min_positions_1\njmp short loc_11CF\nloc_11C6:\nadd rax, 1\ncmp rax, rsi\njz short loc_11E6\nloc_11CF:\ncmp ecx, [r8+rax*4]\njnz short loc_11C6\nmovsxd r9, edi\nmov [r10+r9*4], eax\nlea edi, [rdi+1]\njmp short loc_11C6\nloc_11E1:\nmov edi, 0\nloc_11E6:\nmov [rdx], edi\nlea rax, min_positions_1\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2, _DWORD *a3)\n{\n int *v4; // rax\n int v5; // ecx\n __int64 v6; // rax\n int v7; // edi\n\n if ( a2 <= 0 )\n {\n v7 = 0;\n }\n else\n {\n v4 = a1;\n v5 = 0x7FFFFFFF;\n do\n {\n if ( v5 > *v4 )\n v5 = *v4;\n ++v4;\n }\n while ( v4 != &a1[a2] );\n v6 = 0LL;\n v7 = 0;\n do\n {\n if ( v5 == a1[v6] )\n min_positions_1[v7++] = v6;\n ++v6;\n }\n while ( v6 != a2 );\n }\n *a3 = v7;\n return min_positions_1;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\nmov r8, rdi\ntest esi, esi\njle short loc_11E1\nmov rax, rdi\nmovsxd rsi, esi\nlea r9, [rdi+rsi*4]\nmov ecx, 7FFFFFFFh\nloc_11A3:\nmov edi, [rax]\ncmp ecx, edi\ncmovg ecx, edi\nadd rax, 4\ncmp rax, r9\njnz short loc_11A3\nmov eax, 0\nmov edi, 0\nlea r10, unk_4040\njmp short loc_11CF\nloc_11C6:\nadd rax, 1\ncmp rax, rsi\njz short loc_11E6\nloc_11CF:\ncmp ecx, [r8+rax*4]\njnz short loc_11C6\nmovsxd r9, edi\nmov [r10+r9*4], eax\nlea edi, [rdi+1]\njmp short loc_11C6\nloc_11E1:\nmov edi, 0\nloc_11E6:\nmov [rdx], edi\nlea rax, unk_4040\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1189(int *a1, int a2, _DWORD *a3)\n{\n int *v4; // rax\n int v5; // ecx\n __int64 v6; // rax\n int v7; // edi\n\n if ( a2 <= 0 )\n {\n v7 = 0;\n }\n else\n {\n v4 = a1;\n v5 = 0x7FFFFFFF;\n do\n {\n if ( v5 > *v4 )\n v5 = *v4;\n ++v4;\n }\n while ( v4 != &a1[a2] );\n v6 = 0LL;\n v7 = 0;\n do\n {\n if ( v5 == a1[v6] )\n dword_4040[v7++] = v6;\n ++v6;\n }\n while ( v6 != a2 );\n }\n *a3 = v7;\n return dword_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1189(int *a1, int a2, uint32_t *a3) {\n int *v4;\n int v5;\n long long v6;\n int v7;\n if (a2 <= 0) {\n v7 = 0;\n } else {\n v4 = a1;\n v5 = 2147483647;\n do {\n if (v5 > *v4) v5 = *v4;\n ++v4;\n } while (v4 != &a1[a2]);\n v6 = 0LL;\n v7 = 0;\n do {\n if (v5 == a1[v6]) dword_4040[v7++] = v6;\n ++v6;\n } while (v6 != a2);\n }\n *a3 = v7;\n return dword_4040;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2, uint32_t *a3) {\n int *v4;\n int v5;\n long long v6;\n int v7;\n if (a2 <= 0) {\n v7 = 0;\n } else {\n v4 = a1;\n v5 = 2147483647;\n do {\n if (v5 > *v4) v5 = *v4;\n ++v4;\n } while (v4 != &a1[a2]);\n v6 = 0LL;\n v7 = 0;\n do {\n if (v5 == a1[v6]) min_positions_1[v7++] = v6;\n ++v6;\n } while (v6 != a2);\n }\n *a3 = v7;\n return min_positions_1;\n}" + }, + { + "index": 322, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int list1[], int size, int* resultSize) {\n int min_val = INT_MAX;\n static int min_positions[100];\n int count = 0;\n for (int i = 0; i < size; i++) {\n if (list1[i] < min_val) {\n min_val = list1[i];\n }\n }\n for (int i = 0; i < size; i++) {\n if (list1[i] == min_val) {\n min_positions[count++] = i;\n }\n }\n *resultSize = count;\n return min_positions;\n}", + "test": "int main() {\n\n int resultSize;\n\n int* result;\n\n int list1[] = {12,33,23,10,67,89,45,667,23,12,11,10,54};\n\n int list2[] = {1,2,2,2,4,4,4,5,5,5,5};\n\n int list3[] = {2,1,5,6,8,3,4,9,10,11,8,12};\n\n\n\n result = func0(list1, sizeof(list1)/sizeof(list1[0]), &resultSize);\n\n assert(resultSize == 2 && result[0] == 3 && result[1] == 11);\n\n\n\n result = func0(list2, sizeof(list2)/sizeof(list2[0]), &resultSize);\n\n assert(resultSize == 1 && result[0] == 0);\n\n\n\n result = func0(list3, sizeof(list3)/sizeof(list3[0]), &resultSize);\n\n assert(resultSize == 1 && result[0] == 1);\n\n\n\n printf(\"All tests passed!\\n\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1520 \nlea -0x1(%rsi),%r9d\nmov %rdi,%rax\nmov $0x7fffffff,%ecx\nlea 0x4(%rdi,%r9,4),%r8\nnopl 0x0(%rax)\nmov (%rax),%esi\ncmp %esi,%ecx\ncmovg %esi,%ecx\nadd $0x4,%rax\ncmp %r8,%rax\njne 14d0 \nxor %eax,%eax\nxor %r8d,%r8d\nlea 0x2b54(%rip),%r10\njmp 14f3 \nxchg %ax,%ax\nmov %rsi,%rax\ncmp (%rdi,%rax,4),%ecx\njne 1503 \nmovslq %r8d,%rsi\nadd $0x1,%r8d\nmov %eax,(%r10,%rsi,4)\nlea 0x1(%rax),%rsi\ncmp %rax,%r9\njne 14f0 \nmov %r8d,(%rdx)\nlea 0x2b2a(%rip),%rax\nretq\nnopw 0x0(%rax,%rax,1)\nxor %r8d,%r8d\nlea 0x2b16(%rip),%rax\nmov %r8d,(%rdx)\nretq\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_13B0\nmovsxd rsi, esi\nmov rax, rdi\nmov ecx, 7FFFFFFFh\nlea r9, [rdi+rsi*4]\ntest sil, 1\njz short loc_1360\nmov eax, [rdi]\ncmp ecx, eax\ncmovg ecx, eax\nlea rax, [rdi+4]\ncmp rax, r9\njz short loc_137E\nnop dword ptr [rax]\nloc_1360:\nmov r8d, [rax]\ncmp ecx, r8d\ncmovg ecx, r8d\nmov r8d, [rax+4]\ncmp ecx, r8d\ncmovg ecx, r8d\nadd rax, 8\ncmp rax, r9\njnz short loc_1360\nloc_137E:\nxor eax, eax\nxor r8d, r8d\nlea r10, min_positions_1\nnop word ptr [rax+rax+00h]\nloc_1390:\ncmp ecx, [rdi+rax*4]\njnz short loc_13A0\nmovsxd r9, r8d\nadd r8d, 1\nmov [r10+r9*4], eax\nloc_13A0:\nadd rax, 1\ncmp rax, rsi\njnz short loc_1390\nmov [rdx], r8d\nmov rax, r10\nretn\nloc_13B0:\nxor r8d, r8d\nlea r10, min_positions_1\nmov [rdx], r8d\nmov rax, r10\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2, _DWORD *a3)\n{\n int *v3; // rax\n int v4; // ecx\n int *v5; // r9\n __int64 v6; // rax\n int v7; // r8d\n __int64 v8; // r9\n\n if ( a2 <= 0 )\n {\n *a3 = 0;\n return min_positions_1;\n }\n else\n {\n v3 = a1;\n v4 = 0x7FFFFFFF;\n v5 = &a1[a2];\n if ( (a2 & 1) == 0 )\n goto LABEL_19;\n if ( *a1 != 0x7FFFFFFF )\n v4 = *a1;\n v3 = a1 + 1;\n if ( a1 + 1 != v5 )\n {\nLABEL_19:\n do\n {\n if ( v4 > *v3 )\n v4 = *v3;\n if ( v4 > v3[1] )\n v4 = v3[1];\n v3 += 2;\n }\n while ( v3 != v5 );\n }\n v6 = 0LL;\n v7 = 0;\n do\n {\n if ( v4 == a1[v6] )\n {\n v8 = v7++;\n min_positions_1[v8] = v6;\n }\n ++v6;\n }\n while ( v6 != a2 );\n *a3 = v7;\n return min_positions_1;\n }\n}", + "ida_strip_asm": "sub_1330:\nendbr64\ntest esi, esi\njle short loc_13B0\nmovsxd rsi, esi\nmov rax, rdi\nmov ecx, 7FFFFFFFh\nlea r9, [rdi+rsi*4]\ntest sil, 1\njz short loc_1360\nmov eax, [rdi]\ncmp ecx, eax\ncmovg ecx, eax\nlea rax, [rdi+4]\ncmp rax, r9\njz short loc_137E\nnop dword ptr [rax]\nloc_1360:\nmov r8d, [rax]\ncmp ecx, r8d\ncmovg ecx, r8d\nmov r8d, [rax+4]\ncmp ecx, r8d\ncmovg ecx, r8d\nadd rax, 8\ncmp rax, r9\njnz short loc_1360\nloc_137E:\nxor eax, eax\nxor r8d, r8d\nlea r10, unk_4040\nnop word ptr [rax+rax+00h]\nloc_1390:\ncmp ecx, [rdi+rax*4]\njnz short loc_13A0\nmovsxd r9, r8d\nadd r8d, 1\nmov [r10+r9*4], eax\nloc_13A0:\nadd rax, 1\ncmp rax, rsi\njnz short loc_1390\nmov [rdx], r8d\nmov rax, r10\nretn\nloc_13B0:\nxor r8d, r8d\nlea r10, unk_4040\nmov [rdx], r8d\nmov rax, r10\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1330(int *a1, int a2, _DWORD *a3)\n{\n int *v3; // rax\n int v4; // ecx\n int *v5; // r9\n __int64 v6; // rax\n int v7; // r8d\n __int64 v8; // r9\n\n if ( a2 <= 0 )\n {\n *a3 = 0;\n return dword_4040;\n }\n else\n {\n v3 = a1;\n v4 = 0x7FFFFFFF;\n v5 = &a1[a2];\n if ( (a2 & 1) == 0 )\n goto LABEL_19;\n if ( *a1 != 0x7FFFFFFF )\n v4 = *a1;\n v3 = a1 + 1;\n if ( a1 + 1 != v5 )\n {\nLABEL_19:\n do\n {\n if ( v4 > *v3 )\n v4 = *v3;\n if ( v4 > v3[1] )\n v4 = v3[1];\n v3 += 2;\n }\n while ( v3 != v5 );\n }\n v6 = 0LL;\n v7 = 0;\n do\n {\n if ( v4 == a1[v6] )\n {\n v8 = v7++;\n dword_4040[v8] = v6;\n }\n ++v6;\n }\n while ( v6 != a2 );\n *a3 = v7;\n return dword_4040;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1330(int *a1, int a2, uint32_t *a3) {\n int *v3;\n int v4;\n int *v5;\n long long v6;\n int v7;\n long long v8;\n if (a2 <= 0) {\n *a3 = 0;\n return dword_4040;\n } else {\n v3 = a1;\n v4 = 2147483647;\n v5 = &a1[a2];\n if ((a2 & 1) == 0) goto LABEL_19;\n if (*a1 != 2147483647) v4 = *a1;\n v3 = a1 + 1;\n if (a1 + 1 != v5) {\n LABEL_19:\n do {\n if (v4 > *v3) v4 = *v3;\n if (v4 > v3[1]) v4 = v3[1];\n v3 += 2;\n } while (v3 != v5);\n }\n v6 = 0LL;\n v7 = 0;\n do {\n if (v4 == a1[v6]) {\n v8 = v7++;\n dword_4040[v8] = v6;\n }\n ++v6;\n } while (v6 != a2);\n *a3 = v7;\n return dword_4040;\n }\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2, uint32_t *a3) {\n int *v3;\n int v4;\n int *v5;\n long long v6;\n int v7;\n long long v8;\n if (a2 <= 0) {\n *a3 = 0;\n return min_positions_1;\n } else {\n v3 = a1;\n v4 = 2147483647;\n v5 = &a1[a2];\n if ((a2 & 1) == 0) goto LABEL_19;\n if (*a1 != 2147483647) v4 = *a1;\n v3 = a1 + 1;\n if (a1 + 1 != v5) {\n LABEL_19:\n do {\n if (v4 > *v3) v4 = *v3;\n if (v4 > v3[1]) v4 = v3[1];\n v3 += 2;\n } while (v3 != v5);\n }\n v6 = 0LL;\n v7 = 0;\n do {\n if (v4 == a1[v6]) {\n v8 = v7++;\n min_positions_1[v8] = v6;\n }\n ++v6;\n } while (v6 != a2);\n *a3 = v7;\n return min_positions_1;\n }\n}" + }, + { + "index": 323, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\nvoid right_rotate(int arr[], int n, int out_of_place, int cur) {\n\n int temp = arr[cur];\n\n for (int i = cur; i > out_of_place; --i) {\n\n arr[i] = arr[i - 1];\n\n }\n\n arr[out_of_place] = temp;\n\n}\n\n\n\n", + "func": "void func0(int arr[], int n) {\n int out_of_place = -1;\n for (int index = 0; index < n; ++index) {\n if (out_of_place >= 0) {\n if ((arr[index] >= 0 && arr[out_of_place] < 0) ||\n (arr[index] < 0 && arr[out_of_place] >= 0)) {\n right_rotate(arr, n, out_of_place, index);\n if (index - out_of_place > 2) {\n out_of_place += 2;\n } else {\n out_of_place = -1;\n }\n }\n }\n if (out_of_place == -1) {\n if ((arr[index] >= 0 && index % 2 == 0) ||\n (arr[index] < 0 && index % 2 == 1)) {\n out_of_place = index;\n }\n }\n }\n}", + "test": "int main() {\n\n int arr1[] = {-5, -2, 5, 2, 4, 7, 1, 8, 0, -8};\n\n int arr1_result[] = {-5, 5, -2, 2, -8, 4, 7, 1, 8, 0};\n\n func0(arr1, 10);\n\n for (int i = 0; i < 10; i++) {\n\n assert(arr1[i] == arr1_result[i]);\n\n }\n\n\n\n int arr2[] = {1, 2, 3, -4, -1, 4};\n\n int arr2_result[] = {-4, 1, -1, 2, 3, 4};\n\n func0(arr2, 6);\n\n for (int i = 0; i < 6; i++) {\n\n assert(arr2[i] == arr2_result[i]);\n\n }\n\n \n\n int arr3[] = {4, 7, 9, 77, -4, 5, -3, -9};\n\n int arr3_result[] = {-4, 4, -3, 7, -9, 9, 77, 5};\n\n func0(arr3, 8);\n\n for (int i = 0; i < 8; i++) {\n\n assert(arr3[i] == arr3_result[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0xffffffff,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmpq 131a \ncmpl $0x0,-0x8(%rbp)\njs 12b9 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ntest %eax,%eax\njs 1258 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ntest %eax,%eax\njs 128c \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ntest %eax,%eax\njns 12b9 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ntest %eax,%eax\njs 12b9 \nmov -0x4(%rbp),%ecx\nmov -0x8(%rbp),%edx\nmov -0x1c(%rbp),%esi\nmov -0x18(%rbp),%rax\nmov %rax,%rdi\ncallq 1169 \nmov -0x4(%rbp),%eax\nsub -0x8(%rbp),%eax\ncmp $0x2,%eax\njle 12b2 \naddl $0x2,-0x8(%rbp)\njmp 12b9 \nmovl $0xffffffff,-0x8(%rbp)\ncmpl $0xffffffff,-0x8(%rbp)\njne 1316 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ntest %eax,%eax\njs 12e3 \nmov -0x4(%rbp),%eax\nand $0x1,%eax\ntest %eax,%eax\nje 1310 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ntest %eax,%eax\njns 1316 \nmov -0x4(%rbp),%eax\ncltd\nshr $0x1f,%edx\nadd %edx,%eax\nand $0x1,%eax\nsub %edx,%eax\ncmp $0x1,%eax\njne 1316 \nmov -0x4(%rbp),%eax\nmov %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 121a \nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0FFFFFFFFh\nmov [rbp+var_4], 0\njmp loc_1320\nloc_121A:\ncmp [rbp+var_8], 0\njs loc_12B9\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njs short loc_1258\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njs short loc_128C\nloc_1258:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njns short loc_12B9\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njs short loc_12B9\nloc_128C:\nmov ecx, [rbp+var_4]\nmov edx, [rbp+var_8]\nmov esi, [rbp+var_1C]\nmov rax, [rbp+var_18]\nmov rdi, rax\ncall right_rotate\nmov eax, [rbp+var_4]\nsub eax, [rbp+var_8]\ncmp eax, 2\njle short loc_12B2\nadd [rbp+var_8], 2\njmp short loc_12B9\nloc_12B2:\nmov [rbp+var_8], 0FFFFFFFFh\nloc_12B9:\ncmp [rbp+var_8], 0FFFFFFFFh\njnz short loc_131C\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njs short loc_12E3\nmov eax, [rbp+var_4]\nand eax, 1\ntest eax, eax\njz short loc_1316\nloc_12E3:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njns short loc_131C\nmov edx, [rbp+var_4]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\ncmp eax, 1\njnz short loc_131C\nloc_1316:\nmov eax, [rbp+var_4]\nmov [rbp+var_8], eax\nloc_131C:\nadd [rbp+var_4], 1\nloc_1320:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl loc_121A\nnop\nnop\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 result; // rax\n int v3; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v3 = -1;\n for ( i = 0; ; ++i )\n {\n result = (unsigned int)i;\n if ( i >= a2 )\n break;\n if ( v3 >= 0\n && (*(int *)(4LL * i + a1) >= 0 && *(int *)(4LL * v3 + a1) < 0\n || *(int *)(4LL * i + a1) < 0 && *(int *)(4LL * v3 + a1) >= 0) )\n {\n right_rotate(a1, (unsigned int)a2, (unsigned int)v3, (unsigned int)i);\n if ( i - v3 <= 2 )\n v3 = -1;\n else\n v3 += 2;\n }\n if ( v3 == -1 && (*(int *)(4LL * i + a1) >= 0 && (i & 1) == 0 || *(int *)(4LL * i + a1) < 0 && i % 2 == 1) )\n v3 = i;\n }\n return result;\n}", + "ida_strip_asm": "sub_11F4:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0FFFFFFFFh\nmov [rbp+var_4], 0\njmp loc_1320\nloc_121A:\ncmp [rbp+var_8], 0\njs loc_12B9\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njs short loc_1258\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njs short loc_128C\nloc_1258:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njns short loc_12B9\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njs short loc_12B9\nloc_128C:\nmov ecx, [rbp+var_4]\nmov edx, [rbp+var_8]\nmov esi, [rbp+var_1C]\nmov rax, [rbp+var_18]\nmov rdi, rax\ncall sub_1169\nmov eax, [rbp+var_4]\nsub eax, [rbp+var_8]\ncmp eax, 2\njle short loc_12B2\nadd [rbp+var_8], 2\njmp short loc_12B9\nloc_12B2:\nmov [rbp+var_8], 0FFFFFFFFh\nloc_12B9:\ncmp [rbp+var_8], 0FFFFFFFFh\njnz short loc_131C\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njs short loc_12E3\nmov eax, [rbp+var_4]\nand eax, 1\ntest eax, eax\njz short loc_1316\nloc_12E3:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njns short loc_131C\nmov edx, [rbp+var_4]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\ncmp eax, 1\njnz short loc_131C\nloc_1316:\nmov eax, [rbp+var_4]\nmov [rbp+var_8], eax\nloc_131C:\nadd [rbp+var_4], 1\nloc_1320:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl loc_121A\nnop\nnop\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11F4(__int64 a1, int a2)\n{\n __int64 result; // rax\n int v3; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v3 = -1;\n for ( i = 0; ; ++i )\n {\n result = (unsigned int)i;\n if ( i >= a2 )\n break;\n if ( v3 >= 0\n && (*(int *)(4LL * i + a1) >= 0 && *(int *)(4LL * v3 + a1) < 0\n || *(int *)(4LL * i + a1) < 0 && *(int *)(4LL * v3 + a1) >= 0) )\n {\n sub_1169(a1, (unsigned int)a2, (unsigned int)v3, (unsigned int)i);\n if ( i - v3 <= 2 )\n v3 = -1;\n else\n v3 += 2;\n }\n if ( v3 == -1 && (*(int *)(4LL * i + a1) >= 0 && (i & 1) == 0 || *(int *)(4LL * i + a1) < 0 && i % 2 == 1) )\n v3 = i;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11F4(long long a1, int a2) {\n long long result;\n int v3;\n int i;\n v3 = -1;\n for (i = 0;; ++i) {\n result = (unsigned int)i;\n if (i >= a2) break;\n if (v3 >= 0 &&\n (*(int *)(4LL * i + a1) >= 0 && *(int *)(4LL * v3 + a1) < 0 ||\n *(int *)(4LL * i + a1) < 0 && *(int *)(4LL * v3 + a1) >= 0)) {\n sub_1169(a1, (unsigned int)a2, (unsigned int)v3, (unsigned int)i);\n if (i - v3 <= 2)\n v3 = -1;\n else\n v3 += 2;\n }\n if (v3 == -1 && (*(int *)(4LL * i + a1) >= 0 && (i & 1) == 0 ||\n *(int *)(4LL * i + a1) < 0 && i % 2 == 1))\n v3 = i;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long result;\n int v3;\n int i;\n v3 = -1;\n for (i = 0;; ++i) {\n result = (unsigned int)i;\n if (i >= a2) break;\n if (v3 >= 0 &&\n (*(int *)(4LL * i + a1) >= 0 && *(int *)(4LL * v3 + a1) < 0 ||\n *(int *)(4LL * i + a1) < 0 && *(int *)(4LL * v3 + a1) >= 0)) {\n right_rotate(a1, (unsigned int)a2, (unsigned int)v3, (unsigned int)i);\n if (i - v3 <= 2)\n v3 = -1;\n else\n v3 += 2;\n }\n if (v3 == -1 && (*(int *)(4LL * i + a1) >= 0 && (i & 1) == 0 ||\n *(int *)(4LL * i + a1) < 0 && i % 2 == 1))\n v3 = i;\n }\n return result;\n}" + }, + { + "index": 323, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\nvoid right_rotate(int arr[], int n, int out_of_place, int cur) {\n\n int temp = arr[cur];\n\n for (int i = cur; i > out_of_place; --i) {\n\n arr[i] = arr[i - 1];\n\n }\n\n arr[out_of_place] = temp;\n\n}\n\n\n\n", + "func": "void func0(int arr[], int n) {\n int out_of_place = -1;\n for (int index = 0; index < n; ++index) {\n if (out_of_place >= 0) {\n if ((arr[index] >= 0 && arr[out_of_place] < 0) ||\n (arr[index] < 0 && arr[out_of_place] >= 0)) {\n right_rotate(arr, n, out_of_place, index);\n if (index - out_of_place > 2) {\n out_of_place += 2;\n } else {\n out_of_place = -1;\n }\n }\n }\n if (out_of_place == -1) {\n if ((arr[index] >= 0 && index % 2 == 0) ||\n (arr[index] < 0 && index % 2 == 1)) {\n out_of_place = index;\n }\n }\n }\n}", + "test": "int main() {\n\n int arr1[] = {-5, -2, 5, 2, 4, 7, 1, 8, 0, -8};\n\n int arr1_result[] = {-5, 5, -2, 2, -8, 4, 7, 1, 8, 0};\n\n func0(arr1, 10);\n\n for (int i = 0; i < 10; i++) {\n\n assert(arr1[i] == arr1_result[i]);\n\n }\n\n\n\n int arr2[] = {1, 2, 3, -4, -1, 4};\n\n int arr2_result[] = {-4, 1, -1, 2, 3, 4};\n\n func0(arr2, 6);\n\n for (int i = 0; i < 6; i++) {\n\n assert(arr2[i] == arr2_result[i]);\n\n }\n\n \n\n int arr3[] = {4, 7, 9, 77, -4, 5, -3, -9};\n\n int arr3_result[] = {-4, 4, -3, 7, -9, 9, 77, 5};\n\n func0(arr3, 8);\n\n for (int i = 0; i < 8; i++) {\n\n assert(arr3[i] == arr3_result[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1275 \npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%r12\nmov %esi,%r15d\nlea -0x1(%rsi),%r14d\nmov $0x0,%ebx\nmov $0xffffffff,%ebp\njmp 120d \nmovslq %ebp,%rax\ncmpl $0x0,(%r12,%rax,4)\njns 1229 \njmp 1201 \ncmp $0xffffffff,%ebp\njne 1201 \ncmpl $0x0,(%r12,%rbx,4)\njs 1248 \ntestb $0x1,0x4(%rsp)\nmov $0xffffffff,%ebp\ncmove %r13d,%ebp\nlea 0x1(%rbx),%rax\ncmp %r14,%rbx\nje 1266 \nmov %rax,%rbx\nmov %ebx,0x4(%rsp)\nmov %ebx,%r13d\ntest %ebp,%ebp\njs 11e7 \ncmpl $0x0,(%r12,%rbx,4)\njs 11db \nmovslq %ebp,%rax\ncmpl $0x0,(%r12,%rax,4)\njns 1201 \nmov %r13d,%ecx\nmov %ebp,%edx\nmov %r15d,%esi\nmov %r12,%rdi\ncallq 1169 \nmov %r13d,%eax\nsub %ebp,%eax\nadd $0x2,%ebp\ncmp $0x2,%eax\njg 1201 \njmp 11ec \nmov %r13d,%edx\nshr $0x1f,%edx\nlea 0x0(%r13,%rdx,1),%eax\nand $0x1,%eax\nsub %edx,%eax\ncmp $0x1,%eax\nmov $0xffffffff,%ebp\ncmove %r13d,%ebp\njmp 1201 \nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle locret_1266\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r13, rdi\nmov r15d, esi\nmovsxd r14, esi\nmov ebx, 0\nmov ebp, 0FFFFFFFFh\njmp short loc_1205\nloc_11D5:\nmovsxd rax, ebp\ncmp dword ptr [r13+rax*4+0], 0\njns short loc_121F\njmp short loc_11FC\nloc_11E2:\ncmp ebp, 0FFFFFFFFh\njnz short loc_11FC\nloc_11E7:\ncmp dword ptr [r13+rbx*4+0], 0\njs short loc_123E\ntest r12b, 1\nmov ebp, 0FFFFFFFFh\ncmovz ebp, r12d\nloc_11FC:\nadd rbx, 1\ncmp rbx, r14\njz short loc_125B\nloc_1205:\nmov r12d, ebx\ntest ebp, ebp\njs short loc_11E2\ncmp dword ptr [r13+rbx*4+0], 0\njs short loc_11D5\nmovsxd rax, ebp\ncmp dword ptr [r13+rax*4+0], 0\njns short loc_11FC\nloc_121F:\nmov ecx, r12d\nmov edx, ebp\nmov esi, r15d\nmov rdi, r13\ncall right_rotate\nmov eax, r12d\nsub eax, ebp\nadd ebp, 2\ncmp eax, 2\njg short loc_11FC\njmp short loc_11E7\nloc_123E:\nmov edx, r12d\nshr edx, 1Fh\nlea eax, [r12+rdx]\nand eax, 1\nsub eax, edx\ncmp eax, 1\nmov ebp, 0FFFFFFFFh\ncmovz ebp, r12d\njmp short loc_11FC\nloc_125B:\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nlocret_1266:\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // rbx\n int v3; // ebp\n __int64 result; // rax\n\n if ( a2 > 0 )\n {\n v2 = 0LL;\n v3 = -1;\n do\n {\n if ( v3 < 0 )\n {\n if ( v3 == -1 )\n goto LABEL_6;\n }\n else\n {\n if ( *(int *)(a1 + 4 * v2) < 0 )\n {\n result = v3;\n if ( *(int *)(a1 + 4LL * v3) < 0 )\n goto LABEL_9;\n }\n else\n {\n result = v3;\n if ( *(int *)(a1 + 4LL * v3) >= 0 )\n goto LABEL_9;\n }\n right_rotate(a1, (unsigned int)a2, (unsigned int)v3, (unsigned int)v2);\n result = (unsigned int)(v2 - v3);\n v3 += 2;\n if ( (int)result <= 2 )\n {\nLABEL_6:\n if ( *(int *)(a1 + 4 * v2) < 0 )\n {\n result = (unsigned int)((int)v2 % 2);\n v3 = -1;\n if ( (_DWORD)result == 1 )\n v3 = v2;\n }\n else\n {\n v3 = -1;\n if ( (v2 & 1) == 0 )\n v3 = v2;\n }\n }\n }\nLABEL_9:\n ++v2;\n }\n while ( v2 != a2 );\n }\n return result;\n}", + "ida_strip_asm": "sub_11AA:\nendbr64\ntest esi, esi\njle locret_1266\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r13, rdi\nmov r15d, esi\nmovsxd r14, esi\nmov ebx, 0\nmov ebp, 0FFFFFFFFh\njmp short loc_1205\nloc_11D5:\nmovsxd rax, ebp\ncmp dword ptr [r13+rax*4+0], 0\njns short loc_121F\njmp short loc_11FC\nloc_11E2:\ncmp ebp, 0FFFFFFFFh\njnz short loc_11FC\nloc_11E7:\ncmp dword ptr [r13+rbx*4+0], 0\njs short loc_123E\ntest r12b, 1\nmov ebp, 0FFFFFFFFh\ncmovz ebp, r12d\nloc_11FC:\nadd rbx, 1\ncmp rbx, r14\njz short loc_125B\nloc_1205:\nmov r12d, ebx\ntest ebp, ebp\njs short loc_11E2\ncmp dword ptr [r13+rbx*4+0], 0\njs short loc_11D5\nmovsxd rax, ebp\ncmp dword ptr [r13+rax*4+0], 0\njns short loc_11FC\nloc_121F:\nmov ecx, r12d\nmov edx, ebp\nmov esi, r15d\nmov rdi, r13\ncall sub_1169\nmov eax, r12d\nsub eax, ebp\nadd ebp, 2\ncmp eax, 2\njg short loc_11FC\njmp short loc_11E7\nloc_123E:\nmov edx, r12d\nshr edx, 1Fh\nlea eax, [r12+rdx]\nand eax, 1\nsub eax, edx\ncmp eax, 1\nmov ebp, 0FFFFFFFFh\ncmovz ebp, r12d\njmp short loc_11FC\nloc_125B:\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nlocret_1266:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11AA(__int64 a1, int a2)\n{\n __int64 v2; // rbx\n int v3; // ebp\n __int64 result; // rax\n\n if ( a2 > 0 )\n {\n v2 = 0LL;\n v3 = -1;\n do\n {\n if ( v3 < 0 )\n {\n if ( v3 == -1 )\n goto LABEL_6;\n }\n else\n {\n if ( *(int *)(a1 + 4 * v2) < 0 )\n {\n result = v3;\n if ( *(int *)(a1 + 4LL * v3) < 0 )\n goto LABEL_9;\n }\n else\n {\n result = v3;\n if ( *(int *)(a1 + 4LL * v3) >= 0 )\n goto LABEL_9;\n }\n sub_1169(a1, (unsigned int)a2, (unsigned int)v3, (unsigned int)v2);\n result = (unsigned int)(v2 - v3);\n v3 += 2;\n if ( (int)result <= 2 )\n {\nLABEL_6:\n if ( *(int *)(a1 + 4 * v2) < 0 )\n {\n result = (unsigned int)((int)v2 % 2);\n v3 = -1;\n if ( (_DWORD)result == 1 )\n v3 = v2;\n }\n else\n {\n v3 = -1;\n if ( (v2 & 1) == 0 )\n v3 = v2;\n }\n }\n }\nLABEL_9:\n ++v2;\n }\n while ( v2 != a2 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11AA(long long a1, int a2) {\n long long v2;\n int v3;\n long long result;\n if (a2 > 0) {\n v2 = 0LL;\n v3 = -1;\n do {\n if (v3 < 0) {\n if (v3 == -1) goto LABEL_6;\n } else {\n if (*(int *)(a1 + 4 * v2) < 0) {\n result = v3;\n if (*(int *)(a1 + 4LL * v3) < 0) goto LABEL_9;\n } else {\n result = v3;\n if (*(int *)(a1 + 4LL * v3) >= 0) goto LABEL_9;\n }\n sub_1169(a1, (unsigned int)a2, (unsigned int)v3, (unsigned int)v2);\n result = (unsigned int)(v2 - v3);\n v3 += 2;\n if ((int)result <= 2) {\n LABEL_6:\n if (*(int *)(a1 + 4 * v2) < 0) {\n result = (unsigned int)((int)v2 % 2);\n v3 = -1;\n if ((uint32_t)result == 1) v3 = v2;\n } else {\n v3 = -1;\n if ((v2 & 1) == 0) v3 = v2;\n }\n }\n }\n LABEL_9:\n ++v2;\n } while (v2 != a2);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n int v3;\n long long result;\n if (a2 > 0) {\n v2 = 0LL;\n v3 = -1;\n do {\n if (v3 < 0) {\n if (v3 == -1) goto LABEL_6;\n } else {\n if (*(int *)(a1 + 4 * v2) < 0) {\n result = v3;\n if (*(int *)(a1 + 4LL * v3) < 0) goto LABEL_9;\n } else {\n result = v3;\n if (*(int *)(a1 + 4LL * v3) >= 0) goto LABEL_9;\n }\n right_rotate(a1, (unsigned int)a2, (unsigned int)v3, (unsigned int)v2);\n result = (unsigned int)(v2 - v3);\n v3 += 2;\n if ((int)result <= 2) {\n LABEL_6:\n if (*(int *)(a1 + 4 * v2) < 0) {\n result = (unsigned int)((int)v2 % 2);\n v3 = -1;\n if ((uint32_t)result == 1) v3 = v2;\n } else {\n v3 = -1;\n if ((v2 & 1) == 0) v3 = v2;\n }\n }\n }\n LABEL_9:\n ++v2;\n } while (v2 != a2);\n }\n return result;\n}" + }, + { + "index": 323, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\nvoid right_rotate(int arr[], int n, int out_of_place, int cur) {\n\n int temp = arr[cur];\n\n for (int i = cur; i > out_of_place; --i) {\n\n arr[i] = arr[i - 1];\n\n }\n\n arr[out_of_place] = temp;\n\n}\n\n\n\n", + "func": "void func0(int arr[], int n) {\n int out_of_place = -1;\n for (int index = 0; index < n; ++index) {\n if (out_of_place >= 0) {\n if ((arr[index] >= 0 && arr[out_of_place] < 0) ||\n (arr[index] < 0 && arr[out_of_place] >= 0)) {\n right_rotate(arr, n, out_of_place, index);\n if (index - out_of_place > 2) {\n out_of_place += 2;\n } else {\n out_of_place = -1;\n }\n }\n }\n if (out_of_place == -1) {\n if ((arr[index] >= 0 && index % 2 == 0) ||\n (arr[index] < 0 && index % 2 == 1)) {\n out_of_place = index;\n }\n }\n }\n}", + "test": "int main() {\n\n int arr1[] = {-5, -2, 5, 2, 4, 7, 1, 8, 0, -8};\n\n int arr1_result[] = {-5, 5, -2, 2, -8, 4, 7, 1, 8, 0};\n\n func0(arr1, 10);\n\n for (int i = 0; i < 10; i++) {\n\n assert(arr1[i] == arr1_result[i]);\n\n }\n\n\n\n int arr2[] = {1, 2, 3, -4, -1, 4};\n\n int arr2_result[] = {-4, 1, -1, 2, 3, 4};\n\n func0(arr2, 6);\n\n for (int i = 0; i < 6; i++) {\n\n assert(arr2[i] == arr2_result[i]);\n\n }\n\n \n\n int arr3[] = {4, 7, 9, 77, -4, 5, -3, -9};\n\n int arr3_result[] = {-4, 4, -3, 7, -9, 9, 77, 5};\n\n func0(arr3, 8);\n\n for (int i = 0; i < 8; i++) {\n\n assert(arr3[i] == arr3_result[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1580 \npush %r12\nxor %r8d,%r8d\nmov $0xffffffff,%r10d\nlea -0x4(%rdi),%r12\npush %rbp\npush %rbx\njmp 14bc \nlea 0x0(,%r11,4),%rdx\nmovslq %r10d,%rcx\nlea (%rdi,%rdx,1),%rax\nlea (%rdi,%rcx,4),%rbp\nmov (%rax),%ebx\nmov 0x0(%rbp),%ecx\ntest %ebx,%ebx\njs 1520 \ntest %ecx,%ecx\njs 1524 \nmov %r9d,%r8d\ncmp %r9d,%esi\njle 1571 \nlea 0x1(%r8),%r9d\nmovslq %r8d,%r11\ncmp $0xffffffff,%r10d\njne 1490 \nmov %r8d,%r10d\nlea (%rdi,%r11,4),%rax\nmov (%rax),%edx\nmov %r9d,%r8d\ntest %edx,%edx\njs 14ff \ntest $0x1,%r10b\nje 14b3 \ncmp %r9d,%esi\njle 1571 \nmovslq %r8d,%r11\nmov %r9d,%r10d\nadd $0x1,%r9d\nlea (%rdi,%r11,4),%rax\nmov %r9d,%r8d\nmov (%rax),%edx\ntest %edx,%edx\njns 14d9 \ntest $0x1,%r10b\njne 14b3 \nadd $0x4,%rax\ncmp %r9d,%esi\njle 1571 \nmov %r9d,%r10d\nadd $0x1,%r9d\njmp 14d0 \nnopw 0x0(%rax,%rax,1)\ntest %ecx,%ecx\njs 14b0 \ncmp %r8d,%r10d\njge 154f \nlea -0x1(%r8),%ecx\nadd %r12,%rdx\nsub %r10d,%ecx\nshl $0x2,%rcx\nsub %rcx,%rdx\nnopw 0x0(%rax,%rax,1)\nmov -0x4(%rax),%ecx\nsub $0x4,%rax\nmov %ecx,0x4(%rax)\ncmp %rdx,%rax\njne 1540 \nmov %r8d,%eax\nmov %ebx,0x0(%rbp)\nsub %r10d,%eax\ncmp $0x2,%eax\njle 14c9 \nadd $0x2,%r10d\nmov %r9d,%r8d\ncmp %r9d,%esi\njg 14bc \npop %rbx\npop %rbp\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle locret_1520\npush r15\npush r14\npush r13\nmov r13d, esi\npush r12\nmov r12, rdi\npush rbp\nxor ebp, ebp\npush rbx\nxor ebx, ebx\nsub rsp, 18h\nloc_1414:\nlea rax, [r12+rbp]\nmov edx, ebx\nmov eax, [rax]\nand edx, 1\ntest eax, eax\njs loc_14E8\ntest edx, edx\njnz loc_1500\nlea eax, [rbx+1]\nadd rbp, 4\ncmp r13d, eax\njz loc_14D4\nloc_143F:\nmov ecx, ebx\nmov ebx, eax\njmp short loc_1458\nloc_1448:\ntest eax, eax\njs short loc_146F\nloc_144C:\nadd ebx, 1\nadd rbp, 4\ncmp r13d, ebx\njz short loc_14D4\nloc_1458:\nmovsxd rax, ecx\nmov r15d, [r12+rbp]\nlea r14, [r12+rax*4]\nmov eax, [r14]\ntest r15d, r15d\njns short loc_1448\ntest eax, eax\njs short loc_144C\nloc_146F:\ncmp ecx, ebx\njge loc_1518\nmov r8d, ebx\nmov [rsp+48h+var_3C], ecx\nsub r8d, ecx\nlea eax, [r8-1]\nmov [rsp+48h+var_40], r8d\nmov rdi, rax\nlea rdx, ds:4[rax*4]; n\nneg rdi\nshl rdi, 2\nlea rsi, [rbp+rdi-4]\nadd rdi, rbp\nadd rsi, r12; src\nadd rdi, r12; dest\ncall _memmove\nmov r8d, [rsp+48h+var_40]\nmov ecx, [rsp+48h+var_3C]\nmov [r14], r15d\ncmp r8d, 2\njle loc_1414\nadd ebx, 1\nadd ecx, 2\nadd rbp, 4\ncmp r13d, ebx\njnz short loc_1458\nloc_14D4:\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14E8:\ntest edx, edx\njz short loc_1500\nlea eax, [rbx+1]\nadd rbp, 4\ncmp eax, r13d\njnz loc_143F\njmp short loc_14D4\nloc_1500:\nadd ebx, 1\nadd rbp, 4\ncmp ebx, r13d\njnz loc_1414\njmp short loc_14D4\nloc_1518:\nmov [r14], r15d\njmp loc_1414\nlocret_1520:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // rbp\n int v3; // ebx\n int v4; // eax\n int v5; // ecx\n int v6; // r15d\n int *v7; // r14\n int v8; // eax\n int v9; // [rsp+0h] [rbp-40h]\n int v10; // [rsp+4h] [rbp-3Ch]\n\n if ( a2 > 0 )\n {\n v2 = 0LL;\n v3 = 0;\n while ( 1 )\n {\nLABEL_3:\n while ( *(int *)(a1 + v2) < 0 )\n {\n if ( (v3 & 1) != 0 )\n {\n v4 = v3 + 1;\n v2 += 4LL;\n if ( v3 + 1 == a2 )\n return;\n goto LABEL_6;\n }\nLABEL_18:\n ++v3;\n v2 += 4LL;\n if ( v3 == a2 )\n return;\n }\n if ( (v3 & 1) != 0 )\n goto LABEL_18;\n v4 = v3 + 1;\n v2 += 4LL;\n if ( a2 == v3 + 1 )\n return;\nLABEL_6:\n v5 = v3;\n v3 = v4;\n while ( 1 )\n {\n while ( 1 )\n {\n v6 = *(_DWORD *)(a1 + v2);\n v7 = (int *)(a1 + 4LL * v5);\n v8 = *v7;\n if ( v6 < 0 )\n break;\n if ( v8 < 0 )\n goto LABEL_11;\nLABEL_8:\n ++v3;\n v2 += 4LL;\n if ( a2 == v3 )\n return;\n }\n if ( v8 < 0 )\n goto LABEL_8;\nLABEL_11:\n if ( v5 >= v3 )\n break;\n v10 = v5;\n v9 = v3 - v5;\n memmove(\n (void *)(a1 + v2 - 4LL * (unsigned int)(v3 - v5 - 1)),\n (const void *)(a1 + v2 - 4LL * (unsigned int)(v3 - v5 - 1) - 4),\n 4LL * (unsigned int)(v3 - v5 - 1) + 4);\n *v7 = v6;\n if ( v9 <= 2 )\n goto LABEL_3;\n ++v3;\n v5 = v10 + 2;\n v2 += 4LL;\n if ( a2 == v3 )\n return;\n }\n *v7 = v6;\n }\n }\n}", + "ida_strip_asm": "sub_13F0:\nendbr64\ntest esi, esi\njle locret_1520\npush r15\npush r14\npush r13\nmov r13d, esi\npush r12\nmov r12, rdi\npush rbp\nxor ebp, ebp\npush rbx\nxor ebx, ebx\nsub rsp, 18h\nloc_1414:\nlea rax, [r12+rbp]\nmov edx, ebx\nmov eax, [rax]\nand edx, 1\ntest eax, eax\njs loc_14E8\ntest edx, edx\njnz loc_1500\nlea eax, [rbx+1]\nadd rbp, 4\ncmp r13d, eax\njz loc_14D4\nloc_143F:\nmov ecx, ebx\nmov ebx, eax\njmp short loc_1458\nloc_1448:\ntest eax, eax\njs short loc_146F\nloc_144C:\nadd ebx, 1\nadd rbp, 4\ncmp r13d, ebx\njz short loc_14D4\nloc_1458:\nmovsxd rax, ecx\nmov r15d, [r12+rbp]\nlea r14, [r12+rax*4]\nmov eax, [r14]\ntest r15d, r15d\njns short loc_1448\ntest eax, eax\njs short loc_144C\nloc_146F:\ncmp ecx, ebx\njge loc_1518\nmov r8d, ebx\nmov [rsp+48h+var_3C], ecx\nsub r8d, ecx\nlea eax, [r8-1]\nmov [rsp+48h+var_40], r8d\nmov rdi, rax\nlea rdx, ds:4[rax*4]; n\nneg rdi\nshl rdi, 2\nlea rsi, [rbp+rdi-4]\nadd rdi, rbp\nadd rsi, r12; src\nadd rdi, r12; dest\ncall _memmove\nmov r8d, [rsp+48h+var_40]\nmov ecx, [rsp+48h+var_3C]\nmov [r14], r15d\ncmp r8d, 2\njle loc_1414\nadd ebx, 1\nadd ecx, 2\nadd rbp, 4\ncmp r13d, ebx\njnz short loc_1458\nloc_14D4:\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14E8:\ntest edx, edx\njz short loc_1500\nlea eax, [rbx+1]\nadd rbp, 4\ncmp eax, r13d\njnz loc_143F\njmp short loc_14D4\nloc_1500:\nadd ebx, 1\nadd rbp, 4\ncmp ebx, r13d\njnz loc_1414\njmp short loc_14D4\nloc_1518:\nmov [r14], r15d\njmp loc_1414\nlocret_1520:\nretn", + "ida_strip_pseudo": "void __fastcall sub_13F0(__int64 a1, int a2)\n{\n __int64 v2; // rbp\n int v3; // ebx\n int v4; // eax\n int v5; // ecx\n int v6; // r15d\n int *v7; // r14\n int v8; // eax\n int v9; // [rsp+0h] [rbp-40h]\n int v10; // [rsp+4h] [rbp-3Ch]\n\n if ( a2 > 0 )\n {\n v2 = 0LL;\n v3 = 0;\n while ( 1 )\n {\nLABEL_3:\n while ( *(int *)(a1 + v2) < 0 )\n {\n if ( (v3 & 1) != 0 )\n {\n v4 = v3 + 1;\n v2 += 4LL;\n if ( v3 + 1 == a2 )\n return;\n goto LABEL_6;\n }\nLABEL_18:\n ++v3;\n v2 += 4LL;\n if ( v3 == a2 )\n return;\n }\n if ( (v3 & 1) != 0 )\n goto LABEL_18;\n v4 = v3 + 1;\n v2 += 4LL;\n if ( a2 == v3 + 1 )\n return;\nLABEL_6:\n v5 = v3;\n v3 = v4;\n while ( 1 )\n {\n while ( 1 )\n {\n v6 = *(_DWORD *)(a1 + v2);\n v7 = (int *)(a1 + 4LL * v5);\n v8 = *v7;\n if ( v6 < 0 )\n break;\n if ( v8 < 0 )\n goto LABEL_11;\nLABEL_8:\n ++v3;\n v2 += 4LL;\n if ( a2 == v3 )\n return;\n }\n if ( v8 < 0 )\n goto LABEL_8;\nLABEL_11:\n if ( v5 >= v3 )\n break;\n v10 = v5;\n v9 = v3 - v5;\n memmove(\n (void *)(a1 + v2 - 4LL * (unsigned int)(v3 - v5 - 1)),\n (const void *)(a1 + v2 - 4LL * (unsigned int)(v3 - v5 - 1) - 4),\n 4LL * (unsigned int)(v3 - v5 - 1) + 4);\n *v7 = v6;\n if ( v9 <= 2 )\n goto LABEL_3;\n ++v3;\n v5 = v10 + 2;\n v2 += 4LL;\n if ( a2 == v3 )\n return;\n }\n *v7 = v6;\n }\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_13F0(long long a1, int a2) {\n long long v2;\n int v3;\n int v4;\n int v5;\n int v6;\n int *v7;\n int v8;\n int v9;\n int v10;\n if (a2 > 0) {\n v2 = 0LL;\n v3 = 0;\n while (1) {\n LABEL_3:\n while (*(int *)(a1 + v2) < 0) {\n if ((v3 & 1) != 0) {\n v4 = v3 + 1;\n v2 += 4LL;\n if (v3 + 1 == a2) return;\n goto LABEL_6;\n }\n LABEL_18:\n ++v3;\n v2 += 4LL;\n if (v3 == a2) return;\n }\n if ((v3 & 1) != 0) goto LABEL_18;\n v4 = v3 + 1;\n v2 += 4LL;\n if (a2 == v3 + 1) return;\n LABEL_6:\n v5 = v3;\n v3 = v4;\n while (1) {\n while (1) {\n v6 = *(uint32_t *)(a1 + v2);\n v7 = (int *)(a1 + 4LL * v5);\n v8 = *v7;\n if (v6 < 0) break;\n if (v8 < 0) goto LABEL_11;\n LABEL_8:\n ++v3;\n v2 += 4LL;\n if (a2 == v3) return;\n }\n if (v8 < 0) goto LABEL_8;\n LABEL_11:\n if (v5 >= v3) break;\n v10 = v5;\n v9 = v3 - v5;\n memmove((void *)(a1 + v2 - 4LL * (unsigned int)(v3 - v5 - 1)),\n (const void *)(a1 + v2 - 4LL * (unsigned int)(v3 - v5 - 1) - 4),\n 4LL * (unsigned int)(v3 - v5 - 1) + 4);\n *v7 = v6;\n if (v9 <= 2) goto LABEL_3;\n ++v3;\n v5 = v10 + 2;\n v2 += 4LL;\n if (a2 == v3) return;\n }\n *v7 = v6;\n }\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2) {\n long long v2;\n int v3;\n int v4;\n int v5;\n int v6;\n int *v7;\n int v8;\n int v9;\n int v10;\n if (a2 > 0) {\n v2 = 0LL;\n v3 = 0;\n while (1) {\n LABEL_3:\n while (*(int *)(a1 + v2) < 0) {\n if ((v3 & 1) != 0) {\n v4 = v3 + 1;\n v2 += 4LL;\n if (v3 + 1 == a2) return;\n goto LABEL_6;\n }\n LABEL_18:\n ++v3;\n v2 += 4LL;\n if (v3 == a2) return;\n }\n if ((v3 & 1) != 0) goto LABEL_18;\n v4 = v3 + 1;\n v2 += 4LL;\n if (a2 == v3 + 1) return;\n LABEL_6:\n v5 = v3;\n v3 = v4;\n while (1) {\n while (1) {\n v6 = *(uint32_t *)(a1 + v2);\n v7 = (int *)(a1 + 4LL * v5);\n v8 = *v7;\n if (v6 < 0) break;\n if (v8 < 0) goto LABEL_11;\n LABEL_8:\n ++v3;\n v2 += 4LL;\n if (a2 == v3) return;\n }\n if (v8 < 0) goto LABEL_8;\n LABEL_11:\n if (v5 >= v3) break;\n v10 = v5;\n v9 = v3 - v5;\n memmove((void *)(a1 + v2 - 4LL * (unsigned int)(v3 - v5 - 1)),\n (const void *)(a1 + v2 - 4LL * (unsigned int)(v3 - v5 - 1) - 4),\n 4LL * (unsigned int)(v3 - v5 - 1) + 4);\n *v7 = v6;\n if (v9 <= 2) goto LABEL_3;\n ++v3;\n v5 = v10 + 2;\n v2 += 4LL;\n if (a2 == v3) return;\n }\n *v7 = v6;\n }\n }\n}" + }, + { + "index": 323, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\nvoid right_rotate(int arr[], int n, int out_of_place, int cur) {\n\n int temp = arr[cur];\n\n for (int i = cur; i > out_of_place; --i) {\n\n arr[i] = arr[i - 1];\n\n }\n\n arr[out_of_place] = temp;\n\n}\n\n\n\n", + "func": "void func0(int arr[], int n) {\n int out_of_place = -1;\n for (int index = 0; index < n; ++index) {\n if (out_of_place >= 0) {\n if ((arr[index] >= 0 && arr[out_of_place] < 0) ||\n (arr[index] < 0 && arr[out_of_place] >= 0)) {\n right_rotate(arr, n, out_of_place, index);\n if (index - out_of_place > 2) {\n out_of_place += 2;\n } else {\n out_of_place = -1;\n }\n }\n }\n if (out_of_place == -1) {\n if ((arr[index] >= 0 && index % 2 == 0) ||\n (arr[index] < 0 && index % 2 == 1)) {\n out_of_place = index;\n }\n }\n }\n}", + "test": "int main() {\n\n int arr1[] = {-5, -2, 5, 2, 4, 7, 1, 8, 0, -8};\n\n int arr1_result[] = {-5, 5, -2, 2, -8, 4, 7, 1, 8, 0};\n\n func0(arr1, 10);\n\n for (int i = 0; i < 10; i++) {\n\n assert(arr1[i] == arr1_result[i]);\n\n }\n\n\n\n int arr2[] = {1, 2, 3, -4, -1, 4};\n\n int arr2_result[] = {-4, 1, -1, 2, 3, 4};\n\n func0(arr2, 6);\n\n for (int i = 0; i < 6; i++) {\n\n assert(arr2[i] == arr2_result[i]);\n\n }\n\n \n\n int arr3[] = {4, 7, 9, 77, -4, 5, -3, -9};\n\n int arr3_result[] = {-4, 4, -3, 7, -9, 9, 77, 5};\n\n func0(arr3, 8);\n\n for (int i = 0; i < 8; i++) {\n\n assert(arr3[i] == arr3_result[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1610 \npush %r15\nmov %esi,%r15d\npush %r14\nmov %rdi,%r14\npush %r13\npush %r12\nmov $0xffffffff,%r12d\npush %rbp\npush %rbx\nxor %ebx,%ebx\nsub $0x18,%rsp\nnopl 0x0(%rax,%rax,1)\nlea 0x1(%rbx),%ebp\nmovslq %ebx,%r13\ncmp $0xffffffff,%r12d\nje 15b8 \nmovslq %r12d,%rax\nmov (%r14,%r13,4),%ecx\nlea 0x0(,%r13,4),%rdi\nlea (%r14,%rax,4),%r8\nmov (%r8),%eax\ntest %ecx,%ecx\njs 1558 \ntest %eax,%eax\njs 155c \nmov %ebp,%ebx\ncmp %ebp,%r15d\njg 1510 \nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\ntest %eax,%eax\njs 153e \ncmp %ebx,%r12d\njge 15a0 \nmov %ebx,%eax\nmov %r8,0x8(%rsp)\nsub %r12d,%eax\nmov %ecx,0x4(%rsp)\nlea -0x1(%rax),%edx\nmov %rdx,%rax\nlea 0x4(,%rdx,4),%rdx\nneg %rax\nshl $0x2,%rax\nlea -0x4(%rdi,%rax,1),%rsi\nadd %rax,%rdi\nadd %r14,%rsi\nadd %r14,%rdi\ncallq 1090 \nmov 0x4(%rsp),%ecx\nmov 0x8(%rsp),%r8\nmov %ebx,%eax\nmov %ecx,(%r8)\nsub %r12d,%eax\ncmp $0x2,%eax\njle 15b8 \nadd $0x2,%r12d\nmov %ebp,%ebx\njmp 1540 \nnopl (%rax)\nmov %ebx,%r12d\nlea (%r14,%r13,4),%rax\nmov (%rax),%edx\nmov %ebp,%ebx\ntest %edx,%edx\njs 15ef \ntest $0x1,%r12b\nje 1540 \ncmp %ebp,%r15d\njle 1545 \nmovslq %ebx,%r13\nmov %ebp,%r12d\nadd $0x1,%ebp\nlea (%r14,%r13,4),%rax\nmov %ebp,%ebx\nmov (%rax),%edx\ntest %edx,%edx\njns 15c7 \ntest $0x1,%r12b\njne 1540 \nadd $0x4,%rax\ncmp %ebp,%r15d\njle 1545 \nmov %ebp,%r12d\nadd $0x1,%ebp\njmp 15bf \nxchg %ax,%ax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle locret_1510\npush r15\npush r14\npush r13\nmov r13d, esi\npush r12\nmov r12, rdi\npush rbp\nxor ebp, ebp\npush rbx\nxor ebx, ebx\nsub rsp, 18h\nloc_1414:\nlea rax, [r12+rbp]\nmov edx, ebx\nmov eax, [rax]\nand edx, 1\ntest eax, eax\njs loc_14E8\ntest edx, edx\njnz loc_14F0\nloc_142F:\nlea eax, [rbx+1]\nadd rbp, 4\ncmp r13d, eax\njz loc_14D4\nmov ecx, ebx\nmov ebx, eax\njmp short loc_1458\nloc_1448:\ntest eax, eax\njs short loc_146F\nloc_144C:\nadd ebx, 1\nadd rbp, 4\ncmp r13d, ebx\njz short loc_14D4\nloc_1458:\nmovsxd rax, ecx\nmov r15d, [r12+rbp]\nlea r14, [r12+rax*4]\nmov eax, [r14]\ntest r15d, r15d\njns short loc_1448\ntest eax, eax\njs short loc_144C\nloc_146F:\ncmp ecx, ebx\njge loc_1508\nmov r8d, ebx\nmov [rsp+48h+var_3C], ecx\nsub r8d, ecx\nlea eax, [r8-1]\nmov [rsp+48h+var_40], r8d\nmov rdi, rax\nlea rdx, ds:4[rax*4]; n\nneg rdi\nshl rdi, 2\nlea rsi, [rbp+rdi-4]\nadd rdi, rbp\nadd rsi, r12; src\nadd rdi, r12; dest\ncall _memmove\nmov r8d, [rsp+48h+var_40]\nmov ecx, [rsp+48h+var_3C]\nmov [r14], r15d\ncmp r8d, 2\njle loc_1414\nadd ebx, 1\nadd ecx, 2\nadd rbp, 4\ncmp r13d, ebx\njnz short loc_1458\nloc_14D4:\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14E8:\ntest edx, edx\njnz loc_142F\nloc_14F0:\nadd ebx, 1\nadd rbp, 4\ncmp r13d, ebx\njnz loc_1414\njmp short loc_14D4\nloc_1508:\nmov [r14], r15d\njmp loc_1414\nlocret_1510:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // rbp\n int v3; // ebx\n int v4; // ecx\n int v5; // r15d\n int *v6; // r14\n int v7; // eax\n int v8; // [rsp+0h] [rbp-40h]\n int v9; // [rsp+4h] [rbp-3Ch]\n\n if ( a2 > 0 )\n {\n v2 = 0LL;\n v3 = 0;\n while ( 1 )\n {\nLABEL_3:\n while ( *(int *)(a1 + v2) < 0 )\n {\n if ( (v3 & 1) != 0 )\n goto LABEL_5;\nLABEL_16:\n ++v3;\n v2 += 4LL;\n if ( a2 == v3 )\n return;\n }\n if ( (v3 & 1) != 0 )\n goto LABEL_16;\nLABEL_5:\n v2 += 4LL;\n if ( a2 == v3 + 1 )\n return;\n v4 = v3++;\n while ( 1 )\n {\n while ( 1 )\n {\n v5 = *(_DWORD *)(a1 + v2);\n v6 = (int *)(a1 + 4LL * v4);\n v7 = *v6;\n if ( v5 < 0 )\n break;\n if ( v7 < 0 )\n goto LABEL_11;\nLABEL_8:\n ++v3;\n v2 += 4LL;\n if ( a2 == v3 )\n return;\n }\n if ( v7 < 0 )\n goto LABEL_8;\nLABEL_11:\n if ( v4 >= v3 )\n break;\n v9 = v4;\n v8 = v3 - v4;\n memmove(\n (void *)(a1 + v2 - 4LL * (unsigned int)(v3 - v4 - 1)),\n (const void *)(a1 + v2 - 4LL * (unsigned int)(v3 - v4 - 1) - 4),\n 4LL * (unsigned int)(v3 - v4 - 1) + 4);\n *v6 = v5;\n if ( v8 <= 2 )\n goto LABEL_3;\n ++v3;\n v4 = v9 + 2;\n v2 += 4LL;\n if ( a2 == v3 )\n return;\n }\n *v6 = v5;\n }\n }\n}", + "ida_strip_asm": "sub_13F0:\nendbr64\ntest esi, esi\njle locret_1510\npush r15\npush r14\npush r13\nmov r13d, esi\npush r12\nmov r12, rdi\npush rbp\nxor ebp, ebp\npush rbx\nxor ebx, ebx\nsub rsp, 18h\nloc_1414:\nlea rax, [r12+rbp]\nmov edx, ebx\nmov eax, [rax]\nand edx, 1\ntest eax, eax\njs loc_14E8\ntest edx, edx\njnz loc_14F0\nloc_142F:\nlea eax, [rbx+1]\nadd rbp, 4\ncmp r13d, eax\njz loc_14D4\nmov ecx, ebx\nmov ebx, eax\njmp short loc_1458\nloc_1448:\ntest eax, eax\njs short loc_146F\nloc_144C:\nadd ebx, 1\nadd rbp, 4\ncmp r13d, ebx\njz short loc_14D4\nloc_1458:\nmovsxd rax, ecx\nmov r15d, [r12+rbp]\nlea r14, [r12+rax*4]\nmov eax, [r14]\ntest r15d, r15d\njns short loc_1448\ntest eax, eax\njs short loc_144C\nloc_146F:\ncmp ecx, ebx\njge loc_1508\nmov r8d, ebx\nmov [rsp+48h+var_3C], ecx\nsub r8d, ecx\nlea eax, [r8-1]\nmov [rsp+48h+var_40], r8d\nmov rdi, rax\nlea rdx, ds:4[rax*4]; n\nneg rdi\nshl rdi, 2\nlea rsi, [rbp+rdi-4]\nadd rdi, rbp\nadd rsi, r12; src\nadd rdi, r12; dest\ncall _memmove\nmov r8d, [rsp+48h+var_40]\nmov ecx, [rsp+48h+var_3C]\nmov [r14], r15d\ncmp r8d, 2\njle loc_1414\nadd ebx, 1\nadd ecx, 2\nadd rbp, 4\ncmp r13d, ebx\njnz short loc_1458\nloc_14D4:\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14E8:\ntest edx, edx\njnz loc_142F\nloc_14F0:\nadd ebx, 1\nadd rbp, 4\ncmp r13d, ebx\njnz loc_1414\njmp short loc_14D4\nloc_1508:\nmov [r14], r15d\njmp loc_1414\nlocret_1510:\nretn", + "ida_strip_pseudo": "void __fastcall sub_13F0(__int64 a1, int a2)\n{\n __int64 v2; // rbp\n int v3; // ebx\n int v4; // ecx\n int v5; // r15d\n int *v6; // r14\n int v7; // eax\n int v8; // [rsp+0h] [rbp-40h]\n int v9; // [rsp+4h] [rbp-3Ch]\n\n if ( a2 > 0 )\n {\n v2 = 0LL;\n v3 = 0;\n while ( 1 )\n {\nLABEL_3:\n while ( *(int *)(a1 + v2) < 0 )\n {\n if ( (v3 & 1) != 0 )\n goto LABEL_5;\nLABEL_16:\n ++v3;\n v2 += 4LL;\n if ( a2 == v3 )\n return;\n }\n if ( (v3 & 1) != 0 )\n goto LABEL_16;\nLABEL_5:\n v2 += 4LL;\n if ( a2 == v3 + 1 )\n return;\n v4 = v3++;\n while ( 1 )\n {\n while ( 1 )\n {\n v5 = *(_DWORD *)(a1 + v2);\n v6 = (int *)(a1 + 4LL * v4);\n v7 = *v6;\n if ( v5 < 0 )\n break;\n if ( v7 < 0 )\n goto LABEL_11;\nLABEL_8:\n ++v3;\n v2 += 4LL;\n if ( a2 == v3 )\n return;\n }\n if ( v7 < 0 )\n goto LABEL_8;\nLABEL_11:\n if ( v4 >= v3 )\n break;\n v9 = v4;\n v8 = v3 - v4;\n memmove(\n (void *)(a1 + v2 - 4LL * (unsigned int)(v3 - v4 - 1)),\n (const void *)(a1 + v2 - 4LL * (unsigned int)(v3 - v4 - 1) - 4),\n 4LL * (unsigned int)(v3 - v4 - 1) + 4);\n *v6 = v5;\n if ( v8 <= 2 )\n goto LABEL_3;\n ++v3;\n v4 = v9 + 2;\n v2 += 4LL;\n if ( a2 == v3 )\n return;\n }\n *v6 = v5;\n }\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_13F0(long long a1, int a2) {\n long long v2;\n int v3;\n int v4;\n int v5;\n int *v6;\n int v7;\n int v8;\n int v9;\n if (a2 > 0) {\n v2 = 0LL;\n v3 = 0;\n while (1) {\n LABEL_3:\n while (*(int *)(a1 + v2) < 0) {\n if ((v3 & 1) != 0) goto LABEL_5;\n LABEL_16:\n ++v3;\n v2 += 4LL;\n if (a2 == v3) return;\n }\n if ((v3 & 1) != 0) goto LABEL_16;\n LABEL_5:\n v2 += 4LL;\n if (a2 == v3 + 1) return;\n v4 = v3++;\n while (1) {\n while (1) {\n v5 = *(uint32_t *)(a1 + v2);\n v6 = (int *)(a1 + 4LL * v4);\n v7 = *v6;\n if (v5 < 0) break;\n if (v7 < 0) goto LABEL_11;\n LABEL_8:\n ++v3;\n v2 += 4LL;\n if (a2 == v3) return;\n }\n if (v7 < 0) goto LABEL_8;\n LABEL_11:\n if (v4 >= v3) break;\n v9 = v4;\n v8 = v3 - v4;\n memmove((void *)(a1 + v2 - 4LL * (unsigned int)(v3 - v4 - 1)),\n (const void *)(a1 + v2 - 4LL * (unsigned int)(v3 - v4 - 1) - 4),\n 4LL * (unsigned int)(v3 - v4 - 1) + 4);\n *v6 = v5;\n if (v8 <= 2) goto LABEL_3;\n ++v3;\n v4 = v9 + 2;\n v2 += 4LL;\n if (a2 == v3) return;\n }\n *v6 = v5;\n }\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2) {\n long long v2;\n int v3;\n int v4;\n int v5;\n int *v6;\n int v7;\n int v8;\n int v9;\n if (a2 > 0) {\n v2 = 0LL;\n v3 = 0;\n while (1) {\n LABEL_3:\n while (*(int *)(a1 + v2) < 0) {\n if ((v3 & 1) != 0) goto LABEL_5;\n LABEL_16:\n ++v3;\n v2 += 4LL;\n if (a2 == v3) return;\n }\n if ((v3 & 1) != 0) goto LABEL_16;\n LABEL_5:\n v2 += 4LL;\n if (a2 == v3 + 1) return;\n v4 = v3++;\n while (1) {\n while (1) {\n v5 = *(uint32_t *)(a1 + v2);\n v6 = (int *)(a1 + 4LL * v4);\n v7 = *v6;\n if (v5 < 0) break;\n if (v7 < 0) goto LABEL_11;\n LABEL_8:\n ++v3;\n v2 += 4LL;\n if (a2 == v3) return;\n }\n if (v7 < 0) goto LABEL_8;\n LABEL_11:\n if (v4 >= v3) break;\n v9 = v4;\n v8 = v3 - v4;\n memmove((void *)(a1 + v2 - 4LL * (unsigned int)(v3 - v4 - 1)),\n (const void *)(a1 + v2 - 4LL * (unsigned int)(v3 - v4 - 1) - 4),\n 4LL * (unsigned int)(v3 - v4 - 1) + 4);\n *v6 = v5;\n if (v8 <= 2) goto LABEL_3;\n ++v3;\n v4 = v9 + 2;\n v2 += 4LL;\n if (a2 == v3) return;\n }\n *v6 = v5;\n }\n }\n}" + }, + { + "index": 324, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int test_tuple[], int size) {\n static int sums[2];\n int sum1 = 0;\n int sum2 = 0;\n for (int idx = 0; idx < size; idx++) {\n if (idx % 2) {\n sum1 += test_tuple[idx];\n } else {\n sum2 += test_tuple[idx];\n }\n }\n sums[0] = sum1;\n sums[1] = sum2;\n return sums;\n}", + "test": "int main() {\n\n int arr1[] = {5, 6, 3, 6, 10, 34};\n\n int* result1 = func0(arr1, 6);\n\n assert(result1[0] == 46 && result1[1] == 18);\n\n\n\n int arr2[] = {1, 2, 3, 4, 5};\n\n int* result2 = func0(arr2, 5);\n\n assert(result2[0] == 6 && result2[1] == 9);\n\n\n\n int arr3[] = {6, 7, 8, 9, 4, 5};\n\n int* result3 = func0(arr3, 6);\n\n assert(result3[0] == 21 && result3[1] == 18);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11d1 \nmov -0x4(%rbp),%eax\nand $0x1,%eax\ntest %eax,%eax\nje 11b4 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nadd %eax,-0xc(%rbp)\njmp 11cd \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nadd %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 118f \nmov -0xc(%rbp),%eax\nmov %eax,0x2e36(%rip)\nmov -0x8(%rbp),%eax\nmov %eax,0x2e31(%rip)\nlea 0x2e26(%rip),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11D1\nloc_118F:\nmov eax, [rbp+var_4]\nand eax, 1\ntest eax, eax\njz short loc_11B4\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_C], eax\njmp short loc_11CD\nloc_11B4:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nloc_11CD:\nadd [rbp+var_4], 1\nloc_11D1:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_118F\nmov eax, [rbp+var_C]\nmov cs:sums_1, eax\nmov eax, [rbp+var_8]\nmov cs:dword_401C, eax\nlea rax, sums_1\npop rbp\nretn", + "ida_pseudo": "int *__fastcall func0(__int64 a1, int a2)\n{\n int v3; // [rsp+10h] [rbp-Ch]\n int v4; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( (i & 1) != 0 )\n v3 += *(_DWORD *)(4LL * i + a1);\n else\n v4 += *(_DWORD *)(4LL * i + a1);\n }\n sums_1 = v3;\n dword_401C = v4;\n return &sums_1;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11D1\nloc_118F:\nmov eax, [rbp+var_4]\nand eax, 1\ntest eax, eax\njz short loc_11B4\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_C], eax\njmp short loc_11CD\nloc_11B4:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nloc_11CD:\nadd [rbp+var_4], 1\nloc_11D1:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_118F\nmov eax, [rbp+var_C]\nmov cs:dword_4018, eax\nmov eax, [rbp+var_8]\nmov cs:dword_401C, eax\nlea rax, dword_4018\npop rbp\nretn", + "ida_strip_pseudo": "int *__fastcall sub_1169(__int64 a1, int a2)\n{\n int v3; // [rsp+10h] [rbp-Ch]\n int v4; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( (i & 1) != 0 )\n v3 += *(_DWORD *)(4LL * i + a1);\n else\n v4 += *(_DWORD *)(4LL * i + a1);\n }\n dword_4018 = v3;\n dword_401C = v4;\n return &dword_4018;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "int *sub_1169(long long a1, int a2) {\n int v3;\n int v4;\n int i;\n v3 = 0;\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n if ((i & 1) != 0)\n v3 += *(uint32_t *)(4LL * i + a1);\n else\n v4 += *(uint32_t *)(4LL * i + a1);\n }\n dword_4018 = v3;\n dword_401C = v4;\n return &dword_4018;\n}", + "ida_pseudo_norm": "int *func0(long long a1, int a2) {\n int v3;\n int v4;\n int i;\n v3 = 0;\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n if ((i & 1) != 0)\n v3 += *(uint32_t *)(4LL * i + a1);\n else\n v4 += *(uint32_t *)(4LL * i + a1);\n }\n sums_1 = v3;\n dword_401C = v4;\n return &sums_1;\n}" + }, + { + "index": 324, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int test_tuple[], int size) {\n static int sums[2];\n int sum1 = 0;\n int sum2 = 0;\n for (int idx = 0; idx < size; idx++) {\n if (idx % 2) {\n sum1 += test_tuple[idx];\n } else {\n sum2 += test_tuple[idx];\n }\n }\n sums[0] = sum1;\n sums[1] = sum2;\n return sums;\n}", + "test": "int main() {\n\n int arr1[] = {5, 6, 3, 6, 10, 34};\n\n int* result1 = func0(arr1, 6);\n\n assert(result1[0] == 46 && result1[1] == 18);\n\n\n\n int arr2[] = {1, 2, 3, 4, 5};\n\n int* result2 = func0(arr2, 5);\n\n assert(result2[0] == 6 && result2[1] == 9);\n\n\n\n int arr3[] = {6, 7, 8, 9, 4, 5};\n\n int* result3 = func0(arr3, 6);\n\n assert(result3[0] == 21 && result3[1] == 18);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 119e \nlea -0x1(%rsi),%r8d\nmov $0x0,%eax\nmov $0x0,%ecx\nmov $0x0,%esi\njmp 1195 \nadd (%rdi,%rax,4),%ecx\nlea 0x1(%rax),%rdx\ncmp %r8,%rax\nje 11a8 \nmov %rdx,%rax\ntest $0x1,%al\nje 1186 \nadd (%rdi,%rax,4),%esi\njmp 1189 \nmov $0x0,%ecx\nmov $0x0,%esi\nmov %esi,0x2e6a(%rip)\nmov %ecx,0x2e68(%rip)\nlea 0x2e5d(%rip),%rax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_119A\nmovsxd rsi, esi\nmov eax, 0\nmov edx, 0\nmov ecx, 0\njmp short loc_1191\nloc_1185:\nadd edx, [rdi+rax*4]\nloc_1188:\nadd rax, 1\ncmp rax, rsi\njz short loc_11A4\nloc_1191:\ntest al, 1\njz short loc_1185\nadd ecx, [rdi+rax*4]\njmp short loc_1188\nloc_119A:\nmov edx, 0\nmov ecx, 0\nloc_11A4:\nmov cs:sums_1, ecx\nmov cs:dword_401C, edx\nlea rax, sums_1\nretn", + "ida_pseudo": "int *__fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // rax\n int v3; // edx\n int v4; // ecx\n\n if ( a2 <= 0 )\n {\n v3 = 0;\n v4 = 0;\n }\n else\n {\n v2 = 0LL;\n v3 = 0;\n v4 = 0;\n do\n {\n if ( (v2 & 1) != 0 )\n v4 += *(_DWORD *)(a1 + 4 * v2);\n else\n v3 += *(_DWORD *)(a1 + 4 * v2);\n ++v2;\n }\n while ( v2 != a2 );\n }\n sums_1 = v4;\n dword_401C = v3;\n return &sums_1;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_119A\nmovsxd rsi, esi\nmov eax, 0\nmov edx, 0\nmov ecx, 0\njmp short loc_1191\nloc_1185:\nadd edx, [rdi+rax*4]\nloc_1188:\nadd rax, 1\ncmp rax, rsi\njz short loc_11A4\nloc_1191:\ntest al, 1\njz short loc_1185\nadd ecx, [rdi+rax*4]\njmp short loc_1188\nloc_119A:\nmov edx, 0\nmov ecx, 0\nloc_11A4:\nmov cs:dword_4018, ecx\nmov cs:dword_401C, edx\nlea rax, dword_4018\nretn", + "ida_strip_pseudo": "int *__fastcall sub_1169(__int64 a1, int a2)\n{\n __int64 v2; // rax\n int v3; // edx\n int v4; // ecx\n\n if ( a2 <= 0 )\n {\n v3 = 0;\n v4 = 0;\n }\n else\n {\n v2 = 0LL;\n v3 = 0;\n v4 = 0;\n do\n {\n if ( (v2 & 1) != 0 )\n v4 += *(_DWORD *)(a1 + 4 * v2);\n else\n v3 += *(_DWORD *)(a1 + 4 * v2);\n ++v2;\n }\n while ( v2 != a2 );\n }\n dword_4018 = v4;\n dword_401C = v3;\n return &dword_4018;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "int *sub_1169(long long a1, int a2) {\n long long v2;\n int v3;\n int v4;\n if (a2 <= 0) {\n v3 = 0;\n v4 = 0;\n } else {\n v2 = 0LL;\n v3 = 0;\n v4 = 0;\n do {\n if ((v2 & 1) != 0)\n v4 += *(uint32_t *)(a1 + 4 * v2);\n else\n v3 += *(uint32_t *)(a1 + 4 * v2);\n ++v2;\n } while (v2 != a2);\n }\n dword_4018 = v4;\n dword_401C = v3;\n return &dword_4018;\n}", + "ida_pseudo_norm": "int *func0(long long a1, int a2) {\n long long v2;\n int v3;\n int v4;\n if (a2 <= 0) {\n v3 = 0;\n v4 = 0;\n } else {\n v2 = 0LL;\n v3 = 0;\n v4 = 0;\n do {\n if ((v2 & 1) != 0)\n v4 += *(uint32_t *)(a1 + 4 * v2);\n else\n v3 += *(uint32_t *)(a1 + 4 * v2);\n ++v2;\n } while (v2 != a2);\n }\n sums_1 = v4;\n dword_401C = v3;\n return &sums_1;\n}" + }, + { + "index": 324, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int test_tuple[], int size) {\n static int sums[2];\n int sum1 = 0;\n int sum2 = 0;\n for (int idx = 0; idx < size; idx++) {\n if (idx % 2) {\n sum1 += test_tuple[idx];\n } else {\n sum2 += test_tuple[idx];\n }\n }\n sums[0] = sum1;\n sums[1] = sum2;\n return sums;\n}", + "test": "int main() {\n\n int arr1[] = {5, 6, 3, 6, 10, 34};\n\n int* result1 = func0(arr1, 6);\n\n assert(result1[0] == 46 && result1[1] == 18);\n\n\n\n int arr2[] = {1, 2, 3, 4, 5};\n\n int* result2 = func0(arr2, 5);\n\n assert(result2[0] == 6 && result2[1] == 9);\n\n\n\n int arr3[] = {6, 7, 8, 9, 4, 5};\n\n int* result3 = func0(arr3, 6);\n\n assert(result3[0] == 21 && result3[1] == 18);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11a0 \nlea -0x1(%rsi),%r8d\nxor %eax,%eax\nxor %ecx,%ecx\nxor %esi,%esi\njmp 1176 \nnopl 0x0(%rax)\nadd %edx,%esi\nlea 0x1(%rax),%rdx\ncmp %r8,%rax\nje 1188 \nmov %rdx,%rax\nmov (%rdi,%rax,4),%edx\ntest $0x1,%al\njne 1168 \nadd %edx,%ecx\nlea 0x1(%rax),%rdx\ncmp %r8,%rax\njne 1173 \nmov %esi,0x2e8a(%rip)\nlea 0x2e83(%rip),%rax\nmov %ecx,0x2e81(%rip)\nretq\nnopl 0x0(%rax)\nxor %ecx,%ecx\nxor %esi,%esi\njmp 1188 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_12F0\nmovsxd rsi, esi\nxor eax, eax\nxor ecx, ecx\nxor r8d, r8d\njmp short loc_12C4\nloc_12B8:\nadd rax, 1\nadd r8d, edx\ncmp rax, rsi\njz short loc_12D6\nloc_12C4:\nmov edx, [rdi+rax*4]\ntest al, 1\njnz short loc_12B8\nadd rax, 1\nadd ecx, edx\ncmp rax, rsi\njnz short loc_12C4\nloc_12D6:\nmov cs:sums_1, r8d\nlea rax, sums_1\nmov cs:dword_401C, ecx\nretn\nloc_12F0:\nxor ecx, ecx\nxor r8d, r8d\njmp short loc_12D6", + "ida_pseudo": "int *__fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // rax\n int v3; // ecx\n int v4; // r8d\n int v5; // edx\n int *result; // rax\n\n if ( a2 <= 0 )\n {\n v3 = 0;\n v4 = 0;\n }\n else\n {\n v2 = 0LL;\n v3 = 0;\n v4 = 0;\n do\n {\n while ( 1 )\n {\n v5 = *(_DWORD *)(a1 + 4 * v2);\n if ( (v2 & 1) == 0 )\n break;\n ++v2;\n v4 += v5;\n if ( v2 == a2 )\n goto LABEL_6;\n }\n ++v2;\n v3 += v5;\n }\n while ( v2 != a2 );\n }\nLABEL_6:\n sums_1 = v4;\n result = &sums_1;\n dword_401C = v3;\n return result;\n}", + "ida_strip_asm": "sub_12A0:\nendbr64\ntest esi, esi\njle short loc_12F0\nmovsxd rsi, esi\nxor eax, eax\nxor ecx, ecx\nxor r8d, r8d\njmp short loc_12C4\nloc_12B8:\nadd rax, 1\nadd r8d, edx\ncmp rax, rsi\njz short loc_12D6\nloc_12C4:\nmov edx, [rdi+rax*4]\ntest al, 1\njnz short loc_12B8\nadd rax, 1\nadd ecx, edx\ncmp rax, rsi\njnz short loc_12C4\nloc_12D6:\nmov cs:dword_4018, r8d\nlea rax, dword_4018\nmov cs:dword_401C, ecx\nretn\nloc_12F0:\nxor ecx, ecx\nxor r8d, r8d\njmp short loc_12D6", + "ida_strip_pseudo": "int *__fastcall sub_12A0(__int64 a1, int a2)\n{\n __int64 v2; // rax\n int v3; // ecx\n int v4; // r8d\n int v5; // edx\n int *result; // rax\n\n if ( a2 <= 0 )\n {\n v3 = 0;\n v4 = 0;\n }\n else\n {\n v2 = 0LL;\n v3 = 0;\n v4 = 0;\n do\n {\n while ( 1 )\n {\n v5 = *(_DWORD *)(a1 + 4 * v2);\n if ( (v2 & 1) == 0 )\n break;\n ++v2;\n v4 += v5;\n if ( v2 == a2 )\n goto LABEL_6;\n }\n ++v2;\n v3 += v5;\n }\n while ( v2 != a2 );\n }\nLABEL_6:\n dword_4018 = v4;\n result = &dword_4018;\n dword_401C = v3;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "int *sub_12A0(long long a1, int a2) {\n long long v2;\n int v3;\n int v4;\n int v5;\n int *result;\n if (a2 <= 0) {\n v3 = 0;\n v4 = 0;\n } else {\n v2 = 0LL;\n v3 = 0;\n v4 = 0;\n do {\n while (1) {\n v5 = *(uint32_t *)(a1 + 4 * v2);\n if ((v2 & 1) == 0) break;\n ++v2;\n v4 += v5;\n if (v2 == a2) goto LABEL_6;\n }\n ++v2;\n v3 += v5;\n } while (v2 != a2);\n }\nLABEL_6:\n dword_4018 = v4;\n result = &dword_4018;\n dword_401C = v3;\n return result;\n}", + "ida_pseudo_norm": "int *func0(long long a1, int a2) {\n long long v2;\n int v3;\n int v4;\n int v5;\n int *result;\n if (a2 <= 0) {\n v3 = 0;\n v4 = 0;\n } else {\n v2 = 0LL;\n v3 = 0;\n v4 = 0;\n do {\n while (1) {\n v5 = *(uint32_t *)(a1 + 4 * v2);\n if ((v2 & 1) == 0) break;\n ++v2;\n v4 += v5;\n if (v2 == a2) goto LABEL_6;\n }\n ++v2;\n v3 += v5;\n } while (v2 != a2);\n }\nLABEL_6:\n sums_1 = v4;\n result = &sums_1;\n dword_401C = v3;\n return result;\n}" + }, + { + "index": 325, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n <= 3) {\n return n;\n }\n int res = n;\n for (int x = 1; x <= n; x++) {\n int temp = x * x;\n if (temp > n) {\n break;\n } else {\n res = (res < (1 + func0(n - temp))) ? res : (1 + func0(n - temp));\n }\n }\n return res;\n}", + "test": "int main() {\n\n assert(func0(6) == 3);\n\n assert(func0(2) == 2);\n\n assert(func0(4) == 1);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %edi,-0x14(%rbp)\ncmpl $0x3,-0x14(%rbp)\njg 1163 \nmov -0x14(%rbp),%eax\njmp 11bf \nmov -0x14(%rbp),%eax\nmov %eax,-0xc(%rbp)\nmovl $0x1,-0x8(%rbp)\njmp 11b1 \nmov -0x8(%rbp),%eax\nimul %eax,%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x14(%rbp),%eax\njg 11bb \nmov -0x14(%rbp),%eax\nsub -0x4(%rbp),%eax\nmov %eax,%edi\ncallq 1149 \ncmp %eax,-0xc(%rbp)\njle 11a7 \nmov -0x14(%rbp),%eax\nsub -0x4(%rbp),%eax\nmov %eax,%edi\ncallq 1149 \nadd $0x1,%eax\njmp 11aa \nmov -0xc(%rbp),%eax\nmov %eax,-0xc(%rbp)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x14(%rbp),%eax\njle 1172 \njmp 11bc \nmov -0xc(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\ncmp [rbp+var_14], 3\njg short loc_1163\nmov eax, [rbp+var_14]\njmp short locret_11BF\nloc_1163:\nmov eax, [rbp+var_14]\nmov [rbp+var_C], eax\nmov [rbp+var_8], 1\njmp short loc_11B1\nloc_1172:\nmov eax, [rbp+var_8]\nimul eax, eax\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_14]\njg short loc_11BB\nmov eax, [rbp+var_14]\nsub eax, [rbp+var_4]\nmov edi, eax\ncall func0\ncmp [rbp+var_C], eax\njle short loc_11A7\nmov eax, [rbp+var_14]\nsub eax, [rbp+var_4]\nmov edi, eax\ncall func0\nadd eax, 1\njmp short loc_11AA\nloc_11A7:\nmov eax, [rbp+var_C]\nloc_11AA:\nmov [rbp+var_C], eax\nadd [rbp+var_8], 1\nloc_11B1:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_14]\njle short loc_1172\njmp short loc_11BC\nloc_11BB:\nnop\nloc_11BC:\nmov eax, [rbp+var_C]\nlocret_11BF:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v2; // eax\n int v3; // [rsp+14h] [rbp-Ch]\n int i; // [rsp+18h] [rbp-8h]\n int v5; // [rsp+1Ch] [rbp-4h]\n\n if ( a1 <= 3 )\n return (unsigned int)a1;\n v3 = a1;\n for ( i = 1; i <= a1; ++i )\n {\n v5 = i * i;\n if ( i * i > a1 )\n break;\n if ( v3 <= (int)func0((unsigned int)(a1 - v5)) )\n v2 = v3;\n else\n v2 = func0((unsigned int)(a1 - v5)) + 1;\n v3 = v2;\n }\n return (unsigned int)v3;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\ncmp [rbp+var_14], 3\njg short loc_1163\nmov eax, [rbp+var_14]\njmp short locret_11BF\nloc_1163:\nmov eax, [rbp+var_14]\nmov [rbp+var_C], eax\nmov [rbp+var_8], 1\njmp short loc_11B1\nloc_1172:\nmov eax, [rbp+var_8]\nimul eax, eax\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_14]\njg short loc_11BB\nmov eax, [rbp+var_14]\nsub eax, [rbp+var_4]\nmov edi, eax\ncall sub_1149\ncmp [rbp+var_C], eax\njle short loc_11A7\nmov eax, [rbp+var_14]\nsub eax, [rbp+var_4]\nmov edi, eax\ncall sub_1149\nadd eax, 1\njmp short loc_11AA\nloc_11A7:\nmov eax, [rbp+var_C]\nloc_11AA:\nmov [rbp+var_C], eax\nadd [rbp+var_8], 1\nloc_11B1:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_14]\njle short loc_1172\njmp short loc_11BC\nloc_11BB:\nnop\nloc_11BC:\nmov eax, [rbp+var_C]\nlocret_11BF:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v2; // eax\n int v3; // [rsp+14h] [rbp-Ch]\n int i; // [rsp+18h] [rbp-8h]\n int v5; // [rsp+1Ch] [rbp-4h]\n\n if ( a1 <= 3 )\n return (unsigned int)a1;\n v3 = a1;\n for ( i = 1; i <= a1; ++i )\n {\n v5 = i * i;\n if ( i * i > a1 )\n break;\n if ( v3 <= (int)sub_1149((unsigned int)(a1 - v5)) )\n v2 = v3;\n else\n v2 = sub_1149((unsigned int)(a1 - v5)) + 1;\n v3 = v2;\n }\n return (unsigned int)v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v2;\n int v3;\n int i;\n int v5;\n if (a1 <= 3) return (unsigned int)a1;\n v3 = a1;\n for (i = 1; i <= a1; ++i) {\n v5 = i * i;\n if (i * i > a1) break;\n if (v3 <= (int)sub_1149((unsigned int)(a1 - v5)))\n v2 = v3;\n else\n v2 = sub_1149((unsigned int)(a1 - v5)) + 1;\n v3 = v2;\n }\n return (unsigned int)v3;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v2;\n int v3;\n int i;\n int v5;\n if (a1 <= 3) return (unsigned int)a1;\n v3 = a1;\n for (i = 1; i <= a1; ++i) {\n v5 = i * i;\n if (i * i > a1) break;\n if (v3 <= (int)func0((unsigned int)(a1 - v5)))\n v2 = v3;\n else\n v2 = func0((unsigned int)(a1 - v5)) + 1;\n v3 = v2;\n }\n return (unsigned int)v3;\n}" + }, + { + "index": 325, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n <= 3) {\n return n;\n }\n int res = n;\n for (int x = 1; x <= n; x++) {\n int temp = x * x;\n if (temp > n) {\n break;\n } else {\n res = (res < (1 + func0(n - temp))) ? res : (1 + func0(n - temp));\n }\n }\n return res;\n}", + "test": "int main() {\n\n assert(func0(6) == 3);\n\n assert(func0(2) == 2);\n\n assert(func0(4) == 1);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmov %edi,%r12d\ncmp $0x3,%edi\njle 1188 \nmov %edi,%ebx\nmov $0x1,%eax\nmov $0x1,%ebp\nmov %ebx,%edi\nsub %eax,%edi\ncallq 1149 \nlea 0x1(%rax),%edx\ncmp %r12d,%eax\ncmovl %edx,%r12d\nadd $0x1,%ebp\ncmp %ebp,%ebx\njl 1188 \nmov %ebp,%eax\nimul %ebp,%eax\ncmp %eax,%ebx\njge 1165 \nmov %r12d,%eax\npop %rbx\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov r12d, edi\ncmp edi, 3\njle short loc_118A\nmov ebx, edi\nmov eax, 1\nmov ebp, 1\njmp short loc_1170\nloc_1167:\nmov eax, ebp\nimul eax, ebp\ncmp ebx, eax\njl short loc_118A\nloc_1170:\nmov edi, ebx\nsub edi, eax\ncall func0\nlea edx, [rax+1]\ncmp eax, r12d\ncmovl r12d, edx\nadd ebp, 1\ncmp ebx, ebp\njge short loc_1167\nloc_118A:\nmov eax, r12d\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // r12d\n int v2; // eax\n int v3; // ebp\n int v4; // eax\n\n v1 = a1;\n if ( a1 > 3 )\n {\n v2 = 1;\n v3 = 1;\n do\n {\n v4 = func0((unsigned int)(a1 - v2));\n if ( v4 < v1 )\n v1 = v4 + 1;\n if ( a1 < ++v3 )\n break;\n v2 = v3 * v3;\n }\n while ( a1 >= v3 * v3 );\n }\n return (unsigned int)v1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush r12\npush rbp\npush rbx\nmov r12d, edi\ncmp edi, 3\njle short loc_118A\nmov ebx, edi\nmov eax, 1\nmov ebp, 1\njmp short loc_1170\nloc_1167:\nmov eax, ebp\nimul eax, ebp\ncmp ebx, eax\njl short loc_118A\nloc_1170:\nmov edi, ebx\nsub edi, eax\ncall sub_1149\nlea edx, [rax+1]\ncmp eax, r12d\ncmovl r12d, edx\nadd ebp, 1\ncmp ebx, ebp\njge short loc_1167\nloc_118A:\nmov eax, r12d\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v1; // r12d\n int v2; // eax\n int v3; // ebp\n int v4; // eax\n\n v1 = a1;\n if ( a1 > 3 )\n {\n v2 = 1;\n v3 = 1;\n do\n {\n v4 = sub_1149((unsigned int)(a1 - v2));\n if ( v4 < v1 )\n v1 = v4 + 1;\n if ( a1 < ++v3 )\n break;\n v2 = v3 * v3;\n }\n while ( a1 >= v3 * v3 );\n }\n return (unsigned int)v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v1;\n int v2;\n int v3;\n int v4;\n v1 = a1;\n if (a1 > 3) {\n v2 = 1;\n v3 = 1;\n do {\n v4 = sub_1149((unsigned int)(a1 - v2));\n if (v4 < v1) v1 = v4 + 1;\n if (a1 < ++v3) break;\n v2 = v3 * v3;\n } while (a1 >= v3 * v3);\n }\n return (unsigned int)v1;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v2;\n int v3;\n int v4;\n v1 = a1;\n if (a1 > 3) {\n v2 = 1;\n v3 = 1;\n do {\n v4 = func0((unsigned int)(a1 - v2));\n if (v4 < v1) v1 = v4 + 1;\n if (a1 < ++v3) break;\n v2 = v3 * v3;\n } while (a1 >= v3 * v3);\n }\n return (unsigned int)v1;\n}" + }, + { + "index": 325, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n <= 3) {\n return n;\n }\n int res = n;\n for (int x = 1; x <= n; x++) {\n int temp = x * x;\n if (temp > n) {\n break;\n } else {\n res = (res < (1 + func0(n - temp))) ? res : (1 + func0(n - temp));\n }\n }\n return res;\n}", + "test": "int main() {\n\n assert(func0(6) == 3);\n\n assert(func0(2) == 2);\n\n assert(func0(4) == 1);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x3,%edi\njle 11d0 \njmp 11e0 \nnopl 0x0(%rax,%rax,1)\nmov %edi,%eax\nretq\ndata16 nopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0_part_0:\npush r14\nmov eax, 1\npush r13\nmov r13d, edi\npush r12\nmov r12d, edi\npush rbp\npush rbx\nmov ebx, 1\ntest edi, edi\njle short loc_1207\nloc_11DC:\nmov ebp, r12d\nsub ebp, eax\ncmp ebp, 3\njle short loc_1218\nmov edi, ebp\ncall func0_part_0\nmov r14d, eax\ncmp eax, r13d\njl short loc_1228\nloc_11F5:\nadd ebx, 1\ncmp r12d, ebx\njl short loc_1207\nmov eax, ebx\nimul eax, ebx\ncmp eax, r12d\njle short loc_11DC\nloc_1207:\npop rbx\nmov eax, r13d\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1218:\ncmp ebp, r13d\njge short loc_11F5\nlea r13d, [rbp+1]\njmp short loc_11F5\nloc_1228:\nmov edi, ebp\nmov ebp, r14d\ncall func0_part_0\nlea r13d, [rbp+1]\njmp short loc_11F5", + "ida_pseudo": "__int64 __fastcall func0_part_0(int a1)\n{\n int v1; // eax\n int v2; // r13d\n int v4; // ebx\n unsigned int v5; // ebp\n int v6; // eax\n __int64 v8; // rdi\n int v9; // ebp\n\n v1 = 1;\n v2 = a1;\n v4 = 1;\n if ( a1 > 0 )\n {\n do\n {\n v5 = a1 - v1;\n if ( a1 - v1 <= 3 )\n {\n if ( (int)v5 < v2 )\n v2 = v5 + 1;\n }\n else\n {\n v6 = func0_part_0(v5);\n if ( v6 < v2 )\n {\n v8 = v5;\n v9 = v6;\n func0_part_0(v8);\n v2 = v9 + 1;\n }\n }\n if ( a1 < ++v4 )\n break;\n v1 = v4 * v4;\n }\n while ( v4 * v4 <= a1 );\n }\n return (unsigned int)v2;\n}", + "ida_strip_asm": "sub_11C0:\npush r14\nmov eax, 1\npush r13\nmov r13d, edi\npush r12\nmov r12d, edi\npush rbp\npush rbx\nmov ebx, 1\ntest edi, edi\njle short loc_1207\nloc_11DC:\nmov ebp, r12d\nsub ebp, eax\ncmp ebp, 3\njle short loc_1218\nmov edi, ebp\ncall sub_11C0\nmov r14d, eax\ncmp eax, r13d\njl short loc_1228\nloc_11F5:\nadd ebx, 1\ncmp r12d, ebx\njl short loc_1207\nmov eax, ebx\nimul eax, ebx\ncmp eax, r12d\njle short loc_11DC\nloc_1207:\npop rbx\nmov eax, r13d\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1218:\ncmp ebp, r13d\njge short loc_11F5\nlea r13d, [rbp+1]\njmp short loc_11F5\nloc_1228:\nmov edi, ebp\nmov ebp, r14d\ncall sub_11C0\nlea r13d, [rbp+1]\njmp short loc_11F5", + "ida_strip_pseudo": "__int64 __fastcall sub_11C0(int a1)\n{\n int v1; // eax\n int v2; // r13d\n int v4; // ebx\n unsigned int v5; // ebp\n int v6; // eax\n __int64 v8; // rdi\n int v9; // ebp\n\n v1 = 1;\n v2 = a1;\n v4 = 1;\n if ( a1 > 0 )\n {\n do\n {\n v5 = a1 - v1;\n if ( a1 - v1 <= 3 )\n {\n if ( (int)v5 < v2 )\n v2 = v5 + 1;\n }\n else\n {\n v6 = sub_11C0(v5);\n if ( v6 < v2 )\n {\n v8 = v5;\n v9 = v6;\n sub_11C0(v8);\n v2 = v9 + 1;\n }\n }\n if ( a1 < ++v4 )\n break;\n v1 = v4 * v4;\n }\n while ( v4 * v4 <= a1 );\n }\n return (unsigned int)v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11C0(int a1) {\n int v1;\n int v2;\n int v4;\n unsigned int v5;\n int v6;\n long long v8;\n int v9;\n v1 = 1;\n v2 = a1;\n v4 = 1;\n if (a1 > 0) {\n do {\n v5 = a1 - v1;\n if (a1 - v1 <= 3) {\n if ((int)v5 < v2) v2 = v5 + 1;\n } else {\n v6 = sub_11C0(v5);\n if (v6 < v2) {\n v8 = v5;\n v9 = v6;\n sub_11C0(v8);\n v2 = v9 + 1;\n }\n }\n if (a1 < ++v4) break;\n v1 = v4 * v4;\n } while (v4 * v4 <= a1);\n }\n return (unsigned int)v2;\n}", + "ida_pseudo_norm": "long long func0_part_0(int a1) {\n int v1;\n int v2;\n int v4;\n unsigned int v5;\n int v6;\n long long v8;\n int v9;\n v1 = 1;\n v2 = a1;\n v4 = 1;\n if (a1 > 0) {\n do {\n v5 = a1 - v1;\n if (a1 - v1 <= 3) {\n if ((int)v5 < v2) v2 = v5 + 1;\n } else {\n v6 = func0_part_0(v5);\n if (v6 < v2) {\n v8 = v5;\n v9 = v6;\n func0_part_0(v8);\n v2 = v9 + 1;\n }\n }\n if (a1 < ++v4) break;\n v1 = v4 * v4;\n } while (v4 * v4 <= a1);\n }\n return (unsigned int)v2;\n}" + }, + { + "index": 325, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n <= 3) {\n return n;\n }\n int res = n;\n for (int x = 1; x <= n; x++) {\n int temp = x * x;\n if (temp > n) {\n break;\n } else {\n res = (res < (1 + func0(n - temp))) ? res : (1 + func0(n - temp));\n }\n }\n return res;\n}", + "test": "int main() {\n\n assert(func0(6) == 3);\n\n assert(func0(2) == 2);\n\n assert(func0(4) == 1);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nmov %edi,%r8d\ncmp $0x3,%edi\njle 13e8 \nmov %edi,%ecx\nmov $0x1,%esi\nmov $0x1,%eax\nmov %ecx,%edx\nsub %eax,%edx\ncmp $0x3,%edx\njle 13c8 \npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %edx,%edi\ncallq 11c0 \ncmp %r8d,%eax\njl 12c0 \nadd $0x1,%esi\ncmp %esi,%ecx\njl 12ab \nmov %esi,%eax\nimul %esi,%eax\ncmp %eax,%ecx\njl 12ab \nmov %ecx,%edx\nsub %eax,%edx\ncmp $0x3,%edx\njg 1273 \ncmp %r8d,%edx\njge 127f \nmov %edx,%r8d\nadd $0x1,%esi\nadd $0x1,%r8d\ncmp %esi,%ecx\njge 1286 \nadd $0x8,%rsp\nmov %r8d,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax)\nmov $0x1,%eax\nmov %edx,%r9d\nmov %edx,%r8d\nmov $0x1,%r10d\nsub %eax,%r9d\ncmp $0x3,%r9d\njle 1307 \nmov %r9d,%edi\ncallq 11c0 \ncmp %r8d,%eax\njl 1318 \nadd $0x1,%r10d\ncmp %r10d,%edx\njl 12a0 \nmov %r10d,%eax\nimul %r10d,%eax\ncmp %eax,%edx\njl 12a0 \nmov %edx,%r9d\nsub %eax,%r9d\ncmp $0x3,%r9d\njg 12da \ncmp %r8d,%r9d\njge 12e7 \nmov %r9d,%r8d\nadd $0x1,%r8d\njmp 12e7 \nnopl (%rax)\nmov $0x1,%eax\nmov %r9d,%r11d\nmov %r9d,%r8d\nmov $0x1,%ebx\nsub %eax,%r11d\ncmp $0x3,%r11d\njle 135c \nmov %r11d,%edi\ncallq 11c0 \ncmp %r8d,%eax\njl 1370 \nadd $0x1,%ebx\ncmp %ebx,%r9d\njl 130f \nmov %ebx,%eax\nimul %ebx,%eax\ncmp %eax,%r9d\njl 130f \nmov %r9d,%r11d\nsub %eax,%r11d\ncmp $0x3,%r11d\njg 1331 \ncmp %r8d,%r11d\njge 133e \nmov %r11d,%r8d\nadd $0x1,%r8d\njmp 133e \nnopw 0x0(%rax,%rax,1)\nmov $0x1,%eax\nmov %r11d,%r12d\nmov %r11d,%r8d\nmov $0x1,%ebp\nsub %eax,%r12d\ncmp $0x3,%r12d\njle 13b7 \nmov %r12d,%edi\ncallq 11c0 \nmov %eax,%r13d\ncmp %r8d,%eax\njl 13f0 \nadd $0x1,%ebp\ncmp %ebp,%r11d\njl 1364 \nmov %ebp,%eax\nimul %ebp,%eax\ncmp %eax,%r11d\njl 1364 \nmov %r11d,%r12d\nsub %eax,%r12d\ncmp $0x3,%r12d\njg 1389 \ncmp %r8d,%r12d\njge 1399 \nlea 0x1(%r12),%r8d\njmp 1399 \nnopl 0x0(%rax,%rax,1)\ncmp %r8d,%edx\njge 13d4 \nmov %edx,%r8d\nadd $0x1,%r8d\nadd $0x1,%esi\ncmp %esi,%ecx\njl 13e8 \nmov %esi,%eax\nimul %esi,%eax\ncmp %eax,%ecx\njge 125c \nmov %r8d,%eax\nretq\nnopl 0x0(%rax)\nmov %r12d,%edi\nmov %r13d,%r12d\ncallq 11c0 \nlea 0x1(%r12),%r8d\njmp 1399 \nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0_part_0:\npush r15\npush r14\npush r13\npush r12\npush rbp\nmov ebp, edi\npush rbx\nsub rsp, 38h\ntest edi, edi\njle loc_1371\nmov eax, 1\nmov r13d, 1\nmov r12d, edi\nloc_11E6:\nmov esi, r12d\nsub esi, eax\ncmp esi, 3\njle loc_185B\nmov r14d, 1\nmov [rsp+68h+var_5C], r13d\nmov ebx, esi\nmov eax, 1\nmov [rsp+68h+var_58], ebp\nmov r13d, r12d\nmov ebp, r14d\nmov r14d, esi\nloc_1213:\nmov edx, r14d\nsub edx, eax\ncmp edx, 3\njle loc_15C0\nmov r15d, 1\nmov [rsp+68h+var_60], ebx\nmov eax, 1\nmov r8d, edx\nmov ebx, r15d\nmov r15d, edx\nloc_1239:\nmov r12d, r15d\nsub r12d, eax\ncmp r12d, 3\njle loc_1438\nmov r9d, r12d\nmov eax, 1\nmov esi, 1\nloc_1256:\nmov edx, r12d\nsub edx, eax\ncmp edx, 3\njle loc_13A0\nmov r10d, edx\nmov eax, 1\nmov ecx, 1\nloc_1271:\nmov edi, edx\nsub edi, eax\ncmp edi, 3\njle loc_1388\nmov [rsp+68h+var_3C], r10d\nmov [rsp+68h+var_40], ecx\nmov [rsp+68h+var_44], esi\nmov [rsp+68h+var_48], edx\nmov [rsp+68h+var_4C], r8d\nmov [rsp+68h+var_50], r9d\nmov [rsp+68h+var_54], edi\ncall func0_part_0\nmov r10d, [rsp+68h+var_3C]\nmov edi, [rsp+68h+var_54]\nmov r9d, [rsp+68h+var_50]\nmov r8d, [rsp+68h+var_4C]\ncmp eax, r10d\nmov edx, [rsp+68h+var_48]\nmov esi, [rsp+68h+var_44]\nmov ecx, [rsp+68h+var_40]\njl loc_1924\nnop word ptr [rax+rax+00h]\nloc_12D0:\nadd ecx, 1\ncmp edx, ecx\njl short loc_12E0\nmov eax, ecx\nimul eax, ecx\ncmp edx, eax\njge short loc_1271\nloc_12E0:\ncmp r9d, r10d\njg loc_13B8\nloc_12E9:\nadd esi, 1\ncmp r12d, esi\njl short loc_12FF\nmov eax, esi\nimul eax, esi\ncmp r12d, eax\njge loc_1256\nloc_12FF:\ncmp r9d, r8d\njl loc_1450\nloc_1308:\nadd ebx, 1\ncmp r15d, ebx\njl short loc_131E\nmov eax, ebx\nimul eax, ebx\ncmp r15d, eax\njge loc_1239\nloc_131E:\nmov ebx, [rsp+68h+var_60]\nmov edx, r15d\ncmp r8d, ebx\njl loc_15D2\nloc_132E:\nadd ebp, 1\ncmp r14d, ebp\njl short loc_1344\nmov eax, ebp\nimul eax, ebp\ncmp r14d, eax\njge loc_1213\nloc_1344:\nmov ebp, [rsp+68h+var_58]\nmov r12d, r13d\nmov r13d, [rsp+68h+var_5C]\ncmp ebx, ebp\njl loc_1A0F\nloc_1358:\nadd r13d, 1\ncmp r12d, r13d\njl short loc_1371\nmov eax, r13d\nimul eax, r13d\ncmp eax, r12d\njle loc_11E6\nloc_1371:\nadd rsp, 38h\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1388:\ncmp edi, r10d\njge loc_12D0\nlea r10d, [rdi+1]\njmp loc_12D0\nloc_13A0:\ncmp r9d, edx\njle loc_12E9\nmov r9d, edx\nloc_13AC:\nadd r9d, 1\njmp loc_12E9\nloc_13B8:\nmov eax, 1\nmov edi, edx\nmov r9d, edx\nmov ecx, 1\nsub edi, eax\ncmp edi, 3\njle short loc_1429\nloc_13CE:\nmov [rsp+68h+var_40], ecx\nmov [rsp+68h+var_44], r9d\nmov [rsp+68h+var_48], esi\nmov [rsp+68h+var_4C], edx\nmov [rsp+68h+var_50], r8d\nmov [rsp+68h+var_54], edi\ncall func0_part_0\nmov r9d, [rsp+68h+var_44]\nmov edi, [rsp+68h+var_54]\nmov r8d, [rsp+68h+var_50]\nmov edx, [rsp+68h+var_4C]\ncmp r9d, eax\nmov esi, [rsp+68h+var_48]\nmov ecx, [rsp+68h+var_40]\njg loc_18D2\nloc_1410:\nadd ecx, 1\ncmp edx, ecx\njl short loc_13AC\nmov eax, ecx\nimul eax, ecx\ncmp edx, eax\njl short loc_13AC\nmov edi, edx\nsub edi, eax\ncmp edi, 3\njg short loc_13CE\nloc_1429:\ncmp r9d, edi\njle short loc_1410\nlea r9d, [rdi+1]\njmp short loc_1410\nloc_1438:\ncmp r12d, r8d\njge loc_1308\nmov r8d, r12d\nloc_1444:\nadd r8d, 1\njmp loc_1308\nloc_1450:\nmov r9d, 1\nmov ecx, ebp\nmov r8d, r12d\nmov eax, 1\nmov ebp, r9d\nmov esi, ebx\nmov r9d, r13d\nmov r13d, r12d\nloc_146B:\nmov r12d, r13d\nsub r12d, eax\ncmp r12d, 3\njle loc_1530\nmov edx, r12d\nmov eax, 1\nmov ebx, 1\nloc_1488:\nmov edi, r12d\nsub edi, eax\ncmp edi, 3\njle loc_1520\nmov [rsp+68h+var_40], r9d\nmov [rsp+68h+var_44], edx\nmov [rsp+68h+var_48], r8d\nmov [rsp+68h+var_4C], esi\nmov [rsp+68h+var_50], ecx\nmov [rsp+68h+var_54], edi\ncall func0_part_0\nmov edx, [rsp+68h+var_44]\nmov edi, [rsp+68h+var_54]\nmov ecx, [rsp+68h+var_50]\nmov esi, [rsp+68h+var_4C]\ncmp edx, eax\nmov r8d, [rsp+68h+var_48]\nmov r9d, [rsp+68h+var_40]\njg loc_19A6\nnop word ptr [rax+rax+00000000h]\nloc_14E0:\nadd ebx, 1\ncmp r12d, ebx\njl short loc_14F2\nmov eax, ebx\nimul eax, ebx\ncmp r12d, eax\njge short loc_1488\nloc_14F2:\ncmp r8d, edx\njg short loc_1540\nloc_14F7:\nadd ebp, 1\ncmp r13d, ebp\njl short loc_150D\nmov eax, ebp\nimul eax, ebp\ncmp r13d, eax\njge loc_146B\nloc_150D:\nmov ebp, ecx\nmov ebx, esi\nmov r13d, r9d\njmp loc_1444\nloc_1520:\ncmp edx, edi\njle short loc_14E0\nlea edx, [rdi+1]\njmp short loc_14E0\nloc_1530:\ncmp r8d, r12d\njle short loc_14F7\nmov r8d, r12d\nloc_1538:\nadd r8d, 1\njmp short loc_14F7\nloc_1540:\nmov eax, 1\nmov edi, r12d\nmov r8d, r12d\nmov ebx, 1\nsub edi, eax\ncmp edi, 3\njle short loc_15B4\nloc_1557:\nmov [rsp+68h+var_44], r9d\nmov [rsp+68h+var_48], r8d\nmov [rsp+68h+var_4C], esi\nmov [rsp+68h+var_50], ecx\nmov [rsp+68h+var_54], edi\ncall func0_part_0\nmov r8d, [rsp+68h+var_48]\nmov edi, [rsp+68h+var_54]\nmov ecx, [rsp+68h+var_50]\nmov esi, [rsp+68h+var_4C]\ncmp r8d, eax\nmov r9d, [rsp+68h+var_44]\njg loc_19DF\nnop dword ptr [rax+00000000h]\nloc_1598:\nadd ebx, 1\ncmp r12d, ebx\njl short loc_1538\nmov eax, ebx\nimul eax, ebx\ncmp r12d, eax\njl short loc_1538\nmov edi, r12d\nsub edi, eax\ncmp edi, 3\njg short loc_1557\nloc_15B4:\ncmp r8d, edi\njle short loc_1598\nlea r8d, [rdi+1]\njmp short loc_1598\nloc_15C0:\ncmp edx, ebx\njge loc_132E\nmov ebx, edx\nloc_15CA:\nadd ebx, 1\njmp loc_132E\nloc_15D2:\nmov ebx, r15d\nmov [rsp+68h+var_60], ebp\nmov r15d, 1\nmov r12d, r14d\nmov [rsp+68h+var_54], r13d\nmov esi, r15d\nmov eax, 1\nmov r15d, edx\nmov edx, esi\nloc_15F4:\nmov ebp, r15d\nsub ebp, eax\ncmp ebp, 3\njle loc_1780\nmov r14d, 1\nmov r8d, ebx\nmov r13d, ebp\nmov eax, 1\nmov ebx, r14d\nloc_1616:\nmov r14d, ebp\nsub r14d, eax\ncmp r14d, 3\njle loc_16F0\nmov esi, r14d\nmov eax, 1\nmov ecx, 1\nloc_1633:\nmov edi, r14d\nsub edi, eax\ncmp edi, 3\njle loc_16E0\nmov [rsp+68h+var_40], edx\nmov [rsp+68h+var_44], r8d\nmov [rsp+68h+var_48], ecx\nmov [rsp+68h+var_4C], esi\nmov [rsp+68h+var_50], edi\ncall func0_part_0\nmov esi, [rsp+68h+var_4C]\nmov edi, [rsp+68h+var_50]\nmov ecx, [rsp+68h+var_48]\nmov r8d, [rsp+68h+var_44]\ncmp esi, eax\nmov edx, [rsp+68h+var_40]\njg loc_1950\nnop dword ptr [rax+rax+00000000h]\nloc_1680:\nadd ecx, 1\ncmp r14d, ecx\njl short loc_1692\nmov eax, ecx\nimul eax, ecx\ncmp r14d, eax\njge short loc_1633\nloc_1692:\ncmp esi, r13d\njl short loc_1700\nloc_1697:\nadd ebx, 1\ncmp ebp, ebx\njl short loc_16AB\nmov eax, ebx\nimul eax, ebx\ncmp ebp, eax\njge loc_1616\nloc_16AB:\nmov ebx, r8d\ncmp r8d, r13d\njg loc_1794\nloc_16B7:\nadd edx, 1\ncmp r15d, edx\njl short loc_16CD\nmov eax, edx\nimul eax, edx\ncmp r15d, eax\njge loc_15F4\nloc_16CD:\nmov ebp, [rsp+68h+var_60]\nmov r13d, [rsp+68h+var_54]\nmov r14d, r12d\njmp loc_15CA\nloc_16E0:\ncmp esi, edi\njle short loc_1680\nlea esi, [rdi+1]\njmp short loc_1680\nloc_16F0:\ncmp r14d, r13d\njge short loc_1697\nmov ecx, r14d\nloc_16F8:\nlea r13d, [rcx+1]\njmp short loc_1697\nloc_1700:\nmov eax, 1\nmov edi, r14d\nmov ecx, r14d\nmov r13d, 1\nsub edi, eax\ncmp edi, 3\njle short loc_176F\nloc_1718:\nmov [rsp+68h+var_44], edx\nmov [rsp+68h+var_48], ecx\nmov [rsp+68h+var_4C], r8d\nmov [rsp+68h+var_50], edi\ncall func0_part_0\nmov ecx, [rsp+68h+var_48]\nmov edi, [rsp+68h+var_50]\nmov r8d, [rsp+68h+var_4C]\nmov edx, [rsp+68h+var_44]\ncmp ecx, eax\njg loc_197F\nnop word ptr [rax+rax+00000000h]\nloc_1750:\nadd r13d, 1\ncmp r14d, r13d\njl short loc_16F8\nmov eax, r13d\nimul eax, r13d\ncmp r14d, eax\njl short loc_16F8\nmov edi, r14d\nsub edi, eax\ncmp edi, 3\njg short loc_1718\nloc_176F:\ncmp ecx, edi\njle short loc_1750\nlea ecx, [rdi+1]\njmp short loc_1750\nloc_1780:\ncmp ebx, ebp\njle loc_16B7\nmov r8d, ebp\nloc_178B:\nlea ebx, [r8+1]\njmp loc_16B7\nloc_1794:\nmov [rsp+68h+var_48], edx\nmov r13d, 1\nmov eax, 1\nmov [rsp+68h+var_50], r12d\nmov r12d, r13d\nmov [rsp+68h+var_4C], r15d\nmov r15d, ebp\nloc_17B3:\nmov ebx, r15d\nsub ebx, eax\ncmp ebx, 3\njle loc_1850\nmov ecx, ebx\nmov eax, 1\nmov r14d, 1\nloc_17CE:\nmov r13d, ebx\nsub r13d, eax\ncmp r13d, 3\njle short loc_1840\nmov edi, r13d\nmov [rsp+68h+var_44], ecx\ncall func0_part_0\nmov ecx, [rsp+68h+var_44]\ncmp ecx, eax\njg loc_190A\nnop word ptr [rax+rax+00h]\nloc_17F8:\nadd r14d, 1\ncmp ebx, r14d\njl short loc_180C\nmov eax, r14d\nimul eax, r14d\ncmp ebx, eax\njge short loc_17CE\nloc_180C:\ncmp ebp, ecx\njg short loc_186B\nloc_1810:\nadd r12d, 1\ncmp r15d, r12d\njl short loc_1825\nmov eax, r12d\nimul eax, r12d\ncmp r15d, eax\njge short loc_17B3\nloc_1825:\nmov r12d, [rsp+68h+var_50]\nmov r15d, [rsp+68h+var_4C]\nmov r8d, ebp\nmov edx, [rsp+68h+var_48]\njmp loc_178B\nloc_1840:\ncmp ecx, r13d\njle short loc_17F8\nlea ecx, [r13+1]\njmp short loc_17F8\nloc_1850:\ncmp ebp, ebx\njle short loc_1810\nmov ebp, ebx\nloc_1856:\nadd ebp, 1\njmp short loc_1810\nloc_185B:\ncmp esi, ebp\njge loc_1358\nmov r15d, esi\njmp loc_1B77\nloc_186B:\nmov eax, 1\nmov r14d, ebx\nmov ebp, ebx\nmov r13d, 1\nsub r14d, eax\ncmp r14d, 3\njle short loc_18B0\nloc_1884:\nmov edi, r14d\ncall func0_part_0\ncmp eax, ebp\njl short loc_18BB\nloc_1890:\nadd r13d, 1\ncmp ebx, r13d\njl short loc_1856\nmov eax, r13d\nimul eax, r13d\ncmp ebx, eax\njl short loc_1856\nmov r14d, ebx\nsub r14d, eax\ncmp r14d, 3\njg short loc_1884\nloc_18B0:\ncmp r14d, ebp\njge short loc_1890\nlea ebp, [r14+1]\njmp short loc_1890\nloc_18BB:\nmov edi, r14d\nmov [rsp+68h+var_44], eax\ncall func0_part_0\nmov r14d, [rsp+68h+var_44]\nlea ebp, [r14+1]\njmp short loc_1890\nloc_18D2:\nmov [rsp+68h+var_44], ecx\nmov [rsp+68h+var_48], esi\nmov [rsp+68h+var_4C], edx\nmov [rsp+68h+var_50], r8d\nmov [rsp+68h+var_54], eax\ncall func0_part_0\nmov edi, [rsp+68h+var_54]\nmov ecx, [rsp+68h+var_44]\nmov esi, [rsp+68h+var_48]\nmov edx, [rsp+68h+var_4C]\nmov r8d, [rsp+68h+var_50]\nlea r9d, [rdi+1]\njmp loc_1410\nloc_190A:\nmov edi, r13d\nmov [rsp+68h+var_44], eax\ncall func0_part_0\nmov r13d, [rsp+68h+var_44]\nlea ecx, [r13+1]\njmp loc_17F8\nloc_1924:\nmov [rsp+68h+var_54], eax\ncall func0_part_0\nmov edi, [rsp+68h+var_54]\nmov ecx, [rsp+68h+var_40]\nmov esi, [rsp+68h+var_44]\nmov edx, [rsp+68h+var_48]\nmov r8d, [rsp+68h+var_4C]\nmov r9d, [rsp+68h+var_50]\nlea r10d, [rdi+1]\njmp loc_12D0\nloc_1950:\nmov [rsp+68h+var_44], edx\nmov [rsp+68h+var_48], r8d\nmov [rsp+68h+var_4C], ecx\nmov [rsp+68h+var_50], eax\ncall func0_part_0\nmov edi, [rsp+68h+var_50]\nmov edx, [rsp+68h+var_44]\nmov r8d, [rsp+68h+var_48]\nmov ecx, [rsp+68h+var_4C]\nlea esi, [rdi+1]\njmp loc_1680\nloc_197F:\nmov [rsp+68h+var_48], edx\nmov [rsp+68h+var_4C], r8d\nmov [rsp+68h+var_50], eax\ncall func0_part_0\nmov edi, [rsp+68h+var_50]\nmov edx, [rsp+68h+var_48]\nmov r8d, [rsp+68h+var_4C]\nlea ecx, [rdi+1]\njmp loc_1750\nloc_19A6:\nmov [rsp+68h+var_44], r9d\nmov [rsp+68h+var_48], r8d\nmov [rsp+68h+var_4C], esi\nmov [rsp+68h+var_50], ecx\nmov [rsp+68h+var_54], eax\ncall func0_part_0\nmov edi, [rsp+68h+var_54]\nmov r9d, [rsp+68h+var_44]\nmov r8d, [rsp+68h+var_48]\nmov esi, [rsp+68h+var_4C]\nmov ecx, [rsp+68h+var_50]\nlea edx, [rdi+1]\njmp loc_14E0\nloc_19DF:\nmov [rsp+68h+var_48], r9d\nmov [rsp+68h+var_4C], esi\nmov [rsp+68h+var_50], ecx\nmov [rsp+68h+var_54], eax\ncall func0_part_0\nmov edi, [rsp+68h+var_54]\nmov r9d, [rsp+68h+var_48]\nmov esi, [rsp+68h+var_4C]\nmov ecx, [rsp+68h+var_50]\nlea r8d, [rdi+1]\njmp loc_1598\nloc_1A0F:\nmov [rsp+68h+var_44], r13d\nmov ebx, 1\nmov edx, 1\nmov [rsp+68h+var_40], r12d\nmov ebp, ebx\nmov r12d, r14d\nmov ebx, r14d\nloc_1A2B:\nmov r13d, ebx\nsub r13d, edx\ncmp r13d, 3\njle loc_1D3C\nmov [rsp+68h+var_58], r12d\nmov edx, 1\nmov r14d, 1\nmov [rsp+68h+var_60], ebx\nmov ebx, r13d\nmov [rsp+68h+var_5C], ebp\nmov ebp, r13d\nloc_1A59:\nmov r13d, ebp\nsub r13d, edx\ncmp r13d, 3\njle loc_1C10\nmov r15d, 1\nmov esi, r14d\nmov r12d, r13d\nmov r14d, ebp\nmov eax, 1\nmov ebp, ebx\nmov ebx, r15d\nloc_1A82:\nmov r15d, r13d\nsub r15d, eax\ncmp r15d, 3\njle loc_1B90\nmov ecx, r15d\nmov eax, 1\nmov edx, 1\nloc_1A9F:\nmov edi, r15d\nsub edi, eax\ncmp edi, 3\njle loc_1B80\nmov [rsp+68h+var_48], edx\nmov [rsp+68h+var_4C], esi\nmov [rsp+68h+var_50], ecx\nmov [rsp+68h+var_54], edi\ncall func0_part_0\nmov ecx, [rsp+68h+var_50]\nmov edi, [rsp+68h+var_54]\nmov esi, [rsp+68h+var_4C]\nmov edx, [rsp+68h+var_48]\ncmp ecx, eax\njg loc_1D7E\nnop word ptr [rax+rax+00h]\nloc_1AE0:\nadd edx, 1\ncmp r15d, edx\njl short loc_1AF2\nmov eax, edx\nimul eax, edx\ncmp r15d, eax\njge short loc_1A9F\nloc_1AF2:\ncmp ecx, r12d\njl loc_1BA8\nloc_1AFB:\nadd ebx, 1\ncmp r13d, ebx\njl short loc_1B11\nmov eax, ebx\nimul eax, ebx\ncmp r13d, eax\njge loc_1A82\nloc_1B11:\nmov ebx, ebp\nmov ebp, r14d\nmov r14d, esi\ncmp ebx, r12d\njg loc_1C24\nloc_1B22:\nadd r14d, 1\ncmp ebp, r14d\njl short loc_1B3A\nmov edx, r14d\nimul edx, r14d\ncmp ebp, edx\njge loc_1A59\nloc_1B3A:\nmov r12d, [rsp+68h+var_58]\nmov r15d, ebx\nmov r13d, ebp\nmov ebx, [rsp+68h+var_60]\nmov ebp, [rsp+68h+var_5C]\ncmp r12d, r15d\njg loc_1DC0\nloc_1B56:\nadd ebp, 1\ncmp ebx, ebp\njl short loc_1B6A\nmov edx, ebp\nimul edx, ebp\ncmp ebx, edx\njge loc_1A2B\nloc_1B6A:\nmov r15d, r12d\nmov r13d, [rsp+68h+var_44]\nmov r12d, [rsp+68h+var_40]\nloc_1B77:\nlea ebp, [r15+1]\njmp loc_1358\nloc_1B80:\ncmp ecx, edi\njle loc_1AE0\nlea ecx, [rdi+1]\njmp loc_1AE0\nloc_1B90:\ncmp r15d, r12d\njge loc_1AFB\nmov edx, r15d\nloc_1B9C:\nlea r12d, [rdx+1]\njmp loc_1AFB\nloc_1BA8:\nmov eax, 1\nmov edi, r15d\nmov edx, r15d\nmov r12d, 1\nsub edi, eax\ncmp edi, 3\njle short loc_1C07\nloc_1BC0:\nmov [rsp+68h+var_4C], esi\nmov [rsp+68h+var_50], edx\nmov [rsp+68h+var_54], edi\ncall func0_part_0\nmov edx, [rsp+68h+var_50]\nmov edi, [rsp+68h+var_54]\nmov esi, [rsp+68h+var_4C]\ncmp edx, eax\njg loc_1DA3\nnop dword ptr [rax]\nloc_1BE8:\nadd r12d, 1\ncmp r15d, r12d\njl short loc_1B9C\nmov eax, r12d\nimul eax, r12d\ncmp r15d, eax\njl short loc_1B9C\nmov edi, r15d\nsub edi, eax\ncmp edi, 3\njg short loc_1BC0\nloc_1C07:\ncmp edx, edi\njle short loc_1BE8\nlea edx, [rdi+1]\njmp short loc_1BE8\nloc_1C10:\ncmp ebx, r13d\njle loc_1B22\nmov ebx, r13d\nloc_1C1C:\nadd ebx, 1\njmp loc_1B22\nloc_1C24:\nmov [rsp+68h+var_50], esi\nmov r12d, 1\nmov eax, 1\nmov r14d, r13d\nmov [rsp+68h+var_54], ebp\nmov ebx, r12d\nmov ebp, r13d\nloc_1C40:\nmov r15d, r14d\nsub r15d, eax\ncmp r15d, 3\njle loc_1CD8\nmov edx, r15d\nmov eax, 1\nmov r12d, 1\nloc_1C5E:\nmov r13d, r15d\nsub r13d, eax\ncmp r13d, 3\njle short loc_1CC8\nmov edi, r13d\nmov [rsp+68h+var_4C], edx\ncall func0_part_0\nmov edx, [rsp+68h+var_4C]\ncmp edx, eax\njg loc_1D4D\nnop word ptr [rax+rax+00h]\nloc_1C88:\nadd r12d, 1\ncmp r15d, r12d\njl short loc_1C9D\nmov eax, r12d\nimul eax, r12d\ncmp r15d, eax\njge short loc_1C5E\nloc_1C9D:\ncmp ebp, edx\njg short loc_1CE5\nloc_1CA1:\nadd ebx, 1\ncmp r14d, ebx\njl short loc_1CB3\nmov eax, ebx\nimul eax, ebx\ncmp r14d, eax\njge short loc_1C40\nloc_1CB3:\nmov ebx, ebp\nmov r14d, [rsp+68h+var_50]\nmov ebp, [rsp+68h+var_54]\njmp loc_1C1C\nloc_1CC8:\ncmp edx, r13d\njle short loc_1C88\nlea edx, [r13+1]\njmp short loc_1C88\nloc_1CD8:\ncmp ebp, r15d\njle short loc_1CA1\nmov ebp, r15d\nloc_1CE0:\nadd ebp, 1\njmp short loc_1CA1\nloc_1CE5:\nmov eax, 1\nmov r13d, r15d\nmov ebp, r15d\nmov r12d, 1\nsub r13d, eax\ncmp r13d, 3\njle short loc_1D31\nloc_1CFF:\nmov edi, r13d\ncall func0_part_0\ncmp eax, ebp\njl short loc_1D67\nnop dword ptr [rax+rax+00h]\nloc_1D10:\nadd r12d, 1\ncmp r15d, r12d\njl short loc_1CE0\nmov eax, r12d\nimul eax, r12d\ncmp r15d, eax\njl short loc_1CE0\nmov r13d, r15d\nsub r13d, eax\ncmp r13d, 3\njg short loc_1CFF\nloc_1D31:\ncmp r13d, ebp\njge short loc_1D10\nlea ebp, [r13+1]\njmp short loc_1D10\nloc_1D3C:\ncmp r12d, r13d\njle loc_1B56\nmov r12d, r13d\njmp loc_1E58\nloc_1D4D:\nmov edi, r13d\nmov [rsp+68h+var_4C], eax\ncall func0_part_0\nmov r13d, [rsp+68h+var_4C]\nlea edx, [r13+1]\njmp loc_1C88\nloc_1D67:\nmov edi, r13d\nmov [rsp+68h+var_4C], eax\ncall func0_part_0\nmov r13d, [rsp+68h+var_4C]\nlea ebp, [r13+1]\njmp short loc_1D10\nloc_1D7E:\nmov [rsp+68h+var_4C], edx\nmov [rsp+68h+var_50], esi\nmov [rsp+68h+var_54], eax\ncall func0_part_0\nmov edi, [rsp+68h+var_54]\nmov edx, [rsp+68h+var_4C]\nmov esi, [rsp+68h+var_50]\nlea ecx, [rdi+1]\njmp loc_1AE0\nloc_1DA3:\nmov [rsp+68h+var_50], esi\nmov [rsp+68h+var_54], eax\ncall func0_part_0\nmov edi, [rsp+68h+var_54]\nmov esi, [rsp+68h+var_50]\nlea edx, [rdi+1]\njmp loc_1BE8\nloc_1DC0:\nmov edx, 1\nmov [rsp+68h+var_5C], ebx\nmov eax, 1\nmov ebx, r13d\nmov [rsp+68h+var_58], ebp\nmov r12d, edx\nmov ebp, r13d\nloc_1DDB:\nmov r15d, ebx\nsub r15d, eax\ncmp r15d, 3\njle loc_1E8A\nmov edx, r15d\nmov eax, 1\nmov r14d, 1\nloc_1DF9:\nmov r13d, r15d\nsub r13d, eax\ncmp r13d, 3\njle short loc_1E68\nmov edi, r13d\nmov [rsp+68h+var_60], edx\ncall func0_part_0\nmov edx, [rsp+68h+var_60]\ncmp eax, edx\njl short loc_1E73\nnop dword ptr [rax+00000000h]\nloc_1E20:\nadd r14d, 1\ncmp r15d, r14d\njl short loc_1E35\nmov eax, r14d\nimul eax, r14d\ncmp r15d, eax\njge short loc_1DF9\nloc_1E35:\ncmp edx, ebp\njl short loc_1E95\nloc_1E39:\nadd r12d, 1\ncmp ebx, r12d\njl short loc_1E4D\nmov eax, r12d\nimul eax, r12d\ncmp ebx, eax\njge short loc_1DDB\nloc_1E4D:\nmov r12d, ebp\nmov ebx, [rsp+68h+var_5C]\nmov ebp, [rsp+68h+var_58]\nloc_1E58:\nadd r12d, 1\njmp loc_1B56\nloc_1E68:\ncmp r13d, edx\njge short loc_1E20\nlea edx, [r13+1]\njmp short loc_1E20\nloc_1E73:\nmov edi, r13d\nmov [rsp+68h+var_60], eax\ncall func0_part_0\nmov r13d, [rsp+68h+var_60]\nlea edx, [r13+1]\njmp short loc_1E20\nloc_1E8A:\ncmp r15d, ebp\njge short loc_1E39\nlea ebp, [r15+1]\njmp short loc_1E39\nloc_1E95:\nmov edi, r15d\ncall func0_part_0\nmov r15d, eax\nlea ebp, [r15+1]\njmp short loc_1E39", + "ida_pseudo": "__int64 __fastcall func0_part_0(int a1, __int64 a2, __int64 a3, __int64 a4, __int64 a5, __int64 a6)\n{\n unsigned int v6; // ebp\n int v7; // eax\n int v8; // r13d\n int v9; // r12d\n __int64 v10; // rsi\n int v11; // ebx\n int v12; // eax\n unsigned int v13; // r13d\n unsigned int v14; // ebp\n int v15; // r14d\n int v16; // edx\n int v17; // eax\n unsigned int v18; // ebx\n int v19; // r15d\n int v20; // r12d\n int v21; // eax\n __int64 v22; // rdx\n int v23; // r10d\n int v24; // eax\n int v25; // edi\n int v26; // eax\n __int64 v27; // rdi\n __int64 v29; // r9\n __int64 v30; // rdi\n int v31; // eax\n __int64 v32; // r8\n int v33; // eax\n int v34; // ebp\n int v35; // r13d\n int v36; // r12d\n __int64 v37; // rdx\n int v38; // eax\n int v39; // ebx\n __int64 v40; // rdi\n int v41; // eax\n __int64 v42; // rdi\n __int64 v43; // r8\n int v44; // ebx\n __int64 v45; // rdi\n int v46; // eax\n int v47; // ebx\n int v48; // r12d\n int v49; // eax\n __int64 v50; // rdx\n int v51; // ebp\n int v52; // r13d\n int v53; // eax\n int v54; // ebx\n int v55; // r14d\n int v56; // eax\n __int64 v57; // rdi\n int v58; // eax\n __int64 v59; // rdi\n int v60; // r13d\n __int64 v61; // rdi\n int v62; // eax\n int v63; // eax\n int v64; // r12d\n int v65; // r15d\n int v66; // ebx\n int v67; // eax\n int v68; // r14d\n unsigned int v69; // r13d\n int v70; // eax\n int v71; // ebp\n int v72; // r15d\n int v73; // r13d\n unsigned int v74; // r14d\n int v75; // eax\n int v76; // eax\n int v77; // edx\n int v78; // ebp\n int v79; // r12d\n int v80; // ebx\n int v81; // r13d\n int v82; // edx\n unsigned int v83; // r14d\n int v84; // ebx\n int v85; // ebp\n int v86; // r13d\n int v87; // r12d\n int v88; // r14d\n int v89; // eax\n int v90; // ebp\n int v91; // ebx\n int v92; // r15d\n int v93; // eax\n __int64 v94; // rdx\n __int64 v95; // rdi\n int v96; // eax\n __int64 v97; // rdi\n int v98; // r15d\n int v99; // r13d\n __int64 v100; // rdx\n int v101; // r12d\n __int64 v102; // rdi\n int v103; // eax\n int v104; // ebx\n int v105; // eax\n int v106; // r14d\n int v107; // ebx\n int v108; // ebp\n int v109; // r15d\n __int64 v110; // rdx\n int v111; // eax\n int v112; // r12d\n unsigned int v113; // r13d\n int v114; // eax\n int v115; // ebp\n int v116; // r12d\n unsigned int v117; // r13d\n int v118; // eax\n int v119; // eax\n int v120; // r12d\n int v121; // eax\n int v122; // ebx\n int v123; // r12d\n int v124; // ebp\n int v125; // r15d\n __int64 v126; // rdx\n int v127; // eax\n int v128; // r14d\n unsigned int v129; // r13d\n int v130; // eax\n int v131; // [rsp+8h] [rbp-60h]\n unsigned int v132; // [rsp+8h] [rbp-60h]\n int v133; // [rsp+8h] [rbp-60h]\n unsigned int v134; // [rsp+8h] [rbp-60h]\n int v135; // [rsp+8h] [rbp-60h]\n int v136; // [rsp+Ch] [rbp-5Ch]\n int v137; // [rsp+Ch] [rbp-5Ch]\n int v138; // [rsp+Ch] [rbp-5Ch]\n signed int v139; // [rsp+10h] [rbp-58h]\n int v140; // [rsp+10h] [rbp-58h]\n int v141; // [rsp+10h] [rbp-58h]\n unsigned int v142; // [rsp+14h] [rbp-54h]\n unsigned int v143; // [rsp+14h] [rbp-54h]\n unsigned int v144; // [rsp+14h] [rbp-54h]\n int v145; // [rsp+14h] [rbp-54h]\n int v146; // [rsp+14h] [rbp-54h]\n int v147; // [rsp+14h] [rbp-54h]\n int v148; // [rsp+14h] [rbp-54h]\n unsigned int v149; // [rsp+14h] [rbp-54h]\n int v150; // [rsp+14h] [rbp-54h]\n int v151; // [rsp+14h] [rbp-54h]\n int v152; // [rsp+14h] [rbp-54h]\n unsigned int v153; // [rsp+18h] [rbp-50h]\n unsigned int v154; // [rsp+18h] [rbp-50h]\n unsigned int v155; // [rsp+18h] [rbp-50h]\n unsigned int v156; // [rsp+18h] [rbp-50h]\n unsigned int v157; // [rsp+18h] [rbp-50h]\n int v158; // [rsp+18h] [rbp-50h]\n int v159; // [rsp+18h] [rbp-50h]\n int v160; // [rsp+18h] [rbp-50h]\n unsigned int v161; // [rsp+18h] [rbp-50h]\n unsigned int v162; // [rsp+18h] [rbp-50h]\n unsigned int v163; // [rsp+1Ch] [rbp-4Ch]\n unsigned int v164; // [rsp+1Ch] [rbp-4Ch]\n unsigned int v165; // [rsp+1Ch] [rbp-4Ch]\n int v166; // [rsp+1Ch] [rbp-4Ch]\n unsigned int v167; // [rsp+1Ch] [rbp-4Ch]\n int v168; // [rsp+1Ch] [rbp-4Ch]\n int v169; // [rsp+1Ch] [rbp-4Ch]\n unsigned int v170; // [rsp+20h] [rbp-48h]\n unsigned int v171; // [rsp+20h] [rbp-48h]\n unsigned int v172; // [rsp+20h] [rbp-48h]\n unsigned int v173; // [rsp+20h] [rbp-48h]\n unsigned int v174; // [rsp+20h] [rbp-48h]\n int v175; // [rsp+20h] [rbp-48h]\n unsigned int v176; // [rsp+20h] [rbp-48h]\n unsigned int v177; // [rsp+24h] [rbp-44h]\n unsigned int v178; // [rsp+24h] [rbp-44h]\n unsigned int v179; // [rsp+24h] [rbp-44h]\n unsigned int v180; // [rsp+24h] [rbp-44h]\n unsigned int v181; // [rsp+24h] [rbp-44h]\n unsigned int v182; // [rsp+24h] [rbp-44h]\n int v183; // [rsp+24h] [rbp-44h]\n int v184; // [rsp+24h] [rbp-44h]\n int v185; // [rsp+24h] [rbp-44h]\n unsigned int v186; // [rsp+28h] [rbp-40h]\n unsigned int v187; // [rsp+28h] [rbp-40h]\n unsigned int v188; // [rsp+28h] [rbp-40h]\n unsigned int v189; // [rsp+28h] [rbp-40h]\n int v190; // [rsp+28h] [rbp-40h]\n int v191; // [rsp+2Ch] [rbp-3Ch]\n\n v6 = a1;\n if ( a1 > 0 )\n {\n v7 = 1;\n v8 = 1;\n v9 = a1;\n while ( 1 )\n {\n v10 = (unsigned int)(v9 - v7);\n if ( (int)v10 > 3 )\n break;\n if ( (int)v10 < (int)v6 )\n {\n v72 = v9 - v7;\n goto LABEL_155;\n }\nLABEL_26:\n if ( v9 >= ++v8 )\n {\n v7 = v8 * v8;\n if ( v8 * v8 <= v9 )\n continue;\n }\n return v6;\n }\n v136 = v8;\n v11 = v9 - v7;\n v12 = 1;\n v139 = v6;\n v13 = v9;\n v14 = 1;\n v15 = v10;\n do\n {\n v16 = v15 - v12;\n if ( v15 - v12 > 3 )\n {\n v131 = v11;\n v17 = 1;\n a5 = (unsigned int)v16;\n v18 = 1;\n v19 = v16;\n while ( 1 )\n {\n v20 = v19 - v17;\n if ( v19 - v17 > 3 )\n break;\n if ( v20 < (int)a5 )\n {\n LODWORD(v32) = v19 - v17;\n goto LABEL_44;\n }\nLABEL_20:\n if ( v19 >= (int)++v18 )\n {\n v17 = v18 * v18;\n if ( v19 >= (int)(v18 * v18) )\n continue;\n }\n v11 = v131;\n if ( (int)a5 >= v131 )\n goto LABEL_23;\n v47 = v19;\n v132 = v14;\n v48 = v15;\n v144 = v13;\n v10 = 1LL;\n v49 = 1;\n v50 = 1LL;\n while ( 1 )\n {\n v51 = v19 - v49;\n if ( v19 - v49 > 3 )\n break;\n if ( v47 > v51 )\n {\n a5 = (unsigned int)v51;\n goto LABEL_105;\n }\nLABEL_87:\n v50 = (unsigned int)(v50 + 1);\n if ( v19 >= (int)v50 )\n {\n v49 = v50 * v50;\n if ( v19 >= (int)v50 * (int)v50 )\n continue;\n }\n v14 = v132;\n v13 = v144;\n v15 = v48;\nLABEL_72:\n v11 = v47 + 1;\n goto LABEL_23;\n }\n a5 = (unsigned int)v47;\n v52 = v19 - v49;\n v53 = 1;\n v54 = 1;\n while ( 2 )\n {\n v55 = v51 - v53;\n if ( v51 - v53 <= 3 )\n {\n if ( v55 >= v52 )\n goto LABEL_84;\n a4 = (unsigned int)v55;\n }\n else\n {\n v10 = (unsigned int)v55;\n v56 = 1;\n a4 = 1LL;\n do\n {\n v57 = (unsigned int)(v55 - v56);\n if ( (int)v57 <= 3 )\n {\n if ( (int)v10 > (int)v57 )\n v10 = (unsigned int)(v57 + 1);\n }\n else\n {\n v189 = v50;\n v180 = a5;\n v173 = a4;\n v157 = v55 - v56;\n v58 = func0_part_0(v57, v10, v50, a4, a5, a6);\n v10 = (unsigned int)v10;\n v59 = v157;\n LODWORD(a4) = v173;\n a5 = v180;\n v50 = v189;\n if ( (int)v10 > v58 )\n {\n v159 = v58;\n func0_part_0(v59, (unsigned int)v10, v189, v173, v180, a6);\n v50 = v189;\n a5 = v180;\n LODWORD(a4) = v173;\n v10 = (unsigned int)(v159 + 1);\n }\n }\n a4 = (unsigned int)(a4 + 1);\n if ( v55 < (int)a4 )\n break;\n v56 = a4 * a4;\n }\n while ( v55 >= (int)a4 * (int)a4 );\n if ( (int)v10 >= v52 )\n {\nLABEL_84:\n if ( v51 >= ++v54 )\n {\n v53 = v54 * v54;\n if ( v51 >= v54 * v54 )\n continue;\n }\n v47 = a5;\n if ( (int)a5 <= v52 )\n goto LABEL_87;\n v175 = v50;\n v63 = 1;\n v158 = v48;\n v64 = 1;\n v166 = v19;\n v65 = v51;\n while ( 2 )\n {\n v66 = v65 - v63;\n if ( v65 - v63 <= 3 )\n {\n if ( v51 <= v66 )\n goto LABEL_115;\n v71 = v65 - v63;\n }\n else\n {\n a4 = (unsigned int)v66;\n v67 = 1;\n v68 = 1;\n do\n {\n v69 = v66 - v67;\n if ( v66 - v67 <= 3 )\n {\n if ( (int)a4 > (int)v69 )\n a4 = v69 + 1;\n }\n else\n {\n v182 = a4;\n v70 = func0_part_0(v69, v10, v50, a4, a5, a6);\n a4 = v182;\n if ( (int)v182 > v70 )\n {\n v184 = v70;\n func0_part_0(v69, v10, v50, a4, a5, a6);\n a4 = (unsigned int)(v184 + 1);\n }\n }\n if ( v66 < ++v68 )\n break;\n v67 = v68 * v68;\n }\n while ( v66 >= v68 * v68 );\n if ( v51 <= (int)a4 )\n {\nLABEL_115:\n if ( v65 < ++v64 || (v63 = v64 * v64, v65 < v64 * v64) )\n {\n v48 = v158;\n v19 = v166;\n a5 = (unsigned int)v51;\n LODWORD(v50) = v175;\nLABEL_105:\n v47 = a5 + 1;\n goto LABEL_87;\n }\n continue;\n }\n v71 = v66;\n v73 = 1;\n v74 = v66 - 1;\n if ( v66 - 1 > 3 )\n {\nLABEL_126:\n v75 = func0_part_0(v74, v10, v50, a4, a5, a6);\n if ( v75 < v71 )\n {\n v183 = v75;\n func0_part_0(v74, v10, v50, a4, a5, a6);\n v71 = v183 + 1;\n }\n goto LABEL_128;\n }\n while ( 1 )\n {\n if ( (int)v74 < v71 )\n v71 = v74 + 1;\nLABEL_128:\n if ( v66 < ++v73 )\n break;\n v76 = v73 * v73;\n if ( v66 < v73 * v73 )\n break;\n v74 = v66 - v76;\n if ( v66 - v76 > 3 )\n goto LABEL_126;\n }\n }\n break;\n }\n v51 = v71 + 1;\n goto LABEL_115;\n }\n a4 = (unsigned int)v55;\n v60 = 1;\n v61 = (unsigned int)(v55 - 1);\n if ( (int)v61 > 3 )\n {\nLABEL_96:\n v181 = v50;\n v174 = a4;\n v165 = a5;\n v62 = func0_part_0(v61, v10, v50, a4, a5, a6);\n a4 = v174;\n a5 = v165;\n v50 = v181;\n if ( (int)v174 > v62 )\n {\n v160 = v62;\n func0_part_0((unsigned int)v61, v10, v181, v174, v165, a6);\n v50 = v181;\n a5 = v165;\n a4 = (unsigned int)(v160 + 1);\n }\n goto LABEL_98;\n }\n while ( 1 )\n {\n if ( (int)a4 > (int)v61 )\n a4 = (unsigned int)(v61 + 1);\nLABEL_98:\n if ( v55 < ++v60 || v55 < v60 * v60 )\n break;\n v61 = (unsigned int)(v55 - v60 * v60);\n if ( (int)v61 > 3 )\n goto LABEL_96;\n }\n }\n break;\n }\n v52 = a4 + 1;\n goto LABEL_84;\n }\n a6 = (unsigned int)v20;\n v21 = 1;\n v10 = 1LL;\n while ( 1 )\n {\n v22 = (unsigned int)(v20 - v21);\n if ( (int)v22 <= 3 )\n {\n if ( (int)a6 <= (int)v22 )\n goto LABEL_17;\n LODWORD(v29) = v20 - v21;\n }\n else\n {\n v23 = v20 - v21;\n v24 = 1;\n LODWORD(a4) = 1;\n do\n {\n v25 = v22 - v24;\n if ( (int)v22 - v24 <= 3 )\n {\n if ( v25 < v23 )\n v23 = v25 + 1;\n }\n else\n {\n v191 = v23;\n v186 = a4;\n v170 = v22;\n v163 = a5;\n v153 = a6;\n v142 = v22 - v24;\n v26 = ((__int64 (*)(void))func0_part_0)();\n v23 = v191;\n v27 = v142;\n a6 = v153;\n a5 = v163;\n v22 = v170;\n v10 = (unsigned int)v10;\n LODWORD(a4) = v186;\n if ( v26 < v191 )\n {\n v146 = v26;\n func0_part_0(v27, (unsigned int)v10, v170, v186, v163, v153);\n LODWORD(a4) = v186;\n v10 = (unsigned int)v10;\n v22 = v170;\n a5 = v163;\n a6 = v153;\n v23 = v146 + 1;\n }\n }\n a4 = (unsigned int)(a4 + 1);\n if ( (int)v22 < (int)a4 )\n break;\n v24 = a4 * a4;\n }\n while ( (int)v22 >= (int)a4 * (int)a4 );\n if ( (int)a6 <= v23 )\n goto LABEL_17;\n v29 = (unsigned int)v22;\n a4 = 1LL;\n v30 = (unsigned int)(v22 - 1);\n if ( (int)v30 > 3 )\n {\nLABEL_35:\n v187 = a4;\n v177 = v29;\n v164 = v22;\n v154 = a5;\n v31 = func0_part_0(v30, v10, v22, a4, a5, v29);\n v29 = v177;\n a5 = v154;\n v22 = v164;\n v10 = (unsigned int)v10;\n LODWORD(a4) = v187;\n if ( (int)v177 > v31 )\n {\n v145 = v31;\n func0_part_0((unsigned int)v30, (unsigned int)v10, v164, v187, v154, v177);\n LODWORD(a4) = v187;\n v10 = (unsigned int)v10;\n v22 = v164;\n a5 = v154;\n v29 = (unsigned int)(v145 + 1);\n }\n goto LABEL_37;\n }\n while ( 1 )\n {\n if ( (int)v29 > (int)v30 )\n v29 = (unsigned int)(v30 + 1);\nLABEL_37:\n a4 = (unsigned int)(a4 + 1);\n if ( (int)v22 < (int)a4 || (int)v22 < (int)a4 * (int)a4 )\n break;\n v30 = (unsigned int)(v22 - a4 * a4);\n if ( (int)v30 > 3 )\n goto LABEL_35;\n }\n }\n a6 = (unsigned int)(v29 + 1);\nLABEL_17:\n v10 = (unsigned int)(v10 + 1);\n if ( v20 >= (int)v10 )\n {\n v21 = v10 * v10;\n if ( v20 >= (int)v10 * (int)v10 )\n continue;\n }\n if ( (int)a6 >= (int)a5 )\n goto LABEL_20;\n a4 = v14;\n v32 = (unsigned int)v20;\n v33 = 1;\n v34 = 1;\n v10 = v18;\n a6 = v13;\n v35 = v20;\n while ( 1 )\n {\n v36 = v35 - v33;\n if ( v35 - v33 <= 3 )\n {\n if ( (int)v32 <= v36 )\n goto LABEL_54;\n LODWORD(v43) = v35 - v33;\n }\n else\n {\n v37 = (unsigned int)v36;\n v38 = 1;\n v39 = 1;\n do\n {\n v40 = (unsigned int)(v36 - v38);\n if ( (int)v40 <= 3 )\n {\n if ( (int)v37 > (int)v40 )\n v37 = (unsigned int)(v40 + 1);\n }\n else\n {\n v188 = a6;\n v178 = v37;\n v171 = v32;\n v155 = a4;\n v143 = v36 - v38;\n v41 = func0_part_0(v40, v10, v37, a4, v32, a6);\n v37 = v178;\n v42 = v143;\n a4 = v155;\n v10 = (unsigned int)v10;\n v32 = v171;\n a6 = v188;\n if ( (int)v178 > v41 )\n {\n v147 = v41;\n func0_part_0(v42, (unsigned int)v10, v178, v155, v171, v188);\n a6 = v188;\n v32 = v171;\n v10 = (unsigned int)v10;\n a4 = v155;\n v37 = (unsigned int)(v147 + 1);\n }\n }\n if ( v36 < ++v39 )\n break;\n v38 = v39 * v39;\n }\n while ( v36 >= v39 * v39 );\n if ( (int)v32 <= (int)v37 )\n goto LABEL_54;\n v43 = (unsigned int)v36;\n v44 = 1;\n v45 = (unsigned int)(v36 - 1);\n if ( (int)v45 > 3 )\n {\nLABEL_63:\n v179 = a6;\n v172 = v43;\n v156 = a4;\n v46 = func0_part_0(v45, v10, v37, a4, v43, a6);\n v43 = v172;\n a4 = v156;\n v10 = (unsigned int)v10;\n a6 = v179;\n if ( (int)v172 > v46 )\n {\n v148 = v46;\n func0_part_0((unsigned int)v45, (unsigned int)v10, v37, v156, v172, v179);\n a6 = v179;\n v10 = (unsigned int)v10;\n a4 = v156;\n v43 = (unsigned int)(v148 + 1);\n }\n goto LABEL_65;\n }\n while ( 1 )\n {\n if ( (int)v43 > (int)v45 )\n v43 = (unsigned int)(v45 + 1);\nLABEL_65:\n if ( v36 < ++v44 || v36 < v44 * v44 )\n break;\n v45 = (unsigned int)(v36 - v44 * v44);\n if ( (int)v45 > 3 )\n goto LABEL_63;\n }\n }\n v32 = (unsigned int)(v43 + 1);\nLABEL_54:\n if ( v35 >= ++v34 )\n {\n v33 = v34 * v34;\n if ( v35 >= v34 * v34 )\n continue;\n }\n v14 = a4;\n v18 = v10;\n v13 = a6;\nLABEL_44:\n a5 = (unsigned int)(v32 + 1);\n goto LABEL_20;\n }\n }\n }\n if ( v16 < v11 )\n {\n v47 = v15 - v12;\n goto LABEL_72;\n }\nLABEL_23:\n if ( v15 < (int)++v14 )\n break;\n v12 = v14 * v14;\n }\n while ( v15 >= (int)(v14 * v14) );\n v6 = v139;\n v9 = v13;\n v8 = v136;\n if ( v11 >= v139 )\n goto LABEL_26;\n v185 = v136;\n v77 = 1;\n v190 = v9;\n v78 = 1;\n v79 = v15;\n v80 = v15;\nLABEL_134:\n v81 = v80 - v77;\n if ( v80 - v77 <= 3 )\n {\n if ( v79 <= v81 )\n goto LABEL_152;\n v120 = v80 - v77;\nLABEL_212:\n v79 = v120 + 1;\n goto LABEL_152;\n }\n v140 = v79;\n v82 = 1;\n v83 = 1;\n v133 = v80;\n v84 = v81;\n v137 = v78;\n v85 = v81;\n while ( 1 )\n {\n v86 = v85 - v82;\n if ( v85 - v82 > 3 )\n break;\n if ( v84 > v86 )\n {\n v104 = v85 - v82;\n goto LABEL_171;\n }\nLABEL_149:\n if ( v85 >= (int)++v83 )\n {\n v82 = v83 * v83;\n if ( v85 >= (int)(v83 * v83) )\n continue;\n }\n v79 = v140;\n v98 = v84;\n v99 = v85;\n v80 = v133;\n v78 = v137;\n if ( v140 > v98 )\n {\n v138 = v133;\n v121 = 1;\n v122 = v99;\n v141 = v78;\n v123 = 1;\n v124 = v99;\n do\n {\n v125 = v122 - v121;\n if ( v122 - v121 <= 3 )\n {\n if ( v125 < v124 )\n v124 = v125 + 1;\n }\n else\n {\n v126 = (unsigned int)v125;\n v127 = 1;\n v128 = 1;\n do\n {\n v129 = v125 - v127;\n if ( v125 - v127 <= 3 )\n {\n if ( (int)v129 < (int)v126 )\n v126 = v129 + 1;\n }\n else\n {\n v134 = v126;\n v130 = func0_part_0(v129, v10, v126, a4, a5, a6);\n v126 = v134;\n if ( v130 < (int)v134 )\n {\n v135 = v130;\n func0_part_0(v129, v10, v126, a4, a5, a6);\n v126 = (unsigned int)(v135 + 1);\n }\n }\n if ( v125 < ++v128 )\n break;\n v127 = v128 * v128;\n }\n while ( v125 >= v128 * v128 );\n if ( (int)v126 < v124 )\n v124 = func0_part_0((unsigned int)v125, v10, v126, a4, a5, a6) + 1;\n }\n if ( v122 < ++v123 )\n break;\n v121 = v123 * v123;\n }\n while ( v122 >= v123 * v123 );\n v120 = v124;\n v80 = v138;\n v78 = v141;\n goto LABEL_212;\n }\nLABEL_152:\n if ( v80 < ++v78 || (v77 = v78 * v78, v80 < v78 * v78) )\n {\n v72 = v79;\n v8 = v185;\n v9 = v190;\nLABEL_155:\n v6 = v72 + 1;\n goto LABEL_26;\n }\n goto LABEL_134;\n }\n v10 = v83;\n v87 = v85 - v82;\n v88 = v85;\n v89 = 1;\n v90 = v84;\n v91 = 1;\n while ( 1 )\n {\n v92 = v86 - v89;\n if ( v86 - v89 <= 3 )\n {\n if ( v92 >= v87 )\n goto LABEL_146;\n LODWORD(v100) = v86 - v89;\n }\n else\n {\n a4 = (unsigned int)v92;\n v93 = 1;\n v94 = 1LL;\n do\n {\n v95 = (unsigned int)(v92 - v93);\n if ( (int)v95 <= 3 )\n {\n if ( (int)a4 > (int)v95 )\n a4 = (unsigned int)(v95 + 1);\n }\n else\n {\n v176 = v94;\n v161 = a4;\n v149 = v92 - v93;\n v96 = func0_part_0(v95, v10, v94, a4, a5, a6);\n a4 = v161;\n v97 = v149;\n v10 = (unsigned int)v10;\n LODWORD(v94) = v176;\n if ( (int)v161 > v96 )\n {\n v151 = v96;\n func0_part_0(v97, (unsigned int)v10, v176, v161, a5, a6);\n LODWORD(v94) = v176;\n v10 = (unsigned int)v10;\n a4 = (unsigned int)(v151 + 1);\n }\n }\n v94 = (unsigned int)(v94 + 1);\n if ( v92 < (int)v94 )\n break;\n v93 = v94 * v94;\n }\n while ( v92 >= (int)v94 * (int)v94 );\n if ( (int)a4 >= v87 )\n goto LABEL_146;\n v100 = (unsigned int)v92;\n v101 = 1;\n v102 = (unsigned int)(v92 - 1);\n if ( (int)v102 > 3 )\n {\nLABEL_162:\n v162 = v100;\n v103 = func0_part_0(v102, v10, v100, a4, a5, a6);\n v100 = v162;\n v10 = (unsigned int)v10;\n if ( (int)v162 > v103 )\n {\n v152 = v103;\n func0_part_0((unsigned int)v102, (unsigned int)v10, v162, a4, a5, a6);\n v10 = (unsigned int)v10;\n v100 = (unsigned int)(v152 + 1);\n }\n goto LABEL_164;\n }\n while ( 1 )\n {\n if ( (int)v100 > (int)v102 )\n v100 = (unsigned int)(v102 + 1);\nLABEL_164:\n if ( v92 < ++v101 || v92 < v101 * v101 )\n break;\n v102 = (unsigned int)(v92 - v101 * v101);\n if ( (int)v102 > 3 )\n goto LABEL_162;\n }\n }\n v87 = v100 + 1;\nLABEL_146:\n if ( v86 >= ++v91 )\n {\n v89 = v91 * v91;\n if ( v86 >= v91 * v91 )\n continue;\n }\n v84 = v90;\n v85 = v88;\n v83 = v10;\n if ( v84 <= v87 )\n goto LABEL_149;\n v105 = 1;\n v106 = v86;\n v150 = v85;\n v107 = 1;\n v108 = v86;\n while ( 1 )\n {\n v109 = v106 - v105;\n if ( v106 - v105 <= 3 )\n {\n if ( v108 <= v109 )\n goto LABEL_181;\n v115 = v106 - v105;\n }\n else\n {\n v110 = (unsigned int)v109;\n v111 = 1;\n v112 = 1;\n do\n {\n v113 = v109 - v111;\n if ( v109 - v111 <= 3 )\n {\n if ( (int)v110 > (int)v113 )\n v110 = v113 + 1;\n }\n else\n {\n v167 = v110;\n v114 = func0_part_0(v113, v10, v110, a4, a5, a6);\n v110 = v167;\n if ( (int)v167 > v114 )\n {\n v168 = v114;\n func0_part_0(v113, v10, v110, a4, a5, a6);\n v110 = (unsigned int)(v168 + 1);\n }\n }\n if ( v109 < ++v112 )\n break;\n v111 = v112 * v112;\n }\n while ( v109 >= v112 * v112 );\n if ( v108 <= (int)v110 )\n goto LABEL_181;\n v115 = v109;\n v116 = 1;\n v117 = v109 - 1;\n if ( v109 - 1 > 3 )\n {\nLABEL_190:\n v118 = func0_part_0(v117, v10, v110, a4, a5, a6);\n if ( v118 < v115 )\n {\n v169 = v118;\n func0_part_0(v117, v10, v110, a4, a5, a6);\n v115 = v169 + 1;\n }\n goto LABEL_192;\n }\n while ( 1 )\n {\n if ( (int)v117 < v115 )\n v115 = v117 + 1;\nLABEL_192:\n if ( v109 < ++v116 )\n break;\n v119 = v116 * v116;\n if ( v109 < v116 * v116 )\n break;\n v117 = v109 - v119;\n if ( v109 - v119 > 3 )\n goto LABEL_190;\n }\n }\n v108 = v115 + 1;\nLABEL_181:\n if ( v106 >= ++v107 )\n {\n v105 = v107 * v107;\n if ( v106 >= v107 * v107 )\n continue;\n }\n v104 = v108;\n v83 = v10;\n v85 = v150;\nLABEL_171:\n v84 = v104 + 1;\n goto LABEL_149;\n }\n }\n }\n return v6;\n}", + "ida_strip_asm": "sub_11C0:\npush r15\npush r14\npush r13\npush r12\npush rbp\nmov ebp, edi\npush rbx\nsub rsp, 38h\ntest edi, edi\njle loc_1371\nmov eax, 1\nmov r13d, 1\nmov r12d, edi\nloc_11E6:\nmov esi, r12d\nsub esi, eax\ncmp esi, 3\njle loc_185B\nmov r14d, 1\nmov [rsp+68h+var_5C], r13d\nmov ebx, esi\nmov eax, 1\nmov [rsp+68h+var_58], ebp\nmov r13d, r12d\nmov ebp, r14d\nmov r14d, esi\nloc_1213:\nmov edx, r14d\nsub edx, eax\ncmp edx, 3\njle loc_15C0\nmov r15d, 1\nmov [rsp+68h+var_60], ebx\nmov eax, 1\nmov r8d, edx\nmov ebx, r15d\nmov r15d, edx\nloc_1239:\nmov r12d, r15d\nsub r12d, eax\ncmp r12d, 3\njle loc_1438\nmov r9d, r12d\nmov eax, 1\nmov esi, 1\nloc_1256:\nmov edx, r12d\nsub edx, eax\ncmp edx, 3\njle loc_13A0\nmov r10d, edx\nmov eax, 1\nmov ecx, 1\nloc_1271:\nmov edi, edx\nsub edi, eax\ncmp edi, 3\njle loc_1388\nmov [rsp+68h+var_3C], r10d\nmov [rsp+68h+var_40], ecx\nmov [rsp+68h+var_44], esi\nmov [rsp+68h+var_48], edx\nmov [rsp+68h+var_4C], r8d\nmov [rsp+68h+var_50], r9d\nmov [rsp+68h+var_54], edi\ncall sub_11C0\nmov r10d, [rsp+68h+var_3C]\nmov edi, [rsp+68h+var_54]\nmov r9d, [rsp+68h+var_50]\nmov r8d, [rsp+68h+var_4C]\ncmp eax, r10d\nmov edx, [rsp+68h+var_48]\nmov esi, [rsp+68h+var_44]\nmov ecx, [rsp+68h+var_40]\njl loc_1924\nnop word ptr [rax+rax+00h]\nloc_12D0:\nadd ecx, 1\ncmp edx, ecx\njl short loc_12E0\nmov eax, ecx\nimul eax, ecx\ncmp edx, eax\njge short loc_1271\nloc_12E0:\ncmp r9d, r10d\njg loc_13B8\nloc_12E9:\nadd esi, 1\ncmp r12d, esi\njl short loc_12FF\nmov eax, esi\nimul eax, esi\ncmp r12d, eax\njge loc_1256\nloc_12FF:\ncmp r9d, r8d\njl loc_1450\nloc_1308:\nadd ebx, 1\ncmp r15d, ebx\njl short loc_131E\nmov eax, ebx\nimul eax, ebx\ncmp r15d, eax\njge loc_1239\nloc_131E:\nmov ebx, [rsp+68h+var_60]\nmov edx, r15d\ncmp r8d, ebx\njl loc_15D2\nloc_132E:\nadd ebp, 1\ncmp r14d, ebp\njl short loc_1344\nmov eax, ebp\nimul eax, ebp\ncmp r14d, eax\njge loc_1213\nloc_1344:\nmov ebp, [rsp+68h+var_58]\nmov r12d, r13d\nmov r13d, [rsp+68h+var_5C]\ncmp ebx, ebp\njl loc_1A0F\nloc_1358:\nadd r13d, 1\ncmp r12d, r13d\njl short loc_1371\nmov eax, r13d\nimul eax, r13d\ncmp eax, r12d\njle loc_11E6\nloc_1371:\nadd rsp, 38h\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1388:\ncmp edi, r10d\njge loc_12D0\nlea r10d, [rdi+1]\njmp loc_12D0\nloc_13A0:\ncmp r9d, edx\njle loc_12E9\nmov r9d, edx\nloc_13AC:\nadd r9d, 1\njmp loc_12E9\nloc_13B8:\nmov eax, 1\nmov edi, edx\nmov r9d, edx\nmov ecx, 1\nsub edi, eax\ncmp edi, 3\njle short loc_1429\nloc_13CE:\nmov [rsp+68h+var_40], ecx\nmov [rsp+68h+var_44], r9d\nmov [rsp+68h+var_48], esi\nmov [rsp+68h+var_4C], edx\nmov [rsp+68h+var_50], r8d\nmov [rsp+68h+var_54], edi\ncall sub_11C0\nmov r9d, [rsp+68h+var_44]\nmov edi, [rsp+68h+var_54]\nmov r8d, [rsp+68h+var_50]\nmov edx, [rsp+68h+var_4C]\ncmp r9d, eax\nmov esi, [rsp+68h+var_48]\nmov ecx, [rsp+68h+var_40]\njg loc_18D2\nloc_1410:\nadd ecx, 1\ncmp edx, ecx\njl short loc_13AC\nmov eax, ecx\nimul eax, ecx\ncmp edx, eax\njl short loc_13AC\nmov edi, edx\nsub edi, eax\ncmp edi, 3\njg short loc_13CE\nloc_1429:\ncmp r9d, edi\njle short loc_1410\nlea r9d, [rdi+1]\njmp short loc_1410\nloc_1438:\ncmp r12d, r8d\njge loc_1308\nmov r8d, r12d\nloc_1444:\nadd r8d, 1\njmp loc_1308\nloc_1450:\nmov r9d, 1\nmov ecx, ebp\nmov r8d, r12d\nmov eax, 1\nmov ebp, r9d\nmov esi, ebx\nmov r9d, r13d\nmov r13d, r12d\nloc_146B:\nmov r12d, r13d\nsub r12d, eax\ncmp r12d, 3\njle loc_1530\nmov edx, r12d\nmov eax, 1\nmov ebx, 1\nloc_1488:\nmov edi, r12d\nsub edi, eax\ncmp edi, 3\njle loc_1520\nmov [rsp+68h+var_40], r9d\nmov [rsp+68h+var_44], edx\nmov [rsp+68h+var_48], r8d\nmov [rsp+68h+var_4C], esi\nmov [rsp+68h+var_50], ecx\nmov [rsp+68h+var_54], edi\ncall sub_11C0\nmov edx, [rsp+68h+var_44]\nmov edi, [rsp+68h+var_54]\nmov ecx, [rsp+68h+var_50]\nmov esi, [rsp+68h+var_4C]\ncmp edx, eax\nmov r8d, [rsp+68h+var_48]\nmov r9d, [rsp+68h+var_40]\njg loc_19A6\nnop word ptr [rax+rax+00000000h]\nloc_14E0:\nadd ebx, 1\ncmp r12d, ebx\njl short loc_14F2\nmov eax, ebx\nimul eax, ebx\ncmp r12d, eax\njge short loc_1488\nloc_14F2:\ncmp r8d, edx\njg short loc_1540\nloc_14F7:\nadd ebp, 1\ncmp r13d, ebp\njl short loc_150D\nmov eax, ebp\nimul eax, ebp\ncmp r13d, eax\njge loc_146B\nloc_150D:\nmov ebp, ecx\nmov ebx, esi\nmov r13d, r9d\njmp loc_1444\nloc_1520:\ncmp edx, edi\njle short loc_14E0\nlea edx, [rdi+1]\njmp short loc_14E0\nloc_1530:\ncmp r8d, r12d\njle short loc_14F7\nmov r8d, r12d\nloc_1538:\nadd r8d, 1\njmp short loc_14F7\nloc_1540:\nmov eax, 1\nmov edi, r12d\nmov r8d, r12d\nmov ebx, 1\nsub edi, eax\ncmp edi, 3\njle short loc_15B4\nloc_1557:\nmov [rsp+68h+var_44], r9d\nmov [rsp+68h+var_48], r8d\nmov [rsp+68h+var_4C], esi\nmov [rsp+68h+var_50], ecx\nmov [rsp+68h+var_54], edi\ncall sub_11C0\nmov r8d, [rsp+68h+var_48]\nmov edi, [rsp+68h+var_54]\nmov ecx, [rsp+68h+var_50]\nmov esi, [rsp+68h+var_4C]\ncmp r8d, eax\nmov r9d, [rsp+68h+var_44]\njg loc_19DF\nnop dword ptr [rax+00000000h]\nloc_1598:\nadd ebx, 1\ncmp r12d, ebx\njl short loc_1538\nmov eax, ebx\nimul eax, ebx\ncmp r12d, eax\njl short loc_1538\nmov edi, r12d\nsub edi, eax\ncmp edi, 3\njg short loc_1557\nloc_15B4:\ncmp r8d, edi\njle short loc_1598\nlea r8d, [rdi+1]\njmp short loc_1598\nloc_15C0:\ncmp edx, ebx\njge loc_132E\nmov ebx, edx\nloc_15CA:\nadd ebx, 1\njmp loc_132E\nloc_15D2:\nmov ebx, r15d\nmov [rsp+68h+var_60], ebp\nmov r15d, 1\nmov r12d, r14d\nmov [rsp+68h+var_54], r13d\nmov esi, r15d\nmov eax, 1\nmov r15d, edx\nmov edx, esi\nloc_15F4:\nmov ebp, r15d\nsub ebp, eax\ncmp ebp, 3\njle loc_1780\nmov r14d, 1\nmov r8d, ebx\nmov r13d, ebp\nmov eax, 1\nmov ebx, r14d\nloc_1616:\nmov r14d, ebp\nsub r14d, eax\ncmp r14d, 3\njle loc_16F0\nmov esi, r14d\nmov eax, 1\nmov ecx, 1\nloc_1633:\nmov edi, r14d\nsub edi, eax\ncmp edi, 3\njle loc_16E0\nmov [rsp+68h+var_40], edx\nmov [rsp+68h+var_44], r8d\nmov [rsp+68h+var_48], ecx\nmov [rsp+68h+var_4C], esi\nmov [rsp+68h+var_50], edi\ncall sub_11C0\nmov esi, [rsp+68h+var_4C]\nmov edi, [rsp+68h+var_50]\nmov ecx, [rsp+68h+var_48]\nmov r8d, [rsp+68h+var_44]\ncmp esi, eax\nmov edx, [rsp+68h+var_40]\njg loc_1950\nnop dword ptr [rax+rax+00000000h]\nloc_1680:\nadd ecx, 1\ncmp r14d, ecx\njl short loc_1692\nmov eax, ecx\nimul eax, ecx\ncmp r14d, eax\njge short loc_1633\nloc_1692:\ncmp esi, r13d\njl short loc_1700\nloc_1697:\nadd ebx, 1\ncmp ebp, ebx\njl short loc_16AB\nmov eax, ebx\nimul eax, ebx\ncmp ebp, eax\njge loc_1616\nloc_16AB:\nmov ebx, r8d\ncmp r8d, r13d\njg loc_1794\nloc_16B7:\nadd edx, 1\ncmp r15d, edx\njl short loc_16CD\nmov eax, edx\nimul eax, edx\ncmp r15d, eax\njge loc_15F4\nloc_16CD:\nmov ebp, [rsp+68h+var_60]\nmov r13d, [rsp+68h+var_54]\nmov r14d, r12d\njmp loc_15CA\nloc_16E0:\ncmp esi, edi\njle short loc_1680\nlea esi, [rdi+1]\njmp short loc_1680\nloc_16F0:\ncmp r14d, r13d\njge short loc_1697\nmov ecx, r14d\nloc_16F8:\nlea r13d, [rcx+1]\njmp short loc_1697\nloc_1700:\nmov eax, 1\nmov edi, r14d\nmov ecx, r14d\nmov r13d, 1\nsub edi, eax\ncmp edi, 3\njle short loc_176F\nloc_1718:\nmov [rsp+68h+var_44], edx\nmov [rsp+68h+var_48], ecx\nmov [rsp+68h+var_4C], r8d\nmov [rsp+68h+var_50], edi\ncall sub_11C0\nmov ecx, [rsp+68h+var_48]\nmov edi, [rsp+68h+var_50]\nmov r8d, [rsp+68h+var_4C]\nmov edx, [rsp+68h+var_44]\ncmp ecx, eax\njg loc_197F\nnop word ptr [rax+rax+00000000h]\nloc_1750:\nadd r13d, 1\ncmp r14d, r13d\njl short loc_16F8\nmov eax, r13d\nimul eax, r13d\ncmp r14d, eax\njl short loc_16F8\nmov edi, r14d\nsub edi, eax\ncmp edi, 3\njg short loc_1718\nloc_176F:\ncmp ecx, edi\njle short loc_1750\nlea ecx, [rdi+1]\njmp short loc_1750\nloc_1780:\ncmp ebx, ebp\njle loc_16B7\nmov r8d, ebp\nloc_178B:\nlea ebx, [r8+1]\njmp loc_16B7\nloc_1794:\nmov [rsp+68h+var_48], edx\nmov r13d, 1\nmov eax, 1\nmov [rsp+68h+var_50], r12d\nmov r12d, r13d\nmov [rsp+68h+var_4C], r15d\nmov r15d, ebp\nloc_17B3:\nmov ebx, r15d\nsub ebx, eax\ncmp ebx, 3\njle loc_1850\nmov ecx, ebx\nmov eax, 1\nmov r14d, 1\nloc_17CE:\nmov r13d, ebx\nsub r13d, eax\ncmp r13d, 3\njle short loc_1840\nmov edi, r13d\nmov [rsp+68h+var_44], ecx\ncall sub_11C0\nmov ecx, [rsp+68h+var_44]\ncmp ecx, eax\njg loc_190A\nnop word ptr [rax+rax+00h]\nloc_17F8:\nadd r14d, 1\ncmp ebx, r14d\njl short loc_180C\nmov eax, r14d\nimul eax, r14d\ncmp ebx, eax\njge short loc_17CE\nloc_180C:\ncmp ebp, ecx\njg short loc_186B\nloc_1810:\nadd r12d, 1\ncmp r15d, r12d\njl short loc_1825\nmov eax, r12d\nimul eax, r12d\ncmp r15d, eax\njge short loc_17B3\nloc_1825:\nmov r12d, [rsp+68h+var_50]\nmov r15d, [rsp+68h+var_4C]\nmov r8d, ebp\nmov edx, [rsp+68h+var_48]\njmp loc_178B\nloc_1840:\ncmp ecx, r13d\njle short loc_17F8\nlea ecx, [r13+1]\njmp short loc_17F8\nloc_1850:\ncmp ebp, ebx\njle short loc_1810\nmov ebp, ebx\nloc_1856:\nadd ebp, 1\njmp short loc_1810\nloc_185B:\ncmp esi, ebp\njge loc_1358\nmov r15d, esi\njmp loc_1B77\nloc_186B:\nmov eax, 1\nmov r14d, ebx\nmov ebp, ebx\nmov r13d, 1\nsub r14d, eax\ncmp r14d, 3\njle short loc_18B0\nloc_1884:\nmov edi, r14d\ncall sub_11C0\ncmp eax, ebp\njl short loc_18BB\nloc_1890:\nadd r13d, 1\ncmp ebx, r13d\njl short loc_1856\nmov eax, r13d\nimul eax, r13d\ncmp ebx, eax\njl short loc_1856\nmov r14d, ebx\nsub r14d, eax\ncmp r14d, 3\njg short loc_1884\nloc_18B0:\ncmp r14d, ebp\njge short loc_1890\nlea ebp, [r14+1]\njmp short loc_1890\nloc_18BB:\nmov edi, r14d\nmov [rsp+68h+var_44], eax\ncall sub_11C0\nmov r14d, [rsp+68h+var_44]\nlea ebp, [r14+1]\njmp short loc_1890\nloc_18D2:\nmov [rsp+68h+var_44], ecx\nmov [rsp+68h+var_48], esi\nmov [rsp+68h+var_4C], edx\nmov [rsp+68h+var_50], r8d\nmov [rsp+68h+var_54], eax\ncall sub_11C0\nmov edi, [rsp+68h+var_54]\nmov ecx, [rsp+68h+var_44]\nmov esi, [rsp+68h+var_48]\nmov edx, [rsp+68h+var_4C]\nmov r8d, [rsp+68h+var_50]\nlea r9d, [rdi+1]\njmp loc_1410\nloc_190A:\nmov edi, r13d\nmov [rsp+68h+var_44], eax\ncall sub_11C0\nmov r13d, [rsp+68h+var_44]\nlea ecx, [r13+1]\njmp loc_17F8\nloc_1924:\nmov [rsp+68h+var_54], eax\ncall sub_11C0\nmov edi, [rsp+68h+var_54]\nmov ecx, [rsp+68h+var_40]\nmov esi, [rsp+68h+var_44]\nmov edx, [rsp+68h+var_48]\nmov r8d, [rsp+68h+var_4C]\nmov r9d, [rsp+68h+var_50]\nlea r10d, [rdi+1]\njmp loc_12D0\nloc_1950:\nmov [rsp+68h+var_44], edx\nmov [rsp+68h+var_48], r8d\nmov [rsp+68h+var_4C], ecx\nmov [rsp+68h+var_50], eax\ncall sub_11C0\nmov edi, [rsp+68h+var_50]\nmov edx, [rsp+68h+var_44]\nmov r8d, [rsp+68h+var_48]\nmov ecx, [rsp+68h+var_4C]\nlea esi, [rdi+1]\njmp loc_1680\nloc_197F:\nmov [rsp+68h+var_48], edx\nmov [rsp+68h+var_4C], r8d\nmov [rsp+68h+var_50], eax\ncall sub_11C0\nmov edi, [rsp+68h+var_50]\nmov edx, [rsp+68h+var_48]\nmov r8d, [rsp+68h+var_4C]\nlea ecx, [rdi+1]\njmp loc_1750\nloc_19A6:\nmov [rsp+68h+var_44], r9d\nmov [rsp+68h+var_48], r8d\nmov [rsp+68h+var_4C], esi\nmov [rsp+68h+var_50], ecx\nmov [rsp+68h+var_54], eax\ncall sub_11C0\nmov edi, [rsp+68h+var_54]\nmov r9d, [rsp+68h+var_44]\nmov r8d, [rsp+68h+var_48]\nmov esi, [rsp+68h+var_4C]\nmov ecx, [rsp+68h+var_50]\nlea edx, [rdi+1]\njmp loc_14E0\nloc_19DF:\nmov [rsp+68h+var_48], r9d\nmov [rsp+68h+var_4C], esi\nmov [rsp+68h+var_50], ecx\nmov [rsp+68h+var_54], eax\ncall sub_11C0\nmov edi, [rsp+68h+var_54]\nmov r9d, [rsp+68h+var_48]\nmov esi, [rsp+68h+var_4C]\nmov ecx, [rsp+68h+var_50]\nlea r8d, [rdi+1]\njmp loc_1598\nloc_1A0F:\nmov [rsp+68h+var_44], r13d\nmov ebx, 1\nmov edx, 1\nmov [rsp+68h+var_40], r12d\nmov ebp, ebx\nmov r12d, r14d\nmov ebx, r14d\nloc_1A2B:\nmov r13d, ebx\nsub r13d, edx\ncmp r13d, 3\njle loc_1D3C\nmov [rsp+68h+var_58], r12d\nmov edx, 1\nmov r14d, 1\nmov [rsp+68h+var_60], ebx\nmov ebx, r13d\nmov [rsp+68h+var_5C], ebp\nmov ebp, r13d\nloc_1A59:\nmov r13d, ebp\nsub r13d, edx\ncmp r13d, 3\njle loc_1C10\nmov r15d, 1\nmov esi, r14d\nmov r12d, r13d\nmov r14d, ebp\nmov eax, 1\nmov ebp, ebx\nmov ebx, r15d\nloc_1A82:\nmov r15d, r13d\nsub r15d, eax\ncmp r15d, 3\njle loc_1B90\nmov ecx, r15d\nmov eax, 1\nmov edx, 1\nloc_1A9F:\nmov edi, r15d\nsub edi, eax\ncmp edi, 3\njle loc_1B80\nmov [rsp+68h+var_48], edx\nmov [rsp+68h+var_4C], esi\nmov [rsp+68h+var_50], ecx\nmov [rsp+68h+var_54], edi\ncall sub_11C0\nmov ecx, [rsp+68h+var_50]\nmov edi, [rsp+68h+var_54]\nmov esi, [rsp+68h+var_4C]\nmov edx, [rsp+68h+var_48]\ncmp ecx, eax\njg loc_1D7E\nnop word ptr [rax+rax+00h]\nloc_1AE0:\nadd edx, 1\ncmp r15d, edx\njl short loc_1AF2\nmov eax, edx\nimul eax, edx\ncmp r15d, eax\njge short loc_1A9F\nloc_1AF2:\ncmp ecx, r12d\njl loc_1BA8\nloc_1AFB:\nadd ebx, 1\ncmp r13d, ebx\njl short loc_1B11\nmov eax, ebx\nimul eax, ebx\ncmp r13d, eax\njge loc_1A82\nloc_1B11:\nmov ebx, ebp\nmov ebp, r14d\nmov r14d, esi\ncmp ebx, r12d\njg loc_1C24\nloc_1B22:\nadd r14d, 1\ncmp ebp, r14d\njl short loc_1B3A\nmov edx, r14d\nimul edx, r14d\ncmp ebp, edx\njge loc_1A59\nloc_1B3A:\nmov r12d, [rsp+68h+var_58]\nmov r15d, ebx\nmov r13d, ebp\nmov ebx, [rsp+68h+var_60]\nmov ebp, [rsp+68h+var_5C]\ncmp r12d, r15d\njg loc_1DC0\nloc_1B56:\nadd ebp, 1\ncmp ebx, ebp\njl short loc_1B6A\nmov edx, ebp\nimul edx, ebp\ncmp ebx, edx\njge loc_1A2B\nloc_1B6A:\nmov r15d, r12d\nmov r13d, [rsp+68h+var_44]\nmov r12d, [rsp+68h+var_40]\nloc_1B77:\nlea ebp, [r15+1]\njmp loc_1358\nloc_1B80:\ncmp ecx, edi\njle loc_1AE0\nlea ecx, [rdi+1]\njmp loc_1AE0\nloc_1B90:\ncmp r15d, r12d\njge loc_1AFB\nmov edx, r15d\nloc_1B9C:\nlea r12d, [rdx+1]\njmp loc_1AFB\nloc_1BA8:\nmov eax, 1\nmov edi, r15d\nmov edx, r15d\nmov r12d, 1\nsub edi, eax\ncmp edi, 3\njle short loc_1C07\nloc_1BC0:\nmov [rsp+68h+var_4C], esi\nmov [rsp+68h+var_50], edx\nmov [rsp+68h+var_54], edi\ncall sub_11C0\nmov edx, [rsp+68h+var_50]\nmov edi, [rsp+68h+var_54]\nmov esi, [rsp+68h+var_4C]\ncmp edx, eax\njg loc_1DA3\nnop dword ptr [rax]\nloc_1BE8:\nadd r12d, 1\ncmp r15d, r12d\njl short loc_1B9C\nmov eax, r12d\nimul eax, r12d\ncmp r15d, eax\njl short loc_1B9C\nmov edi, r15d\nsub edi, eax\ncmp edi, 3\njg short loc_1BC0\nloc_1C07:\ncmp edx, edi\njle short loc_1BE8\nlea edx, [rdi+1]\njmp short loc_1BE8\nloc_1C10:\ncmp ebx, r13d\njle loc_1B22\nmov ebx, r13d\nloc_1C1C:\nadd ebx, 1\njmp loc_1B22\nloc_1C24:\nmov [rsp+68h+var_50], esi\nmov r12d, 1\nmov eax, 1\nmov r14d, r13d\nmov [rsp+68h+var_54], ebp\nmov ebx, r12d\nmov ebp, r13d\nloc_1C40:\nmov r15d, r14d\nsub r15d, eax\ncmp r15d, 3\njle loc_1CD8\nmov edx, r15d\nmov eax, 1\nmov r12d, 1\nloc_1C5E:\nmov r13d, r15d\nsub r13d, eax\ncmp r13d, 3\njle short loc_1CC8\nmov edi, r13d\nmov [rsp+68h+var_4C], edx\ncall sub_11C0\nmov edx, [rsp+68h+var_4C]\ncmp edx, eax\njg loc_1D4D\nnop word ptr [rax+rax+00h]\nloc_1C88:\nadd r12d, 1\ncmp r15d, r12d\njl short loc_1C9D\nmov eax, r12d\nimul eax, r12d\ncmp r15d, eax\njge short loc_1C5E\nloc_1C9D:\ncmp ebp, edx\njg short loc_1CE5\nloc_1CA1:\nadd ebx, 1\ncmp r14d, ebx\njl short loc_1CB3\nmov eax, ebx\nimul eax, ebx\ncmp r14d, eax\njge short loc_1C40\nloc_1CB3:\nmov ebx, ebp\nmov r14d, [rsp+68h+var_50]\nmov ebp, [rsp+68h+var_54]\njmp loc_1C1C\nloc_1CC8:\ncmp edx, r13d\njle short loc_1C88\nlea edx, [r13+1]\njmp short loc_1C88\nloc_1CD8:\ncmp ebp, r15d\njle short loc_1CA1\nmov ebp, r15d\nloc_1CE0:\nadd ebp, 1\njmp short loc_1CA1\nloc_1CE5:\nmov eax, 1\nmov r13d, r15d\nmov ebp, r15d\nmov r12d, 1\nsub r13d, eax\ncmp r13d, 3\njle short loc_1D31\nloc_1CFF:\nmov edi, r13d\ncall sub_11C0\ncmp eax, ebp\njl short loc_1D67\nnop dword ptr [rax+rax+00h]\nloc_1D10:\nadd r12d, 1\ncmp r15d, r12d\njl short loc_1CE0\nmov eax, r12d\nimul eax, r12d\ncmp r15d, eax\njl short loc_1CE0\nmov r13d, r15d\nsub r13d, eax\ncmp r13d, 3\njg short loc_1CFF\nloc_1D31:\ncmp r13d, ebp\njge short loc_1D10\nlea ebp, [r13+1]\njmp short loc_1D10\nloc_1D3C:\ncmp r12d, r13d\njle loc_1B56\nmov r12d, r13d\njmp loc_1E58\nloc_1D4D:\nmov edi, r13d\nmov [rsp+68h+var_4C], eax\ncall sub_11C0\nmov r13d, [rsp+68h+var_4C]\nlea edx, [r13+1]\njmp loc_1C88\nloc_1D67:\nmov edi, r13d\nmov [rsp+68h+var_4C], eax\ncall sub_11C0\nmov r13d, [rsp+68h+var_4C]\nlea ebp, [r13+1]\njmp short loc_1D10\nloc_1D7E:\nmov [rsp+68h+var_4C], edx\nmov [rsp+68h+var_50], esi\nmov [rsp+68h+var_54], eax\ncall sub_11C0\nmov edi, [rsp+68h+var_54]\nmov edx, [rsp+68h+var_4C]\nmov esi, [rsp+68h+var_50]\nlea ecx, [rdi+1]\njmp loc_1AE0\nloc_1DA3:\nmov [rsp+68h+var_50], esi\nmov [rsp+68h+var_54], eax\ncall sub_11C0\nmov edi, [rsp+68h+var_54]\nmov esi, [rsp+68h+var_50]\nlea edx, [rdi+1]\njmp loc_1BE8\nloc_1DC0:\nmov edx, 1\nmov [rsp+68h+var_5C], ebx\nmov eax, 1\nmov ebx, r13d\nmov [rsp+68h+var_58], ebp\nmov r12d, edx\nmov ebp, r13d\nloc_1DDB:\nmov r15d, ebx\nsub r15d, eax\ncmp r15d, 3\njle loc_1E8A\nmov edx, r15d\nmov eax, 1\nmov r14d, 1\nloc_1DF9:\nmov r13d, r15d\nsub r13d, eax\ncmp r13d, 3\njle short loc_1E68\nmov edi, r13d\nmov [rsp+68h+var_60], edx\ncall sub_11C0\nmov edx, [rsp+68h+var_60]\ncmp eax, edx\njl short loc_1E73\nnop dword ptr [rax+00000000h]\nloc_1E20:\nadd r14d, 1\ncmp r15d, r14d\njl short loc_1E35\nmov eax, r14d\nimul eax, r14d\ncmp r15d, eax\njge short loc_1DF9\nloc_1E35:\ncmp edx, ebp\njl short loc_1E95\nloc_1E39:\nadd r12d, 1\ncmp ebx, r12d\njl short loc_1E4D\nmov eax, r12d\nimul eax, r12d\ncmp ebx, eax\njge short loc_1DDB\nloc_1E4D:\nmov r12d, ebp\nmov ebx, [rsp+68h+var_5C]\nmov ebp, [rsp+68h+var_58]\nloc_1E58:\nadd r12d, 1\njmp loc_1B56\nloc_1E68:\ncmp r13d, edx\njge short loc_1E20\nlea edx, [r13+1]\njmp short loc_1E20\nloc_1E73:\nmov edi, r13d\nmov [rsp+68h+var_60], eax\ncall sub_11C0\nmov r13d, [rsp+68h+var_60]\nlea edx, [r13+1]\njmp short loc_1E20\nloc_1E8A:\ncmp r15d, ebp\njge short loc_1E39\nlea ebp, [r15+1]\njmp short loc_1E39\nloc_1E95:\nmov edi, r15d\ncall sub_11C0\nmov r15d, eax\nlea ebp, [r15+1]\njmp short loc_1E39", + "ida_strip_pseudo": "__int64 __fastcall sub_11C0(int a1, __int64 a2, __int64 a3, __int64 a4, __int64 a5, __int64 a6)\n{\n unsigned int v6; // ebp\n int v7; // eax\n int v8; // r13d\n int v9; // r12d\n __int64 v10; // rsi\n int v11; // ebx\n int v12; // eax\n unsigned int v13; // r13d\n unsigned int v14; // ebp\n int v15; // r14d\n int v16; // edx\n int v17; // eax\n unsigned int v18; // ebx\n int v19; // r15d\n int v20; // r12d\n int v21; // eax\n __int64 v22; // rdx\n int v23; // r10d\n int v24; // eax\n int v25; // edi\n int v26; // eax\n __int64 v27; // rdi\n __int64 v29; // r9\n __int64 v30; // rdi\n int v31; // eax\n __int64 v32; // r8\n int v33; // eax\n int v34; // ebp\n int v35; // r13d\n int v36; // r12d\n __int64 v37; // rdx\n int v38; // eax\n int v39; // ebx\n __int64 v40; // rdi\n int v41; // eax\n __int64 v42; // rdi\n __int64 v43; // r8\n int v44; // ebx\n __int64 v45; // rdi\n int v46; // eax\n int v47; // ebx\n int v48; // r12d\n int v49; // eax\n __int64 v50; // rdx\n int v51; // ebp\n int v52; // r13d\n int v53; // eax\n int v54; // ebx\n int v55; // r14d\n int v56; // eax\n __int64 v57; // rdi\n int v58; // eax\n __int64 v59; // rdi\n int v60; // r13d\n __int64 v61; // rdi\n int v62; // eax\n int v63; // eax\n int v64; // r12d\n int v65; // r15d\n int v66; // ebx\n int v67; // eax\n int v68; // r14d\n unsigned int v69; // r13d\n int v70; // eax\n int v71; // ebp\n int v72; // r15d\n int v73; // r13d\n unsigned int v74; // r14d\n int v75; // eax\n int v76; // eax\n int v77; // edx\n int v78; // ebp\n int v79; // r12d\n int v80; // ebx\n int v81; // r13d\n int v82; // edx\n unsigned int v83; // r14d\n int v84; // ebx\n int v85; // ebp\n int v86; // r13d\n int v87; // r12d\n int v88; // r14d\n int v89; // eax\n int v90; // ebp\n int v91; // ebx\n int v92; // r15d\n int v93; // eax\n __int64 v94; // rdx\n __int64 v95; // rdi\n int v96; // eax\n __int64 v97; // rdi\n int v98; // r15d\n int v99; // r13d\n __int64 v100; // rdx\n int v101; // r12d\n __int64 v102; // rdi\n int v103; // eax\n int v104; // ebx\n int v105; // eax\n int v106; // r14d\n int v107; // ebx\n int v108; // ebp\n int v109; // r15d\n __int64 v110; // rdx\n int v111; // eax\n int v112; // r12d\n unsigned int v113; // r13d\n int v114; // eax\n int v115; // ebp\n int v116; // r12d\n unsigned int v117; // r13d\n int v118; // eax\n int v119; // eax\n int v120; // r12d\n int v121; // eax\n int v122; // ebx\n int v123; // r12d\n int v124; // ebp\n int v125; // r15d\n __int64 v126; // rdx\n int v127; // eax\n int v128; // r14d\n unsigned int v129; // r13d\n int v130; // eax\n int v131; // [rsp+8h] [rbp-60h]\n unsigned int v132; // [rsp+8h] [rbp-60h]\n int v133; // [rsp+8h] [rbp-60h]\n unsigned int v134; // [rsp+8h] [rbp-60h]\n int v135; // [rsp+8h] [rbp-60h]\n int v136; // [rsp+Ch] [rbp-5Ch]\n int v137; // [rsp+Ch] [rbp-5Ch]\n int v138; // [rsp+Ch] [rbp-5Ch]\n signed int v139; // [rsp+10h] [rbp-58h]\n int v140; // [rsp+10h] [rbp-58h]\n int v141; // [rsp+10h] [rbp-58h]\n unsigned int v142; // [rsp+14h] [rbp-54h]\n unsigned int v143; // [rsp+14h] [rbp-54h]\n unsigned int v144; // [rsp+14h] [rbp-54h]\n int v145; // [rsp+14h] [rbp-54h]\n int v146; // [rsp+14h] [rbp-54h]\n int v147; // [rsp+14h] [rbp-54h]\n int v148; // [rsp+14h] [rbp-54h]\n unsigned int v149; // [rsp+14h] [rbp-54h]\n int v150; // [rsp+14h] [rbp-54h]\n int v151; // [rsp+14h] [rbp-54h]\n int v152; // [rsp+14h] [rbp-54h]\n unsigned int v153; // [rsp+18h] [rbp-50h]\n unsigned int v154; // [rsp+18h] [rbp-50h]\n unsigned int v155; // [rsp+18h] [rbp-50h]\n unsigned int v156; // [rsp+18h] [rbp-50h]\n unsigned int v157; // [rsp+18h] [rbp-50h]\n int v158; // [rsp+18h] [rbp-50h]\n int v159; // [rsp+18h] [rbp-50h]\n int v160; // [rsp+18h] [rbp-50h]\n unsigned int v161; // [rsp+18h] [rbp-50h]\n unsigned int v162; // [rsp+18h] [rbp-50h]\n unsigned int v163; // [rsp+1Ch] [rbp-4Ch]\n unsigned int v164; // [rsp+1Ch] [rbp-4Ch]\n unsigned int v165; // [rsp+1Ch] [rbp-4Ch]\n int v166; // [rsp+1Ch] [rbp-4Ch]\n unsigned int v167; // [rsp+1Ch] [rbp-4Ch]\n int v168; // [rsp+1Ch] [rbp-4Ch]\n int v169; // [rsp+1Ch] [rbp-4Ch]\n unsigned int v170; // [rsp+20h] [rbp-48h]\n unsigned int v171; // [rsp+20h] [rbp-48h]\n unsigned int v172; // [rsp+20h] [rbp-48h]\n unsigned int v173; // [rsp+20h] [rbp-48h]\n unsigned int v174; // [rsp+20h] [rbp-48h]\n int v175; // [rsp+20h] [rbp-48h]\n unsigned int v176; // [rsp+20h] [rbp-48h]\n unsigned int v177; // [rsp+24h] [rbp-44h]\n unsigned int v178; // [rsp+24h] [rbp-44h]\n unsigned int v179; // [rsp+24h] [rbp-44h]\n unsigned int v180; // [rsp+24h] [rbp-44h]\n unsigned int v181; // [rsp+24h] [rbp-44h]\n unsigned int v182; // [rsp+24h] [rbp-44h]\n int v183; // [rsp+24h] [rbp-44h]\n int v184; // [rsp+24h] [rbp-44h]\n int v185; // [rsp+24h] [rbp-44h]\n unsigned int v186; // [rsp+28h] [rbp-40h]\n unsigned int v187; // [rsp+28h] [rbp-40h]\n unsigned int v188; // [rsp+28h] [rbp-40h]\n unsigned int v189; // [rsp+28h] [rbp-40h]\n int v190; // [rsp+28h] [rbp-40h]\n int v191; // [rsp+2Ch] [rbp-3Ch]\n\n v6 = a1;\n if ( a1 > 0 )\n {\n v7 = 1;\n v8 = 1;\n v9 = a1;\n while ( 1 )\n {\n v10 = (unsigned int)(v9 - v7);\n if ( (int)v10 > 3 )\n break;\n if ( (int)v10 < (int)v6 )\n {\n v72 = v9 - v7;\n goto LABEL_155;\n }\nLABEL_26:\n if ( v9 >= ++v8 )\n {\n v7 = v8 * v8;\n if ( v8 * v8 <= v9 )\n continue;\n }\n return v6;\n }\n v136 = v8;\n v11 = v9 - v7;\n v12 = 1;\n v139 = v6;\n v13 = v9;\n v14 = 1;\n v15 = v10;\n do\n {\n v16 = v15 - v12;\n if ( v15 - v12 > 3 )\n {\n v131 = v11;\n v17 = 1;\n a5 = (unsigned int)v16;\n v18 = 1;\n v19 = v16;\n while ( 1 )\n {\n v20 = v19 - v17;\n if ( v19 - v17 > 3 )\n break;\n if ( v20 < (int)a5 )\n {\n LODWORD(v32) = v19 - v17;\n goto LABEL_44;\n }\nLABEL_20:\n if ( v19 >= (int)++v18 )\n {\n v17 = v18 * v18;\n if ( v19 >= (int)(v18 * v18) )\n continue;\n }\n v11 = v131;\n if ( (int)a5 >= v131 )\n goto LABEL_23;\n v47 = v19;\n v132 = v14;\n v48 = v15;\n v144 = v13;\n v10 = 1LL;\n v49 = 1;\n v50 = 1LL;\n while ( 1 )\n {\n v51 = v19 - v49;\n if ( v19 - v49 > 3 )\n break;\n if ( v47 > v51 )\n {\n a5 = (unsigned int)v51;\n goto LABEL_105;\n }\nLABEL_87:\n v50 = (unsigned int)(v50 + 1);\n if ( v19 >= (int)v50 )\n {\n v49 = v50 * v50;\n if ( v19 >= (int)v50 * (int)v50 )\n continue;\n }\n v14 = v132;\n v13 = v144;\n v15 = v48;\nLABEL_72:\n v11 = v47 + 1;\n goto LABEL_23;\n }\n a5 = (unsigned int)v47;\n v52 = v19 - v49;\n v53 = 1;\n v54 = 1;\n while ( 2 )\n {\n v55 = v51 - v53;\n if ( v51 - v53 <= 3 )\n {\n if ( v55 >= v52 )\n goto LABEL_84;\n a4 = (unsigned int)v55;\n }\n else\n {\n v10 = (unsigned int)v55;\n v56 = 1;\n a4 = 1LL;\n do\n {\n v57 = (unsigned int)(v55 - v56);\n if ( (int)v57 <= 3 )\n {\n if ( (int)v10 > (int)v57 )\n v10 = (unsigned int)(v57 + 1);\n }\n else\n {\n v189 = v50;\n v180 = a5;\n v173 = a4;\n v157 = v55 - v56;\n v58 = sub_11C0(v57, v10, v50, a4, a5, a6);\n v10 = (unsigned int)v10;\n v59 = v157;\n LODWORD(a4) = v173;\n a5 = v180;\n v50 = v189;\n if ( (int)v10 > v58 )\n {\n v159 = v58;\n sub_11C0(v59, (unsigned int)v10, v189, v173, v180, a6);\n v50 = v189;\n a5 = v180;\n LODWORD(a4) = v173;\n v10 = (unsigned int)(v159 + 1);\n }\n }\n a4 = (unsigned int)(a4 + 1);\n if ( v55 < (int)a4 )\n break;\n v56 = a4 * a4;\n }\n while ( v55 >= (int)a4 * (int)a4 );\n if ( (int)v10 >= v52 )\n {\nLABEL_84:\n if ( v51 >= ++v54 )\n {\n v53 = v54 * v54;\n if ( v51 >= v54 * v54 )\n continue;\n }\n v47 = a5;\n if ( (int)a5 <= v52 )\n goto LABEL_87;\n v175 = v50;\n v63 = 1;\n v158 = v48;\n v64 = 1;\n v166 = v19;\n v65 = v51;\n while ( 2 )\n {\n v66 = v65 - v63;\n if ( v65 - v63 <= 3 )\n {\n if ( v51 <= v66 )\n goto LABEL_115;\n v71 = v65 - v63;\n }\n else\n {\n a4 = (unsigned int)v66;\n v67 = 1;\n v68 = 1;\n do\n {\n v69 = v66 - v67;\n if ( v66 - v67 <= 3 )\n {\n if ( (int)a4 > (int)v69 )\n a4 = v69 + 1;\n }\n else\n {\n v182 = a4;\n v70 = sub_11C0(v69, v10, v50, a4, a5, a6);\n a4 = v182;\n if ( (int)v182 > v70 )\n {\n v184 = v70;\n sub_11C0(v69, v10, v50, a4, a5, a6);\n a4 = (unsigned int)(v184 + 1);\n }\n }\n if ( v66 < ++v68 )\n break;\n v67 = v68 * v68;\n }\n while ( v66 >= v68 * v68 );\n if ( v51 <= (int)a4 )\n {\nLABEL_115:\n if ( v65 < ++v64 || (v63 = v64 * v64, v65 < v64 * v64) )\n {\n v48 = v158;\n v19 = v166;\n a5 = (unsigned int)v51;\n LODWORD(v50) = v175;\nLABEL_105:\n v47 = a5 + 1;\n goto LABEL_87;\n }\n continue;\n }\n v71 = v66;\n v73 = 1;\n v74 = v66 - 1;\n if ( v66 - 1 > 3 )\n {\nLABEL_126:\n v75 = sub_11C0(v74, v10, v50, a4, a5, a6);\n if ( v75 < v71 )\n {\n v183 = v75;\n sub_11C0(v74, v10, v50, a4, a5, a6);\n v71 = v183 + 1;\n }\n goto LABEL_128;\n }\n while ( 1 )\n {\n if ( (int)v74 < v71 )\n v71 = v74 + 1;\nLABEL_128:\n if ( v66 < ++v73 )\n break;\n v76 = v73 * v73;\n if ( v66 < v73 * v73 )\n break;\n v74 = v66 - v76;\n if ( v66 - v76 > 3 )\n goto LABEL_126;\n }\n }\n break;\n }\n v51 = v71 + 1;\n goto LABEL_115;\n }\n a4 = (unsigned int)v55;\n v60 = 1;\n v61 = (unsigned int)(v55 - 1);\n if ( (int)v61 > 3 )\n {\nLABEL_96:\n v181 = v50;\n v174 = a4;\n v165 = a5;\n v62 = sub_11C0(v61, v10, v50, a4, a5, a6);\n a4 = v174;\n a5 = v165;\n v50 = v181;\n if ( (int)v174 > v62 )\n {\n v160 = v62;\n sub_11C0((unsigned int)v61, v10, v181, v174, v165, a6);\n v50 = v181;\n a5 = v165;\n a4 = (unsigned int)(v160 + 1);\n }\n goto LABEL_98;\n }\n while ( 1 )\n {\n if ( (int)a4 > (int)v61 )\n a4 = (unsigned int)(v61 + 1);\nLABEL_98:\n if ( v55 < ++v60 || v55 < v60 * v60 )\n break;\n v61 = (unsigned int)(v55 - v60 * v60);\n if ( (int)v61 > 3 )\n goto LABEL_96;\n }\n }\n break;\n }\n v52 = a4 + 1;\n goto LABEL_84;\n }\n a6 = (unsigned int)v20;\n v21 = 1;\n v10 = 1LL;\n while ( 1 )\n {\n v22 = (unsigned int)(v20 - v21);\n if ( (int)v22 <= 3 )\n {\n if ( (int)a6 <= (int)v22 )\n goto LABEL_17;\n LODWORD(v29) = v20 - v21;\n }\n else\n {\n v23 = v20 - v21;\n v24 = 1;\n LODWORD(a4) = 1;\n do\n {\n v25 = v22 - v24;\n if ( (int)v22 - v24 <= 3 )\n {\n if ( v25 < v23 )\n v23 = v25 + 1;\n }\n else\n {\n v191 = v23;\n v186 = a4;\n v170 = v22;\n v163 = a5;\n v153 = a6;\n v142 = v22 - v24;\n v26 = ((__int64 (*)(void))sub_11C0)();\n v23 = v191;\n v27 = v142;\n a6 = v153;\n a5 = v163;\n v22 = v170;\n v10 = (unsigned int)v10;\n LODWORD(a4) = v186;\n if ( v26 < v191 )\n {\n v146 = v26;\n sub_11C0(v27, (unsigned int)v10, v170, v186, v163, v153);\n LODWORD(a4) = v186;\n v10 = (unsigned int)v10;\n v22 = v170;\n a5 = v163;\n a6 = v153;\n v23 = v146 + 1;\n }\n }\n a4 = (unsigned int)(a4 + 1);\n if ( (int)v22 < (int)a4 )\n break;\n v24 = a4 * a4;\n }\n while ( (int)v22 >= (int)a4 * (int)a4 );\n if ( (int)a6 <= v23 )\n goto LABEL_17;\n v29 = (unsigned int)v22;\n a4 = 1LL;\n v30 = (unsigned int)(v22 - 1);\n if ( (int)v30 > 3 )\n {\nLABEL_35:\n v187 = a4;\n v177 = v29;\n v164 = v22;\n v154 = a5;\n v31 = sub_11C0(v30, v10, v22, a4, a5, v29);\n v29 = v177;\n a5 = v154;\n v22 = v164;\n v10 = (unsigned int)v10;\n LODWORD(a4) = v187;\n if ( (int)v177 > v31 )\n {\n v145 = v31;\n sub_11C0((unsigned int)v30, (unsigned int)v10, v164, v187, v154, v177);\n LODWORD(a4) = v187;\n v10 = (unsigned int)v10;\n v22 = v164;\n a5 = v154;\n v29 = (unsigned int)(v145 + 1);\n }\n goto LABEL_37;\n }\n while ( 1 )\n {\n if ( (int)v29 > (int)v30 )\n v29 = (unsigned int)(v30 + 1);\nLABEL_37:\n a4 = (unsigned int)(a4 + 1);\n if ( (int)v22 < (int)a4 || (int)v22 < (int)a4 * (int)a4 )\n break;\n v30 = (unsigned int)(v22 - a4 * a4);\n if ( (int)v30 > 3 )\n goto LABEL_35;\n }\n }\n a6 = (unsigned int)(v29 + 1);\nLABEL_17:\n v10 = (unsigned int)(v10 + 1);\n if ( v20 >= (int)v10 )\n {\n v21 = v10 * v10;\n if ( v20 >= (int)v10 * (int)v10 )\n continue;\n }\n if ( (int)a6 >= (int)a5 )\n goto LABEL_20;\n a4 = v14;\n v32 = (unsigned int)v20;\n v33 = 1;\n v34 = 1;\n v10 = v18;\n a6 = v13;\n v35 = v20;\n while ( 1 )\n {\n v36 = v35 - v33;\n if ( v35 - v33 <= 3 )\n {\n if ( (int)v32 <= v36 )\n goto LABEL_54;\n LODWORD(v43) = v35 - v33;\n }\n else\n {\n v37 = (unsigned int)v36;\n v38 = 1;\n v39 = 1;\n do\n {\n v40 = (unsigned int)(v36 - v38);\n if ( (int)v40 <= 3 )\n {\n if ( (int)v37 > (int)v40 )\n v37 = (unsigned int)(v40 + 1);\n }\n else\n {\n v188 = a6;\n v178 = v37;\n v171 = v32;\n v155 = a4;\n v143 = v36 - v38;\n v41 = sub_11C0(v40, v10, v37, a4, v32, a6);\n v37 = v178;\n v42 = v143;\n a4 = v155;\n v10 = (unsigned int)v10;\n v32 = v171;\n a6 = v188;\n if ( (int)v178 > v41 )\n {\n v147 = v41;\n sub_11C0(v42, (unsigned int)v10, v178, v155, v171, v188);\n a6 = v188;\n v32 = v171;\n v10 = (unsigned int)v10;\n a4 = v155;\n v37 = (unsigned int)(v147 + 1);\n }\n }\n if ( v36 < ++v39 )\n break;\n v38 = v39 * v39;\n }\n while ( v36 >= v39 * v39 );\n if ( (int)v32 <= (int)v37 )\n goto LABEL_54;\n v43 = (unsigned int)v36;\n v44 = 1;\n v45 = (unsigned int)(v36 - 1);\n if ( (int)v45 > 3 )\n {\nLABEL_63:\n v179 = a6;\n v172 = v43;\n v156 = a4;\n v46 = sub_11C0(v45, v10, v37, a4, v43, a6);\n v43 = v172;\n a4 = v156;\n v10 = (unsigned int)v10;\n a6 = v179;\n if ( (int)v172 > v46 )\n {\n v148 = v46;\n sub_11C0((unsigned int)v45, (unsigned int)v10, v37, v156, v172, v179);\n a6 = v179;\n v10 = (unsigned int)v10;\n a4 = v156;\n v43 = (unsigned int)(v148 + 1);\n }\n goto LABEL_65;\n }\n while ( 1 )\n {\n if ( (int)v43 > (int)v45 )\n v43 = (unsigned int)(v45 + 1);\nLABEL_65:\n if ( v36 < ++v44 || v36 < v44 * v44 )\n break;\n v45 = (unsigned int)(v36 - v44 * v44);\n if ( (int)v45 > 3 )\n goto LABEL_63;\n }\n }\n v32 = (unsigned int)(v43 + 1);\nLABEL_54:\n if ( v35 >= ++v34 )\n {\n v33 = v34 * v34;\n if ( v35 >= v34 * v34 )\n continue;\n }\n v14 = a4;\n v18 = v10;\n v13 = a6;\nLABEL_44:\n a5 = (unsigned int)(v32 + 1);\n goto LABEL_20;\n }\n }\n }\n if ( v16 < v11 )\n {\n v47 = v15 - v12;\n goto LABEL_72;\n }\nLABEL_23:\n if ( v15 < (int)++v14 )\n break;\n v12 = v14 * v14;\n }\n while ( v15 >= (int)(v14 * v14) );\n v6 = v139;\n v9 = v13;\n v8 = v136;\n if ( v11 >= v139 )\n goto LABEL_26;\n v185 = v136;\n v77 = 1;\n v190 = v9;\n v78 = 1;\n v79 = v15;\n v80 = v15;\nLABEL_134:\n v81 = v80 - v77;\n if ( v80 - v77 <= 3 )\n {\n if ( v79 <= v81 )\n goto LABEL_152;\n v120 = v80 - v77;\nLABEL_212:\n v79 = v120 + 1;\n goto LABEL_152;\n }\n v140 = v79;\n v82 = 1;\n v83 = 1;\n v133 = v80;\n v84 = v81;\n v137 = v78;\n v85 = v81;\n while ( 1 )\n {\n v86 = v85 - v82;\n if ( v85 - v82 > 3 )\n break;\n if ( v84 > v86 )\n {\n v104 = v85 - v82;\n goto LABEL_171;\n }\nLABEL_149:\n if ( v85 >= (int)++v83 )\n {\n v82 = v83 * v83;\n if ( v85 >= (int)(v83 * v83) )\n continue;\n }\n v79 = v140;\n v98 = v84;\n v99 = v85;\n v80 = v133;\n v78 = v137;\n if ( v140 > v98 )\n {\n v138 = v133;\n v121 = 1;\n v122 = v99;\n v141 = v78;\n v123 = 1;\n v124 = v99;\n do\n {\n v125 = v122 - v121;\n if ( v122 - v121 <= 3 )\n {\n if ( v125 < v124 )\n v124 = v125 + 1;\n }\n else\n {\n v126 = (unsigned int)v125;\n v127 = 1;\n v128 = 1;\n do\n {\n v129 = v125 - v127;\n if ( v125 - v127 <= 3 )\n {\n if ( (int)v129 < (int)v126 )\n v126 = v129 + 1;\n }\n else\n {\n v134 = v126;\n v130 = sub_11C0(v129, v10, v126, a4, a5, a6);\n v126 = v134;\n if ( v130 < (int)v134 )\n {\n v135 = v130;\n sub_11C0(v129, v10, v126, a4, a5, a6);\n v126 = (unsigned int)(v135 + 1);\n }\n }\n if ( v125 < ++v128 )\n break;\n v127 = v128 * v128;\n }\n while ( v125 >= v128 * v128 );\n if ( (int)v126 < v124 )\n v124 = sub_11C0((unsigned int)v125, v10, v126, a4, a5, a6) + 1;\n }\n if ( v122 < ++v123 )\n break;\n v121 = v123 * v123;\n }\n while ( v122 >= v123 * v123 );\n v120 = v124;\n v80 = v138;\n v78 = v141;\n goto LABEL_212;\n }\nLABEL_152:\n if ( v80 < ++v78 || (v77 = v78 * v78, v80 < v78 * v78) )\n {\n v72 = v79;\n v8 = v185;\n v9 = v190;\nLABEL_155:\n v6 = v72 + 1;\n goto LABEL_26;\n }\n goto LABEL_134;\n }\n v10 = v83;\n v87 = v85 - v82;\n v88 = v85;\n v89 = 1;\n v90 = v84;\n v91 = 1;\n while ( 1 )\n {\n v92 = v86 - v89;\n if ( v86 - v89 <= 3 )\n {\n if ( v92 >= v87 )\n goto LABEL_146;\n LODWORD(v100) = v86 - v89;\n }\n else\n {\n a4 = (unsigned int)v92;\n v93 = 1;\n v94 = 1LL;\n do\n {\n v95 = (unsigned int)(v92 - v93);\n if ( (int)v95 <= 3 )\n {\n if ( (int)a4 > (int)v95 )\n a4 = (unsigned int)(v95 + 1);\n }\n else\n {\n v176 = v94;\n v161 = a4;\n v149 = v92 - v93;\n v96 = sub_11C0(v95, v10, v94, a4, a5, a6);\n a4 = v161;\n v97 = v149;\n v10 = (unsigned int)v10;\n LODWORD(v94) = v176;\n if ( (int)v161 > v96 )\n {\n v151 = v96;\n sub_11C0(v97, (unsigned int)v10, v176, v161, a5, a6);\n LODWORD(v94) = v176;\n v10 = (unsigned int)v10;\n a4 = (unsigned int)(v151 + 1);\n }\n }\n v94 = (unsigned int)(v94 + 1);\n if ( v92 < (int)v94 )\n break;\n v93 = v94 * v94;\n }\n while ( v92 >= (int)v94 * (int)v94 );\n if ( (int)a4 >= v87 )\n goto LABEL_146;\n v100 = (unsigned int)v92;\n v101 = 1;\n v102 = (unsigned int)(v92 - 1);\n if ( (int)v102 > 3 )\n {\nLABEL_162:\n v162 = v100;\n v103 = sub_11C0(v102, v10, v100, a4, a5, a6);\n v100 = v162;\n v10 = (unsigned int)v10;\n if ( (int)v162 > v103 )\n {\n v152 = v103;\n sub_11C0((unsigned int)v102, (unsigned int)v10, v162, a4, a5, a6);\n v10 = (unsigned int)v10;\n v100 = (unsigned int)(v152 + 1);\n }\n goto LABEL_164;\n }\n while ( 1 )\n {\n if ( (int)v100 > (int)v102 )\n v100 = (unsigned int)(v102 + 1);\nLABEL_164:\n if ( v92 < ++v101 || v92 < v101 * v101 )\n break;\n v102 = (unsigned int)(v92 - v101 * v101);\n if ( (int)v102 > 3 )\n goto LABEL_162;\n }\n }\n v87 = v100 + 1;\nLABEL_146:\n if ( v86 >= ++v91 )\n {\n v89 = v91 * v91;\n if ( v86 >= v91 * v91 )\n continue;\n }\n v84 = v90;\n v85 = v88;\n v83 = v10;\n if ( v84 <= v87 )\n goto LABEL_149;\n v105 = 1;\n v106 = v86;\n v150 = v85;\n v107 = 1;\n v108 = v86;\n while ( 1 )\n {\n v109 = v106 - v105;\n if ( v106 - v105 <= 3 )\n {\n if ( v108 <= v109 )\n goto LABEL_181;\n v115 = v106 - v105;\n }\n else\n {\n v110 = (unsigned int)v109;\n v111 = 1;\n v112 = 1;\n do\n {\n v113 = v109 - v111;\n if ( v109 - v111 <= 3 )\n {\n if ( (int)v110 > (int)v113 )\n v110 = v113 + 1;\n }\n else\n {\n v167 = v110;\n v114 = sub_11C0(v113, v10, v110, a4, a5, a6);\n v110 = v167;\n if ( (int)v167 > v114 )\n {\n v168 = v114;\n sub_11C0(v113, v10, v110, a4, a5, a6);\n v110 = (unsigned int)(v168 + 1);\n }\n }\n if ( v109 < ++v112 )\n break;\n v111 = v112 * v112;\n }\n while ( v109 >= v112 * v112 );\n if ( v108 <= (int)v110 )\n goto LABEL_181;\n v115 = v109;\n v116 = 1;\n v117 = v109 - 1;\n if ( v109 - 1 > 3 )\n {\nLABEL_190:\n v118 = sub_11C0(v117, v10, v110, a4, a5, a6);\n if ( v118 < v115 )\n {\n v169 = v118;\n sub_11C0(v117, v10, v110, a4, a5, a6);\n v115 = v169 + 1;\n }\n goto LABEL_192;\n }\n while ( 1 )\n {\n if ( (int)v117 < v115 )\n v115 = v117 + 1;\nLABEL_192:\n if ( v109 < ++v116 )\n break;\n v119 = v116 * v116;\n if ( v109 < v116 * v116 )\n break;\n v117 = v109 - v119;\n if ( v109 - v119 > 3 )\n goto LABEL_190;\n }\n }\n v108 = v115 + 1;\nLABEL_181:\n if ( v106 >= ++v107 )\n {\n v105 = v107 * v107;\n if ( v106 >= v107 * v107 )\n continue;\n }\n v104 = v108;\n v83 = v10;\n v85 = v150;\nLABEL_171:\n v84 = v104 + 1;\n goto LABEL_149;\n }\n }\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11C0(int a1, long long a2, long long a3, long long a4,\n long long a5, long long a6) {\n unsigned int v6;\n int v7;\n int v8;\n int v9;\n long long v10;\n int v11;\n int v12;\n unsigned int v13;\n unsigned int v14;\n int v15;\n int v16;\n int v17;\n unsigned int v18;\n int v19;\n int v20;\n int v21;\n long long v22;\n int v23;\n int v24;\n int v25;\n int v26;\n long long v27;\n long long v29;\n long long v30;\n int v31;\n long long v32;\n int v33;\n int v34;\n int v35;\n int v36;\n long long v37;\n int v38;\n int v39;\n long long v40;\n int v41;\n long long v42;\n long long v43;\n int v44;\n long long v45;\n int v46;\n int v47;\n int v48;\n int v49;\n long long v50;\n int v51;\n int v52;\n int v53;\n int v54;\n int v55;\n int v56;\n long long v57;\n int v58;\n long long v59;\n int v60;\n long long v61;\n int v62;\n int v63;\n int v64;\n int v65;\n int v66;\n int v67;\n int v68;\n unsigned int v69;\n int v70;\n int v71;\n int v72;\n int v73;\n unsigned int v74;\n int v75;\n int v76;\n int v77;\n int v78;\n int v79;\n int v80;\n int v81;\n int v82;\n unsigned int v83;\n int v84;\n int v85;\n int v86;\n int v87;\n int v88;\n int v89;\n int v90;\n int v91;\n int v92;\n int v93;\n long long v94;\n long long v95;\n int v96;\n long long v97;\n int v98;\n int v99;\n long long v100;\n int v101;\n long long v102;\n int v103;\n int v104;\n int v105;\n int v106;\n int v107;\n int v108;\n int v109;\n long long v110;\n int v111;\n int v112;\n unsigned int v113;\n int v114;\n int v115;\n int v116;\n unsigned int v117;\n int v118;\n int v119;\n int v120;\n int v121;\n int v122;\n int v123;\n int v124;\n int v125;\n long long v126;\n int v127;\n int v128;\n unsigned int v129;\n int v130;\n int v131;\n unsigned int v132;\n int v133;\n unsigned int v134;\n int v135;\n int v136;\n int v137;\n int v138;\n signed int v139;\n int v140;\n int v141;\n unsigned int v142;\n unsigned int v143;\n unsigned int v144;\n int v145;\n int v146;\n int v147;\n int v148;\n unsigned int v149;\n int v150;\n int v151;\n int v152;\n unsigned int v153;\n unsigned int v154;\n unsigned int v155;\n unsigned int v156;\n unsigned int v157;\n int v158;\n int v159;\n int v160;\n unsigned int v161;\n unsigned int v162;\n unsigned int v163;\n unsigned int v164;\n unsigned int v165;\n int v166;\n unsigned int v167;\n int v168;\n int v169;\n unsigned int v170;\n unsigned int v171;\n unsigned int v172;\n unsigned int v173;\n unsigned int v174;\n int v175;\n unsigned int v176;\n unsigned int v177;\n unsigned int v178;\n unsigned int v179;\n unsigned int v180;\n unsigned int v181;\n unsigned int v182;\n int v183;\n int v184;\n int v185;\n unsigned int v186;\n unsigned int v187;\n unsigned int v188;\n unsigned int v189;\n int v190;\n int v191;\n v6 = a1;\n if (a1 > 0) {\n v7 = 1;\n v8 = 1;\n v9 = a1;\n while (1) {\n v10 = (unsigned int)(v9 - v7);\n if ((int)v10 > 3) break;\n if ((int)v10 < (int)v6) {\n v72 = v9 - v7;\n goto LABEL_155;\n }\n LABEL_26:\n if (v9 >= ++v8) {\n v7 = v8 * v8;\n if (v8 * v8 <= v9) continue;\n }\n return v6;\n }\n v136 = v8;\n v11 = v9 - v7;\n v12 = 1;\n v139 = v6;\n v13 = v9;\n v14 = 1;\n v15 = v10;\n do {\n v16 = v15 - v12;\n if (v15 - v12 > 3) {\n v131 = v11;\n v17 = 1;\n a5 = (unsigned int)v16;\n v18 = 1;\n v19 = v16;\n while (1) {\n v20 = v19 - v17;\n if (v19 - v17 > 3) break;\n if (v20 < (int)a5) {\n LODWORD(v32) = v19 - v17;\n goto LABEL_44;\n }\n LABEL_20:\n if (v19 >= (int)++v18) {\n v17 = v18 * v18;\n if (v19 >= (int)(v18 * v18)) continue;\n }\n v11 = v131;\n if ((int)a5 >= v131) goto LABEL_23;\n v47 = v19;\n v132 = v14;\n v48 = v15;\n v144 = v13;\n v10 = 1LL;\n v49 = 1;\n v50 = 1LL;\n while (1) {\n v51 = v19 - v49;\n if (v19 - v49 > 3) break;\n if (v47 > v51) {\n a5 = (unsigned int)v51;\n goto LABEL_105;\n }\n LABEL_87:\n v50 = (unsigned int)(v50 + 1);\n if (v19 >= (int)v50) {\n v49 = v50 * v50;\n if (v19 >= (int)v50 * (int)v50) continue;\n }\n v14 = v132;\n v13 = v144;\n v15 = v48;\n LABEL_72:\n v11 = v47 + 1;\n goto LABEL_23;\n }\n a5 = (unsigned int)v47;\n v52 = v19 - v49;\n v53 = 1;\n v54 = 1;\n while (2) {\n v55 = v51 - v53;\n if (v51 - v53 <= 3) {\n if (v55 >= v52) goto LABEL_84;\n a4 = (unsigned int)v55;\n } else {\n v10 = (unsigned int)v55;\n v56 = 1;\n a4 = 1LL;\n do {\n v57 = (unsigned int)(v55 - v56);\n if ((int)v57 <= 3) {\n if ((int)v10 > (int)v57) v10 = (unsigned int)(v57 + 1);\n } else {\n v189 = v50;\n v180 = a5;\n v173 = a4;\n v157 = v55 - v56;\n v58 = sub_11C0(v57, v10, v50, a4, a5, a6);\n v10 = (unsigned int)v10;\n v59 = v157;\n LODWORD(a4) = v173;\n a5 = v180;\n v50 = v189;\n if ((int)v10 > v58) {\n v159 = v58;\n sub_11C0(v59, (unsigned int)v10, v189, v173, v180, a6);\n v50 = v189;\n a5 = v180;\n LODWORD(a4) = v173;\n v10 = (unsigned int)(v159 + 1);\n }\n }\n a4 = (unsigned int)(a4 + 1);\n if (v55 < (int)a4) break;\n v56 = a4 * a4;\n } while (v55 >= (int)a4 * (int)a4);\n if ((int)v10 >= v52) {\n LABEL_84:\n if (v51 >= ++v54) {\n v53 = v54 * v54;\n if (v51 >= v54 * v54) continue;\n }\n v47 = a5;\n if ((int)a5 <= v52) goto LABEL_87;\n v175 = v50;\n v63 = 1;\n v158 = v48;\n v64 = 1;\n v166 = v19;\n v65 = v51;\n while (2) {\n v66 = v65 - v63;\n if (v65 - v63 <= 3) {\n if (v51 <= v66) goto LABEL_115;\n v71 = v65 - v63;\n } else {\n a4 = (unsigned int)v66;\n v67 = 1;\n v68 = 1;\n do {\n v69 = v66 - v67;\n if (v66 - v67 <= 3) {\n if ((int)a4 > (int)v69) a4 = v69 + 1;\n } else {\n v182 = a4;\n v70 = sub_11C0(v69, v10, v50, a4, a5, a6);\n a4 = v182;\n if ((int)v182 > v70) {\n v184 = v70;\n sub_11C0(v69, v10, v50, a4, a5, a6);\n a4 = (unsigned int)(v184 + 1);\n }\n }\n if (v66 < ++v68) break;\n v67 = v68 * v68;\n } while (v66 >= v68 * v68);\n if (v51 <= (int)a4) {\n LABEL_115:\n if (v65 < ++v64 || (v63 = v64 * v64, v65 < v64 * v64)) {\n v48 = v158;\n v19 = v166;\n a5 = (unsigned int)v51;\n LODWORD(v50) = v175;\n LABEL_105:\n v47 = a5 + 1;\n goto LABEL_87;\n }\n continue;\n }\n v71 = v66;\n v73 = 1;\n v74 = v66 - 1;\n if (v66 - 1 > 3) {\n LABEL_126:\n v75 = sub_11C0(v74, v10, v50, a4, a5, a6);\n if (v75 < v71) {\n v183 = v75;\n sub_11C0(v74, v10, v50, a4, a5, a6);\n v71 = v183 + 1;\n }\n goto LABEL_128;\n }\n while (1) {\n if ((int)v74 < v71) v71 = v74 + 1;\n LABEL_128:\n if (v66 < ++v73) break;\n v76 = v73 * v73;\n if (v66 < v73 * v73) break;\n v74 = v66 - v76;\n if (v66 - v76 > 3) goto LABEL_126;\n }\n }\n break;\n }\n v51 = v71 + 1;\n goto LABEL_115;\n }\n a4 = (unsigned int)v55;\n v60 = 1;\n v61 = (unsigned int)(v55 - 1);\n if ((int)v61 > 3) {\n LABEL_96:\n v181 = v50;\n v174 = a4;\n v165 = a5;\n v62 = sub_11C0(v61, v10, v50, a4, a5, a6);\n a4 = v174;\n a5 = v165;\n v50 = v181;\n if ((int)v174 > v62) {\n v160 = v62;\n sub_11C0((unsigned int)v61, v10, v181, v174, v165, a6);\n v50 = v181;\n a5 = v165;\n a4 = (unsigned int)(v160 + 1);\n }\n goto LABEL_98;\n }\n while (1) {\n if ((int)a4 > (int)v61) a4 = (unsigned int)(v61 + 1);\n LABEL_98:\n if (v55 < ++v60 || v55 < v60 * v60) break;\n v61 = (unsigned int)(v55 - v60 * v60);\n if ((int)v61 > 3) goto LABEL_96;\n }\n }\n break;\n }\n v52 = a4 + 1;\n goto LABEL_84;\n }\n a6 = (unsigned int)v20;\n v21 = 1;\n v10 = 1LL;\n while (1) {\n v22 = (unsigned int)(v20 - v21);\n if ((int)v22 <= 3) {\n if ((int)a6 <= (int)v22) goto LABEL_17;\n LODWORD(v29) = v20 - v21;\n } else {\n v23 = v20 - v21;\n v24 = 1;\n LODWORD(a4) = 1;\n do {\n v25 = v22 - v24;\n if ((int)v22 - v24 <= 3) {\n if (v25 < v23) v23 = v25 + 1;\n } else {\n v191 = v23;\n v186 = a4;\n v170 = v22;\n v163 = a5;\n v153 = a6;\n v142 = v22 - v24;\n v26 = ((long long (*)(void))sub_11C0)();\n v23 = v191;\n v27 = v142;\n a6 = v153;\n a5 = v163;\n v22 = v170;\n v10 = (unsigned int)v10;\n LODWORD(a4) = v186;\n if (v26 < v191) {\n v146 = v26;\n sub_11C0(v27, (unsigned int)v10, v170, v186, v163, v153);\n LODWORD(a4) = v186;\n v10 = (unsigned int)v10;\n v22 = v170;\n a5 = v163;\n a6 = v153;\n v23 = v146 + 1;\n }\n }\n a4 = (unsigned int)(a4 + 1);\n if ((int)v22 < (int)a4) break;\n v24 = a4 * a4;\n } while ((int)v22 >= (int)a4 * (int)a4);\n if ((int)a6 <= v23) goto LABEL_17;\n v29 = (unsigned int)v22;\n a4 = 1LL;\n v30 = (unsigned int)(v22 - 1);\n if ((int)v30 > 3) {\n LABEL_35:\n v187 = a4;\n v177 = v29;\n v164 = v22;\n v154 = a5;\n v31 = sub_11C0(v30, v10, v22, a4, a5, v29);\n v29 = v177;\n a5 = v154;\n v22 = v164;\n v10 = (unsigned int)v10;\n LODWORD(a4) = v187;\n if ((int)v177 > v31) {\n v145 = v31;\n sub_11C0((unsigned int)v30, (unsigned int)v10, v164, v187, v154,\n v177);\n LODWORD(a4) = v187;\n v10 = (unsigned int)v10;\n v22 = v164;\n a5 = v154;\n v29 = (unsigned int)(v145 + 1);\n }\n goto LABEL_37;\n }\n while (1) {\n if ((int)v29 > (int)v30) v29 = (unsigned int)(v30 + 1);\n LABEL_37:\n a4 = (unsigned int)(a4 + 1);\n if ((int)v22 < (int)a4 || (int)v22 < (int)a4 * (int)a4) break;\n v30 = (unsigned int)(v22 - a4 * a4);\n if ((int)v30 > 3) goto LABEL_35;\n }\n }\n a6 = (unsigned int)(v29 + 1);\n LABEL_17:\n v10 = (unsigned int)(v10 + 1);\n if (v20 >= (int)v10) {\n v21 = v10 * v10;\n if (v20 >= (int)v10 * (int)v10) continue;\n }\n if ((int)a6 >= (int)a5) goto LABEL_20;\n a4 = v14;\n v32 = (unsigned int)v20;\n v33 = 1;\n v34 = 1;\n v10 = v18;\n a6 = v13;\n v35 = v20;\n while (1) {\n v36 = v35 - v33;\n if (v35 - v33 <= 3) {\n if ((int)v32 <= v36) goto LABEL_54;\n LODWORD(v43) = v35 - v33;\n } else {\n v37 = (unsigned int)v36;\n v38 = 1;\n v39 = 1;\n do {\n v40 = (unsigned int)(v36 - v38);\n if ((int)v40 <= 3) {\n if ((int)v37 > (int)v40) v37 = (unsigned int)(v40 + 1);\n } else {\n v188 = a6;\n v178 = v37;\n v171 = v32;\n v155 = a4;\n v143 = v36 - v38;\n v41 = sub_11C0(v40, v10, v37, a4, v32, a6);\n v37 = v178;\n v42 = v143;\n a4 = v155;\n v10 = (unsigned int)v10;\n v32 = v171;\n a6 = v188;\n if ((int)v178 > v41) {\n v147 = v41;\n sub_11C0(v42, (unsigned int)v10, v178, v155, v171, v188);\n a6 = v188;\n v32 = v171;\n v10 = (unsigned int)v10;\n a4 = v155;\n v37 = (unsigned int)(v147 + 1);\n }\n }\n if (v36 < ++v39) break;\n v38 = v39 * v39;\n } while (v36 >= v39 * v39);\n if ((int)v32 <= (int)v37) goto LABEL_54;\n v43 = (unsigned int)v36;\n v44 = 1;\n v45 = (unsigned int)(v36 - 1);\n if ((int)v45 > 3) {\n LABEL_63:\n v179 = a6;\n v172 = v43;\n v156 = a4;\n v46 = sub_11C0(v45, v10, v37, a4, v43, a6);\n v43 = v172;\n a4 = v156;\n v10 = (unsigned int)v10;\n a6 = v179;\n if ((int)v172 > v46) {\n v148 = v46;\n sub_11C0((unsigned int)v45, (unsigned int)v10, v37, v156,\n v172, v179);\n a6 = v179;\n v10 = (unsigned int)v10;\n a4 = v156;\n v43 = (unsigned int)(v148 + 1);\n }\n goto LABEL_65;\n }\n while (1) {\n if ((int)v43 > (int)v45) v43 = (unsigned int)(v45 + 1);\n LABEL_65:\n if (v36 < ++v44 || v36 < v44 * v44) break;\n v45 = (unsigned int)(v36 - v44 * v44);\n if ((int)v45 > 3) goto LABEL_63;\n }\n }\n v32 = (unsigned int)(v43 + 1);\n LABEL_54:\n if (v35 >= ++v34) {\n v33 = v34 * v34;\n if (v35 >= v34 * v34) continue;\n }\n v14 = a4;\n v18 = v10;\n v13 = a6;\n LABEL_44:\n a5 = (unsigned int)(v32 + 1);\n goto LABEL_20;\n }\n }\n }\n if (v16 < v11) {\n v47 = v15 - v12;\n goto LABEL_72;\n }\n LABEL_23:\n if (v15 < (int)++v14) break;\n v12 = v14 * v14;\n } while (v15 >= (int)(v14 * v14));\n v6 = v139;\n v9 = v13;\n v8 = v136;\n if (v11 >= v139) goto LABEL_26;\n v185 = v136;\n v77 = 1;\n v190 = v9;\n v78 = 1;\n v79 = v15;\n v80 = v15;\n LABEL_134:\n v81 = v80 - v77;\n if (v80 - v77 <= 3) {\n if (v79 <= v81) goto LABEL_152;\n v120 = v80 - v77;\n LABEL_212:\n v79 = v120 + 1;\n goto LABEL_152;\n }\n v140 = v79;\n v82 = 1;\n v83 = 1;\n v133 = v80;\n v84 = v81;\n v137 = v78;\n v85 = v81;\n while (1) {\n v86 = v85 - v82;\n if (v85 - v82 > 3) break;\n if (v84 > v86) {\n v104 = v85 - v82;\n goto LABEL_171;\n }\n LABEL_149:\n if (v85 >= (int)++v83) {\n v82 = v83 * v83;\n if (v85 >= (int)(v83 * v83)) continue;\n }\n v79 = v140;\n v98 = v84;\n v99 = v85;\n v80 = v133;\n v78 = v137;\n if (v140 > v98) {\n v138 = v133;\n v121 = 1;\n v122 = v99;\n v141 = v78;\n v123 = 1;\n v124 = v99;\n do {\n v125 = v122 - v121;\n if (v122 - v121 <= 3) {\n if (v125 < v124) v124 = v125 + 1;\n } else {\n v126 = (unsigned int)v125;\n v127 = 1;\n v128 = 1;\n do {\n v129 = v125 - v127;\n if (v125 - v127 <= 3) {\n if ((int)v129 < (int)v126) v126 = v129 + 1;\n } else {\n v134 = v126;\n v130 = sub_11C0(v129, v10, v126, a4, a5, a6);\n v126 = v134;\n if (v130 < (int)v134) {\n v135 = v130;\n sub_11C0(v129, v10, v126, a4, a5, a6);\n v126 = (unsigned int)(v135 + 1);\n }\n }\n if (v125 < ++v128) break;\n v127 = v128 * v128;\n } while (v125 >= v128 * v128);\n if ((int)v126 < v124)\n v124 = sub_11C0((unsigned int)v125, v10, v126, a4, a5, a6) + 1;\n }\n if (v122 < ++v123) break;\n v121 = v123 * v123;\n } while (v122 >= v123 * v123);\n v120 = v124;\n v80 = v138;\n v78 = v141;\n goto LABEL_212;\n }\n LABEL_152:\n if (v80 < ++v78 || (v77 = v78 * v78, v80 < v78 * v78)) {\n v72 = v79;\n v8 = v185;\n v9 = v190;\n LABEL_155:\n v6 = v72 + 1;\n goto LABEL_26;\n }\n goto LABEL_134;\n }\n v10 = v83;\n v87 = v85 - v82;\n v88 = v85;\n v89 = 1;\n v90 = v84;\n v91 = 1;\n while (1) {\n v92 = v86 - v89;\n if (v86 - v89 <= 3) {\n if (v92 >= v87) goto LABEL_146;\n LODWORD(v100) = v86 - v89;\n } else {\n a4 = (unsigned int)v92;\n v93 = 1;\n v94 = 1LL;\n do {\n v95 = (unsigned int)(v92 - v93);\n if ((int)v95 <= 3) {\n if ((int)a4 > (int)v95) a4 = (unsigned int)(v95 + 1);\n } else {\n v176 = v94;\n v161 = a4;\n v149 = v92 - v93;\n v96 = sub_11C0(v95, v10, v94, a4, a5, a6);\n a4 = v161;\n v97 = v149;\n v10 = (unsigned int)v10;\n LODWORD(v94) = v176;\n if ((int)v161 > v96) {\n v151 = v96;\n sub_11C0(v97, (unsigned int)v10, v176, v161, a5, a6);\n LODWORD(v94) = v176;\n v10 = (unsigned int)v10;\n a4 = (unsigned int)(v151 + 1);\n }\n }\n v94 = (unsigned int)(v94 + 1);\n if (v92 < (int)v94) break;\n v93 = v94 * v94;\n } while (v92 >= (int)v94 * (int)v94);\n if ((int)a4 >= v87) goto LABEL_146;\n v100 = (unsigned int)v92;\n v101 = 1;\n v102 = (unsigned int)(v92 - 1);\n if ((int)v102 > 3) {\n LABEL_162:\n v162 = v100;\n v103 = sub_11C0(v102, v10, v100, a4, a5, a6);\n v100 = v162;\n v10 = (unsigned int)v10;\n if ((int)v162 > v103) {\n v152 = v103;\n sub_11C0((unsigned int)v102, (unsigned int)v10, v162, a4, a5, a6);\n v10 = (unsigned int)v10;\n v100 = (unsigned int)(v152 + 1);\n }\n goto LABEL_164;\n }\n while (1) {\n if ((int)v100 > (int)v102) v100 = (unsigned int)(v102 + 1);\n LABEL_164:\n if (v92 < ++v101 || v92 < v101 * v101) break;\n v102 = (unsigned int)(v92 - v101 * v101);\n if ((int)v102 > 3) goto LABEL_162;\n }\n }\n v87 = v100 + 1;\n LABEL_146:\n if (v86 >= ++v91) {\n v89 = v91 * v91;\n if (v86 >= v91 * v91) continue;\n }\n v84 = v90;\n v85 = v88;\n v83 = v10;\n if (v84 <= v87) goto LABEL_149;\n v105 = 1;\n v106 = v86;\n v150 = v85;\n v107 = 1;\n v108 = v86;\n while (1) {\n v109 = v106 - v105;\n if (v106 - v105 <= 3) {\n if (v108 <= v109) goto LABEL_181;\n v115 = v106 - v105;\n } else {\n v110 = (unsigned int)v109;\n v111 = 1;\n v112 = 1;\n do {\n v113 = v109 - v111;\n if (v109 - v111 <= 3) {\n if ((int)v110 > (int)v113) v110 = v113 + 1;\n } else {\n v167 = v110;\n v114 = sub_11C0(v113, v10, v110, a4, a5, a6);\n v110 = v167;\n if ((int)v167 > v114) {\n v168 = v114;\n sub_11C0(v113, v10, v110, a4, a5, a6);\n v110 = (unsigned int)(v168 + 1);\n }\n }\n if (v109 < ++v112) break;\n v111 = v112 * v112;\n } while (v109 >= v112 * v112);\n if (v108 <= (int)v110) goto LABEL_181;\n v115 = v109;\n v116 = 1;\n v117 = v109 - 1;\n if (v109 - 1 > 3) {\n LABEL_190:\n v118 = sub_11C0(v117, v10, v110, a4, a5, a6);\n if (v118 < v115) {\n v169 = v118;\n sub_11C0(v117, v10, v110, a4, a5, a6);\n v115 = v169 + 1;\n }\n goto LABEL_192;\n }\n while (1) {\n if ((int)v117 < v115) v115 = v117 + 1;\n LABEL_192:\n if (v109 < ++v116) break;\n v119 = v116 * v116;\n if (v109 < v116 * v116) break;\n v117 = v109 - v119;\n if (v109 - v119 > 3) goto LABEL_190;\n }\n }\n v108 = v115 + 1;\n LABEL_181:\n if (v106 >= ++v107) {\n v105 = v107 * v107;\n if (v106 >= v107 * v107) continue;\n }\n v104 = v108;\n v83 = v10;\n v85 = v150;\n LABEL_171:\n v84 = v104 + 1;\n goto LABEL_149;\n }\n }\n }\n return v6;\n}", + "ida_pseudo_norm": "long long func0_part_0(int a1, long long a2, long long a3, long long a4,\n long long a5, long long a6) {\n unsigned int v6;\n int v7;\n int v8;\n int v9;\n long long v10;\n int v11;\n int v12;\n unsigned int v13;\n unsigned int v14;\n int v15;\n int v16;\n int v17;\n unsigned int v18;\n int v19;\n int v20;\n int v21;\n long long v22;\n int v23;\n int v24;\n int v25;\n int v26;\n long long v27;\n long long v29;\n long long v30;\n int v31;\n long long v32;\n int v33;\n int v34;\n int v35;\n int v36;\n long long v37;\n int v38;\n int v39;\n long long v40;\n int v41;\n long long v42;\n long long v43;\n int v44;\n long long v45;\n int v46;\n int v47;\n int v48;\n int v49;\n long long v50;\n int v51;\n int v52;\n int v53;\n int v54;\n int v55;\n int v56;\n long long v57;\n int v58;\n long long v59;\n int v60;\n long long v61;\n int v62;\n int v63;\n int v64;\n int v65;\n int v66;\n int v67;\n int v68;\n unsigned int v69;\n int v70;\n int v71;\n int v72;\n int v73;\n unsigned int v74;\n int v75;\n int v76;\n int v77;\n int v78;\n int v79;\n int v80;\n int v81;\n int v82;\n unsigned int v83;\n int v84;\n int v85;\n int v86;\n int v87;\n int v88;\n int v89;\n int v90;\n int v91;\n int v92;\n int v93;\n long long v94;\n long long v95;\n int v96;\n long long v97;\n int v98;\n int v99;\n long long v100;\n int v101;\n long long v102;\n int v103;\n int v104;\n int v105;\n int v106;\n int v107;\n int v108;\n int v109;\n long long v110;\n int v111;\n int v112;\n unsigned int v113;\n int v114;\n int v115;\n int v116;\n unsigned int v117;\n int v118;\n int v119;\n int v120;\n int v121;\n int v122;\n int v123;\n int v124;\n int v125;\n long long v126;\n int v127;\n int v128;\n unsigned int v129;\n int v130;\n int v131;\n unsigned int v132;\n int v133;\n unsigned int v134;\n int v135;\n int v136;\n int v137;\n int v138;\n signed int v139;\n int v140;\n int v141;\n unsigned int v142;\n unsigned int v143;\n unsigned int v144;\n int v145;\n int v146;\n int v147;\n int v148;\n unsigned int v149;\n int v150;\n int v151;\n int v152;\n unsigned int v153;\n unsigned int v154;\n unsigned int v155;\n unsigned int v156;\n unsigned int v157;\n int v158;\n int v159;\n int v160;\n unsigned int v161;\n unsigned int v162;\n unsigned int v163;\n unsigned int v164;\n unsigned int v165;\n int v166;\n unsigned int v167;\n int v168;\n int v169;\n unsigned int v170;\n unsigned int v171;\n unsigned int v172;\n unsigned int v173;\n unsigned int v174;\n int v175;\n unsigned int v176;\n unsigned int v177;\n unsigned int v178;\n unsigned int v179;\n unsigned int v180;\n unsigned int v181;\n unsigned int v182;\n int v183;\n int v184;\n int v185;\n unsigned int v186;\n unsigned int v187;\n unsigned int v188;\n unsigned int v189;\n int v190;\n int v191;\n v6 = a1;\n if (a1 > 0) {\n v7 = 1;\n v8 = 1;\n v9 = a1;\n while (1) {\n v10 = (unsigned int)(v9 - v7);\n if ((int)v10 > 3) break;\n if ((int)v10 < (int)v6) {\n v72 = v9 - v7;\n goto LABEL_155;\n }\n LABEL_26:\n if (v9 >= ++v8) {\n v7 = v8 * v8;\n if (v8 * v8 <= v9) continue;\n }\n return v6;\n }\n v136 = v8;\n v11 = v9 - v7;\n v12 = 1;\n v139 = v6;\n v13 = v9;\n v14 = 1;\n v15 = v10;\n do {\n v16 = v15 - v12;\n if (v15 - v12 > 3) {\n v131 = v11;\n v17 = 1;\n a5 = (unsigned int)v16;\n v18 = 1;\n v19 = v16;\n while (1) {\n v20 = v19 - v17;\n if (v19 - v17 > 3) break;\n if (v20 < (int)a5) {\n LODWORD(v32) = v19 - v17;\n goto LABEL_44;\n }\n LABEL_20:\n if (v19 >= (int)++v18) {\n v17 = v18 * v18;\n if (v19 >= (int)(v18 * v18)) continue;\n }\n v11 = v131;\n if ((int)a5 >= v131) goto LABEL_23;\n v47 = v19;\n v132 = v14;\n v48 = v15;\n v144 = v13;\n v10 = 1LL;\n v49 = 1;\n v50 = 1LL;\n while (1) {\n v51 = v19 - v49;\n if (v19 - v49 > 3) break;\n if (v47 > v51) {\n a5 = (unsigned int)v51;\n goto LABEL_105;\n }\n LABEL_87:\n v50 = (unsigned int)(v50 + 1);\n if (v19 >= (int)v50) {\n v49 = v50 * v50;\n if (v19 >= (int)v50 * (int)v50) continue;\n }\n v14 = v132;\n v13 = v144;\n v15 = v48;\n LABEL_72:\n v11 = v47 + 1;\n goto LABEL_23;\n }\n a5 = (unsigned int)v47;\n v52 = v19 - v49;\n v53 = 1;\n v54 = 1;\n while (2) {\n v55 = v51 - v53;\n if (v51 - v53 <= 3) {\n if (v55 >= v52) goto LABEL_84;\n a4 = (unsigned int)v55;\n } else {\n v10 = (unsigned int)v55;\n v56 = 1;\n a4 = 1LL;\n do {\n v57 = (unsigned int)(v55 - v56);\n if ((int)v57 <= 3) {\n if ((int)v10 > (int)v57) v10 = (unsigned int)(v57 + 1);\n } else {\n v189 = v50;\n v180 = a5;\n v173 = a4;\n v157 = v55 - v56;\n v58 = func0_part_0(v57, v10, v50, a4, a5, a6);\n v10 = (unsigned int)v10;\n v59 = v157;\n LODWORD(a4) = v173;\n a5 = v180;\n v50 = v189;\n if ((int)v10 > v58) {\n v159 = v58;\n func0_part_0(v59, (unsigned int)v10, v189, v173, v180, a6);\n v50 = v189;\n a5 = v180;\n LODWORD(a4) = v173;\n v10 = (unsigned int)(v159 + 1);\n }\n }\n a4 = (unsigned int)(a4 + 1);\n if (v55 < (int)a4) break;\n v56 = a4 * a4;\n } while (v55 >= (int)a4 * (int)a4);\n if ((int)v10 >= v52) {\n LABEL_84:\n if (v51 >= ++v54) {\n v53 = v54 * v54;\n if (v51 >= v54 * v54) continue;\n }\n v47 = a5;\n if ((int)a5 <= v52) goto LABEL_87;\n v175 = v50;\n v63 = 1;\n v158 = v48;\n v64 = 1;\n v166 = v19;\n v65 = v51;\n while (2) {\n v66 = v65 - v63;\n if (v65 - v63 <= 3) {\n if (v51 <= v66) goto LABEL_115;\n v71 = v65 - v63;\n } else {\n a4 = (unsigned int)v66;\n v67 = 1;\n v68 = 1;\n do {\n v69 = v66 - v67;\n if (v66 - v67 <= 3) {\n if ((int)a4 > (int)v69) a4 = v69 + 1;\n } else {\n v182 = a4;\n v70 = func0_part_0(v69, v10, v50, a4, a5, a6);\n a4 = v182;\n if ((int)v182 > v70) {\n v184 = v70;\n func0_part_0(v69, v10, v50, a4, a5, a6);\n a4 = (unsigned int)(v184 + 1);\n }\n }\n if (v66 < ++v68) break;\n v67 = v68 * v68;\n } while (v66 >= v68 * v68);\n if (v51 <= (int)a4) {\n LABEL_115:\n if (v65 < ++v64 || (v63 = v64 * v64, v65 < v64 * v64)) {\n v48 = v158;\n v19 = v166;\n a5 = (unsigned int)v51;\n LODWORD(v50) = v175;\n LABEL_105:\n v47 = a5 + 1;\n goto LABEL_87;\n }\n continue;\n }\n v71 = v66;\n v73 = 1;\n v74 = v66 - 1;\n if (v66 - 1 > 3) {\n LABEL_126:\n v75 = func0_part_0(v74, v10, v50, a4, a5, a6);\n if (v75 < v71) {\n v183 = v75;\n func0_part_0(v74, v10, v50, a4, a5, a6);\n v71 = v183 + 1;\n }\n goto LABEL_128;\n }\n while (1) {\n if ((int)v74 < v71) v71 = v74 + 1;\n LABEL_128:\n if (v66 < ++v73) break;\n v76 = v73 * v73;\n if (v66 < v73 * v73) break;\n v74 = v66 - v76;\n if (v66 - v76 > 3) goto LABEL_126;\n }\n }\n break;\n }\n v51 = v71 + 1;\n goto LABEL_115;\n }\n a4 = (unsigned int)v55;\n v60 = 1;\n v61 = (unsigned int)(v55 - 1);\n if ((int)v61 > 3) {\n LABEL_96:\n v181 = v50;\n v174 = a4;\n v165 = a5;\n v62 = func0_part_0(v61, v10, v50, a4, a5, a6);\n a4 = v174;\n a5 = v165;\n v50 = v181;\n if ((int)v174 > v62) {\n v160 = v62;\n func0_part_0((unsigned int)v61, v10, v181, v174, v165, a6);\n v50 = v181;\n a5 = v165;\n a4 = (unsigned int)(v160 + 1);\n }\n goto LABEL_98;\n }\n while (1) {\n if ((int)a4 > (int)v61) a4 = (unsigned int)(v61 + 1);\n LABEL_98:\n if (v55 < ++v60 || v55 < v60 * v60) break;\n v61 = (unsigned int)(v55 - v60 * v60);\n if ((int)v61 > 3) goto LABEL_96;\n }\n }\n break;\n }\n v52 = a4 + 1;\n goto LABEL_84;\n }\n a6 = (unsigned int)v20;\n v21 = 1;\n v10 = 1LL;\n while (1) {\n v22 = (unsigned int)(v20 - v21);\n if ((int)v22 <= 3) {\n if ((int)a6 <= (int)v22) goto LABEL_17;\n LODWORD(v29) = v20 - v21;\n } else {\n v23 = v20 - v21;\n v24 = 1;\n LODWORD(a4) = 1;\n do {\n v25 = v22 - v24;\n if ((int)v22 - v24 <= 3) {\n if (v25 < v23) v23 = v25 + 1;\n } else {\n v191 = v23;\n v186 = a4;\n v170 = v22;\n v163 = a5;\n v153 = a6;\n v142 = v22 - v24;\n v26 = ((long long (*)(void))func0_part_0)();\n v23 = v191;\n v27 = v142;\n a6 = v153;\n a5 = v163;\n v22 = v170;\n v10 = (unsigned int)v10;\n LODWORD(a4) = v186;\n if (v26 < v191) {\n v146 = v26;\n func0_part_0(v27, (unsigned int)v10, v170, v186, v163, v153);\n LODWORD(a4) = v186;\n v10 = (unsigned int)v10;\n v22 = v170;\n a5 = v163;\n a6 = v153;\n v23 = v146 + 1;\n }\n }\n a4 = (unsigned int)(a4 + 1);\n if ((int)v22 < (int)a4) break;\n v24 = a4 * a4;\n } while ((int)v22 >= (int)a4 * (int)a4);\n if ((int)a6 <= v23) goto LABEL_17;\n v29 = (unsigned int)v22;\n a4 = 1LL;\n v30 = (unsigned int)(v22 - 1);\n if ((int)v30 > 3) {\n LABEL_35:\n v187 = a4;\n v177 = v29;\n v164 = v22;\n v154 = a5;\n v31 = func0_part_0(v30, v10, v22, a4, a5, v29);\n v29 = v177;\n a5 = v154;\n v22 = v164;\n v10 = (unsigned int)v10;\n LODWORD(a4) = v187;\n if ((int)v177 > v31) {\n v145 = v31;\n func0_part_0((unsigned int)v30, (unsigned int)v10, v164, v187,\n v154, v177);\n LODWORD(a4) = v187;\n v10 = (unsigned int)v10;\n v22 = v164;\n a5 = v154;\n v29 = (unsigned int)(v145 + 1);\n }\n goto LABEL_37;\n }\n while (1) {\n if ((int)v29 > (int)v30) v29 = (unsigned int)(v30 + 1);\n LABEL_37:\n a4 = (unsigned int)(a4 + 1);\n if ((int)v22 < (int)a4 || (int)v22 < (int)a4 * (int)a4) break;\n v30 = (unsigned int)(v22 - a4 * a4);\n if ((int)v30 > 3) goto LABEL_35;\n }\n }\n a6 = (unsigned int)(v29 + 1);\n LABEL_17:\n v10 = (unsigned int)(v10 + 1);\n if (v20 >= (int)v10) {\n v21 = v10 * v10;\n if (v20 >= (int)v10 * (int)v10) continue;\n }\n if ((int)a6 >= (int)a5) goto LABEL_20;\n a4 = v14;\n v32 = (unsigned int)v20;\n v33 = 1;\n v34 = 1;\n v10 = v18;\n a6 = v13;\n v35 = v20;\n while (1) {\n v36 = v35 - v33;\n if (v35 - v33 <= 3) {\n if ((int)v32 <= v36) goto LABEL_54;\n LODWORD(v43) = v35 - v33;\n } else {\n v37 = (unsigned int)v36;\n v38 = 1;\n v39 = 1;\n do {\n v40 = (unsigned int)(v36 - v38);\n if ((int)v40 <= 3) {\n if ((int)v37 > (int)v40) v37 = (unsigned int)(v40 + 1);\n } else {\n v188 = a6;\n v178 = v37;\n v171 = v32;\n v155 = a4;\n v143 = v36 - v38;\n v41 = func0_part_0(v40, v10, v37, a4, v32, a6);\n v37 = v178;\n v42 = v143;\n a4 = v155;\n v10 = (unsigned int)v10;\n v32 = v171;\n a6 = v188;\n if ((int)v178 > v41) {\n v147 = v41;\n func0_part_0(v42, (unsigned int)v10, v178, v155, v171,\n v188);\n a6 = v188;\n v32 = v171;\n v10 = (unsigned int)v10;\n a4 = v155;\n v37 = (unsigned int)(v147 + 1);\n }\n }\n if (v36 < ++v39) break;\n v38 = v39 * v39;\n } while (v36 >= v39 * v39);\n if ((int)v32 <= (int)v37) goto LABEL_54;\n v43 = (unsigned int)v36;\n v44 = 1;\n v45 = (unsigned int)(v36 - 1);\n if ((int)v45 > 3) {\n LABEL_63:\n v179 = a6;\n v172 = v43;\n v156 = a4;\n v46 = func0_part_0(v45, v10, v37, a4, v43, a6);\n v43 = v172;\n a4 = v156;\n v10 = (unsigned int)v10;\n a6 = v179;\n if ((int)v172 > v46) {\n v148 = v46;\n func0_part_0((unsigned int)v45, (unsigned int)v10, v37, v156,\n v172, v179);\n a6 = v179;\n v10 = (unsigned int)v10;\n a4 = v156;\n v43 = (unsigned int)(v148 + 1);\n }\n goto LABEL_65;\n }\n while (1) {\n if ((int)v43 > (int)v45) v43 = (unsigned int)(v45 + 1);\n LABEL_65:\n if (v36 < ++v44 || v36 < v44 * v44) break;\n v45 = (unsigned int)(v36 - v44 * v44);\n if ((int)v45 > 3) goto LABEL_63;\n }\n }\n v32 = (unsigned int)(v43 + 1);\n LABEL_54:\n if (v35 >= ++v34) {\n v33 = v34 * v34;\n if (v35 >= v34 * v34) continue;\n }\n v14 = a4;\n v18 = v10;\n v13 = a6;\n LABEL_44:\n a5 = (unsigned int)(v32 + 1);\n goto LABEL_20;\n }\n }\n }\n if (v16 < v11) {\n v47 = v15 - v12;\n goto LABEL_72;\n }\n LABEL_23:\n if (v15 < (int)++v14) break;\n v12 = v14 * v14;\n } while (v15 >= (int)(v14 * v14));\n v6 = v139;\n v9 = v13;\n v8 = v136;\n if (v11 >= v139) goto LABEL_26;\n v185 = v136;\n v77 = 1;\n v190 = v9;\n v78 = 1;\n v79 = v15;\n v80 = v15;\n LABEL_134:\n v81 = v80 - v77;\n if (v80 - v77 <= 3) {\n if (v79 <= v81) goto LABEL_152;\n v120 = v80 - v77;\n LABEL_212:\n v79 = v120 + 1;\n goto LABEL_152;\n }\n v140 = v79;\n v82 = 1;\n v83 = 1;\n v133 = v80;\n v84 = v81;\n v137 = v78;\n v85 = v81;\n while (1) {\n v86 = v85 - v82;\n if (v85 - v82 > 3) break;\n if (v84 > v86) {\n v104 = v85 - v82;\n goto LABEL_171;\n }\n LABEL_149:\n if (v85 >= (int)++v83) {\n v82 = v83 * v83;\n if (v85 >= (int)(v83 * v83)) continue;\n }\n v79 = v140;\n v98 = v84;\n v99 = v85;\n v80 = v133;\n v78 = v137;\n if (v140 > v98) {\n v138 = v133;\n v121 = 1;\n v122 = v99;\n v141 = v78;\n v123 = 1;\n v124 = v99;\n do {\n v125 = v122 - v121;\n if (v122 - v121 <= 3) {\n if (v125 < v124) v124 = v125 + 1;\n } else {\n v126 = (unsigned int)v125;\n v127 = 1;\n v128 = 1;\n do {\n v129 = v125 - v127;\n if (v125 - v127 <= 3) {\n if ((int)v129 < (int)v126) v126 = v129 + 1;\n } else {\n v134 = v126;\n v130 = func0_part_0(v129, v10, v126, a4, a5, a6);\n v126 = v134;\n if (v130 < (int)v134) {\n v135 = v130;\n func0_part_0(v129, v10, v126, a4, a5, a6);\n v126 = (unsigned int)(v135 + 1);\n }\n }\n if (v125 < ++v128) break;\n v127 = v128 * v128;\n } while (v125 >= v128 * v128);\n if ((int)v126 < v124)\n v124 =\n func0_part_0((unsigned int)v125, v10, v126, a4, a5, a6) + 1;\n }\n if (v122 < ++v123) break;\n v121 = v123 * v123;\n } while (v122 >= v123 * v123);\n v120 = v124;\n v80 = v138;\n v78 = v141;\n goto LABEL_212;\n }\n LABEL_152:\n if (v80 < ++v78 || (v77 = v78 * v78, v80 < v78 * v78)) {\n v72 = v79;\n v8 = v185;\n v9 = v190;\n LABEL_155:\n v6 = v72 + 1;\n goto LABEL_26;\n }\n goto LABEL_134;\n }\n v10 = v83;\n v87 = v85 - v82;\n v88 = v85;\n v89 = 1;\n v90 = v84;\n v91 = 1;\n while (1) {\n v92 = v86 - v89;\n if (v86 - v89 <= 3) {\n if (v92 >= v87) goto LABEL_146;\n LODWORD(v100) = v86 - v89;\n } else {\n a4 = (unsigned int)v92;\n v93 = 1;\n v94 = 1LL;\n do {\n v95 = (unsigned int)(v92 - v93);\n if ((int)v95 <= 3) {\n if ((int)a4 > (int)v95) a4 = (unsigned int)(v95 + 1);\n } else {\n v176 = v94;\n v161 = a4;\n v149 = v92 - v93;\n v96 = func0_part_0(v95, v10, v94, a4, a5, a6);\n a4 = v161;\n v97 = v149;\n v10 = (unsigned int)v10;\n LODWORD(v94) = v176;\n if ((int)v161 > v96) {\n v151 = v96;\n func0_part_0(v97, (unsigned int)v10, v176, v161, a5, a6);\n LODWORD(v94) = v176;\n v10 = (unsigned int)v10;\n a4 = (unsigned int)(v151 + 1);\n }\n }\n v94 = (unsigned int)(v94 + 1);\n if (v92 < (int)v94) break;\n v93 = v94 * v94;\n } while (v92 >= (int)v94 * (int)v94);\n if ((int)a4 >= v87) goto LABEL_146;\n v100 = (unsigned int)v92;\n v101 = 1;\n v102 = (unsigned int)(v92 - 1);\n if ((int)v102 > 3) {\n LABEL_162:\n v162 = v100;\n v103 = func0_part_0(v102, v10, v100, a4, a5, a6);\n v100 = v162;\n v10 = (unsigned int)v10;\n if ((int)v162 > v103) {\n v152 = v103;\n func0_part_0((unsigned int)v102, (unsigned int)v10, v162, a4, a5,\n a6);\n v10 = (unsigned int)v10;\n v100 = (unsigned int)(v152 + 1);\n }\n goto LABEL_164;\n }\n while (1) {\n if ((int)v100 > (int)v102) v100 = (unsigned int)(v102 + 1);\n LABEL_164:\n if (v92 < ++v101 || v92 < v101 * v101) break;\n v102 = (unsigned int)(v92 - v101 * v101);\n if ((int)v102 > 3) goto LABEL_162;\n }\n }\n v87 = v100 + 1;\n LABEL_146:\n if (v86 >= ++v91) {\n v89 = v91 * v91;\n if (v86 >= v91 * v91) continue;\n }\n v84 = v90;\n v85 = v88;\n v83 = v10;\n if (v84 <= v87) goto LABEL_149;\n v105 = 1;\n v106 = v86;\n v150 = v85;\n v107 = 1;\n v108 = v86;\n while (1) {\n v109 = v106 - v105;\n if (v106 - v105 <= 3) {\n if (v108 <= v109) goto LABEL_181;\n v115 = v106 - v105;\n } else {\n v110 = (unsigned int)v109;\n v111 = 1;\n v112 = 1;\n do {\n v113 = v109 - v111;\n if (v109 - v111 <= 3) {\n if ((int)v110 > (int)v113) v110 = v113 + 1;\n } else {\n v167 = v110;\n v114 = func0_part_0(v113, v10, v110, a4, a5, a6);\n v110 = v167;\n if ((int)v167 > v114) {\n v168 = v114;\n func0_part_0(v113, v10, v110, a4, a5, a6);\n v110 = (unsigned int)(v168 + 1);\n }\n }\n if (v109 < ++v112) break;\n v111 = v112 * v112;\n } while (v109 >= v112 * v112);\n if (v108 <= (int)v110) goto LABEL_181;\n v115 = v109;\n v116 = 1;\n v117 = v109 - 1;\n if (v109 - 1 > 3) {\n LABEL_190:\n v118 = func0_part_0(v117, v10, v110, a4, a5, a6);\n if (v118 < v115) {\n v169 = v118;\n func0_part_0(v117, v10, v110, a4, a5, a6);\n v115 = v169 + 1;\n }\n goto LABEL_192;\n }\n while (1) {\n if ((int)v117 < v115) v115 = v117 + 1;\n LABEL_192:\n if (v109 < ++v116) break;\n v119 = v116 * v116;\n if (v109 < v116 * v116) break;\n v117 = v109 - v119;\n if (v109 - v119 > 3) goto LABEL_190;\n }\n }\n v108 = v115 + 1;\n LABEL_181:\n if (v106 >= ++v107) {\n v105 = v107 * v107;\n if (v106 >= v107 * v107) continue;\n }\n v104 = v108;\n v83 = v10;\n v85 = v150;\n LABEL_171:\n v84 = v104 + 1;\n goto LABEL_149;\n }\n }\n }\n return v6;\n}" + }, + { + "index": 326, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char word[50];\n\n int count;\n\n} WordCount;\n\n\n\n", + "func": "const char* func0(int n, const char* test_list[]) {\n static WordCount words[100];\n int unique = 0;\n for (int i = 0; i < n; i++) {\n const char* str = test_list[i];\n char word[50];\n int pos = 0;\n while (*str) {\n if (!isspace(*str)) {\n word[pos++] = *str;\n }\n else {\n if (pos > 0) {\n word[pos] = '\\0';\n int found = 0;\n for (int j = 0; j < unique; j++) {\n if (strcmp(words[j].word, word) == 0) {\n words[j].count++;\n found = 1;\n break;\n }\n }\n if (!found) {\n strcpy(words[unique].word, word);\n words[unique].count = 1;\n unique++;\n }\n pos = 0;\n }\n }\n str++;\n }\n if (pos > 0) {\n word[pos] = '\\0';\n int found = 0;\n for (int j = 0; j < unique; j++) {\n if (strcmp(words[j].word, word) == 0) {\n words[j].count++;\n found = 1;\n break;\n }\n }\n if (!found) {\n strcpy(words[unique].word, word);\n words[unique].count = 1;\n unique++;\n }\n }\n }\n int max = 0;\n int index = 0;\n for (int i = 0; i < unique; i++) {\n if (words[i].count > max) {\n max = words[i].count;\n index = i;\n }\n }\n return words[index].word;\n}", + "test": "int main(){\n\n const char* test1[] = {\"UTS is best for RTF\", \"RTF love UTS\", \"UTS is best\"};\n\n assert(strcmp(func0(3, test1), \"UTS\") == 0);\n\n \n\n const char* test2[] = {\"Its been a great year\", \"this year is so worse\", \"this year is okay\"};\n\n assert(strcmp(func0(3, test2), \"year\") == 0);\n\n \n\n const char* test3[] = {\"Families can be reunited\", \"people can be reunited\", \"Tasks can be achieved \"};\n\n assert(strcmp(func0(3, test3), \"can\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nadd $0xffffffffffffff80,%rsp\nmov %edi,-0x74(%rbp)\nmov %rsi,-0x80(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovl $0x0,-0x70(%rbp)\nmovl $0x0,-0x6c(%rbp)\njmpq 14ab \nmov -0x6c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x80(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov %rax,-0x48(%rbp)\nmovl $0x0,-0x68(%rbp)\njmpq 1386 \ncallq 10d0 <__ctype_b_loc@plt>\nmov (%rax),%rdx\nmov -0x48(%rbp),%rax\nmovzbl (%rax),%eax\nmovsbq %al,%rax\nadd %rax,%rax\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x2000,%eax\ntest %eax,%eax\njne 1268 \nmov -0x68(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x68(%rbp)\nmov -0x48(%rbp),%rdx\nmovzbl (%rdx),%edx\ncltq\nmov %dl,-0x40(%rbp,%rax,1)\njmpq 1381 \ncmpl $0x0,-0x68(%rbp)\njle 1381 \nmov -0x68(%rbp),%eax\ncltq\nmovb $0x0,-0x40(%rbp,%rax,1)\nmovl $0x0,-0x64(%rbp)\nmovl $0x0,-0x60(%rbp)\njmpq 1312 \nmov -0x60(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x3,%rax\nsub %rdx,%rax\nshl $0x3,%rax\nlea 0x2d96(%rip),%rdx\nadd %rax,%rdx\nlea -0x40(%rbp),%rax\nmov %rax,%rsi\nmov %rdx,%rdi\ncallq 10c0 \ntest %eax,%eax\njne 130e \nmov -0x60(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x3,%rax\nsub %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nlea 0x2d96(%rip),%rax\nmov (%rdx,%rax,1),%eax\nlea 0x1(%rax),%ecx\nmov -0x60(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x3,%rax\nsub %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nlea 0x2d72(%rip),%rax\nmov %ecx,(%rdx,%rax,1)\nmovl $0x1,-0x64(%rbp)\njmp 131e \naddl $0x1,-0x60(%rbp)\nmov -0x60(%rbp),%eax\ncmp -0x70(%rbp),%eax\njl 128f \ncmpl $0x0,-0x64(%rbp)\njne 137a \nmov -0x70(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x3,%rax\nsub %rdx,%rax\nshl $0x3,%rax\nlea 0x2d01(%rip),%rdx\nadd %rax,%rdx\nlea -0x40(%rbp),%rax\nmov %rax,%rsi\nmov %rdx,%rdi\ncallq 1090 \nmov -0x70(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x3,%rax\nsub %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nlea 0x2d05(%rip),%rax\nmovl $0x1,(%rdx,%rax,1)\naddl $0x1,-0x70(%rbp)\nmovl $0x0,-0x68(%rbp)\naddq $0x1,-0x48(%rbp)\nmov -0x48(%rbp),%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 1225 \ncmpl $0x0,-0x68(%rbp)\njle 14a7 \nmov -0x68(%rbp),%eax\ncltq\nmovb $0x0,-0x40(%rbp,%rax,1)\nmovl $0x0,-0x5c(%rbp)\nmovl $0x0,-0x58(%rbp)\njmpq 143f \nmov -0x58(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x3,%rax\nsub %rdx,%rax\nshl $0x3,%rax\nlea 0x2c69(%rip),%rdx\nadd %rax,%rdx\nlea -0x40(%rbp),%rax\nmov %rax,%rsi\nmov %rdx,%rdi\ncallq 10c0 \ntest %eax,%eax\njne 143b \nmov -0x58(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x3,%rax\nsub %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nlea 0x2c69(%rip),%rax\nmov (%rdx,%rax,1),%eax\nlea 0x1(%rax),%ecx\nmov -0x58(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x3,%rax\nsub %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nlea 0x2c45(%rip),%rax\nmov %ecx,(%rdx,%rax,1)\nmovl $0x1,-0x5c(%rbp)\njmp 144b \naddl $0x1,-0x58(%rbp)\nmov -0x58(%rbp),%eax\ncmp -0x70(%rbp),%eax\njl 13bc \ncmpl $0x0,-0x5c(%rbp)\njne 14a7 \nmov -0x70(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x3,%rax\nsub %rdx,%rax\nshl $0x3,%rax\nlea 0x2bd4(%rip),%rdx\nadd %rax,%rdx\nlea -0x40(%rbp),%rax\nmov %rax,%rsi\nmov %rdx,%rdi\ncallq 1090 \nmov -0x70(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x3,%rax\nsub %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nlea 0x2bd8(%rip),%rax\nmovl $0x1,(%rdx,%rax,1)\naddl $0x1,-0x70(%rbp)\naddl $0x1,-0x6c(%rbp)\nmov -0x6c(%rbp),%eax\ncmp -0x74(%rbp),%eax\njl 11fe \nmovl $0x0,-0x54(%rbp)\nmovl $0x0,-0x50(%rbp)\nmovl $0x0,-0x4c(%rbp)\njmp 1522 \nmov -0x4c(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x3,%rax\nsub %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nlea 0x2b88(%rip),%rax\nmov (%rdx,%rax,1),%eax\ncmp %eax,-0x54(%rbp)\njge 151e \nmov -0x4c(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x3,%rax\nsub %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nlea 0x2b62(%rip),%rax\nmov (%rdx,%rax,1),%eax\nmov %eax,-0x54(%rbp)\nmov -0x4c(%rbp),%eax\nmov %eax,-0x50(%rbp)\naddl $0x1,-0x4c(%rbp)\nmov -0x4c(%rbp),%eax\ncmp -0x70(%rbp),%eax\njl 14ce \nmov -0x50(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x3,%rax\nsub %rdx,%rax\nshl $0x3,%rax\nlea 0x2afb(%rip),%rdx\nadd %rdx,%rax\nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 155c \ncallq 10a0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nadd rsp, 0FFFFFFFFFFFFFF80h\nmov [rbp+var_74], edi\nmov [rbp+var_80], rsi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_70], 0\nmov [rbp+var_6C], 0\njmp loc_14AB\nloc_11FE:\nmov eax, [rbp+var_6C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_80]\nadd rax, rdx\nmov rax, [rax]\nmov [rbp+var_48], rax\nmov [rbp+var_68], 0\njmp loc_1386\nloc_1225:\ncall ___ctype_b_loc\nmov rdx, [rax]\nmov rax, [rbp+var_48]\nmovzx eax, byte ptr [rax]\nmovsx rax, al\nadd rax, rax\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 2000h\ntest eax, eax\njnz short loc_1268\nmov eax, [rbp+var_68]\nlea edx, [rax+1]\nmov [rbp+var_68], edx\nmov rdx, [rbp+var_48]\nmovzx edx, byte ptr [rdx]\ncdqe\nmov [rbp+rax+s2], dl\njmp loc_1381\nloc_1268:\ncmp [rbp+var_68], 0\njle loc_1381\nmov eax, [rbp+var_68]\ncdqe\nmov [rbp+rax+s2], 0\nmov [rbp+var_64], 0\nmov [rbp+var_60], 0\njmp loc_1312\nloc_128F:\nmov eax, [rbp+var_60]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nlea rdx, words_1\nadd rdx, rax\nlea rax, [rbp+s2]\nmov rsi, rax; s2\nmov rdi, rdx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_130E\nmov eax, [rbp+var_60]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nmov rdx, rax\nlea rax, unk_4074\nmov eax, [rdx+rax]\nlea ecx, [rax+1]\nmov eax, [rbp+var_60]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nmov rdx, rax\nlea rax, unk_4074\nmov [rdx+rax], ecx\nmov [rbp+var_64], 1\njmp short loc_131E\nloc_130E:\nadd [rbp+var_60], 1\nloc_1312:\nmov eax, [rbp+var_60]\ncmp eax, [rbp+var_70]\njl loc_128F\nloc_131E:\ncmp [rbp+var_64], 0\njnz short loc_137A\nmov eax, [rbp+var_70]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nlea rdx, words_1\nadd rdx, rax\nlea rax, [rbp+s2]\nmov rsi, rax; src\nmov rdi, rdx; dest\ncall _strcpy\nmov eax, [rbp+var_70]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nmov rdx, rax\nlea rax, unk_4074\nmov dword ptr [rdx+rax], 1\nadd [rbp+var_70], 1\nloc_137A:\nmov [rbp+var_68], 0\nloc_1381:\nadd [rbp+var_48], 1\nloc_1386:\nmov rax, [rbp+var_48]\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_1225\ncmp [rbp+var_68], 0\njle loc_14A7\nmov eax, [rbp+var_68]\ncdqe\nmov [rbp+rax+s2], 0\nmov [rbp+var_5C], 0\nmov [rbp+var_58], 0\njmp loc_143F\nloc_13BC:\nmov eax, [rbp+var_58]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nlea rdx, words_1\nadd rdx, rax\nlea rax, [rbp+s2]\nmov rsi, rax; s2\nmov rdi, rdx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_143B\nmov eax, [rbp+var_58]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nmov rdx, rax\nlea rax, unk_4074\nmov eax, [rdx+rax]\nlea ecx, [rax+1]\nmov eax, [rbp+var_58]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nmov rdx, rax\nlea rax, unk_4074\nmov [rdx+rax], ecx\nmov [rbp+var_5C], 1\njmp short loc_144B\nloc_143B:\nadd [rbp+var_58], 1\nloc_143F:\nmov eax, [rbp+var_58]\ncmp eax, [rbp+var_70]\njl loc_13BC\nloc_144B:\ncmp [rbp+var_5C], 0\njnz short loc_14A7\nmov eax, [rbp+var_70]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nlea rdx, words_1\nadd rdx, rax\nlea rax, [rbp+s2]\nmov rsi, rax; src\nmov rdi, rdx; dest\ncall _strcpy\nmov eax, [rbp+var_70]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nmov rdx, rax\nlea rax, unk_4074\nmov dword ptr [rdx+rax], 1\nadd [rbp+var_70], 1\nloc_14A7:\nadd [rbp+var_6C], 1\nloc_14AB:\nmov eax, [rbp+var_6C]\ncmp eax, [rbp+var_74]\njl loc_11FE\nmov [rbp+var_54], 0\nmov [rbp+var_50], 0\nmov [rbp+var_4C], 0\njmp short loc_1522\nloc_14CE:\nmov eax, [rbp+var_4C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nmov rdx, rax\nlea rax, unk_4074\nmov eax, [rdx+rax]\ncmp [rbp+var_54], eax\njge short loc_151E\nmov eax, [rbp+var_4C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nmov rdx, rax\nlea rax, unk_4074\nmov eax, [rdx+rax]\nmov [rbp+var_54], eax\nmov eax, [rbp+var_4C]\nmov [rbp+var_50], eax\nloc_151E:\nadd [rbp+var_4C], 1\nloc_1522:\nmov eax, [rbp+var_4C]\ncmp eax, [rbp+var_70]\njl short loc_14CE\nmov eax, [rbp+var_50]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nlea rdx, words_1\nadd rax, rdx\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_155C\ncall ___stack_chk_fail\nlocret_155C:\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(int a1, __int64 a2)\n{\n int v2; // eax\n int v4; // [rsp+10h] [rbp-70h]\n int i; // [rsp+14h] [rbp-6Ch]\n int v6; // [rsp+18h] [rbp-68h]\n int v7; // [rsp+1Ch] [rbp-64h]\n int j; // [rsp+20h] [rbp-60h]\n int v9; // [rsp+24h] [rbp-5Ch]\n int k; // [rsp+28h] [rbp-58h]\n int v11; // [rsp+2Ch] [rbp-54h]\n int v12; // [rsp+30h] [rbp-50h]\n int m; // [rsp+34h] [rbp-4Ch]\n char *v14; // [rsp+38h] [rbp-48h]\n char s2[56]; // [rsp+40h] [rbp-40h] BYREF\n unsigned __int64 v16; // [rsp+78h] [rbp-8h]\n\n v16 = __readfsqword(0x28u);\n v4 = 0;\n for ( i = 0; i < a1; ++i )\n {\n v14 = *(char **)(8LL * i + a2);\n v6 = 0;\n while ( *v14 )\n {\n if ( ((*__ctype_b_loc())[*v14] & 0x2000) != 0 )\n {\n if ( v6 > 0 )\n {\n s2[v6] = 0;\n v7 = 0;\n for ( j = 0; j < v4; ++j )\n {\n if ( !strcmp((const char *)&words_1 + 56 * j, s2) )\n {\n ++dword_4074[14 * j];\n v7 = 1;\n break;\n }\n }\n if ( !v7 )\n {\n strcpy((char *)&words_1 + 56 * v4, s2);\n dword_4074[14 * v4++] = 1;\n }\n v6 = 0;\n }\n }\n else\n {\n v2 = v6++;\n s2[v2] = *v14;\n }\n ++v14;\n }\n if ( v6 > 0 )\n {\n s2[v6] = 0;\n v9 = 0;\n for ( k = 0; k < v4; ++k )\n {\n if ( !strcmp((const char *)&words_1 + 56 * k, s2) )\n {\n ++dword_4074[14 * k];\n v9 = 1;\n break;\n }\n }\n if ( !v9 )\n {\n strcpy((char *)&words_1 + 56 * v4, s2);\n dword_4074[14 * v4++] = 1;\n }\n }\n }\n v11 = 0;\n v12 = 0;\n for ( m = 0; m < v4; ++m )\n {\n if ( v11 < dword_4074[14 * m] )\n {\n v11 = dword_4074[14 * m];\n v12 = m;\n }\n }\n return (char *)&words_1 + 56 * v12;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nadd rsp, 0FFFFFFFFFFFFFF80h\nmov [rbp+var_74], edi\nmov [rbp+var_80], rsi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_70], 0\nmov [rbp+var_6C], 0\njmp loc_14AB\nloc_11FE:\nmov eax, [rbp+var_6C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_80]\nadd rax, rdx\nmov rax, [rax]\nmov [rbp+var_48], rax\nmov [rbp+var_68], 0\njmp loc_1386\nloc_1225:\ncall ___ctype_b_loc\nmov rdx, [rax]\nmov rax, [rbp+var_48]\nmovzx eax, byte ptr [rax]\nmovsx rax, al\nadd rax, rax\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 2000h\ntest eax, eax\njnz short loc_1268\nmov eax, [rbp+var_68]\nlea edx, [rax+1]\nmov [rbp+var_68], edx\nmov rdx, [rbp+var_48]\nmovzx edx, byte ptr [rdx]\ncdqe\nmov [rbp+rax+s2], dl\njmp loc_1381\nloc_1268:\ncmp [rbp+var_68], 0\njle loc_1381\nmov eax, [rbp+var_68]\ncdqe\nmov [rbp+rax+s2], 0\nmov [rbp+var_64], 0\nmov [rbp+var_60], 0\njmp loc_1312\nloc_128F:\nmov eax, [rbp+var_60]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nlea rdx, unk_4040\nadd rdx, rax\nlea rax, [rbp+s2]\nmov rsi, rax; s2\nmov rdi, rdx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_130E\nmov eax, [rbp+var_60]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nmov rdx, rax\nlea rax, unk_4074\nmov eax, [rdx+rax]\nlea ecx, [rax+1]\nmov eax, [rbp+var_60]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nmov rdx, rax\nlea rax, unk_4074\nmov [rdx+rax], ecx\nmov [rbp+var_64], 1\njmp short loc_131E\nloc_130E:\nadd [rbp+var_60], 1\nloc_1312:\nmov eax, [rbp+var_60]\ncmp eax, [rbp+var_70]\njl loc_128F\nloc_131E:\ncmp [rbp+var_64], 0\njnz short loc_137A\nmov eax, [rbp+var_70]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nlea rdx, unk_4040\nadd rdx, rax\nlea rax, [rbp+s2]\nmov rsi, rax; src\nmov rdi, rdx; dest\ncall _strcpy\nmov eax, [rbp+var_70]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nmov rdx, rax\nlea rax, unk_4074\nmov dword ptr [rdx+rax], 1\nadd [rbp+var_70], 1\nloc_137A:\nmov [rbp+var_68], 0\nloc_1381:\nadd [rbp+var_48], 1\nloc_1386:\nmov rax, [rbp+var_48]\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_1225\ncmp [rbp+var_68], 0\njle loc_14A7\nmov eax, [rbp+var_68]\ncdqe\nmov [rbp+rax+s2], 0\nmov [rbp+var_5C], 0\nmov [rbp+var_58], 0\njmp loc_143F\nloc_13BC:\nmov eax, [rbp+var_58]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nlea rdx, unk_4040\nadd rdx, rax\nlea rax, [rbp+s2]\nmov rsi, rax; s2\nmov rdi, rdx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_143B\nmov eax, [rbp+var_58]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nmov rdx, rax\nlea rax, unk_4074\nmov eax, [rdx+rax]\nlea ecx, [rax+1]\nmov eax, [rbp+var_58]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nmov rdx, rax\nlea rax, unk_4074\nmov [rdx+rax], ecx\nmov [rbp+var_5C], 1\njmp short loc_144B\nloc_143B:\nadd [rbp+var_58], 1\nloc_143F:\nmov eax, [rbp+var_58]\ncmp eax, [rbp+var_70]\njl loc_13BC\nloc_144B:\ncmp [rbp+var_5C], 0\njnz short loc_14A7\nmov eax, [rbp+var_70]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nlea rdx, unk_4040\nadd rdx, rax\nlea rax, [rbp+s2]\nmov rsi, rax; src\nmov rdi, rdx; dest\ncall _strcpy\nmov eax, [rbp+var_70]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nmov rdx, rax\nlea rax, unk_4074\nmov dword ptr [rdx+rax], 1\nadd [rbp+var_70], 1\nloc_14A7:\nadd [rbp+var_6C], 1\nloc_14AB:\nmov eax, [rbp+var_6C]\ncmp eax, [rbp+var_74]\njl loc_11FE\nmov [rbp+var_54], 0\nmov [rbp+var_50], 0\nmov [rbp+var_4C], 0\njmp short loc_1522\nloc_14CE:\nmov eax, [rbp+var_4C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nmov rdx, rax\nlea rax, unk_4074\nmov eax, [rdx+rax]\ncmp [rbp+var_54], eax\njge short loc_151E\nmov eax, [rbp+var_4C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nmov rdx, rax\nlea rax, unk_4074\nmov eax, [rdx+rax]\nmov [rbp+var_54], eax\nmov eax, [rbp+var_4C]\nmov [rbp+var_50], eax\nloc_151E:\nadd [rbp+var_4C], 1\nloc_1522:\nmov eax, [rbp+var_4C]\ncmp eax, [rbp+var_70]\njl short loc_14CE\nmov eax, [rbp+var_50]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nlea rdx, unk_4040\nadd rax, rdx\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_155C\ncall ___stack_chk_fail\nlocret_155C:\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11C9(int a1, __int64 a2)\n{\n int v2; // eax\n int v4; // [rsp+10h] [rbp-70h]\n int i; // [rsp+14h] [rbp-6Ch]\n int v6; // [rsp+18h] [rbp-68h]\n int v7; // [rsp+1Ch] [rbp-64h]\n int j; // [rsp+20h] [rbp-60h]\n int v9; // [rsp+24h] [rbp-5Ch]\n int k; // [rsp+28h] [rbp-58h]\n int v11; // [rsp+2Ch] [rbp-54h]\n int v12; // [rsp+30h] [rbp-50h]\n int m; // [rsp+34h] [rbp-4Ch]\n char *v14; // [rsp+38h] [rbp-48h]\n char s2[56]; // [rsp+40h] [rbp-40h] BYREF\n unsigned __int64 v16; // [rsp+78h] [rbp-8h]\n\n v16 = __readfsqword(0x28u);\n v4 = 0;\n for ( i = 0; i < a1; ++i )\n {\n v14 = *(char **)(8LL * i + a2);\n v6 = 0;\n while ( *v14 )\n {\n if ( ((*__ctype_b_loc())[*v14] & 0x2000) != 0 )\n {\n if ( v6 > 0 )\n {\n s2[v6] = 0;\n v7 = 0;\n for ( j = 0; j < v4; ++j )\n {\n if ( !strcmp((const char *)&unk_4040 + 56 * j, s2) )\n {\n ++dword_4074[14 * j];\n v7 = 1;\n break;\n }\n }\n if ( !v7 )\n {\n strcpy((char *)&unk_4040 + 56 * v4, s2);\n dword_4074[14 * v4++] = 1;\n }\n v6 = 0;\n }\n }\n else\n {\n v2 = v6++;\n s2[v2] = *v14;\n }\n ++v14;\n }\n if ( v6 > 0 )\n {\n s2[v6] = 0;\n v9 = 0;\n for ( k = 0; k < v4; ++k )\n {\n if ( !strcmp((const char *)&unk_4040 + 56 * k, s2) )\n {\n ++dword_4074[14 * k];\n v9 = 1;\n break;\n }\n }\n if ( !v9 )\n {\n strcpy((char *)&unk_4040 + 56 * v4, s2);\n dword_4074[14 * v4++] = 1;\n }\n }\n }\n v11 = 0;\n v12 = 0;\n for ( m = 0; m < v4; ++m )\n {\n if ( v11 < dword_4074[14 * m] )\n {\n v11 = dword_4074[14 * m];\n v12 = m;\n }\n }\n return (char *)&unk_4040 + 56 * v12;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11C9(int a1, long long a2) {\n int v2;\n int v4;\n int i;\n int v6;\n int v7;\n int j;\n int v9;\n int k;\n int v11;\n int v12;\n int m;\n char *v14;\n char s2[56];\n unsigned long long v16;\n v16 = __readfsqword(40u);\n v4 = 0;\n for (i = 0; i < a1; ++i) {\n v14 = *(char **)(8LL * i + a2);\n v6 = 0;\n while (*v14) {\n if (((*__ctype_b_loc())[*v14] & 8192) != 0) {\n if (v6 > 0) {\n s2[v6] = 0;\n v7 = 0;\n for (j = 0; j < v4; ++j) {\n if (!strcmp((const char *)&unk_4040 + 56 * j, s2)) {\n ++dword_4074[14 * j];\n v7 = 1;\n break;\n }\n }\n if (!v7) {\n strcpy((char *)&unk_4040 + 56 * v4, s2);\n dword_4074[14 * v4++] = 1;\n }\n v6 = 0;\n }\n } else {\n v2 = v6++;\n s2[v2] = *v14;\n }\n ++v14;\n }\n if (v6 > 0) {\n s2[v6] = 0;\n v9 = 0;\n for (k = 0; k < v4; ++k) {\n if (!strcmp((const char *)&unk_4040 + 56 * k, s2)) {\n ++dword_4074[14 * k];\n v9 = 1;\n break;\n }\n }\n if (!v9) {\n strcpy((char *)&unk_4040 + 56 * v4, s2);\n dword_4074[14 * v4++] = 1;\n }\n }\n }\n v11 = 0;\n v12 = 0;\n for (m = 0; m < v4; ++m) {\n if (v11 < dword_4074[14 * m]) {\n v11 = dword_4074[14 * m];\n v12 = m;\n }\n }\n return (char *)&unk_4040 + 56 * v12;\n}", + "ida_pseudo_norm": "char *func0(int a1, long long a2) {\n int v2;\n int v4;\n int i;\n int v6;\n int v7;\n int j;\n int v9;\n int k;\n int v11;\n int v12;\n int m;\n char *v14;\n char s2[56];\n unsigned long long v16;\n v16 = __readfsqword(40u);\n v4 = 0;\n for (i = 0; i < a1; ++i) {\n v14 = *(char **)(8LL * i + a2);\n v6 = 0;\n while (*v14) {\n if (((*__ctype_b_loc())[*v14] & 8192) != 0) {\n if (v6 > 0) {\n s2[v6] = 0;\n v7 = 0;\n for (j = 0; j < v4; ++j) {\n if (!strcmp((const char *)&words_1 + 56 * j, s2)) {\n ++dword_4074[14 * j];\n v7 = 1;\n break;\n }\n }\n if (!v7) {\n strcpy((char *)&words_1 + 56 * v4, s2);\n dword_4074[14 * v4++] = 1;\n }\n v6 = 0;\n }\n } else {\n v2 = v6++;\n s2[v2] = *v14;\n }\n ++v14;\n }\n if (v6 > 0) {\n s2[v6] = 0;\n v9 = 0;\n for (k = 0; k < v4; ++k) {\n if (!strcmp((const char *)&words_1 + 56 * k, s2)) {\n ++dword_4074[14 * k];\n v9 = 1;\n break;\n }\n }\n if (!v9) {\n strcpy((char *)&words_1 + 56 * v4, s2);\n dword_4074[14 * v4++] = 1;\n }\n }\n }\n v11 = 0;\n v12 = 0;\n for (m = 0; m < v4; ++m) {\n if (v11 < dword_4074[14 * m]) {\n v11 = dword_4074[14 * m];\n v12 = m;\n }\n }\n return (char *)&words_1 + 56 * v12;\n}" + }, + { + "index": 326, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char word[50];\n\n int count;\n\n} WordCount;\n\n\n\n", + "func": "const char* func0(int n, const char* test_list[]) {\n static WordCount words[100];\n int unique = 0;\n for (int i = 0; i < n; i++) {\n const char* str = test_list[i];\n char word[50];\n int pos = 0;\n while (*str) {\n if (!isspace(*str)) {\n word[pos++] = *str;\n }\n else {\n if (pos > 0) {\n word[pos] = '\\0';\n int found = 0;\n for (int j = 0; j < unique; j++) {\n if (strcmp(words[j].word, word) == 0) {\n words[j].count++;\n found = 1;\n break;\n }\n }\n if (!found) {\n strcpy(words[unique].word, word);\n words[unique].count = 1;\n unique++;\n }\n pos = 0;\n }\n }\n str++;\n }\n if (pos > 0) {\n word[pos] = '\\0';\n int found = 0;\n for (int j = 0; j < unique; j++) {\n if (strcmp(words[j].word, word) == 0) {\n words[j].count++;\n found = 1;\n break;\n }\n }\n if (!found) {\n strcpy(words[unique].word, word);\n words[unique].count = 1;\n unique++;\n }\n }\n }\n int max = 0;\n int index = 0;\n for (int i = 0; i < unique; i++) {\n if (words[i].count > max) {\n max = words[i].count;\n index = i;\n }\n }\n return words[index].word;\n}", + "test": "int main(){\n\n const char* test1[] = {\"UTS is best for RTF\", \"RTF love UTS\", \"UTS is best\"};\n\n assert(strcmp(func0(3, test1), \"UTS\") == 0);\n\n \n\n const char* test2[] = {\"Its been a great year\", \"this year is so worse\", \"this year is okay\"};\n\n assert(strcmp(func0(3, test2), \"year\") == 0);\n\n \n\n const char* test3[] = {\"Families can be reunited\", \"people can be reunited\", \"Tasks can be achieved \"};\n\n assert(strcmp(func0(3, test3), \"can\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x58,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\ntest %edi,%edi\njle 13f2 \nmov %rsi,(%rsp)\nlea -0x1(%rdi),%eax\nlea 0x8(%rsi,%rax,8),%rax\nmov %rax,0x8(%rsp)\nmov $0x0,%r13d\njmpq 12fb \ntest %eax,%eax\njg 123e \nadd $0x1,%r12\nmovzbl (%r12),%ebx\ntest %bl,%bl\nje 12e3 \nmovsbq %bl,%rdx\nmov (%r15),%rcx\ntestb $0x20,0x1(%rcx,%rdx,2)\njne 120f \nmovslq %eax,%rdx\nmov %bl,0x10(%rsp,%rdx,1)\nlea 0x1(%rax),%eax\njmp 1213 \ncltq\nmovb $0x0,0x10(%rsp,%rax,1)\ntest %r13d,%r13d\njle 1276 \nlea 0x2def(%rip),%rbp\nmov $0x0,%ebx\nlea 0x10(%rsp),%r14\nmov %r14,%rsi\nmov %rbp,%rdi\ncallq 10b0 \ntest %eax,%eax\nje 12bb \nadd $0x1,%ebx\nadd $0x38,%rbp\ncmp %r13d,%ebx\njne 125b \nlea 0x10(%rsp),%rsi\nmovslq %r13d,%rbx\nlea 0x0(,%rbx,8),%rbp\nmov %rbp,%rax\nsub %rbx,%rax\nlea 0x2dad(%rip),%r14\nlea (%r14,%rax,8),%rdi\nmov $0x32,%edx\ncallq 10c0 <__strcpy_chk@plt>\nsub %rbx,%rbp\nmovl $0x1,0x34(%r14,%rbp,8)\nadd $0x1,%r13d\nmov $0x0,%eax\njmpq 1213 \nmovslq %ebx,%rbx\nlea 0x0(,%rbx,8),%rdx\nmov %rdx,%rcx\nsub %rbx,%rcx\nlea 0x2d6d(%rip),%rdi\nmov 0x34(%rdi,%rcx,8),%edx\nadd $0x1,%edx\nmov %edx,0x34(%rdi,%rcx,8)\njmpq 1213 \ntest %eax,%eax\njg 131d \naddq $0x8,(%rsp)\nmov (%rsp),%rax\ncmp 0x8(%rsp),%rax\nje 13bd \nmov (%rsp),%rax\nmov (%rax),%r12\nmovzbl (%r12),%ebx\ntest %bl,%bl\nje 12e7 \ncallq 10d0 <__ctype_b_loc@plt>\nmov %rax,%r15\nmov $0x0,%eax\njmpq 1224 \ncltq\nmovb $0x0,0x10(%rsp,%rax,1)\ntest %r13d,%r13d\njle 1355 \nlea 0x2d10(%rip),%rbp\nmov $0x0,%ebx\nlea 0x10(%rsp),%r12\nmov %r12,%rsi\nmov %rbp,%rdi\ncallq 10b0 \ntest %eax,%eax\nje 1395 \nadd $0x1,%ebx\nadd $0x38,%rbp\ncmp %ebx,%r13d\njne 133a \nlea 0x10(%rsp),%rsi\nmovslq %r13d,%rbp\nlea 0x0(,%rbp,8),%rbx\nmov %rbx,%rax\nsub %rbp,%rax\nlea 0x2cce(%rip),%r15\nlea (%r15,%rax,8),%rdi\nmov $0x32,%edx\ncallq 10c0 <__strcpy_chk@plt>\nsub %rbp,%rbx\nmovl $0x1,0x34(%r15,%rbx,8)\nadd $0x1,%r13d\njmpq 12e7 \nmovslq %ebx,%rbx\nlea 0x0(,%rbx,8),%rax\nmov %rax,%rdx\nsub %rbx,%rdx\nlea 0x2c93(%rip),%rcx\nmov 0x34(%rcx,%rdx,8),%eax\nadd $0x1,%eax\nmov %eax,0x34(%rcx,%rdx,8)\njmpq 12e7 \ntest %r13d,%r13d\njle 142f \nlea 0x2cab(%rip),%rdx\nmov $0x0,%eax\nmov $0x0,%edi\nmov $0x0,%esi\njmp 13e6 \nadd $0x1,%eax\nadd $0x38,%rdx\ncmp %eax,%r13d\nje 13f7 \nmov (%rdx),%ecx\ncmp %esi,%ecx\njle 13da \nmov %eax,%edi\nmov %ecx,%esi\njmp 13da \nmov $0x0,%edi\nmovslq %edi,%rdi\nlea 0x0(,%rdi,8),%rax\nsub %rdi,%rax\nlea 0x2c34(%rip),%rdx\nlea (%rdx,%rax,8),%rax\nmov 0x48(%rsp),%rsi\nxor %fs:0x28,%rsi\njne 1436 \nadd $0x58,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmov $0x0,%edi\njmp 13f7 \ncallq 1090 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+88h+var_40], rax\nxor eax, eax\ntest edi, edi\njle loc_13FA\nmov [rsp+88h+var_88], rsi\nmovsxd rdi, edi\nlea rax, [rsi+rdi*8]\nmov [rsp+88h+var_80], rax\nmov r13d, 0\njmp loc_12FE\nloc_120E:\ntest eax, eax\njg short loc_123D\nloc_1212:\nadd r12, 1\nmovzx ebx, byte ptr [r12]\ntest bl, bl\njz loc_12E3\nloc_1223:\nmovsx rdx, bl\nmov rcx, [r15]\ntest byte ptr [rcx+rdx*2+1], 20h\njnz short loc_120E\nmovsxd rdx, eax\nmov [rsp+rdx+88h+s2], bl\nlea eax, [rax+1]\njmp short loc_1212\nloc_123D:\ncdqe\nmov [rsp+rax+88h+s2], 0\ntest r13d, r13d\njle short loc_1270\nlea rbp, words_1\nmov ebx, 0\nloc_1255:\nmov rsi, r14; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njz short loc_12BB\nadd ebx, 1\nadd rbp, 38h ; '8'\ncmp ebx, r13d\njnz short loc_1255\nloc_1270:\nlea rsi, [rsp+88h+s2]\nmovsxd rbx, r13d\nlea rbp, ds:0[rbx*8]\nmov rax, rbp\nsub rax, rbx\nlea rcx, words_1\nlea rdi, [rcx+rax*8]\nmov edx, 32h ; '2'\ncall ___strcpy_chk\nsub rbp, rbx\nlea rcx, words_1\nmov dword ptr [rcx+rbp*8+34h], 1\nadd r13d, 1\nmov eax, 0\njmp loc_1212\nloc_12BB:\nmovsxd rbx, ebx\nlea rdx, ds:0[rbx*8]\nmov rcx, rdx\nsub rcx, rbx\nlea rdi, words_1\nmov edx, [rdi+rcx*8+34h]\nadd edx, 1\nmov [rdi+rcx*8+34h], edx\njmp loc_1212\nloc_12E3:\ntest eax, eax\njg short loc_1325\nloc_12E7:\nadd [rsp+88h+var_88], 8\nmov rax, [rsp+88h+var_88]\nmov rsi, [rsp+88h+var_80]\ncmp rax, rsi\njz loc_13C5\nloc_12FE:\nmov rax, [rsp+88h+var_88]\nmov r12, [rax]\nmovzx ebx, byte ptr [r12]\ntest bl, bl\njz short loc_12E7\ncall ___ctype_b_loc\nmov r15, rax\nmov eax, 0\nlea r14, [rsp+88h+s2]\njmp loc_1223\nloc_1325:\ncdqe\nmov [rsp+rax+88h+s2], 0\ntest r13d, r13d\njle short loc_135D\nlea rbp, words_1\nmov ebx, 0\nlea r12, [rsp+88h+s2]\nloc_1342:\nmov rsi, r12; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njz short loc_139D\nadd ebx, 1\nadd rbp, 38h ; '8'\ncmp r13d, ebx\njnz short loc_1342\nloc_135D:\nlea rsi, [rsp+88h+s2]\nmovsxd rbp, r13d\nlea rbx, ds:0[rbp*8]\nmov rax, rbx\nsub rax, rbp\nlea r15, words_1\nlea rdi, [r15+rax*8]\nmov edx, 32h ; '2'\ncall ___strcpy_chk\nsub rbx, rbp\nmov dword ptr [r15+rbx*8+34h], 1\nadd r13d, 1\njmp loc_12E7\nloc_139D:\nmovsxd rbx, ebx\nlea rax, ds:0[rbx*8]\nmov rdx, rax\nsub rdx, rbx\nlea rsi, words_1\nmov eax, [rsi+rdx*8+34h]\nadd eax, 1\nmov [rsi+rdx*8+34h], eax\njmp loc_12E7\nloc_13C5:\ntest r13d, r13d\njle short loc_1437\nlea rdx, unk_4074\nmov eax, 0\nmov edi, 0\nmov esi, 0\njmp short loc_13EE\nloc_13E2:\nadd eax, 1\nadd rdx, 38h ; '8'\ncmp r13d, eax\njz short loc_13FF\nloc_13EE:\nmov ecx, [rdx]\ncmp ecx, esi\njle short loc_13E2\nmov edi, eax\nmov esi, ecx\njmp short loc_13E2\nloc_13FA:\nmov edi, 0\nloc_13FF:\nmovsxd rdi, edi\nlea rax, ds:0[rdi*8]\nsub rax, rdi\nlea rdx, words_1\nlea rax, [rdx+rax*8]\nmov rdx, [rsp+88h+var_40]\nsub rdx, fs:28h\njnz short loc_143E\nadd rsp, 58h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1437:\nmov edi, 0\njmp short loc_13FF\nloc_143E:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(int a1, char **a2)\n{\n int v2; // r13d\n char *v3; // r12\n char v4; // bl\n int v5; // eax\n const char *v6; // rbp\n int v7; // ebx\n const unsigned __int16 **v8; // r15\n const char *v9; // rbp\n int v10; // ebx\n int *v11; // rdx\n int v12; // eax\n int v13; // edi\n int v14; // esi\n char **v16; // [rsp+0h] [rbp-88h]\n char s2[56]; // [rsp+10h] [rbp-78h] BYREF\n unsigned __int64 v18; // [rsp+48h] [rbp-40h]\n\n v18 = __readfsqword(0x28u);\n if ( a1 <= 0 )\n {\n v13 = 0;\n }\n else\n {\n v16 = a2;\n v2 = 0;\n do\n {\n v3 = *v16;\n v4 = **v16;\n if ( v4 )\n {\n v8 = __ctype_b_loc();\n v5 = 0;\n do\n {\n if ( ((*v8)[v4] & 0x2000) != 0 )\n {\n if ( v5 > 0 )\n {\n s2[v5] = 0;\n if ( v2 <= 0 )\n {\nLABEL_11:\n __strcpy_chk(&words_1[56 * v2], s2, 50LL);\n *(_DWORD *)&words_1[56 * v2++ + 52] = 1;\n v5 = 0;\n }\n else\n {\n v6 = words_1;\n v7 = 0;\n while ( 1 )\n {\n v5 = strcmp(v6, s2);\n if ( !v5 )\n break;\n ++v7;\n v6 += 56;\n if ( v7 == v2 )\n goto LABEL_11;\n }\n ++*(_DWORD *)&words_1[56 * v7 + 52];\n }\n }\n }\n else\n {\n s2[v5++] = v4;\n }\n v4 = *++v3;\n }\n while ( *v3 );\n if ( v5 > 0 )\n {\n s2[v5] = 0;\n if ( v2 <= 0 )\n {\nLABEL_21:\n __strcpy_chk(&words_1[56 * v2], s2, 50LL);\n *(_DWORD *)&words_1[56 * v2++ + 52] = 1;\n }\n else\n {\n v9 = words_1;\n v10 = 0;\n while ( strcmp(v9, s2) )\n {\n ++v10;\n v9 += 56;\n if ( v2 == v10 )\n goto LABEL_21;\n }\n ++*(_DWORD *)&words_1[56 * v10 + 52];\n }\n }\n }\n ++v16;\n }\n while ( v16 != &a2[a1] );\n if ( v2 <= 0 )\n {\n v13 = 0;\n }\n else\n {\n v11 = (int *)&unk_4074;\n v12 = 0;\n v13 = 0;\n v14 = 0;\n do\n {\n if ( *v11 > v14 )\n {\n v13 = v12;\n v14 = *v11;\n }\n ++v12;\n v11 += 14;\n }\n while ( v2 != v12 );\n }\n }\n return &words_1[56 * v13];\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+88h+var_40], rax\nxor eax, eax\ntest edi, edi\njle loc_13FA\nmov [rsp+88h+var_88], rsi\nmovsxd rdi, edi\nlea rax, [rsi+rdi*8]\nmov [rsp+88h+var_80], rax\nmov r13d, 0\njmp loc_12FE\nloc_120E:\ntest eax, eax\njg short loc_123D\nloc_1212:\nadd r12, 1\nmovzx ebx, byte ptr [r12]\ntest bl, bl\njz loc_12E3\nloc_1223:\nmovsx rdx, bl\nmov rcx, [r15]\ntest byte ptr [rcx+rdx*2+1], 20h\njnz short loc_120E\nmovsxd rdx, eax\nmov [rsp+rdx+88h+s2], bl\nlea eax, [rax+1]\njmp short loc_1212\nloc_123D:\ncdqe\nmov [rsp+rax+88h+s2], 0\ntest r13d, r13d\njle short loc_1270\nlea rbp, s1\nmov ebx, 0\nloc_1255:\nmov rsi, r14; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njz short loc_12BB\nadd ebx, 1\nadd rbp, 38h ; '8'\ncmp ebx, r13d\njnz short loc_1255\nloc_1270:\nlea rsi, [rsp+88h+s2]\nmovsxd rbx, r13d\nlea rbp, ds:0[rbx*8]\nmov rax, rbp\nsub rax, rbx\nlea rcx, s1\nlea rdi, [rcx+rax*8]\nmov edx, 32h ; '2'\ncall ___strcpy_chk\nsub rbp, rbx\nlea rcx, s1\nmov dword ptr [rcx+rbp*8+34h], 1\nadd r13d, 1\nmov eax, 0\njmp loc_1212\nloc_12BB:\nmovsxd rbx, ebx\nlea rdx, ds:0[rbx*8]\nmov rcx, rdx\nsub rcx, rbx\nlea rdi, s1\nmov edx, [rdi+rcx*8+34h]\nadd edx, 1\nmov [rdi+rcx*8+34h], edx\njmp loc_1212\nloc_12E3:\ntest eax, eax\njg short loc_1325\nloc_12E7:\nadd [rsp+88h+var_88], 8\nmov rax, [rsp+88h+var_88]\nmov rsi, [rsp+88h+var_80]\ncmp rax, rsi\njz loc_13C5\nloc_12FE:\nmov rax, [rsp+88h+var_88]\nmov r12, [rax]\nmovzx ebx, byte ptr [r12]\ntest bl, bl\njz short loc_12E7\ncall ___ctype_b_loc\nmov r15, rax\nmov eax, 0\nlea r14, [rsp+88h+s2]\njmp loc_1223\nloc_1325:\ncdqe\nmov [rsp+rax+88h+s2], 0\ntest r13d, r13d\njle short loc_135D\nlea rbp, s1\nmov ebx, 0\nlea r12, [rsp+88h+s2]\nloc_1342:\nmov rsi, r12; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njz short loc_139D\nadd ebx, 1\nadd rbp, 38h ; '8'\ncmp r13d, ebx\njnz short loc_1342\nloc_135D:\nlea rsi, [rsp+88h+s2]\nmovsxd rbp, r13d\nlea rbx, ds:0[rbp*8]\nmov rax, rbx\nsub rax, rbp\nlea r15, s1\nlea rdi, [r15+rax*8]\nmov edx, 32h ; '2'\ncall ___strcpy_chk\nsub rbx, rbp\nmov dword ptr [r15+rbx*8+34h], 1\nadd r13d, 1\njmp loc_12E7\nloc_139D:\nmovsxd rbx, ebx\nlea rax, ds:0[rbx*8]\nmov rdx, rax\nsub rdx, rbx\nlea rsi, s1\nmov eax, [rsi+rdx*8+34h]\nadd eax, 1\nmov [rsi+rdx*8+34h], eax\njmp loc_12E7\nloc_13C5:\ntest r13d, r13d\njle short loc_1437\nlea rdx, unk_4074\nmov eax, 0\nmov edi, 0\nmov esi, 0\njmp short loc_13EE\nloc_13E2:\nadd eax, 1\nadd rdx, 38h ; '8'\ncmp r13d, eax\njz short loc_13FF\nloc_13EE:\nmov ecx, [rdx]\ncmp ecx, esi\njle short loc_13E2\nmov edi, eax\nmov esi, ecx\njmp short loc_13E2\nloc_13FA:\nmov edi, 0\nloc_13FF:\nmovsxd rdi, edi\nlea rax, ds:0[rdi*8]\nsub rax, rdi\nlea rdx, s1\nlea rax, [rdx+rax*8]\nmov rdx, [rsp+88h+var_40]\nsub rdx, fs:28h\njnz short loc_143E\nadd rsp, 58h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1437:\nmov edi, 0\njmp short loc_13FF\nloc_143E:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_11C9(int a1, char **a2)\n{\n int v2; // r13d\n char *v3; // r12\n char v4; // bl\n int v5; // eax\n const char *v6; // rbp\n int v7; // ebx\n const unsigned __int16 **v8; // r15\n const char *v9; // rbp\n int v10; // ebx\n int *v11; // rdx\n int v12; // eax\n int v13; // edi\n int v14; // esi\n char **v16; // [rsp+0h] [rbp-88h]\n char s2[56]; // [rsp+10h] [rbp-78h] BYREF\n unsigned __int64 v18; // [rsp+48h] [rbp-40h]\n\n v18 = __readfsqword(0x28u);\n if ( a1 <= 0 )\n {\n v13 = 0;\n }\n else\n {\n v16 = a2;\n v2 = 0;\n do\n {\n v3 = *v16;\n v4 = **v16;\n if ( v4 )\n {\n v8 = __ctype_b_loc();\n v5 = 0;\n do\n {\n if ( ((*v8)[v4] & 0x2000) != 0 )\n {\n if ( v5 > 0 )\n {\n s2[v5] = 0;\n if ( v2 <= 0 )\n {\nLABEL_11:\n __strcpy_chk(&s1[56 * v2], s2, 50LL);\n *(_DWORD *)&s1[56 * v2++ + 52] = 1;\n v5 = 0;\n }\n else\n {\n v6 = s1;\n v7 = 0;\n while ( 1 )\n {\n v5 = strcmp(v6, s2);\n if ( !v5 )\n break;\n ++v7;\n v6 += 56;\n if ( v7 == v2 )\n goto LABEL_11;\n }\n ++*(_DWORD *)&s1[56 * v7 + 52];\n }\n }\n }\n else\n {\n s2[v5++] = v4;\n }\n v4 = *++v3;\n }\n while ( *v3 );\n if ( v5 > 0 )\n {\n s2[v5] = 0;\n if ( v2 <= 0 )\n {\nLABEL_21:\n __strcpy_chk(&s1[56 * v2], s2, 50LL);\n *(_DWORD *)&s1[56 * v2++ + 52] = 1;\n }\n else\n {\n v9 = s1;\n v10 = 0;\n while ( strcmp(v9, s2) )\n {\n ++v10;\n v9 += 56;\n if ( v2 == v10 )\n goto LABEL_21;\n }\n ++*(_DWORD *)&s1[56 * v10 + 52];\n }\n }\n }\n ++v16;\n }\n while ( v16 != &a2[a1] );\n if ( v2 <= 0 )\n {\n v13 = 0;\n }\n else\n {\n v11 = (int *)&unk_4074;\n v12 = 0;\n v13 = 0;\n v14 = 0;\n do\n {\n if ( *v11 > v14 )\n {\n v13 = v12;\n v14 = *v11;\n }\n ++v12;\n v11 += 14;\n }\n while ( v2 != v12 );\n }\n }\n return &s1[56 * v13];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11C9(int a1, char **a2) {\n int v2;\n char *v3;\n char v4;\n int v5;\n const char *v6;\n int v7;\n const unsigned short **v8;\n const char *v9;\n int v10;\n int *v11;\n int v12;\n int v13;\n int v14;\n char **v16;\n char s2[56];\n unsigned long long v18;\n v18 = __readfsqword(40u);\n if (a1 <= 0) {\n v13 = 0;\n } else {\n v16 = a2;\n v2 = 0;\n do {\n v3 = *v16;\n v4 = **v16;\n if (v4) {\n v8 = __ctype_b_loc();\n v5 = 0;\n do {\n if (((*v8)[v4] & 8192) != 0) {\n if (v5 > 0) {\n s2[v5] = 0;\n if (v2 <= 0) {\n LABEL_11:\n __strcpy_chk(&s1[56 * v2], s2, 50LL);\n *(uint32_t *)&s1[56 * v2++ + 52] = 1;\n v5 = 0;\n } else {\n v6 = s1;\n v7 = 0;\n while (1) {\n v5 = strcmp(v6, s2);\n if (!v5) break;\n ++v7;\n v6 += 56;\n if (v7 == v2) goto LABEL_11;\n }\n ++*(uint32_t *)&s1[56 * v7 + 52];\n }\n }\n } else {\n s2[v5++] = v4;\n }\n v4 = *++v3;\n } while (*v3);\n if (v5 > 0) {\n s2[v5] = 0;\n if (v2 <= 0) {\n LABEL_21:\n __strcpy_chk(&s1[56 * v2], s2, 50LL);\n *(uint32_t *)&s1[56 * v2++ + 52] = 1;\n } else {\n v9 = s1;\n v10 = 0;\n while (strcmp(v9, s2)) {\n ++v10;\n v9 += 56;\n if (v2 == v10) goto LABEL_21;\n }\n ++*(uint32_t *)&s1[56 * v10 + 52];\n }\n }\n }\n ++v16;\n } while (v16 != &a2[a1]);\n if (v2 <= 0) {\n v13 = 0;\n } else {\n v11 = (int *)&unk_4074;\n v12 = 0;\n v13 = 0;\n v14 = 0;\n do {\n if (*v11 > v14) {\n v13 = v12;\n v14 = *v11;\n }\n ++v12;\n v11 += 14;\n } while (v2 != v12);\n }\n }\n return &s1[56 * v13];\n}", + "ida_pseudo_norm": "char *func0(int a1, char **a2) {\n int v2;\n char *v3;\n char v4;\n int v5;\n const char *v6;\n int v7;\n const unsigned short **v8;\n const char *v9;\n int v10;\n int *v11;\n int v12;\n int v13;\n int v14;\n char **v16;\n char s2[56];\n unsigned long long v18;\n v18 = __readfsqword(40u);\n if (a1 <= 0) {\n v13 = 0;\n } else {\n v16 = a2;\n v2 = 0;\n do {\n v3 = *v16;\n v4 = **v16;\n if (v4) {\n v8 = __ctype_b_loc();\n v5 = 0;\n do {\n if (((*v8)[v4] & 8192) != 0) {\n if (v5 > 0) {\n s2[v5] = 0;\n if (v2 <= 0) {\n LABEL_11:\n __strcpy_chk(&words_1[56 * v2], s2, 50LL);\n *(uint32_t *)&words_1[56 * v2++ + 52] = 1;\n v5 = 0;\n } else {\n v6 = words_1;\n v7 = 0;\n while (1) {\n v5 = strcmp(v6, s2);\n if (!v5) break;\n ++v7;\n v6 += 56;\n if (v7 == v2) goto LABEL_11;\n }\n ++*(uint32_t *)&words_1[56 * v7 + 52];\n }\n }\n } else {\n s2[v5++] = v4;\n }\n v4 = *++v3;\n } while (*v3);\n if (v5 > 0) {\n s2[v5] = 0;\n if (v2 <= 0) {\n LABEL_21:\n __strcpy_chk(&words_1[56 * v2], s2, 50LL);\n *(uint32_t *)&words_1[56 * v2++ + 52] = 1;\n } else {\n v9 = words_1;\n v10 = 0;\n while (strcmp(v9, s2)) {\n ++v10;\n v9 += 56;\n if (v2 == v10) goto LABEL_21;\n }\n ++*(uint32_t *)&words_1[56 * v10 + 52];\n }\n }\n }\n ++v16;\n } while (v16 != &a2[a1]);\n if (v2 <= 0) {\n v13 = 0;\n } else {\n v11 = (int *)&unk_4074;\n v12 = 0;\n v13 = 0;\n v14 = 0;\n do {\n if (*v11 > v14) {\n v13 = v12;\n v14 = *v11;\n }\n ++v12;\n v11 += 14;\n } while (v2 != v12);\n }\n }\n return &words_1[56 * v13];\n}" + }, + { + "index": 326, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char word[50];\n\n int count;\n\n} WordCount;\n\n\n\n", + "func": "const char* func0(int n, const char* test_list[]) {\n static WordCount words[100];\n int unique = 0;\n for (int i = 0; i < n; i++) {\n const char* str = test_list[i];\n char word[50];\n int pos = 0;\n while (*str) {\n if (!isspace(*str)) {\n word[pos++] = *str;\n }\n else {\n if (pos > 0) {\n word[pos] = '\\0';\n int found = 0;\n for (int j = 0; j < unique; j++) {\n if (strcmp(words[j].word, word) == 0) {\n words[j].count++;\n found = 1;\n break;\n }\n }\n if (!found) {\n strcpy(words[unique].word, word);\n words[unique].count = 1;\n unique++;\n }\n pos = 0;\n }\n }\n str++;\n }\n if (pos > 0) {\n word[pos] = '\\0';\n int found = 0;\n for (int j = 0; j < unique; j++) {\n if (strcmp(words[j].word, word) == 0) {\n words[j].count++;\n found = 1;\n break;\n }\n }\n if (!found) {\n strcpy(words[unique].word, word);\n words[unique].count = 1;\n unique++;\n }\n }\n }\n int max = 0;\n int index = 0;\n for (int i = 0; i < unique; i++) {\n if (words[i].count > max) {\n max = words[i].count;\n index = i;\n }\n }\n return words[index].word;\n}", + "test": "int main(){\n\n const char* test1[] = {\"UTS is best for RTF\", \"RTF love UTS\", \"UTS is best\"};\n\n assert(strcmp(func0(3, test1), \"UTS\") == 0);\n\n \n\n const char* test2[] = {\"Its been a great year\", \"this year is so worse\", \"this year is okay\"};\n\n assert(strcmp(func0(3, test2), \"year\") == 0);\n\n \n\n const char* test3[] = {\"Families can be reunited\", \"people can be reunited\", \"Tasks can be achieved \"};\n\n assert(strcmp(func0(3, test3), \"can\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x58,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\ntest %edi,%edi\njle 15ec \nlea -0x1(%rdi),%eax\nmov %rsi,(%rsp)\nxor %ebp,%ebp\nlea 0x8(%rsi,%rax,8),%rax\nmov %rax,0x8(%rsp)\nnopl (%rax)\nmov (%rsp),%rax\nmov (%rax),%rbx\nmovzbl (%rbx),%r15d\ntest %r15b,%r15b\nje 1464 \ncallq 10d0 <__ctype_b_loc@plt>\nmov %rax,%r12\nxor %eax,%eax\njmp 13cd \nmovslq %eax,%rdx\nadd $0x1,%eax\nmov %r15b,0x10(%rsp,%rdx,1)\nmovzbl 0x1(%rbx),%r15d\nadd $0x1,%rbx\ntest %r15b,%r15b\nje 1460 \nmov (%r12),%rsi\nmovsbq %r15b,%rdx\ntestb $0x20,0x1(%rsi,%rdx,2)\nje 13b0 \ntest %eax,%eax\nje 13bb \ncltq\nlea 0x10(%rsp),%r15\nmovb $0x0,0x10(%rsp,%rax,1)\ntest %ebp,%ebp\nje 1560 \nlea 0x2c45(%rip),%r13\nxor %r14d,%r14d\nlea 0x10(%rsp),%r15\njmp 1419 \nnopl (%rax)\nadd $0x1,%r14d\nadd $0x38,%r13\ncmp %ebp,%r14d\nje 1560 \nmov %r15,%rsi\nmov %r13,%rdi\ncallq 10b0 \ntest %eax,%eax\njne 1408 \nmovslq %r14d,%rdx\nadd $0x1,%rbx\nlea 0x0(,%rdx,8),%rcx\nsub %rdx,%rcx\nmov %rcx,%rdx\nlea 0x2bfc(%rip),%rcx\naddl $0x1,0x34(%rcx,%rdx,8)\nmovzbl (%rbx),%r15d\ntest %r15b,%r15b\njne 13cd \nnopw %cs:0x0(%rax,%rax,1)\ntest %eax,%eax\njne 14e0 \naddq $0x8,(%rsp)\nmov (%rsp),%rax\ncmp %rax,0x8(%rsp)\njne 1390 \ntest %ebp,%ebp\nje 15ec \nlea 0x2bed(%rip),%rdx\nxor %eax,%eax\nxor %edi,%edi\nxor %esi,%esi\nnopl (%rax)\nmov (%rdx),%ecx\ncmp %esi,%ecx\njle 149b \nmovslq %eax,%rdi\nmov %ecx,%esi\nadd $0x1,%eax\nadd $0x38,%rdx\ncmp %eax,%ebp\njne 1490 \nlea 0x0(,%rdi,8),%rax\nlea 0x2b8b(%rip),%rcx\nsub %rdi,%rax\nlea (%rcx,%rax,8),%rax\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 15f8 \nadd $0x58,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\ncltq\nlea 0x10(%rsp),%r15\nmovb $0x0,0x10(%rsp,%rax,1)\ntest %ebp,%ebp\nje 15a0 \nlea 0x2b45(%rip),%r12\nxor %ebx,%ebx\nlea 0x10(%rsp),%r15\njmp 1517 \nnopl 0x0(%rax)\nadd $0x1,%ebx\nadd $0x38,%r12\ncmp %ebx,%ebp\nje 15a0 \nmov %r15,%rsi\nmov %r12,%rdi\ncallq 10b0 \ntest %eax,%eax\njne 1508 \nmovslq %ebx,%rbx\nlea 0x2b10(%rip),%rcx\naddq $0x8,(%rsp)\nlea 0x0(,%rbx,8),%rax\nsub %rbx,%rax\naddl $0x1,0x34(%rcx,%rax,8)\nmov (%rsp),%rax\ncmp %rax,0x8(%rsp)\njne 1390 \njmpq 1478 \nnopl 0x0(%rax)\nmovslq %ebp,%rdx\nlea 0x2ad6(%rip),%rcx\nmov %r15,%rsi\nadd $0x1,%ebp\nlea 0x0(,%rdx,8),%rax\nsub %rdx,%rax\nmov $0x32,%edx\nlea (%rcx,%rax,8),%rcx\nmov %rcx,%rdi\ncallq 10c0 <__strcpy_chk@plt>\nmovl $0x1,0x34(%rax)\nxor %eax,%eax\njmpq 13bb \nnopw 0x0(%rax,%rax,1)\nmovslq %ebp,%rdx\nlea 0x2a96(%rip),%rcx\nmov %r15,%rsi\nadd $0x1,%ebp\nlea 0x0(,%rdx,8),%rax\nsub %rdx,%rax\nmov $0x32,%edx\nlea (%rcx,%rax,8),%rcx\nmov %rcx,%rdi\ncallq 10c0 <__strcpy_chk@plt>\naddq $0x8,(%rsp)\nmovl $0x1,0x34(%rax)\nmov (%rsp),%rax\ncmp %rax,0x8(%rsp)\njne 1390 \njmpq 1478 \nlea 0x2a4d(%rip),%rax\njmpq 14bc \ncallq 1090 <__stack_chk_fail@plt>\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 68h\nmov rax, fs:28h\nmov [rsp+98h+var_40], rax\nxor eax, eax\ntest edi, edi\njle loc_15EA\nmovsxd rdi, edi\nmov [rsp+98h+var_88], rsi\nxor ebp, ebp\nlea rax, [rsi+rdi*8]\nmov [rsp+98h+var_80], rax\nnop dword ptr [rax]\nloc_13A0:\nmov rax, [rsp+98h+var_88]\nmov rbx, [rax]\nmovzx r14d, byte ptr [rbx]\ntest r14b, r14b\njz loc_1474\ncall ___ctype_b_loc\nlea r12, [rsp+98h+s2]\nmov r13, rax\nxor eax, eax\njmp short loc_13ED\nloc_13D0:\nmovsxd rdx, eax\nadd eax, 1\nmov [rsp+rdx+98h+s2], r14b\nloc_13DB:\nmovzx r14d, byte ptr [rbx+1]\nadd rbx, 1\ntest r14b, r14b\njz loc_1470\nloc_13ED:\nmov rcx, [r13+0]\nmovsx rdx, r14b\ntest byte ptr [rcx+rdx*2+1], 20h\njz short loc_13D0\ntest eax, eax\njle short loc_13DB\ncdqe\nmov [rsp+rax+98h+s2], 0\ntest ebp, ebp\njle loc_1557\nmov [rsp+98h+var_90], r12\nlea r14, words_1\nxor r15d, r15d\njmp short loc_1431\nloc_1420:\nadd r15d, 1\nadd r14, 38h ; '8'\ncmp r15d, ebp\njz loc_1568\nloc_1431:\nmov rsi, r12; s2\nmov rdi, r14; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1420\nmovsxd rdx, r15d\nlea rsi, words_1\nadd rbx, 1\nlea rcx, ds:0[rdx*8]\nsub rcx, rdx\nadd dword ptr [rsi+rcx*8+34h], 1\nmovzx r14d, byte ptr [rbx]\ntest r14b, r14b\njnz short loc_13ED\nnop word ptr [rax+rax+00000000h]\nloc_1470:\ntest eax, eax\njg short loc_14F0\nloc_1474:\nadd [rsp+98h+var_88], 8\nmov rax, [rsp+98h+var_88]\ncmp [rsp+98h+var_80], rax\njnz loc_13A0\ntest ebp, ebp\njle loc_15EA\nlea rdx, unk_4074\nxor eax, eax\nxor edi, edi\nxor esi, esi\nnop\nloc_14A0:\nmov ecx, [rdx]\ncmp ecx, esi\njle short loc_14AB\nmovsxd rdi, eax\nmov esi, ecx\nloc_14AB:\nadd eax, 1\nadd rdx, 38h ; '8'\ncmp ebp, eax\njnz short loc_14A0\nlea rax, ds:0[rdi*8]\nsub rax, rdi\nlea rdi, words_1\nlea rax, [rdi+rax*8]\nloc_14CC:\nmov rdx, [rsp+98h+var_40]\nsub rdx, fs:28h\njnz loc_15F6\nadd rsp, 68h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14F0:\ncdqe\nmov [rsp+rax+98h+s2], 0\ntest ebp, ebp\njle loc_15A4\nlea rax, [rsp+98h+s2]\nlea r12, words_1\nxor ebx, ebx\nmov [rsp+98h+var_90], rax\njmp short loc_1527\nloc_1518:\nadd ebx, 1\nadd r12, 38h ; '8'\ncmp ebp, ebx\njz loc_15B0\nloc_1527:\nmov rsi, [rsp+98h+var_90]; s2\nmov rdi, r12; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1518\nmovsxd rbx, ebx\nlea rdi, words_1\nlea rax, ds:0[rbx*8]\nsub rax, rbx\nadd dword ptr [rdi+rax*8+34h], 1\njmp loc_1474\nloc_1557:\nlea rax, [rsp+98h+s2]\nmov [rsp+98h+var_90], rax\nnop dword ptr [rax+00000000h]\nloc_1568:\nmovsxd rdx, ebp\nlea rsi, words_1\nadd ebp, 1\nlea rax, ds:0[rdx*8]\nsub rax, rdx\nmov edx, 32h ; '2'\nlea rcx, [rsi+rax*8]\nmov rsi, [rsp+98h+var_90]\nmov rdi, rcx\ncall ___strcpy_chk\nmov dword ptr [rax+34h], 1\nxor eax, eax\njmp loc_13DB\nloc_15A4:\nlea rax, [rsp+98h+s2]\nmov [rsp+98h+var_90], rax\nxchg ax, ax\nloc_15B0:\nmovsxd rdx, ebp\nlea rdi, words_1\nmov rsi, [rsp+98h+var_90]\nadd ebp, 1\nlea rax, ds:0[rdx*8]\nsub rax, rdx\nmov edx, 32h ; '2'\nlea rcx, [rdi+rax*8]\nmov rdi, rcx\ncall ___strcpy_chk\nmov dword ptr [rax+34h], 1\njmp loc_1474\nloc_15EA:\nlea rax, words_1\njmp loc_14CC\nloc_15F6:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(int a1, char **a2)\n{\n int v2; // ebp\n char *v3; // rbx\n char v4; // r14\n const unsigned __int16 **v5; // r13\n int v6; // eax\n __int64 v7; // rdx\n const char *v8; // r14\n int v9; // r15d\n int *v10; // rdx\n int v11; // eax\n __int64 v12; // rdi\n int v13; // esi\n const char *v15; // r12\n int v16; // ebx\n int i; // eax\n __int64 v18; // rdx\n __int64 v19; // rdx\n char **v20; // [rsp+10h] [rbp-88h]\n char s2[56]; // [rsp+20h] [rbp-78h] BYREF\n unsigned __int64 v22; // [rsp+58h] [rbp-40h]\n\n v22 = __readfsqword(0x28u);\n if ( a1 <= 0 )\n return words_1;\n v20 = a2;\n v2 = 0;\n do\n {\n v3 = *v20;\n v4 = **v20;\n if ( !v4 )\n goto LABEL_15;\n v5 = __ctype_b_loc();\n v6 = 0;\n do\n {\n while ( ((*v5)[v4] & 0x2000) == 0 )\n {\n v7 = v6++;\n s2[v7] = v4;\nLABEL_6:\n v4 = *++v3;\n if ( !v4 )\n goto LABEL_14;\n }\n if ( v6 <= 0 )\n goto LABEL_6;\n s2[v6] = 0;\n if ( v2 <= 0 )\n {\nLABEL_28:\n v18 = v2++;\n *(_DWORD *)(__strcpy_chk(&words_1[56 * v18], s2, 50LL) + 52) = 1;\n v6 = 0;\n goto LABEL_6;\n }\n v8 = words_1;\n v9 = 0;\n while ( 1 )\n {\n v6 = strcmp(v8, s2);\n if ( !v6 )\n break;\n ++v9;\n v8 += 56;\n if ( v9 == v2 )\n goto LABEL_28;\n }\n ++v3;\n ++*(_DWORD *)&words_1[56 * v9 + 52];\n v4 = *v3;\n }\n while ( *v3 );\nLABEL_14:\n if ( v6 > 0 )\n {\n s2[v6] = 0;\n if ( v2 <= 0 )\n {\nLABEL_29:\n v19 = v2++;\n *(_DWORD *)(__strcpy_chk(&words_1[56 * v19], s2, 50LL) + 52) = 1;\n }\n else\n {\n v15 = words_1;\n v16 = 0;\n for ( i = strcmp(words_1, s2); i; i = strcmp(v15, s2) )\n {\n ++v16;\n v15 += 56;\n if ( v2 == v16 )\n goto LABEL_29;\n }\n ++*(_DWORD *)&words_1[56 * v16 + 52];\n }\n }\nLABEL_15:\n ++v20;\n }\n while ( &a2[a1] != v20 );\n if ( v2 <= 0 )\n return words_1;\n v10 = (int *)&unk_4074;\n v11 = 0;\n v12 = 0LL;\n v13 = 0;\n do\n {\n if ( *v10 > v13 )\n {\n v12 = v11;\n v13 = *v10;\n }\n ++v11;\n v10 += 14;\n }\n while ( v2 != v11 );\n return &words_1[56 * v12];\n}", + "ida_strip_asm": "sub_1360:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 68h\nmov rax, fs:28h\nmov [rsp+98h+var_40], rax\nxor eax, eax\ntest edi, edi\njle loc_15EA\nmovsxd rdi, edi\nmov [rsp+98h+var_88], rsi\nxor ebp, ebp\nlea rax, [rsi+rdi*8]\nmov [rsp+98h+var_80], rax\nnop dword ptr [rax]\nloc_13A0:\nmov rax, [rsp+98h+var_88]\nmov rbx, [rax]\nmovzx r14d, byte ptr [rbx]\ntest r14b, r14b\njz loc_1474\ncall ___ctype_b_loc\nlea r12, [rsp+98h+s2]\nmov r13, rax\nxor eax, eax\njmp short loc_13ED\nloc_13D0:\nmovsxd rdx, eax\nadd eax, 1\nmov [rsp+rdx+98h+s2], r14b\nloc_13DB:\nmovzx r14d, byte ptr [rbx+1]\nadd rbx, 1\ntest r14b, r14b\njz loc_1470\nloc_13ED:\nmov rcx, [r13+0]\nmovsx rdx, r14b\ntest byte ptr [rcx+rdx*2+1], 20h\njz short loc_13D0\ntest eax, eax\njle short loc_13DB\ncdqe\nmov [rsp+rax+98h+s2], 0\ntest ebp, ebp\njle loc_1557\nmov [rsp+98h+var_90], r12\nlea r14, s1\nxor r15d, r15d\njmp short loc_1431\nloc_1420:\nadd r15d, 1\nadd r14, 38h ; '8'\ncmp r15d, ebp\njz loc_1568\nloc_1431:\nmov rsi, r12; s2\nmov rdi, r14; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1420\nmovsxd rdx, r15d\nlea rsi, s1\nadd rbx, 1\nlea rcx, ds:0[rdx*8]\nsub rcx, rdx\nadd dword ptr [rsi+rcx*8+34h], 1\nmovzx r14d, byte ptr [rbx]\ntest r14b, r14b\njnz short loc_13ED\nnop word ptr [rax+rax+00000000h]\nloc_1470:\ntest eax, eax\njg short loc_14F0\nloc_1474:\nadd [rsp+98h+var_88], 8\nmov rax, [rsp+98h+var_88]\ncmp [rsp+98h+var_80], rax\njnz loc_13A0\ntest ebp, ebp\njle loc_15EA\nlea rdx, unk_4074\nxor eax, eax\nxor edi, edi\nxor esi, esi\nnop\nloc_14A0:\nmov ecx, [rdx]\ncmp ecx, esi\njle short loc_14AB\nmovsxd rdi, eax\nmov esi, ecx\nloc_14AB:\nadd eax, 1\nadd rdx, 38h ; '8'\ncmp ebp, eax\njnz short loc_14A0\nlea rax, ds:0[rdi*8]\nsub rax, rdi\nlea rdi, s1\nlea rax, [rdi+rax*8]\nloc_14CC:\nmov rdx, [rsp+98h+var_40]\nsub rdx, fs:28h\njnz loc_15F6\nadd rsp, 68h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14F0:\ncdqe\nmov [rsp+rax+98h+s2], 0\ntest ebp, ebp\njle loc_15A4\nlea rax, [rsp+98h+s2]\nlea r12, s1\nxor ebx, ebx\nmov [rsp+98h+var_90], rax\njmp short loc_1527\nloc_1518:\nadd ebx, 1\nadd r12, 38h ; '8'\ncmp ebp, ebx\njz loc_15B0\nloc_1527:\nmov rsi, [rsp+98h+var_90]; s2\nmov rdi, r12; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1518\nmovsxd rbx, ebx\nlea rdi, s1\nlea rax, ds:0[rbx*8]\nsub rax, rbx\nadd dword ptr [rdi+rax*8+34h], 1\njmp loc_1474\nloc_1557:\nlea rax, [rsp+98h+s2]\nmov [rsp+98h+var_90], rax\nnop dword ptr [rax+00000000h]\nloc_1568:\nmovsxd rdx, ebp\nlea rsi, s1\nadd ebp, 1\nlea rax, ds:0[rdx*8]\nsub rax, rdx\nmov edx, 32h ; '2'\nlea rcx, [rsi+rax*8]\nmov rsi, [rsp+98h+var_90]\nmov rdi, rcx\ncall ___strcpy_chk\nmov dword ptr [rax+34h], 1\nxor eax, eax\njmp loc_13DB\nloc_15A4:\nlea rax, [rsp+98h+s2]\nmov [rsp+98h+var_90], rax\nxchg ax, ax\nloc_15B0:\nmovsxd rdx, ebp\nlea rdi, s1\nmov rsi, [rsp+98h+var_90]\nadd ebp, 1\nlea rax, ds:0[rdx*8]\nsub rax, rdx\nmov edx, 32h ; '2'\nlea rcx, [rdi+rax*8]\nmov rdi, rcx\ncall ___strcpy_chk\nmov dword ptr [rax+34h], 1\njmp loc_1474\nloc_15EA:\nlea rax, s1\njmp loc_14CC\nloc_15F6:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_1360(int a1, char **a2)\n{\n int v2; // ebp\n char *v3; // rbx\n char v4; // r14\n const unsigned __int16 **v5; // r13\n int v6; // eax\n __int64 v7; // rdx\n const char *v8; // r14\n int v9; // r15d\n int *v10; // rdx\n int v11; // eax\n __int64 v12; // rdi\n int v13; // esi\n const char *v15; // r12\n int v16; // ebx\n int i; // eax\n __int64 v18; // rdx\n __int64 v19; // rdx\n char **v20; // [rsp+10h] [rbp-88h]\n char s2[56]; // [rsp+20h] [rbp-78h] BYREF\n unsigned __int64 v22; // [rsp+58h] [rbp-40h]\n\n v22 = __readfsqword(0x28u);\n if ( a1 <= 0 )\n return s1;\n v20 = a2;\n v2 = 0;\n do\n {\n v3 = *v20;\n v4 = **v20;\n if ( !v4 )\n goto LABEL_15;\n v5 = __ctype_b_loc();\n v6 = 0;\n do\n {\n while ( ((*v5)[v4] & 0x2000) == 0 )\n {\n v7 = v6++;\n s2[v7] = v4;\nLABEL_6:\n v4 = *++v3;\n if ( !v4 )\n goto LABEL_14;\n }\n if ( v6 <= 0 )\n goto LABEL_6;\n s2[v6] = 0;\n if ( v2 <= 0 )\n {\nLABEL_28:\n v18 = v2++;\n *(_DWORD *)(__strcpy_chk(&s1[56 * v18], s2, 50LL) + 52) = 1;\n v6 = 0;\n goto LABEL_6;\n }\n v8 = s1;\n v9 = 0;\n while ( 1 )\n {\n v6 = strcmp(v8, s2);\n if ( !v6 )\n break;\n ++v9;\n v8 += 56;\n if ( v9 == v2 )\n goto LABEL_28;\n }\n ++v3;\n ++*(_DWORD *)&s1[56 * v9 + 52];\n v4 = *v3;\n }\n while ( *v3 );\nLABEL_14:\n if ( v6 > 0 )\n {\n s2[v6] = 0;\n if ( v2 <= 0 )\n {\nLABEL_29:\n v19 = v2++;\n *(_DWORD *)(__strcpy_chk(&s1[56 * v19], s2, 50LL) + 52) = 1;\n }\n else\n {\n v15 = s1;\n v16 = 0;\n for ( i = strcmp(s1, s2); i; i = strcmp(v15, s2) )\n {\n ++v16;\n v15 += 56;\n if ( v2 == v16 )\n goto LABEL_29;\n }\n ++*(_DWORD *)&s1[56 * v16 + 52];\n }\n }\nLABEL_15:\n ++v20;\n }\n while ( &a2[a1] != v20 );\n if ( v2 <= 0 )\n return s1;\n v10 = (int *)&unk_4074;\n v11 = 0;\n v12 = 0LL;\n v13 = 0;\n do\n {\n if ( *v10 > v13 )\n {\n v12 = v11;\n v13 = *v10;\n }\n ++v11;\n v10 += 14;\n }\n while ( v2 != v11 );\n return &s1[56 * v12];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1360(int a1, char **a2) {\n int v2;\n char *v3;\n char v4;\n const unsigned short **v5;\n int v6;\n long long v7;\n const char *v8;\n int v9;\n int *v10;\n int v11;\n long long v12;\n int v13;\n const char *v15;\n int v16;\n int i;\n long long v18;\n long long v19;\n char **v20;\n char s2[56];\n unsigned long long v22;\n v22 = __readfsqword(40u);\n if (a1 <= 0) return s1;\n v20 = a2;\n v2 = 0;\n do {\n v3 = *v20;\n v4 = **v20;\n if (!v4) goto LABEL_15;\n v5 = __ctype_b_loc();\n v6 = 0;\n do {\n while (((*v5)[v4] & 8192) == 0) {\n v7 = v6++;\n s2[v7] = v4;\n LABEL_6:\n v4 = *++v3;\n if (!v4) goto LABEL_14;\n }\n if (v6 <= 0) goto LABEL_6;\n s2[v6] = 0;\n if (v2 <= 0) {\n LABEL_28:\n v18 = v2++;\n *(uint32_t *)(__strcpy_chk(&s1[56 * v18], s2, 50LL) + 52) = 1;\n v6 = 0;\n goto LABEL_6;\n }\n v8 = s1;\n v9 = 0;\n while (1) {\n v6 = strcmp(v8, s2);\n if (!v6) break;\n ++v9;\n v8 += 56;\n if (v9 == v2) goto LABEL_28;\n }\n ++v3;\n ++*(uint32_t *)&s1[56 * v9 + 52];\n v4 = *v3;\n } while (*v3);\n LABEL_14:\n if (v6 > 0) {\n s2[v6] = 0;\n if (v2 <= 0) {\n LABEL_29:\n v19 = v2++;\n *(uint32_t *)(__strcpy_chk(&s1[56 * v19], s2, 50LL) + 52) = 1;\n } else {\n v15 = s1;\n v16 = 0;\n for (i = strcmp(s1, s2); i; i = strcmp(v15, s2)) {\n ++v16;\n v15 += 56;\n if (v2 == v16) goto LABEL_29;\n }\n ++*(uint32_t *)&s1[56 * v16 + 52];\n }\n }\n LABEL_15:\n ++v20;\n } while (&a2[a1] != v20);\n if (v2 <= 0) return s1;\n v10 = (int *)&unk_4074;\n v11 = 0;\n v12 = 0LL;\n v13 = 0;\n do {\n if (*v10 > v13) {\n v12 = v11;\n v13 = *v10;\n }\n ++v11;\n v10 += 14;\n } while (v2 != v11);\n return &s1[56 * v12];\n}", + "ida_pseudo_norm": "char *func0(int a1, char **a2) {\n int v2;\n char *v3;\n char v4;\n const unsigned short **v5;\n int v6;\n long long v7;\n const char *v8;\n int v9;\n int *v10;\n int v11;\n long long v12;\n int v13;\n const char *v15;\n int v16;\n int i;\n long long v18;\n long long v19;\n char **v20;\n char s2[56];\n unsigned long long v22;\n v22 = __readfsqword(40u);\n if (a1 <= 0) return words_1;\n v20 = a2;\n v2 = 0;\n do {\n v3 = *v20;\n v4 = **v20;\n if (!v4) goto LABEL_15;\n v5 = __ctype_b_loc();\n v6 = 0;\n do {\n while (((*v5)[v4] & 8192) == 0) {\n v7 = v6++;\n s2[v7] = v4;\n LABEL_6:\n v4 = *++v3;\n if (!v4) goto LABEL_14;\n }\n if (v6 <= 0) goto LABEL_6;\n s2[v6] = 0;\n if (v2 <= 0) {\n LABEL_28:\n v18 = v2++;\n *(uint32_t *)(__strcpy_chk(&words_1[56 * v18], s2, 50LL) + 52) = 1;\n v6 = 0;\n goto LABEL_6;\n }\n v8 = words_1;\n v9 = 0;\n while (1) {\n v6 = strcmp(v8, s2);\n if (!v6) break;\n ++v9;\n v8 += 56;\n if (v9 == v2) goto LABEL_28;\n }\n ++v3;\n ++*(uint32_t *)&words_1[56 * v9 + 52];\n v4 = *v3;\n } while (*v3);\n LABEL_14:\n if (v6 > 0) {\n s2[v6] = 0;\n if (v2 <= 0) {\n LABEL_29:\n v19 = v2++;\n *(uint32_t *)(__strcpy_chk(&words_1[56 * v19], s2, 50LL) + 52) = 1;\n } else {\n v15 = words_1;\n v16 = 0;\n for (i = strcmp(words_1, s2); i; i = strcmp(v15, s2)) {\n ++v16;\n v15 += 56;\n if (v2 == v16) goto LABEL_29;\n }\n ++*(uint32_t *)&words_1[56 * v16 + 52];\n }\n }\n LABEL_15:\n ++v20;\n } while (&a2[a1] != v20);\n if (v2 <= 0) return words_1;\n v10 = (int *)&unk_4074;\n v11 = 0;\n v12 = 0LL;\n v13 = 0;\n do {\n if (*v10 > v13) {\n v12 = v11;\n v13 = *v10;\n }\n ++v11;\n v10 += 14;\n } while (v2 != v11);\n return &words_1[56 * v12];\n}" + }, + { + "index": 326, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char word[50];\n\n int count;\n\n} WordCount;\n\n\n\n", + "func": "const char* func0(int n, const char* test_list[]) {\n static WordCount words[100];\n int unique = 0;\n for (int i = 0; i < n; i++) {\n const char* str = test_list[i];\n char word[50];\n int pos = 0;\n while (*str) {\n if (!isspace(*str)) {\n word[pos++] = *str;\n }\n else {\n if (pos > 0) {\n word[pos] = '\\0';\n int found = 0;\n for (int j = 0; j < unique; j++) {\n if (strcmp(words[j].word, word) == 0) {\n words[j].count++;\n found = 1;\n break;\n }\n }\n if (!found) {\n strcpy(words[unique].word, word);\n words[unique].count = 1;\n unique++;\n }\n pos = 0;\n }\n }\n str++;\n }\n if (pos > 0) {\n word[pos] = '\\0';\n int found = 0;\n for (int j = 0; j < unique; j++) {\n if (strcmp(words[j].word, word) == 0) {\n words[j].count++;\n found = 1;\n break;\n }\n }\n if (!found) {\n strcpy(words[unique].word, word);\n words[unique].count = 1;\n unique++;\n }\n }\n }\n int max = 0;\n int index = 0;\n for (int i = 0; i < unique; i++) {\n if (words[i].count > max) {\n max = words[i].count;\n index = i;\n }\n }\n return words[index].word;\n}", + "test": "int main(){\n\n const char* test1[] = {\"UTS is best for RTF\", \"RTF love UTS\", \"UTS is best\"};\n\n assert(strcmp(func0(3, test1), \"UTS\") == 0);\n\n \n\n const char* test2[] = {\"Its been a great year\", \"this year is so worse\", \"this year is okay\"};\n\n assert(strcmp(func0(3, test2), \"year\") == 0);\n\n \n\n const char* test3[] = {\"Families can be reunited\", \"people can be reunited\", \"Tasks can be achieved \"};\n\n assert(strcmp(func0(3, test3), \"can\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x58,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\ntest %edi,%edi\njle 160c \nlea -0x1(%rdi),%eax\nmov %rsi,(%rsp)\nxor %ebp,%ebp\nlea 0x8(%rsi,%rax,8),%rax\nmov %rax,0x8(%rsp)\nnopl (%rax)\nmov (%rsp),%rax\nmov (%rax),%rbx\nmovzbl (%rbx),%r15d\ntest %r15b,%r15b\nje 1484 \ncallq 10d0 <__ctype_b_loc@plt>\nmov %rax,%r12\nxor %eax,%eax\njmp 13ed \nmovslq %eax,%rdx\nadd $0x1,%eax\nmov %r15b,0x10(%rsp,%rdx,1)\nmovzbl 0x1(%rbx),%r15d\nadd $0x1,%rbx\ntest %r15b,%r15b\nje 1480 \nmov (%r12),%rsi\nmovsbq %r15b,%rdx\ntestb $0x20,0x1(%rsi,%rdx,2)\nje 13d0 \ntest %eax,%eax\nje 13db \ncltq\nlea 0x10(%rsp),%r15\nmovb $0x0,0x10(%rsp,%rax,1)\ntest %ebp,%ebp\nje 1580 \nlea 0x2c25(%rip),%r13\nxor %r14d,%r14d\nlea 0x10(%rsp),%r15\njmp 1439 \nnopl (%rax)\nadd $0x1,%r14d\nadd $0x38,%r13\ncmp %ebp,%r14d\nje 1580 \nmov %r15,%rsi\nmov %r13,%rdi\ncallq 10b0 \ntest %eax,%eax\njne 1428 \nmovslq %r14d,%rdx\nadd $0x1,%rbx\nlea 0x0(,%rdx,8),%rcx\nsub %rdx,%rcx\nmov %rcx,%rdx\nlea 0x2bdc(%rip),%rcx\naddl $0x1,0x34(%rcx,%rdx,8)\nmovzbl (%rbx),%r15d\ntest %r15b,%r15b\njne 13ed \nnopw %cs:0x0(%rax,%rax,1)\ntest %eax,%eax\njne 1500 \naddq $0x8,(%rsp)\nmov (%rsp),%rax\ncmp %rax,0x8(%rsp)\njne 13b0 \ntest %ebp,%ebp\nje 160c \nlea 0x2bcd(%rip),%rdx\nxor %eax,%eax\nxor %edi,%edi\nxor %esi,%esi\nnopl (%rax)\nmov (%rdx),%ecx\ncmp %esi,%ecx\njle 14bb \nmovslq %eax,%rdi\nmov %ecx,%esi\nadd $0x1,%eax\nadd $0x38,%rdx\ncmp %eax,%ebp\njne 14b0 \nlea 0x0(,%rdi,8),%rax\nlea 0x2b6b(%rip),%rcx\nsub %rdi,%rax\nlea (%rcx,%rax,8),%rax\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 1618 \nadd $0x58,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\ncltq\nlea 0x10(%rsp),%r15\nmovb $0x0,0x10(%rsp,%rax,1)\ntest %ebp,%ebp\nje 15c0 \nlea 0x2b25(%rip),%r12\nxor %ebx,%ebx\nlea 0x10(%rsp),%r15\njmp 1537 \nnopl 0x0(%rax)\nadd $0x1,%ebx\nadd $0x38,%r12\ncmp %ebx,%ebp\nje 15c0 \nmov %r15,%rsi\nmov %r12,%rdi\ncallq 10b0 \ntest %eax,%eax\njne 1528 \nmovslq %ebx,%rbx\nlea 0x2af0(%rip),%rcx\naddq $0x8,(%rsp)\nlea 0x0(,%rbx,8),%rax\nsub %rbx,%rax\naddl $0x1,0x34(%rcx,%rax,8)\nmov (%rsp),%rax\ncmp %rax,0x8(%rsp)\njne 13b0 \njmpq 1498 \nnopl 0x0(%rax)\nmovslq %ebp,%rdx\nlea 0x2ab6(%rip),%rcx\nmov %r15,%rsi\nadd $0x1,%ebp\nlea 0x0(,%rdx,8),%rax\nsub %rdx,%rax\nmov $0x32,%edx\nlea (%rcx,%rax,8),%rcx\nmov %rcx,%rdi\ncallq 10c0 <__strcpy_chk@plt>\nmovl $0x1,0x34(%rax)\nxor %eax,%eax\njmpq 13db \nnopw 0x0(%rax,%rax,1)\nmovslq %ebp,%rdx\nlea 0x2a76(%rip),%rcx\nmov %r15,%rsi\nadd $0x1,%ebp\nlea 0x0(,%rdx,8),%rax\nsub %rdx,%rax\nmov $0x32,%edx\nlea (%rcx,%rax,8),%rcx\nmov %rcx,%rdi\ncallq 10c0 <__strcpy_chk@plt>\naddq $0x8,(%rsp)\nmovl $0x1,0x34(%rax)\nmov (%rsp),%rax\ncmp %rax,0x8(%rsp)\njne 13b0 \njmpq 1498 \nlea 0x2a2d(%rip),%rax\njmpq 14dc \ncallq 1090 <__stack_chk_fail@plt>\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 68h\nmov rax, fs:28h\nmov [rsp+98h+var_40], rax\nxor eax, eax\ntest edi, edi\njle loc_15EA\nmovsxd rdi, edi\nmov [rsp+98h+var_88], rsi\nxor ebp, ebp\nlea rax, [rsi+rdi*8]\nmov [rsp+98h+var_80], rax\nnop dword ptr [rax]\nloc_13A0:\nmov rax, [rsp+98h+var_88]\nmov rbx, [rax]\nmovzx r14d, byte ptr [rbx]\ntest r14b, r14b\njz loc_1474\ncall ___ctype_b_loc\nlea r12, [rsp+98h+s2]\nmov r13, rax\nxor eax, eax\njmp short loc_13ED\nloc_13D0:\nmovsxd rdx, eax\nadd eax, 1\nmov [rsp+rdx+98h+s2], r14b\nloc_13DB:\nmovzx r14d, byte ptr [rbx+1]\nadd rbx, 1\ntest r14b, r14b\njz loc_1470\nloc_13ED:\nmov rcx, [r13+0]\nmovsx rdx, r14b\ntest byte ptr [rcx+rdx*2+1], 20h\njz short loc_13D0\ntest eax, eax\njle short loc_13DB\ncdqe\nmov [rsp+rax+98h+s2], 0\ntest ebp, ebp\njle loc_1557\nmov [rsp+98h+var_90], r12\nlea r14, words_1\nxor r15d, r15d\njmp short loc_1431\nloc_1420:\nadd r15d, 1\nadd r14, 38h ; '8'\ncmp r15d, ebp\njz loc_1568\nloc_1431:\nmov rsi, r12; s2\nmov rdi, r14; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1420\nmovsxd rdx, r15d\nlea rsi, words_1\nadd rbx, 1\nlea rcx, ds:0[rdx*8]\nsub rcx, rdx\nadd dword ptr [rsi+rcx*8+34h], 1\nmovzx r14d, byte ptr [rbx]\ntest r14b, r14b\njnz short loc_13ED\nnop word ptr [rax+rax+00000000h]\nloc_1470:\ntest eax, eax\njg short loc_14F0\nloc_1474:\nadd [rsp+98h+var_88], 8\nmov rax, [rsp+98h+var_88]\ncmp [rsp+98h+var_80], rax\njnz loc_13A0\ntest ebp, ebp\njle loc_15EA\nlea rdx, unk_4074\nxor eax, eax\nxor edi, edi\nxor esi, esi\nnop\nloc_14A0:\nmov ecx, [rdx]\ncmp ecx, esi\njle short loc_14AB\nmovsxd rdi, eax\nmov esi, ecx\nloc_14AB:\nadd eax, 1\nadd rdx, 38h ; '8'\ncmp ebp, eax\njnz short loc_14A0\nlea rax, ds:0[rdi*8]\nsub rax, rdi\nlea rdi, words_1\nlea rax, [rdi+rax*8]\nloc_14CC:\nmov rdx, [rsp+98h+var_40]\nsub rdx, fs:28h\njnz loc_15F6\nadd rsp, 68h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14F0:\ncdqe\nmov [rsp+rax+98h+s2], 0\ntest ebp, ebp\njle loc_15A4\nlea rax, [rsp+98h+s2]\nlea r12, words_1\nxor ebx, ebx\nmov [rsp+98h+var_90], rax\njmp short loc_1527\nloc_1518:\nadd ebx, 1\nadd r12, 38h ; '8'\ncmp ebp, ebx\njz loc_15B0\nloc_1527:\nmov rsi, [rsp+98h+var_90]; s2\nmov rdi, r12; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1518\nmovsxd rbx, ebx\nlea rdi, words_1\nlea rax, ds:0[rbx*8]\nsub rax, rbx\nadd dword ptr [rdi+rax*8+34h], 1\njmp loc_1474\nloc_1557:\nlea rax, [rsp+98h+s2]\nmov [rsp+98h+var_90], rax\nnop dword ptr [rax+00000000h]\nloc_1568:\nmovsxd rdx, ebp\nlea rsi, words_1\nadd ebp, 1\nlea rax, ds:0[rdx*8]\nsub rax, rdx\nmov edx, 32h ; '2'\nlea rcx, [rsi+rax*8]\nmov rsi, [rsp+98h+var_90]\nmov rdi, rcx\ncall ___strcpy_chk\nmov dword ptr [rax+34h], 1\nxor eax, eax\njmp loc_13DB\nloc_15A4:\nlea rax, [rsp+98h+s2]\nmov [rsp+98h+var_90], rax\nxchg ax, ax\nloc_15B0:\nmovsxd rdx, ebp\nlea rdi, words_1\nmov rsi, [rsp+98h+var_90]\nadd ebp, 1\nlea rax, ds:0[rdx*8]\nsub rax, rdx\nmov edx, 32h ; '2'\nlea rcx, [rdi+rax*8]\nmov rdi, rcx\ncall ___strcpy_chk\nmov dword ptr [rax+34h], 1\njmp loc_1474\nloc_15EA:\nlea rax, words_1\njmp loc_14CC\nloc_15F6:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(int a1, char **a2)\n{\n int v2; // ebp\n char *v3; // rbx\n char v4; // r14\n const unsigned __int16 **v5; // r13\n int v6; // eax\n __int64 v7; // rdx\n const char *v8; // r14\n int v9; // r15d\n int *v10; // rdx\n int v11; // eax\n __int64 v12; // rdi\n int v13; // esi\n const char *v15; // r12\n int v16; // ebx\n int i; // eax\n __int64 v18; // rdx\n __int64 v19; // rdx\n char **v20; // [rsp+10h] [rbp-88h]\n char s2[56]; // [rsp+20h] [rbp-78h] BYREF\n unsigned __int64 v22; // [rsp+58h] [rbp-40h]\n\n v22 = __readfsqword(0x28u);\n if ( a1 <= 0 )\n return words_1;\n v20 = a2;\n v2 = 0;\n do\n {\n v3 = *v20;\n v4 = **v20;\n if ( !v4 )\n goto LABEL_15;\n v5 = __ctype_b_loc();\n v6 = 0;\n do\n {\n while ( ((*v5)[v4] & 0x2000) == 0 )\n {\n v7 = v6++;\n s2[v7] = v4;\nLABEL_6:\n v4 = *++v3;\n if ( !v4 )\n goto LABEL_14;\n }\n if ( v6 <= 0 )\n goto LABEL_6;\n s2[v6] = 0;\n if ( v2 <= 0 )\n {\nLABEL_28:\n v18 = v2++;\n *(_DWORD *)(__strcpy_chk(&words_1[56 * v18], s2, 50LL) + 52) = 1;\n v6 = 0;\n goto LABEL_6;\n }\n v8 = words_1;\n v9 = 0;\n while ( 1 )\n {\n v6 = strcmp(v8, s2);\n if ( !v6 )\n break;\n ++v9;\n v8 += 56;\n if ( v9 == v2 )\n goto LABEL_28;\n }\n ++v3;\n ++*(_DWORD *)&words_1[56 * v9 + 52];\n v4 = *v3;\n }\n while ( *v3 );\nLABEL_14:\n if ( v6 > 0 )\n {\n s2[v6] = 0;\n if ( v2 <= 0 )\n {\nLABEL_29:\n v19 = v2++;\n *(_DWORD *)(__strcpy_chk(&words_1[56 * v19], s2, 50LL) + 52) = 1;\n }\n else\n {\n v15 = words_1;\n v16 = 0;\n for ( i = strcmp(words_1, s2); i; i = strcmp(v15, s2) )\n {\n ++v16;\n v15 += 56;\n if ( v2 == v16 )\n goto LABEL_29;\n }\n ++*(_DWORD *)&words_1[56 * v16 + 52];\n }\n }\nLABEL_15:\n ++v20;\n }\n while ( &a2[a1] != v20 );\n if ( v2 <= 0 )\n return words_1;\n v10 = (int *)&unk_4074;\n v11 = 0;\n v12 = 0LL;\n v13 = 0;\n do\n {\n if ( *v10 > v13 )\n {\n v12 = v11;\n v13 = *v10;\n }\n ++v11;\n v10 += 14;\n }\n while ( v2 != v11 );\n return &words_1[56 * v12];\n}", + "ida_strip_asm": "sub_1360:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 68h\nmov rax, fs:28h\nmov [rsp+98h+var_40], rax\nxor eax, eax\ntest edi, edi\njle loc_15EA\nmovsxd rdi, edi\nmov [rsp+98h+var_88], rsi\nxor ebp, ebp\nlea rax, [rsi+rdi*8]\nmov [rsp+98h+var_80], rax\nnop dword ptr [rax]\nloc_13A0:\nmov rax, [rsp+98h+var_88]\nmov rbx, [rax]\nmovzx r14d, byte ptr [rbx]\ntest r14b, r14b\njz loc_1474\ncall ___ctype_b_loc\nlea r12, [rsp+98h+s2]\nmov r13, rax\nxor eax, eax\njmp short loc_13ED\nloc_13D0:\nmovsxd rdx, eax\nadd eax, 1\nmov [rsp+rdx+98h+s2], r14b\nloc_13DB:\nmovzx r14d, byte ptr [rbx+1]\nadd rbx, 1\ntest r14b, r14b\njz loc_1470\nloc_13ED:\nmov rcx, [r13+0]\nmovsx rdx, r14b\ntest byte ptr [rcx+rdx*2+1], 20h\njz short loc_13D0\ntest eax, eax\njle short loc_13DB\ncdqe\nmov [rsp+rax+98h+s2], 0\ntest ebp, ebp\njle loc_1557\nmov [rsp+98h+var_90], r12\nlea r14, s1\nxor r15d, r15d\njmp short loc_1431\nloc_1420:\nadd r15d, 1\nadd r14, 38h ; '8'\ncmp r15d, ebp\njz loc_1568\nloc_1431:\nmov rsi, r12; s2\nmov rdi, r14; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1420\nmovsxd rdx, r15d\nlea rsi, s1\nadd rbx, 1\nlea rcx, ds:0[rdx*8]\nsub rcx, rdx\nadd dword ptr [rsi+rcx*8+34h], 1\nmovzx r14d, byte ptr [rbx]\ntest r14b, r14b\njnz short loc_13ED\nnop word ptr [rax+rax+00000000h]\nloc_1470:\ntest eax, eax\njg short loc_14F0\nloc_1474:\nadd [rsp+98h+var_88], 8\nmov rax, [rsp+98h+var_88]\ncmp [rsp+98h+var_80], rax\njnz loc_13A0\ntest ebp, ebp\njle loc_15EA\nlea rdx, unk_4074\nxor eax, eax\nxor edi, edi\nxor esi, esi\nnop\nloc_14A0:\nmov ecx, [rdx]\ncmp ecx, esi\njle short loc_14AB\nmovsxd rdi, eax\nmov esi, ecx\nloc_14AB:\nadd eax, 1\nadd rdx, 38h ; '8'\ncmp ebp, eax\njnz short loc_14A0\nlea rax, ds:0[rdi*8]\nsub rax, rdi\nlea rdi, s1\nlea rax, [rdi+rax*8]\nloc_14CC:\nmov rdx, [rsp+98h+var_40]\nsub rdx, fs:28h\njnz loc_15F6\nadd rsp, 68h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14F0:\ncdqe\nmov [rsp+rax+98h+s2], 0\ntest ebp, ebp\njle loc_15A4\nlea rax, [rsp+98h+s2]\nlea r12, s1\nxor ebx, ebx\nmov [rsp+98h+var_90], rax\njmp short loc_1527\nloc_1518:\nadd ebx, 1\nadd r12, 38h ; '8'\ncmp ebp, ebx\njz loc_15B0\nloc_1527:\nmov rsi, [rsp+98h+var_90]; s2\nmov rdi, r12; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1518\nmovsxd rbx, ebx\nlea rdi, s1\nlea rax, ds:0[rbx*8]\nsub rax, rbx\nadd dword ptr [rdi+rax*8+34h], 1\njmp loc_1474\nloc_1557:\nlea rax, [rsp+98h+s2]\nmov [rsp+98h+var_90], rax\nnop dword ptr [rax+00000000h]\nloc_1568:\nmovsxd rdx, ebp\nlea rsi, s1\nadd ebp, 1\nlea rax, ds:0[rdx*8]\nsub rax, rdx\nmov edx, 32h ; '2'\nlea rcx, [rsi+rax*8]\nmov rsi, [rsp+98h+var_90]\nmov rdi, rcx\ncall ___strcpy_chk\nmov dword ptr [rax+34h], 1\nxor eax, eax\njmp loc_13DB\nloc_15A4:\nlea rax, [rsp+98h+s2]\nmov [rsp+98h+var_90], rax\nxchg ax, ax\nloc_15B0:\nmovsxd rdx, ebp\nlea rdi, s1\nmov rsi, [rsp+98h+var_90]\nadd ebp, 1\nlea rax, ds:0[rdx*8]\nsub rax, rdx\nmov edx, 32h ; '2'\nlea rcx, [rdi+rax*8]\nmov rdi, rcx\ncall ___strcpy_chk\nmov dword ptr [rax+34h], 1\njmp loc_1474\nloc_15EA:\nlea rax, s1\njmp loc_14CC\nloc_15F6:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_1360(int a1, char **a2)\n{\n int v2; // ebp\n char *v3; // rbx\n char v4; // r14\n const unsigned __int16 **v5; // r13\n int v6; // eax\n __int64 v7; // rdx\n const char *v8; // r14\n int v9; // r15d\n int *v10; // rdx\n int v11; // eax\n __int64 v12; // rdi\n int v13; // esi\n const char *v15; // r12\n int v16; // ebx\n int i; // eax\n __int64 v18; // rdx\n __int64 v19; // rdx\n char **v20; // [rsp+10h] [rbp-88h]\n char s2[56]; // [rsp+20h] [rbp-78h] BYREF\n unsigned __int64 v22; // [rsp+58h] [rbp-40h]\n\n v22 = __readfsqword(0x28u);\n if ( a1 <= 0 )\n return s1;\n v20 = a2;\n v2 = 0;\n do\n {\n v3 = *v20;\n v4 = **v20;\n if ( !v4 )\n goto LABEL_15;\n v5 = __ctype_b_loc();\n v6 = 0;\n do\n {\n while ( ((*v5)[v4] & 0x2000) == 0 )\n {\n v7 = v6++;\n s2[v7] = v4;\nLABEL_6:\n v4 = *++v3;\n if ( !v4 )\n goto LABEL_14;\n }\n if ( v6 <= 0 )\n goto LABEL_6;\n s2[v6] = 0;\n if ( v2 <= 0 )\n {\nLABEL_28:\n v18 = v2++;\n *(_DWORD *)(__strcpy_chk(&s1[56 * v18], s2, 50LL) + 52) = 1;\n v6 = 0;\n goto LABEL_6;\n }\n v8 = s1;\n v9 = 0;\n while ( 1 )\n {\n v6 = strcmp(v8, s2);\n if ( !v6 )\n break;\n ++v9;\n v8 += 56;\n if ( v9 == v2 )\n goto LABEL_28;\n }\n ++v3;\n ++*(_DWORD *)&s1[56 * v9 + 52];\n v4 = *v3;\n }\n while ( *v3 );\nLABEL_14:\n if ( v6 > 0 )\n {\n s2[v6] = 0;\n if ( v2 <= 0 )\n {\nLABEL_29:\n v19 = v2++;\n *(_DWORD *)(__strcpy_chk(&s1[56 * v19], s2, 50LL) + 52) = 1;\n }\n else\n {\n v15 = s1;\n v16 = 0;\n for ( i = strcmp(s1, s2); i; i = strcmp(v15, s2) )\n {\n ++v16;\n v15 += 56;\n if ( v2 == v16 )\n goto LABEL_29;\n }\n ++*(_DWORD *)&s1[56 * v16 + 52];\n }\n }\nLABEL_15:\n ++v20;\n }\n while ( &a2[a1] != v20 );\n if ( v2 <= 0 )\n return s1;\n v10 = (int *)&unk_4074;\n v11 = 0;\n v12 = 0LL;\n v13 = 0;\n do\n {\n if ( *v10 > v13 )\n {\n v12 = v11;\n v13 = *v10;\n }\n ++v11;\n v10 += 14;\n }\n while ( v2 != v11 );\n return &s1[56 * v12];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1360(int a1, char **a2) {\n int v2;\n char *v3;\n char v4;\n const unsigned short **v5;\n int v6;\n long long v7;\n const char *v8;\n int v9;\n int *v10;\n int v11;\n long long v12;\n int v13;\n const char *v15;\n int v16;\n int i;\n long long v18;\n long long v19;\n char **v20;\n char s2[56];\n unsigned long long v22;\n v22 = __readfsqword(40u);\n if (a1 <= 0) return s1;\n v20 = a2;\n v2 = 0;\n do {\n v3 = *v20;\n v4 = **v20;\n if (!v4) goto LABEL_15;\n v5 = __ctype_b_loc();\n v6 = 0;\n do {\n while (((*v5)[v4] & 8192) == 0) {\n v7 = v6++;\n s2[v7] = v4;\n LABEL_6:\n v4 = *++v3;\n if (!v4) goto LABEL_14;\n }\n if (v6 <= 0) goto LABEL_6;\n s2[v6] = 0;\n if (v2 <= 0) {\n LABEL_28:\n v18 = v2++;\n *(uint32_t *)(__strcpy_chk(&s1[56 * v18], s2, 50LL) + 52) = 1;\n v6 = 0;\n goto LABEL_6;\n }\n v8 = s1;\n v9 = 0;\n while (1) {\n v6 = strcmp(v8, s2);\n if (!v6) break;\n ++v9;\n v8 += 56;\n if (v9 == v2) goto LABEL_28;\n }\n ++v3;\n ++*(uint32_t *)&s1[56 * v9 + 52];\n v4 = *v3;\n } while (*v3);\n LABEL_14:\n if (v6 > 0) {\n s2[v6] = 0;\n if (v2 <= 0) {\n LABEL_29:\n v19 = v2++;\n *(uint32_t *)(__strcpy_chk(&s1[56 * v19], s2, 50LL) + 52) = 1;\n } else {\n v15 = s1;\n v16 = 0;\n for (i = strcmp(s1, s2); i; i = strcmp(v15, s2)) {\n ++v16;\n v15 += 56;\n if (v2 == v16) goto LABEL_29;\n }\n ++*(uint32_t *)&s1[56 * v16 + 52];\n }\n }\n LABEL_15:\n ++v20;\n } while (&a2[a1] != v20);\n if (v2 <= 0) return s1;\n v10 = (int *)&unk_4074;\n v11 = 0;\n v12 = 0LL;\n v13 = 0;\n do {\n if (*v10 > v13) {\n v12 = v11;\n v13 = *v10;\n }\n ++v11;\n v10 += 14;\n } while (v2 != v11);\n return &s1[56 * v12];\n}", + "ida_pseudo_norm": "char *func0(int a1, char **a2) {\n int v2;\n char *v3;\n char v4;\n const unsigned short **v5;\n int v6;\n long long v7;\n const char *v8;\n int v9;\n int *v10;\n int v11;\n long long v12;\n int v13;\n const char *v15;\n int v16;\n int i;\n long long v18;\n long long v19;\n char **v20;\n char s2[56];\n unsigned long long v22;\n v22 = __readfsqword(40u);\n if (a1 <= 0) return words_1;\n v20 = a2;\n v2 = 0;\n do {\n v3 = *v20;\n v4 = **v20;\n if (!v4) goto LABEL_15;\n v5 = __ctype_b_loc();\n v6 = 0;\n do {\n while (((*v5)[v4] & 8192) == 0) {\n v7 = v6++;\n s2[v7] = v4;\n LABEL_6:\n v4 = *++v3;\n if (!v4) goto LABEL_14;\n }\n if (v6 <= 0) goto LABEL_6;\n s2[v6] = 0;\n if (v2 <= 0) {\n LABEL_28:\n v18 = v2++;\n *(uint32_t *)(__strcpy_chk(&words_1[56 * v18], s2, 50LL) + 52) = 1;\n v6 = 0;\n goto LABEL_6;\n }\n v8 = words_1;\n v9 = 0;\n while (1) {\n v6 = strcmp(v8, s2);\n if (!v6) break;\n ++v9;\n v8 += 56;\n if (v9 == v2) goto LABEL_28;\n }\n ++v3;\n ++*(uint32_t *)&words_1[56 * v9 + 52];\n v4 = *v3;\n } while (*v3);\n LABEL_14:\n if (v6 > 0) {\n s2[v6] = 0;\n if (v2 <= 0) {\n LABEL_29:\n v19 = v2++;\n *(uint32_t *)(__strcpy_chk(&words_1[56 * v19], s2, 50LL) + 52) = 1;\n } else {\n v15 = words_1;\n v16 = 0;\n for (i = strcmp(words_1, s2); i; i = strcmp(v15, s2)) {\n ++v16;\n v15 += 56;\n if (v2 == v16) goto LABEL_29;\n }\n ++*(uint32_t *)&words_1[56 * v16 + 52];\n }\n }\n LABEL_15:\n ++v20;\n } while (&a2[a1] != v20);\n if (v2 <= 0) return words_1;\n v10 = (int *)&unk_4074;\n v11 = 0;\n v12 = 0LL;\n v13 = 0;\n do {\n if (*v10 > v13) {\n v12 = v11;\n v13 = *v10;\n }\n ++v11;\n v10 += 14;\n } while (v2 != v11);\n return &words_1[56 * v12];\n}" + }, + { + "index": 327, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int x, int y, int z) {\n if (x == y || y == z || z == x) {\n return true;\n } else {\n return false;\n }\n}", + "test": "int main() {\n\n assert(func0(6, 8, 12) == false);\n\n assert(func0(6, 6, 12) == true);\n\n assert(func0(6, 16, 20) == false);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov %esi,-0x8(%rbp)\nmov %edx,-0xc(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x8(%rbp),%eax\nje 1172 \nmov -0x8(%rbp),%eax\ncmp -0xc(%rbp),%eax\nje 1172 \nmov -0xc(%rbp),%eax\ncmp -0x4(%rbp),%eax\njne 1179 \nmov $0x1,%eax\njmp 117e \nmov $0x0,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov [rbp+var_C], edx\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_8]\njz short loc_1172\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_C]\njz short loc_1172\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_4]\njnz short loc_1179\nloc_1172:\nmov eax, 1\njmp short loc_117E\nloc_1179:\nmov eax, 0\nloc_117E:\npop rbp\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(int a1, int a2, int a3)\n{\n return a1 == a2 || a2 == a3 || a3 == a1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov [rbp+var_C], edx\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_8]\njz short loc_1172\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_C]\njz short loc_1172\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_4]\njnz short loc_1179\nloc_1172:\nmov eax, 1\njmp short loc_117E\nloc_1179:\nmov eax, 0\nloc_117E:\npop rbp\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1149(int a1, int a2, int a3)\n{\n return a1 == a2 || a2 == a3 || a3 == a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1149(int a1, int a2, int a3) {\n return a1 == a2 || a2 == a3 || a3 == a1;\n}", + "ida_pseudo_norm": "uint8_t func0(int a1, int a2, int a3) {\n return a1 == a2 || a2 == a3 || a3 == a1;\n}" + }, + { + "index": 328, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int list1[], int result[], int m, int n, int size) {\n int index = 0;\n for (int i = m; i < size; i++, index++) {\n result[index] = list1[i];\n }\n for (int i = 0; i < n; i++, index++) {\n result[index] = list1[i];\n }\n}", + "test": "int main() {\n\n int arr1[10] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n int result1[10];\n\n func0(arr1, result1, 3, 4, 10);\n\n int expected1[10] = {4, 5, 6, 7, 8, 9, 10, 1, 2, 3};\n\n for (int i = 0; i < 10; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n\n\n int result2[10];\n\n func0(arr1, result2, 2, 2, 10);\n\n int expected2[10] = {3, 4, 5, 6, 7, 8, 9, 10, 1, 2};\n\n for (int i = 0; i < 10; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n\n\n int result3[7];\n\n func0(arr1, result3, 5, 2, 10);\n\n int expected3[7] = {6, 7, 8, 9, 10, 1, 2};\n\n for (int i = 0; i < 7; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n\n\n printf(\"All test cases passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %edx,-0x24(%rbp)\nmov %ecx,-0x28(%rbp)\nmov %r8d,-0x2c(%rbp)\nmovl $0x0,-0xc(%rbp)\nmov -0x24(%rbp),%eax\nmov %eax,-0x8(%rbp)\njmp 11e7 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0xc(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x20(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x8(%rbp)\naddl $0x1,-0xc(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 11b2 \nmovl $0x0,-0x4(%rbp)\njmp 122d \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0xc(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x20(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x4(%rbp)\naddl $0x1,-0xc(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x28(%rbp),%eax\njl 11f8 \npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_28], ecx\nmov [rbp+var_2C], r8d\nmov [rbp+var_C], 0\nmov eax, [rbp+var_24]\nmov [rbp+var_8], eax\njmp short loc_11E7\nloc_11B2:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_20]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_8], 1\nadd [rbp+var_C], 1\nloc_11E7:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_2C]\njl short loc_11B2\nmov [rbp+var_4], 0\njmp short loc_122D\nloc_11F8:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_20]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_4], 1\nadd [rbp+var_C], 1\nloc_122D:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_28]\njl short loc_11F8\nnop\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3, int a4, int a5)\n{\n __int64 result; // rax\n int v6; // [rsp+20h] [rbp-Ch]\n unsigned int i; // [rsp+28h] [rbp-4h]\n\n v6 = 0;\n while ( a3 < a5 )\n *(_DWORD *)(4LL * v6++ + a2) = *(_DWORD *)(4LL * a3++ + a1);\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a4 )\n break;\n *(_DWORD *)(4LL * v6++ + a2) = *(_DWORD *)(4LL * (int)i + a1);\n }\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_28], ecx\nmov [rbp+var_2C], r8d\nmov [rbp+var_C], 0\nmov eax, [rbp+var_24]\nmov [rbp+var_8], eax\njmp short loc_11E7\nloc_11B2:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_20]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_8], 1\nadd [rbp+var_C], 1\nloc_11E7:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_2C]\njl short loc_11B2\nmov [rbp+var_4], 0\njmp short loc_122D\nloc_11F8:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_20]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_4], 1\nadd [rbp+var_C], 1\nloc_122D:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_28]\njl short loc_11F8\nnop\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, __int64 a2, int a3, int a4, int a5)\n{\n __int64 result; // rax\n int v6; // [rsp+20h] [rbp-Ch]\n unsigned int i; // [rsp+28h] [rbp-4h]\n\n v6 = 0;\n while ( a3 < a5 )\n *(_DWORD *)(4LL * v6++ + a2) = *(_DWORD *)(4LL * a3++ + a1);\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a4 )\n break;\n *(_DWORD *)(4LL * v6++ + a2) = *(_DWORD *)(4LL * (int)i + a1);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, long long a2, int a3, int a4, int a5) {\n long long result;\n int v6;\n unsigned int i;\n v6 = 0;\n while (a3 < a5)\n *(uint32_t *)(4LL * v6++ + a2) = *(uint32_t *)(4LL * a3++ + a1);\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a4) break;\n *(uint32_t *)(4LL * v6++ + a2) = *(uint32_t *)(4LL * (int)i + a1);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3, int a4, int a5) {\n long long result;\n int v6;\n unsigned int i;\n v6 = 0;\n while (a3 < a5)\n *(uint32_t *)(4LL * v6++ + a2) = *(uint32_t *)(4LL * a3++ + a1);\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a4) break;\n *(uint32_t *)(4LL * v6++ + a2) = *(uint32_t *)(4LL * (int)i + a1);\n }\n return result;\n}" + }, + { + "index": 328, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int list1[], int result[], int m, int n, int size) {\n int index = 0;\n for (int i = m; i < size; i++, index++) {\n result[index] = list1[i];\n }\n for (int i = 0; i < n; i++, index++) {\n result[index] = list1[i];\n }\n}", + "test": "int main() {\n\n int arr1[10] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n int result1[10];\n\n func0(arr1, result1, 3, 4, 10);\n\n int expected1[10] = {4, 5, 6, 7, 8, 9, 10, 1, 2, 3};\n\n for (int i = 0; i < 10; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n\n\n int result2[10];\n\n func0(arr1, result2, 2, 2, 10);\n\n int expected2[10] = {3, 4, 5, 6, 7, 8, 9, 10, 1, 2};\n\n for (int i = 0; i < 10; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n\n\n int result3[7];\n\n func0(arr1, result3, 5, 2, 10);\n\n int expected3[7] = {6, 7, 8, 9, 10, 1, 2};\n\n for (int i = 0; i < 7; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n\n\n printf(\"All test cases passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ncmp %r8d,%edx\njge 11da \nmovslq %edx,%rax\nmov %rax,%r9\nneg %r9\nlea (%rsi,%r9,4),%r10\nmov (%rdi,%rax,4),%r9d\nmov %r9d,(%r10,%rax,4)\nadd $0x1,%rax\ncmp %eax,%r8d\njg 119f \nsub %edx,%r8d\ntest %ecx,%ecx\njle 11d9 \nlea -0x1(%rcx),%r9d\nmovslq %r8d,%r8\nlea (%rsi,%r8,4),%rcx\nmov $0x0,%eax\nmov (%rdi,%rax,4),%edx\nmov %edx,(%rcx,%rax,4)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %r9,%rdx\njne 11c7 \nretq\nmov $0x0,%r8d\njmp 11b3 \n", + "ida_asm": "func0:\nendbr64\ncmp edx, r8d\njge short loc_11DF\nsub r8d, edx\nmov r9d, r8d\nshl r9, 2\nmovsxd rdx, edx\nlea r10, [rdi+rdx*4]\nmov eax, 0\nloc_11A8:\nmov edx, [r10+rax]\nmov [rsi+rax], edx\nadd rax, 4\ncmp rax, r9\njnz short loc_11A8\nloc_11B8:\ntest ecx, ecx\njle short locret_11DE\nmovsxd rcx, ecx\nshl rcx, 2\nmovsxd r8, r8d\nlea rsi, [rsi+r8*4]\nmov eax, 0\nloc_11CF:\nmov edx, [rdi+rax]\nmov [rsi+rax], edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_11CF\nlocret_11DE:\nretn\nloc_11DF:\nmov r8d, 0\njmp short loc_11B8", + "ida_pseudo": "void __fastcall func0(__int64 a1, __int64 a2, int a3, int a4, int a5)\n{\n unsigned int v5; // r8d\n __int64 v6; // rax\n __int64 v7; // rcx\n __int64 v8; // rsi\n __int64 v9; // rax\n\n if ( a3 >= a5 )\n {\n v5 = 0;\n }\n else\n {\n v5 = a5 - a3;\n v6 = 0LL;\n do\n {\n *(_DWORD *)(a2 + v6) = *(_DWORD *)(a1 + 4LL * a3 + v6);\n v6 += 4LL;\n }\n while ( v6 != 4LL * v5 );\n }\n if ( a4 > 0 )\n {\n v7 = 4LL * a4;\n v8 = a2 + 4LL * (int)v5;\n v9 = 0LL;\n do\n {\n *(_DWORD *)(v8 + v9) = *(_DWORD *)(a1 + v9);\n v9 += 4LL;\n }\n while ( v9 != v7 );\n }\n}", + "ida_strip_asm": "sub_1189:\nendbr64\ncmp edx, r8d\njge short loc_11DF\nsub r8d, edx\nmov r9d, r8d\nshl r9, 2\nmovsxd rdx, edx\nlea r10, [rdi+rdx*4]\nmov eax, 0\nloc_11A8:\nmov edx, [r10+rax]\nmov [rsi+rax], edx\nadd rax, 4\ncmp rax, r9\njnz short loc_11A8\nloc_11B8:\ntest ecx, ecx\njle short locret_11DE\nmovsxd rcx, ecx\nshl rcx, 2\nmovsxd r8, r8d\nlea rsi, [rsi+r8*4]\nmov eax, 0\nloc_11CF:\nmov edx, [rdi+rax]\nmov [rsi+rax], edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_11CF\nlocret_11DE:\nretn\nloc_11DF:\nmov r8d, 0\njmp short loc_11B8", + "ida_strip_pseudo": "void __fastcall sub_1189(__int64 a1, __int64 a2, int a3, int a4, int a5)\n{\n unsigned int v5; // r8d\n __int64 v6; // rax\n __int64 v7; // rcx\n __int64 v8; // rsi\n __int64 v9; // rax\n\n if ( a3 >= a5 )\n {\n v5 = 0;\n }\n else\n {\n v5 = a5 - a3;\n v6 = 0LL;\n do\n {\n *(_DWORD *)(a2 + v6) = *(_DWORD *)(a1 + 4LL * a3 + v6);\n v6 += 4LL;\n }\n while ( v6 != 4LL * v5 );\n }\n if ( a4 > 0 )\n {\n v7 = 4LL * a4;\n v8 = a2 + 4LL * (int)v5;\n v9 = 0LL;\n do\n {\n *(_DWORD *)(v8 + v9) = *(_DWORD *)(a1 + v9);\n v9 += 4LL;\n }\n while ( v9 != v7 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1189(long long a1, long long a2, int a3, int a4, int a5) {\n unsigned int v5;\n long long v6;\n long long v7;\n long long v8;\n long long v9;\n if (a3 >= a5) {\n v5 = 0;\n } else {\n v5 = a5 - a3;\n v6 = 0LL;\n do {\n *(uint32_t *)(a2 + v6) = *(uint32_t *)(a1 + 4LL * a3 + v6);\n v6 += 4LL;\n } while (v6 != 4LL * v5);\n }\n if (a4 > 0) {\n v7 = 4LL * a4;\n v8 = a2 + 4LL * (int)v5;\n v9 = 0LL;\n do {\n *(uint32_t *)(v8 + v9) = *(uint32_t *)(a1 + v9);\n v9 += 4LL;\n } while (v9 != v7);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, long long a2, int a3, int a4, int a5) {\n unsigned int v5;\n long long v6;\n long long v7;\n long long v8;\n long long v9;\n if (a3 >= a5) {\n v5 = 0;\n } else {\n v5 = a5 - a3;\n v6 = 0LL;\n do {\n *(uint32_t *)(a2 + v6) = *(uint32_t *)(a1 + 4LL * a3 + v6);\n v6 += 4LL;\n } while (v6 != 4LL * v5);\n }\n if (a4 > 0) {\n v7 = 4LL * a4;\n v8 = a2 + 4LL * (int)v5;\n v9 = 0LL;\n do {\n *(uint32_t *)(v8 + v9) = *(uint32_t *)(a1 + v9);\n v9 += 4LL;\n } while (v9 != v7);\n }\n}" + }, + { + "index": 328, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int list1[], int result[], int m, int n, int size) {\n int index = 0;\n for (int i = m; i < size; i++, index++) {\n result[index] = list1[i];\n }\n for (int i = 0; i < n; i++, index++) {\n result[index] = list1[i];\n }\n}", + "test": "int main() {\n\n int arr1[10] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n int result1[10];\n\n func0(arr1, result1, 3, 4, 10);\n\n int expected1[10] = {4, 5, 6, 7, 8, 9, 10, 1, 2, 3};\n\n for (int i = 0; i < 10; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n\n\n int result2[10];\n\n func0(arr1, result2, 2, 2, 10);\n\n int expected2[10] = {3, 4, 5, 6, 7, 8, 9, 10, 1, 2};\n\n for (int i = 0; i < 10; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n\n\n int result3[7];\n\n func0(arr1, result3, 5, 2, 10);\n\n int expected3[7] = {6, 7, 8, 9, 10, 1, 2};\n\n for (int i = 0; i < 7; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n\n\n printf(\"All test cases passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ncmp %r8d,%edx\njge 14b0 \nmovslq %edx,%rax\nmov %rax,%r9\nneg %r9\nlea (%rsi,%r9,4),%r10\nnopw %cs:0x0(%rax,%rax,1)\nmov (%rdi,%rax,4),%r9d\nmov %r9d,(%r10,%rax,4)\nadd $0x1,%rax\ncmp %eax,%r8d\njg 1470 \nsub %edx,%r8d\ntest %ecx,%ecx\njle 14aa \nmovslq %r8d,%r8\nlea -0x1(%rcx),%r9d\nxor %eax,%eax\nlea (%rsi,%r8,4),%rcx\nnopl (%rax)\nmov (%rdi,%rax,4),%edx\nmov %edx,(%rcx,%rax,4)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rdx,%r9\njne 1498 \nretq\nnopl 0x0(%rax,%rax,1)\nxor %r8d,%r8d\njmp 1484 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ncmp edx, r8d\njge short loc_1400\nsub r8d, edx\nmovsxd rdx, edx\nxor eax, eax\nmov r9d, r8d\nlea r10, [rdi+rdx*4]\nshl r9, 2\nnop dword ptr [rax+00h]\nloc_13C0:\nmov edx, [r10+rax]\nmov [rsi+rax], edx\nadd rax, 4\ncmp rax, r9\njnz short loc_13C0\nloc_13D0:\ntest ecx, ecx\njle short locret_13F7\nmovsxd rcx, ecx\nmovsxd r8, r8d\nxor eax, eax\nshl rcx, 2\nlea rsi, [rsi+r8*4]\nnop dword ptr [rax+00h]\nloc_13E8:\nmov edx, [rdi+rax]\nmov [rsi+rax], edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_13E8\nlocret_13F7:\nretn\nloc_1400:\nxor r8d, r8d\njmp short loc_13D0", + "ida_pseudo": "void __fastcall func0(__int64 a1, __int64 a2, int a3, int a4, int a5)\n{\n unsigned int v5; // r8d\n __int64 v6; // rax\n __int64 v7; // rax\n __int64 v8; // rcx\n __int64 v9; // rsi\n\n if ( a3 >= a5 )\n {\n v5 = 0;\n }\n else\n {\n v5 = a5 - a3;\n v6 = 0LL;\n do\n {\n *(_DWORD *)(a2 + v6) = *(_DWORD *)(a1 + 4LL * a3 + v6);\n v6 += 4LL;\n }\n while ( v6 != 4LL * v5 );\n }\n if ( a4 > 0 )\n {\n v7 = 0LL;\n v8 = 4LL * a4;\n v9 = a2 + 4LL * (int)v5;\n do\n {\n *(_DWORD *)(v9 + v7) = *(_DWORD *)(a1 + v7);\n v7 += 4LL;\n }\n while ( v7 != v8 );\n }\n}", + "ida_strip_asm": "sub_13A0:\nendbr64\ncmp edx, r8d\njge short loc_1400\nsub r8d, edx\nmovsxd rdx, edx\nxor eax, eax\nmov r9d, r8d\nlea r10, [rdi+rdx*4]\nshl r9, 2\nnop dword ptr [rax+00h]\nloc_13C0:\nmov edx, [r10+rax]\nmov [rsi+rax], edx\nadd rax, 4\ncmp rax, r9\njnz short loc_13C0\nloc_13D0:\ntest ecx, ecx\njle short locret_13F7\nmovsxd rcx, ecx\nmovsxd r8, r8d\nxor eax, eax\nshl rcx, 2\nlea rsi, [rsi+r8*4]\nnop dword ptr [rax+00h]\nloc_13E8:\nmov edx, [rdi+rax]\nmov [rsi+rax], edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_13E8\nlocret_13F7:\nretn\nloc_1400:\nxor r8d, r8d\njmp short loc_13D0", + "ida_strip_pseudo": "void __fastcall sub_13A0(__int64 a1, __int64 a2, int a3, int a4, int a5)\n{\n unsigned int v5; // r8d\n __int64 v6; // rax\n __int64 v7; // rax\n __int64 v8; // rcx\n __int64 v9; // rsi\n\n if ( a3 >= a5 )\n {\n v5 = 0;\n }\n else\n {\n v5 = a5 - a3;\n v6 = 0LL;\n do\n {\n *(_DWORD *)(a2 + v6) = *(_DWORD *)(a1 + 4LL * a3 + v6);\n v6 += 4LL;\n }\n while ( v6 != 4LL * v5 );\n }\n if ( a4 > 0 )\n {\n v7 = 0LL;\n v8 = 4LL * a4;\n v9 = a2 + 4LL * (int)v5;\n do\n {\n *(_DWORD *)(v9 + v7) = *(_DWORD *)(a1 + v7);\n v7 += 4LL;\n }\n while ( v7 != v8 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_13A0(long long a1, long long a2, int a3, int a4, int a5) {\n unsigned int v5;\n long long v6;\n long long v7;\n long long v8;\n long long v9;\n if (a3 >= a5) {\n v5 = 0;\n } else {\n v5 = a5 - a3;\n v6 = 0LL;\n do {\n *(uint32_t *)(a2 + v6) = *(uint32_t *)(a1 + 4LL * a3 + v6);\n v6 += 4LL;\n } while (v6 != 4LL * v5);\n }\n if (a4 > 0) {\n v7 = 0LL;\n v8 = 4LL * a4;\n v9 = a2 + 4LL * (int)v5;\n do {\n *(uint32_t *)(v9 + v7) = *(uint32_t *)(a1 + v7);\n v7 += 4LL;\n } while (v7 != v8);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, long long a2, int a3, int a4, int a5) {\n unsigned int v5;\n long long v6;\n long long v7;\n long long v8;\n long long v9;\n if (a3 >= a5) {\n v5 = 0;\n } else {\n v5 = a5 - a3;\n v6 = 0LL;\n do {\n *(uint32_t *)(a2 + v6) = *(uint32_t *)(a1 + 4LL * a3 + v6);\n v6 += 4LL;\n } while (v6 != 4LL * v5);\n }\n if (a4 > 0) {\n v7 = 0LL;\n v8 = 4LL * a4;\n v9 = a2 + 4LL * (int)v5;\n do {\n *(uint32_t *)(v9 + v7) = *(uint32_t *)(a1 + v7);\n v7 += 4LL;\n } while (v7 != v8);\n }\n}" + }, + { + "index": 329, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int list[], int list_size) {\n int neg_count = 0;\n for (int i = 0; i < list_size; i++) {\n if (list[i] <= 0) {\n neg_count += 1;\n }\n }\n return neg_count;\n}", + "test": "int main() {\n\n int list1[] = {-1, -2, 3, -4, -5};\n\n int list2[] = {1, 2, 3};\n\n int list3[] = {1, 2, -3, -10, 20};\n\n\n\n assert(func0(list1, 5) == 4);\n\n assert(func0(list2, 3) == 0);\n\n assert(func0(list3, 5) == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11aa \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ntest %eax,%eax\njg 11a6 \naddl $0x1,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1188 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11AA\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njg short loc_11A6\nadd [rbp+var_8], 1\nloc_11A6:\nadd [rbp+var_4], 1\nloc_11AA:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(int *)(4LL * i + a1) <= 0 )\n ++v3;\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11AA\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njg short loc_11A6\nadd [rbp+var_8], 1\nloc_11A6:\nadd [rbp+var_4], 1\nloc_11AA:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(int *)(4LL * i + a1) <= 0 )\n ++v3;\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(int *)(4LL * i + a1) <= 0) ++v3;\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(int *)(4LL * i + a1) <= 0) ++v3;\n }\n return v3;\n}" + }, + { + "index": 329, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int list[], int list_size) {\n int neg_count = 0;\n for (int i = 0; i < list_size; i++) {\n if (list[i] <= 0) {\n neg_count += 1;\n }\n }\n return neg_count;\n}", + "test": "int main() {\n\n int list1[] = {-1, -2, 3, -4, -5};\n\n int list2[] = {1, 2, 3};\n\n int list3[] = {1, 2, -3, -10, 20};\n\n\n\n assert(func0(list1, 5) == 4);\n\n assert(func0(list2, 3) == 0);\n\n assert(func0(list3, 5) == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1198 \nmov %rdi,%rax\nlea -0x1(%rsi),%edx\nlea 0x4(%rdi,%rdx,4),%rsi\nmov $0x0,%edx\ncmpl $0x0,(%rax)\nsetle %cl\nmovzbl %cl,%ecx\nadd %ecx,%edx\nadd $0x4,%rax\ncmp %rsi,%rax\njne 1181 \nmov %edx,%eax\nretq\nmov $0x0,%edx\njmp 1195 \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1197\nmov rax, rdi\nmovsxd rsi, esi\nlea rsi, [rdi+rsi*4]\nmov edx, 0\nloc_1180:\ncmp dword ptr [rax], 0\nsetle cl\nmovzx ecx, cl\nadd edx, ecx\nadd rax, 4\ncmp rax, rsi\njnz short loc_1180\nloc_1194:\nmov eax, edx\nretn\nloc_1197:\nmov edx, 0\njmp short loc_1194", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n _DWORD *v3; // rsi\n unsigned int v4; // edx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n v4 += *v2++ <= 0;\n while ( v2 != v3 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_1197\nmov rax, rdi\nmovsxd rsi, esi\nlea rsi, [rdi+rsi*4]\nmov edx, 0\nloc_1180:\ncmp dword ptr [rax], 0\nsetle cl\nmovzx ecx, cl\nadd edx, ecx\nadd rax, 4\ncmp rax, rsi\njnz short loc_1180\nloc_1194:\nmov eax, edx\nretn\nloc_1197:\nmov edx, 0\njmp short loc_1194", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n _DWORD *v3; // rsi\n unsigned int v4; // edx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n v4 += *v2++ <= 0;\n while ( v2 != v3 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2) {\n uint32_t *v2;\n uint32_t *v3;\n unsigned int v4;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n v4 += *v2++ <= 0;\n while (v2 != v3);\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n uint32_t *v3;\n unsigned int v4;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n v4 += *v2++ <= 0;\n while (v2 != v3);\n }\n return v4;\n}" + }, + { + "index": 330, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(const char* text, char output[][6], int* count) {\n regex_t regex;\n regmatch_t pmatch[1];\n const char* pattern = \"\\\\b\\\\w{3,5}\\\\b\";\n regcomp(®ex, pattern, REG_EXTENDED);\n const char* current = text;\n *count = 0;\n while (regexec(®ex, current, 1, pmatch, 0) == 0) {\n int start = pmatch[0].rm_so;\n int end = pmatch[0].rm_eo;\n int length = end - start;\n strncpy(output[*count], current + start, length);\n output[*count][length] = '\\0';\n (*count)++;\n current += end;\n }\n regfree(®ex);\n}", + "test": "int main() {\n\n char words1[5][6];\n\n int count1 = 0;\n\n func0(\"For the four consumer complaints contact manager AKR reddy\", words1, &count1);\n\n assert(count1 == 5 && strcmp(words1[0], \"For\") == 0 && strcmp(words1[1], \"the\") == 0 && strcmp(words1[2], \"four\") == 0 && strcmp(words1[3], \"AKR\") == 0 && strcmp(words1[4], \"reddy\") == 0);\n\n \n\n char words2[2][6];\n\n int count2 = 0;\n\n func0(\"Certain service are subject to change MSR\", words2, &count2);\n\n assert(count2 == 2 && strcmp(words2[0], \"are\") == 0 && strcmp(words2[1], \"MSR\") == 0);\n\n\n\n char words3[3][6];\n\n int count3 = 0;\n\n func0(\"Third party legal desclaimers\", words3, &count3);\n\n assert(count3 == 3 && strcmp(words3[0], \"Third\") == 0 && strcmp(words3[1], \"party\") == 0 && strcmp(words3[2], \"legal\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x90,%rsp\nmov %rdi,-0x78(%rbp)\nmov %rsi,-0x80(%rbp)\nmov %rdx,-0x88(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0xdcb(%rip),%rax\nmov %rax,-0x58(%rbp)\nmov -0x58(%rbp),%rcx\nlea -0x50(%rbp),%rax\nmov $0x1,%edx\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 10f0 \nmov -0x78(%rbp),%rax\nmov %rax,-0x60(%rbp)\nmov -0x88(%rbp),%rax\nmovl $0x0,(%rax)\njmpq 1312 \nmov -0x10(%rbp),%eax\nmov %eax,-0x6c(%rbp)\nmov -0xc(%rbp),%eax\nmov %eax,-0x68(%rbp)\nmov -0x68(%rbp),%eax\nsub -0x6c(%rbp),%eax\nmov %eax,-0x64(%rbp)\nmov -0x64(%rbp),%eax\nmovslq %eax,%rcx\nmov -0x6c(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x60(%rbp),%rax\nlea (%rdx,%rax,1),%rsi\nmov -0x88(%rbp),%rax\nmov (%rax),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nadd %rax,%rax\nmov %rax,%rdx\nmov -0x80(%rbp),%rax\nadd %rdx,%rax\nmov %rcx,%rdx\nmov %rax,%rdi\ncallq 10b0 \nmov -0x88(%rbp),%rax\nmov (%rax),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nadd %rax,%rax\nmov %rax,%rdx\nmov -0x80(%rbp),%rax\nadd %rax,%rdx\nmov -0x64(%rbp),%eax\ncltq\nmovb $0x0,(%rdx,%rax,1)\nmov -0x88(%rbp),%rax\nmov (%rax),%eax\nlea 0x1(%rax),%edx\nmov -0x88(%rbp),%rax\nmov %edx,(%rax)\nmov -0x68(%rbp),%eax\ncltq\nadd %rax,-0x60(%rbp)\nlea -0x10(%rbp),%rdx\nmov -0x60(%rbp),%rsi\nlea -0x50(%rbp),%rax\nmov $0x0,%r8d\nmov %rdx,%rcx\nmov $0x1,%edx\nmov %rax,%rdi\ncallq 1110 \ntest %eax,%eax\nje 1273 \nlea -0x50(%rbp),%rax\nmov %rax,%rdi\ncallq 10c0 \nmov -0x8(%rbp),%rax\nxor %fs:0x28,%rax\nje 135d \ncallq 10d0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 90h\nmov [rbp+var_78], rdi\nmov [rbp+var_80], rsi\nmov [rbp+var_88], rdx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aBW35B; \"\\\\b\\\\w{3,5}\\\\b\"\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov rax, [rbp+var_78]\nmov [rbp+string], rax\nmov rax, [rbp+var_88]\nmov dword ptr [rax], 0\njmp loc_1312\nloc_1273:\nmov eax, [rbp+pmatch.rm_so]\nmov [rbp+var_6C], eax\nmov eax, [rbp+pmatch.rm_eo]\nmov [rbp+var_68], eax\nmov eax, [rbp+var_68]\nsub eax, [rbp+var_6C]\nmov [rbp+var_64], eax\nmov eax, [rbp+var_64]\nmovsxd rcx, eax\nmov eax, [rbp+var_6C]\nmovsxd rdx, eax\nmov rax, [rbp+string]\nlea rsi, [rdx+rax]; src\nmov rax, [rbp+var_88]\nmov eax, [rax]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nadd rax, rax\nmov rdx, rax\nmov rax, [rbp+var_80]\nadd rax, rdx\nmov rdx, rcx; n\nmov rdi, rax; dest\ncall _strncpy\nmov rax, [rbp+var_88]\nmov eax, [rax]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nadd rax, rax\nmov rdx, rax\nmov rax, [rbp+var_80]\nadd rdx, rax\nmov eax, [rbp+var_64]\ncdqe\nmov byte ptr [rdx+rax], 0\nmov rax, [rbp+var_88]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_88]\nmov [rax], edx\nmov eax, [rbp+var_68]\ncdqe\nadd [rbp+string], rax\nloc_1312:\nlea rdx, [rbp+pmatch]\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov rcx, rdx; pmatch\nmov edx, 1; nmatch\nmov rdi, rax; preg\ncall _regexec\ntest eax, eax\njz loc_1273\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nnop\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njz short locret_135D\ncall ___stack_chk_fail\nlocret_135D:\nleave\nretn", + "ida_pseudo": "unsigned __int64 __fastcall func0(const char *a1, __int64 a2, int *a3)\n{\n int i; // eax\n regoff_t rm_eo; // [rsp+28h] [rbp-68h]\n int v7; // [rsp+2Ch] [rbp-64h]\n char *string; // [rsp+30h] [rbp-60h]\n regex_t preg; // [rsp+40h] [rbp-50h] BYREF\n regmatch_t pmatch; // [rsp+80h] [rbp-10h] BYREF\n unsigned __int64 v11; // [rsp+88h] [rbp-8h]\n\n v11 = __readfsqword(0x28u);\n regcomp(&preg, \"\\\\b\\\\w{3,5}\\\\b\", 1);\n string = (char *)a1;\n *a3 = 0;\n for ( i = regexec(&preg, a1, 1uLL, &pmatch, 0); !i; i = regexec(&preg, string, 1uLL, &pmatch, 0) )\n {\n rm_eo = pmatch.rm_eo;\n v7 = pmatch.rm_eo - pmatch.rm_so;\n strncpy((char *)(6LL * *a3 + a2), &string[pmatch.rm_so], pmatch.rm_eo - pmatch.rm_so);\n *(_BYTE *)(a2 + 6LL * (*a3)++ + v7) = 0;\n string += rm_eo;\n }\n regfree(&preg);\n return v11 - __readfsqword(0x28u);\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 90h\nmov [rbp+var_78], rdi\nmov [rbp+var_80], rsi\nmov [rbp+var_88], rdx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aBW35B; \"\\\\b\\\\w{3,5}\\\\b\"\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov rax, [rbp+var_78]\nmov [rbp+string], rax\nmov rax, [rbp+var_88]\nmov dword ptr [rax], 0\njmp loc_1312\nloc_1273:\nmov eax, [rbp+pmatch.rm_so]\nmov [rbp+var_6C], eax\nmov eax, [rbp+pmatch.rm_eo]\nmov [rbp+var_68], eax\nmov eax, [rbp+var_68]\nsub eax, [rbp+var_6C]\nmov [rbp+var_64], eax\nmov eax, [rbp+var_64]\nmovsxd rcx, eax\nmov eax, [rbp+var_6C]\nmovsxd rdx, eax\nmov rax, [rbp+string]\nlea rsi, [rdx+rax]; src\nmov rax, [rbp+var_88]\nmov eax, [rax]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nadd rax, rax\nmov rdx, rax\nmov rax, [rbp+var_80]\nadd rax, rdx\nmov rdx, rcx; n\nmov rdi, rax; dest\ncall _strncpy\nmov rax, [rbp+var_88]\nmov eax, [rax]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nadd rax, rax\nmov rdx, rax\nmov rax, [rbp+var_80]\nadd rdx, rax\nmov eax, [rbp+var_64]\ncdqe\nmov byte ptr [rdx+rax], 0\nmov rax, [rbp+var_88]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_88]\nmov [rax], edx\nmov eax, [rbp+var_68]\ncdqe\nadd [rbp+string], rax\nloc_1312:\nlea rdx, [rbp+pmatch]\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov rcx, rdx; pmatch\nmov edx, 1; nmatch\nmov rdi, rax; preg\ncall _regexec\ntest eax, eax\njz loc_1273\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nnop\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njz short locret_135D\ncall ___stack_chk_fail\nlocret_135D:\nleave\nretn", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_1209(const char *a1, __int64 a2, int *a3)\n{\n int i; // eax\n regoff_t rm_eo; // [rsp+28h] [rbp-68h]\n int v7; // [rsp+2Ch] [rbp-64h]\n char *string; // [rsp+30h] [rbp-60h]\n regex_t preg; // [rsp+40h] [rbp-50h] BYREF\n regmatch_t pmatch; // [rsp+80h] [rbp-10h] BYREF\n unsigned __int64 v11; // [rsp+88h] [rbp-8h]\n\n v11 = __readfsqword(0x28u);\n regcomp(&preg, \"\\\\b\\\\w{3,5}\\\\b\", 1);\n string = (char *)a1;\n *a3 = 0;\n for ( i = regexec(&preg, a1, 1uLL, &pmatch, 0); !i; i = regexec(&preg, string, 1uLL, &pmatch, 0) )\n {\n rm_eo = pmatch.rm_eo;\n v7 = pmatch.rm_eo - pmatch.rm_so;\n strncpy((char *)(6LL * *a3 + a2), &string[pmatch.rm_so], pmatch.rm_eo - pmatch.rm_so);\n *(_BYTE *)(a2 + 6LL * (*a3)++ + v7) = 0;\n string += rm_eo;\n }\n regfree(&preg);\n return v11 - __readfsqword(0x28u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_1209(const char *a1, long long a2, int *a3) {\n int i;\n regoff_t rm_eo;\n int v7;\n char *string;\n regex_t preg;\n regmatch_t pmatch;\n unsigned long long v11;\n v11 = __readfsqword(40u);\n regcomp(&preg, \"\\\\b\\\\w{3,5}\\\\b\", 1);\n string = (char *)a1;\n *a3 = 0;\n for (i = regexec(&preg, a1, 1uLL, &pmatch, 0); !i;\n i = regexec(&preg, string, 1uLL, &pmatch, 0)) {\n rm_eo = pmatch.rm_eo;\n v7 = pmatch.rm_eo - pmatch.rm_so;\n strncpy((char *)(6LL * *a3 + a2), &string[pmatch.rm_so],\n pmatch.rm_eo - pmatch.rm_so);\n *(uint8_t *)(a2 + 6LL * (*a3)++ + v7) = 0;\n string += rm_eo;\n }\n regfree(&preg);\n return v11 - __readfsqword(40u);\n}", + "ida_pseudo_norm": "unsigned long long func0(const char *a1, long long a2, int *a3) {\n int i;\n regoff_t rm_eo;\n int v7;\n char *string;\n regex_t preg;\n regmatch_t pmatch;\n unsigned long long v11;\n v11 = __readfsqword(40u);\n regcomp(&preg, \"\\\\b\\\\w{3,5}\\\\b\", 1);\n string = (char *)a1;\n *a3 = 0;\n for (i = regexec(&preg, a1, 1uLL, &pmatch, 0); !i;\n i = regexec(&preg, string, 1uLL, &pmatch, 0)) {\n rm_eo = pmatch.rm_eo;\n v7 = pmatch.rm_eo - pmatch.rm_so;\n strncpy((char *)(6LL * *a3 + a2), &string[pmatch.rm_so],\n pmatch.rm_eo - pmatch.rm_so);\n *(uint8_t *)(a2 + 6LL * (*a3)++ + v7) = 0;\n string += rm_eo;\n }\n regfree(&preg);\n return v11 - __readfsqword(40u);\n}" + }, + { + "index": 330, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(const char* text, char output[][6], int* count) {\n regex_t regex;\n regmatch_t pmatch[1];\n const char* pattern = \"\\\\b\\\\w{3,5}\\\\b\";\n regcomp(®ex, pattern, REG_EXTENDED);\n const char* current = text;\n *count = 0;\n while (regexec(®ex, current, 1, pmatch, 0) == 0) {\n int start = pmatch[0].rm_so;\n int end = pmatch[0].rm_eo;\n int length = end - start;\n strncpy(output[*count], current + start, length);\n output[*count][length] = '\\0';\n (*count)++;\n current += end;\n }\n regfree(®ex);\n}", + "test": "int main() {\n\n char words1[5][6];\n\n int count1 = 0;\n\n func0(\"For the four consumer complaints contact manager AKR reddy\", words1, &count1);\n\n assert(count1 == 5 && strcmp(words1[0], \"For\") == 0 && strcmp(words1[1], \"the\") == 0 && strcmp(words1[2], \"four\") == 0 && strcmp(words1[3], \"AKR\") == 0 && strcmp(words1[4], \"reddy\") == 0);\n\n \n\n char words2[2][6];\n\n int count2 = 0;\n\n func0(\"Certain service are subject to change MSR\", words2, &count2);\n\n assert(count2 == 2 && strcmp(words2[0], \"are\") == 0 && strcmp(words2[1], \"MSR\") == 0);\n\n\n\n char words3[3][6];\n\n int count3 = 0;\n\n func0(\"Third party legal desclaimers\", words3, &count3);\n\n assert(count3 == 3 && strcmp(words3[0], \"Third\") == 0 && strcmp(words3[1], \"party\") == 0 && strcmp(words3[2], \"legal\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x58,%rsp\nmov %rdi,%r13\nmov %rsi,%r14\nmov %rdx,%r12\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nmov $0x1,%edx\nlea 0xde1(%rip),%rsi\ncallq 10e0 \nmovl $0x0,(%r12)\nlea 0x40(%rsp),%r15\nmov %rsp,%rdi\nmov $0x0,%r8d\nmov %r15,%rcx\nmov $0x1,%edx\nmov %r13,%rsi\ncallq 10f0 \ntest %eax,%eax\njne 1298 \nmov 0x40(%rsp),%esi\nmov 0x44(%rsp),%ebx\nmov %ebx,%ebp\nsub %esi,%ebp\nmovslq %ebp,%rbp\nmovslq %esi,%rsi\nadd %r13,%rsi\nmovslq (%r12),%rax\nlea (%rax,%rax,2),%rax\nlea (%r14,%rax,2),%rdi\nmov %rbp,%rdx\ncallq 10a0 \nmovslq (%r12),%rax\nlea (%rax,%rax,2),%rax\nlea (%r14,%rax,2),%rax\nmovb $0x0,(%rax,%rbp,1)\naddl $0x1,(%r12)\nmovslq %ebx,%rbx\nadd %rbx,%r13\njmp 1235 \nmov %rsp,%rdi\ncallq 10b0 \nmov 0x48(%rsp),%rax\nxor %fs:0x28,%rax\njne 12bf \nadd $0x58,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\ncallq 10c0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 58h\nmov r13, rdi\nmov r14, rsi\nmov r12, rdx\nmov rax, fs:28h\nmov [rsp+88h+var_40], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"\\\\b\\\\w{3,5}\\\\b\"\ncall _regcomp\nmov eax, 0\nlea r15, [rsp+88h+pmatch]\njmp short loc_129A\nloc_1254:\nmov esi, [rsp+88h+pmatch.rm_so]\nmov ebx, [rsp+88h+pmatch.rm_eo]\nmov ebp, ebx\nsub ebp, esi\nmovsxd rbp, ebp\nmovsxd rsi, esi\nadd rsi, r13; src\nmovsxd rax, dword ptr [r12]\nlea rax, [rax+rax*2]\nlea rdi, [r14+rax*2]; dest\nmov rdx, rbp; n\ncall _strncpy\nmovsxd rax, dword ptr [r12]\nlea rax, [rax+rax*2]\nlea rax, [r14+rax*2]\nmov byte ptr [rax+rbp], 0\nmov eax, [r12]\nadd eax, 1\nmovsxd rbx, ebx\nadd r13, rbx\nloc_129A:\nmov [r12], eax\nmov rdi, rsp; preg\nmov r8d, 0; eflags\nmov rcx, r15; pmatch\nmov edx, 1; nmatch\nmov rsi, r13; string\ncall _regexec\ntest eax, eax\njz short loc_1254\nmov rdi, rsp; preg\ncall _regfree\nmov rax, [rsp+88h+var_40]\nsub rax, fs:28h\njnz short loc_12E2\nadd rsp, 58h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_12E2:\ncall ___stack_chk_fail", + "ida_pseudo": "unsigned __int64 __fastcall func0(char *string, __int64 a2, int *a3)\n{\n int v5; // eax\n regoff_t rm_eo; // ebx\n size_t v7; // rbp\n regex_t v9; // [rsp+0h] [rbp-88h] BYREF\n regmatch_t pmatch; // [rsp+40h] [rbp-48h] BYREF\n unsigned __int64 v11; // [rsp+48h] [rbp-40h]\n\n v11 = __readfsqword(0x28u);\n regcomp(&v9, \"\\\\b\\\\w{3,5}\\\\b\", 1);\n v5 = 0;\n while ( 1 )\n {\n *a3 = v5;\n if ( regexec(&v9, string, 1uLL, &pmatch, 0) )\n break;\n rm_eo = pmatch.rm_eo;\n v7 = pmatch.rm_eo - pmatch.rm_so;\n strncpy((char *)(a2 + 6LL * *a3), &string[pmatch.rm_so], v7);\n *(_BYTE *)(a2 + 6LL * *a3 + v7) = 0;\n v5 = *a3 + 1;\n string += rm_eo;\n }\n regfree(&v9);\n return v11 - __readfsqword(0x28u);\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 58h\nmov r13, rdi\nmov r14, rsi\nmov r12, rdx\nmov rax, fs:28h\nmov [rsp+88h+var_40], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"\\\\b\\\\w{3,5}\\\\b\"\ncall _regcomp\nmov eax, 0\nlea r15, [rsp+88h+pmatch]\njmp short loc_129A\nloc_1254:\nmov esi, [rsp+88h+pmatch.rm_so]\nmov ebx, [rsp+88h+pmatch.rm_eo]\nmov ebp, ebx\nsub ebp, esi\nmovsxd rbp, ebp\nmovsxd rsi, esi\nadd rsi, r13; src\nmovsxd rax, dword ptr [r12]\nlea rax, [rax+rax*2]\nlea rdi, [r14+rax*2]; dest\nmov rdx, rbp; n\ncall _strncpy\nmovsxd rax, dword ptr [r12]\nlea rax, [rax+rax*2]\nlea rax, [r14+rax*2]\nmov byte ptr [rax+rbp], 0\nmov eax, [r12]\nadd eax, 1\nmovsxd rbx, ebx\nadd r13, rbx\nloc_129A:\nmov [r12], eax\nmov rdi, rsp; preg\nmov r8d, 0; eflags\nmov rcx, r15; pmatch\nmov edx, 1; nmatch\nmov rsi, r13; string\ncall _regexec\ntest eax, eax\njz short loc_1254\nmov rdi, rsp; preg\ncall _regfree\nmov rax, [rsp+88h+var_40]\nsub rax, fs:28h\njnz short loc_12E2\nadd rsp, 58h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_12E2:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_1209(char *string, __int64 a2, int *a3)\n{\n int v5; // eax\n regoff_t rm_eo; // ebx\n size_t v7; // rbp\n regex_t v9; // [rsp+0h] [rbp-88h] BYREF\n regmatch_t pmatch; // [rsp+40h] [rbp-48h] BYREF\n unsigned __int64 v11; // [rsp+48h] [rbp-40h]\n\n v11 = __readfsqword(0x28u);\n regcomp(&v9, \"\\\\b\\\\w{3,5}\\\\b\", 1);\n v5 = 0;\n while ( 1 )\n {\n *a3 = v5;\n if ( regexec(&v9, string, 1uLL, &pmatch, 0) )\n break;\n rm_eo = pmatch.rm_eo;\n v7 = pmatch.rm_eo - pmatch.rm_so;\n strncpy((char *)(a2 + 6LL * *a3), &string[pmatch.rm_so], v7);\n *(_BYTE *)(a2 + 6LL * *a3 + v7) = 0;\n v5 = *a3 + 1;\n string += rm_eo;\n }\n regfree(&v9);\n return v11 - __readfsqword(0x28u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_1209(char *string, long long a2, int *a3) {\n int v5;\n regoff_t rm_eo;\n unsigned int v7;\n regex_t v9;\n regmatch_t pmatch;\n unsigned long long v11;\n v11 = __readfsqword(40u);\n regcomp(&v9, \"\\\\b\\\\w{3,5}\\\\b\", 1);\n v5 = 0;\n while (1) {\n *a3 = v5;\n if (regexec(&v9, string, 1uLL, &pmatch, 0)) break;\n rm_eo = pmatch.rm_eo;\n v7 = pmatch.rm_eo - pmatch.rm_so;\n strncpy((char *)(a2 + 6LL * *a3), &string[pmatch.rm_so], v7);\n *(uint8_t *)(a2 + 6LL * *a3 + v7) = 0;\n v5 = *a3 + 1;\n string += rm_eo;\n }\n regfree(&v9);\n return v11 - __readfsqword(40u);\n}", + "ida_pseudo_norm": "unsigned long long func0(char *string, long long a2, int *a3) {\n int v5;\n regoff_t rm_eo;\n unsigned int v7;\n regex_t v9;\n regmatch_t pmatch;\n unsigned long long v11;\n v11 = __readfsqword(40u);\n regcomp(&v9, \"\\\\b\\\\w{3,5}\\\\b\", 1);\n v5 = 0;\n while (1) {\n *a3 = v5;\n if (regexec(&v9, string, 1uLL, &pmatch, 0)) break;\n rm_eo = pmatch.rm_eo;\n v7 = pmatch.rm_eo - pmatch.rm_so;\n strncpy((char *)(a2 + 6LL * *a3), &string[pmatch.rm_so], v7);\n *(uint8_t *)(a2 + 6LL * *a3 + v7) = 0;\n v5 = *a3 + 1;\n string += rm_eo;\n }\n regfree(&v9);\n return v11 - __readfsqword(40u);\n}" + }, + { + "index": 330, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(const char* text, char output[][6], int* count) {\n regex_t regex;\n regmatch_t pmatch[1];\n const char* pattern = \"\\\\b\\\\w{3,5}\\\\b\";\n regcomp(®ex, pattern, REG_EXTENDED);\n const char* current = text;\n *count = 0;\n while (regexec(®ex, current, 1, pmatch, 0) == 0) {\n int start = pmatch[0].rm_so;\n int end = pmatch[0].rm_eo;\n int length = end - start;\n strncpy(output[*count], current + start, length);\n output[*count][length] = '\\0';\n (*count)++;\n current += end;\n }\n regfree(®ex);\n}", + "test": "int main() {\n\n char words1[5][6];\n\n int count1 = 0;\n\n func0(\"For the four consumer complaints contact manager AKR reddy\", words1, &count1);\n\n assert(count1 == 5 && strcmp(words1[0], \"For\") == 0 && strcmp(words1[1], \"the\") == 0 && strcmp(words1[2], \"four\") == 0 && strcmp(words1[3], \"AKR\") == 0 && strcmp(words1[4], \"reddy\") == 0);\n\n \n\n char words2[2][6];\n\n int count2 = 0;\n\n func0(\"Certain service are subject to change MSR\", words2, &count2);\n\n assert(count2 == 2 && strcmp(words2[0], \"are\") == 0 && strcmp(words2[1], \"MSR\") == 0);\n\n\n\n char words3[3][6];\n\n int count3 = 0;\n\n func0(\"Third party legal desclaimers\", words3, &count3);\n\n assert(count3 == 3 && strcmp(words3[0], \"Third\") == 0 && strcmp(words3[1], \"party\") == 0 && strcmp(words3[2], \"legal\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmov %rdi,%r15\npush %r14\npush %r13\npush %r12\npush %rbp\nmov %rsi,%rbp\nlea 0xc4a(%rip),%rsi\npush %rbx\nmov %rdx,%rbx\nmov $0x1,%edx\nsub $0x68,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x58(%rsp)\nxor %eax,%eax\nlea 0x10(%rsp),%r12\nlea 0x50(%rsp),%r13\nmov %r12,%rdi\ncallq 10e0 \nmovl $0x0,(%rbx)\njmp 143e \nnopl 0x0(%rax)\nmovslq 0x54(%rsp),%r14\nmovslq 0x50(%rsp),%rsi\nmovslq (%rbx),%rax\nmov %r14d,%edx\nsub %esi,%edx\nlea (%rax,%rax,2),%rax\nadd %r15,%rsi\nadd %r14,%r15\nmovslq %edx,%rdx\nlea 0x0(%rbp,%rax,2),%rdi\nmov %rdx,0x8(%rsp)\ncallq 10a0 \nmovslq (%rbx),%rax\nmov 0x8(%rsp),%rdx\nlea (%rax,%rax,2),%rax\nlea 0x0(%rbp,%rax,2),%rax\nmovb $0x0,(%rax,%rdx,1)\naddl $0x1,(%rbx)\nxor %r8d,%r8d\nmov %r13,%rcx\nmov $0x1,%edx\nmov %r15,%rsi\nmov %r12,%rdi\ncallq 10f0 \ntest %eax,%eax\nje 13f8 \nmov %r12,%rdi\ncallq 10b0 \nmov 0x58(%rsp),%rax\nxor %fs:0x28,%rax\njne 147f \nadd $0x68,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\ncallq 10c0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov r15, rdx\nmov edx, 1; cflags\npush r14\npush r13\npush r12\npush rbp\nmov rbp, rsi\nlea rsi, pattern; \"\\\\b\\\\w{3,5}\\\\b\"\npush rbx\nmov rbx, rdi\nsub rsp, 68h\nmov rax, fs:28h\nmov [rsp+98h+var_40], rax\nxor eax, eax\nlea r12, [rsp+98h+preg]\nmov rdi, r12; preg\ncall _regcomp\nlea rcx, [rsp+98h+var_48]\nxor eax, eax\nmov [rsp+98h+pmatch], rcx\njmp short loc_144B\nloc_1408:\nmovsxd r14, [rsp+98h+var_44]\nmovsxd rsi, [rsp+98h+var_48]\nmovsxd rax, dword ptr [r15]\nmov edx, r14d\nsub edx, esi\nlea rax, [rax+rax*2]\nadd rsi, rbx; src\nadd rbx, r14\nmovsxd r13, edx\nlea rdi, [rbp+rax*2+0]; dest\nmov rdx, r13; n\ncall _strncpy\nmovsxd rax, dword ptr [r15]\nlea rax, [rax+rax*2]\nlea rax, [rbp+rax*2+0]\nmov byte ptr [rax+r13], 0\nmov eax, [r15]\nadd eax, 1\nloc_144B:\nmov [r15], eax\nmov rcx, [rsp+98h+pmatch]; pmatch\nxor r8d, r8d; eflags\nmov edx, 1; nmatch\nmov rsi, rbx; string\nmov rdi, r12; preg\ncall _regexec\ntest eax, eax\njz short loc_1408\nmov rdi, r12; preg\ncall _regfree\nmov rax, [rsp+98h+var_40]\nsub rax, fs:28h\njnz short loc_1491\nadd rsp, 68h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1491:\ncall ___stack_chk_fail", + "ida_pseudo": "unsigned __int64 __fastcall func0(char *string, __int64 a2, int *a3)\n{\n int i; // eax\n const char *v7; // rsi\n size_t v8; // r13\n regex_t preg; // [rsp+10h] [rbp-88h] BYREF\n regmatch_t v11; // [rsp+50h] [rbp-48h] BYREF\n unsigned __int64 v12; // [rsp+58h] [rbp-40h]\n\n v12 = __readfsqword(0x28u);\n regcomp(&preg, \"\\\\b\\\\w{3,5}\\\\b\", 1);\n for ( i = 0; ; i = *a3 + 1 )\n {\n *a3 = i;\n if ( regexec(&preg, string, 1uLL, &v11, 0) )\n break;\n v7 = &string[v11.rm_so];\n string += v11.rm_eo;\n v8 = v11.rm_eo - v11.rm_so;\n strncpy((char *)(a2 + 6LL * *a3), v7, v8);\n *(_BYTE *)(a2 + 6LL * *a3 + v8) = 0;\n }\n regfree(&preg);\n return v12 - __readfsqword(0x28u);\n}", + "ida_strip_asm": "sub_13B0:\nendbr64\npush r15\nmov r15, rdx\nmov edx, 1; cflags\npush r14\npush r13\npush r12\npush rbp\nmov rbp, rsi\nlea rsi, pattern; \"\\\\b\\\\w{3,5}\\\\b\"\npush rbx\nmov rbx, rdi\nsub rsp, 68h\nmov rax, fs:28h\nmov [rsp+98h+var_40], rax\nxor eax, eax\nlea r12, [rsp+98h+preg]\nmov rdi, r12; preg\ncall _regcomp\nlea rcx, [rsp+98h+var_48]\nxor eax, eax\nmov [rsp+98h+pmatch], rcx\njmp short loc_144B\nloc_1408:\nmovsxd r14, [rsp+98h+var_44]\nmovsxd rsi, [rsp+98h+var_48]\nmovsxd rax, dword ptr [r15]\nmov edx, r14d\nsub edx, esi\nlea rax, [rax+rax*2]\nadd rsi, rbx; src\nadd rbx, r14\nmovsxd r13, edx\nlea rdi, [rbp+rax*2+0]; dest\nmov rdx, r13; n\ncall _strncpy\nmovsxd rax, dword ptr [r15]\nlea rax, [rax+rax*2]\nlea rax, [rbp+rax*2+0]\nmov byte ptr [rax+r13], 0\nmov eax, [r15]\nadd eax, 1\nloc_144B:\nmov [r15], eax\nmov rcx, [rsp+98h+pmatch]; pmatch\nxor r8d, r8d; eflags\nmov edx, 1; nmatch\nmov rsi, rbx; string\nmov rdi, r12; preg\ncall _regexec\ntest eax, eax\njz short loc_1408\nmov rdi, r12; preg\ncall _regfree\nmov rax, [rsp+98h+var_40]\nsub rax, fs:28h\njnz short loc_1491\nadd rsp, 68h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1491:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_13B0(char *string, __int64 a2, int *a3)\n{\n int i; // eax\n const char *v7; // rsi\n size_t v8; // r13\n regex_t preg; // [rsp+10h] [rbp-88h] BYREF\n regmatch_t v11; // [rsp+50h] [rbp-48h] BYREF\n unsigned __int64 v12; // [rsp+58h] [rbp-40h]\n\n v12 = __readfsqword(0x28u);\n regcomp(&preg, \"\\\\b\\\\w{3,5}\\\\b\", 1);\n for ( i = 0; ; i = *a3 + 1 )\n {\n *a3 = i;\n if ( regexec(&preg, string, 1uLL, &v11, 0) )\n break;\n v7 = &string[v11.rm_so];\n string += v11.rm_eo;\n v8 = v11.rm_eo - v11.rm_so;\n strncpy((char *)(a2 + 6LL * *a3), v7, v8);\n *(_BYTE *)(a2 + 6LL * *a3 + v8) = 0;\n }\n regfree(&preg);\n return v12 - __readfsqword(0x28u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_13B0(char *string, long long a2, int *a3) {\n int i;\n const char *v7;\n unsigned int v8;\n regex_t preg;\n regmatch_t v11;\n unsigned long long v12;\n v12 = __readfsqword(40u);\n regcomp(&preg, \"\\\\b\\\\w{3,5}\\\\b\", 1);\n for (i = 0;; i = *a3 + 1) {\n *a3 = i;\n if (regexec(&preg, string, 1uLL, &v11, 0)) break;\n v7 = &string[v11.rm_so];\n string += v11.rm_eo;\n v8 = v11.rm_eo - v11.rm_so;\n strncpy((char *)(a2 + 6LL * *a3), v7, v8);\n *(uint8_t *)(a2 + 6LL * *a3 + v8) = 0;\n }\n regfree(&preg);\n return v12 - __readfsqword(40u);\n}", + "ida_pseudo_norm": "unsigned long long func0(char *string, long long a2, int *a3) {\n int i;\n const char *v7;\n unsigned int v8;\n regex_t preg;\n regmatch_t v11;\n unsigned long long v12;\n v12 = __readfsqword(40u);\n regcomp(&preg, \"\\\\b\\\\w{3,5}\\\\b\", 1);\n for (i = 0;; i = *a3 + 1) {\n *a3 = i;\n if (regexec(&preg, string, 1uLL, &v11, 0)) break;\n v7 = &string[v11.rm_so];\n string += v11.rm_eo;\n v8 = v11.rm_eo - v11.rm_so;\n strncpy((char *)(a2 + 6LL * *a3), v7, v8);\n *(uint8_t *)(a2 + 6LL * *a3 + v8) = 0;\n }\n regfree(&preg);\n return v12 - __readfsqword(40u);\n}" + }, + { + "index": 330, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(const char* text, char output[][6], int* count) {\n regex_t regex;\n regmatch_t pmatch[1];\n const char* pattern = \"\\\\b\\\\w{3,5}\\\\b\";\n regcomp(®ex, pattern, REG_EXTENDED);\n const char* current = text;\n *count = 0;\n while (regexec(®ex, current, 1, pmatch, 0) == 0) {\n int start = pmatch[0].rm_so;\n int end = pmatch[0].rm_eo;\n int length = end - start;\n strncpy(output[*count], current + start, length);\n output[*count][length] = '\\0';\n (*count)++;\n current += end;\n }\n regfree(®ex);\n}", + "test": "int main() {\n\n char words1[5][6];\n\n int count1 = 0;\n\n func0(\"For the four consumer complaints contact manager AKR reddy\", words1, &count1);\n\n assert(count1 == 5 && strcmp(words1[0], \"For\") == 0 && strcmp(words1[1], \"the\") == 0 && strcmp(words1[2], \"four\") == 0 && strcmp(words1[3], \"AKR\") == 0 && strcmp(words1[4], \"reddy\") == 0);\n\n \n\n char words2[2][6];\n\n int count2 = 0;\n\n func0(\"Certain service are subject to change MSR\", words2, &count2);\n\n assert(count2 == 2 && strcmp(words2[0], \"are\") == 0 && strcmp(words2[1], \"MSR\") == 0);\n\n\n\n char words3[3][6];\n\n int count3 = 0;\n\n func0(\"Third party legal desclaimers\", words3, &count3);\n\n assert(count3 == 3 && strcmp(words3[0], \"Third\") == 0 && strcmp(words3[1], \"party\") == 0 && strcmp(words3[2], \"legal\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmov %rdi,%r15\npush %r14\npush %r13\npush %r12\npush %rbp\nmov %rsi,%rbp\nlea 0xc4a(%rip),%rsi\npush %rbx\nmov %rdx,%rbx\nmov $0x1,%edx\nsub $0x68,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x58(%rsp)\nxor %eax,%eax\nlea 0x10(%rsp),%r12\nlea 0x50(%rsp),%r13\nmov %r12,%rdi\ncallq 10e0 \nmovl $0x0,(%rbx)\njmp 143e \nnopl 0x0(%rax)\nmovslq 0x54(%rsp),%r14\nmovslq 0x50(%rsp),%rsi\nmovslq (%rbx),%rax\nmov %r14d,%edx\nsub %esi,%edx\nlea (%rax,%rax,2),%rax\nadd %r15,%rsi\nadd %r14,%r15\nmovslq %edx,%rdx\nlea 0x0(%rbp,%rax,2),%rdi\nmov %rdx,0x8(%rsp)\ncallq 10a0 \nmovslq (%rbx),%rax\nmov 0x8(%rsp),%rdx\nlea (%rax,%rax,2),%rax\nlea 0x0(%rbp,%rax,2),%rax\nmovb $0x0,(%rax,%rdx,1)\naddl $0x1,(%rbx)\nxor %r8d,%r8d\nmov %r13,%rcx\nmov $0x1,%edx\nmov %r15,%rsi\nmov %r12,%rdi\ncallq 10f0 \ntest %eax,%eax\nje 13f8 \nmov %r12,%rdi\ncallq 10b0 \nmov 0x58(%rsp),%rax\nxor %fs:0x28,%rax\njne 147f \nadd $0x68,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\ncallq 10c0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov r15, rdx\nmov edx, 1; cflags\npush r14\npush r13\npush r12\npush rbp\nmov rbp, rsi\nlea rsi, pattern; \"\\\\b\\\\w{3,5}\\\\b\"\npush rbx\nmov rbx, rdi\nsub rsp, 68h\nmov rax, fs:28h\nmov [rsp+98h+var_40], rax\nxor eax, eax\nlea r12, [rsp+98h+preg]\nmov rdi, r12; preg\ncall _regcomp\nlea rcx, [rsp+98h+var_48]\nxor eax, eax\nmov [rsp+98h+pmatch], rcx\njmp short loc_144B\nloc_1408:\nmovsxd r14, [rsp+98h+var_44]\nmovsxd rsi, [rsp+98h+var_48]\nmovsxd rax, dword ptr [r15]\nmov edx, r14d\nsub edx, esi\nlea rax, [rax+rax*2]\nadd rsi, rbx; src\nadd rbx, r14\nmovsxd r13, edx\nlea rdi, [rbp+rax*2+0]; dest\nmov rdx, r13; n\ncall _strncpy\nmovsxd rax, dword ptr [r15]\nlea rax, [rax+rax*2]\nlea rax, [rbp+rax*2+0]\nmov byte ptr [rax+r13], 0\nmov eax, [r15]\nadd eax, 1\nloc_144B:\nmov [r15], eax\nmov rcx, [rsp+98h+pmatch]; pmatch\nxor r8d, r8d; eflags\nmov edx, 1; nmatch\nmov rsi, rbx; string\nmov rdi, r12; preg\ncall _regexec\ntest eax, eax\njz short loc_1408\nmov rdi, r12; preg\ncall _regfree\nmov rax, [rsp+98h+var_40]\nsub rax, fs:28h\njnz short loc_1491\nadd rsp, 68h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1491:\ncall ___stack_chk_fail", + "ida_pseudo": "unsigned __int64 __fastcall func0(char *string, __int64 a2, int *a3)\n{\n int i; // eax\n const char *v7; // rsi\n size_t v8; // r13\n regex_t preg; // [rsp+10h] [rbp-88h] BYREF\n regmatch_t v11; // [rsp+50h] [rbp-48h] BYREF\n unsigned __int64 v12; // [rsp+58h] [rbp-40h]\n\n v12 = __readfsqword(0x28u);\n regcomp(&preg, \"\\\\b\\\\w{3,5}\\\\b\", 1);\n for ( i = 0; ; i = *a3 + 1 )\n {\n *a3 = i;\n if ( regexec(&preg, string, 1uLL, &v11, 0) )\n break;\n v7 = &string[v11.rm_so];\n string += v11.rm_eo;\n v8 = v11.rm_eo - v11.rm_so;\n strncpy((char *)(a2 + 6LL * *a3), v7, v8);\n *(_BYTE *)(a2 + 6LL * *a3 + v8) = 0;\n }\n regfree(&preg);\n return v12 - __readfsqword(0x28u);\n}", + "ida_strip_asm": "sub_13B0:\nendbr64\npush r15\nmov r15, rdx\nmov edx, 1; cflags\npush r14\npush r13\npush r12\npush rbp\nmov rbp, rsi\nlea rsi, pattern; \"\\\\b\\\\w{3,5}\\\\b\"\npush rbx\nmov rbx, rdi\nsub rsp, 68h\nmov rax, fs:28h\nmov [rsp+98h+var_40], rax\nxor eax, eax\nlea r12, [rsp+98h+preg]\nmov rdi, r12; preg\ncall _regcomp\nlea rcx, [rsp+98h+var_48]\nxor eax, eax\nmov [rsp+98h+pmatch], rcx\njmp short loc_144B\nloc_1408:\nmovsxd r14, [rsp+98h+var_44]\nmovsxd rsi, [rsp+98h+var_48]\nmovsxd rax, dword ptr [r15]\nmov edx, r14d\nsub edx, esi\nlea rax, [rax+rax*2]\nadd rsi, rbx; src\nadd rbx, r14\nmovsxd r13, edx\nlea rdi, [rbp+rax*2+0]; dest\nmov rdx, r13; n\ncall _strncpy\nmovsxd rax, dword ptr [r15]\nlea rax, [rax+rax*2]\nlea rax, [rbp+rax*2+0]\nmov byte ptr [rax+r13], 0\nmov eax, [r15]\nadd eax, 1\nloc_144B:\nmov [r15], eax\nmov rcx, [rsp+98h+pmatch]; pmatch\nxor r8d, r8d; eflags\nmov edx, 1; nmatch\nmov rsi, rbx; string\nmov rdi, r12; preg\ncall _regexec\ntest eax, eax\njz short loc_1408\nmov rdi, r12; preg\ncall _regfree\nmov rax, [rsp+98h+var_40]\nsub rax, fs:28h\njnz short loc_1491\nadd rsp, 68h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1491:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_13B0(char *string, __int64 a2, int *a3)\n{\n int i; // eax\n const char *v7; // rsi\n size_t v8; // r13\n regex_t preg; // [rsp+10h] [rbp-88h] BYREF\n regmatch_t v11; // [rsp+50h] [rbp-48h] BYREF\n unsigned __int64 v12; // [rsp+58h] [rbp-40h]\n\n v12 = __readfsqword(0x28u);\n regcomp(&preg, \"\\\\b\\\\w{3,5}\\\\b\", 1);\n for ( i = 0; ; i = *a3 + 1 )\n {\n *a3 = i;\n if ( regexec(&preg, string, 1uLL, &v11, 0) )\n break;\n v7 = &string[v11.rm_so];\n string += v11.rm_eo;\n v8 = v11.rm_eo - v11.rm_so;\n strncpy((char *)(a2 + 6LL * *a3), v7, v8);\n *(_BYTE *)(a2 + 6LL * *a3 + v8) = 0;\n }\n regfree(&preg);\n return v12 - __readfsqword(0x28u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_13B0(char *string, long long a2, int *a3) {\n int i;\n const char *v7;\n unsigned int v8;\n regex_t preg;\n regmatch_t v11;\n unsigned long long v12;\n v12 = __readfsqword(40u);\n regcomp(&preg, \"\\\\b\\\\w{3,5}\\\\b\", 1);\n for (i = 0;; i = *a3 + 1) {\n *a3 = i;\n if (regexec(&preg, string, 1uLL, &v11, 0)) break;\n v7 = &string[v11.rm_so];\n string += v11.rm_eo;\n v8 = v11.rm_eo - v11.rm_so;\n strncpy((char *)(a2 + 6LL * *a3), v7, v8);\n *(uint8_t *)(a2 + 6LL * *a3 + v8) = 0;\n }\n regfree(&preg);\n return v12 - __readfsqword(40u);\n}", + "ida_pseudo_norm": "unsigned long long func0(char *string, long long a2, int *a3) {\n int i;\n const char *v7;\n unsigned int v8;\n regex_t preg;\n regmatch_t v11;\n unsigned long long v12;\n v12 = __readfsqword(40u);\n regcomp(&preg, \"\\\\b\\\\w{3,5}\\\\b\", 1);\n for (i = 0;; i = *a3 + 1) {\n *a3 = i;\n if (regexec(&preg, string, 1uLL, &v11, 0)) break;\n v7 = &string[v11.rm_so];\n string += v11.rm_eo;\n v8 = v11.rm_eo - v11.rm_so;\n strncpy((char *)(a2 + 6LL * *a3), v7, v8);\n *(uint8_t *)(a2 + 6LL * *a3 + v8) = 0;\n }\n regfree(&preg);\n return v12 - __readfsqword(40u);\n}" + }, + { + "index": 331, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int count = 0;\n int x = 1;\n while (x < n + 1) {\n if ((x & n) == 0) {\n count += 1;\n }\n x = x << 1;\n }\n return count;\n}", + "test": "int main() {\n\n assert(func0(2) == 1);\n\n assert(func0(4) == 2);\n\n assert(func0(6) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x1,-0x4(%rbp)\njmp 1175 \nmov -0x4(%rbp),%eax\nand -0x14(%rbp),%eax\ntest %eax,%eax\njne 1172 \naddl $0x1,-0x8(%rbp)\nshll -0x4(%rbp)\nmov -0x14(%rbp),%eax\ncmp -0x4(%rbp),%eax\njge 1164 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 1\njmp short loc_1175\nloc_1164:\nmov eax, [rbp+var_4]\nand eax, [rbp+var_14]\ntest eax, eax\njnz short loc_1172\nadd [rbp+var_8], 1\nloc_1172:\nshl [rbp+var_4], 1\nloc_1175:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_4]\njge short loc_1164\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v2; // [rsp+Ch] [rbp-8h]\n int i; // [rsp+10h] [rbp-4h]\n\n v2 = 0;\n for ( i = 1; a1 >= i; i *= 2 )\n {\n if ( (a1 & i) == 0 )\n ++v2;\n }\n return v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 1\njmp short loc_1175\nloc_1164:\nmov eax, [rbp+var_4]\nand eax, [rbp+var_14]\ntest eax, eax\njnz short loc_1172\nadd [rbp+var_8], 1\nloc_1172:\nshl [rbp+var_4], 1\nloc_1175:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_4]\njge short loc_1164\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n unsigned int v2; // [rsp+Ch] [rbp-8h]\n int i; // [rsp+10h] [rbp-4h]\n\n v2 = 0;\n for ( i = 1; a1 >= i; i *= 2 )\n {\n if ( (a1 & i) == 0 )\n ++v2;\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n unsigned int v2;\n int i;\n v2 = 0;\n for (i = 1; a1 >= i; i *= 2) {\n if ((a1 & i) == 0) ++v2;\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v2;\n int i;\n v2 = 0;\n for (i = 1; a1 >= i; i *= 2) {\n if ((a1 & i) == 0) ++v2;\n }\n return v2;\n}" + }, + { + "index": 331, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int count = 0;\n int x = 1;\n while (x < n + 1) {\n if ((x & n) == 0) {\n count += 1;\n }\n x = x << 1;\n }\n return count;\n}", + "test": "int main() {\n\n assert(func0(2) == 1);\n\n assert(func0(4) == 2);\n\n assert(func0(6) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\njle 116e \nmov $0x1,%eax\nmov $0x0,%edx\nmov %edi,%ecx\nand %eax,%ecx\ncmp $0x1,%ecx\nadc $0x0,%edx\nadd %eax,%eax\ncmp %eax,%edi\njge 115b \nmov %edx,%eax\nretq\nmov $0x0,%edx\njmp 116b \n", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njle short loc_116E\nmov eax, 1\nmov edx, 0\nloc_115B:\nmov ecx, edi\nand ecx, eax\ncmp ecx, 1\nadc edx, 0\nadd eax, eax\ncmp edi, eax\njge short loc_115B\nloc_116B:\nmov eax, edx\nretn\nloc_116E:\nmov edx, 0\njmp short loc_116B", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // eax\n unsigned int v2; // edx\n\n if ( a1 <= 0 )\n {\n return 0;\n }\n else\n {\n v1 = 1;\n v2 = 0;\n do\n {\n v2 += (v1 & a1) == 0;\n v1 *= 2;\n }\n while ( a1 >= v1 );\n }\n return v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ntest edi, edi\njle short loc_116E\nmov eax, 1\nmov edx, 0\nloc_115B:\nmov ecx, edi\nand ecx, eax\ncmp ecx, 1\nadc edx, 0\nadd eax, eax\ncmp edi, eax\njge short loc_115B\nloc_116B:\nmov eax, edx\nretn\nloc_116E:\nmov edx, 0\njmp short loc_116B", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v1; // eax\n unsigned int v2; // edx\n\n if ( a1 <= 0 )\n {\n return 0;\n }\n else\n {\n v1 = 1;\n v2 = 0;\n do\n {\n v2 += (v1 & a1) == 0;\n v1 *= 2;\n }\n while ( a1 >= v1 );\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v1;\n unsigned int v2;\n if (a1 <= 0) {\n return 0;\n } else {\n v1 = 1;\n v2 = 0;\n do {\n v2 += (v1 & a1) == 0;\n v1 *= 2;\n } while (a1 >= v1);\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n unsigned int v2;\n if (a1 <= 0) {\n return 0;\n } else {\n v1 = 1;\n v2 = 0;\n do {\n v2 += (v1 & a1) == 0;\n v1 *= 2;\n } while (a1 >= v1);\n }\n return v2;\n}" + }, + { + "index": 332, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n#define NUM_CHARS 256\n\n\n\n", + "func": "int* func0(const char* str) {\n int* freq = calloc(NUM_CHARS, sizeof(int));\n if (freq == NULL) {\n perror(\"Failed to allocate memory\");\n exit(EXIT_FAILURE);\n }\n for (int i = 0; str[i] != '\\0'; i++) {\n unsigned char c = str[i];\n freq[c]++;\n }\n return freq;\n}", + "test": "int main() {\n\n // Test case 1: \"python\"\n\n int* freq1 = func0(\"python\");\n\n assert(freq1['p'] == 1);\n\n assert(freq1['y'] == 1);\n\n assert(freq1['t'] == 1);\n\n assert(freq1['h'] == 1);\n\n assert(freq1['o'] == 1);\n\n assert(freq1['n'] == 1);\n\n free(freq1);\n\n\n\n // Test case 2: \"program\"\n\n int* freq2 = func0(\"program\");\n\n assert(freq2['p'] == 1);\n\n assert(freq2['r'] == 2);\n\n assert(freq2['o'] == 1);\n\n assert(freq2['g'] == 1);\n\n assert(freq2['a'] == 1);\n\n assert(freq2['m'] == 1);\n\n free(freq2);\n\n\n\n // Test case 3: \"language\"\n\n int* freq3 = func0(\"language\");\n\n assert(freq3['l'] == 1);\n\n assert(freq3['a'] == 2);\n\n assert(freq3['n'] == 1);\n\n assert(freq3['g'] == 2);\n\n assert(freq3['u'] == 1);\n\n assert(freq3['e'] == 1);\n\n free(freq3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov $0x4,%esi\nmov $0x100,%edi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\ncmpq $0x0,-0x8(%rbp)\njne 1209 \nlea 0xe0e(%rip),%rdi\ncallq 10c0 \nmov $0x1,%edi\ncallq 10d0 \nmovl $0x0,-0xc(%rbp)\njmp 1243 \nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmov %al,-0xd(%rbp)\nmovzbl -0xd(%rbp),%eax\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nadd $0x1,%edx\nmov %edx,(%rax)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 1212 \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov esi, 4; size\nmov edi, 100h; nmemb\ncall _calloc\nmov [rbp+var_8], rax\ncmp [rbp+var_8], 0\njnz short loc_120C\nlea rax, s; \"Failed to allocate memory\"\nmov rdi, rax; s\ncall _perror\nmov edi, 1; status\ncall _exit\nloc_120C:\nmov [rbp+var_C], 0\njmp short loc_1246\nloc_1215:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_D], al\nmovzx eax, [rbp+var_D]\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rax]\nadd edx, 1\nmov [rax], edx\nadd [rbp+var_C], 1\nloc_1246:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1215\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1)\n{\n char *v1; // rax\n int i; // [rsp+14h] [rbp-Ch]\n char *v4; // [rsp+18h] [rbp-8h]\n\n v4 = (char *)calloc(0x100uLL, 4uLL);\n if ( !v4 )\n {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n {\n v1 = &v4[4 * *(unsigned __int8 *)(i + a1)];\n ++*(_DWORD *)v1;\n }\n return v4;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov esi, 4; size\nmov edi, 100h; nmemb\ncall _calloc\nmov [rbp+var_8], rax\ncmp [rbp+var_8], 0\njnz short loc_120C\nlea rax, s; \"Failed to allocate memory\"\nmov rdi, rax; s\ncall _perror\nmov edi, 1; status\ncall _exit\nloc_120C:\nmov [rbp+var_C], 0\njmp short loc_1246\nloc_1215:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_D], al\nmovzx eax, [rbp+var_D]\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rax]\nadd edx, 1\nmov [rax], edx\nadd [rbp+var_C], 1\nloc_1246:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1215\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11C9(__int64 a1)\n{\n char *v1; // rax\n int i; // [rsp+14h] [rbp-Ch]\n char *v4; // [rsp+18h] [rbp-8h]\n\n v4 = (char *)calloc(0x100uLL, 4uLL);\n if ( !v4 )\n {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n {\n v1 = &v4[4 * *(unsigned __int8 *)(i + a1)];\n ++*(_DWORD *)v1;\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11C9(long long a1) {\n char *v1;\n int i;\n char *v4;\n v4 = (char *)calloc(256uLL, 4uLL);\n if (!v4) {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n for (i = 0; *(uint8_t *)(i + a1); ++i) {\n v1 = &v4[4 * *(unsigned char *)(i + a1)];\n ++*(uint32_t *)v1;\n }\n return v4;\n}", + "ida_pseudo_norm": "char *func0(long long a1) {\n char *v1;\n int i;\n char *v4;\n v4 = (char *)calloc(256uLL, 4uLL);\n if (!v4) {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n for (i = 0; *(uint8_t *)(i + a1); ++i) {\n v1 = &v4[4 * *(unsigned char *)(i + a1)];\n ++*(uint32_t *)v1;\n }\n return v4;\n}" + }, + { + "index": 332, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n#define NUM_CHARS 256\n\n\n\n", + "func": "int* func0(const char* str) {\n int* freq = calloc(NUM_CHARS, sizeof(int));\n if (freq == NULL) {\n perror(\"Failed to allocate memory\");\n exit(EXIT_FAILURE);\n }\n for (int i = 0; str[i] != '\\0'; i++) {\n unsigned char c = str[i];\n freq[c]++;\n }\n return freq;\n}", + "test": "int main() {\n\n // Test case 1: \"python\"\n\n int* freq1 = func0(\"python\");\n\n assert(freq1['p'] == 1);\n\n assert(freq1['y'] == 1);\n\n assert(freq1['t'] == 1);\n\n assert(freq1['h'] == 1);\n\n assert(freq1['o'] == 1);\n\n assert(freq1['n'] == 1);\n\n free(freq1);\n\n\n\n // Test case 2: \"program\"\n\n int* freq2 = func0(\"program\");\n\n assert(freq2['p'] == 1);\n\n assert(freq2['r'] == 2);\n\n assert(freq2['o'] == 1);\n\n assert(freq2['g'] == 1);\n\n assert(freq2['a'] == 1);\n\n assert(freq2['m'] == 1);\n\n free(freq2);\n\n\n\n // Test case 3: \"language\"\n\n int* freq3 = func0(\"language\");\n\n assert(freq3['l'] == 1);\n\n assert(freq3['a'] == 2);\n\n assert(freq3['n'] == 1);\n\n assert(freq3['g'] == 2);\n\n assert(freq3['u'] == 1);\n\n assert(freq3['e'] == 1);\n\n free(freq3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\nmov $0x4,%esi\nmov $0x100,%edi\ncallq 10b0 \ntest %rax,%rax\nje 1205 \nmovzbl (%rbx),%edx\nlea 0x1(%rbx),%rdi\ntest %dl,%dl\nje 1203 \nmovzbl %dl,%edx\naddl $0x1,(%rax,%rdx,4)\nadd $0x1,%rdi\nmovzbl -0x1(%rdi),%edx\ntest %dl,%dl\njne 11f0 \npop %rbx\nretq\nlea 0xdf8(%rip),%rdi\ncallq 10c0 \nmov $0x1,%edi\ncallq 10d0 \n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\nmov esi, 4; size\nmov edi, 100h; nmemb\ncall _calloc\ntest rax, rax\njz short loc_1205\nmovzx edx, byte ptr [rbx]\nlea rdi, [rbx+1]\ntest dl, dl\njz short loc_1203\nloc_11F0:\nmovzx edx, dl\nadd dword ptr [rax+rdx*4], 1\nadd rdi, 1\nmovzx edx, byte ptr [rdi-1]\ntest dl, dl\njnz short loc_11F0\nloc_1203:\npop rbx\nretn\nloc_1205:\nlea rdi, s; \"Failed to allocate memory\"\ncall _perror\nmov edi, 1; status\ncall _exit", + "ida_pseudo": "_DWORD *__fastcall func0(unsigned __int8 *a1)\n{\n _DWORD *result; // rax\n unsigned __int8 v3; // dl\n _BYTE *i; // rdi\n\n result = calloc(0x100uLL, 4uLL);\n if ( !result )\n {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v3 = *a1;\n for ( i = a1 + 1; v3; v3 = *(i - 1) )\n {\n ++result[v3];\n ++i;\n }\n return result;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbx\nmov rbx, rdi\nmov esi, 4; size\nmov edi, 100h; nmemb\ncall _calloc\ntest rax, rax\njz short loc_1205\nmovzx edx, byte ptr [rbx]\nlea rdi, [rbx+1]\ntest dl, dl\njz short loc_1203\nloc_11F0:\nmovzx edx, dl\nadd dword ptr [rax+rdx*4], 1\nadd rdi, 1\nmovzx edx, byte ptr [rdi-1]\ntest dl, dl\njnz short loc_11F0\nloc_1203:\npop rbx\nretn\nloc_1205:\nlea rdi, s; \"Failed to allocate memory\"\ncall _perror\nmov edi, 1; status\ncall _exit", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11C9(unsigned __int8 *a1)\n{\n _DWORD *result; // rax\n unsigned __int8 v3; // dl\n _BYTE *i; // rdi\n\n result = calloc(0x100uLL, 4uLL);\n if ( !result )\n {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v3 = *a1;\n for ( i = a1 + 1; v3; v3 = *(i - 1) )\n {\n ++result[v3];\n ++i;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11C9(unsigned char *a1) {\n uint32_t *result;\n unsigned char v3;\n uint8_t *i;\n result = calloc(256uLL, 4uLL);\n if (!result) {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v3 = *a1;\n for (i = a1 + 1; v3; v3 = *(i - 1)) {\n ++result[v3];\n ++i;\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(unsigned char *a1) {\n uint32_t *result;\n unsigned char v3;\n uint8_t *i;\n result = calloc(256uLL, 4uLL);\n if (!result) {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v3 = *a1;\n for (i = a1 + 1; v3; v3 = *(i - 1)) {\n ++result[v3];\n ++i;\n }\n return result;\n}" + }, + { + "index": 332, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n#define NUM_CHARS 256\n\n\n\n", + "func": "int* func0(const char* str) {\n int* freq = calloc(NUM_CHARS, sizeof(int));\n if (freq == NULL) {\n perror(\"Failed to allocate memory\");\n exit(EXIT_FAILURE);\n }\n for (int i = 0; str[i] != '\\0'; i++) {\n unsigned char c = str[i];\n freq[c]++;\n }\n return freq;\n}", + "test": "int main() {\n\n // Test case 1: \"python\"\n\n int* freq1 = func0(\"python\");\n\n assert(freq1['p'] == 1);\n\n assert(freq1['y'] == 1);\n\n assert(freq1['t'] == 1);\n\n assert(freq1['h'] == 1);\n\n assert(freq1['o'] == 1);\n\n assert(freq1['n'] == 1);\n\n free(freq1);\n\n\n\n // Test case 2: \"program\"\n\n int* freq2 = func0(\"program\");\n\n assert(freq2['p'] == 1);\n\n assert(freq2['r'] == 2);\n\n assert(freq2['o'] == 1);\n\n assert(freq2['g'] == 1);\n\n assert(freq2['a'] == 1);\n\n assert(freq2['m'] == 1);\n\n free(freq2);\n\n\n\n // Test case 3: \"language\"\n\n int* freq3 = func0(\"language\");\n\n assert(freq3['l'] == 1);\n\n assert(freq3['a'] == 2);\n\n assert(freq3['n'] == 1);\n\n assert(freq3['g'] == 2);\n\n assert(freq3['u'] == 1);\n\n assert(freq3['e'] == 1);\n\n free(freq3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov $0x4,%esi\nmov %rdi,%rbx\nmov $0x100,%edi\ncallq 10b0 \ntest %rax,%rax\nje 1575 \nmovzbl (%rbx),%edx\nlea 0x1(%rbx),%rdi\ntest %dl,%dl\nje 1573 \nnopw 0x0(%rax,%rax,1)\nmovzbl %dl,%edx\nadd $0x1,%rdi\naddl $0x1,(%rax,%rdx,4)\nmovzbl -0x1(%rdi),%edx\ntest %dl,%dl\njne 1560 \npop %rbx\nretq\nlea 0xa88(%rip),%rdi\ncallq 10c0 \nmov $0x1,%edi\ncallq 10d0 \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov esi, 4; size\nmov rbx, rdi\nmov edi, 100h; nmemb\ncall _calloc\ntest rax, rax\njz func0_cold\nmovzx edx, byte ptr [rbx]\nlea rdi, [rbx+1]\ntest dl, dl\njz short loc_1590\nnop dword ptr [rax+rax+00h]\nloc_1580:\nadd rdi, 1\nadd dword ptr [rax+rdx*4], 1\nmovzx edx, byte ptr [rdi-1]\ntest dl, dl\njnz short loc_1580\nloc_1590:\npop rbx\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(unsigned __int8 *a1)\n{\n _DWORD *result; // rax\n __int64 v2; // rdx\n unsigned __int8 *i; // rdi\n\n result = calloc(0x100uLL, 4uLL);\n if ( !result )\n func0_cold();\n v2 = *a1;\n for ( i = a1 + 1; (_BYTE)v2; v2 = *(i - 1) )\n {\n ++i;\n ++result[v2];\n }\n return result;\n}", + "ida_strip_asm": "sub_1550:\nendbr64\npush rbx\nmov esi, 4; size\nmov rbx, rdi\nmov edi, 100h; nmemb\ncall _calloc\ntest rax, rax\njz loc_10E0\nmovzx edx, byte ptr [rbx]\nlea rdi, [rbx+1]\ntest dl, dl\njz short loc_1590\nnop dword ptr [rax+rax+00h]\nloc_1580:\nadd rdi, 1\nadd dword ptr [rax+rdx*4], 1\nmovzx edx, byte ptr [rdi-1]\ntest dl, dl\njnz short loc_1580\nloc_1590:\npop rbx\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1550(unsigned __int8 *a1)\n{\n _DWORD *result; // rax\n __int64 v2; // rdx\n unsigned __int8 *i; // rdi\n\n result = calloc(0x100uLL, 4uLL);\n if ( !result )\n {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v2 = *a1;\n for ( i = a1 + 1; (_BYTE)v2; v2 = *(i - 1) )\n {\n ++i;\n ++result[v2];\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1550(unsigned char *a1) {\n uint32_t *result;\n long long v2;\n unsigned char *i;\n result = calloc(256uLL, 4uLL);\n if (!result) {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v2 = *a1;\n for (i = a1 + 1; (uint8_t)v2; v2 = *(i - 1)) {\n ++i;\n ++result[v2];\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(unsigned char *a1) {\n uint32_t *result;\n long long v2;\n unsigned char *i;\n result = calloc(256uLL, 4uLL);\n if (!result) func0_cold();\n v2 = *a1;\n for (i = a1 + 1; (uint8_t)v2; v2 = *(i - 1)) {\n ++i;\n ++result[v2];\n }\n return result;\n}" + }, + { + "index": 332, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n#define NUM_CHARS 256\n\n\n\n", + "func": "int* func0(const char* str) {\n int* freq = calloc(NUM_CHARS, sizeof(int));\n if (freq == NULL) {\n perror(\"Failed to allocate memory\");\n exit(EXIT_FAILURE);\n }\n for (int i = 0; str[i] != '\\0'; i++) {\n unsigned char c = str[i];\n freq[c]++;\n }\n return freq;\n}", + "test": "int main() {\n\n // Test case 1: \"python\"\n\n int* freq1 = func0(\"python\");\n\n assert(freq1['p'] == 1);\n\n assert(freq1['y'] == 1);\n\n assert(freq1['t'] == 1);\n\n assert(freq1['h'] == 1);\n\n assert(freq1['o'] == 1);\n\n assert(freq1['n'] == 1);\n\n free(freq1);\n\n\n\n // Test case 2: \"program\"\n\n int* freq2 = func0(\"program\");\n\n assert(freq2['p'] == 1);\n\n assert(freq2['r'] == 2);\n\n assert(freq2['o'] == 1);\n\n assert(freq2['g'] == 1);\n\n assert(freq2['a'] == 1);\n\n assert(freq2['m'] == 1);\n\n free(freq2);\n\n\n\n // Test case 3: \"language\"\n\n int* freq3 = func0(\"language\");\n\n assert(freq3['l'] == 1);\n\n assert(freq3['a'] == 2);\n\n assert(freq3['n'] == 1);\n\n assert(freq3['g'] == 2);\n\n assert(freq3['u'] == 1);\n\n assert(freq3['e'] == 1);\n\n free(freq3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov $0x4,%esi\nmov %rdi,%rbx\nmov $0x100,%edi\ncallq 10b0 \ntest %rax,%rax\nje 1575 \nmovzbl (%rbx),%edx\nlea 0x1(%rbx),%rdi\ntest %dl,%dl\nje 1573 \nnopw 0x0(%rax,%rax,1)\nmovzbl %dl,%edx\nadd $0x1,%rdi\naddl $0x1,(%rax,%rdx,4)\nmovzbl -0x1(%rdi),%edx\ntest %dl,%dl\njne 1560 \npop %rbx\nretq\nlea 0xa88(%rip),%rdi\ncallq 10c0 \nmov $0x1,%edi\ncallq 10d0 \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov esi, 4; size\nmov rbx, rdi\nmov edi, 100h; nmemb\ncall _calloc\ntest rax, rax\njz func0_cold\nmovzx edx, byte ptr [rbx]\nlea rdi, [rbx+1]\ntest dl, dl\njz short loc_1590\nnop dword ptr [rax+rax+00h]\nloc_1580:\nadd rdi, 1\nadd dword ptr [rax+rdx*4], 1\nmovzx edx, byte ptr [rdi-1]\ntest dl, dl\njnz short loc_1580\nloc_1590:\npop rbx\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(unsigned __int8 *a1)\n{\n _DWORD *result; // rax\n __int64 v2; // rdx\n unsigned __int8 *i; // rdi\n\n result = calloc(0x100uLL, 4uLL);\n if ( !result )\n func0_cold();\n v2 = *a1;\n for ( i = a1 + 1; (_BYTE)v2; v2 = *(i - 1) )\n {\n ++i;\n ++result[v2];\n }\n return result;\n}", + "ida_strip_asm": "sub_1550:\nendbr64\npush rbx\nmov esi, 4; size\nmov rbx, rdi\nmov edi, 100h; nmemb\ncall _calloc\ntest rax, rax\njz loc_10E0\nmovzx edx, byte ptr [rbx]\nlea rdi, [rbx+1]\ntest dl, dl\njz short loc_1590\nnop dword ptr [rax+rax+00h]\nloc_1580:\nadd rdi, 1\nadd dword ptr [rax+rdx*4], 1\nmovzx edx, byte ptr [rdi-1]\ntest dl, dl\njnz short loc_1580\nloc_1590:\npop rbx\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1550(unsigned __int8 *a1)\n{\n _DWORD *result; // rax\n __int64 v2; // rdx\n unsigned __int8 *i; // rdi\n\n result = calloc(0x100uLL, 4uLL);\n if ( !result )\n {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v2 = *a1;\n for ( i = a1 + 1; (_BYTE)v2; v2 = *(i - 1) )\n {\n ++i;\n ++result[v2];\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1550(unsigned char *a1) {\n uint32_t *result;\n long long v2;\n unsigned char *i;\n result = calloc(256uLL, 4uLL);\n if (!result) {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v2 = *a1;\n for (i = a1 + 1; (uint8_t)v2; v2 = *(i - 1)) {\n ++i;\n ++result[v2];\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(unsigned char *a1) {\n uint32_t *result;\n long long v2;\n unsigned char *i;\n result = calloc(256uLL, 4uLL);\n if (!result) func0_cold();\n v2 = *a1;\n for (i = a1 + 1; (uint8_t)v2; v2 = *(i - 1)) {\n ++i;\n ++result[v2];\n }\n return result;\n}" + }, + { + "index": 333, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char* str;\n\n int num;\n\n} pair;\n\n\n\nint compare_pairs(const void* a, const void* b) {\n\n const pair* pa = (const pair*)a;\n\n const pair* pb = (const pair*)b;\n\n return (pa->num - pb->num);\n\n}\n\n\n\n", + "func": "void func0(pair* sub_li, size_t n) {\n qsort(sub_li, n, sizeof(pair), compare_pairs);\n}", + "test": "int main() {\n\n pair array1[] = {{\"a\", 10}, {\"b\", 5}, {\"c\", 20}, {\"d\", 15}};\n\n pair expected1[] = {{\"b\", 5}, {\"a\", 10}, {\"d\", 15}, {\"c\", 20}};\n\n size_t size1 = sizeof(array1) / sizeof(array1[0]);\n\n\n\n pair array2[] = {{\"452\", 10}, {\"256\", 5}, {\"100\", 20}, {\"135\", 15}};\n\n pair expected2[] = {{\"256\", 5}, {\"452\", 10}, {\"135\", 15}, {\"100\", 20}};\n\n size_t size2 = sizeof(array2) / sizeof(array2[0]);\n\n\n\n pair array3[] = {{\"rishi\", 10}, {\"akhil\", 5}, {\"ramya\", 20}, {\"gaur\", 15}};\n\n pair expected3[] = {{\"akhil\", 5}, {\"rishi\", 10}, {\"gaur\", 15}, {\"ramya\", 20}};\n\n size_t size3 = sizeof(array3) / sizeof(array3[0]);\n\n\n\n func0(array1, size1);\n\n func0(array2, size2);\n\n func0(array3, size3);\n\n\n\n for (size_t i = 0; i < size1; i++) {\n\n assert(array1[i].num == expected1[i].num);\n\n }\n\n\n\n for (size_t i = 0; i < size2; i++) {\n\n assert(array2[i].num == expected2[i].num);\n\n }\n\n\n\n for (size_t i = 0; i < size3; i++) {\n\n assert(array3[i].num == expected3[i].num);\n\n }\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %rdi,-0x8(%rbp)\nmov %rsi,-0x10(%rbp)\nmov -0x10(%rbp),%rsi\nmov -0x8(%rbp),%rax\nlea -0x57(%rip),%rcx\nmov $0x10,%edx\nmov %rax,%rdi\ncallq 1070 \nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+base], rdi\nmov [rbp+nmemb], rsi\nmov rsi, [rbp+nmemb]; nmemb\nmov rax, [rbp+base]\nlea rdx, compare_pairs\nmov rcx, rdx; compar\nmov edx, 10h; size\nmov rdi, rax; base\ncall _qsort\nnop\nleave\nretn", + "ida_pseudo": "void __fastcall func0(void *a1, size_t a2)\n{\n qsort(a1, a2, 0x10uLL, compare_pairs);\n}", + "ida_strip_asm": "sub_11BD:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+base], rdi\nmov [rbp+nmemb], rsi\nmov rsi, [rbp+nmemb]; nmemb\nmov rax, [rbp+base]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 10h; size\nmov rdi, rax; base\ncall _qsort\nnop\nleave\nretn", + "ida_strip_pseudo": "void __fastcall sub_11BD(void *a1, size_t a2)\n{\n qsort(a1, a2, 0x10uLL, compar);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_11BD(void *a1, unsigned int a2) { qsort(a1, a2, 16uLL, compar); }", + "ida_pseudo_norm": "void func0(void *a1, unsigned int a2) { qsort(a1, a2, 16uLL, compare_pairs); }" + }, + { + "index": 333, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char* str;\n\n int num;\n\n} pair;\n\n\n\nint compare_pairs(const void* a, const void* b) {\n\n const pair* pa = (const pair*)a;\n\n const pair* pb = (const pair*)b;\n\n return (pa->num - pb->num);\n\n}\n\n\n\n", + "func": "void func0(pair* sub_li, size_t n) {\n qsort(sub_li, n, sizeof(pair), compare_pairs);\n}", + "test": "int main() {\n\n pair array1[] = {{\"a\", 10}, {\"b\", 5}, {\"c\", 20}, {\"d\", 15}};\n\n pair expected1[] = {{\"b\", 5}, {\"a\", 10}, {\"d\", 15}, {\"c\", 20}};\n\n size_t size1 = sizeof(array1) / sizeof(array1[0]);\n\n\n\n pair array2[] = {{\"452\", 10}, {\"256\", 5}, {\"100\", 20}, {\"135\", 15}};\n\n pair expected2[] = {{\"256\", 5}, {\"452\", 10}, {\"135\", 15}, {\"100\", 20}};\n\n size_t size2 = sizeof(array2) / sizeof(array2[0]);\n\n\n\n pair array3[] = {{\"rishi\", 10}, {\"akhil\", 5}, {\"ramya\", 20}, {\"gaur\", 15}};\n\n pair expected3[] = {{\"akhil\", 5}, {\"rishi\", 10}, {\"gaur\", 15}, {\"ramya\", 20}};\n\n size_t size3 = sizeof(array3) / sizeof(array3[0]);\n\n\n\n func0(array1, size1);\n\n func0(array2, size2);\n\n func0(array3, size3);\n\n\n\n for (size_t i = 0; i < size1; i++) {\n\n assert(array1[i].num == expected1[i].num);\n\n }\n\n\n\n for (size_t i = 0; i < size2; i++) {\n\n assert(array2[i].num == expected2[i].num);\n\n }\n\n\n\n for (size_t i = 0; i < size3; i++) {\n\n assert(array3[i].num == expected3[i].num);\n\n }\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x8,%rsp\nlea -0x1a(%rip),%rcx\nmov $0x10,%edx\ncallq 1070 \nadd $0x8,%rsp\nretq\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\nlea rcx, compare_pairs; compar\nmov edx, 10h; size\ncall _qsort\nadd rsp, 8\nretn", + "ida_pseudo": "void __fastcall func0(void *a1, size_t a2)\n{\n qsort(a1, a2, 0x10uLL, compare_pairs);\n}", + "ida_strip_asm": "sub_1194:\nendbr64\nsub rsp, 8\nlea rcx, compar; compar\nmov edx, 10h; size\ncall _qsort\nadd rsp, 8\nretn", + "ida_strip_pseudo": "void __fastcall sub_1194(void *a1, size_t a2)\n{\n qsort(a1, a2, 0x10uLL, compar);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1194(void *a1, unsigned int a2) { qsort(a1, a2, 16uLL, compar); }", + "ida_pseudo_norm": "void func0(void *a1, unsigned int a2) { qsort(a1, a2, 16uLL, compare_pairs); }" + }, + { + "index": 334, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int a, int b, int c) {\n if ((a + b <= c) || (a + c <= b) || (b + c <= a)) {\n return false;\n } else {\n return true;\n }\n}", + "test": "int main() {\n\n assert(func0(1, 2, 3) == false);\n\n assert(func0(2, 3, 5) == false);\n\n assert(func0(7, 10, 5) == true);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov %esi,-0x8(%rbp)\nmov %edx,-0xc(%rbp)\nmov -0x4(%rbp),%edx\nmov -0x8(%rbp),%eax\nadd %edx,%eax\ncmp %eax,-0xc(%rbp)\njge 1181 \nmov -0x4(%rbp),%edx\nmov -0xc(%rbp),%eax\nadd %edx,%eax\ncmp %eax,-0x8(%rbp)\njge 1181 \nmov -0x8(%rbp),%edx\nmov -0xc(%rbp),%eax\nadd %edx,%eax\ncmp %eax,-0x4(%rbp)\njl 1188 \nmov $0x0,%eax\njmp 118d \nmov $0x1,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov [rbp+var_C], edx\nmov edx, [rbp+var_4]\nmov eax, [rbp+var_8]\nadd eax, edx\ncmp [rbp+var_C], eax\njge short loc_1181\nmov edx, [rbp+var_4]\nmov eax, [rbp+var_C]\nadd eax, edx\ncmp [rbp+var_8], eax\njge short loc_1181\nmov edx, [rbp+var_8]\nmov eax, [rbp+var_C]\nadd eax, edx\ncmp [rbp+var_4], eax\njl short loc_1188\nloc_1181:\nmov eax, 0\njmp short loc_118D\nloc_1188:\nmov eax, 1\nloc_118D:\npop rbp\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(int a1, int a2, int a3)\n{\n return a3 < a1 + a2 && a2 < a1 + a3 && a1 < a2 + a3;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov [rbp+var_C], edx\nmov edx, [rbp+var_4]\nmov eax, [rbp+var_8]\nadd eax, edx\ncmp [rbp+var_C], eax\njge short loc_1181\nmov edx, [rbp+var_4]\nmov eax, [rbp+var_C]\nadd eax, edx\ncmp [rbp+var_8], eax\njge short loc_1181\nmov edx, [rbp+var_8]\nmov eax, [rbp+var_C]\nadd eax, edx\ncmp [rbp+var_4], eax\njl short loc_1188\nloc_1181:\nmov eax, 0\njmp short loc_118D\nloc_1188:\nmov eax, 1\nloc_118D:\npop rbp\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1149(int a1, int a2, int a3)\n{\n return a3 < a1 + a2 && a2 < a1 + a3 && a1 < a2 + a3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1149(int a1, int a2, int a3) {\n return a3 < a1 + a2 && a2 < a1 + a3 && a1 < a2 + a3;\n}", + "ida_pseudo_norm": "uint8_t func0(int a1, int a2, int a3) {\n return a3 < a1 + a2 && a2 < a1 + a3 && a1 < a2 + a3;\n}" + }, + { + "index": 335, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "double func0(int a, int n, int d) { return (n * (2 * a + (n - 1) * d)) / 2.0; }", + "test": "int main() {\n\n assert(func0(1, 5, 2) == 25);\n\n assert(func0(2, 6, 4) == 72);\n\n assert(func0(1, 4, 5) == 34);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov %esi,-0x8(%rbp)\nmov %edx,-0xc(%rbp)\nmov -0x4(%rbp),%eax\nlea (%rax,%rax,1),%edx\nmov -0x8(%rbp),%eax\nsub $0x1,%eax\nimul -0xc(%rbp),%eax\nadd %edx,%eax\nimul -0x8(%rbp),%eax\ncvtsi2sd %eax,%xmm0\nmovsd 0xf0c(%rip),%xmm1\ndivsd %xmm1,%xmm0\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov [rbp+var_C], edx\nmov eax, [rbp+var_4]\nlea edx, [rax+rax]\nmov eax, [rbp+var_8]\nsub eax, 1\nimul eax, [rbp+var_C]\nadd eax, edx\nimul eax, [rbp+var_8]\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmovsd xmm1, cs:qword_2070\ndivsd xmm0, xmm1\npop rbp\nretn", + "ida_pseudo": "double __fastcall func0(int a1, int a2, int a3)\n{\n return (double)(a2 * (2 * a1 + a3 * (a2 - 1))) / 2.0;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov [rbp+var_C], edx\nmov eax, [rbp+var_4]\nlea edx, [rax+rax]\nmov eax, [rbp+var_8]\nsub eax, 1\nimul eax, [rbp+var_C]\nadd eax, edx\nimul eax, [rbp+var_8]\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmovsd xmm1, cs:qword_2070\ndivsd xmm0, xmm1\npop rbp\nretn", + "ida_strip_pseudo": "double __fastcall sub_1149(int a1, int a2, int a3)\n{\n return (double)(a2 * (2 * a1 + a3 * (a2 - 1))) / 2.0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1149(int a1, int a2, int a3) {\n return (double)(a2 * (2 * a1 + a3 * (a2 - 1))) / 2.0;\n}", + "ida_pseudo_norm": "double func0(int a1, int a2, int a3) {\n return (double)(a2 * (2 * a1 + a3 * (a2 - 1))) / 2.0;\n}" + }, + { + "index": 336, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "bool func0(char *monthname1) {\n if (monthname1[0] == 'F' && monthname1[1] == 'e' && monthname1[2] == 'b' &&\n monthname1[3] == 'r' && monthname1[4] == 'u' && monthname1[5] == 'a' &&\n monthname1[6] == 'r' && monthname1[7] == 'y' && monthname1[8] == '\\0') {\n return true;\n } else {\n return false;\n }\n}", + "test": "int main() {\n\n assert(func0(\"February\") == true);\n\n assert(func0(\"January\") == false);\n\n assert(func0(\"March\") == false);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x8(%rbp)\nmov -0x8(%rbp),%rax\nmovzbl (%rax),%eax\ncmp $0x46,%al\njne 11df \nmov -0x8(%rbp),%rax\nadd $0x1,%rax\nmovzbl (%rax),%eax\ncmp $0x65,%al\njne 11df \nmov -0x8(%rbp),%rax\nadd $0x2,%rax\nmovzbl (%rax),%eax\ncmp $0x62,%al\njne 11df \nmov -0x8(%rbp),%rax\nadd $0x3,%rax\nmovzbl (%rax),%eax\ncmp $0x72,%al\njne 11df \nmov -0x8(%rbp),%rax\nadd $0x4,%rax\nmovzbl (%rax),%eax\ncmp $0x75,%al\njne 11df \nmov -0x8(%rbp),%rax\nadd $0x5,%rax\nmovzbl (%rax),%eax\ncmp $0x61,%al\njne 11df \nmov -0x8(%rbp),%rax\nadd $0x6,%rax\nmovzbl (%rax),%eax\ncmp $0x72,%al\njne 11df \nmov -0x8(%rbp),%rax\nadd $0x7,%rax\nmovzbl (%rax),%eax\ncmp $0x79,%al\njne 11df \nmov -0x8(%rbp),%rax\nadd $0x8,%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 11df \nmov $0x1,%eax\njmp 11e4 \nmov $0x0,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_8], rdi\nmov rax, [rbp+var_8]\nmovzx eax, byte ptr [rax]\ncmp al, 46h ; 'F'\njnz short loc_11DF\nmov rax, [rbp+var_8]\nadd rax, 1\nmovzx eax, byte ptr [rax]\ncmp al, 65h ; 'e'\njnz short loc_11DF\nmov rax, [rbp+var_8]\nadd rax, 2\nmovzx eax, byte ptr [rax]\ncmp al, 62h ; 'b'\njnz short loc_11DF\nmov rax, [rbp+var_8]\nadd rax, 3\nmovzx eax, byte ptr [rax]\ncmp al, 72h ; 'r'\njnz short loc_11DF\nmov rax, [rbp+var_8]\nadd rax, 4\nmovzx eax, byte ptr [rax]\ncmp al, 75h ; 'u'\njnz short loc_11DF\nmov rax, [rbp+var_8]\nadd rax, 5\nmovzx eax, byte ptr [rax]\ncmp al, 61h ; 'a'\njnz short loc_11DF\nmov rax, [rbp+var_8]\nadd rax, 6\nmovzx eax, byte ptr [rax]\ncmp al, 72h ; 'r'\njnz short loc_11DF\nmov rax, [rbp+var_8]\nadd rax, 7\nmovzx eax, byte ptr [rax]\ncmp al, 79h ; 'y'\njnz short loc_11DF\nmov rax, [rbp+var_8]\nadd rax, 8\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_11DF\nmov eax, 1\njmp short loc_11E4\nloc_11DF:\nmov eax, 0\nloc_11E4:\npop rbp\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(_BYTE *a1)\n{\n return *a1 == 70\n && a1[1] == 101\n && a1[2] == 98\n && a1[3] == 114\n && a1[4] == 117\n && a1[5] == 97\n && a1[6] == 114\n && a1[7] == 121\n && !a1[8];\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_8], rdi\nmov rax, [rbp+var_8]\nmovzx eax, byte ptr [rax]\ncmp al, 46h ; 'F'\njnz short loc_11DF\nmov rax, [rbp+var_8]\nadd rax, 1\nmovzx eax, byte ptr [rax]\ncmp al, 65h ; 'e'\njnz short loc_11DF\nmov rax, [rbp+var_8]\nadd rax, 2\nmovzx eax, byte ptr [rax]\ncmp al, 62h ; 'b'\njnz short loc_11DF\nmov rax, [rbp+var_8]\nadd rax, 3\nmovzx eax, byte ptr [rax]\ncmp al, 72h ; 'r'\njnz short loc_11DF\nmov rax, [rbp+var_8]\nadd rax, 4\nmovzx eax, byte ptr [rax]\ncmp al, 75h ; 'u'\njnz short loc_11DF\nmov rax, [rbp+var_8]\nadd rax, 5\nmovzx eax, byte ptr [rax]\ncmp al, 61h ; 'a'\njnz short loc_11DF\nmov rax, [rbp+var_8]\nadd rax, 6\nmovzx eax, byte ptr [rax]\ncmp al, 72h ; 'r'\njnz short loc_11DF\nmov rax, [rbp+var_8]\nadd rax, 7\nmovzx eax, byte ptr [rax]\ncmp al, 79h ; 'y'\njnz short loc_11DF\nmov rax, [rbp+var_8]\nadd rax, 8\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_11DF\nmov eax, 1\njmp short loc_11E4\nloc_11DF:\nmov eax, 0\nloc_11E4:\npop rbp\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1149(_BYTE *a1)\n{\n return *a1 == 70\n && a1[1] == 101\n && a1[2] == 98\n && a1[3] == 114\n && a1[4] == 117\n && a1[5] == 97\n && a1[6] == 114\n && a1[7] == 121\n && !a1[8];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1149(uint8_t *a1) {\n return *a1 == 70 && a1[1] == 101 && a1[2] == 98 && a1[3] == 114 &&\n a1[4] == 117 && a1[5] == 97 && a1[6] == 114 && a1[7] == 121 && !a1[8];\n}", + "ida_pseudo_norm": "uint8_t func0(uint8_t *a1) {\n return *a1 == 70 && a1[1] == 101 && a1[2] == 98 && a1[3] == 114 &&\n a1[4] == 117 && a1[5] == 97 && a1[6] == 114 && a1[7] == 121 && !a1[8];\n}" + }, + { + "index": 336, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "bool func0(char *monthname1) {\n if (monthname1[0] == 'F' && monthname1[1] == 'e' && monthname1[2] == 'b' &&\n monthname1[3] == 'r' && monthname1[4] == 'u' && monthname1[5] == 'a' &&\n monthname1[6] == 'r' && monthname1[7] == 'y' && monthname1[8] == '\\0') {\n return true;\n } else {\n return false;\n }\n}", + "test": "int main() {\n\n assert(func0(\"February\") == true);\n\n assert(func0(\"January\") == false);\n\n assert(func0(\"March\") == false);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x0,%eax\ncmpb $0x46,(%rdi)\njne 1188 \ncmpb $0x65,0x1(%rdi)\njne 1188 \ncmpb $0x62,0x2(%rdi)\njne 1188 \ncmpb $0x72,0x3(%rdi)\njne 1188 \ncmpb $0x75,0x4(%rdi)\njne 1188 \ncmpb $0x61,0x5(%rdi)\njne 1188 \ncmpb $0x72,0x6(%rdi)\njne 1188 \ncmpb $0x79,0x7(%rdi)\njne 1188 \ncmpb $0x0,0x8(%rdi)\nsete %al\nretq\n", + "ida_asm": "func0:\nendbr64\nmov eax, 0\ncmp byte ptr [rdi], 46h ; 'F'\njnz short locret_1188\ncmp byte ptr [rdi+1], 65h ; 'e'\njnz short locret_1188\ncmp byte ptr [rdi+2], 62h ; 'b'\njnz short locret_1188\ncmp byte ptr [rdi+3], 72h ; 'r'\njnz short locret_1188\ncmp byte ptr [rdi+4], 75h ; 'u'\njnz short locret_1188\ncmp byte ptr [rdi+5], 61h ; 'a'\njnz short locret_1188\ncmp byte ptr [rdi+6], 72h ; 'r'\njnz short locret_1188\ncmp byte ptr [rdi+7], 79h ; 'y'\njnz short locret_1188\ncmp byte ptr [rdi+8], 0\nsetz al\nlocret_1188:\nretn", + "ida_pseudo": "bool __fastcall func0(_BYTE *a1)\n{\n bool result; // al\n\n result = 0;\n if ( *a1 == 70\n && a1[1] == 101\n && a1[2] == 98\n && a1[3] == 114\n && a1[4] == 117\n && a1[5] == 97\n && a1[6] == 114\n && a1[7] == 121 )\n {\n return a1[8] == 0;\n }\n return result;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmov eax, 0\ncmp byte ptr [rdi], 46h ; 'F'\njnz short locret_1188\ncmp byte ptr [rdi+1], 65h ; 'e'\njnz short locret_1188\ncmp byte ptr [rdi+2], 62h ; 'b'\njnz short locret_1188\ncmp byte ptr [rdi+3], 72h ; 'r'\njnz short locret_1188\ncmp byte ptr [rdi+4], 75h ; 'u'\njnz short locret_1188\ncmp byte ptr [rdi+5], 61h ; 'a'\njnz short locret_1188\ncmp byte ptr [rdi+6], 72h ; 'r'\njnz short locret_1188\ncmp byte ptr [rdi+7], 79h ; 'y'\njnz short locret_1188\ncmp byte ptr [rdi+8], 0\nsetz al\nlocret_1188:\nretn", + "ida_strip_pseudo": "bool __fastcall sub_1149(_BYTE *a1)\n{\n bool result; // al\n\n result = 0;\n if ( *a1 == 70\n && a1[1] == 101\n && a1[2] == 98\n && a1[3] == 114\n && a1[4] == 117\n && a1[5] == 97\n && a1[6] == 114\n && a1[7] == 121 )\n {\n return a1[8] == 0;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_1149(uint8_t *a1) {\n bool result;\n result = 0;\n if (*a1 == 70 && a1[1] == 101 && a1[2] == 98 && a1[3] == 114 &&\n a1[4] == 117 && a1[5] == 97 && a1[6] == 114 && a1[7] == 121) {\n return a1[8] == 0;\n }\n return result;\n}", + "ida_pseudo_norm": "bool func0(uint8_t *a1) {\n bool result;\n result = 0;\n if (*a1 == 70 && a1[1] == 101 && a1[2] == 98 && a1[3] == 114 &&\n a1[4] == 117 && a1[5] == 97 && a1[6] == 114 && a1[7] == 121) {\n return a1[8] == 0;\n }\n return result;\n}" + }, + { + "index": 336, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "bool func0(char *monthname1) {\n if (monthname1[0] == 'F' && monthname1[1] == 'e' && monthname1[2] == 'b' &&\n monthname1[3] == 'r' && monthname1[4] == 'u' && monthname1[5] == 'a' &&\n monthname1[6] == 'r' && monthname1[7] == 'y' && monthname1[8] == '\\0') {\n return true;\n } else {\n return false;\n }\n}", + "test": "int main() {\n\n assert(func0(\"February\") == true);\n\n assert(func0(\"January\") == false);\n\n assert(func0(\"March\") == false);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nxor %eax,%eax\ncmpb $0x46,(%rdi)\njne 122c \ncmpb $0x65,0x1(%rdi)\njne 122c \ncmpb $0x62,0x2(%rdi)\njne 122c \ncmpb $0x72,0x3(%rdi)\njne 122c \ncmpb $0x75,0x4(%rdi)\njne 122c \ncmpb $0x61,0x5(%rdi)\njne 122c \ncmpb $0x72,0x6(%rdi)\njne 122c \ncmpb $0x79,0x7(%rdi)\njne 122c \ncmpb $0x0,0x8(%rdi)\nsete %al\nretq\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\nxor eax, eax\ncmp byte ptr [rdi], 46h ; 'F'\njnz short locret_122C\ncmp byte ptr [rdi+1], 65h ; 'e'\njnz short locret_122C\ncmp byte ptr [rdi+2], 62h ; 'b'\njnz short locret_122C\ncmp byte ptr [rdi+3], 72h ; 'r'\njnz short locret_122C\ncmp byte ptr [rdi+4], 75h ; 'u'\njnz short locret_122C\ncmp byte ptr [rdi+5], 61h ; 'a'\njnz short locret_122C\ncmp byte ptr [rdi+6], 72h ; 'r'\njnz short locret_122C\ncmp byte ptr [rdi+7], 79h ; 'y'\njnz short locret_122C\ncmp byte ptr [rdi+8], 0\nsetz al\nlocret_122C:\nretn", + "ida_pseudo": "bool __fastcall func0(_BYTE *a1)\n{\n bool result; // al\n\n result = 0;\n if ( *a1 == 70\n && a1[1] == 101\n && a1[2] == 98\n && a1[3] == 114\n && a1[4] == 117\n && a1[5] == 97\n && a1[6] == 114\n && a1[7] == 121 )\n {\n return a1[8] == 0;\n }\n return result;\n}", + "ida_strip_asm": "sub_11F0:\nendbr64\nxor eax, eax\ncmp byte ptr [rdi], 46h ; 'F'\njnz short locret_122C\ncmp byte ptr [rdi+1], 65h ; 'e'\njnz short locret_122C\ncmp byte ptr [rdi+2], 62h ; 'b'\njnz short locret_122C\ncmp byte ptr [rdi+3], 72h ; 'r'\njnz short locret_122C\ncmp byte ptr [rdi+4], 75h ; 'u'\njnz short locret_122C\ncmp byte ptr [rdi+5], 61h ; 'a'\njnz short locret_122C\ncmp byte ptr [rdi+6], 72h ; 'r'\njnz short locret_122C\ncmp byte ptr [rdi+7], 79h ; 'y'\njnz short locret_122C\ncmp byte ptr [rdi+8], 0\nsetz al\nlocret_122C:\nretn", + "ida_strip_pseudo": "bool __fastcall sub_11F0(_BYTE *a1)\n{\n bool result; // al\n\n result = 0;\n if ( *a1 == 70\n && a1[1] == 101\n && a1[2] == 98\n && a1[3] == 114\n && a1[4] == 117\n && a1[5] == 97\n && a1[6] == 114\n && a1[7] == 121 )\n {\n return a1[8] == 0;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_11F0(uint8_t *a1) {\n bool result;\n result = 0;\n if (*a1 == 70 && a1[1] == 101 && a1[2] == 98 && a1[3] == 114 &&\n a1[4] == 117 && a1[5] == 97 && a1[6] == 114 && a1[7] == 121) {\n return a1[8] == 0;\n }\n return result;\n}", + "ida_pseudo_norm": "bool func0(uint8_t *a1) {\n bool result;\n result = 0;\n if (*a1 == 70 && a1[1] == 101 && a1[2] == 98 && a1[3] == 114 &&\n a1[4] == 117 && a1[5] == 97 && a1[6] == 114 && a1[7] == 121) {\n return a1[8] == 0;\n }\n return result;\n}" + }, + { + "index": 336, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "bool func0(char *monthname1) {\n if (monthname1[0] == 'F' && monthname1[1] == 'e' && monthname1[2] == 'b' &&\n monthname1[3] == 'r' && monthname1[4] == 'u' && monthname1[5] == 'a' &&\n monthname1[6] == 'r' && monthname1[7] == 'y' && monthname1[8] == '\\0') {\n return true;\n } else {\n return false;\n }\n}", + "test": "int main() {\n\n assert(func0(\"February\") == true);\n\n assert(func0(\"January\") == false);\n\n assert(func0(\"March\") == false);\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nxor %eax,%eax\ncmpb $0x46,(%rdi)\njne 122c \ncmpb $0x65,0x1(%rdi)\njne 122c \ncmpb $0x62,0x2(%rdi)\njne 122c \ncmpb $0x72,0x3(%rdi)\njne 122c \ncmpb $0x75,0x4(%rdi)\njne 122c \ncmpb $0x61,0x5(%rdi)\njne 122c \ncmpb $0x72,0x6(%rdi)\njne 122c \ncmpb $0x79,0x7(%rdi)\njne 122c \ncmpb $0x0,0x8(%rdi)\nsete %al\nretq\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\nxor eax, eax\ncmp byte ptr [rdi], 46h ; 'F'\njnz short locret_122C\ncmp byte ptr [rdi+1], 65h ; 'e'\njnz short locret_122C\ncmp byte ptr [rdi+2], 62h ; 'b'\njnz short locret_122C\ncmp byte ptr [rdi+3], 72h ; 'r'\njnz short locret_122C\ncmp byte ptr [rdi+4], 75h ; 'u'\njnz short locret_122C\ncmp byte ptr [rdi+5], 61h ; 'a'\njnz short locret_122C\ncmp byte ptr [rdi+6], 72h ; 'r'\njnz short locret_122C\ncmp byte ptr [rdi+7], 79h ; 'y'\njnz short locret_122C\ncmp byte ptr [rdi+8], 0\nsetz al\nlocret_122C:\nretn", + "ida_pseudo": "bool __fastcall func0(_BYTE *a1)\n{\n bool result; // al\n\n result = 0;\n if ( *a1 == 70\n && a1[1] == 101\n && a1[2] == 98\n && a1[3] == 114\n && a1[4] == 117\n && a1[5] == 97\n && a1[6] == 114\n && a1[7] == 121 )\n {\n return a1[8] == 0;\n }\n return result;\n}", + "ida_strip_asm": "sub_11F0:\nendbr64\nxor eax, eax\ncmp byte ptr [rdi], 46h ; 'F'\njnz short locret_122C\ncmp byte ptr [rdi+1], 65h ; 'e'\njnz short locret_122C\ncmp byte ptr [rdi+2], 62h ; 'b'\njnz short locret_122C\ncmp byte ptr [rdi+3], 72h ; 'r'\njnz short locret_122C\ncmp byte ptr [rdi+4], 75h ; 'u'\njnz short locret_122C\ncmp byte ptr [rdi+5], 61h ; 'a'\njnz short locret_122C\ncmp byte ptr [rdi+6], 72h ; 'r'\njnz short locret_122C\ncmp byte ptr [rdi+7], 79h ; 'y'\njnz short locret_122C\ncmp byte ptr [rdi+8], 0\nsetz al\nlocret_122C:\nretn", + "ida_strip_pseudo": "bool __fastcall sub_11F0(_BYTE *a1)\n{\n bool result; // al\n\n result = 0;\n if ( *a1 == 70\n && a1[1] == 101\n && a1[2] == 98\n && a1[3] == 114\n && a1[4] == 117\n && a1[5] == 97\n && a1[6] == 114\n && a1[7] == 121 )\n {\n return a1[8] == 0;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_11F0(uint8_t *a1) {\n bool result;\n result = 0;\n if (*a1 == 70 && a1[1] == 101 && a1[2] == 98 && a1[3] == 114 &&\n a1[4] == 117 && a1[5] == 97 && a1[6] == 114 && a1[7] == 121) {\n return a1[8] == 0;\n }\n return result;\n}", + "ida_pseudo_norm": "bool func0(uint8_t *a1) {\n bool result;\n result = 0;\n if (*a1 == 70 && a1[1] == 101 && a1[2] == 98 && a1[3] == 114 &&\n a1[4] == 117 && a1[5] == 97 && a1[6] == 114 && a1[7] == 121) {\n return a1[8] == 0;\n }\n return result;\n}" + }, + { + "index": 337, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n regex_t regex;\n char* patterns = \"\\\\w+\\\\S*$\";\n if (regcomp(®ex, patterns, REG_EXTENDED) == 0) {\n regmatch_t matches[1];\n if (regexec(®ex, text, 1, matches, 0) == 0) {\n regfree(®ex);\n return \"Found a match!\";\n } else {\n regfree(®ex);\n return \"Not matched!\";\n }\n }\n return \"Regex compilation failed\";\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"python.\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\"python.\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\" lang .\"), \"Not matched!\") == 0);\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x70,%rsp\nmov %rdi,-0x68(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0xdf9(%rip),%rax\nmov %rax,-0x58(%rbp)\nmov -0x58(%rbp),%rcx\nlea -0x50(%rbp),%rax\nmov $0x1,%edx\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 10d0 \ntest %eax,%eax\njne 127f \nlea -0x10(%rbp),%rdx\nmov -0x68(%rbp),%rsi\nlea -0x50(%rbp),%rax\nmov $0x0,%r8d\nmov %rdx,%rcx\nmov $0x1,%edx\nmov %rax,%rdi\ncallq 10f0 \ntest %eax,%eax\njne 126a \nlea -0x50(%rbp),%rax\nmov %rax,%rdi\ncallq 10a0 \nlea 0xda8(%rip),%rax\njmp 1286 \nlea -0x50(%rbp),%rax\nmov %rax,%rdi\ncallq 10a0 \nlea 0xda2(%rip),%rax\njmp 1286 \nlea 0xda6(%rip),%rax\nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 129a \ncallq 10b0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aWS; \"\\\\w+\\\\S*$\"\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\ntest eax, eax\njnz short loc_127F\nlea rdx, [rbp+pmatch]\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov rcx, rdx; pmatch\nmov edx, 1; nmatch\nmov rdi, rax; preg\ncall _regexec\ntest eax, eax\njnz short loc_126A\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nlea rax, s2; \"Found a match!\"\njmp short loc_1286\nloc_126A:\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nlea rax, aNotMatched; \"Not matched!\"\njmp short loc_1286\nloc_127F:\nlea rax, aRegexCompilati; \"Regex compilation failed\"\nloc_1286:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_129A\ncall ___stack_chk_fail\nlocret_129A:\nleave\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n regmatch_t pmatch; // [rsp+60h] [rbp-10h] BYREF\n unsigned __int64 v4; // [rsp+68h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"\\\\w+\\\\S*$\", 1) )\n return \"Regex compilation failed\";\n if ( regexec(&preg, a1, 1uLL, &pmatch, 0) )\n {\n regfree(&preg);\n return \"Not matched!\";\n }\n else\n {\n regfree(&preg);\n return \"Found a match!\";\n }\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aWS; \"\\\\w+\\\\S*$\"\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\ntest eax, eax\njnz short loc_127F\nlea rdx, [rbp+pmatch]\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov rcx, rdx; pmatch\nmov edx, 1; nmatch\nmov rdi, rax; preg\ncall _regexec\ntest eax, eax\njnz short loc_126A\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nlea rax, s2; \"Found a match!\"\njmp short loc_1286\nloc_126A:\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nlea rax, aNotMatched; \"Not matched!\"\njmp short loc_1286\nloc_127F:\nlea rax, aRegexCompilati; \"Regex compilation failed\"\nloc_1286:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_129A\ncall ___stack_chk_fail\nlocret_129A:\nleave\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_11E9(const char *a1)\n{\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n regmatch_t pmatch; // [rsp+60h] [rbp-10h] BYREF\n unsigned __int64 v4; // [rsp+68h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"\\\\w+\\\\S*$\", 1) )\n return \"Regex compilation failed\";\n if ( regexec(&preg, a1, 1uLL, &pmatch, 0) )\n {\n regfree(&preg);\n return \"Not matched!\";\n }\n else\n {\n regfree(&preg);\n return \"Found a match!\";\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_11E9(const char *a1) {\n regex_t preg;\n regmatch_t pmatch;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n if (regcomp(&preg, \"\\\\w+\\\\S*$\", 1)) return \"Regex compilation failed\";\n if (regexec(&preg, a1, 1uLL, &pmatch, 0)) {\n regfree(&preg);\n return \"Not matched!\";\n } else {\n regfree(&preg);\n return \"Found a match!\";\n }\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n regex_t preg;\n regmatch_t pmatch;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n if (regcomp(&preg, \"\\\\w+\\\\S*$\", 1)) return \"Regex compilation failed\";\n if (regexec(&preg, a1, 1uLL, &pmatch, 0)) {\n regfree(&preg);\n return \"Not matched!\";\n } else {\n regfree(&preg);\n return \"Found a match!\";\n }\n}" + }, + { + "index": 337, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n regex_t regex;\n char* patterns = \"\\\\w+\\\\S*$\";\n if (regcomp(®ex, patterns, REG_EXTENDED) == 0) {\n regmatch_t matches[1];\n if (regexec(®ex, text, 1, matches, 0) == 0) {\n regfree(®ex);\n return \"Found a match!\";\n } else {\n regfree(®ex);\n return \"Not matched!\";\n }\n }\n return \"Regex compilation failed\";\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"python.\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\"python.\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\" lang .\"), \"Not matched!\") == 0);\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nsub $0x50,%rsp\nmov %rdi,%rbx\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nmov $0x1,%edx\nlea 0xe45(%rip),%rsi\ncallq 10c0 \nmov %eax,%edx\nlea 0xe1e(%rip),%rax\ntest %edx,%edx\nje 121c \nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 125d \nadd $0x50,%rsp\npop %rbx\nretq\nlea 0x40(%rsp),%rcx\nmov %rsp,%rdi\nmov $0x0,%r8d\nmov $0x1,%edx\nmov %rbx,%rsi\ncallq 10d0 \ntest %eax,%eax\njne 124c \nmov %rsp,%rdi\ncallq 1090 \nlea 0xdba(%rip),%rax\njmp 1206 \nmov %rsp,%rdi\ncallq 1090 \nlea 0xdb8(%rip),%rax\njmp 1206 \ncallq 10a0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbx\nsub rsp, 50h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+58h+var_10], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"\\\\w+\\\\S*$\"\ncall _regcomp\nmov edx, eax\nlea rax, aRegexCompilati; \"Regex compilation failed\"\ntest edx, edx\njz short loc_123C\nloc_1226:\nmov rdx, [rsp+58h+var_10]\nsub rdx, fs:28h\njnz short loc_127D\nadd rsp, 50h\npop rbx\nretn\nloc_123C:\nlea rcx, [rsp+58h+pmatch]; pmatch\nmov rdi, rsp; preg\nmov r8d, 0; eflags\nmov edx, 1; nmatch\nmov rsi, rbx; string\ncall _regexec\ntest eax, eax\njnz short loc_126C\nmov rdi, rsp; preg\ncall _regfree\nlea rax, s2; \"Found a match!\"\njmp short loc_1226\nloc_126C:\nmov rdi, rsp; preg\ncall _regfree\nlea rax, aNotMatched; \"Not matched!\"\njmp short loc_1226\nloc_127D:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // edx\n const char *result; // rax\n regex_t v3; // [rsp+0h] [rbp-58h] BYREF\n regmatch_t pmatch; // [rsp+40h] [rbp-18h] BYREF\n unsigned __int64 v5; // [rsp+48h] [rbp-10h]\n\n v5 = __readfsqword(0x28u);\n v1 = regcomp(&v3, \"\\\\w+\\\\S*$\", 1);\n result = \"Regex compilation failed\";\n if ( !v1 )\n {\n if ( regexec(&v3, string, 1uLL, &pmatch, 0) )\n {\n regfree(&v3);\n return \"Not matched!\";\n }\n else\n {\n regfree(&v3);\n return \"Found a match!\";\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbx\nsub rsp, 50h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+58h+var_10], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"\\\\w+\\\\S*$\"\ncall _regcomp\nmov edx, eax\nlea rax, aRegexCompilati; \"Regex compilation failed\"\ntest edx, edx\njz short loc_123C\nloc_1226:\nmov rdx, [rsp+58h+var_10]\nsub rdx, fs:28h\njnz short loc_127D\nadd rsp, 50h\npop rbx\nretn\nloc_123C:\nlea rcx, [rsp+58h+pmatch]; pmatch\nmov rdi, rsp; preg\nmov r8d, 0; eflags\nmov edx, 1; nmatch\nmov rsi, rbx; string\ncall _regexec\ntest eax, eax\njnz short loc_126C\nmov rdi, rsp; preg\ncall _regfree\nlea rax, s2; \"Found a match!\"\njmp short loc_1226\nloc_126C:\nmov rdi, rsp; preg\ncall _regfree\nlea rax, aNotMatched; \"Not matched!\"\njmp short loc_1226\nloc_127D:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_11E9(char *string)\n{\n int v1; // edx\n const char *result; // rax\n regex_t v3; // [rsp+0h] [rbp-58h] BYREF\n regmatch_t pmatch; // [rsp+40h] [rbp-18h] BYREF\n unsigned __int64 v5; // [rsp+48h] [rbp-10h]\n\n v5 = __readfsqword(0x28u);\n v1 = regcomp(&v3, \"\\\\w+\\\\S*$\", 1);\n result = \"Regex compilation failed\";\n if ( !v1 )\n {\n if ( regexec(&v3, string, 1uLL, &pmatch, 0) )\n {\n regfree(&v3);\n return \"Not matched!\";\n }\n else\n {\n regfree(&v3);\n return \"Found a match!\";\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_11E9(char *string) {\n int v1;\n const char *result;\n regex_t v3;\n regmatch_t pmatch;\n unsigned long long v5;\n v5 = __readfsqword(40u);\n v1 = regcomp(&v3, \"\\\\w+\\\\S*$\", 1);\n result = \"Regex compilation failed\";\n if (!v1) {\n if (regexec(&v3, string, 1uLL, &pmatch, 0)) {\n regfree(&v3);\n return \"Not matched!\";\n } else {\n regfree(&v3);\n return \"Found a match!\";\n }\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n const char *result;\n regex_t v3;\n regmatch_t pmatch;\n unsigned long long v5;\n v5 = __readfsqword(40u);\n v1 = regcomp(&v3, \"\\\\w+\\\\S*$\", 1);\n result = \"Regex compilation failed\";\n if (!v1) {\n if (regexec(&v3, string, 1uLL, &pmatch, 0)) {\n regfree(&v3);\n return \"Not matched!\";\n } else {\n regfree(&v3);\n return \"Found a match!\";\n }\n }\n return result;\n}" + }, + { + "index": 337, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n regex_t regex;\n char* patterns = \"\\\\w+\\\\S*$\";\n if (regcomp(®ex, patterns, REG_EXTENDED) == 0) {\n regmatch_t matches[1];\n if (regexec(®ex, text, 1, matches, 0) == 0) {\n regfree(®ex);\n return \"Found a match!\";\n } else {\n regfree(®ex);\n return \"Not matched!\";\n }\n }\n return \"Regex compilation failed\";\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"python.\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\"python.\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\" lang .\"), \"Not matched!\") == 0);\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov $0x1,%edx\nlea 0xd77(%rip),%rsi\npush %rbp\nmov %rdi,%rbp\nsub $0x58,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%r12\nmov %r12,%rdi\ncallq 10c0 \nmov %eax,%r8d\nlea 0xd31(%rip),%rax\ntest %r8d,%r8d\nje 1310 \nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 134e \nadd $0x58,%rsp\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax)\nmov %r12,%rdi\nlea 0x40(%rsp),%rcx\nmov $0x1,%edx\nmov %rbp,%rsi\ncallq 10d0 \nmov %r12,%rdi\ntest %eax,%eax\njne 1340 \ncallq 1090 \nlea 0xccc(%rip),%rax\njmp 12f4 \nnopw 0x0(%rax,%rax,1)\ncallq 1090 \nlea 0xcc7(%rip),%rax\njmp 12f4 \ncallq 10a0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov edx, 1; cflags\nmov rbp, rdi\nlea rsi, pattern; \"\\\\w+\\\\S*$\"\npush rbx\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+68h+var_20], rax\nxor eax, eax\nmov rbx, rsp\nmov rdi, rbx; preg\ncall _regcomp\nmov edx, eax\nlea rax, aRegexCompilati; \"Regex compilation failed\"\ntest edx, edx\njz short loc_1320\nloc_1301:\nmov rdx, [rsp+68h+var_20]\nsub rdx, fs:28h\njnz short loc_135E\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1320:\nmov rdi, rbx; preg\nlea rcx, [rsp+68h+pmatch]; pmatch\nxor r8d, r8d; eflags\nmov edx, 1; nmatch\nmov rsi, rbp; string\ncall _regexec\nmov rdi, rbx; preg\ntest eax, eax\njnz short loc_1350\ncall _regfree\nlea rax, s2; \"Found a match!\"\njmp short loc_1301\nloc_1350:\ncall _regfree\nlea rax, aNotMatched; \"Not matched!\"\njmp short loc_1301\nloc_135E:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // edx\n const char *result; // rax\n regex_t v3; // [rsp+0h] [rbp-68h] BYREF\n regmatch_t pmatch; // [rsp+40h] [rbp-28h] BYREF\n unsigned __int64 v5; // [rsp+48h] [rbp-20h]\n\n v5 = __readfsqword(0x28u);\n v1 = regcomp(&v3, \"\\\\w+\\\\S*$\", 1);\n result = \"Regex compilation failed\";\n if ( !v1 )\n {\n if ( regexec(&v3, string, 1uLL, &pmatch, 0) )\n {\n regfree(&v3);\n return \"Not matched!\";\n }\n else\n {\n regfree(&v3);\n return \"Found a match!\";\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\npush rbp\nmov edx, 1; cflags\nmov rbp, rdi\nlea rsi, pattern; \"\\\\w+\\\\S*$\"\npush rbx\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+68h+var_20], rax\nxor eax, eax\nmov rbx, rsp\nmov rdi, rbx; preg\ncall _regcomp\nmov edx, eax\nlea rax, aRegexCompilati; \"Regex compilation failed\"\ntest edx, edx\njz short loc_1320\nloc_1301:\nmov rdx, [rsp+68h+var_20]\nsub rdx, fs:28h\njnz short loc_135E\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1320:\nmov rdi, rbx; preg\nlea rcx, [rsp+68h+pmatch]; pmatch\nxor r8d, r8d; eflags\nmov edx, 1; nmatch\nmov rsi, rbp; string\ncall _regexec\nmov rdi, rbx; preg\ntest eax, eax\njnz short loc_1350\ncall _regfree\nlea rax, s2; \"Found a match!\"\njmp short loc_1301\nloc_1350:\ncall _regfree\nlea rax, aNotMatched; \"Not matched!\"\njmp short loc_1301\nloc_135E:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_12C0(char *string)\n{\n int v1; // edx\n const char *result; // rax\n regex_t v3; // [rsp+0h] [rbp-68h] BYREF\n regmatch_t pmatch; // [rsp+40h] [rbp-28h] BYREF\n unsigned __int64 v5; // [rsp+48h] [rbp-20h]\n\n v5 = __readfsqword(0x28u);\n v1 = regcomp(&v3, \"\\\\w+\\\\S*$\", 1);\n result = \"Regex compilation failed\";\n if ( !v1 )\n {\n if ( regexec(&v3, string, 1uLL, &pmatch, 0) )\n {\n regfree(&v3);\n return \"Not matched!\";\n }\n else\n {\n regfree(&v3);\n return \"Found a match!\";\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_12C0(char *string) {\n int v1;\n const char *result;\n regex_t v3;\n regmatch_t pmatch;\n unsigned long long v5;\n v5 = __readfsqword(40u);\n v1 = regcomp(&v3, \"\\\\w+\\\\S*$\", 1);\n result = \"Regex compilation failed\";\n if (!v1) {\n if (regexec(&v3, string, 1uLL, &pmatch, 0)) {\n regfree(&v3);\n return \"Not matched!\";\n } else {\n regfree(&v3);\n return \"Found a match!\";\n }\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n const char *result;\n regex_t v3;\n regmatch_t pmatch;\n unsigned long long v5;\n v5 = __readfsqword(40u);\n v1 = regcomp(&v3, \"\\\\w+\\\\S*$\", 1);\n result = \"Regex compilation failed\";\n if (!v1) {\n if (regexec(&v3, string, 1uLL, &pmatch, 0)) {\n regfree(&v3);\n return \"Not matched!\";\n } else {\n regfree(&v3);\n return \"Found a match!\";\n }\n }\n return result;\n}" + }, + { + "index": 337, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n regex_t regex;\n char* patterns = \"\\\\w+\\\\S*$\";\n if (regcomp(®ex, patterns, REG_EXTENDED) == 0) {\n regmatch_t matches[1];\n if (regexec(®ex, text, 1, matches, 0) == 0) {\n regfree(®ex);\n return \"Found a match!\";\n } else {\n regfree(®ex);\n return \"Not matched!\";\n }\n }\n return \"Regex compilation failed\";\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"python.\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\"python.\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\" lang .\"), \"Not matched!\") == 0);\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov $0x1,%edx\nlea 0xd77(%rip),%rsi\npush %rbp\nmov %rdi,%rbp\nsub $0x58,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%r12\nmov %r12,%rdi\ncallq 10c0 \nmov %eax,%r8d\nlea 0xd31(%rip),%rax\ntest %r8d,%r8d\nje 1310 \nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 134e \nadd $0x58,%rsp\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax)\nmov %r12,%rdi\nlea 0x40(%rsp),%rcx\nmov $0x1,%edx\nmov %rbp,%rsi\ncallq 10d0 \nmov %r12,%rdi\ntest %eax,%eax\njne 1340 \ncallq 1090 \nlea 0xccc(%rip),%rax\njmp 12f4 \nnopw 0x0(%rax,%rax,1)\ncallq 1090 \nlea 0xcc7(%rip),%rax\njmp 12f4 \ncallq 10a0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov edx, 1; cflags\nmov rbp, rdi\nlea rsi, pattern; \"\\\\w+\\\\S*$\"\npush rbx\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+68h+var_20], rax\nxor eax, eax\nmov rbx, rsp\nmov rdi, rbx; preg\ncall _regcomp\nmov edx, eax\nlea rax, aRegexCompilati; \"Regex compilation failed\"\ntest edx, edx\njz short loc_1320\nloc_1301:\nmov rdx, [rsp+68h+var_20]\nsub rdx, fs:28h\njnz short loc_135E\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1320:\nmov rdi, rbx; preg\nlea rcx, [rsp+68h+pmatch]; pmatch\nxor r8d, r8d; eflags\nmov edx, 1; nmatch\nmov rsi, rbp; string\ncall _regexec\nmov rdi, rbx; preg\ntest eax, eax\njnz short loc_1350\ncall _regfree\nlea rax, s2; \"Found a match!\"\njmp short loc_1301\nloc_1350:\ncall _regfree\nlea rax, aNotMatched; \"Not matched!\"\njmp short loc_1301\nloc_135E:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // edx\n const char *result; // rax\n regex_t v3; // [rsp+0h] [rbp-68h] BYREF\n regmatch_t pmatch; // [rsp+40h] [rbp-28h] BYREF\n unsigned __int64 v5; // [rsp+48h] [rbp-20h]\n\n v5 = __readfsqword(0x28u);\n v1 = regcomp(&v3, \"\\\\w+\\\\S*$\", 1);\n result = \"Regex compilation failed\";\n if ( !v1 )\n {\n if ( regexec(&v3, string, 1uLL, &pmatch, 0) )\n {\n regfree(&v3);\n return \"Not matched!\";\n }\n else\n {\n regfree(&v3);\n return \"Found a match!\";\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\npush rbp\nmov edx, 1; cflags\nmov rbp, rdi\nlea rsi, pattern; \"\\\\w+\\\\S*$\"\npush rbx\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+68h+var_20], rax\nxor eax, eax\nmov rbx, rsp\nmov rdi, rbx; preg\ncall _regcomp\nmov edx, eax\nlea rax, aRegexCompilati; \"Regex compilation failed\"\ntest edx, edx\njz short loc_1320\nloc_1301:\nmov rdx, [rsp+68h+var_20]\nsub rdx, fs:28h\njnz short loc_135E\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1320:\nmov rdi, rbx; preg\nlea rcx, [rsp+68h+pmatch]; pmatch\nxor r8d, r8d; eflags\nmov edx, 1; nmatch\nmov rsi, rbp; string\ncall _regexec\nmov rdi, rbx; preg\ntest eax, eax\njnz short loc_1350\ncall _regfree\nlea rax, s2; \"Found a match!\"\njmp short loc_1301\nloc_1350:\ncall _regfree\nlea rax, aNotMatched; \"Not matched!\"\njmp short loc_1301\nloc_135E:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_12C0(char *string)\n{\n int v1; // edx\n const char *result; // rax\n regex_t v3; // [rsp+0h] [rbp-68h] BYREF\n regmatch_t pmatch; // [rsp+40h] [rbp-28h] BYREF\n unsigned __int64 v5; // [rsp+48h] [rbp-20h]\n\n v5 = __readfsqword(0x28u);\n v1 = regcomp(&v3, \"\\\\w+\\\\S*$\", 1);\n result = \"Regex compilation failed\";\n if ( !v1 )\n {\n if ( regexec(&v3, string, 1uLL, &pmatch, 0) )\n {\n regfree(&v3);\n return \"Not matched!\";\n }\n else\n {\n regfree(&v3);\n return \"Found a match!\";\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_12C0(char *string) {\n int v1;\n const char *result;\n regex_t v3;\n regmatch_t pmatch;\n unsigned long long v5;\n v5 = __readfsqword(40u);\n v1 = regcomp(&v3, \"\\\\w+\\\\S*$\", 1);\n result = \"Regex compilation failed\";\n if (!v1) {\n if (regexec(&v3, string, 1uLL, &pmatch, 0)) {\n regfree(&v3);\n return \"Not matched!\";\n } else {\n regfree(&v3);\n return \"Found a match!\";\n }\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n const char *result;\n regex_t v3;\n regmatch_t pmatch;\n unsigned long long v5;\n v5 = __readfsqword(40u);\n v1 = regcomp(&v3, \"\\\\w+\\\\S*$\", 1);\n result = \"Regex compilation failed\";\n if (!v1) {\n if (regexec(&v3, string, 1uLL, &pmatch, 0)) {\n regfree(&v3);\n return \"Not matched!\";\n } else {\n regfree(&v3);\n return \"Found a match!\";\n }\n }\n return result;\n}" + }, + { + "index": 338, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint check_Equality(char* s, int start, int end) {\n\n return (s[start] == s[end]); \n\n}\n\n\n\n", + "func": "int func0(char* s) {\n int result = 0;\n int n = strlen(s);\n for (int i = 0; i < n; i++) {\n for (int j = 1; j <= n - i; j++) {\n if (check_Equality(s, i, i + j - 1)) {\n result++;\n }\n }\n }\n return result;\n}", + "test": "int main() {\n\n assert(func0(\"aba\") == 4);\n\n assert(func0(\"abcab\") == 7);\n\n assert(func0(\"abc\") == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmovl $0x0,-0x10(%rbp)\nmov -0x18(%rbp),%rax\nmov %rax,%rdi\ncallq 1060 \nmov %eax,-0x4(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 1214 \nmovl $0x1,-0x8(%rbp)\njmp 1205 \nmov -0xc(%rbp),%edx\nmov -0x8(%rbp),%eax\nadd %edx,%eax\nlea -0x1(%rax),%edx\nmov -0xc(%rbp),%ecx\nmov -0x18(%rbp),%rax\nmov %ecx,%esi\nmov %rax,%rdi\ncallq 1169 \ntest %eax,%eax\nje 1201 \naddl $0x1,-0x10(%rbp)\naddl $0x1,-0x8(%rbp)\nmov -0x4(%rbp),%eax\nsub -0xc(%rbp),%eax\ncmp %eax,-0x8(%rbp)\njle 11dd \naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x4(%rbp),%eax\njl 11d4 \nmov -0x10(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov [rbp+var_10], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_C], 0\njmp short loc_1214\nloc_11D4:\nmov [rbp+var_8], 1\njmp short loc_1205\nloc_11DD:\nmov edx, [rbp+var_C]\nmov eax, [rbp+var_8]\nadd eax, edx\nlea edx, [rax-1]\nmov ecx, [rbp+var_C]\nmov rax, [rbp+s]\nmov esi, ecx\nmov rdi, rax\ncall check_Equality\ntest eax, eax\njz short loc_1201\nadd [rbp+var_10], 1\nloc_1201:\nadd [rbp+var_8], 1\nloc_1205:\nmov eax, [rbp+var_4]\nsub eax, [rbp+var_C]\ncmp [rbp+var_8], eax\njle short loc_11DD\nadd [rbp+var_C], 1\nloc_1214:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_4]\njl short loc_11D4\nmov eax, [rbp+var_10]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n unsigned int v2; // [rsp+10h] [rbp-10h]\n unsigned int i; // [rsp+14h] [rbp-Ch]\n int j; // [rsp+18h] [rbp-8h]\n int v5; // [rsp+1Ch] [rbp-4h]\n\n v2 = 0;\n v5 = strlen(a1);\n for ( i = 0; (int)i < v5; ++i )\n {\n for ( j = 1; j <= (int)(v5 - i); ++j )\n {\n if ( (unsigned int)check_Equality(a1, i, i + j - 1) )\n ++v2;\n }\n }\n return v2;\n}", + "ida_strip_asm": "sub_11A5:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov [rbp+var_10], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_C], 0\njmp short loc_1214\nloc_11D4:\nmov [rbp+var_8], 1\njmp short loc_1205\nloc_11DD:\nmov edx, [rbp+var_C]\nmov eax, [rbp+var_8]\nadd eax, edx\nlea edx, [rax-1]\nmov ecx, [rbp+var_C]\nmov rax, [rbp+s]\nmov esi, ecx\nmov rdi, rax\ncall sub_1169\ntest eax, eax\njz short loc_1201\nadd [rbp+var_10], 1\nloc_1201:\nadd [rbp+var_8], 1\nloc_1205:\nmov eax, [rbp+var_4]\nsub eax, [rbp+var_C]\ncmp [rbp+var_8], eax\njle short loc_11DD\nadd [rbp+var_C], 1\nloc_1214:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_4]\njl short loc_11D4\nmov eax, [rbp+var_10]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11A5(const char *a1)\n{\n unsigned int v2; // [rsp+10h] [rbp-10h]\n unsigned int i; // [rsp+14h] [rbp-Ch]\n int j; // [rsp+18h] [rbp-8h]\n int v5; // [rsp+1Ch] [rbp-4h]\n\n v2 = 0;\n v5 = strlen(a1);\n for ( i = 0; (int)i < v5; ++i )\n {\n for ( j = 1; j <= (int)(v5 - i); ++j )\n {\n if ( (unsigned int)sub_1169(a1, i, i + j - 1) )\n ++v2;\n }\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A5(const char *a1) {\n unsigned int v2;\n unsigned int i;\n int j;\n int v5;\n v2 = 0;\n v5 = strlen(a1);\n for (i = 0; (int)i < v5; ++i) {\n for (j = 1; j <= (int)(v5 - i); ++j) {\n if ((unsigned int)sub_1169(a1, i, i + j - 1)) ++v2;\n }\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n unsigned int v2;\n unsigned int i;\n int j;\n int v5;\n v2 = 0;\n v5 = strlen(a1);\n for (i = 0; (int)i < v5; ++i) {\n for (j = 1; j <= (int)(v5 - i); ++j) {\n if ((unsigned int)check_Equality(a1, i, i + j - 1)) ++v2;\n }\n }\n return v2;\n}" + }, + { + "index": 338, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint check_Equality(char* s, int start, int end) {\n\n return (s[start] == s[end]); \n\n}\n\n\n\n", + "func": "int func0(char* s) {\n int result = 0;\n int n = strlen(s);\n for (int i = 0; i < n; i++) {\n for (int j = 1; j <= n - i; j++) {\n if (check_Equality(s, i, i + j - 1)) {\n result++;\n }\n }\n }\n return result;\n}", + "test": "int main() {\n\n assert(func0(\"aba\") == 4);\n\n assert(func0(\"abcab\") == 7);\n\n assert(func0(\"abc\") == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%rdx\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%r10\ntest %r10d,%r10d\njle 11db \npush %rbx\nmov %r10d,%r11d\nmov %rdx,%rdi\nmov $0x0,%r9d\nmov $0x0,%edx\nlea -0x1(%r10),%ebx\njmp 11cf \nmovzbl (%rdi),%r8d\nmov %ebx,%eax\nsub %r9d,%eax\nlea 0x1(%rdi,%rax,1),%rsi\nmov %rdi,%rax\ncmp (%rax),%r8b\nsete %cl\nmovzbl %cl,%ecx\nadd %ecx,%edx\nadd $0x1,%rax\ncmp %rsi,%rax\njne 11ae \nadd $0x1,%r9d\nadd $0x1,%rdi\ncmp %r9d,%r11d\nje 11e3 \nmov %r10d,%eax\nsub %r9d,%eax\ntest %eax,%eax\njg 119d \njmp 11c2 \nmov $0x0,%edx\nmov %edx,%eax\nretq\nmov %edx,%eax\npop %rbx\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest eax, eax\njle short loc_11EA\nmov r10, rax\nmov r11d, eax\nmov rdi, rbx\nmov r9d, 0\nmov eax, 0\nlea ebx, [r10-1]\njmp short loc_11DE\nloc_11AC:\nmovzx r8d, byte ptr [rdi]\nmov edx, ebx\nsub edx, r9d\nlea rsi, [rdi+rdx+1]\nmov rdx, rdi\nloc_11BD:\ncmp r8b, [rdx]\nsetz cl\nmovzx ecx, cl\nadd eax, ecx\nadd rdx, 1\ncmp rdx, rsi\njnz short loc_11BD\nloc_11D1:\nadd r9d, 1\nadd rdi, 1\ncmp r11d, r9d\njz short loc_11EF\nloc_11DE:\nmov edx, r10d\nsub edx, r9d\ntest edx, edx\njg short loc_11AC\njmp short loc_11D1\nloc_11EA:\nmov eax, 0\nloc_11EF:\npop rbx\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v1; // eax\n int v2; // r10d\n int v3; // r11d\n int v4; // r9d\n __int64 result; // rax\n const char *v6; // rdx\n\n v1 = strlen(a1);\n if ( v1 <= 0 )\n return 0LL;\n v2 = v1;\n v3 = v1;\n v4 = 0;\n result = 0LL;\n do\n {\n if ( v2 - v4 > 0 )\n {\n v6 = a1;\n do\n result = (*a1 == *v6++) + (unsigned int)result;\n while ( v6 != &a1[v2 - 1 - v4 + 1] );\n }\n ++v4;\n ++a1;\n }\n while ( v3 != v4 );\n return result;\n}", + "ida_strip_asm": "sub_1181:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest eax, eax\njle short loc_11EA\nmov r10, rax\nmov r11d, eax\nmov rdi, rbx\nmov r9d, 0\nmov eax, 0\nlea ebx, [r10-1]\njmp short loc_11DE\nloc_11AC:\nmovzx r8d, byte ptr [rdi]\nmov edx, ebx\nsub edx, r9d\nlea rsi, [rdi+rdx+1]\nmov rdx, rdi\nloc_11BD:\ncmp r8b, [rdx]\nsetz cl\nmovzx ecx, cl\nadd eax, ecx\nadd rdx, 1\ncmp rdx, rsi\njnz short loc_11BD\nloc_11D1:\nadd r9d, 1\nadd rdi, 1\ncmp r11d, r9d\njz short loc_11EF\nloc_11DE:\nmov edx, r10d\nsub edx, r9d\ntest edx, edx\njg short loc_11AC\njmp short loc_11D1\nloc_11EA:\nmov eax, 0\nloc_11EF:\npop rbx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1181(const char *a1)\n{\n int v1; // eax\n int v2; // r10d\n int v3; // r11d\n int v4; // r9d\n __int64 result; // rax\n const char *v6; // rdx\n\n v1 = strlen(a1);\n if ( v1 <= 0 )\n return 0LL;\n v2 = v1;\n v3 = v1;\n v4 = 0;\n result = 0LL;\n do\n {\n if ( v2 - v4 > 0 )\n {\n v6 = a1;\n do\n result = (*a1 == *v6++) + (unsigned int)result;\n while ( v6 != &a1[v2 - 1 - v4 + 1] );\n }\n ++v4;\n ++a1;\n }\n while ( v3 != v4 );\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1181(const char *a1) {\n int v1;\n int v2;\n int v3;\n int v4;\n long long result;\n const char *v6;\n v1 = strlen(a1);\n if (v1 <= 0) return 0LL;\n v2 = v1;\n v3 = v1;\n v4 = 0;\n result = 0LL;\n do {\n if (v2 - v4 > 0) {\n v6 = a1;\n do\n result = (*a1 == *v6++) + (unsigned int)result;\n while (v6 != &a1[v2 - 1 - v4 + 1]);\n }\n ++v4;\n ++a1;\n } while (v3 != v4);\n return result;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v1;\n int v2;\n int v3;\n int v4;\n long long result;\n const char *v6;\n v1 = strlen(a1);\n if (v1 <= 0) return 0LL;\n v2 = v1;\n v3 = v1;\n v4 = 0;\n result = 0LL;\n do {\n if (v2 - v4 > 0) {\n v6 = a1;\n do\n result = (*a1 == *v6++) + (unsigned int)result;\n while (v6 != &a1[v2 - 1 - v4 + 1]);\n }\n ++v4;\n ++a1;\n } while (v3 != v4);\n return result;\n}" + }, + { + "index": 338, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint check_Equality(char* s, int start, int end) {\n\n return (s[start] == s[end]); \n\n}\n\n\n\n", + "func": "int func0(char* s) {\n int result = 0;\n int n = strlen(s);\n for (int i = 0; i < n; i++) {\n for (int j = 1; j <= n - i; j++) {\n if (check_Equality(s, i, i + j - 1)) {\n result++;\n }\n }\n }\n return result;\n}", + "test": "int main() {\n\n assert(func0(\"aba\") == 4);\n\n assert(func0(\"abcab\") == 7);\n\n assert(func0(\"abc\") == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\ncallq 1060 \ntest %eax,%eax\njle 1292 \nmov %eax,%r10d\nmov %rbx,%rdi\nxor %r9d,%r9d\nxor %r8d,%r8d\nlea -0x1(%rax),%r11d\nnopl 0x0(%rax)\nmov %r11d,%ecx\nmovzbl (%rdi),%esi\nmov %rdi,%rax\nadd $0x1,%rdi\nsub %r9d,%ecx\nadd %rdi,%rcx\nnopl 0x0(%rax,%rax,1)\nxor %edx,%edx\ncmp (%rax),%sil\nsete %dl\nadd $0x1,%rax\nadd %edx,%r8d\ncmp %rax,%rcx\njne 1270 \nadd $0x1,%r9d\ncmp %r9d,%r10d\njne 1258 \nmov %r8d,%eax\npop %rbx\nretq\nxor %r8d,%r8d\npop %rbx\nmov %r8d,%eax\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest eax, eax\njle short loc_1288\nmov r10d, eax\nmov rdi, rbx\nxor r9d, r9d\nxor edx, edx\nlea r11d, [rax-1]\nloc_1250:\nmov esi, r11d\nmovzx r8d, byte ptr [rdi]\nmov rax, rdi\nadd rdi, 1\nsub esi, r9d\nadd rsi, rdi\nnop dword ptr [rax+00h]\nloc_1268:\nxor ecx, ecx\ncmp r8b, [rax]\nsetz cl\nadd rax, 1\nadd edx, ecx\ncmp rsi, rax\njnz short loc_1268\nadd r9d, 1\ncmp r10d, r9d\njnz short loc_1250\nmov eax, edx\npop rbx\nretn\nloc_1288:\nxor edx, edx\npop rbx\nmov eax, edx\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v1; // eax\n int v2; // r10d\n int v3; // r9d\n unsigned int v4; // edx\n int v5; // r11d\n char v6; // r8\n const char *v7; // rax\n int v8; // ecx\n\n v1 = strlen(a1);\n if ( v1 <= 0 )\n return 0LL;\n v2 = v1;\n v3 = 0;\n v4 = 0;\n v5 = v1 - 1;\n do\n {\n v6 = *a1;\n v7 = a1++;\n do\n {\n v8 = v6 == *v7++;\n v4 += v8;\n }\n while ( &a1[v5 - v3] != v7 );\n ++v3;\n }\n while ( v2 != v3 );\n return v4;\n}", + "ida_strip_asm": "sub_1230:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest eax, eax\njle short loc_1288\nmov r10d, eax\nmov rdi, rbx\nxor r9d, r9d\nxor edx, edx\nlea r11d, [rax-1]\nloc_1250:\nmov esi, r11d\nmovzx r8d, byte ptr [rdi]\nmov rax, rdi\nadd rdi, 1\nsub esi, r9d\nadd rsi, rdi\nnop dword ptr [rax+00h]\nloc_1268:\nxor ecx, ecx\ncmp r8b, [rax]\nsetz cl\nadd rax, 1\nadd edx, ecx\ncmp rsi, rax\njnz short loc_1268\nadd r9d, 1\ncmp r10d, r9d\njnz short loc_1250\nmov eax, edx\npop rbx\nretn\nloc_1288:\nxor edx, edx\npop rbx\nmov eax, edx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1230(const char *a1)\n{\n int v1; // eax\n int v2; // r10d\n int v3; // r9d\n unsigned int v4; // edx\n int v5; // r11d\n char v6; // r8\n const char *v7; // rax\n int v8; // ecx\n\n v1 = strlen(a1);\n if ( v1 <= 0 )\n return 0LL;\n v2 = v1;\n v3 = 0;\n v4 = 0;\n v5 = v1 - 1;\n do\n {\n v6 = *a1;\n v7 = a1++;\n do\n {\n v8 = v6 == *v7++;\n v4 += v8;\n }\n while ( &a1[v5 - v3] != v7 );\n ++v3;\n }\n while ( v2 != v3 );\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1230(const char *a1) {\n int v1;\n int v2;\n int v3;\n unsigned int v4;\n int v5;\n char v6;\n const char *v7;\n int v8;\n v1 = strlen(a1);\n if (v1 <= 0) return 0LL;\n v2 = v1;\n v3 = 0;\n v4 = 0;\n v5 = v1 - 1;\n do {\n v6 = *a1;\n v7 = a1++;\n do {\n v8 = v6 == *v7++;\n v4 += v8;\n } while (&a1[v5 - v3] != v7);\n ++v3;\n } while (v2 != v3);\n return v4;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v1;\n int v2;\n int v3;\n unsigned int v4;\n int v5;\n char v6;\n const char *v7;\n int v8;\n v1 = strlen(a1);\n if (v1 <= 0) return 0LL;\n v2 = v1;\n v3 = 0;\n v4 = 0;\n v5 = v1 - 1;\n do {\n v6 = *a1;\n v7 = a1++;\n do {\n v8 = v6 == *v7++;\n v4 += v8;\n } while (&a1[v5 - v3] != v7);\n ++v3;\n } while (v2 != v3);\n return v4;\n}" + }, + { + "index": 338, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint check_Equality(char* s, int start, int end) {\n\n return (s[start] == s[end]); \n\n}\n\n\n\n", + "func": "int func0(char* s) {\n int result = 0;\n int n = strlen(s);\n for (int i = 0; i < n; i++) {\n for (int j = 1; j <= n - i; j++) {\n if (check_Equality(s, i, i + j - 1)) {\n result++;\n }\n }\n }\n return result;\n}", + "test": "int main() {\n\n assert(func0(\"aba\") == 4);\n\n assert(func0(\"abcab\") == 7);\n\n assert(func0(\"abc\") == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nmov %rdi,%rbx\nsub $0x8,%rsp\ncallq 1060 \ntest %eax,%eax\njle 152a \nmovdqa 0xe4e(%rip),%xmm5\nmov %rax,%rdx\nmov %eax,%r11d\nmov %eax,%ebp\nmov %rbx,%rdi\nxor %esi,%esi\npxor %xmm4,%xmm4\nxor %r8d,%r8d\npxor %xmm3,%xmm3\nnopw 0x0(%rax,%rax,1)\nlea -0x1(%rdx),%r10d\nmovzbl (%rdi),%r9d\ncmp $0xe,%r10d\njbe 1520 \nmovd %r9d,%xmm7\nmov %edx,%ecx\npxor %xmm1,%xmm1\nmov %rdi,%rax\npunpcklbw %xmm7,%xmm7\nshr $0x4,%ecx\npunpcklwd %xmm7,%xmm7\nshl $0x4,%rcx\npshufd $0x0,%xmm7,%xmm7\nadd %rdi,%rcx\nnopw 0x0(%rax,%rax,1)\nmovdqu (%rax),%xmm0\nmovdqa %xmm4,%xmm6\nadd $0x10,%rax\npcmpeqb %xmm7,%xmm0\npand %xmm5,%xmm0\npcmpgtb %xmm0,%xmm6\nmovdqa %xmm0,%xmm2\npunpcklbw %xmm6,%xmm2\npunpckhbw %xmm6,%xmm0\nmovdqa %xmm3,%xmm6\npcmpgtw %xmm2,%xmm6\nmovdqa %xmm2,%xmm8\npunpcklwd %xmm6,%xmm8\npunpckhwd %xmm6,%xmm2\nmovdqa %xmm0,%xmm6\npaddd %xmm8,%xmm1\npaddd %xmm2,%xmm1\nmovdqa %xmm3,%xmm2\npcmpgtw %xmm0,%xmm2\npunpcklwd %xmm2,%xmm6\npunpckhwd %xmm2,%xmm0\npaddd %xmm6,%xmm1\npaddd %xmm0,%xmm1\ncmp %rax,%rcx\njne 12b0 \nmovdqa %xmm1,%xmm0\nmov %edx,%ecx\npsrldq $0x8,%xmm0\nand $0xfffffff0,%ecx\npaddd %xmm1,%xmm0\nmovdqa %xmm0,%xmm1\npsrldq $0x4,%xmm1\npaddd %xmm1,%xmm0\nmovd %xmm0,%eax\nadd %eax,%r8d\nlea 0x1(%rcx),%eax\ncmp %ecx,%edx\nje 1500 \nlea -0x1(%rsi,%rax,1),%ecx\nmovslq %ecx,%rcx\ncmp (%rbx,%rcx,1),%r9b\nsete %cl\nmovzbl %cl,%ecx\nadd %ecx,%r8d\nlea 0x1(%rax),%ecx\ncmp %edx,%ecx\njg 1500 \nlea -0x1(%rsi,%rcx,1),%ecx\nmovslq %ecx,%rcx\ncmp (%rbx,%rcx,1),%r9b\nsete %cl\nmovzbl %cl,%ecx\nadd %ecx,%r8d\nlea 0x2(%rax),%ecx\ncmp %edx,%ecx\njg 1500 \nlea -0x1(%rsi,%rcx,1),%ecx\nmovslq %ecx,%rcx\ncmp (%rbx,%rcx,1),%r9b\nsete %cl\nmovzbl %cl,%ecx\nadd %ecx,%r8d\nlea 0x3(%rax),%ecx\ncmp %edx,%ecx\njg 1500 \nlea -0x1(%rsi,%rcx,1),%ecx\nmovslq %ecx,%rcx\ncmp (%rbx,%rcx,1),%r9b\nsete %cl\nmovzbl %cl,%ecx\nadd %ecx,%r8d\nlea 0x4(%rax),%ecx\ncmp %edx,%ecx\njg 1500 \nlea -0x1(%rcx,%rsi,1),%ecx\nmovslq %ecx,%rcx\ncmp (%rbx,%rcx,1),%r9b\nsete %cl\nmovzbl %cl,%ecx\nadd %ecx,%r8d\nlea 0x5(%rax),%ecx\ncmp %edx,%ecx\njg 1500 \nlea -0x1(%rsi,%rcx,1),%ecx\nmovslq %ecx,%rcx\ncmp (%rbx,%rcx,1),%r9b\nsete %cl\nmovzbl %cl,%ecx\nadd %ecx,%r8d\nlea 0x6(%rax),%ecx\ncmp %edx,%ecx\njg 1500 \nlea -0x1(%rsi,%rcx,1),%ecx\nmovslq %ecx,%rcx\ncmp (%rbx,%rcx,1),%r9b\nsete %cl\nmovzbl %cl,%ecx\nadd %ecx,%r8d\nlea 0x7(%rax),%ecx\ncmp %ecx,%edx\njl 1500 \nlea -0x1(%rsi,%rcx,1),%ecx\nmovslq %ecx,%rcx\ncmp (%rbx,%rcx,1),%r9b\nsete %cl\nmovzbl %cl,%ecx\nadd %ecx,%r8d\nlea 0x8(%rax),%ecx\ncmp %ecx,%edx\njl 1500 \nlea -0x1(%rsi,%rcx,1),%ecx\nmovslq %ecx,%rcx\ncmp (%rbx,%rcx,1),%r9b\nsete %cl\nmovzbl %cl,%ecx\nadd %ecx,%r8d\nlea 0x9(%rax),%ecx\ncmp %ecx,%edx\njl 1500 \nlea -0x1(%rsi,%rcx,1),%ecx\nmovslq %ecx,%rcx\ncmp (%rbx,%rcx,1),%r9b\nsete %cl\nmovzbl %cl,%ecx\nadd %ecx,%r8d\nlea 0xa(%rax),%ecx\ncmp %ecx,%edx\njl 1500 \nlea -0x1(%rsi,%rcx,1),%ecx\nmovslq %ecx,%rcx\ncmp (%rbx,%rcx,1),%r9b\nsete %cl\nmovzbl %cl,%ecx\nadd %ecx,%r8d\nlea 0xb(%rax),%ecx\ncmp %ecx,%edx\njl 1500 \nlea -0x1(%rsi,%rcx,1),%ecx\nmovslq %ecx,%rcx\ncmp (%rbx,%rcx,1),%r9b\nsete %cl\nmovzbl %cl,%ecx\nadd %ecx,%r8d\nlea 0xc(%rax),%ecx\ncmp %ecx,%edx\njl 1500 \nlea -0x1(%rsi,%rcx,1),%edx\nmov %ebp,%ecx\nmovslq %edx,%rdx\ncmp (%rbx,%rdx,1),%r9b\nsete %dl\nsub %esi,%ecx\nmovzbl %dl,%edx\nadd %edx,%r8d\nlea 0xd(%rax),%edx\ncmp %ecx,%edx\njg 1500 \nlea -0x1(%rsi,%rdx,1),%edx\nmovslq %edx,%rdx\ncmp (%rbx,%rdx,1),%r9b\nsete %dl\nadd $0xe,%eax\nmovzbl %dl,%edx\nadd %edx,%r8d\ncmp %eax,%ecx\njl 1500 \nlea -0x1(%rsi,%rax,1),%eax\ncltq\ncmp (%rbx,%rax,1),%r9b\nsete %al\nmovzbl %al,%eax\nadd %eax,%r8d\nxchg %ax,%ax\nadd $0x1,%esi\nadd $0x1,%rdi\nmov %r10d,%edx\ncmp %esi,%r11d\njne 1270 \nadd $0x8,%rsp\nmov %r8d,%eax\npop %rbx\npop %rbp\nretq\nnopl (%rax)\nmov $0x1,%eax\njmpq 1345 \nadd $0x8,%rsp\nxor %r8d,%r8d\nmov %r8d,%eax\npop %rbx\npop %rbp\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\ncall _strlen\ntest eax, eax\njle loc_151D\nmov rcx, rax\nmov r10, rbx\nxor r11d, r11d\nxor edi, edi\npxor xmm6, xmm6\npxor xmm5, xmm5\npxor xmm4, xmm4\npxor xmm3, xmm3\nnop word ptr [rax+rax+00000000h]\nloc_1270:\nlea r8d, [rcx-1]\nmovzx edx, byte ptr [r10]\nmov esi, r11d\ncmp r8d, 0Eh\njbe loc_14E0\nmovd xmm8, edx\nmov r9d, ecx\npxor xmm1, xmm1\nmov rax, r10\npunpcklbw xmm8, xmm8\nshr r9d, 4\npunpcklwd xmm8, xmm8\nshl r9, 4\npshufd xmm8, xmm8, 0\nadd r9, r10\nnop\nloc_12B0:\nmovdqu xmm0, xmmword ptr [rax]\nmovdqa xmm7, xmm4\nadd rax, 10h\npcmpeqb xmm0, xmm8\npcmpgtb xmm7, xmm0\nmovdqa xmm2, xmm0\npunpcklbw xmm2, xmm7\npunpckhbw xmm0, xmm7\nmovdqa xmm7, xmm3\npcmpgtw xmm7, xmm2\nmovdqa xmm9, xmm2\npunpcklwd xmm9, xmm7\npunpckhwd xmm2, xmm7\nmovdqa xmm7, xmm0\npsubd xmm1, xmm9\npsubd xmm1, xmm2\nmovdqa xmm2, xmm3\npcmpgtw xmm2, xmm0\npunpcklwd xmm7, xmm2\npunpckhwd xmm0, xmm2\npsubd xmm1, xmm7\npsubd xmm1, xmm0\ncmp r9, rax\njnz short loc_12B0\nmovdqa xmm0, xmm1\nmov ebp, ecx\npsrldq xmm0, 8\nand ebp, 0FFFFFFF0h\npaddd xmm0, xmm1\nlea r14d, [rbp+1]\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\npaddd xmm0, xmm2\nmovd eax, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm1, 8\npaddd xmm0, xmm1\nlea r12d, [rax+rdi]\ntest cl, 0Fh\njz loc_1510\nmov r9d, ecx\nsub r9d, ebp\nlea r13d, [r9-1]\ncmp r13d, 6\njbe loc_1508\nloc_1366:\nlea r12, [rbx+r11]\nmovdqa xmm7, xmm6\nmovq xmm2, qword ptr [r12+rbp]\nmovzx ebp, dl\nmov eax, ebp\nmov ah, al\nmov ebp, eax\nmovd xmm1, ebp\npshuflw xmm1, xmm1, 0\npcmpeqb xmm2, xmm1\npcmpgtb xmm7, xmm2\nmovdqa xmm1, xmm2\npunpcklbw xmm1, xmm7\npunpcklbw xmm2, xmm7\nmovdqa xmm7, xmm5\npcmpgtw xmm7, xmm1\nmovdqa xmm8, xmm1\npshufd xmm2, xmm2, 4Eh ; 'N'\npunpcklwd xmm8, xmm7\npunpcklwd xmm1, xmm7\nmovdqa xmm7, xmm2\npsubd xmm0, xmm8\npshufd xmm1, xmm1, 4Eh ; 'N'\npsubd xmm0, xmm1\nmovdqa xmm1, xmm5\npcmpgtw xmm1, xmm2\npunpcklwd xmm7, xmm1\npunpcklwd xmm2, xmm1\npsubd xmm0, xmm7\npshufd xmm2, xmm2, 4Eh ; 'N'\npsubd xmm0, xmm2\nmovd r12d, xmm0\npshufd xmm1, xmm0, 0E5h\nmovd ebp, xmm1\nadd ebp, r12d\nadd edi, ebp\nmov ebp, r9d\nand ebp, 0FFFFFFF8h\nadd r14d, ebp\nand r9d, 7\njz loc_14D0\nloc_140A:\nlea r9d, [rsi+r14-1]\nmovsxd r9, r9d\ncmp dl, [rbx+r9]\njnz short loc_141B\nadd edi, 1\nloc_141B:\nlea r9d, [r14+1]\ncmp r9d, ecx\njg loc_14D0\nlea r9d, [rsi+r9-1]\nmovsxd r9, r9d\ncmp dl, [rbx+r9]\njnz short loc_1439\nadd edi, 1\nloc_1439:\nlea r9d, [r14+2]\ncmp ecx, r9d\njl short loc_14C0\nlea r9d, [rsi+r9-1]\nmovsxd r9, r9d\ncmp dl, [rbx+r9]\njnz short loc_1453\nadd edi, 1\nloc_1453:\nlea r9d, [r14+3]\ncmp ecx, r9d\njl short loc_14C0\nlea r9d, [rsi+r9-1]\nmovsxd r9, r9d\ncmp dl, [rbx+r9]\njnz short loc_146D\nadd edi, 1\nloc_146D:\nlea r9d, [r14+4]\ncmp r9d, ecx\njg short loc_14C0\nlea r9d, [rsi+r9-1]\nmovsxd r9, r9d\ncmp dl, [rbx+r9]\njnz short loc_1487\nadd edi, 1\nloc_1487:\nlea r9d, [r14+5]\ncmp r9d, ecx\njg short loc_14C0\nlea r9d, [rsi+r9-1]\nmovsxd r9, r9d\ncmp dl, [rbx+r9]\njnz short loc_14A1\nadd edi, 1\nloc_14A1:\nlea eax, [r14+6]\ncmp eax, ecx\njg short loc_14C0\nlea eax, [rsi+rax-1]\ncdqe\ncmp dl, [rbx+rax]\njnz short loc_14C0\nadd edi, 1\nnop word ptr [rax+rax+00000000h]\nloc_14C0:\nadd r11, 1\nadd r10, 1\nloc_14C8:\nmov ecx, r8d\njmp loc_1270\nloc_14D0:\ntest r8d, r8d\njnz short loc_14C0\npop rbx\nmov eax, edi\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_14E0:\nxor ebp, ebp\nmov r9d, ecx\nmov r12d, edi\nmov r14d, 1\nsub r9d, ebp\npxor xmm0, xmm0\nlea r13d, [r9-1]\ncmp r13d, 6\nja loc_1366\nnop dword ptr [rax+rax+00h]\nloc_1508:\nmov edi, r12d\njmp loc_140A\nloc_1510:\nadd r11, 1\nadd r10, 1\nmov edi, r12d\njmp short loc_14C8\nloc_151D:\nxor edi, edi\npop rbx\npop rbp\nmov eax, edi\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v2; // eax\n int v3; // ecx\n const __m128i *v4; // r10\n __int64 v5; // r11\n unsigned int v6; // edi\n unsigned int v7; // edx\n __m128i v8; // xmm8\n __m128i v9; // xmm1\n const __m128i *v10; // rax\n __m128i v11; // xmm8\n __m128i v12; // xmm8\n __m128i v13; // xmm0\n __m128i v14; // xmm0\n __m128i v15; // xmm7\n __m128i v16; // xmm2\n __m128i v17; // xmm0\n __m128i v18; // xmm7\n __m128i v19; // xmm1\n __m128i v20; // xmm2\n __int64 v21; // rbp\n __m128i v22; // xmm0\n int v23; // r14d\n int v24; // eax\n __m128i v25; // xmm0\n unsigned int v26; // r12d\n int v27; // r9d\n unsigned int v28; // eax\n __m128i v29; // xmm2\n __m128i v30; // xmm1\n __m128i v31; // xmm2\n __m128i v32; // xmm1\n __m128i v33; // xmm2\n __m128i v34; // xmm0\n\n v2 = strlen(a1);\n if ( v2 > 0 )\n {\n v3 = v2;\n v4 = (const __m128i *)a1;\n v5 = 0LL;\n v6 = 0;\n while ( 1 )\n {\n v7 = v4->m128i_u8[0];\n if ( (unsigned int)(v3 - 1) <= 0xE )\n break;\n v8 = _mm_cvtsi32_si128(v7);\n v9 = 0LL;\n v10 = v4;\n v11 = _mm_unpacklo_epi8(v8, v8);\n v12 = _mm_shuffle_epi32(_mm_unpacklo_epi16(v11, v11), 0);\n do\n {\n v13 = _mm_loadu_si128(v10++);\n v14 = _mm_cmpeq_epi8(v13, v12);\n v15 = _mm_cmpgt_epi8((__m128i)0LL, v14);\n v16 = _mm_unpacklo_epi8(v14, v15);\n v17 = _mm_unpackhi_epi8(v14, v15);\n v18 = _mm_cmpgt_epi16((__m128i)0LL, v16);\n v19 = _mm_sub_epi32(_mm_sub_epi32(v9, _mm_unpacklo_epi16(v16, v18)), _mm_unpackhi_epi16(v16, v18));\n v20 = _mm_cmpgt_epi16((__m128i)0LL, v17);\n v9 = _mm_sub_epi32(_mm_sub_epi32(v19, _mm_unpacklo_epi16(v17, v20)), _mm_unpackhi_epi16(v17, v20));\n }\n while ( &v4[(unsigned int)v3 >> 4] != v10 );\n v21 = v3 & 0xFFFFFFF0;\n v22 = _mm_add_epi32(_mm_srli_si128(v9, 8), v9);\n v23 = v21 + 1;\n v24 = _mm_cvtsi128_si32(_mm_add_epi32(v22, _mm_srli_si128(v22, 4)));\n v25 = _mm_add_epi32(v9, _mm_srli_si128(v9, 8));\n v26 = v24 + v6;\n if ( (v3 & 0xF) != 0 )\n {\n v27 = v3 - v21;\n if ( (unsigned int)(v3 - v21 - 1) > 6 )\n goto LABEL_8;\nLABEL_34:\n v6 = v26;\n goto LABEL_9;\n }\n ++v5;\n v4 = (const __m128i *)((char *)v4 + 1);\n v6 += v24;\nLABEL_30:\n --v3;\n }\n v21 = 0LL;\n v26 = v6;\n v23 = 1;\n v27 = v3;\n v25 = 0LL;\n if ( (unsigned int)(v3 - 1) <= 6 )\n goto LABEL_34;\nLABEL_8:\n v28 = (unsigned __int8)v7;\n BYTE1(v28) = v4->m128i_i8[0];\n v29 = _mm_cmpeq_epi8(\n _mm_loadl_epi64((const __m128i *)&a1[v5 + v21]),\n _mm_shufflelo_epi16(_mm_cvtsi32_si128(v28), 0));\n v30 = _mm_unpacklo_epi8(v29, _mm_cmpgt_epi8((__m128i)0LL, v29));\n v31 = _mm_shuffle_epi32(v30, 78);\n v32 = _mm_unpacklo_epi16(v30, _mm_cmpgt_epi16((__m128i)0LL, v30));\n v33 = _mm_unpacklo_epi16(v31, _mm_cmpgt_epi16((__m128i)0LL, v31));\n v34 = _mm_sub_epi32(\n _mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(v25, v32), _mm_shuffle_epi32(v32, 78)), v33),\n _mm_shuffle_epi32(v33, 78));\n v6 += _mm_cvtsi128_si32(v34) + _mm_cvtsi128_si32(_mm_shuffle_epi32(v34, 229));\n v23 += v27 & 0xFFFFFFF8;\n if ( (v27 & 7) != 0 )\n {\nLABEL_9:\n if ( (_BYTE)v7 == a1[(int)v5 - 1 + v23] )\n ++v6;\n if ( v23 + 1 <= v3 )\n {\n if ( (_BYTE)v7 == a1[(int)v5 + v23] )\n ++v6;\n if ( v3 >= v23 + 2 )\n {\n if ( (_BYTE)v7 == a1[(int)v5 + 1 + v23] )\n ++v6;\n if ( v3 >= v23 + 3 )\n {\n if ( (_BYTE)v7 == a1[(int)v5 + 2 + v23] )\n ++v6;\n if ( v23 + 4 <= v3 )\n {\n if ( (_BYTE)v7 == a1[(int)v5 + 3 + v23] )\n ++v6;\n if ( v23 + 5 <= v3 )\n {\n if ( (_BYTE)v7 == a1[(int)v5 + 4 + v23] )\n ++v6;\n if ( v23 + 6 <= v3 && (_BYTE)v7 == a1[(int)v5 + 5 + v23] )\n ++v6;\n }\n }\n }\n }\nLABEL_29:\n ++v5;\n v4 = (const __m128i *)((char *)v4 + 1);\n goto LABEL_30;\n }\n }\n if ( v3 == 1 )\n return v6;\n goto LABEL_29;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1230:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\ncall _strlen\ntest eax, eax\njle loc_151D\nmov rcx, rax\nmov r10, rbx\nxor r11d, r11d\nxor edi, edi\npxor xmm6, xmm6\npxor xmm5, xmm5\npxor xmm4, xmm4\npxor xmm3, xmm3\nnop word ptr [rax+rax+00000000h]\nloc_1270:\nlea r8d, [rcx-1]\nmovzx edx, byte ptr [r10]\nmov esi, r11d\ncmp r8d, 0Eh\njbe loc_14E0\nmovd xmm8, edx\nmov r9d, ecx\npxor xmm1, xmm1\nmov rax, r10\npunpcklbw xmm8, xmm8\nshr r9d, 4\npunpcklwd xmm8, xmm8\nshl r9, 4\npshufd xmm8, xmm8, 0\nadd r9, r10\nnop\nloc_12B0:\nmovdqu xmm0, xmmword ptr [rax]\nmovdqa xmm7, xmm4\nadd rax, 10h\npcmpeqb xmm0, xmm8\npcmpgtb xmm7, xmm0\nmovdqa xmm2, xmm0\npunpcklbw xmm2, xmm7\npunpckhbw xmm0, xmm7\nmovdqa xmm7, xmm3\npcmpgtw xmm7, xmm2\nmovdqa xmm9, xmm2\npunpcklwd xmm9, xmm7\npunpckhwd xmm2, xmm7\nmovdqa xmm7, xmm0\npsubd xmm1, xmm9\npsubd xmm1, xmm2\nmovdqa xmm2, xmm3\npcmpgtw xmm2, xmm0\npunpcklwd xmm7, xmm2\npunpckhwd xmm0, xmm2\npsubd xmm1, xmm7\npsubd xmm1, xmm0\ncmp r9, rax\njnz short loc_12B0\nmovdqa xmm0, xmm1\nmov ebp, ecx\npsrldq xmm0, 8\nand ebp, 0FFFFFFF0h\npaddd xmm0, xmm1\nlea r14d, [rbp+1]\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\npaddd xmm0, xmm2\nmovd eax, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm1, 8\npaddd xmm0, xmm1\nlea r12d, [rax+rdi]\ntest cl, 0Fh\njz loc_1510\nmov r9d, ecx\nsub r9d, ebp\nlea r13d, [r9-1]\ncmp r13d, 6\njbe loc_1508\nloc_1366:\nlea r12, [rbx+r11]\nmovdqa xmm7, xmm6\nmovq xmm2, qword ptr [r12+rbp]\nmovzx ebp, dl\nmov eax, ebp\nmov ah, al\nmov ebp, eax\nmovd xmm1, ebp\npshuflw xmm1, xmm1, 0\npcmpeqb xmm2, xmm1\npcmpgtb xmm7, xmm2\nmovdqa xmm1, xmm2\npunpcklbw xmm1, xmm7\npunpcklbw xmm2, xmm7\nmovdqa xmm7, xmm5\npcmpgtw xmm7, xmm1\nmovdqa xmm8, xmm1\npshufd xmm2, xmm2, 4Eh ; 'N'\npunpcklwd xmm8, xmm7\npunpcklwd xmm1, xmm7\nmovdqa xmm7, xmm2\npsubd xmm0, xmm8\npshufd xmm1, xmm1, 4Eh ; 'N'\npsubd xmm0, xmm1\nmovdqa xmm1, xmm5\npcmpgtw xmm1, xmm2\npunpcklwd xmm7, xmm1\npunpcklwd xmm2, xmm1\npsubd xmm0, xmm7\npshufd xmm2, xmm2, 4Eh ; 'N'\npsubd xmm0, xmm2\nmovd r12d, xmm0\npshufd xmm1, xmm0, 0E5h\nmovd ebp, xmm1\nadd ebp, r12d\nadd edi, ebp\nmov ebp, r9d\nand ebp, 0FFFFFFF8h\nadd r14d, ebp\nand r9d, 7\njz loc_14D0\nloc_140A:\nlea r9d, [rsi+r14-1]\nmovsxd r9, r9d\ncmp dl, [rbx+r9]\njnz short loc_141B\nadd edi, 1\nloc_141B:\nlea r9d, [r14+1]\ncmp r9d, ecx\njg loc_14D0\nlea r9d, [rsi+r9-1]\nmovsxd r9, r9d\ncmp dl, [rbx+r9]\njnz short loc_1439\nadd edi, 1\nloc_1439:\nlea r9d, [r14+2]\ncmp ecx, r9d\njl short loc_14C0\nlea r9d, [rsi+r9-1]\nmovsxd r9, r9d\ncmp dl, [rbx+r9]\njnz short loc_1453\nadd edi, 1\nloc_1453:\nlea r9d, [r14+3]\ncmp ecx, r9d\njl short loc_14C0\nlea r9d, [rsi+r9-1]\nmovsxd r9, r9d\ncmp dl, [rbx+r9]\njnz short loc_146D\nadd edi, 1\nloc_146D:\nlea r9d, [r14+4]\ncmp r9d, ecx\njg short loc_14C0\nlea r9d, [rsi+r9-1]\nmovsxd r9, r9d\ncmp dl, [rbx+r9]\njnz short loc_1487\nadd edi, 1\nloc_1487:\nlea r9d, [r14+5]\ncmp r9d, ecx\njg short loc_14C0\nlea r9d, [rsi+r9-1]\nmovsxd r9, r9d\ncmp dl, [rbx+r9]\njnz short loc_14A1\nadd edi, 1\nloc_14A1:\nlea eax, [r14+6]\ncmp eax, ecx\njg short loc_14C0\nlea eax, [rsi+rax-1]\ncdqe\ncmp dl, [rbx+rax]\njnz short loc_14C0\nadd edi, 1\nnop word ptr [rax+rax+00000000h]\nloc_14C0:\nadd r11, 1\nadd r10, 1\nloc_14C8:\nmov ecx, r8d\njmp loc_1270\nloc_14D0:\ntest r8d, r8d\njnz short loc_14C0\npop rbx\nmov eax, edi\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_14E0:\nxor ebp, ebp\nmov r9d, ecx\nmov r12d, edi\nmov r14d, 1\nsub r9d, ebp\npxor xmm0, xmm0\nlea r13d, [r9-1]\ncmp r13d, 6\nja loc_1366\nnop dword ptr [rax+rax+00h]\nloc_1508:\nmov edi, r12d\njmp loc_140A\nloc_1510:\nadd r11, 1\nadd r10, 1\nmov edi, r12d\njmp short loc_14C8\nloc_151D:\nxor edi, edi\npop rbx\npop rbp\nmov eax, edi\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1230(const char *a1)\n{\n int v2; // eax\n int v3; // ecx\n const __m128i *v4; // r10\n __int64 v5; // r11\n unsigned int v6; // edi\n unsigned int v7; // edx\n __m128i v8; // xmm8\n __m128i v9; // xmm1\n const __m128i *v10; // rax\n __m128i v11; // xmm8\n __m128i v12; // xmm8\n __m128i v13; // xmm0\n __m128i v14; // xmm0\n __m128i v15; // xmm7\n __m128i v16; // xmm2\n __m128i v17; // xmm0\n __m128i v18; // xmm7\n __m128i v19; // xmm1\n __m128i v20; // xmm2\n __int64 v21; // rbp\n __m128i v22; // xmm0\n int v23; // r14d\n int v24; // eax\n __m128i v25; // xmm0\n unsigned int v26; // r12d\n int v27; // r9d\n unsigned int v28; // eax\n __m128i v29; // xmm2\n __m128i v30; // xmm1\n __m128i v31; // xmm2\n __m128i v32; // xmm1\n __m128i v33; // xmm2\n __m128i v34; // xmm0\n\n v2 = strlen(a1);\n if ( v2 > 0 )\n {\n v3 = v2;\n v4 = (const __m128i *)a1;\n v5 = 0LL;\n v6 = 0;\n while ( 1 )\n {\n v7 = v4->m128i_u8[0];\n if ( (unsigned int)(v3 - 1) <= 0xE )\n break;\n v8 = _mm_cvtsi32_si128(v7);\n v9 = 0LL;\n v10 = v4;\n v11 = _mm_unpacklo_epi8(v8, v8);\n v12 = _mm_shuffle_epi32(_mm_unpacklo_epi16(v11, v11), 0);\n do\n {\n v13 = _mm_loadu_si128(v10++);\n v14 = _mm_cmpeq_epi8(v13, v12);\n v15 = _mm_cmpgt_epi8((__m128i)0LL, v14);\n v16 = _mm_unpacklo_epi8(v14, v15);\n v17 = _mm_unpackhi_epi8(v14, v15);\n v18 = _mm_cmpgt_epi16((__m128i)0LL, v16);\n v19 = _mm_sub_epi32(_mm_sub_epi32(v9, _mm_unpacklo_epi16(v16, v18)), _mm_unpackhi_epi16(v16, v18));\n v20 = _mm_cmpgt_epi16((__m128i)0LL, v17);\n v9 = _mm_sub_epi32(_mm_sub_epi32(v19, _mm_unpacklo_epi16(v17, v20)), _mm_unpackhi_epi16(v17, v20));\n }\n while ( &v4[(unsigned int)v3 >> 4] != v10 );\n v21 = v3 & 0xFFFFFFF0;\n v22 = _mm_add_epi32(_mm_srli_si128(v9, 8), v9);\n v23 = v21 + 1;\n v24 = _mm_cvtsi128_si32(_mm_add_epi32(v22, _mm_srli_si128(v22, 4)));\n v25 = _mm_add_epi32(v9, _mm_srli_si128(v9, 8));\n v26 = v24 + v6;\n if ( (v3 & 0xF) != 0 )\n {\n v27 = v3 - v21;\n if ( (unsigned int)(v3 - v21 - 1) > 6 )\n goto LABEL_8;\nLABEL_34:\n v6 = v26;\n goto LABEL_9;\n }\n ++v5;\n v4 = (const __m128i *)((char *)v4 + 1);\n v6 += v24;\nLABEL_30:\n --v3;\n }\n v21 = 0LL;\n v26 = v6;\n v23 = 1;\n v27 = v3;\n v25 = 0LL;\n if ( (unsigned int)(v3 - 1) <= 6 )\n goto LABEL_34;\nLABEL_8:\n v28 = (unsigned __int8)v7;\n BYTE1(v28) = v4->m128i_i8[0];\n v29 = _mm_cmpeq_epi8(\n _mm_loadl_epi64((const __m128i *)&a1[v5 + v21]),\n _mm_shufflelo_epi16(_mm_cvtsi32_si128(v28), 0));\n v30 = _mm_unpacklo_epi8(v29, _mm_cmpgt_epi8((__m128i)0LL, v29));\n v31 = _mm_shuffle_epi32(v30, 78);\n v32 = _mm_unpacklo_epi16(v30, _mm_cmpgt_epi16((__m128i)0LL, v30));\n v33 = _mm_unpacklo_epi16(v31, _mm_cmpgt_epi16((__m128i)0LL, v31));\n v34 = _mm_sub_epi32(\n _mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(v25, v32), _mm_shuffle_epi32(v32, 78)), v33),\n _mm_shuffle_epi32(v33, 78));\n v6 += _mm_cvtsi128_si32(v34) + _mm_cvtsi128_si32(_mm_shuffle_epi32(v34, 229));\n v23 += v27 & 0xFFFFFFF8;\n if ( (v27 & 7) != 0 )\n {\nLABEL_9:\n if ( (_BYTE)v7 == a1[(int)v5 - 1 + v23] )\n ++v6;\n if ( v23 + 1 <= v3 )\n {\n if ( (_BYTE)v7 == a1[(int)v5 + v23] )\n ++v6;\n if ( v3 >= v23 + 2 )\n {\n if ( (_BYTE)v7 == a1[(int)v5 + 1 + v23] )\n ++v6;\n if ( v3 >= v23 + 3 )\n {\n if ( (_BYTE)v7 == a1[(int)v5 + 2 + v23] )\n ++v6;\n if ( v23 + 4 <= v3 )\n {\n if ( (_BYTE)v7 == a1[(int)v5 + 3 + v23] )\n ++v6;\n if ( v23 + 5 <= v3 )\n {\n if ( (_BYTE)v7 == a1[(int)v5 + 4 + v23] )\n ++v6;\n if ( v23 + 6 <= v3 && (_BYTE)v7 == a1[(int)v5 + 5 + v23] )\n ++v6;\n }\n }\n }\n }\nLABEL_29:\n ++v5;\n v4 = (const __m128i *)((char *)v4 + 1);\n goto LABEL_30;\n }\n }\n if ( v3 == 1 )\n return v6;\n goto LABEL_29;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1230(const char *a1) {\n int v2;\n int v3;\n const __m128i *v4;\n long long v5;\n unsigned int v6;\n unsigned int v7;\n __m128i v8;\n __m128i v9;\n const __m128i *v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n __m128i v15;\n __m128i v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n __m128i v20;\n long long v21;\n __m128i v22;\n int v23;\n int v24;\n __m128i v25;\n unsigned int v26;\n int v27;\n unsigned int v28;\n __m128i v29;\n __m128i v30;\n __m128i v31;\n __m128i v32;\n __m128i v33;\n __m128i v34;\n v2 = strlen(a1);\n if (v2 > 0) {\n v3 = v2;\n v4 = (const __m128i *)a1;\n v5 = 0LL;\n v6 = 0;\n while (1) {\n v7 = v4->m128i_u8[0];\n if ((unsigned int)(v3 - 1) <= 14) break;\n v8 = _mm_cvtsi32_si128(v7);\n v9 = 0LL;\n v10 = v4;\n v11 = _mm_unpacklo_epi8(v8, v8);\n v12 = _mm_shuffle_epi32(_mm_unpacklo_epi16(v11, v11), 0);\n do {\n v13 = _mm_loadu_si128(v10++);\n v14 = _mm_cmpeq_epi8(v13, v12);\n v15 = _mm_cmpgt_epi8((__m128i)0LL, v14);\n v16 = _mm_unpacklo_epi8(v14, v15);\n v17 = _mm_unpackhi_epi8(v14, v15);\n v18 = _mm_cmpgt_epi16((__m128i)0LL, v16);\n v19 = _mm_sub_epi32(_mm_sub_epi32(v9, _mm_unpacklo_epi16(v16, v18)),\n _mm_unpackhi_epi16(v16, v18));\n v20 = _mm_cmpgt_epi16((__m128i)0LL, v17);\n v9 = _mm_sub_epi32(_mm_sub_epi32(v19, _mm_unpacklo_epi16(v17, v20)),\n _mm_unpackhi_epi16(v17, v20));\n } while (&v4[(unsigned int)v3 >> 4] != v10);\n v21 = v3 & 4294967280;\n v22 = _mm_add_epi32(_mm_srli_si128(v9, 8), v9);\n v23 = v21 + 1;\n v24 = _mm_cvtsi128_si32(_mm_add_epi32(v22, _mm_srli_si128(v22, 4)));\n v25 = _mm_add_epi32(v9, _mm_srli_si128(v9, 8));\n v26 = v24 + v6;\n if ((v3 & 15) != 0) {\n v27 = v3 - v21;\n if ((unsigned int)(v3 - v21 - 1) > 6) goto LABEL_8;\n LABEL_34:\n v6 = v26;\n goto LABEL_9;\n }\n ++v5;\n v4 = (const __m128i *)((char *)v4 + 1);\n v6 += v24;\n LABEL_30:\n --v3;\n }\n v21 = 0LL;\n v26 = v6;\n v23 = 1;\n v27 = v3;\n v25 = 0LL;\n if ((unsigned int)(v3 - 1) <= 6) goto LABEL_34;\n LABEL_8:\n v28 = (unsigned char)v7;\n BYTE1(v28) = v4->m128i_i8[0];\n v29 = _mm_cmpeq_epi8(_mm_loadl_epi64((const __m128i *)&a1[v5 + v21]),\n _mm_shufflelo_epi16(_mm_cvtsi32_si128(v28), 0));\n v30 = _mm_unpacklo_epi8(v29, _mm_cmpgt_epi8((__m128i)0LL, v29));\n v31 = _mm_shuffle_epi32(v30, 78);\n v32 = _mm_unpacklo_epi16(v30, _mm_cmpgt_epi16((__m128i)0LL, v30));\n v33 = _mm_unpacklo_epi16(v31, _mm_cmpgt_epi16((__m128i)0LL, v31));\n v34 = _mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(v25, v32),\n _mm_shuffle_epi32(v32, 78)),\n v33),\n _mm_shuffle_epi32(v33, 78));\n v6 +=\n _mm_cvtsi128_si32(v34) + _mm_cvtsi128_si32(_mm_shuffle_epi32(v34, 229));\n v23 += v27 & 4294967288;\n if ((v27 & 7) != 0) {\n LABEL_9:\n if ((uint8_t)v7 == a1[(int)v5 - 1 + v23]) ++v6;\n if (v23 + 1 <= v3) {\n if ((uint8_t)v7 == a1[(int)v5 + v23]) ++v6;\n if (v3 >= v23 + 2) {\n if ((uint8_t)v7 == a1[(int)v5 + 1 + v23]) ++v6;\n if (v3 >= v23 + 3) {\n if ((uint8_t)v7 == a1[(int)v5 + 2 + v23]) ++v6;\n if (v23 + 4 <= v3) {\n if ((uint8_t)v7 == a1[(int)v5 + 3 + v23]) ++v6;\n if (v23 + 5 <= v3) {\n if ((uint8_t)v7 == a1[(int)v5 + 4 + v23]) ++v6;\n if (v23 + 6 <= v3 && (uint8_t)v7 == a1[(int)v5 + 5 + v23]) ++v6;\n }\n }\n }\n }\n LABEL_29:\n ++v5;\n v4 = (const __m128i *)((char *)v4 + 1);\n goto LABEL_30;\n }\n }\n if (v3 == 1) return v6;\n goto LABEL_29;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v2;\n int v3;\n const __m128i *v4;\n long long v5;\n unsigned int v6;\n unsigned int v7;\n __m128i v8;\n __m128i v9;\n const __m128i *v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n __m128i v15;\n __m128i v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n __m128i v20;\n long long v21;\n __m128i v22;\n int v23;\n int v24;\n __m128i v25;\n unsigned int v26;\n int v27;\n unsigned int v28;\n __m128i v29;\n __m128i v30;\n __m128i v31;\n __m128i v32;\n __m128i v33;\n __m128i v34;\n v2 = strlen(a1);\n if (v2 > 0) {\n v3 = v2;\n v4 = (const __m128i *)a1;\n v5 = 0LL;\n v6 = 0;\n while (1) {\n v7 = v4->m128i_u8[0];\n if ((unsigned int)(v3 - 1) <= 14) break;\n v8 = _mm_cvtsi32_si128(v7);\n v9 = 0LL;\n v10 = v4;\n v11 = _mm_unpacklo_epi8(v8, v8);\n v12 = _mm_shuffle_epi32(_mm_unpacklo_epi16(v11, v11), 0);\n do {\n v13 = _mm_loadu_si128(v10++);\n v14 = _mm_cmpeq_epi8(v13, v12);\n v15 = _mm_cmpgt_epi8((__m128i)0LL, v14);\n v16 = _mm_unpacklo_epi8(v14, v15);\n v17 = _mm_unpackhi_epi8(v14, v15);\n v18 = _mm_cmpgt_epi16((__m128i)0LL, v16);\n v19 = _mm_sub_epi32(_mm_sub_epi32(v9, _mm_unpacklo_epi16(v16, v18)),\n _mm_unpackhi_epi16(v16, v18));\n v20 = _mm_cmpgt_epi16((__m128i)0LL, v17);\n v9 = _mm_sub_epi32(_mm_sub_epi32(v19, _mm_unpacklo_epi16(v17, v20)),\n _mm_unpackhi_epi16(v17, v20));\n } while (&v4[(unsigned int)v3 >> 4] != v10);\n v21 = v3 & 4294967280;\n v22 = _mm_add_epi32(_mm_srli_si128(v9, 8), v9);\n v23 = v21 + 1;\n v24 = _mm_cvtsi128_si32(_mm_add_epi32(v22, _mm_srli_si128(v22, 4)));\n v25 = _mm_add_epi32(v9, _mm_srli_si128(v9, 8));\n v26 = v24 + v6;\n if ((v3 & 15) != 0) {\n v27 = v3 - v21;\n if ((unsigned int)(v3 - v21 - 1) > 6) goto LABEL_8;\n LABEL_34:\n v6 = v26;\n goto LABEL_9;\n }\n ++v5;\n v4 = (const __m128i *)((char *)v4 + 1);\n v6 += v24;\n LABEL_30:\n --v3;\n }\n v21 = 0LL;\n v26 = v6;\n v23 = 1;\n v27 = v3;\n v25 = 0LL;\n if ((unsigned int)(v3 - 1) <= 6) goto LABEL_34;\n LABEL_8:\n v28 = (unsigned char)v7;\n BYTE1(v28) = v4->m128i_i8[0];\n v29 = _mm_cmpeq_epi8(_mm_loadl_epi64((const __m128i *)&a1[v5 + v21]),\n _mm_shufflelo_epi16(_mm_cvtsi32_si128(v28), 0));\n v30 = _mm_unpacklo_epi8(v29, _mm_cmpgt_epi8((__m128i)0LL, v29));\n v31 = _mm_shuffle_epi32(v30, 78);\n v32 = _mm_unpacklo_epi16(v30, _mm_cmpgt_epi16((__m128i)0LL, v30));\n v33 = _mm_unpacklo_epi16(v31, _mm_cmpgt_epi16((__m128i)0LL, v31));\n v34 = _mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(v25, v32),\n _mm_shuffle_epi32(v32, 78)),\n v33),\n _mm_shuffle_epi32(v33, 78));\n v6 +=\n _mm_cvtsi128_si32(v34) + _mm_cvtsi128_si32(_mm_shuffle_epi32(v34, 229));\n v23 += v27 & 4294967288;\n if ((v27 & 7) != 0) {\n LABEL_9:\n if ((uint8_t)v7 == a1[(int)v5 - 1 + v23]) ++v6;\n if (v23 + 1 <= v3) {\n if ((uint8_t)v7 == a1[(int)v5 + v23]) ++v6;\n if (v3 >= v23 + 2) {\n if ((uint8_t)v7 == a1[(int)v5 + 1 + v23]) ++v6;\n if (v3 >= v23 + 3) {\n if ((uint8_t)v7 == a1[(int)v5 + 2 + v23]) ++v6;\n if (v23 + 4 <= v3) {\n if ((uint8_t)v7 == a1[(int)v5 + 3 + v23]) ++v6;\n if (v23 + 5 <= v3) {\n if ((uint8_t)v7 == a1[(int)v5 + 4 + v23]) ++v6;\n if (v23 + 6 <= v3 && (uint8_t)v7 == a1[(int)v5 + 5 + v23]) ++v6;\n }\n }\n }\n }\n LABEL_29:\n ++v5;\n v4 = (const __m128i *)((char *)v4 + 1);\n goto LABEL_30;\n }\n }\n if (v3 == 1) return v6;\n goto LABEL_29;\n }\n return 0LL;\n}" + }, + { + "index": 339, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int x, int y) {\n if (x == y) {\n return y;\n }\n return 2;\n}", + "test": "int main() {\n\n assert(func0(2,2) == 2);\n\n assert(func0(2,5) == 2);\n\n assert(func0(5,10) == 2);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov %esi,-0x8(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x8(%rbp),%eax\njne 1164 \nmov -0x8(%rbp),%eax\njmp 1169 \nmov $0x2,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_8]\njnz short loc_1164\nmov eax, [rbp+var_8]\njmp short loc_1169\nloc_1164:\nmov eax, 2\nloc_1169:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, unsigned int a2)\n{\n if ( a1 == a2 )\n return a2;\n else\n return 2LL;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_8]\njnz short loc_1164\nmov eax, [rbp+var_8]\njmp short loc_1169\nloc_1164:\nmov eax, 2\nloc_1169:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, unsigned int a2)\n{\n if ( a1 == a2 )\n return a2;\n else\n return 2LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, unsigned int a2) {\n if (a1 == a2)\n return a2;\n else\n return 2LL;\n}", + "ida_pseudo_norm": "long long func0(int a1, unsigned int a2) {\n if (a1 == a2)\n return a2;\n else\n return 2LL;\n}" + }, + { + "index": 340, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint compare(const void * a, const void * b) {\n\n return (*(int*)a - *(int*)b);\n\n}\n\n\n\n", + "func": "int func0(int lst[], int size) {\n int positive_numbers[size];\n int count = 0;\n for (int i = 0; i < size; i++) {\n if (lst[i] > 0) {\n positive_numbers[count++] = lst[i];\n }\n }\n qsort(positive_numbers, count, sizeof(int), compare);\n int sum = 0;\n for (int i = 0; i < 3 && i < count; i++) {\n sum += positive_numbers[i];\n }\n return sum;\n}", + "test": "int main() {\n\n int arr1[] = {10, 20, 30, 40, 50, 60, 7};\n\n int arr2[] = {1, 2, 3, 4, 5};\n\n int arr3[] = {0, 1, 2, 3, 4, 5};\n\n \n\n assert(func0(arr1, 7) == 37);\n\n assert(func0(arr2, 5) == 6);\n\n assert(func0(arr3, 6) == 6);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x48,%rsp\nmov %rdi,-0x48(%rbp)\nmov %esi,-0x4c(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmov %rsp,%rax\nmov %rax,%rbx\nmov -0x4c(%rbp),%eax\nmovslq %eax,%rdx\nsub $0x1,%rdx\nmov %rdx,-0x28(%rbp)\nmovslq %eax,%rdx\nmov %rdx,%r10\nmov $0x0,%r11d\nmovslq %eax,%rdx\nmov %rdx,%r8\nmov $0x0,%r9d\ncltq\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%esi\nmov $0x0,%edx\ndiv %rsi\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rdi\nsub %rdx,%rdi\nmov %rdi,%rdx\ncmp %rdx,%rsp\nje 124b \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 1234 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 1275 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x20(%rbp)\nmovl $0x0,-0x2c(%rbp)\nmovl $0x0,-0x30(%rbp)\njmp 12df \nmov -0x30(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ntest %eax,%eax\njle 12db \nmov -0x30(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x48(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x2c(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x2c(%rbp)\nmov (%rcx),%ecx\nmov -0x20(%rbp),%rdx\ncltq\nmov %ecx,(%rdx,%rax,4)\naddl $0x1,-0x30(%rbp)\nmov -0x30(%rbp),%eax\ncmp -0x4c(%rbp),%eax\njl 1298 \nmov -0x2c(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x20(%rbp),%rax\nlea -0x16f(%rip),%rcx\nmov $0x4,%edx\nmov %rax,%rdi\ncallq 1070 \nmovl $0x0,-0x34(%rbp)\nmovl $0x0,-0x38(%rbp)\njmp 1329 \nmov -0x20(%rbp),%rax\nmov -0x38(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nadd %eax,-0x34(%rbp)\naddl $0x1,-0x38(%rbp)\ncmpl $0x2,-0x38(%rbp)\njg 1337 \nmov -0x38(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 1315 \nmov -0x34(%rbp),%eax\nmov %rbx,%rsp\nmov -0x18(%rbp),%rbx\nxor %fs:0x28,%rbx\nje 1351 \ncallq 1080 <__stack_chk_fail@plt>\nmov -0x8(%rbp),%rbx\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 48h\nmov [rbp+var_48], rdi\nmov [rbp+var_4C], esi\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov rax, rsp\nmov rbx, rax\nmov eax, [rbp+var_4C]\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_28], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_1219:\ncmp rsp, rdx\njz short loc_1230\nsub rsp, 1000h\nor [rsp+1050h+var_58], 0\njmp short loc_1219\nloc_1230:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_125A\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_125A:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+base], rax\nmov [rbp+var_38], 0\nmov [rbp+var_34], 0\njmp short loc_12C4\nloc_127D:\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njle short loc_12C0\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_38]\nlea edx, [rax+1]\nmov [rbp+var_38], edx\nmov ecx, [rcx]\nmov rdx, [rbp+base]\ncdqe\nmov [rdx+rax*4], ecx\nloc_12C0:\nadd [rbp+var_34], 1\nloc_12C4:\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_4C]\njl short loc_127D\nmov eax, [rbp+var_38]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compare\nmov rcx, rdx; compar\nmov edx, 4; size\nmov rdi, rax; base\ncall _qsort\nmov [rbp+var_30], 0\nmov [rbp+var_2C], 0\njmp short loc_1311\nloc_12FD:\nmov rax, [rbp+base]\nmov edx, [rbp+var_2C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nadd [rbp+var_30], eax\nadd [rbp+var_2C], 1\nloc_1311:\ncmp [rbp+var_2C], 2\njg short loc_131F\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_38]\njl short loc_12FD\nloc_131F:\nmov eax, [rbp+var_30]\nmov rsp, rbx\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njz short loc_1339\ncall ___stack_chk_fail\nloc_1339:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned __int64 v2; // rax\n void *v3; // rsp\n int v4; // eax\n _BYTE v6[4]; // [rsp+8h] [rbp-50h] BYREF\n int v7; // [rsp+Ch] [rbp-4Ch]\n __int64 v8; // [rsp+10h] [rbp-48h]\n int v9; // [rsp+20h] [rbp-38h]\n int i; // [rsp+24h] [rbp-34h]\n unsigned int v11; // [rsp+28h] [rbp-30h]\n int j; // [rsp+2Ch] [rbp-2Ch]\n __int64 v13; // [rsp+30h] [rbp-28h]\n void *base; // [rsp+38h] [rbp-20h]\n unsigned __int64 v15; // [rsp+40h] [rbp-18h]\n\n v8 = a1;\n v7 = a2;\n v15 = __readfsqword(0x28u);\n v13 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 0x10uLL);\n while ( v6 != &v6[-(v2 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = alloca(v2 & 0xFFF);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)&v6[(v2 & 0xFFF) - 8] = *(_QWORD *)&v6[(v2 & 0xFFF) - 8];\n base = v6;\n v9 = 0;\n for ( i = 0; i < v7; ++i )\n {\n if ( *(int *)(4LL * i + v8) > 0 )\n {\n v4 = v9++;\n *((_DWORD *)base + v4) = *(_DWORD *)(4LL * i + v8);\n }\n }\n qsort(base, v9, 4uLL, compare);\n v11 = 0;\n for ( j = 0; j <= 2 && j < v9; ++j )\n v11 += *((_DWORD *)base + j);\n return v11;\n}", + "ida_strip_asm": "sub_11AB:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 48h\nmov [rbp+var_48], rdi\nmov [rbp+var_4C], esi\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov rax, rsp\nmov rbx, rax\nmov eax, [rbp+var_4C]\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_28], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_1219:\ncmp rsp, rdx\njz short loc_1230\nsub rsp, 1000h\nor [rsp+1050h+var_58], 0\njmp short loc_1219\nloc_1230:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_125A\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_125A:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+base], rax\nmov [rbp+var_38], 0\nmov [rbp+var_34], 0\njmp short loc_12C4\nloc_127D:\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njle short loc_12C0\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_38]\nlea edx, [rax+1]\nmov [rbp+var_38], edx\nmov ecx, [rcx]\nmov rdx, [rbp+base]\ncdqe\nmov [rdx+rax*4], ecx\nloc_12C0:\nadd [rbp+var_34], 1\nloc_12C4:\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_4C]\njl short loc_127D\nmov eax, [rbp+var_38]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 4; size\nmov rdi, rax; base\ncall _qsort\nmov [rbp+var_30], 0\nmov [rbp+var_2C], 0\njmp short loc_1311\nloc_12FD:\nmov rax, [rbp+base]\nmov edx, [rbp+var_2C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nadd [rbp+var_30], eax\nadd [rbp+var_2C], 1\nloc_1311:\ncmp [rbp+var_2C], 2\njg short loc_131F\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_38]\njl short loc_12FD\nloc_131F:\nmov eax, [rbp+var_30]\nmov rsp, rbx\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njz short loc_1339\ncall ___stack_chk_fail\nloc_1339:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11AB(__int64 a1, int a2)\n{\n unsigned __int64 v2; // rax\n void *v3; // rsp\n int v4; // eax\n _BYTE v6[4]; // [rsp+8h] [rbp-50h] BYREF\n int v7; // [rsp+Ch] [rbp-4Ch]\n __int64 v8; // [rsp+10h] [rbp-48h]\n int v9; // [rsp+20h] [rbp-38h]\n int i; // [rsp+24h] [rbp-34h]\n unsigned int v11; // [rsp+28h] [rbp-30h]\n int j; // [rsp+2Ch] [rbp-2Ch]\n __int64 v13; // [rsp+30h] [rbp-28h]\n void *base; // [rsp+38h] [rbp-20h]\n unsigned __int64 v15; // [rsp+40h] [rbp-18h]\n\n v8 = a1;\n v7 = a2;\n v15 = __readfsqword(0x28u);\n v13 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 0x10uLL);\n while ( v6 != &v6[-(v2 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = alloca(v2 & 0xFFF);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)&v6[(v2 & 0xFFF) - 8] = *(_QWORD *)&v6[(v2 & 0xFFF) - 8];\n base = v6;\n v9 = 0;\n for ( i = 0; i < v7; ++i )\n {\n if ( *(int *)(4LL * i + v8) > 0 )\n {\n v4 = v9++;\n *((_DWORD *)base + v4) = *(_DWORD *)(4LL * i + v8);\n }\n }\n qsort(base, v9, 4uLL, compar);\n v11 = 0;\n for ( j = 0; j <= 2 && j < v9; ++j )\n v11 += *((_DWORD *)base + j);\n return v11;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11AB(long long a1, int a2) {\n unsigned long long v2;\n void *v3;\n int v4;\n uint8_t v6[4];\n int v7;\n long long v8;\n int v9;\n int i;\n unsigned int v11;\n int j;\n long long v13;\n void *base;\n unsigned long long v15;\n v8 = a1;\n v7 = a2;\n v15 = __readfsqword(40u);\n v13 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 16uLL);\n while (v6 != &v6[-(v2 & 18446744073709547520LL)])\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)&v6[(v2 & 4095) - 8] = *(uint64_t *)&v6[(v2 & 4095) - 8];\n base = v6;\n v9 = 0;\n for (i = 0; i < v7; ++i) {\n if (*(int *)(4LL * i + v8) > 0) {\n v4 = v9++;\n *((uint32_t *)base + v4) = *(uint32_t *)(4LL * i + v8);\n }\n }\n qsort(base, v9, 4uLL, compar);\n v11 = 0;\n for (j = 0; j <= 2 && j < v9; ++j) v11 += *((uint32_t *)base + j);\n return v11;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned long long v2;\n void *v3;\n int v4;\n uint8_t v6[4];\n int v7;\n long long v8;\n int v9;\n int i;\n unsigned int v11;\n int j;\n long long v13;\n void *base;\n unsigned long long v15;\n v8 = a1;\n v7 = a2;\n v15 = __readfsqword(40u);\n v13 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 16uLL);\n while (v6 != &v6[-(v2 & 18446744073709547520LL)])\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)&v6[(v2 & 4095) - 8] = *(uint64_t *)&v6[(v2 & 4095) - 8];\n base = v6;\n v9 = 0;\n for (i = 0; i < v7; ++i) {\n if (*(int *)(4LL * i + v8) > 0) {\n v4 = v9++;\n *((uint32_t *)base + v4) = *(uint32_t *)(4LL * i + v8);\n }\n }\n qsort(base, v9, 4uLL, compare);\n v11 = 0;\n for (j = 0; j <= 2 && j < v9; ++j) v11 += *((uint32_t *)base + j);\n return v11;\n}" + }, + { + "index": 340, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint compare(const void * a, const void * b) {\n\n return (*(int*)a - *(int*)b);\n\n}\n\n\n\n", + "func": "int func0(int lst[], int size) {\n int positive_numbers[size];\n int count = 0;\n for (int i = 0; i < size; i++) {\n if (lst[i] > 0) {\n positive_numbers[count++] = lst[i];\n }\n }\n qsort(positive_numbers, count, sizeof(int), compare);\n int sum = 0;\n for (int i = 0; i < 3 && i < count; i++) {\n sum += positive_numbers[i];\n }\n return sum;\n}", + "test": "int main() {\n\n int arr1[] = {10, 20, 30, 40, 50, 60, 7};\n\n int arr2[] = {1, 2, 3, 4, 5};\n\n int arr3[] = {0, 1, 2, 3, 4, 5};\n\n \n\n assert(func0(arr1, 7) == 37);\n\n assert(func0(arr2, 5) == 6);\n\n assert(func0(arr3, 6) == 6);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r12\npush %rbx\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmovslq %esi,%rax\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffffff0,%rdx\nand $0xfffffffffffff000,%rax\nmov %rsp,%rbx\nsub %rax,%rbx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 11e8 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11d1 \nmov %rdx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 11fe \norq $0x0,-0x8(%rsp,%rax,1)\nmov %rsp,%r8\nmov %r8,%r12\ntest %esi,%esi\njle 1293 \nmov %rdi,%rax\nlea -0x1(%rsi),%edx\nlea 0x4(%rdi,%rdx,4),%rsi\nmov $0x0,%ebx\njmp 1227 \nadd $0x4,%rax\ncmp %rsi,%rax\nje 1239 \nmov (%rax),%edx\ntest %edx,%edx\njle 121e \nmovslq %ebx,%rcx\nmov %edx,(%r12,%rcx,4)\nlea 0x1(%rbx),%ebx\njmp 121e \nmovslq %ebx,%rsi\nlea -0xba(%rip),%rcx\nmov $0x4,%edx\nmov %r8,%rdi\ncallq 1070 \ntest %ebx,%ebx\njle 128c \nmov $0x1,%eax\nmov $0x0,%ecx\nadd -0x4(%r12,%rax,4),%ecx\nmov %eax,%edx\nadd $0x1,%rax\ncmp $0x2,%edx\njg 1272 \ncmp %edx,%ebx\njg 125e \nmov -0x18(%rbp),%rax\nxor %fs:0x28,%rax\njne 12b3 \nmov %ecx,%eax\nlea -0x10(%rbp),%rsp\npop %rbx\npop %r12\npop %rbp\nretq\nmov $0x0,%ecx\njmp 1272 \nlea -0x111(%rip),%rcx\nmov $0x4,%edx\nmov $0x0,%esi\nmov %r8,%rdi\ncallq 1070 \nmov $0x0,%ecx\njmp 1272 \ncallq 1080 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r12\npush rbx\nsub rsp, 10h\nmov rcx, rdi\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmovsxd rdx, esi\nshl rdx, 2\nlea rax, [rdx+0Fh]\nmov r8, rax\nand r8, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdi, rsp\nsub rdi, rax\nloc_11D1:\ncmp rsp, rdi\njz short loc_11E8\nsub rsp, 1000h\nor [rsp+1020h+var_28], 0\njmp short loc_11D1\nloc_11E8:\nmov rax, r8\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11FE\nor [rsp+rax+20h+var_28], 0\nloc_11FE:\nmov r12, rsp\ntest esi, esi\njle loc_128B\nmov rax, rcx\nadd rcx, rdx\nmov ebx, 0\njmp short loc_1229\nloc_1216:\nmovsxd rsi, ebx\nmov [r12+rsi*4], edx\nlea ebx, [rbx+1]\nloc_1220:\nadd rax, 4\ncmp rax, rcx\njz short loc_1231\nloc_1229:\nmov edx, [rax]\ntest edx, edx\njg short loc_1216\njmp short loc_1220\nloc_1231:\nmovsxd rsi, ebx; nmemb\nlea rcx, compare; compar\nmov edx, 4; size\nmov rdi, r12; base\ncall _qsort\ntest ebx, ebx\njle short loc_1284\nmov eax, 1\nmov ecx, 0\nloc_1256:\nadd ecx, [r12+rax*4-4]\nmov edx, eax\nadd rax, 1\ncmp edx, 2\njg short loc_126A\ncmp ebx, edx\njg short loc_1256\nloc_126A:\nmov rax, [rbp+var_18]\nsub rax, fs:28h\njnz short loc_12AB\nmov eax, ecx\nlea rsp, [rbp-10h]\npop rbx\npop r12\npop rbp\nretn\nloc_1284:\nmov ecx, 0\njmp short loc_126A\nloc_128B:\nlea rcx, compare; compar\nmov edx, 4; size\nmov esi, 0; nmemb\nmov rdi, r12; base\ncall _qsort\nmov ecx, 0\njmp short loc_126A\nloc_12AB:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n __int64 v2; // rdx\n signed __int64 v3; // rax\n void *v4; // rsp\n _DWORD *v5; // rax\n int v6; // ebx\n __int64 v7; // rax\n unsigned int v8; // ecx\n int v9; // edx\n _DWORD v12[2]; // [rsp+8h] [rbp-20h] BYREF\n unsigned __int64 v13; // [rsp+10h] [rbp-18h]\n\n v13 = __readfsqword(0x28u);\n v2 = 4LL * a2;\n while ( v12 != (_DWORD *)((char *)v12 - ((v2 + 15) & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v3 = ((_WORD)v2 + 15) & 0xFF0;\n v4 = alloca(v3);\n if ( (((_WORD)v2 + 15) & 0xFF0) != 0 )\n *(_QWORD *)((char *)&v12[-2] + v3) = *(_QWORD *)((char *)&v12[-2] + v3);\n if ( a2 <= 0 )\n {\n qsort(v12, 0LL, 4uLL, compare);\n return 0;\n }\n else\n {\n v5 = a1;\n v6 = 0;\n do\n {\n if ( (int)*v5 > 0 )\n v12[v6++] = *v5;\n ++v5;\n }\n while ( v5 != &a1[(unsigned __int64)v2 / 4] );\n qsort(v12, v6, 4uLL, compare);\n if ( v6 <= 0 )\n {\n return 0;\n }\n else\n {\n v7 = 1LL;\n v8 = 0;\n do\n {\n v8 += v12[v7 - 1];\n v9 = v7++;\n }\n while ( v9 <= 2 && v6 > v9 );\n }\n }\n return v8;\n}", + "ida_strip_asm": "sub_1192:\nendbr64\npush rbp\nmov rbp, rsp\npush r12\npush rbx\nsub rsp, 10h\nmov rcx, rdi\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmovsxd rdx, esi\nshl rdx, 2\nlea rax, [rdx+0Fh]\nmov r8, rax\nand r8, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdi, rsp\nsub rdi, rax\nloc_11D1:\ncmp rsp, rdi\njz short loc_11E8\nsub rsp, 1000h\nor [rsp+1020h+var_28], 0\njmp short loc_11D1\nloc_11E8:\nmov rax, r8\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11FE\nor [rsp+rax+20h+var_28], 0\nloc_11FE:\nmov r12, rsp\ntest esi, esi\njle loc_128B\nmov rax, rcx\nadd rcx, rdx\nmov ebx, 0\njmp short loc_1229\nloc_1216:\nmovsxd rsi, ebx\nmov [r12+rsi*4], edx\nlea ebx, [rbx+1]\nloc_1220:\nadd rax, 4\ncmp rax, rcx\njz short loc_1231\nloc_1229:\nmov edx, [rax]\ntest edx, edx\njg short loc_1216\njmp short loc_1220\nloc_1231:\nmovsxd rsi, ebx; nmemb\nlea rcx, compar; compar\nmov edx, 4; size\nmov rdi, r12; base\ncall _qsort\ntest ebx, ebx\njle short loc_1284\nmov eax, 1\nmov ecx, 0\nloc_1256:\nadd ecx, [r12+rax*4-4]\nmov edx, eax\nadd rax, 1\ncmp edx, 2\njg short loc_126A\ncmp ebx, edx\njg short loc_1256\nloc_126A:\nmov rax, [rbp+var_18]\nsub rax, fs:28h\njnz short loc_12AB\nmov eax, ecx\nlea rsp, [rbp-10h]\npop rbx\npop r12\npop rbp\nretn\nloc_1284:\nmov ecx, 0\njmp short loc_126A\nloc_128B:\nlea rcx, compar; compar\nmov edx, 4; size\nmov esi, 0; nmemb\nmov rdi, r12; base\ncall _qsort\nmov ecx, 0\njmp short loc_126A\nloc_12AB:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1192(_DWORD *a1, int a2)\n{\n __int64 v2; // rdx\n signed __int64 v3; // rax\n void *v4; // rsp\n _DWORD *v5; // rax\n int v6; // ebx\n __int64 v7; // rax\n unsigned int v8; // ecx\n int v9; // edx\n _DWORD v12[2]; // [rsp+8h] [rbp-20h] BYREF\n unsigned __int64 v13; // [rsp+10h] [rbp-18h]\n\n v13 = __readfsqword(0x28u);\n v2 = 4LL * a2;\n while ( v12 != (_DWORD *)((char *)v12 - ((v2 + 15) & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v3 = ((_WORD)v2 + 15) & 0xFF0;\n v4 = alloca(v3);\n if ( (((_WORD)v2 + 15) & 0xFF0) != 0 )\n *(_QWORD *)((char *)&v12[-2] + v3) = *(_QWORD *)((char *)&v12[-2] + v3);\n if ( a2 <= 0 )\n {\n qsort(v12, 0LL, 4uLL, compar);\n return 0;\n }\n else\n {\n v5 = a1;\n v6 = 0;\n do\n {\n if ( (int)*v5 > 0 )\n v12[v6++] = *v5;\n ++v5;\n }\n while ( v5 != &a1[(unsigned __int64)v2 / 4] );\n qsort(v12, v6, 4uLL, compar);\n if ( v6 <= 0 )\n {\n return 0;\n }\n else\n {\n v7 = 1LL;\n v8 = 0;\n do\n {\n v8 += v12[v7 - 1];\n v9 = v7++;\n }\n while ( v9 <= 2 && v6 > v9 );\n }\n }\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1192(uint32_t *a1, int a2) {\n long long v2;\n signed long long v3;\n void *v4;\n uint32_t *v5;\n int v6;\n long long v7;\n unsigned int v8;\n int v9;\n uint32_t v12[2];\n unsigned long long v13;\n v13 = __readfsqword(40u);\n v2 = 4LL * a2;\n while (v12 !=\n (uint32_t *)((char *)v12 - ((v2 + 15) & 18446744073709547520LL)))\n ;\n v3 = ((unsigned short)v2 + 15) & 4080;\n v4 = alloca(v3);\n if ((((unsigned short)v2 + 15) & 4080) != 0)\n *(uint64_t *)((char *)&v12[-2] + v3) = *(uint64_t *)((char *)&v12[-2] + v3);\n if (a2 <= 0) {\n qsort(v12, 0LL, 4uLL, compar);\n return 0;\n } else {\n v5 = a1;\n v6 = 0;\n do {\n if ((int)*v5 > 0) v12[v6++] = *v5;\n ++v5;\n } while (v5 != &a1[(unsigned long long)v2 / 4]);\n qsort(v12, v6, 4uLL, compar);\n if (v6 <= 0) {\n return 0;\n } else {\n v7 = 1LL;\n v8 = 0;\n do {\n v8 += v12[v7 - 1];\n v9 = v7++;\n } while (v9 <= 2 && v6 > v9);\n }\n }\n return v8;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n long long v2;\n signed long long v3;\n void *v4;\n uint32_t *v5;\n int v6;\n long long v7;\n unsigned int v8;\n int v9;\n uint32_t v12[2];\n unsigned long long v13;\n v13 = __readfsqword(40u);\n v2 = 4LL * a2;\n while (v12 !=\n (uint32_t *)((char *)v12 - ((v2 + 15) & 18446744073709547520LL)))\n ;\n v3 = ((unsigned short)v2 + 15) & 4080;\n v4 = alloca(v3);\n if ((((unsigned short)v2 + 15) & 4080) != 0)\n *(uint64_t *)((char *)&v12[-2] + v3) = *(uint64_t *)((char *)&v12[-2] + v3);\n if (a2 <= 0) {\n qsort(v12, 0LL, 4uLL, compare);\n return 0;\n } else {\n v5 = a1;\n v6 = 0;\n do {\n if ((int)*v5 > 0) v12[v6++] = *v5;\n ++v5;\n } while (v5 != &a1[(unsigned long long)v2 / 4]);\n qsort(v12, v6, 4uLL, compare);\n if (v6 <= 0) {\n return 0;\n } else {\n v7 = 1LL;\n v8 = 0;\n do {\n v8 += v12[v7 - 1];\n v9 = v7++;\n } while (v9 <= 2 && v6 > v9);\n }\n }\n return v8;\n}" + }, + { + "index": 340, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint compare(const void * a, const void * b) {\n\n return (*(int*)a - *(int*)b);\n\n}\n\n\n\n", + "func": "int func0(int lst[], int size) {\n int positive_numbers[size];\n int count = 0;\n for (int i = 0; i < size; i++) {\n if (lst[i] > 0) {\n positive_numbers[count++] = lst[i];\n }\n }\n qsort(positive_numbers, count, sizeof(int), compare);\n int sum = 0;\n for (int i = 0; i < 3 && i < count; i++) {\n sum += positive_numbers[i];\n }\n return sum;\n}", + "test": "int main() {\n\n int arr1[] = {10, 20, 30, 40, 50, 60, 7};\n\n int arr2[] = {1, 2, 3, 4, 5};\n\n int arr3[] = {0, 1, 2, 3, 4, 5};\n\n \n\n assert(func0(arr1, 7) == 37);\n\n assert(func0(arr2, 5) == 6);\n\n assert(func0(arr3, 6) == 6);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r12\npush %rbx\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmovslq %esi,%rax\nmov %rsp,%rcx\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rcx\nand $0xfffffffffffffff0,%rdx\nmov %rcx,%rax\ncmp %rax,%rsp\nje 1359 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 1344 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 1410 \nmov %rsp,%r12\ntest %esi,%esi\njle 13eb \nlea -0x1(%rsi),%eax\nxor %ebx,%ebx\nlea 0x4(%rdi,%rax,4),%rcx\nnopl 0x0(%rax)\nmov (%rdi),%eax\ntest %eax,%eax\njle 1390 \nmovslq %ebx,%rdx\nadd $0x1,%ebx\nmov %eax,(%r12,%rdx,4)\nadd $0x4,%rdi\ncmp %rcx,%rdi\njne 1380 \nmovslq %ebx,%rsi\nlea -0xb3(%rip),%rcx\nmov $0x4,%edx\nmov %r12,%rdi\ncallq 1070 \ntest %ebx,%ebx\nje 1401 \nmov $0x1,%eax\nxor %r8d,%r8d\nmov %eax,%edx\nadd -0x4(%r12,%rax,4),%r8d\nadd $0x1,%rax\ncmp $0x2,%edx\njg 13d0 \ncmp %edx,%ebx\njg 13bc \nmov -0x18(%rbp),%rax\nxor %fs:0x28,%rax\njne 141b \nlea -0x10(%rbp),%rsp\nmov %r8d,%eax\npop %rbx\npop %r12\npop %rbp\nretq\nlea -0x102(%rip),%rcx\nmov $0x4,%edx\nxor %esi,%esi\nmov %r12,%rdi\ncallq 1070 \nxor %r8d,%r8d\njmp 13d0 \nnopw %cs:0x0(%rax,%rax,1)\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 136b \ncallq 1080 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmovsxd rdx, esi\nshl rdx, 2\nmov rbp, rsp\npush r12\npush rbx\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nlea rax, [rdx+0Fh]\nmov r8, rsp\nmov rcx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub r8, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, r8\njz short loc_1316\nloc_1301:\nsub rsp, 1000h\nor [rsp+1020h+var_28], 0\ncmp rsp, r8\njnz short loc_1301\nloc_1316:\nand ecx, 0FFFh\nsub rsp, rcx\ntest rcx, rcx\njnz loc_13B0\nloc_1328:\nmov r12, rsp\ntest esi, esi\njle loc_13BB\nadd rdx, rdi\nxor ebx, ebx\nnop dword ptr [rax+rax+00000000h]\nloc_1340:\nmov eax, [rdi]\ntest eax, eax\njle short loc_1350\nmovsxd rcx, ebx\nadd ebx, 1\nmov [r12+rcx*4], eax\nloc_1350:\nadd rdi, 4\ncmp rdi, rdx\njnz short loc_1340\nmovsxd rsi, ebx; nmemb\nlea rcx, compare; compar\nmov edx, 4; size\nmov rdi, r12; base\ncall _qsort\ntest ebx, ebx\njle short loc_13D1\nmov eax, 1\nxor ecx, ecx\nloc_137B:\nmov edx, eax\nadd ecx, [r12+rax*4-4]\nadd rax, 1\ncmp edx, 2\njg short loc_138F\ncmp ebx, edx\njg short loc_137B\nloc_138F:\nmov rax, [rbp+var_18]\nsub rax, fs:28h\njnz short loc_13D5\nlea rsp, [rbp-10h]\nmov eax, ecx\npop rbx\npop r12\npop rbp\nretn\nloc_13B0:\nor [rsp+rcx+1020h+var_1028], 0\njmp loc_1328\nloc_13BB:\nlea rcx, compare; compar\nmov edx, 4; size\nxor esi, esi; nmemb\nmov rdi, r12; base\ncall _qsort\nloc_13D1:\nxor ecx, ecx\njmp short loc_138F\nloc_13D5:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n __int64 v2; // rdx\n _DWORD *v3; // r8\n signed __int64 v4; // rcx\n void *v5; // rsp\n _DWORD *v6; // rdx\n int v7; // ebx\n __int64 v8; // rcx\n __int64 v9; // rax\n unsigned int v10; // ecx\n int v11; // edx\n _DWORD v14[1022]; // [rsp+8h] [rbp-1020h] BYREF\n _QWORD v15[4]; // [rsp+1008h] [rbp-20h] BYREF\n\n v2 = 4LL * a2;\n v15[1] = __readfsqword(0x28u);\n v3 = (_DWORD *)((char *)v15 - ((v2 + 15) & 0xFFFFFFFFFFFFF000LL));\n if ( v15 != (_QWORD *)v3 )\n {\n while ( v14 != v3 )\n ;\n }\n v4 = ((_WORD)v2 + 15) & 0xFF0;\n v5 = alloca(v4);\n if ( (((_WORD)v2 + 15) & 0xFF0) != 0 )\n *(_QWORD *)((char *)&v14[-2] + v4) = *(_QWORD *)((char *)&v14[-2] + v4);\n if ( a2 <= 0 )\n {\n qsort(v14, 0LL, 4uLL, compare);\n return 0;\n }\n v6 = &a1[(unsigned __int64)v2 / 4];\n v7 = 0;\n do\n {\n if ( (int)*a1 > 0 )\n {\n v8 = v7++;\n v14[v8] = *a1;\n }\n ++a1;\n }\n while ( a1 != v6 );\n qsort(v14, v7, 4uLL, compare);\n if ( v7 <= 0 )\n return 0;\n v9 = 1LL;\n v10 = 0;\n do\n {\n v11 = v9;\n v10 += v14[v9++ - 1];\n }\n while ( v11 <= 2 && v7 > v11 );\n return v10;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\npush rbp\nmovsxd rdx, esi\nshl rdx, 2\nmov rbp, rsp\npush r12\npush rbx\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nlea rax, [rdx+0Fh]\nmov r8, rsp\nmov rcx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub r8, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, r8\njz short loc_1316\nloc_1301:\nsub rsp, 1000h\nor [rsp+1020h+var_28], 0\ncmp rsp, r8\njnz short loc_1301\nloc_1316:\nand ecx, 0FFFh\nsub rsp, rcx\ntest rcx, rcx\njnz loc_13B0\nloc_1328:\nmov r12, rsp\ntest esi, esi\njle loc_13BB\nadd rdx, rdi\nxor ebx, ebx\nnop dword ptr [rax+rax+00000000h]\nloc_1340:\nmov eax, [rdi]\ntest eax, eax\njle short loc_1350\nmovsxd rcx, ebx\nadd ebx, 1\nmov [r12+rcx*4], eax\nloc_1350:\nadd rdi, 4\ncmp rdi, rdx\njnz short loc_1340\nmovsxd rsi, ebx; nmemb\nlea rcx, compar; compar\nmov edx, 4; size\nmov rdi, r12; base\ncall _qsort\ntest ebx, ebx\njle short loc_13D1\nmov eax, 1\nxor ecx, ecx\nloc_137B:\nmov edx, eax\nadd ecx, [r12+rax*4-4]\nadd rax, 1\ncmp edx, 2\njg short loc_138F\ncmp ebx, edx\njg short loc_137B\nloc_138F:\nmov rax, [rbp+var_18]\nsub rax, fs:28h\njnz short loc_13D5\nlea rsp, [rbp-10h]\nmov eax, ecx\npop rbx\npop r12\npop rbp\nretn\nloc_13B0:\nor [rsp+rcx+1020h+var_1028], 0\njmp loc_1328\nloc_13BB:\nlea rcx, compar; compar\nmov edx, 4; size\nxor esi, esi; nmemb\nmov rdi, r12; base\ncall _qsort\nloc_13D1:\nxor ecx, ecx\njmp short loc_138F\nloc_13D5:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12C0(_DWORD *a1, int a2)\n{\n __int64 v2; // rdx\n _DWORD *v3; // r8\n signed __int64 v4; // rcx\n void *v5; // rsp\n _DWORD *v6; // rdx\n int v7; // ebx\n __int64 v8; // rcx\n __int64 v9; // rax\n unsigned int v10; // ecx\n int v11; // edx\n _DWORD v14[1022]; // [rsp+8h] [rbp-1020h] BYREF\n _QWORD v15[4]; // [rsp+1008h] [rbp-20h] BYREF\n\n v2 = 4LL * a2;\n v15[1] = __readfsqword(0x28u);\n v3 = (_DWORD *)((char *)v15 - ((v2 + 15) & 0xFFFFFFFFFFFFF000LL));\n if ( v15 != (_QWORD *)v3 )\n {\n while ( v14 != v3 )\n ;\n }\n v4 = ((_WORD)v2 + 15) & 0xFF0;\n v5 = alloca(v4);\n if ( (((_WORD)v2 + 15) & 0xFF0) != 0 )\n *(_QWORD *)((char *)&v14[-2] + v4) = *(_QWORD *)((char *)&v14[-2] + v4);\n if ( a2 <= 0 )\n {\n qsort(v14, 0LL, 4uLL, compar);\n return 0;\n }\n v6 = &a1[(unsigned __int64)v2 / 4];\n v7 = 0;\n do\n {\n if ( (int)*a1 > 0 )\n {\n v8 = v7++;\n v14[v8] = *a1;\n }\n ++a1;\n }\n while ( a1 != v6 );\n qsort(v14, v7, 4uLL, compar);\n if ( v7 <= 0 )\n return 0;\n v9 = 1LL;\n v10 = 0;\n do\n {\n v11 = v9;\n v10 += v14[v9++ - 1];\n }\n while ( v11 <= 2 && v7 > v11 );\n return v10;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12C0(uint32_t *a1, int a2) {\n long long v2;\n uint32_t *v3;\n signed long long v4;\n void *v5;\n uint32_t *v6;\n int v7;\n long long v8;\n long long v9;\n unsigned int v10;\n int v11;\n uint32_t v14[1022];\n uint64_t v15[4];\n v2 = 4LL * a2;\n v15[1] = __readfsqword(40u);\n v3 = (uint32_t *)((char *)v15 - ((v2 + 15) & 18446744073709547520LL));\n if (v15 != (uint64_t *)v3) {\n while (v14 != v3)\n ;\n }\n v4 = ((unsigned short)v2 + 15) & 4080;\n v5 = alloca(v4);\n if ((((unsigned short)v2 + 15) & 4080) != 0)\n *(uint64_t *)((char *)&v14[-2] + v4) = *(uint64_t *)((char *)&v14[-2] + v4);\n if (a2 <= 0) {\n qsort(v14, 0LL, 4uLL, compar);\n return 0;\n }\n v6 = &a1[(unsigned long long)v2 / 4];\n v7 = 0;\n do {\n if ((int)*a1 > 0) {\n v8 = v7++;\n v14[v8] = *a1;\n }\n ++a1;\n } while (a1 != v6);\n qsort(v14, v7, 4uLL, compar);\n if (v7 <= 0) return 0;\n v9 = 1LL;\n v10 = 0;\n do {\n v11 = v9;\n v10 += v14[v9++ - 1];\n } while (v11 <= 2 && v7 > v11);\n return v10;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n long long v2;\n uint32_t *v3;\n signed long long v4;\n void *v5;\n uint32_t *v6;\n int v7;\n long long v8;\n long long v9;\n unsigned int v10;\n int v11;\n uint32_t v14[1022];\n uint64_t v15[4];\n v2 = 4LL * a2;\n v15[1] = __readfsqword(40u);\n v3 = (uint32_t *)((char *)v15 - ((v2 + 15) & 18446744073709547520LL));\n if (v15 != (uint64_t *)v3) {\n while (v14 != v3)\n ;\n }\n v4 = ((unsigned short)v2 + 15) & 4080;\n v5 = alloca(v4);\n if ((((unsigned short)v2 + 15) & 4080) != 0)\n *(uint64_t *)((char *)&v14[-2] + v4) = *(uint64_t *)((char *)&v14[-2] + v4);\n if (a2 <= 0) {\n qsort(v14, 0LL, 4uLL, compare);\n return 0;\n }\n v6 = &a1[(unsigned long long)v2 / 4];\n v7 = 0;\n do {\n if ((int)*a1 > 0) {\n v8 = v7++;\n v14[v8] = *a1;\n }\n ++a1;\n } while (a1 != v6);\n qsort(v14, v7, 4uLL, compare);\n if (v7 <= 0) return 0;\n v9 = 1LL;\n v10 = 0;\n do {\n v11 = v9;\n v10 += v14[v9++ - 1];\n } while (v11 <= 2 && v7 > v11);\n return v10;\n}" + }, + { + "index": 340, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint compare(const void * a, const void * b) {\n\n return (*(int*)a - *(int*)b);\n\n}\n\n\n\n", + "func": "int func0(int lst[], int size) {\n int positive_numbers[size];\n int count = 0;\n for (int i = 0; i < size; i++) {\n if (lst[i] > 0) {\n positive_numbers[count++] = lst[i];\n }\n }\n qsort(positive_numbers, count, sizeof(int), compare);\n int sum = 0;\n for (int i = 0; i < 3 && i < count; i++) {\n sum += positive_numbers[i];\n }\n return sum;\n}", + "test": "int main() {\n\n int arr1[] = {10, 20, 30, 40, 50, 60, 7};\n\n int arr2[] = {1, 2, 3, 4, 5};\n\n int arr3[] = {0, 1, 2, 3, 4, 5};\n\n \n\n assert(func0(arr1, 7) == 37);\n\n assert(func0(arr2, 5) == 6);\n\n assert(func0(arr3, 6) == 6);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r12\npush %rbx\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmovslq %esi,%rax\nmov %rsp,%rcx\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rcx\nand $0xfffffffffffffff0,%rdx\nmov %rcx,%rax\ncmp %rax,%rsp\nje 1319 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 1304 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 13e0 \nlea 0x3(%rsp),%r8\nmov %r8,%r12\nand $0xfffffffffffffffc,%r8\nshr $0x2,%r12\ntest %esi,%esi\njle 13be \nlea -0x1(%rsi),%eax\nxor %ebx,%ebx\nlea 0x4(%rdi,%rax,4),%rcx\nnopl 0x0(%rax)\nmov (%rdi),%eax\ntest %eax,%eax\njle 1360 \nmovslq %ebx,%rdx\nadd $0x1,%ebx\nmov %eax,(%r8,%rdx,4)\nadd $0x4,%rdi\ncmp %rcx,%rdi\njne 1350 \nmovslq %ebx,%rsi\nlea -0xc3(%rip),%rcx\nmov $0x4,%edx\nmov %r8,%rdi\ncallq 1070 \ntest %ebx,%ebx\nje 13d4 \nmov 0x0(,%r12,4),%eax\ncmp $0x1,%ebx\njle 13a6 \nadd 0x4(,%r12,4),%eax\ncmp $0x2,%ebx\njle 13a6 \nadd 0x8(,%r12,4),%eax\nmov -0x18(%rbp),%rsi\nxor %fs:0x28,%rsi\njne 13eb \nlea -0x10(%rbp),%rsp\npop %rbx\npop %r12\npop %rbp\nretq\nlea -0x115(%rip),%rcx\nmov $0x4,%edx\nxor %esi,%esi\nmov %r8,%rdi\ncallq 1070 \nxor %eax,%eax\njmp 13a6 \nnopl 0x0(%rax,%rax,1)\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 132b \ncallq 1080 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmovsxd rcx, esi\nmov rax, rdi\nshl rcx, 2\nmov rbp, rsp\npush r12\npush rbx\nsub rsp, 10h\nmov rdx, fs:28h\nmov [rbp+var_18], rdx\nxor edx, edx\nlea rdx, [rcx+0Fh]\nmov r8, rsp\nmov rdi, rdx\nand rdx, 0FFFFFFFFFFFFF000h\nsub r8, rdx\nand rdi, 0FFFFFFFFFFFFFFF0h\ncmp rsp, r8\njz short loc_131A\nloc_1305:\nsub rsp, 1000h\nor [rsp+1020h+var_28], 0\ncmp rsp, r8\njnz short loc_1305\nloc_131A:\nand edi, 0FFFh\nsub rsp, rdi\ntest rdi, rdi\njnz loc_13C0\nloc_132C:\nlea rdi, [rsp+1020h+var_101D]\nmov rbx, rdi\nand rdi, 0FFFFFFFFFFFFFFFCh; base\nshr rbx, 2\ntest esi, esi\njle loc_13CB\nadd rcx, rax\nxor r12d, r12d\nnop word ptr [rax+rax+00h]\nloc_1350:\nmov edx, [rax]\ntest edx, edx\njle short loc_1360\nmovsxd rsi, r12d\nadd r12d, 1\nmov [rdi+rsi*4], edx\nloc_1360:\nadd rax, 4\ncmp rcx, rax\njnz short loc_1350\nmovsxd rsi, r12d; nmemb\nlea rcx, compare; compar\nmov edx, 4; size\ncall _qsort\ntest r12d, r12d\njle short loc_13DE\nmov eax, ds:dword_0[rbx*4]\ncmp r12d, 1\njz short loc_13A3\nadd eax, dword ptr ds:byte_4[rbx*4]\ncmp r12d, 2\njz short loc_13A3\nadd eax, dword ptr ds:byte_8[rbx*4]\nloc_13A3:\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njnz short loc_13E2\nlea rsp, [rbp-10h]\npop rbx\npop r12\npop rbp\nretn\nloc_13C0:\nor [rsp+rdi+1020h+var_1028], 0\njmp loc_132C\nloc_13CB:\nlea rcx, compare; compar\nmov edx, 4; size\nxor esi, esi; nmemb\ncall _qsort\nloc_13DE:\nxor eax, eax\njmp short loc_13A3\nloc_13E2:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n __int64 v3; // rcx\n _DWORD *v4; // r8\n signed __int64 v5; // rdi\n void *v6; // rsp\n _DWORD *v7; // rcx\n int v8; // r12d\n __int64 v9; // rsi\n __int64 result; // rax\n _DWORD v12[1022]; // [rsp+8h] [rbp-1020h] BYREF\n _QWORD v13[4]; // [rsp+1008h] [rbp-20h] BYREF\n\n v3 = 4LL * a2;\n v13[1] = __readfsqword(0x28u);\n v4 = (_DWORD *)((char *)v13 - ((v3 + 15) & 0xFFFFFFFFFFFFF000LL));\n if ( v13 != (_QWORD *)v4 )\n {\n while ( v12 != v4 )\n ;\n }\n v5 = ((_WORD)v3 + 15) & 0xFF0;\n v6 = alloca(v5);\n if ( (((_WORD)v3 + 15) & 0xFF0) != 0 )\n *(_QWORD *)((char *)&v12[-2] + v5) = *(_QWORD *)((char *)&v12[-2] + v5);\n if ( a2 <= 0 )\n {\n qsort(v12, 0LL, 4uLL, compare);\n return 0LL;\n }\n v7 = &a1[(unsigned __int64)v3 / 4];\n v8 = 0;\n do\n {\n if ( (int)*a1 > 0 )\n {\n v9 = v8++;\n v12[v9] = *a1;\n }\n ++a1;\n }\n while ( v7 != a1 );\n qsort(v12, v8, 4uLL, compare);\n if ( v8 <= 0 )\n return 0LL;\n result = v12[0];\n if ( v8 != 1 )\n {\n result = (unsigned int)(v12[1] + v12[0]);\n if ( v8 != 2 )\n return (unsigned int)(v12[2] + result);\n }\n return result;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\npush rbp\nmovsxd rcx, esi\nmov rax, rdi\nshl rcx, 2\nmov rbp, rsp\npush r12\npush rbx\nsub rsp, 10h\nmov rdx, fs:28h\nmov [rbp+var_18], rdx\nxor edx, edx\nlea rdx, [rcx+0Fh]\nmov r8, rsp\nmov rdi, rdx\nand rdx, 0FFFFFFFFFFFFF000h\nsub r8, rdx\nand rdi, 0FFFFFFFFFFFFFFF0h\ncmp rsp, r8\njz short loc_131A\nloc_1305:\nsub rsp, 1000h\nor [rsp+1020h+var_28], 0\ncmp rsp, r8\njnz short loc_1305\nloc_131A:\nand edi, 0FFFh\nsub rsp, rdi\ntest rdi, rdi\njnz loc_13C0\nloc_132C:\nlea rdi, [rsp+1020h+var_101D]\nmov rbx, rdi\nand rdi, 0FFFFFFFFFFFFFFFCh; base\nshr rbx, 2\ntest esi, esi\njle loc_13CB\nadd rcx, rax\nxor r12d, r12d\nnop word ptr [rax+rax+00h]\nloc_1350:\nmov edx, [rax]\ntest edx, edx\njle short loc_1360\nmovsxd rsi, r12d\nadd r12d, 1\nmov [rdi+rsi*4], edx\nloc_1360:\nadd rax, 4\ncmp rcx, rax\njnz short loc_1350\nmovsxd rsi, r12d; nmemb\nlea rcx, compar; compar\nmov edx, 4; size\ncall _qsort\ntest r12d, r12d\njle short loc_13DE\nmov eax, ds:dword_0[rbx*4]\ncmp r12d, 1\njz short loc_13A3\nadd eax, dword ptr ds:byte_4[rbx*4]\ncmp r12d, 2\njz short loc_13A3\nadd eax, dword ptr ds:byte_8[rbx*4]\nloc_13A3:\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njnz short loc_13E2\nlea rsp, [rbp-10h]\npop rbx\npop r12\npop rbp\nretn\nloc_13C0:\nor [rsp+rdi+1020h+var_1028], 0\njmp loc_132C\nloc_13CB:\nlea rcx, compar; compar\nmov edx, 4; size\nxor esi, esi; nmemb\ncall _qsort\nloc_13DE:\nxor eax, eax\njmp short loc_13A3\nloc_13E2:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12C0(_DWORD *a1, int a2)\n{\n __int64 v3; // rcx\n _DWORD *v4; // r8\n signed __int64 v5; // rdi\n void *v6; // rsp\n _DWORD *v7; // rcx\n int v8; // r12d\n __int64 v9; // rsi\n __int64 result; // rax\n _DWORD v12[1022]; // [rsp+8h] [rbp-1020h] BYREF\n _QWORD v13[4]; // [rsp+1008h] [rbp-20h] BYREF\n\n v3 = 4LL * a2;\n v13[1] = __readfsqword(0x28u);\n v4 = (_DWORD *)((char *)v13 - ((v3 + 15) & 0xFFFFFFFFFFFFF000LL));\n if ( v13 != (_QWORD *)v4 )\n {\n while ( v12 != v4 )\n ;\n }\n v5 = ((_WORD)v3 + 15) & 0xFF0;\n v6 = alloca(v5);\n if ( (((_WORD)v3 + 15) & 0xFF0) != 0 )\n *(_QWORD *)((char *)&v12[-2] + v5) = *(_QWORD *)((char *)&v12[-2] + v5);\n if ( a2 <= 0 )\n {\n qsort(v12, 0LL, 4uLL, compar);\n return 0LL;\n }\n v7 = &a1[(unsigned __int64)v3 / 4];\n v8 = 0;\n do\n {\n if ( (int)*a1 > 0 )\n {\n v9 = v8++;\n v12[v9] = *a1;\n }\n ++a1;\n }\n while ( v7 != a1 );\n qsort(v12, v8, 4uLL, compar);\n if ( v8 <= 0 )\n return 0LL;\n result = v12[0];\n if ( v8 != 1 )\n {\n result = (unsigned int)(v12[1] + v12[0]);\n if ( v8 != 2 )\n return (unsigned int)(v12[2] + result);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12C0(uint32_t *a1, int a2) {\n long long v3;\n uint32_t *v4;\n signed long long v5;\n void *v6;\n uint32_t *v7;\n int v8;\n long long v9;\n long long result;\n uint32_t v12[1022];\n uint64_t v13[4];\n v3 = 4LL * a2;\n v13[1] = __readfsqword(40u);\n v4 = (uint32_t *)((char *)v13 - ((v3 + 15) & 18446744073709547520LL));\n if (v13 != (uint64_t *)v4) {\n while (v12 != v4)\n ;\n }\n v5 = ((unsigned short)v3 + 15) & 4080;\n v6 = alloca(v5);\n if ((((unsigned short)v3 + 15) & 4080) != 0)\n *(uint64_t *)((char *)&v12[-2] + v5) = *(uint64_t *)((char *)&v12[-2] + v5);\n if (a2 <= 0) {\n qsort(v12, 0LL, 4uLL, compar);\n return 0LL;\n }\n v7 = &a1[(unsigned long long)v3 / 4];\n v8 = 0;\n do {\n if ((int)*a1 > 0) {\n v9 = v8++;\n v12[v9] = *a1;\n }\n ++a1;\n } while (v7 != a1);\n qsort(v12, v8, 4uLL, compar);\n if (v8 <= 0) return 0LL;\n result = v12[0];\n if (v8 != 1) {\n result = (unsigned int)(v12[1] + v12[0]);\n if (v8 != 2) return (unsigned int)(v12[2] + result);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n long long v3;\n uint32_t *v4;\n signed long long v5;\n void *v6;\n uint32_t *v7;\n int v8;\n long long v9;\n long long result;\n uint32_t v12[1022];\n uint64_t v13[4];\n v3 = 4LL * a2;\n v13[1] = __readfsqword(40u);\n v4 = (uint32_t *)((char *)v13 - ((v3 + 15) & 18446744073709547520LL));\n if (v13 != (uint64_t *)v4) {\n while (v12 != v4)\n ;\n }\n v5 = ((unsigned short)v3 + 15) & 4080;\n v6 = alloca(v5);\n if ((((unsigned short)v3 + 15) & 4080) != 0)\n *(uint64_t *)((char *)&v12[-2] + v5) = *(uint64_t *)((char *)&v12[-2] + v5);\n if (a2 <= 0) {\n qsort(v12, 0LL, 4uLL, compare);\n return 0LL;\n }\n v7 = &a1[(unsigned long long)v3 / 4];\n v8 = 0;\n do {\n if ((int)*a1 > 0) {\n v9 = v8++;\n v12[v9] = *a1;\n }\n ++a1;\n } while (v7 != a1);\n qsort(v12, v8, 4uLL, compare);\n if (v8 <= 0) return 0LL;\n result = v12[0];\n if (v8 != 1) {\n result = (unsigned int)(v12[1] + v12[0]);\n if (v8 != 2) return (unsigned int)(v12[2] + result);\n }\n return result;\n}" + }, + { + "index": 341, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\nint cmpfunc (const void * a, const void * b) {\n\n return ( *(int*)a - *(int*)b );\n\n}\n\n\n\n", + "func": "void func0(int arr[], int n, int result[]) {\n qsort(arr, n, sizeof(int), cmpfunc);\n for (int i = 0; i < n; i++) {\n result[i] = arr[i];\n }\n}", + "test": "int main() {\n\n int result[5];\n\n\n\n int set1[] = {1, 2, 3, 4, 5};\n\n func0(set1, 5, result);\n\n assert(result[0] == 1 && result[1] == 2 && result[2] == 3 && result[3] == 4 && result[4] == 5);\n\n\n\n int set2[] = {6, 7, 8, 9, 10, 11};\n\n func0(set2, 6, result);\n\n assert(result[0] == 6 && result[1] == 7 && result[2] == 8 && result[3] == 9 && result[4] == 10 && result[5] == 11);\n\n\n\n int set3[] = {12, 13, 14, 15, 16};\n\n func0(set3, 5, result);\n\n assert(result[0] == 12 && result[1] == 13 && result[2] == 14 && result[3] == 15 && result[4] == 16);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmov -0x1c(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x18(%rbp),%rax\nlea -0x4a(%rip),%rcx\nmov $0x4,%edx\nmov %rax,%rdi\ncallq 1070 \nmovl $0x0,-0x4(%rbp)\njmp 121a \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0x4(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x28(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11e9 \nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+base], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov eax, [rbp+var_1C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, cmpfunc\nmov rcx, rdx; compar\nmov edx, 4; size\nmov rdi, rax; base\ncall _qsort\nmov [rbp+var_4], 0\njmp short loc_121D\nloc_11EC:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_4], 1\nloc_121D:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11EC\nnop\nnop\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(void *a1, int a2, __int64 a3)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+2Ch] [rbp-4h]\n\n qsort(a1, a2, 4uLL, cmpfunc);\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a2 )\n break;\n *(_DWORD *)(4LL * (int)i + a3) = *((_DWORD *)a1 + (int)i);\n }\n return result;\n}", + "ida_strip_asm": "sub_11AB:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+base], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov eax, [rbp+var_1C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 4; size\nmov rdi, rax; base\ncall _qsort\nmov [rbp+var_4], 0\njmp short loc_121D\nloc_11EC:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_4], 1\nloc_121D:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11EC\nnop\nnop\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11AB(void *a1, int a2, __int64 a3)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+2Ch] [rbp-4h]\n\n qsort(a1, a2, 4uLL, compar);\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a2 )\n break;\n *(_DWORD *)(4LL * (int)i + a3) = *((_DWORD *)a1 + (int)i);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11AB(void *a1, int a2, long long a3) {\n long long result;\n unsigned int i;\n qsort(a1, a2, 4uLL, compar);\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a2) break;\n *(uint32_t *)(4LL * (int)i + a3) = *((uint32_t *)a1 + (int)i);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(void *a1, int a2, long long a3) {\n long long result;\n unsigned int i;\n qsort(a1, a2, 4uLL, cmpfunc);\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a2) break;\n *(uint32_t *)(4LL * (int)i + a3) = *((uint32_t *)a1 + (int)i);\n }\n return result;\n}" + }, + { + "index": 341, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\nint cmpfunc (const void * a, const void * b) {\n\n return ( *(int*)a - *(int*)b );\n\n}\n\n\n\n", + "func": "void func0(int arr[], int n, int result[]) {\n qsort(arr, n, sizeof(int), cmpfunc);\n for (int i = 0; i < n; i++) {\n result[i] = arr[i];\n }\n}", + "test": "int main() {\n\n int result[5];\n\n\n\n int set1[] = {1, 2, 3, 4, 5};\n\n func0(set1, 5, result);\n\n assert(result[0] == 1 && result[1] == 2 && result[2] == 3 && result[3] == 4 && result[4] == 5);\n\n\n\n int set2[] = {6, 7, 8, 9, 10, 11};\n\n func0(set2, 6, result);\n\n assert(result[0] == 6 && result[1] == 7 && result[2] == 8 && result[3] == 9 && result[4] == 10 && result[5] == 11);\n\n\n\n int set3[] = {12, 13, 14, 15, 16};\n\n func0(set3, 5, result);\n\n assert(result[0] == 12 && result[1] == 13 && result[2] == 14 && result[3] == 15 && result[4] == 16);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nmov %esi,%r12d\nmov %rdx,%rbp\nmovslq %esi,%rsi\nlea -0x24(%rip),%rcx\nmov $0x4,%edx\ncallq 1070 \ntest %r12d,%r12d\njle 11d9 \nlea -0x1(%r12),%ecx\nmov $0x0,%eax\nmov (%rbx,%rax,4),%edx\nmov %edx,0x0(%rbp,%rax,4)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rcx,%rdx\njne 11c6 \npop %rbx\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov r13d, esi\nmov r12, rdx\nmovsxd rbp, esi\nlea rcx, cmpfunc; compar\nmov edx, 4; size\nmov rsi, rbp; nmemb\ncall _qsort\ntest r13d, r13d\njle short loc_11E2\nlea rcx, ds:0[rbp*4]\nmov eax, 0\nloc_11D2:\nmov edx, [rbx+rax]\nmov [r12+rax], edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_11D2\nloc_11E2:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "void __fastcall func0(char *a1, int a2, __int64 a3)\n{\n __int64 v4; // rax\n\n qsort(a1, a2, 4uLL, cmpfunc);\n if ( a2 > 0 )\n {\n v4 = 0LL;\n do\n {\n *(_DWORD *)(a3 + v4) = *(_DWORD *)&a1[v4];\n v4 += 4LL;\n }\n while ( v4 != 4LL * a2 );\n }\n}", + "ida_strip_asm": "sub_1192:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov r13d, esi\nmov r12, rdx\nmovsxd rbp, esi\nlea rcx, compar; compar\nmov edx, 4; size\nmov rsi, rbp; nmemb\ncall _qsort\ntest r13d, r13d\njle short loc_11E2\nlea rcx, ds:0[rbp*4]\nmov eax, 0\nloc_11D2:\nmov edx, [rbx+rax]\nmov [r12+rax], edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_11D2\nloc_11E2:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "void __fastcall sub_1192(char *a1, int a2, __int64 a3)\n{\n __int64 v4; // rax\n\n qsort(a1, a2, 4uLL, compar);\n if ( a2 > 0 )\n {\n v4 = 0LL;\n do\n {\n *(_DWORD *)(a3 + v4) = *(_DWORD *)&a1[v4];\n v4 += 4LL;\n }\n while ( v4 != 4LL * a2 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1192(char *a1, int a2, long long a3) {\n long long v4;\n qsort(a1, a2, 4uLL, compar);\n if (a2 > 0) {\n v4 = 0LL;\n do {\n *(uint32_t *)(a3 + v4) = *(uint32_t *)&a1[v4];\n v4 += 4LL;\n } while (v4 != 4LL * a2);\n }\n}", + "ida_pseudo_norm": "void func0(char *a1, int a2, long long a3) {\n long long v4;\n qsort(a1, a2, 4uLL, cmpfunc);\n if (a2 > 0) {\n v4 = 0LL;\n do {\n *(uint32_t *)(a3 + v4) = *(uint32_t *)&a1[v4];\n v4 += 4LL;\n } while (v4 != 4LL * a2);\n }\n}" + }, + { + "index": 341, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\nint cmpfunc (const void * a, const void * b) {\n\n return ( *(int*)a - *(int*)b );\n\n}\n\n\n\n", + "func": "void func0(int arr[], int n, int result[]) {\n qsort(arr, n, sizeof(int), cmpfunc);\n for (int i = 0; i < n; i++) {\n result[i] = arr[i];\n }\n}", + "test": "int main() {\n\n int result[5];\n\n\n\n int set1[] = {1, 2, 3, 4, 5};\n\n func0(set1, 5, result);\n\n assert(result[0] == 1 && result[1] == 2 && result[2] == 3 && result[3] == 4 && result[4] == 5);\n\n\n\n int set2[] = {6, 7, 8, 9, 10, 11};\n\n func0(set2, 6, result);\n\n assert(result[0] == 6 && result[1] == 7 && result[2] == 8 && result[3] == 9 && result[4] == 10 && result[5] == 11);\n\n\n\n int set3[] = {12, 13, 14, 15, 16};\n\n func0(set3, 5, result);\n\n assert(result[0] == 12 && result[1] == 13 && result[2] == 14 && result[3] == 15 && result[4] == 16);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmovslq %esi,%rsi\nlea -0x20(%rip),%rcx\npush %rbp\nmov %rsi,%r12\nmov %rdx,%rbp\nmov $0x4,%edx\npush %rbx\nmov %rdi,%rbx\ncallq 1070 \ntest %r12d,%r12d\njle 13cb \nlea -0x1(%r12),%ecx\nxor %eax,%eax\nnopl 0x0(%rax)\nmov (%rbx,%rax,4),%edx\nmov %edx,0x0(%rbp,%rax,4)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rcx,%rdx\njne 13b8 \npop %rbx\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\nlea rcx, cmpfunc; compar\npush r12\nmov r12, rdx\nmov edx, 4; size\npush rbp\nmovsxd rbp, esi\npush rbx\nmov rsi, rbp; nmemb\nmov rbx, rdi\nsub rsp, 8\ncall _qsort\ntest ebp, ebp\njle short loc_1390\nlea rcx, ds:0[rbp*4]\nxor eax, eax\nnop dword ptr [rax+00000000h]\nloc_1380:\nmov edx, [rbx+rax]\nmov [r12+rax], edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_1380\nloc_1390:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "void __fastcall func0(char *a1, int a2, __int64 a3)\n{\n __int64 v4; // rax\n\n qsort(a1, a2, 4uLL, cmpfunc);\n if ( a2 > 0 )\n {\n v4 = 0LL;\n do\n {\n *(_DWORD *)(a3 + v4) = *(_DWORD *)&a1[v4];\n v4 += 4LL;\n }\n while ( v4 != 4LL * a2 );\n }\n}", + "ida_strip_asm": "sub_1340:\nendbr64\npush r13\nlea rcx, compar; compar\npush r12\nmov r12, rdx\nmov edx, 4; size\npush rbp\nmovsxd rbp, esi\npush rbx\nmov rsi, rbp; nmemb\nmov rbx, rdi\nsub rsp, 8\ncall _qsort\ntest ebp, ebp\njle short loc_1390\nlea rcx, ds:0[rbp*4]\nxor eax, eax\nnop dword ptr [rax+00000000h]\nloc_1380:\nmov edx, [rbx+rax]\nmov [r12+rax], edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_1380\nloc_1390:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "void __fastcall sub_1340(char *a1, int a2, __int64 a3)\n{\n __int64 v4; // rax\n\n qsort(a1, a2, 4uLL, compar);\n if ( a2 > 0 )\n {\n v4 = 0LL;\n do\n {\n *(_DWORD *)(a3 + v4) = *(_DWORD *)&a1[v4];\n v4 += 4LL;\n }\n while ( v4 != 4LL * a2 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1340(char *a1, int a2, long long a3) {\n long long v4;\n qsort(a1, a2, 4uLL, compar);\n if (a2 > 0) {\n v4 = 0LL;\n do {\n *(uint32_t *)(a3 + v4) = *(uint32_t *)&a1[v4];\n v4 += 4LL;\n } while (v4 != 4LL * a2);\n }\n}", + "ida_pseudo_norm": "void func0(char *a1, int a2, long long a3) {\n long long v4;\n qsort(a1, a2, 4uLL, cmpfunc);\n if (a2 > 0) {\n v4 = 0LL;\n do {\n *(uint32_t *)(a3 + v4) = *(uint32_t *)&a1[v4];\n v4 += 4LL;\n } while (v4 != 4LL * a2);\n }\n}" + }, + { + "index": 341, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\nint cmpfunc (const void * a, const void * b) {\n\n return ( *(int*)a - *(int*)b );\n\n}\n\n\n\n", + "func": "void func0(int arr[], int n, int result[]) {\n qsort(arr, n, sizeof(int), cmpfunc);\n for (int i = 0; i < n; i++) {\n result[i] = arr[i];\n }\n}", + "test": "int main() {\n\n int result[5];\n\n\n\n int set1[] = {1, 2, 3, 4, 5};\n\n func0(set1, 5, result);\n\n assert(result[0] == 1 && result[1] == 2 && result[2] == 3 && result[3] == 4 && result[4] == 5);\n\n\n\n int set2[] = {6, 7, 8, 9, 10, 11};\n\n func0(set2, 6, result);\n\n assert(result[0] == 6 && result[1] == 7 && result[2] == 8 && result[3] == 9 && result[4] == 10 && result[5] == 11);\n\n\n\n int set3[] = {12, 13, 14, 15, 16};\n\n func0(set3, 5, result);\n\n assert(result[0] == 12 && result[1] == 13 && result[2] == 14 && result[3] == 15 && result[4] == 16);\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmovslq %esi,%rsi\nlea -0x20(%rip),%rcx\npush %rbp\nmov %rsi,%r12\nmov %rdx,%rbp\nmov $0x4,%edx\npush %rbx\nmov %rdi,%rbx\ncallq 1070 \ntest %r12d,%r12d\njle 13db \nlea 0xf(%rbx),%rdx\nlea -0x1(%r12),%eax\nsub %rbp,%rdx\ncmp $0x1e,%rdx\njbe 13e0 \ncmp $0x3,%eax\njbe 13e0 \nmov %r12d,%edx\nxor %eax,%eax\nshr $0x2,%edx\nshl $0x4,%rdx\nnopl (%rax)\nmovdqu (%rbx,%rax,1),%xmm0\nmovups %xmm0,0x0(%rbp,%rax,1)\nadd $0x10,%rax\ncmp %rdx,%rax\njne 1390 \nmov %r12d,%eax\nand $0xfffffffc,%eax\ntest $0x3,%r12b\nje 13db \nmov %eax,%edx\nmov (%rbx,%rdx,4),%ecx\nmov %ecx,0x0(%rbp,%rdx,4)\nlea 0x1(%rax),%edx\ncmp %edx,%r12d\njle 13db \nmovslq %edx,%rdx\nadd $0x2,%eax\nmov (%rbx,%rdx,4),%ecx\nmov %ecx,0x0(%rbp,%rdx,4)\ncmp %eax,%r12d\njle 13db \ncltq\nmov (%rbx,%rax,4),%edx\nmov %edx,0x0(%rbp,%rax,4)\npop %rbx\npop %rbp\npop %r12\nretq\nmov %eax,%edx\nxor %eax,%eax\nnopl 0x0(%rax)\nmov (%rbx,%rax,4),%ecx\nmov %ecx,0x0(%rbp,%rax,4)\nmov %rax,%rcx\nadd $0x1,%rax\ncmp %rdx,%rcx\njne 13e8 \npop %rbx\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\nmovsxd r13, esi\nlea rcx, cmpfunc; compar\npush r12\nmov rsi, r13; nmemb\npush rbp\nmov rbp, rdx\nmov edx, 4; size\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _qsort\ntest r13d, r13d\njle short loc_13B0\nlea eax, [r13-1]\nmov r12, r13\ncmp eax, 2\njbe short loc_138C\nlea rdx, [rbx+4]\nmov rax, rbp\nsub rax, rdx\ncmp rax, 8\nja short loc_13C0\nloc_138C:\nlea rcx, ds:0[r13*4]\nxor eax, eax\nnop word ptr [rax+rax+00000000h]\nloc_13A0:\nmov edx, [rbx+rax]\nmov [rbp+rax+0], edx\nadd rax, 4\ncmp rcx, rax\njnz short loc_13A0\nloc_13B0:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_13C0:\nmov edx, r13d\nxor eax, eax\nshr edx, 2\nshl rdx, 4\nnop dword ptr [rax+00h]\nloc_13D0:\nmovdqu xmm0, xmmword ptr [rbx+rax]\nmovups xmmword ptr [rbp+rax+0], xmm0\nadd rax, 10h\ncmp rax, rdx\njnz short loc_13D0\nmov eax, r12d\nand eax, 0FFFFFFFCh\ntest r12b, 3\njz short loc_13B0\nmov ecx, eax\nmov esi, [rbx+rcx*4]\nlea rdx, ds:0[rcx*4]\nmov [rbp+rcx*4+0], esi\nlea ecx, [rax+1]\ncmp r12d, ecx\njle short loc_13B0\nmov ecx, [rbx+rdx+4]\nadd eax, 2\nmov [rbp+rdx+4], ecx\ncmp r12d, eax\njle short loc_13B0\nmov eax, [rbx+rdx+8]\nmov [rbp+rdx+8], eax\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "void __fastcall func0(char *a1, int a2, __int64 a3)\n{\n __int64 v4; // rax\n __int64 v5; // rax\n unsigned int v6; // eax\n __int64 v7; // rdx\n\n qsort(a1, a2, 4uLL, cmpfunc);\n if ( a2 > 0 )\n {\n if ( (unsigned int)(a2 - 1) > 2 && (unsigned __int64)(a3 - (_QWORD)(a1 + 4)) > 8 )\n {\n v5 = 0LL;\n do\n {\n *(__m128i *)(a3 + v5) = _mm_loadu_si128((const __m128i *)&a1[v5]);\n v5 += 16LL;\n }\n while ( v5 != 16LL * ((unsigned int)a2 >> 2) );\n v6 = a2 & 0xFFFFFFFC;\n if ( (a2 & 3) != 0 )\n {\n v7 = 4LL * v6;\n *(_DWORD *)(a3 + v7) = *(_DWORD *)&a1[v7];\n if ( a2 > (int)(v6 + 1) )\n {\n *(_DWORD *)(a3 + v7 + 4) = *(_DWORD *)&a1[v7 + 4];\n if ( a2 > (int)(v6 + 2) )\n *(_DWORD *)(a3 + v7 + 8) = *(_DWORD *)&a1[v7 + 8];\n }\n }\n }\n else\n {\n v4 = 0LL;\n do\n {\n *(_DWORD *)(a3 + v4) = *(_DWORD *)&a1[v4];\n v4 += 4LL;\n }\n while ( 4LL * a2 != v4 );\n }\n }\n}", + "ida_strip_asm": "sub_1340:\nendbr64\npush r13\nmovsxd r13, esi\nlea rcx, compar; compar\npush r12\nmov rsi, r13; nmemb\npush rbp\nmov rbp, rdx\nmov edx, 4; size\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _qsort\ntest r13d, r13d\njle short loc_13B0\nlea eax, [r13-1]\nmov r12, r13\ncmp eax, 2\njbe short loc_138C\nlea rdx, [rbx+4]\nmov rax, rbp\nsub rax, rdx\ncmp rax, 8\nja short loc_13C0\nloc_138C:\nlea rcx, ds:0[r13*4]\nxor eax, eax\nnop word ptr [rax+rax+00000000h]\nloc_13A0:\nmov edx, [rbx+rax]\nmov [rbp+rax+0], edx\nadd rax, 4\ncmp rcx, rax\njnz short loc_13A0\nloc_13B0:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_13C0:\nmov edx, r13d\nxor eax, eax\nshr edx, 2\nshl rdx, 4\nnop dword ptr [rax+00h]\nloc_13D0:\nmovdqu xmm0, xmmword ptr [rbx+rax]\nmovups xmmword ptr [rbp+rax+0], xmm0\nadd rax, 10h\ncmp rax, rdx\njnz short loc_13D0\nmov eax, r12d\nand eax, 0FFFFFFFCh\ntest r12b, 3\njz short loc_13B0\nmov ecx, eax\nmov esi, [rbx+rcx*4]\nlea rdx, ds:0[rcx*4]\nmov [rbp+rcx*4+0], esi\nlea ecx, [rax+1]\ncmp r12d, ecx\njle short loc_13B0\nmov ecx, [rbx+rdx+4]\nadd eax, 2\nmov [rbp+rdx+4], ecx\ncmp r12d, eax\njle short loc_13B0\nmov eax, [rbx+rdx+8]\nmov [rbp+rdx+8], eax\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "void __fastcall sub_1340(char *a1, int a2, __int64 a3)\n{\n __int64 v4; // rax\n __int64 v5; // rax\n unsigned int v6; // eax\n __int64 v7; // rdx\n\n qsort(a1, a2, 4uLL, compar);\n if ( a2 > 0 )\n {\n if ( (unsigned int)(a2 - 1) > 2 && (unsigned __int64)(a3 - (_QWORD)(a1 + 4)) > 8 )\n {\n v5 = 0LL;\n do\n {\n *(__m128i *)(a3 + v5) = _mm_loadu_si128((const __m128i *)&a1[v5]);\n v5 += 16LL;\n }\n while ( v5 != 16LL * ((unsigned int)a2 >> 2) );\n v6 = a2 & 0xFFFFFFFC;\n if ( (a2 & 3) != 0 )\n {\n v7 = 4LL * v6;\n *(_DWORD *)(a3 + v7) = *(_DWORD *)&a1[v7];\n if ( a2 > (int)(v6 + 1) )\n {\n *(_DWORD *)(a3 + v7 + 4) = *(_DWORD *)&a1[v7 + 4];\n if ( a2 > (int)(v6 + 2) )\n *(_DWORD *)(a3 + v7 + 8) = *(_DWORD *)&a1[v7 + 8];\n }\n }\n }\n else\n {\n v4 = 0LL;\n do\n {\n *(_DWORD *)(a3 + v4) = *(_DWORD *)&a1[v4];\n v4 += 4LL;\n }\n while ( 4LL * a2 != v4 );\n }\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1340(char *a1, int a2, long long a3) {\n long long v4;\n long long v5;\n unsigned int v6;\n long long v7;\n qsort(a1, a2, 4uLL, compar);\n if (a2 > 0) {\n if ((unsigned int)(a2 - 1) > 2 &&\n (unsigned long long)(a3 - (uint64_t)(a1 + 4)) > 8) {\n v5 = 0LL;\n do {\n *(__m128i *)(a3 + v5) = _mm_loadu_si128((const __m128i *)&a1[v5]);\n v5 += 16LL;\n } while (v5 != 16LL * ((unsigned int)a2 >> 2));\n v6 = a2 & 4294967292;\n if ((a2 & 3) != 0) {\n v7 = 4LL * v6;\n *(uint32_t *)(a3 + v7) = *(uint32_t *)&a1[v7];\n if (a2 > (int)(v6 + 1)) {\n *(uint32_t *)(a3 + v7 + 4) = *(uint32_t *)&a1[v7 + 4];\n if (a2 > (int)(v6 + 2))\n *(uint32_t *)(a3 + v7 + 8) = *(uint32_t *)&a1[v7 + 8];\n }\n }\n } else {\n v4 = 0LL;\n do {\n *(uint32_t *)(a3 + v4) = *(uint32_t *)&a1[v4];\n v4 += 4LL;\n } while (4LL * a2 != v4);\n }\n }\n}", + "ida_pseudo_norm": "void func0(char *a1, int a2, long long a3) {\n long long v4;\n long long v5;\n unsigned int v6;\n long long v7;\n qsort(a1, a2, 4uLL, cmpfunc);\n if (a2 > 0) {\n if ((unsigned int)(a2 - 1) > 2 &&\n (unsigned long long)(a3 - (uint64_t)(a1 + 4)) > 8) {\n v5 = 0LL;\n do {\n *(__m128i *)(a3 + v5) = _mm_loadu_si128((const __m128i *)&a1[v5]);\n v5 += 16LL;\n } while (v5 != 16LL * ((unsigned int)a2 >> 2));\n v6 = a2 & 4294967292;\n if ((a2 & 3) != 0) {\n v7 = 4LL * v6;\n *(uint32_t *)(a3 + v7) = *(uint32_t *)&a1[v7];\n if (a2 > (int)(v6 + 1)) {\n *(uint32_t *)(a3 + v7 + 4) = *(uint32_t *)&a1[v7 + 4];\n if (a2 > (int)(v6 + 2))\n *(uint32_t *)(a3 + v7 + 8) = *(uint32_t *)&a1[v7 + 8];\n }\n }\n } else {\n v4 = 0LL;\n do {\n *(uint32_t *)(a3 + v4) = *(uint32_t *)&a1[v4];\n v4 += 4LL;\n } while (4LL * a2 != v4);\n }\n }\n}" + }, + { + "index": 342, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct Node {\n\n int value;\n\n int list_num;\n\n int index;\n\n} Node;\n\n\n\nNode* create_node(int value, int list_num, int index) {\n\n Node* node = (Node*)malloc(sizeof(Node));\n\n node->value = value;\n\n node->list_num = list_num;\n\n node->index = index;\n\n return node;\n\n}\n\n\n\nint compare_nodes(const void *a, const void *b) {\n\n Node* node1 = *(Node**)a;\n\n Node* node2 = *(Node**)b;\n\n return (node1->value > node2->value) - (node1->value < node2->value);\n\n}\n\n\n\n", + "func": "int* func0(int** list, int* list_sizes, int numLists) {\n static int range[2];\n int high = INT_MIN;\n int i, j;\n Node** pq = malloc(numLists * sizeof(Node*));\n int pq_size = 0;\n for (i = 0; i < numLists; i++) {\n pq[pq_size++] = create_node(list[i][0], i, 0);\n if (list[i][0] > high) {\n high = list[i][0];\n }\n }\n qsort(pq, pq_size, sizeof(Node*), compare_nodes);\n range[0] = 0;\n range[1] = INT_MAX;\n while (1) {\n Node* top = pq[0];\n int low = top->value;\n i = top->list_num;\n j = top->index;\n if (high - low < range[1] - range[0]) {\n range[0] = low;\n range[1] = high;\n }\n if (j == list_sizes[i] - 1) {\n break;\n }\n pq[0] = create_node(list[i][j + 1], i, j + 1);\n if (list[i][j + 1] > high) {\n high = list[i][j + 1];\n }\n qsort(pq, pq_size, sizeof(Node*), compare_nodes);\n }\n free(pq);\n return range;\n}", + "test": "int main() {\n\n int list1[] = {3, 6, 8, 10, 15};\n\n int list2[] = {1, 5, 12};\n\n int list3[] = {4, 8, 15, 16};\n\n int list4[] = {2, 6};\n\n int* lists[] = {list1, list2, list3, list4};\n\n int sizes[] = {5, 3, 4, 2};\n\n int* result;\n\n\n\n result = func0(lists, sizes, 4);\n\n assert(result[0] == 4 && result[1] == 6);\n\n\n\n int list5[] = {4, 7, 9, 11, 16};\n\n int list6[] = {2, 6, 13};\n\n int list7[] = {5, 9, 16, 17};\n\n int list8[] = {3, 7};\n\n int* lists2[] = {list5, list6, list7, list8};\n\n int sizes2[] = {5, 3, 4, 2};\n\n\n\n result = func0(lists2, sizes2, 4);\n\n assert(result[0] == 5 && result[1] == 7);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x58,%rsp\nmov %rdi,-0x48(%rbp)\nmov %rsi,-0x50(%rbp)\nmov %edx,-0x54(%rbp)\nmovl $0x80000000,-0x34(%rbp)\nmov -0x54(%rbp),%eax\ncltq\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,-0x20(%rbp)\nmovl $0x0,-0x2c(%rbp)\nmovl $0x0,-0x30(%rbp)\njmpq 1330 \nmov -0x30(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov (%rax),%ecx\nmov -0x2c(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x2c(%rbp)\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x20(%rbp),%rax\nlea (%rdx,%rax,1),%rbx\nmov -0x30(%rbp),%eax\nmov $0x0,%edx\nmov %eax,%esi\nmov %ecx,%edi\ncallq 11c9 \nmov %rax,(%rbx)\nmov -0x30(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov (%rax),%eax\ncmp %eax,-0x34(%rbp)\njge 132c \nmov -0x30(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov (%rax),%eax\nmov %eax,-0x34(%rbp)\naddl $0x1,-0x30(%rbp)\nmov -0x30(%rbp),%eax\ncmp -0x54(%rbp),%eax\njl 12aa \nmov -0x2c(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x20(%rbp),%rax\nlea -0x13e(%rip),%rcx\nmov $0x8,%edx\nmov %rax,%rdi\ncallq 10a0 \nmovl $0x0,0x2cb4(%rip)\nmovl $0x7fffffff,0x2cae(%rip)\nmov -0x20(%rbp),%rax\nmov (%rax),%rax\nmov %rax,-0x18(%rbp)\nmov -0x18(%rbp),%rax\nmov (%rax),%eax\nmov %eax,-0x28(%rbp)\nmov -0x18(%rbp),%rax\nmov 0x4(%rax),%eax\nmov %eax,-0x30(%rbp)\nmov -0x18(%rbp),%rax\nmov 0x8(%rax),%eax\nmov %eax,-0x24(%rbp)\nmov -0x34(%rbp),%eax\nsub -0x28(%rbp),%eax\nmov 0x2c7a(%rip),%ecx\nmov 0x2c70(%rip),%edx\nsub %edx,%ecx\nmov %ecx,%edx\ncmp %edx,%eax\njge 13c2 \nmov -0x28(%rbp),%eax\nmov %eax,0x2c5f(%rip)\nmov -0x34(%rbp),%eax\nmov %eax,0x2c5a(%rip)\nmov -0x30(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x50(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nsub $0x1,%eax\ncmp %eax,-0x24(%rbp)\nje 14a6 \nmov -0x24(%rbp),%eax\nlea 0x1(%rax),%edx\nmov -0x30(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x48(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%rax\nmov -0x24(%rbp),%ecx\nmovslq %ecx,%rcx\nadd $0x1,%rcx\nshl $0x2,%rcx\nadd %rcx,%rax\nmov (%rax),%eax\nmov -0x30(%rbp),%ecx\nmov %ecx,%esi\nmov %eax,%edi\ncallq 11c9 \nmov -0x20(%rbp),%rdx\nmov %rax,(%rdx)\nmov -0x30(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0x24(%rbp),%edx\nmovslq %edx,%rdx\nadd $0x1,%rdx\nshl $0x2,%rdx\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x34(%rbp)\njge 1483 \nmov -0x30(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0x24(%rbp),%edx\nmovslq %edx,%rdx\nadd $0x1,%rdx\nshl $0x2,%rdx\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x34(%rbp)\nmov -0x2c(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x20(%rbp),%rax\nlea -0x285(%rip),%rcx\nmov $0x8,%edx\nmov %rax,%rdi\ncallq 10a0 \njmpq 136e \nmov -0x20(%rbp),%rax\nmov %rax,%rdi\ncallq 1090 \nlea 0x2b5e(%rip),%rax\nadd $0x58,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 58h\nmov [rbp+var_48], rdi\nmov [rbp+var_50], rsi\nmov [rbp+var_54], edx\nmov [rbp+var_34], 80000000h\nmov eax, [rbp+var_54]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+base], rax\nmov [rbp+var_2C], 0\nmov [rbp+var_30], 0\njmp loc_1330\nloc_12AA:\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov rax, [rax]\nmov ecx, [rax]\nmov eax, [rbp+var_2C]\nlea edx, [rax+1]\nmov [rbp+var_2C], edx\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+base]\nlea rbx, [rdx+rax]\nmov eax, [rbp+var_30]\nmov edx, 0\nmov esi, eax\nmov edi, ecx\ncall create_node\nmov [rbx], rax\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov rax, [rax]\nmov eax, [rax]\ncmp [rbp+var_34], eax\njge short loc_132C\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov rax, [rax]\nmov eax, [rax]\nmov [rbp+var_34], eax\nloc_132C:\nadd [rbp+var_30], 1\nloc_1330:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_54]\njl loc_12AA\nmov eax, [rbp+var_2C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compare_nodes\nmov rcx, rdx; compar\nmov edx, 8; size\nmov rdi, rax; base\ncall _qsort\nmov cs:range_1, 0\nmov cs:dword_401C, 7FFFFFFFh\nloc_1371:\nmov rax, [rbp+base]\nmov rax, [rax]\nmov [rbp+var_18], rax\nmov rax, [rbp+var_18]\nmov eax, [rax]\nmov [rbp+var_28], eax\nmov rax, [rbp+var_18]\nmov eax, [rax+4]\nmov [rbp+var_30], eax\nmov rax, [rbp+var_18]\nmov eax, [rax+8]\nmov [rbp+var_24], eax\nmov eax, [rbp+var_34]\nsub eax, [rbp+var_28]\nmov ecx, eax\nmov edx, cs:dword_401C\nmov eax, cs:range_1\nsub edx, eax\ncmp ecx, edx\njge short loc_13C5\nmov eax, [rbp+var_28]\nmov cs:range_1, eax\nmov eax, [rbp+var_34]\nmov cs:dword_401C, eax\nloc_13C5:\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_50]\nadd rax, rdx\nmov eax, [rax]\nsub eax, 1\ncmp [rbp+var_24], eax\njz loc_14AC\nmov eax, [rbp+var_24]\nlea edx, [rax+1]\nmov eax, [rbp+var_30]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nadd rax, rcx\nmov rax, [rax]\nmov ecx, [rbp+var_24]\nmovsxd rcx, ecx\nadd rcx, 1\nshl rcx, 2\nadd rax, rcx\nmov eax, [rax]\nmov ecx, [rbp+var_30]\nmov esi, ecx\nmov edi, eax\ncall create_node\nmov rdx, [rbp+base]\nmov [rdx], rax\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nadd rdx, 1\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_34], eax\njge short loc_1486\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nadd rdx, 1\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_34], eax\nloc_1486:\nmov eax, [rbp+var_2C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compare_nodes\nmov rcx, rdx; compar\nmov edx, 8; size\nmov rdi, rax; base\ncall _qsort\njmp loc_1371\nloc_14AC:\nnop\nmov rax, [rbp+base]\nmov rdi, rax; ptr\ncall _free\nlea rax, range_1\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "int *__fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n int v3; // eax\n signed int v6; // [rsp+2Ch] [rbp-34h]\n unsigned int i; // [rsp+30h] [rbp-30h]\n int v8; // [rsp+30h] [rbp-30h]\n int v9; // [rsp+34h] [rbp-2Ch]\n int v10; // [rsp+3Ch] [rbp-24h]\n int **base; // [rsp+40h] [rbp-20h]\n\n v6 = 0x80000000;\n base = (int **)malloc(8LL * a3);\n v9 = 0;\n for ( i = 0; (int)i < a3; ++i )\n {\n v3 = v9++;\n base[v3] = (int *)create_node(**(unsigned int **)(8LL * (int)i + a1), i, 0LL);\n if ( v6 < **(_DWORD **)(8LL * (int)i + a1) )\n v6 = **(_DWORD **)(8LL * (int)i + a1);\n }\n qsort(base, v9, 8uLL, compare_nodes);\n range_1 = 0;\n dword_401C = 0x7FFFFFFF;\n while ( 1 )\n {\n v8 = (*base)[1];\n v10 = (*base)[2];\n if ( v6 - **base < dword_401C - range_1 )\n {\n range_1 = **base;\n dword_401C = v6;\n }\n if ( v10 == *(_DWORD *)(4LL * v8 + a2) - 1 )\n break;\n *base = (int *)create_node(\n *(unsigned int *)(4 * (v10 + 1LL) + *(_QWORD *)(8LL * v8 + a1)),\n (unsigned int)v8,\n (unsigned int)(v10 + 1));\n if ( v6 < *(_DWORD *)(4 * (v10 + 1LL) + *(_QWORD *)(8LL * v8 + a1)) )\n v6 = *(_DWORD *)(4 * (v10 + 1LL) + *(_QWORD *)(8LL * v8 + a1));\n qsort(base, v9, 8uLL, compare_nodes);\n }\n free(base);\n return &range_1;\n}", + "ida_strip_asm": "sub_1263:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 58h\nmov [rbp+var_48], rdi\nmov [rbp+var_50], rsi\nmov [rbp+var_54], edx\nmov [rbp+var_34], 80000000h\nmov eax, [rbp+var_54]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+base], rax\nmov [rbp+var_2C], 0\nmov [rbp+var_30], 0\njmp loc_1330\nloc_12AA:\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov rax, [rax]\nmov ecx, [rax]\nmov eax, [rbp+var_2C]\nlea edx, [rax+1]\nmov [rbp+var_2C], edx\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+base]\nlea rbx, [rdx+rax]\nmov eax, [rbp+var_30]\nmov edx, 0\nmov esi, eax\nmov edi, ecx\ncall sub_11C9\nmov [rbx], rax\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov rax, [rax]\nmov eax, [rax]\ncmp [rbp+var_34], eax\njge short loc_132C\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov rax, [rax]\nmov eax, [rax]\nmov [rbp+var_34], eax\nloc_132C:\nadd [rbp+var_30], 1\nloc_1330:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_54]\njl loc_12AA\nmov eax, [rbp+var_2C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 8; size\nmov rdi, rax; base\ncall _qsort\nmov cs:dword_4018, 0\nmov cs:dword_401C, 7FFFFFFFh\nloc_1371:\nmov rax, [rbp+base]\nmov rax, [rax]\nmov [rbp+var_18], rax\nmov rax, [rbp+var_18]\nmov eax, [rax]\nmov [rbp+var_28], eax\nmov rax, [rbp+var_18]\nmov eax, [rax+4]\nmov [rbp+var_30], eax\nmov rax, [rbp+var_18]\nmov eax, [rax+8]\nmov [rbp+var_24], eax\nmov eax, [rbp+var_34]\nsub eax, [rbp+var_28]\nmov ecx, eax\nmov edx, cs:dword_401C\nmov eax, cs:dword_4018\nsub edx, eax\ncmp ecx, edx\njge short loc_13C5\nmov eax, [rbp+var_28]\nmov cs:dword_4018, eax\nmov eax, [rbp+var_34]\nmov cs:dword_401C, eax\nloc_13C5:\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_50]\nadd rax, rdx\nmov eax, [rax]\nsub eax, 1\ncmp [rbp+var_24], eax\njz loc_14AC\nmov eax, [rbp+var_24]\nlea edx, [rax+1]\nmov eax, [rbp+var_30]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nadd rax, rcx\nmov rax, [rax]\nmov ecx, [rbp+var_24]\nmovsxd rcx, ecx\nadd rcx, 1\nshl rcx, 2\nadd rax, rcx\nmov eax, [rax]\nmov ecx, [rbp+var_30]\nmov esi, ecx\nmov edi, eax\ncall sub_11C9\nmov rdx, [rbp+base]\nmov [rdx], rax\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nadd rdx, 1\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_34], eax\njge short loc_1486\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nadd rdx, 1\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_34], eax\nloc_1486:\nmov eax, [rbp+var_2C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 8; size\nmov rdi, rax; base\ncall _qsort\njmp loc_1371\nloc_14AC:\nnop\nmov rax, [rbp+base]\nmov rdi, rax; ptr\ncall _free\nlea rax, dword_4018\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "int *__fastcall sub_1263(__int64 a1, __int64 a2, int a3)\n{\n int v3; // eax\n signed int v6; // [rsp+2Ch] [rbp-34h]\n unsigned int i; // [rsp+30h] [rbp-30h]\n int v8; // [rsp+30h] [rbp-30h]\n int v9; // [rsp+34h] [rbp-2Ch]\n int v10; // [rsp+3Ch] [rbp-24h]\n int **base; // [rsp+40h] [rbp-20h]\n\n v6 = 0x80000000;\n base = (int **)malloc(8LL * a3);\n v9 = 0;\n for ( i = 0; (int)i < a3; ++i )\n {\n v3 = v9++;\n base[v3] = (int *)sub_11C9(**(unsigned int **)(8LL * (int)i + a1), i, 0LL);\n if ( v6 < **(_DWORD **)(8LL * (int)i + a1) )\n v6 = **(_DWORD **)(8LL * (int)i + a1);\n }\n qsort(base, v9, 8uLL, compar);\n dword_4018 = 0;\n dword_401C = 0x7FFFFFFF;\n while ( 1 )\n {\n v8 = (*base)[1];\n v10 = (*base)[2];\n if ( v6 - **base < dword_401C - dword_4018 )\n {\n dword_4018 = **base;\n dword_401C = v6;\n }\n if ( v10 == *(_DWORD *)(4LL * v8 + a2) - 1 )\n break;\n *base = (int *)sub_11C9(\n *(unsigned int *)(4 * (v10 + 1LL) + *(_QWORD *)(8LL * v8 + a1)),\n (unsigned int)v8,\n (unsigned int)(v10 + 1));\n if ( v6 < *(_DWORD *)(4 * (v10 + 1LL) + *(_QWORD *)(8LL * v8 + a1)) )\n v6 = *(_DWORD *)(4 * (v10 + 1LL) + *(_QWORD *)(8LL * v8 + a1));\n qsort(base, v9, 8uLL, compar);\n }\n free(base);\n return &dword_4018;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "int *sub_1263(long long a1, long long a2, int a3) {\n int v3;\n signed int v6;\n unsigned int i;\n int v8;\n int v9;\n int v10;\n int **base;\n v6 = 2147483648;\n base = (int **)malloc(8LL * a3);\n v9 = 0;\n for (i = 0; (int)i < a3; ++i) {\n v3 = v9++;\n base[v3] = (int *)sub_11C9(**(unsigned int **)(8LL * (int)i + a1), i, 0LL);\n if (v6 < **(uint32_t **)(8LL * (int)i + a1))\n v6 = **(uint32_t **)(8LL * (int)i + a1);\n }\n qsort(base, v9, 8uLL, compar);\n dword_4018 = 0;\n dword_401C = 2147483647;\n while (1) {\n v8 = (*base)[1];\n v10 = (*base)[2];\n if (v6 - **base < dword_401C - dword_4018) {\n dword_4018 = **base;\n dword_401C = v6;\n }\n if (v10 == *(uint32_t *)(4LL * v8 + a2) - 1) break;\n *base = (int *)sub_11C9(\n *(unsigned int *)(4 * (v10 + 1LL) + *(uint64_t *)(8LL * v8 + a1)),\n (unsigned int)v8, (unsigned int)(v10 + 1));\n if (v6 < *(uint32_t *)(4 * (v10 + 1LL) + *(uint64_t *)(8LL * v8 + a1)))\n v6 = *(uint32_t *)(4 * (v10 + 1LL) + *(uint64_t *)(8LL * v8 + a1));\n qsort(base, v9, 8uLL, compar);\n }\n free(base);\n return &dword_4018;\n}", + "ida_pseudo_norm": "int *func0(long long a1, long long a2, int a3) {\n int v3;\n signed int v6;\n unsigned int i;\n int v8;\n int v9;\n int v10;\n int **base;\n v6 = 2147483648;\n base = (int **)malloc(8LL * a3);\n v9 = 0;\n for (i = 0; (int)i < a3; ++i) {\n v3 = v9++;\n base[v3] =\n (int *)create_node(**(unsigned int **)(8LL * (int)i + a1), i, 0LL);\n if (v6 < **(uint32_t **)(8LL * (int)i + a1))\n v6 = **(uint32_t **)(8LL * (int)i + a1);\n }\n qsort(base, v9, 8uLL, compare_nodes);\n range_1 = 0;\n dword_401C = 2147483647;\n while (1) {\n v8 = (*base)[1];\n v10 = (*base)[2];\n if (v6 - **base < dword_401C - range_1) {\n range_1 = **base;\n dword_401C = v6;\n }\n if (v10 == *(uint32_t *)(4LL * v8 + a2) - 1) break;\n *base = (int *)create_node(\n *(unsigned int *)(4 * (v10 + 1LL) + *(uint64_t *)(8LL * v8 + a1)),\n (unsigned int)v8, (unsigned int)(v10 + 1));\n if (v6 < *(uint32_t *)(4 * (v10 + 1LL) + *(uint64_t *)(8LL * v8 + a1)))\n v6 = *(uint32_t *)(4 * (v10 + 1LL) + *(uint64_t *)(8LL * v8 + a1));\n qsort(base, v9, 8uLL, compare_nodes);\n }\n free(base);\n return &range_1;\n}" + }, + { + "index": 342, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct Node {\n\n int value;\n\n int list_num;\n\n int index;\n\n} Node;\n\n\n\nNode* create_node(int value, int list_num, int index) {\n\n Node* node = (Node*)malloc(sizeof(Node));\n\n node->value = value;\n\n node->list_num = list_num;\n\n node->index = index;\n\n return node;\n\n}\n\n\n\nint compare_nodes(const void *a, const void *b) {\n\n Node* node1 = *(Node**)a;\n\n Node* node2 = *(Node**)b;\n\n return (node1->value > node2->value) - (node1->value < node2->value);\n\n}\n\n\n\n", + "func": "int* func0(int** list, int* list_sizes, int numLists) {\n static int range[2];\n int high = INT_MIN;\n int i, j;\n Node** pq = malloc(numLists * sizeof(Node*));\n int pq_size = 0;\n for (i = 0; i < numLists; i++) {\n pq[pq_size++] = create_node(list[i][0], i, 0);\n if (list[i][0] > high) {\n high = list[i][0];\n }\n }\n qsort(pq, pq_size, sizeof(Node*), compare_nodes);\n range[0] = 0;\n range[1] = INT_MAX;\n while (1) {\n Node* top = pq[0];\n int low = top->value;\n i = top->list_num;\n j = top->index;\n if (high - low < range[1] - range[0]) {\n range[0] = low;\n range[1] = high;\n }\n if (j == list_sizes[i] - 1) {\n break;\n }\n pq[0] = create_node(list[i][j + 1], i, j + 1);\n if (list[i][j + 1] > high) {\n high = list[i][j + 1];\n }\n qsort(pq, pq_size, sizeof(Node*), compare_nodes);\n }\n free(pq);\n return range;\n}", + "test": "int main() {\n\n int list1[] = {3, 6, 8, 10, 15};\n\n int list2[] = {1, 5, 12};\n\n int list3[] = {4, 8, 15, 16};\n\n int list4[] = {2, 6};\n\n int* lists[] = {list1, list2, list3, list4};\n\n int sizes[] = {5, 3, 4, 2};\n\n int* result;\n\n\n\n result = func0(lists, sizes, 4);\n\n assert(result[0] == 4 && result[1] == 6);\n\n\n\n int list5[] = {4, 7, 9, 11, 16};\n\n int list6[] = {2, 6, 13};\n\n int list7[] = {5, 9, 16, 17};\n\n int list8[] = {3, 7};\n\n int* lists2[] = {list5, list6, list7, list8};\n\n int sizes2[] = {5, 3, 4, 2};\n\n\n\n result = func0(lists2, sizes2, 4);\n\n assert(result[0] == 5 && result[1] == 7);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov %rdi,%r13\nmov %rsi,%r15\nmov %edx,%ebx\nmov %edx,0x8(%rsp)\nmovslq %edx,%rdi\nshl $0x3,%rdi\ncallq 10d0 \nmov %rax,%r12\ntest %ebx,%ebx\njle 12b4 \nlea -0x1(%rbx),%r14d\nmov $0x0,%ebp\nmov $0x80000000,%ebx\nmov 0x0(%r13,%rbp,8),%rax\nmov $0x0,%edx\nmov %ebp,%esi\nmov (%rax),%edi\ncallq 11e8 \nmov %rax,(%r12,%rbp,8)\nmov 0x0(%r13,%rbp,8),%rax\nmov (%rax),%eax\ncmp %eax,%ebx\ncmovl %eax,%ebx\nmov %rbp,%rax\nadd $0x1,%rbp\ncmp %r14,%rax\njne 124e \nmovslq 0x8(%rsp),%rax\nmov %rax,0x8(%rsp)\nlea -0xc5(%rip),%rcx\nmov $0x8,%edx\nmov %rax,%rsi\nmov %r12,%rdi\ncallq 10a0 \nmovl $0x0,0x2d70(%rip)\nmovl $0x7fffffff,0x2d6a(%rip)\njmp 131f \nmovl $0x0,0x8(%rsp)\nmov $0x80000000,%ebx\njmp 127d \nmov %ecx,0x2d4f(%rip)\nmov %ebx,0x2d4d(%rip)\nmovslq %esi,%rcx\nmov (%r15,%rcx,4),%eax\nsub $0x1,%eax\ncmp %edx,%eax\nje 1341 \nlea 0x0(%r13,%rcx,8),%r14\nmovslq %edx,%rbp\nadd $0x1,%rbp\nadd $0x1,%edx\nmov (%r14),%rax\nmov (%rax,%rbp,4),%edi\ncallq 11e8 \nmov %rax,(%r12)\nmov (%r14),%rax\nmov (%rax,%rbp,4),%eax\ncmp %eax,%ebx\ncmovl %eax,%ebx\nlea -0x144(%rip),%rcx\nmov $0x8,%edx\nmov 0x8(%rsp),%rsi\nmov %r12,%rdi\ncallq 10a0 \nmov (%r12),%rax\nmov (%rax),%ecx\nmov 0x4(%rax),%esi\nmov 0x8(%rax),%edx\nmov %ebx,%edi\nsub %ecx,%edi\nmov 0x2ce7(%rip),%eax\nsub 0x2cdd(%rip),%eax\ncmp %eax,%edi\njge 12cf \njmp 12c3 \nmov %r12,%rdi\ncallq 1090 \nlea 0x2cc8(%rip),%rax\nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov r14, rdi\nmov r15, rsi\nmov ebx, edx\nmov [rsp+48h+var_3C], edx\nmovsxd rax, edx\nmov [rsp+48h+var_48], rax\nlea rdi, ds:0[rax*8]; size\ncall _malloc\nmov r12, rax\ntest ebx, ebx\njle short loc_12AD\nmov ebp, 0\nmov ebx, 80000000h\nloc_1250:\nmov r13, [r14+rbp*8]\nmov edi, [r13+0]\nmov edx, 0\nmov esi, ebp\ncall create_node\nmov [r12+rbp*8], rax\nmov eax, [r13+0]\ncmp ebx, eax\ncmovl ebx, eax\nadd rbp, 1\ncmp [rsp+48h+var_48], rbp\njnz short loc_1250\nloc_127B:\nmovsxd r13, [rsp+48h+var_3C]\nlea rcx, compare_nodes; compar\nmov edx, 8; size\nmov rsi, r13; nmemb\nmov rdi, r12; base\ncall _qsort\nmov cs:range_1, 0\nmov cs:dword_401C, 7FFFFFFFh\njmp short loc_1310\nloc_12AD:\nmov [rsp+48h+var_3C], 0\nmov ebx, 80000000h\njmp short loc_127B\nloc_12BC:\nmov cs:range_1, ecx\nmov cs:dword_401C, ebx\nloc_12C8:\nmovsxd rcx, esi\nmov eax, [r15+rcx*4]\nsub eax, 1\ncmp eax, edx\njz short loc_1332\nmovsxd rdi, edx\nmov rax, [r14+rcx*8]\nlea rbp, [rax+rdi*4+4]\nadd edx, 1\nmov edi, [rbp+0]\ncall create_node\nmov [r12], rax\nmov eax, [rbp+0]\ncmp ebx, eax\ncmovl ebx, eax\nlea rcx, compare_nodes; compar\nmov edx, 8; size\nmov rsi, r13; nmemb\nmov rdi, r12; base\ncall _qsort\nloc_1310:\nmov rax, [r12]\nmov ecx, [rax]\nmov esi, [rax+4]\nmov edx, [rax+8]\nmov edi, ebx\nsub edi, ecx\nmov eax, cs:dword_401C\nsub eax, cs:range_1\ncmp edi, eax\njge short loc_12C8\njmp short loc_12BC\nloc_1332:\nmov rdi, r12; ptr\ncall _free\nlea rax, range_1\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "int *__fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n int **v5; // r12\n __int64 v6; // rbp\n signed int v7; // ebx\n signed int *v8; // r13\n signed int *v9; // rbp\n __int64 v10; // rsi\n int v11; // edx\n __int64 v13; // [rsp+0h] [rbp-48h]\n int v14; // [rsp+Ch] [rbp-3Ch]\n\n v14 = a3;\n v13 = a3;\n v5 = (int **)malloc(8LL * a3);\n if ( a3 <= 0 )\n {\n v14 = 0;\n v7 = 0x80000000;\n }\n else\n {\n v6 = 0LL;\n v7 = 0x80000000;\n do\n {\n v8 = *(signed int **)(a1 + 8 * v6);\n v5[v6] = (int *)create_node((unsigned int)*v8, (unsigned int)v6, 0LL);\n if ( v7 < *v8 )\n v7 = *v8;\n ++v6;\n }\n while ( v13 != v6 );\n }\n qsort(v5, v14, 8uLL, compare_nodes);\n range_1 = 0;\n dword_401C = 0x7FFFFFFF;\n while ( 1 )\n {\n v10 = (unsigned int)(*v5)[1];\n v11 = (*v5)[2];\n if ( v7 - **v5 < dword_401C - range_1 )\n {\n range_1 = **v5;\n dword_401C = v7;\n }\n if ( *(_DWORD *)(a2 + 4LL * (int)v10) - 1 == v11 )\n break;\n v9 = (signed int *)(*(_QWORD *)(a1 + 8LL * (int)v10) + 4LL * v11 + 4);\n *v5 = (int *)create_node((unsigned int)*v9, v10, (unsigned int)(v11 + 1));\n if ( v7 < *v9 )\n v7 = *v9;\n qsort(v5, v14, 8uLL, compare_nodes);\n }\n free(v5);\n return &range_1;\n}", + "ida_strip_asm": "sub_120D:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov r14, rdi\nmov r15, rsi\nmov ebx, edx\nmov [rsp+48h+var_3C], edx\nmovsxd rax, edx\nmov [rsp+48h+var_48], rax\nlea rdi, ds:0[rax*8]; size\ncall _malloc\nmov r12, rax\ntest ebx, ebx\njle short loc_12AD\nmov ebp, 0\nmov ebx, 80000000h\nloc_1250:\nmov r13, [r14+rbp*8]\nmov edi, [r13+0]\nmov edx, 0\nmov esi, ebp\ncall sub_11E6\nmov [r12+rbp*8], rax\nmov eax, [r13+0]\ncmp ebx, eax\ncmovl ebx, eax\nadd rbp, 1\ncmp [rsp+48h+var_48], rbp\njnz short loc_1250\nloc_127B:\nmovsxd r13, [rsp+48h+var_3C]\nlea rcx, compar; compar\nmov edx, 8; size\nmov rsi, r13; nmemb\nmov rdi, r12; base\ncall _qsort\nmov cs:dword_4018, 0\nmov cs:dword_401C, 7FFFFFFFh\njmp short loc_1310\nloc_12AD:\nmov [rsp+48h+var_3C], 0\nmov ebx, 80000000h\njmp short loc_127B\nloc_12BC:\nmov cs:dword_4018, ecx\nmov cs:dword_401C, ebx\nloc_12C8:\nmovsxd rcx, esi\nmov eax, [r15+rcx*4]\nsub eax, 1\ncmp eax, edx\njz short loc_1332\nmovsxd rdi, edx\nmov rax, [r14+rcx*8]\nlea rbp, [rax+rdi*4+4]\nadd edx, 1\nmov edi, [rbp+0]\ncall sub_11E6\nmov [r12], rax\nmov eax, [rbp+0]\ncmp ebx, eax\ncmovl ebx, eax\nlea rcx, compar; compar\nmov edx, 8; size\nmov rsi, r13; nmemb\nmov rdi, r12; base\ncall _qsort\nloc_1310:\nmov rax, [r12]\nmov ecx, [rax]\nmov esi, [rax+4]\nmov edx, [rax+8]\nmov edi, ebx\nsub edi, ecx\nmov eax, cs:dword_401C\nsub eax, cs:dword_4018\ncmp edi, eax\njge short loc_12C8\njmp short loc_12BC\nloc_1332:\nmov rdi, r12; ptr\ncall _free\nlea rax, dword_4018\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "int *__fastcall sub_120D(__int64 a1, __int64 a2, int a3)\n{\n int **v5; // r12\n __int64 v6; // rbp\n signed int v7; // ebx\n signed int *v8; // r13\n signed int *v9; // rbp\n __int64 v10; // rsi\n int v11; // edx\n __int64 v13; // [rsp+0h] [rbp-48h]\n int v14; // [rsp+Ch] [rbp-3Ch]\n\n v14 = a3;\n v13 = a3;\n v5 = (int **)malloc(8LL * a3);\n if ( a3 <= 0 )\n {\n v14 = 0;\n v7 = 0x80000000;\n }\n else\n {\n v6 = 0LL;\n v7 = 0x80000000;\n do\n {\n v8 = *(signed int **)(a1 + 8 * v6);\n v5[v6] = (int *)sub_11E6((unsigned int)*v8, (unsigned int)v6, 0LL);\n if ( v7 < *v8 )\n v7 = *v8;\n ++v6;\n }\n while ( v13 != v6 );\n }\n qsort(v5, v14, 8uLL, compar);\n dword_4018 = 0;\n dword_401C = 0x7FFFFFFF;\n while ( 1 )\n {\n v10 = (unsigned int)(*v5)[1];\n v11 = (*v5)[2];\n if ( v7 - **v5 < dword_401C - dword_4018 )\n {\n dword_4018 = **v5;\n dword_401C = v7;\n }\n if ( *(_DWORD *)(a2 + 4LL * (int)v10) - 1 == v11 )\n break;\n v9 = (signed int *)(*(_QWORD *)(a1 + 8LL * (int)v10) + 4LL * v11 + 4);\n *v5 = (int *)sub_11E6((unsigned int)*v9, v10, (unsigned int)(v11 + 1));\n if ( v7 < *v9 )\n v7 = *v9;\n qsort(v5, v14, 8uLL, compar);\n }\n free(v5);\n return &dword_4018;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "int *sub_120D(long long a1, long long a2, int a3) {\n int **v5;\n long long v6;\n signed int v7;\n signed int *v8;\n signed int *v9;\n long long v10;\n int v11;\n long long v13;\n int v14;\n v14 = a3;\n v13 = a3;\n v5 = (int **)malloc(8LL * a3);\n if (a3 <= 0) {\n v14 = 0;\n v7 = 2147483648;\n } else {\n v6 = 0LL;\n v7 = 2147483648;\n do {\n v8 = *(signed int **)(a1 + 8 * v6);\n v5[v6] = (int *)sub_11E6((unsigned int)*v8, (unsigned int)v6, 0LL);\n if (v7 < *v8) v7 = *v8;\n ++v6;\n } while (v13 != v6);\n }\n qsort(v5, v14, 8uLL, compar);\n dword_4018 = 0;\n dword_401C = 2147483647;\n while (1) {\n v10 = (unsigned int)(*v5)[1];\n v11 = (*v5)[2];\n if (v7 - **v5 < dword_401C - dword_4018) {\n dword_4018 = **v5;\n dword_401C = v7;\n }\n if (*(uint32_t *)(a2 + 4LL * (int)v10) - 1 == v11) break;\n v9 = (signed int *)(*(uint64_t *)(a1 + 8LL * (int)v10) + 4LL * v11 + 4);\n *v5 = (int *)sub_11E6((unsigned int)*v9, v10, (unsigned int)(v11 + 1));\n if (v7 < *v9) v7 = *v9;\n qsort(v5, v14, 8uLL, compar);\n }\n free(v5);\n return &dword_4018;\n}", + "ida_pseudo_norm": "int *func0(long long a1, long long a2, int a3) {\n int **v5;\n long long v6;\n signed int v7;\n signed int *v8;\n signed int *v9;\n long long v10;\n int v11;\n long long v13;\n int v14;\n v14 = a3;\n v13 = a3;\n v5 = (int **)malloc(8LL * a3);\n if (a3 <= 0) {\n v14 = 0;\n v7 = 2147483648;\n } else {\n v6 = 0LL;\n v7 = 2147483648;\n do {\n v8 = *(signed int **)(a1 + 8 * v6);\n v5[v6] = (int *)create_node((unsigned int)*v8, (unsigned int)v6, 0LL);\n if (v7 < *v8) v7 = *v8;\n ++v6;\n } while (v13 != v6);\n }\n qsort(v5, v14, 8uLL, compare_nodes);\n range_1 = 0;\n dword_401C = 2147483647;\n while (1) {\n v10 = (unsigned int)(*v5)[1];\n v11 = (*v5)[2];\n if (v7 - **v5 < dword_401C - range_1) {\n range_1 = **v5;\n dword_401C = v7;\n }\n if (*(uint32_t *)(a2 + 4LL * (int)v10) - 1 == v11) break;\n v9 = (signed int *)(*(uint64_t *)(a1 + 8LL * (int)v10) + 4LL * v11 + 4);\n *v5 = (int *)create_node((unsigned int)*v9, v10, (unsigned int)(v11 + 1));\n if (v7 < *v9) v7 = *v9;\n qsort(v5, v14, 8uLL, compare_nodes);\n }\n free(v5);\n return &range_1;\n}" + }, + { + "index": 342, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct Node {\n\n int value;\n\n int list_num;\n\n int index;\n\n} Node;\n\n\n\nNode* create_node(int value, int list_num, int index) {\n\n Node* node = (Node*)malloc(sizeof(Node));\n\n node->value = value;\n\n node->list_num = list_num;\n\n node->index = index;\n\n return node;\n\n}\n\n\n\nint compare_nodes(const void *a, const void *b) {\n\n Node* node1 = *(Node**)a;\n\n Node* node2 = *(Node**)b;\n\n return (node1->value > node2->value) - (node1->value < node2->value);\n\n}\n\n\n\n", + "func": "int* func0(int** list, int* list_sizes, int numLists) {\n static int range[2];\n int high = INT_MIN;\n int i, j;\n Node** pq = malloc(numLists * sizeof(Node*));\n int pq_size = 0;\n for (i = 0; i < numLists; i++) {\n pq[pq_size++] = create_node(list[i][0], i, 0);\n if (list[i][0] > high) {\n high = list[i][0];\n }\n }\n qsort(pq, pq_size, sizeof(Node*), compare_nodes);\n range[0] = 0;\n range[1] = INT_MAX;\n while (1) {\n Node* top = pq[0];\n int low = top->value;\n i = top->list_num;\n j = top->index;\n if (high - low < range[1] - range[0]) {\n range[0] = low;\n range[1] = high;\n }\n if (j == list_sizes[i] - 1) {\n break;\n }\n pq[0] = create_node(list[i][j + 1], i, j + 1);\n if (list[i][j + 1] > high) {\n high = list[i][j + 1];\n }\n qsort(pq, pq_size, sizeof(Node*), compare_nodes);\n }\n free(pq);\n return range;\n}", + "test": "int main() {\n\n int list1[] = {3, 6, 8, 10, 15};\n\n int list2[] = {1, 5, 12};\n\n int list3[] = {4, 8, 15, 16};\n\n int list4[] = {2, 6};\n\n int* lists[] = {list1, list2, list3, list4};\n\n int sizes[] = {5, 3, 4, 2};\n\n int* result;\n\n\n\n result = func0(lists, sizes, 4);\n\n assert(result[0] == 4 && result[1] == 6);\n\n\n\n int list5[] = {4, 7, 9, 11, 16};\n\n int list6[] = {2, 6, 13};\n\n int list7[] = {5, 9, 16, 17};\n\n int list8[] = {3, 7};\n\n int* lists2[] = {list5, list6, list7, list8};\n\n int sizes2[] = {5, 3, 4, 2};\n\n\n\n result = func0(lists2, sizes2, 4);\n\n assert(result[0] == 5 && result[1] == 7);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\nmovslq %edx,%r13\npush %r12\nmov %rsi,%r12\npush %rbp\nmov %rdi,%rbp\nlea 0x0(,%r13,8),%rdi\npush %rbx\nsub $0x28,%rsp\ncallq 10d0 \nmov %rax,%r15\ntest %r13d,%r13d\njle 15f0 \nlea -0x1(%r13),%eax\nxor %r14d,%r14d\nmov $0x80000000,%ebx\nmov %rax,0x18(%rsp)\nnopl (%rax)\nmov 0x0(%rbp,%r14,8),%rcx\nmov $0xc,%edi\nmov (%rcx),%esi\nmov %rcx,0x10(%rsp)\nmov %esi,0xc(%rsp)\ncallq 10d0 \nmov 0xc(%rsp),%esi\nmov 0x10(%rsp),%rcx\nmov %r14d,0x4(%rax)\nmov %rax,(%r15,%r14,8)\nmov %esi,(%rax)\nmovl $0x0,0x8(%rax)\nmov (%rcx),%eax\ncmp %eax,%ebx\ncmovl %eax,%ebx\nmov %r14,%rax\nadd $0x1,%r14\ncmp %rax,0x18(%rsp)\njne 14a8 \nmov %r15,%rdi\nlea -0xeb(%rip),%rcx\nmov $0x8,%edx\nmov %r13,%rsi\ncallq 10a0 \nxor %edi,%edi\nmovabs $0x7fffffff00000000,%rax\nmov %rax,0x2afd(%rip)\nmov $0x7fffffff,%eax\njmp 1592 \nnopw 0x0(%rax,%rax,1)\nmov 0x0(%rbp,%rsi,8),%rax\nmovslq %edx,%rdi\nmov %edx,0x18(%rsp)\nlea 0x4(%rax,%rdi,4),%r14\nmov $0xc,%edi\nmov (%r14),%r8d\nmov %r8d,0x10(%rsp)\ncallq 10d0 \nmov 0x18(%rsp),%edx\nmov 0xc(%rsp),%ecx\nmov %r15,%rdi\nmov 0x10(%rsp),%r8d\nmov %rax,(%r15)\nmov %r13,%rsi\nadd $0x1,%edx\nmov %ecx,0x4(%rax)\nlea -0x15e(%rip),%rcx\nmov %edx,0x8(%rax)\nmov $0x8,%edx\nmov %r8d,(%rax)\nmov (%r14),%eax\ncmp %eax,%ebx\ncmovl %eax,%ebx\ncallq 10a0 \nmov 0x2a90(%rip),%eax\nmov 0x2a86(%rip),%edi\nmov (%r15),%rdx\nmov %ebx,%r8d\nsub %edi,%eax\nmov (%rdx),%esi\nmov 0x4(%rdx),%ecx\nmov 0x8(%rdx),%edx\nsub %esi,%r8d\ncmp %eax,%r8d\njge 15b6 \nmov %esi,0x2a68(%rip)\nmov %ebx,0x2a66(%rip)\nmovslq %ecx,%rsi\nmov %ecx,0xc(%rsp)\nmov (%r12,%rsi,4),%eax\nsub $0x1,%eax\ncmp %edx,%eax\njne 1528 \nmov %r15,%rdi\ncallq 1090 \nadd $0x28,%rsp\nlea 0x2a39(%rip),%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw 0x0(%rax,%rax,1)\nxor %r13d,%r13d\nmov $0x80000000,%ebx\njmpq 14f1 \nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14, rsi\npush r13\nmovsxd r13, edx\npush r12\nmov r12d, 80000000h\npush rbp\npush rbx\nxor ebx, ebx\nsub rsp, 18h\nmov [rsp+48h+var_48], rdi\nlea rdi, ds:0[r13*8]; size\ncall _malloc\nmov rbp, rax\ntest r13d, r13d\njle short loc_14BE\nnop dword ptr [rax+00000000h]\nloc_1470:\nmov rax, [rsp+48h+var_48]\nmovd xmm1, ebx\nmov edi, 0Ch; size\nmov r15, [rax+rbx*8]\nmovd xmm0, dword ptr [r15]\npunpckldq xmm0, xmm1\nmovq [rsp+48h+var_40], xmm0\ncall _malloc\nmovq xmm0, [rsp+48h+var_40]\nmov [rbp+rbx*8+0], rax\nmov dword ptr [rax+8], 0\nmovq qword ptr [rax], xmm0\nmov eax, [r15]\ncmp r12d, eax\ncmovl r12d, eax\nadd rbx, 1\ncmp r13, rbx\njnz short loc_1470\nloc_14BE:\nlea rcx, compare_nodes; compar\nmov rdi, rbp; base\nmov edx, 8; size\nmov rsi, rbx; nmemb\ncall _qsort\nmov rax, cs:qword_2078\nxor edi, edi\nmov ecx, 7FFFFFFFh\nmov cs:range_1, rax\njmp short loc_1563\nloc_14F0:\nmov rdx, [rsp+48h+var_48]\nmovsxd rdi, r13d\nmovd xmm2, eax\nmov rsi, [rdx+rsi*8]\nmovd xmm0, dword ptr [rsi+rdi*4+4]\nlea r15, [rsi+rdi*4+4]\nmov edi, 0Ch; size\npunpckldq xmm0, xmm2\nmovq [rsp+48h+var_40], xmm0\ncall _malloc\nlea edx, [r13+1]\nmov rdi, rbp; base\nmov rsi, rbx; nmemb\nmovq xmm0, [rsp+48h+var_40]\nmov [rax+8], edx\nlea rcx, compare_nodes; compar\nmov edx, 8; size\nmov [rbp+0], rax\nmovq qword ptr [rax], xmm0\nmov eax, [r15]\ncmp r12d, eax\ncmovl r12d, eax\ncall _qsort\nlea rax, range_1\nmov ecx, dword ptr cs:range_1+4\nmov edi, [rax]\nloc_1563:\nmov rdx, [rbp+0]\nmov r9d, r12d\nsub ecx, edi\nmov esi, [rdx]\nmov eax, [rdx+4]\nmov r13d, [rdx+8]\nsub r9d, esi\ncmp r9d, ecx\njge short loc_1595\nmovd xmm0, esi\nmovd xmm3, r12d\nlea rdi, range_1\npunpckldq xmm0, xmm3\nmovq qword ptr [rdi], xmm0\nloc_1595:\nmovsxd rsi, eax\nmov ecx, [r14+rsi*4]\nsub ecx, 1\ncmp ecx, r13d\njnz loc_14F0\nmov rdi, rbp; ptr\ncall _free\nadd rsp, 18h\nlea rax, range_1\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "__int64 *__fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n __int64 v4; // r13\n signed int v5; // r12d\n size_t v6; // rbx\n unsigned int **v7; // rbp\n unsigned int *v8; // r15\n unsigned int *v9; // rax\n unsigned __int64 v10; // xmm0_8\n int v11; // edi\n int v12; // ecx\n unsigned int *v13; // r15\n unsigned int *v14; // rax\n unsigned __int64 v15; // xmm0_8\n unsigned int v16; // esi\n signed int v17; // eax\n signed int v18; // r13d\n unsigned __int64 v21; // [rsp+8h] [rbp-40h]\n\n v4 = a3;\n v5 = 0x80000000;\n v6 = 0LL;\n v7 = (unsigned int **)malloc(8LL * a3);\n if ( (int)v4 > 0 )\n {\n do\n {\n v8 = *(unsigned int **)(a1 + 8 * v6);\n v21 = _mm_unpacklo_epi32(_mm_cvtsi32_si128(*v8), _mm_cvtsi32_si128(v6)).m128i_u64[0];\n v9 = (unsigned int *)malloc(0xCuLL);\n v10 = v21;\n v7[v6] = v9;\n v9[2] = 0;\n *(_QWORD *)v9 = v10;\n if ( v5 < (int)*v8 )\n v5 = *v8;\n ++v6;\n }\n while ( v4 != v6 );\n }\n qsort(v7, v6, 8uLL, compare_nodes);\n v11 = 0;\n v12 = 0x7FFFFFFF;\n for ( range_1 = 0x7FFFFFFF00000000LL; ; v11 = range_1 )\n {\n v16 = **v7;\n v17 = (*v7)[1];\n v18 = (*v7)[2];\n if ( (int)(v5 - v16) < v12 - v11 )\n range_1 = _mm_unpacklo_epi32(_mm_cvtsi32_si128(v16), _mm_cvtsi32_si128(v5)).m128i_u64[0];\n if ( *(_DWORD *)(a2 + 4LL * v17) - 1 == v18 )\n break;\n v13 = (unsigned int *)(*(_QWORD *)(a1 + 8LL * v17) + 4LL * v18 + 4);\n v21 = _mm_unpacklo_epi32(_mm_cvtsi32_si128(*v13), _mm_cvtsi32_si128(v17)).m128i_u64[0];\n v14 = (unsigned int *)malloc(0xCuLL);\n v15 = v21;\n v14[2] = v18 + 1;\n *v7 = v14;\n *(_QWORD *)v14 = v15;\n if ( v5 < (int)*v13 )\n v5 = *v13;\n qsort(v7, v6, 8uLL, compare_nodes);\n v12 = HIDWORD(range_1);\n }\n free(v7);\n return &range_1;\n}", + "ida_strip_asm": "sub_1430:\nendbr64\npush r15\npush r14\nmov r14, rsi\npush r13\nmovsxd r13, edx\npush r12\nmov r12d, 80000000h\npush rbp\npush rbx\nxor ebx, ebx\nsub rsp, 18h\nmov [rsp+48h+var_48], rdi\nlea rdi, ds:0[r13*8]; size\ncall _malloc\nmov rbp, rax\ntest r13d, r13d\njle short loc_14BE\nnop dword ptr [rax+00000000h]\nloc_1470:\nmov rax, [rsp+48h+var_48]\nmovd xmm1, ebx\nmov edi, 0Ch; size\nmov r15, [rax+rbx*8]\nmovd xmm0, dword ptr [r15]\npunpckldq xmm0, xmm1\nmovq [rsp+48h+var_40], xmm0\ncall _malloc\nmovq xmm0, [rsp+48h+var_40]\nmov [rbp+rbx*8+0], rax\nmov dword ptr [rax+8], 0\nmovq qword ptr [rax], xmm0\nmov eax, [r15]\ncmp r12d, eax\ncmovl r12d, eax\nadd rbx, 1\ncmp r13, rbx\njnz short loc_1470\nloc_14BE:\nlea rcx, compar; compar\nmov rdi, rbp; base\nmov edx, 8; size\nmov rsi, rbx; nmemb\ncall _qsort\nmov rax, cs:qword_2078\nxor edi, edi\nmov ecx, 7FFFFFFFh\nmov cs:qword_4018, rax\njmp short loc_1563\nloc_14F0:\nmov rdx, [rsp+48h+var_48]\nmovsxd rdi, r13d\nmovd xmm2, eax\nmov rsi, [rdx+rsi*8]\nmovd xmm0, dword ptr [rsi+rdi*4+4]\nlea r15, [rsi+rdi*4+4]\nmov edi, 0Ch; size\npunpckldq xmm0, xmm2\nmovq [rsp+48h+var_40], xmm0\ncall _malloc\nlea edx, [r13+1]\nmov rdi, rbp; base\nmov rsi, rbx; nmemb\nmovq xmm0, [rsp+48h+var_40]\nmov [rax+8], edx\nlea rcx, compar; compar\nmov edx, 8; size\nmov [rbp+0], rax\nmovq qword ptr [rax], xmm0\nmov eax, [r15]\ncmp r12d, eax\ncmovl r12d, eax\ncall _qsort\nlea rax, qword_4018\nmov ecx, dword ptr cs:qword_4018+4\nmov edi, [rax]\nloc_1563:\nmov rdx, [rbp+0]\nmov r9d, r12d\nsub ecx, edi\nmov esi, [rdx]\nmov eax, [rdx+4]\nmov r13d, [rdx+8]\nsub r9d, esi\ncmp r9d, ecx\njge short loc_1595\nmovd xmm0, esi\nmovd xmm3, r12d\nlea rdi, qword_4018\npunpckldq xmm0, xmm3\nmovq qword ptr [rdi], xmm0\nloc_1595:\nmovsxd rsi, eax\nmov ecx, [r14+rsi*4]\nsub ecx, 1\ncmp ecx, r13d\njnz loc_14F0\nmov rdi, rbp; ptr\ncall _free\nadd rsp, 18h\nlea rax, qword_4018\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "__int64 *__fastcall sub_1430(__int64 a1, __int64 a2, int a3)\n{\n __int64 v4; // r13\n signed int v5; // r12d\n size_t v6; // rbx\n unsigned int **v7; // rbp\n unsigned int *v8; // r15\n unsigned int *v9; // rax\n unsigned __int64 v10; // xmm0_8\n int v11; // edi\n int v12; // ecx\n unsigned int *v13; // r15\n unsigned int *v14; // rax\n unsigned __int64 v15; // xmm0_8\n unsigned int v16; // esi\n signed int v17; // eax\n signed int v18; // r13d\n unsigned __int64 v21; // [rsp+8h] [rbp-40h]\n\n v4 = a3;\n v5 = 0x80000000;\n v6 = 0LL;\n v7 = (unsigned int **)malloc(8LL * a3);\n if ( (int)v4 > 0 )\n {\n do\n {\n v8 = *(unsigned int **)(a1 + 8 * v6);\n v21 = _mm_unpacklo_epi32(_mm_cvtsi32_si128(*v8), _mm_cvtsi32_si128(v6)).m128i_u64[0];\n v9 = (unsigned int *)malloc(0xCuLL);\n v10 = v21;\n v7[v6] = v9;\n v9[2] = 0;\n *(_QWORD *)v9 = v10;\n if ( v5 < (int)*v8 )\n v5 = *v8;\n ++v6;\n }\n while ( v4 != v6 );\n }\n qsort(v7, v6, 8uLL, compar);\n v11 = 0;\n v12 = 0x7FFFFFFF;\n for ( qword_4018 = 0x7FFFFFFF00000000LL; ; v11 = qword_4018 )\n {\n v16 = **v7;\n v17 = (*v7)[1];\n v18 = (*v7)[2];\n if ( (int)(v5 - v16) < v12 - v11 )\n qword_4018 = _mm_unpacklo_epi32(_mm_cvtsi32_si128(v16), _mm_cvtsi32_si128(v5)).m128i_u64[0];\n if ( *(_DWORD *)(a2 + 4LL * v17) - 1 == v18 )\n break;\n v13 = (unsigned int *)(*(_QWORD *)(a1 + 8LL * v17) + 4LL * v18 + 4);\n v21 = _mm_unpacklo_epi32(_mm_cvtsi32_si128(*v13), _mm_cvtsi32_si128(v17)).m128i_u64[0];\n v14 = (unsigned int *)malloc(0xCuLL);\n v15 = v21;\n v14[2] = v18 + 1;\n *v7 = v14;\n *(_QWORD *)v14 = v15;\n if ( v5 < (int)*v13 )\n v5 = *v13;\n qsort(v7, v6, 8uLL, compar);\n v12 = HIDWORD(qword_4018);\n }\n free(v7);\n return &qword_4018;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long *sub_1430(long long a1, long long a2, int a3) {\n long long v4;\n signed int v5;\n unsigned int v6;\n unsigned int **v7;\n unsigned int *v8;\n unsigned int *v9;\n unsigned long long v10;\n int v11;\n int v12;\n unsigned int *v13;\n unsigned int *v14;\n unsigned long long v15;\n unsigned int v16;\n signed int v17;\n signed int v18;\n unsigned long long v21;\n v4 = a3;\n v5 = 2147483648;\n v6 = 0LL;\n v7 = (unsigned int **)malloc(8LL * a3);\n if ((int)v4 > 0) {\n do {\n v8 = *(unsigned int **)(a1 + 8 * v6);\n v21 = _mm_unpacklo_epi32(_mm_cvtsi32_si128(*v8), _mm_cvtsi32_si128(v6))\n .m128i_u64[0];\n v9 = (unsigned int *)malloc(12uLL);\n v10 = v21;\n v7[v6] = v9;\n v9[2] = 0;\n *(uint64_t *)v9 = v10;\n if (v5 < (int)*v8) v5 = *v8;\n ++v6;\n } while (v4 != v6);\n }\n qsort(v7, v6, 8uLL, compar);\n v11 = 0;\n v12 = 2147483647;\n for (qword_4018 = 9223372032559808512LL;; v11 = qword_4018) {\n v16 = **v7;\n v17 = (*v7)[1];\n v18 = (*v7)[2];\n if ((int)(v5 - v16) < v12 - v11)\n qword_4018 =\n _mm_unpacklo_epi32(_mm_cvtsi32_si128(v16), _mm_cvtsi32_si128(v5))\n .m128i_u64[0];\n if (*(uint32_t *)(a2 + 4LL * v17) - 1 == v18) break;\n v13 = (unsigned int *)(*(uint64_t *)(a1 + 8LL * v17) + 4LL * v18 + 4);\n v21 = _mm_unpacklo_epi32(_mm_cvtsi32_si128(*v13), _mm_cvtsi32_si128(v17))\n .m128i_u64[0];\n v14 = (unsigned int *)malloc(12uLL);\n v15 = v21;\n v14[2] = v18 + 1;\n *v7 = v14;\n *(uint64_t *)v14 = v15;\n if (v5 < (int)*v13) v5 = *v13;\n qsort(v7, v6, 8uLL, compar);\n v12 = HIDWORD(qword_4018);\n }\n free(v7);\n return &qword_4018;\n}", + "ida_pseudo_norm": "long long *func0(long long a1, long long a2, int a3) {\n long long v4;\n signed int v5;\n unsigned int v6;\n unsigned int **v7;\n unsigned int *v8;\n unsigned int *v9;\n unsigned long long v10;\n int v11;\n int v12;\n unsigned int *v13;\n unsigned int *v14;\n unsigned long long v15;\n unsigned int v16;\n signed int v17;\n signed int v18;\n unsigned long long v21;\n v4 = a3;\n v5 = 2147483648;\n v6 = 0LL;\n v7 = (unsigned int **)malloc(8LL * a3);\n if ((int)v4 > 0) {\n do {\n v8 = *(unsigned int **)(a1 + 8 * v6);\n v21 = _mm_unpacklo_epi32(_mm_cvtsi32_si128(*v8), _mm_cvtsi32_si128(v6))\n .m128i_u64[0];\n v9 = (unsigned int *)malloc(12uLL);\n v10 = v21;\n v7[v6] = v9;\n v9[2] = 0;\n *(uint64_t *)v9 = v10;\n if (v5 < (int)*v8) v5 = *v8;\n ++v6;\n } while (v4 != v6);\n }\n qsort(v7, v6, 8uLL, compare_nodes);\n v11 = 0;\n v12 = 2147483647;\n for (range_1 = 9223372032559808512LL;; v11 = range_1) {\n v16 = **v7;\n v17 = (*v7)[1];\n v18 = (*v7)[2];\n if ((int)(v5 - v16) < v12 - v11)\n range_1 =\n _mm_unpacklo_epi32(_mm_cvtsi32_si128(v16), _mm_cvtsi32_si128(v5))\n .m128i_u64[0];\n if (*(uint32_t *)(a2 + 4LL * v17) - 1 == v18) break;\n v13 = (unsigned int *)(*(uint64_t *)(a1 + 8LL * v17) + 4LL * v18 + 4);\n v21 = _mm_unpacklo_epi32(_mm_cvtsi32_si128(*v13), _mm_cvtsi32_si128(v17))\n .m128i_u64[0];\n v14 = (unsigned int *)malloc(12uLL);\n v15 = v21;\n v14[2] = v18 + 1;\n *v7 = v14;\n *(uint64_t *)v14 = v15;\n if (v5 < (int)*v13) v5 = *v13;\n qsort(v7, v6, 8uLL, compare_nodes);\n v12 = HIDWORD(range_1);\n }\n free(v7);\n return &range_1;\n}" + }, + { + "index": 342, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct Node {\n\n int value;\n\n int list_num;\n\n int index;\n\n} Node;\n\n\n\nNode* create_node(int value, int list_num, int index) {\n\n Node* node = (Node*)malloc(sizeof(Node));\n\n node->value = value;\n\n node->list_num = list_num;\n\n node->index = index;\n\n return node;\n\n}\n\n\n\nint compare_nodes(const void *a, const void *b) {\n\n Node* node1 = *(Node**)a;\n\n Node* node2 = *(Node**)b;\n\n return (node1->value > node2->value) - (node1->value < node2->value);\n\n}\n\n\n\n", + "func": "int* func0(int** list, int* list_sizes, int numLists) {\n static int range[2];\n int high = INT_MIN;\n int i, j;\n Node** pq = malloc(numLists * sizeof(Node*));\n int pq_size = 0;\n for (i = 0; i < numLists; i++) {\n pq[pq_size++] = create_node(list[i][0], i, 0);\n if (list[i][0] > high) {\n high = list[i][0];\n }\n }\n qsort(pq, pq_size, sizeof(Node*), compare_nodes);\n range[0] = 0;\n range[1] = INT_MAX;\n while (1) {\n Node* top = pq[0];\n int low = top->value;\n i = top->list_num;\n j = top->index;\n if (high - low < range[1] - range[0]) {\n range[0] = low;\n range[1] = high;\n }\n if (j == list_sizes[i] - 1) {\n break;\n }\n pq[0] = create_node(list[i][j + 1], i, j + 1);\n if (list[i][j + 1] > high) {\n high = list[i][j + 1];\n }\n qsort(pq, pq_size, sizeof(Node*), compare_nodes);\n }\n free(pq);\n return range;\n}", + "test": "int main() {\n\n int list1[] = {3, 6, 8, 10, 15};\n\n int list2[] = {1, 5, 12};\n\n int list3[] = {4, 8, 15, 16};\n\n int list4[] = {2, 6};\n\n int* lists[] = {list1, list2, list3, list4};\n\n int sizes[] = {5, 3, 4, 2};\n\n int* result;\n\n\n\n result = func0(lists, sizes, 4);\n\n assert(result[0] == 4 && result[1] == 6);\n\n\n\n int list5[] = {4, 7, 9, 11, 16};\n\n int list6[] = {2, 6, 13};\n\n int list7[] = {5, 9, 16, 17};\n\n int list8[] = {3, 7};\n\n int* lists2[] = {list5, list6, list7, list8};\n\n int sizes2[] = {5, 3, 4, 2};\n\n\n\n result = func0(lists2, sizes2, 4);\n\n assert(result[0] == 5 && result[1] == 7);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\nmovslq %edx,%r14\npush %r13\nmov %rsi,%r13\npush %r12\npush %rbp\nmov %rdi,%rbp\nlea 0x0(,%r14,8),%rdi\npush %rbx\nsub $0x28,%rsp\ncallq 10d0 \nmov %rax,%r15\ntest %r14d,%r14d\njle 15d0 \nlea -0x1(%r14),%eax\nxor %r12d,%r12d\nmov $0x80000000,%ebx\nmov %rax,0x18(%rsp)\nnopl (%rax)\nmov 0x0(%rbp,%r12,8),%rcx\nmov $0xc,%edi\nmov (%rcx),%esi\nmov %rcx,0x10(%rsp)\nmov %esi,0xc(%rsp)\ncallq 10d0 \nmov 0xc(%rsp),%esi\nmov 0x10(%rsp),%rcx\nmov %r12d,0x4(%rax)\nmov %rax,(%r15,%r12,8)\nmov %esi,(%rax)\nmovl $0x0,0x8(%rax)\nmov (%rcx),%eax\ncmp %eax,%ebx\ncmovl %eax,%ebx\nmov %r12,%rax\nadd $0x1,%r12\ncmp %rax,0x18(%rsp)\njne 1468 \nmov %r15,%rdi\nlea -0xeb(%rip),%rcx\nmov $0x8,%edx\nmov %r14,%rsi\ncallq 10a0 \nxor %edi,%edi\nmovabs $0x7fffffff00000000,%rax\nmov %rax,0x2b3d(%rip)\nmov $0x7fffffff,%eax\njmpq 157d \nnopl (%rax)\nlea 0x2b29(%rip),%rax\nmov %ebx,0x2b27(%rip)\nmov %esi,(%rax)\nmovslq %ecx,%rax\nmov 0x0(%r13,%rax,4),%edi\nlea -0x1(%rdi),%esi\ncmp %esi,%edx\nje 15ac \nmov 0x0(%rbp,%rax,8),%rax\nmovslq %edx,%rsi\nmov $0xc,%edi\nmov %ecx,0x18(%rsp)\nmov %edx,0x10(%rsp)\nlea 0x4(%rax,%rsi,4),%r12\nmov (%r12),%r8d\nmov %r8d,0xc(%rsp)\ncallq 10d0 \nmov 0x10(%rsp),%edx\nmov 0x18(%rsp),%ecx\nmov %r15,%rdi\nmov 0xc(%rsp),%r8d\nmov %rax,(%r15)\nmov %r14,%rsi\nadd $0x1,%edx\nmov %ecx,0x4(%rax)\nlea -0x185(%rip),%rcx\nmov %edx,0x8(%rax)\nmov $0x8,%edx\nmov %r8d,(%rax)\nmov (%r12),%eax\ncmp %eax,%ebx\ncmovl %eax,%ebx\ncallq 10a0 \nlea 0x2aa3(%rip),%rdi\nmov 0x2aa1(%rip),%eax\nmov (%rdi),%edi\nmov (%r15),%rdx\nmov %ebx,%r8d\nsub %edi,%eax\nmov (%rdx),%esi\nmov 0x4(%rdx),%ecx\nmov 0x8(%rdx),%edx\nsub %esi,%r8d\ncmp %eax,%r8d\njl 14e8 \nmovslq %ecx,%rax\nmov 0x0(%r13,%rax,4),%edi\nlea -0x1(%rdi),%esi\ncmp %edx,%esi\njne 150a \nmov %r15,%rdi\ncallq 1090 \nadd $0x28,%rsp\nlea 0x2a59(%rip),%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw 0x0(%rax,%rax,1)\nxor %r14d,%r14d\nmov $0x80000000,%ebx\njmpq 14b1 \nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14, rsi\npush r13\nmovsxd r13, edx\npush r12\nmov r12d, 80000000h\npush rbp\npush rbx\nxor ebx, ebx\nsub rsp, 18h\nmov [rsp+48h+var_48], rdi\nlea rdi, ds:0[r13*8]; size\ncall _malloc\nmov rbp, rax\ntest r13d, r13d\njle short loc_14BE\nnop dword ptr [rax+00000000h]\nloc_1470:\nmov rax, [rsp+48h+var_48]\nmovd xmm1, ebx\nmov edi, 0Ch; size\nmov r15, [rax+rbx*8]\nmovd xmm0, dword ptr [r15]\npunpckldq xmm0, xmm1\nmovq [rsp+48h+var_40], xmm0\ncall _malloc\nmovq xmm0, [rsp+48h+var_40]\nmov [rbp+rbx*8+0], rax\nmov dword ptr [rax+8], 0\nmovq qword ptr [rax], xmm0\nmov eax, [r15]\ncmp r12d, eax\ncmovl r12d, eax\nadd rbx, 1\ncmp r13, rbx\njnz short loc_1470\nloc_14BE:\nlea rcx, compare_nodes; compar\nmov rdi, rbp; base\nmov edx, 8; size\nmov rsi, rbx; nmemb\ncall _qsort\nmov rax, cs:qword_2078\nxor edi, edi\nmov ecx, 7FFFFFFFh\nmov cs:range_1, rax\njmp loc_158E\nloc_14F0:\nmovd xmm0, esi\nmovd xmm3, r12d\nlea rcx, range_1\npunpckldq xmm0, xmm3\nmovq qword ptr [rcx], xmm0\nmovsxd rcx, eax\nmov edi, [r14+rcx*4]\nlea esi, [rdi-1]\ncmp esi, r13d\njz loc_15BF\nloc_151B:\nmov rdx, [rsp+48h+var_48]\nmovsxd rdi, r13d\nmovd xmm2, eax\nmov rsi, [rdx+rcx*8]\nmovd xmm0, dword ptr [rsi+rdi*4+4]\nlea r15, [rsi+rdi*4+4]\nmov edi, 0Ch; size\npunpckldq xmm0, xmm2\nmovq [rsp+48h+var_40], xmm0\ncall _malloc\nlea edx, [r13+1]\nmov rdi, rbp; base\nmov rsi, rbx; nmemb\nmovq xmm0, [rsp+48h+var_40]\nmov [rax+8], edx\nlea rcx, compare_nodes; compar\nmov edx, 8; size\nmov [rbp+0], rax\nmovq qword ptr [rax], xmm0\nmov eax, [r15]\ncmp r12d, eax\ncmovl r12d, eax\ncall _qsort\nlea rax, range_1\nmov ecx, dword ptr cs:range_1+4\nmov edi, [rax]\nloc_158E:\nmov rdx, [rbp+0]\nmov r9d, r12d\nsub ecx, edi\nmov esi, [rdx]\nmov eax, [rdx+4]\nmov r13d, [rdx+8]\nsub r9d, esi\ncmp r9d, ecx\njl loc_14F0\nmovsxd rcx, eax\nmov esi, [r14+rcx*4]\nsub esi, 1\ncmp esi, r13d\njnz loc_151B\nloc_15BF:\nmov rdi, rbp; ptr\ncall _free\nadd rsp, 18h\nlea rax, range_1\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "__int64 *__fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n __int64 v4; // r13\n signed int v5; // r12d\n size_t v6; // rbx\n unsigned int **v7; // rbp\n unsigned int *v8; // r15\n unsigned int *v9; // rax\n unsigned __int64 v10; // xmm0_8\n int v11; // edi\n int v12; // ecx\n __int64 v13; // rcx\n unsigned int *v14; // r15\n unsigned int *v15; // rax\n unsigned __int64 v16; // xmm0_8\n unsigned int v17; // esi\n signed int v18; // eax\n signed int v19; // r13d\n unsigned __int64 v22; // [rsp+8h] [rbp-40h]\n\n v4 = a3;\n v5 = 0x80000000;\n v6 = 0LL;\n v7 = (unsigned int **)malloc(8LL * a3);\n if ( (int)v4 > 0 )\n {\n do\n {\n v8 = *(unsigned int **)(a1 + 8 * v6);\n v22 = _mm_unpacklo_epi32(_mm_cvtsi32_si128(*v8), _mm_cvtsi32_si128(v6)).m128i_u64[0];\n v9 = (unsigned int *)malloc(0xCuLL);\n v10 = v22;\n v7[v6] = v9;\n v9[2] = 0;\n *(_QWORD *)v9 = v10;\n if ( v5 < (int)*v8 )\n v5 = *v8;\n ++v6;\n }\n while ( v4 != v6 );\n }\n qsort(v7, v6, 8uLL, compare_nodes);\n v11 = 0;\n v12 = 0x7FFFFFFF;\n for ( range_1 = 0x7FFFFFFF00000000LL; ; v11 = range_1 )\n {\n v17 = **v7;\n v18 = (*v7)[1];\n v19 = (*v7)[2];\n if ( (int)(v5 - v17) >= v12 - v11 )\n break;\n range_1 = _mm_unpacklo_epi32(_mm_cvtsi32_si128(v17), _mm_cvtsi32_si128(v5)).m128i_u64[0];\n v13 = v18;\n if ( *(_DWORD *)(a2 + 4LL * v18) - 1 == v19 )\n goto LABEL_12;\nLABEL_7:\n v14 = (unsigned int *)(*(_QWORD *)(a1 + 8 * v13) + 4LL * v19 + 4);\n v22 = _mm_unpacklo_epi32(_mm_cvtsi32_si128(*v14), _mm_cvtsi32_si128(v18)).m128i_u64[0];\n v15 = (unsigned int *)malloc(0xCuLL);\n v16 = v22;\n v15[2] = v19 + 1;\n *v7 = v15;\n *(_QWORD *)v15 = v16;\n if ( v5 < (int)*v14 )\n v5 = *v14;\n qsort(v7, v6, 8uLL, compare_nodes);\n v12 = HIDWORD(range_1);\n }\n v13 = v18;\n if ( *(_DWORD *)(a2 + 4LL * v18) - 1 != v19 )\n goto LABEL_7;\nLABEL_12:\n free(v7);\n return &range_1;\n}", + "ida_strip_asm": "sub_1430:\nendbr64\npush r15\npush r14\nmov r14, rsi\npush r13\nmovsxd r13, edx\npush r12\nmov r12d, 80000000h\npush rbp\npush rbx\nxor ebx, ebx\nsub rsp, 18h\nmov [rsp+48h+var_48], rdi\nlea rdi, ds:0[r13*8]; size\ncall _malloc\nmov rbp, rax\ntest r13d, r13d\njle short loc_14BE\nnop dword ptr [rax+00000000h]\nloc_1470:\nmov rax, [rsp+48h+var_48]\nmovd xmm1, ebx\nmov edi, 0Ch; size\nmov r15, [rax+rbx*8]\nmovd xmm0, dword ptr [r15]\npunpckldq xmm0, xmm1\nmovq [rsp+48h+var_40], xmm0\ncall _malloc\nmovq xmm0, [rsp+48h+var_40]\nmov [rbp+rbx*8+0], rax\nmov dword ptr [rax+8], 0\nmovq qword ptr [rax], xmm0\nmov eax, [r15]\ncmp r12d, eax\ncmovl r12d, eax\nadd rbx, 1\ncmp r13, rbx\njnz short loc_1470\nloc_14BE:\nlea rcx, compar; compar\nmov rdi, rbp; base\nmov edx, 8; size\nmov rsi, rbx; nmemb\ncall _qsort\nmov rax, cs:qword_2078\nxor edi, edi\nmov ecx, 7FFFFFFFh\nmov cs:qword_4018, rax\njmp loc_158E\nloc_14F0:\nmovd xmm0, esi\nmovd xmm3, r12d\nlea rcx, qword_4018\npunpckldq xmm0, xmm3\nmovq qword ptr [rcx], xmm0\nmovsxd rcx, eax\nmov edi, [r14+rcx*4]\nlea esi, [rdi-1]\ncmp esi, r13d\njz loc_15BF\nloc_151B:\nmov rdx, [rsp+48h+var_48]\nmovsxd rdi, r13d\nmovd xmm2, eax\nmov rsi, [rdx+rcx*8]\nmovd xmm0, dword ptr [rsi+rdi*4+4]\nlea r15, [rsi+rdi*4+4]\nmov edi, 0Ch; size\npunpckldq xmm0, xmm2\nmovq [rsp+48h+var_40], xmm0\ncall _malloc\nlea edx, [r13+1]\nmov rdi, rbp; base\nmov rsi, rbx; nmemb\nmovq xmm0, [rsp+48h+var_40]\nmov [rax+8], edx\nlea rcx, compar; compar\nmov edx, 8; size\nmov [rbp+0], rax\nmovq qword ptr [rax], xmm0\nmov eax, [r15]\ncmp r12d, eax\ncmovl r12d, eax\ncall _qsort\nlea rax, qword_4018\nmov ecx, dword ptr cs:qword_4018+4\nmov edi, [rax]\nloc_158E:\nmov rdx, [rbp+0]\nmov r9d, r12d\nsub ecx, edi\nmov esi, [rdx]\nmov eax, [rdx+4]\nmov r13d, [rdx+8]\nsub r9d, esi\ncmp r9d, ecx\njl loc_14F0\nmovsxd rcx, eax\nmov esi, [r14+rcx*4]\nsub esi, 1\ncmp esi, r13d\njnz loc_151B\nloc_15BF:\nmov rdi, rbp; ptr\ncall _free\nadd rsp, 18h\nlea rax, qword_4018\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "__int64 *__fastcall sub_1430(__int64 a1, __int64 a2, int a3)\n{\n __int64 v4; // r13\n signed int v5; // r12d\n size_t v6; // rbx\n unsigned int **v7; // rbp\n unsigned int *v8; // r15\n unsigned int *v9; // rax\n unsigned __int64 v10; // xmm0_8\n int v11; // edi\n int v12; // ecx\n __int64 v13; // rcx\n unsigned int *v14; // r15\n unsigned int *v15; // rax\n unsigned __int64 v16; // xmm0_8\n unsigned int v17; // esi\n signed int v18; // eax\n signed int v19; // r13d\n unsigned __int64 v22; // [rsp+8h] [rbp-40h]\n\n v4 = a3;\n v5 = 0x80000000;\n v6 = 0LL;\n v7 = (unsigned int **)malloc(8LL * a3);\n if ( (int)v4 > 0 )\n {\n do\n {\n v8 = *(unsigned int **)(a1 + 8 * v6);\n v22 = _mm_unpacklo_epi32(_mm_cvtsi32_si128(*v8), _mm_cvtsi32_si128(v6)).m128i_u64[0];\n v9 = (unsigned int *)malloc(0xCuLL);\n v10 = v22;\n v7[v6] = v9;\n v9[2] = 0;\n *(_QWORD *)v9 = v10;\n if ( v5 < (int)*v8 )\n v5 = *v8;\n ++v6;\n }\n while ( v4 != v6 );\n }\n qsort(v7, v6, 8uLL, compar);\n v11 = 0;\n v12 = 0x7FFFFFFF;\n for ( qword_4018 = 0x7FFFFFFF00000000LL; ; v11 = qword_4018 )\n {\n v17 = **v7;\n v18 = (*v7)[1];\n v19 = (*v7)[2];\n if ( (int)(v5 - v17) >= v12 - v11 )\n break;\n qword_4018 = _mm_unpacklo_epi32(_mm_cvtsi32_si128(v17), _mm_cvtsi32_si128(v5)).m128i_u64[0];\n v13 = v18;\n if ( *(_DWORD *)(a2 + 4LL * v18) - 1 == v19 )\n goto LABEL_12;\nLABEL_7:\n v14 = (unsigned int *)(*(_QWORD *)(a1 + 8 * v13) + 4LL * v19 + 4);\n v22 = _mm_unpacklo_epi32(_mm_cvtsi32_si128(*v14), _mm_cvtsi32_si128(v18)).m128i_u64[0];\n v15 = (unsigned int *)malloc(0xCuLL);\n v16 = v22;\n v15[2] = v19 + 1;\n *v7 = v15;\n *(_QWORD *)v15 = v16;\n if ( v5 < (int)*v14 )\n v5 = *v14;\n qsort(v7, v6, 8uLL, compar);\n v12 = HIDWORD(qword_4018);\n }\n v13 = v18;\n if ( *(_DWORD *)(a2 + 4LL * v18) - 1 != v19 )\n goto LABEL_7;\nLABEL_12:\n free(v7);\n return &qword_4018;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long *sub_1430(long long a1, long long a2, int a3) {\n long long v4;\n signed int v5;\n unsigned int v6;\n unsigned int **v7;\n unsigned int *v8;\n unsigned int *v9;\n unsigned long long v10;\n int v11;\n int v12;\n long long v13;\n unsigned int *v14;\n unsigned int *v15;\n unsigned long long v16;\n unsigned int v17;\n signed int v18;\n signed int v19;\n unsigned long long v22;\n v4 = a3;\n v5 = 2147483648;\n v6 = 0LL;\n v7 = (unsigned int **)malloc(8LL * a3);\n if ((int)v4 > 0) {\n do {\n v8 = *(unsigned int **)(a1 + 8 * v6);\n v22 = _mm_unpacklo_epi32(_mm_cvtsi32_si128(*v8), _mm_cvtsi32_si128(v6))\n .m128i_u64[0];\n v9 = (unsigned int *)malloc(12uLL);\n v10 = v22;\n v7[v6] = v9;\n v9[2] = 0;\n *(uint64_t *)v9 = v10;\n if (v5 < (int)*v8) v5 = *v8;\n ++v6;\n } while (v4 != v6);\n }\n qsort(v7, v6, 8uLL, compar);\n v11 = 0;\n v12 = 2147483647;\n for (qword_4018 = 9223372032559808512LL;; v11 = qword_4018) {\n v17 = **v7;\n v18 = (*v7)[1];\n v19 = (*v7)[2];\n if ((int)(v5 - v17) >= v12 - v11) break;\n qword_4018 =\n _mm_unpacklo_epi32(_mm_cvtsi32_si128(v17), _mm_cvtsi32_si128(v5))\n .m128i_u64[0];\n v13 = v18;\n if (*(uint32_t *)(a2 + 4LL * v18) - 1 == v19) goto LABEL_12;\n LABEL_7:\n v14 = (unsigned int *)(*(uint64_t *)(a1 + 8 * v13) + 4LL * v19 + 4);\n v22 = _mm_unpacklo_epi32(_mm_cvtsi32_si128(*v14), _mm_cvtsi32_si128(v18))\n .m128i_u64[0];\n v15 = (unsigned int *)malloc(12uLL);\n v16 = v22;\n v15[2] = v19 + 1;\n *v7 = v15;\n *(uint64_t *)v15 = v16;\n if (v5 < (int)*v14) v5 = *v14;\n qsort(v7, v6, 8uLL, compar);\n v12 = HIDWORD(qword_4018);\n }\n v13 = v18;\n if (*(uint32_t *)(a2 + 4LL * v18) - 1 != v19) goto LABEL_7;\nLABEL_12:\n free(v7);\n return &qword_4018;\n}", + "ida_pseudo_norm": "long long *func0(long long a1, long long a2, int a3) {\n long long v4;\n signed int v5;\n unsigned int v6;\n unsigned int **v7;\n unsigned int *v8;\n unsigned int *v9;\n unsigned long long v10;\n int v11;\n int v12;\n long long v13;\n unsigned int *v14;\n unsigned int *v15;\n unsigned long long v16;\n unsigned int v17;\n signed int v18;\n signed int v19;\n unsigned long long v22;\n v4 = a3;\n v5 = 2147483648;\n v6 = 0LL;\n v7 = (unsigned int **)malloc(8LL * a3);\n if ((int)v4 > 0) {\n do {\n v8 = *(unsigned int **)(a1 + 8 * v6);\n v22 = _mm_unpacklo_epi32(_mm_cvtsi32_si128(*v8), _mm_cvtsi32_si128(v6))\n .m128i_u64[0];\n v9 = (unsigned int *)malloc(12uLL);\n v10 = v22;\n v7[v6] = v9;\n v9[2] = 0;\n *(uint64_t *)v9 = v10;\n if (v5 < (int)*v8) v5 = *v8;\n ++v6;\n } while (v4 != v6);\n }\n qsort(v7, v6, 8uLL, compare_nodes);\n v11 = 0;\n v12 = 2147483647;\n for (range_1 = 9223372032559808512LL;; v11 = range_1) {\n v17 = **v7;\n v18 = (*v7)[1];\n v19 = (*v7)[2];\n if ((int)(v5 - v17) >= v12 - v11) break;\n range_1 = _mm_unpacklo_epi32(_mm_cvtsi32_si128(v17), _mm_cvtsi32_si128(v5))\n .m128i_u64[0];\n v13 = v18;\n if (*(uint32_t *)(a2 + 4LL * v18) - 1 == v19) goto LABEL_12;\n LABEL_7:\n v14 = (unsigned int *)(*(uint64_t *)(a1 + 8 * v13) + 4LL * v19 + 4);\n v22 = _mm_unpacklo_epi32(_mm_cvtsi32_si128(*v14), _mm_cvtsi32_si128(v18))\n .m128i_u64[0];\n v15 = (unsigned int *)malloc(12uLL);\n v16 = v22;\n v15[2] = v19 + 1;\n *v7 = v15;\n *(uint64_t *)v15 = v16;\n if (v5 < (int)*v14) v5 = *v14;\n qsort(v7, v6, 8uLL, compare_nodes);\n v12 = HIDWORD(range_1);\n }\n v13 = v18;\n if (*(uint32_t *)(a2 + 4LL * v18) - 1 != v19) goto LABEL_7;\nLABEL_12:\n free(v7);\n return &range_1;\n}" + }, + { + "index": 343, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(const char *s, int *letters, int *digits) {\n int l = 0, d = 0;\n while (*s) {\n if (isdigit((unsigned char)*s))\n d++;\n else if (isalpha((unsigned char)*s))\n l++;\n s++;\n }\n *letters = l;\n *digits = d;\n}", + "test": "int main() {\n\n int letters, digits;\n\n\n\n func0(\"python\", &letters, &digits);\n\n assert(letters == 6 && digits == 0);\n\n\n\n func0(\"program\", &letters, &digits);\n\n assert(letters == 7 && digits == 0);\n\n\n\n func0(\"python3.0\", &letters, &digits);\n\n assert(letters == 6 && digits == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %rdx,-0x28(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 120e \ncallq 1090 <__ctype_b_loc@plt>\nmov (%rax),%rdx\nmov -0x18(%rbp),%rax\nmovzbl (%rax),%eax\nmovzbl %al,%eax\nadd %rax,%rax\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x800,%eax\ntest %eax,%eax\nje 11de \naddl $0x1,-0x4(%rbp)\njmp 1209 \ncallq 1090 <__ctype_b_loc@plt>\nmov (%rax),%rdx\nmov -0x18(%rbp),%rax\nmovzbl (%rax),%eax\nmovzbl %al,%eax\nadd %rax,%rax\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x400,%eax\ntest %eax,%eax\nje 1209 \naddl $0x1,-0x8(%rbp)\naddq $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 11b1 \nmov -0x20(%rbp),%rax\nmov -0x8(%rbp),%edx\nmov %edx,(%rax)\nmov -0x28(%rbp),%rax\nmov -0x4(%rbp),%edx\nmov %edx,(%rax)\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_28], rdx\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_120E\nloc_11B1:\ncall ___ctype_b_loc\nmov rdx, [rax]\nmov rax, [rbp+var_18]\nmovzx eax, byte ptr [rax]\nmovzx eax, al\nadd rax, rax\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 800h\ntest eax, eax\njz short loc_11DE\nadd [rbp+var_4], 1\njmp short loc_1209\nloc_11DE:\ncall ___ctype_b_loc\nmov rdx, [rax]\nmov rax, [rbp+var_18]\nmovzx eax, byte ptr [rax]\nmovzx eax, al\nadd rax, rax\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 400h\ntest eax, eax\njz short loc_1209\nadd [rbp+var_8], 1\nloc_1209:\nadd [rbp+var_18], 1\nloc_120E:\nmov rax, [rbp+var_18]\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_11B1\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_8]\nmov [rax], edx\nmov rax, [rbp+var_28]\nmov edx, [rbp+var_4]\nmov [rax], edx\nnop\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(_BYTE *a1, _DWORD *a2, _DWORD *a3)\n{\n _DWORD *result; // rax\n int v6; // [rsp+28h] [rbp-8h]\n int v7; // [rsp+2Ch] [rbp-4h]\n\n v6 = 0;\n v7 = 0;\n while ( *a1 )\n {\n if ( ((*__ctype_b_loc())[(unsigned __int8)*a1] & 0x800) != 0 )\n {\n ++v7;\n }\n else if ( ((*__ctype_b_loc())[(unsigned __int8)*a1] & 0x400) != 0 )\n {\n ++v6;\n }\n ++a1;\n }\n *a2 = v6;\n result = a3;\n *a3 = v7;\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_28], rdx\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_120E\nloc_11B1:\ncall ___ctype_b_loc\nmov rdx, [rax]\nmov rax, [rbp+var_18]\nmovzx eax, byte ptr [rax]\nmovzx eax, al\nadd rax, rax\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 800h\ntest eax, eax\njz short loc_11DE\nadd [rbp+var_4], 1\njmp short loc_1209\nloc_11DE:\ncall ___ctype_b_loc\nmov rdx, [rax]\nmov rax, [rbp+var_18]\nmovzx eax, byte ptr [rax]\nmovzx eax, al\nadd rax, rax\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 400h\ntest eax, eax\njz short loc_1209\nadd [rbp+var_8], 1\nloc_1209:\nadd [rbp+var_18], 1\nloc_120E:\nmov rax, [rbp+var_18]\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_11B1\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_8]\nmov [rax], edx\nmov rax, [rbp+var_28]\nmov edx, [rbp+var_4]\nmov [rax], edx\nnop\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1189(_BYTE *a1, _DWORD *a2, _DWORD *a3)\n{\n _DWORD *result; // rax\n int v6; // [rsp+28h] [rbp-8h]\n int v7; // [rsp+2Ch] [rbp-4h]\n\n v6 = 0;\n v7 = 0;\n while ( *a1 )\n {\n if ( ((*__ctype_b_loc())[(unsigned __int8)*a1] & 0x800) != 0 )\n {\n ++v7;\n }\n else if ( ((*__ctype_b_loc())[(unsigned __int8)*a1] & 0x400) != 0 )\n {\n ++v6;\n }\n ++a1;\n }\n *a2 = v6;\n result = a3;\n *a3 = v7;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1189(uint8_t *a1, uint32_t *a2, uint32_t *a3) {\n uint32_t *result;\n int v6;\n int v7;\n v6 = 0;\n v7 = 0;\n while (*a1) {\n if (((*__ctype_b_loc())[(unsigned char)*a1] & 2048) != 0) {\n ++v7;\n } else if (((*__ctype_b_loc())[(unsigned char)*a1] & 1024) != 0) {\n ++v6;\n }\n ++a1;\n }\n *a2 = v6;\n result = a3;\n *a3 = v7;\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(uint8_t *a1, uint32_t *a2, uint32_t *a3) {\n uint32_t *result;\n int v6;\n int v7;\n v6 = 0;\n v7 = 0;\n while (*a1) {\n if (((*__ctype_b_loc())[(unsigned char)*a1] & 2048) != 0) {\n ++v7;\n } else if (((*__ctype_b_loc())[(unsigned char)*a1] & 1024) != 0) {\n ++v6;\n }\n ++a1;\n }\n *a2 = v6;\n result = a3;\n *a3 = v7;\n return result;\n}" + }, + { + "index": 343, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(const char *s, int *letters, int *digits) {\n int l = 0, d = 0;\n while (*s) {\n if (isdigit((unsigned char)*s))\n d++;\n else if (isalpha((unsigned char)*s))\n l++;\n s++;\n }\n *letters = l;\n *digits = d;\n}", + "test": "int main() {\n\n int letters, digits;\n\n\n\n func0(\"python\", &letters, &digits);\n\n assert(letters == 6 && digits == 0);\n\n\n\n func0(\"program\", &letters, &digits);\n\n assert(letters == 7 && digits == 0);\n\n\n\n func0(\"python3.0\", &letters, &digits);\n\n assert(letters == 6 && digits == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rsi,%r13\nmov %rdx,%r12\nmovzbl (%rdi),%ebx\ntest %bl,%bl\nje 11e3 \nmov %rdi,%rbp\ncallq 1090 <__ctype_b_loc@plt>\nmov (%rax),%rsi\nmov $0x0,%edx\nmov $0x0,%ecx\njmp 11d2 \nand $0x400,%ax\ncmp $0x1,%ax\nsbb $0xffffffff,%ecx\nadd $0x1,%rbp\nmovzbl 0x0(%rbp),%ebx\ntest %bl,%bl\nje 11ed \nmovzbl %bl,%ebx\nmovzwl (%rsi,%rbx,2),%eax\ntest $0x8,%ah\nje 11bb \nadd $0x1,%edx\njmp 11c6 \nmov $0x0,%edx\nmov $0x0,%ecx\nmov %ecx,0x0(%r13)\nmov %edx,(%r12)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r13, rsi\nmov r12, rdx\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_11E3\nmov rbp, rdi\ncall ___ctype_b_loc\nmov rsi, [rax]\nmov edx, 0\nmov ecx, 0\njmp short loc_11D2\nloc_11BB:\nand ax, 400h\ncmp ax, 1\nsbb ecx, 0FFFFFFFFh\nloc_11C6:\nadd rbp, 1\nmovzx ebx, byte ptr [rbp+0]\ntest bl, bl\njz short loc_11ED\nloc_11D2:\nmovzx ebx, bl\nmovzx eax, word ptr [rsi+rbx*2]\ntest ah, 8\njz short loc_11BB\nadd edx, 1\njmp short loc_11C6\nloc_11E3:\nmov edx, 0\nmov ecx, 0\nloc_11ED:\nmov [r13+0], ecx\nmov [r12], edx\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "void __fastcall func0(unsigned __int8 *a1, _DWORD *a2, _DWORD *a3)\n{\n unsigned __int8 v5; // bl\n unsigned __int8 *v6; // rbp\n const unsigned __int16 *v7; // rsi\n int v8; // edx\n int v9; // ecx\n unsigned __int16 v10; // ax\n\n v5 = *a1;\n if ( *a1 )\n {\n v6 = a1;\n v7 = *__ctype_b_loc();\n v8 = 0;\n v9 = 0;\n do\n {\n v10 = v7[v5];\n if ( (v10 & 0x800) != 0 )\n ++v8;\n else\n v9 -= ((v10 & 0x400) == 0) - 1;\n v5 = *++v6;\n }\n while ( *v6 );\n }\n else\n {\n v8 = 0;\n v9 = 0;\n }\n *a2 = v9;\n *a3 = v8;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r13, rsi\nmov r12, rdx\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_11E3\nmov rbp, rdi\ncall ___ctype_b_loc\nmov rsi, [rax]\nmov edx, 0\nmov ecx, 0\njmp short loc_11D2\nloc_11BB:\nand ax, 400h\ncmp ax, 1\nsbb ecx, 0FFFFFFFFh\nloc_11C6:\nadd rbp, 1\nmovzx ebx, byte ptr [rbp+0]\ntest bl, bl\njz short loc_11ED\nloc_11D2:\nmovzx ebx, bl\nmovzx eax, word ptr [rsi+rbx*2]\ntest ah, 8\njz short loc_11BB\nadd edx, 1\njmp short loc_11C6\nloc_11E3:\nmov edx, 0\nmov ecx, 0\nloc_11ED:\nmov [r13+0], ecx\nmov [r12], edx\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "void __fastcall sub_1189(unsigned __int8 *a1, _DWORD *a2, _DWORD *a3)\n{\n unsigned __int8 v5; // bl\n unsigned __int8 *v6; // rbp\n const unsigned __int16 *v7; // rsi\n int v8; // edx\n int v9; // ecx\n unsigned __int16 v10; // ax\n\n v5 = *a1;\n if ( *a1 )\n {\n v6 = a1;\n v7 = *__ctype_b_loc();\n v8 = 0;\n v9 = 0;\n do\n {\n v10 = v7[v5];\n if ( (v10 & 0x800) != 0 )\n ++v8;\n else\n v9 -= ((v10 & 0x400) == 0) - 1;\n v5 = *++v6;\n }\n while ( *v6 );\n }\n else\n {\n v8 = 0;\n v9 = 0;\n }\n *a2 = v9;\n *a3 = v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1189(unsigned char *a1, uint32_t *a2, uint32_t *a3) {\n unsigned char v5;\n unsigned char *v6;\n const unsigned short *v7;\n int v8;\n int v9;\n unsigned short v10;\n v5 = *a1;\n if (*a1) {\n v6 = a1;\n v7 = *__ctype_b_loc();\n v8 = 0;\n v9 = 0;\n do {\n v10 = v7[v5];\n if ((v10 & 2048) != 0)\n ++v8;\n else\n v9 -= ((v10 & 1024) == 0) - 1;\n v5 = *++v6;\n } while (*v6);\n } else {\n v8 = 0;\n v9 = 0;\n }\n *a2 = v9;\n *a3 = v8;\n}", + "ida_pseudo_norm": "void func0(unsigned char *a1, uint32_t *a2, uint32_t *a3) {\n unsigned char v5;\n unsigned char *v6;\n const unsigned short *v7;\n int v8;\n int v9;\n unsigned short v10;\n v5 = *a1;\n if (*a1) {\n v6 = a1;\n v7 = *__ctype_b_loc();\n v8 = 0;\n v9 = 0;\n do {\n v10 = v7[v5];\n if ((v10 & 2048) != 0)\n ++v8;\n else\n v9 -= ((v10 & 1024) == 0) - 1;\n v5 = *++v6;\n } while (*v6);\n } else {\n v8 = 0;\n v9 = 0;\n }\n *a2 = v9;\n *a3 = v8;\n}" + }, + { + "index": 343, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(const char *s, int *letters, int *digits) {\n int l = 0, d = 0;\n while (*s) {\n if (isdigit((unsigned char)*s))\n d++;\n else if (isalpha((unsigned char)*s))\n l++;\n s++;\n }\n *letters = l;\n *digits = d;\n}", + "test": "int main() {\n\n int letters, digits;\n\n\n\n func0(\"python\", &letters, &digits);\n\n assert(letters == 6 && digits == 0);\n\n\n\n func0(\"program\", &letters, &digits);\n\n assert(letters == 7 && digits == 0);\n\n\n\n func0(\"python3.0\", &letters, &digits);\n\n assert(letters == 6 && digits == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov %rsi,%r13\npush %r12\nmov %rdx,%r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmovzbl (%rdi),%ebx\ntest %bl,%bl\nje 1308 \nmov %rdi,%rbp\ncallq 1090 <__ctype_b_loc@plt>\nxor %ecx,%ecx\nxor %edi,%edi\nmov (%rax),%r8\njmp 12cf \nnopl 0x0(%rax)\nmovzbl 0x1(%rbp),%ebx\nadd $0x1,%rbp\nadd $0x1,%ecx\ntest %bl,%bl\nje 12f0 \nmovzwl (%r8,%rbx,2),%eax\ntest $0x8,%ah\njne 12c0 \nand $0x400,%ax\ncmp $0x1,%ax\nsbb $0xffffffff,%edi\nmovzbl 0x1(%rbp),%ebx\nadd $0x1,%rbp\ntest %bl,%bl\njne 12cf \nmov %edi,0x0(%r13)\nmov %ecx,(%r12)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax,%rax,1)\nxor %ecx,%ecx\nxor %edi,%edi\njmp 12f0 \nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r13\nmov r13, rsi\npush r12\nmov r12, rdx\npush rbp\npush rbx\nsub rsp, 8\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_1308\nmov rbp, rdi\ncall ___ctype_b_loc\nxor ecx, ecx\nxor edi, edi\nmov r8, [rax]\njmp short loc_12CF\nloc_12C0:\nmovzx ebx, byte ptr [rbp+1]\nadd rbp, 1\nadd ecx, 1\ntest bl, bl\njz short loc_12F0\nloc_12CF:\nmovzx eax, word ptr [r8+rbx*2]\ntest ah, 8\njnz short loc_12C0\nand ax, 400h\ncmp ax, 1\nsbb edi, 0FFFFFFFFh\nmovzx ebx, byte ptr [rbp+1]\nadd rbp, 1\ntest bl, bl\njnz short loc_12CF\nloc_12F0:\nmov [r13+0], edi\nmov [r12], ecx\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1308:\nxor ecx, ecx\nxor edi, edi\njmp short loc_12F0", + "ida_pseudo": "void __fastcall func0(unsigned __int8 *a1, _DWORD *a2, _DWORD *a3)\n{\n __int64 v4; // rbx\n unsigned __int8 *v5; // rbp\n const unsigned __int16 **v6; // rax\n int v7; // ecx\n int v8; // edi\n const unsigned __int16 *v9; // r8\n unsigned __int16 v10; // ax\n\n v4 = *a1;\n if ( (_BYTE)v4 )\n {\n v5 = a1;\n v6 = __ctype_b_loc();\n v7 = 0;\n v8 = 0;\n v9 = *v6;\n do\n {\n while ( 1 )\n {\n v10 = v9[v4];\n if ( (v10 & 0x800) == 0 )\n break;\n v4 = *++v5;\n ++v7;\n if ( !(_BYTE)v4 )\n goto LABEL_6;\n }\n v8 -= ((v10 & 0x400) == 0) - 1;\n v4 = *++v5;\n }\n while ( (_BYTE)v4 );\n }\n else\n {\n v7 = 0;\n v8 = 0;\n }\nLABEL_6:\n *a2 = v8;\n *a3 = v7;\n}", + "ida_strip_asm": "sub_1290:\nendbr64\npush r13\nmov r13, rsi\npush r12\nmov r12, rdx\npush rbp\npush rbx\nsub rsp, 8\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_1308\nmov rbp, rdi\ncall ___ctype_b_loc\nxor ecx, ecx\nxor edi, edi\nmov r8, [rax]\njmp short loc_12CF\nloc_12C0:\nmovzx ebx, byte ptr [rbp+1]\nadd rbp, 1\nadd ecx, 1\ntest bl, bl\njz short loc_12F0\nloc_12CF:\nmovzx eax, word ptr [r8+rbx*2]\ntest ah, 8\njnz short loc_12C0\nand ax, 400h\ncmp ax, 1\nsbb edi, 0FFFFFFFFh\nmovzx ebx, byte ptr [rbp+1]\nadd rbp, 1\ntest bl, bl\njnz short loc_12CF\nloc_12F0:\nmov [r13+0], edi\nmov [r12], ecx\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1308:\nxor ecx, ecx\nxor edi, edi\njmp short loc_12F0", + "ida_strip_pseudo": "void __fastcall sub_1290(unsigned __int8 *a1, _DWORD *a2, _DWORD *a3)\n{\n __int64 v4; // rbx\n unsigned __int8 *v5; // rbp\n const unsigned __int16 **v6; // rax\n int v7; // ecx\n int v8; // edi\n const unsigned __int16 *v9; // r8\n unsigned __int16 v10; // ax\n\n v4 = *a1;\n if ( (_BYTE)v4 )\n {\n v5 = a1;\n v6 = __ctype_b_loc();\n v7 = 0;\n v8 = 0;\n v9 = *v6;\n do\n {\n while ( 1 )\n {\n v10 = v9[v4];\n if ( (v10 & 0x800) == 0 )\n break;\n v4 = *++v5;\n ++v7;\n if ( !(_BYTE)v4 )\n goto LABEL_6;\n }\n v8 -= ((v10 & 0x400) == 0) - 1;\n v4 = *++v5;\n }\n while ( (_BYTE)v4 );\n }\n else\n {\n v7 = 0;\n v8 = 0;\n }\nLABEL_6:\n *a2 = v8;\n *a3 = v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1290(unsigned char *a1, uint32_t *a2, uint32_t *a3) {\n long long v4;\n unsigned char *v5;\n const unsigned short **v6;\n int v7;\n int v8;\n const unsigned short *v9;\n unsigned short v10;\n v4 = *a1;\n if ((uint8_t)v4) {\n v5 = a1;\n v6 = __ctype_b_loc();\n v7 = 0;\n v8 = 0;\n v9 = *v6;\n do {\n while (1) {\n v10 = v9[v4];\n if ((v10 & 2048) == 0) break;\n v4 = *++v5;\n ++v7;\n if (!(uint8_t)v4) goto LABEL_6;\n }\n v8 -= ((v10 & 1024) == 0) - 1;\n v4 = *++v5;\n } while ((uint8_t)v4);\n } else {\n v7 = 0;\n v8 = 0;\n }\nLABEL_6:\n *a2 = v8;\n *a3 = v7;\n}", + "ida_pseudo_norm": "void func0(unsigned char *a1, uint32_t *a2, uint32_t *a3) {\n long long v4;\n unsigned char *v5;\n const unsigned short **v6;\n int v7;\n int v8;\n const unsigned short *v9;\n unsigned short v10;\n v4 = *a1;\n if ((uint8_t)v4) {\n v5 = a1;\n v6 = __ctype_b_loc();\n v7 = 0;\n v8 = 0;\n v9 = *v6;\n do {\n while (1) {\n v10 = v9[v4];\n if ((v10 & 2048) == 0) break;\n v4 = *++v5;\n ++v7;\n if (!(uint8_t)v4) goto LABEL_6;\n }\n v8 -= ((v10 & 1024) == 0) - 1;\n v4 = *++v5;\n } while ((uint8_t)v4);\n } else {\n v7 = 0;\n v8 = 0;\n }\nLABEL_6:\n *a2 = v8;\n *a3 = v7;\n}" + }, + { + "index": 343, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(const char *s, int *letters, int *digits) {\n int l = 0, d = 0;\n while (*s) {\n if (isdigit((unsigned char)*s))\n d++;\n else if (isalpha((unsigned char)*s))\n l++;\n s++;\n }\n *letters = l;\n *digits = d;\n}", + "test": "int main() {\n\n int letters, digits;\n\n\n\n func0(\"python\", &letters, &digits);\n\n assert(letters == 6 && digits == 0);\n\n\n\n func0(\"program\", &letters, &digits);\n\n assert(letters == 7 && digits == 0);\n\n\n\n func0(\"python3.0\", &letters, &digits);\n\n assert(letters == 6 && digits == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov %rsi,%r13\npush %r12\nmov %rdx,%r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmovzbl (%rdi),%ebx\ntest %bl,%bl\nje 1308 \nmov %rdi,%rbp\ncallq 1090 <__ctype_b_loc@plt>\nxor %ecx,%ecx\nxor %edi,%edi\nmov (%rax),%r8\njmp 12cf \nnopl 0x0(%rax)\nmovzbl 0x1(%rbp),%ebx\nadd $0x1,%rbp\nadd $0x1,%ecx\ntest %bl,%bl\nje 12f0 \nmovzwl (%r8,%rbx,2),%eax\ntest $0x8,%ah\njne 12c0 \nand $0x400,%ax\ncmp $0x1,%ax\nsbb $0xffffffff,%edi\nmovzbl 0x1(%rbp),%ebx\nadd $0x1,%rbp\ntest %bl,%bl\njne 12cf \nmov %edi,0x0(%r13)\nmov %ecx,(%r12)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax,%rax,1)\nxor %ecx,%ecx\nxor %edi,%edi\njmp 12f0 \nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r13\nmov r13, rsi\npush r12\nmov r12, rdx\npush rbp\npush rbx\nsub rsp, 8\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_1308\nmov rbp, rdi\ncall ___ctype_b_loc\nxor ecx, ecx\nxor edi, edi\nmov r8, [rax]\njmp short loc_12CF\nloc_12C0:\nmovzx ebx, byte ptr [rbp+1]\nadd rbp, 1\nadd ecx, 1\ntest bl, bl\njz short loc_12F0\nloc_12CF:\nmovzx eax, word ptr [r8+rbx*2]\ntest ah, 8\njnz short loc_12C0\nand ax, 400h\ncmp ax, 1\nsbb edi, 0FFFFFFFFh\nmovzx ebx, byte ptr [rbp+1]\nadd rbp, 1\ntest bl, bl\njnz short loc_12CF\nloc_12F0:\nmov [r13+0], edi\nmov [r12], ecx\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1308:\nxor ecx, ecx\nxor edi, edi\njmp short loc_12F0", + "ida_pseudo": "void __fastcall func0(unsigned __int8 *a1, _DWORD *a2, _DWORD *a3)\n{\n __int64 v4; // rbx\n unsigned __int8 *v5; // rbp\n const unsigned __int16 **v6; // rax\n int v7; // ecx\n int v8; // edi\n const unsigned __int16 *v9; // r8\n unsigned __int16 v10; // ax\n\n v4 = *a1;\n if ( (_BYTE)v4 )\n {\n v5 = a1;\n v6 = __ctype_b_loc();\n v7 = 0;\n v8 = 0;\n v9 = *v6;\n do\n {\n while ( 1 )\n {\n v10 = v9[v4];\n if ( (v10 & 0x800) == 0 )\n break;\n v4 = *++v5;\n ++v7;\n if ( !(_BYTE)v4 )\n goto LABEL_6;\n }\n v8 -= ((v10 & 0x400) == 0) - 1;\n v4 = *++v5;\n }\n while ( (_BYTE)v4 );\n }\n else\n {\n v7 = 0;\n v8 = 0;\n }\nLABEL_6:\n *a2 = v8;\n *a3 = v7;\n}", + "ida_strip_asm": "sub_1290:\nendbr64\npush r13\nmov r13, rsi\npush r12\nmov r12, rdx\npush rbp\npush rbx\nsub rsp, 8\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_1308\nmov rbp, rdi\ncall ___ctype_b_loc\nxor ecx, ecx\nxor edi, edi\nmov r8, [rax]\njmp short loc_12CF\nloc_12C0:\nmovzx ebx, byte ptr [rbp+1]\nadd rbp, 1\nadd ecx, 1\ntest bl, bl\njz short loc_12F0\nloc_12CF:\nmovzx eax, word ptr [r8+rbx*2]\ntest ah, 8\njnz short loc_12C0\nand ax, 400h\ncmp ax, 1\nsbb edi, 0FFFFFFFFh\nmovzx ebx, byte ptr [rbp+1]\nadd rbp, 1\ntest bl, bl\njnz short loc_12CF\nloc_12F0:\nmov [r13+0], edi\nmov [r12], ecx\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1308:\nxor ecx, ecx\nxor edi, edi\njmp short loc_12F0", + "ida_strip_pseudo": "void __fastcall sub_1290(unsigned __int8 *a1, _DWORD *a2, _DWORD *a3)\n{\n __int64 v4; // rbx\n unsigned __int8 *v5; // rbp\n const unsigned __int16 **v6; // rax\n int v7; // ecx\n int v8; // edi\n const unsigned __int16 *v9; // r8\n unsigned __int16 v10; // ax\n\n v4 = *a1;\n if ( (_BYTE)v4 )\n {\n v5 = a1;\n v6 = __ctype_b_loc();\n v7 = 0;\n v8 = 0;\n v9 = *v6;\n do\n {\n while ( 1 )\n {\n v10 = v9[v4];\n if ( (v10 & 0x800) == 0 )\n break;\n v4 = *++v5;\n ++v7;\n if ( !(_BYTE)v4 )\n goto LABEL_6;\n }\n v8 -= ((v10 & 0x400) == 0) - 1;\n v4 = *++v5;\n }\n while ( (_BYTE)v4 );\n }\n else\n {\n v7 = 0;\n v8 = 0;\n }\nLABEL_6:\n *a2 = v8;\n *a3 = v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1290(unsigned char *a1, uint32_t *a2, uint32_t *a3) {\n long long v4;\n unsigned char *v5;\n const unsigned short **v6;\n int v7;\n int v8;\n const unsigned short *v9;\n unsigned short v10;\n v4 = *a1;\n if ((uint8_t)v4) {\n v5 = a1;\n v6 = __ctype_b_loc();\n v7 = 0;\n v8 = 0;\n v9 = *v6;\n do {\n while (1) {\n v10 = v9[v4];\n if ((v10 & 2048) == 0) break;\n v4 = *++v5;\n ++v7;\n if (!(uint8_t)v4) goto LABEL_6;\n }\n v8 -= ((v10 & 1024) == 0) - 1;\n v4 = *++v5;\n } while ((uint8_t)v4);\n } else {\n v7 = 0;\n v8 = 0;\n }\nLABEL_6:\n *a2 = v8;\n *a3 = v7;\n}", + "ida_pseudo_norm": "void func0(unsigned char *a1, uint32_t *a2, uint32_t *a3) {\n long long v4;\n unsigned char *v5;\n const unsigned short **v6;\n int v7;\n int v8;\n const unsigned short *v9;\n unsigned short v10;\n v4 = *a1;\n if ((uint8_t)v4) {\n v5 = a1;\n v6 = __ctype_b_loc();\n v7 = 0;\n v8 = 0;\n v9 = *v6;\n do {\n while (1) {\n v10 = v9[v4];\n if ((v10 & 2048) == 0) break;\n v4 = *++v5;\n ++v7;\n if (!(uint8_t)v4) goto LABEL_6;\n }\n v8 -= ((v10 & 1024) == 0) - 1;\n v4 = *++v5;\n } while ((uint8_t)v4);\n } else {\n v7 = 0;\n v8 = 0;\n }\nLABEL_6:\n *a2 = v8;\n *a3 = v7;\n}" + }, + { + "index": 344, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n, int m) { return (int)sqrt(m) - (int)sqrt(n - 1); }", + "test": "int main() {\n\n assert(func0(5, 100) == 8);\n\n assert(func0(8, 65) == 6);\n\n assert(func0(2, 5) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x18,%rsp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\ncvtsi2sdl -0x18(%rbp),%xmm0\ncallq 1070 \ncvttsd2si %xmm0,%ebx\nmov -0x14(%rbp),%eax\nsub $0x1,%eax\ncvtsi2sd %eax,%xmm0\ncallq 1070 \ncvttsd2si %xmm0,%eax\nsub %eax,%ebx\nmov %ebx,%eax\nadd $0x18,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 18h\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_18]\nmovq rax, xmm1\nmovq xmm0, rax; x\ncall _sqrt\ncvttsd2si ebx, xmm0\nmov eax, [rbp+var_14]\nsub eax, 1\npxor xmm2, xmm2\ncvtsi2sd xmm2, eax\nmovq rax, xmm2\nmovq xmm0, rax; x\ncall _sqrt\ncvttsd2si eax, xmm0\nmov edx, ebx\nsub edx, eax\nmov eax, edx\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n int v2; // ebx\n\n v2 = (int)sqrt((double)a2);\n return (unsigned int)(v2 - (int)sqrt((double)(a1 - 1)));\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 18h\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_18]\nmovq rax, xmm1\nmovq xmm0, rax; x\ncall _sqrt\ncvttsd2si ebx, xmm0\nmov eax, [rbp+var_14]\nsub eax, 1\npxor xmm2, xmm2\ncvtsi2sd xmm2, eax\nmovq rax, xmm2\nmovq xmm0, rax; x\ncall _sqrt\ncvttsd2si eax, xmm0\nmov edx, ebx\nsub edx, eax\nmov eax, edx\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1, int a2)\n{\n int v2; // ebx\n\n v2 = (int)sqrt((double)a2);\n return (unsigned int)(v2 - (int)sqrt((double)(a1 - 1)));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1, int a2) {\n int v2;\n v2 = (int)sqrt((double)a2);\n return (unsigned int)(v2 - (int)sqrt((double)(a1 - 1)));\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n int v2;\n v2 = (int)sqrt((double)a2);\n return (unsigned int)(v2 - (int)sqrt((double)(a1 - 1)));\n}" + }, + { + "index": 344, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n, int m) { return (int)sqrt(m) - (int)sqrt(n - 1); }", + "test": "int main() {\n\n assert(func0(5, 100) == 8);\n\n assert(func0(8, 65) == 6);\n\n assert(func0(2, 5) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov %edi,%ebx\npxor %xmm0,%xmm0\ncvtsi2sd %esi,%xmm0\nmovapd %xmm0,%xmm2\nsqrtsd %xmm2,%xmm2\nmovsd %xmm2,0x8(%rsp)\npxor %xmm1,%xmm1\nucomisd %xmm0,%xmm1\nja 11cf \ncvttsd2si 0x8(%rsp),%ebp\nsub $0x1,%ebx\npxor %xmm0,%xmm0\ncvtsi2sd %ebx,%xmm0\nmovapd %xmm0,%xmm3\nsqrtsd %xmm3,%xmm3\nmovsd %xmm3,0x8(%rsp)\npxor %xmm1,%xmm1\nucomisd %xmm0,%xmm1\nja 11d6 \ncvttsd2si 0x8(%rsp),%eax\nsub %eax,%ebp\nmov %ebp,%eax\nadd $0x18,%rsp\npop %rbx\npop %rbp\nretq\ncallq 1070 \njmp 1195 \ncallq 1070 \njmp 11be \n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov ebx, edi\npxor xmm0, xmm0\ncvtsi2sd xmm0, esi; x\npxor xmm1, xmm1\nucomisd xmm1, xmm0\nja short loc_11B7\nsqrtsd xmm0, xmm0\nloc_118B:\ncvttsd2si ebp, xmm0\nsub ebx, 1\npxor xmm0, xmm0\ncvtsi2sd xmm0, ebx; x\npxor xmm1, xmm1\nucomisd xmm1, xmm0\nja short loc_11BE\nsqrtsd xmm0, xmm0\nloc_11A8:\ncvttsd2si edx, xmm0\nmov eax, ebp\nsub eax, edx\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_11B7:\ncall _sqrt\njmp short loc_118B\nloc_11BE:\ncall _sqrt\njmp short loc_11A8", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n double v2; // xmm0_8\n double v3; // xmm0_8\n int v4; // ebp\n double v5; // xmm0_8\n double v6; // xmm0_8\n\n v2 = (double)a2;\n if ( (double)a2 < 0.0 )\n v3 = sqrt(v2);\n else\n v3 = sqrt(v2);\n v4 = (int)v3;\n v5 = (double)(a1 - 1);\n if ( v5 < 0.0 )\n v6 = sqrt(v5);\n else\n v6 = sqrt(v5);\n return (unsigned int)(v4 - (int)v6);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov ebx, edi\npxor xmm0, xmm0\ncvtsi2sd xmm0, esi; x\npxor xmm1, xmm1\nucomisd xmm1, xmm0\nja short loc_11B7\nsqrtsd xmm0, xmm0\nloc_118B:\ncvttsd2si ebp, xmm0\nsub ebx, 1\npxor xmm0, xmm0\ncvtsi2sd xmm0, ebx; x\npxor xmm1, xmm1\nucomisd xmm1, xmm0\nja short loc_11BE\nsqrtsd xmm0, xmm0\nloc_11A8:\ncvttsd2si edx, xmm0\nmov eax, ebp\nsub eax, edx\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_11B7:\ncall _sqrt\njmp short loc_118B\nloc_11BE:\ncall _sqrt\njmp short loc_11A8", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1, int a2)\n{\n double v2; // xmm0_8\n double v3; // xmm0_8\n int v4; // ebp\n double v5; // xmm0_8\n double v6; // xmm0_8\n\n v2 = (double)a2;\n if ( (double)a2 < 0.0 )\n v3 = sqrt(v2);\n else\n v3 = sqrt(v2);\n v4 = (int)v3;\n v5 = (double)(a1 - 1);\n if ( v5 < 0.0 )\n v6 = sqrt(v5);\n else\n v6 = sqrt(v5);\n return (unsigned int)(v4 - (int)v6);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1, int a2) {\n double v2;\n double v3;\n int v4;\n double v5;\n double v6;\n v2 = (double)a2;\n if ((double)a2 < 0.0)\n v3 = sqrt(v2);\n else\n v3 = sqrt(v2);\n v4 = (int)v3;\n v5 = (double)(a1 - 1);\n if (v5 < 0.0)\n v6 = sqrt(v5);\n else\n v6 = sqrt(v5);\n return (unsigned int)(v4 - (int)v6);\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n double v2;\n double v3;\n int v4;\n double v5;\n double v6;\n v2 = (double)a2;\n if ((double)a2 < 0.0)\n v3 = sqrt(v2);\n else\n v3 = sqrt(v2);\n v4 = (int)v3;\n v5 = (double)(a1 - 1);\n if (v5 < 0.0)\n v6 = sqrt(v5);\n else\n v6 = sqrt(v5);\n return (unsigned int)(v4 - (int)v6);\n}" + }, + { + "index": 344, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n, int m) { return (int)sqrt(m) - (int)sqrt(n - 1); }", + "test": "int main() {\n\n assert(func0(5, 100) == 8);\n\n assert(func0(8, 65) == 6);\n\n assert(func0(2, 5) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npxor %xmm0,%xmm0\npxor %xmm2,%xmm2\nsub $0x18,%rsp\ncvtsi2sd %esi,%xmm0\nucomisd %xmm0,%xmm2\nmovapd %xmm0,%xmm1\nsqrtsd %xmm1,%xmm1\nja 126a \nsub $0x1,%edi\ncvttsd2si %xmm1,%eax\npxor %xmm0,%xmm0\ncvtsi2sd %edi,%xmm0\nucomisd %xmm0,%xmm2\nmovapd %xmm0,%xmm1\nsqrtsd %xmm1,%xmm1\nja 1287 \ncvttsd2si %xmm1,%edx\nadd $0x18,%rsp\nsub %edx,%eax\nretq\nmov %edi,0x8(%rsp)\nmovsd %xmm1,(%rsp)\ncallq 1070 \nmov 0x8(%rsp),%edi\nmovsd (%rsp),%xmm1\npxor %xmm2,%xmm2\njmp 1242 \nmov %eax,(%rsp)\nmovsd %xmm1,0x8(%rsp)\ncallq 1070 \nmovsd 0x8(%rsp),%xmm1\nmov (%rsp),%eax\njmp 125f \n", + "ida_asm": "func0:\nendbr64\npxor xmm0, xmm0\npxor xmm1, xmm1\nsub rsp, 18h\ncvtsi2sd xmm0, esi; x\nucomisd xmm1, xmm0\nja short loc_1266\nsqrtsd xmm0, xmm0\nloc_123E:\nsub edi, 1\ncvttsd2si eax, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, edi; x\npxor xmm1, xmm1\nucomisd xmm1, xmm0\nja short loc_1275\nsqrtsd xmm0, xmm0\nloc_125B:\ncvttsd2si edx, xmm0\nadd rsp, 18h\nsub eax, edx\nretn\nloc_1266:\nmov [rsp+18h+var_C], edi\ncall _sqrt\nmov edi, [rsp+18h+var_C]\njmp short loc_123E\nloc_1275:\nmov [rsp+18h+var_C], eax\ncall _sqrt\nmov eax, [rsp+18h+var_C]\njmp short loc_125B", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n double v2; // xmm0_8\n double v3; // xmm0_8\n int v4; // eax\n double v5; // xmm0_8\n double v6; // xmm0_8\n int v8; // [rsp+Ch] [rbp-Ch]\n\n v2 = (double)a2;\n if ( (double)a2 < 0.0 )\n v3 = sqrt(v2);\n else\n v3 = sqrt(v2);\n v4 = (int)v3;\n v5 = (double)(a1 - 1);\n if ( v5 < 0.0 )\n {\n v8 = v4;\n v6 = sqrt(v5);\n v4 = v8;\n }\n else\n {\n v6 = sqrt(v5);\n }\n return (unsigned int)(v4 - (int)v6);\n}", + "ida_strip_asm": "sub_1220:\nendbr64\npxor xmm0, xmm0\npxor xmm1, xmm1\nsub rsp, 18h\ncvtsi2sd xmm0, esi; x\nucomisd xmm1, xmm0\nja short loc_1266\nsqrtsd xmm0, xmm0\nloc_123E:\nsub edi, 1\ncvttsd2si eax, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, edi; x\npxor xmm1, xmm1\nucomisd xmm1, xmm0\nja short loc_1275\nsqrtsd xmm0, xmm0\nloc_125B:\ncvttsd2si edx, xmm0\nadd rsp, 18h\nsub eax, edx\nretn\nloc_1266:\nmov [rsp+18h+var_C], edi\ncall _sqrt\nmov edi, [rsp+18h+var_C]\njmp short loc_123E\nloc_1275:\nmov [rsp+18h+var_C], eax\ncall _sqrt\nmov eax, [rsp+18h+var_C]\njmp short loc_125B", + "ida_strip_pseudo": "__int64 __fastcall sub_1220(int a1, int a2)\n{\n double v2; // xmm0_8\n double v3; // xmm0_8\n int v4; // eax\n double v5; // xmm0_8\n double v6; // xmm0_8\n int v8; // [rsp+Ch] [rbp-Ch]\n\n v2 = (double)a2;\n if ( (double)a2 < 0.0 )\n v3 = sqrt(v2);\n else\n v3 = sqrt(v2);\n v4 = (int)v3;\n v5 = (double)(a1 - 1);\n if ( v5 < 0.0 )\n {\n v8 = v4;\n v6 = sqrt(v5);\n v4 = v8;\n }\n else\n {\n v6 = sqrt(v5);\n }\n return (unsigned int)(v4 - (int)v6);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1220(int a1, int a2) {\n double v2;\n double v3;\n int v4;\n double v5;\n double v6;\n int v8;\n v2 = (double)a2;\n if ((double)a2 < 0.0)\n v3 = sqrt(v2);\n else\n v3 = sqrt(v2);\n v4 = (int)v3;\n v5 = (double)(a1 - 1);\n if (v5 < 0.0) {\n v8 = v4;\n v6 = sqrt(v5);\n v4 = v8;\n } else {\n v6 = sqrt(v5);\n }\n return (unsigned int)(v4 - (int)v6);\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n double v2;\n double v3;\n int v4;\n double v5;\n double v6;\n int v8;\n v2 = (double)a2;\n if ((double)a2 < 0.0)\n v3 = sqrt(v2);\n else\n v3 = sqrt(v2);\n v4 = (int)v3;\n v5 = (double)(a1 - 1);\n if (v5 < 0.0) {\n v8 = v4;\n v6 = sqrt(v5);\n v4 = v8;\n } else {\n v6 = sqrt(v5);\n }\n return (unsigned int)(v4 - (int)v6);\n}" + }, + { + "index": 344, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n, int m) { return (int)sqrt(m) - (int)sqrt(n - 1); }", + "test": "int main() {\n\n assert(func0(5, 100) == 8);\n\n assert(func0(8, 65) == 6);\n\n assert(func0(2, 5) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npxor %xmm0,%xmm0\npxor %xmm2,%xmm2\nsub $0x18,%rsp\ncvtsi2sd %esi,%xmm0\nucomisd %xmm0,%xmm2\nmovapd %xmm0,%xmm1\nsqrtsd %xmm1,%xmm1\nja 126a \nsub $0x1,%edi\ncvttsd2si %xmm1,%eax\npxor %xmm0,%xmm0\ncvtsi2sd %edi,%xmm0\nucomisd %xmm0,%xmm2\nmovapd %xmm0,%xmm1\nsqrtsd %xmm1,%xmm1\nja 1287 \ncvttsd2si %xmm1,%edx\nadd $0x18,%rsp\nsub %edx,%eax\nretq\nmov %edi,0x8(%rsp)\nmovsd %xmm1,(%rsp)\ncallq 1070 \nmov 0x8(%rsp),%edi\nmovsd (%rsp),%xmm1\npxor %xmm2,%xmm2\njmp 1242 \nmov %eax,(%rsp)\nmovsd %xmm1,0x8(%rsp)\ncallq 1070 \nmovsd 0x8(%rsp),%xmm1\nmov (%rsp),%eax\njmp 125f \n", + "ida_asm": "func0:\nendbr64\npxor xmm0, xmm0\npxor xmm1, xmm1\nsub rsp, 18h\ncvtsi2sd xmm0, esi; x\nucomisd xmm1, xmm0\nja short loc_1266\nsqrtsd xmm0, xmm0\nloc_123E:\nsub edi, 1\ncvttsd2si eax, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, edi; x\npxor xmm1, xmm1\nucomisd xmm1, xmm0\nja short loc_1275\nsqrtsd xmm0, xmm0\nloc_125B:\ncvttsd2si edx, xmm0\nadd rsp, 18h\nsub eax, edx\nretn\nloc_1266:\nmov [rsp+18h+var_C], edi\ncall _sqrt\nmov edi, [rsp+18h+var_C]\njmp short loc_123E\nloc_1275:\nmov [rsp+18h+var_C], eax\ncall _sqrt\nmov eax, [rsp+18h+var_C]\njmp short loc_125B", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n double v2; // xmm0_8\n double v3; // xmm0_8\n int v4; // eax\n double v5; // xmm0_8\n double v6; // xmm0_8\n int v8; // [rsp+Ch] [rbp-Ch]\n\n v2 = (double)a2;\n if ( (double)a2 < 0.0 )\n v3 = sqrt(v2);\n else\n v3 = sqrt(v2);\n v4 = (int)v3;\n v5 = (double)(a1 - 1);\n if ( v5 < 0.0 )\n {\n v8 = v4;\n v6 = sqrt(v5);\n v4 = v8;\n }\n else\n {\n v6 = sqrt(v5);\n }\n return (unsigned int)(v4 - (int)v6);\n}", + "ida_strip_asm": "sub_1220:\nendbr64\npxor xmm0, xmm0\npxor xmm1, xmm1\nsub rsp, 18h\ncvtsi2sd xmm0, esi; x\nucomisd xmm1, xmm0\nja short loc_1266\nsqrtsd xmm0, xmm0\nloc_123E:\nsub edi, 1\ncvttsd2si eax, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, edi; x\npxor xmm1, xmm1\nucomisd xmm1, xmm0\nja short loc_1275\nsqrtsd xmm0, xmm0\nloc_125B:\ncvttsd2si edx, xmm0\nadd rsp, 18h\nsub eax, edx\nretn\nloc_1266:\nmov [rsp+18h+var_C], edi\ncall _sqrt\nmov edi, [rsp+18h+var_C]\njmp short loc_123E\nloc_1275:\nmov [rsp+18h+var_C], eax\ncall _sqrt\nmov eax, [rsp+18h+var_C]\njmp short loc_125B", + "ida_strip_pseudo": "__int64 __fastcall sub_1220(int a1, int a2)\n{\n double v2; // xmm0_8\n double v3; // xmm0_8\n int v4; // eax\n double v5; // xmm0_8\n double v6; // xmm0_8\n int v8; // [rsp+Ch] [rbp-Ch]\n\n v2 = (double)a2;\n if ( (double)a2 < 0.0 )\n v3 = sqrt(v2);\n else\n v3 = sqrt(v2);\n v4 = (int)v3;\n v5 = (double)(a1 - 1);\n if ( v5 < 0.0 )\n {\n v8 = v4;\n v6 = sqrt(v5);\n v4 = v8;\n }\n else\n {\n v6 = sqrt(v5);\n }\n return (unsigned int)(v4 - (int)v6);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1220(int a1, int a2) {\n double v2;\n double v3;\n int v4;\n double v5;\n double v6;\n int v8;\n v2 = (double)a2;\n if ((double)a2 < 0.0)\n v3 = sqrt(v2);\n else\n v3 = sqrt(v2);\n v4 = (int)v3;\n v5 = (double)(a1 - 1);\n if (v5 < 0.0) {\n v8 = v4;\n v6 = sqrt(v5);\n v4 = v8;\n } else {\n v6 = sqrt(v5);\n }\n return (unsigned int)(v4 - (int)v6);\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n double v2;\n double v3;\n int v4;\n double v5;\n double v6;\n int v8;\n v2 = (double)a2;\n if ((double)a2 < 0.0)\n v3 = sqrt(v2);\n else\n v3 = sqrt(v2);\n v4 = (int)v3;\n v5 = (double)(a1 - 1);\n if (v5 < 0.0) {\n v8 = v4;\n v6 = sqrt(v5);\n v4 = v8;\n } else {\n v6 = sqrt(v5);\n }\n return (unsigned int)(v4 - (int)v6);\n}" + }, + { + "index": 345, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int *func0(int nums[], int size, int *result_size) {\n *result_size = size - 1;\n int *result = malloc(*result_size * sizeof(int));\n for (int i = 0; i < *result_size; i++) {\n result[i] = nums[i + 1] - nums[i];\n }\n return result;\n}", + "test": "int main() {\n\n int result_size;\n\n int *result;\n\n\n\n int test1[] = {1, 1, 3, 4, 4, 5, 6, 7};\n\n result = func0(test1, 8, &result_size);\n\n int expected1[] = {0, 2, 1, 0, 1, 1, 1};\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected1[i]);\n\n }\n\n free(result);\n\n\n\n int test2[] = {4, 5, 8, 9, 6, 10};\n\n result = func0(test2, 6, &result_size);\n\n int expected2[] = {1, 3, 1, -3, 4};\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected2[i]);\n\n }\n\n free(result);\n\n\n\n int test3[] = {0, 1, 2, 3, 4, 4, 4, 4, 5, 7};\n\n result = func0(test3, 10, &result_size);\n\n int expected3[] = {1, 1, 1, 1, 0, 0, 0, 1, 2};\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected3[i]);\n\n }\n\n free(result);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmov -0x1c(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x28(%rbp),%rax\nmov %edx,(%rax)\nmov -0x28(%rbp),%rax\nmov (%rax),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 123b \nmov -0xc(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%ecx\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rsi\nmov -0x8(%rbp),%rax\nadd %rsi,%rax\nsub %edx,%ecx\nmov %ecx,%edx\nmov %edx,(%rax)\naddl $0x1,-0xc(%rbp)\nmov -0x28(%rbp),%rax\nmov (%rax),%eax\ncmp %eax,-0xc(%rbp)\njl 11ed \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov eax, [rbp+var_1C]\nlea edx, [rax-1]\nmov rax, [rbp+var_28]\nmov [rax], edx\nmov rax, [rbp+var_28]\nmov eax, [rax]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp short loc_123A\nloc_11ED:\nmov eax, [rbp+var_C]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov ecx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rsi, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rsi\nsub ecx, eax\nmov [rdx], ecx\nadd [rbp+var_C], 1\nloc_123A:\nmov rax, [rbp+var_28]\nmov eax, [rax]\ncmp [rbp+var_C], eax\njl short loc_11ED\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, int *a3)\n{\n int i; // [rsp+24h] [rbp-Ch]\n _DWORD *v6; // [rsp+28h] [rbp-8h]\n\n *a3 = a2 - 1;\n v6 = malloc(4LL * *a3);\n for ( i = 0; i < *a3; ++i )\n v6[i] = *(_DWORD *)(4 * (i + 1LL) + a1) - *(_DWORD *)(4LL * i + a1);\n return v6;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov eax, [rbp+var_1C]\nlea edx, [rax-1]\nmov rax, [rbp+var_28]\nmov [rax], edx\nmov rax, [rbp+var_28]\nmov eax, [rax]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp short loc_123A\nloc_11ED:\nmov eax, [rbp+var_C]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov ecx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rsi, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rsi\nsub ecx, eax\nmov [rdx], ecx\nadd [rbp+var_C], 1\nloc_123A:\nmov rax, [rbp+var_28]\nmov eax, [rax]\ncmp [rbp+var_C], eax\njl short loc_11ED\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(__int64 a1, int a2, int *a3)\n{\n int i; // [rsp+24h] [rbp-Ch]\n _DWORD *v6; // [rsp+28h] [rbp-8h]\n\n *a3 = a2 - 1;\n v6 = malloc(4LL * *a3);\n for ( i = 0; i < *a3; ++i )\n v6[i] = *(_DWORD *)(4 * (i + 1LL) + a1) - *(_DWORD *)(4LL * i + a1);\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(long long a1, int a2, int *a3) {\n int i;\n uint32_t *v6;\n *a3 = a2 - 1;\n v6 = malloc(4LL * *a3);\n for (i = 0; i < *a3; ++i)\n v6[i] = *(uint32_t *)(4 * (i + 1LL) + a1) - *(uint32_t *)(4LL * i + a1);\n return v6;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, int *a3) {\n int i;\n uint32_t *v6;\n *a3 = a2 - 1;\n v6 = malloc(4LL * *a3);\n for (i = 0; i < *a3; ++i)\n v6[i] = *(uint32_t *)(4 * (i + 1LL) + a1) - *(uint32_t *)(4LL * i + a1);\n return v6;\n}" + }, + { + "index": 345, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int *func0(int nums[], int size, int *result_size) {\n *result_size = size - 1;\n int *result = malloc(*result_size * sizeof(int));\n for (int i = 0; i < *result_size; i++) {\n result[i] = nums[i + 1] - nums[i];\n }\n return result;\n}", + "test": "int main() {\n\n int result_size;\n\n int *result;\n\n\n\n int test1[] = {1, 1, 3, 4, 4, 5, 6, 7};\n\n result = func0(test1, 8, &result_size);\n\n int expected1[] = {0, 2, 1, 0, 1, 1, 1};\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected1[i]);\n\n }\n\n free(result);\n\n\n\n int test2[] = {4, 5, 8, 9, 6, 10};\n\n result = func0(test2, 6, &result_size);\n\n int expected2[] = {1, 3, 1, -3, 4};\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected2[i]);\n\n }\n\n free(result);\n\n\n\n int test3[] = {0, 1, 2, 3, 4, 4, 4, 4, 5, 7};\n\n result = func0(test3, 10, &result_size);\n\n int expected3[] = {1, 1, 1, 1, 0, 0, 0, 1, 2};\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected3[i]);\n\n }\n\n free(result);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbx\nmov %rdx,%rbp\nsub $0x1,%esi\nmov %esi,(%rdx)\nmovslq %esi,%rsi\nlea 0x0(,%rsi,4),%rdi\ncallq 10b0 \nmov 0x0(%rbp),%edx\ntest %edx,%edx\njle 11f3 \nlea -0x1(%rdx),%esi\nmov $0x0,%edx\nmov 0x4(%rbx,%rdx,4),%ecx\nsub (%rbx,%rdx,4),%ecx\nmov %ecx,(%rax,%rdx,4)\nmov %rdx,%rcx\nadd $0x1,%rdx\ncmp %rsi,%rcx\njne 11dd \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov rbp, rdx\nsub esi, 1\nmov [rdx], esi\nmovsxd rsi, esi\nlea rdi, ds:0[rsi*4]; size\ncall _malloc\nmov esi, [rbp+0]\ntest esi, esi\njle short loc_11F4\nmovsxd rsi, esi\nshl rsi, 2\nmov edx, 0\nloc_11E1:\nmov ecx, [rbx+rdx+4]\nsub ecx, [rbx+rdx]\nmov [rax+rdx], ecx\nadd rdx, 4\ncmp rdx, rsi\njnz short loc_11E1\nloc_11F4:\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2, int *a3)\n{\n int v4; // esi\n char *result; // rax\n __int64 v6; // rsi\n __int64 v7; // rdx\n\n v4 = a2 - 1;\n *a3 = v4;\n result = (char *)malloc(4LL * v4);\n if ( *a3 > 0 )\n {\n v6 = 4LL * *a3;\n v7 = 0LL;\n do\n {\n *(_DWORD *)&result[v7] = *(_DWORD *)(a1 + v7 + 4) - *(_DWORD *)(a1 + v7);\n v7 += 4LL;\n }\n while ( v7 != v6 );\n }\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov rbp, rdx\nsub esi, 1\nmov [rdx], esi\nmovsxd rsi, esi\nlea rdi, ds:0[rsi*4]; size\ncall _malloc\nmov esi, [rbp+0]\ntest esi, esi\njle short loc_11F4\nmovsxd rsi, esi\nshl rsi, 2\nmov edx, 0\nloc_11E1:\nmov ecx, [rbx+rdx+4]\nsub ecx, [rbx+rdx]\nmov [rax+rdx], ecx\nadd rdx, 4\ncmp rdx, rsi\njnz short loc_11E1\nloc_11F4:\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11A9(__int64 a1, int a2, int *a3)\n{\n int v4; // esi\n char *result; // rax\n __int64 v6; // rsi\n __int64 v7; // rdx\n\n v4 = a2 - 1;\n *a3 = v4;\n result = (char *)malloc(4LL * v4);\n if ( *a3 > 0 )\n {\n v6 = 4LL * *a3;\n v7 = 0LL;\n do\n {\n *(_DWORD *)&result[v7] = *(_DWORD *)(a1 + v7 + 4) - *(_DWORD *)(a1 + v7);\n v7 += 4LL;\n }\n while ( v7 != v6 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11A9(long long a1, int a2, int *a3) {\n int v4;\n char *result;\n long long v6;\n long long v7;\n v4 = a2 - 1;\n *a3 = v4;\n result = (char *)malloc(4LL * v4);\n if (*a3 > 0) {\n v6 = 4LL * *a3;\n v7 = 0LL;\n do {\n *(uint32_t *)&result[v7] =\n *(uint32_t *)(a1 + v7 + 4) - *(uint32_t *)(a1 + v7);\n v7 += 4LL;\n } while (v7 != v6);\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2, int *a3) {\n int v4;\n char *result;\n long long v6;\n long long v7;\n v4 = a2 - 1;\n *a3 = v4;\n result = (char *)malloc(4LL * v4);\n if (*a3 > 0) {\n v6 = 4LL * *a3;\n v7 = 0LL;\n do {\n *(uint32_t *)&result[v7] =\n *(uint32_t *)(a1 + v7 + 4) - *(uint32_t *)(a1 + v7);\n v7 += 4LL;\n } while (v7 != v6);\n }\n return result;\n}" + }, + { + "index": 345, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int *func0(int nums[], int size, int *result_size) {\n *result_size = size - 1;\n int *result = malloc(*result_size * sizeof(int));\n for (int i = 0; i < *result_size; i++) {\n result[i] = nums[i + 1] - nums[i];\n }\n return result;\n}", + "test": "int main() {\n\n int result_size;\n\n int *result;\n\n\n\n int test1[] = {1, 1, 3, 4, 4, 5, 6, 7};\n\n result = func0(test1, 8, &result_size);\n\n int expected1[] = {0, 2, 1, 0, 1, 1, 1};\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected1[i]);\n\n }\n\n free(result);\n\n\n\n int test2[] = {4, 5, 8, 9, 6, 10};\n\n result = func0(test2, 6, &result_size);\n\n int expected2[] = {1, 3, 1, -3, 4};\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected2[i]);\n\n }\n\n free(result);\n\n\n\n int test3[] = {0, 1, 2, 3, 4, 4, 4, 4, 5, 7};\n\n result = func0(test3, 10, &result_size);\n\n int expected3[] = {1, 1, 1, 1, 0, 0, 0, 1, 2};\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected3[i]);\n\n }\n\n free(result);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nsub $0x1,%esi\nmov %rdx,%rbp\npush %rbx\nmov %rdi,%rbx\nsub $0x8,%rsp\nmov %esi,(%rdx)\nmovslq %esi,%rsi\nlea 0x0(,%rsi,4),%rdi\ncallq 10b0 \nmov 0x0(%rbp),%edx\ntest %edx,%edx\njle 14ae \nlea -0x1(%rdx),%esi\nxor %edx,%edx\nnopl 0x0(%rax)\nmov 0x4(%rbx,%rdx,4),%ecx\nsub (%rbx,%rdx,4),%ecx\nmov %ecx,(%rax,%rdx,4)\nmov %rdx,%rcx\nadd $0x1,%rdx\ncmp %rsi,%rcx\njne 1498 \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nsub esi, 1\nmov rbp, rdx\npush rbx\nmov rbx, rdi\nsub rsp, 8\nmov [rdx], esi\nmovsxd rsi, esi\nlea rdi, ds:0[rsi*4]; size\ncall _malloc\nmovsxd r8, dword ptr [rbp+0]\ntest r8d, r8d\njle short loc_1446\nmov ecx, [rbx]\nshl r8, 2\nxor edx, edx\nnop word ptr [rax+rax+00000000h]\nloc_1430:\nmov edi, ecx\nmov ecx, [rbx+rdx+4]\nmov esi, ecx\nsub esi, edi\nmov [rax+rdx], esi\nadd rdx, 4\ncmp r8, rdx\njnz short loc_1430\nloc_1446:\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_pseudo": "char *__fastcall func0(int *a1, int a2, int *a3)\n{\n int v3; // esi\n char *result; // rax\n __int64 v7; // r8\n int v8; // ecx\n __int64 v9; // r8\n unsigned __int64 v10; // rdx\n int v11; // edi\n\n v3 = a2 - 1;\n *a3 = v3;\n result = (char *)malloc(4LL * v3);\n v7 = *a3;\n if ( (int)v7 > 0 )\n {\n v8 = *a1;\n v9 = 4 * v7;\n v10 = 0LL;\n do\n {\n v11 = v8;\n v8 = a1[v10 / 4 + 1];\n *(_DWORD *)&result[v10] = v8 - v11;\n v10 += 4LL;\n }\n while ( v9 != v10 );\n }\n return result;\n}", + "ida_strip_asm": "sub_13F0:\nendbr64\npush rbp\nsub esi, 1\nmov rbp, rdx\npush rbx\nmov rbx, rdi\nsub rsp, 8\nmov [rdx], esi\nmovsxd rsi, esi\nlea rdi, ds:0[rsi*4]; size\ncall _malloc\nmovsxd r8, dword ptr [rbp+0]\ntest r8d, r8d\njle short loc_1446\nmov ecx, [rbx]\nshl r8, 2\nxor edx, edx\nnop word ptr [rax+rax+00000000h]\nloc_1430:\nmov edi, ecx\nmov ecx, [rbx+rdx+4]\nmov esi, ecx\nsub esi, edi\nmov [rax+rdx], esi\nadd rdx, 4\ncmp r8, rdx\njnz short loc_1430\nloc_1446:\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "char *__fastcall sub_13F0(int *a1, int a2, int *a3)\n{\n int v3; // esi\n char *result; // rax\n __int64 v7; // r8\n int v8; // ecx\n __int64 v9; // r8\n unsigned __int64 v10; // rdx\n int v11; // edi\n\n v3 = a2 - 1;\n *a3 = v3;\n result = (char *)malloc(4LL * v3);\n v7 = *a3;\n if ( (int)v7 > 0 )\n {\n v8 = *a1;\n v9 = 4 * v7;\n v10 = 0LL;\n do\n {\n v11 = v8;\n v8 = a1[v10 / 4 + 1];\n *(_DWORD *)&result[v10] = v8 - v11;\n v10 += 4LL;\n }\n while ( v9 != v10 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_13F0(int *a1, int a2, int *a3) {\n int v3;\n char *result;\n long long v7;\n int v8;\n long long v9;\n unsigned long long v10;\n int v11;\n v3 = a2 - 1;\n *a3 = v3;\n result = (char *)malloc(4LL * v3);\n v7 = *a3;\n if ((int)v7 > 0) {\n v8 = *a1;\n v9 = 4 * v7;\n v10 = 0LL;\n do {\n v11 = v8;\n v8 = a1[v10 / 4 + 1];\n *(uint32_t *)&result[v10] = v8 - v11;\n v10 += 4LL;\n } while (v9 != v10);\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(int *a1, int a2, int *a3) {\n int v3;\n char *result;\n long long v7;\n int v8;\n long long v9;\n unsigned long long v10;\n int v11;\n v3 = a2 - 1;\n *a3 = v3;\n result = (char *)malloc(4LL * v3);\n v7 = *a3;\n if ((int)v7 > 0) {\n v8 = *a1;\n v9 = 4 * v7;\n v10 = 0LL;\n do {\n v11 = v8;\n v8 = a1[v10 / 4 + 1];\n *(uint32_t *)&result[v10] = v8 - v11;\n v10 += 4LL;\n } while (v9 != v10);\n }\n return result;\n}" + }, + { + "index": 345, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int *func0(int nums[], int size, int *result_size) {\n *result_size = size - 1;\n int *result = malloc(*result_size * sizeof(int));\n for (int i = 0; i < *result_size; i++) {\n result[i] = nums[i + 1] - nums[i];\n }\n return result;\n}", + "test": "int main() {\n\n int result_size;\n\n int *result;\n\n\n\n int test1[] = {1, 1, 3, 4, 4, 5, 6, 7};\n\n result = func0(test1, 8, &result_size);\n\n int expected1[] = {0, 2, 1, 0, 1, 1, 1};\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected1[i]);\n\n }\n\n free(result);\n\n\n\n int test2[] = {4, 5, 8, 9, 6, 10};\n\n result = func0(test2, 6, &result_size);\n\n int expected2[] = {1, 3, 1, -3, 4};\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected2[i]);\n\n }\n\n free(result);\n\n\n\n int test3[] = {0, 1, 2, 3, 4, 4, 4, 4, 5, 7};\n\n result = func0(test3, 10, &result_size);\n\n int expected3[] = {1, 1, 1, 1, 0, 0, 0, 1, 2};\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected3[i]);\n\n }\n\n free(result);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nsub $0x1,%esi\nmov %rdx,%rbp\npush %rbx\nmov %rdi,%rbx\nsub $0x8,%rsp\nmov %esi,(%rdx)\nmovslq %esi,%rsi\nlea 0x0(,%rsi,4),%rdi\ncallq 10b0 \nmov 0x0(%rbp),%esi\ntest %esi,%esi\njle 15ec \nlea -0x1(%rsi),%edi\ncmp $0x2,%edi\njbe 164a \nmov %esi,%ecx\nxor %edx,%edx\nshr $0x2,%ecx\nshl $0x4,%rcx\nnopw 0x0(%rax,%rax,1)\nmovdqu 0x4(%rbx,%rdx,1),%xmm0\nmovdqu (%rbx,%rdx,1),%xmm1\npsubd %xmm1,%xmm0\nmovups %xmm0,(%rax,%rdx,1)\nadd $0x10,%rdx\ncmp %rdx,%rcx\njne 1530 \nmov %esi,%ecx\nand $0xfffffffc,%ecx\ntest $0x3,%sil\nje 15ec \nmovslq %ecx,%r8\nlea 0x1(%rcx),%r9d\nlea 0x0(,%r8,4),%rdx\nlea (%rbx,%rdx,1),%r10\ncmp %edi,%r9d\njge 1651 \ncmp %ecx,%esi\njle 1651 \nmov 0x4(%rbx,%rdx,1),%r9d\nmov %r9d,%r11d\nsub (%r10),%r11d\nmov 0x8(%rbx,%rdx,1),%r10d\nmov %r11d,(%rax,%r8,4)\nmov %r10d,%r8d\nsub %r9d,%r8d\nlea 0x3(%rcx),%r9d\nmov %r8d,0x4(%rax,%rdx,1)\nlea 0x2(%rcx),%r8d\ncmp %r9d,%edi\njg 15f8 \nmovslq %r8d,%rdx\nadd $0x1,%rdx\nmov (%rbx,%rdx,4),%edi\nlea 0x0(,%rdx,4),%rcx\nsub -0x4(%rbx,%rdx,4),%edi\nmov %edi,-0x4(%rax,%rcx,1)\nlea 0x1(%r8),%edi\ncmp %edi,%esi\njle 15ec \nmov 0x4(%rbx,%rcx,1),%edi\nadd $0x2,%r8d\nsub (%rbx,%rdx,4),%edi\nmov %edi,(%rax,%rdx,4)\ncmp %r8d,%esi\njle 15ec \nmov 0x8(%rbx,%rcx,1),%edx\nsub 0x4(%rbx,%rcx,1),%edx\nmov %edx,0x4(%rax,%rcx,1)\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopl 0x0(%rax,%rax,1)\nmov 0xc(%rbx,%rdx,1),%r8d\nmov %r8d,%r9d\nsub %r10d,%r9d\nlea 0x5(%rcx),%r10d\nmov %r9d,0x8(%rax,%rdx,1)\nmov 0x10(%rbx,%rdx,1),%r9d\nmov %r9d,%r11d\nsub %r8d,%r11d\nlea 0x4(%rcx),%r8d\nmov %r11d,0xc(%rax,%rdx,1)\ncmp %r10d,%edi\njle 15ab \nmov 0x14(%rbx,%rdx,1),%edi\nmov 0x18(%rbx,%rdx,1),%r11d\nmov %edi,%r8d\nsub %edi,%r11d\nsub %r9d,%r8d\nmov %r11d,0x14(%rax,%rdx,1)\nmov %r8d,0x10(%rax,%rdx,1)\nlea 0x6(%rcx),%r8d\njmpq 15ab \nxor %ecx,%ecx\njmpq 155b \nmov %ecx,%r8d\njmpq 15ab \nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nsub esi, 1\nmov rbp, rdx\npush rbx\nmov rbx, rdi\nsub rsp, 8\nmov [rdx], esi\nmovsxd rsi, esi\nlea rdi, ds:0[rsi*4]; size\ncall _malloc\nmov edx, [rbp+0]\nmov rcx, rax\ntest edx, edx\njle loc_14D9\nlea eax, [rdx-1]\ncmp eax, 2\njbe loc_14E3\nmov esi, edx\nxor eax, eax\nshr esi, 2\nshl rsi, 4\nnop word ptr [rax+rax+00h]\nloc_1470:\nmovdqu xmm0, xmmword ptr [rbx+rax+4]\nmovdqu xmm2, xmmword ptr [rbx+rax]\npsubd xmm0, xmm2\nmovups xmmword ptr [rcx+rax], xmm0\nadd rax, 10h\ncmp rsi, rax\njnz short loc_1470\nmov eax, edx\nand eax, 0FFFFFFFCh\nmov esi, eax\ncmp edx, eax\njz short loc_14D9\nloc_1497:\nsub edx, esi\ncmp edx, 1\njz short loc_14C8\nlea edi, [rsi+1]\nlea rsi, ds:0[rdi*4]\nmovq xmm0, qword ptr [rbx+rdi*4]\nmovq xmm1, qword ptr [rbx+rsi-4]\npsubd xmm0, xmm1\nmovq qword ptr [rcx+rsi-4], xmm0\ntest dl, 1\njz short loc_14D9\nand edx, 0FFFFFFFEh\nadd eax, edx\nloc_14C8:\ncdqe\nadd rax, 1\nmov edx, [rbx+rax*4]\nsub edx, [rbx+rax*4-4]\nmov [rcx+rax*4-4], edx\nloc_14D9:\nadd rsp, 8\nmov rax, rcx\npop rbx\npop rbp\nretn\nloc_14E3:\nxor esi, esi\nxor eax, eax\njmp short loc_1497", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, unsigned int *a3)\n{\n unsigned int v3; // esi\n _DWORD *v5; // rax\n unsigned int v6; // edx\n _DWORD *v7; // rcx\n __int64 v8; // rax\n signed int v9; // eax\n unsigned int v10; // esi\n unsigned int v11; // edx\n\n v3 = a2 - 1;\n *a3 = v3;\n v5 = malloc(4LL * (int)v3);\n v6 = *a3;\n v7 = v5;\n if ( (int)*a3 > 0 )\n {\n if ( v6 - 1 <= 2 )\n {\n v10 = 0;\n v9 = 0;\n }\n else\n {\n v8 = 0LL;\n do\n {\n *(__m128i *)&v7[v8] = _mm_sub_epi32(\n _mm_loadu_si128((const __m128i *)(a1 + v8 * 4 + 4)),\n _mm_loadu_si128((const __m128i *)(a1 + v8 * 4)));\n v8 += 4LL;\n }\n while ( 4LL * (v6 >> 2) != v8 );\n v9 = v6 & 0xFFFFFFFC;\n v10 = v6 & 0xFFFFFFFC;\n if ( v6 == (v6 & 0xFFFFFFFC) )\n return v7;\n }\n v11 = v6 - v10;\n if ( v11 == 1 )\n {\nLABEL_9:\n v7[v9] = *(_DWORD *)(a1 + 4 * (v9 + 1LL)) - *(_DWORD *)(a1 + 4 * (v9 + 1LL) - 4);\n return v7;\n }\n *(_QWORD *)&v7[v10] = _mm_sub_epi32(\n _mm_loadl_epi64((const __m128i *)(a1 + 4LL * (v10 + 1))),\n _mm_loadl_epi64((const __m128i *)(a1 + 4LL * (v10 + 1) - 4))).m128i_u64[0];\n if ( (v11 & 1) != 0 )\n {\n v9 += v11 & 0xFFFFFFFE;\n goto LABEL_9;\n }\n }\n return v7;\n}", + "ida_strip_asm": "sub_1420:\nendbr64\npush rbp\nsub esi, 1\nmov rbp, rdx\npush rbx\nmov rbx, rdi\nsub rsp, 8\nmov [rdx], esi\nmovsxd rsi, esi\nlea rdi, ds:0[rsi*4]; size\ncall _malloc\nmov edx, [rbp+0]\nmov rcx, rax\ntest edx, edx\njle loc_14D9\nlea eax, [rdx-1]\ncmp eax, 2\njbe loc_14E3\nmov esi, edx\nxor eax, eax\nshr esi, 2\nshl rsi, 4\nnop word ptr [rax+rax+00h]\nloc_1470:\nmovdqu xmm0, xmmword ptr [rbx+rax+4]\nmovdqu xmm2, xmmword ptr [rbx+rax]\npsubd xmm0, xmm2\nmovups xmmword ptr [rcx+rax], xmm0\nadd rax, 10h\ncmp rsi, rax\njnz short loc_1470\nmov eax, edx\nand eax, 0FFFFFFFCh\nmov esi, eax\ncmp edx, eax\njz short loc_14D9\nloc_1497:\nsub edx, esi\ncmp edx, 1\njz short loc_14C8\nlea edi, [rsi+1]\nlea rsi, ds:0[rdi*4]\nmovq xmm0, qword ptr [rbx+rdi*4]\nmovq xmm1, qword ptr [rbx+rsi-4]\npsubd xmm0, xmm1\nmovq qword ptr [rcx+rsi-4], xmm0\ntest dl, 1\njz short loc_14D9\nand edx, 0FFFFFFFEh\nadd eax, edx\nloc_14C8:\ncdqe\nadd rax, 1\nmov edx, [rbx+rax*4]\nsub edx, [rbx+rax*4-4]\nmov [rcx+rax*4-4], edx\nloc_14D9:\nadd rsp, 8\nmov rax, rcx\npop rbx\npop rbp\nretn\nloc_14E3:\nxor esi, esi\nxor eax, eax\njmp short loc_1497", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1420(__int64 a1, int a2, unsigned int *a3)\n{\n unsigned int v3; // esi\n _DWORD *v5; // rax\n unsigned int v6; // edx\n _DWORD *v7; // rcx\n __int64 v8; // rax\n signed int v9; // eax\n unsigned int v10; // esi\n unsigned int v11; // edx\n\n v3 = a2 - 1;\n *a3 = v3;\n v5 = malloc(4LL * (int)v3);\n v6 = *a3;\n v7 = v5;\n if ( (int)*a3 > 0 )\n {\n if ( v6 - 1 <= 2 )\n {\n v10 = 0;\n v9 = 0;\n }\n else\n {\n v8 = 0LL;\n do\n {\n *(__m128i *)&v7[v8] = _mm_sub_epi32(\n _mm_loadu_si128((const __m128i *)(a1 + v8 * 4 + 4)),\n _mm_loadu_si128((const __m128i *)(a1 + v8 * 4)));\n v8 += 4LL;\n }\n while ( 4LL * (v6 >> 2) != v8 );\n v9 = v6 & 0xFFFFFFFC;\n v10 = v6 & 0xFFFFFFFC;\n if ( v6 == (v6 & 0xFFFFFFFC) )\n return v7;\n }\n v11 = v6 - v10;\n if ( v11 == 1 )\n {\nLABEL_9:\n v7[v9] = *(_DWORD *)(a1 + 4 * (v9 + 1LL)) - *(_DWORD *)(a1 + 4 * (v9 + 1LL) - 4);\n return v7;\n }\n *(_QWORD *)&v7[v10] = _mm_sub_epi32(\n _mm_loadl_epi64((const __m128i *)(a1 + 4LL * (v10 + 1))),\n _mm_loadl_epi64((const __m128i *)(a1 + 4LL * (v10 + 1) - 4))).m128i_u64[0];\n if ( (v11 & 1) != 0 )\n {\n v9 += v11 & 0xFFFFFFFE;\n goto LABEL_9;\n }\n }\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1420(long long a1, int a2, unsigned int *a3) {\n unsigned int v3;\n uint32_t *v5;\n unsigned int v6;\n uint32_t *v7;\n long long v8;\n signed int v9;\n unsigned int v10;\n unsigned int v11;\n v3 = a2 - 1;\n *a3 = v3;\n v5 = malloc(4LL * (int)v3);\n v6 = *a3;\n v7 = v5;\n if ((int)*a3 > 0) {\n if (v6 - 1 <= 2) {\n v10 = 0;\n v9 = 0;\n } else {\n v8 = 0LL;\n do {\n *(__m128i *)&v7[v8] =\n _mm_sub_epi32(_mm_loadu_si128((const __m128i *)(a1 + v8 * 4 + 4)),\n _mm_loadu_si128((const __m128i *)(a1 + v8 * 4)));\n v8 += 4LL;\n } while (4LL * (v6 >> 2) != v8);\n v9 = v6 & 4294967292;\n v10 = v6 & 4294967292;\n if (v6 == (v6 & 4294967292)) return v7;\n }\n v11 = v6 - v10;\n if (v11 == 1) {\n LABEL_9:\n v7[v9] = *(uint32_t *)(a1 + 4 * (v9 + 1LL)) -\n *(uint32_t *)(a1 + 4 * (v9 + 1LL) - 4);\n return v7;\n }\n *(uint64_t *)&v7[v10] =\n _mm_sub_epi32(\n _mm_loadl_epi64((const __m128i *)(a1 + 4LL * (v10 + 1))),\n _mm_loadl_epi64((const __m128i *)(a1 + 4LL * (v10 + 1) - 4)))\n .m128i_u64[0];\n if ((v11 & 1) != 0) {\n v9 += v11 & 4294967294;\n goto LABEL_9;\n }\n }\n return v7;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, unsigned int *a3) {\n unsigned int v3;\n uint32_t *v5;\n unsigned int v6;\n uint32_t *v7;\n long long v8;\n signed int v9;\n unsigned int v10;\n unsigned int v11;\n v3 = a2 - 1;\n *a3 = v3;\n v5 = malloc(4LL * (int)v3);\n v6 = *a3;\n v7 = v5;\n if ((int)*a3 > 0) {\n if (v6 - 1 <= 2) {\n v10 = 0;\n v9 = 0;\n } else {\n v8 = 0LL;\n do {\n *(__m128i *)&v7[v8] =\n _mm_sub_epi32(_mm_loadu_si128((const __m128i *)(a1 + v8 * 4 + 4)),\n _mm_loadu_si128((const __m128i *)(a1 + v8 * 4)));\n v8 += 4LL;\n } while (4LL * (v6 >> 2) != v8);\n v9 = v6 & 4294967292;\n v10 = v6 & 4294967292;\n if (v6 == (v6 & 4294967292)) return v7;\n }\n v11 = v6 - v10;\n if (v11 == 1) {\n LABEL_9:\n v7[v9] = *(uint32_t *)(a1 + 4 * (v9 + 1LL)) -\n *(uint32_t *)(a1 + 4 * (v9 + 1LL) - 4);\n return v7;\n }\n *(uint64_t *)&v7[v10] =\n _mm_sub_epi32(\n _mm_loadl_epi64((const __m128i *)(a1 + 4LL * (v10 + 1))),\n _mm_loadl_epi64((const __m128i *)(a1 + 4LL * (v10 + 1) - 4)))\n .m128i_u64[0];\n if ((v11 & 1) != 0) {\n v9 += v11 & 4294967294;\n goto LABEL_9;\n }\n }\n return v7;\n}" + }, + { + "index": 346, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n, int k) {\n if (n == 0 && k == 0) {\n return 1;\n }\n if (k == 0) {\n return 0;\n }\n return func0(n, k - 1) + func0(n - 1, n - k);\n}", + "test": "int main() {\n\n assert(func0(4, 3) == 5);\n\n assert(func0(4, 2) == 4);\n\n assert(func0(3, 1) == 1);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x18,%rsp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\ncmpl $0x0,-0x14(%rbp)\njne 116f \ncmpl $0x0,-0x18(%rbp)\njne 116f \nmov $0x1,%eax\njmp 11a7 \ncmpl $0x0,-0x18(%rbp)\njne 117c \nmov $0x0,%eax\njmp 11a7 \nmov -0x18(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x14(%rbp),%eax\nmov %edx,%esi\nmov %eax,%edi\ncallq 1149 \nmov %eax,%ebx\nmov -0x14(%rbp),%eax\nsub -0x18(%rbp),%eax\nmov -0x14(%rbp),%edx\nsub $0x1,%edx\nmov %eax,%esi\nmov %edx,%edi\ncallq 1149 \nadd %ebx,%eax\nadd $0x18,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 18h\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\ncmp [rbp+var_14], 0\njnz short loc_116F\ncmp [rbp+var_18], 0\njnz short loc_116F\nmov eax, 1\njmp short loc_11A7\nloc_116F:\ncmp [rbp+var_18], 0\njnz short loc_117C\nmov eax, 0\njmp short loc_11A7\nloc_117C:\nmov eax, [rbp+var_18]\nlea edx, [rax-1]\nmov eax, [rbp+var_14]\nmov esi, edx\nmov edi, eax\ncall func0\nmov ebx, eax\nmov eax, [rbp+var_14]\nsub eax, [rbp+var_18]\nmov edx, [rbp+var_14]\nsub edx, 1\nmov esi, eax\nmov edi, edx\ncall func0\nadd eax, ebx\nloc_11A7:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1, int a2)\n{\n int v3; // ebx\n\n if ( !a1 && !a2 )\n return 1LL;\n if ( !a2 )\n return 0LL;\n v3 = func0(a1, (unsigned int)(a2 - 1));\n return v3 + (unsigned int)func0(a1 - 1, a1 - a2);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 18h\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\ncmp [rbp+var_14], 0\njnz short loc_116F\ncmp [rbp+var_18], 0\njnz short loc_116F\nmov eax, 1\njmp short loc_11A7\nloc_116F:\ncmp [rbp+var_18], 0\njnz short loc_117C\nmov eax, 0\njmp short loc_11A7\nloc_117C:\nmov eax, [rbp+var_18]\nlea edx, [rax-1]\nmov eax, [rbp+var_14]\nmov esi, edx\nmov edi, eax\ncall sub_1149\nmov ebx, eax\nmov eax, [rbp+var_14]\nsub eax, [rbp+var_18]\nmov edx, [rbp+var_14]\nsub edx, 1\nmov esi, eax\nmov edi, edx\ncall sub_1149\nadd eax, ebx\nloc_11A7:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(unsigned int a1, int a2)\n{\n int v3; // ebx\n\n if ( !a1 && !a2 )\n return 1LL;\n if ( !a2 )\n return 0LL;\n v3 = sub_1149(a1, (unsigned int)(a2 - 1));\n return v3 + (unsigned int)sub_1149(a1 - 1, a1 - a2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(unsigned int a1, int a2) {\n int v3;\n if (!a1 && !a2) return 1LL;\n if (!a2) return 0LL;\n v3 = sub_1149(a1, (unsigned int)(a2 - 1));\n return v3 + (unsigned int)sub_1149(a1 - 1, a1 - a2);\n}", + "ida_pseudo_norm": "long long func0(unsigned int a1, int a2) {\n int v3;\n if (!a1 && !a2) return 1LL;\n if (!a2) return 0LL;\n v3 = func0(a1, (unsigned int)(a2 - 1));\n return v3 + (unsigned int)func0(a1 - 1, a1 - a2);\n}" + }, + { + "index": 346, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n, int k) {\n if (n == 0 && k == 0) {\n return 1;\n }\n if (k == 0) {\n return 0;\n }\n return func0(n, k - 1) + func0(n - 1, n - k);\n}", + "test": "int main() {\n\n assert(func0(4, 3) == 5);\n\n assert(func0(4, 2) == 4);\n\n assert(func0(3, 1) == 1);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x1,%eax\nmov %edi,%edx\nor %esi,%edx\nje 1187 \npush %r12\npush %rbp\npush %rbx\nmov %edi,%ebp\nmov %esi,%ebx\nmov %esi,%eax\ntest %esi,%esi\njne 116b \npop %rbx\npop %rbp\npop %r12\nretq\nlea -0x1(%rsi),%esi\ncallq 1149 \nmov %eax,%r12d\nmov %ebp,%esi\nsub %ebx,%esi\nlea -0x1(%rbp),%edi\ncallq 1149 \nadd %r12d,%eax\njmp 1166 \nretq\n", + "ida_asm": "func0:\nendbr64\nmov eax, 1\nmov edx, edi\nor edx, esi\njz short locret_1189\npush r12\npush rbp\npush rbx\nmov r12d, edi\nmov ebx, esi\nmov eax, esi\ntest esi, esi\njnz short loc_116C\nloc_1167:\npop rbx\npop rbp\npop r12\nretn\nloc_116C:\nlea esi, [rsi-1]\ncall func0\nmov ebp, eax\nmov esi, r12d\nsub esi, ebx\nlea edi, [r12-1]\ncall func0\nadd eax, ebp\njmp short loc_1167\nlocret_1189:\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, unsigned int a2)\n{\n __int64 result; // rax\n int v3; // ebp\n\n result = 1LL;\n if ( a2 | (unsigned int)a1 )\n {\n result = a2;\n if ( a2 )\n {\n v3 = func0(a1, a2 - 1);\n return v3 + (unsigned int)func0((unsigned int)(a1 - 1), (unsigned int)a1 - a2);\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmov eax, 1\nmov edx, edi\nor edx, esi\njz short locret_1189\npush r12\npush rbp\npush rbx\nmov r12d, edi\nmov ebx, esi\nmov eax, esi\ntest esi, esi\njnz short loc_116C\nloc_1167:\npop rbx\npop rbp\npop r12\nretn\nloc_116C:\nlea esi, [rsi-1]\ncall sub_1149\nmov ebp, eax\nmov esi, r12d\nsub esi, ebx\nlea edi, [r12-1]\ncall sub_1149\nadd eax, ebp\njmp short loc_1167\nlocret_1189:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(__int64 a1, unsigned int a2)\n{\n __int64 result; // rax\n int v3; // ebp\n\n result = 1LL;\n if ( a2 | (unsigned int)a1 )\n {\n result = a2;\n if ( a2 )\n {\n v3 = sub_1149(a1, a2 - 1);\n return v3 + (unsigned int)sub_1149((unsigned int)(a1 - 1), (unsigned int)a1 - a2);\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(long long a1, unsigned int a2) {\n long long result;\n int v3;\n result = 1LL;\n if (a2 | (unsigned int)a1) {\n result = a2;\n if (a2) {\n v3 = sub_1149(a1, a2 - 1);\n return v3 + (unsigned int)sub_1149((unsigned int)(a1 - 1),\n (unsigned int)a1 - a2);\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, unsigned int a2) {\n long long result;\n int v3;\n result = 1LL;\n if (a2 | (unsigned int)a1) {\n result = a2;\n if (a2) {\n v3 = func0(a1, a2 - 1);\n return v3 +\n (unsigned int)func0((unsigned int)(a1 - 1), (unsigned int)a1 - a2);\n }\n }\n return result;\n}" + }, + { + "index": 346, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n, int k) {\n if (n == 0 && k == 0) {\n return 1;\n }\n if (k == 0) {\n return 0;\n }\n return func0(n, k - 1) + func0(n - 1, n - k);\n}", + "test": "int main() {\n\n assert(func0(4, 3) == 5);\n\n assert(func0(4, 2) == 4);\n\n assert(func0(3, 1) == 1);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov %edi,%eax\npush %r12\nor %esi,%eax\npush %rbp\npush %rbx\nje 1258 \nmov %esi,%ebx\ntest %esi,%esi\nje 1270 \nmov %edi,%ebp\nxor %r12d,%r12d\nlea -0x1(%rbx),%esi\nmov %ebp,%edi\ncallq 1200 \nmov %ebp,%edx\nsub $0x1,%ebp\nsub %ebx,%edx\nadd %eax,%r12d\nmov %edx,%eax\nmov %edx,%ebx\nor %ebp,%eax\nje 1248 \ntest %ebx,%ebx\njne 1219 \nmov %r12d,%eax\npop %rbx\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax)\nadd $0x1,%r12d\npop %rbx\npop %rbp\nmov %r12d,%eax\npop %r12\nretq\nnopl 0x0(%rax)\nmov $0x1,%r12d\npop %rbx\npop %rbp\nmov %r12d,%eax\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxor %r12d,%r12d\njmp 1239 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov eax, edi\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 68h\nor eax, esi\njz loc_1741\nmov ebp, esi\ntest esi, esi\njz loc_1537\nxor r14d, r14d\nmov ebx, edi\nloc_122B:\nlea r15d, [rbp-1]\nmov eax, r15d\nor eax, ebx\njz loc_1728\ntest r15d, r15d\njz loc_151B\nloc_1243:\nmov [rsp+98h+var_68], ebp\nxor eax, eax\nmov esi, r14d\nmov r13d, eax\nmov eax, ebx\nloc_1251:\nlea ebp, [r15-1]\nmov ecx, ebp\nor ecx, ebx\njz loc_16EA\ntest ebp, ebp\njz loc_14F1\nloc_1267:\nmov [rsp+98h+var_64], r15d\nmov ecx, ebx\nxor edx, edx\nmov r9d, esi\nmov [rsp+98h+var_60], ebx\nmov r12d, ecx\nmov ebx, ebp\nmov r8d, eax\nmov [rsp+98h+var_5C], r13d\nmov r13d, edx\nloc_1287:\nlea r14d, [rbx-1]\nmov eax, r14d\nor eax, r12d\njz loc_16D0\ntest r14d, r14d\njz loc_14BB\nloc_12A0:\nmov [rsp+98h+var_58], ebx\nxor r15d, r15d\nmov ebp, r12d\nmov [rsp+98h+var_54], r12d\nloc_12AF:\nlea ebx, [r14-1]\nmov eax, ebx\nor eax, ebp\njz loc_16B7\ntest ebx, ebx\njz loc_1493\nloc_12C5:\nmov [rsp+98h+var_50], r9d\nxor r12d, r12d\nmov [rsp+98h+var_48], ebp\nmov [rsp+98h+var_40], r15d\nmov [rsp+98h+var_3C], r8d\nmov [rsp+98h+var_4C], r13d\nmov r13d, ebx\nmov [rsp+98h+var_44], r14d\nmov r14d, r12d\nloc_12EB:\nlea ebx, [r13-1]\nmov eax, ebx\nor eax, ebp\njz loc_1684\ntest ebx, ebx\njz loc_1454\nloc_1301:\nxor r15d, r15d\nmov edx, ebp\nmov ecx, r14d\nmov esi, r13d\nmov r14d, ebp\nmov eax, ebx\nmov ebp, r15d\nloc_1314:\nlea r13d, [rax-1]\nmov edi, r13d\nor edi, r14d\njz loc_161C\ntest r13d, r13d\njz loc_142A\nloc_132D:\nmov edi, ebp\nxor r15d, r15d\nmov ebp, r14d\nloc_1335:\nlea r12d, [r13-1]\nmov ebx, r12d\nor ebx, ebp\njz loc_169D\ntest r12d, r12d\njz loc_1409\nloc_134D:\nmov [rsp+98h+var_8C], esi\nxor ebx, ebx\nmov [rsp+98h+var_88], edx\nmov [rsp+98h+var_84], ecx\nmov [rsp+98h+var_80], r14d\nmov [rsp+98h+var_78], edi\nmov [rsp+98h+var_70], r13d\nmov [rsp+98h+var_7C], eax\nmov eax, ebp\nmov [rsp+98h+var_74], ebp\nmov ebp, r12d\nmov r12d, ebx\nloc_1379:\nlea ebx, [rbp-1]\nmov edx, ebx\nor edx, eax\njz loc_1550\ntest ebx, ebx\njz short loc_13CF\nloc_138A:\nmov [rsp+98h+var_6C], r12d\nmov r14d, eax\nmov r12d, ebp\nxor r13d, r13d\nmov ebp, eax\nloc_139A:\nmov edi, r14d\nlea esi, [rbx-1]\ncall func0\nmov edi, r14d\nsub r14d, 1\nsub edi, ebx\nadd r13d, eax\nmov eax, edi\nmov ebx, edi\nor eax, r14d\njz loc_1638\ntest ebx, ebx\njnz short loc_139A\nmov eax, ebp\nmov ebp, r12d\nmov r12d, [rsp+98h+var_6C]\nadd r12d, r13d\nloc_13CF:\nmov ecx, eax\nsub eax, 1\nsub ecx, ebp\nmov ebp, ecx\nor ecx, eax\njz loc_1658\nloc_13E0:\ntest ebp, ebp\njnz short loc_1379\nmov esi, [rsp+98h+var_8C]\nmov edx, [rsp+98h+var_88]\nadd r15d, r12d\nmov ecx, [rsp+98h+var_84]\nmov r14d, [rsp+98h+var_80]\nmov eax, [rsp+98h+var_7C]\nmov edi, [rsp+98h+var_78]\nmov ebp, [rsp+98h+var_74]\nmov r13d, [rsp+98h+var_70]\nloc_1409:\nmov ebx, ebp\nsub ebp, 1\nsub ebx, r13d\nmov r13d, ebx\nor ebx, ebp\njz loc_1568\ntest r13d, r13d\njnz loc_1335\nmov ebp, edi\nadd ebp, r15d\nloc_142A:\nmov edi, r14d\nsub r14d, 1\nsub edi, eax\nmov eax, edi\nor edi, r14d\njz loc_1581\nloc_143E:\ntest eax, eax\njnz loc_1314\nmov r15d, ebp\nmov r14d, ecx\nmov r13d, esi\nmov ebp, edx\nadd r14d, r15d\nloc_1454:\nmov eax, ebp\nsub ebp, 1\nsub eax, r13d\nmov r13d, eax\nor eax, ebp\njz loc_15A1\nloc_1467:\ntest r13d, r13d\njnz loc_12EB\nmov r15d, [rsp+98h+var_40]\nmov r12d, r14d\nmov r9d, [rsp+98h+var_50]\nmov r13d, [rsp+98h+var_4C]\nmov ebp, [rsp+98h+var_48]\nmov r14d, [rsp+98h+var_44]\nmov r8d, [rsp+98h+var_3C]\nadd r15d, r12d\nloc_1493:\nmov eax, ebp\nsub ebp, 1\nsub eax, r14d\nmov r14d, eax\nor eax, ebp\njz loc_15D9\nloc_14A6:\ntest r14d, r14d\njnz loc_12AF\nmov ebx, [rsp+98h+var_58]\nmov r12d, [rsp+98h+var_54]\nadd r13d, r15d\nloc_14BB:\nmov eax, r12d\nsub r12d, 1\nsub eax, ebx\nmov ebx, eax\nor eax, r12d\njz loc_15FB\nloc_14CF:\ntest ebx, ebx\njnz loc_1287\nmov edx, r13d\nmov r13d, [rsp+98h+var_5C]\nmov r15d, [rsp+98h+var_64]\nmov esi, r9d\nmov ebx, [rsp+98h+var_60]\nmov eax, r8d\nadd r13d, edx\nloc_14F1:\nmov ecx, ebx\nsub ebx, 1\nsub ecx, r15d\nmov edx, ecx\nmov r15d, ecx\nor edx, ebx\njz loc_1703\ntest r15d, r15d\njnz loc_1251\nmov r14d, esi\nmov ebp, [rsp+98h+var_68]\nmov ebx, eax\nadd r14d, r13d\nloc_151B:\nmov eax, ebx\nsub ebx, 1\nsub eax, ebp\nmov ebp, eax\nor eax, ebx\njz loc_171F\nloc_152C:\ntest ebp, ebp\njnz loc_122B\nmov ebp, r14d\nloc_1537:\nadd rsp, 68h\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1550:\nadd r12d, 1\nmov ebp, 0FFFFFFFFh\nmov eax, 0FFFFFFFFh\nmov ebx, 0FFFFFFFEh\njmp loc_138A\nloc_1568:\nlea ebp, [rdi+r15+1]\nmov edi, r14d\nsub r14d, 1\nsub edi, eax\nmov eax, edi\nor edi, r14d\njnz loc_143E\nloc_1581:\nmov r15d, ebp\nmov ebp, edx\nmov r13d, esi\nmov eax, ebp\nsub ebp, 1\nlea r14d, [rcx+r15+1]\nsub eax, r13d\nmov r13d, eax\nor eax, ebp\njnz loc_1467\nloc_15A1:\nmov ebp, [rsp+98h+var_48]\nmov r12d, r14d\nmov r14d, [rsp+98h+var_44]\nmov r15d, [rsp+98h+var_40]\nmov r9d, [rsp+98h+var_50]\nmov eax, ebp\nsub ebp, 1\nmov r13d, [rsp+98h+var_4C]\nmov r8d, [rsp+98h+var_3C]\nsub eax, r14d\nlea r15d, [r15+r12+1]\nmov r14d, eax\nor eax, ebp\njnz loc_14A6\nloc_15D9:\nmov r12d, [rsp+98h+var_54]\nmov ebx, [rsp+98h+var_58]\nlea r13d, [r13+r15+1]\nmov eax, r12d\nsub r12d, 1\nsub eax, ebx\nmov ebx, eax\nor eax, r12d\njnz loc_14CF\nloc_15FB:\nmov edx, r13d\nmov r13d, [rsp+98h+var_5C]\nmov r15d, [rsp+98h+var_64]\nmov esi, r9d\nmov ebx, [rsp+98h+var_60]\nmov eax, r8d\nlea r13d, [r13+rdx+1]\njmp loc_14F1\nloc_161C:\nadd ebp, 1\nmov eax, 0FFFFFFFFh\nmov r14d, 0FFFFFFFFh\nmov r13d, 0FFFFFFFEh\njmp loc_132D\nloc_1638:\nmov eax, ebp\nmov ebp, r12d\nmov r12d, [rsp+98h+var_6C]\nmov ecx, eax\nsub eax, 1\nsub ecx, ebp\nlea r12d, [r13+r12+1]\nmov ebp, ecx\nor ecx, eax\njnz loc_13E0\nloc_1658:\nmov esi, [rsp+98h+var_8C]\nmov edx, [rsp+98h+var_88]\nlea r15d, [r15+r12+1]\nmov ecx, [rsp+98h+var_84]\nmov r14d, [rsp+98h+var_80]\nmov eax, [rsp+98h+var_7C]\nmov edi, [rsp+98h+var_78]\nmov ebp, [rsp+98h+var_74]\nmov r13d, [rsp+98h+var_70]\njmp loc_1409\nloc_1684:\nadd r14d, 1\nmov r13d, 0FFFFFFFFh\nmov ebp, 0FFFFFFFFh\nmov ebx, 0FFFFFFFEh\njmp loc_1301\nloc_169D:\nadd r15d, 1\nmov r13d, 0FFFFFFFFh\nmov ebp, 0FFFFFFFFh\nmov r12d, 0FFFFFFFEh\njmp loc_134D\nloc_16B7:\nadd r15d, 1\nmov r14d, 0FFFFFFFFh\nmov ebp, 0FFFFFFFFh\nmov ebx, 0FFFFFFFEh\njmp loc_12C5\nloc_16D0:\nadd r13d, 1\nmov ebx, 0FFFFFFFFh\nmov r12d, 0FFFFFFFFh\nmov r14d, 0FFFFFFFEh\njmp loc_12A0\nloc_16EA:\nadd r13d, 1\nmov r15d, 0FFFFFFFFh\nmov ebx, 0FFFFFFFFh\nmov ebp, 0FFFFFFFEh\njmp loc_1267\nloc_1703:\nmov ebp, [rsp+98h+var_68]\nmov ebx, eax\nlea r14d, [rsi+r13+1]\nmov eax, ebx\nsub ebx, 1\nsub eax, ebp\nmov ebp, eax\nor eax, ebx\njnz loc_152C\nloc_171F:\nlea ebp, [r14+1]\njmp loc_1537\nloc_1728:\nadd r14d, 1\nmov ebp, 0FFFFFFFFh\nmov ebx, 0FFFFFFFFh\nmov r15d, 0FFFFFFFEh\njmp loc_1243\nloc_1741:\nmov ebp, 1\njmp loc_1537", + "ida_pseudo": "__int64 __fastcall func0(int a1, unsigned int a2)\n{\n unsigned int v2; // ebp\n unsigned int v3; // r14d\n int v4; // ebx\n int v5; // r15d\n unsigned int v6; // esi\n int v7; // r13d\n int v8; // eax\n int v9; // ebp\n unsigned int v10; // r9d\n int v11; // r12d\n int v12; // ebx\n int v13; // r8d\n int v14; // r13d\n int v15; // r14d\n int v16; // r15d\n int v17; // ebp\n int v18; // ebx\n int v19; // r13d\n int v20; // r14d\n int v21; // ebx\n int v22; // edx\n int v23; // ecx\n int v24; // esi\n int v25; // r14d\n int v26; // eax\n int v27; // ebp\n int v28; // r13d\n int v29; // edi\n int v30; // r15d\n int v31; // ebp\n int v32; // r12d\n int v33; // eax\n int v34; // ebp\n int v35; // r12d\n int v36; // ebx\n unsigned int v37; // r14d\n int v38; // r12d\n int v39; // r13d\n int v40; // ebp\n int v41; // eax\n unsigned int v42; // edi\n int v43; // ecx\n int v44; // ebx\n int v45; // edi\n int v46; // r15d\n int v47; // eax\n int v48; // r12d\n int v49; // eax\n int v50; // eax\n int v51; // ecx\n int v52; // eax\n int v54; // edi\n int v55; // r15d\n int v56; // eax\n int v57; // ebp\n int v58; // ecx\n int v59; // [rsp+10h] [rbp-88h]\n int v60; // [rsp+14h] [rbp-84h]\n int v61; // [rsp+18h] [rbp-80h]\n int v62; // [rsp+1Ch] [rbp-7Ch]\n int v63; // [rsp+20h] [rbp-78h]\n int v64; // [rsp+24h] [rbp-74h]\n int v65; // [rsp+28h] [rbp-70h]\n int v66; // [rsp+2Ch] [rbp-6Ch]\n unsigned int v67; // [rsp+30h] [rbp-68h]\n int v68; // [rsp+34h] [rbp-64h]\n int v69; // [rsp+38h] [rbp-60h]\n int v70; // [rsp+3Ch] [rbp-5Ch]\n int v71; // [rsp+40h] [rbp-58h]\n int v72; // [rsp+44h] [rbp-54h]\n unsigned int v73; // [rsp+48h] [rbp-50h]\n int v74; // [rsp+4Ch] [rbp-4Ch]\n int v75; // [rsp+50h] [rbp-48h]\n int v76; // [rsp+54h] [rbp-44h]\n int v77; // [rsp+58h] [rbp-40h]\n int v78; // [rsp+5Ch] [rbp-3Ch]\n\n if ( !(a2 | a1) )\n return 1;\n v2 = a2;\n if ( a2 )\n {\n v3 = 0;\n v4 = a1;\n while ( 1 )\n {\n v5 = v2 - 1;\n if ( v4 | (v2 - 1) )\n {\n if ( v2 == 1 )\n goto LABEL_52;\n }\n else\n {\n ++v3;\n v2 = -1;\n v4 = -1;\n v5 = -2;\n }\n v67 = v2;\n v6 = v3;\n v7 = 0;\n v8 = v4;\n do\n {\n v9 = v5 - 1;\n if ( v4 | (v5 - 1) )\n {\n if ( v5 == 1 )\n goto LABEL_49;\n }\n else\n {\n ++v7;\n v5 = -1;\n v4 = -1;\n v9 = -2;\n }\n v68 = v5;\n v10 = v6;\n v69 = v4;\n v11 = v4;\n v12 = v9;\n v13 = v8;\n v70 = v7;\n v14 = 0;\n while ( 2 )\n {\n v15 = v12 - 1;\n if ( v11 | (v12 - 1) )\n {\n if ( v12 == 1 )\n goto LABEL_46;\n }\n else\n {\n ++v14;\n v12 = -1;\n v11 = -1;\n v15 = -2;\n }\n v71 = v12;\n v16 = 0;\n v17 = v11;\n v72 = v11;\n do\n {\n v18 = v15 - 1;\n if ( v17 | (v15 - 1) )\n {\n if ( v15 == 1 )\n goto LABEL_43;\n }\n else\n {\n ++v16;\n v15 = -1;\n v17 = -1;\n v18 = -2;\n }\n v73 = v10;\n v75 = v17;\n v77 = v16;\n v78 = v13;\n v74 = v14;\n v19 = v18;\n v76 = v15;\n v20 = 0;\n do\n {\n v21 = v19 - 1;\n if ( v17 | (v19 - 1) )\n {\n if ( v19 == 1 )\n goto LABEL_40;\n }\n else\n {\n ++v20;\n v19 = -1;\n v17 = -1;\n v21 = -2;\n }\n v22 = v17;\n v23 = v20;\n v24 = v19;\n v25 = v17;\n v26 = v21;\n v27 = 0;\n do\n {\n v28 = v26 - 1;\n if ( v25 | (v26 - 1) )\n {\n if ( v26 == 1 )\n goto LABEL_37;\n }\n else\n {\n ++v27;\n v26 = -1;\n v25 = -1;\n v28 = -2;\n }\n v29 = v27;\n v30 = 0;\n v31 = v25;\n do\n {\n v32 = v28 - 1;\n if ( v31 | (v28 - 1) )\n {\n if ( v28 == 1 )\n goto LABEL_34;\n }\n else\n {\n ++v30;\n v28 = -1;\n v31 = -1;\n v32 = -2;\n }\n v59 = v22;\n v60 = v23;\n v61 = v25;\n v63 = v29;\n v65 = v28;\n v62 = v26;\n v33 = v31;\n v64 = v31;\n v34 = v32;\n v35 = 0;\n while ( 1 )\n {\n v36 = v34 - 1;\n if ( !(v33 | (v34 - 1)) )\n break;\n if ( v34 != 1 )\n goto LABEL_27;\nLABEL_31:\n v43 = v33--;\n v34 = v43 - v34;\n if ( !(v33 | v34) )\n goto LABEL_64;\nLABEL_32:\n if ( !v34 )\n {\n v22 = v59;\n v30 += v35;\n v23 = v60;\n v25 = v61;\n v26 = v62;\n v29 = v63;\n v31 = v64;\n v28 = v65;\n goto LABEL_34;\n }\n }\n ++v35;\n v34 = -1;\n v33 = -1;\n v36 = -2;\nLABEL_27:\n v66 = v35;\n v37 = v33;\n v38 = v34;\n v39 = 0;\n v40 = v33;\n while ( 1 )\n {\n v41 = func0(v37, (unsigned int)(v36 - 1));\n v42 = v37--;\n v39 += v41;\n v36 = v42 - v36;\n if ( !(v37 | v36) )\n break;\n if ( !v36 )\n {\n v33 = v40;\n v34 = v38;\n v35 = v39 + v66;\n goto LABEL_31;\n }\n }\n v56 = v40;\n v57 = v38;\n v58 = v56;\n v33 = v56 - 1;\n v35 = v39 + v66 + 1;\n v34 = v58 - v57;\n if ( v33 | v34 )\n goto LABEL_32;\nLABEL_64:\n v22 = v59;\n v30 += v35 + 1;\n v23 = v60;\n v25 = v61;\n v26 = v62;\n v29 = v63;\n v31 = v64;\n v28 = v65;\nLABEL_34:\n v44 = v31--;\n v28 = v44 - v28;\n if ( !(v31 | v28) )\n {\n v27 = v29 + v30 + 1;\n v54 = v25--;\n v26 = v54 - v26;\n if ( v25 | v26 )\n goto LABEL_38;\n goto LABEL_58;\n }\n }\n while ( v28 );\n v27 = v30 + v29;\nLABEL_37:\n v45 = v25--;\n v26 = v45 - v26;\n if ( !(v25 | v26) )\n {\nLABEL_58:\n v55 = v27;\n v17 = v22 - 1;\n v20 = v23 + v55 + 1;\n v19 = v22 - v24;\n if ( (v22 - 1) | (v22 - v24) )\n goto LABEL_41;\n goto LABEL_59;\n }\nLABEL_38:\n ;\n }\n while ( v26 );\n v46 = v27;\n v19 = v24;\n v17 = v22;\n v20 = v46 + v23;\nLABEL_40:\n v47 = v17--;\n v19 = v47 - v19;\n if ( !(v17 | v19) )\n {\nLABEL_59:\n v10 = v73;\n v17 = v75 - 1;\n v14 = v74;\n v13 = v78;\n v16 = v77 + v20 + 1;\n v15 = v75 - v76;\n if ( (v75 - 1) | (v75 - v76) )\n goto LABEL_44;\nLABEL_60:\n v14 += v16 + 1;\n v11 = v72 - 1;\n v12 = v72 - v71;\n if ( (v72 - 1) | (v72 - v71) )\n goto LABEL_47;\n goto LABEL_61;\n }\nLABEL_41:\n ;\n }\n while ( v19 );\n v48 = v20;\n v10 = v73;\n v14 = v74;\n v17 = v75;\n v15 = v76;\n v13 = v78;\n v16 = v48 + v77;\nLABEL_43:\n v49 = v17--;\n v15 = v49 - v15;\n if ( !(v17 | v15) )\n goto LABEL_60;\nLABEL_44:\n ;\n }\n while ( v15 );\n v12 = v71;\n v11 = v72;\n v14 += v16;\nLABEL_46:\n v50 = v11--;\n v12 = v50 - v12;\n if ( v11 | v12 )\n {\nLABEL_47:\n if ( !v12 )\n {\n v5 = v68;\n v6 = v10;\n v4 = v69;\n v8 = v13;\n v7 = v14 + v70;\n goto LABEL_49;\n }\n continue;\n }\n break;\n }\nLABEL_61:\n v5 = v68;\n v6 = v10;\n v4 = v69;\n v8 = v13;\n v7 = v70 + v14 + 1;\nLABEL_49:\n v51 = v4--;\n v5 = v51 - v5;\n if ( !(v4 | v5) )\n {\n v3 = v6 + v7 + 1;\n v4 = v8 - 1;\n v2 = v8 - v67;\n if ( (v8 - 1) | (v8 - v67) )\n goto LABEL_53;\n return v3 + 1;\n }\n }\n while ( v5 );\n v2 = v67;\n v4 = v8;\n v3 = v7 + v6;\nLABEL_52:\n v52 = v4--;\n v2 = v52 - v2;\n if ( !(v4 | v2) )\n return v3 + 1;\nLABEL_53:\n if ( !v2 )\n return v3;\n }\n }\n return v2;\n}", + "ida_strip_asm": "sub_1200:\nendbr64\npush r15\nmov eax, edi\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 68h\nor eax, esi\njz loc_1741\nmov ebp, esi\ntest esi, esi\njz loc_1537\nxor r14d, r14d\nmov ebx, edi\nloc_122B:\nlea r15d, [rbp-1]\nmov eax, r15d\nor eax, ebx\njz loc_1728\ntest r15d, r15d\njz loc_151B\nloc_1243:\nmov [rsp+98h+var_68], ebp\nxor eax, eax\nmov esi, r14d\nmov r13d, eax\nmov eax, ebx\nloc_1251:\nlea ebp, [r15-1]\nmov ecx, ebp\nor ecx, ebx\njz loc_16EA\ntest ebp, ebp\njz loc_14F1\nloc_1267:\nmov [rsp+98h+var_64], r15d\nmov ecx, ebx\nxor edx, edx\nmov r9d, esi\nmov [rsp+98h+var_60], ebx\nmov r12d, ecx\nmov ebx, ebp\nmov r8d, eax\nmov [rsp+98h+var_5C], r13d\nmov r13d, edx\nloc_1287:\nlea r14d, [rbx-1]\nmov eax, r14d\nor eax, r12d\njz loc_16D0\ntest r14d, r14d\njz loc_14BB\nloc_12A0:\nmov [rsp+98h+var_58], ebx\nxor r15d, r15d\nmov ebp, r12d\nmov [rsp+98h+var_54], r12d\nloc_12AF:\nlea ebx, [r14-1]\nmov eax, ebx\nor eax, ebp\njz loc_16B7\ntest ebx, ebx\njz loc_1493\nloc_12C5:\nmov [rsp+98h+var_50], r9d\nxor r12d, r12d\nmov [rsp+98h+var_48], ebp\nmov [rsp+98h+var_40], r15d\nmov [rsp+98h+var_3C], r8d\nmov [rsp+98h+var_4C], r13d\nmov r13d, ebx\nmov [rsp+98h+var_44], r14d\nmov r14d, r12d\nloc_12EB:\nlea ebx, [r13-1]\nmov eax, ebx\nor eax, ebp\njz loc_1684\ntest ebx, ebx\njz loc_1454\nloc_1301:\nxor r15d, r15d\nmov edx, ebp\nmov ecx, r14d\nmov esi, r13d\nmov r14d, ebp\nmov eax, ebx\nmov ebp, r15d\nloc_1314:\nlea r13d, [rax-1]\nmov edi, r13d\nor edi, r14d\njz loc_161C\ntest r13d, r13d\njz loc_142A\nloc_132D:\nmov edi, ebp\nxor r15d, r15d\nmov ebp, r14d\nloc_1335:\nlea r12d, [r13-1]\nmov ebx, r12d\nor ebx, ebp\njz loc_169D\ntest r12d, r12d\njz loc_1409\nloc_134D:\nmov [rsp+98h+var_8C], esi\nxor ebx, ebx\nmov [rsp+98h+var_88], edx\nmov [rsp+98h+var_84], ecx\nmov [rsp+98h+var_80], r14d\nmov [rsp+98h+var_78], edi\nmov [rsp+98h+var_70], r13d\nmov [rsp+98h+var_7C], eax\nmov eax, ebp\nmov [rsp+98h+var_74], ebp\nmov ebp, r12d\nmov r12d, ebx\nloc_1379:\nlea ebx, [rbp-1]\nmov edx, ebx\nor edx, eax\njz loc_1550\ntest ebx, ebx\njz short loc_13CF\nloc_138A:\nmov [rsp+98h+var_6C], r12d\nmov r14d, eax\nmov r12d, ebp\nxor r13d, r13d\nmov ebp, eax\nloc_139A:\nmov edi, r14d\nlea esi, [rbx-1]\ncall sub_1200\nmov edi, r14d\nsub r14d, 1\nsub edi, ebx\nadd r13d, eax\nmov eax, edi\nmov ebx, edi\nor eax, r14d\njz loc_1638\ntest ebx, ebx\njnz short loc_139A\nmov eax, ebp\nmov ebp, r12d\nmov r12d, [rsp+98h+var_6C]\nadd r12d, r13d\nloc_13CF:\nmov ecx, eax\nsub eax, 1\nsub ecx, ebp\nmov ebp, ecx\nor ecx, eax\njz loc_1658\nloc_13E0:\ntest ebp, ebp\njnz short loc_1379\nmov esi, [rsp+98h+var_8C]\nmov edx, [rsp+98h+var_88]\nadd r15d, r12d\nmov ecx, [rsp+98h+var_84]\nmov r14d, [rsp+98h+var_80]\nmov eax, [rsp+98h+var_7C]\nmov edi, [rsp+98h+var_78]\nmov ebp, [rsp+98h+var_74]\nmov r13d, [rsp+98h+var_70]\nloc_1409:\nmov ebx, ebp\nsub ebp, 1\nsub ebx, r13d\nmov r13d, ebx\nor ebx, ebp\njz loc_1568\ntest r13d, r13d\njnz loc_1335\nmov ebp, edi\nadd ebp, r15d\nloc_142A:\nmov edi, r14d\nsub r14d, 1\nsub edi, eax\nmov eax, edi\nor edi, r14d\njz loc_1581\nloc_143E:\ntest eax, eax\njnz loc_1314\nmov r15d, ebp\nmov r14d, ecx\nmov r13d, esi\nmov ebp, edx\nadd r14d, r15d\nloc_1454:\nmov eax, ebp\nsub ebp, 1\nsub eax, r13d\nmov r13d, eax\nor eax, ebp\njz loc_15A1\nloc_1467:\ntest r13d, r13d\njnz loc_12EB\nmov r15d, [rsp+98h+var_40]\nmov r12d, r14d\nmov r9d, [rsp+98h+var_50]\nmov r13d, [rsp+98h+var_4C]\nmov ebp, [rsp+98h+var_48]\nmov r14d, [rsp+98h+var_44]\nmov r8d, [rsp+98h+var_3C]\nadd r15d, r12d\nloc_1493:\nmov eax, ebp\nsub ebp, 1\nsub eax, r14d\nmov r14d, eax\nor eax, ebp\njz loc_15D9\nloc_14A6:\ntest r14d, r14d\njnz loc_12AF\nmov ebx, [rsp+98h+var_58]\nmov r12d, [rsp+98h+var_54]\nadd r13d, r15d\nloc_14BB:\nmov eax, r12d\nsub r12d, 1\nsub eax, ebx\nmov ebx, eax\nor eax, r12d\njz loc_15FB\nloc_14CF:\ntest ebx, ebx\njnz loc_1287\nmov edx, r13d\nmov r13d, [rsp+98h+var_5C]\nmov r15d, [rsp+98h+var_64]\nmov esi, r9d\nmov ebx, [rsp+98h+var_60]\nmov eax, r8d\nadd r13d, edx\nloc_14F1:\nmov ecx, ebx\nsub ebx, 1\nsub ecx, r15d\nmov edx, ecx\nmov r15d, ecx\nor edx, ebx\njz loc_1703\ntest r15d, r15d\njnz loc_1251\nmov r14d, esi\nmov ebp, [rsp+98h+var_68]\nmov ebx, eax\nadd r14d, r13d\nloc_151B:\nmov eax, ebx\nsub ebx, 1\nsub eax, ebp\nmov ebp, eax\nor eax, ebx\njz loc_171F\nloc_152C:\ntest ebp, ebp\njnz loc_122B\nmov ebp, r14d\nloc_1537:\nadd rsp, 68h\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1550:\nadd r12d, 1\nmov ebp, 0FFFFFFFFh\nmov eax, 0FFFFFFFFh\nmov ebx, 0FFFFFFFEh\njmp loc_138A\nloc_1568:\nlea ebp, [rdi+r15+1]\nmov edi, r14d\nsub r14d, 1\nsub edi, eax\nmov eax, edi\nor edi, r14d\njnz loc_143E\nloc_1581:\nmov r15d, ebp\nmov ebp, edx\nmov r13d, esi\nmov eax, ebp\nsub ebp, 1\nlea r14d, [rcx+r15+1]\nsub eax, r13d\nmov r13d, eax\nor eax, ebp\njnz loc_1467\nloc_15A1:\nmov ebp, [rsp+98h+var_48]\nmov r12d, r14d\nmov r14d, [rsp+98h+var_44]\nmov r15d, [rsp+98h+var_40]\nmov r9d, [rsp+98h+var_50]\nmov eax, ebp\nsub ebp, 1\nmov r13d, [rsp+98h+var_4C]\nmov r8d, [rsp+98h+var_3C]\nsub eax, r14d\nlea r15d, [r15+r12+1]\nmov r14d, eax\nor eax, ebp\njnz loc_14A6\nloc_15D9:\nmov r12d, [rsp+98h+var_54]\nmov ebx, [rsp+98h+var_58]\nlea r13d, [r13+r15+1]\nmov eax, r12d\nsub r12d, 1\nsub eax, ebx\nmov ebx, eax\nor eax, r12d\njnz loc_14CF\nloc_15FB:\nmov edx, r13d\nmov r13d, [rsp+98h+var_5C]\nmov r15d, [rsp+98h+var_64]\nmov esi, r9d\nmov ebx, [rsp+98h+var_60]\nmov eax, r8d\nlea r13d, [r13+rdx+1]\njmp loc_14F1\nloc_161C:\nadd ebp, 1\nmov eax, 0FFFFFFFFh\nmov r14d, 0FFFFFFFFh\nmov r13d, 0FFFFFFFEh\njmp loc_132D\nloc_1638:\nmov eax, ebp\nmov ebp, r12d\nmov r12d, [rsp+98h+var_6C]\nmov ecx, eax\nsub eax, 1\nsub ecx, ebp\nlea r12d, [r13+r12+1]\nmov ebp, ecx\nor ecx, eax\njnz loc_13E0\nloc_1658:\nmov esi, [rsp+98h+var_8C]\nmov edx, [rsp+98h+var_88]\nlea r15d, [r15+r12+1]\nmov ecx, [rsp+98h+var_84]\nmov r14d, [rsp+98h+var_80]\nmov eax, [rsp+98h+var_7C]\nmov edi, [rsp+98h+var_78]\nmov ebp, [rsp+98h+var_74]\nmov r13d, [rsp+98h+var_70]\njmp loc_1409\nloc_1684:\nadd r14d, 1\nmov r13d, 0FFFFFFFFh\nmov ebp, 0FFFFFFFFh\nmov ebx, 0FFFFFFFEh\njmp loc_1301\nloc_169D:\nadd r15d, 1\nmov r13d, 0FFFFFFFFh\nmov ebp, 0FFFFFFFFh\nmov r12d, 0FFFFFFFEh\njmp loc_134D\nloc_16B7:\nadd r15d, 1\nmov r14d, 0FFFFFFFFh\nmov ebp, 0FFFFFFFFh\nmov ebx, 0FFFFFFFEh\njmp loc_12C5\nloc_16D0:\nadd r13d, 1\nmov ebx, 0FFFFFFFFh\nmov r12d, 0FFFFFFFFh\nmov r14d, 0FFFFFFFEh\njmp loc_12A0\nloc_16EA:\nadd r13d, 1\nmov r15d, 0FFFFFFFFh\nmov ebx, 0FFFFFFFFh\nmov ebp, 0FFFFFFFEh\njmp loc_1267\nloc_1703:\nmov ebp, [rsp+98h+var_68]\nmov ebx, eax\nlea r14d, [rsi+r13+1]\nmov eax, ebx\nsub ebx, 1\nsub eax, ebp\nmov ebp, eax\nor eax, ebx\njnz loc_152C\nloc_171F:\nlea ebp, [r14+1]\njmp loc_1537\nloc_1728:\nadd r14d, 1\nmov ebp, 0FFFFFFFFh\nmov ebx, 0FFFFFFFFh\nmov r15d, 0FFFFFFFEh\njmp loc_1243\nloc_1741:\nmov ebp, 1\njmp loc_1537", + "ida_strip_pseudo": "__int64 __fastcall sub_1200(int a1, unsigned int a2)\n{\n unsigned int v2; // ebp\n unsigned int v3; // r14d\n int v4; // ebx\n int v5; // r15d\n unsigned int v6; // esi\n int v7; // r13d\n int v8; // eax\n int v9; // ebp\n unsigned int v10; // r9d\n int v11; // r12d\n int v12; // ebx\n int v13; // r8d\n int v14; // r13d\n int v15; // r14d\n int v16; // r15d\n int v17; // ebp\n int v18; // ebx\n int v19; // r13d\n int v20; // r14d\n int v21; // ebx\n int v22; // edx\n int v23; // ecx\n int v24; // esi\n int v25; // r14d\n int v26; // eax\n int v27; // ebp\n int v28; // r13d\n int v29; // edi\n int v30; // r15d\n int v31; // ebp\n int v32; // r12d\n int v33; // eax\n int v34; // ebp\n int v35; // r12d\n int v36; // ebx\n unsigned int v37; // r14d\n int v38; // r12d\n int v39; // r13d\n int v40; // ebp\n int v41; // eax\n unsigned int v42; // edi\n int v43; // ecx\n int v44; // ebx\n int v45; // edi\n int v46; // r15d\n int v47; // eax\n int v48; // r12d\n int v49; // eax\n int v50; // eax\n int v51; // ecx\n int v52; // eax\n int v54; // edi\n int v55; // r15d\n int v56; // eax\n int v57; // ebp\n int v58; // ecx\n int v59; // [rsp+10h] [rbp-88h]\n int v60; // [rsp+14h] [rbp-84h]\n int v61; // [rsp+18h] [rbp-80h]\n int v62; // [rsp+1Ch] [rbp-7Ch]\n int v63; // [rsp+20h] [rbp-78h]\n int v64; // [rsp+24h] [rbp-74h]\n int v65; // [rsp+28h] [rbp-70h]\n int v66; // [rsp+2Ch] [rbp-6Ch]\n unsigned int v67; // [rsp+30h] [rbp-68h]\n int v68; // [rsp+34h] [rbp-64h]\n int v69; // [rsp+38h] [rbp-60h]\n int v70; // [rsp+3Ch] [rbp-5Ch]\n int v71; // [rsp+40h] [rbp-58h]\n int v72; // [rsp+44h] [rbp-54h]\n unsigned int v73; // [rsp+48h] [rbp-50h]\n int v74; // [rsp+4Ch] [rbp-4Ch]\n int v75; // [rsp+50h] [rbp-48h]\n int v76; // [rsp+54h] [rbp-44h]\n int v77; // [rsp+58h] [rbp-40h]\n int v78; // [rsp+5Ch] [rbp-3Ch]\n\n if ( !(a2 | a1) )\n return 1;\n v2 = a2;\n if ( a2 )\n {\n v3 = 0;\n v4 = a1;\n while ( 1 )\n {\n v5 = v2 - 1;\n if ( v4 | (v2 - 1) )\n {\n if ( v2 == 1 )\n goto LABEL_52;\n }\n else\n {\n ++v3;\n v2 = -1;\n v4 = -1;\n v5 = -2;\n }\n v67 = v2;\n v6 = v3;\n v7 = 0;\n v8 = v4;\n do\n {\n v9 = v5 - 1;\n if ( v4 | (v5 - 1) )\n {\n if ( v5 == 1 )\n goto LABEL_49;\n }\n else\n {\n ++v7;\n v5 = -1;\n v4 = -1;\n v9 = -2;\n }\n v68 = v5;\n v10 = v6;\n v69 = v4;\n v11 = v4;\n v12 = v9;\n v13 = v8;\n v70 = v7;\n v14 = 0;\n while ( 2 )\n {\n v15 = v12 - 1;\n if ( v11 | (v12 - 1) )\n {\n if ( v12 == 1 )\n goto LABEL_46;\n }\n else\n {\n ++v14;\n v12 = -1;\n v11 = -1;\n v15 = -2;\n }\n v71 = v12;\n v16 = 0;\n v17 = v11;\n v72 = v11;\n do\n {\n v18 = v15 - 1;\n if ( v17 | (v15 - 1) )\n {\n if ( v15 == 1 )\n goto LABEL_43;\n }\n else\n {\n ++v16;\n v15 = -1;\n v17 = -1;\n v18 = -2;\n }\n v73 = v10;\n v75 = v17;\n v77 = v16;\n v78 = v13;\n v74 = v14;\n v19 = v18;\n v76 = v15;\n v20 = 0;\n do\n {\n v21 = v19 - 1;\n if ( v17 | (v19 - 1) )\n {\n if ( v19 == 1 )\n goto LABEL_40;\n }\n else\n {\n ++v20;\n v19 = -1;\n v17 = -1;\n v21 = -2;\n }\n v22 = v17;\n v23 = v20;\n v24 = v19;\n v25 = v17;\n v26 = v21;\n v27 = 0;\n do\n {\n v28 = v26 - 1;\n if ( v25 | (v26 - 1) )\n {\n if ( v26 == 1 )\n goto LABEL_37;\n }\n else\n {\n ++v27;\n v26 = -1;\n v25 = -1;\n v28 = -2;\n }\n v29 = v27;\n v30 = 0;\n v31 = v25;\n do\n {\n v32 = v28 - 1;\n if ( v31 | (v28 - 1) )\n {\n if ( v28 == 1 )\n goto LABEL_34;\n }\n else\n {\n ++v30;\n v28 = -1;\n v31 = -1;\n v32 = -2;\n }\n v59 = v22;\n v60 = v23;\n v61 = v25;\n v63 = v29;\n v65 = v28;\n v62 = v26;\n v33 = v31;\n v64 = v31;\n v34 = v32;\n v35 = 0;\n while ( 1 )\n {\n v36 = v34 - 1;\n if ( !(v33 | (v34 - 1)) )\n break;\n if ( v34 != 1 )\n goto LABEL_27;\nLABEL_31:\n v43 = v33--;\n v34 = v43 - v34;\n if ( !(v33 | v34) )\n goto LABEL_64;\nLABEL_32:\n if ( !v34 )\n {\n v22 = v59;\n v30 += v35;\n v23 = v60;\n v25 = v61;\n v26 = v62;\n v29 = v63;\n v31 = v64;\n v28 = v65;\n goto LABEL_34;\n }\n }\n ++v35;\n v34 = -1;\n v33 = -1;\n v36 = -2;\nLABEL_27:\n v66 = v35;\n v37 = v33;\n v38 = v34;\n v39 = 0;\n v40 = v33;\n while ( 1 )\n {\n v41 = sub_1200(v37, (unsigned int)(v36 - 1));\n v42 = v37--;\n v39 += v41;\n v36 = v42 - v36;\n if ( !(v37 | v36) )\n break;\n if ( !v36 )\n {\n v33 = v40;\n v34 = v38;\n v35 = v39 + v66;\n goto LABEL_31;\n }\n }\n v56 = v40;\n v57 = v38;\n v58 = v56;\n v33 = v56 - 1;\n v35 = v39 + v66 + 1;\n v34 = v58 - v57;\n if ( v33 | v34 )\n goto LABEL_32;\nLABEL_64:\n v22 = v59;\n v30 += v35 + 1;\n v23 = v60;\n v25 = v61;\n v26 = v62;\n v29 = v63;\n v31 = v64;\n v28 = v65;\nLABEL_34:\n v44 = v31--;\n v28 = v44 - v28;\n if ( !(v31 | v28) )\n {\n v27 = v29 + v30 + 1;\n v54 = v25--;\n v26 = v54 - v26;\n if ( v25 | v26 )\n goto LABEL_38;\n goto LABEL_58;\n }\n }\n while ( v28 );\n v27 = v30 + v29;\nLABEL_37:\n v45 = v25--;\n v26 = v45 - v26;\n if ( !(v25 | v26) )\n {\nLABEL_58:\n v55 = v27;\n v17 = v22 - 1;\n v20 = v23 + v55 + 1;\n v19 = v22 - v24;\n if ( (v22 - 1) | (v22 - v24) )\n goto LABEL_41;\n goto LABEL_59;\n }\nLABEL_38:\n ;\n }\n while ( v26 );\n v46 = v27;\n v19 = v24;\n v17 = v22;\n v20 = v46 + v23;\nLABEL_40:\n v47 = v17--;\n v19 = v47 - v19;\n if ( !(v17 | v19) )\n {\nLABEL_59:\n v10 = v73;\n v17 = v75 - 1;\n v14 = v74;\n v13 = v78;\n v16 = v77 + v20 + 1;\n v15 = v75 - v76;\n if ( (v75 - 1) | (v75 - v76) )\n goto LABEL_44;\nLABEL_60:\n v14 += v16 + 1;\n v11 = v72 - 1;\n v12 = v72 - v71;\n if ( (v72 - 1) | (v72 - v71) )\n goto LABEL_47;\n goto LABEL_61;\n }\nLABEL_41:\n ;\n }\n while ( v19 );\n v48 = v20;\n v10 = v73;\n v14 = v74;\n v17 = v75;\n v15 = v76;\n v13 = v78;\n v16 = v48 + v77;\nLABEL_43:\n v49 = v17--;\n v15 = v49 - v15;\n if ( !(v17 | v15) )\n goto LABEL_60;\nLABEL_44:\n ;\n }\n while ( v15 );\n v12 = v71;\n v11 = v72;\n v14 += v16;\nLABEL_46:\n v50 = v11--;\n v12 = v50 - v12;\n if ( v11 | v12 )\n {\nLABEL_47:\n if ( !v12 )\n {\n v5 = v68;\n v6 = v10;\n v4 = v69;\n v8 = v13;\n v7 = v14 + v70;\n goto LABEL_49;\n }\n continue;\n }\n break;\n }\nLABEL_61:\n v5 = v68;\n v6 = v10;\n v4 = v69;\n v8 = v13;\n v7 = v70 + v14 + 1;\nLABEL_49:\n v51 = v4--;\n v5 = v51 - v5;\n if ( !(v4 | v5) )\n {\n v3 = v6 + v7 + 1;\n v4 = v8 - 1;\n v2 = v8 - v67;\n if ( (v8 - 1) | (v8 - v67) )\n goto LABEL_53;\n return v3 + 1;\n }\n }\n while ( v5 );\n v2 = v67;\n v4 = v8;\n v3 = v7 + v6;\nLABEL_52:\n v52 = v4--;\n v2 = v52 - v2;\n if ( !(v4 | v2) )\n return v3 + 1;\nLABEL_53:\n if ( !v2 )\n return v3;\n }\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1200(int a1, unsigned int a2) {\n unsigned int v2;\n unsigned int v3;\n int v4;\n int v5;\n unsigned int v6;\n int v7;\n int v8;\n int v9;\n unsigned int v10;\n int v11;\n int v12;\n int v13;\n int v14;\n int v15;\n int v16;\n int v17;\n int v18;\n int v19;\n int v20;\n int v21;\n int v22;\n int v23;\n int v24;\n int v25;\n int v26;\n int v27;\n int v28;\n int v29;\n int v30;\n int v31;\n int v32;\n int v33;\n int v34;\n int v35;\n int v36;\n unsigned int v37;\n int v38;\n int v39;\n int v40;\n int v41;\n unsigned int v42;\n int v43;\n int v44;\n int v45;\n int v46;\n int v47;\n int v48;\n int v49;\n int v50;\n int v51;\n int v52;\n int v54;\n int v55;\n int v56;\n int v57;\n int v58;\n int v59;\n int v60;\n int v61;\n int v62;\n int v63;\n int v64;\n int v65;\n int v66;\n unsigned int v67;\n int v68;\n int v69;\n int v70;\n int v71;\n int v72;\n unsigned int v73;\n int v74;\n int v75;\n int v76;\n int v77;\n int v78;\n if (!(a2 | a1)) return 1;\n v2 = a2;\n if (a2) {\n v3 = 0;\n v4 = a1;\n while (1) {\n v5 = v2 - 1;\n if (v4 | (v2 - 1)) {\n if (v2 == 1) goto LABEL_52;\n } else {\n ++v3;\n v2 = -1;\n v4 = -1;\n v5 = -2;\n }\n v67 = v2;\n v6 = v3;\n v7 = 0;\n v8 = v4;\n do {\n v9 = v5 - 1;\n if (v4 | (v5 - 1)) {\n if (v5 == 1) goto LABEL_49;\n } else {\n ++v7;\n v5 = -1;\n v4 = -1;\n v9 = -2;\n }\n v68 = v5;\n v10 = v6;\n v69 = v4;\n v11 = v4;\n v12 = v9;\n v13 = v8;\n v70 = v7;\n v14 = 0;\n while (2) {\n v15 = v12 - 1;\n if (v11 | (v12 - 1)) {\n if (v12 == 1) goto LABEL_46;\n } else {\n ++v14;\n v12 = -1;\n v11 = -1;\n v15 = -2;\n }\n v71 = v12;\n v16 = 0;\n v17 = v11;\n v72 = v11;\n do {\n v18 = v15 - 1;\n if (v17 | (v15 - 1)) {\n if (v15 == 1) goto LABEL_43;\n } else {\n ++v16;\n v15 = -1;\n v17 = -1;\n v18 = -2;\n }\n v73 = v10;\n v75 = v17;\n v77 = v16;\n v78 = v13;\n v74 = v14;\n v19 = v18;\n v76 = v15;\n v20 = 0;\n do {\n v21 = v19 - 1;\n if (v17 | (v19 - 1)) {\n if (v19 == 1) goto LABEL_40;\n } else {\n ++v20;\n v19 = -1;\n v17 = -1;\n v21 = -2;\n }\n v22 = v17;\n v23 = v20;\n v24 = v19;\n v25 = v17;\n v26 = v21;\n v27 = 0;\n do {\n v28 = v26 - 1;\n if (v25 | (v26 - 1)) {\n if (v26 == 1) goto LABEL_37;\n } else {\n ++v27;\n v26 = -1;\n v25 = -1;\n v28 = -2;\n }\n v29 = v27;\n v30 = 0;\n v31 = v25;\n do {\n v32 = v28 - 1;\n if (v31 | (v28 - 1)) {\n if (v28 == 1) goto LABEL_34;\n } else {\n ++v30;\n v28 = -1;\n v31 = -1;\n v32 = -2;\n }\n v59 = v22;\n v60 = v23;\n v61 = v25;\n v63 = v29;\n v65 = v28;\n v62 = v26;\n v33 = v31;\n v64 = v31;\n v34 = v32;\n v35 = 0;\n while (1) {\n v36 = v34 - 1;\n if (!(v33 | (v34 - 1))) break;\n if (v34 != 1) goto LABEL_27;\n LABEL_31:\n v43 = v33--;\n v34 = v43 - v34;\n if (!(v33 | v34)) goto LABEL_64;\n LABEL_32:\n if (!v34) {\n v22 = v59;\n v30 += v35;\n v23 = v60;\n v25 = v61;\n v26 = v62;\n v29 = v63;\n v31 = v64;\n v28 = v65;\n goto LABEL_34;\n }\n }\n ++v35;\n v34 = -1;\n v33 = -1;\n v36 = -2;\n LABEL_27:\n v66 = v35;\n v37 = v33;\n v38 = v34;\n v39 = 0;\n v40 = v33;\n while (1) {\n v41 = sub_1200(v37, (unsigned int)(v36 - 1));\n v42 = v37--;\n v39 += v41;\n v36 = v42 - v36;\n if (!(v37 | v36)) break;\n if (!v36) {\n v33 = v40;\n v34 = v38;\n v35 = v39 + v66;\n goto LABEL_31;\n }\n }\n v56 = v40;\n v57 = v38;\n v58 = v56;\n v33 = v56 - 1;\n v35 = v39 + v66 + 1;\n v34 = v58 - v57;\n if (v33 | v34) goto LABEL_32;\n LABEL_64:\n v22 = v59;\n v30 += v35 + 1;\n v23 = v60;\n v25 = v61;\n v26 = v62;\n v29 = v63;\n v31 = v64;\n v28 = v65;\n LABEL_34:\n v44 = v31--;\n v28 = v44 - v28;\n if (!(v31 | v28)) {\n v27 = v29 + v30 + 1;\n v54 = v25--;\n v26 = v54 - v26;\n if (v25 | v26) goto LABEL_38;\n goto LABEL_58;\n }\n } while (v28);\n v27 = v30 + v29;\n LABEL_37:\n v45 = v25--;\n v26 = v45 - v26;\n if (!(v25 | v26)) {\n LABEL_58:\n v55 = v27;\n v17 = v22 - 1;\n v20 = v23 + v55 + 1;\n v19 = v22 - v24;\n if ((v22 - 1) | (v22 - v24)) goto LABEL_41;\n goto LABEL_59;\n }\n LABEL_38:;\n } while (v26);\n v46 = v27;\n v19 = v24;\n v17 = v22;\n v20 = v46 + v23;\n LABEL_40:\n v47 = v17--;\n v19 = v47 - v19;\n if (!(v17 | v19)) {\n LABEL_59:\n v10 = v73;\n v17 = v75 - 1;\n v14 = v74;\n v13 = v78;\n v16 = v77 + v20 + 1;\n v15 = v75 - v76;\n if ((v75 - 1) | (v75 - v76)) goto LABEL_44;\n LABEL_60:\n v14 += v16 + 1;\n v11 = v72 - 1;\n v12 = v72 - v71;\n if ((v72 - 1) | (v72 - v71)) goto LABEL_47;\n goto LABEL_61;\n }\n LABEL_41:;\n } while (v19);\n v48 = v20;\n v10 = v73;\n v14 = v74;\n v17 = v75;\n v15 = v76;\n v13 = v78;\n v16 = v48 + v77;\n LABEL_43:\n v49 = v17--;\n v15 = v49 - v15;\n if (!(v17 | v15)) goto LABEL_60;\n LABEL_44:;\n } while (v15);\n v12 = v71;\n v11 = v72;\n v14 += v16;\n LABEL_46:\n v50 = v11--;\n v12 = v50 - v12;\n if (v11 | v12) {\n LABEL_47:\n if (!v12) {\n v5 = v68;\n v6 = v10;\n v4 = v69;\n v8 = v13;\n v7 = v14 + v70;\n goto LABEL_49;\n }\n continue;\n }\n break;\n }\n LABEL_61:\n v5 = v68;\n v6 = v10;\n v4 = v69;\n v8 = v13;\n v7 = v70 + v14 + 1;\n LABEL_49:\n v51 = v4--;\n v5 = v51 - v5;\n if (!(v4 | v5)) {\n v3 = v6 + v7 + 1;\n v4 = v8 - 1;\n v2 = v8 - v67;\n if ((v8 - 1) | (v8 - v67)) goto LABEL_53;\n return v3 + 1;\n }\n } while (v5);\n v2 = v67;\n v4 = v8;\n v3 = v7 + v6;\n LABEL_52:\n v52 = v4--;\n v2 = v52 - v2;\n if (!(v4 | v2)) return v3 + 1;\n LABEL_53:\n if (!v2) return v3;\n }\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1, unsigned int a2) {\n unsigned int v2;\n unsigned int v3;\n int v4;\n int v5;\n unsigned int v6;\n int v7;\n int v8;\n int v9;\n unsigned int v10;\n int v11;\n int v12;\n int v13;\n int v14;\n int v15;\n int v16;\n int v17;\n int v18;\n int v19;\n int v20;\n int v21;\n int v22;\n int v23;\n int v24;\n int v25;\n int v26;\n int v27;\n int v28;\n int v29;\n int v30;\n int v31;\n int v32;\n int v33;\n int v34;\n int v35;\n int v36;\n unsigned int v37;\n int v38;\n int v39;\n int v40;\n int v41;\n unsigned int v42;\n int v43;\n int v44;\n int v45;\n int v46;\n int v47;\n int v48;\n int v49;\n int v50;\n int v51;\n int v52;\n int v54;\n int v55;\n int v56;\n int v57;\n int v58;\n int v59;\n int v60;\n int v61;\n int v62;\n int v63;\n int v64;\n int v65;\n int v66;\n unsigned int v67;\n int v68;\n int v69;\n int v70;\n int v71;\n int v72;\n unsigned int v73;\n int v74;\n int v75;\n int v76;\n int v77;\n int v78;\n if (!(a2 | a1)) return 1;\n v2 = a2;\n if (a2) {\n v3 = 0;\n v4 = a1;\n while (1) {\n v5 = v2 - 1;\n if (v4 | (v2 - 1)) {\n if (v2 == 1) goto LABEL_52;\n } else {\n ++v3;\n v2 = -1;\n v4 = -1;\n v5 = -2;\n }\n v67 = v2;\n v6 = v3;\n v7 = 0;\n v8 = v4;\n do {\n v9 = v5 - 1;\n if (v4 | (v5 - 1)) {\n if (v5 == 1) goto LABEL_49;\n } else {\n ++v7;\n v5 = -1;\n v4 = -1;\n v9 = -2;\n }\n v68 = v5;\n v10 = v6;\n v69 = v4;\n v11 = v4;\n v12 = v9;\n v13 = v8;\n v70 = v7;\n v14 = 0;\n while (2) {\n v15 = v12 - 1;\n if (v11 | (v12 - 1)) {\n if (v12 == 1) goto LABEL_46;\n } else {\n ++v14;\n v12 = -1;\n v11 = -1;\n v15 = -2;\n }\n v71 = v12;\n v16 = 0;\n v17 = v11;\n v72 = v11;\n do {\n v18 = v15 - 1;\n if (v17 | (v15 - 1)) {\n if (v15 == 1) goto LABEL_43;\n } else {\n ++v16;\n v15 = -1;\n v17 = -1;\n v18 = -2;\n }\n v73 = v10;\n v75 = v17;\n v77 = v16;\n v78 = v13;\n v74 = v14;\n v19 = v18;\n v76 = v15;\n v20 = 0;\n do {\n v21 = v19 - 1;\n if (v17 | (v19 - 1)) {\n if (v19 == 1) goto LABEL_40;\n } else {\n ++v20;\n v19 = -1;\n v17 = -1;\n v21 = -2;\n }\n v22 = v17;\n v23 = v20;\n v24 = v19;\n v25 = v17;\n v26 = v21;\n v27 = 0;\n do {\n v28 = v26 - 1;\n if (v25 | (v26 - 1)) {\n if (v26 == 1) goto LABEL_37;\n } else {\n ++v27;\n v26 = -1;\n v25 = -1;\n v28 = -2;\n }\n v29 = v27;\n v30 = 0;\n v31 = v25;\n do {\n v32 = v28 - 1;\n if (v31 | (v28 - 1)) {\n if (v28 == 1) goto LABEL_34;\n } else {\n ++v30;\n v28 = -1;\n v31 = -1;\n v32 = -2;\n }\n v59 = v22;\n v60 = v23;\n v61 = v25;\n v63 = v29;\n v65 = v28;\n v62 = v26;\n v33 = v31;\n v64 = v31;\n v34 = v32;\n v35 = 0;\n while (1) {\n v36 = v34 - 1;\n if (!(v33 | (v34 - 1))) break;\n if (v34 != 1) goto LABEL_27;\n LABEL_31:\n v43 = v33--;\n v34 = v43 - v34;\n if (!(v33 | v34)) goto LABEL_64;\n LABEL_32:\n if (!v34) {\n v22 = v59;\n v30 += v35;\n v23 = v60;\n v25 = v61;\n v26 = v62;\n v29 = v63;\n v31 = v64;\n v28 = v65;\n goto LABEL_34;\n }\n }\n ++v35;\n v34 = -1;\n v33 = -1;\n v36 = -2;\n LABEL_27:\n v66 = v35;\n v37 = v33;\n v38 = v34;\n v39 = 0;\n v40 = v33;\n while (1) {\n v41 = func0(v37, (unsigned int)(v36 - 1));\n v42 = v37--;\n v39 += v41;\n v36 = v42 - v36;\n if (!(v37 | v36)) break;\n if (!v36) {\n v33 = v40;\n v34 = v38;\n v35 = v39 + v66;\n goto LABEL_31;\n }\n }\n v56 = v40;\n v57 = v38;\n v58 = v56;\n v33 = v56 - 1;\n v35 = v39 + v66 + 1;\n v34 = v58 - v57;\n if (v33 | v34) goto LABEL_32;\n LABEL_64:\n v22 = v59;\n v30 += v35 + 1;\n v23 = v60;\n v25 = v61;\n v26 = v62;\n v29 = v63;\n v31 = v64;\n v28 = v65;\n LABEL_34:\n v44 = v31--;\n v28 = v44 - v28;\n if (!(v31 | v28)) {\n v27 = v29 + v30 + 1;\n v54 = v25--;\n v26 = v54 - v26;\n if (v25 | v26) goto LABEL_38;\n goto LABEL_58;\n }\n } while (v28);\n v27 = v30 + v29;\n LABEL_37:\n v45 = v25--;\n v26 = v45 - v26;\n if (!(v25 | v26)) {\n LABEL_58:\n v55 = v27;\n v17 = v22 - 1;\n v20 = v23 + v55 + 1;\n v19 = v22 - v24;\n if ((v22 - 1) | (v22 - v24)) goto LABEL_41;\n goto LABEL_59;\n }\n LABEL_38:;\n } while (v26);\n v46 = v27;\n v19 = v24;\n v17 = v22;\n v20 = v46 + v23;\n LABEL_40:\n v47 = v17--;\n v19 = v47 - v19;\n if (!(v17 | v19)) {\n LABEL_59:\n v10 = v73;\n v17 = v75 - 1;\n v14 = v74;\n v13 = v78;\n v16 = v77 + v20 + 1;\n v15 = v75 - v76;\n if ((v75 - 1) | (v75 - v76)) goto LABEL_44;\n LABEL_60:\n v14 += v16 + 1;\n v11 = v72 - 1;\n v12 = v72 - v71;\n if ((v72 - 1) | (v72 - v71)) goto LABEL_47;\n goto LABEL_61;\n }\n LABEL_41:;\n } while (v19);\n v48 = v20;\n v10 = v73;\n v14 = v74;\n v17 = v75;\n v15 = v76;\n v13 = v78;\n v16 = v48 + v77;\n LABEL_43:\n v49 = v17--;\n v15 = v49 - v15;\n if (!(v17 | v15)) goto LABEL_60;\n LABEL_44:;\n } while (v15);\n v12 = v71;\n v11 = v72;\n v14 += v16;\n LABEL_46:\n v50 = v11--;\n v12 = v50 - v12;\n if (v11 | v12) {\n LABEL_47:\n if (!v12) {\n v5 = v68;\n v6 = v10;\n v4 = v69;\n v8 = v13;\n v7 = v14 + v70;\n goto LABEL_49;\n }\n continue;\n }\n break;\n }\n LABEL_61:\n v5 = v68;\n v6 = v10;\n v4 = v69;\n v8 = v13;\n v7 = v70 + v14 + 1;\n LABEL_49:\n v51 = v4--;\n v5 = v51 - v5;\n if (!(v4 | v5)) {\n v3 = v6 + v7 + 1;\n v4 = v8 - 1;\n v2 = v8 - v67;\n if ((v8 - 1) | (v8 - v67)) goto LABEL_53;\n return v3 + 1;\n }\n } while (v5);\n v2 = v67;\n v4 = v8;\n v3 = v7 + v6;\n LABEL_52:\n v52 = v4--;\n v2 = v52 - v2;\n if (!(v4 | v2)) return v3 + 1;\n LABEL_53:\n if (!v2) return v3;\n }\n }\n return v2;\n}" + }, + { + "index": 346, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n, int k) {\n if (n == 0 && k == 0) {\n return 1;\n }\n if (k == 0) {\n return 0;\n }\n return func0(n, k - 1) + func0(n - 1, n - k);\n}", + "test": "int main() {\n\n assert(func0(4, 3) == 5);\n\n assert(func0(4, 2) == 4);\n\n assert(func0(3, 1) == 1);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nmov %edi,%eax\npush %r12\nor %esi,%eax\npush %rbp\npush %rbx\nje 1258 \nmov %esi,%ebx\ntest %esi,%esi\nje 1270 \nmov %edi,%ebp\nxor %r12d,%r12d\nlea -0x1(%rbx),%esi\nmov %ebp,%edi\ncallq 1200 \nmov %ebp,%edx\nsub $0x1,%ebp\nsub %ebx,%edx\nadd %eax,%r12d\nmov %edx,%eax\nmov %edx,%ebx\nor %ebp,%eax\nje 1248 \ntest %ebx,%ebx\njne 1219 \nmov %r12d,%eax\npop %rbx\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax)\nadd $0x1,%r12d\npop %rbx\npop %rbp\nmov %r12d,%eax\npop %r12\nretq\nnopl 0x0(%rax)\nmov $0x1,%r12d\npop %rbx\npop %rbp\nmov %r12d,%eax\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxor %r12d,%r12d\njmp 1239 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov eax, edi\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 68h\nor eax, esi\njz loc_1741\nmov ebp, esi\ntest esi, esi\njz loc_1537\nxor r14d, r14d\nmov ebx, edi\nloc_122B:\nlea r15d, [rbp-1]\nmov eax, r15d\nor eax, ebx\njz loc_1728\ntest r15d, r15d\njz loc_151B\nloc_1243:\nmov [rsp+98h+var_68], ebp\nxor eax, eax\nmov esi, r14d\nmov r13d, eax\nmov eax, ebx\nloc_1251:\nlea ebp, [r15-1]\nmov ecx, ebp\nor ecx, ebx\njz loc_16EA\ntest ebp, ebp\njz loc_14F1\nloc_1267:\nmov [rsp+98h+var_64], r15d\nmov ecx, ebx\nxor edx, edx\nmov r9d, esi\nmov [rsp+98h+var_60], ebx\nmov r12d, ecx\nmov ebx, ebp\nmov r8d, eax\nmov [rsp+98h+var_5C], r13d\nmov r13d, edx\nloc_1287:\nlea r14d, [rbx-1]\nmov eax, r14d\nor eax, r12d\njz loc_16D0\ntest r14d, r14d\njz loc_14BB\nloc_12A0:\nmov [rsp+98h+var_58], ebx\nxor r15d, r15d\nmov ebp, r12d\nmov [rsp+98h+var_54], r12d\nloc_12AF:\nlea ebx, [r14-1]\nmov eax, ebx\nor eax, ebp\njz loc_16B7\ntest ebx, ebx\njz loc_1493\nloc_12C5:\nmov [rsp+98h+var_50], r9d\nxor r12d, r12d\nmov [rsp+98h+var_48], ebp\nmov [rsp+98h+var_40], r15d\nmov [rsp+98h+var_3C], r8d\nmov [rsp+98h+var_4C], r13d\nmov r13d, ebx\nmov [rsp+98h+var_44], r14d\nmov r14d, r12d\nloc_12EB:\nlea ebx, [r13-1]\nmov eax, ebx\nor eax, ebp\njz loc_1684\ntest ebx, ebx\njz loc_1454\nloc_1301:\nxor r15d, r15d\nmov edx, ebp\nmov ecx, r14d\nmov esi, r13d\nmov r14d, ebp\nmov eax, ebx\nmov ebp, r15d\nloc_1314:\nlea r13d, [rax-1]\nmov edi, r13d\nor edi, r14d\njz loc_161C\ntest r13d, r13d\njz loc_142A\nloc_132D:\nmov edi, ebp\nxor r15d, r15d\nmov ebp, r14d\nloc_1335:\nlea r12d, [r13-1]\nmov ebx, r12d\nor ebx, ebp\njz loc_169D\ntest r12d, r12d\njz loc_1409\nloc_134D:\nmov [rsp+98h+var_8C], esi\nxor ebx, ebx\nmov [rsp+98h+var_88], edx\nmov [rsp+98h+var_84], ecx\nmov [rsp+98h+var_80], r14d\nmov [rsp+98h+var_78], edi\nmov [rsp+98h+var_70], r13d\nmov [rsp+98h+var_7C], eax\nmov eax, ebp\nmov [rsp+98h+var_74], ebp\nmov ebp, r12d\nmov r12d, ebx\nloc_1379:\nlea ebx, [rbp-1]\nmov edx, ebx\nor edx, eax\njz loc_1550\ntest ebx, ebx\njz short loc_13CF\nloc_138A:\nmov [rsp+98h+var_6C], r12d\nmov r14d, eax\nmov r12d, ebp\nxor r13d, r13d\nmov ebp, eax\nloc_139A:\nmov edi, r14d\nlea esi, [rbx-1]\ncall func0\nmov edi, r14d\nsub r14d, 1\nsub edi, ebx\nadd r13d, eax\nmov eax, edi\nmov ebx, edi\nor eax, r14d\njz loc_1638\ntest ebx, ebx\njnz short loc_139A\nmov eax, ebp\nmov ebp, r12d\nmov r12d, [rsp+98h+var_6C]\nadd r12d, r13d\nloc_13CF:\nmov ecx, eax\nsub eax, 1\nsub ecx, ebp\nmov ebp, ecx\nor ecx, eax\njz loc_1658\nloc_13E0:\ntest ebp, ebp\njnz short loc_1379\nmov esi, [rsp+98h+var_8C]\nmov edx, [rsp+98h+var_88]\nadd r15d, r12d\nmov ecx, [rsp+98h+var_84]\nmov r14d, [rsp+98h+var_80]\nmov eax, [rsp+98h+var_7C]\nmov edi, [rsp+98h+var_78]\nmov ebp, [rsp+98h+var_74]\nmov r13d, [rsp+98h+var_70]\nloc_1409:\nmov ebx, ebp\nsub ebp, 1\nsub ebx, r13d\nmov r13d, ebx\nor ebx, ebp\njz loc_1568\ntest r13d, r13d\njnz loc_1335\nmov ebp, edi\nadd ebp, r15d\nloc_142A:\nmov edi, r14d\nsub r14d, 1\nsub edi, eax\nmov eax, edi\nor edi, r14d\njz loc_1581\nloc_143E:\ntest eax, eax\njnz loc_1314\nmov r15d, ebp\nmov r14d, ecx\nmov r13d, esi\nmov ebp, edx\nadd r14d, r15d\nloc_1454:\nmov eax, ebp\nsub ebp, 1\nsub eax, r13d\nmov r13d, eax\nor eax, ebp\njz loc_15A1\nloc_1467:\ntest r13d, r13d\njnz loc_12EB\nmov r15d, [rsp+98h+var_40]\nmov r12d, r14d\nmov r9d, [rsp+98h+var_50]\nmov r13d, [rsp+98h+var_4C]\nmov ebp, [rsp+98h+var_48]\nmov r14d, [rsp+98h+var_44]\nmov r8d, [rsp+98h+var_3C]\nadd r15d, r12d\nloc_1493:\nmov eax, ebp\nsub ebp, 1\nsub eax, r14d\nmov r14d, eax\nor eax, ebp\njz loc_15D9\nloc_14A6:\ntest r14d, r14d\njnz loc_12AF\nmov ebx, [rsp+98h+var_58]\nmov r12d, [rsp+98h+var_54]\nadd r13d, r15d\nloc_14BB:\nmov eax, r12d\nsub r12d, 1\nsub eax, ebx\nmov ebx, eax\nor eax, r12d\njz loc_15FB\nloc_14CF:\ntest ebx, ebx\njnz loc_1287\nmov edx, r13d\nmov r13d, [rsp+98h+var_5C]\nmov r15d, [rsp+98h+var_64]\nmov esi, r9d\nmov ebx, [rsp+98h+var_60]\nmov eax, r8d\nadd r13d, edx\nloc_14F1:\nmov ecx, ebx\nsub ebx, 1\nsub ecx, r15d\nmov edx, ecx\nmov r15d, ecx\nor edx, ebx\njz loc_1703\ntest r15d, r15d\njnz loc_1251\nmov r14d, esi\nmov ebp, [rsp+98h+var_68]\nmov ebx, eax\nadd r14d, r13d\nloc_151B:\nmov eax, ebx\nsub ebx, 1\nsub eax, ebp\nmov ebp, eax\nor eax, ebx\njz loc_171F\nloc_152C:\ntest ebp, ebp\njnz loc_122B\nmov ebp, r14d\nloc_1537:\nadd rsp, 68h\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1550:\nadd r12d, 1\nmov ebp, 0FFFFFFFFh\nmov eax, 0FFFFFFFFh\nmov ebx, 0FFFFFFFEh\njmp loc_138A\nloc_1568:\nlea ebp, [rdi+r15+1]\nmov edi, r14d\nsub r14d, 1\nsub edi, eax\nmov eax, edi\nor edi, r14d\njnz loc_143E\nloc_1581:\nmov r15d, ebp\nmov ebp, edx\nmov r13d, esi\nmov eax, ebp\nsub ebp, 1\nlea r14d, [rcx+r15+1]\nsub eax, r13d\nmov r13d, eax\nor eax, ebp\njnz loc_1467\nloc_15A1:\nmov ebp, [rsp+98h+var_48]\nmov r12d, r14d\nmov r14d, [rsp+98h+var_44]\nmov r15d, [rsp+98h+var_40]\nmov r9d, [rsp+98h+var_50]\nmov eax, ebp\nsub ebp, 1\nmov r13d, [rsp+98h+var_4C]\nmov r8d, [rsp+98h+var_3C]\nsub eax, r14d\nlea r15d, [r15+r12+1]\nmov r14d, eax\nor eax, ebp\njnz loc_14A6\nloc_15D9:\nmov r12d, [rsp+98h+var_54]\nmov ebx, [rsp+98h+var_58]\nlea r13d, [r13+r15+1]\nmov eax, r12d\nsub r12d, 1\nsub eax, ebx\nmov ebx, eax\nor eax, r12d\njnz loc_14CF\nloc_15FB:\nmov edx, r13d\nmov r13d, [rsp+98h+var_5C]\nmov r15d, [rsp+98h+var_64]\nmov esi, r9d\nmov ebx, [rsp+98h+var_60]\nmov eax, r8d\nlea r13d, [r13+rdx+1]\njmp loc_14F1\nloc_161C:\nadd ebp, 1\nmov eax, 0FFFFFFFFh\nmov r14d, 0FFFFFFFFh\nmov r13d, 0FFFFFFFEh\njmp loc_132D\nloc_1638:\nmov eax, ebp\nmov ebp, r12d\nmov r12d, [rsp+98h+var_6C]\nmov ecx, eax\nsub eax, 1\nsub ecx, ebp\nlea r12d, [r13+r12+1]\nmov ebp, ecx\nor ecx, eax\njnz loc_13E0\nloc_1658:\nmov esi, [rsp+98h+var_8C]\nmov edx, [rsp+98h+var_88]\nlea r15d, [r15+r12+1]\nmov ecx, [rsp+98h+var_84]\nmov r14d, [rsp+98h+var_80]\nmov eax, [rsp+98h+var_7C]\nmov edi, [rsp+98h+var_78]\nmov ebp, [rsp+98h+var_74]\nmov r13d, [rsp+98h+var_70]\njmp loc_1409\nloc_1684:\nadd r14d, 1\nmov r13d, 0FFFFFFFFh\nmov ebp, 0FFFFFFFFh\nmov ebx, 0FFFFFFFEh\njmp loc_1301\nloc_169D:\nadd r15d, 1\nmov r13d, 0FFFFFFFFh\nmov ebp, 0FFFFFFFFh\nmov r12d, 0FFFFFFFEh\njmp loc_134D\nloc_16B7:\nadd r15d, 1\nmov r14d, 0FFFFFFFFh\nmov ebp, 0FFFFFFFFh\nmov ebx, 0FFFFFFFEh\njmp loc_12C5\nloc_16D0:\nadd r13d, 1\nmov ebx, 0FFFFFFFFh\nmov r12d, 0FFFFFFFFh\nmov r14d, 0FFFFFFFEh\njmp loc_12A0\nloc_16EA:\nadd r13d, 1\nmov r15d, 0FFFFFFFFh\nmov ebx, 0FFFFFFFFh\nmov ebp, 0FFFFFFFEh\njmp loc_1267\nloc_1703:\nmov ebp, [rsp+98h+var_68]\nmov ebx, eax\nlea r14d, [rsi+r13+1]\nmov eax, ebx\nsub ebx, 1\nsub eax, ebp\nmov ebp, eax\nor eax, ebx\njnz loc_152C\nloc_171F:\nlea ebp, [r14+1]\njmp loc_1537\nloc_1728:\nadd r14d, 1\nmov ebp, 0FFFFFFFFh\nmov ebx, 0FFFFFFFFh\nmov r15d, 0FFFFFFFEh\njmp loc_1243\nloc_1741:\nmov ebp, 1\njmp loc_1537", + "ida_pseudo": "__int64 __fastcall func0(int a1, unsigned int a2)\n{\n unsigned int v2; // ebp\n unsigned int v3; // r14d\n int v4; // ebx\n int v5; // r15d\n unsigned int v6; // esi\n int v7; // r13d\n int v8; // eax\n int v9; // ebp\n unsigned int v10; // r9d\n int v11; // r12d\n int v12; // ebx\n int v13; // r8d\n int v14; // r13d\n int v15; // r14d\n int v16; // r15d\n int v17; // ebp\n int v18; // ebx\n int v19; // r13d\n int v20; // r14d\n int v21; // ebx\n int v22; // edx\n int v23; // ecx\n int v24; // esi\n int v25; // r14d\n int v26; // eax\n int v27; // ebp\n int v28; // r13d\n int v29; // edi\n int v30; // r15d\n int v31; // ebp\n int v32; // r12d\n int v33; // eax\n int v34; // ebp\n int v35; // r12d\n int v36; // ebx\n unsigned int v37; // r14d\n int v38; // r12d\n int v39; // r13d\n int v40; // ebp\n int v41; // eax\n unsigned int v42; // edi\n int v43; // ecx\n int v44; // ebx\n int v45; // edi\n int v46; // r15d\n int v47; // eax\n int v48; // r12d\n int v49; // eax\n int v50; // eax\n int v51; // ecx\n int v52; // eax\n int v54; // edi\n int v55; // r15d\n int v56; // eax\n int v57; // ebp\n int v58; // ecx\n int v59; // [rsp+10h] [rbp-88h]\n int v60; // [rsp+14h] [rbp-84h]\n int v61; // [rsp+18h] [rbp-80h]\n int v62; // [rsp+1Ch] [rbp-7Ch]\n int v63; // [rsp+20h] [rbp-78h]\n int v64; // [rsp+24h] [rbp-74h]\n int v65; // [rsp+28h] [rbp-70h]\n int v66; // [rsp+2Ch] [rbp-6Ch]\n unsigned int v67; // [rsp+30h] [rbp-68h]\n int v68; // [rsp+34h] [rbp-64h]\n int v69; // [rsp+38h] [rbp-60h]\n int v70; // [rsp+3Ch] [rbp-5Ch]\n int v71; // [rsp+40h] [rbp-58h]\n int v72; // [rsp+44h] [rbp-54h]\n unsigned int v73; // [rsp+48h] [rbp-50h]\n int v74; // [rsp+4Ch] [rbp-4Ch]\n int v75; // [rsp+50h] [rbp-48h]\n int v76; // [rsp+54h] [rbp-44h]\n int v77; // [rsp+58h] [rbp-40h]\n int v78; // [rsp+5Ch] [rbp-3Ch]\n\n if ( !(a2 | a1) )\n return 1;\n v2 = a2;\n if ( a2 )\n {\n v3 = 0;\n v4 = a1;\n while ( 1 )\n {\n v5 = v2 - 1;\n if ( v4 | (v2 - 1) )\n {\n if ( v2 == 1 )\n goto LABEL_52;\n }\n else\n {\n ++v3;\n v2 = -1;\n v4 = -1;\n v5 = -2;\n }\n v67 = v2;\n v6 = v3;\n v7 = 0;\n v8 = v4;\n do\n {\n v9 = v5 - 1;\n if ( v4 | (v5 - 1) )\n {\n if ( v5 == 1 )\n goto LABEL_49;\n }\n else\n {\n ++v7;\n v5 = -1;\n v4 = -1;\n v9 = -2;\n }\n v68 = v5;\n v10 = v6;\n v69 = v4;\n v11 = v4;\n v12 = v9;\n v13 = v8;\n v70 = v7;\n v14 = 0;\n while ( 2 )\n {\n v15 = v12 - 1;\n if ( v11 | (v12 - 1) )\n {\n if ( v12 == 1 )\n goto LABEL_46;\n }\n else\n {\n ++v14;\n v12 = -1;\n v11 = -1;\n v15 = -2;\n }\n v71 = v12;\n v16 = 0;\n v17 = v11;\n v72 = v11;\n do\n {\n v18 = v15 - 1;\n if ( v17 | (v15 - 1) )\n {\n if ( v15 == 1 )\n goto LABEL_43;\n }\n else\n {\n ++v16;\n v15 = -1;\n v17 = -1;\n v18 = -2;\n }\n v73 = v10;\n v75 = v17;\n v77 = v16;\n v78 = v13;\n v74 = v14;\n v19 = v18;\n v76 = v15;\n v20 = 0;\n do\n {\n v21 = v19 - 1;\n if ( v17 | (v19 - 1) )\n {\n if ( v19 == 1 )\n goto LABEL_40;\n }\n else\n {\n ++v20;\n v19 = -1;\n v17 = -1;\n v21 = -2;\n }\n v22 = v17;\n v23 = v20;\n v24 = v19;\n v25 = v17;\n v26 = v21;\n v27 = 0;\n do\n {\n v28 = v26 - 1;\n if ( v25 | (v26 - 1) )\n {\n if ( v26 == 1 )\n goto LABEL_37;\n }\n else\n {\n ++v27;\n v26 = -1;\n v25 = -1;\n v28 = -2;\n }\n v29 = v27;\n v30 = 0;\n v31 = v25;\n do\n {\n v32 = v28 - 1;\n if ( v31 | (v28 - 1) )\n {\n if ( v28 == 1 )\n goto LABEL_34;\n }\n else\n {\n ++v30;\n v28 = -1;\n v31 = -1;\n v32 = -2;\n }\n v59 = v22;\n v60 = v23;\n v61 = v25;\n v63 = v29;\n v65 = v28;\n v62 = v26;\n v33 = v31;\n v64 = v31;\n v34 = v32;\n v35 = 0;\n while ( 1 )\n {\n v36 = v34 - 1;\n if ( !(v33 | (v34 - 1)) )\n break;\n if ( v34 != 1 )\n goto LABEL_27;\nLABEL_31:\n v43 = v33--;\n v34 = v43 - v34;\n if ( !(v33 | v34) )\n goto LABEL_64;\nLABEL_32:\n if ( !v34 )\n {\n v22 = v59;\n v30 += v35;\n v23 = v60;\n v25 = v61;\n v26 = v62;\n v29 = v63;\n v31 = v64;\n v28 = v65;\n goto LABEL_34;\n }\n }\n ++v35;\n v34 = -1;\n v33 = -1;\n v36 = -2;\nLABEL_27:\n v66 = v35;\n v37 = v33;\n v38 = v34;\n v39 = 0;\n v40 = v33;\n while ( 1 )\n {\n v41 = func0(v37, (unsigned int)(v36 - 1));\n v42 = v37--;\n v39 += v41;\n v36 = v42 - v36;\n if ( !(v37 | v36) )\n break;\n if ( !v36 )\n {\n v33 = v40;\n v34 = v38;\n v35 = v39 + v66;\n goto LABEL_31;\n }\n }\n v56 = v40;\n v57 = v38;\n v58 = v56;\n v33 = v56 - 1;\n v35 = v39 + v66 + 1;\n v34 = v58 - v57;\n if ( v33 | v34 )\n goto LABEL_32;\nLABEL_64:\n v22 = v59;\n v30 += v35 + 1;\n v23 = v60;\n v25 = v61;\n v26 = v62;\n v29 = v63;\n v31 = v64;\n v28 = v65;\nLABEL_34:\n v44 = v31--;\n v28 = v44 - v28;\n if ( !(v31 | v28) )\n {\n v27 = v29 + v30 + 1;\n v54 = v25--;\n v26 = v54 - v26;\n if ( v25 | v26 )\n goto LABEL_38;\n goto LABEL_58;\n }\n }\n while ( v28 );\n v27 = v30 + v29;\nLABEL_37:\n v45 = v25--;\n v26 = v45 - v26;\n if ( !(v25 | v26) )\n {\nLABEL_58:\n v55 = v27;\n v17 = v22 - 1;\n v20 = v23 + v55 + 1;\n v19 = v22 - v24;\n if ( (v22 - 1) | (v22 - v24) )\n goto LABEL_41;\n goto LABEL_59;\n }\nLABEL_38:\n ;\n }\n while ( v26 );\n v46 = v27;\n v19 = v24;\n v17 = v22;\n v20 = v46 + v23;\nLABEL_40:\n v47 = v17--;\n v19 = v47 - v19;\n if ( !(v17 | v19) )\n {\nLABEL_59:\n v10 = v73;\n v17 = v75 - 1;\n v14 = v74;\n v13 = v78;\n v16 = v77 + v20 + 1;\n v15 = v75 - v76;\n if ( (v75 - 1) | (v75 - v76) )\n goto LABEL_44;\nLABEL_60:\n v14 += v16 + 1;\n v11 = v72 - 1;\n v12 = v72 - v71;\n if ( (v72 - 1) | (v72 - v71) )\n goto LABEL_47;\n goto LABEL_61;\n }\nLABEL_41:\n ;\n }\n while ( v19 );\n v48 = v20;\n v10 = v73;\n v14 = v74;\n v17 = v75;\n v15 = v76;\n v13 = v78;\n v16 = v48 + v77;\nLABEL_43:\n v49 = v17--;\n v15 = v49 - v15;\n if ( !(v17 | v15) )\n goto LABEL_60;\nLABEL_44:\n ;\n }\n while ( v15 );\n v12 = v71;\n v11 = v72;\n v14 += v16;\nLABEL_46:\n v50 = v11--;\n v12 = v50 - v12;\n if ( v11 | v12 )\n {\nLABEL_47:\n if ( !v12 )\n {\n v5 = v68;\n v6 = v10;\n v4 = v69;\n v8 = v13;\n v7 = v14 + v70;\n goto LABEL_49;\n }\n continue;\n }\n break;\n }\nLABEL_61:\n v5 = v68;\n v6 = v10;\n v4 = v69;\n v8 = v13;\n v7 = v70 + v14 + 1;\nLABEL_49:\n v51 = v4--;\n v5 = v51 - v5;\n if ( !(v4 | v5) )\n {\n v3 = v6 + v7 + 1;\n v4 = v8 - 1;\n v2 = v8 - v67;\n if ( (v8 - 1) | (v8 - v67) )\n goto LABEL_53;\n return v3 + 1;\n }\n }\n while ( v5 );\n v2 = v67;\n v4 = v8;\n v3 = v7 + v6;\nLABEL_52:\n v52 = v4--;\n v2 = v52 - v2;\n if ( !(v4 | v2) )\n return v3 + 1;\nLABEL_53:\n if ( !v2 )\n return v3;\n }\n }\n return v2;\n}", + "ida_strip_asm": "sub_1200:\nendbr64\npush r15\nmov eax, edi\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 68h\nor eax, esi\njz loc_1741\nmov ebp, esi\ntest esi, esi\njz loc_1537\nxor r14d, r14d\nmov ebx, edi\nloc_122B:\nlea r15d, [rbp-1]\nmov eax, r15d\nor eax, ebx\njz loc_1728\ntest r15d, r15d\njz loc_151B\nloc_1243:\nmov [rsp+98h+var_68], ebp\nxor eax, eax\nmov esi, r14d\nmov r13d, eax\nmov eax, ebx\nloc_1251:\nlea ebp, [r15-1]\nmov ecx, ebp\nor ecx, ebx\njz loc_16EA\ntest ebp, ebp\njz loc_14F1\nloc_1267:\nmov [rsp+98h+var_64], r15d\nmov ecx, ebx\nxor edx, edx\nmov r9d, esi\nmov [rsp+98h+var_60], ebx\nmov r12d, ecx\nmov ebx, ebp\nmov r8d, eax\nmov [rsp+98h+var_5C], r13d\nmov r13d, edx\nloc_1287:\nlea r14d, [rbx-1]\nmov eax, r14d\nor eax, r12d\njz loc_16D0\ntest r14d, r14d\njz loc_14BB\nloc_12A0:\nmov [rsp+98h+var_58], ebx\nxor r15d, r15d\nmov ebp, r12d\nmov [rsp+98h+var_54], r12d\nloc_12AF:\nlea ebx, [r14-1]\nmov eax, ebx\nor eax, ebp\njz loc_16B7\ntest ebx, ebx\njz loc_1493\nloc_12C5:\nmov [rsp+98h+var_50], r9d\nxor r12d, r12d\nmov [rsp+98h+var_48], ebp\nmov [rsp+98h+var_40], r15d\nmov [rsp+98h+var_3C], r8d\nmov [rsp+98h+var_4C], r13d\nmov r13d, ebx\nmov [rsp+98h+var_44], r14d\nmov r14d, r12d\nloc_12EB:\nlea ebx, [r13-1]\nmov eax, ebx\nor eax, ebp\njz loc_1684\ntest ebx, ebx\njz loc_1454\nloc_1301:\nxor r15d, r15d\nmov edx, ebp\nmov ecx, r14d\nmov esi, r13d\nmov r14d, ebp\nmov eax, ebx\nmov ebp, r15d\nloc_1314:\nlea r13d, [rax-1]\nmov edi, r13d\nor edi, r14d\njz loc_161C\ntest r13d, r13d\njz loc_142A\nloc_132D:\nmov edi, ebp\nxor r15d, r15d\nmov ebp, r14d\nloc_1335:\nlea r12d, [r13-1]\nmov ebx, r12d\nor ebx, ebp\njz loc_169D\ntest r12d, r12d\njz loc_1409\nloc_134D:\nmov [rsp+98h+var_8C], esi\nxor ebx, ebx\nmov [rsp+98h+var_88], edx\nmov [rsp+98h+var_84], ecx\nmov [rsp+98h+var_80], r14d\nmov [rsp+98h+var_78], edi\nmov [rsp+98h+var_70], r13d\nmov [rsp+98h+var_7C], eax\nmov eax, ebp\nmov [rsp+98h+var_74], ebp\nmov ebp, r12d\nmov r12d, ebx\nloc_1379:\nlea ebx, [rbp-1]\nmov edx, ebx\nor edx, eax\njz loc_1550\ntest ebx, ebx\njz short loc_13CF\nloc_138A:\nmov [rsp+98h+var_6C], r12d\nmov r14d, eax\nmov r12d, ebp\nxor r13d, r13d\nmov ebp, eax\nloc_139A:\nmov edi, r14d\nlea esi, [rbx-1]\ncall sub_1200\nmov edi, r14d\nsub r14d, 1\nsub edi, ebx\nadd r13d, eax\nmov eax, edi\nmov ebx, edi\nor eax, r14d\njz loc_1638\ntest ebx, ebx\njnz short loc_139A\nmov eax, ebp\nmov ebp, r12d\nmov r12d, [rsp+98h+var_6C]\nadd r12d, r13d\nloc_13CF:\nmov ecx, eax\nsub eax, 1\nsub ecx, ebp\nmov ebp, ecx\nor ecx, eax\njz loc_1658\nloc_13E0:\ntest ebp, ebp\njnz short loc_1379\nmov esi, [rsp+98h+var_8C]\nmov edx, [rsp+98h+var_88]\nadd r15d, r12d\nmov ecx, [rsp+98h+var_84]\nmov r14d, [rsp+98h+var_80]\nmov eax, [rsp+98h+var_7C]\nmov edi, [rsp+98h+var_78]\nmov ebp, [rsp+98h+var_74]\nmov r13d, [rsp+98h+var_70]\nloc_1409:\nmov ebx, ebp\nsub ebp, 1\nsub ebx, r13d\nmov r13d, ebx\nor ebx, ebp\njz loc_1568\ntest r13d, r13d\njnz loc_1335\nmov ebp, edi\nadd ebp, r15d\nloc_142A:\nmov edi, r14d\nsub r14d, 1\nsub edi, eax\nmov eax, edi\nor edi, r14d\njz loc_1581\nloc_143E:\ntest eax, eax\njnz loc_1314\nmov r15d, ebp\nmov r14d, ecx\nmov r13d, esi\nmov ebp, edx\nadd r14d, r15d\nloc_1454:\nmov eax, ebp\nsub ebp, 1\nsub eax, r13d\nmov r13d, eax\nor eax, ebp\njz loc_15A1\nloc_1467:\ntest r13d, r13d\njnz loc_12EB\nmov r15d, [rsp+98h+var_40]\nmov r12d, r14d\nmov r9d, [rsp+98h+var_50]\nmov r13d, [rsp+98h+var_4C]\nmov ebp, [rsp+98h+var_48]\nmov r14d, [rsp+98h+var_44]\nmov r8d, [rsp+98h+var_3C]\nadd r15d, r12d\nloc_1493:\nmov eax, ebp\nsub ebp, 1\nsub eax, r14d\nmov r14d, eax\nor eax, ebp\njz loc_15D9\nloc_14A6:\ntest r14d, r14d\njnz loc_12AF\nmov ebx, [rsp+98h+var_58]\nmov r12d, [rsp+98h+var_54]\nadd r13d, r15d\nloc_14BB:\nmov eax, r12d\nsub r12d, 1\nsub eax, ebx\nmov ebx, eax\nor eax, r12d\njz loc_15FB\nloc_14CF:\ntest ebx, ebx\njnz loc_1287\nmov edx, r13d\nmov r13d, [rsp+98h+var_5C]\nmov r15d, [rsp+98h+var_64]\nmov esi, r9d\nmov ebx, [rsp+98h+var_60]\nmov eax, r8d\nadd r13d, edx\nloc_14F1:\nmov ecx, ebx\nsub ebx, 1\nsub ecx, r15d\nmov edx, ecx\nmov r15d, ecx\nor edx, ebx\njz loc_1703\ntest r15d, r15d\njnz loc_1251\nmov r14d, esi\nmov ebp, [rsp+98h+var_68]\nmov ebx, eax\nadd r14d, r13d\nloc_151B:\nmov eax, ebx\nsub ebx, 1\nsub eax, ebp\nmov ebp, eax\nor eax, ebx\njz loc_171F\nloc_152C:\ntest ebp, ebp\njnz loc_122B\nmov ebp, r14d\nloc_1537:\nadd rsp, 68h\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1550:\nadd r12d, 1\nmov ebp, 0FFFFFFFFh\nmov eax, 0FFFFFFFFh\nmov ebx, 0FFFFFFFEh\njmp loc_138A\nloc_1568:\nlea ebp, [rdi+r15+1]\nmov edi, r14d\nsub r14d, 1\nsub edi, eax\nmov eax, edi\nor edi, r14d\njnz loc_143E\nloc_1581:\nmov r15d, ebp\nmov ebp, edx\nmov r13d, esi\nmov eax, ebp\nsub ebp, 1\nlea r14d, [rcx+r15+1]\nsub eax, r13d\nmov r13d, eax\nor eax, ebp\njnz loc_1467\nloc_15A1:\nmov ebp, [rsp+98h+var_48]\nmov r12d, r14d\nmov r14d, [rsp+98h+var_44]\nmov r15d, [rsp+98h+var_40]\nmov r9d, [rsp+98h+var_50]\nmov eax, ebp\nsub ebp, 1\nmov r13d, [rsp+98h+var_4C]\nmov r8d, [rsp+98h+var_3C]\nsub eax, r14d\nlea r15d, [r15+r12+1]\nmov r14d, eax\nor eax, ebp\njnz loc_14A6\nloc_15D9:\nmov r12d, [rsp+98h+var_54]\nmov ebx, [rsp+98h+var_58]\nlea r13d, [r13+r15+1]\nmov eax, r12d\nsub r12d, 1\nsub eax, ebx\nmov ebx, eax\nor eax, r12d\njnz loc_14CF\nloc_15FB:\nmov edx, r13d\nmov r13d, [rsp+98h+var_5C]\nmov r15d, [rsp+98h+var_64]\nmov esi, r9d\nmov ebx, [rsp+98h+var_60]\nmov eax, r8d\nlea r13d, [r13+rdx+1]\njmp loc_14F1\nloc_161C:\nadd ebp, 1\nmov eax, 0FFFFFFFFh\nmov r14d, 0FFFFFFFFh\nmov r13d, 0FFFFFFFEh\njmp loc_132D\nloc_1638:\nmov eax, ebp\nmov ebp, r12d\nmov r12d, [rsp+98h+var_6C]\nmov ecx, eax\nsub eax, 1\nsub ecx, ebp\nlea r12d, [r13+r12+1]\nmov ebp, ecx\nor ecx, eax\njnz loc_13E0\nloc_1658:\nmov esi, [rsp+98h+var_8C]\nmov edx, [rsp+98h+var_88]\nlea r15d, [r15+r12+1]\nmov ecx, [rsp+98h+var_84]\nmov r14d, [rsp+98h+var_80]\nmov eax, [rsp+98h+var_7C]\nmov edi, [rsp+98h+var_78]\nmov ebp, [rsp+98h+var_74]\nmov r13d, [rsp+98h+var_70]\njmp loc_1409\nloc_1684:\nadd r14d, 1\nmov r13d, 0FFFFFFFFh\nmov ebp, 0FFFFFFFFh\nmov ebx, 0FFFFFFFEh\njmp loc_1301\nloc_169D:\nadd r15d, 1\nmov r13d, 0FFFFFFFFh\nmov ebp, 0FFFFFFFFh\nmov r12d, 0FFFFFFFEh\njmp loc_134D\nloc_16B7:\nadd r15d, 1\nmov r14d, 0FFFFFFFFh\nmov ebp, 0FFFFFFFFh\nmov ebx, 0FFFFFFFEh\njmp loc_12C5\nloc_16D0:\nadd r13d, 1\nmov ebx, 0FFFFFFFFh\nmov r12d, 0FFFFFFFFh\nmov r14d, 0FFFFFFFEh\njmp loc_12A0\nloc_16EA:\nadd r13d, 1\nmov r15d, 0FFFFFFFFh\nmov ebx, 0FFFFFFFFh\nmov ebp, 0FFFFFFFEh\njmp loc_1267\nloc_1703:\nmov ebp, [rsp+98h+var_68]\nmov ebx, eax\nlea r14d, [rsi+r13+1]\nmov eax, ebx\nsub ebx, 1\nsub eax, ebp\nmov ebp, eax\nor eax, ebx\njnz loc_152C\nloc_171F:\nlea ebp, [r14+1]\njmp loc_1537\nloc_1728:\nadd r14d, 1\nmov ebp, 0FFFFFFFFh\nmov ebx, 0FFFFFFFFh\nmov r15d, 0FFFFFFFEh\njmp loc_1243\nloc_1741:\nmov ebp, 1\njmp loc_1537", + "ida_strip_pseudo": "__int64 __fastcall sub_1200(int a1, unsigned int a2)\n{\n unsigned int v2; // ebp\n unsigned int v3; // r14d\n int v4; // ebx\n int v5; // r15d\n unsigned int v6; // esi\n int v7; // r13d\n int v8; // eax\n int v9; // ebp\n unsigned int v10; // r9d\n int v11; // r12d\n int v12; // ebx\n int v13; // r8d\n int v14; // r13d\n int v15; // r14d\n int v16; // r15d\n int v17; // ebp\n int v18; // ebx\n int v19; // r13d\n int v20; // r14d\n int v21; // ebx\n int v22; // edx\n int v23; // ecx\n int v24; // esi\n int v25; // r14d\n int v26; // eax\n int v27; // ebp\n int v28; // r13d\n int v29; // edi\n int v30; // r15d\n int v31; // ebp\n int v32; // r12d\n int v33; // eax\n int v34; // ebp\n int v35; // r12d\n int v36; // ebx\n unsigned int v37; // r14d\n int v38; // r12d\n int v39; // r13d\n int v40; // ebp\n int v41; // eax\n unsigned int v42; // edi\n int v43; // ecx\n int v44; // ebx\n int v45; // edi\n int v46; // r15d\n int v47; // eax\n int v48; // r12d\n int v49; // eax\n int v50; // eax\n int v51; // ecx\n int v52; // eax\n int v54; // edi\n int v55; // r15d\n int v56; // eax\n int v57; // ebp\n int v58; // ecx\n int v59; // [rsp+10h] [rbp-88h]\n int v60; // [rsp+14h] [rbp-84h]\n int v61; // [rsp+18h] [rbp-80h]\n int v62; // [rsp+1Ch] [rbp-7Ch]\n int v63; // [rsp+20h] [rbp-78h]\n int v64; // [rsp+24h] [rbp-74h]\n int v65; // [rsp+28h] [rbp-70h]\n int v66; // [rsp+2Ch] [rbp-6Ch]\n unsigned int v67; // [rsp+30h] [rbp-68h]\n int v68; // [rsp+34h] [rbp-64h]\n int v69; // [rsp+38h] [rbp-60h]\n int v70; // [rsp+3Ch] [rbp-5Ch]\n int v71; // [rsp+40h] [rbp-58h]\n int v72; // [rsp+44h] [rbp-54h]\n unsigned int v73; // [rsp+48h] [rbp-50h]\n int v74; // [rsp+4Ch] [rbp-4Ch]\n int v75; // [rsp+50h] [rbp-48h]\n int v76; // [rsp+54h] [rbp-44h]\n int v77; // [rsp+58h] [rbp-40h]\n int v78; // [rsp+5Ch] [rbp-3Ch]\n\n if ( !(a2 | a1) )\n return 1;\n v2 = a2;\n if ( a2 )\n {\n v3 = 0;\n v4 = a1;\n while ( 1 )\n {\n v5 = v2 - 1;\n if ( v4 | (v2 - 1) )\n {\n if ( v2 == 1 )\n goto LABEL_52;\n }\n else\n {\n ++v3;\n v2 = -1;\n v4 = -1;\n v5 = -2;\n }\n v67 = v2;\n v6 = v3;\n v7 = 0;\n v8 = v4;\n do\n {\n v9 = v5 - 1;\n if ( v4 | (v5 - 1) )\n {\n if ( v5 == 1 )\n goto LABEL_49;\n }\n else\n {\n ++v7;\n v5 = -1;\n v4 = -1;\n v9 = -2;\n }\n v68 = v5;\n v10 = v6;\n v69 = v4;\n v11 = v4;\n v12 = v9;\n v13 = v8;\n v70 = v7;\n v14 = 0;\n while ( 2 )\n {\n v15 = v12 - 1;\n if ( v11 | (v12 - 1) )\n {\n if ( v12 == 1 )\n goto LABEL_46;\n }\n else\n {\n ++v14;\n v12 = -1;\n v11 = -1;\n v15 = -2;\n }\n v71 = v12;\n v16 = 0;\n v17 = v11;\n v72 = v11;\n do\n {\n v18 = v15 - 1;\n if ( v17 | (v15 - 1) )\n {\n if ( v15 == 1 )\n goto LABEL_43;\n }\n else\n {\n ++v16;\n v15 = -1;\n v17 = -1;\n v18 = -2;\n }\n v73 = v10;\n v75 = v17;\n v77 = v16;\n v78 = v13;\n v74 = v14;\n v19 = v18;\n v76 = v15;\n v20 = 0;\n do\n {\n v21 = v19 - 1;\n if ( v17 | (v19 - 1) )\n {\n if ( v19 == 1 )\n goto LABEL_40;\n }\n else\n {\n ++v20;\n v19 = -1;\n v17 = -1;\n v21 = -2;\n }\n v22 = v17;\n v23 = v20;\n v24 = v19;\n v25 = v17;\n v26 = v21;\n v27 = 0;\n do\n {\n v28 = v26 - 1;\n if ( v25 | (v26 - 1) )\n {\n if ( v26 == 1 )\n goto LABEL_37;\n }\n else\n {\n ++v27;\n v26 = -1;\n v25 = -1;\n v28 = -2;\n }\n v29 = v27;\n v30 = 0;\n v31 = v25;\n do\n {\n v32 = v28 - 1;\n if ( v31 | (v28 - 1) )\n {\n if ( v28 == 1 )\n goto LABEL_34;\n }\n else\n {\n ++v30;\n v28 = -1;\n v31 = -1;\n v32 = -2;\n }\n v59 = v22;\n v60 = v23;\n v61 = v25;\n v63 = v29;\n v65 = v28;\n v62 = v26;\n v33 = v31;\n v64 = v31;\n v34 = v32;\n v35 = 0;\n while ( 1 )\n {\n v36 = v34 - 1;\n if ( !(v33 | (v34 - 1)) )\n break;\n if ( v34 != 1 )\n goto LABEL_27;\nLABEL_31:\n v43 = v33--;\n v34 = v43 - v34;\n if ( !(v33 | v34) )\n goto LABEL_64;\nLABEL_32:\n if ( !v34 )\n {\n v22 = v59;\n v30 += v35;\n v23 = v60;\n v25 = v61;\n v26 = v62;\n v29 = v63;\n v31 = v64;\n v28 = v65;\n goto LABEL_34;\n }\n }\n ++v35;\n v34 = -1;\n v33 = -1;\n v36 = -2;\nLABEL_27:\n v66 = v35;\n v37 = v33;\n v38 = v34;\n v39 = 0;\n v40 = v33;\n while ( 1 )\n {\n v41 = sub_1200(v37, (unsigned int)(v36 - 1));\n v42 = v37--;\n v39 += v41;\n v36 = v42 - v36;\n if ( !(v37 | v36) )\n break;\n if ( !v36 )\n {\n v33 = v40;\n v34 = v38;\n v35 = v39 + v66;\n goto LABEL_31;\n }\n }\n v56 = v40;\n v57 = v38;\n v58 = v56;\n v33 = v56 - 1;\n v35 = v39 + v66 + 1;\n v34 = v58 - v57;\n if ( v33 | v34 )\n goto LABEL_32;\nLABEL_64:\n v22 = v59;\n v30 += v35 + 1;\n v23 = v60;\n v25 = v61;\n v26 = v62;\n v29 = v63;\n v31 = v64;\n v28 = v65;\nLABEL_34:\n v44 = v31--;\n v28 = v44 - v28;\n if ( !(v31 | v28) )\n {\n v27 = v29 + v30 + 1;\n v54 = v25--;\n v26 = v54 - v26;\n if ( v25 | v26 )\n goto LABEL_38;\n goto LABEL_58;\n }\n }\n while ( v28 );\n v27 = v30 + v29;\nLABEL_37:\n v45 = v25--;\n v26 = v45 - v26;\n if ( !(v25 | v26) )\n {\nLABEL_58:\n v55 = v27;\n v17 = v22 - 1;\n v20 = v23 + v55 + 1;\n v19 = v22 - v24;\n if ( (v22 - 1) | (v22 - v24) )\n goto LABEL_41;\n goto LABEL_59;\n }\nLABEL_38:\n ;\n }\n while ( v26 );\n v46 = v27;\n v19 = v24;\n v17 = v22;\n v20 = v46 + v23;\nLABEL_40:\n v47 = v17--;\n v19 = v47 - v19;\n if ( !(v17 | v19) )\n {\nLABEL_59:\n v10 = v73;\n v17 = v75 - 1;\n v14 = v74;\n v13 = v78;\n v16 = v77 + v20 + 1;\n v15 = v75 - v76;\n if ( (v75 - 1) | (v75 - v76) )\n goto LABEL_44;\nLABEL_60:\n v14 += v16 + 1;\n v11 = v72 - 1;\n v12 = v72 - v71;\n if ( (v72 - 1) | (v72 - v71) )\n goto LABEL_47;\n goto LABEL_61;\n }\nLABEL_41:\n ;\n }\n while ( v19 );\n v48 = v20;\n v10 = v73;\n v14 = v74;\n v17 = v75;\n v15 = v76;\n v13 = v78;\n v16 = v48 + v77;\nLABEL_43:\n v49 = v17--;\n v15 = v49 - v15;\n if ( !(v17 | v15) )\n goto LABEL_60;\nLABEL_44:\n ;\n }\n while ( v15 );\n v12 = v71;\n v11 = v72;\n v14 += v16;\nLABEL_46:\n v50 = v11--;\n v12 = v50 - v12;\n if ( v11 | v12 )\n {\nLABEL_47:\n if ( !v12 )\n {\n v5 = v68;\n v6 = v10;\n v4 = v69;\n v8 = v13;\n v7 = v14 + v70;\n goto LABEL_49;\n }\n continue;\n }\n break;\n }\nLABEL_61:\n v5 = v68;\n v6 = v10;\n v4 = v69;\n v8 = v13;\n v7 = v70 + v14 + 1;\nLABEL_49:\n v51 = v4--;\n v5 = v51 - v5;\n if ( !(v4 | v5) )\n {\n v3 = v6 + v7 + 1;\n v4 = v8 - 1;\n v2 = v8 - v67;\n if ( (v8 - 1) | (v8 - v67) )\n goto LABEL_53;\n return v3 + 1;\n }\n }\n while ( v5 );\n v2 = v67;\n v4 = v8;\n v3 = v7 + v6;\nLABEL_52:\n v52 = v4--;\n v2 = v52 - v2;\n if ( !(v4 | v2) )\n return v3 + 1;\nLABEL_53:\n if ( !v2 )\n return v3;\n }\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1200(int a1, unsigned int a2) {\n unsigned int v2;\n unsigned int v3;\n int v4;\n int v5;\n unsigned int v6;\n int v7;\n int v8;\n int v9;\n unsigned int v10;\n int v11;\n int v12;\n int v13;\n int v14;\n int v15;\n int v16;\n int v17;\n int v18;\n int v19;\n int v20;\n int v21;\n int v22;\n int v23;\n int v24;\n int v25;\n int v26;\n int v27;\n int v28;\n int v29;\n int v30;\n int v31;\n int v32;\n int v33;\n int v34;\n int v35;\n int v36;\n unsigned int v37;\n int v38;\n int v39;\n int v40;\n int v41;\n unsigned int v42;\n int v43;\n int v44;\n int v45;\n int v46;\n int v47;\n int v48;\n int v49;\n int v50;\n int v51;\n int v52;\n int v54;\n int v55;\n int v56;\n int v57;\n int v58;\n int v59;\n int v60;\n int v61;\n int v62;\n int v63;\n int v64;\n int v65;\n int v66;\n unsigned int v67;\n int v68;\n int v69;\n int v70;\n int v71;\n int v72;\n unsigned int v73;\n int v74;\n int v75;\n int v76;\n int v77;\n int v78;\n if (!(a2 | a1)) return 1;\n v2 = a2;\n if (a2) {\n v3 = 0;\n v4 = a1;\n while (1) {\n v5 = v2 - 1;\n if (v4 | (v2 - 1)) {\n if (v2 == 1) goto LABEL_52;\n } else {\n ++v3;\n v2 = -1;\n v4 = -1;\n v5 = -2;\n }\n v67 = v2;\n v6 = v3;\n v7 = 0;\n v8 = v4;\n do {\n v9 = v5 - 1;\n if (v4 | (v5 - 1)) {\n if (v5 == 1) goto LABEL_49;\n } else {\n ++v7;\n v5 = -1;\n v4 = -1;\n v9 = -2;\n }\n v68 = v5;\n v10 = v6;\n v69 = v4;\n v11 = v4;\n v12 = v9;\n v13 = v8;\n v70 = v7;\n v14 = 0;\n while (2) {\n v15 = v12 - 1;\n if (v11 | (v12 - 1)) {\n if (v12 == 1) goto LABEL_46;\n } else {\n ++v14;\n v12 = -1;\n v11 = -1;\n v15 = -2;\n }\n v71 = v12;\n v16 = 0;\n v17 = v11;\n v72 = v11;\n do {\n v18 = v15 - 1;\n if (v17 | (v15 - 1)) {\n if (v15 == 1) goto LABEL_43;\n } else {\n ++v16;\n v15 = -1;\n v17 = -1;\n v18 = -2;\n }\n v73 = v10;\n v75 = v17;\n v77 = v16;\n v78 = v13;\n v74 = v14;\n v19 = v18;\n v76 = v15;\n v20 = 0;\n do {\n v21 = v19 - 1;\n if (v17 | (v19 - 1)) {\n if (v19 == 1) goto LABEL_40;\n } else {\n ++v20;\n v19 = -1;\n v17 = -1;\n v21 = -2;\n }\n v22 = v17;\n v23 = v20;\n v24 = v19;\n v25 = v17;\n v26 = v21;\n v27 = 0;\n do {\n v28 = v26 - 1;\n if (v25 | (v26 - 1)) {\n if (v26 == 1) goto LABEL_37;\n } else {\n ++v27;\n v26 = -1;\n v25 = -1;\n v28 = -2;\n }\n v29 = v27;\n v30 = 0;\n v31 = v25;\n do {\n v32 = v28 - 1;\n if (v31 | (v28 - 1)) {\n if (v28 == 1) goto LABEL_34;\n } else {\n ++v30;\n v28 = -1;\n v31 = -1;\n v32 = -2;\n }\n v59 = v22;\n v60 = v23;\n v61 = v25;\n v63 = v29;\n v65 = v28;\n v62 = v26;\n v33 = v31;\n v64 = v31;\n v34 = v32;\n v35 = 0;\n while (1) {\n v36 = v34 - 1;\n if (!(v33 | (v34 - 1))) break;\n if (v34 != 1) goto LABEL_27;\n LABEL_31:\n v43 = v33--;\n v34 = v43 - v34;\n if (!(v33 | v34)) goto LABEL_64;\n LABEL_32:\n if (!v34) {\n v22 = v59;\n v30 += v35;\n v23 = v60;\n v25 = v61;\n v26 = v62;\n v29 = v63;\n v31 = v64;\n v28 = v65;\n goto LABEL_34;\n }\n }\n ++v35;\n v34 = -1;\n v33 = -1;\n v36 = -2;\n LABEL_27:\n v66 = v35;\n v37 = v33;\n v38 = v34;\n v39 = 0;\n v40 = v33;\n while (1) {\n v41 = sub_1200(v37, (unsigned int)(v36 - 1));\n v42 = v37--;\n v39 += v41;\n v36 = v42 - v36;\n if (!(v37 | v36)) break;\n if (!v36) {\n v33 = v40;\n v34 = v38;\n v35 = v39 + v66;\n goto LABEL_31;\n }\n }\n v56 = v40;\n v57 = v38;\n v58 = v56;\n v33 = v56 - 1;\n v35 = v39 + v66 + 1;\n v34 = v58 - v57;\n if (v33 | v34) goto LABEL_32;\n LABEL_64:\n v22 = v59;\n v30 += v35 + 1;\n v23 = v60;\n v25 = v61;\n v26 = v62;\n v29 = v63;\n v31 = v64;\n v28 = v65;\n LABEL_34:\n v44 = v31--;\n v28 = v44 - v28;\n if (!(v31 | v28)) {\n v27 = v29 + v30 + 1;\n v54 = v25--;\n v26 = v54 - v26;\n if (v25 | v26) goto LABEL_38;\n goto LABEL_58;\n }\n } while (v28);\n v27 = v30 + v29;\n LABEL_37:\n v45 = v25--;\n v26 = v45 - v26;\n if (!(v25 | v26)) {\n LABEL_58:\n v55 = v27;\n v17 = v22 - 1;\n v20 = v23 + v55 + 1;\n v19 = v22 - v24;\n if ((v22 - 1) | (v22 - v24)) goto LABEL_41;\n goto LABEL_59;\n }\n LABEL_38:;\n } while (v26);\n v46 = v27;\n v19 = v24;\n v17 = v22;\n v20 = v46 + v23;\n LABEL_40:\n v47 = v17--;\n v19 = v47 - v19;\n if (!(v17 | v19)) {\n LABEL_59:\n v10 = v73;\n v17 = v75 - 1;\n v14 = v74;\n v13 = v78;\n v16 = v77 + v20 + 1;\n v15 = v75 - v76;\n if ((v75 - 1) | (v75 - v76)) goto LABEL_44;\n LABEL_60:\n v14 += v16 + 1;\n v11 = v72 - 1;\n v12 = v72 - v71;\n if ((v72 - 1) | (v72 - v71)) goto LABEL_47;\n goto LABEL_61;\n }\n LABEL_41:;\n } while (v19);\n v48 = v20;\n v10 = v73;\n v14 = v74;\n v17 = v75;\n v15 = v76;\n v13 = v78;\n v16 = v48 + v77;\n LABEL_43:\n v49 = v17--;\n v15 = v49 - v15;\n if (!(v17 | v15)) goto LABEL_60;\n LABEL_44:;\n } while (v15);\n v12 = v71;\n v11 = v72;\n v14 += v16;\n LABEL_46:\n v50 = v11--;\n v12 = v50 - v12;\n if (v11 | v12) {\n LABEL_47:\n if (!v12) {\n v5 = v68;\n v6 = v10;\n v4 = v69;\n v8 = v13;\n v7 = v14 + v70;\n goto LABEL_49;\n }\n continue;\n }\n break;\n }\n LABEL_61:\n v5 = v68;\n v6 = v10;\n v4 = v69;\n v8 = v13;\n v7 = v70 + v14 + 1;\n LABEL_49:\n v51 = v4--;\n v5 = v51 - v5;\n if (!(v4 | v5)) {\n v3 = v6 + v7 + 1;\n v4 = v8 - 1;\n v2 = v8 - v67;\n if ((v8 - 1) | (v8 - v67)) goto LABEL_53;\n return v3 + 1;\n }\n } while (v5);\n v2 = v67;\n v4 = v8;\n v3 = v7 + v6;\n LABEL_52:\n v52 = v4--;\n v2 = v52 - v2;\n if (!(v4 | v2)) return v3 + 1;\n LABEL_53:\n if (!v2) return v3;\n }\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1, unsigned int a2) {\n unsigned int v2;\n unsigned int v3;\n int v4;\n int v5;\n unsigned int v6;\n int v7;\n int v8;\n int v9;\n unsigned int v10;\n int v11;\n int v12;\n int v13;\n int v14;\n int v15;\n int v16;\n int v17;\n int v18;\n int v19;\n int v20;\n int v21;\n int v22;\n int v23;\n int v24;\n int v25;\n int v26;\n int v27;\n int v28;\n int v29;\n int v30;\n int v31;\n int v32;\n int v33;\n int v34;\n int v35;\n int v36;\n unsigned int v37;\n int v38;\n int v39;\n int v40;\n int v41;\n unsigned int v42;\n int v43;\n int v44;\n int v45;\n int v46;\n int v47;\n int v48;\n int v49;\n int v50;\n int v51;\n int v52;\n int v54;\n int v55;\n int v56;\n int v57;\n int v58;\n int v59;\n int v60;\n int v61;\n int v62;\n int v63;\n int v64;\n int v65;\n int v66;\n unsigned int v67;\n int v68;\n int v69;\n int v70;\n int v71;\n int v72;\n unsigned int v73;\n int v74;\n int v75;\n int v76;\n int v77;\n int v78;\n if (!(a2 | a1)) return 1;\n v2 = a2;\n if (a2) {\n v3 = 0;\n v4 = a1;\n while (1) {\n v5 = v2 - 1;\n if (v4 | (v2 - 1)) {\n if (v2 == 1) goto LABEL_52;\n } else {\n ++v3;\n v2 = -1;\n v4 = -1;\n v5 = -2;\n }\n v67 = v2;\n v6 = v3;\n v7 = 0;\n v8 = v4;\n do {\n v9 = v5 - 1;\n if (v4 | (v5 - 1)) {\n if (v5 == 1) goto LABEL_49;\n } else {\n ++v7;\n v5 = -1;\n v4 = -1;\n v9 = -2;\n }\n v68 = v5;\n v10 = v6;\n v69 = v4;\n v11 = v4;\n v12 = v9;\n v13 = v8;\n v70 = v7;\n v14 = 0;\n while (2) {\n v15 = v12 - 1;\n if (v11 | (v12 - 1)) {\n if (v12 == 1) goto LABEL_46;\n } else {\n ++v14;\n v12 = -1;\n v11 = -1;\n v15 = -2;\n }\n v71 = v12;\n v16 = 0;\n v17 = v11;\n v72 = v11;\n do {\n v18 = v15 - 1;\n if (v17 | (v15 - 1)) {\n if (v15 == 1) goto LABEL_43;\n } else {\n ++v16;\n v15 = -1;\n v17 = -1;\n v18 = -2;\n }\n v73 = v10;\n v75 = v17;\n v77 = v16;\n v78 = v13;\n v74 = v14;\n v19 = v18;\n v76 = v15;\n v20 = 0;\n do {\n v21 = v19 - 1;\n if (v17 | (v19 - 1)) {\n if (v19 == 1) goto LABEL_40;\n } else {\n ++v20;\n v19 = -1;\n v17 = -1;\n v21 = -2;\n }\n v22 = v17;\n v23 = v20;\n v24 = v19;\n v25 = v17;\n v26 = v21;\n v27 = 0;\n do {\n v28 = v26 - 1;\n if (v25 | (v26 - 1)) {\n if (v26 == 1) goto LABEL_37;\n } else {\n ++v27;\n v26 = -1;\n v25 = -1;\n v28 = -2;\n }\n v29 = v27;\n v30 = 0;\n v31 = v25;\n do {\n v32 = v28 - 1;\n if (v31 | (v28 - 1)) {\n if (v28 == 1) goto LABEL_34;\n } else {\n ++v30;\n v28 = -1;\n v31 = -1;\n v32 = -2;\n }\n v59 = v22;\n v60 = v23;\n v61 = v25;\n v63 = v29;\n v65 = v28;\n v62 = v26;\n v33 = v31;\n v64 = v31;\n v34 = v32;\n v35 = 0;\n while (1) {\n v36 = v34 - 1;\n if (!(v33 | (v34 - 1))) break;\n if (v34 != 1) goto LABEL_27;\n LABEL_31:\n v43 = v33--;\n v34 = v43 - v34;\n if (!(v33 | v34)) goto LABEL_64;\n LABEL_32:\n if (!v34) {\n v22 = v59;\n v30 += v35;\n v23 = v60;\n v25 = v61;\n v26 = v62;\n v29 = v63;\n v31 = v64;\n v28 = v65;\n goto LABEL_34;\n }\n }\n ++v35;\n v34 = -1;\n v33 = -1;\n v36 = -2;\n LABEL_27:\n v66 = v35;\n v37 = v33;\n v38 = v34;\n v39 = 0;\n v40 = v33;\n while (1) {\n v41 = func0(v37, (unsigned int)(v36 - 1));\n v42 = v37--;\n v39 += v41;\n v36 = v42 - v36;\n if (!(v37 | v36)) break;\n if (!v36) {\n v33 = v40;\n v34 = v38;\n v35 = v39 + v66;\n goto LABEL_31;\n }\n }\n v56 = v40;\n v57 = v38;\n v58 = v56;\n v33 = v56 - 1;\n v35 = v39 + v66 + 1;\n v34 = v58 - v57;\n if (v33 | v34) goto LABEL_32;\n LABEL_64:\n v22 = v59;\n v30 += v35 + 1;\n v23 = v60;\n v25 = v61;\n v26 = v62;\n v29 = v63;\n v31 = v64;\n v28 = v65;\n LABEL_34:\n v44 = v31--;\n v28 = v44 - v28;\n if (!(v31 | v28)) {\n v27 = v29 + v30 + 1;\n v54 = v25--;\n v26 = v54 - v26;\n if (v25 | v26) goto LABEL_38;\n goto LABEL_58;\n }\n } while (v28);\n v27 = v30 + v29;\n LABEL_37:\n v45 = v25--;\n v26 = v45 - v26;\n if (!(v25 | v26)) {\n LABEL_58:\n v55 = v27;\n v17 = v22 - 1;\n v20 = v23 + v55 + 1;\n v19 = v22 - v24;\n if ((v22 - 1) | (v22 - v24)) goto LABEL_41;\n goto LABEL_59;\n }\n LABEL_38:;\n } while (v26);\n v46 = v27;\n v19 = v24;\n v17 = v22;\n v20 = v46 + v23;\n LABEL_40:\n v47 = v17--;\n v19 = v47 - v19;\n if (!(v17 | v19)) {\n LABEL_59:\n v10 = v73;\n v17 = v75 - 1;\n v14 = v74;\n v13 = v78;\n v16 = v77 + v20 + 1;\n v15 = v75 - v76;\n if ((v75 - 1) | (v75 - v76)) goto LABEL_44;\n LABEL_60:\n v14 += v16 + 1;\n v11 = v72 - 1;\n v12 = v72 - v71;\n if ((v72 - 1) | (v72 - v71)) goto LABEL_47;\n goto LABEL_61;\n }\n LABEL_41:;\n } while (v19);\n v48 = v20;\n v10 = v73;\n v14 = v74;\n v17 = v75;\n v15 = v76;\n v13 = v78;\n v16 = v48 + v77;\n LABEL_43:\n v49 = v17--;\n v15 = v49 - v15;\n if (!(v17 | v15)) goto LABEL_60;\n LABEL_44:;\n } while (v15);\n v12 = v71;\n v11 = v72;\n v14 += v16;\n LABEL_46:\n v50 = v11--;\n v12 = v50 - v12;\n if (v11 | v12) {\n LABEL_47:\n if (!v12) {\n v5 = v68;\n v6 = v10;\n v4 = v69;\n v8 = v13;\n v7 = v14 + v70;\n goto LABEL_49;\n }\n continue;\n }\n break;\n }\n LABEL_61:\n v5 = v68;\n v6 = v10;\n v4 = v69;\n v8 = v13;\n v7 = v70 + v14 + 1;\n LABEL_49:\n v51 = v4--;\n v5 = v51 - v5;\n if (!(v4 | v5)) {\n v3 = v6 + v7 + 1;\n v4 = v8 - 1;\n v2 = v8 - v67;\n if ((v8 - 1) | (v8 - v67)) goto LABEL_53;\n return v3 + 1;\n }\n } while (v5);\n v2 = v67;\n v4 = v8;\n v3 = v7 + v6;\n LABEL_52:\n v52 = v4--;\n v2 = v52 - v2;\n if (!(v4 | v2)) return v3 + 1;\n LABEL_53:\n if (!v2) return v3;\n }\n }\n return v2;\n}" + }, + { + "index": 347, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int m, int n) {\n if (n < m) {\n int temp = m;\n m = n;\n n = temp;\n }\n return n * (n + 1) * (3 * m - n + 1) / 6;\n}", + "test": "int main() {\n\n assert(func0(4, 3) == 20);\n\n assert(func0(1, 2) == 2);\n\n assert(func0(2, 2) == 5);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov -0x18(%rbp),%eax\ncmp -0x14(%rbp),%eax\njge 1171 \nmov -0x14(%rbp),%eax\nmov %eax,-0x4(%rbp)\nmov -0x18(%rbp),%eax\nmov %eax,-0x14(%rbp)\nmov -0x4(%rbp),%eax\nmov %eax,-0x18(%rbp)\nmov -0x18(%rbp),%eax\nadd $0x1,%eax\nimul -0x18(%rbp),%eax\nmov %eax,%ecx\nmov -0x14(%rbp),%edx\nmov %edx,%eax\nadd %eax,%eax\nadd %edx,%eax\nsub -0x18(%rbp),%eax\nadd $0x1,%eax\nimul %ecx,%eax\nmovslq %eax,%rdx\nimul $0x2aaaaaab,%rdx,%rdx\nshr $0x20,%rdx\nsar $0x1f,%eax\nmov %edx,%esi\nsub %eax,%esi\nmov %esi,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_14]\njge short loc_1171\nmov eax, [rbp+var_14]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_18]\nmov [rbp+var_14], eax\nmov eax, [rbp+var_4]\nmov [rbp+var_18], eax\nloc_1171:\nmov eax, [rbp+var_18]\nadd eax, 1\nimul eax, [rbp+var_18]\nmov ecx, eax\nmov edx, [rbp+var_14]\nmov eax, edx\nadd eax, eax\nadd eax, edx\nsub eax, [rbp+var_18]\nadd eax, 1\nimul eax, ecx\nmovsxd rdx, eax\nimul rdx, 2AAAAAABh\nshr rdx, 20h\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n int v3; // [rsp+0h] [rbp-18h]\n int v4; // [rsp+4h] [rbp-14h]\n\n v4 = a1;\n v3 = a2;\n if ( a2 < a1 )\n {\n v4 = a2;\n v3 = a1;\n }\n return (unsigned int)(v3 * (v3 + 1) * (3 * v4 - v3 + 1) / 6);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_14]\njge short loc_1171\nmov eax, [rbp+var_14]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_18]\nmov [rbp+var_14], eax\nmov eax, [rbp+var_4]\nmov [rbp+var_18], eax\nloc_1171:\nmov eax, [rbp+var_18]\nadd eax, 1\nimul eax, [rbp+var_18]\nmov ecx, eax\nmov edx, [rbp+var_14]\nmov eax, edx\nadd eax, eax\nadd eax, edx\nsub eax, [rbp+var_18]\nadd eax, 1\nimul eax, ecx\nmovsxd rdx, eax\nimul rdx, 2AAAAAABh\nshr rdx, 20h\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2)\n{\n int v3; // [rsp+0h] [rbp-18h]\n int v4; // [rsp+4h] [rbp-14h]\n\n v4 = a1;\n v3 = a2;\n if ( a2 < a1 )\n {\n v4 = a2;\n v3 = a1;\n }\n return (unsigned int)(v3 * (v3 + 1) * (3 * v4 - v3 + 1) / 6);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2) {\n int v3;\n int v4;\n v4 = a1;\n v3 = a2;\n if (a2 < a1) {\n v4 = a2;\n v3 = a1;\n }\n return (unsigned int)(v3 * (v3 + 1) * (3 * v4 - v3 + 1) / 6);\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n int v3;\n int v4;\n v4 = a1;\n v3 = a2;\n if (a2 < a1) {\n v4 = a2;\n v3 = a1;\n }\n return (unsigned int)(v3 * (v3 + 1) * (3 * v4 - v3 + 1) / 6);\n}" + }, + { + "index": 347, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int m, int n) {\n if (n < m) {\n int temp = m;\n m = n;\n n = temp;\n }\n return n * (n + 1) * (3 * m - n + 1) / 6;\n}", + "test": "int main() {\n\n assert(func0(4, 3) == 20);\n\n assert(func0(1, 2) == 2);\n\n assert(func0(2, 2) == 5);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %esi,%eax\ncmp %edi,%esi\njge 1159 \nmov %edi,%edx\nmov %esi,%edi\nmov %edx,%eax\nlea (%rdi,%rdi,2),%esi\nsub %eax,%esi\nadd $0x1,%esi\nlea 0x1(%rax),%edx\nimul %edx,%eax\nimul %eax,%esi\nmovslq %esi,%rax\nimul $0x2aaaaaab,%rax,%rax\nshr $0x20,%rax\nsar $0x1f,%esi\nsub %esi,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov eax, edi\ncmp esi, edi\njl short loc_1159\nmov edx, esi\nmov esi, edi\nmov eax, edx\nloc_1159:\nlea edi, [rsi+rsi*2]\nsub edi, eax\nadd edi, 1\nlea edx, [rax+1]\nimul eax, edx\nimul edi, eax\nmovsxd rax, edi\nimul rax, 2AAAAAABh\nshr rax, 20h\nsar edi, 1Fh\nsub eax, edi\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n int v2; // eax\n int v3; // edx\n\n v2 = a1;\n if ( a2 >= a1 )\n {\n v3 = a2;\n a2 = a1;\n v2 = v3;\n }\n return (unsigned int)((v2 + 1) * v2 * (3 * a2 - v2 + 1) / 6);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmov eax, edi\ncmp esi, edi\njl short loc_1159\nmov edx, esi\nmov esi, edi\nmov eax, edx\nloc_1159:\nlea edi, [rsi+rsi*2]\nsub edi, eax\nadd edi, 1\nlea edx, [rax+1]\nimul eax, edx\nimul edi, eax\nmovsxd rax, edi\nimul rax, 2AAAAAABh\nshr rax, 20h\nsar edi, 1Fh\nsub eax, edi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2)\n{\n int v2; // eax\n int v3; // edx\n\n v2 = a1;\n if ( a2 >= a1 )\n {\n v3 = a2;\n a2 = a1;\n v2 = v3;\n }\n return (unsigned int)((v2 + 1) * v2 * (3 * a2 - v2 + 1) / 6);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2) {\n int v2;\n int v3;\n v2 = a1;\n if (a2 >= a1) {\n v3 = a2;\n a2 = a1;\n v2 = v3;\n }\n return (unsigned int)((v2 + 1) * v2 * (3 * a2 - v2 + 1) / 6);\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n int v2;\n int v3;\n v2 = a1;\n if (a2 >= a1) {\n v3 = a2;\n a2 = a1;\n v2 = v3;\n }\n return (unsigned int)((v2 + 1) * v2 * (3 * a2 - v2 + 1) / 6);\n}" + }, + { + "index": 348, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\nlong bin_coff(int n, int r) {\n\n long val = 1;\n\n if (r > (n - r)) {\n\n r = (n - r);\n\n }\n\n for (int i = 0; i < r; i++) {\n\n val *= (n - i);\n\n val /= (i + 1);\n\n }\n\n return val;\n\n}\n\n\n\n", + "func": "long func0(int M) {\n int n = M / 2;\n long a = bin_coff(2 * n, n);\n long b = a / (n + 1);\n return b;\n}", + "test": "int main() {\n\n assert(func0(4) == 2);\n\n assert(func0(6) == 5);\n\n assert(func0(8) == 14);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x28,%rsp\nmov %edi,-0x24(%rbp)\nmov -0x24(%rbp),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nmov %eax,-0x14(%rbp)\nmov -0x14(%rbp),%eax\nlea (%rax,%rax,1),%edx\nmov -0x14(%rbp),%eax\nmov %eax,%esi\nmov %edx,%edi\ncallq 1149 \nmov %rax,-0x10(%rbp)\nmov -0x14(%rbp),%eax\nadd $0x1,%eax\nmovslq %eax,%rcx\nmov -0x10(%rbp),%rax\ncqto\nidiv %rcx\nmov %rax,-0x8(%rbp)\nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 28h\nmov [rbp+var_24], edi\nmov eax, [rbp+var_24]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_14], eax\nmov eax, [rbp+var_14]\nlea edx, [rax+rax]\nmov eax, [rbp+var_14]\nmov esi, eax\nmov edi, edx\ncall bin_coff\nmov [rbp+var_10], rax\nmov eax, [rbp+var_14]\nadd eax, 1\nmovsxd rcx, eax\nmov rax, [rbp+var_10]\ncqo\nidiv rcx\nmov [rbp+var_8], rax\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n return bin_coff((unsigned int)(2 * (a1 / 2)), (unsigned int)(a1 / 2)) / (a1 / 2 + 1);\n}", + "ida_strip_asm": "sub_11B8:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 28h\nmov [rbp+var_24], edi\nmov eax, [rbp+var_24]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_14], eax\nmov eax, [rbp+var_14]\nlea edx, [rax+rax]\nmov eax, [rbp+var_14]\nmov esi, eax\nmov edi, edx\ncall sub_1149\nmov [rbp+var_10], rax\nmov eax, [rbp+var_14]\nadd eax, 1\nmovsxd rcx, eax\nmov rax, [rbp+var_10]\ncqo\nidiv rcx\nmov [rbp+var_8], rax\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11B8(int a1)\n{\n return sub_1149((unsigned int)(2 * (a1 / 2)), (unsigned int)(a1 / 2)) / (a1 / 2 + 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11B8(int a1) {\n return sub_1149((unsigned int)(2 * (a1 / 2)), (unsigned int)(a1 / 2)) /\n (a1 / 2 + 1);\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n return bin_coff((unsigned int)(2 * (a1 / 2)), (unsigned int)(a1 / 2)) /\n (a1 / 2 + 1);\n}" + }, + { + "index": 348, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\nlong bin_coff(int n, int r) {\n\n long val = 1;\n\n if (r > (n - r)) {\n\n r = (n - r);\n\n }\n\n for (int i = 0; i < r; i++) {\n\n val *= (n - i);\n\n val /= (i + 1);\n\n }\n\n return val;\n\n}\n\n\n\n", + "func": "long func0(int M) {\n int n = M / 2;\n long a = bin_coff(2 * n, n);\n long b = a / (n + 1);\n return b;\n}", + "test": "int main() {\n\n assert(func0(4) == 2);\n\n assert(func0(6) == 5);\n\n assert(func0(8) == 14);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %edi,%eax\nshr $0x1f,%eax\nlea (%rax,%rdi,1),%edi\nmov %edi,%ebx\nsar %ebx\nand $0xfffffffe,%edi\nmov %ebx,%esi\ncallq 1149 \nadd $0x1,%ebx\nmovslq %ebx,%rbx\ncqto\nidiv %rbx\npop %rbx\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov eax, edi\nshr eax, 1Fh\nlea edi, [rax+rdi]\nmov ebx, edi\nsar ebx, 1\nand edi, 0FFFFFFFEh\nmov esi, ebx\ncall bin_coff\nadd ebx, 1\nmovsxd rbx, ebx\ncqo\nidiv rbx\npop rbx\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1)\n{\n return bin_coff(((a1 >> 31) + a1) & 0xFFFFFFFE, (unsigned int)((int)a1 / 2)) / ((int)a1 / 2 + 1);\n}", + "ida_strip_asm": "sub_1190:\nendbr64\npush rbx\nmov eax, edi\nshr eax, 1Fh\nlea edi, [rax+rdi]\nmov ebx, edi\nsar ebx, 1\nand edi, 0FFFFFFFEh\nmov esi, ebx\ncall sub_1149\nadd ebx, 1\nmovsxd rbx, ebx\ncqo\nidiv rbx\npop rbx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1190(unsigned int a1)\n{\n return sub_1149(((a1 >> 31) + a1) & 0xFFFFFFFE, (unsigned int)((int)a1 / 2)) / ((int)a1 / 2 + 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1190(unsigned int a1) {\n return sub_1149(((a1 >> 31) + a1) & 4294967294, (unsigned int)((int)a1 / 2)) /\n ((int)a1 / 2 + 1);\n}", + "ida_pseudo_norm": "long long func0(unsigned int a1) {\n return bin_coff(((a1 >> 31) + a1) & 4294967294, (unsigned int)((int)a1 / 2)) /\n ((int)a1 / 2 + 1);\n}" + }, + { + "index": 349, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* string) {\n int has0 = 0;\n int has1 = 0;\n int hasOther = 0;\n for (int i = 0; i < strlen(string); i++) {\n if (string[i] == '0') {\n has0 = 1;\n } else if (string[i] == '1') {\n has1 = 1;\n } else {\n hasOther = 1;\n break;\n }\n }\n if ((has0 || has1) && !hasOther) {\n return \"Yes\";\n } else {\n return \"No\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"01010101010\"), \"Yes\") == 0);\n\n assert(strcmp(func0(\"name0\"), \"No\") == 0);\n\n assert(strcmp(func0(\"101\"), \"Yes\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x28,%rsp\nmov %rdi,-0x28(%rbp)\nmovl $0x0,-0x20(%rbp)\nmovl $0x0,-0x1c(%rbp)\nmovl $0x0,-0x18(%rbp)\nmovl $0x0,-0x14(%rbp)\njmp 11ff \nmov -0x14(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x30,%al\njne 11d5 \nmovl $0x1,-0x20(%rbp)\njmp 11fb \nmov -0x14(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x31,%al\njne 11f2 \nmovl $0x1,-0x1c(%rbp)\njmp 11fb \nmovl $0x1,-0x18(%rbp)\njmp 1216 \naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\nmovslq %eax,%rbx\nmov -0x28(%rbp),%rax\nmov %rax,%rdi\ncallq 1070 \ncmp %rax,%rbx\njb 11b8 \ncmpl $0x0,-0x20(%rbp)\njne 1222 \ncmpl $0x0,-0x1c(%rbp)\nje 1231 \ncmpl $0x0,-0x18(%rbp)\njne 1231 \nlea 0xdd9(%rip),%rax\njmp 1238 \nlea 0xdd4(%rip),%rax\nadd $0x28,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+s], rdi\nmov [rbp+var_20], 0\nmov [rbp+var_1C], 0\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp short loc_11FF\nloc_11B8:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 30h ; '0'\njnz short loc_11D5\nmov [rbp+var_20], 1\njmp short loc_11FB\nloc_11D5:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 31h ; '1'\njnz short loc_11F2\nmov [rbp+var_1C], 1\njmp short loc_11FB\nloc_11F2:\nmov [rbp+var_18], 1\njmp short loc_1216\nloc_11FB:\nadd [rbp+var_14], 1\nloc_11FF:\nmov eax, [rbp+var_14]\nmovsxd rbx, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rbx, rax\njb short loc_11B8\nloc_1216:\ncmp [rbp+var_20], 0\njnz short loc_1222\ncmp [rbp+var_1C], 0\njz short loc_1231\nloc_1222:\ncmp [rbp+var_18], 0\njnz short loc_1231\nlea rax, s2; \"Yes\"\njmp short loc_1238\nloc_1231:\nlea rax, aNo; \"No\"\nloc_1238:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n int v2; // [rsp+10h] [rbp-20h]\n int v3; // [rsp+14h] [rbp-1Ch]\n int v4; // [rsp+18h] [rbp-18h]\n int i; // [rsp+1Ch] [rbp-14h]\n\n v2 = 0;\n v3 = 0;\n v4 = 0;\n for ( i = 0; i < strlen(a1); ++i )\n {\n if ( a1[i] == 48 )\n {\n v2 = 1;\n }\n else\n {\n if ( a1[i] != 49 )\n {\n v4 = 1;\n break;\n }\n v3 = 1;\n }\n }\n if ( (v2 || v3) && !v4 )\n return \"Yes\";\n else\n return \"No\";\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+s], rdi\nmov [rbp+var_20], 0\nmov [rbp+var_1C], 0\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp short loc_11FF\nloc_11B8:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 30h ; '0'\njnz short loc_11D5\nmov [rbp+var_20], 1\njmp short loc_11FB\nloc_11D5:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 31h ; '1'\njnz short loc_11F2\nmov [rbp+var_1C], 1\njmp short loc_11FB\nloc_11F2:\nmov [rbp+var_18], 1\njmp short loc_1216\nloc_11FB:\nadd [rbp+var_14], 1\nloc_11FF:\nmov eax, [rbp+var_14]\nmovsxd rbx, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rbx, rax\njb short loc_11B8\nloc_1216:\ncmp [rbp+var_20], 0\njnz short loc_1222\ncmp [rbp+var_1C], 0\njz short loc_1231\nloc_1222:\ncmp [rbp+var_18], 0\njnz short loc_1231\nlea rax, s2; \"Yes\"\njmp short loc_1238\nloc_1231:\nlea rax, aNo; \"No\"\nloc_1238:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1189(const char *a1)\n{\n int v2; // [rsp+10h] [rbp-20h]\n int v3; // [rsp+14h] [rbp-1Ch]\n int v4; // [rsp+18h] [rbp-18h]\n int i; // [rsp+1Ch] [rbp-14h]\n\n v2 = 0;\n v3 = 0;\n v4 = 0;\n for ( i = 0; i < strlen(a1); ++i )\n {\n if ( a1[i] == 48 )\n {\n v2 = 1;\n }\n else\n {\n if ( a1[i] != 49 )\n {\n v4 = 1;\n break;\n }\n v3 = 1;\n }\n }\n if ( (v2 || v3) && !v4 )\n return \"Yes\";\n else\n return \"No\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1189(const char *a1) {\n int v2;\n int v3;\n int v4;\n int i;\n v2 = 0;\n v3 = 0;\n v4 = 0;\n for (i = 0; i < strlen(a1); ++i) {\n if (a1[i] == 48) {\n v2 = 1;\n } else {\n if (a1[i] != 49) {\n v4 = 1;\n break;\n }\n v3 = 1;\n }\n }\n if ((v2 || v3) && !v4)\n return \"Yes\";\n else\n return \"No\";\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n int v2;\n int v3;\n int v4;\n int i;\n v2 = 0;\n v3 = 0;\n v4 = 0;\n for (i = 0; i < strlen(a1); ++i) {\n if (a1[i] == 48) {\n v2 = 1;\n } else {\n if (a1[i] != 49) {\n v4 = 1;\n break;\n }\n v3 = 1;\n }\n }\n if ((v2 || v3) && !v4)\n return \"Yes\";\n else\n return \"No\";\n}" + }, + { + "index": 349, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* string) {\n int has0 = 0;\n int has1 = 0;\n int hasOther = 0;\n for (int i = 0; i < strlen(string); i++) {\n if (string[i] == '0') {\n has0 = 1;\n } else if (string[i] == '1') {\n has1 = 1;\n } else {\n hasOther = 1;\n break;\n }\n }\n if ((has0 || has1) && !hasOther) {\n return \"Yes\";\n } else {\n return \"No\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"01010101010\"), \"Yes\") == 0);\n\n assert(strcmp(func0(\"name0\"), \"No\") == 0);\n\n assert(strcmp(func0(\"101\"), \"Yes\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%rsi\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nmov %rsi,%rdx\nlea -0x1(%rsi,%rcx,1),%rcx\nmov $0x0,%edi\nmov $0x0,%r8d\nmov $0x1,%esi\njmp 1182 \nmov %esi,%r8d\nadd $0x1,%rdx\ncmp %rcx,%rdx\nje 1196 \nmovzbl (%rdx),%eax\ncmp $0x30,%al\nje 117b \ncmp $0x31,%al\njne 11ac \nmov %esi,%edi\njmp 117e \nor %edi,%r8d\nlea 0xe64(%rip),%rax\nlea 0xe61(%rip),%rdx\ncmove %rdx,%rax\nretq\nlea 0xe55(%rip),%rax\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmov rdi, rax\nmov rax, rbx\nadd rdi, rbx\nmov esi, 0\nmov r8d, 0\nmov ecx, 1\njmp short loc_11B8\nloc_11B1:\nmov r8d, ecx\nloc_11B4:\nadd rax, 1\nloc_11B8:\ncmp rax, rdi\njz short loc_11CE\nmovzx edx, byte ptr [rax]\ncmp dl, 30h ; '0'\njz short loc_11B1\ncmp dl, 31h ; '1'\njnz short loc_11E5\nmov esi, ecx\njmp short loc_11B4\nloc_11CE:\nor r8d, esi\nlea rax, aNo; \"No\"\nlea rdx, s2; \"Yes\"\ncmovnz rax, rdx\nloc_11E3:\npop rbx\nretn\nloc_11E5:\nlea rax, aNo; \"No\"\njmp short loc_11E3", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n size_t v2; // rdi\n const char *v3; // rax\n const char *v4; // rdi\n int v5; // esi\n int v6; // r8d\n const char *result; // rax\n\n v2 = strlen(a1);\n v3 = a1;\n v4 = &a1[v2];\n v5 = 0;\n v6 = 0;\n while ( v3 != v4 )\n {\n if ( *v3 == 48 )\n {\n v6 = 1;\n }\n else\n {\n if ( *v3 != 49 )\n return \"No\";\n v5 = 1;\n }\n ++v3;\n }\n result = \"No\";\n if ( v5 | v6 )\n return \"Yes\";\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmov rdi, rax\nmov rax, rbx\nadd rdi, rbx\nmov esi, 0\nmov r8d, 0\nmov ecx, 1\njmp short loc_11B8\nloc_11B1:\nmov r8d, ecx\nloc_11B4:\nadd rax, 1\nloc_11B8:\ncmp rax, rdi\njz short loc_11CE\nmovzx edx, byte ptr [rax]\ncmp dl, 30h ; '0'\njz short loc_11B1\ncmp dl, 31h ; '1'\njnz short loc_11E5\nmov esi, ecx\njmp short loc_11B4\nloc_11CE:\nor r8d, esi\nlea rax, aNo; \"No\"\nlea rdx, s2; \"Yes\"\ncmovnz rax, rdx\nloc_11E3:\npop rbx\nretn\nloc_11E5:\nlea rax, aNo; \"No\"\njmp short loc_11E3", + "ida_strip_pseudo": "const char *__fastcall sub_1189(const char *a1)\n{\n size_t v2; // rdi\n const char *v3; // rax\n const char *v4; // rdi\n int v5; // esi\n int v6; // r8d\n const char *result; // rax\n\n v2 = strlen(a1);\n v3 = a1;\n v4 = &a1[v2];\n v5 = 0;\n v6 = 0;\n while ( v3 != v4 )\n {\n if ( *v3 == 48 )\n {\n v6 = 1;\n }\n else\n {\n if ( *v3 != 49 )\n return \"No\";\n v5 = 1;\n }\n ++v3;\n }\n result = \"No\";\n if ( v5 | v6 )\n return \"Yes\";\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1189(const char *a1) {\n unsigned int v2;\n const char *v3;\n const char *v4;\n int v5;\n int v6;\n const char *result;\n v2 = strlen(a1);\n v3 = a1;\n v4 = &a1[v2];\n v5 = 0;\n v6 = 0;\n while (v3 != v4) {\n if (*v3 == 48) {\n v6 = 1;\n } else {\n if (*v3 != 49) return \"No\";\n v5 = 1;\n }\n ++v3;\n }\n result = \"No\";\n if (v5 | v6) return \"Yes\";\n return result;\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n unsigned int v2;\n const char *v3;\n const char *v4;\n int v5;\n int v6;\n const char *result;\n v2 = strlen(a1);\n v3 = a1;\n v4 = &a1[v2];\n v5 = 0;\n v6 = 0;\n while (v3 != v4) {\n if (*v3 == 48) {\n v6 = 1;\n } else {\n if (*v3 != 49) return \"No\";\n v5 = 1;\n }\n ++v3;\n }\n result = \"No\";\n if (v5 | v6) return \"Yes\";\n return result;\n}" + }, + { + "index": 349, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* string) {\n int has0 = 0;\n int has1 = 0;\n int hasOther = 0;\n for (int i = 0; i < strlen(string); i++) {\n if (string[i] == '0') {\n has0 = 1;\n } else if (string[i] == '1') {\n has1 = 1;\n } else {\n hasOther = 1;\n break;\n }\n }\n if ((has0 || has1) && !hasOther) {\n return \"Yes\";\n } else {\n return \"No\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"01010101010\"), \"Yes\") == 0);\n\n assert(strcmp(func0(\"name0\"), \"No\") == 0);\n\n assert(strcmp(func0(\"101\"), \"Yes\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\ncallq 1060 \nmov %rbx,%rdi\nxor %ecx,%ecx\nxor %esi,%esi\nadd %rbx,%rax\njmp 127e \nnopl 0x0(%rax)\ncmp $0x31,%dl\njne 12b0 \nmov $0x1,%ecx\nadd $0x1,%rdi\ncmp %rdi,%rax\nje 1298 \nmovzbl (%rdi),%edx\ncmp $0x30,%dl\njne 1270 \nmov $0x1,%esi\njmp 127a \nnopw 0x0(%rax,%rax,1)\nor %ecx,%esi\nlea 0xd63(%rip),%rax\nlea 0xd5f(%rip),%rdx\npop %rbx\ncmovne %rdx,%rax\nretq\nxchg %ax,%ax\nlea 0xd4d(%rip),%rax\npop %rbx\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmov rdi, rbx\nxor ecx, ecx\nxor esi, esi\nadd rax, rbx\njmp short loc_127E\nloc_1270:\ncmp dl, 31h ; '1'\njnz short loc_12B0\nmov ecx, 1\nloc_127A:\nadd rdi, 1\nloc_127E:\ncmp rdi, rax\njz short loc_1298\nmovzx edx, byte ptr [rdi]\ncmp dl, 30h ; '0'\njnz short loc_1270\nmov esi, 1\njmp short loc_127A\nloc_1298:\nor esi, ecx\nlea rax, s2; \"Yes\"\nlea rdx, aNo; \"No\"\npop rbx\ncmovz rax, rdx\nretn\nloc_12B0:\nlea rax, aNo; \"No\"\npop rbx\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n size_t v1; // rax\n int v2; // ecx\n int v3; // esi\n const char *v4; // rax\n const char *result; // rax\n\n v1 = strlen(a1);\n v2 = 0;\n v3 = 0;\n v4 = &a1[v1];\n while ( a1 != v4 )\n {\n if ( *a1 == 48 )\n {\n v3 = 1;\n }\n else\n {\n if ( *a1 != 49 )\n return \"No\";\n v2 = 1;\n }\n ++a1;\n }\n result = \"Yes\";\n if ( !(v2 | v3) )\n return \"No\";\n return result;\n}", + "ida_strip_asm": "sub_1250:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmov rdi, rbx\nxor ecx, ecx\nxor esi, esi\nadd rax, rbx\njmp short loc_127E\nloc_1270:\ncmp dl, 31h ; '1'\njnz short loc_12B0\nmov ecx, 1\nloc_127A:\nadd rdi, 1\nloc_127E:\ncmp rdi, rax\njz short loc_1298\nmovzx edx, byte ptr [rdi]\ncmp dl, 30h ; '0'\njnz short loc_1270\nmov esi, 1\njmp short loc_127A\nloc_1298:\nor esi, ecx\nlea rax, s2; \"Yes\"\nlea rdx, aNo; \"No\"\npop rbx\ncmovz rax, rdx\nretn\nloc_12B0:\nlea rax, aNo; \"No\"\npop rbx\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1250(const char *a1)\n{\n size_t v1; // rax\n int v2; // ecx\n int v3; // esi\n const char *v4; // rax\n const char *result; // rax\n\n v1 = strlen(a1);\n v2 = 0;\n v3 = 0;\n v4 = &a1[v1];\n while ( a1 != v4 )\n {\n if ( *a1 == 48 )\n {\n v3 = 1;\n }\n else\n {\n if ( *a1 != 49 )\n return \"No\";\n v2 = 1;\n }\n ++a1;\n }\n result = \"Yes\";\n if ( !(v2 | v3) )\n return \"No\";\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1250(const char *a1) {\n unsigned int v1;\n int v2;\n int v3;\n const char *v4;\n const char *result;\n v1 = strlen(a1);\n v2 = 0;\n v3 = 0;\n v4 = &a1[v1];\n while (a1 != v4) {\n if (*a1 == 48) {\n v3 = 1;\n } else {\n if (*a1 != 49) return \"No\";\n v2 = 1;\n }\n ++a1;\n }\n result = \"Yes\";\n if (!(v2 | v3)) return \"No\";\n return result;\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n unsigned int v1;\n int v2;\n int v3;\n const char *v4;\n const char *result;\n v1 = strlen(a1);\n v2 = 0;\n v3 = 0;\n v4 = &a1[v1];\n while (a1 != v4) {\n if (*a1 == 48) {\n v3 = 1;\n } else {\n if (*a1 != 49) return \"No\";\n v2 = 1;\n }\n ++a1;\n }\n result = \"Yes\";\n if (!(v2 | v3)) return \"No\";\n return result;\n}" + }, + { + "index": 349, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* string) {\n int has0 = 0;\n int has1 = 0;\n int hasOther = 0;\n for (int i = 0; i < strlen(string); i++) {\n if (string[i] == '0') {\n has0 = 1;\n } else if (string[i] == '1') {\n has1 = 1;\n } else {\n hasOther = 1;\n break;\n }\n }\n if ((has0 || has1) && !hasOther) {\n return \"Yes\";\n } else {\n return \"No\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"01010101010\"), \"Yes\") == 0);\n\n assert(strcmp(func0(\"name0\"), \"No\") == 0);\n\n assert(strcmp(func0(\"101\"), \"Yes\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\ncallq 1060 \nmov %rbx,%rdi\nxor %ecx,%ecx\nxor %esi,%esi\nadd %rbx,%rax\njmp 127e \nnopl 0x0(%rax)\ncmp $0x31,%dl\njne 12b0 \nmov $0x1,%ecx\nadd $0x1,%rdi\ncmp %rdi,%rax\nje 1298 \nmovzbl (%rdi),%edx\ncmp $0x30,%dl\njne 1270 \nmov $0x1,%esi\njmp 127a \nnopw 0x0(%rax,%rax,1)\nor %ecx,%esi\nlea 0xd63(%rip),%rax\nlea 0xd5f(%rip),%rdx\npop %rbx\ncmovne %rdx,%rax\nretq\nxchg %ax,%ax\nlea 0xd4d(%rip),%rax\npop %rbx\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmov rdi, rbx\nxor ecx, ecx\nxor esi, esi\nadd rax, rbx\njmp short loc_127E\nloc_1270:\ncmp dl, 31h ; '1'\njnz short loc_12B0\nmov ecx, 1\nloc_127A:\nadd rdi, 1\nloc_127E:\ncmp rdi, rax\njz short loc_1298\nmovzx edx, byte ptr [rdi]\ncmp dl, 30h ; '0'\njnz short loc_1270\nmov esi, 1\njmp short loc_127A\nloc_1298:\nor esi, ecx\nlea rax, s2; \"Yes\"\nlea rdx, aNo; \"No\"\npop rbx\ncmovz rax, rdx\nretn\nloc_12B0:\nlea rax, aNo; \"No\"\npop rbx\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n size_t v1; // rax\n int v2; // ecx\n int v3; // esi\n const char *v4; // rax\n const char *result; // rax\n\n v1 = strlen(a1);\n v2 = 0;\n v3 = 0;\n v4 = &a1[v1];\n while ( a1 != v4 )\n {\n if ( *a1 == 48 )\n {\n v3 = 1;\n }\n else\n {\n if ( *a1 != 49 )\n return \"No\";\n v2 = 1;\n }\n ++a1;\n }\n result = \"Yes\";\n if ( !(v2 | v3) )\n return \"No\";\n return result;\n}", + "ida_strip_asm": "sub_1250:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmov rdi, rbx\nxor ecx, ecx\nxor esi, esi\nadd rax, rbx\njmp short loc_127E\nloc_1270:\ncmp dl, 31h ; '1'\njnz short loc_12B0\nmov ecx, 1\nloc_127A:\nadd rdi, 1\nloc_127E:\ncmp rdi, rax\njz short loc_1298\nmovzx edx, byte ptr [rdi]\ncmp dl, 30h ; '0'\njnz short loc_1270\nmov esi, 1\njmp short loc_127A\nloc_1298:\nor esi, ecx\nlea rax, s2; \"Yes\"\nlea rdx, aNo; \"No\"\npop rbx\ncmovz rax, rdx\nretn\nloc_12B0:\nlea rax, aNo; \"No\"\npop rbx\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1250(const char *a1)\n{\n size_t v1; // rax\n int v2; // ecx\n int v3; // esi\n const char *v4; // rax\n const char *result; // rax\n\n v1 = strlen(a1);\n v2 = 0;\n v3 = 0;\n v4 = &a1[v1];\n while ( a1 != v4 )\n {\n if ( *a1 == 48 )\n {\n v3 = 1;\n }\n else\n {\n if ( *a1 != 49 )\n return \"No\";\n v2 = 1;\n }\n ++a1;\n }\n result = \"Yes\";\n if ( !(v2 | v3) )\n return \"No\";\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1250(const char *a1) {\n unsigned int v1;\n int v2;\n int v3;\n const char *v4;\n const char *result;\n v1 = strlen(a1);\n v2 = 0;\n v3 = 0;\n v4 = &a1[v1];\n while (a1 != v4) {\n if (*a1 == 48) {\n v3 = 1;\n } else {\n if (*a1 != 49) return \"No\";\n v2 = 1;\n }\n ++a1;\n }\n result = \"Yes\";\n if (!(v2 | v3)) return \"No\";\n return result;\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n unsigned int v1;\n int v2;\n int v3;\n const char *v4;\n const char *result;\n v1 = strlen(a1);\n v2 = 0;\n v3 = 0;\n v4 = &a1[v1];\n while (a1 != v4) {\n if (*a1 == 48) {\n v3 = 1;\n } else {\n if (*a1 != 49) return \"No\";\n v2 = 1;\n }\n ++a1;\n }\n result = \"Yes\";\n if (!(v2 | v3)) return \"No\";\n return result;\n}" + }, + { + "index": 350, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char* s) {\n int maxOcc = 0;\n int n = strlen(s);\n int arr[26] = {0};\n for (int i = 0; i < n; i++) {\n arr[s[i] - 'a']++;\n }\n for (int i = 0; i < 26; i++) {\n if (arr[i] > maxOcc) {\n maxOcc = arr[i];\n }\n }\n return n - maxOcc;\n}", + "test": "int main() {\n\n assert(func0(\"mnm\") == 1);\n\n assert(func0(\"abcda\") == 3);\n\n assert(func0(\"abcb\") == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x90,%rsp\nmov %rdi,-0x88(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovl $0x0,-0x80(%rbp)\nmov -0x88(%rbp),%rax\nmov %rax,%rdi\ncallq 1070 \nmov %eax,-0x74(%rbp)\nlea -0x70(%rbp),%rdx\nmov $0x0,%eax\nmov $0xd,%ecx\nmov %rdx,%rdi\nrep stos %rax,%es:(%rdi)\nmovl $0x0,-0x7c(%rbp)\njmp 1211 \nmov -0x7c(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x88(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmovsbl %al,%eax\nsub $0x61,%eax\nmovslq %eax,%rdx\nmov -0x70(%rbp,%rdx,4),%edx\nadd $0x1,%edx\ncltq\nmov %edx,-0x70(%rbp,%rax,4)\naddl $0x1,-0x7c(%rbp)\nmov -0x7c(%rbp),%eax\ncmp -0x74(%rbp),%eax\njl 11e4 \nmovl $0x0,-0x78(%rbp)\njmp 1240 \nmov -0x78(%rbp),%eax\ncltq\nmov -0x70(%rbp,%rax,4),%eax\ncmp %eax,-0x80(%rbp)\njge 123c \nmov -0x78(%rbp),%eax\ncltq\nmov -0x70(%rbp,%rax,4),%eax\nmov %eax,-0x80(%rbp)\naddl $0x1,-0x78(%rbp)\ncmpl $0x19,-0x78(%rbp)\njle 1222 \nmov -0x74(%rbp),%eax\nsub -0x80(%rbp),%eax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 1260 \ncallq 1080 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 90h\nmov [rbp+s], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_80], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_74], eax\nlea rdx, [rbp+var_70]\nmov eax, 0\nmov ecx, 0Dh\nmov rdi, rdx\nrep stosq\nmov [rbp+var_7C], 0\njmp short loc_1211\nloc_11E4:\nmov eax, [rbp+var_7C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nsub eax, 61h ; 'a'\nmovsxd rdx, eax\nmov edx, [rbp+rdx*4+var_70]\nadd edx, 1\ncdqe\nmov [rbp+rax*4+var_70], edx\nadd [rbp+var_7C], 1\nloc_1211:\nmov eax, [rbp+var_7C]\ncmp eax, [rbp+var_74]\njl short loc_11E4\nmov [rbp+var_78], 0\njmp short loc_1240\nloc_1222:\nmov eax, [rbp+var_78]\ncdqe\nmov eax, [rbp+rax*4+var_70]\ncmp [rbp+var_80], eax\njge short loc_123C\nmov eax, [rbp+var_78]\ncdqe\nmov eax, [rbp+rax*4+var_70]\nmov [rbp+var_80], eax\nloc_123C:\nadd [rbp+var_78], 1\nloc_1240:\ncmp [rbp+var_78], 19h\njle short loc_1222\nmov eax, [rbp+var_74]\nsub eax, [rbp+var_80]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1260\ncall ___stack_chk_fail\nlocret_1260:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v1; // eax\n int v3; // [rsp+10h] [rbp-80h]\n int i; // [rsp+14h] [rbp-7Ch]\n int j; // [rsp+18h] [rbp-78h]\n int v6; // [rsp+1Ch] [rbp-74h]\n _DWORD v7[26]; // [rsp+20h] [rbp-70h] BYREF\n unsigned __int64 v8; // [rsp+88h] [rbp-8h]\n\n v8 = __readfsqword(0x28u);\n v3 = 0;\n v6 = strlen(a1);\n memset(v7, 0, sizeof(v7));\n for ( i = 0; i < v6; ++i )\n {\n v1 = a1[i] - 97;\n ++v7[v1];\n }\n for ( j = 0; j <= 25; ++j )\n {\n if ( v3 < v7[j] )\n v3 = v7[j];\n }\n return (unsigned int)(v6 - v3);\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 90h\nmov [rbp+s], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_80], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_74], eax\nlea rdx, [rbp+var_70]\nmov eax, 0\nmov ecx, 0Dh\nmov rdi, rdx\nrep stosq\nmov [rbp+var_7C], 0\njmp short loc_1211\nloc_11E4:\nmov eax, [rbp+var_7C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nsub eax, 61h ; 'a'\nmovsxd rdx, eax\nmov edx, [rbp+rdx*4+var_70]\nadd edx, 1\ncdqe\nmov [rbp+rax*4+var_70], edx\nadd [rbp+var_7C], 1\nloc_1211:\nmov eax, [rbp+var_7C]\ncmp eax, [rbp+var_74]\njl short loc_11E4\nmov [rbp+var_78], 0\njmp short loc_1240\nloc_1222:\nmov eax, [rbp+var_78]\ncdqe\nmov eax, [rbp+rax*4+var_70]\ncmp [rbp+var_80], eax\njge short loc_123C\nmov eax, [rbp+var_78]\ncdqe\nmov eax, [rbp+rax*4+var_70]\nmov [rbp+var_80], eax\nloc_123C:\nadd [rbp+var_78], 1\nloc_1240:\ncmp [rbp+var_78], 19h\njle short loc_1222\nmov eax, [rbp+var_74]\nsub eax, [rbp+var_80]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1260\ncall ___stack_chk_fail\nlocret_1260:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(const char *a1)\n{\n int v1; // eax\n int v3; // [rsp+10h] [rbp-80h]\n int i; // [rsp+14h] [rbp-7Ch]\n int j; // [rsp+18h] [rbp-78h]\n int v6; // [rsp+1Ch] [rbp-74h]\n _DWORD v7[26]; // [rsp+20h] [rbp-70h] BYREF\n unsigned __int64 v8; // [rsp+88h] [rbp-8h]\n\n v8 = __readfsqword(0x28u);\n v3 = 0;\n v6 = strlen(a1);\n memset(v7, 0, sizeof(v7));\n for ( i = 0; i < v6; ++i )\n {\n v1 = a1[i] - 97;\n ++v7[v1];\n }\n for ( j = 0; j <= 25; ++j )\n {\n if ( v3 < v7[j] )\n v3 = v7[j];\n }\n return (unsigned int)(v6 - v3);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(const char *a1) {\n int v1;\n int v3;\n int i;\n int j;\n int v6;\n uint32_t v7[26];\n unsigned long long v8;\n v8 = __readfsqword(40u);\n v3 = 0;\n v6 = strlen(a1);\n memset(v7, 0, sizeof(v7));\n for (i = 0; i < v6; ++i) {\n v1 = a1[i] - 97;\n ++v7[v1];\n }\n for (j = 0; j <= 25; ++j) {\n if (v3 < v7[j]) v3 = v7[j];\n }\n return (unsigned int)(v6 - v3);\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v1;\n int v3;\n int i;\n int j;\n int v6;\n uint32_t v7[26];\n unsigned long long v8;\n v8 = __readfsqword(40u);\n v3 = 0;\n v6 = strlen(a1);\n memset(v7, 0, sizeof(v7));\n for (i = 0; i < v6; ++i) {\n v1 = a1[i] - 97;\n ++v7[v1];\n }\n for (j = 0; j <= 25; ++j) {\n if (v3 < v7[j]) v3 = v7[j];\n }\n return (unsigned int)(v6 - v3);\n}" + }, + { + "index": 350, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char* s) {\n int maxOcc = 0;\n int n = strlen(s);\n int arr[26] = {0};\n for (int i = 0; i < n; i++) {\n arr[s[i] - 'a']++;\n }\n for (int i = 0; i < 26; i++) {\n if (arr[i] > maxOcc) {\n maxOcc = arr[i];\n }\n }\n return n - maxOcc;\n}", + "test": "int main() {\n\n assert(func0(\"mnm\") == 1);\n\n assert(func0(\"abcda\") == 3);\n\n assert(func0(\"abcb\") == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x78,%rsp\nmov %rdi,%rsi\nmov %fs:0x28,%rax\nmov %rax,0x68(%rsp)\nxor %eax,%eax\nmov $0xffffffffffffffff,%rcx\nrepnz scas %es:(%rdi),%al\nnot %rcx\nlea -0x1(%rcx),%r8\nmov %rsp,%rdi\nmov $0xd,%ecx\nmov $0x0,%eax\nrep stos %rax,%es:(%rdi)\ntest %r8d,%r8d\njle 11ca \nmov %rsi,%rdx\nlea -0x1(%r8),%eax\nlea 0x1(%rsi,%rax,1),%rcx\nmovsbl (%rdx),%eax\nsub $0x61,%eax\ncltq\naddl $0x1,(%rsp,%rax,4)\nadd $0x1,%rdx\ncmp %rcx,%rdx\njne 11b5 \nmov %rsp,%rax\nlea 0x68(%rsp),%rsi\nmov $0x0,%edx\nmov (%rax),%ecx\ncmp %ecx,%edx\ncmovl %ecx,%edx\nadd $0x4,%rax\ncmp %rsi,%rax\njne 11d7 \nmov %r8d,%eax\nsub %edx,%eax\nmov 0x68(%rsp),%rdi\nxor %fs:0x28,%rdi\njne 1201 \nadd $0x78,%rsp\nretq\ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbx\nsub rsp, 70h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+78h+var_10], rax\nxor eax, eax\ncall _strlen\nmov r8, rax\nmov rdi, rsp\nmov ecx, 0Dh\nmov eax, 0\nrep stosq\ntest r8d, r8d\njle short loc_11E3\nmov rdx, rbx\nlea eax, [r8-1]\nlea rcx, [rbx+rax+1]\nloc_11CE:\nmovsx eax, byte ptr [rdx]\nsub eax, 61h ; 'a'\ncdqe\nadd [rsp+rax*4+78h+var_78], 1\nadd rdx, 1\ncmp rdx, rcx\njnz short loc_11CE\nloc_11E3:\nmov rax, rsp\nlea rsi, [rsp+78h+var_10]\nmov edx, 0\nloc_11F0:\nmov ecx, [rax]\ncmp edx, ecx\ncmovl edx, ecx\nadd rax, 4\ncmp rax, rsi\njnz short loc_11F0\nmov eax, r8d\nsub eax, edx\nmov rdx, [rsp+78h+var_10]\nsub rdx, fs:28h\njnz short loc_121B\nadd rsp, 70h\npop rbx\nretn\nloc_121B:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v1; // r8d\n const char *v2; // rdx\n unsigned __int64 *v3; // rax\n int v4; // edx\n _DWORD v6[26]; // [rsp+0h] [rbp-78h] BYREF\n unsigned __int64 v7; // [rsp+68h] [rbp-10h] BYREF\n\n v7 = __readfsqword(0x28u);\n v1 = strlen(a1);\n memset(v6, 0, sizeof(v6));\n if ( v1 > 0 )\n {\n v2 = a1;\n do\n ++v6[*v2++ - 97];\n while ( v2 != &a1[v1 - 1 + 1] );\n }\n v3 = (unsigned __int64 *)v6;\n v4 = 0;\n do\n {\n if ( v4 < *(_DWORD *)v3 )\n v4 = *(_DWORD *)v3;\n v3 = (unsigned __int64 *)((char *)v3 + 4);\n }\n while ( v3 != &v7 );\n return (unsigned int)(v1 - v4);\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbx\nsub rsp, 70h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+78h+var_10], rax\nxor eax, eax\ncall _strlen\nmov r8, rax\nmov rdi, rsp\nmov ecx, 0Dh\nmov eax, 0\nrep stosq\ntest r8d, r8d\njle short loc_11E3\nmov rdx, rbx\nlea eax, [r8-1]\nlea rcx, [rbx+rax+1]\nloc_11CE:\nmovsx eax, byte ptr [rdx]\nsub eax, 61h ; 'a'\ncdqe\nadd [rsp+rax*4+78h+var_78], 1\nadd rdx, 1\ncmp rdx, rcx\njnz short loc_11CE\nloc_11E3:\nmov rax, rsp\nlea rsi, [rsp+78h+var_10]\nmov edx, 0\nloc_11F0:\nmov ecx, [rax]\ncmp edx, ecx\ncmovl edx, ecx\nadd rax, 4\ncmp rax, rsi\njnz short loc_11F0\nmov eax, r8d\nsub eax, edx\nmov rdx, [rsp+78h+var_10]\nsub rdx, fs:28h\njnz short loc_121B\nadd rsp, 70h\npop rbx\nretn\nloc_121B:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(const char *a1)\n{\n int v1; // r8d\n const char *v2; // rdx\n unsigned __int64 *v3; // rax\n int v4; // edx\n _DWORD v6[26]; // [rsp+0h] [rbp-78h] BYREF\n unsigned __int64 v7; // [rsp+68h] [rbp-10h] BYREF\n\n v7 = __readfsqword(0x28u);\n v1 = strlen(a1);\n memset(v6, 0, sizeof(v6));\n if ( v1 > 0 )\n {\n v2 = a1;\n do\n ++v6[*v2++ - 97];\n while ( v2 != &a1[v1 - 1 + 1] );\n }\n v3 = (unsigned __int64 *)v6;\n v4 = 0;\n do\n {\n if ( v4 < *(_DWORD *)v3 )\n v4 = *(_DWORD *)v3;\n v3 = (unsigned __int64 *)((char *)v3 + 4);\n }\n while ( v3 != &v7 );\n return (unsigned int)(v1 - v4);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(const char *a1) {\n int v1;\n const char *v2;\n unsigned long long *v3;\n int v4;\n uint32_t v6[26];\n unsigned long long v7;\n v7 = __readfsqword(40u);\n v1 = strlen(a1);\n memset(v6, 0, sizeof(v6));\n if (v1 > 0) {\n v2 = a1;\n do\n ++v6[*v2++ - 97];\n while (v2 != &a1[v1 - 1 + 1]);\n }\n v3 = (unsigned long long *)v6;\n v4 = 0;\n do {\n if (v4 < *(uint32_t *)v3) v4 = *(uint32_t *)v3;\n v3 = (unsigned long long *)((char *)v3 + 4);\n } while (v3 != &v7);\n return (unsigned int)(v1 - v4);\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v1;\n const char *v2;\n unsigned long long *v3;\n int v4;\n uint32_t v6[26];\n unsigned long long v7;\n v7 = __readfsqword(40u);\n v1 = strlen(a1);\n memset(v6, 0, sizeof(v6));\n if (v1 > 0) {\n v2 = a1;\n do\n ++v6[*v2++ - 97];\n while (v2 != &a1[v1 - 1 + 1]);\n }\n v3 = (unsigned long long *)v6;\n v4 = 0;\n do {\n if (v4 < *(uint32_t *)v3) v4 = *(uint32_t *)v3;\n v3 = (unsigned long long *)((char *)v3 + 4);\n } while (v3 != &v7);\n return (unsigned int)(v1 - v4);\n}" + }, + { + "index": 350, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char* s) {\n int maxOcc = 0;\n int n = strlen(s);\n int arr[26] = {0};\n for (int i = 0; i < n; i++) {\n arr[s[i] - 'a']++;\n }\n for (int i = 0; i < 26; i++) {\n if (arr[i] > maxOcc) {\n maxOcc = arr[i];\n }\n }\n return n - maxOcc;\n}", + "test": "int main() {\n\n assert(func0(\"mnm\") == 1);\n\n assert(func0(\"abcda\") == 3);\n\n assert(func0(\"abcb\") == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\nsub $0x70,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x68(%rsp)\nxor %eax,%eax\ncallq 1070 \nmov %rsp,%rdi\nmov $0xd,%ecx\nmov %rax,%r8\nxor %eax,%eax\nrep stos %rax,%es:(%rdi)\ntest %r8d,%r8d\njle 12cb \nlea -0x1(%r8),%eax\nmov %rbx,%rdi\nlea 0x1(%rbx,%rax,1),%rdx\nnopw 0x0(%rax,%rax,1)\nmovsbl (%rdi),%eax\nadd $0x1,%rdi\nsub $0x61,%eax\ncltq\naddl $0x1,(%rsp,%rax,4)\ncmp %rdx,%rdi\njne 1278 \nmov (%rsp),%ecx\nlea 0x4(%rsp),%rax\nlea 0x68(%rsp),%rsi\nxor %edx,%edx\njmp 12a6 \nxchg %ax,%ax\nmov (%rax),%ecx\nadd $0x4,%rax\ncmp %ecx,%edx\ncmovl %ecx,%edx\ncmp %rax,%rsi\njne 12a0 \nmov %r8d,%eax\nsub %edx,%eax\nmov 0x68(%rsp),%rbx\nxor %fs:0x28,%rbx\njne 12cf \nadd $0x70,%rsp\npop %rbx\nretq\nxor %ecx,%ecx\njmp 1290 \ncallq 1080 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\nsub rsp, 70h\nmov rax, fs:28h\nmov [rsp+78h+var_10], rax\nxor eax, eax\ncall _strlen\nmov rdx, rsp\nmov ecx, 0Dh\nmov rsi, rax\nmov rdi, rdx\nxor eax, eax\nrep stosq\ntest esi, esi\njle short loc_128D\nlea eax, [rsi-1]\nmov rdi, rbx\nlea rcx, [rbx+rax+1]\nnop dword ptr [rax+rax+00h]\nloc_1278:\nmovsx eax, byte ptr [rdi]\nadd rdi, 1\nsub eax, 61h ; 'a'\ncdqe\nadd [rsp+rax*4+78h+var_78], 1\ncmp rdi, rcx\njnz short loc_1278\nloc_128D:\nmov rdi, rdx\nlea rcx, [rsp+78h+var_10]\nxor edx, edx\nnop word ptr [rax+rax+00000000h]\nloc_12A0:\nmov eax, [rdi]\ncmp edx, eax\ncmovl edx, eax\nmov eax, [rdi+4]\ncmp edx, eax\ncmovl edx, eax\nadd rdi, 8\ncmp rcx, rdi\njnz short loc_12A0\nmov eax, esi\nsub eax, edx\nmov rdx, [rsp+78h+var_10]\nsub rdx, fs:28h\njnz short loc_12D2\nadd rsp, 70h\npop rbx\nretn\nloc_12D2:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v1; // esi\n __int64 v2; // rcx\n int v3; // eax\n unsigned __int64 *v4; // rdi\n int v5; // edx\n _DWORD v7[26]; // [rsp+0h] [rbp-78h] BYREF\n unsigned __int64 v8; // [rsp+68h] [rbp-10h] BYREF\n\n v8 = __readfsqword(0x28u);\n v1 = strlen(a1);\n memset(v7, 0, sizeof(v7));\n if ( v1 > 0 )\n {\n v2 = (__int64)&a1[v1 - 1 + 1];\n do\n {\n v3 = *a1++;\n ++v7[v3 - 97];\n }\n while ( a1 != (const char *)v2 );\n }\n v4 = (unsigned __int64 *)v7;\n v5 = 0;\n do\n {\n if ( v5 < *(_DWORD *)v4 )\n v5 = *(_DWORD *)v4;\n if ( v5 < *((_DWORD *)v4 + 1) )\n v5 = *((_DWORD *)v4 + 1);\n ++v4;\n }\n while ( &v8 != v4 );\n return (unsigned int)(v1 - v5);\n}", + "ida_strip_asm": "sub_1230:\nendbr64\npush rbx\nmov rbx, rdi\nsub rsp, 70h\nmov rax, fs:28h\nmov [rsp+78h+var_10], rax\nxor eax, eax\ncall _strlen\nmov rdx, rsp\nmov ecx, 0Dh\nmov rsi, rax\nmov rdi, rdx\nxor eax, eax\nrep stosq\ntest esi, esi\njle short loc_128D\nlea eax, [rsi-1]\nmov rdi, rbx\nlea rcx, [rbx+rax+1]\nnop dword ptr [rax+rax+00h]\nloc_1278:\nmovsx eax, byte ptr [rdi]\nadd rdi, 1\nsub eax, 61h ; 'a'\ncdqe\nadd [rsp+rax*4+78h+var_78], 1\ncmp rdi, rcx\njnz short loc_1278\nloc_128D:\nmov rdi, rdx\nlea rcx, [rsp+78h+var_10]\nxor edx, edx\nnop word ptr [rax+rax+00000000h]\nloc_12A0:\nmov eax, [rdi]\ncmp edx, eax\ncmovl edx, eax\nmov eax, [rdi+4]\ncmp edx, eax\ncmovl edx, eax\nadd rdi, 8\ncmp rcx, rdi\njnz short loc_12A0\nmov eax, esi\nsub eax, edx\nmov rdx, [rsp+78h+var_10]\nsub rdx, fs:28h\njnz short loc_12D2\nadd rsp, 70h\npop rbx\nretn\nloc_12D2:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1230(const char *a1)\n{\n int v1; // esi\n __int64 v2; // rcx\n int v3; // eax\n unsigned __int64 *v4; // rdi\n int v5; // edx\n _DWORD v7[26]; // [rsp+0h] [rbp-78h] BYREF\n unsigned __int64 v8; // [rsp+68h] [rbp-10h] BYREF\n\n v8 = __readfsqword(0x28u);\n v1 = strlen(a1);\n memset(v7, 0, sizeof(v7));\n if ( v1 > 0 )\n {\n v2 = (__int64)&a1[v1 - 1 + 1];\n do\n {\n v3 = *a1++;\n ++v7[v3 - 97];\n }\n while ( a1 != (const char *)v2 );\n }\n v4 = (unsigned __int64 *)v7;\n v5 = 0;\n do\n {\n if ( v5 < *(_DWORD *)v4 )\n v5 = *(_DWORD *)v4;\n if ( v5 < *((_DWORD *)v4 + 1) )\n v5 = *((_DWORD *)v4 + 1);\n ++v4;\n }\n while ( &v8 != v4 );\n return (unsigned int)(v1 - v5);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1230(const char *a1) {\n int v1;\n long long v2;\n int v3;\n unsigned long long *v4;\n int v5;\n uint32_t v7[26];\n unsigned long long v8;\n v8 = __readfsqword(40u);\n v1 = strlen(a1);\n memset(v7, 0, sizeof(v7));\n if (v1 > 0) {\n v2 = (long long)&a1[v1 - 1 + 1];\n do {\n v3 = *a1++;\n ++v7[v3 - 97];\n } while (a1 != (const char *)v2);\n }\n v4 = (unsigned long long *)v7;\n v5 = 0;\n do {\n if (v5 < *(uint32_t *)v4) v5 = *(uint32_t *)v4;\n if (v5 < *((uint32_t *)v4 + 1)) v5 = *((uint32_t *)v4 + 1);\n ++v4;\n } while (&v8 != v4);\n return (unsigned int)(v1 - v5);\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v1;\n long long v2;\n int v3;\n unsigned long long *v4;\n int v5;\n uint32_t v7[26];\n unsigned long long v8;\n v8 = __readfsqword(40u);\n v1 = strlen(a1);\n memset(v7, 0, sizeof(v7));\n if (v1 > 0) {\n v2 = (long long)&a1[v1 - 1 + 1];\n do {\n v3 = *a1++;\n ++v7[v3 - 97];\n } while (a1 != (const char *)v2);\n }\n v4 = (unsigned long long *)v7;\n v5 = 0;\n do {\n if (v5 < *(uint32_t *)v4) v5 = *(uint32_t *)v4;\n if (v5 < *((uint32_t *)v4 + 1)) v5 = *((uint32_t *)v4 + 1);\n ++v4;\n } while (&v8 != v4);\n return (unsigned int)(v1 - v5);\n}" + }, + { + "index": 350, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char* s) {\n int maxOcc = 0;\n int n = strlen(s);\n int arr[26] = {0};\n for (int i = 0; i < n; i++) {\n arr[s[i] - 'a']++;\n }\n for (int i = 0; i < 26; i++) {\n if (arr[i] > maxOcc) {\n maxOcc = arr[i];\n }\n }\n return n - maxOcc;\n}", + "test": "int main() {\n\n assert(func0(\"mnm\") == 1);\n\n assert(func0(\"abcda\") == 3);\n\n assert(func0(\"abcb\") == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\nsub $0x70,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x68(%rsp)\nxor %eax,%eax\ncallq 1070 \nmov %rsp,%rdi\nmov $0xd,%ecx\nmov %rax,%rsi\nxor %eax,%eax\nrep stos %rax,%es:(%rdi)\ntest %esi,%esi\njle 1285 \nlea -0x1(%rsi),%eax\nmov %rbx,%rdi\nlea 0x1(%rbx,%rax,1),%rdx\nmovsbl (%rdi),%eax\nadd $0x1,%rdi\nsub $0x61,%eax\ncltq\naddl $0x1,(%rsp,%rax,4)\ncmp %rdi,%rdx\njne 1270 \nmovdqa 0x10(%rsp),%xmm0\nmov 0x64(%rsp),%edx\nmov %esi,%ecx\ncmp %edx,0x60(%rsp)\ncmovge 0x60(%rsp),%edx\nmovdqa %xmm0,%xmm1\npcmpgtd 0x20(%rsp),%xmm1\npand %xmm1,%xmm0\nmovdqa %xmm0,%xmm2\nmovdqa %xmm1,%xmm0\npandn 0x20(%rsp),%xmm0\npxor %xmm1,%xmm1\npor %xmm2,%xmm0\nmovdqa (%rsp),%xmm2\npcmpgtd %xmm1,%xmm2\npand (%rsp),%xmm2\nmovdqa %xmm0,%xmm1\npcmpgtd %xmm2,%xmm1\npand %xmm1,%xmm0\npandn %xmm2,%xmm1\npor %xmm1,%xmm0\nmovdqa 0x30(%rsp),%xmm1\nmovdqa %xmm1,%xmm2\npcmpgtd 0x40(%rsp),%xmm2\npand %xmm2,%xmm1\npandn 0x40(%rsp),%xmm2\npor %xmm2,%xmm1\nmovdqa %xmm1,%xmm2\npcmpgtd 0x50(%rsp),%xmm2\npand %xmm2,%xmm1\npandn 0x50(%rsp),%xmm2\npor %xmm2,%xmm1\nmovdqa %xmm0,%xmm2\npcmpgtd %xmm1,%xmm2\npand %xmm2,%xmm0\npandn %xmm1,%xmm2\npor %xmm2,%xmm0\nmovdqa %xmm0,%xmm1\npsrldq $0x8,%xmm1\nmovdqa %xmm1,%xmm2\npcmpgtd %xmm0,%xmm2\npand %xmm2,%xmm1\npandn %xmm0,%xmm2\npor %xmm2,%xmm1\nmovdqa %xmm1,%xmm2\npsrldq $0x4,%xmm2\nmovdqa %xmm2,%xmm0\npcmpgtd %xmm1,%xmm0\npand %xmm0,%xmm2\npandn %xmm1,%xmm0\npor %xmm2,%xmm0\nmovd %xmm0,%eax\ncmp %eax,%edx\ncmovge %edx,%eax\nsub %eax,%ecx\nmov 0x68(%rsp),%rbx\nxor %fs:0x28,%rbx\nmov %ecx,%eax\njne 1387 \nadd $0x70,%rsp\npop %rbx\nretq\ncallq 1080 <__stack_chk_fail@plt>\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\nsub rsp, 70h\nmov rax, fs:28h\nmov [rsp+78h+var_10], rax\nxor eax, eax\ncall _strlen\nmov rdi, rsp\nmov ecx, 0Dh\nmov rsi, rax\nxor eax, eax\nrep stosq\ntest esi, esi\njle short loc_1285\nlea eax, [rsi-1]\nmov rdi, rbx\nlea rdx, [rbx+rax+1]\nloc_1270:\nmovsx eax, byte ptr [rdi]\nadd rdi, 1\nsub eax, 61h ; 'a'\ncdqe\nadd dword ptr [rsp+rax*4+78h+var_78], 1\ncmp rdi, rdx\njnz short loc_1270\nloc_1285:\nmovdqa xmm1, [rsp+78h+var_58]\npxor xmm3, xmm3\nmov edx, [rsp+78h+var_18]\nmov ecx, [rsp+78h+var_14]\nmovdqa xmm0, xmm1\npcmpgtd xmm0, [rsp+78h+var_48]\ncmp edx, ecx\ncmovl edx, ecx\npand xmm1, xmm0\npandn xmm0, [rsp+78h+var_48]\npor xmm0, xmm1\nmovdqa xmm1, [rsp+78h+var_68]\nmovdqa xmm2, xmm1\npcmpgtd xmm2, [rsp+78h+var_78]\npand xmm1, xmm2\npandn xmm2, [rsp+78h+var_78]\npor xmm2, xmm1\nmovdqa xmm1, xmm0\npcmpgtd xmm1, xmm2\npand xmm0, xmm1\npandn xmm1, xmm2\nmovdqa xmm2, [rsp+78h+var_28]\npor xmm1, xmm0\nmovdqa xmm0, xmm2\npcmpgtd xmm0, [rsp+78h+var_38]\npand xmm2, xmm0\npandn xmm0, [rsp+78h+var_38]\npor xmm0, xmm2\nmovdqa xmm2, xmm0\npcmpgtd xmm2, xmm3\npand xmm0, xmm2\nmovdqa xmm2, xmm1\npcmpgtd xmm2, xmm0\npand xmm1, xmm2\npandn xmm2, xmm0\nmovdqa xmm0, xmm2\npor xmm0, xmm1\nmovdqa xmm2, xmm0\npsrldq xmm2, 8\nmovdqa xmm1, xmm2\npcmpgtd xmm1, xmm0\npand xmm2, xmm1\npandn xmm1, xmm0\npor xmm1, xmm2\nmovdqa xmm2, xmm1\npsrldq xmm2, 4\nmovdqa xmm0, xmm2\npcmpgtd xmm0, xmm1\npand xmm2, xmm0\npandn xmm0, xmm1\npor xmm0, xmm2\nmovd eax, xmm0\ncmp edx, eax\ncmovl edx, eax\nmov eax, esi\nsub eax, edx\nmov rdx, [rsp+78h+var_10]\nsub rdx, fs:28h\njnz short loc_1383\nadd rsp, 70h\npop rbx\nretn\nloc_1383:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v1; // esi\n __int64 v2; // rdx\n int v3; // eax\n __m128i si128; // xmm1\n int v5; // edx\n __m128i v6; // xmm0\n __m128i v7; // xmm0\n __m128i v8; // xmm1\n __m128i v9; // xmm2\n __m128i v10; // xmm2\n __m128i v11; // xmm1\n __m128i v12; // xmm0\n __m128i v13; // xmm1\n __m128i v14; // xmm2\n __m128i v15; // xmm1\n __m128i v16; // xmm0\n __m128i v17; // xmm0\n __m128i v18; // xmm0\n __m128i v19; // xmm2\n __m128i v20; // xmm0\n __m128i v21; // xmm2\n __m128i v22; // xmm1\n __m128i v23; // xmm1\n __m128i v24; // xmm2\n __m128i v25; // xmm0\n int v26; // eax\n _BYTE v28[104]; // [rsp+0h] [rbp-78h] BYREF\n unsigned __int64 v29; // [rsp+68h] [rbp-10h]\n\n v29 = __readfsqword(0x28u);\n v1 = strlen(a1);\n memset(v28, 0, sizeof(v28));\n if ( v1 > 0 )\n {\n v2 = (__int64)&a1[v1 - 1 + 1];\n do\n {\n v3 = *a1++;\n ++*(_DWORD *)&v28[4 * v3 - 388];\n }\n while ( a1 != (const char *)v2 );\n }\n si128 = _mm_load_si128((const __m128i *)&v28[32]);\n v5 = *(_DWORD *)&v28[96];\n v6 = _mm_cmpgt_epi32(si128, *(__m128i *)&v28[48]);\n if ( *(int *)&v28[96] < *(int *)&v28[100] )\n v5 = *(_DWORD *)&v28[100];\n v7 = _mm_or_si128(_mm_andnot_si128(v6, *(__m128i *)&v28[48]), _mm_and_si128(si128, v6));\n v8 = _mm_load_si128((const __m128i *)&v28[16]);\n v9 = _mm_cmpgt_epi32(v8, *(__m128i *)v28);\n v10 = _mm_or_si128(_mm_andnot_si128(v9, *(__m128i *)v28), _mm_and_si128(v8, v9));\n v11 = _mm_cmpgt_epi32(v7, v10);\n v12 = _mm_and_si128(v7, v11);\n v13 = _mm_andnot_si128(v11, v10);\n v14 = _mm_load_si128((const __m128i *)&v28[80]);\n v15 = _mm_or_si128(v13, v12);\n v16 = _mm_cmpgt_epi32(v14, *(__m128i *)&v28[64]);\n v17 = _mm_or_si128(_mm_andnot_si128(v16, *(__m128i *)&v28[64]), _mm_and_si128(v14, v16));\n v18 = _mm_and_si128(v17, _mm_cmpgt_epi32(v17, (__m128i)0LL));\n v19 = _mm_cmpgt_epi32(v15, v18);\n v20 = _mm_or_si128(_mm_andnot_si128(v19, v18), _mm_and_si128(v15, v19));\n v21 = _mm_srli_si128(v20, 8);\n v22 = _mm_cmpgt_epi32(v21, v20);\n v23 = _mm_or_si128(_mm_andnot_si128(v22, v20), _mm_and_si128(v21, v22));\n v24 = _mm_srli_si128(v23, 4);\n v25 = _mm_cmpgt_epi32(v24, v23);\n v26 = _mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v25, v23), _mm_and_si128(v24, v25)));\n if ( v5 < v26 )\n v5 = v26;\n return (unsigned int)(v1 - v5);\n}", + "ida_strip_asm": "sub_1230:\nendbr64\npush rbx\nmov rbx, rdi\nsub rsp, 70h\nmov rax, fs:28h\nmov [rsp+78h+var_10], rax\nxor eax, eax\ncall _strlen\nmov rdi, rsp\nmov ecx, 0Dh\nmov rsi, rax\nxor eax, eax\nrep stosq\ntest esi, esi\njle short loc_1285\nlea eax, [rsi-1]\nmov rdi, rbx\nlea rdx, [rbx+rax+1]\nloc_1270:\nmovsx eax, byte ptr [rdi]\nadd rdi, 1\nsub eax, 61h ; 'a'\ncdqe\nadd dword ptr [rsp+rax*4+78h+var_78], 1\ncmp rdi, rdx\njnz short loc_1270\nloc_1285:\nmovdqa xmm1, [rsp+78h+var_58]\npxor xmm3, xmm3\nmov edx, [rsp+78h+var_18]\nmov ecx, [rsp+78h+var_14]\nmovdqa xmm0, xmm1\npcmpgtd xmm0, [rsp+78h+var_48]\ncmp edx, ecx\ncmovl edx, ecx\npand xmm1, xmm0\npandn xmm0, [rsp+78h+var_48]\npor xmm0, xmm1\nmovdqa xmm1, [rsp+78h+var_68]\nmovdqa xmm2, xmm1\npcmpgtd xmm2, [rsp+78h+var_78]\npand xmm1, xmm2\npandn xmm2, [rsp+78h+var_78]\npor xmm2, xmm1\nmovdqa xmm1, xmm0\npcmpgtd xmm1, xmm2\npand xmm0, xmm1\npandn xmm1, xmm2\nmovdqa xmm2, [rsp+78h+var_28]\npor xmm1, xmm0\nmovdqa xmm0, xmm2\npcmpgtd xmm0, [rsp+78h+var_38]\npand xmm2, xmm0\npandn xmm0, [rsp+78h+var_38]\npor xmm0, xmm2\nmovdqa xmm2, xmm0\npcmpgtd xmm2, xmm3\npand xmm0, xmm2\nmovdqa xmm2, xmm1\npcmpgtd xmm2, xmm0\npand xmm1, xmm2\npandn xmm2, xmm0\nmovdqa xmm0, xmm2\npor xmm0, xmm1\nmovdqa xmm2, xmm0\npsrldq xmm2, 8\nmovdqa xmm1, xmm2\npcmpgtd xmm1, xmm0\npand xmm2, xmm1\npandn xmm1, xmm0\npor xmm1, xmm2\nmovdqa xmm2, xmm1\npsrldq xmm2, 4\nmovdqa xmm0, xmm2\npcmpgtd xmm0, xmm1\npand xmm2, xmm0\npandn xmm0, xmm1\npor xmm0, xmm2\nmovd eax, xmm0\ncmp edx, eax\ncmovl edx, eax\nmov eax, esi\nsub eax, edx\nmov rdx, [rsp+78h+var_10]\nsub rdx, fs:28h\njnz short loc_1383\nadd rsp, 70h\npop rbx\nretn\nloc_1383:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1230(const char *a1)\n{\n int v1; // esi\n __int64 v2; // rdx\n int v3; // eax\n __m128i si128; // xmm1\n int v5; // edx\n __m128i v6; // xmm0\n __m128i v7; // xmm0\n __m128i v8; // xmm1\n __m128i v9; // xmm2\n __m128i v10; // xmm2\n __m128i v11; // xmm1\n __m128i v12; // xmm0\n __m128i v13; // xmm1\n __m128i v14; // xmm2\n __m128i v15; // xmm1\n __m128i v16; // xmm0\n __m128i v17; // xmm0\n __m128i v18; // xmm0\n __m128i v19; // xmm2\n __m128i v20; // xmm0\n __m128i v21; // xmm2\n __m128i v22; // xmm1\n __m128i v23; // xmm1\n __m128i v24; // xmm2\n __m128i v25; // xmm0\n int v26; // eax\n _BYTE v28[104]; // [rsp+0h] [rbp-78h] BYREF\n unsigned __int64 v29; // [rsp+68h] [rbp-10h]\n\n v29 = __readfsqword(0x28u);\n v1 = strlen(a1);\n memset(v28, 0, sizeof(v28));\n if ( v1 > 0 )\n {\n v2 = (__int64)&a1[v1 - 1 + 1];\n do\n {\n v3 = *a1++;\n ++*(_DWORD *)&v28[4 * v3 - 388];\n }\n while ( a1 != (const char *)v2 );\n }\n si128 = _mm_load_si128((const __m128i *)&v28[32]);\n v5 = *(_DWORD *)&v28[96];\n v6 = _mm_cmpgt_epi32(si128, *(__m128i *)&v28[48]);\n if ( *(int *)&v28[96] < *(int *)&v28[100] )\n v5 = *(_DWORD *)&v28[100];\n v7 = _mm_or_si128(_mm_andnot_si128(v6, *(__m128i *)&v28[48]), _mm_and_si128(si128, v6));\n v8 = _mm_load_si128((const __m128i *)&v28[16]);\n v9 = _mm_cmpgt_epi32(v8, *(__m128i *)v28);\n v10 = _mm_or_si128(_mm_andnot_si128(v9, *(__m128i *)v28), _mm_and_si128(v8, v9));\n v11 = _mm_cmpgt_epi32(v7, v10);\n v12 = _mm_and_si128(v7, v11);\n v13 = _mm_andnot_si128(v11, v10);\n v14 = _mm_load_si128((const __m128i *)&v28[80]);\n v15 = _mm_or_si128(v13, v12);\n v16 = _mm_cmpgt_epi32(v14, *(__m128i *)&v28[64]);\n v17 = _mm_or_si128(_mm_andnot_si128(v16, *(__m128i *)&v28[64]), _mm_and_si128(v14, v16));\n v18 = _mm_and_si128(v17, _mm_cmpgt_epi32(v17, (__m128i)0LL));\n v19 = _mm_cmpgt_epi32(v15, v18);\n v20 = _mm_or_si128(_mm_andnot_si128(v19, v18), _mm_and_si128(v15, v19));\n v21 = _mm_srli_si128(v20, 8);\n v22 = _mm_cmpgt_epi32(v21, v20);\n v23 = _mm_or_si128(_mm_andnot_si128(v22, v20), _mm_and_si128(v21, v22));\n v24 = _mm_srli_si128(v23, 4);\n v25 = _mm_cmpgt_epi32(v24, v23);\n v26 = _mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v25, v23), _mm_and_si128(v24, v25)));\n if ( v5 < v26 )\n v5 = v26;\n return (unsigned int)(v1 - v5);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1230(const char *a1) {\n int v1;\n long long v2;\n int v3;\n __m128i si128;\n int v5;\n __m128i v6;\n __m128i v7;\n __m128i v8;\n __m128i v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n __m128i v15;\n __m128i v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n __m128i v20;\n __m128i v21;\n __m128i v22;\n __m128i v23;\n __m128i v24;\n __m128i v25;\n int v26;\n uint8_t v28[104];\n unsigned long long v29;\n v29 = __readfsqword(40u);\n v1 = strlen(a1);\n memset(v28, 0, sizeof(v28));\n if (v1 > 0) {\n v2 = (long long)&a1[v1 - 1 + 1];\n do {\n v3 = *a1++;\n ++*(uint32_t *)&v28[4 * v3 - 388];\n } while (a1 != (const char *)v2);\n }\n si128 = _mm_load_si128((const __m128i *)&v28[32]);\n v5 = *(uint32_t *)&v28[96];\n v6 = _mm_cmpgt_epi32(si128, *(__m128i *)&v28[48]);\n if (*(int *)&v28[96] < *(int *)&v28[100]) v5 = *(uint32_t *)&v28[100];\n v7 = _mm_or_si128(_mm_andnot_si128(v6, *(__m128i *)&v28[48]),\n _mm_and_si128(si128, v6));\n v8 = _mm_load_si128((const __m128i *)&v28[16]);\n v9 = _mm_cmpgt_epi32(v8, *(__m128i *)v28);\n v10 = _mm_or_si128(_mm_andnot_si128(v9, *(__m128i *)v28),\n _mm_and_si128(v8, v9));\n v11 = _mm_cmpgt_epi32(v7, v10);\n v12 = _mm_and_si128(v7, v11);\n v13 = _mm_andnot_si128(v11, v10);\n v14 = _mm_load_si128((const __m128i *)&v28[80]);\n v15 = _mm_or_si128(v13, v12);\n v16 = _mm_cmpgt_epi32(v14, *(__m128i *)&v28[64]);\n v17 = _mm_or_si128(_mm_andnot_si128(v16, *(__m128i *)&v28[64]),\n _mm_and_si128(v14, v16));\n v18 = _mm_and_si128(v17, _mm_cmpgt_epi32(v17, (__m128i)0LL));\n v19 = _mm_cmpgt_epi32(v15, v18);\n v20 = _mm_or_si128(_mm_andnot_si128(v19, v18), _mm_and_si128(v15, v19));\n v21 = _mm_srli_si128(v20, 8);\n v22 = _mm_cmpgt_epi32(v21, v20);\n v23 = _mm_or_si128(_mm_andnot_si128(v22, v20), _mm_and_si128(v21, v22));\n v24 = _mm_srli_si128(v23, 4);\n v25 = _mm_cmpgt_epi32(v24, v23);\n v26 = _mm_cvtsi128_si32(\n _mm_or_si128(_mm_andnot_si128(v25, v23), _mm_and_si128(v24, v25)));\n if (v5 < v26) v5 = v26;\n return (unsigned int)(v1 - v5);\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v1;\n long long v2;\n int v3;\n __m128i si128;\n int v5;\n __m128i v6;\n __m128i v7;\n __m128i v8;\n __m128i v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n __m128i v15;\n __m128i v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n __m128i v20;\n __m128i v21;\n __m128i v22;\n __m128i v23;\n __m128i v24;\n __m128i v25;\n int v26;\n uint8_t v28[104];\n unsigned long long v29;\n v29 = __readfsqword(40u);\n v1 = strlen(a1);\n memset(v28, 0, sizeof(v28));\n if (v1 > 0) {\n v2 = (long long)&a1[v1 - 1 + 1];\n do {\n v3 = *a1++;\n ++*(uint32_t *)&v28[4 * v3 - 388];\n } while (a1 != (const char *)v2);\n }\n si128 = _mm_load_si128((const __m128i *)&v28[32]);\n v5 = *(uint32_t *)&v28[96];\n v6 = _mm_cmpgt_epi32(si128, *(__m128i *)&v28[48]);\n if (*(int *)&v28[96] < *(int *)&v28[100]) v5 = *(uint32_t *)&v28[100];\n v7 = _mm_or_si128(_mm_andnot_si128(v6, *(__m128i *)&v28[48]),\n _mm_and_si128(si128, v6));\n v8 = _mm_load_si128((const __m128i *)&v28[16]);\n v9 = _mm_cmpgt_epi32(v8, *(__m128i *)v28);\n v10 = _mm_or_si128(_mm_andnot_si128(v9, *(__m128i *)v28),\n _mm_and_si128(v8, v9));\n v11 = _mm_cmpgt_epi32(v7, v10);\n v12 = _mm_and_si128(v7, v11);\n v13 = _mm_andnot_si128(v11, v10);\n v14 = _mm_load_si128((const __m128i *)&v28[80]);\n v15 = _mm_or_si128(v13, v12);\n v16 = _mm_cmpgt_epi32(v14, *(__m128i *)&v28[64]);\n v17 = _mm_or_si128(_mm_andnot_si128(v16, *(__m128i *)&v28[64]),\n _mm_and_si128(v14, v16));\n v18 = _mm_and_si128(v17, _mm_cmpgt_epi32(v17, (__m128i)0LL));\n v19 = _mm_cmpgt_epi32(v15, v18);\n v20 = _mm_or_si128(_mm_andnot_si128(v19, v18), _mm_and_si128(v15, v19));\n v21 = _mm_srli_si128(v20, 8);\n v22 = _mm_cmpgt_epi32(v21, v20);\n v23 = _mm_or_si128(_mm_andnot_si128(v22, v20), _mm_and_si128(v21, v22));\n v24 = _mm_srli_si128(v23, 4);\n v25 = _mm_cmpgt_epi32(v24, v23);\n v26 = _mm_cvtsi128_si32(\n _mm_or_si128(_mm_andnot_si128(v25, v23), _mm_and_si128(v24, v25)));\n if (v5 < v26) v5 = v26;\n return (unsigned int)(v1 - v5);\n}" + }, + { + "index": 351, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n, int k) {\n int count_map[256] = {0};\n int i;\n for (i = 0; i < n; i++) {\n count_map[arr[i]]++;\n }\n for (i = 0; i < n; i++) {\n if (count_map[arr[i]] == k) {\n return arr[i];\n }\n }\n return -1;\n}", + "test": "int main() {\n\n assert(func0((int[]){0,1,2,3,4,5},6,1) == 0);\n\n assert(func0((int[]){1,2,1,3,4},5,2) == 1);\n\n assert(func0((int[]){2,3,4,3,5,7,1,2,3,5},10,2) == 2);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x430,%rsp\nmov %rdi,-0x428(%rbp)\nmov %esi,-0x42c(%rbp)\nmov %edx,-0x430(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea -0x410(%rbp),%rdx\nmov $0x0,%eax\nmov $0x80,%ecx\nmov %rdx,%rdi\nrep stos %rax,%es:(%rdi)\nmovl $0x0,-0x414(%rbp)\njmp 11f6 \nmov -0x414(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x428(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmovslq %eax,%rdx\nmov -0x410(%rbp,%rdx,4),%edx\nadd $0x1,%edx\ncltq\nmov %edx,-0x410(%rbp,%rax,4)\naddl $0x1,-0x414(%rbp)\nmov -0x414(%rbp),%eax\ncmp -0x42c(%rbp),%eax\njl 11bd \nmovl $0x0,-0x414(%rbp)\njmp 1262 \nmov -0x414(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x428(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncltq\nmov -0x410(%rbp,%rax,4),%eax\ncmp %eax,-0x430(%rbp)\njne 125b \nmov -0x414(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x428(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\njmp 1275 \naddl $0x1,-0x414(%rbp)\nmov -0x414(%rbp),%eax\ncmp -0x42c(%rbp),%eax\njl 1210 \nmov $0xffffffff,%eax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 1289 \ncallq 1060 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 430h\nmov [rbp+var_428], rdi\nmov [rbp+var_42C], esi\nmov [rbp+var_430], edx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rdx, [rbp+var_410]\nmov eax, 0\nmov ecx, 80h\nmov rdi, rdx\nrep stosq\nmov [rbp+var_414], 0\njmp short loc_11F6\nloc_11BD:\nmov eax, [rbp+var_414]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_428]\nadd rax, rdx\nmov eax, [rax]\nmovsxd rdx, eax\nmov edx, [rbp+rdx*4+var_410]\nadd edx, 1\ncdqe\nmov [rbp+rax*4+var_410], edx\nadd [rbp+var_414], 1\nloc_11F6:\nmov eax, [rbp+var_414]\ncmp eax, [rbp+var_42C]\njl short loc_11BD\nmov [rbp+var_414], 0\njmp short loc_1262\nloc_1210:\nmov eax, [rbp+var_414]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_428]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nmov eax, [rbp+rax*4+var_410]\ncmp [rbp+var_430], eax\njnz short loc_125B\nmov eax, [rbp+var_414]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_428]\nadd rax, rdx\nmov eax, [rax]\njmp short loc_1275\nloc_125B:\nadd [rbp+var_414], 1\nloc_1262:\nmov eax, [rbp+var_414]\ncmp eax, [rbp+var_42C]\njl short loc_1210\nmov eax, 0FFFFFFFFh\nloc_1275:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1289\ncall ___stack_chk_fail\nlocret_1289:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n int i; // [rsp+1Ch] [rbp-414h]\n int j; // [rsp+1Ch] [rbp-414h]\n _DWORD v6[258]; // [rsp+20h] [rbp-410h] BYREF\n unsigned __int64 v7; // [rsp+428h] [rbp-8h]\n\n v7 = __readfsqword(0x28u);\n memset(v6, 0, 0x400uLL);\n for ( i = 0; i < a2; ++i )\n ++v6[*(int *)(4LL * i + a1)];\n for ( j = 0; j < a2; ++j )\n {\n if ( a3 == v6[*(int *)(4LL * j + a1)] )\n return *(unsigned int *)(4LL * j + a1);\n }\n return 0xFFFFFFFFLL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 430h\nmov [rbp+var_428], rdi\nmov [rbp+var_42C], esi\nmov [rbp+var_430], edx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rdx, [rbp+var_410]\nmov eax, 0\nmov ecx, 80h\nmov rdi, rdx\nrep stosq\nmov [rbp+var_414], 0\njmp short loc_11F6\nloc_11BD:\nmov eax, [rbp+var_414]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_428]\nadd rax, rdx\nmov eax, [rax]\nmovsxd rdx, eax\nmov edx, [rbp+rdx*4+var_410]\nadd edx, 1\ncdqe\nmov [rbp+rax*4+var_410], edx\nadd [rbp+var_414], 1\nloc_11F6:\nmov eax, [rbp+var_414]\ncmp eax, [rbp+var_42C]\njl short loc_11BD\nmov [rbp+var_414], 0\njmp short loc_1262\nloc_1210:\nmov eax, [rbp+var_414]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_428]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nmov eax, [rbp+rax*4+var_410]\ncmp [rbp+var_430], eax\njnz short loc_125B\nmov eax, [rbp+var_414]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_428]\nadd rax, rdx\nmov eax, [rax]\njmp short loc_1275\nloc_125B:\nadd [rbp+var_414], 1\nloc_1262:\nmov eax, [rbp+var_414]\ncmp eax, [rbp+var_42C]\njl short loc_1210\nmov eax, 0FFFFFFFFh\nloc_1275:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1289\ncall ___stack_chk_fail\nlocret_1289:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n int i; // [rsp+1Ch] [rbp-414h]\n int j; // [rsp+1Ch] [rbp-414h]\n _DWORD v6[258]; // [rsp+20h] [rbp-410h] BYREF\n unsigned __int64 v7; // [rsp+428h] [rbp-8h]\n\n v7 = __readfsqword(0x28u);\n memset(v6, 0, 0x400uLL);\n for ( i = 0; i < a2; ++i )\n ++v6[*(int *)(4LL * i + a1)];\n for ( j = 0; j < a2; ++j )\n {\n if ( a3 == v6[*(int *)(4LL * j + a1)] )\n return *(unsigned int *)(4LL * j + a1);\n }\n return 0xFFFFFFFFLL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n int i;\n int j;\n uint32_t v6[258];\n unsigned long long v7;\n v7 = __readfsqword(40u);\n memset(v6, 0, 1024uLL);\n for (i = 0; i < a2; ++i) ++v6[*(int *)(4LL * i + a1)];\n for (j = 0; j < a2; ++j) {\n if (a3 == v6[*(int *)(4LL * j + a1)])\n return *(unsigned int *)(4LL * j + a1);\n }\n return 4294967295LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n int i;\n int j;\n uint32_t v6[258];\n unsigned long long v7;\n v7 = __readfsqword(40u);\n memset(v6, 0, 1024uLL);\n for (i = 0; i < a2; ++i) ++v6[*(int *)(4LL * i + a1)];\n for (j = 0; j < a2; ++j) {\n if (a3 == v6[*(int *)(4LL * j + a1)])\n return *(unsigned int *)(4LL * j + a1);\n }\n return 4294967295LL;\n}" + }, + { + "index": 351, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n, int k) {\n int count_map[256] = {0};\n int i;\n for (i = 0; i < n; i++) {\n count_map[arr[i]]++;\n }\n for (i = 0; i < n; i++) {\n if (count_map[arr[i]] == k) {\n return arr[i];\n }\n }\n return -1;\n}", + "test": "int main() {\n\n assert(func0((int[]){0,1,2,3,4,5},6,1) == 0);\n\n assert(func0((int[]){1,2,1,3,4},5,2) == 1);\n\n assert(func0((int[]){2,3,4,3,5,7,1,2,3,5},10,2) == 2);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x418,%rsp\nmov %rdi,%r8\nmov %fs:0x28,%rax\nmov %rax,0x408(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nmov $0x80,%ecx\nrep stos %rax,%es:(%rdi)\ntest %esi,%esi\njle 11ec \nmov %r8,%rax\nlea -0x1(%rsi),%ecx\nlea 0x4(%r8,%rcx,4),%r9\nmov %r8,%rdi\nmovslq (%rdi),%rcx\naddl $0x1,(%rsp,%rcx,4)\nadd $0x4,%rdi\ncmp %r9,%rdi\njne 11a7 \nmov (%rax),%ecx\nmovslq %ecx,%rsi\ncmp %edx,(%rsp,%rsi,4)\nje 11cf \nadd $0x4,%rax\ncmp %r9,%rax\njne 11b7 \nmov $0xffffffff,%ecx\nmov 0x408(%rsp),%rax\nxor %fs:0x28,%rax\njne 11f3 \nmov %ecx,%eax\nadd $0x418,%rsp\nretq\nmov $0xffffffff,%ecx\njmp 11cf \ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 418h\nmov r8, rdi\nmov rax, fs:28h\nmov [rsp+418h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nmov ecx, 80h\nrep stosq\ntest esi, esi\njle short loc_11ED\nmov r9d, edx\nmov rdx, r8\nmovsxd rsi, esi\nlea rsi, [r8+rsi*4]\nmov rax, r8\nloc_11A9:\nmovsxd rcx, dword ptr [rax]\nadd [rsp+rcx*4+418h+var_418], 1\nadd rax, 4\ncmp rax, rsi\njnz short loc_11A9\nloc_11B9:\nmov eax, [rdx]\nmovsxd rcx, eax\ncmp [rsp+rcx*4+418h+var_418], r9d\njz short loc_11D2\nadd rdx, 4\ncmp rdx, rsi\njnz short loc_11B9\nmov eax, 0FFFFFFFFh\nloc_11D2:\nmov rdx, [rsp+418h+var_10]\nsub rdx, fs:28h\njnz short loc_11F4\nadd rsp, 418h\nretn\nloc_11ED:\nmov eax, 0FFFFFFFFh\njmp short loc_11D2\nloc_11F4:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2, int a3)\n{\n unsigned int *v4; // rdx\n int *v5; // rsi\n int *v6; // rax\n __int64 result; // rax\n _DWORD v8[258]; // [rsp+0h] [rbp-418h] BYREF\n unsigned __int64 v9; // [rsp+408h] [rbp-10h]\n\n v9 = __readfsqword(0x28u);\n memset(v8, 0, 0x400uLL);\n if ( a2 <= 0 )\n return 0xFFFFFFFFLL;\n v4 = (unsigned int *)a1;\n v5 = &a1[a2];\n v6 = a1;\n do\n ++v8[*v6++];\n while ( v6 != v5 );\n while ( 1 )\n {\n result = *v4;\n if ( v8[(int)result] == a3 )\n break;\n if ( ++v4 == (unsigned int *)v5 )\n return 0xFFFFFFFFLL;\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nsub rsp, 418h\nmov r8, rdi\nmov rax, fs:28h\nmov [rsp+418h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nmov ecx, 80h\nrep stosq\ntest esi, esi\njle short loc_11ED\nmov r9d, edx\nmov rdx, r8\nmovsxd rsi, esi\nlea rsi, [r8+rsi*4]\nmov rax, r8\nloc_11A9:\nmovsxd rcx, dword ptr [rax]\nadd [rsp+rcx*4+418h+var_418], 1\nadd rax, 4\ncmp rax, rsi\njnz short loc_11A9\nloc_11B9:\nmov eax, [rdx]\nmovsxd rcx, eax\ncmp [rsp+rcx*4+418h+var_418], r9d\njz short loc_11D2\nadd rdx, 4\ncmp rdx, rsi\njnz short loc_11B9\nmov eax, 0FFFFFFFFh\nloc_11D2:\nmov rdx, [rsp+418h+var_10]\nsub rdx, fs:28h\njnz short loc_11F4\nadd rsp, 418h\nretn\nloc_11ED:\nmov eax, 0FFFFFFFFh\njmp short loc_11D2\nloc_11F4:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int *a1, int a2, int a3)\n{\n unsigned int *v4; // rdx\n int *v5; // rsi\n int *v6; // rax\n __int64 result; // rax\n _DWORD v8[258]; // [rsp+0h] [rbp-418h] BYREF\n unsigned __int64 v9; // [rsp+408h] [rbp-10h]\n\n v9 = __readfsqword(0x28u);\n memset(v8, 0, 0x400uLL);\n if ( a2 <= 0 )\n return 0xFFFFFFFFLL;\n v4 = (unsigned int *)a1;\n v5 = &a1[a2];\n v6 = a1;\n do\n ++v8[*v6++];\n while ( v6 != v5 );\n while ( 1 )\n {\n result = *v4;\n if ( v8[(int)result] == a3 )\n break;\n if ( ++v4 == (unsigned int *)v5 )\n return 0xFFFFFFFFLL;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int *a1, int a2, int a3) {\n unsigned int *v4;\n int *v5;\n int *v6;\n long long result;\n uint32_t v8[258];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n memset(v8, 0, 1024uLL);\n if (a2 <= 0) return 4294967295LL;\n v4 = (unsigned int *)a1;\n v5 = &a1[a2];\n v6 = a1;\n do\n ++v8[*v6++];\n while (v6 != v5);\n while (1) {\n result = *v4;\n if (v8[(int)result] == a3) break;\n if (++v4 == (unsigned int *)v5) return 4294967295LL;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2, int a3) {\n unsigned int *v4;\n int *v5;\n int *v6;\n long long result;\n uint32_t v8[258];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n memset(v8, 0, 1024uLL);\n if (a2 <= 0) return 4294967295LL;\n v4 = (unsigned int *)a1;\n v5 = &a1[a2];\n v6 = a1;\n do\n ++v8[*v6++];\n while (v6 != v5);\n while (1) {\n result = *v4;\n if (v8[(int)result] == a3) break;\n if (++v4 == (unsigned int *)v5) return 4294967295LL;\n }\n return result;\n}" + }, + { + "index": 351, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n, int k) {\n int count_map[256] = {0};\n int i;\n for (i = 0; i < n; i++) {\n count_map[arr[i]]++;\n }\n for (i = 0; i < n; i++) {\n if (count_map[arr[i]] == k) {\n return arr[i];\n }\n }\n return -1;\n}", + "test": "int main() {\n\n assert(func0((int[]){0,1,2,3,4,5},6,1) == 0);\n\n assert(func0((int[]){1,2,1,3,4},5,2) == 1);\n\n assert(func0((int[]){2,3,4,3,5,7,1,2,3,5},10,2) == 2);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x418,%rsp\nmov %rdi,%r8\nmov $0x80,%ecx\nmov %fs:0x28,%rax\nmov %rax,0x408(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nrep stos %rax,%es:(%rdi)\ntest %esi,%esi\njle 1370 \nlea -0x1(%rsi),%eax\nmov %r8,%rdi\nlea 0x4(%r8,%rax,4),%rsi\nmov %r8,%rax\nxchg %ax,%ax\nmovslq (%rax),%rcx\nadd $0x4,%rax\naddl $0x1,(%rsp,%rcx,4)\ncmp %rsi,%rax\njne 1320 \nmovslq (%rdi),%rcx\nmov %rcx,%rax\ncmp %edx,(%rsp,%rcx,4)\nje 1354 \nnopl 0x0(%rax,%rax,1)\nadd $0x4,%rdi\ncmp %rsi,%rdi\nje 1370 \nmovslq (%rdi),%rcx\nmov %rcx,%rax\ncmp %edx,(%rsp,%rcx,4)\njne 1340 \nmov 0x408(%rsp),%rdx\nxor %fs:0x28,%rdx\njne 1377 \nadd $0x418,%rsp\nretq\nmov $0xffffffff,%eax\njmp 1354 \ncallq 1060 <__stack_chk_fail@plt>\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 418h\nmov r8, rdi\nmov ecx, 80h\nmov rax, fs:28h\nmov [rsp+418h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\ntest esi, esi\njle short loc_1340\nmovsxd rsi, esi\nmov r9d, edx\nmov rdi, r8\nmov rax, r8\nlea rcx, [r8+rsi*4]\nloc_12F0:\nmovsxd rdx, dword ptr [rax]\nadd rax, 4\nadd [rsp+rdx*4+418h+var_418], 1\ncmp rax, rcx\njnz short loc_12F0\nmovsxd rdx, dword ptr [rdi]\nmov rax, rdx\ncmp [rsp+rdx*4+418h+var_418], r9d\njz short loc_1325\nnop dword ptr [rax+00h]\nloc_1310:\nadd rdi, 4\ncmp rdi, rcx\njz short loc_1340\nmovsxd rdx, dword ptr [rdi]\nmov rax, rdx\ncmp [rsp+rdx*4+418h+var_418], r9d\njnz short loc_1310\nloc_1325:\nmov rdx, [rsp+418h+var_10]\nsub rdx, fs:28h\njnz short loc_1347\nadd rsp, 418h\nretn\nloc_1340:\nmov eax, 0FFFFFFFFh\njmp short loc_1325\nloc_1347:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2, int a3)\n{\n int *v4; // rax\n int *v5; // rcx\n __int64 v6; // rdx\n __int64 result; // rax\n _DWORD v8[258]; // [rsp+0h] [rbp-418h] BYREF\n unsigned __int64 v9; // [rsp+408h] [rbp-10h]\n\n v9 = __readfsqword(0x28u);\n memset(v8, 0, 0x400uLL);\n if ( a2 <= 0 )\n return 0xFFFFFFFFLL;\n v4 = a1;\n v5 = &a1[a2];\n do\n {\n v6 = *v4++;\n ++v8[v6];\n }\n while ( v4 != v5 );\n result = *a1;\n if ( v8[result] != a3 )\n {\n while ( ++a1 != v5 )\n {\n result = *a1;\n if ( v8[result] == a3 )\n return result;\n }\n return 0xFFFFFFFFLL;\n }\n return result;\n}", + "ida_strip_asm": "sub_12B0:\nendbr64\nsub rsp, 418h\nmov r8, rdi\nmov ecx, 80h\nmov rax, fs:28h\nmov [rsp+418h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\ntest esi, esi\njle short loc_1340\nmovsxd rsi, esi\nmov r9d, edx\nmov rdi, r8\nmov rax, r8\nlea rcx, [r8+rsi*4]\nloc_12F0:\nmovsxd rdx, dword ptr [rax]\nadd rax, 4\nadd [rsp+rdx*4+418h+var_418], 1\ncmp rax, rcx\njnz short loc_12F0\nmovsxd rdx, dword ptr [rdi]\nmov rax, rdx\ncmp [rsp+rdx*4+418h+var_418], r9d\njz short loc_1325\nnop dword ptr [rax+00h]\nloc_1310:\nadd rdi, 4\ncmp rdi, rcx\njz short loc_1340\nmovsxd rdx, dword ptr [rdi]\nmov rax, rdx\ncmp [rsp+rdx*4+418h+var_418], r9d\njnz short loc_1310\nloc_1325:\nmov rdx, [rsp+418h+var_10]\nsub rdx, fs:28h\njnz short loc_1347\nadd rsp, 418h\nretn\nloc_1340:\nmov eax, 0FFFFFFFFh\njmp short loc_1325\nloc_1347:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12B0(int *a1, int a2, int a3)\n{\n int *v4; // rax\n int *v5; // rcx\n __int64 v6; // rdx\n __int64 result; // rax\n _DWORD v8[258]; // [rsp+0h] [rbp-418h] BYREF\n unsigned __int64 v9; // [rsp+408h] [rbp-10h]\n\n v9 = __readfsqword(0x28u);\n memset(v8, 0, 0x400uLL);\n if ( a2 <= 0 )\n return 0xFFFFFFFFLL;\n v4 = a1;\n v5 = &a1[a2];\n do\n {\n v6 = *v4++;\n ++v8[v6];\n }\n while ( v4 != v5 );\n result = *a1;\n if ( v8[result] != a3 )\n {\n while ( ++a1 != v5 )\n {\n result = *a1;\n if ( v8[result] == a3 )\n return result;\n }\n return 0xFFFFFFFFLL;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12B0(int *a1, int a2, int a3) {\n int *v4;\n int *v5;\n long long v6;\n long long result;\n uint32_t v8[258];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n memset(v8, 0, 1024uLL);\n if (a2 <= 0) return 4294967295LL;\n v4 = a1;\n v5 = &a1[a2];\n do {\n v6 = *v4++;\n ++v8[v6];\n } while (v4 != v5);\n result = *a1;\n if (v8[result] != a3) {\n while (++a1 != v5) {\n result = *a1;\n if (v8[result] == a3) return result;\n }\n return 4294967295LL;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2, int a3) {\n int *v4;\n int *v5;\n long long v6;\n long long result;\n uint32_t v8[258];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n memset(v8, 0, 1024uLL);\n if (a2 <= 0) return 4294967295LL;\n v4 = a1;\n v5 = &a1[a2];\n do {\n v6 = *v4++;\n ++v8[v6];\n } while (v4 != v5);\n result = *a1;\n if (v8[result] != a3) {\n while (++a1 != v5) {\n result = *a1;\n if (v8[result] == a3) return result;\n }\n return 4294967295LL;\n }\n return result;\n}" + }, + { + "index": 351, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n, int k) {\n int count_map[256] = {0};\n int i;\n for (i = 0; i < n; i++) {\n count_map[arr[i]]++;\n }\n for (i = 0; i < n; i++) {\n if (count_map[arr[i]] == k) {\n return arr[i];\n }\n }\n return -1;\n}", + "test": "int main() {\n\n assert(func0((int[]){0,1,2,3,4,5},6,1) == 0);\n\n assert(func0((int[]){1,2,1,3,4},5,2) == 1);\n\n assert(func0((int[]){2,3,4,3,5,7,1,2,3,5},10,2) == 2);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x418,%rsp\nmov %rdi,%r8\nmov $0x80,%ecx\nmov %fs:0x28,%rax\nmov %rax,0x408(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nrep stos %rax,%es:(%rdi)\ntest %esi,%esi\njle 1340 \nlea -0x1(%rsi),%eax\nmov %r8,%rdi\nlea 0x4(%r8,%rax,4),%rsi\nmov %r8,%rax\nxchg %ax,%ax\nmovslq (%rax),%rcx\nadd $0x4,%rax\naddl $0x1,(%rsp,%rcx,4)\ncmp %rsi,%rax\njne 12f0 \nmovslq (%rdi),%rcx\nmov %rcx,%rax\ncmp %edx,(%rsp,%rcx,4)\nje 1324 \nnopl 0x0(%rax,%rax,1)\nadd $0x4,%rdi\ncmp %rsi,%rdi\nje 1340 \nmovslq (%rdi),%rcx\nmov %rcx,%rax\ncmp %edx,(%rsp,%rcx,4)\njne 1310 \nmov 0x408(%rsp),%rdx\nxor %fs:0x28,%rdx\njne 1347 \nadd $0x418,%rsp\nretq\nmov $0xffffffff,%eax\njmp 1324 \ncallq 1060 <__stack_chk_fail@plt>\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 418h\nmov r8, rdi\nmov ecx, 80h\nmov rax, fs:28h\nmov [rsp+418h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\ntest esi, esi\njle short loc_1340\nmovsxd rsi, esi\nmov r9d, edx\nmov rdi, r8\nmov rax, r8\nlea rcx, [r8+rsi*4]\nloc_12F0:\nmovsxd rdx, dword ptr [rax]\nadd rax, 4\nadd [rsp+rdx*4+418h+var_418], 1\ncmp rax, rcx\njnz short loc_12F0\nmovsxd rdx, dword ptr [rdi]\nmov rax, rdx\ncmp [rsp+rdx*4+418h+var_418], r9d\njz short loc_1325\nnop dword ptr [rax+00h]\nloc_1310:\nadd rdi, 4\ncmp rdi, rcx\njz short loc_1340\nmovsxd rdx, dword ptr [rdi]\nmov rax, rdx\ncmp [rsp+rdx*4+418h+var_418], r9d\njnz short loc_1310\nloc_1325:\nmov rdx, [rsp+418h+var_10]\nsub rdx, fs:28h\njnz short loc_1347\nadd rsp, 418h\nretn\nloc_1340:\nmov eax, 0FFFFFFFFh\njmp short loc_1325\nloc_1347:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2, int a3)\n{\n int *v4; // rax\n int *v5; // rcx\n __int64 v6; // rdx\n __int64 result; // rax\n _DWORD v8[258]; // [rsp+0h] [rbp-418h] BYREF\n unsigned __int64 v9; // [rsp+408h] [rbp-10h]\n\n v9 = __readfsqword(0x28u);\n memset(v8, 0, 0x400uLL);\n if ( a2 <= 0 )\n return 0xFFFFFFFFLL;\n v4 = a1;\n v5 = &a1[a2];\n do\n {\n v6 = *v4++;\n ++v8[v6];\n }\n while ( v4 != v5 );\n result = *a1;\n if ( v8[result] != a3 )\n {\n while ( ++a1 != v5 )\n {\n result = *a1;\n if ( v8[result] == a3 )\n return result;\n }\n return 0xFFFFFFFFLL;\n }\n return result;\n}", + "ida_strip_asm": "sub_12B0:\nendbr64\nsub rsp, 418h\nmov r8, rdi\nmov ecx, 80h\nmov rax, fs:28h\nmov [rsp+418h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\ntest esi, esi\njle short loc_1340\nmovsxd rsi, esi\nmov r9d, edx\nmov rdi, r8\nmov rax, r8\nlea rcx, [r8+rsi*4]\nloc_12F0:\nmovsxd rdx, dword ptr [rax]\nadd rax, 4\nadd [rsp+rdx*4+418h+var_418], 1\ncmp rax, rcx\njnz short loc_12F0\nmovsxd rdx, dword ptr [rdi]\nmov rax, rdx\ncmp [rsp+rdx*4+418h+var_418], r9d\njz short loc_1325\nnop dword ptr [rax+00h]\nloc_1310:\nadd rdi, 4\ncmp rdi, rcx\njz short loc_1340\nmovsxd rdx, dword ptr [rdi]\nmov rax, rdx\ncmp [rsp+rdx*4+418h+var_418], r9d\njnz short loc_1310\nloc_1325:\nmov rdx, [rsp+418h+var_10]\nsub rdx, fs:28h\njnz short loc_1347\nadd rsp, 418h\nretn\nloc_1340:\nmov eax, 0FFFFFFFFh\njmp short loc_1325\nloc_1347:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12B0(int *a1, int a2, int a3)\n{\n int *v4; // rax\n int *v5; // rcx\n __int64 v6; // rdx\n __int64 result; // rax\n _DWORD v8[258]; // [rsp+0h] [rbp-418h] BYREF\n unsigned __int64 v9; // [rsp+408h] [rbp-10h]\n\n v9 = __readfsqword(0x28u);\n memset(v8, 0, 0x400uLL);\n if ( a2 <= 0 )\n return 0xFFFFFFFFLL;\n v4 = a1;\n v5 = &a1[a2];\n do\n {\n v6 = *v4++;\n ++v8[v6];\n }\n while ( v4 != v5 );\n result = *a1;\n if ( v8[result] != a3 )\n {\n while ( ++a1 != v5 )\n {\n result = *a1;\n if ( v8[result] == a3 )\n return result;\n }\n return 0xFFFFFFFFLL;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12B0(int *a1, int a2, int a3) {\n int *v4;\n int *v5;\n long long v6;\n long long result;\n uint32_t v8[258];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n memset(v8, 0, 1024uLL);\n if (a2 <= 0) return 4294967295LL;\n v4 = a1;\n v5 = &a1[a2];\n do {\n v6 = *v4++;\n ++v8[v6];\n } while (v4 != v5);\n result = *a1;\n if (v8[result] != a3) {\n while (++a1 != v5) {\n result = *a1;\n if (v8[result] == a3) return result;\n }\n return 4294967295LL;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2, int a3) {\n int *v4;\n int *v5;\n long long v6;\n long long result;\n uint32_t v8[258];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n memset(v8, 0, 1024uLL);\n if (a2 <= 0) return 4294967295LL;\n v4 = a1;\n v5 = &a1[a2];\n do {\n v6 = *v4++;\n ++v8[v6];\n } while (v4 != v5);\n result = *a1;\n if (v8[result] != a3) {\n while (++a1 != v5) {\n result = *a1;\n if (v8[result] == a3) return result;\n }\n return 4294967295LL;\n }\n return result;\n}" + }, + { + "index": 352, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char* str) {\n for (int i = 0; i < strlen(str); i++) {\n for (int j = i + 1; j < strlen(str); j++) {\n if (str[i] == str[j]) {\n return false;\n }\n }\n }\n return true;\n}", + "test": "int main() {\n\n assert(func0(\"aba\") == false);\n\n assert(func0(\"abc\") == true);\n\n assert(func0(\"abab\") == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x28,%rsp\nmov %rdi,-0x28(%rbp)\nmovl $0x0,-0x18(%rbp)\njmp 11d8 \nmov -0x18(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x14(%rbp)\njmp 11bd \nmov -0x18(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%edx\nmov -0x14(%rbp),%eax\nmovslq %eax,%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmovzbl (%rax),%eax\ncmp %al,%dl\njne 11b9 \nmov $0x0,%eax\njmp 11f4 \naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\nmovslq %eax,%rbx\nmov -0x28(%rbp),%rax\nmov %rax,%rdi\ncallq 1060 \ncmp %rax,%rbx\njb 118e \naddl $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%eax\nmovslq %eax,%rbx\nmov -0x28(%rbp),%rax\nmov %rax,%rdi\ncallq 1060 \ncmp %rax,%rbx\njb 1183 \nmov $0x1,%eax\nadd $0x28,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+s], rdi\nmov [rbp+var_18], 0\njmp short loc_11D8\nloc_1183:\nmov eax, [rbp+var_18]\nadd eax, 1\nmov [rbp+var_14], eax\njmp short loc_11BD\nloc_118E:\nmov eax, [rbp+var_18]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_14]\nmovsxd rcx, eax\nmov rax, [rbp+s]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njnz short loc_11B9\nmov eax, 0\njmp short loc_11F4\nloc_11B9:\nadd [rbp+var_14], 1\nloc_11BD:\nmov eax, [rbp+var_14]\nmovsxd rbx, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rbx, rax\njb short loc_118E\nadd [rbp+var_18], 1\nloc_11D8:\nmov eax, [rbp+var_18]\nmovsxd rbx, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rbx, rax\njb short loc_1183\nmov eax, 1\nloc_11F4:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int i; // [rsp+18h] [rbp-18h]\n int j; // [rsp+1Ch] [rbp-14h]\n\n for ( i = 0; i < strlen(a1); ++i )\n {\n for ( j = i + 1; j < strlen(a1); ++j )\n {\n if ( a1[i] == a1[j] )\n return 0LL;\n }\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+s], rdi\nmov [rbp+var_18], 0\njmp short loc_11D8\nloc_1183:\nmov eax, [rbp+var_18]\nadd eax, 1\nmov [rbp+var_14], eax\njmp short loc_11BD\nloc_118E:\nmov eax, [rbp+var_18]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_14]\nmovsxd rcx, eax\nmov rax, [rbp+s]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njnz short loc_11B9\nmov eax, 0\njmp short loc_11F4\nloc_11B9:\nadd [rbp+var_14], 1\nloc_11BD:\nmov eax, [rbp+var_14]\nmovsxd rbx, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rbx, rax\njb short loc_118E\nadd [rbp+var_18], 1\nloc_11D8:\nmov eax, [rbp+var_18]\nmovsxd rbx, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rbx, rax\njb short loc_1183\nmov eax, 1\nloc_11F4:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1)\n{\n int i; // [rsp+18h] [rbp-18h]\n int j; // [rsp+1Ch] [rbp-14h]\n\n for ( i = 0; i < strlen(a1); ++i )\n {\n for ( j = i + 1; j < strlen(a1); ++j )\n {\n if ( a1[i] == a1[j] )\n return 0LL;\n }\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1) {\n int i;\n int j;\n for (i = 0; i < strlen(a1); ++i) {\n for (j = i + 1; j < strlen(a1); ++j) {\n if (a1[i] == a1[j]) return 0LL;\n }\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int i;\n int j;\n for (i = 0; i < strlen(a1); ++i) {\n for (j = i + 1; j < strlen(a1); ++j) {\n if (a1[i] == a1[j]) return 0LL;\n }\n }\n return 1LL;\n}" + }, + { + "index": 352, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char* str) {\n for (int i = 0; i < strlen(str); i++) {\n for (int j = i + 1; j < strlen(str); j++) {\n if (str[i] == str[j]) {\n return false;\n }\n }\n }\n return true;\n}", + "test": "int main() {\n\n assert(func0(\"aba\") == false);\n\n assert(func0(\"abc\") == true);\n\n assert(func0(\"abab\") == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%r8\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nlea -0x1(%rcx),%r9\nmov $0x1,%edi\nlea (%r8,%r9,1),%rsi\ncmp %rcx,%rdi\nje 1197 \ncmp %rdi,%r9\njbe 1191 \nmovzbl -0x1(%r8,%rdi,1),%edx\nmovslq %edi,%rax\nadd %r8,%rax\ncmp (%rax),%dl\nje 119d \nadd $0x1,%rax\ncmp %rsi,%rax\njne 1184 \nadd $0x1,%rdi\njmp 116e \nmov $0x1,%eax\nretq\nmov $0x0,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nlea r8, [rax+1]\nmov edi, 1\nlea rsi, [rbx+rax]\nloc_1183:\ncmp rdi, r8\njz short loc_11AB\ncmp rdi, rax\njnb short loc_11A5\nmovzx ecx, byte ptr [rbx+rdi-1]\nmovsxd rdx, edi\nadd rdx, rbx\nloc_1198:\ncmp cl, [rdx]\njz short loc_11B2\nadd rdx, 1\ncmp rdx, rsi\njnz short loc_1198\nloc_11A5:\nadd rdi, 1\njmp short loc_1183\nloc_11AB:\nmov eax, 1\njmp short loc_11B7\nloc_11B2:\nmov eax, 0\nloc_11B7:\npop rbx\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n size_t v2; // rax\n unsigned __int64 i; // rdi\n const char *v4; // rdx\n\n v2 = strlen(a1);\n for ( i = 1LL; ; ++i )\n {\n if ( i == v2 + 1 )\n return 1LL;\n if ( i < v2 )\n break;\nLABEL_7:\n ;\n }\n v4 = &a1[(int)i];\n while ( a1[i - 1] != *v4 )\n {\n if ( ++v4 == &a1[v2] )\n goto LABEL_7;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nlea r8, [rax+1]\nmov edi, 1\nlea rsi, [rbx+rax]\nloc_1183:\ncmp rdi, r8\njz short loc_11AB\ncmp rdi, rax\njnb short loc_11A5\nmovzx ecx, byte ptr [rbx+rdi-1]\nmovsxd rdx, edi\nadd rdx, rbx\nloc_1198:\ncmp cl, [rdx]\njz short loc_11B2\nadd rdx, 1\ncmp rdx, rsi\njnz short loc_1198\nloc_11A5:\nadd rdi, 1\njmp short loc_1183\nloc_11AB:\nmov eax, 1\njmp short loc_11B7\nloc_11B2:\nmov eax, 0\nloc_11B7:\npop rbx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1)\n{\n size_t v2; // rax\n unsigned __int64 i; // rdi\n const char *v4; // rdx\n\n v2 = strlen(a1);\n for ( i = 1LL; ; ++i )\n {\n if ( i == v2 + 1 )\n return 1LL;\n if ( i < v2 )\n break;\nLABEL_7:\n ;\n }\n v4 = &a1[(int)i];\n while ( a1[i - 1] != *v4 )\n {\n if ( ++v4 == &a1[v2] )\n goto LABEL_7;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1) {\n unsigned int v2;\n unsigned long long i;\n const char *v4;\n v2 = strlen(a1);\n for (i = 1LL;; ++i) {\n if (i == v2 + 1) return 1LL;\n if (i < v2) break;\n LABEL_7:;\n }\n v4 = &a1[(int)i];\n while (a1[i - 1] != *v4) {\n if (++v4 == &a1[v2]) goto LABEL_7;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n unsigned int v2;\n unsigned long long i;\n const char *v4;\n v2 = strlen(a1);\n for (i = 1LL;; ++i) {\n if (i == v2 + 1) return 1LL;\n if (i < v2) break;\n LABEL_7:;\n }\n v4 = &a1[(int)i];\n while (a1[i - 1] != *v4) {\n if (++v4 == &a1[v2]) goto LABEL_7;\n }\n return 0LL;\n}" + }, + { + "index": 352, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char* str) {\n for (int i = 0; i < strlen(str); i++) {\n for (int j = i + 1; j < strlen(str); j++) {\n if (str[i] == str[j]) {\n return false;\n }\n }\n }\n return true;\n}", + "test": "int main() {\n\n assert(func0(\"aba\") == false);\n\n assert(func0(\"abc\") == true);\n\n assert(func0(\"abab\") == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\ncallq 1060 \nmov $0x1,%r8d\nlea 0x1(%rax),%rdi\nlea (%rbx,%rax,1),%rsi\ncmp %rdi,%r8\nje 1269 \ncmp %r8,%rax\njbe 1260 \nmovslq %r8d,%rdx\nmovzbl -0x1(%rbx,%r8,1),%ecx\nadd %rbx,%rdx\njmp 1251 \nnopl 0x0(%rax,%rax,1)\nadd $0x1,%rdx\ncmp %rsi,%rdx\nje 1260 \ncmp (%rdx),%cl\njne 1248 \nxor %eax,%eax\npop %rbx\nretq\nnopl 0x0(%rax)\nadd $0x1,%r8\ncmp %rdi,%r8\njne 1230 \nmov $0x1,%eax\npop %rbx\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmov r8d, 1\nlea rdi, [rax+1]\nlea rsi, [rbx+rax]\ncmp r8, rdi\njz short loc_1269\nloc_1230:\ncmp r8, rax\njnb short loc_1260\nmovsxd rdx, r8d\nmovzx ecx, byte ptr [rbx+r8-1]\nadd rdx, rbx\njmp short loc_1251\nloc_1248:\nadd rdx, 1\ncmp rdx, rsi\njz short loc_1260\nloc_1251:\ncmp cl, [rdx]\njnz short loc_1248\nxor eax, eax\npop rbx\nretn\nloc_1260:\nadd r8, 1\ncmp r8, rdi\njnz short loc_1230\nloc_1269:\nmov eax, 1\npop rbx\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n size_t v1; // rax\n unsigned __int64 v2; // r8\n const char *v3; // rdx\n\n v1 = strlen(a1);\n v2 = 1LL;\n if ( !v1 )\n return 1LL;\n while ( v2 >= v1 )\n {\nLABEL_7:\n if ( ++v2 == v1 + 1 )\n return 1LL;\n }\n v3 = &a1[(int)v2];\n while ( a1[v2 - 1] != *v3 )\n {\n if ( ++v3 == &a1[v1] )\n goto LABEL_7;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmov r8d, 1\nlea rdi, [rax+1]\nlea rsi, [rbx+rax]\ncmp r8, rdi\njz short loc_1269\nloc_1230:\ncmp r8, rax\njnb short loc_1260\nmovsxd rdx, r8d\nmovzx ecx, byte ptr [rbx+r8-1]\nadd rdx, rbx\njmp short loc_1251\nloc_1248:\nadd rdx, 1\ncmp rdx, rsi\njz short loc_1260\nloc_1251:\ncmp cl, [rdx]\njnz short loc_1248\nxor eax, eax\npop rbx\nretn\nloc_1260:\nadd r8, 1\ncmp r8, rdi\njnz short loc_1230\nloc_1269:\nmov eax, 1\npop rbx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(const char *a1)\n{\n size_t v1; // rax\n unsigned __int64 v2; // r8\n const char *v3; // rdx\n\n v1 = strlen(a1);\n v2 = 1LL;\n if ( !v1 )\n return 1LL;\n while ( v2 >= v1 )\n {\nLABEL_7:\n if ( ++v2 == v1 + 1 )\n return 1LL;\n }\n v3 = &a1[(int)v2];\n while ( a1[v2 - 1] != *v3 )\n {\n if ( ++v3 == &a1[v1] )\n goto LABEL_7;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(const char *a1) {\n unsigned int v1;\n unsigned long long v2;\n const char *v3;\n v1 = strlen(a1);\n v2 = 1LL;\n if (!v1) return 1LL;\n while (v2 >= v1) {\n LABEL_7:\n if (++v2 == v1 + 1) return 1LL;\n }\n v3 = &a1[(int)v2];\n while (a1[v2 - 1] != *v3) {\n if (++v3 == &a1[v1]) goto LABEL_7;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n unsigned int v1;\n unsigned long long v2;\n const char *v3;\n v1 = strlen(a1);\n v2 = 1LL;\n if (!v1) return 1LL;\n while (v2 >= v1) {\n LABEL_7:\n if (++v2 == v1 + 1) return 1LL;\n }\n v3 = &a1[(int)v2];\n while (a1[v2 - 1] != *v3) {\n if (++v3 == &a1[v1]) goto LABEL_7;\n }\n return 0LL;\n}" + }, + { + "index": 352, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char* str) {\n for (int i = 0; i < strlen(str); i++) {\n for (int j = i + 1; j < strlen(str); j++) {\n if (str[i] == str[j]) {\n return false;\n }\n }\n }\n return true;\n}", + "test": "int main() {\n\n assert(func0(\"aba\") == false);\n\n assert(func0(\"abc\") == true);\n\n assert(func0(\"abab\") == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\ncallq 1060 \nmov $0x1,%r8d\nlea 0x1(%rax),%rdi\nlea (%rbx,%rax,1),%rsi\ncmp %rdi,%r8\nje 1269 \ncmp %r8,%rax\njbe 1260 \nmovslq %r8d,%rdx\nmovzbl -0x1(%rbx,%r8,1),%ecx\nadd %rbx,%rdx\njmp 1251 \nnopl 0x0(%rax,%rax,1)\nadd $0x1,%rdx\ncmp %rsi,%rdx\nje 1260 \ncmp (%rdx),%cl\njne 1248 \nxor %eax,%eax\npop %rbx\nretq\nnopl 0x0(%rax)\nadd $0x1,%r8\ncmp %rdi,%r8\njne 1230 \nmov $0x1,%eax\npop %rbx\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmov r8d, 1\nlea rdi, [rax+1]\nlea rsi, [rbx+rax]\ncmp r8, rdi\njz short loc_1269\nloc_1230:\ncmp r8, rax\njnb short loc_1260\nmovsxd rdx, r8d\nmovzx ecx, byte ptr [rbx+r8-1]\nadd rdx, rbx\njmp short loc_1251\nloc_1248:\nadd rdx, 1\ncmp rdx, rsi\njz short loc_1260\nloc_1251:\ncmp cl, [rdx]\njnz short loc_1248\nxor eax, eax\npop rbx\nretn\nloc_1260:\nadd r8, 1\ncmp r8, rdi\njnz short loc_1230\nloc_1269:\nmov eax, 1\npop rbx\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n size_t v1; // rax\n unsigned __int64 v2; // r8\n const char *v3; // rdx\n\n v1 = strlen(a1);\n v2 = 1LL;\n if ( !v1 )\n return 1LL;\n while ( v2 >= v1 )\n {\nLABEL_7:\n if ( ++v2 == v1 + 1 )\n return 1LL;\n }\n v3 = &a1[(int)v2];\n while ( a1[v2 - 1] != *v3 )\n {\n if ( ++v3 == &a1[v1] )\n goto LABEL_7;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmov r8d, 1\nlea rdi, [rax+1]\nlea rsi, [rbx+rax]\ncmp r8, rdi\njz short loc_1269\nloc_1230:\ncmp r8, rax\njnb short loc_1260\nmovsxd rdx, r8d\nmovzx ecx, byte ptr [rbx+r8-1]\nadd rdx, rbx\njmp short loc_1251\nloc_1248:\nadd rdx, 1\ncmp rdx, rsi\njz short loc_1260\nloc_1251:\ncmp cl, [rdx]\njnz short loc_1248\nxor eax, eax\npop rbx\nretn\nloc_1260:\nadd r8, 1\ncmp r8, rdi\njnz short loc_1230\nloc_1269:\nmov eax, 1\npop rbx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(const char *a1)\n{\n size_t v1; // rax\n unsigned __int64 v2; // r8\n const char *v3; // rdx\n\n v1 = strlen(a1);\n v2 = 1LL;\n if ( !v1 )\n return 1LL;\n while ( v2 >= v1 )\n {\nLABEL_7:\n if ( ++v2 == v1 + 1 )\n return 1LL;\n }\n v3 = &a1[(int)v2];\n while ( a1[v2 - 1] != *v3 )\n {\n if ( ++v3 == &a1[v1] )\n goto LABEL_7;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(const char *a1) {\n unsigned int v1;\n unsigned long long v2;\n const char *v3;\n v1 = strlen(a1);\n v2 = 1LL;\n if (!v1) return 1LL;\n while (v2 >= v1) {\n LABEL_7:\n if (++v2 == v1 + 1) return 1LL;\n }\n v3 = &a1[(int)v2];\n while (a1[v2 - 1] != *v3) {\n if (++v3 == &a1[v1]) goto LABEL_7;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n unsigned int v1;\n unsigned long long v2;\n const char *v3;\n v1 = strlen(a1);\n v2 = 1LL;\n if (!v1) return 1LL;\n while (v2 >= v1) {\n LABEL_7:\n if (++v2 == v1 + 1) return 1LL;\n }\n v3 = &a1[(int)v2];\n while (a1[v2 - 1] != *v3) {\n if (++v3 == &a1[v1]) goto LABEL_7;\n }\n return 0LL;\n}" + }, + { + "index": 353, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int* data;\n\n int length;\n\n} Row;\n\n\n\n", + "func": "Row* func0(Row list1[], int num_rows, int n) {\n for (int i = 0; i < num_rows; i++) {\n if (n < list1[i].length) {\n for (int j = n; j < list1[i].length - 1; j++) {\n list1[i].data[j] = list1[i].data[j + 1];\n }\n list1[i].length -= 1;\n }\n }\n return list1;\n}", + "test": "int main() {\n\n // Test case 1\n\n {\n\n int row0[] = {1, 2, 3};\n\n int row1[] = {2, 4, 5};\n\n int row2[] = {1, 1, 1};\n\n Row list1[3];\n\n list1[0].data = row0;\n\n list1[0].length = 3;\n\n list1[1].data = row1;\n\n list1[1].length = 3;\n\n list1[2].data = row2;\n\n list1[2].length = 3;\n\n \n\n Row* result = func0(list1, 3, 0);\n\n \n\n int expected0[] = {2, 3};\n\n int expected1[] = {4, 5};\n\n int expected2[] = {1, 1};\n\n Row expected[3];\n\n expected[0].data = expected0;\n\n expected[0].length = 2;\n\n expected[1].data = expected1;\n\n expected[1].length = 2;\n\n expected[2].data = expected2;\n\n expected[2].length = 2;\n\n \n\n for(int i = 0; i < 3; i++) {\n\n assert(result[i].length == expected[i].length);\n\n assert(memcmp(result[i].data, expected[i].data, sizeof(int)*result[i].length) == 0);\n\n }\n\n }\n\n \n\n // Test case 2\n\n {\n\n int row0[] = {1, 2, 3};\n\n int row1[] = {-2, 4, -5};\n\n int row2[] = {1, -1, 1};\n\n Row list1[3];\n\n list1[0].data = row0;\n\n list1[0].length = 3;\n\n list1[1].data = row1;\n\n list1[1].length = 3;\n\n list1[2].data = row2;\n\n list1[2].length = 3;\n\n \n\n Row* result = func0(list1, 3, 2);\n\n \n\n int expected0[] = {1, 2};\n\n int expected1[] = {-2, 4};\n\n int expected2[] = {1, -1};\n\n Row expected[3];\n\n expected[0].data = expected0;\n\n expected[0].length = 2;\n\n expected[1].data = expected1;\n\n expected[1].length = 2;\n\n expected[2].data = expected2;\n\n expected[2].length = 2;\n\n \n\n for(int i = 0; i < 3; i++) {\n\n assert(result[i].length == expected[i].length);\n\n assert(memcmp(result[i].data, expected[i].data, sizeof(int)*result[i].length) == 0);\n\n }\n\n }\n\n \n\n // Test case 3\n\n {\n\n int row0[] = {1, 3};\n\n int row1[] = {5, 7};\n\n int row2[] = {1, 3};\n\n int row3[] = {13, 15, 17};\n\n int row4[] = {5, 7};\n\n int row5[] = {9, 11};\n\n Row list1[6];\n\n list1[0].data = row0;\n\n list1[0].length = 2;\n\n list1[1].data = row1;\n\n list1[1].length = 2;\n\n list1[2].data = row2;\n\n list1[2].length = 2;\n\n list1[3].data = row3;\n\n list1[3].length = 3;\n\n list1[4].data = row4;\n\n list1[4].length = 2;\n\n list1[5].data = row5;\n\n list1[5].length = 2;\n\n \n\n Row* result = func0(list1, 6, 0);\n\n \n\n int expected0[] = {3};\n\n int expected1[] = {7};\n\n int expected2[] = {3};\n\n int expected3[] = {15, 17};\n\n int expected4[] = {7};\n\n int expected5[] = {11};\n\n Row expected[6];\n\n expected[0].data = expected0;\n\n expected[0].length = 1;\n\n expected[1].data = expected1;\n\n expected[1].length = 1;\n\n expected[2].data = expected2;\n\n expected[2].length = 1;\n\n expected[3].data = expected3;\n\n expected[3].length = 2;\n\n expected[4].data = expected4;\n\n expected[4].length = 1;\n\n expected[5].data = expected5;\n\n expected[5].length = 1;\n\n \n\n for(int i = 0; i < 6; i++) {\n\n assert(result[i].length == expected[i].length);\n\n assert(memcmp(result[i].data, expected[i].data, sizeof(int)*result[i].length) == 0);\n\n }\n\n }\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmovl $0x0,-0x8(%rbp)\njmpq 1272 \nmov -0x8(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov 0x8(%rax),%eax\ncmp %eax,-0x20(%rbp)\njge 126e \nmov -0x20(%rbp),%eax\nmov %eax,-0x4(%rbp)\njmp 1221 \nmov -0x8(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0x4(%rbp),%edx\nmovslq %edx,%rdx\nadd $0x1,%rdx\nshl $0x2,%rdx\nadd %rdx,%rax\nmov -0x8(%rbp),%edx\nmovslq %edx,%rdx\nmov %rdx,%rcx\nshl $0x4,%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rdx),%rdx\nmov -0x4(%rbp),%ecx\nmovslq %ecx,%rcx\nshl $0x2,%rcx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x4(%rbp)\nmov -0x8(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov 0x8(%rax),%eax\nsub $0x1,%eax\ncmp %eax,-0x4(%rbp)\njl 11ce \nmov -0x8(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov 0x8(%rax),%edx\nmov -0x8(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nsub $0x1,%edx\nmov %edx,0x8(%rax)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11a7 \nmov -0x18(%rbp),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_8], 0\njmp loc_1272\nloc_11A7:\nmov eax, [rbp+var_8]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax+8]\ncmp [rbp+var_20], eax\njge loc_126E\nmov eax, [rbp+var_20]\nmov [rbp+var_4], eax\njmp short loc_1221\nloc_11CE:\nmov eax, [rbp+var_8]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nadd rdx, 1\nshl rdx, 2\nadd rax, rdx\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nmov rcx, rdx\nshl rcx, 4\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov rdx, [rdx]\nmov ecx, [rbp+var_4]\nmovsxd rcx, ecx\nshl rcx, 2\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_4], 1\nloc_1221:\nmov eax, [rbp+var_8]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax+8]\nsub eax, 1\ncmp [rbp+var_4], eax\njl short loc_11CE\nmov eax, [rbp+var_8]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax+8]\nmov eax, [rbp+var_8]\ncdqe\nshl rax, 4\nmov rcx, rax\nmov rax, [rbp+var_18]\nadd rax, rcx\nsub edx, 1\nmov [rax+8], edx\nloc_126E:\nadd [rbp+var_8], 1\nloc_1272:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl loc_11A7\nmov rax, [rbp+var_18]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n int i; // [rsp+18h] [rbp-8h]\n int j; // [rsp+1Ch] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n if ( a3 < *(_DWORD *)(16LL * i + a1 + 8) )\n {\n for ( j = a3; j < *(_DWORD *)(16LL * i + a1 + 8) - 1; ++j )\n *(_DWORD *)(4LL * j + *(_QWORD *)(16LL * i + a1)) = *(_DWORD *)(4 * (j + 1LL) + *(_QWORD *)(16LL * i + a1));\n --*(_DWORD *)(16LL * i + a1 + 8);\n }\n }\n return a1;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_8], 0\njmp loc_1272\nloc_11A7:\nmov eax, [rbp+var_8]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax+8]\ncmp [rbp+var_20], eax\njge loc_126E\nmov eax, [rbp+var_20]\nmov [rbp+var_4], eax\njmp short loc_1221\nloc_11CE:\nmov eax, [rbp+var_8]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nadd rdx, 1\nshl rdx, 2\nadd rax, rdx\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nmov rcx, rdx\nshl rcx, 4\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov rdx, [rdx]\nmov ecx, [rbp+var_4]\nmovsxd rcx, ecx\nshl rcx, 2\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_4], 1\nloc_1221:\nmov eax, [rbp+var_8]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax+8]\nsub eax, 1\ncmp [rbp+var_4], eax\njl short loc_11CE\nmov eax, [rbp+var_8]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax+8]\nmov eax, [rbp+var_8]\ncdqe\nshl rax, 4\nmov rcx, rax\nmov rax, [rbp+var_18]\nadd rax, rcx\nsub edx, 1\nmov [rax+8], edx\nloc_126E:\nadd [rbp+var_8], 1\nloc_1272:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl loc_11A7\nmov rax, [rbp+var_18]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2, int a3)\n{\n int i; // [rsp+18h] [rbp-8h]\n int j; // [rsp+1Ch] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n if ( a3 < *(_DWORD *)(16LL * i + a1 + 8) )\n {\n for ( j = a3; j < *(_DWORD *)(16LL * i + a1 + 8) - 1; ++j )\n *(_DWORD *)(4LL * j + *(_QWORD *)(16LL * i + a1)) = *(_DWORD *)(4 * (j + 1LL) + *(_QWORD *)(16LL * i + a1));\n --*(_DWORD *)(16LL * i + a1 + 8);\n }\n }\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2, int a3) {\n int i;\n int j;\n for (i = 0; i < a2; ++i) {\n if (a3 < *(uint32_t *)(16LL * i + a1 + 8)) {\n for (j = a3; j < *(uint32_t *)(16LL * i + a1 + 8) - 1; ++j)\n *(uint32_t *)(4LL * j + *(uint64_t *)(16LL * i + a1)) =\n *(uint32_t *)(4 * (j + 1LL) + *(uint64_t *)(16LL * i + a1));\n --*(uint32_t *)(16LL * i + a1 + 8);\n }\n }\n return a1;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n int i;\n int j;\n for (i = 0; i < a2; ++i) {\n if (a3 < *(uint32_t *)(16LL * i + a1 + 8)) {\n for (j = a3; j < *(uint32_t *)(16LL * i + a1 + 8) - 1; ++j)\n *(uint32_t *)(4LL * j + *(uint64_t *)(16LL * i + a1)) =\n *(uint32_t *)(4 * (j + 1LL) + *(uint64_t *)(16LL * i + a1));\n --*(uint32_t *)(16LL * i + a1 + 8);\n }\n }\n return a1;\n}" + }, + { + "index": 353, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int* data;\n\n int length;\n\n} Row;\n\n\n\n", + "func": "Row* func0(Row list1[], int num_rows, int n) {\n for (int i = 0; i < num_rows; i++) {\n if (n < list1[i].length) {\n for (int j = n; j < list1[i].length - 1; j++) {\n list1[i].data[j] = list1[i].data[j + 1];\n }\n list1[i].length -= 1;\n }\n }\n return list1;\n}", + "test": "int main() {\n\n // Test case 1\n\n {\n\n int row0[] = {1, 2, 3};\n\n int row1[] = {2, 4, 5};\n\n int row2[] = {1, 1, 1};\n\n Row list1[3];\n\n list1[0].data = row0;\n\n list1[0].length = 3;\n\n list1[1].data = row1;\n\n list1[1].length = 3;\n\n list1[2].data = row2;\n\n list1[2].length = 3;\n\n \n\n Row* result = func0(list1, 3, 0);\n\n \n\n int expected0[] = {2, 3};\n\n int expected1[] = {4, 5};\n\n int expected2[] = {1, 1};\n\n Row expected[3];\n\n expected[0].data = expected0;\n\n expected[0].length = 2;\n\n expected[1].data = expected1;\n\n expected[1].length = 2;\n\n expected[2].data = expected2;\n\n expected[2].length = 2;\n\n \n\n for(int i = 0; i < 3; i++) {\n\n assert(result[i].length == expected[i].length);\n\n assert(memcmp(result[i].data, expected[i].data, sizeof(int)*result[i].length) == 0);\n\n }\n\n }\n\n \n\n // Test case 2\n\n {\n\n int row0[] = {1, 2, 3};\n\n int row1[] = {-2, 4, -5};\n\n int row2[] = {1, -1, 1};\n\n Row list1[3];\n\n list1[0].data = row0;\n\n list1[0].length = 3;\n\n list1[1].data = row1;\n\n list1[1].length = 3;\n\n list1[2].data = row2;\n\n list1[2].length = 3;\n\n \n\n Row* result = func0(list1, 3, 2);\n\n \n\n int expected0[] = {1, 2};\n\n int expected1[] = {-2, 4};\n\n int expected2[] = {1, -1};\n\n Row expected[3];\n\n expected[0].data = expected0;\n\n expected[0].length = 2;\n\n expected[1].data = expected1;\n\n expected[1].length = 2;\n\n expected[2].data = expected2;\n\n expected[2].length = 2;\n\n \n\n for(int i = 0; i < 3; i++) {\n\n assert(result[i].length == expected[i].length);\n\n assert(memcmp(result[i].data, expected[i].data, sizeof(int)*result[i].length) == 0);\n\n }\n\n }\n\n \n\n // Test case 3\n\n {\n\n int row0[] = {1, 3};\n\n int row1[] = {5, 7};\n\n int row2[] = {1, 3};\n\n int row3[] = {13, 15, 17};\n\n int row4[] = {5, 7};\n\n int row5[] = {9, 11};\n\n Row list1[6];\n\n list1[0].data = row0;\n\n list1[0].length = 2;\n\n list1[1].data = row1;\n\n list1[1].length = 2;\n\n list1[2].data = row2;\n\n list1[2].length = 2;\n\n list1[3].data = row3;\n\n list1[3].length = 3;\n\n list1[4].data = row4;\n\n list1[4].length = 2;\n\n list1[5].data = row5;\n\n list1[5].length = 2;\n\n \n\n Row* result = func0(list1, 6, 0);\n\n \n\n int expected0[] = {3};\n\n int expected1[] = {7};\n\n int expected2[] = {3};\n\n int expected3[] = {15, 17};\n\n int expected4[] = {7};\n\n int expected5[] = {11};\n\n Row expected[6];\n\n expected[0].data = expected0;\n\n expected[0].length = 1;\n\n expected[1].data = expected1;\n\n expected[1].length = 1;\n\n expected[2].data = expected2;\n\n expected[2].length = 1;\n\n expected[3].data = expected3;\n\n expected[3].length = 2;\n\n expected[4].data = expected4;\n\n expected[4].length = 1;\n\n expected[5].data = expected5;\n\n expected[5].length = 1;\n\n \n\n for(int i = 0; i < 6; i++) {\n\n assert(result[i].length == expected[i].length);\n\n assert(memcmp(result[i].data, expected[i].data, sizeof(int)*result[i].length) == 0);\n\n }\n\n }\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11f6 \npush %rbx\nlea 0x8(%rdi),%r9\nlea -0x1(%rsi),%eax\nshl $0x4,%rax\nlea 0x18(%rdi,%rax,1),%r11\nmovslq %edx,%rax\nlea 0x4(,%rax,4),%rbx\njmp 11bb \nmov %eax,(%r8)\nadd $0x10,%r9\ncmp %r11,%r9\nje 11f1 \nmov %r9,%r8\nmov (%r9),%eax\ncmp %edx,%eax\njle 11b2 \nsub $0x1,%eax\ncmp %eax,%edx\njge 11af \nmov %rbx,%rcx\nmov %edx,%esi\nmov -0x8(%r8),%rax\nmov (%rax,%rcx,1),%r10d\nmov %r10d,-0x4(%rax,%rcx,1)\nadd $0x1,%esi\nmov (%r8),%eax\nsub $0x1,%eax\nadd $0x4,%rcx\ncmp %esi,%eax\njg 11d1 \njmp 11af \nmov %rdi,%rax\npop %rbx\nretq\nmov %rdi,%rax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov r10, rdi\ntest esi, esi\njle short loc_11F9\npush rbx\nmov r11d, edx\nmovsxd rsi, esi\nshl rsi, 4\nlea r9, [rsi+rdi]\nmovsxd rax, edx\nlea rbx, ds:4[rax*4]\njmp short loc_11BC\nloc_11B0:\nmov [rsi+8], eax\nloc_11B3:\nadd rdi, 10h\ncmp rdi, r9\njz short loc_11F4\nloc_11BC:\nmov rsi, rdi\nmov eax, [rdi+8]\ncmp eax, r11d\njle short loc_11B3\nsub eax, 1\ncmp r11d, eax\njge short loc_11B0\nmov rdx, rbx\nmov ecx, r11d\nloc_11D5:\nmov rax, [rsi]\nmov r8d, [rax+rdx]\nmov [rax+rdx-4], r8d\nadd ecx, 1\nmov eax, [rsi+8]\nsub eax, 1\nadd rdx, 4\ncmp eax, ecx\njg short loc_11D5\njmp short loc_11B0\nloc_11F4:\nmov rax, r10\npop rbx\nretn\nloc_11F9:\nmov rax, rdi\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n __int64 v3; // r10\n __int64 v5; // r9\n __int64 v6; // rbx\n int v7; // eax\n int v8; // eax\n __int64 v9; // rdx\n int v10; // ecx\n\n v3 = a1;\n if ( a2 <= 0 )\n return a1;\n v5 = 16LL * a2 + a1;\n v6 = 4LL * a3 + 4;\n do\n {\n v7 = *(_DWORD *)(a1 + 8);\n if ( v7 > a3 )\n {\n v8 = v7 - 1;\n if ( a3 < v8 )\n {\n v9 = v6;\n v10 = a3;\n do\n {\n *(_DWORD *)(*(_QWORD *)a1 + v9 - 4) = *(_DWORD *)(*(_QWORD *)a1 + v9);\n ++v10;\n v8 = *(_DWORD *)(a1 + 8) - 1;\n v9 += 4LL;\n }\n while ( v8 > v10 );\n }\n *(_DWORD *)(a1 + 8) = v8;\n }\n a1 += 16LL;\n }\n while ( a1 != v5 );\n return v3;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\nmov r10, rdi\ntest esi, esi\njle short loc_11F9\npush rbx\nmov r11d, edx\nmovsxd rsi, esi\nshl rsi, 4\nlea r9, [rsi+rdi]\nmovsxd rax, edx\nlea rbx, ds:4[rax*4]\njmp short loc_11BC\nloc_11B0:\nmov [rsi+8], eax\nloc_11B3:\nadd rdi, 10h\ncmp rdi, r9\njz short loc_11F4\nloc_11BC:\nmov rsi, rdi\nmov eax, [rdi+8]\ncmp eax, r11d\njle short loc_11B3\nsub eax, 1\ncmp r11d, eax\njge short loc_11B0\nmov rdx, rbx\nmov ecx, r11d\nloc_11D5:\nmov rax, [rsi]\nmov r8d, [rax+rdx]\nmov [rax+rdx-4], r8d\nadd ecx, 1\nmov eax, [rsi+8]\nsub eax, 1\nadd rdx, 4\ncmp eax, ecx\njg short loc_11D5\njmp short loc_11B0\nloc_11F4:\nmov rax, r10\npop rbx\nretn\nloc_11F9:\nmov rax, rdi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2, int a3)\n{\n __int64 v3; // r10\n __int64 v5; // r9\n __int64 v6; // rbx\n int v7; // eax\n int v8; // eax\n __int64 v9; // rdx\n int v10; // ecx\n\n v3 = a1;\n if ( a2 <= 0 )\n return a1;\n v5 = 16LL * a2 + a1;\n v6 = 4LL * a3 + 4;\n do\n {\n v7 = *(_DWORD *)(a1 + 8);\n if ( v7 > a3 )\n {\n v8 = v7 - 1;\n if ( a3 < v8 )\n {\n v9 = v6;\n v10 = a3;\n do\n {\n *(_DWORD *)(*(_QWORD *)a1 + v9 - 4) = *(_DWORD *)(*(_QWORD *)a1 + v9);\n ++v10;\n v8 = *(_DWORD *)(a1 + 8) - 1;\n v9 += 4LL;\n }\n while ( v8 > v10 );\n }\n *(_DWORD *)(a1 + 8) = v8;\n }\n a1 += 16LL;\n }\n while ( a1 != v5 );\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2, int a3) {\n long long v3;\n long long v5;\n long long v6;\n int v7;\n int v8;\n long long v9;\n int v10;\n v3 = a1;\n if (a2 <= 0) return a1;\n v5 = 16LL * a2 + a1;\n v6 = 4LL * a3 + 4;\n do {\n v7 = *(uint32_t *)(a1 + 8);\n if (v7 > a3) {\n v8 = v7 - 1;\n if (a3 < v8) {\n v9 = v6;\n v10 = a3;\n do {\n *(uint32_t *)(*(uint64_t *)a1 + v9 - 4) =\n *(uint32_t *)(*(uint64_t *)a1 + v9);\n ++v10;\n v8 = *(uint32_t *)(a1 + 8) - 1;\n v9 += 4LL;\n } while (v8 > v10);\n }\n *(uint32_t *)(a1 + 8) = v8;\n }\n a1 += 16LL;\n } while (a1 != v5);\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n long long v3;\n long long v5;\n long long v6;\n int v7;\n int v8;\n long long v9;\n int v10;\n v3 = a1;\n if (a2 <= 0) return a1;\n v5 = 16LL * a2 + a1;\n v6 = 4LL * a3 + 4;\n do {\n v7 = *(uint32_t *)(a1 + 8);\n if (v7 > a3) {\n v8 = v7 - 1;\n if (a3 < v8) {\n v9 = v6;\n v10 = a3;\n do {\n *(uint32_t *)(*(uint64_t *)a1 + v9 - 4) =\n *(uint32_t *)(*(uint64_t *)a1 + v9);\n ++v10;\n v8 = *(uint32_t *)(a1 + 8) - 1;\n v9 += 4LL;\n } while (v8 > v10);\n }\n *(uint32_t *)(a1 + 8) = v8;\n }\n a1 += 16LL;\n } while (a1 != v5);\n return v3;\n}" + }, + { + "index": 353, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int* data;\n\n int length;\n\n} Row;\n\n\n\n", + "func": "Row* func0(Row list1[], int num_rows, int n) {\n for (int i = 0; i < num_rows; i++) {\n if (n < list1[i].length) {\n for (int j = n; j < list1[i].length - 1; j++) {\n list1[i].data[j] = list1[i].data[j + 1];\n }\n list1[i].length -= 1;\n }\n }\n return list1;\n}", + "test": "int main() {\n\n // Test case 1\n\n {\n\n int row0[] = {1, 2, 3};\n\n int row1[] = {2, 4, 5};\n\n int row2[] = {1, 1, 1};\n\n Row list1[3];\n\n list1[0].data = row0;\n\n list1[0].length = 3;\n\n list1[1].data = row1;\n\n list1[1].length = 3;\n\n list1[2].data = row2;\n\n list1[2].length = 3;\n\n \n\n Row* result = func0(list1, 3, 0);\n\n \n\n int expected0[] = {2, 3};\n\n int expected1[] = {4, 5};\n\n int expected2[] = {1, 1};\n\n Row expected[3];\n\n expected[0].data = expected0;\n\n expected[0].length = 2;\n\n expected[1].data = expected1;\n\n expected[1].length = 2;\n\n expected[2].data = expected2;\n\n expected[2].length = 2;\n\n \n\n for(int i = 0; i < 3; i++) {\n\n assert(result[i].length == expected[i].length);\n\n assert(memcmp(result[i].data, expected[i].data, sizeof(int)*result[i].length) == 0);\n\n }\n\n }\n\n \n\n // Test case 2\n\n {\n\n int row0[] = {1, 2, 3};\n\n int row1[] = {-2, 4, -5};\n\n int row2[] = {1, -1, 1};\n\n Row list1[3];\n\n list1[0].data = row0;\n\n list1[0].length = 3;\n\n list1[1].data = row1;\n\n list1[1].length = 3;\n\n list1[2].data = row2;\n\n list1[2].length = 3;\n\n \n\n Row* result = func0(list1, 3, 2);\n\n \n\n int expected0[] = {1, 2};\n\n int expected1[] = {-2, 4};\n\n int expected2[] = {1, -1};\n\n Row expected[3];\n\n expected[0].data = expected0;\n\n expected[0].length = 2;\n\n expected[1].data = expected1;\n\n expected[1].length = 2;\n\n expected[2].data = expected2;\n\n expected[2].length = 2;\n\n \n\n for(int i = 0; i < 3; i++) {\n\n assert(result[i].length == expected[i].length);\n\n assert(memcmp(result[i].data, expected[i].data, sizeof(int)*result[i].length) == 0);\n\n }\n\n }\n\n \n\n // Test case 3\n\n {\n\n int row0[] = {1, 3};\n\n int row1[] = {5, 7};\n\n int row2[] = {1, 3};\n\n int row3[] = {13, 15, 17};\n\n int row4[] = {5, 7};\n\n int row5[] = {9, 11};\n\n Row list1[6];\n\n list1[0].data = row0;\n\n list1[0].length = 2;\n\n list1[1].data = row1;\n\n list1[1].length = 2;\n\n list1[2].data = row2;\n\n list1[2].length = 2;\n\n list1[3].data = row3;\n\n list1[3].length = 3;\n\n list1[4].data = row4;\n\n list1[4].length = 2;\n\n list1[5].data = row5;\n\n list1[5].length = 2;\n\n \n\n Row* result = func0(list1, 6, 0);\n\n \n\n int expected0[] = {3};\n\n int expected1[] = {7};\n\n int expected2[] = {3};\n\n int expected3[] = {15, 17};\n\n int expected4[] = {7};\n\n int expected5[] = {11};\n\n Row expected[6];\n\n expected[0].data = expected0;\n\n expected[0].length = 1;\n\n expected[1].data = expected1;\n\n expected[1].length = 1;\n\n expected[2].data = expected2;\n\n expected[2].length = 1;\n\n expected[3].data = expected3;\n\n expected[3].length = 2;\n\n expected[4].data = expected4;\n\n expected[4].length = 1;\n\n expected[5].data = expected5;\n\n expected[5].length = 1;\n\n \n\n for(int i = 0; i < 6; i++) {\n\n assert(result[i].length == expected[i].length);\n\n assert(memcmp(result[i].data, expected[i].data, sizeof(int)*result[i].length) == 0);\n\n }\n\n }\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%r10\ntest %esi,%esi\njle 17d1 \nlea -0x1(%rsi),%eax\nlea 0x8(%rdi),%r8\nshl $0x4,%rax\nlea 0x18(%rdi,%rax,1),%r9\njmp 1799 \nnopl (%rax)\nadd $0x10,%r8\ncmp %r9,%r8\nje 17d1 \nmov (%r8),%eax\ncmp %edx,%eax\njle 1790 \nsub $0x1,%eax\ncmp %eax,%edx\njge 17c5 \nmov -0x8(%r8),%rsi\nmovslq %edx,%rcx\nxchg %ax,%ax\nmov 0x4(%rsi,%rcx,4),%eax\nmov %eax,(%rsi,%rcx,4)\nmov (%r8),%eax\nadd $0x1,%rcx\nsub $0x1,%eax\ncmp %ecx,%eax\njg 17b0 \nmov %eax,(%r8)\nadd $0x10,%r8\ncmp %r9,%r8\njne 1799 \nmov %r10,%rax\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmov r9, rdi\ntest esi, esi\njle short loc_1791\nmovsxd rsi, esi\nshl rsi, 4\nlea r8, [rsi+rdi]\njmp short loc_1759\nloc_1750:\nadd rdi, 10h\ncmp r8, rdi\njz short loc_1791\nloc_1759:\nmov eax, [rdi+8]\ncmp eax, edx\njle short loc_1750\nsub eax, 1\ncmp edx, eax\njge short loc_1785\nmov rsi, [rdi]\nmovsxd rcx, edx\nnop dword ptr [rax]\nloc_1770:\nmov eax, [rsi+rcx*4+4]\nmov [rsi+rcx*4], eax\nmov eax, [rdi+8]\nadd rcx, 1\nsub eax, 1\ncmp eax, ecx\njg short loc_1770\nloc_1785:\nmov [rdi+8], eax\nadd rdi, 10h\ncmp r8, rdi\njnz short loc_1759\nloc_1791:\nmov rax, r9\nretn", + "ida_pseudo": "__int64 *__fastcall func0(__int64 *a1, int a2, int a3)\n{\n __int64 *v3; // r9\n __int64 *v4; // r8\n int v5; // eax\n int v6; // eax\n __int64 v7; // rsi\n __int64 v8; // rcx\n\n v3 = a1;\n if ( a2 > 0 )\n {\n v4 = &a1[2 * a2];\n do\n {\n while ( 1 )\n {\n v5 = *((_DWORD *)a1 + 2);\n if ( v5 > a3 )\n break;\n a1 += 2;\n if ( v4 == a1 )\n return v3;\n }\n v6 = v5 - 1;\n if ( a3 < v6 )\n {\n v7 = *a1;\n v8 = a3;\n do\n {\n *(_DWORD *)(v7 + 4 * v8) = *(_DWORD *)(v7 + 4 * v8 + 4);\n ++v8;\n v6 = *((_DWORD *)a1 + 2) - 1;\n }\n while ( v6 > (int)v8 );\n }\n *((_DWORD *)a1 + 2) = v6;\n a1 += 2;\n }\n while ( v4 != a1 );\n }\n return v3;\n}", + "ida_strip_asm": "sub_1730:\nendbr64\nmov r9, rdi\ntest esi, esi\njle short loc_1791\nmovsxd rsi, esi\nshl rsi, 4\nlea r8, [rsi+rdi]\njmp short loc_1759\nloc_1750:\nadd rdi, 10h\ncmp r8, rdi\njz short loc_1791\nloc_1759:\nmov eax, [rdi+8]\ncmp eax, edx\njle short loc_1750\nsub eax, 1\ncmp edx, eax\njge short loc_1785\nmov rsi, [rdi]\nmovsxd rcx, edx\nnop dword ptr [rax]\nloc_1770:\nmov eax, [rsi+rcx*4+4]\nmov [rsi+rcx*4], eax\nmov eax, [rdi+8]\nadd rcx, 1\nsub eax, 1\ncmp eax, ecx\njg short loc_1770\nloc_1785:\nmov [rdi+8], eax\nadd rdi, 10h\ncmp r8, rdi\njnz short loc_1759\nloc_1791:\nmov rax, r9\nretn", + "ida_strip_pseudo": "__int64 *__fastcall sub_1730(__int64 *a1, int a2, int a3)\n{\n __int64 *v3; // r9\n __int64 *v4; // r8\n int v5; // eax\n int v6; // eax\n __int64 v7; // rsi\n __int64 v8; // rcx\n\n v3 = a1;\n if ( a2 > 0 )\n {\n v4 = &a1[2 * a2];\n do\n {\n while ( 1 )\n {\n v5 = *((_DWORD *)a1 + 2);\n if ( v5 > a3 )\n break;\n a1 += 2;\n if ( v4 == a1 )\n return v3;\n }\n v6 = v5 - 1;\n if ( a3 < v6 )\n {\n v7 = *a1;\n v8 = a3;\n do\n {\n *(_DWORD *)(v7 + 4 * v8) = *(_DWORD *)(v7 + 4 * v8 + 4);\n ++v8;\n v6 = *((_DWORD *)a1 + 2) - 1;\n }\n while ( v6 > (int)v8 );\n }\n *((_DWORD *)a1 + 2) = v6;\n a1 += 2;\n }\n while ( v4 != a1 );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long *sub_1730(long long *a1, int a2, int a3) {\n long long *v3;\n long long *v4;\n int v5;\n int v6;\n long long v7;\n long long v8;\n v3 = a1;\n if (a2 > 0) {\n v4 = &a1[2 * a2];\n do {\n while (1) {\n v5 = *((uint32_t *)a1 + 2);\n if (v5 > a3) break;\n a1 += 2;\n if (v4 == a1) return v3;\n }\n v6 = v5 - 1;\n if (a3 < v6) {\n v7 = *a1;\n v8 = a3;\n do {\n *(uint32_t *)(v7 + 4 * v8) = *(uint32_t *)(v7 + 4 * v8 + 4);\n ++v8;\n v6 = *((uint32_t *)a1 + 2) - 1;\n } while (v6 > (int)v8);\n }\n *((uint32_t *)a1 + 2) = v6;\n a1 += 2;\n } while (v4 != a1);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long *func0(long long *a1, int a2, int a3) {\n long long *v3;\n long long *v4;\n int v5;\n int v6;\n long long v7;\n long long v8;\n v3 = a1;\n if (a2 > 0) {\n v4 = &a1[2 * a2];\n do {\n while (1) {\n v5 = *((uint32_t *)a1 + 2);\n if (v5 > a3) break;\n a1 += 2;\n if (v4 == a1) return v3;\n }\n v6 = v5 - 1;\n if (a3 < v6) {\n v7 = *a1;\n v8 = a3;\n do {\n *(uint32_t *)(v7 + 4 * v8) = *(uint32_t *)(v7 + 4 * v8 + 4);\n ++v8;\n v6 = *((uint32_t *)a1 + 2) - 1;\n } while (v6 > (int)v8);\n }\n *((uint32_t *)a1 + 2) = v6;\n a1 += 2;\n } while (v4 != a1);\n }\n return v3;\n}" + }, + { + "index": 353, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int* data;\n\n int length;\n\n} Row;\n\n\n\n", + "func": "Row* func0(Row list1[], int num_rows, int n) {\n for (int i = 0; i < num_rows; i++) {\n if (n < list1[i].length) {\n for (int j = n; j < list1[i].length - 1; j++) {\n list1[i].data[j] = list1[i].data[j + 1];\n }\n list1[i].length -= 1;\n }\n }\n return list1;\n}", + "test": "int main() {\n\n // Test case 1\n\n {\n\n int row0[] = {1, 2, 3};\n\n int row1[] = {2, 4, 5};\n\n int row2[] = {1, 1, 1};\n\n Row list1[3];\n\n list1[0].data = row0;\n\n list1[0].length = 3;\n\n list1[1].data = row1;\n\n list1[1].length = 3;\n\n list1[2].data = row2;\n\n list1[2].length = 3;\n\n \n\n Row* result = func0(list1, 3, 0);\n\n \n\n int expected0[] = {2, 3};\n\n int expected1[] = {4, 5};\n\n int expected2[] = {1, 1};\n\n Row expected[3];\n\n expected[0].data = expected0;\n\n expected[0].length = 2;\n\n expected[1].data = expected1;\n\n expected[1].length = 2;\n\n expected[2].data = expected2;\n\n expected[2].length = 2;\n\n \n\n for(int i = 0; i < 3; i++) {\n\n assert(result[i].length == expected[i].length);\n\n assert(memcmp(result[i].data, expected[i].data, sizeof(int)*result[i].length) == 0);\n\n }\n\n }\n\n \n\n // Test case 2\n\n {\n\n int row0[] = {1, 2, 3};\n\n int row1[] = {-2, 4, -5};\n\n int row2[] = {1, -1, 1};\n\n Row list1[3];\n\n list1[0].data = row0;\n\n list1[0].length = 3;\n\n list1[1].data = row1;\n\n list1[1].length = 3;\n\n list1[2].data = row2;\n\n list1[2].length = 3;\n\n \n\n Row* result = func0(list1, 3, 2);\n\n \n\n int expected0[] = {1, 2};\n\n int expected1[] = {-2, 4};\n\n int expected2[] = {1, -1};\n\n Row expected[3];\n\n expected[0].data = expected0;\n\n expected[0].length = 2;\n\n expected[1].data = expected1;\n\n expected[1].length = 2;\n\n expected[2].data = expected2;\n\n expected[2].length = 2;\n\n \n\n for(int i = 0; i < 3; i++) {\n\n assert(result[i].length == expected[i].length);\n\n assert(memcmp(result[i].data, expected[i].data, sizeof(int)*result[i].length) == 0);\n\n }\n\n }\n\n \n\n // Test case 3\n\n {\n\n int row0[] = {1, 3};\n\n int row1[] = {5, 7};\n\n int row2[] = {1, 3};\n\n int row3[] = {13, 15, 17};\n\n int row4[] = {5, 7};\n\n int row5[] = {9, 11};\n\n Row list1[6];\n\n list1[0].data = row0;\n\n list1[0].length = 2;\n\n list1[1].data = row1;\n\n list1[1].length = 2;\n\n list1[2].data = row2;\n\n list1[2].length = 2;\n\n list1[3].data = row3;\n\n list1[3].length = 3;\n\n list1[4].data = row4;\n\n list1[4].length = 2;\n\n list1[5].data = row5;\n\n list1[5].length = 2;\n\n \n\n Row* result = func0(list1, 6, 0);\n\n \n\n int expected0[] = {3};\n\n int expected1[] = {7};\n\n int expected2[] = {3};\n\n int expected3[] = {15, 17};\n\n int expected4[] = {7};\n\n int expected5[] = {11};\n\n Row expected[6];\n\n expected[0].data = expected0;\n\n expected[0].length = 1;\n\n expected[1].data = expected1;\n\n expected[1].length = 1;\n\n expected[2].data = expected2;\n\n expected[2].length = 1;\n\n expected[3].data = expected3;\n\n expected[3].length = 2;\n\n expected[4].data = expected4;\n\n expected[4].length = 1;\n\n expected[5].data = expected5;\n\n expected[5].length = 1;\n\n \n\n for(int i = 0; i < 6; i++) {\n\n assert(result[i].length == expected[i].length);\n\n assert(memcmp(result[i].data, expected[i].data, sizeof(int)*result[i].length) == 0);\n\n }\n\n }\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%r10\ntest %esi,%esi\njle 1631 \nlea -0x1(%rsi),%eax\nlea 0x8(%rdi),%r8\nshl $0x4,%rax\nlea 0x18(%rdi,%rax,1),%r9\njmp 15f9 \nnopl (%rax)\nadd $0x10,%r8\ncmp %r8,%r9\nje 1631 \nmov (%r8),%eax\ncmp %edx,%eax\njle 15f0 \nsub $0x1,%eax\ncmp %eax,%edx\njge 1625 \nmov -0x8(%r8),%rsi\nmovslq %edx,%rcx\nxchg %ax,%ax\nmov 0x4(%rsi,%rcx,4),%eax\nmov %eax,(%rsi,%rcx,4)\nmov (%r8),%eax\nadd $0x1,%rcx\nsub $0x1,%eax\ncmp %ecx,%eax\njg 1610 \nmov %eax,(%r8)\nadd $0x10,%r8\ncmp %r8,%r9\njne 15f9 \nmov %r10,%rax\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmov r9, rdi\ntest esi, esi\njle short loc_15D1\nmovsxd rsi, esi\nshl rsi, 4\nlea r8, [rsi+rdi]\njmp short loc_1599\nloc_1590:\nadd rdi, 10h\ncmp r8, rdi\njz short loc_15D1\nloc_1599:\nmov eax, [rdi+8]\ncmp eax, edx\njle short loc_1590\nsub eax, 1\ncmp edx, eax\njge short loc_15C5\nmov rsi, [rdi]\nmovsxd rcx, edx\nnop dword ptr [rax]\nloc_15B0:\nmov eax, [rsi+rcx*4+4]\nmov [rsi+rcx*4], eax\nmov eax, [rdi+8]\nadd rcx, 1\nsub eax, 1\ncmp eax, ecx\njg short loc_15B0\nloc_15C5:\nmov [rdi+8], eax\nadd rdi, 10h\ncmp r8, rdi\njnz short loc_1599\nloc_15D1:\nmov rax, r9\nretn", + "ida_pseudo": "__int64 *__fastcall func0(__int64 *a1, int a2, int a3)\n{\n __int64 *v3; // r9\n __int64 *v4; // r8\n int v5; // eax\n int v6; // eax\n __int64 v7; // rsi\n __int64 v8; // rcx\n\n v3 = a1;\n if ( a2 > 0 )\n {\n v4 = &a1[2 * a2];\n do\n {\n while ( 1 )\n {\n v5 = *((_DWORD *)a1 + 2);\n if ( v5 > a3 )\n break;\n a1 += 2;\n if ( v4 == a1 )\n return v3;\n }\n v6 = v5 - 1;\n if ( a3 < v6 )\n {\n v7 = *a1;\n v8 = a3;\n do\n {\n *(_DWORD *)(v7 + 4 * v8) = *(_DWORD *)(v7 + 4 * v8 + 4);\n ++v8;\n v6 = *((_DWORD *)a1 + 2) - 1;\n }\n while ( v6 > (int)v8 );\n }\n *((_DWORD *)a1 + 2) = v6;\n a1 += 2;\n }\n while ( v4 != a1 );\n }\n return v3;\n}", + "ida_strip_asm": "sub_1570:\nendbr64\nmov r9, rdi\ntest esi, esi\njle short loc_15D1\nmovsxd rsi, esi\nshl rsi, 4\nlea r8, [rsi+rdi]\njmp short loc_1599\nloc_1590:\nadd rdi, 10h\ncmp r8, rdi\njz short loc_15D1\nloc_1599:\nmov eax, [rdi+8]\ncmp eax, edx\njle short loc_1590\nsub eax, 1\ncmp edx, eax\njge short loc_15C5\nmov rsi, [rdi]\nmovsxd rcx, edx\nnop dword ptr [rax]\nloc_15B0:\nmov eax, [rsi+rcx*4+4]\nmov [rsi+rcx*4], eax\nmov eax, [rdi+8]\nadd rcx, 1\nsub eax, 1\ncmp eax, ecx\njg short loc_15B0\nloc_15C5:\nmov [rdi+8], eax\nadd rdi, 10h\ncmp r8, rdi\njnz short loc_1599\nloc_15D1:\nmov rax, r9\nretn", + "ida_strip_pseudo": "__int64 *__fastcall sub_1570(__int64 *a1, int a2, int a3)\n{\n __int64 *v3; // r9\n __int64 *v4; // r8\n int v5; // eax\n int v6; // eax\n __int64 v7; // rsi\n __int64 v8; // rcx\n\n v3 = a1;\n if ( a2 > 0 )\n {\n v4 = &a1[2 * a2];\n do\n {\n while ( 1 )\n {\n v5 = *((_DWORD *)a1 + 2);\n if ( v5 > a3 )\n break;\n a1 += 2;\n if ( v4 == a1 )\n return v3;\n }\n v6 = v5 - 1;\n if ( a3 < v6 )\n {\n v7 = *a1;\n v8 = a3;\n do\n {\n *(_DWORD *)(v7 + 4 * v8) = *(_DWORD *)(v7 + 4 * v8 + 4);\n ++v8;\n v6 = *((_DWORD *)a1 + 2) - 1;\n }\n while ( v6 > (int)v8 );\n }\n *((_DWORD *)a1 + 2) = v6;\n a1 += 2;\n }\n while ( v4 != a1 );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long *sub_1570(long long *a1, int a2, int a3) {\n long long *v3;\n long long *v4;\n int v5;\n int v6;\n long long v7;\n long long v8;\n v3 = a1;\n if (a2 > 0) {\n v4 = &a1[2 * a2];\n do {\n while (1) {\n v5 = *((uint32_t *)a1 + 2);\n if (v5 > a3) break;\n a1 += 2;\n if (v4 == a1) return v3;\n }\n v6 = v5 - 1;\n if (a3 < v6) {\n v7 = *a1;\n v8 = a3;\n do {\n *(uint32_t *)(v7 + 4 * v8) = *(uint32_t *)(v7 + 4 * v8 + 4);\n ++v8;\n v6 = *((uint32_t *)a1 + 2) - 1;\n } while (v6 > (int)v8);\n }\n *((uint32_t *)a1 + 2) = v6;\n a1 += 2;\n } while (v4 != a1);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long *func0(long long *a1, int a2, int a3) {\n long long *v3;\n long long *v4;\n int v5;\n int v6;\n long long v7;\n long long v8;\n v3 = a1;\n if (a2 > 0) {\n v4 = &a1[2 * a2];\n do {\n while (1) {\n v5 = *((uint32_t *)a1 + 2);\n if (v5 > a3) break;\n a1 += 2;\n if (v4 == a1) return v3;\n }\n v6 = v5 - 1;\n if (a3 < v6) {\n v7 = *a1;\n v8 = a3;\n do {\n *(uint32_t *)(v7 + 4 * v8) = *(uint32_t *)(v7 + 4 * v8 + 4);\n ++v8;\n v6 = *((uint32_t *)a1 + 2) - 1;\n } while (v6 > (int)v8);\n }\n *((uint32_t *)a1 + 2) = v6;\n a1 += 2;\n } while (v4 != a1);\n }\n return v3;\n}" + }, + { + "index": 354, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int a, int n, int d) {\n int tn = a + (n - 1) * d;\n return tn;\n}", + "test": "int main() {\n\n assert(func0(1, 5, 2) == 9);\n\n assert(func0(2, 6, 4) == 22);\n\n assert(func0(1, 4, 5) == 16);\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov %edx,-0x1c(%rbp)\nmov -0x18(%rbp),%eax\nsub $0x1,%eax\nimul -0x1c(%rbp),%eax\nmov %eax,%edx\nmov -0x14(%rbp),%eax\nadd %edx,%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov eax, [rbp+var_18]\nsub eax, 1\nimul eax, [rbp+var_1C]\nmov edx, eax\nmov eax, [rbp+var_14]\nadd eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, int a3)\n{\n return (unsigned int)(a3 * (a2 - 1) + a1);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov eax, [rbp+var_18]\nsub eax, 1\nimul eax, [rbp+var_1C]\nmov edx, eax\nmov eax, [rbp+var_14]\nadd eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2, int a3)\n{\n return (unsigned int)(a3 * (a2 - 1) + a1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2, int a3) {\n return (unsigned int)(a3 * (a2 - 1) + a1);\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, int a3) {\n return (unsigned int)(a3 * (a2 - 1) + a1);\n}" + }, + { + "index": 355, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int radius) {\n int rectangles = 0;\n int diameter = 2 * radius;\n int diameterSquare = diameter * diameter;\n for (int a = 1; a < 2 * radius; a++) {\n for (int b = 1; b < 2 * radius; b++) {\n int diagnalLengthSquare = (a * a + b * b);\n if (diagnalLengthSquare <= diameterSquare) {\n rectangles += 1;\n }\n }\n }\n return rectangles;\n}", + "test": "int main() {\n\n assert(func0(2) == 8);\n\n assert(func0(1) == 1);\n\n assert(func0(0) == 0);\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x24(%rbp)\nmovl $0x0,-0x18(%rbp)\nmov -0x24(%rbp),%eax\nadd %eax,%eax\nmov %eax,-0xc(%rbp)\nmov -0xc(%rbp),%eax\nimul %eax,%eax\nmov %eax,-0x8(%rbp)\nmovl $0x1,-0x14(%rbp)\njmp 11af \nmovl $0x1,-0x10(%rbp)\njmp 11a1 \nmov -0x14(%rbp),%eax\nimul %eax,%eax\nmov %eax,%edx\nmov -0x10(%rbp),%eax\nimul %eax,%eax\nadd %edx,%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x8(%rbp),%eax\njg 119d \naddl $0x1,-0x18(%rbp)\naddl $0x1,-0x10(%rbp)\nmov -0x24(%rbp),%eax\nadd %eax,%eax\ncmp %eax,-0x10(%rbp)\njl 117e \naddl $0x1,-0x14(%rbp)\nmov -0x24(%rbp),%eax\nadd %eax,%eax\ncmp %eax,-0x14(%rbp)\njl 1175 \nmov -0x18(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_24], edi\nmov [rbp+var_18], 0\nmov eax, [rbp+var_24]\nadd eax, eax\nmov [rbp+var_C], eax\nmov eax, [rbp+var_C]\nimul eax, eax\nmov [rbp+var_8], eax\nmov [rbp+var_14], 1\njmp short loc_11AF\nloc_1175:\nmov [rbp+var_10], 1\njmp short loc_11A1\nloc_117E:\nmov eax, [rbp+var_14]\nimul eax, eax\nmov edx, eax\nmov eax, [rbp+var_10]\nimul eax, eax\nadd eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_8]\njg short loc_119D\nadd [rbp+var_18], 1\nloc_119D:\nadd [rbp+var_10], 1\nloc_11A1:\nmov eax, [rbp+var_24]\nadd eax, eax\ncmp [rbp+var_10], eax\njl short loc_117E\nadd [rbp+var_14], 1\nloc_11AF:\nmov eax, [rbp+var_24]\nadd eax, eax\ncmp [rbp+var_14], eax\njl short loc_1175\nmov eax, [rbp+var_18]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v2; // [rsp+Ch] [rbp-18h]\n int i; // [rsp+10h] [rbp-14h]\n int j; // [rsp+14h] [rbp-10h]\n\n v2 = 0;\n for ( i = 1; i < 2 * a1; ++i )\n {\n for ( j = 1; j < 2 * a1; ++j )\n {\n if ( i * i + j * j <= 2 * a1 * 2 * a1 )\n ++v2;\n }\n }\n return v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_24], edi\nmov [rbp+var_18], 0\nmov eax, [rbp+var_24]\nadd eax, eax\nmov [rbp+var_C], eax\nmov eax, [rbp+var_C]\nimul eax, eax\nmov [rbp+var_8], eax\nmov [rbp+var_14], 1\njmp short loc_11AF\nloc_1175:\nmov [rbp+var_10], 1\njmp short loc_11A1\nloc_117E:\nmov eax, [rbp+var_14]\nimul eax, eax\nmov edx, eax\nmov eax, [rbp+var_10]\nimul eax, eax\nadd eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_8]\njg short loc_119D\nadd [rbp+var_18], 1\nloc_119D:\nadd [rbp+var_10], 1\nloc_11A1:\nmov eax, [rbp+var_24]\nadd eax, eax\ncmp [rbp+var_10], eax\njl short loc_117E\nadd [rbp+var_14], 1\nloc_11AF:\nmov eax, [rbp+var_24]\nadd eax, eax\ncmp [rbp+var_14], eax\njl short loc_1175\nmov eax, [rbp+var_18]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n unsigned int v2; // [rsp+Ch] [rbp-18h]\n int i; // [rsp+10h] [rbp-14h]\n int j; // [rsp+14h] [rbp-10h]\n\n v2 = 0;\n for ( i = 1; i < 2 * a1; ++i )\n {\n for ( j = 1; j < 2 * a1; ++j )\n {\n if ( i * i + j * j <= 2 * a1 * 2 * a1 )\n ++v2;\n }\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n unsigned int v2;\n int i;\n int j;\n v2 = 0;\n for (i = 1; i < 2 * a1; ++i) {\n for (j = 1; j < 2 * a1; ++j) {\n if (i * i + j * j <= 2 * a1 * 2 * a1) ++v2;\n }\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v2;\n int i;\n int j;\n v2 = 0;\n for (i = 1; i < 2 * a1; ++i) {\n for (j = 1; j < 2 * a1; ++j) {\n if (i * i + j * j <= 2 * a1 * 2 * a1) ++v2;\n }\n }\n return v2;\n}" + }, + { + "index": 355, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int radius) {\n int rectangles = 0;\n int diameter = 2 * radius;\n int diameterSquare = diameter * diameter;\n for (int a = 1; a < 2 * radius; a++) {\n for (int b = 1; b < 2 * radius; b++) {\n int diagnalLengthSquare = (a * a + b * b);\n if (diagnalLengthSquare <= diameterSquare) {\n rectangles += 1;\n }\n }\n }\n return rectangles;\n}", + "test": "int main() {\n\n assert(func0(2) == 8);\n\n assert(func0(1) == 1);\n\n assert(func0(0) == 0);\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nlea (%rdi,%rdi,1),%esi\nmov %esi,%r8d\nimul %esi,%r8d\nmov $0x1,%r9d\nmov $0x0,%ecx\ncmp $0x1,%esi\njg 1173 \nmov %ecx,%eax\nretq\nadd $0x1,%r9d\ncmp %r9d,%esi\nje 1167 \nmov %r9d,%edi\nimul %r9d,%edi\nmov $0x1,%eax\nmov %eax,%edx\nimul %eax,%edx\nadd %edi,%edx\ncmp %edx,%r8d\nsetge %dl\nmovzbl %dl,%edx\nadd %edx,%ecx\nadd $0x1,%eax\ncmp %eax,%esi\njne 117f \njmp 116a \n", + "ida_asm": "func0:\nendbr64\nlea eax, [rdi+rdi]\nmov r8d, eax\nimul r8d, eax\ncmp eax, 1\njle short loc_119A\nmov esi, eax\nmov r9d, 1\nmov ecx, 0\nloc_1169:\nmov edi, r9d\nimul edi, r9d\nmov eax, 1\nloc_1175:\nmov edx, eax\nimul edx, eax\nadd edx, edi\ncmp r8d, edx\nsetnl dl\nmovzx edx, dl\nadd ecx, edx\nadd eax, 1\ncmp eax, esi\njnz short loc_1175\nadd r9d, 1\ncmp r9d, esi\njnz short loc_1169\nloc_1197:\nmov eax, ecx\nretn\nloc_119A:\nmov ecx, 0\njmp short loc_1197", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // esi\n int v2; // r9d\n unsigned int v3; // ecx\n int v4; // eax\n\n if ( 2 * a1 <= 1 )\n {\n return 0;\n }\n else\n {\n v1 = 2 * a1;\n v2 = 1;\n v3 = 0;\n do\n {\n v4 = 1;\n do\n {\n v3 += 2 * a1 * 2 * a1 >= v2 * v2 + v4 * v4;\n ++v4;\n }\n while ( v4 != v1 );\n ++v2;\n }\n while ( v2 != v1 );\n }\n return v3;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nlea eax, [rdi+rdi]\nmov r8d, eax\nimul r8d, eax\ncmp eax, 1\njle short loc_119A\nmov esi, eax\nmov r9d, 1\nmov ecx, 0\nloc_1169:\nmov edi, r9d\nimul edi, r9d\nmov eax, 1\nloc_1175:\nmov edx, eax\nimul edx, eax\nadd edx, edi\ncmp r8d, edx\nsetnl dl\nmovzx edx, dl\nadd ecx, edx\nadd eax, 1\ncmp eax, esi\njnz short loc_1175\nadd r9d, 1\ncmp r9d, esi\njnz short loc_1169\nloc_1197:\nmov eax, ecx\nretn\nloc_119A:\nmov ecx, 0\njmp short loc_1197", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v1; // esi\n int v2; // r9d\n unsigned int v3; // ecx\n int v4; // eax\n\n if ( 2 * a1 <= 1 )\n {\n return 0;\n }\n else\n {\n v1 = 2 * a1;\n v2 = 1;\n v3 = 0;\n do\n {\n v4 = 1;\n do\n {\n v3 += 2 * a1 * 2 * a1 >= v2 * v2 + v4 * v4;\n ++v4;\n }\n while ( v4 != v1 );\n ++v2;\n }\n while ( v2 != v1 );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v1;\n int v2;\n unsigned int v3;\n int v4;\n if (2 * a1 <= 1) {\n return 0;\n } else {\n v1 = 2 * a1;\n v2 = 1;\n v3 = 0;\n do {\n v4 = 1;\n do {\n v3 += 2 * a1 * 2 * a1 >= v2 * v2 + v4 * v4;\n ++v4;\n } while (v4 != v1);\n ++v2;\n } while (v2 != v1);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v2;\n unsigned int v3;\n int v4;\n if (2 * a1 <= 1) {\n return 0;\n } else {\n v1 = 2 * a1;\n v2 = 1;\n v3 = 0;\n do {\n v4 = 1;\n do {\n v3 += 2 * a1 * 2 * a1 >= v2 * v2 + v4 * v4;\n ++v4;\n } while (v4 != v1);\n ++v2;\n } while (v2 != v1);\n }\n return v3;\n}" + }, + { + "index": 355, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int radius) {\n int rectangles = 0;\n int diameter = 2 * radius;\n int diameterSquare = diameter * diameter;\n for (int a = 1; a < 2 * radius; a++) {\n for (int b = 1; b < 2 * radius; b++) {\n int diagnalLengthSquare = (a * a + b * b);\n if (diagnalLengthSquare <= diameterSquare) {\n rectangles += 1;\n }\n }\n }\n return rectangles;\n}", + "test": "int main() {\n\n assert(func0(2) == 8);\n\n assert(func0(1) == 1);\n\n assert(func0(0) == 0);\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nlea (%rdi,%rdi,1),%ecx\nmov %ecx,%edi\nimul %ecx,%edi\ncmp $0x1,%ecx\njle 1196 \nmov $0x1,%r9d\nxor %r8d,%r8d\nnopw 0x0(%rax,%rax,1)\nmov %r9d,%esi\nmov $0x1,%eax\nimul %r9d,%esi\nnopl 0x0(%rax)\nmov %eax,%edx\nimul %eax,%edx\nadd %esi,%edx\ncmp %edx,%edi\nsetge %dl\nadd $0x1,%eax\nmovzbl %dl,%edx\nadd %edx,%r8d\ncmp %eax,%ecx\njne 1170 \nadd $0x1,%r9d\ncmp %r9d,%ecx\njne 1160 \nmov %r8d,%eax\nretq\nxor %r8d,%r8d\nmov %r8d,%eax\nretq\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\nlea esi, [rdi+rdi]\nmov r8d, esi\nimul r8d, esi\ncmp esi, 1\njle short loc_1245\nmov r9d, 1\nxor ecx, ecx\nnop dword ptr [rax+rax+00h]\nloc_1210:\nmov edi, r9d\nmov eax, 1\nimul edi, r9d\nnop dword ptr [rax+00h]\nloc_1220:\nmov edx, eax\nimul edx, eax\nadd edx, edi\ncmp r8d, edx\nsetnl dl\nadd eax, 1\nmovzx edx, dl\nadd ecx, edx\ncmp esi, eax\njnz short loc_1220\nadd r9d, 1\ncmp esi, r9d\njnz short loc_1210\nmov eax, ecx\nretn\nloc_1245:\nxor ecx, ecx\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // esi\n int v2; // r9d\n unsigned int v3; // ecx\n int v4; // eax\n bool v5; // dl\n\n v1 = 2 * a1;\n if ( 2 * a1 <= 1 )\n return 0LL;\n v2 = 1;\n v3 = 0;\n do\n {\n v4 = 1;\n do\n {\n v5 = v1 * v1 >= v2 * v2 + v4 * v4;\n ++v4;\n v3 += v5;\n }\n while ( v1 != v4 );\n ++v2;\n }\n while ( v1 != v2 );\n return v3;\n}", + "ida_strip_asm": "sub_11F0:\nendbr64\nlea esi, [rdi+rdi]\nmov r8d, esi\nimul r8d, esi\ncmp esi, 1\njle short loc_1245\nmov r9d, 1\nxor ecx, ecx\nnop dword ptr [rax+rax+00h]\nloc_1210:\nmov edi, r9d\nmov eax, 1\nimul edi, r9d\nnop dword ptr [rax+00h]\nloc_1220:\nmov edx, eax\nimul edx, eax\nadd edx, edi\ncmp r8d, edx\nsetnl dl\nadd eax, 1\nmovzx edx, dl\nadd ecx, edx\ncmp esi, eax\njnz short loc_1220\nadd r9d, 1\ncmp esi, r9d\njnz short loc_1210\nmov eax, ecx\nretn\nloc_1245:\nxor ecx, ecx\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11F0(int a1)\n{\n int v1; // esi\n int v2; // r9d\n unsigned int v3; // ecx\n int v4; // eax\n bool v5; // dl\n\n v1 = 2 * a1;\n if ( 2 * a1 <= 1 )\n return 0LL;\n v2 = 1;\n v3 = 0;\n do\n {\n v4 = 1;\n do\n {\n v5 = v1 * v1 >= v2 * v2 + v4 * v4;\n ++v4;\n v3 += v5;\n }\n while ( v1 != v4 );\n ++v2;\n }\n while ( v1 != v2 );\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11F0(int a1) {\n int v1;\n int v2;\n unsigned int v3;\n int v4;\n bool v5;\n v1 = 2 * a1;\n if (2 * a1 <= 1) return 0LL;\n v2 = 1;\n v3 = 0;\n do {\n v4 = 1;\n do {\n v5 = v1 * v1 >= v2 * v2 + v4 * v4;\n ++v4;\n v3 += v5;\n } while (v1 != v4);\n ++v2;\n } while (v1 != v2);\n return v3;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v2;\n unsigned int v3;\n int v4;\n bool v5;\n v1 = 2 * a1;\n if (2 * a1 <= 1) return 0LL;\n v2 = 1;\n v3 = 0;\n do {\n v4 = 1;\n do {\n v5 = v1 * v1 >= v2 * v2 + v4 * v4;\n ++v4;\n v3 += v5;\n } while (v1 != v4);\n ++v2;\n } while (v1 != v2);\n return v3;\n}" + }, + { + "index": 356, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int a, int b) {\n int c = 180 - (a + b);\n return c;\n}", + "test": "int main() {\n\n assert(func0(47, 89) == 44);\n\n assert(func0(45, 95) == 40);\n\n assert(func0(50, 40) == 90);\n\n \n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov -0x14(%rbp),%edx\nmov -0x18(%rbp),%eax\nadd %edx,%eax\nmov $0xb4,%edx\nsub %eax,%edx\nmov %edx,%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov edx, [rbp+var_14]\nmov eax, [rbp+var_18]\nadd edx, eax\nmov eax, 0B4h\nsub eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n return (unsigned int)(180 - (a2 + a1));\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov edx, [rbp+var_14]\nmov eax, [rbp+var_18]\nadd edx, eax\nmov eax, 0B4h\nsub eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2)\n{\n return (unsigned int)(180 - (a2 + a1));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2) { return (unsigned int)(180 - (a2 + a1)); }", + "ida_pseudo_norm": "long long func0(int a1, int a2) { return (unsigned int)(180 - (a2 + a1)); }" + }, + { + "index": 357, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int test_list[][2], int n) {\n int res = test_list[0][0];\n for (int i = 0; i < n; i++) {\n for (int j = 0; j < 2; j++) {\n if (test_list[i][j] > res) {\n res = test_list[i][j];\n }\n }\n }\n return res;\n}", + "test": "int main() {\n\n int list1[5][2] = {{2, 4}, {6, 7}, {5, 1}, {6, 10}, {8, 7}};\n\n int list2[5][2] = {{3, 5}, {7, 8}, {6, 2}, {7, 11}, {9, 8}};\n\n int list3[5][2] = {{4, 6}, {8, 9}, {7, 3}, {8, 12}, {10, 9}};\n\n assert(func0(list1, 5) == 10);\n\n assert(func0(list2, 5) == 11);\n\n assert(func0(list3, 5) == 12);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov -0x18(%rbp),%rax\nmov (%rax),%eax\nmov %eax,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11e1 \nmovl $0x0,-0x4(%rbp)\njmp 11d7 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0x4(%rbp),%eax\ncltq\nmov (%rdx,%rax,4),%eax\ncmp %eax,-0xc(%rbp)\njge 11d3 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0x4(%rbp),%eax\ncltq\nmov (%rdx,%rax,4),%eax\nmov %eax,-0xc(%rbp)\naddl $0x1,-0x4(%rbp)\ncmpl $0x1,-0x4(%rbp)\njle 1193 \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 118a \nmov -0xc(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov rax, [rbp+var_18]\nmov eax, [rax]\nmov [rbp+var_C], eax\nmov [rbp+var_8], 0\njmp short loc_11E1\nloc_118A:\nmov [rbp+var_4], 0\njmp short loc_11D7\nloc_1193:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\ncdqe\nmov eax, [rdx+rax*4]\ncmp [rbp+var_C], eax\njge short loc_11D3\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\ncdqe\nmov eax, [rdx+rax*4]\nmov [rbp+var_C], eax\nloc_11D3:\nadd [rbp+var_4], 1\nloc_11D7:\ncmp [rbp+var_4], 1\njle short loc_1193\nadd [rbp+var_8], 1\nloc_11E1:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_118A\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n unsigned int v3; // [rsp+10h] [rbp-Ch]\n int i; // [rsp+14h] [rbp-8h]\n int j; // [rsp+18h] [rbp-4h]\n\n v3 = *a1;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = 0; j <= 1; ++j )\n {\n if ( (int)v3 < (int)a1[2 * i + j] )\n v3 = a1[2 * i + j];\n }\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov rax, [rbp+var_18]\nmov eax, [rax]\nmov [rbp+var_C], eax\nmov [rbp+var_8], 0\njmp short loc_11E1\nloc_118A:\nmov [rbp+var_4], 0\njmp short loc_11D7\nloc_1193:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\ncdqe\nmov eax, [rdx+rax*4]\ncmp [rbp+var_C], eax\njge short loc_11D3\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\ncdqe\nmov eax, [rdx+rax*4]\nmov [rbp+var_C], eax\nloc_11D3:\nadd [rbp+var_4], 1\nloc_11D7:\ncmp [rbp+var_4], 1\njle short loc_1193\nadd [rbp+var_8], 1\nloc_11E1:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_118A\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(unsigned int *a1, int a2)\n{\n unsigned int v3; // [rsp+10h] [rbp-Ch]\n int i; // [rsp+14h] [rbp-8h]\n int j; // [rsp+18h] [rbp-4h]\n\n v3 = *a1;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = 0; j <= 1; ++j )\n {\n if ( (int)v3 < (int)a1[2 * i + j] )\n v3 = a1[2 * i + j];\n }\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(unsigned int *a1, int a2) {\n unsigned int v3;\n int i;\n int j;\n v3 = *a1;\n for (i = 0; i < a2; ++i) {\n for (j = 0; j <= 1; ++j) {\n if ((int)v3 < (int)a1[2 * i + j]) v3 = a1[2 * i + j];\n }\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n unsigned int v3;\n int i;\n int j;\n v3 = *a1;\n for (i = 0; i < a2; ++i) {\n for (j = 0; j <= 1; ++j) {\n if ((int)v3 < (int)a1[2 * i + j]) v3 = a1[2 * i + j];\n }\n }\n return v3;\n}" + }, + { + "index": 357, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int test_list[][2], int n) {\n int res = test_list[0][0];\n for (int i = 0; i < n; i++) {\n for (int j = 0; j < 2; j++) {\n if (test_list[i][j] > res) {\n res = test_list[i][j];\n }\n }\n }\n return res;\n}", + "test": "int main() {\n\n int list1[5][2] = {{2, 4}, {6, 7}, {5, 1}, {6, 10}, {8, 7}};\n\n int list2[5][2] = {{3, 5}, {7, 8}, {6, 2}, {7, 11}, {9, 8}};\n\n int list3[5][2] = {{4, 6}, {8, 9}, {7, 3}, {8, 12}, {10, 9}};\n\n assert(func0(list1, 5) == 10);\n\n assert(func0(list2, 5) == 11);\n\n assert(func0(list3, 5) == 12);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov (%rdi),%ecx\ntest %esi,%esi\njle 1195 \nmov %rdi,%rax\nlea -0x1(%rsi),%edx\nlea 0x8(%rdi,%rdx,8),%rsi\nmov (%rax),%edx\ncmp %edx,0x4(%rax)\ncmovge 0x4(%rax),%edx\ncmp %edx,%ecx\ncmovl %edx,%ecx\nadd $0x8,%rax\ncmp %rsi,%rax\njne 117e \nmov %ecx,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov ecx, [rdi]\ntest esi, esi\njle short loc_1195\nmov rdx, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*8]\nloc_117D:\nmov eax, [rdx+4]\nmov esi, [rdx]\ncmp eax, esi\ncmovl eax, esi\ncmp ecx, eax\ncmovl ecx, eax\nadd rdx, 8\ncmp rdx, rdi\njnz short loc_117D\nloc_1195:\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n unsigned int v2; // ecx\n int *v3; // rdx\n int *v4; // rdi\n int v5; // eax\n\n v2 = *a1;\n if ( a2 > 0 )\n {\n v3 = (int *)a1;\n v4 = (int *)&a1[2 * a2];\n do\n {\n v5 = v3[1];\n if ( v5 < *v3 )\n v5 = *v3;\n if ( (int)v2 < v5 )\n v2 = v5;\n v3 += 2;\n }\n while ( v3 != v4 );\n }\n return v2;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov ecx, [rdi]\ntest esi, esi\njle short loc_1195\nmov rdx, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*8]\nloc_117D:\nmov eax, [rdx+4]\nmov esi, [rdx]\ncmp eax, esi\ncmovl eax, esi\ncmp ecx, eax\ncmovl ecx, eax\nadd rdx, 8\ncmp rdx, rdi\njnz short loc_117D\nloc_1195:\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(unsigned int *a1, int a2)\n{\n unsigned int v2; // ecx\n int *v3; // rdx\n int *v4; // rdi\n int v5; // eax\n\n v2 = *a1;\n if ( a2 > 0 )\n {\n v3 = (int *)a1;\n v4 = (int *)&a1[2 * a2];\n do\n {\n v5 = v3[1];\n if ( v5 < *v3 )\n v5 = *v3;\n if ( (int)v2 < v5 )\n v2 = v5;\n v3 += 2;\n }\n while ( v3 != v4 );\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(unsigned int *a1, int a2) {\n unsigned int v2;\n int *v3;\n int *v4;\n int v5;\n v2 = *a1;\n if (a2 > 0) {\n v3 = (int *)a1;\n v4 = (int *)&a1[2 * a2];\n do {\n v5 = v3[1];\n if (v5 < *v3) v5 = *v3;\n if ((int)v2 < v5) v2 = v5;\n v3 += 2;\n } while (v3 != v4);\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n unsigned int v2;\n int *v3;\n int *v4;\n int v5;\n v2 = *a1;\n if (a2 > 0) {\n v3 = (int *)a1;\n v4 = (int *)&a1[2 * a2];\n do {\n v5 = v3[1];\n if (v5 < *v3) v5 = *v3;\n if ((int)v2 < v5) v2 = v5;\n v3 += 2;\n } while (v3 != v4);\n }\n return v2;\n}" + }, + { + "index": 357, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int test_list[][2], int n) {\n int res = test_list[0][0];\n for (int i = 0; i < n; i++) {\n for (int j = 0; j < 2; j++) {\n if (test_list[i][j] > res) {\n res = test_list[i][j];\n }\n }\n }\n return res;\n}", + "test": "int main() {\n\n int list1[5][2] = {{2, 4}, {6, 7}, {5, 1}, {6, 10}, {8, 7}};\n\n int list2[5][2] = {{3, 5}, {7, 8}, {6, 2}, {7, 11}, {9, 8}};\n\n int list3[5][2] = {{4, 6}, {8, 9}, {7, 3}, {8, 12}, {10, 9}};\n\n assert(func0(list1, 5) == 10);\n\n assert(func0(list2, 5) == 11);\n\n assert(func0(list3, 5) == 12);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov (%rdi),%eax\ntest %esi,%esi\njle 13e6 \nlea -0x1(%rsi),%ecx\nlea 0x4(%rdi),%rdx\nlea 0xc(%rdi,%rcx,8),%rsi\nmov %eax,%ecx\njmp 13d3 \nnopw 0x0(%rax,%rax,1)\nmov -0x4(%rdx),%ecx\ncmp %ecx,%eax\ncmovl %ecx,%eax\ncmp %eax,(%rdx)\ncmovge (%rdx),%eax\nadd $0x8,%rdx\ncmp %rsi,%rdx\njne 13d0 \nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmov edx, [rdi]\ntest esi, esi\njle short loc_12F0\nmovsxd rsi, esi\nlea rsi, [rdi+rsi*8]\nnop dword ptr [rax+00000000h]\nloc_12D8:\nmov eax, [rdi]\nmov ecx, [rdi+4]\ncmp eax, ecx\ncmovl eax, ecx\ncmp edx, eax\ncmovl edx, eax\nadd rdi, 8\ncmp rsi, rdi\njnz short loc_12D8\nloc_12F0:\nmov eax, edx\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n unsigned int v2; // edx\n unsigned int *v3; // rsi\n int v4; // eax\n\n v2 = *a1;\n if ( a2 > 0 )\n {\n v3 = &a1[2 * a2];\n do\n {\n v4 = *a1;\n if ( (int)*a1 < (int)a1[1] )\n v4 = a1[1];\n if ( (int)v2 < v4 )\n v2 = v4;\n a1 += 2;\n }\n while ( v3 != a1 );\n }\n return v2;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\nmov edx, [rdi]\ntest esi, esi\njle short loc_12F0\nmovsxd rsi, esi\nlea rsi, [rdi+rsi*8]\nnop dword ptr [rax+00000000h]\nloc_12D8:\nmov eax, [rdi]\nmov ecx, [rdi+4]\ncmp eax, ecx\ncmovl eax, ecx\ncmp edx, eax\ncmovl edx, eax\nadd rdi, 8\ncmp rsi, rdi\njnz short loc_12D8\nloc_12F0:\nmov eax, edx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12C0(unsigned int *a1, int a2)\n{\n unsigned int v2; // edx\n unsigned int *v3; // rsi\n int v4; // eax\n\n v2 = *a1;\n if ( a2 > 0 )\n {\n v3 = &a1[2 * a2];\n do\n {\n v4 = *a1;\n if ( (int)*a1 < (int)a1[1] )\n v4 = a1[1];\n if ( (int)v2 < v4 )\n v2 = v4;\n a1 += 2;\n }\n while ( v3 != a1 );\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12C0(unsigned int *a1, int a2) {\n unsigned int v2;\n unsigned int *v3;\n int v4;\n v2 = *a1;\n if (a2 > 0) {\n v3 = &a1[2 * a2];\n do {\n v4 = *a1;\n if ((int)*a1 < (int)a1[1]) v4 = a1[1];\n if ((int)v2 < v4) v2 = v4;\n a1 += 2;\n } while (v3 != a1);\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n unsigned int v2;\n unsigned int *v3;\n int v4;\n v2 = *a1;\n if (a2 > 0) {\n v3 = &a1[2 * a2];\n do {\n v4 = *a1;\n if ((int)*a1 < (int)a1[1]) v4 = a1[1];\n if ((int)v2 < v4) v2 = v4;\n a1 += 2;\n } while (v3 != a1);\n }\n return v2;\n}" + }, + { + "index": 358, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int *func0(int *nums1, int *nums2, int size) {\n int *result = malloc(size * sizeof(int));\n for (int i = 0; i < size; i++) {\n result[i] = nums1[i] % nums2[i];\n }\n return result;\n}", + "test": "int main() {\n\n int nums1_1[] = {4, 5, 6};\n\n int nums2_1[] = {1, 2, 3};\n\n int *result1 = func0(nums1_1, nums2_1, 3);\n\n assert(result1[0] == 0 && result1[1] == 1 && result1[2] == 0);\n\n free(result1);\n\n\n\n int nums1_2[] = {3, 2};\n\n int nums2_2[] = {1, 4};\n\n int *result2 = func0(nums1_2, nums2_2, 2);\n\n assert(result2[0] == 0 && result2[1] == 2);\n\n free(result2);\n\n\n\n int nums1_3[] = {90, 120};\n\n int nums2_3[] = {50, 70};\n\n int *result3 = func0(nums1_3, nums2_3, 2);\n\n assert(result3[0] == 40 && result3[1] == 50);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %edx,-0x24(%rbp)\nmov -0x24(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 122b \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov -0xc(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x20(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rdx),%esi\nmov -0xc(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x8(%rbp),%rdx\nadd %rdx,%rcx\ncltd\nidiv %esi\nmov %edx,%eax\nmov %eax,(%rcx)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x24(%rbp),%eax\njl 11de \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov eax, [rbp+var_24]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp short loc_122D\nloc_11DE:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_20]\nadd rdx, rcx\nmov edi, [rdx]\nmov ecx, [rbp+var_C]\nmovsxd rcx, ecx\nlea rsi, ds:0[rcx*4]\nmov rcx, [rbp+var_8]\nadd rcx, rsi\ncdq\nidiv edi\nmov esi, edx\nmov eax, esi\nmov [rcx], eax\nadd [rbp+var_C], 1\nloc_122D:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_24]\njl short loc_11DE\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n int i; // [rsp+24h] [rbp-Ch]\n _DWORD *v6; // [rsp+28h] [rbp-8h]\n\n v6 = malloc(4LL * a3);\n for ( i = 0; i < a3; ++i )\n v6[i] = *(_DWORD *)(4LL * i + a1) % *(_DWORD *)(4LL * i + a2);\n return v6;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov eax, [rbp+var_24]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp short loc_122D\nloc_11DE:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_20]\nadd rdx, rcx\nmov edi, [rdx]\nmov ecx, [rbp+var_C]\nmovsxd rcx, ecx\nlea rsi, ds:0[rcx*4]\nmov rcx, [rbp+var_8]\nadd rcx, rsi\ncdq\nidiv edi\nmov esi, edx\nmov eax, esi\nmov [rcx], eax\nadd [rbp+var_C], 1\nloc_122D:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_24]\njl short loc_11DE\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(__int64 a1, __int64 a2, int a3)\n{\n int i; // [rsp+24h] [rbp-Ch]\n _DWORD *v6; // [rsp+28h] [rbp-8h]\n\n v6 = malloc(4LL * a3);\n for ( i = 0; i < a3; ++i )\n v6[i] = *(_DWORD *)(4LL * i + a1) % *(_DWORD *)(4LL * i + a2);\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(long long a1, long long a2, int a3) {\n int i;\n uint32_t *v6;\n v6 = malloc(4LL * a3);\n for (i = 0; i < a3; ++i)\n v6[i] = *(uint32_t *)(4LL * i + a1) % *(uint32_t *)(4LL * i + a2);\n return v6;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, long long a2, int a3) {\n int i;\n uint32_t *v6;\n v6 = malloc(4LL * a3);\n for (i = 0; i < a3; ++i)\n v6[i] = *(uint32_t *)(4LL * i + a1) % *(uint32_t *)(4LL * i + a2);\n return v6;\n}" + }, + { + "index": 358, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int *func0(int *nums1, int *nums2, int size) {\n int *result = malloc(size * sizeof(int));\n for (int i = 0; i < size; i++) {\n result[i] = nums1[i] % nums2[i];\n }\n return result;\n}", + "test": "int main() {\n\n int nums1_1[] = {4, 5, 6};\n\n int nums2_1[] = {1, 2, 3};\n\n int *result1 = func0(nums1_1, nums2_1, 3);\n\n assert(result1[0] == 0 && result1[1] == 1 && result1[2] == 0);\n\n free(result1);\n\n\n\n int nums1_2[] = {3, 2};\n\n int nums2_2[] = {1, 4};\n\n int *result2 = func0(nums1_2, nums2_2, 2);\n\n assert(result2[0] == 0 && result2[1] == 2);\n\n free(result2);\n\n\n\n int nums1_3[] = {90, 120};\n\n int nums2_3[] = {50, 70};\n\n int *result3 = func0(nums1_3, nums2_3, 2);\n\n assert(result3[0] == 40 && result3[1] == 50);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbp\nmov %rsi,%rbx\nmov %edx,%r12d\nmovslq %edx,%rdi\nshl $0x2,%rdi\ncallq 10b0 \nmov %rax,%rsi\ntest %r12d,%r12d\njle 11ef \nlea -0x1(%r12),%edi\nmov $0x0,%ecx\nmov 0x0(%rbp,%rcx,4),%eax\ncltd\nidivl (%rbx,%rcx,4)\nmov %edx,(%rsi,%rcx,4)\nmov %rcx,%rax\nadd $0x1,%rcx\ncmp %rdi,%rax\njne 11d8 \nmov %rsi,%rax\npop %rbx\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12, rdi\nmov rbx, rsi\nmov r13d, edx\nmovsxd rbp, edx\nshl rbp, 2\nmov rdi, rbp; size\ncall _malloc\nmov rsi, rax\ntest r13d, r13d\njle short loc_11F0\nmov ecx, 0\nloc_11DC:\nmov eax, [r12+rcx]\ncdq\nidiv dword ptr [rbx+rcx]\nmov [rsi+rcx], edx\nadd rcx, 4\ncmp rbp, rcx\njnz short loc_11DC\nloc_11F0:\nmov rax, rsi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n size_t v5; // rbp\n char *v6; // rsi\n __int64 v7; // rcx\n\n v5 = 4LL * a3;\n v6 = (char *)malloc(v5);\n if ( a3 > 0 )\n {\n v7 = 0LL;\n do\n {\n *(_DWORD *)&v6[v7] = *(_DWORD *)(a1 + v7) % *(_DWORD *)(a2 + v7);\n v7 += 4LL;\n }\n while ( v5 != v7 );\n }\n return v6;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12, rdi\nmov rbx, rsi\nmov r13d, edx\nmovsxd rbp, edx\nshl rbp, 2\nmov rdi, rbp; size\ncall _malloc\nmov rsi, rax\ntest r13d, r13d\njle short loc_11F0\nmov ecx, 0\nloc_11DC:\nmov eax, [r12+rcx]\ncdq\nidiv dword ptr [rbx+rcx]\nmov [rsi+rcx], edx\nadd rcx, 4\ncmp rbp, rcx\njnz short loc_11DC\nloc_11F0:\nmov rax, rsi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11A9(__int64 a1, __int64 a2, int a3)\n{\n size_t v5; // rbp\n char *v6; // rsi\n __int64 v7; // rcx\n\n v5 = 4LL * a3;\n v6 = (char *)malloc(v5);\n if ( a3 > 0 )\n {\n v7 = 0LL;\n do\n {\n *(_DWORD *)&v6[v7] = *(_DWORD *)(a1 + v7) % *(_DWORD *)(a2 + v7);\n v7 += 4LL;\n }\n while ( v5 != v7 );\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11A9(long long a1, long long a2, int a3) {\n unsigned int v5;\n char *v6;\n long long v7;\n v5 = 4LL * a3;\n v6 = (char *)malloc(v5);\n if (a3 > 0) {\n v7 = 0LL;\n do {\n *(uint32_t *)&v6[v7] = *(uint32_t *)(a1 + v7) % *(uint32_t *)(a2 + v7);\n v7 += 4LL;\n } while (v5 != v7);\n }\n return v6;\n}", + "ida_pseudo_norm": "char *func0(long long a1, long long a2, int a3) {\n unsigned int v5;\n char *v6;\n long long v7;\n v5 = 4LL * a3;\n v6 = (char *)malloc(v5);\n if (a3 > 0) {\n v7 = 0LL;\n do {\n *(uint32_t *)&v6[v7] = *(uint32_t *)(a1 + v7) % *(uint32_t *)(a2 + v7);\n v7 += 4LL;\n } while (v5 != v7);\n }\n return v6;\n}" + }, + { + "index": 358, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int *func0(int *nums1, int *nums2, int size) {\n int *result = malloc(size * sizeof(int));\n for (int i = 0; i < size; i++) {\n result[i] = nums1[i] % nums2[i];\n }\n return result;\n}", + "test": "int main() {\n\n int nums1_1[] = {4, 5, 6};\n\n int nums2_1[] = {1, 2, 3};\n\n int *result1 = func0(nums1_1, nums2_1, 3);\n\n assert(result1[0] == 0 && result1[1] == 1 && result1[2] == 0);\n\n free(result1);\n\n\n\n int nums1_2[] = {3, 2};\n\n int nums2_2[] = {1, 4};\n\n int *result2 = func0(nums1_2, nums2_2, 2);\n\n assert(result2[0] == 0 && result2[1] == 2);\n\n free(result2);\n\n\n\n int nums1_3[] = {90, 120};\n\n int nums2_3[] = {50, 70};\n\n int *result3 = func0(nums1_3, nums2_3, 2);\n\n assert(result3[0] == 40 && result3[1] == 50);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\nmov %rdi,%rbp\nmovslq %edx,%rdi\npush %rbx\nmov %rdi,%r12\nshl $0x2,%rdi\nmov %rsi,%rbx\ncallq 10b0 \nmov %rax,%r8\ntest %r12d,%r12d\njle 1388 \nlea -0x1(%r12),%esi\nxor %ecx,%ecx\nnopl 0x0(%rax)\nmov 0x0(%rbp,%rcx,4),%eax\ncltd\nidivl (%rbx,%rcx,4)\nmov %rcx,%rax\nmov %edx,(%r8,%rcx,4)\nadd $0x1,%rcx\ncmp %rsi,%rax\njne 1370 \npop %rbx\nmov %r8,%rax\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\nmov r12, rdi\npush rbp\nmovsxd rbp, edx\npush rbx\nmov r13, rbp\nshl rbp, 2\nmov rbx, rsi\nmov rdi, rbp; size\nsub rsp, 8\ncall _malloc\nmov rsi, rax\ntest r13d, r13d\njle short loc_1374\nxor ecx, ecx\nloc_1360:\nmov eax, [r12+rcx]\ncdq\nidiv dword ptr [rbx+rcx]\nmov [rsi+rcx], edx\nadd rcx, 4\ncmp rbp, rcx\njnz short loc_1360\nloc_1374:\nadd rsp, 8\nmov rax, rsi\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n size_t v4; // rbp\n char *v6; // rsi\n __int64 v7; // rcx\n\n v4 = 4LL * a3;\n v6 = (char *)malloc(v4);\n if ( a3 > 0 )\n {\n v7 = 0LL;\n do\n {\n *(_DWORD *)&v6[v7] = *(_DWORD *)(a1 + v7) % *(_DWORD *)(a2 + v7);\n v7 += 4LL;\n }\n while ( v4 != v7 );\n }\n return v6;\n}", + "ida_strip_asm": "sub_1330:\nendbr64\npush r13\npush r12\nmov r12, rdi\npush rbp\nmovsxd rbp, edx\npush rbx\nmov r13, rbp\nshl rbp, 2\nmov rbx, rsi\nmov rdi, rbp; size\nsub rsp, 8\ncall _malloc\nmov rsi, rax\ntest r13d, r13d\njle short loc_1374\nxor ecx, ecx\nloc_1360:\nmov eax, [r12+rcx]\ncdq\nidiv dword ptr [rbx+rcx]\nmov [rsi+rcx], edx\nadd rcx, 4\ncmp rbp, rcx\njnz short loc_1360\nloc_1374:\nadd rsp, 8\nmov rax, rsi\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1330(__int64 a1, __int64 a2, int a3)\n{\n size_t v4; // rbp\n char *v6; // rsi\n __int64 v7; // rcx\n\n v4 = 4LL * a3;\n v6 = (char *)malloc(v4);\n if ( a3 > 0 )\n {\n v7 = 0LL;\n do\n {\n *(_DWORD *)&v6[v7] = *(_DWORD *)(a1 + v7) % *(_DWORD *)(a2 + v7);\n v7 += 4LL;\n }\n while ( v4 != v7 );\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1330(long long a1, long long a2, int a3) {\n unsigned int v4;\n char *v6;\n long long v7;\n v4 = 4LL * a3;\n v6 = (char *)malloc(v4);\n if (a3 > 0) {\n v7 = 0LL;\n do {\n *(uint32_t *)&v6[v7] = *(uint32_t *)(a1 + v7) % *(uint32_t *)(a2 + v7);\n v7 += 4LL;\n } while (v4 != v7);\n }\n return v6;\n}", + "ida_pseudo_norm": "char *func0(long long a1, long long a2, int a3) {\n unsigned int v4;\n char *v6;\n long long v7;\n v4 = 4LL * a3;\n v6 = (char *)malloc(v4);\n if (a3 > 0) {\n v7 = 0LL;\n do {\n *(uint32_t *)&v6[v7] = *(uint32_t *)(a1 + v7) % *(uint32_t *)(a2 + v7);\n v7 += 4LL;\n } while (v4 != v7);\n }\n return v6;\n}" + }, + { + "index": 358, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int *func0(int *nums1, int *nums2, int size) {\n int *result = malloc(size * sizeof(int));\n for (int i = 0; i < size; i++) {\n result[i] = nums1[i] % nums2[i];\n }\n return result;\n}", + "test": "int main() {\n\n int nums1_1[] = {4, 5, 6};\n\n int nums2_1[] = {1, 2, 3};\n\n int *result1 = func0(nums1_1, nums2_1, 3);\n\n assert(result1[0] == 0 && result1[1] == 1 && result1[2] == 0);\n\n free(result1);\n\n\n\n int nums1_2[] = {3, 2};\n\n int nums2_2[] = {1, 4};\n\n int *result2 = func0(nums1_2, nums2_2, 2);\n\n assert(result2[0] == 0 && result2[1] == 2);\n\n free(result2);\n\n\n\n int nums1_3[] = {90, 120};\n\n int nums2_3[] = {50, 70};\n\n int *result3 = func0(nums1_3, nums2_3, 2);\n\n assert(result3[0] == 40 && result3[1] == 50);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\nmov %rdi,%rbp\nmovslq %edx,%rdi\npush %rbx\nmov %rdi,%r12\nshl $0x2,%rdi\nmov %rsi,%rbx\ncallq 10b0 \nmov %rax,%r8\ntest %r12d,%r12d\njle 1388 \nlea -0x1(%r12),%esi\nxor %ecx,%ecx\nnopl 0x0(%rax)\nmov 0x0(%rbp,%rcx,4),%eax\ncltd\nidivl (%rbx,%rcx,4)\nmov %rcx,%rax\nmov %edx,(%r8,%rcx,4)\nadd $0x1,%rcx\ncmp %rax,%rsi\njne 1370 \npop %rbx\nmov %r8,%rax\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\nmov r12, rdi\npush rbp\nmovsxd rbp, edx\npush rbx\nmov r13, rbp\nshl rbp, 2\nmov rbx, rsi\nmov rdi, rbp; size\nsub rsp, 8\ncall _malloc\nmov rsi, rax\ntest r13d, r13d\njle short loc_1374\nxor ecx, ecx\nloc_1360:\nmov eax, [r12+rcx]\ncdq\nidiv dword ptr [rbx+rcx]\nmov [rsi+rcx], edx\nadd rcx, 4\ncmp rbp, rcx\njnz short loc_1360\nloc_1374:\nadd rsp, 8\nmov rax, rsi\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n size_t v4; // rbp\n char *v6; // rsi\n __int64 v7; // rcx\n\n v4 = 4LL * a3;\n v6 = (char *)malloc(v4);\n if ( a3 > 0 )\n {\n v7 = 0LL;\n do\n {\n *(_DWORD *)&v6[v7] = *(_DWORD *)(a1 + v7) % *(_DWORD *)(a2 + v7);\n v7 += 4LL;\n }\n while ( v4 != v7 );\n }\n return v6;\n}", + "ida_strip_asm": "sub_1330:\nendbr64\npush r13\npush r12\nmov r12, rdi\npush rbp\nmovsxd rbp, edx\npush rbx\nmov r13, rbp\nshl rbp, 2\nmov rbx, rsi\nmov rdi, rbp; size\nsub rsp, 8\ncall _malloc\nmov rsi, rax\ntest r13d, r13d\njle short loc_1374\nxor ecx, ecx\nloc_1360:\nmov eax, [r12+rcx]\ncdq\nidiv dword ptr [rbx+rcx]\nmov [rsi+rcx], edx\nadd rcx, 4\ncmp rbp, rcx\njnz short loc_1360\nloc_1374:\nadd rsp, 8\nmov rax, rsi\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1330(__int64 a1, __int64 a2, int a3)\n{\n size_t v4; // rbp\n char *v6; // rsi\n __int64 v7; // rcx\n\n v4 = 4LL * a3;\n v6 = (char *)malloc(v4);\n if ( a3 > 0 )\n {\n v7 = 0LL;\n do\n {\n *(_DWORD *)&v6[v7] = *(_DWORD *)(a1 + v7) % *(_DWORD *)(a2 + v7);\n v7 += 4LL;\n }\n while ( v4 != v7 );\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1330(long long a1, long long a2, int a3) {\n unsigned int v4;\n char *v6;\n long long v7;\n v4 = 4LL * a3;\n v6 = (char *)malloc(v4);\n if (a3 > 0) {\n v7 = 0LL;\n do {\n *(uint32_t *)&v6[v7] = *(uint32_t *)(a1 + v7) % *(uint32_t *)(a2 + v7);\n v7 += 4LL;\n } while (v4 != v7);\n }\n return v6;\n}", + "ida_pseudo_norm": "char *func0(long long a1, long long a2, int a3) {\n unsigned int v4;\n char *v6;\n long long v7;\n v4 = 4LL * a3;\n v6 = (char *)malloc(v4);\n if (a3 > 0) {\n v7 = 0LL;\n do {\n *(uint32_t *)&v6[v7] = *(uint32_t *)(a1 + v7) % *(uint32_t *)(a2 + v7);\n v7 += 4LL;\n } while (v4 != v7);\n }\n return v6;\n}" + }, + { + "index": 359, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "char* func0(int a, int b, int c) {\n if (2 * b * b == 9 * a * c) {\n return \"Yes\";\n } else {\n return \"No\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(1, 3, 2), \"Yes\") == 0);\n\n assert(strcmp(func0(1, 2, 3), \"No\") == 0);\n\n assert(strcmp(func0(1, -5, 6), \"No\") == 0);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov %esi,-0x8(%rbp)\nmov %edx,-0xc(%rbp)\nmov -0x8(%rbp),%eax\nimul %eax,%eax\nlea (%rax,%rax,1),%ecx\nmov -0x4(%rbp),%eax\nimul -0xc(%rbp),%eax\nmov %eax,%edx\nmov %edx,%eax\nshl $0x3,%eax\nadd %edx,%eax\ncmp %eax,%ecx\njne 11a0 \nlea 0xe6a(%rip),%rax\njmp 11a7 \nlea 0xe65(%rip),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov [rbp+var_C], edx\nmov eax, [rbp+var_8]\nimul eax, eax\nlea ecx, [rax+rax]\nmov eax, [rbp+var_4]\nimul eax, [rbp+var_C]\nmov edx, eax\nmov eax, edx\nshl eax, 3\nadd eax, edx\ncmp ecx, eax\njnz short loc_11A0\nlea rax, s2; \"Yes\"\njmp short loc_11A7\nloc_11A0:\nlea rax, aNo; \"No\"\nloc_11A7:\npop rbp\nretn", + "ida_pseudo": "const char *__fastcall func0(int a1, int a2, int a3)\n{\n if ( 2 * a2 * a2 == 9 * a3 * a1 )\n return \"Yes\";\n else\n return \"No\";\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov [rbp+var_C], edx\nmov eax, [rbp+var_8]\nimul eax, eax\nlea ecx, [rax+rax]\nmov eax, [rbp+var_4]\nimul eax, [rbp+var_C]\nmov edx, eax\nmov eax, edx\nshl eax, 3\nadd eax, edx\ncmp ecx, eax\njnz short loc_11A0\nlea rax, s2; \"Yes\"\njmp short loc_11A7\nloc_11A0:\nlea rax, aNo; \"No\"\nloc_11A7:\npop rbp\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1169(int a1, int a2, int a3)\n{\n if ( 2 * a2 * a2 == 9 * a3 * a1 )\n return \"Yes\";\n else\n return \"No\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char* sub_1169(int a1, int a2, int a3) {\n if (2 * a2 * a2 == 9 * a3 * a1)\n return \"Yes\";\n else\n return \"No\";\n}", + "ida_pseudo_norm": "const char* func0(int a1, int a2, int a3) {\n if (2 * a2 * a2 == 9 * a3 * a1)\n return \"Yes\";\n else\n return \"No\";\n}" + }, + { + "index": 360, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int result = pow(2, n) - 1;\n return result * result - 2;\n}", + "test": "int main() {\n\n assert(func0(2) == 7);\n\n assert(func0(4) == 223);\n\n assert(func0(5) == 959);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %edi,-0x14(%rbp)\ncvtsi2sdl -0x14(%rbp),%xmm0\nmov 0xef4(%rip),%rax\nmovapd %xmm0,%xmm1\nmovq %rax,%xmm0\ncallq 1060 \nmovsd 0xee6(%rip),%xmm1\nsubsd %xmm1,%xmm0\ncvttsd2si %xmm0,%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nimul %eax,%eax\nsub $0x2,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_14]\nmov rax, cs:x\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\nmovq rax, xmm0\nmovsd xmm0, cs:qword_2068\nmovq xmm1, rax\nsubsd xmm1, xmm0\ncvttsd2si eax, xmm1\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\nimul eax, eax\nsub eax, 2\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n double v1; // rax\n\n v1 = pow(2.0, (double)a1);\n return (unsigned int)((int)(v1 - 1.0) * (int)(v1 - 1.0) - 2);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_14]\nmov rax, cs:x\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\nmovq rax, xmm0\nmovsd xmm0, cs:qword_2068\nmovq xmm1, rax\nsubsd xmm1, xmm0\ncvttsd2si eax, xmm1\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\nimul eax, eax\nsub eax, 2\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n double v1; // rax\n\n v1 = pow(2.0, (double)a1);\n return (unsigned int)((int)(v1 - 1.0) * (int)(v1 - 1.0) - 2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n double v1;\n v1 = pow(2.0, (double)a1);\n return (unsigned int)((int)(v1 - 1.0) * (int)(v1 - 1.0) - 2);\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n double v1;\n v1 = pow(2.0, (double)a1);\n return (unsigned int)((int)(v1 - 1.0) * (int)(v1 - 1.0) - 2);\n}" + }, + { + "index": 360, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int result = pow(2, n) - 1;\n return result * result - 2;\n}", + "test": "int main() {\n\n assert(func0(2) == 7);\n\n assert(func0(4) == 223);\n\n assert(func0(5) == 959);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x8,%rsp\npxor %xmm1,%xmm1\ncvtsi2sd %edi,%xmm1\nmovsd 0xef7(%rip),%xmm0\ncallq 1060 \nsubsd 0xef2(%rip),%xmm0\ncvttsd2si %xmm0,%eax\nimul %eax,%eax\nsub $0x2,%eax\nadd $0x8,%rsp\nretq\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\npxor xmm1, xmm1\ncvtsi2sd xmm1, edi; y\nmovsd xmm0, cs:x; x\ncall _pow\nsubsd xmm0, cs:qword_2068\ncvttsd2si eax, xmm0\nimul eax, eax\nsub eax, 2\nadd rsp, 8\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n double v1; // xmm0_8\n\n v1 = pow(2.0, (double)a1);\n return (unsigned int)((int)(v1 - 1.0) * (int)(v1 - 1.0) - 2);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nsub rsp, 8\npxor xmm1, xmm1\ncvtsi2sd xmm1, edi; y\nmovsd xmm0, cs:x; x\ncall _pow\nsubsd xmm0, cs:qword_2068\ncvttsd2si eax, xmm0\nimul eax, eax\nsub eax, 2\nadd rsp, 8\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n double v1; // xmm0_8\n\n v1 = pow(2.0, (double)a1);\n return (unsigned int)((int)(v1 - 1.0) * (int)(v1 - 1.0) - 2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n double v1;\n v1 = pow(2.0, (double)a1);\n return (unsigned int)((int)(v1 - 1.0) * (int)(v1 - 1.0) - 2);\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n double v1;\n v1 = pow(2.0, (double)a1);\n return (unsigned int)((int)(v1 - 1.0) * (int)(v1 - 1.0) - 2);\n}" + }, + { + "index": 360, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int result = pow(2, n) - 1;\n return result * result - 2;\n}", + "test": "int main() {\n\n assert(func0(2) == 7);\n\n assert(func0(4) == 223);\n\n assert(func0(5) == 959);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npxor %xmm1,%xmm1\nsub $0x8,%rsp\nmovsd 0xe94(%rip),%xmm0\ncvtsi2sd %edi,%xmm1\ncallq 1050 \nsubsd 0xe8b(%rip),%xmm0\nadd $0x8,%rsp\ncvttsd2si %xmm0,%eax\nimul %eax,%eax\nsub $0x2,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npxor xmm1, xmm1\nsub rsp, 8\nmovsd xmm0, cs:x; x\ncvtsi2sd xmm1, edi; y\ncall _pow\nsubsd xmm0, cs:qword_2068\nadd rsp, 8\ncvttsd2si eax, xmm0\nimul eax, eax\nsub eax, 2\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n double v1; // xmm0_8\n\n v1 = pow(2.0, (double)a1);\n return (unsigned int)((int)(v1 - 1.0) * (int)(v1 - 1.0) - 2);\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npxor xmm1, xmm1\nsub rsp, 8\nmovsd xmm0, cs:x; x\ncvtsi2sd xmm1, edi; y\ncall _pow\nsubsd xmm0, cs:qword_2068\nadd rsp, 8\ncvttsd2si eax, xmm0\nimul eax, eax\nsub eax, 2\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(int a1)\n{\n double v1; // xmm0_8\n\n v1 = pow(2.0, (double)a1);\n return (unsigned int)((int)(v1 - 1.0) * (int)(v1 - 1.0) - 2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(int a1) {\n double v1;\n v1 = pow(2.0, (double)a1);\n return (unsigned int)((int)(v1 - 1.0) * (int)(v1 - 1.0) - 2);\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n double v1;\n v1 = pow(2.0, (double)a1);\n return (unsigned int)((int)(v1 - 1.0) * (int)(v1 - 1.0) - 2);\n}" + }, + { + "index": 360, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int result = pow(2, n) - 1;\n return result * result - 2;\n}", + "test": "int main() {\n\n assert(func0(2) == 7);\n\n assert(func0(4) == 223);\n\n assert(func0(5) == 959);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npxor %xmm1,%xmm1\nsub $0x8,%rsp\nmovsd 0xe94(%rip),%xmm0\ncvtsi2sd %edi,%xmm1\ncallq 1050 \nsubsd 0xe8b(%rip),%xmm0\nadd $0x8,%rsp\ncvttsd2si %xmm0,%eax\nimul %eax,%eax\nsub $0x2,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npxor xmm1, xmm1\nsub rsp, 8\nmovsd xmm0, cs:x; x\ncvtsi2sd xmm1, edi; y\ncall _pow\nsubsd xmm0, cs:qword_2010\nadd rsp, 8\ncvttsd2si eax, xmm0\nimul eax, eax\nsub eax, 2\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n double v1; // xmm0_8\n\n v1 = pow(2.0, (double)a1);\n return (unsigned int)((int)(v1 - 1.0) * (int)(v1 - 1.0) - 2);\n}", + "ida_strip_asm": "sub_1160:\nendbr64\npxor xmm1, xmm1\nsub rsp, 8\nmovsd xmm0, cs:x; x\ncvtsi2sd xmm1, edi; y\ncall _pow\nsubsd xmm0, cs:qword_2010\nadd rsp, 8\ncvttsd2si eax, xmm0\nimul eax, eax\nsub eax, 2\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1160(int a1)\n{\n double v1; // xmm0_8\n\n v1 = pow(2.0, (double)a1);\n return (unsigned int)((int)(v1 - 1.0) * (int)(v1 - 1.0) - 2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1160(int a1) {\n double v1;\n v1 = pow(2.0, (double)a1);\n return (unsigned int)((int)(v1 - 1.0) * (int)(v1 - 1.0) - 2);\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n double v1;\n v1 = pow(2.0, (double)a1);\n return (unsigned int)((int)(v1 - 1.0) * (int)(v1 - 1.0) - 2);\n}" + }, + { + "index": 361, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char* list1[], int size, char* result[]) {\n int k = 0;\n for (int i = 0; i < size; i++) {\n if (strcmp(list1[i], \"\") != 0) {\n result[k++] = list1[i];\n }\n }\n return k;\n}", + "test": "int main() {\n\n // Test data\n\n char* list1[] = {\"\", \"\", \"\", \"Red\", \"Green\", \"12\", \"Blue\", \"\", \"\"};\n\n char* expected1[] = {\"Red\", \"Green\", \"12\", \"Blue\"};\n\n char* result1[4];\n\n\n\n char* list2[] = {\"\", \"\", \"\", \"\", \"\", \"Green\", \"12\", \"Blue\", \"\", \"\"};\n\n char* expected2[] = {\"Green\", \"12\", \"Blue\"};\n\n char* result2[3];\n\n\n\n char* list3[] = {\"\", \"\", \"\", \"Python\", \"\", \"\", \"programming\", \"language\", \"\", \"\", \"\", \"\", \"\"};\n\n char* expected3[] = {\"Python\", \"programming\", \"language\"};\n\n char* result3[3];\n\n\n\n // Test case1\n\n int resSize1 = func0(list1, 9, result1);\n\n assert(resSize1 == 4);\n\n for (int i = 0; i < resSize1; i++) {\n\n assert(strcmp(result1[i], expected1[i]) == 0);\n\n }\n\n\n\n // Test case2\n\n int resSize2 = func0(list2, 10, result2);\n\n assert(resSize2 == 3);\n\n for (int i = 0; i < resSize2; i++) {\n\n assert(strcmp(result2[i], expected2[i]) == 0);\n\n }\n\n\n\n // Test case3\n\n int resSize3 = func0(list3, 13, result3);\n\n assert(resSize3 == 3);\n\n for (int i = 0; i < resSize3; i++) {\n\n assert(strcmp(result3[i], expected3[i]) == 0);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 1206 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmovzbl (%rax),%eax\nmovzbl %al,%eax\ntest %eax,%eax\nje 1202 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x8(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x8(%rbp)\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x28(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%rax\nmov %rax,(%rdx)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11ac \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_1206\nloc_11AC:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmovzx eax, byte ptr [rax]\nmovzx eax, al\ntest eax, eax\njz short loc_1202\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_8]\nlea edx, [rax+1]\nmov [rbp+var_8], edx\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov rax, [rcx]\nmov [rdx], rax\nloc_1202:\nadd [rbp+var_4], 1\nloc_1206:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11AC\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3)\n{\n int v3; // eax\n unsigned int v5; // [rsp+20h] [rbp-8h]\n int i; // [rsp+24h] [rbp-4h]\n\n v5 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( **(_BYTE **)(8LL * i + a1) )\n {\n v3 = v5++;\n *(_QWORD *)(a3 + 8LL * v3) = *(_QWORD *)(8LL * i + a1);\n }\n }\n return v5;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_1206\nloc_11AC:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmovzx eax, byte ptr [rax]\nmovzx eax, al\ntest eax, eax\njz short loc_1202\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_8]\nlea edx, [rax+1]\nmov [rbp+var_8], edx\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov rax, [rcx]\nmov [rdx], rax\nloc_1202:\nadd [rbp+var_4], 1\nloc_1206:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11AC\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2, __int64 a3)\n{\n int v3; // eax\n unsigned int v5; // [rsp+20h] [rbp-8h]\n int i; // [rsp+24h] [rbp-4h]\n\n v5 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( **(_BYTE **)(8LL * i + a1) )\n {\n v3 = v5++;\n *(_QWORD *)(a3 + 8LL * v3) = *(_QWORD *)(8LL * i + a1);\n }\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2, long long a3) {\n int v3;\n unsigned int v5;\n int i;\n v5 = 0;\n for (i = 0; i < a2; ++i) {\n if (**(uint8_t **)(8LL * i + a1)) {\n v3 = v5++;\n *(uint64_t *)(a3 + 8LL * v3) = *(uint64_t *)(8LL * i + a1);\n }\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3) {\n int v3;\n unsigned int v5;\n int i;\n v5 = 0;\n for (i = 0; i < a2; ++i) {\n if (**(uint8_t **)(8LL * i + a1)) {\n v3 = v5++;\n *(uint64_t *)(a3 + 8LL * v3) = *(uint64_t *)(8LL * i + a1);\n }\n }\n return v5;\n}" + }, + { + "index": 361, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char* list1[], int size, char* result[]) {\n int k = 0;\n for (int i = 0; i < size; i++) {\n if (strcmp(list1[i], \"\") != 0) {\n result[k++] = list1[i];\n }\n }\n return k;\n}", + "test": "int main() {\n\n // Test data\n\n char* list1[] = {\"\", \"\", \"\", \"Red\", \"Green\", \"12\", \"Blue\", \"\", \"\"};\n\n char* expected1[] = {\"Red\", \"Green\", \"12\", \"Blue\"};\n\n char* result1[4];\n\n\n\n char* list2[] = {\"\", \"\", \"\", \"\", \"\", \"Green\", \"12\", \"Blue\", \"\", \"\"};\n\n char* expected2[] = {\"Green\", \"12\", \"Blue\"};\n\n char* result2[3];\n\n\n\n char* list3[] = {\"\", \"\", \"\", \"Python\", \"\", \"\", \"programming\", \"language\", \"\", \"\", \"\", \"\", \"\"};\n\n char* expected3[] = {\"Python\", \"programming\", \"language\"};\n\n char* result3[3];\n\n\n\n // Test case1\n\n int resSize1 = func0(list1, 9, result1);\n\n assert(resSize1 == 4);\n\n for (int i = 0; i < resSize1; i++) {\n\n assert(strcmp(result1[i], expected1[i]) == 0);\n\n }\n\n\n\n // Test case2\n\n int resSize2 = func0(list2, 10, result2);\n\n assert(resSize2 == 3);\n\n for (int i = 0; i < resSize2; i++) {\n\n assert(strcmp(result2[i], expected2[i]) == 0);\n\n }\n\n\n\n // Test case3\n\n int resSize3 = func0(list3, 13, result3);\n\n assert(resSize3 == 3);\n\n for (int i = 0; i < resSize3; i++) {\n\n assert(strcmp(result3[i], expected3[i]) == 0);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11c0 \nmov %rdi,%rax\nlea -0x1(%rsi),%ecx\nlea 0x8(%rdi,%rcx,8),%rdi\nmov $0x0,%esi\njmp 11ac \nadd $0x8,%rax\ncmp %rdi,%rax\nje 11c5 \nmov (%rax),%rcx\ncmpb $0x0,(%rcx)\nje 11a3 \nmovslq %esi,%r8\nmov %rcx,(%rdx,%r8,8)\nlea 0x1(%rsi),%esi\njmp 11a3 \nmov $0x0,%esi\nmov %esi,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11BF\nmov rax, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*8]\nmov esi, 0\njmp short loc_11AB\nloc_11A2:\nadd rax, 8\ncmp rax, rdi\njz short loc_11C4\nloc_11AB:\nmov rcx, [rax]\ncmp byte ptr [rcx], 0\njz short loc_11A2\nmovsxd r8, esi\nmov [rdx+r8*8], rcx\nlea esi, [rsi+1]\njmp short loc_11A2\nloc_11BF:\nmov esi, 0\nloc_11C4:\nmov eax, esi\nretn", + "ida_pseudo": "__int64 __fastcall func0(_QWORD *a1, int a2, __int64 a3)\n{\n _QWORD *v3; // rax\n _QWORD *v4; // rdi\n unsigned int v5; // esi\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n do\n {\n if ( *(_BYTE *)*v3 )\n *(_QWORD *)(a3 + 8LL * (int)v5++) = *v3;\n ++v3;\n }\n while ( v3 != v4 );\n }\n return v5;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\ntest esi, esi\njle short loc_11BF\nmov rax, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*8]\nmov esi, 0\njmp short loc_11AB\nloc_11A2:\nadd rax, 8\ncmp rax, rdi\njz short loc_11C4\nloc_11AB:\nmov rcx, [rax]\ncmp byte ptr [rcx], 0\njz short loc_11A2\nmovsxd r8, esi\nmov [rdx+r8*8], rcx\nlea esi, [rsi+1]\njmp short loc_11A2\nloc_11BF:\nmov esi, 0\nloc_11C4:\nmov eax, esi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(_QWORD *a1, int a2, __int64 a3)\n{\n _QWORD *v3; // rax\n _QWORD *v4; // rdi\n unsigned int v5; // esi\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n do\n {\n if ( *(_BYTE *)*v3 )\n *(_QWORD *)(a3 + 8LL * (int)v5++) = *v3;\n ++v3;\n }\n while ( v3 != v4 );\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(uint64_t *a1, int a2, long long a3) {\n uint64_t *v3;\n uint64_t *v4;\n unsigned int v5;\n if (a2 <= 0) {\n return 0;\n } else {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n do {\n if (*(uint8_t *)*v3) *(uint64_t *)(a3 + 8LL * (int)v5++) = *v3;\n ++v3;\n } while (v3 != v4);\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(uint64_t *a1, int a2, long long a3) {\n uint64_t *v3;\n uint64_t *v4;\n unsigned int v5;\n if (a2 <= 0) {\n return 0;\n } else {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n do {\n if (*(uint8_t *)*v3) *(uint64_t *)(a3 + 8LL * (int)v5++) = *v3;\n ++v3;\n } while (v3 != v4);\n }\n return v5;\n}" + }, + { + "index": 361, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char* list1[], int size, char* result[]) {\n int k = 0;\n for (int i = 0; i < size; i++) {\n if (strcmp(list1[i], \"\") != 0) {\n result[k++] = list1[i];\n }\n }\n return k;\n}", + "test": "int main() {\n\n // Test data\n\n char* list1[] = {\"\", \"\", \"\", \"Red\", \"Green\", \"12\", \"Blue\", \"\", \"\"};\n\n char* expected1[] = {\"Red\", \"Green\", \"12\", \"Blue\"};\n\n char* result1[4];\n\n\n\n char* list2[] = {\"\", \"\", \"\", \"\", \"\", \"Green\", \"12\", \"Blue\", \"\", \"\"};\n\n char* expected2[] = {\"Green\", \"12\", \"Blue\"};\n\n char* result2[3];\n\n\n\n char* list3[] = {\"\", \"\", \"\", \"Python\", \"\", \"\", \"programming\", \"language\", \"\", \"\", \"\", \"\", \"\"};\n\n char* expected3[] = {\"Python\", \"programming\", \"language\"};\n\n char* result3[3];\n\n\n\n // Test case1\n\n int resSize1 = func0(list1, 9, result1);\n\n assert(resSize1 == 4);\n\n for (int i = 0; i < resSize1; i++) {\n\n assert(strcmp(result1[i], expected1[i]) == 0);\n\n }\n\n\n\n // Test case2\n\n int resSize2 = func0(list2, 10, result2);\n\n assert(resSize2 == 3);\n\n for (int i = 0; i < resSize2; i++) {\n\n assert(strcmp(result2[i], expected2[i]) == 0);\n\n }\n\n\n\n // Test case3\n\n int resSize3 = func0(list3, 13, result3);\n\n assert(resSize3 == 3);\n\n for (int i = 0; i < resSize3; i++) {\n\n assert(strcmp(result3[i], expected3[i]) == 0);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 15c0 \nlea -0x1(%rsi),%eax\nxor %r8d,%r8d\nlea 0x8(%rdi,%rax,8),%rcx\nnopl 0x0(%rax,%rax,1)\nmov (%rdi),%rax\ncmpb $0x0,(%rax)\nje 15ab \nmovslq %r8d,%rsi\nadd $0x1,%r8d\nmov %rax,(%rdx,%rsi,8)\nadd $0x8,%rdi\ncmp %rcx,%rdi\njne 1598 \nmov %r8d,%eax\nretq\nnopl 0x0(%rax,%rax,1)\nxor %r8d,%r8d\nmov %r8d,%eax\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1510\nmovsxd rsi, esi\nxor ecx, ecx\nlea rsi, [rdi+rsi*8]\nnop dword ptr [rax+00000000h]\nloc_14E8:\nmov rax, [rdi]\ncmp byte ptr [rax], 0\njz short loc_14FA\nmovsxd r8, ecx\nadd ecx, 1\nmov [rdx+r8*8], rax\nloc_14FA:\nadd rdi, 8\ncmp rdi, rsi\njnz short loc_14E8\nmov eax, ecx\nretn\nloc_1510:\nxor ecx, ecx\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(_QWORD *a1, int a2, __int64 a3)\n{\n unsigned int v3; // ecx\n _QWORD *v4; // rsi\n __int64 v5; // r8\n\n if ( a2 <= 0 )\n return 0LL;\n v3 = 0;\n v4 = &a1[a2];\n do\n {\n if ( *(_BYTE *)*a1 )\n {\n v5 = (int)v3++;\n *(_QWORD *)(a3 + 8 * v5) = *a1;\n }\n ++a1;\n }\n while ( a1 != v4 );\n return v3;\n}", + "ida_strip_asm": "sub_14D0:\nendbr64\ntest esi, esi\njle short loc_1510\nmovsxd rsi, esi\nxor ecx, ecx\nlea rsi, [rdi+rsi*8]\nnop dword ptr [rax+00000000h]\nloc_14E8:\nmov rax, [rdi]\ncmp byte ptr [rax], 0\njz short loc_14FA\nmovsxd r8, ecx\nadd ecx, 1\nmov [rdx+r8*8], rax\nloc_14FA:\nadd rdi, 8\ncmp rdi, rsi\njnz short loc_14E8\nmov eax, ecx\nretn\nloc_1510:\nxor ecx, ecx\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_14D0(_QWORD *a1, int a2, __int64 a3)\n{\n unsigned int v3; // ecx\n _QWORD *v4; // rsi\n __int64 v5; // r8\n\n if ( a2 <= 0 )\n return 0LL;\n v3 = 0;\n v4 = &a1[a2];\n do\n {\n if ( *(_BYTE *)*a1 )\n {\n v5 = (int)v3++;\n *(_QWORD *)(a3 + 8 * v5) = *a1;\n }\n ++a1;\n }\n while ( a1 != v4 );\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_14D0(uint64_t *a1, int a2, long long a3) {\n unsigned int v3;\n uint64_t *v4;\n long long v5;\n if (a2 <= 0) return 0LL;\n v3 = 0;\n v4 = &a1[a2];\n do {\n if (*(uint8_t *)*a1) {\n v5 = (int)v3++;\n *(uint64_t *)(a3 + 8 * v5) = *a1;\n }\n ++a1;\n } while (a1 != v4);\n return v3;\n}", + "ida_pseudo_norm": "long long func0(uint64_t *a1, int a2, long long a3) {\n unsigned int v3;\n uint64_t *v4;\n long long v5;\n if (a2 <= 0) return 0LL;\n v3 = 0;\n v4 = &a1[a2];\n do {\n if (*(uint8_t *)*a1) {\n v5 = (int)v3++;\n *(uint64_t *)(a3 + 8 * v5) = *a1;\n }\n ++a1;\n } while (a1 != v4);\n return v3;\n}" + }, + { + "index": 362, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int nums[], int size) {\n int max_val = 0;\n int result = nums[0];\n for (int i = 0; i < size; i++) {\n int occu = 0;\n for (int j = 0; j < size; j++) {\n if (nums[j] == nums[i]) {\n occu++;\n }\n }\n if (occu > max_val) {\n max_val = occu;\n result = nums[i];\n }\n }\n return result;\n}", + "test": "int main() {\n\n int arr1[] = {1,2,3,1,2,3,12,4,2};\n\n int arr2[] = {1,2,6,7,0,1,0,1,0};\n\n int arr3[] = {1,2,3,1,2,4,1};\n\n \n\n assert(func0(arr1, 9) == 2);\n\n assert(func0(arr2, 9) == 1);\n\n assert(func0(arr3, 7) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmovl $0x0,-0x14(%rbp)\nmov -0x28(%rbp),%rax\nmov (%rax),%eax\nmov %eax,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 120c \nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11d9 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 11d5 \naddl $0x1,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 11a1 \nmov -0x8(%rbp),%eax\ncmp -0x14(%rbp),%eax\njle 1208 \nmov -0x8(%rbp),%eax\nmov %eax,-0x14(%rbp)\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x10(%rbp)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 1191 \nmov -0x10(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_14], 0\nmov rax, [rbp+var_28]\nmov eax, [rax]\nmov [rbp+var_10], eax\nmov [rbp+var_C], 0\njmp short loc_120C\nloc_1191:\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11D9\nloc_11A1:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11D5\nadd [rbp+var_8], 1\nloc_11D5:\nadd [rbp+var_4], 1\nloc_11D9:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_2C]\njl short loc_11A1\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_14]\njle short loc_1208\nmov eax, [rbp+var_8]\nmov [rbp+var_14], eax\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_10], eax\nloc_1208:\nadd [rbp+var_C], 1\nloc_120C:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_2C]\njl loc_1191\nmov eax, [rbp+var_10]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n int v3; // [rsp+18h] [rbp-14h]\n unsigned int v4; // [rsp+1Ch] [rbp-10h]\n int i; // [rsp+20h] [rbp-Ch]\n int v6; // [rsp+24h] [rbp-8h]\n int j; // [rsp+28h] [rbp-4h]\n\n v3 = 0;\n v4 = *a1;\n for ( i = 0; i < a2; ++i )\n {\n v6 = 0;\n for ( j = 0; j < a2; ++j )\n {\n if ( a1[j] == a1[i] )\n ++v6;\n }\n if ( v6 > v3 )\n {\n v3 = v6;\n v4 = a1[i];\n }\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_14], 0\nmov rax, [rbp+var_28]\nmov eax, [rax]\nmov [rbp+var_10], eax\nmov [rbp+var_C], 0\njmp short loc_120C\nloc_1191:\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11D9\nloc_11A1:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11D5\nadd [rbp+var_8], 1\nloc_11D5:\nadd [rbp+var_4], 1\nloc_11D9:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_2C]\njl short loc_11A1\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_14]\njle short loc_1208\nmov eax, [rbp+var_8]\nmov [rbp+var_14], eax\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_10], eax\nloc_1208:\nadd [rbp+var_C], 1\nloc_120C:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_2C]\njl loc_1191\nmov eax, [rbp+var_10]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(unsigned int *a1, int a2)\n{\n int v3; // [rsp+18h] [rbp-14h]\n unsigned int v4; // [rsp+1Ch] [rbp-10h]\n int i; // [rsp+20h] [rbp-Ch]\n int v6; // [rsp+24h] [rbp-8h]\n int j; // [rsp+28h] [rbp-4h]\n\n v3 = 0;\n v4 = *a1;\n for ( i = 0; i < a2; ++i )\n {\n v6 = 0;\n for ( j = 0; j < a2; ++j )\n {\n if ( a1[j] == a1[i] )\n ++v6;\n }\n if ( v6 > v3 )\n {\n v3 = v6;\n v4 = a1[i];\n }\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(unsigned int *a1, int a2) {\n int v3;\n unsigned int v4;\n int i;\n int v6;\n int j;\n v3 = 0;\n v4 = *a1;\n for (i = 0; i < a2; ++i) {\n v6 = 0;\n for (j = 0; j < a2; ++j) {\n if (a1[j] == a1[i]) ++v6;\n }\n if (v6 > v3) {\n v3 = v6;\n v4 = a1[i];\n }\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n int v3;\n unsigned int v4;\n int i;\n int v6;\n int j;\n v3 = 0;\n v4 = *a1;\n for (i = 0; i < a2; ++i) {\n v6 = 0;\n for (j = 0; j < a2; ++j) {\n if (a1[j] == a1[i]) ++v6;\n }\n if (v6 > v3) {\n v3 = v6;\n v4 = a1[i];\n }\n }\n return v4;\n}" + }, + { + "index": 362, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int nums[], int size) {\n int max_val = 0;\n int result = nums[0];\n for (int i = 0; i < size; i++) {\n int occu = 0;\n for (int j = 0; j < size; j++) {\n if (nums[j] == nums[i]) {\n occu++;\n }\n }\n if (occu > max_val) {\n max_val = occu;\n result = nums[i];\n }\n }\n return result;\n}", + "test": "int main() {\n\n int arr1[] = {1,2,3,1,2,3,12,4,2};\n\n int arr2[] = {1,2,6,7,0,1,0,1,0};\n\n int arr3[] = {1,2,3,1,2,4,1};\n\n \n\n assert(func0(arr1, 9) == 2);\n\n assert(func0(arr2, 9) == 1);\n\n assert(func0(arr3, 7) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov (%rdi),%r11d\ntest %esi,%esi\njle 11ba \nmov %rdi,%r10\nlea -0x1(%rsi),%eax\nlea 0x4(%rdi,%rax,4),%r8\nmov $0x0,%r9d\njmp 1190 \nadd $0x4,%rdi\ncmp %r8,%rdi\nje 11ba \nmov (%rdi),%esi\nmov %r10,%rax\nmov $0x0,%edx\ncmp %esi,(%rax)\nsete %cl\nmovzbl %cl,%ecx\nadd %ecx,%edx\nadd $0x4,%rax\ncmp %r8,%rax\njne 119a \ncmp %r9d,%edx\njle 1187 \nmov %esi,%r11d\nmov %edx,%r9d\njmp 1187 \nmov %r11d,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov r11d, [rdi]\ntest esi, esi\njle short loc_11BA\nmovsxd rsi, esi\nlea r8, [rdi+rsi*4]\nmov r9, rdi\nmov r10d, 0\njmp short loc_118F\nloc_1186:\nadd r9, 4\ncmp r9, r8\njz short loc_11BA\nloc_118F:\nmov esi, [r9]\nmov rax, rdi\nmov edx, 0\nloc_119A:\ncmp [rax], esi\nsetz cl\nmovzx ecx, cl\nadd edx, ecx\nadd rax, 4\ncmp rax, r8\njnz short loc_119A\ncmp edx, r10d\njle short loc_1186\nmov r11d, esi\nmov r10d, edx\njmp short loc_1186\nloc_11BA:\nmov eax, r11d\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n unsigned int v2; // r11d\n unsigned int *v3; // r8\n unsigned int *v4; // r9\n int v5; // r10d\n unsigned int *v6; // rax\n int v7; // edx\n\n v2 = *a1;\n if ( a2 > 0 )\n {\n v3 = &a1[a2];\n v4 = a1;\n v5 = 0;\n do\n {\n v6 = a1;\n v7 = 0;\n do\n v7 += *v6++ == *v4;\n while ( v6 != v3 );\n if ( v7 > v5 )\n {\n v2 = *v4;\n v5 = v7;\n }\n ++v4;\n }\n while ( v4 != v3 );\n }\n return v2;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov r11d, [rdi]\ntest esi, esi\njle short loc_11BA\nmovsxd rsi, esi\nlea r8, [rdi+rsi*4]\nmov r9, rdi\nmov r10d, 0\njmp short loc_118F\nloc_1186:\nadd r9, 4\ncmp r9, r8\njz short loc_11BA\nloc_118F:\nmov esi, [r9]\nmov rax, rdi\nmov edx, 0\nloc_119A:\ncmp [rax], esi\nsetz cl\nmovzx ecx, cl\nadd edx, ecx\nadd rax, 4\ncmp rax, r8\njnz short loc_119A\ncmp edx, r10d\njle short loc_1186\nmov r11d, esi\nmov r10d, edx\njmp short loc_1186\nloc_11BA:\nmov eax, r11d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(unsigned int *a1, int a2)\n{\n unsigned int v2; // r11d\n unsigned int *v3; // r8\n unsigned int *v4; // r9\n int v5; // r10d\n unsigned int *v6; // rax\n int v7; // edx\n\n v2 = *a1;\n if ( a2 > 0 )\n {\n v3 = &a1[a2];\n v4 = a1;\n v5 = 0;\n do\n {\n v6 = a1;\n v7 = 0;\n do\n v7 += *v6++ == *v4;\n while ( v6 != v3 );\n if ( v7 > v5 )\n {\n v2 = *v4;\n v5 = v7;\n }\n ++v4;\n }\n while ( v4 != v3 );\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(unsigned int *a1, int a2) {\n unsigned int v2;\n unsigned int *v3;\n unsigned int *v4;\n int v5;\n unsigned int *v6;\n int v7;\n v2 = *a1;\n if (a2 > 0) {\n v3 = &a1[a2];\n v4 = a1;\n v5 = 0;\n do {\n v6 = a1;\n v7 = 0;\n do\n v7 += *v6++ == *v4;\n while (v6 != v3);\n if (v7 > v5) {\n v2 = *v4;\n v5 = v7;\n }\n ++v4;\n } while (v4 != v3);\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n unsigned int v2;\n unsigned int *v3;\n unsigned int *v4;\n int v5;\n unsigned int *v6;\n int v7;\n v2 = *a1;\n if (a2 > 0) {\n v3 = &a1[a2];\n v4 = a1;\n v5 = 0;\n do {\n v6 = a1;\n v7 = 0;\n do\n v7 += *v6++ == *v4;\n while (v6 != v3);\n if (v7 > v5) {\n v2 = *v4;\n v5 = v7;\n }\n ++v4;\n } while (v4 != v3);\n }\n return v2;\n}" + }, + { + "index": 362, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int nums[], int size) {\n int max_val = 0;\n int result = nums[0];\n for (int i = 0; i < size; i++) {\n int occu = 0;\n for (int j = 0; j < size; j++) {\n if (nums[j] == nums[i]) {\n occu++;\n }\n }\n if (occu > max_val) {\n max_val = occu;\n result = nums[i];\n }\n }\n return result;\n}", + "test": "int main() {\n\n int arr1[] = {1,2,3,1,2,3,12,4,2};\n\n int arr2[] = {1,2,6,7,0,1,0,1,0};\n\n int arr3[] = {1,2,3,1,2,4,1};\n\n \n\n assert(func0(arr1, 9) == 2);\n\n assert(func0(arr2, 9) == 1);\n\n assert(func0(arr3, 7) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov (%rdi),%r11d\ntest %esi,%esi\njle 1346 \nlea 0x4(%rdi),%r9\nlea -0x1(%rsi),%eax\nmov %r11d,%r12d\nmov %r11d,%esi\nlea (%r9,%rax,4),%rdi\nmov %r9,%r8\nxor %r10d,%r10d\nnopl 0x0(%rax)\nmov %r9,%rax\nmov %r11d,%ecx\nxor %edx,%edx\njmp 131e \nnopw 0x0(%rax,%rax,1)\nmov (%rax),%ecx\nadd $0x4,%rax\ncmp %ecx,%esi\nsete %cl\nmovzbl %cl,%ecx\nadd %ecx,%edx\ncmp %rdi,%rax\njne 1318 \ncmp %r10d,%edx\njle 1338 \nmov %esi,%r12d\nmov %edx,%r10d\ncmp %rdi,%r8\nje 1349 \nmov (%r8),%esi\nadd $0x4,%r8\njmp 1308 \nmov %r11d,%r12d\nmov %r12d,%eax\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\nmov r11d, [rdi]\ntest esi, esi\njle short loc_12F6\nmovsxd rsi, esi\nmov r9, rdi\nxor r10d, r10d\nlea r8, [rdi+rsi*4]\nnop dword ptr [rax+rax+00000000h]\nloc_12C0:\nmov esi, [r9]\nmov rax, rdi\nxor edx, edx\nnop dword ptr [rax+rax+00000000h]\nloc_12D0:\nxor ecx, ecx\ncmp esi, [rax]\nsetz cl\nadd rax, 4\nadd edx, ecx\ncmp r8, rax\njnz short loc_12D0\ncmp edx, r10d\njle short loc_12ED\nmov r11d, esi\nmov r10d, edx\nloc_12ED:\nadd r9, 4\ncmp r8, r9\njnz short loc_12C0\nloc_12F6:\nmov eax, r11d\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n unsigned int v2; // r11d\n unsigned int *v3; // r9\n int v4; // r10d\n unsigned int *v5; // r8\n unsigned int *v6; // rax\n int v7; // edx\n int v8; // ecx\n\n v2 = *a1;\n if ( a2 > 0 )\n {\n v3 = a1;\n v4 = 0;\n v5 = &a1[a2];\n do\n {\n v6 = a1;\n v7 = 0;\n do\n {\n v8 = *v3 == *v6++;\n v7 += v8;\n }\n while ( v5 != v6 );\n if ( v7 > v4 )\n {\n v2 = *v3;\n v4 = v7;\n }\n ++v3;\n }\n while ( v5 != v3 );\n }\n return v2;\n}", + "ida_strip_asm": "sub_12A0:\nendbr64\nmov r11d, [rdi]\ntest esi, esi\njle short loc_12F6\nmovsxd rsi, esi\nmov r9, rdi\nxor r10d, r10d\nlea r8, [rdi+rsi*4]\nnop dword ptr [rax+rax+00000000h]\nloc_12C0:\nmov esi, [r9]\nmov rax, rdi\nxor edx, edx\nnop dword ptr [rax+rax+00000000h]\nloc_12D0:\nxor ecx, ecx\ncmp esi, [rax]\nsetz cl\nadd rax, 4\nadd edx, ecx\ncmp r8, rax\njnz short loc_12D0\ncmp edx, r10d\njle short loc_12ED\nmov r11d, esi\nmov r10d, edx\nloc_12ED:\nadd r9, 4\ncmp r8, r9\njnz short loc_12C0\nloc_12F6:\nmov eax, r11d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12A0(unsigned int *a1, int a2)\n{\n unsigned int v2; // r11d\n unsigned int *v3; // r9\n int v4; // r10d\n unsigned int *v5; // r8\n unsigned int *v6; // rax\n int v7; // edx\n int v8; // ecx\n\n v2 = *a1;\n if ( a2 > 0 )\n {\n v3 = a1;\n v4 = 0;\n v5 = &a1[a2];\n do\n {\n v6 = a1;\n v7 = 0;\n do\n {\n v8 = *v3 == *v6++;\n v7 += v8;\n }\n while ( v5 != v6 );\n if ( v7 > v4 )\n {\n v2 = *v3;\n v4 = v7;\n }\n ++v3;\n }\n while ( v5 != v3 );\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12A0(unsigned int *a1, int a2) {\n unsigned int v2;\n unsigned int *v3;\n int v4;\n unsigned int *v5;\n unsigned int *v6;\n int v7;\n int v8;\n v2 = *a1;\n if (a2 > 0) {\n v3 = a1;\n v4 = 0;\n v5 = &a1[a2];\n do {\n v6 = a1;\n v7 = 0;\n do {\n v8 = *v3 == *v6++;\n v7 += v8;\n } while (v5 != v6);\n if (v7 > v4) {\n v2 = *v3;\n v4 = v7;\n }\n ++v3;\n } while (v5 != v3);\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n unsigned int v2;\n unsigned int *v3;\n int v4;\n unsigned int *v5;\n unsigned int *v6;\n int v7;\n int v8;\n v2 = *a1;\n if (a2 > 0) {\n v3 = a1;\n v4 = 0;\n v5 = &a1[a2];\n do {\n v6 = a1;\n v7 = 0;\n do {\n v8 = *v3 == *v6++;\n v7 += v8;\n } while (v5 != v6);\n if (v7 > v4) {\n v2 = *v3;\n v4 = v7;\n }\n ++v3;\n } while (v5 != v3);\n }\n return v2;\n}" + }, + { + "index": 362, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int nums[], int size) {\n int max_val = 0;\n int result = nums[0];\n for (int i = 0; i < size; i++) {\n int occu = 0;\n for (int j = 0; j < size; j++) {\n if (nums[j] == nums[i]) {\n occu++;\n }\n }\n if (occu > max_val) {\n max_val = occu;\n result = nums[i];\n }\n }\n return result;\n}", + "test": "int main() {\n\n int arr1[] = {1,2,3,1,2,3,12,4,2};\n\n int arr2[] = {1,2,6,7,0,1,0,1,0};\n\n int arr3[] = {1,2,3,1,2,4,1};\n\n \n\n assert(func0(arr1, 9) == 2);\n\n assert(func0(arr2, 9) == 1);\n\n assert(func0(arr3, 7) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\nmov (%rdi),%r13d\npush %r12\npush %rbp\npush %rbx\ntest %esi,%esi\njle 13a6 \nmov %esi,%edx\nlea -0x1(%rsi),%eax\nmov %esi,%r11d\nmov %rdi,%r9\nshr $0x2,%edx\nmov %rax,%rbp\nlea 0x4(%rdi,%rax,4),%r12\nand $0xfffffffc,%r11d\nshl $0x4,%rdx\nxor %ebx,%ebx\nadd %rdi,%rdx\nnopw 0x0(%rax,%rax,1)\nmov (%r9),%ecx\ncmp $0x3,%ebp\njbe 13b8 \nmovd %ecx,%xmm3\nmov %rdi,%rax\npxor %xmm1,%xmm1\npshufd $0x0,%xmm3,%xmm2\nnopl 0x0(%rax)\nmovdqu (%rax),%xmm0\nadd $0x10,%rax\npcmpeqd %xmm2,%xmm0\npsubd %xmm0,%xmm1\ncmp %rax,%rdx\njne 1300 \nmovdqa %xmm1,%xmm0\nmov %r11d,%r8d\npsrldq $0x8,%xmm0\npaddd %xmm0,%xmm1\nmovdqa %xmm1,%xmm0\npsrldq $0x4,%xmm0\npaddd %xmm0,%xmm1\nmovd %xmm1,%eax\ncmp %esi,%r11d\nje 1390 \nmovslq %r8d,%r14\ncmp %ecx,(%rdi,%r14,4)\nlea 0x0(,%r14,4),%r10\nsete %r14b\nmovzbl %r14b,%r14d\nadd %r14d,%eax\nlea 0x1(%r8),%r14d\ncmp %esi,%r14d\njge 1390 \ncmp 0x4(%rdi,%r10,1),%ecx\njne 1368 \nadd $0x1,%eax\nlea 0x2(%r8),%r14d\ncmp %esi,%r14d\njge 1390 \ncmp 0x8(%rdi,%r10,1),%ecx\njne 137b \nadd $0x1,%eax\nadd $0x3,%r8d\ncmp %r8d,%esi\njle 1390 \ncmp 0xc(%rdi,%r10,1),%ecx\njne 1390 \nadd $0x1,%eax\nxchg %ax,%ax\ncmp %eax,%ebx\njge 1399 \nmov %ecx,%r13d\nmov %eax,%ebx\nadd $0x4,%r9\ncmp %r12,%r9\njne 12e0 \npop %rbx\nmov %r13d,%eax\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopw 0x0(%rax,%rax,1)\nxor %r8d,%r8d\nxor %eax,%eax\njmpq 133b \nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\nmov r13d, [rdi]\npush r12\npush rbp\npush rbx\ntest esi, esi\njle loc_138A\nmov edx, esi\nmovsxd rax, esi\nmov r11d, esi\nmov r8, rdi\nshr edx, 2\nmov r9d, esi\nlea r12, [rdi+rax*4]\nand r11d, 0FFFFFFFCh\nshl rdx, 4\nlea ebp, [rsi-1]\nxor ebx, ebx\nadd rdx, rdi\nnop dword ptr [rax+00h]\nloc_12E0:\nmov esi, [rdi]\ncmp ebp, 2\njbe loc_13A0\nmovd xmm3, esi\nmov rax, r8\npxor xmm1, xmm1\npshufd xmm2, xmm3, 0\nnop dword ptr [rax+rax+00h]\nloc_1300:\nmovdqu xmm0, xmmword ptr [rax]\nadd rax, 10h\npcmpeqd xmm0, xmm2\npsubd xmm1, xmm0\ncmp rdx, rax\njnz short loc_1300\nmovdqa xmm0, xmm1\nmov ecx, r11d\npsrldq xmm0, 8\npaddd xmm1, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm0, 4\npaddd xmm1, xmm0\nmovd eax, xmm1\ncmp r9d, r11d\njz short loc_1374\nloc_133B:\nmovsxd r10, ecx\nlea r14, ds:0[r10*4]\ncmp [r8+r10*4], esi\njnz short loc_134F\nadd eax, 1\nloc_134F:\nlea r10d, [rcx+1]\ncmp r9d, r10d\njle short loc_1374\ncmp esi, [r8+r14+4]\njnz short loc_1362\nadd eax, 1\nloc_1362:\nadd ecx, 2\ncmp ecx, r9d\njge short loc_1374\ncmp esi, [r8+r14+8]\njnz short loc_1374\nadd eax, 1\nloc_1374:\ncmp ebx, eax\njge short loc_137D\nmov r13d, esi\nmov ebx, eax\nloc_137D:\nadd rdi, 4\ncmp r12, rdi\njnz loc_12E0\nloc_138A:\npop rbx\nmov eax, r13d\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_13A0:\nxor ecx, ecx\nxor eax, eax\njmp short loc_133B", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n unsigned int v2; // r13d\n const __m128i *v3; // r8\n unsigned int *v5; // r12\n unsigned int v6; // r11d\n unsigned int v7; // ebp\n int v8; // ebx\n const __m128i *v9; // rdx\n unsigned int v10; // esi\n const __m128i *v11; // rax\n __m128i v12; // xmm1\n __m128i v13; // xmm2\n __m128i v14; // xmm0\n signed int v15; // ecx\n __m128i v16; // xmm1\n int v17; // eax\n __int64 v18; // r14\n\n v2 = *a1;\n if ( a2 > 0 )\n {\n v3 = (const __m128i *)a1;\n v5 = &a1[a2];\n v6 = a2 & 0xFFFFFFFC;\n v7 = a2 - 1;\n v8 = 0;\n v9 = (const __m128i *)&a1[4 * ((unsigned int)a2 >> 2)];\n while ( 1 )\n {\n v10 = *a1;\n if ( v7 <= 2 )\n break;\n v11 = v3;\n v12 = 0LL;\n v13 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v10), 0);\n do\n {\n v14 = _mm_loadu_si128(v11++);\n v12 = _mm_sub_epi32(v12, _mm_cmpeq_epi32(v14, v13));\n }\n while ( v9 != v11 );\n v15 = v6;\n v16 = _mm_add_epi32(v12, _mm_srli_si128(v12, 8));\n v17 = _mm_cvtsi128_si32(_mm_add_epi32(v16, _mm_srli_si128(v16, 4)));\n if ( a2 != v6 )\n goto LABEL_7;\nLABEL_15:\n if ( v8 < v17 )\n {\n v2 = *a1;\n v8 = v17;\n }\n if ( v5 == ++a1 )\n return v2;\n }\n v15 = 0;\n v17 = 0;\nLABEL_7:\n v18 = v15;\n if ( v3->m128i_i32[v18] == v10 )\n ++v17;\n if ( a2 > v15 + 1 )\n {\n if ( v10 == v3->m128i_i32[v18 + 1] )\n ++v17;\n if ( v15 + 2 < a2 && v10 == v3->m128i_i32[v18 + 2] )\n ++v17;\n }\n goto LABEL_15;\n }\n return v2;\n}", + "ida_strip_asm": "sub_12A0:\nendbr64\npush r14\npush r13\nmov r13d, [rdi]\npush r12\npush rbp\npush rbx\ntest esi, esi\njle loc_138A\nmov edx, esi\nmovsxd rax, esi\nmov r11d, esi\nmov r8, rdi\nshr edx, 2\nmov r9d, esi\nlea r12, [rdi+rax*4]\nand r11d, 0FFFFFFFCh\nshl rdx, 4\nlea ebp, [rsi-1]\nxor ebx, ebx\nadd rdx, rdi\nnop dword ptr [rax+00h]\nloc_12E0:\nmov esi, [rdi]\ncmp ebp, 2\njbe loc_13A0\nmovd xmm3, esi\nmov rax, r8\npxor xmm1, xmm1\npshufd xmm2, xmm3, 0\nnop dword ptr [rax+rax+00h]\nloc_1300:\nmovdqu xmm0, xmmword ptr [rax]\nadd rax, 10h\npcmpeqd xmm0, xmm2\npsubd xmm1, xmm0\ncmp rdx, rax\njnz short loc_1300\nmovdqa xmm0, xmm1\nmov ecx, r11d\npsrldq xmm0, 8\npaddd xmm1, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm0, 4\npaddd xmm1, xmm0\nmovd eax, xmm1\ncmp r9d, r11d\njz short loc_1374\nloc_133B:\nmovsxd r10, ecx\nlea r14, ds:0[r10*4]\ncmp [r8+r10*4], esi\njnz short loc_134F\nadd eax, 1\nloc_134F:\nlea r10d, [rcx+1]\ncmp r9d, r10d\njle short loc_1374\ncmp esi, [r8+r14+4]\njnz short loc_1362\nadd eax, 1\nloc_1362:\nadd ecx, 2\ncmp ecx, r9d\njge short loc_1374\ncmp esi, [r8+r14+8]\njnz short loc_1374\nadd eax, 1\nloc_1374:\ncmp ebx, eax\njge short loc_137D\nmov r13d, esi\nmov ebx, eax\nloc_137D:\nadd rdi, 4\ncmp r12, rdi\njnz loc_12E0\nloc_138A:\npop rbx\nmov eax, r13d\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_13A0:\nxor ecx, ecx\nxor eax, eax\njmp short loc_133B", + "ida_strip_pseudo": "__int64 __fastcall sub_12A0(unsigned int *a1, int a2)\n{\n unsigned int v2; // r13d\n const __m128i *v3; // r8\n unsigned int *v5; // r12\n unsigned int v6; // r11d\n unsigned int v7; // ebp\n int v8; // ebx\n const __m128i *v9; // rdx\n unsigned int v10; // esi\n const __m128i *v11; // rax\n __m128i v12; // xmm1\n __m128i v13; // xmm2\n __m128i v14; // xmm0\n signed int v15; // ecx\n __m128i v16; // xmm1\n int v17; // eax\n __int64 v18; // r14\n\n v2 = *a1;\n if ( a2 > 0 )\n {\n v3 = (const __m128i *)a1;\n v5 = &a1[a2];\n v6 = a2 & 0xFFFFFFFC;\n v7 = a2 - 1;\n v8 = 0;\n v9 = (const __m128i *)&a1[4 * ((unsigned int)a2 >> 2)];\n while ( 1 )\n {\n v10 = *a1;\n if ( v7 <= 2 )\n break;\n v11 = v3;\n v12 = 0LL;\n v13 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v10), 0);\n do\n {\n v14 = _mm_loadu_si128(v11++);\n v12 = _mm_sub_epi32(v12, _mm_cmpeq_epi32(v14, v13));\n }\n while ( v9 != v11 );\n v15 = v6;\n v16 = _mm_add_epi32(v12, _mm_srli_si128(v12, 8));\n v17 = _mm_cvtsi128_si32(_mm_add_epi32(v16, _mm_srli_si128(v16, 4)));\n if ( a2 != v6 )\n goto LABEL_7;\nLABEL_15:\n if ( v8 < v17 )\n {\n v2 = *a1;\n v8 = v17;\n }\n if ( v5 == ++a1 )\n return v2;\n }\n v15 = 0;\n v17 = 0;\nLABEL_7:\n v18 = v15;\n if ( v3->m128i_i32[v18] == v10 )\n ++v17;\n if ( a2 > v15 + 1 )\n {\n if ( v10 == v3->m128i_i32[v18 + 1] )\n ++v17;\n if ( v15 + 2 < a2 && v10 == v3->m128i_i32[v18 + 2] )\n ++v17;\n }\n goto LABEL_15;\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12A0(unsigned int *a1, int a2) {\n unsigned int v2;\n const __m128i *v3;\n unsigned int *v5;\n unsigned int v6;\n unsigned int v7;\n int v8;\n const __m128i *v9;\n unsigned int v10;\n const __m128i *v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n signed int v15;\n __m128i v16;\n int v17;\n long long v18;\n v2 = *a1;\n if (a2 > 0) {\n v3 = (const __m128i *)a1;\n v5 = &a1[a2];\n v6 = a2 & 4294967292;\n v7 = a2 - 1;\n v8 = 0;\n v9 = (const __m128i *)&a1[4 * ((unsigned int)a2 >> 2)];\n while (1) {\n v10 = *a1;\n if (v7 <= 2) break;\n v11 = v3;\n v12 = 0LL;\n v13 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v10), 0);\n do {\n v14 = _mm_loadu_si128(v11++);\n v12 = _mm_sub_epi32(v12, _mm_cmpeq_epi32(v14, v13));\n } while (v9 != v11);\n v15 = v6;\n v16 = _mm_add_epi32(v12, _mm_srli_si128(v12, 8));\n v17 = _mm_cvtsi128_si32(_mm_add_epi32(v16, _mm_srli_si128(v16, 4)));\n if (a2 != v6) goto LABEL_7;\n LABEL_15:\n if (v8 < v17) {\n v2 = *a1;\n v8 = v17;\n }\n if (v5 == ++a1) return v2;\n }\n v15 = 0;\n v17 = 0;\n LABEL_7:\n v18 = v15;\n if (v3->m128i_i32[v18] == v10) ++v17;\n if (a2 > v15 + 1) {\n if (v10 == v3->m128i_i32[v18 + 1]) ++v17;\n if (v15 + 2 < a2 && v10 == v3->m128i_i32[v18 + 2]) ++v17;\n }\n goto LABEL_15;\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n unsigned int v2;\n const __m128i *v3;\n unsigned int *v5;\n unsigned int v6;\n unsigned int v7;\n int v8;\n const __m128i *v9;\n unsigned int v10;\n const __m128i *v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n signed int v15;\n __m128i v16;\n int v17;\n long long v18;\n v2 = *a1;\n if (a2 > 0) {\n v3 = (const __m128i *)a1;\n v5 = &a1[a2];\n v6 = a2 & 4294967292;\n v7 = a2 - 1;\n v8 = 0;\n v9 = (const __m128i *)&a1[4 * ((unsigned int)a2 >> 2)];\n while (1) {\n v10 = *a1;\n if (v7 <= 2) break;\n v11 = v3;\n v12 = 0LL;\n v13 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v10), 0);\n do {\n v14 = _mm_loadu_si128(v11++);\n v12 = _mm_sub_epi32(v12, _mm_cmpeq_epi32(v14, v13));\n } while (v9 != v11);\n v15 = v6;\n v16 = _mm_add_epi32(v12, _mm_srli_si128(v12, 8));\n v17 = _mm_cvtsi128_si32(_mm_add_epi32(v16, _mm_srli_si128(v16, 4)));\n if (a2 != v6) goto LABEL_7;\n LABEL_15:\n if (v8 < v17) {\n v2 = *a1;\n v8 = v17;\n }\n if (v5 == ++a1) return v2;\n }\n v15 = 0;\n v17 = 0;\n LABEL_7:\n v18 = v15;\n if (v3->m128i_i32[v18] == v10) ++v17;\n if (a2 > v15 + 1) {\n if (v10 == v3->m128i_i32[v18 + 1]) ++v17;\n if (v15 + 2 < a2 && v10 == v3->m128i_i32[v18 + 2]) ++v17;\n }\n goto LABEL_15;\n }\n return v2;\n}" + }, + { + "index": 363, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "void func0(int test_list[][3], int size, int K, int result[][3]) {\n for (int i = 0; i < size; i++) {\n for (int j = 0; j < 3; j++) {\n result[i][j] = test_list[i][j] + K;\n }\n }\n}", + "test": "int main() {\n\n int test_list1[3][3] = {{1, 3, 4}, {2, 4, 6}, {3, 8, 1}};\n\n int result1[3][3];\n\n func0(test_list1, 3, 4, result1);\n\n int expected1[3][3] = {{5, 7, 8}, {6, 8, 10}, {7, 12, 5}};\n\n for(int i = 0; i < 3; i++) {\n\n for(int j = 0; j < 3; j++) {\n\n assert(result1[i][j] == expected1[i][j]);\n\n }\n\n }\n\n\n\n int test_list2[3][3] = {{1, 2, 3}, {4, 5, 6}, {7, 8, 9}};\n\n int result2[3][3];\n\n func0(test_list2, 3, 8, result2);\n\n int expected2[3][3] = {{9, 10, 11}, {12, 13, 14}, {15, 16, 17}};\n\n for(int i = 0; i < 3; i++) {\n\n for(int j = 0; j < 3; j++) {\n\n assert(result2[i][j] == expected2[i][j]);\n\n }\n\n }\n\n\n\n int test_list3[3][3] = {{11, 12, 13}, {14, 15, 16}, {17, 18, 19}};\n\n int result3[3][3];\n\n func0(test_list3, 3, 9, result3);\n\n int expected3[3][3] = {{20, 21, 22}, {23, 24, 25}, {26, 27, 28}};\n\n for(int i = 0; i < 3; i++) {\n\n for(int j = 0; j < 3; j++) {\n\n assert(result3[i][j] == expected3[i][j]);\n\n }\n\n }\n\n \n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmov %rcx,-0x28(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11ee \nmovl $0x0,-0x4(%rbp)\njmp 11e4 \nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0x4(%rbp),%eax\ncltq\nmov (%rdx,%rax,4),%ecx\nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x28(%rbp),%rax\nadd %rax,%rdx\nmov -0x20(%rbp),%eax\nadd %eax,%ecx\nmov -0x4(%rbp),%eax\ncltq\nmov %ecx,(%rdx,%rax,4)\naddl $0x1,-0x4(%rbp)\ncmpl $0x2,-0x4(%rbp)\njle 1191 \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1188 \npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_28], rcx\nmov [rbp+var_8], 0\njmp short loc_11EE\nloc_1188:\nmov [rbp+var_4], 0\njmp short loc_11E4\nloc_1191:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\ncdqe\nmov ecx, [rdx+rax*4]\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov eax, [rbp+var_20]\nadd ecx, eax\nmov eax, [rbp+var_4]\ncdqe\nmov [rdx+rax*4], ecx\nadd [rbp+var_4], 1\nloc_11E4:\ncmp [rbp+var_4], 2\njle short loc_1191\nadd [rbp+var_8], 1\nloc_11EE:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nnop\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3, __int64 a4)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+20h] [rbp-8h]\n int j; // [rsp+24h] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a2 )\n break;\n for ( j = 0; j <= 2; ++j )\n *(_DWORD *)(a4 + 12LL * (int)i + 4LL * j) = a3 + *(_DWORD *)(a1 + 12LL * (int)i + 4LL * j);\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_28], rcx\nmov [rbp+var_8], 0\njmp short loc_11EE\nloc_1188:\nmov [rbp+var_4], 0\njmp short loc_11E4\nloc_1191:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\ncdqe\nmov ecx, [rdx+rax*4]\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov eax, [rbp+var_20]\nadd ecx, eax\nmov eax, [rbp+var_4]\ncdqe\nmov [rdx+rax*4], ecx\nadd [rbp+var_4], 1\nloc_11E4:\ncmp [rbp+var_4], 2\njle short loc_1191\nadd [rbp+var_8], 1\nloc_11EE:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nnop\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3, __int64 a4)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+20h] [rbp-8h]\n int j; // [rsp+24h] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a2 )\n break;\n for ( j = 0; j <= 2; ++j )\n *(_DWORD *)(a4 + 12LL * (int)i + 4LL * j) = a3 + *(_DWORD *)(a1 + 12LL * (int)i + 4LL * j);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3, long long a4) {\n long long result;\n unsigned int i;\n int j;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a2) break;\n for (j = 0; j <= 2; ++j)\n *(uint32_t *)(a4 + 12LL * (int)i + 4LL * j) =\n a3 + *(uint32_t *)(a1 + 12LL * (int)i + 4LL * j);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3, long long a4) {\n long long result;\n unsigned int i;\n int j;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a2) break;\n for (j = 0; j <= 2; ++j)\n *(uint32_t *)(a4 + 12LL * (int)i + 4LL * j) =\n a3 + *(uint32_t *)(a1 + 12LL * (int)i + 4LL * j);\n }\n return result;\n}" + }, + { + "index": 363, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "void func0(int test_list[][3], int size, int K, int result[][3]) {\n for (int i = 0; i < size; i++) {\n for (int j = 0; j < 3; j++) {\n result[i][j] = test_list[i][j] + K;\n }\n }\n}", + "test": "int main() {\n\n int test_list1[3][3] = {{1, 3, 4}, {2, 4, 6}, {3, 8, 1}};\n\n int result1[3][3];\n\n func0(test_list1, 3, 4, result1);\n\n int expected1[3][3] = {{5, 7, 8}, {6, 8, 10}, {7, 12, 5}};\n\n for(int i = 0; i < 3; i++) {\n\n for(int j = 0; j < 3; j++) {\n\n assert(result1[i][j] == expected1[i][j]);\n\n }\n\n }\n\n\n\n int test_list2[3][3] = {{1, 2, 3}, {4, 5, 6}, {7, 8, 9}};\n\n int result2[3][3];\n\n func0(test_list2, 3, 8, result2);\n\n int expected2[3][3] = {{9, 10, 11}, {12, 13, 14}, {15, 16, 17}};\n\n for(int i = 0; i < 3; i++) {\n\n for(int j = 0; j < 3; j++) {\n\n assert(result2[i][j] == expected2[i][j]);\n\n }\n\n }\n\n\n\n int test_list3[3][3] = {{11, 12, 13}, {14, 15, 16}, {17, 18, 19}};\n\n int result3[3][3];\n\n func0(test_list3, 3, 9, result3);\n\n int expected3[3][3] = {{20, 21, 22}, {23, 24, 25}, {26, 27, 28}};\n\n for(int i = 0; i < 3; i++) {\n\n for(int j = 0; j < 3; j++) {\n\n assert(result3[i][j] == expected3[i][j]);\n\n }\n\n }\n\n \n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11a3 \nmov %rdi,%rax\nlea -0x1(%rsi),%esi\nlea (%rsi,%rsi,2),%rsi\nlea 0xc(%rdi,%rsi,4),%rdi\nmov %edx,%esi\nadd (%rax),%esi\nmov %esi,(%rcx)\nmov %edx,%esi\nadd 0x4(%rax),%esi\nmov %esi,0x4(%rcx)\nmov %edx,%esi\nadd 0x8(%rax),%esi\nmov %esi,0x8(%rcx)\nadd $0xc,%rax\nadd $0xc,%rcx\ncmp %rdi,%rax\njne 1180 \nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short locret_11A2\nmov rax, rdi\nmovsxd rsi, esi\nlea rsi, [rsi+rsi*2]\nlea rdi, [rdi+rsi*4]\nloc_117F:\nmov esi, edx\nadd esi, [rax]\nmov [rcx], esi\nmov esi, edx\nadd esi, [rax+4]\nmov [rcx+4], esi\nmov esi, edx\nadd esi, [rax+8]\nmov [rcx+8], esi\nadd rax, 0Ch\nadd rcx, 0Ch\ncmp rdi, rax\njnz short loc_117F\nlocret_11A2:\nretn", + "ida_pseudo": "void __fastcall func0(_DWORD *a1, int a2, int a3, _DWORD *a4)\n{\n _DWORD *v4; // rax\n _DWORD *v5; // rdi\n\n if ( a2 > 0 )\n {\n v4 = a1;\n v5 = &a1[3 * a2];\n do\n {\n *a4 = *v4 + a3;\n a4[1] = v4[1] + a3;\n a4[2] = v4[2] + a3;\n v4 += 3;\n a4 += 3;\n }\n while ( v5 != v4 );\n }\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short locret_11A2\nmov rax, rdi\nmovsxd rsi, esi\nlea rsi, [rsi+rsi*2]\nlea rdi, [rdi+rsi*4]\nloc_117F:\nmov esi, edx\nadd esi, [rax]\nmov [rcx], esi\nmov esi, edx\nadd esi, [rax+4]\nmov [rcx+4], esi\nmov esi, edx\nadd esi, [rax+8]\nmov [rcx+8], esi\nadd rax, 0Ch\nadd rcx, 0Ch\ncmp rdi, rax\njnz short loc_117F\nlocret_11A2:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1169(_DWORD *a1, int a2, int a3, _DWORD *a4)\n{\n _DWORD *v4; // rax\n _DWORD *v5; // rdi\n\n if ( a2 > 0 )\n {\n v4 = a1;\n v5 = &a1[3 * a2];\n do\n {\n *a4 = *v4 + a3;\n a4[1] = v4[1] + a3;\n a4[2] = v4[2] + a3;\n v4 += 3;\n a4 += 3;\n }\n while ( v5 != v4 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1169(uint32_t *a1, int a2, int a3, uint32_t *a4) {\n uint32_t *v4;\n uint32_t *v5;\n if (a2 > 0) {\n v4 = a1;\n v5 = &a1[3 * a2];\n do {\n *a4 = *v4 + a3;\n a4[1] = v4[1] + a3;\n a4[2] = v4[2] + a3;\n v4 += 3;\n a4 += 3;\n } while (v5 != v4);\n }\n}", + "ida_pseudo_norm": "void func0(uint32_t *a1, int a2, int a3, uint32_t *a4) {\n uint32_t *v4;\n uint32_t *v5;\n if (a2 > 0) {\n v4 = a1;\n v5 = &a1[3 * a2];\n do {\n *a4 = *v4 + a3;\n a4[1] = v4[1] + a3;\n a4[2] = v4[2] + a3;\n v4 += 3;\n a4 += 3;\n } while (v5 != v4);\n }\n}" + }, + { + "index": 363, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "void func0(int test_list[][3], int size, int K, int result[][3]) {\n for (int i = 0; i < size; i++) {\n for (int j = 0; j < 3; j++) {\n result[i][j] = test_list[i][j] + K;\n }\n }\n}", + "test": "int main() {\n\n int test_list1[3][3] = {{1, 3, 4}, {2, 4, 6}, {3, 8, 1}};\n\n int result1[3][3];\n\n func0(test_list1, 3, 4, result1);\n\n int expected1[3][3] = {{5, 7, 8}, {6, 8, 10}, {7, 12, 5}};\n\n for(int i = 0; i < 3; i++) {\n\n for(int j = 0; j < 3; j++) {\n\n assert(result1[i][j] == expected1[i][j]);\n\n }\n\n }\n\n\n\n int test_list2[3][3] = {{1, 2, 3}, {4, 5, 6}, {7, 8, 9}};\n\n int result2[3][3];\n\n func0(test_list2, 3, 8, result2);\n\n int expected2[3][3] = {{9, 10, 11}, {12, 13, 14}, {15, 16, 17}};\n\n for(int i = 0; i < 3; i++) {\n\n for(int j = 0; j < 3; j++) {\n\n assert(result2[i][j] == expected2[i][j]);\n\n }\n\n }\n\n\n\n int test_list3[3][3] = {{11, 12, 13}, {14, 15, 16}, {17, 18, 19}};\n\n int result3[3][3];\n\n func0(test_list3, 3, 9, result3);\n\n int expected3[3][3] = {{20, 21, 22}, {23, 24, 25}, {26, 27, 28}};\n\n for(int i = 0; i < 3; i++) {\n\n for(int j = 0; j < 3; j++) {\n\n assert(result3[i][j] == expected3[i][j]);\n\n }\n\n }\n\n \n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 15bc \nlea -0x1(%rsi),%eax\nlea (%rax,%rax,2),%rax\nlea 0xc(%rdi,%rax,4),%rsi\nnopl 0x0(%rax)\nmov (%rdi),%eax\nadd $0xc,%rdi\nadd $0xc,%rcx\nadd %edx,%eax\nmov %eax,-0xc(%rcx)\nmov -0x8(%rdi),%eax\nadd %edx,%eax\nmov %eax,-0x8(%rcx)\nmov -0x4(%rdi),%eax\nadd %edx,%eax\nmov %eax,-0x4(%rcx)\ncmp %rsi,%rdi\njne 1598 \nretq\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short locret_145C\nmovsxd rsi, esi\nlea rax, [rsi+rsi*2]\nlea rsi, [rdi+rax*4]\nnop dword ptr [rax+rax+00h]\nloc_1438:\nmov eax, [rdi]\nadd rdi, 0Ch\nadd rcx, 0Ch\nadd eax, edx\nmov [rcx-0Ch], eax\nmov eax, [rdi-8]\nadd eax, edx\nmov [rcx-8], eax\nmov eax, [rdi-4]\nadd eax, edx\nmov [rcx-4], eax\ncmp rsi, rdi\njnz short loc_1438\nlocret_145C:\nretn", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2, int a3, __int64 a4)\n{\n int *v4; // rsi\n int v5; // eax\n __int64 result; // rax\n\n if ( a2 > 0 )\n {\n v4 = &a1[3 * a2];\n do\n {\n v5 = *a1;\n a1 += 3;\n a4 += 12LL;\n *(_DWORD *)(a4 - 12) = a3 + v5;\n *(_DWORD *)(a4 - 8) = a3 + *(a1 - 2);\n result = (unsigned int)(a3 + *(a1 - 1));\n *(_DWORD *)(a4 - 4) = result;\n }\n while ( v4 != a1 );\n }\n return result;\n}", + "ida_strip_asm": "sub_1420:\nendbr64\ntest esi, esi\njle short locret_145C\nmovsxd rsi, esi\nlea rax, [rsi+rsi*2]\nlea rsi, [rdi+rax*4]\nnop dword ptr [rax+rax+00h]\nloc_1438:\nmov eax, [rdi]\nadd rdi, 0Ch\nadd rcx, 0Ch\nadd eax, edx\nmov [rcx-0Ch], eax\nmov eax, [rdi-8]\nadd eax, edx\nmov [rcx-8], eax\nmov eax, [rdi-4]\nadd eax, edx\nmov [rcx-4], eax\ncmp rsi, rdi\njnz short loc_1438\nlocret_145C:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1420(int *a1, int a2, int a3, __int64 a4)\n{\n int *v4; // rsi\n int v5; // eax\n __int64 result; // rax\n\n if ( a2 > 0 )\n {\n v4 = &a1[3 * a2];\n do\n {\n v5 = *a1;\n a1 += 3;\n a4 += 12LL;\n *(_DWORD *)(a4 - 12) = a3 + v5;\n *(_DWORD *)(a4 - 8) = a3 + *(a1 - 2);\n result = (unsigned int)(a3 + *(a1 - 1));\n *(_DWORD *)(a4 - 4) = result;\n }\n while ( v4 != a1 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1420(int *a1, int a2, int a3, long long a4) {\n int *v4;\n int v5;\n long long result;\n if (a2 > 0) {\n v4 = &a1[3 * a2];\n do {\n v5 = *a1;\n a1 += 3;\n a4 += 12LL;\n *(uint32_t *)(a4 - 12) = a3 + v5;\n *(uint32_t *)(a4 - 8) = a3 + *(a1 - 2);\n result = (unsigned int)(a3 + *(a1 - 1));\n *(uint32_t *)(a4 - 4) = result;\n } while (v4 != a1);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2, int a3, long long a4) {\n int *v4;\n int v5;\n long long result;\n if (a2 > 0) {\n v4 = &a1[3 * a2];\n do {\n v5 = *a1;\n a1 += 3;\n a4 += 12LL;\n *(uint32_t *)(a4 - 12) = a3 + v5;\n *(uint32_t *)(a4 - 8) = a3 + *(a1 - 2);\n result = (unsigned int)(a3 + *(a1 - 1));\n *(uint32_t *)(a4 - 4) = result;\n } while (v4 != a1);\n }\n return result;\n}" + }, + { + "index": 364, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nchar make_flip(char ch) {\n\n return (ch == '0') ? '1' : '0';\n\n}\n\n\n\nint get_flip_with_starting_character(const char *str, char expected) {\n\n int flip_count = 0;\n\n int length = strlen(str);\n\n for (int i = 0; i < length; i++) {\n\n if (str[i] != expected) {\n\n flip_count++;\n\n }\n\n expected = make_flip(expected);\n\n }\n\n return flip_count;\n\n}\n\n\n\n", + "func": "int func0(const char *str) {\n return (get_flip_with_starting_character(str, '0') <\n get_flip_with_starting_character(str, '1'))\n ? get_flip_with_starting_character(str, '0')\n : get_flip_with_starting_character(str, '1');\n}", + "test": "int main() {\n\n assert(func0(\"0001010111\") == 2);\n\n assert(func0(\"001\") == 1);\n\n assert(func0(\"010111011\") == 2);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x18,%rsp\nmov %rdi,-0x18(%rbp)\nmov -0x18(%rbp),%rax\nmov $0x30,%esi\nmov %rax,%rdi\ncallq 118a \nmov %eax,%ebx\nmov -0x18(%rbp),%rax\nmov $0x31,%esi\nmov %rax,%rdi\ncallq 118a \ncmp %eax,%ebx\njge 1242 \nmov -0x18(%rbp),%rax\nmov $0x30,%esi\nmov %rax,%rdi\ncallq 118a \njmp 1253 \nmov -0x18(%rbp),%rax\nmov $0x31,%esi\nmov %rax,%rdi\ncallq 118a \nadd $0x18,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 18h\nmov [rbp+var_18], rdi\nmov rax, [rbp+var_18]\nmov esi, 30h ; '0'\nmov rdi, rax\ncall get_flip_with_starting_character\nmov ebx, eax\nmov rax, [rbp+var_18]\nmov esi, 31h ; '1'\nmov rdi, rax\ncall get_flip_with_starting_character\ncmp ebx, eax\njge short loc_1242\nmov rax, [rbp+var_18]\nmov esi, 30h ; '0'\nmov rdi, rax\ncall get_flip_with_starting_character\njmp short loc_1253\nloc_1242:\nmov rax, [rbp+var_18]\nmov esi, 31h ; '1'\nmov rdi, rax\ncall get_flip_with_starting_character\nloc_1253:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1)\n{\n int flip_with_starting_character; // ebx\n\n flip_with_starting_character = get_flip_with_starting_character(a1, 48LL);\n if ( flip_with_starting_character >= (int)get_flip_with_starting_character(a1, 49LL) )\n return get_flip_with_starting_character(a1, 49LL);\n else\n return get_flip_with_starting_character(a1, 48LL);\n}", + "ida_strip_asm": "sub_11F6:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 18h\nmov [rbp+var_18], rdi\nmov rax, [rbp+var_18]\nmov esi, 30h ; '0'\nmov rdi, rax\ncall sub_118A\nmov ebx, eax\nmov rax, [rbp+var_18]\nmov esi, 31h ; '1'\nmov rdi, rax\ncall sub_118A\ncmp ebx, eax\njge short loc_1242\nmov rax, [rbp+var_18]\nmov esi, 30h ; '0'\nmov rdi, rax\ncall sub_118A\njmp short loc_1253\nloc_1242:\nmov rax, [rbp+var_18]\nmov esi, 31h ; '1'\nmov rdi, rax\ncall sub_118A\nloc_1253:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11F6(__int64 a1)\n{\n int v1; // ebx\n\n v1 = sub_118A(a1, 48LL);\n if ( v1 >= (int)sub_118A(a1, 49LL) )\n return sub_118A(a1, 49LL);\n else\n return sub_118A(a1, 48LL);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11F6(long long a1) {\n int v1;\n v1 = sub_118A(a1, 48LL);\n if (v1 >= (int)sub_118A(a1, 49LL))\n return sub_118A(a1, 49LL);\n else\n return sub_118A(a1, 48LL);\n}", + "ida_pseudo_norm": "long long func0(long long a1) {\n int flip_with_starting_character;\n flip_with_starting_character = get_flip_with_starting_character(a1, 48LL);\n if (flip_with_starting_character >=\n (int)get_flip_with_starting_character(a1, 49LL))\n return get_flip_with_starting_character(a1, 49LL);\n else\n return get_flip_with_starting_character(a1, 48LL);\n}" + }, + { + "index": 364, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nchar make_flip(char ch) {\n\n return (ch == '0') ? '1' : '0';\n\n}\n\n\n\nint get_flip_with_starting_character(const char *str, char expected) {\n\n int flip_count = 0;\n\n int length = strlen(str);\n\n for (int i = 0; i < length; i++) {\n\n if (str[i] != expected) {\n\n flip_count++;\n\n }\n\n expected = make_flip(expected);\n\n }\n\n return flip_count;\n\n}\n\n\n\n", + "func": "int func0(const char *str) {\n return (get_flip_with_starting_character(str, '0') <\n get_flip_with_starting_character(str, '1'))\n ? get_flip_with_starting_character(str, '0')\n : get_flip_with_starting_character(str, '1');\n}", + "test": "int main() {\n\n assert(func0(\"0001010111\") == 2);\n\n assert(func0(\"001\") == 1);\n\n assert(func0(\"010111011\") == 2);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nmov %rdi,%rbp\nmov $0x30,%esi\ncallq 1158 \nmov %eax,%ebx\nmov $0x31,%esi\nmov %rbp,%rdi\ncallq 1158 \ncmp %eax,%ebx\ncmovle %ebx,%eax\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov esi, 30h ; '0'\ncall get_flip_with_starting_character\nmov ebx, eax\nmov esi, 31h ; '1'\nmov rdi, rbp\ncall get_flip_with_starting_character\ncmp ebx, eax\ncmovle eax, ebx\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1)\n{\n int flip_with_starting_character; // ebx\n __int64 result; // rax\n\n flip_with_starting_character = get_flip_with_starting_character(a1, 48LL);\n result = get_flip_with_starting_character(a1, 49LL);\n if ( flip_with_starting_character <= (int)result )\n return (unsigned int)flip_with_starting_character;\n return result;\n}", + "ida_strip_asm": "sub_11CA:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov esi, 30h ; '0'\ncall sub_1178\nmov ebx, eax\nmov esi, 31h ; '1'\nmov rdi, rbp\ncall sub_1178\ncmp ebx, eax\ncmovle eax, ebx\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11CA(__int64 a1)\n{\n int v1; // ebx\n __int64 result; // rax\n\n v1 = sub_1178(a1, 48LL);\n result = sub_1178(a1, 49LL);\n if ( v1 <= (int)result )\n return (unsigned int)v1;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11CA(long long a1) {\n int v1;\n long long result;\n v1 = sub_1178(a1, 48LL);\n result = sub_1178(a1, 49LL);\n if (v1 <= (int)result) return (unsigned int)v1;\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1) {\n int flip_with_starting_character;\n long long result;\n flip_with_starting_character = get_flip_with_starting_character(a1, 48LL);\n result = get_flip_with_starting_character(a1, 49LL);\n if (flip_with_starting_character <= (int)result)\n return (unsigned int)flip_with_starting_character;\n return result;\n}" + }, + { + "index": 364, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nchar make_flip(char ch) {\n\n return (ch == '0') ? '1' : '0';\n\n}\n\n\n\nint get_flip_with_starting_character(const char *str, char expected) {\n\n int flip_count = 0;\n\n int length = strlen(str);\n\n for (int i = 0; i < length; i++) {\n\n if (str[i] != expected) {\n\n flip_count++;\n\n }\n\n expected = make_flip(expected);\n\n }\n\n return flip_count;\n\n}\n\n\n\n", + "func": "int func0(const char *str) {\n return (get_flip_with_starting_character(str, '0') <\n get_flip_with_starting_character(str, '1'))\n ? get_flip_with_starting_character(str, '0')\n : get_flip_with_starting_character(str, '1');\n}", + "test": "int main() {\n\n assert(func0(\"0001010111\") == 2);\n\n assert(func0(\"001\") == 1);\n\n assert(func0(\"010111011\") == 2);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov $0x30,%esi\nmov %rdi,%rbp\npush %rbx\nsub $0x8,%rsp\ncallq 1220 \nmov %rbp,%rdi\nmov $0x31,%esi\nmov %eax,%ebx\ncallq 1220 \ncmp %eax,%ebx\ncmovle %ebx,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest eax, eax\njle short loc_1308\nsub eax, 1\nmov rdi, rbx\nxor ecx, ecx\nmov edx, 30h ; '0'\nlea rsi, [rbx+rax+1]\nmov r9d, 61h ; 'a'\nmov rax, rbx\nnop dword ptr [rax+00h]\nloc_12B0:\nxor r8d, r8d\nmov ebx, r9d\ncmp dl, [rax]\nsetnz r8b\nsub ebx, edx\nadd rax, 1\nadd ecx, r8d\nmov edx, ebx\ncmp rax, rsi\njnz short loc_12B0\nxor eax, eax\nmov edx, 31h ; '1'\nmov r9d, 61h ; 'a'\nnop dword ptr [rax+00000000h]\nloc_12E0:\nxor r8d, r8d\nmov ebx, r9d\ncmp dl, [rdi]\nsetnz r8b\nsub ebx, edx\nadd rdi, 1\nadd eax, r8d\nmov edx, ebx\ncmp rdi, rsi\njnz short loc_12E0\ncmp eax, ecx\npop rbx\ncmovg eax, ecx\nretn\nloc_1308:\nxor eax, eax\npop rbx\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v1; // eax\n int v2; // ecx\n int v3; // edx\n __int64 v4; // rsi\n const char *v5; // rax\n int v6; // r8d\n __int64 result; // rax\n int v8; // edx\n _BOOL4 v9; // r8d\n\n v1 = strlen(a1);\n if ( v1 <= 0 )\n return 0LL;\n v2 = 0;\n v3 = 48;\n v4 = (__int64)&a1[v1 - 1 + 1];\n v5 = a1;\n do\n {\n v6 = (_BYTE)v3 != *v5++;\n v2 += v6;\n v3 = 97 - v3;\n }\n while ( v5 != (const char *)v4 );\n LODWORD(result) = 0;\n v8 = 49;\n do\n {\n v9 = (_BYTE)v8 != *a1++;\n result = (unsigned int)(v9 + result);\n v8 = 97 - v8;\n }\n while ( a1 != (const char *)v4 );\n if ( (int)result > v2 )\n return (unsigned int)v2;\n return result;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest eax, eax\njle short loc_1308\nsub eax, 1\nmov rdi, rbx\nxor ecx, ecx\nmov edx, 30h ; '0'\nlea rsi, [rbx+rax+1]\nmov r9d, 61h ; 'a'\nmov rax, rbx\nnop dword ptr [rax+00h]\nloc_12B0:\nxor r8d, r8d\nmov ebx, r9d\ncmp dl, [rax]\nsetnz r8b\nsub ebx, edx\nadd rax, 1\nadd ecx, r8d\nmov edx, ebx\ncmp rax, rsi\njnz short loc_12B0\nxor eax, eax\nmov edx, 31h ; '1'\nmov r9d, 61h ; 'a'\nnop dword ptr [rax+00000000h]\nloc_12E0:\nxor r8d, r8d\nmov ebx, r9d\ncmp dl, [rdi]\nsetnz r8b\nsub ebx, edx\nadd rdi, 1\nadd eax, r8d\nmov edx, ebx\ncmp rdi, rsi\njnz short loc_12E0\ncmp eax, ecx\npop rbx\ncmovg eax, ecx\nretn\nloc_1308:\nxor eax, eax\npop rbx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1280(const char *a1)\n{\n int v1; // eax\n int v2; // ecx\n int v3; // edx\n __int64 v4; // rsi\n const char *v5; // rax\n int v6; // r8d\n __int64 result; // rax\n int v8; // edx\n _BOOL4 v9; // r8d\n\n v1 = strlen(a1);\n if ( v1 <= 0 )\n return 0LL;\n v2 = 0;\n v3 = 48;\n v4 = (__int64)&a1[v1 - 1 + 1];\n v5 = a1;\n do\n {\n v6 = (_BYTE)v3 != *v5++;\n v2 += v6;\n v3 = 97 - v3;\n }\n while ( v5 != (const char *)v4 );\n LODWORD(result) = 0;\n v8 = 49;\n do\n {\n v9 = (_BYTE)v8 != *a1++;\n result = (unsigned int)(v9 + result);\n v8 = 97 - v8;\n }\n while ( a1 != (const char *)v4 );\n if ( (int)result > v2 )\n return (unsigned int)v2;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1280(const char *a1) {\n int v1;\n int v2;\n int v3;\n long long v4;\n const char *v5;\n int v6;\n long long result;\n int v8;\n int v9;\n v1 = strlen(a1);\n if (v1 <= 0) return 0LL;\n v2 = 0;\n v3 = 48;\n v4 = (long long)&a1[v1 - 1 + 1];\n v5 = a1;\n do {\n v6 = (uint8_t)v3 != *v5++;\n v2 += v6;\n v3 = 97 - v3;\n } while (v5 != (const char *)v4);\n LODWORD(result) = 0;\n v8 = 49;\n do {\n v9 = (uint8_t)v8 != *a1++;\n result = (unsigned int)(v9 + result);\n v8 = 97 - v8;\n } while (a1 != (const char *)v4);\n if ((int)result > v2) return (unsigned int)v2;\n return result;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v1;\n int v2;\n int v3;\n long long v4;\n const char *v5;\n int v6;\n long long result;\n int v8;\n int v9;\n v1 = strlen(a1);\n if (v1 <= 0) return 0LL;\n v2 = 0;\n v3 = 48;\n v4 = (long long)&a1[v1 - 1 + 1];\n v5 = a1;\n do {\n v6 = (uint8_t)v3 != *v5++;\n v2 += v6;\n v3 = 97 - v3;\n } while (v5 != (const char *)v4);\n LODWORD(result) = 0;\n v8 = 49;\n do {\n v9 = (uint8_t)v8 != *a1++;\n result = (unsigned int)(v9 + result);\n v8 = 97 - v8;\n } while (a1 != (const char *)v4);\n if ((int)result > v2) return (unsigned int)v2;\n return result;\n}" + }, + { + "index": 364, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nchar make_flip(char ch) {\n\n return (ch == '0') ? '1' : '0';\n\n}\n\n\n\nint get_flip_with_starting_character(const char *str, char expected) {\n\n int flip_count = 0;\n\n int length = strlen(str);\n\n for (int i = 0; i < length; i++) {\n\n if (str[i] != expected) {\n\n flip_count++;\n\n }\n\n expected = make_flip(expected);\n\n }\n\n return flip_count;\n\n}\n\n\n\n", + "func": "int func0(const char *str) {\n return (get_flip_with_starting_character(str, '0') <\n get_flip_with_starting_character(str, '1'))\n ? get_flip_with_starting_character(str, '0')\n : get_flip_with_starting_character(str, '1');\n}", + "test": "int main() {\n\n assert(func0(\"0001010111\") == 2);\n\n assert(func0(\"001\") == 1);\n\n assert(func0(\"010111011\") == 2);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\ncallq 1060 \ntest %eax,%eax\njle 1308 \nsub $0x1,%eax\nmov %rbx,%rdi\nmov %rbx,%rdx\nxor %ecx,%ecx\nlea 0x1(%rbx,%rax,1),%rsi\nmov $0x61,%r9d\nmov $0x30,%eax\nnopl 0x0(%rax)\nxor %r8d,%r8d\nmov %r9d,%ebx\ncmp (%rdx),%al\nsetne %r8b\nsub %eax,%ebx\nadd $0x1,%rdx\nadd %r8d,%ecx\nmov %ebx,%eax\ncmp %rsi,%rdx\njne 12b0 \nxor %eax,%eax\nmov $0x31,%edx\nmov $0x61,%r9d\nnopl 0x0(%rax)\nxor %r8d,%r8d\nmov %r9d,%ebx\ncmp (%rdi),%dl\nsetne %r8b\nsub %edx,%ebx\nadd $0x1,%rdi\nadd %r8d,%eax\nmov %ebx,%edx\ncmp %rsi,%rdi\njne 12e0 \ncmp %ecx,%eax\npop %rbx\ncmovg %ecx,%eax\nretq\nnopl 0x0(%rax,%rax,1)\nxor %eax,%eax\npop %rbx\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest eax, eax\njle short loc_1308\nsub eax, 1\nmov rdi, rbx\nxor ecx, ecx\nmov edx, 30h ; '0'\nlea rsi, [rbx+rax+1]\nmov r9d, 61h ; 'a'\nmov rax, rbx\nnop dword ptr [rax+00h]\nloc_12B0:\nxor r8d, r8d\nmov ebx, r9d\ncmp dl, [rax]\nsetnz r8b\nsub ebx, edx\nadd rax, 1\nadd ecx, r8d\nmov edx, ebx\ncmp rax, rsi\njnz short loc_12B0\nxor eax, eax\nmov edx, 31h ; '1'\nmov r9d, 61h ; 'a'\nnop dword ptr [rax+00000000h]\nloc_12E0:\nxor r8d, r8d\nmov ebx, r9d\ncmp dl, [rdi]\nsetnz r8b\nsub ebx, edx\nadd rdi, 1\nadd eax, r8d\nmov edx, ebx\ncmp rdi, rsi\njnz short loc_12E0\ncmp eax, ecx\npop rbx\ncmovg eax, ecx\nretn\nloc_1308:\nxor eax, eax\npop rbx\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v1; // eax\n int v2; // ecx\n int v3; // edx\n __int64 v4; // rsi\n const char *v5; // rax\n int v6; // r8d\n __int64 result; // rax\n int v8; // edx\n _BOOL4 v9; // r8d\n\n v1 = strlen(a1);\n if ( v1 <= 0 )\n return 0LL;\n v2 = 0;\n v3 = 48;\n v4 = (__int64)&a1[v1 - 1 + 1];\n v5 = a1;\n do\n {\n v6 = (_BYTE)v3 != *v5++;\n v2 += v6;\n v3 = 97 - v3;\n }\n while ( v5 != (const char *)v4 );\n LODWORD(result) = 0;\n v8 = 49;\n do\n {\n v9 = (_BYTE)v8 != *a1++;\n result = (unsigned int)(v9 + result);\n v8 = 97 - v8;\n }\n while ( a1 != (const char *)v4 );\n if ( (int)result > v2 )\n return (unsigned int)v2;\n return result;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest eax, eax\njle short loc_1308\nsub eax, 1\nmov rdi, rbx\nxor ecx, ecx\nmov edx, 30h ; '0'\nlea rsi, [rbx+rax+1]\nmov r9d, 61h ; 'a'\nmov rax, rbx\nnop dword ptr [rax+00h]\nloc_12B0:\nxor r8d, r8d\nmov ebx, r9d\ncmp dl, [rax]\nsetnz r8b\nsub ebx, edx\nadd rax, 1\nadd ecx, r8d\nmov edx, ebx\ncmp rax, rsi\njnz short loc_12B0\nxor eax, eax\nmov edx, 31h ; '1'\nmov r9d, 61h ; 'a'\nnop dword ptr [rax+00000000h]\nloc_12E0:\nxor r8d, r8d\nmov ebx, r9d\ncmp dl, [rdi]\nsetnz r8b\nsub ebx, edx\nadd rdi, 1\nadd eax, r8d\nmov edx, ebx\ncmp rdi, rsi\njnz short loc_12E0\ncmp eax, ecx\npop rbx\ncmovg eax, ecx\nretn\nloc_1308:\nxor eax, eax\npop rbx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1280(const char *a1)\n{\n int v1; // eax\n int v2; // ecx\n int v3; // edx\n __int64 v4; // rsi\n const char *v5; // rax\n int v6; // r8d\n __int64 result; // rax\n int v8; // edx\n _BOOL4 v9; // r8d\n\n v1 = strlen(a1);\n if ( v1 <= 0 )\n return 0LL;\n v2 = 0;\n v3 = 48;\n v4 = (__int64)&a1[v1 - 1 + 1];\n v5 = a1;\n do\n {\n v6 = (_BYTE)v3 != *v5++;\n v2 += v6;\n v3 = 97 - v3;\n }\n while ( v5 != (const char *)v4 );\n LODWORD(result) = 0;\n v8 = 49;\n do\n {\n v9 = (_BYTE)v8 != *a1++;\n result = (unsigned int)(v9 + result);\n v8 = 97 - v8;\n }\n while ( a1 != (const char *)v4 );\n if ( (int)result > v2 )\n return (unsigned int)v2;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1280(const char *a1) {\n int v1;\n int v2;\n int v3;\n long long v4;\n const char *v5;\n int v6;\n long long result;\n int v8;\n int v9;\n v1 = strlen(a1);\n if (v1 <= 0) return 0LL;\n v2 = 0;\n v3 = 48;\n v4 = (long long)&a1[v1 - 1 + 1];\n v5 = a1;\n do {\n v6 = (uint8_t)v3 != *v5++;\n v2 += v6;\n v3 = 97 - v3;\n } while (v5 != (const char *)v4);\n LODWORD(result) = 0;\n v8 = 49;\n do {\n v9 = (uint8_t)v8 != *a1++;\n result = (unsigned int)(v9 + result);\n v8 = 97 - v8;\n } while (a1 != (const char *)v4);\n if ((int)result > v2) return (unsigned int)v2;\n return result;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v1;\n int v2;\n int v3;\n long long v4;\n const char *v5;\n int v6;\n long long result;\n int v8;\n int v9;\n v1 = strlen(a1);\n if (v1 <= 0) return 0LL;\n v2 = 0;\n v3 = 48;\n v4 = (long long)&a1[v1 - 1 + 1];\n v5 = a1;\n do {\n v6 = (uint8_t)v3 != *v5++;\n v2 += v6;\n v3 = 97 - v3;\n } while (v5 != (const char *)v4);\n LODWORD(result) = 0;\n v8 = 49;\n do {\n v9 = (uint8_t)v8 != *a1++;\n result = (unsigned int)(v9 + result);\n v8 = 97 - v8;\n } while (a1 != (const char *)v4);\n if ((int)result > v2) return (unsigned int)v2;\n return result;\n}" + }, + { + "index": 365, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int count = 0;\n while (n != 0) {\n n /= 10;\n count += 1;\n }\n return count;\n}", + "test": "int main() {\n\n assert(func0(12345) == 5);\n\n assert(func0(11223305) == 8);\n\n assert(func0(4123459) == 7);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 117f \nmov -0x14(%rbp),%eax\nmovslq %eax,%rdx\nimul $0x66666667,%rdx,%rdx\nshr $0x20,%rdx\nsar $0x2,%edx\nsar $0x1f,%eax\nsub %eax,%edx\nmov %edx,%eax\nmov %eax,-0x14(%rbp)\naddl $0x1,-0x4(%rbp)\ncmpl $0x0,-0x14(%rbp)\njne 115d \nmov -0x4(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_4], 0\njmp short loc_117F\nloc_115D:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_14], eax\nadd [rbp+var_4], 1\nloc_117F:\ncmp [rbp+var_14], 0\njnz short loc_115D\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v3; // [rsp+10h] [rbp-4h]\n\n v3 = 0;\n while ( a1 )\n {\n a1 /= 10;\n ++v3;\n }\n return v3;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_4], 0\njmp short loc_117F\nloc_115D:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_14], eax\nadd [rbp+var_4], 1\nloc_117F:\ncmp [rbp+var_14], 0\njnz short loc_115D\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n unsigned int v3; // [rsp+10h] [rbp-4h]\n\n v3 = 0;\n while ( a1 )\n {\n a1 /= 10;\n ++v3;\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n unsigned int v3;\n v3 = 0;\n while (a1) {\n a1 /= 10;\n ++v3;\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v3;\n v3 = 0;\n while (a1) {\n a1 /= 10;\n ++v3;\n }\n return v3;\n}" + }, + { + "index": 365, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int count = 0;\n while (n != 0) {\n n /= 10;\n count += 1;\n }\n return count;\n}", + "test": "int main() {\n\n assert(func0(12345) == 5);\n\n assert(func0(11223305) == 8);\n\n assert(func0(4123459) == 7);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\nje 1175 \nmov $0x0,%edx\nmovslq %edi,%rax\nimul $0x66666667,%rax,%rax\nsar $0x22,%rax\nsar $0x1f,%edi\nsub %edi,%eax\nmov %eax,%edi\nadd $0x1,%edx\ntest %eax,%eax\njne 1156 \nmov %edx,%eax\nretq\nmov %edi,%edx\njmp 1172 \n", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njz short loc_1175\nmov edx, 0\nloc_1156:\nmovsxd rax, edi\nimul rax, 66666667h\nsar rax, 22h\nsar edi, 1Fh\nsub eax, edi\nmov edi, eax\nadd edx, 1\ntest eax, eax\njnz short loc_1156\nloc_1172:\nmov eax, edx\nretn\nloc_1175:\nmov edx, edi\njmp short loc_1172", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v1; // edx\n\n if ( a1 )\n {\n v1 = 0;\n do\n {\n a1 /= 10;\n ++v1;\n }\n while ( a1 );\n }\n else\n {\n return 0;\n }\n return v1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ntest edi, edi\njz short loc_1175\nmov edx, 0\nloc_1156:\nmovsxd rax, edi\nimul rax, 66666667h\nsar rax, 22h\nsar edi, 1Fh\nsub eax, edi\nmov edi, eax\nadd edx, 1\ntest eax, eax\njnz short loc_1156\nloc_1172:\nmov eax, edx\nretn\nloc_1175:\nmov edx, edi\njmp short loc_1172", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n unsigned int v1; // edx\n\n if ( a1 )\n {\n v1 = 0;\n do\n {\n a1 /= 10;\n ++v1;\n }\n while ( a1 );\n }\n else\n {\n return 0;\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n unsigned int v1;\n if (a1) {\n v1 = 0;\n do {\n a1 /= 10;\n ++v1;\n } while (a1);\n } else {\n return 0;\n }\n return v1;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v1;\n if (a1) {\n v1 = 0;\n do {\n a1 /= 10;\n ++v1;\n } while (a1);\n } else {\n return 0;\n }\n return v1;\n}" + }, + { + "index": 366, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int list_nums[], size_t list_length) {\n int max_product = list_nums[0] * list_nums[1];\n for (size_t i = 1; i < list_length - 1; i++) {\n int product = list_nums[i] * list_nums[i + 1];\n if (product > max_product) {\n max_product = product;\n }\n }\n return max_product;\n}", + "test": "int main() {\n\n int list1[] = {1, 2, 3, 4, 5, 6};\n\n int list2[] = {1, 2, 3, 4, 5};\n\n int list3[] = {2, 3};\n\n\n\n assert(func0(list1, sizeof(list1)/sizeof(list1[0])) == 30);\n\n assert(func0(list2, sizeof(list2)/sizeof(list2[0])) == 20);\n\n assert(func0(list3, sizeof(list3)/sizeof(list3[0])) == 6);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov -0x18(%rbp),%rax\nmov (%rax),%edx\nmov -0x18(%rbp),%rax\nadd $0x4,%rax\nmov (%rax),%eax\nimul %edx,%eax\nmov %eax,-0x10(%rbp)\nmovq $0x1,-0x8(%rbp)\njmp 11e0 \nmov -0x8(%rbp),%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x8(%rbp),%rax\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\nimul %edx,%eax\nmov %eax,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x10(%rbp),%eax\njle 11db \nmov -0xc(%rbp),%eax\nmov %eax,-0x10(%rbp)\naddq $0x1,-0x8(%rbp)\nmov -0x20(%rbp),%rax\nsub $0x1,%rax\ncmp %rax,-0x8(%rbp)\njb 1199 \nmov -0x10(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov rax, [rbp+var_18]\nmov edx, [rax]\nmov rax, [rbp+var_18]\nadd rax, 4\nmov eax, [rax]\nimul eax, edx\nmov [rbp+var_10], eax\nmov [rbp+var_8], 1\njmp short loc_11E0\nloc_1199:\nmov rax, [rbp+var_8]\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_8]\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nimul eax, edx\nmov [rbp+var_C], eax\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_10]\njle short loc_11DB\nmov eax, [rbp+var_C]\nmov [rbp+var_10], eax\nloc_11DB:\nadd [rbp+var_8], 1\nloc_11E0:\nmov rax, [rbp+var_20]\nsub rax, 1\ncmp [rbp+var_8], rax\njb short loc_1199\nmov eax, [rbp+var_10]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, __int64 a2)\n{\n int v3; // [rsp+10h] [rbp-10h]\n unsigned __int64 i; // [rsp+18h] [rbp-8h]\n\n v3 = *a1 * a1[1];\n for ( i = 1LL; i < a2 - 1; ++i )\n {\n if ( a1[i] * a1[i + 1] > v3 )\n v3 = a1[i] * a1[i + 1];\n }\n return (unsigned int)v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov rax, [rbp+var_18]\nmov edx, [rax]\nmov rax, [rbp+var_18]\nadd rax, 4\nmov eax, [rax]\nimul eax, edx\nmov [rbp+var_10], eax\nmov [rbp+var_8], 1\njmp short loc_11E0\nloc_1199:\nmov rax, [rbp+var_8]\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_8]\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nimul eax, edx\nmov [rbp+var_C], eax\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_10]\njle short loc_11DB\nmov eax, [rbp+var_C]\nmov [rbp+var_10], eax\nloc_11DB:\nadd [rbp+var_8], 1\nloc_11E0:\nmov rax, [rbp+var_20]\nsub rax, 1\ncmp [rbp+var_8], rax\njb short loc_1199\nmov eax, [rbp+var_10]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, __int64 a2)\n{\n int v3; // [rsp+10h] [rbp-10h]\n unsigned __int64 i; // [rsp+18h] [rbp-8h]\n\n v3 = *a1 * a1[1];\n for ( i = 1LL; i < a2 - 1; ++i )\n {\n if ( a1[i] * a1[i + 1] > v3 )\n v3 = a1[i] * a1[i + 1];\n }\n return (unsigned int)v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, long long a2) {\n int v3;\n unsigned long long i;\n v3 = *a1 * a1[1];\n for (i = 1LL; i < a2 - 1; ++i) {\n if (a1[i] * a1[i + 1] > v3) v3 = a1[i] * a1[i + 1];\n }\n return (unsigned int)v3;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, long long a2) {\n int v3;\n unsigned long long i;\n v3 = *a1 * a1[1];\n for (i = 1LL; i < a2 - 1; ++i) {\n if (a1[i] * a1[i + 1] > v3) v3 = a1[i] * a1[i + 1];\n }\n return (unsigned int)v3;\n}" + }, + { + "index": 366, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int list_nums[], size_t list_length) {\n int max_product = list_nums[0] * list_nums[1];\n for (size_t i = 1; i < list_length - 1; i++) {\n int product = list_nums[i] * list_nums[i + 1];\n if (product > max_product) {\n max_product = product;\n }\n }\n return max_product;\n}", + "test": "int main() {\n\n int list1[] = {1, 2, 3, 4, 5, 6};\n\n int list2[] = {1, 2, 3, 4, 5};\n\n int list3[] = {2, 3};\n\n\n\n assert(func0(list1, sizeof(list1)/sizeof(list1[0])) == 30);\n\n assert(func0(list2, sizeof(list2)/sizeof(list2[0])) == 20);\n\n assert(func0(list3, sizeof(list3)/sizeof(list3[0])) == 6);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov (%rdi),%eax\nimul 0x4(%rdi),%eax\nlea -0x1(%rsi),%rdx\ncmp $0x1,%rdx\njbe 119a \nlea 0x4(%rdi),%rdx\nlea -0x4(%rdi,%rsi,4),%rsi\nmov (%rdx),%ecx\nimul 0x4(%rdx),%ecx\ncmp %ecx,%eax\ncmovl %ecx,%eax\nadd $0x4,%rdx\ncmp %rsi,%rdx\njne 1186 \nretq\n", + "ida_asm": "func0:\nendbr64\nmov eax, [rdi]\nimul eax, [rdi+4]\nlea rdx, [rsi-1]\ncmp rdx, 1\njbe short locret_119A\nlea rdx, [rdi+4]\nlea rsi, [rdi+rsi*4-4]\nloc_1186:\nmov ecx, [rdx]\nimul ecx, [rdx+4]\ncmp eax, ecx\ncmovl eax, ecx\nadd rdx, 4\ncmp rdx, rsi\njnz short loc_1186\nlocret_119A:\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, __int64 a2)\n{\n __int64 result; // rax\n _DWORD *v3; // rdx\n __int64 v4; // rsi\n int v5; // ecx\n\n result = (unsigned int)(a1[1] * *a1);\n if ( (unsigned __int64)(a2 - 1) > 1 )\n {\n v3 = a1 + 1;\n v4 = (__int64)&a1[a2 - 1];\n do\n {\n v5 = v3[1] * *v3;\n if ( (int)result < v5 )\n result = (unsigned int)v5;\n ++v3;\n }\n while ( v3 != (_DWORD *)v4 );\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov eax, [rdi]\nimul eax, [rdi+4]\nlea rdx, [rsi-1]\ncmp rdx, 1\njbe short locret_119A\nlea rdx, [rdi+4]\nlea rsi, [rdi+rsi*4-4]\nloc_1186:\nmov ecx, [rdx]\nimul ecx, [rdx+4]\ncmp eax, ecx\ncmovl eax, ecx\nadd rdx, 4\ncmp rdx, rsi\njnz short loc_1186\nlocret_119A:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, __int64 a2)\n{\n __int64 result; // rax\n _DWORD *v3; // rdx\n __int64 v4; // rsi\n int v5; // ecx\n\n result = (unsigned int)(a1[1] * *a1);\n if ( (unsigned __int64)(a2 - 1) > 1 )\n {\n v3 = a1 + 1;\n v4 = (__int64)&a1[a2 - 1];\n do\n {\n v5 = v3[1] * *v3;\n if ( (int)result < v5 )\n result = (unsigned int)v5;\n ++v3;\n }\n while ( v3 != (_DWORD *)v4 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, long long a2) {\n long long result;\n uint32_t *v3;\n long long v4;\n int v5;\n result = (unsigned int)(a1[1] * *a1);\n if ((unsigned long long)(a2 - 1) > 1) {\n v3 = a1 + 1;\n v4 = (long long)&a1[a2 - 1];\n do {\n v5 = v3[1] * *v3;\n if ((int)result < v5) result = (unsigned int)v5;\n ++v3;\n } while (v3 != (uint32_t *)v4);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, long long a2) {\n long long result;\n uint32_t *v3;\n long long v4;\n int v5;\n result = (unsigned int)(a1[1] * *a1);\n if ((unsigned long long)(a2 - 1) > 1) {\n v3 = a1 + 1;\n v4 = (long long)&a1[a2 - 1];\n do {\n v5 = v3[1] * *v3;\n if ((int)result < v5) result = (unsigned int)v5;\n ++v3;\n } while (v3 != (uint32_t *)v4);\n }\n return result;\n}" + }, + { + "index": 366, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int list_nums[], size_t list_length) {\n int max_product = list_nums[0] * list_nums[1];\n for (size_t i = 1; i < list_length - 1; i++) {\n int product = list_nums[i] * list_nums[i + 1];\n if (product > max_product) {\n max_product = product;\n }\n }\n return max_product;\n}", + "test": "int main() {\n\n int list1[] = {1, 2, 3, 4, 5, 6};\n\n int list2[] = {1, 2, 3, 4, 5};\n\n int list3[] = {2, 3};\n\n\n\n assert(func0(list1, sizeof(list1)/sizeof(list1[0])) == 30);\n\n assert(func0(list2, sizeof(list2)/sizeof(list2[0])) == 20);\n\n assert(func0(list3, sizeof(list3)/sizeof(list3[0])) == 6);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nlea -0x1(%rsi),%rdx\nmov (%rdi),%eax\nimul 0x4(%rdi),%eax\ncmp $0x1,%rdx\njbe 1178 \nmov 0x4(%rdi),%r8d\nlea 0x8(%rdi),%rcx\nlea (%rdi,%rsi,4),%rsi\nmov %r8d,%edx\nmov (%rcx),%r8d\nimul %r8d,%edx\ncmp %edx,%eax\ncmovl %edx,%eax\nadd $0x4,%rcx\ncmp %rcx,%rsi\njne 1160 \nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\nmov r8d, [rdi+4]\nmov ecx, [rdi]\nlea rax, [rsi-1]\nimul ecx, r8d\ncmp rax, 1\njbe short loc_12A8\nlea rdx, [rdi+8]\nlea rsi, [rdi+rsi*4]\nloc_1290:\nmov eax, r8d\nmov r8d, [rdx]\nimul eax, r8d\ncmp ecx, eax\ncmovl ecx, eax\nadd rdx, 4\ncmp rdx, rsi\njnz short loc_1290\nloc_12A8:\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, __int64 a2)\n{\n int v2; // r8d\n int v3; // ecx\n int *v4; // rdx\n int *v5; // rsi\n int v6; // eax\n int v7; // eax\n\n v2 = a1[1];\n v3 = v2 * *a1;\n if ( (unsigned __int64)(a2 - 1) > 1 )\n {\n v4 = a1 + 2;\n v5 = &a1[a2];\n do\n {\n v6 = v2;\n v2 = *v4;\n v7 = *v4 * v6;\n if ( v3 < v7 )\n v3 = v7;\n ++v4;\n }\n while ( v4 != v5 );\n }\n return (unsigned int)v3;\n}", + "ida_strip_asm": "sub_1270:\nendbr64\nmov r8d, [rdi+4]\nmov ecx, [rdi]\nlea rax, [rsi-1]\nimul ecx, r8d\ncmp rax, 1\njbe short loc_12A8\nlea rdx, [rdi+8]\nlea rsi, [rdi+rsi*4]\nloc_1290:\nmov eax, r8d\nmov r8d, [rdx]\nimul eax, r8d\ncmp ecx, eax\ncmovl ecx, eax\nadd rdx, 4\ncmp rdx, rsi\njnz short loc_1290\nloc_12A8:\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1270(_DWORD *a1, __int64 a2)\n{\n int v2; // r8d\n int v3; // ecx\n int *v4; // rdx\n int *v5; // rsi\n int v6; // eax\n int v7; // eax\n\n v2 = a1[1];\n v3 = v2 * *a1;\n if ( (unsigned __int64)(a2 - 1) > 1 )\n {\n v4 = a1 + 2;\n v5 = &a1[a2];\n do\n {\n v6 = v2;\n v2 = *v4;\n v7 = *v4 * v6;\n if ( v3 < v7 )\n v3 = v7;\n ++v4;\n }\n while ( v4 != v5 );\n }\n return (unsigned int)v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1270(uint32_t *a1, long long a2) {\n int v2;\n int v3;\n int *v4;\n int *v5;\n int v6;\n int v7;\n v2 = a1[1];\n v3 = v2 * *a1;\n if ((unsigned long long)(a2 - 1) > 1) {\n v4 = a1 + 2;\n v5 = &a1[a2];\n do {\n v6 = v2;\n v2 = *v4;\n v7 = *v4 * v6;\n if (v3 < v7) v3 = v7;\n ++v4;\n } while (v4 != v5);\n }\n return (unsigned int)v3;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, long long a2) {\n int v2;\n int v3;\n int *v4;\n int *v5;\n int v6;\n int v7;\n v2 = a1[1];\n v3 = v2 * *a1;\n if ((unsigned long long)(a2 - 1) > 1) {\n v4 = a1 + 2;\n v5 = &a1[a2];\n do {\n v6 = v2;\n v2 = *v4;\n v7 = *v4 * v6;\n if (v3 < v7) v3 = v7;\n ++v4;\n } while (v4 != v5);\n }\n return (unsigned int)v3;\n}" + }, + { + "index": 367, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct Node {\n\n int data;\n\n struct Node *left;\n\n struct Node *right;\n\n} Node;\n\n\n\nNode* newNode(int data) {\n\n Node* node = (Node*)malloc(sizeof(Node));\n\n node->data = data;\n\n node->left = NULL;\n\n node->right = NULL;\n\n return node;\n\n}\n\n\n\nint get_height(Node* root) {\n\n if (root == NULL) {\n\n return 0;\n\n }\n\n int leftHeight = get_height(root->left);\n\n int rightHeight = get_height(root->right);\n\n return (leftHeight > rightHeight ? leftHeight : rightHeight) + 1;\n\n}\n\n\n\n", + "func": "bool func0(Node* root) {\n if (root == NULL) {\n return true;\n }\n int lh = get_height(root->left);\n int rh = get_height(root->right);\n if (abs(lh - rh) <= 1 && func0(root->left) && func0(root->right)) {\n return true;\n }\n return false;\n}", + "test": "int main() {\n\n Node* root = newNode(1);\n\n root->left = newNode(2);\n\n root->right = newNode(3);\n\n root->left->left = newNode(4);\n\n root->left->right = newNode(5);\n\n root->left->left->left = newNode(8);\n\n \n\n Node* root1 = newNode(1);\n\n root1->left = newNode(2);\n\n root1->right = newNode(3);\n\n root1->left->left = newNode(4);\n\n root1->left->right = newNode(5);\n\n root1->right->left = newNode(6);\n\n root1->left->left->left = newNode(7);\n\n \n\n Node* root2 = newNode(1);\n\n root2->left = newNode(2);\n\n root2->right = newNode(3);\n\n root2->left->left = newNode(4);\n\n root2->left->right = newNode(5);\n\n root2->left->left->left = newNode(7);\n\n \n\n assert(func0(root) == false);\n\n assert(func0(root1) == true);\n\n assert(func0(root2) == false);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\ncmpq $0x0,-0x18(%rbp)\njne 121e \nmov $0x1,%eax\njmp 128e \nmov -0x18(%rbp),%rax\nmov 0x8(%rax),%rax\nmov %rax,%rdi\ncallq 11ad \nmov %eax,-0x8(%rbp)\nmov -0x18(%rbp),%rax\nmov 0x10(%rax),%rax\nmov %rax,%rdi\ncallq 11ad \nmov %eax,-0x4(%rbp)\nmov -0x8(%rbp),%eax\nsub -0x4(%rbp),%eax\ncmp $0xffffffff,%eax\njl 1289 \nmov -0x8(%rbp),%eax\nsub -0x4(%rbp),%eax\ncmp $0x1,%eax\njg 1289 \nmov -0x18(%rbp),%rax\nmov 0x8(%rax),%rax\nmov %rax,%rdi\ncallq 1200 \ntest %al,%al\nje 1289 \nmov -0x18(%rbp),%rax\nmov 0x10(%rax),%rax\nmov %rax,%rdi\ncallq 1200 \ntest %al,%al\nje 1289 \nmov $0x1,%eax\njmp 128e \nmov $0x0,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\ncmp [rbp+var_18], 0\njnz short loc_121F\nmov eax, 1\njmp short locret_128F\nloc_121F:\nmov rax, [rbp+var_18]\nmov rax, [rax+8]\nmov rdi, rax\ncall get_height\nmov [rbp+var_8], eax\nmov rax, [rbp+var_18]\nmov rax, [rax+10h]\nmov rdi, rax\ncall get_height\nmov [rbp+var_4], eax\nmov eax, [rbp+var_8]\nsub eax, [rbp+var_4]\ncmp eax, 0FFFFFFFFh\njl short loc_128A\nmov eax, [rbp+var_8]\nsub eax, [rbp+var_4]\ncmp eax, 1\njg short loc_128A\nmov rax, [rbp+var_18]\nmov rax, [rax+8]\nmov rdi, rax\ncall func0\ntest al, al\njz short loc_128A\nmov rax, [rbp+var_18]\nmov rax, [rax+10h]\nmov rdi, rax\ncall func0\ntest al, al\njz short loc_128A\nmov eax, 1\njmp short locret_128F\nloc_128A:\nmov eax, 0\nlocret_128F:\nleave\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(__int64 a1)\n{\n int height; // [rsp+18h] [rbp-8h]\n int v3; // [rsp+1Ch] [rbp-4h]\n\n if ( !a1 )\n return 1LL;\n height = get_height(*(_QWORD *)(a1 + 8));\n v3 = get_height(*(_QWORD *)(a1 + 16));\n return height - v3 >= -1\n && height - v3 <= 1\n && (unsigned __int8)func0(*(_QWORD *)(a1 + 8))\n && (unsigned __int8)func0(*(_QWORD *)(a1 + 16));\n}", + "ida_strip_asm": "sub_1201:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\ncmp [rbp+var_18], 0\njnz short loc_121F\nmov eax, 1\njmp short locret_128F\nloc_121F:\nmov rax, [rbp+var_18]\nmov rax, [rax+8]\nmov rdi, rax\ncall sub_11AD\nmov [rbp+var_8], eax\nmov rax, [rbp+var_18]\nmov rax, [rax+10h]\nmov rdi, rax\ncall sub_11AD\nmov [rbp+var_4], eax\nmov eax, [rbp+var_8]\nsub eax, [rbp+var_4]\ncmp eax, 0FFFFFFFFh\njl short loc_128A\nmov eax, [rbp+var_8]\nsub eax, [rbp+var_4]\ncmp eax, 1\njg short loc_128A\nmov rax, [rbp+var_18]\nmov rax, [rax+8]\nmov rdi, rax\ncall sub_1201\ntest al, al\njz short loc_128A\nmov rax, [rbp+var_18]\nmov rax, [rax+10h]\nmov rdi, rax\ncall sub_1201\ntest al, al\njz short loc_128A\nmov eax, 1\njmp short locret_128F\nloc_128A:\nmov eax, 0\nlocret_128F:\nleave\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1201(__int64 a1)\n{\n int v2; // [rsp+18h] [rbp-8h]\n int v3; // [rsp+1Ch] [rbp-4h]\n\n if ( !a1 )\n return 1LL;\n v2 = sub_11AD(*(_QWORD *)(a1 + 8));\n v3 = sub_11AD(*(_QWORD *)(a1 + 16));\n return v2 - v3 >= -1\n && v2 - v3 <= 1\n && (unsigned __int8)sub_1201(*(_QWORD *)(a1 + 8))\n && (unsigned __int8)sub_1201(*(_QWORD *)(a1 + 16));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1201(long long a1) {\n int v2;\n int v3;\n if (!a1) return 1LL;\n v2 = sub_11AD(*(uint64_t *)(a1 + 8));\n v3 = sub_11AD(*(uint64_t *)(a1 + 16));\n return v2 - v3 >= -1 && v2 - v3 <= 1 &&\n (unsigned char)sub_1201(*(uint64_t *)(a1 + 8)) &&\n (unsigned char)sub_1201(*(uint64_t *)(a1 + 16));\n}", + "ida_pseudo_norm": "uint8_t func0(long long a1) {\n int height;\n int v3;\n if (!a1) return 1LL;\n height = get_height(*(uint64_t *)(a1 + 8));\n v3 = get_height(*(uint64_t *)(a1 + 16));\n return height - v3 >= -1 && height - v3 <= 1 &&\n (unsigned char)func0(*(uint64_t *)(a1 + 8)) &&\n (unsigned char)func0(*(uint64_t *)(a1 + 16));\n}" + }, + { + "index": 367, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct Node {\n\n int data;\n\n struct Node *left;\n\n struct Node *right;\n\n} Node;\n\n\n\nNode* newNode(int data) {\n\n Node* node = (Node*)malloc(sizeof(Node));\n\n node->data = data;\n\n node->left = NULL;\n\n node->right = NULL;\n\n return node;\n\n}\n\n\n\nint get_height(Node* root) {\n\n if (root == NULL) {\n\n return 0;\n\n }\n\n int leftHeight = get_height(root->left);\n\n int rightHeight = get_height(root->right);\n\n return (leftHeight > rightHeight ? leftHeight : rightHeight) + 1;\n\n}\n\n\n\n", + "func": "bool func0(Node* root) {\n if (root == NULL) {\n return true;\n }\n int lh = get_height(root->left);\n int rh = get_height(root->right);\n if (abs(lh - rh) <= 1 && func0(root->left) && func0(root->right)) {\n return true;\n }\n return false;\n}", + "test": "int main() {\n\n Node* root = newNode(1);\n\n root->left = newNode(2);\n\n root->right = newNode(3);\n\n root->left->left = newNode(4);\n\n root->left->right = newNode(5);\n\n root->left->left->left = newNode(8);\n\n \n\n Node* root1 = newNode(1);\n\n root1->left = newNode(2);\n\n root1->right = newNode(3);\n\n root1->left->left = newNode(4);\n\n root1->left->right = newNode(5);\n\n root1->right->left = newNode(6);\n\n root1->left->left->left = newNode(7);\n\n \n\n Node* root2 = newNode(1);\n\n root2->left = newNode(2);\n\n root2->right = newNode(3);\n\n root2->left->left = newNode(4);\n\n root2->left->right = newNode(5);\n\n root2->left->left->left = newNode(7);\n\n \n\n assert(func0(root) == false);\n\n assert(func0(root1) == true);\n\n assert(func0(root2) == false);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x1,%eax\ntest %rdi,%rdi\nje 1222 \npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbp\nmov 0x8(%rdi),%r12\nmov %r12,%rdi\ncallq 118e \nmov %eax,%ebx\nmov 0x10(%rbp),%rbp\nmov %rbp,%rdi\ncallq 118e \nsub %eax,%ebx\nadd $0x1,%ebx\nmov $0x0,%eax\ncmp $0x2,%ebx\njbe 120c \npop %rbx\npop %rbp\npop %r12\nretq\nmov %r12,%rdi\ncallq 11c9 \ntest %al,%al\nje 1207 \nmov %rbp,%rdi\ncallq 11c9 \njmp 1207 \nretq\n", + "ida_asm": "func0:\nendbr64\nmov eax, 1\ntest rdi, rdi\njz short locret_1222\npush r12\npush rbp\npush rbx\nmov rbp, rdi\nmov r12, [rdi+8]\nmov rdi, r12\ncall get_height\nmov ebx, eax\nmov rbp, [rbp+10h]\nmov rdi, rbp\ncall get_height\nsub ebx, eax\nadd ebx, 1\nmov eax, 0\ncmp ebx, 2\njbe short loc_120C\nloc_1207:\npop rbx\npop rbp\npop r12\nretn\nloc_120C:\nmov rdi, r12\ncall func0\ntest al, al\njz short loc_1207\nmov rdi, rbp\ncall func0\njmp short loc_1207\nlocret_1222:\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1)\n{\n __int64 result; // rax\n __int64 v2; // r12\n int height; // ebx\n __int64 v4; // rbp\n unsigned int v5; // ebx\n\n result = 1LL;\n if ( a1 )\n {\n v2 = *(_QWORD *)(a1 + 8);\n height = get_height(v2);\n v4 = *(_QWORD *)(a1 + 16);\n v5 = height - get_height(v4) + 1;\n result = 0LL;\n if ( v5 <= 2 )\n {\n result = func0(v2);\n if ( (_BYTE)result )\n return func0(v4);\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\nmov eax, 1\ntest rdi, rdi\njz short locret_1222\npush r12\npush rbp\npush rbx\nmov rbp, rdi\nmov r12, [rdi+8]\nmov rdi, r12\ncall sub_118E\nmov ebx, eax\nmov rbp, [rbp+10h]\nmov rdi, rbp\ncall sub_118E\nsub ebx, eax\nadd ebx, 1\nmov eax, 0\ncmp ebx, 2\njbe short loc_120C\nloc_1207:\npop rbx\npop rbp\npop r12\nretn\nloc_120C:\nmov rdi, r12\ncall sub_11C9\ntest al, al\njz short loc_1207\nmov rdi, rbp\ncall sub_11C9\njmp short loc_1207\nlocret_1222:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11C9(__int64 a1)\n{\n __int64 result; // rax\n __int64 v2; // r12\n int v3; // ebx\n __int64 v4; // rbp\n unsigned int v5; // ebx\n\n result = 1LL;\n if ( a1 )\n {\n v2 = *(_QWORD *)(a1 + 8);\n v3 = sub_118E(v2);\n v4 = *(_QWORD *)(a1 + 16);\n v5 = v3 - sub_118E(v4) + 1;\n result = 0LL;\n if ( v5 <= 2 )\n {\n result = sub_11C9(v2);\n if ( (_BYTE)result )\n return sub_11C9(v4);\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11C9(long long a1) {\n long long result;\n long long v2;\n int v3;\n long long v4;\n unsigned int v5;\n result = 1LL;\n if (a1) {\n v2 = *(uint64_t *)(a1 + 8);\n v3 = sub_118E(v2);\n v4 = *(uint64_t *)(a1 + 16);\n v5 = v3 - sub_118E(v4) + 1;\n result = 0LL;\n if (v5 <= 2) {\n result = sub_11C9(v2);\n if ((uint8_t)result) return sub_11C9(v4);\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1) {\n long long result;\n long long v2;\n int height;\n long long v4;\n unsigned int v5;\n result = 1LL;\n if (a1) {\n v2 = *(uint64_t *)(a1 + 8);\n height = get_height(v2);\n v4 = *(uint64_t *)(a1 + 16);\n v5 = height - get_height(v4) + 1;\n result = 0LL;\n if (v5 <= 2) {\n result = func0(v2);\n if ((uint8_t)result) return func0(v4);\n }\n }\n return result;\n}" + }, + { + "index": 367, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct Node {\n\n int data;\n\n struct Node *left;\n\n struct Node *right;\n\n} Node;\n\n\n\nNode* newNode(int data) {\n\n Node* node = (Node*)malloc(sizeof(Node));\n\n node->data = data;\n\n node->left = NULL;\n\n node->right = NULL;\n\n return node;\n\n}\n\n\n\nint get_height(Node* root) {\n\n if (root == NULL) {\n\n return 0;\n\n }\n\n int leftHeight = get_height(root->left);\n\n int rightHeight = get_height(root->right);\n\n return (leftHeight > rightHeight ? leftHeight : rightHeight) + 1;\n\n}\n\n\n\n", + "func": "bool func0(Node* root) {\n if (root == NULL) {\n return true;\n }\n int lh = get_height(root->left);\n int rh = get_height(root->right);\n if (abs(lh - rh) <= 1 && func0(root->left) && func0(root->right)) {\n return true;\n }\n return false;\n}", + "test": "int main() {\n\n Node* root = newNode(1);\n\n root->left = newNode(2);\n\n root->right = newNode(3);\n\n root->left->left = newNode(4);\n\n root->left->right = newNode(5);\n\n root->left->left->left = newNode(8);\n\n \n\n Node* root1 = newNode(1);\n\n root1->left = newNode(2);\n\n root1->right = newNode(3);\n\n root1->left->left = newNode(4);\n\n root1->left->right = newNode(5);\n\n root1->right->left = newNode(6);\n\n root1->left->left->left = newNode(7);\n\n \n\n Node* root2 = newNode(1);\n\n root2->left = newNode(2);\n\n root2->right = newNode(3);\n\n root2->left->left = newNode(4);\n\n root2->left->right = newNode(5);\n\n root2->left->left->left = newNode(7);\n\n \n\n assert(func0(root) == false);\n\n assert(func0(root1) == true);\n\n assert(func0(root2) == false);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\ntest %rbx,%rbx\nje 1540 \nmov 0x8(%rbx),%r12\ntest %r12,%r12\nje 1518 \nmov %r12,%rdi\ncallq 14a0 \nmov 0x10(%rbx),%rbx\nmov %eax,%ebp\ntest %rbx,%rbx\nje 1506 \nmov %rbx,%rdi\ncallq 14a0 \nsub %eax,%ebp\nadd $0x1,%ebp\ncmp $0x2,%ebp\njbe 1528 \npop %rbx\nxor %eax,%eax\npop %rbp\npop %r12\nretq\nnopl (%rax)\nmov 0x10(%rbx),%rbx\ntest %rbx,%rbx\nje 1540 \nxor %ebp,%ebp\njmp 14fc \nnopl (%rax)\nmov %r12,%rdi\ncallq 14d0 \ntest %al,%al\njne 14db \npop %rbx\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax)\npop %rbx\nmov $0x1,%eax\npop %rbp\npop %r12\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\nloc_19F8:\ntest rbx, rbx\njz loc_1C68\nmov rsi, [rbx+8]\ntest rsi, rsi\njz loc_1C28\nmov r9, [rsi+8]\nxor r8d, r8d\ntest r9, r9\njz short loc_1A90\nmov r8, [r9+8]\nxor ecx, ecx\ntest r8, r8\njz short loc_1A4D\nmov rdi, [r8+8]\ntest rdi, rdi\njz short loc_1A35\ncall get_height_part_0\nmov ecx, eax\nloc_1A35:\nmov rdi, [r8+10h]\nxor eax, eax\ntest rdi, rdi\njz short loc_1A45\ncall get_height_part_0\nloc_1A45:\ncmp eax, ecx\ncmovl eax, ecx\nlea ecx, [rax+1]\nloc_1A4D:\nmov r9, [r9+10h]\nxor r8d, r8d\ntest r9, r9\njz short loc_1A85\nmov rdi, [r9+8]\ntest rdi, rdi\njz short loc_1A6A\ncall get_height_part_0\nmov r8d, eax\nloc_1A6A:\nmov rdi, [r9+10h]\nxor eax, eax\ntest rdi, rdi\njz short loc_1A7A\ncall get_height_part_0\nloc_1A7A:\ncmp eax, r8d\ncmovge r8d, eax\nadd r8d, 1\nloc_1A85:\ncmp r8d, ecx\ncmovl r8d, ecx\nadd r8d, 1\nloc_1A90:\nmov r10, [rsi+10h]\nxor ecx, ecx\ntest r10, r10\njz short loc_1B0D\nmov r11, [r10+8]\nxor r9d, r9d\ntest r11, r11\njz short loc_1AD0\nmov rdi, [r11+8]\ntest rdi, rdi\njz short loc_1AB7\ncall get_height_part_0\nmov ecx, eax\nloc_1AB7:\nmov rdi, [r11+10h]\nxor eax, eax\ntest rdi, rdi\njz short loc_1AC7\ncall get_height_part_0\nloc_1AC7:\ncmp eax, ecx\ncmovl eax, ecx\nlea r9d, [rax+1]\nloc_1AD0:\nmov r10, [r10+10h]\nxor ecx, ecx\ntest r10, r10\njz short loc_1B03\nmov rdi, [r10+8]\ntest rdi, rdi\njz short loc_1AEB\ncall get_height_part_0\nmov ecx, eax\nloc_1AEB:\nmov rdi, [r10+10h]\nxor eax, eax\ntest rdi, rdi\njz short loc_1AFB\ncall get_height_part_0\nloc_1AFB:\ncmp eax, ecx\ncmovge ecx, eax\nadd ecx, 1\nloc_1B03:\ncmp ecx, r9d\ncmovl ecx, r9d\nadd ecx, 1\nloc_1B0D:\ncmp ecx, r8d\nmov rbx, [rbx+10h]\ncmovl ecx, r8d\nadd ecx, 1\ntest rbx, rbx\njz loc_1C15\nmov r10, [rbx+8]\nxor r8d, r8d\ntest r10, r10\njz short loc_1B83\nloc_1B30:\nmov r11, [r10+8]\nxor r9d, r9d\ntest r11, r11\njz short loc_1B68\nmov rdi, [r11+8]\ntest rdi, rdi\njz short loc_1B4D\ncall get_height_part_0\nmov r8d, eax\nloc_1B4D:\nmov rdi, [r11+10h]\nxor eax, eax\ntest rdi, rdi\njz short loc_1B5D\ncall get_height_part_0\nloc_1B5D:\ncmp eax, r8d\ncmovl eax, r8d\nlea r9d, [rax+1]\nloc_1B68:\nmov rdi, [r10+10h]\nxor eax, eax\ntest rdi, rdi\njz short loc_1B78\ncall get_height_part_0\nloc_1B78:\ncmp eax, r9d\ncmovl eax, r9d\nlea r8d, [rax+1]\nloc_1B83:\nmov r10, [rbx+10h]\nxor eax, eax\ntest r10, r10\njz short loc_1C09\nmov r11, [r10+8]\nxor r9d, r9d\ntest r11, r11\njz short loc_1BC6\nmov rdi, [r11+8]\ntest rdi, rdi\njz short loc_1BAB\ncall get_height_part_0\nmov r9d, eax\nloc_1BAB:\nmov rdi, [r11+10h]\nxor eax, eax\ntest rdi, rdi\njz short loc_1BBB\ncall get_height_part_0\nloc_1BBB:\ncmp eax, r9d\ncmovl eax, r9d\nlea r9d, [rax+1]\nloc_1BC6:\nmov r11, [r10+10h]\nxor eax, eax\ntest r11, r11\njz short loc_1BFF\nmov rdi, [r11+8]\nxor r10d, r10d\ntest rdi, rdi\njz short loc_1BE5\ncall get_height_part_0\nmov r10d, eax\nloc_1BE5:\nmov rdi, [r11+10h]\nxor eax, eax\ntest rdi, rdi\njz short loc_1BF5\ncall get_height_part_0\nloc_1BF5:\ncmp eax, r10d\ncmovl eax, r10d\nadd eax, 1\nloc_1BFF:\ncmp eax, r9d\ncmovl eax, r9d\nadd eax, 1\nloc_1C09:\ncmp eax, r8d\ncmovl eax, r8d\nadd eax, 1\nsub ecx, eax\nloc_1C15:\nadd ecx, 1\ncmp ecx, 2\njbe short loc_1C50\nxor eax, eax\npop rbx\nretn\nloc_1C28:\nmov rbx, [rbx+10h]\ntest rbx, rbx\njz short loc_1C68\nmov r10, [rbx+8]\nxor ecx, ecx\nxor r8d, r8d\ntest r10, r10\njnz loc_1B30\njmp loc_1B83\nloc_1C50:\nmov rdi, rsi\ncall func0\ntest al, al\njnz loc_19F8\npop rbx\nretn\nloc_1C68:\nmov eax, 1\npop rbx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, __int64 a3)\n{\n __int64 v4; // rsi\n __int64 v5; // r9\n int v6; // r8d\n __int64 v7; // r8\n __int64 v8; // rcx\n __int64 v9; // rdi\n __int64 v10; // rdi\n int v11; // eax\n __int64 v12; // r9\n int v13; // r8d\n __int64 v14; // rdi\n __int64 v15; // rdi\n int v16; // eax\n __int64 v17; // r10\n __int64 v18; // rcx\n __int64 v19; // r11\n int v20; // r9d\n __int64 v21; // rdi\n __int64 v22; // rdi\n int v23; // eax\n __int64 v24; // r10\n __int64 v25; // rdi\n __int64 v26; // rdi\n int v27; // eax\n __int64 v28; // rcx\n __int64 v29; // r10\n int height_part_0; // r8d\n __int64 v31; // r11\n int v32; // r9d\n __int64 v33; // rdi\n __int64 v34; // rdi\n int v35; // eax\n __int64 v36; // rdi\n int v37; // eax\n __int64 v38; // r10\n int v39; // eax\n __int64 v40; // r11\n int v41; // r9d\n __int64 v42; // rdi\n __int64 v43; // rdi\n int v44; // eax\n __int64 v45; // r11\n int v46; // eax\n __int64 v47; // rdi\n int v48; // r10d\n __int64 v49; // rdi\n int v50; // eax\n __int64 result; // rax\n\n while ( a1 )\n {\n v4 = *(_QWORD *)(a1 + 8);\n if ( !v4 )\n {\n a1 = *(_QWORD *)(a1 + 16);\n if ( !a1 )\n return 1LL;\n v29 = *(_QWORD *)(a1 + 8);\n v28 = 0LL;\n height_part_0 = 0;\n if ( v29 )\n {\nLABEL_47:\n v31 = *(_QWORD *)(v29 + 8);\n v32 = 0;\n if ( v31 )\n {\n v33 = *(_QWORD *)(v31 + 8);\n if ( v33 )\n height_part_0 = get_height_part_0(v33, v4, a3, v28);\n v34 = *(_QWORD *)(v31 + 16);\n v35 = 0;\n if ( v34 )\n v35 = get_height_part_0(v34, v4, a3, v28);\n if ( v35 < height_part_0 )\n v35 = height_part_0;\n v32 = v35 + 1;\n }\n v36 = *(_QWORD *)(v29 + 16);\n v37 = 0;\n if ( v36 )\n v37 = get_height_part_0(v36, v4, a3, v28);\n if ( v37 < v32 )\n v37 = v32;\n height_part_0 = v37 + 1;\n }\nLABEL_60:\n v38 = *(_QWORD *)(a1 + 16);\n v39 = 0;\n if ( v38 )\n {\n v40 = *(_QWORD *)(v38 + 8);\n v41 = 0;\n if ( v40 )\n {\n v42 = *(_QWORD *)(v40 + 8);\n if ( v42 )\n v41 = get_height_part_0(v42, v4, a3, v28);\n v43 = *(_QWORD *)(v40 + 16);\n v44 = 0;\n if ( v43 )\n v44 = get_height_part_0(v43, v4, a3, v28);\n if ( v44 < v41 )\n v44 = v41;\n v41 = v44 + 1;\n }\n v45 = *(_QWORD *)(v38 + 16);\n v46 = 0;\n if ( v45 )\n {\n v47 = *(_QWORD *)(v45 + 8);\n v48 = 0;\n if ( v47 )\n v48 = get_height_part_0(v47, v4, a3, v28);\n v49 = *(_QWORD *)(v45 + 16);\n v50 = 0;\n if ( v49 )\n v50 = get_height_part_0(v49, v4, a3, v28);\n if ( v50 < v48 )\n v50 = v48;\n v46 = v50 + 1;\n }\n if ( v46 < v41 )\n v46 = v41;\n v39 = v46 + 1;\n }\n if ( v39 < height_part_0 )\n v39 = height_part_0;\n LODWORD(v28) = v28 - (v39 + 1);\n goto LABEL_83;\n }\n v5 = *(_QWORD *)(v4 + 8);\n v6 = 0;\n if ( v5 )\n {\n v7 = *(_QWORD *)(v5 + 8);\n v8 = 0LL;\n if ( v7 )\n {\n v9 = *(_QWORD *)(v7 + 8);\n if ( v9 )\n v8 = (unsigned int)get_height_part_0(v9, v4, a3, 0LL);\n v10 = *(_QWORD *)(v7 + 16);\n v11 = 0;\n if ( v10 )\n v11 = get_height_part_0(v10, v4, a3, v8);\n if ( v11 < (int)v8 )\n v11 = v8;\n v8 = (unsigned int)(v11 + 1);\n }\n v12 = *(_QWORD *)(v5 + 16);\n v13 = 0;\n if ( v12 )\n {\n v14 = *(_QWORD *)(v12 + 8);\n if ( v14 )\n v13 = get_height_part_0(v14, v4, a3, v8);\n v15 = *(_QWORD *)(v12 + 16);\n v16 = 0;\n if ( v15 )\n v16 = get_height_part_0(v15, v4, a3, v8);\n if ( v16 >= v13 )\n v13 = v16;\n ++v13;\n }\n if ( v13 < (int)v8 )\n v13 = v8;\n v6 = v13 + 1;\n }\n v17 = *(_QWORD *)(v4 + 16);\n v18 = 0LL;\n if ( v17 )\n {\n v19 = *(_QWORD *)(v17 + 8);\n v20 = 0;\n if ( v19 )\n {\n v21 = *(_QWORD *)(v19 + 8);\n if ( v21 )\n v18 = (unsigned int)get_height_part_0(v21, v4, a3, 0LL);\n v22 = *(_QWORD *)(v19 + 16);\n v23 = 0;\n if ( v22 )\n v23 = get_height_part_0(v22, v4, a3, v18);\n if ( v23 < (int)v18 )\n v23 = v18;\n v20 = v23 + 1;\n }\n v24 = *(_QWORD *)(v17 + 16);\n v18 = 0LL;\n if ( v24 )\n {\n v25 = *(_QWORD *)(v24 + 8);\n if ( v25 )\n v18 = (unsigned int)get_height_part_0(v25, v4, a3, 0LL);\n v26 = *(_QWORD *)(v24 + 16);\n v27 = 0;\n if ( v26 )\n v27 = get_height_part_0(v26, v4, a3, v18);\n if ( v27 >= (int)v18 )\n LODWORD(v18) = v27;\n LODWORD(v18) = v18 + 1;\n }\n if ( (int)v18 < v20 )\n LODWORD(v18) = v20;\n LODWORD(v18) = v18 + 1;\n }\n a1 = *(_QWORD *)(a1 + 16);\n if ( (int)v18 < v6 )\n LODWORD(v18) = v6;\n v28 = (unsigned int)(v18 + 1);\n if ( a1 )\n {\n v29 = *(_QWORD *)(a1 + 8);\n height_part_0 = 0;\n if ( v29 )\n goto LABEL_47;\n goto LABEL_60;\n }\nLABEL_83:\n if ( (unsigned int)(v28 + 1) > 2 )\n return 0LL;\n result = func0(v4);\n if ( !(_BYTE)result )\n return result;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_19F0:\nendbr64\npush rbx\nmov rbx, rdi\nloc_19F8:\ntest rbx, rbx\njz loc_1C68\nmov rsi, [rbx+8]\ntest rsi, rsi\njz loc_1C28\nmov r9, [rsi+8]\nxor r8d, r8d\ntest r9, r9\njz short loc_1A90\nmov r8, [r9+8]\nxor ecx, ecx\ntest r8, r8\njz short loc_1A4D\nmov rdi, [r8+8]\ntest rdi, rdi\njz short loc_1A35\ncall sub_13A0\nmov ecx, eax\nloc_1A35:\nmov rdi, [r8+10h]\nxor eax, eax\ntest rdi, rdi\njz short loc_1A45\ncall sub_13A0\nloc_1A45:\ncmp eax, ecx\ncmovl eax, ecx\nlea ecx, [rax+1]\nloc_1A4D:\nmov r9, [r9+10h]\nxor r8d, r8d\ntest r9, r9\njz short loc_1A85\nmov rdi, [r9+8]\ntest rdi, rdi\njz short loc_1A6A\ncall sub_13A0\nmov r8d, eax\nloc_1A6A:\nmov rdi, [r9+10h]\nxor eax, eax\ntest rdi, rdi\njz short loc_1A7A\ncall sub_13A0\nloc_1A7A:\ncmp eax, r8d\ncmovge r8d, eax\nadd r8d, 1\nloc_1A85:\ncmp r8d, ecx\ncmovl r8d, ecx\nadd r8d, 1\nloc_1A90:\nmov r10, [rsi+10h]\nxor ecx, ecx\ntest r10, r10\njz short loc_1B0D\nmov r11, [r10+8]\nxor r9d, r9d\ntest r11, r11\njz short loc_1AD0\nmov rdi, [r11+8]\ntest rdi, rdi\njz short loc_1AB7\ncall sub_13A0\nmov ecx, eax\nloc_1AB7:\nmov rdi, [r11+10h]\nxor eax, eax\ntest rdi, rdi\njz short loc_1AC7\ncall sub_13A0\nloc_1AC7:\ncmp eax, ecx\ncmovl eax, ecx\nlea r9d, [rax+1]\nloc_1AD0:\nmov r10, [r10+10h]\nxor ecx, ecx\ntest r10, r10\njz short loc_1B03\nmov rdi, [r10+8]\ntest rdi, rdi\njz short loc_1AEB\ncall sub_13A0\nmov ecx, eax\nloc_1AEB:\nmov rdi, [r10+10h]\nxor eax, eax\ntest rdi, rdi\njz short loc_1AFB\ncall sub_13A0\nloc_1AFB:\ncmp eax, ecx\ncmovge ecx, eax\nadd ecx, 1\nloc_1B03:\ncmp ecx, r9d\ncmovl ecx, r9d\nadd ecx, 1\nloc_1B0D:\ncmp ecx, r8d\nmov rbx, [rbx+10h]\ncmovl ecx, r8d\nadd ecx, 1\ntest rbx, rbx\njz loc_1C15\nmov r10, [rbx+8]\nxor r8d, r8d\ntest r10, r10\njz short loc_1B83\nloc_1B30:\nmov r11, [r10+8]\nxor r9d, r9d\ntest r11, r11\njz short loc_1B68\nmov rdi, [r11+8]\ntest rdi, rdi\njz short loc_1B4D\ncall sub_13A0\nmov r8d, eax\nloc_1B4D:\nmov rdi, [r11+10h]\nxor eax, eax\ntest rdi, rdi\njz short loc_1B5D\ncall sub_13A0\nloc_1B5D:\ncmp eax, r8d\ncmovl eax, r8d\nlea r9d, [rax+1]\nloc_1B68:\nmov rdi, [r10+10h]\nxor eax, eax\ntest rdi, rdi\njz short loc_1B78\ncall sub_13A0\nloc_1B78:\ncmp eax, r9d\ncmovl eax, r9d\nlea r8d, [rax+1]\nloc_1B83:\nmov r10, [rbx+10h]\nxor eax, eax\ntest r10, r10\njz short loc_1C09\nmov r11, [r10+8]\nxor r9d, r9d\ntest r11, r11\njz short loc_1BC6\nmov rdi, [r11+8]\ntest rdi, rdi\njz short loc_1BAB\ncall sub_13A0\nmov r9d, eax\nloc_1BAB:\nmov rdi, [r11+10h]\nxor eax, eax\ntest rdi, rdi\njz short loc_1BBB\ncall sub_13A0\nloc_1BBB:\ncmp eax, r9d\ncmovl eax, r9d\nlea r9d, [rax+1]\nloc_1BC6:\nmov r11, [r10+10h]\nxor eax, eax\ntest r11, r11\njz short loc_1BFF\nmov rdi, [r11+8]\nxor r10d, r10d\ntest rdi, rdi\njz short loc_1BE5\ncall sub_13A0\nmov r10d, eax\nloc_1BE5:\nmov rdi, [r11+10h]\nxor eax, eax\ntest rdi, rdi\njz short loc_1BF5\ncall sub_13A0\nloc_1BF5:\ncmp eax, r10d\ncmovl eax, r10d\nadd eax, 1\nloc_1BFF:\ncmp eax, r9d\ncmovl eax, r9d\nadd eax, 1\nloc_1C09:\ncmp eax, r8d\ncmovl eax, r8d\nadd eax, 1\nsub ecx, eax\nloc_1C15:\nadd ecx, 1\ncmp ecx, 2\njbe short loc_1C50\nxor eax, eax\npop rbx\nretn\nloc_1C28:\nmov rbx, [rbx+10h]\ntest rbx, rbx\njz short loc_1C68\nmov r10, [rbx+8]\nxor ecx, ecx\nxor r8d, r8d\ntest r10, r10\njnz loc_1B30\njmp loc_1B83\nloc_1C50:\nmov rdi, rsi\ncall sub_19F0\ntest al, al\njnz loc_19F8\npop rbx\nretn\nloc_1C68:\nmov eax, 1\npop rbx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_19F0(__int64 a1, __int64 a2, __int64 a3)\n{\n __int64 v4; // rsi\n __int64 v5; // r9\n int v6; // r8d\n __int64 v7; // r8\n __int64 v8; // rcx\n __int64 v9; // rdi\n __int64 v10; // rdi\n int v11; // eax\n __int64 v12; // r9\n int v13; // r8d\n __int64 v14; // rdi\n __int64 v15; // rdi\n int v16; // eax\n __int64 v17; // r10\n __int64 v18; // rcx\n __int64 v19; // r11\n int v20; // r9d\n __int64 v21; // rdi\n __int64 v22; // rdi\n int v23; // eax\n __int64 v24; // r10\n __int64 v25; // rdi\n __int64 v26; // rdi\n int v27; // eax\n __int64 v28; // rcx\n __int64 v29; // r10\n int v30; // r8d\n __int64 v31; // r11\n int v32; // r9d\n __int64 v33; // rdi\n __int64 v34; // rdi\n int v35; // eax\n __int64 v36; // rdi\n int v37; // eax\n __int64 v38; // r10\n int v39; // eax\n __int64 v40; // r11\n int v41; // r9d\n __int64 v42; // rdi\n __int64 v43; // rdi\n int v44; // eax\n __int64 v45; // r11\n int v46; // eax\n __int64 v47; // rdi\n int v48; // r10d\n __int64 v49; // rdi\n int v50; // eax\n __int64 result; // rax\n\n while ( a1 )\n {\n v4 = *(_QWORD *)(a1 + 8);\n if ( !v4 )\n {\n a1 = *(_QWORD *)(a1 + 16);\n if ( !a1 )\n return 1LL;\n v29 = *(_QWORD *)(a1 + 8);\n v28 = 0LL;\n v30 = 0;\n if ( v29 )\n {\nLABEL_47:\n v31 = *(_QWORD *)(v29 + 8);\n v32 = 0;\n if ( v31 )\n {\n v33 = *(_QWORD *)(v31 + 8);\n if ( v33 )\n v30 = sub_13A0(v33, v4, a3, v28);\n v34 = *(_QWORD *)(v31 + 16);\n v35 = 0;\n if ( v34 )\n v35 = sub_13A0(v34, v4, a3, v28);\n if ( v35 < v30 )\n v35 = v30;\n v32 = v35 + 1;\n }\n v36 = *(_QWORD *)(v29 + 16);\n v37 = 0;\n if ( v36 )\n v37 = sub_13A0(v36, v4, a3, v28);\n if ( v37 < v32 )\n v37 = v32;\n v30 = v37 + 1;\n }\nLABEL_60:\n v38 = *(_QWORD *)(a1 + 16);\n v39 = 0;\n if ( v38 )\n {\n v40 = *(_QWORD *)(v38 + 8);\n v41 = 0;\n if ( v40 )\n {\n v42 = *(_QWORD *)(v40 + 8);\n if ( v42 )\n v41 = sub_13A0(v42, v4, a3, v28);\n v43 = *(_QWORD *)(v40 + 16);\n v44 = 0;\n if ( v43 )\n v44 = sub_13A0(v43, v4, a3, v28);\n if ( v44 < v41 )\n v44 = v41;\n v41 = v44 + 1;\n }\n v45 = *(_QWORD *)(v38 + 16);\n v46 = 0;\n if ( v45 )\n {\n v47 = *(_QWORD *)(v45 + 8);\n v48 = 0;\n if ( v47 )\n v48 = sub_13A0(v47, v4, a3, v28);\n v49 = *(_QWORD *)(v45 + 16);\n v50 = 0;\n if ( v49 )\n v50 = sub_13A0(v49, v4, a3, v28);\n if ( v50 < v48 )\n v50 = v48;\n v46 = v50 + 1;\n }\n if ( v46 < v41 )\n v46 = v41;\n v39 = v46 + 1;\n }\n if ( v39 < v30 )\n v39 = v30;\n LODWORD(v28) = v28 - (v39 + 1);\n goto LABEL_83;\n }\n v5 = *(_QWORD *)(v4 + 8);\n v6 = 0;\n if ( v5 )\n {\n v7 = *(_QWORD *)(v5 + 8);\n v8 = 0LL;\n if ( v7 )\n {\n v9 = *(_QWORD *)(v7 + 8);\n if ( v9 )\n v8 = (unsigned int)sub_13A0(v9, v4, a3, 0LL);\n v10 = *(_QWORD *)(v7 + 16);\n v11 = 0;\n if ( v10 )\n v11 = sub_13A0(v10, v4, a3, v8);\n if ( v11 < (int)v8 )\n v11 = v8;\n v8 = (unsigned int)(v11 + 1);\n }\n v12 = *(_QWORD *)(v5 + 16);\n v13 = 0;\n if ( v12 )\n {\n v14 = *(_QWORD *)(v12 + 8);\n if ( v14 )\n v13 = sub_13A0(v14, v4, a3, v8);\n v15 = *(_QWORD *)(v12 + 16);\n v16 = 0;\n if ( v15 )\n v16 = sub_13A0(v15, v4, a3, v8);\n if ( v16 >= v13 )\n v13 = v16;\n ++v13;\n }\n if ( v13 < (int)v8 )\n v13 = v8;\n v6 = v13 + 1;\n }\n v17 = *(_QWORD *)(v4 + 16);\n v18 = 0LL;\n if ( v17 )\n {\n v19 = *(_QWORD *)(v17 + 8);\n v20 = 0;\n if ( v19 )\n {\n v21 = *(_QWORD *)(v19 + 8);\n if ( v21 )\n v18 = (unsigned int)sub_13A0(v21, v4, a3, 0LL);\n v22 = *(_QWORD *)(v19 + 16);\n v23 = 0;\n if ( v22 )\n v23 = sub_13A0(v22, v4, a3, v18);\n if ( v23 < (int)v18 )\n v23 = v18;\n v20 = v23 + 1;\n }\n v24 = *(_QWORD *)(v17 + 16);\n v18 = 0LL;\n if ( v24 )\n {\n v25 = *(_QWORD *)(v24 + 8);\n if ( v25 )\n v18 = (unsigned int)sub_13A0(v25, v4, a3, 0LL);\n v26 = *(_QWORD *)(v24 + 16);\n v27 = 0;\n if ( v26 )\n v27 = sub_13A0(v26, v4, a3, v18);\n if ( v27 >= (int)v18 )\n LODWORD(v18) = v27;\n LODWORD(v18) = v18 + 1;\n }\n if ( (int)v18 < v20 )\n LODWORD(v18) = v20;\n LODWORD(v18) = v18 + 1;\n }\n a1 = *(_QWORD *)(a1 + 16);\n if ( (int)v18 < v6 )\n LODWORD(v18) = v6;\n v28 = (unsigned int)(v18 + 1);\n if ( a1 )\n {\n v29 = *(_QWORD *)(a1 + 8);\n v30 = 0;\n if ( v29 )\n goto LABEL_47;\n goto LABEL_60;\n }\nLABEL_83:\n if ( (unsigned int)(v28 + 1) > 2 )\n return 0LL;\n result = sub_19F0(v4);\n if ( !(_BYTE)result )\n return result;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_19F0(long long a1, long long a2, long long a3) {\n long long v4;\n long long v5;\n int v6;\n long long v7;\n long long v8;\n long long v9;\n long long v10;\n int v11;\n long long v12;\n int v13;\n long long v14;\n long long v15;\n int v16;\n long long v17;\n long long v18;\n long long v19;\n int v20;\n long long v21;\n long long v22;\n int v23;\n long long v24;\n long long v25;\n long long v26;\n int v27;\n long long v28;\n long long v29;\n int v30;\n long long v31;\n int v32;\n long long v33;\n long long v34;\n int v35;\n long long v36;\n int v37;\n long long v38;\n int v39;\n long long v40;\n int v41;\n long long v42;\n long long v43;\n int v44;\n long long v45;\n int v46;\n long long v47;\n int v48;\n long long v49;\n int v50;\n long long result;\n while (a1) {\n v4 = *(uint64_t *)(a1 + 8);\n if (!v4) {\n a1 = *(uint64_t *)(a1 + 16);\n if (!a1) return 1LL;\n v29 = *(uint64_t *)(a1 + 8);\n v28 = 0LL;\n v30 = 0;\n if (v29) {\n LABEL_47:\n v31 = *(uint64_t *)(v29 + 8);\n v32 = 0;\n if (v31) {\n v33 = *(uint64_t *)(v31 + 8);\n if (v33) v30 = sub_13A0(v33, v4, a3, v28);\n v34 = *(uint64_t *)(v31 + 16);\n v35 = 0;\n if (v34) v35 = sub_13A0(v34, v4, a3, v28);\n if (v35 < v30) v35 = v30;\n v32 = v35 + 1;\n }\n v36 = *(uint64_t *)(v29 + 16);\n v37 = 0;\n if (v36) v37 = sub_13A0(v36, v4, a3, v28);\n if (v37 < v32) v37 = v32;\n v30 = v37 + 1;\n }\n LABEL_60:\n v38 = *(uint64_t *)(a1 + 16);\n v39 = 0;\n if (v38) {\n v40 = *(uint64_t *)(v38 + 8);\n v41 = 0;\n if (v40) {\n v42 = *(uint64_t *)(v40 + 8);\n if (v42) v41 = sub_13A0(v42, v4, a3, v28);\n v43 = *(uint64_t *)(v40 + 16);\n v44 = 0;\n if (v43) v44 = sub_13A0(v43, v4, a3, v28);\n if (v44 < v41) v44 = v41;\n v41 = v44 + 1;\n }\n v45 = *(uint64_t *)(v38 + 16);\n v46 = 0;\n if (v45) {\n v47 = *(uint64_t *)(v45 + 8);\n v48 = 0;\n if (v47) v48 = sub_13A0(v47, v4, a3, v28);\n v49 = *(uint64_t *)(v45 + 16);\n v50 = 0;\n if (v49) v50 = sub_13A0(v49, v4, a3, v28);\n if (v50 < v48) v50 = v48;\n v46 = v50 + 1;\n }\n if (v46 < v41) v46 = v41;\n v39 = v46 + 1;\n }\n if (v39 < v30) v39 = v30;\n LODWORD(v28) = v28 - (v39 + 1);\n goto LABEL_83;\n }\n v5 = *(uint64_t *)(v4 + 8);\n v6 = 0;\n if (v5) {\n v7 = *(uint64_t *)(v5 + 8);\n v8 = 0LL;\n if (v7) {\n v9 = *(uint64_t *)(v7 + 8);\n if (v9) v8 = (unsigned int)sub_13A0(v9, v4, a3, 0LL);\n v10 = *(uint64_t *)(v7 + 16);\n v11 = 0;\n if (v10) v11 = sub_13A0(v10, v4, a3, v8);\n if (v11 < (int)v8) v11 = v8;\n v8 = (unsigned int)(v11 + 1);\n }\n v12 = *(uint64_t *)(v5 + 16);\n v13 = 0;\n if (v12) {\n v14 = *(uint64_t *)(v12 + 8);\n if (v14) v13 = sub_13A0(v14, v4, a3, v8);\n v15 = *(uint64_t *)(v12 + 16);\n v16 = 0;\n if (v15) v16 = sub_13A0(v15, v4, a3, v8);\n if (v16 >= v13) v13 = v16;\n ++v13;\n }\n if (v13 < (int)v8) v13 = v8;\n v6 = v13 + 1;\n }\n v17 = *(uint64_t *)(v4 + 16);\n v18 = 0LL;\n if (v17) {\n v19 = *(uint64_t *)(v17 + 8);\n v20 = 0;\n if (v19) {\n v21 = *(uint64_t *)(v19 + 8);\n if (v21) v18 = (unsigned int)sub_13A0(v21, v4, a3, 0LL);\n v22 = *(uint64_t *)(v19 + 16);\n v23 = 0;\n if (v22) v23 = sub_13A0(v22, v4, a3, v18);\n if (v23 < (int)v18) v23 = v18;\n v20 = v23 + 1;\n }\n v24 = *(uint64_t *)(v17 + 16);\n v18 = 0LL;\n if (v24) {\n v25 = *(uint64_t *)(v24 + 8);\n if (v25) v18 = (unsigned int)sub_13A0(v25, v4, a3, 0LL);\n v26 = *(uint64_t *)(v24 + 16);\n v27 = 0;\n if (v26) v27 = sub_13A0(v26, v4, a3, v18);\n if (v27 >= (int)v18) LODWORD(v18) = v27;\n LODWORD(v18) = v18 + 1;\n }\n if ((int)v18 < v20) LODWORD(v18) = v20;\n LODWORD(v18) = v18 + 1;\n }\n a1 = *(uint64_t *)(a1 + 16);\n if ((int)v18 < v6) LODWORD(v18) = v6;\n v28 = (unsigned int)(v18 + 1);\n if (a1) {\n v29 = *(uint64_t *)(a1 + 8);\n v30 = 0;\n if (v29) goto LABEL_47;\n goto LABEL_60;\n }\n LABEL_83:\n if ((unsigned int)(v28 + 1) > 2) return 0LL;\n result = sub_19F0(v4);\n if (!(uint8_t)result) return result;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, long long a3) {\n long long v4;\n long long v5;\n int v6;\n long long v7;\n long long v8;\n long long v9;\n long long v10;\n int v11;\n long long v12;\n int v13;\n long long v14;\n long long v15;\n int v16;\n long long v17;\n long long v18;\n long long v19;\n int v20;\n long long v21;\n long long v22;\n int v23;\n long long v24;\n long long v25;\n long long v26;\n int v27;\n long long v28;\n long long v29;\n int height_part_0;\n long long v31;\n int v32;\n long long v33;\n long long v34;\n int v35;\n long long v36;\n int v37;\n long long v38;\n int v39;\n long long v40;\n int v41;\n long long v42;\n long long v43;\n int v44;\n long long v45;\n int v46;\n long long v47;\n int v48;\n long long v49;\n int v50;\n long long result;\n while (a1) {\n v4 = *(uint64_t *)(a1 + 8);\n if (!v4) {\n a1 = *(uint64_t *)(a1 + 16);\n if (!a1) return 1LL;\n v29 = *(uint64_t *)(a1 + 8);\n v28 = 0LL;\n height_part_0 = 0;\n if (v29) {\n LABEL_47:\n v31 = *(uint64_t *)(v29 + 8);\n v32 = 0;\n if (v31) {\n v33 = *(uint64_t *)(v31 + 8);\n if (v33) height_part_0 = get_height_part_0(v33, v4, a3, v28);\n v34 = *(uint64_t *)(v31 + 16);\n v35 = 0;\n if (v34) v35 = get_height_part_0(v34, v4, a3, v28);\n if (v35 < height_part_0) v35 = height_part_0;\n v32 = v35 + 1;\n }\n v36 = *(uint64_t *)(v29 + 16);\n v37 = 0;\n if (v36) v37 = get_height_part_0(v36, v4, a3, v28);\n if (v37 < v32) v37 = v32;\n height_part_0 = v37 + 1;\n }\n LABEL_60:\n v38 = *(uint64_t *)(a1 + 16);\n v39 = 0;\n if (v38) {\n v40 = *(uint64_t *)(v38 + 8);\n v41 = 0;\n if (v40) {\n v42 = *(uint64_t *)(v40 + 8);\n if (v42) v41 = get_height_part_0(v42, v4, a3, v28);\n v43 = *(uint64_t *)(v40 + 16);\n v44 = 0;\n if (v43) v44 = get_height_part_0(v43, v4, a3, v28);\n if (v44 < v41) v44 = v41;\n v41 = v44 + 1;\n }\n v45 = *(uint64_t *)(v38 + 16);\n v46 = 0;\n if (v45) {\n v47 = *(uint64_t *)(v45 + 8);\n v48 = 0;\n if (v47) v48 = get_height_part_0(v47, v4, a3, v28);\n v49 = *(uint64_t *)(v45 + 16);\n v50 = 0;\n if (v49) v50 = get_height_part_0(v49, v4, a3, v28);\n if (v50 < v48) v50 = v48;\n v46 = v50 + 1;\n }\n if (v46 < v41) v46 = v41;\n v39 = v46 + 1;\n }\n if (v39 < height_part_0) v39 = height_part_0;\n LODWORD(v28) = v28 - (v39 + 1);\n goto LABEL_83;\n }\n v5 = *(uint64_t *)(v4 + 8);\n v6 = 0;\n if (v5) {\n v7 = *(uint64_t *)(v5 + 8);\n v8 = 0LL;\n if (v7) {\n v9 = *(uint64_t *)(v7 + 8);\n if (v9) v8 = (unsigned int)get_height_part_0(v9, v4, a3, 0LL);\n v10 = *(uint64_t *)(v7 + 16);\n v11 = 0;\n if (v10) v11 = get_height_part_0(v10, v4, a3, v8);\n if (v11 < (int)v8) v11 = v8;\n v8 = (unsigned int)(v11 + 1);\n }\n v12 = *(uint64_t *)(v5 + 16);\n v13 = 0;\n if (v12) {\n v14 = *(uint64_t *)(v12 + 8);\n if (v14) v13 = get_height_part_0(v14, v4, a3, v8);\n v15 = *(uint64_t *)(v12 + 16);\n v16 = 0;\n if (v15) v16 = get_height_part_0(v15, v4, a3, v8);\n if (v16 >= v13) v13 = v16;\n ++v13;\n }\n if (v13 < (int)v8) v13 = v8;\n v6 = v13 + 1;\n }\n v17 = *(uint64_t *)(v4 + 16);\n v18 = 0LL;\n if (v17) {\n v19 = *(uint64_t *)(v17 + 8);\n v20 = 0;\n if (v19) {\n v21 = *(uint64_t *)(v19 + 8);\n if (v21) v18 = (unsigned int)get_height_part_0(v21, v4, a3, 0LL);\n v22 = *(uint64_t *)(v19 + 16);\n v23 = 0;\n if (v22) v23 = get_height_part_0(v22, v4, a3, v18);\n if (v23 < (int)v18) v23 = v18;\n v20 = v23 + 1;\n }\n v24 = *(uint64_t *)(v17 + 16);\n v18 = 0LL;\n if (v24) {\n v25 = *(uint64_t *)(v24 + 8);\n if (v25) v18 = (unsigned int)get_height_part_0(v25, v4, a3, 0LL);\n v26 = *(uint64_t *)(v24 + 16);\n v27 = 0;\n if (v26) v27 = get_height_part_0(v26, v4, a3, v18);\n if (v27 >= (int)v18) LODWORD(v18) = v27;\n LODWORD(v18) = v18 + 1;\n }\n if ((int)v18 < v20) LODWORD(v18) = v20;\n LODWORD(v18) = v18 + 1;\n }\n a1 = *(uint64_t *)(a1 + 16);\n if ((int)v18 < v6) LODWORD(v18) = v6;\n v28 = (unsigned int)(v18 + 1);\n if (a1) {\n v29 = *(uint64_t *)(a1 + 8);\n height_part_0 = 0;\n if (v29) goto LABEL_47;\n goto LABEL_60;\n }\n LABEL_83:\n if ((unsigned int)(v28 + 1) > 2) return 0LL;\n result = func0(v4);\n if (!(uint8_t)result) return result;\n }\n return 1LL;\n}" + }, + { + "index": 367, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct Node {\n\n int data;\n\n struct Node *left;\n\n struct Node *right;\n\n} Node;\n\n\n\nNode* newNode(int data) {\n\n Node* node = (Node*)malloc(sizeof(Node));\n\n node->data = data;\n\n node->left = NULL;\n\n node->right = NULL;\n\n return node;\n\n}\n\n\n\nint get_height(Node* root) {\n\n if (root == NULL) {\n\n return 0;\n\n }\n\n int leftHeight = get_height(root->left);\n\n int rightHeight = get_height(root->right);\n\n return (leftHeight > rightHeight ? leftHeight : rightHeight) + 1;\n\n}\n\n\n\n", + "func": "bool func0(Node* root) {\n if (root == NULL) {\n return true;\n }\n int lh = get_height(root->left);\n int rh = get_height(root->right);\n if (abs(lh - rh) <= 1 && func0(root->left) && func0(root->right)) {\n return true;\n }\n return false;\n}", + "test": "int main() {\n\n Node* root = newNode(1);\n\n root->left = newNode(2);\n\n root->right = newNode(3);\n\n root->left->left = newNode(4);\n\n root->left->right = newNode(5);\n\n root->left->left->left = newNode(8);\n\n \n\n Node* root1 = newNode(1);\n\n root1->left = newNode(2);\n\n root1->right = newNode(3);\n\n root1->left->left = newNode(4);\n\n root1->left->right = newNode(5);\n\n root1->right->left = newNode(6);\n\n root1->left->left->left = newNode(7);\n\n \n\n Node* root2 = newNode(1);\n\n root2->left = newNode(2);\n\n root2->right = newNode(3);\n\n root2->left->left = newNode(4);\n\n root2->left->right = newNode(5);\n\n root2->left->left->left = newNode(7);\n\n \n\n assert(func0(root) == false);\n\n assert(func0(root1) == true);\n\n assert(func0(root2) == false);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nmov %rdi,%rbx\nsub $0x8,%rsp\ntest %rbx,%rbx\nje 22b0 \nmov 0x8(%rbx),%r8\nmov 0x10(%rbx),%rbx\ntest %r8,%r8\nje 2288 \nmov 0x8(%r8),%rsi\nxor %ecx,%ecx\ntest %rsi,%rsi\nje 1b84 \nmov 0x8(%rsi),%r10\ntest %r10,%r10\nje 1a6f \nmov 0x8(%r10),%r9\ntest %r9,%r9\nje 19ea \nmov 0x8(%r9),%r11\ntest %r11,%r11\nje 19af \nmov 0x8(%r11),%rdi\nxor %edx,%edx\ntest %rdi,%rdi\nje 1997 \ncallq 1410 \nmov %eax,%edx\nmov 0x10(%r11),%rdi\nxor %eax,%eax\ntest %rdi,%rdi\nje 19a7 \ncallq 1410 \ncmp %edx,%eax\ncmovge %eax,%edx\nlea 0x1(%rdx),%ecx\nmov 0x10(%r9),%r9\nxor %edx,%edx\ntest %r9,%r9\nje 19e2 \nmov 0x8(%r9),%rdi\ntest %rdi,%rdi\nje 19ca \ncallq 1410 \nmov %eax,%edx\nmov 0x10(%r9),%rdi\nxor %eax,%eax\ntest %rdi,%rdi\nje 19da \ncallq 1410 \ncmp %edx,%eax\ncmovl %edx,%eax\nlea 0x1(%rax),%edx\ncmp %ecx,%edx\ncmovl %ecx,%edx\nlea 0x1(%rdx),%ecx\nmov 0x10(%r10),%r9\nxor %edx,%edx\ntest %r9,%r9\nje 1a67 \nmov 0x8(%r9),%r10\ntest %r10,%r10\nje 1a26 \nmov 0x8(%r10),%rdi\ntest %rdi,%rdi\nje 1a0e \ncallq 1410 \nmov %eax,%edx\nmov 0x10(%r10),%rdi\nxor %eax,%eax\ntest %rdi,%rdi\nje 1a1e \ncallq 1410 \ncmp %edx,%eax\ncmovl %edx,%eax\nlea 0x1(%rax),%edx\nmov 0x10(%r9),%r10\nxor %eax,%eax\ntest %r10,%r10\nje 1a5f \nmov 0x8(%r10),%rdi\nxor %r9d,%r9d\ntest %rdi,%rdi\nje 1a45 \ncallq 1410 \nmov %eax,%r9d\nmov 0x10(%r10),%rdi\nxor %eax,%eax\ntest %rdi,%rdi\nje 1a55 \ncallq 1410 \ncmp %r9d,%eax\ncmovl %r9d,%eax\nadd $0x1,%eax\ncmp %edx,%eax\ncmovl %edx,%eax\nlea 0x1(%rax),%edx\ncmp %ecx,%edx\ncmovl %ecx,%edx\nlea 0x1(%rdx),%ecx\nmov 0x10(%rsi),%r9\nxor %edx,%edx\ntest %r9,%r9\nje 1b7c \nmov 0x8(%r9),%rsi\ntest %rsi,%rsi\nje 1af5 \nmov 0x8(%rsi),%r10\ntest %r10,%r10\nje 1ab8 \nmov 0x8(%r10),%rdi\ntest %rdi,%rdi\nje 1aa0 \ncallq 1410 \nmov %eax,%edx\nmov 0x10(%r10),%rdi\nxor %eax,%eax\ntest %rdi,%rdi\nje 1ab0 \ncallq 1410 \ncmp %edx,%eax\ncmovl %edx,%eax\nlea 0x1(%rax),%edx\nmov 0x10(%rsi),%r10\nxor %eax,%eax\ntest %r10,%r10\nje 1aed \nmov 0x8(%r10),%rdi\nxor %esi,%esi\ntest %rdi,%rdi\nje 1ad5 \ncallq 1410 \nmov %eax,%esi\nmov 0x10(%r10),%rdi\nxor %eax,%eax\ntest %rdi,%rdi\nje 1ae5 \ncallq 1410 \ncmp %esi,%eax\ncmovl %esi,%eax\nadd $0x1,%eax\ncmp %edx,%eax\ncmovl %edx,%eax\nlea 0x1(%rax),%edx\nmov 0x10(%r9),%r9\nxor %eax,%eax\ntest %r9,%r9\nje 1b74 \nmov 0x8(%r9),%r10\nxor %esi,%esi\ntest %r10,%r10\nje 1b33 \nmov 0x8(%r10),%rdi\ntest %rdi,%rdi\nje 1b1b \ncallq 1410 \nmov %eax,%esi\nmov 0x10(%r10),%rdi\nxor %eax,%eax\ntest %rdi,%rdi\nje 1b2b \ncallq 1410 \ncmp %esi,%eax\ncmovl %esi,%eax\nlea 0x1(%rax),%esi\nmov 0x10(%r9),%r10\nxor %eax,%eax\ntest %r10,%r10\nje 1b6c \nmov 0x8(%r10),%rdi\nxor %r9d,%r9d\ntest %rdi,%rdi\nje 1b52 \ncallq 1410 \nmov %eax,%r9d\nmov 0x10(%r10),%rdi\nxor %eax,%eax\ntest %rdi,%rdi\nje 1b62 \ncallq 1410 \ncmp %r9d,%eax\ncmovl %r9d,%eax\nadd $0x1,%eax\ncmp %esi,%eax\ncmovl %esi,%eax\nadd $0x1,%eax\ncmp %edx,%eax\ncmovl %edx,%eax\nlea 0x1(%rax),%edx\ncmp %ecx,%edx\ncmovl %ecx,%edx\nlea 0x1(%rdx),%ecx\nmov 0x10(%r8),%r9\nxor %edx,%edx\ntest %r9,%r9\nje 1dbc \nmov 0x8(%r9),%r10\nxor %esi,%esi\ntest %r10,%r10\nje 1c9c \nmov 0x8(%r10),%r11\ntest %r11,%r11\nje 1c17 \nmov 0x8(%r11),%rbp\ntest %rbp,%rbp\nje 1bdc \nmov 0x8(%rbp),%rdi\ntest %rdi,%rdi\nje 1bc4 \ncallq 1410 \nmov %eax,%edx\nmov 0x10(%rbp),%rdi\nxor %eax,%eax\ntest %rdi,%rdi\nje 1bd4 \ncallq 1410 \ncmp %edx,%eax\ncmovge %eax,%edx\nlea 0x1(%rdx),%esi\nmov 0x10(%r11),%r11\nxor %edx,%edx\ntest %r11,%r11\nje 1c0f \nmov 0x8(%r11),%rdi\ntest %rdi,%rdi\nje 1bf7 \ncallq 1410 \nmov %eax,%edx\nmov 0x10(%r11),%rdi\nxor %eax,%eax\ntest %rdi,%rdi\nje 1c07 \ncallq 1410 \ncmp %edx,%eax\ncmovl %edx,%eax\nlea 0x1(%rax),%edx\ncmp %esi,%edx\ncmovl %esi,%edx\nlea 0x1(%rdx),%esi\nmov 0x10(%r10),%r10\nxor %edx,%edx\ntest %r10,%r10\nje 1c94 \nmov 0x8(%r10),%r11\ntest %r11,%r11\nje 1c53 \nmov 0x8(%r11),%rdi\ntest %rdi,%rdi\nje 1c3b \ncallq 1410 \nmov %eax,%edx\nmov 0x10(%r11),%rdi\nxor %eax,%eax\ntest %rdi,%rdi\nje 1c4b \ncallq 1410 \ncmp %edx,%eax\ncmovl %edx,%eax\nlea 0x1(%rax),%edx\nmov 0x10(%r10),%r11\nxor %eax,%eax\ntest %r11,%r11\nje 1c8c \nmov 0x8(%r11),%rdi\nxor %r10d,%r10d\ntest %rdi,%rdi\nje 1c72 \ncallq 1410 \nmov %eax,%r10d\nmov 0x10(%r11),%rdi\nxor %eax,%eax\ntest %rdi,%rdi\nje 1c82 \ncallq 1410 \ncmp %r10d,%eax\ncmovl %r10d,%eax\nadd $0x1,%eax\ncmp %edx,%eax\ncmovl %edx,%eax\nlea 0x1(%rax),%edx\ncmp %esi,%edx\ncmovl %esi,%edx\nlea 0x1(%rdx),%esi\nmov 0x10(%r9),%r9\nxor %edx,%edx\ntest %r9,%r9\nje 1db4 \nmov 0x8(%r9),%r10\ntest %r10,%r10\nje 1d26 \nmov 0x8(%r10),%r11\ntest %r11,%r11\nje 1ce5 \nmov 0x8(%r11),%rdi\ntest %rdi,%rdi\nje 1ccd \ncallq 1410 \nmov %eax,%edx\nmov 0x10(%r11),%rdi\nxor %eax,%eax\ntest %rdi,%rdi\nje 1cdd \ncallq 1410 \ncmp %edx,%eax\ncmovl %edx,%eax\nlea 0x1(%rax),%edx\nmov 0x10(%r10),%r11\nxor %eax,%eax\ntest %r11,%r11\nje 1d1e \nmov 0x8(%r11),%rdi\nxor %r10d,%r10d\ntest %rdi,%rdi\nje 1d04 \ncallq 1410 \nmov %eax,%r10d\nmov 0x10(%r11),%rdi\nxor %eax,%eax\ntest %rdi,%rdi\nje 1d14 \ncallq 1410 \ncmp %r10d,%eax\ncmovl %r10d,%eax\nadd $0x1,%eax\ncmp %edx,%eax\ncmovl %edx,%eax\nlea 0x1(%rax),%edx\nmov 0x10(%r9),%r10\nxor %eax,%eax\ntest %r10,%r10\nje 1dac \nmov 0x8(%r10),%r11\nxor %r9d,%r9d\ntest %r11,%r11\nje 1d69 \nmov 0x8(%r11),%rdi\ntest %rdi,%rdi\nje 1d4e \ncallq 1410 \nmov %eax,%r9d\nmov 0x10(%r11),%rdi\nxor %eax,%eax\ntest %rdi,%rdi\nje 1d5e \ncallq 1410 \ncmp %r9d,%eax\ncmovl %r9d,%eax\nlea 0x1(%rax),%r9d\nmov 0x10(%r10),%r11\nxor %eax,%eax\ntest %r11,%r11\nje 1da2 \nmov 0x8(%r11),%rdi\nxor %r10d,%r10d\ntest %rdi,%rdi\nje 1d88 \ncallq 1410 \nmov %eax,%r10d\nmov 0x10(%r11),%rdi\nxor %eax,%eax\ntest %rdi,%rdi\nje 1d98 \ncallq 1410 \ncmp %r10d,%eax\ncmovl %r10d,%eax\nadd $0x1,%eax\ncmp %r9d,%eax\ncmovl %r9d,%eax\nadd $0x1,%eax\ncmp %edx,%eax\ncmovl %edx,%eax\nlea 0x1(%rax),%edx\ncmp %esi,%edx\ncmovl %esi,%edx\nadd $0x1,%edx\ncmp %ecx,%edx\ncmovl %ecx,%edx\nadd $0x1,%edx\ntest %rbx,%rbx\nje 2271 \nmov 0x8(%rbx),%rsi\nxor %ecx,%ecx\ntest %rsi,%rsi\nje 2014 \nmov 0x8(%rsi),%r9\ntest %r9,%r9\nje 1ef2 \nmov 0x8(%r9),%r10\ntest %r10,%r10\nje 1e64 \nmov 0x8(%r10),%r11\ntest %r11,%r11\nje 1e23 \nmov 0x8(%r11),%rdi\ntest %rdi,%rdi\nje 1e0b \ncallq 1410 \nmov %eax,%ecx\nmov 0x10(%r11),%rdi\nxor %eax,%eax\ntest %rdi,%rdi\nje 1e1b \ncallq 1410 \ncmp %ecx,%eax\ncmovl %ecx,%eax\nlea 0x1(%rax),%ecx\nmov 0x10(%r10),%r11\nxor %eax,%eax\ntest %r11,%r11\nje 1e5c \nmov 0x8(%r11),%rdi\nxor %r10d,%r10d\ntest %rdi,%rdi\nje 1e42 \ncallq 1410 \nmov %eax,%r10d\nmov 0x10(%r11),%rdi\nxor %eax,%eax\ntest %rdi,%rdi\nje 1e52 \ncallq 1410 \ncmp %r10d,%eax\ncmovl %r10d,%eax\nadd $0x1,%eax\ncmp %ecx,%eax\ncmovl %ecx,%eax\nlea 0x1(%rax),%ecx\nmov 0x10(%r9),%r10\nxor %eax,%eax\ntest %r10,%r10\nje 1eea \nmov 0x8(%r10),%r11\nxor %r9d,%r9d\ntest %r11,%r11\nje 1ea7 \nmov 0x8(%r11),%rdi\ntest %rdi,%rdi\nje 1e8c \ncallq 1410 \nmov %eax,%r9d\nmov 0x10(%r11),%rdi\nxor %eax,%eax\ntest %rdi,%rdi\nje 1e9c \ncallq 1410 \ncmp %r9d,%eax\ncmovl %r9d,%eax\nlea 0x1(%rax),%r9d\nmov 0x10(%r10),%r11\nxor %eax,%eax\ntest %r11,%r11\nje 1ee0 \nmov 0x8(%r11),%rdi\nxor %r10d,%r10d\ntest %rdi,%rdi\nje 1ec6 \ncallq 1410 \nmov %eax,%r10d\nmov 0x10(%r11),%rdi\nxor %eax,%eax\ntest %rdi,%rdi\nje 1ed6 \ncallq 1410 \ncmp %r10d,%eax\ncmovl %r10d,%eax\nadd $0x1,%eax\ncmp %r9d,%eax\ncmovl %r9d,%eax\nadd $0x1,%eax\ncmp %ecx,%eax\ncmovl %ecx,%eax\nlea 0x1(%rax),%ecx\nmov 0x10(%rsi),%r9\nxor %eax,%eax\ntest %r9,%r9\nje 200c \nmov 0x8(%r9),%r10\nxor %esi,%esi\ntest %r10,%r10\nje 1f7e \nmov 0x8(%r10),%r11\ntest %r11,%r11\nje 1f3d \nmov 0x8(%r11),%rdi\ntest %rdi,%rdi\nje 1f25 \ncallq 1410 \nmov %eax,%esi\nmov 0x10(%r11),%rdi\nxor %eax,%eax\ntest %rdi,%rdi\nje 1f35 \ncallq 1410 \ncmp %esi,%eax\ncmovl %esi,%eax\nlea 0x1(%rax),%esi\nmov 0x10(%r10),%r11\nxor %eax,%eax\ntest %r11,%r11\nje 1f76 \nmov 0x8(%r11),%rdi\nxor %r10d,%r10d\ntest %rdi,%rdi\nje 1f5c \ncallq 1410 \nmov %eax,%r10d\nmov 0x10(%r11),%rdi\nxor %eax,%eax\ntest %rdi,%rdi\nje 1f6c \ncallq 1410 \ncmp %r10d,%eax\ncmovl %r10d,%eax\nadd $0x1,%eax\ncmp %esi,%eax\ncmovl %esi,%eax\nlea 0x1(%rax),%esi\nmov 0x10(%r9),%r10\nxor %eax,%eax\ntest %r10,%r10\nje 2004 \nmov 0x8(%r10),%r11\nxor %r9d,%r9d\ntest %r11,%r11\nje 1fc1 \nmov 0x8(%r11),%rdi\ntest %rdi,%rdi\nje 1fa6 \ncallq 1410 \nmov %eax,%r9d\nmov 0x10(%r11),%rdi\nxor %eax,%eax\ntest %rdi,%rdi\nje 1fb6 \ncallq 1410 \ncmp %r9d,%eax\ncmovl %r9d,%eax\nlea 0x1(%rax),%r9d\nmov 0x10(%r10),%r11\nxor %eax,%eax\ntest %r11,%r11\nje 1ffa \nmov 0x8(%r11),%rdi\nxor %r10d,%r10d\ntest %rdi,%rdi\nje 1fe0 \ncallq 1410 \nmov %eax,%r10d\nmov 0x10(%r11),%rdi\nxor %eax,%eax\ntest %rdi,%rdi\nje 1ff0 \ncallq 1410 \ncmp %r10d,%eax\ncmovl %r10d,%eax\nadd $0x1,%eax\ncmp %r9d,%eax\ncmovl %r9d,%eax\nadd $0x1,%eax\ncmp %esi,%eax\ncmovl %esi,%eax\nadd $0x1,%eax\ncmp %ecx,%eax\ncmovl %ecx,%eax\nlea 0x1(%rax),%ecx\nmov 0x10(%rbx),%r9\nxor %eax,%eax\ntest %r9,%r9\nje 2267 \nmov 0x8(%r9),%r10\nxor %esi,%esi\ntest %r10,%r10\nje 213b \nmov 0x8(%r10),%r11\ntest %r11,%r11\nje 20ad \nmov 0x8(%r11),%rbp\ntest %rbp,%rbp\nje 206c \nmov 0x8(%rbp),%rdi\ntest %rdi,%rdi\nje 2054 \ncallq 1410 \nmov %eax,%esi\nmov 0x10(%rbp),%rdi\nxor %eax,%eax\ntest %rdi,%rdi\nje 2064 \ncallq 1410 \ncmp %esi,%eax\ncmovl %esi,%eax\nlea 0x1(%rax),%esi\nmov 0x10(%r11),%rbp\nxor %eax,%eax\ntest %rbp,%rbp\nje 20a5 \nmov 0x8(%rbp),%rdi\nxor %r11d,%r11d\ntest %rdi,%rdi\nje 208b \ncallq 1410 \nmov %eax,%r11d\nmov 0x10(%rbp),%rdi\nxor %eax,%eax\ntest %rdi,%rdi\nje 209b \ncallq 1410 \ncmp %r11d,%eax\ncmovl %r11d,%eax\nadd $0x1,%eax\ncmp %esi,%eax\ncmovl %esi,%eax\nlea 0x1(%rax),%esi\nmov 0x10(%r10),%r11\nxor %eax,%eax\ntest %r11,%r11\nje 2133 \nmov 0x8(%r11),%rbp\nxor %r10d,%r10d\ntest %rbp,%rbp\nje 20f0 \nmov 0x8(%rbp),%rdi\ntest %rdi,%rdi\nje 20d5 \ncallq 1410 \nmov %eax,%r10d\nmov 0x10(%rbp),%rdi\nxor %eax,%eax\ntest %rdi,%rdi\nje 20e5 \ncallq 1410 \ncmp %r10d,%eax\ncmovl %r10d,%eax\nlea 0x1(%rax),%r10d\nmov 0x10(%r11),%rbp\nxor %eax,%eax\ntest %rbp,%rbp\nje 2129 \nmov 0x8(%rbp),%rdi\nxor %r11d,%r11d\ntest %rdi,%rdi\nje 210f \ncallq 1410 \nmov %eax,%r11d\nmov 0x10(%rbp),%rdi\nxor %eax,%eax\ntest %rdi,%rdi\nje 211f \ncallq 1410 \ncmp %r11d,%eax\ncmovl %r11d,%eax\nadd $0x1,%eax\ncmp %r10d,%eax\ncmovl %r10d,%eax\nadd $0x1,%eax\ncmp %esi,%eax\ncmovl %esi,%eax\nlea 0x1(%rax),%esi\nmov 0x10(%r9),%r10\nxor %eax,%eax\ntest %r10,%r10\nje 225f \nmov 0x8(%r10),%r11\nxor %r9d,%r9d\ntest %r11,%r11\nje 21cf \nmov 0x8(%r11),%rbp\ntest %rbp,%rbp\nje 218b \nmov 0x8(%rbp),%rdi\ntest %rdi,%rdi\nje 2170 \ncallq 1410 \nmov %eax,%r9d\nmov 0x10(%rbp),%rdi\nxor %eax,%eax\ntest %rdi,%rdi\nje 2180 \ncallq 1410 \ncmp %r9d,%eax\ncmovl %r9d,%eax\nlea 0x1(%rax),%r9d\nmov 0x10(%r11),%rbp\nxor %eax,%eax\ntest %rbp,%rbp\nje 21c4 \nmov 0x8(%rbp),%rdi\nxor %r11d,%r11d\ntest %rdi,%rdi\nje 21aa \ncallq 1410 \nmov %eax,%r11d\nmov 0x10(%rbp),%rdi\nxor %eax,%eax\ntest %rdi,%rdi\nje 21ba \ncallq 1410 \ncmp %r11d,%eax\ncmovl %r11d,%eax\nadd $0x1,%eax\ncmp %r9d,%eax\ncmovl %r9d,%eax\nlea 0x1(%rax),%r9d\nmov 0x10(%r10),%r11\nxor %eax,%eax\ntest %r11,%r11\nje 2255 \nmov 0x8(%r11),%rbp\nxor %r10d,%r10d\ntest %rbp,%rbp\nje 2212 \nmov 0x8(%rbp),%rdi\ntest %rdi,%rdi\nje 21f7 \ncallq 1410 \nmov %eax,%r10d\nmov 0x10(%rbp),%rdi\nxor %eax,%eax\ntest %rdi,%rdi\nje 2207 \ncallq 1410 \ncmp %r10d,%eax\ncmovl %r10d,%eax\nlea 0x1(%rax),%r10d\nmov 0x10(%r11),%rbp\nxor %eax,%eax\ntest %rbp,%rbp\nje 224b \nmov 0x8(%rbp),%rdi\nxor %r11d,%r11d\ntest %rdi,%rdi\nje 2231 \ncallq 1410 \nmov %eax,%r11d\nmov 0x10(%rbp),%rdi\nxor %eax,%eax\ntest %rdi,%rdi\nje 2241 \ncallq 1410 \ncmp %r11d,%eax\ncmovl %r11d,%eax\nadd $0x1,%eax\ncmp %r10d,%eax\ncmovl %r10d,%eax\nadd $0x1,%eax\ncmp %r9d,%eax\ncmovl %r9d,%eax\nadd $0x1,%eax\ncmp %esi,%eax\ncmovl %esi,%eax\nadd $0x1,%eax\ncmp %ecx,%eax\ncmovl %ecx,%eax\nadd $0x1,%eax\nsub %eax,%edx\nadd $0x1,%edx\ncmp $0x2,%edx\njbe 2293 \nadd $0x8,%rsp\nxor %eax,%eax\npop %rbx\npop %rbp\nretq\nnopw 0x0(%rax,%rax,1)\nxor %edx,%edx\ntest %rbx,%rbx\njne 1dcd \nmov %r8,%rdi\ncallq 1930 \ntest %al,%al\njne 193d \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopw 0x0(%rax,%rax,1)\nadd $0x8,%rsp\nmov $0x1,%eax\npop %rbx\npop %rbp\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\nloc_19F8:\ntest rbx, rbx\njz loc_1C48\nmov r8, [rbx+8]\ntest r8, r8\njz loc_1C10\nmov r9, [r8+8]\nxor esi, esi\ntest r9, r9\njz short loc_1A87\nmov rsi, [r9+8]\nxor ecx, ecx\ntest rsi, rsi\njz short loc_1A4C\nmov rdi, [rsi+8]\ntest rdi, rdi\njz short loc_1A34\ncall get_height_part_0\nmov ecx, eax\nloc_1A34:\nmov rdi, [rsi+10h]\nxor eax, eax\ntest rdi, rdi\njz short loc_1A44\ncall get_height_part_0\nloc_1A44:\ncmp eax, ecx\ncmovl eax, ecx\nlea ecx, [rax+1]\nloc_1A4C:\nmov r9, [r9+10h]\nxor esi, esi\ntest r9, r9\njz short loc_1A7F\nmov rdi, [r9+8]\ntest rdi, rdi\njz short loc_1A67\ncall get_height_part_0\nmov esi, eax\nloc_1A67:\nmov rdi, [r9+10h]\nxor eax, eax\ntest rdi, rdi\njz short loc_1A77\ncall get_height_part_0\nloc_1A77:\ncmp eax, esi\ncmovge esi, eax\nadd esi, 1\nloc_1A7F:\ncmp esi, ecx\ncmovl esi, ecx\nadd esi, 1\nloc_1A87:\nmov r9, [r8+10h]\nxor ecx, ecx\ntest r9, r9\njz short loc_1ADB\nmov r10, [r9+8]\ntest r10, r10\njz short loc_1AC3\nmov rdi, [r10+8]\ntest rdi, rdi\njz short loc_1AAB\ncall get_height_part_0\nmov ecx, eax\nloc_1AAB:\nmov rdi, [r10+10h]\nxor eax, eax\ntest rdi, rdi\njz short loc_1ABB\ncall get_height_part_0\nloc_1ABB:\ncmp eax, ecx\ncmovl eax, ecx\nlea ecx, [rax+1]\nloc_1AC3:\nmov rdi, [r9+10h]\nxor eax, eax\ntest rdi, rdi\njz short loc_1AD3\ncall get_height_part_0\nloc_1AD3:\ncmp eax, ecx\ncmovge ecx, eax\nadd ecx, 1\nloc_1ADB:\ncmp ecx, esi\nmov rbx, [rbx+10h]\ncmovl ecx, esi\nadd ecx, 1\ntest rbx, rbx\njz loc_1BFD\nmov r10, [rbx+8]\nxor esi, esi\ntest r10, r10\njz short loc_1B6D\nloc_1AFB:\nmov r11, [r10+8]\nxor r9d, r9d\ntest r11, r11\njz short loc_1B30\nmov rdi, [r11+8]\ntest rdi, rdi\njz short loc_1B17\ncall get_height_part_0\nmov esi, eax\nloc_1B17:\nmov rdi, [r11+10h]\nxor eax, eax\ntest rdi, rdi\njz short loc_1B27\ncall get_height_part_0\nloc_1B27:\ncmp eax, esi\ncmovl eax, esi\nlea r9d, [rax+1]\nloc_1B30:\nmov r10, [r10+10h]\nxor esi, esi\ntest r10, r10\njz short loc_1B63\nmov rdi, [r10+8]\ntest rdi, rdi\njz short loc_1B4B\ncall get_height_part_0\nmov esi, eax\nloc_1B4B:\nmov rdi, [r10+10h]\nxor eax, eax\ntest rdi, rdi\njz short loc_1B5B\ncall get_height_part_0\nloc_1B5B:\ncmp eax, esi\ncmovge esi, eax\nadd esi, 1\nloc_1B63:\ncmp esi, r9d\ncmovl esi, r9d\nadd esi, 1\nloc_1B6D:\nmov r10, [rbx+10h]\nxor eax, eax\ntest r10, r10\njz short loc_1BF3\nmov r11, [r10+8]\nxor r9d, r9d\ntest r11, r11\njz short loc_1BB0\nmov rdi, [r11+8]\ntest rdi, rdi\njz short loc_1B95\ncall get_height_part_0\nmov r9d, eax\nloc_1B95:\nmov rdi, [r11+10h]\nxor eax, eax\ntest rdi, rdi\njz short loc_1BA5\ncall get_height_part_0\nloc_1BA5:\ncmp eax, r9d\ncmovl eax, r9d\nlea r9d, [rax+1]\nloc_1BB0:\nmov r11, [r10+10h]\nxor eax, eax\ntest r11, r11\njz short loc_1BE9\nmov rdi, [r11+8]\nxor r10d, r10d\ntest rdi, rdi\njz short loc_1BCF\ncall get_height_part_0\nmov r10d, eax\nloc_1BCF:\nmov rdi, [r11+10h]\nxor eax, eax\ntest rdi, rdi\njz short loc_1BDF\ncall get_height_part_0\nloc_1BDF:\ncmp eax, r10d\ncmovl eax, r10d\nadd eax, 1\nloc_1BE9:\ncmp eax, r9d\ncmovl eax, r9d\nadd eax, 1\nloc_1BF3:\ncmp eax, esi\ncmovl eax, esi\nadd eax, 1\nsub ecx, eax\nloc_1BFD:\nadd ecx, 1\ncmp ecx, 2\njbe short loc_1C30\nxor eax, eax\npop rbx\nretn\nloc_1C10:\nmov rbx, [rbx+10h]\ntest rbx, rbx\njz short loc_1C48\nmov r10, [rbx+8]\nxor ecx, ecx\nxor esi, esi\ntest r10, r10\njnz loc_1AFB\njmp loc_1B6D\nloc_1C30:\nmov rdi, r8\ncall func0\ntest al, al\njnz loc_19F8\npop rbx\nretn\nloc_1C48:\nmov eax, 1\npop rbx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, __int64 a3)\n{\n __int64 v4; // r8\n __int64 v5; // r9\n __int64 v6; // rsi\n __int64 v7; // rsi\n __int64 v8; // rcx\n __int64 v9; // rdi\n __int64 v10; // rdi\n int v11; // eax\n __int64 v12; // r9\n __int64 v13; // rsi\n __int64 v14; // rdi\n __int64 v15; // rdi\n int v16; // eax\n __int64 v17; // r9\n __int64 v18; // rcx\n __int64 v19; // r10\n __int64 v20; // rdi\n __int64 v21; // rdi\n int v22; // eax\n __int64 v23; // rdi\n int v24; // eax\n __int64 v25; // rcx\n __int64 v26; // r10\n __int64 height_part_0; // rsi\n __int64 v28; // r11\n int v29; // r9d\n __int64 v30; // rdi\n __int64 v31; // rdi\n int v32; // eax\n __int64 v33; // r10\n __int64 v34; // rsi\n __int64 v35; // rdi\n __int64 v36; // rdi\n int v37; // eax\n __int64 v38; // r10\n int v39; // eax\n __int64 v40; // r11\n int v41; // r9d\n __int64 v42; // rdi\n __int64 v43; // rdi\n int v44; // eax\n __int64 v45; // r11\n int v46; // eax\n __int64 v47; // rdi\n int v48; // r10d\n __int64 v49; // rdi\n int v50; // eax\n __int64 result; // rax\n\n while ( a1 )\n {\n v4 = *(_QWORD *)(a1 + 8);\n if ( !v4 )\n {\n a1 = *(_QWORD *)(a1 + 16);\n if ( !a1 )\n return 1LL;\n v26 = *(_QWORD *)(a1 + 8);\n v25 = 0LL;\n height_part_0 = 0LL;\n if ( v26 )\n {\nLABEL_41:\n v28 = *(_QWORD *)(v26 + 8);\n v29 = 0;\n if ( v28 )\n {\n v30 = *(_QWORD *)(v28 + 8);\n if ( v30 )\n height_part_0 = (unsigned int)get_height_part_0(v30, 0LL, a3, v25);\n v31 = *(_QWORD *)(v28 + 16);\n v32 = 0;\n if ( v31 )\n v32 = get_height_part_0(v31, height_part_0, a3, v25);\n if ( v32 < (int)height_part_0 )\n v32 = height_part_0;\n v29 = v32 + 1;\n }\n v33 = *(_QWORD *)(v26 + 16);\n v34 = 0LL;\n if ( v33 )\n {\n v35 = *(_QWORD *)(v33 + 8);\n if ( v35 )\n v34 = (unsigned int)get_height_part_0(v35, 0LL, a3, v25);\n v36 = *(_QWORD *)(v33 + 16);\n v37 = 0;\n if ( v36 )\n v37 = get_height_part_0(v36, v34, a3, v25);\n if ( v37 >= (int)v34 )\n LODWORD(v34) = v37;\n LODWORD(v34) = v34 + 1;\n }\n if ( (int)v34 < v29 )\n LODWORD(v34) = v29;\n height_part_0 = (unsigned int)(v34 + 1);\n }\nLABEL_60:\n v38 = *(_QWORD *)(a1 + 16);\n v39 = 0;\n if ( v38 )\n {\n v40 = *(_QWORD *)(v38 + 8);\n v41 = 0;\n if ( v40 )\n {\n v42 = *(_QWORD *)(v40 + 8);\n if ( v42 )\n v41 = get_height_part_0(v42, height_part_0, a3, v25);\n v43 = *(_QWORD *)(v40 + 16);\n v44 = 0;\n if ( v43 )\n v44 = get_height_part_0(v43, height_part_0, a3, v25);\n if ( v44 < v41 )\n v44 = v41;\n v41 = v44 + 1;\n }\n v45 = *(_QWORD *)(v38 + 16);\n v46 = 0;\n if ( v45 )\n {\n v47 = *(_QWORD *)(v45 + 8);\n v48 = 0;\n if ( v47 )\n v48 = get_height_part_0(v47, height_part_0, a3, v25);\n v49 = *(_QWORD *)(v45 + 16);\n v50 = 0;\n if ( v49 )\n v50 = get_height_part_0(v49, height_part_0, a3, v25);\n if ( v50 < v48 )\n v50 = v48;\n v46 = v50 + 1;\n }\n if ( v46 < v41 )\n v46 = v41;\n v39 = v46 + 1;\n }\n if ( v39 < (int)height_part_0 )\n v39 = height_part_0;\n LODWORD(v25) = v25 - (v39 + 1);\n goto LABEL_83;\n }\n v5 = *(_QWORD *)(v4 + 8);\n v6 = 0LL;\n if ( v5 )\n {\n v7 = *(_QWORD *)(v5 + 8);\n v8 = 0LL;\n if ( v7 )\n {\n v9 = *(_QWORD *)(v7 + 8);\n if ( v9 )\n v8 = (unsigned int)get_height_part_0(v9, v7, a3, 0LL);\n v10 = *(_QWORD *)(v7 + 16);\n v11 = 0;\n if ( v10 )\n v11 = get_height_part_0(v10, v7, a3, v8);\n if ( v11 < (int)v8 )\n v11 = v8;\n v8 = (unsigned int)(v11 + 1);\n }\n v12 = *(_QWORD *)(v5 + 16);\n v13 = 0LL;\n if ( v12 )\n {\n v14 = *(_QWORD *)(v12 + 8);\n if ( v14 )\n v13 = (unsigned int)get_height_part_0(v14, 0LL, a3, v8);\n v15 = *(_QWORD *)(v12 + 16);\n v16 = 0;\n if ( v15 )\n v16 = get_height_part_0(v15, v13, a3, v8);\n if ( v16 >= (int)v13 )\n LODWORD(v13) = v16;\n LODWORD(v13) = v13 + 1;\n }\n if ( (int)v13 < (int)v8 )\n LODWORD(v13) = v8;\n v6 = (unsigned int)(v13 + 1);\n }\n v17 = *(_QWORD *)(v4 + 16);\n v18 = 0LL;\n if ( v17 )\n {\n v19 = *(_QWORD *)(v17 + 8);\n if ( v19 )\n {\n v20 = *(_QWORD *)(v19 + 8);\n if ( v20 )\n v18 = (unsigned int)get_height_part_0(v20, v6, a3, 0LL);\n v21 = *(_QWORD *)(v19 + 16);\n v22 = 0;\n if ( v21 )\n v22 = get_height_part_0(v21, v6, a3, v18);\n if ( v22 < (int)v18 )\n v22 = v18;\n v18 = (unsigned int)(v22 + 1);\n }\n v23 = *(_QWORD *)(v17 + 16);\n v24 = 0;\n if ( v23 )\n v24 = get_height_part_0(v23, v6, a3, v18);\n if ( v24 >= (int)v18 )\n LODWORD(v18) = v24;\n LODWORD(v18) = v18 + 1;\n }\n a1 = *(_QWORD *)(a1 + 16);\n if ( (int)v18 < (int)v6 )\n LODWORD(v18) = v6;\n v25 = (unsigned int)(v18 + 1);\n if ( a1 )\n {\n v26 = *(_QWORD *)(a1 + 8);\n height_part_0 = 0LL;\n if ( v26 )\n goto LABEL_41;\n goto LABEL_60;\n }\nLABEL_83:\n if ( (unsigned int)(v25 + 1) > 2 )\n return 0LL;\n result = func0(v4);\n if ( !(_BYTE)result )\n return result;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_19F0:\nendbr64\npush rbx\nmov rbx, rdi\nloc_19F8:\ntest rbx, rbx\njz loc_1C48\nmov r8, [rbx+8]\ntest r8, r8\njz loc_1C10\nmov r9, [r8+8]\nxor esi, esi\ntest r9, r9\njz short loc_1A87\nmov rsi, [r9+8]\nxor ecx, ecx\ntest rsi, rsi\njz short loc_1A4C\nmov rdi, [rsi+8]\ntest rdi, rdi\njz short loc_1A34\ncall sub_13A0\nmov ecx, eax\nloc_1A34:\nmov rdi, [rsi+10h]\nxor eax, eax\ntest rdi, rdi\njz short loc_1A44\ncall sub_13A0\nloc_1A44:\ncmp eax, ecx\ncmovl eax, ecx\nlea ecx, [rax+1]\nloc_1A4C:\nmov r9, [r9+10h]\nxor esi, esi\ntest r9, r9\njz short loc_1A7F\nmov rdi, [r9+8]\ntest rdi, rdi\njz short loc_1A67\ncall sub_13A0\nmov esi, eax\nloc_1A67:\nmov rdi, [r9+10h]\nxor eax, eax\ntest rdi, rdi\njz short loc_1A77\ncall sub_13A0\nloc_1A77:\ncmp eax, esi\ncmovge esi, eax\nadd esi, 1\nloc_1A7F:\ncmp esi, ecx\ncmovl esi, ecx\nadd esi, 1\nloc_1A87:\nmov r9, [r8+10h]\nxor ecx, ecx\ntest r9, r9\njz short loc_1ADB\nmov r10, [r9+8]\ntest r10, r10\njz short loc_1AC3\nmov rdi, [r10+8]\ntest rdi, rdi\njz short loc_1AAB\ncall sub_13A0\nmov ecx, eax\nloc_1AAB:\nmov rdi, [r10+10h]\nxor eax, eax\ntest rdi, rdi\njz short loc_1ABB\ncall sub_13A0\nloc_1ABB:\ncmp eax, ecx\ncmovl eax, ecx\nlea ecx, [rax+1]\nloc_1AC3:\nmov rdi, [r9+10h]\nxor eax, eax\ntest rdi, rdi\njz short loc_1AD3\ncall sub_13A0\nloc_1AD3:\ncmp eax, ecx\ncmovge ecx, eax\nadd ecx, 1\nloc_1ADB:\ncmp ecx, esi\nmov rbx, [rbx+10h]\ncmovl ecx, esi\nadd ecx, 1\ntest rbx, rbx\njz loc_1BFD\nmov r10, [rbx+8]\nxor esi, esi\ntest r10, r10\njz short loc_1B6D\nloc_1AFB:\nmov r11, [r10+8]\nxor r9d, r9d\ntest r11, r11\njz short loc_1B30\nmov rdi, [r11+8]\ntest rdi, rdi\njz short loc_1B17\ncall sub_13A0\nmov esi, eax\nloc_1B17:\nmov rdi, [r11+10h]\nxor eax, eax\ntest rdi, rdi\njz short loc_1B27\ncall sub_13A0\nloc_1B27:\ncmp eax, esi\ncmovl eax, esi\nlea r9d, [rax+1]\nloc_1B30:\nmov r10, [r10+10h]\nxor esi, esi\ntest r10, r10\njz short loc_1B63\nmov rdi, [r10+8]\ntest rdi, rdi\njz short loc_1B4B\ncall sub_13A0\nmov esi, eax\nloc_1B4B:\nmov rdi, [r10+10h]\nxor eax, eax\ntest rdi, rdi\njz short loc_1B5B\ncall sub_13A0\nloc_1B5B:\ncmp eax, esi\ncmovge esi, eax\nadd esi, 1\nloc_1B63:\ncmp esi, r9d\ncmovl esi, r9d\nadd esi, 1\nloc_1B6D:\nmov r10, [rbx+10h]\nxor eax, eax\ntest r10, r10\njz short loc_1BF3\nmov r11, [r10+8]\nxor r9d, r9d\ntest r11, r11\njz short loc_1BB0\nmov rdi, [r11+8]\ntest rdi, rdi\njz short loc_1B95\ncall sub_13A0\nmov r9d, eax\nloc_1B95:\nmov rdi, [r11+10h]\nxor eax, eax\ntest rdi, rdi\njz short loc_1BA5\ncall sub_13A0\nloc_1BA5:\ncmp eax, r9d\ncmovl eax, r9d\nlea r9d, [rax+1]\nloc_1BB0:\nmov r11, [r10+10h]\nxor eax, eax\ntest r11, r11\njz short loc_1BE9\nmov rdi, [r11+8]\nxor r10d, r10d\ntest rdi, rdi\njz short loc_1BCF\ncall sub_13A0\nmov r10d, eax\nloc_1BCF:\nmov rdi, [r11+10h]\nxor eax, eax\ntest rdi, rdi\njz short loc_1BDF\ncall sub_13A0\nloc_1BDF:\ncmp eax, r10d\ncmovl eax, r10d\nadd eax, 1\nloc_1BE9:\ncmp eax, r9d\ncmovl eax, r9d\nadd eax, 1\nloc_1BF3:\ncmp eax, esi\ncmovl eax, esi\nadd eax, 1\nsub ecx, eax\nloc_1BFD:\nadd ecx, 1\ncmp ecx, 2\njbe short loc_1C30\nxor eax, eax\npop rbx\nretn\nloc_1C10:\nmov rbx, [rbx+10h]\ntest rbx, rbx\njz short loc_1C48\nmov r10, [rbx+8]\nxor ecx, ecx\nxor esi, esi\ntest r10, r10\njnz loc_1AFB\njmp loc_1B6D\nloc_1C30:\nmov rdi, r8\ncall sub_19F0\ntest al, al\njnz loc_19F8\npop rbx\nretn\nloc_1C48:\nmov eax, 1\npop rbx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_19F0(__int64 a1, __int64 a2, __int64 a3)\n{\n __int64 v4; // r8\n __int64 v5; // r9\n __int64 v6; // rsi\n __int64 v7; // rsi\n __int64 v8; // rcx\n __int64 v9; // rdi\n __int64 v10; // rdi\n int v11; // eax\n __int64 v12; // r9\n __int64 v13; // rsi\n __int64 v14; // rdi\n __int64 v15; // rdi\n int v16; // eax\n __int64 v17; // r9\n __int64 v18; // rcx\n __int64 v19; // r10\n __int64 v20; // rdi\n __int64 v21; // rdi\n int v22; // eax\n __int64 v23; // rdi\n int v24; // eax\n __int64 v25; // rcx\n __int64 v26; // r10\n __int64 v27; // rsi\n __int64 v28; // r11\n int v29; // r9d\n __int64 v30; // rdi\n __int64 v31; // rdi\n int v32; // eax\n __int64 v33; // r10\n __int64 v34; // rsi\n __int64 v35; // rdi\n __int64 v36; // rdi\n int v37; // eax\n __int64 v38; // r10\n int v39; // eax\n __int64 v40; // r11\n int v41; // r9d\n __int64 v42; // rdi\n __int64 v43; // rdi\n int v44; // eax\n __int64 v45; // r11\n int v46; // eax\n __int64 v47; // rdi\n int v48; // r10d\n __int64 v49; // rdi\n int v50; // eax\n __int64 result; // rax\n\n while ( a1 )\n {\n v4 = *(_QWORD *)(a1 + 8);\n if ( !v4 )\n {\n a1 = *(_QWORD *)(a1 + 16);\n if ( !a1 )\n return 1LL;\n v26 = *(_QWORD *)(a1 + 8);\n v25 = 0LL;\n v27 = 0LL;\n if ( v26 )\n {\nLABEL_41:\n v28 = *(_QWORD *)(v26 + 8);\n v29 = 0;\n if ( v28 )\n {\n v30 = *(_QWORD *)(v28 + 8);\n if ( v30 )\n v27 = (unsigned int)sub_13A0(v30, 0LL, a3, v25);\n v31 = *(_QWORD *)(v28 + 16);\n v32 = 0;\n if ( v31 )\n v32 = sub_13A0(v31, v27, a3, v25);\n if ( v32 < (int)v27 )\n v32 = v27;\n v29 = v32 + 1;\n }\n v33 = *(_QWORD *)(v26 + 16);\n v34 = 0LL;\n if ( v33 )\n {\n v35 = *(_QWORD *)(v33 + 8);\n if ( v35 )\n v34 = (unsigned int)sub_13A0(v35, 0LL, a3, v25);\n v36 = *(_QWORD *)(v33 + 16);\n v37 = 0;\n if ( v36 )\n v37 = sub_13A0(v36, v34, a3, v25);\n if ( v37 >= (int)v34 )\n LODWORD(v34) = v37;\n LODWORD(v34) = v34 + 1;\n }\n if ( (int)v34 < v29 )\n LODWORD(v34) = v29;\n v27 = (unsigned int)(v34 + 1);\n }\nLABEL_60:\n v38 = *(_QWORD *)(a1 + 16);\n v39 = 0;\n if ( v38 )\n {\n v40 = *(_QWORD *)(v38 + 8);\n v41 = 0;\n if ( v40 )\n {\n v42 = *(_QWORD *)(v40 + 8);\n if ( v42 )\n v41 = sub_13A0(v42, v27, a3, v25);\n v43 = *(_QWORD *)(v40 + 16);\n v44 = 0;\n if ( v43 )\n v44 = sub_13A0(v43, v27, a3, v25);\n if ( v44 < v41 )\n v44 = v41;\n v41 = v44 + 1;\n }\n v45 = *(_QWORD *)(v38 + 16);\n v46 = 0;\n if ( v45 )\n {\n v47 = *(_QWORD *)(v45 + 8);\n v48 = 0;\n if ( v47 )\n v48 = sub_13A0(v47, v27, a3, v25);\n v49 = *(_QWORD *)(v45 + 16);\n v50 = 0;\n if ( v49 )\n v50 = sub_13A0(v49, v27, a3, v25);\n if ( v50 < v48 )\n v50 = v48;\n v46 = v50 + 1;\n }\n if ( v46 < v41 )\n v46 = v41;\n v39 = v46 + 1;\n }\n if ( v39 < (int)v27 )\n v39 = v27;\n LODWORD(v25) = v25 - (v39 + 1);\n goto LABEL_83;\n }\n v5 = *(_QWORD *)(v4 + 8);\n v6 = 0LL;\n if ( v5 )\n {\n v7 = *(_QWORD *)(v5 + 8);\n v8 = 0LL;\n if ( v7 )\n {\n v9 = *(_QWORD *)(v7 + 8);\n if ( v9 )\n v8 = (unsigned int)sub_13A0(v9, v7, a3, 0LL);\n v10 = *(_QWORD *)(v7 + 16);\n v11 = 0;\n if ( v10 )\n v11 = sub_13A0(v10, v7, a3, v8);\n if ( v11 < (int)v8 )\n v11 = v8;\n v8 = (unsigned int)(v11 + 1);\n }\n v12 = *(_QWORD *)(v5 + 16);\n v13 = 0LL;\n if ( v12 )\n {\n v14 = *(_QWORD *)(v12 + 8);\n if ( v14 )\n v13 = (unsigned int)sub_13A0(v14, 0LL, a3, v8);\n v15 = *(_QWORD *)(v12 + 16);\n v16 = 0;\n if ( v15 )\n v16 = sub_13A0(v15, v13, a3, v8);\n if ( v16 >= (int)v13 )\n LODWORD(v13) = v16;\n LODWORD(v13) = v13 + 1;\n }\n if ( (int)v13 < (int)v8 )\n LODWORD(v13) = v8;\n v6 = (unsigned int)(v13 + 1);\n }\n v17 = *(_QWORD *)(v4 + 16);\n v18 = 0LL;\n if ( v17 )\n {\n v19 = *(_QWORD *)(v17 + 8);\n if ( v19 )\n {\n v20 = *(_QWORD *)(v19 + 8);\n if ( v20 )\n v18 = (unsigned int)sub_13A0(v20, v6, a3, 0LL);\n v21 = *(_QWORD *)(v19 + 16);\n v22 = 0;\n if ( v21 )\n v22 = sub_13A0(v21, v6, a3, v18);\n if ( v22 < (int)v18 )\n v22 = v18;\n v18 = (unsigned int)(v22 + 1);\n }\n v23 = *(_QWORD *)(v17 + 16);\n v24 = 0;\n if ( v23 )\n v24 = sub_13A0(v23, v6, a3, v18);\n if ( v24 >= (int)v18 )\n LODWORD(v18) = v24;\n LODWORD(v18) = v18 + 1;\n }\n a1 = *(_QWORD *)(a1 + 16);\n if ( (int)v18 < (int)v6 )\n LODWORD(v18) = v6;\n v25 = (unsigned int)(v18 + 1);\n if ( a1 )\n {\n v26 = *(_QWORD *)(a1 + 8);\n v27 = 0LL;\n if ( v26 )\n goto LABEL_41;\n goto LABEL_60;\n }\nLABEL_83:\n if ( (unsigned int)(v25 + 1) > 2 )\n return 0LL;\n result = sub_19F0(v4);\n if ( !(_BYTE)result )\n return result;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_19F0(long long a1, long long a2, long long a3) {\n long long v4;\n long long v5;\n long long v6;\n long long v7;\n long long v8;\n long long v9;\n long long v10;\n int v11;\n long long v12;\n long long v13;\n long long v14;\n long long v15;\n int v16;\n long long v17;\n long long v18;\n long long v19;\n long long v20;\n long long v21;\n int v22;\n long long v23;\n int v24;\n long long v25;\n long long v26;\n long long v27;\n long long v28;\n int v29;\n long long v30;\n long long v31;\n int v32;\n long long v33;\n long long v34;\n long long v35;\n long long v36;\n int v37;\n long long v38;\n int v39;\n long long v40;\n int v41;\n long long v42;\n long long v43;\n int v44;\n long long v45;\n int v46;\n long long v47;\n int v48;\n long long v49;\n int v50;\n long long result;\n while (a1) {\n v4 = *(uint64_t *)(a1 + 8);\n if (!v4) {\n a1 = *(uint64_t *)(a1 + 16);\n if (!a1) return 1LL;\n v26 = *(uint64_t *)(a1 + 8);\n v25 = 0LL;\n v27 = 0LL;\n if (v26) {\n LABEL_41:\n v28 = *(uint64_t *)(v26 + 8);\n v29 = 0;\n if (v28) {\n v30 = *(uint64_t *)(v28 + 8);\n if (v30) v27 = (unsigned int)sub_13A0(v30, 0LL, a3, v25);\n v31 = *(uint64_t *)(v28 + 16);\n v32 = 0;\n if (v31) v32 = sub_13A0(v31, v27, a3, v25);\n if (v32 < (int)v27) v32 = v27;\n v29 = v32 + 1;\n }\n v33 = *(uint64_t *)(v26 + 16);\n v34 = 0LL;\n if (v33) {\n v35 = *(uint64_t *)(v33 + 8);\n if (v35) v34 = (unsigned int)sub_13A0(v35, 0LL, a3, v25);\n v36 = *(uint64_t *)(v33 + 16);\n v37 = 0;\n if (v36) v37 = sub_13A0(v36, v34, a3, v25);\n if (v37 >= (int)v34) LODWORD(v34) = v37;\n LODWORD(v34) = v34 + 1;\n }\n if ((int)v34 < v29) LODWORD(v34) = v29;\n v27 = (unsigned int)(v34 + 1);\n }\n LABEL_60:\n v38 = *(uint64_t *)(a1 + 16);\n v39 = 0;\n if (v38) {\n v40 = *(uint64_t *)(v38 + 8);\n v41 = 0;\n if (v40) {\n v42 = *(uint64_t *)(v40 + 8);\n if (v42) v41 = sub_13A0(v42, v27, a3, v25);\n v43 = *(uint64_t *)(v40 + 16);\n v44 = 0;\n if (v43) v44 = sub_13A0(v43, v27, a3, v25);\n if (v44 < v41) v44 = v41;\n v41 = v44 + 1;\n }\n v45 = *(uint64_t *)(v38 + 16);\n v46 = 0;\n if (v45) {\n v47 = *(uint64_t *)(v45 + 8);\n v48 = 0;\n if (v47) v48 = sub_13A0(v47, v27, a3, v25);\n v49 = *(uint64_t *)(v45 + 16);\n v50 = 0;\n if (v49) v50 = sub_13A0(v49, v27, a3, v25);\n if (v50 < v48) v50 = v48;\n v46 = v50 + 1;\n }\n if (v46 < v41) v46 = v41;\n v39 = v46 + 1;\n }\n if (v39 < (int)v27) v39 = v27;\n LODWORD(v25) = v25 - (v39 + 1);\n goto LABEL_83;\n }\n v5 = *(uint64_t *)(v4 + 8);\n v6 = 0LL;\n if (v5) {\n v7 = *(uint64_t *)(v5 + 8);\n v8 = 0LL;\n if (v7) {\n v9 = *(uint64_t *)(v7 + 8);\n if (v9) v8 = (unsigned int)sub_13A0(v9, v7, a3, 0LL);\n v10 = *(uint64_t *)(v7 + 16);\n v11 = 0;\n if (v10) v11 = sub_13A0(v10, v7, a3, v8);\n if (v11 < (int)v8) v11 = v8;\n v8 = (unsigned int)(v11 + 1);\n }\n v12 = *(uint64_t *)(v5 + 16);\n v13 = 0LL;\n if (v12) {\n v14 = *(uint64_t *)(v12 + 8);\n if (v14) v13 = (unsigned int)sub_13A0(v14, 0LL, a3, v8);\n v15 = *(uint64_t *)(v12 + 16);\n v16 = 0;\n if (v15) v16 = sub_13A0(v15, v13, a3, v8);\n if (v16 >= (int)v13) LODWORD(v13) = v16;\n LODWORD(v13) = v13 + 1;\n }\n if ((int)v13 < (int)v8) LODWORD(v13) = v8;\n v6 = (unsigned int)(v13 + 1);\n }\n v17 = *(uint64_t *)(v4 + 16);\n v18 = 0LL;\n if (v17) {\n v19 = *(uint64_t *)(v17 + 8);\n if (v19) {\n v20 = *(uint64_t *)(v19 + 8);\n if (v20) v18 = (unsigned int)sub_13A0(v20, v6, a3, 0LL);\n v21 = *(uint64_t *)(v19 + 16);\n v22 = 0;\n if (v21) v22 = sub_13A0(v21, v6, a3, v18);\n if (v22 < (int)v18) v22 = v18;\n v18 = (unsigned int)(v22 + 1);\n }\n v23 = *(uint64_t *)(v17 + 16);\n v24 = 0;\n if (v23) v24 = sub_13A0(v23, v6, a3, v18);\n if (v24 >= (int)v18) LODWORD(v18) = v24;\n LODWORD(v18) = v18 + 1;\n }\n a1 = *(uint64_t *)(a1 + 16);\n if ((int)v18 < (int)v6) LODWORD(v18) = v6;\n v25 = (unsigned int)(v18 + 1);\n if (a1) {\n v26 = *(uint64_t *)(a1 + 8);\n v27 = 0LL;\n if (v26) goto LABEL_41;\n goto LABEL_60;\n }\n LABEL_83:\n if ((unsigned int)(v25 + 1) > 2) return 0LL;\n result = sub_19F0(v4);\n if (!(uint8_t)result) return result;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, long long a3) {\n long long v4;\n long long v5;\n long long v6;\n long long v7;\n long long v8;\n long long v9;\n long long v10;\n int v11;\n long long v12;\n long long v13;\n long long v14;\n long long v15;\n int v16;\n long long v17;\n long long v18;\n long long v19;\n long long v20;\n long long v21;\n int v22;\n long long v23;\n int v24;\n long long v25;\n long long v26;\n long long height_part_0;\n long long v28;\n int v29;\n long long v30;\n long long v31;\n int v32;\n long long v33;\n long long v34;\n long long v35;\n long long v36;\n int v37;\n long long v38;\n int v39;\n long long v40;\n int v41;\n long long v42;\n long long v43;\n int v44;\n long long v45;\n int v46;\n long long v47;\n int v48;\n long long v49;\n int v50;\n long long result;\n while (a1) {\n v4 = *(uint64_t *)(a1 + 8);\n if (!v4) {\n a1 = *(uint64_t *)(a1 + 16);\n if (!a1) return 1LL;\n v26 = *(uint64_t *)(a1 + 8);\n v25 = 0LL;\n height_part_0 = 0LL;\n if (v26) {\n LABEL_41:\n v28 = *(uint64_t *)(v26 + 8);\n v29 = 0;\n if (v28) {\n v30 = *(uint64_t *)(v28 + 8);\n if (v30)\n height_part_0 = (unsigned int)get_height_part_0(v30, 0LL, a3, v25);\n v31 = *(uint64_t *)(v28 + 16);\n v32 = 0;\n if (v31) v32 = get_height_part_0(v31, height_part_0, a3, v25);\n if (v32 < (int)height_part_0) v32 = height_part_0;\n v29 = v32 + 1;\n }\n v33 = *(uint64_t *)(v26 + 16);\n v34 = 0LL;\n if (v33) {\n v35 = *(uint64_t *)(v33 + 8);\n if (v35) v34 = (unsigned int)get_height_part_0(v35, 0LL, a3, v25);\n v36 = *(uint64_t *)(v33 + 16);\n v37 = 0;\n if (v36) v37 = get_height_part_0(v36, v34, a3, v25);\n if (v37 >= (int)v34) LODWORD(v34) = v37;\n LODWORD(v34) = v34 + 1;\n }\n if ((int)v34 < v29) LODWORD(v34) = v29;\n height_part_0 = (unsigned int)(v34 + 1);\n }\n LABEL_60:\n v38 = *(uint64_t *)(a1 + 16);\n v39 = 0;\n if (v38) {\n v40 = *(uint64_t *)(v38 + 8);\n v41 = 0;\n if (v40) {\n v42 = *(uint64_t *)(v40 + 8);\n if (v42) v41 = get_height_part_0(v42, height_part_0, a3, v25);\n v43 = *(uint64_t *)(v40 + 16);\n v44 = 0;\n if (v43) v44 = get_height_part_0(v43, height_part_0, a3, v25);\n if (v44 < v41) v44 = v41;\n v41 = v44 + 1;\n }\n v45 = *(uint64_t *)(v38 + 16);\n v46 = 0;\n if (v45) {\n v47 = *(uint64_t *)(v45 + 8);\n v48 = 0;\n if (v47) v48 = get_height_part_0(v47, height_part_0, a3, v25);\n v49 = *(uint64_t *)(v45 + 16);\n v50 = 0;\n if (v49) v50 = get_height_part_0(v49, height_part_0, a3, v25);\n if (v50 < v48) v50 = v48;\n v46 = v50 + 1;\n }\n if (v46 < v41) v46 = v41;\n v39 = v46 + 1;\n }\n if (v39 < (int)height_part_0) v39 = height_part_0;\n LODWORD(v25) = v25 - (v39 + 1);\n goto LABEL_83;\n }\n v5 = *(uint64_t *)(v4 + 8);\n v6 = 0LL;\n if (v5) {\n v7 = *(uint64_t *)(v5 + 8);\n v8 = 0LL;\n if (v7) {\n v9 = *(uint64_t *)(v7 + 8);\n if (v9) v8 = (unsigned int)get_height_part_0(v9, v7, a3, 0LL);\n v10 = *(uint64_t *)(v7 + 16);\n v11 = 0;\n if (v10) v11 = get_height_part_0(v10, v7, a3, v8);\n if (v11 < (int)v8) v11 = v8;\n v8 = (unsigned int)(v11 + 1);\n }\n v12 = *(uint64_t *)(v5 + 16);\n v13 = 0LL;\n if (v12) {\n v14 = *(uint64_t *)(v12 + 8);\n if (v14) v13 = (unsigned int)get_height_part_0(v14, 0LL, a3, v8);\n v15 = *(uint64_t *)(v12 + 16);\n v16 = 0;\n if (v15) v16 = get_height_part_0(v15, v13, a3, v8);\n if (v16 >= (int)v13) LODWORD(v13) = v16;\n LODWORD(v13) = v13 + 1;\n }\n if ((int)v13 < (int)v8) LODWORD(v13) = v8;\n v6 = (unsigned int)(v13 + 1);\n }\n v17 = *(uint64_t *)(v4 + 16);\n v18 = 0LL;\n if (v17) {\n v19 = *(uint64_t *)(v17 + 8);\n if (v19) {\n v20 = *(uint64_t *)(v19 + 8);\n if (v20) v18 = (unsigned int)get_height_part_0(v20, v6, a3, 0LL);\n v21 = *(uint64_t *)(v19 + 16);\n v22 = 0;\n if (v21) v22 = get_height_part_0(v21, v6, a3, v18);\n if (v22 < (int)v18) v22 = v18;\n v18 = (unsigned int)(v22 + 1);\n }\n v23 = *(uint64_t *)(v17 + 16);\n v24 = 0;\n if (v23) v24 = get_height_part_0(v23, v6, a3, v18);\n if (v24 >= (int)v18) LODWORD(v18) = v24;\n LODWORD(v18) = v18 + 1;\n }\n a1 = *(uint64_t *)(a1 + 16);\n if ((int)v18 < (int)v6) LODWORD(v18) = v6;\n v25 = (unsigned int)(v18 + 1);\n if (a1) {\n v26 = *(uint64_t *)(a1 + 8);\n height_part_0 = 0LL;\n if (v26) goto LABEL_41;\n goto LABEL_60;\n }\n LABEL_83:\n if ((unsigned int)(v25 + 1) > 2) return 0LL;\n result = func0(v4);\n if (!(uint8_t)result) return result;\n }\n return 1LL;\n}" + }, + { + "index": 368, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int a;\n\n int b;\n\n} repeat_tuples_result;\n\n\n\n", + "func": "repeat_tuples_result* func0(repeat_tuples_result test_tup, int N) {\n repeat_tuples_result* res = malloc(N * sizeof(repeat_tuples_result));\n for (int i = 0; i < N; i++) {\n res[i] = test_tup;\n }\n return res;\n}", + "test": "int main() {\n\n // First test\n\n repeat_tuples_result t1 = {1, 3};\n\n int N1 = 4;\n\n repeat_tuples_result* res1 = func0(t1, N1);\n\n repeat_tuples_result expected1[4] = { {1,3}, {1,3}, {1,3}, {1,3} };\n\n for(int i = 0; i < N1; i++) {\n\n assert(res1[i].a == expected1[i].a && res1[i].b == expected1[i].b);\n\n }\n\n free(res1);\n\n\n\n // Second test\n\n repeat_tuples_result t2 = {1, 2};\n\n int N2 = 3;\n\n repeat_tuples_result* res2 = func0(t2, N2);\n\n repeat_tuples_result expected2[3] = { {1,2}, {1,2}, {1,2} };\n\n for(int i = 0; i < N2; i++) {\n\n assert(res2[i].a == expected2[i].a && res2[i].b == expected2[i].b);\n\n }\n\n free(res2);\n\n\n\n // Third test\n\n repeat_tuples_result t3 = {3, 4};\n\n int N3 = 5;\n\n repeat_tuples_result* res3 = func0(t3, N3);\n\n repeat_tuples_result expected3[5] = { {3,4}, {3,4}, {3,4}, {3,4}, {3,4} };\n\n for(int i = 0; i < N3; i++) {\n\n assert(res3[i].a == expected3[i].a && res3[i].b == expected3[i].b);\n\n }\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov -0x1c(%rbp),%eax\ncltq\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 11f9 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov -0x18(%rbp),%rax\nmov %rax,(%rdx)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11da \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp short loc_11F9\nloc_11DA:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov rax, [rbp+var_18]\nmov [rdx], rax\nadd [rbp+var_C], 1\nloc_11F9:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_11DA\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+14h] [rbp-Ch]\n _QWORD *v4; // [rsp+18h] [rbp-8h]\n\n v4 = malloc(8LL * a2);\n for ( i = 0; i < a2; ++i )\n v4[i] = a1;\n return v4;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp short loc_11F9\nloc_11DA:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov rax, [rbp+var_18]\nmov [rdx], rax\nadd [rbp+var_C], 1\nloc_11F9:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_11DA\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11A9(__int64 a1, int a2)\n{\n int i; // [rsp+14h] [rbp-Ch]\n _QWORD *v4; // [rsp+18h] [rbp-8h]\n\n v4 = malloc(8LL * a2);\n for ( i = 0; i < a2; ++i )\n v4[i] = a1;\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11A9(long long a1, int a2) {\n int i;\n uint64_t *v4;\n v4 = malloc(8LL * a2);\n for (i = 0; i < a2; ++i) v4[i] = a1;\n return v4;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, int a2) {\n int i;\n uint64_t *v4;\n v4 = malloc(8LL * a2);\n for (i = 0; i < a2; ++i) v4[i] = a1;\n return v4;\n}" + }, + { + "index": 368, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int a;\n\n int b;\n\n} repeat_tuples_result;\n\n\n\n", + "func": "repeat_tuples_result* func0(repeat_tuples_result test_tup, int N) {\n repeat_tuples_result* res = malloc(N * sizeof(repeat_tuples_result));\n for (int i = 0; i < N; i++) {\n res[i] = test_tup;\n }\n return res;\n}", + "test": "int main() {\n\n // First test\n\n repeat_tuples_result t1 = {1, 3};\n\n int N1 = 4;\n\n repeat_tuples_result* res1 = func0(t1, N1);\n\n repeat_tuples_result expected1[4] = { {1,3}, {1,3}, {1,3}, {1,3} };\n\n for(int i = 0; i < N1; i++) {\n\n assert(res1[i].a == expected1[i].a && res1[i].b == expected1[i].b);\n\n }\n\n free(res1);\n\n\n\n // Second test\n\n repeat_tuples_result t2 = {1, 2};\n\n int N2 = 3;\n\n repeat_tuples_result* res2 = func0(t2, N2);\n\n repeat_tuples_result expected2[3] = { {1,2}, {1,2}, {1,2} };\n\n for(int i = 0; i < N2; i++) {\n\n assert(res2[i].a == expected2[i].a && res2[i].b == expected2[i].b);\n\n }\n\n free(res2);\n\n\n\n // Third test\n\n repeat_tuples_result t3 = {3, 4};\n\n int N3 = 5;\n\n repeat_tuples_result* res3 = func0(t3, N3);\n\n repeat_tuples_result expected3[5] = { {3,4}, {3,4}, {3,4}, {3,4}, {3,4} };\n\n for(int i = 0; i < N3; i++) {\n\n assert(res3[i].a == expected3[i].a && res3[i].b == expected3[i].b);\n\n }\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbx\nmov %esi,%ebp\nmovslq %esi,%rdi\nshl $0x3,%rdi\ncallq 10b0 \ntest %ebp,%ebp\njle 11df \nmov %rax,%rdx\nlea -0x1(%rbp),%ecx\nlea 0x8(%rax,%rcx,8),%rcx\nmov %rbx,(%rdx)\nadd $0x8,%rdx\ncmp %rcx,%rdx\njne 11d3 \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbp, rdi\nmov r12d, esi\nmovsxd rcx, esi\nlea rbx, ds:0[rcx*8]\nmov rdi, rbx; size\ncall _malloc\ntest r12d, r12d\njle short loc_11E2\nmov rdx, rax\nlea rcx, [rbx+rax]\nloc_11D6:\nmov [rdx], rbp\nadd rdx, 8\ncmp rdx, rcx\njnz short loc_11D6\nloc_11E2:\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, int a2)\n{\n _QWORD *result; // rax\n _QWORD *v3; // rdx\n\n result = malloc(8LL * a2);\n if ( a2 > 0 )\n {\n v3 = result;\n do\n *v3++ = a1;\n while ( v3 != &result[a2] );\n }\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbp, rdi\nmov r12d, esi\nmovsxd rcx, esi\nlea rbx, ds:0[rcx*8]\nmov rdi, rbx; size\ncall _malloc\ntest r12d, r12d\njle short loc_11E2\nmov rdx, rax\nlea rcx, [rbx+rax]\nloc_11D6:\nmov [rdx], rbp\nadd rdx, 8\ncmp rdx, rcx\njnz short loc_11D6\nloc_11E2:\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11A9(__int64 a1, int a2)\n{\n _QWORD *result; // rax\n _QWORD *v3; // rdx\n\n result = malloc(8LL * a2);\n if ( a2 > 0 )\n {\n v3 = result;\n do\n *v3++ = a1;\n while ( v3 != &result[a2] );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11A9(long long a1, int a2) {\n uint64_t *result;\n uint64_t *v3;\n result = malloc(8LL * a2);\n if (a2 > 0) {\n v3 = result;\n do\n *v3++ = a1;\n while (v3 != &result[a2]);\n }\n return result;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, int a2) {\n uint64_t *result;\n uint64_t *v3;\n result = malloc(8LL * a2);\n if (a2 > 0) {\n v3 = result;\n do\n *v3++ = a1;\n while (v3 != &result[a2]);\n }\n return result;\n}" + }, + { + "index": 368, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int a;\n\n int b;\n\n} repeat_tuples_result;\n\n\n\n", + "func": "repeat_tuples_result* func0(repeat_tuples_result test_tup, int N) {\n repeat_tuples_result* res = malloc(N * sizeof(repeat_tuples_result));\n for (int i = 0; i < N; i++) {\n res[i] = test_tup;\n }\n return res;\n}", + "test": "int main() {\n\n // First test\n\n repeat_tuples_result t1 = {1, 3};\n\n int N1 = 4;\n\n repeat_tuples_result* res1 = func0(t1, N1);\n\n repeat_tuples_result expected1[4] = { {1,3}, {1,3}, {1,3}, {1,3} };\n\n for(int i = 0; i < N1; i++) {\n\n assert(res1[i].a == expected1[i].a && res1[i].b == expected1[i].b);\n\n }\n\n free(res1);\n\n\n\n // Second test\n\n repeat_tuples_result t2 = {1, 2};\n\n int N2 = 3;\n\n repeat_tuples_result* res2 = func0(t2, N2);\n\n repeat_tuples_result expected2[3] = { {1,2}, {1,2}, {1,2} };\n\n for(int i = 0; i < N2; i++) {\n\n assert(res2[i].a == expected2[i].a && res2[i].b == expected2[i].b);\n\n }\n\n free(res2);\n\n\n\n // Third test\n\n repeat_tuples_result t3 = {3, 4};\n\n int N3 = 5;\n\n repeat_tuples_result* res3 = func0(t3, N3);\n\n repeat_tuples_result expected3[5] = { {3,4}, {3,4}, {3,4}, {3,4}, {3,4} };\n\n for(int i = 0; i < N3; i++) {\n\n assert(res3[i].a == expected3[i].a && res3[i].b == expected3[i].b);\n\n }\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nmov %rdi,%rbx\nmovslq %esi,%rdi\nmov %rdi,%rbp\nshl $0x3,%rdi\nsub $0x8,%rsp\ncallq 10b0 \ntest %ebp,%ebp\njle 13dc \nlea -0x1(%rbp),%ecx\nmov %rax,%rdx\nlea 0x8(%rax,%rcx,8),%rcx\nnopl 0x0(%rax,%rax,1)\nmov %rbx,(%rdx)\nadd $0x8,%rdx\ncmp %rcx,%rdx\njne 13d0 \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\nmovsxd rbp, esi\npush rbx\nmov r12, rbp\nshl rbp, 3\nmov rbx, rdi\nmov rdi, rbp; size\ncall _malloc\ntest r12d, r12d\njle short loc_13C0\nlea rcx, [rbp+rax+0]\nand ebp, 8\nmov rdx, rax\njz short loc_13B0\nlea rdx, [rax+8]\nmov [rax], rbx\ncmp rdx, rcx\njz short loc_13C0\nnop dword ptr [rax+rax+00h]\nloc_13B0:\nmov [rdx], rbx\nadd rdx, 10h\nmov [rdx-8], rbx\ncmp rdx, rcx\njnz short loc_13B0\nloc_13C0:\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, int a2)\n{\n size_t v2; // rbp\n _QWORD *result; // rax\n _QWORD *v4; // rcx\n _QWORD *v5; // rdx\n\n v2 = 8LL * a2;\n result = malloc(v2);\n if ( a2 > 0 )\n {\n v4 = &result[v2 / 8];\n v5 = result;\n if ( (v2 & 8) == 0 || (v5 = result + 1, *result = a1, result + 1 != v4) )\n {\n do\n {\n *v5 = a1;\n v5 += 2;\n *(v5 - 1) = a1;\n }\n while ( v5 != v4 );\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1370:\nendbr64\npush r12\npush rbp\nmovsxd rbp, esi\npush rbx\nmov r12, rbp\nshl rbp, 3\nmov rbx, rdi\nmov rdi, rbp; size\ncall _malloc\ntest r12d, r12d\njle short loc_13C0\nlea rcx, [rbp+rax+0]\nand ebp, 8\nmov rdx, rax\njz short loc_13B0\nlea rdx, [rax+8]\nmov [rax], rbx\ncmp rdx, rcx\njz short loc_13C0\nnop dword ptr [rax+rax+00h]\nloc_13B0:\nmov [rdx], rbx\nadd rdx, 10h\nmov [rdx-8], rbx\ncmp rdx, rcx\njnz short loc_13B0\nloc_13C0:\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1370(__int64 a1, int a2)\n{\n size_t v2; // rbp\n _QWORD *result; // rax\n _QWORD *v4; // rcx\n _QWORD *v5; // rdx\n\n v2 = 8LL * a2;\n result = malloc(v2);\n if ( a2 > 0 )\n {\n v4 = &result[v2 / 8];\n v5 = result;\n if ( (v2 & 8) == 0 || (v5 = result + 1, *result = a1, result + 1 != v4) )\n {\n do\n {\n *v5 = a1;\n v5 += 2;\n *(v5 - 1) = a1;\n }\n while ( v5 != v4 );\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1370(long long a1, int a2) {\n unsigned int v2;\n uint64_t *result;\n uint64_t *v4;\n uint64_t *v5;\n v2 = 8LL * a2;\n result = malloc(v2);\n if (a2 > 0) {\n v4 = &result[v2 / 8];\n v5 = result;\n if ((v2 & 8) == 0 || (v5 = result + 1, *result = a1, result + 1 != v4)) {\n do {\n *v5 = a1;\n v5 += 2;\n *(v5 - 1) = a1;\n } while (v5 != v4);\n }\n }\n return result;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, int a2) {\n unsigned int v2;\n uint64_t *result;\n uint64_t *v4;\n uint64_t *v5;\n v2 = 8LL * a2;\n result = malloc(v2);\n if (a2 > 0) {\n v4 = &result[v2 / 8];\n v5 = result;\n if ((v2 & 8) == 0 || (v5 = result + 1, *result = a1, result + 1 != v4)) {\n do {\n *v5 = a1;\n v5 += 2;\n *(v5 - 1) = a1;\n } while (v5 != v4);\n }\n }\n return result;\n}" + }, + { + "index": 368, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int a;\n\n int b;\n\n} repeat_tuples_result;\n\n\n\n", + "func": "repeat_tuples_result* func0(repeat_tuples_result test_tup, int N) {\n repeat_tuples_result* res = malloc(N * sizeof(repeat_tuples_result));\n for (int i = 0; i < N; i++) {\n res[i] = test_tup;\n }\n return res;\n}", + "test": "int main() {\n\n // First test\n\n repeat_tuples_result t1 = {1, 3};\n\n int N1 = 4;\n\n repeat_tuples_result* res1 = func0(t1, N1);\n\n repeat_tuples_result expected1[4] = { {1,3}, {1,3}, {1,3}, {1,3} };\n\n for(int i = 0; i < N1; i++) {\n\n assert(res1[i].a == expected1[i].a && res1[i].b == expected1[i].b);\n\n }\n\n free(res1);\n\n\n\n // Second test\n\n repeat_tuples_result t2 = {1, 2};\n\n int N2 = 3;\n\n repeat_tuples_result* res2 = func0(t2, N2);\n\n repeat_tuples_result expected2[3] = { {1,2}, {1,2}, {1,2} };\n\n for(int i = 0; i < N2; i++) {\n\n assert(res2[i].a == expected2[i].a && res2[i].b == expected2[i].b);\n\n }\n\n free(res2);\n\n\n\n // Third test\n\n repeat_tuples_result t3 = {3, 4};\n\n int N3 = 5;\n\n repeat_tuples_result* res3 = func0(t3, N3);\n\n repeat_tuples_result expected3[5] = { {3,4}, {3,4}, {3,4}, {3,4}, {3,4} };\n\n for(int i = 0; i < N3; i++) {\n\n assert(res3[i].a == expected3[i].a && res3[i].b == expected3[i].b);\n\n }\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nmov %rdi,%rbx\nmovslq %esi,%rdi\nmov %rdi,%rbp\nshl $0x3,%rdi\nsub $0x8,%rsp\ncallq 10b0 \ntest %ebp,%ebp\njle 13fc \nlea -0x1(%rbp),%ecx\nmov %rax,%rdx\nlea 0x8(%rax,%rcx,8),%rcx\nnopl 0x0(%rax,%rax,1)\nmov %rbx,(%rdx)\nadd $0x8,%rdx\ncmp %rcx,%rdx\njne 13f0 \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\nmovsxd rbp, esi\npush rbx\nmov r12, rbp\nshl rbp, 3\nmov rbx, rdi\nmov rdi, rbp; size\ncall _malloc\ntest r12d, r12d\njle short loc_11B0\nlea rcx, [rbp+rax+0]\nand ebp, 8\nmov rdx, rax\njz short loc_11A0\nlea rdx, [rax+8]\nmov [rax], rbx\ncmp rdx, rcx\njz short loc_11B0\nnop dword ptr [rax+rax+00h]\nloc_11A0:\nmov [rdx], rbx\nadd rdx, 10h\nmov [rdx-8], rbx\ncmp rdx, rcx\njnz short loc_11A0\nloc_11B0:\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, int a2)\n{\n size_t v2; // rbp\n _QWORD *result; // rax\n _QWORD *v4; // rcx\n _QWORD *v5; // rdx\n\n v2 = 8LL * a2;\n result = malloc(v2);\n if ( a2 > 0 )\n {\n v4 = &result[v2 / 8];\n v5 = result;\n if ( (v2 & 8) == 0 || (v5 = result + 1, *result = a1, result + 1 != v4) )\n {\n do\n {\n *v5 = a1;\n v5 += 2;\n *(v5 - 1) = a1;\n }\n while ( v5 != v4 );\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1160:\nendbr64\npush r12\npush rbp\nmovsxd rbp, esi\npush rbx\nmov r12, rbp\nshl rbp, 3\nmov rbx, rdi\nmov rdi, rbp; size\ncall _malloc\ntest r12d, r12d\njle short loc_11B0\nlea rcx, [rbp+rax+0]\nand ebp, 8\nmov rdx, rax\njz short loc_11A0\nlea rdx, [rax+8]\nmov [rax], rbx\ncmp rdx, rcx\njz short loc_11B0\nnop dword ptr [rax+rax+00h]\nloc_11A0:\nmov [rdx], rbx\nadd rdx, 10h\nmov [rdx-8], rbx\ncmp rdx, rcx\njnz short loc_11A0\nloc_11B0:\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1160(__int64 a1, int a2)\n{\n size_t v2; // rbp\n _QWORD *result; // rax\n _QWORD *v4; // rcx\n _QWORD *v5; // rdx\n\n v2 = 8LL * a2;\n result = malloc(v2);\n if ( a2 > 0 )\n {\n v4 = &result[v2 / 8];\n v5 = result;\n if ( (v2 & 8) == 0 || (v5 = result + 1, *result = a1, result + 1 != v4) )\n {\n do\n {\n *v5 = a1;\n v5 += 2;\n *(v5 - 1) = a1;\n }\n while ( v5 != v4 );\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1160(long long a1, int a2) {\n unsigned int v2;\n uint64_t *result;\n uint64_t *v4;\n uint64_t *v5;\n v2 = 8LL * a2;\n result = malloc(v2);\n if (a2 > 0) {\n v4 = &result[v2 / 8];\n v5 = result;\n if ((v2 & 8) == 0 || (v5 = result + 1, *result = a1, result + 1 != v4)) {\n do {\n *v5 = a1;\n v5 += 2;\n *(v5 - 1) = a1;\n } while (v5 != v4);\n }\n }\n return result;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, int a2) {\n unsigned int v2;\n uint64_t *result;\n uint64_t *v4;\n uint64_t *v5;\n v2 = 8LL * a2;\n result = malloc(v2);\n if (a2 > 0) {\n v4 = &result[v2 / 8];\n v5 = result;\n if ((v2 & 8) == 0 || (v5 = result + 1, *result = a1, result + 1 != v4)) {\n do {\n *v5 = a1;\n v5 += 2;\n *(v5 - 1) = a1;\n } while (v5 != v4);\n }\n }\n return result;\n}" + }, + { + "index": 369, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int l, int w, int h) {\n int LSA = 2 * h * (l + w);\n return LSA;\n}", + "test": "int main() {\n\n assert(func0(8, 5, 6) == 156);\n\n assert(func0(7, 9, 10) == 320);\n\n assert(func0(10, 20, 30) == 1800);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov %edx,-0x1c(%rbp)\nmov -0x14(%rbp),%edx\nmov -0x18(%rbp),%eax\nadd %edx,%eax\nimul -0x1c(%rbp),%eax\nadd %eax,%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov edx, [rbp+var_14]\nmov eax, [rbp+var_18]\nadd eax, edx\nimul eax, [rbp+var_1C]\nadd eax, eax\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, int a3)\n{\n return (unsigned int)(2 * a3 * (a1 + a2));\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov edx, [rbp+var_14]\nmov eax, [rbp+var_18]\nadd eax, edx\nimul eax, [rbp+var_1C]\nadd eax, eax\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2, int a3)\n{\n return (unsigned int)(2 * a3 * (a1 + a2));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2, int a3) {\n return (unsigned int)(2 * a3 * (a1 + a2));\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, int a3) {\n return (unsigned int)(2 * a3 * (a1 + a2));\n}" + }, + { + "index": 370, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char *item;\n\n char *price;\n\n} Tuple;\n\n\n\nint compare_tuples(const void *a, const void *b) {\n\n const Tuple *tuple_a = (const Tuple *)a;\n\n const Tuple *tuple_b = (const Tuple *)b;\n\n float price_a = atof(tuple_a->price);\n\n float price_b = atof(tuple_b->price);\n\n return (price_b > price_a) - (price_b < price_a);\n\n}\n\n\n\n", + "func": "Tuple* func0(Tuple arr[], int len) {\n qsort(arr, len, sizeof(Tuple), compare_tuples);\n return arr;\n}", + "test": "int main() {\n\n Tuple arr1[3] = {{\"item1\", \"12.20\"}, {\"item2\", \"15.10\"}, {\"item3\", \"24.5\"}};\n\n Tuple arr2[3] = {{\"item1\", \"15\"}, {\"item2\", \"10\"}, {\"item3\", \"20\"}};\n\n Tuple arr3[3] = {{\"item1\", \"5\"}, {\"item2\", \"10\"}, {\"item3\", \"14\"}};\n\n \n\n Tuple *sorted_arr1 = func0(arr1, 3);\n\n assert(strcmp(sorted_arr1[0].item, \"item3\") == 0 && strcmp(sorted_arr1[1].item, \"item2\") == 0 && strcmp(sorted_arr1[2].item, \"item1\") == 0);\n\n\n\n Tuple *sorted_arr2 = func0(arr2, 3);\n\n assert(strcmp(sorted_arr2[0].item, \"item3\") == 0 && strcmp(sorted_arr2[1].item, \"item1\") == 0 && strcmp(sorted_arr2[2].item, \"item2\") == 0);\n\n \n\n Tuple *sorted_arr3 = func0(arr3, 3);\n\n assert(strcmp(sorted_arr3[0].item, \"item3\") == 0 && strcmp(sorted_arr3[1].item, \"item2\") == 0 && strcmp(sorted_arr3[2].item, \"item1\") == 0);\n\n \n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %rdi,-0x8(%rbp)\nmov %esi,-0xc(%rbp)\nmov -0xc(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x8(%rbp),%rax\nlea -0x9e(%rip),%rcx\nmov $0x10,%edx\nmov %rax,%rdi\ncallq 1090 \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+base], rdi\nmov [rbp+var_C], esi\nmov eax, [rbp+var_C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compare_tuples\nmov rcx, rdx; compar\nmov edx, 10h; size\nmov rdi, rax; base\ncall _qsort\nmov rax, [rbp+base]\nleave\nretn", + "ida_pseudo": "void *__fastcall func0(void *a1, int a2)\n{\n qsort(a1, a2, 0x10uLL, compare_tuples);\n return a1;\n}", + "ida_strip_asm": "sub_1243:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+base], rdi\nmov [rbp+var_C], esi\nmov eax, [rbp+var_C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 10h; size\nmov rdi, rax; base\ncall _qsort\nmov rax, [rbp+base]\nleave\nretn", + "ida_strip_pseudo": "void *__fastcall sub_1243(void *a1, int a2)\n{\n qsort(a1, a2, 0x10uLL, compar);\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1243(void *a1, int a2) {\n qsort(a1, a2, 16uLL, compar);\n return a1;\n}", + "ida_pseudo_norm": "void *func0(void *a1, int a2) {\n qsort(a1, a2, 16uLL, compare_tuples);\n return a1;\n}" + }, + { + "index": 370, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char *item;\n\n char *price;\n\n} Tuple;\n\n\n\nint compare_tuples(const void *a, const void *b) {\n\n const Tuple *tuple_a = (const Tuple *)a;\n\n const Tuple *tuple_b = (const Tuple *)b;\n\n float price_a = atof(tuple_a->price);\n\n float price_b = atof(tuple_b->price);\n\n return (price_b > price_a) - (price_b < price_a);\n\n}\n\n\n\n", + "func": "Tuple* func0(Tuple arr[], int len) {\n qsort(arr, len, sizeof(Tuple), compare_tuples);\n return arr;\n}", + "test": "int main() {\n\n Tuple arr1[3] = {{\"item1\", \"12.20\"}, {\"item2\", \"15.10\"}, {\"item3\", \"24.5\"}};\n\n Tuple arr2[3] = {{\"item1\", \"15\"}, {\"item2\", \"10\"}, {\"item3\", \"20\"}};\n\n Tuple arr3[3] = {{\"item1\", \"5\"}, {\"item2\", \"10\"}, {\"item3\", \"14\"}};\n\n \n\n Tuple *sorted_arr1 = func0(arr1, 3);\n\n assert(strcmp(sorted_arr1[0].item, \"item3\") == 0 && strcmp(sorted_arr1[1].item, \"item2\") == 0 && strcmp(sorted_arr1[2].item, \"item1\") == 0);\n\n\n\n Tuple *sorted_arr2 = func0(arr2, 3);\n\n assert(strcmp(sorted_arr2[0].item, \"item3\") == 0 && strcmp(sorted_arr2[1].item, \"item1\") == 0 && strcmp(sorted_arr2[2].item, \"item2\") == 0);\n\n \n\n Tuple *sorted_arr3 = func0(arr3, 3);\n\n assert(strcmp(sorted_arr3[0].item, \"item3\") == 0 && strcmp(sorted_arr3[1].item, \"item2\") == 0 && strcmp(sorted_arr3[2].item, \"item1\") == 0);\n\n \n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\nmovslq %esi,%rsi\nlea -0x6c(%rip),%rcx\nmov $0x10,%edx\ncallq 1080 \nmov %rbx,%rax\npop %rbx\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\nmovsxd rsi, esi; nmemb\nlea rcx, compare_tuples; compar\nmov edx, 10h; size\ncall _qsort\nmov rax, rbx\npop rbx\nretn", + "ida_pseudo": "void *__fastcall func0(void *a1, int a2)\n{\n qsort(a1, a2, 0x10uLL, compare_tuples);\n return a1;\n}", + "ida_strip_asm": "sub_1223:\nendbr64\npush rbx\nmov rbx, rdi\nmovsxd rsi, esi; nmemb\nlea rcx, compar; compar\nmov edx, 10h; size\ncall _qsort\nmov rax, rbx\npop rbx\nretn", + "ida_strip_pseudo": "void *__fastcall sub_1223(void *a1, int a2)\n{\n qsort(a1, a2, 0x10uLL, compar);\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1223(void *a1, int a2) {\n qsort(a1, a2, 16uLL, compar);\n return a1;\n}", + "ida_pseudo_norm": "void *func0(void *a1, int a2) {\n qsort(a1, a2, 16uLL, compare_tuples);\n return a1;\n}" + }, + { + "index": 371, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int A[], int left_element, int right_element) {\n if (left_element > right_element) {\n return left_element;\n }\n int mid = left_element + (right_element - left_element) / 2;\n if (A[mid] == mid) {\n return func0(A, mid + 1, right_element);\n } else {\n return func0(A, left_element, mid - 1);\n }\n}", + "test": "int main() {\n\n int test_array1[] = {0, 1, 2, 3, 4, 5, 6};\n\n int test_array2[] = {0, 1, 2, 6, 9, 11, 15};\n\n int test_array3[] = {1, 2, 3, 4, 6, 9, 11, 15};\n\n\n\n assert(func0(test_array1, 0, 6) == 7);\n\n assert(func0(test_array2, 0, 6) == 3);\n\n assert(func0(test_array3, 0, 7) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmov -0x1c(%rbp),%eax\ncmp -0x20(%rbp),%eax\njle 118c \nmov -0x1c(%rbp),%eax\njmp 11f0 \nmov -0x20(%rbp),%eax\nsub -0x1c(%rbp),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nmov %eax,%edx\nmov -0x1c(%rbp),%eax\nadd %edx,%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x4(%rbp)\njne 11d9 \nmov -0x4(%rbp),%eax\nlea 0x1(%rax),%ecx\nmov -0x20(%rbp),%edx\nmov -0x18(%rbp),%rax\nmov %ecx,%esi\nmov %rax,%rdi\ncallq 1169 \njmp 11f0 \nmov -0x4(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x1c(%rbp),%ecx\nmov -0x18(%rbp),%rax\nmov %ecx,%esi\nmov %rax,%rdi\ncallq 1169 \nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_20]\njle short loc_118C\nmov eax, [rbp+var_1C]\njmp short locret_11F0\nloc_118C:\nmov eax, [rbp+var_20]\nsub eax, [rbp+var_1C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov edx, eax\nmov eax, [rbp+var_1C]\nadd eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_4], eax\njnz short loc_11D9\nmov eax, [rbp+var_4]\nlea ecx, [rax+1]\nmov edx, [rbp+var_20]\nmov rax, [rbp+var_18]\nmov esi, ecx\nmov rdi, rax\ncall func0\njmp short locret_11F0\nloc_11D9:\nmov eax, [rbp+var_4]\nlea edx, [rax-1]\nmov ecx, [rbp+var_1C]\nmov rax, [rbp+var_18]\nmov esi, ecx\nmov rdi, rax\ncall func0\nlocret_11F0:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, unsigned int a2, unsigned int a3)\n{\n unsigned int v4; // [rsp+1Ch] [rbp-4h]\n\n if ( (int)a2 > (int)a3 )\n return a2;\n v4 = (int)(a3 - a2) / 2 + a2;\n if ( v4 == *(_DWORD *)(4LL * (int)v4 + a1) )\n return func0(a1, v4 + 1, a3);\n else\n return func0(a1, a2, v4 - 1);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_20]\njle short loc_118C\nmov eax, [rbp+var_1C]\njmp short locret_11F0\nloc_118C:\nmov eax, [rbp+var_20]\nsub eax, [rbp+var_1C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov edx, eax\nmov eax, [rbp+var_1C]\nadd eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_4], eax\njnz short loc_11D9\nmov eax, [rbp+var_4]\nlea ecx, [rax+1]\nmov edx, [rbp+var_20]\nmov rax, [rbp+var_18]\nmov esi, ecx\nmov rdi, rax\ncall sub_1169\njmp short locret_11F0\nloc_11D9:\nmov eax, [rbp+var_4]\nlea edx, [rax-1]\nmov ecx, [rbp+var_1C]\nmov rax, [rbp+var_18]\nmov esi, ecx\nmov rdi, rax\ncall sub_1169\nlocret_11F0:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, unsigned int a2, unsigned int a3)\n{\n unsigned int v4; // [rsp+1Ch] [rbp-4h]\n\n if ( (int)a2 > (int)a3 )\n return a2;\n v4 = (int)(a3 - a2) / 2 + a2;\n if ( v4 == *(_DWORD *)(4LL * (int)v4 + a1) )\n return sub_1169(a1, v4 + 1, a3);\n else\n return sub_1169(a1, a2, v4 - 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, unsigned int a2, unsigned int a3) {\n unsigned int v4;\n if ((int)a2 > (int)a3) return a2;\n v4 = (int)(a3 - a2) / 2 + a2;\n if (v4 == *(uint32_t *)(4LL * (int)v4 + a1))\n return sub_1169(a1, v4 + 1, a3);\n else\n return sub_1169(a1, a2, v4 - 1);\n}", + "ida_pseudo_norm": "long long func0(long long a1, unsigned int a2, unsigned int a3) {\n unsigned int v4;\n if ((int)a2 > (int)a3) return a2;\n v4 = (int)(a3 - a2) / 2 + a2;\n if (v4 == *(uint32_t *)(4LL * (int)v4 + a1))\n return func0(a1, v4 + 1, a3);\n else\n return func0(a1, a2, v4 - 1);\n}" + }, + { + "index": 371, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int A[], int left_element, int right_element) {\n if (left_element > right_element) {\n return left_element;\n }\n int mid = left_element + (right_element - left_element) / 2;\n if (A[mid] == mid) {\n return func0(A, mid + 1, right_element);\n } else {\n return func0(A, left_element, mid - 1);\n }\n}", + "test": "int main() {\n\n int test_array1[] = {0, 1, 2, 3, 4, 5, 6};\n\n int test_array2[] = {0, 1, 2, 6, 9, 11, 15};\n\n int test_array3[] = {1, 2, 3, 4, 6, 9, 11, 15};\n\n\n\n assert(func0(test_array1, 0, 6) == 7);\n\n assert(func0(test_array2, 0, 6) == 3);\n\n assert(func0(test_array3, 0, 7) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %esi,%eax\ncmp %edx,%esi\njg 11a5 \nsub $0x8,%rsp\nmov %edx,%ecx\nsub %esi,%ecx\nmov %ecx,%eax\nshr $0x1f,%eax\nadd %ecx,%eax\nsar %eax\nadd %esi,%eax\nmovslq %eax,%rcx\ncmp %eax,(%rdi,%rcx,4)\nje 119b \nlea -0x1(%rax),%edx\ncallq 1169 \nadd $0x8,%rsp\nretq\nlea 0x1(%rax),%esi\ncallq 1169 \njmp 1196 \nretq\n", + "ida_asm": "func0:\nendbr64\nmov eax, esi\ncmp esi, edx\njg short locret_11A5\nsub rsp, 8\nmov ecx, edx\nsub ecx, esi\nmov eax, ecx\nshr eax, 1Fh\nadd eax, ecx\nsar eax, 1\nadd eax, esi\nmovsxd rcx, eax\ncmp [rdi+rcx*4], eax\njz short loc_119B\nlea edx, [rax-1]\ncall func0\nloc_1196:\nadd rsp, 8\nretn\nloc_119B:\nlea esi, [rax+1]\ncall func0\njmp short loc_1196\nlocret_11A5:\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n __int64 result; // rax\n int v4; // eax\n\n result = (unsigned int)a2;\n if ( (int)a2 <= a3 )\n {\n v4 = a2 + (a3 - (int)a2) / 2;\n if ( *(_DWORD *)(a1 + 4LL * v4) == v4 )\n return func0(a1, (unsigned int)(v4 + 1));\n else\n return func0(a1, a2);\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov eax, esi\ncmp esi, edx\njg short locret_11A5\nsub rsp, 8\nmov ecx, edx\nsub ecx, esi\nmov eax, ecx\nshr eax, 1Fh\nadd eax, ecx\nsar eax, 1\nadd eax, esi\nmovsxd rcx, eax\ncmp [rdi+rcx*4], eax\njz short loc_119B\nlea edx, [rax-1]\ncall sub_1169\nloc_1196:\nadd rsp, 8\nretn\nloc_119B:\nlea esi, [rax+1]\ncall sub_1169\njmp short loc_1196\nlocret_11A5:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, int a3)\n{\n __int64 result; // rax\n int v4; // eax\n\n result = (unsigned int)a2;\n if ( (int)a2 <= a3 )\n {\n v4 = a2 + (a3 - (int)a2) / 2;\n if ( *(_DWORD *)(a1 + 4LL * v4) == v4 )\n return sub_1169(a1, (unsigned int)(v4 + 1));\n else\n return sub_1169(a1, a2);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, int a3) {\n long long result;\n int v4;\n result = (unsigned int)a2;\n if ((int)a2 <= a3) {\n v4 = a2 + (a3 - (int)a2) / 2;\n if (*(uint32_t *)(a1 + 4LL * v4) == v4)\n return sub_1169(a1, (unsigned int)(v4 + 1));\n else\n return sub_1169(a1, a2);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3) {\n long long result;\n int v4;\n result = (unsigned int)a2;\n if ((int)a2 <= a3) {\n v4 = a2 + (a3 - (int)a2) / 2;\n if (*(uint32_t *)(a1 + 4LL * v4) == v4)\n return func0(a1, (unsigned int)(v4 + 1));\n else\n return func0(a1, a2);\n }\n return result;\n}" + }, + { + "index": 371, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int A[], int left_element, int right_element) {\n if (left_element > right_element) {\n return left_element;\n }\n int mid = left_element + (right_element - left_element) / 2;\n if (A[mid] == mid) {\n return func0(A, mid + 1, right_element);\n } else {\n return func0(A, left_element, mid - 1);\n }\n}", + "test": "int main() {\n\n int test_array1[] = {0, 1, 2, 3, 4, 5, 6};\n\n int test_array2[] = {0, 1, 2, 6, 9, 11, 15};\n\n int test_array3[] = {1, 2, 3, 4, 6, 9, 11, 15};\n\n\n\n assert(func0(test_array1, 0, 6) == 7);\n\n assert(func0(test_array2, 0, 6) == 3);\n\n assert(func0(test_array3, 0, 7) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov %esi,%eax\ncmp %edx,%esi\njle 1347 \njmp 1360 \nnopl 0x0(%rax)\nlea -0x1(%rcx),%edx\ncmp %edx,%eax\njg 135e \nmov %edx,%ecx\nsub %eax,%ecx\nsar %ecx\nadd %eax,%ecx\nmovslq %ecx,%rsi\ncmp %ecx,(%rdi,%rsi,4)\njne 1340 \nlea 0x1(%rcx),%eax\ncmp %edx,%eax\njle 1347 \nretq\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmov eax, esi\nloc_12A6:\ncmp eax, edx\njg short locret_12C1\nloc_12AA:\nmov ecx, edx\nsub ecx, eax\nsar ecx, 1\nadd ecx, eax\nmovsxd rsi, ecx\ncmp ecx, [rdi+rsi*4]\njz short loc_12C8\nlea edx, [rcx-1]\ncmp eax, edx\njle short loc_12AA\nlocret_12C1:\nretn\nloc_12C8:\nlea eax, [rcx+1]\njmp short loc_12A6", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, unsigned int a2, int a3)\n{\n __int64 result; // rax\n int v4; // ecx\n\n for ( result = a2; (int)result <= a3; result = (unsigned int)(v4 + 1) )\n {\n while ( 1 )\n {\n v4 = result + ((a3 - (int)result) >> 1);\n if ( v4 == *(_DWORD *)(a1 + 4LL * v4) )\n break;\n a3 = v4 - 1;\n if ( (int)result > v4 - 1 )\n return result;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_12A0:\nendbr64\nmov eax, esi\nloc_12A6:\ncmp eax, edx\njg short locret_12C1\nloc_12AA:\nmov ecx, edx\nsub ecx, eax\nsar ecx, 1\nadd ecx, eax\nmovsxd rsi, ecx\ncmp ecx, [rdi+rsi*4]\njz short loc_12C8\nlea edx, [rcx-1]\ncmp eax, edx\njle short loc_12AA\nlocret_12C1:\nretn\nloc_12C8:\nlea eax, [rcx+1]\njmp short loc_12A6", + "ida_strip_pseudo": "__int64 __fastcall sub_12A0(__int64 a1, unsigned int a2, int a3)\n{\n __int64 result; // rax\n int v4; // ecx\n\n for ( result = a2; (int)result <= a3; result = (unsigned int)(v4 + 1) )\n {\n while ( 1 )\n {\n v4 = result + ((a3 - (int)result) >> 1);\n if ( v4 == *(_DWORD *)(a1 + 4LL * v4) )\n break;\n a3 = v4 - 1;\n if ( (int)result > v4 - 1 )\n return result;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12A0(long long a1, unsigned int a2, int a3) {\n long long result;\n int v4;\n for (result = a2; (int)result <= a3; result = (unsigned int)(v4 + 1)) {\n while (1) {\n v4 = result + ((a3 - (int)result) >> 1);\n if (v4 == *(uint32_t *)(a1 + 4LL * v4)) break;\n a3 = v4 - 1;\n if ((int)result > v4 - 1) return result;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, unsigned int a2, int a3) {\n long long result;\n int v4;\n for (result = a2; (int)result <= a3; result = (unsigned int)(v4 + 1)) {\n while (1) {\n v4 = result + ((a3 - (int)result) >> 1);\n if (v4 == *(uint32_t *)(a1 + 4LL * v4)) break;\n a3 = v4 - 1;\n if ((int)result > v4 - 1) return result;\n }\n }\n return result;\n}" + }, + { + "index": 372, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n// Function to maintain the min heap property\n\nvoid min_heapify(int* heap, int size, int i) {\n\n int smallest = i;\n\n int left = 2*i +1;\n\n int right = 2*i +2;\n\n\n\n if(left < size && heap[left] < heap[smallest])\n\n smallest = left;\n\n if(right < size && heap[right] < heap[smallest])\n\n smallest = right;\n\n if(smallest != i){\n\n int temp = heap[i];\n\n heap[i] = heap[smallest];\n\n heap[smallest] = temp;\n\n min_heapify(heap, size, smallest);\n\n }\n\n}\n\n\n\n", + "func": "int* func0(int* nums, int size) {\n int* heap = malloc(size * sizeof(int));\n for (int i = 0; i < size; i++) heap[i] = nums[i];\n for (int i = (size / 2) - 1; i >= 0; i--) min_heapify(heap, size, i);\n int* sorted = malloc(size * sizeof(int));\n int heap_size = size;\n for (int i = 0; i < size; i++) {\n sorted[i] = heap[0];\n heap[0] = heap[heap_size - 1];\n heap_size--;\n min_heapify(heap, heap_size, 0);\n }\n free(heap);\n return sorted;\n}", + "test": "int main() {\n\n // Test Case 1\n\n int test1[] = {18, 14, 10, 9, 8, 7, 9, 3, 2, 4, 1};\n\n int expected1[] = {1, 2, 3, 4, 7, 8, 9, 9, 10, 14, 18};\n\n int size1 = sizeof(test1)/sizeof(test1[0]);\n\n int* result1 = func0(test1, size1);\n\n for(int i=0; i\nmov %rax,-0x10(%rbp)\nmovl $0x0,-0x20(%rbp)\njmp 1337 \nmov -0x20(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov -0x20(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x10(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x20(%rbp)\nmov -0x20(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 1306 \nmov -0x2c(%rbp),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nsub $0x1,%eax\nmov %eax,-0x1c(%rbp)\njmp 136b \nmov -0x1c(%rbp),%edx\nmov -0x2c(%rbp),%ecx\nmov -0x10(%rbp),%rax\nmov %ecx,%esi\nmov %rax,%rdi\ncallq 11a9 \nsubl $0x1,-0x1c(%rbp)\ncmpl $0x0,-0x1c(%rbp)\njns 1353 \nmov -0x2c(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\nmov -0x2c(%rbp),%eax\nmov %eax,-0x18(%rbp)\nmovl $0x0,-0x14(%rbp)\njmp 13eb \nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov -0x10(%rbp),%rax\nmov (%rax),%eax\nmov %eax,(%rdx)\nmov -0x18(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rdx\nmov -0x10(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x10(%rbp),%rax\nmov %edx,(%rax)\nsubl $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%ecx\nmov -0x10(%rbp),%rax\nmov $0x0,%edx\nmov %ecx,%esi\nmov %rax,%rdi\ncallq 11a9 \naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 1395 \nmov -0x10(%rbp),%rax\nmov %rax,%rdi\ncallq 1080 \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov [rbp+var_20], 0\njmp short loc_1337\nloc_1306:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+ptr]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_20], 1\nloc_1337:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_2C]\njl short loc_1306\nmov eax, [rbp+var_2C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nsub eax, 1\nmov [rbp+var_1C], eax\njmp short loc_136B\nloc_1353:\nmov edx, [rbp+var_1C]\nmov ecx, [rbp+var_2C]\nmov rax, [rbp+ptr]\nmov esi, ecx\nmov rdi, rax\ncall min_heapify\nsub [rbp+var_1C], 1\nloc_136B:\ncmp [rbp+var_1C], 0\njns short loc_1353\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov eax, [rbp+var_2C]\nmov [rbp+var_18], eax\nmov [rbp+var_14], 0\njmp short loc_13EB\nloc_1395:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov rax, [rbp+ptr]\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_18]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+ptr]\nmov [rax], edx\nsub [rbp+var_18], 1\nmov ecx, [rbp+var_18]\nmov rax, [rbp+ptr]\nmov edx, 0\nmov esi, ecx\nmov rdi, rax\ncall min_heapify\nadd [rbp+var_14], 1\nloc_13EB:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl short loc_1395\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, signed int a2)\n{\n int i; // [rsp+10h] [rbp-20h]\n int j; // [rsp+14h] [rbp-1Ch]\n unsigned int v5; // [rsp+18h] [rbp-18h]\n int k; // [rsp+1Ch] [rbp-14h]\n _DWORD *ptr; // [rsp+20h] [rbp-10h]\n _DWORD *v8; // [rsp+28h] [rbp-8h]\n\n ptr = malloc(4LL * a2);\n for ( i = 0; i < a2; ++i )\n ptr[i] = *(_DWORD *)(4LL * i + a1);\n for ( j = a2 / 2 - 1; j >= 0; --j )\n min_heapify(ptr, (unsigned int)a2, (unsigned int)j);\n v8 = malloc(4LL * a2);\n v5 = a2;\n for ( k = 0; k < a2; ++k )\n {\n v8[k] = *ptr;\n *ptr = ptr[--v5];\n min_heapify(ptr, v5, 0LL);\n }\n free(ptr);\n return v8;\n}", + "ida_strip_asm": "sub_12D5:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov [rbp+var_20], 0\njmp short loc_1337\nloc_1306:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+ptr]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_20], 1\nloc_1337:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_2C]\njl short loc_1306\nmov eax, [rbp+var_2C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nsub eax, 1\nmov [rbp+var_1C], eax\njmp short loc_136B\nloc_1353:\nmov edx, [rbp+var_1C]\nmov ecx, [rbp+var_2C]\nmov rax, [rbp+ptr]\nmov esi, ecx\nmov rdi, rax\ncall sub_11A9\nsub [rbp+var_1C], 1\nloc_136B:\ncmp [rbp+var_1C], 0\njns short loc_1353\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov eax, [rbp+var_2C]\nmov [rbp+var_18], eax\nmov [rbp+var_14], 0\njmp short loc_13EB\nloc_1395:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov rax, [rbp+ptr]\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_18]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+ptr]\nmov [rax], edx\nsub [rbp+var_18], 1\nmov ecx, [rbp+var_18]\nmov rax, [rbp+ptr]\nmov edx, 0\nmov esi, ecx\nmov rdi, rax\ncall sub_11A9\nadd [rbp+var_14], 1\nloc_13EB:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl short loc_1395\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_12D5(__int64 a1, signed int a2)\n{\n int i; // [rsp+10h] [rbp-20h]\n int j; // [rsp+14h] [rbp-1Ch]\n unsigned int v5; // [rsp+18h] [rbp-18h]\n int k; // [rsp+1Ch] [rbp-14h]\n _DWORD *ptr; // [rsp+20h] [rbp-10h]\n _DWORD *v8; // [rsp+28h] [rbp-8h]\n\n ptr = malloc(4LL * a2);\n for ( i = 0; i < a2; ++i )\n ptr[i] = *(_DWORD *)(4LL * i + a1);\n for ( j = a2 / 2 - 1; j >= 0; --j )\n sub_11A9(ptr, (unsigned int)a2, (unsigned int)j);\n v8 = malloc(4LL * a2);\n v5 = a2;\n for ( k = 0; k < a2; ++k )\n {\n v8[k] = *ptr;\n *ptr = ptr[--v5];\n sub_11A9(ptr, v5, 0LL);\n }\n free(ptr);\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_12D5(long long a1, signed int a2) {\n int i;\n int j;\n unsigned int v5;\n int k;\n uint32_t *ptr;\n uint32_t *v8;\n ptr = malloc(4LL * a2);\n for (i = 0; i < a2; ++i) ptr[i] = *(uint32_t *)(4LL * i + a1);\n for (j = a2 / 2 - 1; j >= 0; --j)\n sub_11A9(ptr, (unsigned int)a2, (unsigned int)j);\n v8 = malloc(4LL * a2);\n v5 = a2;\n for (k = 0; k < a2; ++k) {\n v8[k] = *ptr;\n *ptr = ptr[--v5];\n sub_11A9(ptr, v5, 0LL);\n }\n free(ptr);\n return v8;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, signed int a2) {\n int i;\n int j;\n unsigned int v5;\n int k;\n uint32_t *ptr;\n uint32_t *v8;\n ptr = malloc(4LL * a2);\n for (i = 0; i < a2; ++i) ptr[i] = *(uint32_t *)(4LL * i + a1);\n for (j = a2 / 2 - 1; j >= 0; --j)\n min_heapify(ptr, (unsigned int)a2, (unsigned int)j);\n v8 = malloc(4LL * a2);\n v5 = a2;\n for (k = 0; k < a2; ++k) {\n v8[k] = *ptr;\n *ptr = ptr[--v5];\n min_heapify(ptr, v5, 0LL);\n }\n free(ptr);\n return v8;\n}" + }, + { + "index": 372, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n// Function to maintain the min heap property\n\nvoid min_heapify(int* heap, int size, int i) {\n\n int smallest = i;\n\n int left = 2*i +1;\n\n int right = 2*i +2;\n\n\n\n if(left < size && heap[left] < heap[smallest])\n\n smallest = left;\n\n if(right < size && heap[right] < heap[smallest])\n\n smallest = right;\n\n if(smallest != i){\n\n int temp = heap[i];\n\n heap[i] = heap[smallest];\n\n heap[smallest] = temp;\n\n min_heapify(heap, size, smallest);\n\n }\n\n}\n\n\n\n", + "func": "int* func0(int* nums, int size) {\n int* heap = malloc(size * sizeof(int));\n for (int i = 0; i < size; i++) heap[i] = nums[i];\n for (int i = (size / 2) - 1; i >= 0; i--) min_heapify(heap, size, i);\n int* sorted = malloc(size * sizeof(int));\n int heap_size = size;\n for (int i = 0; i < size; i++) {\n sorted[i] = heap[0];\n heap[0] = heap[heap_size - 1];\n heap_size--;\n min_heapify(heap, heap_size, 0);\n }\n free(heap);\n return sorted;\n}", + "test": "int main() {\n\n // Test Case 1\n\n int test1[] = {18, 14, 10, 9, 8, 7, 9, 3, 2, 4, 1};\n\n int expected1[] = {1, 2, 3, 4, 7, 8, 9, 9, 10, 14, 18};\n\n int size1 = sizeof(test1)/sizeof(test1[0]);\n\n int* result1 = func0(test1, size1);\n\n for(int i=0; i\nmov %rax,%rbx\ntest %r12d,%r12d\njle 12f7 \nlea -0x1(%r12),%ecx\nmov $0x0,%eax\nmov 0x0(%rbp,%rax,4),%edx\nmov %edx,(%rbx,%rax,4)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rcx,%rdx\njne 125c \nmov %r12d,%ebp\nshr $0x1f,%ebp\nadd %r12d,%ebp\nsar %ebp\nsub $0x1,%ebp\njs 12ea \nmov %ebp,%edx\nmov %r12d,%esi\nmov %rbx,%rdi\ncallq 11a9 \nsub $0x1,%ebp\njns 127f \nmov %r13,%rdi\ncallq 10b0 \nmov %rax,%r14\ntest %r12d,%r12d\njle 12d6 \nlea -0x1(%r12),%ebp\nmovslq %ebp,%rbp\nmov $0x0,%r13d\nmov (%rbx),%eax\nmov %eax,(%r14,%r13,4)\nmov (%rbx,%rbp,4),%eax\nmov %eax,(%rbx)\nmov $0x0,%edx\nmov %ebp,%esi\nmov %rbx,%rdi\ncallq 11a9 \nadd $0x1,%r13\nsub $0x1,%rbp\ncmp %r13d,%r12d\njg 12af \nmov %rbx,%rdi\ncallq 1080 \nmov %r14,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nmov %r13,%rdi\ncallq 10b0 \nmov %rax,%r14\njmp 12a1 \nmov %r13,%rdi\ncallq 10b0 \nmov %rax,%r14\njmp 12d6 \n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12, rdi\nmov ebx, esi\nmovsxd r13, esi\nshl r13, 2\nmov rdi, r13; size\ncall _malloc\nmov rbp, rax\ntest ebx, ebx\njle loc_12E7\nmov eax, 0\nloc_1257:\nmov edx, [r12+rax]\nmov [rbp+rax+0], edx\nadd rax, 4\ncmp r13, rax\njnz short loc_1257\nmov r12d, ebx\nshr r12d, 1Fh\nadd r12d, ebx\nsar r12d, 1\nsub r12d, 1\njs short loc_1292\nloc_127B:\nmov edx, r12d\nmov esi, ebx\nmov rdi, rbp\ncall min_heapify\nsub r12d, 1\ncmp r12d, 0FFFFFFFFh\njnz short loc_127B\nloc_1292:\nmov rdi, r13; size\ncall _malloc\nmov r13, rax\nsub ebx, 1\nmovsxd rbx, ebx\nmov r12, rax\nloc_12A6:\nmov eax, [rbp+0]\nmov [r12], eax\nmov eax, [rbp+rbx*4+0]\nmov [rbp+0], eax\nmov edx, 0\nmov esi, ebx\nmov rdi, rbp\ncall min_heapify\nsub rbx, 1\nadd r12, 4\ncmp rbx, 0FFFFFFFFFFFFFFFFh\njnz short loc_12A6\nloc_12D1:\nmov rdi, rbp; ptr\ncall _free\nmov rax, r13\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_12E7:\nmov rdi, r13; size\ncall _malloc\nmov r13, rax\njmp short loc_12D1", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2)\n{\n size_t v2; // r13\n _DWORD *v3; // rbp\n unsigned __int64 v4; // rax\n int v5; // r12d\n _DWORD *v6; // r13\n __int64 v7; // rbx\n _DWORD *v8; // r12\n\n v2 = 4LL * a2;\n v3 = malloc(v2);\n if ( a2 <= 0 )\n {\n v6 = malloc(4LL * a2);\n }\n else\n {\n v4 = 0LL;\n do\n {\n v3[v4 / 4] = *(_DWORD *)(a1 + v4);\n v4 += 4LL;\n }\n while ( v2 != v4 );\n v5 = a2 / 2 - 1;\n if ( v5 >= 0 )\n {\n do\n min_heapify(v3, (unsigned int)a2, (unsigned int)v5--);\n while ( v5 != -1 );\n }\n v6 = malloc(v2);\n v7 = a2 - 1;\n v8 = v6;\n do\n {\n *v8 = *v3;\n *v3 = v3[v7];\n min_heapify(v3, (unsigned int)v7--, 0LL);\n ++v8;\n }\n while ( v7 != -1 );\n }\n free(v3);\n return v6;\n}", + "ida_strip_asm": "sub_1225:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12, rdi\nmov ebx, esi\nmovsxd r13, esi\nshl r13, 2\nmov rdi, r13; size\ncall _malloc\nmov rbp, rax\ntest ebx, ebx\njle loc_12E7\nmov eax, 0\nloc_1257:\nmov edx, [r12+rax]\nmov [rbp+rax+0], edx\nadd rax, 4\ncmp r13, rax\njnz short loc_1257\nmov r12d, ebx\nshr r12d, 1Fh\nadd r12d, ebx\nsar r12d, 1\nsub r12d, 1\njs short loc_1292\nloc_127B:\nmov edx, r12d\nmov esi, ebx\nmov rdi, rbp\ncall sub_11A9\nsub r12d, 1\ncmp r12d, 0FFFFFFFFh\njnz short loc_127B\nloc_1292:\nmov rdi, r13; size\ncall _malloc\nmov r13, rax\nsub ebx, 1\nmovsxd rbx, ebx\nmov r12, rax\nloc_12A6:\nmov eax, [rbp+0]\nmov [r12], eax\nmov eax, [rbp+rbx*4+0]\nmov [rbp+0], eax\nmov edx, 0\nmov esi, ebx\nmov rdi, rbp\ncall sub_11A9\nsub rbx, 1\nadd r12, 4\ncmp rbx, 0FFFFFFFFFFFFFFFFh\njnz short loc_12A6\nloc_12D1:\nmov rdi, rbp; ptr\ncall _free\nmov rax, r13\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_12E7:\nmov rdi, r13; size\ncall _malloc\nmov r13, rax\njmp short loc_12D1", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1225(__int64 a1, int a2)\n{\n size_t v2; // r13\n _DWORD *v3; // rbp\n unsigned __int64 v4; // rax\n int v5; // r12d\n _DWORD *v6; // r13\n __int64 v7; // rbx\n _DWORD *v8; // r12\n\n v2 = 4LL * a2;\n v3 = malloc(v2);\n if ( a2 <= 0 )\n {\n v6 = malloc(4LL * a2);\n }\n else\n {\n v4 = 0LL;\n do\n {\n v3[v4 / 4] = *(_DWORD *)(a1 + v4);\n v4 += 4LL;\n }\n while ( v2 != v4 );\n v5 = a2 / 2 - 1;\n if ( v5 >= 0 )\n {\n do\n sub_11A9(v3, (unsigned int)a2, (unsigned int)v5--);\n while ( v5 != -1 );\n }\n v6 = malloc(v2);\n v7 = a2 - 1;\n v8 = v6;\n do\n {\n *v8 = *v3;\n *v3 = v3[v7];\n sub_11A9(v3, (unsigned int)v7--, 0LL);\n ++v8;\n }\n while ( v7 != -1 );\n }\n free(v3);\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1225(long long a1, int a2) {\n unsigned int v2;\n uint32_t *v3;\n unsigned long long v4;\n int v5;\n uint32_t *v6;\n long long v7;\n uint32_t *v8;\n v2 = 4LL * a2;\n v3 = malloc(v2);\n if (a2 <= 0) {\n v6 = malloc(4LL * a2);\n } else {\n v4 = 0LL;\n do {\n v3[v4 / 4] = *(uint32_t *)(a1 + v4);\n v4 += 4LL;\n } while (v2 != v4);\n v5 = a2 / 2 - 1;\n if (v5 >= 0) {\n do\n sub_11A9(v3, (unsigned int)a2, (unsigned int)v5--);\n while (v5 != -1);\n }\n v6 = malloc(v2);\n v7 = a2 - 1;\n v8 = v6;\n do {\n *v8 = *v3;\n *v3 = v3[v7];\n sub_11A9(v3, (unsigned int)v7--, 0LL);\n ++v8;\n } while (v7 != -1);\n }\n free(v3);\n return v6;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2) {\n unsigned int v2;\n uint32_t *v3;\n unsigned long long v4;\n int v5;\n uint32_t *v6;\n long long v7;\n uint32_t *v8;\n v2 = 4LL * a2;\n v3 = malloc(v2);\n if (a2 <= 0) {\n v6 = malloc(4LL * a2);\n } else {\n v4 = 0LL;\n do {\n v3[v4 / 4] = *(uint32_t *)(a1 + v4);\n v4 += 4LL;\n } while (v2 != v4);\n v5 = a2 / 2 - 1;\n if (v5 >= 0) {\n do\n min_heapify(v3, (unsigned int)a2, (unsigned int)v5--);\n while (v5 != -1);\n }\n v6 = malloc(v2);\n v7 = a2 - 1;\n v8 = v6;\n do {\n *v8 = *v3;\n *v3 = v3[v7];\n min_heapify(v3, (unsigned int)v7--, 0LL);\n ++v8;\n } while (v7 != -1);\n }\n free(v3);\n return v6;\n}" + }, + { + "index": 372, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n// Function to maintain the min heap property\n\nvoid min_heapify(int* heap, int size, int i) {\n\n int smallest = i;\n\n int left = 2*i +1;\n\n int right = 2*i +2;\n\n\n\n if(left < size && heap[left] < heap[smallest])\n\n smallest = left;\n\n if(right < size && heap[right] < heap[smallest])\n\n smallest = right;\n\n if(smallest != i){\n\n int temp = heap[i];\n\n heap[i] = heap[smallest];\n\n heap[smallest] = temp;\n\n min_heapify(heap, size, smallest);\n\n }\n\n}\n\n\n\n", + "func": "int* func0(int* nums, int size) {\n int* heap = malloc(size * sizeof(int));\n for (int i = 0; i < size; i++) heap[i] = nums[i];\n for (int i = (size / 2) - 1; i >= 0; i--) min_heapify(heap, size, i);\n int* sorted = malloc(size * sizeof(int));\n int heap_size = size;\n for (int i = 0; i < size; i++) {\n sorted[i] = heap[0];\n heap[0] = heap[heap_size - 1];\n heap_size--;\n min_heapify(heap, heap_size, 0);\n }\n free(heap);\n return sorted;\n}", + "test": "int main() {\n\n // Test Case 1\n\n int test1[] = {18, 14, 10, 9, 8, 7, 9, 3, 2, 4, 1};\n\n int expected1[] = {1, 2, 3, 4, 7, 8, 9, 9, 10, 14, 18};\n\n int size1 = sizeof(test1)/sizeof(test1[0]);\n\n int* result1 = func0(test1, size1);\n\n for(int i=0; i\nsub $0x1,%ebx\nmov %rax,%rbp\ntest %r12d,%r12d\njle 1648 \nlea -0x1(%r12),%ecx\nxor %eax,%eax\nmov %rcx,%r14\nnopl 0x0(%rax,%rax,1)\nmov (%r15,%rax,4),%edx\nmov %edx,0x0(%rbp,%rax,4)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rcx,%rdx\njne 15b0 \ntest %ebx,%ebx\njs 1660 \nnopl 0x0(%rax)\nmov %ebx,%edx\nmov %r12d,%esi\nmov %rbp,%rdi\nsub $0x1,%ebx\ncallq 14d0 \ncmp $0xffffffff,%ebx\njne 15d0 \nmov %r13,%rdi\ncallq 10b0 \nmov %rax,%r15\ntest %r12d,%r12d\njle 1629 \nlea -0x1(%r12),%r14d\nmovslq %r14d,%r14\nxor %r13d,%r13d\nmov 0x0(%rbp),%eax\nmov %r14d,%esi\nxor %edx,%edx\nmov %rbp,%rdi\nmov %eax,(%r15,%r13,4)\nmov 0x0(%rbp,%r14,4),%eax\nadd $0x1,%r13\nsub $0x1,%r14\nmov %eax,0x0(%rbp)\ncallq 14d0 \ncmp %r13d,%r12d\njg 1600 \nmov %rbp,%rdi\ncallq 1080 \nadd $0x8,%rsp\nmov %r15,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax,%rax,1)\ntest %ebx,%ebx\njns 15d0 \nmov %r13,%rdi\ncallq 10b0 \nmov %rax,%r15\njmp 1629 \nnopl 0x0(%rax)\nmov %r13,%rdi\ncallq 10b0 \nmov %rax,%r15\njmp 15fa \nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r13\nmovsxd r13, esi\npush r12\nmov r12, rdi\npush rbp\npush rbx\nmov rbx, r13\nshl r13, 2\nmov rdi, r13; size\nsub rsp, 8\ncall _malloc\nmov rbp, rax\ntest ebx, ebx\njle loc_1570\nmov edx, ebx\nmov rsi, r12; src\nmov rdi, rax; dest\nshl rdx, 2; n\ncall _memcpy\nmov eax, ebx\nsar eax, 1\nlea r12d, [rax-1]\njz short loc_1513\nnop dword ptr [rax+00000000h]\nloc_1500:\nmov edx, r12d\nmov esi, ebx\nmov rdi, rbp\ncall min_heapify\nsub r12d, 1\njnb short loc_1500\nloc_1513:\nmov rdi, r13; size\nsub ebx, 1\ncall _malloc\nmovsxd rbx, ebx\nmov r13, rax\nmov r12, rax\nnop word ptr [rax+rax+00000000h]\nloc_1530:\nmov eax, [rbp+0]\nmov esi, ebx\nxor edx, edx\nmov rdi, rbp\nadd r12, 4\nmov [r12-4], eax\nmov eax, [rbp+rbx*4+0]\nsub rbx, 1\nmov [rbp+0], eax\ncall min_heapify\ncmp rbx, 0FFFFFFFFFFFFFFFFh\njnz short loc_1530\nloc_1559:\nmov rdi, rbp; ptr\ncall _free\nadd rsp, 8\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1570:\nmov rdi, r13; size\ncall _malloc\nmov r13, rax\njmp short loc_1559", + "ida_pseudo": "_DWORD *__fastcall func0(void *src, int a2)\n{\n _DWORD *v2; // rax\n _DWORD *v3; // rbp\n unsigned int v4; // r12d\n __int64 v6; // rbx\n _DWORD *v7; // r13\n _DWORD *v8; // r12\n __int64 v9; // rsi\n int v10; // eax\n\n v2 = malloc(4LL * a2);\n v3 = v2;\n if ( a2 <= 0 )\n {\n v7 = malloc(4LL * a2);\n }\n else\n {\n memcpy(v2, src, 4LL * (unsigned int)a2);\n v4 = (a2 >> 1) - 1;\n if ( a2 >> 1 )\n {\n do\n min_heapify(v3, (unsigned int)a2, v4);\n while ( v4-- != 0 );\n }\n v6 = a2 - 1;\n v7 = malloc(4LL * a2);\n v8 = v7;\n do\n {\n v9 = (unsigned int)v6;\n *v8++ = *v3;\n v10 = v3[v6--];\n *v3 = v10;\n min_heapify(v3, v9, 0LL);\n }\n while ( v6 != -1 );\n }\n free(v3);\n return v7;\n}", + "ida_strip_asm": "sub_14B0:\nendbr64\npush r13\nmovsxd r13, esi\npush r12\nmov r12, rdi\npush rbp\npush rbx\nmov rbx, r13\nshl r13, 2\nmov rdi, r13; size\nsub rsp, 8\ncall _malloc\nmov rbp, rax\ntest ebx, ebx\njle loc_1570\nmov edx, ebx\nmov rsi, r12; src\nmov rdi, rax; dest\nshl rdx, 2; n\ncall _memcpy\nmov eax, ebx\nsar eax, 1\nlea r12d, [rax-1]\njz short loc_1513\nnop dword ptr [rax+00000000h]\nloc_1500:\nmov edx, r12d\nmov esi, ebx\nmov rdi, rbp\ncall sub_1430\nsub r12d, 1\njnb short loc_1500\nloc_1513:\nmov rdi, r13; size\nsub ebx, 1\ncall _malloc\nmovsxd rbx, ebx\nmov r13, rax\nmov r12, rax\nnop word ptr [rax+rax+00000000h]\nloc_1530:\nmov eax, [rbp+0]\nmov esi, ebx\nxor edx, edx\nmov rdi, rbp\nadd r12, 4\nmov [r12-4], eax\nmov eax, [rbp+rbx*4+0]\nsub rbx, 1\nmov [rbp+0], eax\ncall sub_1430\ncmp rbx, 0FFFFFFFFFFFFFFFFh\njnz short loc_1530\nloc_1559:\nmov rdi, rbp; ptr\ncall _free\nadd rsp, 8\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1570:\nmov rdi, r13; size\ncall _malloc\nmov r13, rax\njmp short loc_1559", + "ida_strip_pseudo": "_DWORD *__fastcall sub_14B0(void *src, int a2)\n{\n _DWORD *v2; // rax\n _DWORD *v3; // rbp\n unsigned int v4; // r12d\n __int64 v6; // rbx\n _DWORD *v7; // r13\n _DWORD *v8; // r12\n __int64 v9; // rsi\n int v10; // eax\n\n v2 = malloc(4LL * a2);\n v3 = v2;\n if ( a2 <= 0 )\n {\n v7 = malloc(4LL * a2);\n }\n else\n {\n memcpy(v2, src, 4LL * (unsigned int)a2);\n v4 = (a2 >> 1) - 1;\n if ( a2 >> 1 )\n {\n do\n sub_1430(v3, (unsigned int)a2, v4);\n while ( v4-- != 0 );\n }\n v6 = a2 - 1;\n v7 = malloc(4LL * a2);\n v8 = v7;\n do\n {\n v9 = (unsigned int)v6;\n *v8++ = *v3;\n v10 = v3[v6--];\n *v3 = v10;\n sub_1430(v3, v9, 0LL);\n }\n while ( v6 != -1 );\n }\n free(v3);\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_14B0(void *src, int a2) {\n uint32_t *v2;\n uint32_t *v3;\n unsigned int v4;\n long long v6;\n uint32_t *v7;\n uint32_t *v8;\n long long v9;\n int v10;\n v2 = malloc(4LL * a2);\n v3 = v2;\n if (a2 <= 0) {\n v7 = malloc(4LL * a2);\n } else {\n memcpy(v2, src, 4LL * (unsigned int)a2);\n v4 = (a2 >> 1) - 1;\n if (a2 >> 1) {\n do\n sub_1430(v3, (unsigned int)a2, v4);\n while (v4-- != 0);\n }\n v6 = a2 - 1;\n v7 = malloc(4LL * a2);\n v8 = v7;\n do {\n v9 = (unsigned int)v6;\n *v8++ = *v3;\n v10 = v3[v6--];\n *v3 = v10;\n sub_1430(v3, v9, 0LL);\n } while (v6 != -1);\n }\n free(v3);\n return v7;\n}", + "ida_pseudo_norm": "uint32_t *func0(void *src, int a2) {\n uint32_t *v2;\n uint32_t *v3;\n unsigned int v4;\n long long v6;\n uint32_t *v7;\n uint32_t *v8;\n long long v9;\n int v10;\n v2 = malloc(4LL * a2);\n v3 = v2;\n if (a2 <= 0) {\n v7 = malloc(4LL * a2);\n } else {\n memcpy(v2, src, 4LL * (unsigned int)a2);\n v4 = (a2 >> 1) - 1;\n if (a2 >> 1) {\n do\n min_heapify(v3, (unsigned int)a2, v4);\n while (v4-- != 0);\n }\n v6 = a2 - 1;\n v7 = malloc(4LL * a2);\n v8 = v7;\n do {\n v9 = (unsigned int)v6;\n *v8++ = *v3;\n v10 = v3[v6--];\n *v3 = v10;\n min_heapify(v3, v9, 0LL);\n } while (v6 != -1);\n }\n free(v3);\n return v7;\n}" + }, + { + "index": 372, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n// Function to maintain the min heap property\n\nvoid min_heapify(int* heap, int size, int i) {\n\n int smallest = i;\n\n int left = 2*i +1;\n\n int right = 2*i +2;\n\n\n\n if(left < size && heap[left] < heap[smallest])\n\n smallest = left;\n\n if(right < size && heap[right] < heap[smallest])\n\n smallest = right;\n\n if(smallest != i){\n\n int temp = heap[i];\n\n heap[i] = heap[smallest];\n\n heap[smallest] = temp;\n\n min_heapify(heap, size, smallest);\n\n }\n\n}\n\n\n\n", + "func": "int* func0(int* nums, int size) {\n int* heap = malloc(size * sizeof(int));\n for (int i = 0; i < size; i++) heap[i] = nums[i];\n for (int i = (size / 2) - 1; i >= 0; i--) min_heapify(heap, size, i);\n int* sorted = malloc(size * sizeof(int));\n int heap_size = size;\n for (int i = 0; i < size; i++) {\n sorted[i] = heap[0];\n heap[0] = heap[heap_size - 1];\n heap_size--;\n min_heapify(heap, heap_size, 0);\n }\n free(heap);\n return sorted;\n}", + "test": "int main() {\n\n // Test Case 1\n\n int test1[] = {18, 14, 10, 9, 8, 7, 9, 3, 2, 4, 1};\n\n int expected1[] = {1, 2, 3, 4, 7, 8, 9, 9, 10, 14, 18};\n\n int size1 = sizeof(test1)/sizeof(test1[0]);\n\n int* result1 = func0(test1, size1);\n\n for(int i=0; i\nsub $0x1,%ebx\nmov %rax,%rbp\ntest %r12d,%r12d\njle 16c8 \nlea -0x1(%r12),%eax\nmov %r15,%rsi\nmov %rbp,%rdi\nlea 0x4(,%rax,4),%rdx\nmov %rax,%r14\ncallq 10c0 \ntest %ebx,%ebx\njs 16e0 \nnopl 0x0(%rax)\nmov %ebx,%edx\nmov %r12d,%esi\nmov %rbp,%rdi\nsub $0x1,%ebx\ncallq 1550 \ncmp $0xffffffff,%ebx\njne 1648 \nmov %r13,%rdi\ncallq 10d0 \nmov %rax,%r15\ntest %r12d,%r12d\njle 16a9 \nlea -0x1(%r12),%r14d\nmovslq %r14d,%r14\nxor %r13d,%r13d\nnopl 0x0(%rax,%rax,1)\nmov 0x0(%rbp),%eax\nmov %r14d,%esi\nxor %edx,%edx\nmov %rbp,%rdi\nmov %eax,(%r15,%r13,4)\nmov 0x0(%rbp,%r14,4),%eax\nadd $0x1,%r13\nsub $0x1,%r14\nmov %eax,0x0(%rbp)\ncallq 1550 \ncmp %r13d,%r12d\njg 1680 \nmov %rbp,%rdi\ncallq 1090 \nadd $0x8,%rsp\nmov %r15,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax,%rax,1)\ntest %ebx,%ebx\njns 1648 \nmov %r13,%rdi\ncallq 10d0 \nmov %rax,%r15\njmp 16a9 \nnopl (%rax)\nmov %r13,%rdi\ncallq 10d0 \nmov %rax,%r15\njmp 1672 \nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r13\nmovsxd r13, esi\npush r12\nmov r12, rdi\npush rbp\npush rbx\nmov rbx, r13\nshl r13, 2\nmov rdi, r13; size\nsub rsp, 8\ncall _malloc\nmov rbp, rax\ntest ebx, ebx\njle loc_1590\nmov edx, ebx\nmov rsi, r12; src\nmov rdi, rax; dest\nshl rdx, 2; n\ncall _memcpy\nmov eax, ebx\nsar eax, 1\nlea r12d, [rax-1]\njz short loc_1533\nnop dword ptr [rax+00000000h]\nloc_1520:\nmov edx, r12d\nmov esi, ebx\nmov rdi, rbp\ncall min_heapify\nsub r12d, 1\njnb short loc_1520\nloc_1533:\nmov rdi, r13; size\nsub ebx, 1\ncall _malloc\nmovsxd rbx, ebx\nmov r13, rax\nmov r12, rax\nnop word ptr [rax+rax+00000000h]\nloc_1550:\nmov eax, [rbp+0]\nmov esi, ebx\nxor edx, edx\nmov rdi, rbp\nadd r12, 4\nmov [r12-4], eax\nmov eax, [rbp+rbx*4+0]\nsub rbx, 1\nmov [rbp+0], eax\ncall min_heapify\ncmp rbx, 0FFFFFFFFFFFFFFFFh\njnz short loc_1550\nloc_1579:\nmov rdi, rbp; ptr\ncall _free\nadd rsp, 8\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1590:\nmov rdi, r13; size\ncall _malloc\nmov r13, rax\njmp short loc_1579", + "ida_pseudo": "_DWORD *__fastcall func0(void *src, int a2)\n{\n _DWORD *v2; // rax\n _DWORD *v3; // rbp\n unsigned int v4; // r12d\n __int64 v6; // rbx\n _DWORD *v7; // r13\n _DWORD *v8; // r12\n __int64 v9; // rsi\n int v10; // eax\n\n v2 = malloc(4LL * a2);\n v3 = v2;\n if ( a2 <= 0 )\n {\n v7 = malloc(4LL * a2);\n }\n else\n {\n memcpy(v2, src, 4LL * (unsigned int)a2);\n v4 = (a2 >> 1) - 1;\n if ( a2 >> 1 )\n {\n do\n min_heapify(v3, (unsigned int)a2, v4);\n while ( v4-- != 0 );\n }\n v6 = a2 - 1;\n v7 = malloc(4LL * a2);\n v8 = v7;\n do\n {\n v9 = (unsigned int)v6;\n *v8++ = *v3;\n v10 = v3[v6--];\n *v3 = v10;\n min_heapify(v3, v9, 0LL);\n }\n while ( v6 != -1 );\n }\n free(v3);\n return v7;\n}", + "ida_strip_asm": "sub_14D0:\nendbr64\npush r13\nmovsxd r13, esi\npush r12\nmov r12, rdi\npush rbp\npush rbx\nmov rbx, r13\nshl r13, 2\nmov rdi, r13; size\nsub rsp, 8\ncall _malloc\nmov rbp, rax\ntest ebx, ebx\njle loc_1590\nmov edx, ebx\nmov rsi, r12; src\nmov rdi, rax; dest\nshl rdx, 2; n\ncall _memcpy\nmov eax, ebx\nsar eax, 1\nlea r12d, [rax-1]\njz short loc_1533\nnop dword ptr [rax+00000000h]\nloc_1520:\nmov edx, r12d\nmov esi, ebx\nmov rdi, rbp\ncall sub_1430\nsub r12d, 1\njnb short loc_1520\nloc_1533:\nmov rdi, r13; size\nsub ebx, 1\ncall _malloc\nmovsxd rbx, ebx\nmov r13, rax\nmov r12, rax\nnop word ptr [rax+rax+00000000h]\nloc_1550:\nmov eax, [rbp+0]\nmov esi, ebx\nxor edx, edx\nmov rdi, rbp\nadd r12, 4\nmov [r12-4], eax\nmov eax, [rbp+rbx*4+0]\nsub rbx, 1\nmov [rbp+0], eax\ncall sub_1430\ncmp rbx, 0FFFFFFFFFFFFFFFFh\njnz short loc_1550\nloc_1579:\nmov rdi, rbp; ptr\ncall _free\nadd rsp, 8\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1590:\nmov rdi, r13; size\ncall _malloc\nmov r13, rax\njmp short loc_1579", + "ida_strip_pseudo": "_DWORD *__fastcall sub_14D0(void *src, int a2)\n{\n _DWORD *v2; // rax\n _DWORD *v3; // rbp\n unsigned int v4; // r12d\n __int64 v6; // rbx\n _DWORD *v7; // r13\n _DWORD *v8; // r12\n __int64 v9; // rsi\n int v10; // eax\n\n v2 = malloc(4LL * a2);\n v3 = v2;\n if ( a2 <= 0 )\n {\n v7 = malloc(4LL * a2);\n }\n else\n {\n memcpy(v2, src, 4LL * (unsigned int)a2);\n v4 = (a2 >> 1) - 1;\n if ( a2 >> 1 )\n {\n do\n sub_1430(v3, (unsigned int)a2, v4);\n while ( v4-- != 0 );\n }\n v6 = a2 - 1;\n v7 = malloc(4LL * a2);\n v8 = v7;\n do\n {\n v9 = (unsigned int)v6;\n *v8++ = *v3;\n v10 = v3[v6--];\n *v3 = v10;\n sub_1430(v3, v9, 0LL);\n }\n while ( v6 != -1 );\n }\n free(v3);\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_14D0(void *src, int a2) {\n uint32_t *v2;\n uint32_t *v3;\n unsigned int v4;\n long long v6;\n uint32_t *v7;\n uint32_t *v8;\n long long v9;\n int v10;\n v2 = malloc(4LL * a2);\n v3 = v2;\n if (a2 <= 0) {\n v7 = malloc(4LL * a2);\n } else {\n memcpy(v2, src, 4LL * (unsigned int)a2);\n v4 = (a2 >> 1) - 1;\n if (a2 >> 1) {\n do\n sub_1430(v3, (unsigned int)a2, v4);\n while (v4-- != 0);\n }\n v6 = a2 - 1;\n v7 = malloc(4LL * a2);\n v8 = v7;\n do {\n v9 = (unsigned int)v6;\n *v8++ = *v3;\n v10 = v3[v6--];\n *v3 = v10;\n sub_1430(v3, v9, 0LL);\n } while (v6 != -1);\n }\n free(v3);\n return v7;\n}", + "ida_pseudo_norm": "uint32_t *func0(void *src, int a2) {\n uint32_t *v2;\n uint32_t *v3;\n unsigned int v4;\n long long v6;\n uint32_t *v7;\n uint32_t *v8;\n long long v9;\n int v10;\n v2 = malloc(4LL * a2);\n v3 = v2;\n if (a2 <= 0) {\n v7 = malloc(4LL * a2);\n } else {\n memcpy(v2, src, 4LL * (unsigned int)a2);\n v4 = (a2 >> 1) - 1;\n if (a2 >> 1) {\n do\n min_heapify(v3, (unsigned int)a2, v4);\n while (v4-- != 0);\n }\n v6 = a2 - 1;\n v7 = malloc(4LL * a2);\n v8 = v7;\n do {\n v9 = (unsigned int)v6;\n *v8++ = *v3;\n v10 = v3[v6--];\n *v3 = v10;\n min_heapify(v3, v9, 0LL);\n } while (v6 != -1);\n }\n free(v3);\n return v7;\n}" + }, + { + "index": 373, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int l, int w, int h) {\n int volume = l * w * h;\n return volume;\n}", + "test": "int main() {\n\n assert(func0(1, 2, 3) == 6);\n\n assert(func0(5, 7, 9) == 315);\n\n assert(func0(10, 15, 21) == 3150);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov %edx,-0x1c(%rbp)\nmov -0x14(%rbp),%eax\nimul -0x18(%rbp),%eax\nmov -0x1c(%rbp),%edx\nimul %edx,%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov eax, [rbp+var_14]\nimul eax, [rbp+var_18]\nmov edx, [rbp+var_1C]\nimul eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, int a3)\n{\n return (unsigned int)(a3 * a2 * a1);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov eax, [rbp+var_14]\nimul eax, [rbp+var_18]\nmov edx, [rbp+var_1C]\nimul eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2, int a3)\n{\n return (unsigned int)(a3 * a2 * a1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2, int a3) {\n return (unsigned int)(a3 * a2 * a1);\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, int a3) { return (unsigned int)(a3 * a2 * a1); }" + }, + { + "index": 374, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(const char *str, char **result, int *index) {\n int len = strlen(str);\n if (len == 0) {\n result[*index] = strdup(\"\");\n (*index)++;\n return;\n }\n char **prev_list = malloc(40320 * sizeof(char *));\n int prev_index = 0;\n func0(str + 1, prev_list, &prev_index);\n int i, j, k;\n for (i = 0; i < prev_index; i++) {\n for (j = 0; j <= strlen(prev_list[i]); j++) {\n char *new_str = malloc((len + 1) * sizeof(char));\n strncpy(new_str, prev_list[i], j);\n new_str[j] = str[0];\n strcpy(new_str + j + 1, prev_list[i] + j);\n int found = 0;\n for (k = 0; k < *index; k++) {\n if (strcmp(result[k], new_str) == 0) {\n found = 1;\n break;\n }\n }\n if (!found) {\n result[*index] = new_str;\n (*index)++;\n } else {\n free(new_str);\n }\n }\n }\n for (i = 0; i < prev_index; i++) {\n free(prev_list[i]);\n }\n free(prev_list);\n}", + "test": "int main() {\n\n char *result[100];\n\n int index;\n\n\n\n index = 0;\n\n func0(\"ab\", result, &index);\n\n assert(strcmp(result[0], \"ab\") == 0 && strcmp(result[1], \"ba\") == 0 && index == 2);\n\n\n\n index = 0;\n\n func0(\"abc\", result, &index);\n\n assert(strcmp(result[0], \"abc\") == 0 && strcmp(result[1], \"bac\") == 0 && strcmp(result[2], \"bca\") == 0 &&\n\n strcmp(result[3], \"acb\") == 0 && strcmp(result[4], \"cab\") == 0 && strcmp(result[5], \"cba\") == 0 && index == 6);\n\n\n\n index = 0;\n\n func0(\"abcd\", result, &index);\n\n assert(index == 24);\n\n \n\n // Clean up allocated memory\n\n for (int i = 0; i < index; i++) {\n\n free(result[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x58,%rsp\nmov %rdi,-0x48(%rbp)\nmov %rsi,-0x50(%rbp)\nmov %rdx,-0x58(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmov -0x48(%rbp),%rax\nmov %rax,%rdi\ncallq 1100 \nmov %eax,-0x2c(%rbp)\ncmpl $0x0,-0x2c(%rbp)\njne 12c1 \nmov -0x58(%rbp),%rax\nmov (%rax),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x50(%rbp),%rax\nlea (%rdx,%rax,1),%rbx\nlea 0xd63(%rip),%rdi\ncallq 1150 \nmov %rax,(%rbx)\nmov -0x58(%rbp),%rax\nmov (%rax),%eax\nlea 0x1(%rax),%edx\nmov -0x58(%rbp),%rax\nmov %edx,(%rax)\njmpq 14ae \nmov $0x4ec00,%edi\ncallq 1140 \nmov %rax,-0x28(%rbp)\nmovl $0x0,-0x40(%rbp)\nmov -0x48(%rbp),%rax\nlea 0x1(%rax),%rcx\nlea -0x40(%rbp),%rdx\nmov -0x28(%rbp),%rax\nmov %rax,%rsi\nmov %rcx,%rdi\ncallq 1249 \nmovl $0x0,-0x3c(%rbp)\njmpq 1462 \nmovl $0x0,-0x38(%rbp)\njmpq 1430 \nmov -0x2c(%rbp),%eax\nadd $0x1,%eax\ncltq\nmov %rax,%rdi\ncallq 1140 \nmov %rax,-0x20(%rbp)\nmov -0x38(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x3c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%rcx\nmov -0x20(%rbp),%rax\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 10e0 \nmov -0x38(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x20(%rbp),%rax\nadd %rax,%rdx\nmov -0x48(%rbp),%rax\nmovzbl (%rax),%eax\nmov %al,(%rdx)\nmov -0x3c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rdx\nmov -0x38(%rbp),%eax\ncltq\nadd %rax,%rdx\nmov -0x38(%rbp),%eax\ncltq\nlea 0x1(%rax),%rcx\nmov -0x20(%rbp),%rax\nadd %rcx,%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10f0 \nmovl $0x0,-0x30(%rbp)\nmovl $0x0,-0x34(%rbp)\njmp 13e0 \nmov -0x34(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x50(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0x20(%rbp),%rdx\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1130 \ntest %eax,%eax\njne 13dc \nmovl $0x1,-0x30(%rbp)\njmp 13eb \naddl $0x1,-0x34(%rbp)\nmov -0x58(%rbp),%rax\nmov (%rax),%eax\ncmp %eax,-0x34(%rbp)\njl 13a9 \ncmpl $0x0,-0x30(%rbp)\njne 1420 \nmov -0x58(%rbp),%rax\nmov (%rax),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x50(%rbp),%rax\nadd %rax,%rdx\nmov -0x20(%rbp),%rax\nmov %rax,(%rdx)\nmov -0x58(%rbp),%rax\nmov (%rax),%eax\nlea 0x1(%rax),%edx\nmov -0x58(%rbp),%rax\nmov %edx,(%rax)\njmp 142c \nmov -0x20(%rbp),%rax\nmov %rax,%rdi\ncallq 10d0 \naddl $0x1,-0x38(%rbp)\nmov -0x38(%rbp),%eax\nmovslq %eax,%rbx\nmov -0x3c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov %rax,%rdi\ncallq 1100 \ncmp %rax,%rbx\njbe 1309 \naddl $0x1,-0x3c(%rbp)\nmov -0x40(%rbp),%eax\ncmp %eax,-0x3c(%rbp)\njl 12fd \nmovl $0x0,-0x3c(%rbp)\njmp 149a \nmov -0x3c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov %rax,%rdi\ncallq 10d0 \naddl $0x1,-0x3c(%rbp)\nmov -0x40(%rbp),%eax\ncmp %eax,-0x3c(%rbp)\njl 1477 \nmov -0x28(%rbp),%rax\nmov %rax,%rdi\ncallq 10d0 \nmov -0x18(%rbp),%rax\nxor %fs:0x28,%rax\nje 14c2 \ncallq 1110 <__stack_chk_fail@plt>\nadd $0x58,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 58h\nmov [rbp+s], rdi\nmov [rbp+var_50], rsi\nmov [rbp+var_58], rdx\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_2C], eax\ncmp [rbp+var_2C], 0\njnz short loc_12C4\nmov rax, [rbp+var_58]\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_50]\nlea rbx, [rdx+rax]\nlea rax, s\nmov rdi, rax; s\ncall _strdup\nmov [rbx], rax\nmov rax, [rbp+var_58]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_58]\nmov [rax], edx\njmp loc_14B1\nloc_12C4:\nmov edi, 4EC00h; size\ncall _malloc\nmov [rbp+ptr], rax\nmov [rbp+var_40], 0\nmov rax, [rbp+s]\nlea rcx, [rax+1]\nlea rdx, [rbp+var_40]\nmov rax, [rbp+ptr]\nmov rsi, rax\nmov rdi, rcx\ncall func0\nmov [rbp+var_3C], 0\njmp loc_1465\nloc_1300:\nmov [rbp+var_38], 0\njmp loc_1433\nloc_130C:\nmov eax, [rbp+var_2C]\nadd eax, 1\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+dest], rax\nmov eax, [rbp+var_38]\nmovsxd rdx, eax; n\nmov eax, [rbp+var_3C]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rcx\nmov rcx, [rax]\nmov rax, [rbp+dest]\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strncpy\nmov eax, [rbp+var_38]\nmovsxd rdx, eax\nmov rax, [rbp+dest]\nadd rdx, rax\nmov rax, [rbp+s]\nmovzx eax, byte ptr [rax]\nmov [rdx], al\nmov eax, [rbp+var_3C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_38]\ncdqe\nadd rdx, rax\nmov eax, [rbp+var_38]\ncdqe\nlea rcx, [rax+1]\nmov rax, [rbp+dest]\nadd rax, rcx\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\nmov [rbp+var_30], 0\nmov [rbp+var_34], 0\njmp short loc_13E3\nloc_13AC:\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_50]\nadd rax, rdx\nmov rax, [rax]\nmov rdx, [rbp+dest]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_13DF\nmov [rbp+var_30], 1\njmp short loc_13EE\nloc_13DF:\nadd [rbp+var_34], 1\nloc_13E3:\nmov rax, [rbp+var_58]\nmov eax, [rax]\ncmp [rbp+var_34], eax\njl short loc_13AC\nloc_13EE:\ncmp [rbp+var_30], 0\njnz short loc_1423\nmov rax, [rbp+var_58]\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_50]\nadd rdx, rax\nmov rax, [rbp+dest]\nmov [rdx], rax\nmov rax, [rbp+var_58]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_58]\nmov [rax], edx\njmp short loc_142F\nloc_1423:\nmov rax, [rbp+dest]\nmov rdi, rax; ptr\ncall _free\nloc_142F:\nadd [rbp+var_38], 1\nloc_1433:\nmov eax, [rbp+var_38]\nmovsxd rbx, eax\nmov eax, [rbp+var_3C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; s\ncall _strlen\ncmp rax, rbx\njnb loc_130C\nadd [rbp+var_3C], 1\nloc_1465:\nmov eax, [rbp+var_40]\ncmp [rbp+var_3C], eax\njl loc_1300\nmov [rbp+var_3C], 0\njmp short loc_149D\nloc_147A:\nmov eax, [rbp+var_3C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; ptr\ncall _free\nadd [rbp+var_3C], 1\nloc_149D:\nmov eax, [rbp+var_40]\ncmp [rbp+var_3C], eax\njl short loc_147A\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nloc_14B1:\nmov rax, [rbp+var_18]\nsub rax, fs:28h\njz short loc_14C5\ncall ___stack_chk_fail\nloc_14C5:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "unsigned __int64 __fastcall func0(const char *a1, __int64 a2, int *a3)\n{\n char **v3; // rbx\n size_t v4; // rbx\n int v7; // [rsp+20h] [rbp-40h] BYREF\n int i; // [rsp+24h] [rbp-3Ch]\n int j; // [rsp+28h] [rbp-38h]\n int k; // [rsp+2Ch] [rbp-34h]\n int v11; // [rsp+30h] [rbp-30h]\n int v12; // [rsp+34h] [rbp-2Ch]\n void *ptr; // [rsp+38h] [rbp-28h]\n char *dest; // [rsp+40h] [rbp-20h]\n unsigned __int64 v15; // [rsp+48h] [rbp-18h]\n\n v15 = __readfsqword(0x28u);\n v12 = strlen(a1);\n if ( v12 )\n {\n ptr = malloc(0x4EC00uLL);\n v7 = 0;\n func0(a1 + 1, ptr, &v7);\n for ( i = 0; i < v7; ++i )\n {\n for ( j = 0; ; ++j )\n {\n v4 = j;\n if ( strlen(*((const char **)ptr + i)) < v4 )\n break;\n dest = (char *)malloc(v12 + 1);\n strncpy(dest, *((const char **)ptr + i), j);\n dest[j] = *a1;\n strcpy(&dest[j + 1], (const char *)(j + *((_QWORD *)ptr + i)));\n v11 = 0;\n for ( k = 0; k < *a3; ++k )\n {\n if ( !strcmp(*(const char **)(8LL * k + a2), dest) )\n {\n v11 = 1;\n break;\n }\n }\n if ( v11 )\n free(dest);\n else\n *(_QWORD *)(a2 + 8LL * (*a3)++) = dest;\n }\n }\n for ( i = 0; i < v7; ++i )\n free(*((void **)ptr + i));\n free(ptr);\n }\n else\n {\n v3 = (char **)(8LL * *a3 + a2);\n *v3 = strdup(&s);\n ++*a3;\n }\n return v15 - __readfsqword(0x28u);\n}", + "ida_strip_asm": "sub_1249:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 58h\nmov [rbp+s], rdi\nmov [rbp+var_50], rsi\nmov [rbp+var_58], rdx\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_2C], eax\ncmp [rbp+var_2C], 0\njnz short loc_12C4\nmov rax, [rbp+var_58]\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_50]\nlea rbx, [rdx+rax]\nlea rax, s\nmov rdi, rax; s\ncall _strdup\nmov [rbx], rax\nmov rax, [rbp+var_58]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_58]\nmov [rax], edx\njmp loc_14B1\nloc_12C4:\nmov edi, 4EC00h; size\ncall _malloc\nmov [rbp+ptr], rax\nmov [rbp+var_40], 0\nmov rax, [rbp+s]\nlea rcx, [rax+1]\nlea rdx, [rbp+var_40]\nmov rax, [rbp+ptr]\nmov rsi, rax\nmov rdi, rcx\ncall sub_1249\nmov [rbp+var_3C], 0\njmp loc_1465\nloc_1300:\nmov [rbp+var_38], 0\njmp loc_1433\nloc_130C:\nmov eax, [rbp+var_2C]\nadd eax, 1\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+dest], rax\nmov eax, [rbp+var_38]\nmovsxd rdx, eax; n\nmov eax, [rbp+var_3C]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rcx\nmov rcx, [rax]\nmov rax, [rbp+dest]\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strncpy\nmov eax, [rbp+var_38]\nmovsxd rdx, eax\nmov rax, [rbp+dest]\nadd rdx, rax\nmov rax, [rbp+s]\nmovzx eax, byte ptr [rax]\nmov [rdx], al\nmov eax, [rbp+var_3C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_38]\ncdqe\nadd rdx, rax\nmov eax, [rbp+var_38]\ncdqe\nlea rcx, [rax+1]\nmov rax, [rbp+dest]\nadd rax, rcx\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\nmov [rbp+var_30], 0\nmov [rbp+var_34], 0\njmp short loc_13E3\nloc_13AC:\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_50]\nadd rax, rdx\nmov rax, [rax]\nmov rdx, [rbp+dest]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_13DF\nmov [rbp+var_30], 1\njmp short loc_13EE\nloc_13DF:\nadd [rbp+var_34], 1\nloc_13E3:\nmov rax, [rbp+var_58]\nmov eax, [rax]\ncmp [rbp+var_34], eax\njl short loc_13AC\nloc_13EE:\ncmp [rbp+var_30], 0\njnz short loc_1423\nmov rax, [rbp+var_58]\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_50]\nadd rdx, rax\nmov rax, [rbp+dest]\nmov [rdx], rax\nmov rax, [rbp+var_58]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_58]\nmov [rax], edx\njmp short loc_142F\nloc_1423:\nmov rax, [rbp+dest]\nmov rdi, rax; ptr\ncall _free\nloc_142F:\nadd [rbp+var_38], 1\nloc_1433:\nmov eax, [rbp+var_38]\nmovsxd rbx, eax\nmov eax, [rbp+var_3C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; s\ncall _strlen\ncmp rax, rbx\njnb loc_130C\nadd [rbp+var_3C], 1\nloc_1465:\nmov eax, [rbp+var_40]\ncmp [rbp+var_3C], eax\njl loc_1300\nmov [rbp+var_3C], 0\njmp short loc_149D\nloc_147A:\nmov eax, [rbp+var_3C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; ptr\ncall _free\nadd [rbp+var_3C], 1\nloc_149D:\nmov eax, [rbp+var_40]\ncmp [rbp+var_3C], eax\njl short loc_147A\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nloc_14B1:\nmov rax, [rbp+var_18]\nsub rax, fs:28h\njz short loc_14C5\ncall ___stack_chk_fail\nloc_14C5:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_1249(const char *a1, __int64 a2, int *a3)\n{\n char **v3; // rbx\n size_t v4; // rbx\n int v7; // [rsp+20h] [rbp-40h] BYREF\n int i; // [rsp+24h] [rbp-3Ch]\n int j; // [rsp+28h] [rbp-38h]\n int k; // [rsp+2Ch] [rbp-34h]\n int v11; // [rsp+30h] [rbp-30h]\n int v12; // [rsp+34h] [rbp-2Ch]\n void *ptr; // [rsp+38h] [rbp-28h]\n char *dest; // [rsp+40h] [rbp-20h]\n unsigned __int64 v15; // [rsp+48h] [rbp-18h]\n\n v15 = __readfsqword(0x28u);\n v12 = strlen(a1);\n if ( v12 )\n {\n ptr = malloc(0x4EC00uLL);\n v7 = 0;\n sub_1249(a1 + 1, ptr, &v7);\n for ( i = 0; i < v7; ++i )\n {\n for ( j = 0; ; ++j )\n {\n v4 = j;\n if ( strlen(*((const char **)ptr + i)) < v4 )\n break;\n dest = (char *)malloc(v12 + 1);\n strncpy(dest, *((const char **)ptr + i), j);\n dest[j] = *a1;\n strcpy(&dest[j + 1], (const char *)(j + *((_QWORD *)ptr + i)));\n v11 = 0;\n for ( k = 0; k < *a3; ++k )\n {\n if ( !strcmp(*(const char **)(8LL * k + a2), dest) )\n {\n v11 = 1;\n break;\n }\n }\n if ( v11 )\n free(dest);\n else\n *(_QWORD *)(a2 + 8LL * (*a3)++) = dest;\n }\n }\n for ( i = 0; i < v7; ++i )\n free(*((void **)ptr + i));\n free(ptr);\n }\n else\n {\n v3 = (char **)(8LL * *a3 + a2);\n *v3 = strdup(&s);\n ++*a3;\n }\n return v15 - __readfsqword(0x28u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_1249(const char *a1, long long a2, int *a3) {\n char **v3;\n unsigned int v4;\n int v7;\n int i;\n int j;\n int k;\n int v11;\n int v12;\n void *ptr;\n char *dest;\n unsigned long long v15;\n v15 = __readfsqword(40u);\n v12 = strlen(a1);\n if (v12) {\n ptr = malloc(322560uLL);\n v7 = 0;\n sub_1249(a1 + 1, ptr, &v7);\n for (i = 0; i < v7; ++i) {\n for (j = 0;; ++j) {\n v4 = j;\n if (strlen(*((const char **)ptr + i)) < v4) break;\n dest = (char *)malloc(v12 + 1);\n strncpy(dest, *((const char **)ptr + i), j);\n dest[j] = *a1;\n strcpy(&dest[j + 1], (const char *)(j + *((uint64_t *)ptr + i)));\n v11 = 0;\n for (k = 0; k < *a3; ++k) {\n if (!strcmp(*(const char **)(8LL * k + a2), dest)) {\n v11 = 1;\n break;\n }\n }\n if (v11)\n free(dest);\n else\n *(uint64_t *)(a2 + 8LL * (*a3)++) = dest;\n }\n }\n for (i = 0; i < v7; ++i) free(*((void **)ptr + i));\n free(ptr);\n } else {\n v3 = (char **)(8LL * *a3 + a2);\n *v3 = strdup(&s);\n ++*a3;\n }\n return v15 - __readfsqword(40u);\n}", + "ida_pseudo_norm": "unsigned long long func0(const char *a1, long long a2, int *a3) {\n char **v3;\n unsigned int v4;\n int v7;\n int i;\n int j;\n int k;\n int v11;\n int v12;\n void *ptr;\n char *dest;\n unsigned long long v15;\n v15 = __readfsqword(40u);\n v12 = strlen(a1);\n if (v12) {\n ptr = malloc(322560uLL);\n v7 = 0;\n func0(a1 + 1, ptr, &v7);\n for (i = 0; i < v7; ++i) {\n for (j = 0;; ++j) {\n v4 = j;\n if (strlen(*((const char **)ptr + i)) < v4) break;\n dest = (char *)malloc(v12 + 1);\n strncpy(dest, *((const char **)ptr + i), j);\n dest[j] = *a1;\n strcpy(&dest[j + 1], (const char *)(j + *((uint64_t *)ptr + i)));\n v11 = 0;\n for (k = 0; k < *a3; ++k) {\n if (!strcmp(*(const char **)(8LL * k + a2), dest)) {\n v11 = 1;\n break;\n }\n }\n if (v11)\n free(dest);\n else\n *(uint64_t *)(a2 + 8LL * (*a3)++) = dest;\n }\n }\n for (i = 0; i < v7; ++i) free(*((void **)ptr + i));\n free(ptr);\n } else {\n v3 = (char **)(8LL * *a3 + a2);\n *v3 = strdup(&s);\n ++*a3;\n }\n return v15 - __readfsqword(40u);\n}" + }, + { + "index": 374, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(const char *str, char **result, int *index) {\n int len = strlen(str);\n if (len == 0) {\n result[*index] = strdup(\"\");\n (*index)++;\n return;\n }\n char **prev_list = malloc(40320 * sizeof(char *));\n int prev_index = 0;\n func0(str + 1, prev_list, &prev_index);\n int i, j, k;\n for (i = 0; i < prev_index; i++) {\n for (j = 0; j <= strlen(prev_list[i]); j++) {\n char *new_str = malloc((len + 1) * sizeof(char));\n strncpy(new_str, prev_list[i], j);\n new_str[j] = str[0];\n strcpy(new_str + j + 1, prev_list[i] + j);\n int found = 0;\n for (k = 0; k < *index; k++) {\n if (strcmp(result[k], new_str) == 0) {\n found = 1;\n break;\n }\n }\n if (!found) {\n result[*index] = new_str;\n (*index)++;\n } else {\n free(new_str);\n }\n }\n }\n for (i = 0; i < prev_index; i++) {\n free(prev_list[i]);\n }\n free(prev_list);\n}", + "test": "int main() {\n\n char *result[100];\n\n int index;\n\n\n\n index = 0;\n\n func0(\"ab\", result, &index);\n\n assert(strcmp(result[0], \"ab\") == 0 && strcmp(result[1], \"ba\") == 0 && index == 2);\n\n\n\n index = 0;\n\n func0(\"abc\", result, &index);\n\n assert(strcmp(result[0], \"abc\") == 0 && strcmp(result[1], \"bac\") == 0 && strcmp(result[2], \"bca\") == 0 &&\n\n strcmp(result[3], \"acb\") == 0 && strcmp(result[4], \"cab\") == 0 && strcmp(result[5], \"cba\") == 0 && index == 6);\n\n\n\n index = 0;\n\n func0(\"abcd\", result, &index);\n\n assert(index == 24);\n\n \n\n // Clean up allocated memory\n\n for (int i = 0; i < index; i++) {\n\n free(result[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x58,%rsp\nmov %rdi,0x18(%rsp)\nmov %rsi,0x10(%rsp)\nmov %rdx,0x8(%rsp)\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov $0xffffffffffffffff,%rcx\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nsub $0x1,%rax\ntest %eax,%eax\nje 12c8 \nmov %eax,%ebx\nmov $0x4ec00,%edi\ncallq 1120 \nmov %rax,%r15\nmov %rax,0x38(%rsp)\nmovl $0x0,0x44(%rsp)\nlea 0x44(%rsp),%rdx\nmov 0x18(%rsp),%rcx\nlea 0x1(%rcx),%rdi\nmov %rax,%rsi\ncallq 1229 \ncmpl $0x0,0x44(%rsp)\njle 1332 \nmov %r15,0x30(%rsp)\nmovl $0x0,0x2c(%rsp)\nadd $0x1,%ebx\nmovslq %ebx,%rax\nmov %rax,0x20(%rsp)\njmp 12fe \nmov %rdx,%r15\nmovslq (%rdx),%rax\nlea (%rsi,%rax,8),%rbx\nlea 0xd53(%rip),%rdi\ncallq 1130 \nmov %rax,(%rbx)\naddl $0x1,(%r15)\njmp 133c \naddl $0x1,0x2c(%rsp)\nmov 0x2c(%rsp),%edx\nmov 0x44(%rsp),%eax\naddq $0x8,0x30(%rsp)\ncmp %edx,%eax\njle 1311 \nmov 0x30(%rsp),%rax\nmov (%rax),%r15\nmov $0x0,%r13d\njmpq 1397 \ntest %eax,%eax\njle 1332 \nmov $0x0,%ebx\nmov 0x38(%rsp),%rax\nmov (%rax,%rbx,8),%rdi\ncallq 10c0 \nadd $0x1,%rbx\ncmp %ebx,0x44(%rsp)\njg 131a \nmov 0x38(%rsp),%rdi\ncallq 10c0 \nmov 0x48(%rsp),%rax\nxor %fs:0x28,%rax\njne 1419 \nadd $0x58,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmovslq %r14d,%r14\nmov 0x10(%rsp),%rax\nmov %rbp,(%rax,%r14,8)\nmov 0x8(%rsp),%rax\naddl $0x1,(%rax)\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nmov %r15,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nsub $0x1,%rax\ncmp %r13,%rax\njb 12e7 \nmov 0x20(%rsp),%rdi\ncallq 1120 \nmov %rax,%rbp\nmov %r13,%rdx\nmov %r15,%rsi\nmov %rax,%rdi\ncallq 10d0 \nmov 0x18(%rsp),%rax\nmovzbl (%rax),%eax\nmov %al,0x0(%rbp,%r13,1)\nlea (%r15,%r13,1),%rsi\nadd $0x1,%r13\nlea 0x0(%rbp,%r13,1),%rdi\ncallq 10e0 \nmov 0x8(%rsp),%rax\nmov (%rax),%r14d\ntest %r14d,%r14d\njle 135f \nmov 0x10(%rsp),%rdx\nmov %rdx,%rbx\nlea -0x1(%r14),%eax\nlea 0x8(%rdx,%rax,8),%r12\nmov %rbp,%rsi\nmov (%rbx),%rdi\ncallq 1110 \ntest %eax,%eax\nje 140c \nadd $0x8,%rbx\ncmp %rbx,%r12\njne 13ef \njmpq 135f \nmov %rbp,%rdi\ncallq 10c0 \njmpq 1373 \ncallq 10f0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 48h\nmov [rsp+78h+var_70], rdi\nmov r14, rsi\nmov r15, rdx\nmov rax, fs:28h\nmov [rsp+78h+var_40], rax\nxor eax, eax\ncall _strlen\ntest eax, eax\njz short loc_12DE\nmov ebx, eax\nmov edi, 4EC00h; size\ncall _malloc\nmov rbp, rax\nmov [rsp+78h+var_44], 0\nlea rdx, [rsp+78h+var_44]\nmov rax, [rsp+78h+var_70]\nlea rdi, [rax+1]; s\nmov rsi, rbp\ncall func0\nmov eax, [rsp+78h+var_44]\ntest eax, eax\njle loc_13E3\ncdqe\nlea r13, [rbp+rax*8+0]\nmov [rsp+78h+var_78], rbp\nlea eax, [rbx+1]\nmov [rsp+78h+var_64], eax\nmov [rsp+78h+var_58], rbp\nmov [rsp+78h+var_50], rbp\nmov [rsp+78h+var_60], r13\njmp loc_13B7\nloc_12DE:\nmovsxd rax, dword ptr [r15]\nlea rbx, [r14+rax*8]\nlea rdi, aIndex24+0Bh; s\ncall _strdup\nmov [rbx], rax\nadd dword ptr [r15], 1\njmp loc_13EB\nloc_12FD:\nmovsxd rdx, edx\nmov [r14+rdx*8], rbp\nadd dword ptr [r15], 1\nloc_1308:\nmov rax, [rsp+78h+var_78]\nmov r13, [rax]\nmov rdi, r13; s\ncall _strlen\ncmp rax, r12\njb loc_13A4\nmovsxd rbx, [rsp+78h+var_64]\nmov rdi, rbx; size\ncall _malloc\nmov rbp, rax\nmov rcx, rbx\nmov rdx, r12\nmov rsi, r13\nmov rdi, rax\ncall ___strncpy_chk\nmov rax, [rsp+78h+var_70]\nmovzx eax, byte ptr [rax]\nmov [rbp+r12+0], al\nlea rsi, [r13+r12+0]\nadd r12, 1\ncmp rbx, r12\nmov rdx, rbx\ncmovb rdx, r12\nsub rdx, r12\nlea rdi, [rbp+r12+0]\ncall ___strcpy_chk\nmov edx, [r15]\ntest edx, edx\njle short loc_12FD\nmov rbx, r14\nmovsxd rax, edx\nlea r13, [r14+rax*8]\nmov [rsp+78h+var_68], edx\nloc_1383:\nmov rdi, [rbx]; s1\nmov rsi, rbp; s2\ncall _strcmp\ntest eax, eax\njz short loc_140A\nadd rbx, 8\ncmp rbx, r13\njnz short loc_1383\nmov edx, [rsp+78h+var_68]\njmp loc_12FD\nloc_13A4:\nadd [rsp+78h+var_78], 8\nmov rax, [rsp+78h+var_78]\nmov rcx, [rsp+78h+var_60]\ncmp rax, rcx\njz short loc_13C2\nloc_13B7:\nmov r12d, 0\njmp loc_1308\nloc_13C2:\nmov r12, [rsp+78h+var_58]\nmov rbp, [rsp+78h+var_50]\nmov r13, [rsp+78h+var_60]\nloc_13D1:\nmov rdi, [r12]; ptr\ncall _free\nadd r12, 8\ncmp r12, r13\njnz short loc_13D1\nloc_13E3:\nmov rdi, rbp; ptr\ncall _free\nloc_13EB:\nmov rax, [rsp+78h+var_40]\nsub rax, fs:28h\njnz short loc_1417\nadd rsp, 48h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_140A:\nmov rdi, rbp; ptr\ncall _free\njmp loc_1308\nloc_1417:\ncall ___stack_chk_fail", + "ida_pseudo": "unsigned __int64 __fastcall func0(const char *a1, const char **a2, int *a3)\n{\n int v5; // eax\n int v6; // ebx\n const char **v7; // rbp\n char **v8; // rbx\n const char *v9; // r13\n char *v10; // rbp\n const char *v11; // rsi\n size_t v12; // r12\n size_t v13; // rdx\n int v14; // edx\n const char **v15; // rbx\n const char **v16; // r13\n void **v17; // r12\n const char **v19; // [rsp+0h] [rbp-78h]\n int v20; // [rsp+10h] [rbp-68h]\n int v21; // [rsp+14h] [rbp-64h]\n const char **v22; // [rsp+18h] [rbp-60h]\n void **v23; // [rsp+20h] [rbp-58h]\n const char **v24; // [rsp+28h] [rbp-50h]\n int v25; // [rsp+34h] [rbp-44h] BYREF\n unsigned __int64 v26; // [rsp+38h] [rbp-40h]\n\n v26 = __readfsqword(0x28u);\n v5 = strlen(a1);\n if ( v5 )\n {\n v6 = v5;\n v7 = (const char **)malloc(0x4EC00uLL);\n v25 = 0;\n func0(a1 + 1, v7, &v25);\n if ( v25 > 0 )\n {\n v19 = v7;\n v21 = v6 + 1;\n v23 = (void **)v7;\n v24 = v7;\n v22 = &v7[v25];\n do\n {\n v12 = 0LL;\n while ( 1 )\n {\n v9 = *v19;\n if ( strlen(*v19) < v12 )\n break;\n v10 = (char *)malloc(v21);\n __strncpy_chk(v10, v9, v12, v21);\n v10[v12] = *a1;\n v11 = &v9[v12++];\n v13 = v21;\n if ( v21 < v12 )\n v13 = v12;\n __strcpy_chk(&v10[v12], v11, v13 - v12);\n v14 = *a3;\n if ( *a3 <= 0 )\n {\nLABEL_5:\n a2[v14] = v10;\n ++*a3;\n }\n else\n {\n v15 = a2;\n v16 = &a2[v14];\n v20 = *a3;\n while ( strcmp(*v15, v10) )\n {\n if ( ++v15 == v16 )\n {\n v14 = v20;\n goto LABEL_5;\n }\n }\n free(v10);\n }\n }\n ++v19;\n }\n while ( v19 != v22 );\n v17 = v23;\n v7 = v24;\n do\n free(*v17++);\n while ( v17 != (void **)v22 );\n }\n free(v7);\n }\n else\n {\n v8 = (char **)&a2[*a3];\n *v8 = strdup(\"\");\n ++*a3;\n }\n return v26 - __readfsqword(0x28u);\n}", + "ida_strip_asm": "sub_1249:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 48h\nmov [rsp+78h+var_70], rdi\nmov r14, rsi\nmov r15, rdx\nmov rax, fs:28h\nmov [rsp+78h+var_40], rax\nxor eax, eax\ncall _strlen\ntest eax, eax\njz short loc_12DE\nmov ebx, eax\nmov edi, 4EC00h; size\ncall _malloc\nmov rbp, rax\nmov [rsp+78h+var_44], 0\nlea rdx, [rsp+78h+var_44]\nmov rax, [rsp+78h+var_70]\nlea rdi, [rax+1]; s\nmov rsi, rbp\ncall sub_1249\nmov eax, [rsp+78h+var_44]\ntest eax, eax\njle loc_13E3\ncdqe\nlea r13, [rbp+rax*8+0]\nmov [rsp+78h+var_78], rbp\nlea eax, [rbx+1]\nmov [rsp+78h+var_64], eax\nmov [rsp+78h+var_58], rbp\nmov [rsp+78h+var_50], rbp\nmov [rsp+78h+var_60], r13\njmp loc_13B7\nloc_12DE:\nmovsxd rax, dword ptr [r15]\nlea rbx, [r14+rax*8]\nlea rdi, aIndex24+0Bh; s\ncall _strdup\nmov [rbx], rax\nadd dword ptr [r15], 1\njmp loc_13EB\nloc_12FD:\nmovsxd rdx, edx\nmov [r14+rdx*8], rbp\nadd dword ptr [r15], 1\nloc_1308:\nmov rax, [rsp+78h+var_78]\nmov r13, [rax]\nmov rdi, r13; s\ncall _strlen\ncmp rax, r12\njb loc_13A4\nmovsxd rbx, [rsp+78h+var_64]\nmov rdi, rbx; size\ncall _malloc\nmov rbp, rax\nmov rcx, rbx\nmov rdx, r12\nmov rsi, r13\nmov rdi, rax\ncall ___strncpy_chk\nmov rax, [rsp+78h+var_70]\nmovzx eax, byte ptr [rax]\nmov [rbp+r12+0], al\nlea rsi, [r13+r12+0]\nadd r12, 1\ncmp rbx, r12\nmov rdx, rbx\ncmovb rdx, r12\nsub rdx, r12\nlea rdi, [rbp+r12+0]\ncall ___strcpy_chk\nmov edx, [r15]\ntest edx, edx\njle short loc_12FD\nmov rbx, r14\nmovsxd rax, edx\nlea r13, [r14+rax*8]\nmov [rsp+78h+var_68], edx\nloc_1383:\nmov rdi, [rbx]; s1\nmov rsi, rbp; s2\ncall _strcmp\ntest eax, eax\njz short loc_140A\nadd rbx, 8\ncmp rbx, r13\njnz short loc_1383\nmov edx, [rsp+78h+var_68]\njmp loc_12FD\nloc_13A4:\nadd [rsp+78h+var_78], 8\nmov rax, [rsp+78h+var_78]\nmov rcx, [rsp+78h+var_60]\ncmp rax, rcx\njz short loc_13C2\nloc_13B7:\nmov r12d, 0\njmp loc_1308\nloc_13C2:\nmov r12, [rsp+78h+var_58]\nmov rbp, [rsp+78h+var_50]\nmov r13, [rsp+78h+var_60]\nloc_13D1:\nmov rdi, [r12]; ptr\ncall _free\nadd r12, 8\ncmp r12, r13\njnz short loc_13D1\nloc_13E3:\nmov rdi, rbp; ptr\ncall _free\nloc_13EB:\nmov rax, [rsp+78h+var_40]\nsub rax, fs:28h\njnz short loc_1417\nadd rsp, 48h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_140A:\nmov rdi, rbp; ptr\ncall _free\njmp loc_1308\nloc_1417:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_1249(const char *a1, const char **a2, int *a3)\n{\n int v5; // eax\n int v6; // ebx\n const char **v7; // rbp\n char **v8; // rbx\n const char *v9; // r13\n char *v10; // rbp\n const char *v11; // rsi\n size_t v12; // r12\n size_t v13; // rdx\n int v14; // edx\n const char **v15; // rbx\n const char **v16; // r13\n void **v17; // r12\n const char **v19; // [rsp+0h] [rbp-78h]\n int v20; // [rsp+10h] [rbp-68h]\n int v21; // [rsp+14h] [rbp-64h]\n const char **v22; // [rsp+18h] [rbp-60h]\n void **v23; // [rsp+20h] [rbp-58h]\n const char **v24; // [rsp+28h] [rbp-50h]\n int v25; // [rsp+34h] [rbp-44h] BYREF\n unsigned __int64 v26; // [rsp+38h] [rbp-40h]\n\n v26 = __readfsqword(0x28u);\n v5 = strlen(a1);\n if ( v5 )\n {\n v6 = v5;\n v7 = (const char **)malloc(0x4EC00uLL);\n v25 = 0;\n sub_1249(a1 + 1, v7, &v25);\n if ( v25 > 0 )\n {\n v19 = v7;\n v21 = v6 + 1;\n v23 = (void **)v7;\n v24 = v7;\n v22 = &v7[v25];\n do\n {\n v12 = 0LL;\n while ( 1 )\n {\n v9 = *v19;\n if ( strlen(*v19) < v12 )\n break;\n v10 = (char *)malloc(v21);\n __strncpy_chk(v10, v9, v12, v21);\n v10[v12] = *a1;\n v11 = &v9[v12++];\n v13 = v21;\n if ( v21 < v12 )\n v13 = v12;\n __strcpy_chk(&v10[v12], v11, v13 - v12);\n v14 = *a3;\n if ( *a3 <= 0 )\n {\nLABEL_5:\n a2[v14] = v10;\n ++*a3;\n }\n else\n {\n v15 = a2;\n v16 = &a2[v14];\n v20 = *a3;\n while ( strcmp(*v15, v10) )\n {\n if ( ++v15 == v16 )\n {\n v14 = v20;\n goto LABEL_5;\n }\n }\n free(v10);\n }\n }\n ++v19;\n }\n while ( v19 != v22 );\n v17 = v23;\n v7 = v24;\n do\n free(*v17++);\n while ( v17 != (void **)v22 );\n }\n free(v7);\n }\n else\n {\n v8 = (char **)&a2[*a3];\n *v8 = strdup(\"\");\n ++*a3;\n }\n return v26 - __readfsqword(0x28u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_1249(const char *a1, const char **a2, int *a3) {\n int v5;\n int v6;\n const char **v7;\n char **v8;\n const char *v9;\n char *v10;\n const char *v11;\n unsigned int v12;\n unsigned int v13;\n int v14;\n const char **v15;\n const char **v16;\n void **v17;\n const char **v19;\n int v20;\n int v21;\n const char **v22;\n void **v23;\n const char **v24;\n int v25;\n unsigned long long v26;\n v26 = __readfsqword(40u);\n v5 = strlen(a1);\n if (v5) {\n v6 = v5;\n v7 = (const char **)malloc(322560uLL);\n v25 = 0;\n sub_1249(a1 + 1, v7, &v25);\n if (v25 > 0) {\n v19 = v7;\n v21 = v6 + 1;\n v23 = (void **)v7;\n v24 = v7;\n v22 = &v7[v25];\n do {\n v12 = 0LL;\n while (1) {\n v9 = *v19;\n if (strlen(*v19) < v12) break;\n v10 = (char *)malloc(v21);\n __strncpy_chk(v10, v9, v12, v21);\n v10[v12] = *a1;\n v11 = &v9[v12++];\n v13 = v21;\n if (v21 < v12) v13 = v12;\n __strcpy_chk(&v10[v12], v11, v13 - v12);\n v14 = *a3;\n if (*a3 <= 0) {\n LABEL_5:\n a2[v14] = v10;\n ++*a3;\n } else {\n v15 = a2;\n v16 = &a2[v14];\n v20 = *a3;\n while (strcmp(*v15, v10)) {\n if (++v15 == v16) {\n v14 = v20;\n goto LABEL_5;\n }\n }\n free(v10);\n }\n }\n ++v19;\n } while (v19 != v22);\n v17 = v23;\n v7 = v24;\n do\n free(*v17++);\n while (v17 != (void **)v22);\n }\n free(v7);\n } else {\n v8 = (char **)&a2[*a3];\n *v8 = strdup(\"\");\n ++*a3;\n }\n return v26 - __readfsqword(40u);\n}", + "ida_pseudo_norm": "unsigned long long func0(const char *a1, const char **a2, int *a3) {\n int v5;\n int v6;\n const char **v7;\n char **v8;\n const char *v9;\n char *v10;\n const char *v11;\n unsigned int v12;\n unsigned int v13;\n int v14;\n const char **v15;\n const char **v16;\n void **v17;\n const char **v19;\n int v20;\n int v21;\n const char **v22;\n void **v23;\n const char **v24;\n int v25;\n unsigned long long v26;\n v26 = __readfsqword(40u);\n v5 = strlen(a1);\n if (v5) {\n v6 = v5;\n v7 = (const char **)malloc(322560uLL);\n v25 = 0;\n func0(a1 + 1, v7, &v25);\n if (v25 > 0) {\n v19 = v7;\n v21 = v6 + 1;\n v23 = (void **)v7;\n v24 = v7;\n v22 = &v7[v25];\n do {\n v12 = 0LL;\n while (1) {\n v9 = *v19;\n if (strlen(*v19) < v12) break;\n v10 = (char *)malloc(v21);\n __strncpy_chk(v10, v9, v12, v21);\n v10[v12] = *a1;\n v11 = &v9[v12++];\n v13 = v21;\n if (v21 < v12) v13 = v12;\n __strcpy_chk(&v10[v12], v11, v13 - v12);\n v14 = *a3;\n if (*a3 <= 0) {\n LABEL_5:\n a2[v14] = v10;\n ++*a3;\n } else {\n v15 = a2;\n v16 = &a2[v14];\n v20 = *a3;\n while (strcmp(*v15, v10)) {\n if (++v15 == v16) {\n v14 = v20;\n goto LABEL_5;\n }\n }\n free(v10);\n }\n }\n ++v19;\n } while (v19 != v22);\n v17 = v23;\n v7 = v24;\n do\n free(*v17++);\n while (v17 != (void **)v22);\n }\n free(v7);\n } else {\n v8 = (char **)&a2[*a3];\n *v8 = strdup(\"\");\n ++*a3;\n }\n return v26 - __readfsqword(40u);\n}" + }, + { + "index": 374, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(const char *str, char **result, int *index) {\n int len = strlen(str);\n if (len == 0) {\n result[*index] = strdup(\"\");\n (*index)++;\n return;\n }\n char **prev_list = malloc(40320 * sizeof(char *));\n int prev_index = 0;\n func0(str + 1, prev_list, &prev_index);\n int i, j, k;\n for (i = 0; i < prev_index; i++) {\n for (j = 0; j <= strlen(prev_list[i]); j++) {\n char *new_str = malloc((len + 1) * sizeof(char));\n strncpy(new_str, prev_list[i], j);\n new_str[j] = str[0];\n strcpy(new_str + j + 1, prev_list[i] + j);\n int found = 0;\n for (k = 0; k < *index; k++) {\n if (strcmp(result[k], new_str) == 0) {\n found = 1;\n break;\n }\n }\n if (!found) {\n result[*index] = new_str;\n (*index)++;\n } else {\n free(new_str);\n }\n }\n }\n for (i = 0; i < prev_index; i++) {\n free(prev_list[i]);\n }\n free(prev_list);\n}", + "test": "int main() {\n\n char *result[100];\n\n int index;\n\n\n\n index = 0;\n\n func0(\"ab\", result, &index);\n\n assert(strcmp(result[0], \"ab\") == 0 && strcmp(result[1], \"ba\") == 0 && index == 2);\n\n\n\n index = 0;\n\n func0(\"abc\", result, &index);\n\n assert(strcmp(result[0], \"abc\") == 0 && strcmp(result[1], \"bac\") == 0 && strcmp(result[2], \"bca\") == 0 &&\n\n strcmp(result[3], \"acb\") == 0 && strcmp(result[4], \"cab\") == 0 && strcmp(result[5], \"cba\") == 0 && index == 6);\n\n\n\n index = 0;\n\n func0(\"abcd\", result, &index);\n\n assert(index == 24);\n\n \n\n // Clean up allocated memory\n\n for (int i = 0; i < index; i++) {\n\n free(result[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x58,%rsp\nmov %rdi,0x18(%rsp)\nmov %rsi,0x10(%rsp)\nmov %rdx,0x8(%rsp)\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\ncallq 1100 \ntest %eax,%eax\nje 162d \nmov $0x4ec00,%edi\nmov %rax,%rbx\ncallq 1140 \nmov 0x18(%rsp),%rcx\nadd $0x1,%ebx\nlea 0x44(%rsp),%rdx\nmov %rax,%rsi\nmov %rax,0x38(%rsp)\nlea 0x1(%rcx),%rdi\nmovl $0x0,0x44(%rsp)\ncallq 1460 \nmovslq %ebx,%rax\nmovq $0x0,0x30(%rsp)\nmov %rax,0x20(%rsp)\nmov 0x10(%rsp),%rax\nadd $0x8,%rax\nmov %rax,0x28(%rsp)\nmov 0x44(%rsp),%eax\ntest %eax,%eax\njle 15e0 \nnopl 0x0(%rax)\nmov 0x38(%rsp),%rax\nmov 0x30(%rsp),%rdx\nxor %ebp,%ebp\nmov (%rax,%rdx,8),%r13\nmov 0x20(%rsp),%rdi\ncallq 1140 \nmov %rbp,%rdx\nmov %r13,%rsi\nmov %rax,%rdi\nmov %rax,%r14\ncallq 10e0 \nmov 0x18(%rsp),%rax\nlea 0x0(%r13,%rbp,1),%rsi\nmovzbl (%rax),%eax\nmov %al,(%r14,%rbp,1)\nadd $0x1,%rbp\nlea (%r14,%rbp,1),%rdi\ncallq 10f0 \nmov 0x8(%rsp),%rax\nmov (%rax),%r12d\ntest %r12d,%r12d\njle 1610 \nmov 0x28(%rsp),%rcx\nlea -0x1(%r12),%eax\nmov 0x10(%rsp),%r15\nlea (%rcx,%rax,8),%rbx\njmp 157d \nadd $0x8,%r15\ncmp %rbx,%r15\nje 1610 \nmov (%r15),%rdi\nmov %r14,%rsi\ncallq 1130 \ntest %eax,%eax\njne 1570 \nmov %r14,%rdi\ncallq 10d0 \nmov %r13,%rdi\ncallq 1100 \ncmp %rbp,%rax\njae 1510 \naddq $0x1,0x30(%rsp)\nmov 0x44(%rsp),%eax\nmov 0x30(%rsp),%rcx\ncmp %ecx,%eax\njg 1500 \ntest %eax,%eax\njle 15e0 \nxor %ebx,%ebx\nnopw 0x0(%rax,%rax,1)\nmov 0x38(%rsp),%rax\nmov (%rax,%rbx,8),%rdi\nadd $0x1,%rbx\ncallq 10d0 \ncmp %ebx,0x44(%rsp)\njg 15c8 \nmov 0x48(%rsp),%rax\nxor %fs:0x28,%rax\njne 1670 \nmov 0x38(%rsp),%rdi\nadd $0x58,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\njmpq 10d0 \nnopl 0x0(%rax)\nmov 0x10(%rsp),%rdx\nmovslq %r12d,%rax\nadd $0x1,%r12d\nmov %r14,(%rdx,%rax,8)\nmov 0x8(%rsp),%rax\nmov %r12d,(%rax)\njmpq 1594 \nmov 0x8(%rsp),%r14\nmov 0x10(%rsp),%rcx\nlea 0x9ee(%rip),%rdi\nmovslq (%r14),%rax\nlea (%rcx,%rax,8),%rbx\ncallq 1150 \nmov %rax,(%rbx)\naddl $0x1,(%r14)\nmov 0x48(%rsp),%rax\nxor %fs:0x28,%rax\njne 1670 \nadd $0x58,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\ncallq 1110 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14, rsi\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 58h\nmov [rsp+88h+var_78], rdi\nmov [rsp+88h+var_88], rdx\nmov rax, fs:28h\nmov [rsp+88h+var_40], rax\nxor eax, eax\ncall _strlen\ntest eax, eax\njz loc_162B\nmov edi, 4EC00h; size\nmov ebx, eax\ncall _malloc\nlea rdx, [rsp+88h+var_44]\nmov [rsp+88h+var_44], 0\nmov r13, rax\nmov rax, [rsp+88h+var_78]\nmov rsi, r13\nlea rdi, [rax+1]; s\ncall func0\nmovsxd rax, [rsp+88h+var_44]\ntest eax, eax\njle loc_15E2\nlea rax, [r13+rax*8+0]\nmov [rsp+88h+var_58], r13\nmov [rsp+88h+var_60], rax\nlea eax, [rbx+1]\nmov [rsp+88h+var_6C], eax\nmov [rsp+88h+var_50], r13\nmov [rsp+88h+var_68], r13\nnop dword ptr [rax]\nloc_14D8:\nmov rax, [rsp+88h+var_68]\nxor ebp, ebp\nmov r13, [rax]\nnop word ptr [rax+rax+00h]\nloc_14E8:\nmov rdi, r13; s\ncall _strlen\ncmp rax, rbp\njb loc_15A6\nloc_14F9:\nmovsxd r15, [rsp+88h+var_6C]\nmov rdi, r15; size\ncall _malloc\nmov rdx, rbp\nmov rcx, r15\nmov rsi, r13\nmov rdi, rax\nmov rbx, rax\ncall ___strncpy_chk\nmov rax, [rsp+88h+var_78]\nlea rsi, [r13+rbp+0]\nmov rdx, r15\nmovzx eax, byte ptr [rax]\nmov [rbx+rbp], al\nadd rbp, 1\ncmp r15, rbp\nlea rdi, [rbx+rbp]\ncmovb rdx, rbp\nsub rdx, rbp\ncall ___strcpy_chk\nmov rax, [rsp+88h+var_88]\nmov edx, [rax]\nmovsxd rsi, edx\ntest edx, edx\njle loc_1619\nmovsxd rsi, edx\nmov [rsp+88h+var_70], edx\nmov r12, r14\nmov [rsp+88h+var_80], rsi\nlea r15, [r14+rsi*8]\njmp short loc_157D\nloc_1570:\nadd r12, 8\ncmp r12, r15\njz loc_1610\nloc_157D:\nmov rdi, [r12]; s1\nmov rsi, rbx; s2\ncall _strcmp\ntest eax, eax\njnz short loc_1570\nmov rdi, rbx; ptr\ncall _free\nmov rdi, r13; s\ncall _strlen\ncmp rax, rbp\njnb loc_14F9\nloc_15A6:\nadd [rsp+88h+var_68], 8\nmov rcx, [rsp+88h+var_60]\nmov rax, [rsp+88h+var_68]\ncmp rax, rcx\njnz loc_14D8\nmov rbp, [rsp+88h+var_58]\nmov r13, [rsp+88h+var_50]\nmov rbx, [rsp+88h+var_60]\nxchg ax, ax\nloc_15D0:\nmov rdi, [rbp+0]; ptr\nadd rbp, 8\ncall _free\ncmp rbp, rbx\njnz short loc_15D0\nloc_15E2:\nmov rax, [rsp+88h+var_40]\nsub rax, fs:28h\njnz short loc_1668\nadd rsp, 58h\nmov rdi, r13; ptr\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\njmp _free\nloc_1610:\nmov edx, [rsp+88h+var_70]\nmov rsi, [rsp+88h+var_80]\nloc_1619:\nmov rax, [rsp+88h+var_88]\nlea ecx, [rdx+1]\nmov [r14+rsi*8], rbx\nmov [rax], ecx\njmp loc_14E8\nloc_162B:\nmov r15, [rsp+88h+var_88]\nlea rdi, aIndex24+0Bh; s\nmovsxd rax, dword ptr [r15]\nlea rbx, [r14+rax*8]\ncall _strdup\nmov [rbx], rax\nadd dword ptr [r15], 1\nmov rax, [rsp+88h+var_40]\nsub rax, fs:28h\njnz short loc_1668\nadd rsp, 58h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1668:\ncall ___stack_chk_fail", + "ida_pseudo": "void __fastcall func0(const char *a1, const char **a2, int *a3)\n{\n int v4; // eax\n int v5; // ebx\n const char **v6; // r13\n size_t v7; // rbp\n const char *v8; // r13\n char *v9; // rbx\n const char *v10; // rsi\n size_t v11; // rdx\n int v12; // edx\n __int64 v13; // rsi\n const char **v14; // r12\n const char **v15; // r15\n void **v16; // rbp\n void *v17; // rdi\n char **v18; // rbx\n __int64 v20; // [rsp+8h] [rbp-80h]\n int v21; // [rsp+18h] [rbp-70h]\n int v22; // [rsp+1Ch] [rbp-6Ch]\n const char **v23; // [rsp+20h] [rbp-68h]\n const char **v24; // [rsp+28h] [rbp-60h]\n void **v25; // [rsp+30h] [rbp-58h]\n const char **v26; // [rsp+38h] [rbp-50h]\n int v27; // [rsp+44h] [rbp-44h] BYREF\n unsigned __int64 v28; // [rsp+48h] [rbp-40h]\n\n v28 = __readfsqword(0x28u);\n v4 = strlen(a1);\n if ( v4 )\n {\n v5 = v4;\n v27 = 0;\n v6 = (const char **)malloc(0x4EC00uLL);\n func0(a1 + 1, v6, &v27);\n if ( v27 > 0 )\n {\n v25 = (void **)v6;\n v24 = &v6[v27];\n v22 = v5 + 1;\n v26 = v6;\n v23 = v6;\n do\n {\n v7 = 0LL;\n v8 = *v23;\n while ( strlen(v8) >= v7 )\n {\n while ( 2 )\n {\n v9 = (char *)malloc(v22);\n __strncpy_chk(v9, v8, v7, v22);\n v10 = &v8[v7];\n v11 = v22;\n v9[v7++] = *a1;\n if ( v22 < v7 )\n v11 = v7;\n __strcpy_chk(&v9[v7], v10, v11 - v7);\n v12 = *a3;\n v13 = *a3;\n if ( *a3 > 0 )\n {\n v21 = *a3;\n v14 = a2;\n v20 = v12;\n v15 = &a2[v12];\n while ( strcmp(*v14, v9) )\n {\n if ( ++v14 == v15 )\n {\n v12 = v21;\n v13 = v20;\n goto LABEL_18;\n }\n }\n free(v9);\n if ( strlen(v8) >= v7 )\n continue;\n goto LABEL_13;\n }\n break;\n }\nLABEL_18:\n a2[v13] = v9;\n *a3 = v12 + 1;\n }\nLABEL_13:\n ++v23;\n }\n while ( v23 != v24 );\n v16 = v25;\n v6 = v26;\n do\n {\n v17 = *v16++;\n free(v17);\n }\n while ( v16 != (void **)v24 );\n }\n free(v6);\n }\n else\n {\n v18 = (char **)&a2[*a3];\n *v18 = strdup(\"\");\n ++*a3;\n }\n}", + "ida_strip_asm": "sub_1440:\nendbr64\npush r15\npush r14\nmov r14, rsi\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 58h\nmov [rsp+88h+var_78], rdi\nmov [rsp+88h+var_88], rdx\nmov rax, fs:28h\nmov [rsp+88h+var_40], rax\nxor eax, eax\ncall _strlen\ntest eax, eax\njz loc_162B\nmov edi, 4EC00h; size\nmov ebx, eax\ncall _malloc\nlea rdx, [rsp+88h+var_44]\nmov [rsp+88h+var_44], 0\nmov r13, rax\nmov rax, [rsp+88h+var_78]\nmov rsi, r13\nlea rdi, [rax+1]; s\ncall sub_1440\nmovsxd rax, [rsp+88h+var_44]\ntest eax, eax\njle loc_15E2\nlea rax, [r13+rax*8+0]\nmov [rsp+88h+var_58], r13\nmov [rsp+88h+var_60], rax\nlea eax, [rbx+1]\nmov [rsp+88h+var_6C], eax\nmov [rsp+88h+var_50], r13\nmov [rsp+88h+var_68], r13\nnop dword ptr [rax]\nloc_14D8:\nmov rax, [rsp+88h+var_68]\nxor ebp, ebp\nmov r13, [rax]\nnop word ptr [rax+rax+00h]\nloc_14E8:\nmov rdi, r13; s\ncall _strlen\ncmp rax, rbp\njb loc_15A6\nloc_14F9:\nmovsxd r15, [rsp+88h+var_6C]\nmov rdi, r15; size\ncall _malloc\nmov rdx, rbp\nmov rcx, r15\nmov rsi, r13\nmov rdi, rax\nmov rbx, rax\ncall ___strncpy_chk\nmov rax, [rsp+88h+var_78]\nlea rsi, [r13+rbp+0]\nmov rdx, r15\nmovzx eax, byte ptr [rax]\nmov [rbx+rbp], al\nadd rbp, 1\ncmp r15, rbp\nlea rdi, [rbx+rbp]\ncmovb rdx, rbp\nsub rdx, rbp\ncall ___strcpy_chk\nmov rax, [rsp+88h+var_88]\nmov edx, [rax]\nmovsxd rsi, edx\ntest edx, edx\njle loc_1619\nmovsxd rsi, edx\nmov [rsp+88h+var_70], edx\nmov r12, r14\nmov [rsp+88h+var_80], rsi\nlea r15, [r14+rsi*8]\njmp short loc_157D\nloc_1570:\nadd r12, 8\ncmp r12, r15\njz loc_1610\nloc_157D:\nmov rdi, [r12]; s1\nmov rsi, rbx; s2\ncall _strcmp\ntest eax, eax\njnz short loc_1570\nmov rdi, rbx; ptr\ncall _free\nmov rdi, r13; s\ncall _strlen\ncmp rax, rbp\njnb loc_14F9\nloc_15A6:\nadd [rsp+88h+var_68], 8\nmov rcx, [rsp+88h+var_60]\nmov rax, [rsp+88h+var_68]\ncmp rax, rcx\njnz loc_14D8\nmov rbp, [rsp+88h+var_58]\nmov r13, [rsp+88h+var_50]\nmov rbx, [rsp+88h+var_60]\nxchg ax, ax\nloc_15D0:\nmov rdi, [rbp+0]; ptr\nadd rbp, 8\ncall _free\ncmp rbp, rbx\njnz short loc_15D0\nloc_15E2:\nmov rax, [rsp+88h+var_40]\nsub rax, fs:28h\njnz short loc_1668\nadd rsp, 58h\nmov rdi, r13; ptr\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\njmp _free\nloc_1610:\nmov edx, [rsp+88h+var_70]\nmov rsi, [rsp+88h+var_80]\nloc_1619:\nmov rax, [rsp+88h+var_88]\nlea ecx, [rdx+1]\nmov [r14+rsi*8], rbx\nmov [rax], ecx\njmp loc_14E8\nloc_162B:\nmov r15, [rsp+88h+var_88]\nlea rdi, aIndex24+0Bh; s\nmovsxd rax, dword ptr [r15]\nlea rbx, [r14+rax*8]\ncall _strdup\nmov [rbx], rax\nadd dword ptr [r15], 1\nmov rax, [rsp+88h+var_40]\nsub rax, fs:28h\njnz short loc_1668\nadd rsp, 58h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1668:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "void __fastcall sub_1440(const char *a1, const char **a2, int *a3)\n{\n int v4; // eax\n int v5; // ebx\n const char **v6; // r13\n size_t v7; // rbp\n const char *v8; // r13\n char *v9; // rbx\n const char *v10; // rsi\n size_t v11; // rdx\n int v12; // edx\n __int64 v13; // rsi\n const char **v14; // r12\n const char **v15; // r15\n void **v16; // rbp\n void *v17; // rdi\n char **v18; // rbx\n __int64 v20; // [rsp+8h] [rbp-80h]\n int v21; // [rsp+18h] [rbp-70h]\n int v22; // [rsp+1Ch] [rbp-6Ch]\n const char **v23; // [rsp+20h] [rbp-68h]\n const char **v24; // [rsp+28h] [rbp-60h]\n void **v25; // [rsp+30h] [rbp-58h]\n const char **v26; // [rsp+38h] [rbp-50h]\n int v27; // [rsp+44h] [rbp-44h] BYREF\n unsigned __int64 v28; // [rsp+48h] [rbp-40h]\n\n v28 = __readfsqword(0x28u);\n v4 = strlen(a1);\n if ( v4 )\n {\n v5 = v4;\n v27 = 0;\n v6 = (const char **)malloc(0x4EC00uLL);\n sub_1440(a1 + 1, v6, &v27);\n if ( v27 > 0 )\n {\n v25 = (void **)v6;\n v24 = &v6[v27];\n v22 = v5 + 1;\n v26 = v6;\n v23 = v6;\n do\n {\n v7 = 0LL;\n v8 = *v23;\n while ( strlen(v8) >= v7 )\n {\n while ( 2 )\n {\n v9 = (char *)malloc(v22);\n __strncpy_chk(v9, v8, v7, v22);\n v10 = &v8[v7];\n v11 = v22;\n v9[v7++] = *a1;\n if ( v22 < v7 )\n v11 = v7;\n __strcpy_chk(&v9[v7], v10, v11 - v7);\n v12 = *a3;\n v13 = *a3;\n if ( *a3 > 0 )\n {\n v21 = *a3;\n v14 = a2;\n v20 = v12;\n v15 = &a2[v12];\n while ( strcmp(*v14, v9) )\n {\n if ( ++v14 == v15 )\n {\n v12 = v21;\n v13 = v20;\n goto LABEL_18;\n }\n }\n free(v9);\n if ( strlen(v8) >= v7 )\n continue;\n goto LABEL_13;\n }\n break;\n }\nLABEL_18:\n a2[v13] = v9;\n *a3 = v12 + 1;\n }\nLABEL_13:\n ++v23;\n }\n while ( v23 != v24 );\n v16 = v25;\n v6 = v26;\n do\n {\n v17 = *v16++;\n free(v17);\n }\n while ( v16 != (void **)v24 );\n }\n free(v6);\n }\n else\n {\n v18 = (char **)&a2[*a3];\n *v18 = strdup(\"\");\n ++*a3;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1440(const char *a1, const char **a2, int *a3) {\n int v4;\n int v5;\n const char **v6;\n unsigned int v7;\n const char *v8;\n char *v9;\n const char *v10;\n unsigned int v11;\n int v12;\n long long v13;\n const char **v14;\n const char **v15;\n void **v16;\n void *v17;\n char **v18;\n long long v20;\n int v21;\n int v22;\n const char **v23;\n const char **v24;\n void **v25;\n const char **v26;\n int v27;\n unsigned long long v28;\n v28 = __readfsqword(40u);\n v4 = strlen(a1);\n if (v4) {\n v5 = v4;\n v27 = 0;\n v6 = (const char **)malloc(322560uLL);\n sub_1440(a1 + 1, v6, &v27);\n if (v27 > 0) {\n v25 = (void **)v6;\n v24 = &v6[v27];\n v22 = v5 + 1;\n v26 = v6;\n v23 = v6;\n do {\n v7 = 0LL;\n v8 = *v23;\n while (strlen(v8) >= v7) {\n while (2) {\n v9 = (char *)malloc(v22);\n __strncpy_chk(v9, v8, v7, v22);\n v10 = &v8[v7];\n v11 = v22;\n v9[v7++] = *a1;\n if (v22 < v7) v11 = v7;\n __strcpy_chk(&v9[v7], v10, v11 - v7);\n v12 = *a3;\n v13 = *a3;\n if (*a3 > 0) {\n v21 = *a3;\n v14 = a2;\n v20 = v12;\n v15 = &a2[v12];\n while (strcmp(*v14, v9)) {\n if (++v14 == v15) {\n v12 = v21;\n v13 = v20;\n goto LABEL_18;\n }\n }\n free(v9);\n if (strlen(v8) >= v7) continue;\n goto LABEL_13;\n }\n break;\n }\n LABEL_18:\n a2[v13] = v9;\n *a3 = v12 + 1;\n }\n LABEL_13:\n ++v23;\n } while (v23 != v24);\n v16 = v25;\n v6 = v26;\n do {\n v17 = *v16++;\n free(v17);\n } while (v16 != (void **)v24);\n }\n free(v6);\n } else {\n v18 = (char **)&a2[*a3];\n *v18 = strdup(\"\");\n ++*a3;\n }\n}", + "ida_pseudo_norm": "void func0(const char *a1, const char **a2, int *a3) {\n int v4;\n int v5;\n const char **v6;\n unsigned int v7;\n const char *v8;\n char *v9;\n const char *v10;\n unsigned int v11;\n int v12;\n long long v13;\n const char **v14;\n const char **v15;\n void **v16;\n void *v17;\n char **v18;\n long long v20;\n int v21;\n int v22;\n const char **v23;\n const char **v24;\n void **v25;\n const char **v26;\n int v27;\n unsigned long long v28;\n v28 = __readfsqword(40u);\n v4 = strlen(a1);\n if (v4) {\n v5 = v4;\n v27 = 0;\n v6 = (const char **)malloc(322560uLL);\n func0(a1 + 1, v6, &v27);\n if (v27 > 0) {\n v25 = (void **)v6;\n v24 = &v6[v27];\n v22 = v5 + 1;\n v26 = v6;\n v23 = v6;\n do {\n v7 = 0LL;\n v8 = *v23;\n while (strlen(v8) >= v7) {\n while (2) {\n v9 = (char *)malloc(v22);\n __strncpy_chk(v9, v8, v7, v22);\n v10 = &v8[v7];\n v11 = v22;\n v9[v7++] = *a1;\n if (v22 < v7) v11 = v7;\n __strcpy_chk(&v9[v7], v10, v11 - v7);\n v12 = *a3;\n v13 = *a3;\n if (*a3 > 0) {\n v21 = *a3;\n v14 = a2;\n v20 = v12;\n v15 = &a2[v12];\n while (strcmp(*v14, v9)) {\n if (++v14 == v15) {\n v12 = v21;\n v13 = v20;\n goto LABEL_18;\n }\n }\n free(v9);\n if (strlen(v8) >= v7) continue;\n goto LABEL_13;\n }\n break;\n }\n LABEL_18:\n a2[v13] = v9;\n *a3 = v12 + 1;\n }\n LABEL_13:\n ++v23;\n } while (v23 != v24);\n v16 = v25;\n v6 = v26;\n do {\n v17 = *v16++;\n free(v17);\n } while (v16 != (void **)v24);\n }\n free(v6);\n } else {\n v18 = (char **)&a2[*a3];\n *v18 = strdup(\"\");\n ++*a3;\n }\n}" + }, + { + "index": 374, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(const char *str, char **result, int *index) {\n int len = strlen(str);\n if (len == 0) {\n result[*index] = strdup(\"\");\n (*index)++;\n return;\n }\n char **prev_list = malloc(40320 * sizeof(char *));\n int prev_index = 0;\n func0(str + 1, prev_list, &prev_index);\n int i, j, k;\n for (i = 0; i < prev_index; i++) {\n for (j = 0; j <= strlen(prev_list[i]); j++) {\n char *new_str = malloc((len + 1) * sizeof(char));\n strncpy(new_str, prev_list[i], j);\n new_str[j] = str[0];\n strcpy(new_str + j + 1, prev_list[i] + j);\n int found = 0;\n for (k = 0; k < *index; k++) {\n if (strcmp(result[k], new_str) == 0) {\n found = 1;\n break;\n }\n }\n if (!found) {\n result[*index] = new_str;\n (*index)++;\n } else {\n free(new_str);\n }\n }\n }\n for (i = 0; i < prev_index; i++) {\n free(prev_list[i]);\n }\n free(prev_list);\n}", + "test": "int main() {\n\n char *result[100];\n\n int index;\n\n\n\n index = 0;\n\n func0(\"ab\", result, &index);\n\n assert(strcmp(result[0], \"ab\") == 0 && strcmp(result[1], \"ba\") == 0 && index == 2);\n\n\n\n index = 0;\n\n func0(\"abc\", result, &index);\n\n assert(strcmp(result[0], \"abc\") == 0 && strcmp(result[1], \"bac\") == 0 && strcmp(result[2], \"bca\") == 0 &&\n\n strcmp(result[3], \"acb\") == 0 && strcmp(result[4], \"cab\") == 0 && strcmp(result[5], \"cba\") == 0 && index == 6);\n\n\n\n index = 0;\n\n func0(\"abcd\", result, &index);\n\n assert(index == 24);\n\n \n\n // Clean up allocated memory\n\n for (int i = 0; i < index; i++) {\n\n free(result[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x58,%rsp\nmov %rdi,0x18(%rsp)\nmov %rsi,0x10(%rsp)\nmov %rdx,0x8(%rsp)\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\ncallq 1100 \ntest %eax,%eax\nje 162d \nmov $0x4ec00,%edi\nmov %rax,%rbx\ncallq 1140 \nmov 0x18(%rsp),%rcx\nadd $0x1,%ebx\nlea 0x44(%rsp),%rdx\nmov %rax,%rsi\nmov %rax,0x38(%rsp)\nlea 0x1(%rcx),%rdi\nmovl $0x0,0x44(%rsp)\ncallq 1460 \nmovslq %ebx,%rax\nmovq $0x0,0x30(%rsp)\nmov %rax,0x20(%rsp)\nmov 0x10(%rsp),%rax\nadd $0x8,%rax\nmov %rax,0x28(%rsp)\nmov 0x44(%rsp),%eax\ntest %eax,%eax\njle 15e0 \nnopl 0x0(%rax)\nmov 0x38(%rsp),%rax\nmov 0x30(%rsp),%rdx\nxor %ebp,%ebp\nmov (%rax,%rdx,8),%r13\nmov 0x20(%rsp),%rdi\ncallq 1140 \nmov %rbp,%rdx\nmov %r13,%rsi\nmov %rax,%rdi\nmov %rax,%r14\ncallq 10e0 \nmov 0x18(%rsp),%rax\nlea 0x0(%r13,%rbp,1),%rsi\nmovzbl (%rax),%eax\nmov %al,(%r14,%rbp,1)\nadd $0x1,%rbp\nlea (%r14,%rbp,1),%rdi\ncallq 10f0 \nmov 0x8(%rsp),%rax\nmov (%rax),%r12d\ntest %r12d,%r12d\njle 1610 \nmov 0x28(%rsp),%rcx\nlea -0x1(%r12),%eax\nmov 0x10(%rsp),%r15\nlea (%rcx,%rax,8),%rbx\njmp 157d \nadd $0x8,%r15\ncmp %r15,%rbx\nje 1610 \nmov (%r15),%rdi\nmov %r14,%rsi\ncallq 1130 \ntest %eax,%eax\njne 1570 \nmov %r14,%rdi\ncallq 10d0 \nmov %r13,%rdi\ncallq 1100 \ncmp %rax,%rbp\njbe 1510 \naddq $0x1,0x30(%rsp)\nmov 0x44(%rsp),%eax\nmov 0x30(%rsp),%rcx\ncmp %ecx,%eax\njg 1500 \ntest %eax,%eax\njle 15e0 \nxor %ebx,%ebx\nnopw 0x0(%rax,%rax,1)\nmov 0x38(%rsp),%rax\nmov (%rax,%rbx,8),%rdi\nadd $0x1,%rbx\ncallq 10d0 \ncmp %ebx,0x44(%rsp)\njg 15c8 \nmov 0x48(%rsp),%rax\nxor %fs:0x28,%rax\njne 1670 \nmov 0x38(%rsp),%rdi\nadd $0x58,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\njmpq 10d0 \nnopl 0x0(%rax)\nmov 0x10(%rsp),%rdx\nmovslq %r12d,%rax\nadd $0x1,%r12d\nmov %r14,(%rdx,%rax,8)\nmov 0x8(%rsp),%rax\nmov %r12d,(%rax)\njmpq 1594 \nmov 0x8(%rsp),%r14\nmov 0x10(%rsp),%rcx\nlea 0x9ee(%rip),%rdi\nmovslq (%r14),%rax\nlea (%rcx,%rax,8),%rbx\ncallq 1150 \nmov %rax,(%rbx)\naddl $0x1,(%r14)\nmov 0x48(%rsp),%rax\nxor %fs:0x28,%rax\njne 1670 \nadd $0x58,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\ncallq 1110 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14, rsi\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 58h\nmov [rsp+88h+var_78], rdi\nmov [rsp+88h+var_88], rdx\nmov rax, fs:28h\nmov [rsp+88h+var_40], rax\nxor eax, eax\ncall _strlen\ntest eax, eax\njz loc_162B\nmov edi, 4EC00h; size\nmov ebx, eax\ncall _malloc\nlea rdx, [rsp+88h+var_44]\nmov [rsp+88h+var_44], 0\nmov r13, rax\nmov rax, [rsp+88h+var_78]\nmov rsi, r13\nlea rdi, [rax+1]; s\ncall func0\nmovsxd rax, [rsp+88h+var_44]\ntest eax, eax\njle loc_15E2\nlea rax, [r13+rax*8+0]\nmov [rsp+88h+var_58], r13\nmov [rsp+88h+var_60], rax\nlea eax, [rbx+1]\nmov [rsp+88h+var_6C], eax\nmov [rsp+88h+var_50], r13\nmov [rsp+88h+var_68], r13\nnop dword ptr [rax]\nloc_14D8:\nmov rax, [rsp+88h+var_68]\nxor ebp, ebp\nmov r13, [rax]\nnop word ptr [rax+rax+00h]\nloc_14E8:\nmov rdi, r13; s\ncall _strlen\ncmp rax, rbp\njb loc_15A6\nloc_14F9:\nmovsxd r15, [rsp+88h+var_6C]\nmov rdi, r15; size\ncall _malloc\nmov rdx, rbp\nmov rcx, r15\nmov rsi, r13\nmov rdi, rax\nmov rbx, rax\ncall ___strncpy_chk\nmov rax, [rsp+88h+var_78]\nlea rsi, [r13+rbp+0]\nmov rdx, r15\nmovzx eax, byte ptr [rax]\nmov [rbx+rbp], al\nadd rbp, 1\ncmp r15, rbp\nlea rdi, [rbx+rbp]\ncmovb rdx, rbp\nsub rdx, rbp\ncall ___strcpy_chk\nmov rax, [rsp+88h+var_88]\nmov edx, [rax]\nmovsxd rsi, edx\ntest edx, edx\njle loc_1619\nmovsxd rsi, edx\nmov [rsp+88h+var_70], edx\nmov r12, r14\nmov [rsp+88h+var_80], rsi\nlea r15, [r14+rsi*8]\njmp short loc_157D\nloc_1570:\nadd r12, 8\ncmp r15, r12\njz loc_1610\nloc_157D:\nmov rdi, [r12]; s1\nmov rsi, rbx; s2\ncall _strcmp\ntest eax, eax\njnz short loc_1570\nmov rdi, rbx; ptr\ncall _free\nmov rdi, r13; s\ncall _strlen\ncmp rax, rbp\njnb loc_14F9\nloc_15A6:\nadd [rsp+88h+var_68], 8\nmov rcx, [rsp+88h+var_60]\nmov rax, [rsp+88h+var_68]\ncmp rax, rcx\njnz loc_14D8\nmov r13, [rsp+88h+var_58]\nmov rbp, [rsp+88h+var_50]\nmov rbx, rcx\nnop dword ptr [rax+00h]\nloc_15D0:\nmov rdi, [rbp+0]; ptr\nadd rbp, 8\ncall _free\ncmp rbp, rbx\njnz short loc_15D0\nloc_15E2:\nmov rax, [rsp+88h+var_40]\nsub rax, fs:28h\njnz short loc_1668\nadd rsp, 58h\nmov rdi, r13; ptr\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\njmp _free\nloc_1610:\nmov edx, [rsp+88h+var_70]\nmov rsi, [rsp+88h+var_80]\nloc_1619:\nmov rax, [rsp+88h+var_88]\nlea ecx, [rdx+1]\nmov [r14+rsi*8], rbx\nmov [rax], ecx\njmp loc_14E8\nloc_162B:\nmov r15, [rsp+88h+var_88]\nlea rdi, aIndex24+0Bh; s\nmovsxd rax, dword ptr [r15]\nlea rbx, [r14+rax*8]\ncall _strdup\nmov [rbx], rax\nadd dword ptr [r15], 1\nmov rax, [rsp+88h+var_40]\nsub rax, fs:28h\njnz short loc_1668\nadd rsp, 58h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1668:\ncall ___stack_chk_fail", + "ida_pseudo": "void __fastcall func0(const char *a1, const char **a2, int *a3)\n{\n int v4; // eax\n int v5; // ebx\n const char **v6; // r13\n size_t v7; // rbp\n const char *v8; // r13\n char *v9; // rbx\n const char *v10; // rsi\n size_t v11; // rdx\n int v12; // edx\n __int64 v13; // rsi\n const char **v14; // r12\n const char **v15; // r15\n void **v16; // rbp\n void *v17; // rdi\n char **v18; // rbx\n __int64 v20; // [rsp+8h] [rbp-80h]\n int v21; // [rsp+18h] [rbp-70h]\n int v22; // [rsp+1Ch] [rbp-6Ch]\n const char **v23; // [rsp+20h] [rbp-68h]\n const char **v24; // [rsp+28h] [rbp-60h]\n const char **v25; // [rsp+30h] [rbp-58h]\n void **v26; // [rsp+38h] [rbp-50h]\n int v27; // [rsp+44h] [rbp-44h] BYREF\n unsigned __int64 v28; // [rsp+48h] [rbp-40h]\n\n v28 = __readfsqword(0x28u);\n v4 = strlen(a1);\n if ( v4 )\n {\n v5 = v4;\n v27 = 0;\n v6 = (const char **)malloc(0x4EC00uLL);\n func0(a1 + 1, v6, &v27);\n if ( v27 > 0 )\n {\n v25 = v6;\n v24 = &v6[v27];\n v22 = v5 + 1;\n v26 = (void **)v6;\n v23 = v6;\n do\n {\n v7 = 0LL;\n v8 = *v23;\n while ( strlen(v8) >= v7 )\n {\n while ( 2 )\n {\n v9 = (char *)malloc(v22);\n __strncpy_chk(v9, v8, v7, v22);\n v10 = &v8[v7];\n v11 = v22;\n v9[v7++] = *a1;\n if ( v22 < v7 )\n v11 = v7;\n __strcpy_chk(&v9[v7], v10, v11 - v7);\n v12 = *a3;\n v13 = *a3;\n if ( *a3 > 0 )\n {\n v21 = *a3;\n v14 = a2;\n v20 = v12;\n v15 = &a2[v12];\n while ( strcmp(*v14, v9) )\n {\n if ( v15 == ++v14 )\n {\n v12 = v21;\n v13 = v20;\n goto LABEL_18;\n }\n }\n free(v9);\n if ( strlen(v8) >= v7 )\n continue;\n goto LABEL_13;\n }\n break;\n }\nLABEL_18:\n a2[v13] = v9;\n *a3 = v12 + 1;\n }\nLABEL_13:\n ++v23;\n }\n while ( v23 != v24 );\n v6 = v25;\n v16 = v26;\n do\n {\n v17 = *v16++;\n free(v17);\n }\n while ( v16 != (void **)v24 );\n }\n free(v6);\n }\n else\n {\n v18 = (char **)&a2[*a3];\n *v18 = strdup(\"\");\n ++*a3;\n }\n}", + "ida_strip_asm": "sub_1440:\nendbr64\npush r15\npush r14\nmov r14, rsi\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 58h\nmov [rsp+88h+var_78], rdi\nmov [rsp+88h+var_88], rdx\nmov rax, fs:28h\nmov [rsp+88h+var_40], rax\nxor eax, eax\ncall _strlen\ntest eax, eax\njz loc_162B\nmov edi, 4EC00h; size\nmov ebx, eax\ncall _malloc\nlea rdx, [rsp+88h+var_44]\nmov [rsp+88h+var_44], 0\nmov r13, rax\nmov rax, [rsp+88h+var_78]\nmov rsi, r13\nlea rdi, [rax+1]; s\ncall sub_1440\nmovsxd rax, [rsp+88h+var_44]\ntest eax, eax\njle loc_15E2\nlea rax, [r13+rax*8+0]\nmov [rsp+88h+var_58], r13\nmov [rsp+88h+var_60], rax\nlea eax, [rbx+1]\nmov [rsp+88h+var_6C], eax\nmov [rsp+88h+var_50], r13\nmov [rsp+88h+var_68], r13\nnop dword ptr [rax]\nloc_14D8:\nmov rax, [rsp+88h+var_68]\nxor ebp, ebp\nmov r13, [rax]\nnop word ptr [rax+rax+00h]\nloc_14E8:\nmov rdi, r13; s\ncall _strlen\ncmp rax, rbp\njb loc_15A6\nloc_14F9:\nmovsxd r15, [rsp+88h+var_6C]\nmov rdi, r15; size\ncall _malloc\nmov rdx, rbp\nmov rcx, r15\nmov rsi, r13\nmov rdi, rax\nmov rbx, rax\ncall ___strncpy_chk\nmov rax, [rsp+88h+var_78]\nlea rsi, [r13+rbp+0]\nmov rdx, r15\nmovzx eax, byte ptr [rax]\nmov [rbx+rbp], al\nadd rbp, 1\ncmp r15, rbp\nlea rdi, [rbx+rbp]\ncmovb rdx, rbp\nsub rdx, rbp\ncall ___strcpy_chk\nmov rax, [rsp+88h+var_88]\nmov edx, [rax]\nmovsxd rsi, edx\ntest edx, edx\njle loc_1619\nmovsxd rsi, edx\nmov [rsp+88h+var_70], edx\nmov r12, r14\nmov [rsp+88h+var_80], rsi\nlea r15, [r14+rsi*8]\njmp short loc_157D\nloc_1570:\nadd r12, 8\ncmp r15, r12\njz loc_1610\nloc_157D:\nmov rdi, [r12]; s1\nmov rsi, rbx; s2\ncall _strcmp\ntest eax, eax\njnz short loc_1570\nmov rdi, rbx; ptr\ncall _free\nmov rdi, r13; s\ncall _strlen\ncmp rax, rbp\njnb loc_14F9\nloc_15A6:\nadd [rsp+88h+var_68], 8\nmov rcx, [rsp+88h+var_60]\nmov rax, [rsp+88h+var_68]\ncmp rax, rcx\njnz loc_14D8\nmov r13, [rsp+88h+var_58]\nmov rbp, [rsp+88h+var_50]\nmov rbx, rcx\nnop dword ptr [rax+00h]\nloc_15D0:\nmov rdi, [rbp+0]; ptr\nadd rbp, 8\ncall _free\ncmp rbp, rbx\njnz short loc_15D0\nloc_15E2:\nmov rax, [rsp+88h+var_40]\nsub rax, fs:28h\njnz short loc_1668\nadd rsp, 58h\nmov rdi, r13; ptr\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\njmp _free\nloc_1610:\nmov edx, [rsp+88h+var_70]\nmov rsi, [rsp+88h+var_80]\nloc_1619:\nmov rax, [rsp+88h+var_88]\nlea ecx, [rdx+1]\nmov [r14+rsi*8], rbx\nmov [rax], ecx\njmp loc_14E8\nloc_162B:\nmov r15, [rsp+88h+var_88]\nlea rdi, aIndex24+0Bh; s\nmovsxd rax, dword ptr [r15]\nlea rbx, [r14+rax*8]\ncall _strdup\nmov [rbx], rax\nadd dword ptr [r15], 1\nmov rax, [rsp+88h+var_40]\nsub rax, fs:28h\njnz short loc_1668\nadd rsp, 58h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1668:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "void __fastcall sub_1440(const char *a1, const char **a2, int *a3)\n{\n int v4; // eax\n int v5; // ebx\n const char **v6; // r13\n size_t v7; // rbp\n const char *v8; // r13\n char *v9; // rbx\n const char *v10; // rsi\n size_t v11; // rdx\n int v12; // edx\n __int64 v13; // rsi\n const char **v14; // r12\n const char **v15; // r15\n void **v16; // rbp\n void *v17; // rdi\n char **v18; // rbx\n __int64 v20; // [rsp+8h] [rbp-80h]\n int v21; // [rsp+18h] [rbp-70h]\n int v22; // [rsp+1Ch] [rbp-6Ch]\n const char **v23; // [rsp+20h] [rbp-68h]\n const char **v24; // [rsp+28h] [rbp-60h]\n const char **v25; // [rsp+30h] [rbp-58h]\n void **v26; // [rsp+38h] [rbp-50h]\n int v27; // [rsp+44h] [rbp-44h] BYREF\n unsigned __int64 v28; // [rsp+48h] [rbp-40h]\n\n v28 = __readfsqword(0x28u);\n v4 = strlen(a1);\n if ( v4 )\n {\n v5 = v4;\n v27 = 0;\n v6 = (const char **)malloc(0x4EC00uLL);\n sub_1440(a1 + 1, v6, &v27);\n if ( v27 > 0 )\n {\n v25 = v6;\n v24 = &v6[v27];\n v22 = v5 + 1;\n v26 = (void **)v6;\n v23 = v6;\n do\n {\n v7 = 0LL;\n v8 = *v23;\n while ( strlen(v8) >= v7 )\n {\n while ( 2 )\n {\n v9 = (char *)malloc(v22);\n __strncpy_chk(v9, v8, v7, v22);\n v10 = &v8[v7];\n v11 = v22;\n v9[v7++] = *a1;\n if ( v22 < v7 )\n v11 = v7;\n __strcpy_chk(&v9[v7], v10, v11 - v7);\n v12 = *a3;\n v13 = *a3;\n if ( *a3 > 0 )\n {\n v21 = *a3;\n v14 = a2;\n v20 = v12;\n v15 = &a2[v12];\n while ( strcmp(*v14, v9) )\n {\n if ( v15 == ++v14 )\n {\n v12 = v21;\n v13 = v20;\n goto LABEL_18;\n }\n }\n free(v9);\n if ( strlen(v8) >= v7 )\n continue;\n goto LABEL_13;\n }\n break;\n }\nLABEL_18:\n a2[v13] = v9;\n *a3 = v12 + 1;\n }\nLABEL_13:\n ++v23;\n }\n while ( v23 != v24 );\n v6 = v25;\n v16 = v26;\n do\n {\n v17 = *v16++;\n free(v17);\n }\n while ( v16 != (void **)v24 );\n }\n free(v6);\n }\n else\n {\n v18 = (char **)&a2[*a3];\n *v18 = strdup(\"\");\n ++*a3;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1440(const char *a1, const char **a2, int *a3) {\n int v4;\n int v5;\n const char **v6;\n unsigned int v7;\n const char *v8;\n char *v9;\n const char *v10;\n unsigned int v11;\n int v12;\n long long v13;\n const char **v14;\n const char **v15;\n void **v16;\n void *v17;\n char **v18;\n long long v20;\n int v21;\n int v22;\n const char **v23;\n const char **v24;\n const char **v25;\n void **v26;\n int v27;\n unsigned long long v28;\n v28 = __readfsqword(40u);\n v4 = strlen(a1);\n if (v4) {\n v5 = v4;\n v27 = 0;\n v6 = (const char **)malloc(322560uLL);\n sub_1440(a1 + 1, v6, &v27);\n if (v27 > 0) {\n v25 = v6;\n v24 = &v6[v27];\n v22 = v5 + 1;\n v26 = (void **)v6;\n v23 = v6;\n do {\n v7 = 0LL;\n v8 = *v23;\n while (strlen(v8) >= v7) {\n while (2) {\n v9 = (char *)malloc(v22);\n __strncpy_chk(v9, v8, v7, v22);\n v10 = &v8[v7];\n v11 = v22;\n v9[v7++] = *a1;\n if (v22 < v7) v11 = v7;\n __strcpy_chk(&v9[v7], v10, v11 - v7);\n v12 = *a3;\n v13 = *a3;\n if (*a3 > 0) {\n v21 = *a3;\n v14 = a2;\n v20 = v12;\n v15 = &a2[v12];\n while (strcmp(*v14, v9)) {\n if (v15 == ++v14) {\n v12 = v21;\n v13 = v20;\n goto LABEL_18;\n }\n }\n free(v9);\n if (strlen(v8) >= v7) continue;\n goto LABEL_13;\n }\n break;\n }\n LABEL_18:\n a2[v13] = v9;\n *a3 = v12 + 1;\n }\n LABEL_13:\n ++v23;\n } while (v23 != v24);\n v6 = v25;\n v16 = v26;\n do {\n v17 = *v16++;\n free(v17);\n } while (v16 != (void **)v24);\n }\n free(v6);\n } else {\n v18 = (char **)&a2[*a3];\n *v18 = strdup(\"\");\n ++*a3;\n }\n}", + "ida_pseudo_norm": "void func0(const char *a1, const char **a2, int *a3) {\n int v4;\n int v5;\n const char **v6;\n unsigned int v7;\n const char *v8;\n char *v9;\n const char *v10;\n unsigned int v11;\n int v12;\n long long v13;\n const char **v14;\n const char **v15;\n void **v16;\n void *v17;\n char **v18;\n long long v20;\n int v21;\n int v22;\n const char **v23;\n const char **v24;\n const char **v25;\n void **v26;\n int v27;\n unsigned long long v28;\n v28 = __readfsqword(40u);\n v4 = strlen(a1);\n if (v4) {\n v5 = v4;\n v27 = 0;\n v6 = (const char **)malloc(322560uLL);\n func0(a1 + 1, v6, &v27);\n if (v27 > 0) {\n v25 = v6;\n v24 = &v6[v27];\n v22 = v5 + 1;\n v26 = (void **)v6;\n v23 = v6;\n do {\n v7 = 0LL;\n v8 = *v23;\n while (strlen(v8) >= v7) {\n while (2) {\n v9 = (char *)malloc(v22);\n __strncpy_chk(v9, v8, v7, v22);\n v10 = &v8[v7];\n v11 = v22;\n v9[v7++] = *a1;\n if (v22 < v7) v11 = v7;\n __strcpy_chk(&v9[v7], v10, v11 - v7);\n v12 = *a3;\n v13 = *a3;\n if (*a3 > 0) {\n v21 = *a3;\n v14 = a2;\n v20 = v12;\n v15 = &a2[v12];\n while (strcmp(*v14, v9)) {\n if (v15 == ++v14) {\n v12 = v21;\n v13 = v20;\n goto LABEL_18;\n }\n }\n free(v9);\n if (strlen(v8) >= v7) continue;\n goto LABEL_13;\n }\n break;\n }\n LABEL_18:\n a2[v13] = v9;\n *a3 = v12 + 1;\n }\n LABEL_13:\n ++v23;\n } while (v23 != v24);\n v6 = v25;\n v16 = v26;\n do {\n v17 = *v16++;\n free(v17);\n } while (v16 != (void **)v24);\n }\n free(v6);\n } else {\n v18 = (char **)&a2[*a3];\n *v18 = strdup(\"\");\n ++*a3;\n }\n}" + }, + { + "index": 375, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n, int m) {\n int a = (n / m) * m;\n int b = a + m;\n return (n - a > b - n) ? b : a;\n}", + "test": "int main() {\n\n assert(func0(4722, 10) == 4720);\n\n assert(func0(1111, 5) == 1110);\n\n assert(func0(219, 2) == 218);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov -0x14(%rbp),%eax\ncltd\nidivl -0x18(%rbp)\nmov %eax,%edx\nmov -0x18(%rbp),%eax\nimul %edx,%eax\nmov %eax,-0x8(%rbp)\nmov -0x8(%rbp),%edx\nmov -0x18(%rbp),%eax\nadd %edx,%eax\nmov %eax,-0x4(%rbp)\nmov -0x14(%rbp),%eax\nsub -0x8(%rbp),%eax\nmov %eax,%edx\nmov -0x4(%rbp),%eax\nsub -0x14(%rbp),%eax\ncmp %eax,%edx\njle 118b \nmov -0x4(%rbp),%eax\njmp 118e \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_18]\nmov edx, eax\nmov eax, [rbp+var_18]\nimul eax, edx\nmov [rbp+var_8], eax\nmov edx, [rbp+var_8]\nmov eax, [rbp+var_18]\nadd eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_14]\nsub eax, [rbp+var_8]\nmov edx, eax\nmov eax, [rbp+var_4]\nsub eax, [rbp+var_14]\ncmp edx, eax\njle short loc_118B\nmov eax, [rbp+var_4]\njmp short loc_118E\nloc_118B:\nmov eax, [rbp+var_8]\nloc_118E:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n if ( a1 % a2 <= a1 / a2 * a2 + a2 - a1 )\n return (unsigned int)(a1 / a2 * a2);\n else\n return (unsigned int)(a1 / a2 * a2 + a2);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_18]\nmov edx, eax\nmov eax, [rbp+var_18]\nimul eax, edx\nmov [rbp+var_8], eax\nmov edx, [rbp+var_8]\nmov eax, [rbp+var_18]\nadd eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_14]\nsub eax, [rbp+var_8]\nmov edx, eax\nmov eax, [rbp+var_4]\nsub eax, [rbp+var_14]\ncmp edx, eax\njle short loc_118B\nmov eax, [rbp+var_4]\njmp short loc_118E\nloc_118B:\nmov eax, [rbp+var_8]\nloc_118E:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2)\n{\n if ( a1 % a2 <= a1 / a2 * a2 + a2 - a1 )\n return (unsigned int)(a1 / a2 * a2);\n else\n return (unsigned int)(a1 / a2 * a2 + a2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2) {\n if (a1 % a2 <= a1 / a2 * a2 + a2 - a1)\n return (unsigned int)(a1 / a2 * a2);\n else\n return (unsigned int)(a1 / a2 * a2 + a2);\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n if (a1 % a2 <= a1 / a2 * a2 + a2 - a1)\n return (unsigned int)(a1 / a2 * a2);\n else\n return (unsigned int)(a1 / a2 * a2 + a2);\n}" + }, + { + "index": 376, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int *arr;\n\n int length;\n\n} Tuple;\n\n\n\n", + "func": "Tuple func0(Tuple test_tup) {\n bool found[256] = {false};\n Tuple res;\n res.arr = (int*)malloc(test_tup.length * sizeof(int));\n res.length = test_tup.length;\n for (int i = 0; i < test_tup.length; i++) {\n int ele = test_tup.arr[i];\n if (!found[ele]) {\n res.arr[i] = ele;\n found[ele] = true;\n } else {\n res.arr[i] = -1;\n }\n }\n return res;\n}", + "test": "int main() {\n\n Tuple tuple1 = { (int[]){1, 1, 4, 4, 4, 5, 5, 6, 7, 7}, 10 };\n\n Tuple res1 = func0(tuple1);\n\n int expected1[10] = {1, -1, 4, -1, -1, 5, -1, 6, 7, -1};\n\n for (int i = 0; i < 10; i++) {\n\n assert(res1.arr[i] == expected1[i]);\n\n }\n\n\n\n Tuple tuple2 = { (int[]){2, 3, 4, 4, 5, 6, 6, 7, 8, 9, 9}, 11 };\n\n Tuple res2 = func0(tuple2);\n\n int expected2[11] = {2, 3, 4, -1, 5, 6, -1, 7, 8, 9, -1};\n\n for (int i = 0; i < 11; i++) {\n\n assert(res2.arr[i] == expected2[i]);\n\n }\n\n\n\n Tuple tuple3 = { (int[]){2, 2, 5, 4, 5, 7, 5, 6, 7, 7}, 10 };\n\n Tuple res3 = func0(tuple3);\n\n int expected3[10] = {2, -1, 5, 4, -1, 7, -1, 6, -1, -1};\n\n for (int i = 0; i < 10; i++) {\n\n assert(res3.arr[i] == expected3[i]);\n\n }\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x140,%rsp\nmov %rdi,%rax\nmov %rsi,%rcx\nmov %rcx,%rdx\nmov %rax,-0x140(%rbp)\nmov %rdx,-0x138(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea -0x110(%rbp),%rdx\nmov $0x0,%eax\nmov $0x20,%ecx\nmov %rdx,%rdi\nrep stos %rax,%es:(%rdi)\nmov -0x138(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x120(%rbp)\nmov -0x138(%rbp),%eax\nmov %eax,-0x118(%rbp)\nmovl $0x0,-0x128(%rbp)\njmpq 12b6 \nmov -0x140(%rbp),%rax\nmov -0x128(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x2,%rdx\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x124(%rbp)\nmov -0x124(%rbp),%eax\ncltq\nmovzbl -0x110(%rbp,%rax,1),%eax\nxor $0x1,%eax\ntest %al,%al\nje 1292 \nmov -0x120(%rbp),%rax\nmov -0x128(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x2,%rdx\nadd %rax,%rdx\nmov -0x124(%rbp),%eax\nmov %eax,(%rdx)\nmov -0x124(%rbp),%eax\ncltq\nmovb $0x1,-0x110(%rbp,%rax,1)\njmp 12af \nmov -0x120(%rbp),%rax\nmov -0x128(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x2,%rdx\nadd %rdx,%rax\nmovl $0xffffffff,(%rax)\naddl $0x1,-0x128(%rbp)\nmov -0x138(%rbp),%eax\ncmp %eax,-0x128(%rbp)\njl 122b \nmov -0x120(%rbp),%rax\nmov -0x118(%rbp),%rdx\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 12ea \ncallq 1090 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 140h\nmov rax, rdi\nmov rcx, rsi\nmov rdx, rcx\nmov [rbp+var_140], rax\nmov [rbp+var_138], rdx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rdx, [rbp+var_110]\nmov eax, 0\nmov ecx, 20h ; ' '\nmov rdi, rdx\nrep stosq\nmov eax, dword ptr [rbp+var_138]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_120], rax\nmov eax, dword ptr [rbp+var_138]\nmov dword ptr [rbp+var_118], eax\nmov [rbp+var_128], 0\njmp loc_12B6\nloc_122B:\nmov rax, [rbp+var_140]\nmov edx, [rbp+var_128]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_124], eax\nmov eax, [rbp+var_124]\ncdqe\nmovzx eax, [rbp+rax+var_110]\nxor eax, 1\ntest al, al\njz short loc_1292\nmov rax, [rbp+var_120]\nmov edx, [rbp+var_128]\nmovsxd rdx, edx\nshl rdx, 2\nadd rdx, rax\nmov eax, [rbp+var_124]\nmov [rdx], eax\nmov eax, [rbp+var_124]\ncdqe\nmov [rbp+rax+var_110], 1\njmp short loc_12AF\nloc_1292:\nmov rax, [rbp+var_120]\nmov edx, [rbp+var_128]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov dword ptr [rax], 0FFFFFFFFh\nloc_12AF:\nadd [rbp+var_128], 1\nloc_12B6:\nmov eax, dword ptr [rbp+var_138]\ncmp [rbp+var_128], eax\njl loc_122B\nmov rax, [rbp+var_120]\nmov rdx, [rbp+var_118]\nmov rcx, [rbp+var_8]\nsub rcx, fs:28h\njz short locret_12EA\ncall ___stack_chk_fail\nlocret_12EA:\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-128h]\n int v4; // [rsp+1Ch] [rbp-124h]\n _DWORD *v5; // [rsp+20h] [rbp-120h]\n _BYTE v6[264]; // [rsp+30h] [rbp-110h] BYREF\n unsigned __int64 v7; // [rsp+138h] [rbp-8h]\n\n v7 = __readfsqword(0x28u);\n memset(v6, 0, 0x100uLL);\n v5 = malloc(4LL * a2);\n for ( i = 0; i < a2; ++i )\n {\n v4 = *(_DWORD *)(4LL * i + a1);\n if ( v6[v4] != 1 )\n {\n v5[i] = v4;\n v6[v4] = 1;\n }\n else\n {\n v5[i] = -1;\n }\n }\n return v5;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 140h\nmov rax, rdi\nmov rcx, rsi\nmov rdx, rcx\nmov [rbp+var_140], rax\nmov [rbp+var_138], rdx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rdx, [rbp+var_110]\nmov eax, 0\nmov ecx, 20h ; ' '\nmov rdi, rdx\nrep stosq\nmov eax, dword ptr [rbp+var_138]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_120], rax\nmov eax, dword ptr [rbp+var_138]\nmov dword ptr [rbp+var_118], eax\nmov [rbp+var_128], 0\njmp loc_12B6\nloc_122B:\nmov rax, [rbp+var_140]\nmov edx, [rbp+var_128]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_124], eax\nmov eax, [rbp+var_124]\ncdqe\nmovzx eax, [rbp+rax+var_110]\nxor eax, 1\ntest al, al\njz short loc_1292\nmov rax, [rbp+var_120]\nmov edx, [rbp+var_128]\nmovsxd rdx, edx\nshl rdx, 2\nadd rdx, rax\nmov eax, [rbp+var_124]\nmov [rdx], eax\nmov eax, [rbp+var_124]\ncdqe\nmov [rbp+rax+var_110], 1\njmp short loc_12AF\nloc_1292:\nmov rax, [rbp+var_120]\nmov edx, [rbp+var_128]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov dword ptr [rax], 0FFFFFFFFh\nloc_12AF:\nadd [rbp+var_128], 1\nloc_12B6:\nmov eax, dword ptr [rbp+var_138]\ncmp [rbp+var_128], eax\njl loc_122B\nmov rax, [rbp+var_120]\nmov rdx, [rbp+var_118]\nmov rcx, [rbp+var_8]\nsub rcx, fs:28h\njz short locret_12EA\ncall ___stack_chk_fail\nlocret_12EA:\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-128h]\n int v4; // [rsp+1Ch] [rbp-124h]\n _DWORD *v5; // [rsp+20h] [rbp-120h]\n _BYTE v6[264]; // [rsp+30h] [rbp-110h] BYREF\n unsigned __int64 v7; // [rsp+138h] [rbp-8h]\n\n v7 = __readfsqword(0x28u);\n memset(v6, 0, 0x100uLL);\n v5 = malloc(4LL * a2);\n for ( i = 0; i < a2; ++i )\n {\n v4 = *(_DWORD *)(4LL * i + a1);\n if ( v6[v4] != 1 )\n {\n v5[i] = v4;\n v6[v4] = 1;\n }\n else\n {\n v5[i] = -1;\n }\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(long long a1, int a2) {\n int i;\n int v4;\n uint32_t *v5;\n uint8_t v6[264];\n unsigned long long v7;\n v7 = __readfsqword(40u);\n memset(v6, 0, 256uLL);\n v5 = malloc(4LL * a2);\n for (i = 0; i < a2; ++i) {\n v4 = *(uint32_t *)(4LL * i + a1);\n if (v6[v4] != 1) {\n v5[i] = v4;\n v6[v4] = 1;\n } else {\n v5[i] = -1;\n }\n }\n return v5;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2) {\n int i;\n int v4;\n uint32_t *v5;\n uint8_t v6[264];\n unsigned long long v7;\n v7 = __readfsqword(40u);\n memset(v6, 0, 256uLL);\n v5 = malloc(4LL * a2);\n for (i = 0; i < a2; ++i) {\n v4 = *(uint32_t *)(4LL * i + a1);\n if (v6[v4] != 1) {\n v5[i] = v4;\n v6[v4] = 1;\n } else {\n v5[i] = -1;\n }\n }\n return v5;\n}" + }, + { + "index": 376, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int *arr;\n\n int length;\n\n} Tuple;\n\n\n\n", + "func": "Tuple func0(Tuple test_tup) {\n bool found[256] = {false};\n Tuple res;\n res.arr = (int*)malloc(test_tup.length * sizeof(int));\n res.length = test_tup.length;\n for (int i = 0; i < test_tup.length; i++) {\n int ele = test_tup.arr[i];\n if (!found[ele]) {\n res.arr[i] = ele;\n found[ele] = true;\n } else {\n res.arr[i] = -1;\n }\n }\n return res;\n}", + "test": "int main() {\n\n Tuple tuple1 = { (int[]){1, 1, 4, 4, 4, 5, 5, 6, 7, 7}, 10 };\n\n Tuple res1 = func0(tuple1);\n\n int expected1[10] = {1, -1, 4, -1, -1, 5, -1, 6, 7, -1};\n\n for (int i = 0; i < 10; i++) {\n\n assert(res1.arr[i] == expected1[i]);\n\n }\n\n\n\n Tuple tuple2 = { (int[]){2, 3, 4, 4, 5, 6, 6, 7, 8, 9, 9}, 11 };\n\n Tuple res2 = func0(tuple2);\n\n int expected2[11] = {2, 3, 4, -1, 5, 6, -1, 7, 8, 9, -1};\n\n for (int i = 0; i < 11; i++) {\n\n assert(res2.arr[i] == expected2[i]);\n\n }\n\n\n\n Tuple tuple3 = { (int[]){2, 2, 5, 4, 5, 7, 5, 6, 7, 7}, 10 };\n\n Tuple res3 = func0(tuple3);\n\n int expected3[10] = {2, -1, 5, 4, -1, 7, -1, 6, -1, -1};\n\n for (int i = 0; i < 10; i++) {\n\n assert(res3.arr[i] == expected3[i]);\n\n }\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x118,%rsp\nmov %rdi,%rbp\nmov %rsi,%rbx\nmov %fs:0x28,%rax\nmov %rax,0x108(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nmov $0x20,%ecx\nrep stos %rax,%es:(%rdi)\nmovslq %esi,%rdi\nshl $0x2,%rdi\ncallq 10b0 \ntest %ebx,%ebx\njle 1220 \nmov %rbp,%rdi\nlea -0x1(%rbx),%r8d\nmov $0x0,%edx\njmp 120b \nmovl $0xffffffff,(%rax,%rdx,4)\nlea 0x1(%rdx),%rcx\ncmp %r8,%rdx\nje 1220 \nmov %rcx,%rdx\nmov (%rdi,%rdx,4),%ecx\nmovslq %ecx,%rsi\ncmpb $0x0,(%rsp,%rsi,1)\njne 11f8 \nmov %ecx,(%rax,%rdx,4)\nmovb $0x1,(%rsp,%rsi,1)\njmp 11ff \nmov %ebx,%edx\nmov 0x108(%rsp),%rbx\nxor %fs:0x28,%rbx\njne 123f \nadd $0x118,%rsp\npop %rbx\npop %rbp\nretq\ncallq 1090 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 110h\nmov rbp, rdi\nmov r12, rsi\nmov rax, fs:28h\nmov [rsp+128h+var_20], rax\nxor eax, eax\nmov rdi, rsp\nmov ecx, 20h ; ' '\nrep stosq\nmovsxd rbx, esi\nshl rbx, 2\nmov rdi, rbx; size\ncall _malloc\ntest r12d, r12d\njle short loc_121D\nmov edx, 0\njmp short loc_1207\nloc_11F7:\nmov dword ptr [rax+rdx], 0FFFFFFFFh\nloc_11FE:\nadd rdx, 4\ncmp rbx, rdx\njz short loc_121D\nloc_1207:\nmov ecx, [rbp+rdx+0]\nmovsxd rsi, ecx\ncmp [rsp+rsi+128h+var_128], 0\njnz short loc_11F7\nmov [rax+rdx], ecx\nmov [rsp+rsi+128h+var_128], 1\njmp short loc_11FE\nloc_121D:\nmov edx, r12d\nmov rcx, [rsp+128h+var_20]\nsub rcx, fs:28h\njnz short loc_123F\nadd rsp, 110h\npop rbx\npop rbp\npop r12\nretn\nloc_123F:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2)\n{\n char *result; // rax\n __int64 v3; // rdx\n int v4; // ecx\n _BYTE v5[264]; // [rsp+0h] [rbp-128h] BYREF\n unsigned __int64 v6; // [rsp+108h] [rbp-20h]\n\n v6 = __readfsqword(0x28u);\n memset(v5, 0, 0x100uLL);\n result = (char *)malloc(4LL * a2);\n if ( a2 > 0 )\n {\n v3 = 0LL;\n do\n {\n v4 = *(_DWORD *)(a1 + v3);\n if ( v5[v4] )\n {\n *(_DWORD *)&result[v3] = -1;\n }\n else\n {\n *(_DWORD *)&result[v3] = v4;\n v5[v4] = 1;\n }\n v3 += 4LL;\n }\n while ( 4LL * a2 != v3 );\n }\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 110h\nmov rbp, rdi\nmov r12, rsi\nmov rax, fs:28h\nmov [rsp+128h+var_20], rax\nxor eax, eax\nmov rdi, rsp\nmov ecx, 20h ; ' '\nrep stosq\nmovsxd rbx, esi\nshl rbx, 2\nmov rdi, rbx; size\ncall _malloc\ntest r12d, r12d\njle short loc_121D\nmov edx, 0\njmp short loc_1207\nloc_11F7:\nmov dword ptr [rax+rdx], 0FFFFFFFFh\nloc_11FE:\nadd rdx, 4\ncmp rbx, rdx\njz short loc_121D\nloc_1207:\nmov ecx, [rbp+rdx+0]\nmovsxd rsi, ecx\ncmp [rsp+rsi+128h+var_128], 0\njnz short loc_11F7\nmov [rax+rdx], ecx\nmov [rsp+rsi+128h+var_128], 1\njmp short loc_11FE\nloc_121D:\nmov edx, r12d\nmov rcx, [rsp+128h+var_20]\nsub rcx, fs:28h\njnz short loc_123F\nadd rsp, 110h\npop rbx\npop rbp\npop r12\nretn\nloc_123F:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_11A9(__int64 a1, int a2)\n{\n char *result; // rax\n __int64 v3; // rdx\n int v4; // ecx\n _BYTE v5[264]; // [rsp+0h] [rbp-128h] BYREF\n unsigned __int64 v6; // [rsp+108h] [rbp-20h]\n\n v6 = __readfsqword(0x28u);\n memset(v5, 0, 0x100uLL);\n result = (char *)malloc(4LL * a2);\n if ( a2 > 0 )\n {\n v3 = 0LL;\n do\n {\n v4 = *(_DWORD *)(a1 + v3);\n if ( v5[v4] )\n {\n *(_DWORD *)&result[v3] = -1;\n }\n else\n {\n *(_DWORD *)&result[v3] = v4;\n v5[v4] = 1;\n }\n v3 += 4LL;\n }\n while ( 4LL * a2 != v3 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11A9(long long a1, int a2) {\n char *result;\n long long v3;\n int v4;\n uint8_t v5[264];\n unsigned long long v6;\n v6 = __readfsqword(40u);\n memset(v5, 0, 256uLL);\n result = (char *)malloc(4LL * a2);\n if (a2 > 0) {\n v3 = 0LL;\n do {\n v4 = *(uint32_t *)(a1 + v3);\n if (v5[v4]) {\n *(uint32_t *)&result[v3] = -1;\n } else {\n *(uint32_t *)&result[v3] = v4;\n v5[v4] = 1;\n }\n v3 += 4LL;\n } while (4LL * a2 != v3);\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2) {\n char *result;\n long long v3;\n int v4;\n uint8_t v5[264];\n unsigned long long v6;\n v6 = __readfsqword(40u);\n memset(v5, 0, 256uLL);\n result = (char *)malloc(4LL * a2);\n if (a2 > 0) {\n v3 = 0LL;\n do {\n v4 = *(uint32_t *)(a1 + v3);\n if (v5[v4]) {\n *(uint32_t *)&result[v3] = -1;\n } else {\n *(uint32_t *)&result[v3] = v4;\n v5[v4] = 1;\n }\n v3 += 4LL;\n } while (4LL * a2 != v3);\n }\n return result;\n}" + }, + { + "index": 376, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int *arr;\n\n int length;\n\n} Tuple;\n\n\n\n", + "func": "Tuple func0(Tuple test_tup) {\n bool found[256] = {false};\n Tuple res;\n res.arr = (int*)malloc(test_tup.length * sizeof(int));\n res.length = test_tup.length;\n for (int i = 0; i < test_tup.length; i++) {\n int ele = test_tup.arr[i];\n if (!found[ele]) {\n res.arr[i] = ele;\n found[ele] = true;\n } else {\n res.arr[i] = -1;\n }\n }\n return res;\n}", + "test": "int main() {\n\n Tuple tuple1 = { (int[]){1, 1, 4, 4, 4, 5, 5, 6, 7, 7}, 10 };\n\n Tuple res1 = func0(tuple1);\n\n int expected1[10] = {1, -1, 4, -1, -1, 5, -1, 6, 7, -1};\n\n for (int i = 0; i < 10; i++) {\n\n assert(res1.arr[i] == expected1[i]);\n\n }\n\n\n\n Tuple tuple2 = { (int[]){2, 3, 4, 4, 5, 6, 6, 7, 8, 9, 9}, 11 };\n\n Tuple res2 = func0(tuple2);\n\n int expected2[11] = {2, 3, 4, -1, 5, 6, -1, 7, 8, 9, -1};\n\n for (int i = 0; i < 11; i++) {\n\n assert(res2.arr[i] == expected2[i]);\n\n }\n\n\n\n Tuple tuple3 = { (int[]){2, 2, 5, 4, 5, 7, 5, 6, 7, 7}, 10 };\n\n Tuple res3 = func0(tuple3);\n\n int expected3[10] = {2, -1, 5, 4, -1, 7, -1, 6, -1, -1};\n\n for (int i = 0; i < 10; i++) {\n\n assert(res3.arr[i] == expected3[i]);\n\n }\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov $0x20,%ecx\nmov %rsi,%rbp\npush %rbx\nmov %rdi,%rbx\nsub $0x118,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x108(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nrep stos %rax,%es:(%rdi)\nmovslq %esi,%rdi\nshl $0x2,%rdi\ncallq 10b0 \nlea -0x1(%rbp),%r9d\nxor %ecx,%ecx\ntest %ebp,%ebp\njg 1543 \njmp 155d \nnopl 0x0(%rax)\nmov %edi,(%rax,%rcx,4)\nmovb $0x1,(%rsp,%rdi,1)\nlea 0x1(%rcx),%rdi\ncmp %rcx,%r9\nje 155d \nmov %rdi,%rcx\nmovslq (%rbx,%rcx,4),%rdi\ncmpb $0x0,(%rsp,%rdi,1)\nje 1530 \nmovl $0xffffffff,(%rax,%rcx,4)\nlea 0x1(%rcx),%rdi\ncmp %rcx,%r9\njne 1540 \nmov 0x108(%rsp),%rsi\nxor %fs:0x28,%rsi\nmov %ebp,%edx\njne 157c \nadd $0x118,%rsp\npop %rbx\npop %rbp\nretq\ncallq 1090 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r12\nmov ecx, 20h ; ' '\nmov r12, rsi\npush rbp\nmov rbp, rdi\npush rbx\nmovsxd rbx, esi\nshl rbx, 2\nsub rsp, 110h\nmov rax, fs:28h\nmov [rsp+128h+var_20], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\nmov rdi, rbx; size\ncall _malloc\nxor ecx, ecx\ntest r12d, r12d\njg short loc_1450\njmp short loc_146B\nloc_1440:\nmov [rax+rcx], esi\nadd rcx, 4\nmov [rsp+rsi+128h+var_128], 1\ncmp rbx, rcx\njz short loc_146B\nloc_1450:\nmovsxd rsi, dword ptr [rbp+rcx+0]\ncmp [rsp+rsi+128h+var_128], 0\njz short loc_1440\nmov dword ptr [rax+rcx], 0FFFFFFFFh\nadd rcx, 4\ncmp rbx, rcx\njnz short loc_1450\nloc_146B:\nmov edx, r12d\nmov rcx, [rsp+128h+var_20]\nsub rcx, fs:28h\njnz short loc_148D\nadd rsp, 110h\npop rbx\npop rbp\npop r12\nretn\nloc_148D:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2)\n{\n size_t v2; // rbx\n char *result; // rax\n __int64 v4; // rcx\n __int64 v5; // rsi\n _BYTE v6[264]; // [rsp+0h] [rbp-128h] BYREF\n unsigned __int64 v7; // [rsp+108h] [rbp-20h]\n\n v2 = 4LL * a2;\n v7 = __readfsqword(0x28u);\n memset(v6, 0, 0x100uLL);\n result = (char *)malloc(v2);\n v4 = 0LL;\n if ( a2 > 0 )\n {\n do\n {\n while ( 1 )\n {\n v5 = *(int *)(a1 + v4);\n if ( v6[v5] )\n break;\n *(_DWORD *)&result[v4] = v5;\n v4 += 4LL;\n v6[v5] = 1;\n if ( v2 == v4 )\n return result;\n }\n *(_DWORD *)&result[v4] = -1;\n v4 += 4LL;\n }\n while ( v2 != v4 );\n }\n return result;\n}", + "ida_strip_asm": "sub_13F0:\nendbr64\npush r12\nmov ecx, 20h ; ' '\nmov r12, rsi\npush rbp\nmov rbp, rdi\npush rbx\nmovsxd rbx, esi\nshl rbx, 2\nsub rsp, 110h\nmov rax, fs:28h\nmov [rsp+128h+var_20], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\nmov rdi, rbx; size\ncall _malloc\nxor ecx, ecx\ntest r12d, r12d\njg short loc_1450\njmp short loc_146B\nloc_1440:\nmov [rax+rcx], esi\nadd rcx, 4\nmov [rsp+rsi+128h+var_128], 1\ncmp rbx, rcx\njz short loc_146B\nloc_1450:\nmovsxd rsi, dword ptr [rbp+rcx+0]\ncmp [rsp+rsi+128h+var_128], 0\njz short loc_1440\nmov dword ptr [rax+rcx], 0FFFFFFFFh\nadd rcx, 4\ncmp rbx, rcx\njnz short loc_1450\nloc_146B:\nmov edx, r12d\nmov rcx, [rsp+128h+var_20]\nsub rcx, fs:28h\njnz short loc_148D\nadd rsp, 110h\npop rbx\npop rbp\npop r12\nretn\nloc_148D:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_13F0(__int64 a1, int a2)\n{\n size_t v2; // rbx\n char *result; // rax\n __int64 v4; // rcx\n __int64 v5; // rsi\n _BYTE v6[264]; // [rsp+0h] [rbp-128h] BYREF\n unsigned __int64 v7; // [rsp+108h] [rbp-20h]\n\n v2 = 4LL * a2;\n v7 = __readfsqword(0x28u);\n memset(v6, 0, 0x100uLL);\n result = (char *)malloc(v2);\n v4 = 0LL;\n if ( a2 > 0 )\n {\n do\n {\n while ( 1 )\n {\n v5 = *(int *)(a1 + v4);\n if ( v6[v5] )\n break;\n *(_DWORD *)&result[v4] = v5;\n v4 += 4LL;\n v6[v5] = 1;\n if ( v2 == v4 )\n return result;\n }\n *(_DWORD *)&result[v4] = -1;\n v4 += 4LL;\n }\n while ( v2 != v4 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_13F0(long long a1, int a2) {\n unsigned int v2;\n char *result;\n long long v4;\n long long v5;\n uint8_t v6[264];\n unsigned long long v7;\n v2 = 4LL * a2;\n v7 = __readfsqword(40u);\n memset(v6, 0, 256uLL);\n result = (char *)malloc(v2);\n v4 = 0LL;\n if (a2 > 0) {\n do {\n while (1) {\n v5 = *(int *)(a1 + v4);\n if (v6[v5]) break;\n *(uint32_t *)&result[v4] = v5;\n v4 += 4LL;\n v6[v5] = 1;\n if (v2 == v4) return result;\n }\n *(uint32_t *)&result[v4] = -1;\n v4 += 4LL;\n } while (v2 != v4);\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2) {\n unsigned int v2;\n char *result;\n long long v4;\n long long v5;\n uint8_t v6[264];\n unsigned long long v7;\n v2 = 4LL * a2;\n v7 = __readfsqword(40u);\n memset(v6, 0, 256uLL);\n result = (char *)malloc(v2);\n v4 = 0LL;\n if (a2 > 0) {\n do {\n while (1) {\n v5 = *(int *)(a1 + v4);\n if (v6[v5]) break;\n *(uint32_t *)&result[v4] = v5;\n v4 += 4LL;\n v6[v5] = 1;\n if (v2 == v4) return result;\n }\n *(uint32_t *)&result[v4] = -1;\n v4 += 4LL;\n } while (v2 != v4);\n }\n return result;\n}" + }, + { + "index": 376, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int *arr;\n\n int length;\n\n} Tuple;\n\n\n\n", + "func": "Tuple func0(Tuple test_tup) {\n bool found[256] = {false};\n Tuple res;\n res.arr = (int*)malloc(test_tup.length * sizeof(int));\n res.length = test_tup.length;\n for (int i = 0; i < test_tup.length; i++) {\n int ele = test_tup.arr[i];\n if (!found[ele]) {\n res.arr[i] = ele;\n found[ele] = true;\n } else {\n res.arr[i] = -1;\n }\n }\n return res;\n}", + "test": "int main() {\n\n Tuple tuple1 = { (int[]){1, 1, 4, 4, 4, 5, 5, 6, 7, 7}, 10 };\n\n Tuple res1 = func0(tuple1);\n\n int expected1[10] = {1, -1, 4, -1, -1, 5, -1, 6, 7, -1};\n\n for (int i = 0; i < 10; i++) {\n\n assert(res1.arr[i] == expected1[i]);\n\n }\n\n\n\n Tuple tuple2 = { (int[]){2, 3, 4, 4, 5, 6, 6, 7, 8, 9, 9}, 11 };\n\n Tuple res2 = func0(tuple2);\n\n int expected2[11] = {2, 3, 4, -1, 5, 6, -1, 7, 8, 9, -1};\n\n for (int i = 0; i < 11; i++) {\n\n assert(res2.arr[i] == expected2[i]);\n\n }\n\n\n\n Tuple tuple3 = { (int[]){2, 2, 5, 4, 5, 7, 5, 6, 7, 7}, 10 };\n\n Tuple res3 = func0(tuple3);\n\n int expected3[10] = {2, -1, 5, 4, -1, 7, -1, 6, -1, -1};\n\n for (int i = 0; i < 10; i++) {\n\n assert(res3.arr[i] == expected3[i]);\n\n }\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov $0x20,%ecx\nmov %rsi,%rbp\npush %rbx\nmov %rdi,%rbx\nsub $0x118,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x108(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nrep stos %rax,%es:(%rdi)\nmovslq %esi,%rdi\nshl $0x2,%rdi\ncallq 10b0 \nlea -0x1(%rbp),%r9d\nxor %ecx,%ecx\ntest %ebp,%ebp\njg 15a3 \njmp 15bd \nnopl 0x0(%rax)\nmov %edi,(%rax,%rcx,4)\nmovb $0x1,(%rsp,%rdi,1)\nlea 0x1(%rcx),%rdi\ncmp %rcx,%r9\nje 15bd \nmov %rdi,%rcx\nmovslq (%rbx,%rcx,4),%rdi\ncmpb $0x0,(%rsp,%rdi,1)\nje 1590 \nmovl $0xffffffff,(%rax,%rcx,4)\nlea 0x1(%rcx),%rdi\ncmp %rcx,%r9\njne 15a0 \nmov 0x108(%rsp),%rsi\nxor %fs:0x28,%rsi\nmov %ebp,%edx\njne 15dc \nadd $0x118,%rsp\npop %rbx\npop %rbp\nretq\ncallq 1090 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r12\nmov ecx, 20h ; ' '\nmov r12, rsi\npush rbp\nmov rbp, rdi\npush rbx\nmovsxd rbx, esi\nshl rbx, 2\nsub rsp, 110h\nmov rax, fs:28h\nmov [rsp+128h+var_20], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\nmov rdi, rbx; size\ncall _malloc\nxor ecx, ecx\ntest r12d, r12d\njg short loc_1490\njmp short loc_14AB\nloc_1480:\nmov [rax+rcx], esi\nadd rcx, 4\nmov [rsp+rsi+128h+var_128], 1\ncmp rbx, rcx\njz short loc_14AB\nloc_1490:\nmovsxd rsi, dword ptr [rbp+rcx+0]\ncmp [rsp+rsi+128h+var_128], 0\njz short loc_1480\nmov dword ptr [rax+rcx], 0FFFFFFFFh\nadd rcx, 4\ncmp rbx, rcx\njnz short loc_1490\nloc_14AB:\nmov edx, r12d\nmov rcx, [rsp+128h+var_20]\nsub rcx, fs:28h\njnz short loc_14CD\nadd rsp, 110h\npop rbx\npop rbp\npop r12\nretn\nloc_14CD:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2)\n{\n size_t v2; // rbx\n char *result; // rax\n __int64 v4; // rcx\n __int64 v5; // rsi\n _BYTE v6[264]; // [rsp+0h] [rbp-128h] BYREF\n unsigned __int64 v7; // [rsp+108h] [rbp-20h]\n\n v2 = 4LL * a2;\n v7 = __readfsqword(0x28u);\n memset(v6, 0, 0x100uLL);\n result = (char *)malloc(v2);\n v4 = 0LL;\n if ( a2 > 0 )\n {\n do\n {\n while ( 1 )\n {\n v5 = *(int *)(a1 + v4);\n if ( v6[v5] )\n break;\n *(_DWORD *)&result[v4] = v5;\n v4 += 4LL;\n v6[v5] = 1;\n if ( v2 == v4 )\n return result;\n }\n *(_DWORD *)&result[v4] = -1;\n v4 += 4LL;\n }\n while ( v2 != v4 );\n }\n return result;\n}", + "ida_strip_asm": "sub_1430:\nendbr64\npush r12\nmov ecx, 20h ; ' '\nmov r12, rsi\npush rbp\nmov rbp, rdi\npush rbx\nmovsxd rbx, esi\nshl rbx, 2\nsub rsp, 110h\nmov rax, fs:28h\nmov [rsp+128h+var_20], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\nmov rdi, rbx; size\ncall _malloc\nxor ecx, ecx\ntest r12d, r12d\njg short loc_1490\njmp short loc_14AB\nloc_1480:\nmov [rax+rcx], esi\nadd rcx, 4\nmov [rsp+rsi+128h+var_128], 1\ncmp rbx, rcx\njz short loc_14AB\nloc_1490:\nmovsxd rsi, dword ptr [rbp+rcx+0]\ncmp [rsp+rsi+128h+var_128], 0\njz short loc_1480\nmov dword ptr [rax+rcx], 0FFFFFFFFh\nadd rcx, 4\ncmp rbx, rcx\njnz short loc_1490\nloc_14AB:\nmov edx, r12d\nmov rcx, [rsp+128h+var_20]\nsub rcx, fs:28h\njnz short loc_14CD\nadd rsp, 110h\npop rbx\npop rbp\npop r12\nretn\nloc_14CD:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_1430(__int64 a1, int a2)\n{\n size_t v2; // rbx\n char *result; // rax\n __int64 v4; // rcx\n __int64 v5; // rsi\n _BYTE v6[264]; // [rsp+0h] [rbp-128h] BYREF\n unsigned __int64 v7; // [rsp+108h] [rbp-20h]\n\n v2 = 4LL * a2;\n v7 = __readfsqword(0x28u);\n memset(v6, 0, 0x100uLL);\n result = (char *)malloc(v2);\n v4 = 0LL;\n if ( a2 > 0 )\n {\n do\n {\n while ( 1 )\n {\n v5 = *(int *)(a1 + v4);\n if ( v6[v5] )\n break;\n *(_DWORD *)&result[v4] = v5;\n v4 += 4LL;\n v6[v5] = 1;\n if ( v2 == v4 )\n return result;\n }\n *(_DWORD *)&result[v4] = -1;\n v4 += 4LL;\n }\n while ( v2 != v4 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1430(long long a1, int a2) {\n unsigned int v2;\n char *result;\n long long v4;\n long long v5;\n uint8_t v6[264];\n unsigned long long v7;\n v2 = 4LL * a2;\n v7 = __readfsqword(40u);\n memset(v6, 0, 256uLL);\n result = (char *)malloc(v2);\n v4 = 0LL;\n if (a2 > 0) {\n do {\n while (1) {\n v5 = *(int *)(a1 + v4);\n if (v6[v5]) break;\n *(uint32_t *)&result[v4] = v5;\n v4 += 4LL;\n v6[v5] = 1;\n if (v2 == v4) return result;\n }\n *(uint32_t *)&result[v4] = -1;\n v4 += 4LL;\n } while (v2 != v4);\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2) {\n unsigned int v2;\n char *result;\n long long v4;\n long long v5;\n uint8_t v6[264];\n unsigned long long v7;\n v2 = 4LL * a2;\n v7 = __readfsqword(40u);\n memset(v6, 0, 256uLL);\n result = (char *)malloc(v2);\n v4 = 0LL;\n if (a2 > 0) {\n do {\n while (1) {\n v5 = *(int *)(a1 + v4);\n if (v6[v5]) break;\n *(uint32_t *)&result[v4] = v5;\n v4 += 4LL;\n v6[v5] = 1;\n if (v2 == v4) return result;\n }\n *(uint32_t *)&result[v4] = -1;\n v4 += 4LL;\n } while (v2 != v4);\n }\n return result;\n}" + }, + { + "index": 377, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* s, char c) {\n int counts = 0;\n for (int i = 0; s[i] != '\\0'; i++) {\n if (s[i] == c) {\n counts++;\n }\n }\n char* result = (char*)malloc(strlen(s) - counts + 1);\n int j = 0;\n for (int i = 0; s[i] != '\\0'; i++) {\n if (s[i] != c) {\n result[j] = s[i];\n j++;\n }\n }\n result[j] = '\\0';\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"aba\", 'a'), \"b\") == 0);\n\n assert(strcmp(func0(\"toggle\", 'g'), \"tole\") == 0);\n\n assert(strcmp(func0(\"aabbc\", 'b'), \"aac\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x28(%rbp)\nmov %esi,%eax\nmov %al,-0x2c(%rbp)\nmovl $0x0,-0x18(%rbp)\nmovl $0x0,-0x14(%rbp)\njmp 11eb \nmov -0x14(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp %al,-0x2c(%rbp)\njne 11e7 \naddl $0x1,-0x18(%rbp)\naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 11ce \nmov -0x28(%rbp),%rax\nmov %rax,%rdi\ncallq 1080 \nmov -0x18(%rbp),%edx\nmovslq %edx,%rdx\nsub %rdx,%rax\nadd $0x1,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 1270 \nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp %al,-0x2c(%rbp)\nje 126c \nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov -0x10(%rbp),%edx\nmovslq %edx,%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rax),%eax\nmov %al,(%rdx)\naddl $0x1,-0x10(%rbp)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 1234 \nmov -0x10(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmovb $0x0,(%rax)\nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov eax, esi\nmov [rbp+var_2C], al\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp short loc_11EB\nloc_11CE:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp [rbp+var_2C], al\njnz short loc_11E7\nadd [rbp+var_18], 1\nloc_11E7:\nadd [rbp+var_14], 1\nloc_11EB:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_11CE\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov eax, [rbp+var_18]\ncdqe\nsub rdx, rax\nlea rax, [rdx+1]\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp short loc_1272\nloc_1236:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp [rbp+var_2C], al\njz short loc_126E\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmov edx, [rbp+var_10]\nmovsxd rcx, edx\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmovzx eax, byte ptr [rax]\nmov [rdx], al\nadd [rbp+var_10], 1\nloc_126E:\nadd [rbp+var_C], 1\nloc_1272:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1236\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1, char a2)\n{\n size_t v2; // rax\n int v4; // [rsp+18h] [rbp-18h]\n int i; // [rsp+1Ch] [rbp-14h]\n int v6; // [rsp+20h] [rbp-10h]\n int j; // [rsp+24h] [rbp-Ch]\n _BYTE *v8; // [rsp+28h] [rbp-8h]\n\n v4 = 0;\n for ( i = 0; a1[i]; ++i )\n {\n if ( a2 == a1[i] )\n ++v4;\n }\n v2 = strlen(a1);\n v8 = malloc(v2 - v4 + 1);\n v6 = 0;\n for ( j = 0; a1[j]; ++j )\n {\n if ( a2 != a1[j] )\n v8[v6++] = a1[j];\n }\n v8[v6] = 0;\n return v8;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov eax, esi\nmov [rbp+var_2C], al\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp short loc_11EB\nloc_11CE:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp [rbp+var_2C], al\njnz short loc_11E7\nadd [rbp+var_18], 1\nloc_11E7:\nadd [rbp+var_14], 1\nloc_11EB:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_11CE\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov eax, [rbp+var_18]\ncdqe\nsub rdx, rax\nlea rax, [rdx+1]\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp short loc_1272\nloc_1236:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp [rbp+var_2C], al\njz short loc_126E\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmov edx, [rbp+var_10]\nmovsxd rcx, edx\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmovzx eax, byte ptr [rax]\nmov [rdx], al\nadd [rbp+var_10], 1\nloc_126E:\nadd [rbp+var_C], 1\nloc_1272:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1236\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_11A9(const char *a1, char a2)\n{\n size_t v2; // rax\n int v4; // [rsp+18h] [rbp-18h]\n int i; // [rsp+1Ch] [rbp-14h]\n int v6; // [rsp+20h] [rbp-10h]\n int j; // [rsp+24h] [rbp-Ch]\n _BYTE *v8; // [rsp+28h] [rbp-8h]\n\n v4 = 0;\n for ( i = 0; a1[i]; ++i )\n {\n if ( a2 == a1[i] )\n ++v4;\n }\n v2 = strlen(a1);\n v8 = malloc(v2 - v4 + 1);\n v6 = 0;\n for ( j = 0; a1[j]; ++j )\n {\n if ( a2 != a1[j] )\n v8[v6++] = a1[j];\n }\n v8[v6] = 0;\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_11A9(const char *a1, char a2) {\n unsigned int v2;\n int v4;\n int i;\n int v6;\n int j;\n uint8_t *v8;\n v4 = 0;\n for (i = 0; a1[i]; ++i) {\n if (a2 == a1[i]) ++v4;\n }\n v2 = strlen(a1);\n v8 = malloc(v2 - v4 + 1);\n v6 = 0;\n for (j = 0; a1[j]; ++j) {\n if (a2 != a1[j]) v8[v6++] = a1[j];\n }\n v8[v6] = 0;\n return v8;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1, char a2) {\n unsigned int v2;\n int v4;\n int i;\n int v6;\n int j;\n uint8_t *v8;\n v4 = 0;\n for (i = 0; a1[i]; ++i) {\n if (a2 == a1[i]) ++v4;\n }\n v2 = strlen(a1);\n v8 = malloc(v2 - v4 + 1);\n v6 = 0;\n for (j = 0; a1[j]; ++j) {\n if (a2 != a1[j]) v8[v6++] = a1[j];\n }\n v8[v6] = 0;\n return v8;\n}" + }, + { + "index": 377, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* s, char c) {\n int counts = 0;\n for (int i = 0; s[i] != '\\0'; i++) {\n if (s[i] == c) {\n counts++;\n }\n }\n char* result = (char*)malloc(strlen(s) - counts + 1);\n int j = 0;\n for (int i = 0; s[i] != '\\0'; i++) {\n if (s[i] != c) {\n result[j] = s[i];\n j++;\n }\n }\n result[j] = '\\0';\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"aba\", 'a'), \"b\") == 0);\n\n assert(strcmp(func0(\"toggle\", 'g'), \"tole\") == 0);\n\n assert(strcmp(func0(\"aabbc\", 'b'), \"aac\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmovzbl (%rdi),%ebx\ntest %bl,%bl\nje 11e4 \nmov %esi,%r12d\nlea 0x1(%rdi),%rbp\nmov %rbp,%rsi\nmov %ebx,%edx\nmov $0x0,%r8d\ncmp %dl,%r12b\nsete %dl\nmovzbl %dl,%edx\nadd %edx,%r8d\nadd $0x1,%rsi\nmovzbl -0x1(%rsi),%edx\ntest %dl,%dl\njne 118a \nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nmovslq %r8d,%r8\nmov %rcx,%rdi\nsub %r8,%rdi\ncallq 1070 \nmov $0x0,%edx\njmp 11dd \nmovslq %edx,%rcx\nmov %bl,(%rax,%rcx,1)\nadd $0x1,%edx\nadd $0x1,%rbp\nmovzbl -0x1(%rbp),%ebx\ntest %bl,%bl\nje 1202 \ncmp %bl,%r12b\njne 11c8 \njmp 11d1 \nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rdi\nnot %rdi\ncallq 1070 \nmov $0x0,%edx\nmovslq %edx,%rdx\nmovb $0x0,(%rax,%rdx,1)\npop %rbx\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_121F\nmov r12d, esi\nlea rbp, [rdi+1]\nmov rdx, rbp\nmov eax, ebx\nmov r13d, 0\nloc_11D0:\ncmp r12b, al\nsetz al\nmovzx eax, al\nadd r13d, eax\nadd rdx, 1\nmovzx eax, byte ptr [rdx-1]\ntest al, al\njnz short loc_11D0\ncall _strlen\nmovsxd r13, r13d\nsub rax, r13\nlea rdi, [rax+1]; s\ncall _malloc\nmov edx, 0\njmp short loc_120F\nloc_1203:\nadd rbp, 1\nmovzx ebx, byte ptr [rbp-1]\ntest bl, bl\njz short loc_1232\nloc_120F:\ncmp r12b, bl\njz short loc_1203\nmovsxd rcx, edx\nmov [rax+rcx], bl\nadd edx, 1\njmp short loc_1203\nloc_121F:\ncall _strlen\nlea rdi, [rax+1]; size\ncall _malloc\nmov edx, 0\nloc_1232:\nmovsxd rdx, edx\nmov byte ptr [rax+rdx], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1, char a2)\n{\n char v2; // bl\n char *v3; // rbp\n char *v4; // rdx\n char v5; // al\n int v6; // r13d\n size_t v7; // rax\n _BYTE *result; // rax\n int v9; // edx\n size_t v10; // rax\n\n v2 = *a1;\n if ( *a1 )\n {\n v3 = (char *)(a1 + 1);\n v4 = (char *)(a1 + 1);\n v5 = *a1;\n v6 = 0;\n do\n {\n v6 += a2 == v5;\n v5 = *v4++;\n }\n while ( v5 );\n v7 = strlen(a1);\n result = malloc(v7 - v6 + 1);\n v9 = 0;\n do\n {\n if ( a2 != v2 )\n result[v9++] = v2;\n v2 = *v3++;\n }\n while ( v2 );\n }\n else\n {\n v10 = strlen(a1);\n result = malloc(v10 + 1);\n v9 = 0;\n }\n result[v9] = 0;\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_121F\nmov r12d, esi\nlea rbp, [rdi+1]\nmov rdx, rbp\nmov eax, ebx\nmov r13d, 0\nloc_11D0:\ncmp r12b, al\nsetz al\nmovzx eax, al\nadd r13d, eax\nadd rdx, 1\nmovzx eax, byte ptr [rdx-1]\ntest al, al\njnz short loc_11D0\ncall _strlen\nmovsxd r13, r13d\nsub rax, r13\nlea rdi, [rax+1]; s\ncall _malloc\nmov edx, 0\njmp short loc_120F\nloc_1203:\nadd rbp, 1\nmovzx ebx, byte ptr [rbp-1]\ntest bl, bl\njz short loc_1232\nloc_120F:\ncmp r12b, bl\njz short loc_1203\nmovsxd rcx, edx\nmov [rax+rcx], bl\nadd edx, 1\njmp short loc_1203\nloc_121F:\ncall _strlen\nlea rdi, [rax+1]; size\ncall _malloc\nmov edx, 0\nloc_1232:\nmovsxd rdx, edx\nmov byte ptr [rax+rdx], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_11A9(const char *a1, char a2)\n{\n char v2; // bl\n char *v3; // rbp\n char *v4; // rdx\n char v5; // al\n int v6; // r13d\n size_t v7; // rax\n _BYTE *result; // rax\n int v9; // edx\n size_t v10; // rax\n\n v2 = *a1;\n if ( *a1 )\n {\n v3 = (char *)(a1 + 1);\n v4 = (char *)(a1 + 1);\n v5 = *a1;\n v6 = 0;\n do\n {\n v6 += a2 == v5;\n v5 = *v4++;\n }\n while ( v5 );\n v7 = strlen(a1);\n result = malloc(v7 - v6 + 1);\n v9 = 0;\n do\n {\n if ( a2 != v2 )\n result[v9++] = v2;\n v2 = *v3++;\n }\n while ( v2 );\n }\n else\n {\n v10 = strlen(a1);\n result = malloc(v10 + 1);\n v9 = 0;\n }\n result[v9] = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_11A9(const char *a1, char a2) {\n char v2;\n char *v3;\n char *v4;\n char v5;\n int v6;\n unsigned int v7;\n uint8_t *result;\n int v9;\n unsigned int v10;\n v2 = *a1;\n if (*a1) {\n v3 = (char *)(a1 + 1);\n v4 = (char *)(a1 + 1);\n v5 = *a1;\n v6 = 0;\n do {\n v6 += a2 == v5;\n v5 = *v4++;\n } while (v5);\n v7 = strlen(a1);\n result = malloc(v7 - v6 + 1);\n v9 = 0;\n do {\n if (a2 != v2) result[v9++] = v2;\n v2 = *v3++;\n } while (v2);\n } else {\n v10 = strlen(a1);\n result = malloc(v10 + 1);\n v9 = 0;\n }\n result[v9] = 0;\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1, char a2) {\n char v2;\n char *v3;\n char *v4;\n char v5;\n int v6;\n unsigned int v7;\n uint8_t *result;\n int v9;\n unsigned int v10;\n v2 = *a1;\n if (*a1) {\n v3 = (char *)(a1 + 1);\n v4 = (char *)(a1 + 1);\n v5 = *a1;\n v6 = 0;\n do {\n v6 += a2 == v5;\n v5 = *v4++;\n } while (v5);\n v7 = strlen(a1);\n result = malloc(v7 - v6 + 1);\n v9 = 0;\n do {\n if (a2 != v2) result[v9++] = v2;\n v2 = *v3++;\n } while (v2);\n } else {\n v10 = strlen(a1);\n result = malloc(v10 + 1);\n v9 = 0;\n }\n result[v9] = 0;\n return result;\n}" + }, + { + "index": 377, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* s, char c) {\n int counts = 0;\n for (int i = 0; s[i] != '\\0'; i++) {\n if (s[i] == c) {\n counts++;\n }\n }\n char* result = (char*)malloc(strlen(s) - counts + 1);\n int j = 0;\n for (int i = 0; s[i] != '\\0'; i++) {\n if (s[i] != c) {\n result[j] = s[i];\n j++;\n }\n }\n result[j] = '\\0';\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"aba\", 'a'), \"b\") == 0);\n\n assert(strcmp(func0(\"toggle\", 'g'), \"tole\") == 0);\n\n assert(strcmp(func0(\"aabbc\", 'b'), \"aac\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %esi,%r12d\npush %rbp\nmov %rdi,%rbp\npush %rbx\nmovzbl (%rdi),%ebx\ncallq 1070 \ntest %bl,%bl\nje 1300 \nadd $0x1,%rbp\nmov %ebx,%edx\nxor %r8d,%r8d\nmov %rbp,%rcx\nnopw %cs:0x0(%rax,%rax,1)\ncmp %dl,%r12b\nsete %dl\nadd $0x1,%rcx\nmovzbl %dl,%edx\nadd %edx,%r8d\nmovzbl -0x1(%rcx),%edx\ntest %dl,%dl\njne 12a0 \nlea 0x1(%rax),%rdi\nmovslq %r8d,%r8\nsub %r8,%rdi\ncallq 1090 \nxor %esi,%esi\nxor %ecx,%ecx\nnopl 0x0(%rax,%rax,1)\nlea (%rax,%rcx,1),%rdx\ncmp %bl,%r12b\nje 12e5 \nadd $0x1,%esi\nmov %bl,(%rdx)\nmovslq %esi,%rcx\nlea (%rax,%rcx,1),%rdx\nmovzbl 0x0(%rbp),%ebx\nadd $0x1,%rbp\ntest %bl,%bl\njne 12d0 \nmovb $0x0,(%rdx)\npop %rbx\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax)\nlea 0x1(%rax),%rdi\ncallq 1090 \nmov %rax,%rdx\nmovb $0x0,(%rdx)\npop %rbx\npop %rbp\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r12\nmov r12d, esi\npush rbp\nmov rbp, rdi\npush rbx\nmovzx ebx, byte ptr [rdi]\ncall _strlen\ntest bl, bl\njz short loc_1300\nadd rbp, 1\nmov edx, ebx\nxor esi, esi\nmov rcx, rbp\nnop dword ptr [rax]\nloc_12A8:\ncmp r12b, dl\nsetz dl\nadd rcx, 1\nmovzx edx, dl\nadd esi, edx\nmovzx edx, byte ptr [rcx-1]\ntest dl, dl\njnz short loc_12A8\nlea rdi, [rax+1]\nmovsxd rsi, esi\nsub rdi, rsi; size\ncall _malloc\nxor edx, edx\nloc_12D0:\ncmp r12b, bl\njz short loc_12DE\nmovsxd rcx, edx\nadd edx, 1\nmov [rax+rcx], bl\nloc_12DE:\nmovzx ebx, byte ptr [rbp+0]\nadd rbp, 1\ntest bl, bl\njnz short loc_12D0\nmovsxd rdx, edx\nadd rdx, rax\nmov byte ptr [rdx], 0\npop rbx\npop rbp\npop r12\nretn\nloc_1300:\nlea rdi, [rax+1]; size\ncall _malloc\nmov rdx, rax\nmov byte ptr [rdx], 0\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1, char a2)\n{\n char v3; // bl\n size_t v4; // rax\n char *v5; // rbp\n char v6; // dl\n int v7; // esi\n const char *v8; // rcx\n _BYTE *result; // rax\n int v10; // edx\n __int64 v11; // rcx\n\n v3 = *a1;\n v4 = strlen(a1);\n if ( v3 )\n {\n v5 = (char *)(a1 + 1);\n v6 = v3;\n v7 = 0;\n v8 = a1 + 1;\n do\n {\n ++v8;\n v7 += a2 == v6;\n v6 = *(v8 - 1);\n }\n while ( v6 );\n result = malloc(v4 + 1 - v7);\n v10 = 0;\n do\n {\n if ( a2 != v3 )\n {\n v11 = v10++;\n result[v11] = v3;\n }\n v3 = *v5++;\n }\n while ( v3 );\n result[v10] = 0;\n }\n else\n {\n result = malloc(v4 + 1);\n *result = 0;\n }\n return result;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\npush r12\nmov r12d, esi\npush rbp\nmov rbp, rdi\npush rbx\nmovzx ebx, byte ptr [rdi]\ncall _strlen\ntest bl, bl\njz short loc_1300\nadd rbp, 1\nmov edx, ebx\nxor esi, esi\nmov rcx, rbp\nnop dword ptr [rax]\nloc_12A8:\ncmp r12b, dl\nsetz dl\nadd rcx, 1\nmovzx edx, dl\nadd esi, edx\nmovzx edx, byte ptr [rcx-1]\ntest dl, dl\njnz short loc_12A8\nlea rdi, [rax+1]\nmovsxd rsi, esi\nsub rdi, rsi; size\ncall _malloc\nxor edx, edx\nloc_12D0:\ncmp r12b, bl\njz short loc_12DE\nmovsxd rcx, edx\nadd edx, 1\nmov [rax+rcx], bl\nloc_12DE:\nmovzx ebx, byte ptr [rbp+0]\nadd rbp, 1\ntest bl, bl\njnz short loc_12D0\nmovsxd rdx, edx\nadd rdx, rax\nmov byte ptr [rdx], 0\npop rbx\npop rbp\npop r12\nretn\nloc_1300:\nlea rdi, [rax+1]; size\ncall _malloc\nmov rdx, rax\nmov byte ptr [rdx], 0\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1280(const char *a1, char a2)\n{\n char v3; // bl\n size_t v4; // rax\n char *v5; // rbp\n char v6; // dl\n int v7; // esi\n const char *v8; // rcx\n _BYTE *result; // rax\n int v10; // edx\n __int64 v11; // rcx\n\n v3 = *a1;\n v4 = strlen(a1);\n if ( v3 )\n {\n v5 = (char *)(a1 + 1);\n v6 = v3;\n v7 = 0;\n v8 = a1 + 1;\n do\n {\n ++v8;\n v7 += a2 == v6;\n v6 = *(v8 - 1);\n }\n while ( v6 );\n result = malloc(v4 + 1 - v7);\n v10 = 0;\n do\n {\n if ( a2 != v3 )\n {\n v11 = v10++;\n result[v11] = v3;\n }\n v3 = *v5++;\n }\n while ( v3 );\n result[v10] = 0;\n }\n else\n {\n result = malloc(v4 + 1);\n *result = 0;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1280(const char *a1, char a2) {\n char v3;\n unsigned int v4;\n char *v5;\n char v6;\n int v7;\n const char *v8;\n uint8_t *result;\n int v10;\n long long v11;\n v3 = *a1;\n v4 = strlen(a1);\n if (v3) {\n v5 = (char *)(a1 + 1);\n v6 = v3;\n v7 = 0;\n v8 = a1 + 1;\n do {\n ++v8;\n v7 += a2 == v6;\n v6 = *(v8 - 1);\n } while (v6);\n result = malloc(v4 + 1 - v7);\n v10 = 0;\n do {\n if (a2 != v3) {\n v11 = v10++;\n result[v11] = v3;\n }\n v3 = *v5++;\n } while (v3);\n result[v10] = 0;\n } else {\n result = malloc(v4 + 1);\n *result = 0;\n }\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1, char a2) {\n char v3;\n unsigned int v4;\n char *v5;\n char v6;\n int v7;\n const char *v8;\n uint8_t *result;\n int v10;\n long long v11;\n v3 = *a1;\n v4 = strlen(a1);\n if (v3) {\n v5 = (char *)(a1 + 1);\n v6 = v3;\n v7 = 0;\n v8 = a1 + 1;\n do {\n ++v8;\n v7 += a2 == v6;\n v6 = *(v8 - 1);\n } while (v6);\n result = malloc(v4 + 1 - v7);\n v10 = 0;\n do {\n if (a2 != v3) {\n v11 = v10++;\n result[v11] = v3;\n }\n v3 = *v5++;\n } while (v3);\n result[v10] = 0;\n } else {\n result = malloc(v4 + 1);\n *result = 0;\n }\n return result;\n}" + }, + { + "index": 377, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* s, char c) {\n int counts = 0;\n for (int i = 0; s[i] != '\\0'; i++) {\n if (s[i] == c) {\n counts++;\n }\n }\n char* result = (char*)malloc(strlen(s) - counts + 1);\n int j = 0;\n for (int i = 0; s[i] != '\\0'; i++) {\n if (s[i] != c) {\n result[j] = s[i];\n j++;\n }\n }\n result[j] = '\\0';\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"aba\", 'a'), \"b\") == 0);\n\n assert(strcmp(func0(\"toggle\", 'g'), \"tole\") == 0);\n\n assert(strcmp(func0(\"aabbc\", 'b'), \"aac\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %esi,%r12d\npush %rbp\nmov %rdi,%rbp\npush %rbx\nmovzbl (%rdi),%ebx\ncallq 1070 \ntest %bl,%bl\nje 1318 \nadd $0x1,%rbp\nmov %ebx,%edx\nxor %r8d,%r8d\nmov %rbp,%rcx\nnopw 0x0(%rax,%rax,1)\ncmp %dl,%r12b\nsete %dl\nadd $0x1,%rcx\nmovzbl %dl,%edx\nadd %edx,%r8d\nmovzbl -0x1(%rcx),%edx\ntest %dl,%dl\njne 12a0 \nlea 0x1(%rax),%rdi\nmovslq %r8d,%r8\nsub %r8,%rdi\ncallq 1090 \nxor %esi,%esi\nxor %ecx,%ecx\nnopl 0x0(%rax,%rax,1)\nlea (%rax,%rcx,1),%rdx\ncmp %bl,%r12b\nje 1300 \nadd $0x1,%rbp\nmov %bl,(%rdx)\nadd $0x1,%esi\nmovzbl -0x1(%rbp),%ebx\nmovslq %esi,%rcx\nlea (%rax,%rcx,1),%rdx\ntest %bl,%bl\njne 12d0 \nmovb $0x0,(%rdx)\npop %rbx\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax)\nmovzbl 0x0(%rbp),%ebx\nadd $0x1,%rbp\ntest %bl,%bl\njne 12d0 \nmovb $0x0,(%rdx)\npop %rbx\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax)\nlea 0x1(%rax),%rdi\ncallq 1090 \nmov %rax,%rdx\nmovb $0x0,(%rdx)\npop %rbx\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r12\nmov r12d, esi\npush rbp\nmov rbp, rdi\npush rbx\nmovzx ebx, byte ptr [rdi]\ncall _strlen\ntest bl, bl\njz short loc_1310\nadd rbp, 1\nmov edx, ebx\nxor esi, esi\nmov rcx, rbp\nnop dword ptr [rax]\nloc_12A8:\ncmp r12b, dl\nsetz dl\nadd rcx, 1\nmovzx edx, dl\nadd esi, edx\nmovzx edx, byte ptr [rcx-1]\ntest dl, dl\njnz short loc_12A8\nlea rdi, [rax+1]\nmovsxd rsi, esi\nsub rdi, rsi; size\ncall _malloc\nxor edx, edx\nloc_12D0:\ncmp r12b, bl\njz short loc_1300\nmovsxd rcx, edx\nadd rbp, 1\nadd edx, 1\nmov [rax+rcx], bl\nmovzx ebx, byte ptr [rbp-1]\ntest bl, bl\njnz short loc_12D0\nloc_12EA:\nmovsxd rdx, edx\nadd rdx, rax\nmov byte ptr [rdx], 0\npop rbx\npop rbp\npop r12\nretn\nloc_1300:\nmovzx ebx, byte ptr [rbp+0]\nadd rbp, 1\ntest bl, bl\njnz short loc_12D0\njmp short loc_12EA\nloc_1310:\nlea rdi, [rax+1]; size\ncall _malloc\nmov rdx, rax\nmov byte ptr [rdx], 0\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1, char a2)\n{\n char v3; // bl\n size_t v4; // rax\n char *v5; // rbp\n char v6; // dl\n int v7; // esi\n const char *v8; // rcx\n _BYTE *result; // rax\n int v10; // edx\n __int64 v11; // rcx\n\n v3 = *a1;\n v4 = strlen(a1);\n if ( v3 )\n {\n v5 = (char *)(a1 + 1);\n v6 = v3;\n v7 = 0;\n v8 = a1 + 1;\n do\n {\n ++v8;\n v7 += a2 == v6;\n v6 = *(v8 - 1);\n }\n while ( v6 );\n result = malloc(v4 + 1 - v7);\n v10 = 0;\n do\n {\n while ( a2 != v3 )\n {\n v11 = v10;\n ++v5;\n ++v10;\n result[v11] = v3;\n v3 = *(v5 - 1);\n if ( !v3 )\n goto LABEL_7;\n }\n v3 = *v5++;\n }\n while ( v3 );\nLABEL_7:\n result[v10] = 0;\n }\n else\n {\n result = malloc(v4 + 1);\n *result = 0;\n }\n return result;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\npush r12\nmov r12d, esi\npush rbp\nmov rbp, rdi\npush rbx\nmovzx ebx, byte ptr [rdi]\ncall _strlen\ntest bl, bl\njz short loc_1310\nadd rbp, 1\nmov edx, ebx\nxor esi, esi\nmov rcx, rbp\nnop dword ptr [rax]\nloc_12A8:\ncmp r12b, dl\nsetz dl\nadd rcx, 1\nmovzx edx, dl\nadd esi, edx\nmovzx edx, byte ptr [rcx-1]\ntest dl, dl\njnz short loc_12A8\nlea rdi, [rax+1]\nmovsxd rsi, esi\nsub rdi, rsi; size\ncall _malloc\nxor edx, edx\nloc_12D0:\ncmp r12b, bl\njz short loc_1300\nmovsxd rcx, edx\nadd rbp, 1\nadd edx, 1\nmov [rax+rcx], bl\nmovzx ebx, byte ptr [rbp-1]\ntest bl, bl\njnz short loc_12D0\nloc_12EA:\nmovsxd rdx, edx\nadd rdx, rax\nmov byte ptr [rdx], 0\npop rbx\npop rbp\npop r12\nretn\nloc_1300:\nmovzx ebx, byte ptr [rbp+0]\nadd rbp, 1\ntest bl, bl\njnz short loc_12D0\njmp short loc_12EA\nloc_1310:\nlea rdi, [rax+1]; size\ncall _malloc\nmov rdx, rax\nmov byte ptr [rdx], 0\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1280(const char *a1, char a2)\n{\n char v3; // bl\n size_t v4; // rax\n char *v5; // rbp\n char v6; // dl\n int v7; // esi\n const char *v8; // rcx\n _BYTE *result; // rax\n int v10; // edx\n __int64 v11; // rcx\n\n v3 = *a1;\n v4 = strlen(a1);\n if ( v3 )\n {\n v5 = (char *)(a1 + 1);\n v6 = v3;\n v7 = 0;\n v8 = a1 + 1;\n do\n {\n ++v8;\n v7 += a2 == v6;\n v6 = *(v8 - 1);\n }\n while ( v6 );\n result = malloc(v4 + 1 - v7);\n v10 = 0;\n do\n {\n while ( a2 != v3 )\n {\n v11 = v10;\n ++v5;\n ++v10;\n result[v11] = v3;\n v3 = *(v5 - 1);\n if ( !v3 )\n goto LABEL_7;\n }\n v3 = *v5++;\n }\n while ( v3 );\nLABEL_7:\n result[v10] = 0;\n }\n else\n {\n result = malloc(v4 + 1);\n *result = 0;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1280(const char *a1, char a2) {\n char v3;\n unsigned int v4;\n char *v5;\n char v6;\n int v7;\n const char *v8;\n uint8_t *result;\n int v10;\n long long v11;\n v3 = *a1;\n v4 = strlen(a1);\n if (v3) {\n v5 = (char *)(a1 + 1);\n v6 = v3;\n v7 = 0;\n v8 = a1 + 1;\n do {\n ++v8;\n v7 += a2 == v6;\n v6 = *(v8 - 1);\n } while (v6);\n result = malloc(v4 + 1 - v7);\n v10 = 0;\n do {\n while (a2 != v3) {\n v11 = v10;\n ++v5;\n ++v10;\n result[v11] = v3;\n v3 = *(v5 - 1);\n if (!v3) goto LABEL_7;\n }\n v3 = *v5++;\n } while (v3);\n LABEL_7:\n result[v10] = 0;\n } else {\n result = malloc(v4 + 1);\n *result = 0;\n }\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1, char a2) {\n char v3;\n unsigned int v4;\n char *v5;\n char v6;\n int v7;\n const char *v8;\n uint8_t *result;\n int v10;\n long long v11;\n v3 = *a1;\n v4 = strlen(a1);\n if (v3) {\n v5 = (char *)(a1 + 1);\n v6 = v3;\n v7 = 0;\n v8 = a1 + 1;\n do {\n ++v8;\n v7 += a2 == v6;\n v6 = *(v8 - 1);\n } while (v6);\n result = malloc(v4 + 1 - v7);\n v10 = 0;\n do {\n while (a2 != v3) {\n v11 = v10;\n ++v5;\n ++v10;\n result[v11] = v3;\n v3 = *(v5 - 1);\n if (!v3) goto LABEL_7;\n }\n v3 = *v5++;\n } while (v3);\n LABEL_7:\n result[v10] = 0;\n } else {\n result = malloc(v4 + 1);\n *result = 0;\n }\n return result;\n}" + }, + { + "index": 378, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int test_list[], int n, int result[]) {\n result[0] = test_list[n - 1];\n for (int i = 1; i < n; i++) {\n result[i] = test_list[i - 1];\n }\n}", + "test": "int main() {\n\n int test1[] = {1, 2, 3, 4};\n\n int result1[4];\n\n func0(test1, 4, result1);\n\n assert(result1[0] == 4 && result1[1] == 1 && result1[2] == 2 && result1[3] == 3);\n\n\n\n int test2[] = {0, 1, 2, 3};\n\n int result2[4];\n\n func0(test2, 4, result2);\n\n assert(result2[0] == 3 && result2[1] == 0 && result2[2] == 1 && result2[3] == 2);\n\n \n\n int test3[] = {9, 8, 7, 1};\n\n int result3[4];\n\n func0(test3, 4, result3);\n\n assert(result3[0] == 1 && result3[1] == 9 && result3[2] == 8 && result3[3] == 7);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmov -0x1c(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x28(%rbp),%rax\nmov %edx,(%rax)\nmovl $0x1,-0x4(%rbp)\njmp 11d2 \nmov -0x4(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0x4(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x28(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11a1 \npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_28]\nmov [rax], edx\nmov [rbp+var_4], 1\njmp short loc_11D2\nloc_11A1:\nmov eax, [rbp+var_4]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_4], 1\nloc_11D2:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11A1\nnop\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, _DWORD *a3)\n{\n __int64 result; // rax\n int i; // [rsp+24h] [rbp-4h]\n\n *a3 = *(_DWORD *)(4LL * a2 - 4 + a1);\n for ( i = 1; ; ++i )\n {\n result = (unsigned int)i;\n if ( i >= a2 )\n break;\n a3[i] = *(_DWORD *)(4LL * i - 4 + a1);\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_28]\nmov [rax], edx\nmov [rbp+var_4], 1\njmp short loc_11D2\nloc_11A1:\nmov eax, [rbp+var_4]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_4], 1\nloc_11D2:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11A1\nnop\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, _DWORD *a3)\n{\n __int64 result; // rax\n int i; // [rsp+24h] [rbp-4h]\n\n *a3 = *(_DWORD *)(4LL * a2 - 4 + a1);\n for ( i = 1; ; ++i )\n {\n result = (unsigned int)i;\n if ( i >= a2 )\n break;\n a3[i] = *(_DWORD *)(4LL * i - 4 + a1);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, uint32_t *a3) {\n long long result;\n int i;\n *a3 = *(uint32_t *)(4LL * a2 - 4 + a1);\n for (i = 1;; ++i) {\n result = (unsigned int)i;\n if (i >= a2) break;\n a3[i] = *(uint32_t *)(4LL * i - 4 + a1);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, uint32_t *a3) {\n long long result;\n int i;\n *a3 = *(uint32_t *)(4LL * a2 - 4 + a1);\n for (i = 1;; ++i) {\n result = (unsigned int)i;\n if (i >= a2) break;\n a3[i] = *(uint32_t *)(4LL * i - 4 + a1);\n }\n return result;\n}" + }, + { + "index": 378, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int test_list[], int n, int result[]) {\n result[0] = test_list[n - 1];\n for (int i = 1; i < n; i++) {\n result[i] = test_list[i - 1];\n }\n}", + "test": "int main() {\n\n int test1[] = {1, 2, 3, 4};\n\n int result1[4];\n\n func0(test1, 4, result1);\n\n assert(result1[0] == 4 && result1[1] == 1 && result1[2] == 2 && result1[3] == 3);\n\n\n\n int test2[] = {0, 1, 2, 3};\n\n int result2[4];\n\n func0(test2, 4, result2);\n\n assert(result2[0] == 3 && result2[1] == 0 && result2[2] == 1 && result2[3] == 2);\n\n \n\n int test3[] = {9, 8, 7, 1};\n\n int result3[4];\n\n func0(test3, 4, result3);\n\n assert(result3[0] == 1 && result3[1] == 9 && result3[2] == 8 && result3[3] == 7);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmovslq %esi,%rax\nmov -0x4(%rdi,%rax,4),%eax\nmov %eax,(%rdx)\ncmp $0x1,%esi\njle 1196 \nlea -0x2(%rsi),%esi\nmov $0x0,%eax\nmov (%rdi,%rax,4),%ecx\nmov %ecx,0x4(%rdx,%rax,4)\nmov %rax,%rcx\nadd $0x1,%rax\ncmp %rsi,%rcx\njne 1183 \nretq\n", + "ida_asm": "func0:\nendbr64\nmovsxd rax, esi\nmov eax, [rdi+rax*4-4]\nmov [rdx], eax\ncmp esi, 1\njle short locret_1193\nlea esi, [rsi-1]\nmov eax, 0\nloc_1183:\nmov ecx, [rdi+rax*4]\nmov [rdx+rax*4+4], ecx\nadd rax, 1\ncmp rax, rsi\njnz short loc_1183\nlocret_1193:\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, _DWORD *a3)\n{\n __int64 result; // rax\n __int64 v4; // rsi\n\n result = *(unsigned int *)(a1 + 4LL * a2 - 4);\n *a3 = result;\n if ( a2 > 1 )\n {\n v4 = (unsigned int)(a2 - 1);\n result = 0LL;\n do\n {\n a3[result + 1] = *(_DWORD *)(a1 + 4 * result);\n ++result;\n }\n while ( result != v4 );\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmovsxd rax, esi\nmov eax, [rdi+rax*4-4]\nmov [rdx], eax\ncmp esi, 1\njle short locret_1193\nlea esi, [rsi-1]\nmov eax, 0\nloc_1183:\nmov ecx, [rdi+rax*4]\nmov [rdx+rax*4+4], ecx\nadd rax, 1\ncmp rax, rsi\njnz short loc_1183\nlocret_1193:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, _DWORD *a3)\n{\n __int64 result; // rax\n __int64 v4; // rsi\n\n result = *(unsigned int *)(a1 + 4LL * a2 - 4);\n *a3 = result;\n if ( a2 > 1 )\n {\n v4 = (unsigned int)(a2 - 1);\n result = 0LL;\n do\n {\n a3[result + 1] = *(_DWORD *)(a1 + 4 * result);\n ++result;\n }\n while ( result != v4 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, uint32_t *a3) {\n long long result;\n long long v4;\n result = *(unsigned int *)(a1 + 4LL * a2 - 4);\n *a3 = result;\n if (a2 > 1) {\n v4 = (unsigned int)(a2 - 1);\n result = 0LL;\n do {\n a3[result + 1] = *(uint32_t *)(a1 + 4 * result);\n ++result;\n } while (result != v4);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, uint32_t *a3) {\n long long result;\n long long v4;\n result = *(unsigned int *)(a1 + 4LL * a2 - 4);\n *a3 = result;\n if (a2 > 1) {\n v4 = (unsigned int)(a2 - 1);\n result = 0LL;\n do {\n a3[result + 1] = *(uint32_t *)(a1 + 4 * result);\n ++result;\n } while (result != v4);\n }\n return result;\n}" + }, + { + "index": 378, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int test_list[], int n, int result[]) {\n result[0] = test_list[n - 1];\n for (int i = 1; i < n; i++) {\n result[i] = test_list[i - 1];\n }\n}", + "test": "int main() {\n\n int test1[] = {1, 2, 3, 4};\n\n int result1[4];\n\n func0(test1, 4, result1);\n\n assert(result1[0] == 4 && result1[1] == 1 && result1[2] == 2 && result1[3] == 3);\n\n\n\n int test2[] = {0, 1, 2, 3};\n\n int result2[4];\n\n func0(test2, 4, result2);\n\n assert(result2[0] == 3 && result2[1] == 0 && result2[2] == 1 && result2[3] == 2);\n\n \n\n int test3[] = {9, 8, 7, 1};\n\n int result3[4];\n\n func0(test3, 4, result3);\n\n assert(result3[0] == 1 && result3[1] == 9 && result3[2] == 8 && result3[3] == 7);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmovslq %esi,%rax\nmov -0x4(%rdi,%rax,4),%eax\nmov %eax,(%rdx)\ncmp $0x1,%esi\njle 1173 \nsub $0x2,%esi\nxor %eax,%eax\nnopw 0x0(%rax,%rax,1)\nmov (%rdi,%rax,4),%ecx\nmov %ecx,0x4(%rdx,%rax,4)\nmov %rax,%rcx\nadd $0x1,%rax\ncmp %rcx,%rsi\njne 1160 \nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\nmovsxd rax, esi\nmov eax, [rdi+rax*4-4]\nmov [rdx], eax\ncmp esi, 1\njle short locret_1310\nsub esi, 1\nxor eax, eax\nnop word ptr [rax+rax+00000000h]\nloc_1300:\nmov ecx, [rdi+rax*4]\nmov [rdx+rax*4+4], ecx\nadd rax, 1\ncmp rax, rsi\njnz short loc_1300\nlocret_1310:\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, _DWORD *a3)\n{\n __int64 result; // rax\n __int64 v4; // rsi\n\n result = *(unsigned int *)(a1 + 4LL * a2 - 4);\n *a3 = result;\n if ( a2 > 1 )\n {\n v4 = (unsigned int)(a2 - 1);\n result = 0LL;\n do\n {\n a3[result + 1] = *(_DWORD *)(a1 + 4 * result);\n ++result;\n }\n while ( result != v4 );\n }\n return result;\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\nmovsxd rax, esi\nmov eax, [rdi+rax*4-4]\nmov [rdx], eax\ncmp esi, 1\njle short locret_1310\nsub esi, 1\nxor eax, eax\nnop word ptr [rax+rax+00000000h]\nloc_1300:\nmov ecx, [rdi+rax*4]\nmov [rdx+rax*4+4], ecx\nadd rax, 1\ncmp rax, rsi\njnz short loc_1300\nlocret_1310:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12E0(__int64 a1, int a2, _DWORD *a3)\n{\n __int64 result; // rax\n __int64 v4; // rsi\n\n result = *(unsigned int *)(a1 + 4LL * a2 - 4);\n *a3 = result;\n if ( a2 > 1 )\n {\n v4 = (unsigned int)(a2 - 1);\n result = 0LL;\n do\n {\n a3[result + 1] = *(_DWORD *)(a1 + 4 * result);\n ++result;\n }\n while ( result != v4 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12E0(long long a1, int a2, uint32_t *a3) {\n long long result;\n long long v4;\n result = *(unsigned int *)(a1 + 4LL * a2 - 4);\n *a3 = result;\n if (a2 > 1) {\n v4 = (unsigned int)(a2 - 1);\n result = 0LL;\n do {\n a3[result + 1] = *(uint32_t *)(a1 + 4 * result);\n ++result;\n } while (result != v4);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, uint32_t *a3) {\n long long result;\n long long v4;\n result = *(unsigned int *)(a1 + 4LL * a2 - 4);\n *a3 = result;\n if (a2 > 1) {\n v4 = (unsigned int)(a2 - 1);\n result = 0LL;\n do {\n a3[result + 1] = *(uint32_t *)(a1 + 4 * result);\n ++result;\n } while (result != v4);\n }\n return result;\n}" + }, + { + "index": 379, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int l, int w, int h) {\n int SA = 2 * (l * w + l * h + w * h);\n return SA;\n}", + "test": "int main() {\n\n assert(func0(1, 2, 3) == 22);\n\n assert(func0(5, 7, 9) == 286);\n\n assert(func0(10, 15, 21) == 1350);\n\n \n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov %edx,-0x1c(%rbp)\nmov -0x14(%rbp),%eax\nimul -0x18(%rbp),%eax\nmov %eax,%edx\nmov -0x14(%rbp),%eax\nimul -0x1c(%rbp),%eax\nadd %eax,%edx\nmov -0x18(%rbp),%eax\nimul -0x1c(%rbp),%eax\nadd %edx,%eax\nadd %eax,%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov eax, [rbp+var_14]\nimul eax, [rbp+var_18]\nmov edx, eax\nmov eax, [rbp+var_14]\nimul eax, [rbp+var_1C]\nadd edx, eax\nmov eax, [rbp+var_18]\nimul eax, [rbp+var_1C]\nadd eax, edx\nadd eax, eax\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, int a3)\n{\n return (unsigned int)(2 * (a3 * a1 + a2 * a1 + a3 * a2));\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov eax, [rbp+var_14]\nimul eax, [rbp+var_18]\nmov edx, eax\nmov eax, [rbp+var_14]\nimul eax, [rbp+var_1C]\nadd edx, eax\nmov eax, [rbp+var_18]\nimul eax, [rbp+var_1C]\nadd eax, edx\nadd eax, eax\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2, int a3)\n{\n return (unsigned int)(2 * (a3 * a1 + a2 * a1 + a3 * a2));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2, int a3) {\n return (unsigned int)(2 * (a3 * a1 + a2 * a1 + a3 * a2));\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, int a3) {\n return (unsigned int)(2 * (a3 * a1 + a2 * a1 + a3 * a2));\n}" + }, + { + "index": 380, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int** func0(int rownum, int colnum) {\n int** matrix = malloc(rownum * sizeof(int*));\n for (int i = 0; i < rownum; i++) {\n matrix[i] = malloc(colnum * sizeof(int));\n for (int j = 0; j < colnum; j++) {\n matrix[i][j] = i * j;\n }\n }\n return matrix;\n}", + "test": "int main() {\n\n int **result;\n\n int i, j;\n\n\n\n result = func0(3, 4);\n\n int expected_3_4[3][4] = {{0, 0, 0, 0}, {0, 1, 2, 3}, {0, 2, 4, 6}};\n\n for (i = 0; i < 3; i++) {\n\n for (j = 0; j < 4; j++) {\n\n assert(result[i][j] == expected_3_4[i][j]);\n\n }\n\n }\n\n\n\n result = func0(5, 7);\n\n int expected_5_7[5][7] = {{0, 0, 0, 0, 0, 0, 0}, {0, 1, 2, 3, 4, 5, 6}, {0, 2, 4, 6, 8, 10, 12}, {0, 3, 6, 9, 12, 15, 18}, {0, 4, 8, 12, 16, 20, 24}};\n\n for (i = 0; i < 5; i++) {\n\n for (j = 0; j < 7; j++) {\n\n assert(result[i][j] == expected_5_7[i][j]);\n\n }\n\n }\n\n\n\n result = func0(10, 15);\n\n int expected_10_15[10][15] = {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14}, {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28}, {0, 3, 6, 9, 12, 15, 18, 21, 24, 27, 30, 33, 36, 39, 42}, {0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56}, {0, 5, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 65, 70}, {0, 6, 12, 18, 24, 30, 36, 42, 48, 54, 60, 66, 72, 78, 84}, {0, 7, 14, 21, 28, 35, 42, 49, 56, 63, 70, 77, 84, 91, 98}, {0, 8, 16, 24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112}, {0, 9, 18, 27, 36, 45, 54, 63, 72, 81, 90, 99, 108, 117, 126}};\n\n for (i = 0; i < 10; i++) {\n\n for (j = 0; j < 15; j++) {\n\n assert(result[i][j] == expected_10_15[i][j]);\n\n }\n\n }\n\n\n\n for (i = 0; i < 10; i++) {\n\n free(result[i]); \n\n }\n\n free(result);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x28,%rsp\nmov %edi,-0x24(%rbp)\nmov %esi,-0x28(%rbp)\nmov -0x24(%rbp),%eax\ncltq\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x18(%rbp)\nmovl $0x0,-0x20(%rbp)\njmp 124a \nmov -0x28(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov -0x20(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x18(%rbp),%rdx\nlea (%rcx,%rdx,1),%rbx\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,(%rbx)\nmovl $0x0,-0x1c(%rbp)\njmp 123e \nmov -0x20(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0x1c(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x2,%rdx\nadd %rax,%rdx\nmov -0x20(%rbp),%eax\nimul -0x1c(%rbp),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x1c(%rbp)\nmov -0x1c(%rbp),%eax\ncmp -0x28(%rbp),%eax\njl 120d \naddl $0x1,-0x20(%rbp)\nmov -0x20(%rbp),%eax\ncmp -0x24(%rbp),%eax\njl 11da \nmov -0x18(%rbp),%rax\nadd $0x28,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+var_24], edi\nmov [rbp+var_28], esi\nmov eax, [rbp+var_24]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_20], 0\njmp short loc_124A\nloc_11DA:\nmov eax, [rbp+var_28]\ncdqe\nshl rax, 2\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nlea rbx, [rcx+rdx]\nmov rdi, rax; size\ncall _malloc\nmov [rbx], rax\nmov [rbp+var_1C], 0\njmp short loc_123E\nloc_120D:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nshl rdx, 2\nadd rdx, rax\nmov eax, [rbp+var_20]\nimul eax, [rbp+var_1C]\nmov [rdx], eax\nadd [rbp+var_1C], 1\nloc_123E:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_28]\njl short loc_120D\nadd [rbp+var_20], 1\nloc_124A:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_24]\njl short loc_11DA\nmov rax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(int a1, int a2)\n{\n int i; // [rsp+10h] [rbp-20h]\n int j; // [rsp+14h] [rbp-1Ch]\n _QWORD *v5; // [rsp+18h] [rbp-18h]\n\n v5 = malloc(8LL * a1);\n for ( i = 0; i < a1; ++i )\n {\n v5[i] = malloc(4LL * a2);\n for ( j = 0; j < a2; ++j )\n *(_DWORD *)(v5[i] + 4LL * j) = j * i;\n }\n return v5;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+var_24], edi\nmov [rbp+var_28], esi\nmov eax, [rbp+var_24]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_20], 0\njmp short loc_124A\nloc_11DA:\nmov eax, [rbp+var_28]\ncdqe\nshl rax, 2\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nlea rbx, [rcx+rdx]\nmov rdi, rax; size\ncall _malloc\nmov [rbx], rax\nmov [rbp+var_1C], 0\njmp short loc_123E\nloc_120D:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nshl rdx, 2\nadd rdx, rax\nmov eax, [rbp+var_20]\nimul eax, [rbp+var_1C]\nmov [rdx], eax\nadd [rbp+var_1C], 1\nloc_123E:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_28]\njl short loc_120D\nadd [rbp+var_20], 1\nloc_124A:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_24]\njl short loc_11DA\nmov rax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11A9(int a1, int a2)\n{\n int i; // [rsp+10h] [rbp-20h]\n int j; // [rsp+14h] [rbp-1Ch]\n _QWORD *v5; // [rsp+18h] [rbp-18h]\n\n v5 = malloc(8LL * a1);\n for ( i = 0; i < a1; ++i )\n {\n v5[i] = malloc(4LL * a2);\n for ( j = 0; j < a2; ++j )\n *(_DWORD *)(v5[i] + 4LL * j) = j * i;\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11A9(int a1, int a2) {\n int i;\n int j;\n uint64_t *v5;\n v5 = malloc(8LL * a1);\n for (i = 0; i < a1; ++i) {\n v5[i] = malloc(4LL * a2);\n for (j = 0; j < a2; ++j) *(uint32_t *)(v5[i] + 4LL * j) = j * i;\n }\n return v5;\n}", + "ida_pseudo_norm": "uint64_t *func0(int a1, int a2) {\n int i;\n int j;\n uint64_t *v5;\n v5 = malloc(8LL * a1);\n for (i = 0; i < a1; ++i) {\n v5[i] = malloc(4LL * a2);\n for (j = 0; j < a2; ++j) *(uint32_t *)(v5[i] + 4LL * j) = j * i;\n }\n return v5;\n}" + }, + { + "index": 380, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int** func0(int rownum, int colnum) {\n int** matrix = malloc(rownum * sizeof(int*));\n for (int i = 0; i < rownum; i++) {\n matrix[i] = malloc(colnum * sizeof(int));\n for (int j = 0; j < colnum; j++) {\n matrix[i][j] = i * j;\n }\n }\n return matrix;\n}", + "test": "int main() {\n\n int **result;\n\n int i, j;\n\n\n\n result = func0(3, 4);\n\n int expected_3_4[3][4] = {{0, 0, 0, 0}, {0, 1, 2, 3}, {0, 2, 4, 6}};\n\n for (i = 0; i < 3; i++) {\n\n for (j = 0; j < 4; j++) {\n\n assert(result[i][j] == expected_3_4[i][j]);\n\n }\n\n }\n\n\n\n result = func0(5, 7);\n\n int expected_5_7[5][7] = {{0, 0, 0, 0, 0, 0, 0}, {0, 1, 2, 3, 4, 5, 6}, {0, 2, 4, 6, 8, 10, 12}, {0, 3, 6, 9, 12, 15, 18}, {0, 4, 8, 12, 16, 20, 24}};\n\n for (i = 0; i < 5; i++) {\n\n for (j = 0; j < 7; j++) {\n\n assert(result[i][j] == expected_5_7[i][j]);\n\n }\n\n }\n\n\n\n result = func0(10, 15);\n\n int expected_10_15[10][15] = {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14}, {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28}, {0, 3, 6, 9, 12, 15, 18, 21, 24, 27, 30, 33, 36, 39, 42}, {0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56}, {0, 5, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 65, 70}, {0, 6, 12, 18, 24, 30, 36, 42, 48, 54, 60, 66, 72, 78, 84}, {0, 7, 14, 21, 28, 35, 42, 49, 56, 63, 70, 77, 84, 91, 98}, {0, 8, 16, 24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112}, {0, 9, 18, 27, 36, 45, 54, 63, 72, 81, 90, 99, 108, 117, 126}};\n\n for (i = 0; i < 10; i++) {\n\n for (j = 0; j < 15; j++) {\n\n assert(result[i][j] == expected_10_15[i][j]);\n\n }\n\n }\n\n\n\n for (i = 0; i < 10; i++) {\n\n free(result[i]); \n\n }\n\n free(result);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov %edi,%r13d\nmov %esi,%r14d\nmovslq %edi,%rdi\nshl $0x3,%rdi\ncallq 10b0 \nmov %rax,0x8(%rsp)\ntest %r13d,%r13d\njle 1236 \nmovslq %r14d,%r15\nshl $0x2,%r15\nmov %rax,%rbp\nlea -0x1(%r14),%eax\nlea 0x4(,%rax,4),%rbx\nmov $0x0,%r12d\njmp 1202 \nadd $0x1,%r12d\nadd $0x8,%rbp\ncmp %r12d,%r13d\nje 1236 \nmov %r15,%rdi\ncallq 10b0 \nmov %rbp,%rsi\nmov %rax,0x0(%rbp)\ntest %r14d,%r14d\njle 11f5 \nmov %r12d,%edi\nmov $0x0,%edx\nmov $0x0,%eax\nmov (%rsi),%rcx\nmov %edx,(%rcx,%rax,1)\nadd $0x4,%rax\nadd %edi,%edx\ncmp %rbx,%rax\njne 1223 \njmp 11f5 \nmov 0x8(%rsp),%rax\nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov ebx, edi\nmov r13d, esi\nmovsxd r14, edi\nlea rdi, ds:0[r14*8]; size\ncall _malloc\nmov r12, rax\ntest ebx, ebx\njle short loc_1211\nmovsxd rbp, r13d\nshl rbp, 2\nmov ebx, 0\nloc_11DD:\nmov rdi, rbp; size\ncall _malloc\nmov [r12+rbx*8], rax\ntest r13d, r13d\njle short loc_1208\nmov esi, ebx\nmov rdx, rax\nadd rax, rbp\nmov ecx, 0\nloc_11FB:\nmov [rdx], ecx\nadd ecx, esi\nadd rdx, 4\ncmp rdx, rax\njnz short loc_11FB\nloc_1208:\nadd rbx, 1\ncmp r14, rbx\njnz short loc_11DD\nloc_1211:\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(int a1, int a2)\n{\n _QWORD *v2; // r12\n __int64 i; // rbx\n _DWORD *v4; // rax\n _DWORD *v5; // rdx\n _DWORD *v6; // rax\n int v7; // ecx\n\n v2 = malloc(8LL * a1);\n if ( a1 > 0 )\n {\n for ( i = 0LL; i != a1; ++i )\n {\n v4 = malloc(4LL * a2);\n v2[i] = v4;\n if ( a2 > 0 )\n {\n v5 = v4;\n v6 = &v4[a2];\n v7 = 0;\n do\n {\n *v5 = v7;\n v7 += i;\n ++v5;\n }\n while ( v5 != v6 );\n }\n }\n }\n return v2;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov ebx, edi\nmov r13d, esi\nmovsxd r14, edi\nlea rdi, ds:0[r14*8]; size\ncall _malloc\nmov r12, rax\ntest ebx, ebx\njle short loc_1211\nmovsxd rbp, r13d\nshl rbp, 2\nmov ebx, 0\nloc_11DD:\nmov rdi, rbp; size\ncall _malloc\nmov [r12+rbx*8], rax\ntest r13d, r13d\njle short loc_1208\nmov esi, ebx\nmov rdx, rax\nadd rax, rbp\nmov ecx, 0\nloc_11FB:\nmov [rdx], ecx\nadd ecx, esi\nadd rdx, 4\ncmp rdx, rax\njnz short loc_11FB\nloc_1208:\nadd rbx, 1\ncmp r14, rbx\njnz short loc_11DD\nloc_1211:\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11A9(int a1, int a2)\n{\n _QWORD *v2; // r12\n __int64 i; // rbx\n _DWORD *v4; // rax\n _DWORD *v5; // rdx\n _DWORD *v6; // rax\n int v7; // ecx\n\n v2 = malloc(8LL * a1);\n if ( a1 > 0 )\n {\n for ( i = 0LL; i != a1; ++i )\n {\n v4 = malloc(4LL * a2);\n v2[i] = v4;\n if ( a2 > 0 )\n {\n v5 = v4;\n v6 = &v4[a2];\n v7 = 0;\n do\n {\n *v5 = v7;\n v7 += i;\n ++v5;\n }\n while ( v5 != v6 );\n }\n }\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11A9(int a1, int a2) {\n uint64_t *v2;\n long long i;\n uint32_t *v4;\n uint32_t *v5;\n uint32_t *v6;\n int v7;\n v2 = malloc(8LL * a1);\n if (a1 > 0) {\n for (i = 0LL; i != a1; ++i) {\n v4 = malloc(4LL * a2);\n v2[i] = v4;\n if (a2 > 0) {\n v5 = v4;\n v6 = &v4[a2];\n v7 = 0;\n do {\n *v5 = v7;\n v7 += i;\n ++v5;\n } while (v5 != v6);\n }\n }\n }\n return v2;\n}", + "ida_pseudo_norm": "uint64_t *func0(int a1, int a2) {\n uint64_t *v2;\n long long i;\n uint32_t *v4;\n uint32_t *v5;\n uint32_t *v6;\n int v7;\n v2 = malloc(8LL * a1);\n if (a1 > 0) {\n for (i = 0LL; i != a1; ++i) {\n v4 = malloc(4LL * a2);\n v2[i] = v4;\n if (a2 > 0) {\n v5 = v4;\n v6 = &v4[a2];\n v7 = 0;\n do {\n *v5 = v7;\n v7 += i;\n ++v5;\n } while (v5 != v6);\n }\n }\n }\n return v2;\n}" + }, + { + "index": 380, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int** func0(int rownum, int colnum) {\n int** matrix = malloc(rownum * sizeof(int*));\n for (int i = 0; i < rownum; i++) {\n matrix[i] = malloc(colnum * sizeof(int));\n for (int j = 0; j < colnum; j++) {\n matrix[i][j] = i * j;\n }\n }\n return matrix;\n}", + "test": "int main() {\n\n int **result;\n\n int i, j;\n\n\n\n result = func0(3, 4);\n\n int expected_3_4[3][4] = {{0, 0, 0, 0}, {0, 1, 2, 3}, {0, 2, 4, 6}};\n\n for (i = 0; i < 3; i++) {\n\n for (j = 0; j < 4; j++) {\n\n assert(result[i][j] == expected_3_4[i][j]);\n\n }\n\n }\n\n\n\n result = func0(5, 7);\n\n int expected_5_7[5][7] = {{0, 0, 0, 0, 0, 0, 0}, {0, 1, 2, 3, 4, 5, 6}, {0, 2, 4, 6, 8, 10, 12}, {0, 3, 6, 9, 12, 15, 18}, {0, 4, 8, 12, 16, 20, 24}};\n\n for (i = 0; i < 5; i++) {\n\n for (j = 0; j < 7; j++) {\n\n assert(result[i][j] == expected_5_7[i][j]);\n\n }\n\n }\n\n\n\n result = func0(10, 15);\n\n int expected_10_15[10][15] = {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14}, {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28}, {0, 3, 6, 9, 12, 15, 18, 21, 24, 27, 30, 33, 36, 39, 42}, {0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56}, {0, 5, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 65, 70}, {0, 6, 12, 18, 24, 30, 36, 42, 48, 54, 60, 66, 72, 78, 84}, {0, 7, 14, 21, 28, 35, 42, 49, 56, 63, 70, 77, 84, 91, 98}, {0, 8, 16, 24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112}, {0, 9, 18, 27, 36, 45, 54, 63, 72, 81, 90, 99, 108, 117, 126}};\n\n for (i = 0; i < 10; i++) {\n\n for (j = 0; j < 15; j++) {\n\n assert(result[i][j] == expected_10_15[i][j]);\n\n }\n\n }\n\n\n\n for (i = 0; i < 10; i++) {\n\n free(result[i]); \n\n }\n\n free(result);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmovslq %edi,%rdi\npush %r14\npush %r13\npush %r12\npush %rbp\nmov %rdi,%rbp\nshl $0x3,%rdi\npush %rbx\nmov %esi,%ebx\nsub $0x8,%rsp\ncallq 10b0 \nmov %rax,%r12\ntest %ebp,%ebp\njle 1550 \nmovslq %ebx,%r13\nlea -0x1(%rbp),%r14d\nlea -0x1(%rbx),%ebp\nxor %r15d,%r15d\nshl $0x2,%r13\nadd $0x1,%rbp\nmov %r13,%rdi\ncallq 10b0 \nmov %rax,(%r12,%r15,8)\ntest %ebx,%ebx\njle 153d \nmov %r15d,%esi\nlea (%rax,%rbp,4),%rcx\nxor %edx,%edx\nnopl 0x0(%rax)\nmov %edx,(%rax)\nadd $0x4,%rax\nadd %esi,%edx\ncmp %rcx,%rax\njne 1530 \nlea 0x1(%r15),%rax\ncmp %r14,%r15\nje 1550 \nmov %rax,%r15\njmp 1510 \nnopl 0x0(%rax,%rax,1)\nadd $0x8,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\nmovsxd r13, edi\npush r12\nlea rdi, ds:0[r13*8]; size\nmov r12d, esi\npush rbp\npush rbx\ncall _malloc\nmov rbp, rax\ntest r13d, r13d\njle short loc_147E\nmovsxd rbx, r12d\nxor r14d, r14d\nshl rbx, 2\nnop dword ptr [rax+00000000h]\nloc_1448:\nmov rdi, rbx; size\ncall _malloc\nmov [rbp+r14*8+0], rax\ntest r12d, r12d\njle short loc_1475\nmov esi, r14d\nlea rcx, [rax+rbx]\nxor edx, edx\nnop dword ptr [rax+rax+00h]\nloc_1468:\nmov [rax], edx\nadd rax, 4\nadd edx, esi\ncmp rax, rcx\njnz short loc_1468\nloc_1475:\nadd r14, 1\ncmp r13, r14\njnz short loc_1448\nloc_147E:\npop rbx\nmov rax, rbp\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(int a1, int a2)\n{\n _QWORD *v2; // rbp\n __int64 i; // r14\n _DWORD *v4; // rax\n _DWORD *v5; // rcx\n int v6; // edx\n\n v2 = malloc(8LL * a1);\n if ( a1 > 0 )\n {\n for ( i = 0LL; i != a1; ++i )\n {\n v4 = malloc(4LL * a2);\n v2[i] = v4;\n if ( a2 > 0 )\n {\n v5 = &v4[a2];\n v6 = 0;\n do\n {\n *v4++ = v6;\n v6 += i;\n }\n while ( v4 != v5 );\n }\n }\n }\n return v2;\n}", + "ida_strip_asm": "sub_1410:\nendbr64\npush r14\npush r13\nmovsxd r13, edi\npush r12\nlea rdi, ds:0[r13*8]; size\nmov r12d, esi\npush rbp\npush rbx\ncall _malloc\nmov rbp, rax\ntest r13d, r13d\njle short loc_147E\nmovsxd rbx, r12d\nxor r14d, r14d\nshl rbx, 2\nnop dword ptr [rax+00000000h]\nloc_1448:\nmov rdi, rbx; size\ncall _malloc\nmov [rbp+r14*8+0], rax\ntest r12d, r12d\njle short loc_1475\nmov esi, r14d\nlea rcx, [rax+rbx]\nxor edx, edx\nnop dword ptr [rax+rax+00h]\nloc_1468:\nmov [rax], edx\nadd rax, 4\nadd edx, esi\ncmp rax, rcx\njnz short loc_1468\nloc_1475:\nadd r14, 1\ncmp r13, r14\njnz short loc_1448\nloc_147E:\npop rbx\nmov rax, rbp\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1410(int a1, int a2)\n{\n _QWORD *v2; // rbp\n __int64 i; // r14\n _DWORD *v4; // rax\n _DWORD *v5; // rcx\n int v6; // edx\n\n v2 = malloc(8LL * a1);\n if ( a1 > 0 )\n {\n for ( i = 0LL; i != a1; ++i )\n {\n v4 = malloc(4LL * a2);\n v2[i] = v4;\n if ( a2 > 0 )\n {\n v5 = &v4[a2];\n v6 = 0;\n do\n {\n *v4++ = v6;\n v6 += i;\n }\n while ( v4 != v5 );\n }\n }\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1410(int a1, int a2) {\n uint64_t *v2;\n long long i;\n uint32_t *v4;\n uint32_t *v5;\n int v6;\n v2 = malloc(8LL * a1);\n if (a1 > 0) {\n for (i = 0LL; i != a1; ++i) {\n v4 = malloc(4LL * a2);\n v2[i] = v4;\n if (a2 > 0) {\n v5 = &v4[a2];\n v6 = 0;\n do {\n *v4++ = v6;\n v6 += i;\n } while (v4 != v5);\n }\n }\n }\n return v2;\n}", + "ida_pseudo_norm": "uint64_t *func0(int a1, int a2) {\n uint64_t *v2;\n long long i;\n uint32_t *v4;\n uint32_t *v5;\n int v6;\n v2 = malloc(8LL * a1);\n if (a1 > 0) {\n for (i = 0LL; i != a1; ++i) {\n v4 = malloc(4LL * a2);\n v2[i] = v4;\n if (a2 > 0) {\n v5 = &v4[a2];\n v6 = 0;\n do {\n *v4++ = v6;\n v6 += i;\n } while (v4 != v5);\n }\n }\n }\n return v2;\n}" + }, + { + "index": 380, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int** func0(int rownum, int colnum) {\n int** matrix = malloc(rownum * sizeof(int*));\n for (int i = 0; i < rownum; i++) {\n matrix[i] = malloc(colnum * sizeof(int));\n for (int j = 0; j < colnum; j++) {\n matrix[i][j] = i * j;\n }\n }\n return matrix;\n}", + "test": "int main() {\n\n int **result;\n\n int i, j;\n\n\n\n result = func0(3, 4);\n\n int expected_3_4[3][4] = {{0, 0, 0, 0}, {0, 1, 2, 3}, {0, 2, 4, 6}};\n\n for (i = 0; i < 3; i++) {\n\n for (j = 0; j < 4; j++) {\n\n assert(result[i][j] == expected_3_4[i][j]);\n\n }\n\n }\n\n\n\n result = func0(5, 7);\n\n int expected_5_7[5][7] = {{0, 0, 0, 0, 0, 0, 0}, {0, 1, 2, 3, 4, 5, 6}, {0, 2, 4, 6, 8, 10, 12}, {0, 3, 6, 9, 12, 15, 18}, {0, 4, 8, 12, 16, 20, 24}};\n\n for (i = 0; i < 5; i++) {\n\n for (j = 0; j < 7; j++) {\n\n assert(result[i][j] == expected_5_7[i][j]);\n\n }\n\n }\n\n\n\n result = func0(10, 15);\n\n int expected_10_15[10][15] = {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14}, {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28}, {0, 3, 6, 9, 12, 15, 18, 21, 24, 27, 30, 33, 36, 39, 42}, {0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56}, {0, 5, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 65, 70}, {0, 6, 12, 18, 24, 30, 36, 42, 48, 54, 60, 66, 72, 78, 84}, {0, 7, 14, 21, 28, 35, 42, 49, 56, 63, 70, 77, 84, 91, 98}, {0, 8, 16, 24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112}, {0, 9, 18, 27, 36, 45, 54, 63, 72, 81, 90, 99, 108, 117, 126}};\n\n for (i = 0; i < 10; i++) {\n\n for (j = 0; j < 15; j++) {\n\n assert(result[i][j] == expected_10_15[i][j]);\n\n }\n\n }\n\n\n\n for (i = 0; i < 10; i++) {\n\n free(result[i]); \n\n }\n\n free(result);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmovslq %edi,%rdi\npush %r14\nmov %esi,%r14d\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nshl $0x3,%rdi\nsub $0x28,%rsp\ncallq 10b0 \nmov %rax,%r12\ntest %ebx,%ebx\njle 1800 \nmov %r14d,%ebp\nlea -0x1(%rbx),%eax\nmovslq %r14d,%r13\nmov %r14d,%ebx\nshr $0x2,%ebp\nmov %rax,0x8(%rsp)\nlea -0x1(%r14),%eax\nshl $0x2,%r13\nshl $0x4,%rbp\nmov %eax,0x14(%rsp)\nand $0xfffffffc,%ebx\nxor %r15d,%r15d\nmov %rbp,0x18(%rsp)\nxchg %ax,%ax\nmov %r13,%rdi\nmov %r15d,%ebp\ncallq 10b0 \ntest %r14d,%r14d\nmovdqa 0xbfa(%rip),%xmm5\nmov %rax,(%r12,%r15,8)\njle 17e8 \ncmpl $0x2,0x14(%rsp)\njbe 1812 \nmovd %r15d,%xmm6\nmov 0x18(%rsp),%rdi\nmovdqa 0xbc3(%rip),%xmm2\nmov %rax,%rdx\npshufd $0x0,%xmm6,%xmm3\nmovdqa %xmm3,%xmm4\nlea (%rdi,%rax,1),%rcx\npsrlq $0x20,%xmm4\nnopw 0x0(%rax,%rax,1)\nmovdqa %xmm2,%xmm0\nadd $0x10,%rdx\npaddd %xmm5,%xmm2\nmovdqa %xmm0,%xmm1\npsrlq $0x20,%xmm0\npmuludq %xmm3,%xmm1\npmuludq %xmm4,%xmm0\npshufd $0x8,%xmm1,%xmm1\npshufd $0x8,%xmm0,%xmm0\npunpckldq %xmm0,%xmm1\nmovups %xmm1,-0x10(%rdx)\ncmp %rcx,%rdx\njne 1778 \nmov %ebx,%edx\ncmp %ebx,%r14d\nje 17e8 \nmov %edx,%ecx\nmovslq %edx,%r10\nimul %ebp,%ecx\nlea 0x0(,%r10,4),%rdi\nmov %ecx,(%rax,%r10,4)\nlea 0x1(%rdx),%r10d\ncmp %r10d,%r14d\njle 17e8 \nadd %ebp,%ecx\nadd $0x2,%edx\nmov %ecx,0x4(%rax,%rdi,1)\ncmp %edx,%r14d\njle 17e8 \nlea 0x0(%rbp,%rcx,1),%r9d\nmov %r9d,0x8(%rax,%rdi,1)\nlea 0x1(%r15),%rax\ncmp 0x8(%rsp),%r15\nje 1800 \nmov %rax,%r15\njmpq 1720 \nnopl 0x0(%rax,%rax,1)\nadd $0x28,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nxor %edx,%edx\njmp 17b3 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov r15d, esi\npush r14\nmovsxd r14, edi\npush r13\nlea rdi, ds:0[r14*8]; size\npush r12\npush rbp\npush rbx\nsub rsp, 28h\ncall _malloc\nmov rbp, rax\ntest r14d, r14d\njle loc_16CE\nmovsxd r13, r15d\nmov r12d, r15d\nmov ebx, r15d\nlea rax, ds:0[r13*4]\nshr r12d, 2\nand ebx, 0FFFFFFFCh\nxor r13d, r13d\nmov [rsp+58h+size], rax\nshl r12, 4\nlea eax, [r15-1]\nmov [rsp+58h+var_44], eax\nmov [rsp+58h+var_40], r12\nnop word ptr [rax+rax+00h]\nloc_15F8:\nmov rdi, [rsp+58h+size]; size\nmov r12d, r13d\ncall _malloc\ntest r15d, r15d\nmovdqa xmm5, cs:xmmword_2330\nmov [rbp+r13*8+0], rax\nmov rdx, rax\njle loc_16C1\ncmp [rsp+58h+var_44], 2\njbe loc_16E0\nmovd xmm6, r13d\nmov rsi, [rsp+58h+var_40]\nmovdqa xmm2, cs:xmmword_2320\npshufd xmm3, xmm6, 0\nmovdqa xmm4, xmm3\nlea rcx, [rsi+rax]\npsrlq xmm4, 20h ; ' '\nnop dword ptr [rax]\nloc_1650:\nmovdqa xmm0, xmm2\nadd rax, 10h\npaddd xmm2, xmm5\nmovdqa xmm1, xmm0\npsrlq xmm0, 20h ; ' '\npmuludq xmm1, xmm3\npmuludq xmm0, xmm4\npshufd xmm1, xmm1, 8\npshufd xmm0, xmm0, 8\npunpckldq xmm1, xmm0\nmovups xmmword ptr [rax-10h], xmm1\ncmp rax, rcx\njnz short loc_1650\nmov eax, ebx\ncmp r15d, ebx\njz short loc_16C1\nloc_168B:\nmov ecx, r12d\nmovsxd r10, eax\nimul ecx, eax\nlea rdi, ds:0[r10*4]\nmov [rdx+r10*4], ecx\nlea r10d, [rax+1]\ncmp r15d, r10d\njle short loc_16C1\nadd ecx, r12d\nadd eax, 2\nmov [rdx+rdi+4], ecx\ncmp r15d, eax\njle short loc_16C1\nlea r8d, [r12+rcx]\nmov [rdx+rdi+8], r8d\nloc_16C1:\nadd r13, 1\ncmp r14, r13\njnz loc_15F8\nloc_16CE:\nadd rsp, 28h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_16E0:\nxor eax, eax\njmp short loc_168B", + "ida_pseudo": "_QWORD *__fastcall func0(int a1, int a2)\n{\n __int64 v2; // r14\n _QWORD *v3; // rbp\n __int64 i; // r13\n __m128i *v5; // rax\n __m128i si128; // xmm5\n __m128i *v7; // rdx\n __m128i v8; // xmm2\n __m128i v9; // xmm3\n __m128i *v10; // rcx\n __m128i v11; // xmm4\n __m128i v12; // xmm0\n signed int v13; // eax\n __int64 v14; // rdi\n __int32 v15; // ecx\n\n v2 = a1;\n v3 = malloc(8LL * a1);\n if ( a1 > 0 )\n {\n for ( i = 0LL; v2 != i; ++i )\n {\n v5 = (__m128i *)malloc(4LL * a2);\n si128 = _mm_load_si128((const __m128i *)&xmmword_2330);\n v3[i] = v5;\n v7 = v5;\n if ( a2 > 0 )\n {\n if ( (unsigned int)(a2 - 1) <= 2 )\n {\n v13 = 0;\nLABEL_8:\n v14 = v13;\n v7->m128i_i32[v14] = v13 * i;\n if ( a2 > v13 + 1 )\n {\n v15 = i + v13 * i;\n v7->m128i_i32[v14 + 1] = v15;\n if ( a2 > v13 + 2 )\n v7->m128i_i32[v14 + 2] = i + v15;\n }\n continue;\n }\n v8 = _mm_load_si128((const __m128i *)&xmmword_2320);\n v9 = _mm_shuffle_epi32(_mm_cvtsi32_si128(i), 0);\n v10 = &v5[(unsigned int)a2 >> 2];\n v11 = _mm_srli_epi64(v9, 0x20u);\n do\n {\n v12 = v8;\n ++v5;\n v8 = _mm_add_epi32(v8, si128);\n v5[-1] = _mm_unpacklo_epi32(\n _mm_shuffle_epi32(_mm_mul_epu32(v12, v9), 8),\n _mm_shuffle_epi32(_mm_mul_epu32(_mm_srli_epi64(v12, 0x20u), v11), 8));\n }\n while ( v5 != v10 );\n v13 = a2 & 0xFFFFFFFC;\n if ( a2 != (a2 & 0xFFFFFFFC) )\n goto LABEL_8;\n }\n }\n }\n return v3;\n}", + "ida_strip_asm": "sub_1590:\nendbr64\npush r15\nmov r15d, esi\npush r14\nmovsxd r14, edi\npush r13\nlea rdi, ds:0[r14*8]; size\npush r12\npush rbp\npush rbx\nsub rsp, 28h\ncall _malloc\nmov rbp, rax\ntest r14d, r14d\njle loc_16CE\nmovsxd r13, r15d\nmov r12d, r15d\nmov ebx, r15d\nlea rax, ds:0[r13*4]\nshr r12d, 2\nand ebx, 0FFFFFFFCh\nxor r13d, r13d\nmov [rsp+58h+size], rax\nshl r12, 4\nlea eax, [r15-1]\nmov [rsp+58h+var_44], eax\nmov [rsp+58h+var_40], r12\nnop word ptr [rax+rax+00h]\nloc_15F8:\nmov rdi, [rsp+58h+size]; size\nmov r12d, r13d\ncall _malloc\ntest r15d, r15d\nmovdqa xmm5, cs:xmmword_2330\nmov [rbp+r13*8+0], rax\nmov rdx, rax\njle loc_16C1\ncmp [rsp+58h+var_44], 2\njbe loc_16E0\nmovd xmm6, r13d\nmov rsi, [rsp+58h+var_40]\nmovdqa xmm2, cs:xmmword_2320\npshufd xmm3, xmm6, 0\nmovdqa xmm4, xmm3\nlea rcx, [rsi+rax]\npsrlq xmm4, 20h ; ' '\nnop dword ptr [rax]\nloc_1650:\nmovdqa xmm0, xmm2\nadd rax, 10h\npaddd xmm2, xmm5\nmovdqa xmm1, xmm0\npsrlq xmm0, 20h ; ' '\npmuludq xmm1, xmm3\npmuludq xmm0, xmm4\npshufd xmm1, xmm1, 8\npshufd xmm0, xmm0, 8\npunpckldq xmm1, xmm0\nmovups xmmword ptr [rax-10h], xmm1\ncmp rax, rcx\njnz short loc_1650\nmov eax, ebx\ncmp r15d, ebx\njz short loc_16C1\nloc_168B:\nmov ecx, r12d\nmovsxd r10, eax\nimul ecx, eax\nlea rdi, ds:0[r10*4]\nmov [rdx+r10*4], ecx\nlea r10d, [rax+1]\ncmp r15d, r10d\njle short loc_16C1\nadd ecx, r12d\nadd eax, 2\nmov [rdx+rdi+4], ecx\ncmp r15d, eax\njle short loc_16C1\nlea r8d, [r12+rcx]\nmov [rdx+rdi+8], r8d\nloc_16C1:\nadd r13, 1\ncmp r14, r13\njnz loc_15F8\nloc_16CE:\nadd rsp, 28h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_16E0:\nxor eax, eax\njmp short loc_168B", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1590(int a1, int a2)\n{\n __int64 v2; // r14\n _QWORD *v3; // rbp\n __int64 i; // r13\n __m128i *v5; // rax\n __m128i si128; // xmm5\n __m128i *v7; // rdx\n __m128i v8; // xmm2\n __m128i v9; // xmm3\n __m128i *v10; // rcx\n __m128i v11; // xmm4\n __m128i v12; // xmm0\n signed int v13; // eax\n __int64 v14; // rdi\n __int32 v15; // ecx\n\n v2 = a1;\n v3 = malloc(8LL * a1);\n if ( a1 > 0 )\n {\n for ( i = 0LL; v2 != i; ++i )\n {\n v5 = (__m128i *)malloc(4LL * a2);\n si128 = _mm_load_si128((const __m128i *)&xmmword_2330);\n v3[i] = v5;\n v7 = v5;\n if ( a2 > 0 )\n {\n if ( (unsigned int)(a2 - 1) <= 2 )\n {\n v13 = 0;\nLABEL_8:\n v14 = v13;\n v7->m128i_i32[v14] = v13 * i;\n if ( a2 > v13 + 1 )\n {\n v15 = i + v13 * i;\n v7->m128i_i32[v14 + 1] = v15;\n if ( a2 > v13 + 2 )\n v7->m128i_i32[v14 + 2] = i + v15;\n }\n continue;\n }\n v8 = _mm_load_si128((const __m128i *)&xmmword_2320);\n v9 = _mm_shuffle_epi32(_mm_cvtsi32_si128(i), 0);\n v10 = &v5[(unsigned int)a2 >> 2];\n v11 = _mm_srli_epi64(v9, 0x20u);\n do\n {\n v12 = v8;\n ++v5;\n v8 = _mm_add_epi32(v8, si128);\n v5[-1] = _mm_unpacklo_epi32(\n _mm_shuffle_epi32(_mm_mul_epu32(v12, v9), 8),\n _mm_shuffle_epi32(_mm_mul_epu32(_mm_srli_epi64(v12, 0x20u), v11), 8));\n }\n while ( v5 != v10 );\n v13 = a2 & 0xFFFFFFFC;\n if ( a2 != (a2 & 0xFFFFFFFC) )\n goto LABEL_8;\n }\n }\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1590(int a1, int a2) {\n long long v2;\n uint64_t *v3;\n long long i;\n __m128i *v5;\n __m128i si128;\n __m128i *v7;\n __m128i v8;\n __m128i v9;\n __m128i *v10;\n __m128i v11;\n __m128i v12;\n signed int v13;\n long long v14;\n int v15;\n v2 = a1;\n v3 = malloc(8LL * a1);\n if (a1 > 0) {\n for (i = 0LL; v2 != i; ++i) {\n v5 = (__m128i *)malloc(4LL * a2);\n si128 = _mm_load_si128((const __m128i *)&xmmword_2330);\n v3[i] = v5;\n v7 = v5;\n if (a2 > 0) {\n if ((unsigned int)(a2 - 1) <= 2) {\n v13 = 0;\n LABEL_8:\n v14 = v13;\n v7->m128i_i32[v14] = v13 * i;\n if (a2 > v13 + 1) {\n v15 = i + v13 * i;\n v7->m128i_i32[v14 + 1] = v15;\n if (a2 > v13 + 2) v7->m128i_i32[v14 + 2] = i + v15;\n }\n continue;\n }\n v8 = _mm_load_si128((const __m128i *)&xmmword_2320);\n v9 = _mm_shuffle_epi32(_mm_cvtsi32_si128(i), 0);\n v10 = &v5[(unsigned int)a2 >> 2];\n v11 = _mm_srli_epi64(v9, 32u);\n do {\n v12 = v8;\n ++v5;\n v8 = _mm_add_epi32(v8, si128);\n v5[-1] = _mm_unpacklo_epi32(\n _mm_shuffle_epi32(_mm_mul_epu32(v12, v9), 8),\n _mm_shuffle_epi32(_mm_mul_epu32(_mm_srli_epi64(v12, 32u), v11),\n 8));\n } while (v5 != v10);\n v13 = a2 & 4294967292;\n if (a2 != (a2 & 4294967292)) goto LABEL_8;\n }\n }\n }\n return v3;\n}", + "ida_pseudo_norm": "uint64_t *func0(int a1, int a2) {\n long long v2;\n uint64_t *v3;\n long long i;\n __m128i *v5;\n __m128i si128;\n __m128i *v7;\n __m128i v8;\n __m128i v9;\n __m128i *v10;\n __m128i v11;\n __m128i v12;\n signed int v13;\n long long v14;\n int v15;\n v2 = a1;\n v3 = malloc(8LL * a1);\n if (a1 > 0) {\n for (i = 0LL; v2 != i; ++i) {\n v5 = (__m128i *)malloc(4LL * a2);\n si128 = _mm_load_si128((const __m128i *)&xmmword_2330);\n v3[i] = v5;\n v7 = v5;\n if (a2 > 0) {\n if ((unsigned int)(a2 - 1) <= 2) {\n v13 = 0;\n LABEL_8:\n v14 = v13;\n v7->m128i_i32[v14] = v13 * i;\n if (a2 > v13 + 1) {\n v15 = i + v13 * i;\n v7->m128i_i32[v14 + 1] = v15;\n if (a2 > v13 + 2) v7->m128i_i32[v14 + 2] = i + v15;\n }\n continue;\n }\n v8 = _mm_load_si128((const __m128i *)&xmmword_2320);\n v9 = _mm_shuffle_epi32(_mm_cvtsi32_si128(i), 0);\n v10 = &v5[(unsigned int)a2 >> 2];\n v11 = _mm_srli_epi64(v9, 32u);\n do {\n v12 = v8;\n ++v5;\n v8 = _mm_add_epi32(v8, si128);\n v5[-1] = _mm_unpacklo_epi32(\n _mm_shuffle_epi32(_mm_mul_epu32(v12, v9), 8),\n _mm_shuffle_epi32(_mm_mul_epu32(_mm_srli_epi64(v12, 32u), v11),\n 8));\n } while (v5 != v10);\n v13 = a2 & 4294967292;\n if (a2 != (a2 & 4294967292)) goto LABEL_8;\n }\n }\n }\n return v3;\n}" + }, + { + "index": 381, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n const char* name;\n\n int score1;\n\n int score2;\n\n} Tuple;\n\n\n\nint compare_by_index(const void *a, const void *b, void *index_ptr) {\n\n int index = *(int*)index_ptr;\n\n Tuple *tupleA = (Tuple*)a;\n\n Tuple *tupleB = (Tuple*)b;\n\n \n\n if (index == 0) {\n\n return strcmp(tupleA->name, tupleB->name);\n\n } else if (index == 1) {\n\n return (tupleA->score1 - tupleB->score1);\n\n } else if (index == 2) {\n\n return (tupleA->score2 - tupleB->score2);\n\n }\n\n return 0; // Should never be reached, assuming valid index\n\n}\n\n\n\n", + "func": "void func0(Tuple *list_data, int size, int index_no) {\n qsort_r(list_data, size, sizeof(Tuple), compare_by_index, &index_no);\n}", + "test": "int main() {\n\n Tuple data[] = {\n\n {\"Greyson Fulton\", 98, 99},\n\n {\"Brady Kent\", 97, 96},\n\n {\"Wyatt Knott\", 91, 94},\n\n {\"Beau Turnbull\", 94, 98}\n\n };\n\n int num_tuples = sizeof(data) / sizeof(data[0]);\n\n\n\n func0(data, num_tuples, 0);\n\n assert(strcmp(data[0].name, \"Beau Turnbull\") == 0 && strcmp(data[1].name, \"Brady Kent\") == 0 && strcmp(data[2].name, \"Greyson Fulton\") == 0 && strcmp(data[3].name, \"Wyatt Knott\") == 0);\n\n\n\n func0(data, num_tuples, 1);\n\n assert(data[0].score1 == 91 && data[1].score1 == 94 && data[2].score1 == 97 && data[3].score1 == 98);\n\n\n\n func0(data, num_tuples, 2);\n\n assert(data[0].score2 == 94 && data[1].score2 == 96 && data[2].score2 == 98 && data[3].score2 == 99);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %rdi,-0x8(%rbp)\nmov %esi,-0xc(%rbp)\nmov %edx,-0x10(%rbp)\nlea -0x10(%rbp),%rdx\nmov -0xc(%rbp),%esi\nmov -0x8(%rbp),%rax\nmov %rdx,%r8\nlea -0xb8(%rip),%rcx\nmov $0x10,%edx\nmov %rax,%rdi\nmov $0x0,%eax\ncallq 10b0 \nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+nmemb+4], rdi\nmov dword ptr [rbp+nmemb], esi\nmov [rbp+arg], edx\nlea rdx, [rbp+arg]\nmov esi, dword ptr [rbp+nmemb]; nmemb\nmov rax, [rbp+nmemb+4]\nmov r8, rdx; arg\nlea rdx, compare_by_index\nmov rcx, rdx; compar\nmov edx, 10h; size\nmov rdi, rax; base\nmov eax, 0\ncall _qsort_r\nnop\nleave\nretn", + "ida_pseudo": "void __fastcall func0(void *a1, unsigned int a2, int a3)\n{\n _DWORD arg[2]; // [rsp+0h] [rbp-10h] BYREF\n void *nmemb_4; // [rsp+8h] [rbp-8h]\n\n nmemb_4 = a1;\n arg[1] = a2;\n arg[0] = a3;\n qsort_r(a1, a2, 0x10uLL, compare_by_index, arg);\n}", + "ida_strip_asm": "sub_1236:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+nmemb+4], rdi\nmov dword ptr [rbp+nmemb], esi\nmov [rbp+arg], edx\nlea rdx, [rbp+arg]\nmov esi, dword ptr [rbp+nmemb]; nmemb\nmov rax, [rbp+nmemb+4]\nmov r8, rdx; arg\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 10h; size\nmov rdi, rax; base\nmov eax, 0\ncall _qsort_r\nnop\nleave\nretn", + "ida_strip_pseudo": "void __fastcall sub_1236(void *a1, unsigned int a2, int a3)\n{\n _DWORD arg[2]; // [rsp+0h] [rbp-10h] BYREF\n void *nmemb_4; // [rsp+8h] [rbp-8h]\n\n nmemb_4 = a1;\n arg[1] = a2;\n arg[0] = a3;\n qsort_r(a1, a2, 0x10uLL, compar, arg);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1236(void *a1, unsigned int a2, int a3) {\n uint32_t arg[2];\n void *nmemb_4;\n nmemb_4 = a1;\n arg[1] = a2;\n arg[0] = a3;\n qsort_r(a1, a2, 16uLL, compar, arg);\n}", + "ida_pseudo_norm": "void func0(void *a1, unsigned int a2, int a3) {\n uint32_t arg[2];\n void *nmemb_4;\n nmemb_4 = a1;\n arg[1] = a2;\n arg[0] = a3;\n qsort_r(a1, a2, 16uLL, compare_by_index, arg);\n}" + }, + { + "index": 381, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n const char* name;\n\n int score1;\n\n int score2;\n\n} Tuple;\n\n\n\nint compare_by_index(const void *a, const void *b, void *index_ptr) {\n\n int index = *(int*)index_ptr;\n\n Tuple *tupleA = (Tuple*)a;\n\n Tuple *tupleB = (Tuple*)b;\n\n \n\n if (index == 0) {\n\n return strcmp(tupleA->name, tupleB->name);\n\n } else if (index == 1) {\n\n return (tupleA->score1 - tupleB->score1);\n\n } else if (index == 2) {\n\n return (tupleA->score2 - tupleB->score2);\n\n }\n\n return 0; // Should never be reached, assuming valid index\n\n}\n\n\n\n", + "func": "void func0(Tuple *list_data, int size, int index_no) {\n qsort_r(list_data, size, sizeof(Tuple), compare_by_index, &index_no);\n}", + "test": "int main() {\n\n Tuple data[] = {\n\n {\"Greyson Fulton\", 98, 99},\n\n {\"Brady Kent\", 97, 96},\n\n {\"Wyatt Knott\", 91, 94},\n\n {\"Beau Turnbull\", 94, 98}\n\n };\n\n int num_tuples = sizeof(data) / sizeof(data[0]);\n\n\n\n func0(data, num_tuples, 0);\n\n assert(strcmp(data[0].name, \"Beau Turnbull\") == 0 && strcmp(data[1].name, \"Brady Kent\") == 0 && strcmp(data[2].name, \"Greyson Fulton\") == 0 && strcmp(data[3].name, \"Wyatt Knott\") == 0);\n\n\n\n func0(data, num_tuples, 1);\n\n assert(data[0].score1 == 91 && data[1].score1 == 94 && data[2].score1 == 97 && data[3].score1 == 98);\n\n\n\n func0(data, num_tuples, 2);\n\n assert(data[0].score2 == 94 && data[1].score2 == 96 && data[2].score2 == 98 && data[3].score2 == 99);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x18,%rsp\nmov %edx,0xc(%rsp)\nlea 0xc(%rsp),%r8\nlea -0x54(%rip),%rcx\nmov $0x10,%edx\nmov $0x0,%eax\ncallq 10b0 \nadd $0x18,%rsp\nretq\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 18h\nmov [rsp+18h+arg], edx\nlea r8, [rsp+18h+arg]; arg\nlea rcx, compare_by_index; compar\nmov edx, 10h; size\nmov eax, 0\ncall _qsort_r\nadd rsp, 18h\nretn", + "ida_pseudo": "void __fastcall func0(void *a1, size_t a2, int a3)\n{\n _DWORD arg[3]; // [rsp+Ch] [rbp-Ch] BYREF\n\n arg[0] = a3;\n qsort_r(a1, a2, 0x10uLL, compare_by_index, arg);\n}", + "ida_strip_asm": "sub_11E5:\nendbr64\nsub rsp, 18h\nmov [rsp+18h+arg], edx\nlea r8, [rsp+18h+arg]; arg\nlea rcx, compar; compar\nmov edx, 10h; size\nmov eax, 0\ncall _qsort_r\nadd rsp, 18h\nretn", + "ida_strip_pseudo": "void __fastcall sub_11E5(void *a1, size_t a2, int a3)\n{\n _DWORD arg[3]; // [rsp+Ch] [rbp-Ch] BYREF\n\n arg[0] = a3;\n qsort_r(a1, a2, 0x10uLL, compar, arg);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_11E5(void *a1, unsigned int a2, int a3) {\n uint32_t arg[3];\n arg[0] = a3;\n qsort_r(a1, a2, 16uLL, compar, arg);\n}", + "ida_pseudo_norm": "void func0(void *a1, unsigned int a2, int a3) {\n uint32_t arg[3];\n arg[0] = a3;\n qsort_r(a1, a2, 16uLL, compare_by_index, arg);\n}" + }, + { + "index": 381, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n const char* name;\n\n int score1;\n\n int score2;\n\n} Tuple;\n\n\n\nint compare_by_index(const void *a, const void *b, void *index_ptr) {\n\n int index = *(int*)index_ptr;\n\n Tuple *tupleA = (Tuple*)a;\n\n Tuple *tupleB = (Tuple*)b;\n\n \n\n if (index == 0) {\n\n return strcmp(tupleA->name, tupleB->name);\n\n } else if (index == 1) {\n\n return (tupleA->score1 - tupleB->score1);\n\n } else if (index == 2) {\n\n return (tupleA->score2 - tupleB->score2);\n\n }\n\n return 0; // Should never be reached, assuming valid index\n\n}\n\n\n\n", + "func": "void func0(Tuple *list_data, int size, int index_no) {\n qsort_r(list_data, size, sizeof(Tuple), compare_by_index, &index_no);\n}", + "test": "int main() {\n\n Tuple data[] = {\n\n {\"Greyson Fulton\", 98, 99},\n\n {\"Brady Kent\", 97, 96},\n\n {\"Wyatt Knott\", 91, 94},\n\n {\"Beau Turnbull\", 94, 98}\n\n };\n\n int num_tuples = sizeof(data) / sizeof(data[0]);\n\n\n\n func0(data, num_tuples, 0);\n\n assert(strcmp(data[0].name, \"Beau Turnbull\") == 0 && strcmp(data[1].name, \"Brady Kent\") == 0 && strcmp(data[2].name, \"Greyson Fulton\") == 0 && strcmp(data[3].name, \"Wyatt Knott\") == 0);\n\n\n\n func0(data, num_tuples, 1);\n\n assert(data[0].score1 == 91 && data[1].score1 == 94 && data[2].score1 == 97 && data[3].score1 == 98);\n\n\n\n func0(data, num_tuples, 2);\n\n assert(data[0].score2 == 94 && data[1].score2 == 96 && data[2].score2 == 98 && data[3].score2 == 99);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x18,%rsp\nlea -0x5f(%rip),%rcx\nxor %eax,%eax\nmov %edx,0xc(%rsp)\nlea 0xc(%rsp),%r8\nmov $0x10,%edx\ncallq 10b0 \nadd $0x18,%rsp\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 18h\nlea rcx, compare_by_index; compar\nxor eax, eax\nmov [rsp+18h+arg], edx\nlea r8, [rsp+18h+arg]; arg\nmov edx, 10h; size\ncall _qsort_r\nadd rsp, 18h\nretn", + "ida_pseudo": "void __fastcall func0(void *a1, size_t a2, int a3)\n{\n _DWORD arg[3]; // [rsp+Ch] [rbp-Ch] BYREF\n\n arg[0] = a3;\n qsort_r(a1, a2, 0x10uLL, compare_by_index, arg);\n}", + "ida_strip_asm": "sub_1420:\nendbr64\nsub rsp, 18h\nlea rcx, compar; compar\nxor eax, eax\nmov [rsp+18h+arg], edx\nlea r8, [rsp+18h+arg]; arg\nmov edx, 10h; size\ncall _qsort_r\nadd rsp, 18h\nretn", + "ida_strip_pseudo": "void __fastcall sub_1420(void *a1, size_t a2, int a3)\n{\n _DWORD arg[3]; // [rsp+Ch] [rbp-Ch] BYREF\n\n arg[0] = a3;\n qsort_r(a1, a2, 0x10uLL, compar, arg);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1420(void *a1, unsigned int a2, int a3) {\n uint32_t arg[3];\n arg[0] = a3;\n qsort_r(a1, a2, 16uLL, compar, arg);\n}", + "ida_pseudo_norm": "void func0(void *a1, unsigned int a2, int a3) {\n uint32_t arg[3];\n arg[0] = a3;\n qsort_r(a1, a2, 16uLL, compare_by_index, arg);\n}" + }, + { + "index": 381, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n const char* name;\n\n int score1;\n\n int score2;\n\n} Tuple;\n\n\n\nint compare_by_index(const void *a, const void *b, void *index_ptr) {\n\n int index = *(int*)index_ptr;\n\n Tuple *tupleA = (Tuple*)a;\n\n Tuple *tupleB = (Tuple*)b;\n\n \n\n if (index == 0) {\n\n return strcmp(tupleA->name, tupleB->name);\n\n } else if (index == 1) {\n\n return (tupleA->score1 - tupleB->score1);\n\n } else if (index == 2) {\n\n return (tupleA->score2 - tupleB->score2);\n\n }\n\n return 0; // Should never be reached, assuming valid index\n\n}\n\n\n\n", + "func": "void func0(Tuple *list_data, int size, int index_no) {\n qsort_r(list_data, size, sizeof(Tuple), compare_by_index, &index_no);\n}", + "test": "int main() {\n\n Tuple data[] = {\n\n {\"Greyson Fulton\", 98, 99},\n\n {\"Brady Kent\", 97, 96},\n\n {\"Wyatt Knott\", 91, 94},\n\n {\"Beau Turnbull\", 94, 98}\n\n };\n\n int num_tuples = sizeof(data) / sizeof(data[0]);\n\n\n\n func0(data, num_tuples, 0);\n\n assert(strcmp(data[0].name, \"Beau Turnbull\") == 0 && strcmp(data[1].name, \"Brady Kent\") == 0 && strcmp(data[2].name, \"Greyson Fulton\") == 0 && strcmp(data[3].name, \"Wyatt Knott\") == 0);\n\n\n\n func0(data, num_tuples, 1);\n\n assert(data[0].score1 == 91 && data[1].score1 == 94 && data[2].score1 == 97 && data[3].score1 == 98);\n\n\n\n func0(data, num_tuples, 2);\n\n assert(data[0].score2 == 94 && data[1].score2 == 96 && data[2].score2 == 98 && data[3].score2 == 99);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x18,%rsp\nlea -0x5f(%rip),%rcx\nxor %eax,%eax\nmov %edx,0xc(%rsp)\nlea 0xc(%rsp),%r8\nmov $0x10,%edx\ncallq 10b0 \nadd $0x18,%rsp\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 18h\nlea rcx, compare_by_index; compar\nxor eax, eax\nmov [rsp+18h+arg], edx\nlea r8, [rsp+18h+arg]; arg\nmov edx, 10h; size\ncall _qsort_r\nadd rsp, 18h\nretn", + "ida_pseudo": "void __fastcall func0(void *a1, size_t a2, int a3)\n{\n _DWORD arg[3]; // [rsp+Ch] [rbp-Ch] BYREF\n\n arg[0] = a3;\n qsort_r(a1, a2, 0x10uLL, compare_by_index, arg);\n}", + "ida_strip_asm": "sub_1420:\nendbr64\nsub rsp, 18h\nlea rcx, compar; compar\nxor eax, eax\nmov [rsp+18h+arg], edx\nlea r8, [rsp+18h+arg]; arg\nmov edx, 10h; size\ncall _qsort_r\nadd rsp, 18h\nretn", + "ida_strip_pseudo": "void __fastcall sub_1420(void *a1, size_t a2, int a3)\n{\n _DWORD arg[3]; // [rsp+Ch] [rbp-Ch] BYREF\n\n arg[0] = a3;\n qsort_r(a1, a2, 0x10uLL, compar, arg);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1420(void *a1, unsigned int a2, int a3) {\n uint32_t arg[3];\n arg[0] = a3;\n qsort_r(a1, a2, 16uLL, compar, arg);\n}", + "ida_pseudo_norm": "void func0(void *a1, unsigned int a2, int a3) {\n uint32_t arg[3];\n arg[0] = a3;\n qsort_r(a1, a2, 16uLL, compare_by_index, arg);\n}" + }, + { + "index": 382, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int A[], int n) {\n int left = 0;\n int right = n - 1;\n while (left <= right) {\n if (A[left] <= A[right]) {\n return left;\n }\n int mid = (left + right) / 2;\n int next = (mid + 1) % n;\n int prev = (mid - 1 + n) % n;\n if (A[mid] <= A[next] && A[mid] <= A[prev]) {\n return mid;\n } else if (A[mid] <= A[right]) {\n right = mid - 1;\n } else if (A[mid] >= A[left]) {\n left = mid + 1;\n }\n }\n return -1;\n}", + "test": "int main() {\n\n int arr1[] = {8, 9, 10, 1, 2, 3, 4, 5, 6, 7};\n\n int n1 = sizeof(arr1) / sizeof(arr1[0]);\n\n assert(func0(arr1, n1) == 3);\n\n\n\n int arr2[] = {8, 9, 10, 2, 5, 6};\n\n int n2 = sizeof(arr2) / sizeof(arr2[0]);\n\n assert(func0(arr2, n2) == 3);\n\n\n\n int arr3[] = {2, 5, 6, 8, 9, 10};\n\n int n3 = sizeof(arr3) / sizeof(arr3[0]);\n\n assert(func0(arr3, n3) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmovl $0x0,-0x14(%rbp)\nmov -0x2c(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0x10(%rbp)\njmpq 12d4 \nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njg 11c5 \nmov -0x14(%rbp),%eax\njmpq 12e5 \nmov -0x14(%rbp),%edx\nmov -0x10(%rbp),%eax\nadd %edx,%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nmov %eax,-0xc(%rbp)\nmov -0xc(%rbp),%eax\nadd $0x1,%eax\ncltd\nidivl -0x2c(%rbp)\nmov %edx,-0x8(%rbp)\nmov -0xc(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x2c(%rbp),%eax\nadd %edx,%eax\ncltd\nidivl -0x2c(%rbp)\nmov %edx,-0x4(%rbp)\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njg 1260 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njg 1260 \nmov -0xc(%rbp),%eax\njmpq 12e5 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njg 129b \nmov -0xc(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0x10(%rbp)\njmp 12d4 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njl 12d4 \nmov -0xc(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x14(%rbp)\nmov -0x14(%rbp),%eax\ncmp -0x10(%rbp),%eax\njle 118d \nmov $0xffffffff,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_14], 0\nmov eax, [rbp+var_2C]\nsub eax, 1\nmov [rbp+var_10], eax\njmp loc_12D4\nloc_118D:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njg short loc_11C5\nmov eax, [rbp+var_14]\njmp loc_12E5\nloc_11C5:\nmov edx, [rbp+var_14]\nmov eax, [rbp+var_10]\nadd eax, edx\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_C], eax\nmov eax, [rbp+var_C]\nadd eax, 1\ncdq\nidiv [rbp+var_2C]\nmov [rbp+var_8], edx\nmov eax, [rbp+var_C]\nlea edx, [rax-1]\nmov eax, [rbp+var_2C]\nadd eax, edx\ncdq\nidiv [rbp+var_2C]\nmov [rbp+var_4], edx\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njg short loc_1260\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njg short loc_1260\nmov eax, [rbp+var_C]\njmp loc_12E5\nloc_1260:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njg short loc_129B\nmov eax, [rbp+var_C]\nsub eax, 1\nmov [rbp+var_10], eax\njmp short loc_12D4\nloc_129B:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_14]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njl short loc_12D4\nmov eax, [rbp+var_C]\nadd eax, 1\nmov [rbp+var_14], eax\nloc_12D4:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_10]\njle loc_118D\nmov eax, 0FFFFFFFFh\nloc_12E5:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int v3; // [rsp+18h] [rbp-14h]\n int v4; // [rsp+1Ch] [rbp-10h]\n int v5; // [rsp+20h] [rbp-Ch]\n\n v3 = 0;\n v4 = a2 - 1;\n while ( v3 <= v4 )\n {\n if ( *(_DWORD *)(4LL * v3 + a1) <= *(_DWORD *)(4LL * v4 + a1) )\n return (unsigned int)v3;\n v5 = (v3 + v4) / 2;\n if ( *(_DWORD *)(4LL * v5 + a1) <= *(_DWORD *)(4LL * ((v5 + 1) % a2) + a1)\n && *(_DWORD *)(4LL * v5 + a1) <= *(_DWORD *)(4LL * (((v3 + v4) / 2 - 1 + a2) % a2) + a1) )\n {\n return (unsigned int)v5;\n }\n if ( *(_DWORD *)(4LL * v5 + a1) > *(_DWORD *)(4LL * v4 + a1) )\n {\n if ( *(_DWORD *)(4LL * v5 + a1) >= *(_DWORD *)(4LL * v3 + a1) )\n v3 = v5 + 1;\n }\n else\n {\n v4 = v5 - 1;\n }\n }\n return 0xFFFFFFFFLL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_14], 0\nmov eax, [rbp+var_2C]\nsub eax, 1\nmov [rbp+var_10], eax\njmp loc_12D4\nloc_118D:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njg short loc_11C5\nmov eax, [rbp+var_14]\njmp loc_12E5\nloc_11C5:\nmov edx, [rbp+var_14]\nmov eax, [rbp+var_10]\nadd eax, edx\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_C], eax\nmov eax, [rbp+var_C]\nadd eax, 1\ncdq\nidiv [rbp+var_2C]\nmov [rbp+var_8], edx\nmov eax, [rbp+var_C]\nlea edx, [rax-1]\nmov eax, [rbp+var_2C]\nadd eax, edx\ncdq\nidiv [rbp+var_2C]\nmov [rbp+var_4], edx\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njg short loc_1260\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njg short loc_1260\nmov eax, [rbp+var_C]\njmp loc_12E5\nloc_1260:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njg short loc_129B\nmov eax, [rbp+var_C]\nsub eax, 1\nmov [rbp+var_10], eax\njmp short loc_12D4\nloc_129B:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_14]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njl short loc_12D4\nmov eax, [rbp+var_C]\nadd eax, 1\nmov [rbp+var_14], eax\nloc_12D4:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_10]\njle loc_118D\nmov eax, 0FFFFFFFFh\nloc_12E5:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int v3; // [rsp+18h] [rbp-14h]\n int v4; // [rsp+1Ch] [rbp-10h]\n int v5; // [rsp+20h] [rbp-Ch]\n\n v3 = 0;\n v4 = a2 - 1;\n while ( v3 <= v4 )\n {\n if ( *(_DWORD *)(4LL * v3 + a1) <= *(_DWORD *)(4LL * v4 + a1) )\n return (unsigned int)v3;\n v5 = (v3 + v4) / 2;\n if ( *(_DWORD *)(4LL * v5 + a1) <= *(_DWORD *)(4LL * ((v5 + 1) % a2) + a1)\n && *(_DWORD *)(4LL * v5 + a1) <= *(_DWORD *)(4LL * (((v3 + v4) / 2 - 1 + a2) % a2) + a1) )\n {\n return (unsigned int)v5;\n }\n if ( *(_DWORD *)(4LL * v5 + a1) > *(_DWORD *)(4LL * v4 + a1) )\n {\n if ( *(_DWORD *)(4LL * v5 + a1) >= *(_DWORD *)(4LL * v3 + a1) )\n v3 = v5 + 1;\n }\n else\n {\n v4 = v5 - 1;\n }\n }\n return 0xFFFFFFFFLL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int v3;\n int v4;\n int v5;\n v3 = 0;\n v4 = a2 - 1;\n while (v3 <= v4) {\n if (*(uint32_t *)(4LL * v3 + a1) <= *(uint32_t *)(4LL * v4 + a1))\n return (unsigned int)v3;\n v5 = (v3 + v4) / 2;\n if (*(uint32_t *)(4LL * v5 + a1) <=\n *(uint32_t *)(4LL * ((v5 + 1) % a2) + a1) &&\n *(uint32_t *)(4LL * v5 + a1) <=\n *(uint32_t *)(4LL * (((v3 + v4) / 2 - 1 + a2) % a2) + a1)) {\n return (unsigned int)v5;\n }\n if (*(uint32_t *)(4LL * v5 + a1) > *(uint32_t *)(4LL * v4 + a1)) {\n if (*(uint32_t *)(4LL * v5 + a1) >= *(uint32_t *)(4LL * v3 + a1))\n v3 = v5 + 1;\n } else {\n v4 = v5 - 1;\n }\n }\n return 4294967295LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int v3;\n int v4;\n int v5;\n v3 = 0;\n v4 = a2 - 1;\n while (v3 <= v4) {\n if (*(uint32_t *)(4LL * v3 + a1) <= *(uint32_t *)(4LL * v4 + a1))\n return (unsigned int)v3;\n v5 = (v3 + v4) / 2;\n if (*(uint32_t *)(4LL * v5 + a1) <=\n *(uint32_t *)(4LL * ((v5 + 1) % a2) + a1) &&\n *(uint32_t *)(4LL * v5 + a1) <=\n *(uint32_t *)(4LL * (((v3 + v4) / 2 - 1 + a2) % a2) + a1)) {\n return (unsigned int)v5;\n }\n if (*(uint32_t *)(4LL * v5 + a1) > *(uint32_t *)(4LL * v4 + a1)) {\n if (*(uint32_t *)(4LL * v5 + a1) >= *(uint32_t *)(4LL * v3 + a1))\n v3 = v5 + 1;\n } else {\n v4 = v5 - 1;\n }\n }\n return 4294967295LL;\n}" + }, + { + "index": 382, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int A[], int n) {\n int left = 0;\n int right = n - 1;\n while (left <= right) {\n if (A[left] <= A[right]) {\n return left;\n }\n int mid = (left + right) / 2;\n int next = (mid + 1) % n;\n int prev = (mid - 1 + n) % n;\n if (A[mid] <= A[next] && A[mid] <= A[prev]) {\n return mid;\n } else if (A[mid] <= A[right]) {\n right = mid - 1;\n } else if (A[mid] >= A[left]) {\n left = mid + 1;\n }\n }\n return -1;\n}", + "test": "int main() {\n\n int arr1[] = {8, 9, 10, 1, 2, 3, 4, 5, 6, 7};\n\n int n1 = sizeof(arr1) / sizeof(arr1[0]);\n\n assert(func0(arr1, n1) == 3);\n\n\n\n int arr2[] = {8, 9, 10, 2, 5, 6};\n\n int n2 = sizeof(arr2) / sizeof(arr2[0]);\n\n assert(func0(arr2, n2) == 3);\n\n\n\n int arr3[] = {2, 5, 6, 8, 9, 10};\n\n int n3 = sizeof(arr3) / sizeof(arr3[0]);\n\n assert(func0(arr3, n3) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nlea -0x1(%rsi),%ecx\nmov $0x0,%r10d\nmovslq %r10d,%rax\nlea (%rdi,%rax,4),%rbx\njmp 118c \ncmp %r13d,%r8d\njl 11e1 \nmov %ebp,%ecx\ncmp %ecx,%r10d\njg 11ea \nmov (%rbx),%r11d\nmovslq %ecx,%rax\nmov (%rdi,%rax,4),%r8d\ncmp %r8d,%r11d\njle 11f0 \nlea (%r10,%rcx,1),%edx\nmov %edx,%eax\nshr $0x1f,%eax\nadd %edx,%eax\nsar %eax\nmov %eax,%r12d\nlea 0x1(%rax),%r9d\nlea -0x1(%rax),%ebp\ncltq\nmov (%rdi,%rax,4),%r13d\nmov %r9d,%eax\ncltd\nidiv %esi\nmovslq %edx,%rdx\ncmp (%rdi,%rdx,4),%r13d\njg 1185 \nlea 0x0(%rbp,%rsi,1),%eax\ncltd\nidiv %esi\nmovslq %edx,%rdx\ncmp (%rdi,%rdx,4),%r13d\njg 1185 \nmov %r12d,%r10d\njmp 11f0 \ncmp %r13d,%r11d\ncmovle %r9d,%r10d\njmp 117c \nmov $0xffffffff,%r10d\nmov %r10d,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nmov r8d, esi\nlea esi, [rsi-1]\nmov r11d, 0\nloc_117F:\nmovsxd rax, r11d\nlea rbp, [rdi+rax*4]\njmp short loc_1190\nloc_1188:\ncmp r10d, r9d\njl short loc_11E7\nmov esi, r13d\nloc_1190:\ncmp r11d, esi\njg short loc_11F0\nmov ebx, [rbp+0]\nmovsxd rax, esi\nmov r10d, [rdi+rax*4]\ncmp ebx, r10d\njle short loc_11F6\nlea eax, [r11+rsi]\nmov ecx, eax\nshr ecx, 1Fh\nadd ecx, eax\nsar ecx, 1\nlea r12d, [rcx+1]\nlea r13d, [rcx-1]\nmovsxd rax, ecx\nmov r9d, [rdi+rax*4]\nmov eax, r12d\ncdq\nidiv r8d\nmovsxd rdx, edx\ncmp r9d, [rdi+rdx*4]\njg short loc_1188\nlea eax, [r13+r8+0]\ncdq\nidiv r8d\nmovsxd rdx, edx\ncmp r9d, [rdi+rdx*4]\njg short loc_1188\nmov r11d, ecx\njmp short loc_11F6\nloc_11E7:\ncmp ebx, r9d\ncmovle r11d, r12d\njmp short loc_117F\nloc_11F0:\nmov r11d, 0FFFFFFFFh\nloc_11F6:\nmov eax, r11d\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int v3; // esi\n int v4; // r11d\n int v5; // ebx\n int v6; // r10d\n int v7; // ecx\n int v8; // r9d\n\n v3 = a2 - 1;\n v4 = 0;\n while ( v4 <= v3 )\n {\n v5 = *(_DWORD *)(a1 + 4LL * v4);\n v6 = *(_DWORD *)(a1 + 4LL * v3);\n if ( v5 <= v6 )\n return (unsigned int)v4;\n v7 = (v4 + v3) / 2;\n v8 = *(_DWORD *)(a1 + 4LL * v7);\n if ( v8 <= *(_DWORD *)(a1 + 4LL * ((v7 + 1) % a2)) && v8 <= *(_DWORD *)(a1 + 4LL * ((v7 - 1 + a2) % a2)) )\n return (unsigned int)((v4 + v3) / 2);\n if ( v6 < v8 )\n {\n if ( v5 <= v8 )\n v4 = v7 + 1;\n }\n else\n {\n v3 = v7 - 1;\n }\n }\n return (unsigned int)-1;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nmov r8d, esi\nlea esi, [rsi-1]\nmov r11d, 0\nloc_117F:\nmovsxd rax, r11d\nlea rbp, [rdi+rax*4]\njmp short loc_1190\nloc_1188:\ncmp r10d, r9d\njl short loc_11E7\nmov esi, r13d\nloc_1190:\ncmp r11d, esi\njg short loc_11F0\nmov ebx, [rbp+0]\nmovsxd rax, esi\nmov r10d, [rdi+rax*4]\ncmp ebx, r10d\njle short loc_11F6\nlea eax, [r11+rsi]\nmov ecx, eax\nshr ecx, 1Fh\nadd ecx, eax\nsar ecx, 1\nlea r12d, [rcx+1]\nlea r13d, [rcx-1]\nmovsxd rax, ecx\nmov r9d, [rdi+rax*4]\nmov eax, r12d\ncdq\nidiv r8d\nmovsxd rdx, edx\ncmp r9d, [rdi+rdx*4]\njg short loc_1188\nlea eax, [r13+r8+0]\ncdq\nidiv r8d\nmovsxd rdx, edx\ncmp r9d, [rdi+rdx*4]\njg short loc_1188\nmov r11d, ecx\njmp short loc_11F6\nloc_11E7:\ncmp ebx, r9d\ncmovle r11d, r12d\njmp short loc_117F\nloc_11F0:\nmov r11d, 0FFFFFFFFh\nloc_11F6:\nmov eax, r11d\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int v3; // esi\n int v4; // r11d\n int v5; // ebx\n int v6; // r10d\n int v7; // ecx\n int v8; // r9d\n\n v3 = a2 - 1;\n v4 = 0;\n while ( v4 <= v3 )\n {\n v5 = *(_DWORD *)(a1 + 4LL * v4);\n v6 = *(_DWORD *)(a1 + 4LL * v3);\n if ( v5 <= v6 )\n return (unsigned int)v4;\n v7 = (v4 + v3) / 2;\n v8 = *(_DWORD *)(a1 + 4LL * v7);\n if ( v8 <= *(_DWORD *)(a1 + 4LL * ((v7 + 1) % a2)) && v8 <= *(_DWORD *)(a1 + 4LL * ((v7 - 1 + a2) % a2)) )\n return (unsigned int)((v4 + v3) / 2);\n if ( v6 < v8 )\n {\n if ( v5 <= v8 )\n v4 = v7 + 1;\n }\n else\n {\n v3 = v7 - 1;\n }\n }\n return (unsigned int)-1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n int v8;\n v3 = a2 - 1;\n v4 = 0;\n while (v4 <= v3) {\n v5 = *(uint32_t *)(a1 + 4LL * v4);\n v6 = *(uint32_t *)(a1 + 4LL * v3);\n if (v5 <= v6) return (unsigned int)v4;\n v7 = (v4 + v3) / 2;\n v8 = *(uint32_t *)(a1 + 4LL * v7);\n if (v8 <= *(uint32_t *)(a1 + 4LL * ((v7 + 1) % a2)) &&\n v8 <= *(uint32_t *)(a1 + 4LL * ((v7 - 1 + a2) % a2)))\n return (unsigned int)((v4 + v3) / 2);\n if (v6 < v8) {\n if (v5 <= v8) v4 = v7 + 1;\n } else {\n v3 = v7 - 1;\n }\n }\n return (unsigned int)-1;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n int v8;\n v3 = a2 - 1;\n v4 = 0;\n while (v4 <= v3) {\n v5 = *(uint32_t *)(a1 + 4LL * v4);\n v6 = *(uint32_t *)(a1 + 4LL * v3);\n if (v5 <= v6) return (unsigned int)v4;\n v7 = (v4 + v3) / 2;\n v8 = *(uint32_t *)(a1 + 4LL * v7);\n if (v8 <= *(uint32_t *)(a1 + 4LL * ((v7 + 1) % a2)) &&\n v8 <= *(uint32_t *)(a1 + 4LL * ((v7 - 1 + a2) % a2)))\n return (unsigned int)((v4 + v3) / 2);\n if (v6 < v8) {\n if (v5 <= v8) v4 = v7 + 1;\n } else {\n v3 = v7 - 1;\n }\n }\n return (unsigned int)-1;\n}" + }, + { + "index": 382, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int A[], int n) {\n int left = 0;\n int right = n - 1;\n while (left <= right) {\n if (A[left] <= A[right]) {\n return left;\n }\n int mid = (left + right) / 2;\n int next = (mid + 1) % n;\n int prev = (mid - 1 + n) % n;\n if (A[mid] <= A[next] && A[mid] <= A[prev]) {\n return mid;\n } else if (A[mid] <= A[right]) {\n right = mid - 1;\n } else if (A[mid] >= A[left]) {\n left = mid + 1;\n }\n }\n return -1;\n}", + "test": "int main() {\n\n int arr1[] = {8, 9, 10, 1, 2, 3, 4, 5, 6, 7};\n\n int n1 = sizeof(arr1) / sizeof(arr1[0]);\n\n assert(func0(arr1, n1) == 3);\n\n\n\n int arr2[] = {8, 9, 10, 2, 5, 6};\n\n int n2 = sizeof(arr2) / sizeof(arr2[0]);\n\n assert(func0(arr2, n2) == 3);\n\n\n\n int arr3[] = {2, 5, 6, 8, 9, 10};\n\n int n3 = sizeof(arr3) / sizeof(arr3[0]);\n\n assert(func0(arr3, n3) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\nlea -0x1(%rsi),%r8d\nxor %r14d,%r14d\npush %r13\npush %r12\nxor %r12d,%r12d\npush %rbp\npush %rbx\nlea (%rdi,%r14,4),%r13\njmp 134a \nnopl 0x0(%rax)\nmovslq %r8d,%rax\nmov 0x0(%r13),%ebp\nmov (%rdi,%rax,4),%r10d\ncmp %r10d,%ebp\njle 1355 \nlea (%r12,%r8,1),%ecx\nsar %ecx\nmovslq %ecx,%rax\nlea 0x1(%rcx),%r11d\nlea -0x1(%rcx),%ebx\nmov (%rdi,%rax,4),%r9d\nmov %r11d,%eax\ncltd\nidiv %esi\nmovslq %edx,%rdx\ncmp (%rdi,%rdx,4),%r9d\njg 1342 \nlea (%rbx,%rsi,1),%eax\ncltd\nidiv %esi\nmovslq %edx,%rdx\ncmp (%rdi,%rdx,4),%r9d\njle 1378 \ncmp %r9d,%r10d\njl 1368 \nmov %ebx,%r8d\ncmp %r8d,%r12d\njle 1300 \nmov $0xffffffff,%r12d\npop %rbx\nmov %r12d,%eax\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopl 0x0(%rax)\ncmp %r9d,%ebp\njg 12f6 \nmovslq %r11d,%r14\nmov %r14,%r12\njmp 12f6 \nnopl (%rax)\nmov %ecx,%r12d\npop %rbx\npop %rbp\nmov %r12d,%eax\npop %r12\npop %r13\npop %r14\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\nmov r8d, esi\nxor r14d, r14d\nsub esi, 1\npush r13\npush r12\npush rbp\nxor ebp, ebp\npush rbx\nloc_12B7:\nlea r13, [rdi+r14*4]\njmp short loc_1313\nloc_12C0:\nmovsxd rax, esi\nmov r12d, [r13+0]\nmov r10d, [rdi+rax*4]\ncmp r12d, r10d\njle short loc_131C\nlea eax, [rbp+rsi+0]\nmov ecx, eax\nshr ecx, 1Fh\nadd ecx, eax\nsar ecx, 1\nmovsxd rax, ecx\nlea r11d, [rcx+1]\nlea ebx, [rcx-1]\nmov r9d, [rdi+rax*4]\nmov eax, r11d\ncdq\nidiv r8d\nmovsxd rdx, edx\ncmp r9d, [rdi+rdx*4]\njg short loc_130C\nlea eax, [rbx+r8]\ncdq\nidiv r8d\nmovsxd rdx, edx\ncmp r9d, [rdi+rdx*4]\njle short loc_1340\nloc_130C:\ncmp r10d, r9d\njl short loc_1330\nmov esi, ebx\nloc_1313:\ncmp ebp, esi\njle short loc_12C0\nmov ebp, 0FFFFFFFFh\nloc_131C:\npop rbx\nmov eax, ebp\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1330:\ncmp r12d, r9d\njg short loc_12B7\nmovsxd r14, r11d\nmov rbp, r14\njmp loc_12B7\nloc_1340:\nmov ebp, ecx\npop rbx\nmov eax, ebp\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v3; // r14\n int v4; // esi\n int v5; // ebp\n int v6; // r12d\n int v7; // r10d\n int v8; // ecx\n int v9; // r9d\n\n v3 = 0LL;\n v4 = a2 - 1;\n v5 = 0;\n while ( 1 )\n {\n if ( v5 > v4 )\n return (unsigned int)-1;\n v6 = *(_DWORD *)(a1 + 4 * v3);\n v7 = *(_DWORD *)(a1 + 4LL * v4);\n if ( v6 <= v7 )\n return (unsigned int)v5;\n v8 = (v5 + v4) / 2;\n v9 = *(_DWORD *)(a1 + 4LL * v8);\n if ( v9 <= *(_DWORD *)(a1 + 4LL * ((v8 + 1) % a2)) && v9 <= *(_DWORD *)(a1 + 4LL * ((v8 - 1 + a2) % a2)) )\n break;\n if ( v7 < v9 )\n {\n if ( v6 <= v9 )\n {\n v3 = v8 + 1;\n v5 = v8 + 1;\n }\n }\n else\n {\n v4 = v8 - 1;\n }\n }\n return (unsigned int)v8;\n}", + "ida_strip_asm": "sub_12A0:\nendbr64\npush r14\nmov r8d, esi\nxor r14d, r14d\nsub esi, 1\npush r13\npush r12\npush rbp\nxor ebp, ebp\npush rbx\nloc_12B7:\nlea r13, [rdi+r14*4]\njmp short loc_1313\nloc_12C0:\nmovsxd rax, esi\nmov r12d, [r13+0]\nmov r10d, [rdi+rax*4]\ncmp r12d, r10d\njle short loc_131C\nlea eax, [rbp+rsi+0]\nmov ecx, eax\nshr ecx, 1Fh\nadd ecx, eax\nsar ecx, 1\nmovsxd rax, ecx\nlea r11d, [rcx+1]\nlea ebx, [rcx-1]\nmov r9d, [rdi+rax*4]\nmov eax, r11d\ncdq\nidiv r8d\nmovsxd rdx, edx\ncmp r9d, [rdi+rdx*4]\njg short loc_130C\nlea eax, [rbx+r8]\ncdq\nidiv r8d\nmovsxd rdx, edx\ncmp r9d, [rdi+rdx*4]\njle short loc_1340\nloc_130C:\ncmp r10d, r9d\njl short loc_1330\nmov esi, ebx\nloc_1313:\ncmp ebp, esi\njle short loc_12C0\nmov ebp, 0FFFFFFFFh\nloc_131C:\npop rbx\nmov eax, ebp\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1330:\ncmp r12d, r9d\njg short loc_12B7\nmovsxd r14, r11d\nmov rbp, r14\njmp loc_12B7\nloc_1340:\nmov ebp, ecx\npop rbx\nmov eax, ebp\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12A0(__int64 a1, int a2)\n{\n __int64 v3; // r14\n int v4; // esi\n int v5; // ebp\n int v6; // r12d\n int v7; // r10d\n int v8; // ecx\n int v9; // r9d\n\n v3 = 0LL;\n v4 = a2 - 1;\n v5 = 0;\n while ( 1 )\n {\n if ( v5 > v4 )\n return (unsigned int)-1;\n v6 = *(_DWORD *)(a1 + 4 * v3);\n v7 = *(_DWORD *)(a1 + 4LL * v4);\n if ( v6 <= v7 )\n return (unsigned int)v5;\n v8 = (v5 + v4) / 2;\n v9 = *(_DWORD *)(a1 + 4LL * v8);\n if ( v9 <= *(_DWORD *)(a1 + 4LL * ((v8 + 1) % a2)) && v9 <= *(_DWORD *)(a1 + 4LL * ((v8 - 1 + a2) % a2)) )\n break;\n if ( v7 < v9 )\n {\n if ( v6 <= v9 )\n {\n v3 = v8 + 1;\n v5 = v8 + 1;\n }\n }\n else\n {\n v4 = v8 - 1;\n }\n }\n return (unsigned int)v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12A0(long long a1, int a2) {\n long long v3;\n int v4;\n int v5;\n int v6;\n int v7;\n int v8;\n int v9;\n v3 = 0LL;\n v4 = a2 - 1;\n v5 = 0;\n while (1) {\n if (v5 > v4) return (unsigned int)-1;\n v6 = *(uint32_t *)(a1 + 4 * v3);\n v7 = *(uint32_t *)(a1 + 4LL * v4);\n if (v6 <= v7) return (unsigned int)v5;\n v8 = (v5 + v4) / 2;\n v9 = *(uint32_t *)(a1 + 4LL * v8);\n if (v9 <= *(uint32_t *)(a1 + 4LL * ((v8 + 1) % a2)) &&\n v9 <= *(uint32_t *)(a1 + 4LL * ((v8 - 1 + a2) % a2)))\n break;\n if (v7 < v9) {\n if (v6 <= v9) {\n v3 = v8 + 1;\n v5 = v8 + 1;\n }\n } else {\n v4 = v8 - 1;\n }\n }\n return (unsigned int)v8;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v3;\n int v4;\n int v5;\n int v6;\n int v7;\n int v8;\n int v9;\n v3 = 0LL;\n v4 = a2 - 1;\n v5 = 0;\n while (1) {\n if (v5 > v4) return (unsigned int)-1;\n v6 = *(uint32_t *)(a1 + 4 * v3);\n v7 = *(uint32_t *)(a1 + 4LL * v4);\n if (v6 <= v7) return (unsigned int)v5;\n v8 = (v5 + v4) / 2;\n v9 = *(uint32_t *)(a1 + 4LL * v8);\n if (v9 <= *(uint32_t *)(a1 + 4LL * ((v8 + 1) % a2)) &&\n v9 <= *(uint32_t *)(a1 + 4LL * ((v8 - 1 + a2) % a2)))\n break;\n if (v7 < v9) {\n if (v6 <= v9) {\n v3 = v8 + 1;\n v5 = v8 + 1;\n }\n } else {\n v4 = v8 - 1;\n }\n }\n return (unsigned int)v8;\n}" + }, + { + "index": 382, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int A[], int n) {\n int left = 0;\n int right = n - 1;\n while (left <= right) {\n if (A[left] <= A[right]) {\n return left;\n }\n int mid = (left + right) / 2;\n int next = (mid + 1) % n;\n int prev = (mid - 1 + n) % n;\n if (A[mid] <= A[next] && A[mid] <= A[prev]) {\n return mid;\n } else if (A[mid] <= A[right]) {\n right = mid - 1;\n } else if (A[mid] >= A[left]) {\n left = mid + 1;\n }\n }\n return -1;\n}", + "test": "int main() {\n\n int arr1[] = {8, 9, 10, 1, 2, 3, 4, 5, 6, 7};\n\n int n1 = sizeof(arr1) / sizeof(arr1[0]);\n\n assert(func0(arr1, n1) == 3);\n\n\n\n int arr2[] = {8, 9, 10, 2, 5, 6};\n\n int n2 = sizeof(arr2) / sizeof(arr2[0]);\n\n assert(func0(arr2, n2) == 3);\n\n\n\n int arr3[] = {2, 5, 6, 8, 9, 10};\n\n int n3 = sizeof(arr3) / sizeof(arr3[0]);\n\n assert(func0(arr3, n3) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\nlea -0x1(%rsi),%r8d\nxor %r14d,%r14d\npush %r13\npush %r12\nxor %r12d,%r12d\npush %rbp\npush %rbx\nlea (%rdi,%r14,4),%r13\njmp 130a \nnopl 0x0(%rax)\nmovslq %r8d,%rax\nmov 0x0(%r13),%ebp\nmov (%rdi,%rax,4),%r10d\ncmp %r10d,%ebp\njle 1315 \nlea (%r12,%r8,1),%ecx\nsar %ecx\nmovslq %ecx,%rax\nlea 0x1(%rcx),%r11d\nlea -0x1(%rcx),%ebx\nmov (%rdi,%rax,4),%r9d\nmov %r11d,%eax\ncltd\nidiv %esi\nmovslq %edx,%rdx\ncmp (%rdi,%rdx,4),%r9d\njg 1302 \nlea (%rbx,%rsi,1),%eax\ncltd\nidiv %esi\nmovslq %edx,%rdx\ncmp (%rdi,%rdx,4),%r9d\njle 1338 \ncmp %r9d,%r10d\njl 1328 \nmov %ebx,%r8d\ncmp %r8d,%r12d\njle 12c0 \nmov $0xffffffff,%r12d\npop %rbx\nmov %r12d,%eax\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopl 0x0(%rax)\ncmp %r9d,%ebp\njg 12b6 \nmovslq %r11d,%r14\nmov %r14,%r12\njmp 12b6 \nnopl (%rax)\nmov %ecx,%r12d\npop %rbx\npop %rbp\nmov %r12d,%eax\npop %r12\npop %r13\npop %r14\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\nmov r8d, esi\nxor r14d, r14d\nsub esi, 1\npush r13\npush r12\npush rbp\nxor ebp, ebp\npush rbx\nloc_12B7:\nlea r13, [rdi+r14*4]\njmp short loc_1313\nloc_12C0:\nmovsxd rax, esi\nmov r12d, [r13+0]\nmov r10d, [rdi+rax*4]\ncmp r12d, r10d\njle short loc_131C\nlea eax, [rbp+rsi+0]\nmov ecx, eax\nshr ecx, 1Fh\nadd ecx, eax\nsar ecx, 1\nmovsxd rax, ecx\nlea r11d, [rcx+1]\nlea ebx, [rcx-1]\nmov r9d, [rdi+rax*4]\nmov eax, r11d\ncdq\nidiv r8d\nmovsxd rdx, edx\ncmp r9d, [rdi+rdx*4]\njg short loc_130C\nlea eax, [rbx+r8]\ncdq\nidiv r8d\nmovsxd rdx, edx\ncmp r9d, [rdi+rdx*4]\njle short loc_1340\nloc_130C:\ncmp r10d, r9d\njl short loc_1330\nmov esi, ebx\nloc_1313:\ncmp ebp, esi\njle short loc_12C0\nmov ebp, 0FFFFFFFFh\nloc_131C:\npop rbx\nmov eax, ebp\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1330:\ncmp r12d, r9d\njg short loc_12B7\nmovsxd r14, r11d\nmov rbp, r14\njmp loc_12B7\nloc_1340:\nmov ebp, ecx\npop rbx\nmov eax, ebp\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v3; // r14\n int v4; // esi\n int v5; // ebp\n int v6; // r12d\n int v7; // r10d\n int v8; // ecx\n int v9; // r9d\n\n v3 = 0LL;\n v4 = a2 - 1;\n v5 = 0;\n while ( 1 )\n {\n if ( v5 > v4 )\n return (unsigned int)-1;\n v6 = *(_DWORD *)(a1 + 4 * v3);\n v7 = *(_DWORD *)(a1 + 4LL * v4);\n if ( v6 <= v7 )\n return (unsigned int)v5;\n v8 = (v5 + v4) / 2;\n v9 = *(_DWORD *)(a1 + 4LL * v8);\n if ( v9 <= *(_DWORD *)(a1 + 4LL * ((v8 + 1) % a2)) && v9 <= *(_DWORD *)(a1 + 4LL * ((v8 - 1 + a2) % a2)) )\n break;\n if ( v7 < v9 )\n {\n if ( v6 <= v9 )\n {\n v3 = v8 + 1;\n v5 = v8 + 1;\n }\n }\n else\n {\n v4 = v8 - 1;\n }\n }\n return (unsigned int)v8;\n}", + "ida_strip_asm": "sub_12A0:\nendbr64\npush r14\nmov r8d, esi\nxor r14d, r14d\nsub esi, 1\npush r13\npush r12\npush rbp\nxor ebp, ebp\npush rbx\nloc_12B7:\nlea r13, [rdi+r14*4]\njmp short loc_1313\nloc_12C0:\nmovsxd rax, esi\nmov r12d, [r13+0]\nmov r10d, [rdi+rax*4]\ncmp r12d, r10d\njle short loc_131C\nlea eax, [rbp+rsi+0]\nmov ecx, eax\nshr ecx, 1Fh\nadd ecx, eax\nsar ecx, 1\nmovsxd rax, ecx\nlea r11d, [rcx+1]\nlea ebx, [rcx-1]\nmov r9d, [rdi+rax*4]\nmov eax, r11d\ncdq\nidiv r8d\nmovsxd rdx, edx\ncmp r9d, [rdi+rdx*4]\njg short loc_130C\nlea eax, [rbx+r8]\ncdq\nidiv r8d\nmovsxd rdx, edx\ncmp r9d, [rdi+rdx*4]\njle short loc_1340\nloc_130C:\ncmp r10d, r9d\njl short loc_1330\nmov esi, ebx\nloc_1313:\ncmp ebp, esi\njle short loc_12C0\nmov ebp, 0FFFFFFFFh\nloc_131C:\npop rbx\nmov eax, ebp\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1330:\ncmp r12d, r9d\njg short loc_12B7\nmovsxd r14, r11d\nmov rbp, r14\njmp loc_12B7\nloc_1340:\nmov ebp, ecx\npop rbx\nmov eax, ebp\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12A0(__int64 a1, int a2)\n{\n __int64 v3; // r14\n int v4; // esi\n int v5; // ebp\n int v6; // r12d\n int v7; // r10d\n int v8; // ecx\n int v9; // r9d\n\n v3 = 0LL;\n v4 = a2 - 1;\n v5 = 0;\n while ( 1 )\n {\n if ( v5 > v4 )\n return (unsigned int)-1;\n v6 = *(_DWORD *)(a1 + 4 * v3);\n v7 = *(_DWORD *)(a1 + 4LL * v4);\n if ( v6 <= v7 )\n return (unsigned int)v5;\n v8 = (v5 + v4) / 2;\n v9 = *(_DWORD *)(a1 + 4LL * v8);\n if ( v9 <= *(_DWORD *)(a1 + 4LL * ((v8 + 1) % a2)) && v9 <= *(_DWORD *)(a1 + 4LL * ((v8 - 1 + a2) % a2)) )\n break;\n if ( v7 < v9 )\n {\n if ( v6 <= v9 )\n {\n v3 = v8 + 1;\n v5 = v8 + 1;\n }\n }\n else\n {\n v4 = v8 - 1;\n }\n }\n return (unsigned int)v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12A0(long long a1, int a2) {\n long long v3;\n int v4;\n int v5;\n int v6;\n int v7;\n int v8;\n int v9;\n v3 = 0LL;\n v4 = a2 - 1;\n v5 = 0;\n while (1) {\n if (v5 > v4) return (unsigned int)-1;\n v6 = *(uint32_t *)(a1 + 4 * v3);\n v7 = *(uint32_t *)(a1 + 4LL * v4);\n if (v6 <= v7) return (unsigned int)v5;\n v8 = (v5 + v4) / 2;\n v9 = *(uint32_t *)(a1 + 4LL * v8);\n if (v9 <= *(uint32_t *)(a1 + 4LL * ((v8 + 1) % a2)) &&\n v9 <= *(uint32_t *)(a1 + 4LL * ((v8 - 1 + a2) % a2)))\n break;\n if (v7 < v9) {\n if (v6 <= v9) {\n v3 = v8 + 1;\n v5 = v8 + 1;\n }\n } else {\n v4 = v8 - 1;\n }\n }\n return (unsigned int)v8;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v3;\n int v4;\n int v5;\n int v6;\n int v7;\n int v8;\n int v9;\n v3 = 0LL;\n v4 = a2 - 1;\n v5 = 0;\n while (1) {\n if (v5 > v4) return (unsigned int)-1;\n v6 = *(uint32_t *)(a1 + 4 * v3);\n v7 = *(uint32_t *)(a1 + 4LL * v4);\n if (v6 <= v7) return (unsigned int)v5;\n v8 = (v5 + v4) / 2;\n v9 = *(uint32_t *)(a1 + 4LL * v8);\n if (v9 <= *(uint32_t *)(a1 + 4LL * ((v8 + 1) % a2)) &&\n v9 <= *(uint32_t *)(a1 + 4LL * ((v8 - 1 + a2) % a2)))\n break;\n if (v7 < v9) {\n if (v6 <= v9) {\n v3 = v8 + 1;\n v5 = v8 + 1;\n }\n } else {\n v4 = v8 - 1;\n }\n }\n return (unsigned int)v8;\n}" + }, + { + "index": 383, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int res = 0, count = 0, temp = n;\n while (temp > 0) {\n if (count % 2 == 0) {\n res = res | (1 << count);\n }\n count = count + 1;\n temp >>= 1;\n }\n return n ^ res;\n}", + "test": "int main() {\n\n assert(func0(10) == 15);\n\n assert(func0(20) == 1);\n\n assert(func0(30) == 11);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\nmov -0x14(%rbp),%eax\nmov %eax,-0x4(%rbp)\njmp 118c \nmov -0x8(%rbp),%eax\nand $0x1,%eax\ntest %eax,%eax\njne 1185 \nmov -0x8(%rbp),%eax\nmov $0x1,%edx\nmov %eax,%ecx\nshl %cl,%edx\nmov %edx,%eax\nor %eax,-0xc(%rbp)\naddl $0x1,-0x8(%rbp)\nsarl -0x4(%rbp)\ncmpl $0x0,-0x4(%rbp)\njg 116a \nmov -0x14(%rbp),%eax\nxor -0xc(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\nmov eax, [rbp+var_14]\nmov [rbp+var_4], eax\njmp short loc_118C\nloc_116A:\nmov eax, [rbp+var_8]\nand eax, 1\ntest eax, eax\njnz short loc_1185\nmov eax, [rbp+var_8]\nmov edx, 1\nmov ecx, eax\nshl edx, cl\nmov eax, edx\nor [rbp+var_C], eax\nloc_1185:\nadd [rbp+var_8], 1\nsar [rbp+var_4], 1\nloc_118C:\ncmp [rbp+var_4], 0\njg short loc_116A\nmov eax, [rbp+var_14]\nxor eax, [rbp+var_C]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v2; // [rsp+8h] [rbp-Ch]\n char v3; // [rsp+Ch] [rbp-8h]\n int i; // [rsp+10h] [rbp-4h]\n\n v2 = 0;\n v3 = 0;\n for ( i = a1; i > 0; i >>= 1 )\n {\n if ( (v3 & 1) == 0 )\n v2 |= 1 << v3;\n ++v3;\n }\n return v2 ^ (unsigned int)a1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\nmov eax, [rbp+var_14]\nmov [rbp+var_4], eax\njmp short loc_118C\nloc_116A:\nmov eax, [rbp+var_8]\nand eax, 1\ntest eax, eax\njnz short loc_1185\nmov eax, [rbp+var_8]\nmov edx, 1\nmov ecx, eax\nshl edx, cl\nmov eax, edx\nor [rbp+var_C], eax\nloc_1185:\nadd [rbp+var_8], 1\nsar [rbp+var_4], 1\nloc_118C:\ncmp [rbp+var_4], 0\njg short loc_116A\nmov eax, [rbp+var_14]\nxor eax, [rbp+var_C]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v2; // [rsp+8h] [rbp-Ch]\n char v3; // [rsp+Ch] [rbp-8h]\n int i; // [rsp+10h] [rbp-4h]\n\n v2 = 0;\n v3 = 0;\n for ( i = a1; i > 0; i >>= 1 )\n {\n if ( (v3 & 1) == 0 )\n v2 |= 1 << v3;\n ++v3;\n }\n return v2 ^ (unsigned int)a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v2;\n char v3;\n int i;\n v2 = 0;\n v3 = 0;\n for (i = a1; i > 0; i >>= 1) {\n if ((v3 & 1) == 0) v2 |= 1 << v3;\n ++v3;\n }\n return v2 ^ (unsigned int)a1;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v2;\n char v3;\n int i;\n v2 = 0;\n v3 = 0;\n for (i = a1; i > 0; i >>= 1) {\n if ((v3 & 1) == 0) v2 |= 1 << v3;\n ++v3;\n }\n return v2 ^ (unsigned int)a1;\n}" + }, + { + "index": 383, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int res = 0, count = 0, temp = n;\n while (temp > 0) {\n if (count % 2 == 0) {\n res = res | (1 << count);\n }\n count = count + 1;\n temp >>= 1;\n }\n return n ^ res;\n}", + "test": "int main() {\n\n assert(func0(10) == 15);\n\n assert(func0(20) == 1);\n\n assert(func0(30) == 11);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\njle 117c \nmov %edi,%edx\nmov $0x0,%ecx\nmov $0x0,%eax\nmov $0x1,%r8d\njmp 116e \nadd $0x1,%ecx\nsar %edx\ntest %edx,%edx\njle 1181 \ntest $0x1,%cl\njne 1165 \nmov %r8d,%esi\nshl %cl,%esi\nor %esi,%eax\njmp 1165 \nmov $0x0,%eax\nxor %edi,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov eax, edi\ntest edi, edi\njle short loc_117F\nmov edx, edi\nmov ecx, 0\nmov esi, 0\nmov edi, 1\njmp short loc_116F\nloc_1166:\nadd ecx, 1\nsar edx, 1\ntest edx, edx\njle short loc_1184\nloc_116F:\ntest cl, 1\njnz short loc_1166\nmov r8d, edi\nshl r8d, cl\nor esi, r8d\njmp short loc_1166\nloc_117F:\nmov esi, 0\nloc_1184:\nxor eax, esi\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // edx\n char v2; // cl\n int v3; // esi\n\n if ( a1 <= 0 )\n {\n v3 = 0;\n }\n else\n {\n v1 = a1;\n v2 = 0;\n v3 = 0;\n do\n {\n if ( (v2 & 1) == 0 )\n v3 |= 1 << v2;\n ++v2;\n v1 >>= 1;\n }\n while ( v1 > 0 );\n }\n return v3 ^ (unsigned int)a1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmov eax, edi\ntest edi, edi\njle short loc_117F\nmov edx, edi\nmov ecx, 0\nmov esi, 0\nmov edi, 1\njmp short loc_116F\nloc_1166:\nadd ecx, 1\nsar edx, 1\ntest edx, edx\njle short loc_1184\nloc_116F:\ntest cl, 1\njnz short loc_1166\nmov r8d, edi\nshl r8d, cl\nor esi, r8d\njmp short loc_1166\nloc_117F:\nmov esi, 0\nloc_1184:\nxor eax, esi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v1; // edx\n char v2; // cl\n int v3; // esi\n\n if ( a1 <= 0 )\n {\n v3 = 0;\n }\n else\n {\n v1 = a1;\n v2 = 0;\n v3 = 0;\n do\n {\n if ( (v2 & 1) == 0 )\n v3 |= 1 << v2;\n ++v2;\n v1 >>= 1;\n }\n while ( v1 > 0 );\n }\n return v3 ^ (unsigned int)a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v1;\n char v2;\n int v3;\n if (a1 <= 0) {\n v3 = 0;\n } else {\n v1 = a1;\n v2 = 0;\n v3 = 0;\n do {\n if ((v2 & 1) == 0) v3 |= 1 << v2;\n ++v2;\n v1 >>= 1;\n } while (v1 > 0);\n }\n return v3 ^ (unsigned int)a1;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n char v2;\n int v3;\n if (a1 <= 0) {\n v3 = 0;\n } else {\n v1 = a1;\n v2 = 0;\n v3 = 0;\n do {\n if ((v2 & 1) == 0) v3 |= 1 << v2;\n ++v2;\n v1 >>= 1;\n } while (v1 > 0);\n }\n return v3 ^ (unsigned int)a1;\n}" + }, + { + "index": 383, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int res = 0, count = 0, temp = n;\n while (temp > 0) {\n if (count % 2 == 0) {\n res = res | (1 << count);\n }\n count = count + 1;\n temp >>= 1;\n }\n return n ^ res;\n}", + "test": "int main() {\n\n assert(func0(10) == 15);\n\n assert(func0(20) == 1);\n\n assert(func0(30) == 11);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\njle 1170 \nmov %edi,%edx\nxor %ecx,%ecx\nxor %eax,%eax\nmov $0x1,%r8d\nnopl 0x0(%rax)\ntest $0x1,%cl\njne 1164 \nmov %r8d,%esi\nshl %cl,%esi\nor %esi,%eax\nadd $0x1,%ecx\nsar %edx\njne 1158 \nxor %edi,%eax\nretq\nxchg %ax,%ax\nmov %edi,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njle short loc_1228\nmov edx, edi\nxor ecx, ecx\nxor esi, esi\nmov eax, 1\nnop dword ptr [rax+rax+00h]\nloc_1208:\ntest cl, 1\njnz short loc_1216\nmov r8d, eax\nshl r8d, cl\nor esi, r8d\nloc_1216:\nadd ecx, 1\nsar edx, 1\njnz short loc_1208\nmov eax, edi\nxor eax, esi\nretn\nloc_1228:\nmov eax, edi\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // edx\n char v2; // cl\n int v3; // esi\n\n if ( a1 <= 0 )\n return (unsigned int)a1;\n v1 = a1;\n v2 = 0;\n v3 = 0;\n do\n {\n if ( (v2 & 1) == 0 )\n v3 |= 1 << v2;\n ++v2;\n v1 >>= 1;\n }\n while ( v1 );\n return v3 ^ (unsigned int)a1;\n}", + "ida_strip_asm": "sub_11F0:\nendbr64\ntest edi, edi\njle short loc_1228\nmov edx, edi\nxor ecx, ecx\nxor esi, esi\nmov eax, 1\nnop dword ptr [rax+rax+00h]\nloc_1208:\ntest cl, 1\njnz short loc_1216\nmov r8d, eax\nshl r8d, cl\nor esi, r8d\nloc_1216:\nadd ecx, 1\nsar edx, 1\njnz short loc_1208\nmov eax, edi\nxor eax, esi\nretn\nloc_1228:\nmov eax, edi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11F0(int a1)\n{\n int v1; // edx\n char v2; // cl\n int v3; // esi\n\n if ( a1 <= 0 )\n return (unsigned int)a1;\n v1 = a1;\n v2 = 0;\n v3 = 0;\n do\n {\n if ( (v2 & 1) == 0 )\n v3 |= 1 << v2;\n ++v2;\n v1 >>= 1;\n }\n while ( v1 );\n return v3 ^ (unsigned int)a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11F0(int a1) {\n int v1;\n char v2;\n int v3;\n if (a1 <= 0) return (unsigned int)a1;\n v1 = a1;\n v2 = 0;\n v3 = 0;\n do {\n if ((v2 & 1) == 0) v3 |= 1 << v2;\n ++v2;\n v1 >>= 1;\n } while (v1);\n return v3 ^ (unsigned int)a1;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n char v2;\n int v3;\n if (a1 <= 0) return (unsigned int)a1;\n v1 = a1;\n v2 = 0;\n v3 = 0;\n do {\n if ((v2 & 1) == 0) v3 |= 1 << v2;\n ++v2;\n v1 >>= 1;\n } while (v1);\n return v3 ^ (unsigned int)a1;\n}" + }, + { + "index": 384, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n, int arr[]) {\n int mn = arr[0];\n int freq = 1;\n for (int i = 1; i < n; i++) {\n if (arr[i] < mn) {\n mn = arr[i];\n freq = 1;\n } else if (arr[i] == mn) {\n freq++;\n }\n }\n return freq;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4, 3};\n\n int arr2[] = {3, 1, 2, 5, 6, 2, 3};\n\n int arr3[] = {3, 3, 6, 3, 7, 4, 9};\n\n\n\n assert(func0(5, arr1) == 1);\n\n assert(func0(7, arr2) == 1);\n\n assert(func0(7, arr3) == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %rsi,-0x20(%rbp)\nmov -0x20(%rbp),%rax\nmov (%rax),%eax\nmov %eax,-0xc(%rbp)\nmovl $0x1,-0x8(%rbp)\nmovl $0x1,-0x4(%rbp)\njmp 11f1 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0xc(%rbp)\njle 11ce \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0xc(%rbp)\nmovl $0x1,-0x8(%rbp)\njmp 11ed \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0xc(%rbp)\njne 11ed \naddl $0x1,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x14(%rbp),%eax\njl 1191 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_20], rsi\nmov rax, [rbp+var_20]\nmov eax, [rax]\nmov [rbp+var_C], eax\nmov [rbp+var_8], 1\nmov [rbp+var_4], 1\njmp short loc_11F1\nloc_1191:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_C], eax\njle short loc_11CE\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nmov [rbp+var_8], 1\njmp short loc_11ED\nloc_11CE:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_C], eax\njnz short loc_11ED\nadd [rbp+var_8], 1\nloc_11ED:\nadd [rbp+var_4], 1\nloc_11F1:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_14]\njl short loc_1191\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int *a2)\n{\n int v3; // [rsp+14h] [rbp-Ch]\n unsigned int v4; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v3 = *a2;\n v4 = 1;\n for ( i = 1; i < a1; ++i )\n {\n if ( v3 <= a2[i] )\n {\n if ( v3 == a2[i] )\n ++v4;\n }\n else\n {\n v3 = a2[i];\n v4 = 1;\n }\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_20], rsi\nmov rax, [rbp+var_20]\nmov eax, [rax]\nmov [rbp+var_C], eax\nmov [rbp+var_8], 1\nmov [rbp+var_4], 1\njmp short loc_11F1\nloc_1191:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_C], eax\njle short loc_11CE\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nmov [rbp+var_8], 1\njmp short loc_11ED\nloc_11CE:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_C], eax\njnz short loc_11ED\nadd [rbp+var_8], 1\nloc_11ED:\nadd [rbp+var_4], 1\nloc_11F1:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_14]\njl short loc_1191\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1, int *a2)\n{\n int v3; // [rsp+14h] [rbp-Ch]\n unsigned int v4; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v3 = *a2;\n v4 = 1;\n for ( i = 1; i < a1; ++i )\n {\n if ( v3 <= a2[i] )\n {\n if ( v3 == a2[i] )\n ++v4;\n }\n else\n {\n v3 = a2[i];\n v4 = 1;\n }\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1, int *a2) {\n int v3;\n unsigned int v4;\n int i;\n v3 = *a2;\n v4 = 1;\n for (i = 1; i < a1; ++i) {\n if (v3 <= a2[i]) {\n if (v3 == a2[i]) ++v4;\n } else {\n v3 = a2[i];\n v4 = 1;\n }\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(int a1, int *a2) {\n int v3;\n unsigned int v4;\n int i;\n v3 = *a2;\n v4 = 1;\n for (i = 1; i < a1; ++i) {\n if (v3 <= a2[i]) {\n if (v3 == a2[i]) ++v4;\n } else {\n v3 = a2[i];\n v4 = 1;\n }\n }\n return v4;\n}" + }, + { + "index": 384, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n, int arr[]) {\n int mn = arr[0];\n int freq = 1;\n for (int i = 1; i < n; i++) {\n if (arr[i] < mn) {\n mn = arr[i];\n freq = 1;\n } else if (arr[i] == mn) {\n freq++;\n }\n }\n return freq;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4, 3};\n\n int arr2[] = {3, 1, 2, 5, 6, 2, 3};\n\n int arr3[] = {3, 3, 6, 3, 7, 4, 9};\n\n\n\n assert(func0(5, arr1) == 1);\n\n assert(func0(7, arr2) == 1);\n\n assert(func0(7, arr3) == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov (%rsi),%ecx\ncmp $0x1,%edi\njle 11a7 \nlea 0x4(%rsi),%rax\nlea -0x2(%rdi),%edx\nlea 0x8(%rsi,%rdx,4),%rdi\nmov $0x1,%esi\njmp 1197 \nmov %edx,%ecx\nmov $0x1,%esi\nadd $0x4,%rax\ncmp %rdi,%rax\nje 11ac \nmov (%rax),%edx\ncmp %ecx,%edx\njl 1187 \nsete %dl\nmovzbl %dl,%edx\nadd %edx,%esi\njmp 118e \nmov $0x1,%esi\nmov %esi,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov ecx, [rsi]\ncmp edi, 1\njle short loc_11A7\nlea rax, [rsi+4]\nlea edx, [rdi-2]\nlea rdi, [rsi+rdx*4+8]\nmov esi, 1\njmp short loc_1197\nloc_1187:\nmov ecx, edx\nmov esi, 1\nloc_118E:\nadd rax, 4\ncmp rax, rdi\njz short loc_11AC\nloc_1197:\nmov edx, [rax]\ncmp edx, ecx\njl short loc_1187\nsetz dl\nmovzx edx, dl\nadd esi, edx\njmp short loc_118E\nloc_11A7:\nmov esi, 1\nloc_11AC:\nmov eax, esi\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int *a2)\n{\n int v2; // ecx\n int *v3; // rax\n __int64 v4; // rdi\n unsigned int v5; // esi\n\n v2 = *a2;\n if ( a1 <= 1 )\n {\n return 1;\n }\n else\n {\n v3 = a2 + 1;\n v4 = (__int64)&a2[a1 - 2 + 2];\n v5 = 1;\n do\n {\n if ( *v3 < v2 )\n {\n v2 = *v3;\n v5 = 1;\n }\n else\n {\n v5 += *v3 == v2;\n }\n ++v3;\n }\n while ( v3 != (int *)v4 );\n }\n return v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov ecx, [rsi]\ncmp edi, 1\njle short loc_11A7\nlea rax, [rsi+4]\nlea edx, [rdi-2]\nlea rdi, [rsi+rdx*4+8]\nmov esi, 1\njmp short loc_1197\nloc_1187:\nmov ecx, edx\nmov esi, 1\nloc_118E:\nadd rax, 4\ncmp rax, rdi\njz short loc_11AC\nloc_1197:\nmov edx, [rax]\ncmp edx, ecx\njl short loc_1187\nsetz dl\nmovzx edx, dl\nadd esi, edx\njmp short loc_118E\nloc_11A7:\nmov esi, 1\nloc_11AC:\nmov eax, esi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1, int *a2)\n{\n int v2; // ecx\n int *v3; // rax\n __int64 v4; // rdi\n unsigned int v5; // esi\n\n v2 = *a2;\n if ( a1 <= 1 )\n {\n return 1;\n }\n else\n {\n v3 = a2 + 1;\n v4 = (__int64)&a2[a1 - 2 + 2];\n v5 = 1;\n do\n {\n if ( *v3 < v2 )\n {\n v2 = *v3;\n v5 = 1;\n }\n else\n {\n v5 += *v3 == v2;\n }\n ++v3;\n }\n while ( v3 != (int *)v4 );\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1, int *a2) {\n int v2;\n int *v3;\n long long v4;\n unsigned int v5;\n v2 = *a2;\n if (a1 <= 1) {\n return 1;\n } else {\n v3 = a2 + 1;\n v4 = (long long)&a2[a1 - 2 + 2];\n v5 = 1;\n do {\n if (*v3 < v2) {\n v2 = *v3;\n v5 = 1;\n } else {\n v5 += *v3 == v2;\n }\n ++v3;\n } while (v3 != (int *)v4);\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(int a1, int *a2) {\n int v2;\n int *v3;\n long long v4;\n unsigned int v5;\n v2 = *a2;\n if (a1 <= 1) {\n return 1;\n } else {\n v3 = a2 + 1;\n v4 = (long long)&a2[a1 - 2 + 2];\n v5 = 1;\n do {\n if (*v3 < v2) {\n v2 = *v3;\n v5 = 1;\n } else {\n v5 += *v3 == v2;\n }\n ++v3;\n } while (v3 != (int *)v4);\n }\n return v5;\n}" + }, + { + "index": 384, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n, int arr[]) {\n int mn = arr[0];\n int freq = 1;\n for (int i = 1; i < n; i++) {\n if (arr[i] < mn) {\n mn = arr[i];\n freq = 1;\n } else if (arr[i] == mn) {\n freq++;\n }\n }\n return freq;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4, 3};\n\n int arr2[] = {3, 1, 2, 5, 6, 2, 3};\n\n int arr3[] = {3, 3, 6, 3, 7, 4, 9};\n\n\n\n assert(func0(5, arr1) == 1);\n\n assert(func0(7, arr2) == 1);\n\n assert(func0(7, arr3) == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov (%rsi),%ecx\ncmp $0x1,%edi\njle 13c0 \nlea -0x2(%rdi),%edx\nlea 0x4(%rsi),%rax\nmov $0x1,%r8d\nlea 0x8(%rsi,%rdx,4),%rsi\njmp 13a2 \nsete %dl\nadd $0x4,%rax\nmovzbl %dl,%edx\nadd %edx,%r8d\ncmp %rsi,%rax\nje 13b9 \nmov (%rax),%edx\ncmp %ecx,%edx\njge 1390 \nadd $0x4,%rax\nmov %edx,%ecx\nmov $0x1,%r8d\ncmp %rsi,%rax\njne 13a2 \nmov %r8d,%eax\nretq\nnopl (%rax)\nmov $0x1,%r8d\nmov %r8d,%eax\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmov r8d, [rsi]\ncmp edi, 1\njle short loc_12F0\nlea edx, [rdi-2]\nlea rax, [rsi+4]\nmov ecx, 1\nlea rsi, [rsi+rdx*4+8]\njmp short loc_12D1\nloc_12C0:\nsetz dl\nadd rax, 4\nmovzx edx, dl\nadd ecx, edx\ncmp rsi, rax\njz short loc_12E9\nloc_12D1:\nmov edx, [rax]\ncmp r8d, edx\njle short loc_12C0\nadd rax, 4\nmov r8d, edx\nmov ecx, 1\ncmp rsi, rax\njnz short loc_12D1\nloc_12E9:\nmov eax, ecx\nretn\nloc_12F0:\nmov ecx, 1\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int *a2)\n{\n int v2; // r8d\n int *v3; // rax\n unsigned int v4; // ecx\n __int64 v5; // rsi\n int v6; // edx\n bool v7; // zf\n\n v2 = *a2;\n if ( a1 <= 1 )\n return 1LL;\n v3 = a2 + 1;\n v4 = 1;\n v5 = (__int64)&a2[a1 - 2 + 2];\n do\n {\n while ( 1 )\n {\n v6 = *v3;\n v7 = v2 == *v3;\n if ( v2 > *v3 )\n break;\n ++v3;\n v4 += v7;\n if ( (int *)v5 == v3 )\n return v4;\n }\n ++v3;\n v2 = v6;\n v4 = 1;\n }\n while ( (int *)v5 != v3 );\n return v4;\n}", + "ida_strip_asm": "sub_12A0:\nendbr64\nmov r8d, [rsi]\ncmp edi, 1\njle short loc_12F0\nlea edx, [rdi-2]\nlea rax, [rsi+4]\nmov ecx, 1\nlea rsi, [rsi+rdx*4+8]\njmp short loc_12D1\nloc_12C0:\nsetz dl\nadd rax, 4\nmovzx edx, dl\nadd ecx, edx\ncmp rsi, rax\njz short loc_12E9\nloc_12D1:\nmov edx, [rax]\ncmp r8d, edx\njle short loc_12C0\nadd rax, 4\nmov r8d, edx\nmov ecx, 1\ncmp rsi, rax\njnz short loc_12D1\nloc_12E9:\nmov eax, ecx\nretn\nloc_12F0:\nmov ecx, 1\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12A0(int a1, int *a2)\n{\n int v2; // r8d\n int *v3; // rax\n unsigned int v4; // ecx\n __int64 v5; // rsi\n int v6; // edx\n bool v7; // zf\n\n v2 = *a2;\n if ( a1 <= 1 )\n return 1LL;\n v3 = a2 + 1;\n v4 = 1;\n v5 = (__int64)&a2[a1 - 2 + 2];\n do\n {\n while ( 1 )\n {\n v6 = *v3;\n v7 = v2 == *v3;\n if ( v2 > *v3 )\n break;\n ++v3;\n v4 += v7;\n if ( (int *)v5 == v3 )\n return v4;\n }\n ++v3;\n v2 = v6;\n v4 = 1;\n }\n while ( (int *)v5 != v3 );\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12A0(int a1, int *a2) {\n int v2;\n int *v3;\n unsigned int v4;\n long long v5;\n int v6;\n bool v7;\n v2 = *a2;\n if (a1 <= 1) return 1LL;\n v3 = a2 + 1;\n v4 = 1;\n v5 = (long long)&a2[a1 - 2 + 2];\n do {\n while (1) {\n v6 = *v3;\n v7 = v2 == *v3;\n if (v2 > *v3) break;\n ++v3;\n v4 += v7;\n if ((int *)v5 == v3) return v4;\n }\n ++v3;\n v2 = v6;\n v4 = 1;\n } while ((int *)v5 != v3);\n return v4;\n}", + "ida_pseudo_norm": "long long func0(int a1, int *a2) {\n int v2;\n int *v3;\n unsigned int v4;\n long long v5;\n int v6;\n bool v7;\n v2 = *a2;\n if (a1 <= 1) return 1LL;\n v3 = a2 + 1;\n v4 = 1;\n v5 = (long long)&a2[a1 - 2 + 2];\n do {\n while (1) {\n v6 = *v3;\n v7 = v2 == *v3;\n if (v2 > *v3) break;\n ++v3;\n v4 += v7;\n if ((int *)v5 == v3) return v4;\n }\n ++v3;\n v2 = v6;\n v4 = 1;\n } while ((int *)v5 != v3);\n return v4;\n}" + }, + { + "index": 385, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int n) {\n if (n == 0) return 3;\n if (n == 1) return 0;\n if (n == 2) return 2;\n return func0(n - 2) + func0(n - 3);\n}", + "test": "int main() {\n\n assert(func0(9) == 12);\n\n assert(func0(4) == 2);\n\n assert(func0(6) == 5);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x18,%rsp\nmov %edi,-0x14(%rbp)\ncmpl $0x0,-0x14(%rbp)\njne 1166 \nmov $0x3,%eax\njmp 119e \ncmpl $0x1,-0x14(%rbp)\njne 1173 \nmov $0x0,%eax\njmp 119e \ncmpl $0x2,-0x14(%rbp)\njne 1180 \nmov $0x2,%eax\njmp 119e \nmov -0x14(%rbp),%eax\nsub $0x2,%eax\nmov %eax,%edi\ncallq 1149 \nmov %eax,%ebx\nmov -0x14(%rbp),%eax\nsub $0x3,%eax\nmov %eax,%edi\ncallq 1149 \nadd %ebx,%eax\nadd $0x18,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 18h\nmov [rbp+var_14], edi\ncmp [rbp+var_14], 0\njnz short loc_1166\nmov eax, 3\njmp short loc_119E\nloc_1166:\ncmp [rbp+var_14], 1\njnz short loc_1173\nmov eax, 0\njmp short loc_119E\nloc_1173:\ncmp [rbp+var_14], 2\njnz short loc_1180\nmov eax, 2\njmp short loc_119E\nloc_1180:\nmov eax, [rbp+var_14]\nsub eax, 2\nmov edi, eax\ncall func0\nmov ebx, eax\nmov eax, [rbp+var_14]\nsub eax, 3\nmov edi, eax\ncall func0\nadd eax, ebx\nloc_119E:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v2; // ebx\n\n switch ( a1 )\n {\n case 0:\n return 3LL;\n case 1:\n return 0LL;\n case 2:\n return 2LL;\n }\n v2 = func0((unsigned int)(a1 - 2));\n return v2 + (unsigned int)func0((unsigned int)(a1 - 3));\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 18h\nmov [rbp+var_14], edi\ncmp [rbp+var_14], 0\njnz short loc_1166\nmov eax, 3\njmp short loc_119E\nloc_1166:\ncmp [rbp+var_14], 1\njnz short loc_1173\nmov eax, 0\njmp short loc_119E\nloc_1173:\ncmp [rbp+var_14], 2\njnz short loc_1180\nmov eax, 2\njmp short loc_119E\nloc_1180:\nmov eax, [rbp+var_14]\nsub eax, 2\nmov edi, eax\ncall sub_1149\nmov ebx, eax\nmov eax, [rbp+var_14]\nsub eax, 3\nmov edi, eax\ncall sub_1149\nadd eax, ebx\nloc_119E:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v2; // ebx\n\n switch ( a1 )\n {\n case 0:\n return 3LL;\n case 1:\n return 0LL;\n case 2:\n return 2LL;\n }\n v2 = sub_1149((unsigned int)(a1 - 2));\n return v2 + (unsigned int)sub_1149((unsigned int)(a1 - 3));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v2;\n switch (a1) {\n case 0:\n return 3LL;\n case 1:\n return 0LL;\n case 2:\n return 2LL;\n }\n v2 = sub_1149((unsigned int)(a1 - 2));\n return v2 + (unsigned int)sub_1149((unsigned int)(a1 - 3));\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v2;\n switch (a1) {\n case 0:\n return 3LL;\n case 1:\n return 0LL;\n case 2:\n return 2LL;\n }\n v2 = func0((unsigned int)(a1 - 2));\n return v2 + (unsigned int)func0((unsigned int)(a1 - 3));\n}" + }, + { + "index": 385, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int n) {\n if (n == 0) return 3;\n if (n == 1) return 0;\n if (n == 2) return 2;\n return func0(n - 2) + func0(n - 3);\n}", + "test": "int main() {\n\n assert(func0(9) == 12);\n\n assert(func0(4) == 2);\n\n assert(func0(6) == 5);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x3,%eax\ntest %edi,%edi\nje 118a \npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %edi,%ebx\nmov $0x0,%eax\ncmp $0x1,%edi\nje 1183 \nmov %edi,%eax\ncmp $0x2,%edi\nje 1183 \nlea -0x2(%rdi),%edi\ncallq 1149 \nmov %eax,%ebp\nlea -0x3(%rbx),%edi\ncallq 1149 \nadd %ebp,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nretq\n", + "ida_asm": "func0:\nendbr64\nmov eax, 3\ntest edi, edi\njz short locret_118A\npush rbp\npush rbx\nsub rsp, 8\nmov ebx, edi\nmov eax, 0\ncmp edi, 1\njz short loc_1183\nmov eax, edi\ncmp edi, 2\njz short loc_1183\nlea edi, [rdi-2]\ncall func0\nmov ebp, eax\nlea edi, [rbx-3]\ncall func0\nadd eax, ebp\nloc_1183:\nadd rsp, 8\npop rbx\npop rbp\nretn\nlocret_118A:\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1)\n{\n __int64 result; // rax\n int v2; // ebp\n\n result = 3LL;\n if ( a1 )\n {\n result = 0LL;\n if ( a1 != 1 )\n {\n result = a1;\n if ( a1 != 2 )\n {\n v2 = func0(a1 - 2);\n return v2 + (unsigned int)func0(a1 - 3);\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmov eax, 3\ntest edi, edi\njz short locret_118A\npush rbp\npush rbx\nsub rsp, 8\nmov ebx, edi\nmov eax, 0\ncmp edi, 1\njz short loc_1183\nmov eax, edi\ncmp edi, 2\njz short loc_1183\nlea edi, [rdi-2]\ncall sub_1149\nmov ebp, eax\nlea edi, [rbx-3]\ncall sub_1149\nadd eax, ebp\nloc_1183:\nadd rsp, 8\npop rbx\npop rbp\nretn\nlocret_118A:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(unsigned int a1)\n{\n __int64 result; // rax\n int v2; // ebp\n\n result = 3LL;\n if ( a1 )\n {\n result = 0LL;\n if ( a1 != 1 )\n {\n result = a1;\n if ( a1 != 2 )\n {\n v2 = sub_1149(a1 - 2);\n return v2 + (unsigned int)sub_1149(a1 - 3);\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(unsigned int a1) {\n long long result;\n int v2;\n result = 3LL;\n if (a1) {\n result = 0LL;\n if (a1 != 1) {\n result = a1;\n if (a1 != 2) {\n v2 = sub_1149(a1 - 2);\n return v2 + (unsigned int)sub_1149(a1 - 3);\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(unsigned int a1) {\n long long result;\n int v2;\n result = 3LL;\n if (a1) {\n result = 0LL;\n if (a1 != 1) {\n result = a1;\n if (a1 != 2) {\n v2 = func0(a1 - 2);\n return v2 + (unsigned int)func0(a1 - 3);\n }\n }\n }\n return result;\n}" + }, + { + "index": 385, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int n) {\n if (n == 0) return 3;\n if (n == 1) return 0;\n if (n == 2) return 2;\n return func0(n - 2) + func0(n - 3);\n}", + "test": "int main() {\n\n assert(func0(9) == 12);\n\n assert(func0(4) == 2);\n\n assert(func0(6) == 5);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbx\nsub $0x8,%rsp\ntest %edi,%edi\nje 1250 \ncmp $0x1,%edi\nje 1260 \nlea -0x2(%rdi),%ebx\nxor %r12d,%r12d\ncmp $0x2,%edi\nje 1268 \nmov %ebx,%edi\ncallq 11f0 \nadd %eax,%r12d\ncmp $0x1,%ebx\nje 1240 \ncmp $0x2,%ebx\nje 122c \nsub $0x3,%ebx\njne 120f \nadd $0x2,%r12d\nadd $0x8,%rsp\nmov %r12d,%eax\npop %rbx\npop %r12\nretq\nnopw 0x0(%rax,%rax,1)\nadd $0x3,%r12d\nadd $0x8,%rsp\nmov %r12d,%eax\npop %rbx\npop %r12\nretq\nmov $0x3,%r12d\njmp 122c \nnopl 0x0(%rax,%rax,1)\nxor %r12d,%r12d\njmp 122c \nnopl (%rax)\nmov $0x2,%r12d\njmp 122c \n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 38h\ntest edi, edi\njz loc_1546\nmov r13d, edi\ncmp edi, 1\njz loc_1551\ncmp edi, 2\njz loc_1484\nlea ebx, [rdi-2]\nxor ebp, ebp\nloc_1224:\ncmp ebx, 1\njz loc_153A\ncmp ebx, 2\njz loc_147D\nmov [rsp+68h+var_68], ebp\nlea r12d, [rbx-2]\nxor r15d, r15d\nmov r13d, ebx\nloc_1243:\ncmp r12d, 1\njz loc_152B\ncmp r12d, 2\njz loc_1467\nmov [rsp+68h+var_64], r15d\nlea ebx, [r12-2]\nxor ebp, ebp\nmov eax, r12d\nmov r14d, r13d\nmov r12d, ebx\nmov r13d, ebp\nloc_126F:\ncmp r12d, 1\njz loc_1515\ncmp r12d, 2\njz loc_1449\nlea ebp, [r12-2]\nxor r15d, r15d\nmov [rsp+68h+var_60], r12d\nmov ecx, eax\nmov r12d, r13d\nmov eax, r14d\nmov ebx, r15d\nmov r14d, ebp\nloc_129E:\ncmp r14d, 1\njz loc_14FC\ncmp r14d, 2\njz loc_1428\nmov [rsp+68h+var_5C], ebx\nlea r15d, [r14-2]\nxor r13d, r13d\nmov r8d, ecx\nmov esi, r15d\nmov edx, r14d\nmov r15d, r12d\nmov r14d, r13d\nmov ecx, eax\nloc_12CE:\ncmp esi, 1\njz loc_14E1\ncmp esi, 2\njz loc_1405\nlea r13d, [rsi-2]\nxor r12d, r12d\nmov r10d, r8d\nmov r8d, r14d\nmov ebx, r13d\nmov r9d, r12d\nloc_12F3:\ncmp ebx, 1\njz loc_14BF\ncmp ebx, 2\njz loc_13EC\nlea r14d, [rbx-2]\nxor ebp, ebp\nmov r12d, ebx\nmov ebx, r10d\nmov r11d, ebp\nmov ebp, r14d\nloc_1317:\ncmp ebp, 1\njz loc_14AE\ncmp ebp, 2\njz loc_13D4\nlea r14d, [rbp-2]\nmov r10d, ebp\nxor r13d, r13d\nmov ebp, ebx\nmov ebx, r14d\nloc_1338:\ncmp ebx, 1\njz loc_14A0\ncmp ebx, 2\njz short loc_13BF\nlea edi, [rbx-2]\nxor r14d, r14d\nloc_134C:\nmov [rsp+68h+var_3C], ecx\nmov [rsp+68h+var_40], edx\nmov [rsp+68h+var_44], r11d\nmov [rsp+68h+var_48], r9d\nmov [rsp+68h+var_4C], r10d\nmov [rsp+68h+var_50], r8d\nmov [rsp+68h+var_54], esi\nmov [rsp+68h+var_58], edi\ncall func0\nmov edi, [rsp+68h+var_58]\nmov esi, [rsp+68h+var_54]\nadd r14d, eax\nmov r8d, [rsp+68h+var_50]\nmov r10d, [rsp+68h+var_4C]\ncmp edi, 1\nmov r9d, [rsp+68h+var_48]\nmov r11d, [rsp+68h+var_44]\nmov edx, [rsp+68h+var_40]\nmov ecx, [rsp+68h+var_3C]\njz loc_14D8\ncmp edi, 2\njz short loc_13B3\nsub edi, 3\njnz short loc_134C\nadd r14d, 2\nloc_13B3:\nadd r13d, r14d\nsub ebx, 3\njnz loc_1338\nloc_13BF:\nmov ebx, ebp\nadd r13d, 2\nmov ebp, r10d\nloc_13C8:\nadd r11d, r13d\nsub ebp, 3\njnz loc_1317\nloc_13D4:\nmov ebp, r11d\nmov r10d, ebx\nmov ebx, r12d\nadd ebp, 2\nloc_13E0:\nadd r9d, ebp\nsub ebx, 3\njnz loc_12F3\nloc_13EC:\nmov r12d, r9d\nmov r14d, r8d\nmov r8d, r10d\nadd r12d, 2\nloc_13F9:\nadd r14d, r12d\nsub esi, 3\njnz loc_12CE\nloc_1405:\nmov r13d, r14d\nmov ebx, [rsp+68h+var_5C]\nmov eax, ecx\nmov r12d, r15d\nmov r14d, edx\nmov ecx, r8d\nadd r13d, 2\nloc_141B:\nadd ebx, r13d\nsub r14d, 3\njnz loc_129E\nloc_1428:\nmov r13d, r12d\nmov r15d, ebx\nmov r12d, [rsp+68h+var_60]\nmov r14d, eax\nadd r15d, 2\nmov eax, ecx\nloc_143C:\nadd r13d, r15d\nsub r12d, 3\njnz loc_126F\nloc_1449:\nmov ebp, r13d\nmov r15d, [rsp+68h+var_64]\nmov r12d, eax\nmov r13d, r14d\nadd ebp, 2\nloc_145A:\nadd r15d, ebp\nsub r12d, 3\njnz loc_1243\nloc_1467:\nmov ebp, [rsp+68h+var_68]\nmov ebx, r13d\nadd r15d, 2\nloc_1471:\nadd ebp, r15d\nsub ebx, 3\njnz loc_1224\nloc_147D:\nmov r13d, ebp\nadd r13d, 2\nloc_1484:\nadd rsp, 38h\nmov eax, r13d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14A0:\nmov ebx, ebp\nadd r13d, 3\nmov ebp, r10d\njmp loc_13C8\nloc_14AE:\nmov ebp, r11d\nmov r10d, ebx\nmov ebx, r12d\nadd ebp, 3\njmp loc_13E0\nloc_14BF:\nmov r12d, r9d\nmov r14d, r8d\nmov r8d, r10d\nadd r12d, 3\njmp loc_13F9\nloc_14D8:\nadd r14d, 3\njmp loc_13B3\nloc_14E1:\nmov r13d, r14d\nmov eax, ecx\nmov ebx, [rsp+68h+var_5C]\nmov r12d, r15d\nmov r14d, edx\nmov ecx, r8d\nadd r13d, 3\njmp loc_141B\nloc_14FC:\nmov r15d, ebx\nmov r13d, r12d\nmov r14d, eax\nmov r12d, [rsp+68h+var_60]\nmov eax, ecx\nadd r15d, 3\njmp loc_143C\nloc_1515:\nmov ebp, r13d\nmov r15d, [rsp+68h+var_64]\nmov r12d, eax\nmov r13d, r14d\nadd ebp, 3\njmp loc_145A\nloc_152B:\nmov ebp, [rsp+68h+var_68]\nmov ebx, r13d\nadd r15d, 3\njmp loc_1471\nloc_153A:\nmov r13d, ebp\nadd r13d, 3\njmp loc_1484\nloc_1546:\nmov r13d, 3\njmp loc_1484\nloc_1551:\nxor r13d, r13d\njmp loc_1484", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1)\n{\n unsigned int v1; // r13d\n unsigned int v2; // ebx\n int v3; // ebp\n unsigned int v4; // r12d\n int v5; // r15d\n unsigned int v6; // r13d\n unsigned int v7; // eax\n unsigned int v8; // r14d\n unsigned int v9; // r12d\n int v10; // r13d\n unsigned int v11; // ebp\n unsigned int v12; // ecx\n int v13; // r12d\n unsigned int v14; // eax\n int v15; // ebx\n unsigned int v16; // r14d\n unsigned int v17; // r8d\n unsigned int v18; // esi\n unsigned int v19; // edx\n int v20; // r15d\n int v21; // r14d\n unsigned int v22; // ecx\n unsigned int v23; // r10d\n int v24; // r8d\n unsigned int v25; // ebx\n int v26; // r9d\n int v27; // r14d\n int v28; // r12d\n unsigned int v29; // ebx\n int v30; // r11d\n int v31; // ebp\n int v32; // r14d\n int v33; // r10d\n int v34; // r13d\n unsigned int v35; // ebp\n int v36; // ebx\n int v37; // edi\n int v38; // r14d\n int v39; // r13d\n int v40; // ebp\n int v41; // ebx\n int v42; // ebp\n int v43; // r14d\n int v44; // r12d\n int v45; // r13d\n int v46; // ebx\n unsigned int v47; // r14d\n int v48; // r13d\n int v49; // r13d\n unsigned int v50; // r12d\n int v51; // r15d\n int v52; // ebp\n int v53; // r15d\n unsigned int v54; // r12d\n int v55; // ebp\n int v56; // ebp\n unsigned int v57; // ebx\n int v58; // r15d\n int v60; // r13d\n int v61; // ebp\n int v62; // [rsp+0h] [rbp-68h]\n int v63; // [rsp+4h] [rbp-64h]\n unsigned int v64; // [rsp+8h] [rbp-60h]\n int v65; // [rsp+Ch] [rbp-5Ch]\n int v66; // [rsp+18h] [rbp-50h]\n int v67; // [rsp+1Ch] [rbp-4Ch]\n int v68; // [rsp+20h] [rbp-48h]\n int v69; // [rsp+24h] [rbp-44h]\n unsigned int v70; // [rsp+28h] [rbp-40h]\n unsigned int v71; // [rsp+2Ch] [rbp-3Ch]\n\n if ( a1 )\n {\n v1 = a1;\n if ( a1 == 1 )\n {\n return 0;\n }\n else if ( a1 != 2 )\n {\n v2 = a1 - 2;\n v3 = 0;\n while ( v2 != 1 )\n {\n if ( v2 != 2 )\n {\n v62 = v3;\n v4 = v2 - 2;\n v5 = 0;\n v6 = v2;\n while ( v4 != 1 )\n {\n if ( v4 != 2 )\n {\n v63 = v5;\n v7 = v4;\n v8 = v6;\n v9 = v4 - 2;\n v10 = 0;\n while ( v9 != 1 )\n {\n if ( v9 != 2 )\n {\n v11 = v9 - 2;\n v64 = v9;\n v12 = v7;\n v13 = v10;\n v14 = v8;\n v15 = 0;\n v16 = v11;\n while ( v16 != 1 )\n {\n if ( v16 != 2 )\n {\n v65 = v15;\n v17 = v12;\n v18 = v16 - 2;\n v19 = v16;\n v20 = v13;\n v21 = 0;\n v22 = v14;\n while ( v18 != 1 )\n {\n if ( v18 != 2 )\n {\n v23 = v17;\n v24 = v21;\n v25 = v18 - 2;\n v26 = 0;\n while ( v25 != 1 )\n {\n if ( v25 != 2 )\n {\n v27 = v25 - 2;\n v28 = v25;\n v29 = v23;\n v30 = 0;\n v31 = v27;\n while ( v31 != 1 )\n {\n if ( v31 != 2 )\n {\n v32 = v31 - 2;\n v33 = v31;\n v34 = 0;\n v35 = v29;\n v36 = v32;\n while ( v36 != 1 )\n {\n if ( v36 != 2 )\n {\n v37 = v36 - 2;\n v38 = 0;\n while ( 1 )\n {\n v71 = v22;\n v70 = v19;\n v69 = v30;\n v68 = v26;\n v67 = v33;\n v66 = v24;\n v38 += func0();\n v24 = v66;\n v33 = v67;\n v26 = v68;\n v30 = v69;\n v19 = v70;\n v22 = v71;\n if ( v37 == 1 )\n break;\n if ( v37 == 2 )\n goto LABEL_33;\n v37 -= 3;\n if ( !v37 )\n {\n v38 += 2;\n goto LABEL_33;\n }\n }\n v38 += 3;\nLABEL_33:\n v34 += v38;\n v36 -= 3;\n if ( v36 )\n continue;\n }\n v29 = v35;\n v39 = v34 + 2;\n v40 = v33;\n goto LABEL_35;\n }\n v29 = v35;\n v39 = v34 + 3;\n v40 = v33;\nLABEL_35:\n v30 += v39;\n v31 = v40 - 3;\n if ( v31 )\n continue;\n }\n v23 = v29;\n v41 = v28;\n v42 = v30 + 2;\n goto LABEL_37;\n }\n v23 = v29;\n v41 = v28;\n v42 = v30 + 3;\nLABEL_37:\n v26 += v42;\n v25 = v41 - 3;\n if ( v25 )\n continue;\n }\n v43 = v24;\n v17 = v23;\n v44 = v26 + 2;\n goto LABEL_39;\n }\n v43 = v24;\n v17 = v23;\n v44 = v26 + 3;\nLABEL_39:\n v21 = v44 + v43;\n v18 -= 3;\n if ( v18 )\n continue;\n }\n v45 = v21;\n v46 = v65;\n v14 = v22;\n v13 = v20;\n v47 = v19;\n v12 = v17;\n v48 = v45 + 2;\n goto LABEL_41;\n }\n v60 = v21;\n v14 = v22;\n v46 = v65;\n v13 = v20;\n v47 = v19;\n v12 = v17;\n v48 = v60 + 3;\nLABEL_41:\n v15 = v48 + v46;\n v16 = v47 - 3;\n if ( v16 )\n continue;\n }\n v49 = v13;\n v50 = v64;\n v8 = v14;\n v51 = v15 + 2;\n v7 = v12;\n goto LABEL_43;\n }\n v49 = v13;\n v8 = v14;\n v50 = v64;\n v7 = v12;\n v51 = v15 + 3;\nLABEL_43:\n v10 = v51 + v49;\n v9 = v50 - 3;\n if ( v9 )\n continue;\n }\n v52 = v10;\n v53 = v63;\n v54 = v7;\n v6 = v8;\n v55 = v52 + 2;\n goto LABEL_45;\n }\n v61 = v10;\n v53 = v63;\n v54 = v7;\n v6 = v8;\n v55 = v61 + 3;\nLABEL_45:\n v5 = v55 + v53;\n v4 = v54 - 3;\n if ( v4 )\n continue;\n }\n v56 = v62;\n v57 = v6;\n v58 = v5 + 2;\n goto LABEL_47;\n }\n v56 = v62;\n v57 = v6;\n v58 = v5 + 3;\nLABEL_47:\n v3 = v58 + v56;\n v2 = v57 - 3;\n if ( v2 )\n continue;\n }\n return (unsigned int)(v3 + 2);\n }\n return (unsigned int)(v3 + 3);\n }\n }\n else\n {\n return 3;\n }\n return v1;\n}", + "ida_strip_asm": "sub_11F0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 38h\ntest edi, edi\njz loc_1546\nmov r13d, edi\ncmp edi, 1\njz loc_1551\ncmp edi, 2\njz loc_1484\nlea ebx, [rdi-2]\nxor ebp, ebp\nloc_1224:\ncmp ebx, 1\njz loc_153A\ncmp ebx, 2\njz loc_147D\nmov [rsp+68h+var_68], ebp\nlea r12d, [rbx-2]\nxor r15d, r15d\nmov r13d, ebx\nloc_1243:\ncmp r12d, 1\njz loc_152B\ncmp r12d, 2\njz loc_1467\nmov [rsp+68h+var_64], r15d\nlea ebx, [r12-2]\nxor ebp, ebp\nmov eax, r12d\nmov r14d, r13d\nmov r12d, ebx\nmov r13d, ebp\nloc_126F:\ncmp r12d, 1\njz loc_1515\ncmp r12d, 2\njz loc_1449\nlea ebp, [r12-2]\nxor r15d, r15d\nmov [rsp+68h+var_60], r12d\nmov ecx, eax\nmov r12d, r13d\nmov eax, r14d\nmov ebx, r15d\nmov r14d, ebp\nloc_129E:\ncmp r14d, 1\njz loc_14FC\ncmp r14d, 2\njz loc_1428\nmov [rsp+68h+var_5C], ebx\nlea r15d, [r14-2]\nxor r13d, r13d\nmov r8d, ecx\nmov esi, r15d\nmov edx, r14d\nmov r15d, r12d\nmov r14d, r13d\nmov ecx, eax\nloc_12CE:\ncmp esi, 1\njz loc_14E1\ncmp esi, 2\njz loc_1405\nlea r13d, [rsi-2]\nxor r12d, r12d\nmov r10d, r8d\nmov r8d, r14d\nmov ebx, r13d\nmov r9d, r12d\nloc_12F3:\ncmp ebx, 1\njz loc_14BF\ncmp ebx, 2\njz loc_13EC\nlea r14d, [rbx-2]\nxor ebp, ebp\nmov r12d, ebx\nmov ebx, r10d\nmov r11d, ebp\nmov ebp, r14d\nloc_1317:\ncmp ebp, 1\njz loc_14AE\ncmp ebp, 2\njz loc_13D4\nlea r14d, [rbp-2]\nmov r10d, ebp\nxor r13d, r13d\nmov ebp, ebx\nmov ebx, r14d\nloc_1338:\ncmp ebx, 1\njz loc_14A0\ncmp ebx, 2\njz short loc_13BF\nlea edi, [rbx-2]\nxor r14d, r14d\nloc_134C:\nmov [rsp+68h+var_3C], ecx\nmov [rsp+68h+var_40], edx\nmov [rsp+68h+var_44], r11d\nmov [rsp+68h+var_48], r9d\nmov [rsp+68h+var_4C], r10d\nmov [rsp+68h+var_50], r8d\nmov [rsp+68h+var_54], esi\nmov [rsp+68h+var_58], edi\ncall sub_11F0\nmov edi, [rsp+68h+var_58]\nmov esi, [rsp+68h+var_54]\nadd r14d, eax\nmov r8d, [rsp+68h+var_50]\nmov r10d, [rsp+68h+var_4C]\ncmp edi, 1\nmov r9d, [rsp+68h+var_48]\nmov r11d, [rsp+68h+var_44]\nmov edx, [rsp+68h+var_40]\nmov ecx, [rsp+68h+var_3C]\njz loc_14D8\ncmp edi, 2\njz short loc_13B3\nsub edi, 3\njnz short loc_134C\nadd r14d, 2\nloc_13B3:\nadd r13d, r14d\nsub ebx, 3\njnz loc_1338\nloc_13BF:\nmov ebx, ebp\nadd r13d, 2\nmov ebp, r10d\nloc_13C8:\nadd r11d, r13d\nsub ebp, 3\njnz loc_1317\nloc_13D4:\nmov ebp, r11d\nmov r10d, ebx\nmov ebx, r12d\nadd ebp, 2\nloc_13E0:\nadd r9d, ebp\nsub ebx, 3\njnz loc_12F3\nloc_13EC:\nmov r12d, r9d\nmov r14d, r8d\nmov r8d, r10d\nadd r12d, 2\nloc_13F9:\nadd r14d, r12d\nsub esi, 3\njnz loc_12CE\nloc_1405:\nmov r13d, r14d\nmov ebx, [rsp+68h+var_5C]\nmov eax, ecx\nmov r12d, r15d\nmov r14d, edx\nmov ecx, r8d\nadd r13d, 2\nloc_141B:\nadd ebx, r13d\nsub r14d, 3\njnz loc_129E\nloc_1428:\nmov r13d, r12d\nmov r15d, ebx\nmov r12d, [rsp+68h+var_60]\nmov r14d, eax\nadd r15d, 2\nmov eax, ecx\nloc_143C:\nadd r13d, r15d\nsub r12d, 3\njnz loc_126F\nloc_1449:\nmov ebp, r13d\nmov r15d, [rsp+68h+var_64]\nmov r12d, eax\nmov r13d, r14d\nadd ebp, 2\nloc_145A:\nadd r15d, ebp\nsub r12d, 3\njnz loc_1243\nloc_1467:\nmov ebp, [rsp+68h+var_68]\nmov ebx, r13d\nadd r15d, 2\nloc_1471:\nadd ebp, r15d\nsub ebx, 3\njnz loc_1224\nloc_147D:\nmov r13d, ebp\nadd r13d, 2\nloc_1484:\nadd rsp, 38h\nmov eax, r13d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14A0:\nmov ebx, ebp\nadd r13d, 3\nmov ebp, r10d\njmp loc_13C8\nloc_14AE:\nmov ebp, r11d\nmov r10d, ebx\nmov ebx, r12d\nadd ebp, 3\njmp loc_13E0\nloc_14BF:\nmov r12d, r9d\nmov r14d, r8d\nmov r8d, r10d\nadd r12d, 3\njmp loc_13F9\nloc_14D8:\nadd r14d, 3\njmp loc_13B3\nloc_14E1:\nmov r13d, r14d\nmov eax, ecx\nmov ebx, [rsp+68h+var_5C]\nmov r12d, r15d\nmov r14d, edx\nmov ecx, r8d\nadd r13d, 3\njmp loc_141B\nloc_14FC:\nmov r15d, ebx\nmov r13d, r12d\nmov r14d, eax\nmov r12d, [rsp+68h+var_60]\nmov eax, ecx\nadd r15d, 3\njmp loc_143C\nloc_1515:\nmov ebp, r13d\nmov r15d, [rsp+68h+var_64]\nmov r12d, eax\nmov r13d, r14d\nadd ebp, 3\njmp loc_145A\nloc_152B:\nmov ebp, [rsp+68h+var_68]\nmov ebx, r13d\nadd r15d, 3\njmp loc_1471\nloc_153A:\nmov r13d, ebp\nadd r13d, 3\njmp loc_1484\nloc_1546:\nmov r13d, 3\njmp loc_1484\nloc_1551:\nxor r13d, r13d\njmp loc_1484", + "ida_strip_pseudo": "__int64 __fastcall sub_11F0(unsigned int a1)\n{\n unsigned int v1; // r13d\n unsigned int v2; // ebx\n int v3; // ebp\n unsigned int v4; // r12d\n int v5; // r15d\n unsigned int v6; // r13d\n unsigned int v7; // eax\n unsigned int v8; // r14d\n unsigned int v9; // r12d\n int v10; // r13d\n unsigned int v11; // ebp\n unsigned int v12; // ecx\n int v13; // r12d\n unsigned int v14; // eax\n int v15; // ebx\n unsigned int v16; // r14d\n unsigned int v17; // r8d\n unsigned int v18; // esi\n unsigned int v19; // edx\n int v20; // r15d\n int v21; // r14d\n unsigned int v22; // ecx\n unsigned int v23; // r10d\n int v24; // r8d\n unsigned int v25; // ebx\n int v26; // r9d\n int v27; // r14d\n int v28; // r12d\n unsigned int v29; // ebx\n int v30; // r11d\n int v31; // ebp\n int v32; // r14d\n int v33; // r10d\n int v34; // r13d\n unsigned int v35; // ebp\n int v36; // ebx\n int v37; // edi\n int v38; // r14d\n int v39; // r13d\n int v40; // ebp\n int v41; // ebx\n int v42; // ebp\n int v43; // r14d\n int v44; // r12d\n int v45; // r13d\n int v46; // ebx\n unsigned int v47; // r14d\n int v48; // r13d\n int v49; // r13d\n unsigned int v50; // r12d\n int v51; // r15d\n int v52; // ebp\n int v53; // r15d\n unsigned int v54; // r12d\n int v55; // ebp\n int v56; // ebp\n unsigned int v57; // ebx\n int v58; // r15d\n int v60; // r13d\n int v61; // ebp\n int v62; // [rsp+0h] [rbp-68h]\n int v63; // [rsp+4h] [rbp-64h]\n unsigned int v64; // [rsp+8h] [rbp-60h]\n int v65; // [rsp+Ch] [rbp-5Ch]\n int v66; // [rsp+18h] [rbp-50h]\n int v67; // [rsp+1Ch] [rbp-4Ch]\n int v68; // [rsp+20h] [rbp-48h]\n int v69; // [rsp+24h] [rbp-44h]\n unsigned int v70; // [rsp+28h] [rbp-40h]\n unsigned int v71; // [rsp+2Ch] [rbp-3Ch]\n\n if ( a1 )\n {\n v1 = a1;\n if ( a1 == 1 )\n {\n return 0;\n }\n else if ( a1 != 2 )\n {\n v2 = a1 - 2;\n v3 = 0;\n while ( v2 != 1 )\n {\n if ( v2 != 2 )\n {\n v62 = v3;\n v4 = v2 - 2;\n v5 = 0;\n v6 = v2;\n while ( v4 != 1 )\n {\n if ( v4 != 2 )\n {\n v63 = v5;\n v7 = v4;\n v8 = v6;\n v9 = v4 - 2;\n v10 = 0;\n while ( v9 != 1 )\n {\n if ( v9 != 2 )\n {\n v11 = v9 - 2;\n v64 = v9;\n v12 = v7;\n v13 = v10;\n v14 = v8;\n v15 = 0;\n v16 = v11;\n while ( v16 != 1 )\n {\n if ( v16 != 2 )\n {\n v65 = v15;\n v17 = v12;\n v18 = v16 - 2;\n v19 = v16;\n v20 = v13;\n v21 = 0;\n v22 = v14;\n while ( v18 != 1 )\n {\n if ( v18 != 2 )\n {\n v23 = v17;\n v24 = v21;\n v25 = v18 - 2;\n v26 = 0;\n while ( v25 != 1 )\n {\n if ( v25 != 2 )\n {\n v27 = v25 - 2;\n v28 = v25;\n v29 = v23;\n v30 = 0;\n v31 = v27;\n while ( v31 != 1 )\n {\n if ( v31 != 2 )\n {\n v32 = v31 - 2;\n v33 = v31;\n v34 = 0;\n v35 = v29;\n v36 = v32;\n while ( v36 != 1 )\n {\n if ( v36 != 2 )\n {\n v37 = v36 - 2;\n v38 = 0;\n while ( 1 )\n {\n v71 = v22;\n v70 = v19;\n v69 = v30;\n v68 = v26;\n v67 = v33;\n v66 = v24;\n v38 += sub_11F0();\n v24 = v66;\n v33 = v67;\n v26 = v68;\n v30 = v69;\n v19 = v70;\n v22 = v71;\n if ( v37 == 1 )\n break;\n if ( v37 == 2 )\n goto LABEL_33;\n v37 -= 3;\n if ( !v37 )\n {\n v38 += 2;\n goto LABEL_33;\n }\n }\n v38 += 3;\nLABEL_33:\n v34 += v38;\n v36 -= 3;\n if ( v36 )\n continue;\n }\n v29 = v35;\n v39 = v34 + 2;\n v40 = v33;\n goto LABEL_35;\n }\n v29 = v35;\n v39 = v34 + 3;\n v40 = v33;\nLABEL_35:\n v30 += v39;\n v31 = v40 - 3;\n if ( v31 )\n continue;\n }\n v23 = v29;\n v41 = v28;\n v42 = v30 + 2;\n goto LABEL_37;\n }\n v23 = v29;\n v41 = v28;\n v42 = v30 + 3;\nLABEL_37:\n v26 += v42;\n v25 = v41 - 3;\n if ( v25 )\n continue;\n }\n v43 = v24;\n v17 = v23;\n v44 = v26 + 2;\n goto LABEL_39;\n }\n v43 = v24;\n v17 = v23;\n v44 = v26 + 3;\nLABEL_39:\n v21 = v44 + v43;\n v18 -= 3;\n if ( v18 )\n continue;\n }\n v45 = v21;\n v46 = v65;\n v14 = v22;\n v13 = v20;\n v47 = v19;\n v12 = v17;\n v48 = v45 + 2;\n goto LABEL_41;\n }\n v60 = v21;\n v14 = v22;\n v46 = v65;\n v13 = v20;\n v47 = v19;\n v12 = v17;\n v48 = v60 + 3;\nLABEL_41:\n v15 = v48 + v46;\n v16 = v47 - 3;\n if ( v16 )\n continue;\n }\n v49 = v13;\n v50 = v64;\n v8 = v14;\n v51 = v15 + 2;\n v7 = v12;\n goto LABEL_43;\n }\n v49 = v13;\n v8 = v14;\n v50 = v64;\n v7 = v12;\n v51 = v15 + 3;\nLABEL_43:\n v10 = v51 + v49;\n v9 = v50 - 3;\n if ( v9 )\n continue;\n }\n v52 = v10;\n v53 = v63;\n v54 = v7;\n v6 = v8;\n v55 = v52 + 2;\n goto LABEL_45;\n }\n v61 = v10;\n v53 = v63;\n v54 = v7;\n v6 = v8;\n v55 = v61 + 3;\nLABEL_45:\n v5 = v55 + v53;\n v4 = v54 - 3;\n if ( v4 )\n continue;\n }\n v56 = v62;\n v57 = v6;\n v58 = v5 + 2;\n goto LABEL_47;\n }\n v56 = v62;\n v57 = v6;\n v58 = v5 + 3;\nLABEL_47:\n v3 = v58 + v56;\n v2 = v57 - 3;\n if ( v2 )\n continue;\n }\n return (unsigned int)(v3 + 2);\n }\n return (unsigned int)(v3 + 3);\n }\n }\n else\n {\n return 3;\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11F0(unsigned int a1) {\n unsigned int v1;\n unsigned int v2;\n int v3;\n unsigned int v4;\n int v5;\n unsigned int v6;\n unsigned int v7;\n unsigned int v8;\n unsigned int v9;\n int v10;\n unsigned int v11;\n unsigned int v12;\n int v13;\n unsigned int v14;\n int v15;\n unsigned int v16;\n unsigned int v17;\n unsigned int v18;\n unsigned int v19;\n int v20;\n int v21;\n unsigned int v22;\n unsigned int v23;\n int v24;\n unsigned int v25;\n int v26;\n int v27;\n int v28;\n unsigned int v29;\n int v30;\n int v31;\n int v32;\n int v33;\n int v34;\n unsigned int v35;\n int v36;\n int v37;\n int v38;\n int v39;\n int v40;\n int v41;\n int v42;\n int v43;\n int v44;\n int v45;\n int v46;\n unsigned int v47;\n int v48;\n int v49;\n unsigned int v50;\n int v51;\n int v52;\n int v53;\n unsigned int v54;\n int v55;\n int v56;\n unsigned int v57;\n int v58;\n int v60;\n int v61;\n int v62;\n int v63;\n unsigned int v64;\n int v65;\n int v66;\n int v67;\n int v68;\n int v69;\n unsigned int v70;\n unsigned int v71;\n if (a1) {\n v1 = a1;\n if (a1 == 1) {\n return 0;\n } else if (a1 != 2) {\n v2 = a1 - 2;\n v3 = 0;\n while (v2 != 1) {\n if (v2 != 2) {\n v62 = v3;\n v4 = v2 - 2;\n v5 = 0;\n v6 = v2;\n while (v4 != 1) {\n if (v4 != 2) {\n v63 = v5;\n v7 = v4;\n v8 = v6;\n v9 = v4 - 2;\n v10 = 0;\n while (v9 != 1) {\n if (v9 != 2) {\n v11 = v9 - 2;\n v64 = v9;\n v12 = v7;\n v13 = v10;\n v14 = v8;\n v15 = 0;\n v16 = v11;\n while (v16 != 1) {\n if (v16 != 2) {\n v65 = v15;\n v17 = v12;\n v18 = v16 - 2;\n v19 = v16;\n v20 = v13;\n v21 = 0;\n v22 = v14;\n while (v18 != 1) {\n if (v18 != 2) {\n v23 = v17;\n v24 = v21;\n v25 = v18 - 2;\n v26 = 0;\n while (v25 != 1) {\n if (v25 != 2) {\n v27 = v25 - 2;\n v28 = v25;\n v29 = v23;\n v30 = 0;\n v31 = v27;\n while (v31 != 1) {\n if (v31 != 2) {\n v32 = v31 - 2;\n v33 = v31;\n v34 = 0;\n v35 = v29;\n v36 = v32;\n while (v36 != 1) {\n if (v36 != 2) {\n v37 = v36 - 2;\n v38 = 0;\n while (1) {\n v71 = v22;\n v70 = v19;\n v69 = v30;\n v68 = v26;\n v67 = v33;\n v66 = v24;\n v38 += sub_11F0();\n v24 = v66;\n v33 = v67;\n v26 = v68;\n v30 = v69;\n v19 = v70;\n v22 = v71;\n if (v37 == 1) break;\n if (v37 == 2) goto LABEL_33;\n v37 -= 3;\n if (!v37) {\n v38 += 2;\n goto LABEL_33;\n }\n }\n v38 += 3;\n LABEL_33:\n v34 += v38;\n v36 -= 3;\n if (v36) continue;\n }\n v29 = v35;\n v39 = v34 + 2;\n v40 = v33;\n goto LABEL_35;\n }\n v29 = v35;\n v39 = v34 + 3;\n v40 = v33;\n LABEL_35:\n v30 += v39;\n v31 = v40 - 3;\n if (v31) continue;\n }\n v23 = v29;\n v41 = v28;\n v42 = v30 + 2;\n goto LABEL_37;\n }\n v23 = v29;\n v41 = v28;\n v42 = v30 + 3;\n LABEL_37:\n v26 += v42;\n v25 = v41 - 3;\n if (v25) continue;\n }\n v43 = v24;\n v17 = v23;\n v44 = v26 + 2;\n goto LABEL_39;\n }\n v43 = v24;\n v17 = v23;\n v44 = v26 + 3;\n LABEL_39:\n v21 = v44 + v43;\n v18 -= 3;\n if (v18) continue;\n }\n v45 = v21;\n v46 = v65;\n v14 = v22;\n v13 = v20;\n v47 = v19;\n v12 = v17;\n v48 = v45 + 2;\n goto LABEL_41;\n }\n v60 = v21;\n v14 = v22;\n v46 = v65;\n v13 = v20;\n v47 = v19;\n v12 = v17;\n v48 = v60 + 3;\n LABEL_41:\n v15 = v48 + v46;\n v16 = v47 - 3;\n if (v16) continue;\n }\n v49 = v13;\n v50 = v64;\n v8 = v14;\n v51 = v15 + 2;\n v7 = v12;\n goto LABEL_43;\n }\n v49 = v13;\n v8 = v14;\n v50 = v64;\n v7 = v12;\n v51 = v15 + 3;\n LABEL_43:\n v10 = v51 + v49;\n v9 = v50 - 3;\n if (v9) continue;\n }\n v52 = v10;\n v53 = v63;\n v54 = v7;\n v6 = v8;\n v55 = v52 + 2;\n goto LABEL_45;\n }\n v61 = v10;\n v53 = v63;\n v54 = v7;\n v6 = v8;\n v55 = v61 + 3;\n LABEL_45:\n v5 = v55 + v53;\n v4 = v54 - 3;\n if (v4) continue;\n }\n v56 = v62;\n v57 = v6;\n v58 = v5 + 2;\n goto LABEL_47;\n }\n v56 = v62;\n v57 = v6;\n v58 = v5 + 3;\n LABEL_47:\n v3 = v58 + v56;\n v2 = v57 - 3;\n if (v2) continue;\n }\n return (unsigned int)(v3 + 2);\n }\n return (unsigned int)(v3 + 3);\n }\n } else {\n return 3;\n }\n return v1;\n}", + "ida_pseudo_norm": "long long func0(unsigned int a1) {\n unsigned int v1;\n unsigned int v2;\n int v3;\n unsigned int v4;\n int v5;\n unsigned int v6;\n unsigned int v7;\n unsigned int v8;\n unsigned int v9;\n int v10;\n unsigned int v11;\n unsigned int v12;\n int v13;\n unsigned int v14;\n int v15;\n unsigned int v16;\n unsigned int v17;\n unsigned int v18;\n unsigned int v19;\n int v20;\n int v21;\n unsigned int v22;\n unsigned int v23;\n int v24;\n unsigned int v25;\n int v26;\n int v27;\n int v28;\n unsigned int v29;\n int v30;\n int v31;\n int v32;\n int v33;\n int v34;\n unsigned int v35;\n int v36;\n int v37;\n int v38;\n int v39;\n int v40;\n int v41;\n int v42;\n int v43;\n int v44;\n int v45;\n int v46;\n unsigned int v47;\n int v48;\n int v49;\n unsigned int v50;\n int v51;\n int v52;\n int v53;\n unsigned int v54;\n int v55;\n int v56;\n unsigned int v57;\n int v58;\n int v60;\n int v61;\n int v62;\n int v63;\n unsigned int v64;\n int v65;\n int v66;\n int v67;\n int v68;\n int v69;\n unsigned int v70;\n unsigned int v71;\n if (a1) {\n v1 = a1;\n if (a1 == 1) {\n return 0;\n } else if (a1 != 2) {\n v2 = a1 - 2;\n v3 = 0;\n while (v2 != 1) {\n if (v2 != 2) {\n v62 = v3;\n v4 = v2 - 2;\n v5 = 0;\n v6 = v2;\n while (v4 != 1) {\n if (v4 != 2) {\n v63 = v5;\n v7 = v4;\n v8 = v6;\n v9 = v4 - 2;\n v10 = 0;\n while (v9 != 1) {\n if (v9 != 2) {\n v11 = v9 - 2;\n v64 = v9;\n v12 = v7;\n v13 = v10;\n v14 = v8;\n v15 = 0;\n v16 = v11;\n while (v16 != 1) {\n if (v16 != 2) {\n v65 = v15;\n v17 = v12;\n v18 = v16 - 2;\n v19 = v16;\n v20 = v13;\n v21 = 0;\n v22 = v14;\n while (v18 != 1) {\n if (v18 != 2) {\n v23 = v17;\n v24 = v21;\n v25 = v18 - 2;\n v26 = 0;\n while (v25 != 1) {\n if (v25 != 2) {\n v27 = v25 - 2;\n v28 = v25;\n v29 = v23;\n v30 = 0;\n v31 = v27;\n while (v31 != 1) {\n if (v31 != 2) {\n v32 = v31 - 2;\n v33 = v31;\n v34 = 0;\n v35 = v29;\n v36 = v32;\n while (v36 != 1) {\n if (v36 != 2) {\n v37 = v36 - 2;\n v38 = 0;\n while (1) {\n v71 = v22;\n v70 = v19;\n v69 = v30;\n v68 = v26;\n v67 = v33;\n v66 = v24;\n v38 += func0();\n v24 = v66;\n v33 = v67;\n v26 = v68;\n v30 = v69;\n v19 = v70;\n v22 = v71;\n if (v37 == 1) break;\n if (v37 == 2) goto LABEL_33;\n v37 -= 3;\n if (!v37) {\n v38 += 2;\n goto LABEL_33;\n }\n }\n v38 += 3;\n LABEL_33:\n v34 += v38;\n v36 -= 3;\n if (v36) continue;\n }\n v29 = v35;\n v39 = v34 + 2;\n v40 = v33;\n goto LABEL_35;\n }\n v29 = v35;\n v39 = v34 + 3;\n v40 = v33;\n LABEL_35:\n v30 += v39;\n v31 = v40 - 3;\n if (v31) continue;\n }\n v23 = v29;\n v41 = v28;\n v42 = v30 + 2;\n goto LABEL_37;\n }\n v23 = v29;\n v41 = v28;\n v42 = v30 + 3;\n LABEL_37:\n v26 += v42;\n v25 = v41 - 3;\n if (v25) continue;\n }\n v43 = v24;\n v17 = v23;\n v44 = v26 + 2;\n goto LABEL_39;\n }\n v43 = v24;\n v17 = v23;\n v44 = v26 + 3;\n LABEL_39:\n v21 = v44 + v43;\n v18 -= 3;\n if (v18) continue;\n }\n v45 = v21;\n v46 = v65;\n v14 = v22;\n v13 = v20;\n v47 = v19;\n v12 = v17;\n v48 = v45 + 2;\n goto LABEL_41;\n }\n v60 = v21;\n v14 = v22;\n v46 = v65;\n v13 = v20;\n v47 = v19;\n v12 = v17;\n v48 = v60 + 3;\n LABEL_41:\n v15 = v48 + v46;\n v16 = v47 - 3;\n if (v16) continue;\n }\n v49 = v13;\n v50 = v64;\n v8 = v14;\n v51 = v15 + 2;\n v7 = v12;\n goto LABEL_43;\n }\n v49 = v13;\n v8 = v14;\n v50 = v64;\n v7 = v12;\n v51 = v15 + 3;\n LABEL_43:\n v10 = v51 + v49;\n v9 = v50 - 3;\n if (v9) continue;\n }\n v52 = v10;\n v53 = v63;\n v54 = v7;\n v6 = v8;\n v55 = v52 + 2;\n goto LABEL_45;\n }\n v61 = v10;\n v53 = v63;\n v54 = v7;\n v6 = v8;\n v55 = v61 + 3;\n LABEL_45:\n v5 = v55 + v53;\n v4 = v54 - 3;\n if (v4) continue;\n }\n v56 = v62;\n v57 = v6;\n v58 = v5 + 2;\n goto LABEL_47;\n }\n v56 = v62;\n v57 = v6;\n v58 = v5 + 3;\n LABEL_47:\n v3 = v58 + v56;\n v2 = v57 - 3;\n if (v2) continue;\n }\n return (unsigned int)(v3 + 2);\n }\n return (unsigned int)(v3 + 3);\n }\n } else {\n return 3;\n }\n return v1;\n}" + }, + { + "index": 385, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int n) {\n if (n == 0) return 3;\n if (n == 1) return 0;\n if (n == 2) return 2;\n return func0(n - 2) + func0(n - 3);\n}", + "test": "int main() {\n\n assert(func0(9) == 12);\n\n assert(func0(4) == 2);\n\n assert(func0(6) == 5);\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbx\nsub $0x8,%rsp\ntest %edi,%edi\nje 1250 \ncmp $0x1,%edi\nje 1260 \nlea -0x2(%rdi),%ebx\nxor %r12d,%r12d\ncmp $0x2,%edi\nje 1268 \nmov %ebx,%edi\ncallq 11f0 \nadd %eax,%r12d\ncmp $0x1,%ebx\nje 1240 \ncmp $0x2,%ebx\nje 122c \nsub $0x3,%ebx\njne 120f \nadd $0x2,%r12d\nadd $0x8,%rsp\nmov %r12d,%eax\npop %rbx\npop %r12\nretq\nnopw 0x0(%rax,%rax,1)\nadd $0x3,%r12d\nadd $0x8,%rsp\nmov %r12d,%eax\npop %rbx\npop %r12\nretq\nmov $0x3,%r12d\njmp 122c \nnopl 0x0(%rax,%rax,1)\nxor %r12d,%r12d\njmp 122c \nnopl (%rax)\nmov $0x2,%r12d\njmp 122c \n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 38h\ntest edi, edi\njz loc_1537\nmov r13d, edi\ncmp edi, 1\njz loc_1542\ncmp edi, 2\njz loc_1488\nlea ebx, [rdi-2]\nxor ebp, ebp\nloc_1244:\ncmp ebx, 1\njz loc_152B\ncmp ebx, 2\njz loc_1481\nmov [rsp+68h+var_68], ebp\nlea r12d, [rbx-2]\nxor r15d, r15d\nmov r13d, ebx\nloc_1263:\ncmp r12d, 1\njz loc_151C\ncmp r12d, 2\njz loc_146B\nmov [rsp+68h+var_64], r15d\nlea ebx, [r12-2]\nxor ebp, ebp\nmov r14d, r13d\nmov [rsp+68h+var_60], r12d\nmov r13d, ebp\nmov r12d, ebx\nloc_1291:\ncmp r12d, 1\njz loc_1504\ncmp r12d, 2\njz loc_144B\nlea ebp, [r12-2]\nxor r15d, r15d\nmov [rsp+68h+var_5C], r12d\nmov eax, r14d\nmov r12d, r13d\nmov ebx, r15d\nmov r14d, ebp\nloc_12BE:\ncmp r14d, 1\njz loc_14ED\ncmp r14d, 2\njz loc_142C\nlea r15d, [r14-2]\nxor r13d, r13d\nmov edx, r14d\nmov ecx, eax\nmov esi, r15d\nmov r14d, r13d\nmov r15d, r12d\nloc_12E7:\ncmp esi, 1\njz loc_14D9\ncmp esi, 2\njz loc_1410\nxor r12d, r12d\nlea r13d, [rsi-2]\nmov r8d, r14d\nmov r9d, r12d\nmov r12d, ebx\nmov ebx, r13d\nloc_130C:\ncmp ebx, 1\njz loc_14B9\ncmp ebx, 2\njz loc_13F7\nlea r14d, [rbx-2]\nxor r10d, r10d\nmov ebp, r14d\nloc_1328:\ncmp ebp, 1\njz loc_14AE\ncmp ebp, 2\njz loc_13E5\nlea r14d, [rbp-2]\nmov r11d, ebp\nxor r13d, r13d\nmov ebp, ebx\nmov ebx, r14d\nloc_1349:\ncmp ebx, 1\njz loc_14A0\ncmp ebx, 2\njz short loc_13D0\nlea edi, [rbx-2]\nxor r14d, r14d\nloc_135D:\nmov [rsp+68h+var_3C], ecx\nmov [rsp+68h+var_40], r11d\nmov [rsp+68h+var_44], r10d\nmov [rsp+68h+var_48], edx\nmov [rsp+68h+var_4C], r9d\nmov [rsp+68h+var_50], r8d\nmov [rsp+68h+var_54], esi\nmov [rsp+68h+var_58], edi\ncall func0\nmov edi, [rsp+68h+var_58]\nmov esi, [rsp+68h+var_54]\nadd r14d, eax\nmov r8d, [rsp+68h+var_50]\nmov r9d, [rsp+68h+var_4C]\ncmp edi, 1\nmov edx, [rsp+68h+var_48]\nmov r10d, [rsp+68h+var_44]\nmov r11d, [rsp+68h+var_40]\nmov ecx, [rsp+68h+var_3C]\njz loc_14D0\ncmp edi, 2\njz short loc_13C4\nsub edi, 3\njnz short loc_135D\nadd r14d, 2\nloc_13C4:\nadd r13d, r14d\nsub ebx, 3\njnz loc_1349\nloc_13D0:\nmov ebx, ebp\nadd r13d, 2\nmov ebp, r11d\nloc_13D9:\nadd r10d, r13d\nsub ebp, 3\njnz loc_1328\nloc_13E5:\nmov ebp, r10d\nadd ebp, 2\nloc_13EB:\nadd r9d, ebp\nsub ebx, 3\njnz loc_130C\nloc_13F7:\nmov ebx, r12d\nmov r12d, r9d\nmov r14d, r8d\nadd r12d, 2\nloc_1404:\nadd r14d, r12d\nsub esi, 3\njnz loc_12E7\nloc_1410:\nmov r13d, r14d\nmov r12d, r15d\nmov r14d, edx\nmov eax, ecx\nadd r13d, 2\nloc_141F:\nadd ebx, r13d\nsub r14d, 3\njnz loc_12BE\nloc_142C:\nmov r13d, r12d\nmov r15d, ebx\nmov r12d, [rsp+68h+var_5C]\nmov r14d, eax\nadd r15d, 2\nloc_143E:\nadd r13d, r15d\nsub r12d, 3\njnz loc_1291\nloc_144B:\nmov ebp, r13d\nmov r15d, [rsp+68h+var_64]\nmov r12d, [rsp+68h+var_60]\nmov r13d, r14d\nadd ebp, 2\nloc_145E:\nadd r15d, ebp\nsub r12d, 3\njnz loc_1263\nloc_146B:\nmov ebp, [rsp+68h+var_68]\nmov ebx, r13d\nadd r15d, 2\nloc_1475:\nadd ebp, r15d\nsub ebx, 3\njnz loc_1244\nloc_1481:\nmov r13d, ebp\nadd r13d, 2\nloc_1488:\nadd rsp, 38h\nmov eax, r13d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14A0:\nmov ebx, ebp\nadd r13d, 3\nmov ebp, r11d\njmp loc_13D9\nloc_14AE:\nmov ebp, r10d\nadd ebp, 3\njmp loc_13EB\nloc_14B9:\nmov ebx, r12d\nmov r12d, r9d\nmov r14d, r8d\nadd r12d, 3\njmp loc_1404\nloc_14D0:\nadd r14d, 3\njmp loc_13C4\nloc_14D9:\nmov r13d, r14d\nmov r12d, r15d\nmov r14d, edx\nmov eax, ecx\nadd r13d, 3\njmp loc_141F\nloc_14ED:\nmov r15d, ebx\nmov r13d, r12d\nmov r14d, eax\nmov r12d, [rsp+68h+var_5C]\nadd r15d, 3\njmp loc_143E\nloc_1504:\nmov ebp, r13d\nmov r15d, [rsp+68h+var_64]\nmov r12d, [rsp+68h+var_60]\nmov r13d, r14d\nadd ebp, 3\njmp loc_145E\nloc_151C:\nmov ebp, [rsp+68h+var_68]\nmov ebx, r13d\nadd r15d, 3\njmp loc_1475\nloc_152B:\nmov r13d, ebp\nadd r13d, 3\njmp loc_1488\nloc_1537:\nmov r13d, 3\njmp loc_1488\nloc_1542:\nxor r13d, r13d\njmp loc_1488", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1)\n{\n unsigned int v1; // r13d\n unsigned int v2; // ebx\n int v3; // ebp\n unsigned int v4; // r12d\n int v5; // r15d\n unsigned int v6; // r13d\n unsigned int v7; // r14d\n int v8; // r13d\n unsigned int v9; // r12d\n unsigned int v10; // ebp\n unsigned int v11; // eax\n int v12; // r12d\n int v13; // ebx\n unsigned int v14; // r14d\n unsigned int v15; // edx\n unsigned int v16; // ecx\n unsigned int v17; // esi\n int v18; // r14d\n int v19; // r15d\n int v20; // r8d\n int v21; // r9d\n int v22; // r12d\n unsigned int v23; // ebx\n int v24; // r10d\n int v25; // ebp\n int v26; // r14d\n int v27; // r11d\n int v28; // r13d\n int v29; // ebp\n int v30; // ebx\n int v31; // edi\n int v32; // r14d\n int v33; // r13d\n int v34; // ebp\n int v35; // ebp\n int v36; // r14d\n int v37; // r12d\n int v38; // r13d\n unsigned int v39; // r14d\n int v40; // r13d\n int v41; // r13d\n unsigned int v42; // r12d\n int v43; // r15d\n int v44; // ebp\n int v45; // r15d\n unsigned int v46; // r12d\n int v47; // ebp\n int v48; // ebp\n unsigned int v49; // ebx\n int v50; // r15d\n int v52; // r13d\n int v53; // ebp\n int v54; // [rsp+0h] [rbp-68h]\n int v55; // [rsp+4h] [rbp-64h]\n unsigned int v56; // [rsp+8h] [rbp-60h]\n unsigned int v57; // [rsp+Ch] [rbp-5Ch]\n int v58; // [rsp+18h] [rbp-50h]\n int v59; // [rsp+1Ch] [rbp-4Ch]\n unsigned int v60; // [rsp+20h] [rbp-48h]\n int v61; // [rsp+24h] [rbp-44h]\n int v62; // [rsp+28h] [rbp-40h]\n unsigned int v63; // [rsp+2Ch] [rbp-3Ch]\n\n if ( a1 )\n {\n v1 = a1;\n if ( a1 == 1 )\n {\n return 0;\n }\n else if ( a1 != 2 )\n {\n v2 = a1 - 2;\n v3 = 0;\n while ( v2 != 1 )\n {\n if ( v2 != 2 )\n {\n v54 = v3;\n v4 = v2 - 2;\n v5 = 0;\n v6 = v2;\n while ( v4 != 1 )\n {\n if ( v4 != 2 )\n {\n v55 = v5;\n v7 = v6;\n v56 = v4;\n v8 = 0;\n v9 = v4 - 2;\n while ( v9 != 1 )\n {\n if ( v9 != 2 )\n {\n v10 = v9 - 2;\n v57 = v9;\n v11 = v7;\n v12 = v8;\n v13 = 0;\n v14 = v10;\n while ( v14 != 1 )\n {\n if ( v14 != 2 )\n {\n v15 = v14;\n v16 = v11;\n v17 = v14 - 2;\n v18 = 0;\n v19 = v12;\n while ( v17 != 1 )\n {\n if ( v17 != 2 )\n {\n v20 = v18;\n v21 = 0;\n v22 = v13;\n v23 = v17 - 2;\n while ( v23 != 1 )\n {\n if ( v23 != 2 )\n {\n v24 = 0;\n v25 = v23 - 2;\n while ( v25 != 1 )\n {\n if ( v25 != 2 )\n {\n v26 = v25 - 2;\n v27 = v25;\n v28 = 0;\n v29 = v23;\n v30 = v26;\n while ( v30 != 1 )\n {\n if ( v30 != 2 )\n {\n v31 = v30 - 2;\n v32 = 0;\n while ( 1 )\n {\n v63 = v16;\n v62 = v27;\n v61 = v24;\n v60 = v15;\n v59 = v21;\n v58 = v20;\n v32 += func0();\n v20 = v58;\n v21 = v59;\n v15 = v60;\n v24 = v61;\n v27 = v62;\n v16 = v63;\n if ( v31 == 1 )\n break;\n if ( v31 == 2 )\n goto LABEL_33;\n v31 -= 3;\n if ( !v31 )\n {\n v32 += 2;\n goto LABEL_33;\n }\n }\n v32 += 3;\nLABEL_33:\n v28 += v32;\n v30 -= 3;\n if ( v30 )\n continue;\n }\n v23 = v29;\n v33 = v28 + 2;\n v34 = v27;\n goto LABEL_35;\n }\n v23 = v29;\n v33 = v28 + 3;\n v34 = v27;\nLABEL_35:\n v24 += v33;\n v25 = v34 - 3;\n if ( v25 )\n continue;\n }\n v35 = v24 + 2;\n goto LABEL_37;\n }\n v35 = v24 + 3;\nLABEL_37:\n v21 += v35;\n v23 -= 3;\n if ( v23 )\n continue;\n }\n v13 = v22;\n v36 = v20;\n v37 = v21 + 2;\n goto LABEL_39;\n }\n v13 = v22;\n v36 = v20;\n v37 = v21 + 3;\nLABEL_39:\n v18 = v37 + v36;\n v17 -= 3;\n if ( v17 )\n continue;\n }\n v38 = v18;\n v12 = v19;\n v39 = v15;\n v11 = v16;\n v40 = v38 + 2;\n goto LABEL_41;\n }\n v52 = v18;\n v12 = v19;\n v39 = v15;\n v11 = v16;\n v40 = v52 + 3;\nLABEL_41:\n v13 += v40;\n v14 = v39 - 3;\n if ( v14 )\n continue;\n }\n v41 = v12;\n v42 = v57;\n v7 = v11;\n v43 = v13 + 2;\n goto LABEL_43;\n }\n v41 = v12;\n v7 = v11;\n v42 = v57;\n v43 = v13 + 3;\nLABEL_43:\n v8 = v43 + v41;\n v9 = v42 - 3;\n if ( v9 )\n continue;\n }\n v44 = v8;\n v45 = v55;\n v46 = v56;\n v6 = v7;\n v47 = v44 + 2;\n goto LABEL_45;\n }\n v53 = v8;\n v45 = v55;\n v46 = v56;\n v6 = v7;\n v47 = v53 + 3;\nLABEL_45:\n v5 = v47 + v45;\n v4 = v46 - 3;\n if ( v4 )\n continue;\n }\n v48 = v54;\n v49 = v6;\n v50 = v5 + 2;\n goto LABEL_47;\n }\n v48 = v54;\n v49 = v6;\n v50 = v5 + 3;\nLABEL_47:\n v3 = v50 + v48;\n v2 = v49 - 3;\n if ( v2 )\n continue;\n }\n return (unsigned int)(v3 + 2);\n }\n return (unsigned int)(v3 + 3);\n }\n }\n else\n {\n return 3;\n }\n return v1;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 38h\ntest edi, edi\njz loc_1537\nmov r13d, edi\ncmp edi, 1\njz loc_1542\ncmp edi, 2\njz loc_1488\nlea ebx, [rdi-2]\nxor ebp, ebp\nloc_1244:\ncmp ebx, 1\njz loc_152B\ncmp ebx, 2\njz loc_1481\nmov [rsp+68h+var_68], ebp\nlea r12d, [rbx-2]\nxor r15d, r15d\nmov r13d, ebx\nloc_1263:\ncmp r12d, 1\njz loc_151C\ncmp r12d, 2\njz loc_146B\nmov [rsp+68h+var_64], r15d\nlea ebx, [r12-2]\nxor ebp, ebp\nmov r14d, r13d\nmov [rsp+68h+var_60], r12d\nmov r13d, ebp\nmov r12d, ebx\nloc_1291:\ncmp r12d, 1\njz loc_1504\ncmp r12d, 2\njz loc_144B\nlea ebp, [r12-2]\nxor r15d, r15d\nmov [rsp+68h+var_5C], r12d\nmov eax, r14d\nmov r12d, r13d\nmov ebx, r15d\nmov r14d, ebp\nloc_12BE:\ncmp r14d, 1\njz loc_14ED\ncmp r14d, 2\njz loc_142C\nlea r15d, [r14-2]\nxor r13d, r13d\nmov edx, r14d\nmov ecx, eax\nmov esi, r15d\nmov r14d, r13d\nmov r15d, r12d\nloc_12E7:\ncmp esi, 1\njz loc_14D9\ncmp esi, 2\njz loc_1410\nxor r12d, r12d\nlea r13d, [rsi-2]\nmov r8d, r14d\nmov r9d, r12d\nmov r12d, ebx\nmov ebx, r13d\nloc_130C:\ncmp ebx, 1\njz loc_14B9\ncmp ebx, 2\njz loc_13F7\nlea r14d, [rbx-2]\nxor r10d, r10d\nmov ebp, r14d\nloc_1328:\ncmp ebp, 1\njz loc_14AE\ncmp ebp, 2\njz loc_13E5\nlea r14d, [rbp-2]\nmov r11d, ebp\nxor r13d, r13d\nmov ebp, ebx\nmov ebx, r14d\nloc_1349:\ncmp ebx, 1\njz loc_14A0\ncmp ebx, 2\njz short loc_13D0\nlea edi, [rbx-2]\nxor r14d, r14d\nloc_135D:\nmov [rsp+68h+var_3C], ecx\nmov [rsp+68h+var_40], r11d\nmov [rsp+68h+var_44], r10d\nmov [rsp+68h+var_48], edx\nmov [rsp+68h+var_4C], r9d\nmov [rsp+68h+var_50], r8d\nmov [rsp+68h+var_54], esi\nmov [rsp+68h+var_58], edi\ncall sub_1210\nmov edi, [rsp+68h+var_58]\nmov esi, [rsp+68h+var_54]\nadd r14d, eax\nmov r8d, [rsp+68h+var_50]\nmov r9d, [rsp+68h+var_4C]\ncmp edi, 1\nmov edx, [rsp+68h+var_48]\nmov r10d, [rsp+68h+var_44]\nmov r11d, [rsp+68h+var_40]\nmov ecx, [rsp+68h+var_3C]\njz loc_14D0\ncmp edi, 2\njz short loc_13C4\nsub edi, 3\njnz short loc_135D\nadd r14d, 2\nloc_13C4:\nadd r13d, r14d\nsub ebx, 3\njnz loc_1349\nloc_13D0:\nmov ebx, ebp\nadd r13d, 2\nmov ebp, r11d\nloc_13D9:\nadd r10d, r13d\nsub ebp, 3\njnz loc_1328\nloc_13E5:\nmov ebp, r10d\nadd ebp, 2\nloc_13EB:\nadd r9d, ebp\nsub ebx, 3\njnz loc_130C\nloc_13F7:\nmov ebx, r12d\nmov r12d, r9d\nmov r14d, r8d\nadd r12d, 2\nloc_1404:\nadd r14d, r12d\nsub esi, 3\njnz loc_12E7\nloc_1410:\nmov r13d, r14d\nmov r12d, r15d\nmov r14d, edx\nmov eax, ecx\nadd r13d, 2\nloc_141F:\nadd ebx, r13d\nsub r14d, 3\njnz loc_12BE\nloc_142C:\nmov r13d, r12d\nmov r15d, ebx\nmov r12d, [rsp+68h+var_5C]\nmov r14d, eax\nadd r15d, 2\nloc_143E:\nadd r13d, r15d\nsub r12d, 3\njnz loc_1291\nloc_144B:\nmov ebp, r13d\nmov r15d, [rsp+68h+var_64]\nmov r12d, [rsp+68h+var_60]\nmov r13d, r14d\nadd ebp, 2\nloc_145E:\nadd r15d, ebp\nsub r12d, 3\njnz loc_1263\nloc_146B:\nmov ebp, [rsp+68h+var_68]\nmov ebx, r13d\nadd r15d, 2\nloc_1475:\nadd ebp, r15d\nsub ebx, 3\njnz loc_1244\nloc_1481:\nmov r13d, ebp\nadd r13d, 2\nloc_1488:\nadd rsp, 38h\nmov eax, r13d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14A0:\nmov ebx, ebp\nadd r13d, 3\nmov ebp, r11d\njmp loc_13D9\nloc_14AE:\nmov ebp, r10d\nadd ebp, 3\njmp loc_13EB\nloc_14B9:\nmov ebx, r12d\nmov r12d, r9d\nmov r14d, r8d\nadd r12d, 3\njmp loc_1404\nloc_14D0:\nadd r14d, 3\njmp loc_13C4\nloc_14D9:\nmov r13d, r14d\nmov r12d, r15d\nmov r14d, edx\nmov eax, ecx\nadd r13d, 3\njmp loc_141F\nloc_14ED:\nmov r15d, ebx\nmov r13d, r12d\nmov r14d, eax\nmov r12d, [rsp+68h+var_5C]\nadd r15d, 3\njmp loc_143E\nloc_1504:\nmov ebp, r13d\nmov r15d, [rsp+68h+var_64]\nmov r12d, [rsp+68h+var_60]\nmov r13d, r14d\nadd ebp, 3\njmp loc_145E\nloc_151C:\nmov ebp, [rsp+68h+var_68]\nmov ebx, r13d\nadd r15d, 3\njmp loc_1475\nloc_152B:\nmov r13d, ebp\nadd r13d, 3\njmp loc_1488\nloc_1537:\nmov r13d, 3\njmp loc_1488\nloc_1542:\nxor r13d, r13d\njmp loc_1488", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(unsigned int a1)\n{\n unsigned int v1; // r13d\n unsigned int v2; // ebx\n int v3; // ebp\n unsigned int v4; // r12d\n int v5; // r15d\n unsigned int v6; // r13d\n unsigned int v7; // r14d\n int v8; // r13d\n unsigned int v9; // r12d\n unsigned int v10; // ebp\n unsigned int v11; // eax\n int v12; // r12d\n int v13; // ebx\n unsigned int v14; // r14d\n unsigned int v15; // edx\n unsigned int v16; // ecx\n unsigned int v17; // esi\n int v18; // r14d\n int v19; // r15d\n int v20; // r8d\n int v21; // r9d\n int v22; // r12d\n unsigned int v23; // ebx\n int v24; // r10d\n int v25; // ebp\n int v26; // r14d\n int v27; // r11d\n int v28; // r13d\n int v29; // ebp\n int v30; // ebx\n int v31; // edi\n int v32; // r14d\n int v33; // r13d\n int v34; // ebp\n int v35; // ebp\n int v36; // r14d\n int v37; // r12d\n int v38; // r13d\n unsigned int v39; // r14d\n int v40; // r13d\n int v41; // r13d\n unsigned int v42; // r12d\n int v43; // r15d\n int v44; // ebp\n int v45; // r15d\n unsigned int v46; // r12d\n int v47; // ebp\n int v48; // ebp\n unsigned int v49; // ebx\n int v50; // r15d\n int v52; // r13d\n int v53; // ebp\n int v54; // [rsp+0h] [rbp-68h]\n int v55; // [rsp+4h] [rbp-64h]\n unsigned int v56; // [rsp+8h] [rbp-60h]\n unsigned int v57; // [rsp+Ch] [rbp-5Ch]\n int v58; // [rsp+18h] [rbp-50h]\n int v59; // [rsp+1Ch] [rbp-4Ch]\n unsigned int v60; // [rsp+20h] [rbp-48h]\n int v61; // [rsp+24h] [rbp-44h]\n int v62; // [rsp+28h] [rbp-40h]\n unsigned int v63; // [rsp+2Ch] [rbp-3Ch]\n\n if ( a1 )\n {\n v1 = a1;\n if ( a1 == 1 )\n {\n return 0;\n }\n else if ( a1 != 2 )\n {\n v2 = a1 - 2;\n v3 = 0;\n while ( v2 != 1 )\n {\n if ( v2 != 2 )\n {\n v54 = v3;\n v4 = v2 - 2;\n v5 = 0;\n v6 = v2;\n while ( v4 != 1 )\n {\n if ( v4 != 2 )\n {\n v55 = v5;\n v7 = v6;\n v56 = v4;\n v8 = 0;\n v9 = v4 - 2;\n while ( v9 != 1 )\n {\n if ( v9 != 2 )\n {\n v10 = v9 - 2;\n v57 = v9;\n v11 = v7;\n v12 = v8;\n v13 = 0;\n v14 = v10;\n while ( v14 != 1 )\n {\n if ( v14 != 2 )\n {\n v15 = v14;\n v16 = v11;\n v17 = v14 - 2;\n v18 = 0;\n v19 = v12;\n while ( v17 != 1 )\n {\n if ( v17 != 2 )\n {\n v20 = v18;\n v21 = 0;\n v22 = v13;\n v23 = v17 - 2;\n while ( v23 != 1 )\n {\n if ( v23 != 2 )\n {\n v24 = 0;\n v25 = v23 - 2;\n while ( v25 != 1 )\n {\n if ( v25 != 2 )\n {\n v26 = v25 - 2;\n v27 = v25;\n v28 = 0;\n v29 = v23;\n v30 = v26;\n while ( v30 != 1 )\n {\n if ( v30 != 2 )\n {\n v31 = v30 - 2;\n v32 = 0;\n while ( 1 )\n {\n v63 = v16;\n v62 = v27;\n v61 = v24;\n v60 = v15;\n v59 = v21;\n v58 = v20;\n v32 += sub_1210();\n v20 = v58;\n v21 = v59;\n v15 = v60;\n v24 = v61;\n v27 = v62;\n v16 = v63;\n if ( v31 == 1 )\n break;\n if ( v31 == 2 )\n goto LABEL_33;\n v31 -= 3;\n if ( !v31 )\n {\n v32 += 2;\n goto LABEL_33;\n }\n }\n v32 += 3;\nLABEL_33:\n v28 += v32;\n v30 -= 3;\n if ( v30 )\n continue;\n }\n v23 = v29;\n v33 = v28 + 2;\n v34 = v27;\n goto LABEL_35;\n }\n v23 = v29;\n v33 = v28 + 3;\n v34 = v27;\nLABEL_35:\n v24 += v33;\n v25 = v34 - 3;\n if ( v25 )\n continue;\n }\n v35 = v24 + 2;\n goto LABEL_37;\n }\n v35 = v24 + 3;\nLABEL_37:\n v21 += v35;\n v23 -= 3;\n if ( v23 )\n continue;\n }\n v13 = v22;\n v36 = v20;\n v37 = v21 + 2;\n goto LABEL_39;\n }\n v13 = v22;\n v36 = v20;\n v37 = v21 + 3;\nLABEL_39:\n v18 = v37 + v36;\n v17 -= 3;\n if ( v17 )\n continue;\n }\n v38 = v18;\n v12 = v19;\n v39 = v15;\n v11 = v16;\n v40 = v38 + 2;\n goto LABEL_41;\n }\n v52 = v18;\n v12 = v19;\n v39 = v15;\n v11 = v16;\n v40 = v52 + 3;\nLABEL_41:\n v13 += v40;\n v14 = v39 - 3;\n if ( v14 )\n continue;\n }\n v41 = v12;\n v42 = v57;\n v7 = v11;\n v43 = v13 + 2;\n goto LABEL_43;\n }\n v41 = v12;\n v7 = v11;\n v42 = v57;\n v43 = v13 + 3;\nLABEL_43:\n v8 = v43 + v41;\n v9 = v42 - 3;\n if ( v9 )\n continue;\n }\n v44 = v8;\n v45 = v55;\n v46 = v56;\n v6 = v7;\n v47 = v44 + 2;\n goto LABEL_45;\n }\n v53 = v8;\n v45 = v55;\n v46 = v56;\n v6 = v7;\n v47 = v53 + 3;\nLABEL_45:\n v5 = v47 + v45;\n v4 = v46 - 3;\n if ( v4 )\n continue;\n }\n v48 = v54;\n v49 = v6;\n v50 = v5 + 2;\n goto LABEL_47;\n }\n v48 = v54;\n v49 = v6;\n v50 = v5 + 3;\nLABEL_47:\n v3 = v50 + v48;\n v2 = v49 - 3;\n if ( v2 )\n continue;\n }\n return (unsigned int)(v3 + 2);\n }\n return (unsigned int)(v3 + 3);\n }\n }\n else\n {\n return 3;\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(unsigned int a1) {\n unsigned int v1;\n unsigned int v2;\n int v3;\n unsigned int v4;\n int v5;\n unsigned int v6;\n unsigned int v7;\n int v8;\n unsigned int v9;\n unsigned int v10;\n unsigned int v11;\n int v12;\n int v13;\n unsigned int v14;\n unsigned int v15;\n unsigned int v16;\n unsigned int v17;\n int v18;\n int v19;\n int v20;\n int v21;\n int v22;\n unsigned int v23;\n int v24;\n int v25;\n int v26;\n int v27;\n int v28;\n int v29;\n int v30;\n int v31;\n int v32;\n int v33;\n int v34;\n int v35;\n int v36;\n int v37;\n int v38;\n unsigned int v39;\n int v40;\n int v41;\n unsigned int v42;\n int v43;\n int v44;\n int v45;\n unsigned int v46;\n int v47;\n int v48;\n unsigned int v49;\n int v50;\n int v52;\n int v53;\n int v54;\n int v55;\n unsigned int v56;\n unsigned int v57;\n int v58;\n int v59;\n unsigned int v60;\n int v61;\n int v62;\n unsigned int v63;\n if (a1) {\n v1 = a1;\n if (a1 == 1) {\n return 0;\n } else if (a1 != 2) {\n v2 = a1 - 2;\n v3 = 0;\n while (v2 != 1) {\n if (v2 != 2) {\n v54 = v3;\n v4 = v2 - 2;\n v5 = 0;\n v6 = v2;\n while (v4 != 1) {\n if (v4 != 2) {\n v55 = v5;\n v7 = v6;\n v56 = v4;\n v8 = 0;\n v9 = v4 - 2;\n while (v9 != 1) {\n if (v9 != 2) {\n v10 = v9 - 2;\n v57 = v9;\n v11 = v7;\n v12 = v8;\n v13 = 0;\n v14 = v10;\n while (v14 != 1) {\n if (v14 != 2) {\n v15 = v14;\n v16 = v11;\n v17 = v14 - 2;\n v18 = 0;\n v19 = v12;\n while (v17 != 1) {\n if (v17 != 2) {\n v20 = v18;\n v21 = 0;\n v22 = v13;\n v23 = v17 - 2;\n while (v23 != 1) {\n if (v23 != 2) {\n v24 = 0;\n v25 = v23 - 2;\n while (v25 != 1) {\n if (v25 != 2) {\n v26 = v25 - 2;\n v27 = v25;\n v28 = 0;\n v29 = v23;\n v30 = v26;\n while (v30 != 1) {\n if (v30 != 2) {\n v31 = v30 - 2;\n v32 = 0;\n while (1) {\n v63 = v16;\n v62 = v27;\n v61 = v24;\n v60 = v15;\n v59 = v21;\n v58 = v20;\n v32 += sub_1210();\n v20 = v58;\n v21 = v59;\n v15 = v60;\n v24 = v61;\n v27 = v62;\n v16 = v63;\n if (v31 == 1) break;\n if (v31 == 2) goto LABEL_33;\n v31 -= 3;\n if (!v31) {\n v32 += 2;\n goto LABEL_33;\n }\n }\n v32 += 3;\n LABEL_33:\n v28 += v32;\n v30 -= 3;\n if (v30) continue;\n }\n v23 = v29;\n v33 = v28 + 2;\n v34 = v27;\n goto LABEL_35;\n }\n v23 = v29;\n v33 = v28 + 3;\n v34 = v27;\n LABEL_35:\n v24 += v33;\n v25 = v34 - 3;\n if (v25) continue;\n }\n v35 = v24 + 2;\n goto LABEL_37;\n }\n v35 = v24 + 3;\n LABEL_37:\n v21 += v35;\n v23 -= 3;\n if (v23) continue;\n }\n v13 = v22;\n v36 = v20;\n v37 = v21 + 2;\n goto LABEL_39;\n }\n v13 = v22;\n v36 = v20;\n v37 = v21 + 3;\n LABEL_39:\n v18 = v37 + v36;\n v17 -= 3;\n if (v17) continue;\n }\n v38 = v18;\n v12 = v19;\n v39 = v15;\n v11 = v16;\n v40 = v38 + 2;\n goto LABEL_41;\n }\n v52 = v18;\n v12 = v19;\n v39 = v15;\n v11 = v16;\n v40 = v52 + 3;\n LABEL_41:\n v13 += v40;\n v14 = v39 - 3;\n if (v14) continue;\n }\n v41 = v12;\n v42 = v57;\n v7 = v11;\n v43 = v13 + 2;\n goto LABEL_43;\n }\n v41 = v12;\n v7 = v11;\n v42 = v57;\n v43 = v13 + 3;\n LABEL_43:\n v8 = v43 + v41;\n v9 = v42 - 3;\n if (v9) continue;\n }\n v44 = v8;\n v45 = v55;\n v46 = v56;\n v6 = v7;\n v47 = v44 + 2;\n goto LABEL_45;\n }\n v53 = v8;\n v45 = v55;\n v46 = v56;\n v6 = v7;\n v47 = v53 + 3;\n LABEL_45:\n v5 = v47 + v45;\n v4 = v46 - 3;\n if (v4) continue;\n }\n v48 = v54;\n v49 = v6;\n v50 = v5 + 2;\n goto LABEL_47;\n }\n v48 = v54;\n v49 = v6;\n v50 = v5 + 3;\n LABEL_47:\n v3 = v50 + v48;\n v2 = v49 - 3;\n if (v2) continue;\n }\n return (unsigned int)(v3 + 2);\n }\n return (unsigned int)(v3 + 3);\n }\n } else {\n return 3;\n }\n return v1;\n}", + "ida_pseudo_norm": "long long func0(unsigned int a1) {\n unsigned int v1;\n unsigned int v2;\n int v3;\n unsigned int v4;\n int v5;\n unsigned int v6;\n unsigned int v7;\n int v8;\n unsigned int v9;\n unsigned int v10;\n unsigned int v11;\n int v12;\n int v13;\n unsigned int v14;\n unsigned int v15;\n unsigned int v16;\n unsigned int v17;\n int v18;\n int v19;\n int v20;\n int v21;\n int v22;\n unsigned int v23;\n int v24;\n int v25;\n int v26;\n int v27;\n int v28;\n int v29;\n int v30;\n int v31;\n int v32;\n int v33;\n int v34;\n int v35;\n int v36;\n int v37;\n int v38;\n unsigned int v39;\n int v40;\n int v41;\n unsigned int v42;\n int v43;\n int v44;\n int v45;\n unsigned int v46;\n int v47;\n int v48;\n unsigned int v49;\n int v50;\n int v52;\n int v53;\n int v54;\n int v55;\n unsigned int v56;\n unsigned int v57;\n int v58;\n int v59;\n unsigned int v60;\n int v61;\n int v62;\n unsigned int v63;\n if (a1) {\n v1 = a1;\n if (a1 == 1) {\n return 0;\n } else if (a1 != 2) {\n v2 = a1 - 2;\n v3 = 0;\n while (v2 != 1) {\n if (v2 != 2) {\n v54 = v3;\n v4 = v2 - 2;\n v5 = 0;\n v6 = v2;\n while (v4 != 1) {\n if (v4 != 2) {\n v55 = v5;\n v7 = v6;\n v56 = v4;\n v8 = 0;\n v9 = v4 - 2;\n while (v9 != 1) {\n if (v9 != 2) {\n v10 = v9 - 2;\n v57 = v9;\n v11 = v7;\n v12 = v8;\n v13 = 0;\n v14 = v10;\n while (v14 != 1) {\n if (v14 != 2) {\n v15 = v14;\n v16 = v11;\n v17 = v14 - 2;\n v18 = 0;\n v19 = v12;\n while (v17 != 1) {\n if (v17 != 2) {\n v20 = v18;\n v21 = 0;\n v22 = v13;\n v23 = v17 - 2;\n while (v23 != 1) {\n if (v23 != 2) {\n v24 = 0;\n v25 = v23 - 2;\n while (v25 != 1) {\n if (v25 != 2) {\n v26 = v25 - 2;\n v27 = v25;\n v28 = 0;\n v29 = v23;\n v30 = v26;\n while (v30 != 1) {\n if (v30 != 2) {\n v31 = v30 - 2;\n v32 = 0;\n while (1) {\n v63 = v16;\n v62 = v27;\n v61 = v24;\n v60 = v15;\n v59 = v21;\n v58 = v20;\n v32 += func0();\n v20 = v58;\n v21 = v59;\n v15 = v60;\n v24 = v61;\n v27 = v62;\n v16 = v63;\n if (v31 == 1) break;\n if (v31 == 2) goto LABEL_33;\n v31 -= 3;\n if (!v31) {\n v32 += 2;\n goto LABEL_33;\n }\n }\n v32 += 3;\n LABEL_33:\n v28 += v32;\n v30 -= 3;\n if (v30) continue;\n }\n v23 = v29;\n v33 = v28 + 2;\n v34 = v27;\n goto LABEL_35;\n }\n v23 = v29;\n v33 = v28 + 3;\n v34 = v27;\n LABEL_35:\n v24 += v33;\n v25 = v34 - 3;\n if (v25) continue;\n }\n v35 = v24 + 2;\n goto LABEL_37;\n }\n v35 = v24 + 3;\n LABEL_37:\n v21 += v35;\n v23 -= 3;\n if (v23) continue;\n }\n v13 = v22;\n v36 = v20;\n v37 = v21 + 2;\n goto LABEL_39;\n }\n v13 = v22;\n v36 = v20;\n v37 = v21 + 3;\n LABEL_39:\n v18 = v37 + v36;\n v17 -= 3;\n if (v17) continue;\n }\n v38 = v18;\n v12 = v19;\n v39 = v15;\n v11 = v16;\n v40 = v38 + 2;\n goto LABEL_41;\n }\n v52 = v18;\n v12 = v19;\n v39 = v15;\n v11 = v16;\n v40 = v52 + 3;\n LABEL_41:\n v13 += v40;\n v14 = v39 - 3;\n if (v14) continue;\n }\n v41 = v12;\n v42 = v57;\n v7 = v11;\n v43 = v13 + 2;\n goto LABEL_43;\n }\n v41 = v12;\n v7 = v11;\n v42 = v57;\n v43 = v13 + 3;\n LABEL_43:\n v8 = v43 + v41;\n v9 = v42 - 3;\n if (v9) continue;\n }\n v44 = v8;\n v45 = v55;\n v46 = v56;\n v6 = v7;\n v47 = v44 + 2;\n goto LABEL_45;\n }\n v53 = v8;\n v45 = v55;\n v46 = v56;\n v6 = v7;\n v47 = v53 + 3;\n LABEL_45:\n v5 = v47 + v45;\n v4 = v46 - 3;\n if (v4) continue;\n }\n v48 = v54;\n v49 = v6;\n v50 = v5 + 2;\n goto LABEL_47;\n }\n v48 = v54;\n v49 = v6;\n v50 = v5 + 3;\n LABEL_47:\n v3 = v50 + v48;\n v2 = v49 - 3;\n if (v2) continue;\n }\n return (unsigned int)(v3 + 2);\n }\n return (unsigned int)(v3 + 3);\n }\n } else {\n return 3;\n }\n return v1;\n}" + }, + { + "index": 386, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *s) {\n int count_left = 0;\n int count_right = 0;\n int swap = 0;\n int imbalance = 0;\n int i;\n for (i = 0; i < strlen(s); i++) {\n if (s[i] == '[') {\n count_left++;\n if (imbalance > 0) {\n swap += imbalance;\n imbalance--;\n }\n } else if (s[i] == ']') {\n count_right++;\n imbalance = count_right - count_left;\n }\n }\n return swap;\n}", + "test": "int main() {\n\n assert(func0(\"[]][][\") == 2);\n\n assert(func0(\"[[][]]\") == 0);\n\n assert(func0(\"[[][]]][\") == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x38,%rsp\nmov %rdi,-0x38(%rbp)\nmovl $0x0,-0x24(%rbp)\nmovl $0x0,-0x20(%rbp)\nmovl $0x0,-0x1c(%rbp)\nmovl $0x0,-0x18(%rbp)\nmovl $0x0,-0x14(%rbp)\njmp 11ee \nmov -0x14(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x5b,%al\njne 11c9 \naddl $0x1,-0x24(%rbp)\ncmpl $0x0,-0x18(%rbp)\njle 11ea \nmov -0x18(%rbp),%eax\nadd %eax,-0x1c(%rbp)\nsubl $0x1,-0x18(%rbp)\njmp 11ea \nmov -0x14(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x5d,%al\njne 11ea \naddl $0x1,-0x20(%rbp)\nmov -0x20(%rbp),%eax\nsub -0x24(%rbp),%eax\nmov %eax,-0x18(%rbp)\naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\nmovslq %eax,%rbx\nmov -0x38(%rbp),%rax\nmov %rax,%rdi\ncallq 1060 \ncmp %rax,%rbx\njb 119f \nmov -0x1c(%rbp),%eax\nadd $0x38,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+s], rdi\nmov [rbp+var_24], 0\nmov [rbp+var_20], 0\nmov [rbp+var_1C], 0\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp short loc_11EE\nloc_119F:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 5Bh ; '['\njnz short loc_11C9\nadd [rbp+var_24], 1\ncmp [rbp+var_18], 0\njle short loc_11EA\nmov eax, [rbp+var_18]\nadd [rbp+var_1C], eax\nsub [rbp+var_18], 1\njmp short loc_11EA\nloc_11C9:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 5Dh ; ']'\njnz short loc_11EA\nadd [rbp+var_20], 1\nmov eax, [rbp+var_20]\nsub eax, [rbp+var_24]\nmov [rbp+var_18], eax\nloc_11EA:\nadd [rbp+var_14], 1\nloc_11EE:\nmov eax, [rbp+var_14]\nmovsxd rbx, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rbx, rax\njb short loc_119F\nmov eax, [rbp+var_1C]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v2; // [rsp+1Ch] [rbp-24h]\n int v3; // [rsp+20h] [rbp-20h]\n unsigned int v4; // [rsp+24h] [rbp-1Ch]\n int v5; // [rsp+28h] [rbp-18h]\n int i; // [rsp+2Ch] [rbp-14h]\n\n v2 = 0;\n v3 = 0;\n v4 = 0;\n v5 = 0;\n for ( i = 0; i < strlen(a1); ++i )\n {\n if ( a1[i] == 91 )\n {\n ++v2;\n if ( v5 > 0 )\n v4 += v5--;\n }\n else if ( a1[i] == 93 )\n {\n v5 = ++v3 - v2;\n }\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+s], rdi\nmov [rbp+var_24], 0\nmov [rbp+var_20], 0\nmov [rbp+var_1C], 0\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp short loc_11EE\nloc_119F:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 5Bh ; '['\njnz short loc_11C9\nadd [rbp+var_24], 1\ncmp [rbp+var_18], 0\njle short loc_11EA\nmov eax, [rbp+var_18]\nadd [rbp+var_1C], eax\nsub [rbp+var_18], 1\njmp short loc_11EA\nloc_11C9:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 5Dh ; ']'\njnz short loc_11EA\nadd [rbp+var_20], 1\nmov eax, [rbp+var_20]\nsub eax, [rbp+var_24]\nmov [rbp+var_18], eax\nloc_11EA:\nadd [rbp+var_14], 1\nloc_11EE:\nmov eax, [rbp+var_14]\nmovsxd rbx, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rbx, rax\njb short loc_119F\nmov eax, [rbp+var_1C]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1)\n{\n int v2; // [rsp+1Ch] [rbp-24h]\n int v3; // [rsp+20h] [rbp-20h]\n unsigned int v4; // [rsp+24h] [rbp-1Ch]\n int v5; // [rsp+28h] [rbp-18h]\n int i; // [rsp+2Ch] [rbp-14h]\n\n v2 = 0;\n v3 = 0;\n v4 = 0;\n v5 = 0;\n for ( i = 0; i < strlen(a1); ++i )\n {\n if ( a1[i] == 91 )\n {\n ++v2;\n if ( v5 > 0 )\n v4 += v5--;\n }\n else if ( a1[i] == 93 )\n {\n v5 = ++v3 - v2;\n }\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1) {\n int v2;\n int v3;\n unsigned int v4;\n int v5;\n int i;\n v2 = 0;\n v3 = 0;\n v4 = 0;\n v5 = 0;\n for (i = 0; i < strlen(a1); ++i) {\n if (a1[i] == 91) {\n ++v2;\n if (v5 > 0) v4 += v5--;\n } else if (a1[i] == 93) {\n v5 = ++v3 - v2;\n }\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v2;\n int v3;\n unsigned int v4;\n int v5;\n int i;\n v2 = 0;\n v3 = 0;\n v4 = 0;\n v5 = 0;\n for (i = 0; i < strlen(a1); ++i) {\n if (a1[i] == 91) {\n ++v2;\n if (v5 > 0) v4 += v5--;\n } else if (a1[i] == 93) {\n v5 = ++v3 - v2;\n }\n }\n return v4;\n}" + }, + { + "index": 386, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *s) {\n int count_left = 0;\n int count_right = 0;\n int swap = 0;\n int imbalance = 0;\n int i;\n for (i = 0; i < strlen(s); i++) {\n if (s[i] == '[') {\n count_left++;\n if (imbalance > 0) {\n swap += imbalance;\n imbalance--;\n }\n } else if (s[i] == ']') {\n count_right++;\n imbalance = count_right - count_left;\n }\n }\n return swap;\n}", + "test": "int main() {\n\n assert(func0(\"[]][][\") == 2);\n\n assert(func0(\"[[][]]\") == 0);\n\n assert(func0(\"[[][]]][\") == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%rsi\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nmov %rsi,%rdx\nlea -0x1(%rsi,%rcx,1),%rsi\nmov $0x0,%ecx\nmov $0x0,%r9d\nmov $0x0,%r8d\nmov $0x0,%edi\njmp 1192 \nadd $0x1,%edi\ntest %ecx,%ecx\njle 118e \nadd %ecx,%r9d\nsub $0x1,%ecx\nadd $0x1,%rdx\ncmp %rsi,%rdx\nje 11ad \nmovzbl (%rdx),%eax\ncmp $0x5b,%al\nje 1181 \ncmp $0x5d,%al\njne 118e \nadd $0x1,%r8d\nmov %r8d,%ecx\nsub %edi,%ecx\njmp 118e \nmov %r9d,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmov rdi, rax\nmov rax, rbx\nadd rdi, rbx\nmov ecx, 0\nmov r9d, 0\nmov r8d, 0\nmov esi, 0\njmp short loc_11A8\nloc_1197:\nadd esi, 1\ntest ecx, ecx\njle short loc_11A4\nadd r9d, ecx\nsub ecx, 1\nloc_11A4:\nadd rax, 1\nloc_11A8:\ncmp rax, rdi\njz short loc_11C5\nmovzx edx, byte ptr [rax]\ncmp dl, 5Bh ; '['\njz short loc_1197\ncmp dl, 5Dh ; ']'\njnz short loc_11A4\nadd r8d, 1\nmov ecx, r8d\nsub ecx, esi\njmp short loc_11A4\nloc_11C5:\nmov eax, r9d\npop rbx\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n size_t v2; // rdi\n const char *v3; // rax\n const char *v4; // rdi\n int v5; // ecx\n unsigned int v6; // r9d\n int v7; // r8d\n int v8; // esi\n\n v2 = strlen(a1);\n v3 = a1;\n v4 = &a1[v2];\n v5 = 0;\n v6 = 0;\n v7 = 0;\n v8 = 0;\n while ( v3 != v4 )\n {\n if ( *v3 == 91 )\n {\n ++v8;\n if ( v5 > 0 )\n v6 += v5--;\n }\n else if ( *v3 == 93 )\n {\n v5 = ++v7 - v8;\n }\n ++v3;\n }\n return v6;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmov rdi, rax\nmov rax, rbx\nadd rdi, rbx\nmov ecx, 0\nmov r9d, 0\nmov r8d, 0\nmov esi, 0\njmp short loc_11A8\nloc_1197:\nadd esi, 1\ntest ecx, ecx\njle short loc_11A4\nadd r9d, ecx\nsub ecx, 1\nloc_11A4:\nadd rax, 1\nloc_11A8:\ncmp rax, rdi\njz short loc_11C5\nmovzx edx, byte ptr [rax]\ncmp dl, 5Bh ; '['\njz short loc_1197\ncmp dl, 5Dh ; ']'\njnz short loc_11A4\nadd r8d, 1\nmov ecx, r8d\nsub ecx, esi\njmp short loc_11A4\nloc_11C5:\nmov eax, r9d\npop rbx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1)\n{\n size_t v2; // rdi\n const char *v3; // rax\n const char *v4; // rdi\n int v5; // ecx\n unsigned int v6; // r9d\n int v7; // r8d\n int v8; // esi\n\n v2 = strlen(a1);\n v3 = a1;\n v4 = &a1[v2];\n v5 = 0;\n v6 = 0;\n v7 = 0;\n v8 = 0;\n while ( v3 != v4 )\n {\n if ( *v3 == 91 )\n {\n ++v8;\n if ( v5 > 0 )\n v6 += v5--;\n }\n else if ( *v3 == 93 )\n {\n v5 = ++v7 - v8;\n }\n ++v3;\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1) {\n unsigned int v2;\n const char *v3;\n const char *v4;\n int v5;\n unsigned int v6;\n int v7;\n int v8;\n v2 = strlen(a1);\n v3 = a1;\n v4 = &a1[v2];\n v5 = 0;\n v6 = 0;\n v7 = 0;\n v8 = 0;\n while (v3 != v4) {\n if (*v3 == 91) {\n ++v8;\n if (v5 > 0) v6 += v5--;\n } else if (*v3 == 93) {\n v5 = ++v7 - v8;\n }\n ++v3;\n }\n return v6;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n unsigned int v2;\n const char *v3;\n const char *v4;\n int v5;\n unsigned int v6;\n int v7;\n int v8;\n v2 = strlen(a1);\n v3 = a1;\n v4 = &a1[v2];\n v5 = 0;\n v6 = 0;\n v7 = 0;\n v8 = 0;\n while (v3 != v4) {\n if (*v3 == 91) {\n ++v8;\n if (v5 > 0) v6 += v5--;\n } else if (*v3 == 93) {\n v5 = ++v7 - v8;\n }\n ++v3;\n }\n return v6;\n}" + }, + { + "index": 386, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *s) {\n int count_left = 0;\n int count_right = 0;\n int swap = 0;\n int imbalance = 0;\n int i;\n for (i = 0; i < strlen(s); i++) {\n if (s[i] == '[') {\n count_left++;\n if (imbalance > 0) {\n swap += imbalance;\n imbalance--;\n }\n } else if (s[i] == ']') {\n count_right++;\n imbalance = count_right - count_left;\n }\n }\n return swap;\n}", + "test": "int main() {\n\n assert(func0(\"[]][][\") == 2);\n\n assert(func0(\"[[][]]\") == 0);\n\n assert(func0(\"[[][]]][\") == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\ncallq 1060 \nmov %rbx,%rdi\nxor %ecx,%ecx\nxor %r9d,%r9d\nadd %rbx,%rax\nxor %r8d,%r8d\nxor %esi,%esi\njmp 1242 \ncmp $0x5d,%dl\njne 123e \nadd $0x1,%r8d\nmov %r8d,%ecx\nsub %esi,%ecx\nadd $0x1,%rdi\ncmp %rdi,%rax\nje 1260 \nmovzbl (%rdi),%edx\ncmp $0x5b,%dl\njne 1230 \nadd $0x1,%esi\ntest %ecx,%ecx\njle 123e \nadd %ecx,%r9d\nsub $0x1,%ecx\njmp 123e \nxchg %ax,%ax\nmov %r9d,%eax\npop %rbx\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest rax, rax\njz short loc_1278\nmov rdi, rbx\nadd rax, rbx\nxor ecx, ecx\nxor r9d, r9d\nxor r8d, r8d\nxor esi, esi\njmp short loc_124F\nloc_1238:\ncmp dl, 5Dh ; ']'\njnz short loc_1246\nadd r8d, 1\nmov ecx, r8d\nsub ecx, esi\nloc_1246:\nadd rdi, 1\ncmp rax, rdi\njz short loc_126D\nloc_124F:\nmovzx edx, byte ptr [rdi]\ncmp dl, 5Bh ; '['\njnz short loc_1238\nadd esi, 1\ntest ecx, ecx\njle short loc_1246\nadd rdi, 1\nadd r9d, ecx\nsub ecx, 1\ncmp rax, rdi\njnz short loc_124F\nloc_126D:\nmov eax, r9d\npop rbx\nretn\nloc_1278:\nxor r9d, r9d\npop rbx\nmov eax, r9d\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n size_t v1; // rax\n const char *v2; // rax\n int v3; // ecx\n unsigned int v4; // r9d\n int v5; // r8d\n int v6; // esi\n\n v1 = strlen(a1);\n if ( v1 )\n {\n v2 = &a1[v1];\n v3 = 0;\n v4 = 0;\n v5 = 0;\n v6 = 0;\n while ( *a1 == 91 )\n {\n ++v6;\n if ( v3 <= 0 )\n {\nLABEL_5:\n if ( v2 == ++a1 )\n return v4;\n }\n else\n {\n ++a1;\n v4 += v3--;\n if ( v2 == a1 )\n return v4;\n }\n }\n if ( *a1 == 93 )\n v3 = ++v5 - v6;\n goto LABEL_5;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest rax, rax\njz short loc_1278\nmov rdi, rbx\nadd rax, rbx\nxor ecx, ecx\nxor r9d, r9d\nxor r8d, r8d\nxor esi, esi\njmp short loc_124F\nloc_1238:\ncmp dl, 5Dh ; ']'\njnz short loc_1246\nadd r8d, 1\nmov ecx, r8d\nsub ecx, esi\nloc_1246:\nadd rdi, 1\ncmp rax, rdi\njz short loc_126D\nloc_124F:\nmovzx edx, byte ptr [rdi]\ncmp dl, 5Bh ; '['\njnz short loc_1238\nadd esi, 1\ntest ecx, ecx\njle short loc_1246\nadd rdi, 1\nadd r9d, ecx\nsub ecx, 1\ncmp rax, rdi\njnz short loc_124F\nloc_126D:\nmov eax, r9d\npop rbx\nretn\nloc_1278:\nxor r9d, r9d\npop rbx\nmov eax, r9d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(const char *a1)\n{\n size_t v1; // rax\n const char *v2; // rax\n int v3; // ecx\n unsigned int v4; // r9d\n int v5; // r8d\n int v6; // esi\n\n v1 = strlen(a1);\n if ( v1 )\n {\n v2 = &a1[v1];\n v3 = 0;\n v4 = 0;\n v5 = 0;\n v6 = 0;\n while ( *a1 == 91 )\n {\n ++v6;\n if ( v3 <= 0 )\n {\nLABEL_5:\n if ( v2 == ++a1 )\n return v4;\n }\n else\n {\n ++a1;\n v4 += v3--;\n if ( v2 == a1 )\n return v4;\n }\n }\n if ( *a1 == 93 )\n v3 = ++v5 - v6;\n goto LABEL_5;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(const char *a1) {\n unsigned int v1;\n const char *v2;\n int v3;\n unsigned int v4;\n int v5;\n int v6;\n v1 = strlen(a1);\n if (v1) {\n v2 = &a1[v1];\n v3 = 0;\n v4 = 0;\n v5 = 0;\n v6 = 0;\n while (*a1 == 91) {\n ++v6;\n if (v3 <= 0) {\n LABEL_5:\n if (v2 == ++a1) return v4;\n } else {\n ++a1;\n v4 += v3--;\n if (v2 == a1) return v4;\n }\n }\n if (*a1 == 93) v3 = ++v5 - v6;\n goto LABEL_5;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n unsigned int v1;\n const char *v2;\n int v3;\n unsigned int v4;\n int v5;\n int v6;\n v1 = strlen(a1);\n if (v1) {\n v2 = &a1[v1];\n v3 = 0;\n v4 = 0;\n v5 = 0;\n v6 = 0;\n while (*a1 == 91) {\n ++v6;\n if (v3 <= 0) {\n LABEL_5:\n if (v2 == ++a1) return v4;\n } else {\n ++a1;\n v4 += v3--;\n if (v2 == a1) return v4;\n }\n }\n if (*a1 == 93) v3 = ++v5 - v6;\n goto LABEL_5;\n }\n return 0LL;\n}" + }, + { + "index": 386, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *s) {\n int count_left = 0;\n int count_right = 0;\n int swap = 0;\n int imbalance = 0;\n int i;\n for (i = 0; i < strlen(s); i++) {\n if (s[i] == '[') {\n count_left++;\n if (imbalance > 0) {\n swap += imbalance;\n imbalance--;\n }\n } else if (s[i] == ']') {\n count_right++;\n imbalance = count_right - count_left;\n }\n }\n return swap;\n}", + "test": "int main() {\n\n assert(func0(\"[]][][\") == 2);\n\n assert(func0(\"[[][]]\") == 0);\n\n assert(func0(\"[[][]]][\") == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\ncallq 1060 \ntest %rax,%rax\nje 1270 \nmov %rbx,%rdi\nlea (%rbx,%rax,1),%rdx\nxor %ecx,%ecx\nxor %r9d,%r9d\nxor %r8d,%r8d\nxor %esi,%esi\njmp 124e \nnopl (%rax)\ncmp $0x5d,%al\njne 1245 \nadd $0x1,%r8d\nmov %r8d,%ecx\nsub %esi,%ecx\nadd $0x1,%rdi\ncmp %rdi,%rdx\nje 126b \nmovzbl (%rdi),%eax\ncmp $0x5b,%al\njne 1238 \nadd $0x1,%esi\ntest %ecx,%ecx\njle 1245 \nadd $0x1,%rdi\nadd %ecx,%r9d\nsub $0x1,%ecx\ncmp %rdi,%rdx\njne 124e \nmov %r9d,%eax\npop %rbx\nretq\nxor %r9d,%r9d\npop %rbx\nmov %r9d,%eax\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest rax, rax\njz short loc_1278\nmov rdi, rbx\nadd rax, rbx\nxor ecx, ecx\nxor r9d, r9d\nxor r8d, r8d\nxor esi, esi\njmp short loc_124F\nloc_1238:\ncmp dl, 5Dh ; ']'\njnz short loc_1246\nadd r8d, 1\nmov ecx, r8d\nsub ecx, esi\nloc_1246:\nadd rdi, 1\ncmp rax, rdi\njz short loc_126D\nloc_124F:\nmovzx edx, byte ptr [rdi]\ncmp dl, 5Bh ; '['\njnz short loc_1238\nadd esi, 1\ntest ecx, ecx\njle short loc_1246\nadd rdi, 1\nadd r9d, ecx\nsub ecx, 1\ncmp rax, rdi\njnz short loc_124F\nloc_126D:\nmov eax, r9d\npop rbx\nretn\nloc_1278:\nxor r9d, r9d\npop rbx\nmov eax, r9d\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n size_t v1; // rax\n const char *v2; // rax\n int v3; // ecx\n unsigned int v4; // r9d\n int v5; // r8d\n int v6; // esi\n\n v1 = strlen(a1);\n if ( v1 )\n {\n v2 = &a1[v1];\n v3 = 0;\n v4 = 0;\n v5 = 0;\n v6 = 0;\n while ( *a1 == 91 )\n {\n ++v6;\n if ( v3 <= 0 )\n {\nLABEL_5:\n if ( v2 == ++a1 )\n return v4;\n }\n else\n {\n ++a1;\n v4 += v3--;\n if ( v2 == a1 )\n return v4;\n }\n }\n if ( *a1 == 93 )\n v3 = ++v5 - v6;\n goto LABEL_5;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest rax, rax\njz short loc_1278\nmov rdi, rbx\nadd rax, rbx\nxor ecx, ecx\nxor r9d, r9d\nxor r8d, r8d\nxor esi, esi\njmp short loc_124F\nloc_1238:\ncmp dl, 5Dh ; ']'\njnz short loc_1246\nadd r8d, 1\nmov ecx, r8d\nsub ecx, esi\nloc_1246:\nadd rdi, 1\ncmp rax, rdi\njz short loc_126D\nloc_124F:\nmovzx edx, byte ptr [rdi]\ncmp dl, 5Bh ; '['\njnz short loc_1238\nadd esi, 1\ntest ecx, ecx\njle short loc_1246\nadd rdi, 1\nadd r9d, ecx\nsub ecx, 1\ncmp rax, rdi\njnz short loc_124F\nloc_126D:\nmov eax, r9d\npop rbx\nretn\nloc_1278:\nxor r9d, r9d\npop rbx\nmov eax, r9d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(const char *a1)\n{\n size_t v1; // rax\n const char *v2; // rax\n int v3; // ecx\n unsigned int v4; // r9d\n int v5; // r8d\n int v6; // esi\n\n v1 = strlen(a1);\n if ( v1 )\n {\n v2 = &a1[v1];\n v3 = 0;\n v4 = 0;\n v5 = 0;\n v6 = 0;\n while ( *a1 == 91 )\n {\n ++v6;\n if ( v3 <= 0 )\n {\nLABEL_5:\n if ( v2 == ++a1 )\n return v4;\n }\n else\n {\n ++a1;\n v4 += v3--;\n if ( v2 == a1 )\n return v4;\n }\n }\n if ( *a1 == 93 )\n v3 = ++v5 - v6;\n goto LABEL_5;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(const char *a1) {\n unsigned int v1;\n const char *v2;\n int v3;\n unsigned int v4;\n int v5;\n int v6;\n v1 = strlen(a1);\n if (v1) {\n v2 = &a1[v1];\n v3 = 0;\n v4 = 0;\n v5 = 0;\n v6 = 0;\n while (*a1 == 91) {\n ++v6;\n if (v3 <= 0) {\n LABEL_5:\n if (v2 == ++a1) return v4;\n } else {\n ++a1;\n v4 += v3--;\n if (v2 == a1) return v4;\n }\n }\n if (*a1 == 93) v3 = ++v5 - v6;\n goto LABEL_5;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n unsigned int v1;\n const char *v2;\n int v3;\n unsigned int v4;\n int v5;\n int v6;\n v1 = strlen(a1);\n if (v1) {\n v2 = &a1[v1];\n v3 = 0;\n v4 = 0;\n v5 = 0;\n v6 = 0;\n while (*a1 == 91) {\n ++v6;\n if (v3 <= 0) {\n LABEL_5:\n if (v2 == ++a1) return v4;\n } else {\n ++a1;\n v4 += v3--;\n if (v2 == a1) return v4;\n }\n }\n if (*a1 == 93) v3 = ++v5 - v6;\n goto LABEL_5;\n }\n return 0LL;\n}" + }, + { + "index": 387, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* N) {\n int l = strlen(N);\n if (N[l - 1] == '0' || N[l - 1] == '2' ||\n N[l - 1] == '4' || N[l - 1] == '6' ||\n N[l - 1] == '8' || N[l - 1] == 'A' ||\n N[l - 1] == 'C' || N[l - 1] == 'E') {\n return \"Even\";\n } else {\n return \"Odd\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"AB3454D\"), \"Odd\") == 0);\n\n assert(strcmp(func0(\"ABC\"), \"Even\") == 0);\n\n assert(strcmp(func0(\"AAD\"), \"Odd\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov -0x18(%rbp),%rax\nmov %rax,%rdi\ncallq 1070 \nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncltq\nlea -0x1(%rax),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x30,%al\nje 1268 \nmov -0x4(%rbp),%eax\ncltq\nlea -0x1(%rax),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x32,%al\nje 1268 \nmov -0x4(%rbp),%eax\ncltq\nlea -0x1(%rax),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x34,%al\nje 1268 \nmov -0x4(%rbp),%eax\ncltq\nlea -0x1(%rax),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x36,%al\nje 1268 \nmov -0x4(%rbp),%eax\ncltq\nlea -0x1(%rax),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x38,%al\nje 1268 \nmov -0x4(%rbp),%eax\ncltq\nlea -0x1(%rax),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x41,%al\nje 1268 \nmov -0x4(%rbp),%eax\ncltq\nlea -0x1(%rax),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x43,%al\nje 1268 \nmov -0x4(%rbp),%eax\ncltq\nlea -0x1(%rax),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x45,%al\njne 1271 \nlea 0xd99(%rip),%rax\njmp 1278 \nlea 0xd95(%rip),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 30h ; '0'\njz loc_1268\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 32h ; '2'\njz loc_1268\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 34h ; '4'\njz short loc_1268\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 36h ; '6'\njz short loc_1268\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 38h ; '8'\njz short loc_1268\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 41h ; 'A'\njz short loc_1268\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 43h ; 'C'\njz short loc_1268\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 45h ; 'E'\njnz short loc_1271\nloc_1268:\nlea rax, aEven; \"Even\"\njmp short locret_1278\nloc_1271:\nlea rax, s2; \"Odd\"\nlocret_1278:\nleave\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n int v2; // [rsp+1Ch] [rbp-4h]\n\n v2 = strlen(a1);\n if ( a1[v2 - 1] == 48\n || a1[v2 - 1] == 50\n || a1[v2 - 1] == 52\n || a1[v2 - 1] == 54\n || a1[v2 - 1] == 56\n || a1[v2 - 1] == 65\n || a1[v2 - 1] == 67\n || a1[v2 - 1] == 69 )\n {\n return \"Even\";\n }\n else\n {\n return \"Odd\";\n }\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 30h ; '0'\njz loc_1268\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 32h ; '2'\njz loc_1268\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 34h ; '4'\njz short loc_1268\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 36h ; '6'\njz short loc_1268\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 38h ; '8'\njz short loc_1268\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 41h ; 'A'\njz short loc_1268\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 43h ; 'C'\njz short loc_1268\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 45h ; 'E'\njnz short loc_1271\nloc_1268:\nlea rax, aEven; \"Even\"\njmp short locret_1278\nloc_1271:\nlea rax, s2; \"Odd\"\nlocret_1278:\nleave\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1189(const char *a1)\n{\n int v2; // [rsp+1Ch] [rbp-4h]\n\n v2 = strlen(a1);\n if ( a1[v2 - 1] == 48\n || a1[v2 - 1] == 50\n || a1[v2 - 1] == 52\n || a1[v2 - 1] == 54\n || a1[v2 - 1] == 56\n || a1[v2 - 1] == 65\n || a1[v2 - 1] == 67\n || a1[v2 - 1] == 69 )\n {\n return \"Even\";\n }\n else\n {\n return \"Odd\";\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1189(const char *a1) {\n int v2;\n v2 = strlen(a1);\n if (a1[v2 - 1] == 48 || a1[v2 - 1] == 50 || a1[v2 - 1] == 52 ||\n a1[v2 - 1] == 54 || a1[v2 - 1] == 56 || a1[v2 - 1] == 65 ||\n a1[v2 - 1] == 67 || a1[v2 - 1] == 69) {\n return \"Even\";\n } else {\n return \"Odd\";\n }\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n int v2;\n v2 = strlen(a1);\n if (a1[v2 - 1] == 48 || a1[v2 - 1] == 50 || a1[v2 - 1] == 52 ||\n a1[v2 - 1] == 54 || a1[v2 - 1] == 56 || a1[v2 - 1] == 65 ||\n a1[v2 - 1] == 67 || a1[v2 - 1] == 69) {\n return \"Even\";\n } else {\n return \"Odd\";\n }\n}" + }, + { + "index": 387, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* N) {\n int l = strlen(N);\n if (N[l - 1] == '0' || N[l - 1] == '2' ||\n N[l - 1] == '4' || N[l - 1] == '6' ||\n N[l - 1] == '8' || N[l - 1] == 'A' ||\n N[l - 1] == 'C' || N[l - 1] == 'E') {\n return \"Even\";\n } else {\n return \"Odd\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"AB3454D\"), \"Odd\") == 0);\n\n assert(strcmp(func0(\"ABC\"), \"Even\") == 0);\n\n assert(strcmp(func0(\"AAD\"), \"Odd\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%rdx\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nsub $0x1,%rax\ncltq\nmovzbl -0x1(%rdx,%rax,1),%ecx\nsub $0x30,%ecx\nlea 0xe8b(%rip),%rax\ncmp $0x15,%cl\nja 119a \nmov $0x2a0155,%eax\nshr %cl,%rax\ntest $0x1,%al\nlea 0xe79(%rip),%rax\nlea 0xe6e(%rip),%rdx\ncmove %rdx,%rax\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ncdqe\nmovzx eax, byte ptr [rbx+rax-1]\nsub eax, 30h ; '0'\nlea rdx, s2; \"Odd\"\ncmp al, 15h\nja short loc_11C6\nmov edx, 2A0155h\nbt rdx, rax\nlea rdx, aEven; \"Even\"\nlea rax, s2; \"Odd\"\ncmovnb rdx, rax\nloc_11C6:\nmov rax, rdx\npop rbx\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n unsigned __int64 v1; // rax\n const char *v2; // rdx\n __int64 v3; // rdx\n unsigned __int8 v4; // cf\n\n v1 = (unsigned int)(unsigned __int8)a1[(int)strlen(a1) - 1] - 48;\n v2 = \"Odd\";\n if ( (unsigned __int8)v1 <= 0x15u )\n {\n v3 = 2752853LL;\n v4 = _bittest64(&v3, v1);\n v2 = \"Even\";\n if ( !v4 )\n return \"Odd\";\n }\n return v2;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ncdqe\nmovzx eax, byte ptr [rbx+rax-1]\nsub eax, 30h ; '0'\nlea rdx, s2; \"Odd\"\ncmp al, 15h\nja short loc_11C6\nmov edx, 2A0155h\nbt rdx, rax\nlea rdx, aEven; \"Even\"\nlea rax, s2; \"Odd\"\ncmovnb rdx, rax\nloc_11C6:\nmov rax, rdx\npop rbx\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1189(const char *a1)\n{\n unsigned __int64 v1; // rax\n const char *v2; // rdx\n __int64 v3; // rdx\n unsigned __int8 v4; // cf\n\n v1 = (unsigned int)(unsigned __int8)a1[(int)strlen(a1) - 1] - 48;\n v2 = \"Odd\";\n if ( (unsigned __int8)v1 <= 0x15u )\n {\n v3 = 2752853LL;\n v4 = _bittest64(&v3, v1);\n v2 = \"Even\";\n if ( !v4 )\n return \"Odd\";\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1189(const char *a1) {\n unsigned long long v1;\n const char *v2;\n long long v3;\n unsigned char v4;\n v1 = (unsigned int)(unsigned char)a1[(int)strlen(a1) - 1] - 48;\n v2 = \"Odd\";\n if ((unsigned char)v1 <= 21u) {\n v3 = 2752853LL;\n v4 = _bittest64(&v3, v1);\n v2 = \"Even\";\n if (!v4) return \"Odd\";\n }\n return v2;\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n unsigned long long v1;\n const char *v2;\n long long v3;\n unsigned char v4;\n v1 = (unsigned int)(unsigned char)a1[(int)strlen(a1) - 1] - 48;\n v2 = \"Odd\";\n if ((unsigned char)v1 <= 21u) {\n v3 = 2752853LL;\n v4 = _bittest64(&v3, v1);\n v2 = \"Even\";\n if (!v4) return \"Odd\";\n }\n return v2;\n}" + }, + { + "index": 387, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* N) {\n int l = strlen(N);\n if (N[l - 1] == '0' || N[l - 1] == '2' ||\n N[l - 1] == '4' || N[l - 1] == '6' ||\n N[l - 1] == '8' || N[l - 1] == 'A' ||\n N[l - 1] == 'C' || N[l - 1] == 'E') {\n return \"Even\";\n } else {\n return \"Odd\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"AB3454D\"), \"Odd\") == 0);\n\n assert(strcmp(func0(\"ABC\"), \"Even\") == 0);\n\n assert(strcmp(func0(\"AAD\"), \"Odd\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\ncallq 1060 \ncltq\nmovzbl -0x1(%rbx,%rax,1),%ecx\nlea 0xd99(%rip),%rax\nsub $0x30,%ecx\ncmp $0x15,%cl\nja 1289 \nmov $0x2a0155,%edx\nshr %cl,%rdx\nand $0x1,%edx\nlea 0xd83(%rip),%rdx\ncmovne %rdx,%rax\npop %rbx\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nlea rdx, s2; \"Odd\"\ncdqe\nmovzx eax, byte ptr [rbx+rax-1]\nsub eax, 30h ; '0'\ncmp al, 15h\nja short loc_1296\nmov ecx, 2A0155h\nbt rcx, rax\nlea rax, aEven; \"Even\"\ncmovb rdx, rax\nloc_1296:\nmov rax, rdx\npop rbx\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n int v1; // eax\n const char *v2; // rdx\n unsigned __int64 v3; // rax\n __int64 v4; // rcx\n\n v1 = strlen(a1);\n v2 = \"Odd\";\n v3 = (unsigned int)(unsigned __int8)a1[v1 - 1] - 48;\n if ( (unsigned __int8)v3 <= 0x15u )\n {\n v4 = 2752853LL;\n if ( _bittest64(&v4, v3) )\n return \"Even\";\n }\n return v2;\n}", + "ida_strip_asm": "sub_1260:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nlea rdx, s2; \"Odd\"\ncdqe\nmovzx eax, byte ptr [rbx+rax-1]\nsub eax, 30h ; '0'\ncmp al, 15h\nja short loc_1296\nmov ecx, 2A0155h\nbt rcx, rax\nlea rax, aEven; \"Even\"\ncmovb rdx, rax\nloc_1296:\nmov rax, rdx\npop rbx\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1260(const char *a1)\n{\n int v1; // eax\n const char *v2; // rdx\n unsigned __int64 v3; // rax\n __int64 v4; // rcx\n\n v1 = strlen(a1);\n v2 = \"Odd\";\n v3 = (unsigned int)(unsigned __int8)a1[v1 - 1] - 48;\n if ( (unsigned __int8)v3 <= 0x15u )\n {\n v4 = 2752853LL;\n if ( _bittest64(&v4, v3) )\n return \"Even\";\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1260(const char *a1) {\n int v1;\n const char *v2;\n unsigned long long v3;\n long long v4;\n v1 = strlen(a1);\n v2 = \"Odd\";\n v3 = (unsigned int)(unsigned char)a1[v1 - 1] - 48;\n if ((unsigned char)v3 <= 21u) {\n v4 = 2752853LL;\n if (_bittest64(&v4, v3)) return \"Even\";\n }\n return v2;\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n int v1;\n const char *v2;\n unsigned long long v3;\n long long v4;\n v1 = strlen(a1);\n v2 = \"Odd\";\n v3 = (unsigned int)(unsigned char)a1[v1 - 1] - 48;\n if ((unsigned char)v3 <= 21u) {\n v4 = 2752853LL;\n if (_bittest64(&v4, v3)) return \"Even\";\n }\n return v2;\n}" + }, + { + "index": 387, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* N) {\n int l = strlen(N);\n if (N[l - 1] == '0' || N[l - 1] == '2' ||\n N[l - 1] == '4' || N[l - 1] == '6' ||\n N[l - 1] == '8' || N[l - 1] == 'A' ||\n N[l - 1] == 'C' || N[l - 1] == 'E') {\n return \"Even\";\n } else {\n return \"Odd\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"AB3454D\"), \"Odd\") == 0);\n\n assert(strcmp(func0(\"ABC\"), \"Even\") == 0);\n\n assert(strcmp(func0(\"AAD\"), \"Odd\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\ncallq 1060 \ncltq\nmovzbl -0x1(%rbx,%rax,1),%ecx\nlea 0xd99(%rip),%rax\nsub $0x30,%ecx\ncmp $0x15,%cl\nja 1289 \nmov $0x2a0155,%edx\nshr %cl,%rdx\nand $0x1,%edx\nlea 0xd83(%rip),%rdx\ncmovne %rdx,%rax\npop %rbx\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nlea rdx, s2; \"Odd\"\ncdqe\nmovzx eax, byte ptr [rbx+rax-1]\nsub eax, 30h ; '0'\ncmp al, 15h\nja short loc_1296\nmov ecx, 2A0155h\nbt rcx, rax\nlea rax, aEven; \"Even\"\ncmovb rdx, rax\nloc_1296:\nmov rax, rdx\npop rbx\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n int v1; // eax\n const char *v2; // rdx\n unsigned __int64 v3; // rax\n __int64 v4; // rcx\n\n v1 = strlen(a1);\n v2 = \"Odd\";\n v3 = (unsigned int)(unsigned __int8)a1[v1 - 1] - 48;\n if ( (unsigned __int8)v3 <= 0x15u )\n {\n v4 = 2752853LL;\n if ( _bittest64(&v4, v3) )\n return \"Even\";\n }\n return v2;\n}", + "ida_strip_asm": "sub_1260:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nlea rdx, s2; \"Odd\"\ncdqe\nmovzx eax, byte ptr [rbx+rax-1]\nsub eax, 30h ; '0'\ncmp al, 15h\nja short loc_1296\nmov ecx, 2A0155h\nbt rcx, rax\nlea rax, aEven; \"Even\"\ncmovb rdx, rax\nloc_1296:\nmov rax, rdx\npop rbx\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1260(const char *a1)\n{\n int v1; // eax\n const char *v2; // rdx\n unsigned __int64 v3; // rax\n __int64 v4; // rcx\n\n v1 = strlen(a1);\n v2 = \"Odd\";\n v3 = (unsigned int)(unsigned __int8)a1[v1 - 1] - 48;\n if ( (unsigned __int8)v3 <= 0x15u )\n {\n v4 = 2752853LL;\n if ( _bittest64(&v4, v3) )\n return \"Even\";\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1260(const char *a1) {\n int v1;\n const char *v2;\n unsigned long long v3;\n long long v4;\n v1 = strlen(a1);\n v2 = \"Odd\";\n v3 = (unsigned int)(unsigned char)a1[v1 - 1] - 48;\n if ((unsigned char)v3 <= 21u) {\n v4 = 2752853LL;\n if (_bittest64(&v4, v3)) return \"Even\";\n }\n return v2;\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n int v1;\n const char *v2;\n unsigned long long v3;\n long long v4;\n v1 = strlen(a1);\n v2 = \"Odd\";\n v3 = (unsigned int)(unsigned char)a1[v1 - 1] - 48;\n if ((unsigned char)v3 <= 21u) {\n v4 = 2752853LL;\n if (_bittest64(&v4, v3)) return \"Even\";\n }\n return v2;\n}" + }, + { + "index": 388, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int res = 0;\n for (int i = n; i > 0; --i) {\n if ((i & (i - 1)) == 0) {\n res = i;\n break;\n }\n }\n return res;\n}", + "test": "int main() {\n\n assert(func0(10) == 8);\n\n assert(func0(19) == 16);\n\n assert(func0(32) == 32);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmovl $0x0,-0x8(%rbp)\nmov -0x14(%rbp),%eax\nmov %eax,-0x4(%rbp)\njmp 117c \nmov -0x4(%rbp),%eax\nsub $0x1,%eax\nand -0x4(%rbp),%eax\ntest %eax,%eax\njne 1178 \nmov -0x4(%rbp),%eax\nmov %eax,-0x8(%rbp)\njmp 1182 \nsubl $0x1,-0x4(%rbp)\ncmpl $0x0,-0x4(%rbp)\njg 1163 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_8], 0\nmov eax, [rbp+var_14]\nmov [rbp+var_4], eax\njmp short loc_117C\nloc_1163:\nmov eax, [rbp+var_4]\nsub eax, 1\nand eax, [rbp+var_4]\ntest eax, eax\njnz short loc_1178\nmov eax, [rbp+var_4]\nmov [rbp+var_8], eax\njmp short loc_1182\nloc_1178:\nsub [rbp+var_4], 1\nloc_117C:\ncmp [rbp+var_4], 0\njg short loc_1163\nloc_1182:\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v2; // [rsp+Ch] [rbp-8h]\n\n v2 = 0;\n while ( a1 > 0 )\n {\n if ( (a1 & (a1 - 1)) == 0 )\n return (unsigned int)a1;\n --a1;\n }\n return v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_8], 0\nmov eax, [rbp+var_14]\nmov [rbp+var_4], eax\njmp short loc_117C\nloc_1163:\nmov eax, [rbp+var_4]\nsub eax, 1\nand eax, [rbp+var_4]\ntest eax, eax\njnz short loc_1178\nmov eax, [rbp+var_4]\nmov [rbp+var_8], eax\njmp short loc_1182\nloc_1178:\nsub [rbp+var_4], 1\nloc_117C:\ncmp [rbp+var_4], 0\njg short loc_1163\nloc_1182:\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n unsigned int v2; // [rsp+Ch] [rbp-8h]\n\n v2 = 0;\n while ( a1 > 0 )\n {\n if ( (a1 & (a1 - 1)) == 0 )\n return (unsigned int)a1;\n --a1;\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n unsigned int v2;\n v2 = 0;\n while (a1 > 0) {\n if ((a1 & (a1 - 1)) == 0) return (unsigned int)a1;\n --a1;\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v2;\n v2 = 0;\n while (a1 > 0) {\n if ((a1 & (a1 - 1)) == 0) return (unsigned int)a1;\n --a1;\n }\n return v2;\n}" + }, + { + "index": 388, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int res = 0;\n for (int i = n; i > 0; --i) {\n if ((i & (i - 1)) == 0) {\n res = i;\n break;\n }\n }\n return res;\n}", + "test": "int main() {\n\n assert(func0(10) == 8);\n\n assert(func0(19) == 16);\n\n assert(func0(32) == 32);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\njle 115c \nlea -0x1(%rdi),%eax\ntest %edi,%eax\nje 1162 \nmov %eax,%edi\njmp 114d \nmov $0x0,%eax\nretq\nmov %edi,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nloc_114D:\ntest edi, edi\njle short loc_115C\nlea eax, [rdi-1]\ntest eax, edi\njz short loc_1162\nmov edi, eax\njmp short loc_114D\nloc_115C:\nmov eax, 0\nretn\nloc_1162:\nmov eax, edi\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n while ( 1 )\n {\n if ( a1 <= 0 )\n return 0LL;\n if ( (a1 & (a1 - 1)) == 0 )\n break;\n --a1;\n }\n return (unsigned int)a1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nloc_114D:\ntest edi, edi\njle short loc_115C\nlea eax, [rdi-1]\ntest eax, edi\njz short loc_1162\nmov edi, eax\njmp short loc_114D\nloc_115C:\nmov eax, 0\nretn\nloc_1162:\nmov eax, edi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n while ( 1 )\n {\n if ( a1 <= 0 )\n return 0LL;\n if ( (a1 & (a1 - 1)) == 0 )\n break;\n --a1;\n }\n return (unsigned int)a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n while (1) {\n if (a1 <= 0) return 0LL;\n if ((a1 & (a1 - 1)) == 0) break;\n --a1;\n }\n return (unsigned int)a1;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n while (1) {\n if (a1 <= 0) return 0LL;\n if ((a1 & (a1 - 1)) == 0) break;\n --a1;\n }\n return (unsigned int)a1;\n}" + }, + { + "index": 389, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n == 0) return 2;\n if (n == 1) return 1;\n return func0(n - 1) + func0(n - 2);\n}", + "test": "int main() {\n\n assert(func0(9) == 76);\n\n assert(func0(4) == 7);\n\n assert(func0(3) == 4);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x18,%rsp\nmov %edi,-0x14(%rbp)\ncmpl $0x0,-0x14(%rbp)\njne 1166 \nmov $0x2,%eax\njmp 1191 \ncmpl $0x1,-0x14(%rbp)\njne 1173 \nmov $0x1,%eax\njmp 1191 \nmov -0x14(%rbp),%eax\nsub $0x1,%eax\nmov %eax,%edi\ncallq 1149 \nmov %eax,%ebx\nmov -0x14(%rbp),%eax\nsub $0x2,%eax\nmov %eax,%edi\ncallq 1149 \nadd %ebx,%eax\nadd $0x18,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 18h\nmov [rbp+var_14], edi\ncmp [rbp+var_14], 0\njnz short loc_1166\nmov eax, 2\njmp short loc_1191\nloc_1166:\ncmp [rbp+var_14], 1\njnz short loc_1173\nmov eax, 1\njmp short loc_1191\nloc_1173:\nmov eax, [rbp+var_14]\nsub eax, 1\nmov edi, eax\ncall func0\nmov ebx, eax\nmov eax, [rbp+var_14]\nsub eax, 2\nmov edi, eax\ncall func0\nadd eax, ebx\nloc_1191:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v2; // ebx\n\n if ( !a1 )\n return 2LL;\n if ( a1 == 1 )\n return 1LL;\n v2 = func0((unsigned int)(a1 - 1));\n return v2 + (unsigned int)func0((unsigned int)(a1 - 2));\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 18h\nmov [rbp+var_14], edi\ncmp [rbp+var_14], 0\njnz short loc_1166\nmov eax, 2\njmp short loc_1191\nloc_1166:\ncmp [rbp+var_14], 1\njnz short loc_1173\nmov eax, 1\njmp short loc_1191\nloc_1173:\nmov eax, [rbp+var_14]\nsub eax, 1\nmov edi, eax\ncall sub_1149\nmov ebx, eax\nmov eax, [rbp+var_14]\nsub eax, 2\nmov edi, eax\ncall sub_1149\nadd eax, ebx\nloc_1191:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v2; // ebx\n\n if ( !a1 )\n return 2LL;\n if ( a1 == 1 )\n return 1LL;\n v2 = sub_1149((unsigned int)(a1 - 1));\n return v2 + (unsigned int)sub_1149((unsigned int)(a1 - 2));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v2;\n if (!a1) return 2LL;\n if (a1 == 1) return 1LL;\n v2 = sub_1149((unsigned int)(a1 - 1));\n return v2 + (unsigned int)sub_1149((unsigned int)(a1 - 2));\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v2;\n if (!a1) return 2LL;\n if (a1 == 1) return 1LL;\n v2 = func0((unsigned int)(a1 - 1));\n return v2 + (unsigned int)func0((unsigned int)(a1 - 2));\n}" + }, + { + "index": 389, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n == 0) return 2;\n if (n == 1) return 1;\n return func0(n - 1) + func0(n - 2);\n}", + "test": "int main() {\n\n assert(func0(9) == 76);\n\n assert(func0(4) == 7);\n\n assert(func0(3) == 4);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x2,%eax\ntest %edi,%edi\nje 1180 \npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %edi,%ebx\nmov %edi,%eax\ncmp $0x1,%edi\nje 1179 \nlea -0x1(%rdi),%edi\ncallq 1149 \nmov %eax,%ebp\nlea -0x2(%rbx),%edi\ncallq 1149 \nadd %ebp,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nretq\n", + "ida_asm": "func0:\nendbr64\nmov eax, 2\ntest edi, edi\njz short locret_1180\npush rbp\npush rbx\nsub rsp, 8\nmov ebx, edi\nmov eax, edi\ncmp edi, 1\njz short loc_1179\nlea edi, [rdi-1]\ncall func0\nmov ebp, eax\nlea edi, [rbx-2]\ncall func0\nadd eax, ebp\nloc_1179:\nadd rsp, 8\npop rbx\npop rbp\nretn\nlocret_1180:\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1)\n{\n __int64 result; // rax\n int v2; // ebp\n\n result = 2LL;\n if ( a1 )\n {\n result = a1;\n if ( a1 != 1 )\n {\n v2 = func0(a1 - 1);\n return v2 + (unsigned int)func0(a1 - 2);\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmov eax, 2\ntest edi, edi\njz short locret_1180\npush rbp\npush rbx\nsub rsp, 8\nmov ebx, edi\nmov eax, edi\ncmp edi, 1\njz short loc_1179\nlea edi, [rdi-1]\ncall sub_1149\nmov ebp, eax\nlea edi, [rbx-2]\ncall sub_1149\nadd eax, ebp\nloc_1179:\nadd rsp, 8\npop rbx\npop rbp\nretn\nlocret_1180:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(unsigned int a1)\n{\n __int64 result; // rax\n int v2; // ebp\n\n result = 2LL;\n if ( a1 )\n {\n result = a1;\n if ( a1 != 1 )\n {\n v2 = sub_1149(a1 - 1);\n return v2 + (unsigned int)sub_1149(a1 - 2);\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(unsigned int a1) {\n long long result;\n int v2;\n result = 2LL;\n if (a1) {\n result = a1;\n if (a1 != 1) {\n v2 = sub_1149(a1 - 1);\n return v2 + (unsigned int)sub_1149(a1 - 2);\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(unsigned int a1) {\n long long result;\n int v2;\n result = 2LL;\n if (a1) {\n result = a1;\n if (a1 != 1) {\n v2 = func0(a1 - 1);\n return v2 + (unsigned int)func0(a1 - 2);\n }\n }\n return result;\n}" + }, + { + "index": 389, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n == 0) return 2;\n if (n == 1) return 1;\n return func0(n - 1) + func0(n - 2);\n}", + "test": "int main() {\n\n assert(func0(9) == 76);\n\n assert(func0(4) == 7);\n\n assert(func0(3) == 4);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\nje 1238 \npush %rbp\npush %rbx\nmov %edi,%ebx\nsub $0x8,%rsp\ncmp $0x1,%edi\nje 1240 \nxor %ebp,%ebp\nlea -0x1(%rbx),%edi\ncallq 11f0 \nadd %eax,%ebp\nsub $0x2,%ebx\nje 1228 \ncmp $0x1,%ebx\njne 1207 \nlea 0x1(%rbp),%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopl (%rax)\nadd $0x8,%rsp\nlea 0x2(%rbp),%eax\npop %rbx\npop %rbp\nretq\nnopw 0x0(%rax,%rax,1)\nmov $0x2,%eax\nretq\nxchg %ax,%ax\nmov $0x1,%eax\njmp 121e \nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 58h\ntest edi, edi\njz loc_153C\nmov r15d, edi\ncmp edi, 1\njz loc_1449\nlea r13d, [rdi-1]\nxor r15d, r15d\nloc_121D:\ncmp r13d, 1\njz loc_1533\nlea ebx, [r13-1]\nmov [rsp+88h+var_6C], r15d\nxor r12d, r12d\nmov eax, r13d\nmov [rsp+88h+var_68], ebx\nmov ebp, r12d\nloc_123D:\ncmp ebx, 1\njz loc_1516\nmov [rsp+88h+var_64], ebp\nlea edx, [rbx-1]\nxor r13d, r13d\nmov [rsp+88h+var_60], ebx\nmov esi, edx\nmov ebx, edx\nmov edx, eax\nloc_125A:\ncmp ebx, 1\njz loc_14FC\nlea edi, [rbx-1]\nmov [rsp+88h+var_5C], r13d\nxor r12d, r12d\nmov [rsp+88h+var_58], edi\nmov r15d, edi\nloc_1275:\ncmp r15d, 1\njz loc_14E4\nlea r9d, [r15-1]\nxor ebp, ebp\nmov [rsp+88h+var_54], r15d\nmov [rsp+88h+var_50], r12d\nmov r14d, r9d\nmov [rsp+88h+var_78], ebp\nmov [rsp+88h+var_4C], r9d\nmov [rsp+88h+var_48], ebx\nmov [rsp+88h+var_44], esi\nmov [rsp+88h+var_40], edx\nloc_12A7:\ncmp r14d, 1\njz loc_14A1\nlea ebx, [r14-1]\nxor r12d, r12d\nmov [rsp+88h+var_3C], ebx\nmov r15d, r12d\nmov ebp, ebx\nloc_12C1:\ncmp ebp, 1\njz loc_1478\nlea r12d, [rbp-1]\nmov [rsp+88h+var_84], r14d\nxor ebx, ebx\nmov [rsp+88h+var_80], r12d\nmov esi, ebx\nmov ebx, r12d\nmov [rsp+88h+var_7C], ebp\nloc_12E3:\ncmp ebx, 1\njz loc_145B\nlea ebp, [rbx-1]\nmov ecx, ebx\nxor r12d, r12d\nmov r14d, ebp\nmov edx, ebp\nmov ebp, esi\nmov ebx, r14d\nloc_12FE:\nmov r13d, ebx\ncmp ebx, 1\njz loc_14D0\nmov [rsp+88h+var_74], ebx\nxor r14d, r14d\nmov ebx, edx\nloc_1313:\nlea edi, [r13-1]\nmov [rsp+88h+var_70], ecx\ncall func0\nmov ecx, [rsp+88h+var_70]\nadd r14d, eax\nsub r13d, 2\njz loc_1490\ncmp r13d, 1\njnz short loc_1313\nmov edx, ebx\nmov ebx, [rsp+88h+var_74]\nloc_133D:\nlea eax, [r14+r13]\nadd r12d, eax\nsub ebx, 2\njnz short loc_12FE\nmov esi, ebp\nmov ebx, ecx\nmov ebp, edx\nmov edi, 1\nloc_1354:\nadd edi, r12d\nsub ebx, 2\nadd esi, edi\ncmp ebp, 1\njnz short loc_12E3\nmov r14d, [rsp+88h+var_84]\nmov ebp, [rsp+88h+var_7C]\nmov ebx, esi\nmov edx, 1\nmov r12d, [rsp+88h+var_80]\nloc_1376:\nadd edx, ebx\nsub ebp, 2\nadd r15d, edx\ncmp r12d, 1\njnz loc_12C1\nmov ebx, [rsp+88h+var_3C]\nmov r12d, r15d\nmov eax, 1\nloc_1394:\nadd eax, r12d\nsub r14d, 2\nadd [rsp+88h+var_78], eax\ncmp ebx, 1\njnz loc_12A7\nmov r15d, [rsp+88h+var_54]\nmov r12d, [rsp+88h+var_50]\nmov r11d, 1\nmov ebp, [rsp+88h+var_78]\nmov r9d, [rsp+88h+var_4C]\nmov ebx, [rsp+88h+var_48]\nmov esi, [rsp+88h+var_44]\nmov edx, [rsp+88h+var_40]\nloc_13CD:\nadd r11d, ebp\nsub r15d, 2\nadd r12d, r11d\ncmp r9d, 1\njnz loc_1275\nmov r13d, [rsp+88h+var_5C]\nmov edi, [rsp+88h+var_58]\nloc_13EA:\nadd r9d, r12d\nsub ebx, 2\nadd r13d, r9d\ncmp edi, 1\njnz loc_125A\nmov ebp, [rsp+88h+var_64]\nmov ebx, [rsp+88h+var_60]\nmov eax, edx\nmov edx, esi\nmov esi, 1\nloc_140D:\nadd esi, r13d\nsub ebx, 2\nadd ebp, esi\ncmp edx, 1\njnz loc_123D\nmov r15d, [rsp+88h+var_6C]\nmov ebx, [rsp+88h+var_68]\nmov r13d, eax\nmov r12d, ebp\nmov eax, 1\nloc_1432:\nadd eax, r12d\nsub r13d, 2\nadd r15d, eax\ncmp ebx, 1\njnz loc_121D\nadd r15d, 1\nloc_1449:\nadd rsp, 58h\nmov eax, r15d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_145B:\nmov ebx, esi\nmov r14d, [rsp+88h+var_84]\nmov ebp, [rsp+88h+var_7C]\nmov edx, 2\nmov r12d, [rsp+88h+var_80]\nadd ebx, 1\njmp loc_1376\nloc_1478:\nmov r12d, r15d\nmov ebx, [rsp+88h+var_3C]\nmov eax, 2\nadd r12d, 1\njmp loc_1394\nloc_1490:\nmov edx, ebx\nmov r13d, 2\nmov ebx, [rsp+88h+var_74]\njmp loc_133D\nloc_14A1:\nmov ebp, [rsp+88h+var_78]\nmov r15d, [rsp+88h+var_54]\nmov r11d, 2\nmov r12d, [rsp+88h+var_50]\nmov r9d, [rsp+88h+var_4C]\nmov ebx, [rsp+88h+var_48]\nmov esi, [rsp+88h+var_44]\nadd ebp, 1\nmov edx, [rsp+88h+var_40]\njmp loc_13CD\nloc_14D0:\nmov esi, ebp\nmov ebx, ecx\nmov ebp, edx\nadd r12d, 1\nmov edi, 2\njmp loc_1354\nloc_14E4:\nmov r13d, [rsp+88h+var_5C]\nmov edi, [rsp+88h+var_58]\nadd r12d, 1\nmov r9d, 2\njmp loc_13EA\nloc_14FC:\nmov eax, edx\nmov ebp, [rsp+88h+var_64]\nmov edx, esi\nmov ebx, [rsp+88h+var_60]\nadd r13d, 1\nmov esi, 2\njmp loc_140D\nloc_1516:\nmov r12d, ebp\nmov r13d, eax\nmov r15d, [rsp+88h+var_6C]\nmov ebx, [rsp+88h+var_68]\nadd r12d, 1\nmov eax, 2\njmp loc_1432\nloc_1533:\nadd r15d, 3\njmp loc_1449\nloc_153C:\nmov r15d, 2\njmp loc_1449", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1)\n{\n unsigned int v1; // r15d\n unsigned int v2; // r13d\n int v3; // r15d\n unsigned int v4; // ebx\n unsigned int v5; // eax\n int v6; // ebp\n int v7; // r13d\n unsigned int v8; // esi\n unsigned int v9; // ebx\n unsigned int v10; // edx\n int v11; // r12d\n unsigned int v12; // r15d\n unsigned int v13; // r14d\n int v14; // r15d\n int v15; // ebp\n int v16; // esi\n int v17; // ebx\n int v18; // ecx\n int v19; // r12d\n int v20; // edx\n int v21; // ebx\n int v22; // r13d\n int v23; // r14d\n int v24; // ebx\n int v25; // eax\n int v26; // ebx\n int v27; // ebx\n int v28; // ebp\n int v29; // edi\n int v30; // ebp\n int v31; // ebx\n int v32; // edx\n int v33; // r12d\n int v34; // ebx\n int v35; // r12d\n int v36; // eax\n unsigned int v37; // r15d\n int v38; // r12d\n int v39; // r11d\n int v40; // ebp\n int v41; // r9d\n int v42; // r13d\n unsigned int v43; // edi\n int v44; // ebp\n unsigned int v45; // ebx\n unsigned int v46; // edx\n int v47; // esi\n int v48; // r15d\n unsigned int v49; // ebx\n unsigned int v50; // r13d\n int v51; // r12d\n int v52; // eax\n int v54; // [rsp+4h] [rbp-84h]\n int v55; // [rsp+8h] [rbp-80h]\n int v56; // [rsp+Ch] [rbp-7Ch]\n int v57; // [rsp+10h] [rbp-78h]\n int v58; // [rsp+14h] [rbp-74h]\n int v59; // [rsp+18h] [rbp-70h]\n int v60; // [rsp+1Ch] [rbp-6Ch]\n unsigned int v61; // [rsp+20h] [rbp-68h]\n int v62; // [rsp+24h] [rbp-64h]\n unsigned int v63; // [rsp+28h] [rbp-60h]\n int v64; // [rsp+2Ch] [rbp-5Ch]\n unsigned int v65; // [rsp+30h] [rbp-58h]\n unsigned int v66; // [rsp+34h] [rbp-54h]\n int v67; // [rsp+38h] [rbp-50h]\n int v68; // [rsp+3Ch] [rbp-4Ch]\n unsigned int v69; // [rsp+40h] [rbp-48h]\n unsigned int v70; // [rsp+44h] [rbp-44h]\n unsigned int v71; // [rsp+48h] [rbp-40h]\n int v72; // [rsp+4Ch] [rbp-3Ch]\n\n if ( a1 )\n {\n v1 = a1;\n if ( a1 != 1 )\n {\n v2 = a1 - 1;\n v3 = 0;\n while ( v2 != 1 )\n {\n v4 = v2 - 1;\n v60 = v3;\n v5 = v2;\n v61 = v2 - 1;\n v6 = 0;\n while ( v4 != 1 )\n {\n v62 = v6;\n v7 = 0;\n v63 = v4;\n v8 = v4 - 1;\n v9 = v4 - 1;\n v10 = v5;\n while ( v9 != 1 )\n {\n v64 = v7;\n v11 = 0;\n v65 = v9 - 1;\n v12 = v9 - 1;\n while ( v12 != 1 )\n {\n v66 = v12;\n v67 = v11;\n v13 = v12 - 1;\n v57 = 0;\n v68 = v12 - 1;\n v69 = v9;\n v70 = v8;\n v71 = v10;\n while ( v13 != 1 )\n {\n v72 = v13 - 1;\n v14 = 0;\n v15 = v13 - 1;\n while ( v15 != 1 )\n {\n v54 = v13;\n v55 = v15 - 1;\n v16 = 0;\n v17 = v15 - 1;\n v56 = v15;\n while ( v17 != 1 )\n {\n v18 = v17;\n v19 = 0;\n v20 = v17 - 1;\n v21 = v17 - 1;\n while ( 1 )\n {\n v22 = v21;\n if ( v21 == 1 )\n break;\n v58 = v21;\n v23 = 0;\n v24 = v20;\n while ( 1 )\n {\n v59 = v18;\n v25 = func0((unsigned int)(v22 - 1));\n v18 = v59;\n v23 += v25;\n v22 -= 2;\n if ( !v22 )\n break;\n if ( v22 == 1 )\n {\n v20 = v24;\n v26 = v58;\n goto LABEL_23;\n }\n }\n v20 = v24;\n v22 = 2;\n v26 = v58;\nLABEL_23:\n v19 += v23 + v22;\n v21 = v26 - 2;\n if ( !v21 )\n {\n v27 = v59;\n v28 = v20;\n v29 = 1;\n goto LABEL_25;\n }\n }\n v27 = v18;\n v28 = v20;\n ++v19;\n v29 = 2;\nLABEL_25:\n v17 = v27 - 2;\n v16 += v19 + v29;\n if ( v28 == 1 )\n {\n v13 = v54;\n v30 = v56;\n v31 = v16;\n v32 = 1;\n v33 = v55;\n goto LABEL_27;\n }\n }\n v13 = v54;\n v30 = v56;\n v32 = 2;\n v33 = v55;\n v31 = v16 + 1;\nLABEL_27:\n v15 = v30 - 2;\n v14 += v31 + v32;\n if ( v33 == 1 )\n {\n v34 = v72;\n v35 = v14;\n v36 = 1;\n goto LABEL_29;\n }\n }\n v34 = v72;\n v36 = 2;\n v35 = v14 + 1;\nLABEL_29:\n v13 -= 2;\n v57 += v35 + v36;\n if ( v34 == 1 )\n {\n v37 = v66;\n v38 = v67;\n v39 = 1;\n v40 = v57;\n v41 = v68;\n v9 = v69;\n v8 = v70;\n v10 = v71;\n goto LABEL_31;\n }\n }\n v37 = v66;\n v39 = 2;\n v38 = v67;\n v41 = v68;\n v9 = v69;\n v8 = v70;\n v40 = v57 + 1;\n v10 = v71;\nLABEL_31:\n v12 = v37 - 2;\n v11 = v40 + v39 + v38;\n if ( v41 == 1 )\n {\n v42 = v64;\n v43 = v65;\n goto LABEL_33;\n }\n }\n v42 = v64;\n v43 = v65;\n ++v11;\n v41 = 2;\nLABEL_33:\n v9 -= 2;\n v7 = v11 + v41 + v42;\n if ( v43 == 1 )\n {\n v44 = v62;\n v45 = v63;\n v5 = v10;\n v46 = v8;\n v47 = 1;\n goto LABEL_35;\n }\n }\n v5 = v10;\n v44 = v62;\n v46 = v8;\n v45 = v63;\n ++v7;\n v47 = 2;\nLABEL_35:\n v4 = v45 - 2;\n v6 = v7 + v47 + v44;\n if ( v46 == 1 )\n {\n v48 = v60;\n v49 = v61;\n v50 = v5;\n v51 = v6;\n v52 = 1;\n goto LABEL_37;\n }\n }\n v50 = v5;\n v48 = v60;\n v49 = v61;\n v51 = v6 + 1;\n v52 = 2;\nLABEL_37:\n v2 = v50 - 2;\n v3 = v51 + v52 + v48;\n if ( v49 == 1 )\n return (unsigned int)(v3 + 1);\n }\n return (unsigned int)(v3 + 3);\n }\n }\n else\n {\n return 2;\n }\n return v1;\n}", + "ida_strip_asm": "sub_11F0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 58h\ntest edi, edi\njz loc_153C\nmov r15d, edi\ncmp edi, 1\njz loc_1449\nlea r13d, [rdi-1]\nxor r15d, r15d\nloc_121D:\ncmp r13d, 1\njz loc_1533\nlea ebx, [r13-1]\nmov [rsp+88h+var_6C], r15d\nxor r12d, r12d\nmov eax, r13d\nmov [rsp+88h+var_68], ebx\nmov ebp, r12d\nloc_123D:\ncmp ebx, 1\njz loc_1516\nmov [rsp+88h+var_64], ebp\nlea edx, [rbx-1]\nxor r13d, r13d\nmov [rsp+88h+var_60], ebx\nmov esi, edx\nmov ebx, edx\nmov edx, eax\nloc_125A:\ncmp ebx, 1\njz loc_14FC\nlea edi, [rbx-1]\nmov [rsp+88h+var_5C], r13d\nxor r12d, r12d\nmov [rsp+88h+var_58], edi\nmov r15d, edi\nloc_1275:\ncmp r15d, 1\njz loc_14E4\nlea r9d, [r15-1]\nxor ebp, ebp\nmov [rsp+88h+var_54], r15d\nmov [rsp+88h+var_50], r12d\nmov r14d, r9d\nmov [rsp+88h+var_78], ebp\nmov [rsp+88h+var_4C], r9d\nmov [rsp+88h+var_48], ebx\nmov [rsp+88h+var_44], esi\nmov [rsp+88h+var_40], edx\nloc_12A7:\ncmp r14d, 1\njz loc_14A1\nlea ebx, [r14-1]\nxor r12d, r12d\nmov [rsp+88h+var_3C], ebx\nmov r15d, r12d\nmov ebp, ebx\nloc_12C1:\ncmp ebp, 1\njz loc_1478\nlea r12d, [rbp-1]\nmov [rsp+88h+var_84], r14d\nxor ebx, ebx\nmov [rsp+88h+var_80], r12d\nmov esi, ebx\nmov ebx, r12d\nmov [rsp+88h+var_7C], ebp\nloc_12E3:\ncmp ebx, 1\njz loc_145B\nlea ebp, [rbx-1]\nmov ecx, ebx\nxor r12d, r12d\nmov r14d, ebp\nmov edx, ebp\nmov ebp, esi\nmov ebx, r14d\nloc_12FE:\nmov r13d, ebx\ncmp ebx, 1\njz loc_14D0\nmov [rsp+88h+var_74], ebx\nxor r14d, r14d\nmov ebx, edx\nloc_1313:\nlea edi, [r13-1]\nmov [rsp+88h+var_70], ecx\ncall sub_11F0\nmov ecx, [rsp+88h+var_70]\nadd r14d, eax\nsub r13d, 2\njz loc_1490\ncmp r13d, 1\njnz short loc_1313\nmov edx, ebx\nmov ebx, [rsp+88h+var_74]\nloc_133D:\nlea eax, [r14+r13]\nadd r12d, eax\nsub ebx, 2\njnz short loc_12FE\nmov esi, ebp\nmov ebx, ecx\nmov ebp, edx\nmov edi, 1\nloc_1354:\nadd edi, r12d\nsub ebx, 2\nadd esi, edi\ncmp ebp, 1\njnz short loc_12E3\nmov r14d, [rsp+88h+var_84]\nmov ebp, [rsp+88h+var_7C]\nmov ebx, esi\nmov edx, 1\nmov r12d, [rsp+88h+var_80]\nloc_1376:\nadd edx, ebx\nsub ebp, 2\nadd r15d, edx\ncmp r12d, 1\njnz loc_12C1\nmov ebx, [rsp+88h+var_3C]\nmov r12d, r15d\nmov eax, 1\nloc_1394:\nadd eax, r12d\nsub r14d, 2\nadd [rsp+88h+var_78], eax\ncmp ebx, 1\njnz loc_12A7\nmov r15d, [rsp+88h+var_54]\nmov r12d, [rsp+88h+var_50]\nmov r11d, 1\nmov ebp, [rsp+88h+var_78]\nmov r9d, [rsp+88h+var_4C]\nmov ebx, [rsp+88h+var_48]\nmov esi, [rsp+88h+var_44]\nmov edx, [rsp+88h+var_40]\nloc_13CD:\nadd r11d, ebp\nsub r15d, 2\nadd r12d, r11d\ncmp r9d, 1\njnz loc_1275\nmov r13d, [rsp+88h+var_5C]\nmov edi, [rsp+88h+var_58]\nloc_13EA:\nadd r9d, r12d\nsub ebx, 2\nadd r13d, r9d\ncmp edi, 1\njnz loc_125A\nmov ebp, [rsp+88h+var_64]\nmov ebx, [rsp+88h+var_60]\nmov eax, edx\nmov edx, esi\nmov esi, 1\nloc_140D:\nadd esi, r13d\nsub ebx, 2\nadd ebp, esi\ncmp edx, 1\njnz loc_123D\nmov r15d, [rsp+88h+var_6C]\nmov ebx, [rsp+88h+var_68]\nmov r13d, eax\nmov r12d, ebp\nmov eax, 1\nloc_1432:\nadd eax, r12d\nsub r13d, 2\nadd r15d, eax\ncmp ebx, 1\njnz loc_121D\nadd r15d, 1\nloc_1449:\nadd rsp, 58h\nmov eax, r15d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_145B:\nmov ebx, esi\nmov r14d, [rsp+88h+var_84]\nmov ebp, [rsp+88h+var_7C]\nmov edx, 2\nmov r12d, [rsp+88h+var_80]\nadd ebx, 1\njmp loc_1376\nloc_1478:\nmov r12d, r15d\nmov ebx, [rsp+88h+var_3C]\nmov eax, 2\nadd r12d, 1\njmp loc_1394\nloc_1490:\nmov edx, ebx\nmov r13d, 2\nmov ebx, [rsp+88h+var_74]\njmp loc_133D\nloc_14A1:\nmov ebp, [rsp+88h+var_78]\nmov r15d, [rsp+88h+var_54]\nmov r11d, 2\nmov r12d, [rsp+88h+var_50]\nmov r9d, [rsp+88h+var_4C]\nmov ebx, [rsp+88h+var_48]\nmov esi, [rsp+88h+var_44]\nadd ebp, 1\nmov edx, [rsp+88h+var_40]\njmp loc_13CD\nloc_14D0:\nmov esi, ebp\nmov ebx, ecx\nmov ebp, edx\nadd r12d, 1\nmov edi, 2\njmp loc_1354\nloc_14E4:\nmov r13d, [rsp+88h+var_5C]\nmov edi, [rsp+88h+var_58]\nadd r12d, 1\nmov r9d, 2\njmp loc_13EA\nloc_14FC:\nmov eax, edx\nmov ebp, [rsp+88h+var_64]\nmov edx, esi\nmov ebx, [rsp+88h+var_60]\nadd r13d, 1\nmov esi, 2\njmp loc_140D\nloc_1516:\nmov r12d, ebp\nmov r13d, eax\nmov r15d, [rsp+88h+var_6C]\nmov ebx, [rsp+88h+var_68]\nadd r12d, 1\nmov eax, 2\njmp loc_1432\nloc_1533:\nadd r15d, 3\njmp loc_1449\nloc_153C:\nmov r15d, 2\njmp loc_1449", + "ida_strip_pseudo": "__int64 __fastcall sub_11F0(unsigned int a1)\n{\n unsigned int v1; // r15d\n unsigned int v2; // r13d\n int v3; // r15d\n unsigned int v4; // ebx\n unsigned int v5; // eax\n int v6; // ebp\n int v7; // r13d\n unsigned int v8; // esi\n unsigned int v9; // ebx\n unsigned int v10; // edx\n int v11; // r12d\n unsigned int v12; // r15d\n unsigned int v13; // r14d\n int v14; // r15d\n int v15; // ebp\n int v16; // esi\n int v17; // ebx\n int v18; // ecx\n int v19; // r12d\n int v20; // edx\n int v21; // ebx\n int v22; // r13d\n int v23; // r14d\n int v24; // ebx\n int v25; // eax\n int v26; // ebx\n int v27; // ebx\n int v28; // ebp\n int v29; // edi\n int v30; // ebp\n int v31; // ebx\n int v32; // edx\n int v33; // r12d\n int v34; // ebx\n int v35; // r12d\n int v36; // eax\n unsigned int v37; // r15d\n int v38; // r12d\n int v39; // r11d\n int v40; // ebp\n int v41; // r9d\n int v42; // r13d\n unsigned int v43; // edi\n int v44; // ebp\n unsigned int v45; // ebx\n unsigned int v46; // edx\n int v47; // esi\n int v48; // r15d\n unsigned int v49; // ebx\n unsigned int v50; // r13d\n int v51; // r12d\n int v52; // eax\n int v54; // [rsp+4h] [rbp-84h]\n int v55; // [rsp+8h] [rbp-80h]\n int v56; // [rsp+Ch] [rbp-7Ch]\n int v57; // [rsp+10h] [rbp-78h]\n int v58; // [rsp+14h] [rbp-74h]\n int v59; // [rsp+18h] [rbp-70h]\n int v60; // [rsp+1Ch] [rbp-6Ch]\n unsigned int v61; // [rsp+20h] [rbp-68h]\n int v62; // [rsp+24h] [rbp-64h]\n unsigned int v63; // [rsp+28h] [rbp-60h]\n int v64; // [rsp+2Ch] [rbp-5Ch]\n unsigned int v65; // [rsp+30h] [rbp-58h]\n unsigned int v66; // [rsp+34h] [rbp-54h]\n int v67; // [rsp+38h] [rbp-50h]\n int v68; // [rsp+3Ch] [rbp-4Ch]\n unsigned int v69; // [rsp+40h] [rbp-48h]\n unsigned int v70; // [rsp+44h] [rbp-44h]\n unsigned int v71; // [rsp+48h] [rbp-40h]\n int v72; // [rsp+4Ch] [rbp-3Ch]\n\n if ( a1 )\n {\n v1 = a1;\n if ( a1 != 1 )\n {\n v2 = a1 - 1;\n v3 = 0;\n while ( v2 != 1 )\n {\n v4 = v2 - 1;\n v60 = v3;\n v5 = v2;\n v61 = v2 - 1;\n v6 = 0;\n while ( v4 != 1 )\n {\n v62 = v6;\n v7 = 0;\n v63 = v4;\n v8 = v4 - 1;\n v9 = v4 - 1;\n v10 = v5;\n while ( v9 != 1 )\n {\n v64 = v7;\n v11 = 0;\n v65 = v9 - 1;\n v12 = v9 - 1;\n while ( v12 != 1 )\n {\n v66 = v12;\n v67 = v11;\n v13 = v12 - 1;\n v57 = 0;\n v68 = v12 - 1;\n v69 = v9;\n v70 = v8;\n v71 = v10;\n while ( v13 != 1 )\n {\n v72 = v13 - 1;\n v14 = 0;\n v15 = v13 - 1;\n while ( v15 != 1 )\n {\n v54 = v13;\n v55 = v15 - 1;\n v16 = 0;\n v17 = v15 - 1;\n v56 = v15;\n while ( v17 != 1 )\n {\n v18 = v17;\n v19 = 0;\n v20 = v17 - 1;\n v21 = v17 - 1;\n while ( 1 )\n {\n v22 = v21;\n if ( v21 == 1 )\n break;\n v58 = v21;\n v23 = 0;\n v24 = v20;\n while ( 1 )\n {\n v59 = v18;\n v25 = sub_11F0((unsigned int)(v22 - 1));\n v18 = v59;\n v23 += v25;\n v22 -= 2;\n if ( !v22 )\n break;\n if ( v22 == 1 )\n {\n v20 = v24;\n v26 = v58;\n goto LABEL_23;\n }\n }\n v20 = v24;\n v22 = 2;\n v26 = v58;\nLABEL_23:\n v19 += v23 + v22;\n v21 = v26 - 2;\n if ( !v21 )\n {\n v27 = v59;\n v28 = v20;\n v29 = 1;\n goto LABEL_25;\n }\n }\n v27 = v18;\n v28 = v20;\n ++v19;\n v29 = 2;\nLABEL_25:\n v17 = v27 - 2;\n v16 += v19 + v29;\n if ( v28 == 1 )\n {\n v13 = v54;\n v30 = v56;\n v31 = v16;\n v32 = 1;\n v33 = v55;\n goto LABEL_27;\n }\n }\n v13 = v54;\n v30 = v56;\n v32 = 2;\n v33 = v55;\n v31 = v16 + 1;\nLABEL_27:\n v15 = v30 - 2;\n v14 += v31 + v32;\n if ( v33 == 1 )\n {\n v34 = v72;\n v35 = v14;\n v36 = 1;\n goto LABEL_29;\n }\n }\n v34 = v72;\n v36 = 2;\n v35 = v14 + 1;\nLABEL_29:\n v13 -= 2;\n v57 += v35 + v36;\n if ( v34 == 1 )\n {\n v37 = v66;\n v38 = v67;\n v39 = 1;\n v40 = v57;\n v41 = v68;\n v9 = v69;\n v8 = v70;\n v10 = v71;\n goto LABEL_31;\n }\n }\n v37 = v66;\n v39 = 2;\n v38 = v67;\n v41 = v68;\n v9 = v69;\n v8 = v70;\n v40 = v57 + 1;\n v10 = v71;\nLABEL_31:\n v12 = v37 - 2;\n v11 = v40 + v39 + v38;\n if ( v41 == 1 )\n {\n v42 = v64;\n v43 = v65;\n goto LABEL_33;\n }\n }\n v42 = v64;\n v43 = v65;\n ++v11;\n v41 = 2;\nLABEL_33:\n v9 -= 2;\n v7 = v11 + v41 + v42;\n if ( v43 == 1 )\n {\n v44 = v62;\n v45 = v63;\n v5 = v10;\n v46 = v8;\n v47 = 1;\n goto LABEL_35;\n }\n }\n v5 = v10;\n v44 = v62;\n v46 = v8;\n v45 = v63;\n ++v7;\n v47 = 2;\nLABEL_35:\n v4 = v45 - 2;\n v6 = v7 + v47 + v44;\n if ( v46 == 1 )\n {\n v48 = v60;\n v49 = v61;\n v50 = v5;\n v51 = v6;\n v52 = 1;\n goto LABEL_37;\n }\n }\n v50 = v5;\n v48 = v60;\n v49 = v61;\n v51 = v6 + 1;\n v52 = 2;\nLABEL_37:\n v2 = v50 - 2;\n v3 = v51 + v52 + v48;\n if ( v49 == 1 )\n return (unsigned int)(v3 + 1);\n }\n return (unsigned int)(v3 + 3);\n }\n }\n else\n {\n return 2;\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11F0(unsigned int a1) {\n unsigned int v1;\n unsigned int v2;\n int v3;\n unsigned int v4;\n unsigned int v5;\n int v6;\n int v7;\n unsigned int v8;\n unsigned int v9;\n unsigned int v10;\n int v11;\n unsigned int v12;\n unsigned int v13;\n int v14;\n int v15;\n int v16;\n int v17;\n int v18;\n int v19;\n int v20;\n int v21;\n int v22;\n int v23;\n int v24;\n int v25;\n int v26;\n int v27;\n int v28;\n int v29;\n int v30;\n int v31;\n int v32;\n int v33;\n int v34;\n int v35;\n int v36;\n unsigned int v37;\n int v38;\n int v39;\n int v40;\n int v41;\n int v42;\n unsigned int v43;\n int v44;\n unsigned int v45;\n unsigned int v46;\n int v47;\n int v48;\n unsigned int v49;\n unsigned int v50;\n int v51;\n int v52;\n int v54;\n int v55;\n int v56;\n int v57;\n int v58;\n int v59;\n int v60;\n unsigned int v61;\n int v62;\n unsigned int v63;\n int v64;\n unsigned int v65;\n unsigned int v66;\n int v67;\n int v68;\n unsigned int v69;\n unsigned int v70;\n unsigned int v71;\n int v72;\n if (a1) {\n v1 = a1;\n if (a1 != 1) {\n v2 = a1 - 1;\n v3 = 0;\n while (v2 != 1) {\n v4 = v2 - 1;\n v60 = v3;\n v5 = v2;\n v61 = v2 - 1;\n v6 = 0;\n while (v4 != 1) {\n v62 = v6;\n v7 = 0;\n v63 = v4;\n v8 = v4 - 1;\n v9 = v4 - 1;\n v10 = v5;\n while (v9 != 1) {\n v64 = v7;\n v11 = 0;\n v65 = v9 - 1;\n v12 = v9 - 1;\n while (v12 != 1) {\n v66 = v12;\n v67 = v11;\n v13 = v12 - 1;\n v57 = 0;\n v68 = v12 - 1;\n v69 = v9;\n v70 = v8;\n v71 = v10;\n while (v13 != 1) {\n v72 = v13 - 1;\n v14 = 0;\n v15 = v13 - 1;\n while (v15 != 1) {\n v54 = v13;\n v55 = v15 - 1;\n v16 = 0;\n v17 = v15 - 1;\n v56 = v15;\n while (v17 != 1) {\n v18 = v17;\n v19 = 0;\n v20 = v17 - 1;\n v21 = v17 - 1;\n while (1) {\n v22 = v21;\n if (v21 == 1) break;\n v58 = v21;\n v23 = 0;\n v24 = v20;\n while (1) {\n v59 = v18;\n v25 = sub_11F0((unsigned int)(v22 - 1));\n v18 = v59;\n v23 += v25;\n v22 -= 2;\n if (!v22) break;\n if (v22 == 1) {\n v20 = v24;\n v26 = v58;\n goto LABEL_23;\n }\n }\n v20 = v24;\n v22 = 2;\n v26 = v58;\n LABEL_23:\n v19 += v23 + v22;\n v21 = v26 - 2;\n if (!v21) {\n v27 = v59;\n v28 = v20;\n v29 = 1;\n goto LABEL_25;\n }\n }\n v27 = v18;\n v28 = v20;\n ++v19;\n v29 = 2;\n LABEL_25:\n v17 = v27 - 2;\n v16 += v19 + v29;\n if (v28 == 1) {\n v13 = v54;\n v30 = v56;\n v31 = v16;\n v32 = 1;\n v33 = v55;\n goto LABEL_27;\n }\n }\n v13 = v54;\n v30 = v56;\n v32 = 2;\n v33 = v55;\n v31 = v16 + 1;\n LABEL_27:\n v15 = v30 - 2;\n v14 += v31 + v32;\n if (v33 == 1) {\n v34 = v72;\n v35 = v14;\n v36 = 1;\n goto LABEL_29;\n }\n }\n v34 = v72;\n v36 = 2;\n v35 = v14 + 1;\n LABEL_29:\n v13 -= 2;\n v57 += v35 + v36;\n if (v34 == 1) {\n v37 = v66;\n v38 = v67;\n v39 = 1;\n v40 = v57;\n v41 = v68;\n v9 = v69;\n v8 = v70;\n v10 = v71;\n goto LABEL_31;\n }\n }\n v37 = v66;\n v39 = 2;\n v38 = v67;\n v41 = v68;\n v9 = v69;\n v8 = v70;\n v40 = v57 + 1;\n v10 = v71;\n LABEL_31:\n v12 = v37 - 2;\n v11 = v40 + v39 + v38;\n if (v41 == 1) {\n v42 = v64;\n v43 = v65;\n goto LABEL_33;\n }\n }\n v42 = v64;\n v43 = v65;\n ++v11;\n v41 = 2;\n LABEL_33:\n v9 -= 2;\n v7 = v11 + v41 + v42;\n if (v43 == 1) {\n v44 = v62;\n v45 = v63;\n v5 = v10;\n v46 = v8;\n v47 = 1;\n goto LABEL_35;\n }\n }\n v5 = v10;\n v44 = v62;\n v46 = v8;\n v45 = v63;\n ++v7;\n v47 = 2;\n LABEL_35:\n v4 = v45 - 2;\n v6 = v7 + v47 + v44;\n if (v46 == 1) {\n v48 = v60;\n v49 = v61;\n v50 = v5;\n v51 = v6;\n v52 = 1;\n goto LABEL_37;\n }\n }\n v50 = v5;\n v48 = v60;\n v49 = v61;\n v51 = v6 + 1;\n v52 = 2;\n LABEL_37:\n v2 = v50 - 2;\n v3 = v51 + v52 + v48;\n if (v49 == 1) return (unsigned int)(v3 + 1);\n }\n return (unsigned int)(v3 + 3);\n }\n } else {\n return 2;\n }\n return v1;\n}", + "ida_pseudo_norm": "long long func0(unsigned int a1) {\n unsigned int v1;\n unsigned int v2;\n int v3;\n unsigned int v4;\n unsigned int v5;\n int v6;\n int v7;\n unsigned int v8;\n unsigned int v9;\n unsigned int v10;\n int v11;\n unsigned int v12;\n unsigned int v13;\n int v14;\n int v15;\n int v16;\n int v17;\n int v18;\n int v19;\n int v20;\n int v21;\n int v22;\n int v23;\n int v24;\n int v25;\n int v26;\n int v27;\n int v28;\n int v29;\n int v30;\n int v31;\n int v32;\n int v33;\n int v34;\n int v35;\n int v36;\n unsigned int v37;\n int v38;\n int v39;\n int v40;\n int v41;\n int v42;\n unsigned int v43;\n int v44;\n unsigned int v45;\n unsigned int v46;\n int v47;\n int v48;\n unsigned int v49;\n unsigned int v50;\n int v51;\n int v52;\n int v54;\n int v55;\n int v56;\n int v57;\n int v58;\n int v59;\n int v60;\n unsigned int v61;\n int v62;\n unsigned int v63;\n int v64;\n unsigned int v65;\n unsigned int v66;\n int v67;\n int v68;\n unsigned int v69;\n unsigned int v70;\n unsigned int v71;\n int v72;\n if (a1) {\n v1 = a1;\n if (a1 != 1) {\n v2 = a1 - 1;\n v3 = 0;\n while (v2 != 1) {\n v4 = v2 - 1;\n v60 = v3;\n v5 = v2;\n v61 = v2 - 1;\n v6 = 0;\n while (v4 != 1) {\n v62 = v6;\n v7 = 0;\n v63 = v4;\n v8 = v4 - 1;\n v9 = v4 - 1;\n v10 = v5;\n while (v9 != 1) {\n v64 = v7;\n v11 = 0;\n v65 = v9 - 1;\n v12 = v9 - 1;\n while (v12 != 1) {\n v66 = v12;\n v67 = v11;\n v13 = v12 - 1;\n v57 = 0;\n v68 = v12 - 1;\n v69 = v9;\n v70 = v8;\n v71 = v10;\n while (v13 != 1) {\n v72 = v13 - 1;\n v14 = 0;\n v15 = v13 - 1;\n while (v15 != 1) {\n v54 = v13;\n v55 = v15 - 1;\n v16 = 0;\n v17 = v15 - 1;\n v56 = v15;\n while (v17 != 1) {\n v18 = v17;\n v19 = 0;\n v20 = v17 - 1;\n v21 = v17 - 1;\n while (1) {\n v22 = v21;\n if (v21 == 1) break;\n v58 = v21;\n v23 = 0;\n v24 = v20;\n while (1) {\n v59 = v18;\n v25 = func0((unsigned int)(v22 - 1));\n v18 = v59;\n v23 += v25;\n v22 -= 2;\n if (!v22) break;\n if (v22 == 1) {\n v20 = v24;\n v26 = v58;\n goto LABEL_23;\n }\n }\n v20 = v24;\n v22 = 2;\n v26 = v58;\n LABEL_23:\n v19 += v23 + v22;\n v21 = v26 - 2;\n if (!v21) {\n v27 = v59;\n v28 = v20;\n v29 = 1;\n goto LABEL_25;\n }\n }\n v27 = v18;\n v28 = v20;\n ++v19;\n v29 = 2;\n LABEL_25:\n v17 = v27 - 2;\n v16 += v19 + v29;\n if (v28 == 1) {\n v13 = v54;\n v30 = v56;\n v31 = v16;\n v32 = 1;\n v33 = v55;\n goto LABEL_27;\n }\n }\n v13 = v54;\n v30 = v56;\n v32 = 2;\n v33 = v55;\n v31 = v16 + 1;\n LABEL_27:\n v15 = v30 - 2;\n v14 += v31 + v32;\n if (v33 == 1) {\n v34 = v72;\n v35 = v14;\n v36 = 1;\n goto LABEL_29;\n }\n }\n v34 = v72;\n v36 = 2;\n v35 = v14 + 1;\n LABEL_29:\n v13 -= 2;\n v57 += v35 + v36;\n if (v34 == 1) {\n v37 = v66;\n v38 = v67;\n v39 = 1;\n v40 = v57;\n v41 = v68;\n v9 = v69;\n v8 = v70;\n v10 = v71;\n goto LABEL_31;\n }\n }\n v37 = v66;\n v39 = 2;\n v38 = v67;\n v41 = v68;\n v9 = v69;\n v8 = v70;\n v40 = v57 + 1;\n v10 = v71;\n LABEL_31:\n v12 = v37 - 2;\n v11 = v40 + v39 + v38;\n if (v41 == 1) {\n v42 = v64;\n v43 = v65;\n goto LABEL_33;\n }\n }\n v42 = v64;\n v43 = v65;\n ++v11;\n v41 = 2;\n LABEL_33:\n v9 -= 2;\n v7 = v11 + v41 + v42;\n if (v43 == 1) {\n v44 = v62;\n v45 = v63;\n v5 = v10;\n v46 = v8;\n v47 = 1;\n goto LABEL_35;\n }\n }\n v5 = v10;\n v44 = v62;\n v46 = v8;\n v45 = v63;\n ++v7;\n v47 = 2;\n LABEL_35:\n v4 = v45 - 2;\n v6 = v7 + v47 + v44;\n if (v46 == 1) {\n v48 = v60;\n v49 = v61;\n v50 = v5;\n v51 = v6;\n v52 = 1;\n goto LABEL_37;\n }\n }\n v50 = v5;\n v48 = v60;\n v49 = v61;\n v51 = v6 + 1;\n v52 = 2;\n LABEL_37:\n v2 = v50 - 2;\n v3 = v51 + v52 + v48;\n if (v49 == 1) return (unsigned int)(v3 + 1);\n }\n return (unsigned int)(v3 + 3);\n }\n } else {\n return 2;\n }\n return v1;\n}" + }, + { + "index": 389, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n == 0) return 2;\n if (n == 1) return 1;\n return func0(n - 1) + func0(n - 2);\n}", + "test": "int main() {\n\n assert(func0(9) == 76);\n\n assert(func0(4) == 7);\n\n assert(func0(3) == 4);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\nje 1238 \npush %rbp\npush %rbx\nmov %edi,%ebx\nsub $0x8,%rsp\ncmp $0x1,%edi\nje 1240 \nxor %ebp,%ebp\nlea -0x1(%rbx),%edi\ncallq 11f0 \nadd %eax,%ebp\nsub $0x2,%ebx\nje 1228 \ncmp $0x1,%ebx\njne 1207 \nlea 0x1(%rbp),%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopl (%rax)\nadd $0x8,%rsp\nlea 0x2(%rbp),%eax\npop %rbx\npop %rbp\nretq\nnopw 0x0(%rax,%rax,1)\nmov $0x2,%eax\nretq\nxchg %ax,%ax\nmov $0x1,%eax\njmp 121e \nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 58h\ntest edi, edi\njz loc_1528\nmov r15d, edi\ncmp edi, 1\njz loc_143D\nlea r13d, [rdi-1]\nxor r15d, r15d\nloc_121D:\ncmp r13d, 1\njz loc_151F\nlea ebx, [r13-1]\nmov [rsp+88h+var_6C], r15d\nxor r12d, r12d\nmov [rsp+88h+var_68], r13d\nmov ebp, r12d\nmov [rsp+88h+var_64], ebx\nloc_123F:\ncmp ebx, 1\njz loc_1500\nlea edx, [rbx-1]\nmov [rsp+88h+var_60], ebx\nxor r13d, r13d\nmov ecx, ebp\nmov ebx, edx\nloc_1256:\ncmp ebx, 1\njz loc_14EC\nmov [rsp+88h+var_5C], edx\nlea edi, [rbx-1]\nxor r12d, r12d\nmov [rsp+88h+var_58], r13d\nmov r15d, edi\nloc_1271:\ncmp r15d, 1\njz loc_14D4\nlea r9d, [r15-1]\nxor ebp, ebp\nmov [rsp+88h+var_54], ecx\nmov [rsp+88h+var_50], r12d\nmov r14d, r9d\nmov [rsp+88h+var_78], ebp\nmov [rsp+88h+var_4C], edi\nmov [rsp+88h+var_48], ebx\nmov [rsp+88h+var_44], r9d\nmov [rsp+88h+var_40], r15d\nloc_12A3:\ncmp r14d, 1\njz loc_1491\nlea ebx, [r14-1]\nxor r15d, r15d\nmov [rsp+88h+var_3C], ebx\nmov r13d, ebx\nloc_12BB:\ncmp r13d, 1\njz loc_146C\nlea ebp, [r13-1]\nmov [rsp+88h+var_84], r14d\nxor esi, esi\nmov [rsp+88h+var_80], ebp\nmov ebx, ebp\nmov [rsp+88h+var_7C], r13d\nloc_12DB:\ncmp ebx, 1\njz loc_144F\nlea ebp, [rbx-1]\nmov ecx, ebx\nxor r13d, r13d\nmov r14d, ebp\nmov edx, ebp\nmov ebp, esi\nmov ebx, r14d\nloc_12F6:\nmov r12d, ebx\ncmp ebx, 1\njz loc_14C0\nmov [rsp+88h+var_74], ebx\nxor r14d, r14d\nmov ebx, edx\nloc_130B:\nlea edi, [r12-1]\nmov [rsp+88h+var_70], ecx\ncall func0\nmov ecx, [rsp+88h+var_70]\nadd r14d, eax\nsub r12d, 2\njz loc_1480\ncmp r12d, 1\njnz short loc_130B\nmov edx, ebx\nmov ebx, [rsp+88h+var_74]\nloc_1336:\nlea eax, [r14+r12]\nadd r13d, eax\nsub ebx, 2\njnz short loc_12F6\nmov esi, ebp\nmov ebx, ecx\nmov ebp, edx\nmov edi, 1\nloc_134D:\nadd edi, r13d\nsub ebx, 2\nadd esi, edi\ncmp ebp, 1\njnz short loc_12DB\nmov r14d, [rsp+88h+var_84]\nmov ebp, [rsp+88h+var_80]\nmov ebx, esi\nmov edx, 1\nmov r13d, [rsp+88h+var_7C]\nloc_136F:\nadd edx, ebx\nsub r13d, 2\nadd r15d, edx\ncmp ebp, 1\njnz loc_12BB\nmov ebx, [rsp+88h+var_3C]\nmov ebp, r15d\nmov eax, 1\nloc_138D:\nadd eax, ebp\nsub r14d, 2\nadd [rsp+88h+var_78], eax\ncmp ebx, 1\njnz loc_12A3\nmov ecx, [rsp+88h+var_54]\nmov r12d, [rsp+88h+var_50]\nmov r11d, 1\nmov ebp, [rsp+88h+var_78]\nmov edi, [rsp+88h+var_4C]\nmov ebx, [rsp+88h+var_48]\nmov r9d, [rsp+88h+var_44]\nmov r15d, [rsp+88h+var_40]\nloc_13C5:\nadd r11d, ebp\nsub r15d, 2\nadd r12d, r11d\ncmp r9d, 1\njnz loc_1271\nmov edx, [rsp+88h+var_5C]\nmov r13d, [rsp+88h+var_58]\nloc_13E2:\nadd r9d, r12d\nsub ebx, 2\nadd r13d, r9d\ncmp edi, 1\njnz loc_1256\nmov ebx, [rsp+88h+var_60]\nmov ebp, ecx\nmov esi, 1\nloc_13FF:\nadd esi, r13d\nsub ebx, 2\nadd ebp, esi\ncmp edx, 1\njnz loc_123F\nmov r15d, [rsp+88h+var_6C]\nmov r13d, [rsp+88h+var_68]\nmov r12d, ebp\nmov eax, 1\nmov ebx, [rsp+88h+var_64]\nloc_1426:\nadd eax, r12d\nsub r13d, 2\nadd r15d, eax\ncmp ebx, 1\njnz loc_121D\nadd r15d, 1\nloc_143D:\nadd rsp, 58h\nmov eax, r15d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_144F:\nmov ebx, esi\nmov r14d, [rsp+88h+var_84]\nmov ebp, [rsp+88h+var_80]\nmov edx, 2\nmov r13d, [rsp+88h+var_7C]\nadd ebx, 1\njmp loc_136F\nloc_146C:\nmov ebp, r15d\nmov ebx, [rsp+88h+var_3C]\nmov eax, 2\nadd ebp, 1\njmp loc_138D\nloc_1480:\nmov edx, ebx\nmov r12d, 2\nmov ebx, [rsp+88h+var_74]\njmp loc_1336\nloc_1491:\nmov ebp, [rsp+88h+var_78]\nmov ecx, [rsp+88h+var_54]\nmov r11d, 2\nmov r12d, [rsp+88h+var_50]\nmov edi, [rsp+88h+var_4C]\nmov ebx, [rsp+88h+var_48]\nmov r9d, [rsp+88h+var_44]\nadd ebp, 1\nmov r15d, [rsp+88h+var_40]\njmp loc_13C5\nloc_14C0:\nmov esi, ebp\nmov ebx, ecx\nmov ebp, edx\nadd r13d, 1\nmov edi, 2\njmp loc_134D\nloc_14D4:\nmov edx, [rsp+88h+var_5C]\nmov r13d, [rsp+88h+var_58]\nadd r12d, 1\nmov r9d, 2\njmp loc_13E2\nloc_14EC:\nmov ebx, [rsp+88h+var_60]\nmov ebp, ecx\nadd r13d, 1\nmov esi, 2\njmp loc_13FF\nloc_1500:\nmov r12d, ebp\nmov r15d, [rsp+88h+var_6C]\nmov r13d, [rsp+88h+var_68]\nmov eax, 2\nmov ebx, [rsp+88h+var_64]\nadd r12d, 1\njmp loc_1426\nloc_151F:\nadd r15d, 3\njmp loc_143D\nloc_1528:\nmov r15d, 2\njmp loc_143D", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1)\n{\n unsigned int v1; // r15d\n unsigned int v2; // r13d\n int v3; // r15d\n unsigned int v4; // ebx\n int v5; // ebp\n unsigned int v6; // edx\n int v7; // r13d\n int v8; // ecx\n unsigned int v9; // ebx\n unsigned int v10; // edi\n int v11; // r12d\n unsigned int v12; // r15d\n unsigned int v13; // r14d\n int v14; // r15d\n int v15; // r13d\n int v16; // esi\n int v17; // ebx\n int v18; // ecx\n int v19; // r13d\n int v20; // edx\n int v21; // ebx\n int v22; // r12d\n int v23; // r14d\n int v24; // ebx\n int v25; // eax\n int v26; // ebx\n int v27; // ebx\n int v28; // ebp\n int v29; // edi\n int v30; // ebp\n int v31; // ebx\n int v32; // edx\n int v33; // r13d\n int v34; // ebx\n int v35; // ebp\n int v36; // eax\n int v37; // r12d\n int v38; // r11d\n int v39; // ebp\n int v40; // r9d\n unsigned int v41; // r15d\n int v42; // r13d\n unsigned int v43; // ebx\n int v44; // ebp\n int v45; // esi\n int v46; // r15d\n unsigned int v47; // r13d\n int v48; // r12d\n int v49; // eax\n unsigned int v50; // ebx\n int v52; // [rsp+4h] [rbp-84h]\n int v53; // [rsp+8h] [rbp-80h]\n int v54; // [rsp+Ch] [rbp-7Ch]\n int v55; // [rsp+10h] [rbp-78h]\n int v56; // [rsp+14h] [rbp-74h]\n int v57; // [rsp+18h] [rbp-70h]\n int v58; // [rsp+1Ch] [rbp-6Ch]\n unsigned int v59; // [rsp+20h] [rbp-68h]\n unsigned int v60; // [rsp+24h] [rbp-64h]\n unsigned int v61; // [rsp+28h] [rbp-60h]\n unsigned int v62; // [rsp+2Ch] [rbp-5Ch]\n int v63; // [rsp+30h] [rbp-58h]\n int v64; // [rsp+34h] [rbp-54h]\n int v65; // [rsp+38h] [rbp-50h]\n unsigned int v66; // [rsp+3Ch] [rbp-4Ch]\n unsigned int v67; // [rsp+40h] [rbp-48h]\n int v68; // [rsp+44h] [rbp-44h]\n unsigned int v69; // [rsp+48h] [rbp-40h]\n int v70; // [rsp+4Ch] [rbp-3Ch]\n\n if ( a1 )\n {\n v1 = a1;\n if ( a1 != 1 )\n {\n v2 = a1 - 1;\n v3 = 0;\n while ( v2 != 1 )\n {\n v4 = v2 - 1;\n v58 = v3;\n v59 = v2;\n v5 = 0;\n v60 = v2 - 1;\n while ( v4 != 1 )\n {\n v6 = v4 - 1;\n v61 = v4;\n v7 = 0;\n v8 = v5;\n v9 = v4 - 1;\n while ( v9 != 1 )\n {\n v62 = v6;\n v10 = v9 - 1;\n v11 = 0;\n v63 = v7;\n v12 = v9 - 1;\n while ( v12 != 1 )\n {\n v64 = v8;\n v65 = v11;\n v13 = v12 - 1;\n v55 = 0;\n v66 = v10;\n v67 = v9;\n v68 = v12 - 1;\n v69 = v12;\n while ( v13 != 1 )\n {\n v14 = 0;\n v70 = v13 - 1;\n v15 = v13 - 1;\n while ( v15 != 1 )\n {\n v52 = v13;\n v16 = 0;\n v53 = v15 - 1;\n v17 = v15 - 1;\n v54 = v15;\n while ( v17 != 1 )\n {\n v18 = v17;\n v19 = 0;\n v20 = v17 - 1;\n v21 = v17 - 1;\n while ( 1 )\n {\n v22 = v21;\n if ( v21 == 1 )\n break;\n v56 = v21;\n v23 = 0;\n v24 = v20;\n while ( 1 )\n {\n v57 = v18;\n v25 = func0((unsigned int)(v22 - 1));\n v18 = v57;\n v23 += v25;\n v22 -= 2;\n if ( !v22 )\n break;\n if ( v22 == 1 )\n {\n v20 = v24;\n v26 = v56;\n goto LABEL_23;\n }\n }\n v20 = v24;\n v22 = 2;\n v26 = v56;\nLABEL_23:\n v19 += v23 + v22;\n v21 = v26 - 2;\n if ( !v21 )\n {\n v27 = v57;\n v28 = v20;\n v29 = 1;\n goto LABEL_25;\n }\n }\n v27 = v18;\n v28 = v20;\n ++v19;\n v29 = 2;\nLABEL_25:\n v17 = v27 - 2;\n v16 += v19 + v29;\n if ( v28 == 1 )\n {\n v13 = v52;\n v30 = v53;\n v31 = v16;\n v32 = 1;\n v33 = v54;\n goto LABEL_27;\n }\n }\n v13 = v52;\n v30 = v53;\n v32 = 2;\n v33 = v54;\n v31 = v16 + 1;\nLABEL_27:\n v15 = v33 - 2;\n v14 += v31 + v32;\n if ( v30 == 1 )\n {\n v34 = v70;\n v35 = v14;\n v36 = 1;\n goto LABEL_29;\n }\n }\n v34 = v70;\n v36 = 2;\n v35 = v14 + 1;\nLABEL_29:\n v13 -= 2;\n v55 += v35 + v36;\n if ( v34 == 1 )\n {\n v8 = v64;\n v37 = v65;\n v38 = 1;\n v39 = v55;\n v10 = v66;\n v9 = v67;\n v40 = v68;\n v41 = v69;\n goto LABEL_31;\n }\n }\n v8 = v64;\n v38 = 2;\n v37 = v65;\n v10 = v66;\n v9 = v67;\n v40 = v68;\n v39 = v55 + 1;\n v41 = v69;\nLABEL_31:\n v12 = v41 - 2;\n v11 = v39 + v38 + v37;\n if ( v40 == 1 )\n {\n v6 = v62;\n v42 = v63;\n goto LABEL_33;\n }\n }\n v6 = v62;\n v42 = v63;\n ++v11;\n v40 = 2;\nLABEL_33:\n v9 -= 2;\n v7 = v11 + v40 + v42;\n if ( v10 == 1 )\n {\n v43 = v61;\n v44 = v8;\n v45 = 1;\n goto LABEL_35;\n }\n }\n v43 = v61;\n v44 = v8;\n ++v7;\n v45 = 2;\nLABEL_35:\n v4 = v43 - 2;\n v5 = v7 + v45 + v44;\n if ( v6 == 1 )\n {\n v46 = v58;\n v47 = v59;\n v48 = v5;\n v49 = 1;\n v50 = v60;\n goto LABEL_37;\n }\n }\n v46 = v58;\n v47 = v59;\n v49 = 2;\n v50 = v60;\n v48 = v5 + 1;\nLABEL_37:\n v2 = v47 - 2;\n v3 = v48 + v49 + v46;\n if ( v50 == 1 )\n return (unsigned int)(v3 + 1);\n }\n return (unsigned int)(v3 + 3);\n }\n }\n else\n {\n return 2;\n }\n return v1;\n}", + "ida_strip_asm": "sub_11F0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 58h\ntest edi, edi\njz loc_1528\nmov r15d, edi\ncmp edi, 1\njz loc_143D\nlea r13d, [rdi-1]\nxor r15d, r15d\nloc_121D:\ncmp r13d, 1\njz loc_151F\nlea ebx, [r13-1]\nmov [rsp+88h+var_6C], r15d\nxor r12d, r12d\nmov [rsp+88h+var_68], r13d\nmov ebp, r12d\nmov [rsp+88h+var_64], ebx\nloc_123F:\ncmp ebx, 1\njz loc_1500\nlea edx, [rbx-1]\nmov [rsp+88h+var_60], ebx\nxor r13d, r13d\nmov ecx, ebp\nmov ebx, edx\nloc_1256:\ncmp ebx, 1\njz loc_14EC\nmov [rsp+88h+var_5C], edx\nlea edi, [rbx-1]\nxor r12d, r12d\nmov [rsp+88h+var_58], r13d\nmov r15d, edi\nloc_1271:\ncmp r15d, 1\njz loc_14D4\nlea r9d, [r15-1]\nxor ebp, ebp\nmov [rsp+88h+var_54], ecx\nmov [rsp+88h+var_50], r12d\nmov r14d, r9d\nmov [rsp+88h+var_78], ebp\nmov [rsp+88h+var_4C], edi\nmov [rsp+88h+var_48], ebx\nmov [rsp+88h+var_44], r9d\nmov [rsp+88h+var_40], r15d\nloc_12A3:\ncmp r14d, 1\njz loc_1491\nlea ebx, [r14-1]\nxor r15d, r15d\nmov [rsp+88h+var_3C], ebx\nmov r13d, ebx\nloc_12BB:\ncmp r13d, 1\njz loc_146C\nlea ebp, [r13-1]\nmov [rsp+88h+var_84], r14d\nxor esi, esi\nmov [rsp+88h+var_80], ebp\nmov ebx, ebp\nmov [rsp+88h+var_7C], r13d\nloc_12DB:\ncmp ebx, 1\njz loc_144F\nlea ebp, [rbx-1]\nmov ecx, ebx\nxor r13d, r13d\nmov r14d, ebp\nmov edx, ebp\nmov ebp, esi\nmov ebx, r14d\nloc_12F6:\nmov r12d, ebx\ncmp ebx, 1\njz loc_14C0\nmov [rsp+88h+var_74], ebx\nxor r14d, r14d\nmov ebx, edx\nloc_130B:\nlea edi, [r12-1]\nmov [rsp+88h+var_70], ecx\ncall sub_11F0\nmov ecx, [rsp+88h+var_70]\nadd r14d, eax\nsub r12d, 2\njz loc_1480\ncmp r12d, 1\njnz short loc_130B\nmov edx, ebx\nmov ebx, [rsp+88h+var_74]\nloc_1336:\nlea eax, [r14+r12]\nadd r13d, eax\nsub ebx, 2\njnz short loc_12F6\nmov esi, ebp\nmov ebx, ecx\nmov ebp, edx\nmov edi, 1\nloc_134D:\nadd edi, r13d\nsub ebx, 2\nadd esi, edi\ncmp ebp, 1\njnz short loc_12DB\nmov r14d, [rsp+88h+var_84]\nmov ebp, [rsp+88h+var_80]\nmov ebx, esi\nmov edx, 1\nmov r13d, [rsp+88h+var_7C]\nloc_136F:\nadd edx, ebx\nsub r13d, 2\nadd r15d, edx\ncmp ebp, 1\njnz loc_12BB\nmov ebx, [rsp+88h+var_3C]\nmov ebp, r15d\nmov eax, 1\nloc_138D:\nadd eax, ebp\nsub r14d, 2\nadd [rsp+88h+var_78], eax\ncmp ebx, 1\njnz loc_12A3\nmov ecx, [rsp+88h+var_54]\nmov r12d, [rsp+88h+var_50]\nmov r11d, 1\nmov ebp, [rsp+88h+var_78]\nmov edi, [rsp+88h+var_4C]\nmov ebx, [rsp+88h+var_48]\nmov r9d, [rsp+88h+var_44]\nmov r15d, [rsp+88h+var_40]\nloc_13C5:\nadd r11d, ebp\nsub r15d, 2\nadd r12d, r11d\ncmp r9d, 1\njnz loc_1271\nmov edx, [rsp+88h+var_5C]\nmov r13d, [rsp+88h+var_58]\nloc_13E2:\nadd r9d, r12d\nsub ebx, 2\nadd r13d, r9d\ncmp edi, 1\njnz loc_1256\nmov ebx, [rsp+88h+var_60]\nmov ebp, ecx\nmov esi, 1\nloc_13FF:\nadd esi, r13d\nsub ebx, 2\nadd ebp, esi\ncmp edx, 1\njnz loc_123F\nmov r15d, [rsp+88h+var_6C]\nmov r13d, [rsp+88h+var_68]\nmov r12d, ebp\nmov eax, 1\nmov ebx, [rsp+88h+var_64]\nloc_1426:\nadd eax, r12d\nsub r13d, 2\nadd r15d, eax\ncmp ebx, 1\njnz loc_121D\nadd r15d, 1\nloc_143D:\nadd rsp, 58h\nmov eax, r15d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_144F:\nmov ebx, esi\nmov r14d, [rsp+88h+var_84]\nmov ebp, [rsp+88h+var_80]\nmov edx, 2\nmov r13d, [rsp+88h+var_7C]\nadd ebx, 1\njmp loc_136F\nloc_146C:\nmov ebp, r15d\nmov ebx, [rsp+88h+var_3C]\nmov eax, 2\nadd ebp, 1\njmp loc_138D\nloc_1480:\nmov edx, ebx\nmov r12d, 2\nmov ebx, [rsp+88h+var_74]\njmp loc_1336\nloc_1491:\nmov ebp, [rsp+88h+var_78]\nmov ecx, [rsp+88h+var_54]\nmov r11d, 2\nmov r12d, [rsp+88h+var_50]\nmov edi, [rsp+88h+var_4C]\nmov ebx, [rsp+88h+var_48]\nmov r9d, [rsp+88h+var_44]\nadd ebp, 1\nmov r15d, [rsp+88h+var_40]\njmp loc_13C5\nloc_14C0:\nmov esi, ebp\nmov ebx, ecx\nmov ebp, edx\nadd r13d, 1\nmov edi, 2\njmp loc_134D\nloc_14D4:\nmov edx, [rsp+88h+var_5C]\nmov r13d, [rsp+88h+var_58]\nadd r12d, 1\nmov r9d, 2\njmp loc_13E2\nloc_14EC:\nmov ebx, [rsp+88h+var_60]\nmov ebp, ecx\nadd r13d, 1\nmov esi, 2\njmp loc_13FF\nloc_1500:\nmov r12d, ebp\nmov r15d, [rsp+88h+var_6C]\nmov r13d, [rsp+88h+var_68]\nmov eax, 2\nmov ebx, [rsp+88h+var_64]\nadd r12d, 1\njmp loc_1426\nloc_151F:\nadd r15d, 3\njmp loc_143D\nloc_1528:\nmov r15d, 2\njmp loc_143D", + "ida_strip_pseudo": "__int64 __fastcall sub_11F0(unsigned int a1)\n{\n unsigned int v1; // r15d\n unsigned int v2; // r13d\n int v3; // r15d\n unsigned int v4; // ebx\n int v5; // ebp\n unsigned int v6; // edx\n int v7; // r13d\n int v8; // ecx\n unsigned int v9; // ebx\n unsigned int v10; // edi\n int v11; // r12d\n unsigned int v12; // r15d\n unsigned int v13; // r14d\n int v14; // r15d\n int v15; // r13d\n int v16; // esi\n int v17; // ebx\n int v18; // ecx\n int v19; // r13d\n int v20; // edx\n int v21; // ebx\n int v22; // r12d\n int v23; // r14d\n int v24; // ebx\n int v25; // eax\n int v26; // ebx\n int v27; // ebx\n int v28; // ebp\n int v29; // edi\n int v30; // ebp\n int v31; // ebx\n int v32; // edx\n int v33; // r13d\n int v34; // ebx\n int v35; // ebp\n int v36; // eax\n int v37; // r12d\n int v38; // r11d\n int v39; // ebp\n int v40; // r9d\n unsigned int v41; // r15d\n int v42; // r13d\n unsigned int v43; // ebx\n int v44; // ebp\n int v45; // esi\n int v46; // r15d\n unsigned int v47; // r13d\n int v48; // r12d\n int v49; // eax\n unsigned int v50; // ebx\n int v52; // [rsp+4h] [rbp-84h]\n int v53; // [rsp+8h] [rbp-80h]\n int v54; // [rsp+Ch] [rbp-7Ch]\n int v55; // [rsp+10h] [rbp-78h]\n int v56; // [rsp+14h] [rbp-74h]\n int v57; // [rsp+18h] [rbp-70h]\n int v58; // [rsp+1Ch] [rbp-6Ch]\n unsigned int v59; // [rsp+20h] [rbp-68h]\n unsigned int v60; // [rsp+24h] [rbp-64h]\n unsigned int v61; // [rsp+28h] [rbp-60h]\n unsigned int v62; // [rsp+2Ch] [rbp-5Ch]\n int v63; // [rsp+30h] [rbp-58h]\n int v64; // [rsp+34h] [rbp-54h]\n int v65; // [rsp+38h] [rbp-50h]\n unsigned int v66; // [rsp+3Ch] [rbp-4Ch]\n unsigned int v67; // [rsp+40h] [rbp-48h]\n int v68; // [rsp+44h] [rbp-44h]\n unsigned int v69; // [rsp+48h] [rbp-40h]\n int v70; // [rsp+4Ch] [rbp-3Ch]\n\n if ( a1 )\n {\n v1 = a1;\n if ( a1 != 1 )\n {\n v2 = a1 - 1;\n v3 = 0;\n while ( v2 != 1 )\n {\n v4 = v2 - 1;\n v58 = v3;\n v59 = v2;\n v5 = 0;\n v60 = v2 - 1;\n while ( v4 != 1 )\n {\n v6 = v4 - 1;\n v61 = v4;\n v7 = 0;\n v8 = v5;\n v9 = v4 - 1;\n while ( v9 != 1 )\n {\n v62 = v6;\n v10 = v9 - 1;\n v11 = 0;\n v63 = v7;\n v12 = v9 - 1;\n while ( v12 != 1 )\n {\n v64 = v8;\n v65 = v11;\n v13 = v12 - 1;\n v55 = 0;\n v66 = v10;\n v67 = v9;\n v68 = v12 - 1;\n v69 = v12;\n while ( v13 != 1 )\n {\n v14 = 0;\n v70 = v13 - 1;\n v15 = v13 - 1;\n while ( v15 != 1 )\n {\n v52 = v13;\n v16 = 0;\n v53 = v15 - 1;\n v17 = v15 - 1;\n v54 = v15;\n while ( v17 != 1 )\n {\n v18 = v17;\n v19 = 0;\n v20 = v17 - 1;\n v21 = v17 - 1;\n while ( 1 )\n {\n v22 = v21;\n if ( v21 == 1 )\n break;\n v56 = v21;\n v23 = 0;\n v24 = v20;\n while ( 1 )\n {\n v57 = v18;\n v25 = sub_11F0((unsigned int)(v22 - 1));\n v18 = v57;\n v23 += v25;\n v22 -= 2;\n if ( !v22 )\n break;\n if ( v22 == 1 )\n {\n v20 = v24;\n v26 = v56;\n goto LABEL_23;\n }\n }\n v20 = v24;\n v22 = 2;\n v26 = v56;\nLABEL_23:\n v19 += v23 + v22;\n v21 = v26 - 2;\n if ( !v21 )\n {\n v27 = v57;\n v28 = v20;\n v29 = 1;\n goto LABEL_25;\n }\n }\n v27 = v18;\n v28 = v20;\n ++v19;\n v29 = 2;\nLABEL_25:\n v17 = v27 - 2;\n v16 += v19 + v29;\n if ( v28 == 1 )\n {\n v13 = v52;\n v30 = v53;\n v31 = v16;\n v32 = 1;\n v33 = v54;\n goto LABEL_27;\n }\n }\n v13 = v52;\n v30 = v53;\n v32 = 2;\n v33 = v54;\n v31 = v16 + 1;\nLABEL_27:\n v15 = v33 - 2;\n v14 += v31 + v32;\n if ( v30 == 1 )\n {\n v34 = v70;\n v35 = v14;\n v36 = 1;\n goto LABEL_29;\n }\n }\n v34 = v70;\n v36 = 2;\n v35 = v14 + 1;\nLABEL_29:\n v13 -= 2;\n v55 += v35 + v36;\n if ( v34 == 1 )\n {\n v8 = v64;\n v37 = v65;\n v38 = 1;\n v39 = v55;\n v10 = v66;\n v9 = v67;\n v40 = v68;\n v41 = v69;\n goto LABEL_31;\n }\n }\n v8 = v64;\n v38 = 2;\n v37 = v65;\n v10 = v66;\n v9 = v67;\n v40 = v68;\n v39 = v55 + 1;\n v41 = v69;\nLABEL_31:\n v12 = v41 - 2;\n v11 = v39 + v38 + v37;\n if ( v40 == 1 )\n {\n v6 = v62;\n v42 = v63;\n goto LABEL_33;\n }\n }\n v6 = v62;\n v42 = v63;\n ++v11;\n v40 = 2;\nLABEL_33:\n v9 -= 2;\n v7 = v11 + v40 + v42;\n if ( v10 == 1 )\n {\n v43 = v61;\n v44 = v8;\n v45 = 1;\n goto LABEL_35;\n }\n }\n v43 = v61;\n v44 = v8;\n ++v7;\n v45 = 2;\nLABEL_35:\n v4 = v43 - 2;\n v5 = v7 + v45 + v44;\n if ( v6 == 1 )\n {\n v46 = v58;\n v47 = v59;\n v48 = v5;\n v49 = 1;\n v50 = v60;\n goto LABEL_37;\n }\n }\n v46 = v58;\n v47 = v59;\n v49 = 2;\n v50 = v60;\n v48 = v5 + 1;\nLABEL_37:\n v2 = v47 - 2;\n v3 = v48 + v49 + v46;\n if ( v50 == 1 )\n return (unsigned int)(v3 + 1);\n }\n return (unsigned int)(v3 + 3);\n }\n }\n else\n {\n return 2;\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11F0(unsigned int a1) {\n unsigned int v1;\n unsigned int v2;\n int v3;\n unsigned int v4;\n int v5;\n unsigned int v6;\n int v7;\n int v8;\n unsigned int v9;\n unsigned int v10;\n int v11;\n unsigned int v12;\n unsigned int v13;\n int v14;\n int v15;\n int v16;\n int v17;\n int v18;\n int v19;\n int v20;\n int v21;\n int v22;\n int v23;\n int v24;\n int v25;\n int v26;\n int v27;\n int v28;\n int v29;\n int v30;\n int v31;\n int v32;\n int v33;\n int v34;\n int v35;\n int v36;\n int v37;\n int v38;\n int v39;\n int v40;\n unsigned int v41;\n int v42;\n unsigned int v43;\n int v44;\n int v45;\n int v46;\n unsigned int v47;\n int v48;\n int v49;\n unsigned int v50;\n int v52;\n int v53;\n int v54;\n int v55;\n int v56;\n int v57;\n int v58;\n unsigned int v59;\n unsigned int v60;\n unsigned int v61;\n unsigned int v62;\n int v63;\n int v64;\n int v65;\n unsigned int v66;\n unsigned int v67;\n int v68;\n unsigned int v69;\n int v70;\n if (a1) {\n v1 = a1;\n if (a1 != 1) {\n v2 = a1 - 1;\n v3 = 0;\n while (v2 != 1) {\n v4 = v2 - 1;\n v58 = v3;\n v59 = v2;\n v5 = 0;\n v60 = v2 - 1;\n while (v4 != 1) {\n v6 = v4 - 1;\n v61 = v4;\n v7 = 0;\n v8 = v5;\n v9 = v4 - 1;\n while (v9 != 1) {\n v62 = v6;\n v10 = v9 - 1;\n v11 = 0;\n v63 = v7;\n v12 = v9 - 1;\n while (v12 != 1) {\n v64 = v8;\n v65 = v11;\n v13 = v12 - 1;\n v55 = 0;\n v66 = v10;\n v67 = v9;\n v68 = v12 - 1;\n v69 = v12;\n while (v13 != 1) {\n v14 = 0;\n v70 = v13 - 1;\n v15 = v13 - 1;\n while (v15 != 1) {\n v52 = v13;\n v16 = 0;\n v53 = v15 - 1;\n v17 = v15 - 1;\n v54 = v15;\n while (v17 != 1) {\n v18 = v17;\n v19 = 0;\n v20 = v17 - 1;\n v21 = v17 - 1;\n while (1) {\n v22 = v21;\n if (v21 == 1) break;\n v56 = v21;\n v23 = 0;\n v24 = v20;\n while (1) {\n v57 = v18;\n v25 = sub_11F0((unsigned int)(v22 - 1));\n v18 = v57;\n v23 += v25;\n v22 -= 2;\n if (!v22) break;\n if (v22 == 1) {\n v20 = v24;\n v26 = v56;\n goto LABEL_23;\n }\n }\n v20 = v24;\n v22 = 2;\n v26 = v56;\n LABEL_23:\n v19 += v23 + v22;\n v21 = v26 - 2;\n if (!v21) {\n v27 = v57;\n v28 = v20;\n v29 = 1;\n goto LABEL_25;\n }\n }\n v27 = v18;\n v28 = v20;\n ++v19;\n v29 = 2;\n LABEL_25:\n v17 = v27 - 2;\n v16 += v19 + v29;\n if (v28 == 1) {\n v13 = v52;\n v30 = v53;\n v31 = v16;\n v32 = 1;\n v33 = v54;\n goto LABEL_27;\n }\n }\n v13 = v52;\n v30 = v53;\n v32 = 2;\n v33 = v54;\n v31 = v16 + 1;\n LABEL_27:\n v15 = v33 - 2;\n v14 += v31 + v32;\n if (v30 == 1) {\n v34 = v70;\n v35 = v14;\n v36 = 1;\n goto LABEL_29;\n }\n }\n v34 = v70;\n v36 = 2;\n v35 = v14 + 1;\n LABEL_29:\n v13 -= 2;\n v55 += v35 + v36;\n if (v34 == 1) {\n v8 = v64;\n v37 = v65;\n v38 = 1;\n v39 = v55;\n v10 = v66;\n v9 = v67;\n v40 = v68;\n v41 = v69;\n goto LABEL_31;\n }\n }\n v8 = v64;\n v38 = 2;\n v37 = v65;\n v10 = v66;\n v9 = v67;\n v40 = v68;\n v39 = v55 + 1;\n v41 = v69;\n LABEL_31:\n v12 = v41 - 2;\n v11 = v39 + v38 + v37;\n if (v40 == 1) {\n v6 = v62;\n v42 = v63;\n goto LABEL_33;\n }\n }\n v6 = v62;\n v42 = v63;\n ++v11;\n v40 = 2;\n LABEL_33:\n v9 -= 2;\n v7 = v11 + v40 + v42;\n if (v10 == 1) {\n v43 = v61;\n v44 = v8;\n v45 = 1;\n goto LABEL_35;\n }\n }\n v43 = v61;\n v44 = v8;\n ++v7;\n v45 = 2;\n LABEL_35:\n v4 = v43 - 2;\n v5 = v7 + v45 + v44;\n if (v6 == 1) {\n v46 = v58;\n v47 = v59;\n v48 = v5;\n v49 = 1;\n v50 = v60;\n goto LABEL_37;\n }\n }\n v46 = v58;\n v47 = v59;\n v49 = 2;\n v50 = v60;\n v48 = v5 + 1;\n LABEL_37:\n v2 = v47 - 2;\n v3 = v48 + v49 + v46;\n if (v50 == 1) return (unsigned int)(v3 + 1);\n }\n return (unsigned int)(v3 + 3);\n }\n } else {\n return 2;\n }\n return v1;\n}", + "ida_pseudo_norm": "long long func0(unsigned int a1) {\n unsigned int v1;\n unsigned int v2;\n int v3;\n unsigned int v4;\n int v5;\n unsigned int v6;\n int v7;\n int v8;\n unsigned int v9;\n unsigned int v10;\n int v11;\n unsigned int v12;\n unsigned int v13;\n int v14;\n int v15;\n int v16;\n int v17;\n int v18;\n int v19;\n int v20;\n int v21;\n int v22;\n int v23;\n int v24;\n int v25;\n int v26;\n int v27;\n int v28;\n int v29;\n int v30;\n int v31;\n int v32;\n int v33;\n int v34;\n int v35;\n int v36;\n int v37;\n int v38;\n int v39;\n int v40;\n unsigned int v41;\n int v42;\n unsigned int v43;\n int v44;\n int v45;\n int v46;\n unsigned int v47;\n int v48;\n int v49;\n unsigned int v50;\n int v52;\n int v53;\n int v54;\n int v55;\n int v56;\n int v57;\n int v58;\n unsigned int v59;\n unsigned int v60;\n unsigned int v61;\n unsigned int v62;\n int v63;\n int v64;\n int v65;\n unsigned int v66;\n unsigned int v67;\n int v68;\n unsigned int v69;\n int v70;\n if (a1) {\n v1 = a1;\n if (a1 != 1) {\n v2 = a1 - 1;\n v3 = 0;\n while (v2 != 1) {\n v4 = v2 - 1;\n v58 = v3;\n v59 = v2;\n v5 = 0;\n v60 = v2 - 1;\n while (v4 != 1) {\n v6 = v4 - 1;\n v61 = v4;\n v7 = 0;\n v8 = v5;\n v9 = v4 - 1;\n while (v9 != 1) {\n v62 = v6;\n v10 = v9 - 1;\n v11 = 0;\n v63 = v7;\n v12 = v9 - 1;\n while (v12 != 1) {\n v64 = v8;\n v65 = v11;\n v13 = v12 - 1;\n v55 = 0;\n v66 = v10;\n v67 = v9;\n v68 = v12 - 1;\n v69 = v12;\n while (v13 != 1) {\n v14 = 0;\n v70 = v13 - 1;\n v15 = v13 - 1;\n while (v15 != 1) {\n v52 = v13;\n v16 = 0;\n v53 = v15 - 1;\n v17 = v15 - 1;\n v54 = v15;\n while (v17 != 1) {\n v18 = v17;\n v19 = 0;\n v20 = v17 - 1;\n v21 = v17 - 1;\n while (1) {\n v22 = v21;\n if (v21 == 1) break;\n v56 = v21;\n v23 = 0;\n v24 = v20;\n while (1) {\n v57 = v18;\n v25 = func0((unsigned int)(v22 - 1));\n v18 = v57;\n v23 += v25;\n v22 -= 2;\n if (!v22) break;\n if (v22 == 1) {\n v20 = v24;\n v26 = v56;\n goto LABEL_23;\n }\n }\n v20 = v24;\n v22 = 2;\n v26 = v56;\n LABEL_23:\n v19 += v23 + v22;\n v21 = v26 - 2;\n if (!v21) {\n v27 = v57;\n v28 = v20;\n v29 = 1;\n goto LABEL_25;\n }\n }\n v27 = v18;\n v28 = v20;\n ++v19;\n v29 = 2;\n LABEL_25:\n v17 = v27 - 2;\n v16 += v19 + v29;\n if (v28 == 1) {\n v13 = v52;\n v30 = v53;\n v31 = v16;\n v32 = 1;\n v33 = v54;\n goto LABEL_27;\n }\n }\n v13 = v52;\n v30 = v53;\n v32 = 2;\n v33 = v54;\n v31 = v16 + 1;\n LABEL_27:\n v15 = v33 - 2;\n v14 += v31 + v32;\n if (v30 == 1) {\n v34 = v70;\n v35 = v14;\n v36 = 1;\n goto LABEL_29;\n }\n }\n v34 = v70;\n v36 = 2;\n v35 = v14 + 1;\n LABEL_29:\n v13 -= 2;\n v55 += v35 + v36;\n if (v34 == 1) {\n v8 = v64;\n v37 = v65;\n v38 = 1;\n v39 = v55;\n v10 = v66;\n v9 = v67;\n v40 = v68;\n v41 = v69;\n goto LABEL_31;\n }\n }\n v8 = v64;\n v38 = 2;\n v37 = v65;\n v10 = v66;\n v9 = v67;\n v40 = v68;\n v39 = v55 + 1;\n v41 = v69;\n LABEL_31:\n v12 = v41 - 2;\n v11 = v39 + v38 + v37;\n if (v40 == 1) {\n v6 = v62;\n v42 = v63;\n goto LABEL_33;\n }\n }\n v6 = v62;\n v42 = v63;\n ++v11;\n v40 = 2;\n LABEL_33:\n v9 -= 2;\n v7 = v11 + v40 + v42;\n if (v10 == 1) {\n v43 = v61;\n v44 = v8;\n v45 = 1;\n goto LABEL_35;\n }\n }\n v43 = v61;\n v44 = v8;\n ++v7;\n v45 = 2;\n LABEL_35:\n v4 = v43 - 2;\n v5 = v7 + v45 + v44;\n if (v6 == 1) {\n v46 = v58;\n v47 = v59;\n v48 = v5;\n v49 = 1;\n v50 = v60;\n goto LABEL_37;\n }\n }\n v46 = v58;\n v47 = v59;\n v49 = 2;\n v50 = v60;\n v48 = v5 + 1;\n LABEL_37:\n v2 = v47 - 2;\n v3 = v48 + v49 + v46;\n if (v50 == 1) return (unsigned int)(v3 + 1);\n }\n return (unsigned int)(v3 + 3);\n }\n } else {\n return 2;\n }\n return v1;\n}" + }, + { + "index": 390, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(char* list[], int size, const char* format) {\n char** result = malloc(size * sizeof(char*));\n for (int i = 0; i < size; i++) {\n result[i] = malloc(100);\n sprintf(result[i], format, list[i]);\n }\n return result;\n}", + "test": "int main() {\n\n // First test case\n\n char* list1[] = {\"1\", \"2\", \"3\", \"4\"};\n\n char** res1 = func0(list1, 4, \"temp%s\");\n\n assert(strcmp(res1[0], \"temp1\") == 0);\n\n assert(strcmp(res1[1], \"temp2\") == 0);\n\n assert(strcmp(res1[2], \"temp3\") == 0);\n\n assert(strcmp(res1[3], \"temp4\") == 0);\n\n for(int i = 0; i < 4; i++) free(res1[i]);\n\n free(res1);\n\n\n\n // Second test case\n\n char* list2[] = {\"a\", \"b\", \"c\", \"d\"};\n\n char** res2 = func0(list2, 4, \"python%s\");\n\n assert(strcmp(res2[0], \"pythona\") == 0);\n\n assert(strcmp(res2[1], \"pythonb\") == 0);\n\n assert(strcmp(res2[2], \"pythonc\") == 0);\n\n assert(strcmp(res2[3], \"pythond\") == 0);\n\n for(int i = 0; i < 4; i++) free(res2[i]);\n\n free(res2);\n\n\n\n // Third test case\n\n char* list3[] = {\"5\", \"6\", \"7\", \"8\"};\n\n char** res3 = func0(list3, 4, \"string%s\");\n\n assert(strcmp(res3[0], \"string5\") == 0);\n\n assert(strcmp(res3[1], \"string6\") == 0);\n\n assert(strcmp(res3[2], \"string7\") == 0);\n\n assert(strcmp(res3[3], \"string8\") == 0);\n\n for(int i = 0; i < 4; i++) free(res3[i]);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x38,%rsp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmov %rdx,-0x38(%rbp)\nmov -0x2c(%rbp),%eax\ncltq\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 10e0 \nmov %rax,-0x18(%rbp)\nmovl $0x0,-0x1c(%rbp)\njmp 1287 \nmov -0x1c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rbx\nmov $0x64,%edi\ncallq 10e0 \nmov %rax,(%rbx)\nmov -0x1c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rdx\nmov -0x1c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%rax\nmov -0x38(%rbp),%rcx\nmov %rcx,%rsi\nmov %rax,%rdi\nmov $0x0,%eax\ncallq 10f0 \naddl $0x1,-0x1c(%rbp)\nmov -0x1c(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 121f \nmov -0x18(%rbp),%rax\nadd $0x38,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+format], rdx\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_1C], 0\njmp short loc_1287\nloc_121F:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nlea rbx, [rdx+rax]\nmov edi, 64h ; 'd'; size\ncall _malloc\nmov [rbx], rax\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_1C]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov rax, [rax]\nmov rcx, [rbp+format]\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nadd [rbp+var_1C], 1\nloc_1287:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_2C]\njl short loc_121F\nmov rax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, int a2, const char *a3)\n{\n int i; // [rsp+24h] [rbp-1Ch]\n _QWORD *v6; // [rsp+28h] [rbp-18h]\n\n v6 = malloc(8LL * a2);\n for ( i = 0; i < a2; ++i )\n {\n v6[i] = malloc(0x64uLL);\n sprintf((char *)v6[i], a3, *(_QWORD *)(8LL * i + a1));\n }\n return v6;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+format], rdx\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_1C], 0\njmp short loc_1287\nloc_121F:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nlea rbx, [rdx+rax]\nmov edi, 64h ; 'd'; size\ncall _malloc\nmov [rbx], rax\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_1C]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov rax, [rax]\nmov rcx, [rbp+format]\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nadd [rbp+var_1C], 1\nloc_1287:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_2C]\njl short loc_121F\nmov rax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11E9(__int64 a1, int a2, const char *a3)\n{\n int i; // [rsp+24h] [rbp-1Ch]\n _QWORD *v6; // [rsp+28h] [rbp-18h]\n\n v6 = malloc(8LL * a2);\n for ( i = 0; i < a2; ++i )\n {\n v6[i] = malloc(0x64uLL);\n sprintf((char *)v6[i], a3, *(_QWORD *)(8LL * i + a1));\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11E9(long long a1, int a2, const char *a3) {\n int i;\n uint64_t *v6;\n v6 = malloc(8LL * a2);\n for (i = 0; i < a2; ++i) {\n v6[i] = malloc(100uLL);\n sprintf((char *)v6[i], a3, *(uint64_t *)(8LL * i + a1));\n }\n return v6;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, int a2, const char *a3) {\n int i;\n uint64_t *v6;\n v6 = malloc(8LL * a2);\n for (i = 0; i < a2; ++i) {\n v6[i] = malloc(100uLL);\n sprintf((char *)v6[i], a3, *(uint64_t *)(8LL * i + a1));\n }\n return v6;\n}" + }, + { + "index": 390, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(char* list[], int size, const char* format) {\n char** result = malloc(size * sizeof(char*));\n for (int i = 0; i < size; i++) {\n result[i] = malloc(100);\n sprintf(result[i], format, list[i]);\n }\n return result;\n}", + "test": "int main() {\n\n // First test case\n\n char* list1[] = {\"1\", \"2\", \"3\", \"4\"};\n\n char** res1 = func0(list1, 4, \"temp%s\");\n\n assert(strcmp(res1[0], \"temp1\") == 0);\n\n assert(strcmp(res1[1], \"temp2\") == 0);\n\n assert(strcmp(res1[2], \"temp3\") == 0);\n\n assert(strcmp(res1[3], \"temp4\") == 0);\n\n for(int i = 0; i < 4; i++) free(res1[i]);\n\n free(res1);\n\n\n\n // Second test case\n\n char* list2[] = {\"a\", \"b\", \"c\", \"d\"};\n\n char** res2 = func0(list2, 4, \"python%s\");\n\n assert(strcmp(res2[0], \"pythona\") == 0);\n\n assert(strcmp(res2[1], \"pythonb\") == 0);\n\n assert(strcmp(res2[2], \"pythonc\") == 0);\n\n assert(strcmp(res2[3], \"pythond\") == 0);\n\n for(int i = 0; i < 4; i++) free(res2[i]);\n\n free(res2);\n\n\n\n // Third test case\n\n char* list3[] = {\"5\", \"6\", \"7\", \"8\"};\n\n char** res3 = func0(list3, 4, \"string%s\");\n\n assert(strcmp(res3[0], \"string5\") == 0);\n\n assert(strcmp(res3[1], \"string6\") == 0);\n\n assert(strcmp(res3[2], \"string7\") == 0);\n\n assert(strcmp(res3[3], \"string8\") == 0);\n\n for(int i = 0; i < 4; i++) free(res3[i]);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%r12\nmov %esi,%ebx\nmov %rdx,%r13\nmovslq %esi,%rdi\nshl $0x3,%rdi\ncallq 10c0 \nmov %rax,%rbp\ntest %ebx,%ebx\njle 1232 \nlea -0x1(%rbx),%r14d\nmov $0x0,%ebx\nmov $0x64,%edi\ncallq 10c0 \nmov %rax,%rdi\nmov %rax,0x0(%rbp,%rbx,8)\nmov (%r12,%rbx,8),%r8\nmov %r13,%rcx\nmov $0x64,%edx\nmov $0x1,%esi\nmov $0x0,%eax\ncallq 10d0 <__sprintf_chk@plt>\nmov %rbx,%rax\nadd $0x1,%rbx\ncmp %r14,%rax\njne 11f9 \nmov %rbp,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbp, rdi\nmov ebx, esi\nmov r13, rdx\nmovsxd r12, esi\nshl r12, 3\nmov rdi, r12; size\ncall _malloc\nmov r14, rax\ntest ebx, ebx\njle short loc_1251\nmov rbx, rax\nadd r12, rax\nloc_1219:\nmov edi, 64h ; 'd'; size\ncall _malloc\nmov rdi, rax\nmov [rbx], rax\nmov r8, [rbp+0]\nmov rcx, r13\nmov edx, 64h ; 'd'\nmov esi, 2\nmov eax, 0\ncall ___sprintf_chk\nadd rbx, 8\nadd rbp, 8\ncmp rbx, r12\njnz short loc_1219\nloc_1251:\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(_QWORD *a1, int a2, __int64 a3)\n{\n _QWORD *v5; // rax\n _QWORD *v6; // r14\n _QWORD *v7; // rbx\n _QWORD *v8; // r12\n void *v9; // rax\n\n v5 = malloc(8LL * a2);\n v6 = v5;\n if ( a2 > 0 )\n {\n v7 = v5;\n v8 = &v5[a2];\n do\n {\n v9 = malloc(0x64uLL);\n *v7 = v9;\n __sprintf_chk(v9, 2LL, 100LL, a3, *a1);\n ++v7;\n ++a1;\n }\n while ( v7 != v8 );\n }\n return v6;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbp, rdi\nmov ebx, esi\nmov r13, rdx\nmovsxd r12, esi\nshl r12, 3\nmov rdi, r12; size\ncall _malloc\nmov r14, rax\ntest ebx, ebx\njle short loc_1251\nmov rbx, rax\nadd r12, rax\nloc_1219:\nmov edi, 64h ; 'd'; size\ncall _malloc\nmov rdi, rax\nmov [rbx], rax\nmov r8, [rbp+0]\nmov rcx, r13\nmov edx, 64h ; 'd'\nmov esi, 2\nmov eax, 0\ncall ___sprintf_chk\nadd rbx, 8\nadd rbp, 8\ncmp rbx, r12\njnz short loc_1219\nloc_1251:\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11E9(_QWORD *a1, int a2, __int64 a3)\n{\n _QWORD *v5; // rax\n _QWORD *v6; // r14\n _QWORD *v7; // rbx\n _QWORD *v8; // r12\n void *v9; // rax\n\n v5 = malloc(8LL * a2);\n v6 = v5;\n if ( a2 > 0 )\n {\n v7 = v5;\n v8 = &v5[a2];\n do\n {\n v9 = malloc(0x64uLL);\n *v7 = v9;\n __sprintf_chk(v9, 2LL, 100LL, a3, *a1);\n ++v7;\n ++a1;\n }\n while ( v7 != v8 );\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11E9(uint64_t *a1, int a2, long long a3) {\n uint64_t *v5;\n uint64_t *v6;\n uint64_t *v7;\n uint64_t *v8;\n void *v9;\n v5 = malloc(8LL * a2);\n v6 = v5;\n if (a2 > 0) {\n v7 = v5;\n v8 = &v5[a2];\n do {\n v9 = malloc(100uLL);\n *v7 = v9;\n __sprintf_chk(v9, 2LL, 100LL, a3, *a1);\n ++v7;\n ++a1;\n } while (v7 != v8);\n }\n return v6;\n}", + "ida_pseudo_norm": "uint64_t *func0(uint64_t *a1, int a2, long long a3) {\n uint64_t *v5;\n uint64_t *v6;\n uint64_t *v7;\n uint64_t *v8;\n void *v9;\n v5 = malloc(8LL * a2);\n v6 = v5;\n if (a2 > 0) {\n v7 = v5;\n v8 = &v5[a2];\n do {\n v9 = malloc(100uLL);\n *v7 = v9;\n __sprintf_chk(v9, 2LL, 100LL, a3, *a1);\n ++v7;\n ++a1;\n } while (v7 != v8);\n }\n return v6;\n}" + }, + { + "index": 390, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(char* list[], int size, const char* format) {\n char** result = malloc(size * sizeof(char*));\n for (int i = 0; i < size; i++) {\n result[i] = malloc(100);\n sprintf(result[i], format, list[i]);\n }\n return result;\n}", + "test": "int main() {\n\n // First test case\n\n char* list1[] = {\"1\", \"2\", \"3\", \"4\"};\n\n char** res1 = func0(list1, 4, \"temp%s\");\n\n assert(strcmp(res1[0], \"temp1\") == 0);\n\n assert(strcmp(res1[1], \"temp2\") == 0);\n\n assert(strcmp(res1[2], \"temp3\") == 0);\n\n assert(strcmp(res1[3], \"temp4\") == 0);\n\n for(int i = 0; i < 4; i++) free(res1[i]);\n\n free(res1);\n\n\n\n // Second test case\n\n char* list2[] = {\"a\", \"b\", \"c\", \"d\"};\n\n char** res2 = func0(list2, 4, \"python%s\");\n\n assert(strcmp(res2[0], \"pythona\") == 0);\n\n assert(strcmp(res2[1], \"pythonb\") == 0);\n\n assert(strcmp(res2[2], \"pythonc\") == 0);\n\n assert(strcmp(res2[3], \"pythond\") == 0);\n\n for(int i = 0; i < 4; i++) free(res2[i]);\n\n free(res2);\n\n\n\n // Third test case\n\n char* list3[] = {\"5\", \"6\", \"7\", \"8\"};\n\n char** res3 = func0(list3, 4, \"string%s\");\n\n assert(strcmp(res3[0], \"string5\") == 0);\n\n assert(strcmp(res3[1], \"string6\") == 0);\n\n assert(strcmp(res3[2], \"string7\") == 0);\n\n assert(strcmp(res3[3], \"string8\") == 0);\n\n for(int i = 0; i < 4; i++) free(res3[i]);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\nmov %rdx,%r13\npush %r12\npush %rbp\nmov %rdi,%rbp\nmovslq %esi,%rdi\npush %rbx\nmov %rdi,%rbx\nshl $0x3,%rdi\ncallq 10c0 \nmov %rax,%r12\ntest %ebx,%ebx\njle 16b6 \nlea -0x1(%rbx),%r14d\nxor %ebx,%ebx\nxchg %ax,%ax\nmov $0x64,%edi\ncallq 10c0 \nmov 0x0(%rbp,%rbx,8),%r8\nmov %r13,%rcx\nmov $0x64,%edx\nmov %rax,(%r12,%rbx,8)\nmov %rax,%rdi\nmov $0x1,%esi\nxor %eax,%eax\ncallq 10d0 <__sprintf_chk@plt>\nmov %rbx,%rax\nadd $0x1,%rbx\ncmp %rax,%r14\njne 1680 \npop %rbx\nmov %r12,%rax\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\nmov r13, rdx\npush r12\nmovsxd r12, esi\npush rbp\nmov rbp, rdi\npush rbx\nmov rbx, r12\nshl r12, 3\nmov rdi, r12; size\ncall _malloc\nmov r14, rax\ntest ebx, ebx\njle short loc_169E\nmov rbx, rax\nadd r12, rax\nnop dword ptr [rax+00000000h]\nloc_1668:\nmov edi, 64h ; 'd'; size\nadd rbx, 8\nadd rbp, 8\ncall _malloc\nmov r8, [rbp-8]\nmov rcx, r13\nmov edx, 64h ; 'd'\nmov [rbx-8], rax\nmov rdi, rax\nmov esi, 2\nxor eax, eax\ncall ___sprintf_chk\ncmp rbx, r12\njnz short loc_1668\nloc_169E:\npop rbx\nmov rax, r14\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2, __int64 a3)\n{\n char *v5; // rax\n char *v6; // r14\n char *v7; // rbx\n char *v8; // r12\n void *v9; // rax\n __int64 v10; // r8\n\n v5 = (char *)malloc(8LL * a2);\n v6 = v5;\n if ( a2 > 0 )\n {\n v7 = v5;\n v8 = &v5[8 * a2];\n do\n {\n v7 += 8;\n a1 += 8LL;\n v9 = malloc(0x64uLL);\n v10 = *(_QWORD *)(a1 - 8);\n *((_QWORD *)v7 - 1) = v9;\n __sprintf_chk(v9, 2LL, 100LL, a3, v10);\n }\n while ( v7 != v8 );\n }\n return v6;\n}", + "ida_strip_asm": "sub_1630:\nendbr64\npush r14\npush r13\nmov r13, rdx\npush r12\nmovsxd r12, esi\npush rbp\nmov rbp, rdi\npush rbx\nmov rbx, r12\nshl r12, 3\nmov rdi, r12; size\ncall _malloc\nmov r14, rax\ntest ebx, ebx\njle short loc_169E\nmov rbx, rax\nadd r12, rax\nnop dword ptr [rax+00000000h]\nloc_1668:\nmov edi, 64h ; 'd'; size\nadd rbx, 8\nadd rbp, 8\ncall _malloc\nmov r8, [rbp-8]\nmov rcx, r13\nmov edx, 64h ; 'd'\nmov [rbx-8], rax\nmov rdi, rax\nmov esi, 2\nxor eax, eax\ncall ___sprintf_chk\ncmp rbx, r12\njnz short loc_1668\nloc_169E:\npop rbx\nmov rax, r14\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1630(__int64 a1, int a2, __int64 a3)\n{\n char *v5; // rax\n char *v6; // r14\n char *v7; // rbx\n char *v8; // r12\n void *v9; // rax\n __int64 v10; // r8\n\n v5 = (char *)malloc(8LL * a2);\n v6 = v5;\n if ( a2 > 0 )\n {\n v7 = v5;\n v8 = &v5[8 * a2];\n do\n {\n v7 += 8;\n a1 += 8LL;\n v9 = malloc(0x64uLL);\n v10 = *(_QWORD *)(a1 - 8);\n *((_QWORD *)v7 - 1) = v9;\n __sprintf_chk(v9, 2LL, 100LL, a3, v10);\n }\n while ( v7 != v8 );\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1630(long long a1, int a2, long long a3) {\n char *v5;\n char *v6;\n char *v7;\n char *v8;\n void *v9;\n long long v10;\n v5 = (char *)malloc(8LL * a2);\n v6 = v5;\n if (a2 > 0) {\n v7 = v5;\n v8 = &v5[8 * a2];\n do {\n v7 += 8;\n a1 += 8LL;\n v9 = malloc(100uLL);\n v10 = *(uint64_t *)(a1 - 8);\n *((uint64_t *)v7 - 1) = v9;\n __sprintf_chk(v9, 2LL, 100LL, a3, v10);\n } while (v7 != v8);\n }\n return v6;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2, long long a3) {\n char *v5;\n char *v6;\n char *v7;\n char *v8;\n void *v9;\n long long v10;\n v5 = (char *)malloc(8LL * a2);\n v6 = v5;\n if (a2 > 0) {\n v7 = v5;\n v8 = &v5[8 * a2];\n do {\n v7 += 8;\n a1 += 8LL;\n v9 = malloc(100uLL);\n v10 = *(uint64_t *)(a1 - 8);\n *((uint64_t *)v7 - 1) = v9;\n __sprintf_chk(v9, 2LL, 100LL, a3, v10);\n } while (v7 != v8);\n }\n return v6;\n}" + }, + { + "index": 390, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(char* list[], int size, const char* format) {\n char** result = malloc(size * sizeof(char*));\n for (int i = 0; i < size; i++) {\n result[i] = malloc(100);\n sprintf(result[i], format, list[i]);\n }\n return result;\n}", + "test": "int main() {\n\n // First test case\n\n char* list1[] = {\"1\", \"2\", \"3\", \"4\"};\n\n char** res1 = func0(list1, 4, \"temp%s\");\n\n assert(strcmp(res1[0], \"temp1\") == 0);\n\n assert(strcmp(res1[1], \"temp2\") == 0);\n\n assert(strcmp(res1[2], \"temp3\") == 0);\n\n assert(strcmp(res1[3], \"temp4\") == 0);\n\n for(int i = 0; i < 4; i++) free(res1[i]);\n\n free(res1);\n\n\n\n // Second test case\n\n char* list2[] = {\"a\", \"b\", \"c\", \"d\"};\n\n char** res2 = func0(list2, 4, \"python%s\");\n\n assert(strcmp(res2[0], \"pythona\") == 0);\n\n assert(strcmp(res2[1], \"pythonb\") == 0);\n\n assert(strcmp(res2[2], \"pythonc\") == 0);\n\n assert(strcmp(res2[3], \"pythond\") == 0);\n\n for(int i = 0; i < 4; i++) free(res2[i]);\n\n free(res2);\n\n\n\n // Third test case\n\n char* list3[] = {\"5\", \"6\", \"7\", \"8\"};\n\n char** res3 = func0(list3, 4, \"string%s\");\n\n assert(strcmp(res3[0], \"string5\") == 0);\n\n assert(strcmp(res3[1], \"string6\") == 0);\n\n assert(strcmp(res3[2], \"string7\") == 0);\n\n assert(strcmp(res3[3], \"string8\") == 0);\n\n for(int i = 0; i < 4; i++) free(res3[i]);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\nmov %rdx,%r13\npush %r12\npush %rbp\nmov %rdi,%rbp\nmovslq %esi,%rdi\npush %rbx\nmov %rdi,%rbx\nshl $0x3,%rdi\ncallq 10c0 \nmov %rax,%r12\ntest %ebx,%ebx\njle 16c6 \nlea -0x1(%rbx),%r14d\nxor %ebx,%ebx\nxchg %ax,%ax\nmov $0x64,%edi\ncallq 10c0 \nmov 0x0(%rbp,%rbx,8),%r8\nmov %r13,%rcx\nmov $0x64,%edx\nmov %rax,(%r12,%rbx,8)\nmov %rax,%rdi\nmov $0x1,%esi\nxor %eax,%eax\ncallq 10d0 <__sprintf_chk@plt>\nmov %rbx,%rax\nadd $0x1,%rbx\ncmp %r14,%rax\njne 1690 \npop %rbx\nmov %r12,%rax\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\nmov r13, rdx\npush r12\nmovsxd r12, esi\npush rbp\nmov rbp, rdi\npush rbx\nmov rbx, r12\nshl r12, 3\nmov rdi, r12; size\ncall _malloc\nmov r14, rax\ntest ebx, ebx\njle short loc_169E\nmov rbx, rax\nadd r12, rax\nnop dword ptr [rax+00000000h]\nloc_1668:\nmov edi, 64h ; 'd'; size\nadd rbx, 8\nadd rbp, 8\ncall _malloc\nmov r8, [rbp-8]\nmov rcx, r13\nmov edx, 64h ; 'd'\nmov [rbx-8], rax\nmov rdi, rax\nmov esi, 2\nxor eax, eax\ncall ___sprintf_chk\ncmp rbx, r12\njnz short loc_1668\nloc_169E:\npop rbx\nmov rax, r14\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2, __int64 a3)\n{\n char *v5; // rax\n char *v6; // r14\n char *v7; // rbx\n char *v8; // r12\n void *v9; // rax\n __int64 v10; // r8\n\n v5 = (char *)malloc(8LL * a2);\n v6 = v5;\n if ( a2 > 0 )\n {\n v7 = v5;\n v8 = &v5[8 * a2];\n do\n {\n v7 += 8;\n a1 += 8LL;\n v9 = malloc(0x64uLL);\n v10 = *(_QWORD *)(a1 - 8);\n *((_QWORD *)v7 - 1) = v9;\n __sprintf_chk(v9, 2LL, 100LL, a3, v10);\n }\n while ( v7 != v8 );\n }\n return v6;\n}", + "ida_strip_asm": "sub_1630:\nendbr64\npush r14\npush r13\nmov r13, rdx\npush r12\nmovsxd r12, esi\npush rbp\nmov rbp, rdi\npush rbx\nmov rbx, r12\nshl r12, 3\nmov rdi, r12; size\ncall _malloc\nmov r14, rax\ntest ebx, ebx\njle short loc_169E\nmov rbx, rax\nadd r12, rax\nnop dword ptr [rax+00000000h]\nloc_1668:\nmov edi, 64h ; 'd'; size\nadd rbx, 8\nadd rbp, 8\ncall _malloc\nmov r8, [rbp-8]\nmov rcx, r13\nmov edx, 64h ; 'd'\nmov [rbx-8], rax\nmov rdi, rax\nmov esi, 2\nxor eax, eax\ncall ___sprintf_chk\ncmp rbx, r12\njnz short loc_1668\nloc_169E:\npop rbx\nmov rax, r14\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1630(__int64 a1, int a2, __int64 a3)\n{\n char *v5; // rax\n char *v6; // r14\n char *v7; // rbx\n char *v8; // r12\n void *v9; // rax\n __int64 v10; // r8\n\n v5 = (char *)malloc(8LL * a2);\n v6 = v5;\n if ( a2 > 0 )\n {\n v7 = v5;\n v8 = &v5[8 * a2];\n do\n {\n v7 += 8;\n a1 += 8LL;\n v9 = malloc(0x64uLL);\n v10 = *(_QWORD *)(a1 - 8);\n *((_QWORD *)v7 - 1) = v9;\n __sprintf_chk(v9, 2LL, 100LL, a3, v10);\n }\n while ( v7 != v8 );\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1630(long long a1, int a2, long long a3) {\n char *v5;\n char *v6;\n char *v7;\n char *v8;\n void *v9;\n long long v10;\n v5 = (char *)malloc(8LL * a2);\n v6 = v5;\n if (a2 > 0) {\n v7 = v5;\n v8 = &v5[8 * a2];\n do {\n v7 += 8;\n a1 += 8LL;\n v9 = malloc(100uLL);\n v10 = *(uint64_t *)(a1 - 8);\n *((uint64_t *)v7 - 1) = v9;\n __sprintf_chk(v9, 2LL, 100LL, a3, v10);\n } while (v7 != v8);\n }\n return v6;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2, long long a3) {\n char *v5;\n char *v6;\n char *v7;\n char *v8;\n void *v9;\n long long v10;\n v5 = (char *)malloc(8LL * a2);\n v6 = v5;\n if (a2 > 0) {\n v7 = v5;\n v8 = &v5[8 * a2];\n do {\n v7 += 8;\n a1 += 8LL;\n v9 = malloc(100uLL);\n v10 = *(uint64_t *)(a1 - 8);\n *((uint64_t *)v7 - 1) = v9;\n __sprintf_chk(v9, 2LL, 100LL, a3, v10);\n } while (v7 != v8);\n }\n return v6;\n}" + }, + { + "index": 391, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char *key;\n\n int value;\n\n} dictionary;\n\n\n\ntypedef struct {\n\n char *key;\n\n dictionary dict;\n\n} dict_of_dict;\n\n\n\n", + "func": "dict_of_dict *func0(char *l1[], char *l2[], int l3[], int size) {\n dict_of_dict *result = (dict_of_dict *)malloc(sizeof(dict_of_dict) * size);\n for (int i = 0; i < size; i++) {\n result[i].key = l1[i];\n result[i].dict.key = l2[i];\n result[i].dict.value = l3[i];\n }\n return result;\n}", + "test": "int main() {\n\n char *keys1[] = {\"S001\", \"S002\", \"S003\", \"S004\"};\n\n char *values1[] = {\"Adina Park\", \"Leyton Marsh\", \"Duncan Boyle\", \"Saim Richards\"};\n\n int numbers1[] = {85, 98, 89, 92};\n\n dict_of_dict *result1 = func0(keys1, values1, numbers1, 4);\n\n \n\n char *keys2[] = {\"abc\", \"def\", \"ghi\", \"jkl\"};\n\n char *values2[] = {\"python\", \"program\", \"language\", \"programs\"};\n\n int numbers2[] = {100, 200, 300, 400};\n\n dict_of_dict *result2 = func0(keys2, values2, numbers2, 4);\n\n \n\n char *keys3[] = {\"A1\", \"A2\", \"A3\", \"A4\"};\n\n char *values3[] = {\"java\", \"C\", \"C++\", \"DBMS\"};\n\n int numbers3[] = {10, 20, 30, 40};\n\n dict_of_dict *result3 = func0(keys3, values3, numbers3, 4);\n\n\n\n // Using string comparisons for dictionary checks\n\n assert(strcmp(result1[0].key, \"S001\") == 0 && strcmp(result1[0].dict.key, \"Adina Park\") == 0 && result1[0].dict.value == 85);\n\n assert(strcmp(result1[1].key, \"S002\") == 0 && strcmp(result1[1].dict.key, \"Leyton Marsh\") == 0 && result1[1].dict.value == 98);\n\n assert(strcmp(result1[2].key, \"S003\") == 0 && strcmp(result1[2].dict.key, \"Duncan Boyle\") == 0 && result1[2].dict.value == 89);\n\n assert(strcmp(result1[3].key, \"S004\") == 0 && strcmp(result1[3].dict.key, \"Saim Richards\") == 0 && result1[3].dict.value == 92);\n\n\n\n assert(strcmp(result2[0].key, \"abc\") == 0 && strcmp(result2[0].dict.key, \"python\") == 0 && result2[0].dict.value == 100);\n\n assert(strcmp(result2[1].key, \"def\") == 0 && strcmp(result2[1].dict.key, \"program\") == 0 && result2[1].dict.value == 200);\n\n assert(strcmp(result2[2].key, \"ghi\") == 0 && strcmp(result2[2].dict.key, \"language\") == 0 && result2[2].dict.value == 300);\n\n assert(strcmp(result2[3].key, \"jkl\") == 0 && strcmp(result2[3].dict.key, \"programs\") == 0 && result2[3].dict.value == 400);\n\n\n\n assert(strcmp(result3[0].key, \"A1\") == 0 && strcmp(result3[0].dict.key, \"java\") == 0 && result3[0].dict.value == 10);\n\n assert(strcmp(result3[1].key, \"A2\") == 0 && strcmp(result3[1].dict.key, \"C\") == 0 && result3[1].dict.value == 20);\n\n assert(strcmp(result3[2].key, \"A3\") == 0 && strcmp(result3[2].dict.key, \"C++\") == 0 && result3[2].dict.value == 30);\n\n assert(strcmp(result3[3].key, \"A4\") == 0 && strcmp(result3[3].dict.key, \"DBMS\") == 0 && result3[3].dict.value == 40);\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %ecx,-0x2c(%rbp)\nmov -0x2c(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0xc(%rbp)\njmpq 12bb \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%rax\nmov %rax,(%rdx)\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x20(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%rax\nmov %rax,0x8(%rdx)\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,0x10(%rdx)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 120f \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_28], rdx\nmov [rbp+var_2C], ecx\nmov eax, [rbp+var_2C]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp loc_12BB\nloc_120F:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov rax, [rcx]\nmov [rdx], rax\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_20]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov rax, [rcx]\nmov [rdx+8], rax\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx+10h], eax\nadd [rbp+var_C], 1\nloc_12BB:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_2C]\njl loc_120F\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n int i; // [rsp+24h] [rbp-Ch]\n _QWORD *v8; // [rsp+28h] [rbp-8h]\n\n v8 = malloc(24LL * a4);\n for ( i = 0; i < a4; ++i )\n {\n v8[3 * i] = *(_QWORD *)(8LL * i + a1);\n v8[3 * i + 1] = *(_QWORD *)(8LL * i + a2);\n LODWORD(v8[3 * i + 2]) = *(_DWORD *)(4LL * i + a3);\n }\n return v8;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_28], rdx\nmov [rbp+var_2C], ecx\nmov eax, [rbp+var_2C]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp loc_12BB\nloc_120F:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov rax, [rcx]\nmov [rdx], rax\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_20]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov rax, [rcx]\nmov [rdx+8], rax\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx+10h], eax\nadd [rbp+var_C], 1\nloc_12BB:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_2C]\njl loc_120F\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11C9(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n int i; // [rsp+24h] [rbp-Ch]\n _QWORD *v8; // [rsp+28h] [rbp-8h]\n\n v8 = malloc(24LL * a4);\n for ( i = 0; i < a4; ++i )\n {\n v8[3 * i] = *(_QWORD *)(8LL * i + a1);\n v8[3 * i + 1] = *(_QWORD *)(8LL * i + a2);\n LODWORD(v8[3 * i + 2]) = *(_DWORD *)(4LL * i + a3);\n }\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11C9(long long a1, long long a2, long long a3, int a4) {\n int i;\n uint64_t *v8;\n v8 = malloc(24LL * a4);\n for (i = 0; i < a4; ++i) {\n v8[3 * i] = *(uint64_t *)(8LL * i + a1);\n v8[3 * i + 1] = *(uint64_t *)(8LL * i + a2);\n LODWORD(v8[3 * i + 2]) = *(uint32_t *)(4LL * i + a3);\n }\n return v8;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, long long a2, long long a3, int a4) {\n int i;\n uint64_t *v8;\n v8 = malloc(24LL * a4);\n for (i = 0; i < a4; ++i) {\n v8[3 * i] = *(uint64_t *)(8LL * i + a1);\n v8[3 * i + 1] = *(uint64_t *)(8LL * i + a2);\n LODWORD(v8[3 * i + 2]) = *(uint32_t *)(4LL * i + a3);\n }\n return v8;\n}" + }, + { + "index": 391, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char *key;\n\n int value;\n\n} dictionary;\n\n\n\ntypedef struct {\n\n char *key;\n\n dictionary dict;\n\n} dict_of_dict;\n\n\n\n", + "func": "dict_of_dict *func0(char *l1[], char *l2[], int l3[], int size) {\n dict_of_dict *result = (dict_of_dict *)malloc(sizeof(dict_of_dict) * size);\n for (int i = 0; i < size; i++) {\n result[i].key = l1[i];\n result[i].dict.key = l2[i];\n result[i].dict.value = l3[i];\n }\n return result;\n}", + "test": "int main() {\n\n char *keys1[] = {\"S001\", \"S002\", \"S003\", \"S004\"};\n\n char *values1[] = {\"Adina Park\", \"Leyton Marsh\", \"Duncan Boyle\", \"Saim Richards\"};\n\n int numbers1[] = {85, 98, 89, 92};\n\n dict_of_dict *result1 = func0(keys1, values1, numbers1, 4);\n\n \n\n char *keys2[] = {\"abc\", \"def\", \"ghi\", \"jkl\"};\n\n char *values2[] = {\"python\", \"program\", \"language\", \"programs\"};\n\n int numbers2[] = {100, 200, 300, 400};\n\n dict_of_dict *result2 = func0(keys2, values2, numbers2, 4);\n\n \n\n char *keys3[] = {\"A1\", \"A2\", \"A3\", \"A4\"};\n\n char *values3[] = {\"java\", \"C\", \"C++\", \"DBMS\"};\n\n int numbers3[] = {10, 20, 30, 40};\n\n dict_of_dict *result3 = func0(keys3, values3, numbers3, 4);\n\n\n\n // Using string comparisons for dictionary checks\n\n assert(strcmp(result1[0].key, \"S001\") == 0 && strcmp(result1[0].dict.key, \"Adina Park\") == 0 && result1[0].dict.value == 85);\n\n assert(strcmp(result1[1].key, \"S002\") == 0 && strcmp(result1[1].dict.key, \"Leyton Marsh\") == 0 && result1[1].dict.value == 98);\n\n assert(strcmp(result1[2].key, \"S003\") == 0 && strcmp(result1[2].dict.key, \"Duncan Boyle\") == 0 && result1[2].dict.value == 89);\n\n assert(strcmp(result1[3].key, \"S004\") == 0 && strcmp(result1[3].dict.key, \"Saim Richards\") == 0 && result1[3].dict.value == 92);\n\n\n\n assert(strcmp(result2[0].key, \"abc\") == 0 && strcmp(result2[0].dict.key, \"python\") == 0 && result2[0].dict.value == 100);\n\n assert(strcmp(result2[1].key, \"def\") == 0 && strcmp(result2[1].dict.key, \"program\") == 0 && result2[1].dict.value == 200);\n\n assert(strcmp(result2[2].key, \"ghi\") == 0 && strcmp(result2[2].dict.key, \"language\") == 0 && result2[2].dict.value == 300);\n\n assert(strcmp(result2[3].key, \"jkl\") == 0 && strcmp(result2[3].dict.key, \"programs\") == 0 && result2[3].dict.value == 400);\n\n\n\n assert(strcmp(result3[0].key, \"A1\") == 0 && strcmp(result3[0].dict.key, \"java\") == 0 && result3[0].dict.value == 10);\n\n assert(strcmp(result3[1].key, \"A2\") == 0 && strcmp(result3[1].dict.key, \"C\") == 0 && result3[1].dict.value == 20);\n\n assert(strcmp(result3[2].key, \"A3\") == 0 && strcmp(result3[2].dict.key, \"C++\") == 0 && result3[2].dict.value == 30);\n\n assert(strcmp(result3[3].key, \"A4\") == 0 && strcmp(result3[3].dict.key, \"DBMS\") == 0 && result3[3].dict.value == 40);\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbx\nmov %rsi,%rbp\nmov %rdx,%r12\nmov %ecx,%r13d\nmovslq %ecx,%rax\nlea (%rax,%rax,2),%rdi\nshl $0x3,%rdi\ncallq 10b0 \ntest %r13d,%r13d\njle 120b \nmov %rax,%rcx\nlea -0x1(%r13),%edi\nmov $0x0,%edx\nmov (%rbx,%rdx,8),%rsi\nmov %rsi,(%rcx)\nmov 0x0(%rbp,%rdx,8),%rsi\nmov %rsi,0x8(%rcx)\nmov (%r12,%rdx,4),%esi\nmov %esi,0x10(%rcx)\nmov %rdx,%rsi\nadd $0x1,%rdx\nadd $0x18,%rcx\ncmp %rdi,%rsi\njne 11e4 \nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbp, rdi\nmov r12, rsi\nmov r13, rdx\nmov r14d, ecx\nmovsxd rbx, ecx\nlea rdi, [rbx+rbx*2]\nshl rdi, 3; size\ncall _malloc\ntest r14d, r14d\njle short loc_1223\nmov rcx, rax\nmov edx, 0\nloc_11FE:\nmov rsi, [rbp+rdx*8+0]\nmov [rcx], rsi\nmov rsi, [r12+rdx*8]\nmov [rcx+8], rsi\nmov esi, [r13+rdx*4+0]\nmov [rcx+10h], esi\nadd rdx, 1\nadd rcx, 18h\ncmp rbx, rdx\njnz short loc_11FE\nloc_1223:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 v6; // rbx\n _QWORD *result; // rax\n _QWORD *v8; // rcx\n __int64 v9; // rdx\n\n v6 = a4;\n result = malloc(24LL * a4);\n if ( a4 > 0 )\n {\n v8 = result;\n v9 = 0LL;\n do\n {\n *v8 = *(_QWORD *)(a1 + 8 * v9);\n v8[1] = *(_QWORD *)(a2 + 8 * v9);\n *((_DWORD *)v8 + 4) = *(_DWORD *)(a3 + 4 * v9++);\n v8 += 3;\n }\n while ( v6 != v9 );\n }\n return result;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbp, rdi\nmov r12, rsi\nmov r13, rdx\nmov r14d, ecx\nmovsxd rbx, ecx\nlea rdi, [rbx+rbx*2]\nshl rdi, 3; size\ncall _malloc\ntest r14d, r14d\njle short loc_1223\nmov rcx, rax\nmov edx, 0\nloc_11FE:\nmov rsi, [rbp+rdx*8+0]\nmov [rcx], rsi\nmov rsi, [r12+rdx*8]\nmov [rcx+8], rsi\nmov esi, [r13+rdx*4+0]\nmov [rcx+10h], esi\nadd rdx, 1\nadd rcx, 18h\ncmp rbx, rdx\njnz short loc_11FE\nloc_1223:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11C9(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 v6; // rbx\n _QWORD *result; // rax\n _QWORD *v8; // rcx\n __int64 v9; // rdx\n\n v6 = a4;\n result = malloc(24LL * a4);\n if ( a4 > 0 )\n {\n v8 = result;\n v9 = 0LL;\n do\n {\n *v8 = *(_QWORD *)(a1 + 8 * v9);\n v8[1] = *(_QWORD *)(a2 + 8 * v9);\n *((_DWORD *)v8 + 4) = *(_DWORD *)(a3 + 4 * v9++);\n v8 += 3;\n }\n while ( v6 != v9 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11C9(long long a1, long long a2, long long a3, int a4) {\n long long v6;\n uint64_t *result;\n uint64_t *v8;\n long long v9;\n v6 = a4;\n result = malloc(24LL * a4);\n if (a4 > 0) {\n v8 = result;\n v9 = 0LL;\n do {\n *v8 = *(uint64_t *)(a1 + 8 * v9);\n v8[1] = *(uint64_t *)(a2 + 8 * v9);\n *((uint32_t *)v8 + 4) = *(uint32_t *)(a3 + 4 * v9++);\n v8 += 3;\n } while (v6 != v9);\n }\n return result;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, long long a2, long long a3, int a4) {\n long long v6;\n uint64_t *result;\n uint64_t *v8;\n long long v9;\n v6 = a4;\n result = malloc(24LL * a4);\n if (a4 > 0) {\n v8 = result;\n v9 = 0LL;\n do {\n *v8 = *(uint64_t *)(a1 + 8 * v9);\n v8[1] = *(uint64_t *)(a2 + 8 * v9);\n *((uint32_t *)v8 + 4) = *(uint32_t *)(a3 + 4 * v9++);\n v8 += 3;\n } while (v6 != v9);\n }\n return result;\n}" + }, + { + "index": 391, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char *key;\n\n int value;\n\n} dictionary;\n\n\n\ntypedef struct {\n\n char *key;\n\n dictionary dict;\n\n} dict_of_dict;\n\n\n\n", + "func": "dict_of_dict *func0(char *l1[], char *l2[], int l3[], int size) {\n dict_of_dict *result = (dict_of_dict *)malloc(sizeof(dict_of_dict) * size);\n for (int i = 0; i < size; i++) {\n result[i].key = l1[i];\n result[i].dict.key = l2[i];\n result[i].dict.value = l3[i];\n }\n return result;\n}", + "test": "int main() {\n\n char *keys1[] = {\"S001\", \"S002\", \"S003\", \"S004\"};\n\n char *values1[] = {\"Adina Park\", \"Leyton Marsh\", \"Duncan Boyle\", \"Saim Richards\"};\n\n int numbers1[] = {85, 98, 89, 92};\n\n dict_of_dict *result1 = func0(keys1, values1, numbers1, 4);\n\n \n\n char *keys2[] = {\"abc\", \"def\", \"ghi\", \"jkl\"};\n\n char *values2[] = {\"python\", \"program\", \"language\", \"programs\"};\n\n int numbers2[] = {100, 200, 300, 400};\n\n dict_of_dict *result2 = func0(keys2, values2, numbers2, 4);\n\n \n\n char *keys3[] = {\"A1\", \"A2\", \"A3\", \"A4\"};\n\n char *values3[] = {\"java\", \"C\", \"C++\", \"DBMS\"};\n\n int numbers3[] = {10, 20, 30, 40};\n\n dict_of_dict *result3 = func0(keys3, values3, numbers3, 4);\n\n\n\n // Using string comparisons for dictionary checks\n\n assert(strcmp(result1[0].key, \"S001\") == 0 && strcmp(result1[0].dict.key, \"Adina Park\") == 0 && result1[0].dict.value == 85);\n\n assert(strcmp(result1[1].key, \"S002\") == 0 && strcmp(result1[1].dict.key, \"Leyton Marsh\") == 0 && result1[1].dict.value == 98);\n\n assert(strcmp(result1[2].key, \"S003\") == 0 && strcmp(result1[2].dict.key, \"Duncan Boyle\") == 0 && result1[2].dict.value == 89);\n\n assert(strcmp(result1[3].key, \"S004\") == 0 && strcmp(result1[3].dict.key, \"Saim Richards\") == 0 && result1[3].dict.value == 92);\n\n\n\n assert(strcmp(result2[0].key, \"abc\") == 0 && strcmp(result2[0].dict.key, \"python\") == 0 && result2[0].dict.value == 100);\n\n assert(strcmp(result2[1].key, \"def\") == 0 && strcmp(result2[1].dict.key, \"program\") == 0 && result2[1].dict.value == 200);\n\n assert(strcmp(result2[2].key, \"ghi\") == 0 && strcmp(result2[2].dict.key, \"language\") == 0 && result2[2].dict.value == 300);\n\n assert(strcmp(result2[3].key, \"jkl\") == 0 && strcmp(result2[3].dict.key, \"programs\") == 0 && result2[3].dict.value == 400);\n\n\n\n assert(strcmp(result3[0].key, \"A1\") == 0 && strcmp(result3[0].dict.key, \"java\") == 0 && result3[0].dict.value == 10);\n\n assert(strcmp(result3[1].key, \"A2\") == 0 && strcmp(result3[1].dict.key, \"C\") == 0 && result3[1].dict.value == 20);\n\n assert(strcmp(result3[2].key, \"A3\") == 0 && strcmp(result3[2].dict.key, \"C++\") == 0 && result3[2].dict.value == 30);\n\n assert(strcmp(result3[3].key, \"A4\") == 0 && strcmp(result3[3].dict.key, \"DBMS\") == 0 && result3[3].dict.value == 40);\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmovslq %ecx,%rax\npush %r12\nmov %rax,%r13\nmov %rdx,%r12\npush %rbp\nmov %rsi,%rbp\npush %rbx\nmov %rdi,%rbx\nlea (%rax,%rax,2),%rdi\nshl $0x3,%rdi\nsub $0x8,%rsp\ncallq 10b0 \ntest %r13d,%r13d\njle 1949 \nmov %rax,%rdi\nlea -0x1(%r13),%edx\nxor %ecx,%ecx\nnopl 0x0(%rax,%rax,1)\nmov (%rbx,%rcx,8),%r8\nadd $0x18,%rdi\nmov %r8,-0x18(%rdi)\nmov 0x0(%rbp,%rcx,8),%r8\nmov %r8,-0x10(%rdi)\nmov (%r12,%rcx,4),%r8d\nmov %r8d,-0x8(%rdi)\nmov %rcx,%r8\nadd $0x1,%rcx\ncmp %rdx,%r8\njne 1920 \nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\nmov r13, rdx\npush r12\nmov r12, rsi\npush rbp\nmov rbp, rdi\npush rbx\nmovsxd rbx, ecx\nlea rdi, [rbx+rbx*2]\nshl rdi, 3; size\ncall _malloc\ntest ebx, ebx\njle short loc_18B4\nmov rcx, rax\nxor edx, edx\nxchg ax, ax\nloc_1890:\nmovq xmm0, qword ptr [rbp+rdx*8+0]\nmov esi, [r13+rdx*4+0]\nadd rcx, 18h\nmovhps xmm0, qword ptr [r12+rdx*8]\nadd rdx, 1\nmov [rcx-8], esi\nmovups xmmword ptr [rcx-18h], xmm0\ncmp rbx, rdx\njnz short loc_1890\nloc_18B4:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 v6; // rbx\n _DWORD *result; // rax\n _DWORD *v8; // rcx\n __int64 i; // rdx\n int v10; // esi\n __m128 v11; // xmm0\n\n v6 = a4;\n result = malloc(24LL * a4);\n if ( (int)v6 > 0 )\n {\n v8 = result;\n for ( i = 0LL; i != v6; ++i )\n {\n v10 = *(_DWORD *)(a3 + 4 * i);\n v8 += 6;\n v11 = _mm_loadh_ps((const double *)(a2 + 8 * i));\n *(v8 - 2) = v10;\n *(__m128 *)(v8 - 6) = v11;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1860:\nendbr64\npush r14\npush r13\nmov r13, rdx\npush r12\nmov r12, rsi\npush rbp\nmov rbp, rdi\npush rbx\nmovsxd rbx, ecx\nlea rdi, [rbx+rbx*2]\nshl rdi, 3; size\ncall _malloc\ntest ebx, ebx\njle short loc_18B4\nmov rcx, rax\nxor edx, edx\nxchg ax, ax\nloc_1890:\nmovq xmm0, qword ptr [rbp+rdx*8+0]\nmov esi, [r13+rdx*4+0]\nadd rcx, 18h\nmovhps xmm0, qword ptr [r12+rdx*8]\nadd rdx, 1\nmov [rcx-8], esi\nmovups xmmword ptr [rcx-18h], xmm0\ncmp rbx, rdx\njnz short loc_1890\nloc_18B4:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1860(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 v6; // rbx\n _DWORD *result; // rax\n _DWORD *v8; // rcx\n __int64 i; // rdx\n int v10; // esi\n __m128 v11; // xmm0\n\n v6 = a4;\n result = malloc(24LL * a4);\n if ( (int)v6 > 0 )\n {\n v8 = result;\n for ( i = 0LL; i != v6; ++i )\n {\n v10 = *(_DWORD *)(a3 + 4 * i);\n v8 += 6;\n v11 = _mm_loadh_ps((const double *)(a2 + 8 * i));\n *(v8 - 2) = v10;\n *(__m128 *)(v8 - 6) = v11;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1860(long long a1, long long a2, long long a3, int a4) {\n long long v6;\n uint32_t *result;\n uint32_t *v8;\n long long i;\n int v10;\n __m128 v11;\n v6 = a4;\n result = malloc(24LL * a4);\n if ((int)v6 > 0) {\n v8 = result;\n for (i = 0LL; i != v6; ++i) {\n v10 = *(uint32_t *)(a3 + 4 * i);\n v8 += 6;\n v11 = _mm_loadh_ps((const double *)(a2 + 8 * i));\n *(v8 - 2) = v10;\n *(__m128 *)(v8 - 6) = v11;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, long long a2, long long a3, int a4) {\n long long v6;\n uint32_t *result;\n uint32_t *v8;\n long long i;\n int v10;\n __m128 v11;\n v6 = a4;\n result = malloc(24LL * a4);\n if ((int)v6 > 0) {\n v8 = result;\n for (i = 0LL; i != v6; ++i) {\n v10 = *(uint32_t *)(a3 + 4 * i);\n v8 += 6;\n v11 = _mm_loadh_ps((const double *)(a2 + 8 * i));\n *(v8 - 2) = v10;\n *(__m128 *)(v8 - 6) = v11;\n }\n }\n return result;\n}" + }, + { + "index": 391, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char *key;\n\n int value;\n\n} dictionary;\n\n\n\ntypedef struct {\n\n char *key;\n\n dictionary dict;\n\n} dict_of_dict;\n\n\n\n", + "func": "dict_of_dict *func0(char *l1[], char *l2[], int l3[], int size) {\n dict_of_dict *result = (dict_of_dict *)malloc(sizeof(dict_of_dict) * size);\n for (int i = 0; i < size; i++) {\n result[i].key = l1[i];\n result[i].dict.key = l2[i];\n result[i].dict.value = l3[i];\n }\n return result;\n}", + "test": "int main() {\n\n char *keys1[] = {\"S001\", \"S002\", \"S003\", \"S004\"};\n\n char *values1[] = {\"Adina Park\", \"Leyton Marsh\", \"Duncan Boyle\", \"Saim Richards\"};\n\n int numbers1[] = {85, 98, 89, 92};\n\n dict_of_dict *result1 = func0(keys1, values1, numbers1, 4);\n\n \n\n char *keys2[] = {\"abc\", \"def\", \"ghi\", \"jkl\"};\n\n char *values2[] = {\"python\", \"program\", \"language\", \"programs\"};\n\n int numbers2[] = {100, 200, 300, 400};\n\n dict_of_dict *result2 = func0(keys2, values2, numbers2, 4);\n\n \n\n char *keys3[] = {\"A1\", \"A2\", \"A3\", \"A4\"};\n\n char *values3[] = {\"java\", \"C\", \"C++\", \"DBMS\"};\n\n int numbers3[] = {10, 20, 30, 40};\n\n dict_of_dict *result3 = func0(keys3, values3, numbers3, 4);\n\n\n\n // Using string comparisons for dictionary checks\n\n assert(strcmp(result1[0].key, \"S001\") == 0 && strcmp(result1[0].dict.key, \"Adina Park\") == 0 && result1[0].dict.value == 85);\n\n assert(strcmp(result1[1].key, \"S002\") == 0 && strcmp(result1[1].dict.key, \"Leyton Marsh\") == 0 && result1[1].dict.value == 98);\n\n assert(strcmp(result1[2].key, \"S003\") == 0 && strcmp(result1[2].dict.key, \"Duncan Boyle\") == 0 && result1[2].dict.value == 89);\n\n assert(strcmp(result1[3].key, \"S004\") == 0 && strcmp(result1[3].dict.key, \"Saim Richards\") == 0 && result1[3].dict.value == 92);\n\n\n\n assert(strcmp(result2[0].key, \"abc\") == 0 && strcmp(result2[0].dict.key, \"python\") == 0 && result2[0].dict.value == 100);\n\n assert(strcmp(result2[1].key, \"def\") == 0 && strcmp(result2[1].dict.key, \"program\") == 0 && result2[1].dict.value == 200);\n\n assert(strcmp(result2[2].key, \"ghi\") == 0 && strcmp(result2[2].dict.key, \"language\") == 0 && result2[2].dict.value == 300);\n\n assert(strcmp(result2[3].key, \"jkl\") == 0 && strcmp(result2[3].dict.key, \"programs\") == 0 && result2[3].dict.value == 400);\n\n\n\n assert(strcmp(result3[0].key, \"A1\") == 0 && strcmp(result3[0].dict.key, \"java\") == 0 && result3[0].dict.value == 10);\n\n assert(strcmp(result3[1].key, \"A2\") == 0 && strcmp(result3[1].dict.key, \"C\") == 0 && result3[1].dict.value == 20);\n\n assert(strcmp(result3[2].key, \"A3\") == 0 && strcmp(result3[2].dict.key, \"C++\") == 0 && result3[2].dict.value == 30);\n\n assert(strcmp(result3[3].key, \"A4\") == 0 && strcmp(result3[3].dict.key, \"DBMS\") == 0 && result3[3].dict.value == 40);\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmovslq %ecx,%rax\nmov %rdx,%r13\npush %r12\nmov %rax,%r12\npush %rbp\nmov %rdi,%rbp\nlea (%rax,%rax,2),%rdi\npush %rbx\nshl $0x3,%rdi\nmov %rsi,%rbx\nsub $0x8,%rsp\ncallq 10b0 \ntest %r12d,%r12d\njle 1a1e \nlea -0x1(%r12),%edx\ncmp $0x2,%edx\njbe 1a29 \nmov %r12d,%ecx\nmov %rax,%rdi\nmov %r13,%r9\nxor %r8d,%r8d\nshr $0x2,%ecx\nshl $0x5,%rcx\nnopl 0x0(%rax)\nmovdqu 0x10(%rbx,%r8,1),%xmm0\nadd $0x60,%rdi\nadd $0x10,%r9\nmovdqu (%rbx,%r8,1),%xmm1\nmovdqu 0x0(%rbp,%r8,1),%xmm3\nmovdqu 0x10(%rbp,%r8,1),%xmm2\nadd $0x20,%r8\nmovq %xmm0,-0x28(%rdi)\nmovhps %xmm0,-0x10(%rdi)\nmovdqu -0x10(%r9),%xmm0\nmovq %xmm1,-0x58(%rdi)\nmovhps %xmm1,-0x40(%rdi)\npshufd $0x55,%xmm0,%xmm1\nmovd %xmm1,-0x38(%rdi)\nmovdqa %xmm0,%xmm1\npunpckhdq %xmm0,%xmm1\nmovd %xmm0,-0x50(%rdi)\npshufd $0xff,%xmm0,%xmm0\nmovq %xmm3,-0x60(%rdi)\nmovhps %xmm3,-0x48(%rdi)\nmovq %xmm2,-0x30(%rdi)\nmovhps %xmm2,-0x18(%rdi)\nmovd %xmm1,-0x20(%rdi)\nmovd %xmm0,-0x8(%rdi)\ncmp %r8,%rcx\njne 1928 \nmov %r12d,%ecx\nand $0xfffffffc,%ecx\ntest $0x3,%r12b\nje 1a1e \nmovslq %ecx,%rdx\nmovq 0x0(%rbp,%rdx,8),%xmm0\nlea (%rdx,%rdx,2),%rsi\nshl $0x3,%rsi\nmovhps (%rbx,%rdx,8),%xmm0\nmov 0x0(%r13,%rdx,4),%edx\nlea (%rax,%rsi,1),%rdi\nmovups %xmm0,(%rdi)\nmov %edx,0x10(%rdi)\nlea 0x1(%rcx),%edx\ncmp %edx,%r12d\njle 1a1e \nmovslq %edx,%rdx\nlea 0x18(%rax,%rsi,1),%rdi\nadd $0x2,%ecx\nmovq 0x0(%rbp,%rdx,8),%xmm0\nmovhps (%rbx,%rdx,8),%xmm0\nmov 0x0(%r13,%rdx,4),%edx\nmovups %xmm0,(%rdi)\nmov %edx,0x10(%rdi)\ncmp %ecx,%r12d\njle 1a1e \nmovslq %ecx,%rcx\nlea 0x30(%rax,%rsi,1),%rdx\nmovq 0x0(%rbp,%rcx,8),%xmm0\nmovhps (%rbx,%rcx,8),%xmm0\nmov 0x0(%r13,%rcx,4),%ecx\nmovups %xmm0,(%rdx)\nmov %ecx,0x10(%rdx)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nxor %ecx,%ecx\njmp 19b0 \nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r13\nmovsxd rax, ecx\npush r12\nmov r13, rax\nmov r12, rdx\npush rbp\nmov rbp, rdi\nlea rdi, [rax+rax*2]\npush rbx\nshl rdi, 3; size\nmov rbx, rsi\nsub rsp, 8\ncall _malloc\nmov r8, rax\ntest r13d, r13d\njle loc_19A6\nlea eax, [r13-1]\ncmp eax, 2\njbe loc_19B4\nmov edi, r13d\nmov rax, r8\nmov rcx, r12\nxor edx, edx\nshr edi, 2\nshl rdi, 5\nnop dword ptr [rax]\nloc_18B8:\nlea rsi, [rbp+rdx+0]\nmov r9d, [rcx+8]\nmov r11d, [rcx]\nadd rax, 60h ; '`'\nmovq xmm3, qword ptr [rsi]\nmovq xmm2, qword ptr [rsi+8]\nadd rcx, 10h\nmovq xmm0, qword ptr [rsi+18h]\nmovq xmm1, qword ptr [rsi+10h]\nmovhps xmm3, qword ptr [rbx+rdx]\nmov esi, [rcx-4]\nmov r10d, [rcx-0Ch]\nmovups xmmword ptr [rax-60h], xmm3\nmovhps xmm2, qword ptr [rbx+rdx+8]\nmovups xmmword ptr [rax-48h], xmm2\nmovhps xmm1, qword ptr [rbx+rdx+10h]\nmovups xmmword ptr [rax-30h], xmm1\nmovhps xmm0, qword ptr [rbx+rdx+18h]\nadd rdx, 20h ; ' '\nmov [rax-50h], r11d\nmovups xmmword ptr [rax-18h], xmm0\nmov [rax-38h], r10d\nmov [rax-20h], r9d\nmov [rax-8], esi\ncmp rdi, rdx\njnz short loc_18B8\nmov edx, r13d\nand edx, 0FFFFFFFCh\ntest r13b, 3\njz short loc_19A6\nloc_192D:\nmovsxd rax, edx\nmovq xmm0, qword ptr [rbp+rax*8+0]\nlea rcx, [rax+rax*2]\nlea rsi, ds:0[rax*8]\nshl rcx, 3\nlea r9, ds:0[rax*4]\nmovhps xmm0, qword ptr [rbx+rax*8]\nmov eax, [r12+rax*4]\nlea rdi, [r8+rcx]\nmovups xmmword ptr [rdi], xmm0\nmov [rdi+10h], eax\nlea eax, [rdx+1]\ncmp r13d, eax\njle short loc_19A6\nmovq xmm0, qword ptr [rbp+rsi+8]\nmov edi, [r12+r9+4]\nlea rax, [r8+rcx+18h]\nadd edx, 2\nmovhps xmm0, qword ptr [rbx+rsi+8]\nmov [rax+10h], edi\nmovups xmmword ptr [rax], xmm0\ncmp r13d, edx\njle short loc_19A6\nmov edx, [r12+r9+8]\nlea rax, [r8+rcx+30h]\nmovq xmm0, qword ptr [rbp+rsi+10h]\nmov [rax+10h], edx\nmovhps xmm0, qword ptr [rbx+rsi+10h]\nmovups xmmword ptr [rax], xmm0\nloc_19A6:\nadd rsp, 8\nmov rax, r8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_19B4:\nxor edx, edx\njmp loc_192D", + "ida_pseudo": "__m128 *__fastcall func0(__int64 a1, __int64 a2, __int32 *a3, int a4)\n{\n __m128 *v7; // r8\n __m128 *v8; // rax\n __int32 *v9; // rcx\n __int64 v10; // rdx\n __int32 v11; // r9d\n __int32 v12; // r11d\n __int32 v13; // esi\n __int32 v14; // r10d\n __m128 v15; // xmm0\n int v16; // edx\n __int64 v17; // rsi\n __int64 v18; // rcx\n __int64 v19; // r9\n __int32 v20; // eax\n __m128 *v21; // rdi\n __int64 v22; // rax\n __m128 v23; // xmm0\n __m128 *v24; // rax\n\n v7 = (__m128 *)malloc(24LL * a4);\n if ( a4 > 0 )\n {\n if ( (unsigned int)(a4 - 1) <= 2 )\n {\n v16 = 0;\n }\n else\n {\n v8 = v7;\n v9 = a3;\n v10 = 0LL;\n do\n {\n v11 = v9[2];\n v12 = *v9;\n v8 += 6;\n v9 += 4;\n v13 = *(v9 - 1);\n v14 = *(v9 - 3);\n v8[-6] = _mm_loadh_ps((const double *)(a2 + v10));\n *(__m128 *)((char *)v8 - 72) = _mm_loadh_ps((const double *)(a2 + v10 + 8));\n v8[-3] = _mm_loadh_ps((const double *)(a2 + v10 + 16));\n v15 = _mm_loadh_ps((const double *)(a2 + v10 + 24));\n v10 += 32LL;\n v8[-5].m128_i32[0] = v12;\n *(__m128 *)((char *)v8 - 24) = v15;\n v8[-4].m128_i32[2] = v14;\n v8[-2].m128_i32[0] = v11;\n v8[-1].m128_i32[2] = v13;\n }\n while ( 32LL * ((unsigned int)a4 >> 2) != v10 );\n v16 = a4 & 0x7FFFFFFC;\n if ( (a4 & 3) == 0 )\n return v7;\n }\n v17 = 8LL * v16;\n v18 = 24LL * v16;\n v19 = v16;\n v20 = a3[v19];\n v21 = (__m128 *)((char *)v7 + v18);\n *v21 = _mm_loadh_ps((const double *)(a2 + v17));\n v21[1].m128_i32[0] = v20;\n if ( a4 > v16 + 1 )\n {\n v22 = (__int64)&v7[1].m128_i64[(unsigned __int64)v18 / 8 + 1];\n v23 = _mm_loadh_ps((const double *)(a2 + v17 + 8));\n *(_DWORD *)(v22 + 16) = a3[v19 + 1];\n *(__m128 *)v22 = v23;\n if ( a4 > v16 + 2 )\n {\n v24 = (__m128 *)((char *)v7 + v18 + 48);\n v24[1].m128_i32[0] = a3[v19 + 2];\n *v24 = _mm_loadh_ps((const double *)(a2 + v17 + 16));\n }\n }\n }\n return v7;\n}", + "ida_strip_asm": "sub_1860:\nendbr64\npush r13\nmovsxd rax, ecx\npush r12\nmov r13, rax\nmov r12, rdx\npush rbp\nmov rbp, rdi\nlea rdi, [rax+rax*2]\npush rbx\nshl rdi, 3; size\nmov rbx, rsi\nsub rsp, 8\ncall _malloc\nmov r8, rax\ntest r13d, r13d\njle loc_19A6\nlea eax, [r13-1]\ncmp eax, 2\njbe loc_19B4\nmov edi, r13d\nmov rax, r8\nmov rcx, r12\nxor edx, edx\nshr edi, 2\nshl rdi, 5\nnop dword ptr [rax]\nloc_18B8:\nlea rsi, [rbp+rdx+0]\nmov r9d, [rcx+8]\nmov r11d, [rcx]\nadd rax, 60h ; '`'\nmovq xmm3, qword ptr [rsi]\nmovq xmm2, qword ptr [rsi+8]\nadd rcx, 10h\nmovq xmm0, qword ptr [rsi+18h]\nmovq xmm1, qword ptr [rsi+10h]\nmovhps xmm3, qword ptr [rbx+rdx]\nmov esi, [rcx-4]\nmov r10d, [rcx-0Ch]\nmovups xmmword ptr [rax-60h], xmm3\nmovhps xmm2, qword ptr [rbx+rdx+8]\nmovups xmmword ptr [rax-48h], xmm2\nmovhps xmm1, qword ptr [rbx+rdx+10h]\nmovups xmmword ptr [rax-30h], xmm1\nmovhps xmm0, qword ptr [rbx+rdx+18h]\nadd rdx, 20h ; ' '\nmov [rax-50h], r11d\nmovups xmmword ptr [rax-18h], xmm0\nmov [rax-38h], r10d\nmov [rax-20h], r9d\nmov [rax-8], esi\ncmp rdi, rdx\njnz short loc_18B8\nmov edx, r13d\nand edx, 0FFFFFFFCh\ntest r13b, 3\njz short loc_19A6\nloc_192D:\nmovsxd rax, edx\nmovq xmm0, qword ptr [rbp+rax*8+0]\nlea rcx, [rax+rax*2]\nlea rsi, ds:0[rax*8]\nshl rcx, 3\nlea r9, ds:0[rax*4]\nmovhps xmm0, qword ptr [rbx+rax*8]\nmov eax, [r12+rax*4]\nlea rdi, [r8+rcx]\nmovups xmmword ptr [rdi], xmm0\nmov [rdi+10h], eax\nlea eax, [rdx+1]\ncmp r13d, eax\njle short loc_19A6\nmovq xmm0, qword ptr [rbp+rsi+8]\nmov edi, [r12+r9+4]\nlea rax, [r8+rcx+18h]\nadd edx, 2\nmovhps xmm0, qword ptr [rbx+rsi+8]\nmov [rax+10h], edi\nmovups xmmword ptr [rax], xmm0\ncmp r13d, edx\njle short loc_19A6\nmov edx, [r12+r9+8]\nlea rax, [r8+rcx+30h]\nmovq xmm0, qword ptr [rbp+rsi+10h]\nmov [rax+10h], edx\nmovhps xmm0, qword ptr [rbx+rsi+10h]\nmovups xmmword ptr [rax], xmm0\nloc_19A6:\nadd rsp, 8\nmov rax, r8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_19B4:\nxor edx, edx\njmp loc_192D", + "ida_strip_pseudo": "__m128 *__fastcall sub_1860(__int64 a1, __int64 a2, __int32 *a3, int a4)\n{\n __m128 *v7; // r8\n __m128 *v8; // rax\n __int32 *v9; // rcx\n __int64 v10; // rdx\n __int32 v11; // r9d\n __int32 v12; // r11d\n __int32 v13; // esi\n __int32 v14; // r10d\n __m128 v15; // xmm0\n int v16; // edx\n __int64 v17; // rsi\n __int64 v18; // rcx\n __int64 v19; // r9\n __int32 v20; // eax\n __m128 *v21; // rdi\n __int64 v22; // rax\n __m128 v23; // xmm0\n __m128 *v24; // rax\n\n v7 = (__m128 *)malloc(24LL * a4);\n if ( a4 > 0 )\n {\n if ( (unsigned int)(a4 - 1) <= 2 )\n {\n v16 = 0;\n }\n else\n {\n v8 = v7;\n v9 = a3;\n v10 = 0LL;\n do\n {\n v11 = v9[2];\n v12 = *v9;\n v8 += 6;\n v9 += 4;\n v13 = *(v9 - 1);\n v14 = *(v9 - 3);\n v8[-6] = _mm_loadh_ps((const double *)(a2 + v10));\n *(__m128 *)((char *)v8 - 72) = _mm_loadh_ps((const double *)(a2 + v10 + 8));\n v8[-3] = _mm_loadh_ps((const double *)(a2 + v10 + 16));\n v15 = _mm_loadh_ps((const double *)(a2 + v10 + 24));\n v10 += 32LL;\n v8[-5].m128_i32[0] = v12;\n *(__m128 *)((char *)v8 - 24) = v15;\n v8[-4].m128_i32[2] = v14;\n v8[-2].m128_i32[0] = v11;\n v8[-1].m128_i32[2] = v13;\n }\n while ( 32LL * ((unsigned int)a4 >> 2) != v10 );\n v16 = a4 & 0x7FFFFFFC;\n if ( (a4 & 3) == 0 )\n return v7;\n }\n v17 = 8LL * v16;\n v18 = 24LL * v16;\n v19 = v16;\n v20 = a3[v19];\n v21 = (__m128 *)((char *)v7 + v18);\n *v21 = _mm_loadh_ps((const double *)(a2 + v17));\n v21[1].m128_i32[0] = v20;\n if ( a4 > v16 + 1 )\n {\n v22 = (__int64)&v7[1].m128_i64[(unsigned __int64)v18 / 8 + 1];\n v23 = _mm_loadh_ps((const double *)(a2 + v17 + 8));\n *(_DWORD *)(v22 + 16) = a3[v19 + 1];\n *(__m128 *)v22 = v23;\n if ( a4 > v16 + 2 )\n {\n v24 = (__m128 *)((char *)v7 + v18 + 48);\n v24[1].m128_i32[0] = a3[v19 + 2];\n *v24 = _mm_loadh_ps((const double *)(a2 + v17 + 16));\n }\n }\n }\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__m128 *sub_1860(long long a1, long long a2, int *a3, int a4) {\n __m128 *v7;\n __m128 *v8;\n int *v9;\n long long v10;\n int v11;\n int v12;\n int v13;\n int v14;\n __m128 v15;\n int v16;\n long long v17;\n long long v18;\n long long v19;\n int v20;\n __m128 *v21;\n long long v22;\n __m128 v23;\n __m128 *v24;\n v7 = (__m128 *)malloc(24LL * a4);\n if (a4 > 0) {\n if ((unsigned int)(a4 - 1) <= 2) {\n v16 = 0;\n } else {\n v8 = v7;\n v9 = a3;\n v10 = 0LL;\n do {\n v11 = v9[2];\n v12 = *v9;\n v8 += 6;\n v9 += 4;\n v13 = *(v9 - 1);\n v14 = *(v9 - 3);\n v8[-6] = _mm_loadh_ps((const double *)(a2 + v10));\n *(__m128 *)((char *)v8 - 72) =\n _mm_loadh_ps((const double *)(a2 + v10 + 8));\n v8[-3] = _mm_loadh_ps((const double *)(a2 + v10 + 16));\n v15 = _mm_loadh_ps((const double *)(a2 + v10 + 24));\n v10 += 32LL;\n v8[-5].m128_i32[0] = v12;\n *(__m128 *)((char *)v8 - 24) = v15;\n v8[-4].m128_i32[2] = v14;\n v8[-2].m128_i32[0] = v11;\n v8[-1].m128_i32[2] = v13;\n } while (32LL * ((unsigned int)a4 >> 2) != v10);\n v16 = a4 & 2147483644;\n if ((a4 & 3) == 0) return v7;\n }\n v17 = 8LL * v16;\n v18 = 24LL * v16;\n v19 = v16;\n v20 = a3[v19];\n v21 = (__m128 *)((char *)v7 + v18);\n *v21 = _mm_loadh_ps((const double *)(a2 + v17));\n v21[1].m128_i32[0] = v20;\n if (a4 > v16 + 1) {\n v22 = (long long)&v7[1].m128_i64[(unsigned long long)v18 / 8 + 1];\n v23 = _mm_loadh_ps((const double *)(a2 + v17 + 8));\n *(uint32_t *)(v22 + 16) = a3[v19 + 1];\n *(__m128 *)v22 = v23;\n if (a4 > v16 + 2) {\n v24 = (__m128 *)((char *)v7 + v18 + 48);\n v24[1].m128_i32[0] = a3[v19 + 2];\n *v24 = _mm_loadh_ps((const double *)(a2 + v17 + 16));\n }\n }\n }\n return v7;\n}", + "ida_pseudo_norm": "__m128 *func0(long long a1, long long a2, int *a3, int a4) {\n __m128 *v7;\n __m128 *v8;\n int *v9;\n long long v10;\n int v11;\n int v12;\n int v13;\n int v14;\n __m128 v15;\n int v16;\n long long v17;\n long long v18;\n long long v19;\n int v20;\n __m128 *v21;\n long long v22;\n __m128 v23;\n __m128 *v24;\n v7 = (__m128 *)malloc(24LL * a4);\n if (a4 > 0) {\n if ((unsigned int)(a4 - 1) <= 2) {\n v16 = 0;\n } else {\n v8 = v7;\n v9 = a3;\n v10 = 0LL;\n do {\n v11 = v9[2];\n v12 = *v9;\n v8 += 6;\n v9 += 4;\n v13 = *(v9 - 1);\n v14 = *(v9 - 3);\n v8[-6] = _mm_loadh_ps((const double *)(a2 + v10));\n *(__m128 *)((char *)v8 - 72) =\n _mm_loadh_ps((const double *)(a2 + v10 + 8));\n v8[-3] = _mm_loadh_ps((const double *)(a2 + v10 + 16));\n v15 = _mm_loadh_ps((const double *)(a2 + v10 + 24));\n v10 += 32LL;\n v8[-5].m128_i32[0] = v12;\n *(__m128 *)((char *)v8 - 24) = v15;\n v8[-4].m128_i32[2] = v14;\n v8[-2].m128_i32[0] = v11;\n v8[-1].m128_i32[2] = v13;\n } while (32LL * ((unsigned int)a4 >> 2) != v10);\n v16 = a4 & 2147483644;\n if ((a4 & 3) == 0) return v7;\n }\n v17 = 8LL * v16;\n v18 = 24LL * v16;\n v19 = v16;\n v20 = a3[v19];\n v21 = (__m128 *)((char *)v7 + v18);\n *v21 = _mm_loadh_ps((const double *)(a2 + v17));\n v21[1].m128_i32[0] = v20;\n if (a4 > v16 + 1) {\n v22 = (long long)&v7[1].m128_i64[(unsigned long long)v18 / 8 + 1];\n v23 = _mm_loadh_ps((const double *)(a2 + v17 + 8));\n *(uint32_t *)(v22 + 16) = a3[v19 + 1];\n *(__m128 *)v22 = v23;\n if (a4 > v16 + 2) {\n v24 = (__m128 *)((char *)v7 + v18 + 48);\n v24[1].m128_i32[0] = a3[v19 + 2];\n *v24 = _mm_loadh_ps((const double *)(a2 + v17 + 16));\n }\n }\n }\n return v7;\n}" + }, + { + "index": 392, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int res[n + 1];\n res[0] = 0;\n res[1] = 1;\n int i = 2;\n while (i < n + 1) {\n res[i] = i;\n int temp = res[i / 2] + res[i / 3] + res[i / 4] + res[i / 5];\n if (temp > res[i]) res[i] = temp;\n i++;\n }\n return res[n];\n}", + "test": "int main() {\n\n assert(func0(60) == 106);\n\n assert(func0(10) == 12);\n\n assert(func0(2) == 2);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x38,%rsp\nmov %edi,-0x34(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmov %rsp,%rax\nmov %rax,%rsi\nmov -0x34(%rbp),%eax\nadd $0x1,%eax\nmovslq %eax,%rdx\nsub $0x1,%rdx\nmov %rdx,-0x28(%rbp)\nmovslq %eax,%rdx\nmov %rdx,%r8\nmov $0x0,%r9d\nmovslq %eax,%rdx\nmov %rdx,%rcx\nmov $0x0,%ebx\ncltq\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%edi\nmov $0x0,%edx\ndiv %rdi\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rbx\nsub %rdx,%rbx\nmov %rbx,%rdx\ncmp %rdx,%rsp\nje 1207 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11f0 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 1231 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x20(%rbp)\nmov -0x20(%rbp),%rax\nmovl $0x0,(%rax)\nmov -0x20(%rbp),%rax\nmovl $0x1,0x4(%rax)\nmovl $0x2,-0x30(%rbp)\njmpq 1318 \nmov -0x20(%rbp),%rax\nmov -0x30(%rbp),%edx\nmovslq %edx,%rdx\nmov -0x30(%rbp),%ecx\nmov %ecx,(%rax,%rdx,4)\nmov -0x30(%rbp),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nmov %eax,%edx\nmov -0x20(%rbp),%rax\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%ecx\nmov -0x30(%rbp),%eax\nmovslq %eax,%rdx\nimul $0x55555556,%rdx,%rdx\nshr $0x20,%rdx\nsar $0x1f,%eax\nsub %eax,%edx\nmov -0x20(%rbp),%rax\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nadd %eax,%ecx\nmov -0x30(%rbp),%eax\nlea 0x3(%rax),%edx\ntest %eax,%eax\ncmovs %edx,%eax\nsar $0x2,%eax\nmov %eax,%edx\nmov -0x20(%rbp),%rax\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nadd %eax,%ecx\nmov -0x30(%rbp),%eax\nmovslq %eax,%rdx\nimul $0x66666667,%rdx,%rdx\nshr $0x20,%rdx\nsar %edx\nsar $0x1f,%eax\nsub %eax,%edx\nmov -0x20(%rbp),%rax\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nadd %ecx,%eax\nmov %eax,-0x2c(%rbp)\nmov -0x20(%rbp),%rax\nmov -0x30(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\ncmp %eax,-0x2c(%rbp)\njle 1314 \nmov -0x20(%rbp),%rax\nmov -0x30(%rbp),%edx\nmovslq %edx,%rdx\nmov -0x2c(%rbp),%ecx\nmov %ecx,(%rax,%rdx,4)\naddl $0x1,-0x30(%rbp)\nmov -0x34(%rbp),%eax\ncmp -0x30(%rbp),%eax\njge 1265 \nmov -0x20(%rbp),%rax\nmov -0x34(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nmov %rsi,%rsp\nmov -0x18(%rbp),%rdi\nxor %fs:0x28,%rdi\nje 1348 \ncallq 1060 <__stack_chk_fail@plt>\nmov -0x8(%rbp),%rbx\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_24], edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov eax, [rbp+var_24]\nadd eax, 1\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11D5:\ncmp rsp, rdx\njz short loc_11EC\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\njmp short loc_11D5\nloc_11EC:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1216\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1216:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov rax, [rbp+var_10]\nmov dword ptr [rax], 0\nmov rax, [rbp+var_10]\nmov dword ptr [rax+4], 1\nmov [rbp+var_20], 2\njmp loc_12FD\nloc_124A:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nmov ecx, [rbp+var_20]\nmov [rax+rdx*4], ecx\nmov eax, [rbp+var_20]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov edx, eax\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov eax, [rbp+var_20]\nmovsxd rdx, eax\nimul rdx, 55555556h\nshr rdx, 20h\nsar eax, 1Fh\nsub edx, eax\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nadd ecx, eax\nmov eax, [rbp+var_20]\nlea edx, [rax+3]\ntest eax, eax\ncmovs eax, edx\nsar eax, 2\nmov edx, eax\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nadd ecx, eax\nmov eax, [rbp+var_20]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nsar edx, 1\nsar eax, 1Fh\nsub edx, eax\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nadd eax, ecx\nmov [rbp+var_1C], eax\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ncmp [rbp+var_1C], eax\njle short loc_12F9\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nmov ecx, [rbp+var_1C]\nmov [rax+rdx*4], ecx\nloc_12F9:\nadd [rbp+var_20], 1\nloc_12FD:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_20]\njge loc_124A\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_132D\ncall ___stack_chk_fail\nlocret_132D:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned __int64 v1; // rax\n void *v2; // rsp\n _DWORD v4[3]; // [rsp+8h] [rbp-30h] BYREF\n int v5; // [rsp+14h] [rbp-24h]\n int i; // [rsp+18h] [rbp-20h]\n int v7; // [rsp+1Ch] [rbp-1Ch]\n __int64 v8; // [rsp+20h] [rbp-18h]\n _DWORD *v9; // [rsp+28h] [rbp-10h]\n unsigned __int64 v10; // [rsp+30h] [rbp-8h]\n\n v5 = a1;\n v10 = __readfsqword(0x28u);\n v8 = a1 + 1 - 1LL;\n v1 = 16 * ((4LL * (a1 + 1) + 15) / 0x10uLL);\n while ( v4 != (_DWORD *)((char *)v4 - (v1 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v2 = alloca(v1 & 0xFFF);\n if ( (v1 & 0xFFF) != 0 )\n *(_QWORD *)((char *)&v4[-2] + (v1 & 0xFFF)) = *(_QWORD *)((char *)&v4[-2] + (v1 & 0xFFF));\n v9 = v4;\n v4[0] = 0;\n v4[1] = 1;\n for ( i = 2; v5 >= i; ++i )\n {\n v9[i] = i;\n v7 = v9[i / 4] + v9[i / 3] + v9[i / 2] + v9[i / 5];\n if ( v7 > v9[i] )\n v9[i] = v7;\n }\n return (unsigned int)v9[v5];\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_24], edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov eax, [rbp+var_24]\nadd eax, 1\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11D5:\ncmp rsp, rdx\njz short loc_11EC\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\njmp short loc_11D5\nloc_11EC:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1216\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1216:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov rax, [rbp+var_10]\nmov dword ptr [rax], 0\nmov rax, [rbp+var_10]\nmov dword ptr [rax+4], 1\nmov [rbp+var_20], 2\njmp loc_12FD\nloc_124A:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nmov ecx, [rbp+var_20]\nmov [rax+rdx*4], ecx\nmov eax, [rbp+var_20]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov edx, eax\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov eax, [rbp+var_20]\nmovsxd rdx, eax\nimul rdx, 55555556h\nshr rdx, 20h\nsar eax, 1Fh\nsub edx, eax\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nadd ecx, eax\nmov eax, [rbp+var_20]\nlea edx, [rax+3]\ntest eax, eax\ncmovs eax, edx\nsar eax, 2\nmov edx, eax\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nadd ecx, eax\nmov eax, [rbp+var_20]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nsar edx, 1\nsar eax, 1Fh\nsub edx, eax\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nadd eax, ecx\nmov [rbp+var_1C], eax\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ncmp [rbp+var_1C], eax\njle short loc_12F9\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nmov ecx, [rbp+var_1C]\nmov [rax+rdx*4], ecx\nloc_12F9:\nadd [rbp+var_20], 1\nloc_12FD:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_20]\njge loc_124A\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_132D\ncall ___stack_chk_fail\nlocret_132D:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n unsigned __int64 v1; // rax\n void *v2; // rsp\n _DWORD v4[3]; // [rsp+8h] [rbp-30h] BYREF\n int v5; // [rsp+14h] [rbp-24h]\n int i; // [rsp+18h] [rbp-20h]\n int v7; // [rsp+1Ch] [rbp-1Ch]\n __int64 v8; // [rsp+20h] [rbp-18h]\n _DWORD *v9; // [rsp+28h] [rbp-10h]\n unsigned __int64 v10; // [rsp+30h] [rbp-8h]\n\n v5 = a1;\n v10 = __readfsqword(0x28u);\n v8 = a1 + 1 - 1LL;\n v1 = 16 * ((4LL * (a1 + 1) + 15) / 0x10uLL);\n while ( v4 != (_DWORD *)((char *)v4 - (v1 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v2 = alloca(v1 & 0xFFF);\n if ( (v1 & 0xFFF) != 0 )\n *(_QWORD *)((char *)&v4[-2] + (v1 & 0xFFF)) = *(_QWORD *)((char *)&v4[-2] + (v1 & 0xFFF));\n v9 = v4;\n v4[0] = 0;\n v4[1] = 1;\n for ( i = 2; v5 >= i; ++i )\n {\n v9[i] = i;\n v7 = v9[i / 4] + v9[i / 3] + v9[i / 2] + v9[i / 5];\n if ( v7 > v9[i] )\n v9[i] = v7;\n }\n return (unsigned int)v9[v5];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n unsigned long long v1;\n void *v2;\n uint32_t v4[3];\n int v5;\n int i;\n int v7;\n long long v8;\n uint32_t *v9;\n unsigned long long v10;\n v5 = a1;\n v10 = __readfsqword(40u);\n v8 = a1 + 1 - 1LL;\n v1 = 16 * ((4LL * (a1 + 1) + 15) / 16uLL);\n while (v4 != (uint32_t *)((char *)v4 - (v1 & 18446744073709547520LL)))\n ;\n v2 = alloca(v1 & 4095);\n if ((v1 & 4095) != 0)\n *(uint64_t *)((char *)&v4[-2] + (v1 & 4095)) =\n *(uint64_t *)((char *)&v4[-2] + (v1 & 4095));\n v9 = v4;\n v4[0] = 0;\n v4[1] = 1;\n for (i = 2; v5 >= i; ++i) {\n v9[i] = i;\n v7 = v9[i / 4] + v9[i / 3] + v9[i / 2] + v9[i / 5];\n if (v7 > v9[i]) v9[i] = v7;\n }\n return (unsigned int)v9[v5];\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned long long v1;\n void *v2;\n uint32_t v4[3];\n int v5;\n int i;\n int v7;\n long long v8;\n uint32_t *v9;\n unsigned long long v10;\n v5 = a1;\n v10 = __readfsqword(40u);\n v8 = a1 + 1 - 1LL;\n v1 = 16 * ((4LL * (a1 + 1) + 15) / 16uLL);\n while (v4 != (uint32_t *)((char *)v4 - (v1 & 18446744073709547520LL)))\n ;\n v2 = alloca(v1 & 4095);\n if ((v1 & 4095) != 0)\n *(uint64_t *)((char *)&v4[-2] + (v1 & 4095)) =\n *(uint64_t *)((char *)&v4[-2] + (v1 & 4095));\n v9 = v4;\n v4[0] = 0;\n v4[1] = 1;\n for (i = 2; v5 >= i; ++i) {\n v9[i] = i;\n v7 = v9[i / 4] + v9[i / 3] + v9[i / 2] + v9[i / 5];\n if (v7 > v9[i]) v9[i] = v7;\n }\n return (unsigned int)v9[v5];\n}" + }, + { + "index": 392, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int res[n + 1];\n res[0] = 0;\n res[1] = 1;\n int i = 2;\n while (i < n + 1) {\n res[i] = i;\n int temp = res[i / 2] + res[i / 3] + res[i / 4] + res[i / 5];\n if (temp > res[i]) res[i] = temp;\n i++;\n }\n return res[n];\n}", + "test": "int main() {\n\n assert(func0(60) == 106);\n\n assert(func0(10) == 12);\n\n assert(func0(2) == 2);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0x1(%rdi),%eax\ncltq\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffffff0,%rdx\nand $0xfffffffffffff000,%rax\nmov %rsp,%rsi\nsub %rax,%rsi\nmov %rsi,%rax\ncmp %rax,%rsp\nje 11be \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11a7 \nmov %rdx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 11d4 \norq $0x0,-0x8(%rsp,%rax,1)\nlea 0x3(%rsp),%r9\nmov %r9,%rax\nshr $0x2,%rax\nand $0xfffffffffffffffc,%r9\nmov %r9,%rsi\nmovl $0x0,0x0(,%rax,4)\nmovl $0x1,0x4(,%rax,4)\ncmp $0x1,%edi\njle 127e \nlea -0x2(%rdi),%r8d\nadd $0x3,%r8\nmov $0x2,%eax\nmov %eax,(%rsi,%rax,4)\nmov %eax,%r10d\nshr $0x1f,%r10d\nadd %eax,%r10d\nsar %r10d\nmovslq %r10d,%r10\nmovslq %eax,%rcx\nimul $0x55555556,%rcx,%rdx\nshr $0x20,%rdx\nmov %eax,%r11d\nsar $0x1f,%r11d\nsub %r11d,%edx\nmovslq %edx,%rdx\nmov (%rsi,%rdx,4),%edx\nadd (%rsi,%r10,4),%edx\nlea 0x3(%rax),%r10d\ntest %eax,%eax\ncmovns %eax,%r10d\nsar $0x2,%r10d\nmovslq %r10d,%r10\nadd (%rsi,%r10,4),%edx\nimul $0x66666667,%rcx,%rcx\nsar $0x21,%rcx\nsub %r11d,%ecx\nmovslq %ecx,%rcx\nadd (%rsi,%rcx,4),%edx\ncmp %eax,%edx\ncmovle %eax,%edx\nmov %edx,(%rsi,%rax,4)\nadd $0x1,%rax\ncmp %r8,%rax\njne 120f \nmovslq %edi,%rdi\nmov (%r9,%rdi,4),%eax\nmov -0x8(%rbp),%rdi\nxor %fs:0x28,%rdi\njne 1296 \nleaveq\nretq\ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov r9d, edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea eax, [rdi+1]\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11A7:\ncmp rsp, rdx\njz short loc_11BE\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11A7\nloc_11BE:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11D4\nor [rsp+rax+10h+var_18], 0\nloc_11D4:\nlea rdi, [rsp+10h+var_D]\nmov rax, rdi\nshr rax, 2\nand rdi, 0FFFFFFFFFFFFFFFCh\nmov ds:dword_0[rax*4], 0\nmov dword ptr ds:byte_4[rax*4], 1\ncmp r9d, 1\njle short loc_1276\nlea r8d, [r9+1]\nmov eax, 2\njmp short loc_1217\nloc_120B:\nmov [rdi+rax*4], edx\nadd rax, 1\ncmp rax, r8\njz short loc_1276\nloc_1217:\nmov [rdi+rax*4], eax\nmov esi, eax\nshr esi, 1Fh\nadd esi, eax\nsar esi, 1\nmovsxd rsi, esi\nmovsxd rdx, eax\nimul rcx, rdx, 55555556h\nshr rcx, 20h\nmov r10d, eax\nsar r10d, 1Fh\nsub ecx, r10d\nmovsxd rcx, ecx\nmov ecx, [rdi+rcx*4]\nadd ecx, [rdi+rsi*4]\nlea esi, [rax+3]\ntest eax, eax\ncmovns esi, eax\nsar esi, 2\nmovsxd rsi, esi\nadd ecx, [rdi+rsi*4]\nimul rdx, 66666667h\nsar rdx, 21h\nsub edx, r10d\nmovsxd rdx, edx\nadd ecx, [rdi+rdx*4]\nmov edx, ecx\ncmp ecx, eax\njg short loc_120B\nmov edx, eax\njmp short loc_120B\nloc_1276:\nmovsxd r9, r9d\nmov eax, [rdi+r9*4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_128E\nleave\nretn\nloc_128E:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n signed __int64 v1; // rax\n void *v2; // rsp\n unsigned __int64 v3; // rax\n __int64 v4; // rax\n int v5; // edx\n _BYTE v8[3]; // [rsp+8h] [rbp-10h] BYREF\n char v9; // [rsp+Bh] [rbp-Dh] BYREF\n unsigned __int64 v10; // [rsp+10h] [rbp-8h]\n\n v10 = __readfsqword(0x28u);\n while ( v8 != &v8[-((4LL * (a1 + 1) + 15) & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v1 = (4 * ((_WORD)a1 + 1) + 15) & 0xFF0;\n v2 = alloca(v1);\n if ( ((4 * ((_WORD)a1 + 1) + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v8[v1 - 8] = *(_QWORD *)&v8[v1 - 8];\n v3 = (unsigned __int64)&v9 >> 2;\n *(_DWORD *)(4 * v3) = 0;\n *(_DWORD *)&byte_4[4 * v3] = 1;\n if ( a1 > 1 )\n {\n v4 = 2LL;\n do\n {\n *(_DWORD *)&v8[4 * v4] = v4;\n v5 = *(_DWORD *)&v8[4 * ((int)v4 / 5)]\n + *(_DWORD *)&v8[4 * ((int)v4 / 4)]\n + *(_DWORD *)&v8[4 * ((int)v4 / 2)]\n + *(_DWORD *)&v8[4 * ((int)v4 / 3)];\n if ( v5 <= (int)v4 )\n v5 = v4;\n *(_DWORD *)&v8[4 * v4++] = v5;\n }\n while ( v4 != a1 + 1 );\n }\n return *(unsigned int *)&v8[4 * a1];\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov r9d, edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea eax, [rdi+1]\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11A7:\ncmp rsp, rdx\njz short loc_11BE\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11A7\nloc_11BE:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11D4\nor [rsp+rax+10h+var_18], 0\nloc_11D4:\nlea rdi, [rsp+10h+var_D]\nmov rax, rdi\nshr rax, 2\nand rdi, 0FFFFFFFFFFFFFFFCh\nmov ds:dword_0[rax*4], 0\nmov dword ptr ds:byte_4[rax*4], 1\ncmp r9d, 1\njle short loc_1276\nlea r8d, [r9+1]\nmov eax, 2\njmp short loc_1217\nloc_120B:\nmov [rdi+rax*4], edx\nadd rax, 1\ncmp rax, r8\njz short loc_1276\nloc_1217:\nmov [rdi+rax*4], eax\nmov esi, eax\nshr esi, 1Fh\nadd esi, eax\nsar esi, 1\nmovsxd rsi, esi\nmovsxd rdx, eax\nimul rcx, rdx, 55555556h\nshr rcx, 20h\nmov r10d, eax\nsar r10d, 1Fh\nsub ecx, r10d\nmovsxd rcx, ecx\nmov ecx, [rdi+rcx*4]\nadd ecx, [rdi+rsi*4]\nlea esi, [rax+3]\ntest eax, eax\ncmovns esi, eax\nsar esi, 2\nmovsxd rsi, esi\nadd ecx, [rdi+rsi*4]\nimul rdx, 66666667h\nsar rdx, 21h\nsub edx, r10d\nmovsxd rdx, edx\nadd ecx, [rdi+rdx*4]\nmov edx, ecx\ncmp ecx, eax\njg short loc_120B\nmov edx, eax\njmp short loc_120B\nloc_1276:\nmovsxd r9, r9d\nmov eax, [rdi+r9*4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_128E\nleave\nretn\nloc_128E:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n signed __int64 v1; // rax\n void *v2; // rsp\n unsigned __int64 v3; // rax\n __int64 v4; // rax\n int v5; // edx\n _BYTE v8[3]; // [rsp+8h] [rbp-10h] BYREF\n char v9; // [rsp+Bh] [rbp-Dh] BYREF\n unsigned __int64 v10; // [rsp+10h] [rbp-8h]\n\n v10 = __readfsqword(0x28u);\n while ( v8 != &v8[-((4LL * (a1 + 1) + 15) & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v1 = (4 * ((_WORD)a1 + 1) + 15) & 0xFF0;\n v2 = alloca(v1);\n if ( ((4 * ((_WORD)a1 + 1) + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v8[v1 - 8] = *(_QWORD *)&v8[v1 - 8];\n v3 = (unsigned __int64)&v9 >> 2;\n *(_DWORD *)(4 * v3) = 0;\n *(_DWORD *)&byte_4[4 * v3] = 1;\n if ( a1 > 1 )\n {\n v4 = 2LL;\n do\n {\n *(_DWORD *)&v8[4 * v4] = v4;\n v5 = *(_DWORD *)&v8[4 * ((int)v4 / 5)]\n + *(_DWORD *)&v8[4 * ((int)v4 / 4)]\n + *(_DWORD *)&v8[4 * ((int)v4 / 2)]\n + *(_DWORD *)&v8[4 * ((int)v4 / 3)];\n if ( v5 <= (int)v4 )\n v5 = v4;\n *(_DWORD *)&v8[4 * v4++] = v5;\n }\n while ( v4 != a1 + 1 );\n }\n return *(unsigned int *)&v8[4 * a1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n signed long long v1;\n void *v2;\n unsigned long long v3;\n long long v4;\n int v5;\n uint8_t v8[3];\n char v9;\n unsigned long long v10;\n v10 = __readfsqword(40u);\n while (v8 != &v8[-((4LL * (a1 + 1) + 15) & 18446744073709547520LL)])\n ;\n v1 = (4 * ((unsigned short)a1 + 1) + 15) & 4080;\n v2 = alloca(v1);\n if (((4 * ((unsigned short)a1 + 1) + 15) & 4080) != 0)\n *(uint64_t *)&v8[v1 - 8] = *(uint64_t *)&v8[v1 - 8];\n v3 = (unsigned long long)&v9 >> 2;\n *(uint32_t *)(4 * v3) = 0;\n *(uint32_t *)&byte_4[4 * v3] = 1;\n if (a1 > 1) {\n v4 = 2LL;\n do {\n *(uint32_t *)&v8[4 * v4] = v4;\n v5 = *(uint32_t *)&v8[4 * ((int)v4 / 5)] +\n *(uint32_t *)&v8[4 * ((int)v4 / 4)] +\n *(uint32_t *)&v8[4 * ((int)v4 / 2)] +\n *(uint32_t *)&v8[4 * ((int)v4 / 3)];\n if (v5 <= (int)v4) v5 = v4;\n *(uint32_t *)&v8[4 * v4++] = v5;\n } while (v4 != a1 + 1);\n }\n return *(unsigned int *)&v8[4 * a1];\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n signed long long v1;\n void *v2;\n unsigned long long v3;\n long long v4;\n int v5;\n uint8_t v8[3];\n char v9;\n unsigned long long v10;\n v10 = __readfsqword(40u);\n while (v8 != &v8[-((4LL * (a1 + 1) + 15) & 18446744073709547520LL)])\n ;\n v1 = (4 * ((unsigned short)a1 + 1) + 15) & 4080;\n v2 = alloca(v1);\n if (((4 * ((unsigned short)a1 + 1) + 15) & 4080) != 0)\n *(uint64_t *)&v8[v1 - 8] = *(uint64_t *)&v8[v1 - 8];\n v3 = (unsigned long long)&v9 >> 2;\n *(uint32_t *)(4 * v3) = 0;\n *(uint32_t *)&byte_4[4 * v3] = 1;\n if (a1 > 1) {\n v4 = 2LL;\n do {\n *(uint32_t *)&v8[4 * v4] = v4;\n v5 = *(uint32_t *)&v8[4 * ((int)v4 / 5)] +\n *(uint32_t *)&v8[4 * ((int)v4 / 4)] +\n *(uint32_t *)&v8[4 * ((int)v4 / 2)] +\n *(uint32_t *)&v8[4 * ((int)v4 / 3)];\n if (v5 <= (int)v4) v5 = v4;\n *(uint32_t *)&v8[4 * v4++] = v5;\n } while (v4 != a1 + 1);\n }\n return *(unsigned int *)&v8[4 * a1];\n}" + }, + { + "index": 392, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int res[n + 1];\n res[0] = 0;\n res[1] = 1;\n int i = 2;\n while (i < n + 1) {\n res[i] = i;\n int temp = res[i / 2] + res[i / 3] + res[i / 4] + res[i / 5];\n if (temp > res[i]) res[i] = temp;\n i++;\n }\n return res[n];\n}", + "test": "int main() {\n\n assert(func0(60) == 106);\n\n assert(func0(10) == 12);\n\n assert(func0(2) == 2);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0x1(%rdi),%eax\nmov %rsp,%rsi\ncltq\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rsi\nand $0xfffffffffffffff0,%rdx\nmov %rsi,%rax\ncmp %rax,%rsp\nje 1268 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 1253 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 1338 \nmovabs $0x100000000,%rcx\nlea 0x3(%rsp),%rsi\nmov %rsi,%rax\nand $0xfffffffffffffffc,%rsi\nshr $0x2,%rax\nmov %rcx,0x0(,%rax,4)\ncmp $0x1,%edi\njle 131a \nlea -0x2(%rdi),%r8d\nmov $0xaaaaaaab,%r10d\nmovl $0x2,0x8(,%rax,4)\nmov $0xcccccccd,%r9d\nadd $0x3,%r8\nmov $0x3,%eax\njmp 1315 \nnopw 0x0(%rax,%rax,1)\nmov %eax,%ecx\nmov %eax,%r11d\nmov %eax,(%rsi,%rax,4)\nmov %rcx,%rdx\nsar %r11d\nimul %r9,%rcx\nimul %r10,%rdx\nmovslq %r11d,%r11\nshr $0x22,%rcx\nshr $0x21,%rdx\nmov (%rsi,%rdx,4),%edx\nadd (%rsi,%r11,4),%edx\nmov %eax,%r11d\nsar $0x2,%r11d\nmovslq %r11d,%r11\nadd (%rsi,%r11,4),%edx\nadd (%rsi,%rcx,4),%edx\ncmp %eax,%edx\ncmovle %eax,%edx\nmov %edx,(%rsi,%rax,4)\nadd $0x1,%rax\ncmp %r8,%rax\njne 12d0 \nmovslq %edi,%rdi\nmov (%rsi,%rdi,4),%eax\nmov -0x8(%rbp),%rdi\nxor %fs:0x28,%rdi\njne 1343 \nleaveq\nretq\nnopl 0x0(%rax)\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 127a \ncallq 1060 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmovsxd r11, edi\nlea r8d, [r11+1]\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmovsxd rax, r8d\nmov rcx, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_126A\nloc_1255:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rcx\njnz short loc_1255\nloc_126A:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1318\nloc_127C:\nlea rsi, [rsp+1010h+var_100D]\nmov rdx, cs:qword_2060\nmov r8d, r8d\nmov r10d, 0AAAAAAABh\nmov rax, rsi\nmov r9d, 0CCCCCCCDh\nand rsi, 0FFFFFFFFFFFFFFFCh\nshr rax, 2\nmov qword ptr ds:dword_0[rax*4], rdx\nmov edx, 2\ncmp r11d, 1\njle short loc_12FC\nnop dword ptr [rax]\nloc_12B8:\nmov ecx, edx\nmov edi, edx\nmov [rsi+rdx*4], edx\nmov rax, rcx\nsar edi, 1\nimul rcx, r9\nimul rax, r10\nmovsxd rdi, edi\nshr rcx, 22h\nshr rax, 21h\nmov eax, [rsi+rax*4]\nadd eax, [rsi+rdi*4]\nmov edi, edx\nsar edi, 2\nmovsxd rdi, edi\nadd eax, [rsi+rdi*4]\nadd eax, [rsi+rcx*4]\ncmp eax, edx\ncmovl eax, edx\nmov [rsi+rdx*4], eax\nadd rdx, 1\ncmp r8, rdx\njnz short loc_12B8\nloc_12FC:\nmov eax, [rsi+r11*4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_1323\nleave\nretn\nloc_1318:\nor [rsp+rdx+1010h+var_1018], 0\njmp loc_127C\nloc_1323:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n __int64 v1; // rdx\n _QWORD *v2; // rcx\n __int16 v3; // dx\n signed __int64 v4; // rdx\n void *v5; // rsp\n __int64 v6; // rdx\n int v7; // eax\n _QWORD v10[511]; // [rsp+8h] [rbp-1010h] BYREF\n _QWORD v11[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v11[1] = __readfsqword(0x28u);\n v1 = 4LL * (a1 + 1) + 15;\n v2 = (_QWORD *)((char *)v11 - (v1 & 0xFFFFFFFFFFFFF000LL));\n v3 = v1 & 0xFFF0;\n if ( v11 != v2 )\n {\n while ( v10 != v2 )\n ;\n }\n v4 = v3 & 0xFFF;\n v5 = alloca(v4);\n if ( v4 )\n *(_QWORD *)((char *)&v10[-1] + v4) = *(_QWORD *)((char *)&v10[-1] + v4);\n v10[0] = 0x100000000LL;\n v6 = 2LL;\n if ( a1 > 1 )\n {\n do\n {\n *((_DWORD *)v10 + v6) = v6;\n v7 = *((_DWORD *)v10 + (unsigned int)v6 / 5uLL)\n + *((_DWORD *)v10 + ((int)v6 >> 2))\n + *((_DWORD *)v10 + ((int)v6 >> 1))\n + *((_DWORD *)v10 + (unsigned int)v6 / 3uLL);\n if ( v7 < (int)v6 )\n v7 = v6;\n *((_DWORD *)v10 + v6++) = v7;\n }\n while ( a1 + 1 != v6 );\n }\n return *((unsigned int *)v10 + a1);\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbp\nmovsxd r11, edi\nlea r8d, [r11+1]\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmovsxd rax, r8d\nmov rcx, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_126A\nloc_1255:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rcx\njnz short loc_1255\nloc_126A:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1318\nloc_127C:\nlea rsi, [rsp+1010h+var_100D]\nmov rdx, cs:qword_2060\nmov r8d, r8d\nmov r10d, 0AAAAAAABh\nmov rax, rsi\nmov r9d, 0CCCCCCCDh\nand rsi, 0FFFFFFFFFFFFFFFCh\nshr rax, 2\nmov qword ptr ds:dword_0[rax*4], rdx\nmov edx, 2\ncmp r11d, 1\njle short loc_12FC\nnop dword ptr [rax]\nloc_12B8:\nmov ecx, edx\nmov edi, edx\nmov [rsi+rdx*4], edx\nmov rax, rcx\nsar edi, 1\nimul rcx, r9\nimul rax, r10\nmovsxd rdi, edi\nshr rcx, 22h\nshr rax, 21h\nmov eax, [rsi+rax*4]\nadd eax, [rsi+rdi*4]\nmov edi, edx\nsar edi, 2\nmovsxd rdi, edi\nadd eax, [rsi+rdi*4]\nadd eax, [rsi+rcx*4]\ncmp eax, edx\ncmovl eax, edx\nmov [rsi+rdx*4], eax\nadd rdx, 1\ncmp r8, rdx\njnz short loc_12B8\nloc_12FC:\nmov eax, [rsi+r11*4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_1323\nleave\nretn\nloc_1318:\nor [rsp+rdx+1010h+var_1018], 0\njmp loc_127C\nloc_1323:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(int a1)\n{\n __int64 v1; // rdx\n _QWORD *v2; // rcx\n __int16 v3; // dx\n signed __int64 v4; // rdx\n void *v5; // rsp\n __int64 v6; // rdx\n int v7; // eax\n _QWORD v10[511]; // [rsp+8h] [rbp-1010h] BYREF\n _QWORD v11[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v11[1] = __readfsqword(0x28u);\n v1 = 4LL * (a1 + 1) + 15;\n v2 = (_QWORD *)((char *)v11 - (v1 & 0xFFFFFFFFFFFFF000LL));\n v3 = v1 & 0xFFF0;\n if ( v11 != v2 )\n {\n while ( v10 != v2 )\n ;\n }\n v4 = v3 & 0xFFF;\n v5 = alloca(v4);\n if ( v4 )\n *(_QWORD *)((char *)&v10[-1] + v4) = *(_QWORD *)((char *)&v10[-1] + v4);\n v10[0] = 0x100000000LL;\n v6 = 2LL;\n if ( a1 > 1 )\n {\n do\n {\n *((_DWORD *)v10 + v6) = v6;\n v7 = *((_DWORD *)v10 + (unsigned int)v6 / 5uLL)\n + *((_DWORD *)v10 + ((int)v6 >> 2))\n + *((_DWORD *)v10 + ((int)v6 >> 1))\n + *((_DWORD *)v10 + (unsigned int)v6 / 3uLL);\n if ( v7 < (int)v6 )\n v7 = v6;\n *((_DWORD *)v10 + v6++) = v7;\n }\n while ( a1 + 1 != v6 );\n }\n return *((unsigned int *)v10 + a1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(int a1) {\n long long v1;\n uint64_t *v2;\n short v3;\n signed long long v4;\n void *v5;\n long long v6;\n int v7;\n uint64_t v10[511];\n uint64_t v11[2];\n v11[1] = __readfsqword(40u);\n v1 = 4LL * (a1 + 1) + 15;\n v2 = (uint64_t *)((char *)v11 - (v1 & 18446744073709547520LL));\n v3 = v1 & 65520;\n if (v11 != v2) {\n while (v10 != v2)\n ;\n }\n v4 = v3 & 4095;\n v5 = alloca(v4);\n if (v4)\n *(uint64_t *)((char *)&v10[-1] + v4) = *(uint64_t *)((char *)&v10[-1] + v4);\n v10[0] = 4294967296LL;\n v6 = 2LL;\n if (a1 > 1) {\n do {\n *((uint32_t *)v10 + v6) = v6;\n v7 = *((uint32_t *)v10 + (unsigned int)v6 / 5uLL) +\n *((uint32_t *)v10 + ((int)v6 >> 2)) +\n *((uint32_t *)v10 + ((int)v6 >> 1)) +\n *((uint32_t *)v10 + (unsigned int)v6 / 3uLL);\n if (v7 < (int)v6) v7 = v6;\n *((uint32_t *)v10 + v6++) = v7;\n } while (a1 + 1 != v6);\n }\n return *((unsigned int *)v10 + a1);\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n long long v1;\n uint64_t *v2;\n short v3;\n signed long long v4;\n void *v5;\n long long v6;\n int v7;\n uint64_t v10[511];\n uint64_t v11[2];\n v11[1] = __readfsqword(40u);\n v1 = 4LL * (a1 + 1) + 15;\n v2 = (uint64_t *)((char *)v11 - (v1 & 18446744073709547520LL));\n v3 = v1 & 65520;\n if (v11 != v2) {\n while (v10 != v2)\n ;\n }\n v4 = v3 & 4095;\n v5 = alloca(v4);\n if (v4)\n *(uint64_t *)((char *)&v10[-1] + v4) = *(uint64_t *)((char *)&v10[-1] + v4);\n v10[0] = 4294967296LL;\n v6 = 2LL;\n if (a1 > 1) {\n do {\n *((uint32_t *)v10 + v6) = v6;\n v7 = *((uint32_t *)v10 + (unsigned int)v6 / 5uLL) +\n *((uint32_t *)v10 + ((int)v6 >> 2)) +\n *((uint32_t *)v10 + ((int)v6 >> 1)) +\n *((uint32_t *)v10 + (unsigned int)v6 / 3uLL);\n if (v7 < (int)v6) v7 = v6;\n *((uint32_t *)v10 + v6++) = v7;\n } while (a1 + 1 != v6);\n }\n return *((unsigned int *)v10 + a1);\n}" + }, + { + "index": 392, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int res[n + 1];\n res[0] = 0;\n res[1] = 1;\n int i = 2;\n while (i < n + 1) {\n res[i] = i;\n int temp = res[i / 2] + res[i / 3] + res[i / 4] + res[i / 5];\n if (temp > res[i]) res[i] = temp;\n i++;\n }\n return res[n];\n}", + "test": "int main() {\n\n assert(func0(60) == 106);\n\n assert(func0(10) == 12);\n\n assert(func0(2) == 2);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0x1(%rdi),%eax\nmov %rsp,%rsi\ncltq\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rsi\nand $0xfffffffffffffff0,%rdx\nmov %rsi,%rax\ncmp %rax,%rsp\nje 1268 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 1253 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 1338 \nmovabs $0x100000000,%rcx\nlea 0x3(%rsp),%rsi\nmov %rsi,%rax\nand $0xfffffffffffffffc,%rsi\nshr $0x2,%rax\nmov %rcx,0x0(,%rax,4)\ncmp $0x1,%edi\njle 131a \nmovl $0x2,0x8(,%rax,4)\ncmp $0x2,%edi\nje 131a \nlea -0x3(%rdi),%r8d\nmov $0x3,%eax\nmov $0xaaaaaaab,%r10d\nmov $0xcccccccd,%r9d\nadd $0x4,%r8\nnopw 0x0(%rax,%rax,1)\nmov %eax,%ecx\nmov %eax,%r11d\nmov %eax,(%rsi,%rax,4)\nmov %rcx,%rdx\nsar %r11d\nimul %r9,%rcx\nimul %r10,%rdx\nmovslq %r11d,%r11\nshr $0x22,%rcx\nshr $0x21,%rdx\nmov (%rsi,%rdx,4),%edx\nadd (%rsi,%r11,4),%edx\nmov %eax,%r11d\nsar $0x2,%r11d\nmovslq %r11d,%r11\nadd (%rsi,%r11,4),%edx\nadd (%rsi,%rcx,4),%edx\ncmp %eax,%edx\ncmovle %eax,%edx\nmov %edx,(%rsi,%rax,4)\nadd $0x1,%rax\ncmp %rax,%r8\njne 12d0 \nmovslq %edi,%rdi\nmov (%rsi,%rdi,4),%eax\nmov -0x8(%rbp),%rdi\nxor %fs:0x28,%rdi\njne 1343 \nleaveq\nretq\nnopl 0x0(%rax)\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 127a \ncallq 1060 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmovsxd r11, edi\nlea r8d, [r11+1]\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmovsxd rax, r8d\nmov rcx, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_126A\nloc_1255:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rcx\njnz short loc_1255\nloc_126A:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1320\nloc_127C:\nlea rsi, [rsp+1010h+var_100D]\nmov rdx, cs:qword_2060\nmov r8d, r8d\nmov r10d, 0AAAAAAABh\nmov rax, rsi\nmov r9d, 0CCCCCCCDh\nand rsi, 0FFFFFFFFFFFFFFFCh\nshr rax, 2\nmov qword ptr ds:dword_0[rax*4], rdx\nmov eax, 2\ncmp r11d, 1\njle short loc_12FB\nnop dword ptr [rax]\nloc_12B8:\nmov ecx, eax\nmov edi, eax\nmov [rsi+rax*4], eax\nmov rdx, rcx\nsar edi, 1\nimul rcx, r9\nimul rdx, r10\nmovsxd rdi, edi\nshr rcx, 22h\nshr rdx, 21h\nmov edx, [rsi+rdx*4]\nadd edx, [rsi+rdi*4]\nmov edi, eax\nsar edi, 2\nmovsxd rdi, edi\nadd edx, [rsi+rdi*4]\nadd edx, [rsi+rcx*4]\ncmp edx, eax\njg short loc_1310\nmov [rsi+rax*4], eax\nadd rax, 1\ncmp r8, rax\njnz short loc_12B8\nloc_12FB:\nmov eax, [rsi+r11*4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_132B\nleave\nretn\nloc_1310:\nmov [rsi+rax*4], edx\nadd rax, 1\ncmp r8, rax\njnz short loc_12B8\njmp short loc_12FB\nloc_1320:\nor [rsp+rdx+1010h+var_1018], 0\njmp loc_127C\nloc_132B:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // r8d\n __int64 v2; // rdx\n _QWORD *v3; // rcx\n __int16 v4; // dx\n signed __int64 v5; // rdx\n void *v6; // rsp\n __int64 v7; // rax\n int v8; // edx\n _QWORD v11[511]; // [rsp+8h] [rbp-1010h] BYREF\n _QWORD v12[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v1 = a1 + 1;\n v12[1] = __readfsqword(0x28u);\n v2 = 4LL * (a1 + 1) + 15;\n v3 = (_QWORD *)((char *)v12 - (v2 & 0xFFFFFFFFFFFFF000LL));\n v4 = v2 & 0xFFF0;\n if ( v12 != v3 )\n {\n while ( v11 != v3 )\n ;\n }\n v5 = v4 & 0xFFF;\n v6 = alloca(v5);\n if ( v5 )\n *(_QWORD *)((char *)&v11[-1] + v5) = *(_QWORD *)((char *)&v11[-1] + v5);\n v11[0] = 0x100000000LL;\n v7 = 2LL;\n if ( a1 > 1 )\n {\n do\n {\n while ( 1 )\n {\n *((_DWORD *)v11 + v7) = v7;\n v8 = *((_DWORD *)v11 + (unsigned int)v7 / 5uLL)\n + *((_DWORD *)v11 + ((int)v7 >> 2))\n + *((_DWORD *)v11 + ((int)v7 >> 1))\n + *((_DWORD *)v11 + (unsigned int)v7 / 3uLL);\n if ( v8 > (int)v7 )\n break;\n *((_DWORD *)v11 + v7) = v7;\n if ( v1 == ++v7 )\n return *((unsigned int *)v11 + a1);\n }\n *((_DWORD *)v11 + v7++) = v8;\n }\n while ( v1 != v7 );\n }\n return *((unsigned int *)v11 + a1);\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbp\nmovsxd r11, edi\nlea r8d, [r11+1]\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmovsxd rax, r8d\nmov rcx, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_126A\nloc_1255:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rcx\njnz short loc_1255\nloc_126A:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1320\nloc_127C:\nlea rsi, [rsp+1010h+var_100D]\nmov rdx, cs:qword_2060\nmov r8d, r8d\nmov r10d, 0AAAAAAABh\nmov rax, rsi\nmov r9d, 0CCCCCCCDh\nand rsi, 0FFFFFFFFFFFFFFFCh\nshr rax, 2\nmov qword ptr ds:dword_0[rax*4], rdx\nmov eax, 2\ncmp r11d, 1\njle short loc_12FB\nnop dword ptr [rax]\nloc_12B8:\nmov ecx, eax\nmov edi, eax\nmov [rsi+rax*4], eax\nmov rdx, rcx\nsar edi, 1\nimul rcx, r9\nimul rdx, r10\nmovsxd rdi, edi\nshr rcx, 22h\nshr rdx, 21h\nmov edx, [rsi+rdx*4]\nadd edx, [rsi+rdi*4]\nmov edi, eax\nsar edi, 2\nmovsxd rdi, edi\nadd edx, [rsi+rdi*4]\nadd edx, [rsi+rcx*4]\ncmp edx, eax\njg short loc_1310\nmov [rsi+rax*4], eax\nadd rax, 1\ncmp r8, rax\njnz short loc_12B8\nloc_12FB:\nmov eax, [rsi+r11*4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_132B\nleave\nretn\nloc_1310:\nmov [rsi+rax*4], edx\nadd rax, 1\ncmp r8, rax\njnz short loc_12B8\njmp short loc_12FB\nloc_1320:\nor [rsp+rdx+1010h+var_1018], 0\njmp loc_127C\nloc_132B:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(int a1)\n{\n int v1; // r8d\n __int64 v2; // rdx\n _QWORD *v3; // rcx\n __int16 v4; // dx\n signed __int64 v5; // rdx\n void *v6; // rsp\n __int64 v7; // rax\n int v8; // edx\n _QWORD v11[511]; // [rsp+8h] [rbp-1010h] BYREF\n _QWORD v12[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v1 = a1 + 1;\n v12[1] = __readfsqword(0x28u);\n v2 = 4LL * (a1 + 1) + 15;\n v3 = (_QWORD *)((char *)v12 - (v2 & 0xFFFFFFFFFFFFF000LL));\n v4 = v2 & 0xFFF0;\n if ( v12 != v3 )\n {\n while ( v11 != v3 )\n ;\n }\n v5 = v4 & 0xFFF;\n v6 = alloca(v5);\n if ( v5 )\n *(_QWORD *)((char *)&v11[-1] + v5) = *(_QWORD *)((char *)&v11[-1] + v5);\n v11[0] = 0x100000000LL;\n v7 = 2LL;\n if ( a1 > 1 )\n {\n do\n {\n while ( 1 )\n {\n *((_DWORD *)v11 + v7) = v7;\n v8 = *((_DWORD *)v11 + (unsigned int)v7 / 5uLL)\n + *((_DWORD *)v11 + ((int)v7 >> 2))\n + *((_DWORD *)v11 + ((int)v7 >> 1))\n + *((_DWORD *)v11 + (unsigned int)v7 / 3uLL);\n if ( v8 > (int)v7 )\n break;\n *((_DWORD *)v11 + v7) = v7;\n if ( v1 == ++v7 )\n return *((unsigned int *)v11 + a1);\n }\n *((_DWORD *)v11 + v7++) = v8;\n }\n while ( v1 != v7 );\n }\n return *((unsigned int *)v11 + a1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(int a1) {\n int v1;\n long long v2;\n uint64_t *v3;\n short v4;\n signed long long v5;\n void *v6;\n long long v7;\n int v8;\n uint64_t v11[511];\n uint64_t v12[2];\n v1 = a1 + 1;\n v12[1] = __readfsqword(40u);\n v2 = 4LL * (a1 + 1) + 15;\n v3 = (uint64_t *)((char *)v12 - (v2 & 18446744073709547520LL));\n v4 = v2 & 65520;\n if (v12 != v3) {\n while (v11 != v3)\n ;\n }\n v5 = v4 & 4095;\n v6 = alloca(v5);\n if (v5)\n *(uint64_t *)((char *)&v11[-1] + v5) = *(uint64_t *)((char *)&v11[-1] + v5);\n v11[0] = 4294967296LL;\n v7 = 2LL;\n if (a1 > 1) {\n do {\n while (1) {\n *((uint32_t *)v11 + v7) = v7;\n v8 = *((uint32_t *)v11 + (unsigned int)v7 / 5uLL) +\n *((uint32_t *)v11 + ((int)v7 >> 2)) +\n *((uint32_t *)v11 + ((int)v7 >> 1)) +\n *((uint32_t *)v11 + (unsigned int)v7 / 3uLL);\n if (v8 > (int)v7) break;\n *((uint32_t *)v11 + v7) = v7;\n if (v1 == ++v7) return *((unsigned int *)v11 + a1);\n }\n *((uint32_t *)v11 + v7++) = v8;\n } while (v1 != v7);\n }\n return *((unsigned int *)v11 + a1);\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n long long v2;\n uint64_t *v3;\n short v4;\n signed long long v5;\n void *v6;\n long long v7;\n int v8;\n uint64_t v11[511];\n uint64_t v12[2];\n v1 = a1 + 1;\n v12[1] = __readfsqword(40u);\n v2 = 4LL * (a1 + 1) + 15;\n v3 = (uint64_t *)((char *)v12 - (v2 & 18446744073709547520LL));\n v4 = v2 & 65520;\n if (v12 != v3) {\n while (v11 != v3)\n ;\n }\n v5 = v4 & 4095;\n v6 = alloca(v5);\n if (v5)\n *(uint64_t *)((char *)&v11[-1] + v5) = *(uint64_t *)((char *)&v11[-1] + v5);\n v11[0] = 4294967296LL;\n v7 = 2LL;\n if (a1 > 1) {\n do {\n while (1) {\n *((uint32_t *)v11 + v7) = v7;\n v8 = *((uint32_t *)v11 + (unsigned int)v7 / 5uLL) +\n *((uint32_t *)v11 + ((int)v7 >> 2)) +\n *((uint32_t *)v11 + ((int)v7 >> 1)) +\n *((uint32_t *)v11 + (unsigned int)v7 / 3uLL);\n if (v8 > (int)v7) break;\n *((uint32_t *)v11 + v7) = v7;\n if (v1 == ++v7) return *((unsigned int *)v11 + a1);\n }\n *((uint32_t *)v11 + v7++) = v8;\n } while (v1 != v7);\n }\n return *((unsigned int *)v11 + a1);\n}" + }, + { + "index": 393, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int length;\n\n int *list;\n\n} MaxLengthListResult;\n\n\n\n", + "func": "MaxLengthListResult func0(int **input_list, int list_size, int *sublist_sizes) {\n int max_length = 0;\n int *max_list = NULL;\n for (int i = 0; i < list_size; i++) {\n if (sublist_sizes[i] > max_length) {\n max_length = sublist_sizes[i];\n max_list = input_list[i];\n }\n }\n MaxLengthListResult result = {max_length, max_list};\n return result;\n}", + "test": "int main() {\n\n int list1[] = {0};\n\n int list2[] = {1, 3};\n\n int list3[] = {5, 7};\n\n int list4[] = {9, 11};\n\n int list5[] = {13, 15, 17};\n\n \n\n int *input1[] = {list1, list2, list3, list4, list5};\n\n int sizes1[] = {1, 2, 2, 2, 3};\n\n MaxLengthListResult result1 = func0(input1, 5, sizes1);\n\n assert(result1.length == 3 && result1.list[0] == 13 && result1.list[1] == 15 && result1.list[2] == 17);\n\n\n\n int list6[] = {1, 2, 3, 4, 5};\n\n int list7[] = {1, 2, 3, 4};\n\n int list8[] = {1, 2, 3};\n\n int list9[] = {1, 2};\n\n int list10[] = {1};\n\n \n\n int *input2[] = {list6, list7, list8, list9, list10};\n\n int sizes2[] = {5, 4, 3, 2, 1};\n\n MaxLengthListResult result2 = func0(input2, 5, sizes2);\n\n assert(result2.length == 5 && result2.list[0] == 1 && result2.list[1] == 2 && result2.list[2] == 3 && result2.list[3] == 4 && result2.list[4] == 5);\n\n\n\n int list11[] = {3, 4, 5};\n\n int list12[] = {6, 7, 8, 9};\n\n int list13[] = {10, 11, 12};\n\n \n\n int *input3[] = {list11, list12, list13};\n\n int sizes3[] = {3, 4, 3};\n\n MaxLengthListResult result3 = func0(input3, 3, sizes3);\n\n assert(result3.length == 4 && result3.list[0] == 6 && result3.list[1] == 7 && result3.list[2] == 8 && result3.list[3] == 9);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nmov %rdi,-0x30(%rbp)\nmov %esi,-0x34(%rbp)\nmov %rdx,-0x40(%rbp)\nmovl $0x0,-0x28(%rbp)\nmovq $0x0,-0x20(%rbp)\nmovl $0x0,-0x24(%rbp)\njmp 11e8 \nmov -0x24(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x40(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x28(%rbp)\njge 11e4 \nmov -0x24(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x40(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x28(%rbp)\nmov -0x24(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x30(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov %rax,-0x20(%rbp)\naddl $0x1,-0x24(%rbp)\nmov -0x24(%rbp),%eax\ncmp -0x34(%rbp),%eax\njl 1195 \nmov -0x28(%rbp),%eax\nmov %eax,-0x18(%rbp)\nmov -0x20(%rbp),%rax\nmov %rax,-0x10(%rbp)\nmov -0x18(%rbp),%rax\nmov -0x10(%rbp),%rdx\nmov %rax,%rcx\nmov %rdx,%rbx\nmov %ecx,%eax\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov [rbp+var_48], rdx\nmov [rbp+var_30], 0\nmov [rbp+var_28], 0\nmov [rbp+var_2C], 0\njmp short loc_11E8\nloc_1195:\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_30], eax\njge short loc_11E4\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_30], eax\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nmov [rbp+var_28], rax\nloc_11E4:\nadd [rbp+var_2C], 1\nloc_11E8:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_3C]\njl short loc_1195\nmov eax, [rbp+var_30]\nmov dword ptr [rbp+var_20], eax\nmov rax, [rbp+var_28]\nmov [rbp+var_18], rax\nmov rax, [rbp+var_20]\nmov rdx, [rbp+var_18]\nmov rsi, rax\nmov rdi, rdx\nmov rcx, rax\nmov rbx, rdx\nmov eax, esi\nmov rdx, rbx\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3)\n{\n unsigned int v4; // [rsp+18h] [rbp-30h]\n int i; // [rsp+1Ch] [rbp-2Ch]\n\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( (signed int)v4 < *(_DWORD *)(4LL * i + a3) )\n v4 = *(_DWORD *)(4LL * i + a3);\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov [rbp+var_48], rdx\nmov [rbp+var_30], 0\nmov [rbp+var_28], 0\nmov [rbp+var_2C], 0\njmp short loc_11E8\nloc_1195:\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_30], eax\njge short loc_11E4\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_30], eax\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nmov [rbp+var_28], rax\nloc_11E4:\nadd [rbp+var_2C], 1\nloc_11E8:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_3C]\njl short loc_1195\nmov eax, [rbp+var_30]\nmov dword ptr [rbp+var_20], eax\nmov rax, [rbp+var_28]\nmov [rbp+var_18], rax\nmov rax, [rbp+var_20]\nmov rdx, [rbp+var_18]\nmov rsi, rax\nmov rdi, rdx\nmov rcx, rax\nmov rbx, rdx\nmov eax, esi\nmov rdx, rbx\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, __int64 a3)\n{\n unsigned int v4; // [rsp+18h] [rbp-30h]\n int i; // [rsp+1Ch] [rbp-2Ch]\n\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( (signed int)v4 < *(_DWORD *)(4LL * i + a3) )\n v4 = *(_DWORD *)(4LL * i + a3);\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, long long a3) {\n unsigned int v4;\n int i;\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n if ((signed int)v4 < *(uint32_t *)(4LL * i + a3))\n v4 = *(uint32_t *)(4LL * i + a3);\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3) {\n unsigned int v4;\n int i;\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n if ((signed int)v4 < *(uint32_t *)(4LL * i + a3))\n v4 = *(uint32_t *)(4LL * i + a3);\n }\n return v4;\n}" + }, + { + "index": 393, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int length;\n\n int *list;\n\n} MaxLengthListResult;\n\n\n\n", + "func": "MaxLengthListResult func0(int **input_list, int list_size, int *sublist_sizes) {\n int max_length = 0;\n int *max_list = NULL;\n for (int i = 0; i < list_size; i++) {\n if (sublist_sizes[i] > max_length) {\n max_length = sublist_sizes[i];\n max_list = input_list[i];\n }\n }\n MaxLengthListResult result = {max_length, max_list};\n return result;\n}", + "test": "int main() {\n\n int list1[] = {0};\n\n int list2[] = {1, 3};\n\n int list3[] = {5, 7};\n\n int list4[] = {9, 11};\n\n int list5[] = {13, 15, 17};\n\n \n\n int *input1[] = {list1, list2, list3, list4, list5};\n\n int sizes1[] = {1, 2, 2, 2, 3};\n\n MaxLengthListResult result1 = func0(input1, 5, sizes1);\n\n assert(result1.length == 3 && result1.list[0] == 13 && result1.list[1] == 15 && result1.list[2] == 17);\n\n\n\n int list6[] = {1, 2, 3, 4, 5};\n\n int list7[] = {1, 2, 3, 4};\n\n int list8[] = {1, 2, 3};\n\n int list9[] = {1, 2};\n\n int list10[] = {1};\n\n \n\n int *input2[] = {list6, list7, list8, list9, list10};\n\n int sizes2[] = {5, 4, 3, 2, 1};\n\n MaxLengthListResult result2 = func0(input2, 5, sizes2);\n\n assert(result2.length == 5 && result2.list[0] == 1 && result2.list[1] == 2 && result2.list[2] == 3 && result2.list[3] == 4 && result2.list[4] == 5);\n\n\n\n int list11[] = {3, 4, 5};\n\n int list12[] = {6, 7, 8, 9};\n\n int list13[] = {10, 11, 12};\n\n \n\n int *input3[] = {list11, list12, list13};\n\n int sizes3[] = {3, 4, 3};\n\n MaxLengthListResult result3 = func0(input3, 3, sizes3);\n\n assert(result3.length == 4 && result3.list[0] == 6 && result3.list[1] == 7 && result3.list[2] == 8 && result3.list[3] == 9);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11a2 \nlea -0x1(%rsi),%r8d\nmov $0x0,%ecx\nmov $0x0,%r9d\nmov $0x0,%eax\njmp 1193 \nlea 0x1(%rcx),%rsi\ncmp %r8,%rcx\nje 11ad \nmov %rsi,%rcx\nmov (%rdx,%rcx,4),%esi\ncmp %eax,%esi\njle 1187 \nmov (%rdi,%rcx,8),%r9\nmov %esi,%eax\njmp 1187 \nmov $0x0,%r9d\nmov $0x0,%eax\nmov %eax,%eax\nmov %r9,%rdx\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11A1\nmovsxd rsi, esi\nmov ecx, 0\nmov r9d, 0\nmov eax, 0\njmp short loc_118F\nloc_1186:\nadd rcx, 1\ncmp rcx, rsi\njz short loc_11AC\nloc_118F:\nmov r8d, [rdx+rcx*4]\ncmp r8d, eax\njle short loc_1186\nmov r9, [rdi+rcx*8]\nmov eax, r8d\njmp short loc_1186\nloc_11A1:\nmov r9d, 0\nmov eax, 0\nloc_11AC:\nmov rdx, r9\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3)\n{\n __int64 v3; // rcx\n __int64 result; // rax\n int v5; // r8d\n\n if ( a2 <= 0 )\n return 0LL;\n v3 = 0LL;\n result = 0LL;\n do\n {\n v5 = *(_DWORD *)(a3 + 4 * v3);\n if ( v5 > (int)result )\n result = (unsigned int)v5;\n ++v3;\n }\n while ( v3 != a2 );\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11A1\nmovsxd rsi, esi\nmov ecx, 0\nmov r9d, 0\nmov eax, 0\njmp short loc_118F\nloc_1186:\nadd rcx, 1\ncmp rcx, rsi\njz short loc_11AC\nloc_118F:\nmov r8d, [rdx+rcx*4]\ncmp r8d, eax\njle short loc_1186\nmov r9, [rdi+rcx*8]\nmov eax, r8d\njmp short loc_1186\nloc_11A1:\nmov r9d, 0\nmov eax, 0\nloc_11AC:\nmov rdx, r9\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, __int64 a3)\n{\n __int64 v3; // rcx\n __int64 result; // rax\n int v5; // r8d\n\n if ( a2 <= 0 )\n return 0LL;\n v3 = 0LL;\n result = 0LL;\n do\n {\n v5 = *(_DWORD *)(a3 + 4 * v3);\n if ( v5 > (int)result )\n result = (unsigned int)v5;\n ++v3;\n }\n while ( v3 != a2 );\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, long long a3) {\n long long v3;\n long long result;\n int v5;\n if (a2 <= 0) return 0LL;\n v3 = 0LL;\n result = 0LL;\n do {\n v5 = *(uint32_t *)(a3 + 4 * v3);\n if (v5 > (int)result) result = (unsigned int)v5;\n ++v3;\n } while (v3 != a2);\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3) {\n long long v3;\n long long result;\n int v5;\n if (a2 <= 0) return 0LL;\n v3 = 0LL;\n result = 0LL;\n do {\n v5 = *(uint32_t *)(a3 + 4 * v3);\n if (v5 > (int)result) result = (unsigned int)v5;\n ++v3;\n } while (v3 != a2);\n return result;\n}" + }, + { + "index": 393, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int length;\n\n int *list;\n\n} MaxLengthListResult;\n\n\n\n", + "func": "MaxLengthListResult func0(int **input_list, int list_size, int *sublist_sizes) {\n int max_length = 0;\n int *max_list = NULL;\n for (int i = 0; i < list_size; i++) {\n if (sublist_sizes[i] > max_length) {\n max_length = sublist_sizes[i];\n max_list = input_list[i];\n }\n }\n MaxLengthListResult result = {max_length, max_list};\n return result;\n}", + "test": "int main() {\n\n int list1[] = {0};\n\n int list2[] = {1, 3};\n\n int list3[] = {5, 7};\n\n int list4[] = {9, 11};\n\n int list5[] = {13, 15, 17};\n\n \n\n int *input1[] = {list1, list2, list3, list4, list5};\n\n int sizes1[] = {1, 2, 2, 2, 3};\n\n MaxLengthListResult result1 = func0(input1, 5, sizes1);\n\n assert(result1.length == 3 && result1.list[0] == 13 && result1.list[1] == 15 && result1.list[2] == 17);\n\n\n\n int list6[] = {1, 2, 3, 4, 5};\n\n int list7[] = {1, 2, 3, 4};\n\n int list8[] = {1, 2, 3};\n\n int list9[] = {1, 2};\n\n int list10[] = {1};\n\n \n\n int *input2[] = {list6, list7, list8, list9, list10};\n\n int sizes2[] = {5, 4, 3, 2, 1};\n\n MaxLengthListResult result2 = func0(input2, 5, sizes2);\n\n assert(result2.length == 5 && result2.list[0] == 1 && result2.list[1] == 2 && result2.list[2] == 3 && result2.list[3] == 4 && result2.list[4] == 5);\n\n\n\n int list11[] = {3, 4, 5};\n\n int list12[] = {6, 7, 8, 9};\n\n int list13[] = {10, 11, 12};\n\n \n\n int *input3[] = {list11, list12, list13};\n\n int sizes3[] = {3, 4, 3};\n\n MaxLengthListResult result3 = func0(input3, 3, sizes3);\n\n assert(result3.length == 4 && result3.list[0] == 6 && result3.list[1] == 7 && result3.list[2] == 8 && result3.list[3] == 9);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1178 \nlea -0x1(%rsi),%r8d\nxor %ecx,%ecx\nxor %r9d,%r9d\nxor %eax,%eax\njmp 115b \nnopl (%rax)\nmov %rsi,%rcx\nmov (%rdx,%rcx,4),%esi\ncmp %eax,%esi\njle 1168 \nmov (%rdi,%rcx,8),%r9\nmov %esi,%eax\nlea 0x1(%rcx),%rsi\ncmp %r8,%rcx\njne 1158 \nmov %r9,%rdx\nretq\nnopl (%rax)\nxor %r9d,%r9d\nxor %eax,%eax\nmov %r9,%rdx\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_14E8\nmovsxd rsi, esi\nxor ecx, ecx\nxor r9d, r9d\nxor eax, eax\nnop word ptr [rax+rax+00h]\nloc_14C8:\nmov r8d, [rdx+rcx*4]\ncmp r8d, eax\njle short loc_14D8\nmov r9, [rdi+rcx*8]\nmov eax, r8d\nloc_14D8:\nadd rcx, 1\ncmp rcx, rsi\njnz short loc_14C8\nmov rdx, r9\nretn\nloc_14E8:\nxor r9d, r9d\nxor eax, eax\nmov rdx, r9\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3)\n{\n __int64 v3; // rcx\n __int64 result; // rax\n int v5; // r8d\n\n if ( a2 <= 0 )\n return 0LL;\n v3 = 0LL;\n result = 0LL;\n do\n {\n v5 = *(_DWORD *)(a3 + 4 * v3);\n if ( v5 > (int)result )\n result = (unsigned int)v5;\n ++v3;\n }\n while ( v3 != a2 );\n return result;\n}", + "ida_strip_asm": "sub_14B0:\nendbr64\ntest esi, esi\njle short loc_14E8\nmovsxd rsi, esi\nxor ecx, ecx\nxor r9d, r9d\nxor eax, eax\nnop word ptr [rax+rax+00h]\nloc_14C8:\nmov r8d, [rdx+rcx*4]\ncmp r8d, eax\njle short loc_14D8\nmov r9, [rdi+rcx*8]\nmov eax, r8d\nloc_14D8:\nadd rcx, 1\ncmp rcx, rsi\njnz short loc_14C8\nmov rdx, r9\nretn\nloc_14E8:\nxor r9d, r9d\nxor eax, eax\nmov rdx, r9\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_14B0(__int64 a1, int a2, __int64 a3)\n{\n __int64 v3; // rcx\n __int64 result; // rax\n int v5; // r8d\n\n if ( a2 <= 0 )\n return 0LL;\n v3 = 0LL;\n result = 0LL;\n do\n {\n v5 = *(_DWORD *)(a3 + 4 * v3);\n if ( v5 > (int)result )\n result = (unsigned int)v5;\n ++v3;\n }\n while ( v3 != a2 );\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_14B0(long long a1, int a2, long long a3) {\n long long v3;\n long long result;\n int v5;\n if (a2 <= 0) return 0LL;\n v3 = 0LL;\n result = 0LL;\n do {\n v5 = *(uint32_t *)(a3 + 4 * v3);\n if (v5 > (int)result) result = (unsigned int)v5;\n ++v3;\n } while (v3 != a2);\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3) {\n long long v3;\n long long result;\n int v5;\n if (a2 <= 0) return 0LL;\n v3 = 0LL;\n result = 0LL;\n do {\n v5 = *(uint32_t *)(a3 + 4 * v3);\n if (v5 > (int)result) result = (unsigned int)v5;\n ++v3;\n } while (v3 != a2);\n return result;\n}" + }, + { + "index": 394, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int test_tup[], int size) {\n bool res = true;\n int temp[size];\n int temp_size = 0;\n for (int i = 0; i < size; i++) {\n int ele = test_tup[i];\n bool found = false;\n for (int j = 0; j < temp_size; j++) {\n if (temp[j] == ele) {\n found = true;\n break;\n }\n }\n if (found) {\n res = false;\n break;\n }\n temp[temp_size++] = ele;\n }\n return res;\n}", + "test": "int main() {\n\n int test1[] = {1, 4, 5, 6, 1, 4};\n\n int test2[] = {1, 4, 5, 6};\n\n int test3[] = {2, 3, 4, 5, 6};\n\n \n\n assert(func0(test1, sizeof(test1)/sizeof(test1[0])) == false);\n\n assert(func0(test2, sizeof(test2)/sizeof(test2[0])) == true);\n\n assert(func0(test3, sizeof(test3)/sizeof(test3[0])) == true);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x48,%rsp\nmov %rdi,-0x48(%rbp)\nmov %esi,-0x4c(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmov %rsp,%rax\nmov %rax,%rsi\nmovb $0x1,-0x39(%rbp)\nmov -0x4c(%rbp),%eax\nmovslq %eax,%rdx\nsub $0x1,%rdx\nmov %rdx,-0x28(%rbp)\nmovslq %eax,%rdx\nmov %rdx,%r8\nmov $0x0,%r9d\nmovslq %eax,%rdx\nmov %rdx,%rcx\nmov $0x0,%ebx\ncltq\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%edi\nmov $0x0,%edx\ndiv %rdi\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rbx\nsub %rdx,%rbx\nmov %rbx,%rdx\ncmp %rdx,%rsp\nje 120c \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11f5 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 1236 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x20(%rbp)\nmovl $0x0,-0x30(%rbp)\nmovl $0x0,-0x34(%rbp)\njmp 12c8 \nmov -0x34(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x2c(%rbp)\nmovb $0x0,-0x3a(%rbp)\nmovl $0x0,-0x38(%rbp)\njmp 129b \nmov -0x20(%rbp),%rax\nmov -0x38(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\ncmp %eax,-0x2c(%rbp)\njne 1297 \nmovb $0x1,-0x3a(%rbp)\njmp 12a3 \naddl $0x1,-0x38(%rbp)\nmov -0x38(%rbp),%eax\ncmp -0x30(%rbp),%eax\njl 127f \ncmpb $0x0,-0x3a(%rbp)\nje 12af \nmovb $0x0,-0x39(%rbp)\njmp 12d0 \nmov -0x30(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x30(%rbp)\nmov -0x20(%rbp),%rdx\ncltq\nmov -0x2c(%rbp),%ecx\nmov %ecx,(%rdx,%rax,4)\naddl $0x1,-0x34(%rbp)\nmov -0x34(%rbp),%eax\ncmp -0x4c(%rbp),%eax\njl 1259 \nmovzbl -0x39(%rbp),%eax\nmov %rsi,%rsp\nmov -0x18(%rbp),%rdi\nxor %fs:0x28,%rdi\nje 12eb \ncallq 1060 <__stack_chk_fail@plt>\nmov -0x8(%rbp),%rbx\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov [rbp+var_2A], 1\nmov eax, [rbp+var_3C]\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11DA:\ncmp rsp, rdx\njz short loc_11F1\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_11DA\nloc_11F1:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_121B\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_121B:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov [rbp+var_28], 0\nmov [rbp+var_24], 0\njmp short loc_12AD\nloc_123E:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_1C], eax\nmov [rbp+var_29], 0\nmov [rbp+var_20], 0\njmp short loc_1280\nloc_1264:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ncmp [rbp+var_1C], eax\njnz short loc_127C\nmov [rbp+var_29], 1\njmp short loc_1288\nloc_127C:\nadd [rbp+var_20], 1\nloc_1280:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_28]\njl short loc_1264\nloc_1288:\ncmp [rbp+var_29], 0\njz short loc_1294\nmov [rbp+var_2A], 0\njmp short loc_12B5\nloc_1294:\nmov eax, [rbp+var_28]\nlea edx, [rax+1]\nmov [rbp+var_28], edx\nmov rdx, [rbp+var_10]\ncdqe\nmov ecx, [rbp+var_1C]\nmov [rdx+rax*4], ecx\nadd [rbp+var_24], 1\nloc_12AD:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_3C]\njl short loc_123E\nloc_12B5:\nmovzx eax, [rbp+var_2A]\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12D0\ncall ___stack_chk_fail\nlocret_12D0:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned __int64 v2; // rax\n void *v3; // rsp\n int v4; // eax\n _BYTE v6[4]; // [rsp+8h] [rbp-40h] BYREF\n int v7; // [rsp+Ch] [rbp-3Ch]\n __int64 v8; // [rsp+10h] [rbp-38h]\n unsigned __int8 v9; // [rsp+1Eh] [rbp-2Ah]\n char v10; // [rsp+1Fh] [rbp-29h]\n int v11; // [rsp+20h] [rbp-28h]\n int i; // [rsp+24h] [rbp-24h]\n int j; // [rsp+28h] [rbp-20h]\n int v14; // [rsp+2Ch] [rbp-1Ch]\n __int64 v15; // [rsp+30h] [rbp-18h]\n _BYTE *v16; // [rsp+38h] [rbp-10h]\n unsigned __int64 v17; // [rsp+40h] [rbp-8h]\n\n v8 = a1;\n v7 = a2;\n v17 = __readfsqword(0x28u);\n v9 = 1;\n v15 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 0x10uLL);\n while ( v6 != &v6[-(v2 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = alloca(v2 & 0xFFF);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)&v6[(v2 & 0xFFF) - 8] = *(_QWORD *)&v6[(v2 & 0xFFF) - 8];\n v16 = v6;\n v11 = 0;\n for ( i = 0; i < v7; ++i )\n {\n v14 = *(_DWORD *)(4LL * i + v8);\n v10 = 0;\n for ( j = 0; j < v11; ++j )\n {\n if ( v14 == *(_DWORD *)&v16[4 * j] )\n {\n v10 = 1;\n break;\n }\n }\n if ( v10 )\n return 0;\n v4 = v11++;\n *(_DWORD *)&v16[4 * v4] = v14;\n }\n return v9;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov [rbp+var_2A], 1\nmov eax, [rbp+var_3C]\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11DA:\ncmp rsp, rdx\njz short loc_11F1\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_11DA\nloc_11F1:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_121B\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_121B:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov [rbp+var_28], 0\nmov [rbp+var_24], 0\njmp short loc_12AD\nloc_123E:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_1C], eax\nmov [rbp+var_29], 0\nmov [rbp+var_20], 0\njmp short loc_1280\nloc_1264:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ncmp [rbp+var_1C], eax\njnz short loc_127C\nmov [rbp+var_29], 1\njmp short loc_1288\nloc_127C:\nadd [rbp+var_20], 1\nloc_1280:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_28]\njl short loc_1264\nloc_1288:\ncmp [rbp+var_29], 0\njz short loc_1294\nmov [rbp+var_2A], 0\njmp short loc_12B5\nloc_1294:\nmov eax, [rbp+var_28]\nlea edx, [rax+1]\nmov [rbp+var_28], edx\nmov rdx, [rbp+var_10]\ncdqe\nmov ecx, [rbp+var_1C]\nmov [rdx+rax*4], ecx\nadd [rbp+var_24], 1\nloc_12AD:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_3C]\njl short loc_123E\nloc_12B5:\nmovzx eax, [rbp+var_2A]\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12D0\ncall ___stack_chk_fail\nlocret_12D0:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned __int64 v2; // rax\n void *v3; // rsp\n int v4; // eax\n _BYTE v6[4]; // [rsp+8h] [rbp-40h] BYREF\n int v7; // [rsp+Ch] [rbp-3Ch]\n __int64 v8; // [rsp+10h] [rbp-38h]\n unsigned __int8 v9; // [rsp+1Eh] [rbp-2Ah]\n char v10; // [rsp+1Fh] [rbp-29h]\n int v11; // [rsp+20h] [rbp-28h]\n int i; // [rsp+24h] [rbp-24h]\n int j; // [rsp+28h] [rbp-20h]\n int v14; // [rsp+2Ch] [rbp-1Ch]\n __int64 v15; // [rsp+30h] [rbp-18h]\n _BYTE *v16; // [rsp+38h] [rbp-10h]\n unsigned __int64 v17; // [rsp+40h] [rbp-8h]\n\n v8 = a1;\n v7 = a2;\n v17 = __readfsqword(0x28u);\n v9 = 1;\n v15 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 0x10uLL);\n while ( v6 != &v6[-(v2 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = alloca(v2 & 0xFFF);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)&v6[(v2 & 0xFFF) - 8] = *(_QWORD *)&v6[(v2 & 0xFFF) - 8];\n v16 = v6;\n v11 = 0;\n for ( i = 0; i < v7; ++i )\n {\n v14 = *(_DWORD *)(4LL * i + v8);\n v10 = 0;\n for ( j = 0; j < v11; ++j )\n {\n if ( v14 == *(_DWORD *)&v16[4 * j] )\n {\n v10 = 1;\n break;\n }\n }\n if ( v10 )\n return 0;\n v4 = v11++;\n *(_DWORD *)&v16[4 * v4] = v14;\n }\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n unsigned long long v2;\n void *v3;\n int v4;\n uint8_t v6[4];\n int v7;\n long long v8;\n unsigned char v9;\n char v10;\n int v11;\n int i;\n int j;\n int v14;\n long long v15;\n uint8_t *v16;\n unsigned long long v17;\n v8 = a1;\n v7 = a2;\n v17 = __readfsqword(40u);\n v9 = 1;\n v15 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 16uLL);\n while (v6 != &v6[-(v2 & 18446744073709547520LL)])\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)&v6[(v2 & 4095) - 8] = *(uint64_t *)&v6[(v2 & 4095) - 8];\n v16 = v6;\n v11 = 0;\n for (i = 0; i < v7; ++i) {\n v14 = *(uint32_t *)(4LL * i + v8);\n v10 = 0;\n for (j = 0; j < v11; ++j) {\n if (v14 == *(uint32_t *)&v16[4 * j]) {\n v10 = 1;\n break;\n }\n }\n if (v10) return 0;\n v4 = v11++;\n *(uint32_t *)&v16[4 * v4] = v14;\n }\n return v9;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned long long v2;\n void *v3;\n int v4;\n uint8_t v6[4];\n int v7;\n long long v8;\n unsigned char v9;\n char v10;\n int v11;\n int i;\n int j;\n int v14;\n long long v15;\n uint8_t *v16;\n unsigned long long v17;\n v8 = a1;\n v7 = a2;\n v17 = __readfsqword(40u);\n v9 = 1;\n v15 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 16uLL);\n while (v6 != &v6[-(v2 & 18446744073709547520LL)])\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)&v6[(v2 & 4095) - 8] = *(uint64_t *)&v6[(v2 & 4095) - 8];\n v16 = v6;\n v11 = 0;\n for (i = 0; i < v7; ++i) {\n v14 = *(uint32_t *)(4LL * i + v8);\n v10 = 0;\n for (j = 0; j < v11; ++j) {\n if (v14 == *(uint32_t *)&v16[4 * j]) {\n v10 = 1;\n break;\n }\n }\n if (v10) return 0;\n v4 = v11++;\n *(uint32_t *)&v16[4 * v4] = v14;\n }\n return v9;\n}" + }, + { + "index": 394, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int test_tup[], int size) {\n bool res = true;\n int temp[size];\n int temp_size = 0;\n for (int i = 0; i < size; i++) {\n int ele = test_tup[i];\n bool found = false;\n for (int j = 0; j < temp_size; j++) {\n if (temp[j] == ele) {\n found = true;\n break;\n }\n }\n if (found) {\n res = false;\n break;\n }\n temp[temp_size++] = ele;\n }\n return res;\n}", + "test": "int main() {\n\n int test1[] = {1, 4, 5, 6, 1, 4};\n\n int test2[] = {1, 4, 5, 6};\n\n int test3[] = {2, 3, 4, 5, 6};\n\n \n\n assert(func0(test1, sizeof(test1)/sizeof(test1[0])) == false);\n\n assert(func0(test2, sizeof(test2)/sizeof(test2[0])) == true);\n\n assert(func0(test3, sizeof(test3)/sizeof(test3[0])) == true);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %esi,%r8d\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovslq %esi,%rax\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffffff0,%rdx\nand $0xfffffffffffff000,%rax\nmov %rsp,%rsi\nsub %rax,%rsi\nmov %rsi,%rax\ncmp %rax,%rsp\nje 11bf \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11a8 \nmov %rdx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 11d5 \norq $0x0,-0x8(%rsp,%rax,1)\nmov %rsp,%rcx\nmov $0x1,%eax\ntest %r8d,%r8d\njle 1224 \nmov (%rdi),%edx\nadd $0x4,%rdi\nmov %rcx,%r9\nadd $0x4,%rcx\nmov $0x1,%esi\nmov %edx,-0x4(%rcx)\ncmp %r8d,%esi\nje 1235 \nmov (%rdi),%edx\ntest %esi,%esi\njle 1212 \nmov %r9,%rax\ncmp %edx,(%rax)\nje 121f \nadd $0x4,%rax\ncmp %rcx,%rax\njne 1205 \nadd $0x1,%esi\nadd $0x4,%rdi\nadd $0x4,%rcx\njmp 11f4 \nmov $0x0,%eax\nmov -0x8(%rbp),%rdi\nxor %fs:0x28,%rdi\njne 123c \nleaveq\nretq\nmov $0x1,%eax\njmp 1224 \ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmovsxd r8, esi\nlea rax, ds:0Fh[r8*4]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11A2:\ncmp rsp, rdx\njz short loc_11B9\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11A2\nloc_11B9:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11CF\nor [rsp+rax+10h+var_18], 0\nloc_11CF:\nmov r9, rsp\ntest esi, esi\njle short loc_120F\nmov rdx, r9\nmov esi, 0\njmp short loc_11EF\nloc_11E0:\nmov [rdx], ecx\nadd rsi, 1\nadd rdx, 4\ncmp r8, rsi\njz short loc_1208\nloc_11EF:\nmov ecx, [rdi+rsi*4]\ntest esi, esi\njle short loc_11E0\nmov rax, r9\nloc_11F9:\ncmp [rax], ecx\njz short loc_1216\nadd rax, 4\ncmp rax, rdx\njnz short loc_11F9\njmp short loc_11E0\nloc_1208:\nmov eax, 1\njmp short loc_121B\nloc_120F:\nmov eax, 1\njmp short loc_121B\nloc_1216:\nmov eax, 0\nloc_121B:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_122C\nleave\nretn\nloc_122C:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // r8\n signed __int64 v3; // rax\n void *v4; // rsp\n _DWORD *v5; // rdx\n __int64 v6; // rsi\n int v7; // ecx\n _DWORD *v8; // rax\n _QWORD v11[2]; // [rsp+8h] [rbp-10h] BYREF\n\n v11[1] = __readfsqword(0x28u);\n v2 = a2;\n while ( v11 != (_QWORD *)((char *)v11 - ((4LL * a2 + 15) & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v3 = (4 * (_WORD)a2 + 15) & 0xFF0;\n v4 = alloca(v3);\n if ( ((4 * (_WORD)a2 + 15) & 0xFF0) != 0 )\n *(_QWORD *)((char *)&v11[-1] + v3) = *(_QWORD *)((char *)&v11[-1] + v3);\n if ( a2 <= 0 )\n return 1LL;\n v5 = v11;\n v6 = 0LL;\n while ( 1 )\n {\n v7 = *(_DWORD *)(a1 + 4 * v6);\n if ( (int)v6 > 0 )\n break;\nLABEL_7:\n *v5 = v7;\n ++v6;\n ++v5;\n if ( v2 == v6 )\n return 1LL;\n }\n v8 = v11;\n while ( *v8 != v7 )\n {\n if ( ++v8 == v5 )\n goto LABEL_7;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmovsxd r8, esi\nlea rax, ds:0Fh[r8*4]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11A2:\ncmp rsp, rdx\njz short loc_11B9\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11A2\nloc_11B9:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11CF\nor [rsp+rax+10h+var_18], 0\nloc_11CF:\nmov r9, rsp\ntest esi, esi\njle short loc_120F\nmov rdx, r9\nmov esi, 0\njmp short loc_11EF\nloc_11E0:\nmov [rdx], ecx\nadd rsi, 1\nadd rdx, 4\ncmp r8, rsi\njz short loc_1208\nloc_11EF:\nmov ecx, [rdi+rsi*4]\ntest esi, esi\njle short loc_11E0\nmov rax, r9\nloc_11F9:\ncmp [rax], ecx\njz short loc_1216\nadd rax, 4\ncmp rax, rdx\njnz short loc_11F9\njmp short loc_11E0\nloc_1208:\nmov eax, 1\njmp short loc_121B\nloc_120F:\nmov eax, 1\njmp short loc_121B\nloc_1216:\nmov eax, 0\nloc_121B:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_122C\nleave\nretn\nloc_122C:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n __int64 v2; // r8\n signed __int64 v3; // rax\n void *v4; // rsp\n _DWORD *v5; // rdx\n __int64 v6; // rsi\n int v7; // ecx\n _DWORD *v8; // rax\n _QWORD v11[2]; // [rsp+8h] [rbp-10h] BYREF\n\n v11[1] = __readfsqword(0x28u);\n v2 = a2;\n while ( v11 != (_QWORD *)((char *)v11 - ((4LL * a2 + 15) & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v3 = (4 * (_WORD)a2 + 15) & 0xFF0;\n v4 = alloca(v3);\n if ( ((4 * (_WORD)a2 + 15) & 0xFF0) != 0 )\n *(_QWORD *)((char *)&v11[-1] + v3) = *(_QWORD *)((char *)&v11[-1] + v3);\n if ( a2 <= 0 )\n return 1LL;\n v5 = v11;\n v6 = 0LL;\n while ( 1 )\n {\n v7 = *(_DWORD *)(a1 + 4 * v6);\n if ( (int)v6 > 0 )\n break;\nLABEL_7:\n *v5 = v7;\n ++v6;\n ++v5;\n if ( v2 == v6 )\n return 1LL;\n }\n v8 = v11;\n while ( *v8 != v7 )\n {\n if ( ++v8 == v5 )\n goto LABEL_7;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n long long v2;\n signed long long v3;\n void *v4;\n uint32_t *v5;\n long long v6;\n int v7;\n uint32_t *v8;\n uint64_t v11[2];\n v11[1] = __readfsqword(40u);\n v2 = a2;\n while (v11 !=\n (uint64_t *)((char *)v11 - ((4LL * a2 + 15) & 18446744073709547520LL)))\n ;\n v3 = (4 * (unsigned short)a2 + 15) & 4080;\n v4 = alloca(v3);\n if (((4 * (unsigned short)a2 + 15) & 4080) != 0)\n *(uint64_t *)((char *)&v11[-1] + v3) = *(uint64_t *)((char *)&v11[-1] + v3);\n if (a2 <= 0) return 1LL;\n v5 = v11;\n v6 = 0LL;\n while (1) {\n v7 = *(uint32_t *)(a1 + 4 * v6);\n if ((int)v6 > 0) break;\n LABEL_7:\n *v5 = v7;\n ++v6;\n ++v5;\n if (v2 == v6) return 1LL;\n }\n v8 = v11;\n while (*v8 != v7) {\n if (++v8 == v5) goto LABEL_7;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n signed long long v3;\n void *v4;\n uint32_t *v5;\n long long v6;\n int v7;\n uint32_t *v8;\n uint64_t v11[2];\n v11[1] = __readfsqword(40u);\n v2 = a2;\n while (v11 !=\n (uint64_t *)((char *)v11 - ((4LL * a2 + 15) & 18446744073709547520LL)))\n ;\n v3 = (4 * (unsigned short)a2 + 15) & 4080;\n v4 = alloca(v3);\n if (((4 * (unsigned short)a2 + 15) & 4080) != 0)\n *(uint64_t *)((char *)&v11[-1] + v3) = *(uint64_t *)((char *)&v11[-1] + v3);\n if (a2 <= 0) return 1LL;\n v5 = v11;\n v6 = 0LL;\n while (1) {\n v7 = *(uint32_t *)(a1 + 4 * v6);\n if ((int)v6 > 0) break;\n LABEL_7:\n *v5 = v7;\n ++v6;\n ++v5;\n if (v2 == v6) return 1LL;\n }\n v8 = v11;\n while (*v8 != v7) {\n if (++v8 == v5) goto LABEL_7;\n }\n return 0LL;\n}" + }, + { + "index": 394, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int test_tup[], int size) {\n bool res = true;\n int temp[size];\n int temp_size = 0;\n for (int i = 0; i < size; i++) {\n int ele = test_tup[i];\n bool found = false;\n for (int j = 0; j < temp_size; j++) {\n if (temp[j] == ele) {\n found = true;\n break;\n }\n }\n if (found) {\n res = false;\n break;\n }\n temp[temp_size++] = ele;\n }\n return res;\n}", + "test": "int main() {\n\n int test1[] = {1, 4, 5, 6, 1, 4};\n\n int test2[] = {1, 4, 5, 6};\n\n int test3[] = {2, 3, 4, 5, 6};\n\n \n\n assert(func0(test1, sizeof(test1)/sizeof(test1[0])) == false);\n\n assert(func0(test2, sizeof(test2)/sizeof(test2[0])) == true);\n\n assert(func0(test3, sizeof(test3)/sizeof(test3[0])) == true);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovslq %esi,%rax\nmov %rsp,%rcx\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rcx\nand $0xfffffffffffffff0,%rdx\nmov %rcx,%rax\ncmp %rax,%rsp\nje 1396 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 1381 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 140b \nmov %rsp,%r9\ntest %esi,%esi\njle 1404 \nmov (%rdi),%edx\nmov $0x1,%r8d\nlea 0x4(%r9),%rcx\nadd $0x4,%rdi\nmov %edx,-0x4(%rcx)\ncmp %esi,%r8d\nje 1404 \nnopl 0x0(%rax,%rax,1)\nmov (%rdi),%edx\nmov %r9,%rax\njmp 13d9 \nadd $0x4,%rax\ncmp %rcx,%rax\nje 13f0 \ncmp %edx,(%rax)\njne 13d0 \nxor %eax,%eax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\njne 1413 \nleaveq\nretq\nadd $0x1,%r8d\nadd $0x4,%rcx\nadd $0x4,%rdi\nmov %edx,-0x4(%rcx)\ncmp %esi,%r8d\njne 13c8 \nmov $0x1,%eax\njmp 13df \norq $0x0,-0x8(%rsp,%rdx,1)\njmp 13a4 \ncallq 1060 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmovsxd r8, esi\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, ds:0Fh[r8*4]\nmov rcx, rsp\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_12C3\nloc_12AE:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rcx\njnz short loc_12AE\nloc_12C3:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz short loc_1326\nloc_12D1:\nmov r9, rsp\ntest esi, esi\njle short loc_131F\nmov rdx, r9\nxor esi, esi\nnop dword ptr [rax]\nloc_12E0:\nmov ecx, [rdi+rsi*4]\ntest esi, esi\njz short loc_1310\nmov rax, r9\njmp short loc_12F9\nloc_12F0:\nadd rax, 4\ncmp rax, rdx\njz short loc_1310\nloc_12F9:\ncmp [rax], ecx\njnz short loc_12F0\nxor eax, eax\nloc_12FF:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_132E\nleave\nretn\nloc_1310:\nadd rsi, 1\nmov [rdx], ecx\nadd rdx, 4\ncmp r8, rsi\njnz short loc_12E0\nloc_131F:\nmov eax, 1\njmp short loc_12FF\nloc_1326:\nor [rsp+rdx+1010h+var_1018], 0\njmp short loc_12D1\nloc_132E:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // r8\n __int64 v3; // rdx\n _BYTE *v4; // rcx\n __int16 v5; // dx\n signed __int64 v6; // rdx\n void *v7; // rsp\n _DWORD *v8; // rdx\n __int64 v9; // rsi\n int v10; // ecx\n _DWORD *v11; // rax\n _BYTE v14[4088]; // [rsp+8h] [rbp-1010h] BYREF\n _QWORD v15[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v2 = a2;\n v15[1] = __readfsqword(0x28u);\n v3 = 4LL * a2 + 15;\n v4 = (char *)v15 - (v3 & 0xFFFFFFFFFFFFF000LL);\n v5 = v3 & 0xFFF0;\n if ( v15 != (_QWORD *)v4 )\n {\n while ( v14 != v4 )\n ;\n }\n v6 = v5 & 0xFFF;\n v7 = alloca(v6);\n if ( v6 )\n *(_QWORD *)&v14[v6 - 8] = *(_QWORD *)&v14[v6 - 8];\n if ( a2 <= 0 )\n return 1LL;\n v8 = v14;\n v9 = 0LL;\n while ( 1 )\n {\n v10 = *(_DWORD *)(a1 + 4 * v9);\n if ( (_DWORD)v9 )\n break;\nLABEL_12:\n ++v9;\n *v8++ = v10;\n if ( v2 == v9 )\n return 1LL;\n }\n v11 = v14;\n while ( *v11 != v10 )\n {\n if ( ++v11 == v8 )\n goto LABEL_12;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1270:\nendbr64\npush rbp\nmovsxd r8, esi\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, ds:0Fh[r8*4]\nmov rcx, rsp\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_12C3\nloc_12AE:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rcx\njnz short loc_12AE\nloc_12C3:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz short loc_1326\nloc_12D1:\nmov r9, rsp\ntest esi, esi\njle short loc_131F\nmov rdx, r9\nxor esi, esi\nnop dword ptr [rax]\nloc_12E0:\nmov ecx, [rdi+rsi*4]\ntest esi, esi\njz short loc_1310\nmov rax, r9\njmp short loc_12F9\nloc_12F0:\nadd rax, 4\ncmp rax, rdx\njz short loc_1310\nloc_12F9:\ncmp [rax], ecx\njnz short loc_12F0\nxor eax, eax\nloc_12FF:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_132E\nleave\nretn\nloc_1310:\nadd rsi, 1\nmov [rdx], ecx\nadd rdx, 4\ncmp r8, rsi\njnz short loc_12E0\nloc_131F:\nmov eax, 1\njmp short loc_12FF\nloc_1326:\nor [rsp+rdx+1010h+var_1018], 0\njmp short loc_12D1\nloc_132E:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1270(__int64 a1, int a2)\n{\n __int64 v2; // r8\n __int64 v3; // rdx\n _BYTE *v4; // rcx\n __int16 v5; // dx\n signed __int64 v6; // rdx\n void *v7; // rsp\n _DWORD *v8; // rdx\n __int64 v9; // rsi\n int v10; // ecx\n _DWORD *v11; // rax\n _BYTE v14[4088]; // [rsp+8h] [rbp-1010h] BYREF\n _QWORD v15[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v2 = a2;\n v15[1] = __readfsqword(0x28u);\n v3 = 4LL * a2 + 15;\n v4 = (char *)v15 - (v3 & 0xFFFFFFFFFFFFF000LL);\n v5 = v3 & 0xFFF0;\n if ( v15 != (_QWORD *)v4 )\n {\n while ( v14 != v4 )\n ;\n }\n v6 = v5 & 0xFFF;\n v7 = alloca(v6);\n if ( v6 )\n *(_QWORD *)&v14[v6 - 8] = *(_QWORD *)&v14[v6 - 8];\n if ( a2 <= 0 )\n return 1LL;\n v8 = v14;\n v9 = 0LL;\n while ( 1 )\n {\n v10 = *(_DWORD *)(a1 + 4 * v9);\n if ( (_DWORD)v9 )\n break;\nLABEL_12:\n ++v9;\n *v8++ = v10;\n if ( v2 == v9 )\n return 1LL;\n }\n v11 = v14;\n while ( *v11 != v10 )\n {\n if ( ++v11 == v8 )\n goto LABEL_12;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1270(long long a1, int a2) {\n long long v2;\n long long v3;\n uint8_t *v4;\n short v5;\n signed long long v6;\n void *v7;\n uint32_t *v8;\n long long v9;\n int v10;\n uint32_t *v11;\n uint8_t v14[4088];\n uint64_t v15[2];\n v2 = a2;\n v15[1] = __readfsqword(40u);\n v3 = 4LL * a2 + 15;\n v4 = (char *)v15 - (v3 & 18446744073709547520LL);\n v5 = v3 & 65520;\n if (v15 != (uint64_t *)v4) {\n while (v14 != v4)\n ;\n }\n v6 = v5 & 4095;\n v7 = alloca(v6);\n if (v6) *(uint64_t *)&v14[v6 - 8] = *(uint64_t *)&v14[v6 - 8];\n if (a2 <= 0) return 1LL;\n v8 = v14;\n v9 = 0LL;\n while (1) {\n v10 = *(uint32_t *)(a1 + 4 * v9);\n if ((uint32_t)v9) break;\n LABEL_12:\n ++v9;\n *v8++ = v10;\n if (v2 == v9) return 1LL;\n }\n v11 = v14;\n while (*v11 != v10) {\n if (++v11 == v8) goto LABEL_12;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n long long v3;\n uint8_t *v4;\n short v5;\n signed long long v6;\n void *v7;\n uint32_t *v8;\n long long v9;\n int v10;\n uint32_t *v11;\n uint8_t v14[4088];\n uint64_t v15[2];\n v2 = a2;\n v15[1] = __readfsqword(40u);\n v3 = 4LL * a2 + 15;\n v4 = (char *)v15 - (v3 & 18446744073709547520LL);\n v5 = v3 & 65520;\n if (v15 != (uint64_t *)v4) {\n while (v14 != v4)\n ;\n }\n v6 = v5 & 4095;\n v7 = alloca(v6);\n if (v6) *(uint64_t *)&v14[v6 - 8] = *(uint64_t *)&v14[v6 - 8];\n if (a2 <= 0) return 1LL;\n v8 = v14;\n v9 = 0LL;\n while (1) {\n v10 = *(uint32_t *)(a1 + 4 * v9);\n if ((uint32_t)v9) break;\n LABEL_12:\n ++v9;\n *v8++ = v10;\n if (v2 == v9) return 1LL;\n }\n v11 = v14;\n while (*v11 != v10) {\n if (++v11 == v8) goto LABEL_12;\n }\n return 0LL;\n}" + }, + { + "index": 394, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int test_tup[], int size) {\n bool res = true;\n int temp[size];\n int temp_size = 0;\n for (int i = 0; i < size; i++) {\n int ele = test_tup[i];\n bool found = false;\n for (int j = 0; j < temp_size; j++) {\n if (temp[j] == ele) {\n found = true;\n break;\n }\n }\n if (found) {\n res = false;\n break;\n }\n temp[temp_size++] = ele;\n }\n return res;\n}", + "test": "int main() {\n\n int test1[] = {1, 4, 5, 6, 1, 4};\n\n int test2[] = {1, 4, 5, 6};\n\n int test3[] = {2, 3, 4, 5, 6};\n\n \n\n assert(func0(test1, sizeof(test1)/sizeof(test1[0])) == false);\n\n assert(func0(test2, sizeof(test2)/sizeof(test2[0])) == true);\n\n assert(func0(test3, sizeof(test3)/sizeof(test3[0])) == true);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovslq %esi,%rax\nmov %rsp,%rcx\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rcx\nand $0xfffffffffffffff0,%rdx\nmov %rcx,%rax\ncmp %rax,%rsp\nje 1266 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 1251 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 12db \nmov %rsp,%r9\ntest %esi,%esi\njle 12d4 \nmov (%rdi),%edx\nmov $0x1,%r8d\nlea 0x4(%r9),%rcx\nadd $0x4,%rdi\nmov %edx,-0x4(%rcx)\ncmp %esi,%r8d\nje 12d4 \nnopl 0x0(%rax,%rax,1)\nmov (%rdi),%edx\nmov %r9,%rax\njmp 12a9 \nadd $0x4,%rax\ncmp %rcx,%rax\nje 12c0 \ncmp %edx,(%rax)\njne 12a0 \nxor %eax,%eax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\njne 12e3 \nleaveq\nretq\nadd $0x1,%r8d\nadd $0x4,%rcx\nadd $0x4,%rdi\nmov %edx,-0x4(%rcx)\ncmp %esi,%r8d\njne 1298 \nmov $0x1,%eax\njmp 12af \norq $0x0,-0x8(%rsp,%rdx,1)\njmp 1274 \ncallq 1060 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmovsxd r8, esi\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, ds:0Fh[r8*4]\nmov rcx, rsp\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_11B3\nloc_119E:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rcx\njnz short loc_119E\nloc_11B3:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz short loc_1216\nloc_11C1:\nmov r9, rsp\ntest esi, esi\njle short loc_120F\nmov rdx, r9\nxor esi, esi\nnop dword ptr [rax]\nloc_11D0:\nmov ecx, [rdi+rsi*4]\ntest esi, esi\njz short loc_1200\nmov rax, r9\njmp short loc_11E9\nloc_11E0:\nadd rax, 4\ncmp rax, rdx\njz short loc_1200\nloc_11E9:\ncmp [rax], ecx\njnz short loc_11E0\nxor eax, eax\nloc_11EF:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_121E\nleave\nretn\nloc_1200:\nadd rsi, 1\nmov [rdx], ecx\nadd rdx, 4\ncmp r8, rsi\njnz short loc_11D0\nloc_120F:\nmov eax, 1\njmp short loc_11EF\nloc_1216:\nor [rsp+rdx+1010h+var_1018], 0\njmp short loc_11C1\nloc_121E:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // r8\n __int64 v3; // rdx\n _BYTE *v4; // rcx\n __int16 v5; // dx\n signed __int64 v6; // rdx\n void *v7; // rsp\n _DWORD *v8; // rdx\n __int64 v9; // rsi\n int v10; // ecx\n _DWORD *v11; // rax\n _BYTE v14[4088]; // [rsp+8h] [rbp-1010h] BYREF\n _QWORD v15[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v2 = a2;\n v15[1] = __readfsqword(0x28u);\n v3 = 4LL * a2 + 15;\n v4 = (char *)v15 - (v3 & 0xFFFFFFFFFFFFF000LL);\n v5 = v3 & 0xFFF0;\n if ( v15 != (_QWORD *)v4 )\n {\n while ( v14 != v4 )\n ;\n }\n v6 = v5 & 0xFFF;\n v7 = alloca(v6);\n if ( v6 )\n *(_QWORD *)&v14[v6 - 8] = *(_QWORD *)&v14[v6 - 8];\n if ( a2 <= 0 )\n return 1LL;\n v8 = v14;\n v9 = 0LL;\n while ( 1 )\n {\n v10 = *(_DWORD *)(a1 + 4 * v9);\n if ( (_DWORD)v9 )\n break;\nLABEL_12:\n ++v9;\n *v8++ = v10;\n if ( v2 == v9 )\n return 1LL;\n }\n v11 = v14;\n while ( *v11 != v10 )\n {\n if ( ++v11 == v8 )\n goto LABEL_12;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1160:\nendbr64\npush rbp\nmovsxd r8, esi\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, ds:0Fh[r8*4]\nmov rcx, rsp\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_11B3\nloc_119E:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rcx\njnz short loc_119E\nloc_11B3:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz short loc_1216\nloc_11C1:\nmov r9, rsp\ntest esi, esi\njle short loc_120F\nmov rdx, r9\nxor esi, esi\nnop dword ptr [rax]\nloc_11D0:\nmov ecx, [rdi+rsi*4]\ntest esi, esi\njz short loc_1200\nmov rax, r9\njmp short loc_11E9\nloc_11E0:\nadd rax, 4\ncmp rax, rdx\njz short loc_1200\nloc_11E9:\ncmp [rax], ecx\njnz short loc_11E0\nxor eax, eax\nloc_11EF:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_121E\nleave\nretn\nloc_1200:\nadd rsi, 1\nmov [rdx], ecx\nadd rdx, 4\ncmp r8, rsi\njnz short loc_11D0\nloc_120F:\nmov eax, 1\njmp short loc_11EF\nloc_1216:\nor [rsp+rdx+1010h+var_1018], 0\njmp short loc_11C1\nloc_121E:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1160(__int64 a1, int a2)\n{\n __int64 v2; // r8\n __int64 v3; // rdx\n _BYTE *v4; // rcx\n __int16 v5; // dx\n signed __int64 v6; // rdx\n void *v7; // rsp\n _DWORD *v8; // rdx\n __int64 v9; // rsi\n int v10; // ecx\n _DWORD *v11; // rax\n _BYTE v14[4088]; // [rsp+8h] [rbp-1010h] BYREF\n _QWORD v15[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v2 = a2;\n v15[1] = __readfsqword(0x28u);\n v3 = 4LL * a2 + 15;\n v4 = (char *)v15 - (v3 & 0xFFFFFFFFFFFFF000LL);\n v5 = v3 & 0xFFF0;\n if ( v15 != (_QWORD *)v4 )\n {\n while ( v14 != v4 )\n ;\n }\n v6 = v5 & 0xFFF;\n v7 = alloca(v6);\n if ( v6 )\n *(_QWORD *)&v14[v6 - 8] = *(_QWORD *)&v14[v6 - 8];\n if ( a2 <= 0 )\n return 1LL;\n v8 = v14;\n v9 = 0LL;\n while ( 1 )\n {\n v10 = *(_DWORD *)(a1 + 4 * v9);\n if ( (_DWORD)v9 )\n break;\nLABEL_12:\n ++v9;\n *v8++ = v10;\n if ( v2 == v9 )\n return 1LL;\n }\n v11 = v14;\n while ( *v11 != v10 )\n {\n if ( ++v11 == v8 )\n goto LABEL_12;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1160(long long a1, int a2) {\n long long v2;\n long long v3;\n uint8_t *v4;\n short v5;\n signed long long v6;\n void *v7;\n uint32_t *v8;\n long long v9;\n int v10;\n uint32_t *v11;\n uint8_t v14[4088];\n uint64_t v15[2];\n v2 = a2;\n v15[1] = __readfsqword(40u);\n v3 = 4LL * a2 + 15;\n v4 = (char *)v15 - (v3 & 18446744073709547520LL);\n v5 = v3 & 65520;\n if (v15 != (uint64_t *)v4) {\n while (v14 != v4)\n ;\n }\n v6 = v5 & 4095;\n v7 = alloca(v6);\n if (v6) *(uint64_t *)&v14[v6 - 8] = *(uint64_t *)&v14[v6 - 8];\n if (a2 <= 0) return 1LL;\n v8 = v14;\n v9 = 0LL;\n while (1) {\n v10 = *(uint32_t *)(a1 + 4 * v9);\n if ((uint32_t)v9) break;\n LABEL_12:\n ++v9;\n *v8++ = v10;\n if (v2 == v9) return 1LL;\n }\n v11 = v14;\n while (*v11 != v10) {\n if (++v11 == v8) goto LABEL_12;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n long long v3;\n uint8_t *v4;\n short v5;\n signed long long v6;\n void *v7;\n uint32_t *v8;\n long long v9;\n int v10;\n uint32_t *v11;\n uint8_t v14[4088];\n uint64_t v15[2];\n v2 = a2;\n v15[1] = __readfsqword(40u);\n v3 = 4LL * a2 + 15;\n v4 = (char *)v15 - (v3 & 18446744073709547520LL);\n v5 = v3 & 65520;\n if (v15 != (uint64_t *)v4) {\n while (v14 != v4)\n ;\n }\n v6 = v5 & 4095;\n v7 = alloca(v6);\n if (v6) *(uint64_t *)&v14[v6 - 8] = *(uint64_t *)&v14[v6 - 8];\n if (a2 <= 0) return 1LL;\n v8 = v14;\n v9 = 0LL;\n while (1) {\n v10 = *(uint32_t *)(a1 + 4 * v9);\n if ((uint32_t)v9) break;\n LABEL_12:\n ++v9;\n *v8++ = v10;\n if (v2 == v9) return 1LL;\n }\n v11 = v14;\n while (*v11 != v10) {\n if (++v11 == v8) goto LABEL_12;\n }\n return 0LL;\n}" + }, + { + "index": 395, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char func0(char* str1) {\n int ctr[256] = {0};\n char char_order[256];\n int idx = 0;\n int length = strlen(str1);\n for (int i = 0; i < length; i++) {\n char c = str1[i];\n if (ctr[c] == 0) {\n char_order[idx++] = c;\n }\n ctr[c]++;\n }\n for (int i = 0; i < idx; i++) {\n char c = char_order[i];\n if (ctr[c] == 1) {\n return c;\n }\n }\n return '\\0';\n}", + "test": "int main() {\n\n assert(func0(\"abcabc\") == '\\0');\n\n assert(func0(\"abc\") == 'a');\n\n assert(func0(\"ababc\") == 'c');\n\n \n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x540,%rsp\nmov %rdi,-0x538(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea -0x510(%rbp),%rdx\nmov $0x0,%eax\nmov $0x80,%ecx\nmov %rdx,%rdi\nrep stos %rax,%es:(%rdi)\nmovl $0x0,-0x520(%rbp)\nmov -0x538(%rbp),%rax\nmov %rax,%rdi\ncallq 1090 \nmov %eax,-0x514(%rbp)\nmovl $0x0,-0x51c(%rbp)\njmp 1283 \nmov -0x51c(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x538(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmov %al,-0x521(%rbp)\nmovsbl -0x521(%rbp),%eax\ncltq\nmov -0x510(%rbp,%rax,4),%eax\ntest %eax,%eax\njne 125f \nmov -0x520(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x520(%rbp)\ncltq\nmovzbl -0x521(%rbp),%edx\nmov %dl,-0x110(%rbp,%rax,1)\nmovsbl -0x521(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x510(%rbp,%rdx,4),%edx\nadd $0x1,%edx\ncltq\nmov %edx,-0x510(%rbp,%rax,4)\naddl $0x1,-0x51c(%rbp)\nmov -0x51c(%rbp),%eax\ncmp -0x514(%rbp),%eax\njl 1210 \nmovl $0x0,-0x518(%rbp)\njmp 12dc \nmov -0x518(%rbp),%eax\ncltq\nmovzbl -0x110(%rbp,%rax,1),%eax\nmov %al,-0x522(%rbp)\nmovsbl -0x522(%rbp),%eax\ncltq\nmov -0x510(%rbp,%rax,4),%eax\ncmp $0x1,%eax\njne 12d5 \nmovzbl -0x522(%rbp),%eax\njmp 12ef \naddl $0x1,-0x518(%rbp)\nmov -0x518(%rbp),%eax\ncmp -0x520(%rbp),%eax\njl 12a1 \nmov $0x0,%eax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 1303 \ncallq 10a0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 540h\nmov [rbp+s], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rdx, [rbp+var_510]\nmov eax, 0\nmov ecx, 80h\nmov rdi, rdx\nrep stosq\nmov [rbp+var_520], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_514], eax\nmov [rbp+var_51C], 0\njmp short loc_1283\nloc_1210:\nmov eax, [rbp+var_51C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_521], al\nmovsx eax, [rbp+var_521]\ncdqe\nmov eax, [rbp+rax*4+var_510]\ntest eax, eax\njnz short loc_125F\nmov eax, [rbp+var_520]\nlea edx, [rax+1]\nmov [rbp+var_520], edx\ncdqe\nmovzx edx, [rbp+var_521]\nmov [rbp+rax+var_110], dl\nloc_125F:\nmovsx eax, [rbp+var_521]\nmovsxd rdx, eax\nmov edx, [rbp+rdx*4+var_510]\nadd edx, 1\ncdqe\nmov [rbp+rax*4+var_510], edx\nadd [rbp+var_51C], 1\nloc_1283:\nmov eax, [rbp+var_51C]\ncmp eax, [rbp+var_514]\njl loc_1210\nmov [rbp+var_518], 0\njmp short loc_12DC\nloc_12A1:\nmov eax, [rbp+var_518]\ncdqe\nmovzx eax, [rbp+rax+var_110]\nmov [rbp+var_522], al\nmovsx eax, [rbp+var_522]\ncdqe\nmov eax, [rbp+rax*4+var_510]\ncmp eax, 1\njnz short loc_12D5\nmovzx eax, [rbp+var_522]\njmp short loc_12EF\nloc_12D5:\nadd [rbp+var_518], 1\nloc_12DC:\nmov eax, [rbp+var_518]\ncmp eax, [rbp+var_520]\njl short loc_12A1\nmov eax, 0\nloc_12EF:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1303\ncall ___stack_chk_fail\nlocret_1303:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v1; // eax\n unsigned __int8 v3; // [rsp+1Eh] [rbp-522h]\n char v4; // [rsp+1Fh] [rbp-521h]\n int v5; // [rsp+20h] [rbp-520h]\n int i; // [rsp+24h] [rbp-51Ch]\n int j; // [rsp+28h] [rbp-518h]\n int v8; // [rsp+2Ch] [rbp-514h]\n _DWORD v9[322]; // [rsp+30h] [rbp-510h] BYREF\n unsigned __int64 v10; // [rsp+538h] [rbp-8h]\n\n v10 = __readfsqword(0x28u);\n memset(v9, 0, 0x400uLL);\n v5 = 0;\n v8 = strlen(a1);\n for ( i = 0; i < v8; ++i )\n {\n v4 = a1[i];\n if ( !v9[v4] )\n {\n v1 = v5++;\n *((_BYTE *)&v9[256] + v1) = v4;\n }\n ++v9[v4];\n }\n for ( j = 0; j < v5; ++j )\n {\n v3 = *((_BYTE *)&v9[256] + j);\n if ( v9[(char)v3] == 1 )\n return v3;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 540h\nmov [rbp+s], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rdx, [rbp+var_510]\nmov eax, 0\nmov ecx, 80h\nmov rdi, rdx\nrep stosq\nmov [rbp+var_520], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_514], eax\nmov [rbp+var_51C], 0\njmp short loc_1283\nloc_1210:\nmov eax, [rbp+var_51C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_521], al\nmovsx eax, [rbp+var_521]\ncdqe\nmov eax, [rbp+rax*4+var_510]\ntest eax, eax\njnz short loc_125F\nmov eax, [rbp+var_520]\nlea edx, [rax+1]\nmov [rbp+var_520], edx\ncdqe\nmovzx edx, [rbp+var_521]\nmov [rbp+rax+var_110], dl\nloc_125F:\nmovsx eax, [rbp+var_521]\nmovsxd rdx, eax\nmov edx, [rbp+rdx*4+var_510]\nadd edx, 1\ncdqe\nmov [rbp+rax*4+var_510], edx\nadd [rbp+var_51C], 1\nloc_1283:\nmov eax, [rbp+var_51C]\ncmp eax, [rbp+var_514]\njl loc_1210\nmov [rbp+var_518], 0\njmp short loc_12DC\nloc_12A1:\nmov eax, [rbp+var_518]\ncdqe\nmovzx eax, [rbp+rax+var_110]\nmov [rbp+var_522], al\nmovsx eax, [rbp+var_522]\ncdqe\nmov eax, [rbp+rax*4+var_510]\ncmp eax, 1\njnz short loc_12D5\nmovzx eax, [rbp+var_522]\njmp short loc_12EF\nloc_12D5:\nadd [rbp+var_518], 1\nloc_12DC:\nmov eax, [rbp+var_518]\ncmp eax, [rbp+var_520]\njl short loc_12A1\nmov eax, 0\nloc_12EF:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1303\ncall ___stack_chk_fail\nlocret_1303:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(const char *a1)\n{\n int v1; // eax\n unsigned __int8 v3; // [rsp+1Eh] [rbp-522h]\n char v4; // [rsp+1Fh] [rbp-521h]\n int v5; // [rsp+20h] [rbp-520h]\n int i; // [rsp+24h] [rbp-51Ch]\n int j; // [rsp+28h] [rbp-518h]\n int v8; // [rsp+2Ch] [rbp-514h]\n _DWORD v9[322]; // [rsp+30h] [rbp-510h] BYREF\n unsigned __int64 v10; // [rsp+538h] [rbp-8h]\n\n v10 = __readfsqword(0x28u);\n memset(v9, 0, 0x400uLL);\n v5 = 0;\n v8 = strlen(a1);\n for ( i = 0; i < v8; ++i )\n {\n v4 = a1[i];\n if ( !v9[v4] )\n {\n v1 = v5++;\n *((_BYTE *)&v9[256] + v1) = v4;\n }\n ++v9[v4];\n }\n for ( j = 0; j < v5; ++j )\n {\n v3 = *((_BYTE *)&v9[256] + j);\n if ( v9[(char)v3] == 1 )\n return v3;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(const char *a1) {\n int v1;\n unsigned char v3;\n char v4;\n int v5;\n int i;\n int j;\n int v8;\n uint32_t v9[322];\n unsigned long long v10;\n v10 = __readfsqword(40u);\n memset(v9, 0, 1024uLL);\n v5 = 0;\n v8 = strlen(a1);\n for (i = 0; i < v8; ++i) {\n v4 = a1[i];\n if (!v9[v4]) {\n v1 = v5++;\n *((uint8_t *)&v9[256] + v1) = v4;\n }\n ++v9[v4];\n }\n for (j = 0; j < v5; ++j) {\n v3 = *((uint8_t *)&v9[256] + j);\n if (v9[(char)v3] == 1) return v3;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v1;\n unsigned char v3;\n char v4;\n int v5;\n int i;\n int j;\n int v8;\n uint32_t v9[322];\n unsigned long long v10;\n v10 = __readfsqword(40u);\n memset(v9, 0, 1024uLL);\n v5 = 0;\n v8 = strlen(a1);\n for (i = 0; i < v8; ++i) {\n v4 = a1[i];\n if (!v9[v4]) {\n v1 = v5++;\n *((uint8_t *)&v9[256] + v1) = v4;\n }\n ++v9[v4];\n }\n for (j = 0; j < v5; ++j) {\n v3 = *((uint8_t *)&v9[256] + j);\n if (v9[(char)v3] == 1) return v3;\n }\n return 0LL;\n}" + }, + { + "index": 395, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char func0(char* str1) {\n int ctr[256] = {0};\n char char_order[256];\n int idx = 0;\n int length = strlen(str1);\n for (int i = 0; i < length; i++) {\n char c = str1[i];\n if (ctr[c] == 0) {\n char_order[idx++] = c;\n }\n ctr[c]++;\n }\n for (int i = 0; i < idx; i++) {\n char c = char_order[i];\n if (ctr[c] == 1) {\n return c;\n }\n }\n return '\\0';\n}", + "test": "int main() {\n\n assert(func0(\"abcabc\") == '\\0');\n\n assert(func0(\"abc\") == 'a');\n\n assert(func0(\"ababc\") == 'c');\n\n \n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x518,%rsp\nmov %rdi,%rsi\nmov %fs:0x28,%rax\nmov %rax,0x508(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nmov $0x80,%ecx\nrep stos %rax,%es:(%rdi)\nmov $0xffffffffffffffff,%rcx\nmov %rsi,%rdi\nrepnz scas %es:(%rdi),%al\nnot %rcx\nsub $0x1,%rcx\ntest %ecx,%ecx\njle 1265 \nmov %rsi,%rdx\nlea -0x1(%rcx),%eax\nlea 0x1(%rsi,%rax,1),%r8\nmov $0x0,%edi\njmp 11f4 \nmovslq %ecx,%rcx\nadd $0x1,%eax\nmov %eax,(%rsp,%rcx,4)\nadd $0x1,%rdx\ncmp %r8,%rdx\nje 1216 \nmovzbl (%rdx),%esi\nmovsbl %sil,%ecx\nmovsbq %sil,%rax\nmov (%rsp,%rax,4),%eax\ntest %eax,%eax\njne 11e2 \nmovslq %edi,%r9\nmov %sil,0x400(%rsp,%r9,1)\nlea 0x1(%rdi),%edi\njmp 11e2 \ntest %edi,%edi\njle 126c \nlea 0x400(%rsp),%rax\nlea -0x1(%rdi),%edx\nlea 0x401(%rsp,%rdx,1),%rsi\nmovzbl (%rax),%edx\nmovsbq %dl,%rcx\ncmpl $0x1,(%rsp,%rcx,4)\nje 1248 \nadd $0x1,%rax\ncmp %rsi,%rax\njne 122d \nmov $0x0,%edx\nmov 0x508(%rsp),%rax\nxor %fs:0x28,%rax\njne 1273 \nmov %edx,%eax\nadd $0x518,%rsp\nretq\nmov $0x0,%edx\njmp 1248 \nmov $0x0,%edx\njmp 1248 \ncallq 1080 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbx\nsub rsp, 510h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+518h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nmov ecx, 80h\nrep stosq\nmov rdi, rbx; s\ncall _strlen\ntest eax, eax\njle loc_1277\nmov rdx, rbx\nlea eax, [rax-1]\nlea r8, [rbx+rax+1]\nmov edi, 0\njmp short loc_120A\nloc_11F8:\nmovsxd rcx, ecx\nadd eax, 1\nmov [rsp+rcx*4+518h+var_518], eax\nadd rdx, 1\ncmp rdx, r8\njz short loc_122C\nloc_120A:\nmovzx esi, byte ptr [rdx]\nmovsx ecx, sil\nmovsx rax, sil\nmov eax, [rsp+rax*4+518h+var_518]\ntest eax, eax\njnz short loc_11F8\nmovsxd r9, edi\nmov [rsp+r9+518h+var_118], sil\nlea edi, [rdi+1]\njmp short loc_11F8\nloc_122C:\ntest edi, edi\njle short loc_127E\nlea rax, [rsp+518h+var_118]\nmovsxd rdi, edi\nadd rdi, rax\nloc_123E:\nmovzx edx, byte ptr [rax]\nmovsx rcx, dl\ncmp [rsp+rcx*4+518h+var_518], 1\njz short loc_1259\nadd rax, 1\ncmp rax, rdi\njnz short loc_123E\nmov edx, 0\nloc_1259:\nmov rax, [rsp+518h+var_10]\nsub rax, fs:28h\njnz short loc_1285\nmov eax, edx\nadd rsp, 510h\npop rbx\nretn\nloc_1277:\nmov edx, 0\njmp short loc_1259\nloc_127E:\nmov edx, 0\njmp short loc_1259\nloc_1285:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(char *s)\n{\n int v1; // eax\n char *v2; // rdx\n char *v3; // r8\n int v4; // edi\n int v5; // ecx\n int v6; // eax\n unsigned __int8 *v7; // rax\n unsigned __int8 *v8; // rdi\n unsigned int v9; // edx\n _DWORD v11[256]; // [rsp+0h] [rbp-518h] BYREF\n _BYTE v12[264]; // [rsp+400h] [rbp-118h] BYREF\n unsigned __int64 v13; // [rsp+508h] [rbp-10h]\n\n v13 = __readfsqword(0x28u);\n memset(v11, 0, sizeof(v11));\n v1 = strlen(s);\n if ( v1 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = s;\n v3 = &s[v1 - 1 + 1];\n v4 = 0;\n do\n {\n v5 = *v2;\n v6 = v11[*v2];\n if ( !v6 )\n v12[v4++] = *v2;\n v11[v5] = v6 + 1;\n ++v2;\n }\n while ( v2 != v3 );\n if ( v4 <= 0 )\n {\n return 0;\n }\n else\n {\n v7 = v12;\n v8 = &v12[v4];\n while ( 1 )\n {\n v9 = *v7;\n if ( v11[(char)v9] == 1 )\n break;\n if ( ++v7 == v8 )\n return 0;\n }\n }\n }\n return v9;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbx\nsub rsp, 510h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+518h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nmov ecx, 80h\nrep stosq\nmov rdi, rbx; s\ncall _strlen\ntest eax, eax\njle loc_1277\nmov rdx, rbx\nlea eax, [rax-1]\nlea r8, [rbx+rax+1]\nmov edi, 0\njmp short loc_120A\nloc_11F8:\nmovsxd rcx, ecx\nadd eax, 1\nmov [rsp+rcx*4+518h+var_518], eax\nadd rdx, 1\ncmp rdx, r8\njz short loc_122C\nloc_120A:\nmovzx esi, byte ptr [rdx]\nmovsx ecx, sil\nmovsx rax, sil\nmov eax, [rsp+rax*4+518h+var_518]\ntest eax, eax\njnz short loc_11F8\nmovsxd r9, edi\nmov [rsp+r9+518h+var_118], sil\nlea edi, [rdi+1]\njmp short loc_11F8\nloc_122C:\ntest edi, edi\njle short loc_127E\nlea rax, [rsp+518h+var_118]\nmovsxd rdi, edi\nadd rdi, rax\nloc_123E:\nmovzx edx, byte ptr [rax]\nmovsx rcx, dl\ncmp [rsp+rcx*4+518h+var_518], 1\njz short loc_1259\nadd rax, 1\ncmp rax, rdi\njnz short loc_123E\nmov edx, 0\nloc_1259:\nmov rax, [rsp+518h+var_10]\nsub rax, fs:28h\njnz short loc_1285\nmov eax, edx\nadd rsp, 510h\npop rbx\nretn\nloc_1277:\nmov edx, 0\njmp short loc_1259\nloc_127E:\nmov edx, 0\njmp short loc_1259\nloc_1285:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(char *s)\n{\n int v1; // eax\n char *v2; // rdx\n char *v3; // r8\n int v4; // edi\n int v5; // ecx\n int v6; // eax\n unsigned __int8 *v7; // rax\n unsigned __int8 *v8; // rdi\n unsigned int v9; // edx\n _DWORD v11[256]; // [rsp+0h] [rbp-518h] BYREF\n _BYTE v12[264]; // [rsp+400h] [rbp-118h] BYREF\n unsigned __int64 v13; // [rsp+508h] [rbp-10h]\n\n v13 = __readfsqword(0x28u);\n memset(v11, 0, sizeof(v11));\n v1 = strlen(s);\n if ( v1 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = s;\n v3 = &s[v1 - 1 + 1];\n v4 = 0;\n do\n {\n v5 = *v2;\n v6 = v11[*v2];\n if ( !v6 )\n v12[v4++] = *v2;\n v11[v5] = v6 + 1;\n ++v2;\n }\n while ( v2 != v3 );\n if ( v4 <= 0 )\n {\n return 0;\n }\n else\n {\n v7 = v12;\n v8 = &v12[v4];\n while ( 1 )\n {\n v9 = *v7;\n if ( v11[(char)v9] == 1 )\n break;\n if ( ++v7 == v8 )\n return 0;\n }\n }\n }\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(char *s) {\n int v1;\n char *v2;\n char *v3;\n int v4;\n int v5;\n int v6;\n unsigned char *v7;\n unsigned char *v8;\n unsigned int v9;\n uint32_t v11[256];\n uint8_t v12[264];\n unsigned long long v13;\n v13 = __readfsqword(40u);\n memset(v11, 0, sizeof(v11));\n v1 = strlen(s);\n if (v1 <= 0) {\n return 0;\n } else {\n v2 = s;\n v3 = &s[v1 - 1 + 1];\n v4 = 0;\n do {\n v5 = *v2;\n v6 = v11[*v2];\n if (!v6) v12[v4++] = *v2;\n v11[v5] = v6 + 1;\n ++v2;\n } while (v2 != v3);\n if (v4 <= 0) {\n return 0;\n } else {\n v7 = v12;\n v8 = &v12[v4];\n while (1) {\n v9 = *v7;\n if (v11[(char)v9] == 1) break;\n if (++v7 == v8) return 0;\n }\n }\n }\n return v9;\n}", + "ida_pseudo_norm": "long long func0(char *s) {\n int v1;\n char *v2;\n char *v3;\n int v4;\n int v5;\n int v6;\n unsigned char *v7;\n unsigned char *v8;\n unsigned int v9;\n uint32_t v11[256];\n uint8_t v12[264];\n unsigned long long v13;\n v13 = __readfsqword(40u);\n memset(v11, 0, sizeof(v11));\n v1 = strlen(s);\n if (v1 <= 0) {\n return 0;\n } else {\n v2 = s;\n v3 = &s[v1 - 1 + 1];\n v4 = 0;\n do {\n v5 = *v2;\n v6 = v11[*v2];\n if (!v6) v12[v4++] = *v2;\n v11[v5] = v6 + 1;\n ++v2;\n } while (v2 != v3);\n if (v4 <= 0) {\n return 0;\n } else {\n v7 = v12;\n v8 = &v12[v4];\n while (1) {\n v9 = *v7;\n if (v11[(char)v9] == 1) break;\n if (++v7 == v8) return 0;\n }\n }\n }\n return v9;\n}" + }, + { + "index": 395, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char func0(char* str1) {\n int ctr[256] = {0};\n char char_order[256];\n int idx = 0;\n int length = strlen(str1);\n for (int i = 0; i < length; i++) {\n char c = str1[i];\n if (ctr[c] == 0) {\n char_order[idx++] = c;\n }\n ctr[c]++;\n }\n for (int i = 0; i < idx; i++) {\n char c = char_order[i];\n if (ctr[c] == 1) {\n return c;\n }\n }\n return '\\0';\n}", + "test": "int main() {\n\n assert(func0(\"abcabc\") == '\\0');\n\n assert(func0(\"abc\") == 'a');\n\n assert(func0(\"ababc\") == 'c');\n\n \n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov $0x80,%ecx\nmov %rdi,%rbx\nsub $0x510,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x508(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nrep stos %rax,%es:(%rdi)\nmov %rbx,%rdi\ncallq 1090 \ntest %eax,%eax\njle 1330 \nsub $0x1,%eax\nmov %rbx,%rdi\nxor %esi,%esi\nlea 0x1(%rbx,%rax,1),%r8\nnopw 0x0(%rax,%rax,1)\nmovsbq (%rdi),%rdx\nmov (%rsp,%rdx,4),%eax\ntest %eax,%eax\njne 12c9 \nmovslq %esi,%r9\nadd $0x1,%esi\nmov %dl,0x400(%rsp,%r9,1)\nadd $0x1,%eax\nadd $0x1,%rdi\nmov %eax,(%rsp,%rdx,4)\ncmp %r8,%rdi\njne 12b0 \ntest %esi,%esi\nje 1330 \nlea -0x1(%rsi),%edx\nlea 0x400(%rsp),%rax\nlea 0x401(%rsp,%rdx,1),%rcx\njmp 1301 \nnopl 0x0(%rax)\nadd $0x1,%rax\ncmp %rax,%rcx\nje 1330 \nmovsbq (%rax),%rdx\ncmpl $0x1,(%rsp,%rdx,4)\nmov %rdx,%r8\njne 12f8 \nmov 0x508(%rsp),%rax\nxor %fs:0x28,%rax\njne 1335 \nadd $0x510,%rsp\nmov %r8d,%eax\npop %rbx\nretq\nnopl (%rax)\nxor %r8d,%r8d\njmp 130e \ncallq 10a0 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov ecx, 80h\nmov rbx, rdi\nsub rsp, 510h\nmov rax, fs:28h\nmov [rsp+518h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\nmov rdi, rbx; s\ncall _strlen\ntest eax, eax\njle loc_1328\nsub eax, 1\nmov rdi, rbx\nxor edx, edx\nlea r8, [rbx+rax+1]\nnop word ptr [rax+rax+00h]\nloc_12B0:\nmovsx rcx, byte ptr [rdi]\nmov eax, [rsp+rcx*4+518h+var_518]\ntest eax, eax\njnz short loc_12C9\nmovsxd r9, edx\nadd edx, 1\nmov [rsp+r9+518h+var_118], cl\nloc_12C9:\nadd eax, 1\nadd rdi, 1\nmov [rsp+rcx*4+518h+var_518], eax\ncmp rdi, r8\njnz short loc_12B0\ntest edx, edx\njle short loc_1328\nlea rax, [rsp+518h+var_118]\nmovsxd rdx, edx\nadd rdx, rax\njmp short loc_12F9\nloc_12F0:\nadd rax, 1\ncmp rdx, rax\njz short loc_1328\nloc_12F9:\nmovsx rsi, byte ptr [rax]\ncmp [rsp+rsi*4+518h+var_518], 1\nmov rcx, rsi\njnz short loc_12F0\nloc_1306:\nmov rax, [rsp+518h+var_10]\nsub rax, fs:28h\njnz short loc_132C\nadd rsp, 510h\nmov eax, ecx\npop rbx\nretn\nloc_1328:\nxor ecx, ecx\njmp short loc_1306\nloc_132C:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(char *s)\n{\n int v1; // eax\n int v2; // edx\n char *v3; // r8\n __int64 v4; // rcx\n int v5; // eax\n __int64 v6; // r9\n char *v7; // rax\n char *v8; // rdx\n unsigned int v9; // ecx\n _DWORD v11[256]; // [rsp+0h] [rbp-518h] BYREF\n _BYTE v12[264]; // [rsp+400h] [rbp-118h] BYREF\n unsigned __int64 v13; // [rsp+508h] [rbp-10h]\n\n v13 = __readfsqword(0x28u);\n memset(v11, 0, sizeof(v11));\n v1 = strlen(s);\n if ( v1 <= 0 )\n return 0;\n v2 = 0;\n v3 = &s[v1 - 1 + 1];\n do\n {\n v4 = *s;\n v5 = v11[v4];\n if ( !v5 )\n {\n v6 = v2++;\n v12[v6] = v4;\n }\n ++s;\n v11[v4] = v5 + 1;\n }\n while ( s != v3 );\n if ( v2 <= 0 )\n {\n return 0;\n }\n else\n {\n v7 = v12;\n v8 = &v12[v2];\n while ( 1 )\n {\n v9 = *v7;\n if ( v11[*v7] == 1 )\n break;\n if ( v8 == ++v7 )\n return 0;\n }\n }\n return v9;\n}", + "ida_strip_asm": "sub_1260:\nendbr64\npush rbx\nmov ecx, 80h\nmov rbx, rdi\nsub rsp, 510h\nmov rax, fs:28h\nmov [rsp+518h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\nmov rdi, rbx; s\ncall _strlen\ntest eax, eax\njle loc_1328\nsub eax, 1\nmov rdi, rbx\nxor edx, edx\nlea r8, [rbx+rax+1]\nnop word ptr [rax+rax+00h]\nloc_12B0:\nmovsx rcx, byte ptr [rdi]\nmov eax, [rsp+rcx*4+518h+var_518]\ntest eax, eax\njnz short loc_12C9\nmovsxd r9, edx\nadd edx, 1\nmov [rsp+r9+518h+var_118], cl\nloc_12C9:\nadd eax, 1\nadd rdi, 1\nmov [rsp+rcx*4+518h+var_518], eax\ncmp rdi, r8\njnz short loc_12B0\ntest edx, edx\njle short loc_1328\nlea rax, [rsp+518h+var_118]\nmovsxd rdx, edx\nadd rdx, rax\njmp short loc_12F9\nloc_12F0:\nadd rax, 1\ncmp rdx, rax\njz short loc_1328\nloc_12F9:\nmovsx rsi, byte ptr [rax]\ncmp [rsp+rsi*4+518h+var_518], 1\nmov rcx, rsi\njnz short loc_12F0\nloc_1306:\nmov rax, [rsp+518h+var_10]\nsub rax, fs:28h\njnz short loc_132C\nadd rsp, 510h\nmov eax, ecx\npop rbx\nretn\nloc_1328:\nxor ecx, ecx\njmp short loc_1306\nloc_132C:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1260(char *s)\n{\n int v1; // eax\n int v2; // edx\n char *v3; // r8\n __int64 v4; // rcx\n int v5; // eax\n __int64 v6; // r9\n char *v7; // rax\n char *v8; // rdx\n unsigned int v9; // ecx\n _DWORD v11[256]; // [rsp+0h] [rbp-518h] BYREF\n _BYTE v12[264]; // [rsp+400h] [rbp-118h] BYREF\n unsigned __int64 v13; // [rsp+508h] [rbp-10h]\n\n v13 = __readfsqword(0x28u);\n memset(v11, 0, sizeof(v11));\n v1 = strlen(s);\n if ( v1 <= 0 )\n return 0;\n v2 = 0;\n v3 = &s[v1 - 1 + 1];\n do\n {\n v4 = *s;\n v5 = v11[v4];\n if ( !v5 )\n {\n v6 = v2++;\n v12[v6] = v4;\n }\n ++s;\n v11[v4] = v5 + 1;\n }\n while ( s != v3 );\n if ( v2 <= 0 )\n {\n return 0;\n }\n else\n {\n v7 = v12;\n v8 = &v12[v2];\n while ( 1 )\n {\n v9 = *v7;\n if ( v11[*v7] == 1 )\n break;\n if ( v8 == ++v7 )\n return 0;\n }\n }\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1260(char *s) {\n int v1;\n int v2;\n char *v3;\n long long v4;\n int v5;\n long long v6;\n char *v7;\n char *v8;\n unsigned int v9;\n uint32_t v11[256];\n uint8_t v12[264];\n unsigned long long v13;\n v13 = __readfsqword(40u);\n memset(v11, 0, sizeof(v11));\n v1 = strlen(s);\n if (v1 <= 0) return 0;\n v2 = 0;\n v3 = &s[v1 - 1 + 1];\n do {\n v4 = *s;\n v5 = v11[v4];\n if (!v5) {\n v6 = v2++;\n v12[v6] = v4;\n }\n ++s;\n v11[v4] = v5 + 1;\n } while (s != v3);\n if (v2 <= 0) {\n return 0;\n } else {\n v7 = v12;\n v8 = &v12[v2];\n while (1) {\n v9 = *v7;\n if (v11[*v7] == 1) break;\n if (v8 == ++v7) return 0;\n }\n }\n return v9;\n}", + "ida_pseudo_norm": "long long func0(char *s) {\n int v1;\n int v2;\n char *v3;\n long long v4;\n int v5;\n long long v6;\n char *v7;\n char *v8;\n unsigned int v9;\n uint32_t v11[256];\n uint8_t v12[264];\n unsigned long long v13;\n v13 = __readfsqword(40u);\n memset(v11, 0, sizeof(v11));\n v1 = strlen(s);\n if (v1 <= 0) return 0;\n v2 = 0;\n v3 = &s[v1 - 1 + 1];\n do {\n v4 = *s;\n v5 = v11[v4];\n if (!v5) {\n v6 = v2++;\n v12[v6] = v4;\n }\n ++s;\n v11[v4] = v5 + 1;\n } while (s != v3);\n if (v2 <= 0) {\n return 0;\n } else {\n v7 = v12;\n v8 = &v12[v2];\n while (1) {\n v9 = *v7;\n if (v11[*v7] == 1) break;\n if (v8 == ++v7) return 0;\n }\n }\n return v9;\n}" + }, + { + "index": 395, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char func0(char* str1) {\n int ctr[256] = {0};\n char char_order[256];\n int idx = 0;\n int length = strlen(str1);\n for (int i = 0; i < length; i++) {\n char c = str1[i];\n if (ctr[c] == 0) {\n char_order[idx++] = c;\n }\n ctr[c]++;\n }\n for (int i = 0; i < idx; i++) {\n char c = char_order[i];\n if (ctr[c] == 1) {\n return c;\n }\n }\n return '\\0';\n}", + "test": "int main() {\n\n assert(func0(\"abcabc\") == '\\0');\n\n assert(func0(\"abc\") == 'a');\n\n assert(func0(\"ababc\") == 'c');\n\n \n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov $0x80,%ecx\nmov %rdi,%rbx\nsub $0x510,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x508(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nrep stos %rax,%es:(%rdi)\nmov %rbx,%rdi\ncallq 1090 \ntest %eax,%eax\njle 1348 \nsub $0x1,%eax\nmov %rbx,%rdi\nxor %ecx,%ecx\nlea 0x1(%rbx,%rax,1),%r8\nnopw 0x0(%rax,%rax,1)\nmovsbq (%rdi),%rdx\nmov (%rsp,%rdx,4),%eax\ntest %eax,%eax\njne 12e4 \nadd $0x1,%rdi\nmov %dl,0x400(%rsp,%rcx,1)\nlea 0x1(%rcx),%r9d\nmovl $0x1,(%rsp,%rdx,4)\ncmp %r8,%rdi\nje 12fa \nmovsbq (%rdi),%rdx\nmovslq %r9d,%rcx\nmov (%rsp,%rdx,4),%eax\ntest %eax,%eax\nje 12bb \nadd $0x1,%eax\nadd $0x1,%rdi\nmov %eax,(%rsp,%rdx,4)\ncmp %r8,%rdi\njne 12b0 \ntest %ecx,%ecx\nje 1348 \nmov %ecx,%r9d\nlea -0x1(%r9),%edx\nlea 0x400(%rsp),%rax\nlea 0x401(%rsp,%rdx,1),%rcx\njmp 1319 \nadd $0x1,%rax\ncmp %rax,%rcx\nje 1348 \nmovsbq (%rax),%rdx\ncmpl $0x1,(%rsp,%rdx,4)\nmov %rdx,%r8\njne 1310 \nmov 0x508(%rsp),%rax\nxor %fs:0x28,%rax\njne 134d \nadd $0x510,%rsp\nmov %r8d,%eax\npop %rbx\nretq\nnopl (%rax)\nxor %r8d,%r8d\njmp 1326 \ncallq 10a0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov ecx, 80h\nmov rbx, rdi\nsub rsp, 510h\nmov rax, fs:28h\nmov [rsp+518h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\nmov rdi, rbx; s\ncall _strlen\ntest eax, eax\njle loc_1340\nsub eax, 1\nmov rdi, rbx\nxor edx, edx\nlea r8, [rbx+rax+1]\nnop word ptr [rax+rax+00h]\nloc_12B0:\nmovsx rcx, byte ptr [rdi]\nmov eax, [rsp+rcx*4+518h+var_518]\ntest eax, eax\njnz short loc_1328\nlea eax, [rdx+1]\nadd rdi, 1\nmov [rsp+rdx+518h+var_118], cl\nmov [rsp+rcx*4+518h+var_518], 1\nmovsxd rdx, eax\ncmp rdi, r8\njnz short loc_12B0\nloc_12D8:\ntest edx, edx\njle short loc_1340\nlea rax, [rsp+518h+var_118]\nadd rdx, rax\njmp short loc_12F9\nloc_12F0:\nadd rax, 1\ncmp rdx, rax\njz short loc_1340\nloc_12F9:\nmovsx rsi, byte ptr [rax]\ncmp [rsp+rsi*4+518h+var_518], 1\nmov rcx, rsi\njnz short loc_12F0\nloc_1306:\nmov rax, [rsp+518h+var_10]\nsub rax, fs:28h\njnz short loc_1344\nadd rsp, 510h\nmov eax, ecx\npop rbx\nretn\nloc_1328:\nadd eax, 1\nadd rdi, 1\nmov [rsp+rcx*4+518h+var_518], eax\ncmp rdi, r8\njnz loc_12B0\njmp short loc_12D8\nloc_1340:\nxor ecx, ecx\njmp short loc_1306\nloc_1344:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(char *s)\n{\n int v1; // eax\n __int64 v2; // rdx\n char *v3; // r8\n __int64 v4; // rcx\n int v5; // eax\n char *v6; // rax\n char *v7; // rdx\n unsigned int v8; // ecx\n _DWORD v10[256]; // [rsp+0h] [rbp-518h] BYREF\n _BYTE v11[264]; // [rsp+400h] [rbp-118h] BYREF\n unsigned __int64 v12; // [rsp+508h] [rbp-10h]\n\n v12 = __readfsqword(0x28u);\n memset(v10, 0, sizeof(v10));\n v1 = strlen(s);\n if ( v1 <= 0 )\n return 0;\n v2 = 0LL;\n v3 = &s[v1 - 1 + 1];\n do\n {\n while ( 1 )\n {\n v4 = *s;\n v5 = v10[v4];\n if ( v5 )\n break;\n ++s;\n v11[v2] = v4;\n v10[v4] = 1;\n v2 = (int)v2 + 1;\n if ( s == v3 )\n goto LABEL_5;\n }\n ++s;\n v10[v4] = v5 + 1;\n }\n while ( s != v3 );\nLABEL_5:\n if ( (int)v2 <= 0 )\n {\n return 0;\n }\n else\n {\n v6 = v11;\n v7 = &v11[v2];\n while ( 1 )\n {\n v8 = *v6;\n if ( v10[*v6] == 1 )\n break;\n if ( v7 == ++v6 )\n return 0;\n }\n }\n return v8;\n}", + "ida_strip_asm": "sub_1260:\nendbr64\npush rbx\nmov ecx, 80h\nmov rbx, rdi\nsub rsp, 510h\nmov rax, fs:28h\nmov [rsp+518h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\nmov rdi, rbx; s\ncall _strlen\ntest eax, eax\njle loc_1340\nsub eax, 1\nmov rdi, rbx\nxor edx, edx\nlea r8, [rbx+rax+1]\nnop word ptr [rax+rax+00h]\nloc_12B0:\nmovsx rcx, byte ptr [rdi]\nmov eax, [rsp+rcx*4+518h+var_518]\ntest eax, eax\njnz short loc_1328\nlea eax, [rdx+1]\nadd rdi, 1\nmov [rsp+rdx+518h+var_118], cl\nmov [rsp+rcx*4+518h+var_518], 1\nmovsxd rdx, eax\ncmp rdi, r8\njnz short loc_12B0\nloc_12D8:\ntest edx, edx\njle short loc_1340\nlea rax, [rsp+518h+var_118]\nadd rdx, rax\njmp short loc_12F9\nloc_12F0:\nadd rax, 1\ncmp rdx, rax\njz short loc_1340\nloc_12F9:\nmovsx rsi, byte ptr [rax]\ncmp [rsp+rsi*4+518h+var_518], 1\nmov rcx, rsi\njnz short loc_12F0\nloc_1306:\nmov rax, [rsp+518h+var_10]\nsub rax, fs:28h\njnz short loc_1344\nadd rsp, 510h\nmov eax, ecx\npop rbx\nretn\nloc_1328:\nadd eax, 1\nadd rdi, 1\nmov [rsp+rcx*4+518h+var_518], eax\ncmp rdi, r8\njnz loc_12B0\njmp short loc_12D8\nloc_1340:\nxor ecx, ecx\njmp short loc_1306\nloc_1344:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1260(char *s)\n{\n int v1; // eax\n __int64 v2; // rdx\n char *v3; // r8\n __int64 v4; // rcx\n int v5; // eax\n char *v6; // rax\n char *v7; // rdx\n unsigned int v8; // ecx\n _DWORD v10[256]; // [rsp+0h] [rbp-518h] BYREF\n _BYTE v11[264]; // [rsp+400h] [rbp-118h] BYREF\n unsigned __int64 v12; // [rsp+508h] [rbp-10h]\n\n v12 = __readfsqword(0x28u);\n memset(v10, 0, sizeof(v10));\n v1 = strlen(s);\n if ( v1 <= 0 )\n return 0;\n v2 = 0LL;\n v3 = &s[v1 - 1 + 1];\n do\n {\n while ( 1 )\n {\n v4 = *s;\n v5 = v10[v4];\n if ( v5 )\n break;\n ++s;\n v11[v2] = v4;\n v10[v4] = 1;\n v2 = (int)v2 + 1;\n if ( s == v3 )\n goto LABEL_5;\n }\n ++s;\n v10[v4] = v5 + 1;\n }\n while ( s != v3 );\nLABEL_5:\n if ( (int)v2 <= 0 )\n {\n return 0;\n }\n else\n {\n v6 = v11;\n v7 = &v11[v2];\n while ( 1 )\n {\n v8 = *v6;\n if ( v10[*v6] == 1 )\n break;\n if ( v7 == ++v6 )\n return 0;\n }\n }\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1260(char *s) {\n int v1;\n long long v2;\n char *v3;\n long long v4;\n int v5;\n char *v6;\n char *v7;\n unsigned int v8;\n uint32_t v10[256];\n uint8_t v11[264];\n unsigned long long v12;\n v12 = __readfsqword(40u);\n memset(v10, 0, sizeof(v10));\n v1 = strlen(s);\n if (v1 <= 0) return 0;\n v2 = 0LL;\n v3 = &s[v1 - 1 + 1];\n do {\n while (1) {\n v4 = *s;\n v5 = v10[v4];\n if (v5) break;\n ++s;\n v11[v2] = v4;\n v10[v4] = 1;\n v2 = (int)v2 + 1;\n if (s == v3) goto LABEL_5;\n }\n ++s;\n v10[v4] = v5 + 1;\n } while (s != v3);\nLABEL_5:\n if ((int)v2 <= 0) {\n return 0;\n } else {\n v6 = v11;\n v7 = &v11[v2];\n while (1) {\n v8 = *v6;\n if (v10[*v6] == 1) break;\n if (v7 == ++v6) return 0;\n }\n }\n return v8;\n}", + "ida_pseudo_norm": "long long func0(char *s) {\n int v1;\n long long v2;\n char *v3;\n long long v4;\n int v5;\n char *v6;\n char *v7;\n unsigned int v8;\n uint32_t v10[256];\n uint8_t v11[264];\n unsigned long long v12;\n v12 = __readfsqword(40u);\n memset(v10, 0, sizeof(v10));\n v1 = strlen(s);\n if (v1 <= 0) return 0;\n v2 = 0LL;\n v3 = &s[v1 - 1 + 1];\n do {\n while (1) {\n v4 = *s;\n v5 = v10[v4];\n if (v5) break;\n ++s;\n v11[v2] = v4;\n v10[v4] = 1;\n v2 = (int)v2 + 1;\n if (s == v3) goto LABEL_5;\n }\n ++s;\n v10[v4] = v5 + 1;\n } while (s != v3);\nLABEL_5:\n if ((int)v2 <= 0) {\n return 0;\n } else {\n v6 = v11;\n v7 = &v11[v2];\n while (1) {\n v8 = *v6;\n if (v10[*v6] == 1) break;\n if (v7 == ++v6) return 0;\n }\n }\n return v8;\n}" + }, + { + "index": 396, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* string) {\n regex_t regex;\n int reti;\n char msgbuf[100];\n reti = regcomp(®ex, \"^[a-z]$|^([a-z]).*\\\\1$\", REG_EXTENDED);\n if (reti) {\n fprintf(stderr, \"Could not compile regex\\n\");\n return \"Invalid\";\n }\n reti = regexec(®ex, string, 0, NULL, 0);\n if (!reti) {\n regfree(®ex);\n return \"Valid\";\n }\n else if (reti == REG_NOMATCH) {\n regfree(®ex);\n return \"Invalid\";\n }\n else {\n regerror(reti, ®ex, msgbuf, sizeof(msgbuf));\n fprintf(stderr, \"Regex match failed: %s\\n\", msgbuf);\n regfree(®ex);\n return \"Invalid\";\n }\n}", + "test": "int main() {\n\n assert(func0(\"abba\") == \"Valid\");\n\n assert(func0(\"a\") == \"Valid\");\n\n assert(func0(\"abcd\") == \"Invalid\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0xd0,%rsp\nmov %rdi,-0xc8(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea -0xb0(%rbp),%rax\nmov $0x1,%edx\nlea 0xda7(%rip),%rsi\nmov %rax,%rdi\ncallq 10f0 \nmov %eax,-0xb4(%rbp)\ncmpl $0x0,-0xb4(%rbp)\nje 12a4 \nmov 0x2da1(%rip),%rax\nmov %rax,%rcx\nmov $0x18,%edx\nmov $0x1,%esi\nlea 0xd8b(%rip),%rdi\ncallq 1130 \nlea 0xd98(%rip),%rax\njmpq 1364 \nmov -0xc8(%rbp),%rsi\nlea -0xb0(%rbp),%rax\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rax,%rdi\ncallq 1120 \nmov %eax,-0xb4(%rbp)\ncmpl $0x0,-0xb4(%rbp)\njne 12f1 \nlea -0xb0(%rbp),%rax\nmov %rax,%rdi\ncallq 10c0 \nlea 0xd50(%rip),%rax\njmp 1364 \ncmpl $0x1,-0xb4(%rbp)\njne 1312 \nlea -0xb0(%rbp),%rax\nmov %rax,%rdi\ncallq 10c0 \nlea 0xd27(%rip),%rax\njmp 1364 \nlea -0x70(%rbp),%rdx\nlea -0xb0(%rbp),%rsi\nmov -0xb4(%rbp),%eax\nmov $0x64,%ecx\nmov %eax,%edi\ncallq 1110 \nmov 0x2cea(%rip),%rax\nlea -0x70(%rbp),%rdx\nlea 0xd04(%rip),%rsi\nmov %rax,%rdi\nmov $0x0,%eax\ncallq 1100 \nlea -0xb0(%rbp),%rax\nmov %rax,%rdi\ncallq 10c0 \nlea 0xcd3(%rip),%rax\nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 1378 \ncallq 10d0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0D0h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nlea rcx, pattern; \"^[a-z]$|^([a-z]).*\\\\1$\"\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+errcode], eax\ncmp [rbp+errcode], 0\njz short loc_12AA\nmov rax, cs:__bss_start\nmov rcx, rax; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rax, aCouldNotCompil; \"Could not compile regex\\n\"\nmov rdi, rax; ptr\ncall _fwrite\nlea rax, aInvalid; \"Invalid\"\njmp loc_136D\nloc_12AA:\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+errcode], eax\ncmp [rbp+errcode], 0\njnz short loc_12F7\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nlea rax, aValid; \"Valid\"\njmp short loc_136D\nloc_12F7:\ncmp [rbp+errcode], 1\njnz short loc_1318\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nlea rax, aInvalid; \"Invalid\"\njmp short loc_136D\nloc_1318:\nlea rdx, [rbp+errbuf]; errbuf\nlea rsi, [rbp+preg]; preg\nmov eax, [rbp+errcode]\nmov ecx, 64h ; 'd'; errbuf_size\nmov edi, eax; errcode\ncall _regerror\nmov rax, cs:__bss_start\nlea rdx, [rbp+errbuf]\nlea rcx, format; \"Regex match failed: %s\\n\"\nmov rsi, rcx; format\nmov rdi, rax; stream\nmov eax, 0\ncall _fprintf\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nlea rax, aInvalid; \"Invalid\"\nloc_136D:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1381\ncall ___stack_chk_fail\nlocret_1381:\nleave\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n int errcode; // [rsp+1Ch] [rbp-B4h]\n regex_t preg; // [rsp+20h] [rbp-B0h] BYREF\n char errbuf[104]; // [rsp+60h] [rbp-70h] BYREF\n unsigned __int64 v5; // [rsp+C8h] [rbp-8h]\n\n v5 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"^[a-z]$|^([a-z]).*\\\\1$\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n return \"Invalid\";\n }\n else\n {\n errcode = regexec(&preg, a1, 0LL, 0LL, 0);\n if ( errcode )\n {\n if ( errcode != 1 )\n {\n regerror(errcode, &preg, errbuf, 0x64uLL);\n fprintf(_bss_start, \"Regex match failed: %s\\n\", errbuf);\n }\n regfree(&preg);\n return \"Invalid\";\n }\n else\n {\n regfree(&preg);\n return \"Valid\";\n }\n }\n}", + "ida_strip_asm": "sub_1229:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0D0h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nlea rcx, pattern; \"^[a-z]$|^([a-z]).*\\\\1$\"\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+errcode], eax\ncmp [rbp+errcode], 0\njz short loc_12AA\nmov rax, cs:stderr\nmov rcx, rax; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rax, aCouldNotCompil; \"Could not compile regex\\n\"\nmov rdi, rax; ptr\ncall _fwrite\nlea rax, aInvalid; \"Invalid\"\njmp loc_136D\nloc_12AA:\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+errcode], eax\ncmp [rbp+errcode], 0\njnz short loc_12F7\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nlea rax, aValid; \"Valid\"\njmp short loc_136D\nloc_12F7:\ncmp [rbp+errcode], 1\njnz short loc_1318\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nlea rax, aInvalid; \"Invalid\"\njmp short loc_136D\nloc_1318:\nlea rdx, [rbp+errbuf]; errbuf\nlea rsi, [rbp+preg]; preg\nmov eax, [rbp+errcode]\nmov ecx, 64h ; 'd'; errbuf_size\nmov edi, eax; errcode\ncall _regerror\nmov rax, cs:stderr\nlea rdx, [rbp+errbuf]\nlea rcx, format; \"Regex match failed: %s\\n\"\nmov rsi, rcx; format\nmov rdi, rax; stream\nmov eax, 0\ncall _fprintf\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nlea rax, aInvalid; \"Invalid\"\nloc_136D:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1381\ncall ___stack_chk_fail\nlocret_1381:\nleave\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1229(const char *a1)\n{\n int errcode; // [rsp+1Ch] [rbp-B4h]\n regex_t preg; // [rsp+20h] [rbp-B0h] BYREF\n char errbuf[104]; // [rsp+60h] [rbp-70h] BYREF\n unsigned __int64 v5; // [rsp+C8h] [rbp-8h]\n\n v5 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"^[a-z]$|^([a-z]).*\\\\1$\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n return \"Invalid\";\n }\n else\n {\n errcode = regexec(&preg, a1, 0LL, 0LL, 0);\n if ( errcode )\n {\n if ( errcode != 1 )\n {\n regerror(errcode, &preg, errbuf, 0x64uLL);\n fprintf(stderr, \"Regex match failed: %s\\n\", errbuf);\n }\n regfree(&preg);\n return \"Invalid\";\n }\n else\n {\n regfree(&preg);\n return \"Valid\";\n }\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1229(const char *a1) {\n int errcode;\n regex_t preg;\n char errbuf[104];\n unsigned long long v5;\n v5 = __readfsqword(40u);\n if (regcomp(&preg, \"^[a-z]$|^([a-z]).*\\\\1$\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n return \"Invalid\";\n } else {\n errcode = regexec(&preg, a1, 0LL, 0LL, 0);\n if (errcode) {\n if (errcode != 1) {\n regerror(errcode, &preg, errbuf, 100uLL);\n fprintf(stderr, \"Regex match failed: %s\\n\", errbuf);\n }\n regfree(&preg);\n return \"Invalid\";\n } else {\n regfree(&preg);\n return \"Valid\";\n }\n }\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n int errcode;\n regex_t preg;\n char errbuf[104];\n unsigned long long v5;\n v5 = __readfsqword(40u);\n if (regcomp(&preg, \"^[a-z]$|^([a-z]).*\\\\1$\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n return \"Invalid\";\n } else {\n errcode = regexec(&preg, a1, 0LL, 0LL, 0);\n if (errcode) {\n if (errcode != 1) {\n regerror(errcode, &preg, errbuf, 100uLL);\n fprintf(_bss_start, \"Regex match failed: %s\\n\", errbuf);\n }\n regfree(&preg);\n return \"Invalid\";\n } else {\n regfree(&preg);\n return \"Valid\";\n }\n }\n}" + }, + { + "index": 396, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* string) {\n regex_t regex;\n int reti;\n char msgbuf[100];\n reti = regcomp(®ex, \"^[a-z]$|^([a-z]).*\\\\1$\", REG_EXTENDED);\n if (reti) {\n fprintf(stderr, \"Could not compile regex\\n\");\n return \"Invalid\";\n }\n reti = regexec(®ex, string, 0, NULL, 0);\n if (!reti) {\n regfree(®ex);\n return \"Valid\";\n }\n else if (reti == REG_NOMATCH) {\n regfree(®ex);\n return \"Invalid\";\n }\n else {\n regerror(reti, ®ex, msgbuf, sizeof(msgbuf));\n fprintf(stderr, \"Regex match failed: %s\\n\", msgbuf);\n regfree(®ex);\n return \"Invalid\";\n }\n}", + "test": "int main() {\n\n assert(func0(\"abba\") == \"Valid\");\n\n assert(func0(\"a\") == \"Valid\");\n\n assert(func0(\"abcd\") == \"Invalid\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0xb8,%rsp\nmov %rdi,%rbx\nmov %fs:0x28,%rax\nmov %rax,0xa8(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nmov $0x1,%edx\nlea 0xdb7(%rip),%rsi\ncallq 10f0 \ntest %eax,%eax\njne 12fa \nmov %rsp,%rdi\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rbx,%rsi\ncallq 1110 \ntest %eax,%eax\nje 1320 \ncmp $0x1,%eax\nje 1331 \nlea 0x40(%rsp),%rbp\nmov %rsp,%rbx\nmov $0x64,%ecx\nmov %rbp,%rdx\nmov %rbx,%rsi\nmov %eax,%edi\ncallq 1100 \nmov %rbp,%rcx\nlea 0xd89(%rip),%rdx\nmov $0x1,%esi\nmov 0x2d5c(%rip),%rdi\nmov $0x0,%eax\ncallq 1130 <__fprintf_chk@plt>\nmov %rbx,%rdi\ncallq 10c0 \nlea 0xd27(%rip),%rax\nmov 0xa8(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 1342 \nadd $0xb8,%rsp\npop %rbx\npop %rbp\nretq\nmov 0x2d1f(%rip),%rcx\nmov $0x18,%edx\nmov $0x1,%esi\nlea 0xd16(%rip),%rdi\ncallq 1120 \nlea 0xce6(%rip),%rax\njmp 12dd \nmov %rsp,%rdi\ncallq 10c0 \nlea 0xcdd(%rip),%rax\njmp 12dd \nmov %rsp,%rdi\ncallq 10c0 \nlea 0xcc4(%rip),%rax\njmp 12dd \ncallq 10d0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 0B8h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+0C8h+var_20], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"^[a-z]$|^([a-z]).*\\\\1$\"\ncall _regcomp\ntest eax, eax\njnz loc_12FA\nmov rdi, rsp; preg\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\ncall _regexec\ntest eax, eax\njz loc_1320\ncmp eax, 1\njz loc_1331\nlea rbp, [rsp+0C8h+errbuf]\nmov rbx, rsp\nmov ecx, 64h ; 'd'; errbuf_size\nmov rdx, rbp; errbuf\nmov rsi, rbx; preg\nmov edi, eax; errcode\ncall _regerror\nmov rcx, rbp\nlea rdx, aRegexMatchFail; \"Regex match failed: %s\\n\"\nmov esi, 2\nmov rdi, cs:__bss_start\nmov eax, 0\ncall ___fprintf_chk\nmov rdi, rbx; preg\ncall _regfree\nlea rax, aInvalid; \"Invalid\"\nloc_12DD:\nmov rdx, [rsp+0C8h+var_20]\nsub rdx, fs:28h\njnz short loc_1342\nadd rsp, 0B8h\npop rbx\npop rbp\nretn\nloc_12FA:\nmov rcx, cs:__bss_start; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nlea rax, aInvalid; \"Invalid\"\njmp short loc_12DD\nloc_1320:\nmov rdi, rsp; preg\ncall _regfree\nlea rax, aValid; \"Valid\"\njmp short loc_12DD\nloc_1331:\nmov rdi, rsp; preg\ncall _regfree\nlea rax, aInvalid; \"Invalid\"\njmp short loc_12DD\nloc_1342:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // eax\n regex_t v3; // [rsp+0h] [rbp-C8h] BYREF\n char errbuf[104]; // [rsp+40h] [rbp-88h] BYREF\n unsigned __int64 v5; // [rsp+A8h] [rbp-20h]\n\n v5 = __readfsqword(0x28u);\n if ( regcomp(&v3, \"^[a-z]$|^([a-z]).*\\\\1$\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n return \"Invalid\";\n }\n else\n {\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n if ( v1 )\n {\n if ( v1 != 1 )\n {\n regerror(v1, &v3, errbuf, 0x64uLL);\n __fprintf_chk(_bss_start, 2LL, \"Regex match failed: %s\\n\", errbuf);\n }\n regfree(&v3);\n return \"Invalid\";\n }\n else\n {\n regfree(&v3);\n return \"Valid\";\n }\n }\n}", + "ida_strip_asm": "sub_1229:\nendbr64\npush rbp\npush rbx\nsub rsp, 0B8h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+0C8h+var_20], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"^[a-z]$|^([a-z]).*\\\\1$\"\ncall _regcomp\ntest eax, eax\njnz loc_12FA\nmov rdi, rsp; preg\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\ncall _regexec\ntest eax, eax\njz loc_1320\ncmp eax, 1\njz loc_1331\nlea rbp, [rsp+0C8h+errbuf]\nmov rbx, rsp\nmov ecx, 64h ; 'd'; errbuf_size\nmov rdx, rbp; errbuf\nmov rsi, rbx; preg\nmov edi, eax; errcode\ncall _regerror\nmov rcx, rbp\nlea rdx, aRegexMatchFail; \"Regex match failed: %s\\n\"\nmov esi, 2\nmov rdi, cs:stderr\nmov eax, 0\ncall ___fprintf_chk\nmov rdi, rbx; preg\ncall _regfree\nlea rax, aInvalid; \"Invalid\"\nloc_12DD:\nmov rdx, [rsp+0C8h+var_20]\nsub rdx, fs:28h\njnz short loc_1342\nadd rsp, 0B8h\npop rbx\npop rbp\nretn\nloc_12FA:\nmov rcx, cs:stderr; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nlea rax, aInvalid; \"Invalid\"\njmp short loc_12DD\nloc_1320:\nmov rdi, rsp; preg\ncall _regfree\nlea rax, aValid; \"Valid\"\njmp short loc_12DD\nloc_1331:\nmov rdi, rsp; preg\ncall _regfree\nlea rax, aInvalid; \"Invalid\"\njmp short loc_12DD\nloc_1342:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_1229(char *string)\n{\n int v1; // eax\n regex_t v3; // [rsp+0h] [rbp-C8h] BYREF\n char errbuf[104]; // [rsp+40h] [rbp-88h] BYREF\n unsigned __int64 v5; // [rsp+A8h] [rbp-20h]\n\n v5 = __readfsqword(0x28u);\n if ( regcomp(&v3, \"^[a-z]$|^([a-z]).*\\\\1$\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n return \"Invalid\";\n }\n else\n {\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n if ( v1 )\n {\n if ( v1 != 1 )\n {\n regerror(v1, &v3, errbuf, 0x64uLL);\n __fprintf_chk(stderr, 2LL, \"Regex match failed: %s\\n\", errbuf);\n }\n regfree(&v3);\n return \"Invalid\";\n }\n else\n {\n regfree(&v3);\n return \"Valid\";\n }\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1229(char *string) {\n int v1;\n regex_t v3;\n char errbuf[104];\n unsigned long long v5;\n v5 = __readfsqword(40u);\n if (regcomp(&v3, \"^[a-z]$|^([a-z]).*\\\\1$\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n return \"Invalid\";\n } else {\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n if (v1) {\n if (v1 != 1) {\n regerror(v1, &v3, errbuf, 100uLL);\n __fprintf_chk(stderr, 2LL, \"Regex match failed: %s\\n\", errbuf);\n }\n regfree(&v3);\n return \"Invalid\";\n } else {\n regfree(&v3);\n return \"Valid\";\n }\n }\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n regex_t v3;\n char errbuf[104];\n unsigned long long v5;\n v5 = __readfsqword(40u);\n if (regcomp(&v3, \"^[a-z]$|^([a-z]).*\\\\1$\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n return \"Invalid\";\n } else {\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n if (v1) {\n if (v1 != 1) {\n regerror(v1, &v3, errbuf, 100uLL);\n __fprintf_chk(_bss_start, 2LL, \"Regex match failed: %s\\n\", errbuf);\n }\n regfree(&v3);\n return \"Invalid\";\n } else {\n regfree(&v3);\n return \"Valid\";\n }\n }\n}" + }, + { + "index": 396, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* string) {\n regex_t regex;\n int reti;\n char msgbuf[100];\n reti = regcomp(®ex, \"^[a-z]$|^([a-z]).*\\\\1$\", REG_EXTENDED);\n if (reti) {\n fprintf(stderr, \"Could not compile regex\\n\");\n return \"Invalid\";\n }\n reti = regexec(®ex, string, 0, NULL, 0);\n if (!reti) {\n regfree(®ex);\n return \"Valid\";\n }\n else if (reti == REG_NOMATCH) {\n regfree(®ex);\n return \"Invalid\";\n }\n else {\n regerror(reti, ®ex, msgbuf, sizeof(msgbuf));\n fprintf(stderr, \"Regex match failed: %s\\n\", msgbuf);\n regfree(®ex);\n return \"Invalid\";\n }\n}", + "test": "int main() {\n\n assert(func0(\"abba\") == \"Valid\");\n\n assert(func0(\"a\") == \"Valid\");\n\n assert(func0(\"abcd\") == \"Invalid\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov $0x1,%edx\nmov %rdi,%r12\nlea 0xd1d(%rip),%rsi\npush %rbp\nsub $0xb8,%rsp\nmov %fs:0x28,%rax\nmov %rax,0xa8(%rsp)\nxor %eax,%eax\nmov %rsp,%rbp\nmov %rbp,%rdi\ncallq 10f0 \ntest %eax,%eax\njne 13a8 \nmov %rbp,%rdi\nxor %r8d,%r8d\nxor %ecx,%ecx\nxor %edx,%edx\nmov %r12,%rsi\ncallq 1110 \nmov %eax,%edi\ntest %eax,%eax\nje 13d0 \ncmp $0x1,%eax\nje 1376 \nlea 0x40(%rsp),%r12\nmov $0x64,%ecx\nmov %rbp,%rsi\nmov %r12,%rdx\ncallq 1100 \nmov %r12,%rcx\nmov $0x1,%esi\nxor %eax,%eax\nmov 0x2cb6(%rip),%rdi\nlea 0xcd0(%rip),%rdx\ncallq 1130 <__fprintf_chk@plt>\nmov %rbp,%rdi\ncallq 10c0 \nlea 0xc7f(%rip),%rax\nmov 0xa8(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 13e1 \nadd $0xb8,%rsp\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax,%rax,1)\nmov 0x2c71(%rip),%rcx\nmov $0x18,%edx\nmov $0x1,%esi\nlea 0xc68(%rip),%rdi\ncallq 1120 \nlea 0xc38(%rip),%rax\njmp 1385 \nxchg %ax,%ax\nmov %rbp,%rdi\ncallq 10c0 \nlea 0xc2d(%rip),%rax\njmp 1385 \ncallq 10d0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov edx, 1; cflags\nmov rbp, rdi\nlea rsi, pattern; \"^[a-z]$|^([a-z]).*\\\\1$\"\npush rbx\nsub rsp, 0B8h\nmov rax, fs:28h\nmov [rsp+0C8h+var_20], rax\nxor eax, eax\nmov rbx, rsp\nmov rdi, rbx; preg\ncall _regcomp\ntest eax, eax\njnz loc_13A8\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbp; string\nmov rdi, rbx; preg\ncall _regexec\ntest eax, eax\njz loc_13E0\ncmp eax, 1\njz loc_13D0\nlea rbp, [rsp+0C8h+errbuf]\nmov ecx, 64h ; 'd'; errbuf_size\nmov rsi, rbx; preg\nmov edi, eax; errcode\nmov rdx, rbp; errbuf\ncall _regerror\nmov rcx, rbp\nmov esi, 2\nxor eax, eax\nmov rdi, cs:__bss_start\nlea rdx, aRegexMatchFail; \"Regex match failed: %s\\n\"\ncall ___fprintf_chk\nmov rdi, rbx; preg\ncall _regfree\nloc_1381:\nlea rax, aInvalid; \"Invalid\"\nloc_1388:\nmov rdx, [rsp+0C8h+var_20]\nsub rdx, fs:28h\njnz short loc_13F1\nadd rsp, 0B8h\npop rbx\npop rbp\nretn\nloc_13A8:\nmov rcx, cs:__bss_start; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\njmp short loc_1381\nloc_13D0:\nmov rdi, rbx; preg\ncall _regfree\njmp short loc_1381\nloc_13E0:\nmov rdi, rbx; preg\ncall _regfree\nlea rax, aValid; \"Valid\"\njmp short loc_1388\nloc_13F1:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // eax\n regex_t v3; // [rsp+0h] [rbp-C8h] BYREF\n char errbuf[104]; // [rsp+40h] [rbp-88h] BYREF\n unsigned __int64 v5; // [rsp+A8h] [rbp-20h]\n\n v5 = __readfsqword(0x28u);\n if ( regcomp(&v3, \"^[a-z]$|^([a-z]).*\\\\1$\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n return \"Invalid\";\n }\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n if ( v1 )\n {\n if ( v1 != 1 )\n {\n regerror(v1, &v3, errbuf, 0x64uLL);\n __fprintf_chk(_bss_start, 2LL, \"Regex match failed: %s\\n\", errbuf);\n }\n regfree(&v3);\n return \"Invalid\";\n }\n regfree(&v3);\n return \"Valid\";\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\npush rbp\nmov edx, 1; cflags\nmov rbp, rdi\nlea rsi, pattern; \"^[a-z]$|^([a-z]).*\\\\1$\"\npush rbx\nsub rsp, 0B8h\nmov rax, fs:28h\nmov [rsp+0C8h+var_20], rax\nxor eax, eax\nmov rbx, rsp\nmov rdi, rbx; preg\ncall _regcomp\ntest eax, eax\njnz loc_13A8\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbp; string\nmov rdi, rbx; preg\ncall _regexec\ntest eax, eax\njz loc_13E0\ncmp eax, 1\njz loc_13D0\nlea rbp, [rsp+0C8h+errbuf]\nmov ecx, 64h ; 'd'; errbuf_size\nmov rsi, rbx; preg\nmov edi, eax; errcode\nmov rdx, rbp; errbuf\ncall _regerror\nmov rcx, rbp\nmov esi, 2\nxor eax, eax\nmov rdi, cs:stderr\nlea rdx, aRegexMatchFail; \"Regex match failed: %s\\n\"\ncall ___fprintf_chk\nmov rdi, rbx; preg\ncall _regfree\nloc_1381:\nlea rax, aInvalid; \"Invalid\"\nloc_1388:\nmov rdx, [rsp+0C8h+var_20]\nsub rdx, fs:28h\njnz short loc_13F1\nadd rsp, 0B8h\npop rbx\npop rbp\nretn\nloc_13A8:\nmov rcx, cs:stderr; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\njmp short loc_1381\nloc_13D0:\nmov rdi, rbx; preg\ncall _regfree\njmp short loc_1381\nloc_13E0:\nmov rdi, rbx; preg\ncall _regfree\nlea rax, aValid; \"Valid\"\njmp short loc_1388\nloc_13F1:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_12E0(char *string)\n{\n int v1; // eax\n regex_t v3; // [rsp+0h] [rbp-C8h] BYREF\n char errbuf[104]; // [rsp+40h] [rbp-88h] BYREF\n unsigned __int64 v5; // [rsp+A8h] [rbp-20h]\n\n v5 = __readfsqword(0x28u);\n if ( regcomp(&v3, \"^[a-z]$|^([a-z]).*\\\\1$\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n return \"Invalid\";\n }\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n if ( v1 )\n {\n if ( v1 != 1 )\n {\n regerror(v1, &v3, errbuf, 0x64uLL);\n __fprintf_chk(stderr, 2LL, \"Regex match failed: %s\\n\", errbuf);\n }\n regfree(&v3);\n return \"Invalid\";\n }\n regfree(&v3);\n return \"Valid\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_12E0(char *string) {\n int v1;\n regex_t v3;\n char errbuf[104];\n unsigned long long v5;\n v5 = __readfsqword(40u);\n if (regcomp(&v3, \"^[a-z]$|^([a-z]).*\\\\1$\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n return \"Invalid\";\n }\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n if (v1) {\n if (v1 != 1) {\n regerror(v1, &v3, errbuf, 100uLL);\n __fprintf_chk(stderr, 2LL, \"Regex match failed: %s\\n\", errbuf);\n }\n regfree(&v3);\n return \"Invalid\";\n }\n regfree(&v3);\n return \"Valid\";\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n regex_t v3;\n char errbuf[104];\n unsigned long long v5;\n v5 = __readfsqword(40u);\n if (regcomp(&v3, \"^[a-z]$|^([a-z]).*\\\\1$\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n return \"Invalid\";\n }\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n if (v1) {\n if (v1 != 1) {\n regerror(v1, &v3, errbuf, 100uLL);\n __fprintf_chk(_bss_start, 2LL, \"Regex match failed: %s\\n\", errbuf);\n }\n regfree(&v3);\n return \"Invalid\";\n }\n regfree(&v3);\n return \"Valid\";\n}" + }, + { + "index": 396, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* string) {\n regex_t regex;\n int reti;\n char msgbuf[100];\n reti = regcomp(®ex, \"^[a-z]$|^([a-z]).*\\\\1$\", REG_EXTENDED);\n if (reti) {\n fprintf(stderr, \"Could not compile regex\\n\");\n return \"Invalid\";\n }\n reti = regexec(®ex, string, 0, NULL, 0);\n if (!reti) {\n regfree(®ex);\n return \"Valid\";\n }\n else if (reti == REG_NOMATCH) {\n regfree(®ex);\n return \"Invalid\";\n }\n else {\n regerror(reti, ®ex, msgbuf, sizeof(msgbuf));\n fprintf(stderr, \"Regex match failed: %s\\n\", msgbuf);\n regfree(®ex);\n return \"Invalid\";\n }\n}", + "test": "int main() {\n\n assert(func0(\"abba\") == \"Valid\");\n\n assert(func0(\"a\") == \"Valid\");\n\n assert(func0(\"abcd\") == \"Invalid\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov $0x1,%edx\nmov %rdi,%r12\nlea 0xd1d(%rip),%rsi\npush %rbp\nsub $0xb8,%rsp\nmov %fs:0x28,%rax\nmov %rax,0xa8(%rsp)\nxor %eax,%eax\nmov %rsp,%rbp\nmov %rbp,%rdi\ncallq 10f0 \ntest %eax,%eax\njne 13a8 \nmov %rbp,%rdi\nxor %r8d,%r8d\nxor %ecx,%ecx\nxor %edx,%edx\nmov %r12,%rsi\ncallq 1110 \nmov %eax,%edi\ntest %eax,%eax\nje 13d0 \ncmp $0x1,%eax\nje 1376 \nlea 0x40(%rsp),%r12\nmov $0x64,%ecx\nmov %rbp,%rsi\nmov %r12,%rdx\ncallq 1100 \nmov %r12,%rcx\nmov $0x1,%esi\nxor %eax,%eax\nmov 0x2cb6(%rip),%rdi\nlea 0xcd0(%rip),%rdx\ncallq 1130 <__fprintf_chk@plt>\nmov %rbp,%rdi\ncallq 10c0 \nlea 0xc7f(%rip),%rax\nmov 0xa8(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 13e1 \nadd $0xb8,%rsp\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax,%rax,1)\nmov 0x2c71(%rip),%rcx\nmov $0x18,%edx\nmov $0x1,%esi\nlea 0xc68(%rip),%rdi\ncallq 1120 \nlea 0xc38(%rip),%rax\njmp 1385 \nxchg %ax,%ax\nmov %rbp,%rdi\ncallq 10c0 \nlea 0xc2d(%rip),%rax\njmp 1385 \ncallq 10d0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov edx, 1; cflags\nmov rbp, rdi\nlea rsi, pattern; \"^[a-z]$|^([a-z]).*\\\\1$\"\npush rbx\nsub rsp, 0B8h\nmov rax, fs:28h\nmov [rsp+0C8h+var_20], rax\nxor eax, eax\nmov rbx, rsp\nmov rdi, rbx; preg\ncall _regcomp\ntest eax, eax\njnz loc_13A8\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbp; string\nmov rdi, rbx; preg\ncall _regexec\ntest eax, eax\njz loc_13E0\ncmp eax, 1\njz loc_13D0\nlea rbp, [rsp+0C8h+errbuf]\nmov ecx, 64h ; 'd'; errbuf_size\nmov rsi, rbx; preg\nmov edi, eax; errcode\nmov rdx, rbp; errbuf\ncall _regerror\nmov rcx, rbp\nmov esi, 2\nxor eax, eax\nmov rdi, cs:__bss_start\nlea rdx, aRegexMatchFail; \"Regex match failed: %s\\n\"\ncall ___fprintf_chk\nmov rdi, rbx; preg\ncall _regfree\nloc_1381:\nlea rax, aInvalid; \"Invalid\"\nloc_1388:\nmov rdx, [rsp+0C8h+var_20]\nsub rdx, fs:28h\njnz short loc_13F1\nadd rsp, 0B8h\npop rbx\npop rbp\nretn\nloc_13A8:\nmov rcx, cs:__bss_start; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\njmp short loc_1381\nloc_13D0:\nmov rdi, rbx; preg\ncall _regfree\njmp short loc_1381\nloc_13E0:\nmov rdi, rbx; preg\ncall _regfree\nlea rax, aValid; \"Valid\"\njmp short loc_1388\nloc_13F1:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // eax\n regex_t v3; // [rsp+0h] [rbp-C8h] BYREF\n char errbuf[104]; // [rsp+40h] [rbp-88h] BYREF\n unsigned __int64 v5; // [rsp+A8h] [rbp-20h]\n\n v5 = __readfsqword(0x28u);\n if ( regcomp(&v3, \"^[a-z]$|^([a-z]).*\\\\1$\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n return \"Invalid\";\n }\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n if ( v1 )\n {\n if ( v1 != 1 )\n {\n regerror(v1, &v3, errbuf, 0x64uLL);\n __fprintf_chk(_bss_start, 2LL, \"Regex match failed: %s\\n\", errbuf);\n }\n regfree(&v3);\n return \"Invalid\";\n }\n regfree(&v3);\n return \"Valid\";\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\npush rbp\nmov edx, 1; cflags\nmov rbp, rdi\nlea rsi, pattern; \"^[a-z]$|^([a-z]).*\\\\1$\"\npush rbx\nsub rsp, 0B8h\nmov rax, fs:28h\nmov [rsp+0C8h+var_20], rax\nxor eax, eax\nmov rbx, rsp\nmov rdi, rbx; preg\ncall _regcomp\ntest eax, eax\njnz loc_13A8\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbp; string\nmov rdi, rbx; preg\ncall _regexec\ntest eax, eax\njz loc_13E0\ncmp eax, 1\njz loc_13D0\nlea rbp, [rsp+0C8h+errbuf]\nmov ecx, 64h ; 'd'; errbuf_size\nmov rsi, rbx; preg\nmov edi, eax; errcode\nmov rdx, rbp; errbuf\ncall _regerror\nmov rcx, rbp\nmov esi, 2\nxor eax, eax\nmov rdi, cs:stderr\nlea rdx, aRegexMatchFail; \"Regex match failed: %s\\n\"\ncall ___fprintf_chk\nmov rdi, rbx; preg\ncall _regfree\nloc_1381:\nlea rax, aInvalid; \"Invalid\"\nloc_1388:\nmov rdx, [rsp+0C8h+var_20]\nsub rdx, fs:28h\njnz short loc_13F1\nadd rsp, 0B8h\npop rbx\npop rbp\nretn\nloc_13A8:\nmov rcx, cs:stderr; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\njmp short loc_1381\nloc_13D0:\nmov rdi, rbx; preg\ncall _regfree\njmp short loc_1381\nloc_13E0:\nmov rdi, rbx; preg\ncall _regfree\nlea rax, aValid; \"Valid\"\njmp short loc_1388\nloc_13F1:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_12E0(char *string)\n{\n int v1; // eax\n regex_t v3; // [rsp+0h] [rbp-C8h] BYREF\n char errbuf[104]; // [rsp+40h] [rbp-88h] BYREF\n unsigned __int64 v5; // [rsp+A8h] [rbp-20h]\n\n v5 = __readfsqword(0x28u);\n if ( regcomp(&v3, \"^[a-z]$|^([a-z]).*\\\\1$\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n return \"Invalid\";\n }\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n if ( v1 )\n {\n if ( v1 != 1 )\n {\n regerror(v1, &v3, errbuf, 0x64uLL);\n __fprintf_chk(stderr, 2LL, \"Regex match failed: %s\\n\", errbuf);\n }\n regfree(&v3);\n return \"Invalid\";\n }\n regfree(&v3);\n return \"Valid\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_12E0(char *string) {\n int v1;\n regex_t v3;\n char errbuf[104];\n unsigned long long v5;\n v5 = __readfsqword(40u);\n if (regcomp(&v3, \"^[a-z]$|^([a-z]).*\\\\1$\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n return \"Invalid\";\n }\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n if (v1) {\n if (v1 != 1) {\n regerror(v1, &v3, errbuf, 100uLL);\n __fprintf_chk(stderr, 2LL, \"Regex match failed: %s\\n\", errbuf);\n }\n regfree(&v3);\n return \"Invalid\";\n }\n regfree(&v3);\n return \"Valid\";\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n regex_t v3;\n char errbuf[104];\n unsigned long long v5;\n v5 = __readfsqword(40u);\n if (regcomp(&v3, \"^[a-z]$|^([a-z]).*\\\\1$\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n return \"Invalid\";\n }\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n if (v1) {\n if (v1 != 1) {\n regerror(v1, &v3, errbuf, 100uLL);\n __fprintf_chk(_bss_start, 2LL, \"Regex match failed: %s\\n\", errbuf);\n }\n regfree(&v3);\n return \"Invalid\";\n }\n regfree(&v3);\n return \"Valid\";\n}" + }, + { + "index": 397, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int a, int b, int c) {\n int median;\n if (a > b) {\n if (a < c) {\n median = a;\n } else if (b > c) {\n median = b;\n } else {\n median = c;\n }\n } else {\n if (a > c) {\n median = a;\n } else if (b < c) {\n median = b;\n } else {\n median = c;\n }\n }\n return median;\n}", + "test": "int main() {\n\n assert(func0(25, 55, 65) == 55);\n\n assert(func0(20, 10, 30) == 20);\n\n assert(func0(15, 45, 75) == 45);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov %edx,-0x1c(%rbp)\nmov -0x14(%rbp),%eax\ncmp -0x18(%rbp),%eax\njle 118a \nmov -0x14(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njge 1172 \nmov -0x14(%rbp),%eax\nmov %eax,-0x4(%rbp)\njmp 11b0 \nmov -0x18(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njle 1182 \nmov -0x18(%rbp),%eax\nmov %eax,-0x4(%rbp)\njmp 11b0 \nmov -0x1c(%rbp),%eax\nmov %eax,-0x4(%rbp)\njmp 11b0 \nmov -0x14(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njle 119a \nmov -0x14(%rbp),%eax\nmov %eax,-0x4(%rbp)\njmp 11b0 \nmov -0x18(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njge 11aa \nmov -0x18(%rbp),%eax\nmov %eax,-0x4(%rbp)\njmp 11b0 \nmov -0x1c(%rbp),%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_18]\njle short loc_118A\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_1C]\njge short loc_1172\nmov eax, [rbp+var_14]\nmov [rbp+var_4], eax\njmp short loc_11B0\nloc_1172:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_1C]\njle short loc_1182\nmov eax, [rbp+var_18]\nmov [rbp+var_4], eax\njmp short loc_11B0\nloc_1182:\nmov eax, [rbp+var_1C]\nmov [rbp+var_4], eax\njmp short loc_11B0\nloc_118A:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_1C]\njle short loc_119A\nmov eax, [rbp+var_14]\nmov [rbp+var_4], eax\njmp short loc_11B0\nloc_119A:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_1C]\njge short loc_11AA\nmov eax, [rbp+var_18]\nmov [rbp+var_4], eax\njmp short loc_11B0\nloc_11AA:\nmov eax, [rbp+var_1C]\nmov [rbp+var_4], eax\nloc_11B0:\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(signed int a1, signed int a2, signed int a3)\n{\n if ( a1 <= a2 )\n {\n if ( a1 <= a3 )\n {\n if ( a2 >= a3 )\n return (unsigned int)a3;\n else\n return (unsigned int)a2;\n }\n else\n {\n return (unsigned int)a1;\n }\n }\n else if ( a1 >= a3 )\n {\n if ( a2 <= a3 )\n return (unsigned int)a3;\n else\n return (unsigned int)a2;\n }\n else\n {\n return (unsigned int)a1;\n }\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_18]\njle short loc_118A\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_1C]\njge short loc_1172\nmov eax, [rbp+var_14]\nmov [rbp+var_4], eax\njmp short loc_11B0\nloc_1172:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_1C]\njle short loc_1182\nmov eax, [rbp+var_18]\nmov [rbp+var_4], eax\njmp short loc_11B0\nloc_1182:\nmov eax, [rbp+var_1C]\nmov [rbp+var_4], eax\njmp short loc_11B0\nloc_118A:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_1C]\njle short loc_119A\nmov eax, [rbp+var_14]\nmov [rbp+var_4], eax\njmp short loc_11B0\nloc_119A:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_1C]\njge short loc_11AA\nmov eax, [rbp+var_18]\nmov [rbp+var_4], eax\njmp short loc_11B0\nloc_11AA:\nmov eax, [rbp+var_1C]\nmov [rbp+var_4], eax\nloc_11B0:\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(signed int a1, signed int a2, signed int a3)\n{\n if ( a1 <= a2 )\n {\n if ( a1 <= a3 )\n {\n if ( a2 >= a3 )\n return (unsigned int)a3;\n else\n return (unsigned int)a2;\n }\n else\n {\n return (unsigned int)a1;\n }\n }\n else if ( a1 >= a3 )\n {\n if ( a2 <= a3 )\n return (unsigned int)a3;\n else\n return (unsigned int)a2;\n }\n else\n {\n return (unsigned int)a1;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(signed int a1, signed int a2, signed int a3) {\n if (a1 <= a2) {\n if (a1 <= a3) {\n if (a2 >= a3)\n return (unsigned int)a3;\n else\n return (unsigned int)a2;\n } else {\n return (unsigned int)a1;\n }\n } else if (a1 >= a3) {\n if (a2 <= a3)\n return (unsigned int)a3;\n else\n return (unsigned int)a2;\n } else {\n return (unsigned int)a1;\n }\n}", + "ida_pseudo_norm": "long long func0(signed int a1, signed int a2, signed int a3) {\n if (a1 <= a2) {\n if (a1 <= a3) {\n if (a2 >= a3)\n return (unsigned int)a3;\n else\n return (unsigned int)a2;\n } else {\n return (unsigned int)a1;\n }\n } else if (a1 >= a3) {\n if (a2 <= a3)\n return (unsigned int)a3;\n else\n return (unsigned int)a2;\n } else {\n return (unsigned int)a1;\n }\n}" + }, + { + "index": 398, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int nums[], int length) {\n int sum = 0;\n for (int i = 0; i < length; i++) {\n int n = nums[i];\n if (n < 0) n = -n;\n while (n > 0) {\n sum += n % 10;\n n /= 10;\n }\n }\n return sum;\n}", + "test": "int main() {\n\n int nums1[] = {10, 2, 56};\n\n assert(func0(nums1, 3) == 14);\n\n\n\n int nums2[] = {10, 20, 4, 5,70};\n\n assert(func0(nums2, 5) == 19);\n\n\n\n int nums3[] = {10, 20, -4, 5,-70};\n\n assert(func0(nums3, 5) == 19);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 1201 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x4(%rbp)\ncmpl $0x0,-0x4(%rbp)\njns 11f7 \nnegl -0x4(%rbp)\njmp 11f7 \nmov -0x4(%rbp),%ecx\nmovslq %ecx,%rax\nimul $0x66666667,%rax,%rax\nshr $0x20,%rax\nmov %eax,%edx\nsar $0x2,%edx\nmov %ecx,%eax\nsar $0x1f,%eax\nsub %eax,%edx\nmov %edx,%eax\nshl $0x2,%eax\nadd %edx,%eax\nadd %eax,%eax\nsub %eax,%ecx\nmov %ecx,%edx\nadd %edx,-0xc(%rbp)\nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nimul $0x66666667,%rdx,%rdx\nshr $0x20,%rdx\nsar $0x2,%edx\nsar $0x1f,%eax\nsub %eax,%edx\nmov %edx,%eax\nmov %eax,-0x4(%rbp)\ncmpl $0x0,-0x4(%rbp)\njg 11ac \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1188 \nmov -0xc(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_1201\nloc_1188:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\ncmp [rbp+var_4], 0\njns short loc_11F7\nneg [rbp+var_4]\njmp short loc_11F7\nloc_11AC:\nmov ecx, [rbp+var_4]\nmovsxd rax, ecx\nimul rax, 66666667h\nshr rax, 20h\nmov edx, eax\nsar edx, 2\nmov eax, ecx\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nsub ecx, eax\nmov edx, ecx\nadd [rbp+var_C], edx\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_4], eax\nloc_11F7:\ncmp [rbp+var_4], 0\njg short loc_11AC\nadd [rbp+var_8], 1\nloc_1201:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl loc_1188\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+10h] [rbp-Ch]\n int i; // [rsp+14h] [rbp-8h]\n int v5; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v5 = *(_DWORD *)(4LL * i + a1);\n if ( v5 < 0 )\n v5 = -v5;\n while ( v5 > 0 )\n {\n v3 += v5 % 10;\n v5 /= 10;\n }\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_1201\nloc_1188:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\ncmp [rbp+var_4], 0\njns short loc_11F7\nneg [rbp+var_4]\njmp short loc_11F7\nloc_11AC:\nmov ecx, [rbp+var_4]\nmovsxd rax, ecx\nimul rax, 66666667h\nshr rax, 20h\nmov edx, eax\nsar edx, 2\nmov eax, ecx\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nsub ecx, eax\nmov edx, ecx\nadd [rbp+var_C], edx\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_4], eax\nloc_11F7:\ncmp [rbp+var_4], 0\njg short loc_11AC\nadd [rbp+var_8], 1\nloc_1201:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl loc_1188\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+10h] [rbp-Ch]\n int i; // [rsp+14h] [rbp-8h]\n int v5; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v5 = *(_DWORD *)(4LL * i + a1);\n if ( v5 < 0 )\n v5 = -v5;\n while ( v5 > 0 )\n {\n v3 += v5 % 10;\n v5 /= 10;\n }\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n unsigned int v3;\n int i;\n int v5;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n v5 = *(uint32_t *)(4LL * i + a1);\n if (v5 < 0) v5 = -v5;\n while (v5 > 0) {\n v3 += v5 % 10;\n v5 /= 10;\n }\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n int v5;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n v5 = *(uint32_t *)(4LL * i + a1);\n if (v5 < 0) v5 = -v5;\n while (v5 > 0) {\n v3 += v5 % 10;\n v5 /= 10;\n }\n }\n return v3;\n}" + }, + { + "index": 398, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int nums[], int length) {\n int sum = 0;\n for (int i = 0; i < length; i++) {\n int n = nums[i];\n if (n < 0) n = -n;\n while (n > 0) {\n sum += n % 10;\n n /= 10;\n }\n }\n return sum;\n}", + "test": "int main() {\n\n int nums1[] = {10, 2, 56};\n\n assert(func0(nums1, 3) == 14);\n\n\n\n int nums2[] = {10, 20, 4, 5,70};\n\n assert(func0(nums2, 5) == 19);\n\n\n\n int nums3[] = {10, 20, -4, 5,-70};\n\n assert(func0(nums3, 5) == 19);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11ca \nmov %rdi,%r8\nlea -0x1(%rsi),%eax\nlea 0x4(%rdi,%rax,4),%rdi\nmov $0x0,%esi\njmp 118c \nadd $0x4,%r8\ncmp %rdi,%r8\nje 11cf \nmov (%r8),%edx\nmov %edx,%eax\nsar $0x1f,%eax\nxor %eax,%edx\nsub %eax,%edx\ntest %edx,%edx\njle 1183 \nmovslq %edx,%rax\nimul $0x66666667,%rax,%rax\nsar $0x22,%rax\nmov %edx,%ecx\nsar $0x1f,%ecx\nsub %ecx,%eax\nlea (%rax,%rax,4),%ecx\nadd %ecx,%ecx\nmov %edx,%r9d\nsub %ecx,%r9d\nadd %r9d,%esi\nmov %edx,%ecx\nmov %eax,%edx\ncmp $0x9,%ecx\njg 119c \njmp 1183 \nmov $0x0,%esi\nmov %esi,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11C3\nmov r8, rdi\nmovsxd rsi, esi\nlea r9, [rdi+rsi*4]\nmov esi, 0\nloc_1180:\nmov eax, [r8]\nmov edx, eax\nneg edx\ncmovs edx, eax\ntest edx, edx\njle short loc_11B7\nloc_118E:\nmovsxd rax, edx\nimul rax, 66666667h\nsar rax, 22h\nmov ecx, edx\nsar ecx, 1Fh\nsub eax, ecx\nlea ecx, [rax+rax*4]\nadd ecx, ecx\nmov edi, edx\nsub edi, ecx\nadd esi, edi\nmov ecx, edx\nmov edx, eax\ncmp ecx, 9\njg short loc_118E\nloc_11B7:\nadd r8, 4\ncmp r8, r9\njnz short loc_1180\nloc_11C0:\nmov eax, esi\nretn\nloc_11C3:\nmov esi, 0\njmp short loc_11C0", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int *v2; // r8\n int *v3; // r9\n unsigned int v4; // esi\n int v5; // edx\n int v6; // ecx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n {\n v5 = -*v2;\n if ( *v2 > 0 )\n v5 = *v2;\n if ( v5 > 0 )\n {\n do\n {\n v4 += v5 % 10;\n v6 = v5;\n v5 /= 10;\n }\n while ( v6 > 9 );\n }\n ++v2;\n }\n while ( v2 != v3 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11C3\nmov r8, rdi\nmovsxd rsi, esi\nlea r9, [rdi+rsi*4]\nmov esi, 0\nloc_1180:\nmov eax, [r8]\nmov edx, eax\nneg edx\ncmovs edx, eax\ntest edx, edx\njle short loc_11B7\nloc_118E:\nmovsxd rax, edx\nimul rax, 66666667h\nsar rax, 22h\nmov ecx, edx\nsar ecx, 1Fh\nsub eax, ecx\nlea ecx, [rax+rax*4]\nadd ecx, ecx\nmov edi, edx\nsub edi, ecx\nadd esi, edi\nmov ecx, edx\nmov edx, eax\ncmp ecx, 9\njg short loc_118E\nloc_11B7:\nadd r8, 4\ncmp r8, r9\njnz short loc_1180\nloc_11C0:\nmov eax, esi\nretn\nloc_11C3:\nmov esi, 0\njmp short loc_11C0", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int *a1, int a2)\n{\n int *v2; // r8\n int *v3; // r9\n unsigned int v4; // esi\n int v5; // edx\n int v6; // ecx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n {\n v5 = -*v2;\n if ( *v2 > 0 )\n v5 = *v2;\n if ( v5 > 0 )\n {\n do\n {\n v4 += v5 % 10;\n v6 = v5;\n v5 /= 10;\n }\n while ( v6 > 9 );\n }\n ++v2;\n }\n while ( v2 != v3 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int *a1, int a2) {\n int *v2;\n int *v3;\n unsigned int v4;\n int v5;\n int v6;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do {\n v5 = -*v2;\n if (*v2 > 0) v5 = *v2;\n if (v5 > 0) {\n do {\n v4 += v5 % 10;\n v6 = v5;\n v5 /= 10;\n } while (v6 > 9);\n }\n ++v2;\n } while (v2 != v3);\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int *v2;\n int *v3;\n unsigned int v4;\n int v5;\n int v6;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do {\n v5 = -*v2;\n if (*v2 > 0) v5 = *v2;\n if (v5 > 0) {\n do {\n v4 += v5 % 10;\n v6 = v5;\n v5 /= 10;\n } while (v6 > 9);\n }\n ++v2;\n } while (v2 != v3);\n }\n return v4;\n}" + }, + { + "index": 398, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int nums[], int length) {\n int sum = 0;\n for (int i = 0; i < length; i++) {\n int n = nums[i];\n if (n < 0) n = -n;\n while (n > 0) {\n sum += n % 10;\n n /= 10;\n }\n }\n return sum;\n}", + "test": "int main() {\n\n int nums1[] = {10, 2, 56};\n\n assert(func0(nums1, 3) == 14);\n\n\n\n int nums2[] = {10, 20, 4, 5,70};\n\n assert(func0(nums2, 5) == 19);\n\n\n\n int nums3[] = {10, 20, -4, 5,-70};\n\n assert(func0(nums3, 5) == 19);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 13ef \nlea -0x1(%rsi),%eax\nxor %r8d,%r8d\nmov $0xcccccccd,%esi\nlea 0x4(%rdi,%rax,4),%r9\nnopl 0x0(%rax,%rax,1)\nmov (%rdi),%eax\nmov %eax,%ecx\nsar $0x1f,%ecx\nmov %ecx,%edx\nxor %eax,%edx\nsub %ecx,%edx\ntest %eax,%eax\nje 13e2 \nnopl 0x0(%rax)\nmov %edx,%eax\nimul %rsi,%rax\nshr $0x23,%rax\nlea (%rax,%rax,4),%ecx\nadd %ecx,%ecx\nsub %ecx,%edx\nadd %edx,%r8d\nmov %eax,%edx\ntest %eax,%eax\njne 13c8 \nadd $0x4,%rdi\ncmp %r9,%rdi\njne 13b0 \nmov %r8d,%eax\nretq\nxor %r8d,%r8d\nmov %r8d,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_12D5\nmovsxd rsi, esi\nmov r8d, 0CCCCCCCDh\nlea r9, [rdi+rsi*4]\nxor esi, esi\nnop word ptr [rax+rax+00000000h]\nloc_12A0:\nmov eax, [rdi]\nmov edx, eax\nneg edx\ncmovs edx, eax\ntest eax, eax\njz short loc_12C9\nnop dword ptr [rax]\nloc_12B0:\nmov eax, edx\nimul rax, r8\nshr rax, 23h\nlea ecx, [rax+rax*4]\nadd ecx, ecx\nsub edx, ecx\nadd esi, edx\nmov edx, eax\ntest eax, eax\njnz short loc_12B0\nloc_12C9:\nadd rdi, 4\ncmp rdi, r9\njnz short loc_12A0\nmov eax, esi\nretn\nloc_12D5:\nxor esi, esi\nmov eax, esi\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n unsigned int *v2; // r9\n unsigned int v3; // esi\n unsigned int v4; // edx\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = &a1[a2];\n v3 = 0;\n do\n {\n v4 = -*a1;\n if ( (int)*a1 > 0 )\n v4 = *a1;\n if ( *a1 )\n {\n do\n {\n v3 += v4 % 0xA;\n v4 /= 0xAu;\n }\n while ( v4 );\n }\n ++a1;\n }\n while ( a1 != v2 );\n return v3;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\ntest esi, esi\njle short loc_12D5\nmovsxd rsi, esi\nmov r8d, 0CCCCCCCDh\nlea r9, [rdi+rsi*4]\nxor esi, esi\nnop word ptr [rax+rax+00000000h]\nloc_12A0:\nmov eax, [rdi]\nmov edx, eax\nneg edx\ncmovs edx, eax\ntest eax, eax\njz short loc_12C9\nnop dword ptr [rax]\nloc_12B0:\nmov eax, edx\nimul rax, r8\nshr rax, 23h\nlea ecx, [rax+rax*4]\nadd ecx, ecx\nsub edx, ecx\nadd esi, edx\nmov edx, eax\ntest eax, eax\njnz short loc_12B0\nloc_12C9:\nadd rdi, 4\ncmp rdi, r9\njnz short loc_12A0\nmov eax, esi\nretn\nloc_12D5:\nxor esi, esi\nmov eax, esi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1280(unsigned int *a1, int a2)\n{\n unsigned int *v2; // r9\n unsigned int v3; // esi\n unsigned int v4; // edx\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = &a1[a2];\n v3 = 0;\n do\n {\n v4 = -*a1;\n if ( (int)*a1 > 0 )\n v4 = *a1;\n if ( *a1 )\n {\n do\n {\n v3 += v4 % 0xA;\n v4 /= 0xAu;\n }\n while ( v4 );\n }\n ++a1;\n }\n while ( a1 != v2 );\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1280(unsigned int *a1, int a2) {\n unsigned int *v2;\n unsigned int v3;\n unsigned int v4;\n if (a2 <= 0) return 0LL;\n v2 = &a1[a2];\n v3 = 0;\n do {\n v4 = -*a1;\n if ((int)*a1 > 0) v4 = *a1;\n if (*a1) {\n do {\n v3 += v4 % 10;\n v4 /= 10u;\n } while (v4);\n }\n ++a1;\n } while (a1 != v2);\n return v3;\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n unsigned int *v2;\n unsigned int v3;\n unsigned int v4;\n if (a2 <= 0) return 0LL;\n v2 = &a1[a2];\n v3 = 0;\n do {\n v4 = -*a1;\n if ((int)*a1 > 0) v4 = *a1;\n if (*a1) {\n do {\n v3 += v4 % 10;\n v4 /= 10u;\n } while (v4);\n }\n ++a1;\n } while (a1 != v2);\n return v3;\n}" + }, + { + "index": 399, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "void func0(const int test_tup1[], const int test_tup2[], int res[], int size) {\n for (int i = 0; i < size; i++) {\n res[i] = test_tup1[i] ^ test_tup2[i];\n }\n}", + "test": "int main() {\n\n int size = 4;\n\n int result[4];\n\n\n\n int test_tup1[4] = {10, 4, 6, 9};\n\n int test_tup2[4] = {5, 2, 3, 3};\n\n int expected1[4] = {15, 6, 5, 10};\n\n func0(test_tup1, test_tup2, result, size);\n\n for (int i = 0; i < size; i++) {\n\n assert(result[i] == expected1[i]);\n\n }\n\n\n\n int test_tup3[4] = {11, 5, 7, 10};\n\n int test_tup4[4] = {6, 3, 4, 4};\n\n int expected2[4] = {13, 6, 3, 14};\n\n func0(test_tup3, test_tup4, result, size);\n\n for (int i = 0; i < size; i++) {\n\n assert(result[i] == expected2[i]);\n\n }\n\n\n\n int test_tup5[4] = {12, 6, 8, 11};\n\n int test_tup6[4] = {7, 4, 5, 6};\n\n int expected3[4] = {11, 2, 13, 13};\n\n func0(test_tup5, test_tup6, result, size);\n\n for (int i = 0; i < size; i++) {\n\n assert(result[i] == expected3[i]);\n\n }\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %ecx,-0x2c(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11d1 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%ecx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rsi\nmov -0x28(%rbp),%rax\nadd %rsi,%rax\nxor %ecx,%edx\nmov %edx,(%rax)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 1189 \npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_28], rdx\nmov [rbp+var_2C], ecx\nmov [rbp+var_4], 0\njmp short loc_11D1\nloc_1189:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov ecx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rsi, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rsi\nxor edx, ecx\nmov [rax], edx\nadd [rbp+var_4], 1\nloc_11D1:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_2C]\njl short loc_1189\nnop\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+28h] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a4 )\n break;\n *(_DWORD *)(4LL * (int)i + a3) = *(_DWORD *)(4LL * (int)i + a1) ^ *(_DWORD *)(4LL * (int)i + a2);\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_28], rdx\nmov [rbp+var_2C], ecx\nmov [rbp+var_4], 0\njmp short loc_11D1\nloc_1189:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov ecx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rsi, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rsi\nxor edx, ecx\nmov [rax], edx\nadd [rbp+var_4], 1\nloc_11D1:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_2C]\njl short loc_1189\nnop\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+28h] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a4 )\n break;\n *(_DWORD *)(4LL * (int)i + a3) = *(_DWORD *)(4LL * (int)i + a1) ^ *(_DWORD *)(4LL * (int)i + a2);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, long long a3, int a4) {\n long long result;\n unsigned int i;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a4) break;\n *(uint32_t *)(4LL * (int)i + a3) =\n *(uint32_t *)(4LL * (int)i + a1) ^ *(uint32_t *)(4LL * (int)i + a2);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, long long a3, int a4) {\n long long result;\n unsigned int i;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a4) break;\n *(uint32_t *)(4LL * (int)i + a3) =\n *(uint32_t *)(4LL * (int)i + a1) ^ *(uint32_t *)(4LL * (int)i + a2);\n }\n return result;\n}" + }, + { + "index": 399, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "void func0(const int test_tup1[], const int test_tup2[], int res[], int size) {\n for (int i = 0; i < size; i++) {\n res[i] = test_tup1[i] ^ test_tup2[i];\n }\n}", + "test": "int main() {\n\n int size = 4;\n\n int result[4];\n\n\n\n int test_tup1[4] = {10, 4, 6, 9};\n\n int test_tup2[4] = {5, 2, 3, 3};\n\n int expected1[4] = {15, 6, 5, 10};\n\n func0(test_tup1, test_tup2, result, size);\n\n for (int i = 0; i < size; i++) {\n\n assert(result[i] == expected1[i]);\n\n }\n\n\n\n int test_tup3[4] = {11, 5, 7, 10};\n\n int test_tup4[4] = {6, 3, 4, 4};\n\n int expected2[4] = {13, 6, 3, 14};\n\n func0(test_tup3, test_tup4, result, size);\n\n for (int i = 0; i < size; i++) {\n\n assert(result[i] == expected2[i]);\n\n }\n\n\n\n int test_tup5[4] = {12, 6, 8, 11};\n\n int test_tup6[4] = {7, 4, 5, 6};\n\n int expected3[4] = {11, 2, 13, 13};\n\n func0(test_tup5, test_tup6, result, size);\n\n for (int i = 0; i < size; i++) {\n\n assert(result[i] == expected3[i]);\n\n }\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %ecx,%ecx\njle 118f \nlea -0x1(%rcx),%r8d\nmov $0x0,%eax\nmov (%rdi,%rax,4),%ecx\nxor (%rsi,%rax,4),%ecx\nmov %ecx,(%rdx,%rax,4)\nmov %rax,%rcx\nadd $0x1,%rax\ncmp %r8,%rcx\njne 117a \nretq\n", + "ida_asm": "func0:\nendbr64\ntest ecx, ecx\njle short locret_1193\nmovsxd rcx, ecx\nlea r8, ds:0[rcx*4]\nmov eax, 0\nloc_1181:\nmov ecx, [rdi+rax]\nxor ecx, [rsi+rax]\nmov [rdx+rax], ecx\nadd rax, 4\ncmp rax, r8\njnz short loc_1181\nlocret_1193:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 v4; // rax\n\n if ( a4 > 0 )\n {\n v4 = 0LL;\n do\n {\n *(_DWORD *)(a3 + v4) = *(_DWORD *)(a2 + v4) ^ *(_DWORD *)(a1 + v4);\n v4 += 4LL;\n }\n while ( v4 != 4LL * a4 );\n }\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest ecx, ecx\njle short locret_1193\nmovsxd rcx, ecx\nlea r8, ds:0[rcx*4]\nmov eax, 0\nloc_1181:\nmov ecx, [rdi+rax]\nxor ecx, [rsi+rax]\nmov [rdx+rax], ecx\nadd rax, 4\ncmp rax, r8\njnz short loc_1181\nlocret_1193:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1169(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 v4; // rax\n\n if ( a4 > 0 )\n {\n v4 = 0LL;\n do\n {\n *(_DWORD *)(a3 + v4) = *(_DWORD *)(a2 + v4) ^ *(_DWORD *)(a1 + v4);\n v4 += 4LL;\n }\n while ( v4 != 4LL * a4 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1169(long long a1, long long a2, long long a3, int a4) {\n long long v4;\n if (a4 > 0) {\n v4 = 0LL;\n do {\n *(uint32_t *)(a3 + v4) = *(uint32_t *)(a2 + v4) ^ *(uint32_t *)(a1 + v4);\n v4 += 4LL;\n } while (v4 != 4LL * a4);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, long long a2, long long a3, int a4) {\n long long v4;\n if (a4 > 0) {\n v4 = 0LL;\n do {\n *(uint32_t *)(a3 + v4) = *(uint32_t *)(a2 + v4) ^ *(uint32_t *)(a1 + v4);\n v4 += 4LL;\n } while (v4 != 4LL * a4);\n }\n}" + }, + { + "index": 400, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nint cmp(const void *a, const void *b) {\n\n int *pair_a = (int *)a;\n\n int *pair_b = (int *)b;\n\n if(pair_a[0] != pair_b[0])\n\n return pair_a[0] - pair_b[0];\n\n return pair_a[1] - pair_b[1];\n\n}\n\n\n\n", + "func": "int func0(int test_list[][2], int n) {\n for (int i = 0; i < n; i++) {\n if (test_list[i][0] > test_list[i][1]) {\n int temp = test_list[i][0];\n test_list[i][0] = test_list[i][1];\n test_list[i][1] = temp;\n }\n }\n qsort(test_list, n, sizeof(test_list[0]), cmp);\n if (n == 0) return 0;\n int res = 1;\n for (int i = 1; i < n; i++) {\n if (test_list[i][0] != test_list[i - 1][0] ||\n test_list[i][1] != test_list[i - 1][1]) {\n res++;\n }\n }\n return res;\n}", + "test": "int main() {\n\n int test1[][2] = {{3,4}, {1,2}, {4,3}, {5,6}};\n\n assert(func0(test1, 4) == 3);\n\n \n\n int test2[][2] = {{4,15}, {2,3}, {5,4}, {6,7}};\n\n assert(func0(test2, 4) == 4);\n\n \n\n int test3[][2] = {{5,16}, {2,3}, {6,5}, {6,9}};\n\n assert(func0(test3, 4) == 4);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x10(%rbp)\njmpq 129a \nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov 0x4(%rax),%eax\ncmp %eax,%edx\njle 1296 \nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x4(%rbp)\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0x10(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmov 0x4(%rax),%eax\nmov %eax,(%rdx)\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0x4(%rbp),%eax\nmov %eax,0x4(%rdx)\naddl $0x1,-0x10(%rbp)\nmov -0x10(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1204 \nmov -0x1c(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x18(%rbp),%rax\nlea -0x12e(%rip),%rcx\nmov $0x8,%edx\nmov %rax,%rdi\ncallq 1070 \ncmpl $0x0,-0x1c(%rbp)\njne 12d4 \nmov $0x0,%eax\njmpq 1359 \nmovl $0x1,-0xc(%rbp)\nmovl $0x1,-0x8(%rbp)\njmp 134e \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x8(%rbp),%eax\ncltq\nshl $0x3,%rax\nlea -0x8(%rax),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 1346 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov 0x4(%rax),%edx\nmov -0x8(%rbp),%eax\ncltq\nshl $0x3,%rax\nlea -0x8(%rax),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov 0x4(%rax),%eax\ncmp %eax,%edx\nje 134a \naddl $0x1,-0xc(%rbp)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 12e4 \nmov -0xc(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+base], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_10], 0\njmp loc_1298\nloc_1202:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rax, rcx\nmov eax, [rax+4]\ncmp edx, eax\njle short loc_1294\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+base]\nadd rdx, rcx\nmov eax, [rax+4]\nmov [rdx], eax\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx+4], eax\nloc_1294:\nadd [rbp+var_10], 1\nloc_1298:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_1C]\njl loc_1202\nmov eax, [rbp+var_1C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, cmp\nmov rcx, rdx; compar\nmov edx, 8; size\nmov rdi, rax; base\ncall _qsort\ncmp [rbp+var_1C], 0\njnz short loc_12D5\nmov eax, 0\njmp locret_135A\nloc_12D5:\nmov [rbp+var_C], 1\nmov [rbp+var_8], 1\njmp short loc_134F\nloc_12E5:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nshl rax, 3\nlea rcx, [rax-8]\nmov rax, [rbp+base]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_1347\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rax+4]\nmov eax, [rbp+var_8]\ncdqe\nshl rax, 3\nlea rcx, [rax-8]\nmov rax, [rbp+base]\nadd rax, rcx\nmov eax, [rax+4]\ncmp edx, eax\njz short loc_134B\nloc_1347:\nadd [rbp+var_C], 1\nloc_134B:\nadd [rbp+var_8], 1\nloc_134F:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_12E5\nmov eax, [rbp+var_C]\nlocret_135A:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n int i; // [rsp+10h] [rbp-10h]\n unsigned int v4; // [rsp+14h] [rbp-Ch]\n int j; // [rsp+18h] [rbp-8h]\n int v6; // [rsp+1Ch] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n if ( a1[2 * i] > a1[2 * i + 1] )\n {\n v6 = a1[2 * i];\n a1[2 * i] = a1[2 * i + 1];\n a1[2 * i + 1] = v6;\n }\n }\n qsort(a1, a2, 8uLL, cmp);\n if ( !a2 )\n return 0LL;\n v4 = 1;\n for ( j = 1; j < a2; ++j )\n {\n if ( a1[2 * j] != a1[2 * j - 2] || a1[2 * j + 1] != a1[2 * j - 1] )\n ++v4;\n }\n return v4;\n}", + "ida_strip_asm": "sub_11E3:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+base], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_10], 0\njmp loc_1298\nloc_1202:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rax, rcx\nmov eax, [rax+4]\ncmp edx, eax\njle short loc_1294\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+base]\nadd rdx, rcx\nmov eax, [rax+4]\nmov [rdx], eax\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx+4], eax\nloc_1294:\nadd [rbp+var_10], 1\nloc_1298:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_1C]\njl loc_1202\nmov eax, [rbp+var_1C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 8; size\nmov rdi, rax; base\ncall _qsort\ncmp [rbp+var_1C], 0\njnz short loc_12D5\nmov eax, 0\njmp locret_135A\nloc_12D5:\nmov [rbp+var_C], 1\nmov [rbp+var_8], 1\njmp short loc_134F\nloc_12E5:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nshl rax, 3\nlea rcx, [rax-8]\nmov rax, [rbp+base]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_1347\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rax+4]\nmov eax, [rbp+var_8]\ncdqe\nshl rax, 3\nlea rcx, [rax-8]\nmov rax, [rbp+base]\nadd rax, rcx\nmov eax, [rax+4]\ncmp edx, eax\njz short loc_134B\nloc_1347:\nadd [rbp+var_C], 1\nloc_134B:\nadd [rbp+var_8], 1\nloc_134F:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_12E5\nmov eax, [rbp+var_C]\nlocret_135A:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11E3(_DWORD *a1, int a2)\n{\n int i; // [rsp+10h] [rbp-10h]\n unsigned int v4; // [rsp+14h] [rbp-Ch]\n int j; // [rsp+18h] [rbp-8h]\n int v6; // [rsp+1Ch] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n if ( a1[2 * i] > a1[2 * i + 1] )\n {\n v6 = a1[2 * i];\n a1[2 * i] = a1[2 * i + 1];\n a1[2 * i + 1] = v6;\n }\n }\n qsort(a1, a2, 8uLL, compar);\n if ( !a2 )\n return 0LL;\n v4 = 1;\n for ( j = 1; j < a2; ++j )\n {\n if ( a1[2 * j] != a1[2 * j - 2] || a1[2 * j + 1] != a1[2 * j - 1] )\n ++v4;\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11E3(uint32_t *a1, int a2) {\n int i;\n unsigned int v4;\n int j;\n int v6;\n for (i = 0; i < a2; ++i) {\n if (a1[2 * i] > a1[2 * i + 1]) {\n v6 = a1[2 * i];\n a1[2 * i] = a1[2 * i + 1];\n a1[2 * i + 1] = v6;\n }\n }\n qsort(a1, a2, 8uLL, compar);\n if (!a2) return 0LL;\n v4 = 1;\n for (j = 1; j < a2; ++j) {\n if (a1[2 * j] != a1[2 * j - 2] || a1[2 * j + 1] != a1[2 * j - 1]) ++v4;\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n int i;\n unsigned int v4;\n int j;\n int v6;\n for (i = 0; i < a2; ++i) {\n if (a1[2 * i] > a1[2 * i + 1]) {\n v6 = a1[2 * i];\n a1[2 * i] = a1[2 * i + 1];\n a1[2 * i + 1] = v6;\n }\n }\n qsort(a1, a2, 8uLL, cmp);\n if (!a2) return 0LL;\n v4 = 1;\n for (j = 1; j < a2; ++j) {\n if (a1[2 * j] != a1[2 * j - 2] || a1[2 * j + 1] != a1[2 * j - 1]) ++v4;\n }\n return v4;\n}" + }, + { + "index": 400, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nint cmp(const void *a, const void *b) {\n\n int *pair_a = (int *)a;\n\n int *pair_b = (int *)b;\n\n if(pair_a[0] != pair_b[0])\n\n return pair_a[0] - pair_b[0];\n\n return pair_a[1] - pair_b[1];\n\n}\n\n\n\n", + "func": "int func0(int test_list[][2], int n) {\n for (int i = 0; i < n; i++) {\n if (test_list[i][0] > test_list[i][1]) {\n int temp = test_list[i][0];\n test_list[i][0] = test_list[i][1];\n test_list[i][1] = temp;\n }\n }\n qsort(test_list, n, sizeof(test_list[0]), cmp);\n if (n == 0) return 0;\n int res = 1;\n for (int i = 1; i < n; i++) {\n if (test_list[i][0] != test_list[i - 1][0] ||\n test_list[i][1] != test_list[i - 1][1]) {\n res++;\n }\n }\n return res;\n}", + "test": "int main() {\n\n int test1[][2] = {{3,4}, {1,2}, {4,3}, {5,6}};\n\n assert(func0(test1, 4) == 3);\n\n \n\n int test2[][2] = {{4,15}, {2,3}, {5,4}, {6,7}};\n\n assert(func0(test2, 4) == 4);\n\n \n\n int test3[][2] = {{5,16}, {2,3}, {6,5}, {6,9}};\n\n assert(func0(test3, 4) == 4);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbp\nmov %esi,%ebx\ntest %esi,%esi\njle 11d8 \nmov %rdi,%rax\nlea -0x1(%rsi),%edx\nlea 0x8(%rdi,%rdx,8),%rsi\njmp 11c8 \nadd $0x8,%rax\ncmp %rsi,%rax\nje 121a \nmov (%rax),%edx\nmov 0x4(%rax),%ecx\ncmp %ecx,%edx\njle 11bf \nmov %ecx,(%rax)\nmov %edx,0x4(%rax)\njmp 11bf \nmovslq %esi,%rsi\nlea -0x59(%rip),%rcx\nmov $0x8,%edx\ncallq 1070 \ntest %ebx,%ebx\nsetne %dl\nmovzbl %dl,%edx\nmov %edx,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nadd $0x1,%edx\nadd $0x8,%rax\ncmp %rcx,%rax\nje 11f4 \nmov (%rax),%edi\ncmp %edi,0x8(%rax)\njne 11fd \nmov 0x4(%rax),%ebx\ncmp %ebx,0xc(%rax)\njne 11fd \njmp 1200 \nmovslq %ebx,%rsi\nlea -0x9b(%rip),%rcx\nmov $0x8,%edx\nmov %rbp,%rdi\ncallq 1070 \ncmp $0x1,%ebx\njle 1248 \nmov %rbp,%rax\nlea -0x2(%rbx),%edx\nlea 0x8(%rbp,%rdx,8),%rcx\nmov $0x1,%edx\njmp 1209 \nmov $0x1,%edx\njmp 11f4 \n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov ebx, esi\ntest esi, esi\njle short loc_11D7\nmov rax, rdi\nmovsxd rdx, esi\nlea rsi, [rdi+rdx*8]\njmp short loc_11C7\nloc_11BE:\nadd rax, 8\ncmp rax, rsi\njz short loc_121C\nloc_11C7:\nmov edx, [rax]\nmov ecx, [rax+4]\ncmp edx, ecx\njle short loc_11BE\nmov [rax], ecx\nmov [rax+4], edx\njmp short loc_11BE\nloc_11D7:\nmovsxd rsi, esi; nmemb\nlea rcx, cmp; compar\nmov edx, 8; size\ncall _qsort\ntest ebx, ebx\njnz short loc_1233\nloc_11EF:\nmov eax, ebx\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_11F8:\nadd ebx, 1\nloc_11FB:\nadd rax, 8\ncmp rax, rcx\njz short loc_11EF\nloc_1204:\nmov edi, [rax]\ncmp [rax+8], edi\njnz short loc_11F8\nmov edi, [rax+4]\ncmp [rax+0Ch], edi\njnz short loc_11F8\njmp short loc_11FB\nloc_1215:\nmov ebx, 1\njmp short loc_11EF\nloc_121C:\nmovsxd rsi, ebx; nmemb\nlea rcx, cmp; compar\nmov edx, 8; size\nmov rdi, rbp; base\ncall _qsort\nloc_1233:\ncmp ebx, 1\njle short loc_1215\nmov rax, rbp\nlea edx, [rbx-2]\nlea rcx, [rbp+rdx*8+8]\nmov ebx, 1\njmp short loc_1204", + "ida_pseudo": "__int64 __fastcall func0(char *base, int a2)\n{\n int v2; // ebx\n char *v3; // rax\n char *v4; // rsi\n int v5; // edx\n int v6; // ecx\n char *v8; // rax\n char *v9; // rcx\n\n v2 = a2;\n if ( a2 <= 0 )\n {\n qsort(base, a2, 8uLL, cmp);\n if ( !a2 )\n return (unsigned int)v2;\n }\n else\n {\n v3 = base;\n v4 = &base[8 * a2];\n do\n {\n v5 = *(_DWORD *)v3;\n v6 = *((_DWORD *)v3 + 1);\n if ( *(_DWORD *)v3 > v6 )\n {\n *(_DWORD *)v3 = v6;\n *((_DWORD *)v3 + 1) = v5;\n }\n v3 += 8;\n }\n while ( v3 != v4 );\n qsort(base, v2, 8uLL, cmp);\n }\n if ( v2 <= 1 )\n {\n return 1;\n }\n else\n {\n v8 = base;\n v9 = &base[8 * (v2 - 2) + 8];\n v2 = 1;\n do\n {\n if ( *((_DWORD *)v8 + 2) != *(_DWORD *)v8 || *((_DWORD *)v8 + 3) != *((_DWORD *)v8 + 1) )\n ++v2;\n v8 += 8;\n }\n while ( v8 != v9 );\n }\n return (unsigned int)v2;\n}", + "ida_strip_asm": "sub_119F:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov ebx, esi\ntest esi, esi\njle short loc_11D7\nmov rax, rdi\nmovsxd rdx, esi\nlea rsi, [rdi+rdx*8]\njmp short loc_11C7\nloc_11BE:\nadd rax, 8\ncmp rax, rsi\njz short loc_121C\nloc_11C7:\nmov edx, [rax]\nmov ecx, [rax+4]\ncmp edx, ecx\njle short loc_11BE\nmov [rax], ecx\nmov [rax+4], edx\njmp short loc_11BE\nloc_11D7:\nmovsxd rsi, esi; nmemb\nlea rcx, compar; compar\nmov edx, 8; size\ncall _qsort\ntest ebx, ebx\njnz short loc_1233\nloc_11EF:\nmov eax, ebx\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_11F8:\nadd ebx, 1\nloc_11FB:\nadd rax, 8\ncmp rax, rcx\njz short loc_11EF\nloc_1204:\nmov edi, [rax]\ncmp [rax+8], edi\njnz short loc_11F8\nmov edi, [rax+4]\ncmp [rax+0Ch], edi\njnz short loc_11F8\njmp short loc_11FB\nloc_1215:\nmov ebx, 1\njmp short loc_11EF\nloc_121C:\nmovsxd rsi, ebx; nmemb\nlea rcx, compar; compar\nmov edx, 8; size\nmov rdi, rbp; base\ncall _qsort\nloc_1233:\ncmp ebx, 1\njle short loc_1215\nmov rax, rbp\nlea edx, [rbx-2]\nlea rcx, [rbp+rdx*8+8]\nmov ebx, 1\njmp short loc_1204", + "ida_strip_pseudo": "__int64 __fastcall sub_119F(char *base, int a2)\n{\n int v2; // ebx\n char *v3; // rax\n char *v4; // rsi\n int v5; // edx\n int v6; // ecx\n char *v8; // rax\n char *v9; // rcx\n\n v2 = a2;\n if ( a2 <= 0 )\n {\n qsort(base, a2, 8uLL, compar);\n if ( !a2 )\n return (unsigned int)v2;\n }\n else\n {\n v3 = base;\n v4 = &base[8 * a2];\n do\n {\n v5 = *(_DWORD *)v3;\n v6 = *((_DWORD *)v3 + 1);\n if ( *(_DWORD *)v3 > v6 )\n {\n *(_DWORD *)v3 = v6;\n *((_DWORD *)v3 + 1) = v5;\n }\n v3 += 8;\n }\n while ( v3 != v4 );\n qsort(base, v2, 8uLL, compar);\n }\n if ( v2 <= 1 )\n {\n return 1;\n }\n else\n {\n v8 = base;\n v9 = &base[8 * (v2 - 2) + 8];\n v2 = 1;\n do\n {\n if ( *((_DWORD *)v8 + 2) != *(_DWORD *)v8 || *((_DWORD *)v8 + 3) != *((_DWORD *)v8 + 1) )\n ++v2;\n v8 += 8;\n }\n while ( v8 != v9 );\n }\n return (unsigned int)v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_119F(char *base, int a2) {\n int v2;\n char *v3;\n char *v4;\n int v5;\n int v6;\n char *v8;\n char *v9;\n v2 = a2;\n if (a2 <= 0) {\n qsort(base, a2, 8uLL, compar);\n if (!a2) return (unsigned int)v2;\n } else {\n v3 = base;\n v4 = &base[8 * a2];\n do {\n v5 = *(uint32_t *)v3;\n v6 = *((uint32_t *)v3 + 1);\n if (*(uint32_t *)v3 > v6) {\n *(uint32_t *)v3 = v6;\n *((uint32_t *)v3 + 1) = v5;\n }\n v3 += 8;\n } while (v3 != v4);\n qsort(base, v2, 8uLL, compar);\n }\n if (v2 <= 1) {\n return 1;\n } else {\n v8 = base;\n v9 = &base[8 * (v2 - 2) + 8];\n v2 = 1;\n do {\n if (*((uint32_t *)v8 + 2) != *(uint32_t *)v8 ||\n *((uint32_t *)v8 + 3) != *((uint32_t *)v8 + 1))\n ++v2;\n v8 += 8;\n } while (v8 != v9);\n }\n return (unsigned int)v2;\n}", + "ida_pseudo_norm": "long long func0(char *base, int a2) {\n int v2;\n char *v3;\n char *v4;\n int v5;\n int v6;\n char *v8;\n char *v9;\n v2 = a2;\n if (a2 <= 0) {\n qsort(base, a2, 8uLL, cmp);\n if (!a2) return (unsigned int)v2;\n } else {\n v3 = base;\n v4 = &base[8 * a2];\n do {\n v5 = *(uint32_t *)v3;\n v6 = *((uint32_t *)v3 + 1);\n if (*(uint32_t *)v3 > v6) {\n *(uint32_t *)v3 = v6;\n *((uint32_t *)v3 + 1) = v5;\n }\n v3 += 8;\n } while (v3 != v4);\n qsort(base, v2, 8uLL, cmp);\n }\n if (v2 <= 1) {\n return 1;\n } else {\n v8 = base;\n v9 = &base[8 * (v2 - 2) + 8];\n v2 = 1;\n do {\n if (*((uint32_t *)v8 + 2) != *(uint32_t *)v8 ||\n *((uint32_t *)v8 + 3) != *((uint32_t *)v8 + 1))\n ++v2;\n v8 += 8;\n } while (v8 != v9);\n }\n return (unsigned int)v2;\n}" + }, + { + "index": 400, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nint cmp(const void *a, const void *b) {\n\n int *pair_a = (int *)a;\n\n int *pair_b = (int *)b;\n\n if(pair_a[0] != pair_b[0])\n\n return pair_a[0] - pair_b[0];\n\n return pair_a[1] - pair_b[1];\n\n}\n\n\n\n", + "func": "int func0(int test_list[][2], int n) {\n for (int i = 0; i < n; i++) {\n if (test_list[i][0] > test_list[i][1]) {\n int temp = test_list[i][0];\n test_list[i][0] = test_list[i][1];\n test_list[i][1] = temp;\n }\n }\n qsort(test_list, n, sizeof(test_list[0]), cmp);\n if (n == 0) return 0;\n int res = 1;\n for (int i = 1; i < n; i++) {\n if (test_list[i][0] != test_list[i - 1][0] ||\n test_list[i][1] != test_list[i - 1][1]) {\n res++;\n }\n }\n return res;\n}", + "test": "int main() {\n\n int test1[][2] = {{3,4}, {1,2}, {4,3}, {5,6}};\n\n assert(func0(test1, 4) == 3);\n\n \n\n int test2[][2] = {{4,15}, {2,3}, {5,4}, {6,7}};\n\n assert(func0(test2, 4) == 4);\n\n \n\n int test3[][2] = {{5,16}, {2,3}, {6,5}, {6,9}};\n\n assert(func0(test3, 4) == 4);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmovslq %esi,%r8\npush %r12\npush %rbp\nmov %rdi,%rbp\npush %rbx\nmov %r8,%rbx\ntest %r8d,%r8d\njle 13d8 \nlea -0x1(%r8),%edx\nlea 0x8(%rdi),%r12\nmov %rdi,%rax\nlea (%r12,%rdx,8),%rsi\nnopl 0x0(%rax)\nmov (%rax),%edx\nmov 0x4(%rax),%ecx\ncmp %ecx,%edx\njle 136e \nmov %ecx,(%rax)\nmov %edx,0x4(%rax)\nadd $0x8,%rax\ncmp %rsi,%rax\njne 1360 \nlea -0x6e(%rip),%rcx\nmov $0x8,%edx\nmov %r8,%rsi\nmov %rbp,%rdi\ncallq 1070 \ncmp $0x1,%ebx\nje 13f8 \nlea -0x2(%rbx),%eax\nmov %rbp,%rdi\nlea (%r12,%rax,8),%rdx\nmov $0x1,%eax\njmp 13b4 \nnopl 0x0(%rax)\nadd $0x8,%rdi\nadd $0x1,%eax\ncmp %rdx,%rdi\nje 13cc \nmov (%rdi),%ebx\ncmp %ebx,0x8(%rdi)\njne 13a8 \nmov 0x4(%rdi),%esi\ncmp %esi,0xc(%rdi)\njne 13a8 \nadd $0x8,%rdi\ncmp %rdx,%rdi\njne 13b4 \npop %rbx\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax)\nlea -0xcf(%rip),%rcx\nmov $0x8,%edx\nmov %r8,%rsi\ncallq 1070 \nxor %eax,%eax\ntest %ebx,%ebx\npop %rbx\nsetne %al\npop %rbp\npop %r12\nretq\nmov $0x1,%eax\njmp 13cc \n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nmov rbx, rdi\nmovsxd rdi, esi\nmov rbp, rdi\nsub rsp, 8\ntest edi, edi\njle loc_1380\nlea rsi, [rbx+rdi*8]\nmov rax, rbx\nnop word ptr [rax+rax+00h]\nloc_12F8:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd ecx, xmm0\nmovd edx, xmm1\ncmp ecx, edx\njle short loc_1316\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_1316:\nadd rax, 8\ncmp rax, rsi\njnz short loc_12F8\nmov rsi, rdi; nmemb\nlea rcx, cmp; compar\nmov edx, 8; size\nmov rdi, rbx; base\ncall _qsort\ncmp ebp, 1\njz short loc_13A7\nlea ecx, [rbp-2]\nmov edx, [rbx]\nlea rax, [rbx+4]\nlea rdi, [rbx+rcx*8+0Ch]\nmov ecx, 1\njmp short loc_135C\nloc_1350:\nadd rax, 8\nadd ecx, 1\ncmp rax, rdi\njz short loc_1375\nloc_135C:\nmov esi, edx\nmov edx, [rax+4]\ncmp edx, esi\njnz short loc_1350\nmov ebx, [rax]\ncmp [rax+8], ebx\njnz short loc_1350\nadd rax, 8\ncmp rax, rdi\njnz short loc_135C\nloc_1375:\nadd rsp, 8\nmov eax, ecx\npop rbx\npop rbp\nretn\nloc_1380:\nlea rcx, cmp; compar\nmov rsi, rdi; nmemb\nmov edx, 8; size\nmov rdi, rbx; base\ncall _qsort\nxor ecx, ecx\ntest ebp, ebp\nsetnz cl\nadd rsp, 8\nmov eax, ecx\npop rbx\npop rbp\nretn\nloc_13A7:\nmov ecx, 1\njmp short loc_1375", + "ida_pseudo": "__int64 __fastcall func0(__m128i *base, int a2)\n{\n size_t v3; // rdi\n __m128i *v5; // rsi\n __m128i *v6; // rax\n __m128i v7; // xmm0\n __int32 v8; // edx\n char *v9; // rax\n char *v10; // rdi\n unsigned int v11; // ecx\n __int32 v12; // esi\n\n v3 = a2;\n if ( a2 <= 0 )\n {\n qsort(base, a2, 8uLL, cmp);\n return a2 != 0;\n }\n else\n {\n v5 = (__m128i *)((char *)base + 8 * a2);\n v6 = base;\n do\n {\n v7 = _mm_loadl_epi64(v6);\n if ( _mm_cvtsi128_si32(v7) > _mm_cvtsi128_si32(_mm_shuffle_epi32(v7, 229)) )\n v6->m128i_i64[0] = _mm_shuffle_epi32(v7, 225).m128i_u64[0];\n v6 = (__m128i *)((char *)v6 + 8);\n }\n while ( v6 != v5 );\n qsort(base, v3, 8uLL, cmp);\n if ( a2 == 1 )\n {\n return 1;\n }\n else\n {\n v8 = base->m128i_i32[0];\n v9 = &base->m128i_i8[4];\n v10 = &base->m128i_i8[8 * (a2 - 2) + 12];\n v11 = 1;\n do\n {\n while ( 1 )\n {\n v12 = v8;\n v8 = *((_DWORD *)v9 + 1);\n if ( v8 == v12 && *((_DWORD *)v9 + 2) == *(_DWORD *)v9 )\n break;\n v9 += 8;\n ++v11;\n if ( v9 == v10 )\n return v11;\n }\n v9 += 8;\n }\n while ( v9 != v10 );\n }\n return v11;\n }\n}", + "ida_strip_asm": "sub_12D0:\nendbr64\npush rbp\npush rbx\nmov rbx, rdi\nmovsxd rdi, esi\nmov rbp, rdi\nsub rsp, 8\ntest edi, edi\njle loc_1380\nlea rsi, [rbx+rdi*8]\nmov rax, rbx\nnop word ptr [rax+rax+00h]\nloc_12F8:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd ecx, xmm0\nmovd edx, xmm1\ncmp ecx, edx\njle short loc_1316\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_1316:\nadd rax, 8\ncmp rax, rsi\njnz short loc_12F8\nmov rsi, rdi; nmemb\nlea rcx, compar; compar\nmov edx, 8; size\nmov rdi, rbx; base\ncall _qsort\ncmp ebp, 1\njz short loc_13A7\nlea ecx, [rbp-2]\nmov edx, [rbx]\nlea rax, [rbx+4]\nlea rdi, [rbx+rcx*8+0Ch]\nmov ecx, 1\njmp short loc_135C\nloc_1350:\nadd rax, 8\nadd ecx, 1\ncmp rax, rdi\njz short loc_1375\nloc_135C:\nmov esi, edx\nmov edx, [rax+4]\ncmp edx, esi\njnz short loc_1350\nmov ebx, [rax]\ncmp [rax+8], ebx\njnz short loc_1350\nadd rax, 8\ncmp rax, rdi\njnz short loc_135C\nloc_1375:\nadd rsp, 8\nmov eax, ecx\npop rbx\npop rbp\nretn\nloc_1380:\nlea rcx, compar; compar\nmov rsi, rdi; nmemb\nmov edx, 8; size\nmov rdi, rbx; base\ncall _qsort\nxor ecx, ecx\ntest ebp, ebp\nsetnz cl\nadd rsp, 8\nmov eax, ecx\npop rbx\npop rbp\nretn\nloc_13A7:\nmov ecx, 1\njmp short loc_1375", + "ida_strip_pseudo": "__int64 __fastcall sub_12D0(__m128i *base, int a2)\n{\n size_t v3; // rdi\n __m128i *v5; // rsi\n __m128i *v6; // rax\n __m128i v7; // xmm0\n __int32 v8; // edx\n char *v9; // rax\n char *v10; // rdi\n unsigned int v11; // ecx\n __int32 v12; // esi\n\n v3 = a2;\n if ( a2 <= 0 )\n {\n qsort(base, a2, 8uLL, compar);\n return a2 != 0;\n }\n else\n {\n v5 = (__m128i *)((char *)base + 8 * a2);\n v6 = base;\n do\n {\n v7 = _mm_loadl_epi64(v6);\n if ( _mm_cvtsi128_si32(v7) > _mm_cvtsi128_si32(_mm_shuffle_epi32(v7, 229)) )\n v6->m128i_i64[0] = _mm_shuffle_epi32(v7, 225).m128i_u64[0];\n v6 = (__m128i *)((char *)v6 + 8);\n }\n while ( v6 != v5 );\n qsort(base, v3, 8uLL, compar);\n if ( a2 == 1 )\n {\n return 1;\n }\n else\n {\n v8 = base->m128i_i32[0];\n v9 = &base->m128i_i8[4];\n v10 = &base->m128i_i8[8 * (a2 - 2) + 12];\n v11 = 1;\n do\n {\n while ( 1 )\n {\n v12 = v8;\n v8 = *((_DWORD *)v9 + 1);\n if ( v8 == v12 && *((_DWORD *)v9 + 2) == *(_DWORD *)v9 )\n break;\n v9 += 8;\n ++v11;\n if ( v9 == v10 )\n return v11;\n }\n v9 += 8;\n }\n while ( v9 != v10 );\n }\n return v11;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12D0(__m128i *base, int a2) {\n unsigned int v3;\n __m128i *v5;\n __m128i *v6;\n __m128i v7;\n int v8;\n char *v9;\n char *v10;\n unsigned int v11;\n int v12;\n v3 = a2;\n if (a2 <= 0) {\n qsort(base, a2, 8uLL, compar);\n return a2 != 0;\n } else {\n v5 = (__m128i *)((char *)base + 8 * a2);\n v6 = base;\n do {\n v7 = _mm_loadl_epi64(v6);\n if (_mm_cvtsi128_si32(v7) > _mm_cvtsi128_si32(_mm_shuffle_epi32(v7, 229)))\n v6->m128i_i64[0] = _mm_shuffle_epi32(v7, 225).m128i_u64[0];\n v6 = (__m128i *)((char *)v6 + 8);\n } while (v6 != v5);\n qsort(base, v3, 8uLL, compar);\n if (a2 == 1) {\n return 1;\n } else {\n v8 = base->m128i_i32[0];\n v9 = &base->m128i_i8[4];\n v10 = &base->m128i_i8[8 * (a2 - 2) + 12];\n v11 = 1;\n do {\n while (1) {\n v12 = v8;\n v8 = *((uint32_t *)v9 + 1);\n if (v8 == v12 && *((uint32_t *)v9 + 2) == *(uint32_t *)v9) break;\n v9 += 8;\n ++v11;\n if (v9 == v10) return v11;\n }\n v9 += 8;\n } while (v9 != v10);\n }\n return v11;\n }\n}", + "ida_pseudo_norm": "long long func0(__m128i *base, int a2) {\n unsigned int v3;\n __m128i *v5;\n __m128i *v6;\n __m128i v7;\n int v8;\n char *v9;\n char *v10;\n unsigned int v11;\n int v12;\n v3 = a2;\n if (a2 <= 0) {\n qsort(base, a2, 8uLL, cmp);\n return a2 != 0;\n } else {\n v5 = (__m128i *)((char *)base + 8 * a2);\n v6 = base;\n do {\n v7 = _mm_loadl_epi64(v6);\n if (_mm_cvtsi128_si32(v7) > _mm_cvtsi128_si32(_mm_shuffle_epi32(v7, 229)))\n v6->m128i_i64[0] = _mm_shuffle_epi32(v7, 225).m128i_u64[0];\n v6 = (__m128i *)((char *)v6 + 8);\n } while (v6 != v5);\n qsort(base, v3, 8uLL, cmp);\n if (a2 == 1) {\n return 1;\n } else {\n v8 = base->m128i_i32[0];\n v9 = &base->m128i_i8[4];\n v10 = &base->m128i_i8[8 * (a2 - 2) + 12];\n v11 = 1;\n do {\n while (1) {\n v12 = v8;\n v8 = *((uint32_t *)v9 + 1);\n if (v8 == v12 && *((uint32_t *)v9 + 2) == *(uint32_t *)v9) break;\n v9 += 8;\n ++v11;\n if (v9 == v10) return v11;\n }\n v9 += 8;\n } while (v9 != v10);\n }\n return v11;\n }\n}" + }, + { + "index": 400, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nint cmp(const void *a, const void *b) {\n\n int *pair_a = (int *)a;\n\n int *pair_b = (int *)b;\n\n if(pair_a[0] != pair_b[0])\n\n return pair_a[0] - pair_b[0];\n\n return pair_a[1] - pair_b[1];\n\n}\n\n\n\n", + "func": "int func0(int test_list[][2], int n) {\n for (int i = 0; i < n; i++) {\n if (test_list[i][0] > test_list[i][1]) {\n int temp = test_list[i][0];\n test_list[i][0] = test_list[i][1];\n test_list[i][1] = temp;\n }\n }\n qsort(test_list, n, sizeof(test_list[0]), cmp);\n if (n == 0) return 0;\n int res = 1;\n for (int i = 1; i < n; i++) {\n if (test_list[i][0] != test_list[i - 1][0] ||\n test_list[i][1] != test_list[i - 1][1]) {\n res++;\n }\n }\n return res;\n}", + "test": "int main() {\n\n int test1[][2] = {{3,4}, {1,2}, {4,3}, {5,6}};\n\n assert(func0(test1, 4) == 3);\n\n \n\n int test2[][2] = {{4,15}, {2,3}, {5,4}, {6,7}};\n\n assert(func0(test2, 4) == 4);\n\n \n\n int test3[][2] = {{5,16}, {2,3}, {6,5}, {6,9}};\n\n assert(func0(test3, 4) == 4);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmovslq %esi,%r8\nmov %rdi,%rbp\npush %rbx\nmov %r8,%rbx\nsub $0x8,%rsp\ntest %r8d,%r8d\njle 13a8 \nlea -0x1(%r8),%edx\nmov %rdi,%rax\nlea 0x8(%rdi,%rdx,8),%rsi\nnopl 0x0(%rax,%rax,1)\nmov (%rax),%edx\nmov 0x4(%rax),%ecx\ncmp %ecx,%edx\njle 130e \nmov %ecx,(%rax)\nmov %edx,0x4(%rax)\nadd $0x8,%rax\ncmp %rsi,%rax\njne 1300 \nlea -0x6e(%rip),%rcx\nmov $0x8,%edx\nmov %r8,%rsi\nmov %rbp,%rdi\ncallq 1070 \ncmp $0x1,%ebx\nje 13ea \ncmp $0x3,%ebx\njle 13f2 \nlea -0x4(%rbx),%ecx\nmov 0x0(%rbp),%esi\nlea 0x4(%rbp),%rdx\nmov $0x1,%r8d\nand $0xfffffffe,%ecx\nmov $0x1,%eax\nadd $0x3,%ecx\nmov 0x4(%rdx),%edi\ncmp %edi,%esi\nje 13d0 \nadd $0x1,%r8d\nmov 0xc(%rdx),%esi\ncmp %esi,%edi\nje 13e0 \nadd $0x1,%r8d\nadd $0x2,%eax\nadd $0x10,%rdx\ncmp %ecx,%eax\njne 135b \ncltq\njmp 138c \nadd $0x1,%r8d\nadd $0x1,%rax\ncmp %eax,%ebx\njle 13c5 \nmov -0x8(%rbp,%rax,8),%edi\ncmp %edi,0x0(%rbp,%rax,8)\njne 1380 \nmov -0x4(%rbp,%rax,8),%esi\ncmp %esi,0x4(%rbp,%rax,8)\njne 1380 \njmp 1384 \nnopw 0x0(%rax,%rax,1)\nmov %r8,%rsi\nlea -0x102(%rip),%rcx\nmov $0x8,%edx\ncallq 1070 \nxor %r8d,%r8d\ntest %ebx,%ebx\nsetne %r8b\nadd $0x8,%rsp\nmov %r8d,%eax\npop %rbx\npop %rbp\nretq\nmov (%rdx),%esi\ncmp %esi,0x8(%rdx)\njne 1362 \njmp 1366 \nnopl 0x0(%rax)\nmov 0x8(%rdx),%edi\ncmp %edi,0x10(%rdx)\njne 136d \njmp 1371 \nmov $0x1,%r8d\njmp 13c5 \nmov $0x1,%r8d\nmov $0x1,%eax\njmpq 137c \nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nmov rbx, rdi\nmovsxd rdi, esi\nmov rbp, rdi\nsub rsp, 8\ntest edi, edi\njle loc_13E0\nmov rax, rbx\nlea rsi, [rbx+rdi*8]\nnop word ptr [rax+rax+00h]\nloc_12F8:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd ecx, xmm0\nmovd edx, xmm1\ncmp ecx, edx\njle short loc_1316\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_1316:\nadd rax, 8\ncmp rax, rsi\njnz short loc_12F8\nmov rsi, rdi; nmemb\nlea rcx, cmp; compar\nmov edx, 8; size\nmov rdi, rbx; base\ncall _qsort\ncmp ebp, 1\njz loc_1407\ncmp ebp, 3\njle short loc_139C\nlea eax, [rbp-4]\nmov edi, [rbx]\nlea rcx, [rbx+4]\nmov edx, 1\nand eax, 0FFFFFFFEh\nmov esi, 1\nadd eax, 3\njmp short loc_1379\nloc_1360:\nadd edx, 1\nloc_1363:\nmov edi, [rcx+0Ch]\ncmp r8d, edi\njz short loc_1390\nloc_136B:\nadd edx, 1\nloc_136E:\nadd esi, 2\nadd rcx, 10h\ncmp esi, eax\njz short loc_13A6\nloc_1379:\nmov r8d, [rcx+4]\ncmp r8d, edi\njnz short loc_1360\nmov edi, [rcx]\ncmp [rcx+8], edi\njnz short loc_1360\njmp short loc_1363\nloc_1390:\nmov r9d, [rcx+8]\ncmp [rcx+10h], r9d\njnz short loc_136B\njmp short loc_136E\nloc_139C:\nmov edx, 1\nmov eax, 1\nloc_13A6:\ncdqe\njmp short loc_13BB\nloc_13B0:\nadd rax, 1\nadd edx, 1\ncmp ebp, eax\njle short loc_13D6\nloc_13BB:\nmov edi, [rbx+rax*8-8]\ncmp [rbx+rax*8], edi\njnz short loc_13B0\nmov esi, [rbx+rax*8-4]\ncmp [rbx+rax*8+4], esi\njnz short loc_13B0\nadd rax, 1\ncmp ebp, eax\njg short loc_13BB\nloc_13D6:\nadd rsp, 8\nmov eax, edx\npop rbx\npop rbp\nretn\nloc_13E0:\nmov edx, 8; size\nmov rsi, rdi; nmemb\nlea rcx, cmp; compar\nmov rdi, rbx; base\ncall _qsort\nxor edx, edx\ntest ebp, ebp\nsetnz dl\nadd rsp, 8\nmov eax, edx\npop rbx\npop rbp\nretn\nloc_1407:\nmov edx, 1\njmp short loc_13D6", + "ida_pseudo": "__int64 __fastcall func0(__m128i *base, int a2)\n{\n size_t v3; // rdi\n __m128i *v5; // rax\n __m128i *v6; // rsi\n __m128i v7; // xmm0\n __int32 v8; // edi\n __int32 *v9; // rcx\n unsigned int v10; // edx\n int v11; // esi\n __int64 v12; // rax\n __int32 v13; // r8d\n\n v3 = a2;\n if ( a2 <= 0 )\n {\n qsort(base, a2, 8uLL, cmp);\n return a2 != 0;\n }\n else\n {\n v5 = base;\n v6 = (__m128i *)((char *)base + 8 * a2);\n do\n {\n v7 = _mm_loadl_epi64(v5);\n if ( _mm_cvtsi128_si32(v7) > _mm_cvtsi128_si32(_mm_shuffle_epi32(v7, 229)) )\n v5->m128i_i64[0] = _mm_shuffle_epi32(v7, 225).m128i_u64[0];\n v5 = (__m128i *)((char *)v5 + 8);\n }\n while ( v5 != v6 );\n qsort(base, v3, 8uLL, cmp);\n if ( a2 == 1 )\n {\n return 1;\n }\n else\n {\n if ( a2 <= 3 )\n {\n v10 = 1;\n LODWORD(v12) = 1;\n }\n else\n {\n v8 = base->m128i_i32[0];\n v9 = &base->m128i_i32[1];\n v10 = 1;\n v11 = 1;\n LODWORD(v12) = ((a2 - 4) & 0xFFFFFFFE) + 3;\n do\n {\n v13 = v9[1];\n if ( v13 != v8 || v9[2] != *v9 )\n ++v10;\n v8 = v9[3];\n if ( v13 != v8 || v9[4] != v9[2] )\n ++v10;\n v11 += 2;\n v9 += 4;\n }\n while ( v11 != (_DWORD)v12 );\n }\n v12 = (int)v12;\n do\n {\n while ( base->m128i_i32[2 * v12] != base->m128i_i32[2 * v12 - 2]\n || base->m128i_i32[2 * v12 + 1] != base->m128i_i32[2 * v12 - 1] )\n {\n ++v12;\n ++v10;\n if ( a2 <= (int)v12 )\n return v10;\n }\n ++v12;\n }\n while ( a2 > (int)v12 );\n }\n return v10;\n }\n}", + "ida_strip_asm": "sub_12D0:\nendbr64\npush rbp\npush rbx\nmov rbx, rdi\nmovsxd rdi, esi\nmov rbp, rdi\nsub rsp, 8\ntest edi, edi\njle loc_13E0\nmov rax, rbx\nlea rsi, [rbx+rdi*8]\nnop word ptr [rax+rax+00h]\nloc_12F8:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd ecx, xmm0\nmovd edx, xmm1\ncmp ecx, edx\njle short loc_1316\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_1316:\nadd rax, 8\ncmp rax, rsi\njnz short loc_12F8\nmov rsi, rdi; nmemb\nlea rcx, compar; compar\nmov edx, 8; size\nmov rdi, rbx; base\ncall _qsort\ncmp ebp, 1\njz loc_1407\ncmp ebp, 3\njle short loc_139C\nlea eax, [rbp-4]\nmov edi, [rbx]\nlea rcx, [rbx+4]\nmov edx, 1\nand eax, 0FFFFFFFEh\nmov esi, 1\nadd eax, 3\njmp short loc_1379\nloc_1360:\nadd edx, 1\nloc_1363:\nmov edi, [rcx+0Ch]\ncmp r8d, edi\njz short loc_1390\nloc_136B:\nadd edx, 1\nloc_136E:\nadd esi, 2\nadd rcx, 10h\ncmp esi, eax\njz short loc_13A6\nloc_1379:\nmov r8d, [rcx+4]\ncmp r8d, edi\njnz short loc_1360\nmov edi, [rcx]\ncmp [rcx+8], edi\njnz short loc_1360\njmp short loc_1363\nloc_1390:\nmov r9d, [rcx+8]\ncmp [rcx+10h], r9d\njnz short loc_136B\njmp short loc_136E\nloc_139C:\nmov edx, 1\nmov eax, 1\nloc_13A6:\ncdqe\njmp short loc_13BB\nloc_13B0:\nadd rax, 1\nadd edx, 1\ncmp ebp, eax\njle short loc_13D6\nloc_13BB:\nmov edi, [rbx+rax*8-8]\ncmp [rbx+rax*8], edi\njnz short loc_13B0\nmov esi, [rbx+rax*8-4]\ncmp [rbx+rax*8+4], esi\njnz short loc_13B0\nadd rax, 1\ncmp ebp, eax\njg short loc_13BB\nloc_13D6:\nadd rsp, 8\nmov eax, edx\npop rbx\npop rbp\nretn\nloc_13E0:\nmov edx, 8; size\nmov rsi, rdi; nmemb\nlea rcx, compar; compar\nmov rdi, rbx; base\ncall _qsort\nxor edx, edx\ntest ebp, ebp\nsetnz dl\nadd rsp, 8\nmov eax, edx\npop rbx\npop rbp\nretn\nloc_1407:\nmov edx, 1\njmp short loc_13D6", + "ida_strip_pseudo": "__int64 __fastcall sub_12D0(__m128i *base, int a2)\n{\n size_t v3; // rdi\n __m128i *v5; // rax\n __m128i *v6; // rsi\n __m128i v7; // xmm0\n __int32 v8; // edi\n __int32 *v9; // rcx\n unsigned int v10; // edx\n int v11; // esi\n __int64 v12; // rax\n __int32 v13; // r8d\n\n v3 = a2;\n if ( a2 <= 0 )\n {\n qsort(base, a2, 8uLL, compar);\n return a2 != 0;\n }\n else\n {\n v5 = base;\n v6 = (__m128i *)((char *)base + 8 * a2);\n do\n {\n v7 = _mm_loadl_epi64(v5);\n if ( _mm_cvtsi128_si32(v7) > _mm_cvtsi128_si32(_mm_shuffle_epi32(v7, 229)) )\n v5->m128i_i64[0] = _mm_shuffle_epi32(v7, 225).m128i_u64[0];\n v5 = (__m128i *)((char *)v5 + 8);\n }\n while ( v5 != v6 );\n qsort(base, v3, 8uLL, compar);\n if ( a2 == 1 )\n {\n return 1;\n }\n else\n {\n if ( a2 <= 3 )\n {\n v10 = 1;\n LODWORD(v12) = 1;\n }\n else\n {\n v8 = base->m128i_i32[0];\n v9 = &base->m128i_i32[1];\n v10 = 1;\n v11 = 1;\n LODWORD(v12) = ((a2 - 4) & 0xFFFFFFFE) + 3;\n do\n {\n v13 = v9[1];\n if ( v13 != v8 || v9[2] != *v9 )\n ++v10;\n v8 = v9[3];\n if ( v13 != v8 || v9[4] != v9[2] )\n ++v10;\n v11 += 2;\n v9 += 4;\n }\n while ( v11 != (_DWORD)v12 );\n }\n v12 = (int)v12;\n do\n {\n while ( base->m128i_i32[2 * v12] != base->m128i_i32[2 * v12 - 2]\n || base->m128i_i32[2 * v12 + 1] != base->m128i_i32[2 * v12 - 1] )\n {\n ++v12;\n ++v10;\n if ( a2 <= (int)v12 )\n return v10;\n }\n ++v12;\n }\n while ( a2 > (int)v12 );\n }\n return v10;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12D0(__m128i *base, int a2) {\n unsigned int v3;\n __m128i *v5;\n __m128i *v6;\n __m128i v7;\n int v8;\n int *v9;\n unsigned int v10;\n int v11;\n long long v12;\n int v13;\n v3 = a2;\n if (a2 <= 0) {\n qsort(base, a2, 8uLL, compar);\n return a2 != 0;\n } else {\n v5 = base;\n v6 = (__m128i *)((char *)base + 8 * a2);\n do {\n v7 = _mm_loadl_epi64(v5);\n if (_mm_cvtsi128_si32(v7) > _mm_cvtsi128_si32(_mm_shuffle_epi32(v7, 229)))\n v5->m128i_i64[0] = _mm_shuffle_epi32(v7, 225).m128i_u64[0];\n v5 = (__m128i *)((char *)v5 + 8);\n } while (v5 != v6);\n qsort(base, v3, 8uLL, compar);\n if (a2 == 1) {\n return 1;\n } else {\n if (a2 <= 3) {\n v10 = 1;\n LODWORD(v12) = 1;\n } else {\n v8 = base->m128i_i32[0];\n v9 = &base->m128i_i32[1];\n v10 = 1;\n v11 = 1;\n LODWORD(v12) = ((a2 - 4) & 4294967294) + 3;\n do {\n v13 = v9[1];\n if (v13 != v8 || v9[2] != *v9) ++v10;\n v8 = v9[3];\n if (v13 != v8 || v9[4] != v9[2]) ++v10;\n v11 += 2;\n v9 += 4;\n } while (v11 != (uint32_t)v12);\n }\n v12 = (int)v12;\n do {\n while (base->m128i_i32[2 * v12] != base->m128i_i32[2 * v12 - 2] ||\n base->m128i_i32[2 * v12 + 1] != base->m128i_i32[2 * v12 - 1]) {\n ++v12;\n ++v10;\n if (a2 <= (int)v12) return v10;\n }\n ++v12;\n } while (a2 > (int)v12);\n }\n return v10;\n }\n}", + "ida_pseudo_norm": "long long func0(__m128i *base, int a2) {\n unsigned int v3;\n __m128i *v5;\n __m128i *v6;\n __m128i v7;\n int v8;\n int *v9;\n unsigned int v10;\n int v11;\n long long v12;\n int v13;\n v3 = a2;\n if (a2 <= 0) {\n qsort(base, a2, 8uLL, cmp);\n return a2 != 0;\n } else {\n v5 = base;\n v6 = (__m128i *)((char *)base + 8 * a2);\n do {\n v7 = _mm_loadl_epi64(v5);\n if (_mm_cvtsi128_si32(v7) > _mm_cvtsi128_si32(_mm_shuffle_epi32(v7, 229)))\n v5->m128i_i64[0] = _mm_shuffle_epi32(v7, 225).m128i_u64[0];\n v5 = (__m128i *)((char *)v5 + 8);\n } while (v5 != v6);\n qsort(base, v3, 8uLL, cmp);\n if (a2 == 1) {\n return 1;\n } else {\n if (a2 <= 3) {\n v10 = 1;\n LODWORD(v12) = 1;\n } else {\n v8 = base->m128i_i32[0];\n v9 = &base->m128i_i32[1];\n v10 = 1;\n v11 = 1;\n LODWORD(v12) = ((a2 - 4) & 4294967294) + 3;\n do {\n v13 = v9[1];\n if (v13 != v8 || v9[2] != *v9) ++v10;\n v8 = v9[3];\n if (v13 != v8 || v9[4] != v9[2]) ++v10;\n v11 += 2;\n v9 += 4;\n } while (v11 != (uint32_t)v12);\n }\n v12 = (int)v12;\n do {\n while (base->m128i_i32[2 * v12] != base->m128i_i32[2 * v12 - 2] ||\n base->m128i_i32[2 * v12 + 1] != base->m128i_i32[2 * v12 - 1]) {\n ++v12;\n ++v10;\n if (a2 <= (int)v12) return v10;\n }\n ++v12;\n } while (a2 > (int)v12);\n }\n return v10;\n }\n}" + }, + { + "index": 401, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(const int test_tup1[][2], const int test_tup2[][2], int result[][2],\n int size) {\n for (int i = 0; i < size; i++) {\n for (int j = 0; j < 2; j++) {\n result[i][j] = test_tup1[i][j] + test_tup2[i][j];\n }\n }\n}", + "test": "int main() {\n\n int size = 4;\n\n int res[4][2];\n\n\n\n int test_tup1[][2] = {{1, 3}, {4, 5}, {2, 9}, {1, 10}};\n\n int test_tup2[][2] = {{6, 7}, {3, 9}, {1, 1}, {7, 3}};\n\n int expected[][2] = {{7, 10}, {7, 14}, {3, 10}, {8, 13}};\n\n func0(test_tup1, test_tup2, res, size);\n\n for (int i = 0; i < size; i++)\n\n for (int j = 0; j < 2; j++)\n\n assert(res[i][j] == expected[i][j]);\n\n\n\n int test_tup1_2[][2] = {{2, 4}, {5, 6}, {3, 10}, {2, 11}};\n\n int test_tup2_2[][2] = {{7, 8}, {4, 10}, {2, 2}, {8, 4}};\n\n int expected_2[][2] = {{9, 12}, {9, 16}, {5, 12}, {10, 15}};\n\n func0(test_tup1_2, test_tup2_2, res, size);\n\n for (int i = 0; i < size; i++)\n\n for (int j = 0; j < 2; j++)\n\n assert(res[i][j] == expected_2[i][j]);\n\n\n\n int test_tup1_3[][2] = {{3, 5}, {6, 7}, {4, 11}, {3, 12}};\n\n int test_tup2_3[][2] = {{8, 9}, {5, 11}, {3, 3}, {9, 5}};\n\n int expected_3[][2] = {{11, 14}, {11, 18}, {7, 14}, {12, 17}};\n\n func0(test_tup1_3, test_tup2_3, res, size);\n\n for (int i = 0; i < size; i++)\n\n for (int j = 0; j < 2; j++)\n\n assert(res[i][j] == expected_3[i][j]);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %ecx,-0x2c(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11f7 \nmovl $0x0,-0x4(%rbp)\njmp 11ed \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0x4(%rbp),%eax\ncltq\nmov (%rdx,%rax,4),%ecx\nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x20(%rbp),%rax\nadd %rax,%rdx\nmov -0x4(%rbp),%eax\ncltq\nmov (%rdx,%rax,4),%eax\nmov -0x8(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rsi\nmov -0x28(%rbp),%rdx\nadd %rsi,%rdx\nadd %eax,%ecx\nmov -0x4(%rbp),%eax\ncltq\nmov %ecx,(%rdx,%rax,4)\naddl $0x1,-0x4(%rbp)\ncmpl $0x1,-0x4(%rbp)\njle 1192 \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 1189 \npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_28], rdx\nmov [rbp+var_2C], ecx\nmov [rbp+var_8], 0\njmp short loc_11F7\nloc_1189:\nmov [rbp+var_4], 0\njmp short loc_11ED\nloc_1192:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\ncdqe\nmov ecx, [rdx+rax*4]\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_20]\nadd rdx, rax\nmov eax, [rbp+var_4]\ncdqe\nmov eax, [rdx+rax*4]\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nlea rsi, ds:0[rdx*8]\nmov rdx, [rbp+var_28]\nadd rdx, rsi\nadd ecx, eax\nmov eax, [rbp+var_4]\ncdqe\nmov [rdx+rax*4], ecx\nadd [rbp+var_4], 1\nloc_11ED:\ncmp [rbp+var_4], 1\njle short loc_1192\nadd [rbp+var_8], 1\nloc_11F7:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_2C]\njl short loc_1189\nnop\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+24h] [rbp-8h]\n int j; // [rsp+28h] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a4 )\n break;\n for ( j = 0; j <= 1; ++j )\n *(_DWORD *)(8LL * (int)i + a3 + 4LL * j) = *(_DWORD *)(a2 + 8LL * (int)i + 4LL * j)\n + *(_DWORD *)(a1 + 8LL * (int)i + 4LL * j);\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_28], rdx\nmov [rbp+var_2C], ecx\nmov [rbp+var_8], 0\njmp short loc_11F7\nloc_1189:\nmov [rbp+var_4], 0\njmp short loc_11ED\nloc_1192:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\ncdqe\nmov ecx, [rdx+rax*4]\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_20]\nadd rdx, rax\nmov eax, [rbp+var_4]\ncdqe\nmov eax, [rdx+rax*4]\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nlea rsi, ds:0[rdx*8]\nmov rdx, [rbp+var_28]\nadd rdx, rsi\nadd ecx, eax\nmov eax, [rbp+var_4]\ncdqe\nmov [rdx+rax*4], ecx\nadd [rbp+var_4], 1\nloc_11ED:\ncmp [rbp+var_4], 1\njle short loc_1192\nadd [rbp+var_8], 1\nloc_11F7:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_2C]\njl short loc_1189\nnop\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+24h] [rbp-8h]\n int j; // [rsp+28h] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a4 )\n break;\n for ( j = 0; j <= 1; ++j )\n *(_DWORD *)(8LL * (int)i + a3 + 4LL * j) = *(_DWORD *)(a2 + 8LL * (int)i + 4LL * j)\n + *(_DWORD *)(a1 + 8LL * (int)i + 4LL * j);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, long long a3, int a4) {\n long long result;\n unsigned int i;\n int j;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a4) break;\n for (j = 0; j <= 1; ++j)\n *(uint32_t *)(8LL * (int)i + a3 + 4LL * j) =\n *(uint32_t *)(a2 + 8LL * (int)i + 4LL * j) +\n *(uint32_t *)(a1 + 8LL * (int)i + 4LL * j);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, long long a3, int a4) {\n long long result;\n unsigned int i;\n int j;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a4) break;\n for (j = 0; j <= 1; ++j)\n *(uint32_t *)(8LL * (int)i + a3 + 4LL * j) =\n *(uint32_t *)(a2 + 8LL * (int)i + 4LL * j) +\n *(uint32_t *)(a1 + 8LL * (int)i + 4LL * j);\n }\n return result;\n}" + }, + { + "index": 401, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(const int test_tup1[][2], const int test_tup2[][2], int result[][2],\n int size) {\n for (int i = 0; i < size; i++) {\n for (int j = 0; j < 2; j++) {\n result[i][j] = test_tup1[i][j] + test_tup2[i][j];\n }\n }\n}", + "test": "int main() {\n\n int size = 4;\n\n int res[4][2];\n\n\n\n int test_tup1[][2] = {{1, 3}, {4, 5}, {2, 9}, {1, 10}};\n\n int test_tup2[][2] = {{6, 7}, {3, 9}, {1, 1}, {7, 3}};\n\n int expected[][2] = {{7, 10}, {7, 14}, {3, 10}, {8, 13}};\n\n func0(test_tup1, test_tup2, res, size);\n\n for (int i = 0; i < size; i++)\n\n for (int j = 0; j < 2; j++)\n\n assert(res[i][j] == expected[i][j]);\n\n\n\n int test_tup1_2[][2] = {{2, 4}, {5, 6}, {3, 10}, {2, 11}};\n\n int test_tup2_2[][2] = {{7, 8}, {4, 10}, {2, 2}, {8, 4}};\n\n int expected_2[][2] = {{9, 12}, {9, 16}, {5, 12}, {10, 15}};\n\n func0(test_tup1_2, test_tup2_2, res, size);\n\n for (int i = 0; i < size; i++)\n\n for (int j = 0; j < 2; j++)\n\n assert(res[i][j] == expected_2[i][j]);\n\n\n\n int test_tup1_3[][2] = {{3, 5}, {6, 7}, {4, 11}, {3, 12}};\n\n int test_tup2_3[][2] = {{8, 9}, {5, 11}, {3, 3}, {9, 5}};\n\n int expected_3[][2] = {{11, 14}, {11, 18}, {7, 14}, {12, 17}};\n\n func0(test_tup1_3, test_tup2_3, res, size);\n\n for (int i = 0; i < size; i++)\n\n for (int j = 0; j < 2; j++)\n\n assert(res[i][j] == expected_3[i][j]);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %ecx,%ecx\njle 119b \nlea -0x1(%rcx),%r8d\nmov $0x0,%eax\nmov (%rsi,%rax,8),%ecx\nadd (%rdi,%rax,8),%ecx\nmov %ecx,(%rdx,%rax,8)\nmov 0x4(%rsi,%rax,8),%ecx\nadd 0x4(%rdi,%rax,8),%ecx\nmov %ecx,0x4(%rdx,%rax,8)\nmov %rax,%rcx\nadd $0x1,%rax\ncmp %r8,%rcx\njne 117a \nretq\n", + "ida_asm": "func0:\nendbr64\ntest ecx, ecx\njle short locret_119F\nmovsxd rcx, ecx\nlea r8, ds:0[rcx*8]\nmov eax, 0\nloc_1181:\nmov ecx, [rdi+rax]\nadd ecx, [rsi+rax]\nmov [rdx+rax], ecx\nmov ecx, [rsi+rax+4]\nadd ecx, [rdi+rax+4]\nmov [rdx+rax+4], ecx\nadd rax, 8\ncmp r8, rax\njnz short loc_1181\nlocret_119F:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 v4; // rax\n\n if ( a4 > 0 )\n {\n v4 = 0LL;\n do\n {\n *(_DWORD *)(a3 + v4) = *(_DWORD *)(a2 + v4) + *(_DWORD *)(a1 + v4);\n *(_DWORD *)(a3 + v4 + 4) = *(_DWORD *)(a1 + v4 + 4) + *(_DWORD *)(a2 + v4 + 4);\n v4 += 8LL;\n }\n while ( 8LL * a4 != v4 );\n }\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest ecx, ecx\njle short locret_119F\nmovsxd rcx, ecx\nlea r8, ds:0[rcx*8]\nmov eax, 0\nloc_1181:\nmov ecx, [rdi+rax]\nadd ecx, [rsi+rax]\nmov [rdx+rax], ecx\nmov ecx, [rsi+rax+4]\nadd ecx, [rdi+rax+4]\nmov [rdx+rax+4], ecx\nadd rax, 8\ncmp r8, rax\njnz short loc_1181\nlocret_119F:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1169(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 v4; // rax\n\n if ( a4 > 0 )\n {\n v4 = 0LL;\n do\n {\n *(_DWORD *)(a3 + v4) = *(_DWORD *)(a2 + v4) + *(_DWORD *)(a1 + v4);\n *(_DWORD *)(a3 + v4 + 4) = *(_DWORD *)(a1 + v4 + 4) + *(_DWORD *)(a2 + v4 + 4);\n v4 += 8LL;\n }\n while ( 8LL * a4 != v4 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1169(long long a1, long long a2, long long a3, int a4) {\n long long v4;\n if (a4 > 0) {\n v4 = 0LL;\n do {\n *(uint32_t *)(a3 + v4) = *(uint32_t *)(a2 + v4) + *(uint32_t *)(a1 + v4);\n *(uint32_t *)(a3 + v4 + 4) =\n *(uint32_t *)(a1 + v4 + 4) + *(uint32_t *)(a2 + v4 + 4);\n v4 += 8LL;\n } while (8LL * a4 != v4);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, long long a2, long long a3, int a4) {\n long long v4;\n if (a4 > 0) {\n v4 = 0LL;\n do {\n *(uint32_t *)(a3 + v4) = *(uint32_t *)(a2 + v4) + *(uint32_t *)(a1 + v4);\n *(uint32_t *)(a3 + v4 + 4) =\n *(uint32_t *)(a1 + v4 + 4) + *(uint32_t *)(a2 + v4 + 4);\n v4 += 8LL;\n } while (8LL * a4 != v4);\n }\n}" + }, + { + "index": 401, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(const int test_tup1[][2], const int test_tup2[][2], int result[][2],\n int size) {\n for (int i = 0; i < size; i++) {\n for (int j = 0; j < 2; j++) {\n result[i][j] = test_tup1[i][j] + test_tup2[i][j];\n }\n }\n}", + "test": "int main() {\n\n int size = 4;\n\n int res[4][2];\n\n\n\n int test_tup1[][2] = {{1, 3}, {4, 5}, {2, 9}, {1, 10}};\n\n int test_tup2[][2] = {{6, 7}, {3, 9}, {1, 1}, {7, 3}};\n\n int expected[][2] = {{7, 10}, {7, 14}, {3, 10}, {8, 13}};\n\n func0(test_tup1, test_tup2, res, size);\n\n for (int i = 0; i < size; i++)\n\n for (int j = 0; j < 2; j++)\n\n assert(res[i][j] == expected[i][j]);\n\n\n\n int test_tup1_2[][2] = {{2, 4}, {5, 6}, {3, 10}, {2, 11}};\n\n int test_tup2_2[][2] = {{7, 8}, {4, 10}, {2, 2}, {8, 4}};\n\n int expected_2[][2] = {{9, 12}, {9, 16}, {5, 12}, {10, 15}};\n\n func0(test_tup1_2, test_tup2_2, res, size);\n\n for (int i = 0; i < size; i++)\n\n for (int j = 0; j < 2; j++)\n\n assert(res[i][j] == expected_2[i][j]);\n\n\n\n int test_tup1_3[][2] = {{3, 5}, {6, 7}, {4, 11}, {3, 12}};\n\n int test_tup2_3[][2] = {{8, 9}, {5, 11}, {3, 3}, {9, 5}};\n\n int expected_3[][2] = {{11, 14}, {11, 18}, {7, 14}, {12, 17}};\n\n func0(test_tup1_3, test_tup2_3, res, size);\n\n for (int i = 0; i < size; i++)\n\n for (int j = 0; j < 2; j++)\n\n assert(res[i][j] == expected_3[i][j]);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %ecx,%ecx\njle 1591 \nlea -0x1(%rcx),%r8d\nxor %eax,%eax\nxchg %ax,%ax\nmov (%rsi,%rax,8),%ecx\nadd (%rdi,%rax,8),%ecx\nmov %ecx,(%rdx,%rax,8)\nmov 0x4(%rsi,%rax,8),%ecx\nadd 0x4(%rdi,%rax,8),%ecx\nmov %ecx,0x4(%rdx,%rax,8)\nmov %rax,%rcx\nadd $0x1,%rax\ncmp %rcx,%r8\njne 1570 \nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\ntest ecx, ecx\njle short locret_1436\nmovsxd rcx, ecx\nxor eax, eax\nlea r8, ds:0[rcx*8]\nnop dword ptr [rax]\nloc_1418:\nmov ecx, [rsi+rax]\nadd ecx, [rdi+rax]\nmov [rdx+rax], ecx\nmov ecx, [rsi+rax+4]\nadd ecx, [rdi+rax+4]\nmov [rdx+rax+4], ecx\nadd rax, 8\ncmp r8, rax\njnz short loc_1418\nlocret_1436:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 v4; // rax\n\n if ( a4 > 0 )\n {\n v4 = 0LL;\n do\n {\n *(_DWORD *)(a3 + v4) = *(_DWORD *)(a1 + v4) + *(_DWORD *)(a2 + v4);\n *(_DWORD *)(a3 + v4 + 4) = *(_DWORD *)(a1 + v4 + 4) + *(_DWORD *)(a2 + v4 + 4);\n v4 += 8LL;\n }\n while ( 8LL * a4 != v4 );\n }\n}", + "ida_strip_asm": "sub_1400:\nendbr64\ntest ecx, ecx\njle short locret_1436\nmovsxd rcx, ecx\nxor eax, eax\nlea r8, ds:0[rcx*8]\nnop dword ptr [rax]\nloc_1418:\nmov ecx, [rsi+rax]\nadd ecx, [rdi+rax]\nmov [rdx+rax], ecx\nmov ecx, [rsi+rax+4]\nadd ecx, [rdi+rax+4]\nmov [rdx+rax+4], ecx\nadd rax, 8\ncmp r8, rax\njnz short loc_1418\nlocret_1436:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1400(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 v4; // rax\n\n if ( a4 > 0 )\n {\n v4 = 0LL;\n do\n {\n *(_DWORD *)(a3 + v4) = *(_DWORD *)(a1 + v4) + *(_DWORD *)(a2 + v4);\n *(_DWORD *)(a3 + v4 + 4) = *(_DWORD *)(a1 + v4 + 4) + *(_DWORD *)(a2 + v4 + 4);\n v4 += 8LL;\n }\n while ( 8LL * a4 != v4 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1400(long long a1, long long a2, long long a3, int a4) {\n long long v4;\n if (a4 > 0) {\n v4 = 0LL;\n do {\n *(uint32_t *)(a3 + v4) = *(uint32_t *)(a1 + v4) + *(uint32_t *)(a2 + v4);\n *(uint32_t *)(a3 + v4 + 4) =\n *(uint32_t *)(a1 + v4 + 4) + *(uint32_t *)(a2 + v4 + 4);\n v4 += 8LL;\n } while (8LL * a4 != v4);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, long long a2, long long a3, int a4) {\n long long v4;\n if (a4 > 0) {\n v4 = 0LL;\n do {\n *(uint32_t *)(a3 + v4) = *(uint32_t *)(a1 + v4) + *(uint32_t *)(a2 + v4);\n *(uint32_t *)(a3 + v4 + 4) =\n *(uint32_t *)(a1 + v4 + 4) + *(uint32_t *)(a2 + v4 + 4);\n v4 += 8LL;\n } while (8LL * a4 != v4);\n }\n}" + }, + { + "index": 402, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int n, int r, int p) {\n int C[r + 1];\n for (int i = 0; i <= r; i++) {\n C[i] = 0;\n }\n C[0] = 1;\n for (int i = 1; i <= n; i++) {\n for (int j = (i < r ? i : r); j > 0; j--) {\n C[j] = (C[j] + C[j - 1]) % p;\n }\n }\n return C[r];\n}", + "test": "int main() {\n\n assert(func0(10, 2, 13) == 6);\n\n assert(func0(15, 12, 43) == 25);\n\n assert(func0(17, 9, 18) == 10);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x48,%rsp\nmov %edi,-0x44(%rbp)\nmov %esi,-0x48(%rbp)\nmov %edx,-0x4c(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmov %rsp,%rax\nmov %rax,%rsi\nmov -0x48(%rbp),%eax\nadd $0x1,%eax\nmovslq %eax,%rdx\nsub $0x1,%rdx\nmov %rdx,-0x28(%rbp)\nmovslq %eax,%rdx\nmov %rdx,%r8\nmov $0x0,%r9d\nmovslq %eax,%rdx\nmov %rdx,%rcx\nmov $0x0,%ebx\ncltq\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%edi\nmov $0x0,%edx\ndiv %rdi\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rbx\nsub %rdx,%rbx\nmov %rbx,%rdx\ncmp %rdx,%rsp\nje 120d \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11f6 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 1237 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x20(%rbp)\nmovl $0x0,-0x2c(%rbp)\njmp 1268 \nmov -0x20(%rbp),%rax\nmov -0x2c(%rbp),%edx\nmovslq %edx,%rdx\nmovl $0x0,(%rax,%rdx,4)\naddl $0x1,-0x2c(%rbp)\nmov -0x2c(%rbp),%eax\ncmp -0x48(%rbp),%eax\njle 1253 \nmov -0x20(%rbp),%rax\nmovl $0x1,(%rax)\nmovl $0x1,-0x30(%rbp)\njmp 12d2 \nmov -0x30(%rbp),%eax\ncmp %eax,-0x48(%rbp)\ncmovle -0x48(%rbp),%eax\nmov %eax,-0x34(%rbp)\njmp 12c8 \nmov -0x20(%rbp),%rax\nmov -0x34(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%ecx\nmov -0x34(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x20(%rbp),%rax\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nadd %ecx,%eax\ncltd\nidivl -0x4c(%rbp)\nmov %edx,%ecx\nmov -0x20(%rbp),%rax\nmov -0x34(%rbp),%edx\nmovslq %edx,%rdx\nmov %ecx,(%rax,%rdx,4)\nsubl $0x1,-0x34(%rbp)\ncmpl $0x0,-0x34(%rbp)\njg 1292 \naddl $0x1,-0x30(%rbp)\nmov -0x30(%rbp),%eax\ncmp -0x44(%rbp),%eax\njle 1283 \nmov -0x20(%rbp),%rax\nmov -0x48(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nmov %rsi,%rsp\nmov -0x18(%rbp),%rdi\nxor %fs:0x28,%rdi\nje 12fe \ncallq 1060 <__stack_chk_fail@plt>\nmov -0x8(%rbp),%rbx\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_34], edi\nmov [rbp+var_38], esi\nmov [rbp+var_3C], edx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov eax, [rbp+var_38]\nadd eax, 1\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11DB:\ncmp rsp, rdx\njz short loc_11F2\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_11DB\nloc_11F2:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_121C\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_121C:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov [rbp+var_24], 0\njmp short loc_124D\nloc_1238:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov dword ptr [rax+rdx*4], 0\nadd [rbp+var_24], 1\nloc_124D:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_38]\njle short loc_1238\nmov rax, [rbp+var_10]\nmov dword ptr [rax], 1\nmov [rbp+var_20], 1\njmp short loc_12B8\nloc_1268:\nmov edx, [rbp+var_38]\nmov eax, [rbp+var_20]\ncmp edx, eax\ncmovle eax, edx\nmov [rbp+var_1C], eax\njmp short loc_12AE\nloc_1278:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov eax, [rbp+var_1C]\nlea edx, [rax-1]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nadd eax, ecx\ncdq\nidiv [rbp+var_3C]\nmov ecx, edx\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nsub [rbp+var_1C], 1\nloc_12AE:\ncmp [rbp+var_1C], 0\njg short loc_1278\nadd [rbp+var_20], 1\nloc_12B8:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_34]\njle short loc_1268\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12E4\ncall ___stack_chk_fail\nlocret_12E4:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, int a3)\n{\n unsigned __int64 v3; // rax\n void *v4; // rsp\n int v5; // eax\n _BYTE v7[4]; // [rsp+8h] [rbp-40h] BYREF\n int v8; // [rsp+Ch] [rbp-3Ch]\n int v9; // [rsp+10h] [rbp-38h]\n int v10; // [rsp+14h] [rbp-34h]\n int i; // [rsp+24h] [rbp-24h]\n int j; // [rsp+28h] [rbp-20h]\n int k; // [rsp+2Ch] [rbp-1Ch]\n __int64 v14; // [rsp+30h] [rbp-18h]\n _DWORD *v15; // [rsp+38h] [rbp-10h]\n unsigned __int64 v16; // [rsp+40h] [rbp-8h]\n\n v10 = a1;\n v9 = a2;\n v8 = a3;\n v16 = __readfsqword(0x28u);\n v14 = a2 + 1 - 1LL;\n v3 = 16 * ((4LL * (a2 + 1) + 15) / 0x10uLL);\n while ( v7 != &v7[-(v3 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v4 = alloca(v3 & 0xFFF);\n if ( (v3 & 0xFFF) != 0 )\n *(_QWORD *)&v7[(v3 & 0xFFF) - 8] = *(_QWORD *)&v7[(v3 & 0xFFF) - 8];\n v15 = v7;\n for ( i = 0; i <= v9; ++i )\n v15[i] = 0;\n *v15 = 1;\n for ( j = 1; j <= v10; ++j )\n {\n v5 = j;\n if ( v9 <= j )\n v5 = v9;\n for ( k = v5; k > 0; --k )\n v15[k] = (v15[k] + v15[k - 1]) % v8;\n }\n return (unsigned int)v15[v9];\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_34], edi\nmov [rbp+var_38], esi\nmov [rbp+var_3C], edx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov eax, [rbp+var_38]\nadd eax, 1\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11DB:\ncmp rsp, rdx\njz short loc_11F2\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_11DB\nloc_11F2:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_121C\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_121C:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov [rbp+var_24], 0\njmp short loc_124D\nloc_1238:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov dword ptr [rax+rdx*4], 0\nadd [rbp+var_24], 1\nloc_124D:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_38]\njle short loc_1238\nmov rax, [rbp+var_10]\nmov dword ptr [rax], 1\nmov [rbp+var_20], 1\njmp short loc_12B8\nloc_1268:\nmov edx, [rbp+var_38]\nmov eax, [rbp+var_20]\ncmp edx, eax\ncmovle eax, edx\nmov [rbp+var_1C], eax\njmp short loc_12AE\nloc_1278:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov eax, [rbp+var_1C]\nlea edx, [rax-1]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nadd eax, ecx\ncdq\nidiv [rbp+var_3C]\nmov ecx, edx\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nsub [rbp+var_1C], 1\nloc_12AE:\ncmp [rbp+var_1C], 0\njg short loc_1278\nadd [rbp+var_20], 1\nloc_12B8:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_34]\njle short loc_1268\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12E4\ncall ___stack_chk_fail\nlocret_12E4:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1, int a2, int a3)\n{\n unsigned __int64 v3; // rax\n void *v4; // rsp\n int v5; // eax\n _BYTE v7[4]; // [rsp+8h] [rbp-40h] BYREF\n int v8; // [rsp+Ch] [rbp-3Ch]\n int v9; // [rsp+10h] [rbp-38h]\n int v10; // [rsp+14h] [rbp-34h]\n int i; // [rsp+24h] [rbp-24h]\n int j; // [rsp+28h] [rbp-20h]\n int k; // [rsp+2Ch] [rbp-1Ch]\n __int64 v14; // [rsp+30h] [rbp-18h]\n _DWORD *v15; // [rsp+38h] [rbp-10h]\n unsigned __int64 v16; // [rsp+40h] [rbp-8h]\n\n v10 = a1;\n v9 = a2;\n v8 = a3;\n v16 = __readfsqword(0x28u);\n v14 = a2 + 1 - 1LL;\n v3 = 16 * ((4LL * (a2 + 1) + 15) / 0x10uLL);\n while ( v7 != &v7[-(v3 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v4 = alloca(v3 & 0xFFF);\n if ( (v3 & 0xFFF) != 0 )\n *(_QWORD *)&v7[(v3 & 0xFFF) - 8] = *(_QWORD *)&v7[(v3 & 0xFFF) - 8];\n v15 = v7;\n for ( i = 0; i <= v9; ++i )\n v15[i] = 0;\n *v15 = 1;\n for ( j = 1; j <= v10; ++j )\n {\n v5 = j;\n if ( v9 <= j )\n v5 = v9;\n for ( k = v5; k > 0; --k )\n v15[k] = (v15[k] + v15[k - 1]) % v8;\n }\n return (unsigned int)v15[v9];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1, int a2, int a3) {\n unsigned long long v3;\n void *v4;\n int v5;\n uint8_t v7[4];\n int v8;\n int v9;\n int v10;\n int i;\n int j;\n int k;\n long long v14;\n uint32_t *v15;\n unsigned long long v16;\n v10 = a1;\n v9 = a2;\n v8 = a3;\n v16 = __readfsqword(40u);\n v14 = a2 + 1 - 1LL;\n v3 = 16 * ((4LL * (a2 + 1) + 15) / 16uLL);\n while (v7 != &v7[-(v3 & 18446744073709547520LL)])\n ;\n v4 = alloca(v3 & 4095);\n if ((v3 & 4095) != 0)\n *(uint64_t *)&v7[(v3 & 4095) - 8] = *(uint64_t *)&v7[(v3 & 4095) - 8];\n v15 = v7;\n for (i = 0; i <= v9; ++i) v15[i] = 0;\n *v15 = 1;\n for (j = 1; j <= v10; ++j) {\n v5 = j;\n if (v9 <= j) v5 = v9;\n for (k = v5; k > 0; --k) v15[k] = (v15[k] + v15[k - 1]) % v8;\n }\n return (unsigned int)v15[v9];\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, int a3) {\n unsigned long long v3;\n void *v4;\n int v5;\n uint8_t v7[4];\n int v8;\n int v9;\n int v10;\n int i;\n int j;\n int k;\n long long v14;\n uint32_t *v15;\n unsigned long long v16;\n v10 = a1;\n v9 = a2;\n v8 = a3;\n v16 = __readfsqword(40u);\n v14 = a2 + 1 - 1LL;\n v3 = 16 * ((4LL * (a2 + 1) + 15) / 16uLL);\n while (v7 != &v7[-(v3 & 18446744073709547520LL)])\n ;\n v4 = alloca(v3 & 4095);\n if ((v3 & 4095) != 0)\n *(uint64_t *)&v7[(v3 & 4095) - 8] = *(uint64_t *)&v7[(v3 & 4095) - 8];\n v15 = v7;\n for (i = 0; i <= v9; ++i) v15[i] = 0;\n *v15 = 1;\n for (j = 1; j <= v10; ++j) {\n v5 = j;\n if (v9 <= j) v5 = v9;\n for (k = v5; k > 0; --k) v15[k] = (v15[k] + v15[k - 1]) % v8;\n }\n return (unsigned int)v15[v9];\n}" + }, + { + "index": 402, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int n, int r, int p) {\n int C[r + 1];\n for (int i = 0; i <= r; i++) {\n C[i] = 0;\n }\n C[0] = 1;\n for (int i = 1; i <= n; i++) {\n for (int j = (i < r ? i : r); j > 0; j--) {\n C[j] = (C[j] + C[j - 1]) % p;\n }\n }\n return C[r];\n}", + "test": "int main() {\n\n assert(func0(10, 2, 13) == 6);\n\n assert(func0(15, 12, 43) == 25);\n\n assert(func0(17, 9, 18) == 10);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r12\npush %rbx\nsub $0x10,%rsp\nmov %edx,%r8d\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nlea 0x1(%rsi),%eax\ncltq\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffffff0,%rdx\nand $0xfffffffffffff000,%rax\nmov %rsp,%rbx\nsub %rax,%rbx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 11c4 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11ad \nmov %rdx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 11da \norq $0x0,-0x8(%rsp,%rax,1)\nlea 0x3(%rsp),%r12\nmov %r12,%rcx\nshr $0x2,%rcx\nand $0xfffffffffffffffc,%r12\nmov %r12,%r11\ntest %esi,%esi\njs 120a \nmov %r12,%rax\nmov %esi,%edx\nlea 0x4(%r12,%rdx,4),%rdx\nmovl $0x0,(%rax)\nadd $0x4,%rax\ncmp %rdx,%rax\njne 11fb \nmovl $0x1,0x0(,%rcx,4)\ntest %edi,%edi\njle 126d \nlea 0x1(%rdi),%r10d\nmov $0x1,%r9d\nlea -0x4(%r11),%rbx\njmp 1232 \nadd $0x1,%r9d\ncmp %r10d,%r9d\nje 126d \ncmp %r9d,%esi\nmov %r9d,%eax\ncmovle %esi,%eax\ntest %eax,%eax\njle 1229 \nmovslq %eax,%rdi\nshl $0x2,%rdi\nlea (%r11,%rdi,1),%rcx\nadd %rbx,%rdi\nlea -0x1(%rax),%eax\nshl $0x2,%rax\nsub %rax,%rdi\nmov -0x4(%rcx),%eax\nadd (%rcx),%eax\ncltd\nidiv %r8d\nmov %edx,(%rcx)\nsub $0x4,%rcx\ncmp %rdi,%rcx\njne 1257 \njmp 1229 \nmovslq %esi,%rsi\nmov (%r12,%rsi,4),%eax\nmov -0x18(%rbp),%rbx\nxor %fs:0x28,%rbx\njne 128c \nlea -0x10(%rbp),%rsp\npop %rbx\npop %r12\npop %rbp\nretq\ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 18h\nmov r10d, edi\nmov r9d, esi\nmov esi, edx\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nlea eax, [r9+1]\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11AE:\ncmp rsp, rdx\njz short loc_11C5\nsub rsp, 1000h\nor [rsp+1020h+var_28], 0\njmp short loc_11AE\nloc_11C5:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11DB\nor [rsp+rax+20h+var_28], 0\nloc_11DB:\nlea r11, [rsp+20h+var_1D]\nmov rcx, r11\nshr rcx, 2\nand r11, 0FFFFFFFFFFFFFFFCh\ntest r9d, r9d\njs short loc_120A\nmov rax, r11\nlea edx, [r9+1]\nlea rdx, [r11+rdx*4]\nloc_11FB:\nmov dword ptr [rax], 0\nadd rax, 4\ncmp rax, rdx\njnz short loc_11FB\nloc_120A:\nmov ds:dword_0[rcx*4], 1\ntest r10d, r10d\njle short loc_126A\nadd r10d, 1\nmov r8d, 1\nlea rbx, [r11-4]\nloc_1228:\ncmp r9d, r8d\nmov eax, r8d\ncmovle eax, r9d\ntest eax, eax\njle short loc_1261\nmovsxd rdi, eax\nshl rdi, 2\nlea rcx, [r11+rdi]\nadd rdi, rbx\nlea eax, [rax-1]\nshl rax, 2\nsub rdi, rax\nloc_124E:\nmov eax, [rcx-4]\nadd eax, [rcx]\ncdq\nidiv esi\nmov [rcx], edx\nsub rcx, 4\ncmp rcx, rdi\njnz short loc_124E\nloc_1261:\nadd r8d, 1\ncmp r8d, r10d\njnz short loc_1228\nloc_126A:\nmovsxd r9, r9d\nmov eax, [r11+r9*4]\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njnz short loc_1286\nmov rbx, [rbp+var_8]\nleave\nretn\nloc_1286:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, int a3)\n{\n signed __int64 v3; // rax\n void *v4; // rsp\n _DWORD *v5; // rax\n int v6; // r10d\n int v7; // r8d\n int v8; // eax\n __int64 v9; // rdi\n int *v10; // rcx\n int *v11; // rdi\n _DWORD v14[2]; // [rsp+8h] [rbp-20h] BYREF\n unsigned __int64 v15; // [rsp+10h] [rbp-18h]\n\n v15 = __readfsqword(0x28u);\n while ( v14 != (_DWORD *)((char *)v14 - ((4LL * (a2 + 1) + 15) & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v3 = (4 * ((_WORD)a2 + 1) + 15) & 0xFF0;\n v4 = alloca(v3);\n if ( ((4 * ((_WORD)a2 + 1) + 15) & 0xFF0) != 0 )\n *(_QWORD *)((char *)&v14[-2] + v3) = *(_QWORD *)((char *)&v14[-2] + v3);\n if ( a2 >= 0 )\n {\n v5 = v14;\n do\n *v5++ = 0;\n while ( v5 != &v14[a2 + 1] );\n }\n v14[0] = 1;\n if ( a1 > 0 )\n {\n v6 = a1 + 1;\n v7 = 1;\n do\n {\n v8 = v7;\n if ( a2 <= v7 )\n v8 = a2;\n if ( v8 > 0 )\n {\n v9 = v8;\n v10 = &v14[v9];\n v11 = &v14[v9 - 1 - (unsigned int)(v8 - 1)];\n do\n {\n *v10 = (*v10 + *(v10 - 1)) % a3;\n --v10;\n }\n while ( v10 != v11 );\n }\n ++v7;\n }\n while ( v7 != v6 );\n }\n return (unsigned int)v14[a2];\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 18h\nmov r10d, edi\nmov r9d, esi\nmov esi, edx\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nlea eax, [r9+1]\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11AE:\ncmp rsp, rdx\njz short loc_11C5\nsub rsp, 1000h\nor [rsp+1020h+var_28], 0\njmp short loc_11AE\nloc_11C5:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11DB\nor [rsp+rax+20h+var_28], 0\nloc_11DB:\nlea r11, [rsp+20h+var_1D]\nmov rcx, r11\nshr rcx, 2\nand r11, 0FFFFFFFFFFFFFFFCh\ntest r9d, r9d\njs short loc_120A\nmov rax, r11\nlea edx, [r9+1]\nlea rdx, [r11+rdx*4]\nloc_11FB:\nmov dword ptr [rax], 0\nadd rax, 4\ncmp rax, rdx\njnz short loc_11FB\nloc_120A:\nmov ds:dword_0[rcx*4], 1\ntest r10d, r10d\njle short loc_126A\nadd r10d, 1\nmov r8d, 1\nlea rbx, [r11-4]\nloc_1228:\ncmp r9d, r8d\nmov eax, r8d\ncmovle eax, r9d\ntest eax, eax\njle short loc_1261\nmovsxd rdi, eax\nshl rdi, 2\nlea rcx, [r11+rdi]\nadd rdi, rbx\nlea eax, [rax-1]\nshl rax, 2\nsub rdi, rax\nloc_124E:\nmov eax, [rcx-4]\nadd eax, [rcx]\ncdq\nidiv esi\nmov [rcx], edx\nsub rcx, 4\ncmp rcx, rdi\njnz short loc_124E\nloc_1261:\nadd r8d, 1\ncmp r8d, r10d\njnz short loc_1228\nloc_126A:\nmovsxd r9, r9d\nmov eax, [r11+r9*4]\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njnz short loc_1286\nmov rbx, [rbp+var_8]\nleave\nretn\nloc_1286:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1, int a2, int a3)\n{\n signed __int64 v3; // rax\n void *v4; // rsp\n _DWORD *v5; // rax\n int v6; // r10d\n int v7; // r8d\n int v8; // eax\n __int64 v9; // rdi\n int *v10; // rcx\n int *v11; // rdi\n _DWORD v14[2]; // [rsp+8h] [rbp-20h] BYREF\n unsigned __int64 v15; // [rsp+10h] [rbp-18h]\n\n v15 = __readfsqword(0x28u);\n while ( v14 != (_DWORD *)((char *)v14 - ((4LL * (a2 + 1) + 15) & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v3 = (4 * ((_WORD)a2 + 1) + 15) & 0xFF0;\n v4 = alloca(v3);\n if ( ((4 * ((_WORD)a2 + 1) + 15) & 0xFF0) != 0 )\n *(_QWORD *)((char *)&v14[-2] + v3) = *(_QWORD *)((char *)&v14[-2] + v3);\n if ( a2 >= 0 )\n {\n v5 = v14;\n do\n *v5++ = 0;\n while ( v5 != &v14[a2 + 1] );\n }\n v14[0] = 1;\n if ( a1 > 0 )\n {\n v6 = a1 + 1;\n v7 = 1;\n do\n {\n v8 = v7;\n if ( a2 <= v7 )\n v8 = a2;\n if ( v8 > 0 )\n {\n v9 = v8;\n v10 = &v14[v9];\n v11 = &v14[v9 - 1 - (unsigned int)(v8 - 1)];\n do\n {\n *v10 = (*v10 + *(v10 - 1)) % a3;\n --v10;\n }\n while ( v10 != v11 );\n }\n ++v7;\n }\n while ( v7 != v6 );\n }\n return (unsigned int)v14[a2];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1, int a2, int a3) {\n signed long long v3;\n void *v4;\n uint32_t *v5;\n int v6;\n int v7;\n int v8;\n long long v9;\n int *v10;\n int *v11;\n uint32_t v14[2];\n unsigned long long v15;\n v15 = __readfsqword(40u);\n while (v14 != (uint32_t *)((char *)v14 -\n ((4LL * (a2 + 1) + 15) & 18446744073709547520LL)))\n ;\n v3 = (4 * ((unsigned short)a2 + 1) + 15) & 4080;\n v4 = alloca(v3);\n if (((4 * ((unsigned short)a2 + 1) + 15) & 4080) != 0)\n *(uint64_t *)((char *)&v14[-2] + v3) = *(uint64_t *)((char *)&v14[-2] + v3);\n if (a2 >= 0) {\n v5 = v14;\n do\n *v5++ = 0;\n while (v5 != &v14[a2 + 1]);\n }\n v14[0] = 1;\n if (a1 > 0) {\n v6 = a1 + 1;\n v7 = 1;\n do {\n v8 = v7;\n if (a2 <= v7) v8 = a2;\n if (v8 > 0) {\n v9 = v8;\n v10 = &v14[v9];\n v11 = &v14[v9 - 1 - (unsigned int)(v8 - 1)];\n do {\n *v10 = (*v10 + *(v10 - 1)) % a3;\n --v10;\n } while (v10 != v11);\n }\n ++v7;\n } while (v7 != v6);\n }\n return (unsigned int)v14[a2];\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, int a3) {\n signed long long v3;\n void *v4;\n uint32_t *v5;\n int v6;\n int v7;\n int v8;\n long long v9;\n int *v10;\n int *v11;\n uint32_t v14[2];\n unsigned long long v15;\n v15 = __readfsqword(40u);\n while (v14 != (uint32_t *)((char *)v14 -\n ((4LL * (a2 + 1) + 15) & 18446744073709547520LL)))\n ;\n v3 = (4 * ((unsigned short)a2 + 1) + 15) & 4080;\n v4 = alloca(v3);\n if (((4 * ((unsigned short)a2 + 1) + 15) & 4080) != 0)\n *(uint64_t *)((char *)&v14[-2] + v3) = *(uint64_t *)((char *)&v14[-2] + v3);\n if (a2 >= 0) {\n v5 = v14;\n do\n *v5++ = 0;\n while (v5 != &v14[a2 + 1]);\n }\n v14[0] = 1;\n if (a1 > 0) {\n v6 = a1 + 1;\n v7 = 1;\n do {\n v8 = v7;\n if (a2 <= v7) v8 = a2;\n if (v8 > 0) {\n v9 = v8;\n v10 = &v14[v9];\n v11 = &v14[v9 - 1 - (unsigned int)(v8 - 1)];\n do {\n *v10 = (*v10 + *(v10 - 1)) % a3;\n --v10;\n } while (v10 != v11);\n }\n ++v7;\n } while (v7 != v6);\n }\n return (unsigned int)v14[a2];\n}" + }, + { + "index": 402, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int n, int r, int p) {\n int C[r + 1];\n for (int i = 0; i <= r; i++) {\n C[i] = 0;\n }\n C[0] = 1;\n for (int i = 1; i <= n; i++) {\n for (int j = (i < r ? i : r); j > 0; j--) {\n C[j] = (C[j] + C[j - 1]) % p;\n }\n }\n return C[r];\n}", + "test": "int main() {\n\n assert(func0(10, 2, 13) == 6);\n\n assert(func0(15, 12, 43) == 25);\n\n assert(func0(17, 9, 18) == 10);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %edx,%r8d\nmov %rsp,%rbp\npush %r12\npush %rbx\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nlea 0x1(%rsi),%eax\nmov %rsp,%rbx\ncltq\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rbx\nand $0xfffffffffffffff0,%rdx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 151e \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 1509 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 15ea \nlea 0x3(%rsp),%r11\nmovslq %esi,%r12\nmov %r11,%rcx\nand $0xfffffffffffffffc,%r11\nshr $0x2,%rcx\ntest %esi,%esi\njs 1567 \nmovslq %esi,%r12\nmov %r11,%rax\nlea 0x4(%r11,%r12,4),%rdx\nnopw 0x0(%rax,%rax,1)\nmovl $0x0,(%rax)\nadd $0x4,%rax\ncmp %rdx,%rax\njne 1558 \nmovl $0x1,0x0(,%rcx,4)\ntest %edi,%edi\njle 15ce \nlea 0x1(%rdi),%r10d\nmov $0x1,%r9d\nlea -0x4(%r11),%rbx\nnopl 0x0(%rax)\ncmp %r9d,%esi\nmov %r9d,%eax\ncmovle %esi,%eax\ntest %eax,%eax\njle 15c5 \nmovslq %eax,%rdi\nsub $0x1,%eax\nshl $0x2,%rdi\nshl $0x2,%rax\nlea (%r11,%rdi,1),%rcx\nadd %rbx,%rdi\nsub %rax,%rdi\nnopl (%rax)\nmov -0x4(%rcx),%eax\nadd (%rcx),%eax\nsub $0x4,%rcx\ncltd\nidiv %r8d\nmov %edx,0x4(%rcx)\ncmp %rdi,%rcx\njne 15b0 \nadd $0x1,%r9d\ncmp %r10d,%r9d\njne 1588 \nmov -0x18(%rbp),%rbx\nxor %fs:0x28,%rbx\nmov (%r11,%r12,4),%eax\njne 15f5 \nlea -0x10(%rbp),%rsp\npop %rbx\npop %r12\npop %rbp\nretq\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 1530 \ncallq 1060 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\nmov r15d, edi\npush r14\npush r13\npush r12\nmov r12d, esi\npush rbx\nmov ebx, edx\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nlea eax, [rsi+1]\nmov rcx, rsp\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_12B6\nloc_12A1:\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\ncmp rsp, rcx\njnz short loc_12A1\nloc_12B6:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1381\nloc_12C8:\nlea r10, [rsp+1040h+var_103D]\nmovsxd r13, r12d\nmov r14, r10\nand r10, 0FFFFFFFFFFFFFFFCh\nshr r14, 2\ntest r12d, r12d\njs short loc_12F5\nmov rdi, r10; s\nlea rdx, ds:4[r13*4]; n\nxor esi, esi; c\ncall _memset\nmov r10, rax\nloc_12F5:\nmov ds:dword_0[r14*4], 1\ntest r15d, r15d\njle short loc_135F\nlea r9d, [r15+1]\nmov r8d, 1\nlea r11, [r10-4]\nnop dword ptr [rax+00h]\nloc_1318:\ncmp r12d, r8d\nmov eax, r8d\ncmovle eax, r12d\ntest eax, eax\njle short loc_1356\nmovsxd rdi, eax\nsub eax, 1\nshl rdi, 2\nshl rax, 2\nlea rcx, [r10+rdi]\nadd rdi, r11\nmov esi, [rcx]\nsub rdi, rax\nloc_1340:\nmov eax, esi\nmov esi, [rcx-4]\nsub rcx, 4\nadd eax, esi\ncdq\nidiv ebx\nmov [rcx+4], edx\ncmp rcx, rdi\njnz short loc_1340\nloc_1356:\nadd r8d, 1\ncmp r8d, r9d\njnz short loc_1318\nloc_135F:\nmov eax, [r10+r13*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_138C\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1381:\nor [rsp+rdx+1040h+var_1048], 0\njmp loc_12C8\nloc_138C:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, int a3)\n{\n __int64 v5; // rdx\n _DWORD *v6; // rcx\n __int16 v7; // dx\n signed __int64 v8; // rdx\n void *v9; // rsp\n _DWORD *v10; // r10\n int v11; // r9d\n int v12; // r8d\n int v13; // eax\n __int64 v14; // rdi\n _DWORD *v15; // rcx\n int v16; // esi\n __int64 v17; // rdi\n int v18; // eax\n _DWORD v21[1022]; // [rsp+8h] [rbp-1040h] BYREF\n _QWORD v22[8]; // [rsp+1008h] [rbp-40h] BYREF\n\n v22[1] = __readfsqword(0x28u);\n v5 = 4LL * (a2 + 1) + 15;\n v6 = (_DWORD *)((char *)v22 - (v5 & 0xFFFFFFFFFFFFF000LL));\n v7 = v5 & 0xFFF0;\n if ( v22 != (_QWORD *)v6 )\n {\n while ( v21 != v6 )\n ;\n }\n v8 = v7 & 0xFFF;\n v9 = alloca(v8);\n if ( v8 )\n *(_QWORD *)((char *)&v21[-2] + v8) = *(_QWORD *)((char *)&v21[-2] + v8);\n v10 = v21;\n if ( a2 >= 0 )\n v10 = memset(v21, 0, 4LL * a2 + 4);\n v21[0] = 1;\n if ( a1 > 0 )\n {\n v11 = a1 + 1;\n v12 = 1;\n do\n {\n v13 = v12;\n if ( a2 <= v12 )\n v13 = a2;\n if ( v13 > 0 )\n {\n v14 = v13;\n v15 = &v10[v14];\n v16 = v10[v14];\n v17 = (__int64)&v10[v14 - 1 - (unsigned int)(v13 - 1)];\n do\n {\n v18 = v16;\n v16 = *--v15;\n v15[1] = (v16 + v18) % a3;\n }\n while ( v15 != (_DWORD *)v17 );\n }\n ++v12;\n }\n while ( v12 != v11 );\n }\n return (unsigned int)v10[a2];\n}", + "ida_strip_asm": "sub_1250:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\nmov r15d, edi\npush r14\npush r13\npush r12\nmov r12d, esi\npush rbx\nmov ebx, edx\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nlea eax, [rsi+1]\nmov rcx, rsp\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_12B6\nloc_12A1:\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\ncmp rsp, rcx\njnz short loc_12A1\nloc_12B6:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1381\nloc_12C8:\nlea r10, [rsp+1040h+var_103D]\nmovsxd r13, r12d\nmov r14, r10\nand r10, 0FFFFFFFFFFFFFFFCh\nshr r14, 2\ntest r12d, r12d\njs short loc_12F5\nmov rdi, r10; s\nlea rdx, ds:4[r13*4]; n\nxor esi, esi; c\ncall _memset\nmov r10, rax\nloc_12F5:\nmov ds:dword_0[r14*4], 1\ntest r15d, r15d\njle short loc_135F\nlea r9d, [r15+1]\nmov r8d, 1\nlea r11, [r10-4]\nnop dword ptr [rax+00h]\nloc_1318:\ncmp r12d, r8d\nmov eax, r8d\ncmovle eax, r12d\ntest eax, eax\njle short loc_1356\nmovsxd rdi, eax\nsub eax, 1\nshl rdi, 2\nshl rax, 2\nlea rcx, [r10+rdi]\nadd rdi, r11\nmov esi, [rcx]\nsub rdi, rax\nloc_1340:\nmov eax, esi\nmov esi, [rcx-4]\nsub rcx, 4\nadd eax, esi\ncdq\nidiv ebx\nmov [rcx+4], edx\ncmp rcx, rdi\njnz short loc_1340\nloc_1356:\nadd r8d, 1\ncmp r8d, r9d\njnz short loc_1318\nloc_135F:\nmov eax, [r10+r13*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_138C\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1381:\nor [rsp+rdx+1040h+var_1048], 0\njmp loc_12C8\nloc_138C:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1250(int a1, int a2, int a3)\n{\n __int64 v5; // rdx\n _DWORD *v6; // rcx\n __int16 v7; // dx\n signed __int64 v8; // rdx\n void *v9; // rsp\n _DWORD *v10; // r10\n int v11; // r9d\n int v12; // r8d\n int v13; // eax\n __int64 v14; // rdi\n _DWORD *v15; // rcx\n int v16; // esi\n __int64 v17; // rdi\n int v18; // eax\n _DWORD v21[1022]; // [rsp+8h] [rbp-1040h] BYREF\n _QWORD v22[8]; // [rsp+1008h] [rbp-40h] BYREF\n\n v22[1] = __readfsqword(0x28u);\n v5 = 4LL * (a2 + 1) + 15;\n v6 = (_DWORD *)((char *)v22 - (v5 & 0xFFFFFFFFFFFFF000LL));\n v7 = v5 & 0xFFF0;\n if ( v22 != (_QWORD *)v6 )\n {\n while ( v21 != v6 )\n ;\n }\n v8 = v7 & 0xFFF;\n v9 = alloca(v8);\n if ( v8 )\n *(_QWORD *)((char *)&v21[-2] + v8) = *(_QWORD *)((char *)&v21[-2] + v8);\n v10 = v21;\n if ( a2 >= 0 )\n v10 = memset(v21, 0, 4LL * a2 + 4);\n v21[0] = 1;\n if ( a1 > 0 )\n {\n v11 = a1 + 1;\n v12 = 1;\n do\n {\n v13 = v12;\n if ( a2 <= v12 )\n v13 = a2;\n if ( v13 > 0 )\n {\n v14 = v13;\n v15 = &v10[v14];\n v16 = v10[v14];\n v17 = (__int64)&v10[v14 - 1 - (unsigned int)(v13 - 1)];\n do\n {\n v18 = v16;\n v16 = *--v15;\n v15[1] = (v16 + v18) % a3;\n }\n while ( v15 != (_DWORD *)v17 );\n }\n ++v12;\n }\n while ( v12 != v11 );\n }\n return (unsigned int)v10[a2];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1250(int a1, int a2, int a3) {\n long long v5;\n uint32_t *v6;\n short v7;\n signed long long v8;\n void *v9;\n uint32_t *v10;\n int v11;\n int v12;\n int v13;\n long long v14;\n uint32_t *v15;\n int v16;\n long long v17;\n int v18;\n uint32_t v21[1022];\n uint64_t v22[8];\n v22[1] = __readfsqword(40u);\n v5 = 4LL * (a2 + 1) + 15;\n v6 = (uint32_t *)((char *)v22 - (v5 & 18446744073709547520LL));\n v7 = v5 & 65520;\n if (v22 != (uint64_t *)v6) {\n while (v21 != v6)\n ;\n }\n v8 = v7 & 4095;\n v9 = alloca(v8);\n if (v8)\n *(uint64_t *)((char *)&v21[-2] + v8) = *(uint64_t *)((char *)&v21[-2] + v8);\n v10 = v21;\n if (a2 >= 0) v10 = memset(v21, 0, 4LL * a2 + 4);\n v21[0] = 1;\n if (a1 > 0) {\n v11 = a1 + 1;\n v12 = 1;\n do {\n v13 = v12;\n if (a2 <= v12) v13 = a2;\n if (v13 > 0) {\n v14 = v13;\n v15 = &v10[v14];\n v16 = v10[v14];\n v17 = (long long)&v10[v14 - 1 - (unsigned int)(v13 - 1)];\n do {\n v18 = v16;\n v16 = *--v15;\n v15[1] = (v16 + v18) % a3;\n } while (v15 != (uint32_t *)v17);\n }\n ++v12;\n } while (v12 != v11);\n }\n return (unsigned int)v10[a2];\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, int a3) {\n long long v5;\n uint32_t *v6;\n short v7;\n signed long long v8;\n void *v9;\n uint32_t *v10;\n int v11;\n int v12;\n int v13;\n long long v14;\n uint32_t *v15;\n int v16;\n long long v17;\n int v18;\n uint32_t v21[1022];\n uint64_t v22[8];\n v22[1] = __readfsqword(40u);\n v5 = 4LL * (a2 + 1) + 15;\n v6 = (uint32_t *)((char *)v22 - (v5 & 18446744073709547520LL));\n v7 = v5 & 65520;\n if (v22 != (uint64_t *)v6) {\n while (v21 != v6)\n ;\n }\n v8 = v7 & 4095;\n v9 = alloca(v8);\n if (v8)\n *(uint64_t *)((char *)&v21[-2] + v8) = *(uint64_t *)((char *)&v21[-2] + v8);\n v10 = v21;\n if (a2 >= 0) v10 = memset(v21, 0, 4LL * a2 + 4);\n v21[0] = 1;\n if (a1 > 0) {\n v11 = a1 + 1;\n v12 = 1;\n do {\n v13 = v12;\n if (a2 <= v12) v13 = a2;\n if (v13 > 0) {\n v14 = v13;\n v15 = &v10[v14];\n v16 = v10[v14];\n v17 = (long long)&v10[v14 - 1 - (unsigned int)(v13 - 1)];\n do {\n v18 = v16;\n v16 = *--v15;\n v15[1] = (v16 + v18) % a3;\n } while (v15 != (uint32_t *)v17);\n }\n ++v12;\n } while (v12 != v11);\n }\n return (unsigned int)v10[a2];\n}" + }, + { + "index": 402, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int n, int r, int p) {\n int C[r + 1];\n for (int i = 0; i <= r; i++) {\n C[i] = 0;\n }\n C[0] = 1;\n for (int i = 1; i <= n; i++) {\n for (int j = (i < r ? i : r); j > 0; j--) {\n C[j] = (C[j] + C[j - 1]) % p;\n }\n }\n return C[r];\n}", + "test": "int main() {\n\n assert(func0(10, 2, 13) == 6);\n\n assert(func0(15, 12, 43) == 25);\n\n assert(func0(17, 9, 18) == 10);\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\nmov %edi,%r15d\npush %r14\npush %r13\npush %r12\nmov %esi,%r12d\npush %rbx\nmov %edx,%ebx\nsub $0x18,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nlea 0x1(%rsi),%eax\nmov %rsp,%rdi\ncltq\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rdi\nand $0xfffffffffffffff0,%rdx\nmov %rdi,%rax\ncmp %rax,%rsp\nje 1909 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 18f4 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 19e1 \nlea 0x3(%rsp),%r10\nmovslq %r12d,%r13\nmov %r10,%r14\nand $0xfffffffffffffffc,%r10\nshr $0x2,%r14\ntest %r12d,%r12d\njs 1948 \nmov %r10,%rdi\nlea 0x4(,%r13,4),%rdx\nxor %esi,%esi\ncallq 1090 \nmov %rax,%r10\nmovl $0x1,0x0(,%r14,4)\ntest %r15d,%r15d\njle 19bf \nlea 0x1(%r15),%r9d\nmov $0x1,%r8d\nlea -0x4(%r10),%r11\nnopw 0x0(%rax,%rax,1)\ncmp %r8d,%r12d\nmov %r8d,%eax\ncmovle %r12d,%eax\ntest %eax,%eax\njle 19b6 \nmovslq %eax,%rdi\nsub $0x1,%eax\nshl $0x2,%rdi\nshl $0x2,%rax\nlea (%r10,%rdi,1),%rcx\nadd %r11,%rdi\nmov (%rcx),%esi\nsub %rax,%rdi\nnopl 0x0(%rax,%rax,1)\nmov %esi,%eax\nmov -0x4(%rcx),%esi\nsub $0x4,%rcx\nadd %esi,%eax\ncltd\nidiv %ebx\nmov %edx,0x4(%rcx)\ncmp %rdi,%rcx\njne 19a0 \nadd $0x1,%r8d\ncmp %r9d,%r8d\njne 1970 \nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\nmov (%r10,%r13,4),%eax\njne 19ec \nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 191b \ncallq 1070 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\nmov r15d, edi\npush r14\npush r13\npush r12\nmov r12d, esi\npush rbx\nmov ebx, edx\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nlea eax, [rsi+1]\nmov rcx, rsp\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_12B6\nloc_12A1:\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\ncmp rsp, rcx\njnz short loc_12A1\nloc_12B6:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1381\nloc_12C8:\nlea r10, [rsp+1040h+var_103D]\nmovsxd r13, r12d\nmov r14, r10\nand r10, 0FFFFFFFFFFFFFFFCh\nshr r14, 2\ntest r12d, r12d\njs short loc_12F5\nmov rdi, r10; s\nlea rdx, ds:4[r13*4]; n\nxor esi, esi; c\ncall _memset\nmov r10, rax\nloc_12F5:\nmov ds:dword_0[r14*4], 1\ntest r15d, r15d\njle short loc_135F\nlea r9d, [r15+1]\nmov r8d, 1\nlea r11, [r10-4]\nnop dword ptr [rax+00h]\nloc_1318:\ncmp r12d, r8d\nmov eax, r8d\ncmovle eax, r12d\ntest eax, eax\njle short loc_1356\nmovsxd rdi, eax\nsub eax, 1\nshl rdi, 2\nshl rax, 2\nlea rcx, [r10+rdi]\nadd rdi, r11\nmov esi, [rcx]\nsub rdi, rax\nloc_1340:\nmov eax, esi\nmov esi, [rcx-4]\nsub rcx, 4\nadd eax, esi\ncdq\nidiv ebx\nmov [rcx+4], edx\ncmp rcx, rdi\njnz short loc_1340\nloc_1356:\nadd r8d, 1\ncmp r8d, r9d\njnz short loc_1318\nloc_135F:\nmov eax, [r10+r13*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_138C\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1381:\nor [rsp+rdx+1040h+var_1048], 0\njmp loc_12C8\nloc_138C:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, int a3)\n{\n __int64 v5; // rdx\n _DWORD *v6; // rcx\n __int16 v7; // dx\n signed __int64 v8; // rdx\n void *v9; // rsp\n _DWORD *v10; // r10\n int v11; // r9d\n int v12; // r8d\n int v13; // eax\n __int64 v14; // rdi\n _DWORD *v15; // rcx\n int v16; // esi\n __int64 v17; // rdi\n int v18; // eax\n _DWORD v21[1022]; // [rsp+8h] [rbp-1040h] BYREF\n _QWORD v22[8]; // [rsp+1008h] [rbp-40h] BYREF\n\n v22[1] = __readfsqword(0x28u);\n v5 = 4LL * (a2 + 1) + 15;\n v6 = (_DWORD *)((char *)v22 - (v5 & 0xFFFFFFFFFFFFF000LL));\n v7 = v5 & 0xFFF0;\n if ( v22 != (_QWORD *)v6 )\n {\n while ( v21 != v6 )\n ;\n }\n v8 = v7 & 0xFFF;\n v9 = alloca(v8);\n if ( v8 )\n *(_QWORD *)((char *)&v21[-2] + v8) = *(_QWORD *)((char *)&v21[-2] + v8);\n v10 = v21;\n if ( a2 >= 0 )\n v10 = memset(v21, 0, 4LL * a2 + 4);\n v21[0] = 1;\n if ( a1 > 0 )\n {\n v11 = a1 + 1;\n v12 = 1;\n do\n {\n v13 = v12;\n if ( a2 <= v12 )\n v13 = a2;\n if ( v13 > 0 )\n {\n v14 = v13;\n v15 = &v10[v14];\n v16 = v10[v14];\n v17 = (__int64)&v10[v14 - 1 - (unsigned int)(v13 - 1)];\n do\n {\n v18 = v16;\n v16 = *--v15;\n v15[1] = (v16 + v18) % a3;\n }\n while ( v15 != (_DWORD *)v17 );\n }\n ++v12;\n }\n while ( v12 != v11 );\n }\n return (unsigned int)v10[a2];\n}", + "ida_strip_asm": "sub_1250:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\nmov r15d, edi\npush r14\npush r13\npush r12\nmov r12d, esi\npush rbx\nmov ebx, edx\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nlea eax, [rsi+1]\nmov rcx, rsp\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_12B6\nloc_12A1:\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\ncmp rsp, rcx\njnz short loc_12A1\nloc_12B6:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1381\nloc_12C8:\nlea r10, [rsp+1040h+var_103D]\nmovsxd r13, r12d\nmov r14, r10\nand r10, 0FFFFFFFFFFFFFFFCh\nshr r14, 2\ntest r12d, r12d\njs short loc_12F5\nmov rdi, r10; s\nlea rdx, ds:4[r13*4]; n\nxor esi, esi; c\ncall _memset\nmov r10, rax\nloc_12F5:\nmov ds:dword_0[r14*4], 1\ntest r15d, r15d\njle short loc_135F\nlea r9d, [r15+1]\nmov r8d, 1\nlea r11, [r10-4]\nnop dword ptr [rax+00h]\nloc_1318:\ncmp r12d, r8d\nmov eax, r8d\ncmovle eax, r12d\ntest eax, eax\njle short loc_1356\nmovsxd rdi, eax\nsub eax, 1\nshl rdi, 2\nshl rax, 2\nlea rcx, [r10+rdi]\nadd rdi, r11\nmov esi, [rcx]\nsub rdi, rax\nloc_1340:\nmov eax, esi\nmov esi, [rcx-4]\nsub rcx, 4\nadd eax, esi\ncdq\nidiv ebx\nmov [rcx+4], edx\ncmp rcx, rdi\njnz short loc_1340\nloc_1356:\nadd r8d, 1\ncmp r8d, r9d\njnz short loc_1318\nloc_135F:\nmov eax, [r10+r13*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_138C\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1381:\nor [rsp+rdx+1040h+var_1048], 0\njmp loc_12C8\nloc_138C:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1250(int a1, int a2, int a3)\n{\n __int64 v5; // rdx\n _DWORD *v6; // rcx\n __int16 v7; // dx\n signed __int64 v8; // rdx\n void *v9; // rsp\n _DWORD *v10; // r10\n int v11; // r9d\n int v12; // r8d\n int v13; // eax\n __int64 v14; // rdi\n _DWORD *v15; // rcx\n int v16; // esi\n __int64 v17; // rdi\n int v18; // eax\n _DWORD v21[1022]; // [rsp+8h] [rbp-1040h] BYREF\n _QWORD v22[8]; // [rsp+1008h] [rbp-40h] BYREF\n\n v22[1] = __readfsqword(0x28u);\n v5 = 4LL * (a2 + 1) + 15;\n v6 = (_DWORD *)((char *)v22 - (v5 & 0xFFFFFFFFFFFFF000LL));\n v7 = v5 & 0xFFF0;\n if ( v22 != (_QWORD *)v6 )\n {\n while ( v21 != v6 )\n ;\n }\n v8 = v7 & 0xFFF;\n v9 = alloca(v8);\n if ( v8 )\n *(_QWORD *)((char *)&v21[-2] + v8) = *(_QWORD *)((char *)&v21[-2] + v8);\n v10 = v21;\n if ( a2 >= 0 )\n v10 = memset(v21, 0, 4LL * a2 + 4);\n v21[0] = 1;\n if ( a1 > 0 )\n {\n v11 = a1 + 1;\n v12 = 1;\n do\n {\n v13 = v12;\n if ( a2 <= v12 )\n v13 = a2;\n if ( v13 > 0 )\n {\n v14 = v13;\n v15 = &v10[v14];\n v16 = v10[v14];\n v17 = (__int64)&v10[v14 - 1 - (unsigned int)(v13 - 1)];\n do\n {\n v18 = v16;\n v16 = *--v15;\n v15[1] = (v16 + v18) % a3;\n }\n while ( v15 != (_DWORD *)v17 );\n }\n ++v12;\n }\n while ( v12 != v11 );\n }\n return (unsigned int)v10[a2];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1250(int a1, int a2, int a3) {\n long long v5;\n uint32_t *v6;\n short v7;\n signed long long v8;\n void *v9;\n uint32_t *v10;\n int v11;\n int v12;\n int v13;\n long long v14;\n uint32_t *v15;\n int v16;\n long long v17;\n int v18;\n uint32_t v21[1022];\n uint64_t v22[8];\n v22[1] = __readfsqword(40u);\n v5 = 4LL * (a2 + 1) + 15;\n v6 = (uint32_t *)((char *)v22 - (v5 & 18446744073709547520LL));\n v7 = v5 & 65520;\n if (v22 != (uint64_t *)v6) {\n while (v21 != v6)\n ;\n }\n v8 = v7 & 4095;\n v9 = alloca(v8);\n if (v8)\n *(uint64_t *)((char *)&v21[-2] + v8) = *(uint64_t *)((char *)&v21[-2] + v8);\n v10 = v21;\n if (a2 >= 0) v10 = memset(v21, 0, 4LL * a2 + 4);\n v21[0] = 1;\n if (a1 > 0) {\n v11 = a1 + 1;\n v12 = 1;\n do {\n v13 = v12;\n if (a2 <= v12) v13 = a2;\n if (v13 > 0) {\n v14 = v13;\n v15 = &v10[v14];\n v16 = v10[v14];\n v17 = (long long)&v10[v14 - 1 - (unsigned int)(v13 - 1)];\n do {\n v18 = v16;\n v16 = *--v15;\n v15[1] = (v16 + v18) % a3;\n } while (v15 != (uint32_t *)v17);\n }\n ++v12;\n } while (v12 != v11);\n }\n return (unsigned int)v10[a2];\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, int a3) {\n long long v5;\n uint32_t *v6;\n short v7;\n signed long long v8;\n void *v9;\n uint32_t *v10;\n int v11;\n int v12;\n int v13;\n long long v14;\n uint32_t *v15;\n int v16;\n long long v17;\n int v18;\n uint32_t v21[1022];\n uint64_t v22[8];\n v22[1] = __readfsqword(40u);\n v5 = 4LL * (a2 + 1) + 15;\n v6 = (uint32_t *)((char *)v22 - (v5 & 18446744073709547520LL));\n v7 = v5 & 65520;\n if (v22 != (uint64_t *)v6) {\n while (v21 != v6)\n ;\n }\n v8 = v7 & 4095;\n v9 = alloca(v8);\n if (v8)\n *(uint64_t *)((char *)&v21[-2] + v8) = *(uint64_t *)((char *)&v21[-2] + v8);\n v10 = v21;\n if (a2 >= 0) v10 = memset(v21, 0, 4LL * a2 + 4);\n v21[0] = 1;\n if (a1 > 0) {\n v11 = a1 + 1;\n v12 = 1;\n do {\n v13 = v12;\n if (a2 <= v12) v13 = a2;\n if (v13 > 0) {\n v14 = v13;\n v15 = &v10[v14];\n v16 = v10[v14];\n v17 = (long long)&v10[v14 - 1 - (unsigned int)(v13 - 1)];\n do {\n v18 = v16;\n v16 = *--v15;\n v15[1] = (v16 + v18) % a3;\n } while (v15 != (uint32_t *)v17);\n }\n ++v12;\n } while (v12 != v11);\n }\n return (unsigned int)v10[a2];\n}" + }, + { + "index": 403, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char *str) {\n regex_t regex;\n const char *pattern =\n \"((http|https)://)(www.)?\"\n \"[a-zA-Z0-9@:%._\\\\+~#?&//=]{2,256}\\\\.[a-z]{2,6}\\\\b([-a-zA-Z0-9@:%\"\n \"._\\\\+~#?&//=]*)\";\n int result;\n bool match;\n if (str == NULL) {\n return false;\n }\n result = regcomp(®ex, pattern, REG_EXTENDED);\n if (result) {\n return false;\n }\n result = regexec(®ex, str, 0, NULL, 0);\n match = (result == 0);\n regfree(®ex);\n return match;\n}", + "test": "int main() {\n\n assert(func0(\"https://www.google.com\") == true);\n\n assert(func0(\"https:/www.gmail.com\") == false);\n\n assert(func0(\"https:// www.redit.com\") == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x70,%rsp\nmov %rdi,-0x68(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0xe19(%rip),%rax\nmov %rax,-0x58(%rbp)\ncmpq $0x0,-0x68(%rbp)\njne 1201 \nmov $0x0,%eax\njmp 1266 \nmov -0x58(%rbp),%rcx\nlea -0x50(%rbp),%rax\nmov $0x1,%edx\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 10c0 \nmov %eax,-0x5c(%rbp)\ncmpl $0x0,-0x5c(%rbp)\nje 1229 \nmov $0x0,%eax\njmp 1266 \nmov -0x68(%rbp),%rsi\nlea -0x50(%rbp),%rax\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rax,%rdi\ncallq 10d0 \nmov %eax,-0x5c(%rbp)\ncmpl $0x0,-0x5c(%rbp)\nsete %al\nmov %al,-0x5d(%rbp)\nlea -0x50(%rbp),%rax\nmov %rax,%rdi\ncallq 1090 \nmovzbl -0x5d(%rbp),%eax\nmov -0x8(%rbp),%rdx\nxor %fs:0x28,%rdx\nje 127a \ncallq 10a0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aHttpHttpsWwwAZ; \"((http|https)://)(www.)?[a-zA-Z0-9@:%._\"...\nmov [rbp+pattern], rax\ncmp [rbp+string], 0\njnz short loc_1201\nmov eax, 0\njmp short loc_1266\nloc_1201:\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+var_5C], eax\ncmp [rbp+var_5C], 0\njz short loc_1229\nmov eax, 0\njmp short loc_1266\nloc_1229:\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_5C], eax\ncmp [rbp+var_5C], 0\nsetz al\nmov [rbp+var_5D], al\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nmovzx eax, [rbp+var_5D]\nloc_1266:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_127A\ncall ___stack_chk_fail\nlocret_127A:\nleave\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(const char *a1)\n{\n bool v2; // [rsp+13h] [rbp-5Dh]\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n unsigned __int64 v4; // [rsp+68h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n if ( !a1 )\n return 0LL;\n if ( regcomp(\n &preg,\n \"((http|https)://)(www.)?[a-zA-Z0-9@:%._\\\\+~#?&//=]{2,256}\\\\.[a-z]{2,6}\\\\b([-a-zA-Z0-9@:%._\\\\+~#?&//=]*)\",\n 1) )\n {\n return 0LL;\n }\n v2 = regexec(&preg, a1, 0LL, 0LL, 0) == 0;\n regfree(&preg);\n return v2;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aHttpHttpsWwwAZ; \"((http|https)://)(www.)?[a-zA-Z0-9@:%._\"...\nmov [rbp+pattern], rax\ncmp [rbp+string], 0\njnz short loc_1201\nmov eax, 0\njmp short loc_1266\nloc_1201:\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+var_5C], eax\ncmp [rbp+var_5C], 0\njz short loc_1229\nmov eax, 0\njmp short loc_1266\nloc_1229:\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_5C], eax\ncmp [rbp+var_5C], 0\nsetz al\nmov [rbp+var_5D], al\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nmovzx eax, [rbp+var_5D]\nloc_1266:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_127A\ncall ___stack_chk_fail\nlocret_127A:\nleave\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_11C9(const char *a1)\n{\n bool v2; // [rsp+13h] [rbp-5Dh]\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n unsigned __int64 v4; // [rsp+68h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n if ( !a1 )\n return 0LL;\n if ( regcomp(\n &preg,\n \"((http|https)://)(www.)?[a-zA-Z0-9@:%._\\\\+~#?&//=]{2,256}\\\\.[a-z]{2,6}\\\\b([-a-zA-Z0-9@:%._\\\\+~#?&//=]*)\",\n 1) )\n {\n return 0LL;\n }\n v2 = regexec(&preg, a1, 0LL, 0LL, 0) == 0;\n regfree(&preg);\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_11C9(const char *a1) {\n bool v2;\n regex_t preg;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n if (!a1) return 0LL;\n if (regcomp(&preg, \"((http|https):\n 1)) {\n return 0LL;\n }\n v2 = regexec(&preg, a1, 0LL, 0LL, 0) == 0;\n regfree(&preg);\n return v2;\n}", + "ida_pseudo_norm": "uint8_t func0(const char *a1) {\n bool v2;\n regex_t preg;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n if (!a1) return 0LL;\n if (regcomp(&preg, \"((http|https):\n 1)) {\n return 0LL;\n }\n v2 = regexec(&preg, a1, 0LL, 0LL, 0) == 0;\n regfree(&preg);\n return v2;\n}" + }, + { + "index": 403, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char *str) {\n regex_t regex;\n const char *pattern =\n \"((http|https)://)(www.)?\"\n \"[a-zA-Z0-9@:%._\\\\+~#?&//=]{2,256}\\\\.[a-z]{2,6}\\\\b([-a-zA-Z0-9@:%\"\n \"._\\\\+~#?&//=]*)\";\n int result;\n bool match;\n if (str == NULL) {\n return false;\n }\n result = regcomp(®ex, pattern, REG_EXTENDED);\n if (result) {\n return false;\n }\n result = regexec(®ex, str, 0, NULL, 0);\n match = (result == 0);\n regfree(®ex);\n return match;\n}", + "test": "int main() {\n\n assert(func0(\"https://www.google.com\") == true);\n\n assert(func0(\"https:/www.gmail.com\") == false);\n\n assert(func0(\"https:// www.redit.com\") == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nsub $0x50,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov $0x0,%ebp\ntest %rdi,%rdi\nje 120a \nmov %rdi,%rbx\nmov %rsp,%rdi\nmov $0x1,%edx\nlea 0xe07(%rip),%rsi\ncallq 10c0 \ntest %eax,%eax\nje 1225 \nmov 0x48(%rsp),%rax\nxor %fs:0x28,%rax\njne 1253 \nmov %ebp,%eax\nadd $0x50,%rsp\npop %rbx\npop %rbp\npop %r12\nretq\nmov %rsp,%r12\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rbx,%rsi\nmov %r12,%rdi\ncallq 10d0 \ntest %eax,%eax\nsete %bpl\nmov %r12,%rdi\ncallq 1090 \njmp 120a \ncallq 10a0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 50h\nmov rax, fs:28h\nmov [rsp+68h+var_20], rax\nxor eax, eax\nmov ebp, 0\ntest rdi, rdi\njz short loc_120A\nmov rbx, rdi\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"((http|https)://)(www.)?[a-zA-Z0-9@:%._\"...\ncall _regcomp\ntest eax, eax\njz short loc_1225\nloc_120A:\nmov rax, [rsp+68h+var_20]\nsub rax, fs:28h\njnz short loc_1253\nmov eax, ebp\nadd rsp, 50h\npop rbx\npop rbp\npop r12\nretn\nloc_1225:\nmov r12, rsp\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\nmov rdi, r12; preg\ncall _regexec\ntest eax, eax\nsetz bpl\nmov rdi, r12; preg\ncall _regfree\njmp short loc_120A\nloc_1253:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(char *string)\n{\n unsigned int v1; // ebp\n regex_t v3; // [rsp+0h] [rbp-68h] BYREF\n unsigned __int64 v4; // [rsp+48h] [rbp-20h]\n\n v4 = __readfsqword(0x28u);\n v1 = 0;\n if ( string\n && !regcomp(\n &v3,\n \"((http|https)://)(www.)?[a-zA-Z0-9@:%._\\\\+~#?&//=]{2,256}\\\\.[a-z]{2,6}\\\\b([-a-zA-Z0-9@:%._\\\\+~#?&//=]*)\",\n 1) )\n {\n LOBYTE(v1) = regexec(&v3, string, 0LL, 0LL, 0) == 0;\n regfree(&v3);\n }\n return v1;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 50h\nmov rax, fs:28h\nmov [rsp+68h+var_20], rax\nxor eax, eax\nmov ebp, 0\ntest rdi, rdi\njz short loc_120A\nmov rbx, rdi\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"((http|https)://)(www.)?[a-zA-Z0-9@:%._\"...\ncall _regcomp\ntest eax, eax\njz short loc_1225\nloc_120A:\nmov rax, [rsp+68h+var_20]\nsub rax, fs:28h\njnz short loc_1253\nmov eax, ebp\nadd rsp, 50h\npop rbx\npop rbp\npop r12\nretn\nloc_1225:\nmov r12, rsp\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\nmov rdi, r12; preg\ncall _regexec\ntest eax, eax\nsetz bpl\nmov rdi, r12; preg\ncall _regfree\njmp short loc_120A\nloc_1253:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_11C9(char *string)\n{\n unsigned int v1; // ebp\n regex_t v3; // [rsp+0h] [rbp-68h] BYREF\n unsigned __int64 v4; // [rsp+48h] [rbp-20h]\n\n v4 = __readfsqword(0x28u);\n v1 = 0;\n if ( string\n && !regcomp(\n &v3,\n \"((http|https)://)(www.)?[a-zA-Z0-9@:%._\\\\+~#?&//=]{2,256}\\\\.[a-z]{2,6}\\\\b([-a-zA-Z0-9@:%._\\\\+~#?&//=]*)\",\n 1) )\n {\n LOBYTE(v1) = regexec(&v3, string, 0LL, 0LL, 0) == 0;\n regfree(&v3);\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11C9(char *string) {\n unsigned int v1;\n regex_t v3;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n v1 = 0;\n if (string && !regcomp(&v3, \"((http|https):\n 1)) {\n LOBYTE(v1) = regexec(&v3, string, 0LL, 0LL, 0) == 0;\n regfree(&v3);\n }\n return v1;\n}", + "ida_pseudo_norm": "long long func0(char *string) {\n unsigned int v1;\n regex_t v3;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n v1 = 0;\n if (string && !regcomp(&v3, \"((http|https):\n 1)) {\n LOBYTE(v1) = regexec(&v3, string, 0LL, 0LL, 0) == 0;\n regfree(&v3);\n }\n return v1;\n}" + }, + { + "index": 403, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char *str) {\n regex_t regex;\n const char *pattern =\n \"((http|https)://)(www.)?\"\n \"[a-zA-Z0-9@:%._\\\\+~#?&//=]{2,256}\\\\.[a-z]{2,6}\\\\b([-a-zA-Z0-9@:%\"\n \"._\\\\+~#?&//=]*)\";\n int result;\n bool match;\n if (str == NULL) {\n return false;\n }\n result = regcomp(®ex, pattern, REG_EXTENDED);\n if (result) {\n return false;\n }\n result = regexec(®ex, str, 0, NULL, 0);\n match = (result == 0);\n regfree(®ex);\n return match;\n}", + "test": "int main() {\n\n assert(func0(\"https://www.google.com\") == true);\n\n assert(func0(\"https:/www.gmail.com\") == false);\n\n assert(func0(\"https:// www.redit.com\") == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %rdi,%rdi\nje 1300 \njmpq 1270 \nxchg %ax,%ax\nxor %eax,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+68h+var_20], rax\nxor eax, eax\ntest rdi, rdi\njz short loc_12AD\nmov rbp, rsp\nmov rbx, rdi\nmov edx, 1; cflags\nlea rsi, pattern; \"((http|https)://)(www.)?[a-zA-Z0-9@:%._\"...\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njz short loc_12D0\nloc_12AD:\nxor ebx, ebx\nloc_12AF:\nmov rax, [rsp+68h+var_20]\nsub rax, fs:28h\njnz short loc_12F1\nadd rsp, 58h\nmov eax, ebx\npop rbx\npop rbp\nretn\nloc_12D0:\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\ntest eax, eax\nsetz bl\ncall _regfree\njmp short loc_12AF\nloc_12F1:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(char *string)\n{\n unsigned int v1; // ebx\n regex_t v3; // [rsp+0h] [rbp-68h] BYREF\n unsigned __int64 v4; // [rsp+48h] [rbp-20h]\n\n v4 = __readfsqword(0x28u);\n if ( string\n && (v1 = (unsigned int)string,\n !regcomp(\n &v3,\n \"((http|https)://)(www.)?[a-zA-Z0-9@:%._\\\\+~#?&//=]{2,256}\\\\.[a-z]{2,6}\\\\b([-a-zA-Z0-9@:%._\\\\+~#?&//=]*)\",\n 1)) )\n {\n LOBYTE(v1) = regexec(&v3, string, 0LL, 0LL, 0) == 0;\n regfree(&v3);\n }\n else\n {\n return 0;\n }\n return v1;\n}", + "ida_strip_asm": "sub_1270:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+68h+var_20], rax\nxor eax, eax\ntest rdi, rdi\njz short loc_12AD\nmov rbp, rsp\nmov rbx, rdi\nmov edx, 1; cflags\nlea rsi, pattern; \"((http|https)://)(www.)?[a-zA-Z0-9@:%._\"...\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njz short loc_12D0\nloc_12AD:\nxor ebx, ebx\nloc_12AF:\nmov rax, [rsp+68h+var_20]\nsub rax, fs:28h\njnz short loc_12F1\nadd rsp, 58h\nmov eax, ebx\npop rbx\npop rbp\nretn\nloc_12D0:\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\ntest eax, eax\nsetz bl\ncall _regfree\njmp short loc_12AF\nloc_12F1:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1270(char *string)\n{\n unsigned int v1; // ebx\n regex_t v3; // [rsp+0h] [rbp-68h] BYREF\n unsigned __int64 v4; // [rsp+48h] [rbp-20h]\n\n v4 = __readfsqword(0x28u);\n if ( string\n && (v1 = (unsigned int)string,\n !regcomp(\n &v3,\n \"((http|https)://)(www.)?[a-zA-Z0-9@:%._\\\\+~#?&//=]{2,256}\\\\.[a-z]{2,6}\\\\b([-a-zA-Z0-9@:%._\\\\+~#?&//=]*)\",\n 1)) )\n {\n LOBYTE(v1) = regexec(&v3, string, 0LL, 0LL, 0) == 0;\n regfree(&v3);\n }\n else\n {\n return 0;\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1270(char *string) {\n unsigned int v1;\n regex_t v3;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n if (string && (v1 = (unsigned int)string, !regcomp(&v3, \"((http|https):\n 1))) {\n LOBYTE(v1) = regexec(&v3, string, 0LL, 0LL, 0) == 0;\n regfree(&v3);\n } else {\n return 0;\n }\n return v1;\n}", + "ida_pseudo_norm": "long long func0(char *string) {\n unsigned int v1;\n regex_t v3;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n if (string && (v1 = (unsigned int)string, !regcomp(&v3, \"((http|https):\n 1))) {\n LOBYTE(v1) = regexec(&v3, string, 0LL, 0LL, 0) == 0;\n regfree(&v3);\n } else {\n return 0;\n }\n return v1;\n}" + }, + { + "index": 403, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char *str) {\n regex_t regex;\n const char *pattern =\n \"((http|https)://)(www.)?\"\n \"[a-zA-Z0-9@:%._\\\\+~#?&//=]{2,256}\\\\.[a-z]{2,6}\\\\b([-a-zA-Z0-9@:%\"\n \"._\\\\+~#?&//=]*)\";\n int result;\n bool match;\n if (str == NULL) {\n return false;\n }\n result = regcomp(®ex, pattern, REG_EXTENDED);\n if (result) {\n return false;\n }\n result = regexec(®ex, str, 0, NULL, 0);\n match = (result == 0);\n regfree(®ex);\n return match;\n}", + "test": "int main() {\n\n assert(func0(\"https://www.google.com\") == true);\n\n assert(func0(\"https:/www.gmail.com\") == false);\n\n assert(func0(\"https:// www.redit.com\") == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\nxor %r12d,%r12d\npush %rbp\nsub $0x50,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\ntest %rdi,%rdi\nje 1333 \nmov %rsp,%r13\nmov %rdi,%rbp\nmov $0x1,%edx\nlea 0xce1(%rip),%rsi\nmov %r13,%rdi\ncallq 10c0 \ntest %eax,%eax\nje 1350 \nmov 0x48(%rsp),%rax\nxor %fs:0x28,%rax\njne 1372 \nadd $0x50,%rsp\nmov %r12d,%eax\npop %rbp\npop %r12\npop %r13\nretq\nxor %r8d,%r8d\nxor %ecx,%ecx\nxor %edx,%edx\nmov %r13,%rdi\nmov %rbp,%rsi\ncallq 10d0 \nmov %r13,%rdi\ntest %eax,%eax\nsete %r12b\ncallq 1090 \njmp 1333 \ncallq 10a0 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+68h+var_20], rax\nxor eax, eax\ntest rdi, rdi\njz short loc_12AD\nmov rbp, rsp\nmov rbx, rdi\nmov edx, 1; cflags\nlea rsi, pattern; \"((http|https)://)(www.)?[a-zA-Z0-9@:%._\"...\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njz short loc_12D0\nloc_12AD:\nxor ebx, ebx\nloc_12AF:\nmov rax, [rsp+68h+var_20]\nsub rax, fs:28h\njnz short loc_12F1\nadd rsp, 58h\nmov eax, ebx\npop rbx\npop rbp\nretn\nloc_12D0:\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\ntest eax, eax\nsetz bl\ncall _regfree\njmp short loc_12AF\nloc_12F1:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(char *string)\n{\n unsigned int v1; // ebx\n regex_t v3; // [rsp+0h] [rbp-68h] BYREF\n unsigned __int64 v4; // [rsp+48h] [rbp-20h]\n\n v4 = __readfsqword(0x28u);\n if ( string\n && (v1 = (unsigned int)string,\n !regcomp(\n &v3,\n \"((http|https)://)(www.)?[a-zA-Z0-9@:%._\\\\+~#?&//=]{2,256}\\\\.[a-z]{2,6}\\\\b([-a-zA-Z0-9@:%._\\\\+~#?&//=]*)\",\n 1)) )\n {\n LOBYTE(v1) = regexec(&v3, string, 0LL, 0LL, 0) == 0;\n regfree(&v3);\n }\n else\n {\n return 0;\n }\n return v1;\n}", + "ida_strip_asm": "sub_1270:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+68h+var_20], rax\nxor eax, eax\ntest rdi, rdi\njz short loc_12AD\nmov rbp, rsp\nmov rbx, rdi\nmov edx, 1; cflags\nlea rsi, pattern; \"((http|https)://)(www.)?[a-zA-Z0-9@:%._\"...\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njz short loc_12D0\nloc_12AD:\nxor ebx, ebx\nloc_12AF:\nmov rax, [rsp+68h+var_20]\nsub rax, fs:28h\njnz short loc_12F1\nadd rsp, 58h\nmov eax, ebx\npop rbx\npop rbp\nretn\nloc_12D0:\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\ntest eax, eax\nsetz bl\ncall _regfree\njmp short loc_12AF\nloc_12F1:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1270(char *string)\n{\n unsigned int v1; // ebx\n regex_t v3; // [rsp+0h] [rbp-68h] BYREF\n unsigned __int64 v4; // [rsp+48h] [rbp-20h]\n\n v4 = __readfsqword(0x28u);\n if ( string\n && (v1 = (unsigned int)string,\n !regcomp(\n &v3,\n \"((http|https)://)(www.)?[a-zA-Z0-9@:%._\\\\+~#?&//=]{2,256}\\\\.[a-z]{2,6}\\\\b([-a-zA-Z0-9@:%._\\\\+~#?&//=]*)\",\n 1)) )\n {\n LOBYTE(v1) = regexec(&v3, string, 0LL, 0LL, 0) == 0;\n regfree(&v3);\n }\n else\n {\n return 0;\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1270(char *string) {\n unsigned int v1;\n regex_t v3;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n if (string && (v1 = (unsigned int)string, !regcomp(&v3, \"((http|https):\n 1))) {\n LOBYTE(v1) = regexec(&v3, string, 0LL, 0LL, 0) == 0;\n regfree(&v3);\n } else {\n return 0;\n }\n return v1;\n}", + "ida_pseudo_norm": "long long func0(char *string) {\n unsigned int v1;\n regex_t v3;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n if (string && (v1 = (unsigned int)string, !regcomp(&v3, \"((http|https):\n 1))) {\n LOBYTE(v1) = regexec(&v3, string, 0LL, 0LL, 0) == 0;\n regfree(&v3);\n } else {\n return 0;\n }\n return v1;\n}" + }, + { + "index": 404, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int a, int b) {\n if (a <= b) {\n return a;\n } else {\n return b;\n }\n}", + "test": "int main() {\n\n assert(func0(1, 2) == 1);\n\n assert(func0(-5, -4) == -5);\n\n assert(func0(0, 0) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov %esi,-0x8(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x8(%rbp),%eax\njg 1164 \nmov -0x4(%rbp),%eax\njmp 1167 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_8]\njg short loc_1164\nmov eax, [rbp+var_4]\njmp short loc_1167\nloc_1164:\nmov eax, [rbp+var_8]\nloc_1167:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1, unsigned int a2)\n{\n if ( (int)a1 > (int)a2 )\n return a2;\n else\n return a1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_8]\njg short loc_1164\nmov eax, [rbp+var_4]\njmp short loc_1167\nloc_1164:\nmov eax, [rbp+var_8]\nloc_1167:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(unsigned int a1, unsigned int a2)\n{\n if ( (int)a1 > (int)a2 )\n return a2;\n else\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(unsigned int a1, unsigned int a2) {\n if ((int)a1 > (int)a2)\n return a2;\n else\n return a1;\n}", + "ida_pseudo_norm": "long long func0(unsigned int a1, unsigned int a2) {\n if ((int)a1 > (int)a2)\n return a2;\n else\n return a1;\n}" + }, + { + "index": 405, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "bool func0(char tuplex[], char tuple1) {\n int i;\n for (i = 0; i < 10; i++) {\n if (tuplex[i] == tuple1) {\n return true;\n }\n }\n return false;\n}", + "test": "int main() {\n\n char tuplex[] = {'w', '3', 'r', 'e', 's', 'o', 'u', 'r', 'c', 'e'};\n\n assert(func0(tuplex, 'r') == true);\n\n assert(func0(tuplex, '5') == false);\n\n assert(func0(tuplex, '3') == true);\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,%eax\nmov %al,-0x1c(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11a3 \nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp %al,-0x1c(%rbp)\njne 119f \nmov $0x1,%eax\njmp 11ae \naddl $0x1,-0x4(%rbp)\ncmpl $0x9,-0x4(%rbp)\njle 1183 \nmov $0x0,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov eax, esi\nmov [rbp+var_1C], al\nmov [rbp+var_4], 0\njmp short loc_11A3\nloc_1183:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp [rbp+var_1C], al\njnz short loc_119F\nmov eax, 1\njmp short loc_11AE\nloc_119F:\nadd [rbp+var_4], 1\nloc_11A3:\ncmp [rbp+var_4], 9\njle short loc_1183\nmov eax, 0\nloc_11AE:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, char a2)\n{\n int i; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i <= 9; ++i )\n {\n if ( a2 == *(_BYTE *)(i + a1) )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov eax, esi\nmov [rbp+var_1C], al\nmov [rbp+var_4], 0\njmp short loc_11A3\nloc_1183:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp [rbp+var_1C], al\njnz short loc_119F\nmov eax, 1\njmp short loc_11AE\nloc_119F:\nadd [rbp+var_4], 1\nloc_11A3:\ncmp [rbp+var_4], 9\njle short loc_1183\nmov eax, 0\nloc_11AE:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, char a2)\n{\n int i; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i <= 9; ++i )\n {\n if ( a2 == *(_BYTE *)(i + a1) )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, char a2) {\n int i;\n for (i = 0; i <= 9; ++i) {\n if (a2 == *(uint8_t *)(i + a1)) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, char a2) {\n int i;\n for (i = 0; i <= 9; ++i) {\n if (a2 == *(uint8_t *)(i + a1)) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 405, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "bool func0(char tuplex[], char tuple1) {\n int i;\n for (i = 0; i < 10; i++) {\n if (tuplex[i] == tuple1) {\n return true;\n }\n }\n return false;\n}", + "test": "int main() {\n\n char tuplex[] = {'w', '3', 'r', 'e', 's', 'o', 'u', 'r', 'c', 'e'};\n\n assert(func0(tuplex, 'r') == true);\n\n assert(func0(tuplex, '5') == false);\n\n assert(func0(tuplex, '3') == true);\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%rax\nadd $0xa,%rdi\ncmp %sil,(%rax)\nje 1188 \nadd $0x1,%rax\ncmp %rdi,%rax\njne 1174 \nmov $0x0,%eax\nretq\nmov $0x1,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov rax, rdi\nadd rdi, 0Ah\nloc_1174:\ncmp [rax], sil\njz short loc_1188\nadd rax, 1\ncmp rax, rdi\njnz short loc_1174\nmov eax, 0\nretn\nloc_1188:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(_BYTE *a1, char a2)\n{\n _BYTE *v2; // rax\n _BYTE *v3; // rdi\n\n v2 = a1;\n v3 = a1 + 10;\n while ( *v2 != a2 )\n {\n if ( ++v2 == v3 )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov rax, rdi\nadd rdi, 0Ah\nloc_1174:\ncmp [rax], sil\njz short loc_1188\nadd rax, 1\ncmp rax, rdi\njnz short loc_1174\nmov eax, 0\nretn\nloc_1188:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_BYTE *a1, char a2)\n{\n _BYTE *v2; // rax\n _BYTE *v3; // rdi\n\n v2 = a1;\n v3 = a1 + 10;\n while ( *v2 != a2 )\n {\n if ( ++v2 == v3 )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint8_t *a1, char a2) {\n uint8_t *v2;\n uint8_t *v3;\n v2 = a1;\n v3 = a1 + 10;\n while (*v2 != a2) {\n if (++v2 == v3) return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(uint8_t *a1, char a2) {\n uint8_t *v2;\n uint8_t *v3;\n v2 = a1;\n v3 = a1 + 10;\n while (*v2 != a2) {\n if (++v2 == v3) return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": 406, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "const char* func0(unsigned int x) {\n unsigned int y = x ^ (x >> 1);\n y = y ^ (y >> 2);\n y = y ^ (y >> 4);\n y = y ^ (y >> 8);\n y = y ^ (y >> 16);\n if (y & 1) {\n return \"Odd Parity\";\n }\n return \"Even Parity\";\n}", + "test": "int main() {\n\n assert(strcmp(func0(12), \"Even Parity\") == 0);\n\n assert(strcmp(func0(7), \"Odd Parity\") == 0);\n\n assert(strcmp(func0(10), \"Even Parity\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov -0x14(%rbp),%eax\nshr %eax\nxor -0x14(%rbp),%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nshr $0x2,%eax\nxor %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nshr $0x4,%eax\nxor %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nshr $0x8,%eax\nxor %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nshr $0x10,%eax\nxor %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nand $0x1,%eax\ntest %eax,%eax\nje 11b6 \nlea 0xe54(%rip),%rax\njmp 11bd \nlea 0xe56(%rip),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov eax, [rbp+var_14]\nshr eax, 1\nxor eax, [rbp+var_14]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\nshr eax, 2\nxor [rbp+var_4], eax\nmov eax, [rbp+var_4]\nshr eax, 4\nxor [rbp+var_4], eax\nmov eax, [rbp+var_4]\nshr eax, 8\nxor [rbp+var_4], eax\nmov eax, [rbp+var_4]\nshr eax, 10h\nxor [rbp+var_4], eax\nmov eax, [rbp+var_4]\nand eax, 1\ntest eax, eax\njz short loc_11B6\nlea rax, aOddParity; \"Odd Parity\"\njmp short loc_11BD\nloc_11B6:\nlea rax, s2; \"Even Parity\"\nloc_11BD:\npop rbp\nretn", + "ida_pseudo": "const char *__fastcall func0(unsigned int a1)\n{\n unsigned int v2; // [rsp+10h] [rbp-4h]\n unsigned int v3; // [rsp+10h] [rbp-4h]\n\n v2 = ((a1 ^ (a1 >> 1)) >> 2) ^ a1 ^ (a1 >> 1);\n v3 = (((v2 >> 4) ^ v2) >> 8) ^ (v2 >> 4) ^ v2;\n if ( ((BYTE2(v3) ^ (unsigned __int8)v3) & 1) != 0 )\n return \"Odd Parity\";\n else\n return \"Even Parity\";\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov eax, [rbp+var_14]\nshr eax, 1\nxor eax, [rbp+var_14]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\nshr eax, 2\nxor [rbp+var_4], eax\nmov eax, [rbp+var_4]\nshr eax, 4\nxor [rbp+var_4], eax\nmov eax, [rbp+var_4]\nshr eax, 8\nxor [rbp+var_4], eax\nmov eax, [rbp+var_4]\nshr eax, 10h\nxor [rbp+var_4], eax\nmov eax, [rbp+var_4]\nand eax, 1\ntest eax, eax\njz short loc_11B6\nlea rax, aOddParity; \"Odd Parity\"\njmp short loc_11BD\nloc_11B6:\nlea rax, s2; \"Even Parity\"\nloc_11BD:\npop rbp\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1169(unsigned int a1)\n{\n unsigned int v2; // [rsp+10h] [rbp-4h]\n unsigned int v3; // [rsp+10h] [rbp-4h]\n\n v2 = ((a1 ^ (a1 >> 1)) >> 2) ^ a1 ^ (a1 >> 1);\n v3 = (((v2 >> 4) ^ v2) >> 8) ^ (v2 >> 4) ^ v2;\n if ( ((BYTE2(v3) ^ (unsigned __int8)v3) & 1) != 0 )\n return \"Odd Parity\";\n else\n return \"Even Parity\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char* sub_1169(unsigned int a1) {\n unsigned int v2;\n unsigned int v3;\n v2 = ((a1 ^ (a1 >> 1)) >> 2) ^ a1 ^ (a1 >> 1);\n v3 = (((v2 >> 4) ^ v2) >> 8) ^ (v2 >> 4) ^ v2;\n if (((BYTE2(v3) ^ (unsigned char)v3) & 1) != 0)\n return \"Odd Parity\";\n else\n return \"Even Parity\";\n}", + "ida_pseudo_norm": "const char* func0(unsigned int a1) {\n unsigned int v2;\n unsigned int v3;\n v2 = ((a1 ^ (a1 >> 1)) >> 2) ^ a1 ^ (a1 >> 1);\n v3 = (((v2 >> 4) ^ v2) >> 8) ^ (v2 >> 4) ^ v2;\n if (((BYTE2(v3) ^ (unsigned char)v3) & 1) != 0)\n return \"Odd Parity\";\n else\n return \"Even Parity\";\n}" + }, + { + "index": 407, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n char nums[11];\n sprintf(nums, \"%d\", n);\n size_t length = strlen(nums);\n for (int i = length - 2; i >= 0; --i) {\n if (nums[i] < nums[i + 1]) {\n char z[11];\n strcpy(z, nums + i);\n size_t z_len = strlen(z);\n char y = z[1];\n for (size_t j = 1; j < z_len; ++j) {\n if (z[j] > z[0] && z[j] < y) {\n y = z[j];\n }\n }\n for (size_t j = 0; j < z_len; ++j) {\n if (z[j] == y) {\n for (size_t k = j; k < z_len - 1; ++k) {\n z[k] = z[k + 1];\n }\n z[z_len - 1] = '\\0';\n break;\n }\n }\n qsort(z, strlen(z), sizeof(char),\n (int (*)(const void *, const void *))strcmp);\n nums[i] = y;\n strcpy(nums + i + 1, z);\n return atoi(nums);\n }\n }\n return 0;\n}", + "test": "int main() {\n\n assert(func0(12) == 21);\n\n assert(func0(10) == 0);\n\n assert(func0(102) == 120);\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x60,%rsp\nmov %edi,-0x54(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmov -0x54(%rbp),%edx\nlea -0x1e(%rbp),%rax\nlea 0xdb3(%rip),%rsi\nmov %rax,%rdi\nmov $0x0,%eax\ncallq 1130 \nlea -0x1e(%rbp),%rax\nmov %rax,%rdi\ncallq 10f0 \nmov %rax,-0x30(%rbp)\nmov -0x30(%rbp),%rax\nsub $0x2,%eax\nmov %eax,-0x4c(%rbp)\njmpq 13ff \nmov -0x4c(%rbp),%eax\ncltq\nmovzbl -0x1e(%rbp,%rax,1),%edx\nmov -0x4c(%rbp),%eax\nadd $0x1,%eax\ncltq\nmovzbl -0x1e(%rbp,%rax,1),%eax\ncmp %al,%dl\njge 13fb \nmov -0x4c(%rbp),%eax\ncltq\nlea -0x1e(%rbp),%rdx\nadd %rax,%rdx\nlea -0x13(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10c0 \nlea -0x13(%rbp),%rax\nmov %rax,%rdi\ncallq 10f0 \nmov %rax,-0x28(%rbp)\nmovzbl -0x12(%rbp),%eax\nmov %al,-0x4d(%rbp)\nmovq $0x1,-0x48(%rbp)\njmp 131b \nlea -0x13(%rbp),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%edx\nmovzbl -0x13(%rbp),%eax\ncmp %al,%dl\njle 1316 \nlea -0x13(%rbp),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp %al,-0x4d(%rbp)\njle 1316 \nlea -0x13(%rbp),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmov %al,-0x4d(%rbp)\naddq $0x1,-0x48(%rbp)\nmov -0x48(%rbp),%rax\ncmp -0x28(%rbp),%rax\njb 12dc \nmovq $0x0,-0x40(%rbp)\njmp 138d \nlea -0x13(%rbp),%rdx\nmov -0x40(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp %al,-0x4d(%rbp)\njne 1388 \nmov -0x40(%rbp),%rax\nmov %rax,-0x38(%rbp)\njmp 136b \nmov -0x38(%rbp),%rax\nadd $0x1,%rax\nmovzbl -0x13(%rbp,%rax,1),%eax\nlea -0x13(%rbp),%rcx\nmov -0x38(%rbp),%rdx\nadd %rcx,%rdx\nmov %al,(%rdx)\naddq $0x1,-0x38(%rbp)\nmov -0x28(%rbp),%rax\nsub $0x1,%rax\ncmp %rax,-0x38(%rbp)\njb 134c \nmov -0x28(%rbp),%rax\nsub $0x1,%rax\nmovb $0x0,-0x13(%rbp,%rax,1)\njmp 1397 \naddq $0x1,-0x40(%rbp)\nmov -0x40(%rbp),%rax\ncmp -0x28(%rbp),%rax\njb 132f \nlea -0x13(%rbp),%rax\nmov %rax,%rdi\ncallq 10f0 \nmov %rax,%rsi\nlea -0x13(%rbp),%rax\nmov 0x2c2f(%rip),%rdx\nmov %rdx,%rcx\nmov $0x1,%edx\nmov %rax,%rdi\ncallq 10e0 \nmov -0x4c(%rbp),%eax\ncltq\nmovzbl -0x4d(%rbp),%edx\nmov %dl,-0x1e(%rbp,%rax,1)\nmov -0x4c(%rbp),%eax\ncltq\nlea 0x1(%rax),%rdx\nlea -0x1e(%rbp),%rax\nadd %rax,%rdx\nlea -0x13(%rbp),%rax\nmov %rax,%rsi\nmov %rdx,%rdi\ncallq 10c0 \nlea -0x1e(%rbp),%rax\nmov %rax,%rdi\ncallq 1120 \njmp 140e \nsubl $0x1,-0x4c(%rbp)\ncmpl $0x0,-0x4c(%rbp)\njns 1281 \nmov $0x0,%eax\nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 1422 \ncallq 1100 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 60h\nmov [rbp+var_54], edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov edx, [rbp+var_54]\nlea rax, [rbp+s]\nlea rcx, format; \"%d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_30], rax\nmov rax, [rbp+var_30]\nsub eax, 2\nmov [rbp+var_4C], eax\njmp loc_1402\nloc_1284:\nmov eax, [rbp+var_4C]\ncdqe\nmovzx edx, [rbp+rax+s]\nmov eax, [rbp+var_4C]\nadd eax, 1\ncdqe\nmovzx eax, [rbp+rax+s]\ncmp dl, al\njge loc_13FE\nmov eax, [rbp+var_4C]\ncdqe\nlea rdx, [rbp+s]\nadd rdx, rax\nlea rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\nlea rax, [rbp+dest]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_28], rax\nmovzx eax, [rbp+var_12]\nmov [rbp+var_4D], al\nmov [rbp+var_48], 1\njmp short loc_131E\nloc_12DF:\nlea rdx, [rbp+dest]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmovzx eax, [rbp+dest]\ncmp dl, al\njle short loc_1319\nlea rdx, [rbp+dest]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp [rbp+var_4D], al\njle short loc_1319\nlea rdx, [rbp+dest]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_4D], al\nloc_1319:\nadd [rbp+var_48], 1\nloc_131E:\nmov rax, [rbp+var_48]\ncmp rax, [rbp+var_28]\njb short loc_12DF\nmov [rbp+var_40], 0\njmp short loc_1390\nloc_1332:\nlea rdx, [rbp+dest]\nmov rax, [rbp+var_40]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp [rbp+var_4D], al\njnz short loc_138B\nmov rax, [rbp+var_40]\nmov [rbp+var_38], rax\njmp short loc_136E\nloc_134F:\nmov rax, [rbp+var_38]\nadd rax, 1\nmovzx eax, [rbp+rax+dest]\nlea rcx, [rbp+dest]\nmov rdx, [rbp+var_38]\nadd rdx, rcx\nmov [rdx], al\nadd [rbp+var_38], 1\nloc_136E:\nmov rax, [rbp+var_28]\nsub rax, 1\ncmp [rbp+var_38], rax\njb short loc_134F\nmov rax, [rbp+var_28]\nsub rax, 1\nmov [rbp+rax+dest], 0\njmp short loc_139A\nloc_138B:\nadd [rbp+var_40], 1\nloc_1390:\nmov rax, [rbp+var_40]\ncmp rax, [rbp+var_28]\njb short loc_1332\nloc_139A:\nlea rax, [rbp+dest]\nmov rdi, rax; s\ncall _strlen\nmov rsi, rax; nmemb\nlea rax, [rbp+dest]\nmov rdx, cs:compar\nmov rcx, rdx; compar\nmov edx, 1; size\nmov rdi, rax; base\ncall _qsort\nmov eax, [rbp+var_4C]\ncdqe\nmovzx edx, [rbp+var_4D]\nmov [rbp+rax+s], dl\nmov eax, [rbp+var_4C]\ncdqe\nlea rdx, [rax+1]\nlea rax, [rbp+s]\nadd rdx, rax\nlea rax, [rbp+dest]\nmov rsi, rax; src\nmov rdi, rdx; dest\ncall _strcpy\nlea rax, [rbp+s]\nmov rdi, rax; nptr\ncall _atoi\njmp short loc_1411\nloc_13FE:\nsub [rbp+var_4C], 1\nloc_1402:\ncmp [rbp+var_4C], 0\njns loc_1284\nmov eax, 0\nloc_1411:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1425\ncall ___stack_chk_fail\nlocret_1425:\nleave\nretn", + "ida_pseudo": "int __fastcall func0(int a1)\n{\n size_t v1; // rax\n char v3; // [rsp+13h] [rbp-4Dh]\n int i; // [rsp+14h] [rbp-4Ch]\n unsigned __int64 j; // [rsp+18h] [rbp-48h]\n size_t k; // [rsp+20h] [rbp-40h]\n unsigned __int64 m; // [rsp+28h] [rbp-38h]\n size_t v8; // [rsp+38h] [rbp-28h]\n char s[11]; // [rsp+42h] [rbp-1Eh] BYREF\n char dest[11]; // [rsp+4Dh] [rbp-13h] BYREF\n unsigned __int64 v11; // [rsp+58h] [rbp-8h]\n\n v11 = __readfsqword(0x28u);\n sprintf(s, \"%d\", a1);\n for ( i = strlen(s) - 2; ; --i )\n {\n if ( i < 0 )\n return 0;\n if ( s[i] < s[i + 1] )\n break;\n }\n strcpy(dest, &s[i]);\n v8 = strlen(dest);\n v3 = dest[1];\n for ( j = 1LL; j < v8; ++j )\n {\n if ( dest[j] > dest[0] && v3 > dest[j] )\n v3 = dest[j];\n }\n for ( k = 0LL; k < v8; ++k )\n {\n if ( v3 == dest[k] )\n {\n for ( m = k; m < v8 - 1; ++m )\n dest[m] = dest[m + 1];\n dest[v8 - 1] = 0;\n break;\n }\n }\n v1 = strlen(dest);\n qsort(dest, v1, 1uLL, (__compar_fn_t)&strcmp);\n s[i] = v3;\n strcpy(&s[i + 1], dest);\n return atoi(s);\n}", + "ida_strip_asm": "sub_1229:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 60h\nmov [rbp+var_54], edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov edx, [rbp+var_54]\nlea rax, [rbp+s]\nlea rcx, format; \"%d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_30], rax\nmov rax, [rbp+var_30]\nsub eax, 2\nmov [rbp+var_4C], eax\njmp loc_1402\nloc_1284:\nmov eax, [rbp+var_4C]\ncdqe\nmovzx edx, [rbp+rax+s]\nmov eax, [rbp+var_4C]\nadd eax, 1\ncdqe\nmovzx eax, [rbp+rax+s]\ncmp dl, al\njge loc_13FE\nmov eax, [rbp+var_4C]\ncdqe\nlea rdx, [rbp+s]\nadd rdx, rax\nlea rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\nlea rax, [rbp+dest]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_28], rax\nmovzx eax, [rbp+var_12]\nmov [rbp+var_4D], al\nmov [rbp+var_48], 1\njmp short loc_131E\nloc_12DF:\nlea rdx, [rbp+dest]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmovzx eax, [rbp+dest]\ncmp dl, al\njle short loc_1319\nlea rdx, [rbp+dest]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp [rbp+var_4D], al\njle short loc_1319\nlea rdx, [rbp+dest]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_4D], al\nloc_1319:\nadd [rbp+var_48], 1\nloc_131E:\nmov rax, [rbp+var_48]\ncmp rax, [rbp+var_28]\njb short loc_12DF\nmov [rbp+var_40], 0\njmp short loc_1390\nloc_1332:\nlea rdx, [rbp+dest]\nmov rax, [rbp+var_40]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp [rbp+var_4D], al\njnz short loc_138B\nmov rax, [rbp+var_40]\nmov [rbp+var_38], rax\njmp short loc_136E\nloc_134F:\nmov rax, [rbp+var_38]\nadd rax, 1\nmovzx eax, [rbp+rax+dest]\nlea rcx, [rbp+dest]\nmov rdx, [rbp+var_38]\nadd rdx, rcx\nmov [rdx], al\nadd [rbp+var_38], 1\nloc_136E:\nmov rax, [rbp+var_28]\nsub rax, 1\ncmp [rbp+var_38], rax\njb short loc_134F\nmov rax, [rbp+var_28]\nsub rax, 1\nmov [rbp+rax+dest], 0\njmp short loc_139A\nloc_138B:\nadd [rbp+var_40], 1\nloc_1390:\nmov rax, [rbp+var_40]\ncmp rax, [rbp+var_28]\njb short loc_1332\nloc_139A:\nlea rax, [rbp+dest]\nmov rdi, rax; s\ncall _strlen\nmov rsi, rax; nmemb\nlea rax, [rbp+dest]\nmov rdx, cs:compar\nmov rcx, rdx; compar\nmov edx, 1; size\nmov rdi, rax; base\ncall _qsort\nmov eax, [rbp+var_4C]\ncdqe\nmovzx edx, [rbp+var_4D]\nmov [rbp+rax+s], dl\nmov eax, [rbp+var_4C]\ncdqe\nlea rdx, [rax+1]\nlea rax, [rbp+s]\nadd rdx, rax\nlea rax, [rbp+dest]\nmov rsi, rax; src\nmov rdi, rdx; dest\ncall _strcpy\nlea rax, [rbp+s]\nmov rdi, rax; nptr\ncall _atoi\njmp short loc_1411\nloc_13FE:\nsub [rbp+var_4C], 1\nloc_1402:\ncmp [rbp+var_4C], 0\njns loc_1284\nmov eax, 0\nloc_1411:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1425\ncall ___stack_chk_fail\nlocret_1425:\nleave\nretn", + "ida_strip_pseudo": "int __fastcall sub_1229(int a1)\n{\n size_t v1; // rax\n char v3; // [rsp+13h] [rbp-4Dh]\n int i; // [rsp+14h] [rbp-4Ch]\n unsigned __int64 j; // [rsp+18h] [rbp-48h]\n size_t k; // [rsp+20h] [rbp-40h]\n unsigned __int64 m; // [rsp+28h] [rbp-38h]\n size_t v8; // [rsp+38h] [rbp-28h]\n char s[11]; // [rsp+42h] [rbp-1Eh] BYREF\n char dest[11]; // [rsp+4Dh] [rbp-13h] BYREF\n unsigned __int64 v11; // [rsp+58h] [rbp-8h]\n\n v11 = __readfsqword(0x28u);\n sprintf(s, \"%d\", a1);\n for ( i = strlen(s) - 2; ; --i )\n {\n if ( i < 0 )\n return 0;\n if ( s[i] < s[i + 1] )\n break;\n }\n strcpy(dest, &s[i]);\n v8 = strlen(dest);\n v3 = dest[1];\n for ( j = 1LL; j < v8; ++j )\n {\n if ( dest[j] > dest[0] && v3 > dest[j] )\n v3 = dest[j];\n }\n for ( k = 0LL; k < v8; ++k )\n {\n if ( v3 == dest[k] )\n {\n for ( m = k; m < v8 - 1; ++m )\n dest[m] = dest[m + 1];\n dest[v8 - 1] = 0;\n break;\n }\n }\n v1 = strlen(dest);\n qsort(dest, v1, 1uLL, (__compar_fn_t)&strcmp);\n s[i] = v3;\n strcpy(&s[i + 1], dest);\n return atoi(s);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "int sub_1229(int a1) {\n unsigned int v1;\n char v3;\n int i;\n unsigned long long j;\n unsigned int k;\n unsigned long long m;\n unsigned int v8;\n char s[11];\n char dest[11];\n unsigned long long v11;\n v11 = __readfsqword(40u);\n sprintf(s, \"%d\", a1);\n for (i = strlen(s) - 2;; --i) {\n if (i < 0) return 0;\n if (s[i] < s[i + 1]) break;\n }\n strcpy(dest, &s[i]);\n v8 = strlen(dest);\n v3 = dest[1];\n for (j = 1LL; j < v8; ++j) {\n if (dest[j] > dest[0] && v3 > dest[j]) v3 = dest[j];\n }\n for (k = 0LL; k < v8; ++k) {\n if (v3 == dest[k]) {\n for (m = k; m < v8 - 1; ++m) dest[m] = dest[m + 1];\n dest[v8 - 1] = 0;\n break;\n }\n }\n v1 = strlen(dest);\n qsort(dest, v1, 1uLL, (int (*)(const void *, const void *)) & strcmp);\n s[i] = v3;\n strcpy(&s[i + 1], dest);\n return atoi(s);\n}", + "ida_pseudo_norm": "int func0(int a1) {\n unsigned int v1;\n char v3;\n int i;\n unsigned long long j;\n unsigned int k;\n unsigned long long m;\n unsigned int v8;\n char s[11];\n char dest[11];\n unsigned long long v11;\n v11 = __readfsqword(40u);\n sprintf(s, \"%d\", a1);\n for (i = strlen(s) - 2;; --i) {\n if (i < 0) return 0;\n if (s[i] < s[i + 1]) break;\n }\n strcpy(dest, &s[i]);\n v8 = strlen(dest);\n v3 = dest[1];\n for (j = 1LL; j < v8; ++j) {\n if (dest[j] > dest[0] && v3 > dest[j]) v3 = dest[j];\n }\n for (k = 0LL; k < v8; ++k) {\n if (v3 == dest[k]) {\n for (m = k; m < v8 - 1; ++m) dest[m] = dest[m + 1];\n dest[v8 - 1] = 0;\n break;\n }\n }\n v1 = strlen(dest);\n qsort(dest, v1, 1uLL, (int (*)(const void *, const void *)) & strcmp);\n s[i] = v3;\n strcpy(&s[i + 1], dest);\n return atoi(s);\n}" + }, + { + "index": 407, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n char nums[11];\n sprintf(nums, \"%d\", n);\n size_t length = strlen(nums);\n for (int i = length - 2; i >= 0; --i) {\n if (nums[i] < nums[i + 1]) {\n char z[11];\n strcpy(z, nums + i);\n size_t z_len = strlen(z);\n char y = z[1];\n for (size_t j = 1; j < z_len; ++j) {\n if (z[j] > z[0] && z[j] < y) {\n y = z[j];\n }\n }\n for (size_t j = 0; j < z_len; ++j) {\n if (z[j] == y) {\n for (size_t k = j; k < z_len - 1; ++k) {\n z[k] = z[k + 1];\n }\n z[z_len - 1] = '\\0';\n break;\n }\n }\n qsort(z, strlen(z), sizeof(char),\n (int (*)(const void *, const void *))strcmp);\n nums[i] = y;\n strcpy(nums + i + 1, z);\n return atoi(nums);\n }\n }\n return 0;\n}", + "test": "int main() {\n\n assert(func0(12) == 21);\n\n assert(func0(10) == 0);\n\n assert(func0(102) == 120);\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x28,%rsp\nmov %edi,%r8d\nmov %fs:0x28,%rax\nmov %rax,0x18(%rsp)\nxor %eax,%eax\nlea 0x2(%rsp),%rbx\nlea 0xdae(%rip),%rcx\nmov $0xb,%edx\nmov $0x1,%esi\nmov %rbx,%rdi\ncallq 1130 <__sprintf_chk@plt>\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nmov %rbx,%rdi\nrepnz scas %es:(%rdi),%al\nnot %rcx\nsub $0x1,%rcx\nmov %ecx,%edx\nsub $0x2,%ecx\njs 13e3 \nmovslq %ecx,%rcx\nmov %rcx,%rax\nlea 0x2(%rsp),%rsi\nsub $0x1,%edx\nmovslq %edx,%rdx\nsub %rcx,%rdx\nadd %rsi,%rdx\nmov %eax,%ebx\nmovzbl (%rdx,%rax,1),%edi\ncmp %dil,(%rsi,%rax,1)\njl 12c0 \nsub $0x1,%rax\ntest %eax,%eax\njns 12a2 \nmov $0x0,%eax\njmpq 13c8 \nmovslq %eax,%r12\nlea 0x2(%rsp,%r12,1),%rsi\nlea 0xd(%rsp),%rbp\nmov $0xb,%edx\nmov %rbp,%rdi\ncallq 1120 <__strcpy_chk@plt>\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nmov %rbp,%rdi\nrepnz scas %es:(%rdi),%al\nnot %rcx\nsub $0x1,%rcx\nmovzbl 0xe(%rsp),%ebp\ncmp $0x1,%rcx\njbe 1327 \nmovzbl 0xd(%rsp),%edi\nlea 0xe(%rsp),%rax\nlea 0xd(%rsp,%rcx,1),%rsi\njmp 1317 \nadd $0x1,%rax\ncmp %rsi,%rax\nje 132c \nmovzbl (%rax),%edx\ncmp %dil,%dl\njle 130e \ncmp %dl,%bpl\ncmovg %edx,%ebp\njmp 130e \ntest %rcx,%rcx\nje 136e \nmov $0x0,%eax\nlea 0xd(%rsp),%rdx\ncmp %bpl,(%rax,%rdx,1)\nje 1347 \nadd $0x1,%rax\ncmp %rax,%rcx\nja 1336 \njmp 136e \nlea -0x1(%rcx),%rsi\ncmp %rax,%rsi\njbe 1369 \nlea 0xd(%rsp,%rax,1),%rax\nlea 0xc(%rsp,%rcx,1),%rcx\nmovzbl 0x1(%rax),%edx\nmov %dl,(%rax)\nadd $0x1,%rax\ncmp %rcx,%rax\njne 135a \nmovb $0x0,0xd(%rsp,%rsi,1)\nlea 0xd(%rsp),%r13\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nmov %r13,%rdi\nrepnz scas %es:(%rdi),%al\nnot %rcx\nlea -0x1(%rcx),%rsi\nmov 0x2c4e(%rip),%rcx\nmov $0x1,%edx\nmov %r13,%rdi\ncallq 10e0 \nmovslq %ebx,%rbx\nmov %bpl,0x2(%rsp,%rbx,1)\nlea 0x3(%rsp,%r12,1),%rdi\nmov %r13,%rsi\ncallq 10c0 \nmov $0xa,%edx\nmov $0x0,%esi\nlea 0x2(%rsp),%rdi\ncallq 1110 \nmov 0x18(%rsp),%rbx\nxor %fs:0x28,%rbx\njne 13ea \nadd $0x28,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nmov $0x0,%eax\njmp 13c8 \ncallq 10f0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov r8d, edi\nmov rax, fs:28h\nmov [rsp+48h+var_30], rax\nxor eax, eax\nlea rbx, [rsp+48h+s]\nlea rcx, unk_2004\nmov edx, 0Bh\nmov esi, 2\nmov rdi, rbx\ncall ___sprintf_chk\nmov rdi, rbx; s\ncall _strlen\nmov edx, eax\nsub eax, 2\njs loc_13CB\nmovsxd rcx, eax\nmov rax, rcx\nmov rsi, rbx\nsub edx, 1\nmovsxd rdx, edx\nsub rdx, rcx\nadd rdx, rbx\nloc_1290:\nmovzx ebx, byte ptr [rdx+rax]\ncmp [rsi+rax], bl\njl short loc_12AB\nsub rax, 1\ntest eax, eax\njns short loc_1290\nmov eax, 0\njmp loc_13B0\nloc_12AB:\nmov r12d, eax\nmovsxd rbx, eax\nlea rsi, [rsp+rbx+48h+s]\nlea rbp, [rsp+48h+base]\nmov edx, 0Bh\nmov rdi, rbp\ncall ___strcpy_chk\nmov rdi, rbp; s\ncall _strlen\nmovzx ebp, [rsp+48h+var_3A]\ncmp rax, 1\njbe short loc_1320\nmovzx r8d, [rsp+48h+base]\nlea rdx, [rsp+48h+var_3A]\nlea rdi, [rsp+rax+48h+base]\nloc_12EB:\nmovzx ecx, byte ptr [rdx]\ncmp bpl, cl\nmov esi, ecx\ncmovle esi, ebp\ncmp cl, r8b\ncmovg ebp, esi\nadd rdx, 1\ncmp rdx, rdi\njnz short loc_12EB\nloc_1305:\nmov edx, 0\nlea rcx, [rsp+48h+base]\nloc_130F:\ncmp [rdx+rcx], bpl\njz short loc_1327\nadd rdx, 1\ncmp rax, rdx\njnz short loc_130F\njmp short loc_134E\nloc_1320:\ntest rax, rax\njz short loc_134E\njmp short loc_1305\nloc_1327:\nlea rsi, [rax-1]\ncmp rdx, rsi\njnb short loc_1349\nlea rdx, [rsp+rdx+48h+base]\nlea rcx, [rsp+rax+48h+var_3C]\nloc_133A:\nmovzx eax, byte ptr [rdx+1]\nmov [rdx], al\nadd rdx, 1\ncmp rdx, rcx\njnz short loc_133A\nloc_1349:\nmov [rsp+rsi+48h+base], 0\nloc_134E:\nlea r13, [rsp+48h+base]\nmov rdi, r13; s\ncall _strlen\nmov rsi, rax; nmemb\nmov rcx, cs:compar; compar\nmov edx, 1; size\nmov rdi, r13; base\ncall _qsort\nmovsxd r12, r12d\nmov [rsp+r12+48h+s], bpl\nlea rax, [rbx+1]\nmov edx, 0Bh\ncmp rax, rdx\ncmovnb rdx, rax\nsub rdx, rax\nlea rbx, [rsp+48h+s]\nlea rdi, [rbx+rax]\nmov rsi, r13\ncall ___strcpy_chk\nmov edx, 0Ah; base\nmov esi, 0; endptr\nmov rdi, rbx; nptr\ncall _strtol\nloc_13B0:\nmov rdx, [rsp+48h+var_30]\nsub rdx, fs:28h\njnz short loc_13D2\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_13CB:\nmov eax, 0\njmp short loc_13B0\nloc_13D2:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1)\n{\n int v1; // edx\n __int64 v2; // rax\n char *v3; // rdx\n int v5; // r12d\n __int64 v6; // rbx\n size_t v7; // rax\n int v8; // ebp\n char *v9; // rdx\n int v10; // esi\n unsigned __int64 v11; // rdx\n char *v12; // rdx\n size_t v13; // rax\n __int64 v14; // rdx\n char s[11]; // [rsp+2h] [rbp-46h] BYREF\n char base; // [rsp+Dh] [rbp-3Bh] BYREF\n unsigned __int8 v17; // [rsp+Eh] [rbp-3Ah] BYREF\n unsigned __int64 v18; // [rsp+18h] [rbp-30h]\n\n v18 = __readfsqword(0x28u);\n __sprintf_chk(s, 2LL, 11LL, &unk_2004, a1);\n v1 = strlen(s);\n LODWORD(v2) = v1 - 2;\n if ( v1 - 2 < 0 )\n return 0LL;\n v2 = (int)v2;\n v3 = &s[v1 - 1 - (__int64)(int)v2];\n while ( s[v2] >= v3[v2] )\n {\n if ( (int)--v2 < 0 )\n return 0LL;\n }\n v5 = v2;\n v6 = (int)v2;\n __strcpy_chk(&base, &s[(int)v2], 11LL);\n v7 = strlen(&base);\n v8 = v17;\n if ( v7 > 1 )\n {\n v9 = (char *)&v17;\n do\n {\n v10 = (unsigned __int8)*v9;\n if ( (char)v8 <= *v9 )\n v10 = v8;\n if ( *v9 > base )\n v8 = v10;\n ++v9;\n }\n while ( v9 != &base + v7 );\nLABEL_13:\n v11 = 0LL;\n while ( *(&base + v11) != (_BYTE)v8 )\n {\n if ( v7 == ++v11 )\n goto LABEL_23;\n }\n if ( v11 < v7 - 1 )\n {\n v12 = &base + v11;\n do\n {\n *v12 = v12[1];\n ++v12;\n }\n while ( v12 != &s[v7 + 10] );\n }\n *(&base + v7 - 1) = 0;\n goto LABEL_23;\n }\n if ( v7 )\n goto LABEL_13;\nLABEL_23:\n v13 = strlen(&base);\n qsort(&base, v13, 1uLL, (__compar_fn_t)&strcmp);\n s[v5] = v8;\n v14 = 11LL;\n if ( (unsigned __int64)(v6 + 1) >= 0xB )\n v14 = v6 + 1;\n __strcpy_chk(&s[v6 + 1], &base, v14 - (v6 + 1));\n return strtol(s, 0LL, 10);\n}", + "ida_strip_asm": "sub_1229:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov r8d, edi\nmov rax, fs:28h\nmov [rsp+48h+var_30], rax\nxor eax, eax\nlea rbx, [rsp+48h+s]\nlea rcx, unk_2004\nmov edx, 0Bh\nmov esi, 2\nmov rdi, rbx\ncall ___sprintf_chk\nmov rdi, rbx; s\ncall _strlen\nmov edx, eax\nsub eax, 2\njs loc_13CB\nmovsxd rcx, eax\nmov rax, rcx\nmov rsi, rbx\nsub edx, 1\nmovsxd rdx, edx\nsub rdx, rcx\nadd rdx, rbx\nloc_1290:\nmovzx ebx, byte ptr [rdx+rax]\ncmp [rsi+rax], bl\njl short loc_12AB\nsub rax, 1\ntest eax, eax\njns short loc_1290\nmov eax, 0\njmp loc_13B0\nloc_12AB:\nmov r12d, eax\nmovsxd rbx, eax\nlea rsi, [rsp+rbx+48h+s]\nlea rbp, [rsp+48h+base]\nmov edx, 0Bh\nmov rdi, rbp\ncall ___strcpy_chk\nmov rdi, rbp; s\ncall _strlen\nmovzx ebp, [rsp+48h+var_3A]\ncmp rax, 1\njbe short loc_1320\nmovzx r8d, [rsp+48h+base]\nlea rdx, [rsp+48h+var_3A]\nlea rdi, [rsp+rax+48h+base]\nloc_12EB:\nmovzx ecx, byte ptr [rdx]\ncmp bpl, cl\nmov esi, ecx\ncmovle esi, ebp\ncmp cl, r8b\ncmovg ebp, esi\nadd rdx, 1\ncmp rdx, rdi\njnz short loc_12EB\nloc_1305:\nmov edx, 0\nlea rcx, [rsp+48h+base]\nloc_130F:\ncmp [rdx+rcx], bpl\njz short loc_1327\nadd rdx, 1\ncmp rax, rdx\njnz short loc_130F\njmp short loc_134E\nloc_1320:\ntest rax, rax\njz short loc_134E\njmp short loc_1305\nloc_1327:\nlea rsi, [rax-1]\ncmp rdx, rsi\njnb short loc_1349\nlea rdx, [rsp+rdx+48h+base]\nlea rcx, [rsp+rax+48h+var_3C]\nloc_133A:\nmovzx eax, byte ptr [rdx+1]\nmov [rdx], al\nadd rdx, 1\ncmp rdx, rcx\njnz short loc_133A\nloc_1349:\nmov [rsp+rsi+48h+base], 0\nloc_134E:\nlea r13, [rsp+48h+base]\nmov rdi, r13; s\ncall _strlen\nmov rsi, rax; nmemb\nmov rcx, cs:compar; compar\nmov edx, 1; size\nmov rdi, r13; base\ncall _qsort\nmovsxd r12, r12d\nmov [rsp+r12+48h+s], bpl\nlea rax, [rbx+1]\nmov edx, 0Bh\ncmp rax, rdx\ncmovnb rdx, rax\nsub rdx, rax\nlea rbx, [rsp+48h+s]\nlea rdi, [rbx+rax]\nmov rsi, r13\ncall ___strcpy_chk\nmov edx, 0Ah; base\nmov esi, 0; endptr\nmov rdi, rbx; nptr\ncall _strtol\nloc_13B0:\nmov rdx, [rsp+48h+var_30]\nsub rdx, fs:28h\njnz short loc_13D2\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_13CB:\nmov eax, 0\njmp short loc_13B0\nloc_13D2:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1229(unsigned int a1)\n{\n int v1; // edx\n __int64 v2; // rax\n char *v3; // rdx\n int v5; // r12d\n __int64 v6; // rbx\n size_t v7; // rax\n int v8; // ebp\n char *v9; // rdx\n int v10; // esi\n unsigned __int64 v11; // rdx\n char *v12; // rdx\n size_t v13; // rax\n __int64 v14; // rdx\n char s[11]; // [rsp+2h] [rbp-46h] BYREF\n char base; // [rsp+Dh] [rbp-3Bh] BYREF\n unsigned __int8 v17; // [rsp+Eh] [rbp-3Ah] BYREF\n unsigned __int64 v18; // [rsp+18h] [rbp-30h]\n\n v18 = __readfsqword(0x28u);\n __sprintf_chk(s, 2LL, 11LL, &unk_2004, a1);\n v1 = strlen(s);\n LODWORD(v2) = v1 - 2;\n if ( v1 - 2 < 0 )\n return 0LL;\n v2 = (int)v2;\n v3 = &s[v1 - 1 - (__int64)(int)v2];\n while ( s[v2] >= v3[v2] )\n {\n if ( (int)--v2 < 0 )\n return 0LL;\n }\n v5 = v2;\n v6 = (int)v2;\n __strcpy_chk(&base, &s[(int)v2], 11LL);\n v7 = strlen(&base);\n v8 = v17;\n if ( v7 > 1 )\n {\n v9 = (char *)&v17;\n do\n {\n v10 = (unsigned __int8)*v9;\n if ( (char)v8 <= *v9 )\n v10 = v8;\n if ( *v9 > base )\n v8 = v10;\n ++v9;\n }\n while ( v9 != &base + v7 );\nLABEL_13:\n v11 = 0LL;\n while ( *(&base + v11) != (_BYTE)v8 )\n {\n if ( v7 == ++v11 )\n goto LABEL_23;\n }\n if ( v11 < v7 - 1 )\n {\n v12 = &base + v11;\n do\n {\n *v12 = v12[1];\n ++v12;\n }\n while ( v12 != &s[v7 + 10] );\n }\n *(&base + v7 - 1) = 0;\n goto LABEL_23;\n }\n if ( v7 )\n goto LABEL_13;\nLABEL_23:\n v13 = strlen(&base);\n qsort(&base, v13, 1uLL, (__compar_fn_t)&strcmp);\n s[v5] = v8;\n v14 = 11LL;\n if ( (unsigned __int64)(v6 + 1) >= 0xB )\n v14 = v6 + 1;\n __strcpy_chk(&s[v6 + 1], &base, v14 - (v6 + 1));\n return strtol(s, 0LL, 10);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1229(unsigned int a1) {\n int v1;\n long long v2;\n char *v3;\n int v5;\n long long v6;\n unsigned int v7;\n int v8;\n char *v9;\n int v10;\n unsigned long long v11;\n char *v12;\n unsigned int v13;\n long long v14;\n char s[11];\n char base;\n unsigned char v17;\n unsigned long long v18;\n v18 = __readfsqword(40u);\n __sprintf_chk(s, 2LL, 11LL, &unk_2004, a1);\n v1 = strlen(s);\n LODWORD(v2) = v1 - 2;\n if (v1 - 2 < 0) return 0LL;\n v2 = (int)v2;\n v3 = &s[v1 - 1 - (long long)(int)v2];\n while (s[v2] >= v3[v2]) {\n if ((int)--v2 < 0) return 0LL;\n }\n v5 = v2;\n v6 = (int)v2;\n __strcpy_chk(&base, &s[(int)v2], 11LL);\n v7 = strlen(&base);\n v8 = v17;\n if (v7 > 1) {\n v9 = (char *)&v17;\n do {\n v10 = (unsigned char)*v9;\n if ((char)v8 <= *v9) v10 = v8;\n if (*v9 > base) v8 = v10;\n ++v9;\n } while (v9 != &base + v7);\n LABEL_13:\n v11 = 0LL;\n while (*(&base + v11) != (uint8_t)v8) {\n if (v7 == ++v11) goto LABEL_23;\n }\n if (v11 < v7 - 1) {\n v12 = &base + v11;\n do {\n *v12 = v12[1];\n ++v12;\n } while (v12 != &s[v7 + 10]);\n }\n *(&base + v7 - 1) = 0;\n goto LABEL_23;\n }\n if (v7) goto LABEL_13;\nLABEL_23:\n v13 = strlen(&base);\n qsort(&base, v13, 1uLL, (int (*)(const void *, const void *)) & strcmp);\n s[v5] = v8;\n v14 = 11LL;\n if ((unsigned long long)(v6 + 1) >= 11) v14 = v6 + 1;\n __strcpy_chk(&s[v6 + 1], &base, v14 - (v6 + 1));\n return strtol(s, 0LL, 10);\n}", + "ida_pseudo_norm": "long long func0(unsigned int a1) {\n int v1;\n long long v2;\n char *v3;\n int v5;\n long long v6;\n unsigned int v7;\n int v8;\n char *v9;\n int v10;\n unsigned long long v11;\n char *v12;\n unsigned int v13;\n long long v14;\n char s[11];\n char base;\n unsigned char v17;\n unsigned long long v18;\n v18 = __readfsqword(40u);\n __sprintf_chk(s, 2LL, 11LL, &unk_2004, a1);\n v1 = strlen(s);\n LODWORD(v2) = v1 - 2;\n if (v1 - 2 < 0) return 0LL;\n v2 = (int)v2;\n v3 = &s[v1 - 1 - (long long)(int)v2];\n while (s[v2] >= v3[v2]) {\n if ((int)--v2 < 0) return 0LL;\n }\n v5 = v2;\n v6 = (int)v2;\n __strcpy_chk(&base, &s[(int)v2], 11LL);\n v7 = strlen(&base);\n v8 = v17;\n if (v7 > 1) {\n v9 = (char *)&v17;\n do {\n v10 = (unsigned char)*v9;\n if ((char)v8 <= *v9) v10 = v8;\n if (*v9 > base) v8 = v10;\n ++v9;\n } while (v9 != &base + v7);\n LABEL_13:\n v11 = 0LL;\n while (*(&base + v11) != (uint8_t)v8) {\n if (v7 == ++v11) goto LABEL_23;\n }\n if (v11 < v7 - 1) {\n v12 = &base + v11;\n do {\n *v12 = v12[1];\n ++v12;\n } while (v12 != &s[v7 + 10]);\n }\n *(&base + v7 - 1) = 0;\n goto LABEL_23;\n }\n if (v7) goto LABEL_13;\nLABEL_23:\n v13 = strlen(&base);\n qsort(&base, v13, 1uLL, (int (*)(const void *, const void *)) & strcmp);\n s[v5] = v8;\n v14 = 11LL;\n if ((unsigned long long)(v6 + 1) >= 11) v14 = v6 + 1;\n __strcpy_chk(&s[v6 + 1], &base, v14 - (v6 + 1));\n return strtol(s, 0LL, 10);\n}" + }, + { + "index": 407, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n char nums[11];\n sprintf(nums, \"%d\", n);\n size_t length = strlen(nums);\n for (int i = length - 2; i >= 0; --i) {\n if (nums[i] < nums[i + 1]) {\n char z[11];\n strcpy(z, nums + i);\n size_t z_len = strlen(z);\n char y = z[1];\n for (size_t j = 1; j < z_len; ++j) {\n if (z[j] > z[0] && z[j] < y) {\n y = z[j];\n }\n }\n for (size_t j = 0; j < z_len; ++j) {\n if (z[j] == y) {\n for (size_t k = j; k < z_len - 1; ++k) {\n z[k] = z[k + 1];\n }\n z[z_len - 1] = '\\0';\n break;\n }\n }\n qsort(z, strlen(z), sizeof(char),\n (int (*)(const void *, const void *))strcmp);\n nums[i] = y;\n strcpy(nums + i + 1, z);\n return atoi(nums);\n }\n }\n return 0;\n}", + "test": "int main() {\n\n assert(func0(12) == 21);\n\n assert(func0(10) == 0);\n\n assert(func0(102) == 120);\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov %edi,%r8d\nmov $0xb,%edx\nmov $0x1,%esi\npush %r12\nlea 0xce8(%rip),%rcx\npush %rbp\npush %rbx\nsub $0x28,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x18(%rsp)\nxor %eax,%eax\nlea 0x2(%rsp),%rbp\nmov %rbp,%rdi\ncallq 1150 <__sprintf_chk@plt>\nmov %rbp,%rdi\ncallq 1100 \nmov %eax,%edx\nsub $0x2,%eax\njs 1470 \nsub $0x1,%edx\ncltq\nmovslq %edx,%rdx\nsub %rax,%rdx\nadd %rbp,%rdx\njmp 1374 \nnopw 0x0(%rax,%rax,1)\nsub $0x1,%rax\ntest %eax,%eax\njs 1470 \nmovzbl (%rdx,%rax,1),%edi\nmovslq %eax,%rbx\ncmp %dil,0x0(%rbp,%rax,1)\njge 1368 \nlea 0xd(%rsp),%r13\nlea 0x0(%rbp,%rbx,1),%rsi\nmov $0xb,%edx\nmov %r13,%rdi\ncallq 1140 <__stpcpy_chk@plt>\nmovzbl 0xe(%rsp),%r12d\nsub %r13,%rax\nmov %rax,%r8\ncmp $0x1,%rax\njbe 148d \nmovzbl 0xd(%rsp),%ecx\nlea 0xf(%rsp),%rdx\nlea 0x0(%r13,%rax,1),%rax\nmov %r12d,%esi\njmp 13cf \nnopl 0x0(%rax,%rax,1)\nmovzbl (%rdx),%esi\nadd $0x1,%rdx\ncmp %sil,%cl\njge 13db \ncmp %sil,%r12b\ncmovg %esi,%r12d\ncmp %rax,%rdx\njne 13c8 \nxor %edx,%edx\njmp 13f7 \nnopl 0x0(%rax)\nadd $0x1,%rdx\ncmp %rdx,%r8\njbe 1430 \nmovzbl 0x0(%r13,%rdx,1),%ecx\ncmp %cl,%r12b\njne 13e8 \nlea -0x1(%r8),%rdi\nlea 0x0(%r13,%rdx,1),%rcx\nlea 0xc(%rsp,%r8,1),%rsi\ncmp %rdx,%rdi\njbe 1420 \nmovzbl 0x1(%rcx),%eax\nadd $0x1,%rcx\nmov %al,-0x1(%rcx)\ncmp %rcx,%rsi\njne 1410 \nmovb $0x0,0xd(%rsp,%rdi,1)\nmov %r13,%rdi\ncallq 1100 \nmov %rax,%r8\nmov 0x2ba9(%rip),%rcx\nmov %r8,%rsi\nmov $0x1,%edx\nmov %r13,%rdi\ncallq 10f0 \nlea 0x1(%rbp,%rbx,1),%rdi\nmov %r13,%rsi\nmov %r12b,0x2(%rsp,%rbx,1)\ncallq 10d0 \nmov $0xa,%edx\nxor %esi,%esi\nmov %rbp,%rdi\ncallq 1130 \njmp 1472 \nnopw 0x0(%rax,%rax,1)\nxor %eax,%eax\nmov 0x18(%rsp),%rbx\nxor %fs:0x28,%rbx\njne 149c \nadd $0x28,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\ntest %rax,%rax\nje 1430 \nmovzbl 0xd(%rsp),%ecx\njmpq 13e0 \ncallq 1110 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov r8d, edi\nmov edx, 0Bh\nmov esi, 2\npush r14\nlea rcx, unk_2004\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov rax, fs:28h\nmov [rsp+58h+var_40], rax\nxor eax, eax\nlea r12, [rsp+58h+s]\nmov rdi, r12\ncall ___sprintf_chk\nmov rdi, r12; s\ncall _strlen\nsub eax, 2\njs loc_1480\nmov eax, eax\nmovzx edx, [rsp+rax+58h+var_55]\njmp short loc_138C\nloc_1380:\nsub rax, 1\ntest eax, eax\njs loc_1480\nloc_138C:\nmov ecx, edx\nmovzx edx, byte ptr [r12+rax]\ncmp dl, cl\njge short loc_1380\nmovsxd rbx, eax\nlea r14, [rsp+58h+base]\nmov edx, 0Bh\nmovsxd r13, eax\nlea rsi, [r12+rbx]\nmov rdi, r14\ncall ___stpcpy_chk\nmovzx ebp, [rsp+58h+var_4A]\nsub rax, r14\nmov rsi, rax\ncmp rax, 1\njbe loc_14A1\nmovzx r8d, [rsp+58h+base]\nlea rdx, [rsp+58h+var_4A]\nlea rdi, [r14+rax]\nnop word ptr [rax+rax+00000000h]\nloc_13E0:\nmovzx ecx, byte ptr [rdx]\ncmp bpl, cl\nmov eax, ecx\ncmovle eax, ebp\ncmp r8b, cl\ncmovl ebp, eax\nadd rdx, 1\ncmp rdx, rdi\njnz short loc_13E0\nloc_13FA:\nxor edi, edi\njmp short loc_1409\nloc_1400:\nadd rdi, 1\ncmp rsi, rdi\njz short loc_143C\nloc_1409:\ncmp [r14+rdi], bpl\njnz short loc_1400\nlea r15, [rsi-1]\ncmp rdi, r15\njnb short loc_142B\nmov rdx, r15\nlea rsi, [r14+rdi+1]; src\nsub rdx, rdi; n\nadd rdi, r14; dest\ncall _memmove\nloc_142B:\nmov rdi, r14; s\nmov [rsp+r15+58h+base], 0\ncall _strlen\nmov rsi, rax; nmemb\nloc_143C:\nmov rcx, cs:compar; compar\nmov rdi, r14; base\nmov edx, 1; size\ncall _qsort\nlea rax, [rbx+1]\nmov edx, 0Bh\nmov rsi, r14\nsub rdx, rax\nlea rdi, [r12+rax]\nmov [rsp+r13+58h+s], bpl\ncall ___strcpy_chk\nmov edx, 0Ah; base\nxor esi, esi; endptr\nmov rdi, r12; nptr\ncall _strtol\njmp short loc_1482\nloc_1480:\nxor eax, eax\nloc_1482:\nmov rdx, [rsp+58h+var_40]\nsub rdx, fs:28h\njnz short loc_14AB\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14A1:\ntest rax, rax\njz short loc_143C\njmp loc_13FA\nloc_14AB:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1)\n{\n __int64 v1; // rax\n char v2; // dl\n char v3; // cl\n __int64 v4; // rbx\n __int64 v5; // r13\n __int64 v6; // rax\n int v7; // ebp\n unsigned __int64 v8; // rax\n size_t v9; // rsi\n char *v10; // rdx\n char *v11; // rdi\n int v12; // eax\n unsigned __int64 v13; // rdi\n size_t v14; // r15\n char s[11]; // [rsp+2h] [rbp-56h] BYREF\n char base; // [rsp+Dh] [rbp-4Bh] BYREF\n unsigned __int8 v18; // [rsp+Eh] [rbp-4Ah] BYREF\n unsigned __int64 v19; // [rsp+18h] [rbp-40h]\n\n v19 = __readfsqword(0x28u);\n __sprintf_chk(s, 2LL, 11LL, &unk_2004, a1);\n LODWORD(v1) = strlen(s) - 2;\n if ( (int)v1 >= 0 )\n {\n v1 = (unsigned int)v1;\n v2 = s[(unsigned int)v1 + 1];\n while ( 1 )\n {\n v3 = v2;\n v2 = s[v1];\n if ( v2 < v3 )\n break;\n if ( (int)--v1 < 0 )\n return 0LL;\n }\n v4 = (int)v1;\n v5 = (int)v1;\n v6 = __stpcpy_chk(&base, &s[(int)v1], 11LL);\n v7 = v18;\n v8 = v6 - (_QWORD)&base;\n v9 = v8;\n if ( v8 <= 1 )\n {\n if ( !v8 )\n {\nLABEL_18:\n qsort(&base, v9, 1uLL, (__compar_fn_t)&strcmp);\n s[v5] = v7;\n __strcpy_chk(&s[v4 + 1], &base, 11 - (v4 + 1));\n return strtol(s, 0LL, 10);\n }\n }\n else\n {\n v10 = (char *)&v18;\n v11 = &base + v8;\n do\n {\n v12 = (unsigned __int8)*v10;\n if ( (char)v7 <= *v10 )\n v12 = v7;\n if ( base < *v10 )\n v7 = v12;\n ++v10;\n }\n while ( v10 != v11 );\n }\n v13 = 0LL;\n while ( *(&base + v13) != (_BYTE)v7 )\n {\n if ( v9 == ++v13 )\n goto LABEL_18;\n }\n v14 = v9 - 1;\n if ( v13 < v9 - 1 )\n memmove(&base + v13, &base + v13 + 1, v14 - v13);\n *(&base + v14) = 0;\n v9 = strlen(&base);\n goto LABEL_18;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1320:\nendbr64\npush r15\nmov r8d, edi\nmov edx, 0Bh\nmov esi, 2\npush r14\nlea rcx, unk_2004\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov rax, fs:28h\nmov [rsp+58h+var_40], rax\nxor eax, eax\nlea r12, [rsp+58h+s]\nmov rdi, r12\ncall ___sprintf_chk\nmov rdi, r12; s\ncall _strlen\nsub eax, 2\njs loc_1480\nmov eax, eax\nmovzx edx, [rsp+rax+58h+var_55]\njmp short loc_138C\nloc_1380:\nsub rax, 1\ntest eax, eax\njs loc_1480\nloc_138C:\nmov ecx, edx\nmovzx edx, byte ptr [r12+rax]\ncmp dl, cl\njge short loc_1380\nmovsxd rbx, eax\nlea r14, [rsp+58h+base]\nmov edx, 0Bh\nmovsxd r13, eax\nlea rsi, [r12+rbx]\nmov rdi, r14\ncall ___stpcpy_chk\nmovzx ebp, [rsp+58h+var_4A]\nsub rax, r14\nmov rsi, rax\ncmp rax, 1\njbe loc_14A1\nmovzx r8d, [rsp+58h+base]\nlea rdx, [rsp+58h+var_4A]\nlea rdi, [r14+rax]\nnop word ptr [rax+rax+00000000h]\nloc_13E0:\nmovzx ecx, byte ptr [rdx]\ncmp bpl, cl\nmov eax, ecx\ncmovle eax, ebp\ncmp r8b, cl\ncmovl ebp, eax\nadd rdx, 1\ncmp rdx, rdi\njnz short loc_13E0\nloc_13FA:\nxor edi, edi\njmp short loc_1409\nloc_1400:\nadd rdi, 1\ncmp rsi, rdi\njz short loc_143C\nloc_1409:\ncmp [r14+rdi], bpl\njnz short loc_1400\nlea r15, [rsi-1]\ncmp rdi, r15\njnb short loc_142B\nmov rdx, r15\nlea rsi, [r14+rdi+1]; src\nsub rdx, rdi; n\nadd rdi, r14; dest\ncall _memmove\nloc_142B:\nmov rdi, r14; s\nmov [rsp+r15+58h+base], 0\ncall _strlen\nmov rsi, rax; nmemb\nloc_143C:\nmov rcx, cs:compar; compar\nmov rdi, r14; base\nmov edx, 1; size\ncall _qsort\nlea rax, [rbx+1]\nmov edx, 0Bh\nmov rsi, r14\nsub rdx, rax\nlea rdi, [r12+rax]\nmov [rsp+r13+58h+s], bpl\ncall ___strcpy_chk\nmov edx, 0Ah; base\nxor esi, esi; endptr\nmov rdi, r12; nptr\ncall _strtol\njmp short loc_1482\nloc_1480:\nxor eax, eax\nloc_1482:\nmov rdx, [rsp+58h+var_40]\nsub rdx, fs:28h\njnz short loc_14AB\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14A1:\ntest rax, rax\njz short loc_143C\njmp loc_13FA\nloc_14AB:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1320(unsigned int a1)\n{\n __int64 v1; // rax\n char v2; // dl\n char v3; // cl\n __int64 v4; // rbx\n __int64 v5; // r13\n __int64 v6; // rax\n int v7; // ebp\n unsigned __int64 v8; // rax\n size_t v9; // rsi\n char *v10; // rdx\n char *v11; // rdi\n int v12; // eax\n unsigned __int64 v13; // rdi\n size_t v14; // r15\n char s[11]; // [rsp+2h] [rbp-56h] BYREF\n char base; // [rsp+Dh] [rbp-4Bh] BYREF\n unsigned __int8 v18; // [rsp+Eh] [rbp-4Ah] BYREF\n unsigned __int64 v19; // [rsp+18h] [rbp-40h]\n\n v19 = __readfsqword(0x28u);\n __sprintf_chk(s, 2LL, 11LL, &unk_2004, a1);\n LODWORD(v1) = strlen(s) - 2;\n if ( (int)v1 >= 0 )\n {\n v1 = (unsigned int)v1;\n v2 = s[(unsigned int)v1 + 1];\n while ( 1 )\n {\n v3 = v2;\n v2 = s[v1];\n if ( v2 < v3 )\n break;\n if ( (int)--v1 < 0 )\n return 0LL;\n }\n v4 = (int)v1;\n v5 = (int)v1;\n v6 = __stpcpy_chk(&base, &s[(int)v1], 11LL);\n v7 = v18;\n v8 = v6 - (_QWORD)&base;\n v9 = v8;\n if ( v8 <= 1 )\n {\n if ( !v8 )\n {\nLABEL_18:\n qsort(&base, v9, 1uLL, (__compar_fn_t)&strcmp);\n s[v5] = v7;\n __strcpy_chk(&s[v4 + 1], &base, 11 - (v4 + 1));\n return strtol(s, 0LL, 10);\n }\n }\n else\n {\n v10 = (char *)&v18;\n v11 = &base + v8;\n do\n {\n v12 = (unsigned __int8)*v10;\n if ( (char)v7 <= *v10 )\n v12 = v7;\n if ( base < *v10 )\n v7 = v12;\n ++v10;\n }\n while ( v10 != v11 );\n }\n v13 = 0LL;\n while ( *(&base + v13) != (_BYTE)v7 )\n {\n if ( v9 == ++v13 )\n goto LABEL_18;\n }\n v14 = v9 - 1;\n if ( v13 < v9 - 1 )\n memmove(&base + v13, &base + v13 + 1, v14 - v13);\n *(&base + v14) = 0;\n v9 = strlen(&base);\n goto LABEL_18;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1320(unsigned int a1) {\n long long v1;\n char v2;\n char v3;\n long long v4;\n long long v5;\n long long v6;\n int v7;\n unsigned long long v8;\n unsigned int v9;\n char *v10;\n char *v11;\n int v12;\n unsigned long long v13;\n unsigned int v14;\n char s[11];\n char base;\n unsigned char v18;\n unsigned long long v19;\n v19 = __readfsqword(40u);\n __sprintf_chk(s, 2LL, 11LL, &unk_2004, a1);\n LODWORD(v1) = strlen(s) - 2;\n if ((int)v1 >= 0) {\n v1 = (unsigned int)v1;\n v2 = s[(unsigned int)v1 + 1];\n while (1) {\n v3 = v2;\n v2 = s[v1];\n if (v2 < v3) break;\n if ((int)--v1 < 0) return 0LL;\n }\n v4 = (int)v1;\n v5 = (int)v1;\n v6 = __stpcpy_chk(&base, &s[(int)v1], 11LL);\n v7 = v18;\n v8 = v6 - (uint64_t)&base;\n v9 = v8;\n if (v8 <= 1) {\n if (!v8) {\n LABEL_18:\n qsort(&base, v9, 1uLL, (int (*)(const void *, const void *)) & strcmp);\n s[v5] = v7;\n __strcpy_chk(&s[v4 + 1], &base, 11 - (v4 + 1));\n return strtol(s, 0LL, 10);\n }\n } else {\n v10 = (char *)&v18;\n v11 = &base + v8;\n do {\n v12 = (unsigned char)*v10;\n if ((char)v7 <= *v10) v12 = v7;\n if (base < *v10) v7 = v12;\n ++v10;\n } while (v10 != v11);\n }\n v13 = 0LL;\n while (*(&base + v13) != (uint8_t)v7) {\n if (v9 == ++v13) goto LABEL_18;\n }\n v14 = v9 - 1;\n if (v13 < v9 - 1) memmove(&base + v13, &base + v13 + 1, v14 - v13);\n *(&base + v14) = 0;\n v9 = strlen(&base);\n goto LABEL_18;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(unsigned int a1) {\n long long v1;\n char v2;\n char v3;\n long long v4;\n long long v5;\n long long v6;\n int v7;\n unsigned long long v8;\n unsigned int v9;\n char *v10;\n char *v11;\n int v12;\n unsigned long long v13;\n unsigned int v14;\n char s[11];\n char base;\n unsigned char v18;\n unsigned long long v19;\n v19 = __readfsqword(40u);\n __sprintf_chk(s, 2LL, 11LL, &unk_2004, a1);\n LODWORD(v1) = strlen(s) - 2;\n if ((int)v1 >= 0) {\n v1 = (unsigned int)v1;\n v2 = s[(unsigned int)v1 + 1];\n while (1) {\n v3 = v2;\n v2 = s[v1];\n if (v2 < v3) break;\n if ((int)--v1 < 0) return 0LL;\n }\n v4 = (int)v1;\n v5 = (int)v1;\n v6 = __stpcpy_chk(&base, &s[(int)v1], 11LL);\n v7 = v18;\n v8 = v6 - (uint64_t)&base;\n v9 = v8;\n if (v8 <= 1) {\n if (!v8) {\n LABEL_18:\n qsort(&base, v9, 1uLL, (int (*)(const void *, const void *)) & strcmp);\n s[v5] = v7;\n __strcpy_chk(&s[v4 + 1], &base, 11 - (v4 + 1));\n return strtol(s, 0LL, 10);\n }\n } else {\n v10 = (char *)&v18;\n v11 = &base + v8;\n do {\n v12 = (unsigned char)*v10;\n if ((char)v7 <= *v10) v12 = v7;\n if (base < *v10) v7 = v12;\n ++v10;\n } while (v10 != v11);\n }\n v13 = 0LL;\n while (*(&base + v13) != (uint8_t)v7) {\n if (v9 == ++v13) goto LABEL_18;\n }\n v14 = v9 - 1;\n if (v13 < v9 - 1) memmove(&base + v13, &base + v13 + 1, v14 - v13);\n *(&base + v14) = 0;\n v9 = strlen(&base);\n goto LABEL_18;\n }\n return 0LL;\n}" + }, + { + "index": 407, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n char nums[11];\n sprintf(nums, \"%d\", n);\n size_t length = strlen(nums);\n for (int i = length - 2; i >= 0; --i) {\n if (nums[i] < nums[i + 1]) {\n char z[11];\n strcpy(z, nums + i);\n size_t z_len = strlen(z);\n char y = z[1];\n for (size_t j = 1; j < z_len; ++j) {\n if (z[j] > z[0] && z[j] < y) {\n y = z[j];\n }\n }\n for (size_t j = 0; j < z_len; ++j) {\n if (z[j] == y) {\n for (size_t k = j; k < z_len - 1; ++k) {\n z[k] = z[k + 1];\n }\n z[z_len - 1] = '\\0';\n break;\n }\n }\n qsort(z, strlen(z), sizeof(char),\n (int (*)(const void *, const void *))strcmp);\n nums[i] = y;\n strcpy(nums + i + 1, z);\n return atoi(nums);\n }\n }\n return 0;\n}", + "test": "int main() {\n\n assert(func0(12) == 21);\n\n assert(func0(10) == 0);\n\n assert(func0(102) == 120);\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\nmov %edi,%r8d\nmov $0xb,%edx\nmov $0x1,%esi\npush %r13\nlea 0xcc8(%rip),%rcx\npush %r12\npush %rbp\npush %rbx\nsub $0x20,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x18(%rsp)\nxor %eax,%eax\nlea 0x2(%rsp),%rbp\nmov %rbp,%rdi\ncallq 1170 <__sprintf_chk@plt>\nmov %rbp,%rdi\ncallq 1110 \nmov %eax,%ebx\nsub $0x2,%ebx\njs 1460 \nmovslq %ebx,%rbx\nmovzbl 0x2(%rsp,%rbx,1),%edx\ncmp %dl,0x3(%rsp,%rbx,1)\njg 1470 \nlea -0x3(%rax),%ebx\ncmp $0x2,%eax\nje 1460 \nmovslq %ebx,%rbx\nmovzbl 0x2(%rsp,%rbx,1),%ecx\ncmp %cl,%dl\njg 1470 \nlea -0x4(%rax),%ebx\ncmp $0x3,%eax\nje 1460 \nmovslq %ebx,%rbx\nmovzbl 0x2(%rsp,%rbx,1),%edx\ncmp %dl,%cl\njg 1470 \nlea -0x5(%rax),%ebx\ncmp $0x4,%eax\nje 1460 \nmovslq %ebx,%rbx\nmovzbl 0x2(%rsp,%rbx,1),%ecx\ncmp %cl,%dl\njg 1470 \nlea -0x6(%rax),%ebx\ncmp $0x5,%eax\nje 1460 \nmovslq %ebx,%rbx\nmovzbl 0x2(%rsp,%rbx,1),%edx\ncmp %dl,%cl\njg 1470 \nlea -0x7(%rax),%ebx\ncmp $0x6,%eax\nje 1460 \nmovslq %ebx,%rbx\nmovzbl 0x2(%rsp,%rbx,1),%ecx\ncmp %cl,%dl\njg 1470 \nlea -0x8(%rax),%ebx\ncmp $0x7,%eax\nje 1460 \nmovslq %ebx,%rbx\nmovzbl 0x2(%rsp,%rbx,1),%edx\ncmp %dl,%cl\njg 1470 \nlea -0x9(%rax),%ebx\ncmp $0x8,%eax\nje 1460 \nmovslq %ebx,%rbx\nmovzbl 0x2(%rsp,%rbx,1),%ecx\ncmp %cl,%dl\njg 1470 \ncmp $0xa,%eax\nmov $0x0,%eax\njne 143e \ncmp %cl,0x2(%rsp)\njl 1464 \nmov 0x18(%rsp),%rdi\nxor %fs:0x28,%rdi\njne 1734 \nadd $0x20,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nxor %eax,%eax\njmp 143e \nxor %ebx,%ebx\nnopw %cs:0x0(%rax,%rax,1)\nlea 0xd(%rsp),%r13\nlea 0x0(%rbp,%rbx,1),%rsi\nmov $0xb,%edx\nmov %r13,%rdi\ncallq 1150 <__stpcpy_chk@plt>\nmovzbl 0xe(%rsp),%edx\nsub %r13,%rax\nmov %rax,%rsi\ncmp $0x1,%rax\njbe 167c \nmovzbl 0xd(%rsp),%eax\ncmp $0x2,%rsi\nje 16e2 \nmovzbl 0xf(%rsp),%ecx\nmov %edx,%r12d\ncmp %cl,%al\njl 1630 \ncmp $0x3,%rsi\nje 1550 \nmovzbl 0x10(%rsp),%ecx\ncmp %cl,%al\njl 1640 \ncmp $0x4,%rsi\nje 1550 \nmovzbl 0x11(%rsp),%ecx\ncmp %cl,%al\njl 1650 \ncmp $0x5,%rsi\nje 1550 \nmovzbl 0x12(%rsp),%ecx\ncmp %cl,%al\njl 1660 \ncmp $0x6,%rsi\nje 1550 \nmovzbl 0x13(%rsp),%ecx\ncmp %cl,%al\njl 1670 \ncmp $0x7,%rsi\nje 1550 \nmovzbl 0x14(%rsp),%ecx\ncmp %cl,%al\njge 1521 \ncmp %cl,%r12b\ncmovg %ecx,%r12d\ncmp $0x8,%rsi\nje 1550 \nmovzbl 0x15(%rsp),%ecx\ncmp %cl,%al\njge 1537 \ncmp %cl,%r12b\ncmovg %ecx,%r12d\ncmp $0xa,%rsi\njne 1550 \nmovzbl 0x16(%rsp),%ecx\ncmp %cl,%al\njge 1550 \ncmp %cl,%r12b\ncmovg %ecx,%r12d\nnopl (%rax)\ncmp 0xd(%rsp),%r12b\nje 16ea \ncmp %r12b,%dl\nje 16f2 \ncmp $0x2,%rsi\nje 15f4 \ncmp %r12b,0xf(%rsp)\nje 16f9 \ncmp $0x3,%rsi\nje 15f4 \ncmp %r12b,0x10(%rsp)\nje 1700 \ncmp $0x4,%rsi\nje 15f4 \ncmp %r12b,0x11(%rsp)\nje 1707 \ncmp $0x5,%rsi\nje 15f4 \ncmp %r12b,0x12(%rsp)\nje 170e \ncmp $0x6,%rsi\nje 15f4 \ncmp %r12b,0x13(%rsp)\nje 1715 \ncmp $0x7,%rsi\nje 15f4 \ncmp %r12b,0x14(%rsp)\nje 169c \ncmp $0x8,%rsi\nje 15f4 \ncmp %r12b,0x15(%rsp)\nje 171c \ncmp $0xa,%rsi\njne 1723 \ncmp %r12b,0x16(%rsp)\nje 16da \nmov 0x29e5(%rip),%rcx\nmov $0x1,%edx\nmov %r13,%rdi\ncallq 1100 \nlea 0x1(%rbp,%rbx,1),%rdi\nmov %r13,%rsi\nmov %r12b,0x2(%rsp,%rbx,1)\ncallq 10e0 \nmov $0xa,%edx\nxor %esi,%esi\nmov %rbp,%rdi\ncallq 1140 \njmpq 143e \nxchg %ax,%ax\ncmp %cl,%dl\ncmovle %edx,%ecx\nmov %ecx,%r12d\njmpq 14bb \nnopl (%rax)\ncmp %cl,%r12b\ncmovg %ecx,%r12d\njmpq 14d2 \nnopl 0x0(%rax)\ncmp %cl,%r12b\ncmovg %ecx,%r12d\njmpq 14e5 \nnopl 0x0(%rax)\ncmp %cl,%r12b\ncmovg %ecx,%r12d\njmpq 14f8 \nnopl 0x0(%rax)\ncmp %cl,%r12b\ncmovg %ecx,%r12d\njmpq 150b \nmov %edx,%r12d\ntest %rax,%rax\nje 15f4 \ncmp 0xd(%rsp),%dl\nje 172d \nmov $0x1,%esi\njmpq 15f4 \nmov $0x7,%edi\nnopl 0x0(%rax)\nlea -0x1(%rsi),%r14\ncmp %rdi,%r14\njbe 16c4 \nmov %r14,%rdx\nlea 0x1(%r13,%rdi,1),%rsi\nsub %rdi,%rdx\nadd %r13,%rdi\ncallq 1160 \nmov %r13,%rdi\nmovb $0x0,0xd(%rsp,%r14,1)\ncallq 1110 \nmov %rax,%rsi\njmpq 15f4 \nmov $0x9,%r14d\njmp 16c4 \nmov %edx,%r12d\njmpq 1550 \nlea -0x1(%rsi),%r14\nxor %edi,%edi\njmp 16b1 \nmov $0x1,%edi\njmp 16a8 \nmov $0x2,%edi\njmp 16a8 \nmov $0x3,%edi\njmp 16a8 \nmov $0x4,%edi\njmp 16a8 \nmov $0x5,%edi\njmp 16a8 \nmov $0x6,%edi\njmp 16a8 \nmov $0x8,%edi\njmp 16a8 \nmov $0x9,%esi\njmpq 15f4 \nxor %edi,%edi\njmpq 16a8 \ncallq 1120 <__stack_chk_fail@plt>\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r14\nmov r8d, edi\nmov edx, 0Bh\nmov esi, 2\npush r13\nlea rcx, unk_2004\npush r12\npush rbp\npush rbx\nsub rsp, 20h\nmov rax, fs:28h\nmov [rsp+48h+var_30], rax\nxor eax, eax\nlea rbp, [rsp+48h+s]\nmov rdi, rbp\ncall ___sprintf_chk\nmov rdi, rbp; s\ncall _strlen\nmov edx, eax\nsub edx, 2\njs loc_1468\nmovsxd rbx, edx\nmov edx, edx\nmovzx ecx, [rsp+rbx+48h+s]\ncmp [rsp+rdx+48h+var_45], cl\njg loc_1470\nlea ebx, [rax-3]\ncmp eax, 2\njz loc_1468\nmovsxd rbx, ebx\nmovzx edx, [rsp+rbx+48h+s]\ncmp cl, dl\njg loc_1470\nlea ebx, [rax-4]\ncmp eax, 3\njz loc_1468\nmovsxd rbx, ebx\nmovzx ecx, [rsp+rbx+48h+s]\ncmp dl, cl\njg loc_1470\nlea ebx, [rax-5]\ncmp eax, 4\njz loc_1468\nmovsxd rbx, ebx\nmovzx edx, [rsp+rbx+48h+s]\ncmp cl, dl\njg loc_1470\nlea ebx, [rax-6]\ncmp eax, 5\njz loc_1468\nmovsxd rbx, ebx\nmovzx ecx, [rsp+rbx+48h+s]\ncmp dl, cl\njg loc_1470\nlea ebx, [rax-7]\ncmp eax, 6\njz short loc_1468\nmovsxd rbx, ebx\nmovzx edx, [rsp+rbx+48h+s]\ncmp cl, dl\njg short loc_1470\nlea ebx, [rax-8]\ncmp eax, 7\njz short loc_1468\nmovsxd rbx, ebx\nmovzx ecx, [rsp+rbx+48h+s]\ncmp dl, cl\njg short loc_1470\nlea ebx, [rax-9]\ncmp eax, 8\njz short loc_1468\nmovsxd rbx, ebx\nmovzx edx, [rsp+rbx+48h+s]\ncmp cl, dl\njg short loc_1470\ncmp eax, 0Ah\nmov eax, 0\njnz short loc_1444\ncmp [rsp+48h+s], dl\njl short loc_146C\nloc_1444:\nmov rdx, [rsp+48h+var_30]\nsub rdx, fs:28h\njnz loc_17AB\nadd rsp, 20h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1468:\nxor eax, eax\njmp short loc_1444\nloc_146C:\nxor ebx, ebx\nxchg ax, ax\nloc_1470:\nlea r14, [rsp+48h+base]\nlea rsi, [rbp+rbx+0]\nmov edx, 0Bh\nmov rdi, r14\ncall ___stpcpy_chk\nmovzx edx, [rsp+48h+var_3A]\nsub rax, r14\nmov rsi, rax; nmemb\ncmp rax, 1\njbe loc_1710\nmovzx eax, [rsp+48h+base]\ncmp rsi, 2\njz loc_1703\nmovzx ecx, [rsp+48h+var_39]\ncmp cl, al\njg loc_1650\ncmp rsi, 3\njz loc_1703\nmovzx edi, [rsp+48h+var_38]\nmov r13d, edx\ncmp al, dil\njl loc_16C0\ncmp rsi, 4\njz loc_178A\nloc_14DD:\nmovzx ecx, [rsp+48h+var_37]\ncmp cl, al\njg loc_16F0\ncmp rsi, 5\njz loc_1742\nloc_14F4:\nmovzx ecx, [rsp+48h+var_36]\ncmp cl, al\njle short loc_1504\ncmp r13b, cl\ncmovg r13d, ecx\nloc_1504:\ncmp rsi, 6\njz loc_16D8\nmovzx ecx, [rsp+48h+var_35]\ncmp cl, al\njle short loc_151E\ncmp r13b, cl\ncmovg r13d, ecx\nloc_151E:\ncmp rsi, 7\njz loc_16D8\nmovzx ecx, [rsp+48h+var_34]\ncmp al, cl\njge short loc_1538\ncmp r13b, cl\ncmovg r13d, ecx\nloc_1538:\ncmp rsi, 8\njz loc_16D8\nmovzx ecx, [rsp+48h+var_33]\ncmp al, cl\njge short loc_1552\ncmp r13b, cl\ncmovg r13d, ecx\nloc_1552:\ncmp rsi, 0Ah\njnz loc_16D8\nmovzx ecx, [rsp+48h+var_32]\ncmp cl, al\njle loc_16D8\ncmp r13b, cl\ncmovg r13d, ecx\ncmp al, r13b\njz loc_16E1\nloc_1579:\ncmp dl, r13b\njz loc_1680\nloc_1582:\ncmp [rsp+48h+var_39], r13b\njz loc_172E\ncmp rsi, 3\njz short loc_1604\ncmp [rsp+48h+var_38], r13b\njz loc_1738\ncmp rsi, 4\njz short loc_1604\ncmp [rsp+48h+var_37], r13b\njz loc_1758\ncmp rsi, 5\njz short loc_1604\ncmp [rsp+48h+var_36], r13b\njz loc_1762\ncmp rsi, 6\njz short loc_1604\ncmp [rsp+48h+var_35], r13b\njz loc_176C\ncmp rsi, 7\njz short loc_1604\ncmp [rsp+48h+var_34], r13b\njz loc_1776\ncmp rsi, 8\njz short loc_1604\ncmp [rsp+48h+var_33], r13b\njz loc_1780\ncmp rsi, 0Ah\njnz short loc_1604\ncmp r13b, [rsp+48h+var_32]\njz loc_17A0\nloc_1604:\nmov rcx, cs:compar; compar\nmov rdi, r14; base\nmov edx, 1; size\ncall _qsort\nmov [rsp+rbx+48h+s], r13b\nmov edx, 0Bh\nmov rsi, r14\nadd rbx, 1\nsub rdx, rbx\nlea rdi, [rbp+rbx+0]\ncall ___strcpy_chk\nmov edx, 0Ah; base\nxor esi, esi; endptr\nmov rdi, rbp; nptr\ncall _strtol\njmp loc_1444\nloc_1650:\ncmp dl, cl\nmov r13d, ecx\ncmovle r13d, edx\ncmp rsi, 3\njz short loc_16D8\nmovzx edi, [rsp+48h+var_38]\ncmp dil, al\njg short loc_16C0\ncmp rsi, 4\njnz loc_14DD\ncmp r13b, al\njz short loc_16E1\ncmp dl, cl\njg loc_1582\nloc_1680:\nmov edi, 1\nloc_1685:\nlea r12, [rsi-1]\ncmp rdi, r12\njnb short loc_16A1\nloc_168E:\nmov rdx, r12\nlea rsi, [r14+rdi+1]; src\nsub rdx, rdi; n\nadd rdi, r14; dest\ncall _memmove\nloc_16A1:\nmov rdi, r14; s\nmov [rsp+r12+48h+base], 0\ncall _strlen\nmov rsi, rax\njmp loc_1604\nloc_16C0:\ncmp r13b, dil\ncmovg r13d, edi\ncmp rsi, 4\nja loc_14DD\nnop dword ptr [rax+00000000h]\nloc_16D8:\ncmp r13b, al\njnz loc_1579\nloc_16E1:\nlea r12, [rsi-1]\nxor edi, edi\njmp short loc_168E\nloc_16F0:\ncmp r13b, cl\ncmovg r13d, ecx\ncmp rsi, 5\njnz loc_14F4\njmp short loc_16D8\nloc_1703:\nmov r13d, edx\ncmp dl, al\njnz loc_1680\njmp short loc_16E1\nloc_1710:\nmov r13d, edx\ntest rax, rax\njz loc_1604\ncmp dl, [rsp+48h+base]\njnz loc_1604\nxor r12d, r12d\njmp loc_16A1\nloc_172E:\nmov edi, 2\njmp loc_1685\nloc_1738:\nmov edi, 3\njmp loc_1685\nloc_1742:\ncmp r13b, al\njz short loc_16E1\ncmp r13b, dl\njnz loc_1582\njmp loc_1680\nloc_1758:\nmov edi, 4\njmp loc_1685\nloc_1762:\nmov edi, 5\njmp loc_1685\nloc_176C:\nmov edi, 6\njmp loc_1685\nloc_1776:\nmov edi, 7\njmp loc_1685\nloc_1780:\nmov edi, 8\njmp loc_1685\nloc_178A:\ncmp dl, al\njnz loc_1680\njmp loc_16E1\nloc_17A0:\nmov r12d, 9\njmp loc_16A1\nloc_17AB:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1)\n{\n int v1; // eax\n int v2; // edx\n __int64 v3; // rbx\n char v4; // cl\n char v5; // dl\n char v6; // cl\n char v7; // dl\n char v8; // cl\n char v9; // dl\n char v10; // cl\n char v11; // dl\n bool v12; // zf\n __int64 result; // rax\n unsigned __int64 v14; // rax\n size_t v15; // rsi\n char v16; // di\n char v17; // r13\n unsigned __int64 v18; // rdi\n __int64 v19; // r12\n char s[11]; // [rsp+2h] [rbp-46h] BYREF\n char base; // [rsp+Dh] [rbp-3Bh] BYREF\n char v22; // [rsp+Eh] [rbp-3Ah]\n char v23; // [rsp+Fh] [rbp-39h]\n char v24; // [rsp+10h] [rbp-38h]\n char v25; // [rsp+11h] [rbp-37h]\n char v26; // [rsp+12h] [rbp-36h]\n char v27; // [rsp+13h] [rbp-35h]\n char v28; // [rsp+14h] [rbp-34h]\n char v29; // [rsp+15h] [rbp-33h]\n char v30; // [rsp+16h] [rbp-32h]\n unsigned __int64 v31; // [rsp+18h] [rbp-30h]\n\n v31 = __readfsqword(0x28u);\n __sprintf_chk(s, 2LL, 11LL, &unk_2004, a1);\n v1 = strlen(s);\n v2 = v1 - 2;\n if ( v1 - 2 < 0 )\n return 0LL;\n v3 = v2;\n v4 = s[v2];\n if ( s[v2 + 1] > v4 )\n goto LABEL_22;\n LODWORD(v3) = v1 - 3;\n if ( v1 == 2 )\n return 0LL;\n v3 = (int)v3;\n v5 = s[(int)v3];\n if ( v4 > v5 )\n goto LABEL_22;\n LODWORD(v3) = v1 - 4;\n if ( v1 == 3 )\n return 0LL;\n v3 = (int)v3;\n v6 = s[(int)v3];\n if ( v5 > v6 )\n goto LABEL_22;\n LODWORD(v3) = v1 - 5;\n if ( v1 == 4 )\n return 0LL;\n v3 = (int)v3;\n v7 = s[(int)v3];\n if ( v6 > v7 )\n goto LABEL_22;\n LODWORD(v3) = v1 - 6;\n if ( v1 == 5 )\n return 0LL;\n v3 = (int)v3;\n v8 = s[(int)v3];\n if ( v7 > v8 )\n goto LABEL_22;\n LODWORD(v3) = v1 - 7;\n if ( v1 == 6 )\n return 0LL;\n v3 = (int)v3;\n v9 = s[(int)v3];\n if ( v8 > v9 )\n goto LABEL_22;\n LODWORD(v3) = v1 - 8;\n if ( v1 == 7 )\n return 0LL;\n v3 = (int)v3;\n v10 = s[(int)v3];\n if ( v9 > v10 )\n goto LABEL_22;\n LODWORD(v3) = v1 - 9;\n if ( v1 == 8 )\n return 0LL;\n v3 = (int)v3;\n v11 = s[(int)v3];\n if ( v10 > v11 )\n {\nLABEL_22:\n v14 = __stpcpy_chk(&base, &s[v3], 11LL) - (_QWORD)&base;\n v15 = v14;\n if ( v14 <= 1 )\n {\n v17 = v22;\n if ( !v14 || v22 != base )\n goto LABEL_66;\n v19 = 0LL;\n goto LABEL_77;\n }\n if ( v14 != 2 )\n {\n if ( v23 > base )\n {\n v17 = v23;\n if ( v22 <= v23 )\n v17 = v22;\n if ( v14 == 3 )\n goto LABEL_81;\n v16 = v24;\n if ( v24 <= base )\n {\n if ( v14 == 4 )\n {\n if ( v17 == base )\n goto LABEL_82;\n if ( v22 <= v23 )\n goto LABEL_74;\n goto LABEL_51;\n }\nLABEL_28:\n if ( v25 > base )\n {\n if ( v17 > v25 )\n v17 = v25;\n if ( v14 == 5 )\n goto LABEL_81;\n goto LABEL_30;\n }\n if ( v14 != 5 )\n {\nLABEL_30:\n if ( v26 > base && v17 > v26 )\n v17 = v26;\n if ( v14 != 6 )\n {\n if ( v27 > base && v17 > v27 )\n v17 = v27;\n if ( v14 != 7 )\n {\n if ( base < v28 && v17 > v28 )\n v17 = v28;\n if ( v14 != 8 )\n {\n if ( base < v29 && v17 > v29 )\n v17 = v29;\n if ( v14 == 10 && v30 > base )\n {\n if ( v17 > v30 )\n v17 = v30;\n if ( base != v17 )\n {\nLABEL_50:\n if ( v22 != v17 )\n goto LABEL_51;\nLABEL_74:\n v18 = 1LL;\n goto LABEL_75;\n }\nLABEL_82:\n v19 = v14 - 1;\n v18 = 0LL;\n goto LABEL_76;\n }\n }\n }\n }\nLABEL_81:\n if ( v17 != base )\n goto LABEL_50;\n goto LABEL_82;\n }\n if ( v17 == base )\n goto LABEL_82;\n if ( v17 == v22 )\n goto LABEL_74;\nLABEL_51:\n if ( v23 == v17 )\n {\n v18 = 2LL;\n goto LABEL_75;\n }\n if ( v14 != 3 )\n {\n if ( v24 == v17 )\n {\n v18 = 3LL;\n goto LABEL_75;\n }\n if ( v14 != 4 )\n {\n if ( v25 == v17 )\n {\n v18 = 4LL;\n goto LABEL_75;\n }\n if ( v14 != 5 )\n {\n if ( v26 == v17 )\n {\n v18 = 5LL;\n goto LABEL_75;\n }\n if ( v14 != 6 )\n {\n if ( v27 == v17 )\n {\n v18 = 6LL;\n goto LABEL_75;\n }\n if ( v14 != 7 )\n {\n if ( v28 == v17 )\n {\n v18 = 7LL;\n goto LABEL_75;\n }\n if ( v14 != 8 )\n {\n if ( v29 != v17 )\n {\n if ( v14 != 10 || v17 != v30 )\n goto LABEL_66;\n v19 = 9LL;\n goto LABEL_77;\n }\n v18 = 8LL;\nLABEL_75:\n v19 = v14 - 1;\n if ( v18 >= v14 - 1 )\n {\nLABEL_77:\n *(&base + v19) = 0;\n v15 = strlen(&base);\n goto LABEL_66;\n }\nLABEL_76:\n memmove(&base + v18, &base + v18 + 1, v19 - v18);\n goto LABEL_77;\n }\n }\n }\n }\n }\n }\nLABEL_66:\n qsort(&base, v15, 1uLL, (__compar_fn_t)&strcmp);\n s[v3] = v17;\n __strcpy_chk(&s[v3 + 1], &base, 11 - (v3 + 1));\n return strtol(s, 0LL, 10);\n }\nLABEL_78:\n if ( v17 > v16 )\n v17 = v16;\n if ( v14 <= 4 )\n goto LABEL_81;\n goto LABEL_28;\n }\n if ( v14 != 3 )\n {\n v16 = v24;\n v17 = v22;\n if ( base >= v24 )\n {\n if ( v14 == 4 )\n {\n if ( v22 != base )\n goto LABEL_74;\n goto LABEL_82;\n }\n goto LABEL_28;\n }\n goto LABEL_78;\n }\n }\n v17 = v22;\n if ( v22 != base )\n goto LABEL_74;\n goto LABEL_82;\n }\n v12 = v1 == 10;\n result = 0LL;\n if ( v12 && s[0] < v11 )\n {\n v3 = 0LL;\n goto LABEL_22;\n }\n return result;\n}", + "ida_strip_asm": "sub_1320:\nendbr64\npush r14\nmov r8d, edi\nmov edx, 0Bh\nmov esi, 2\npush r13\nlea rcx, unk_2004\npush r12\npush rbp\npush rbx\nsub rsp, 20h\nmov rax, fs:28h\nmov [rsp+48h+var_30], rax\nxor eax, eax\nlea rbp, [rsp+48h+s]\nmov rdi, rbp\ncall ___sprintf_chk\nmov rdi, rbp; s\ncall _strlen\nmov edx, eax\nsub edx, 2\njs loc_1468\nmovsxd rbx, edx\nmov edx, edx\nmovzx ecx, [rsp+rbx+48h+s]\ncmp [rsp+rdx+48h+var_45], cl\njg loc_1470\nlea ebx, [rax-3]\ncmp eax, 2\njz loc_1468\nmovsxd rbx, ebx\nmovzx edx, [rsp+rbx+48h+s]\ncmp cl, dl\njg loc_1470\nlea ebx, [rax-4]\ncmp eax, 3\njz loc_1468\nmovsxd rbx, ebx\nmovzx ecx, [rsp+rbx+48h+s]\ncmp dl, cl\njg loc_1470\nlea ebx, [rax-5]\ncmp eax, 4\njz loc_1468\nmovsxd rbx, ebx\nmovzx edx, [rsp+rbx+48h+s]\ncmp cl, dl\njg loc_1470\nlea ebx, [rax-6]\ncmp eax, 5\njz loc_1468\nmovsxd rbx, ebx\nmovzx ecx, [rsp+rbx+48h+s]\ncmp dl, cl\njg loc_1470\nlea ebx, [rax-7]\ncmp eax, 6\njz short loc_1468\nmovsxd rbx, ebx\nmovzx edx, [rsp+rbx+48h+s]\ncmp cl, dl\njg short loc_1470\nlea ebx, [rax-8]\ncmp eax, 7\njz short loc_1468\nmovsxd rbx, ebx\nmovzx ecx, [rsp+rbx+48h+s]\ncmp dl, cl\njg short loc_1470\nlea ebx, [rax-9]\ncmp eax, 8\njz short loc_1468\nmovsxd rbx, ebx\nmovzx edx, [rsp+rbx+48h+s]\ncmp cl, dl\njg short loc_1470\ncmp eax, 0Ah\nmov eax, 0\njnz short loc_1444\ncmp [rsp+48h+s], dl\njl short loc_146C\nloc_1444:\nmov rdx, [rsp+48h+var_30]\nsub rdx, fs:28h\njnz loc_17AB\nadd rsp, 20h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1468:\nxor eax, eax\njmp short loc_1444\nloc_146C:\nxor ebx, ebx\nxchg ax, ax\nloc_1470:\nlea r14, [rsp+48h+base]\nlea rsi, [rbp+rbx+0]\nmov edx, 0Bh\nmov rdi, r14\ncall ___stpcpy_chk\nmovzx edx, [rsp+48h+var_3A]\nsub rax, r14\nmov rsi, rax; nmemb\ncmp rax, 1\njbe loc_1710\nmovzx eax, [rsp+48h+base]\ncmp rsi, 2\njz loc_1703\nmovzx ecx, [rsp+48h+var_39]\ncmp cl, al\njg loc_1650\ncmp rsi, 3\njz loc_1703\nmovzx edi, [rsp+48h+var_38]\nmov r13d, edx\ncmp al, dil\njl loc_16C0\ncmp rsi, 4\njz loc_178A\nloc_14DD:\nmovzx ecx, [rsp+48h+var_37]\ncmp cl, al\njg loc_16F0\ncmp rsi, 5\njz loc_1742\nloc_14F4:\nmovzx ecx, [rsp+48h+var_36]\ncmp cl, al\njle short loc_1504\ncmp r13b, cl\ncmovg r13d, ecx\nloc_1504:\ncmp rsi, 6\njz loc_16D8\nmovzx ecx, [rsp+48h+var_35]\ncmp cl, al\njle short loc_151E\ncmp r13b, cl\ncmovg r13d, ecx\nloc_151E:\ncmp rsi, 7\njz loc_16D8\nmovzx ecx, [rsp+48h+var_34]\ncmp al, cl\njge short loc_1538\ncmp r13b, cl\ncmovg r13d, ecx\nloc_1538:\ncmp rsi, 8\njz loc_16D8\nmovzx ecx, [rsp+48h+var_33]\ncmp al, cl\njge short loc_1552\ncmp r13b, cl\ncmovg r13d, ecx\nloc_1552:\ncmp rsi, 0Ah\njnz loc_16D8\nmovzx ecx, [rsp+48h+var_32]\ncmp cl, al\njle loc_16D8\ncmp r13b, cl\ncmovg r13d, ecx\ncmp al, r13b\njz loc_16E1\nloc_1579:\ncmp dl, r13b\njz loc_1680\nloc_1582:\ncmp [rsp+48h+var_39], r13b\njz loc_172E\ncmp rsi, 3\njz short loc_1604\ncmp [rsp+48h+var_38], r13b\njz loc_1738\ncmp rsi, 4\njz short loc_1604\ncmp [rsp+48h+var_37], r13b\njz loc_1758\ncmp rsi, 5\njz short loc_1604\ncmp [rsp+48h+var_36], r13b\njz loc_1762\ncmp rsi, 6\njz short loc_1604\ncmp [rsp+48h+var_35], r13b\njz loc_176C\ncmp rsi, 7\njz short loc_1604\ncmp [rsp+48h+var_34], r13b\njz loc_1776\ncmp rsi, 8\njz short loc_1604\ncmp [rsp+48h+var_33], r13b\njz loc_1780\ncmp rsi, 0Ah\njnz short loc_1604\ncmp r13b, [rsp+48h+var_32]\njz loc_17A0\nloc_1604:\nmov rcx, cs:compar; compar\nmov rdi, r14; base\nmov edx, 1; size\ncall _qsort\nmov [rsp+rbx+48h+s], r13b\nmov edx, 0Bh\nmov rsi, r14\nadd rbx, 1\nsub rdx, rbx\nlea rdi, [rbp+rbx+0]\ncall ___strcpy_chk\nmov edx, 0Ah; base\nxor esi, esi; endptr\nmov rdi, rbp; nptr\ncall _strtol\njmp loc_1444\nloc_1650:\ncmp dl, cl\nmov r13d, ecx\ncmovle r13d, edx\ncmp rsi, 3\njz short loc_16D8\nmovzx edi, [rsp+48h+var_38]\ncmp dil, al\njg short loc_16C0\ncmp rsi, 4\njnz loc_14DD\ncmp r13b, al\njz short loc_16E1\ncmp dl, cl\njg loc_1582\nloc_1680:\nmov edi, 1\nloc_1685:\nlea r12, [rsi-1]\ncmp rdi, r12\njnb short loc_16A1\nloc_168E:\nmov rdx, r12\nlea rsi, [r14+rdi+1]; src\nsub rdx, rdi; n\nadd rdi, r14; dest\ncall _memmove\nloc_16A1:\nmov rdi, r14; s\nmov [rsp+r12+48h+base], 0\ncall _strlen\nmov rsi, rax\njmp loc_1604\nloc_16C0:\ncmp r13b, dil\ncmovg r13d, edi\ncmp rsi, 4\nja loc_14DD\nnop dword ptr [rax+00000000h]\nloc_16D8:\ncmp r13b, al\njnz loc_1579\nloc_16E1:\nlea r12, [rsi-1]\nxor edi, edi\njmp short loc_168E\nloc_16F0:\ncmp r13b, cl\ncmovg r13d, ecx\ncmp rsi, 5\njnz loc_14F4\njmp short loc_16D8\nloc_1703:\nmov r13d, edx\ncmp dl, al\njnz loc_1680\njmp short loc_16E1\nloc_1710:\nmov r13d, edx\ntest rax, rax\njz loc_1604\ncmp dl, [rsp+48h+base]\njnz loc_1604\nxor r12d, r12d\njmp loc_16A1\nloc_172E:\nmov edi, 2\njmp loc_1685\nloc_1738:\nmov edi, 3\njmp loc_1685\nloc_1742:\ncmp r13b, al\njz short loc_16E1\ncmp r13b, dl\njnz loc_1582\njmp loc_1680\nloc_1758:\nmov edi, 4\njmp loc_1685\nloc_1762:\nmov edi, 5\njmp loc_1685\nloc_176C:\nmov edi, 6\njmp loc_1685\nloc_1776:\nmov edi, 7\njmp loc_1685\nloc_1780:\nmov edi, 8\njmp loc_1685\nloc_178A:\ncmp dl, al\njnz loc_1680\njmp loc_16E1\nloc_17A0:\nmov r12d, 9\njmp loc_16A1\nloc_17AB:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1320(unsigned int a1)\n{\n int v1; // eax\n int v2; // edx\n __int64 v3; // rbx\n char v4; // cl\n char v5; // dl\n char v6; // cl\n char v7; // dl\n char v8; // cl\n char v9; // dl\n char v10; // cl\n char v11; // dl\n bool v12; // zf\n __int64 result; // rax\n unsigned __int64 v14; // rax\n size_t v15; // rsi\n char v16; // di\n char v17; // r13\n unsigned __int64 v18; // rdi\n __int64 v19; // r12\n char s[11]; // [rsp+2h] [rbp-46h] BYREF\n char base; // [rsp+Dh] [rbp-3Bh] BYREF\n char v22; // [rsp+Eh] [rbp-3Ah]\n char v23; // [rsp+Fh] [rbp-39h]\n char v24; // [rsp+10h] [rbp-38h]\n char v25; // [rsp+11h] [rbp-37h]\n char v26; // [rsp+12h] [rbp-36h]\n char v27; // [rsp+13h] [rbp-35h]\n char v28; // [rsp+14h] [rbp-34h]\n char v29; // [rsp+15h] [rbp-33h]\n char v30; // [rsp+16h] [rbp-32h]\n unsigned __int64 v31; // [rsp+18h] [rbp-30h]\n\n v31 = __readfsqword(0x28u);\n __sprintf_chk(s, 2LL, 11LL, &unk_2004, a1);\n v1 = strlen(s);\n v2 = v1 - 2;\n if ( v1 - 2 < 0 )\n return 0LL;\n v3 = v2;\n v4 = s[v2];\n if ( s[v2 + 1] > v4 )\n goto LABEL_22;\n LODWORD(v3) = v1 - 3;\n if ( v1 == 2 )\n return 0LL;\n v3 = (int)v3;\n v5 = s[(int)v3];\n if ( v4 > v5 )\n goto LABEL_22;\n LODWORD(v3) = v1 - 4;\n if ( v1 == 3 )\n return 0LL;\n v3 = (int)v3;\n v6 = s[(int)v3];\n if ( v5 > v6 )\n goto LABEL_22;\n LODWORD(v3) = v1 - 5;\n if ( v1 == 4 )\n return 0LL;\n v3 = (int)v3;\n v7 = s[(int)v3];\n if ( v6 > v7 )\n goto LABEL_22;\n LODWORD(v3) = v1 - 6;\n if ( v1 == 5 )\n return 0LL;\n v3 = (int)v3;\n v8 = s[(int)v3];\n if ( v7 > v8 )\n goto LABEL_22;\n LODWORD(v3) = v1 - 7;\n if ( v1 == 6 )\n return 0LL;\n v3 = (int)v3;\n v9 = s[(int)v3];\n if ( v8 > v9 )\n goto LABEL_22;\n LODWORD(v3) = v1 - 8;\n if ( v1 == 7 )\n return 0LL;\n v3 = (int)v3;\n v10 = s[(int)v3];\n if ( v9 > v10 )\n goto LABEL_22;\n LODWORD(v3) = v1 - 9;\n if ( v1 == 8 )\n return 0LL;\n v3 = (int)v3;\n v11 = s[(int)v3];\n if ( v10 > v11 )\n {\nLABEL_22:\n v14 = __stpcpy_chk(&base, &s[v3], 11LL) - (_QWORD)&base;\n v15 = v14;\n if ( v14 <= 1 )\n {\n v17 = v22;\n if ( !v14 || v22 != base )\n goto LABEL_66;\n v19 = 0LL;\n goto LABEL_77;\n }\n if ( v14 != 2 )\n {\n if ( v23 > base )\n {\n v17 = v23;\n if ( v22 <= v23 )\n v17 = v22;\n if ( v14 == 3 )\n goto LABEL_81;\n v16 = v24;\n if ( v24 <= base )\n {\n if ( v14 == 4 )\n {\n if ( v17 == base )\n goto LABEL_82;\n if ( v22 <= v23 )\n goto LABEL_74;\n goto LABEL_51;\n }\nLABEL_28:\n if ( v25 > base )\n {\n if ( v17 > v25 )\n v17 = v25;\n if ( v14 == 5 )\n goto LABEL_81;\n goto LABEL_30;\n }\n if ( v14 != 5 )\n {\nLABEL_30:\n if ( v26 > base && v17 > v26 )\n v17 = v26;\n if ( v14 != 6 )\n {\n if ( v27 > base && v17 > v27 )\n v17 = v27;\n if ( v14 != 7 )\n {\n if ( base < v28 && v17 > v28 )\n v17 = v28;\n if ( v14 != 8 )\n {\n if ( base < v29 && v17 > v29 )\n v17 = v29;\n if ( v14 == 10 && v30 > base )\n {\n if ( v17 > v30 )\n v17 = v30;\n if ( base != v17 )\n {\nLABEL_50:\n if ( v22 != v17 )\n goto LABEL_51;\nLABEL_74:\n v18 = 1LL;\n goto LABEL_75;\n }\nLABEL_82:\n v19 = v14 - 1;\n v18 = 0LL;\n goto LABEL_76;\n }\n }\n }\n }\nLABEL_81:\n if ( v17 != base )\n goto LABEL_50;\n goto LABEL_82;\n }\n if ( v17 == base )\n goto LABEL_82;\n if ( v17 == v22 )\n goto LABEL_74;\nLABEL_51:\n if ( v23 == v17 )\n {\n v18 = 2LL;\n goto LABEL_75;\n }\n if ( v14 != 3 )\n {\n if ( v24 == v17 )\n {\n v18 = 3LL;\n goto LABEL_75;\n }\n if ( v14 != 4 )\n {\n if ( v25 == v17 )\n {\n v18 = 4LL;\n goto LABEL_75;\n }\n if ( v14 != 5 )\n {\n if ( v26 == v17 )\n {\n v18 = 5LL;\n goto LABEL_75;\n }\n if ( v14 != 6 )\n {\n if ( v27 == v17 )\n {\n v18 = 6LL;\n goto LABEL_75;\n }\n if ( v14 != 7 )\n {\n if ( v28 == v17 )\n {\n v18 = 7LL;\n goto LABEL_75;\n }\n if ( v14 != 8 )\n {\n if ( v29 != v17 )\n {\n if ( v14 != 10 || v17 != v30 )\n goto LABEL_66;\n v19 = 9LL;\n goto LABEL_77;\n }\n v18 = 8LL;\nLABEL_75:\n v19 = v14 - 1;\n if ( v18 >= v14 - 1 )\n {\nLABEL_77:\n *(&base + v19) = 0;\n v15 = strlen(&base);\n goto LABEL_66;\n }\nLABEL_76:\n memmove(&base + v18, &base + v18 + 1, v19 - v18);\n goto LABEL_77;\n }\n }\n }\n }\n }\n }\nLABEL_66:\n qsort(&base, v15, 1uLL, (__compar_fn_t)&strcmp);\n s[v3] = v17;\n __strcpy_chk(&s[v3 + 1], &base, 11 - (v3 + 1));\n return strtol(s, 0LL, 10);\n }\nLABEL_78:\n if ( v17 > v16 )\n v17 = v16;\n if ( v14 <= 4 )\n goto LABEL_81;\n goto LABEL_28;\n }\n if ( v14 != 3 )\n {\n v16 = v24;\n v17 = v22;\n if ( base >= v24 )\n {\n if ( v14 == 4 )\n {\n if ( v22 != base )\n goto LABEL_74;\n goto LABEL_82;\n }\n goto LABEL_28;\n }\n goto LABEL_78;\n }\n }\n v17 = v22;\n if ( v22 != base )\n goto LABEL_74;\n goto LABEL_82;\n }\n v12 = v1 == 10;\n result = 0LL;\n if ( v12 && s[0] < v11 )\n {\n v3 = 0LL;\n goto LABEL_22;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1320(unsigned int a1) {\n int v1;\n int v2;\n long long v3;\n char v4;\n char v5;\n char v6;\n char v7;\n char v8;\n char v9;\n char v10;\n char v11;\n bool v12;\n long long result;\n unsigned long long v14;\n unsigned int v15;\n char v16;\n char v17;\n unsigned long long v18;\n long long v19;\n char s[11];\n char base;\n char v22;\n char v23;\n char v24;\n char v25;\n char v26;\n char v27;\n char v28;\n char v29;\n char v30;\n unsigned long long v31;\n v31 = __readfsqword(40u);\n __sprintf_chk(s, 2LL, 11LL, &unk_2004, a1);\n v1 = strlen(s);\n v2 = v1 - 2;\n if (v1 - 2 < 0) return 0LL;\n v3 = v2;\n v4 = s[v2];\n if (s[v2 + 1] > v4) goto LABEL_22;\n LODWORD(v3) = v1 - 3;\n if (v1 == 2) return 0LL;\n v3 = (int)v3;\n v5 = s[(int)v3];\n if (v4 > v5) goto LABEL_22;\n LODWORD(v3) = v1 - 4;\n if (v1 == 3) return 0LL;\n v3 = (int)v3;\n v6 = s[(int)v3];\n if (v5 > v6) goto LABEL_22;\n LODWORD(v3) = v1 - 5;\n if (v1 == 4) return 0LL;\n v3 = (int)v3;\n v7 = s[(int)v3];\n if (v6 > v7) goto LABEL_22;\n LODWORD(v3) = v1 - 6;\n if (v1 == 5) return 0LL;\n v3 = (int)v3;\n v8 = s[(int)v3];\n if (v7 > v8) goto LABEL_22;\n LODWORD(v3) = v1 - 7;\n if (v1 == 6) return 0LL;\n v3 = (int)v3;\n v9 = s[(int)v3];\n if (v8 > v9) goto LABEL_22;\n LODWORD(v3) = v1 - 8;\n if (v1 == 7) return 0LL;\n v3 = (int)v3;\n v10 = s[(int)v3];\n if (v9 > v10) goto LABEL_22;\n LODWORD(v3) = v1 - 9;\n if (v1 == 8) return 0LL;\n v3 = (int)v3;\n v11 = s[(int)v3];\n if (v10 > v11) {\n LABEL_22:\n v14 = __stpcpy_chk(&base, &s[v3], 11LL) - (uint64_t)&base;\n v15 = v14;\n if (v14 <= 1) {\n v17 = v22;\n if (!v14 || v22 != base) goto LABEL_66;\n v19 = 0LL;\n goto LABEL_77;\n }\n if (v14 != 2) {\n if (v23 > base) {\n v17 = v23;\n if (v22 <= v23) v17 = v22;\n if (v14 == 3) goto LABEL_81;\n v16 = v24;\n if (v24 <= base) {\n if (v14 == 4) {\n if (v17 == base) goto LABEL_82;\n if (v22 <= v23) goto LABEL_74;\n goto LABEL_51;\n }\n LABEL_28:\n if (v25 > base) {\n if (v17 > v25) v17 = v25;\n if (v14 == 5) goto LABEL_81;\n goto LABEL_30;\n }\n if (v14 != 5) {\n LABEL_30:\n if (v26 > base && v17 > v26) v17 = v26;\n if (v14 != 6) {\n if (v27 > base && v17 > v27) v17 = v27;\n if (v14 != 7) {\n if (base < v28 && v17 > v28) v17 = v28;\n if (v14 != 8) {\n if (base < v29 && v17 > v29) v17 = v29;\n if (v14 == 10 && v30 > base) {\n if (v17 > v30) v17 = v30;\n if (base != v17) {\n LABEL_50:\n if (v22 != v17) goto LABEL_51;\n LABEL_74:\n v18 = 1LL;\n goto LABEL_75;\n }\n LABEL_82:\n v19 = v14 - 1;\n v18 = 0LL;\n goto LABEL_76;\n }\n }\n }\n }\n LABEL_81:\n if (v17 != base) goto LABEL_50;\n goto LABEL_82;\n }\n if (v17 == base) goto LABEL_82;\n if (v17 == v22) goto LABEL_74;\n LABEL_51:\n if (v23 == v17) {\n v18 = 2LL;\n goto LABEL_75;\n }\n if (v14 != 3) {\n if (v24 == v17) {\n v18 = 3LL;\n goto LABEL_75;\n }\n if (v14 != 4) {\n if (v25 == v17) {\n v18 = 4LL;\n goto LABEL_75;\n }\n if (v14 != 5) {\n if (v26 == v17) {\n v18 = 5LL;\n goto LABEL_75;\n }\n if (v14 != 6) {\n if (v27 == v17) {\n v18 = 6LL;\n goto LABEL_75;\n }\n if (v14 != 7) {\n if (v28 == v17) {\n v18 = 7LL;\n goto LABEL_75;\n }\n if (v14 != 8) {\n if (v29 != v17) {\n if (v14 != 10 || v17 != v30) goto LABEL_66;\n v19 = 9LL;\n goto LABEL_77;\n }\n v18 = 8LL;\n LABEL_75:\n v19 = v14 - 1;\n if (v18 >= v14 - 1) {\n LABEL_77:\n *(&base + v19) = 0;\n v15 = strlen(&base);\n goto LABEL_66;\n }\n LABEL_76:\n memmove(&base + v18, &base + v18 + 1, v19 - v18);\n goto LABEL_77;\n }\n }\n }\n }\n }\n }\n LABEL_66:\n qsort(&base, v15, 1uLL,\n (int (*)(const void *, const void *)) & strcmp);\n s[v3] = v17;\n __strcpy_chk(&s[v3 + 1], &base, 11 - (v3 + 1));\n return strtol(s, 0LL, 10);\n }\n LABEL_78:\n if (v17 > v16) v17 = v16;\n if (v14 <= 4) goto LABEL_81;\n goto LABEL_28;\n }\n if (v14 != 3) {\n v16 = v24;\n v17 = v22;\n if (base >= v24) {\n if (v14 == 4) {\n if (v22 != base) goto LABEL_74;\n goto LABEL_82;\n }\n goto LABEL_28;\n }\n goto LABEL_78;\n }\n }\n v17 = v22;\n if (v22 != base) goto LABEL_74;\n goto LABEL_82;\n }\n v12 = v1 == 10;\n result = 0LL;\n if (v12 && s[0] < v11) {\n v3 = 0LL;\n goto LABEL_22;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(unsigned int a1) {\n int v1;\n int v2;\n long long v3;\n char v4;\n char v5;\n char v6;\n char v7;\n char v8;\n char v9;\n char v10;\n char v11;\n bool v12;\n long long result;\n unsigned long long v14;\n unsigned int v15;\n char v16;\n char v17;\n unsigned long long v18;\n long long v19;\n char s[11];\n char base;\n char v22;\n char v23;\n char v24;\n char v25;\n char v26;\n char v27;\n char v28;\n char v29;\n char v30;\n unsigned long long v31;\n v31 = __readfsqword(40u);\n __sprintf_chk(s, 2LL, 11LL, &unk_2004, a1);\n v1 = strlen(s);\n v2 = v1 - 2;\n if (v1 - 2 < 0) return 0LL;\n v3 = v2;\n v4 = s[v2];\n if (s[v2 + 1] > v4) goto LABEL_22;\n LODWORD(v3) = v1 - 3;\n if (v1 == 2) return 0LL;\n v3 = (int)v3;\n v5 = s[(int)v3];\n if (v4 > v5) goto LABEL_22;\n LODWORD(v3) = v1 - 4;\n if (v1 == 3) return 0LL;\n v3 = (int)v3;\n v6 = s[(int)v3];\n if (v5 > v6) goto LABEL_22;\n LODWORD(v3) = v1 - 5;\n if (v1 == 4) return 0LL;\n v3 = (int)v3;\n v7 = s[(int)v3];\n if (v6 > v7) goto LABEL_22;\n LODWORD(v3) = v1 - 6;\n if (v1 == 5) return 0LL;\n v3 = (int)v3;\n v8 = s[(int)v3];\n if (v7 > v8) goto LABEL_22;\n LODWORD(v3) = v1 - 7;\n if (v1 == 6) return 0LL;\n v3 = (int)v3;\n v9 = s[(int)v3];\n if (v8 > v9) goto LABEL_22;\n LODWORD(v3) = v1 - 8;\n if (v1 == 7) return 0LL;\n v3 = (int)v3;\n v10 = s[(int)v3];\n if (v9 > v10) goto LABEL_22;\n LODWORD(v3) = v1 - 9;\n if (v1 == 8) return 0LL;\n v3 = (int)v3;\n v11 = s[(int)v3];\n if (v10 > v11) {\n LABEL_22:\n v14 = __stpcpy_chk(&base, &s[v3], 11LL) - (uint64_t)&base;\n v15 = v14;\n if (v14 <= 1) {\n v17 = v22;\n if (!v14 || v22 != base) goto LABEL_66;\n v19 = 0LL;\n goto LABEL_77;\n }\n if (v14 != 2) {\n if (v23 > base) {\n v17 = v23;\n if (v22 <= v23) v17 = v22;\n if (v14 == 3) goto LABEL_81;\n v16 = v24;\n if (v24 <= base) {\n if (v14 == 4) {\n if (v17 == base) goto LABEL_82;\n if (v22 <= v23) goto LABEL_74;\n goto LABEL_51;\n }\n LABEL_28:\n if (v25 > base) {\n if (v17 > v25) v17 = v25;\n if (v14 == 5) goto LABEL_81;\n goto LABEL_30;\n }\n if (v14 != 5) {\n LABEL_30:\n if (v26 > base && v17 > v26) v17 = v26;\n if (v14 != 6) {\n if (v27 > base && v17 > v27) v17 = v27;\n if (v14 != 7) {\n if (base < v28 && v17 > v28) v17 = v28;\n if (v14 != 8) {\n if (base < v29 && v17 > v29) v17 = v29;\n if (v14 == 10 && v30 > base) {\n if (v17 > v30) v17 = v30;\n if (base != v17) {\n LABEL_50:\n if (v22 != v17) goto LABEL_51;\n LABEL_74:\n v18 = 1LL;\n goto LABEL_75;\n }\n LABEL_82:\n v19 = v14 - 1;\n v18 = 0LL;\n goto LABEL_76;\n }\n }\n }\n }\n LABEL_81:\n if (v17 != base) goto LABEL_50;\n goto LABEL_82;\n }\n if (v17 == base) goto LABEL_82;\n if (v17 == v22) goto LABEL_74;\n LABEL_51:\n if (v23 == v17) {\n v18 = 2LL;\n goto LABEL_75;\n }\n if (v14 != 3) {\n if (v24 == v17) {\n v18 = 3LL;\n goto LABEL_75;\n }\n if (v14 != 4) {\n if (v25 == v17) {\n v18 = 4LL;\n goto LABEL_75;\n }\n if (v14 != 5) {\n if (v26 == v17) {\n v18 = 5LL;\n goto LABEL_75;\n }\n if (v14 != 6) {\n if (v27 == v17) {\n v18 = 6LL;\n goto LABEL_75;\n }\n if (v14 != 7) {\n if (v28 == v17) {\n v18 = 7LL;\n goto LABEL_75;\n }\n if (v14 != 8) {\n if (v29 != v17) {\n if (v14 != 10 || v17 != v30) goto LABEL_66;\n v19 = 9LL;\n goto LABEL_77;\n }\n v18 = 8LL;\n LABEL_75:\n v19 = v14 - 1;\n if (v18 >= v14 - 1) {\n LABEL_77:\n *(&base + v19) = 0;\n v15 = strlen(&base);\n goto LABEL_66;\n }\n LABEL_76:\n memmove(&base + v18, &base + v18 + 1, v19 - v18);\n goto LABEL_77;\n }\n }\n }\n }\n }\n }\n LABEL_66:\n qsort(&base, v15, 1uLL,\n (int (*)(const void *, const void *)) & strcmp);\n s[v3] = v17;\n __strcpy_chk(&s[v3 + 1], &base, 11 - (v3 + 1));\n return strtol(s, 0LL, 10);\n }\n LABEL_78:\n if (v17 > v16) v17 = v16;\n if (v14 <= 4) goto LABEL_81;\n goto LABEL_28;\n }\n if (v14 != 3) {\n v16 = v24;\n v17 = v22;\n if (base >= v24) {\n if (v14 == 4) {\n if (v22 != base) goto LABEL_74;\n goto LABEL_82;\n }\n goto LABEL_28;\n }\n goto LABEL_78;\n }\n }\n v17 = v22;\n if (v22 != base) goto LABEL_74;\n goto LABEL_82;\n }\n v12 = v1 == 10;\n result = 0LL;\n if (v12 && s[0] < v11) {\n v3 = 0LL;\n goto LABEL_22;\n }\n return result;\n}" + }, + { + "index": 408, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int sum;\n\n int index1;\n\n int index2;\n\n} HeapNode;\n\n\n\nvoid swap(HeapNode *a, HeapNode *b) {\n\n HeapNode temp = *a;\n\n *a = *b;\n\n *b = temp;\n\n}\n\n\n\nvoid heapify(HeapNode heap[], int n, int i) {\n\n int smallest = i;\n\n int l = 2*i + 1;\n\n int r = 2*i + 2;\n\n\n\n if (l < n && heap[l].sum < heap[smallest].sum)\n\n smallest = l;\n\n\n\n if (r < n && heap[r].sum < heap[smallest].sum)\n\n smallest = r;\n\n\n\n if (smallest != i) {\n\n swap(&heap[i], &heap[smallest]);\n\n heapify(heap, n, smallest);\n\n }\n\n}\n\n\n\nvoid heapPush(HeapNode heap[], int *size, HeapNode node) {\n\n int i = *size;\n\n heap[i] = node;\n\n (*size)++;\n\n while (i != 0 && heap[(i-1)/2].sum > heap[i].sum) {\n\n swap(&heap[(i-1)/2], &heap[i]);\n\n i = (i-1)/2;\n\n }\n\n}\n\n\n\nHeapNode heapPop(HeapNode heap[], int *size) {\n\n if (*size <= 0) {\n\n HeapNode invalid = {-1, -1, -1};\n\n return invalid;\n\n }\n\n if (*size == 1) {\n\n (*size)--;\n\n return heap[0];\n\n }\n\n HeapNode root = heap[0];\n\n heap[0] = heap[*size - 1];\n\n (*size)--;\n\n heapify(heap, *size, 0);\n\n return root;\n\n}\n\n\n\n", + "func": "int **func0(int nums1[], int nums1Size, int nums2[], int nums2Size, int k,\n int *returnSize) {\n HeapNode *heap =\n (HeapNode *)malloc(sizeof(HeapNode) * (nums1Size * nums2Size));\n int heapSize = 0;\n int **result = (int **)malloc(sizeof(int *) * k);\n for (int i = 0; i < k; i++) {\n result[i] = (int *)malloc(sizeof(int) * 2);\n }\n if (nums1Size == 0 || nums2Size == 0 || k == 0) {\n *returnSize = 0;\n free(heap);\n return result;\n }\n heapPush(heap, &heapSize, (HeapNode){nums1[0] + nums2[0], 0, 0});\n int count = 0;\n while (heapSize > 0 && count < k) {\n HeapNode node = heapPop(heap, &heapSize);\n result[count][0] = nums1[node.index1];\n result[count][1] = nums2[node.index2];\n count++;\n if (node.index2 + 1 < nums2Size) {\n heapPush(heap, &heapSize,\n (HeapNode){nums1[node.index1] + nums2[node.index2 + 1],\n node.index1, node.index2 + 1});\n }\n if (node.index2 == 0 && node.index1 + 1 < nums1Size) {\n heapPush(\n heap, &heapSize,\n (HeapNode){nums1[node.index1 + 1] + nums2[0], node.index1 + 1, 0});\n }\n }\n *returnSize = count;\n free(heap);\n return result;\n}", + "test": "int main() {\n\n int returnSize;\n\n int **result;\n\n\n\n result = func0((int[]){1, 3, 7}, 3, (int[]){2, 4, 6}, 3, 2, &returnSize);\n\n assert(returnSize == 2 && result[0][0] == 1 && result[0][1] == 2 && result[1][0] == 1 && result[1][1] == 4);\n\n\n\n result = func0((int[]){1, 3, 7}, 3, (int[]){2, 4, 6}, 3, 1, &returnSize);\n\n assert(returnSize == 1 && result[0][0] == 1 && result[0][1] == 2);\n\n\n\n result = func0((int[]){1, 3, 7}, 3, (int[]){2, 4, 6}, 3, 7, &returnSize);\n\n assert(returnSize == 7 && result[0][0] == 1 && result[0][1] == 2 && result[1][0] == 1 && result[1][1] == 4);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x88,%rsp\nmov %rdi,-0x68(%rbp)\nmov %esi,-0x6c(%rbp)\nmov %rdx,-0x78(%rbp)\nmov %ecx,-0x70(%rbp)\nmov %r8d,-0x7c(%rbp)\nmov %r9,-0x88(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmov -0x6c(%rbp),%eax\nimul -0x70(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x50(%rbp)\nmovl $0x0,-0x5c(%rbp)\nmov -0x7c(%rbp),%eax\ncltq\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x48(%rbp)\nmovl $0x0,-0x58(%rbp)\njmp 15f2 \nmov -0x58(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x48(%rbp),%rax\nlea (%rdx,%rax,1),%rbx\nmov $0x8,%edi\ncallq 10b0 \nmov %rax,(%rbx)\naddl $0x1,-0x58(%rbp)\nmov -0x58(%rbp),%eax\ncmp -0x7c(%rbp),%eax\njl 15cc \ncmpl $0x0,-0x6c(%rbp)\nje 160c \ncmpl $0x0,-0x70(%rbp)\nje 160c \ncmpl $0x0,-0x7c(%rbp)\njne 162e \nmov -0x88(%rbp),%rax\nmovl $0x0,(%rax)\nmov -0x50(%rbp),%rax\nmov %rax,%rdi\ncallq 1080 \nmov -0x48(%rbp),%rax\njmpq 17fe \nmov -0x68(%rbp),%rax\nmov (%rax),%edx\nmov -0x78(%rbp),%rax\nmov (%rax),%eax\nadd %edx,%eax\nmov %eax,-0x3c(%rbp)\nmovl $0x0,-0x38(%rbp)\nmovl $0x0,-0x34(%rbp)\nmov -0x3c(%rbp),%rax\nmov -0x34(%rbp),%ecx\nmov %rcx,%rdx\nlea -0x5c(%rbp),%rsi\nmov -0x50(%rbp),%rdi\nmov %rdx,%rcx\nmov %rax,%rdx\ncallq 1329 \nmovl $0x0,-0x54(%rbp)\njmpq 17cf \nlea -0x5c(%rbp),%rdx\nmov -0x50(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1455 \nmov %rax,-0x30(%rbp)\nmov -0x28(%rbp),%eax\nand $0x0,%eax\nor %edx,%eax\nmov %eax,-0x28(%rbp)\nmov -0x2c(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x68(%rbp),%rax\nadd %rax,%rdx\nmov -0x54(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x48(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%rax\nmov (%rdx),%edx\nmov %edx,(%rax)\nmov -0x28(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x78(%rbp),%rax\nadd %rdx,%rax\nmov -0x54(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x48(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rdx),%rdx\nadd $0x4,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x54(%rbp)\nmov -0x28(%rbp),%eax\nadd $0x1,%eax\ncmp %eax,-0x70(%rbp)\njle 176b \nmov -0x2c(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x68(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x28(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rcx\nmov -0x78(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\nadd %edx,%eax\nmov %eax,-0x24(%rbp)\nmov -0x2c(%rbp),%eax\nmov %eax,-0x20(%rbp)\nmov -0x28(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x1c(%rbp)\nmov -0x24(%rbp),%rax\nmov -0x1c(%rbp),%ecx\nmov %rcx,%rdx\nlea -0x5c(%rbp),%rsi\nmov -0x50(%rbp),%rdi\nmov %rdx,%rcx\nmov %rax,%rdx\ncallq 1329 \nmov -0x28(%rbp),%eax\ntest %eax,%eax\njne 17cf \nmov -0x2c(%rbp),%eax\nadd $0x1,%eax\ncmp %eax,-0x6c(%rbp)\njle 17cf \nmov -0x2c(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x68(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x78(%rbp),%rax\nmov (%rax),%eax\nadd %edx,%eax\nmov %eax,-0x24(%rbp)\nmov -0x2c(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x20(%rbp)\nmovl $0x0,-0x1c(%rbp)\nmov -0x24(%rbp),%rax\nmov -0x1c(%rbp),%ecx\nmov %rcx,%rdx\nlea -0x5c(%rbp),%rsi\nmov -0x50(%rbp),%rdi\nmov %rdx,%rcx\nmov %rax,%rdx\ncallq 1329 \nmov -0x5c(%rbp),%eax\ntest %eax,%eax\njle 17e2 \nmov -0x54(%rbp),%eax\ncmp -0x7c(%rbp),%eax\njl 1676 \nmov -0x88(%rbp),%rax\nmov -0x54(%rbp),%edx\nmov %edx,(%rax)\nmov -0x50(%rbp),%rax\nmov %rax,%rdi\ncallq 1080 \nmov -0x48(%rbp),%rax\nmov -0x18(%rbp),%rbx\nxor %fs:0x28,%rbx\nje 1812 \ncallq 1090 <__stack_chk_fail@plt>\nadd $0x88,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 88h\nmov [rbp+var_68], rdi\nmov [rbp+var_6C], esi\nmov [rbp+var_78], rdx\nmov [rbp+var_70], ecx\nmov [rbp+var_7C], r8d\nmov [rbp+var_88], r9\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov eax, [rbp+var_6C]\nimul eax, [rbp+var_70]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov [rbp+var_5C], 0\nmov eax, [rbp+var_7C]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_48], rax\nmov [rbp+var_58], 0\njmp short loc_15F2\nloc_15CC:\nmov eax, [rbp+var_58]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nlea rbx, [rdx+rax]\nmov edi, 8; size\ncall _malloc\nmov [rbx], rax\nadd [rbp+var_58], 1\nloc_15F2:\nmov eax, [rbp+var_58]\ncmp eax, [rbp+var_7C]\njl short loc_15CC\ncmp [rbp+var_6C], 0\njz short loc_160C\ncmp [rbp+var_70], 0\njz short loc_160C\ncmp [rbp+var_7C], 0\njnz short loc_162E\nloc_160C:\nmov rax, [rbp+var_88]\nmov dword ptr [rax], 0\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_48]\njmp loc_17FE\nloc_162E:\nmov rax, [rbp+var_68]\nmov edx, [rax]\nmov rax, [rbp+var_78]\nmov eax, [rax]\nadd eax, edx\nmov dword ptr [rbp+var_3C], eax\nmov dword ptr [rbp+var_3C+4], 0\nmov [rbp+var_34], 0\nmov rax, [rbp+var_3C]\nmov ecx, [rbp+var_34]\nmov rdx, rcx\nlea rsi, [rbp+var_5C]\nmov rdi, [rbp+ptr]\nmov rcx, rdx\nmov rdx, rax\ncall heapPush\nmov [rbp+var_54], 0\njmp loc_17CF\nloc_1676:\nlea rdx, [rbp+var_5C]\nmov rax, [rbp+ptr]\nmov rsi, rdx\nmov rdi, rax\ncall heapPop\nmov [rbp+var_30], rax\nmov eax, [rbp+var_28]\nand eax, 0\nor eax, edx\nmov [rbp+var_28], eax\nmov eax, dword ptr [rbp+var_30+4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_68]\nadd rdx, rax\nmov eax, [rbp+var_54]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nadd rax, rcx\nmov rax, [rax]\nmov edx, [rdx]\nmov [rax], edx\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_78]\nadd rax, rdx\nmov edx, [rbp+var_54]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_48]\nadd rdx, rcx\nmov rdx, [rdx]\nadd rdx, 4\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_54], 1\nmov eax, [rbp+var_28]\nadd eax, 1\ncmp [rbp+var_70], eax\njle short loc_176B\nmov eax, dword ptr [rbp+var_30+4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_68]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_28]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_78]\nadd rax, rcx\nmov eax, [rax]\nadd eax, edx\nmov dword ptr [rbp+var_24], eax\nmov eax, dword ptr [rbp+var_30+4]\nmov dword ptr [rbp+var_24+4], eax\nmov eax, [rbp+var_28]\nadd eax, 1\nmov [rbp+var_1C], eax\nmov rax, [rbp+var_24]\nmov ecx, [rbp+var_1C]\nmov rdx, rcx\nlea rsi, [rbp+var_5C]\nmov rdi, [rbp+ptr]\nmov rcx, rdx\nmov rdx, rax\ncall heapPush\nloc_176B:\nmov eax, [rbp+var_28]\ntest eax, eax\njnz short loc_17CF\nmov eax, dword ptr [rbp+var_30+4]\nadd eax, 1\ncmp [rbp+var_6C], eax\njle short loc_17CF\nmov eax, dword ptr [rbp+var_30+4]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_68]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_78]\nmov eax, [rax]\nadd eax, edx\nmov dword ptr [rbp+var_24], eax\nmov eax, dword ptr [rbp+var_30+4]\nadd eax, 1\nmov dword ptr [rbp+var_24+4], eax\nmov [rbp+var_1C], 0\nmov rax, [rbp+var_24]\nmov ecx, [rbp+var_1C]\nmov rdx, rcx\nlea rsi, [rbp+var_5C]\nmov rdi, [rbp+ptr]\nmov rcx, rdx\nmov rdx, rax\ncall heapPush\nloc_17CF:\nmov eax, [rbp+var_5C]\ntest eax, eax\njle short loc_17E2\nmov eax, [rbp+var_54]\ncmp eax, [rbp+var_7C]\njl loc_1676\nloc_17E2:\nmov rax, [rbp+var_88]\nmov edx, [rbp+var_54]\nmov [rax], edx\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_48]\nloc_17FE:\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njz short loc_1812\ncall ___stack_chk_fail\nloc_1812:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(_DWORD *a1, int a2, _DWORD *a3, int a4, int a5, _DWORD *a6)\n{\n int v7; // edx\n int v12; // [rsp+34h] [rbp-5Ch] BYREF\n int i; // [rsp+38h] [rbp-58h]\n int v14; // [rsp+3Ch] [rbp-54h]\n void *ptr; // [rsp+40h] [rbp-50h]\n _QWORD *v16; // [rsp+48h] [rbp-48h]\n __int64 v17; // [rsp+54h] [rbp-3Ch]\n int v18; // [rsp+5Ch] [rbp-34h]\n __int64 v19; // [rsp+60h] [rbp-30h]\n int v20; // [rsp+68h] [rbp-28h]\n __int64 v21; // [rsp+6Ch] [rbp-24h]\n int v22; // [rsp+74h] [rbp-1Ch]\n unsigned __int64 v23; // [rsp+78h] [rbp-18h]\n\n v23 = __readfsqword(0x28u);\n ptr = malloc(12LL * a4 * a2);\n v12 = 0;\n v16 = malloc(8LL * a5);\n for ( i = 0; i < a5; ++i )\n v16[i] = malloc(8uLL);\n if ( a2 && a4 && a5 )\n {\n v17 = (unsigned int)(*a1 + *a3);\n v18 = 0;\n heapPush(ptr, &v12, v17, 0LL);\n v14 = 0;\n while ( v12 > 0 && v14 < a5 )\n {\n v19 = heapPop(ptr, &v12);\n v20 = v7;\n *(_DWORD *)v16[v14] = a1[SHIDWORD(v19)];\n *(_DWORD *)(v16[v14++] + 4LL) = a3[v20];\n if ( a4 > v20 + 1 )\n {\n LODWORD(v21) = a1[SHIDWORD(v19)] + a3[v20 + 1];\n HIDWORD(v21) = HIDWORD(v19);\n v22 = v20 + 1;\n heapPush(ptr, &v12, v21, (unsigned int)(v20 + 1));\n }\n if ( !v20 && a2 > HIDWORD(v19) + 1 )\n {\n LODWORD(v21) = a1[SHIDWORD(v19) + 1] + *a3;\n HIDWORD(v21) = HIDWORD(v19) + 1;\n v22 = 0;\n heapPush(ptr, &v12, v21, 0LL);\n }\n }\n *a6 = v14;\n free(ptr);\n return v16;\n }\n else\n {\n *a6 = 0;\n free(ptr);\n return v16;\n }\n}", + "ida_strip_asm": "sub_154C:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 88h\nmov [rbp+var_68], rdi\nmov [rbp+var_6C], esi\nmov [rbp+var_78], rdx\nmov [rbp+var_70], ecx\nmov [rbp+var_7C], r8d\nmov [rbp+var_88], r9\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov eax, [rbp+var_6C]\nimul eax, [rbp+var_70]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov [rbp+var_5C], 0\nmov eax, [rbp+var_7C]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_48], rax\nmov [rbp+var_58], 0\njmp short loc_15F2\nloc_15CC:\nmov eax, [rbp+var_58]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nlea rbx, [rdx+rax]\nmov edi, 8; size\ncall _malloc\nmov [rbx], rax\nadd [rbp+var_58], 1\nloc_15F2:\nmov eax, [rbp+var_58]\ncmp eax, [rbp+var_7C]\njl short loc_15CC\ncmp [rbp+var_6C], 0\njz short loc_160C\ncmp [rbp+var_70], 0\njz short loc_160C\ncmp [rbp+var_7C], 0\njnz short loc_162E\nloc_160C:\nmov rax, [rbp+var_88]\nmov dword ptr [rax], 0\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_48]\njmp loc_17FE\nloc_162E:\nmov rax, [rbp+var_68]\nmov edx, [rax]\nmov rax, [rbp+var_78]\nmov eax, [rax]\nadd eax, edx\nmov dword ptr [rbp+var_3C], eax\nmov dword ptr [rbp+var_3C+4], 0\nmov [rbp+var_34], 0\nmov rax, [rbp+var_3C]\nmov ecx, [rbp+var_34]\nmov rdx, rcx\nlea rsi, [rbp+var_5C]\nmov rdi, [rbp+ptr]\nmov rcx, rdx\nmov rdx, rax\ncall sub_1329\nmov [rbp+var_54], 0\njmp loc_17CF\nloc_1676:\nlea rdx, [rbp+var_5C]\nmov rax, [rbp+ptr]\nmov rsi, rdx\nmov rdi, rax\ncall sub_1455\nmov [rbp+var_30], rax\nmov eax, [rbp+var_28]\nand eax, 0\nor eax, edx\nmov [rbp+var_28], eax\nmov eax, dword ptr [rbp+var_30+4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_68]\nadd rdx, rax\nmov eax, [rbp+var_54]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nadd rax, rcx\nmov rax, [rax]\nmov edx, [rdx]\nmov [rax], edx\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_78]\nadd rax, rdx\nmov edx, [rbp+var_54]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_48]\nadd rdx, rcx\nmov rdx, [rdx]\nadd rdx, 4\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_54], 1\nmov eax, [rbp+var_28]\nadd eax, 1\ncmp [rbp+var_70], eax\njle short loc_176B\nmov eax, dword ptr [rbp+var_30+4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_68]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_28]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_78]\nadd rax, rcx\nmov eax, [rax]\nadd eax, edx\nmov dword ptr [rbp+var_24], eax\nmov eax, dword ptr [rbp+var_30+4]\nmov dword ptr [rbp+var_24+4], eax\nmov eax, [rbp+var_28]\nadd eax, 1\nmov [rbp+var_1C], eax\nmov rax, [rbp+var_24]\nmov ecx, [rbp+var_1C]\nmov rdx, rcx\nlea rsi, [rbp+var_5C]\nmov rdi, [rbp+ptr]\nmov rcx, rdx\nmov rdx, rax\ncall sub_1329\nloc_176B:\nmov eax, [rbp+var_28]\ntest eax, eax\njnz short loc_17CF\nmov eax, dword ptr [rbp+var_30+4]\nadd eax, 1\ncmp [rbp+var_6C], eax\njle short loc_17CF\nmov eax, dword ptr [rbp+var_30+4]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_68]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_78]\nmov eax, [rax]\nadd eax, edx\nmov dword ptr [rbp+var_24], eax\nmov eax, dword ptr [rbp+var_30+4]\nadd eax, 1\nmov dword ptr [rbp+var_24+4], eax\nmov [rbp+var_1C], 0\nmov rax, [rbp+var_24]\nmov ecx, [rbp+var_1C]\nmov rdx, rcx\nlea rsi, [rbp+var_5C]\nmov rdi, [rbp+ptr]\nmov rcx, rdx\nmov rdx, rax\ncall sub_1329\nloc_17CF:\nmov eax, [rbp+var_5C]\ntest eax, eax\njle short loc_17E2\nmov eax, [rbp+var_54]\ncmp eax, [rbp+var_7C]\njl loc_1676\nloc_17E2:\nmov rax, [rbp+var_88]\nmov edx, [rbp+var_54]\nmov [rax], edx\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_48]\nloc_17FE:\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njz short loc_1812\ncall ___stack_chk_fail\nloc_1812:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_154C(_DWORD *a1, int a2, _DWORD *a3, int a4, int a5, _DWORD *a6)\n{\n int v7; // edx\n int v12; // [rsp+34h] [rbp-5Ch] BYREF\n int i; // [rsp+38h] [rbp-58h]\n int v14; // [rsp+3Ch] [rbp-54h]\n void *ptr; // [rsp+40h] [rbp-50h]\n _QWORD *v16; // [rsp+48h] [rbp-48h]\n __int64 v17; // [rsp+54h] [rbp-3Ch]\n int v18; // [rsp+5Ch] [rbp-34h]\n __int64 v19; // [rsp+60h] [rbp-30h]\n int v20; // [rsp+68h] [rbp-28h]\n __int64 v21; // [rsp+6Ch] [rbp-24h]\n int v22; // [rsp+74h] [rbp-1Ch]\n unsigned __int64 v23; // [rsp+78h] [rbp-18h]\n\n v23 = __readfsqword(0x28u);\n ptr = malloc(12LL * a4 * a2);\n v12 = 0;\n v16 = malloc(8LL * a5);\n for ( i = 0; i < a5; ++i )\n v16[i] = malloc(8uLL);\n if ( a2 && a4 && a5 )\n {\n v17 = (unsigned int)(*a1 + *a3);\n v18 = 0;\n sub_1329(ptr, &v12, v17, 0LL);\n v14 = 0;\n while ( v12 > 0 && v14 < a5 )\n {\n v19 = sub_1455(ptr, &v12);\n v20 = v7;\n *(_DWORD *)v16[v14] = a1[SHIDWORD(v19)];\n *(_DWORD *)(v16[v14++] + 4LL) = a3[v20];\n if ( a4 > v20 + 1 )\n {\n LODWORD(v21) = a1[SHIDWORD(v19)] + a3[v20 + 1];\n HIDWORD(v21) = HIDWORD(v19);\n v22 = v20 + 1;\n sub_1329(ptr, &v12, v21, (unsigned int)(v20 + 1));\n }\n if ( !v20 && a2 > HIDWORD(v19) + 1 )\n {\n LODWORD(v21) = a1[SHIDWORD(v19) + 1] + *a3;\n HIDWORD(v21) = HIDWORD(v19) + 1;\n v22 = 0;\n sub_1329(ptr, &v12, v21, 0LL);\n }\n }\n *a6 = v14;\n free(ptr);\n return v16;\n }\n else\n {\n *a6 = 0;\n free(ptr);\n return v16;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_154C(uint32_t *a1, int a2, uint32_t *a3, int a4, int a5,\n uint32_t *a6) {\n int v7;\n int v12;\n int i;\n int v14;\n void *ptr;\n uint64_t *v16;\n long long v17;\n int v18;\n long long v19;\n int v20;\n long long v21;\n int v22;\n unsigned long long v23;\n v23 = __readfsqword(40u);\n ptr = malloc(12LL * a4 * a2);\n v12 = 0;\n v16 = malloc(8LL * a5);\n for (i = 0; i < a5; ++i) v16[i] = malloc(8uLL);\n if (a2 && a4 && a5) {\n v17 = (unsigned int)(*a1 + *a3);\n v18 = 0;\n sub_1329(ptr, &v12, v17, 0LL);\n v14 = 0;\n while (v12 > 0 && v14 < a5) {\n v19 = sub_1455(ptr, &v12);\n v20 = v7;\n *(uint32_t *)v16[v14] = a1[SHIDWORD(v19)];\n *(uint32_t *)(v16[v14++] + 4LL) = a3[v20];\n if (a4 > v20 + 1) {\n LODWORD(v21) = a1[SHIDWORD(v19)] + a3[v20 + 1];\n HIDWORD(v21) = HIDWORD(v19);\n v22 = v20 + 1;\n sub_1329(ptr, &v12, v21, (unsigned int)(v20 + 1));\n }\n if (!v20 && a2 > HIDWORD(v19) + 1) {\n LODWORD(v21) = a1[SHIDWORD(v19) + 1] + *a3;\n HIDWORD(v21) = HIDWORD(v19) + 1;\n v22 = 0;\n sub_1329(ptr, &v12, v21, 0LL);\n }\n }\n *a6 = v14;\n free(ptr);\n return v16;\n } else {\n *a6 = 0;\n free(ptr);\n return v16;\n }\n}", + "ida_pseudo_norm": "uint64_t *func0(uint32_t *a1, int a2, uint32_t *a3, int a4, int a5,\n uint32_t *a6) {\n int v7;\n int v12;\n int i;\n int v14;\n void *ptr;\n uint64_t *v16;\n long long v17;\n int v18;\n long long v19;\n int v20;\n long long v21;\n int v22;\n unsigned long long v23;\n v23 = __readfsqword(40u);\n ptr = malloc(12LL * a4 * a2);\n v12 = 0;\n v16 = malloc(8LL * a5);\n for (i = 0; i < a5; ++i) v16[i] = malloc(8uLL);\n if (a2 && a4 && a5) {\n v17 = (unsigned int)(*a1 + *a3);\n v18 = 0;\n heapPush(ptr, &v12, v17, 0LL);\n v14 = 0;\n while (v12 > 0 && v14 < a5) {\n v19 = heapPop(ptr, &v12);\n v20 = v7;\n *(uint32_t *)v16[v14] = a1[SHIDWORD(v19)];\n *(uint32_t *)(v16[v14++] + 4LL) = a3[v20];\n if (a4 > v20 + 1) {\n LODWORD(v21) = a1[SHIDWORD(v19)] + a3[v20 + 1];\n HIDWORD(v21) = HIDWORD(v19);\n v22 = v20 + 1;\n heapPush(ptr, &v12, v21, (unsigned int)(v20 + 1));\n }\n if (!v20 && a2 > HIDWORD(v19) + 1) {\n LODWORD(v21) = a1[SHIDWORD(v19) + 1] + *a3;\n HIDWORD(v21) = HIDWORD(v19) + 1;\n v22 = 0;\n heapPush(ptr, &v12, v21, 0LL);\n }\n }\n *a6 = v14;\n free(ptr);\n return v16;\n } else {\n *a6 = 0;\n free(ptr);\n return v16;\n }\n}" + }, + { + "index": 408, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int sum;\n\n int index1;\n\n int index2;\n\n} HeapNode;\n\n\n\nvoid swap(HeapNode *a, HeapNode *b) {\n\n HeapNode temp = *a;\n\n *a = *b;\n\n *b = temp;\n\n}\n\n\n\nvoid heapify(HeapNode heap[], int n, int i) {\n\n int smallest = i;\n\n int l = 2*i + 1;\n\n int r = 2*i + 2;\n\n\n\n if (l < n && heap[l].sum < heap[smallest].sum)\n\n smallest = l;\n\n\n\n if (r < n && heap[r].sum < heap[smallest].sum)\n\n smallest = r;\n\n\n\n if (smallest != i) {\n\n swap(&heap[i], &heap[smallest]);\n\n heapify(heap, n, smallest);\n\n }\n\n}\n\n\n\nvoid heapPush(HeapNode heap[], int *size, HeapNode node) {\n\n int i = *size;\n\n heap[i] = node;\n\n (*size)++;\n\n while (i != 0 && heap[(i-1)/2].sum > heap[i].sum) {\n\n swap(&heap[(i-1)/2], &heap[i]);\n\n i = (i-1)/2;\n\n }\n\n}\n\n\n\nHeapNode heapPop(HeapNode heap[], int *size) {\n\n if (*size <= 0) {\n\n HeapNode invalid = {-1, -1, -1};\n\n return invalid;\n\n }\n\n if (*size == 1) {\n\n (*size)--;\n\n return heap[0];\n\n }\n\n HeapNode root = heap[0];\n\n heap[0] = heap[*size - 1];\n\n (*size)--;\n\n heapify(heap, *size, 0);\n\n return root;\n\n}\n\n\n\n", + "func": "int **func0(int nums1[], int nums1Size, int nums2[], int nums2Size, int k,\n int *returnSize) {\n HeapNode *heap =\n (HeapNode *)malloc(sizeof(HeapNode) * (nums1Size * nums2Size));\n int heapSize = 0;\n int **result = (int **)malloc(sizeof(int *) * k);\n for (int i = 0; i < k; i++) {\n result[i] = (int *)malloc(sizeof(int) * 2);\n }\n if (nums1Size == 0 || nums2Size == 0 || k == 0) {\n *returnSize = 0;\n free(heap);\n return result;\n }\n heapPush(heap, &heapSize, (HeapNode){nums1[0] + nums2[0], 0, 0});\n int count = 0;\n while (heapSize > 0 && count < k) {\n HeapNode node = heapPop(heap, &heapSize);\n result[count][0] = nums1[node.index1];\n result[count][1] = nums2[node.index2];\n count++;\n if (node.index2 + 1 < nums2Size) {\n heapPush(heap, &heapSize,\n (HeapNode){nums1[node.index1] + nums2[node.index2 + 1],\n node.index1, node.index2 + 1});\n }\n if (node.index2 == 0 && node.index1 + 1 < nums1Size) {\n heapPush(\n heap, &heapSize,\n (HeapNode){nums1[node.index1 + 1] + nums2[0], node.index1 + 1, 0});\n }\n }\n *returnSize = count;\n free(heap);\n return result;\n}", + "test": "int main() {\n\n int returnSize;\n\n int **result;\n\n\n\n result = func0((int[]){1, 3, 7}, 3, (int[]){2, 4, 6}, 3, 2, &returnSize);\n\n assert(returnSize == 2 && result[0][0] == 1 && result[0][1] == 2 && result[1][0] == 1 && result[1][1] == 4);\n\n\n\n result = func0((int[]){1, 3, 7}, 3, (int[]){2, 4, 6}, 3, 1, &returnSize);\n\n assert(returnSize == 1 && result[0][0] == 1 && result[0][1] == 2);\n\n\n\n result = func0((int[]){1, 3, 7}, 3, (int[]){2, 4, 6}, 3, 7, &returnSize);\n\n assert(returnSize == 7 && result[0][0] == 1 && result[0][1] == 2 && result[1][0] == 1 && result[1][1] == 4);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x68,%rsp\nmov %rdi,0x10(%rsp)\nmov %esi,0x24(%rsp)\nmov %rdx,%r15\nmov %ecx,0x18(%rsp)\nmov %r8d,%ebx\nmov %r8d,0x1c(%rsp)\nmov %r9,0x28(%rsp)\nmov %fs:0x28,%rax\nmov %rax,0x58(%rsp)\nxor %eax,%eax\nmov %esi,%eax\nimul %ecx,%eax\ncltq\nlea (%rax,%rax,2),%rdi\nshl $0x2,%rdi\ncallq 10b0 \nmov %rax,(%rsp)\nmovl $0x0,0x30(%rsp)\nmovslq %ebx,%rdi\nshl $0x3,%rdi\ncallq 10b0 \nmov %rax,%r14\ntest %ebx,%ebx\njle 15a9 \nmov %ebx,%eax\nmov %r14,%rbx\nlea -0x1(%rax),%eax\nlea 0x8(%r14,%rax,8),%rbp\nmov $0x8,%edi\ncallq 10b0 \nmov %rax,(%rbx)\nadd $0x8,%rbx\ncmp %rbp,%rbx\njne 13f3 \ncmpl $0x0,0x24(%rsp)\nje 146d \ncmpl $0x0,0x18(%rsp)\nje 146d \nmov (%r15),%eax\nmov 0x10(%rsp),%rsi\nadd (%rsi),%eax\nmov %eax,0x34(%rsp)\nmovl $0x0,0x38(%rsp)\nmovl $0x0,0x3c(%rsp)\nlea 0x30(%rsp),%rsi\nmov 0x34(%rsp),%rdx\nmov $0x0,%ecx\nmov (%rsp),%rdi\ncallq 1270 \ncmpl $0x0,0x30(%rsp)\njle 159f \nmov $0x1,%r12d\nlea 0x30(%rsp),%rax\nmov %rax,0x8(%rsp)\njmpq 14ed \nmov 0x28(%rsp),%rax\nmovl $0x0,(%rax)\nmov (%rsp),%rdi\ncallq 1080 \nmov 0x58(%rsp),%rax\nxor %fs:0x28,%rax\njne 161b \nmov %r14,%rax\nadd $0x68,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmov (%rdx),%eax\nadd 0x4(%r15,%rsi,1),%eax\nmov %eax,0x4c(%rsp)\nmov %ebx,0x50(%rsp)\nmov %ecx,0x54(%rsp)\nmov %ecx,%ecx\nmov 0x4c(%rsp),%rdx\nmov 0x8(%rsp),%rsi\nmov (%rsp),%rdi\ncallq 1270 \njmp 1550 \ncmpl $0x0,0x30(%rsp)\nsetg %dl\ncmp %r12d,0x1c(%rsp)\nsetg %al\nadd $0x1,%r12\ntest %al,%dl\nje 1602 \nmov 0x8(%rsp),%rsi\nmov (%rsp),%rdi\ncallq 12d6 \nmov %rax,%rbx\nmov %rdx,%rbp\nmov %rax,0x40(%rsp)\nmov %edx,0x48(%rsp)\nshr $0x20,%rbx\nmovslq %ebx,%r13\nshl $0x2,%r13\nmov 0x10(%rsp),%rax\nlea (%rax,%r13,1),%rdx\nmov -0x8(%r14,%r12,8),%rax\nmov (%rdx),%ecx\nmov %ecx,(%rax)\nmovslq %ebp,%rax\nlea 0x0(,%rax,4),%rsi\nmov -0x8(%r14,%r12,8),%rcx\nmov (%r15,%rax,4),%eax\nmov %eax,0x4(%rcx)\nmov %r12d,0x20(%rsp)\nlea 0x1(%rbp),%ecx\ncmp 0x18(%rsp),%ecx\njl 14a7 \ntest %ebp,%ebp\njne 14d1 \nadd $0x1,%ebx\ncmp 0x24(%rsp),%ebx\njge 14d1 \nmov (%r15),%eax\nmov 0x10(%rsp),%rsi\nadd 0x4(%rsi,%r13,1),%eax\nmov %eax,0x4c(%rsp)\nmov %ebx,0x50(%rsp)\nmovl $0x0,0x54(%rsp)\nmov 0x4c(%rsp),%rdx\nmov $0x0,%ecx\nmov 0x8(%rsp),%rsi\nmov (%rsp),%rdi\ncallq 1270 \njmpq 14d1 \nmovl $0x0,0x20(%rsp)\njmp 1602 \ncmpl $0x0,0x18(%rsp)\nsete %dl\ncmpl $0x0,0x1c(%rsp)\nsete %al\nor %al,%dl\njne 146d \ncmpl $0x0,0x24(%rsp)\nje 146d \nmov 0x10(%rsp),%rax\nmov (%rax),%eax\nadd (%r15),%eax\nmov %eax,0x34(%rsp)\nmovl $0x0,0x38(%rsp)\nlea 0x30(%rsp),%rsi\nmov 0x34(%rsp),%rdx\nmov $0x0,%ecx\nmov (%rsp),%rdi\ncallq 1270 \nmovl $0x0,0x20(%rsp)\nmov 0x28(%rsp),%rax\nmov 0x20(%rsp),%esi\nmov %esi,(%rax)\nmov (%rsp),%rdi\ncallq 1080 \njmpq 1481 \ncallq 1090 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 68h\nmov [rsp+98h+var_90], rdi\nmov [rsp+98h+var_78], esi\nmov r15, rdx\nmov [rsp+98h+var_88], ecx\nmov ebx, r8d\nmov [rsp+98h+var_84], r8d\nmov r12, r9\nmov rax, fs:28h\nmov [rsp+98h+var_40], rax\nxor eax, eax\nmov eax, esi\nimul eax, ecx\ncdqe\nlea rdi, [rax+rax*2]\nshl rdi, 2; size\ncall _malloc\nmov r13, rax\nmov [rsp+98h+var_68], 0\nmovsxd rbp, ebx\nshl rbp, 3\nmov rdi, rbp; size\ncall _malloc\nmov r14, rax\ntest ebx, ebx\njle loc_15BE\nmov rbx, rax\nadd rbp, rax\nloc_13EC:\nmov edi, 8; size\ncall _malloc\nmov [rbx], rax\nadd rbx, 8\ncmp rbx, rbp\njnz short loc_13EC\ncmp [rsp+98h+var_78], 0\njz short loc_146F\ncmp [rsp+98h+var_88], 0\njz short loc_146F\nmov rbx, r15\nmov eax, [r15]\nmov [rsp+98h+var_74], eax\nmov rdi, [rsp+98h+var_90]\nadd eax, [rdi]\nmov dword ptr [rsp+98h+var_64], eax\nmov dword ptr [rsp+98h+var_64+4], 0\nmov [rsp+98h+var_5C], 0\nlea rsi, [rsp+98h+var_68]\nmov rdx, [rsp+98h+var_64]\nmov ecx, 0\nmov rdi, r13\ncall heapPush\ncmp [rsp+98h+var_68], 0\njle loc_15B7\nmov ebp, 1\nlea r15, [rsp+98h+var_68]\nmov [rsp+98h+var_70], r12\nmov [rsp+98h+var_98], r15\nmov r15, rbx\njmp short loc_14E8\nloc_146F:\nmov dword ptr [r12], 0\nmov rdi, r13; ptr\ncall _free\nloc_147F:\nmov rax, [rsp+98h+var_40]\nsub rax, fs:28h\njnz loc_1615\nmov rax, r14\nadd rsp, 68h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14A5:\nadd esi, [r15+rdi+4]\nmov dword ptr [rsp+98h+var_4C], esi\nmov dword ptr [rsp+98h+var_4C+4], r12d\nmov [rsp+98h+var_44], ecx\nmov ecx, ecx\nmov rdx, [rsp+98h+var_4C]\nmov rsi, [rsp+98h+var_98]\nmov rdi, r13\ncall heapPush\njmp short loc_154A\nloc_14CC:\nlea rax, [rbp+1]\ncmp [rsp+98h+var_68], 0\njle loc_15A1\ncmp [rsp+98h+var_84], ebp\njle loc_15A1\nmov rbp, rax\nloc_14E8:\nmov rsi, [rsp+98h+var_98]\nmov rdi, r13\ncall heapPop\nmov rbx, rdx\nmov rcx, rax\nshr rcx, 20h\nmov r12d, ecx\nmov [rsp+98h+var_58], rax\nmov [rsp+98h+var_50], edx\nmovsxd rdx, ecx\nlea rax, ds:0[rdx*4]\nmov [rsp+98h+var_80], rax\nmov rax, [r14+rbp*8-8]\nmov rsi, [rsp+98h+var_90]\nmov esi, [rsi+rdx*4]\nmov [rax], esi\nmovsxd rdx, ebx\nlea rdi, ds:0[rdx*4]\nmov edx, [r15+rdx*4]\nmov [rax+4], edx\nlea ecx, [rbx+1]\nmov eax, [rsp+98h+var_88]\ncmp ecx, eax\njl loc_14A5\nloc_154A:\ntest ebx, ebx\njnz loc_14CC\nadd r12d, 1\nmov eax, [rsp+98h+var_78]\ncmp r12d, eax\njge loc_14CC\nmov rdi, [rsp+98h+var_90]\nmov rcx, [rsp+98h+var_80]\nmov eax, [rsp+98h+var_74]\nadd eax, [rdi+rcx+4]\nmov dword ptr [rsp+98h+var_4C], eax\nmov dword ptr [rsp+98h+var_4C+4], r12d\nmov [rsp+98h+var_44], 0\nmov rdx, [rsp+98h+var_4C]\nmov ecx, 0\nmov rsi, [rsp+98h+var_98]\nmov rdi, r13\ncall heapPush\njmp loc_14CC\nloc_15A1:\nmov r12, [rsp+98h+var_70]\nloc_15A6:\nmov [r12], ebp\nmov rdi, r13; ptr\ncall _free\njmp loc_147F\nloc_15B7:\nmov ebp, 0\njmp short loc_15A6\nloc_15BE:\ncmp [rsp+98h+var_88], 0\nsetz al\ncmp [rsp+98h+var_84], 0\nsetz dl\nor al, dl\njnz loc_146F\ncmp [rsp+98h+var_78], 0\njz loc_146F\nmov rax, [rsp+98h+var_90]\nmov eax, [rax]\nadd eax, [r15]\nmov dword ptr [rsp+98h+var_64], eax\nmov dword ptr [rsp+98h+var_64+4], 0\nlea rsi, [rsp+98h+var_68]\nmov rdx, [rsp+98h+var_64]\nmov ecx, 0\nmov rdi, r13\ncall heapPush\nmov ebp, 0\njmp short loc_15A6\nloc_1615:\ncall ___stack_chk_fail", + "ida_pseudo": "_QWORD *__fastcall func0(_DWORD *a1, int a2, int *a3, int a4, int a5, _DWORD *a6)\n{\n void *v9; // r13\n size_t v10; // rbp\n _QWORD *v11; // rax\n _QWORD *v12; // r14\n void **v13; // rbx\n void **v14; // rbp\n __int64 v15; // rbp\n __int64 i; // rax\n int v17; // edx\n int v19; // ebx\n int v20; // r12d\n __int64 v21; // rdx\n _DWORD *v22; // rax\n int v23; // esi\n __int64 v24; // rdi\n int v25; // r12d\n __int64 v29; // [rsp+18h] [rbp-80h]\n int v31; // [rsp+24h] [rbp-74h]\n _DWORD *v32; // [rsp+28h] [rbp-70h]\n int v33; // [rsp+30h] [rbp-68h] BYREF\n __int64 v34; // [rsp+34h] [rbp-64h]\n int v35; // [rsp+3Ch] [rbp-5Ch]\n __int64 v36; // [rsp+40h] [rbp-58h]\n int v37; // [rsp+48h] [rbp-50h]\n __int64 v38; // [rsp+4Ch] [rbp-4Ch]\n int v39; // [rsp+54h] [rbp-44h]\n unsigned __int64 v40; // [rsp+58h] [rbp-40h]\n\n v40 = __readfsqword(0x28u);\n v9 = malloc(12LL * a4 * a2);\n v33 = 0;\n v10 = a5;\n v11 = malloc(v10 * 8);\n v12 = v11;\n if ( a5 <= 0 )\n {\n if ( a5 != 0 && a4 != 0 && a2 )\n {\n v34 = (unsigned int)(*a3 + *a1);\n heapPush(v9, &v33, v34, 0LL);\n LODWORD(v15) = 0;\nLABEL_19:\n *a6 = v15;\n free(v9);\n return v12;\n }\n }\n else\n {\n v13 = (void **)v11;\n v14 = (void **)&v11[v10];\n do\n *v13++ = malloc(8uLL);\n while ( v13 != v14 );\n if ( a2 && a4 )\n {\n v31 = *a3;\n v34 = (unsigned int)(*a1 + *a3);\n v35 = 0;\n heapPush(v9, &v33, v34, 0LL);\n if ( v33 <= 0 )\n {\n LODWORD(v15) = 0;\n }\n else\n {\n v15 = 1LL;\n v32 = a6;\n for ( i = heapPop(v9, &v33); ; i = heapPop(v9, &v33) )\n {\n v19 = v17;\n v20 = HIDWORD(i);\n v36 = i;\n v37 = v17;\n v21 = SHIDWORD(i);\n v29 = SHIDWORD(i);\n v22 = (_DWORD *)v12[v15 - 1];\n v23 = a1[v21];\n *v22 = v23;\n v24 = v19;\n v22[1] = a3[v24];\n if ( v19 + 1 < a4 )\n {\n LODWORD(v38) = a3[v24 + 1] + v23;\n HIDWORD(v38) = v20;\n v39 = v19 + 1;\n heapPush(v9, &v33, v38, (unsigned int)(v19 + 1));\n }\n if ( !v19 )\n {\n v25 = v20 + 1;\n if ( v25 < a2 )\n {\n LODWORD(v38) = a1[v29 + 1] + v31;\n HIDWORD(v38) = v25;\n v39 = 0;\n heapPush(v9, &v33, v38, 0LL);\n }\n }\n if ( v33 <= 0 || a5 <= (int)v15 )\n break;\n ++v15;\n }\n a6 = v32;\n }\n goto LABEL_19;\n }\n }\n *a6 = 0;\n free(v9);\n return v12;\n}", + "ida_strip_asm": "sub_1370:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 68h\nmov [rsp+98h+var_90], rdi\nmov [rsp+98h+var_78], esi\nmov r15, rdx\nmov [rsp+98h+var_88], ecx\nmov ebx, r8d\nmov [rsp+98h+var_84], r8d\nmov r12, r9\nmov rax, fs:28h\nmov [rsp+98h+var_40], rax\nxor eax, eax\nmov eax, esi\nimul eax, ecx\ncdqe\nlea rdi, [rax+rax*2]\nshl rdi, 2; size\ncall _malloc\nmov r13, rax\nmov [rsp+98h+var_68], 0\nmovsxd rbp, ebx\nshl rbp, 3\nmov rdi, rbp; size\ncall _malloc\nmov r14, rax\ntest ebx, ebx\njle loc_15BE\nmov rbx, rax\nadd rbp, rax\nloc_13EC:\nmov edi, 8; size\ncall _malloc\nmov [rbx], rax\nadd rbx, 8\ncmp rbx, rbp\njnz short loc_13EC\ncmp [rsp+98h+var_78], 0\njz short loc_146F\ncmp [rsp+98h+var_88], 0\njz short loc_146F\nmov rbx, r15\nmov eax, [r15]\nmov [rsp+98h+var_74], eax\nmov rdi, [rsp+98h+var_90]\nadd eax, [rdi]\nmov dword ptr [rsp+98h+var_64], eax\nmov dword ptr [rsp+98h+var_64+4], 0\nmov [rsp+98h+var_5C], 0\nlea rsi, [rsp+98h+var_68]\nmov rdx, [rsp+98h+var_64]\nmov ecx, 0\nmov rdi, r13\ncall sub_1270\ncmp [rsp+98h+var_68], 0\njle loc_15B7\nmov ebp, 1\nlea r15, [rsp+98h+var_68]\nmov [rsp+98h+var_70], r12\nmov [rsp+98h+var_98], r15\nmov r15, rbx\njmp short loc_14E8\nloc_146F:\nmov dword ptr [r12], 0\nmov rdi, r13; ptr\ncall _free\nloc_147F:\nmov rax, [rsp+98h+var_40]\nsub rax, fs:28h\njnz loc_1615\nmov rax, r14\nadd rsp, 68h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14A5:\nadd esi, [r15+rdi+4]\nmov dword ptr [rsp+98h+var_4C], esi\nmov dword ptr [rsp+98h+var_4C+4], r12d\nmov [rsp+98h+var_44], ecx\nmov ecx, ecx\nmov rdx, [rsp+98h+var_4C]\nmov rsi, [rsp+98h+var_98]\nmov rdi, r13\ncall sub_1270\njmp short loc_154A\nloc_14CC:\nlea rax, [rbp+1]\ncmp [rsp+98h+var_68], 0\njle loc_15A1\ncmp [rsp+98h+var_84], ebp\njle loc_15A1\nmov rbp, rax\nloc_14E8:\nmov rsi, [rsp+98h+var_98]\nmov rdi, r13\ncall sub_12D6\nmov rbx, rdx\nmov rcx, rax\nshr rcx, 20h\nmov r12d, ecx\nmov [rsp+98h+var_58], rax\nmov [rsp+98h+var_50], edx\nmovsxd rdx, ecx\nlea rax, ds:0[rdx*4]\nmov [rsp+98h+var_80], rax\nmov rax, [r14+rbp*8-8]\nmov rsi, [rsp+98h+var_90]\nmov esi, [rsi+rdx*4]\nmov [rax], esi\nmovsxd rdx, ebx\nlea rdi, ds:0[rdx*4]\nmov edx, [r15+rdx*4]\nmov [rax+4], edx\nlea ecx, [rbx+1]\nmov eax, [rsp+98h+var_88]\ncmp ecx, eax\njl loc_14A5\nloc_154A:\ntest ebx, ebx\njnz loc_14CC\nadd r12d, 1\nmov eax, [rsp+98h+var_78]\ncmp r12d, eax\njge loc_14CC\nmov rdi, [rsp+98h+var_90]\nmov rcx, [rsp+98h+var_80]\nmov eax, [rsp+98h+var_74]\nadd eax, [rdi+rcx+4]\nmov dword ptr [rsp+98h+var_4C], eax\nmov dword ptr [rsp+98h+var_4C+4], r12d\nmov [rsp+98h+var_44], 0\nmov rdx, [rsp+98h+var_4C]\nmov ecx, 0\nmov rsi, [rsp+98h+var_98]\nmov rdi, r13\ncall sub_1270\njmp loc_14CC\nloc_15A1:\nmov r12, [rsp+98h+var_70]\nloc_15A6:\nmov [r12], ebp\nmov rdi, r13; ptr\ncall _free\njmp loc_147F\nloc_15B7:\nmov ebp, 0\njmp short loc_15A6\nloc_15BE:\ncmp [rsp+98h+var_88], 0\nsetz al\ncmp [rsp+98h+var_84], 0\nsetz dl\nor al, dl\njnz loc_146F\ncmp [rsp+98h+var_78], 0\njz loc_146F\nmov rax, [rsp+98h+var_90]\nmov eax, [rax]\nadd eax, [r15]\nmov dword ptr [rsp+98h+var_64], eax\nmov dword ptr [rsp+98h+var_64+4], 0\nlea rsi, [rsp+98h+var_68]\nmov rdx, [rsp+98h+var_64]\nmov ecx, 0\nmov rdi, r13\ncall sub_1270\nmov ebp, 0\njmp short loc_15A6\nloc_1615:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1370(_DWORD *a1, int a2, int *a3, int a4, int a5, _DWORD *a6)\n{\n void *v9; // r13\n size_t v10; // rbp\n _QWORD *v11; // rax\n _QWORD *v12; // r14\n void **v13; // rbx\n void **v14; // rbp\n __int64 v15; // rbp\n __int64 i; // rax\n int v17; // edx\n int v19; // ebx\n int v20; // r12d\n __int64 v21; // rdx\n _DWORD *v22; // rax\n int v23; // esi\n __int64 v24; // rdi\n int v25; // r12d\n __int64 v29; // [rsp+18h] [rbp-80h]\n int v31; // [rsp+24h] [rbp-74h]\n _DWORD *v32; // [rsp+28h] [rbp-70h]\n int v33; // [rsp+30h] [rbp-68h] BYREF\n __int64 v34; // [rsp+34h] [rbp-64h]\n int v35; // [rsp+3Ch] [rbp-5Ch]\n __int64 v36; // [rsp+40h] [rbp-58h]\n int v37; // [rsp+48h] [rbp-50h]\n __int64 v38; // [rsp+4Ch] [rbp-4Ch]\n int v39; // [rsp+54h] [rbp-44h]\n unsigned __int64 v40; // [rsp+58h] [rbp-40h]\n\n v40 = __readfsqword(0x28u);\n v9 = malloc(12LL * a4 * a2);\n v33 = 0;\n v10 = a5;\n v11 = malloc(v10 * 8);\n v12 = v11;\n if ( a5 <= 0 )\n {\n if ( a5 != 0 && a4 != 0 && a2 )\n {\n v34 = (unsigned int)(*a3 + *a1);\n sub_1270(v9, &v33, v34, 0LL);\n LODWORD(v15) = 0;\nLABEL_19:\n *a6 = v15;\n free(v9);\n return v12;\n }\n }\n else\n {\n v13 = (void **)v11;\n v14 = (void **)&v11[v10];\n do\n *v13++ = malloc(8uLL);\n while ( v13 != v14 );\n if ( a2 && a4 )\n {\n v31 = *a3;\n v34 = (unsigned int)(*a1 + *a3);\n v35 = 0;\n sub_1270(v9, &v33, v34, 0LL);\n if ( v33 <= 0 )\n {\n LODWORD(v15) = 0;\n }\n else\n {\n v15 = 1LL;\n v32 = a6;\n for ( i = sub_12D6(v9, &v33); ; i = sub_12D6(v9, &v33) )\n {\n v19 = v17;\n v20 = HIDWORD(i);\n v36 = i;\n v37 = v17;\n v21 = SHIDWORD(i);\n v29 = SHIDWORD(i);\n v22 = (_DWORD *)v12[v15 - 1];\n v23 = a1[v21];\n *v22 = v23;\n v24 = v19;\n v22[1] = a3[v24];\n if ( v19 + 1 < a4 )\n {\n LODWORD(v38) = a3[v24 + 1] + v23;\n HIDWORD(v38) = v20;\n v39 = v19 + 1;\n sub_1270(v9, &v33, v38, (unsigned int)(v19 + 1));\n }\n if ( !v19 )\n {\n v25 = v20 + 1;\n if ( v25 < a2 )\n {\n LODWORD(v38) = a1[v29 + 1] + v31;\n HIDWORD(v38) = v25;\n v39 = 0;\n sub_1270(v9, &v33, v38, 0LL);\n }\n }\n if ( v33 <= 0 || a5 <= (int)v15 )\n break;\n ++v15;\n }\n a6 = v32;\n }\n goto LABEL_19;\n }\n }\n *a6 = 0;\n free(v9);\n return v12;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1370(uint32_t *a1, int a2, int *a3, int a4, int a5,\n uint32_t *a6) {\n void *v9;\n unsigned int v10;\n uint64_t *v11;\n uint64_t *v12;\n void **v13;\n void **v14;\n long long v15;\n long long i;\n int v17;\n int v19;\n int v20;\n long long v21;\n uint32_t *v22;\n int v23;\n long long v24;\n int v25;\n long long v29;\n int v31;\n uint32_t *v32;\n int v33;\n long long v34;\n int v35;\n long long v36;\n int v37;\n long long v38;\n int v39;\n unsigned long long v40;\n v40 = __readfsqword(40u);\n v9 = malloc(12LL * a4 * a2);\n v33 = 0;\n v10 = a5;\n v11 = malloc(v10 * 8);\n v12 = v11;\n if (a5 <= 0) {\n if (a5 != 0 && a4 != 0 && a2) {\n v34 = (unsigned int)(*a3 + *a1);\n sub_1270(v9, &v33, v34, 0LL);\n LODWORD(v15) = 0;\n LABEL_19:\n *a6 = v15;\n free(v9);\n return v12;\n }\n } else {\n v13 = (void **)v11;\n v14 = (void **)&v11[v10];\n do\n *v13++ = malloc(8uLL);\n while (v13 != v14);\n if (a2 && a4) {\n v31 = *a3;\n v34 = (unsigned int)(*a1 + *a3);\n v35 = 0;\n sub_1270(v9, &v33, v34, 0LL);\n if (v33 <= 0) {\n LODWORD(v15) = 0;\n } else {\n v15 = 1LL;\n v32 = a6;\n for (i = sub_12D6(v9, &v33);; i = sub_12D6(v9, &v33)) {\n v19 = v17;\n v20 = HIDWORD(i);\n v36 = i;\n v37 = v17;\n v21 = SHIDWORD(i);\n v29 = SHIDWORD(i);\n v22 = (uint32_t *)v12[v15 - 1];\n v23 = a1[v21];\n *v22 = v23;\n v24 = v19;\n v22[1] = a3[v24];\n if (v19 + 1 < a4) {\n LODWORD(v38) = a3[v24 + 1] + v23;\n HIDWORD(v38) = v20;\n v39 = v19 + 1;\n sub_1270(v9, &v33, v38, (unsigned int)(v19 + 1));\n }\n if (!v19) {\n v25 = v20 + 1;\n if (v25 < a2) {\n LODWORD(v38) = a1[v29 + 1] + v31;\n HIDWORD(v38) = v25;\n v39 = 0;\n sub_1270(v9, &v33, v38, 0LL);\n }\n }\n if (v33 <= 0 || a5 <= (int)v15) break;\n ++v15;\n }\n a6 = v32;\n }\n goto LABEL_19;\n }\n }\n *a6 = 0;\n free(v9);\n return v12;\n}", + "ida_pseudo_norm": "uint64_t *func0(uint32_t *a1, int a2, int *a3, int a4, int a5, uint32_t *a6) {\n void *v9;\n unsigned int v10;\n uint64_t *v11;\n uint64_t *v12;\n void **v13;\n void **v14;\n long long v15;\n long long i;\n int v17;\n int v19;\n int v20;\n long long v21;\n uint32_t *v22;\n int v23;\n long long v24;\n int v25;\n long long v29;\n int v31;\n uint32_t *v32;\n int v33;\n long long v34;\n int v35;\n long long v36;\n int v37;\n long long v38;\n int v39;\n unsigned long long v40;\n v40 = __readfsqword(40u);\n v9 = malloc(12LL * a4 * a2);\n v33 = 0;\n v10 = a5;\n v11 = malloc(v10 * 8);\n v12 = v11;\n if (a5 <= 0) {\n if (a5 != 0 && a4 != 0 && a2) {\n v34 = (unsigned int)(*a3 + *a1);\n heapPush(v9, &v33, v34, 0LL);\n LODWORD(v15) = 0;\n LABEL_19:\n *a6 = v15;\n free(v9);\n return v12;\n }\n } else {\n v13 = (void **)v11;\n v14 = (void **)&v11[v10];\n do\n *v13++ = malloc(8uLL);\n while (v13 != v14);\n if (a2 && a4) {\n v31 = *a3;\n v34 = (unsigned int)(*a1 + *a3);\n v35 = 0;\n heapPush(v9, &v33, v34, 0LL);\n if (v33 <= 0) {\n LODWORD(v15) = 0;\n } else {\n v15 = 1LL;\n v32 = a6;\n for (i = heapPop(v9, &v33);; i = heapPop(v9, &v33)) {\n v19 = v17;\n v20 = HIDWORD(i);\n v36 = i;\n v37 = v17;\n v21 = SHIDWORD(i);\n v29 = SHIDWORD(i);\n v22 = (uint32_t *)v12[v15 - 1];\n v23 = a1[v21];\n *v22 = v23;\n v24 = v19;\n v22[1] = a3[v24];\n if (v19 + 1 < a4) {\n LODWORD(v38) = a3[v24 + 1] + v23;\n HIDWORD(v38) = v20;\n v39 = v19 + 1;\n heapPush(v9, &v33, v38, (unsigned int)(v19 + 1));\n }\n if (!v19) {\n v25 = v20 + 1;\n if (v25 < a2) {\n LODWORD(v38) = a1[v29 + 1] + v31;\n HIDWORD(v38) = v25;\n v39 = 0;\n heapPush(v9, &v33, v38, 0LL);\n }\n }\n if (v33 <= 0 || a5 <= (int)v15) break;\n ++v15;\n }\n a6 = v32;\n }\n goto LABEL_19;\n }\n }\n *a6 = 0;\n free(v9);\n return v12;\n}" + }, + { + "index": 408, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int sum;\n\n int index1;\n\n int index2;\n\n} HeapNode;\n\n\n\nvoid swap(HeapNode *a, HeapNode *b) {\n\n HeapNode temp = *a;\n\n *a = *b;\n\n *b = temp;\n\n}\n\n\n\nvoid heapify(HeapNode heap[], int n, int i) {\n\n int smallest = i;\n\n int l = 2*i + 1;\n\n int r = 2*i + 2;\n\n\n\n if (l < n && heap[l].sum < heap[smallest].sum)\n\n smallest = l;\n\n\n\n if (r < n && heap[r].sum < heap[smallest].sum)\n\n smallest = r;\n\n\n\n if (smallest != i) {\n\n swap(&heap[i], &heap[smallest]);\n\n heapify(heap, n, smallest);\n\n }\n\n}\n\n\n\nvoid heapPush(HeapNode heap[], int *size, HeapNode node) {\n\n int i = *size;\n\n heap[i] = node;\n\n (*size)++;\n\n while (i != 0 && heap[(i-1)/2].sum > heap[i].sum) {\n\n swap(&heap[(i-1)/2], &heap[i]);\n\n i = (i-1)/2;\n\n }\n\n}\n\n\n\nHeapNode heapPop(HeapNode heap[], int *size) {\n\n if (*size <= 0) {\n\n HeapNode invalid = {-1, -1, -1};\n\n return invalid;\n\n }\n\n if (*size == 1) {\n\n (*size)--;\n\n return heap[0];\n\n }\n\n HeapNode root = heap[0];\n\n heap[0] = heap[*size - 1];\n\n (*size)--;\n\n heapify(heap, *size, 0);\n\n return root;\n\n}\n\n\n\n", + "func": "int **func0(int nums1[], int nums1Size, int nums2[], int nums2Size, int k,\n int *returnSize) {\n HeapNode *heap =\n (HeapNode *)malloc(sizeof(HeapNode) * (nums1Size * nums2Size));\n int heapSize = 0;\n int **result = (int **)malloc(sizeof(int *) * k);\n for (int i = 0; i < k; i++) {\n result[i] = (int *)malloc(sizeof(int) * 2);\n }\n if (nums1Size == 0 || nums2Size == 0 || k == 0) {\n *returnSize = 0;\n free(heap);\n return result;\n }\n heapPush(heap, &heapSize, (HeapNode){nums1[0] + nums2[0], 0, 0});\n int count = 0;\n while (heapSize > 0 && count < k) {\n HeapNode node = heapPop(heap, &heapSize);\n result[count][0] = nums1[node.index1];\n result[count][1] = nums2[node.index2];\n count++;\n if (node.index2 + 1 < nums2Size) {\n heapPush(heap, &heapSize,\n (HeapNode){nums1[node.index1] + nums2[node.index2 + 1],\n node.index1, node.index2 + 1});\n }\n if (node.index2 == 0 && node.index1 + 1 < nums1Size) {\n heapPush(\n heap, &heapSize,\n (HeapNode){nums1[node.index1 + 1] + nums2[0], node.index1 + 1, 0});\n }\n }\n *returnSize = count;\n free(heap);\n return result;\n}", + "test": "int main() {\n\n int returnSize;\n\n int **result;\n\n\n\n result = func0((int[]){1, 3, 7}, 3, (int[]){2, 4, 6}, 3, 2, &returnSize);\n\n assert(returnSize == 2 && result[0][0] == 1 && result[0][1] == 2 && result[1][0] == 1 && result[1][1] == 4);\n\n\n\n result = func0((int[]){1, 3, 7}, 3, (int[]){2, 4, 6}, 3, 1, &returnSize);\n\n assert(returnSize == 1 && result[0][0] == 1 && result[0][1] == 2);\n\n\n\n result = func0((int[]){1, 3, 7}, 3, (int[]){2, 4, 6}, 3, 7, &returnSize);\n\n assert(returnSize == 7 && result[0][0] == 1 && result[0][1] == 2 && result[1][0] == 1 && result[1][1] == 4);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmov %ecx,%r15d\npush %r14\nmov %rdx,%r14\npush %r13\nmov %esi,%r13d\npush %r12\npush %rbp\npush %rbx\nmov %r8d,%ebx\nsub $0x58,%rsp\nmov %rdi,0x10(%rsp)\nmov %esi,0xc(%rsp)\nmov %ecx,0x4(%rsp)\nmov %r9,0x18(%rsp)\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %esi,%eax\nimul %ecx,%eax\ncltq\nlea (%rax,%rax,2),%rdi\nshl $0x2,%rdi\ncallq 10b0 \nmovslq %ebx,%rdi\nmovl $0x0,0x20(%rsp)\nshl $0x3,%rdi\nmov %rax,%rbp\ncallq 10b0 \ntest %r15d,%r15d\nsete %r15b\ntest %ebx,%ebx\nmov %rax,%r12\nsete %al\nor %eax,%r15d\ntest %r13d,%r13d\nsete %al\nor %eax,%r15d\nmov %r15b,0x8(%rsp)\ntest %ebx,%ebx\njle 17f0 \nlea -0x1(%rbx),%eax\nmov %r12,%r15\nlea 0x8(%r12,%rax,8),%r13\nxchg %ax,%ax\nmov $0x8,%edi\nadd $0x8,%r15\ncallq 10b0 \nmov %rax,-0x8(%r15)\ncmp %r13,%r15\njne 1640 \ncmpb $0x0,0x8(%rsp)\nje 16a0 \nmov 0x18(%rsp),%rax\nmov %rbp,%rdi\nmovl $0x0,(%rax)\ncallq 1080 \nmov 0x48(%rsp),%rax\nxor %fs:0x28,%rax\njne 182d \nadd $0x58,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw 0x0(%rax,%rax,1)\nmov 0x10(%rsp),%r11\nmov (%r14),%eax\nlea 0x20(%rsp),%r13\nmov %rbp,%rdi\nmovq $0x0,0x28(%rsp)\nmov 0x2c(%rsp),%ecx\nmov %r13,%rsi\nadd (%r11),%eax\nmov %eax,0x24(%rsp)\nmov 0x24(%rsp),%rdx\ncallq 1480 \nmov 0x20(%rsp),%edx\ntest %edx,%edx\njle 1832 \nmov %ebx,0x8(%rsp)\nmov $0x1,%r15d\nmov %r11,%rbx\njmp 1721 \nnopl 0x0(%rax)\ntest %r11d,%r11d\njne 1704 \nadd $0x1,%r10d\ncmp 0xc(%rsp),%r10d\njl 17a0 \nmov 0x20(%rsp),%eax\ntest %eax,%eax\nsetg %dl\ncmp %r15d,0x8(%rsp)\nsetg %al\nadd $0x1,%r15\ntest %al,%dl\nje 17d0 \nmov %r13,%rsi\nmov %r15d,%ebp\ncallq 14f0 \nmov -0x8(%r12,%r15,8),%rcx\nmov %rax,%r10\nmov %rax,0x30(%rsp)\nmov %rdx,%r11\nshr $0x20,%r10\nmov %edx,0x38(%rsp)\nmovslq %r11d,%r9\nmovslq %r10d,%rax\nshl $0x2,%rax\nlea (%rbx,%rax,1),%rdx\nmov (%rdx),%esi\nmov %esi,(%rcx)\nlea 0x0(,%r9,4),%rsi\nmov (%r14,%r9,4),%r9d\nmov %r9d,0x4(%rcx)\nlea 0x1(%r11),%ecx\ncmp 0x4(%rsp),%ecx\njge 16f0 \nmov (%rdx),%edx\nadd 0x4(%r14,%rsi,1),%edx\nmov %r10d,0x40(%rsp)\nmov %r13,%rsi\nmov %edx,0x3c(%rsp)\nmov 0x3c(%rsp),%rdx\nmov %rax,0x10(%rsp)\nmov %ecx,0x44(%rsp)\ncallq 1480 \nmov 0x10(%rsp),%rax\njmpq 16f0 \nmov (%r14),%edx\nadd 0x4(%rbx,%rax,1),%edx\nmov %r10d,0x40(%rsp)\nxor %ecx,%ecx\nmov %edx,0x3c(%rsp)\nmov 0x3c(%rsp),%rdx\nmov %r13,%rsi\nmovl $0x0,0x44(%rsp)\ncallq 1480 \njmpq 1704 \nnopl 0x0(%rax)\nmov %ebp,%r9d\nmov %rdi,%rbp\nmov 0x18(%rsp),%rax\nmov %rbp,%rdi\nmov %r9d,(%rax)\ncallq 1080 \njmpq 1671 \nnopl 0x0(%rax,%rax,1)\ncmpb $0x0,0x8(%rsp)\njne 165e \nmov 0x10(%rsp),%rax\nlea 0x20(%rsp),%rsi\nmov %rbp,%rdi\nmovq $0x0,0x28(%rsp)\nmov 0x2c(%rsp),%ecx\nmov (%rax),%eax\nadd (%r14),%eax\nmov %eax,0x24(%rsp)\nmov 0x24(%rsp),%rdx\ncallq 1480 \nxor %r9d,%r9d\njmp 17d6 \ncallq 1090 <__stack_chk_fail@plt>\nxor %r9d,%r9d\njmp 17d6 \nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov r15d, esi\npush r14\nmov r14d, ecx\npush r13\npush r12\npush rbp\npush rbx\nmovsxd rbx, r8d\nmov r12, rbx\nshl rbx, 3\nsub rsp, 78h\nmov [rsp+0A8h+var_80], rdx\nmov [rsp+0A8h+var_90], rdi\nmov [rsp+0A8h+var_94], esi\nmov [rsp+0A8h+var_88], r9\nmov rax, fs:28h\nmov [rsp+0A8h+var_40], rax\nmov eax, esi\nimul eax, ecx\ncdqe\nlea rdi, [rax+rax*2]\nshl rdi, 2; size\ncall _malloc\nmov rdi, rbx; size\nmov [rsp+0A8h+var_6C], 0\nmov rbp, rax\ncall _malloc\ntest r14d, r14d\nmov r13, rax\nsetz al\ntest r12d, r12d\nsetz dl\nor eax, edx\ntest r15d, r15d\nsetz dl\nor eax, edx\ntest r12d, r12d\njle loc_1810\nmov [rsp+0A8h+ptr], rbp\nadd rbx, r13\nmov rbp, r13\nmov r15d, eax\nnop word ptr [rax+rax+00h]\nloc_1620:\nmov edi, 8; size\nadd rbp, 8\ncall _malloc\nmov [rbp-8], rax\ncmp rbp, rbx\njnz short loc_1620\nmov rbp, [rsp+0A8h+ptr]\ntest r15b, r15b\njz short loc_1680\nloc_1641:\nmov rax, [rsp+0A8h+var_88]\nmov rdi, rbp; ptr\nmov dword ptr [rax], 0\ncall _free\nloc_1654:\nmov rax, [rsp+0A8h+var_40]\nsub rax, fs:28h\njnz loc_184E\nadd rsp, 78h\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1680:\nmov r11, [rsp+0A8h+var_80]\nmov r10, [rsp+0A8h+var_90]\nmov rdi, rbp\nmov [rsp+0A8h+var_68+4], 0\nmov ecx, [rsp+0A8h+var_60]\nmov eax, [r11]\nmov dword ptr [rsp+0A8h+var_80], eax\nadd eax, [r10]\nmov dword ptr [rsp+0A8h+var_68], eax\nlea rax, [rsp+0A8h+var_6C]\nmov rdx, [rsp+0A8h+var_68]\nmov rsi, rax\nmov [rsp+0A8h+ptr], rax\ncall heapPush\nmov ecx, [rsp+0A8h+var_6C]\ntest ecx, ecx\njle loc_1849\nmov ebx, r14d\nmov ebp, r12d\nmov r15d, 1\nmov r14, r10\nmov r12, r11\njmp short loc_1712\nloc_16E0:\ntest r10d, r10d\njnz short loc_16F6\nmov ecx, [rsp+0A8h+var_94]\nadd r11d, 1\ncmp r11d, ecx\njl loc_17B0\nloc_16F6:\nmov edx, [rsp+0A8h+var_6C]\nlea rax, [r15+1]\ntest edx, edx\njle loc_17F0\nloc_1706:\ncmp ebp, r15d\njle loc_17F0\nmov r15, rax\nloc_1712:\nmov rsi, [rsp+0A8h+ptr]\ncall heapPop\nmov rsi, rax\nmov r10, rdx\nmov [rsp+0A8h+var_5C], rax\nshr rsi, 20h\nlea ecx, [r10+1]\nmov [rsp+0A8h+var_54], r10d\nmovsxd rdx, esi\nmovd xmm0, dword ptr [r14+rdx*4]\nmov r11, rdx\nlea rax, ds:0[rdx*4]\nmovsxd rdx, r10d\nmovd xmm2, dword ptr [r12+rdx*4]\nlea rsi, ds:0[rdx*4]\nmov rdx, [r13+r15*8-8]\nmovdqa xmm1, xmm0\npunpckldq xmm1, xmm2\nmovq qword ptr [rdx], xmm1\ncmp ecx, ebx\njge loc_16E0\nmov [rsp+0A8h+var_90], rax\nmovd eax, xmm0\nadd eax, [r12+rsi+4]\nmovd xmm3, r11d\nmovd xmm0, eax\nmov rsi, [rsp+0A8h+ptr]\nmov [rsp+0A8h+var_48], ecx\npunpckldq xmm0, xmm3\nmovq rdx, xmm0\nmovq [rsp+0A8h+var_50], xmm0\ncall heapPush\nmov rax, [rsp+0A8h+var_90]\njmp loc_16E0\nloc_17B0:\nmov ecx, dword ptr [rsp+0A8h+var_80]\nadd ecx, [r14+rax+4]\nmov dword ptr [rsp+0A8h+var_50+4], r11d\nmov dword ptr [rsp+0A8h+var_50], ecx\nmov rsi, [rsp+0A8h+ptr]\nxor ecx, ecx\nmov rdx, [rsp+0A8h+var_50]\nmov [rsp+0A8h+var_48], 0\ncall heapPush\nmov edx, [rsp+0A8h+var_6C]\nlea rax, [r15+1]\ntest edx, edx\njg loc_1706\nnop dword ptr [rax+rax+00h]\nloc_17F0:\nmov rbp, rdi\nmov r8d, r15d\nloc_17F6:\nmov rax, [rsp+0A8h+var_88]\nmov rdi, rbp; ptr\nmov [rax], r8d\ncall _free\njmp loc_1654\nloc_1810:\ntest al, al\njnz loc_1641\nmov rax, [rsp+0A8h+var_90]\nmov rbx, [rsp+0A8h+var_80]\nlea rsi, [rsp+0A8h+var_6C]\nmov rdi, rbp\nmov [rsp+0A8h+var_68+4], 0\nmov ecx, [rsp+0A8h+var_60]\nmov eax, [rax]\nadd eax, [rbx]\nmov dword ptr [rsp+0A8h+var_68], eax\nmov rdx, [rsp+0A8h+var_68]\ncall heapPush\nloc_1849:\nxor r8d, r8d\njmp short loc_17F6\nloc_184E:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(_DWORD *a1, signed int a2, int *a3, int a4, int a5, _DWORD *a6)\n{\n size_t v8; // rbx\n void *v9; // rbp\n char *v10; // r13\n char *v11; // rbx\n char *v12; // rbp\n __int64 v14; // r10\n __int64 v15; // r11\n int v16; // ebx\n int v17; // ebp\n __int64 v18; // r15\n __int64 v19; // r14\n __int64 v20; // r12\n signed int v21; // r11d\n __int64 v22; // rax\n __int64 v23; // rax\n int v24; // edx\n int v25; // r10d\n __int64 v26; // rcx\n __m128i v27; // xmm0\n unsigned int v28; // r11d\n __int64 v29; // rax\n __m128i v30; // xmm0\n int v31; // r8d\n void *ptr; // [rsp+8h] [rbp-A0h]\n __int64 v33; // [rsp+18h] [rbp-90h]\n int v36; // [rsp+28h] [rbp-80h]\n int v37; // [rsp+3Ch] [rbp-6Ch] BYREF\n _BYTE v38[12]; // [rsp+40h] [rbp-68h]\n __int64 v39; // [rsp+4Ch] [rbp-5Ch]\n int v40; // [rsp+54h] [rbp-54h]\n unsigned __int64 v41; // [rsp+58h] [rbp-50h]\n int v42; // [rsp+60h] [rbp-48h]\n unsigned __int64 v43; // [rsp+68h] [rbp-40h]\n\n v8 = 8LL * a5;\n v43 = __readfsqword(0x28u);\n v37 = 0;\n v9 = malloc(12LL * a4 * a2);\n v10 = (char *)malloc(v8);\n if ( a5 <= 0 )\n {\n if ( a2 == 0 || a5 == 0 || a4 == 0 )\n {\nLABEL_5:\n *a6 = 0;\n free(v9);\n return v10;\n }\n *(_QWORD *)&v38[4] = 0LL;\n *(_DWORD *)v38 = *a3 + *a1;\n heapPush(v9, &v37, *(unsigned int *)v38, 0LL);\n }\n else\n {\n ptr = v9;\n v11 = &v10[v8];\n v12 = v10;\n do\n {\n v12 += 8;\n *((_QWORD *)v12 - 1) = malloc(8uLL);\n }\n while ( v12 != v11 );\n v9 = ptr;\n if ( a2 == 0 || a5 == 0 || a4 == 0 )\n goto LABEL_5;\n *(_QWORD *)&v38[4] = 0LL;\n v36 = *a3;\n *(_QWORD *)v38 = (unsigned int)(*a1 + v36);\n heapPush(ptr, &v37, *(_QWORD *)v38, 0LL);\n if ( v37 > 0 )\n {\n v16 = a4;\n v17 = a5;\n v18 = 1LL;\n v19 = v14;\n v20 = v15;\n while ( 1 )\n {\n v23 = heapPop(ptr, &v37);\n v25 = v24;\n v39 = v23;\n v26 = (unsigned int)(v24 + 1);\n v40 = v24;\n v27 = _mm_cvtsi32_si128(*(_DWORD *)(v19 + 4LL * SHIDWORD(v23)));\n v28 = HIDWORD(v23);\n v29 = 4LL * SHIDWORD(v23);\n **(_QWORD **)&v10[8 * v18 - 8] = _mm_unpacklo_epi32(v27, _mm_cvtsi32_si128(*(_DWORD *)(v20 + 4LL * v24))).m128i_u64[0];\n if ( (int)v26 < v16 )\n {\n v33 = v29;\n v30 = _mm_cvtsi32_si128(*(_DWORD *)(v20 + 4LL * v24 + 4) + _mm_cvtsi128_si32(v27));\n v42 = v24 + 1;\n v41 = _mm_unpacklo_epi32(v30, _mm_cvtsi32_si128(v28)).m128i_u64[0];\n heapPush(ptr, &v37, v41, v26);\n v29 = v33;\n }\n if ( v25 || (v21 = v28 + 1, v21 >= a2) )\n {\n v22 = v18 + 1;\n if ( v37 <= 0 )\n goto LABEL_17;\n }\n else\n {\n v41 = __PAIR64__(v21, *(_DWORD *)(v19 + v29 + 4) + v36);\n v42 = 0;\n heapPush(ptr, &v37, v41, 0LL);\n v22 = v18 + 1;\n if ( v37 <= 0 )\n {\nLABEL_17:\n v9 = ptr;\n v31 = v18;\n goto LABEL_18;\n }\n }\n if ( v17 <= (int)v18 )\n goto LABEL_17;\n v18 = v22;\n }\n }\n }\n v31 = 0;\nLABEL_18:\n *a6 = v31;\n free(v9);\n return v10;\n}", + "ida_strip_asm": "sub_1580:\nendbr64\npush r15\nmov r15d, esi\npush r14\nmov r14d, ecx\npush r13\npush r12\npush rbp\npush rbx\nmovsxd rbx, r8d\nmov r12, rbx\nshl rbx, 3\nsub rsp, 78h\nmov [rsp+0A8h+var_80], rdx\nmov [rsp+0A8h+var_90], rdi\nmov [rsp+0A8h+var_94], esi\nmov [rsp+0A8h+var_88], r9\nmov rax, fs:28h\nmov [rsp+0A8h+var_40], rax\nmov eax, esi\nimul eax, ecx\ncdqe\nlea rdi, [rax+rax*2]\nshl rdi, 2; size\ncall _malloc\nmov rdi, rbx; size\nmov [rsp+0A8h+var_6C], 0\nmov rbp, rax\ncall _malloc\ntest r14d, r14d\nmov r13, rax\nsetz al\ntest r12d, r12d\nsetz dl\nor eax, edx\ntest r15d, r15d\nsetz dl\nor eax, edx\ntest r12d, r12d\njle loc_1810\nmov [rsp+0A8h+ptr], rbp\nadd rbx, r13\nmov rbp, r13\nmov r15d, eax\nnop word ptr [rax+rax+00h]\nloc_1620:\nmov edi, 8; size\nadd rbp, 8\ncall _malloc\nmov [rbp-8], rax\ncmp rbp, rbx\njnz short loc_1620\nmov rbp, [rsp+0A8h+ptr]\ntest r15b, r15b\njz short loc_1680\nloc_1641:\nmov rax, [rsp+0A8h+var_88]\nmov rdi, rbp; ptr\nmov dword ptr [rax], 0\ncall _free\nloc_1654:\nmov rax, [rsp+0A8h+var_40]\nsub rax, fs:28h\njnz loc_184E\nadd rsp, 78h\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1680:\nmov r11, [rsp+0A8h+var_80]\nmov r10, [rsp+0A8h+var_90]\nmov rdi, rbp\nmov [rsp+0A8h+var_68+4], 0\nmov ecx, [rsp+0A8h+var_60]\nmov eax, [r11]\nmov dword ptr [rsp+0A8h+var_80], eax\nadd eax, [r10]\nmov dword ptr [rsp+0A8h+var_68], eax\nlea rax, [rsp+0A8h+var_6C]\nmov rdx, [rsp+0A8h+var_68]\nmov rsi, rax\nmov [rsp+0A8h+ptr], rax\ncall sub_1460\nmov ecx, [rsp+0A8h+var_6C]\ntest ecx, ecx\njle loc_1849\nmov ebx, r14d\nmov ebp, r12d\nmov r15d, 1\nmov r14, r10\nmov r12, r11\njmp short loc_1712\nloc_16E0:\ntest r10d, r10d\njnz short loc_16F6\nmov ecx, [rsp+0A8h+var_94]\nadd r11d, 1\ncmp r11d, ecx\njl loc_17B0\nloc_16F6:\nmov edx, [rsp+0A8h+var_6C]\nlea rax, [r15+1]\ntest edx, edx\njle loc_17F0\nloc_1706:\ncmp ebp, r15d\njle loc_17F0\nmov r15, rax\nloc_1712:\nmov rsi, [rsp+0A8h+ptr]\ncall sub_14D0\nmov rsi, rax\nmov r10, rdx\nmov [rsp+0A8h+var_5C], rax\nshr rsi, 20h\nlea ecx, [r10+1]\nmov [rsp+0A8h+var_54], r10d\nmovsxd rdx, esi\nmovd xmm0, dword ptr [r14+rdx*4]\nmov r11, rdx\nlea rax, ds:0[rdx*4]\nmovsxd rdx, r10d\nmovd xmm2, dword ptr [r12+rdx*4]\nlea rsi, ds:0[rdx*4]\nmov rdx, [r13+r15*8-8]\nmovdqa xmm1, xmm0\npunpckldq xmm1, xmm2\nmovq qword ptr [rdx], xmm1\ncmp ecx, ebx\njge loc_16E0\nmov [rsp+0A8h+var_90], rax\nmovd eax, xmm0\nadd eax, [r12+rsi+4]\nmovd xmm3, r11d\nmovd xmm0, eax\nmov rsi, [rsp+0A8h+ptr]\nmov [rsp+0A8h+var_48], ecx\npunpckldq xmm0, xmm3\nmovq rdx, xmm0\nmovq [rsp+0A8h+var_50], xmm0\ncall sub_1460\nmov rax, [rsp+0A8h+var_90]\njmp loc_16E0\nloc_17B0:\nmov ecx, dword ptr [rsp+0A8h+var_80]\nadd ecx, [r14+rax+4]\nmov dword ptr [rsp+0A8h+var_50+4], r11d\nmov dword ptr [rsp+0A8h+var_50], ecx\nmov rsi, [rsp+0A8h+ptr]\nxor ecx, ecx\nmov rdx, [rsp+0A8h+var_50]\nmov [rsp+0A8h+var_48], 0\ncall sub_1460\nmov edx, [rsp+0A8h+var_6C]\nlea rax, [r15+1]\ntest edx, edx\njg loc_1706\nnop dword ptr [rax+rax+00h]\nloc_17F0:\nmov rbp, rdi\nmov r8d, r15d\nloc_17F6:\nmov rax, [rsp+0A8h+var_88]\nmov rdi, rbp; ptr\nmov [rax], r8d\ncall _free\njmp loc_1654\nloc_1810:\ntest al, al\njnz loc_1641\nmov rax, [rsp+0A8h+var_90]\nmov rbx, [rsp+0A8h+var_80]\nlea rsi, [rsp+0A8h+var_6C]\nmov rdi, rbp\nmov [rsp+0A8h+var_68+4], 0\nmov ecx, [rsp+0A8h+var_60]\nmov eax, [rax]\nadd eax, [rbx]\nmov dword ptr [rsp+0A8h+var_68], eax\nmov rdx, [rsp+0A8h+var_68]\ncall sub_1460\nloc_1849:\nxor r8d, r8d\njmp short loc_17F6\nloc_184E:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_1580(_DWORD *a1, signed int a2, int *a3, int a4, int a5, _DWORD *a6)\n{\n size_t v8; // rbx\n void *v9; // rbp\n char *v10; // r13\n char *v11; // rbx\n char *v12; // rbp\n __int64 v14; // r10\n __int64 v15; // r11\n int v16; // ebx\n int v17; // ebp\n __int64 v18; // r15\n __int64 v19; // r14\n __int64 v20; // r12\n signed int v21; // r11d\n __int64 v22; // rax\n __int64 v23; // rax\n int v24; // edx\n int v25; // r10d\n __int64 v26; // rcx\n __m128i v27; // xmm0\n unsigned int v28; // r11d\n __int64 v29; // rax\n __m128i v30; // xmm0\n int v31; // r8d\n void *ptr; // [rsp+8h] [rbp-A0h]\n __int64 v33; // [rsp+18h] [rbp-90h]\n int v36; // [rsp+28h] [rbp-80h]\n int v37; // [rsp+3Ch] [rbp-6Ch] BYREF\n _BYTE v38[12]; // [rsp+40h] [rbp-68h]\n __int64 v39; // [rsp+4Ch] [rbp-5Ch]\n int v40; // [rsp+54h] [rbp-54h]\n unsigned __int64 v41; // [rsp+58h] [rbp-50h]\n int v42; // [rsp+60h] [rbp-48h]\n unsigned __int64 v43; // [rsp+68h] [rbp-40h]\n\n v8 = 8LL * a5;\n v43 = __readfsqword(0x28u);\n v37 = 0;\n v9 = malloc(12LL * a4 * a2);\n v10 = (char *)malloc(v8);\n if ( a5 <= 0 )\n {\n if ( a2 == 0 || a5 == 0 || a4 == 0 )\n {\nLABEL_5:\n *a6 = 0;\n free(v9);\n return v10;\n }\n *(_QWORD *)&v38[4] = 0LL;\n *(_DWORD *)v38 = *a3 + *a1;\n sub_1460(v9, &v37, *(unsigned int *)v38, 0LL);\n }\n else\n {\n ptr = v9;\n v11 = &v10[v8];\n v12 = v10;\n do\n {\n v12 += 8;\n *((_QWORD *)v12 - 1) = malloc(8uLL);\n }\n while ( v12 != v11 );\n v9 = ptr;\n if ( a2 == 0 || a5 == 0 || a4 == 0 )\n goto LABEL_5;\n *(_QWORD *)&v38[4] = 0LL;\n v36 = *a3;\n *(_QWORD *)v38 = (unsigned int)(*a1 + v36);\n sub_1460(ptr, &v37, *(_QWORD *)v38, 0LL);\n if ( v37 > 0 )\n {\n v16 = a4;\n v17 = a5;\n v18 = 1LL;\n v19 = v14;\n v20 = v15;\n while ( 1 )\n {\n v23 = sub_14D0(ptr, &v37);\n v25 = v24;\n v39 = v23;\n v26 = (unsigned int)(v24 + 1);\n v40 = v24;\n v27 = _mm_cvtsi32_si128(*(_DWORD *)(v19 + 4LL * SHIDWORD(v23)));\n v28 = HIDWORD(v23);\n v29 = 4LL * SHIDWORD(v23);\n **(_QWORD **)&v10[8 * v18 - 8] = _mm_unpacklo_epi32(v27, _mm_cvtsi32_si128(*(_DWORD *)(v20 + 4LL * v24))).m128i_u64[0];\n if ( (int)v26 < v16 )\n {\n v33 = v29;\n v30 = _mm_cvtsi32_si128(*(_DWORD *)(v20 + 4LL * v24 + 4) + _mm_cvtsi128_si32(v27));\n v42 = v24 + 1;\n v41 = _mm_unpacklo_epi32(v30, _mm_cvtsi32_si128(v28)).m128i_u64[0];\n sub_1460(ptr, &v37, v41, v26);\n v29 = v33;\n }\n if ( v25 || (v21 = v28 + 1, v21 >= a2) )\n {\n v22 = v18 + 1;\n if ( v37 <= 0 )\n goto LABEL_17;\n }\n else\n {\n v41 = __PAIR64__(v21, *(_DWORD *)(v19 + v29 + 4) + v36);\n v42 = 0;\n sub_1460(ptr, &v37, v41, 0LL);\n v22 = v18 + 1;\n if ( v37 <= 0 )\n {\nLABEL_17:\n v9 = ptr;\n v31 = v18;\n goto LABEL_18;\n }\n }\n if ( v17 <= (int)v18 )\n goto LABEL_17;\n v18 = v22;\n }\n }\n }\n v31 = 0;\nLABEL_18:\n *a6 = v31;\n free(v9);\n return v10;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1580(uint32_t *a1, signed int a2, int *a3, int a4, int a5,\n uint32_t *a6) {\n unsigned int v8;\n void *v9;\n char *v10;\n char *v11;\n char *v12;\n long long v14;\n long long v15;\n int v16;\n int v17;\n long long v18;\n long long v19;\n long long v20;\n signed int v21;\n long long v22;\n long long v23;\n int v24;\n int v25;\n long long v26;\n __m128i v27;\n unsigned int v28;\n long long v29;\n __m128i v30;\n int v31;\n void *ptr;\n long long v33;\n int v36;\n int v37;\n uint8_t v38[12];\n long long v39;\n int v40;\n unsigned long long v41;\n int v42;\n unsigned long long v43;\n v8 = 8LL * a5;\n v43 = __readfsqword(40u);\n v37 = 0;\n v9 = malloc(12LL * a4 * a2);\n v10 = (char *)malloc(v8);\n if (a5 <= 0) {\n if (a2 == 0 || a5 == 0 || a4 == 0) {\n LABEL_5:\n *a6 = 0;\n free(v9);\n return v10;\n }\n *(uint64_t *)&v38[4] = 0LL;\n *(uint32_t *)v38 = *a3 + *a1;\n sub_1460(v9, &v37, *(unsigned int *)v38, 0LL);\n } else {\n ptr = v9;\n v11 = &v10[v8];\n v12 = v10;\n do {\n v12 += 8;\n *((uint64_t *)v12 - 1) = malloc(8uLL);\n } while (v12 != v11);\n v9 = ptr;\n if (a2 == 0 || a5 == 0 || a4 == 0) goto LABEL_5;\n *(uint64_t *)&v38[4] = 0LL;\n v36 = *a3;\n *(uint64_t *)v38 = (unsigned int)(*a1 + v36);\n sub_1460(ptr, &v37, *(uint64_t *)v38, 0LL);\n if (v37 > 0) {\n v16 = a4;\n v17 = a5;\n v18 = 1LL;\n v19 = v14;\n v20 = v15;\n while (1) {\n v23 = sub_14D0(ptr, &v37);\n v25 = v24;\n v39 = v23;\n v26 = (unsigned int)(v24 + 1);\n v40 = v24;\n v27 = _mm_cvtsi32_si128(*(uint32_t *)(v19 + 4LL * SHIDWORD(v23)));\n v28 = HIDWORD(v23);\n v29 = 4LL * SHIDWORD(v23);\n **(uint64_t **)&v10[8 * v18 - 8] =\n _mm_unpacklo_epi32(\n v27, _mm_cvtsi32_si128(*(uint32_t *)(v20 + 4LL * v24)))\n .m128i_u64[0];\n if ((int)v26 < v16) {\n v33 = v29;\n v30 = _mm_cvtsi32_si128(*(uint32_t *)(v20 + 4LL * v24 + 4) +\n _mm_cvtsi128_si32(v27));\n v42 = v24 + 1;\n v41 = _mm_unpacklo_epi32(v30, _mm_cvtsi32_si128(v28)).m128i_u64[0];\n sub_1460(ptr, &v37, v41, v26);\n v29 = v33;\n }\n if (v25 || (v21 = v28 + 1, v21 >= a2)) {\n v22 = v18 + 1;\n if (v37 <= 0) goto LABEL_17;\n } else {\n v41 = __PAIR64__(v21, *(uint32_t *)(v19 + v29 + 4) + v36);\n v42 = 0;\n sub_1460(ptr, &v37, v41, 0LL);\n v22 = v18 + 1;\n if (v37 <= 0) {\n LABEL_17:\n v9 = ptr;\n v31 = v18;\n goto LABEL_18;\n }\n }\n if (v17 <= (int)v18) goto LABEL_17;\n v18 = v22;\n }\n }\n }\n v31 = 0;\nLABEL_18:\n *a6 = v31;\n free(v9);\n return v10;\n}", + "ida_pseudo_norm": "char *func0(uint32_t *a1, signed int a2, int *a3, int a4, int a5,\n uint32_t *a6) {\n unsigned int v8;\n void *v9;\n char *v10;\n char *v11;\n char *v12;\n long long v14;\n long long v15;\n int v16;\n int v17;\n long long v18;\n long long v19;\n long long v20;\n signed int v21;\n long long v22;\n long long v23;\n int v24;\n int v25;\n long long v26;\n __m128i v27;\n unsigned int v28;\n long long v29;\n __m128i v30;\n int v31;\n void *ptr;\n long long v33;\n int v36;\n int v37;\n uint8_t v38[12];\n long long v39;\n int v40;\n unsigned long long v41;\n int v42;\n unsigned long long v43;\n v8 = 8LL * a5;\n v43 = __readfsqword(40u);\n v37 = 0;\n v9 = malloc(12LL * a4 * a2);\n v10 = (char *)malloc(v8);\n if (a5 <= 0) {\n if (a2 == 0 || a5 == 0 || a4 == 0) {\n LABEL_5:\n *a6 = 0;\n free(v9);\n return v10;\n }\n *(uint64_t *)&v38[4] = 0LL;\n *(uint32_t *)v38 = *a3 + *a1;\n heapPush(v9, &v37, *(unsigned int *)v38, 0LL);\n } else {\n ptr = v9;\n v11 = &v10[v8];\n v12 = v10;\n do {\n v12 += 8;\n *((uint64_t *)v12 - 1) = malloc(8uLL);\n } while (v12 != v11);\n v9 = ptr;\n if (a2 == 0 || a5 == 0 || a4 == 0) goto LABEL_5;\n *(uint64_t *)&v38[4] = 0LL;\n v36 = *a3;\n *(uint64_t *)v38 = (unsigned int)(*a1 + v36);\n heapPush(ptr, &v37, *(uint64_t *)v38, 0LL);\n if (v37 > 0) {\n v16 = a4;\n v17 = a5;\n v18 = 1LL;\n v19 = v14;\n v20 = v15;\n while (1) {\n v23 = heapPop(ptr, &v37);\n v25 = v24;\n v39 = v23;\n v26 = (unsigned int)(v24 + 1);\n v40 = v24;\n v27 = _mm_cvtsi32_si128(*(uint32_t *)(v19 + 4LL * SHIDWORD(v23)));\n v28 = HIDWORD(v23);\n v29 = 4LL * SHIDWORD(v23);\n **(uint64_t **)&v10[8 * v18 - 8] =\n _mm_unpacklo_epi32(\n v27, _mm_cvtsi32_si128(*(uint32_t *)(v20 + 4LL * v24)))\n .m128i_u64[0];\n if ((int)v26 < v16) {\n v33 = v29;\n v30 = _mm_cvtsi32_si128(*(uint32_t *)(v20 + 4LL * v24 + 4) +\n _mm_cvtsi128_si32(v27));\n v42 = v24 + 1;\n v41 = _mm_unpacklo_epi32(v30, _mm_cvtsi32_si128(v28)).m128i_u64[0];\n heapPush(ptr, &v37, v41, v26);\n v29 = v33;\n }\n if (v25 || (v21 = v28 + 1, v21 >= a2)) {\n v22 = v18 + 1;\n if (v37 <= 0) goto LABEL_17;\n } else {\n v41 = __PAIR64__(v21, *(uint32_t *)(v19 + v29 + 4) + v36);\n v42 = 0;\n heapPush(ptr, &v37, v41, 0LL);\n v22 = v18 + 1;\n if (v37 <= 0) {\n LABEL_17:\n v9 = ptr;\n v31 = v18;\n goto LABEL_18;\n }\n }\n if (v17 <= (int)v18) goto LABEL_17;\n v18 = v22;\n }\n }\n }\n v31 = 0;\nLABEL_18:\n *a6 = v31;\n free(v9);\n return v10;\n}" + }, + { + "index": 408, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int sum;\n\n int index1;\n\n int index2;\n\n} HeapNode;\n\n\n\nvoid swap(HeapNode *a, HeapNode *b) {\n\n HeapNode temp = *a;\n\n *a = *b;\n\n *b = temp;\n\n}\n\n\n\nvoid heapify(HeapNode heap[], int n, int i) {\n\n int smallest = i;\n\n int l = 2*i + 1;\n\n int r = 2*i + 2;\n\n\n\n if (l < n && heap[l].sum < heap[smallest].sum)\n\n smallest = l;\n\n\n\n if (r < n && heap[r].sum < heap[smallest].sum)\n\n smallest = r;\n\n\n\n if (smallest != i) {\n\n swap(&heap[i], &heap[smallest]);\n\n heapify(heap, n, smallest);\n\n }\n\n}\n\n\n\nvoid heapPush(HeapNode heap[], int *size, HeapNode node) {\n\n int i = *size;\n\n heap[i] = node;\n\n (*size)++;\n\n while (i != 0 && heap[(i-1)/2].sum > heap[i].sum) {\n\n swap(&heap[(i-1)/2], &heap[i]);\n\n i = (i-1)/2;\n\n }\n\n}\n\n\n\nHeapNode heapPop(HeapNode heap[], int *size) {\n\n if (*size <= 0) {\n\n HeapNode invalid = {-1, -1, -1};\n\n return invalid;\n\n }\n\n if (*size == 1) {\n\n (*size)--;\n\n return heap[0];\n\n }\n\n HeapNode root = heap[0];\n\n heap[0] = heap[*size - 1];\n\n (*size)--;\n\n heapify(heap, *size, 0);\n\n return root;\n\n}\n\n\n\n", + "func": "int **func0(int nums1[], int nums1Size, int nums2[], int nums2Size, int k,\n int *returnSize) {\n HeapNode *heap =\n (HeapNode *)malloc(sizeof(HeapNode) * (nums1Size * nums2Size));\n int heapSize = 0;\n int **result = (int **)malloc(sizeof(int *) * k);\n for (int i = 0; i < k; i++) {\n result[i] = (int *)malloc(sizeof(int) * 2);\n }\n if (nums1Size == 0 || nums2Size == 0 || k == 0) {\n *returnSize = 0;\n free(heap);\n return result;\n }\n heapPush(heap, &heapSize, (HeapNode){nums1[0] + nums2[0], 0, 0});\n int count = 0;\n while (heapSize > 0 && count < k) {\n HeapNode node = heapPop(heap, &heapSize);\n result[count][0] = nums1[node.index1];\n result[count][1] = nums2[node.index2];\n count++;\n if (node.index2 + 1 < nums2Size) {\n heapPush(heap, &heapSize,\n (HeapNode){nums1[node.index1] + nums2[node.index2 + 1],\n node.index1, node.index2 + 1});\n }\n if (node.index2 == 0 && node.index1 + 1 < nums1Size) {\n heapPush(\n heap, &heapSize,\n (HeapNode){nums1[node.index1 + 1] + nums2[0], node.index1 + 1, 0});\n }\n }\n *returnSize = count;\n free(heap);\n return result;\n}", + "test": "int main() {\n\n int returnSize;\n\n int **result;\n\n\n\n result = func0((int[]){1, 3, 7}, 3, (int[]){2, 4, 6}, 3, 2, &returnSize);\n\n assert(returnSize == 2 && result[0][0] == 1 && result[0][1] == 2 && result[1][0] == 1 && result[1][1] == 4);\n\n\n\n result = func0((int[]){1, 3, 7}, 3, (int[]){2, 4, 6}, 3, 1, &returnSize);\n\n assert(returnSize == 1 && result[0][0] == 1 && result[0][1] == 2);\n\n\n\n result = func0((int[]){1, 3, 7}, 3, (int[]){2, 4, 6}, 3, 7, &returnSize);\n\n assert(returnSize == 7 && result[0][0] == 1 && result[0][1] == 2 && result[1][0] == 1 && result[1][1] == 4);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nmov %esi,%eax\npush %r15\nmov %rdi,%r15\nimul %ecx,%eax\npush %r14\npush %r13\npush %r12\nmov %rdx,%r12\npush %rbp\ncltq\nmov %r8d,%ebp\npush %rbx\nlea (%rax,%rax,2),%rdi\nshl $0x2,%rdi\nsub $0x38,%rsp\nmov %esi,0x14(%rsp)\nmov %ecx,0xc(%rsp)\nmov %r9,0x28(%rsp)\ncallq 10b0 \nmovslq %ebp,%rdi\nshl $0x3,%rdi\nmov %rax,%r13\ncallq 10b0 \nmov %rax,(%rsp)\ntest %ebp,%ebp\njle 160f \nmov %rax,%rbx\nmov %rax,%r14\nlea -0x1(%rbp),%eax\nlea 0x8(%rbx,%rax,8),%rbx\nnopl 0x0(%rax)\nmov $0x8,%edi\nadd $0x8,%r14\ncallq 10b0 \nmov %rax,-0x8(%r14)\ncmp %r14,%rbx\njne 15f8 \nmov 0xc(%rsp),%edx\ntest %edx,%edx\nsete %dl\ntest %ebp,%ebp\nsete %al\nor %al,%dl\njne 1820 \nmov 0x14(%rsp),%eax\ntest %eax,%eax\nje 1820 \nmov (%r12),%eax\nadd (%r15),%eax\nmov %ebp,0x10(%rsp)\nmov %r15,%r8\nmov %eax,0x0(%r13)\nxor %r14d,%r14d\nmov $0x1,%ebx\nmovq $0x0,0x4(%r13)\njmp 1678 \nnopl (%rax)\nmov %esi,%ebx\ntest %r15d,%r15d\njne 166c \nadd $0x1,%ebp\ncmp 0x14(%rsp),%ebp\njl 179e \ntest %ebx,%ebx\nje 1850 \nadd $0x1,%r14\nmov %r14d,%eax\nmov %r14d,%r11d\ncmp %r14d,0x10(%rsp)\njle 1850 \nmov 0x4(%r13),%ebp\nmov 0x8(%r13),%r15d\nxor %esi,%esi\ncmp $0x1,%ebx\nje 16d2 \nmovslq %ebx,%rdx\nlea -0x1(%rbx),%esi\nmov %r13,%rdi\nmov %r8,0x20(%rsp)\nlea (%rdx,%rdx,2),%rdx\nmov %eax,0x18(%rsp)\nlea 0x0(%r13,%rdx,4),%rdx\nmov -0xc(%rdx),%rcx\nmov %rcx,0x0(%r13)\nmov -0x4(%rdx),%edx\nmov %edx,0x8(%r13)\nxor %edx,%edx\ncallq 13c0 \nmov 0x20(%rsp),%r8\nmov 0x18(%rsp),%eax\nmovslq %ebp,%r10\nmov (%rsp),%rdi\nmovslq %r15d,%r9\nlea 0x1(%rax),%r11d\nshl $0x2,%r10\nlea 0x1(%r15),%eax\nlea (%r8,%r10,1),%rdx\nmov (%rdi,%r14,8),%rdi\nmov (%rdx),%ecx\nmov %ecx,(%rdi)\nlea 0x0(,%r9,4),%rcx\nmov (%r12,%r9,4),%r9d\nmov %r9d,0x4(%rdi)\ncmp 0xc(%rsp),%eax\njge 1658 \nmov (%rdx),%r9d\nadd 0x4(%r12,%rcx,1),%r9d\nmovslq %esi,%rcx\nlea (%rcx,%rcx,2),%rdx\nlea 0x0(%r13,%rdx,4),%rdx\nmov %r9d,(%rdx)\nmov %ebp,0x4(%rdx)\nmov %eax,0x8(%rdx)\ntest %esi,%esi\nje 1788 \nmov %r8,0x18(%rsp)\njmp 1764 \nnopw %cs:0x0(%rax,%rax,1)\nmov (%rdx),%r8\nmov 0x8(%rax),%ecx\nmov (%rax),%r9\nmov %r8,(%rax)\nmov 0x8(%rdx),%r8d\nmov %r8d,0x8(%rax)\nmov %r9,(%rdx)\nmov %ecx,0x8(%rdx)\ntest %esi,%esi\nje 1783 \nmov (%rax),%r9d\nmov %rdi,%rcx\nsub $0x1,%esi\nlea (%rcx,%rcx,2),%rdx\nsar %esi\nlea 0x0(%r13,%rdx,4),%rdx\nmovslq %esi,%rdi\nlea (%rdi,%rdi,2),%rax\nlea 0x0(%r13,%rax,4),%rax\ncmp %r9d,(%rax)\njg 1740 \nmov 0x18(%rsp),%r8\ntest %r15d,%r15d\njne 1674 \nadd $0x1,%ebp\ncmp 0x14(%rsp),%ebp\njge 166c \nmovslq %ebx,%rdx\nmov (%r12),%esi\nadd 0x4(%r8,%r10,1),%esi\nlea 0x1(%rbx),%edi\nlea (%rdx,%rdx,2),%rax\nlea 0x0(%r13,%rax,4),%rax\nmov %esi,(%rax)\nmov %ebp,0x4(%rax)\nmovl $0x0,0x8(%rax)\ntest %ebx,%ebx\njne 17f3 \njmp 1811 \nnopl 0x0(%rax,%rax,1)\nmov (%rdx),%r10\nmov 0x8(%rax),%esi\nmov (%rax),%r9\nmov %r10,(%rax)\nmov 0x8(%rdx),%r10d\nmov %r10d,0x8(%rax)\nmov %r9,(%rdx)\nmov %esi,0x8(%rdx)\ntest %ebx,%ebx\nje 1811 \nmov (%rax),%esi\nmov %rcx,%rdx\nsub $0x1,%ebx\nlea (%rdx,%rdx,2),%rdx\nsar %ebx\nlea 0x0(%r13,%rdx,4),%rdx\nmovslq %ebx,%rcx\nlea (%rcx,%rcx,2),%rax\nlea 0x0(%r13,%rax,4),%rax\ncmp %esi,(%rax)\njg 17d0 \nmov %edi,%ebx\njmpq 1674 \nnopl 0x0(%rax,%rax,1)\nmov 0x28(%rsp),%rax\nmov %r13,%rdi\nmovl $0x0,(%rax)\ncallq 1080 \nmov (%rsp),%rax\nadd $0x38,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw %cs:0x0(%rax,%rax,1)\nmov 0x28(%rsp),%rax\nmov %r13,%rdi\nmov %r11d,(%rax)\ncallq 1080 \njmp 1833 \nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\nmov eax, esi\npush r15\nimul eax, ecx\npush r14\npush r13\nmov r13, rdx\npush r12\nmov r12d, ecx\npush rbp\ncdqe\npush rbx\nmovsxd rbx, r8d\nsub rsp, 38h\nmov [rsp+68h+var_60], rdi\nlea rdi, [rax+rax*2]\nshl rdi, 2; size\nmov [rsp+68h+var_64], esi\nmov [rsp+68h+var_48], r9\ncall _malloc\nmov [rsp+68h+var_68], ebx\nshl rbx, 3\nmov rdi, rbx; size\nmov r14, rax\ncall _malloc\nmov esi, [rsp+68h+var_68]\nmov rbp, rax\nadd rbx, rax\nmov r15, rax\ntest esi, esi\njle loc_1750\nnop dword ptr [rax+rax+00h]\nloc_15F8:\nmov edi, 8; size\nadd r15, 8\ncall _malloc\nmov [r15-8], rax\ncmp r15, rbx\njnz short loc_15F8\nmov ecx, [rsp+68h+var_64]\ntest ecx, ecx\njz loc_1778\ntest r12d, r12d\njz loc_1778\nmov rdi, [rsp+68h+var_60]\nmov r9d, [r13+0]\nxor ecx, ecx\nxor r15d, r15d\nmov qword ptr [r14+4], 0\nmov r8d, 1\nmov r11d, 1\nxor ebx, ebx\nmov eax, [rdi]\nmov [rsp+68h+var_3C], r9d\nadd eax, r9d\nmov [r14], eax\nmov rax, rdi\nmov edi, r12d\nmov r12d, ecx\nmov rcx, rbp\nmov rbp, r13\nmov r13, r8\nmov r8d, edi\nnop word ptr [rax+rax+00h]\nloc_1670:\nmovsxd rdx, r12d\nmovsxd r9, r15d\nmovd xmm0, dword ptr [rax+rdx*4]\nmovd xmm2, dword ptr [rbp+r9*4+0]\nlea rsi, ds:0[rdx*4]\nlea rdx, ds:0[r9*4]\nmov r9, [rcx+r13*8-8]\nmovdqa xmm1, xmm0\npunpckldq xmm1, xmm2\nmovq qword ptr [r9], xmm1\nlea r9d, [r15+1]\ncmp r9d, r8d\njl loc_17A0\nloc_16B1:\ntest r15d, r15d\njnz short loc_16C7\nmov edi, [rsp+68h+var_64]\nadd r12d, 1\ncmp r12d, edi\njl loc_1830\nloc_16C7:\ntest ebx, ebx\nsetnz dl\ncmp [rsp+68h+var_68], r13d\njle loc_18C0\nloc_16D6:\ntest dl, dl\njz loc_18C0\nmov r12d, [r14+4]\nmov r15d, [r14+8]\nxor esi, esi\ncmp ebx, 1\njz short loc_1739\nmovsxd rdx, ebx\nmov rdi, r14\nmov [rsp+68h+var_40], r8d\nlea rdx, [rdx+rdx*2]\nmov [rsp+68h+var_50], rax\nlea rdx, [r14+rdx*4]\nmov [rsp+68h+var_58], rcx\nmov rsi, [rdx-0Ch]\nmov [r14], rsi\nmov edx, [rdx-4]\nlea esi, [rbx-1]\nmov dword ptr [rsp+68h+var_60], esi\nmov [r14+8], edx\nxor edx, edx\ncall heapify\nmov r8d, [rsp+68h+var_40]\nmov rax, [rsp+68h+var_50]\nmov rcx, [rsp+68h+var_58]\nmov esi, dword ptr [rsp+68h+var_60]\nloc_1739:\nmov r11d, ebx\nadd r13, 1\nmov ebx, esi\njmp loc_1670\nloc_1750:\nmov edx, [rsp+68h+var_68]\ntest r12d, r12d\nsetz al\ntest edx, edx\nsetz dl\nor al, dl\njnz short loc_1778\nmov eax, [rsp+68h+var_64]\nxor r8d, r8d\ntest eax, eax\njnz loc_18C6\nnop dword ptr [rax+00000000h]\nloc_1778:\nmov rax, [rsp+68h+var_48]\nmov rdi, r14; ptr\nmov dword ptr [rax], 0\ncall _free\nloc_178B:\nadd rsp, 38h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_17A0:\nmovd edi, xmm0\nadd edi, [rbp+rdx+4]\nmovsxd rdx, ebx\nlea r10, [rdx+rdx*2]\nlea r10, [r14+r10*4]\nmov [r10], edi\nmov [r10+4], r12d\nmov [r10+8], r9d\ntest ebx, ebx\njz short loc_1820\nmov [rsp+68h+var_60], rsi\nmov [rsp+68h+var_58], rax\njmp short loc_17F1\nloc_17D0:\nmov rax, [rdx]\nmov r10, [rsi]\nmov edi, [rsi+8]\nmov [rsi], rax\nmov eax, [rdx+8]\nmov [rsi+8], eax\nmov [rdx], r10\nmov [rdx+8], edi\ntest ebx, ebx\njz short loc_1816\nmov edi, [rsi]\nmov rdx, r9\nloc_17F1:\nsub ebx, 1\nlea rdx, [rdx+rdx*2]\nmov esi, ebx\nlea rdx, [r14+rdx*4]\nshr esi, 1Fh\nadd esi, ebx\nmov ebx, esi\nsar ebx, 1\nmovsxd r9, ebx\nlea rsi, [r9+r9*2]\nlea rsi, [r14+rsi*4]\ncmp [rsi], edi\njg short loc_17D0\nloc_1816:\nmov rsi, [rsp+68h+var_60]\nmov rax, [rsp+68h+var_58]\nloc_1820:\nmov ebx, r11d\njmp loc_16B1\nloc_1830:\nmovsxd rdx, ebx\nmov r9d, [rsp+68h+var_3C]\nadd r9d, [rax+rsi+4]\nlea edi, [rbx+1]\nlea rsi, [rdx+rdx*2]\nlea rsi, [r14+rsi*4]\nmov [rsi], r9d\nmov [rsi+4], r12d\nmov dword ptr [rsi+8], 0\ntest ebx, ebx\njnz short loc_1886\njmp short loc_18AC\nloc_1860:\nmov r12, [rdx]\nmov r11, [rsi]\nmov r9d, [rsi+8]\nmov [rsi], r12\nmov r12d, [rdx+8]\nmov [rsi+8], r12d\nmov [rdx], r11\nmov [rdx+8], r9d\ntest ebx, ebx\njz short loc_18AC\nmov r9d, [rsi]\nmov rdx, r10\nloc_1886:\nsub ebx, 1\nlea rdx, [rdx+rdx*2]\nmov esi, ebx\nlea rdx, [r14+rdx*4]\nshr esi, 1Fh\nadd esi, ebx\nmov ebx, esi\nsar ebx, 1\nmovsxd r10, ebx\nlea rsi, [r10+r10*2]\nlea rsi, [r14+rsi*4]\ncmp [rsi], r9d\njg short loc_1860\nloc_18AC:\nmov ebx, edi\nmov edx, 1\ncmp [rsp+68h+var_68], r13d\njg loc_16D6\nnop dword ptr [rax]\nloc_18C0:\nmov r8, r13\nmov rbp, rcx\nloc_18C6:\nmov rax, [rsp+68h+var_48]\nmov rdi, r14; ptr\nmov [rax], r8d\ncall _free\njmp loc_178B", + "ida_pseudo": "char *__fastcall func0(_DWORD *a1, int a2, _DWORD *a3, int a4, int a5, _DWORD *a6)\n{\n size_t v8; // rbx\n _DWORD *v9; // r14\n char *v10; // rbp\n char *v11; // rbx\n char *v12; // r15\n int v13; // r9d\n int v14; // r15d\n int v15; // r11d\n int v16; // ebx\n _DWORD *v17; // rax\n int v18; // edi\n int v19; // r12d\n char *v20; // rcx\n _DWORD *v21; // rbp\n __int64 v22; // r13\n int v23; // r8d\n __m128i v24; // xmm0\n __int64 v25; // rsi\n int v26; // r12d\n bool v27; // dl\n int v28; // esi\n _DWORD *v29; // rdx\n int v30; // r8d\n int v32; // edi\n __int64 v33; // rdx\n int *v34; // r10\n __int64 v35; // r10\n int v36; // edi\n _DWORD *v37; // rdx\n int *v38; // rsi\n __int64 v39; // rdx\n int v40; // r9d\n int v41; // edi\n _DWORD *v42; // rsi\n __int64 v43; // r11\n int v44; // r9d\n _DWORD *v45; // rdx\n _DWORD *v46; // rsi\n char *v49; // [rsp+10h] [rbp-58h]\n _DWORD *v50; // [rsp+18h] [rbp-50h]\n int v52; // [rsp+28h] [rbp-40h]\n int v53; // [rsp+2Ch] [rbp-3Ch]\n\n v8 = 8LL * a5;\n v9 = malloc(12LL * a4 * a2);\n v10 = (char *)malloc(v8);\n v11 = &v10[v8];\n v12 = v10;\n if ( a5 <= 0 )\n {\n if ( a5 != 0 && a4 != 0 )\n {\n v30 = 0;\n if ( a2 )\n {\nLABEL_32:\n *a6 = v30;\n free(v9);\n return v10;\n }\n }\n }\n else\n {\n do\n {\n v12 += 8;\n *((_QWORD *)v12 - 1) = malloc(8uLL);\n }\n while ( v12 != v11 );\n if ( a2 && a4 )\n {\n v13 = *a3;\n v14 = 0;\n *(_QWORD *)(v9 + 1) = 0LL;\n v15 = 1;\n v16 = 0;\n v53 = v13;\n *v9 = v13 + *a1;\n v17 = a1;\n v18 = a4;\n v19 = 0;\n v20 = v10;\n v21 = a3;\n v22 = 1LL;\n v23 = v18;\n while ( 1 )\n {\n v24 = _mm_cvtsi32_si128(v17[v19]);\n v25 = v19;\n **(_QWORD **)&v20[8 * v22 - 8] = _mm_unpacklo_epi32(v24, _mm_cvtsi32_si128(v21[v14])).m128i_u64[0];\n if ( v14 + 1 < v23 )\n {\n v32 = v21[v14 + 1] + _mm_cvtsi128_si32(v24);\n v33 = v16;\n v34 = &v9[3 * v16];\n *v34 = v32;\n v34[1] = v19;\n v34[2] = v14 + 1;\n if ( v16 )\n {\n while ( 1 )\n {\n v37 = &v9[3 * v33];\n v16 = (v16 - 1) / 2;\n v38 = &v9[3 * v16];\n if ( *v38 <= v32 )\n break;\n v35 = *(_QWORD *)v38;\n v36 = v38[2];\n *(_QWORD *)v38 = *(_QWORD *)v37;\n v38[2] = v37[2];\n *(_QWORD *)v37 = v35;\n v37[2] = v36;\n if ( !v16 )\n break;\n v32 = *v38;\n v33 = v16;\n }\n v25 = v19;\n }\n v16 = v15;\n }\n if ( v14 || (v26 = v19 + 1, v26 >= a2) )\n {\n v27 = v16 != 0;\n if ( a5 <= (int)v22 )\n goto LABEL_31;\n }\n else\n {\n v39 = v16;\n v40 = v17[v25 + 1] + v53;\n v41 = v16 + 1;\n v42 = &v9[3 * v16];\n *v42 = v40;\n v42[1] = v26;\n v42[2] = 0;\n if ( v16 )\n {\n while ( 1 )\n {\n v45 = &v9[3 * v39];\n v16 = (v16 - 1) / 2;\n v46 = &v9[3 * v16];\n if ( *v46 <= v40 )\n break;\n v43 = *(_QWORD *)v46;\n v44 = v46[2];\n *(_QWORD *)v46 = *(_QWORD *)v45;\n v46[2] = v45[2];\n *(_QWORD *)v45 = v43;\n v45[2] = v44;\n if ( !v16 )\n break;\n v40 = *v46;\n v39 = v16;\n }\n }\n v16 = v41;\n v27 = 1;\n if ( a5 <= (int)v22 )\n {\nLABEL_31:\n v30 = v22;\n v10 = v20;\n goto LABEL_32;\n }\n }\n if ( !v27 )\n goto LABEL_31;\n v19 = v9[1];\n v14 = v9[2];\n v28 = 0;\n if ( v16 != 1 )\n {\n v52 = v23;\n v50 = v17;\n v29 = &v9[3 * v16];\n v49 = v20;\n *(_QWORD *)v9 = *(_QWORD *)(v29 - 3);\n v9[2] = *(v29 - 1);\n heapify(v9, (unsigned int)(v16 - 1), 0LL);\n v23 = v52;\n v17 = v50;\n v20 = v49;\n v28 = v16 - 1;\n }\n v15 = v16;\n ++v22;\n v16 = v28;\n }\n }\n }\n *a6 = 0;\n free(v9);\n return v10;\n}", + "ida_strip_asm": "sub_1590:\nendbr64\nmov eax, esi\npush r15\nimul eax, ecx\npush r14\npush r13\nmov r13, rdx\npush r12\nmov r12d, ecx\npush rbp\ncdqe\npush rbx\nmovsxd rbx, r8d\nsub rsp, 38h\nmov [rsp+68h+var_60], rdi\nlea rdi, [rax+rax*2]\nshl rdi, 2; size\nmov [rsp+68h+var_64], esi\nmov [rsp+68h+var_48], r9\ncall _malloc\nmov [rsp+68h+var_68], ebx\nshl rbx, 3\nmov rdi, rbx; size\nmov r14, rax\ncall _malloc\nmov esi, [rsp+68h+var_68]\nmov rbp, rax\nadd rbx, rax\nmov r15, rax\ntest esi, esi\njle loc_1750\nnop dword ptr [rax+rax+00h]\nloc_15F8:\nmov edi, 8; size\nadd r15, 8\ncall _malloc\nmov [r15-8], rax\ncmp r15, rbx\njnz short loc_15F8\nmov ecx, [rsp+68h+var_64]\ntest ecx, ecx\njz loc_1778\ntest r12d, r12d\njz loc_1778\nmov rdi, [rsp+68h+var_60]\nmov r9d, [r13+0]\nxor ecx, ecx\nxor r15d, r15d\nmov qword ptr [r14+4], 0\nmov r8d, 1\nmov r11d, 1\nxor ebx, ebx\nmov eax, [rdi]\nmov [rsp+68h+var_3C], r9d\nadd eax, r9d\nmov [r14], eax\nmov rax, rdi\nmov edi, r12d\nmov r12d, ecx\nmov rcx, rbp\nmov rbp, r13\nmov r13, r8\nmov r8d, edi\nnop word ptr [rax+rax+00h]\nloc_1670:\nmovsxd rdx, r12d\nmovsxd r9, r15d\nmovd xmm0, dword ptr [rax+rdx*4]\nmovd xmm2, dword ptr [rbp+r9*4+0]\nlea rsi, ds:0[rdx*4]\nlea rdx, ds:0[r9*4]\nmov r9, [rcx+r13*8-8]\nmovdqa xmm1, xmm0\npunpckldq xmm1, xmm2\nmovq qword ptr [r9], xmm1\nlea r9d, [r15+1]\ncmp r9d, r8d\njl loc_17A0\nloc_16B1:\ntest r15d, r15d\njnz short loc_16C7\nmov edi, [rsp+68h+var_64]\nadd r12d, 1\ncmp r12d, edi\njl loc_1830\nloc_16C7:\ntest ebx, ebx\nsetnz dl\ncmp [rsp+68h+var_68], r13d\njle loc_18C0\nloc_16D6:\ntest dl, dl\njz loc_18C0\nmov r12d, [r14+4]\nmov r15d, [r14+8]\nxor esi, esi\ncmp ebx, 1\njz short loc_1739\nmovsxd rdx, ebx\nmov rdi, r14\nmov [rsp+68h+var_40], r8d\nlea rdx, [rdx+rdx*2]\nmov [rsp+68h+var_50], rax\nlea rdx, [r14+rdx*4]\nmov [rsp+68h+var_58], rcx\nmov rsi, [rdx-0Ch]\nmov [r14], rsi\nmov edx, [rdx-4]\nlea esi, [rbx-1]\nmov dword ptr [rsp+68h+var_60], esi\nmov [r14+8], edx\nxor edx, edx\ncall sub_13B0\nmov r8d, [rsp+68h+var_40]\nmov rax, [rsp+68h+var_50]\nmov rcx, [rsp+68h+var_58]\nmov esi, dword ptr [rsp+68h+var_60]\nloc_1739:\nmov r11d, ebx\nadd r13, 1\nmov ebx, esi\njmp loc_1670\nloc_1750:\nmov edx, [rsp+68h+var_68]\ntest r12d, r12d\nsetz al\ntest edx, edx\nsetz dl\nor al, dl\njnz short loc_1778\nmov eax, [rsp+68h+var_64]\nxor r8d, r8d\ntest eax, eax\njnz loc_18C6\nnop dword ptr [rax+00000000h]\nloc_1778:\nmov rax, [rsp+68h+var_48]\nmov rdi, r14; ptr\nmov dword ptr [rax], 0\ncall _free\nloc_178B:\nadd rsp, 38h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_17A0:\nmovd edi, xmm0\nadd edi, [rbp+rdx+4]\nmovsxd rdx, ebx\nlea r10, [rdx+rdx*2]\nlea r10, [r14+r10*4]\nmov [r10], edi\nmov [r10+4], r12d\nmov [r10+8], r9d\ntest ebx, ebx\njz short loc_1820\nmov [rsp+68h+var_60], rsi\nmov [rsp+68h+var_58], rax\njmp short loc_17F1\nloc_17D0:\nmov rax, [rdx]\nmov r10, [rsi]\nmov edi, [rsi+8]\nmov [rsi], rax\nmov eax, [rdx+8]\nmov [rsi+8], eax\nmov [rdx], r10\nmov [rdx+8], edi\ntest ebx, ebx\njz short loc_1816\nmov edi, [rsi]\nmov rdx, r9\nloc_17F1:\nsub ebx, 1\nlea rdx, [rdx+rdx*2]\nmov esi, ebx\nlea rdx, [r14+rdx*4]\nshr esi, 1Fh\nadd esi, ebx\nmov ebx, esi\nsar ebx, 1\nmovsxd r9, ebx\nlea rsi, [r9+r9*2]\nlea rsi, [r14+rsi*4]\ncmp [rsi], edi\njg short loc_17D0\nloc_1816:\nmov rsi, [rsp+68h+var_60]\nmov rax, [rsp+68h+var_58]\nloc_1820:\nmov ebx, r11d\njmp loc_16B1\nloc_1830:\nmovsxd rdx, ebx\nmov r9d, [rsp+68h+var_3C]\nadd r9d, [rax+rsi+4]\nlea edi, [rbx+1]\nlea rsi, [rdx+rdx*2]\nlea rsi, [r14+rsi*4]\nmov [rsi], r9d\nmov [rsi+4], r12d\nmov dword ptr [rsi+8], 0\ntest ebx, ebx\njnz short loc_1886\njmp short loc_18AC\nloc_1860:\nmov r12, [rdx]\nmov r11, [rsi]\nmov r9d, [rsi+8]\nmov [rsi], r12\nmov r12d, [rdx+8]\nmov [rsi+8], r12d\nmov [rdx], r11\nmov [rdx+8], r9d\ntest ebx, ebx\njz short loc_18AC\nmov r9d, [rsi]\nmov rdx, r10\nloc_1886:\nsub ebx, 1\nlea rdx, [rdx+rdx*2]\nmov esi, ebx\nlea rdx, [r14+rdx*4]\nshr esi, 1Fh\nadd esi, ebx\nmov ebx, esi\nsar ebx, 1\nmovsxd r10, ebx\nlea rsi, [r10+r10*2]\nlea rsi, [r14+rsi*4]\ncmp [rsi], r9d\njg short loc_1860\nloc_18AC:\nmov ebx, edi\nmov edx, 1\ncmp [rsp+68h+var_68], r13d\njg loc_16D6\nnop dword ptr [rax]\nloc_18C0:\nmov r8, r13\nmov rbp, rcx\nloc_18C6:\nmov rax, [rsp+68h+var_48]\nmov rdi, r14; ptr\nmov [rax], r8d\ncall _free\njmp loc_178B", + "ida_strip_pseudo": "char *__fastcall sub_1590(_DWORD *a1, int a2, _DWORD *a3, int a4, int a5, _DWORD *a6)\n{\n size_t v8; // rbx\n _DWORD *v9; // r14\n char *v10; // rbp\n char *v11; // rbx\n char *v12; // r15\n int v13; // r9d\n int v14; // r15d\n int v15; // r11d\n int v16; // ebx\n _DWORD *v17; // rax\n int v18; // edi\n int v19; // r12d\n char *v20; // rcx\n _DWORD *v21; // rbp\n __int64 v22; // r13\n int v23; // r8d\n __m128i v24; // xmm0\n __int64 v25; // rsi\n int v26; // r12d\n bool v27; // dl\n int v28; // esi\n _DWORD *v29; // rdx\n int v30; // r8d\n int v32; // edi\n __int64 v33; // rdx\n int *v34; // r10\n __int64 v35; // r10\n int v36; // edi\n _DWORD *v37; // rdx\n int *v38; // rsi\n __int64 v39; // rdx\n int v40; // r9d\n int v41; // edi\n _DWORD *v42; // rsi\n __int64 v43; // r11\n int v44; // r9d\n _DWORD *v45; // rdx\n _DWORD *v46; // rsi\n char *v49; // [rsp+10h] [rbp-58h]\n _DWORD *v50; // [rsp+18h] [rbp-50h]\n int v52; // [rsp+28h] [rbp-40h]\n int v53; // [rsp+2Ch] [rbp-3Ch]\n\n v8 = 8LL * a5;\n v9 = malloc(12LL * a4 * a2);\n v10 = (char *)malloc(v8);\n v11 = &v10[v8];\n v12 = v10;\n if ( a5 <= 0 )\n {\n if ( a5 != 0 && a4 != 0 )\n {\n v30 = 0;\n if ( a2 )\n {\nLABEL_32:\n *a6 = v30;\n free(v9);\n return v10;\n }\n }\n }\n else\n {\n do\n {\n v12 += 8;\n *((_QWORD *)v12 - 1) = malloc(8uLL);\n }\n while ( v12 != v11 );\n if ( a2 && a4 )\n {\n v13 = *a3;\n v14 = 0;\n *(_QWORD *)(v9 + 1) = 0LL;\n v15 = 1;\n v16 = 0;\n v53 = v13;\n *v9 = v13 + *a1;\n v17 = a1;\n v18 = a4;\n v19 = 0;\n v20 = v10;\n v21 = a3;\n v22 = 1LL;\n v23 = v18;\n while ( 1 )\n {\n v24 = _mm_cvtsi32_si128(v17[v19]);\n v25 = v19;\n **(_QWORD **)&v20[8 * v22 - 8] = _mm_unpacklo_epi32(v24, _mm_cvtsi32_si128(v21[v14])).m128i_u64[0];\n if ( v14 + 1 < v23 )\n {\n v32 = v21[v14 + 1] + _mm_cvtsi128_si32(v24);\n v33 = v16;\n v34 = &v9[3 * v16];\n *v34 = v32;\n v34[1] = v19;\n v34[2] = v14 + 1;\n if ( v16 )\n {\n while ( 1 )\n {\n v37 = &v9[3 * v33];\n v16 = (v16 - 1) / 2;\n v38 = &v9[3 * v16];\n if ( *v38 <= v32 )\n break;\n v35 = *(_QWORD *)v38;\n v36 = v38[2];\n *(_QWORD *)v38 = *(_QWORD *)v37;\n v38[2] = v37[2];\n *(_QWORD *)v37 = v35;\n v37[2] = v36;\n if ( !v16 )\n break;\n v32 = *v38;\n v33 = v16;\n }\n v25 = v19;\n }\n v16 = v15;\n }\n if ( v14 || (v26 = v19 + 1, v26 >= a2) )\n {\n v27 = v16 != 0;\n if ( a5 <= (int)v22 )\n goto LABEL_31;\n }\n else\n {\n v39 = v16;\n v40 = v17[v25 + 1] + v53;\n v41 = v16 + 1;\n v42 = &v9[3 * v16];\n *v42 = v40;\n v42[1] = v26;\n v42[2] = 0;\n if ( v16 )\n {\n while ( 1 )\n {\n v45 = &v9[3 * v39];\n v16 = (v16 - 1) / 2;\n v46 = &v9[3 * v16];\n if ( *v46 <= v40 )\n break;\n v43 = *(_QWORD *)v46;\n v44 = v46[2];\n *(_QWORD *)v46 = *(_QWORD *)v45;\n v46[2] = v45[2];\n *(_QWORD *)v45 = v43;\n v45[2] = v44;\n if ( !v16 )\n break;\n v40 = *v46;\n v39 = v16;\n }\n }\n v16 = v41;\n v27 = 1;\n if ( a5 <= (int)v22 )\n {\nLABEL_31:\n v30 = v22;\n v10 = v20;\n goto LABEL_32;\n }\n }\n if ( !v27 )\n goto LABEL_31;\n v19 = v9[1];\n v14 = v9[2];\n v28 = 0;\n if ( v16 != 1 )\n {\n v52 = v23;\n v50 = v17;\n v29 = &v9[3 * v16];\n v49 = v20;\n *(_QWORD *)v9 = *(_QWORD *)(v29 - 3);\n v9[2] = *(v29 - 1);\n sub_13B0(v9, (unsigned int)(v16 - 1), 0LL);\n v23 = v52;\n v17 = v50;\n v20 = v49;\n v28 = v16 - 1;\n }\n v15 = v16;\n ++v22;\n v16 = v28;\n }\n }\n }\n *a6 = 0;\n free(v9);\n return v10;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1590(uint32_t *a1, int a2, uint32_t *a3, int a4, int a5,\n uint32_t *a6) {\n unsigned int v8;\n uint32_t *v9;\n char *v10;\n char *v11;\n char *v12;\n int v13;\n int v14;\n int v15;\n int v16;\n uint32_t *v17;\n int v18;\n int v19;\n char *v20;\n uint32_t *v21;\n long long v22;\n int v23;\n __m128i v24;\n long long v25;\n int v26;\n bool v27;\n int v28;\n uint32_t *v29;\n int v30;\n int v32;\n long long v33;\n int *v34;\n long long v35;\n int v36;\n uint32_t *v37;\n int *v38;\n long long v39;\n int v40;\n int v41;\n uint32_t *v42;\n long long v43;\n int v44;\n uint32_t *v45;\n uint32_t *v46;\n char *v49;\n uint32_t *v50;\n int v52;\n int v53;\n v8 = 8LL * a5;\n v9 = malloc(12LL * a4 * a2);\n v10 = (char *)malloc(v8);\n v11 = &v10[v8];\n v12 = v10;\n if (a5 <= 0) {\n if (a5 != 0 && a4 != 0) {\n v30 = 0;\n if (a2) {\n LABEL_32:\n *a6 = v30;\n free(v9);\n return v10;\n }\n }\n } else {\n do {\n v12 += 8;\n *((uint64_t *)v12 - 1) = malloc(8uLL);\n } while (v12 != v11);\n if (a2 && a4) {\n v13 = *a3;\n v14 = 0;\n *(uint64_t *)(v9 + 1) = 0LL;\n v15 = 1;\n v16 = 0;\n v53 = v13;\n *v9 = v13 + *a1;\n v17 = a1;\n v18 = a4;\n v19 = 0;\n v20 = v10;\n v21 = a3;\n v22 = 1LL;\n v23 = v18;\n while (1) {\n v24 = _mm_cvtsi32_si128(v17[v19]);\n v25 = v19;\n **(uint64_t **)&v20[8 * v22 - 8] =\n _mm_unpacklo_epi32(v24, _mm_cvtsi32_si128(v21[v14])).m128i_u64[0];\n if (v14 + 1 < v23) {\n v32 = v21[v14 + 1] + _mm_cvtsi128_si32(v24);\n v33 = v16;\n v34 = &v9[3 * v16];\n *v34 = v32;\n v34[1] = v19;\n v34[2] = v14 + 1;\n if (v16) {\n while (1) {\n v37 = &v9[3 * v33];\n v16 = (v16 - 1) / 2;\n v38 = &v9[3 * v16];\n if (*v38 <= v32) break;\n v35 = *(uint64_t *)v38;\n v36 = v38[2];\n *(uint64_t *)v38 = *(uint64_t *)v37;\n v38[2] = v37[2];\n *(uint64_t *)v37 = v35;\n v37[2] = v36;\n if (!v16) break;\n v32 = *v38;\n v33 = v16;\n }\n v25 = v19;\n }\n v16 = v15;\n }\n if (v14 || (v26 = v19 + 1, v26 >= a2)) {\n v27 = v16 != 0;\n if (a5 <= (int)v22) goto LABEL_31;\n } else {\n v39 = v16;\n v40 = v17[v25 + 1] + v53;\n v41 = v16 + 1;\n v42 = &v9[3 * v16];\n *v42 = v40;\n v42[1] = v26;\n v42[2] = 0;\n if (v16) {\n while (1) {\n v45 = &v9[3 * v39];\n v16 = (v16 - 1) / 2;\n v46 = &v9[3 * v16];\n if (*v46 <= v40) break;\n v43 = *(uint64_t *)v46;\n v44 = v46[2];\n *(uint64_t *)v46 = *(uint64_t *)v45;\n v46[2] = v45[2];\n *(uint64_t *)v45 = v43;\n v45[2] = v44;\n if (!v16) break;\n v40 = *v46;\n v39 = v16;\n }\n }\n v16 = v41;\n v27 = 1;\n if (a5 <= (int)v22) {\n LABEL_31:\n v30 = v22;\n v10 = v20;\n goto LABEL_32;\n }\n }\n if (!v27) goto LABEL_31;\n v19 = v9[1];\n v14 = v9[2];\n v28 = 0;\n if (v16 != 1) {\n v52 = v23;\n v50 = v17;\n v29 = &v9[3 * v16];\n v49 = v20;\n *(uint64_t *)v9 = *(uint64_t *)(v29 - 3);\n v9[2] = *(v29 - 1);\n sub_13B0(v9, (unsigned int)(v16 - 1), 0LL);\n v23 = v52;\n v17 = v50;\n v20 = v49;\n v28 = v16 - 1;\n }\n v15 = v16;\n ++v22;\n v16 = v28;\n }\n }\n }\n *a6 = 0;\n free(v9);\n return v10;\n}", + "ida_pseudo_norm": "char *func0(uint32_t *a1, int a2, uint32_t *a3, int a4, int a5, uint32_t *a6) {\n unsigned int v8;\n uint32_t *v9;\n char *v10;\n char *v11;\n char *v12;\n int v13;\n int v14;\n int v15;\n int v16;\n uint32_t *v17;\n int v18;\n int v19;\n char *v20;\n uint32_t *v21;\n long long v22;\n int v23;\n __m128i v24;\n long long v25;\n int v26;\n bool v27;\n int v28;\n uint32_t *v29;\n int v30;\n int v32;\n long long v33;\n int *v34;\n long long v35;\n int v36;\n uint32_t *v37;\n int *v38;\n long long v39;\n int v40;\n int v41;\n uint32_t *v42;\n long long v43;\n int v44;\n uint32_t *v45;\n uint32_t *v46;\n char *v49;\n uint32_t *v50;\n int v52;\n int v53;\n v8 = 8LL * a5;\n v9 = malloc(12LL * a4 * a2);\n v10 = (char *)malloc(v8);\n v11 = &v10[v8];\n v12 = v10;\n if (a5 <= 0) {\n if (a5 != 0 && a4 != 0) {\n v30 = 0;\n if (a2) {\n LABEL_32:\n *a6 = v30;\n free(v9);\n return v10;\n }\n }\n } else {\n do {\n v12 += 8;\n *((uint64_t *)v12 - 1) = malloc(8uLL);\n } while (v12 != v11);\n if (a2 && a4) {\n v13 = *a3;\n v14 = 0;\n *(uint64_t *)(v9 + 1) = 0LL;\n v15 = 1;\n v16 = 0;\n v53 = v13;\n *v9 = v13 + *a1;\n v17 = a1;\n v18 = a4;\n v19 = 0;\n v20 = v10;\n v21 = a3;\n v22 = 1LL;\n v23 = v18;\n while (1) {\n v24 = _mm_cvtsi32_si128(v17[v19]);\n v25 = v19;\n **(uint64_t **)&v20[8 * v22 - 8] =\n _mm_unpacklo_epi32(v24, _mm_cvtsi32_si128(v21[v14])).m128i_u64[0];\n if (v14 + 1 < v23) {\n v32 = v21[v14 + 1] + _mm_cvtsi128_si32(v24);\n v33 = v16;\n v34 = &v9[3 * v16];\n *v34 = v32;\n v34[1] = v19;\n v34[2] = v14 + 1;\n if (v16) {\n while (1) {\n v37 = &v9[3 * v33];\n v16 = (v16 - 1) / 2;\n v38 = &v9[3 * v16];\n if (*v38 <= v32) break;\n v35 = *(uint64_t *)v38;\n v36 = v38[2];\n *(uint64_t *)v38 = *(uint64_t *)v37;\n v38[2] = v37[2];\n *(uint64_t *)v37 = v35;\n v37[2] = v36;\n if (!v16) break;\n v32 = *v38;\n v33 = v16;\n }\n v25 = v19;\n }\n v16 = v15;\n }\n if (v14 || (v26 = v19 + 1, v26 >= a2)) {\n v27 = v16 != 0;\n if (a5 <= (int)v22) goto LABEL_31;\n } else {\n v39 = v16;\n v40 = v17[v25 + 1] + v53;\n v41 = v16 + 1;\n v42 = &v9[3 * v16];\n *v42 = v40;\n v42[1] = v26;\n v42[2] = 0;\n if (v16) {\n while (1) {\n v45 = &v9[3 * v39];\n v16 = (v16 - 1) / 2;\n v46 = &v9[3 * v16];\n if (*v46 <= v40) break;\n v43 = *(uint64_t *)v46;\n v44 = v46[2];\n *(uint64_t *)v46 = *(uint64_t *)v45;\n v46[2] = v45[2];\n *(uint64_t *)v45 = v43;\n v45[2] = v44;\n if (!v16) break;\n v40 = *v46;\n v39 = v16;\n }\n }\n v16 = v41;\n v27 = 1;\n if (a5 <= (int)v22) {\n LABEL_31:\n v30 = v22;\n v10 = v20;\n goto LABEL_32;\n }\n }\n if (!v27) goto LABEL_31;\n v19 = v9[1];\n v14 = v9[2];\n v28 = 0;\n if (v16 != 1) {\n v52 = v23;\n v50 = v17;\n v29 = &v9[3 * v16];\n v49 = v20;\n *(uint64_t *)v9 = *(uint64_t *)(v29 - 3);\n v9[2] = *(v29 - 1);\n heapify(v9, (unsigned int)(v16 - 1), 0LL);\n v23 = v52;\n v17 = v50;\n v20 = v49;\n v28 = v16 - 1;\n }\n v15 = v16;\n ++v22;\n v16 = v28;\n }\n }\n }\n *a6 = 0;\n free(v9);\n return v10;\n}" + }, + { + "index": 409, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int list1[][2], int length) {\n int result_min = abs(list1[0][0] * list1[0][1]);\n for (int i = 1; i < length; i++) {\n int product = abs(list1[i][0] * list1[i][1]);\n if (product < result_min) {\n result_min = product;\n }\n }\n return result_min;\n}", + "test": "int main() {\n\n int list1[][2] = {{2, 7}, {2, 6}, {1, 8}, {4, 9}};\n\n int list2[][2] = {{10, 20}, {15, 2}, {5, 10}};\n\n int list3[][2] = {{11, 44}, {10, 15}, {20, 5}, {12, 9}};\n\n\n\n assert(func0(list1, 4) == 8);\n\n assert(func0(list2, 3) == 30);\n\n assert(func0(list3, 4) == 100);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov -0x18(%rbp),%rax\nmov (%rax),%edx\nmov -0x18(%rbp),%rax\nmov 0x4(%rax),%eax\nimul %eax,%edx\nmov %edx,%eax\nsar $0x1f,%eax\nxor %eax,%edx\nmov %edx,-0xc(%rbp)\nsub %eax,-0xc(%rbp)\nmovl $0x1,-0x8(%rbp)\njmp 11ed \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov 0x4(%rax),%eax\nimul %eax,%edx\nmov %edx,%eax\nsar $0x1f,%eax\nxor %eax,%edx\nmov %edx,-0x4(%rbp)\nsub %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0xc(%rbp),%eax\njge 11e9 \nmov -0x4(%rbp),%eax\nmov %eax,-0xc(%rbp)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 119e \nmov -0xc(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov rax, [rbp+var_18]\nmov edx, [rax]\nmov rax, [rbp+var_18]\nmov eax, [rax+4]\nimul eax, edx\nmov edx, eax\nneg edx\ncmovns eax, edx\nmov [rbp+var_C], eax\nmov [rbp+var_8], 1\njmp short loc_11E7\nloc_119B:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax+4]\nimul eax, edx\nmov edx, eax\nneg edx\ncmovns eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_C]\njge short loc_11E3\nmov eax, [rbp+var_4]\nmov [rbp+var_C], eax\nloc_11E3:\nadd [rbp+var_8], 1\nloc_11E7:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_119B\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n int v2; // eax\n int v3; // eax\n int v5; // [rsp+10h] [rbp-Ch]\n int i; // [rsp+14h] [rbp-8h]\n\n v2 = *a1 * a1[1];\n if ( v2 <= 0 )\n v2 = -(*a1 * a1[1]);\n v5 = v2;\n for ( i = 1; i < a2; ++i )\n {\n v3 = a1[2 * i] * a1[2 * i + 1];\n if ( v3 <= 0 )\n v3 = -v3;\n if ( v3 < v5 )\n v5 = v3;\n }\n return (unsigned int)v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov rax, [rbp+var_18]\nmov edx, [rax]\nmov rax, [rbp+var_18]\nmov eax, [rax+4]\nimul eax, edx\nmov edx, eax\nneg edx\ncmovns eax, edx\nmov [rbp+var_C], eax\nmov [rbp+var_8], 1\njmp short loc_11E7\nloc_119B:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax+4]\nimul eax, edx\nmov edx, eax\nneg edx\ncmovns eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_C]\njge short loc_11E3\nmov eax, [rbp+var_4]\nmov [rbp+var_C], eax\nloc_11E3:\nadd [rbp+var_8], 1\nloc_11E7:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_119B\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2)\n{\n int v2; // eax\n int v3; // eax\n int v5; // [rsp+10h] [rbp-Ch]\n int i; // [rsp+14h] [rbp-8h]\n\n v2 = *a1 * a1[1];\n if ( v2 <= 0 )\n v2 = -(*a1 * a1[1]);\n v5 = v2;\n for ( i = 1; i < a2; ++i )\n {\n v3 = a1[2 * i] * a1[2 * i + 1];\n if ( v3 <= 0 )\n v3 = -v3;\n if ( v3 < v5 )\n v5 = v3;\n }\n return (unsigned int)v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2) {\n int v2;\n int v3;\n int v5;\n int i;\n v2 = *a1 * a1[1];\n if (v2 <= 0) v2 = -(*a1 * a1[1]);\n v5 = v2;\n for (i = 1; i < a2; ++i) {\n v3 = a1[2 * i] * a1[2 * i + 1];\n if (v3 <= 0) v3 = -v3;\n if (v3 < v5) v5 = v3;\n }\n return (unsigned int)v5;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n int v2;\n int v3;\n int v5;\n int i;\n v2 = *a1 * a1[1];\n if (v2 <= 0) v2 = -(*a1 * a1[1]);\n v5 = v2;\n for (i = 1; i < a2; ++i) {\n v3 = a1[2 * i] * a1[2 * i + 1];\n if (v3 <= 0) v3 = -v3;\n if (v3 < v5) v5 = v3;\n }\n return (unsigned int)v5;\n}" + }, + { + "index": 409, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int list1[][2], int length) {\n int result_min = abs(list1[0][0] * list1[0][1]);\n for (int i = 1; i < length; i++) {\n int product = abs(list1[i][0] * list1[i][1]);\n if (product < result_min) {\n result_min = product;\n }\n }\n return result_min;\n}", + "test": "int main() {\n\n int list1[][2] = {{2, 7}, {2, 6}, {1, 8}, {4, 9}};\n\n int list2[][2] = {{10, 20}, {15, 2}, {5, 10}};\n\n int list3[][2] = {{11, 44}, {10, 15}, {20, 5}, {12, 9}};\n\n\n\n assert(func0(list1, 4) == 8);\n\n assert(func0(list2, 3) == 30);\n\n assert(func0(list3, 4) == 100);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov (%rdi),%eax\nimul 0x4(%rdi),%eax\ncltd\nxor %edx,%eax\nsub %edx,%eax\ncmp $0x1,%esi\njle 11a6 \nlea 0x8(%rdi),%rcx\nlea -0x2(%rsi),%edx\nlea 0x10(%rdi,%rdx,8),%rdi\nmov (%rcx),%edx\nimul 0x4(%rcx),%edx\nmov %edx,%esi\nsar $0x1f,%esi\nxor %esi,%edx\nsub %esi,%edx\ncmp %edx,%eax\ncmovg %edx,%eax\nadd $0x8,%rcx\ncmp %rdi,%rcx\njne 1189 \nretq\n", + "ida_asm": "func0:\nendbr64\nmov eax, [rdi]\nimul eax, [rdi+4]\nmov r8d, eax\nneg r8d\ncmovs r8d, eax\ncmp esi, 1\njle short loc_11AB\nlea rdx, [rdi+8]\nlea eax, [rsi-2]\nlea rsi, [rdi+rax*8+10h]\nloc_118E:\nmov eax, [rdx]\nimul eax, [rdx+4]\nmov ecx, eax\nneg ecx\ncmovns eax, ecx\ncmp r8d, eax\ncmovg r8d, eax\nadd rdx, 8\ncmp rdx, rsi\njnz short loc_118E\nloc_11AB:\nmov eax, r8d\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n int v2; // r8d\n _DWORD *v3; // rdx\n __int64 v4; // rsi\n int v5; // eax\n\n v2 = -(a1[1] * *a1);\n if ( a1[1] * *a1 > 0 )\n v2 = a1[1] * *a1;\n if ( a2 > 1 )\n {\n v3 = a1 + 2;\n v4 = (__int64)&a1[2 * (a2 - 2) + 4];\n do\n {\n v5 = v3[1] * *v3;\n if ( v5 <= 0 )\n v5 = -(v3[1] * *v3);\n if ( v2 > v5 )\n v2 = v5;\n v3 += 2;\n }\n while ( v3 != (_DWORD *)v4 );\n }\n return (unsigned int)v2;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov eax, [rdi]\nimul eax, [rdi+4]\nmov r8d, eax\nneg r8d\ncmovs r8d, eax\ncmp esi, 1\njle short loc_11AB\nlea rdx, [rdi+8]\nlea eax, [rsi-2]\nlea rsi, [rdi+rax*8+10h]\nloc_118E:\nmov eax, [rdx]\nimul eax, [rdx+4]\nmov ecx, eax\nneg ecx\ncmovns eax, ecx\ncmp r8d, eax\ncmovg r8d, eax\nadd rdx, 8\ncmp rdx, rsi\njnz short loc_118E\nloc_11AB:\nmov eax, r8d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2)\n{\n int v2; // r8d\n _DWORD *v3; // rdx\n __int64 v4; // rsi\n int v5; // eax\n\n v2 = -(a1[1] * *a1);\n if ( a1[1] * *a1 > 0 )\n v2 = a1[1] * *a1;\n if ( a2 > 1 )\n {\n v3 = a1 + 2;\n v4 = (__int64)&a1[2 * (a2 - 2) + 4];\n do\n {\n v5 = v3[1] * *v3;\n if ( v5 <= 0 )\n v5 = -(v3[1] * *v3);\n if ( v2 > v5 )\n v2 = v5;\n v3 += 2;\n }\n while ( v3 != (_DWORD *)v4 );\n }\n return (unsigned int)v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2) {\n int v2;\n uint32_t *v3;\n long long v4;\n int v5;\n v2 = -(a1[1] * *a1);\n if (a1[1] * *a1 > 0) v2 = a1[1] * *a1;\n if (a2 > 1) {\n v3 = a1 + 2;\n v4 = (long long)&a1[2 * (a2 - 2) + 4];\n do {\n v5 = v3[1] * *v3;\n if (v5 <= 0) v5 = -(v3[1] * *v3);\n if (v2 > v5) v2 = v5;\n v3 += 2;\n } while (v3 != (uint32_t *)v4);\n }\n return (unsigned int)v2;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n int v2;\n uint32_t *v3;\n long long v4;\n int v5;\n v2 = -(a1[1] * *a1);\n if (a1[1] * *a1 > 0) v2 = a1[1] * *a1;\n if (a2 > 1) {\n v3 = a1 + 2;\n v4 = (long long)&a1[2 * (a2 - 2) + 4];\n do {\n v5 = v3[1] * *v3;\n if (v5 <= 0) v5 = -(v3[1] * *v3);\n if (v2 > v5) v2 = v5;\n v3 += 2;\n } while (v3 != (uint32_t *)v4);\n }\n return (unsigned int)v2;\n}" + }, + { + "index": 409, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int list1[][2], int length) {\n int result_min = abs(list1[0][0] * list1[0][1]);\n for (int i = 1; i < length; i++) {\n int product = abs(list1[i][0] * list1[i][1]);\n if (product < result_min) {\n result_min = product;\n }\n }\n return result_min;\n}", + "test": "int main() {\n\n int list1[][2] = {{2, 7}, {2, 6}, {1, 8}, {4, 9}};\n\n int list2[][2] = {{10, 20}, {15, 2}, {5, 10}};\n\n int list3[][2] = {{11, 44}, {10, 15}, {20, 5}, {12, 9}};\n\n\n\n assert(func0(list1, 4) == 8);\n\n assert(func0(list2, 3) == 30);\n\n assert(func0(list3, 4) == 100);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov (%rdi),%eax\nimul 0x4(%rdi),%eax\ncltd\nxor %edx,%eax\nsub %edx,%eax\ncmp $0x1,%esi\njle 117d \nlea -0x2(%rsi),%edx\nlea 0x8(%rdi),%rcx\nlea 0x10(%rdi,%rdx,8),%rdi\nmov (%rcx),%edx\nimul 0x4(%rcx),%edx\nmov %edx,%esi\nsar $0x1f,%esi\nxor %esi,%edx\nsub %esi,%edx\ncmp %edx,%eax\ncmovg %edx,%eax\nadd $0x8,%rcx\ncmp %rdi,%rcx\njne 1160 \nretq\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\nmov eax, [rdi]\nimul eax, [rdi+4]\nmov r8d, eax\nneg r8d\ncmovs r8d, eax\ncmp esi, 1\njle short loc_12D5\nlea eax, [rsi-2]\nlea rdx, [rdi+8]\nlea rsi, [rdi+rax*8+10h]\nnop dword ptr [rax]\nloc_12B8:\nmov eax, [rdx]\nimul eax, [rdx+4]\nmov ecx, eax\nneg ecx\ncmovns eax, ecx\ncmp r8d, eax\ncmovg r8d, eax\nadd rdx, 8\ncmp rdx, rsi\njnz short loc_12B8\nloc_12D5:\nmov eax, r8d\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n int v2; // r8d\n _DWORD *v3; // rdx\n __int64 v4; // rsi\n int v5; // eax\n\n v2 = -(a1[1] * *a1);\n if ( a1[1] * *a1 > 0 )\n v2 = a1[1] * *a1;\n if ( a2 > 1 )\n {\n v3 = a1 + 2;\n v4 = (__int64)&a1[2 * (a2 - 2) + 4];\n do\n {\n v5 = v3[1] * *v3;\n if ( v5 <= 0 )\n v5 = -(v3[1] * *v3);\n if ( v2 > v5 )\n v2 = v5;\n v3 += 2;\n }\n while ( v3 != (_DWORD *)v4 );\n }\n return (unsigned int)v2;\n}", + "ida_strip_asm": "sub_1290:\nendbr64\nmov eax, [rdi]\nimul eax, [rdi+4]\nmov r8d, eax\nneg r8d\ncmovs r8d, eax\ncmp esi, 1\njle short loc_12D5\nlea eax, [rsi-2]\nlea rdx, [rdi+8]\nlea rsi, [rdi+rax*8+10h]\nnop dword ptr [rax]\nloc_12B8:\nmov eax, [rdx]\nimul eax, [rdx+4]\nmov ecx, eax\nneg ecx\ncmovns eax, ecx\ncmp r8d, eax\ncmovg r8d, eax\nadd rdx, 8\ncmp rdx, rsi\njnz short loc_12B8\nloc_12D5:\nmov eax, r8d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1290(_DWORD *a1, int a2)\n{\n int v2; // r8d\n _DWORD *v3; // rdx\n __int64 v4; // rsi\n int v5; // eax\n\n v2 = -(a1[1] * *a1);\n if ( a1[1] * *a1 > 0 )\n v2 = a1[1] * *a1;\n if ( a2 > 1 )\n {\n v3 = a1 + 2;\n v4 = (__int64)&a1[2 * (a2 - 2) + 4];\n do\n {\n v5 = v3[1] * *v3;\n if ( v5 <= 0 )\n v5 = -(v3[1] * *v3);\n if ( v2 > v5 )\n v2 = v5;\n v3 += 2;\n }\n while ( v3 != (_DWORD *)v4 );\n }\n return (unsigned int)v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1290(uint32_t *a1, int a2) {\n int v2;\n uint32_t *v3;\n long long v4;\n int v5;\n v2 = -(a1[1] * *a1);\n if (a1[1] * *a1 > 0) v2 = a1[1] * *a1;\n if (a2 > 1) {\n v3 = a1 + 2;\n v4 = (long long)&a1[2 * (a2 - 2) + 4];\n do {\n v5 = v3[1] * *v3;\n if (v5 <= 0) v5 = -(v3[1] * *v3);\n if (v2 > v5) v2 = v5;\n v3 += 2;\n } while (v3 != (uint32_t *)v4);\n }\n return (unsigned int)v2;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n int v2;\n uint32_t *v3;\n long long v4;\n int v5;\n v2 = -(a1[1] * *a1);\n if (a1[1] * *a1 > 0) v2 = a1[1] * *a1;\n if (a2 > 1) {\n v3 = a1 + 2;\n v4 = (long long)&a1[2 * (a2 - 2) + 4];\n do {\n v5 = v3[1] * *v3;\n if (v5 <= 0) v5 = -(v3[1] * *v3);\n if (v2 > v5) v2 = v5;\n v3 += 2;\n } while (v3 != (uint32_t *)v4);\n }\n return (unsigned int)v2;\n}" + }, + { + "index": 410, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char *listval[], int size) {\n int min_val = INT_MAX;\n int current_val;\n for (int i = 0; i < size; i++) {\n if (sscanf(listval[i], \"%d\", ¤t_val)) {\n if (current_val < min_val) {\n min_val = current_val;\n }\n }\n }\n return min_val;\n}", + "test": "int main() {\n\n char *list1[] = {\"Python\", \"3\", \"2\", \"4\", \"5\", \"version\"};\n\n assert(func0(list1, 6) == 2);\n\n\n\n char *list2[] = {\"Python\", \"15\", \"20\", \"25\"};\n\n assert(func0(list2, 4) == 15);\n\n \n\n char *list3[] = {\"Python\", \"30\", \"20\", \"40\", \"50\", \"version\"};\n\n assert(func0(list3, 6) == 20);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovl $0x7fffffff,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 1200 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nlea -0x14(%rbp),%rdx\nlea 0xe2b(%rip),%rsi\nmov %rax,%rdi\nmov $0x0,%eax\ncallq 1090 <__isoc99_sscanf@plt>\ntest %eax,%eax\nje 11fc \nmov -0x14(%rbp),%eax\ncmp %eax,-0x10(%rbp)\njle 11fc \nmov -0x14(%rbp),%eax\nmov %eax,-0x10(%rbp)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 11bb \nmov -0x10(%rbp),%eax\nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 121f \ncallq 1070 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_10], 7FFFFFFFh\nmov [rbp+var_C], 0\njmp short loc_1203\nloc_11BB:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nlea rdx, [rbp+var_14]\nlea rcx, unk_2008\nmov rsi, rcx\nmov rdi, rax\nmov eax, 0\ncall ___isoc99_sscanf\ntest eax, eax\njz short loc_11FF\nmov eax, [rbp+var_14]\ncmp [rbp+var_10], eax\njle short loc_11FF\nmov eax, [rbp+var_14]\nmov [rbp+var_10], eax\nloc_11FF:\nadd [rbp+var_C], 1\nloc_1203:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_2C]\njl short loc_11BB\nmov eax, [rbp+var_10]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1222\ncall ___stack_chk_fail\nlocret_1222:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int v3; // [rsp+1Ch] [rbp-14h] BYREF\n int v4; // [rsp+20h] [rbp-10h]\n int i; // [rsp+24h] [rbp-Ch]\n unsigned __int64 v6; // [rsp+28h] [rbp-8h]\n\n v6 = __readfsqword(0x28u);\n v4 = 0x7FFFFFFF;\n for ( i = 0; i < a2; ++i )\n {\n if ( (unsigned int)__isoc99_sscanf(*(_QWORD *)(8LL * i + a1), &unk_2008, &v3) && v4 > v3 )\n v4 = v3;\n }\n return (unsigned int)v4;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_10], 7FFFFFFFh\nmov [rbp+var_C], 0\njmp short loc_1203\nloc_11BB:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nlea rdx, [rbp+var_14]\nlea rcx, unk_2008\nmov rsi, rcx\nmov rdi, rax\nmov eax, 0\ncall ___isoc99_sscanf\ntest eax, eax\njz short loc_11FF\nmov eax, [rbp+var_14]\ncmp [rbp+var_10], eax\njle short loc_11FF\nmov eax, [rbp+var_14]\nmov [rbp+var_10], eax\nloc_11FF:\nadd [rbp+var_C], 1\nloc_1203:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_2C]\njl short loc_11BB\nmov eax, [rbp+var_10]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1222\ncall ___stack_chk_fail\nlocret_1222:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2)\n{\n int v3; // [rsp+1Ch] [rbp-14h] BYREF\n int v4; // [rsp+20h] [rbp-10h]\n int i; // [rsp+24h] [rbp-Ch]\n unsigned __int64 v6; // [rsp+28h] [rbp-8h]\n\n v6 = __readfsqword(0x28u);\n v4 = 0x7FFFFFFF;\n for ( i = 0; i < a2; ++i )\n {\n if ( (unsigned int)__isoc99_sscanf(*(_QWORD *)(8LL * i + a1), &unk_2008, &v3) && v4 > v3 )\n v4 = v3;\n }\n return (unsigned int)v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2) {\n int v3;\n int v4;\n int i;\n unsigned long long v6;\n v6 = __readfsqword(40u);\n v4 = 2147483647;\n for (i = 0; i < a2; ++i) {\n if ((unsigned int)__isoc99_sscanf(*(uint64_t *)(8LL * i + a1), &unk_2008,\n &v3) &&\n v4 > v3)\n v4 = v3;\n }\n return (unsigned int)v4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int v3;\n int v4;\n int i;\n unsigned long long v6;\n v6 = __readfsqword(40u);\n v4 = 2147483647;\n for (i = 0; i < a2; ++i) {\n if ((unsigned int)__isoc99_sscanf(*(uint64_t *)(8LL * i + a1), &unk_2008,\n &v3) &&\n v4 > v3)\n v4 = v3;\n }\n return (unsigned int)v4;\n}" + }, + { + "index": 410, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char *listval[], int size) {\n int min_val = INT_MAX;\n int current_val;\n for (int i = 0; i < size; i++) {\n if (sscanf(listval[i], \"%d\", ¤t_val)) {\n if (current_val < min_val) {\n min_val = current_val;\n }\n }\n }\n return min_val;\n}", + "test": "int main() {\n\n char *list1[] = {\"Python\", \"3\", \"2\", \"4\", \"5\", \"version\"};\n\n assert(func0(list1, 6) == 2);\n\n\n\n char *list2[] = {\"Python\", \"15\", \"20\", \"25\"};\n\n assert(func0(list2, 4) == 15);\n\n \n\n char *list3[] = {\"Python\", \"30\", \"20\", \"40\", \"50\", \"version\"};\n\n assert(func0(list3, 6) == 20);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x8(%rsp)\nxor %eax,%eax\ntest %esi,%esi\njle 11f1 \nmov %rdi,%rbx\nlea -0x1(%rsi),%eax\nlea 0x8(%rdi,%rax,8),%r13\nmov $0x7fffffff,%ebp\nlea 0x4(%rsp),%r12\njmp 11cb \nadd $0x8,%rbx\ncmp %r13,%rbx\nje 11f6 \nmov %r12,%rdx\nlea 0xe2f(%rip),%rsi\nmov (%rbx),%rdi\nmov $0x0,%eax\ncallq 1090 <__isoc99_sscanf@plt>\ntest %eax,%eax\nje 11c2 \nmov 0x4(%rsp),%eax\ncmp %eax,%ebp\ncmovg %eax,%ebp\njmp 11c2 \nmov $0x7fffffff,%ebp\nmov 0x8(%rsp),%rax\nxor %fs:0x28,%rax\njne 1213 \nmov %ebp,%eax\nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\ncallq 1070 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov rax, fs:28h\nmov [rsp+38h+var_30], rax\nxor eax, eax\ntest esi, esi\njle short loc_11F0\nmov rbx, rdi\nmovsxd rsi, esi\nlea r13, [rdi+rsi*8]\nmov ebp, 7FFFFFFFh\nlea r12, unk_2004\njmp short loc_11CC\nloc_11C3:\nadd rbx, 8\ncmp rbx, r13\njz short loc_11F5\nloc_11CC:\nlea rdx, [rsp+38h+var_34]\nmov rdi, [rbx]\nmov rsi, r12\nmov eax, 0\ncall ___isoc99_sscanf\ntest eax, eax\njz short loc_11C3\nmov eax, [rsp+38h+var_34]\ncmp ebp, eax\ncmovg ebp, eax\njmp short loc_11C3\nloc_11F0:\nmov ebp, 7FFFFFFFh\nloc_11F5:\nmov rax, [rsp+38h+var_30]\nsub rax, fs:28h\njnz short loc_1212\nmov eax, ebp\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1212:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(_QWORD *a1, int a2)\n{\n _QWORD *v2; // rbx\n int v3; // ebp\n int v5; // [rsp+4h] [rbp-34h] BYREF\n unsigned __int64 v6; // [rsp+8h] [rbp-30h]\n\n v6 = __readfsqword(0x28u);\n if ( a2 <= 0 )\n {\n return 0x7FFFFFFF;\n }\n else\n {\n v2 = a1;\n v3 = 0x7FFFFFFF;\n do\n {\n if ( (unsigned int)__isoc99_sscanf(*v2, &unk_2004, &v5) && v3 > v5 )\n v3 = v5;\n ++v2;\n }\n while ( v2 != &a1[a2] );\n }\n return (unsigned int)v3;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov rax, fs:28h\nmov [rsp+38h+var_30], rax\nxor eax, eax\ntest esi, esi\njle short loc_11F0\nmov rbx, rdi\nmovsxd rsi, esi\nlea r13, [rdi+rsi*8]\nmov ebp, 7FFFFFFFh\nlea r12, unk_2004\njmp short loc_11CC\nloc_11C3:\nadd rbx, 8\ncmp rbx, r13\njz short loc_11F5\nloc_11CC:\nlea rdx, [rsp+38h+var_34]\nmov rdi, [rbx]\nmov rsi, r12\nmov eax, 0\ncall ___isoc99_sscanf\ntest eax, eax\njz short loc_11C3\nmov eax, [rsp+38h+var_34]\ncmp ebp, eax\ncmovg ebp, eax\njmp short loc_11C3\nloc_11F0:\nmov ebp, 7FFFFFFFh\nloc_11F5:\nmov rax, [rsp+38h+var_30]\nsub rax, fs:28h\njnz short loc_1212\nmov eax, ebp\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1212:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(_QWORD *a1, int a2)\n{\n _QWORD *v2; // rbx\n int v3; // ebp\n int v5; // [rsp+4h] [rbp-34h] BYREF\n unsigned __int64 v6; // [rsp+8h] [rbp-30h]\n\n v6 = __readfsqword(0x28u);\n if ( a2 <= 0 )\n {\n return 0x7FFFFFFF;\n }\n else\n {\n v2 = a1;\n v3 = 0x7FFFFFFF;\n do\n {\n if ( (unsigned int)__isoc99_sscanf(*v2, &unk_2004, &v5) && v3 > v5 )\n v3 = v5;\n ++v2;\n }\n while ( v2 != &a1[a2] );\n }\n return (unsigned int)v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(uint64_t *a1, int a2) {\n uint64_t *v2;\n int v3;\n int v5;\n unsigned long long v6;\n v6 = __readfsqword(40u);\n if (a2 <= 0) {\n return 2147483647;\n } else {\n v2 = a1;\n v3 = 2147483647;\n do {\n if ((unsigned int)__isoc99_sscanf(*v2, &unk_2004, &v5) && v3 > v5)\n v3 = v5;\n ++v2;\n } while (v2 != &a1[a2]);\n }\n return (unsigned int)v3;\n}", + "ida_pseudo_norm": "long long func0(uint64_t *a1, int a2) {\n uint64_t *v2;\n int v3;\n int v5;\n unsigned long long v6;\n v6 = __readfsqword(40u);\n if (a2 <= 0) {\n return 2147483647;\n } else {\n v2 = a1;\n v3 = 2147483647;\n do {\n if ((unsigned int)__isoc99_sscanf(*v2, &unk_2004, &v5) && v3 > v5)\n v3 = v5;\n ++v2;\n } while (v2 != &a1[a2]);\n }\n return (unsigned int)v3;\n}" + }, + { + "index": 410, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char *listval[], int size) {\n int min_val = INT_MAX;\n int current_val;\n for (int i = 0; i < size; i++) {\n if (sscanf(listval[i], \"%d\", ¤t_val)) {\n if (current_val < min_val) {\n min_val = current_val;\n }\n }\n }\n return min_val;\n}", + "test": "int main() {\n\n char *list1[] = {\"Python\", \"3\", \"2\", \"4\", \"5\", \"version\"};\n\n assert(func0(list1, 6) == 2);\n\n\n\n char *list2[] = {\"Python\", \"15\", \"20\", \"25\"};\n\n assert(func0(list2, 4) == 15);\n\n \n\n char *list3[] = {\"Python\", \"30\", \"20\", \"40\", \"50\", \"version\"};\n\n assert(func0(list3, 6) == 20);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x8(%rsp)\nxor %eax,%eax\ntest %esi,%esi\njle 13b0 \nlea -0x1(%rsi),%eax\nmov %rdi,%rbx\nmov $0x7fffffff,%r12d\nlea 0x8(%rdi,%rax,8),%r14\nlea 0x4(%rsp),%r13\nlea 0xca3(%rip),%rbp\nnopl 0x0(%rax)\nmov (%rbx),%rdi\nxor %eax,%eax\nmov %r13,%rdx\nmov %rbp,%rsi\ncallq 1090 <__isoc99_sscanf@plt>\ntest %eax,%eax\nje 1387 \nmov 0x4(%rsp),%eax\ncmp %eax,%r12d\ncmovg %eax,%r12d\nadd $0x8,%rbx\ncmp %r14,%rbx\njne 1368 \nmov 0x8(%rsp),%rax\nxor %fs:0x28,%rax\njne 13b8 \nadd $0x10,%rsp\nmov %r12d,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nmov $0x7fffffff,%r12d\njmp 1390 \ncallq 1070 <__stack_chk_fail@plt>\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 10h\nmov rax, fs:28h\nmov [rsp+38h+var_30], rax\nxor eax, eax\ntest esi, esi\njle short loc_1428\nmovsxd rsi, esi\nmov rbx, rdi\nlea r13, [rsp+38h+var_34]\nmov ebp, 7FFFFFFFh\nlea r14, [rdi+rsi*8]\nlea r12, unk_2004\nnop\nloc_13E0:\nmov rdi, [rbx]\nxor eax, eax\nmov rdx, r13\nmov rsi, r12\ncall ___isoc99_sscanf\ntest eax, eax\njz short loc_13FD\nmov eax, [rsp+38h+var_34]\ncmp ebp, eax\ncmovg ebp, eax\nloc_13FD:\nadd rbx, 8\ncmp rbx, r14\njnz short loc_13E0\nloc_1406:\nmov rax, [rsp+38h+var_30]\nsub rax, fs:28h\njnz short loc_142F\nadd rsp, 10h\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1428:\nmov ebp, 7FFFFFFFh\njmp short loc_1406\nloc_142F:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(_QWORD *a1, int a2)\n{\n _QWORD *v2; // rbx\n int v3; // ebp\n int v5; // [rsp+4h] [rbp-34h] BYREF\n unsigned __int64 v6; // [rsp+8h] [rbp-30h]\n\n v6 = __readfsqword(0x28u);\n if ( a2 <= 0 )\n {\n return 0x7FFFFFFF;\n }\n else\n {\n v2 = a1;\n v3 = 0x7FFFFFFF;\n do\n {\n if ( (unsigned int)__isoc99_sscanf(*v2, &unk_2004, &v5) && v3 > v5 )\n v3 = v5;\n ++v2;\n }\n while ( v2 != &a1[a2] );\n }\n return (unsigned int)v3;\n}", + "ida_strip_asm": "sub_13A0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 10h\nmov rax, fs:28h\nmov [rsp+38h+var_30], rax\nxor eax, eax\ntest esi, esi\njle short loc_1428\nmovsxd rsi, esi\nmov rbx, rdi\nlea r13, [rsp+38h+var_34]\nmov ebp, 7FFFFFFFh\nlea r14, [rdi+rsi*8]\nlea r12, unk_2004\nnop\nloc_13E0:\nmov rdi, [rbx]\nxor eax, eax\nmov rdx, r13\nmov rsi, r12\ncall ___isoc99_sscanf\ntest eax, eax\njz short loc_13FD\nmov eax, [rsp+38h+var_34]\ncmp ebp, eax\ncmovg ebp, eax\nloc_13FD:\nadd rbx, 8\ncmp rbx, r14\njnz short loc_13E0\nloc_1406:\nmov rax, [rsp+38h+var_30]\nsub rax, fs:28h\njnz short loc_142F\nadd rsp, 10h\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1428:\nmov ebp, 7FFFFFFFh\njmp short loc_1406\nloc_142F:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_13A0(_QWORD *a1, int a2)\n{\n _QWORD *v2; // rbx\n int v3; // ebp\n int v5; // [rsp+4h] [rbp-34h] BYREF\n unsigned __int64 v6; // [rsp+8h] [rbp-30h]\n\n v6 = __readfsqword(0x28u);\n if ( a2 <= 0 )\n {\n return 0x7FFFFFFF;\n }\n else\n {\n v2 = a1;\n v3 = 0x7FFFFFFF;\n do\n {\n if ( (unsigned int)__isoc99_sscanf(*v2, &unk_2004, &v5) && v3 > v5 )\n v3 = v5;\n ++v2;\n }\n while ( v2 != &a1[a2] );\n }\n return (unsigned int)v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_13A0(uint64_t *a1, int a2) {\n uint64_t *v2;\n int v3;\n int v5;\n unsigned long long v6;\n v6 = __readfsqword(40u);\n if (a2 <= 0) {\n return 2147483647;\n } else {\n v2 = a1;\n v3 = 2147483647;\n do {\n if ((unsigned int)__isoc99_sscanf(*v2, &unk_2004, &v5) && v3 > v5)\n v3 = v5;\n ++v2;\n } while (v2 != &a1[a2]);\n }\n return (unsigned int)v3;\n}", + "ida_pseudo_norm": "long long func0(uint64_t *a1, int a2) {\n uint64_t *v2;\n int v3;\n int v5;\n unsigned long long v6;\n v6 = __readfsqword(40u);\n if (a2 <= 0) {\n return 2147483647;\n } else {\n v2 = a1;\n v3 = 2147483647;\n do {\n if ((unsigned int)__isoc99_sscanf(*v2, &unk_2004, &v5) && v3 > v5)\n v3 = v5;\n ++v2;\n } while (v2 != &a1[a2]);\n }\n return (unsigned int)v3;\n}" + }, + { + "index": 410, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char *listval[], int size) {\n int min_val = INT_MAX;\n int current_val;\n for (int i = 0; i < size; i++) {\n if (sscanf(listval[i], \"%d\", ¤t_val)) {\n if (current_val < min_val) {\n min_val = current_val;\n }\n }\n }\n return min_val;\n}", + "test": "int main() {\n\n char *list1[] = {\"Python\", \"3\", \"2\", \"4\", \"5\", \"version\"};\n\n assert(func0(list1, 6) == 2);\n\n\n\n char *list2[] = {\"Python\", \"15\", \"20\", \"25\"};\n\n assert(func0(list2, 4) == 15);\n\n \n\n char *list3[] = {\"Python\", \"30\", \"20\", \"40\", \"50\", \"version\"};\n\n assert(func0(list3, 6) == 20);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x8(%rsp)\nxor %eax,%eax\ntest %esi,%esi\njle 13e0 \nlea -0x1(%rsi),%eax\nmov %rdi,%rbx\nmov $0x7fffffff,%r12d\nlea 0x8(%rdi,%rax,8),%r14\nlea 0x4(%rsp),%r13\nlea 0xc73(%rip),%rbp\nnopl 0x0(%rax)\nmov (%rbx),%rdi\nxor %eax,%eax\nmov %r13,%rdx\nmov %rbp,%rsi\ncallq 1090 <__isoc99_sscanf@plt>\ntest %eax,%eax\nje 13b7 \nmov 0x4(%rsp),%eax\ncmp %eax,%r12d\ncmovg %eax,%r12d\nadd $0x8,%rbx\ncmp %r14,%rbx\njne 1398 \nmov 0x8(%rsp),%rax\nxor %fs:0x28,%rax\njne 13e8 \nadd $0x10,%rsp\nmov %r12d,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nmov $0x7fffffff,%r12d\njmp 13c0 \ncallq 1070 <__stack_chk_fail@plt>\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 10h\nmov rax, fs:28h\nmov [rsp+38h+var_30], rax\nxor eax, eax\ntest esi, esi\njle short loc_1428\nmovsxd rsi, esi\nmov rbx, rdi\nlea r13, [rsp+38h+var_34]\nmov ebp, 7FFFFFFFh\nlea r14, [rdi+rsi*8]\nlea r12, unk_2004\nnop\nloc_13E0:\nmov rdi, [rbx]\nxor eax, eax\nmov rdx, r13\nmov rsi, r12\ncall ___isoc99_sscanf\ntest eax, eax\njz short loc_13FD\nmov eax, [rsp+38h+var_34]\ncmp ebp, eax\ncmovg ebp, eax\nloc_13FD:\nadd rbx, 8\ncmp rbx, r14\njnz short loc_13E0\nloc_1406:\nmov rax, [rsp+38h+var_30]\nsub rax, fs:28h\njnz short loc_142F\nadd rsp, 10h\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1428:\nmov ebp, 7FFFFFFFh\njmp short loc_1406\nloc_142F:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(_QWORD *a1, int a2)\n{\n _QWORD *v2; // rbx\n int v3; // ebp\n int v5; // [rsp+4h] [rbp-34h] BYREF\n unsigned __int64 v6; // [rsp+8h] [rbp-30h]\n\n v6 = __readfsqword(0x28u);\n if ( a2 <= 0 )\n {\n return 0x7FFFFFFF;\n }\n else\n {\n v2 = a1;\n v3 = 0x7FFFFFFF;\n do\n {\n if ( (unsigned int)__isoc99_sscanf(*v2, &unk_2004, &v5) && v3 > v5 )\n v3 = v5;\n ++v2;\n }\n while ( v2 != &a1[a2] );\n }\n return (unsigned int)v3;\n}", + "ida_strip_asm": "sub_13A0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 10h\nmov rax, fs:28h\nmov [rsp+38h+var_30], rax\nxor eax, eax\ntest esi, esi\njle short loc_1428\nmovsxd rsi, esi\nmov rbx, rdi\nlea r13, [rsp+38h+var_34]\nmov ebp, 7FFFFFFFh\nlea r14, [rdi+rsi*8]\nlea r12, unk_2004\nnop\nloc_13E0:\nmov rdi, [rbx]\nxor eax, eax\nmov rdx, r13\nmov rsi, r12\ncall ___isoc99_sscanf\ntest eax, eax\njz short loc_13FD\nmov eax, [rsp+38h+var_34]\ncmp ebp, eax\ncmovg ebp, eax\nloc_13FD:\nadd rbx, 8\ncmp rbx, r14\njnz short loc_13E0\nloc_1406:\nmov rax, [rsp+38h+var_30]\nsub rax, fs:28h\njnz short loc_142F\nadd rsp, 10h\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1428:\nmov ebp, 7FFFFFFFh\njmp short loc_1406\nloc_142F:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_13A0(_QWORD *a1, int a2)\n{\n _QWORD *v2; // rbx\n int v3; // ebp\n int v5; // [rsp+4h] [rbp-34h] BYREF\n unsigned __int64 v6; // [rsp+8h] [rbp-30h]\n\n v6 = __readfsqword(0x28u);\n if ( a2 <= 0 )\n {\n return 0x7FFFFFFF;\n }\n else\n {\n v2 = a1;\n v3 = 0x7FFFFFFF;\n do\n {\n if ( (unsigned int)__isoc99_sscanf(*v2, &unk_2004, &v5) && v3 > v5 )\n v3 = v5;\n ++v2;\n }\n while ( v2 != &a1[a2] );\n }\n return (unsigned int)v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_13A0(uint64_t *a1, int a2) {\n uint64_t *v2;\n int v3;\n int v5;\n unsigned long long v6;\n v6 = __readfsqword(40u);\n if (a2 <= 0) {\n return 2147483647;\n } else {\n v2 = a1;\n v3 = 2147483647;\n do {\n if ((unsigned int)__isoc99_sscanf(*v2, &unk_2004, &v5) && v3 > v5)\n v3 = v5;\n ++v2;\n } while (v2 != &a1[a2]);\n }\n return (unsigned int)v3;\n}", + "ida_pseudo_norm": "long long func0(uint64_t *a1, int a2) {\n uint64_t *v2;\n int v3;\n int v5;\n unsigned long long v6;\n v6 = __readfsqword(40u);\n if (a2 <= 0) {\n return 2147483647;\n } else {\n v2 = a1;\n v3 = 2147483647;\n do {\n if ((unsigned int)__isoc99_sscanf(*v2, &unk_2004, &v5) && v3 > v5)\n v3 = v5;\n ++v2;\n } while (v2 != &a1[a2]);\n }\n return (unsigned int)v3;\n}" + }, + { + "index": 411, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* word, char* result) {\n int index = 0, capitalize = 1;\n for (int i = 0; word[i] != '\\0'; i++) {\n if (word[i] == '_') {\n capitalize = 1;\n } else {\n if (capitalize) {\n result[index++] = toupper(word[i]);\n capitalize = 0;\n } else {\n result[index++] = word[i];\n }\n }\n }\n result[index] = '\\0';\n return result;\n}", + "test": "int main() {\n\n char result[100];\n\n\n\n assert(strcmp(func0(\"android_tv\", result), \"AndroidTv\") == 0);\n\n assert(strcmp(func0(\"google_pixel\", result), \"GooglePixel\") == 0);\n\n assert(strcmp(func0(\"apple_watch\", result), \"AppleWatch\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x1,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmpq 1260 \nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x5f,%al\njne 11f4 \nmovl $0x1,-0x8(%rbp)\njmp 125c \ncmpl $0x0,-0x8(%rbp)\nje 1236 \nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmovsbl %al,%eax\nmov %eax,%edi\ncallq 1080 \nmov %eax,%ecx\nmov -0xc(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0xc(%rbp)\nmovslq %eax,%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov %ecx,%edx\nmov %dl,(%rax)\nmovl $0x0,-0x8(%rbp)\njmp 125c \nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0xc(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0xc(%rbp)\nmovslq %eax,%rdx\nmov -0x20(%rbp),%rax\nadd %rax,%rdx\nmovzbl (%rcx),%eax\nmov %al,(%rdx)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 11d7 \nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmovb $0x0,(%rax)\nmov -0x20(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 1\nmov [rbp+var_4], 0\njmp loc_1260\nloc_11D7:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 5Fh ; '_'\njnz short loc_11F4\nmov [rbp+var_8], 1\njmp short loc_125C\nloc_11F4:\ncmp [rbp+var_8], 0\njz short loc_1236\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nmov edi, eax; c\ncall _toupper\nmov ecx, eax\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov edx, ecx\nmov [rax], dl\nmov [rbp+var_8], 0\njmp short loc_125C\nloc_1236:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_20]\nadd rdx, rax\nmovzx eax, byte ptr [rcx]\nmov [rdx], al\nloc_125C:\nadd [rbp+var_4], 1\nloc_1260:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_11D7\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+var_20]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2)\n{\n char v2; // cl\n int v3; // eax\n int v4; // eax\n int v6; // [rsp+14h] [rbp-Ch]\n int v7; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v6 = 0;\n v7 = 1;\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n {\n if ( *(_BYTE *)(i + a1) == 95 )\n {\n v7 = 1;\n }\n else if ( v7 )\n {\n v2 = toupper(*(char *)(i + a1));\n v3 = v6++;\n *(_BYTE *)(v3 + a2) = v2;\n v7 = 0;\n }\n else\n {\n v4 = v6++;\n *(_BYTE *)(a2 + v4) = *(_BYTE *)(i + a1);\n }\n }\n *(_BYTE *)(v6 + a2) = 0;\n return a2;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 1\nmov [rbp+var_4], 0\njmp loc_1260\nloc_11D7:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 5Fh ; '_'\njnz short loc_11F4\nmov [rbp+var_8], 1\njmp short loc_125C\nloc_11F4:\ncmp [rbp+var_8], 0\njz short loc_1236\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nmov edi, eax; c\ncall _toupper\nmov ecx, eax\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov edx, ecx\nmov [rax], dl\nmov [rbp+var_8], 0\njmp short loc_125C\nloc_1236:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_20]\nadd rdx, rax\nmovzx eax, byte ptr [rcx]\nmov [rdx], al\nloc_125C:\nadd [rbp+var_4], 1\nloc_1260:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_11D7\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+var_20]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(__int64 a1, __int64 a2)\n{\n char v2; // cl\n int v3; // eax\n int v4; // eax\n int v6; // [rsp+14h] [rbp-Ch]\n int v7; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v6 = 0;\n v7 = 1;\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n {\n if ( *(_BYTE *)(i + a1) == 95 )\n {\n v7 = 1;\n }\n else if ( v7 )\n {\n v2 = toupper(*(char *)(i + a1));\n v3 = v6++;\n *(_BYTE *)(v3 + a2) = v2;\n v7 = 0;\n }\n else\n {\n v4 = v6++;\n *(_BYTE *)(a2 + v4) = *(_BYTE *)(i + a1);\n }\n }\n *(_BYTE *)(v6 + a2) = 0;\n return a2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(long long a1, long long a2) {\n char v2;\n int v3;\n int v4;\n int v6;\n int v7;\n int i;\n v6 = 0;\n v7 = 1;\n for (i = 0; *(uint8_t *)(i + a1); ++i) {\n if (*(uint8_t *)(i + a1) == 95) {\n v7 = 1;\n } else if (v7) {\n v2 = toupper(*(char *)(i + a1));\n v3 = v6++;\n *(uint8_t *)(v3 + a2) = v2;\n v7 = 0;\n } else {\n v4 = v6++;\n *(uint8_t *)(a2 + v4) = *(uint8_t *)(i + a1);\n }\n }\n *(uint8_t *)(v6 + a2) = 0;\n return a2;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2) {\n char v2;\n int v3;\n int v4;\n int v6;\n int v7;\n int i;\n v6 = 0;\n v7 = 1;\n for (i = 0; *(uint8_t *)(i + a1); ++i) {\n if (*(uint8_t *)(i + a1) == 95) {\n v7 = 1;\n } else if (v7) {\n v2 = toupper(*(char *)(i + a1));\n v3 = v6++;\n *(uint8_t *)(v3 + a2) = v2;\n v7 = 0;\n } else {\n v4 = v6++;\n *(uint8_t *)(a2 + v4) = *(uint8_t *)(i + a1);\n }\n }\n *(uint8_t *)(v6 + a2) = 0;\n return a2;\n}" + }, + { + "index": 411, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* word, char* result) {\n int index = 0, capitalize = 1;\n for (int i = 0; word[i] != '\\0'; i++) {\n if (word[i] == '_') {\n capitalize = 1;\n } else {\n if (capitalize) {\n result[index++] = toupper(word[i]);\n capitalize = 0;\n } else {\n result[index++] = word[i];\n }\n }\n }\n result[index] = '\\0';\n return result;\n}", + "test": "int main() {\n\n char result[100];\n\n\n\n assert(strcmp(func0(\"android_tv\", result), \"AndroidTv\") == 0);\n\n assert(strcmp(func0(\"google_pixel\", result), \"GooglePixel\") == 0);\n\n assert(strcmp(func0(\"apple_watch\", result), \"AppleWatch\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rsi,%r13\nmovzbl (%rdi),%ebx\ntest %bl,%bl\nje 120d \nlea 0x1(%rdi),%rbp\nmov $0x1,%eax\nmov $0x0,%r12d\nmov $0x1,%r14d\nmov $0x0,%r15d\njmp 11e0 \nmovslq %r12d,%rdx\nmov %bl,0x0(%r13,%rdx,1)\nlea 0x1(%r12),%r12d\njmp 11d4 \nmov %r14d,%eax\nadd $0x1,%rbp\nmovzbl -0x1(%rbp),%ebx\ntest %bl,%bl\nje 1213 \ncmp $0x5f,%bl\nje 11d1 \ntest %eax,%eax\nje 11c2 \ncallq 1070 <__ctype_toupper_loc@plt>\nmov %rax,%rdx\nmovslq %r12d,%rax\nmovsbq %bl,%rbx\nmov (%rdx),%rdx\nmov (%rdx,%rbx,4),%edx\nmov %dl,0x0(%r13,%rax,1)\nlea 0x1(%r12),%r12d\nmov %r15d,%eax\njmp 11d4 \nmov $0x0,%r12d\nmovslq %r12d,%r12\nmovb $0x0,0x0(%r13,%r12,1)\nmov %r13,%rax\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r13, rsi\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_122D\nlea rbp, [rdi+1]\nmov eax, 1\nmov r12d, 0\nmov r14d, 1\nmov r15d, 0\njmp short loc_1200\nloc_11E2:\nmovsxd rdx, r12d\nmov [r13+rdx+0], bl\nlea r12d, [r12+1]\njmp short loc_11F4\nloc_11F1:\nmov eax, r14d\nloc_11F4:\nadd rbp, 1\nmovzx ebx, byte ptr [rbp-1]\ntest bl, bl\njz short loc_1233\nloc_1200:\ncmp bl, 5Fh ; '_'\njz short loc_11F1\ntest eax, eax\njz short loc_11E2\ncall ___ctype_toupper_loc\nmov rdx, rax\nmovsxd rax, r12d\nmovsx rbx, bl\nmov rdx, [rdx]\nmov edx, [rdx+rbx*4]\nmov [r13+rax+0], dl\nlea r12d, [r12+1]\nmov eax, r15d\njmp short loc_11F4\nloc_122D:\nmov r12d, 0\nloc_1233:\nmovsxd r12, r12d\nmov byte ptr [r13+r12+0], 0\nmov rax, r13\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "__int64 __fastcall func0(char *a1, __int64 a2)\n{\n char v2; // bl\n char *v3; // rbp\n int v4; // eax\n int v5; // r12d\n\n v2 = *a1;\n if ( *a1 )\n {\n v3 = a1 + 1;\n v4 = 1;\n v5 = 0;\n do\n {\n if ( v2 == 95 )\n {\n v4 = 1;\n }\n else if ( v4 )\n {\n *(_BYTE *)(a2 + v5++) = (*__ctype_toupper_loc())[v2];\n v4 = 0;\n }\n else\n {\n *(_BYTE *)(a2 + v5++) = v2;\n }\n v2 = *v3++;\n }\n while ( v2 );\n }\n else\n {\n v5 = 0;\n }\n *(_BYTE *)(a2 + v5) = 0;\n return a2;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r13, rsi\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_122D\nlea rbp, [rdi+1]\nmov eax, 1\nmov r12d, 0\nmov r14d, 1\nmov r15d, 0\njmp short loc_1200\nloc_11E2:\nmovsxd rdx, r12d\nmov [r13+rdx+0], bl\nlea r12d, [r12+1]\njmp short loc_11F4\nloc_11F1:\nmov eax, r14d\nloc_11F4:\nadd rbp, 1\nmovzx ebx, byte ptr [rbp-1]\ntest bl, bl\njz short loc_1233\nloc_1200:\ncmp bl, 5Fh ; '_'\njz short loc_11F1\ntest eax, eax\njz short loc_11E2\ncall ___ctype_toupper_loc\nmov rdx, rax\nmovsxd rax, r12d\nmovsx rbx, bl\nmov rdx, [rdx]\nmov edx, [rdx+rbx*4]\nmov [r13+rax+0], dl\nlea r12d, [r12+1]\nmov eax, r15d\njmp short loc_11F4\nloc_122D:\nmov r12d, 0\nloc_1233:\nmovsxd r12, r12d\nmov byte ptr [r13+r12+0], 0\nmov rax, r13\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(char *a1, __int64 a2)\n{\n char v2; // bl\n char *v3; // rbp\n int v4; // eax\n int v5; // r12d\n\n v2 = *a1;\n if ( *a1 )\n {\n v3 = a1 + 1;\n v4 = 1;\n v5 = 0;\n do\n {\n if ( v2 == 95 )\n {\n v4 = 1;\n }\n else if ( v4 )\n {\n *(_BYTE *)(a2 + v5++) = (*__ctype_toupper_loc())[v2];\n v4 = 0;\n }\n else\n {\n *(_BYTE *)(a2 + v5++) = v2;\n }\n v2 = *v3++;\n }\n while ( v2 );\n }\n else\n {\n v5 = 0;\n }\n *(_BYTE *)(a2 + v5) = 0;\n return a2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(char *a1, long long a2) {\n char v2;\n char *v3;\n int v4;\n int v5;\n v2 = *a1;\n if (*a1) {\n v3 = a1 + 1;\n v4 = 1;\n v5 = 0;\n do {\n if (v2 == 95) {\n v4 = 1;\n } else if (v4) {\n *(uint8_t *)(a2 + v5++) = (*__ctype_toupper_loc())[v2];\n v4 = 0;\n } else {\n *(uint8_t *)(a2 + v5++) = v2;\n }\n v2 = *v3++;\n } while (v2);\n } else {\n v5 = 0;\n }\n *(uint8_t *)(a2 + v5) = 0;\n return a2;\n}", + "ida_pseudo_norm": "long long func0(char *a1, long long a2) {\n char v2;\n char *v3;\n int v4;\n int v5;\n v2 = *a1;\n if (*a1) {\n v3 = a1 + 1;\n v4 = 1;\n v5 = 0;\n do {\n if (v2 == 95) {\n v4 = 1;\n } else if (v4) {\n *(uint8_t *)(a2 + v5++) = (*__ctype_toupper_loc())[v2];\n v4 = 0;\n } else {\n *(uint8_t *)(a2 + v5++) = v2;\n }\n v2 = *v3++;\n } while (v2);\n } else {\n v5 = 0;\n }\n *(uint8_t *)(a2 + v5) = 0;\n return a2;\n}" + }, + { + "index": 411, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* word, char* result) {\n int index = 0, capitalize = 1;\n for (int i = 0; word[i] != '\\0'; i++) {\n if (word[i] == '_') {\n capitalize = 1;\n } else {\n if (capitalize) {\n result[index++] = toupper(word[i]);\n capitalize = 0;\n } else {\n result[index++] = word[i];\n }\n }\n }\n result[index] = '\\0';\n return result;\n}", + "test": "int main() {\n\n char result[100];\n\n\n\n assert(strcmp(func0(\"android_tv\", result), \"AndroidTv\") == 0);\n\n assert(strcmp(func0(\"google_pixel\", result), \"GooglePixel\") == 0);\n\n assert(strcmp(func0(\"apple_watch\", result), \"AppleWatch\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\nmov %rsi,%r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmovsbq (%rdi),%rbx\ntest %bl,%bl\nje 1368 \nlea 0x1(%rdi),%rbp\nmov $0x1,%eax\nxor %r15d,%r15d\nxor %r13d,%r13d\njmp 1322 \nnopw 0x0(%rax,%rax,1)\nadd $0x1,%r15d\nmovslq %r15d,%r13\nlea (%r14,%r13,1),%rdx\ntest %eax,%eax\nje 1358 \nmov %rdx,0x8(%rsp)\ncallq 1070 <__ctype_toupper_loc@plt>\nmov 0x8(%rsp),%rdx\nmov (%rax),%rax\nmov (%rax,%rbx,4),%eax\nmov %al,(%r12)\nmov %rdx,%r12\nxor %eax,%eax\nmovsbq 0x0(%rbp),%rbx\nadd $0x1,%rbp\ntest %bl,%bl\nje 133d \nlea (%r14,%r13,1),%r12\ncmp $0x5f,%bl\njne 12e8 \nmovsbq 0x0(%rbp),%rbx\nadd $0x1,%rbp\nmov $0x1,%eax\ntest %bl,%bl\njne 1322 \nmovb $0x0,(%r12)\nadd $0x18,%rsp\nmov %r14,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\nmov %bl,(%r12)\nmov %rdx,%r12\njmp 1315 \nnopl 0x0(%rax)\nmov %rsi,%r12\njmp 133d \nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r13\nmov r13, rsi\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmovsx rbx, byte ptr [rdi]\ntest bl, bl\njz short loc_1340\nlea rbp, [rdi+1]\nmov eax, 1\nxor r12d, r12d\njmp short loc_130B\nloc_12E0:\ntest eax, eax\njz short loc_12F0\ncall ___ctype_toupper_loc\nmov rax, [rax]\nmovzx ebx, byte ptr [rax+rbx*4]\nloc_12F0:\nmovsxd rax, r12d\nadd rbp, 1\nadd r12d, 1\nmov [r13+rax+0], bl\nmovsx rbx, byte ptr [rbp-1]\nxor eax, eax\ntest bl, bl\njz short loc_1322\nloc_130B:\ncmp bl, 5Fh ; '_'\njnz short loc_12E0\nmovsx rbx, byte ptr [rbp+0]\nadd rbp, 1\nmov eax, 1\ntest bl, bl\njnz short loc_130B\nloc_1322:\nmovsxd r12, r12d\nadd r12, r13\nloc_1328:\nmov byte ptr [r12], 0\nadd rsp, 8\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1340:\nmov r12, rsi\njmp short loc_1328", + "ida_pseudo": "_BYTE *__fastcall func0(char *a1, _BYTE *a2)\n{\n __int64 v2; // rbx\n char *v3; // rbp\n int v4; // eax\n int v5; // r12d\n __int64 v6; // rax\n _BYTE *v7; // r12\n\n v2 = *a1;\n if ( (_BYTE)v2 )\n {\n v3 = a1 + 1;\n v4 = 1;\n v5 = 0;\n do\n {\n while ( (_BYTE)v2 == 95 )\n {\n v2 = *v3++;\n v4 = 1;\n if ( !(_BYTE)v2 )\n goto LABEL_8;\n }\n if ( v4 )\n LOBYTE(v2) = (*__ctype_toupper_loc())[v2];\n v6 = v5;\n ++v3;\n ++v5;\n a2[v6] = v2;\n v2 = *(v3 - 1);\n v4 = 0;\n }\n while ( (_BYTE)v2 );\nLABEL_8:\n v7 = &a2[v5];\n }\n else\n {\n v7 = a2;\n }\n *v7 = 0;\n return a2;\n}", + "ida_strip_asm": "sub_12B0:\nendbr64\npush r13\nmov r13, rsi\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmovsx rbx, byte ptr [rdi]\ntest bl, bl\njz short loc_1340\nlea rbp, [rdi+1]\nmov eax, 1\nxor r12d, r12d\njmp short loc_130B\nloc_12E0:\ntest eax, eax\njz short loc_12F0\ncall ___ctype_toupper_loc\nmov rax, [rax]\nmovzx ebx, byte ptr [rax+rbx*4]\nloc_12F0:\nmovsxd rax, r12d\nadd rbp, 1\nadd r12d, 1\nmov [r13+rax+0], bl\nmovsx rbx, byte ptr [rbp-1]\nxor eax, eax\ntest bl, bl\njz short loc_1322\nloc_130B:\ncmp bl, 5Fh ; '_'\njnz short loc_12E0\nmovsx rbx, byte ptr [rbp+0]\nadd rbp, 1\nmov eax, 1\ntest bl, bl\njnz short loc_130B\nloc_1322:\nmovsxd r12, r12d\nadd r12, r13\nloc_1328:\nmov byte ptr [r12], 0\nadd rsp, 8\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1340:\nmov r12, rsi\njmp short loc_1328", + "ida_strip_pseudo": "_BYTE *__fastcall sub_12B0(char *a1, _BYTE *a2)\n{\n __int64 v2; // rbx\n char *v3; // rbp\n int v4; // eax\n int v5; // r12d\n __int64 v6; // rax\n _BYTE *v7; // r12\n\n v2 = *a1;\n if ( (_BYTE)v2 )\n {\n v3 = a1 + 1;\n v4 = 1;\n v5 = 0;\n do\n {\n while ( (_BYTE)v2 == 95 )\n {\n v2 = *v3++;\n v4 = 1;\n if ( !(_BYTE)v2 )\n goto LABEL_8;\n }\n if ( v4 )\n LOBYTE(v2) = (*__ctype_toupper_loc())[v2];\n v6 = v5;\n ++v3;\n ++v5;\n a2[v6] = v2;\n v2 = *(v3 - 1);\n v4 = 0;\n }\n while ( (_BYTE)v2 );\nLABEL_8:\n v7 = &a2[v5];\n }\n else\n {\n v7 = a2;\n }\n *v7 = 0;\n return a2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_12B0(char *a1, uint8_t *a2) {\n long long v2;\n char *v3;\n int v4;\n int v5;\n long long v6;\n uint8_t *v7;\n v2 = *a1;\n if ((uint8_t)v2) {\n v3 = a1 + 1;\n v4 = 1;\n v5 = 0;\n do {\n while ((uint8_t)v2 == 95) {\n v2 = *v3++;\n v4 = 1;\n if (!(uint8_t)v2) goto LABEL_8;\n }\n if (v4) LOBYTE(v2) = (*__ctype_toupper_loc())[v2];\n v6 = v5;\n ++v3;\n ++v5;\n a2[v6] = v2;\n v2 = *(v3 - 1);\n v4 = 0;\n } while ((uint8_t)v2);\n LABEL_8:\n v7 = &a2[v5];\n } else {\n v7 = a2;\n }\n *v7 = 0;\n return a2;\n}", + "ida_pseudo_norm": "uint8_t *func0(char *a1, uint8_t *a2) {\n long long v2;\n char *v3;\n int v4;\n int v5;\n long long v6;\n uint8_t *v7;\n v2 = *a1;\n if ((uint8_t)v2) {\n v3 = a1 + 1;\n v4 = 1;\n v5 = 0;\n do {\n while ((uint8_t)v2 == 95) {\n v2 = *v3++;\n v4 = 1;\n if (!(uint8_t)v2) goto LABEL_8;\n }\n if (v4) LOBYTE(v2) = (*__ctype_toupper_loc())[v2];\n v6 = v5;\n ++v3;\n ++v5;\n a2[v6] = v2;\n v2 = *(v3 - 1);\n v4 = 0;\n } while ((uint8_t)v2);\n LABEL_8:\n v7 = &a2[v5];\n } else {\n v7 = a2;\n }\n *v7 = 0;\n return a2;\n}" + }, + { + "index": 411, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* word, char* result) {\n int index = 0, capitalize = 1;\n for (int i = 0; word[i] != '\\0'; i++) {\n if (word[i] == '_') {\n capitalize = 1;\n } else {\n if (capitalize) {\n result[index++] = toupper(word[i]);\n capitalize = 0;\n } else {\n result[index++] = word[i];\n }\n }\n }\n result[index] = '\\0';\n return result;\n}", + "test": "int main() {\n\n char result[100];\n\n\n\n assert(strcmp(func0(\"android_tv\", result), \"AndroidTv\") == 0);\n\n assert(strcmp(func0(\"google_pixel\", result), \"GooglePixel\") == 0);\n\n assert(strcmp(func0(\"apple_watch\", result), \"AppleWatch\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\nmov %rsi,%r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmovsbq (%rdi),%rbx\ntest %bl,%bl\nje 1368 \nlea 0x1(%rdi),%rbp\nmov $0x1,%eax\nxor %r15d,%r15d\nxor %r13d,%r13d\njmp 1322 \nnopw 0x0(%rax,%rax,1)\nadd $0x1,%r15d\nmovslq %r15d,%r13\nlea (%r14,%r13,1),%rdx\ntest %eax,%eax\nje 1358 \nmov %rdx,0x8(%rsp)\ncallq 1070 <__ctype_toupper_loc@plt>\nmov 0x8(%rsp),%rdx\nmov (%rax),%rax\nmov (%rax,%rbx,4),%eax\nmov %al,(%r12)\nmov %rdx,%r12\nxor %eax,%eax\nmovsbq 0x0(%rbp),%rbx\nadd $0x1,%rbp\ntest %bl,%bl\nje 133d \nlea (%r14,%r13,1),%r12\ncmp $0x5f,%bl\njne 12e8 \nmovsbq 0x0(%rbp),%rbx\nadd $0x1,%rbp\nmov $0x1,%eax\ntest %bl,%bl\njne 1322 \nmovb $0x0,(%r12)\nadd $0x18,%rsp\nmov %r14,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\nmov %bl,(%r12)\nmov %rdx,%r12\njmp 1315 \nnopl 0x0(%rax)\nmov %rsi,%r12\njmp 133d \nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r13\nmov r13, rsi\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmovsx rbx, byte ptr [rdi]\ntest bl, bl\njz short loc_1340\nlea rbp, [rdi+1]\nmov eax, 1\nxor r12d, r12d\njmp short loc_130B\nloc_12E0:\ntest eax, eax\njz short loc_12F0\ncall ___ctype_toupper_loc\nmov rax, [rax]\nmovzx ebx, byte ptr [rax+rbx*4]\nloc_12F0:\nmovsxd rax, r12d\nadd rbp, 1\nadd r12d, 1\nmov [r13+rax+0], bl\nmovsx rbx, byte ptr [rbp-1]\nxor eax, eax\ntest bl, bl\njz short loc_1322\nloc_130B:\ncmp bl, 5Fh ; '_'\njnz short loc_12E0\nmovsx rbx, byte ptr [rbp+0]\nadd rbp, 1\nmov eax, 1\ntest bl, bl\njnz short loc_130B\nloc_1322:\nmovsxd r12, r12d\nadd r12, r13\nloc_1328:\nmov byte ptr [r12], 0\nadd rsp, 8\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1340:\nmov r12, rsi\njmp short loc_1328", + "ida_pseudo": "_BYTE *__fastcall func0(char *a1, _BYTE *a2)\n{\n __int64 v2; // rbx\n char *v3; // rbp\n int v4; // eax\n int v5; // r12d\n __int64 v6; // rax\n _BYTE *v7; // r12\n\n v2 = *a1;\n if ( (_BYTE)v2 )\n {\n v3 = a1 + 1;\n v4 = 1;\n v5 = 0;\n do\n {\n while ( (_BYTE)v2 == 95 )\n {\n v2 = *v3++;\n v4 = 1;\n if ( !(_BYTE)v2 )\n goto LABEL_8;\n }\n if ( v4 )\n LOBYTE(v2) = (*__ctype_toupper_loc())[v2];\n v6 = v5;\n ++v3;\n ++v5;\n a2[v6] = v2;\n v2 = *(v3 - 1);\n v4 = 0;\n }\n while ( (_BYTE)v2 );\nLABEL_8:\n v7 = &a2[v5];\n }\n else\n {\n v7 = a2;\n }\n *v7 = 0;\n return a2;\n}", + "ida_strip_asm": "sub_12B0:\nendbr64\npush r13\nmov r13, rsi\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmovsx rbx, byte ptr [rdi]\ntest bl, bl\njz short loc_1340\nlea rbp, [rdi+1]\nmov eax, 1\nxor r12d, r12d\njmp short loc_130B\nloc_12E0:\ntest eax, eax\njz short loc_12F0\ncall ___ctype_toupper_loc\nmov rax, [rax]\nmovzx ebx, byte ptr [rax+rbx*4]\nloc_12F0:\nmovsxd rax, r12d\nadd rbp, 1\nadd r12d, 1\nmov [r13+rax+0], bl\nmovsx rbx, byte ptr [rbp-1]\nxor eax, eax\ntest bl, bl\njz short loc_1322\nloc_130B:\ncmp bl, 5Fh ; '_'\njnz short loc_12E0\nmovsx rbx, byte ptr [rbp+0]\nadd rbp, 1\nmov eax, 1\ntest bl, bl\njnz short loc_130B\nloc_1322:\nmovsxd r12, r12d\nadd r12, r13\nloc_1328:\nmov byte ptr [r12], 0\nadd rsp, 8\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1340:\nmov r12, rsi\njmp short loc_1328", + "ida_strip_pseudo": "_BYTE *__fastcall sub_12B0(char *a1, _BYTE *a2)\n{\n __int64 v2; // rbx\n char *v3; // rbp\n int v4; // eax\n int v5; // r12d\n __int64 v6; // rax\n _BYTE *v7; // r12\n\n v2 = *a1;\n if ( (_BYTE)v2 )\n {\n v3 = a1 + 1;\n v4 = 1;\n v5 = 0;\n do\n {\n while ( (_BYTE)v2 == 95 )\n {\n v2 = *v3++;\n v4 = 1;\n if ( !(_BYTE)v2 )\n goto LABEL_8;\n }\n if ( v4 )\n LOBYTE(v2) = (*__ctype_toupper_loc())[v2];\n v6 = v5;\n ++v3;\n ++v5;\n a2[v6] = v2;\n v2 = *(v3 - 1);\n v4 = 0;\n }\n while ( (_BYTE)v2 );\nLABEL_8:\n v7 = &a2[v5];\n }\n else\n {\n v7 = a2;\n }\n *v7 = 0;\n return a2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_12B0(char *a1, uint8_t *a2) {\n long long v2;\n char *v3;\n int v4;\n int v5;\n long long v6;\n uint8_t *v7;\n v2 = *a1;\n if ((uint8_t)v2) {\n v3 = a1 + 1;\n v4 = 1;\n v5 = 0;\n do {\n while ((uint8_t)v2 == 95) {\n v2 = *v3++;\n v4 = 1;\n if (!(uint8_t)v2) goto LABEL_8;\n }\n if (v4) LOBYTE(v2) = (*__ctype_toupper_loc())[v2];\n v6 = v5;\n ++v3;\n ++v5;\n a2[v6] = v2;\n v2 = *(v3 - 1);\n v4 = 0;\n } while ((uint8_t)v2);\n LABEL_8:\n v7 = &a2[v5];\n } else {\n v7 = a2;\n }\n *v7 = 0;\n return a2;\n}", + "ida_pseudo_norm": "uint8_t *func0(char *a1, uint8_t *a2) {\n long long v2;\n char *v3;\n int v4;\n int v5;\n long long v6;\n uint8_t *v7;\n v2 = *a1;\n if ((uint8_t)v2) {\n v3 = a1 + 1;\n v4 = 1;\n v5 = 0;\n do {\n while ((uint8_t)v2 == 95) {\n v2 = *v3++;\n v4 = 1;\n if (!(uint8_t)v2) goto LABEL_8;\n }\n if (v4) LOBYTE(v2) = (*__ctype_toupper_loc())[v2];\n v6 = v5;\n ++v3;\n ++v5;\n a2[v6] = v2;\n v2 = *(v3 - 1);\n v4 = 0;\n } while ((uint8_t)v2);\n LABEL_8:\n v7 = &a2[v5];\n } else {\n v7 = a2;\n }\n *v7 = 0;\n return a2;\n}" + }, + { + "index": 412, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nvoid remove_odd(int l[], int *size) {\n\n int write_index = 0;\n\n for (int i = 0; i < *size; ++i) {\n\n if (l[i] % 2 == 0) {\n\n l[write_index++] = l[i];\n\n }\n\n }\n\n *size = write_index;\n\n}\n\n\n\n", + "func": "bool func0(int arr1[], int size1, int arr2[], int size2) {\n if (size1 != size2) return false;\n for (int i = 0; i < size1; i++) {\n if (arr1[i] != arr2[i]) return false;\n }\n return true;\n}", + "test": "int main() {\n\n int l1[] = {1, 2, 3};\n\n int l2[] = {2, 4, 6};\n\n int l3[] = {10, 20, 3};\n\n int sizeL1 = 3, sizeL2 = 3, sizeL3 = 3;\n\n\n\n remove_odd(l1, &sizeL1);\n\n remove_odd(l2, &sizeL2);\n\n remove_odd(l3, &sizeL3);\n\n\n\n int expectedL1[] = {2};\n\n int expectedL2[] = {2, 4, 6};\n\n int expectedL3[] = {10, 20};\n\n\n\n assert(func0(l1, sizeL1, expectedL1, 1));\n\n assert(func0(l2, sizeL2, expectedL2, 3));\n\n assert(func0(l3, sizeL3, expectedL3, 2));\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %ecx,-0x20(%rbp)\nmov -0x1c(%rbp),%eax\ncmp -0x20(%rbp),%eax\nje 1219 \nmov $0x0,%eax\njmp 126a \nmovl $0x0,-0x4(%rbp)\njmp 125d \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\nje 1259 \nmov $0x0,%eax\njmp 126a \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1222 \nmov $0x1,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_20]\njz short loc_1219\nmov eax, 0\njmp short loc_126A\nloc_1219:\nmov [rbp+var_4], 0\njmp short loc_125D\nloc_1222:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_1259\nmov eax, 0\njmp short loc_126A\nloc_1259:\nadd [rbp+var_4], 1\nloc_125D:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1222\nmov eax, 1\nloc_126A:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3, int a4)\n{\n int i; // [rsp+24h] [rbp-4h]\n\n if ( a2 != a4 )\n return 0LL;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) != *(_DWORD *)(4LL * i + a3) )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_11F4:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_20]\njz short loc_1219\nmov eax, 0\njmp short loc_126A\nloc_1219:\nmov [rbp+var_4], 0\njmp short loc_125D\nloc_1222:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_1259\nmov eax, 0\njmp short loc_126A\nloc_1259:\nadd [rbp+var_4], 1\nloc_125D:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1222\nmov eax, 1\nloc_126A:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11F4(__int64 a1, int a2, __int64 a3, int a4)\n{\n int i; // [rsp+24h] [rbp-4h]\n\n if ( a2 != a4 )\n return 0LL;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) != *(_DWORD *)(4LL * i + a3) )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11F4(long long a1, int a2, long long a3, int a4) {\n int i;\n if (a2 != a4) return 0LL;\n for (i = 0; i < a2; ++i) {\n if (*(uint32_t *)(4LL * i + a1) != *(uint32_t *)(4LL * i + a3)) return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3, int a4) {\n int i;\n if (a2 != a4) return 0LL;\n for (i = 0; i < a2; ++i) {\n if (*(uint32_t *)(4LL * i + a1) != *(uint32_t *)(4LL * i + a3)) return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": 412, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nvoid remove_odd(int l[], int *size) {\n\n int write_index = 0;\n\n for (int i = 0; i < *size; ++i) {\n\n if (l[i] % 2 == 0) {\n\n l[write_index++] = l[i];\n\n }\n\n }\n\n *size = write_index;\n\n}\n\n\n\n", + "func": "bool func0(int arr1[], int size1, int arr2[], int size2) {\n if (size1 != size2) return false;\n for (int i = 0; i < size1; i++) {\n if (arr1[i] != arr2[i]) return false;\n }\n return true;\n}", + "test": "int main() {\n\n int l1[] = {1, 2, 3};\n\n int l2[] = {2, 4, 6};\n\n int l3[] = {10, 20, 3};\n\n int sizeL1 = 3, sizeL2 = 3, sizeL3 = 3;\n\n\n\n remove_odd(l1, &sizeL1);\n\n remove_odd(l2, &sizeL2);\n\n remove_odd(l3, &sizeL3);\n\n\n\n int expectedL1[] = {2};\n\n int expectedL2[] = {2, 4, 6};\n\n int expectedL3[] = {10, 20};\n\n\n\n assert(func0(l1, sizeL1, expectedL1, 1));\n\n assert(func0(l2, sizeL2, expectedL2, 3));\n\n assert(func0(l3, sizeL3, expectedL3, 2));\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x0,%eax\ncmp %ecx,%esi\njne 11e2 \ntest %esi,%esi\njle 11d7 \nlea -0x1(%rsi),%esi\nmov $0x0,%eax\njmp 11c0 \nmov %rcx,%rax\nmov (%rdx,%rax,4),%ecx\ncmp %ecx,(%rdi,%rax,4)\njne 11dd \nlea 0x1(%rax),%rcx\ncmp %rsi,%rax\njne 11bd \nmov $0x1,%eax\nretq\nmov $0x1,%eax\nretq\nmov $0x0,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov eax, 0\ncmp esi, ecx\njnz short locret_11E5\ntest esi, esi\njle short loc_11DA\nmovsxd rsi, esi\nlea rcx, ds:0[rsi*4]\nmov eax, 0\nloc_11C3:\nmov esi, [rdx+rax]\ncmp [rdi+rax], esi\njnz short loc_11E0\nadd rax, 4\ncmp rax, rcx\njnz short loc_11C3\nmov eax, 1\nretn\nloc_11DA:\nmov eax, 1\nretn\nloc_11E0:\nmov eax, 0\nlocret_11E5:\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3, int a4)\n{\n __int64 result; // rax\n __int64 v5; // rax\n\n result = 0LL;\n if ( a2 == a4 )\n {\n if ( a2 <= 0 )\n {\n return 1LL;\n }\n else\n {\n v5 = 0LL;\n while ( *(_DWORD *)(a1 + v5) == *(_DWORD *)(a3 + v5) )\n {\n v5 += 4LL;\n if ( v5 == 4LL * a2 )\n return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_11A2:\nendbr64\nmov eax, 0\ncmp esi, ecx\njnz short locret_11E5\ntest esi, esi\njle short loc_11DA\nmovsxd rsi, esi\nlea rcx, ds:0[rsi*4]\nmov eax, 0\nloc_11C3:\nmov esi, [rdx+rax]\ncmp [rdi+rax], esi\njnz short loc_11E0\nadd rax, 4\ncmp rax, rcx\njnz short loc_11C3\nmov eax, 1\nretn\nloc_11DA:\nmov eax, 1\nretn\nloc_11E0:\nmov eax, 0\nlocret_11E5:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11A2(__int64 a1, int a2, __int64 a3, int a4)\n{\n __int64 result; // rax\n __int64 v5; // rax\n\n result = 0LL;\n if ( a2 == a4 )\n {\n if ( a2 <= 0 )\n {\n return 1LL;\n }\n else\n {\n v5 = 0LL;\n while ( *(_DWORD *)(a1 + v5) == *(_DWORD *)(a3 + v5) )\n {\n v5 += 4LL;\n if ( v5 == 4LL * a2 )\n return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A2(long long a1, int a2, long long a3, int a4) {\n long long result;\n long long v5;\n result = 0LL;\n if (a2 == a4) {\n if (a2 <= 0) {\n return 1LL;\n } else {\n v5 = 0LL;\n while (*(uint32_t *)(a1 + v5) == *(uint32_t *)(a3 + v5)) {\n v5 += 4LL;\n if (v5 == 4LL * a2) return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3, int a4) {\n long long result;\n long long v5;\n result = 0LL;\n if (a2 == a4) {\n if (a2 <= 0) {\n return 1LL;\n } else {\n v5 = 0LL;\n while (*(uint32_t *)(a1 + v5) == *(uint32_t *)(a3 + v5)) {\n v5 += 4LL;\n if (v5 == 4LL * a2) return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}" + }, + { + "index": 412, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nvoid remove_odd(int l[], int *size) {\n\n int write_index = 0;\n\n for (int i = 0; i < *size; ++i) {\n\n if (l[i] % 2 == 0) {\n\n l[write_index++] = l[i];\n\n }\n\n }\n\n *size = write_index;\n\n}\n\n\n\n", + "func": "bool func0(int arr1[], int size1, int arr2[], int size2) {\n if (size1 != size2) return false;\n for (int i = 0; i < size1; i++) {\n if (arr1[i] != arr2[i]) return false;\n }\n return true;\n}", + "test": "int main() {\n\n int l1[] = {1, 2, 3};\n\n int l2[] = {2, 4, 6};\n\n int l3[] = {10, 20, 3};\n\n int sizeL1 = 3, sizeL2 = 3, sizeL3 = 3;\n\n\n\n remove_odd(l1, &sizeL1);\n\n remove_odd(l2, &sizeL2);\n\n remove_odd(l3, &sizeL3);\n\n\n\n int expectedL1[] = {2};\n\n int expectedL2[] = {2, 4, 6};\n\n int expectedL3[] = {10, 20};\n\n\n\n assert(func0(l1, sizeL1, expectedL1, 1));\n\n assert(func0(l2, sizeL2, expectedL2, 3));\n\n assert(func0(l3, sizeL3, expectedL3, 2));\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ncmp %ecx,%esi\njne 1340 \njmpq 12b0 \nnopl (%rax)\nxor %eax,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0_part_0:\ntest esi, esi\njle short loc_1330\nmovsxd rsi, esi\nxor eax, eax\nlea rcx, ds:0[rsi*4]\njmp short loc_1321\nloc_1318:\nadd rax, 4\ncmp rcx, rax\njz short loc_1330\nloc_1321:\nmov esi, [rdx+rax]\ncmp [rdi+rax], esi\njz short loc_1318\nxor eax, eax\nretn\nloc_1330:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0_part_0(__int64 a1, int a2, __int64 a3)\n{\n __int64 v3; // rax\n\n if ( a2 <= 0 )\n return 1LL;\n v3 = 0LL;\n while ( *(_DWORD *)(a1 + v3) == *(_DWORD *)(a3 + v3) )\n {\n v3 += 4LL;\n if ( 4LL * a2 == v3 )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1300:\ntest esi, esi\njle short loc_1330\nmovsxd rsi, esi\nxor eax, eax\nlea rcx, ds:0[rsi*4]\njmp short loc_1321\nloc_1318:\nadd rax, 4\ncmp rcx, rax\njz short loc_1330\nloc_1321:\nmov esi, [rdx+rax]\ncmp [rdi+rax], esi\njz short loc_1318\nxor eax, eax\nretn\nloc_1330:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1300(__int64 a1, int a2, __int64 a3)\n{\n __int64 v3; // rax\n\n if ( a2 <= 0 )\n return 1LL;\n v3 = 0LL;\n while ( *(_DWORD *)(a1 + v3) == *(_DWORD *)(a3 + v3) )\n {\n v3 += 4LL;\n if ( 4LL * a2 == v3 )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1300(long long a1, int a2, long long a3) {\n long long v3;\n if (a2 <= 0) return 1LL;\n v3 = 0LL;\n while (*(uint32_t *)(a1 + v3) == *(uint32_t *)(a3 + v3)) {\n v3 += 4LL;\n if (4LL * a2 == v3) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0_part_0(long long a1, int a2, long long a3) {\n long long v3;\n if (a2 <= 0) return 1LL;\n v3 = 0LL;\n while (*(uint32_t *)(a1 + v3) == *(uint32_t *)(a3 + v3)) {\n v3 += 4LL;\n if (4LL * a2 == v3) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 412, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nvoid remove_odd(int l[], int *size) {\n\n int write_index = 0;\n\n for (int i = 0; i < *size; ++i) {\n\n if (l[i] % 2 == 0) {\n\n l[write_index++] = l[i];\n\n }\n\n }\n\n *size = write_index;\n\n}\n\n\n\n", + "func": "bool func0(int arr1[], int size1, int arr2[], int size2) {\n if (size1 != size2) return false;\n for (int i = 0; i < size1; i++) {\n if (arr1[i] != arr2[i]) return false;\n }\n return true;\n}", + "test": "int main() {\n\n int l1[] = {1, 2, 3};\n\n int l2[] = {2, 4, 6};\n\n int l3[] = {10, 20, 3};\n\n int sizeL1 = 3, sizeL2 = 3, sizeL3 = 3;\n\n\n\n remove_odd(l1, &sizeL1);\n\n remove_odd(l2, &sizeL2);\n\n remove_odd(l3, &sizeL3);\n\n\n\n int expectedL1[] = {2};\n\n int expectedL2[] = {2, 4, 6};\n\n int expectedL3[] = {10, 20};\n\n\n\n assert(func0(l1, sizeL1, expectedL1, 1));\n\n assert(func0(l2, sizeL2, expectedL2, 3));\n\n assert(func0(l3, sizeL3, expectedL3, 2));\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nxor %eax,%eax\ncmp %ecx,%esi\njne 137e \ntest %esi,%esi\njle 1380 \nsub $0x1,%esi\nxor %eax,%eax\njmp 1374 \nnopl (%rax)\nlea 0x1(%rax),%rcx\ncmp %rsi,%rax\nje 1380 \nmov %rcx,%rax\nmov (%rdx,%rax,4),%ecx\ncmp %ecx,(%rdi,%rax,4)\nje 1368 \nxor %eax,%eax\nretq\nmov $0x1,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0_part_0:\ntest esi, esi\njle short loc_12D0\nmovsxd rsi, esi\nxor eax, eax\nlea rcx, ds:0[rsi*4]\njmp short loc_12C1\nloc_12B8:\nadd rax, 4\ncmp rcx, rax\njz short loc_12D0\nloc_12C1:\nmov esi, [rdx+rax]\ncmp [rdi+rax], esi\njz short loc_12B8\nxor eax, eax\nretn\nloc_12D0:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0_part_0(__int64 a1, int a2, __int64 a3)\n{\n __int64 v3; // rax\n\n if ( a2 <= 0 )\n return 1LL;\n v3 = 0LL;\n while ( *(_DWORD *)(a1 + v3) == *(_DWORD *)(a3 + v3) )\n {\n v3 += 4LL;\n if ( 4LL * a2 == v3 )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_12A0:\ntest esi, esi\njle short loc_12D0\nmovsxd rsi, esi\nxor eax, eax\nlea rcx, ds:0[rsi*4]\njmp short loc_12C1\nloc_12B8:\nadd rax, 4\ncmp rcx, rax\njz short loc_12D0\nloc_12C1:\nmov esi, [rdx+rax]\ncmp [rdi+rax], esi\njz short loc_12B8\nxor eax, eax\nretn\nloc_12D0:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12A0(__int64 a1, int a2, __int64 a3)\n{\n __int64 v3; // rax\n\n if ( a2 <= 0 )\n return 1LL;\n v3 = 0LL;\n while ( *(_DWORD *)(a1 + v3) == *(_DWORD *)(a3 + v3) )\n {\n v3 += 4LL;\n if ( 4LL * a2 == v3 )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12A0(long long a1, int a2, long long a3) {\n long long v3;\n if (a2 <= 0) return 1LL;\n v3 = 0LL;\n while (*(uint32_t *)(a1 + v3) == *(uint32_t *)(a3 + v3)) {\n v3 += 4LL;\n if (4LL * a2 == v3) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0_part_0(long long a1, int a2, long long a3) {\n long long v3;\n if (a2 <= 0) return 1LL;\n v3 = 0LL;\n while (*(uint32_t *)(a1 + v3) == *(uint32_t *)(a3 + v3)) {\n v3 += 4LL;\n if (4LL * a2 == v3) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 413, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(char list1[][3][50], int count, int n, char result[][50]) {\n for (int i = 0; i < count; i++) {\n strcpy(result[i], list1[i][n]);\n }\n return result;\n}", + "test": "int main() {\n\n char data[4][3][50] = {{\"Greyson Fulton\", \"98\", \"99\"}, {\"Brady Kent\", \"97\", \"96\"}, {\"Wyatt Knott\", \"91\", \"94\"}, {\"Beau Turnbull\", \"94\", \"98\"}};\n\n char result[4][50];\n\n\n\n func0(data, 4, 0, result);\n\n assert(strcmp(result[0], \"Greyson Fulton\") == 0);\n\n assert(strcmp(result[1], \"Brady Kent\") == 0);\n\n assert(strcmp(result[2], \"Wyatt Knott\") == 0);\n\n assert(strcmp(result[3], \"Beau Turnbull\") == 0);\n\n\n\n func0(data, 4, 2, result);\n\n assert(strcmp(result[0], \"99\") == 0);\n\n assert(strcmp(result[1], \"96\") == 0);\n\n assert(strcmp(result[2], \"94\") == 0);\n\n assert(strcmp(result[3], \"98\") == 0);\n\n\n\n func0(data, 4, 1, result);\n\n assert(strcmp(result[0], \"98\") == 0);\n\n assert(strcmp(result[1], \"97\") == 0);\n\n assert(strcmp(result[2], \"91\") == 0);\n\n assert(strcmp(result[3], \"94\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmov %rcx,-0x28(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 1238 \nmov -0x4(%rbp),%eax\ncltq\nimul $0x96,%rax,%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x20(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nadd %rax,%rax\nadd %rax,%rcx\nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nadd %rax,%rax\nmov %rax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 1080 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11cc \nmov -0x28(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_28], rcx\nmov [rbp+var_4], 0\njmp short loc_1238\nloc_11CC:\nmov eax, [rbp+var_4]\ncdqe\nimul rdx, rax, 96h\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_20]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nadd rax, rax\nadd rcx, rax\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nadd rax, rax\nmov rdx, rax\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strcpy\nadd [rbp+var_4], 1\nloc_1238:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11CC\nmov rax, [rbp+var_28]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3, __int64 a4)\n{\n int i; // [rsp+2Ch] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n strcpy((char *)(50LL * i + a4), (const char *)(50LL * a3 + 150LL * i + a1));\n return a4;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_28], rcx\nmov [rbp+var_4], 0\njmp short loc_1238\nloc_11CC:\nmov eax, [rbp+var_4]\ncdqe\nimul rdx, rax, 96h\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_20]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nadd rax, rax\nadd rcx, rax\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nadd rax, rax\nmov rdx, rax\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strcpy\nadd [rbp+var_4], 1\nloc_1238:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11CC\nmov rax, [rbp+var_28]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(__int64 a1, int a2, int a3, __int64 a4)\n{\n int i; // [rsp+2Ch] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n strcpy((char *)(50LL * i + a4), (const char *)(50LL * a3 + 150LL * i + a1));\n return a4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(long long a1, int a2, int a3, long long a4) {\n int i;\n for (i = 0; i < a2; ++i)\n strcpy((char *)(50LL * i + a4), (const char *)(50LL * a3 + 150LL * i + a1));\n return a4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3, long long a4) {\n int i;\n for (i = 0; i < a2; ++i)\n strcpy((char *)(50LL * i + a4), (const char *)(50LL * a3 + 150LL * i + a1));\n return a4;\n}" + }, + { + "index": 413, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(char list1[][3][50], int count, int n, char result[][50]) {\n for (int i = 0; i < count; i++) {\n strcpy(result[i], list1[i][n]);\n }\n return result;\n}", + "test": "int main() {\n\n char data[4][3][50] = {{\"Greyson Fulton\", \"98\", \"99\"}, {\"Brady Kent\", \"97\", \"96\"}, {\"Wyatt Knott\", \"91\", \"94\"}, {\"Beau Turnbull\", \"94\", \"98\"}};\n\n char result[4][50];\n\n\n\n func0(data, 4, 0, result);\n\n assert(strcmp(result[0], \"Greyson Fulton\") == 0);\n\n assert(strcmp(result[1], \"Brady Kent\") == 0);\n\n assert(strcmp(result[2], \"Wyatt Knott\") == 0);\n\n assert(strcmp(result[3], \"Beau Turnbull\") == 0);\n\n\n\n func0(data, 4, 2, result);\n\n assert(strcmp(result[0], \"99\") == 0);\n\n assert(strcmp(result[1], \"96\") == 0);\n\n assert(strcmp(result[2], \"94\") == 0);\n\n assert(strcmp(result[3], \"98\") == 0);\n\n\n\n func0(data, 4, 1, result);\n\n assert(strcmp(result[0], \"98\") == 0);\n\n assert(strcmp(result[1], \"97\") == 0);\n\n assert(strcmp(result[2], \"91\") == 0);\n\n assert(strcmp(result[3], \"94\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rcx,%r13\ntest %esi,%esi\njle 11db \nmov %rcx,%rbx\nmovslq %edx,%rdx\nlea (%rdx,%rdx,4),%rax\nlea (%rax,%rax,4),%rax\nlea (%rdi,%rax,2),%rbp\nlea -0x1(%rsi),%eax\nlea (%rax,%rax,4),%rax\nlea (%rax,%rax,4),%rax\nlea 0x32(%rcx,%rax,2),%r12\nmov %rbp,%rsi\nmov %rbx,%rdi\ncallq 1070 \nadd $0x32,%rbx\nadd $0x96,%rbp\ncmp %r12,%rbx\njne 11c0 \nmov %r13,%rax\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r13, rcx\ntest esi, esi\njle short loc_11FA\nmov rbx, rcx\nmovsxd rdx, edx\nlea rax, [rdx+rdx*4]\nlea rax, [rax+rax*4]\nlea rbp, [rdi+rax*2]\nmovsxd rsi, esi\nlea rax, [rsi+rsi*4]\nlea rax, [rax+rax*4]\nlea r12, [rcx+rax*2]\nloc_11DF:\nmov rsi, rbp; src\nmov rdi, rbx; dest\ncall _strcpy\nadd rbx, 32h ; '2'\nadd rbp, 96h\ncmp rbx, r12\njnz short loc_11DF\nloc_11FA:\nmov rax, r13\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2, int a3, char *a4)\n{\n char *v5; // rbx\n const char *v6; // rbp\n char *v7; // r12\n\n if ( a2 > 0 )\n {\n v5 = a4;\n v6 = (const char *)(a1 + 50LL * a3);\n v7 = &a4[50 * a2];\n do\n {\n strcpy(v5, v6);\n v5 += 50;\n v6 += 150;\n }\n while ( v5 != v7 );\n }\n return a4;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r13, rcx\ntest esi, esi\njle short loc_11FA\nmov rbx, rcx\nmovsxd rdx, edx\nlea rax, [rdx+rdx*4]\nlea rax, [rax+rax*4]\nlea rbp, [rdi+rax*2]\nmovsxd rsi, esi\nlea rax, [rsi+rsi*4]\nlea rax, [rax+rax*4]\nlea r12, [rcx+rax*2]\nloc_11DF:\nmov rsi, rbp; src\nmov rdi, rbx; dest\ncall _strcpy\nadd rbx, 32h ; '2'\nadd rbp, 96h\ncmp rbx, r12\njnz short loc_11DF\nloc_11FA:\nmov rax, r13\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11A9(__int64 a1, int a2, int a3, char *a4)\n{\n char *v5; // rbx\n const char *v6; // rbp\n char *v7; // r12\n\n if ( a2 > 0 )\n {\n v5 = a4;\n v6 = (const char *)(a1 + 50LL * a3);\n v7 = &a4[50 * a2];\n do\n {\n strcpy(v5, v6);\n v5 += 50;\n v6 += 150;\n }\n while ( v5 != v7 );\n }\n return a4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11A9(long long a1, int a2, int a3, char *a4) {\n char *v5;\n const char *v6;\n char *v7;\n if (a2 > 0) {\n v5 = a4;\n v6 = (const char *)(a1 + 50LL * a3);\n v7 = &a4[50 * a2];\n do {\n strcpy(v5, v6);\n v5 += 50;\n v6 += 150;\n } while (v5 != v7);\n }\n return a4;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2, int a3, char *a4) {\n char *v5;\n const char *v6;\n char *v7;\n if (a2 > 0) {\n v5 = a4;\n v6 = (const char *)(a1 + 50LL * a3);\n v7 = &a4[50 * a2];\n do {\n strcpy(v5, v6);\n v5 += 50;\n v6 += 150;\n } while (v5 != v7);\n }\n return a4;\n}" + }, + { + "index": 413, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(char list1[][3][50], int count, int n, char result[][50]) {\n for (int i = 0; i < count; i++) {\n strcpy(result[i], list1[i][n]);\n }\n return result;\n}", + "test": "int main() {\n\n char data[4][3][50] = {{\"Greyson Fulton\", \"98\", \"99\"}, {\"Brady Kent\", \"97\", \"96\"}, {\"Wyatt Knott\", \"91\", \"94\"}, {\"Beau Turnbull\", \"94\", \"98\"}};\n\n char result[4][50];\n\n\n\n func0(data, 4, 0, result);\n\n assert(strcmp(result[0], \"Greyson Fulton\") == 0);\n\n assert(strcmp(result[1], \"Brady Kent\") == 0);\n\n assert(strcmp(result[2], \"Wyatt Knott\") == 0);\n\n assert(strcmp(result[3], \"Beau Turnbull\") == 0);\n\n\n\n func0(data, 4, 2, result);\n\n assert(strcmp(result[0], \"99\") == 0);\n\n assert(strcmp(result[1], \"96\") == 0);\n\n assert(strcmp(result[2], \"94\") == 0);\n\n assert(strcmp(result[3], \"98\") == 0);\n\n\n\n func0(data, 4, 1, result);\n\n assert(strcmp(result[0], \"98\") == 0);\n\n assert(strcmp(result[1], \"97\") == 0);\n\n assert(strcmp(result[2], \"91\") == 0);\n\n assert(strcmp(result[3], \"94\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %rcx,%r12\npush %rbp\npush %rbx\ntest %esi,%esi\njle 161e \nmovslq %edx,%rdx\nlea (%rdx,%rdx,4),%rax\nlea (%rax,%rax,4),%rax\nlea (%rdi,%rax,2),%rbx\nlea -0x1(%rsi),%eax\nlea (%rax,%rax,4),%rax\nlea (%rax,%rax,4),%rax\nlea 0x32(%rcx,%rax,2),%rbp\nxchg %ax,%ax\nmov %rbx,%rsi\nmov %rcx,%rdi\nadd $0x96,%rbx\ncallq 1080 \nmov %rax,%rcx\nadd $0x32,%rcx\ncmp %rbp,%rcx\njne 1600 \nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r12\nmov r12, rcx\npush rbp\npush rbx\ntest esi, esi\njle short loc_14FE\nmovsxd rdx, edx\nmovsxd rsi, esi\nlea rax, [rdx+rdx*4]\nlea rax, [rax+rax*4]\nlea rbx, [rdi+rax*2]\nlea rax, [rsi+rsi*4]\nlea rax, [rax+rax*4]\nlea rbp, [rcx+rax*2]\nnop dword ptr [rax]\nloc_14E0:\nmov rsi, rbx; src\nmov rdi, rcx; dest\nadd rbx, 96h\ncall _strcpy\nmov rcx, rax\nadd rcx, 32h ; '2'\ncmp rcx, rbp\njnz short loc_14E0\nloc_14FE:\nmov rax, r12\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2, int a3, char *a4)\n{\n char *v4; // r12\n const char *v5; // rbx\n char *v6; // rbp\n const char *v7; // rsi\n\n v4 = a4;\n if ( a2 > 0 )\n {\n v5 = (const char *)(a1 + 50LL * a3);\n v6 = &a4[50 * a2];\n do\n {\n v7 = v5;\n v5 += 150;\n a4 = strcpy(a4, v7) + 50;\n }\n while ( a4 != v6 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_14B0:\nendbr64\npush r12\nmov r12, rcx\npush rbp\npush rbx\ntest esi, esi\njle short loc_14FE\nmovsxd rdx, edx\nmovsxd rsi, esi\nlea rax, [rdx+rdx*4]\nlea rax, [rax+rax*4]\nlea rbx, [rdi+rax*2]\nlea rax, [rsi+rsi*4]\nlea rax, [rax+rax*4]\nlea rbp, [rcx+rax*2]\nnop dword ptr [rax]\nloc_14E0:\nmov rsi, rbx; src\nmov rdi, rcx; dest\nadd rbx, 96h\ncall _strcpy\nmov rcx, rax\nadd rcx, 32h ; '2'\ncmp rcx, rbp\njnz short loc_14E0\nloc_14FE:\nmov rax, r12\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "char *__fastcall sub_14B0(__int64 a1, int a2, int a3, char *a4)\n{\n char *v4; // r12\n const char *v5; // rbx\n char *v6; // rbp\n const char *v7; // rsi\n\n v4 = a4;\n if ( a2 > 0 )\n {\n v5 = (const char *)(a1 + 50LL * a3);\n v6 = &a4[50 * a2];\n do\n {\n v7 = v5;\n v5 += 150;\n a4 = strcpy(a4, v7) + 50;\n }\n while ( a4 != v6 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_14B0(long long a1, int a2, int a3, char *a4) {\n char *v4;\n const char *v5;\n char *v6;\n const char *v7;\n v4 = a4;\n if (a2 > 0) {\n v5 = (const char *)(a1 + 50LL * a3);\n v6 = &a4[50 * a2];\n do {\n v7 = v5;\n v5 += 150;\n a4 = strcpy(a4, v7) + 50;\n } while (a4 != v6);\n }\n return v4;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2, int a3, char *a4) {\n char *v4;\n const char *v5;\n char *v6;\n const char *v7;\n v4 = a4;\n if (a2 > 0) {\n v5 = (const char *)(a1 + 50LL * a3);\n v6 = &a4[50 * a2];\n do {\n v7 = v5;\n v5 += 150;\n a4 = strcpy(a4, v7) + 50;\n } while (a4 != v6);\n }\n return v4;\n}" + }, + { + "index": 413, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(char list1[][3][50], int count, int n, char result[][50]) {\n for (int i = 0; i < count; i++) {\n strcpy(result[i], list1[i][n]);\n }\n return result;\n}", + "test": "int main() {\n\n char data[4][3][50] = {{\"Greyson Fulton\", \"98\", \"99\"}, {\"Brady Kent\", \"97\", \"96\"}, {\"Wyatt Knott\", \"91\", \"94\"}, {\"Beau Turnbull\", \"94\", \"98\"}};\n\n char result[4][50];\n\n\n\n func0(data, 4, 0, result);\n\n assert(strcmp(result[0], \"Greyson Fulton\") == 0);\n\n assert(strcmp(result[1], \"Brady Kent\") == 0);\n\n assert(strcmp(result[2], \"Wyatt Knott\") == 0);\n\n assert(strcmp(result[3], \"Beau Turnbull\") == 0);\n\n\n\n func0(data, 4, 2, result);\n\n assert(strcmp(result[0], \"99\") == 0);\n\n assert(strcmp(result[1], \"96\") == 0);\n\n assert(strcmp(result[2], \"94\") == 0);\n\n assert(strcmp(result[3], \"98\") == 0);\n\n\n\n func0(data, 4, 1, result);\n\n assert(strcmp(result[0], \"98\") == 0);\n\n assert(strcmp(result[1], \"97\") == 0);\n\n assert(strcmp(result[2], \"91\") == 0);\n\n assert(strcmp(result[3], \"94\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %rcx,%r12\npush %rbp\npush %rbx\ntest %esi,%esi\njle 161e \nmovslq %edx,%rdx\nlea (%rdx,%rdx,4),%rax\nlea (%rax,%rax,4),%rax\nlea (%rdi,%rax,2),%rbx\nlea -0x1(%rsi),%eax\nlea (%rax,%rax,4),%rax\nlea (%rax,%rax,4),%rax\nlea 0x32(%rcx,%rax,2),%rbp\nxchg %ax,%ax\nmov %rbx,%rsi\nmov %rcx,%rdi\nadd $0x96,%rbx\ncallq 1080 \nmov %rax,%rcx\nadd $0x32,%rcx\ncmp %rbp,%rcx\njne 1600 \nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r12\nmov r12, rcx\npush rbp\npush rbx\ntest esi, esi\njle short loc_14FE\nmovsxd rdx, edx\nmovsxd rsi, esi\nlea rax, [rdx+rdx*4]\nlea rax, [rax+rax*4]\nlea rbx, [rdi+rax*2]\nlea rax, [rsi+rsi*4]\nlea rax, [rax+rax*4]\nlea rbp, [rcx+rax*2]\nnop dword ptr [rax]\nloc_14E0:\nmov rsi, rbx; src\nmov rdi, rcx; dest\nadd rbx, 96h\ncall _strcpy\nmov rcx, rax\nadd rcx, 32h ; '2'\ncmp rcx, rbp\njnz short loc_14E0\nloc_14FE:\nmov rax, r12\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2, int a3, char *a4)\n{\n char *v4; // r12\n const char *v5; // rbx\n char *v6; // rbp\n const char *v7; // rsi\n\n v4 = a4;\n if ( a2 > 0 )\n {\n v5 = (const char *)(a1 + 50LL * a3);\n v6 = &a4[50 * a2];\n do\n {\n v7 = v5;\n v5 += 150;\n a4 = strcpy(a4, v7) + 50;\n }\n while ( a4 != v6 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_14B0:\nendbr64\npush r12\nmov r12, rcx\npush rbp\npush rbx\ntest esi, esi\njle short loc_14FE\nmovsxd rdx, edx\nmovsxd rsi, esi\nlea rax, [rdx+rdx*4]\nlea rax, [rax+rax*4]\nlea rbx, [rdi+rax*2]\nlea rax, [rsi+rsi*4]\nlea rax, [rax+rax*4]\nlea rbp, [rcx+rax*2]\nnop dword ptr [rax]\nloc_14E0:\nmov rsi, rbx; src\nmov rdi, rcx; dest\nadd rbx, 96h\ncall _strcpy\nmov rcx, rax\nadd rcx, 32h ; '2'\ncmp rcx, rbp\njnz short loc_14E0\nloc_14FE:\nmov rax, r12\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "char *__fastcall sub_14B0(__int64 a1, int a2, int a3, char *a4)\n{\n char *v4; // r12\n const char *v5; // rbx\n char *v6; // rbp\n const char *v7; // rsi\n\n v4 = a4;\n if ( a2 > 0 )\n {\n v5 = (const char *)(a1 + 50LL * a3);\n v6 = &a4[50 * a2];\n do\n {\n v7 = v5;\n v5 += 150;\n a4 = strcpy(a4, v7) + 50;\n }\n while ( a4 != v6 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_14B0(long long a1, int a2, int a3, char *a4) {\n char *v4;\n const char *v5;\n char *v6;\n const char *v7;\n v4 = a4;\n if (a2 > 0) {\n v5 = (const char *)(a1 + 50LL * a3);\n v6 = &a4[50 * a2];\n do {\n v7 = v5;\n v5 += 150;\n a4 = strcpy(a4, v7) + 50;\n } while (a4 != v6);\n }\n return v4;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2, int a3, char *a4) {\n char *v4;\n const char *v5;\n char *v6;\n const char *v7;\n v4 = a4;\n if (a2 > 0) {\n v5 = (const char *)(a1 + 50LL * a3);\n v6 = &a4[50 * a2];\n do {\n v7 = v5;\n v5 += 150;\n a4 = strcpy(a4, v7) + 50;\n } while (a4 != v6);\n }\n return v4;\n}" + }, + { + "index": 414, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int *list1, int size1, int *list2, int size2) {\n int i, j;\n for (i = 0; i < size1; i++) {\n for (j = 0; j < size2; j++) {\n if (list1[i] == list2[j]) {\n return 1;\n }\n }\n }\n return 0;\n}", + "test": "int main() {\n\n int list1_a[] = {1, 2, 3, 4, 5};\n\n int list2_a[] = {6, 7, 8, 9};\n\n assert(func0(list1_a, 5, list2_a, 4) == 0);\n\n\n\n int list1_b[] = {1, 2, 3};\n\n int list2_b[] = {4, 5, 6};\n\n assert(func0(list1_b, 3, list2_b, 3) == 0);\n\n\n\n int list1_c[] = {1, 4, 5};\n\n int list2_c[] = {1, 4, 5};\n\n assert(func0(list1_c, 3, list2_c, 3) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %ecx,-0x20(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11d8 \nmovl $0x0,-0x4(%rbp)\njmp 11cc \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 11c8 \nmov $0x1,%eax\njmp 11e5 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x20(%rbp),%eax\njl 1191 \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1188 \nmov $0x0,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov [rbp+var_8], 0\njmp short loc_11D8\nloc_1188:\nmov [rbp+var_4], 0\njmp short loc_11CC\nloc_1191:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11C8\nmov eax, 1\njmp short loc_11E5\nloc_11C8:\nadd [rbp+var_4], 1\nloc_11CC:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_20]\njl short loc_1191\nadd [rbp+var_8], 1\nloc_11D8:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, 0\nloc_11E5:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3, int a4)\n{\n int i; // [rsp+20h] [rbp-8h]\n int j; // [rsp+24h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n for ( j = 0; j < a4; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4LL * j + a3) )\n return 1LL;\n }\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov [rbp+var_8], 0\njmp short loc_11D8\nloc_1188:\nmov [rbp+var_4], 0\njmp short loc_11CC\nloc_1191:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11C8\nmov eax, 1\njmp short loc_11E5\nloc_11C8:\nadd [rbp+var_4], 1\nloc_11CC:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_20]\njl short loc_1191\nadd [rbp+var_8], 1\nloc_11D8:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, 0\nloc_11E5:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, __int64 a3, int a4)\n{\n int i; // [rsp+20h] [rbp-8h]\n int j; // [rsp+24h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n for ( j = 0; j < a4; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4LL * j + a3) )\n return 1LL;\n }\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, long long a3, int a4) {\n int i;\n int j;\n for (i = 0; i < a2; ++i) {\n for (j = 0; j < a4; ++j) {\n if (*(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4LL * j + a3))\n return 1LL;\n }\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3, int a4) {\n int i;\n int j;\n for (i = 0; i < a2; ++i) {\n for (j = 0; j < a4; ++j) {\n if (*(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4LL * j + a3))\n return 1LL;\n }\n }\n return 0LL;\n}" + }, + { + "index": 414, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int *list1, int size1, int *list2, int size2) {\n int i, j;\n for (i = 0; i < size1; i++) {\n for (j = 0; j < size2; j++) {\n if (list1[i] == list2[j]) {\n return 1;\n }\n }\n }\n return 0;\n}", + "test": "int main() {\n\n int list1_a[] = {1, 2, 3, 4, 5};\n\n int list2_a[] = {6, 7, 8, 9};\n\n assert(func0(list1_a, 5, list2_a, 4) == 0);\n\n\n\n int list1_b[] = {1, 2, 3};\n\n int list2_b[] = {4, 5, 6};\n\n assert(func0(list1_b, 3, list2_b, 3) == 0);\n\n\n\n int list1_c[] = {1, 4, 5};\n\n int list2_c[] = {1, 4, 5};\n\n assert(func0(list1_c, 3, list2_c, 3) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11ad \nmov %rdi,%r8\nlea -0x1(%rsi),%eax\nlea 0x4(%rdi,%rax,4),%r9\nmov %rdx,%rdi\nlea -0x1(%rcx),%eax\nlea 0x4(%rdx,%rax,4),%rsi\ntest %ecx,%ecx\njle 119e \nmov (%r8),%edx\nmov %rdi,%rax\ncmp (%rax),%edx\nje 11b3 \nadd $0x4,%rax\ncmp %rsi,%rax\njne 1191 \nadd $0x4,%r8\ncmp %r9,%r8\njne 1187 \nmov $0x0,%eax\nretq\nmov $0x0,%eax\nretq\nmov $0x1,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11A8\nmov r8, rdi\nmovsxd rsi, esi\nlea r9, [rdi+rsi*4]\nmovsxd rax, ecx\nlea rdi, [rdx+rax*4]\nloc_1182:\ntest ecx, ecx\njle short loc_1199\nmov esi, [r8]\nmov rax, rdx\nloc_118C:\ncmp esi, [rax]\njz short loc_11AE\nadd rax, 4\ncmp rax, rdi\njnz short loc_118C\nloc_1199:\nadd r8, 4\ncmp r8, r9\njnz short loc_1182\nmov eax, 0\nretn\nloc_11A8:\nmov eax, 0\nretn\nloc_11AE:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2, _DWORD *a3, int a4)\n{\n _DWORD *v4; // r8\n _DWORD *v5; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v4 = a1;\n while ( a4 <= 0 )\n {\nLABEL_7:\n if ( ++v4 == &a1[a2] )\n return 0LL;\n }\n v5 = a3;\n while ( *v4 != *v5 )\n {\n if ( ++v5 == &a3[a4] )\n goto LABEL_7;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11A8\nmov r8, rdi\nmovsxd rsi, esi\nlea r9, [rdi+rsi*4]\nmovsxd rax, ecx\nlea rdi, [rdx+rax*4]\nloc_1182:\ntest ecx, ecx\njle short loc_1199\nmov esi, [r8]\nmov rax, rdx\nloc_118C:\ncmp esi, [rax]\njz short loc_11AE\nadd rax, 4\ncmp rax, rdi\njnz short loc_118C\nloc_1199:\nadd r8, 4\ncmp r8, r9\njnz short loc_1182\nmov eax, 0\nretn\nloc_11A8:\nmov eax, 0\nretn\nloc_11AE:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2, _DWORD *a3, int a4)\n{\n _DWORD *v4; // r8\n _DWORD *v5; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v4 = a1;\n while ( a4 <= 0 )\n {\nLABEL_7:\n if ( ++v4 == &a1[a2] )\n return 0LL;\n }\n v5 = a3;\n while ( *v4 != *v5 )\n {\n if ( ++v5 == &a3[a4] )\n goto LABEL_7;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2, uint32_t *a3, int a4) {\n uint32_t *v4;\n uint32_t *v5;\n if (a2 <= 0) return 0LL;\n v4 = a1;\n while (a4 <= 0) {\n LABEL_7:\n if (++v4 == &a1[a2]) return 0LL;\n }\n v5 = a3;\n while (*v4 != *v5) {\n if (++v5 == &a3[a4]) goto LABEL_7;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2, uint32_t *a3, int a4) {\n uint32_t *v4;\n uint32_t *v5;\n if (a2 <= 0) return 0LL;\n v4 = a1;\n while (a4 <= 0) {\n LABEL_7:\n if (++v4 == &a1[a2]) return 0LL;\n }\n v5 = a3;\n while (*v4 != *v5) {\n if (++v5 == &a3[a4]) goto LABEL_7;\n }\n return 1LL;\n}" + }, + { + "index": 414, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int *list1, int size1, int *list2, int size2) {\n int i, j;\n for (i = 0; i < size1; i++) {\n for (j = 0; j < size2; j++) {\n if (list1[i] == list2[j]) {\n return 1;\n }\n }\n }\n return 0;\n}", + "test": "int main() {\n\n int list1_a[] = {1, 2, 3, 4, 5};\n\n int list2_a[] = {6, 7, 8, 9};\n\n assert(func0(list1_a, 5, list2_a, 4) == 0);\n\n\n\n int list1_b[] = {1, 2, 3};\n\n int list2_b[] = {4, 5, 6};\n\n assert(func0(list1_b, 3, list2_b, 3) == 0);\n\n\n\n int list1_c[] = {1, 4, 5};\n\n int list2_c[] = {1, 4, 5};\n\n assert(func0(list1_c, 3, list2_c, 3) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1289 \nlea -0x1(%rsi),%eax\nlea 0x4(%rdi,%rax,4),%r9\nlea -0x1(%rcx),%eax\nlea 0x4(%rdx,%rax,4),%r8\ntest %ecx,%ecx\njle 1280 \nmov (%rdi),%esi\nmov %rdx,%rax\njmp 1271 \nnopl 0x0(%rax,%rax,1)\nadd $0x4,%rax\ncmp %r8,%rax\nje 1280 \ncmp (%rax),%esi\njne 1268 \nmov $0x1,%eax\nretq\nnopl 0x0(%rax,%rax,1)\nadd $0x4,%rdi\ncmp %r9,%rdi\njne 1258 \nxor %eax,%eax\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1319\nmovsxd rsi, esi\nmovsxd rax, ecx\nlea r8, [rdi+rsi*4]\nlea rsi, [rdx+rax*4]\nloc_12E6:\ntest ecx, ecx\njle short loc_1320\nloc_12EA:\nmov ecx, [rdi]\nmov rax, rdx\njmp short loc_1301\nloc_12F8:\nadd rax, 4\ncmp rax, rsi\njz short loc_1310\nloc_1301:\ncmp ecx, [rax]\njnz short loc_12F8\nmov eax, 1\nretn\nloc_1310:\nadd rdi, 4\ncmp rdi, r8\njnz short loc_12EA\nloc_1319:\nxor eax, eax\nretn\nloc_1320:\nadd rdi, 4\ncmp rdi, r8\njnz short loc_12E6\njmp short loc_1319", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2, _DWORD *a3, int a4)\n{\n _DWORD *v4; // r8\n _DWORD *v5; // rax\n\n if ( a2 > 0 )\n {\n v4 = &a1[a2];\n while ( a4 <= 0 )\n {\n if ( ++a1 == v4 )\n return 0LL;\n }\n do\n {\n v5 = a3;\n do\n {\n if ( *a1 == *v5 )\n return 1LL;\n ++v5;\n }\n while ( v5 != &a3[a4] );\n ++a1;\n }\n while ( a1 != v4 );\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_12D0:\nendbr64\ntest esi, esi\njle short loc_1319\nmovsxd rsi, esi\nmovsxd rax, ecx\nlea r8, [rdi+rsi*4]\nlea rsi, [rdx+rax*4]\nloc_12E6:\ntest ecx, ecx\njle short loc_1320\nloc_12EA:\nmov ecx, [rdi]\nmov rax, rdx\njmp short loc_1301\nloc_12F8:\nadd rax, 4\ncmp rax, rsi\njz short loc_1310\nloc_1301:\ncmp ecx, [rax]\njnz short loc_12F8\nmov eax, 1\nretn\nloc_1310:\nadd rdi, 4\ncmp rdi, r8\njnz short loc_12EA\nloc_1319:\nxor eax, eax\nretn\nloc_1320:\nadd rdi, 4\ncmp rdi, r8\njnz short loc_12E6\njmp short loc_1319", + "ida_strip_pseudo": "__int64 __fastcall sub_12D0(_DWORD *a1, int a2, _DWORD *a3, int a4)\n{\n _DWORD *v4; // r8\n _DWORD *v5; // rax\n\n if ( a2 > 0 )\n {\n v4 = &a1[a2];\n while ( a4 <= 0 )\n {\n if ( ++a1 == v4 )\n return 0LL;\n }\n do\n {\n v5 = a3;\n do\n {\n if ( *a1 == *v5 )\n return 1LL;\n ++v5;\n }\n while ( v5 != &a3[a4] );\n ++a1;\n }\n while ( a1 != v4 );\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12D0(uint32_t *a1, int a2, uint32_t *a3, int a4) {\n uint32_t *v4;\n uint32_t *v5;\n if (a2 > 0) {\n v4 = &a1[a2];\n while (a4 <= 0) {\n if (++a1 == v4) return 0LL;\n }\n do {\n v5 = a3;\n do {\n if (*a1 == *v5) return 1LL;\n ++v5;\n } while (v5 != &a3[a4]);\n ++a1;\n } while (a1 != v4);\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2, uint32_t *a3, int a4) {\n uint32_t *v4;\n uint32_t *v5;\n if (a2 > 0) {\n v4 = &a1[a2];\n while (a4 <= 0) {\n if (++a1 == v4) return 0LL;\n }\n do {\n v5 = a3;\n do {\n if (*a1 == *v5) return 1LL;\n ++v5;\n } while (v5 != &a3[a4]);\n ++a1;\n } while (a1 != v4);\n }\n return 0LL;\n}" + }, + { + "index": 415, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int arr[], int arr_len, int result[2]) {\n if (arr_len < 2) {\n return NULL;\n }\n int x = arr[0];\n int y = arr[1];\n for (int i = 0; i < arr_len; i++) {\n for (int j = i + 1; j < arr_len; j++) {\n if (arr[i] * arr[j] > x * y) {\n x = arr[i];\n y = arr[j];\n }\n }\n }\n result[0] = x;\n result[1] = y;\n return result;\n}", + "test": "int main() {\n\n int result1[2];\n\n int arr1[] = {1,2,3,4,7,0,8,4};\n\n func0(arr1, 8, result1);\n\n assert(result1[0] == 7 && result1[1] == 8);\n\n\n\n int result2[2];\n\n int arr2[] = {0,-1,-2,-4,5,0,-6};\n\n func0(arr2, 7, result2);\n\n assert(result2[0] == -4 && result2[1] == -6);\n\n\n\n int result3[2];\n\n int arr3[] = {1,2,3};\n\n func0(arr3, 3, result3);\n\n assert(result3[0] == 2 && result3[1] == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\ncmpl $0x1,-0x1c(%rbp)\njg 118c \nmov $0x0,%eax\njmpq 1258 \nmov -0x18(%rbp),%rax\nmov (%rax),%eax\nmov %eax,-0x10(%rbp)\nmov -0x18(%rbp),%rax\nmov 0x4(%rax),%eax\nmov %eax,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\njmpq 1232 \nmov -0x8(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x4(%rbp)\njmp 1226 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\nimul %eax,%edx\nmov -0x10(%rbp),%eax\nimul -0xc(%rbp),%eax\ncmp %eax,%edx\njle 1222 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x10(%rbp)\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0xc(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11b6 \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11ab \nmov -0x28(%rbp),%rax\nmov -0x10(%rbp),%edx\nmov %edx,(%rax)\nmov -0x28(%rbp),%rax\nlea 0x4(%rax),%rdx\nmov -0xc(%rbp),%eax\nmov %eax,(%rdx)\nmov -0x28(%rbp),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\ncmp [rbp+var_1C], 1\njg short loc_118C\nmov eax, 0\njmp loc_1258\nloc_118C:\nmov rax, [rbp+var_18]\nmov eax, [rax]\nmov [rbp+var_10], eax\nmov rax, [rbp+var_18]\nmov eax, [rax+4]\nmov [rbp+var_C], eax\nmov [rbp+var_8], 0\njmp loc_1232\nloc_11AB:\nmov eax, [rbp+var_8]\nadd eax, 1\nmov [rbp+var_4], eax\njmp short loc_1226\nloc_11B6:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nimul edx, eax\nmov eax, [rbp+var_10]\nimul eax, [rbp+var_C]\ncmp edx, eax\njle short loc_1222\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_10], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nloc_1222:\nadd [rbp+var_4], 1\nloc_1226:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11B6\nadd [rbp+var_8], 1\nloc_1232:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl loc_11AB\nmov rax, [rbp+var_28]\nmov edx, [rbp+var_10]\nmov [rax], edx\nmov rax, [rbp+var_28]\nlea rdx, [rax+4]\nmov eax, [rbp+var_C]\nmov [rdx], eax\nmov rax, [rbp+var_28]\nloc_1258:\npop rbp\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2, _DWORD *a3)\n{\n int v4; // [rsp+18h] [rbp-10h]\n int v5; // [rsp+1Ch] [rbp-Ch]\n int i; // [rsp+20h] [rbp-8h]\n int j; // [rsp+24h] [rbp-4h]\n\n if ( a2 <= 1 )\n return 0LL;\n v4 = *a1;\n v5 = a1[1];\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( a1[j] * a1[i] > v5 * v4 )\n {\n v4 = a1[i];\n v5 = a1[j];\n }\n }\n }\n *a3 = v4;\n a3[1] = v5;\n return a3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\ncmp [rbp+var_1C], 1\njg short loc_118C\nmov eax, 0\njmp loc_1258\nloc_118C:\nmov rax, [rbp+var_18]\nmov eax, [rax]\nmov [rbp+var_10], eax\nmov rax, [rbp+var_18]\nmov eax, [rax+4]\nmov [rbp+var_C], eax\nmov [rbp+var_8], 0\njmp loc_1232\nloc_11AB:\nmov eax, [rbp+var_8]\nadd eax, 1\nmov [rbp+var_4], eax\njmp short loc_1226\nloc_11B6:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nimul edx, eax\nmov eax, [rbp+var_10]\nimul eax, [rbp+var_C]\ncmp edx, eax\njle short loc_1222\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_10], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nloc_1222:\nadd [rbp+var_4], 1\nloc_1226:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11B6\nadd [rbp+var_8], 1\nloc_1232:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl loc_11AB\nmov rax, [rbp+var_28]\nmov edx, [rbp+var_10]\nmov [rax], edx\nmov rax, [rbp+var_28]\nlea rdx, [rax+4]\nmov eax, [rbp+var_C]\nmov [rdx], eax\nmov rax, [rbp+var_28]\nloc_1258:\npop rbp\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1169(int *a1, int a2, _DWORD *a3)\n{\n int v4; // [rsp+18h] [rbp-10h]\n int v5; // [rsp+1Ch] [rbp-Ch]\n int i; // [rsp+20h] [rbp-8h]\n int j; // [rsp+24h] [rbp-4h]\n\n if ( a2 <= 1 )\n return 0LL;\n v4 = *a1;\n v5 = a1[1];\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( a1[j] * a1[i] > v5 * v4 )\n {\n v4 = a1[i];\n v5 = a1[j];\n }\n }\n }\n *a3 = v4;\n a3[1] = v5;\n return a3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1169(int *a1, int a2, uint32_t *a3) {\n int v4;\n int v5;\n int i;\n int j;\n if (a2 <= 1) return 0LL;\n v4 = *a1;\n v5 = a1[1];\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if (a1[j] * a1[i] > v5 * v4) {\n v4 = a1[i];\n v5 = a1[j];\n }\n }\n }\n *a3 = v4;\n a3[1] = v5;\n return a3;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2, uint32_t *a3) {\n int v4;\n int v5;\n int i;\n int j;\n if (a2 <= 1) return 0LL;\n v4 = *a1;\n v5 = a1[1];\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if (a1[j] * a1[i] > v5 * v4) {\n v4 = a1[i];\n v5 = a1[j];\n }\n }\n }\n *a3 = v4;\n a3[1] = v5;\n return a3;\n}" + }, + { + "index": 415, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int arr[], int arr_len, int result[2]) {\n if (arr_len < 2) {\n return NULL;\n }\n int x = arr[0];\n int y = arr[1];\n for (int i = 0; i < arr_len; i++) {\n for (int j = i + 1; j < arr_len; j++) {\n if (arr[i] * arr[j] > x * y) {\n x = arr[i];\n y = arr[j];\n }\n }\n }\n result[0] = x;\n result[1] = y;\n return result;\n}", + "test": "int main() {\n\n int result1[2];\n\n int arr1[] = {1,2,3,4,7,0,8,4};\n\n func0(arr1, 8, result1);\n\n assert(result1[0] == 7 && result1[1] == 8);\n\n\n\n int result2[2];\n\n int arr2[] = {0,-1,-2,-4,5,0,-6};\n\n func0(arr2, 7, result2);\n\n assert(result2[0] == -4 && result2[1] == -6);\n\n\n\n int result3[2];\n\n int arr3[] = {1,2,3};\n\n func0(arr3, 3, result3);\n\n assert(result3[0] == 2 && result3[1] == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%esi\njle 11da \npush %r12\npush %rbp\npush %rbx\nmov %rdx,%r12\nmov (%rdi),%r8d\nmov 0x4(%rdi),%r9d\nmov $0x0,%ebx\nmov $0x1,%ebp\nmov $0x1,%ecx\njmp 1195 \nmov %ebp,%ebx\nmov %ecx,%ebp\nmovslq %ebx,%r10\nmov (%rdi,%r10,4),%r10d\nmovslq %ecx,%r11\nmov (%rdi,%r11,4),%edx\nmov %r10d,%eax\nimul %edx,%eax\nmov %r8d,%r11d\nimul %r9d,%r11d\ncmp %r11d,%eax\ncmovg %edx,%r9d\ncmovg %r10d,%r8d\nadd $0x1,%ecx\ncmp %ecx,%esi\njg 1195 \nlea 0x1(%rbp),%ecx\ncmp %ecx,%esi\njg 1191 \nmov %r8d,(%r12)\nmov %r9d,0x4(%r12)\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\nretq\nmov $0x0,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ncmp esi, 1\njle short loc_11E2\npush r13\npush r12\npush rbp\npush rbx\nmov rax, rdi\nmov ebx, esi\nmov r12, rdx\nmov edi, [rdi]\nmov esi, [rax+4]\nmov ebp, ebx\nmovsxd r13, ebx\nmov edx, 1\njmp short loc_1194\nloc_1191:\nmov rdx, rcx\nloc_1194:\ncmp rdx, rbp\njz short loc_11CF\nmov r11d, [rax+rdx*4-4]\nmov rcx, rdx\nloc_11A1:\nmov r10d, [rax+rcx*4]\nmov r9d, r11d\nimul r9d, r10d\nmov r8d, edi\nimul r8d, esi\ncmp r9d, r8d\ncmovg esi, r10d\ncmovg edi, r11d\nadd rcx, 1\ncmp ebx, ecx\njg short loc_11A1\nlea rcx, [rdx+1]\ncmp rdx, r13\njnz short loc_1191\nloc_11CF:\nmov [r12], edi\nmov [r12+4], esi\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_11E2:\nmov eax, 0\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2, _DWORD *a3)\n{\n int v6; // edi\n int v7; // esi\n __int64 i; // rdx\n int v9; // r11d\n __int64 v10; // rcx\n int v11; // r10d\n int v12; // r8d\n\n if ( a2 <= 1 )\n return 0LL;\n v6 = *a1;\n v7 = a1[1];\n for ( i = 1LL; i != a2; ++i )\n {\n v9 = a1[i - 1];\n v10 = i;\n do\n {\n v11 = a1[v10];\n v12 = v7 * v6;\n if ( v11 * v9 > v7 * v6 )\n v7 = a1[v10];\n if ( v11 * v9 > v12 )\n v6 = a1[i - 1];\n ++v10;\n }\n while ( a2 > (int)v10 );\n if ( i == a2 )\n break;\n }\n *a3 = v6;\n a3[1] = v7;\n return a3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ncmp esi, 1\njle short loc_11E2\npush r13\npush r12\npush rbp\npush rbx\nmov rax, rdi\nmov ebx, esi\nmov r12, rdx\nmov edi, [rdi]\nmov esi, [rax+4]\nmov ebp, ebx\nmovsxd r13, ebx\nmov edx, 1\njmp short loc_1194\nloc_1191:\nmov rdx, rcx\nloc_1194:\ncmp rdx, rbp\njz short loc_11CF\nmov r11d, [rax+rdx*4-4]\nmov rcx, rdx\nloc_11A1:\nmov r10d, [rax+rcx*4]\nmov r9d, r11d\nimul r9d, r10d\nmov r8d, edi\nimul r8d, esi\ncmp r9d, r8d\ncmovg esi, r10d\ncmovg edi, r11d\nadd rcx, 1\ncmp ebx, ecx\njg short loc_11A1\nlea rcx, [rdx+1]\ncmp rdx, r13\njnz short loc_1191\nloc_11CF:\nmov [r12], edi\nmov [r12+4], esi\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_11E2:\nmov eax, 0\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1169(int *a1, int a2, _DWORD *a3)\n{\n int v6; // edi\n int v7; // esi\n __int64 i; // rdx\n int v9; // r11d\n __int64 v10; // rcx\n int v11; // r10d\n int v12; // r8d\n\n if ( a2 <= 1 )\n return 0LL;\n v6 = *a1;\n v7 = a1[1];\n for ( i = 1LL; i != a2; ++i )\n {\n v9 = a1[i - 1];\n v10 = i;\n do\n {\n v11 = a1[v10];\n v12 = v7 * v6;\n if ( v11 * v9 > v7 * v6 )\n v7 = a1[v10];\n if ( v11 * v9 > v12 )\n v6 = a1[i - 1];\n ++v10;\n }\n while ( a2 > (int)v10 );\n if ( i == a2 )\n break;\n }\n *a3 = v6;\n a3[1] = v7;\n return a3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1169(int *a1, int a2, uint32_t *a3) {\n int v6;\n int v7;\n long long i;\n int v9;\n long long v10;\n int v11;\n int v12;\n if (a2 <= 1) return 0LL;\n v6 = *a1;\n v7 = a1[1];\n for (i = 1LL; i != a2; ++i) {\n v9 = a1[i - 1];\n v10 = i;\n do {\n v11 = a1[v10];\n v12 = v7 * v6;\n if (v11 * v9 > v7 * v6) v7 = a1[v10];\n if (v11 * v9 > v12) v6 = a1[i - 1];\n ++v10;\n } while (a2 > (int)v10);\n if (i == a2) break;\n }\n *a3 = v6;\n a3[1] = v7;\n return a3;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2, uint32_t *a3) {\n int v6;\n int v7;\n long long i;\n int v9;\n long long v10;\n int v11;\n int v12;\n if (a2 <= 1) return 0LL;\n v6 = *a1;\n v7 = a1[1];\n for (i = 1LL; i != a2; ++i) {\n v9 = a1[i - 1];\n v10 = i;\n do {\n v11 = a1[v10];\n v12 = v7 * v6;\n if (v11 * v9 > v7 * v6) v7 = a1[v10];\n if (v11 * v9 > v12) v6 = a1[i - 1];\n ++v10;\n } while (a2 > (int)v10);\n if (i == a2) break;\n }\n *a3 = v6;\n a3[1] = v7;\n return a3;\n}" + }, + { + "index": 415, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int arr[], int arr_len, int result[2]) {\n if (arr_len < 2) {\n return NULL;\n }\n int x = arr[0];\n int y = arr[1];\n for (int i = 0; i < arr_len; i++) {\n for (int j = i + 1; j < arr_len; j++) {\n if (arr[i] * arr[j] > x * y) {\n x = arr[i];\n y = arr[j];\n }\n }\n }\n result[0] = x;\n result[1] = y;\n return result;\n}", + "test": "int main() {\n\n int result1[2];\n\n int arr1[] = {1,2,3,4,7,0,8,4};\n\n func0(arr1, 8, result1);\n\n assert(result1[0] == 7 && result1[1] == 8);\n\n\n\n int result2[2];\n\n int arr2[] = {0,-1,-2,-4,5,0,-6};\n\n func0(arr2, 7, result2);\n\n assert(result2[0] == -4 && result2[1] == -6);\n\n\n\n int result3[2];\n\n int arr3[] = {1,2,3};\n\n func0(arr3, 3, result3);\n\n assert(result3[0] == 2 && result3[1] == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%esi\njle 143e \nmov (%rdi),%r8d\nmov 0x4(%rdi),%r9d\npush %rbp\nmov $0x1,%ecx\npush %rbx\nmov %rdx,%rbp\nmov $0x1,%ebx\nmov %r8d,%edx\nnopw 0x0(%rax,%rax,1)\nmovslq %ecx,%r10\nmov (%rdi,%r10,4),%eax\nmov %r9d,%r10d\nimul %r8d,%r10d\nmov %eax,%r11d\nimul %edx,%r11d\ncmp %r10d,%r11d\ncmovg %eax,%r9d\ncmovg %edx,%r8d\nadd $0x1,%ecx\ncmp %ecx,%esi\njg 13f8 \nlea 0x1(%rbx),%ecx\ncmp %ecx,%esi\njle 1430 \nmov (%rdi,%rbx,4),%edx\nmovslq %ecx,%rbx\njmp 13f8 \nxchg %ax,%ax\nmov %r8d,0x0(%rbp)\nmov %rbp,%rax\nmov %r9d,0x4(%rbp)\npop %rbx\npop %rbp\nretq\nxor %eax,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ncmp esi, 1\njle short loc_133D\npush r12\nmov r12d, esi\npush rbp\nmov rbp, rdx\nmov edx, 1\npush rbx\nmov rbx, rdi\nmov r8d, [rdi]\nmov edi, [rdi+4]\nnop dword ptr [rax+00000000h]\nloc_12F8:\nmov r10d, [rbx+rdx*4-4]\nmov rcx, rdx\nloc_1300:\nmov r9d, [rbx+rcx*4]\nmov r11d, r8d\nmov eax, r10d\nimul r11d, edi\nimul eax, r9d\ncmp eax, r11d\ncmovg edi, r9d\ncmovg r8d, r10d\nadd rcx, 1\ncmp esi, ecx\njg short loc_1300\nadd rdx, 1\ncmp rdx, r12\njnz short loc_12F8\nmov [rbp+0], r8d\nmov rax, rbp\nmov [rbp+4], edi\npop rbx\npop rbp\npop r12\nretn\nloc_133D:\nxor eax, eax\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2, _DWORD *a3)\n{\n __int64 v4; // rdx\n int v6; // r8d\n int v7; // edi\n int v8; // r10d\n __int64 v9; // rcx\n int v10; // r9d\n int v11; // r11d\n _DWORD *result; // rax\n\n if ( a2 <= 1 )\n return 0LL;\n v4 = 1LL;\n v6 = *a1;\n v7 = a1[1];\n do\n {\n v8 = a1[v4 - 1];\n v9 = v4;\n do\n {\n v10 = a1[v9];\n v11 = v7 * v6;\n if ( v10 * v8 > v7 * v6 )\n v7 = a1[v9];\n if ( v10 * v8 > v11 )\n v6 = a1[v4 - 1];\n ++v9;\n }\n while ( a2 > (int)v9 );\n ++v4;\n }\n while ( v4 != a2 );\n *a3 = v6;\n result = a3;\n a3[1] = v7;\n return result;\n}", + "ida_strip_asm": "sub_12D0:\nendbr64\ncmp esi, 1\njle short loc_133D\npush r12\nmov r12d, esi\npush rbp\nmov rbp, rdx\nmov edx, 1\npush rbx\nmov rbx, rdi\nmov r8d, [rdi]\nmov edi, [rdi+4]\nnop dword ptr [rax+00000000h]\nloc_12F8:\nmov r10d, [rbx+rdx*4-4]\nmov rcx, rdx\nloc_1300:\nmov r9d, [rbx+rcx*4]\nmov r11d, r8d\nmov eax, r10d\nimul r11d, edi\nimul eax, r9d\ncmp eax, r11d\ncmovg edi, r9d\ncmovg r8d, r10d\nadd rcx, 1\ncmp esi, ecx\njg short loc_1300\nadd rdx, 1\ncmp rdx, r12\njnz short loc_12F8\nmov [rbp+0], r8d\nmov rax, rbp\nmov [rbp+4], edi\npop rbx\npop rbp\npop r12\nretn\nloc_133D:\nxor eax, eax\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_12D0(int *a1, int a2, _DWORD *a3)\n{\n __int64 v4; // rdx\n int v6; // r8d\n int v7; // edi\n int v8; // r10d\n __int64 v9; // rcx\n int v10; // r9d\n int v11; // r11d\n _DWORD *result; // rax\n\n if ( a2 <= 1 )\n return 0LL;\n v4 = 1LL;\n v6 = *a1;\n v7 = a1[1];\n do\n {\n v8 = a1[v4 - 1];\n v9 = v4;\n do\n {\n v10 = a1[v9];\n v11 = v7 * v6;\n if ( v10 * v8 > v7 * v6 )\n v7 = a1[v9];\n if ( v10 * v8 > v11 )\n v6 = a1[v4 - 1];\n ++v9;\n }\n while ( a2 > (int)v9 );\n ++v4;\n }\n while ( v4 != a2 );\n *a3 = v6;\n result = a3;\n a3[1] = v7;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_12D0(int *a1, int a2, uint32_t *a3) {\n long long v4;\n int v6;\n int v7;\n int v8;\n long long v9;\n int v10;\n int v11;\n uint32_t *result;\n if (a2 <= 1) return 0LL;\n v4 = 1LL;\n v6 = *a1;\n v7 = a1[1];\n do {\n v8 = a1[v4 - 1];\n v9 = v4;\n do {\n v10 = a1[v9];\n v11 = v7 * v6;\n if (v10 * v8 > v7 * v6) v7 = a1[v9];\n if (v10 * v8 > v11) v6 = a1[v4 - 1];\n ++v9;\n } while (a2 > (int)v9);\n ++v4;\n } while (v4 != a2);\n *a3 = v6;\n result = a3;\n a3[1] = v7;\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2, uint32_t *a3) {\n long long v4;\n int v6;\n int v7;\n int v8;\n long long v9;\n int v10;\n int v11;\n uint32_t *result;\n if (a2 <= 1) return 0LL;\n v4 = 1LL;\n v6 = *a1;\n v7 = a1[1];\n do {\n v8 = a1[v4 - 1];\n v9 = v4;\n do {\n v10 = a1[v9];\n v11 = v7 * v6;\n if (v10 * v8 > v7 * v6) v7 = a1[v9];\n if (v10 * v8 > v11) v6 = a1[v4 - 1];\n ++v9;\n } while (a2 > (int)v9);\n ++v4;\n } while (v4 != a2);\n *a3 = v6;\n result = a3;\n a3[1] = v7;\n return result;\n}" + }, + { + "index": 416, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n#define MAX 1000000\n\n\n\n", + "func": "int func0(int n) {\n int dp[n + 1];\n dp[0] = 0;\n dp[1] = 1;\n for (int i = 2; i <= n; i++) {\n dp[i] = dp[i / 2] + dp[i / 3] + dp[i / 4];\n if (dp[i] < i) {\n dp[i] = i;\n }\n }\n return dp[n];\n}", + "test": "int main() {\n\n assert(func0(12) == 13);\n\n assert(func0(24) == 27);\n\n assert(func0(23) == 23);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x38,%rsp\nmov %edi,-0x34(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmov %rsp,%rax\nmov %rax,%rsi\nmov -0x34(%rbp),%eax\nadd $0x1,%eax\nmovslq %eax,%rdx\nsub $0x1,%rdx\nmov %rdx,-0x28(%rbp)\nmovslq %eax,%rdx\nmov %rdx,%r8\nmov $0x0,%r9d\nmovslq %eax,%rdx\nmov %rdx,%rcx\nmov $0x0,%ebx\ncltq\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%edi\nmov $0x0,%edx\ndiv %rdi\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rbx\nsub %rdx,%rbx\nmov %rbx,%rdx\ncmp %rdx,%rsp\nje 1207 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11f0 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 1231 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x20(%rbp)\nmov -0x20(%rbp),%rax\nmovl $0x0,(%rax)\nmov -0x20(%rbp),%rax\nmovl $0x1,0x4(%rax)\nmovl $0x2,-0x2c(%rbp)\njmpq 12ee \nmov -0x2c(%rbp),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nmov %eax,%edx\nmov -0x20(%rbp),%rax\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%ecx\nmov -0x2c(%rbp),%eax\nmovslq %eax,%rdx\nimul $0x55555556,%rdx,%rdx\nshr $0x20,%rdx\nsar $0x1f,%eax\nsub %eax,%edx\nmov -0x20(%rbp),%rax\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nadd %eax,%ecx\nmov -0x2c(%rbp),%eax\nlea 0x3(%rax),%edx\ntest %eax,%eax\ncmovs %edx,%eax\nsar $0x2,%eax\nmov %eax,%edx\nmov -0x20(%rbp),%rax\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nadd %eax,%ecx\nmov -0x20(%rbp),%rax\nmov -0x2c(%rbp),%edx\nmovslq %edx,%rdx\nmov %ecx,(%rax,%rdx,4)\nmov -0x20(%rbp),%rax\nmov -0x2c(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\ncmp %eax,-0x2c(%rbp)\njle 12ea \nmov -0x20(%rbp),%rax\nmov -0x2c(%rbp),%edx\nmovslq %edx,%rdx\nmov -0x2c(%rbp),%ecx\nmov %ecx,(%rax,%rdx,4)\naddl $0x1,-0x2c(%rbp)\nmov -0x2c(%rbp),%eax\ncmp -0x34(%rbp),%eax\njle 1265 \nmov -0x20(%rbp),%rax\nmov -0x34(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nmov %rsi,%rsp\nmov -0x18(%rbp),%rdi\nxor %fs:0x28,%rdi\nje 131e \ncallq 1060 <__stack_chk_fail@plt>\nmov -0x8(%rbp),%rbx\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_24], edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov eax, [rbp+var_24]\nadd eax, 1\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11D5:\ncmp rsp, rdx\njz short loc_11EC\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\njmp short loc_11D5\nloc_11EC:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1216\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1216:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov rax, [rbp+var_10]\nmov dword ptr [rax], 0\nmov rax, [rbp+var_10]\nmov dword ptr [rax+4], 1\nmov [rbp+var_1C], 2\njmp loc_12D3\nloc_124A:\nmov eax, [rbp+var_1C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov edx, eax\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov eax, [rbp+var_1C]\nmovsxd rdx, eax\nimul rdx, 55555556h\nshr rdx, 20h\nsar eax, 1Fh\nsub edx, eax\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nadd ecx, eax\nmov eax, [rbp+var_1C]\nlea edx, [rax+3]\ntest eax, eax\ncmovs eax, edx\nsar eax, 2\nmov edx, eax\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nadd ecx, eax\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ncmp [rbp+var_1C], eax\njle short loc_12CF\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov ecx, [rbp+var_1C]\nmov [rax+rdx*4], ecx\nloc_12CF:\nadd [rbp+var_1C], 1\nloc_12D3:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_24]\njle loc_124A\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1303\ncall ___stack_chk_fail\nlocret_1303:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned __int64 v1; // rax\n void *v2; // rsp\n _DWORD v4[3]; // [rsp+8h] [rbp-30h] BYREF\n int v5; // [rsp+14h] [rbp-24h]\n int i; // [rsp+1Ch] [rbp-1Ch]\n __int64 v7; // [rsp+20h] [rbp-18h]\n _DWORD *v8; // [rsp+28h] [rbp-10h]\n unsigned __int64 v9; // [rsp+30h] [rbp-8h]\n\n v5 = a1;\n v9 = __readfsqword(0x28u);\n v7 = a1 + 1 - 1LL;\n v1 = 16 * ((4LL * (a1 + 1) + 15) / 0x10uLL);\n while ( v4 != (_DWORD *)((char *)v4 - (v1 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v2 = alloca(v1 & 0xFFF);\n if ( (v1 & 0xFFF) != 0 )\n *(_QWORD *)((char *)&v4[-2] + (v1 & 0xFFF)) = *(_QWORD *)((char *)&v4[-2] + (v1 & 0xFFF));\n v8 = v4;\n v4[0] = 0;\n v4[1] = 1;\n for ( i = 2; i <= v5; ++i )\n {\n v8[i] = v8[i / 4] + v8[i / 3] + v8[i / 2];\n if ( i > v8[i] )\n v8[i] = i;\n }\n return (unsigned int)v8[v5];\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_24], edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov eax, [rbp+var_24]\nadd eax, 1\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11D5:\ncmp rsp, rdx\njz short loc_11EC\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\njmp short loc_11D5\nloc_11EC:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1216\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1216:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov rax, [rbp+var_10]\nmov dword ptr [rax], 0\nmov rax, [rbp+var_10]\nmov dword ptr [rax+4], 1\nmov [rbp+var_1C], 2\njmp loc_12D3\nloc_124A:\nmov eax, [rbp+var_1C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov edx, eax\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov eax, [rbp+var_1C]\nmovsxd rdx, eax\nimul rdx, 55555556h\nshr rdx, 20h\nsar eax, 1Fh\nsub edx, eax\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nadd ecx, eax\nmov eax, [rbp+var_1C]\nlea edx, [rax+3]\ntest eax, eax\ncmovs eax, edx\nsar eax, 2\nmov edx, eax\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nadd ecx, eax\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ncmp [rbp+var_1C], eax\njle short loc_12CF\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov ecx, [rbp+var_1C]\nmov [rax+rdx*4], ecx\nloc_12CF:\nadd [rbp+var_1C], 1\nloc_12D3:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_24]\njle loc_124A\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1303\ncall ___stack_chk_fail\nlocret_1303:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n unsigned __int64 v1; // rax\n void *v2; // rsp\n _DWORD v4[3]; // [rsp+8h] [rbp-30h] BYREF\n int v5; // [rsp+14h] [rbp-24h]\n int i; // [rsp+1Ch] [rbp-1Ch]\n __int64 v7; // [rsp+20h] [rbp-18h]\n _DWORD *v8; // [rsp+28h] [rbp-10h]\n unsigned __int64 v9; // [rsp+30h] [rbp-8h]\n\n v5 = a1;\n v9 = __readfsqword(0x28u);\n v7 = a1 + 1 - 1LL;\n v1 = 16 * ((4LL * (a1 + 1) + 15) / 0x10uLL);\n while ( v4 != (_DWORD *)((char *)v4 - (v1 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v2 = alloca(v1 & 0xFFF);\n if ( (v1 & 0xFFF) != 0 )\n *(_QWORD *)((char *)&v4[-2] + (v1 & 0xFFF)) = *(_QWORD *)((char *)&v4[-2] + (v1 & 0xFFF));\n v8 = v4;\n v4[0] = 0;\n v4[1] = 1;\n for ( i = 2; i <= v5; ++i )\n {\n v8[i] = v8[i / 4] + v8[i / 3] + v8[i / 2];\n if ( i > v8[i] )\n v8[i] = i;\n }\n return (unsigned int)v8[v5];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n unsigned long long v1;\n void *v2;\n uint32_t v4[3];\n int v5;\n int i;\n long long v7;\n uint32_t *v8;\n unsigned long long v9;\n v5 = a1;\n v9 = __readfsqword(40u);\n v7 = a1 + 1 - 1LL;\n v1 = 16 * ((4LL * (a1 + 1) + 15) / 16uLL);\n while (v4 != (uint32_t *)((char *)v4 - (v1 & 18446744073709547520LL)))\n ;\n v2 = alloca(v1 & 4095);\n if ((v1 & 4095) != 0)\n *(uint64_t *)((char *)&v4[-2] + (v1 & 4095)) =\n *(uint64_t *)((char *)&v4[-2] + (v1 & 4095));\n v8 = v4;\n v4[0] = 0;\n v4[1] = 1;\n for (i = 2; i <= v5; ++i) {\n v8[i] = v8[i / 4] + v8[i / 3] + v8[i / 2];\n if (i > v8[i]) v8[i] = i;\n }\n return (unsigned int)v8[v5];\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned long long v1;\n void *v2;\n uint32_t v4[3];\n int v5;\n int i;\n long long v7;\n uint32_t *v8;\n unsigned long long v9;\n v5 = a1;\n v9 = __readfsqword(40u);\n v7 = a1 + 1 - 1LL;\n v1 = 16 * ((4LL * (a1 + 1) + 15) / 16uLL);\n while (v4 != (uint32_t *)((char *)v4 - (v1 & 18446744073709547520LL)))\n ;\n v2 = alloca(v1 & 4095);\n if ((v1 & 4095) != 0)\n *(uint64_t *)((char *)&v4[-2] + (v1 & 4095)) =\n *(uint64_t *)((char *)&v4[-2] + (v1 & 4095));\n v8 = v4;\n v4[0] = 0;\n v4[1] = 1;\n for (i = 2; i <= v5; ++i) {\n v8[i] = v8[i / 4] + v8[i / 3] + v8[i / 2];\n if (i > v8[i]) v8[i] = i;\n }\n return (unsigned int)v8[v5];\n}" + }, + { + "index": 416, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n#define MAX 1000000\n\n\n\n", + "func": "int func0(int n) {\n int dp[n + 1];\n dp[0] = 0;\n dp[1] = 1;\n for (int i = 2; i <= n; i++) {\n dp[i] = dp[i / 2] + dp[i / 3] + dp[i / 4];\n if (dp[i] < i) {\n dp[i] = i;\n }\n }\n return dp[n];\n}", + "test": "int main() {\n\n assert(func0(12) == 13);\n\n assert(func0(24) == 27);\n\n assert(func0(23) == 23);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0x1(%rdi),%eax\ncltq\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffffff0,%rdx\nand $0xfffffffffffff000,%rax\nmov %rsp,%rsi\nsub %rax,%rsi\nmov %rsi,%rax\ncmp %rax,%rsp\nje 11be \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11a7 \nmov %rdx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 11d4 \norq $0x0,-0x8(%rsp,%rax,1)\nlea 0x3(%rsp),%r8\nmov %r8,%rax\nshr $0x2,%rax\nand $0xfffffffffffffffc,%r8\nmov %r8,%rcx\nmovl $0x0,0x0(,%rax,4)\nmovl $0x1,0x4(,%rax,4)\ncmp $0x1,%edi\njle 1266 \nlea -0x2(%rdi),%esi\nadd $0x3,%rsi\nmov $0x2,%eax\nmov %eax,%r9d\nshr $0x1f,%r9d\nadd %eax,%r9d\nsar %r9d\nmovslq %r9d,%r9\nmovslq %eax,%rdx\nimul $0x55555556,%rdx,%rdx\nshr $0x20,%rdx\nmov %eax,%r10d\nsar $0x1f,%r10d\nsub %r10d,%edx\nmovslq %edx,%rdx\nmov (%rcx,%rdx,4),%edx\nadd (%rcx,%r9,4),%edx\nlea 0x3(%rax),%r9d\ntest %eax,%eax\ncmovns %eax,%r9d\nsar $0x2,%r9d\nmovslq %r9d,%r9\nadd (%rcx,%r9,4),%edx\ncmp %eax,%edx\ncmovl %eax,%edx\nmov %edx,(%rcx,%rax,4)\nadd $0x1,%rax\ncmp %rsi,%rax\njne 120e \nmovslq %edi,%rdi\nmov (%r8,%rdi,4),%eax\nmov -0x8(%rbp),%rdi\nxor %fs:0x28,%rdi\njne 127e \nleaveq\nretq\ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov r8d, edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea eax, [rdi+1]\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11A7:\ncmp rsp, rdx\njz short loc_11BE\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11A7\nloc_11BE:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11D4\nor [rsp+rax+10h+var_18], 0\nloc_11D4:\nlea rcx, [rsp+10h+var_D]\nmov rax, rcx\nshr rax, 2\nand rcx, 0FFFFFFFFFFFFFFFCh\nmov ds:dword_0[rax*4], 0\nmov dword ptr ds:byte_4[rax*4], 1\ncmp r8d, 1\njle short loc_126E\nlea edi, [r8+1]\nmov eax, 2\njmp short loc_1217\nloc_120B:\nmov [rcx+rax*4], esi\nadd rax, 1\ncmp rax, rdi\njz short loc_126E\nloc_1217:\nmov esi, eax\nmov r9d, eax\nshr r9d, 1Fh\nadd r9d, eax\nsar r9d, 1\nmovsxd r9, r9d\nmovsxd rdx, eax\nimul rdx, 55555556h\nshr rdx, 20h\nmov r10d, eax\nsar r10d, 1Fh\nsub edx, r10d\nmovsxd rdx, edx\nmov edx, [rcx+rdx*4]\nadd edx, [rcx+r9*4]\nmov r9d, edx\nlea edx, [rax+3]\ntest eax, eax\ncmovns edx, eax\nsar edx, 2\nmovsxd rdx, edx\nadd r9d, [rcx+rdx*4]\nmov [rcx+rax*4], r9d\ncmp r9d, eax\njl short loc_120B\nmov esi, r9d\njmp short loc_120B\nloc_126E:\nmovsxd r8, r8d\nmov eax, [rcx+r8*4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_1286\nleave\nretn\nloc_1286:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n signed __int64 v2; // rax\n void *v3; // rsp\n unsigned __int64 v4; // rax\n __int64 v5; // rdi\n __int64 v6; // rax\n int v7; // esi\n int v8; // r9d\n _BYTE v11[3]; // [rsp+8h] [rbp-10h] BYREF\n char v12; // [rsp+Bh] [rbp-Dh] BYREF\n unsigned __int64 v13; // [rsp+10h] [rbp-8h]\n\n v13 = __readfsqword(0x28u);\n while ( v11 != &v11[-((4LL * (a1 + 1) + 15) & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v2 = (4 * ((_WORD)a1 + 1) + 15) & 0xFF0;\n v3 = alloca(v2);\n if ( ((4 * ((_WORD)a1 + 1) + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v11[v2 - 8] = *(_QWORD *)&v11[v2 - 8];\n v4 = (unsigned __int64)&v12 >> 2;\n *(_DWORD *)(4 * v4) = 0;\n *(_DWORD *)&byte_4[4 * v4] = 1;\n if ( a1 > 1 )\n {\n v5 = (unsigned int)(a1 + 1);\n v6 = 2LL;\n do\n {\n v7 = v6;\n v8 = *(_DWORD *)&v11[4 * ((int)v6 / 4)] + *(_DWORD *)&v11[4 * ((int)v6 / 2)] + *(_DWORD *)&v11[4 * ((int)v6 / 3)];\n *(_DWORD *)&v11[4 * v6] = v8;\n if ( v8 >= (int)v6 )\n v7 = v8;\n *(_DWORD *)&v11[4 * v6++] = v7;\n }\n while ( v6 != v5 );\n }\n return *(unsigned int *)&v11[4 * a1];\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov r8d, edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea eax, [rdi+1]\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11A7:\ncmp rsp, rdx\njz short loc_11BE\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11A7\nloc_11BE:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11D4\nor [rsp+rax+10h+var_18], 0\nloc_11D4:\nlea rcx, [rsp+10h+var_D]\nmov rax, rcx\nshr rax, 2\nand rcx, 0FFFFFFFFFFFFFFFCh\nmov ds:dword_0[rax*4], 0\nmov dword ptr ds:byte_4[rax*4], 1\ncmp r8d, 1\njle short loc_126E\nlea edi, [r8+1]\nmov eax, 2\njmp short loc_1217\nloc_120B:\nmov [rcx+rax*4], esi\nadd rax, 1\ncmp rax, rdi\njz short loc_126E\nloc_1217:\nmov esi, eax\nmov r9d, eax\nshr r9d, 1Fh\nadd r9d, eax\nsar r9d, 1\nmovsxd r9, r9d\nmovsxd rdx, eax\nimul rdx, 55555556h\nshr rdx, 20h\nmov r10d, eax\nsar r10d, 1Fh\nsub edx, r10d\nmovsxd rdx, edx\nmov edx, [rcx+rdx*4]\nadd edx, [rcx+r9*4]\nmov r9d, edx\nlea edx, [rax+3]\ntest eax, eax\ncmovns edx, eax\nsar edx, 2\nmovsxd rdx, edx\nadd r9d, [rcx+rdx*4]\nmov [rcx+rax*4], r9d\ncmp r9d, eax\njl short loc_120B\nmov esi, r9d\njmp short loc_120B\nloc_126E:\nmovsxd r8, r8d\nmov eax, [rcx+r8*4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_1286\nleave\nretn\nloc_1286:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n signed __int64 v2; // rax\n void *v3; // rsp\n unsigned __int64 v4; // rax\n __int64 v5; // rdi\n __int64 v6; // rax\n int v7; // esi\n int v8; // r9d\n _BYTE v11[3]; // [rsp+8h] [rbp-10h] BYREF\n char v12; // [rsp+Bh] [rbp-Dh] BYREF\n unsigned __int64 v13; // [rsp+10h] [rbp-8h]\n\n v13 = __readfsqword(0x28u);\n while ( v11 != &v11[-((4LL * (a1 + 1) + 15) & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v2 = (4 * ((_WORD)a1 + 1) + 15) & 0xFF0;\n v3 = alloca(v2);\n if ( ((4 * ((_WORD)a1 + 1) + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v11[v2 - 8] = *(_QWORD *)&v11[v2 - 8];\n v4 = (unsigned __int64)&v12 >> 2;\n *(_DWORD *)(4 * v4) = 0;\n *(_DWORD *)&byte_4[4 * v4] = 1;\n if ( a1 > 1 )\n {\n v5 = (unsigned int)(a1 + 1);\n v6 = 2LL;\n do\n {\n v7 = v6;\n v8 = *(_DWORD *)&v11[4 * ((int)v6 / 4)] + *(_DWORD *)&v11[4 * ((int)v6 / 2)] + *(_DWORD *)&v11[4 * ((int)v6 / 3)];\n *(_DWORD *)&v11[4 * v6] = v8;\n if ( v8 >= (int)v6 )\n v7 = v8;\n *(_DWORD *)&v11[4 * v6++] = v7;\n }\n while ( v6 != v5 );\n }\n return *(unsigned int *)&v11[4 * a1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n signed long long v2;\n void *v3;\n unsigned long long v4;\n long long v5;\n long long v6;\n int v7;\n int v8;\n uint8_t v11[3];\n char v12;\n unsigned long long v13;\n v13 = __readfsqword(40u);\n while (v11 != &v11[-((4LL * (a1 + 1) + 15) & 18446744073709547520LL)])\n ;\n v2 = (4 * ((unsigned short)a1 + 1) + 15) & 4080;\n v3 = alloca(v2);\n if (((4 * ((unsigned short)a1 + 1) + 15) & 4080) != 0)\n *(uint64_t *)&v11[v2 - 8] = *(uint64_t *)&v11[v2 - 8];\n v4 = (unsigned long long)&v12 >> 2;\n *(uint32_t *)(4 * v4) = 0;\n *(uint32_t *)&byte_4[4 * v4] = 1;\n if (a1 > 1) {\n v5 = (unsigned int)(a1 + 1);\n v6 = 2LL;\n do {\n v7 = v6;\n v8 = *(uint32_t *)&v11[4 * ((int)v6 / 4)] +\n *(uint32_t *)&v11[4 * ((int)v6 / 2)] +\n *(uint32_t *)&v11[4 * ((int)v6 / 3)];\n *(uint32_t *)&v11[4 * v6] = v8;\n if (v8 >= (int)v6) v7 = v8;\n *(uint32_t *)&v11[4 * v6++] = v7;\n } while (v6 != v5);\n }\n return *(unsigned int *)&v11[4 * a1];\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n signed long long v2;\n void *v3;\n unsigned long long v4;\n long long v5;\n long long v6;\n int v7;\n int v8;\n uint8_t v11[3];\n char v12;\n unsigned long long v13;\n v13 = __readfsqword(40u);\n while (v11 != &v11[-((4LL * (a1 + 1) + 15) & 18446744073709547520LL)])\n ;\n v2 = (4 * ((unsigned short)a1 + 1) + 15) & 4080;\n v3 = alloca(v2);\n if (((4 * ((unsigned short)a1 + 1) + 15) & 4080) != 0)\n *(uint64_t *)&v11[v2 - 8] = *(uint64_t *)&v11[v2 - 8];\n v4 = (unsigned long long)&v12 >> 2;\n *(uint32_t *)(4 * v4) = 0;\n *(uint32_t *)&byte_4[4 * v4] = 1;\n if (a1 > 1) {\n v5 = (unsigned int)(a1 + 1);\n v6 = 2LL;\n do {\n v7 = v6;\n v8 = *(uint32_t *)&v11[4 * ((int)v6 / 4)] +\n *(uint32_t *)&v11[4 * ((int)v6 / 2)] +\n *(uint32_t *)&v11[4 * ((int)v6 / 3)];\n *(uint32_t *)&v11[4 * v6] = v8;\n if (v8 >= (int)v6) v7 = v8;\n *(uint32_t *)&v11[4 * v6++] = v7;\n } while (v6 != v5);\n }\n return *(unsigned int *)&v11[4 * a1];\n}" + }, + { + "index": 416, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n#define MAX 1000000\n\n\n\n", + "func": "int func0(int n) {\n int dp[n + 1];\n dp[0] = 0;\n dp[1] = 1;\n for (int i = 2; i <= n; i++) {\n dp[i] = dp[i / 2] + dp[i / 3] + dp[i / 4];\n if (dp[i] < i) {\n dp[i] = i;\n }\n }\n return dp[n];\n}", + "test": "int main() {\n\n assert(func0(12) == 13);\n\n assert(func0(24) == 27);\n\n assert(func0(23) == 23);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0x1(%rdi),%eax\nmov %rsp,%rcx\ncltq\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rcx\nand $0xfffffffffffffff0,%rdx\nmov %rcx,%rax\ncmp %rax,%rsp\nje 1268 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 1253 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 1318 \nmovabs $0x100000000,%rcx\nlea 0x3(%rsp),%r8\nmov %r8,%rax\nand $0xfffffffffffffffc,%r8\nshr $0x2,%rax\nmov %rcx,0x0(,%rax,4)\ncmp $0x1,%edi\njle 12fb \nlea -0x2(%rdi),%r9d\nmov $0x2,%ecx\nxor %edx,%edx\nxor %esi,%esi\nadd $0x3,%r9\nmov $0x1,%eax\nmov $0xaaaaaaab,%r10d\njmp 12e2 \nmov %edx,%esi\nmov %edx,%eax\nsar $0x2,%edx\nimul %r10,%rsi\nsar %eax\nmovslq %edx,%rdx\ncltq\nmov (%r8,%rdx,4),%edx\nmov (%r8,%rax,4),%eax\nshr $0x21,%rsi\nmov (%r8,%rsi,4),%esi\nadd %esi,%eax\nadd %edx,%eax\nlea 0x1(%rcx),%edx\ncmp %ecx,%eax\ncmovl %ecx,%eax\nmov %eax,(%r8,%rcx,4)\nadd $0x1,%rcx\ncmp %rcx,%r9\njne 12c0 \nmovslq %edi,%rdi\nmov (%r8,%rdi,4),%eax\nmov -0x8(%rbp),%rdi\nxor %fs:0x28,%rdi\njne 1323 \nleaveq\nretq\nnopl 0x0(%rax,%rax,1)\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 127a \ncallq 1060 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmovsxd r10, edi\nlea r8d, [r10+1]\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmovsxd rax, r8d\nmov rcx, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_126A\nloc_1255:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rcx\njnz short loc_1255\nloc_126A:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1310\nloc_127C:\nlea rdi, [rsp+1010h+var_100D]\nmov rdx, cs:qword_2060\nmov rax, rdi\nand rdi, 0FFFFFFFFFFFFFFFCh\nshr rax, 2\nmov qword ptr ds:dword_0[rax*4], rdx\ncmp r10d, 1\njle short loc_12F7\nmov r8d, r8d\nmov ecx, 2\nxor edx, edx\nxor esi, esi\nmov eax, 1\nmov r9d, 0AAAAAAABh\njmp short loc_12DF\nloc_12C0:\nmov esi, edx\nmov eax, edx\nsar edx, 2\nimul rsi, r9\nsar eax, 1\nmovsxd rdx, edx\ncdqe\nmov edx, [rdi+rdx*4]\nmov eax, [rdi+rax*4]\nshr rsi, 21h\nmov esi, [rdi+rsi*4]\nloc_12DF:\nadd eax, esi\nadd eax, edx\nlea edx, [rcx+1]\ncmp eax, ecx\ncmovl eax, ecx\nmov [rdi+rcx*4], eax\nadd rcx, 1\ncmp rcx, r8\njnz short loc_12C0\nloc_12F7:\nmov eax, [rdi+r10*4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_131B\nleave\nretn\nloc_1310:\nor [rsp+rdx+1010h+var_1018], 0\njmp loc_127C\nloc_131B:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n __int64 v1; // rdx\n _QWORD *v2; // rcx\n __int16 v3; // dx\n signed __int64 v4; // rdx\n void *v5; // rsp\n __int64 v6; // rcx\n int v7; // edx\n int v8; // esi\n int v9; // eax\n int v10; // eax\n unsigned int v11; // kr00_4\n int v12; // eax\n int v13; // edx\n _QWORD v16[511]; // [rsp+8h] [rbp-1010h] BYREF\n _QWORD v17[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v17[1] = __readfsqword(0x28u);\n v1 = 4LL * (a1 + 1) + 15;\n v2 = (_QWORD *)((char *)v17 - (v1 & 0xFFFFFFFFFFFFF000LL));\n v3 = v1 & 0xFFF0;\n if ( v17 != v2 )\n {\n while ( v16 != v2 )\n ;\n }\n v4 = v3 & 0xFFF;\n v5 = alloca(v4);\n if ( v4 )\n *(_QWORD *)((char *)&v16[-1] + v4) = *(_QWORD *)((char *)&v16[-1] + v4);\n v16[0] = 0x100000000LL;\n if ( a1 > 1 )\n {\n v6 = 2LL;\n v7 = 0;\n v8 = 0;\n v9 = 1;\n while ( 1 )\n {\n v12 = v7 + v8 + v9;\n v13 = v6 + 1;\n if ( v12 < (int)v6 )\n v12 = v6;\n *((_DWORD *)v16 + v6++) = v12;\n if ( v6 == a1 + 1 )\n break;\n v10 = v13;\n v11 = v13;\n v7 = *((_DWORD *)v16 + (v13 >> 2));\n v9 = *((_DWORD *)v16 + (v10 >> 1));\n v8 = *((_DWORD *)v16 + v11 / 3uLL);\n }\n }\n return *((unsigned int *)v16 + a1);\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbp\nmovsxd r10, edi\nlea r8d, [r10+1]\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmovsxd rax, r8d\nmov rcx, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_126A\nloc_1255:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rcx\njnz short loc_1255\nloc_126A:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1310\nloc_127C:\nlea rdi, [rsp+1010h+var_100D]\nmov rdx, cs:qword_2060\nmov rax, rdi\nand rdi, 0FFFFFFFFFFFFFFFCh\nshr rax, 2\nmov qword ptr ds:dword_0[rax*4], rdx\ncmp r10d, 1\njle short loc_12F7\nmov r8d, r8d\nmov ecx, 2\nxor edx, edx\nxor esi, esi\nmov eax, 1\nmov r9d, 0AAAAAAABh\njmp short loc_12DF\nloc_12C0:\nmov esi, edx\nmov eax, edx\nsar edx, 2\nimul rsi, r9\nsar eax, 1\nmovsxd rdx, edx\ncdqe\nmov edx, [rdi+rdx*4]\nmov eax, [rdi+rax*4]\nshr rsi, 21h\nmov esi, [rdi+rsi*4]\nloc_12DF:\nadd eax, esi\nadd eax, edx\nlea edx, [rcx+1]\ncmp eax, ecx\ncmovl eax, ecx\nmov [rdi+rcx*4], eax\nadd rcx, 1\ncmp rcx, r8\njnz short loc_12C0\nloc_12F7:\nmov eax, [rdi+r10*4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_131B\nleave\nretn\nloc_1310:\nor [rsp+rdx+1010h+var_1018], 0\njmp loc_127C\nloc_131B:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(int a1)\n{\n __int64 v1; // rdx\n _QWORD *v2; // rcx\n __int16 v3; // dx\n signed __int64 v4; // rdx\n void *v5; // rsp\n __int64 v6; // rcx\n int v7; // edx\n int v8; // esi\n int v9; // eax\n int v10; // eax\n unsigned int v11; // kr00_4\n int v12; // eax\n int v13; // edx\n _QWORD v16[511]; // [rsp+8h] [rbp-1010h] BYREF\n _QWORD v17[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v17[1] = __readfsqword(0x28u);\n v1 = 4LL * (a1 + 1) + 15;\n v2 = (_QWORD *)((char *)v17 - (v1 & 0xFFFFFFFFFFFFF000LL));\n v3 = v1 & 0xFFF0;\n if ( v17 != v2 )\n {\n while ( v16 != v2 )\n ;\n }\n v4 = v3 & 0xFFF;\n v5 = alloca(v4);\n if ( v4 )\n *(_QWORD *)((char *)&v16[-1] + v4) = *(_QWORD *)((char *)&v16[-1] + v4);\n v16[0] = 0x100000000LL;\n if ( a1 > 1 )\n {\n v6 = 2LL;\n v7 = 0;\n v8 = 0;\n v9 = 1;\n while ( 1 )\n {\n v12 = v7 + v8 + v9;\n v13 = v6 + 1;\n if ( v12 < (int)v6 )\n v12 = v6;\n *((_DWORD *)v16 + v6++) = v12;\n if ( v6 == a1 + 1 )\n break;\n v10 = v13;\n v11 = v13;\n v7 = *((_DWORD *)v16 + (v13 >> 2));\n v9 = *((_DWORD *)v16 + (v10 >> 1));\n v8 = *((_DWORD *)v16 + v11 / 3uLL);\n }\n }\n return *((unsigned int *)v16 + a1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(int a1) {\n long long v1;\n uint64_t *v2;\n short v3;\n signed long long v4;\n void *v5;\n long long v6;\n int v7;\n int v8;\n int v9;\n int v10;\n unsigned int v11;\n int v12;\n int v13;\n uint64_t v16[511];\n uint64_t v17[2];\n v17[1] = __readfsqword(40u);\n v1 = 4LL * (a1 + 1) + 15;\n v2 = (uint64_t *)((char *)v17 - (v1 & 18446744073709547520LL));\n v3 = v1 & 65520;\n if (v17 != v2) {\n while (v16 != v2)\n ;\n }\n v4 = v3 & 4095;\n v5 = alloca(v4);\n if (v4)\n *(uint64_t *)((char *)&v16[-1] + v4) = *(uint64_t *)((char *)&v16[-1] + v4);\n v16[0] = 4294967296LL;\n if (a1 > 1) {\n v6 = 2LL;\n v7 = 0;\n v8 = 0;\n v9 = 1;\n while (1) {\n v12 = v7 + v8 + v9;\n v13 = v6 + 1;\n if (v12 < (int)v6) v12 = v6;\n *((uint32_t *)v16 + v6++) = v12;\n if (v6 == a1 + 1) break;\n v10 = v13;\n v11 = v13;\n v7 = *((uint32_t *)v16 + (v13 >> 2));\n v9 = *((uint32_t *)v16 + (v10 >> 1));\n v8 = *((uint32_t *)v16 + v11 / 3uLL);\n }\n }\n return *((unsigned int *)v16 + a1);\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n long long v1;\n uint64_t *v2;\n short v3;\n signed long long v4;\n void *v5;\n long long v6;\n int v7;\n int v8;\n int v9;\n int v10;\n unsigned int v11;\n int v12;\n int v13;\n uint64_t v16[511];\n uint64_t v17[2];\n v17[1] = __readfsqword(40u);\n v1 = 4LL * (a1 + 1) + 15;\n v2 = (uint64_t *)((char *)v17 - (v1 & 18446744073709547520LL));\n v3 = v1 & 65520;\n if (v17 != v2) {\n while (v16 != v2)\n ;\n }\n v4 = v3 & 4095;\n v5 = alloca(v4);\n if (v4)\n *(uint64_t *)((char *)&v16[-1] + v4) = *(uint64_t *)((char *)&v16[-1] + v4);\n v16[0] = 4294967296LL;\n if (a1 > 1) {\n v6 = 2LL;\n v7 = 0;\n v8 = 0;\n v9 = 1;\n while (1) {\n v12 = v7 + v8 + v9;\n v13 = v6 + 1;\n if (v12 < (int)v6) v12 = v6;\n *((uint32_t *)v16 + v6++) = v12;\n if (v6 == a1 + 1) break;\n v10 = v13;\n v11 = v13;\n v7 = *((uint32_t *)v16 + (v13 >> 2));\n v9 = *((uint32_t *)v16 + (v10 >> 1));\n v8 = *((uint32_t *)v16 + v11 / 3uLL);\n }\n }\n return *((unsigned int *)v16 + a1);\n}" + }, + { + "index": 416, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n#define MAX 1000000\n\n\n\n", + "func": "int func0(int n) {\n int dp[n + 1];\n dp[0] = 0;\n dp[1] = 1;\n for (int i = 2; i <= n; i++) {\n dp[i] = dp[i / 2] + dp[i / 3] + dp[i / 4];\n if (dp[i] < i) {\n dp[i] = i;\n }\n }\n return dp[n];\n}", + "test": "int main() {\n\n assert(func0(12) == 13);\n\n assert(func0(24) == 27);\n\n assert(func0(23) == 23);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0x1(%rdi),%eax\nmov %rsp,%rcx\ncltq\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rcx\nand $0xfffffffffffffff0,%rdx\nmov %rcx,%rax\ncmp %rax,%rsp\nje 1268 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 1253 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 1318 \nmovabs $0x100000000,%rcx\nlea 0x3(%rsp),%r8\nmov %r8,%rax\nand $0xfffffffffffffffc,%r8\nshr $0x2,%rax\nmov %rcx,0x0(,%rax,4)\ncmp $0x1,%edi\njle 12fb \nlea -0x2(%rdi),%r9d\nmov $0x2,%ecx\nxor %edx,%edx\nxor %esi,%esi\nadd $0x3,%r9\nmov $0x1,%eax\nmov $0xaaaaaaab,%r10d\njmp 12e2 \nmov %edx,%esi\nmov %edx,%eax\nsar $0x2,%edx\nimul %r10,%rsi\nsar %eax\nmovslq %edx,%rdx\ncltq\nmov (%r8,%rdx,4),%edx\nmov (%r8,%rax,4),%eax\nshr $0x21,%rsi\nmov (%r8,%rsi,4),%esi\nadd %esi,%eax\nadd %edx,%eax\nlea 0x1(%rcx),%edx\ncmp %ecx,%eax\ncmovl %ecx,%eax\nmov %eax,(%r8,%rcx,4)\nadd $0x1,%rcx\ncmp %r9,%rcx\njne 12c0 \nmovslq %edi,%rdi\nmov (%r8,%rdi,4),%eax\nmov -0x8(%rbp),%rdi\nxor %fs:0x28,%rdi\njne 1323 \nleaveq\nretq\nnopl 0x0(%rax,%rax,1)\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 127a \ncallq 1060 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmovsxd r10, edi\nlea r8d, [r10+1]\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmovsxd rax, r8d\nmov rcx, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_126A\nloc_1255:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rcx\njnz short loc_1255\nloc_126A:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1320\nloc_127C:\nlea rdi, [rsp+1010h+var_100D]\nmov rdx, cs:qword_2060\nmov rax, rdi\nand rdi, 0FFFFFFFFFFFFFFFCh\nshr rax, 2\nmov qword ptr ds:dword_0[rax*4], rdx\ncmp r10d, 1\njle short loc_1308\nmov r8d, r8d\nmov edx, 2\nxor r11d, r11d\nxor esi, esi\nmov ecx, 1\nmov r9d, 0AAAAAAABh\njmp short loc_12EF\nloc_12C0:\nmov [rdi+rdx*4], edx\nlea eax, [rdx+1]\nadd rdx, 1\ncmp r8, rdx\njz short loc_1308\nloc_12CF:\nmov esi, eax\nmov ecx, eax\nsar eax, 2\nimul rsi, r9\nsar ecx, 1\ncdqe\nmovsxd rcx, ecx\nmov r11d, [rdi+rax*4]\nmov ecx, [rdi+rcx*4]\nshr rsi, 21h\nmov esi, [rdi+rsi*4]\nloc_12EF:\nlea eax, [rcx+rsi]\nadd eax, r11d\ncmp eax, edx\njl short loc_12C0\nmov [rdi+rdx*4], eax\nlea eax, [rdx+1]\nadd rdx, 1\ncmp rdx, r8\njnz short loc_12CF\nloc_1308:\nmov eax, [rdi+r10*4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_132B\nleave\nretn\nloc_1320:\nor [rsp+rdx+1010h+var_1018], 0\njmp loc_127C\nloc_132B:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // r8d\n __int64 v2; // rdx\n _QWORD *v3; // rcx\n __int16 v4; // dx\n signed __int64 v5; // rdx\n void *v6; // rsp\n __int64 v7; // rdx\n int v8; // r11d\n int v9; // esi\n int v10; // ecx\n int v11; // eax\n int v12; // eax\n _QWORD v15[511]; // [rsp+8h] [rbp-1010h] BYREF\n _QWORD v16[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v1 = a1 + 1;\n v16[1] = __readfsqword(0x28u);\n v2 = 4LL * (a1 + 1) + 15;\n v3 = (_QWORD *)((char *)v16 - (v2 & 0xFFFFFFFFFFFFF000LL));\n v4 = v2 & 0xFFF0;\n if ( v16 != v3 )\n {\n while ( v15 != v3 )\n ;\n }\n v5 = v4 & 0xFFF;\n v6 = alloca(v5);\n if ( v5 )\n *(_QWORD *)((char *)&v15[-1] + v5) = *(_QWORD *)((char *)&v15[-1] + v5);\n v15[0] = 0x100000000LL;\n if ( a1 > 1 )\n {\n v7 = 2LL;\n v8 = 0;\n v9 = 0;\n v10 = 1;\n while ( 1 )\n {\n v12 = v8 + v10 + v9;\n if ( v12 < (int)v7 )\n {\n *((_DWORD *)v15 + v7) = v7;\n v11 = ++v7;\n if ( v1 == v7 )\n return *((unsigned int *)v15 + a1);\n }\n else\n {\n *((_DWORD *)v15 + v7) = v12;\n v11 = ++v7;\n if ( v7 == v1 )\n return *((unsigned int *)v15 + a1);\n }\n v8 = *((_DWORD *)v15 + (v11 >> 2));\n v10 = *((_DWORD *)v15 + (v11 >> 1));\n v9 = *((_DWORD *)v15 + (unsigned int)v11 / 3uLL);\n }\n }\n return *((unsigned int *)v15 + a1);\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbp\nmovsxd r10, edi\nlea r8d, [r10+1]\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmovsxd rax, r8d\nmov rcx, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_126A\nloc_1255:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rcx\njnz short loc_1255\nloc_126A:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1320\nloc_127C:\nlea rdi, [rsp+1010h+var_100D]\nmov rdx, cs:qword_2060\nmov rax, rdi\nand rdi, 0FFFFFFFFFFFFFFFCh\nshr rax, 2\nmov qword ptr ds:dword_0[rax*4], rdx\ncmp r10d, 1\njle short loc_1308\nmov r8d, r8d\nmov edx, 2\nxor r11d, r11d\nxor esi, esi\nmov ecx, 1\nmov r9d, 0AAAAAAABh\njmp short loc_12EF\nloc_12C0:\nmov [rdi+rdx*4], edx\nlea eax, [rdx+1]\nadd rdx, 1\ncmp r8, rdx\njz short loc_1308\nloc_12CF:\nmov esi, eax\nmov ecx, eax\nsar eax, 2\nimul rsi, r9\nsar ecx, 1\ncdqe\nmovsxd rcx, ecx\nmov r11d, [rdi+rax*4]\nmov ecx, [rdi+rcx*4]\nshr rsi, 21h\nmov esi, [rdi+rsi*4]\nloc_12EF:\nlea eax, [rcx+rsi]\nadd eax, r11d\ncmp eax, edx\njl short loc_12C0\nmov [rdi+rdx*4], eax\nlea eax, [rdx+1]\nadd rdx, 1\ncmp rdx, r8\njnz short loc_12CF\nloc_1308:\nmov eax, [rdi+r10*4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_132B\nleave\nretn\nloc_1320:\nor [rsp+rdx+1010h+var_1018], 0\njmp loc_127C\nloc_132B:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(int a1)\n{\n int v1; // r8d\n __int64 v2; // rdx\n _QWORD *v3; // rcx\n __int16 v4; // dx\n signed __int64 v5; // rdx\n void *v6; // rsp\n __int64 v7; // rdx\n int v8; // r11d\n int v9; // esi\n int v10; // ecx\n int v11; // eax\n int v12; // eax\n _QWORD v15[511]; // [rsp+8h] [rbp-1010h] BYREF\n _QWORD v16[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v1 = a1 + 1;\n v16[1] = __readfsqword(0x28u);\n v2 = 4LL * (a1 + 1) + 15;\n v3 = (_QWORD *)((char *)v16 - (v2 & 0xFFFFFFFFFFFFF000LL));\n v4 = v2 & 0xFFF0;\n if ( v16 != v3 )\n {\n while ( v15 != v3 )\n ;\n }\n v5 = v4 & 0xFFF;\n v6 = alloca(v5);\n if ( v5 )\n *(_QWORD *)((char *)&v15[-1] + v5) = *(_QWORD *)((char *)&v15[-1] + v5);\n v15[0] = 0x100000000LL;\n if ( a1 > 1 )\n {\n v7 = 2LL;\n v8 = 0;\n v9 = 0;\n v10 = 1;\n while ( 1 )\n {\n v12 = v8 + v10 + v9;\n if ( v12 < (int)v7 )\n {\n *((_DWORD *)v15 + v7) = v7;\n v11 = ++v7;\n if ( v1 == v7 )\n return *((unsigned int *)v15 + a1);\n }\n else\n {\n *((_DWORD *)v15 + v7) = v12;\n v11 = ++v7;\n if ( v7 == v1 )\n return *((unsigned int *)v15 + a1);\n }\n v8 = *((_DWORD *)v15 + (v11 >> 2));\n v10 = *((_DWORD *)v15 + (v11 >> 1));\n v9 = *((_DWORD *)v15 + (unsigned int)v11 / 3uLL);\n }\n }\n return *((unsigned int *)v15 + a1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(int a1) {\n int v1;\n long long v2;\n uint64_t *v3;\n short v4;\n signed long long v5;\n void *v6;\n long long v7;\n int v8;\n int v9;\n int v10;\n int v11;\n int v12;\n uint64_t v15[511];\n uint64_t v16[2];\n v1 = a1 + 1;\n v16[1] = __readfsqword(40u);\n v2 = 4LL * (a1 + 1) + 15;\n v3 = (uint64_t *)((char *)v16 - (v2 & 18446744073709547520LL));\n v4 = v2 & 65520;\n if (v16 != v3) {\n while (v15 != v3)\n ;\n }\n v5 = v4 & 4095;\n v6 = alloca(v5);\n if (v5)\n *(uint64_t *)((char *)&v15[-1] + v5) = *(uint64_t *)((char *)&v15[-1] + v5);\n v15[0] = 4294967296LL;\n if (a1 > 1) {\n v7 = 2LL;\n v8 = 0;\n v9 = 0;\n v10 = 1;\n while (1) {\n v12 = v8 + v10 + v9;\n if (v12 < (int)v7) {\n *((uint32_t *)v15 + v7) = v7;\n v11 = ++v7;\n if (v1 == v7) return *((unsigned int *)v15 + a1);\n } else {\n *((uint32_t *)v15 + v7) = v12;\n v11 = ++v7;\n if (v7 == v1) return *((unsigned int *)v15 + a1);\n }\n v8 = *((uint32_t *)v15 + (v11 >> 2));\n v10 = *((uint32_t *)v15 + (v11 >> 1));\n v9 = *((uint32_t *)v15 + (unsigned int)v11 / 3uLL);\n }\n }\n return *((unsigned int *)v15 + a1);\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n long long v2;\n uint64_t *v3;\n short v4;\n signed long long v5;\n void *v6;\n long long v7;\n int v8;\n int v9;\n int v10;\n int v11;\n int v12;\n uint64_t v15[511];\n uint64_t v16[2];\n v1 = a1 + 1;\n v16[1] = __readfsqword(40u);\n v2 = 4LL * (a1 + 1) + 15;\n v3 = (uint64_t *)((char *)v16 - (v2 & 18446744073709547520LL));\n v4 = v2 & 65520;\n if (v16 != v3) {\n while (v15 != v3)\n ;\n }\n v5 = v4 & 4095;\n v6 = alloca(v5);\n if (v5)\n *(uint64_t *)((char *)&v15[-1] + v5) = *(uint64_t *)((char *)&v15[-1] + v5);\n v15[0] = 4294967296LL;\n if (a1 > 1) {\n v7 = 2LL;\n v8 = 0;\n v9 = 0;\n v10 = 1;\n while (1) {\n v12 = v8 + v10 + v9;\n if (v12 < (int)v7) {\n *((uint32_t *)v15 + v7) = v7;\n v11 = ++v7;\n if (v1 == v7) return *((unsigned int *)v15 + a1);\n } else {\n *((uint32_t *)v15 + v7) = v12;\n v11 = ++v7;\n if (v7 == v1) return *((unsigned int *)v15 + a1);\n }\n v8 = *((uint32_t *)v15 + (v11 >> 2));\n v10 = *((uint32_t *)v15 + (v11 >> 1));\n v9 = *((uint32_t *)v15 + (unsigned int)v11 / 3uLL);\n }\n }\n return *((unsigned int *)v15 + a1);\n}" + }, + { + "index": 417, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char key;\n\n char *values;\n\n size_t size;\n\n} TupleGroup;\n\n\n\n", + "func": "TupleGroup *func0(char Input[][2], size_t n, int *returnSize) {\n TupleGroup *out = malloc(n * sizeof(TupleGroup));\n int outCount = 0;\n for (int i = 0; i < n; i++) {\n int found = 0;\n for (int j = 0; j < outCount; j++) {\n if (out[j].key == Input[i][0]) {\n size_t new_size = out[j].size + 1;\n out[j].values = realloc(out[j].values, new_size);\n out[j].values[new_size - 1] = Input[i][1];\n out[j].size = new_size;\n found = 1;\n break;\n }\n }\n if (!found) {\n out[outCount].key = Input[i][0];\n out[outCount].values = malloc(2);\n out[outCount].values[0] = Input[i][0];\n out[outCount].values[1] = Input[i][1];\n out[outCount].size = 2;\n outCount++;\n }\n }\n *returnSize = outCount;\n return out;\n}", + "test": "int main() {\n\n char input1[][2] = { {'x', 'y'}, {'x', 'z'}, {'w', 't'} };\n\n int size1;\n\n TupleGroup *result1 = func0(input1, 3, &size1);\n\n assert(size1 == 2);\n\n assert(memcmp(result1[0].values, \"xyz\", 3) == 0 && result1[0].size == 3);\n\n assert(memcmp(result1[1].values, \"wt\", 2) == 0 && result1[1].size == 2);\n\n free(result1[0].values);\n\n free(result1[1].values);\n\n free(result1);\n\n\n\n char input2[][2] = { {'a', 'b'}, {'a', 'c'}, {'d', 'e'} };\n\n int size2;\n\n TupleGroup *result2 = func0(input2, 3, &size2);\n\n assert(size2 == 2);\n\n assert(memcmp(result2[0].values, \"abc\", 3) == 0 && result2[0].size == 3);\n\n assert(memcmp(result2[1].values, \"de\", 2) == 0 && result2[1].size == 2);\n\n free(result2[0].values);\n\n free(result2[1].values);\n\n free(result2);\n\n\n\n char input3[][2] = { {'f', 'g'}, {'f', 'g'}, {'h', 'i'} };\n\n int size3;\n\n TupleGroup *result3 = func0(input3, 3, &size3);\n\n assert(size3 == 2);\n\n assert(memcmp(result3[0].values, \"fgg\", 3) == 0 && result3[0].size == 3);\n\n assert(memcmp(result3[1].values, \"hi\", 2) == 0 && result3[1].size == 2);\n\n free(result3[0].values);\n\n free(result3[1].values);\n\n free(result3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x48,%rsp\nmov %rdi,-0x38(%rbp)\nmov %rsi,-0x40(%rbp)\nmov %rdx,-0x48(%rbp)\nmov -0x40(%rbp),%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 10e0 \nmov %rax,-0x20(%rbp)\nmovl $0x0,-0x30(%rbp)\nmovl $0x0,-0x2c(%rbp)\njmpq 1485 \nmovl $0x0,-0x28(%rbp)\nmovl $0x0,-0x24(%rbp)\njmpq 1370 \nmov -0x24(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%edx\nmov -0x2c(%rbp),%eax\ncltq\nlea (%rax,%rax,1),%rcx\nmov -0x38(%rbp),%rax\nadd %rcx,%rax\nmovzbl (%rax),%eax\ncmp %al,%dl\njne 136c \nmov -0x24(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov 0x10(%rax),%rax\nadd $0x1,%rax\nmov %rax,-0x18(%rbp)\nmov -0x24(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov 0x8(%rax),%rcx\nmov -0x24(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nmov -0x20(%rbp),%rax\nlea (%rdx,%rax,1),%rbx\nmov -0x18(%rbp),%rax\nmov %rax,%rsi\nmov %rcx,%rdi\ncallq 10f0 \nmov %rax,0x8(%rbx)\nmov -0x2c(%rbp),%eax\ncltq\nlea (%rax,%rax,1),%rdx\nmov -0x38(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x24(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov 0x8(%rax),%rax\nmov -0x18(%rbp),%rdx\nsub $0x1,%rdx\nadd %rax,%rdx\nmovzbl 0x1(%rcx),%eax\nmov %al,(%rdx)\nmov -0x24(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nmov -0x20(%rbp),%rax\nadd %rax,%rdx\nmov -0x18(%rbp),%rax\nmov %rax,0x10(%rdx)\nmovl $0x1,-0x28(%rbp)\njmp 137c \naddl $0x1,-0x24(%rbp)\nmov -0x24(%rbp),%eax\ncmp -0x30(%rbp),%eax\njl 1245 \ncmpl $0x0,-0x28(%rbp)\njne 1481 \nmov -0x2c(%rbp),%eax\ncltq\nlea (%rax,%rax,1),%rdx\nmov -0x38(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x30(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nmov -0x20(%rbp),%rax\nadd %rax,%rdx\nmovzbl (%rcx),%eax\nmov %al,(%rdx)\nmov -0x30(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nmov -0x20(%rbp),%rax\nlea (%rdx,%rax,1),%rbx\nmov $0x2,%edi\ncallq 10e0 \nmov %rax,0x8(%rbx)\nmov -0x2c(%rbp),%eax\ncltq\nlea (%rax,%rax,1),%rdx\nmov -0x38(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x30(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov 0x8(%rax),%rax\nmovzbl (%rcx),%edx\nmov %dl,(%rax)\nmov -0x2c(%rbp),%eax\ncltq\nlea (%rax,%rax,1),%rdx\nmov -0x38(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x30(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov 0x8(%rax),%rax\nlea 0x1(%rax),%rdx\nmovzbl 0x1(%rcx),%eax\nmov %al,(%rdx)\nmov -0x30(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmovq $0x2,0x10(%rax)\naddl $0x1,-0x30(%rbp)\naddl $0x1,-0x2c(%rbp)\nmov -0x2c(%rbp),%eax\ncltq\ncmp %rax,-0x40(%rbp)\nja 1232 \nmov -0x48(%rbp),%rax\nmov -0x30(%rbp),%edx\nmov %edx,(%rax)\nmov -0x20(%rbp),%rax\nadd $0x48,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 48h\nmov [rbp+var_38], rdi\nmov [rbp+var_40], rsi\nmov [rbp+var_48], rdx\nmov rdx, [rbp+var_40]\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_20], rax\nmov [rbp+var_30], 0\nmov [rbp+var_2C], 0\njmp loc_1485\nloc_1232:\nmov [rbp+var_28], 0\nmov [rbp+var_24], 0\njmp loc_1370\nloc_1245:\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_20]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_2C]\ncdqe\nlea rcx, [rax+rax]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njnz loc_136C\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov rax, [rax+10h]\nadd rax, 1\nmov [rbp+size], rax\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov rcx, [rax+8]\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_20]\nlea rbx, [rdx+rax]\nmov rax, [rbp+size]\nmov rsi, rax; size\nmov rdi, rcx; ptr\ncall _realloc\nmov [rbx+8], rax\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, [rax+rax]\nmov rax, [rbp+var_38]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov rax, [rax+8]\nmov rdx, [rbp+size]\nsub rdx, 1\nadd rdx, rax\nmovzx eax, byte ptr [rcx+1]\nmov [rdx], al\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_20]\nadd rdx, rax\nmov rax, [rbp+size]\nmov [rdx+10h], rax\nmov [rbp+var_28], 1\njmp short loc_137C\nloc_136C:\nadd [rbp+var_24], 1\nloc_1370:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_30]\njl loc_1245\nloc_137C:\ncmp [rbp+var_28], 0\njnz loc_1481\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, [rax+rax]\nmov rax, [rbp+var_38]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_30]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_20]\nadd rdx, rax\nmovzx eax, byte ptr [rcx]\nmov [rdx], al\nmov eax, [rbp+var_30]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_20]\nlea rbx, [rdx+rax]\nmov edi, 2; size\ncall _malloc\nmov [rbx+8], rax\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, [rax+rax]\nmov rax, [rbp+var_38]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_30]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov rax, [rax+8]\nmovzx edx, byte ptr [rcx]\nmov [rax], dl\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, [rax+rax]\nmov rax, [rbp+var_38]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_30]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov rax, [rax+8]\nlea rdx, [rax+1]\nmovzx eax, byte ptr [rcx+1]\nmov [rdx], al\nmov eax, [rbp+var_30]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov qword ptr [rax+10h], 2\nadd [rbp+var_30], 1\nloc_1481:\nadd [rbp+var_2C], 1\nloc_1485:\nmov eax, [rbp+var_2C]\ncdqe\ncmp rax, [rbp+var_40]\njb loc_1232\nmov rax, [rbp+var_48]\nmov edx, [rbp+var_30]\nmov [rax], edx\nmov rax, [rbp+var_20]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, unsigned __int64 a2, _DWORD *a3)\n{\n int v5; // [rsp+20h] [rbp-30h]\n int i; // [rsp+24h] [rbp-2Ch]\n int v7; // [rsp+28h] [rbp-28h]\n int j; // [rsp+2Ch] [rbp-24h]\n _QWORD *v9; // [rsp+30h] [rbp-20h]\n __int64 size; // [rsp+38h] [rbp-18h]\n\n v9 = malloc(24 * a2);\n v5 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v7 = 0;\n for ( j = 0; j < v5; ++j )\n {\n if ( LOBYTE(v9[3 * j]) == *(_BYTE *)(2LL * i + a1) )\n {\n size = v9[3 * j + 2] + 1LL;\n v9[3 * j + 1] = realloc((void *)v9[3 * j + 1], size);\n *(_BYTE *)(v9[3 * j + 1] + size - 1) = *(_BYTE *)(2LL * i + a1 + 1);\n v9[3 * j + 2] = size;\n v7 = 1;\n break;\n }\n }\n if ( !v7 )\n {\n LOBYTE(v9[3 * v5]) = *(_BYTE *)(2LL * i + a1);\n v9[3 * v5 + 1] = malloc(2uLL);\n *(_BYTE *)v9[3 * v5 + 1] = *(_BYTE *)(2LL * i + a1);\n *(_BYTE *)(v9[3 * v5 + 1] + 1LL) = *(_BYTE *)(2LL * i + a1 + 1);\n v9[3 * v5++ + 2] = 2LL;\n }\n }\n *a3 = v5;\n return v9;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 48h\nmov [rbp+var_38], rdi\nmov [rbp+var_40], rsi\nmov [rbp+var_48], rdx\nmov rdx, [rbp+var_40]\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_20], rax\nmov [rbp+var_30], 0\nmov [rbp+var_2C], 0\njmp loc_1485\nloc_1232:\nmov [rbp+var_28], 0\nmov [rbp+var_24], 0\njmp loc_1370\nloc_1245:\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_20]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_2C]\ncdqe\nlea rcx, [rax+rax]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njnz loc_136C\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov rax, [rax+10h]\nadd rax, 1\nmov [rbp+size], rax\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov rcx, [rax+8]\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_20]\nlea rbx, [rdx+rax]\nmov rax, [rbp+size]\nmov rsi, rax; size\nmov rdi, rcx; ptr\ncall _realloc\nmov [rbx+8], rax\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, [rax+rax]\nmov rax, [rbp+var_38]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov rax, [rax+8]\nmov rdx, [rbp+size]\nsub rdx, 1\nadd rdx, rax\nmovzx eax, byte ptr [rcx+1]\nmov [rdx], al\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_20]\nadd rdx, rax\nmov rax, [rbp+size]\nmov [rdx+10h], rax\nmov [rbp+var_28], 1\njmp short loc_137C\nloc_136C:\nadd [rbp+var_24], 1\nloc_1370:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_30]\njl loc_1245\nloc_137C:\ncmp [rbp+var_28], 0\njnz loc_1481\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, [rax+rax]\nmov rax, [rbp+var_38]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_30]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_20]\nadd rdx, rax\nmovzx eax, byte ptr [rcx]\nmov [rdx], al\nmov eax, [rbp+var_30]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_20]\nlea rbx, [rdx+rax]\nmov edi, 2; size\ncall _malloc\nmov [rbx+8], rax\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, [rax+rax]\nmov rax, [rbp+var_38]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_30]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov rax, [rax+8]\nmovzx edx, byte ptr [rcx]\nmov [rax], dl\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, [rax+rax]\nmov rax, [rbp+var_38]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_30]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov rax, [rax+8]\nlea rdx, [rax+1]\nmovzx eax, byte ptr [rcx+1]\nmov [rdx], al\nmov eax, [rbp+var_30]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov qword ptr [rax+10h], 2\nadd [rbp+var_30], 1\nloc_1481:\nadd [rbp+var_2C], 1\nloc_1485:\nmov eax, [rbp+var_2C]\ncdqe\ncmp rax, [rbp+var_40]\njb loc_1232\nmov rax, [rbp+var_48]\nmov edx, [rbp+var_30]\nmov [rax], edx\nmov rax, [rbp+var_20]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11E9(__int64 a1, unsigned __int64 a2, _DWORD *a3)\n{\n int v5; // [rsp+20h] [rbp-30h]\n int i; // [rsp+24h] [rbp-2Ch]\n int v7; // [rsp+28h] [rbp-28h]\n int j; // [rsp+2Ch] [rbp-24h]\n _QWORD *v9; // [rsp+30h] [rbp-20h]\n __int64 size; // [rsp+38h] [rbp-18h]\n\n v9 = malloc(24 * a2);\n v5 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v7 = 0;\n for ( j = 0; j < v5; ++j )\n {\n if ( LOBYTE(v9[3 * j]) == *(_BYTE *)(2LL * i + a1) )\n {\n size = v9[3 * j + 2] + 1LL;\n v9[3 * j + 1] = realloc((void *)v9[3 * j + 1], size);\n *(_BYTE *)(v9[3 * j + 1] + size - 1) = *(_BYTE *)(2LL * i + a1 + 1);\n v9[3 * j + 2] = size;\n v7 = 1;\n break;\n }\n }\n if ( !v7 )\n {\n LOBYTE(v9[3 * v5]) = *(_BYTE *)(2LL * i + a1);\n v9[3 * v5 + 1] = malloc(2uLL);\n *(_BYTE *)v9[3 * v5 + 1] = *(_BYTE *)(2LL * i + a1);\n *(_BYTE *)(v9[3 * v5 + 1] + 1LL) = *(_BYTE *)(2LL * i + a1 + 1);\n v9[3 * v5++ + 2] = 2LL;\n }\n }\n *a3 = v5;\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11E9(long long a1, unsigned long long a2, uint32_t *a3) {\n int v5;\n int i;\n int v7;\n int j;\n uint64_t *v9;\n long long size;\n v9 = malloc(24 * a2);\n v5 = 0;\n for (i = 0; i < a2; ++i) {\n v7 = 0;\n for (j = 0; j < v5; ++j) {\n if (LOBYTE(v9[3 * j]) == *(uint8_t *)(2LL * i + a1)) {\n size = v9[3 * j + 2] + 1LL;\n v9[3 * j + 1] = realloc((void *)v9[3 * j + 1], size);\n *(uint8_t *)(v9[3 * j + 1] + size - 1) = *(uint8_t *)(2LL * i + a1 + 1);\n v9[3 * j + 2] = size;\n v7 = 1;\n break;\n }\n }\n if (!v7) {\n LOBYTE(v9[3 * v5]) = *(uint8_t *)(2LL * i + a1);\n v9[3 * v5 + 1] = malloc(2uLL);\n *(uint8_t *)v9[3 * v5 + 1] = *(uint8_t *)(2LL * i + a1);\n *(uint8_t *)(v9[3 * v5 + 1] + 1LL) = *(uint8_t *)(2LL * i + a1 + 1);\n v9[3 * v5++ + 2] = 2LL;\n }\n }\n *a3 = v5;\n return v9;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, unsigned long long a2, uint32_t *a3) {\n int v5;\n int i;\n int v7;\n int j;\n uint64_t *v9;\n long long size;\n v9 = malloc(24 * a2);\n v5 = 0;\n for (i = 0; i < a2; ++i) {\n v7 = 0;\n for (j = 0; j < v5; ++j) {\n if (LOBYTE(v9[3 * j]) == *(uint8_t *)(2LL * i + a1)) {\n size = v9[3 * j + 2] + 1LL;\n v9[3 * j + 1] = realloc((void *)v9[3 * j + 1], size);\n *(uint8_t *)(v9[3 * j + 1] + size - 1) = *(uint8_t *)(2LL * i + a1 + 1);\n v9[3 * j + 2] = size;\n v7 = 1;\n break;\n }\n }\n if (!v7) {\n LOBYTE(v9[3 * v5]) = *(uint8_t *)(2LL * i + a1);\n v9[3 * v5 + 1] = malloc(2uLL);\n *(uint8_t *)v9[3 * v5 + 1] = *(uint8_t *)(2LL * i + a1);\n *(uint8_t *)(v9[3 * v5 + 1] + 1LL) = *(uint8_t *)(2LL * i + a1 + 1);\n v9[3 * v5++ + 2] = 2LL;\n }\n }\n *a3 = v5;\n return v9;\n}" + }, + { + "index": 417, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char key;\n\n char *values;\n\n size_t size;\n\n} TupleGroup;\n\n\n\n", + "func": "TupleGroup *func0(char Input[][2], size_t n, int *returnSize) {\n TupleGroup *out = malloc(n * sizeof(TupleGroup));\n int outCount = 0;\n for (int i = 0; i < n; i++) {\n int found = 0;\n for (int j = 0; j < outCount; j++) {\n if (out[j].key == Input[i][0]) {\n size_t new_size = out[j].size + 1;\n out[j].values = realloc(out[j].values, new_size);\n out[j].values[new_size - 1] = Input[i][1];\n out[j].size = new_size;\n found = 1;\n break;\n }\n }\n if (!found) {\n out[outCount].key = Input[i][0];\n out[outCount].values = malloc(2);\n out[outCount].values[0] = Input[i][0];\n out[outCount].values[1] = Input[i][1];\n out[outCount].size = 2;\n outCount++;\n }\n }\n *returnSize = outCount;\n return out;\n}", + "test": "int main() {\n\n char input1[][2] = { {'x', 'y'}, {'x', 'z'}, {'w', 't'} };\n\n int size1;\n\n TupleGroup *result1 = func0(input1, 3, &size1);\n\n assert(size1 == 2);\n\n assert(memcmp(result1[0].values, \"xyz\", 3) == 0 && result1[0].size == 3);\n\n assert(memcmp(result1[1].values, \"wt\", 2) == 0 && result1[1].size == 2);\n\n free(result1[0].values);\n\n free(result1[1].values);\n\n free(result1);\n\n\n\n char input2[][2] = { {'a', 'b'}, {'a', 'c'}, {'d', 'e'} };\n\n int size2;\n\n TupleGroup *result2 = func0(input2, 3, &size2);\n\n assert(size2 == 2);\n\n assert(memcmp(result2[0].values, \"abc\", 3) == 0 && result2[0].size == 3);\n\n assert(memcmp(result2[1].values, \"de\", 2) == 0 && result2[1].size == 2);\n\n free(result2[0].values);\n\n free(result2[1].values);\n\n free(result2);\n\n\n\n char input3[][2] = { {'f', 'g'}, {'f', 'g'}, {'h', 'i'} };\n\n int size3;\n\n TupleGroup *result3 = func0(input3, 3, &size3);\n\n assert(size3 == 2);\n\n assert(memcmp(result3[0].values, \"fgg\", 3) == 0 && result3[0].size == 3);\n\n assert(memcmp(result3[1].values, \"hi\", 2) == 0 && result3[1].size == 2);\n\n free(result3[0].values);\n\n free(result3[1].values);\n\n free(result3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x28,%rsp\nmov %rdi,%r12\nmov %rsi,%rbx\nmov %rdx,0x18(%rsp)\nlea (%rsi,%rsi,2),%rdi\nshl $0x3,%rdi\ncallq 10e0 \nmov %rax,%r13\ntest %rbx,%rbx\nje 12e1 \nmov %r12,%rbp\nlea (%r12,%rbx,2),%rax\nmov %rax,0x8(%rsp)\nmov $0x0,%r12d\nlea 0x18(%r13),%rax\nmov %rax,0x10(%rsp)\njmp 12a9 \nmov 0x10(%rax),%r15\nlea 0x1(%r15),%r14\nmov 0x8(%rax),%rdi\nmov %r14,%rsi\ncallq 10f0 \nmov %rax,0x8(%rbx)\nmov (%rsp),%rsi\nmovzbl 0x1(%rsi),%edx\nmov %dl,(%rax,%r15,1)\nmov %r14,0x10(%rbx)\njmp 129e \nmovslq %r12d,%rax\nlea (%rax,%rax,2),%rax\nlea 0x0(%r13,%rax,8),%rbx\nmovzbl 0x0(%rbp),%r14d\nmov %r14b,(%rbx)\nmov $0x2,%edi\ncallq 10e0 \nmov %rax,0x8(%rbx)\nmov %r14b,(%rax)\nmovzbl 0x1(%rbp),%edx\nmov %dl,0x1(%rax)\nmovq $0x2,0x10(%rbx)\nadd $0x1,%r12d\nadd $0x2,%rbp\ncmp 0x8(%rsp),%rbp\nje 12e7 \ntest %r12d,%r12d\njle 1266 \nmov %rbp,(%rsp)\nmovzbl 0x0(%rbp),%edx\nmov %r13,%rax\nlea -0x1(%r12),%ecx\nlea (%rcx,%rcx,2),%rcx\nmov 0x10(%rsp),%rsi\nlea (%rsi,%rcx,8),%rcx\nmov %rax,%rbx\ncmp %dl,(%rax)\nje 123c \nadd $0x18,%rax\ncmp %rcx,%rax\njne 12cb \njmp 1266 \nmov $0x0,%r12d\nmov 0x18(%rsp),%rax\nmov %r12d,(%rax)\nmov %r13,%rax\nadd $0x28,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov r12, rdi\nmov rbx, rsi\nmov [rsp+58h+var_40], rdx\nlea rdi, [rsi+rsi*2]\nshl rdi, 3; size\ncall _malloc\nmov r13, rax\ntest rbx, rbx\njz loc_12D4\nmov rbp, r12\nlea rax, [r12+rbx*2]\nmov [rsp+58h+var_48], rax\nmov r12d, 0\njmp short loc_12A4\nloc_1233:\nmov r15, [rbx+10h]\nlea r14, [r15+1]\nmov rdi, [rbx+8]; ptr\nmov rsi, r14; size\ncall _realloc\nmov [rbx+8], rax\nmov rcx, [rsp+58h+var_50]\nmovzx edx, byte ptr [rcx+1]\nmov [rax+r15], dl\nmov [rbx+10h], r14\njmp short loc_1296\nloc_125E:\nmovsxd rax, r12d\nlea rax, [rax+rax*2]\nlea rbx, [r13+rax*8+0]\nmovzx r14d, byte ptr [rbp+0]\nmov [rbx], r14b\nmov edi, 2; size\ncall _malloc\nmov [rbx+8], rax\nmov [rax], r14b\nmovzx edx, byte ptr [rbp+1]\nmov [rax+1], dl\nmov qword ptr [rbx+10h], 2\nadd r12d, 1\nloc_1296:\nadd rbp, 2\nmov rax, [rsp+58h+var_48]\ncmp rbp, rax\njz short loc_12DA\nloc_12A4:\ntest r12d, r12d\njle short loc_125E\nmov [rsp+58h+var_50], rbp\nmovzx eax, byte ptr [rbp+0]\nmov rbx, r13\nmovsxd rdx, r12d\nlea rdx, [rdx+rdx*2]\nlea rdx, [r13+rdx*8+0]\nloc_12C1:\ncmp [rbx], al\njz loc_1233\nadd rbx, 18h\ncmp rbx, rdx\njnz short loc_12C1\njmp short loc_125E\nloc_12D4:\nmov r12d, 0\nloc_12DA:\nmov rax, [rsp+58h+var_40]\nmov [rax], r12d\nmov rax, r13\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "char *__fastcall func0(char *a1, __int64 a2, int *a3)\n{\n char *v3; // r13\n char *v4; // rbp\n int v5; // r12d\n __int64 v6; // r15\n _BYTE *v7; // rax\n char *v8; // rbx\n char v9; // r14\n _BYTE *v10; // rax\n char *v11; // rbx\n\n v3 = (char *)malloc(24 * a2);\n if ( a2 )\n {\n v4 = a1;\n v5 = 0;\n do\n {\n if ( v5 <= 0 )\n {\nLABEL_4:\n v8 = &v3[24 * v5];\n v9 = *v4;\n *v8 = *v4;\n v10 = malloc(2uLL);\n *((_QWORD *)v8 + 1) = v10;\n *v10 = v9;\n v10[1] = v4[1];\n *((_QWORD *)v8 + 2) = 2LL;\n ++v5;\n }\n else\n {\n v11 = v3;\n while ( *v11 != *v4 )\n {\n v11 += 24;\n if ( v11 == &v3[24 * v5] )\n goto LABEL_4;\n }\n v6 = *((_QWORD *)v11 + 2);\n v7 = realloc(*((void **)v11 + 1), v6 + 1);\n *((_QWORD *)v11 + 1) = v7;\n v7[v6] = v4[1];\n *((_QWORD *)v11 + 2) = v6 + 1;\n }\n v4 += 2;\n }\n while ( v4 != &a1[2 * a2] );\n }\n else\n {\n v5 = 0;\n }\n *a3 = v5;\n return v3;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov r12, rdi\nmov rbx, rsi\nmov [rsp+58h+var_40], rdx\nlea rdi, [rsi+rsi*2]\nshl rdi, 3; size\ncall _malloc\nmov r13, rax\ntest rbx, rbx\njz loc_12D4\nmov rbp, r12\nlea rax, [r12+rbx*2]\nmov [rsp+58h+var_48], rax\nmov r12d, 0\njmp short loc_12A4\nloc_1233:\nmov r15, [rbx+10h]\nlea r14, [r15+1]\nmov rdi, [rbx+8]; ptr\nmov rsi, r14; size\ncall _realloc\nmov [rbx+8], rax\nmov rcx, [rsp+58h+var_50]\nmovzx edx, byte ptr [rcx+1]\nmov [rax+r15], dl\nmov [rbx+10h], r14\njmp short loc_1296\nloc_125E:\nmovsxd rax, r12d\nlea rax, [rax+rax*2]\nlea rbx, [r13+rax*8+0]\nmovzx r14d, byte ptr [rbp+0]\nmov [rbx], r14b\nmov edi, 2; size\ncall _malloc\nmov [rbx+8], rax\nmov [rax], r14b\nmovzx edx, byte ptr [rbp+1]\nmov [rax+1], dl\nmov qword ptr [rbx+10h], 2\nadd r12d, 1\nloc_1296:\nadd rbp, 2\nmov rax, [rsp+58h+var_48]\ncmp rbp, rax\njz short loc_12DA\nloc_12A4:\ntest r12d, r12d\njle short loc_125E\nmov [rsp+58h+var_50], rbp\nmovzx eax, byte ptr [rbp+0]\nmov rbx, r13\nmovsxd rdx, r12d\nlea rdx, [rdx+rdx*2]\nlea rdx, [r13+rdx*8+0]\nloc_12C1:\ncmp [rbx], al\njz loc_1233\nadd rbx, 18h\ncmp rbx, rdx\njnz short loc_12C1\njmp short loc_125E\nloc_12D4:\nmov r12d, 0\nloc_12DA:\nmov rax, [rsp+58h+var_40]\nmov [rax], r12d\nmov rax, r13\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11E9(char *a1, __int64 a2, int *a3)\n{\n char *v3; // r13\n char *v4; // rbp\n int v5; // r12d\n __int64 v6; // r15\n _BYTE *v7; // rax\n char *v8; // rbx\n char v9; // r14\n _BYTE *v10; // rax\n char *v11; // rbx\n\n v3 = (char *)malloc(24 * a2);\n if ( a2 )\n {\n v4 = a1;\n v5 = 0;\n do\n {\n if ( v5 <= 0 )\n {\nLABEL_4:\n v8 = &v3[24 * v5];\n v9 = *v4;\n *v8 = *v4;\n v10 = malloc(2uLL);\n *((_QWORD *)v8 + 1) = v10;\n *v10 = v9;\n v10[1] = v4[1];\n *((_QWORD *)v8 + 2) = 2LL;\n ++v5;\n }\n else\n {\n v11 = v3;\n while ( *v11 != *v4 )\n {\n v11 += 24;\n if ( v11 == &v3[24 * v5] )\n goto LABEL_4;\n }\n v6 = *((_QWORD *)v11 + 2);\n v7 = realloc(*((void **)v11 + 1), v6 + 1);\n *((_QWORD *)v11 + 1) = v7;\n v7[v6] = v4[1];\n *((_QWORD *)v11 + 2) = v6 + 1;\n }\n v4 += 2;\n }\n while ( v4 != &a1[2 * a2] );\n }\n else\n {\n v5 = 0;\n }\n *a3 = v5;\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11E9(char *a1, long long a2, int *a3) {\n char *v3;\n char *v4;\n int v5;\n long long v6;\n uint8_t *v7;\n char *v8;\n char v9;\n uint8_t *v10;\n char *v11;\n v3 = (char *)malloc(24 * a2);\n if (a2) {\n v4 = a1;\n v5 = 0;\n do {\n if (v5 <= 0) {\n LABEL_4:\n v8 = &v3[24 * v5];\n v9 = *v4;\n *v8 = *v4;\n v10 = malloc(2uLL);\n *((uint64_t *)v8 + 1) = v10;\n *v10 = v9;\n v10[1] = v4[1];\n *((uint64_t *)v8 + 2) = 2LL;\n ++v5;\n } else {\n v11 = v3;\n while (*v11 != *v4) {\n v11 += 24;\n if (v11 == &v3[24 * v5]) goto LABEL_4;\n }\n v6 = *((uint64_t *)v11 + 2);\n v7 = realloc(*((void **)v11 + 1), v6 + 1);\n *((uint64_t *)v11 + 1) = v7;\n v7[v6] = v4[1];\n *((uint64_t *)v11 + 2) = v6 + 1;\n }\n v4 += 2;\n } while (v4 != &a1[2 * a2]);\n } else {\n v5 = 0;\n }\n *a3 = v5;\n return v3;\n}", + "ida_pseudo_norm": "char *func0(char *a1, long long a2, int *a3) {\n char *v3;\n char *v4;\n int v5;\n long long v6;\n uint8_t *v7;\n char *v8;\n char v9;\n uint8_t *v10;\n char *v11;\n v3 = (char *)malloc(24 * a2);\n if (a2) {\n v4 = a1;\n v5 = 0;\n do {\n if (v5 <= 0) {\n LABEL_4:\n v8 = &v3[24 * v5];\n v9 = *v4;\n *v8 = *v4;\n v10 = malloc(2uLL);\n *((uint64_t *)v8 + 1) = v10;\n *v10 = v9;\n v10[1] = v4[1];\n *((uint64_t *)v8 + 2) = 2LL;\n ++v5;\n } else {\n v11 = v3;\n while (*v11 != *v4) {\n v11 += 24;\n if (v11 == &v3[24 * v5]) goto LABEL_4;\n }\n v6 = *((uint64_t *)v11 + 2);\n v7 = realloc(*((void **)v11 + 1), v6 + 1);\n *((uint64_t *)v11 + 1) = v7;\n v7[v6] = v4[1];\n *((uint64_t *)v11 + 2) = v6 + 1;\n }\n v4 += 2;\n } while (v4 != &a1[2 * a2]);\n } else {\n v5 = 0;\n }\n *a3 = v5;\n return v3;\n}" + }, + { + "index": 417, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char key;\n\n char *values;\n\n size_t size;\n\n} TupleGroup;\n\n\n\n", + "func": "TupleGroup *func0(char Input[][2], size_t n, int *returnSize) {\n TupleGroup *out = malloc(n * sizeof(TupleGroup));\n int outCount = 0;\n for (int i = 0; i < n; i++) {\n int found = 0;\n for (int j = 0; j < outCount; j++) {\n if (out[j].key == Input[i][0]) {\n size_t new_size = out[j].size + 1;\n out[j].values = realloc(out[j].values, new_size);\n out[j].values[new_size - 1] = Input[i][1];\n out[j].size = new_size;\n found = 1;\n break;\n }\n }\n if (!found) {\n out[outCount].key = Input[i][0];\n out[outCount].values = malloc(2);\n out[outCount].values[0] = Input[i][0];\n out[outCount].values[1] = Input[i][1];\n out[outCount].size = 2;\n outCount++;\n }\n }\n *returnSize = outCount;\n return out;\n}", + "test": "int main() {\n\n char input1[][2] = { {'x', 'y'}, {'x', 'z'}, {'w', 't'} };\n\n int size1;\n\n TupleGroup *result1 = func0(input1, 3, &size1);\n\n assert(size1 == 2);\n\n assert(memcmp(result1[0].values, \"xyz\", 3) == 0 && result1[0].size == 3);\n\n assert(memcmp(result1[1].values, \"wt\", 2) == 0 && result1[1].size == 2);\n\n free(result1[0].values);\n\n free(result1[1].values);\n\n free(result1);\n\n\n\n char input2[][2] = { {'a', 'b'}, {'a', 'c'}, {'d', 'e'} };\n\n int size2;\n\n TupleGroup *result2 = func0(input2, 3, &size2);\n\n assert(size2 == 2);\n\n assert(memcmp(result2[0].values, \"abc\", 3) == 0 && result2[0].size == 3);\n\n assert(memcmp(result2[1].values, \"de\", 2) == 0 && result2[1].size == 2);\n\n free(result2[0].values);\n\n free(result2[1].values);\n\n free(result2);\n\n\n\n char input3[][2] = { {'f', 'g'}, {'f', 'g'}, {'h', 'i'} };\n\n int size3;\n\n TupleGroup *result3 = func0(input3, 3, &size3);\n\n assert(size3 == 2);\n\n assert(memcmp(result3[0].values, \"fgg\", 3) == 0 && result3[0].size == 3);\n\n assert(memcmp(result3[1].values, \"hi\", 2) == 0 && result3[1].size == 2);\n\n free(result3[0].values);\n\n free(result3[1].values);\n\n free(result3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\nmov %rdi,%r14\npush %r13\nlea (%rsi,%rsi,1),%r13\npush %r12\nlea 0x0(%r13,%rsi,1),%rdi\npush %rbp\nshl $0x3,%rdi\npush %rbx\nmov %rsi,%rbx\nsub $0x28,%rsp\nmov %rdx,0x18(%rsp)\ncallq 10c0 \nmov %rax,%r12\ntest %rbx,%rbx\nje 15a6 \nlea (%r14,%r13,1),%rax\nxor %r15d,%r15d\nmov %rax,0x8(%rsp)\nlea 0x18(%r12),%rax\nmov %rax,0x10(%rsp)\nnopl 0x0(%rax)\nmovzbl (%r14),%ebp\ntest %r15d,%r15d\nje 1570 \nmov 0x10(%rsp),%rcx\nlea -0x1(%r15),%eax\nmov %r12,%rbx\nlea (%rax,%rax,2),%rax\nlea (%rcx,%rax,8),%rax\njmp 1519 \nnopw 0x0(%rax,%rax,1)\nadd $0x18,%rbx\ncmp %rax,%rbx\nje 1570 \ncmp %bpl,(%rbx)\njne 1510 \nmov 0x10(%rbx),%r13\nmov 0x8(%rbx),%rdi\nlea 0x1(%r13),%rbp\nmov %rbp,%rsi\ncallq 10d0 \nmovzbl 0x1(%r14),%esi\nmov %rax,0x8(%rbx)\nmov %sil,(%rax,%r13,1)\nmov %rbp,0x10(%rbx)\nadd $0x2,%r14\ncmp 0x8(%rsp),%r14\njne 14e8 \nmov 0x18(%rsp),%rax\nmov %r15d,(%rax)\nadd $0x28,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax,%rax,1)\nmovslq %r15d,%rax\nmov $0x2,%edi\nadd $0x1,%r15d\nlea (%rax,%rax,2),%rax\nlea (%r12,%rax,8),%rbx\nmov %bpl,(%rbx)\ncallq 10c0 \nmovzbl 0x1(%r14),%esi\nmovq $0x2,0x10(%rbx)\nmov %rax,0x8(%rbx)\nmov %bpl,(%rax)\nmov %sil,0x1(%rax)\njmp 1543 \nxor %r15d,%r15d\njmp 154e \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14, rdi\npush r13\npush r12\npush rbp\nlea rbp, [rsi+rsi]\npush rbx\nlea rdi, [rbp+rsi+0]\nmov rbx, rsi\nshl rdi, 3; size\nsub rsp, 28h\nmov [rsp+58h+var_40], rdx\ncall _malloc\nmov r13, rax\ntest rbx, rbx\njz loc_15BF\nlea rax, [r14+rbp]\nxor r15d, r15d\nmov [rsp+58h+var_58], rax\nnop word ptr [rax+rax+00000000h]\nloc_14E0:\nmovzx ebp, byte ptr [r14]\nmovsxd rcx, r15d\ntest r15d, r15d\njle short loc_1560\nlea rax, [rcx+rcx*2]\nlea r12, [r13+rax*8+0]\nloc_14F5:\nmov rbx, r13\njmp short loc_1509\nloc_1500:\nadd rbx, 18h\ncmp r12, rbx\njz short loc_1560\nloc_1509:\ncmp [rbx], bpl\njnz short loc_1500\nmov r9, [rbx+10h]\nmov rdi, [rbx+8]; ptr\nmov [rsp+58h+var_48], rcx\nadd r14, 2\nlea rbp, [r9+1]\nmov [rsp+58h+var_50], r9\nmov rsi, rbp; size\ncall _realloc\nmovzx esi, byte ptr [r14-1]\nmov r9, [rsp+58h+var_50]\nmov [rbx+8], rax\nmov [rax+r9], sil\nmov rax, [rsp+58h+var_58]\nmov [rbx+10h], rbp\ncmp r14, rax\njz short loc_15A5\nmovzx ebp, byte ptr [r14]\nmov rcx, [rsp+58h+var_48]\njmp short loc_14F5\nloc_1560:\nlea rax, [rcx+rcx*2]\nmov edi, 2; size\nadd r14, 2\nadd r15d, 1\nlea rbx, [r13+rax*8+0]\nmov [rbx], bpl\ncall _malloc\nmovzx edx, byte ptr [r14-1]\nmovzx ecx, bpl\nmov qword ptr [rbx+10h], 2\nmov [rbx+8], rax\nmov ch, dl\nmov [rax], cx\nmov rax, [rsp+58h+var_58]\ncmp r14, rax\njnz loc_14E0\nloc_15A5:\nmov rax, [rsp+58h+var_40]\nmov [rax], r15d\nadd rsp, 28h\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15BF:\nxor r15d, r15d\njmp short loc_15A5", + "ida_pseudo": "char *__fastcall func0(char *a1, __int64 a2, int *a3)\n{\n char *v3; // r14\n char *v4; // r13\n int v5; // r15d\n char v6; // bp\n __int64 v7; // rcx\n char *v8; // rbx\n size_t v9; // rbp\n _BYTE *v10; // rax\n char v11; // si\n char *v12; // rbx\n _WORD *v13; // rax\n char v14; // dl\n __int16 v15; // cx\n char *v17; // [rsp+0h] [rbp-58h]\n __int64 v18; // [rsp+8h] [rbp-50h]\n __int64 v19; // [rsp+10h] [rbp-48h]\n\n v3 = a1;\n v4 = (char *)malloc(24 * a2);\n if ( a2 )\n {\n v5 = 0;\n v17 = &a1[2 * a2];\n while ( 1 )\n {\n v6 = *v3;\n v7 = v5;\n if ( v5 > 0 )\n break;\nLABEL_9:\n v3 += 2;\n ++v5;\n v12 = &v4[24 * v7];\n *v12 = v6;\n v13 = malloc(2uLL);\n v14 = *(v3 - 1);\n LOBYTE(v15) = v6;\n *((_QWORD *)v12 + 2) = 2LL;\n *((_QWORD *)v12 + 1) = v13;\n HIBYTE(v15) = v14;\n *v13 = v15;\n if ( v3 == v17 )\n goto LABEL_10;\n }\n while ( 1 )\n {\n v8 = v4;\n while ( *v8 != v6 )\n {\n v8 += 24;\n if ( &v4[24 * v5] == v8 )\n goto LABEL_9;\n }\n v19 = v7;\n v3 += 2;\n v9 = *((_QWORD *)v8 + 2) + 1LL;\n v18 = *((_QWORD *)v8 + 2);\n v10 = realloc(*((void **)v8 + 1), v9);\n v11 = *(v3 - 1);\n *((_QWORD *)v8 + 1) = v10;\n v10[v18] = v11;\n *((_QWORD *)v8 + 2) = v9;\n if ( v3 == v17 )\n break;\n v6 = *v3;\n v7 = v19;\n }\n }\n else\n {\n v5 = 0;\n }\nLABEL_10:\n *a3 = v5;\n return v4;\n}", + "ida_strip_asm": "sub_1490:\nendbr64\npush r15\npush r14\nmov r14, rdi\npush r13\npush r12\npush rbp\nlea rbp, [rsi+rsi]\npush rbx\nlea rdi, [rbp+rsi+0]\nmov rbx, rsi\nshl rdi, 3; size\nsub rsp, 28h\nmov [rsp+58h+var_40], rdx\ncall _malloc\nmov r13, rax\ntest rbx, rbx\njz loc_15BF\nlea rax, [r14+rbp]\nxor r15d, r15d\nmov [rsp+58h+var_58], rax\nnop word ptr [rax+rax+00000000h]\nloc_14E0:\nmovzx ebp, byte ptr [r14]\nmovsxd rcx, r15d\ntest r15d, r15d\njle short loc_1560\nlea rax, [rcx+rcx*2]\nlea r12, [r13+rax*8+0]\nloc_14F5:\nmov rbx, r13\njmp short loc_1509\nloc_1500:\nadd rbx, 18h\ncmp r12, rbx\njz short loc_1560\nloc_1509:\ncmp [rbx], bpl\njnz short loc_1500\nmov r9, [rbx+10h]\nmov rdi, [rbx+8]; ptr\nmov [rsp+58h+var_48], rcx\nadd r14, 2\nlea rbp, [r9+1]\nmov [rsp+58h+var_50], r9\nmov rsi, rbp; size\ncall _realloc\nmovzx esi, byte ptr [r14-1]\nmov r9, [rsp+58h+var_50]\nmov [rbx+8], rax\nmov [rax+r9], sil\nmov rax, [rsp+58h+var_58]\nmov [rbx+10h], rbp\ncmp r14, rax\njz short loc_15A5\nmovzx ebp, byte ptr [r14]\nmov rcx, [rsp+58h+var_48]\njmp short loc_14F5\nloc_1560:\nlea rax, [rcx+rcx*2]\nmov edi, 2; size\nadd r14, 2\nadd r15d, 1\nlea rbx, [r13+rax*8+0]\nmov [rbx], bpl\ncall _malloc\nmovzx edx, byte ptr [r14-1]\nmovzx ecx, bpl\nmov qword ptr [rbx+10h], 2\nmov [rbx+8], rax\nmov ch, dl\nmov [rax], cx\nmov rax, [rsp+58h+var_58]\ncmp r14, rax\njnz loc_14E0\nloc_15A5:\nmov rax, [rsp+58h+var_40]\nmov [rax], r15d\nadd rsp, 28h\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15BF:\nxor r15d, r15d\njmp short loc_15A5", + "ida_strip_pseudo": "char *__fastcall sub_1490(char *a1, __int64 a2, int *a3)\n{\n char *v3; // r14\n char *v4; // r13\n int v5; // r15d\n char v6; // bp\n __int64 v7; // rcx\n char *v8; // rbx\n size_t v9; // rbp\n _BYTE *v10; // rax\n char v11; // si\n char *v12; // rbx\n _WORD *v13; // rax\n char v14; // dl\n __int16 v15; // cx\n char *v17; // [rsp+0h] [rbp-58h]\n __int64 v18; // [rsp+8h] [rbp-50h]\n __int64 v19; // [rsp+10h] [rbp-48h]\n\n v3 = a1;\n v4 = (char *)malloc(24 * a2);\n if ( a2 )\n {\n v5 = 0;\n v17 = &a1[2 * a2];\n while ( 1 )\n {\n v6 = *v3;\n v7 = v5;\n if ( v5 > 0 )\n break;\nLABEL_9:\n v3 += 2;\n ++v5;\n v12 = &v4[24 * v7];\n *v12 = v6;\n v13 = malloc(2uLL);\n v14 = *(v3 - 1);\n LOBYTE(v15) = v6;\n *((_QWORD *)v12 + 2) = 2LL;\n *((_QWORD *)v12 + 1) = v13;\n HIBYTE(v15) = v14;\n *v13 = v15;\n if ( v3 == v17 )\n goto LABEL_10;\n }\n while ( 1 )\n {\n v8 = v4;\n while ( *v8 != v6 )\n {\n v8 += 24;\n if ( &v4[24 * v5] == v8 )\n goto LABEL_9;\n }\n v19 = v7;\n v3 += 2;\n v9 = *((_QWORD *)v8 + 2) + 1LL;\n v18 = *((_QWORD *)v8 + 2);\n v10 = realloc(*((void **)v8 + 1), v9);\n v11 = *(v3 - 1);\n *((_QWORD *)v8 + 1) = v10;\n v10[v18] = v11;\n *((_QWORD *)v8 + 2) = v9;\n if ( v3 == v17 )\n break;\n v6 = *v3;\n v7 = v19;\n }\n }\n else\n {\n v5 = 0;\n }\nLABEL_10:\n *a3 = v5;\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1490(char *a1, long long a2, int *a3) {\n char *v3;\n char *v4;\n int v5;\n char v6;\n long long v7;\n char *v8;\n unsigned int v9;\n uint8_t *v10;\n char v11;\n char *v12;\n unsigned short *v13;\n char v14;\n short v15;\n char *v17;\n long long v18;\n long long v19;\n v3 = a1;\n v4 = (char *)malloc(24 * a2);\n if (a2) {\n v5 = 0;\n v17 = &a1[2 * a2];\n while (1) {\n v6 = *v3;\n v7 = v5;\n if (v5 > 0) break;\n LABEL_9:\n v3 += 2;\n ++v5;\n v12 = &v4[24 * v7];\n *v12 = v6;\n v13 = malloc(2uLL);\n v14 = *(v3 - 1);\n LOBYTE(v15) = v6;\n *((uint64_t *)v12 + 2) = 2LL;\n *((uint64_t *)v12 + 1) = v13;\n HIBYTE(v15) = v14;\n *v13 = v15;\n if (v3 == v17) goto LABEL_10;\n }\n while (1) {\n v8 = v4;\n while (*v8 != v6) {\n v8 += 24;\n if (&v4[24 * v5] == v8) goto LABEL_9;\n }\n v19 = v7;\n v3 += 2;\n v9 = *((uint64_t *)v8 + 2) + 1LL;\n v18 = *((uint64_t *)v8 + 2);\n v10 = realloc(*((void **)v8 + 1), v9);\n v11 = *(v3 - 1);\n *((uint64_t *)v8 + 1) = v10;\n v10[v18] = v11;\n *((uint64_t *)v8 + 2) = v9;\n if (v3 == v17) break;\n v6 = *v3;\n v7 = v19;\n }\n } else {\n v5 = 0;\n }\nLABEL_10:\n *a3 = v5;\n return v4;\n}", + "ida_pseudo_norm": "char *func0(char *a1, long long a2, int *a3) {\n char *v3;\n char *v4;\n int v5;\n char v6;\n long long v7;\n char *v8;\n unsigned int v9;\n uint8_t *v10;\n char v11;\n char *v12;\n unsigned short *v13;\n char v14;\n short v15;\n char *v17;\n long long v18;\n long long v19;\n v3 = a1;\n v4 = (char *)malloc(24 * a2);\n if (a2) {\n v5 = 0;\n v17 = &a1[2 * a2];\n while (1) {\n v6 = *v3;\n v7 = v5;\n if (v5 > 0) break;\n LABEL_9:\n v3 += 2;\n ++v5;\n v12 = &v4[24 * v7];\n *v12 = v6;\n v13 = malloc(2uLL);\n v14 = *(v3 - 1);\n LOBYTE(v15) = v6;\n *((uint64_t *)v12 + 2) = 2LL;\n *((uint64_t *)v12 + 1) = v13;\n HIBYTE(v15) = v14;\n *v13 = v15;\n if (v3 == v17) goto LABEL_10;\n }\n while (1) {\n v8 = v4;\n while (*v8 != v6) {\n v8 += 24;\n if (&v4[24 * v5] == v8) goto LABEL_9;\n }\n v19 = v7;\n v3 += 2;\n v9 = *((uint64_t *)v8 + 2) + 1LL;\n v18 = *((uint64_t *)v8 + 2);\n v10 = realloc(*((void **)v8 + 1), v9);\n v11 = *(v3 - 1);\n *((uint64_t *)v8 + 1) = v10;\n v10[v18] = v11;\n *((uint64_t *)v8 + 2) = v9;\n if (v3 == v17) break;\n v6 = *v3;\n v7 = v19;\n }\n } else {\n v5 = 0;\n }\nLABEL_10:\n *a3 = v5;\n return v4;\n}" + }, + { + "index": 417, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char key;\n\n char *values;\n\n size_t size;\n\n} TupleGroup;\n\n\n\n", + "func": "TupleGroup *func0(char Input[][2], size_t n, int *returnSize) {\n TupleGroup *out = malloc(n * sizeof(TupleGroup));\n int outCount = 0;\n for (int i = 0; i < n; i++) {\n int found = 0;\n for (int j = 0; j < outCount; j++) {\n if (out[j].key == Input[i][0]) {\n size_t new_size = out[j].size + 1;\n out[j].values = realloc(out[j].values, new_size);\n out[j].values[new_size - 1] = Input[i][1];\n out[j].size = new_size;\n found = 1;\n break;\n }\n }\n if (!found) {\n out[outCount].key = Input[i][0];\n out[outCount].values = malloc(2);\n out[outCount].values[0] = Input[i][0];\n out[outCount].values[1] = Input[i][1];\n out[outCount].size = 2;\n outCount++;\n }\n }\n *returnSize = outCount;\n return out;\n}", + "test": "int main() {\n\n char input1[][2] = { {'x', 'y'}, {'x', 'z'}, {'w', 't'} };\n\n int size1;\n\n TupleGroup *result1 = func0(input1, 3, &size1);\n\n assert(size1 == 2);\n\n assert(memcmp(result1[0].values, \"xyz\", 3) == 0 && result1[0].size == 3);\n\n assert(memcmp(result1[1].values, \"wt\", 2) == 0 && result1[1].size == 2);\n\n free(result1[0].values);\n\n free(result1[1].values);\n\n free(result1);\n\n\n\n char input2[][2] = { {'a', 'b'}, {'a', 'c'}, {'d', 'e'} };\n\n int size2;\n\n TupleGroup *result2 = func0(input2, 3, &size2);\n\n assert(size2 == 2);\n\n assert(memcmp(result2[0].values, \"abc\", 3) == 0 && result2[0].size == 3);\n\n assert(memcmp(result2[1].values, \"de\", 2) == 0 && result2[1].size == 2);\n\n free(result2[0].values);\n\n free(result2[1].values);\n\n free(result2);\n\n\n\n char input3[][2] = { {'f', 'g'}, {'f', 'g'}, {'h', 'i'} };\n\n int size3;\n\n TupleGroup *result3 = func0(input3, 3, &size3);\n\n assert(size3 == 2);\n\n assert(memcmp(result3[0].values, \"fgg\", 3) == 0 && result3[0].size == 3);\n\n assert(memcmp(result3[1].values, \"hi\", 2) == 0 && result3[1].size == 2);\n\n free(result3[0].values);\n\n free(result3[1].values);\n\n free(result3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\nmov %rdi,%r14\npush %r13\nlea (%rsi,%rsi,1),%r13\npush %r12\nlea 0x0(%r13,%rsi,1),%rdi\npush %rbp\nshl $0x3,%rdi\npush %rbx\nmov %rsi,%rbx\nsub $0x28,%rsp\nmov %rdx,0x18(%rsp)\ncallq 10c0 \nmov %rax,%r12\ntest %rbx,%rbx\nje 15a6 \nlea (%r14,%r13,1),%rax\nxor %r15d,%r15d\nmov %rax,0x8(%rsp)\nlea 0x18(%r12),%rax\nmov %rax,0x10(%rsp)\nnopl 0x0(%rax)\nmovzbl (%r14),%ebp\ntest %r15d,%r15d\nje 1570 \nmov 0x10(%rsp),%rcx\nlea -0x1(%r15),%eax\nmov %r12,%rbx\nlea (%rax,%rax,2),%rax\nlea (%rcx,%rax,8),%rax\njmp 1519 \nnopw 0x0(%rax,%rax,1)\nadd $0x18,%rbx\ncmp %rax,%rbx\nje 1570 \ncmp %bpl,(%rbx)\njne 1510 \nmov 0x10(%rbx),%r13\nmov 0x8(%rbx),%rdi\nlea 0x1(%r13),%rbp\nmov %rbp,%rsi\ncallq 10d0 \nmovzbl 0x1(%r14),%esi\nmov %rax,0x8(%rbx)\nmov %sil,(%rax,%r13,1)\nmov %rbp,0x10(%rbx)\nadd $0x2,%r14\ncmp %r14,0x8(%rsp)\njne 14e8 \nmov 0x18(%rsp),%rax\nmov %r15d,(%rax)\nadd $0x28,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax,%rax,1)\nmovslq %r15d,%rax\nmov $0x2,%edi\nadd $0x1,%r15d\nlea (%rax,%rax,2),%rax\nlea (%r12,%rax,8),%rbx\nmov %bpl,(%rbx)\ncallq 10c0 \nmovzbl 0x1(%r14),%esi\nmovq $0x2,0x10(%rbx)\nmov %rax,0x8(%rbx)\nmov %bpl,(%rax)\nmov %sil,0x1(%rax)\njmp 1543 \nxor %r15d,%r15d\njmp 154e \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14, rdi\npush r13\npush r12\npush rbp\nlea rbp, [rsi+rsi]\npush rbx\nlea rdi, [rbp+rsi+0]\nmov rbx, rsi\nshl rdi, 3; size\nsub rsp, 28h\nmov [rsp+58h+var_40], rdx\ncall _malloc\nmov r13, rax\ntest rbx, rbx\njz loc_15BF\nlea rax, [r14+rbp]\nxor r15d, r15d\nmov [rsp+58h+var_58], rax\nnop word ptr [rax+rax+00000000h]\nloc_14E0:\nmovzx ebp, byte ptr [r14]\nmovsxd rcx, r15d\ntest r15d, r15d\njle short loc_1560\nlea rax, [rcx+rcx*2]\nlea r12, [r13+rax*8+0]\nloc_14F5:\nmov rbx, r13\njmp short loc_1509\nloc_1500:\nadd rbx, 18h\ncmp rbx, r12\njz short loc_1560\nloc_1509:\ncmp [rbx], bpl\njnz short loc_1500\nmov r9, [rbx+10h]\nmov rdi, [rbx+8]; ptr\nmov [rsp+58h+var_48], rcx\nadd r14, 2\nlea rbp, [r9+1]\nmov [rsp+58h+var_50], r9\nmov rsi, rbp; size\ncall _realloc\nmovzx esi, byte ptr [r14-1]\nmov r9, [rsp+58h+var_50]\nmov [rbx+8], rax\nmov [rax+r9], sil\nmov rax, [rsp+58h+var_58]\nmov [rbx+10h], rbp\ncmp r14, rax\njz short loc_15A5\nmovzx ebp, byte ptr [r14]\nmov rcx, [rsp+58h+var_48]\njmp short loc_14F5\nloc_1560:\nlea rax, [rcx+rcx*2]\nmov edi, 2; size\nadd r14, 2\nadd r15d, 1\nlea rbx, [r13+rax*8+0]\nmov [rbx], bpl\ncall _malloc\nmovzx edx, byte ptr [r14-1]\nmovzx ecx, bpl\nmov qword ptr [rbx+10h], 2\nmov [rbx+8], rax\nmov ch, dl\nmov [rax], cx\nmov rax, [rsp+58h+var_58]\ncmp r14, rax\njnz loc_14E0\nloc_15A5:\nmov rax, [rsp+58h+var_40]\nmov [rax], r15d\nadd rsp, 28h\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15BF:\nxor r15d, r15d\njmp short loc_15A5", + "ida_pseudo": "char *__fastcall func0(char *a1, __int64 a2, int *a3)\n{\n char *v3; // r14\n char *v4; // r13\n int v5; // r15d\n char v6; // bp\n __int64 v7; // rcx\n char *v8; // rbx\n size_t v9; // rbp\n _BYTE *v10; // rax\n char v11; // si\n char *v12; // rbx\n _WORD *v13; // rax\n char v14; // dl\n __int16 v15; // cx\n char *v17; // [rsp+0h] [rbp-58h]\n __int64 v18; // [rsp+8h] [rbp-50h]\n __int64 v19; // [rsp+10h] [rbp-48h]\n\n v3 = a1;\n v4 = (char *)malloc(24 * a2);\n if ( a2 )\n {\n v5 = 0;\n v17 = &a1[2 * a2];\n while ( 1 )\n {\n v6 = *v3;\n v7 = v5;\n if ( v5 > 0 )\n break;\nLABEL_9:\n v3 += 2;\n ++v5;\n v12 = &v4[24 * v7];\n *v12 = v6;\n v13 = malloc(2uLL);\n v14 = *(v3 - 1);\n LOBYTE(v15) = v6;\n *((_QWORD *)v12 + 2) = 2LL;\n *((_QWORD *)v12 + 1) = v13;\n HIBYTE(v15) = v14;\n *v13 = v15;\n if ( v3 == v17 )\n goto LABEL_10;\n }\n while ( 1 )\n {\n v8 = v4;\n while ( *v8 != v6 )\n {\n v8 += 24;\n if ( v8 == &v4[24 * v5] )\n goto LABEL_9;\n }\n v19 = v7;\n v3 += 2;\n v9 = *((_QWORD *)v8 + 2) + 1LL;\n v18 = *((_QWORD *)v8 + 2);\n v10 = realloc(*((void **)v8 + 1), v9);\n v11 = *(v3 - 1);\n *((_QWORD *)v8 + 1) = v10;\n v10[v18] = v11;\n *((_QWORD *)v8 + 2) = v9;\n if ( v3 == v17 )\n break;\n v6 = *v3;\n v7 = v19;\n }\n }\n else\n {\n v5 = 0;\n }\nLABEL_10:\n *a3 = v5;\n return v4;\n}", + "ida_strip_asm": "sub_1490:\nendbr64\npush r15\npush r14\nmov r14, rdi\npush r13\npush r12\npush rbp\nlea rbp, [rsi+rsi]\npush rbx\nlea rdi, [rbp+rsi+0]\nmov rbx, rsi\nshl rdi, 3; size\nsub rsp, 28h\nmov [rsp+58h+var_40], rdx\ncall _malloc\nmov r13, rax\ntest rbx, rbx\njz loc_15BF\nlea rax, [r14+rbp]\nxor r15d, r15d\nmov [rsp+58h+var_58], rax\nnop word ptr [rax+rax+00000000h]\nloc_14E0:\nmovzx ebp, byte ptr [r14]\nmovsxd rcx, r15d\ntest r15d, r15d\njle short loc_1560\nlea rax, [rcx+rcx*2]\nlea r12, [r13+rax*8+0]\nloc_14F5:\nmov rbx, r13\njmp short loc_1509\nloc_1500:\nadd rbx, 18h\ncmp rbx, r12\njz short loc_1560\nloc_1509:\ncmp [rbx], bpl\njnz short loc_1500\nmov r9, [rbx+10h]\nmov rdi, [rbx+8]; ptr\nmov [rsp+58h+var_48], rcx\nadd r14, 2\nlea rbp, [r9+1]\nmov [rsp+58h+var_50], r9\nmov rsi, rbp; size\ncall _realloc\nmovzx esi, byte ptr [r14-1]\nmov r9, [rsp+58h+var_50]\nmov [rbx+8], rax\nmov [rax+r9], sil\nmov rax, [rsp+58h+var_58]\nmov [rbx+10h], rbp\ncmp r14, rax\njz short loc_15A5\nmovzx ebp, byte ptr [r14]\nmov rcx, [rsp+58h+var_48]\njmp short loc_14F5\nloc_1560:\nlea rax, [rcx+rcx*2]\nmov edi, 2; size\nadd r14, 2\nadd r15d, 1\nlea rbx, [r13+rax*8+0]\nmov [rbx], bpl\ncall _malloc\nmovzx edx, byte ptr [r14-1]\nmovzx ecx, bpl\nmov qword ptr [rbx+10h], 2\nmov [rbx+8], rax\nmov ch, dl\nmov [rax], cx\nmov rax, [rsp+58h+var_58]\ncmp r14, rax\njnz loc_14E0\nloc_15A5:\nmov rax, [rsp+58h+var_40]\nmov [rax], r15d\nadd rsp, 28h\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15BF:\nxor r15d, r15d\njmp short loc_15A5", + "ida_strip_pseudo": "char *__fastcall sub_1490(char *a1, __int64 a2, int *a3)\n{\n char *v3; // r14\n char *v4; // r13\n int v5; // r15d\n char v6; // bp\n __int64 v7; // rcx\n char *v8; // rbx\n size_t v9; // rbp\n _BYTE *v10; // rax\n char v11; // si\n char *v12; // rbx\n _WORD *v13; // rax\n char v14; // dl\n __int16 v15; // cx\n char *v17; // [rsp+0h] [rbp-58h]\n __int64 v18; // [rsp+8h] [rbp-50h]\n __int64 v19; // [rsp+10h] [rbp-48h]\n\n v3 = a1;\n v4 = (char *)malloc(24 * a2);\n if ( a2 )\n {\n v5 = 0;\n v17 = &a1[2 * a2];\n while ( 1 )\n {\n v6 = *v3;\n v7 = v5;\n if ( v5 > 0 )\n break;\nLABEL_9:\n v3 += 2;\n ++v5;\n v12 = &v4[24 * v7];\n *v12 = v6;\n v13 = malloc(2uLL);\n v14 = *(v3 - 1);\n LOBYTE(v15) = v6;\n *((_QWORD *)v12 + 2) = 2LL;\n *((_QWORD *)v12 + 1) = v13;\n HIBYTE(v15) = v14;\n *v13 = v15;\n if ( v3 == v17 )\n goto LABEL_10;\n }\n while ( 1 )\n {\n v8 = v4;\n while ( *v8 != v6 )\n {\n v8 += 24;\n if ( v8 == &v4[24 * v5] )\n goto LABEL_9;\n }\n v19 = v7;\n v3 += 2;\n v9 = *((_QWORD *)v8 + 2) + 1LL;\n v18 = *((_QWORD *)v8 + 2);\n v10 = realloc(*((void **)v8 + 1), v9);\n v11 = *(v3 - 1);\n *((_QWORD *)v8 + 1) = v10;\n v10[v18] = v11;\n *((_QWORD *)v8 + 2) = v9;\n if ( v3 == v17 )\n break;\n v6 = *v3;\n v7 = v19;\n }\n }\n else\n {\n v5 = 0;\n }\nLABEL_10:\n *a3 = v5;\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1490(char *a1, long long a2, int *a3) {\n char *v3;\n char *v4;\n int v5;\n char v6;\n long long v7;\n char *v8;\n unsigned int v9;\n uint8_t *v10;\n char v11;\n char *v12;\n unsigned short *v13;\n char v14;\n short v15;\n char *v17;\n long long v18;\n long long v19;\n v3 = a1;\n v4 = (char *)malloc(24 * a2);\n if (a2) {\n v5 = 0;\n v17 = &a1[2 * a2];\n while (1) {\n v6 = *v3;\n v7 = v5;\n if (v5 > 0) break;\n LABEL_9:\n v3 += 2;\n ++v5;\n v12 = &v4[24 * v7];\n *v12 = v6;\n v13 = malloc(2uLL);\n v14 = *(v3 - 1);\n LOBYTE(v15) = v6;\n *((uint64_t *)v12 + 2) = 2LL;\n *((uint64_t *)v12 + 1) = v13;\n HIBYTE(v15) = v14;\n *v13 = v15;\n if (v3 == v17) goto LABEL_10;\n }\n while (1) {\n v8 = v4;\n while (*v8 != v6) {\n v8 += 24;\n if (v8 == &v4[24 * v5]) goto LABEL_9;\n }\n v19 = v7;\n v3 += 2;\n v9 = *((uint64_t *)v8 + 2) + 1LL;\n v18 = *((uint64_t *)v8 + 2);\n v10 = realloc(*((void **)v8 + 1), v9);\n v11 = *(v3 - 1);\n *((uint64_t *)v8 + 1) = v10;\n v10[v18] = v11;\n *((uint64_t *)v8 + 2) = v9;\n if (v3 == v17) break;\n v6 = *v3;\n v7 = v19;\n }\n } else {\n v5 = 0;\n }\nLABEL_10:\n *a3 = v5;\n return v4;\n}", + "ida_pseudo_norm": "char *func0(char *a1, long long a2, int *a3) {\n char *v3;\n char *v4;\n int v5;\n char v6;\n long long v7;\n char *v8;\n unsigned int v9;\n uint8_t *v10;\n char v11;\n char *v12;\n unsigned short *v13;\n char v14;\n short v15;\n char *v17;\n long long v18;\n long long v19;\n v3 = a1;\n v4 = (char *)malloc(24 * a2);\n if (a2) {\n v5 = 0;\n v17 = &a1[2 * a2];\n while (1) {\n v6 = *v3;\n v7 = v5;\n if (v5 > 0) break;\n LABEL_9:\n v3 += 2;\n ++v5;\n v12 = &v4[24 * v7];\n *v12 = v6;\n v13 = malloc(2uLL);\n v14 = *(v3 - 1);\n LOBYTE(v15) = v6;\n *((uint64_t *)v12 + 2) = 2LL;\n *((uint64_t *)v12 + 1) = v13;\n HIBYTE(v15) = v14;\n *v13 = v15;\n if (v3 == v17) goto LABEL_10;\n }\n while (1) {\n v8 = v4;\n while (*v8 != v6) {\n v8 += 24;\n if (v8 == &v4[24 * v5]) goto LABEL_9;\n }\n v19 = v7;\n v3 += 2;\n v9 = *((uint64_t *)v8 + 2) + 1LL;\n v18 = *((uint64_t *)v8 + 2);\n v10 = realloc(*((void **)v8 + 1), v9);\n v11 = *(v3 - 1);\n *((uint64_t *)v8 + 1) = v10;\n v10[v18] = v11;\n *((uint64_t *)v8 + 2) = v9;\n if (v3 == v17) break;\n v6 = *v3;\n v7 = v19;\n }\n } else {\n v5 = 0;\n }\nLABEL_10:\n *a3 = v5;\n return v4;\n}" + }, + { + "index": 418, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int* func0(int lst[][4], int rows) {\n int max_len = 0;\n int* maxList = lst[0];\n for (int i = 0; i < rows; i++) {\n for (int j = 0; lst[i][j] != '\\0'; j++) {\n if (j > max_len) {\n max_len = j;\n maxList = lst[i];\n }\n }\n }\n return maxList;\n}", + "test": "int main() {\n\n int list1[][4] = {{'A','\\0'}, {'A','B','\\0'}, {'A','B','C','\\0'}};\n\n int list2[][4] = {{1,'\\0'}, {1, 2, '\\0'}, {1, 2, 3, '\\0'}};\n\n int list3[][4] = {{1,1,'\\0'}, {1, 2, 3, '\\0'}, {1, 5, 6, 1, '\\0'}};\n\n\n\n assert(func0(list1, 3)[2] == 'C');\n\n assert(func0(list2, 3)[2] == 3);\n\n assert(func0(list3, 3)[3] == 1);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmovl $0x0,-0x14(%rbp)\nmov -0x28(%rbp),%rax\nmov %rax,-0x8(%rbp)\nmovl $0x0,-0x10(%rbp)\njmp 1205 \nmovl $0x0,-0xc(%rbp)\njmp 11e2 \nmov -0xc(%rbp),%eax\ncmp -0x14(%rbp),%eax\njle 11de \nmov -0xc(%rbp),%eax\nmov %eax,-0x14(%rbp)\nmov -0x10(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov %rax,-0x8(%rbp)\naddl $0x1,-0xc(%rbp)\nmov -0x10(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x28(%rbp),%rax\nadd %rax,%rdx\nmov -0xc(%rbp),%eax\ncltq\nmov (%rdx,%rax,4),%eax\ntest %eax,%eax\njne 11b9 \naddl $0x1,-0x10(%rbp)\nmov -0x10(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 11b0 \nmov -0x8(%rbp),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_14], 0\nmov rax, [rbp+var_28]\nmov [rbp+var_8], rax\nmov [rbp+var_10], 0\njmp short loc_1205\nloc_11B0:\nmov [rbp+var_C], 0\njmp short loc_11E2\nloc_11B9:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_14]\njle short loc_11DE\nmov eax, [rbp+var_C]\nmov [rbp+var_14], eax\nmov eax, [rbp+var_10]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov [rbp+var_8], rax\nloc_11DE:\nadd [rbp+var_C], 1\nloc_11E2:\nmov eax, [rbp+var_10]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov eax, [rbp+var_C]\ncdqe\nmov eax, [rdx+rax*4]\ntest eax, eax\njnz short loc_11B9\nadd [rbp+var_10], 1\nloc_1205:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_2C]\njl short loc_11B0\nmov rax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int v3; // [rsp+18h] [rbp-14h]\n int i; // [rsp+1Ch] [rbp-10h]\n int j; // [rsp+20h] [rbp-Ch]\n __int64 v6; // [rsp+24h] [rbp-8h]\n\n v3 = 0;\n v6 = a1;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = 0; *(_DWORD *)(a1 + 16LL * i + 4LL * j); ++j )\n {\n if ( j > v3 )\n {\n v3 = j;\n v6 = 16LL * i + a1;\n }\n }\n }\n return v6;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_14], 0\nmov rax, [rbp+var_28]\nmov [rbp+var_8], rax\nmov [rbp+var_10], 0\njmp short loc_1205\nloc_11B0:\nmov [rbp+var_C], 0\njmp short loc_11E2\nloc_11B9:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_14]\njle short loc_11DE\nmov eax, [rbp+var_C]\nmov [rbp+var_14], eax\nmov eax, [rbp+var_10]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov [rbp+var_8], rax\nloc_11DE:\nadd [rbp+var_C], 1\nloc_11E2:\nmov eax, [rbp+var_10]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov eax, [rbp+var_C]\ncdqe\nmov eax, [rdx+rax*4]\ntest eax, eax\njnz short loc_11B9\nadd [rbp+var_10], 1\nloc_1205:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_2C]\njl short loc_11B0\nmov rax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2)\n{\n int v3; // [rsp+18h] [rbp-14h]\n int i; // [rsp+1Ch] [rbp-10h]\n int j; // [rsp+20h] [rbp-Ch]\n __int64 v6; // [rsp+24h] [rbp-8h]\n\n v3 = 0;\n v6 = a1;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = 0; *(_DWORD *)(a1 + 16LL * i + 4LL * j); ++j )\n {\n if ( j > v3 )\n {\n v3 = j;\n v6 = 16LL * i + a1;\n }\n }\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2) {\n int v3;\n int i;\n int j;\n long long v6;\n v3 = 0;\n v6 = a1;\n for (i = 0; i < a2; ++i) {\n for (j = 0; *(uint32_t *)(a1 + 16LL * i + 4LL * j); ++j) {\n if (j > v3) {\n v3 = j;\n v6 = 16LL * i + a1;\n }\n }\n }\n return v6;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int v3;\n int i;\n int j;\n long long v6;\n v3 = 0;\n v6 = a1;\n for (i = 0; i < a2; ++i) {\n for (j = 0; *(uint32_t *)(a1 + 16LL * i + 4LL * j); ++j) {\n if (j > v3) {\n v3 = j;\n v6 = 16LL * i + a1;\n }\n }\n }\n return v6;\n}" + }, + { + "index": 418, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int* func0(int lst[][4], int rows) {\n int max_len = 0;\n int* maxList = lst[0];\n for (int i = 0; i < rows; i++) {\n for (int j = 0; lst[i][j] != '\\0'; j++) {\n if (j > max_len) {\n max_len = j;\n maxList = lst[i];\n }\n }\n }\n return maxList;\n}", + "test": "int main() {\n\n int list1[][4] = {{'A','\\0'}, {'A','B','\\0'}, {'A','B','C','\\0'}};\n\n int list2[][4] = {{1,'\\0'}, {1, 2, '\\0'}, {1, 2, 3, '\\0'}};\n\n int list3[][4] = {{1,1,'\\0'}, {1, 2, 3, '\\0'}, {1, 5, 6, 1, '\\0'}};\n\n\n\n assert(func0(list1, 3)[2] == 'C');\n\n assert(func0(list2, 3)[2] == 3);\n\n assert(func0(list3, 3)[3] == 1);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11d8 \nmov %rdi,%r8\nlea -0x1(%rsi),%eax\nshl $0x4,%rax\nlea 0x10(%rdi,%rax,1),%r9\nmov $0x0,%edx\njmp 11c5 \nadd $0x1,%rax\ncmpl $0x0,(%rcx,%rax,4)\nje 11bc \ncmp %eax,%edx\njge 11a7 \nmov %rsi,%rdi\nmov %eax,%edx\njmp 11a7 \nadd $0x10,%r8\ncmp %r9,%r8\nje 11d8 \nmov %r8,%rcx\nmov $0x0,%eax\nmov %r8,%rsi\ncmpl $0x0,(%r8)\njne 11b1 \njmp 11bc \nmov %rdi,%rax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11D1\nmov r8, rdi\nmovsxd rsi, esi\nshl rsi, 4\nadd rsi, rdi\nmov edx, 0\njmp short loc_11C1\nloc_11A5:\ncmp edx, eax\ncmovl edx, eax\ncmovl rdi, rcx\nadd rax, 1\ncmp dword ptr [rcx+rax*4], 0\njnz short loc_11A5\nloc_11B8:\nadd r8, 10h\ncmp r8, rsi\njz short loc_11D1\nloc_11C1:\nmov rcx, r8\nmov eax, 0\ncmp dword ptr [r8], 0\njnz short loc_11A5\njmp short loc_11B8\nloc_11D1:\nmov rax, rdi\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // r8\n _DWORD *v3; // rsi\n int v4; // edx\n __int64 v5; // rax\n\n if ( a2 > 0 )\n {\n v2 = a1;\n v3 = &a1[4 * a2];\n v4 = 0;\n do\n {\n v5 = 0LL;\n if ( *v2 )\n {\n do\n {\n if ( v4 < (int)v5 )\n {\n v4 = v5;\n a1 = v2;\n }\n ++v5;\n }\n while ( v2[v5] );\n }\n v2 += 4;\n }\n while ( v2 != v3 );\n }\n return a1;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\ntest esi, esi\njle short loc_11D1\nmov r8, rdi\nmovsxd rsi, esi\nshl rsi, 4\nadd rsi, rdi\nmov edx, 0\njmp short loc_11C1\nloc_11A5:\ncmp edx, eax\ncmovl edx, eax\ncmovl rdi, rcx\nadd rax, 1\ncmp dword ptr [rcx+rax*4], 0\njnz short loc_11A5\nloc_11B8:\nadd r8, 10h\ncmp r8, rsi\njz short loc_11D1\nloc_11C1:\nmov rcx, r8\nmov eax, 0\ncmp dword ptr [r8], 0\njnz short loc_11A5\njmp short loc_11B8\nloc_11D1:\nmov rax, rdi\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1189(_DWORD *a1, int a2)\n{\n _DWORD *v2; // r8\n _DWORD *v3; // rsi\n int v4; // edx\n __int64 v5; // rax\n\n if ( a2 > 0 )\n {\n v2 = a1;\n v3 = &a1[4 * a2];\n v4 = 0;\n do\n {\n v5 = 0LL;\n if ( *v2 )\n {\n do\n {\n if ( v4 < (int)v5 )\n {\n v4 = v5;\n a1 = v2;\n }\n ++v5;\n }\n while ( v2[v5] );\n }\n v2 += 4;\n }\n while ( v2 != v3 );\n }\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1189(uint32_t *a1, int a2) {\n uint32_t *v2;\n uint32_t *v3;\n int v4;\n long long v5;\n if (a2 > 0) {\n v2 = a1;\n v3 = &a1[4 * a2];\n v4 = 0;\n do {\n v5 = 0LL;\n if (*v2) {\n do {\n if (v4 < (int)v5) {\n v4 = v5;\n a1 = v2;\n }\n ++v5;\n } while (v2[v5]);\n }\n v2 += 4;\n } while (v2 != v3);\n }\n return a1;\n}", + "ida_pseudo_norm": "uint32_t *func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n uint32_t *v3;\n int v4;\n long long v5;\n if (a2 > 0) {\n v2 = a1;\n v3 = &a1[4 * a2];\n v4 = 0;\n do {\n v5 = 0LL;\n if (*v2) {\n do {\n if (v4 < (int)v5) {\n v4 = v5;\n a1 = v2;\n }\n ++v5;\n } while (v2[v5]);\n }\n v2 += 4;\n } while (v2 != v3);\n }\n return a1;\n}" + }, + { + "index": 418, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int* func0(int lst[][4], int rows) {\n int max_len = 0;\n int* maxList = lst[0];\n for (int i = 0; i < rows; i++) {\n for (int j = 0; lst[i][j] != '\\0'; j++) {\n if (j > max_len) {\n max_len = j;\n maxList = lst[i];\n }\n }\n }\n return maxList;\n}", + "test": "int main() {\n\n int list1[][4] = {{'A','\\0'}, {'A','B','\\0'}, {'A','B','C','\\0'}};\n\n int list2[][4] = {{1,'\\0'}, {1, 2, '\\0'}, {1, 2, 3, '\\0'}};\n\n int list3[][4] = {{1,1,'\\0'}, {1, 2, 3, '\\0'}, {1, 5, 6, 1, '\\0'}};\n\n\n\n assert(func0(list1, 3)[2] == 'C');\n\n assert(func0(list2, 3)[2] == 3);\n\n assert(func0(list3, 3)[3] == 1);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1463 \nlea -0x1(%rsi),%eax\nmov %rdi,%r8\nxor %edx,%edx\nshl $0x4,%rax\nlea 0x10(%rdi,%rax,1),%rcx\nnopl 0x0(%rax)\nmov (%rdi),%esi\nxor %eax,%eax\ntest %esi,%esi\nje 1456 \nnopl 0x0(%rax,%rax,1)\ncmp %eax,%edx\njge 1449 \nmov %rdi,%r8\nmov %eax,%edx\nadd $0x1,%rax\nmov (%rdi,%rax,4),%r9d\ntest %r9d,%r9d\njne 1440 \nadd $0x10,%rdi\ncmp %rcx,%rdi\njne 1430 \nmov %r8,%rax\nretq\nmov %rdi,%r8\nmov %r8,%rax\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_136D\nmovsxd rsi, esi\nmov rcx, rdi\nxor edx, edx\nshl rsi, 4\nadd rsi, rdi\nnop word ptr [rax+rax+00000000h]\nloc_1340:\nmov r8d, [rdi]\nxor eax, eax\ntest r8d, r8d\njz short loc_1360\nloc_134A:\ncmp edx, eax\ncmovl edx, eax\ncmovl rcx, rdi\nadd rax, 1\nmov r9d, [rdi+rax*4]\ntest r9d, r9d\njnz short loc_134A\nloc_1360:\nadd rdi, 10h\ncmp rdi, rsi\njnz short loc_1340\nmov rax, rcx\nretn\nloc_136D:\nmov rcx, rdi\nmov rax, rcx\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rcx\n int v3; // edx\n _DWORD *v4; // rsi\n __int64 v5; // rax\n\n if ( a2 <= 0 )\n return a1;\n v2 = a1;\n v3 = 0;\n v4 = &a1[4 * a2];\n do\n {\n v5 = 0LL;\n if ( *a1 )\n {\n do\n {\n if ( v3 < (int)v5 )\n {\n v3 = v5;\n v2 = a1;\n }\n ++v5;\n }\n while ( a1[v5] );\n }\n a1 += 4;\n }\n while ( a1 != v4 );\n return v2;\n}", + "ida_strip_asm": "sub_1320:\nendbr64\ntest esi, esi\njle short loc_136D\nmovsxd rsi, esi\nmov rcx, rdi\nxor edx, edx\nshl rsi, 4\nadd rsi, rdi\nnop word ptr [rax+rax+00000000h]\nloc_1340:\nmov r8d, [rdi]\nxor eax, eax\ntest r8d, r8d\njz short loc_1360\nloc_134A:\ncmp edx, eax\ncmovl edx, eax\ncmovl rcx, rdi\nadd rax, 1\nmov r9d, [rdi+rax*4]\ntest r9d, r9d\njnz short loc_134A\nloc_1360:\nadd rdi, 10h\ncmp rdi, rsi\njnz short loc_1340\nmov rax, rcx\nretn\nloc_136D:\nmov rcx, rdi\nmov rax, rcx\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1320(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rcx\n int v3; // edx\n _DWORD *v4; // rsi\n __int64 v5; // rax\n\n if ( a2 <= 0 )\n return a1;\n v2 = a1;\n v3 = 0;\n v4 = &a1[4 * a2];\n do\n {\n v5 = 0LL;\n if ( *a1 )\n {\n do\n {\n if ( v3 < (int)v5 )\n {\n v3 = v5;\n v2 = a1;\n }\n ++v5;\n }\n while ( a1[v5] );\n }\n a1 += 4;\n }\n while ( a1 != v4 );\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1320(uint32_t *a1, int a2) {\n uint32_t *v2;\n int v3;\n uint32_t *v4;\n long long v5;\n if (a2 <= 0) return a1;\n v2 = a1;\n v3 = 0;\n v4 = &a1[4 * a2];\n do {\n v5 = 0LL;\n if (*a1) {\n do {\n if (v3 < (int)v5) {\n v3 = v5;\n v2 = a1;\n }\n ++v5;\n } while (a1[v5]);\n }\n a1 += 4;\n } while (a1 != v4);\n return v2;\n}", + "ida_pseudo_norm": "uint32_t *func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n int v3;\n uint32_t *v4;\n long long v5;\n if (a2 <= 0) return a1;\n v2 = a1;\n v3 = 0;\n v4 = &a1[4 * a2];\n do {\n v5 = 0LL;\n if (*a1) {\n do {\n if (v3 < (int)v5) {\n v3 = v5;\n v2 = a1;\n }\n ++v5;\n } while (a1[v5]);\n }\n a1 += 4;\n } while (a1 != v4);\n return v2;\n}" + }, + { + "index": 419, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(double list1[], int length) {\n int i;\n int sum = 0;\n for (i = 0; i < length; i++) {\n sum += round(list1[i]);\n }\n return sum * length;\n}", + "test": "int main() {\n\n double list1[] = {22.4, 4.0, -16.22, -9.10, 11.00, -12.22, 14.20, -5.20, 17.50};\n\n double list2[] = {5, 2, 9, 24.3, 29};\n\n double list3[] = {25.0, 56.7, 89.2};\n\n \n\n assert(func0(list1, sizeof(list1) / sizeof(list1[0])) == 243);\n\n assert(func0(list2, sizeof(list2) / sizeof(list2[0])) == 345);\n\n assert(func0(list3, sizeof(list3) / sizeof(list3[0])) == 513);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x4(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11e7 \ncvtsi2sdl -0x4(%rbp),%xmm1\nmovsd %xmm1,-0x28(%rbp)\nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmovq %rax,%xmm0\ncallq 1070 \naddsd -0x28(%rbp),%xmm0\ncvttsd2si %xmm0,%eax\nmov %eax,-0x4(%rbp)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11ac \nmov -0x4(%rbp),%eax\nimul -0x1c(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 0\nmov [rbp+var_8], 0\njmp short loc_11EB\nloc_11AC:\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_4]\nmovsd [rbp+var_28], xmm1\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmovq xmm0, rax; x\ncall _round\naddsd xmm0, [rbp+var_28]\ncvttsd2si eax, xmm0\nmov [rbp+var_4], eax\nadd [rbp+var_8], 1\nloc_11EB:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_11AC\nmov eax, [rbp+var_4]\nimul eax, [rbp+var_1C]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+28h] [rbp-8h]\n int v4; // [rsp+2Ch] [rbp-4h]\n\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n v4 = (int)(round(*(double *)(8LL * i + a1)) + (double)v4);\n return (unsigned int)(a2 * v4);\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 0\nmov [rbp+var_8], 0\njmp short loc_11EB\nloc_11AC:\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_4]\nmovsd [rbp+var_28], xmm1\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmovq xmm0, rax; x\ncall _round\naddsd xmm0, [rbp+var_28]\ncvttsd2si eax, xmm0\nmov [rbp+var_4], eax\nadd [rbp+var_8], 1\nloc_11EB:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_11AC\nmov eax, [rbp+var_4]\nimul eax, [rbp+var_1C]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2)\n{\n int i; // [rsp+28h] [rbp-8h]\n int v4; // [rsp+2Ch] [rbp-4h]\n\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n v4 = (int)(round(*(double *)(8LL * i + a1)) + (double)v4);\n return (unsigned int)(a2 * v4);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2) {\n int i;\n int v4;\n v4 = 0;\n for (i = 0; i < a2; ++i)\n v4 = (int)(round(*(double *)(8LL * i + a1)) + (double)v4);\n return (unsigned int)(a2 * v4);\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int i;\n int v4;\n v4 = 0;\n for (i = 0; i < a2; ++i)\n v4 = (int)(round(*(double *)(8LL * i + a1)) + (double)v4);\n return (unsigned int)(a2 * v4);\n}" + }, + { + "index": 419, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(double list1[], int length) {\n int i;\n int sum = 0;\n for (i = 0; i < length; i++) {\n sum += round(list1[i]);\n }\n return sum * length;\n}", + "test": "int main() {\n\n double list1[] = {22.4, 4.0, -16.22, -9.10, 11.00, -12.22, 14.20, -5.20, 17.50};\n\n double list2[] = {5, 2, 9, 24.3, 29};\n\n double list3[] = {25.0, 56.7, 89.2};\n\n \n\n assert(func0(list1, sizeof(list1) / sizeof(list1[0])) == 243);\n\n assert(func0(list2, sizeof(list2) / sizeof(list2[0])) == 345);\n\n assert(func0(list3, sizeof(list3) / sizeof(list3[0])) == 513);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %esi,%r13d\ntest %esi,%esi\njle 11e6 \nmov %rdi,%rbp\nlea -0x1(%rsi),%eax\nlea 0x8(%rdi,%rax,8),%r12\nmov $0x0,%ebx\nmovsd 0x0(%rbp),%xmm0\ncallq 1070 \nmovapd %xmm0,%xmm1\npxor %xmm0,%xmm0\ncvtsi2sd %ebx,%xmm0\naddsd %xmm1,%xmm0\ncvttsd2si %xmm0,%ebx\nadd $0x8,%rbp\ncmp %r12,%rbp\njne 11ae \nmov %r13d,%eax\nimul %ebx,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nmov $0x0,%ebx\njmp 11d5 \n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r13d, esi\ntest esi, esi\njle short loc_11E4\nmov rbx, rdi\nmovsxd rax, esi\nlea r12, [rdi+rax*8]\nmov ebp, 0\nloc_11AD:\nmovsd xmm0, qword ptr [rbx]; x\ncall _round\nmovapd xmm1, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, ebp\naddsd xmm0, xmm1\ncvttsd2si ebp, xmm0\nadd rbx, 8\ncmp rbx, r12\njnz short loc_11AD\nloc_11D3:\nmov eax, r13d\nimul eax, ebp\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_11E4:\nmov ebp, 0\njmp short loc_11D3", + "ida_pseudo": "__int64 __fastcall func0(double *a1, int a2)\n{\n double *v2; // rbx\n int v3; // ebp\n\n if ( a2 <= 0 )\n {\n v3 = 0;\n }\n else\n {\n v2 = a1;\n v3 = 0;\n do\n v3 = (int)((double)v3 + round(*v2++));\n while ( v2 != &a1[a2] );\n }\n return (unsigned int)(v3 * a2);\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r13d, esi\ntest esi, esi\njle short loc_11E4\nmov rbx, rdi\nmovsxd rax, esi\nlea r12, [rdi+rax*8]\nmov ebp, 0\nloc_11AD:\nmovsd xmm0, qword ptr [rbx]; x\ncall _round\nmovapd xmm1, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, ebp\naddsd xmm0, xmm1\ncvttsd2si ebp, xmm0\nadd rbx, 8\ncmp rbx, r12\njnz short loc_11AD\nloc_11D3:\nmov eax, r13d\nimul eax, ebp\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_11E4:\nmov ebp, 0\njmp short loc_11D3", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(double *a1, int a2)\n{\n double *v2; // rbx\n int v3; // ebp\n\n if ( a2 <= 0 )\n {\n v3 = 0;\n }\n else\n {\n v2 = a1;\n v3 = 0;\n do\n v3 = (int)((double)v3 + round(*v2++));\n while ( v2 != &a1[a2] );\n }\n return (unsigned int)(v3 * a2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(double *a1, int a2) {\n double *v2;\n int v3;\n if (a2 <= 0) {\n v3 = 0;\n } else {\n v2 = a1;\n v3 = 0;\n do\n v3 = (int)((double)v3 + round(*v2++));\n while (v2 != &a1[a2]);\n }\n return (unsigned int)(v3 * a2);\n}", + "ida_pseudo_norm": "long long func0(double *a1, int a2) {\n double *v2;\n int v3;\n if (a2 <= 0) {\n v3 = 0;\n } else {\n v2 = a1;\n v3 = 0;\n do\n v3 = (int)((double)v3 + round(*v2++));\n while (v2 != &a1[a2]);\n }\n return (unsigned int)(v3 * a2);\n}" + }, + { + "index": 419, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(double list1[], int length) {\n int i;\n int sum = 0;\n for (i = 0; i < length; i++) {\n sum += round(list1[i]);\n }\n return sum * length;\n}", + "test": "int main() {\n\n double list1[] = {22.4, 4.0, -16.22, -9.10, 11.00, -12.22, 14.20, -5.20, 17.50};\n\n double list2[] = {5, 2, 9, 24.3, 29};\n\n double list3[] = {25.0, 56.7, 89.2};\n\n \n\n assert(func0(list1, sizeof(list1) / sizeof(list1[0])) == 243);\n\n assert(func0(list2, sizeof(list2) / sizeof(list2[0])) == 345);\n\n assert(func0(list3, sizeof(list3) / sizeof(list3[0])) == 513);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 13b0 \npush %r13\nlea -0x1(%rsi),%eax\nmov %esi,%r13d\npush %r12\nlea 0x8(%rdi,%rax,8),%r12\npush %rbp\nmov %rdi,%rbp\npush %rbx\nxor %ebx,%ebx\nsub $0x8,%rsp\nnopw 0x0(%rax,%rax,1)\nmovsd 0x0(%rbp),%xmm0\nadd $0x8,%rbp\ncallq 1070 \nmovapd %xmm0,%xmm1\npxor %xmm0,%xmm0\ncvtsi2sd %ebx,%xmm0\naddsd %xmm1,%xmm0\ncvttsd2si %xmm0,%ebx\ncmp %rbp,%r12\njne 1378 \nadd $0x8,%rsp\nmov %r13d,%eax\nimul %ebx,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nxor %eax,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1360\npush r13\nmovsxd rax, esi\nmov r13d, esi\npush r12\nlea r12, [rdi+rax*8]\npush rbp\nxor ebp, ebp\npush rbx\nmov rbx, rdi\nsub rsp, 8\nnop dword ptr [rax+00000000h]\nloc_1328:\nmovsd xmm0, qword ptr [rbx]; x\nadd rbx, 8\ncall _round\nmovapd xmm1, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, ebp\naddsd xmm0, xmm1\ncvttsd2si ebp, xmm0\ncmp r12, rbx\njnz short loc_1328\nadd rsp, 8\nmov eax, r13d\npop rbx\nimul eax, ebp\npop rbp\npop r12\npop r13\nretn\nloc_1360:\nxor eax, eax\nretn", + "ida_pseudo": "__int64 __fastcall func0(double *a1, int a2)\n{\n int v2; // ebp\n double *v3; // rbx\n double v4; // xmm0_8\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 0;\n v3 = a1;\n do\n {\n v4 = *v3++;\n v2 = (int)((double)v2 + round(v4));\n }\n while ( &a1[a2] != v3 );\n return (unsigned int)(v2 * a2);\n}", + "ida_strip_asm": "sub_1300:\nendbr64\ntest esi, esi\njle short loc_1360\npush r13\nmovsxd rax, esi\nmov r13d, esi\npush r12\nlea r12, [rdi+rax*8]\npush rbp\nxor ebp, ebp\npush rbx\nmov rbx, rdi\nsub rsp, 8\nnop dword ptr [rax+00000000h]\nloc_1328:\nmovsd xmm0, qword ptr [rbx]; x\nadd rbx, 8\ncall _round\nmovapd xmm1, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, ebp\naddsd xmm0, xmm1\ncvttsd2si ebp, xmm0\ncmp r12, rbx\njnz short loc_1328\nadd rsp, 8\nmov eax, r13d\npop rbx\nimul eax, ebp\npop rbp\npop r12\npop r13\nretn\nloc_1360:\nxor eax, eax\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1300(double *a1, int a2)\n{\n int v2; // ebp\n double *v3; // rbx\n double v4; // xmm0_8\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 0;\n v3 = a1;\n do\n {\n v4 = *v3++;\n v2 = (int)((double)v2 + round(v4));\n }\n while ( &a1[a2] != v3 );\n return (unsigned int)(v2 * a2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1300(double *a1, int a2) {\n int v2;\n double *v3;\n double v4;\n if (a2 <= 0) return 0LL;\n v2 = 0;\n v3 = a1;\n do {\n v4 = *v3++;\n v2 = (int)((double)v2 + round(v4));\n } while (&a1[a2] != v3);\n return (unsigned int)(v2 * a2);\n}", + "ida_pseudo_norm": "long long func0(double *a1, int a2) {\n int v2;\n double *v3;\n double v4;\n if (a2 <= 0) return 0LL;\n v2 = 0;\n v3 = a1;\n do {\n v4 = *v3++;\n v2 = (int)((double)v2 + round(v4));\n } while (&a1[a2] != v3);\n return (unsigned int)(v2 * a2);\n}" + }, + { + "index": 419, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(double list1[], int length) {\n int i;\n int sum = 0;\n for (i = 0; i < length; i++) {\n sum += round(list1[i]);\n }\n return sum * length;\n}", + "test": "int main() {\n\n double list1[] = {22.4, 4.0, -16.22, -9.10, 11.00, -12.22, 14.20, -5.20, 17.50};\n\n double list2[] = {5, 2, 9, 24.3, 29};\n\n double list3[] = {25.0, 56.7, 89.2};\n\n \n\n assert(func0(list1, sizeof(list1) / sizeof(list1[0])) == 243);\n\n assert(func0(list2, sizeof(list2) / sizeof(list2[0])) == 345);\n\n assert(func0(list3, sizeof(list3) / sizeof(list3[0])) == 513);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1360 \npush %r13\nlea -0x1(%rsi),%eax\nmov %esi,%r13d\npush %r12\nlea 0x8(%rdi,%rax,8),%r12\npush %rbp\nmov %rdi,%rbp\npush %rbx\nxor %ebx,%ebx\nsub $0x8,%rsp\nnopw 0x0(%rax,%rax,1)\nmovsd 0x0(%rbp),%xmm0\nadd $0x8,%rbp\ncallq 1070 \nmovapd %xmm0,%xmm1\npxor %xmm0,%xmm0\ncvtsi2sd %ebx,%xmm0\naddsd %xmm1,%xmm0\ncvttsd2si %xmm0,%ebx\ncmp %rbp,%r12\njne 1328 \nadd $0x8,%rsp\nmov %r13d,%eax\nimul %ebx,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nxor %eax,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1360\npush r13\nmovsxd rax, esi\nmov r13d, esi\npush r12\nlea r12, [rdi+rax*8]\npush rbp\nxor ebp, ebp\npush rbx\nmov rbx, rdi\nsub rsp, 8\nnop dword ptr [rax+00000000h]\nloc_1328:\nmovsd xmm0, qword ptr [rbx]; x\nadd rbx, 8\ncall _round\nmovapd xmm1, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, ebp\naddsd xmm0, xmm1\ncvttsd2si ebp, xmm0\ncmp r12, rbx\njnz short loc_1328\nadd rsp, 8\nmov eax, r13d\npop rbx\nimul eax, ebp\npop rbp\npop r12\npop r13\nretn\nloc_1360:\nxor eax, eax\nretn", + "ida_pseudo": "__int64 __fastcall func0(double *a1, int a2)\n{\n int v2; // ebp\n double *v3; // rbx\n double v4; // xmm0_8\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 0;\n v3 = a1;\n do\n {\n v4 = *v3++;\n v2 = (int)((double)v2 + round(v4));\n }\n while ( &a1[a2] != v3 );\n return (unsigned int)(v2 * a2);\n}", + "ida_strip_asm": "sub_1300:\nendbr64\ntest esi, esi\njle short loc_1360\npush r13\nmovsxd rax, esi\nmov r13d, esi\npush r12\nlea r12, [rdi+rax*8]\npush rbp\nxor ebp, ebp\npush rbx\nmov rbx, rdi\nsub rsp, 8\nnop dword ptr [rax+00000000h]\nloc_1328:\nmovsd xmm0, qword ptr [rbx]; x\nadd rbx, 8\ncall _round\nmovapd xmm1, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, ebp\naddsd xmm0, xmm1\ncvttsd2si ebp, xmm0\ncmp r12, rbx\njnz short loc_1328\nadd rsp, 8\nmov eax, r13d\npop rbx\nimul eax, ebp\npop rbp\npop r12\npop r13\nretn\nloc_1360:\nxor eax, eax\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1300(double *a1, int a2)\n{\n int v2; // ebp\n double *v3; // rbx\n double v4; // xmm0_8\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 0;\n v3 = a1;\n do\n {\n v4 = *v3++;\n v2 = (int)((double)v2 + round(v4));\n }\n while ( &a1[a2] != v3 );\n return (unsigned int)(v2 * a2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1300(double *a1, int a2) {\n int v2;\n double *v3;\n double v4;\n if (a2 <= 0) return 0LL;\n v2 = 0;\n v3 = a1;\n do {\n v4 = *v3++;\n v2 = (int)((double)v2 + round(v4));\n } while (&a1[a2] != v3);\n return (unsigned int)(v2 * a2);\n}", + "ida_pseudo_norm": "long long func0(double *a1, int a2) {\n int v2;\n double *v3;\n double v4;\n if (a2 <= 0) return 0LL;\n v2 = 0;\n v3 = a1;\n do {\n v4 = *v3++;\n v2 = (int)((double)v2 + round(v4));\n } while (&a1[a2] != v3);\n return (unsigned int)(v2 * a2);\n}" + }, + { + "index": 420, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int sum = 0;\n for (int i = 1; i <= n; i++) {\n sum += (2 * i) * (2 * i) * (2 * i);\n }\n return sum;\n}", + "test": "int main() {\n\n assert(func0(2) == 72);\n\n assert(func0(3) == 288);\n\n assert(func0(4) == 800);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x1,-0x4(%rbp)\njmp 1178 \nmov -0x4(%rbp),%eax\nimul %eax,%eax\nimul -0x4(%rbp),%eax\nshl $0x3,%eax\nadd %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x14(%rbp),%eax\njle 1164 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 1\njmp short loc_1178\nloc_1164:\nmov eax, [rbp+var_4]\nimul eax, eax\nimul eax, [rbp+var_4]\nshl eax, 3\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_1178:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_14]\njle short loc_1164\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v2; // [rsp+Ch] [rbp-8h]\n int i; // [rsp+10h] [rbp-4h]\n\n v2 = 0;\n for ( i = 1; i <= a1; ++i )\n v2 += 8 * i * i * i;\n return v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 1\njmp short loc_1178\nloc_1164:\nmov eax, [rbp+var_4]\nimul eax, eax\nimul eax, [rbp+var_4]\nshl eax, 3\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_1178:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_14]\njle short loc_1164\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n unsigned int v2; // [rsp+Ch] [rbp-8h]\n int i; // [rsp+10h] [rbp-4h]\n\n v2 = 0;\n for ( i = 1; i <= a1; ++i )\n v2 += 8 * i * i * i;\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n unsigned int v2;\n int i;\n v2 = 0;\n for (i = 1; i <= a1; ++i) v2 += 8 * i * i * i;\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v2;\n int i;\n v2 = 0;\n for (i = 1; i <= a1; ++i) v2 += 8 * i * i * i;\n return v2;\n}" + }, + { + "index": 420, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int sum = 0;\n for (int i = 1; i <= n; i++) {\n sum += (2 * i) * (2 * i) * (2 * i);\n }\n return sum;\n}", + "test": "int main() {\n\n assert(func0(2) == 72);\n\n assert(func0(3) == 288);\n\n assert(func0(4) == 800);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\njle 1173 \nadd $0x1,%edi\nmov $0x1,%eax\nmov $0x0,%ecx\nmov %eax,%edx\nimul %eax,%edx\nimul %eax,%edx\nlea (%rcx,%rdx,8),%ecx\nadd $0x1,%eax\ncmp %edi,%eax\njne 115e \nmov %ecx,%eax\nretq\nmov $0x0,%ecx\njmp 1170 \n", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njle short loc_1173\nadd edi, 1\nmov eax, 1\nmov ecx, 0\nloc_115E:\nmov edx, eax\nimul edx, eax\nimul edx, eax\nlea ecx, [rcx+rdx*8]\nadd eax, 1\ncmp eax, edi\njnz short loc_115E\nloc_1170:\nmov eax, ecx\nretn\nloc_1173:\nmov ecx, 0\njmp short loc_1170", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // edi\n int v2; // eax\n unsigned int v3; // ecx\n\n if ( a1 <= 0 )\n {\n return 0;\n }\n else\n {\n v1 = a1 + 1;\n v2 = 1;\n v3 = 0;\n do\n {\n v3 += 8 * v2 * v2 * v2;\n ++v2;\n }\n while ( v2 != v1 );\n }\n return v3;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ntest edi, edi\njle short loc_1173\nadd edi, 1\nmov eax, 1\nmov ecx, 0\nloc_115E:\nmov edx, eax\nimul edx, eax\nimul edx, eax\nlea ecx, [rcx+rdx*8]\nadd eax, 1\ncmp eax, edi\njnz short loc_115E\nloc_1170:\nmov eax, ecx\nretn\nloc_1173:\nmov ecx, 0\njmp short loc_1170", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v1; // edi\n int v2; // eax\n unsigned int v3; // ecx\n\n if ( a1 <= 0 )\n {\n return 0;\n }\n else\n {\n v1 = a1 + 1;\n v2 = 1;\n v3 = 0;\n do\n {\n v3 += 8 * v2 * v2 * v2;\n ++v2;\n }\n while ( v2 != v1 );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v1;\n int v2;\n unsigned int v3;\n if (a1 <= 0) {\n return 0;\n } else {\n v1 = a1 + 1;\n v2 = 1;\n v3 = 0;\n do {\n v3 += 8 * v2 * v2 * v2;\n ++v2;\n } while (v2 != v1);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v2;\n unsigned int v3;\n if (a1 <= 0) {\n return 0;\n } else {\n v1 = a1 + 1;\n v2 = 1;\n v3 = 0;\n do {\n v3 += 8 * v2 * v2 * v2;\n ++v2;\n } while (v2 != v1);\n }\n return v3;\n}" + }, + { + "index": 421, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char *func0(char *test_tup[], int size) {\n static char res[1000];\n strcpy(res, \"\");\n char delim[] = \"-\";\n for (int i = 0; i < size; i++) {\n strcat(res, test_tup[i]);\n if (i < size - 1) {\n strcat(res, delim);\n }\n }\n return res;\n}", + "test": "int main() {\n\n char *s1[] = {\"ID\", \"is\", \"4\", \"UTS\"};\n\n char *s2[] = {\"QWE\", \"is\", \"4\", \"RTY\"};\n\n char *s3[] = {\"ZEN\", \"is\", \"4\", \"OP\"};\n\n\n\n assert(strcmp(func0(s1, 4), \"ID-is-4-UTS\") == 0);\n\n assert(strcmp(func0(s2, 4), \"QWE-is-4-RTY\") == 0);\n\n assert(strcmp(func0(s3, 4), \"ZEN-is-4-OP\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovb $0x0,0x2e6e(%rip)\nmovw $0x2d,-0xa(%rbp)\nmovl $0x0,-0x10(%rbp)\njmp 1229 \nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov %rax,%rsi\nlea 0x2e3e(%rip),%rdi\ncallq 10b0 \nmov -0x1c(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x10(%rbp)\njge 1225 \nlea -0xa(%rbp),%rax\nmov %rax,%rsi\nlea 0x2e20(%rip),%rdi\ncallq 10b0 \naddl $0x1,-0x10(%rbp)\nmov -0x10(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11e1 \nlea 0x2e08(%rip),%rax\nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 124c \ncallq 1080 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov cs:res_1, 0\nmov word ptr [rbp+src], 2Dh ; '-'\nmov [rbp+var_10], 0\njmp short loc_122F\nloc_11E1:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov rsi, rax; src\nlea rax, res_1\nmov rdi, rax; dest\ncall _strcat\nmov eax, [rbp+var_1C]\nsub eax, 1\ncmp [rbp+var_10], eax\njge short loc_122B\nlea rax, [rbp+src]\nmov rsi, rax; src\nlea rax, res_1\nmov rdi, rax; dest\ncall _strcat\nloc_122B:\nadd [rbp+var_10], 1\nloc_122F:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_1C]\njl short loc_11E1\nlea rax, res_1\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1252\ncall ___stack_chk_fail\nlocret_1252:\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+10h] [rbp-10h]\n char src[2]; // [rsp+16h] [rbp-Ah] BYREF\n unsigned __int64 v5; // [rsp+18h] [rbp-8h]\n\n v5 = __readfsqword(0x28u);\n res_1 = 0;\n strcpy(src, \"-\");\n for ( i = 0; i < a2; ++i )\n {\n strcat(&res_1, *(const char **)(8LL * i + a1));\n if ( i < a2 - 1 )\n strcat(&res_1, src);\n }\n return &res_1;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov cs:dest, 0\nmov word ptr [rbp+src], 2Dh ; '-'\nmov [rbp+var_10], 0\njmp short loc_122F\nloc_11E1:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov rsi, rax; src\nlea rax, dest\nmov rdi, rax; dest\ncall _strcat\nmov eax, [rbp+var_1C]\nsub eax, 1\ncmp [rbp+var_10], eax\njge short loc_122B\nlea rax, [rbp+src]\nmov rsi, rax; src\nlea rax, dest\nmov rdi, rax; dest\ncall _strcat\nloc_122B:\nadd [rbp+var_10], 1\nloc_122F:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_1C]\njl short loc_11E1\nlea rax, dest\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1252\ncall ___stack_chk_fail\nlocret_1252:\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11A9(__int64 a1, int a2)\n{\n int i; // [rsp+10h] [rbp-10h]\n char src[2]; // [rsp+16h] [rbp-Ah] BYREF\n unsigned __int64 v5; // [rsp+18h] [rbp-8h]\n\n v5 = __readfsqword(0x28u);\n dest = 0;\n strcpy(src, \"-\");\n for ( i = 0; i < a2; ++i )\n {\n strcat(&dest, *(const char **)(8LL * i + a1));\n if ( i < a2 - 1 )\n strcat(&dest, src);\n }\n return &dest;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11A9(long long a1, int a2) {\n int i;\n char src[2];\n unsigned long long v5;\n v5 = __readfsqword(40u);\n dest = 0;\n strcpy(src, \"-\");\n for (i = 0; i < a2; ++i) {\n strcat(&dest, *(const char **)(8LL * i + a1));\n if (i < a2 - 1) strcat(&dest, src);\n }\n return &dest;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2) {\n int i;\n char src[2];\n unsigned long long v5;\n v5 = __readfsqword(40u);\n res_1 = 0;\n strcpy(src, \"-\");\n for (i = 0; i < a2; ++i) {\n strcat(&res_1, *(const char **)(8LL * i + a1));\n if (i < a2 - 1) strcat(&res_1, src);\n }\n return &res_1;\n}" + }, + { + "index": 421, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char *func0(char *test_tup[], int size) {\n static char res[1000];\n strcpy(res, \"\");\n char delim[] = \"-\";\n for (int i = 0; i < size; i++) {\n strcat(res, test_tup[i]);\n if (i < size - 1) {\n strcat(res, delim);\n }\n }\n return res;\n}", + "test": "int main() {\n\n char *s1[] = {\"ID\", \"is\", \"4\", \"UTS\"};\n\n char *s2[] = {\"QWE\", \"is\", \"4\", \"RTY\"};\n\n char *s3[] = {\"ZEN\", \"is\", \"4\", \"OP\"};\n\n\n\n assert(strcmp(func0(s1, 4), \"ID-is-4-UTS\") == 0);\n\n assert(strcmp(func0(s2, 4), \"QWE-is-4-RTY\") == 0);\n\n assert(strcmp(func0(s3, 4), \"ZEN-is-4-OP\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x8(%rsp)\nxor %eax,%eax\nmovb $0x0,0x2e92(%rip)\nmovw $0x2d,0x6(%rsp)\ntest %esi,%esi\njle 1207 \nmov %rdi,%r12\nlea -0x1(%rsi),%r13d\nmov $0x0,%ebx\nlea -0x1(%rsi),%ebp\njmp 11ec \nlea 0x6(%rsp),%rsi\nmov $0x3e8,%edx\nlea 0x2e65(%rip),%rdi\ncallq 1070 <__strcat_chk@plt>\nlea 0x1(%rbx),%rax\ncmp %r13,%rbx\nje 1207 \nmov %rax,%rbx\nmov (%r12,%rbx,8),%rsi\nmov $0x3e8,%edx\nlea 0x2e44(%rip),%rdi\ncallq 1070 <__strcat_chk@plt>\ncmp %ebx,%ebp\njle 11e0 \njmp 11ca \nmov 0x8(%rsp),%rax\nxor %fs:0x28,%rax\njne 1229 \nlea 0x2e22(%rip),%rax\nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\ncallq 1080 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 10h\nmov rax, fs:28h\nmov [rsp+38h+var_30], rax\nxor eax, eax\nmov cs:res_1, 0\nmov [rsp+38h+var_32], 2Dh ; '-'\ntest esi, esi\njle short loc_1227\nmov r13, rdi\nmov ebp, esi\nmovsxd r14, esi\nmov ebx, 0\nlea r12, res_1\njmp short loc_11FA\nloc_11F1:\nadd rbx, 1\ncmp rbx, r14\njz short loc_1227\nloc_11FA:\nmov rsi, [r13+rbx*8+0]\nmov edx, 3E8h\nmov rdi, r12\ncall ___strcat_chk\nlea eax, [rbp-1]\ncmp eax, ebx\njle short loc_11F1\nlea rsi, [rsp+38h+var_32]\nmov edx, 3E8h\nmov rdi, r12\ncall ___strcat_chk\njmp short loc_11F1\nloc_1227:\nmov rax, [rsp+38h+var_30]\nsub rax, fs:28h\njnz short loc_124B\nlea rax, res_1\nadd rsp, 10h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_124B:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2)\n{\n __int64 i; // rbx\n __int16 v4; // [rsp+6h] [rbp-32h] BYREF\n unsigned __int64 v5; // [rsp+8h] [rbp-30h]\n\n v5 = __readfsqword(0x28u);\n res_1 = 0;\n v4 = 45;\n if ( a2 > 0 )\n {\n for ( i = 0LL; i != a2; ++i )\n {\n __strcat_chk(&res_1, *(_QWORD *)(a1 + 8 * i), 1000LL);\n if ( a2 - 1 > (int)i )\n __strcat_chk(&res_1, &v4, 1000LL);\n }\n }\n return &res_1;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 10h\nmov rax, fs:28h\nmov [rsp+38h+var_30], rax\nxor eax, eax\nmov cs:byte_4040, 0\nmov [rsp+38h+var_32], 2Dh ; '-'\ntest esi, esi\njle short loc_1227\nmov r13, rdi\nmov ebp, esi\nmovsxd r14, esi\nmov ebx, 0\nlea r12, byte_4040\njmp short loc_11FA\nloc_11F1:\nadd rbx, 1\ncmp rbx, r14\njz short loc_1227\nloc_11FA:\nmov rsi, [r13+rbx*8+0]\nmov edx, 3E8h\nmov rdi, r12\ncall ___strcat_chk\nlea eax, [rbp-1]\ncmp eax, ebx\njle short loc_11F1\nlea rsi, [rsp+38h+var_32]\nmov edx, 3E8h\nmov rdi, r12\ncall ___strcat_chk\njmp short loc_11F1\nloc_1227:\nmov rax, [rsp+38h+var_30]\nsub rax, fs:28h\njnz short loc_124B\nlea rax, byte_4040\nadd rsp, 10h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_124B:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_11A9(__int64 a1, int a2)\n{\n __int64 i; // rbx\n __int16 v4; // [rsp+6h] [rbp-32h] BYREF\n unsigned __int64 v5; // [rsp+8h] [rbp-30h]\n\n v5 = __readfsqword(0x28u);\n byte_4040 = 0;\n v4 = 45;\n if ( a2 > 0 )\n {\n for ( i = 0LL; i != a2; ++i )\n {\n __strcat_chk(&byte_4040, *(_QWORD *)(a1 + 8 * i), 1000LL);\n if ( a2 - 1 > (int)i )\n __strcat_chk(&byte_4040, &v4, 1000LL);\n }\n }\n return &byte_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11A9(long long a1, int a2) {\n long long i;\n short v4;\n unsigned long long v5;\n v5 = __readfsqword(40u);\n byte_4040 = 0;\n v4 = 45;\n if (a2 > 0) {\n for (i = 0LL; i != a2; ++i) {\n __strcat_chk(&byte_4040, *(uint64_t *)(a1 + 8 * i), 1000LL);\n if (a2 - 1 > (int)i) __strcat_chk(&byte_4040, &v4, 1000LL);\n }\n }\n return &byte_4040;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2) {\n long long i;\n short v4;\n unsigned long long v5;\n v5 = __readfsqword(40u);\n res_1 = 0;\n v4 = 45;\n if (a2 > 0) {\n for (i = 0LL; i != a2; ++i) {\n __strcat_chk(&res_1, *(uint64_t *)(a1 + 8 * i), 1000LL);\n if (a2 - 1 > (int)i) __strcat_chk(&res_1, &v4, 1000LL);\n }\n }\n return &res_1;\n}" + }, + { + "index": 421, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char *func0(char *test_tup[], int size) {\n static char res[1000];\n strcpy(res, \"\");\n char delim[] = \"-\";\n for (int i = 0; i < size; i++) {\n strcat(res, test_tup[i]);\n if (i < size - 1) {\n strcat(res, delim);\n }\n }\n return res;\n}", + "test": "int main() {\n\n char *s1[] = {\"ID\", \"is\", \"4\", \"UTS\"};\n\n char *s2[] = {\"QWE\", \"is\", \"4\", \"RTY\"};\n\n char *s3[] = {\"ZEN\", \"is\", \"4\", \"OP\"};\n\n\n\n assert(strcmp(func0(s1, 4), \"ID-is-4-UTS\") == 0);\n\n assert(strcmp(func0(s2, 4), \"QWE-is-4-RTY\") == 0);\n\n assert(strcmp(func0(s3, 4), \"ZEN-is-4-OP\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x28,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x18(%rsp)\nxor %eax,%eax\nmov $0x2d,%eax\nmovb $0x0,0x2cd2(%rip)\nmov %ax,0x16(%rsp)\nlea 0x16(%rsp),%rax\nmov %rax,0x8(%rsp)\ntest %esi,%esi\njle 141c \nlea -0x1(%rsi),%r14d\nlea 0x2cb0(%rip),%rbp\nmov %rdi,%rbx\nxor %r15d,%r15d\nmov %r14,%r12\nmov %rbp,%r13\njmp 13a3 \nxchg %ax,%ax\nmov %rax,%r15\nlea 0x2c96(%rip),%rdi\nmov (%rdi),%edx\nadd $0x4,%rdi\nlea -0x1010101(%rdx),%eax\nnot %edx\nand %edx,%eax\nand $0x80808080,%eax\nje 13aa \nmov %eax,%edx\nmov (%rbx,%r15,8),%rsi\nshr $0x10,%edx\ntest $0x8080,%eax\ncmove %edx,%eax\nlea 0x2(%rdi),%rdx\ncmove %rdx,%rdi\nmov $0x3e8,%edx\nmov %eax,%ecx\nadd %al,%cl\nsbb $0x3,%rdi\nsub %rbp,%rdi\nadd %r13,%rdi\ncallq 10b0 <__stpcpy_chk@plt>\nmov %rax,%rdi\ncmp %r15d,%r12d\njle 1413 \nlea 0x3027(%rip),%rcx\nmov 0x8(%rsp),%rsi\nmov $0x2,%edx\nsub %rax,%rcx\ncallq 10a0 <__memcpy_chk@plt>\nlea 0x1(%r15),%rax\ncmp %r15,%r14\njne 13a0 \nmov 0x18(%rsp),%rax\nxor %fs:0x28,%rax\njne 1442 \nadd $0x28,%rsp\nlea 0x2c09(%rip),%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\ncallq 1080 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov rax, fs:28h\nmov [rsp+48h+var_40], rax\nxor eax, eax\nmov eax, 2Dh ; '-'\nmov cs:res_1, 0\nmov [rsp+48h+var_42], ax\ntest esi, esi\njle loc_1440\nlea rbp, res_1\nmov r13, rdi\nlea r14d, [rsi-1]\nxor ebx, ebx\nmovsxd r12, esi\nlea r15, [rbp+3E8h]\nnop dword ptr [rax]\nloc_13D8:\nmov rdi, rbp; s\ncall _strlen\nmov rsi, [r13+rbx*8+0]\nmov edx, 3E8h\nlea rdi, [rbp+rax+0]\ncall ___stpcpy_chk\ncmp r14d, ebx\njle short loc_1411\nmov rcx, r15\nlea rsi, [rsp+48h+var_42]\nmov edx, 2\nmov rdi, rax\nsub rcx, rax\ncall ___memcpy_chk\nloc_1411:\nadd rbx, 1\ncmp r12, rbx\njnz short loc_13D8\nloc_141A:\nmov rax, [rsp+48h+var_40]\nsub rax, fs:28h\njnz short loc_1449\nadd rsp, 18h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1440:\nlea rbp, res_1\njmp short loc_141A\nloc_1449:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2)\n{\n __int64 i; // rbx\n size_t v3; // rax\n __int64 v4; // rax\n __int16 v6; // [rsp+6h] [rbp-42h] BYREF\n unsigned __int64 v7; // [rsp+8h] [rbp-40h]\n\n v7 = __readfsqword(0x28u);\n res_1[0] = 0;\n v6 = 45;\n if ( a2 > 0 )\n {\n for ( i = 0LL; i != a2; ++i )\n {\n v3 = strlen(res_1);\n v4 = __stpcpy_chk(&res_1[v3], *(_QWORD *)(a1 + 8 * i), 1000LL);\n if ( a2 - 1 > (int)i )\n __memcpy_chk(v4, &v6, 2LL, &res_1[-v4 + 1000]);\n }\n }\n return res_1;\n}", + "ida_strip_asm": "sub_1380:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov rax, fs:28h\nmov [rsp+48h+var_40], rax\nxor eax, eax\nmov eax, 2Dh ; '-'\nmov cs:s, 0\nmov [rsp+48h+var_42], ax\ntest esi, esi\njle loc_1440\nlea rbp, s\nmov r13, rdi\nlea r14d, [rsi-1]\nxor ebx, ebx\nmovsxd r12, esi\nlea r15, [rbp+3E8h]\nnop dword ptr [rax]\nloc_13D8:\nmov rdi, rbp; s\ncall _strlen\nmov rsi, [r13+rbx*8+0]\nmov edx, 3E8h\nlea rdi, [rbp+rax+0]\ncall ___stpcpy_chk\ncmp r14d, ebx\njle short loc_1411\nmov rcx, r15\nlea rsi, [rsp+48h+var_42]\nmov edx, 2\nmov rdi, rax\nsub rcx, rax\ncall ___memcpy_chk\nloc_1411:\nadd rbx, 1\ncmp r12, rbx\njnz short loc_13D8\nloc_141A:\nmov rax, [rsp+48h+var_40]\nsub rax, fs:28h\njnz short loc_1449\nadd rsp, 18h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1440:\nlea rbp, s\njmp short loc_141A\nloc_1449:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_1380(__int64 a1, int a2)\n{\n __int64 i; // rbx\n size_t v3; // rax\n __int64 v4; // rax\n __int16 v6; // [rsp+6h] [rbp-42h] BYREF\n unsigned __int64 v7; // [rsp+8h] [rbp-40h]\n\n v7 = __readfsqword(0x28u);\n s[0] = 0;\n v6 = 45;\n if ( a2 > 0 )\n {\n for ( i = 0LL; i != a2; ++i )\n {\n v3 = strlen(s);\n v4 = __stpcpy_chk(&s[v3], *(_QWORD *)(a1 + 8 * i), 1000LL);\n if ( a2 - 1 > (int)i )\n __memcpy_chk(v4, &v6, 2LL, &s[-v4 + 1000]);\n }\n }\n return s;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1380(long long a1, int a2) {\n long long i;\n unsigned int v3;\n long long v4;\n short v6;\n unsigned long long v7;\n v7 = __readfsqword(40u);\n s[0] = 0;\n v6 = 45;\n if (a2 > 0) {\n for (i = 0LL; i != a2; ++i) {\n v3 = strlen(s);\n v4 = __stpcpy_chk(&s[v3], *(uint64_t *)(a1 + 8 * i), 1000LL);\n if (a2 - 1 > (int)i) __memcpy_chk(v4, &v6, 2LL, &s[-v4 + 1000]);\n }\n }\n return s;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2) {\n long long i;\n unsigned int v3;\n long long v4;\n short v6;\n unsigned long long v7;\n v7 = __readfsqword(40u);\n res_1[0] = 0;\n v6 = 45;\n if (a2 > 0) {\n for (i = 0LL; i != a2; ++i) {\n v3 = strlen(res_1);\n v4 = __stpcpy_chk(&res_1[v3], *(uint64_t *)(a1 + 8 * i), 1000LL);\n if (a2 - 1 > (int)i) __memcpy_chk(v4, &v6, 2LL, &res_1[-v4 + 1000]);\n }\n }\n return res_1;\n}" + }, + { + "index": 421, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char *func0(char *test_tup[], int size) {\n static char res[1000];\n strcpy(res, \"\");\n char delim[] = \"-\";\n for (int i = 0; i < size; i++) {\n strcat(res, test_tup[i]);\n if (i < size - 1) {\n strcat(res, delim);\n }\n }\n return res;\n}", + "test": "int main() {\n\n char *s1[] = {\"ID\", \"is\", \"4\", \"UTS\"};\n\n char *s2[] = {\"QWE\", \"is\", \"4\", \"RTY\"};\n\n char *s3[] = {\"ZEN\", \"is\", \"4\", \"OP\"};\n\n\n\n assert(strcmp(func0(s1, 4), \"ID-is-4-UTS\") == 0);\n\n assert(strcmp(func0(s2, 4), \"QWE-is-4-RTY\") == 0);\n\n assert(strcmp(func0(s3, 4), \"ZEN-is-4-OP\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x8(%rsp)\nxor %eax,%eax\nmov $0x2d,%eax\nmovb $0x0,0x2c92(%rip)\nmov %ax,0x6(%rsp)\ntest %esi,%esi\njle 147e \nlea -0x1(%rsi),%r12d\nmov %rdi,%rbp\nmov %esi,%ebx\ntest %r12d,%r12d\njle 14a8 \nmov %rdi,%r14\nxor %r15d,%r15d\nlea 0x6(%rsp),%r13\nnopl 0x0(%rax,%rax,1)\nlea 0x2c59(%rip),%rdi\nmov (%rdi),%edx\nadd $0x4,%rdi\nlea -0x1010101(%rdx),%eax\nnot %edx\nand %edx,%eax\nand $0x80808080,%eax\nje 13e7 \nmov %eax,%edx\nshr $0x10,%edx\ntest $0x8080,%eax\ncmove %edx,%eax\nlea 0x2(%rdi),%rdx\ncmove %rdx,%rdi\nmov $0x3e8,%edx\nmov %eax,%esi\nadd %al,%sil\nmov (%r14),%rsi\nsbb $0x3,%rdi\nadd $0x1,%r15d\nadd $0x8,%r14\ncallq 10d0 <__stpcpy_chk@plt>\nlea 0x2ff0(%rip),%rcx\nmov $0x2,%edx\nmov %r13,%rsi\nmov %rax,%rdi\nsub %rax,%rcx\ncallq 10c0 <__memcpy_chk@plt>\ncmp %r12d,%r15d\njl 13e0 \ncmp %r15d,%ebx\njle 147e \nmovslq %r15d,%r15\nlea 0x2be1(%rip),%rcx\nmov 0x0(%rbp,%r15,8),%rsi\nmov %rcx,%rdi\nmov $0x3e8,%edx\nadd $0x1,%r15\ncallq 1090 <__strcat_chk@plt>\nmov %rax,%rcx\ncmp %r15d,%ebx\njg 1460 \nmov 0x8(%rsp),%rax\nxor %fs:0x28,%rax\njne 14ad \nadd $0x18,%rsp\nlea 0x2ba7(%rip),%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\nxor %r15d,%r15d\njmp 1455 \ncallq 10a0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov rax, fs:28h\nmov [rsp+58h+var_40], rax\nxor eax, eax\nmov eax, 2Dh ; '-'\nmov cs:res_1, 0\nmov [rsp+58h+var_42], ax\ntest esi, esi\njle loc_14B0\nlea r14d, [rsi-1]\nmov r13, rdi\nmov r12d, esi\nxor r15d, r15d\nlea rbx, res_1\ntest r14d, r14d\njg short loc_1448\nloc_13F4:\nmovsxd rbp, r15d\nnop word ptr [rax+rax+00000000h]\nloc_1400:\nmov rsi, [r13+rbp*8+0]\nmov edx, 3E8h\nmov rdi, rbx\nadd rbp, 1\ncall ___strcat_chk\ncmp r12d, ebp\njg short loc_1400\nloc_141B:\nmov rax, [rsp+58h+var_40]\nsub rax, fs:28h\njnz loc_14BC\nadd rsp, 28h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1448:\nlea rax, [rsp+58h+var_42]\nmov rbp, rdi\nmov [rsp+58h+var_50], rax\nloc_1455:\nmov rdi, rbx; s\nadd r15d, 1\nadd rbp, 8\ncall _strlen\nmov rsi, [rbp-8]\nmov edx, 3E8h\nlea rdi, [rbx+rax]\ncall ___stpcpy_chk\nmov rsi, [rsp+58h+var_50]\nmov edx, 2\nlea rcx, _end\nmov rdi, rax\nsub rcx, rax\ncall ___memcpy_chk\ncmp r15d, r14d\njl short loc_1455\ncmp r12d, r15d\njg loc_13F4\njmp loc_141B\nloc_14B0:\nlea rbx, res_1\njmp loc_141B\nloc_14BC:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2)\n{\n int v3; // r15d\n __int64 v4; // rbp\n __int64 v5; // rsi\n __int64 v7; // rbp\n size_t v8; // rax\n __int64 v9; // rax\n __int16 v10; // [rsp+16h] [rbp-42h] BYREF\n unsigned __int64 v11; // [rsp+18h] [rbp-40h]\n\n v11 = __readfsqword(0x28u);\n res_1[0] = 0;\n v10 = 45;\n if ( a2 > 0 )\n {\n v3 = 0;\n if ( a2 - 1 <= 0 )\n goto LABEL_3;\n v7 = a1;\n do\n {\n ++v3;\n v7 += 8LL;\n v8 = strlen(res_1);\n v9 = __stpcpy_chk(&res_1[v8], *(_QWORD *)(v7 - 8), 1000LL);\n __memcpy_chk(v9, &v10, 2LL, (char *)&end - v9);\n }\n while ( v3 < a2 - 1 );\n if ( a2 > v3 )\n {\nLABEL_3:\n v4 = v3;\n do\n {\n v5 = *(_QWORD *)(a1 + 8 * v4++);\n __strcat_chk(res_1, v5, 1000LL);\n }\n while ( a2 > (int)v4 );\n }\n }\n return res_1;\n}", + "ida_strip_asm": "sub_13A0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov rax, fs:28h\nmov [rsp+58h+var_40], rax\nxor eax, eax\nmov eax, 2Dh ; '-'\nmov cs:s, 0\nmov [rsp+58h+var_42], ax\ntest esi, esi\njle loc_14B0\nlea r14d, [rsi-1]\nmov r13, rdi\nmov r12d, esi\nxor r15d, r15d\nlea rbx, s\ntest r14d, r14d\njg short loc_1448\nloc_13F4:\nmovsxd rbp, r15d\nnop word ptr [rax+rax+00000000h]\nloc_1400:\nmov rsi, [r13+rbp*8+0]\nmov edx, 3E8h\nmov rdi, rbx\nadd rbp, 1\ncall ___strcat_chk\ncmp r12d, ebp\njg short loc_1400\nloc_141B:\nmov rax, [rsp+58h+var_40]\nsub rax, fs:28h\njnz loc_14BC\nadd rsp, 28h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1448:\nlea rax, [rsp+58h+var_42]\nmov rbp, rdi\nmov [rsp+58h+var_50], rax\nloc_1455:\nmov rdi, rbx; s\nadd r15d, 1\nadd rbp, 8\ncall _strlen\nmov rsi, [rbp-8]\nmov edx, 3E8h\nlea rdi, [rbx+rax]\ncall ___stpcpy_chk\nmov rsi, [rsp+58h+var_50]\nmov edx, 2\nlea rcx, __strcat_chk\nmov rdi, rax\nsub rcx, rax\ncall ___memcpy_chk\ncmp r15d, r14d\njl short loc_1455\ncmp r12d, r15d\njg loc_13F4\njmp loc_141B\nloc_14B0:\nlea rbx, s\njmp loc_141B\nloc_14BC:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_13A0(__int64 a1, int a2)\n{\n int v3; // r15d\n __int64 v4; // rbp\n __int64 v5; // rsi\n __int64 v7; // rbp\n size_t v8; // rax\n __int64 v9; // rax\n __int16 v10; // [rsp+16h] [rbp-42h] BYREF\n unsigned __int64 v11; // [rsp+18h] [rbp-40h]\n\n v11 = __readfsqword(0x28u);\n s[0] = 0;\n v10 = 45;\n if ( a2 > 0 )\n {\n v3 = 0;\n if ( a2 - 1 <= 0 )\n goto LABEL_3;\n v7 = a1;\n do\n {\n ++v3;\n v7 += 8LL;\n v8 = strlen(s);\n v9 = __stpcpy_chk(&s[v8], *(_QWORD *)(v7 - 8), 1000LL);\n __memcpy_chk(v9, &v10, 2LL, (char *)&_strcat_chk - v9);\n }\n while ( v3 < a2 - 1 );\n if ( a2 > v3 )\n {\nLABEL_3:\n v4 = v3;\n do\n {\n v5 = *(_QWORD *)(a1 + 8 * v4++);\n __strcat_chk(s, v5, 1000LL);\n }\n while ( a2 > (int)v4 );\n }\n }\n return s;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_13A0(long long a1, int a2) {\n int v3;\n long long v4;\n long long v5;\n long long v7;\n unsigned int v8;\n long long v9;\n short v10;\n unsigned long long v11;\n v11 = __readfsqword(40u);\n s[0] = 0;\n v10 = 45;\n if (a2 > 0) {\n v3 = 0;\n if (a2 - 1 <= 0) goto LABEL_3;\n v7 = a1;\n do {\n ++v3;\n v7 += 8LL;\n v8 = strlen(s);\n v9 = __stpcpy_chk(&s[v8], *(uint64_t *)(v7 - 8), 1000LL);\n __memcpy_chk(v9, &v10, 2LL, (char *)&_strcat_chk - v9);\n } while (v3 < a2 - 1);\n if (a2 > v3) {\n LABEL_3:\n v4 = v3;\n do {\n v5 = *(uint64_t *)(a1 + 8 * v4++);\n __strcat_chk(s, v5, 1000LL);\n } while (a2 > (int)v4);\n }\n }\n return s;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2) {\n int v3;\n long long v4;\n long long v5;\n long long v7;\n unsigned int v8;\n long long v9;\n short v10;\n unsigned long long v11;\n v11 = __readfsqword(40u);\n res_1[0] = 0;\n v10 = 45;\n if (a2 > 0) {\n v3 = 0;\n if (a2 - 1 <= 0) goto LABEL_3;\n v7 = a1;\n do {\n ++v3;\n v7 += 8LL;\n v8 = strlen(res_1);\n v9 = __stpcpy_chk(&res_1[v8], *(uint64_t *)(v7 - 8), 1000LL);\n __memcpy_chk(v9, &v10, 2LL, (char *)&end - v9);\n } while (v3 < a2 - 1);\n if (a2 > v3) {\n LABEL_3:\n v4 = v3;\n do {\n v5 = *(uint64_t *)(a1 + 8 * v4++);\n __strcat_chk(res_1, v5, 1000LL);\n } while (a2 > (int)v4);\n }\n }\n return res_1;\n}" + }, + { + "index": 422, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int n) {\n double sum = 0;\n for (int i = 1; i <= n; i++) {\n sum += i * i * i;\n }\n return round(sum / n * 1000000) / 1000000;\n}", + "test": "int main() {\n\n assert(func0(2) == 4.5);\n\n assert(func0(3) == 12);\n\n assert(func0(1) == 1);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %edi,-0x14(%rbp)\npxor %xmm0,%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmovl $0x1,-0xc(%rbp)\njmp 11aa \nmov -0xc(%rbp),%eax\nimul %eax,%eax\nimul -0xc(%rbp),%eax\ncvtsi2sd %eax,%xmm0\nmovsd -0x8(%rbp),%xmm1\naddsd %xmm1,%xmm0\nmovsd %xmm0,-0x8(%rbp)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x14(%rbp),%eax\njle 118a \ncvtsi2sdl -0x14(%rbp),%xmm1\nmovsd -0x8(%rbp),%xmm0\ndivsd %xmm1,%xmm0\nmovapd %xmm0,%xmm1\nmovsd 0xeac(%rip),%xmm0\nmulsd %xmm1,%xmm0\ncallq 1060 \nmovsd 0xe9b(%rip),%xmm1\ndivsd %xmm1,%xmm0\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\npxor xmm0, xmm0\nmovsd [rbp+var_8], xmm0\nmov [rbp+var_C], 1\njmp short loc_11AE\nloc_118A:\nmov eax, [rbp+var_C]\nimul eax, eax\nimul eax, [rbp+var_C]\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmovsd xmm1, [rbp+var_8]\naddsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nadd [rbp+var_C], 1\nloc_11AE:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_14]\njle short loc_118A\npxor xmm2, xmm2\ncvtsi2sd xmm2, [rbp+var_14]\nmovsd xmm0, [rbp+var_8]\nmovapd xmm1, xmm0\ndivsd xmm1, xmm2\nmovsd xmm0, cs:qword_2060\nmulsd xmm1, xmm0\nmovq rax, xmm1\nmovq xmm0, rax; x\ncall _round\nmovq rax, xmm0\nmovsd xmm0, cs:qword_2060\nmovq xmm1, rax\ndivsd xmm1, xmm0\nmovapd xmm0, xmm1\nleave\nretn", + "ida_pseudo": "__int128 __usercall func0@(int a1@)\n{\n double v1; // rax\n __int128 v2; // xmm1\n int i; // [rsp+14h] [rbp-Ch]\n double v5; // [rsp+18h] [rbp-8h]\n\n v5 = 0.0;\n for ( i = 1; i <= a1; ++i )\n v5 = (double)(i * i * i) + v5;\n v1 = round(v5 / (double)a1 * 1000000.0);\n v2 = *(unsigned __int64 *)&v1;\n *(double *)&v2 = v1 / 1000000.0;\n return v2;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\npxor xmm0, xmm0\nmovsd [rbp+var_8], xmm0\nmov [rbp+var_C], 1\njmp short loc_11AE\nloc_118A:\nmov eax, [rbp+var_C]\nimul eax, eax\nimul eax, [rbp+var_C]\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmovsd xmm1, [rbp+var_8]\naddsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nadd [rbp+var_C], 1\nloc_11AE:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_14]\njle short loc_118A\npxor xmm2, xmm2\ncvtsi2sd xmm2, [rbp+var_14]\nmovsd xmm0, [rbp+var_8]\nmovapd xmm1, xmm0\ndivsd xmm1, xmm2\nmovsd xmm0, cs:qword_2060\nmulsd xmm1, xmm0\nmovq rax, xmm1\nmovq xmm0, rax; x\ncall _round\nmovq rax, xmm0\nmovsd xmm0, cs:qword_2060\nmovq xmm1, rax\ndivsd xmm1, xmm0\nmovapd xmm0, xmm1\nleave\nretn", + "ida_strip_pseudo": "__int128 __usercall sub_1169@(int a1@)\n{\n double v1; // rax\n __int128 v2; // xmm1\n int i; // [rsp+14h] [rbp-Ch]\n double v5; // [rsp+18h] [rbp-8h]\n\n v5 = 0.0;\n for ( i = 1; i <= a1; ++i )\n v5 = (double)(i * i * i) + v5;\n v1 = round(v5 / (double)a1 * 1000000.0);\n v2 = *(unsigned __int64 *)&v1;\n *(double *)&v2 = v1 / 1000000.0;\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__int128 __usercall sub_1169 @(int a1 @) {\n double v1;\n __int128 v2;\n int i;\n double v5;\n v5 = 0.0;\n for (i = 1; i <= a1; ++i) v5 = (double)(i * i * i) + v5;\n v1 = round(v5 / (double)a1 * 1000000.0);\n v2 = *(unsigned long long *)&v1;\n *(double *)&v2 = v1 / 1000000.0;\n return v2;\n}", + "ida_pseudo_norm": "__int128 __usercall func0 @(int a1 @) {\n double v1;\n __int128 v2;\n int i;\n double v5;\n v5 = 0.0;\n for (i = 1; i <= a1; ++i) v5 = (double)(i * i * i) + v5;\n v1 = round(v5 / (double)a1 * 1000000.0);\n v2 = *(unsigned long long *)&v1;\n *(double *)&v2 = v1 / 1000000.0;\n return v2;\n}" + }, + { + "index": 422, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int n) {\n double sum = 0;\n for (int i = 1; i <= n; i++) {\n sum += i * i * i;\n }\n return round(sum / n * 1000000) / 1000000;\n}", + "test": "int main() {\n\n assert(func0(2) == 4.5);\n\n assert(func0(3) == 12);\n\n assert(func0(1) == 1);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x8,%rsp\ntest %edi,%edi\njle 11c2 \nlea 0x1(%rdi),%ecx\nmov $0x1,%eax\npxor %xmm0,%xmm0\nmov %eax,%edx\nimul %eax,%edx\nimul %eax,%edx\npxor %xmm1,%xmm1\ncvtsi2sd %edx,%xmm1\naddsd %xmm1,%xmm0\nadd $0x1,%eax\ncmp %ecx,%eax\njne 1181 \npxor %xmm1,%xmm1\ncvtsi2sd %edi,%xmm1\ndivsd %xmm1,%xmm0\nmulsd 0xec8(%rip),%xmm0\ncallq 1060 \ndivsd 0xebb(%rip),%xmm0\nadd $0x8,%rsp\nretq\npxor %xmm0,%xmm0\njmp 119c \n", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\ntest edi, edi\njle short loc_11C2\nlea ecx, [rdi+1]\nmov eax, 1\npxor xmm0, xmm0\nloc_1181:\nmov edx, eax\nimul edx, eax\nimul edx, eax\npxor xmm1, xmm1\ncvtsi2sd xmm1, edx\naddsd xmm0, xmm1\nadd eax, 1\ncmp eax, ecx\njnz short loc_1181\nloc_119C:\npxor xmm1, xmm1\ncvtsi2sd xmm1, edi\ndivsd xmm0, xmm1\nmulsd xmm0, cs:qword_2060; x\ncall _round\ndivsd xmm0, cs:qword_2060\nadd rsp, 8\nretn\nloc_11C2:\npxor xmm0, xmm0\njmp short loc_119C", + "ida_pseudo": "double __fastcall func0(int a1)\n{\n int v1; // eax\n double v2; // xmm0_8\n\n if ( a1 <= 0 )\n {\n v2 = 0.0;\n }\n else\n {\n v1 = 1;\n v2 = 0.0;\n do\n {\n v2 = v2 + (double)(v1 * v1 * v1);\n ++v1;\n }\n while ( v1 != a1 + 1 );\n }\n return round(v2 / (double)a1 * 1000000.0) / 1000000.0;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nsub rsp, 8\ntest edi, edi\njle short loc_11C2\nlea ecx, [rdi+1]\nmov eax, 1\npxor xmm0, xmm0\nloc_1181:\nmov edx, eax\nimul edx, eax\nimul edx, eax\npxor xmm1, xmm1\ncvtsi2sd xmm1, edx\naddsd xmm0, xmm1\nadd eax, 1\ncmp eax, ecx\njnz short loc_1181\nloc_119C:\npxor xmm1, xmm1\ncvtsi2sd xmm1, edi\ndivsd xmm0, xmm1\nmulsd xmm0, cs:qword_2060; x\ncall _round\ndivsd xmm0, cs:qword_2060\nadd rsp, 8\nretn\nloc_11C2:\npxor xmm0, xmm0\njmp short loc_119C", + "ida_strip_pseudo": "double __fastcall sub_1169(int a1)\n{\n int v1; // eax\n double v2; // xmm0_8\n\n if ( a1 <= 0 )\n {\n v2 = 0.0;\n }\n else\n {\n v1 = 1;\n v2 = 0.0;\n do\n {\n v2 = v2 + (double)(v1 * v1 * v1);\n ++v1;\n }\n while ( v1 != a1 + 1 );\n }\n return round(v2 / (double)a1 * 1000000.0) / 1000000.0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1169(int a1) {\n int v1;\n double v2;\n if (a1 <= 0) {\n v2 = 0.0;\n } else {\n v1 = 1;\n v2 = 0.0;\n do {\n v2 = v2 + (double)(v1 * v1 * v1);\n ++v1;\n } while (v1 != a1 + 1);\n }\n return round(v2 / (double)a1 * 1000000.0) / 1000000.0;\n}", + "ida_pseudo_norm": "double func0(int a1) {\n int v1;\n double v2;\n if (a1 <= 0) {\n v2 = 0.0;\n } else {\n v1 = 1;\n v2 = 0.0;\n do {\n v2 = v2 + (double)(v1 * v1 * v1);\n ++v1;\n } while (v1 != a1 + 1);\n }\n return round(v2 / (double)a1 * 1000000.0) / 1000000.0;\n}" + }, + { + "index": 422, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int n) {\n double sum = 0;\n for (int i = 1; i <= n; i++) {\n sum += i * i * i;\n }\n return round(sum / n * 1000000) / 1000000;\n}", + "test": "int main() {\n\n assert(func0(2) == 4.5);\n\n assert(func0(3) == 12);\n\n assert(func0(1) == 1);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x8,%rsp\ntest %edi,%edi\njle 1288 \nlea 0x1(%rdi),%ecx\nmov $0x1,%eax\npxor %xmm0,%xmm0\nnopl 0x0(%rax,%rax,1)\nmov %eax,%edx\npxor %xmm1,%xmm1\nimul %eax,%edx\nimul %eax,%edx\nadd $0x1,%eax\ncvtsi2sd %edx,%xmm1\naddsd %xmm1,%xmm0\ncmp %ecx,%eax\njne 1240 \npxor %xmm1,%xmm1\ncvtsi2sd %edi,%xmm1\ndivsd %xmm1,%xmm0\nmulsd 0xe09(%rip),%xmm0\ncallq 1060 \ndivsd 0xdfc(%rip),%xmm0\nadd $0x8,%rsp\nretq\nnopl 0x0(%rax)\npxor %xmm0,%xmm0\njmp 125b \nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\ntest edi, edi\njle short loc_1288\nlea ecx, [rdi+1]\nmov eax, 1\npxor xmm0, xmm0\nnop dword ptr [rax+rax+00000000h]\nloc_1240:\nmov edx, eax\npxor xmm1, xmm1\nimul edx, eax\nimul edx, eax\nadd eax, 1\ncvtsi2sd xmm1, edx\naddsd xmm0, xmm1\ncmp eax, ecx\njnz short loc_1240\nloc_125B:\npxor xmm1, xmm1\ncvtsi2sd xmm1, edi\ndivsd xmm0, xmm1\nmulsd xmm0, cs:qword_2060; x\ncall _round\ndivsd xmm0, cs:qword_2060\nadd rsp, 8\nretn\nloc_1288:\npxor xmm0, xmm0\njmp short loc_125B", + "ida_pseudo": "double __fastcall func0(int a1)\n{\n int v1; // eax\n double v2; // xmm0_8\n int v3; // edx\n\n if ( a1 <= 0 )\n {\n v2 = 0.0;\n }\n else\n {\n v1 = 1;\n v2 = 0.0;\n do\n {\n v3 = v1 * v1 * v1;\n ++v1;\n v2 = v2 + (double)v3;\n }\n while ( v1 != a1 + 1 );\n }\n return round(v2 / (double)a1 * 1000000.0) / 1000000.0;\n}", + "ida_strip_asm": "sub_1220:\nendbr64\nsub rsp, 8\ntest edi, edi\njle short loc_1288\nlea ecx, [rdi+1]\nmov eax, 1\npxor xmm0, xmm0\nnop dword ptr [rax+rax+00000000h]\nloc_1240:\nmov edx, eax\npxor xmm1, xmm1\nimul edx, eax\nimul edx, eax\nadd eax, 1\ncvtsi2sd xmm1, edx\naddsd xmm0, xmm1\ncmp eax, ecx\njnz short loc_1240\nloc_125B:\npxor xmm1, xmm1\ncvtsi2sd xmm1, edi\ndivsd xmm0, xmm1\nmulsd xmm0, cs:qword_2060; x\ncall _round\ndivsd xmm0, cs:qword_2060\nadd rsp, 8\nretn\nloc_1288:\npxor xmm0, xmm0\njmp short loc_125B", + "ida_strip_pseudo": "double __fastcall sub_1220(int a1)\n{\n int v1; // eax\n double v2; // xmm0_8\n int v3; // edx\n\n if ( a1 <= 0 )\n {\n v2 = 0.0;\n }\n else\n {\n v1 = 1;\n v2 = 0.0;\n do\n {\n v3 = v1 * v1 * v1;\n ++v1;\n v2 = v2 + (double)v3;\n }\n while ( v1 != a1 + 1 );\n }\n return round(v2 / (double)a1 * 1000000.0) / 1000000.0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1220(int a1) {\n int v1;\n double v2;\n int v3;\n if (a1 <= 0) {\n v2 = 0.0;\n } else {\n v1 = 1;\n v2 = 0.0;\n do {\n v3 = v1 * v1 * v1;\n ++v1;\n v2 = v2 + (double)v3;\n } while (v1 != a1 + 1);\n }\n return round(v2 / (double)a1 * 1000000.0) / 1000000.0;\n}", + "ida_pseudo_norm": "double func0(int a1) {\n int v1;\n double v2;\n int v3;\n if (a1 <= 0) {\n v2 = 0.0;\n } else {\n v1 = 1;\n v2 = 0.0;\n do {\n v3 = v1 * v1 * v1;\n ++v1;\n v2 = v2 + (double)v3;\n } while (v1 != a1 + 1);\n }\n return round(v2 / (double)a1 * 1000000.0) / 1000000.0;\n}" + }, + { + "index": 422, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int n) {\n double sum = 0;\n for (int i = 1; i <= n; i++) {\n sum += i * i * i;\n }\n return round(sum / n * 1000000) / 1000000;\n}", + "test": "int main() {\n\n assert(func0(2) == 4.5);\n\n assert(func0(3) == 12);\n\n assert(func0(1) == 1);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x8,%rsp\ntest %edi,%edi\njle 1288 \nlea 0x1(%rdi),%ecx\nmov $0x1,%eax\npxor %xmm0,%xmm0\nnopl 0x0(%rax,%rax,1)\nmov %eax,%edx\npxor %xmm1,%xmm1\nimul %eax,%edx\nimul %eax,%edx\nadd $0x1,%eax\ncvtsi2sd %edx,%xmm1\naddsd %xmm1,%xmm0\ncmp %ecx,%eax\njne 1240 \npxor %xmm1,%xmm1\ncvtsi2sd %edi,%xmm1\ndivsd %xmm1,%xmm0\nmulsd 0xe09(%rip),%xmm0\ncallq 1060 \ndivsd 0xdfc(%rip),%xmm0\nadd $0x8,%rsp\nretq\nnopl 0x0(%rax)\npxor %xmm0,%xmm0\njmp 125b \nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\ntest edi, edi\njle short loc_1288\nlea ecx, [rdi+1]\nmov eax, 1\npxor xmm0, xmm0\nnop dword ptr [rax+rax+00000000h]\nloc_1240:\nmov edx, eax\npxor xmm1, xmm1\nimul edx, eax\nimul edx, eax\nadd eax, 1\ncvtsi2sd xmm1, edx\naddsd xmm0, xmm1\ncmp eax, ecx\njnz short loc_1240\nloc_125B:\npxor xmm1, xmm1\ncvtsi2sd xmm1, edi\ndivsd xmm0, xmm1\nmulsd xmm0, cs:qword_2060; x\ncall _round\ndivsd xmm0, cs:qword_2060\nadd rsp, 8\nretn\nloc_1288:\npxor xmm0, xmm0\njmp short loc_125B", + "ida_pseudo": "double __fastcall func0(int a1)\n{\n int v1; // eax\n double v2; // xmm0_8\n int v3; // edx\n\n if ( a1 <= 0 )\n {\n v2 = 0.0;\n }\n else\n {\n v1 = 1;\n v2 = 0.0;\n do\n {\n v3 = v1 * v1 * v1;\n ++v1;\n v2 = v2 + (double)v3;\n }\n while ( v1 != a1 + 1 );\n }\n return round(v2 / (double)a1 * 1000000.0) / 1000000.0;\n}", + "ida_strip_asm": "sub_1220:\nendbr64\nsub rsp, 8\ntest edi, edi\njle short loc_1288\nlea ecx, [rdi+1]\nmov eax, 1\npxor xmm0, xmm0\nnop dword ptr [rax+rax+00000000h]\nloc_1240:\nmov edx, eax\npxor xmm1, xmm1\nimul edx, eax\nimul edx, eax\nadd eax, 1\ncvtsi2sd xmm1, edx\naddsd xmm0, xmm1\ncmp eax, ecx\njnz short loc_1240\nloc_125B:\npxor xmm1, xmm1\ncvtsi2sd xmm1, edi\ndivsd xmm0, xmm1\nmulsd xmm0, cs:qword_2060; x\ncall _round\ndivsd xmm0, cs:qword_2060\nadd rsp, 8\nretn\nloc_1288:\npxor xmm0, xmm0\njmp short loc_125B", + "ida_strip_pseudo": "double __fastcall sub_1220(int a1)\n{\n int v1; // eax\n double v2; // xmm0_8\n int v3; // edx\n\n if ( a1 <= 0 )\n {\n v2 = 0.0;\n }\n else\n {\n v1 = 1;\n v2 = 0.0;\n do\n {\n v3 = v1 * v1 * v1;\n ++v1;\n v2 = v2 + (double)v3;\n }\n while ( v1 != a1 + 1 );\n }\n return round(v2 / (double)a1 * 1000000.0) / 1000000.0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1220(int a1) {\n int v1;\n double v2;\n int v3;\n if (a1 <= 0) {\n v2 = 0.0;\n } else {\n v1 = 1;\n v2 = 0.0;\n do {\n v3 = v1 * v1 * v1;\n ++v1;\n v2 = v2 + (double)v3;\n } while (v1 != a1 + 1);\n }\n return round(v2 / (double)a1 * 1000000.0) / 1000000.0;\n}", + "ida_pseudo_norm": "double func0(int a1) {\n int v1;\n double v2;\n int v3;\n if (a1 <= 0) {\n v2 = 0.0;\n } else {\n v1 = 1;\n v2 = 0.0;\n do {\n v3 = v1 * v1 * v1;\n ++v1;\n v2 = v2 + (double)v3;\n } while (v1 != a1 + 1);\n }\n return round(v2 / (double)a1 * 1000000.0) / 1000000.0;\n}" + }, + { + "index": 423, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint max_three(int a, int b, int c) {\n\n int m = a > b ? a : b;\n\n return m > c ? m : c;\n\n}\n\n\n\n", + "func": "int func0(int** gold, int m, int n) {\n int** goldTable = (int**)malloc(m * sizeof(int*));\n for (int i = 0; i < m; i++) {\n goldTable[i] = (int*)calloc(n, sizeof(int));\n }\n for (int col = n - 1; col >= 0; col--) {\n for (int row = 0; row < m; row++) {\n int right = (col == n - 1) ? 0 : goldTable[row][col + 1];\n int right_up =\n (row == 0 || col == n - 1) ? 0 : goldTable[row - 1][col + 1];\n int right_down =\n (row == m - 1 || col == n - 1) ? 0 : goldTable[row + 1][col + 1];\n goldTable[row][col] =\n gold[row][col] + max_three(right, right_up, right_down);\n }\n }\n int res = goldTable[0][0];\n for (int i = 1; i < m; i++) {\n if (goldTable[i][0] > res) res = goldTable[i][0];\n }\n for (int i = 0; i < m; i++) free(goldTable[i]);\n free(goldTable);\n return res;\n}", + "test": "int main() {\n\n // Test case 1\n\n int gold1_data[4][4] = {\n\n {1, 3, 1, 5},\n\n {2, 2, 4, 1},\n\n {5, 0, 2, 3},\n\n {0, 6, 1, 2}\n\n };\n\n int* gold1[4];\n\n for(int i=0; i <4; i++)\n\n gold1[i] = gold1_data[i];\n\n assert(func0(gold1, 4, 4) == 16);\n\n\n\n // Test case 2\n\n int gold2_data[2][2] = {\n\n {10, 20},\n\n {30, 40}\n\n };\n\n int* gold2[2];\n\n for(int i=0; i <2; i++)\n\n gold2[i] = gold2_data[i];\n\n assert(func0(gold2, 2, 2) == 70);\n\n\n\n // Test case 3\n\n int gold3_data[2][2] = {\n\n {4, 9},\n\n {3, 7}\n\n };\n\n int* gold3[2];\n\n for(int i=0; i <2; i++)\n\n gold3[i] = gold3_data[i];\n\n assert(func0(gold3, 2, 2) == 13);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x48,%rsp\nmov %rdi,-0x48(%rbp)\nmov %esi,-0x4c(%rbp)\nmov %edx,-0x50(%rbp)\nmov -0x4c(%rbp),%eax\ncltq\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,-0x18(%rbp)\nmovl $0x0,-0x3c(%rbp)\njmp 1257 \nmov -0x50(%rbp),%eax\ncltq\nmov -0x3c(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x18(%rbp),%rdx\nlea (%rcx,%rdx,1),%rbx\nmov $0x4,%esi\nmov %rax,%rdi\ncallq 10c0 \nmov %rax,(%rbx)\naddl $0x1,-0x3c(%rbp)\nmov -0x3c(%rbp),%eax\ncmp -0x4c(%rbp),%eax\njl 1228 \nmov -0x50(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0x38(%rbp)\njmpq 13c0 \nmovl $0x0,-0x34(%rbp)\njmpq 13b0 \nmov -0x50(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x38(%rbp)\nje 12b0 \nmov -0x34(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0x38(%rbp),%edx\nmovslq %edx,%rdx\nadd $0x1,%rdx\nshl $0x2,%rdx\nadd %rdx,%rax\nmov (%rax),%eax\njmp 12b5 \nmov $0x0,%eax\nmov %eax,-0x24(%rbp)\ncmpl $0x0,-0x34(%rbp)\nje 12f5 \nmov -0x50(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x38(%rbp)\nje 12f5 \nmov -0x34(%rbp),%eax\ncltq\nshl $0x3,%rax\nlea -0x8(%rax),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0x38(%rbp),%edx\nmovslq %edx,%rdx\nadd $0x1,%rdx\nshl $0x2,%rdx\nadd %rdx,%rax\nmov (%rax),%eax\njmp 12fa \nmov $0x0,%eax\nmov %eax,-0x20(%rbp)\nmov -0x4c(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x34(%rbp)\nje 1343 \nmov -0x50(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x38(%rbp)\nje 1343 \nmov -0x34(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0x38(%rbp),%edx\nmovslq %edx,%rdx\nadd $0x1,%rdx\nshl $0x2,%rdx\nadd %rdx,%rax\nmov (%rax),%eax\njmp 1348 \nmov $0x0,%eax\nmov %eax,-0x1c(%rbp)\nmov -0x34(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0x38(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x2,%rdx\nadd %rdx,%rax\nmov (%rax),%ebx\nmov -0x1c(%rbp),%edx\nmov -0x20(%rbp),%ecx\nmov -0x24(%rbp),%eax\nmov %ecx,%esi\nmov %eax,%edi\ncallq 11c9 \nmov -0x34(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rdx),%rdx\nmov -0x38(%rbp),%ecx\nmovslq %ecx,%rcx\nshl $0x2,%rcx\nadd %rcx,%rdx\nadd %ebx,%eax\nmov %eax,(%rdx)\naddl $0x1,-0x34(%rbp)\nmov -0x34(%rbp),%eax\ncmp -0x4c(%rbp),%eax\njl 1279 \nsubl $0x1,-0x38(%rbp)\ncmpl $0x0,-0x38(%rbp)\njns 126d \nmov -0x18(%rbp),%rax\nmov (%rax),%rax\nmov (%rax),%eax\nmov %eax,-0x30(%rbp)\nmovl $0x1,-0x2c(%rbp)\njmp 141d \nmov -0x2c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov (%rax),%eax\ncmp %eax,-0x30(%rbp)\njge 1419 \nmov -0x2c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov (%rax),%eax\nmov %eax,-0x30(%rbp)\naddl $0x1,-0x2c(%rbp)\nmov -0x2c(%rbp),%eax\ncmp -0x4c(%rbp),%eax\njl 13df \nmovl $0x0,-0x28(%rbp)\njmp 1451 \nmov -0x28(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov %rax,%rdi\ncallq 1090 \naddl $0x1,-0x28(%rbp)\nmov -0x28(%rbp),%eax\ncmp -0x4c(%rbp),%eax\njl 142e \nmov -0x18(%rbp),%rax\nmov %rax,%rdi\ncallq 1090 \nmov -0x30(%rbp),%eax\nadd $0x48,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 48h\nmov [rbp+var_48], rdi\nmov [rbp+var_4C], esi\nmov [rbp+var_50], edx\nmov eax, [rbp+var_4C]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov [rbp+var_3C], 0\njmp short loc_1259\nloc_122A:\nmov eax, [rbp+var_50]\ncdqe\nmov edx, [rbp+var_3C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+ptr]\nlea rbx, [rcx+rdx]\nmov esi, 4; size\nmov rdi, rax; nmemb\ncall _calloc\nmov [rbx], rax\nadd [rbp+var_3C], 1\nloc_1259:\nmov eax, [rbp+var_3C]\ncmp eax, [rbp+var_4C]\njl short loc_122A\nmov eax, [rbp+var_50]\nsub eax, 1\nmov [rbp+var_38], eax\njmp loc_13C2\nloc_126F:\nmov [rbp+var_34], 0\njmp loc_13B2\nloc_127B:\nmov eax, [rbp+var_50]\nsub eax, 1\ncmp [rbp+var_38], eax\njz short loc_12B2\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nadd rdx, 1\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\njmp short loc_12B7\nloc_12B2:\nmov eax, 0\nloc_12B7:\nmov [rbp+var_24], eax\ncmp [rbp+var_34], 0\njz short loc_12F7\nmov eax, [rbp+var_50]\nsub eax, 1\ncmp [rbp+var_38], eax\njz short loc_12F7\nmov eax, [rbp+var_34]\ncdqe\nshl rax, 3\nlea rdx, [rax-8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nadd rdx, 1\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\njmp short loc_12FC\nloc_12F7:\nmov eax, 0\nloc_12FC:\nmov [rbp+var_20], eax\nmov eax, [rbp+var_4C]\nsub eax, 1\ncmp [rbp+var_34], eax\njz short loc_1345\nmov eax, [rbp+var_50]\nsub eax, 1\ncmp [rbp+var_38], eax\njz short loc_1345\nmov eax, [rbp+var_34]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nadd rdx, 1\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\njmp short loc_134A\nloc_1345:\nmov eax, 0\nloc_134A:\nmov [rbp+var_1C], eax\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov ebx, [rax]\nmov edx, [rbp+var_1C]\nmov ecx, [rbp+var_20]\nmov eax, [rbp+var_24]\nmov esi, ecx\nmov edi, eax\ncall max_three\nmov edx, [rbp+var_34]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+ptr]\nadd rdx, rcx\nmov rdx, [rdx]\nmov ecx, [rbp+var_38]\nmovsxd rcx, ecx\nshl rcx, 2\nadd rdx, rcx\nadd eax, ebx\nmov [rdx], eax\nadd [rbp+var_34], 1\nloc_13B2:\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_4C]\njl loc_127B\nsub [rbp+var_38], 1\nloc_13C2:\ncmp [rbp+var_38], 0\njns loc_126F\nmov rax, [rbp+ptr]\nmov rax, [rax]\nmov eax, [rax]\nmov [rbp+var_30], eax\nmov [rbp+var_2C], 1\njmp short loc_141F\nloc_13E1:\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rax, [rax]\nmov eax, [rax]\ncmp [rbp+var_30], eax\njge short loc_141B\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rax, [rax]\nmov eax, [rax]\nmov [rbp+var_30], eax\nloc_141B:\nadd [rbp+var_2C], 1\nloc_141F:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_4C]\njl short loc_13E1\nmov [rbp+var_28], 0\njmp short loc_1453\nloc_1430:\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; ptr\ncall _free\nadd [rbp+var_28], 1\nloc_1453:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_4C]\njl short loc_1430\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov eax, [rbp+var_30]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n unsigned int v3; // eax\n unsigned int v4; // eax\n unsigned int v5; // eax\n int v6; // ebx\n int i; // [rsp+14h] [rbp-3Ch]\n int j; // [rsp+18h] [rbp-38h]\n int k; // [rsp+1Ch] [rbp-34h]\n unsigned int v12; // [rsp+20h] [rbp-30h]\n int m; // [rsp+24h] [rbp-2Ch]\n int n; // [rsp+28h] [rbp-28h]\n unsigned int v15; // [rsp+2Ch] [rbp-24h]\n unsigned int v16; // [rsp+30h] [rbp-20h]\n unsigned int **ptr; // [rsp+38h] [rbp-18h]\n\n ptr = (unsigned int **)malloc(8LL * a2);\n for ( i = 0; i < a2; ++i )\n ptr[i] = (unsigned int *)calloc(a3, 4uLL);\n for ( j = a3 - 1; j >= 0; --j )\n {\n for ( k = 0; k < a2; ++k )\n {\n if ( j == a3 - 1 )\n v3 = 0;\n else\n v3 = ptr[k][j + 1];\n v15 = v3;\n if ( !k || j == a3 - 1 )\n v4 = 0;\n else\n v4 = ptr[k - 1][j + 1];\n v16 = v4;\n if ( k == a2 - 1 || j == a3 - 1 )\n v5 = 0;\n else\n v5 = ptr[k + 1][j + 1];\n v6 = *(_DWORD *)(4LL * j + *(_QWORD *)(8LL * k + a1));\n ptr[k][j] = v6 + max_three(v15, v16, v5);\n }\n }\n v12 = **ptr;\n for ( m = 1; m < a2; ++m )\n {\n if ( (int)v12 < (int)*ptr[m] )\n v12 = *ptr[m];\n }\n for ( n = 0; n < a2; ++n )\n free(ptr[n]);\n free(ptr);\n return v12;\n}", + "ida_strip_asm": "sub_11F5:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 48h\nmov [rbp+var_48], rdi\nmov [rbp+var_4C], esi\nmov [rbp+var_50], edx\nmov eax, [rbp+var_4C]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov [rbp+var_3C], 0\njmp short loc_1259\nloc_122A:\nmov eax, [rbp+var_50]\ncdqe\nmov edx, [rbp+var_3C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+ptr]\nlea rbx, [rcx+rdx]\nmov esi, 4; size\nmov rdi, rax; nmemb\ncall _calloc\nmov [rbx], rax\nadd [rbp+var_3C], 1\nloc_1259:\nmov eax, [rbp+var_3C]\ncmp eax, [rbp+var_4C]\njl short loc_122A\nmov eax, [rbp+var_50]\nsub eax, 1\nmov [rbp+var_38], eax\njmp loc_13C2\nloc_126F:\nmov [rbp+var_34], 0\njmp loc_13B2\nloc_127B:\nmov eax, [rbp+var_50]\nsub eax, 1\ncmp [rbp+var_38], eax\njz short loc_12B2\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nadd rdx, 1\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\njmp short loc_12B7\nloc_12B2:\nmov eax, 0\nloc_12B7:\nmov [rbp+var_24], eax\ncmp [rbp+var_34], 0\njz short loc_12F7\nmov eax, [rbp+var_50]\nsub eax, 1\ncmp [rbp+var_38], eax\njz short loc_12F7\nmov eax, [rbp+var_34]\ncdqe\nshl rax, 3\nlea rdx, [rax-8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nadd rdx, 1\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\njmp short loc_12FC\nloc_12F7:\nmov eax, 0\nloc_12FC:\nmov [rbp+var_20], eax\nmov eax, [rbp+var_4C]\nsub eax, 1\ncmp [rbp+var_34], eax\njz short loc_1345\nmov eax, [rbp+var_50]\nsub eax, 1\ncmp [rbp+var_38], eax\njz short loc_1345\nmov eax, [rbp+var_34]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nadd rdx, 1\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\njmp short loc_134A\nloc_1345:\nmov eax, 0\nloc_134A:\nmov [rbp+var_1C], eax\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov ebx, [rax]\nmov edx, [rbp+var_1C]\nmov ecx, [rbp+var_20]\nmov eax, [rbp+var_24]\nmov esi, ecx\nmov edi, eax\ncall sub_11C9\nmov edx, [rbp+var_34]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+ptr]\nadd rdx, rcx\nmov rdx, [rdx]\nmov ecx, [rbp+var_38]\nmovsxd rcx, ecx\nshl rcx, 2\nadd rdx, rcx\nadd eax, ebx\nmov [rdx], eax\nadd [rbp+var_34], 1\nloc_13B2:\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_4C]\njl loc_127B\nsub [rbp+var_38], 1\nloc_13C2:\ncmp [rbp+var_38], 0\njns loc_126F\nmov rax, [rbp+ptr]\nmov rax, [rax]\nmov eax, [rax]\nmov [rbp+var_30], eax\nmov [rbp+var_2C], 1\njmp short loc_141F\nloc_13E1:\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rax, [rax]\nmov eax, [rax]\ncmp [rbp+var_30], eax\njge short loc_141B\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rax, [rax]\nmov eax, [rax]\nmov [rbp+var_30], eax\nloc_141B:\nadd [rbp+var_2C], 1\nloc_141F:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_4C]\njl short loc_13E1\nmov [rbp+var_28], 0\njmp short loc_1453\nloc_1430:\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; ptr\ncall _free\nadd [rbp+var_28], 1\nloc_1453:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_4C]\njl short loc_1430\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov eax, [rbp+var_30]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11F5(__int64 a1, int a2, int a3)\n{\n unsigned int v3; // eax\n unsigned int v4; // eax\n unsigned int v5; // eax\n int v6; // ebx\n int i; // [rsp+14h] [rbp-3Ch]\n int j; // [rsp+18h] [rbp-38h]\n int k; // [rsp+1Ch] [rbp-34h]\n unsigned int v12; // [rsp+20h] [rbp-30h]\n int m; // [rsp+24h] [rbp-2Ch]\n int n; // [rsp+28h] [rbp-28h]\n unsigned int v15; // [rsp+2Ch] [rbp-24h]\n unsigned int v16; // [rsp+30h] [rbp-20h]\n unsigned int **ptr; // [rsp+38h] [rbp-18h]\n\n ptr = (unsigned int **)malloc(8LL * a2);\n for ( i = 0; i < a2; ++i )\n ptr[i] = (unsigned int *)calloc(a3, 4uLL);\n for ( j = a3 - 1; j >= 0; --j )\n {\n for ( k = 0; k < a2; ++k )\n {\n if ( j == a3 - 1 )\n v3 = 0;\n else\n v3 = ptr[k][j + 1];\n v15 = v3;\n if ( !k || j == a3 - 1 )\n v4 = 0;\n else\n v4 = ptr[k - 1][j + 1];\n v16 = v4;\n if ( k == a2 - 1 || j == a3 - 1 )\n v5 = 0;\n else\n v5 = ptr[k + 1][j + 1];\n v6 = *(_DWORD *)(4LL * j + *(_QWORD *)(8LL * k + a1));\n ptr[k][j] = v6 + sub_11C9(v15, v16, v5);\n }\n }\n v12 = **ptr;\n for ( m = 1; m < a2; ++m )\n {\n if ( (int)v12 < (int)*ptr[m] )\n v12 = *ptr[m];\n }\n for ( n = 0; n < a2; ++n )\n free(ptr[n]);\n free(ptr);\n return v12;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11F5(long long a1, int a2, int a3) {\n unsigned int v3;\n unsigned int v4;\n unsigned int v5;\n int v6;\n int i;\n int j;\n int k;\n unsigned int v12;\n int m;\n int n;\n unsigned int v15;\n unsigned int v16;\n unsigned int **ptr;\n ptr = (unsigned int **)malloc(8LL * a2);\n for (i = 0; i < a2; ++i) ptr[i] = (unsigned int *)calloc(a3, 4uLL);\n for (j = a3 - 1; j >= 0; --j) {\n for (k = 0; k < a2; ++k) {\n if (j == a3 - 1)\n v3 = 0;\n else\n v3 = ptr[k][j + 1];\n v15 = v3;\n if (!k || j == a3 - 1)\n v4 = 0;\n else\n v4 = ptr[k - 1][j + 1];\n v16 = v4;\n if (k == a2 - 1 || j == a3 - 1)\n v5 = 0;\n else\n v5 = ptr[k + 1][j + 1];\n v6 = *(uint32_t *)(4LL * j + *(uint64_t *)(8LL * k + a1));\n ptr[k][j] = v6 + sub_11C9(v15, v16, v5);\n }\n }\n v12 = **ptr;\n for (m = 1; m < a2; ++m) {\n if ((int)v12 < (int)*ptr[m]) v12 = *ptr[m];\n }\n for (n = 0; n < a2; ++n) free(ptr[n]);\n free(ptr);\n return v12;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n unsigned int v3;\n unsigned int v4;\n unsigned int v5;\n int v6;\n int i;\n int j;\n int k;\n unsigned int v12;\n int m;\n int n;\n unsigned int v15;\n unsigned int v16;\n unsigned int **ptr;\n ptr = (unsigned int **)malloc(8LL * a2);\n for (i = 0; i < a2; ++i) ptr[i] = (unsigned int *)calloc(a3, 4uLL);\n for (j = a3 - 1; j >= 0; --j) {\n for (k = 0; k < a2; ++k) {\n if (j == a3 - 1)\n v3 = 0;\n else\n v3 = ptr[k][j + 1];\n v15 = v3;\n if (!k || j == a3 - 1)\n v4 = 0;\n else\n v4 = ptr[k - 1][j + 1];\n v16 = v4;\n if (k == a2 - 1 || j == a3 - 1)\n v5 = 0;\n else\n v5 = ptr[k + 1][j + 1];\n v6 = *(uint32_t *)(4LL * j + *(uint64_t *)(8LL * k + a1));\n ptr[k][j] = v6 + max_three(v15, v16, v5);\n }\n }\n v12 = **ptr;\n for (m = 1; m < a2; ++m) {\n if ((int)v12 < (int)*ptr[m]) v12 = *ptr[m];\n }\n for (n = 0; n < a2; ++n) free(ptr[n]);\n free(ptr);\n return v12;\n}" + }, + { + "index": 423, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint max_three(int a, int b, int c) {\n\n int m = a > b ? a : b;\n\n return m > c ? m : c;\n\n}\n\n\n\n", + "func": "int func0(int** gold, int m, int n) {\n int** goldTable = (int**)malloc(m * sizeof(int*));\n for (int i = 0; i < m; i++) {\n goldTable[i] = (int*)calloc(n, sizeof(int));\n }\n for (int col = n - 1; col >= 0; col--) {\n for (int row = 0; row < m; row++) {\n int right = (col == n - 1) ? 0 : goldTable[row][col + 1];\n int right_up =\n (row == 0 || col == n - 1) ? 0 : goldTable[row - 1][col + 1];\n int right_down =\n (row == m - 1 || col == n - 1) ? 0 : goldTable[row + 1][col + 1];\n goldTable[row][col] =\n gold[row][col] + max_three(right, right_up, right_down);\n }\n }\n int res = goldTable[0][0];\n for (int i = 1; i < m; i++) {\n if (goldTable[i][0] > res) res = goldTable[i][0];\n }\n for (int i = 0; i < m; i++) free(goldTable[i]);\n free(goldTable);\n return res;\n}", + "test": "int main() {\n\n // Test case 1\n\n int gold1_data[4][4] = {\n\n {1, 3, 1, 5},\n\n {2, 2, 4, 1},\n\n {5, 0, 2, 3},\n\n {0, 6, 1, 2}\n\n };\n\n int* gold1[4];\n\n for(int i=0; i <4; i++)\n\n gold1[i] = gold1_data[i];\n\n assert(func0(gold1, 4, 4) == 16);\n\n\n\n // Test case 2\n\n int gold2_data[2][2] = {\n\n {10, 20},\n\n {30, 40}\n\n };\n\n int* gold2[2];\n\n for(int i=0; i <2; i++)\n\n gold2[i] = gold2_data[i];\n\n assert(func0(gold2, 2, 2) == 70);\n\n\n\n // Test case 3\n\n int gold3_data[2][2] = {\n\n {4, 9},\n\n {3, 7}\n\n };\n\n int* gold3[2];\n\n for(int i=0; i <2; i++)\n\n gold3[i] = gold3_data[i];\n\n assert(func0(gold3, 2, 2) == 13);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov %rdi,%rbp\nmov %esi,%r13d\nmov %edx,%r14d\nmov %edx,0xc(%rsp)\nmovslq %esi,%rdi\nshl $0x3,%rdi\ncallq 10d0 \nmov %rax,%rbx\ntest %r13d,%r13d\njle 1236 \nmov %rax,%r12\nlea -0x1(%r13),%eax\nlea 0x8(%rbx,%rax,8),%r15\nmovslq %r14d,%r14\nmov $0x4,%esi\nmov %r14,%rdi\ncallq 10c0 \nmov %rax,(%r12)\nadd $0x8,%r12\ncmp %r15,%r12\njne 121c \nmov 0xc(%rsp),%r11d\nsub $0x1,%r11d\njs 12e2 \nmovslq %r11d,%rax\nlea 0x4(,%rax,4),%rdi\nmov %r11d,%r10d\nlea -0x1(%r13),%r14d\nmov %r14d,%r12d\nmov $0x0,%r15d\nmov $0x0,%r9d\njmp 12d4 \nmov %r9d,%ecx\ncmp %edx,%r14d\nje 1278 \nmov 0x8(%rbx,%rdx,8),%rcx\nmov (%rcx,%rdi,1),%ecx\ncmp %esi,%eax\ncmovl %esi,%eax\ncmp %ecx,%eax\ncmovl %ecx,%eax\nmov 0x0(%rbp,%rdx,8),%rsi\nadd (%rsi,%r8,1),%eax\nmov (%rbx,%rdx,8),%rcx\nmov %eax,(%rcx,%r8,1)\nlea 0x1(%rdx),%rax\ncmp %r12,%rdx\nje 12c6 \nmov %rax,%rdx\ncmp %r10d,%r11d\nje 12bb \nmov (%rbx,%rdx,8),%rax\nmov (%rax,%rdi,1),%esi\nmov %edx,%eax\ntest %edx,%edx\nje 1268 \nmov -0x8(%rbx,%rdx,8),%rax\nmov (%rax,%rdi,1),%eax\njmp 1268 \nmov %r9d,%esi\nmov %r9d,%eax\nmov %r9d,%ecx\njmp 1278 \nsub $0x1,%r10d\nsub $0x4,%rdi\ncmp $0xffffffff,%r10d\nje 12e2 \nlea -0x4(%rdi),%r8\nmov %r15,%rdx\ntest %r13d,%r13d\njg 129f \njmp 12c6 \nmov (%rbx),%rax\nmov (%rax),%r12d\ncmp $0x1,%r13d\njle 1341 \nlea 0x8(%rbx),%rax\nlea -0x2(%r13),%edx\nlea 0x10(%rbx,%rdx,8),%rcx\nmov (%rax),%rdx\nmov (%rdx),%edx\ncmp %edx,%r12d\ncmovl %edx,%r12d\nadd $0x8,%rax\ncmp %rax,%rcx\njne 12fb \nmov $0x0,%ebp\nmov (%rbx,%rbp,8),%rdi\ncallq 1090 \nadd $0x1,%rbp\ncmp %ebp,%r13d\njg 1315 \nmov %rbx,%rdi\ncallq 1090 \nmov %r12d,%eax\nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\njne 1327 \nmov (%rbx),%rdi\ncallq 1090 \njmp 1327 \n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov rbp, rdi\nmov r14d, esi\nmov [rsp+58h+var_4C], edx\nmovsxd r12, esi\nlea rbx, ds:0[r12*8]\nmov [rsp+58h+var_48], rbx\nmov rdi, rbx; size\ncall _malloc\nmov rsi, rax\ntest r14d, r14d\njle loc_1367\nmov r13, rax\nlea r15, [rbx+rax]\nmovsxd rbx, [rsp+58h+var_4C]\nmov [rsp+58h+var_40], r12\nmov r12, rax\nloc_122E:\nmov esi, 4; size\nmov rdi, rbx; nmemb\ncall _calloc\nmov [r13+0], rax\nadd r13, 8\ncmp r13, r15\njnz short loc_122E\nmov rsi, r12\nmov r12, [rsp+58h+var_40]\nmov ebx, [rsp+58h+var_4C]\nsub ebx, 1\njs loc_137B\nloc_125D:\nmovsxd r8, ebx\nshl r8, 2\nlea edi, [rbx+1]\nmov r11d, ebx\nmov r10d, 0\nlea r13d, [r14-1]\njmp short loc_12E7\nloc_1276:\nmov ecx, r10d\ncmp r13d, edx\njz short loc_1287\nmov rcx, [rsi+rdx*8+8]\nmov ecx, [rcx+r15]\nloc_1287:\ncmp eax, r9d\ncmovl eax, r9d\ncmp eax, ecx\ncmovl eax, ecx\nmov rcx, [rbp+rdx*8+0]\nadd eax, [rcx+r8]\nmov rcx, [rsi+rdx*8]\nmov [rcx+r8], eax\nadd rdx, 1\ncmp r12, rdx\njz short loc_12D6\nloc_12AD:\ncmp ebx, r11d\njz short loc_12CB\nmov rax, [rsi+rdx*8]\nmov r9d, [rax+r15]\nmov eax, edx\ntest edx, edx\njz short loc_1276\nmov rax, [rsi+rdx*8-8]\nmov eax, [rax+r15]\njmp short loc_1276\nloc_12CB:\nmov r9d, r10d\nmov eax, r10d\nmov ecx, r10d\njmp short loc_1287\nloc_12D6:\nsub r11d, 1\nsub r8, 4\nsub edi, 1\ncmp r11d, 0FFFFFFFFh\njz short loc_12FA\nloc_12E7:\nmovsxd r15, edi\nshl r15, 2\nmov edx, 0\ntest r14d, r14d\njg short loc_12AD\njmp short loc_12D6\nloc_12FA:\nmov rax, [rsi]\nmov ebp, [rax]\ncmp r14d, 1\njle short loc_1360\nloc_1305:\nlea rax, [rsi+8]\nlea edx, [r14-2]\nlea rcx, [rsi+rdx*8+10h]\nloc_1312:\nmov rdx, [rax]\nmov edx, [rdx]\ncmp ebp, edx\ncmovl ebp, edx\nadd rax, 8\ncmp rax, rcx\njnz short loc_1312\nloc_1325:\nmov rbx, rsi\nmov r12, [rsp+58h+var_48]\nadd r12, rsi\nmov r13, rsi\nloc_1333:\nmov rdi, [rbx]; ptr\ncall _free\nadd rbx, 8\ncmp rbx, r12\njnz short loc_1333\nmov rsi, r13\nloc_1347:\nmov rdi, rsi; ptr\ncall _free\nmov eax, ebp\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1360:\ntest r14d, r14d\njle short loc_1347\njmp short loc_1325\nloc_1367:\nmov ebx, [rsp+58h+var_4C]\nsub ebx, 1\njns loc_125D\nmov rax, [rsi]\nmov ebp, [rax]\njmp short loc_1347\nloc_137B:\nmov rax, [rsi]\nmov ebp, [rax]\ncmp r14d, 1\njg loc_1305\njmp short loc_1325", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n __int64 v5; // r12\n size_t v6; // rbx\n void **v7; // rax\n void **v8; // rsi\n void **v9; // r13\n void **v10; // r15\n void **v11; // r12\n int v12; // ebx\n __int64 v13; // r8\n int v14; // edi\n int v15; // r11d\n int v16; // ecx\n int v17; // eax\n __int64 v18; // rdx\n int v19; // r9d\n unsigned int v20; // ebp\n void **v21; // rax\n void **v22; // rbx\n size_t v25; // [rsp+10h] [rbp-48h]\n __int64 v26; // [rsp+18h] [rbp-40h]\n\n v5 = a2;\n v6 = 8LL * a2;\n v25 = v6;\n v7 = (void **)malloc(v6);\n v8 = v7;\n if ( a2 <= 0 )\n {\n v12 = a3 - 1;\n if ( a3 - 1 < 0 )\n {\n v20 = *(_DWORD *)*v7;\n goto LABEL_27;\n }\nLABEL_5:\n v13 = 4LL * v12;\n v14 = v12 + 1;\n v15 = v12;\n do\n {\n v18 = 0LL;\n if ( a2 > 0 )\n {\n do\n {\n if ( v12 == v15 )\n {\n v19 = 0;\n v17 = 0;\n v16 = 0;\n }\n else\n {\n v19 = *((_DWORD *)v8[v18] + v14);\n v17 = v18;\n if ( (_DWORD)v18 )\n v17 = *((_DWORD *)v8[v18 - 1] + v14);\n v16 = 0;\n if ( a2 - 1 != (_DWORD)v18 )\n v16 = *((_DWORD *)v8[v18 + 1] + v14);\n }\n if ( v17 < v19 )\n v17 = v19;\n if ( v17 < v16 )\n v17 = v16;\n *(_DWORD *)((char *)v8[v18] + v13) = *(_DWORD *)(*(_QWORD *)(a1 + 8 * v18) + v13) + v17;\n ++v18;\n }\n while ( v5 != v18 );\n }\n --v15;\n v13 -= 4LL;\n --v14;\n }\n while ( v15 != -1 );\n v20 = *(_DWORD *)*v8;\n if ( a2 <= 1 )\n {\n if ( a2 <= 0 )\n goto LABEL_27;\n goto LABEL_25;\n }\n goto LABEL_21;\n }\n v9 = v7;\n v10 = &v7[v6 / 8];\n v26 = v5;\n v11 = v7;\n do\n *v9++ = calloc(a3, 4uLL);\n while ( v9 != v10 );\n v8 = v11;\n v5 = v26;\n v12 = a3 - 1;\n if ( a3 - 1 >= 0 )\n goto LABEL_5;\n v20 = *(_DWORD *)*v8;\n if ( a2 > 1 )\n {\nLABEL_21:\n v21 = v8 + 1;\n do\n {\n if ( (signed int)v20 < *(_DWORD *)*v21 )\n v20 = *(_DWORD *)*v21;\n ++v21;\n }\n while ( v21 != &v8[(unsigned int)(a2 - 2) + 2] );\n }\nLABEL_25:\n v22 = v8;\n do\n free(*v22++);\n while ( v22 != (void **)((char *)v8 + v25) );\nLABEL_27:\n free(v8);\n return v20;\n}", + "ida_strip_asm": "sub_11DA:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov rbp, rdi\nmov r14d, esi\nmov [rsp+58h+var_4C], edx\nmovsxd r12, esi\nlea rbx, ds:0[r12*8]\nmov [rsp+58h+var_48], rbx\nmov rdi, rbx; size\ncall _malloc\nmov rsi, rax\ntest r14d, r14d\njle loc_1367\nmov r13, rax\nlea r15, [rbx+rax]\nmovsxd rbx, [rsp+58h+var_4C]\nmov [rsp+58h+var_40], r12\nmov r12, rax\nloc_122E:\nmov esi, 4; size\nmov rdi, rbx; nmemb\ncall _calloc\nmov [r13+0], rax\nadd r13, 8\ncmp r13, r15\njnz short loc_122E\nmov rsi, r12\nmov r12, [rsp+58h+var_40]\nmov ebx, [rsp+58h+var_4C]\nsub ebx, 1\njs loc_137B\nloc_125D:\nmovsxd r8, ebx\nshl r8, 2\nlea edi, [rbx+1]\nmov r11d, ebx\nmov r10d, 0\nlea r13d, [r14-1]\njmp short loc_12E7\nloc_1276:\nmov ecx, r10d\ncmp r13d, edx\njz short loc_1287\nmov rcx, [rsi+rdx*8+8]\nmov ecx, [rcx+r15]\nloc_1287:\ncmp eax, r9d\ncmovl eax, r9d\ncmp eax, ecx\ncmovl eax, ecx\nmov rcx, [rbp+rdx*8+0]\nadd eax, [rcx+r8]\nmov rcx, [rsi+rdx*8]\nmov [rcx+r8], eax\nadd rdx, 1\ncmp r12, rdx\njz short loc_12D6\nloc_12AD:\ncmp ebx, r11d\njz short loc_12CB\nmov rax, [rsi+rdx*8]\nmov r9d, [rax+r15]\nmov eax, edx\ntest edx, edx\njz short loc_1276\nmov rax, [rsi+rdx*8-8]\nmov eax, [rax+r15]\njmp short loc_1276\nloc_12CB:\nmov r9d, r10d\nmov eax, r10d\nmov ecx, r10d\njmp short loc_1287\nloc_12D6:\nsub r11d, 1\nsub r8, 4\nsub edi, 1\ncmp r11d, 0FFFFFFFFh\njz short loc_12FA\nloc_12E7:\nmovsxd r15, edi\nshl r15, 2\nmov edx, 0\ntest r14d, r14d\njg short loc_12AD\njmp short loc_12D6\nloc_12FA:\nmov rax, [rsi]\nmov ebp, [rax]\ncmp r14d, 1\njle short loc_1360\nloc_1305:\nlea rax, [rsi+8]\nlea edx, [r14-2]\nlea rcx, [rsi+rdx*8+10h]\nloc_1312:\nmov rdx, [rax]\nmov edx, [rdx]\ncmp ebp, edx\ncmovl ebp, edx\nadd rax, 8\ncmp rax, rcx\njnz short loc_1312\nloc_1325:\nmov rbx, rsi\nmov r12, [rsp+58h+var_48]\nadd r12, rsi\nmov r13, rsi\nloc_1333:\nmov rdi, [rbx]; ptr\ncall _free\nadd rbx, 8\ncmp rbx, r12\njnz short loc_1333\nmov rsi, r13\nloc_1347:\nmov rdi, rsi; ptr\ncall _free\nmov eax, ebp\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1360:\ntest r14d, r14d\njle short loc_1347\njmp short loc_1325\nloc_1367:\nmov ebx, [rsp+58h+var_4C]\nsub ebx, 1\njns loc_125D\nmov rax, [rsi]\nmov ebp, [rax]\njmp short loc_1347\nloc_137B:\nmov rax, [rsi]\nmov ebp, [rax]\ncmp r14d, 1\njg loc_1305\njmp short loc_1325", + "ida_strip_pseudo": "__int64 __fastcall sub_11DA(__int64 a1, int a2, int a3)\n{\n __int64 v5; // r12\n size_t v6; // rbx\n void **v7; // rax\n void **v8; // rsi\n void **v9; // r13\n void **v10; // r15\n void **v11; // r12\n int v12; // ebx\n __int64 v13; // r8\n int v14; // edi\n int v15; // r11d\n int v16; // ecx\n int v17; // eax\n __int64 v18; // rdx\n int v19; // r9d\n unsigned int v20; // ebp\n void **v21; // rax\n void **v22; // rbx\n size_t v25; // [rsp+10h] [rbp-48h]\n __int64 v26; // [rsp+18h] [rbp-40h]\n\n v5 = a2;\n v6 = 8LL * a2;\n v25 = v6;\n v7 = (void **)malloc(v6);\n v8 = v7;\n if ( a2 <= 0 )\n {\n v12 = a3 - 1;\n if ( a3 - 1 < 0 )\n {\n v20 = *(_DWORD *)*v7;\n goto LABEL_27;\n }\nLABEL_5:\n v13 = 4LL * v12;\n v14 = v12 + 1;\n v15 = v12;\n do\n {\n v18 = 0LL;\n if ( a2 > 0 )\n {\n do\n {\n if ( v12 == v15 )\n {\n v19 = 0;\n v17 = 0;\n v16 = 0;\n }\n else\n {\n v19 = *((_DWORD *)v8[v18] + v14);\n v17 = v18;\n if ( (_DWORD)v18 )\n v17 = *((_DWORD *)v8[v18 - 1] + v14);\n v16 = 0;\n if ( a2 - 1 != (_DWORD)v18 )\n v16 = *((_DWORD *)v8[v18 + 1] + v14);\n }\n if ( v17 < v19 )\n v17 = v19;\n if ( v17 < v16 )\n v17 = v16;\n *(_DWORD *)((char *)v8[v18] + v13) = *(_DWORD *)(*(_QWORD *)(a1 + 8 * v18) + v13) + v17;\n ++v18;\n }\n while ( v5 != v18 );\n }\n --v15;\n v13 -= 4LL;\n --v14;\n }\n while ( v15 != -1 );\n v20 = *(_DWORD *)*v8;\n if ( a2 <= 1 )\n {\n if ( a2 <= 0 )\n goto LABEL_27;\n goto LABEL_25;\n }\n goto LABEL_21;\n }\n v9 = v7;\n v10 = &v7[v6 / 8];\n v26 = v5;\n v11 = v7;\n do\n *v9++ = calloc(a3, 4uLL);\n while ( v9 != v10 );\n v8 = v11;\n v5 = v26;\n v12 = a3 - 1;\n if ( a3 - 1 >= 0 )\n goto LABEL_5;\n v20 = *(_DWORD *)*v8;\n if ( a2 > 1 )\n {\nLABEL_21:\n v21 = v8 + 1;\n do\n {\n if ( (signed int)v20 < *(_DWORD *)*v21 )\n v20 = *(_DWORD *)*v21;\n ++v21;\n }\n while ( v21 != &v8[(unsigned int)(a2 - 2) + 2] );\n }\nLABEL_25:\n v22 = v8;\n do\n free(*v22++);\n while ( v22 != (void **)((char *)v8 + v25) );\nLABEL_27:\n free(v8);\n return v20;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11DA(long long a1, int a2, int a3) {\n long long v5;\n unsigned int v6;\n void **v7;\n void **v8;\n void **v9;\n void **v10;\n void **v11;\n int v12;\n long long v13;\n int v14;\n int v15;\n int v16;\n int v17;\n long long v18;\n int v19;\n unsigned int v20;\n void **v21;\n void **v22;\n unsigned int v25;\n long long v26;\n v5 = a2;\n v6 = 8LL * a2;\n v25 = v6;\n v7 = (void **)malloc(v6);\n v8 = v7;\n if (a2 <= 0) {\n v12 = a3 - 1;\n if (a3 - 1 < 0) {\n v20 = *(uint32_t *)*v7;\n goto LABEL_27;\n }\n LABEL_5:\n v13 = 4LL * v12;\n v14 = v12 + 1;\n v15 = v12;\n do {\n v18 = 0LL;\n if (a2 > 0) {\n do {\n if (v12 == v15) {\n v19 = 0;\n v17 = 0;\n v16 = 0;\n } else {\n v19 = *((uint32_t *)v8[v18] + v14);\n v17 = v18;\n if ((uint32_t)v18) v17 = *((uint32_t *)v8[v18 - 1] + v14);\n v16 = 0;\n if (a2 - 1 != (uint32_t)v18) v16 = *((uint32_t *)v8[v18 + 1] + v14);\n }\n if (v17 < v19) v17 = v19;\n if (v17 < v16) v17 = v16;\n *(uint32_t *)((char *)v8[v18] + v13) =\n *(uint32_t *)(*(uint64_t *)(a1 + 8 * v18) + v13) + v17;\n ++v18;\n } while (v5 != v18);\n }\n --v15;\n v13 -= 4LL;\n --v14;\n } while (v15 != -1);\n v20 = *(uint32_t *)*v8;\n if (a2 <= 1) {\n if (a2 <= 0) goto LABEL_27;\n goto LABEL_25;\n }\n goto LABEL_21;\n }\n v9 = v7;\n v10 = &v7[v6 / 8];\n v26 = v5;\n v11 = v7;\n do\n *v9++ = calloc(a3, 4uLL);\n while (v9 != v10);\n v8 = v11;\n v5 = v26;\n v12 = a3 - 1;\n if (a3 - 1 >= 0) goto LABEL_5;\n v20 = *(uint32_t *)*v8;\n if (a2 > 1) {\n LABEL_21:\n v21 = v8 + 1;\n do {\n if ((signed int)v20 < *(uint32_t *)*v21) v20 = *(uint32_t *)*v21;\n ++v21;\n } while (v21 != &v8[(unsigned int)(a2 - 2) + 2]);\n }\nLABEL_25:\n v22 = v8;\n do\n free(*v22++);\n while (v22 != (void **)((char *)v8 + v25));\nLABEL_27:\n free(v8);\n return v20;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n long long v5;\n unsigned int v6;\n void **v7;\n void **v8;\n void **v9;\n void **v10;\n void **v11;\n int v12;\n long long v13;\n int v14;\n int v15;\n int v16;\n int v17;\n long long v18;\n int v19;\n unsigned int v20;\n void **v21;\n void **v22;\n unsigned int v25;\n long long v26;\n v5 = a2;\n v6 = 8LL * a2;\n v25 = v6;\n v7 = (void **)malloc(v6);\n v8 = v7;\n if (a2 <= 0) {\n v12 = a3 - 1;\n if (a3 - 1 < 0) {\n v20 = *(uint32_t *)*v7;\n goto LABEL_27;\n }\n LABEL_5:\n v13 = 4LL * v12;\n v14 = v12 + 1;\n v15 = v12;\n do {\n v18 = 0LL;\n if (a2 > 0) {\n do {\n if (v12 == v15) {\n v19 = 0;\n v17 = 0;\n v16 = 0;\n } else {\n v19 = *((uint32_t *)v8[v18] + v14);\n v17 = v18;\n if ((uint32_t)v18) v17 = *((uint32_t *)v8[v18 - 1] + v14);\n v16 = 0;\n if (a2 - 1 != (uint32_t)v18) v16 = *((uint32_t *)v8[v18 + 1] + v14);\n }\n if (v17 < v19) v17 = v19;\n if (v17 < v16) v17 = v16;\n *(uint32_t *)((char *)v8[v18] + v13) =\n *(uint32_t *)(*(uint64_t *)(a1 + 8 * v18) + v13) + v17;\n ++v18;\n } while (v5 != v18);\n }\n --v15;\n v13 -= 4LL;\n --v14;\n } while (v15 != -1);\n v20 = *(uint32_t *)*v8;\n if (a2 <= 1) {\n if (a2 <= 0) goto LABEL_27;\n goto LABEL_25;\n }\n goto LABEL_21;\n }\n v9 = v7;\n v10 = &v7[v6 / 8];\n v26 = v5;\n v11 = v7;\n do\n *v9++ = calloc(a3, 4uLL);\n while (v9 != v10);\n v8 = v11;\n v5 = v26;\n v12 = a3 - 1;\n if (a3 - 1 >= 0) goto LABEL_5;\n v20 = *(uint32_t *)*v8;\n if (a2 > 1) {\n LABEL_21:\n v21 = v8 + 1;\n do {\n if ((signed int)v20 < *(uint32_t *)*v21) v20 = *(uint32_t *)*v21;\n ++v21;\n } while (v21 != &v8[(unsigned int)(a2 - 2) + 2]);\n }\nLABEL_25:\n v22 = v8;\n do\n free(*v22++);\n while (v22 != (void **)((char *)v8 + v25));\nLABEL_27:\n free(v8);\n return v20;\n}" + }, + { + "index": 423, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint max_three(int a, int b, int c) {\n\n int m = a > b ? a : b;\n\n return m > c ? m : c;\n\n}\n\n\n\n", + "func": "int func0(int** gold, int m, int n) {\n int** goldTable = (int**)malloc(m * sizeof(int*));\n for (int i = 0; i < m; i++) {\n goldTable[i] = (int*)calloc(n, sizeof(int));\n }\n for (int col = n - 1; col >= 0; col--) {\n for (int row = 0; row < m; row++) {\n int right = (col == n - 1) ? 0 : goldTable[row][col + 1];\n int right_up =\n (row == 0 || col == n - 1) ? 0 : goldTable[row - 1][col + 1];\n int right_down =\n (row == m - 1 || col == n - 1) ? 0 : goldTable[row + 1][col + 1];\n goldTable[row][col] =\n gold[row][col] + max_three(right, right_up, right_down);\n }\n }\n int res = goldTable[0][0];\n for (int i = 1; i < m; i++) {\n if (goldTable[i][0] > res) res = goldTable[i][0];\n }\n for (int i = 0; i < m; i++) free(goldTable[i]);\n free(goldTable);\n return res;\n}", + "test": "int main() {\n\n // Test case 1\n\n int gold1_data[4][4] = {\n\n {1, 3, 1, 5},\n\n {2, 2, 4, 1},\n\n {5, 0, 2, 3},\n\n {0, 6, 1, 2}\n\n };\n\n int* gold1[4];\n\n for(int i=0; i <4; i++)\n\n gold1[i] = gold1_data[i];\n\n assert(func0(gold1, 4, 4) == 16);\n\n\n\n // Test case 2\n\n int gold2_data[2][2] = {\n\n {10, 20},\n\n {30, 40}\n\n };\n\n int* gold2[2];\n\n for(int i=0; i <2; i++)\n\n gold2[i] = gold2_data[i];\n\n assert(func0(gold2, 2, 2) == 70);\n\n\n\n // Test case 3\n\n int gold3_data[2][2] = {\n\n {4, 9},\n\n {3, 7}\n\n };\n\n int* gold3[2];\n\n for(int i=0; i <2; i++)\n\n gold3[i] = gold3_data[i];\n\n assert(func0(gold3, 2, 2) == 13);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\nmov %rdi,%r12\nmovslq %esi,%rdi\npush %rbp\npush %rbx\nmov %rdi,%rbx\nshl $0x3,%rdi\nsub $0x18,%rsp\nmov %edx,0xc(%rsp)\ncallq 10d0 \nmov %rax,%rbp\ntest %ebx,%ebx\njle 144a \nmov %rax,%r15\nmovslq 0xc(%rsp),%r14\nlea -0x1(%rbx),%eax\nlea 0x8(%rbp,%rax,8),%r13\nmov $0x4,%esi\nmov %r14,%rdi\nadd $0x8,%r15\ncallq 10c0 \nmov %rax,-0x8(%r15)\ncmp %r13,%r15\njne 1430 \nmov 0xc(%rsp),%r9d\nsub $0x1,%r9d\njs 1502 \nmovslq %r9d,%rdi\nlea -0x1(%rbx),%r10d\nmov %r9d,%r8d\nshl $0x2,%rdi\nmov %r10,%r11\nnopw 0x0(%rax,%rax,1)\nlea 0x4(%rdi),%rsi\nxor %edx,%edx\ntest %ebx,%ebx\njg 14c0 \njmp 14f0 \nnopl 0x0(%rax)\nmov -0x8(%rbp,%rdx,8),%r13\ncmp %eax,0x0(%r13,%rsi,1)\ncmovge 0x0(%r13,%rsi,1),%eax\nxor %r13d,%r13d\ncmp %edx,%r11d\nje 14a2 \nmov 0x8(%rbp,%rdx,8),%r13\nmov 0x0(%r13,%rsi,1),%r13d\nmov (%r12,%rdx,8),%r14\ncmp %r13d,%eax\ncmovl %r13d,%eax\nadd (%r14,%rdi,1),%eax\nmov %eax,(%rcx,%rdi,1)\nlea 0x1(%rdx),%rax\ncmp %rdx,%r10\nje 14f0 \nmov %rax,%rdx\ncmp %r8d,%r9d\nje 14e0 \nmov 0x0(%rbp,%rdx,8),%rcx\nmov (%rcx,%rsi,1),%eax\ntest %edx,%edx\njne 1480 \ntest %eax,%eax\ncmovs %edx,%eax\njmp 1490 \nnopl 0x0(%rax,%rax,1)\nmov 0x0(%rbp,%rdx,8),%rcx\nxor %eax,%eax\nxor %r13d,%r13d\njmp 14a2 \nnopl 0x0(%rax)\nsub $0x1,%r8d\nsub $0x4,%rdi\ncmp $0xffffffff,%r8d\njne 1470 \nmov 0x0(%rbp),%rdi\nmov (%rdi),%r13d\ncmp $0x1,%ebx\njle 156d \nlea -0x2(%rbx),%edx\nlea 0x8(%rbp),%rax\nlea 0x10(%rbp,%rdx,8),%rcx\nnopw 0x0(%rax,%rax,1)\nmov (%rax),%rdx\nmov (%rdx),%edx\ncmp %edx,%r13d\ncmovl %edx,%r13d\nadd $0x8,%rax\ncmp %rcx,%rax\njne 1520 \nxor %r12d,%r12d\njmp 1545 \nnopw 0x0(%rax,%rax,1)\nmov 0x0(%rbp,%r12,8),%rdi\ncallq 1090 \nadd $0x1,%r12\ncmp %r12d,%ebx\njg 1540 \nmov %rbp,%rdi\ncallq 1090 \nadd $0x18,%rsp\nmov %r13d,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\njne 1553 \ncallq 1090 \njmp 1553 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmovsxd r14, edx\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nmovsxd rbx, esi\nlea r13, ds:0[rbx*8]\nmov rdi, r13; size\nsub rsp, 28h\nmov dword ptr [rsp+58h+var_50], ebx\nmov [rsp+58h+var_48], r13\ncall _malloc\nmov ecx, dword ptr [rsp+58h+var_50]\nlea r11d, [r14-1]\nmov rbp, rax\ntest ecx, ecx\njle loc_15A2\nmov [rsp+58h+var_3C], r11d\nadd r13, rax\nmov r15d, ecx\nmov [rsp+58h+var_50], rbx\nmov rbx, rax\nnop word ptr [rax+rax+00h]\nloc_1430:\nmov esi, 4; size\nmov rdi, r14; nmemb\nadd rbx, 8\ncall _calloc\nmov [rbx-8], rax\ncmp rbx, r13\njnz short loc_1430\nmov r11d, [rsp+58h+var_3C]\nmov rbx, [rsp+58h+var_50]\nmov ecx, r15d\ntest r11d, r11d\njs loc_15B3\nmov rsi, [rbp+0]\nloc_1464:\nmovsxd rdi, r11d\nmov r13d, r11d\nshl rdi, 2\nloc_146E:\ntest ecx, ecx\njle loc_158B\nlea r14d, [rcx-1]\nnop word ptr [rax+rax+00h]\nloc_1480:\nlea r9d, [r13+1]\nxor eax, eax\nshl r9, 2\njmp short loc_14DD\nloc_1490:\nmov r8, [rbp+rax*8+0]\nmov r15d, eax\nxor edx, edx\nmov r10d, [r8+r9]\ntest rax, rax\njz short loc_14AC\nmov rdx, [rbp+rax*8-8]\nmov edx, [rdx+r9]\nloc_14AC:\ncmp r14d, r15d\njz short loc_14F0\nmov r15, [rbp+rax*8+8]\nmov r15d, [r15+r9]\ncmp r10d, r15d\ncmovl r10d, r15d\ncmp r10d, edx\ncmovge edx, r10d\nloc_14C8:\nmov r10, [r12+rax*8]\nadd rax, 1\nadd edx, [r10+rdi]\nmov [r8+rdi], edx\ncmp rbx, rax\njz short loc_1508\nloc_14DD:\ncmp r13d, r11d\njnz short loc_1490\nmov r8, [rbp+rax*8+0]\nxor edx, edx\njmp short loc_14C8\nloc_14F0:\nxor r15d, r15d\ntest r10d, r10d\ncmovs r10d, r15d\ncmp r10d, edx\ncmovge edx, r10d\njmp short loc_14C8\nloc_1508:\nsub r13d, 1\nsub rdi, 4\ncmp r13d, 0FFFFFFFFh\njnz loc_1480\nloc_151A:\nmov r12d, [rsi]\ncmp ecx, 1\njle loc_15D0\nmov rax, [rsp+58h+var_48]\nlea r13, [rax+rbp]\nloc_152F:\nlea edx, [rcx-2]\nlea rax, [rbp+8]\nlea rcx, [rbp+rdx*8+10h]\nnop dword ptr [rax+rax+00h]\nloc_1540:\nmov rdx, [rax]\nmov edx, [rdx]\ncmp r12d, edx\ncmovl r12d, edx\nadd rax, 8\ncmp rax, rcx\njnz short loc_1540\nloc_1555:\nmov rbx, rbp\nnop dword ptr [rax+rax+00000000h]\nloc_1560:\nmov rdi, [rbx]; ptr\nadd rbx, 8\ncall _free\ncmp rbx, r13\njnz short loc_1560\nloc_1571:\nmov rdi, rbp; ptr\ncall _free\nadd rsp, 28h\nmov eax, r12d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_158B:\nsub r13d, 1\nsub rdi, 4\ncmp r13d, 0FFFFFFFFh\njnz loc_146E\njmp loc_151A\nloc_15A2:\nmov rsi, [rax]\ntest r14d, r14d\njg loc_1464\nmov r12d, [rsi]\njmp short loc_1571\nloc_15B3:\nmov rax, [rbp+0]\nmov r12d, [rax]\ncmp r15d, 1\njnz loc_152F\njmp short loc_1555\nloc_15D0:\njnz short loc_1571\nmov rax, [rsp+58h+var_48]\nlea r13, [rax+rbp]\njmp loc_1555", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n size_t v3; // r14\n __int64 v5; // rbx\n void **v6; // rax\n int v7; // ecx\n int v8; // r11d\n void **v9; // rbp\n void **v10; // r13\n void **v11; // rbx\n unsigned int *v12; // rsi\n int v13; // r13d\n __int64 v14; // rdi\n __int64 v15; // rax\n _DWORD *v16; // r8\n int v17; // edx\n int v18; // r10d\n __int64 v19; // r10\n unsigned int v20; // r12d\n unsigned int **v21; // rax\n __int64 v22; // rcx\n void **v23; // rbx\n void *v24; // rdi\n size_t v26; // [rsp+10h] [rbp-48h]\n\n v3 = a3;\n v5 = a2;\n v26 = a2;\n v6 = (void **)malloc(v26 * 8);\n v7 = a2;\n v8 = v3 - 1;\n v9 = v6;\n if ( a2 <= 0 )\n {\n v12 = (unsigned int *)*v6;\n if ( (int)v3 <= 0 )\n {\n v20 = *v12;\n goto LABEL_33;\n }\n goto LABEL_6;\n }\n v10 = &v6[a2];\n v11 = v6;\n do\n *v11++ = calloc(v3, 4uLL);\n while ( v11 != v10 );\n v8 = v3 - 1;\n v5 = a2;\n v7 = a2;\n if ( (int)v3 - 1 >= 0 )\n {\n v12 = (unsigned int *)*v9;\nLABEL_6:\n v13 = v8;\n v14 = v8;\n while ( v7 <= 0 )\n {\n --v13;\n --v14;\n if ( v13 == -1 )\n goto LABEL_25;\n }\n do\n {\n v15 = 0LL;\n do\n {\n if ( v13 == v8 )\n {\n v16 = v9[v15];\n v17 = 0;\n }\n else\n {\n v16 = v9[v15];\n v17 = 0;\n v18 = v16[v13 + 1];\n if ( v15 )\n v17 = *((_DWORD *)v9[v15 - 1] + (unsigned int)(v13 + 1));\n if ( v7 - 1 == (_DWORD)v15 )\n {\n if ( v18 < 0 )\n v18 = 0;\n if ( v18 >= v17 )\n v17 = v18;\n }\n else\n {\n if ( v18 < *((_DWORD *)v9[v15 + 1] + (unsigned int)(v13 + 1)) )\n v18 = *((_DWORD *)v9[v15 + 1] + (unsigned int)(v13 + 1));\n if ( v18 >= v17 )\n v17 = v18;\n }\n }\n v19 = *(_QWORD *)(a1 + 8 * v15++);\n v16[v14] = *(_DWORD *)(v19 + v14 * 4) + v17;\n }\n while ( v5 != v15 );\n --v13;\n --v14;\n }\n while ( v13 != -1 );\nLABEL_25:\n v20 = *v12;\n if ( v7 <= 1 )\n {\n if ( v7 != 1 )\n goto LABEL_33;\n v10 = &v9[v26];\n goto LABEL_31;\n }\n v10 = &v9[v26];\n goto LABEL_27;\n }\n v20 = *(_DWORD *)*v9;\n if ( a2 != 1 )\n {\nLABEL_27:\n v21 = (unsigned int **)(v9 + 1);\n v22 = (__int64)&v9[(unsigned int)(v7 - 2) + 2];\n do\n {\n if ( (int)v20 < (int)**v21 )\n v20 = **v21;\n ++v21;\n }\n while ( v21 != (unsigned int **)v22 );\n }\nLABEL_31:\n v23 = v9;\n do\n {\n v24 = *v23++;\n free(v24);\n }\n while ( v23 != v10 );\nLABEL_33:\n free(v9);\n return v20;\n}", + "ida_strip_asm": "sub_13D0:\nendbr64\npush r15\npush r14\nmovsxd r14, edx\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nmovsxd rbx, esi\nlea r13, ds:0[rbx*8]\nmov rdi, r13; size\nsub rsp, 28h\nmov dword ptr [rsp+58h+var_50], ebx\nmov [rsp+58h+var_48], r13\ncall _malloc\nmov ecx, dword ptr [rsp+58h+var_50]\nlea r11d, [r14-1]\nmov rbp, rax\ntest ecx, ecx\njle loc_15A2\nmov [rsp+58h+var_3C], r11d\nadd r13, rax\nmov r15d, ecx\nmov [rsp+58h+var_50], rbx\nmov rbx, rax\nnop word ptr [rax+rax+00h]\nloc_1430:\nmov esi, 4; size\nmov rdi, r14; nmemb\nadd rbx, 8\ncall _calloc\nmov [rbx-8], rax\ncmp rbx, r13\njnz short loc_1430\nmov r11d, [rsp+58h+var_3C]\nmov rbx, [rsp+58h+var_50]\nmov ecx, r15d\ntest r11d, r11d\njs loc_15B3\nmov rsi, [rbp+0]\nloc_1464:\nmovsxd rdi, r11d\nmov r13d, r11d\nshl rdi, 2\nloc_146E:\ntest ecx, ecx\njle loc_158B\nlea r14d, [rcx-1]\nnop word ptr [rax+rax+00h]\nloc_1480:\nlea r9d, [r13+1]\nxor eax, eax\nshl r9, 2\njmp short loc_14DD\nloc_1490:\nmov r8, [rbp+rax*8+0]\nmov r15d, eax\nxor edx, edx\nmov r10d, [r8+r9]\ntest rax, rax\njz short loc_14AC\nmov rdx, [rbp+rax*8-8]\nmov edx, [rdx+r9]\nloc_14AC:\ncmp r14d, r15d\njz short loc_14F0\nmov r15, [rbp+rax*8+8]\nmov r15d, [r15+r9]\ncmp r10d, r15d\ncmovl r10d, r15d\ncmp r10d, edx\ncmovge edx, r10d\nloc_14C8:\nmov r10, [r12+rax*8]\nadd rax, 1\nadd edx, [r10+rdi]\nmov [r8+rdi], edx\ncmp rbx, rax\njz short loc_1508\nloc_14DD:\ncmp r13d, r11d\njnz short loc_1490\nmov r8, [rbp+rax*8+0]\nxor edx, edx\njmp short loc_14C8\nloc_14F0:\nxor r15d, r15d\ntest r10d, r10d\ncmovs r10d, r15d\ncmp r10d, edx\ncmovge edx, r10d\njmp short loc_14C8\nloc_1508:\nsub r13d, 1\nsub rdi, 4\ncmp r13d, 0FFFFFFFFh\njnz loc_1480\nloc_151A:\nmov r12d, [rsi]\ncmp ecx, 1\njle loc_15D0\nmov rax, [rsp+58h+var_48]\nlea r13, [rax+rbp]\nloc_152F:\nlea edx, [rcx-2]\nlea rax, [rbp+8]\nlea rcx, [rbp+rdx*8+10h]\nnop dword ptr [rax+rax+00h]\nloc_1540:\nmov rdx, [rax]\nmov edx, [rdx]\ncmp r12d, edx\ncmovl r12d, edx\nadd rax, 8\ncmp rax, rcx\njnz short loc_1540\nloc_1555:\nmov rbx, rbp\nnop dword ptr [rax+rax+00000000h]\nloc_1560:\nmov rdi, [rbx]; ptr\nadd rbx, 8\ncall _free\ncmp rbx, r13\njnz short loc_1560\nloc_1571:\nmov rdi, rbp; ptr\ncall _free\nadd rsp, 28h\nmov eax, r12d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_158B:\nsub r13d, 1\nsub rdi, 4\ncmp r13d, 0FFFFFFFFh\njnz loc_146E\njmp loc_151A\nloc_15A2:\nmov rsi, [rax]\ntest r14d, r14d\njg loc_1464\nmov r12d, [rsi]\njmp short loc_1571\nloc_15B3:\nmov rax, [rbp+0]\nmov r12d, [rax]\ncmp r15d, 1\njnz loc_152F\njmp short loc_1555\nloc_15D0:\njnz short loc_1571\nmov rax, [rsp+58h+var_48]\nlea r13, [rax+rbp]\njmp loc_1555", + "ida_strip_pseudo": "__int64 __fastcall sub_13D0(__int64 a1, int a2, int a3)\n{\n size_t v3; // r14\n __int64 v5; // rbx\n void **v6; // rax\n int v7; // ecx\n int v8; // r11d\n void **v9; // rbp\n void **v10; // r13\n void **v11; // rbx\n unsigned int *v12; // rsi\n int v13; // r13d\n __int64 v14; // rdi\n __int64 v15; // rax\n _DWORD *v16; // r8\n int v17; // edx\n int v18; // r10d\n __int64 v19; // r10\n unsigned int v20; // r12d\n unsigned int **v21; // rax\n __int64 v22; // rcx\n void **v23; // rbx\n void *v24; // rdi\n size_t v26; // [rsp+10h] [rbp-48h]\n\n v3 = a3;\n v5 = a2;\n v26 = a2;\n v6 = (void **)malloc(v26 * 8);\n v7 = a2;\n v8 = v3 - 1;\n v9 = v6;\n if ( a2 <= 0 )\n {\n v12 = (unsigned int *)*v6;\n if ( (int)v3 <= 0 )\n {\n v20 = *v12;\n goto LABEL_33;\n }\n goto LABEL_6;\n }\n v10 = &v6[a2];\n v11 = v6;\n do\n *v11++ = calloc(v3, 4uLL);\n while ( v11 != v10 );\n v8 = v3 - 1;\n v5 = a2;\n v7 = a2;\n if ( (int)v3 - 1 >= 0 )\n {\n v12 = (unsigned int *)*v9;\nLABEL_6:\n v13 = v8;\n v14 = v8;\n while ( v7 <= 0 )\n {\n --v13;\n --v14;\n if ( v13 == -1 )\n goto LABEL_25;\n }\n do\n {\n v15 = 0LL;\n do\n {\n if ( v13 == v8 )\n {\n v16 = v9[v15];\n v17 = 0;\n }\n else\n {\n v16 = v9[v15];\n v17 = 0;\n v18 = v16[v13 + 1];\n if ( v15 )\n v17 = *((_DWORD *)v9[v15 - 1] + (unsigned int)(v13 + 1));\n if ( v7 - 1 == (_DWORD)v15 )\n {\n if ( v18 < 0 )\n v18 = 0;\n if ( v18 >= v17 )\n v17 = v18;\n }\n else\n {\n if ( v18 < *((_DWORD *)v9[v15 + 1] + (unsigned int)(v13 + 1)) )\n v18 = *((_DWORD *)v9[v15 + 1] + (unsigned int)(v13 + 1));\n if ( v18 >= v17 )\n v17 = v18;\n }\n }\n v19 = *(_QWORD *)(a1 + 8 * v15++);\n v16[v14] = *(_DWORD *)(v19 + v14 * 4) + v17;\n }\n while ( v5 != v15 );\n --v13;\n --v14;\n }\n while ( v13 != -1 );\nLABEL_25:\n v20 = *v12;\n if ( v7 <= 1 )\n {\n if ( v7 != 1 )\n goto LABEL_33;\n v10 = &v9[v26];\n goto LABEL_31;\n }\n v10 = &v9[v26];\n goto LABEL_27;\n }\n v20 = *(_DWORD *)*v9;\n if ( a2 != 1 )\n {\nLABEL_27:\n v21 = (unsigned int **)(v9 + 1);\n v22 = (__int64)&v9[(unsigned int)(v7 - 2) + 2];\n do\n {\n if ( (int)v20 < (int)**v21 )\n v20 = **v21;\n ++v21;\n }\n while ( v21 != (unsigned int **)v22 );\n }\nLABEL_31:\n v23 = v9;\n do\n {\n v24 = *v23++;\n free(v24);\n }\n while ( v23 != v10 );\nLABEL_33:\n free(v9);\n return v20;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_13D0(long long a1, int a2, int a3) {\n unsigned int v3;\n long long v5;\n void **v6;\n int v7;\n int v8;\n void **v9;\n void **v10;\n void **v11;\n unsigned int *v12;\n int v13;\n long long v14;\n long long v15;\n uint32_t *v16;\n int v17;\n int v18;\n long long v19;\n unsigned int v20;\n unsigned int **v21;\n long long v22;\n void **v23;\n void *v24;\n unsigned int v26;\n v3 = a3;\n v5 = a2;\n v26 = a2;\n v6 = (void **)malloc(v26 * 8);\n v7 = a2;\n v8 = v3 - 1;\n v9 = v6;\n if (a2 <= 0) {\n v12 = (unsigned int *)*v6;\n if ((int)v3 <= 0) {\n v20 = *v12;\n goto LABEL_33;\n }\n goto LABEL_6;\n }\n v10 = &v6[a2];\n v11 = v6;\n do\n *v11++ = calloc(v3, 4uLL);\n while (v11 != v10);\n v8 = v3 - 1;\n v5 = a2;\n v7 = a2;\n if ((int)v3 - 1 >= 0) {\n v12 = (unsigned int *)*v9;\n LABEL_6:\n v13 = v8;\n v14 = v8;\n while (v7 <= 0) {\n --v13;\n --v14;\n if (v13 == -1) goto LABEL_25;\n }\n do {\n v15 = 0LL;\n do {\n if (v13 == v8) {\n v16 = v9[v15];\n v17 = 0;\n } else {\n v16 = v9[v15];\n v17 = 0;\n v18 = v16[v13 + 1];\n if (v15) v17 = *((uint32_t *)v9[v15 - 1] + (unsigned int)(v13 + 1));\n if (v7 - 1 == (uint32_t)v15) {\n if (v18 < 0) v18 = 0;\n if (v18 >= v17) v17 = v18;\n } else {\n if (v18 < *((uint32_t *)v9[v15 + 1] + (unsigned int)(v13 + 1)))\n v18 = *((uint32_t *)v9[v15 + 1] + (unsigned int)(v13 + 1));\n if (v18 >= v17) v17 = v18;\n }\n }\n v19 = *(uint64_t *)(a1 + 8 * v15++);\n v16[v14] = *(uint32_t *)(v19 + v14 * 4) + v17;\n } while (v5 != v15);\n --v13;\n --v14;\n } while (v13 != -1);\n LABEL_25:\n v20 = *v12;\n if (v7 <= 1) {\n if (v7 != 1) goto LABEL_33;\n v10 = &v9[v26];\n goto LABEL_31;\n }\n v10 = &v9[v26];\n goto LABEL_27;\n }\n v20 = *(uint32_t *)*v9;\n if (a2 != 1) {\n LABEL_27:\n v21 = (unsigned int **)(v9 + 1);\n v22 = (long long)&v9[(unsigned int)(v7 - 2) + 2];\n do {\n if ((int)v20 < (int)**v21) v20 = **v21;\n ++v21;\n } while (v21 != (unsigned int **)v22);\n }\nLABEL_31:\n v23 = v9;\n do {\n v24 = *v23++;\n free(v24);\n } while (v23 != v10);\nLABEL_33:\n free(v9);\n return v20;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n unsigned int v3;\n long long v5;\n void **v6;\n int v7;\n int v8;\n void **v9;\n void **v10;\n void **v11;\n unsigned int *v12;\n int v13;\n long long v14;\n long long v15;\n uint32_t *v16;\n int v17;\n int v18;\n long long v19;\n unsigned int v20;\n unsigned int **v21;\n long long v22;\n void **v23;\n void *v24;\n unsigned int v26;\n v3 = a3;\n v5 = a2;\n v26 = a2;\n v6 = (void **)malloc(v26 * 8);\n v7 = a2;\n v8 = v3 - 1;\n v9 = v6;\n if (a2 <= 0) {\n v12 = (unsigned int *)*v6;\n if ((int)v3 <= 0) {\n v20 = *v12;\n goto LABEL_33;\n }\n goto LABEL_6;\n }\n v10 = &v6[a2];\n v11 = v6;\n do\n *v11++ = calloc(v3, 4uLL);\n while (v11 != v10);\n v8 = v3 - 1;\n v5 = a2;\n v7 = a2;\n if ((int)v3 - 1 >= 0) {\n v12 = (unsigned int *)*v9;\n LABEL_6:\n v13 = v8;\n v14 = v8;\n while (v7 <= 0) {\n --v13;\n --v14;\n if (v13 == -1) goto LABEL_25;\n }\n do {\n v15 = 0LL;\n do {\n if (v13 == v8) {\n v16 = v9[v15];\n v17 = 0;\n } else {\n v16 = v9[v15];\n v17 = 0;\n v18 = v16[v13 + 1];\n if (v15) v17 = *((uint32_t *)v9[v15 - 1] + (unsigned int)(v13 + 1));\n if (v7 - 1 == (uint32_t)v15) {\n if (v18 < 0) v18 = 0;\n if (v18 >= v17) v17 = v18;\n } else {\n if (v18 < *((uint32_t *)v9[v15 + 1] + (unsigned int)(v13 + 1)))\n v18 = *((uint32_t *)v9[v15 + 1] + (unsigned int)(v13 + 1));\n if (v18 >= v17) v17 = v18;\n }\n }\n v19 = *(uint64_t *)(a1 + 8 * v15++);\n v16[v14] = *(uint32_t *)(v19 + v14 * 4) + v17;\n } while (v5 != v15);\n --v13;\n --v14;\n } while (v13 != -1);\n LABEL_25:\n v20 = *v12;\n if (v7 <= 1) {\n if (v7 != 1) goto LABEL_33;\n v10 = &v9[v26];\n goto LABEL_31;\n }\n v10 = &v9[v26];\n goto LABEL_27;\n }\n v20 = *(uint32_t *)*v9;\n if (a2 != 1) {\n LABEL_27:\n v21 = (unsigned int **)(v9 + 1);\n v22 = (long long)&v9[(unsigned int)(v7 - 2) + 2];\n do {\n if ((int)v20 < (int)**v21) v20 = **v21;\n ++v21;\n } while (v21 != (unsigned int **)v22);\n }\nLABEL_31:\n v23 = v9;\n do {\n v24 = *v23++;\n free(v24);\n } while (v23 != v10);\nLABEL_33:\n free(v9);\n return v20;\n}" + }, + { + "index": 423, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint max_three(int a, int b, int c) {\n\n int m = a > b ? a : b;\n\n return m > c ? m : c;\n\n}\n\n\n\n", + "func": "int func0(int** gold, int m, int n) {\n int** goldTable = (int**)malloc(m * sizeof(int*));\n for (int i = 0; i < m; i++) {\n goldTable[i] = (int*)calloc(n, sizeof(int));\n }\n for (int col = n - 1; col >= 0; col--) {\n for (int row = 0; row < m; row++) {\n int right = (col == n - 1) ? 0 : goldTable[row][col + 1];\n int right_up =\n (row == 0 || col == n - 1) ? 0 : goldTable[row - 1][col + 1];\n int right_down =\n (row == m - 1 || col == n - 1) ? 0 : goldTable[row + 1][col + 1];\n goldTable[row][col] =\n gold[row][col] + max_three(right, right_up, right_down);\n }\n }\n int res = goldTable[0][0];\n for (int i = 1; i < m; i++) {\n if (goldTable[i][0] > res) res = goldTable[i][0];\n }\n for (int i = 0; i < m; i++) free(goldTable[i]);\n free(goldTable);\n return res;\n}", + "test": "int main() {\n\n // Test case 1\n\n int gold1_data[4][4] = {\n\n {1, 3, 1, 5},\n\n {2, 2, 4, 1},\n\n {5, 0, 2, 3},\n\n {0, 6, 1, 2}\n\n };\n\n int* gold1[4];\n\n for(int i=0; i <4; i++)\n\n gold1[i] = gold1_data[i];\n\n assert(func0(gold1, 4, 4) == 16);\n\n\n\n // Test case 2\n\n int gold2_data[2][2] = {\n\n {10, 20},\n\n {30, 40}\n\n };\n\n int* gold2[2];\n\n for(int i=0; i <2; i++)\n\n gold2[i] = gold2_data[i];\n\n assert(func0(gold2, 2, 2) == 70);\n\n\n\n // Test case 3\n\n int gold3_data[2][2] = {\n\n {4, 9},\n\n {3, 7}\n\n };\n\n int* gold3[2];\n\n for(int i=0; i <2; i++)\n\n gold3[i] = gold3_data[i];\n\n assert(func0(gold3, 2, 2) == 13);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\nmov %rdi,%r12\nmovslq %esi,%rdi\npush %rbp\npush %rbx\nmov %rdi,%rbx\nshl $0x3,%rdi\nsub $0x18,%rsp\nmov %edx,0xc(%rsp)\ncallq 10d0 \nmov %rax,%rbp\ntest %ebx,%ebx\njle 140a \nmov %rax,%r13\nmovslq 0xc(%rsp),%r15\nlea -0x1(%rbx),%eax\nlea 0x8(%rbp,%rax,8),%r14\nmov $0x4,%esi\nmov %r15,%rdi\nadd $0x8,%r13\ncallq 10c0 \nmov %rax,-0x8(%r13)\ncmp %r13,%r14\njne 13f0 \nmov 0xc(%rsp),%r13d\nsub $0x1,%r13d\njs 14bf \nmovslq %r13d,%rsi\nlea -0x1(%rbx),%r8d\nmov %r13d,%r10d\nxor %r11d,%r11d\nshl $0x2,%rsi\nmov %r8,%r9\nnopl (%rax)\ntest %ebx,%ebx\njle 14ad \nlea 0x4(%rsi),%rcx\nxor %edx,%edx\ncmp %r10d,%r13d\njne 146d \njmpq 1540 \nnopl 0x0(%rax)\nmov 0x8(%rbp,%rdx,8),%r14\ncmp %eax,(%r14,%rcx,1)\ncmovge (%r14,%rcx,1),%eax\nmov (%r12,%rdx,8),%r14\nadd (%r14,%rsi,1),%eax\nmov %eax,(%rdi,%rsi,1)\nlea 0x1(%rdx),%rax\ncmp %rdx,%r8\nje 14ad \nmov %rax,%rdx\nmov 0x0(%rbp,%rdx,8),%rdi\nmov %edx,%r14d\nmov (%rdi,%rcx,1),%eax\ntest %edx,%edx\nje 1530 \nmov -0x8(%rbp,%rdx,8),%r15\ncmp %eax,(%r15,%rcx,1)\ncmovge (%r15,%rcx,1),%eax\ncmp %r14d,%r9d\njne 1448 \nmov (%r12,%rdx,8),%r14\ntest %eax,%eax\ncmovs %r11d,%eax\nadd (%r14,%rsi,1),%eax\nmov %eax,(%rdi,%rsi,1)\nlea 0x1(%rdx),%rax\ncmp %rdx,%r8\njne 146a \nsub $0x1,%r10d\nsub $0x4,%rsi\ncmp $0xffffffff,%r10d\njne 1430 \nmov 0x0(%rbp),%rdi\nmov (%rdi),%r13d\ncmp $0x1,%ebx\njle 157a \nlea -0x2(%rbx),%edx\nlea 0x8(%rbp),%rax\nlea 0x10(%rbp,%rdx,8),%rcx\nnopl 0x0(%rax,%rax,1)\nmov (%rax),%rdx\nmov (%rdx),%edx\ncmp %edx,%r13d\ncmovl %edx,%r13d\nadd $0x8,%rax\ncmp %rcx,%rax\njne 14e0 \nxor %r12d,%r12d\nnopl 0x0(%rax,%rax,1)\nmov 0x0(%rbp,%r12,8),%rdi\nadd $0x1,%r12\ncallq 1090 \ncmp %r12d,%ebx\njg 1500 \nmov %rbp,%rdi\ncallq 1090 \nadd $0x18,%rsp\nmov %r13d,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl (%rax)\ntest %eax,%eax\ncmovs %edx,%eax\njmpq 148e \nnopw 0x0(%rax,%rax,1)\nxor %eax,%eax\nnopw 0x0(%rax,%rax,1)\nmov (%r12,%rax,8),%rcx\nmov 0x0(%rbp,%rax,8),%rdx\nmov (%rcx,%rsi,1),%ecx\nmov %ecx,(%rdx,%rsi,1)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rdx,%r8\njne 1548 \nsub $0x1,%r10d\nsub $0x4,%rsi\ncmp $0xffffffff,%r10d\njne 1430 \njmpq 14bf \njne 1513 \ncallq 1090 \njmp 1513 \nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov r15d, edx\npush r14\npush r13\nmovsxd r13, esi\npush r12\nlea r14, ds:0[r13*8]\nmov r12, rdi\npush rbp\nmov rdi, r14; size\npush rbx\nsub rsp, 28h\nmov dword ptr [rsp+58h+ptr], esi\ncall _malloc\nmov esi, dword ptr [rsp+58h+ptr]\nmov rbp, rax\ntest esi, esi\njle loc_15BB\nlea r8d, [r15-1]\nmovsxd rax, r15d\nmov r15, rbp\nmov [rsp+58h+ptr], rbp\nmov [rsp+58h+var_44], r8d\nlea rbx, [r14+rbp]\nmov rbp, rax\nmov [rsp+58h+var_40], r12\nmov r12, r15\nmov r15d, esi\nnop dword ptr [rax+00h]\nloc_1438:\nmov esi, 4; size\nmov rdi, rbp; nmemb\nadd r12, 8\ncall _calloc\nmov [r12-8], rax\ncmp rbx, r12\njnz short loc_1438\nmovsxd rdi, [rsp+58h+var_44]\nmov rbp, [rsp+58h+ptr]\nmov esi, r15d\nlea r10d, [r15-1]\nmov r12, [rsp+58h+var_40]\nmov r8, rdi\nshl rdi, 2\nmov r11d, r8d\ntest r8d, r8d\njs loc_15C6\nmov [rsp+58h+ptr], r14\nmov r9d, r15d\nnop dword ptr [rax+00h]\nloc_1488:\nlea r15d, [r11+1]\nmov r14, [rsp+58h+ptr]\nxor eax, eax\nshl r15, 2\ncmp r11d, r8d\njz loc_1560\nloc_14A0:\nxor esi, esi\ntest rax, rax\njz short loc_14B0\nmov rdx, [rbp+rax*8-8]\nmov esi, [rdx+r15]\nloc_14B0:\nmov r14, [rbp+rax*8+0]\nmov edx, [r14+r15]\ncmp r10d, eax\njz loc_1580\nmov rcx, [rbp+rax*8+8]\nmov ecx, [rcx+r15]\ncmp edx, ecx\ncmovl edx, ecx\nmov rcx, [r12+rax*8]\ncmp edx, esi\ncmovl edx, esi\nadd rax, 1\nadd edx, [rcx+rdi]\nmov [r14+rdi], edx\ncmp r13, rax\njnz short loc_14A0\nloc_14E9:\nsub r11d, 1\nsub rdi, 4\ncmp r11d, 0FFFFFFFFh\njnz short loc_1488\nloc_14F7:\nmov rax, [rbp+0]\nmov esi, r9d\nmov r13d, [rax]\ncmp r9d, 1\njz short loc_152D\nloc_1507:\nlea edx, [rsi-2]\nlea rax, [rbp+8]\nlea rcx, [rbp+rdx*8+10h]\nnop dword ptr [rax+rax+00h]\nloc_1518:\nmov rdx, [rax]\nmov edx, [rdx]\ncmp r13d, edx\ncmovl r13d, edx\nadd rax, 8\ncmp rax, rcx\njnz short loc_1518\nloc_152D:\nmov r12, rbp\nloc_1530:\nmov rdi, [r12]; ptr\nadd r12, 8\ncall _free\ncmp r12, rbx\njnz short loc_1530\nloc_1542:\nmov rdi, rbp; ptr\ncall _free\nadd rsp, 28h\nmov eax, r13d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1560:\nmov rcx, [r12+rax]\nmov rdx, [rbp+rax+0]\nadd rax, 8\nmov ecx, [rcx+rdi]\nmov [rdx+rdi], ecx\ncmp r14, rax\njnz short loc_1560\njmp loc_14E9\nloc_1580:\nxor ecx, ecx\ntest edx, edx\ncmovns ecx, edx\ncmp ecx, esi\ncmovl ecx, esi\nmov rsi, [r12+rax*8]\nadd rax, 1\nadd ecx, [rsi+rdi]\nmov [r14+rdi], ecx\ncmp r13, rax\njnz loc_14A0\nsub r11d, 1\nsub rdi, 4\ncmp r11d, 0FFFFFFFFh\njnz loc_1488\njmp loc_14F7\nloc_15BB:\nmov rax, [rax]\nmov r13d, [rax]\njmp loc_1542\nloc_15C6:\nmov rax, [rbp+0]\nmov r13d, [rax]\ncmp r15d, 1\njnz loc_1507\njmp loc_152D", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n void *v4; // r13\n _DWORD **v5; // rax\n _DWORD **v6; // rbp\n int v7; // r8d\n size_t v8; // rax\n void **v9; // r15\n void **v10; // rbx\n size_t v11; // rbp\n void **v12; // r12\n int v13; // r15d\n int v14; // r10d\n __int64 v15; // rdi\n int v16; // r11d\n void *v17; // rax\n int v18; // esi\n _DWORD *v19; // r14\n int v20; // edx\n __int64 v21; // rcx\n unsigned int v22; // r13d\n unsigned int **v23; // rax\n void **v24; // r12\n void *v25; // rdi\n __int64 v27; // rcx\n __int64 v28; // rdx\n int v29; // ecx\n __int64 v30; // rsi\n _DWORD **ptr; // [rsp+8h] [rbp-50h]\n void *ptra; // [rsp+8h] [rbp-50h]\n int v33; // [rsp+14h] [rbp-44h]\n\n v4 = (void *)a2;\n v5 = (_DWORD **)malloc(8LL * a2);\n v6 = v5;\n if ( a2 <= 0 )\n {\n v22 = **v5;\n goto LABEL_23;\n }\n v7 = a3 - 1;\n v8 = a3;\n v9 = (void **)v6;\n ptr = v6;\n v33 = v7;\n v10 = (void **)&v6[a2];\n v11 = v8;\n v12 = v9;\n v13 = a2;\n do\n *v12++ = calloc(v11, 4uLL);\n while ( v10 != v12 );\n v6 = ptr;\n v14 = a2 - 1;\n v15 = v33;\n v16 = v33;\n if ( v33 >= 0 )\n {\n ptra = (void *)(8LL * a2);\n do\n {\n while ( 1 )\n {\n v17 = 0LL;\n if ( v16 != v33 )\n break;\n do\n {\n v27 = *(_QWORD *)((char *)v17 + a1);\n v28 = *(_QWORD *)((char *)v17 + (_QWORD)v6);\n v17 = (char *)v17 + 8;\n *(_DWORD *)(v28 + v15 * 4) = *(_DWORD *)(v27 + v15 * 4);\n }\n while ( ptra != v17 );\nLABEL_15:\n --v16;\n --v15;\n if ( v16 == -1 )\n goto LABEL_16;\n }\n do\n {\n while ( 1 )\n {\n v18 = 0;\n if ( v17 )\n v18 = v6[(_QWORD)v17 - 1][v16 + 1];\n v19 = v6[(_QWORD)v17];\n v20 = v19[v16 + 1];\n if ( v14 == (_DWORD)v17 )\n break;\n if ( v20 < v6[(_QWORD)v17 + 1][v16 + 1] )\n v20 = v6[(_QWORD)v17 + 1][v16 + 1];\n v21 = *(_QWORD *)(a1 + 8LL * (_QWORD)v17);\n if ( v20 < v18 )\n v20 = v18;\n v17 = (char *)v17 + 1;\n v19[v15] = *(_DWORD *)(v21 + v15 * 4) + v20;\n if ( v4 == v17 )\n goto LABEL_15;\n }\n v29 = 0;\n if ( v20 >= 0 )\n v29 = v19[v16 + 1];\n if ( v29 < v18 )\n v29 = v18;\n v30 = *(_QWORD *)(a1 + 8LL * (_QWORD)v17);\n v17 = (char *)v17 + 1;\n v19[v15] = *(_DWORD *)(v30 + v15 * 4) + v29;\n }\n while ( v4 != v17 );\n --v16;\n --v15;\n }\n while ( v16 != -1 );\nLABEL_16:\n a2 = v13;\n v22 = **v6;\n if ( v13 == 1 )\n goto LABEL_21;\n goto LABEL_17;\n }\n v22 = **ptr;\n if ( a2 != 1 )\n {\nLABEL_17:\n v23 = v6 + 1;\n do\n {\n if ( (int)v22 < (int)**v23 )\n v22 = **v23;\n ++v23;\n }\n while ( v23 != &v6[(unsigned int)(a2 - 2) + 2] );\n }\nLABEL_21:\n v24 = (void **)v6;\n do\n {\n v25 = *v24++;\n free(v25);\n }\n while ( v24 != v10 );\nLABEL_23:\n free(v6);\n return v22;\n}", + "ida_strip_asm": "sub_13D0:\nendbr64\npush r15\nmov r15d, edx\npush r14\npush r13\nmovsxd r13, esi\npush r12\nlea r14, ds:0[r13*8]\nmov r12, rdi\npush rbp\nmov rdi, r14; size\npush rbx\nsub rsp, 28h\nmov dword ptr [rsp+58h+ptr], esi\ncall _malloc\nmov esi, dword ptr [rsp+58h+ptr]\nmov rbp, rax\ntest esi, esi\njle loc_15BB\nlea r8d, [r15-1]\nmovsxd rax, r15d\nmov r15, rbp\nmov [rsp+58h+ptr], rbp\nmov [rsp+58h+var_44], r8d\nlea rbx, [r14+rbp]\nmov rbp, rax\nmov [rsp+58h+var_40], r12\nmov r12, r15\nmov r15d, esi\nnop dword ptr [rax+00h]\nloc_1438:\nmov esi, 4; size\nmov rdi, rbp; nmemb\nadd r12, 8\ncall _calloc\nmov [r12-8], rax\ncmp rbx, r12\njnz short loc_1438\nmovsxd rdi, [rsp+58h+var_44]\nmov rbp, [rsp+58h+ptr]\nmov esi, r15d\nlea r10d, [r15-1]\nmov r12, [rsp+58h+var_40]\nmov r8, rdi\nshl rdi, 2\nmov r11d, r8d\ntest r8d, r8d\njs loc_15C6\nmov [rsp+58h+ptr], r14\nmov r9d, r15d\nnop dword ptr [rax+00h]\nloc_1488:\nlea r15d, [r11+1]\nmov r14, [rsp+58h+ptr]\nxor eax, eax\nshl r15, 2\ncmp r11d, r8d\njz loc_1560\nloc_14A0:\nxor esi, esi\ntest rax, rax\njz short loc_14B0\nmov rdx, [rbp+rax*8-8]\nmov esi, [rdx+r15]\nloc_14B0:\nmov r14, [rbp+rax*8+0]\nmov edx, [r14+r15]\ncmp r10d, eax\njz loc_1580\nmov rcx, [rbp+rax*8+8]\nmov ecx, [rcx+r15]\ncmp edx, ecx\ncmovl edx, ecx\nmov rcx, [r12+rax*8]\ncmp edx, esi\ncmovl edx, esi\nadd rax, 1\nadd edx, [rcx+rdi]\nmov [r14+rdi], edx\ncmp r13, rax\njnz short loc_14A0\nloc_14E9:\nsub r11d, 1\nsub rdi, 4\ncmp r11d, 0FFFFFFFFh\njnz short loc_1488\nloc_14F7:\nmov rax, [rbp+0]\nmov esi, r9d\nmov r13d, [rax]\ncmp r9d, 1\njz short loc_152D\nloc_1507:\nlea edx, [rsi-2]\nlea rax, [rbp+8]\nlea rcx, [rbp+rdx*8+10h]\nnop dword ptr [rax+rax+00h]\nloc_1518:\nmov rdx, [rax]\nmov edx, [rdx]\ncmp r13d, edx\ncmovl r13d, edx\nadd rax, 8\ncmp rax, rcx\njnz short loc_1518\nloc_152D:\nmov r12, rbp\nloc_1530:\nmov rdi, [r12]; ptr\nadd r12, 8\ncall _free\ncmp r12, rbx\njnz short loc_1530\nloc_1542:\nmov rdi, rbp; ptr\ncall _free\nadd rsp, 28h\nmov eax, r13d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1560:\nmov rcx, [r12+rax]\nmov rdx, [rbp+rax+0]\nadd rax, 8\nmov ecx, [rcx+rdi]\nmov [rdx+rdi], ecx\ncmp r14, rax\njnz short loc_1560\njmp loc_14E9\nloc_1580:\nxor ecx, ecx\ntest edx, edx\ncmovns ecx, edx\ncmp ecx, esi\ncmovl ecx, esi\nmov rsi, [r12+rax*8]\nadd rax, 1\nadd ecx, [rsi+rdi]\nmov [r14+rdi], ecx\ncmp r13, rax\njnz loc_14A0\nsub r11d, 1\nsub rdi, 4\ncmp r11d, 0FFFFFFFFh\njnz loc_1488\njmp loc_14F7\nloc_15BB:\nmov rax, [rax]\nmov r13d, [rax]\njmp loc_1542\nloc_15C6:\nmov rax, [rbp+0]\nmov r13d, [rax]\ncmp r15d, 1\njnz loc_1507\njmp loc_152D", + "ida_strip_pseudo": "__int64 __fastcall sub_13D0(__int64 a1, int a2, int a3)\n{\n void *v4; // r13\n _DWORD **v5; // rax\n _DWORD **v6; // rbp\n int v7; // r8d\n size_t v8; // rax\n void **v9; // r15\n void **v10; // rbx\n size_t v11; // rbp\n void **v12; // r12\n int v13; // r15d\n int v14; // r10d\n __int64 v15; // rdi\n int v16; // r11d\n void *v17; // rax\n int v18; // esi\n _DWORD *v19; // r14\n int v20; // edx\n __int64 v21; // rcx\n unsigned int v22; // r13d\n unsigned int **v23; // rax\n void **v24; // r12\n void *v25; // rdi\n __int64 v27; // rcx\n __int64 v28; // rdx\n int v29; // ecx\n __int64 v30; // rsi\n _DWORD **ptr; // [rsp+8h] [rbp-50h]\n void *ptra; // [rsp+8h] [rbp-50h]\n int v33; // [rsp+14h] [rbp-44h]\n\n v4 = (void *)a2;\n v5 = (_DWORD **)malloc(8LL * a2);\n v6 = v5;\n if ( a2 <= 0 )\n {\n v22 = **v5;\n goto LABEL_23;\n }\n v7 = a3 - 1;\n v8 = a3;\n v9 = (void **)v6;\n ptr = v6;\n v33 = v7;\n v10 = (void **)&v6[a2];\n v11 = v8;\n v12 = v9;\n v13 = a2;\n do\n *v12++ = calloc(v11, 4uLL);\n while ( v10 != v12 );\n v6 = ptr;\n v14 = a2 - 1;\n v15 = v33;\n v16 = v33;\n if ( v33 >= 0 )\n {\n ptra = (void *)(8LL * a2);\n do\n {\n while ( 1 )\n {\n v17 = 0LL;\n if ( v16 != v33 )\n break;\n do\n {\n v27 = *(_QWORD *)((char *)v17 + a1);\n v28 = *(_QWORD *)((char *)v17 + (_QWORD)v6);\n v17 = (char *)v17 + 8;\n *(_DWORD *)(v28 + v15 * 4) = *(_DWORD *)(v27 + v15 * 4);\n }\n while ( ptra != v17 );\nLABEL_15:\n --v16;\n --v15;\n if ( v16 == -1 )\n goto LABEL_16;\n }\n do\n {\n while ( 1 )\n {\n v18 = 0;\n if ( v17 )\n v18 = v6[(_QWORD)v17 - 1][v16 + 1];\n v19 = v6[(_QWORD)v17];\n v20 = v19[v16 + 1];\n if ( v14 == (_DWORD)v17 )\n break;\n if ( v20 < v6[(_QWORD)v17 + 1][v16 + 1] )\n v20 = v6[(_QWORD)v17 + 1][v16 + 1];\n v21 = *(_QWORD *)(a1 + 8LL * (_QWORD)v17);\n if ( v20 < v18 )\n v20 = v18;\n v17 = (char *)v17 + 1;\n v19[v15] = *(_DWORD *)(v21 + v15 * 4) + v20;\n if ( v4 == v17 )\n goto LABEL_15;\n }\n v29 = 0;\n if ( v20 >= 0 )\n v29 = v19[v16 + 1];\n if ( v29 < v18 )\n v29 = v18;\n v30 = *(_QWORD *)(a1 + 8LL * (_QWORD)v17);\n v17 = (char *)v17 + 1;\n v19[v15] = *(_DWORD *)(v30 + v15 * 4) + v29;\n }\n while ( v4 != v17 );\n --v16;\n --v15;\n }\n while ( v16 != -1 );\nLABEL_16:\n a2 = v13;\n v22 = **v6;\n if ( v13 == 1 )\n goto LABEL_21;\n goto LABEL_17;\n }\n v22 = **ptr;\n if ( a2 != 1 )\n {\nLABEL_17:\n v23 = v6 + 1;\n do\n {\n if ( (int)v22 < (int)**v23 )\n v22 = **v23;\n ++v23;\n }\n while ( v23 != &v6[(unsigned int)(a2 - 2) + 2] );\n }\nLABEL_21:\n v24 = (void **)v6;\n do\n {\n v25 = *v24++;\n free(v25);\n }\n while ( v24 != v10 );\nLABEL_23:\n free(v6);\n return v22;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_13D0(long long a1, int a2, int a3) {\n void *v4;\n uint32_t **v5;\n uint32_t **v6;\n int v7;\n unsigned int v8;\n void **v9;\n void **v10;\n unsigned int v11;\n void **v12;\n int v13;\n int v14;\n long long v15;\n int v16;\n void *v17;\n int v18;\n uint32_t *v19;\n int v20;\n long long v21;\n unsigned int v22;\n unsigned int **v23;\n void **v24;\n void *v25;\n long long v27;\n long long v28;\n int v29;\n long long v30;\n uint32_t **ptr;\n void *ptra;\n int v33;\n v4 = (void *)a2;\n v5 = (uint32_t **)malloc(8LL * a2);\n v6 = v5;\n if (a2 <= 0) {\n v22 = **v5;\n goto LABEL_23;\n }\n v7 = a3 - 1;\n v8 = a3;\n v9 = (void **)v6;\n ptr = v6;\n v33 = v7;\n v10 = (void **)&v6[a2];\n v11 = v8;\n v12 = v9;\n v13 = a2;\n do\n *v12++ = calloc(v11, 4uLL);\n while (v10 != v12);\n v6 = ptr;\n v14 = a2 - 1;\n v15 = v33;\n v16 = v33;\n if (v33 >= 0) {\n ptra = (void *)(8LL * a2);\n do {\n while (1) {\n v17 = 0LL;\n if (v16 != v33) break;\n do {\n v27 = *(uint64_t *)((char *)v17 + a1);\n v28 = *(uint64_t *)((char *)v17 + (uint64_t)v6);\n v17 = (char *)v17 + 8;\n *(uint32_t *)(v28 + v15 * 4) = *(uint32_t *)(v27 + v15 * 4);\n } while (ptra != v17);\n LABEL_15:\n --v16;\n --v15;\n if (v16 == -1) goto LABEL_16;\n }\n do {\n while (1) {\n v18 = 0;\n if (v17) v18 = v6[(uint64_t)v17 - 1][v16 + 1];\n v19 = v6[(uint64_t)v17];\n v20 = v19[v16 + 1];\n if (v14 == (uint32_t)v17) break;\n if (v20 < v6[(uint64_t)v17 + 1][v16 + 1])\n v20 = v6[(uint64_t)v17 + 1][v16 + 1];\n v21 = *(uint64_t *)(a1 + 8LL * (uint64_t)v17);\n if (v20 < v18) v20 = v18;\n v17 = (char *)v17 + 1;\n v19[v15] = *(uint32_t *)(v21 + v15 * 4) + v20;\n if (v4 == v17) goto LABEL_15;\n }\n v29 = 0;\n if (v20 >= 0) v29 = v19[v16 + 1];\n if (v29 < v18) v29 = v18;\n v30 = *(uint64_t *)(a1 + 8LL * (uint64_t)v17);\n v17 = (char *)v17 + 1;\n v19[v15] = *(uint32_t *)(v30 + v15 * 4) + v29;\n } while (v4 != v17);\n --v16;\n --v15;\n } while (v16 != -1);\n LABEL_16:\n a2 = v13;\n v22 = **v6;\n if (v13 == 1) goto LABEL_21;\n goto LABEL_17;\n }\n v22 = **ptr;\n if (a2 != 1) {\n LABEL_17:\n v23 = v6 + 1;\n do {\n if ((int)v22 < (int)**v23) v22 = **v23;\n ++v23;\n } while (v23 != &v6[(unsigned int)(a2 - 2) + 2]);\n }\nLABEL_21:\n v24 = (void **)v6;\n do {\n v25 = *v24++;\n free(v25);\n } while (v24 != v10);\nLABEL_23:\n free(v6);\n return v22;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n void *v4;\n uint32_t **v5;\n uint32_t **v6;\n int v7;\n unsigned int v8;\n void **v9;\n void **v10;\n unsigned int v11;\n void **v12;\n int v13;\n int v14;\n long long v15;\n int v16;\n void *v17;\n int v18;\n uint32_t *v19;\n int v20;\n long long v21;\n unsigned int v22;\n unsigned int **v23;\n void **v24;\n void *v25;\n long long v27;\n long long v28;\n int v29;\n long long v30;\n uint32_t **ptr;\n void *ptra;\n int v33;\n v4 = (void *)a2;\n v5 = (uint32_t **)malloc(8LL * a2);\n v6 = v5;\n if (a2 <= 0) {\n v22 = **v5;\n goto LABEL_23;\n }\n v7 = a3 - 1;\n v8 = a3;\n v9 = (void **)v6;\n ptr = v6;\n v33 = v7;\n v10 = (void **)&v6[a2];\n v11 = v8;\n v12 = v9;\n v13 = a2;\n do\n *v12++ = calloc(v11, 4uLL);\n while (v10 != v12);\n v6 = ptr;\n v14 = a2 - 1;\n v15 = v33;\n v16 = v33;\n if (v33 >= 0) {\n ptra = (void *)(8LL * a2);\n do {\n while (1) {\n v17 = 0LL;\n if (v16 != v33) break;\n do {\n v27 = *(uint64_t *)((char *)v17 + a1);\n v28 = *(uint64_t *)((char *)v17 + (uint64_t)v6);\n v17 = (char *)v17 + 8;\n *(uint32_t *)(v28 + v15 * 4) = *(uint32_t *)(v27 + v15 * 4);\n } while (ptra != v17);\n LABEL_15:\n --v16;\n --v15;\n if (v16 == -1) goto LABEL_16;\n }\n do {\n while (1) {\n v18 = 0;\n if (v17) v18 = v6[(uint64_t)v17 - 1][v16 + 1];\n v19 = v6[(uint64_t)v17];\n v20 = v19[v16 + 1];\n if (v14 == (uint32_t)v17) break;\n if (v20 < v6[(uint64_t)v17 + 1][v16 + 1])\n v20 = v6[(uint64_t)v17 + 1][v16 + 1];\n v21 = *(uint64_t *)(a1 + 8LL * (uint64_t)v17);\n if (v20 < v18) v20 = v18;\n v17 = (char *)v17 + 1;\n v19[v15] = *(uint32_t *)(v21 + v15 * 4) + v20;\n if (v4 == v17) goto LABEL_15;\n }\n v29 = 0;\n if (v20 >= 0) v29 = v19[v16 + 1];\n if (v29 < v18) v29 = v18;\n v30 = *(uint64_t *)(a1 + 8LL * (uint64_t)v17);\n v17 = (char *)v17 + 1;\n v19[v15] = *(uint32_t *)(v30 + v15 * 4) + v29;\n } while (v4 != v17);\n --v16;\n --v15;\n } while (v16 != -1);\n LABEL_16:\n a2 = v13;\n v22 = **v6;\n if (v13 == 1) goto LABEL_21;\n goto LABEL_17;\n }\n v22 = **ptr;\n if (a2 != 1) {\n LABEL_17:\n v23 = v6 + 1;\n do {\n if ((int)v22 < (int)**v23) v22 = **v23;\n ++v23;\n } while (v23 != &v6[(unsigned int)(a2 - 2) + 2]);\n }\nLABEL_21:\n v24 = (void **)v6;\n do {\n v25 = *v24++;\n free(v25);\n } while (v24 != v10);\nLABEL_23:\n free(v6);\n return v22;\n}" + }, + { + "index": 424, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char *func0(const char *test_tuple[], int size) {\n static char res[100];\n for (int i = 0; i < size; i++) {\n int length = strlen(test_tuple[i]);\n res[i] = test_tuple[i][length - 1];\n }\n res[size] = '\\0';\n return res;\n}", + "test": "int main() {\n\n const char *test_tuple1[] = {\"Mers\", \"for\", \"Vers\"};\n\n const char *test_tuple2[] = {\"Avenge\", \"for\", \"People\"};\n\n const char *test_tuple3[] = {\"Gotta\", \"get\", \"go\"};\n\n\n\n assert(strcmp(func0(test_tuple1, 3), \"srs\") == 0);\n\n assert(strcmp(func0(test_tuple2, 3), \"ere\") == 0);\n\n assert(strcmp(func0(test_tuple3, 3), \"ato\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 1221 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov %rax,%rdi\ncallq 1080 \nmov %eax,-0x4(%rbp)\nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0x4(%rbp),%edx\nmovslq %edx,%rdx\nsub $0x1,%rdx\nadd %rdx,%rax\nmovzbl (%rax),%edx\nmov -0x8(%rbp),%eax\ncltq\nlea 0x2e26(%rip),%rcx\nmov %dl,(%rax,%rcx,1)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11c5 \nmov -0x1c(%rbp),%eax\ncltq\nlea 0x2e0b(%rip),%rdx\nmovb $0x0,(%rax,%rdx,1)\nlea 0x2e00(%rip),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\njmp short loc_1221\nloc_11C5:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nsub rdx, 1\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_8]\ncdqe\nlea rcx, res_1\nmov [rax+rcx], dl\nadd [rbp+var_8], 1\nloc_1221:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_11C5\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, res_1\nmov byte ptr [rax+rdx], 0\nlea rax, res_1\nleave\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-8h]\n\n for ( i = 0; i < a2; ++i )\n res_1[i] = *(_BYTE *)((int)strlen(*(const char **)(8LL * i + a1)) - 1LL + *(_QWORD *)(8LL * i + a1));\n res_1[a2] = 0;\n return res_1;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\njmp short loc_1221\nloc_11C5:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nsub rdx, 1\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_8]\ncdqe\nlea rcx, unk_4040\nmov [rax+rcx], dl\nadd [rbp+var_8], 1\nloc_1221:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_11C5\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, unk_4040\nmov byte ptr [rax+rdx], 0\nlea rax, unk_4040\nleave\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_11A9(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-8h]\n\n for ( i = 0; i < a2; ++i )\n byte_4040[i] = *(_BYTE *)((int)strlen(*(const char **)(8LL * i + a1)) - 1LL + *(_QWORD *)(8LL * i + a1));\n byte_4040[a2] = 0;\n return byte_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_11A9(long long a1, int a2) {\n int i;\n for (i = 0; i < a2; ++i)\n byte_4040[i] = *(uint8_t *)((int)strlen(*(const char **)(8LL * i + a1)) -\n 1LL + *(uint64_t *)(8LL * i + a1));\n byte_4040[a2] = 0;\n return byte_4040;\n}", + "ida_pseudo_norm": "uint8_t *func0(long long a1, int a2) {\n int i;\n for (i = 0; i < a2; ++i)\n res_1[i] = *(uint8_t *)((int)strlen(*(const char **)(8LL * i + a1)) - 1LL +\n *(uint64_t *)(8LL * i + a1));\n res_1[a2] = 0;\n return res_1;\n}" + }, + { + "index": 424, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char *func0(const char *test_tuple[], int size) {\n static char res[100];\n for (int i = 0; i < size; i++) {\n int length = strlen(test_tuple[i]);\n res[i] = test_tuple[i][length - 1];\n }\n res[size] = '\\0';\n return res;\n}", + "test": "int main() {\n\n const char *test_tuple1[] = {\"Mers\", \"for\", \"Vers\"};\n\n const char *test_tuple2[] = {\"Avenge\", \"for\", \"People\"};\n\n const char *test_tuple3[] = {\"Gotta\", \"get\", \"go\"};\n\n\n\n assert(strcmp(func0(test_tuple1, 3), \"srs\") == 0);\n\n assert(strcmp(func0(test_tuple2, 3), \"ere\") == 0);\n\n assert(strcmp(func0(test_tuple3, 3), \"ato\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11ba \nmov %rdi,%rdx\nlea 0x2ec5(%rip),%r8\nlea -0x1(%rsi),%eax\nlea 0x8(%rdi,%rax,8),%r11\nmov $0xffffffffffffffff,%r10\nmov $0x0,%eax\nmov (%rdx),%r9\nmov %r10,%rcx\nmov %r9,%rdi\nrepnz scas %es:(%rdi),%al\nnot %rcx\nsub $0x1,%rcx\nmovslq %ecx,%rcx\nmovzbl -0x1(%r9,%rcx,1),%ecx\nmov %cl,(%r8)\nadd $0x8,%rdx\nadd $0x1,%r8\ncmp %r11,%rdx\njne 118f \nlea 0x2e7f(%rip),%rax\nmovslq %esi,%rsi\nmovb $0x0,(%rax,%rsi,1)\nretq\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r14d, esi\ntest esi, esi\njle short loc_11F0\nmov rbx, rdi\nlea rbp, res_1\nmovsxd rax, esi\nlea r13, [rdi+rax*8]\nloc_11CD:\nmov r12, [rbx]\nmov rdi, r12; s\ncall _strlen\ncdqe\nmovzx eax, byte ptr [r12+rax-1]\nmov [rbp+0], al\nadd rbx, 8\nadd rbp, 1\ncmp rbx, r13\njnz short loc_11CD\nloc_11F0:\nlea rax, res_1\nmovsxd r14, r14d\nmov byte ptr [rax+r14], 0\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(const char **a1, int a2)\n{\n const char **v2; // rbx\n _BYTE *v3; // rbp\n const char *v4; // r12\n _BYTE *result; // rax\n\n if ( a2 > 0 )\n {\n v2 = a1;\n v3 = res_1;\n do\n {\n v4 = *v2;\n *v3++ = v4[(int)strlen(*v2++) - 1];\n }\n while ( v2 != &a1[a2] );\n }\n result = res_1;\n res_1[a2] = 0;\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r14d, esi\ntest esi, esi\njle short loc_11F0\nmov rbx, rdi\nlea rbp, unk_4040\nmovsxd rax, esi\nlea r13, [rdi+rax*8]\nloc_11CD:\nmov r12, [rbx]\nmov rdi, r12; s\ncall _strlen\ncdqe\nmovzx eax, byte ptr [r12+rax-1]\nmov [rbp+0], al\nadd rbx, 8\nadd rbp, 1\ncmp rbx, r13\njnz short loc_11CD\nloc_11F0:\nlea rax, unk_4040\nmovsxd r14, r14d\nmov byte ptr [rax+r14], 0\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_11A9(const char **a1, int a2)\n{\n const char **v2; // rbx\n _BYTE *v3; // rbp\n const char *v4; // r12\n _BYTE *result; // rax\n\n if ( a2 > 0 )\n {\n v2 = a1;\n v3 = byte_4040;\n do\n {\n v4 = *v2;\n *v3++ = v4[(int)strlen(*v2++) - 1];\n }\n while ( v2 != &a1[a2] );\n }\n result = byte_4040;\n byte_4040[a2] = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_11A9(const char **a1, int a2) {\n const char **v2;\n uint8_t *v3;\n const char *v4;\n uint8_t *result;\n if (a2 > 0) {\n v2 = a1;\n v3 = byte_4040;\n do {\n v4 = *v2;\n *v3++ = v4[(int)strlen(*v2++) - 1];\n } while (v2 != &a1[a2]);\n }\n result = byte_4040;\n byte_4040[a2] = 0;\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char **a1, int a2) {\n const char **v2;\n uint8_t *v3;\n const char *v4;\n uint8_t *result;\n if (a2 > 0) {\n v2 = a1;\n v3 = res_1;\n do {\n v4 = *v2;\n *v3++ = v4[(int)strlen(*v2++) - 1];\n } while (v2 != &a1[a2]);\n }\n result = res_1;\n res_1[a2] = 0;\n return result;\n}" + }, + { + "index": 424, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char *func0(const char *test_tuple[], int size) {\n static char res[100];\n for (int i = 0; i < size; i++) {\n int length = strlen(test_tuple[i]);\n res[i] = test_tuple[i][length - 1];\n }\n res[size] = '\\0';\n return res;\n}", + "test": "int main() {\n\n const char *test_tuple1[] = {\"Mers\", \"for\", \"Vers\"};\n\n const char *test_tuple2[] = {\"Avenge\", \"for\", \"People\"};\n\n const char *test_tuple3[] = {\"Gotta\", \"get\", \"go\"};\n\n\n\n assert(strcmp(func0(test_tuple1, 3), \"srs\") == 0);\n\n assert(strcmp(func0(test_tuple2, 3), \"ere\") == 0);\n\n assert(strcmp(func0(test_tuple3, 3), \"ato\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\nlea 0x2d1d(%rip),%r12\npush %rbp\nmovslq %esi,%rbp\npush %rbx\nsub $0x8,%rsp\ntest %ebp,%ebp\njle 1364 \nlea -0x1(%rbp),%eax\nmov %rdi,%rbx\nmov %r12,%r14\nlea 0x8(%rdi,%rax,8),%r13\nxchg %ax,%ax\nmov (%rbx),%r15\nadd $0x8,%rbx\nadd $0x1,%r14\nmov %r15,%rdi\ncallq 1070 \ncltq\nmovzbl -0x1(%r15,%rax,1),%eax\nmov %al,-0x1(%r14)\ncmp %r13,%rbx\njne 1340 \nmovb $0x0,(%r12,%rbp,1)\nadd $0x8,%rsp\nlea 0x2ccc(%rip),%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\nlea r13, res_1\npush r12\nmovsxd r12, esi\npush rbp\npush rbx\nsub rsp, 8\ntest esi, esi\njle short loc_137C\nlea r13, res_1\nmovsxd r12, esi\nmov rbx, rdi\nmov r14, r13\nlea rbp, [rdi+r12*8]\nnop dword ptr [rax+00h]\nloc_1358:\nmov r15, [rbx]\nadd rbx, 8\nadd r14, 1\nmov rdi, r15; s\ncall _strlen\ncdqe\nmovzx eax, byte ptr [r15+rax-1]\nmov [r14-1], al\ncmp rbp, rbx\njnz short loc_1358\nloc_137C:\nmov byte ptr [r13+r12+0], 0\nadd rsp, 8\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(const char **a1, int a2)\n{\n __int64 v2; // r12\n const char **v3; // rbx\n _BYTE *v4; // r14\n const char *v5; // r15\n\n v2 = a2;\n if ( a2 > 0 )\n {\n v2 = a2;\n v3 = a1;\n v4 = res_1;\n do\n {\n v5 = *v3++;\n *v4++ = v5[(int)strlen(v5) - 1];\n }\n while ( &a1[a2] != v3 );\n }\n res_1[v2] = 0;\n return res_1;\n}", + "ida_strip_asm": "sub_1320:\nendbr64\npush r15\npush r14\npush r13\nlea r13, unk_4040\npush r12\nmovsxd r12, esi\npush rbp\npush rbx\nsub rsp, 8\ntest esi, esi\njle short loc_137C\nlea r13, unk_4040\nmovsxd r12, esi\nmov rbx, rdi\nmov r14, r13\nlea rbp, [rdi+r12*8]\nnop dword ptr [rax+00h]\nloc_1358:\nmov r15, [rbx]\nadd rbx, 8\nadd r14, 1\nmov rdi, r15; s\ncall _strlen\ncdqe\nmovzx eax, byte ptr [r15+rax-1]\nmov [r14-1], al\ncmp rbp, rbx\njnz short loc_1358\nloc_137C:\nmov byte ptr [r13+r12+0], 0\nadd rsp, 8\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1320(const char **a1, int a2)\n{\n __int64 v2; // r12\n const char **v3; // rbx\n _BYTE *v4; // r14\n const char *v5; // r15\n\n v2 = a2;\n if ( a2 > 0 )\n {\n v2 = a2;\n v3 = a1;\n v4 = byte_4040;\n do\n {\n v5 = *v3++;\n *v4++ = v5[(int)strlen(v5) - 1];\n }\n while ( &a1[a2] != v3 );\n }\n byte_4040[v2] = 0;\n return byte_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1320(const char **a1, int a2) {\n long long v2;\n const char **v3;\n uint8_t *v4;\n const char *v5;\n v2 = a2;\n if (a2 > 0) {\n v2 = a2;\n v3 = a1;\n v4 = byte_4040;\n do {\n v5 = *v3++;\n *v4++ = v5[(int)strlen(v5) - 1];\n } while (&a1[a2] != v3);\n }\n byte_4040[v2] = 0;\n return byte_4040;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char **a1, int a2) {\n long long v2;\n const char **v3;\n uint8_t *v4;\n const char *v5;\n v2 = a2;\n if (a2 > 0) {\n v2 = a2;\n v3 = a1;\n v4 = res_1;\n do {\n v5 = *v3++;\n *v4++ = v5[(int)strlen(v5) - 1];\n } while (&a1[a2] != v3);\n }\n res_1[v2] = 0;\n return res_1;\n}" + }, + { + "index": 424, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char *func0(const char *test_tuple[], int size) {\n static char res[100];\n for (int i = 0; i < size; i++) {\n int length = strlen(test_tuple[i]);\n res[i] = test_tuple[i][length - 1];\n }\n res[size] = '\\0';\n return res;\n}", + "test": "int main() {\n\n const char *test_tuple1[] = {\"Mers\", \"for\", \"Vers\"};\n\n const char *test_tuple2[] = {\"Avenge\", \"for\", \"People\"};\n\n const char *test_tuple3[] = {\"Gotta\", \"get\", \"go\"};\n\n\n\n assert(strcmp(func0(test_tuple1, 3), \"srs\") == 0);\n\n assert(strcmp(func0(test_tuple2, 3), \"ere\") == 0);\n\n assert(strcmp(func0(test_tuple3, 3), \"ato\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\nlea 0x2d0d(%rip),%r12\npush %rbp\nmovslq %esi,%rbp\npush %rbx\nsub $0x8,%rsp\ntest %ebp,%ebp\njle 1374 \nlea -0x1(%rbp),%eax\nmov %rdi,%rbx\nmov %r12,%r14\nlea 0x8(%rdi,%rax,8),%r13\nxchg %ax,%ax\nmov (%rbx),%r15\nadd $0x8,%rbx\nadd $0x1,%r14\nmov %r15,%rdi\ncallq 1070 \ncltq\nmovzbl -0x1(%r15,%rax,1),%eax\nmov %al,-0x1(%r14)\ncmp %rbx,%r13\njne 1350 \nmovb $0x0,(%r12,%rbp,1)\nadd $0x8,%rsp\nlea 0x2cbc(%rip),%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\nlea r13, res_1\npush r12\nmovsxd r12, esi\npush rbp\npush rbx\nsub rsp, 8\ntest esi, esi\njle short loc_137C\nlea r13, res_1\nmovsxd r12, esi\nmov rbx, rdi\nmov r14, r13\nlea rbp, [rdi+r12*8]\nnop dword ptr [rax+00h]\nloc_1358:\nmov r15, [rbx]\nadd rbx, 8\nadd r14, 1\nmov rdi, r15; s\ncall _strlen\ncdqe\nmovzx eax, byte ptr [r15+rax-1]\nmov [r14-1], al\ncmp rbp, rbx\njnz short loc_1358\nloc_137C:\nmov byte ptr [r13+r12+0], 0\nadd rsp, 8\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(const char **a1, int a2)\n{\n __int64 v2; // r12\n const char **v3; // rbx\n _BYTE *v4; // r14\n const char *v5; // r15\n\n v2 = a2;\n if ( a2 > 0 )\n {\n v2 = a2;\n v3 = a1;\n v4 = res_1;\n do\n {\n v5 = *v3++;\n *v4++ = v5[(int)strlen(v5) - 1];\n }\n while ( &a1[a2] != v3 );\n }\n res_1[v2] = 0;\n return res_1;\n}", + "ida_strip_asm": "sub_1320:\nendbr64\npush r15\npush r14\npush r13\nlea r13, unk_4040\npush r12\nmovsxd r12, esi\npush rbp\npush rbx\nsub rsp, 8\ntest esi, esi\njle short loc_137C\nlea r13, unk_4040\nmovsxd r12, esi\nmov rbx, rdi\nmov r14, r13\nlea rbp, [rdi+r12*8]\nnop dword ptr [rax+00h]\nloc_1358:\nmov r15, [rbx]\nadd rbx, 8\nadd r14, 1\nmov rdi, r15; s\ncall _strlen\ncdqe\nmovzx eax, byte ptr [r15+rax-1]\nmov [r14-1], al\ncmp rbp, rbx\njnz short loc_1358\nloc_137C:\nmov byte ptr [r13+r12+0], 0\nadd rsp, 8\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1320(const char **a1, int a2)\n{\n __int64 v2; // r12\n const char **v3; // rbx\n _BYTE *v4; // r14\n const char *v5; // r15\n\n v2 = a2;\n if ( a2 > 0 )\n {\n v2 = a2;\n v3 = a1;\n v4 = byte_4040;\n do\n {\n v5 = *v3++;\n *v4++ = v5[(int)strlen(v5) - 1];\n }\n while ( &a1[a2] != v3 );\n }\n byte_4040[v2] = 0;\n return byte_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1320(const char **a1, int a2) {\n long long v2;\n const char **v3;\n uint8_t *v4;\n const char *v5;\n v2 = a2;\n if (a2 > 0) {\n v2 = a2;\n v3 = a1;\n v4 = byte_4040;\n do {\n v5 = *v3++;\n *v4++ = v5[(int)strlen(v5) - 1];\n } while (&a1[a2] != v3);\n }\n byte_4040[v2] = 0;\n return byte_4040;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char **a1, int a2) {\n long long v2;\n const char **v3;\n uint8_t *v4;\n const char *v5;\n v2 = a2;\n if (a2 > 0) {\n v2 = a2;\n v3 = a1;\n v4 = res_1;\n do {\n v5 = *v3++;\n *v4++ = v5[(int)strlen(v5) - 1];\n } while (&a1[a2] != v3);\n }\n res_1[v2] = 0;\n return res_1;\n}" + }, + { + "index": 425, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(char list1[][3][2], int list_length, char x) {\n int ctr = 0;\n for (int i = 0; i < list_length; i++) {\n for (int j = 0; j < 3; j++) {\n if (list1[i][j][0] == x) {\n ctr++;\n break;\n }\n }\n }\n return ctr;\n}", + "test": "int main() {\n\n char list1[4][3][2] = {{{'1', '\\0'}, {'3', '\\0'}}, {{'5', '\\0'}, {'7', '\\0'}}, {{'1', '\\0'}, {'1', '1'}}, {{'1', '\\0'}, {'1', '5'}, {'7', '\\0'}}};\n\n char list2[4][3][2] = {{{'A', '\\0'}, {'B', '\\0'}}, {{'A', '\\0'}, {'C', '\\0'}}, {{'A', '\\0'}, {'D', '\\0'}, {'E', '\\0'}}, {{'B', '\\0'}, {'C', '\\0'}, {'D', '\\0'}}};\n\n assert(func0(list1, 4, '1') == 3);\n\n assert(func0(list2, 4, 'A') == 3);\n\n assert(func0(list2, 4, 'E') == 1);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,%eax\nmov %al,-0x20(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11d4 \nmovl $0x0,-0x4(%rbp)\njmp 11ca \nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nadd %rax,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0x4(%rbp),%eax\ncltq\nmovzbl (%rdx,%rax,2),%eax\ncmp %al,-0x20(%rbp)\njne 11c6 \naddl $0x1,-0xc(%rbp)\njmp 11d0 \naddl $0x1,-0x4(%rbp)\ncmpl $0x2,-0x4(%rbp)\njle 1196 \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 118d \nmov -0xc(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov eax, edx\nmov [rbp+var_20], al\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_11D4\nloc_118D:\nmov [rbp+var_4], 0\njmp short loc_11CA\nloc_1196:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nadd rax, rax\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\ncdqe\nmovzx eax, byte ptr [rdx+rax*2]\ncmp [rbp+var_20], al\njnz short loc_11C6\nadd [rbp+var_C], 1\njmp short loc_11D0\nloc_11C6:\nadd [rbp+var_4], 1\nloc_11CA:\ncmp [rbp+var_4], 2\njle short loc_1196\nloc_11D0:\nadd [rbp+var_8], 1\nloc_11D4:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_118D\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, char a3)\n{\n unsigned int v4; // [rsp+14h] [rbp-Ch]\n int i; // [rsp+18h] [rbp-8h]\n int j; // [rsp+1Ch] [rbp-4h]\n\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = 0; j <= 2; ++j )\n {\n if ( a3 == *(_BYTE *)(a1 + 6LL * i + 2LL * j) )\n {\n ++v4;\n break;\n }\n }\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov eax, edx\nmov [rbp+var_20], al\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_11D4\nloc_118D:\nmov [rbp+var_4], 0\njmp short loc_11CA\nloc_1196:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nadd rax, rax\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\ncdqe\nmovzx eax, byte ptr [rdx+rax*2]\ncmp [rbp+var_20], al\njnz short loc_11C6\nadd [rbp+var_C], 1\njmp short loc_11D0\nloc_11C6:\nadd [rbp+var_4], 1\nloc_11CA:\ncmp [rbp+var_4], 2\njle short loc_1196\nloc_11D0:\nadd [rbp+var_8], 1\nloc_11D4:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_118D\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, char a3)\n{\n unsigned int v4; // [rsp+14h] [rbp-Ch]\n int i; // [rsp+18h] [rbp-8h]\n int j; // [rsp+1Ch] [rbp-4h]\n\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = 0; j <= 2; ++j )\n {\n if ( a3 == *(_BYTE *)(a1 + 6LL * i + 2LL * j) )\n {\n ++v4;\n break;\n }\n }\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, char a3) {\n unsigned int v4;\n int i;\n int j;\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = 0; j <= 2; ++j) {\n if (a3 == *(uint8_t *)(a1 + 6LL * i + 2LL * j)) {\n ++v4;\n break;\n }\n }\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, char a3) {\n unsigned int v4;\n int i;\n int j;\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = 0; j <= 2; ++j) {\n if (a3 == *(uint8_t *)(a1 + 6LL * i + 2LL * j)) {\n ++v4;\n break;\n }\n }\n }\n return v4;\n}" + }, + { + "index": 425, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(char list1[][3][2], int list_length, char x) {\n int ctr = 0;\n for (int i = 0; i < list_length; i++) {\n for (int j = 0; j < 3; j++) {\n if (list1[i][j][0] == x) {\n ctr++;\n break;\n }\n }\n }\n return ctr;\n}", + "test": "int main() {\n\n char list1[4][3][2] = {{{'1', '\\0'}, {'3', '\\0'}}, {{'5', '\\0'}, {'7', '\\0'}}, {{'1', '\\0'}, {'1', '1'}}, {{'1', '\\0'}, {'1', '5'}, {'7', '\\0'}}};\n\n char list2[4][3][2] = {{{'A', '\\0'}, {'B', '\\0'}}, {{'A', '\\0'}, {'C', '\\0'}}, {{'A', '\\0'}, {'D', '\\0'}, {'E', '\\0'}}, {{'B', '\\0'}, {'C', '\\0'}, {'D', '\\0'}}};\n\n assert(func0(list1, 4, '1') == 3);\n\n assert(func0(list2, 4, 'A') == 3);\n\n assert(func0(list2, 4, 'E') == 1);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11a6 \nmov %rdi,%rax\nlea -0x1(%rsi),%ecx\nlea (%rcx,%rcx,2),%rcx\nlea 0x6(%rdi,%rcx,2),%rsi\nmov $0x0,%edi\njmp 1193 \nadd $0x1,%edi\nadd $0x6,%rax\ncmp %rsi,%rax\nje 11ab \nmov %rax,%rcx\ncmp (%rax),%dl\nje 1187 \ncmp 0x2(%rax),%dl\nje 1187 \ncmp %dl,0x4(%rcx)\njne 118a \njmp 1187 \nmov $0x0,%edi\nmov %edi,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11A5\nmov rax, rdi\nmovsxd rsi, esi\nlea rcx, [rsi+rsi*2]\nlea rsi, [rdi+rcx*2]\nmov edi, 0\njmp short loc_1192\nloc_1186:\nadd edi, 1\nloc_1189:\nadd rax, 6\ncmp rsi, rax\njz short loc_11AA\nloc_1192:\nmov rcx, rax\ncmp dl, [rax]\njz short loc_1186\ncmp dl, [rax+2]\njz short loc_1186\ncmp [rcx+4], dl\njnz short loc_1189\njmp short loc_1186\nloc_11A5:\nmov edi, 0\nloc_11AA:\nmov eax, edi\nretn", + "ida_pseudo": "__int64 __fastcall func0(_BYTE *a1, int a2, char a3)\n{\n _BYTE *v3; // rax\n _BYTE *v4; // rsi\n unsigned int v5; // edi\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v3 = a1;\n v4 = &a1[6 * a2];\n v5 = 0;\n do\n {\n if ( a3 == *v3 || a3 == v3[2] || v3[4] == a3 )\n ++v5;\n v3 += 6;\n }\n while ( v4 != v3 );\n }\n return v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11A5\nmov rax, rdi\nmovsxd rsi, esi\nlea rcx, [rsi+rsi*2]\nlea rsi, [rdi+rcx*2]\nmov edi, 0\njmp short loc_1192\nloc_1186:\nadd edi, 1\nloc_1189:\nadd rax, 6\ncmp rsi, rax\njz short loc_11AA\nloc_1192:\nmov rcx, rax\ncmp dl, [rax]\njz short loc_1186\ncmp dl, [rax+2]\njz short loc_1186\ncmp [rcx+4], dl\njnz short loc_1189\njmp short loc_1186\nloc_11A5:\nmov edi, 0\nloc_11AA:\nmov eax, edi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_BYTE *a1, int a2, char a3)\n{\n _BYTE *v3; // rax\n _BYTE *v4; // rsi\n unsigned int v5; // edi\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v3 = a1;\n v4 = &a1[6 * a2];\n v5 = 0;\n do\n {\n if ( a3 == *v3 || a3 == v3[2] || v3[4] == a3 )\n ++v5;\n v3 += 6;\n }\n while ( v4 != v3 );\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint8_t *a1, int a2, char a3) {\n uint8_t *v3;\n uint8_t *v4;\n unsigned int v5;\n if (a2 <= 0) {\n return 0;\n } else {\n v3 = a1;\n v4 = &a1[6 * a2];\n v5 = 0;\n do {\n if (a3 == *v3 || a3 == v3[2] || v3[4] == a3) ++v5;\n v3 += 6;\n } while (v4 != v3);\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(uint8_t *a1, int a2, char a3) {\n uint8_t *v3;\n uint8_t *v4;\n unsigned int v5;\n if (a2 <= 0) {\n return 0;\n } else {\n v3 = a1;\n v4 = &a1[6 * a2];\n v5 = 0;\n do {\n if (a3 == *v3 || a3 == v3[2] || v3[4] == a3) ++v5;\n v3 += 6;\n } while (v4 != v3);\n }\n return v5;\n}" + }, + { + "index": 425, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(char list1[][3][2], int list_length, char x) {\n int ctr = 0;\n for (int i = 0; i < list_length; i++) {\n for (int j = 0; j < 3; j++) {\n if (list1[i][j][0] == x) {\n ctr++;\n break;\n }\n }\n }\n return ctr;\n}", + "test": "int main() {\n\n char list1[4][3][2] = {{{'1', '\\0'}, {'3', '\\0'}}, {{'5', '\\0'}, {'7', '\\0'}}, {{'1', '\\0'}, {'1', '1'}}, {{'1', '\\0'}, {'1', '5'}, {'7', '\\0'}}};\n\n char list2[4][3][2] = {{{'A', '\\0'}, {'B', '\\0'}}, {{'A', '\\0'}, {'C', '\\0'}}, {{'A', '\\0'}, {'D', '\\0'}, {'E', '\\0'}}, {{'B', '\\0'}, {'C', '\\0'}, {'D', '\\0'}}};\n\n assert(func0(list1, 4, '1') == 3);\n\n assert(func0(list2, 4, 'A') == 3);\n\n assert(func0(list2, 4, 'E') == 1);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1386 \nlea -0x1(%rsi),%eax\nxor %r8d,%r8d\nlea (%rax,%rax,2),%rax\nlea 0x6(%rdi,%rax,2),%rax\nnopw 0x0(%rax,%rax,1)\ncmp (%rdi),%dl\nje 1380 \ncmp 0x2(%rdi),%dl\nje 1380 \ncmp %dl,0x4(%rdi)\nje 1380 \nadd $0x6,%rdi\ncmp %rax,%rdi\njne 1360 \nmov %r8d,%eax\nretq\nnopl 0x0(%rax,%rax,1)\nadd $0x1,%r8d\njmp 136e \nxor %r8d,%r8d\nmov %r8d,%eax\nretq\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_12ED\nmovsxd rsi, esi\nxor ecx, ecx\nlea rax, [rsi+rsi*2]\nlea rax, [rdi+rax*2]\nnop dword ptr [rax]\nloc_12C8:\ncmp dl, [rdi]\njz short loc_12E8\ncmp dl, [rdi+2]\njz short loc_12E8\ncmp [rdi+4], dl\njz short loc_12E8\nloc_12D6:\nadd rdi, 6\ncmp rax, rdi\njnz short loc_12C8\nmov eax, ecx\nretn\nloc_12E8:\nadd ecx, 1\njmp short loc_12D6\nloc_12ED:\nxor ecx, ecx\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(_BYTE *a1, int a2, char a3)\n{\n unsigned int v3; // ecx\n _BYTE *v4; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v3 = 0;\n v4 = &a1[6 * a2];\n do\n {\n if ( a3 == *a1 || a3 == a1[2] || a1[4] == a3 )\n ++v3;\n a1 += 6;\n }\n while ( v4 != a1 );\n return v3;\n}", + "ida_strip_asm": "sub_12B0:\nendbr64\ntest esi, esi\njle short loc_12ED\nmovsxd rsi, esi\nxor ecx, ecx\nlea rax, [rsi+rsi*2]\nlea rax, [rdi+rax*2]\nnop dword ptr [rax]\nloc_12C8:\ncmp dl, [rdi]\njz short loc_12E8\ncmp dl, [rdi+2]\njz short loc_12E8\ncmp [rdi+4], dl\njz short loc_12E8\nloc_12D6:\nadd rdi, 6\ncmp rax, rdi\njnz short loc_12C8\nmov eax, ecx\nretn\nloc_12E8:\nadd ecx, 1\njmp short loc_12D6\nloc_12ED:\nxor ecx, ecx\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12B0(_BYTE *a1, int a2, char a3)\n{\n unsigned int v3; // ecx\n _BYTE *v4; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v3 = 0;\n v4 = &a1[6 * a2];\n do\n {\n if ( a3 == *a1 || a3 == a1[2] || a1[4] == a3 )\n ++v3;\n a1 += 6;\n }\n while ( v4 != a1 );\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12B0(uint8_t *a1, int a2, char a3) {\n unsigned int v3;\n uint8_t *v4;\n if (a2 <= 0) return 0LL;\n v3 = 0;\n v4 = &a1[6 * a2];\n do {\n if (a3 == *a1 || a3 == a1[2] || a1[4] == a3) ++v3;\n a1 += 6;\n } while (v4 != a1);\n return v3;\n}", + "ida_pseudo_norm": "long long func0(uint8_t *a1, int a2, char a3) {\n unsigned int v3;\n uint8_t *v4;\n if (a2 <= 0) return 0LL;\n v3 = 0;\n v4 = &a1[6 * a2];\n do {\n if (a3 == *a1 || a3 == a1[2] || a1[4] == a3) ++v3;\n a1 += 6;\n } while (v4 != a1);\n return v3;\n}" + }, + { + "index": 426, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int nums[], int size, int* odd_size) {\n static int odd_nums[100];\n int j = 0;\n for (int i = 0; i < size; i++) {\n if (nums[i] % 2 != 0) {\n odd_nums[j] = nums[i];\n j++;\n }\n }\n *odd_size = j;\n return odd_nums;\n}", + "test": "int main() {\n\n int odd_size;\n\n \n\n int array1[10] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n int result1[] = {1, 3, 5, 7, 9};\n\n int* filtered1 = func0(array1, 10, &odd_size);\n\n assert(odd_size == 5);\n\n for (int i = 0; i < odd_size; i++) {\n\n assert(filtered1[i] == result1[i]);\n\n }\n\n \n\n int array2[6] = {10, 20, 45, 67, 84, 93};\n\n int result2[] = {45, 67, 93};\n\n int* filtered2 = func0(array2, 6, &odd_size);\n\n assert(odd_size == 3);\n\n for (int i = 0; i < odd_size; i++) {\n\n assert(filtered2[i] == result2[i]);\n\n }\n\n \n\n int array3[7] = {5, 7, 9, 8, 6, 4, 3};\n\n int result3[] = {5, 7, 9, 3};\n\n int* filtered3 = func0(array3, 7, &odd_size);\n\n assert(odd_size == 4);\n\n for (int i = 0; i < odd_size; i++) {\n\n assert(filtered3[i] == result3[i]);\n\n }\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11df \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nand $0x1,%eax\ntest %eax,%eax\nje 11db \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov -0x8(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nlea 0x2e6c(%rip),%rdx\nmov %eax,(%rcx,%rdx,1)\naddl $0x1,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 118c \nmov -0x28(%rbp),%rax\nmov -0x8(%rbp),%edx\nmov %edx,(%rax)\nlea 0x2e49(%rip),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11DF\nloc_118C:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njz short loc_11DB\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nlea rdx, odd_nums_1\nmov [rcx+rdx], eax\nadd [rbp+var_8], 1\nloc_11DB:\nadd [rbp+var_4], 1\nloc_11DF:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_118C\nmov rax, [rbp+var_28]\nmov edx, [rbp+var_8]\nmov [rax], edx\nlea rax, odd_nums_1\npop rbp\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, _DWORD *a3)\n{\n int v4; // [rsp+20h] [rbp-8h]\n int i; // [rsp+24h] [rbp-4h]\n\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( (*(_DWORD *)(4LL * i + a1) & 1) != 0 )\n odd_nums_1[v4++] = *(_DWORD *)(4LL * i + a1);\n }\n *a3 = v4;\n return odd_nums_1;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11DF\nloc_118C:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njz short loc_11DB\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nlea rdx, unk_4040\nmov [rcx+rdx], eax\nadd [rbp+var_8], 1\nloc_11DB:\nadd [rbp+var_4], 1\nloc_11DF:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_118C\nmov rax, [rbp+var_28]\nmov edx, [rbp+var_8]\nmov [rax], edx\nlea rax, unk_4040\npop rbp\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1169(__int64 a1, int a2, _DWORD *a3)\n{\n int v4; // [rsp+20h] [rbp-8h]\n int i; // [rsp+24h] [rbp-4h]\n\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( (*(_DWORD *)(4LL * i + a1) & 1) != 0 )\n dword_4040[v4++] = *(_DWORD *)(4LL * i + a1);\n }\n *a3 = v4;\n return dword_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1169(long long a1, int a2, uint32_t *a3) {\n int v4;\n int i;\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n if ((*(uint32_t *)(4LL * i + a1) & 1) != 0)\n dword_4040[v4++] = *(uint32_t *)(4LL * i + a1);\n }\n *a3 = v4;\n return dword_4040;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, uint32_t *a3) {\n int v4;\n int i;\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n if ((*(uint32_t *)(4LL * i + a1) & 1) != 0)\n odd_nums_1[v4++] = *(uint32_t *)(4LL * i + a1);\n }\n *a3 = v4;\n return odd_nums_1;\n}" + }, + { + "index": 426, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int nums[], int size, int* odd_size) {\n static int odd_nums[100];\n int j = 0;\n for (int i = 0; i < size; i++) {\n if (nums[i] % 2 != 0) {\n odd_nums[j] = nums[i];\n j++;\n }\n }\n *odd_size = j;\n return odd_nums;\n}", + "test": "int main() {\n\n int odd_size;\n\n \n\n int array1[10] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n int result1[] = {1, 3, 5, 7, 9};\n\n int* filtered1 = func0(array1, 10, &odd_size);\n\n assert(odd_size == 5);\n\n for (int i = 0; i < odd_size; i++) {\n\n assert(filtered1[i] == result1[i]);\n\n }\n\n \n\n int array2[6] = {10, 20, 45, 67, 84, 93};\n\n int result2[] = {45, 67, 93};\n\n int* filtered2 = func0(array2, 6, &odd_size);\n\n assert(odd_size == 3);\n\n for (int i = 0; i < odd_size; i++) {\n\n assert(filtered2[i] == result2[i]);\n\n }\n\n \n\n int array3[7] = {5, 7, 9, 8, 6, 4, 3};\n\n int result3[] = {5, 7, 9, 3};\n\n int* filtered3 = func0(array3, 7, &odd_size);\n\n assert(odd_size == 4);\n\n for (int i = 0; i < odd_size; i++) {\n\n assert(filtered3[i] == result3[i]);\n\n }\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11a6 \nmov %rdi,%rax\nlea -0x1(%rsi),%ecx\nlea 0x4(%rdi,%rcx,4),%rdi\nmov $0x0,%esi\nlea 0x2eb8(%rip),%r9\njmp 1193 \nadd $0x4,%rax\ncmp %rdi,%rax\nje 11ab \nmov (%rax),%ecx\ntest $0x1,%cl\nje 118a \nmovslq %esi,%r8\nmov %ecx,(%r9,%r8,4)\nadd $0x1,%esi\njmp 118a \nmov $0x0,%esi\nmov %esi,(%rdx)\nlea 0x2e8c(%rip),%rax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11A5\nmov rax, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*4]\nmov esi, 0\nlea r9, odd_nums_1\njmp short loc_1192\nloc_1189:\nadd rax, 4\ncmp rax, rdi\njz short loc_11AA\nloc_1192:\nmov ecx, [rax]\ntest cl, 1\njz short loc_1189\nmovsxd r8, esi\nmov [r9+r8*4], ecx\nadd esi, 1\njmp short loc_1189\nloc_11A5:\nmov esi, 0\nloc_11AA:\nmov [rdx], esi\nlea rax, odd_nums_1\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(_DWORD *a1, int a2, _DWORD *a3)\n{\n _DWORD *v3; // rax\n _DWORD *v4; // rdi\n int v5; // esi\n\n if ( a2 <= 0 )\n {\n v5 = 0;\n }\n else\n {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n do\n {\n if ( (*v3 & 1) != 0 )\n odd_nums_1[v5++] = *v3;\n ++v3;\n }\n while ( v3 != v4 );\n }\n *a3 = v5;\n return odd_nums_1;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11A5\nmov rax, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*4]\nmov esi, 0\nlea r9, unk_4040\njmp short loc_1192\nloc_1189:\nadd rax, 4\ncmp rax, rdi\njz short loc_11AA\nloc_1192:\nmov ecx, [rax]\ntest cl, 1\njz short loc_1189\nmovsxd r8, esi\nmov [r9+r8*4], ecx\nadd esi, 1\njmp short loc_1189\nloc_11A5:\nmov esi, 0\nloc_11AA:\nmov [rdx], esi\nlea rax, unk_4040\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1169(_DWORD *a1, int a2, _DWORD *a3)\n{\n _DWORD *v3; // rax\n _DWORD *v4; // rdi\n int v5; // esi\n\n if ( a2 <= 0 )\n {\n v5 = 0;\n }\n else\n {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n do\n {\n if ( (*v3 & 1) != 0 )\n dword_4040[v5++] = *v3;\n ++v3;\n }\n while ( v3 != v4 );\n }\n *a3 = v5;\n return dword_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1169(uint32_t *a1, int a2, uint32_t *a3) {\n uint32_t *v3;\n uint32_t *v4;\n int v5;\n if (a2 <= 0) {\n v5 = 0;\n } else {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n do {\n if ((*v3 & 1) != 0) dword_4040[v5++] = *v3;\n ++v3;\n } while (v3 != v4);\n }\n *a3 = v5;\n return dword_4040;\n}", + "ida_pseudo_norm": "uint32_t *func0(uint32_t *a1, int a2, uint32_t *a3) {\n uint32_t *v3;\n uint32_t *v4;\n int v5;\n if (a2 <= 0) {\n v5 = 0;\n } else {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n do {\n if ((*v3 & 1) != 0) odd_nums_1[v5++] = *v3;\n ++v3;\n } while (v3 != v4);\n }\n *a3 = v5;\n return odd_nums_1;\n}" + }, + { + "index": 426, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int nums[], int size, int* odd_size) {\n static int odd_nums[100];\n int j = 0;\n for (int i = 0; i < size; i++) {\n if (nums[i] % 2 != 0) {\n odd_nums[j] = nums[i];\n j++;\n }\n }\n *odd_size = j;\n return odd_nums;\n}", + "test": "int main() {\n\n int odd_size;\n\n \n\n int array1[10] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n int result1[] = {1, 3, 5, 7, 9};\n\n int* filtered1 = func0(array1, 10, &odd_size);\n\n assert(odd_size == 5);\n\n for (int i = 0; i < odd_size; i++) {\n\n assert(filtered1[i] == result1[i]);\n\n }\n\n \n\n int array2[6] = {10, 20, 45, 67, 84, 93};\n\n int result2[] = {45, 67, 93};\n\n int* filtered2 = func0(array2, 6, &odd_size);\n\n assert(odd_size == 3);\n\n for (int i = 0; i < odd_size; i++) {\n\n assert(filtered2[i] == result2[i]);\n\n }\n\n \n\n int array3[7] = {5, 7, 9, 8, 6, 4, 3};\n\n int result3[] = {5, 7, 9, 3};\n\n int* filtered3 = func0(array3, 7, &odd_size);\n\n assert(odd_size == 4);\n\n for (int i = 0; i < odd_size; i++) {\n\n assert(filtered3[i] == result3[i]);\n\n }\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 14b8 \nlea -0x1(%rsi),%eax\nxor %ecx,%ecx\nlea 0x2bbc(%rip),%r9\nlea 0x4(%rdi,%rax,4),%rsi\nnopl 0x0(%rax)\nmov (%rdi),%eax\ntest $0x1,%al\nje 14a0 \nmovslq %ecx,%r8\nadd $0x1,%ecx\nmov %eax,(%r9,%r8,4)\nadd $0x4,%rdi\ncmp %rsi,%rdi\njne 1490 \nmov %ecx,(%rdx)\nlea 0x2b8e(%rip),%rax\nretq\nnopl 0x0(%rax,%rax,1)\nxor %ecx,%ecx\nlea 0x2b7f(%rip),%rax\nmov %ecx,(%rdx)\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_13F0\nmovsxd rsi, esi\nxor ecx, ecx\nlea r9, odd_nums_1\nlea rsi, [rdi+rsi*4]\nnop dword ptr [rax+rax+00000000h]\nloc_13D0:\nmov eax, [rdi]\ntest al, 1\njz short loc_13E0\nmovsxd r8, ecx\nadd ecx, 1\nmov [r9+r8*4], eax\nloc_13E0:\nadd rdi, 4\ncmp rdi, rsi\njnz short loc_13D0\nmov [rdx], ecx\nmov rax, r9\nretn\nloc_13F0:\nxor ecx, ecx\nlea r9, odd_nums_1\nmov [rdx], ecx\nmov rax, r9\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(_DWORD *a1, int a2, _DWORD *a3)\n{\n int v3; // ecx\n _DWORD *v4; // rsi\n __int64 v5; // r8\n\n if ( a2 <= 0 )\n {\n *a3 = 0;\n return odd_nums_1;\n }\n else\n {\n v3 = 0;\n v4 = &a1[a2];\n do\n {\n if ( (*a1 & 1) != 0 )\n {\n v5 = v3++;\n odd_nums_1[v5] = *a1;\n }\n ++a1;\n }\n while ( a1 != v4 );\n *a3 = v3;\n return odd_nums_1;\n }\n}", + "ida_strip_asm": "sub_13B0:\nendbr64\ntest esi, esi\njle short loc_13F0\nmovsxd rsi, esi\nxor ecx, ecx\nlea r9, unk_4040\nlea rsi, [rdi+rsi*4]\nnop dword ptr [rax+rax+00000000h]\nloc_13D0:\nmov eax, [rdi]\ntest al, 1\njz short loc_13E0\nmovsxd r8, ecx\nadd ecx, 1\nmov [r9+r8*4], eax\nloc_13E0:\nadd rdi, 4\ncmp rdi, rsi\njnz short loc_13D0\nmov [rdx], ecx\nmov rax, r9\nretn\nloc_13F0:\nxor ecx, ecx\nlea r9, unk_4040\nmov [rdx], ecx\nmov rax, r9\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_13B0(_DWORD *a1, int a2, _DWORD *a3)\n{\n int v3; // ecx\n _DWORD *v4; // rsi\n __int64 v5; // r8\n\n if ( a2 <= 0 )\n {\n *a3 = 0;\n return dword_4040;\n }\n else\n {\n v3 = 0;\n v4 = &a1[a2];\n do\n {\n if ( (*a1 & 1) != 0 )\n {\n v5 = v3++;\n dword_4040[v5] = *a1;\n }\n ++a1;\n }\n while ( a1 != v4 );\n *a3 = v3;\n return dword_4040;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_13B0(uint32_t *a1, int a2, uint32_t *a3) {\n int v3;\n uint32_t *v4;\n long long v5;\n if (a2 <= 0) {\n *a3 = 0;\n return dword_4040;\n } else {\n v3 = 0;\n v4 = &a1[a2];\n do {\n if ((*a1 & 1) != 0) {\n v5 = v3++;\n dword_4040[v5] = *a1;\n }\n ++a1;\n } while (a1 != v4);\n *a3 = v3;\n return dword_4040;\n }\n}", + "ida_pseudo_norm": "uint32_t *func0(uint32_t *a1, int a2, uint32_t *a3) {\n int v3;\n uint32_t *v4;\n long long v5;\n if (a2 <= 0) {\n *a3 = 0;\n return odd_nums_1;\n } else {\n v3 = 0;\n v4 = &a1[a2];\n do {\n if ((*a1 & 1) != 0) {\n v5 = v3++;\n odd_nums_1[v5] = *a1;\n }\n ++a1;\n } while (a1 != v4);\n *a3 = v3;\n return odd_nums_1;\n }\n}" + }, + { + "index": 427, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* dt) {\n static char new_date[11];\n int year, month, day;\n sscanf(dt, \"%4d-%2d-%2d\", &year, &month, &day);\n sprintf(new_date, \"%02d-%02d-%4d\", day, month, year);\n return new_date;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"2026-01-02\"), \"02-01-2026\") == 0);\n\n assert(strcmp(func0(\"2020-11-13\"), \"13-11-2020\") == 0);\n\n assert(strcmp(func0(\"2021-04-26\"), \"26-04-2021\") == 0);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x28(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea -0xc(%rbp),%rsi\nlea -0x10(%rbp),%rcx\nlea -0x14(%rbp),%rdx\nmov -0x28(%rbp),%rax\nmov %rsi,%r8\nlea 0xe06(%rip),%rsi\nmov %rax,%rdi\nmov $0x0,%eax\ncallq 10c0 <__isoc99_sscanf@plt>\nmov -0x14(%rbp),%ecx\nmov -0x10(%rbp),%edx\nmov -0xc(%rbp),%eax\nmov %ecx,%r8d\nmov %edx,%ecx\nmov %eax,%edx\nlea 0xdee(%rip),%rsi\nlea 0x2deb(%rip),%rdi\nmov $0x0,%eax\ncallq 10d0 \nlea 0x2dda(%rip),%rax\nmov -0x8(%rbp),%rdi\nxor %fs:0x28,%rdi\nje 1252 \ncallq 1090 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rsi, [rbp+var_C]\nlea rcx, [rbp+var_10]\nlea rdx, [rbp+var_14]\nmov rax, [rbp+var_28]\nmov r8, rsi\nlea rsi, a4d2d2d; \"%4d-%2d-%2d\"\nmov rdi, rax\nmov eax, 0\ncall ___isoc99_sscanf\nmov ecx, [rbp+var_14]\nmov edx, [rbp+var_10]\nmov eax, [rbp+var_C]\nmov r8d, ecx\nmov ecx, edx\nmov edx, eax\nlea rax, format; \"%02d-%02d-%4d\"\nmov rsi, rax; format\nlea rax, new_date_1\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rax, new_date_1\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1258\ncall ___stack_chk_fail\nlocret_1258:\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1)\n{\n int v2; // [rsp+1Ch] [rbp-14h] BYREF\n int v3; // [rsp+20h] [rbp-10h] BYREF\n int v4; // [rsp+24h] [rbp-Ch] BYREF\n unsigned __int64 v5; // [rsp+28h] [rbp-8h]\n\n v5 = __readfsqword(0x28u);\n __isoc99_sscanf(a1, \"%4d-%2d-%2d\", &v2, &v3, &v4);\n sprintf(new_date_1, \"%02d-%02d-%4d\", v4, v3, v2);\n return new_date_1;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rsi, [rbp+var_C]\nlea rcx, [rbp+var_10]\nlea rdx, [rbp+var_14]\nmov rax, [rbp+var_28]\nmov r8, rsi\nlea rsi, a4d2d2d; \"%4d-%2d-%2d\"\nmov rdi, rax\nmov eax, 0\ncall ___isoc99_sscanf\nmov ecx, [rbp+var_14]\nmov edx, [rbp+var_10]\nmov eax, [rbp+var_C]\nmov r8d, ecx\nmov ecx, edx\nmov edx, eax\nlea rax, format; \"%02d-%02d-%4d\"\nmov rsi, rax; format\nlea rax, s\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rax, s\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1258\ncall ___stack_chk_fail\nlocret_1258:\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11C9(__int64 a1)\n{\n int v2; // [rsp+1Ch] [rbp-14h] BYREF\n int v3; // [rsp+20h] [rbp-10h] BYREF\n int v4; // [rsp+24h] [rbp-Ch] BYREF\n unsigned __int64 v5; // [rsp+28h] [rbp-8h]\n\n v5 = __readfsqword(0x28u);\n __isoc99_sscanf(a1, \"%4d-%2d-%2d\", &v2, &v3, &v4);\n sprintf(s, \"%02d-%02d-%4d\", v4, v3, v2);\n return s;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char* sub_11C9(long long a1) {\n int v2;\n int v3;\n int v4;\n unsigned long long v5;\n v5 = __readfsqword(40u);\n __isoc99_sscanf(a1, \"%4d-%2d-%2d\", &v2, &v3, &v4);\n sprintf(s, \"%02d-%02d-%4d\", v4, v3, v2);\n return s;\n}", + "ida_pseudo_norm": "char* func0(long long a1) {\n int v2;\n int v3;\n int v4;\n unsigned long long v5;\n v5 = __readfsqword(40u);\n __isoc99_sscanf(a1, \"%4d-%2d-%2d\", &v2, &v3, &v4);\n sprintf(new_date_1, \"%02d-%02d-%4d\", v4, v3, v2);\n return new_date_1;\n}" + }, + { + "index": 427, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* dt) {\n static char new_date[11];\n int year, month, day;\n sscanf(dt, \"%4d-%2d-%2d\", &year, &month, &day);\n sprintf(new_date, \"%02d-%02d-%4d\", day, month, year);\n return new_date;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"2026-01-02\"), \"02-01-2026\") == 0);\n\n assert(strcmp(func0(\"2020-11-13\"), \"13-11-2020\") == 0);\n\n assert(strcmp(func0(\"2021-04-26\"), \"26-04-2021\") == 0);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nsub $0x20,%rsp\nmov $0x28,%ebx\nmov %fs:(%rbx),%rax\nmov %rax,0x18(%rsp)\nxor %eax,%eax\nlea 0x10(%rsp),%rcx\nlea 0xc(%rsp),%rdx\nlea 0x14(%rsp),%r8\nlea 0xe2c(%rip),%rsi\ncallq 10a0 <__isoc99_sscanf@plt>\nsub $0x8,%rsp\nmov 0x14(%rsp),%eax\npush %rax\nmov 0x20(%rsp),%r9d\nmov 0x24(%rsp),%r8d\nlea 0xe19(%rip),%rcx\nmov $0xb,%edx\nmov $0x1,%esi\nlea 0x2e10(%rip),%rdi\nmov $0x0,%eax\ncallq 10b0 <__sprintf_chk@plt>\nadd $0x10,%rsp\nmov 0x18(%rsp),%rax\nxor %fs:(%rbx),%rax\njne 122e \nlea 0x2df0(%rip),%rax\nadd $0x20,%rsp\npop %rbx\nretq\ncallq 1080 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbx\nsub rsp, 20h\nmov rax, fs:28h\nmov [rsp+28h+var_10], rax\nxor eax, eax\nlea rcx, [rsp+28h+var_18]\nlea rdx, [rsp+28h+var_1C]\nlea r8, [rsp+28h+var_14]\nlea rsi, a4d2d2d; \"%4d-%2d-%2d\"\ncall ___isoc99_sscanf\nsub rsp, 8\nmov eax, [rsp+30h+var_1C]\npush rax\nmov r9d, [rsp+38h+var_18]\nmov r8d, [rsp+38h+var_14]\nlea rcx, a02d02d4d; \"%02d-%02d-%4d\"\nmov edx, 0Bh\nmov esi, 2\nlea rbx, new_date_1\nmov rdi, rbx\nmov eax, 0\ncall ___sprintf_chk\nadd rsp, 10h\nmov rax, [rsp+28h+var_10]\nsub rax, fs:28h\njnz short loc_1252\nmov rax, rbx\nadd rsp, 20h\npop rbx\nretn\nloc_1252:\ncall ___stack_chk_fail", + "ida_pseudo": "void *__fastcall func0(__int64 a1)\n{\n int v2; // [rsp+Ch] [rbp-1Ch] BYREF\n int v3; // [rsp+10h] [rbp-18h] BYREF\n int v4; // [rsp+14h] [rbp-14h] BYREF\n unsigned __int64 v5; // [rsp+18h] [rbp-10h]\n\n v5 = __readfsqword(0x28u);\n __isoc99_sscanf(a1, \"%4d-%2d-%2d\", &v2, &v3, &v4);\n __sprintf_chk(&new_date_1, 2LL, 11LL, \"%02d-%02d-%4d\", v4, v3, v2);\n return &new_date_1;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbx\nsub rsp, 20h\nmov rax, fs:28h\nmov [rsp+28h+var_10], rax\nxor eax, eax\nlea rcx, [rsp+28h+var_18]\nlea rdx, [rsp+28h+var_1C]\nlea r8, [rsp+28h+var_14]\nlea rsi, a4d2d2d; \"%4d-%2d-%2d\"\ncall ___isoc99_sscanf\nsub rsp, 8\nmov eax, [rsp+30h+var_1C]\npush rax\nmov r9d, [rsp+38h+var_18]\nmov r8d, [rsp+38h+var_14]\nlea rcx, a02d02d4d; \"%02d-%02d-%4d\"\nmov edx, 0Bh\nmov esi, 2\nlea rbx, unk_4018\nmov rdi, rbx\nmov eax, 0\ncall ___sprintf_chk\nadd rsp, 10h\nmov rax, [rsp+28h+var_10]\nsub rax, fs:28h\njnz short loc_1252\nmov rax, rbx\nadd rsp, 20h\npop rbx\nretn\nloc_1252:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "void *__fastcall sub_11C9(__int64 a1)\n{\n int v2; // [rsp+Ch] [rbp-1Ch] BYREF\n int v3; // [rsp+10h] [rbp-18h] BYREF\n int v4; // [rsp+14h] [rbp-14h] BYREF\n unsigned __int64 v5; // [rsp+18h] [rbp-10h]\n\n v5 = __readfsqword(0x28u);\n __isoc99_sscanf(a1, \"%4d-%2d-%2d\", &v2, &v3, &v4);\n __sprintf_chk(&unk_4018, 2LL, 11LL, \"%02d-%02d-%4d\", v4, v3, v2);\n return &unk_4018;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void* sub_11C9(long long a1) {\n int v2;\n int v3;\n int v4;\n unsigned long long v5;\n v5 = __readfsqword(40u);\n __isoc99_sscanf(a1, \"%4d-%2d-%2d\", &v2, &v3, &v4);\n __sprintf_chk(&unk_4018, 2LL, 11LL, \"%02d-%02d-%4d\", v4, v3, v2);\n return &unk_4018;\n}", + "ida_pseudo_norm": "void* func0(long long a1) {\n int v2;\n int v3;\n int v4;\n unsigned long long v5;\n v5 = __readfsqword(40u);\n __isoc99_sscanf(a1, \"%4d-%2d-%2d\", &v2, &v3, &v4);\n __sprintf_chk(&new_date_1, 2LL, 11LL, \"%02d-%02d-%4d\", v4, v3, v2);\n return &new_date_1;\n}" + }, + { + "index": 427, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* dt) {\n static char new_date[11];\n int year, month, day;\n sscanf(dt, \"%4d-%2d-%2d\", &year, &month, &day);\n sprintf(new_date, \"%02d-%02d-%4d\", day, month, year);\n return new_date;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"2026-01-02\"), \"02-01-2026\") == 0);\n\n assert(strcmp(func0(\"2020-11-13\"), \"13-11-2020\") == 0);\n\n assert(strcmp(func0(\"2021-04-26\"), \"26-04-2021\") == 0);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x28,%rsp\nlea 0xd65(%rip),%rsi\nmov %fs:0x28,%rax\nmov %rax,0x18(%rsp)\nxor %eax,%eax\nlea 0x10(%rsp),%rcx\nlea 0xc(%rsp),%rdx\nlea 0x14(%rsp),%r8\ncallq 10a0 <__isoc99_sscanf@plt>\nsub $0x8,%rsp\nmov $0xb,%edx\nlea 0xd3d(%rip),%rcx\nmov 0x14(%rsp),%eax\nmov $0x1,%esi\nlea 0x2d35(%rip),%rdi\npush %rax\nmov 0x20(%rsp),%r9d\nxor %eax,%eax\nmov 0x24(%rsp),%r8d\ncallq 10b0 <__sprintf_chk@plt>\npop %rax\npop %rdx\nmov 0x18(%rsp),%rax\nxor %fs:0x28,%rax\njne 1313 \nlea 0x2d0a(%rip),%rax\nadd $0x28,%rsp\nretq\ncallq 1080 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nlea rsi, a4d2d2d; \"%4d-%2d-%2d\"\nlea rbx, new_date_1\nsub rsp, 20h\nmov rax, fs:28h\nmov [rsp+28h+var_10], rax\nxor eax, eax\nlea rcx, [rsp+28h+var_18]\nlea rdx, [rsp+28h+var_1C]\nlea r8, [rsp+28h+var_14]\ncall ___isoc99_sscanf\nsub rsp, 8\nmov edx, 0Bh\nmov rdi, rbx\nmov eax, [rsp+30h+var_1C]\nlea rcx, a02d02d4d; \"%02d-%02d-%4d\"\nmov esi, 2\npush rax\nmov r9d, [rsp+38h+var_18]\nxor eax, eax\nmov r8d, [rsp+38h+var_14]\ncall ___sprintf_chk\npop rax\npop rdx\nmov rax, [rsp+28h+var_10]\nsub rax, fs:28h\njnz short loc_1324\nadd rsp, 20h\nmov rax, rbx\npop rbx\nretn\nloc_1324:\ncall ___stack_chk_fail", + "ida_pseudo": "void *__fastcall func0(__int64 a1)\n{\n int v2; // [rsp+Ch] [rbp-1Ch] BYREF\n int v3; // [rsp+10h] [rbp-18h] BYREF\n int v4; // [rsp+14h] [rbp-14h] BYREF\n unsigned __int64 v5; // [rsp+18h] [rbp-10h]\n\n v5 = __readfsqword(0x28u);\n __isoc99_sscanf(a1, \"%4d-%2d-%2d\", &v2, &v3, &v4);\n __sprintf_chk(&new_date_1, 2LL, 11LL, \"%02d-%02d-%4d\", v4, v3, v2);\n return &new_date_1;\n}", + "ida_strip_asm": "sub_12A0:\nendbr64\npush rbx\nlea rsi, a4d2d2d; \"%4d-%2d-%2d\"\nlea rbx, unk_4018\nsub rsp, 20h\nmov rax, fs:28h\nmov [rsp+28h+var_10], rax\nxor eax, eax\nlea rcx, [rsp+28h+var_18]\nlea rdx, [rsp+28h+var_1C]\nlea r8, [rsp+28h+var_14]\ncall ___isoc99_sscanf\nsub rsp, 8\nmov edx, 0Bh\nmov rdi, rbx\nmov eax, [rsp+30h+var_1C]\nlea rcx, a02d02d4d; \"%02d-%02d-%4d\"\nmov esi, 2\npush rax\nmov r9d, [rsp+38h+var_18]\nxor eax, eax\nmov r8d, [rsp+38h+var_14]\ncall ___sprintf_chk\npop rax\npop rdx\nmov rax, [rsp+28h+var_10]\nsub rax, fs:28h\njnz short loc_1324\nadd rsp, 20h\nmov rax, rbx\npop rbx\nretn\nloc_1324:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "void *__fastcall sub_12A0(__int64 a1)\n{\n int v2; // [rsp+Ch] [rbp-1Ch] BYREF\n int v3; // [rsp+10h] [rbp-18h] BYREF\n int v4; // [rsp+14h] [rbp-14h] BYREF\n unsigned __int64 v5; // [rsp+18h] [rbp-10h]\n\n v5 = __readfsqword(0x28u);\n __isoc99_sscanf(a1, \"%4d-%2d-%2d\", &v2, &v3, &v4);\n __sprintf_chk(&unk_4018, 2LL, 11LL, \"%02d-%02d-%4d\", v4, v3, v2);\n return &unk_4018;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void* sub_12A0(long long a1) {\n int v2;\n int v3;\n int v4;\n unsigned long long v5;\n v5 = __readfsqword(40u);\n __isoc99_sscanf(a1, \"%4d-%2d-%2d\", &v2, &v3, &v4);\n __sprintf_chk(&unk_4018, 2LL, 11LL, \"%02d-%02d-%4d\", v4, v3, v2);\n return &unk_4018;\n}", + "ida_pseudo_norm": "void* func0(long long a1) {\n int v2;\n int v3;\n int v4;\n unsigned long long v5;\n v5 = __readfsqword(40u);\n __isoc99_sscanf(a1, \"%4d-%2d-%2d\", &v2, &v3, &v4);\n __sprintf_chk(&new_date_1, 2LL, 11LL, \"%02d-%02d-%4d\", v4, v3, v2);\n return &new_date_1;\n}" + }, + { + "index": 427, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* dt) {\n static char new_date[11];\n int year, month, day;\n sscanf(dt, \"%4d-%2d-%2d\", &year, &month, &day);\n sprintf(new_date, \"%02d-%02d-%4d\", day, month, year);\n return new_date;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"2026-01-02\"), \"02-01-2026\") == 0);\n\n assert(strcmp(func0(\"2020-11-13\"), \"13-11-2020\") == 0);\n\n assert(strcmp(func0(\"2021-04-26\"), \"26-04-2021\") == 0);\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x28,%rsp\nlea 0xd65(%rip),%rsi\nmov %fs:0x28,%rax\nmov %rax,0x18(%rsp)\nxor %eax,%eax\nlea 0x10(%rsp),%rcx\nlea 0xc(%rsp),%rdx\nlea 0x14(%rsp),%r8\ncallq 10a0 <__isoc99_sscanf@plt>\nsub $0x8,%rsp\nmov $0xb,%edx\nlea 0xd3d(%rip),%rcx\nmov 0x14(%rsp),%eax\nmov $0x1,%esi\nlea 0x2d35(%rip),%rdi\npush %rax\nmov 0x20(%rsp),%r9d\nxor %eax,%eax\nmov 0x24(%rsp),%r8d\ncallq 10b0 <__sprintf_chk@plt>\npop %rax\npop %rdx\nmov 0x18(%rsp),%rax\nxor %fs:0x28,%rax\njne 1313 \nlea 0x2d0a(%rip),%rax\nadd $0x28,%rsp\nretq\ncallq 1080 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nlea rsi, a4d2d2d; \"%4d-%2d-%2d\"\nlea rbx, new_date_1\nsub rsp, 20h\nmov rax, fs:28h\nmov [rsp+28h+var_10], rax\nxor eax, eax\nlea rcx, [rsp+28h+var_18]\nlea rdx, [rsp+28h+var_1C]\nlea r8, [rsp+28h+var_14]\ncall ___isoc99_sscanf\nsub rsp, 8\nmov edx, 0Bh\nmov rdi, rbx\nmov eax, [rsp+30h+var_1C]\nlea rcx, a02d02d4d; \"%02d-%02d-%4d\"\nmov esi, 2\npush rax\nmov r9d, [rsp+38h+var_18]\nxor eax, eax\nmov r8d, [rsp+38h+var_14]\ncall ___sprintf_chk\npop rax\npop rdx\nmov rax, [rsp+28h+var_10]\nsub rax, fs:28h\njnz short loc_1324\nadd rsp, 20h\nmov rax, rbx\npop rbx\nretn\nloc_1324:\ncall ___stack_chk_fail", + "ida_pseudo": "void *__fastcall func0(__int64 a1)\n{\n int v2; // [rsp+Ch] [rbp-1Ch] BYREF\n int v3; // [rsp+10h] [rbp-18h] BYREF\n int v4; // [rsp+14h] [rbp-14h] BYREF\n unsigned __int64 v5; // [rsp+18h] [rbp-10h]\n\n v5 = __readfsqword(0x28u);\n __isoc99_sscanf(a1, \"%4d-%2d-%2d\", &v2, &v3, &v4);\n __sprintf_chk(&new_date_1, 2LL, 11LL, \"%02d-%02d-%4d\", v4, v3, v2);\n return &new_date_1;\n}", + "ida_strip_asm": "sub_12A0:\nendbr64\npush rbx\nlea rsi, a4d2d2d; \"%4d-%2d-%2d\"\nlea rbx, unk_4018\nsub rsp, 20h\nmov rax, fs:28h\nmov [rsp+28h+var_10], rax\nxor eax, eax\nlea rcx, [rsp+28h+var_18]\nlea rdx, [rsp+28h+var_1C]\nlea r8, [rsp+28h+var_14]\ncall ___isoc99_sscanf\nsub rsp, 8\nmov edx, 0Bh\nmov rdi, rbx\nmov eax, [rsp+30h+var_1C]\nlea rcx, a02d02d4d; \"%02d-%02d-%4d\"\nmov esi, 2\npush rax\nmov r9d, [rsp+38h+var_18]\nxor eax, eax\nmov r8d, [rsp+38h+var_14]\ncall ___sprintf_chk\npop rax\npop rdx\nmov rax, [rsp+28h+var_10]\nsub rax, fs:28h\njnz short loc_1324\nadd rsp, 20h\nmov rax, rbx\npop rbx\nretn\nloc_1324:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "void *__fastcall sub_12A0(__int64 a1)\n{\n int v2; // [rsp+Ch] [rbp-1Ch] BYREF\n int v3; // [rsp+10h] [rbp-18h] BYREF\n int v4; // [rsp+14h] [rbp-14h] BYREF\n unsigned __int64 v5; // [rsp+18h] [rbp-10h]\n\n v5 = __readfsqword(0x28u);\n __isoc99_sscanf(a1, \"%4d-%2d-%2d\", &v2, &v3, &v4);\n __sprintf_chk(&unk_4018, 2LL, 11LL, \"%02d-%02d-%4d\", v4, v3, v2);\n return &unk_4018;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void* sub_12A0(long long a1) {\n int v2;\n int v3;\n int v4;\n unsigned long long v5;\n v5 = __readfsqword(40u);\n __isoc99_sscanf(a1, \"%4d-%2d-%2d\", &v2, &v3, &v4);\n __sprintf_chk(&unk_4018, 2LL, 11LL, \"%02d-%02d-%4d\", v4, v3, v2);\n return &unk_4018;\n}", + "ida_pseudo_norm": "void* func0(long long a1) {\n int v2;\n int v3;\n int v4;\n unsigned long long v5;\n v5 = __readfsqword(40u);\n __isoc99_sscanf(a1, \"%4d-%2d-%2d\", &v2, &v3, &v4);\n __sprintf_chk(&new_date_1, 2LL, 11LL, \"%02d-%02d-%4d\", v4, v3, v2);\n return &new_date_1;\n}" + }, + { + "index": 428, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "void func0(int my_list[], int length) {\n int gap = length / 2;\n while (gap > 0) {\n for (int i = gap; i < length; i++) {\n int current_item = my_list[i];\n int j = i;\n while (j >= gap && my_list[j - gap] > current_item) {\n my_list[j] = my_list[j - gap];\n j -= gap;\n }\n my_list[j] = current_item;\n }\n gap /= 2;\n }\n}", + "test": "int main() {\n\n int list1[] = {12, 23, 4, 5, 3, 2, 12, 81, 56, 95};\n\n int list2[] = {24, 22, 39, 34, 87, 73, 68};\n\n int list3[] = {32, 30, 16, 96, 82, 83, 74};\n\n\n\n func0(list1, 10);\n\n func0(list2, 7);\n\n func0(list3, 7);\n\n\n\n int sorted1[] = {2, 3, 4, 5, 12, 12, 23, 56, 81, 95};\n\n int sorted2[] = {22, 24, 34, 39, 68, 73, 87};\n\n int sorted3[] = {16, 30, 32, 74, 82, 83, 96};\n\n\n\n for (int i = 0; i < 10; i++) {\n\n assert(list1[i] == sorted1[i]);\n\n }\n\n for (int i = 0; i < 7; i++) {\n\n assert(list2[i] == sorted2[i]);\n\n }\n\n for (int i = 0; i < 7; i++) {\n\n assert(list3[i] == sorted3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov -0x1c(%rbp),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nmov %eax,-0x10(%rbp)\njmpq 124c \nmov -0x10(%rbp),%eax\nmov %eax,-0xc(%rbp)\njmpq 1231 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x4(%rbp)\nmov -0xc(%rbp),%eax\nmov %eax,-0x8(%rbp)\njmp 11ee \nmov -0x8(%rbp),%eax\nsub -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0x8(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\nmov -0x10(%rbp),%eax\nsub %eax,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x10(%rbp),%eax\njl 1214 \nmov -0x8(%rbp),%eax\nsub -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x4(%rbp)\njl 11b8 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0x4(%rbp),%eax\nmov %eax,(%rdx)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1197 \nmov -0x10(%rbp),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nmov %eax,-0x10(%rbp)\ncmpl $0x0,-0x10(%rbp)\njg 118c \npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov eax, [rbp+var_1C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_10], eax\njmp loc_124C\nloc_118C:\nmov eax, [rbp+var_10]\nmov [rbp+var_C], eax\njmp loc_1231\nloc_1197:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_C]\nmov [rbp+var_8], eax\njmp short loc_11EE\nloc_11B8:\nmov eax, [rbp+var_8]\nsub eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_10]\nsub [rbp+var_8], eax\nloc_11EE:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_10]\njl short loc_1214\nmov eax, [rbp+var_8]\nsub eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_4], eax\njl short loc_11B8\nloc_1214:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nadd [rbp+var_C], 1\nloc_1231:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl loc_1197\nmov eax, [rbp+var_10]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_10], eax\nloc_124C:\ncmp [rbp+var_10], 0\njg loc_118C\nnop\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 result; // rax\n int i; // [rsp+Ch] [rbp-10h]\n int j; // [rsp+10h] [rbp-Ch]\n int k; // [rsp+14h] [rbp-8h]\n int v6; // [rsp+18h] [rbp-4h]\n\n result = (unsigned int)(a2 / 2);\n for ( i = a2 / 2; i > 0; i /= 2 )\n {\n for ( j = i; j < a2; ++j )\n {\n v6 = *(_DWORD *)(4LL * j + a1);\n for ( k = j; k >= i && v6 < *(_DWORD *)(4LL * (k - i) + a1); k -= i )\n *(_DWORD *)(4LL * k + a1) = *(_DWORD *)(4LL * (k - i) + a1);\n *(_DWORD *)(a1 + 4LL * k) = v6;\n }\n result = (unsigned int)(i / 2);\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov eax, [rbp+var_1C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_10], eax\njmp loc_124C\nloc_118C:\nmov eax, [rbp+var_10]\nmov [rbp+var_C], eax\njmp loc_1231\nloc_1197:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_C]\nmov [rbp+var_8], eax\njmp short loc_11EE\nloc_11B8:\nmov eax, [rbp+var_8]\nsub eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_10]\nsub [rbp+var_8], eax\nloc_11EE:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_10]\njl short loc_1214\nmov eax, [rbp+var_8]\nsub eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_4], eax\njl short loc_11B8\nloc_1214:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nadd [rbp+var_C], 1\nloc_1231:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl loc_1197\nmov eax, [rbp+var_10]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_10], eax\nloc_124C:\ncmp [rbp+var_10], 0\njg loc_118C\nnop\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n __int64 result; // rax\n int i; // [rsp+Ch] [rbp-10h]\n int j; // [rsp+10h] [rbp-Ch]\n int k; // [rsp+14h] [rbp-8h]\n int v6; // [rsp+18h] [rbp-4h]\n\n result = (unsigned int)(a2 / 2);\n for ( i = a2 / 2; i > 0; i /= 2 )\n {\n for ( j = i; j < a2; ++j )\n {\n v6 = *(_DWORD *)(4LL * j + a1);\n for ( k = j; k >= i && v6 < *(_DWORD *)(4LL * (k - i) + a1); k -= i )\n *(_DWORD *)(4LL * k + a1) = *(_DWORD *)(4LL * (k - i) + a1);\n *(_DWORD *)(a1 + 4LL * k) = v6;\n }\n result = (unsigned int)(i / 2);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n long long result;\n int i;\n int j;\n int k;\n int v6;\n result = (unsigned int)(a2 / 2);\n for (i = a2 / 2; i > 0; i /= 2) {\n for (j = i; j < a2; ++j) {\n v6 = *(uint32_t *)(4LL * j + a1);\n for (k = j; k >= i && v6 < *(uint32_t *)(4LL * (k - i) + a1); k -= i)\n *(uint32_t *)(4LL * k + a1) = *(uint32_t *)(4LL * (k - i) + a1);\n *(uint32_t *)(a1 + 4LL * k) = v6;\n }\n result = (unsigned int)(i / 2);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long result;\n int i;\n int j;\n int k;\n int v6;\n result = (unsigned int)(a2 / 2);\n for (i = a2 / 2; i > 0; i /= 2) {\n for (j = i; j < a2; ++j) {\n v6 = *(uint32_t *)(4LL * j + a1);\n for (k = j; k >= i && v6 < *(uint32_t *)(4LL * (k - i) + a1); k -= i)\n *(uint32_t *)(4LL * k + a1) = *(uint32_t *)(4LL * (k - i) + a1);\n *(uint32_t *)(a1 + 4LL * k) = v6;\n }\n result = (unsigned int)(i / 2);\n }\n return result;\n}" + }, + { + "index": 428, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "void func0(int my_list[], int length) {\n int gap = length / 2;\n while (gap > 0) {\n for (int i = gap; i < length; i++) {\n int current_item = my_list[i];\n int j = i;\n while (j >= gap && my_list[j - gap] > current_item) {\n my_list[j] = my_list[j - gap];\n j -= gap;\n }\n my_list[j] = current_item;\n }\n gap /= 2;\n }\n}", + "test": "int main() {\n\n int list1[] = {12, 23, 4, 5, 3, 2, 12, 81, 56, 95};\n\n int list2[] = {24, 22, 39, 34, 87, 73, 68};\n\n int list3[] = {32, 30, 16, 96, 82, 83, 74};\n\n\n\n func0(list1, 10);\n\n func0(list2, 7);\n\n func0(list3, 7);\n\n\n\n int sorted1[] = {2, 3, 4, 5, 12, 12, 23, 56, 81, 95};\n\n int sorted2[] = {22, 24, 34, 39, 68, 73, 87};\n\n int sorted3[] = {16, 30, 32, 74, 82, 83, 96};\n\n\n\n for (int i = 0; i < 10; i++) {\n\n assert(list1[i] == sorted1[i]);\n\n }\n\n for (int i = 0; i < 7; i++) {\n\n assert(list2[i] == sorted2[i]);\n\n }\n\n for (int i = 0; i < 7; i++) {\n\n assert(list3[i] == sorted3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nmov %esi,%ebp\nshr $0x1f,%esi\nadd %ebp,%esi\nsar %esi\ncmp $0x1,%ebp\njg 11d6 \npop %rbx\npop %rbp\npop %r12\nretq\nmovslq %edi,%rdi\nmov %r8d,(%rbx,%rdi,4)\nadd $0x1,%r12d\nadd $0x4,%r11\ncmp %r12d,%ebp\nje 11c6 \nmov (%r11),%r8d\nmov %r11,%rdx\nmov %r12d,%eax\nmov %r12d,%edi\ncmp %r12d,%esi\njg 1187 \nmov %eax,%edi\nsub %esi,%eax\nmov (%rdx,%r9,1),%ecx\ncmp %r8d,%ecx\njle 1187 \nmov %ecx,(%rdx)\nadd %r10,%rdx\ncmp %esi,%eax\njge 11ac \nmov %eax,%edi\njmp 1187 \nmov %esi,%eax\nshr $0x1f,%eax\nadd %esi,%eax\nsar %eax\ncmp $0x1,%esi\njle 1182 \nmov %eax,%esi\ncmp %esi,%ebp\njle 11c6 \nmovslq %esi,%r9\nlea (%rbx,%r9,4),%r11\nmov %esi,%r10d\nneg %r10d\nmovslq %r10d,%r10\nshl $0x2,%r10\nneg %r9\nshl $0x2,%r9\nmov %esi,%r12d\njmp 119b \n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nmov ebp, esi\nshr esi, 1Fh\nadd esi, ebp\nsar esi, 1\ncmp ebp, 1\njg short loc_11D6\nloc_1182:\npop rbx\npop rbp\npop r12\nretn\nloc_1187:\nmovsxd rdi, edi\nmov [rbx+rdi*4], r8d\nadd r12d, 1\nadd r11, 4\ncmp ebp, r12d\njz short loc_11C6\nloc_119B:\nmov r8d, [r11]\nmov rdx, r11\nmov eax, r12d\nmov edi, r12d\ncmp esi, r12d\njg short loc_1187\nloc_11AC:\nmov edi, eax\nsub eax, esi\nmov ecx, [rdx+r9]\ncmp ecx, r8d\njle short loc_1187\nmov [rdx], ecx\nadd rdx, r10\ncmp eax, esi\njge short loc_11AC\nmov edi, eax\njmp short loc_1187\nloc_11C6:\nmov eax, esi\nshr eax, 1Fh\nadd eax, esi\nsar eax, 1\ncmp esi, 1\njle short loc_1182\nloc_11D4:\nmov esi, eax\nloc_11D6:\ncmp ebp, esi\njle short loc_11FA\nmovsxd r9, esi\nlea r11, [rbx+r9*4]\nmov r10d, esi\nneg r10d\nmovsxd r10, r10d\nshl r10, 2\nneg r9\nshl r9, 2\nmov r12d, esi\njmp short loc_119B\nloc_11FA:\nmov eax, esi\nshr eax, 1Fh\nadd eax, esi\nsar eax, 1\njmp short loc_11D4", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2)\n{\n int v4; // esi\n int v5; // r12d\n _DWORD *v6; // r11\n int v7; // r8d\n _DWORD *v8; // rdx\n int v9; // eax\n int v10; // edi\n int v11; // ecx\n int v12; // eax\n\n v4 = a2 / 2;\n if ( a2 > 1 )\n {\n while ( 1 )\n {\n if ( a2 <= v4 )\n {\n v12 = v4 / 2;\n }\n else\n {\n v6 = (_DWORD *)(a1 + 4LL * v4);\n v5 = v4;\n do\n {\n v7 = *v6;\n v8 = v6;\n v9 = v5;\n v10 = v5;\n if ( v4 <= v5 )\n {\n while ( 1 )\n {\n v10 = v9;\n v9 -= v4;\n v11 = v8[-v4];\n if ( v11 <= v7 )\n break;\n *v8 = v11;\n v8 -= v4;\n if ( v9 < v4 )\n {\n v10 = v9;\n break;\n }\n }\n }\n *(_DWORD *)(a1 + 4LL * v10) = v7;\n ++v5;\n ++v6;\n }\n while ( a2 != v5 );\n v12 = v4 / 2;\n if ( v4 <= 1 )\n return;\n }\n v4 = v12;\n }\n }\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nmov ebp, esi\nshr esi, 1Fh\nadd esi, ebp\nsar esi, 1\ncmp ebp, 1\njg short loc_11D6\nloc_1182:\npop rbx\npop rbp\npop r12\nretn\nloc_1187:\nmovsxd rdi, edi\nmov [rbx+rdi*4], r8d\nadd r12d, 1\nadd r11, 4\ncmp ebp, r12d\njz short loc_11C6\nloc_119B:\nmov r8d, [r11]\nmov rdx, r11\nmov eax, r12d\nmov edi, r12d\ncmp esi, r12d\njg short loc_1187\nloc_11AC:\nmov edi, eax\nsub eax, esi\nmov ecx, [rdx+r9]\ncmp ecx, r8d\njle short loc_1187\nmov [rdx], ecx\nadd rdx, r10\ncmp eax, esi\njge short loc_11AC\nmov edi, eax\njmp short loc_1187\nloc_11C6:\nmov eax, esi\nshr eax, 1Fh\nadd eax, esi\nsar eax, 1\ncmp esi, 1\njle short loc_1182\nloc_11D4:\nmov esi, eax\nloc_11D6:\ncmp ebp, esi\njle short loc_11FA\nmovsxd r9, esi\nlea r11, [rbx+r9*4]\nmov r10d, esi\nneg r10d\nmovsxd r10, r10d\nshl r10, 2\nneg r9\nshl r9, 2\nmov r12d, esi\njmp short loc_119B\nloc_11FA:\nmov eax, esi\nshr eax, 1Fh\nadd eax, esi\nsar eax, 1\njmp short loc_11D4", + "ida_strip_pseudo": "void __fastcall sub_1169(__int64 a1, int a2)\n{\n int v4; // esi\n int v5; // r12d\n _DWORD *v6; // r11\n int v7; // r8d\n _DWORD *v8; // rdx\n int v9; // eax\n int v10; // edi\n int v11; // ecx\n int v12; // eax\n\n v4 = a2 / 2;\n if ( a2 > 1 )\n {\n while ( 1 )\n {\n if ( a2 <= v4 )\n {\n v12 = v4 / 2;\n }\n else\n {\n v6 = (_DWORD *)(a1 + 4LL * v4);\n v5 = v4;\n do\n {\n v7 = *v6;\n v8 = v6;\n v9 = v5;\n v10 = v5;\n if ( v4 <= v5 )\n {\n while ( 1 )\n {\n v10 = v9;\n v9 -= v4;\n v11 = v8[-v4];\n if ( v11 <= v7 )\n break;\n *v8 = v11;\n v8 -= v4;\n if ( v9 < v4 )\n {\n v10 = v9;\n break;\n }\n }\n }\n *(_DWORD *)(a1 + 4LL * v10) = v7;\n ++v5;\n ++v6;\n }\n while ( a2 != v5 );\n v12 = v4 / 2;\n if ( v4 <= 1 )\n return;\n }\n v4 = v12;\n }\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1169(long long a1, int a2) {\n int v4;\n int v5;\n uint32_t *v6;\n int v7;\n uint32_t *v8;\n int v9;\n int v10;\n int v11;\n int v12;\n v4 = a2 / 2;\n if (a2 > 1) {\n while (1) {\n if (a2 <= v4) {\n v12 = v4 / 2;\n } else {\n v6 = (uint32_t *)(a1 + 4LL * v4);\n v5 = v4;\n do {\n v7 = *v6;\n v8 = v6;\n v9 = v5;\n v10 = v5;\n if (v4 <= v5) {\n while (1) {\n v10 = v9;\n v9 -= v4;\n v11 = v8[-v4];\n if (v11 <= v7) break;\n *v8 = v11;\n v8 -= v4;\n if (v9 < v4) {\n v10 = v9;\n break;\n }\n }\n }\n *(uint32_t *)(a1 + 4LL * v10) = v7;\n ++v5;\n ++v6;\n } while (a2 != v5);\n v12 = v4 / 2;\n if (v4 <= 1) return;\n }\n v4 = v12;\n }\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2) {\n int v4;\n int v5;\n uint32_t *v6;\n int v7;\n uint32_t *v8;\n int v9;\n int v10;\n int v11;\n int v12;\n v4 = a2 / 2;\n if (a2 > 1) {\n while (1) {\n if (a2 <= v4) {\n v12 = v4 / 2;\n } else {\n v6 = (uint32_t *)(a1 + 4LL * v4);\n v5 = v4;\n do {\n v7 = *v6;\n v8 = v6;\n v9 = v5;\n v10 = v5;\n if (v4 <= v5) {\n while (1) {\n v10 = v9;\n v9 -= v4;\n v11 = v8[-v4];\n if (v11 <= v7) break;\n *v8 = v11;\n v8 -= v4;\n if (v9 < v4) {\n v10 = v9;\n break;\n }\n }\n }\n *(uint32_t *)(a1 + 4LL * v10) = v7;\n ++v5;\n ++v6;\n } while (a2 != v5);\n v12 = v4 / 2;\n if (v4 <= 1) return;\n }\n v4 = v12;\n }\n }\n}" + }, + { + "index": 428, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "void func0(int my_list[], int length) {\n int gap = length / 2;\n while (gap > 0) {\n for (int i = gap; i < length; i++) {\n int current_item = my_list[i];\n int j = i;\n while (j >= gap && my_list[j - gap] > current_item) {\n my_list[j] = my_list[j - gap];\n j -= gap;\n }\n my_list[j] = current_item;\n }\n gap /= 2;\n }\n}", + "test": "int main() {\n\n int list1[] = {12, 23, 4, 5, 3, 2, 12, 81, 56, 95};\n\n int list2[] = {24, 22, 39, 34, 87, 73, 68};\n\n int list3[] = {32, 30, 16, 96, 82, 83, 74};\n\n\n\n func0(list1, 10);\n\n func0(list2, 7);\n\n func0(list3, 7);\n\n\n\n int sorted1[] = {2, 3, 4, 5, 12, 12, 23, 56, 81, 95};\n\n int sorted2[] = {22, 24, 34, 39, 68, 73, 87};\n\n int sorted3[] = {16, 30, 32, 74, 82, 83, 96};\n\n\n\n for (int i = 0; i < 10; i++) {\n\n assert(list1[i] == sorted1[i]);\n\n }\n\n for (int i = 0; i < 7; i++) {\n\n assert(list2[i] == sorted2[i]);\n\n }\n\n for (int i = 0; i < 7; i++) {\n\n assert(list3[i] == sorted3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov %esi,%r8d\nshr $0x1f,%r8d\nadd %esi,%r8d\nsar %r8d\ncmp $0x1,%esi\njle 14f4 \npush %r14\nmov %esi,%r14d\npush %r13\nmov %rdi,%r13\npush %r12\npush %rbp\npush %rbx\nnopl 0x0(%rax,%rax,1)\ncmp %r8d,%r14d\njle 14cd \nmov %r8d,%r9d\nmovslq %r8d,%r12\nmov %r8d,%ebp\nneg %r9d\nlea 0x0(%r13,%r12,4),%rbx\nneg %r12\nmovslq %r9d,%r9\nshl $0x2,%r12\nshl $0x2,%r9\nnopl 0x0(%rax)\nmov (%rbx),%r10d\nlea (%rbx,%r12,1),%rax\nmov %rbx,%rcx\nmov %ebp,%edx\njmp 14ae \nnopw %cs:0x0(%rax,%rax,1)\nmov %esi,(%rcx)\nadd %r9,%rax\nlea (%rdi,%r9,1),%rcx\ncmp %r8d,%edx\njl 14e0 \nmov (%rax),%esi\nsub %r8d,%edx\nmov %rax,%r11\nmov %rcx,%rdi\ncmp %r10d,%esi\njg 14a0 \nadd $0x1,%ebp\nmov %r10d,(%rdi)\nadd $0x4,%rbx\ncmp %ebp,%r14d\njne 1488 \nsar %r8d\njne 1460 \npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopl 0x0(%rax,%rax,1)\nmov %r11,%rdi\nadd $0x1,%ebp\nadd $0x4,%rbx\nmov %r10d,(%rdi)\ncmp %ebp,%r14d\njne 1488 \njmp 14cd \nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmov r8d, esi\npush r14\nshr r8d, 1Fh\npush r13\nmov r13d, esi\nadd r8d, esi\npush r12\nmov r12, rdi\npush rbp\nsar r8d, 1\npush rbx\ncmp esi, 1\njle short loc_1433\nnop dword ptr [rax+00h]\nloc_13B8:\ncmp r13d, r8d\njle loc_1455\nmov r9d, r8d\nmovsxd rbp, r8d\nmov r14d, r8d\nneg r9d\nshl rbp, 2\nmovsxd r9, r9d\nlea rbx, [r12+rbp]\nshl r9, 2\nnop dword ptr [rax+00h]\nloc_13E0:\nmov r10d, [rbx]\nmov rdi, rbx\ncmp r8d, r14d\njg short loc_141E\nmov rax, rbx\nmov rcx, rbx\nmov edx, r14d\nsub rax, rbp\njmp short loc_140E\nloc_1400:\nmov [rcx], esi\nadd rax, r9\nlea rcx, [rdi+r9]\ncmp edx, r8d\njl short loc_1440\nloc_140E:\nmov esi, [rax]\nsub edx, r8d\nmov r11, rax\nmov rdi, rcx\ncmp esi, r10d\njg short loc_1400\nloc_141E:\nadd r14d, 1\nmov [rdi], r10d\nadd rbx, 4\ncmp r13d, r14d\njnz short loc_13E0\nloc_142E:\nsar r8d, 1\njnz short loc_13B8\nloc_1433:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1440:\nmov rdi, r11\nadd r14d, 1\nadd rbx, 4\nmov [rdi], r10d\ncmp r13d, r14d\njnz short loc_13E0\njmp short loc_142E\nloc_1455:\nsar r8d, 1\njmp loc_13B8", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2)\n{\n int v3; // r8d\n int v4; // r14d\n __int64 v5; // rbp\n _DWORD *v6; // rbx\n __int64 v7; // r9\n int v8; // r10d\n _DWORD *v9; // rdi\n _DWORD *v10; // rcx\n int v11; // edx\n _DWORD *v12; // rax\n _DWORD *v13; // r11\n\n v3 = a2 / 2;\n if ( a2 > 1 )\n {\n do\n {\n while ( a2 <= v3 )\n v3 >>= 1;\n v4 = v3;\n v5 = 4LL * v3;\n v6 = (_DWORD *)(a1 + v5);\n v7 = 4LL * -v3;\n do\n {\nLABEL_4:\n v8 = *v6;\n v9 = v6;\n if ( v3 <= v4 )\n {\n v10 = v6;\n v11 = v4;\n v12 = &v6[v5 / 0xFFFFFFFFFFFFFFFCLL];\n while ( 1 )\n {\n v11 -= v3;\n v13 = v12;\n v9 = v10;\n if ( *v12 <= v8 )\n break;\n *v10 = *v12;\n v12 = (_DWORD *)((char *)v12 + v7);\n v10 = (_DWORD *)((char *)v10 + v7);\n if ( v11 < v3 )\n {\n ++v4;\n ++v6;\n *v13 = v8;\n if ( a2 != v4 )\n goto LABEL_4;\n goto LABEL_9;\n }\n }\n }\n ++v4;\n *v9 = v8;\n ++v6;\n }\n while ( a2 != v4 );\nLABEL_9:\n v3 >>= 1;\n }\n while ( v3 );\n }\n}", + "ida_strip_asm": "sub_1390:\nendbr64\nmov r8d, esi\npush r14\nshr r8d, 1Fh\npush r13\nmov r13d, esi\nadd r8d, esi\npush r12\nmov r12, rdi\npush rbp\nsar r8d, 1\npush rbx\ncmp esi, 1\njle short loc_1433\nnop dword ptr [rax+00h]\nloc_13B8:\ncmp r13d, r8d\njle loc_1455\nmov r9d, r8d\nmovsxd rbp, r8d\nmov r14d, r8d\nneg r9d\nshl rbp, 2\nmovsxd r9, r9d\nlea rbx, [r12+rbp]\nshl r9, 2\nnop dword ptr [rax+00h]\nloc_13E0:\nmov r10d, [rbx]\nmov rdi, rbx\ncmp r8d, r14d\njg short loc_141E\nmov rax, rbx\nmov rcx, rbx\nmov edx, r14d\nsub rax, rbp\njmp short loc_140E\nloc_1400:\nmov [rcx], esi\nadd rax, r9\nlea rcx, [rdi+r9]\ncmp edx, r8d\njl short loc_1440\nloc_140E:\nmov esi, [rax]\nsub edx, r8d\nmov r11, rax\nmov rdi, rcx\ncmp esi, r10d\njg short loc_1400\nloc_141E:\nadd r14d, 1\nmov [rdi], r10d\nadd rbx, 4\ncmp r13d, r14d\njnz short loc_13E0\nloc_142E:\nsar r8d, 1\njnz short loc_13B8\nloc_1433:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1440:\nmov rdi, r11\nadd r14d, 1\nadd rbx, 4\nmov [rdi], r10d\ncmp r13d, r14d\njnz short loc_13E0\njmp short loc_142E\nloc_1455:\nsar r8d, 1\njmp loc_13B8", + "ida_strip_pseudo": "void __fastcall sub_1390(__int64 a1, int a2)\n{\n int v3; // r8d\n int v4; // r14d\n __int64 v5; // rbp\n _DWORD *v6; // rbx\n __int64 v7; // r9\n int v8; // r10d\n _DWORD *v9; // rdi\n _DWORD *v10; // rcx\n int v11; // edx\n _DWORD *v12; // rax\n _DWORD *v13; // r11\n\n v3 = a2 / 2;\n if ( a2 > 1 )\n {\n do\n {\n while ( a2 <= v3 )\n v3 >>= 1;\n v4 = v3;\n v5 = 4LL * v3;\n v6 = (_DWORD *)(a1 + v5);\n v7 = 4LL * -v3;\n do\n {\nLABEL_4:\n v8 = *v6;\n v9 = v6;\n if ( v3 <= v4 )\n {\n v10 = v6;\n v11 = v4;\n v12 = &v6[v5 / 0xFFFFFFFFFFFFFFFCLL];\n while ( 1 )\n {\n v11 -= v3;\n v13 = v12;\n v9 = v10;\n if ( *v12 <= v8 )\n break;\n *v10 = *v12;\n v12 = (_DWORD *)((char *)v12 + v7);\n v10 = (_DWORD *)((char *)v10 + v7);\n if ( v11 < v3 )\n {\n ++v4;\n ++v6;\n *v13 = v8;\n if ( a2 != v4 )\n goto LABEL_4;\n goto LABEL_9;\n }\n }\n }\n ++v4;\n *v9 = v8;\n ++v6;\n }\n while ( a2 != v4 );\nLABEL_9:\n v3 >>= 1;\n }\n while ( v3 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1390(long long a1, int a2) {\n int v3;\n int v4;\n long long v5;\n uint32_t *v6;\n long long v7;\n int v8;\n uint32_t *v9;\n uint32_t *v10;\n int v11;\n uint32_t *v12;\n uint32_t *v13;\n v3 = a2 / 2;\n if (a2 > 1) {\n do {\n while (a2 <= v3) v3 >>= 1;\n v4 = v3;\n v5 = 4LL * v3;\n v6 = (uint32_t *)(a1 + v5);\n v7 = 4LL * -v3;\n do {\n LABEL_4:\n v8 = *v6;\n v9 = v6;\n if (v3 <= v4) {\n v10 = v6;\n v11 = v4;\n v12 = &v6[v5 / 18446744073709551612LL];\n while (1) {\n v11 -= v3;\n v13 = v12;\n v9 = v10;\n if (*v12 <= v8) break;\n *v10 = *v12;\n v12 = (uint32_t *)((char *)v12 + v7);\n v10 = (uint32_t *)((char *)v10 + v7);\n if (v11 < v3) {\n ++v4;\n ++v6;\n *v13 = v8;\n if (a2 != v4) goto LABEL_4;\n goto LABEL_9;\n }\n }\n }\n ++v4;\n *v9 = v8;\n ++v6;\n } while (a2 != v4);\n LABEL_9:\n v3 >>= 1;\n } while (v3);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2) {\n int v3;\n int v4;\n long long v5;\n uint32_t *v6;\n long long v7;\n int v8;\n uint32_t *v9;\n uint32_t *v10;\n int v11;\n uint32_t *v12;\n uint32_t *v13;\n v3 = a2 / 2;\n if (a2 > 1) {\n do {\n while (a2 <= v3) v3 >>= 1;\n v4 = v3;\n v5 = 4LL * v3;\n v6 = (uint32_t *)(a1 + v5);\n v7 = 4LL * -v3;\n do {\n LABEL_4:\n v8 = *v6;\n v9 = v6;\n if (v3 <= v4) {\n v10 = v6;\n v11 = v4;\n v12 = &v6[v5 / 18446744073709551612LL];\n while (1) {\n v11 -= v3;\n v13 = v12;\n v9 = v10;\n if (*v12 <= v8) break;\n *v10 = *v12;\n v12 = (uint32_t *)((char *)v12 + v7);\n v10 = (uint32_t *)((char *)v10 + v7);\n if (v11 < v3) {\n ++v4;\n ++v6;\n *v13 = v8;\n if (a2 != v4) goto LABEL_4;\n goto LABEL_9;\n }\n }\n }\n ++v4;\n *v9 = v8;\n ++v6;\n } while (a2 != v4);\n LABEL_9:\n v3 >>= 1;\n } while (v3);\n }\n}" + }, + { + "index": 428, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "void func0(int my_list[], int length) {\n int gap = length / 2;\n while (gap > 0) {\n for (int i = gap; i < length; i++) {\n int current_item = my_list[i];\n int j = i;\n while (j >= gap && my_list[j - gap] > current_item) {\n my_list[j] = my_list[j - gap];\n j -= gap;\n }\n my_list[j] = current_item;\n }\n gap /= 2;\n }\n}", + "test": "int main() {\n\n int list1[] = {12, 23, 4, 5, 3, 2, 12, 81, 56, 95};\n\n int list2[] = {24, 22, 39, 34, 87, 73, 68};\n\n int list3[] = {32, 30, 16, 96, 82, 83, 74};\n\n\n\n func0(list1, 10);\n\n func0(list2, 7);\n\n func0(list3, 7);\n\n\n\n int sorted1[] = {2, 3, 4, 5, 12, 12, 23, 56, 81, 95};\n\n int sorted2[] = {22, 24, 34, 39, 68, 73, 87};\n\n int sorted3[] = {16, 30, 32, 74, 82, 83, 96};\n\n\n\n for (int i = 0; i < 10; i++) {\n\n assert(list1[i] == sorted1[i]);\n\n }\n\n for (int i = 0; i < 7; i++) {\n\n assert(list2[i] == sorted2[i]);\n\n }\n\n for (int i = 0; i < 7; i++) {\n\n assert(list3[i] == sorted3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nmov %esi,%r8d\nshr $0x1f,%r8d\nadd %esi,%r8d\nsar %r8d\ncmp $0x1,%esi\njle 1514 \npush %r14\nmov %esi,%r14d\npush %r13\nmov %rdi,%r13\npush %r12\npush %rbp\npush %rbx\nnopl 0x0(%rax,%rax,1)\ncmp %r8d,%r14d\njle 14ed \nmov %r8d,%r9d\nmovslq %r8d,%r12\nmov %r8d,%ebp\nneg %r9d\nlea 0x0(%r13,%r12,4),%rbx\nneg %r12\nmovslq %r9d,%r9\nshl $0x2,%r12\nshl $0x2,%r9\nnopl 0x0(%rax)\nmov (%rbx),%r10d\nlea (%r12,%rbx,1),%rax\nmov %rbx,%rcx\nmov %ebp,%edx\njmp 14ce \nnopw %cs:0x0(%rax,%rax,1)\nmov %esi,(%rcx)\nadd %r9,%rax\nlea (%rcx,%r9,1),%rcx\ncmp %edx,%r8d\njg 1500 \nmov (%rax),%esi\nsub %r8d,%edx\nmov %rax,%r11\nmov %rcx,%rdi\ncmp %r10d,%esi\njg 14c0 \nadd $0x1,%ebp\nmov %r10d,(%rdi)\nadd $0x4,%rbx\ncmp %ebp,%r14d\njne 14a8 \nsar %r8d\njne 1480 \npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopl 0x0(%rax,%rax,1)\nmov %r11,%rdi\nadd $0x1,%ebp\nadd $0x4,%rbx\nmov %r10d,(%rdi)\ncmp %ebp,%r14d\njne 14a8 \njmp 14ed \nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmov ecx, esi\npush r13\nshr ecx, 1Fh\npush r12\nmov r12d, esi\nadd ecx, esi\npush rbp\nmov rbp, rdi\npush rbx\nsar ecx, 1\ncmp esi, 1\njle short loc_13F7\nxchg ax, ax\nloc_13A0:\ncmp r12d, ecx\njle short loc_1413\nmovsxd r9, ecx\nmov r13d, ecx\nshl r9, 2\nlea rbx, [rbp+r9+0]\nloc_13B4:\nmov rax, rbx\nmov r10d, [rbx]\nmov rsi, rbx\nmov edx, r13d\nsub rax, r9\njmp short loc_13D4\nloc_13C8:\nmov [rsi], edi\nsub rax, r9\nsub rsi, r9\ncmp ecx, edx\njg short loc_13FE\nloc_13D4:\nmov edi, [rax]\nsub edx, ecx\nmov r11, rax\nmov r8, rsi\ncmp edi, r10d\njg short loc_13C8\nadd r13d, 1\nmov [r8], r10d\nadd rbx, 4\ncmp r12d, r13d\njnz short loc_13B4\nloc_13F3:\nsar ecx, 1\njnz short loc_13A0\nloc_13F7:\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_13FE:\nmov r8, r11\nadd r13d, 1\nadd rbx, 4\nmov [r8], r10d\ncmp r12d, r13d\njnz short loc_13B4\njmp short loc_13F3\nloc_1413:\nsar ecx, 1\njmp short loc_13A0", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2)\n{\n int v3; // ecx\n int v4; // r13d\n __int64 v5; // r9\n _DWORD *v6; // rbx\n int v7; // r10d\n _DWORD *v8; // rsi\n int v9; // edx\n _DWORD *v10; // rax\n _DWORD *v11; // r11\n\n v3 = a2 / 2;\n if ( a2 > 1 )\n {\n do\n {\n while ( a2 <= v3 )\n v3 >>= 1;\n v4 = v3;\n v5 = 4LL * v3;\n v6 = (_DWORD *)(a1 + v5);\nLABEL_4:\n while ( 2 )\n {\n v7 = *v6;\n v8 = v6;\n v9 = v4;\n v10 = &v6[v5 / 0xFFFFFFFFFFFFFFFCLL];\n do\n {\n v9 -= v3;\n v11 = v10;\n if ( *v10 <= v7 )\n {\n ++v4;\n *v8 = v7;\n ++v6;\n if ( a2 != v4 )\n goto LABEL_4;\n goto LABEL_8;\n }\n *v8 = *v10;\n v10 = (_DWORD *)((char *)v10 - v5);\n v8 = (_DWORD *)((char *)v8 - v5);\n }\n while ( v3 <= v9 );\n ++v4;\n ++v6;\n *v11 = v7;\n if ( a2 != v4 )\n continue;\n break;\n }\nLABEL_8:\n v3 >>= 1;\n }\n while ( v3 );\n }\n}", + "ida_strip_asm": "sub_1380:\nendbr64\nmov ecx, esi\npush r13\nshr ecx, 1Fh\npush r12\nmov r12d, esi\nadd ecx, esi\npush rbp\nmov rbp, rdi\npush rbx\nsar ecx, 1\ncmp esi, 1\njle short loc_13F7\nxchg ax, ax\nloc_13A0:\ncmp r12d, ecx\njle short loc_1413\nmovsxd r9, ecx\nmov r13d, ecx\nshl r9, 2\nlea rbx, [rbp+r9+0]\nloc_13B4:\nmov rax, rbx\nmov r10d, [rbx]\nmov rsi, rbx\nmov edx, r13d\nsub rax, r9\njmp short loc_13D4\nloc_13C8:\nmov [rsi], edi\nsub rax, r9\nsub rsi, r9\ncmp ecx, edx\njg short loc_13FE\nloc_13D4:\nmov edi, [rax]\nsub edx, ecx\nmov r11, rax\nmov r8, rsi\ncmp edi, r10d\njg short loc_13C8\nadd r13d, 1\nmov [r8], r10d\nadd rbx, 4\ncmp r12d, r13d\njnz short loc_13B4\nloc_13F3:\nsar ecx, 1\njnz short loc_13A0\nloc_13F7:\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_13FE:\nmov r8, r11\nadd r13d, 1\nadd rbx, 4\nmov [r8], r10d\ncmp r12d, r13d\njnz short loc_13B4\njmp short loc_13F3\nloc_1413:\nsar ecx, 1\njmp short loc_13A0", + "ida_strip_pseudo": "void __fastcall sub_1380(__int64 a1, int a2)\n{\n int v3; // ecx\n int v4; // r13d\n __int64 v5; // r9\n _DWORD *v6; // rbx\n int v7; // r10d\n _DWORD *v8; // rsi\n int v9; // edx\n _DWORD *v10; // rax\n _DWORD *v11; // r11\n\n v3 = a2 / 2;\n if ( a2 > 1 )\n {\n do\n {\n while ( a2 <= v3 )\n v3 >>= 1;\n v4 = v3;\n v5 = 4LL * v3;\n v6 = (_DWORD *)(a1 + v5);\nLABEL_4:\n while ( 2 )\n {\n v7 = *v6;\n v8 = v6;\n v9 = v4;\n v10 = &v6[v5 / 0xFFFFFFFFFFFFFFFCLL];\n do\n {\n v9 -= v3;\n v11 = v10;\n if ( *v10 <= v7 )\n {\n ++v4;\n *v8 = v7;\n ++v6;\n if ( a2 != v4 )\n goto LABEL_4;\n goto LABEL_8;\n }\n *v8 = *v10;\n v10 = (_DWORD *)((char *)v10 - v5);\n v8 = (_DWORD *)((char *)v8 - v5);\n }\n while ( v3 <= v9 );\n ++v4;\n ++v6;\n *v11 = v7;\n if ( a2 != v4 )\n continue;\n break;\n }\nLABEL_8:\n v3 >>= 1;\n }\n while ( v3 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1380(long long a1, int a2) {\n int v3;\n int v4;\n long long v5;\n uint32_t *v6;\n int v7;\n uint32_t *v8;\n int v9;\n uint32_t *v10;\n uint32_t *v11;\n v3 = a2 / 2;\n if (a2 > 1) {\n do {\n while (a2 <= v3) v3 >>= 1;\n v4 = v3;\n v5 = 4LL * v3;\n v6 = (uint32_t *)(a1 + v5);\n LABEL_4:\n while (2) {\n v7 = *v6;\n v8 = v6;\n v9 = v4;\n v10 = &v6[v5 / 18446744073709551612LL];\n do {\n v9 -= v3;\n v11 = v10;\n if (*v10 <= v7) {\n ++v4;\n *v8 = v7;\n ++v6;\n if (a2 != v4) goto LABEL_4;\n goto LABEL_8;\n }\n *v8 = *v10;\n v10 = (uint32_t *)((char *)v10 - v5);\n v8 = (uint32_t *)((char *)v8 - v5);\n } while (v3 <= v9);\n ++v4;\n ++v6;\n *v11 = v7;\n if (a2 != v4) continue;\n break;\n }\n LABEL_8:\n v3 >>= 1;\n } while (v3);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2) {\n int v3;\n int v4;\n long long v5;\n uint32_t *v6;\n int v7;\n uint32_t *v8;\n int v9;\n uint32_t *v10;\n uint32_t *v11;\n v3 = a2 / 2;\n if (a2 > 1) {\n do {\n while (a2 <= v3) v3 >>= 1;\n v4 = v3;\n v5 = 4LL * v3;\n v6 = (uint32_t *)(a1 + v5);\n LABEL_4:\n while (2) {\n v7 = *v6;\n v8 = v6;\n v9 = v4;\n v10 = &v6[v5 / 18446744073709551612LL];\n do {\n v9 -= v3;\n v11 = v10;\n if (*v10 <= v7) {\n ++v4;\n *v8 = v7;\n ++v6;\n if (a2 != v4) goto LABEL_4;\n goto LABEL_8;\n }\n *v8 = *v10;\n v10 = (uint32_t *)((char *)v10 - v5);\n v8 = (uint32_t *)((char *)v8 - v5);\n } while (v3 <= v9);\n ++v4;\n ++v6;\n *v11 = v7;\n if (a2 != v4) continue;\n break;\n }\n LABEL_8:\n v3 >>= 1;\n } while (v3);\n }\n}" + }, + { + "index": 429, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "void func0(int test_tup1[], int test_tup2[], int res[], int size) {\n for (int i = 0; i < size; i++) {\n res[i] = test_tup1[i] & test_tup2[i];\n }\n}", + "test": "int main() {\n\n int res[4];\n\n \n\n int test_tup1_1[4] = {10, 4, 6, 9};\n\n int test_tup2_1[4] = {5, 2, 3, 3};\n\n int expected_1[4] = {0, 0, 2, 1};\n\n func0(test_tup1_1, test_tup2_1, res, 4);\n\n for (int i = 0; i < 4; i++) {\n\n assert(res[i] == expected_1[i]);\n\n }\n\n\n\n int test_tup1_2[4] = {1, 2, 3, 4};\n\n int test_tup2_2[4] = {5, 6, 7, 8};\n\n int expected_2[4] = {1, 2, 3, 0};\n\n func0(test_tup1_2, test_tup2_2, res, 4);\n\n for (int i = 0; i < 4; i++) {\n\n assert(res[i] == expected_2[i]);\n\n }\n\n\n\n int test_tup1_3[4] = {8, 9, 11, 12};\n\n int test_tup2_3[4] = {7, 13, 14, 17};\n\n int expected_3[4] = {0, 9, 10, 0};\n\n func0(test_tup1_3, test_tup2_3, res, 4);\n\n for (int i = 0; i < 4; i++) {\n\n assert(res[i] == expected_3[i]);\n\n }\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %ecx,-0x2c(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11d1 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%ecx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rsi\nmov -0x28(%rbp),%rax\nadd %rsi,%rax\nand %ecx,%edx\nmov %edx,(%rax)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 1189 \npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_28], rdx\nmov [rbp+var_2C], ecx\nmov [rbp+var_4], 0\njmp short loc_11D1\nloc_1189:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov ecx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rsi, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rsi\nand edx, ecx\nmov [rax], edx\nadd [rbp+var_4], 1\nloc_11D1:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_2C]\njl short loc_1189\nnop\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+28h] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a4 )\n break;\n *(_DWORD *)(4LL * (int)i + a3) = *(_DWORD *)(4LL * (int)i + a1) & *(_DWORD *)(4LL * (int)i + a2);\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_28], rdx\nmov [rbp+var_2C], ecx\nmov [rbp+var_4], 0\njmp short loc_11D1\nloc_1189:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov ecx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rsi, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rsi\nand edx, ecx\nmov [rax], edx\nadd [rbp+var_4], 1\nloc_11D1:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_2C]\njl short loc_1189\nnop\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+28h] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a4 )\n break;\n *(_DWORD *)(4LL * (int)i + a3) = *(_DWORD *)(4LL * (int)i + a1) & *(_DWORD *)(4LL * (int)i + a2);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, long long a3, int a4) {\n long long result;\n unsigned int i;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a4) break;\n *(uint32_t *)(4LL * (int)i + a3) =\n *(uint32_t *)(4LL * (int)i + a1) & *(uint32_t *)(4LL * (int)i + a2);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, long long a3, int a4) {\n long long result;\n unsigned int i;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a4) break;\n *(uint32_t *)(4LL * (int)i + a3) =\n *(uint32_t *)(4LL * (int)i + a1) & *(uint32_t *)(4LL * (int)i + a2);\n }\n return result;\n}" + }, + { + "index": 429, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "void func0(int test_tup1[], int test_tup2[], int res[], int size) {\n for (int i = 0; i < size; i++) {\n res[i] = test_tup1[i] & test_tup2[i];\n }\n}", + "test": "int main() {\n\n int res[4];\n\n \n\n int test_tup1_1[4] = {10, 4, 6, 9};\n\n int test_tup2_1[4] = {5, 2, 3, 3};\n\n int expected_1[4] = {0, 0, 2, 1};\n\n func0(test_tup1_1, test_tup2_1, res, 4);\n\n for (int i = 0; i < 4; i++) {\n\n assert(res[i] == expected_1[i]);\n\n }\n\n\n\n int test_tup1_2[4] = {1, 2, 3, 4};\n\n int test_tup2_2[4] = {5, 6, 7, 8};\n\n int expected_2[4] = {1, 2, 3, 0};\n\n func0(test_tup1_2, test_tup2_2, res, 4);\n\n for (int i = 0; i < 4; i++) {\n\n assert(res[i] == expected_2[i]);\n\n }\n\n\n\n int test_tup1_3[4] = {8, 9, 11, 12};\n\n int test_tup2_3[4] = {7, 13, 14, 17};\n\n int expected_3[4] = {0, 9, 10, 0};\n\n func0(test_tup1_3, test_tup2_3, res, 4);\n\n for (int i = 0; i < 4; i++) {\n\n assert(res[i] == expected_3[i]);\n\n }\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %ecx,%ecx\njle 118f \nlea -0x1(%rcx),%r8d\nmov $0x0,%eax\nmov (%rdi,%rax,4),%ecx\nand (%rsi,%rax,4),%ecx\nmov %ecx,(%rdx,%rax,4)\nmov %rax,%rcx\nadd $0x1,%rax\ncmp %r8,%rcx\njne 117a \nretq\n", + "ida_asm": "func0:\nendbr64\ntest ecx, ecx\njle short locret_1193\nmovsxd rcx, ecx\nlea r8, ds:0[rcx*4]\nmov eax, 0\nloc_1181:\nmov ecx, [rdi+rax]\nand ecx, [rsi+rax]\nmov [rdx+rax], ecx\nadd rax, 4\ncmp rax, r8\njnz short loc_1181\nlocret_1193:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 v4; // rax\n\n if ( a4 > 0 )\n {\n v4 = 0LL;\n do\n {\n *(_DWORD *)(a3 + v4) = *(_DWORD *)(a2 + v4) & *(_DWORD *)(a1 + v4);\n v4 += 4LL;\n }\n while ( v4 != 4LL * a4 );\n }\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest ecx, ecx\njle short locret_1193\nmovsxd rcx, ecx\nlea r8, ds:0[rcx*4]\nmov eax, 0\nloc_1181:\nmov ecx, [rdi+rax]\nand ecx, [rsi+rax]\nmov [rdx+rax], ecx\nadd rax, 4\ncmp rax, r8\njnz short loc_1181\nlocret_1193:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1169(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 v4; // rax\n\n if ( a4 > 0 )\n {\n v4 = 0LL;\n do\n {\n *(_DWORD *)(a3 + v4) = *(_DWORD *)(a2 + v4) & *(_DWORD *)(a1 + v4);\n v4 += 4LL;\n }\n while ( v4 != 4LL * a4 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1169(long long a1, long long a2, long long a3, int a4) {\n long long v4;\n if (a4 > 0) {\n v4 = 0LL;\n do {\n *(uint32_t *)(a3 + v4) = *(uint32_t *)(a2 + v4) & *(uint32_t *)(a1 + v4);\n v4 += 4LL;\n } while (v4 != 4LL * a4);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, long long a2, long long a3, int a4) {\n long long v4;\n if (a4 > 0) {\n v4 = 0LL;\n do {\n *(uint32_t *)(a3 + v4) = *(uint32_t *)(a2 + v4) & *(uint32_t *)(a1 + v4);\n v4 += 4LL;\n } while (v4 != 4LL * a4);\n }\n}" + }, + { + "index": 430, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int a, int b, int c) {\n int directrix = c - ((b * b) + 1) * 4 * a;\n return directrix;\n}", + "test": "int main() {\n\n assert(func0(5, 3, 2) == -198);\n\n assert(func0(9, 8, 4) == -2336);\n\n assert(func0(2, 4, 6) == -130);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov %edx,-0x1c(%rbp)\nmov -0x18(%rbp),%eax\nimul %eax,%eax\nadd $0x1,%eax\nimul -0x14(%rbp),%eax\nlea 0x0(,%rax,4),%edx\nmov -0x1c(%rbp),%eax\nsub %edx,%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov eax, [rbp+var_18]\nimul eax, eax\nadd eax, 1\nimul eax, [rbp+var_14]\nlea edx, ds:0[rax*4]\nmov eax, [rbp+var_1C]\nsub eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, int a3)\n{\n return (unsigned int)(a3 - 4 * a1 * (a2 * a2 + 1));\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov eax, [rbp+var_18]\nimul eax, eax\nadd eax, 1\nimul eax, [rbp+var_14]\nlea edx, ds:0[rax*4]\nmov eax, [rbp+var_1C]\nsub eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2, int a3)\n{\n return (unsigned int)(a3 - 4 * a1 * (a2 * a2 + 1));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2, int a3) {\n return (unsigned int)(a3 - 4 * a1 * (a2 * a2 + 1));\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, int a3) {\n return (unsigned int)(a3 - 4 * a1 * (a2 * a2 + 1));\n}" + }, + { + "index": 431, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int* list1, int size1, int* list2, int size2) {\n for (int i = 0; i < size1; i++) {\n for (int j = 0; j < size2; j++) {\n if (list1[i] == list2[j]) {\n return 1;\n }\n }\n }\n return 0;\n}", + "test": "int main(){\n\n int list1_a[] = {1, 2, 3, 4, 5};\n\n int list2_a[] = {5, 6, 7, 8, 9};\n\n assert(func0(list1_a, 5, list2_a, 5) == 1);\n\n\n\n int list1_b[] = {1, 2, 3, 4, 5};\n\n int list2_b[] = {6, 7, 8, 9};\n\n assert(func0(list1_b, 5, list2_b, 4) == 0);\n\n\n\n int list1_c[] = {'a', 'b', 'c'};\n\n int list2_c[] = {'d', 'b', 'e'};\n\n assert(func0(list1_c, 3, list2_c, 3) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %ecx,-0x20(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11d8 \nmovl $0x0,-0x4(%rbp)\njmp 11cc \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 11c8 \nmov $0x1,%eax\njmp 11e5 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x20(%rbp),%eax\njl 1191 \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1188 \nmov $0x0,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov [rbp+var_8], 0\njmp short loc_11D8\nloc_1188:\nmov [rbp+var_4], 0\njmp short loc_11CC\nloc_1191:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11C8\nmov eax, 1\njmp short loc_11E5\nloc_11C8:\nadd [rbp+var_4], 1\nloc_11CC:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_20]\njl short loc_1191\nadd [rbp+var_8], 1\nloc_11D8:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, 0\nloc_11E5:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3, int a4)\n{\n int i; // [rsp+20h] [rbp-8h]\n int j; // [rsp+24h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n for ( j = 0; j < a4; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4LL * j + a3) )\n return 1LL;\n }\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov [rbp+var_8], 0\njmp short loc_11D8\nloc_1188:\nmov [rbp+var_4], 0\njmp short loc_11CC\nloc_1191:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11C8\nmov eax, 1\njmp short loc_11E5\nloc_11C8:\nadd [rbp+var_4], 1\nloc_11CC:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_20]\njl short loc_1191\nadd [rbp+var_8], 1\nloc_11D8:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, 0\nloc_11E5:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, __int64 a3, int a4)\n{\n int i; // [rsp+20h] [rbp-8h]\n int j; // [rsp+24h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n for ( j = 0; j < a4; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4LL * j + a3) )\n return 1LL;\n }\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, long long a3, int a4) {\n int i;\n int j;\n for (i = 0; i < a2; ++i) {\n for (j = 0; j < a4; ++j) {\n if (*(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4LL * j + a3))\n return 1LL;\n }\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3, int a4) {\n int i;\n int j;\n for (i = 0; i < a2; ++i) {\n for (j = 0; j < a4; ++j) {\n if (*(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4LL * j + a3))\n return 1LL;\n }\n }\n return 0LL;\n}" + }, + { + "index": 431, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int* list1, int size1, int* list2, int size2) {\n for (int i = 0; i < size1; i++) {\n for (int j = 0; j < size2; j++) {\n if (list1[i] == list2[j]) {\n return 1;\n }\n }\n }\n return 0;\n}", + "test": "int main(){\n\n int list1_a[] = {1, 2, 3, 4, 5};\n\n int list2_a[] = {5, 6, 7, 8, 9};\n\n assert(func0(list1_a, 5, list2_a, 5) == 1);\n\n\n\n int list1_b[] = {1, 2, 3, 4, 5};\n\n int list2_b[] = {6, 7, 8, 9};\n\n assert(func0(list1_b, 5, list2_b, 4) == 0);\n\n\n\n int list1_c[] = {'a', 'b', 'c'};\n\n int list2_c[] = {'d', 'b', 'e'};\n\n assert(func0(list1_c, 3, list2_c, 3) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11ad \nmov %rdi,%r8\nlea -0x1(%rsi),%eax\nlea 0x4(%rdi,%rax,4),%r9\nmov %rdx,%rdi\nlea -0x1(%rcx),%eax\nlea 0x4(%rdx,%rax,4),%rsi\ntest %ecx,%ecx\njle 119e \nmov (%r8),%edx\nmov %rdi,%rax\ncmp (%rax),%edx\nje 11b3 \nadd $0x4,%rax\ncmp %rsi,%rax\njne 1191 \nadd $0x4,%r8\ncmp %r9,%r8\njne 1187 \nmov $0x0,%eax\nretq\nmov $0x0,%eax\nretq\nmov $0x1,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11A8\nmov r8, rdi\nmovsxd rsi, esi\nlea r9, [rdi+rsi*4]\nmovsxd rax, ecx\nlea rdi, [rdx+rax*4]\nloc_1182:\ntest ecx, ecx\njle short loc_1199\nmov esi, [r8]\nmov rax, rdx\nloc_118C:\ncmp esi, [rax]\njz short loc_11AE\nadd rax, 4\ncmp rax, rdi\njnz short loc_118C\nloc_1199:\nadd r8, 4\ncmp r8, r9\njnz short loc_1182\nmov eax, 0\nretn\nloc_11A8:\nmov eax, 0\nretn\nloc_11AE:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2, _DWORD *a3, int a4)\n{\n _DWORD *v4; // r8\n _DWORD *v5; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v4 = a1;\n while ( a4 <= 0 )\n {\nLABEL_7:\n if ( ++v4 == &a1[a2] )\n return 0LL;\n }\n v5 = a3;\n while ( *v4 != *v5 )\n {\n if ( ++v5 == &a3[a4] )\n goto LABEL_7;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11A8\nmov r8, rdi\nmovsxd rsi, esi\nlea r9, [rdi+rsi*4]\nmovsxd rax, ecx\nlea rdi, [rdx+rax*4]\nloc_1182:\ntest ecx, ecx\njle short loc_1199\nmov esi, [r8]\nmov rax, rdx\nloc_118C:\ncmp esi, [rax]\njz short loc_11AE\nadd rax, 4\ncmp rax, rdi\njnz short loc_118C\nloc_1199:\nadd r8, 4\ncmp r8, r9\njnz short loc_1182\nmov eax, 0\nretn\nloc_11A8:\nmov eax, 0\nretn\nloc_11AE:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2, _DWORD *a3, int a4)\n{\n _DWORD *v4; // r8\n _DWORD *v5; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v4 = a1;\n while ( a4 <= 0 )\n {\nLABEL_7:\n if ( ++v4 == &a1[a2] )\n return 0LL;\n }\n v5 = a3;\n while ( *v4 != *v5 )\n {\n if ( ++v5 == &a3[a4] )\n goto LABEL_7;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2, uint32_t *a3, int a4) {\n uint32_t *v4;\n uint32_t *v5;\n if (a2 <= 0) return 0LL;\n v4 = a1;\n while (a4 <= 0) {\n LABEL_7:\n if (++v4 == &a1[a2]) return 0LL;\n }\n v5 = a3;\n while (*v4 != *v5) {\n if (++v5 == &a3[a4]) goto LABEL_7;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2, uint32_t *a3, int a4) {\n uint32_t *v4;\n uint32_t *v5;\n if (a2 <= 0) return 0LL;\n v4 = a1;\n while (a4 <= 0) {\n LABEL_7:\n if (++v4 == &a1[a2]) return 0LL;\n }\n v5 = a3;\n while (*v4 != *v5) {\n if (++v5 == &a3[a4]) goto LABEL_7;\n }\n return 1LL;\n}" + }, + { + "index": 431, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int* list1, int size1, int* list2, int size2) {\n for (int i = 0; i < size1; i++) {\n for (int j = 0; j < size2; j++) {\n if (list1[i] == list2[j]) {\n return 1;\n }\n }\n }\n return 0;\n}", + "test": "int main(){\n\n int list1_a[] = {1, 2, 3, 4, 5};\n\n int list2_a[] = {5, 6, 7, 8, 9};\n\n assert(func0(list1_a, 5, list2_a, 5) == 1);\n\n\n\n int list1_b[] = {1, 2, 3, 4, 5};\n\n int list2_b[] = {6, 7, 8, 9};\n\n assert(func0(list1_b, 5, list2_b, 4) == 0);\n\n\n\n int list1_c[] = {'a', 'b', 'c'};\n\n int list2_c[] = {'d', 'b', 'e'};\n\n assert(func0(list1_c, 3, list2_c, 3) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1329 \nlea -0x1(%rsi),%eax\nlea 0x4(%rdi,%rax,4),%r9\nlea -0x1(%rcx),%eax\nlea 0x4(%rdx,%rax,4),%r8\ntest %ecx,%ecx\njle 1320 \nmov (%rdi),%esi\nmov %rdx,%rax\njmp 1311 \nnopl 0x0(%rax,%rax,1)\nadd $0x4,%rax\ncmp %r8,%rax\nje 1320 \ncmp (%rax),%esi\njne 1308 \nmov $0x1,%eax\nretq\nnopl 0x0(%rax,%rax,1)\nadd $0x4,%rdi\ncmp %r9,%rdi\njne 12f8 \nxor %eax,%eax\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1329\nmovsxd rsi, esi\nmovsxd rax, ecx\nlea r8, [rdi+rsi*4]\nlea rsi, [rdx+rax*4]\nloc_12F6:\ntest ecx, ecx\njle short loc_1330\nloc_12FA:\nmov ecx, [rdi]\nmov rax, rdx\njmp short loc_1311\nloc_1308:\nadd rax, 4\ncmp rax, rsi\njz short loc_1320\nloc_1311:\ncmp ecx, [rax]\njnz short loc_1308\nmov eax, 1\nretn\nloc_1320:\nadd rdi, 4\ncmp rdi, r8\njnz short loc_12FA\nloc_1329:\nxor eax, eax\nretn\nloc_1330:\nadd rdi, 4\ncmp rdi, r8\njnz short loc_12F6\njmp short loc_1329", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2, _DWORD *a3, int a4)\n{\n _DWORD *v4; // r8\n _DWORD *v5; // rax\n\n if ( a2 > 0 )\n {\n v4 = &a1[a2];\n while ( a4 <= 0 )\n {\n if ( ++a1 == v4 )\n return 0LL;\n }\n do\n {\n v5 = a3;\n do\n {\n if ( *a1 == *v5 )\n return 1LL;\n ++v5;\n }\n while ( v5 != &a3[a4] );\n ++a1;\n }\n while ( a1 != v4 );\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\ntest esi, esi\njle short loc_1329\nmovsxd rsi, esi\nmovsxd rax, ecx\nlea r8, [rdi+rsi*4]\nlea rsi, [rdx+rax*4]\nloc_12F6:\ntest ecx, ecx\njle short loc_1330\nloc_12FA:\nmov ecx, [rdi]\nmov rax, rdx\njmp short loc_1311\nloc_1308:\nadd rax, 4\ncmp rax, rsi\njz short loc_1320\nloc_1311:\ncmp ecx, [rax]\njnz short loc_1308\nmov eax, 1\nretn\nloc_1320:\nadd rdi, 4\ncmp rdi, r8\njnz short loc_12FA\nloc_1329:\nxor eax, eax\nretn\nloc_1330:\nadd rdi, 4\ncmp rdi, r8\njnz short loc_12F6\njmp short loc_1329", + "ida_strip_pseudo": "__int64 __fastcall sub_12E0(_DWORD *a1, int a2, _DWORD *a3, int a4)\n{\n _DWORD *v4; // r8\n _DWORD *v5; // rax\n\n if ( a2 > 0 )\n {\n v4 = &a1[a2];\n while ( a4 <= 0 )\n {\n if ( ++a1 == v4 )\n return 0LL;\n }\n do\n {\n v5 = a3;\n do\n {\n if ( *a1 == *v5 )\n return 1LL;\n ++v5;\n }\n while ( v5 != &a3[a4] );\n ++a1;\n }\n while ( a1 != v4 );\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12E0(uint32_t *a1, int a2, uint32_t *a3, int a4) {\n uint32_t *v4;\n uint32_t *v5;\n if (a2 > 0) {\n v4 = &a1[a2];\n while (a4 <= 0) {\n if (++a1 == v4) return 0LL;\n }\n do {\n v5 = a3;\n do {\n if (*a1 == *v5) return 1LL;\n ++v5;\n } while (v5 != &a3[a4]);\n ++a1;\n } while (a1 != v4);\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2, uint32_t *a3, int a4) {\n uint32_t *v4;\n uint32_t *v5;\n if (a2 > 0) {\n v4 = &a1[a2];\n while (a4 <= 0) {\n if (++a1 == v4) return 0LL;\n }\n do {\n v5 = a3;\n do {\n if (*a1 == *v5) return 1LL;\n ++v5;\n } while (v5 != &a3[a4]);\n ++a1;\n } while (a1 != v4);\n }\n return 0LL;\n}" + }, + { + "index": 432, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "double func0(double base1, double base2, double height) {\n double median = 0.5 * (base1 + base2);\n return median;\n}", + "test": "int main() {\n\n assert(func0(15, 25, 35) == 20);\n\n assert(func0(10, 20, 30) == 15);\n\n assert(func0(6, 9, 4) == 7.5);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmovsd %xmm0,-0x18(%rbp)\nmovsd %xmm1,-0x20(%rbp)\nmovsd %xmm2,-0x28(%rbp)\nmovsd -0x18(%rbp),%xmm0\nmovapd %xmm0,%xmm1\naddsd -0x20(%rbp),%xmm1\nmovsd 0xf1a(%rip),%xmm0\nmulsd %xmm1,%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmovsd -0x8(%rbp),%xmm0\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmovsd [rbp+var_18], xmm0\nmovsd [rbp+var_20], xmm1\nmovsd [rbp+var_28], xmm2\nmovsd xmm0, [rbp+var_18]\nmovapd xmm1, xmm0\naddsd xmm1, [rbp+var_20]\nmovsd xmm0, cs:qword_2078\nmulsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "double __fastcall func0(double a1, double a2)\n{\n return 0.5 * (a1 + a2);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmovsd [rbp+var_18], xmm0\nmovsd [rbp+var_20], xmm1\nmovsd [rbp+var_28], xmm2\nmovsd xmm0, [rbp+var_18]\nmovapd xmm1, xmm0\naddsd xmm1, [rbp+var_20]\nmovsd xmm0, cs:qword_2078\nmulsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "double __fastcall sub_1149(double a1, double a2)\n{\n return 0.5 * (a1 + a2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1149(double a1, double a2) { return 0.5 * (a1 + a2); }", + "ida_pseudo_norm": "double func0(double a1, double a2) { return 0.5 * (a1 + a2); }" + }, + { + "index": 433, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int arr[], int size, int number) {\n for (int i = 0; i < size - 1; i++) {\n for (int j = 0; j < size - i - 1; j++) {\n if (arr[j] > arr[j + 1]) {\n int temp = arr[j];\n arr[j] = arr[j + 1];\n arr[j + 1] = temp;\n }\n }\n }\n if (number > arr[size - 1]) {\n printf(\"Yes, the entered number is greater than those in the array\\n\");\n } else {\n printf(\"No, entered number is less than those in the array\\n\");\n }\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4, 5};\n\n int arr2[] = {2, 3, 4, 5, 6};\n\n int arr3[] = {9, 7, 4, 8, 6, 1};\n\n\n\n func0(arr1, 5, 4); // Expected output: No, entered number is less than those in the array\n\n func0(arr2, 5, 8); // Expected output: Yes, the entered number is greater than those in the array\n\n func0(arr3, 6, 11); // Expected output: Yes, the entered number is greater than those in the array\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmovl $0x0,-0xc(%rbp)\njmpq 124c \nmovl $0x0,-0x8(%rbp)\njmpq 1236 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x8(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njle 1232 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x4(%rbp)\nmov -0x8(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0x8(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\nmov -0x8(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0x4(%rbp),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x8(%rbp)\nmov -0x1c(%rbp),%eax\nsub -0xc(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x8(%rbp)\njl 1197 \naddl $0x1,-0xc(%rbp)\nmov -0x1c(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0xc(%rbp)\njl 118b \nmov -0x1c(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x20(%rbp)\njle 1284 \nlea 0xd8b(%rip),%rdi\ncallq 1060 \njmp 1290 \nlea 0xdbd(%rip),%rdi\ncallq 1060 \nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_C], 0\njmp loc_124C\nloc_118B:\nmov [rbp+var_8], 0\njmp loc_1236\nloc_1197:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_1232\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_8]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_8]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nloc_1232:\nadd [rbp+var_8], 1\nloc_1236:\nmov eax, [rbp+var_1C]\nsub eax, [rbp+var_C]\nsub eax, 1\ncmp [rbp+var_8], eax\njl loc_1197\nadd [rbp+var_C], 1\nloc_124C:\nmov eax, [rbp+var_1C]\nsub eax, 1\ncmp [rbp+var_C], eax\njl loc_118B\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njle short loc_1287\nlea rax, s; \"Yes, the entered number is greater than\"...\nmov rdi, rax; s\ncall _puts\njmp short loc_1296\nloc_1287:\nlea rax, aNoEnteredNumbe; \"No, entered number is less than those i\"...\nmov rdi, rax; s\ncall _puts\nloc_1296:\nnop\nleave\nretn", + "ida_pseudo": "int __fastcall func0(__int64 a1, int a2, int a3)\n{\n int i; // [rsp+14h] [rbp-Ch]\n int j; // [rsp+18h] [rbp-8h]\n int v6; // [rsp+1Ch] [rbp-4h]\n\n for ( i = 0; i < a2 - 1; ++i )\n {\n for ( j = 0; j < a2 - i - 1; ++j )\n {\n if ( *(_DWORD *)(4LL * j + a1) > *(_DWORD *)(4 * (j + 1LL) + a1) )\n {\n v6 = *(_DWORD *)(4LL * j + a1);\n *(_DWORD *)(4LL * j + a1) = *(_DWORD *)(4 * (j + 1LL) + a1);\n *(_DWORD *)(a1 + 4 * (j + 1LL)) = v6;\n }\n }\n }\n if ( a3 <= *(_DWORD *)(4LL * a2 - 4 + a1) )\n return puts(\"No, entered number is less than those in the array\");\n else\n return puts(\"Yes, the entered number is greater than those in the array\");\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_C], 0\njmp loc_124C\nloc_118B:\nmov [rbp+var_8], 0\njmp loc_1236\nloc_1197:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_1232\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_8]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_8]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nloc_1232:\nadd [rbp+var_8], 1\nloc_1236:\nmov eax, [rbp+var_1C]\nsub eax, [rbp+var_C]\nsub eax, 1\ncmp [rbp+var_8], eax\njl loc_1197\nadd [rbp+var_C], 1\nloc_124C:\nmov eax, [rbp+var_1C]\nsub eax, 1\ncmp [rbp+var_C], eax\njl loc_118B\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njle short loc_1287\nlea rax, s; \"Yes, the entered number is greater than\"...\nmov rdi, rax; s\ncall _puts\njmp short loc_1296\nloc_1287:\nlea rax, aNoEnteredNumbe; \"No, entered number is less than those i\"...\nmov rdi, rax; s\ncall _puts\nloc_1296:\nnop\nleave\nretn", + "ida_strip_pseudo": "int __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n int i; // [rsp+14h] [rbp-Ch]\n int j; // [rsp+18h] [rbp-8h]\n int v6; // [rsp+1Ch] [rbp-4h]\n\n for ( i = 0; i < a2 - 1; ++i )\n {\n for ( j = 0; j < a2 - i - 1; ++j )\n {\n if ( *(_DWORD *)(4LL * j + a1) > *(_DWORD *)(4 * (j + 1LL) + a1) )\n {\n v6 = *(_DWORD *)(4LL * j + a1);\n *(_DWORD *)(4LL * j + a1) = *(_DWORD *)(4 * (j + 1LL) + a1);\n *(_DWORD *)(a1 + 4 * (j + 1LL)) = v6;\n }\n }\n }\n if ( a3 <= *(_DWORD *)(4LL * a2 - 4 + a1) )\n return puts(\"No, entered number is less than those in the array\");\n else\n return puts(\"Yes, the entered number is greater than those in the array\");\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "int sub_1169(long long a1, int a2, int a3) {\n int i;\n int j;\n int v6;\n for (i = 0; i < a2 - 1; ++i) {\n for (j = 0; j < a2 - i - 1; ++j) {\n if (*(uint32_t *)(4LL * j + a1) > *(uint32_t *)(4 * (j + 1LL) + a1)) {\n v6 = *(uint32_t *)(4LL * j + a1);\n *(uint32_t *)(4LL * j + a1) = *(uint32_t *)(4 * (j + 1LL) + a1);\n *(uint32_t *)(a1 + 4 * (j + 1LL)) = v6;\n }\n }\n }\n if (a3 <= *(uint32_t *)(4LL * a2 - 4 + a1))\n return puts(\"No, entered number is less than those in the array\");\n else\n return puts(\"Yes, the entered number is greater than those in the array\");\n}", + "ida_pseudo_norm": "int func0(long long a1, int a2, int a3) {\n int i;\n int j;\n int v6;\n for (i = 0; i < a2 - 1; ++i) {\n for (j = 0; j < a2 - i - 1; ++j) {\n if (*(uint32_t *)(4LL * j + a1) > *(uint32_t *)(4 * (j + 1LL) + a1)) {\n v6 = *(uint32_t *)(4LL * j + a1);\n *(uint32_t *)(4LL * j + a1) = *(uint32_t *)(4 * (j + 1LL) + a1);\n *(uint32_t *)(a1 + 4 * (j + 1LL)) = v6;\n }\n }\n }\n if (a3 <= *(uint32_t *)(4LL * a2 - 4 + a1))\n return puts(\"No, entered number is less than those in the array\");\n else\n return puts(\"Yes, the entered number is greater than those in the array\");\n}" + }, + { + "index": 433, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int arr[], int size, int number) {\n for (int i = 0; i < size - 1; i++) {\n for (int j = 0; j < size - i - 1; j++) {\n if (arr[j] > arr[j + 1]) {\n int temp = arr[j];\n arr[j] = arr[j + 1];\n arr[j + 1] = temp;\n }\n }\n }\n if (number > arr[size - 1]) {\n printf(\"Yes, the entered number is greater than those in the array\\n\");\n } else {\n printf(\"No, entered number is less than those in the array\\n\");\n }\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4, 5};\n\n int arr2[] = {2, 3, 4, 5, 6};\n\n int arr3[] = {9, 7, 4, 8, 6, 1};\n\n\n\n func0(arr1, 5, 4); // Expected output: No, entered number is less than those in the array\n\n func0(arr2, 5, 8); // Expected output: Yes, the entered number is greater than those in the array\n\n func0(arr3, 6, 11); // Expected output: Yes, the entered number is greater than those in the array\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x8,%rsp\nlea -0x1(%rsi),%r10d\ntest %r10d,%r10d\njle 11b4 \nlea 0x4(%rdi),%r11\njmp 11a2 \nadd $0x4,%rax\ncmp %r9,%rax\nje 119c \nmov (%rax),%ecx\nmov 0x4(%rax),%r8d\ncmp %r8d,%ecx\njle 1180 \nmov %r8d,(%rax)\nmov %ecx,0x4(%rax)\njmp 1180 \nsub $0x1,%r10d\nje 11b4 \ntest %r10d,%r10d\njle 119c \nmov %rdi,%rax\nlea -0x1(%r10),%ecx\nlea (%r11,%rcx,4),%r9\njmp 1189 \nmovslq %esi,%rsi\ncmp %edx,-0x4(%rdi,%rsi,4)\njge 11ce \nlea 0xe44(%rip),%rdi\ncallq 1060 \nadd $0x8,%rsp\nretq\nlea 0xe73(%rip),%rdi\ncallq 1060 \njmp 11c9 \n", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\ncmp esi, 1\njle short loc_11B8\nmov r10d, esi\nlea r11, [rdi+4]\njmp short loc_11A5\nloc_117F:\nadd rax, 4\ncmp rax, r9\njz short loc_119B\nloc_1188:\nmov ecx, [rax]\nmov r8d, [rax+4]\ncmp ecx, r8d\njle short loc_117F\nmov [rax], r8d\nmov [rax+4], ecx\njmp short loc_117F\nloc_119B:\nsub r10d, 1\ncmp r10d, 1\njz short loc_11B8\nloc_11A5:\ncmp r10d, 1\njle short loc_11E0\nmov rax, rdi\nlea ecx, [r10-2]\nlea r9, [r11+rcx*4]\njmp short loc_1188\nloc_11B8:\nmovsxd rsi, esi\ncmp [rdi+rsi*4-4], edx\njge short loc_11D2\nlea rdi, s; \"Yes, the entered number is greater than\"...\ncall _puts\nloc_11CD:\nadd rsp, 8\nretn\nloc_11D2:\nlea rdi, aNoEnteredNumbe; \"No, entered number is less than those i\"...\ncall _puts\njmp short loc_11CD\nloc_11E0:\nsub r10d, 1\njmp short loc_11A5", + "ida_pseudo": "int __fastcall func0(int *a1, int a2, int a3)\n{\n int i; // r10d\n int *v4; // rax\n int v5; // ecx\n int v6; // r8d\n\n if ( a2 > 1 )\n {\n for ( i = a2; i != 1; --i )\n {\n while ( i <= 1 )\n --i;\n v4 = a1;\n do\n {\n v5 = *v4;\n v6 = v4[1];\n if ( *v4 > v6 )\n {\n *v4 = v6;\n v4[1] = v5;\n }\n ++v4;\n }\n while ( v4 != &a1[i - 2 + 1] );\n }\n }\n if ( a1[a2 - 1] >= a3 )\n return puts(\"No, entered number is less than those in the array\");\n else\n return puts(\"Yes, the entered number is greater than those in the array\");\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nsub rsp, 8\ncmp esi, 1\njle short loc_11B8\nmov r10d, esi\nlea r11, [rdi+4]\njmp short loc_11A5\nloc_117F:\nadd rax, 4\ncmp rax, r9\njz short loc_119B\nloc_1188:\nmov ecx, [rax]\nmov r8d, [rax+4]\ncmp ecx, r8d\njle short loc_117F\nmov [rax], r8d\nmov [rax+4], ecx\njmp short loc_117F\nloc_119B:\nsub r10d, 1\ncmp r10d, 1\njz short loc_11B8\nloc_11A5:\ncmp r10d, 1\njle short loc_11E0\nmov rax, rdi\nlea ecx, [r10-2]\nlea r9, [r11+rcx*4]\njmp short loc_1188\nloc_11B8:\nmovsxd rsi, esi\ncmp [rdi+rsi*4-4], edx\njge short loc_11D2\nlea rdi, s; \"Yes, the entered number is greater than\"...\ncall _puts\nloc_11CD:\nadd rsp, 8\nretn\nloc_11D2:\nlea rdi, aNoEnteredNumbe; \"No, entered number is less than those i\"...\ncall _puts\njmp short loc_11CD\nloc_11E0:\nsub r10d, 1\njmp short loc_11A5", + "ida_strip_pseudo": "int __fastcall sub_1169(int *a1, int a2, int a3)\n{\n int i; // r10d\n int *v4; // rax\n int v5; // ecx\n int v6; // r8d\n\n if ( a2 > 1 )\n {\n for ( i = a2; i != 1; --i )\n {\n while ( i <= 1 )\n --i;\n v4 = a1;\n do\n {\n v5 = *v4;\n v6 = v4[1];\n if ( *v4 > v6 )\n {\n *v4 = v6;\n v4[1] = v5;\n }\n ++v4;\n }\n while ( v4 != &a1[i - 2 + 1] );\n }\n }\n if ( a1[a2 - 1] >= a3 )\n return puts(\"No, entered number is less than those in the array\");\n else\n return puts(\"Yes, the entered number is greater than those in the array\");\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "int sub_1169(int *a1, int a2, int a3) {\n int i;\n int *v4;\n int v5;\n int v6;\n if (a2 > 1) {\n for (i = a2; i != 1; --i) {\n while (i <= 1) --i;\n v4 = a1;\n do {\n v5 = *v4;\n v6 = v4[1];\n if (*v4 > v6) {\n *v4 = v6;\n v4[1] = v5;\n }\n ++v4;\n } while (v4 != &a1[i - 2 + 1]);\n }\n }\n if (a1[a2 - 1] >= a3)\n return puts(\"No, entered number is less than those in the array\");\n else\n return puts(\"Yes, the entered number is greater than those in the array\");\n}", + "ida_pseudo_norm": "int func0(int *a1, int a2, int a3) {\n int i;\n int *v4;\n int v5;\n int v6;\n if (a2 > 1) {\n for (i = a2; i != 1; --i) {\n while (i <= 1) --i;\n v4 = a1;\n do {\n v5 = *v4;\n v6 = v4[1];\n if (*v4 > v6) {\n *v4 = v6;\n v4[1] = v5;\n }\n ++v4;\n } while (v4 != &a1[i - 2 + 1]);\n }\n }\n if (a1[a2 - 1] >= a3)\n return puts(\"No, entered number is less than those in the array\");\n else\n return puts(\"Yes, the entered number is greater than those in the array\");\n}" + }, + { + "index": 433, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int arr[], int size, int number) {\n for (int i = 0; i < size - 1; i++) {\n for (int j = 0; j < size - i - 1; j++) {\n if (arr[j] > arr[j + 1]) {\n int temp = arr[j];\n arr[j] = arr[j + 1];\n arr[j + 1] = temp;\n }\n }\n }\n if (number > arr[size - 1]) {\n printf(\"Yes, the entered number is greater than those in the array\\n\");\n } else {\n printf(\"No, entered number is less than those in the array\\n\");\n }\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4, 5};\n\n int arr2[] = {2, 3, 4, 5, 6};\n\n int arr3[] = {9, 7, 4, 8, 6, 1};\n\n\n\n func0(arr1, 5, 4); // Expected output: No, entered number is less than those in the array\n\n func0(arr2, 5, 8); // Expected output: Yes, the entered number is greater than those in the array\n\n func0(arr3, 6, 11); // Expected output: Yes, the entered number is greater than those in the array\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nlea -0x1(%rsi),%ecx\ntest %ecx,%ecx\njle 12a2 \nlea 0x4(%rdi),%r11\nsub $0x1,%ecx\nmov %rdi,%rax\nmov %rcx,%r10\nlea (%r11,%rcx,4),%r9\nnopl (%rax)\nmov (%rax),%ecx\nmov 0x4(%rax),%r8d\ncmp %r8d,%ecx\njle 1291 \nmov %r8d,(%rax)\nmov %ecx,0x4(%rax)\nadd $0x4,%rax\ncmp %r9,%rax\njne 1280 \nmov %r10d,%ecx\ntest %r10d,%r10d\njne 1270 \nmovslq %esi,%rsi\ncmp %edx,-0x4(%rdi,%rsi,4)\njge 12b7 \nlea 0xd56(%rip),%rdi\njmpq 1060 \nlea 0xd8a(%rip),%rdi\njmpq 1060 \nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\nmov r10, rdi\ncmp esi, 1\njle short loc_1281\nmov r9d, esi\nlea r11, [rdi+4]\nnop dword ptr [rax+rax+00h]\nloc_1238:\ncmp r9d, 1\njle short loc_12A0\nlea ecx, [r9-2]\nmov rax, r10\nlea r8, [r11+rcx*4]\nnop dword ptr [rax+00000000h]\nloc_1250:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd ecx, xmm0\nmovd edi, xmm1\ncmp edi, ecx\njge short loc_126E\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_126E:\nadd rax, 4\ncmp rax, r8\njnz short loc_1250\nsub r9d, 1\ncmp r9d, 1\njnz short loc_1238\nloc_1281:\nmovsxd rsi, esi\ncmp [r10+rsi*4-4], edx\njge short loc_12A6\nlea rdi, s; \"Yes, the entered number is greater than\"...\njmp _puts\nloc_12A0:\nsub r9d, 1\njmp short loc_1238\nloc_12A6:\nlea rdi, aNoEnteredNumbe; \"No, entered number is less than those i\"...\njmp _puts", + "ida_pseudo": "int __fastcall func0(__m128i *a1, int a2, __int32 a3)\n{\n int i; // r9d\n __m128i *v4; // rax\n __m128i v5; // xmm0\n\n if ( a2 > 1 )\n {\n for ( i = a2; i != 1; --i )\n {\n while ( i <= 1 )\n --i;\n v4 = a1;\n do\n {\n v5 = _mm_loadl_epi64(v4);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v5, 229)) < _mm_cvtsi128_si32(v5) )\n v4->m128i_i64[0] = _mm_shuffle_epi32(v5, 225).m128i_u64[0];\n v4 = (__m128i *)((char *)v4 + 4);\n }\n while ( v4 != (__m128i *)((char *)a1->m128i_i64 + 4 * (unsigned int)(i - 2) + 4) );\n }\n }\n if ( a1->m128i_i32[a2 - 1] >= a3 )\n return puts(\"No, entered number is less than those in the array\");\n else\n return puts(\"Yes, the entered number is greater than those in the array\");\n}", + "ida_strip_asm": "sub_1220:\nendbr64\nmov r10, rdi\ncmp esi, 1\njle short loc_1281\nmov r9d, esi\nlea r11, [rdi+4]\nnop dword ptr [rax+rax+00h]\nloc_1238:\ncmp r9d, 1\njle short loc_12A0\nlea ecx, [r9-2]\nmov rax, r10\nlea r8, [r11+rcx*4]\nnop dword ptr [rax+00000000h]\nloc_1250:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd ecx, xmm0\nmovd edi, xmm1\ncmp edi, ecx\njge short loc_126E\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_126E:\nadd rax, 4\ncmp rax, r8\njnz short loc_1250\nsub r9d, 1\ncmp r9d, 1\njnz short loc_1238\nloc_1281:\nmovsxd rsi, esi\ncmp [r10+rsi*4-4], edx\njge short loc_12A6\nlea rdi, s; \"Yes, the entered number is greater than\"...\njmp _puts\nloc_12A0:\nsub r9d, 1\njmp short loc_1238\nloc_12A6:\nlea rdi, aNoEnteredNumbe; \"No, entered number is less than those i\"...\njmp _puts", + "ida_strip_pseudo": "int __fastcall sub_1220(__m128i *a1, int a2, __int32 a3)\n{\n int i; // r9d\n __m128i *v4; // rax\n __m128i v5; // xmm0\n\n if ( a2 > 1 )\n {\n for ( i = a2; i != 1; --i )\n {\n while ( i <= 1 )\n --i;\n v4 = a1;\n do\n {\n v5 = _mm_loadl_epi64(v4);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v5, 229)) < _mm_cvtsi128_si32(v5) )\n v4->m128i_i64[0] = _mm_shuffle_epi32(v5, 225).m128i_u64[0];\n v4 = (__m128i *)((char *)v4 + 4);\n }\n while ( v4 != (__m128i *)((char *)a1->m128i_i64 + 4 * (unsigned int)(i - 2) + 4) );\n }\n }\n if ( a1->m128i_i32[a2 - 1] >= a3 )\n return puts(\"No, entered number is less than those in the array\");\n else\n return puts(\"Yes, the entered number is greater than those in the array\");\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "int sub_1220(__m128i *a1, int a2, int a3) {\n int i;\n __m128i *v4;\n __m128i v5;\n if (a2 > 1) {\n for (i = a2; i != 1; --i) {\n while (i <= 1) --i;\n v4 = a1;\n do {\n v5 = _mm_loadl_epi64(v4);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v5, 229)) <\n _mm_cvtsi128_si32(v5))\n v4->m128i_i64[0] = _mm_shuffle_epi32(v5, 225).m128i_u64[0];\n v4 = (__m128i *)((char *)v4 + 4);\n } while (v4 != (__m128i *)((char *)a1->m128i_i64 +\n 4 * (unsigned int)(i - 2) + 4));\n }\n }\n if (a1->m128i_i32[a2 - 1] >= a3)\n return puts(\"No, entered number is less than those in the array\");\n else\n return puts(\"Yes, the entered number is greater than those in the array\");\n}", + "ida_pseudo_norm": "int func0(__m128i *a1, int a2, int a3) {\n int i;\n __m128i *v4;\n __m128i v5;\n if (a2 > 1) {\n for (i = a2; i != 1; --i) {\n while (i <= 1) --i;\n v4 = a1;\n do {\n v5 = _mm_loadl_epi64(v4);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v5, 229)) <\n _mm_cvtsi128_si32(v5))\n v4->m128i_i64[0] = _mm_shuffle_epi32(v5, 225).m128i_u64[0];\n v4 = (__m128i *)((char *)v4 + 4);\n } while (v4 != (__m128i *)((char *)a1->m128i_i64 +\n 4 * (unsigned int)(i - 2) + 4));\n }\n }\n if (a1->m128i_i32[a2 - 1] >= a3)\n return puts(\"No, entered number is less than those in the array\");\n else\n return puts(\"Yes, the entered number is greater than those in the array\");\n}" + }, + { + "index": 433, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int arr[], int size, int number) {\n for (int i = 0; i < size - 1; i++) {\n for (int j = 0; j < size - i - 1; j++) {\n if (arr[j] > arr[j + 1]) {\n int temp = arr[j];\n arr[j] = arr[j + 1];\n arr[j + 1] = temp;\n }\n }\n }\n if (number > arr[size - 1]) {\n printf(\"Yes, the entered number is greater than those in the array\\n\");\n } else {\n printf(\"No, entered number is less than those in the array\\n\");\n }\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4, 5};\n\n int arr2[] = {2, 3, 4, 5, 6};\n\n int arr3[] = {9, 7, 4, 8, 6, 1};\n\n\n\n func0(arr1, 5, 4); // Expected output: No, entered number is less than those in the array\n\n func0(arr2, 5, 8); // Expected output: Yes, the entered number is greater than those in the array\n\n func0(arr3, 6, 11); // Expected output: Yes, the entered number is greater than those in the array\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nlea -0x1(%rsi),%ecx\ntest %ecx,%ecx\njle 1272 \nlea 0x4(%rdi),%r11\nsub $0x1,%ecx\nmov %rdi,%rax\nmov %rcx,%r10\nlea (%r11,%rcx,4),%r9\nnopl (%rax)\nmov (%rax),%ecx\nmov 0x4(%rax),%r8d\ncmp %r8d,%ecx\njle 1261 \nmov %r8d,(%rax)\nmov %ecx,0x4(%rax)\nadd $0x4,%rax\ncmp %r9,%rax\njne 1250 \nmov %r10d,%ecx\ntest %r10d,%r10d\njne 1240 \nmovslq %esi,%rsi\ncmp %edx,-0x4(%rdi,%rsi,4)\njge 1287 \nlea 0xd86(%rip),%rdi\njmpq 1060 \nlea 0xdba(%rip),%rdi\njmpq 1060 \nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\nmov r10, rdi\ncmp esi, 1\njle short loc_1281\nmov r9d, esi\nlea r11, [rdi+4]\nnop dword ptr [rax+rax+00h]\nloc_1238:\ncmp r9d, 1\njle short loc_12A0\nlea ecx, [r9-2]\nmov rax, r10\nlea r8, [r11+rcx*4]\nnop dword ptr [rax+00000000h]\nloc_1250:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd ecx, xmm0\nmovd edi, xmm1\ncmp edi, ecx\njge short loc_126E\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_126E:\nadd rax, 4\ncmp rax, r8\njnz short loc_1250\nsub r9d, 1\ncmp r9d, 1\njnz short loc_1238\nloc_1281:\nmovsxd rsi, esi\ncmp [r10+rsi*4-4], edx\njge short loc_12A6\nlea rdi, s; \"Yes, the entered number is greater than\"...\njmp _puts\nloc_12A0:\nsub r9d, 1\njmp short loc_1238\nloc_12A6:\nlea rdi, aNoEnteredNumbe; \"No, entered number is less than those i\"...\njmp _puts", + "ida_pseudo": "int __fastcall func0(__m128i *a1, int a2, __int32 a3)\n{\n int i; // r9d\n __m128i *v4; // rax\n __m128i v5; // xmm0\n\n if ( a2 > 1 )\n {\n for ( i = a2; i != 1; --i )\n {\n while ( i <= 1 )\n --i;\n v4 = a1;\n do\n {\n v5 = _mm_loadl_epi64(v4);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v5, 229)) < _mm_cvtsi128_si32(v5) )\n v4->m128i_i64[0] = _mm_shuffle_epi32(v5, 225).m128i_u64[0];\n v4 = (__m128i *)((char *)v4 + 4);\n }\n while ( v4 != (__m128i *)((char *)a1->m128i_i64 + 4 * (unsigned int)(i - 2) + 4) );\n }\n }\n if ( a1->m128i_i32[a2 - 1] >= a3 )\n return puts(\"No, entered number is less than those in the array\");\n else\n return puts(\"Yes, the entered number is greater than those in the array\");\n}", + "ida_strip_asm": "sub_1220:\nendbr64\nmov r10, rdi\ncmp esi, 1\njle short loc_1281\nmov r9d, esi\nlea r11, [rdi+4]\nnop dword ptr [rax+rax+00h]\nloc_1238:\ncmp r9d, 1\njle short loc_12A0\nlea ecx, [r9-2]\nmov rax, r10\nlea r8, [r11+rcx*4]\nnop dword ptr [rax+00000000h]\nloc_1250:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd ecx, xmm0\nmovd edi, xmm1\ncmp edi, ecx\njge short loc_126E\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_126E:\nadd rax, 4\ncmp rax, r8\njnz short loc_1250\nsub r9d, 1\ncmp r9d, 1\njnz short loc_1238\nloc_1281:\nmovsxd rsi, esi\ncmp [r10+rsi*4-4], edx\njge short loc_12A6\nlea rdi, s; \"Yes, the entered number is greater than\"...\njmp _puts\nloc_12A0:\nsub r9d, 1\njmp short loc_1238\nloc_12A6:\nlea rdi, aNoEnteredNumbe; \"No, entered number is less than those i\"...\njmp _puts", + "ida_strip_pseudo": "int __fastcall sub_1220(__m128i *a1, int a2, __int32 a3)\n{\n int i; // r9d\n __m128i *v4; // rax\n __m128i v5; // xmm0\n\n if ( a2 > 1 )\n {\n for ( i = a2; i != 1; --i )\n {\n while ( i <= 1 )\n --i;\n v4 = a1;\n do\n {\n v5 = _mm_loadl_epi64(v4);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v5, 229)) < _mm_cvtsi128_si32(v5) )\n v4->m128i_i64[0] = _mm_shuffle_epi32(v5, 225).m128i_u64[0];\n v4 = (__m128i *)((char *)v4 + 4);\n }\n while ( v4 != (__m128i *)((char *)a1->m128i_i64 + 4 * (unsigned int)(i - 2) + 4) );\n }\n }\n if ( a1->m128i_i32[a2 - 1] >= a3 )\n return puts(\"No, entered number is less than those in the array\");\n else\n return puts(\"Yes, the entered number is greater than those in the array\");\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "int sub_1220(__m128i *a1, int a2, int a3) {\n int i;\n __m128i *v4;\n __m128i v5;\n if (a2 > 1) {\n for (i = a2; i != 1; --i) {\n while (i <= 1) --i;\n v4 = a1;\n do {\n v5 = _mm_loadl_epi64(v4);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v5, 229)) <\n _mm_cvtsi128_si32(v5))\n v4->m128i_i64[0] = _mm_shuffle_epi32(v5, 225).m128i_u64[0];\n v4 = (__m128i *)((char *)v4 + 4);\n } while (v4 != (__m128i *)((char *)a1->m128i_i64 +\n 4 * (unsigned int)(i - 2) + 4));\n }\n }\n if (a1->m128i_i32[a2 - 1] >= a3)\n return puts(\"No, entered number is less than those in the array\");\n else\n return puts(\"Yes, the entered number is greater than those in the array\");\n}", + "ida_pseudo_norm": "int func0(__m128i *a1, int a2, int a3) {\n int i;\n __m128i *v4;\n __m128i v5;\n if (a2 > 1) {\n for (i = a2; i != 1; --i) {\n while (i <= 1) --i;\n v4 = a1;\n do {\n v5 = _mm_loadl_epi64(v4);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v5, 229)) <\n _mm_cvtsi128_si32(v5))\n v4->m128i_i64[0] = _mm_shuffle_epi32(v5, 225).m128i_u64[0];\n v4 = (__m128i *)((char *)v4 + 4);\n } while (v4 != (__m128i *)((char *)a1->m128i_i64 +\n 4 * (unsigned int)(i - 2) + 4));\n }\n }\n if (a1->m128i_i32[a2 - 1] >= a3)\n return puts(\"No, entered number is less than those in the array\");\n else\n return puts(\"Yes, the entered number is greater than those in the array\");\n}" + }, + { + "index": 434, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "const char* func0(const char* text) {\n regex_t regex;\n int ret;\n ret = regcomp(®ex, \"ab+\", REG_EXTENDED);\n if (ret) {\n return \"Regex compilation failed!\";\n }\n ret = regexec(®ex, text, 0, NULL, 0);\n regfree(®ex);\n if (ret == 0) {\n return \"Found a match!\";\n } else {\n return \"Not matched!\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"ac\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"dc\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"abba\"), \"Found a match!\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x70,%rsp\nmov %rdi,-0x68(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea -0x50(%rbp),%rax\nmov $0x1,%edx\nlea 0xdf0(%rip),%rsi\nmov %rax,%rdi\ncallq 10d0 \nmov %eax,-0x54(%rbp)\ncmpl $0x0,-0x54(%rbp)\nje 1232 \nlea 0xddc(%rip),%rax\njmp 1277 \nmov -0x68(%rbp),%rsi\nlea -0x50(%rbp),%rax\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rax,%rdi\ncallq 10f0 \nmov %eax,-0x54(%rbp)\nlea -0x50(%rbp),%rax\nmov %rax,%rdi\ncallq 10a0 \ncmpl $0x0,-0x54(%rbp)\njne 1270 \nlea 0xdb8(%rip),%rax\njmp 1277 \nlea 0xdbe(%rip),%rax\nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 128b \ncallq 10b0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nlea rcx, pattern; \"ab+\"\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+var_54], eax\ncmp [rbp+var_54], 0\njz short loc_1235\nlea rax, aRegexCompilati; \"Regex compilation failed!\"\njmp short loc_127A\nloc_1235:\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_54], eax\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\ncmp [rbp+var_54], 0\njnz short loc_1273\nlea rax, aFoundAMatch; \"Found a match!\"\njmp short loc_127A\nloc_1273:\nlea rax, s2; \"Not matched!\"\nloc_127A:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_128E\ncall ___stack_chk_fail\nlocret_128E:\nleave\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n int v2; // [rsp+1Ch] [rbp-54h]\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n unsigned __int64 v4; // [rsp+68h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"ab+\", 1) )\n return \"Regex compilation failed!\";\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if ( v2 )\n return \"Not matched!\";\n else\n return \"Found a match!\";\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nlea rcx, pattern; \"ab+\"\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+var_54], eax\ncmp [rbp+var_54], 0\njz short loc_1235\nlea rax, aRegexCompilati; \"Regex compilation failed!\"\njmp short loc_127A\nloc_1235:\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_54], eax\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\ncmp [rbp+var_54], 0\njnz short loc_1273\nlea rax, aFoundAMatch; \"Found a match!\"\njmp short loc_127A\nloc_1273:\nlea rax, s2; \"Not matched!\"\nloc_127A:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_128E\ncall ___stack_chk_fail\nlocret_128E:\nleave\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_11E9(const char *a1)\n{\n int v2; // [rsp+1Ch] [rbp-54h]\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n unsigned __int64 v4; // [rsp+68h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"ab+\", 1) )\n return \"Regex compilation failed!\";\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if ( v2 )\n return \"Not matched!\";\n else\n return \"Found a match!\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_11E9(const char *a1) {\n int v2;\n regex_t preg;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n if (regcomp(&preg, \"ab+\", 1)) return \"Regex compilation failed!\";\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if (v2)\n return \"Not matched!\";\n else\n return \"Found a match!\";\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n int v2;\n regex_t preg;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n if (regcomp(&preg, \"ab+\", 1)) return \"Regex compilation failed!\";\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if (v2)\n return \"Not matched!\";\n else\n return \"Found a match!\";\n}" + }, + { + "index": 434, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "const char* func0(const char* text) {\n regex_t regex;\n int ret;\n ret = regcomp(®ex, \"ab+\", REG_EXTENDED);\n if (ret) {\n return \"Regex compilation failed!\";\n }\n ret = regexec(®ex, text, 0, NULL, 0);\n regfree(®ex);\n if (ret == 0) {\n return \"Found a match!\";\n } else {\n return \"Not matched!\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"ac\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"dc\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"abba\"), \"Found a match!\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x58,%rsp\nmov %rdi,%rbx\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nmov $0x1,%edx\nlea 0xe45(%rip),%rsi\ncallq 10c0 \nmov %eax,%edx\nlea 0xe01(%rip),%rax\ntest %edx,%edx\nje 121e \nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 125c \nadd $0x58,%rsp\npop %rbx\npop %rbp\nretq\nmov %rsp,%rbp\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rbx,%rsi\nmov %rbp,%rdi\ncallq 10d0 \nmov %eax,%ebx\nmov %rbp,%rdi\ncallq 1090 \ntest %ebx,%ebx\nlea 0xdcf(%rip),%rax\nlea 0xdd7(%rip),%rdx\ncmovne %rdx,%rax\njmp 1207 \ncallq 10a0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+68h+var_20], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"ab+\"\ncall _regcomp\nmov edx, eax\nlea rax, aRegexCompilati; \"Regex compilation failed!\"\ntest edx, edx\njz short loc_123E\nloc_1227:\nmov rdx, [rsp+68h+var_20]\nsub rdx, fs:28h\njnz short loc_127C\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_123E:\nmov rbp, rsp\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov ebx, eax\nmov rdi, rbp; preg\ncall _regfree\ntest ebx, ebx\nlea rax, s2; \"Not matched!\"\nlea rdx, aFoundAMatch; \"Found a match!\"\ncmovz rax, rdx\njmp short loc_1227\nloc_127C:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // edx\n const char *result; // rax\n int v3; // ebx\n regex_t v4; // [rsp+0h] [rbp-68h] BYREF\n unsigned __int64 v5; // [rsp+48h] [rbp-20h]\n\n v5 = __readfsqword(0x28u);\n v1 = regcomp(&v4, \"ab+\", 1);\n result = \"Regex compilation failed!\";\n if ( !v1 )\n {\n v3 = regexec(&v4, string, 0LL, 0LL, 0);\n regfree(&v4);\n result = \"Not matched!\";\n if ( !v3 )\n return \"Found a match!\";\n }\n return result;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+68h+var_20], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"ab+\"\ncall _regcomp\nmov edx, eax\nlea rax, aRegexCompilati; \"Regex compilation failed!\"\ntest edx, edx\njz short loc_123E\nloc_1227:\nmov rdx, [rsp+68h+var_20]\nsub rdx, fs:28h\njnz short loc_127C\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_123E:\nmov rbp, rsp\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov ebx, eax\nmov rdi, rbp; preg\ncall _regfree\ntest ebx, ebx\nlea rax, s2; \"Not matched!\"\nlea rdx, aFoundAMatch; \"Found a match!\"\ncmovz rax, rdx\njmp short loc_1227\nloc_127C:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_11E9(char *string)\n{\n int v1; // edx\n const char *result; // rax\n int v3; // ebx\n regex_t v4; // [rsp+0h] [rbp-68h] BYREF\n unsigned __int64 v5; // [rsp+48h] [rbp-20h]\n\n v5 = __readfsqword(0x28u);\n v1 = regcomp(&v4, \"ab+\", 1);\n result = \"Regex compilation failed!\";\n if ( !v1 )\n {\n v3 = regexec(&v4, string, 0LL, 0LL, 0);\n regfree(&v4);\n result = \"Not matched!\";\n if ( !v3 )\n return \"Found a match!\";\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_11E9(char *string) {\n int v1;\n const char *result;\n int v3;\n regex_t v4;\n unsigned long long v5;\n v5 = __readfsqword(40u);\n v1 = regcomp(&v4, \"ab+\", 1);\n result = \"Regex compilation failed!\";\n if (!v1) {\n v3 = regexec(&v4, string, 0LL, 0LL, 0);\n regfree(&v4);\n result = \"Not matched!\";\n if (!v3) return \"Found a match!\";\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n const char *result;\n int v3;\n regex_t v4;\n unsigned long long v5;\n v5 = __readfsqword(40u);\n v1 = regcomp(&v4, \"ab+\", 1);\n result = \"Regex compilation failed!\";\n if (!v1) {\n v3 = regexec(&v4, string, 0LL, 0LL, 0);\n regfree(&v4);\n result = \"Not matched!\";\n if (!v3) return \"Found a match!\";\n }\n return result;\n}" + }, + { + "index": 434, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "const char* func0(const char* text) {\n regex_t regex;\n int ret;\n ret = regcomp(®ex, \"ab+\", REG_EXTENDED);\n if (ret) {\n return \"Regex compilation failed!\";\n }\n ret = regexec(®ex, text, 0, NULL, 0);\n regfree(®ex);\n if (ret == 0) {\n return \"Found a match!\";\n } else {\n return \"Not matched!\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"ac\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"dc\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"abba\"), \"Found a match!\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov $0x1,%edx\nlea 0xd78(%rip),%rsi\npush %rbp\nmov %rdi,%rbp\nsub $0x58,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%r12\nmov %r12,%rdi\ncallq 10c0 \nmov %eax,%r8d\nlea 0xd15(%rip),%rax\ntest %r8d,%r8d\njne 1321 \nxor %edx,%edx\nxor %ecx,%ecx\nmov %rbp,%rsi\nmov %r12,%rdi\ncallq 10d0 \nmov %r12,%rdi\nmov %eax,%ebp\ncallq 1090 \ntest %ebp,%ebp\nlea 0xd08(%rip),%rax\nlea 0xd10(%rip),%rdx\ncmovne %rdx,%rax\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 1339 \nadd $0x58,%rsp\npop %rbp\npop %r12\nretq\ncallq 10a0 <__stack_chk_fail@plt>\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"ab+\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nmov edx, eax\nlea rax, aRegexCompilati; \"Regex compilation failed!\"\ntest edx, edx\njnz short loc_1331\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, s2; \"Not matched!\"\nlea rdx, aFoundAMatch; \"Found a match!\"\ncmovz rax, rdx\nloc_1331:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_1348\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1348:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // edx\n const char *result; // rax\n int v3; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n v1 = regcomp(&_0, \"ab+\", 1);\n result = \"Regex compilation failed!\";\n if ( !v1 )\n {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if ( !v3 )\n return \"Found a match!\";\n }\n return result;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"ab+\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nmov edx, eax\nlea rax, aRegexCompilati; \"Regex compilation failed!\"\ntest edx, edx\njnz short loc_1331\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, s2; \"Not matched!\"\nlea rdx, aFoundAMatch; \"Found a match!\"\ncmovz rax, rdx\nloc_1331:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_1348\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1348:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_12C0(char *string)\n{\n int v1; // edx\n const char *result; // rax\n int v3; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n v1 = regcomp(&_0, \"ab+\", 1);\n result = \"Regex compilation failed!\";\n if ( !v1 )\n {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if ( !v3 )\n return \"Found a match!\";\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_12C0(char *string) {\n int v1;\n const char *result;\n int v3;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n v1 = regcomp(&_0, \"ab+\", 1);\n result = \"Regex compilation failed!\";\n if (!v1) {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if (!v3) return \"Found a match!\";\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n const char *result;\n int v3;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n v1 = regcomp(&_0, \"ab+\", 1);\n result = \"Regex compilation failed!\";\n if (!v1) {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if (!v3) return \"Found a match!\";\n }\n return result;\n}" + }, + { + "index": 434, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "const char* func0(const char* text) {\n regex_t regex;\n int ret;\n ret = regcomp(®ex, \"ab+\", REG_EXTENDED);\n if (ret) {\n return \"Regex compilation failed!\";\n }\n ret = regexec(®ex, text, 0, NULL, 0);\n regfree(®ex);\n if (ret == 0) {\n return \"Found a match!\";\n } else {\n return \"Not matched!\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"ac\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"dc\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"abba\"), \"Found a match!\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov $0x1,%edx\nlea 0xd78(%rip),%rsi\npush %rbp\nmov %rdi,%rbp\nsub $0x58,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%r12\nmov %r12,%rdi\ncallq 10c0 \nmov %eax,%r8d\nlea 0xd15(%rip),%rax\ntest %r8d,%r8d\njne 1321 \nxor %edx,%edx\nxor %ecx,%ecx\nmov %rbp,%rsi\nmov %r12,%rdi\ncallq 10d0 \nmov %r12,%rdi\nmov %eax,%ebp\ncallq 1090 \ntest %ebp,%ebp\nlea 0xd08(%rip),%rax\nlea 0xd10(%rip),%rdx\ncmovne %rdx,%rax\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 1339 \nadd $0x58,%rsp\npop %rbp\npop %r12\nretq\ncallq 10a0 <__stack_chk_fail@plt>\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"ab+\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nmov edx, eax\nlea rax, aRegexCompilati; \"Regex compilation failed!\"\ntest edx, edx\njnz short loc_1331\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, s2; \"Not matched!\"\nlea rdx, aFoundAMatch; \"Found a match!\"\ncmovz rax, rdx\nloc_1331:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_1348\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1348:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // edx\n const char *result; // rax\n int v3; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n v1 = regcomp(&_0, \"ab+\", 1);\n result = \"Regex compilation failed!\";\n if ( !v1 )\n {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if ( !v3 )\n return \"Found a match!\";\n }\n return result;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"ab+\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nmov edx, eax\nlea rax, aRegexCompilati; \"Regex compilation failed!\"\ntest edx, edx\njnz short loc_1331\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, s2; \"Not matched!\"\nlea rdx, aFoundAMatch; \"Found a match!\"\ncmovz rax, rdx\nloc_1331:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_1348\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1348:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_12C0(char *string)\n{\n int v1; // edx\n const char *result; // rax\n int v3; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n v1 = regcomp(&_0, \"ab+\", 1);\n result = \"Regex compilation failed!\";\n if ( !v1 )\n {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if ( !v3 )\n return \"Found a match!\";\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_12C0(char *string) {\n int v1;\n const char *result;\n int v3;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n v1 = regcomp(&_0, \"ab+\", 1);\n result = \"Regex compilation failed!\";\n if (!v1) {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if (!v3) return \"Found a match!\";\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n const char *result;\n int v3;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n v1 = regcomp(&_0, \"ab+\", 1);\n result = \"Regex compilation failed!\";\n if (!v1) {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if (!v3) return \"Found a match!\";\n }\n return result;\n}" + }, + { + "index": 435, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) { return n % 10; }", + "test": "int main() {\n\n assert(func0(123) == 3);\n\n assert(func0(25) == 5);\n\n assert(func0(30) == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov -0x4(%rbp),%ecx\nmovslq %ecx,%rax\nimul $0x66666667,%rax,%rax\nshr $0x20,%rax\nmov %eax,%edx\nsar $0x2,%edx\nmov %ecx,%eax\nsar $0x1f,%eax\nsub %eax,%edx\nmov %edx,%eax\nshl $0x2,%eax\nadd %edx,%eax\nadd %eax,%eax\nsub %eax,%ecx\nmov %ecx,%edx\nmov %edx,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov ecx, [rbp+var_4]\nmovsxd rax, ecx\nimul rax, 66666667h\nshr rax, 20h\nmov edx, eax\nsar edx, 2\nmov eax, ecx\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nsub ecx, eax\nmov edx, ecx\nmov eax, edx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n return (unsigned int)(a1 % 10);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov ecx, [rbp+var_4]\nmovsxd rax, ecx\nimul rax, 66666667h\nshr rax, 20h\nmov edx, eax\nsar edx, 2\nmov eax, ecx\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nsub ecx, eax\nmov edx, ecx\nmov eax, edx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n return (unsigned int)(a1 % 10);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) { return (unsigned int)(a1 % 10); }", + "ida_pseudo_norm": "long long func0(int a1) { return (unsigned int)(a1 % 10); }" + }, + { + "index": 436, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int list1[], int size) {\n for (int i = 0; i < size; i++) {\n if (list1[i] < 0) {\n return list1[i];\n }\n }\n return 0;\n}", + "test": "int main() {\n\n int list1[] = {-1, 4, 5, -6};\n\n int list2[] = {-1, -2, 3, 4};\n\n int list3[] = {-7, -6, 8, 9};\n\n\n\n assert(func0(list1, 4) == -1);\n\n assert(func0(list2, 4) == -1);\n\n assert(func0(list3, 4) == -7);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11b7 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ntest %eax,%eax\njns 11b3 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\njmp 11c4 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1181 \nmov $0x0,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 0\njmp short loc_11B7\nloc_1181:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njns short loc_11B3\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\njmp short loc_11C4\nloc_11B3:\nadd [rbp+var_4], 1\nloc_11B7:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1181\nmov eax, 0\nloc_11C4:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n if ( *(int *)(4LL * i + a1) < 0 )\n return *(unsigned int *)(4LL * i + a1);\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 0\njmp short loc_11B7\nloc_1181:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njns short loc_11B3\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\njmp short loc_11C4\nloc_11B3:\nadd [rbp+var_4], 1\nloc_11B7:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1181\nmov eax, 0\nloc_11C4:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n if ( *(int *)(4LL * i + a1) < 0 )\n return *(unsigned int *)(4LL * i + a1);\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int i;\n for (i = 0; i < a2; ++i) {\n if (*(int *)(4LL * i + a1) < 0) return *(unsigned int *)(4LL * i + a1);\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int i;\n for (i = 0; i < a2; ++i) {\n if (*(int *)(4LL * i + a1) < 0) return *(unsigned int *)(4LL * i + a1);\n }\n return 0LL;\n}" + }, + { + "index": 436, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int list1[], int size) {\n for (int i = 0; i < size; i++) {\n if (list1[i] < 0) {\n return list1[i];\n }\n }\n return 0;\n}", + "test": "int main() {\n\n int list1[] = {-1, 4, 5, -6};\n\n int list2[] = {-1, -2, 3, 4};\n\n int list3[] = {-7, -6, 8, 9};\n\n\n\n assert(func0(list1, 4) == -1);\n\n assert(func0(list2, 4) == -1);\n\n assert(func0(list3, 4) == -7);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1193 \nmov %rdi,%rax\nlea -0x1(%rsi),%edx\nlea 0x4(%rdi,%rdx,4),%rcx\nmov (%rax),%edx\ntest %edx,%edx\njs 1190 \nadd $0x4,%rax\ncmp %rcx,%rax\njne 117c \nmov $0x0,%edx\nmov %edx,%eax\nretq\nmov $0x0,%edx\njmp 1190 \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1192\nmov rax, rdi\nmovsxd rsi, esi\nlea rcx, [rdi+rsi*4]\nloc_117B:\nmov edx, [rax]\ntest edx, edx\njs short loc_118F\nadd rax, 4\ncmp rax, rcx\njnz short loc_117B\nmov edx, 0\nloc_118F:\nmov eax, edx\nretn\nloc_1192:\nmov edx, 0\njmp short loc_118F", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n unsigned int *v2; // rax\n unsigned int v3; // edx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n while ( 1 )\n {\n v3 = *v2;\n if ( (*v2 & 0x80000000) != 0 )\n break;\n if ( ++v2 == &a1[a2] )\n return 0;\n }\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_1192\nmov rax, rdi\nmovsxd rsi, esi\nlea rcx, [rdi+rsi*4]\nloc_117B:\nmov edx, [rax]\ntest edx, edx\njs short loc_118F\nadd rax, 4\ncmp rax, rcx\njnz short loc_117B\nmov edx, 0\nloc_118F:\nmov eax, edx\nretn\nloc_1192:\nmov edx, 0\njmp short loc_118F", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(unsigned int *a1, int a2)\n{\n unsigned int *v2; // rax\n unsigned int v3; // edx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n while ( 1 )\n {\n v3 = *v2;\n if ( (*v2 & 0x80000000) != 0 )\n break;\n if ( ++v2 == &a1[a2] )\n return 0;\n }\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(unsigned int *a1, int a2) {\n unsigned int *v2;\n unsigned int v3;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n while (1) {\n v3 = *v2;\n if ((*v2 & 2147483648) != 0) break;\n if (++v2 == &a1[a2]) return 0;\n }\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n unsigned int *v2;\n unsigned int v3;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n while (1) {\n v3 = *v2;\n if ((*v2 & 2147483648) != 0) break;\n if (++v2 == &a1[a2]) return 0;\n }\n }\n return v3;\n}" + }, + { + "index": 437, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* str1) {\n static char str2[100];\n int j = 0;\n for (int i = 1; i <= strlen(str1); i++) {\n if (i % 2 == 0) {\n str2[j++] = str1[i - 1];\n }\n }\n str2[j] = '\\0';\n return str2;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"python\"), \"yhn\") == 0);\n\n assert(strcmp(func0(\"program\"), \"rga\") == 0);\n\n assert(strcmp(func0(\"language\"), \"agae\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x28,%rsp\nmov %rdi,-0x28(%rbp)\nmovl $0x0,-0x18(%rbp)\nmovl $0x1,-0x14(%rbp)\njmp 11e1 \nmov -0x14(%rbp),%eax\nand $0x1,%eax\ntest %eax,%eax\njne 11dd \nmov -0x14(%rbp),%eax\ncltq\nlea -0x1(%rax),%rdx\nmov -0x28(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x18(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x18(%rbp)\nmovzbl (%rcx),%edx\ncltq\nlea 0x2e66(%rip),%rcx\nmov %dl,(%rax,%rcx,1)\naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\nmovslq %eax,%rbx\nmov -0x28(%rbp),%rax\nmov %rax,%rdi\ncallq 1070 \ncmp %rax,%rbx\njbe 11aa \nmov -0x18(%rbp),%eax\ncltq\nlea 0x2e3c(%rip),%rdx\nmovb $0x0,(%rax,%rdx,1)\nlea 0x2e31(%rip),%rax\nadd $0x28,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+s], rdi\nmov [rbp+var_18], 0\nmov [rbp+var_14], 1\njmp short loc_11E1\nloc_11AA:\nmov eax, [rbp+var_14]\nand eax, 1\ntest eax, eax\njnz short loc_11DD\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\nmovzx edx, byte ptr [rcx]\ncdqe\nlea rcx, str2_1\nmov [rax+rcx], dl\nloc_11DD:\nadd [rbp+var_14], 1\nloc_11E1:\nmov eax, [rbp+var_14]\nmovsxd rbx, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rax, rbx\njnb short loc_11AA\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, str2_1\nmov byte ptr [rax+rdx], 0\nlea rax, str2_1\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1)\n{\n int v1; // eax\n int v3; // [rsp+18h] [rbp-18h]\n int i; // [rsp+1Ch] [rbp-14h]\n\n v3 = 0;\n for ( i = 1; strlen(a1) >= i; ++i )\n {\n if ( (i & 1) == 0 )\n {\n v1 = v3++;\n str2_1[v1] = a1[i - 1];\n }\n }\n str2_1[v3] = 0;\n return str2_1;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+s], rdi\nmov [rbp+var_18], 0\nmov [rbp+var_14], 1\njmp short loc_11E1\nloc_11AA:\nmov eax, [rbp+var_14]\nand eax, 1\ntest eax, eax\njnz short loc_11DD\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\nmovzx edx, byte ptr [rcx]\ncdqe\nlea rcx, unk_4040\nmov [rax+rcx], dl\nloc_11DD:\nadd [rbp+var_14], 1\nloc_11E1:\nmov eax, [rbp+var_14]\nmovsxd rbx, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rax, rbx\njnb short loc_11AA\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, unk_4040\nmov byte ptr [rax+rdx], 0\nlea rax, unk_4040\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1189(const char *a1)\n{\n int v1; // eax\n int v3; // [rsp+18h] [rbp-18h]\n int i; // [rsp+1Ch] [rbp-14h]\n\n v3 = 0;\n for ( i = 1; strlen(a1) >= i; ++i )\n {\n if ( (i & 1) == 0 )\n {\n v1 = v3++;\n byte_4040[v1] = a1[i - 1];\n }\n }\n byte_4040[v3] = 0;\n return byte_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1189(const char *a1) {\n int v1;\n int v3;\n int i;\n v3 = 0;\n for (i = 1; strlen(a1) >= i; ++i) {\n if ((i & 1) == 0) {\n v1 = v3++;\n byte_4040[v1] = a1[i - 1];\n }\n }\n byte_4040[v3] = 0;\n return byte_4040;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1) {\n int v1;\n int v3;\n int i;\n v3 = 0;\n for (i = 1; strlen(a1) >= i; ++i) {\n if ((i & 1) == 0) {\n v1 = v3++;\n str2_1[v1] = a1[i - 1];\n }\n }\n str2_1[v3] = 0;\n return str2_1;\n}" + }, + { + "index": 437, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* str1) {\n static char str2[100];\n int j = 0;\n for (int i = 1; i <= strlen(str1); i++) {\n if (i % 2 == 0) {\n str2[j++] = str1[i - 1];\n }\n }\n str2[j] = '\\0';\n return str2;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"python\"), \"yhn\") == 0);\n\n assert(strcmp(func0(\"program\"), \"rga\") == 0);\n\n assert(strcmp(func0(\"language\"), \"agae\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%r8\nmov $0x1,%edx\nmov $0x0,%esi\nmov $0xffffffffffffffff,%r9\nmov $0x0,%eax\nlea 0x2ed3(%rip),%r10\njmp 1173 \nadd $0x1,%rdx\nmov %r9,%rcx\nmov %r8,%rdi\nrepnz scas %es:(%rdi),%al\nnot %rcx\nsub $0x1,%rcx\ncmp %rdx,%rcx\njb 119e \ntest $0x1,%dl\njne 116f \nmovzbl -0x1(%r8,%rdx,1),%edi\nmovslq %esi,%rcx\nmov %dil,(%r10,%rcx,1)\nlea 0x1(%rsi),%esi\njmp 116f \nlea 0x2e9b(%rip),%rax\nmovslq %esi,%rsi\nmovb $0x0,(%rax,%rsi,1)\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12, rdi\nmov ebx, 1\nmov ebp, 0\nlea r13, str2_1\njmp short loc_11B1\nloc_11AD:\nadd rbx, 1\nloc_11B1:\nmov rdi, r12; s\ncall _strlen\ncmp rax, rbx\njb short loc_11D6\ntest bl, 1\njnz short loc_11AD\nmovzx edx, byte ptr [r12+rbx-1]\nmovsxd rax, ebp\nmov [r13+rax+0], dl\nlea ebp, [rbp+1]\njmp short loc_11AD\nloc_11D6:\nlea rax, str2_1\nmovsxd rbp, ebp\nmov byte ptr [rax+rbp], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(char *s)\n{\n size_t v1; // rbx\n int v2; // ebp\n _BYTE *result; // rax\n\n v1 = 1LL;\n v2 = 0;\n while ( strlen(s) >= v1 )\n {\n if ( (v1 & 1) == 0 )\n str2_1[v2++] = s[v1 - 1];\n ++v1;\n }\n result = str2_1;\n str2_1[v2] = 0;\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12, rdi\nmov ebx, 1\nmov ebp, 0\nlea r13, unk_4040\njmp short loc_11B1\nloc_11AD:\nadd rbx, 1\nloc_11B1:\nmov rdi, r12; s\ncall _strlen\ncmp rax, rbx\njb short loc_11D6\ntest bl, 1\njnz short loc_11AD\nmovzx edx, byte ptr [r12+rbx-1]\nmovsxd rax, ebp\nmov [r13+rax+0], dl\nlea ebp, [rbp+1]\njmp short loc_11AD\nloc_11D6:\nlea rax, unk_4040\nmovsxd rbp, ebp\nmov byte ptr [rax+rbp], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1189(char *s)\n{\n size_t v1; // rbx\n int v2; // ebp\n _BYTE *result; // rax\n\n v1 = 1LL;\n v2 = 0;\n while ( strlen(s) >= v1 )\n {\n if ( (v1 & 1) == 0 )\n byte_4040[v2++] = s[v1 - 1];\n ++v1;\n }\n result = byte_4040;\n byte_4040[v2] = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1189(char *s) {\n unsigned int v1;\n int v2;\n uint8_t *result;\n v1 = 1LL;\n v2 = 0;\n while (strlen(s) >= v1) {\n if ((v1 & 1) == 0) byte_4040[v2++] = s[v1 - 1];\n ++v1;\n }\n result = byte_4040;\n byte_4040[v2] = 0;\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(char *s) {\n unsigned int v1;\n int v2;\n uint8_t *result;\n v1 = 1LL;\n v2 = 0;\n while (strlen(s) >= v1) {\n if ((v1 & 1) == 0) str2_1[v2++] = s[v1 - 1];\n ++v1;\n }\n result = str2_1;\n str2_1[v2] = 0;\n return result;\n}" + }, + { + "index": 437, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* str1) {\n static char str2[100];\n int j = 0;\n for (int i = 1; i <= strlen(str1); i++) {\n if (i % 2 == 0) {\n str2[j++] = str1[i - 1];\n }\n }\n str2[j] = '\\0';\n return str2;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"python\"), \"yhn\") == 0);\n\n assert(strcmp(func0(\"program\"), \"rga\") == 0);\n\n assert(strcmp(func0(\"language\"), \"agae\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov %rdi,%r13\npush %r12\npush %rbp\nlea 0x2ddd(%rip),%rbp\npush %rbx\nmov $0x1,%ebx\nsub $0x8,%rsp\ncallq 1060 \nxor %edx,%edx\njmp 12a2 \nnopw %cs:0x0(%rax,%rax,1)\ntest $0x1,%bl\njne 129e \nmovzbl -0x1(%r13,%rbx,1),%eax\nlea 0x1(%rdx),%r12d\nmov %r13,%rdi\nmov %al,0x0(%rbp,%rdx,1)\ncallq 1060 \nmovslq %r12d,%rdx\nadd $0x1,%rbx\ncmp %rax,%rbx\njbe 1280 \nmovb $0x0,0x0(%rbp,%rdx,1)\nadd $0x8,%rsp\nlea 0x2d89(%rip),%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r13\nlea r13, str2_1\npush r12\nmov r12, rdi\npush rbp\nxor ebp, ebp\npush rbx\nmov ebx, 1\nsub rsp, 8\njmp short loc_12A2\nloc_1288:\ntest bl, 1\njnz short loc_129E\nmovzx edx, byte ptr [r12+rbx-1]\nmovsxd rax, ebp\nadd ebp, 1\nmov [r13+rax+0], dl\nloc_129E:\nadd rbx, 1\nloc_12A2:\nmov rdi, r12; s\ncall _strlen\ncmp rax, rbx\njnb short loc_1288\nmovsxd rbp, ebp\nmov rax, r13\nmov byte ptr [r13+rbp+0], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(char *s)\n{\n int v1; // ebp\n size_t i; // rbx\n __int64 v3; // rax\n _BYTE *result; // rax\n\n v1 = 0;\n for ( i = 1LL; strlen(s) >= i; ++i )\n {\n if ( (i & 1) == 0 )\n {\n v3 = v1++;\n str2_1[v3] = s[i - 1];\n }\n }\n result = str2_1;\n str2_1[v1] = 0;\n return result;\n}", + "ida_strip_asm": "sub_1260:\nendbr64\npush r13\nlea r13, unk_4040\npush r12\nmov r12, rdi\npush rbp\nxor ebp, ebp\npush rbx\nmov ebx, 1\nsub rsp, 8\njmp short loc_12A2\nloc_1288:\ntest bl, 1\njnz short loc_129E\nmovzx edx, byte ptr [r12+rbx-1]\nmovsxd rax, ebp\nadd ebp, 1\nmov [r13+rax+0], dl\nloc_129E:\nadd rbx, 1\nloc_12A2:\nmov rdi, r12; s\ncall _strlen\ncmp rax, rbx\njnb short loc_1288\nmovsxd rbp, ebp\nmov rax, r13\nmov byte ptr [r13+rbp+0], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1260(char *s)\n{\n int v1; // ebp\n size_t i; // rbx\n __int64 v3; // rax\n _BYTE *result; // rax\n\n v1 = 0;\n for ( i = 1LL; strlen(s) >= i; ++i )\n {\n if ( (i & 1) == 0 )\n {\n v3 = v1++;\n byte_4040[v3] = s[i - 1];\n }\n }\n result = byte_4040;\n byte_4040[v1] = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1260(char *s) {\n int v1;\n unsigned int i;\n long long v3;\n uint8_t *result;\n v1 = 0;\n for (i = 1LL; strlen(s) >= i; ++i) {\n if ((i & 1) == 0) {\n v3 = v1++;\n byte_4040[v3] = s[i - 1];\n }\n }\n result = byte_4040;\n byte_4040[v1] = 0;\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(char *s) {\n int v1;\n unsigned int i;\n long long v3;\n uint8_t *result;\n v1 = 0;\n for (i = 1LL; strlen(s) >= i; ++i) {\n if ((i & 1) == 0) {\n v3 = v1++;\n str2_1[v3] = s[i - 1];\n }\n }\n result = str2_1;\n str2_1[v1] = 0;\n return result;\n}" + }, + { + "index": 437, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* str1) {\n static char str2[100];\n int j = 0;\n for (int i = 1; i <= strlen(str1); i++) {\n if (i % 2 == 0) {\n str2[j++] = str1[i - 1];\n }\n }\n str2[j] = '\\0';\n return str2;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"python\"), \"yhn\") == 0);\n\n assert(strcmp(func0(\"program\"), \"rga\") == 0);\n\n assert(strcmp(func0(\"language\"), \"agae\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\nmov %rdi,%r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\ncallq 1060 \ntest %rax,%rax\nje 12d8 \nxor %edx,%edx\nmov $0x1,%ebx\nlea 0x2dc7(%rip),%rbp\nnopl 0x0(%rax)\ntest $0x1,%bl\njne 12ac \nmovzbl -0x1(%r12,%rbx,1),%eax\nmov %r12,%rdi\nlea 0x1(%rdx),%r13d\nadd $0x1,%rbx\nmov %al,0x0(%rbp,%rdx,1)\ncallq 1060 \ncmp %rax,%rbx\nja 12b8 \nmovslq %r13d,%rdx\ntest $0x1,%bl\nje 1285 \nadd $0x1,%rbx\ncmp %rax,%rbx\njbe 1280 \nmov %edx,%r13d\nmovslq %r13d,%r13\nlea 0x2d7e(%rip),%rax\nmovb $0x0,0x0(%rbp,%r13,1)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax,%rax,1)\nxor %r13d,%r13d\nlea 0x2d5e(%rip),%rbp\njmp 12b8 \nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r13\nlea r13, str2_1\npush r12\nmov r12, rdi\npush rbp\nxor ebp, ebp\npush rbx\nmov ebx, 1\nsub rsp, 8\njmp short loc_12A2\nloc_1288:\ntest bl, 1\njnz short loc_129E\nmovzx edx, byte ptr [r12+rbx-1]\nmovsxd rax, ebp\nadd ebp, 1\nmov [r13+rax+0], dl\nloc_129E:\nadd rbx, 1\nloc_12A2:\nmov rdi, r12; s\ncall _strlen\ncmp rax, rbx\njnb short loc_1288\nmovsxd rbp, ebp\nmov rax, r13\nmov byte ptr [r13+rbp+0], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(char *s)\n{\n int v1; // ebp\n size_t i; // rbx\n __int64 v3; // rax\n _BYTE *result; // rax\n\n v1 = 0;\n for ( i = 1LL; strlen(s) >= i; ++i )\n {\n if ( (i & 1) == 0 )\n {\n v3 = v1++;\n str2_1[v3] = s[i - 1];\n }\n }\n result = str2_1;\n str2_1[v1] = 0;\n return result;\n}", + "ida_strip_asm": "sub_1260:\nendbr64\npush r13\nlea r13, unk_4040\npush r12\nmov r12, rdi\npush rbp\nxor ebp, ebp\npush rbx\nmov ebx, 1\nsub rsp, 8\njmp short loc_12A2\nloc_1288:\ntest bl, 1\njnz short loc_129E\nmovzx edx, byte ptr [r12+rbx-1]\nmovsxd rax, ebp\nadd ebp, 1\nmov [r13+rax+0], dl\nloc_129E:\nadd rbx, 1\nloc_12A2:\nmov rdi, r12; s\ncall _strlen\ncmp rax, rbx\njnb short loc_1288\nmovsxd rbp, ebp\nmov rax, r13\nmov byte ptr [r13+rbp+0], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1260(char *s)\n{\n int v1; // ebp\n size_t i; // rbx\n __int64 v3; // rax\n _BYTE *result; // rax\n\n v1 = 0;\n for ( i = 1LL; strlen(s) >= i; ++i )\n {\n if ( (i & 1) == 0 )\n {\n v3 = v1++;\n byte_4040[v3] = s[i - 1];\n }\n }\n result = byte_4040;\n byte_4040[v1] = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1260(char *s) {\n int v1;\n unsigned int i;\n long long v3;\n uint8_t *result;\n v1 = 0;\n for (i = 1LL; strlen(s) >= i; ++i) {\n if ((i & 1) == 0) {\n v3 = v1++;\n byte_4040[v3] = s[i - 1];\n }\n }\n result = byte_4040;\n byte_4040[v1] = 0;\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(char *s) {\n int v1;\n unsigned int i;\n long long v3;\n uint8_t *result;\n v1 = 0;\n for (i = 1LL; strlen(s) >= i; ++i) {\n if ((i & 1) == 0) {\n v3 = v1++;\n str2_1[v3] = s[i - 1];\n }\n }\n result = str2_1;\n str2_1[v1] = 0;\n return result;\n}" + }, + { + "index": 438, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n} pair;\n\n\n\n", + "func": "char* func0(pair test_list[], int len) {\n int res = 0;\n for (int idx = 0; idx < len; idx++) {\n for (int iidx = idx + 1; iidx < len; iidx++) {\n if (test_list[iidx].first == test_list[idx].second &&\n test_list[idx].second == test_list[iidx].first) {\n res += 1;\n }\n }\n }\n char* str = malloc(12);\n sprintf(str, \"%d\", res);\n return str;\n}", + "test": "int main(){\n\n pair test1[] = { {5,6}, {1,2}, {6,5}, {9,1}, {6,5}, {2,1} };\n\n char* res1 = func0(test1, 6);\n\n assert(strcmp(res1, \"3\") == 0);\n\n free(res1);\n\n\n\n pair test2[] = { {5,6}, {1,3}, {6,5}, {9,1}, {6,5}, {2,1} };\n\n char* res2 = func0(test2, 6);\n\n assert(strcmp(res2, \"2\") == 0);\n\n free(res2);\n\n\n\n pair test3[] = { {5,6}, {1,2}, {6,5}, {9,2}, {6,5}, {2,1} };\n\n char* res3 = func0(test3, 6);\n\n assert(strcmp(res3, \"4\") == 0);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmovl $0x0,-0x14(%rbp)\nmovl $0x0,-0x10(%rbp)\njmpq 1290 \nmov -0x10(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0xc(%rbp)\njmp 1284 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov 0x4(%rax),%eax\ncmp %eax,%edx\njne 1280 \nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov 0x4(%rax),%edx\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 1280 \naddl $0x1,-0x14(%rbp)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 121a \naddl $0x1,-0x10(%rbp)\nmov -0x10(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 120f \nmov $0xc,%edi\ncallq 10e0 \nmov %rax,-0x8(%rbp)\nmov -0x14(%rbp),%edx\nmov -0x8(%rbp),%rax\nlea 0xd50(%rip),%rsi\nmov %rax,%rdi\nmov $0x0,%eax\ncallq 10f0 \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\njmp loc_1290\nloc_120F:\nmov eax, [rbp+var_10]\nadd eax, 1\nmov [rbp+var_C], eax\njmp short loc_1284\nloc_121A:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax+4]\ncmp edx, eax\njnz short loc_1280\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax+4]\nmov eax, [rbp+var_C]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_1280\nadd [rbp+var_14], 1\nloc_1280:\nadd [rbp+var_C], 1\nloc_1284:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_2C]\njl short loc_121A\nadd [rbp+var_10], 1\nloc_1290:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_2C]\njl loc_120F\nmov edi, 0Ch; size\ncall _malloc\nmov [rbp+s], rax\nmov edx, [rbp+var_14]\nmov rax, [rbp+s]\nlea rcx, format; \"%d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nmov rax, [rbp+s]\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2)\n{\n int v3; // [rsp+1Ch] [rbp-14h]\n int i; // [rsp+20h] [rbp-10h]\n int j; // [rsp+24h] [rbp-Ch]\n char *s; // [rsp+28h] [rbp-8h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( *(_DWORD *)(8LL * j + a1) == *(_DWORD *)(8LL * i + a1 + 4) )\n ++v3;\n }\n }\n s = (char *)malloc(0xCuLL);\n sprintf(s, \"%d\", v3);\n return s;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\njmp loc_1290\nloc_120F:\nmov eax, [rbp+var_10]\nadd eax, 1\nmov [rbp+var_C], eax\njmp short loc_1284\nloc_121A:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax+4]\ncmp edx, eax\njnz short loc_1280\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax+4]\nmov eax, [rbp+var_C]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_1280\nadd [rbp+var_14], 1\nloc_1280:\nadd [rbp+var_C], 1\nloc_1284:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_2C]\njl short loc_121A\nadd [rbp+var_10], 1\nloc_1290:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_2C]\njl loc_120F\nmov edi, 0Ch; size\ncall _malloc\nmov [rbp+s], rax\nmov edx, [rbp+var_14]\nmov rax, [rbp+s]\nlea rcx, format; \"%d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nmov rax, [rbp+s]\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11E9(__int64 a1, int a2)\n{\n int v3; // [rsp+1Ch] [rbp-14h]\n int i; // [rsp+20h] [rbp-10h]\n int j; // [rsp+24h] [rbp-Ch]\n char *s; // [rsp+28h] [rbp-8h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( *(_DWORD *)(8LL * j + a1) == *(_DWORD *)(8LL * i + a1 + 4) )\n ++v3;\n }\n }\n s = (char *)malloc(0xCuLL);\n sprintf(s, \"%d\", v3);\n return s;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11E9(long long a1, int a2) {\n int v3;\n int i;\n int j;\n char *s;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if (*(uint32_t *)(8LL * j + a1) == *(uint32_t *)(8LL * i + a1 + 4)) ++v3;\n }\n }\n s = (char *)malloc(12uLL);\n sprintf(s, \"%d\", v3);\n return s;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2) {\n int v3;\n int i;\n int j;\n char *s;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if (*(uint32_t *)(8LL * j + a1) == *(uint32_t *)(8LL * i + a1 + 4)) ++v3;\n }\n }\n s = (char *)malloc(12uLL);\n sprintf(s, \"%d\", v3);\n return s;\n}" + }, + { + "index": 438, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n} pair;\n\n\n\n", + "func": "char* func0(pair test_list[], int len) {\n int res = 0;\n for (int idx = 0; idx < len; idx++) {\n for (int iidx = idx + 1; iidx < len; iidx++) {\n if (test_list[iidx].first == test_list[idx].second &&\n test_list[idx].second == test_list[iidx].first) {\n res += 1;\n }\n }\n }\n char* str = malloc(12);\n sprintf(str, \"%d\", res);\n return str;\n}", + "test": "int main(){\n\n pair test1[] = { {5,6}, {1,2}, {6,5}, {9,1}, {6,5}, {2,1} };\n\n char* res1 = func0(test1, 6);\n\n assert(strcmp(res1, \"3\") == 0);\n\n free(res1);\n\n\n\n pair test2[] = { {5,6}, {1,3}, {6,5}, {9,1}, {6,5}, {2,1} };\n\n char* res2 = func0(test2, 6);\n\n assert(strcmp(res2, \"2\") == 0);\n\n free(res2);\n\n\n\n pair test3[] = { {5,6}, {1,2}, {6,5}, {9,2}, {6,5}, {2,1} };\n\n char* res3 = func0(test3, 6);\n\n assert(strcmp(res3, \"4\") == 0);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\ntest %esi,%esi\njle 122d \nlea -0x1(%rsi),%r10d\nmov %r10d,%r11d\nadd $0x1,%r11\nmov %rdi,%r9\nmov $0x1,%r8d\nmov $0x0,%ebx\nadd $0x8,%rdi\ncmp %r11,%r8\nje 1232 \nmov 0x4(%r9),%esi\nmov %r10d,%eax\nsub %r8d,%eax\nlea -0x1(%r8,%rax,1),%rax\nlea (%rdi,%rax,8),%rcx\nmov %r9,%rax\ncmp %esi,0x8(%rax)\nsete %dl\nmovzbl %dl,%edx\nadd %edx,%ebx\nadd $0x8,%rax\ncmp %rcx,%rax\njne 120f \nadd $0x1,%r8\nadd $0x8,%r9\njmp 11f4 \nmov $0x0,%ebx\nmov $0xc,%edi\ncallq 10c0 \nmov %rax,%rbp\nmov %ebx,%r8d\nlea 0xdbb(%rip),%rcx\nmov $0xc,%edx\nmov $0x1,%esi\nmov %rax,%rdi\nmov $0x0,%eax\ncallq 10d0 <__sprintf_chk@plt>\nmov %rbp,%rax\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\ntest esi, esi\njle short loc_124F\nlea r10d, [rsi-1]\nmovsxd r11, esi\nmov r9, rdi\nmov r8d, 0\nmov ebx, 0\nsub esi, 2\nadd rdi, 8\njmp short loc_1235\nloc_1215:\nadd rax, 8\ncmp rax, rdx\njz short loc_1228\nloc_121E:\ncmp [rax+8], ecx\njnz short loc_1215\nadd ebx, 1\njmp short loc_1215\nloc_1228:\nadd r8, 1\nadd r9, 8\ncmp r8, r11\njz short loc_1254\nloc_1235:\ncmp r8, r10\njz short loc_1254\nmov ecx, [r9+4]\nmov eax, esi\nsub eax, r8d\nadd rax, r8\nlea rdx, [rdi+rax*8]\nmov rax, r9\njmp short loc_121E\nloc_124F:\nmov ebx, 0\nloc_1254:\nmov edi, 0Ch; size\ncall _malloc\nmov rbp, rax\nmov r8d, ebx\nlea rcx, unk_2004\nmov edx, 0Ch\nmov esi, 2\nmov rdi, rax\nmov eax, 0\ncall ___sprintf_chk\nmov rax, rbp\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_pseudo": "void *__fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // r10\n __int64 v3; // r11\n __int64 v4; // r9\n __int64 v5; // r8\n unsigned int v6; // ebx\n int v7; // esi\n __int64 v8; // rdi\n __int64 v9; // rax\n void *v10; // rbp\n\n if ( a2 <= 0 )\n {\n v6 = 0;\n }\n else\n {\n v2 = (unsigned int)(a2 - 1);\n v3 = a2;\n v4 = a1;\n v5 = 0LL;\n v6 = 0;\n v7 = a2 - 2;\n v8 = a1 + 8;\n do\n {\n if ( v5 == v2 )\n break;\n v9 = v4;\n do\n {\n if ( *(_DWORD *)(v9 + 8) == *(_DWORD *)(v4 + 4) )\n ++v6;\n v9 += 8LL;\n }\n while ( v9 != v8 + 8 * (v5 + (unsigned int)(v7 - v5)) );\n ++v5;\n v4 += 8LL;\n }\n while ( v5 != v3 );\n }\n v10 = malloc(0xCuLL);\n __sprintf_chk(v10, 2LL, 12LL, &unk_2004, v6);\n return v10;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\ntest esi, esi\njle short loc_124F\nlea r10d, [rsi-1]\nmovsxd r11, esi\nmov r9, rdi\nmov r8d, 0\nmov ebx, 0\nsub esi, 2\nadd rdi, 8\njmp short loc_1235\nloc_1215:\nadd rax, 8\ncmp rax, rdx\njz short loc_1228\nloc_121E:\ncmp [rax+8], ecx\njnz short loc_1215\nadd ebx, 1\njmp short loc_1215\nloc_1228:\nadd r8, 1\nadd r9, 8\ncmp r8, r11\njz short loc_1254\nloc_1235:\ncmp r8, r10\njz short loc_1254\nmov ecx, [r9+4]\nmov eax, esi\nsub eax, r8d\nadd rax, r8\nlea rdx, [rdi+rax*8]\nmov rax, r9\njmp short loc_121E\nloc_124F:\nmov ebx, 0\nloc_1254:\nmov edi, 0Ch; size\ncall _malloc\nmov rbp, rax\nmov r8d, ebx\nlea rcx, unk_2004\nmov edx, 0Ch\nmov esi, 2\nmov rdi, rax\nmov eax, 0\ncall ___sprintf_chk\nmov rax, rbp\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "void *__fastcall sub_11E9(__int64 a1, int a2)\n{\n __int64 v2; // r10\n __int64 v3; // r11\n __int64 v4; // r9\n __int64 v5; // r8\n unsigned int v6; // ebx\n int v7; // esi\n __int64 v8; // rdi\n __int64 v9; // rax\n void *v10; // rbp\n\n if ( a2 <= 0 )\n {\n v6 = 0;\n }\n else\n {\n v2 = (unsigned int)(a2 - 1);\n v3 = a2;\n v4 = a1;\n v5 = 0LL;\n v6 = 0;\n v7 = a2 - 2;\n v8 = a1 + 8;\n do\n {\n if ( v5 == v2 )\n break;\n v9 = v4;\n do\n {\n if ( *(_DWORD *)(v9 + 8) == *(_DWORD *)(v4 + 4) )\n ++v6;\n v9 += 8LL;\n }\n while ( v9 != v8 + 8 * (v5 + (unsigned int)(v7 - v5)) );\n ++v5;\n v4 += 8LL;\n }\n while ( v5 != v3 );\n }\n v10 = malloc(0xCuLL);\n __sprintf_chk(v10, 2LL, 12LL, &unk_2004, v6);\n return v10;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_11E9(long long a1, int a2) {\n long long v2;\n long long v3;\n long long v4;\n long long v5;\n unsigned int v6;\n int v7;\n long long v8;\n long long v9;\n void *v10;\n if (a2 <= 0) {\n v6 = 0;\n } else {\n v2 = (unsigned int)(a2 - 1);\n v3 = a2;\n v4 = a1;\n v5 = 0LL;\n v6 = 0;\n v7 = a2 - 2;\n v8 = a1 + 8;\n do {\n if (v5 == v2) break;\n v9 = v4;\n do {\n if (*(uint32_t *)(v9 + 8) == *(uint32_t *)(v4 + 4)) ++v6;\n v9 += 8LL;\n } while (v9 != v8 + 8 * (v5 + (unsigned int)(v7 - v5)));\n ++v5;\n v4 += 8LL;\n } while (v5 != v3);\n }\n v10 = malloc(12uLL);\n __sprintf_chk(v10, 2LL, 12LL, &unk_2004, v6);\n return v10;\n}", + "ida_pseudo_norm": "void *func0(long long a1, int a2) {\n long long v2;\n long long v3;\n long long v4;\n long long v5;\n unsigned int v6;\n int v7;\n long long v8;\n long long v9;\n void *v10;\n if (a2 <= 0) {\n v6 = 0;\n } else {\n v2 = (unsigned int)(a2 - 1);\n v3 = a2;\n v4 = a1;\n v5 = 0LL;\n v6 = 0;\n v7 = a2 - 2;\n v8 = a1 + 8;\n do {\n if (v5 == v2) break;\n v9 = v4;\n do {\n if (*(uint32_t *)(v9 + 8) == *(uint32_t *)(v4 + 4)) ++v6;\n v9 += 8LL;\n } while (v9 != v8 + 8 * (v5 + (unsigned int)(v7 - v5)));\n ++v5;\n v4 += 8LL;\n } while (v5 != v3);\n }\n v10 = malloc(12uLL);\n __sprintf_chk(v10, 2LL, 12LL, &unk_2004, v6);\n return v10;\n}" + }, + { + "index": 438, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n} pair;\n\n\n\n", + "func": "char* func0(pair test_list[], int len) {\n int res = 0;\n for (int idx = 0; idx < len; idx++) {\n for (int iidx = idx + 1; iidx < len; iidx++) {\n if (test_list[iidx].first == test_list[idx].second &&\n test_list[idx].second == test_list[iidx].first) {\n res += 1;\n }\n }\n }\n char* str = malloc(12);\n sprintf(str, \"%d\", res);\n return str;\n}", + "test": "int main(){\n\n pair test1[] = { {5,6}, {1,2}, {6,5}, {9,1}, {6,5}, {2,1} };\n\n char* res1 = func0(test1, 6);\n\n assert(strcmp(res1, \"3\") == 0);\n\n free(res1);\n\n\n\n pair test2[] = { {5,6}, {1,3}, {6,5}, {9,1}, {6,5}, {2,1} };\n\n char* res2 = func0(test2, 6);\n\n assert(strcmp(res2, \"2\") == 0);\n\n free(res2);\n\n\n\n pair test3[] = { {5,6}, {1,2}, {6,5}, {9,2}, {6,5}, {2,1} };\n\n char* res3 = func0(test3, 6);\n\n assert(strcmp(res3, \"4\") == 0);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbx\nsub $0x8,%rsp\ntest %esi,%esi\njle 1436 \nlea -0x1(%rsi),%r10d\nmov %rdi,%r8\nmov $0x1,%edi\nxor %ebx,%ebx\nmov %r10,%r9\nadd $0x1,%r10\nlea 0x8(%r8),%r11\ncmp %r10,%rdi\nje 1400 \nnopl 0x0(%rax)\nmov %r9d,%eax\nmov 0x4(%r8),%esi\nsub %edi,%eax\nlea -0x1(%rdi,%rax,1),%rax\nlea (%r11,%rax,8),%rcx\nmov %r8,%rax\nnopl (%rax)\nxor %edx,%edx\ncmp %esi,0x8(%rax)\nsete %dl\nadd $0x8,%rax\nadd %edx,%ebx\ncmp %rcx,%rax\njne 13e0 \nadd $0x1,%rdi\nadd $0x8,%r8\ncmp %r10,%rdi\njne 13c8 \nmov $0xc,%edi\ncallq 10c0 \nmov %ebx,%r8d\nmov $0xc,%edx\nlea 0xbeb(%rip),%rcx\nmov %rax,%r12\nmov %rax,%rdi\nmov $0x1,%esi\nxor %eax,%eax\ncallq 10d0 <__sprintf_chk@plt>\nadd $0x8,%rsp\nmov %r12,%rax\npop %rbx\npop %r12\nretq\nxor %ebx,%ebx\njmp 1400 \nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\ntest esi, esi\njle short loc_13CE\nmov r8d, esi\nmov ecx, 1\nxor ebx, ebx\ncmp esi, 1\njz short loc_1399\nnop dword ptr [rax]\nloc_1370:\nmov edx, [rdi+rcx*8-4]\nmov rax, rcx\nnop word ptr [rax+rax+00000000h]\nloc_1380:\ncmp edx, [rdi+rax*8]\njnz short loc_1388\nadd ebx, 1\nloc_1388:\nadd rax, 1\ncmp esi, eax\njg short loc_1380\nadd rcx, 1\ncmp rcx, r8\njnz short loc_1370\nloc_1399:\nmov edi, 0Ch; size\ncall _malloc\nmov r8d, ebx\nmov edx, 0Ch\nlea rcx, unk_2004\nmov rbp, rax\nmov rdi, rax\nmov esi, 2\nxor eax, eax\ncall ___sprintf_chk\nadd rsp, 8\nmov rax, rbp\npop rbx\npop rbp\nretn\nloc_13CE:\nxor ebx, ebx\njmp short loc_1399", + "ida_pseudo": "void *__fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // rcx\n unsigned int v3; // ebx\n __int64 v4; // rax\n void *v5; // rbp\n\n if ( a2 <= 0 )\n {\n v3 = 0;\n }\n else\n {\n v2 = 1LL;\n v3 = 0;\n if ( a2 != 1 )\n {\n do\n {\n v4 = v2;\n do\n {\n if ( *(_DWORD *)(a1 + 8 * v2 - 4) == *(_DWORD *)(a1 + 8 * v4) )\n ++v3;\n ++v4;\n }\n while ( a2 > (int)v4 );\n ++v2;\n }\n while ( v2 != a2 );\n }\n }\n v5 = malloc(0xCuLL);\n __sprintf_chk(v5, 2LL, 12LL, &unk_2004, v3);\n return v5;\n}", + "ida_strip_asm": "sub_1350:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\ntest esi, esi\njle short loc_13CE\nmov r8d, esi\nmov ecx, 1\nxor ebx, ebx\ncmp esi, 1\njz short loc_1399\nnop dword ptr [rax]\nloc_1370:\nmov edx, [rdi+rcx*8-4]\nmov rax, rcx\nnop word ptr [rax+rax+00000000h]\nloc_1380:\ncmp edx, [rdi+rax*8]\njnz short loc_1388\nadd ebx, 1\nloc_1388:\nadd rax, 1\ncmp esi, eax\njg short loc_1380\nadd rcx, 1\ncmp rcx, r8\njnz short loc_1370\nloc_1399:\nmov edi, 0Ch; size\ncall _malloc\nmov r8d, ebx\nmov edx, 0Ch\nlea rcx, unk_2004\nmov rbp, rax\nmov rdi, rax\nmov esi, 2\nxor eax, eax\ncall ___sprintf_chk\nadd rsp, 8\nmov rax, rbp\npop rbx\npop rbp\nretn\nloc_13CE:\nxor ebx, ebx\njmp short loc_1399", + "ida_strip_pseudo": "void *__fastcall sub_1350(__int64 a1, int a2)\n{\n __int64 v2; // rcx\n unsigned int v3; // ebx\n __int64 v4; // rax\n void *v5; // rbp\n\n if ( a2 <= 0 )\n {\n v3 = 0;\n }\n else\n {\n v2 = 1LL;\n v3 = 0;\n if ( a2 != 1 )\n {\n do\n {\n v4 = v2;\n do\n {\n if ( *(_DWORD *)(a1 + 8 * v2 - 4) == *(_DWORD *)(a1 + 8 * v4) )\n ++v3;\n ++v4;\n }\n while ( a2 > (int)v4 );\n ++v2;\n }\n while ( v2 != a2 );\n }\n }\n v5 = malloc(0xCuLL);\n __sprintf_chk(v5, 2LL, 12LL, &unk_2004, v3);\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1350(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n long long v4;\n void *v5;\n if (a2 <= 0) {\n v3 = 0;\n } else {\n v2 = 1LL;\n v3 = 0;\n if (a2 != 1) {\n do {\n v4 = v2;\n do {\n if (*(uint32_t *)(a1 + 8 * v2 - 4) == *(uint32_t *)(a1 + 8 * v4))\n ++v3;\n ++v4;\n } while (a2 > (int)v4);\n ++v2;\n } while (v2 != a2);\n }\n }\n v5 = malloc(12uLL);\n __sprintf_chk(v5, 2LL, 12LL, &unk_2004, v3);\n return v5;\n}", + "ida_pseudo_norm": "void *func0(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n long long v4;\n void *v5;\n if (a2 <= 0) {\n v3 = 0;\n } else {\n v2 = 1LL;\n v3 = 0;\n if (a2 != 1) {\n do {\n v4 = v2;\n do {\n if (*(uint32_t *)(a1 + 8 * v2 - 4) == *(uint32_t *)(a1 + 8 * v4))\n ++v3;\n ++v4;\n } while (a2 > (int)v4);\n ++v2;\n } while (v2 != a2);\n }\n }\n v5 = malloc(12uLL);\n __sprintf_chk(v5, 2LL, 12LL, &unk_2004, v3);\n return v5;\n}" + }, + { + "index": 438, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n} pair;\n\n\n\n", + "func": "char* func0(pair test_list[], int len) {\n int res = 0;\n for (int idx = 0; idx < len; idx++) {\n for (int iidx = idx + 1; iidx < len; iidx++) {\n if (test_list[iidx].first == test_list[idx].second &&\n test_list[idx].second == test_list[iidx].first) {\n res += 1;\n }\n }\n }\n char* str = malloc(12);\n sprintf(str, \"%d\", res);\n return str;\n}", + "test": "int main(){\n\n pair test1[] = { {5,6}, {1,2}, {6,5}, {9,1}, {6,5}, {2,1} };\n\n char* res1 = func0(test1, 6);\n\n assert(strcmp(res1, \"3\") == 0);\n\n free(res1);\n\n\n\n pair test2[] = { {5,6}, {1,3}, {6,5}, {9,1}, {6,5}, {2,1} };\n\n char* res2 = func0(test2, 6);\n\n assert(strcmp(res2, \"2\") == 0);\n\n free(res2);\n\n\n\n pair test3[] = { {5,6}, {1,2}, {6,5}, {9,2}, {6,5}, {2,1} };\n\n char* res3 = func0(test3, 6);\n\n assert(strcmp(res3, \"4\") == 0);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\ntest %esi,%esi\njle 14a2 \ncmp $0x1,%esi\nje 14a2 \nlea 0x8(%rdi),%r9\nxor %ebx,%ebx\nlea -0x1(%rsi),%r11d\nmov $0x1,%ecx\nmov $0x1,%r10d\nxchg %ax,%ax\nmov %esi,%eax\nmov %r11d,%edx\nmov -0x4(%r9),%r8d\nsub %ecx,%eax\ncmp %ecx,%esi\ncmovle %r10d,%eax\nsub %ecx,%edx\ncmp $0x3,%edx\njbe 149b \ncmp %ecx,%esi\njle 149b \nlea -0x1(%rax),%edx\nmovd %r8d,%xmm4\npxor %xmm1,%xmm1\nmov %r9,%rax\nmov %edx,%ebp\npshufd $0x0,%xmm4,%xmm2\nshr $0x2,%ebp\nshl $0x5,%rbp\nadd %r9,%rbp\nnopl 0x0(%rax)\nmovdqu (%rax),%xmm0\nmovdqu 0x10(%rax),%xmm3\nadd $0x20,%rax\nshufps $0x88,%xmm3,%xmm0\npcmpeqd %xmm2,%xmm0\npsubd %xmm0,%xmm1\ncmp %rax,%rbp\njne 13c8 \nmovdqa %xmm1,%xmm0\npsrldq $0x8,%xmm0\npaddd %xmm0,%xmm1\nmovdqa %xmm1,%xmm0\npsrldq $0x4,%xmm0\npaddd %xmm0,%xmm1\nmovd %xmm1,%eax\nadd %eax,%ebx\nmov %edx,%eax\nand $0xfffffffc,%eax\nadd %ecx,%eax\nmovslq %eax,%rbp\ncmp (%rdi,%rbp,8),%r8d\nlea 0x0(,%rbp,8),%rdx\nsete %bpl\nmovzbl %bpl,%ebp\nadd %ebp,%ebx\nlea 0x1(%rax),%ebp\ncmp %ebp,%esi\njle 1459 \ncmp 0x8(%rdi,%rdx,1),%r8d\njne 1437 \nadd $0x1,%ebx\nlea 0x2(%rax),%ebp\ncmp %ebp,%esi\njle 1459 \ncmp 0x10(%rdi,%rdx,1),%r8d\njne 1448 \nadd $0x1,%ebx\nadd $0x3,%eax\ncmp %esi,%eax\njge 1459 \ncmp 0x18(%rdi,%rdx,1),%r8d\njne 1459 \nadd $0x1,%ebx\nadd $0x1,%ecx\nadd $0x8,%r9\ncmp %ecx,%esi\njne 1380 \nmov $0xc,%edi\ncallq 10c0 \nmov %ebx,%r8d\nmov $0xc,%edx\nlea 0xb83(%rip),%rcx\nmov %rax,%r12\nmov %rax,%rdi\nmov $0x1,%esi\nxor %eax,%eax\ncallq 10d0 <__sprintf_chk@plt>\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\nretq\nmov %ecx,%eax\njmpq 140d \nxor %ebx,%ebx\njmp 1468 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\ntest esi, esi\njle loc_14A7\ncmp esi, 1\njz loc_14A7\nmov r8, rdi\nlea r9, [rdi+8]\nxor ebx, ebx\nmov ecx, 1\nlea r11d, [rsi-1]\nmov r10d, 1\nnop dword ptr [rax+rax+00h]\nloc_1388:\nmov eax, esi\nmov edx, r11d\nmov edi, [r9-4]\nsub eax, ecx\ncmp esi, ecx\ncmovle eax, r10d\nsub edx, ecx\ncmp edx, 3\njbe loc_14A0\ncmp esi, ecx\njle loc_14A0\nlea edx, [rax-1]\nmovd xmm4, edi\npxor xmm1, xmm1\nmov rax, r9\nmov ebp, edx\npshufd xmm2, xmm4, 0\nshr ebp, 2\nshl rbp, 5\nadd rbp, r9\nnop dword ptr [rax+rax+00h]\nloc_13D0:\nmovdqu xmm0, xmmword ptr [rax]\nmovdqu xmm3, xmmword ptr [rax+10h]\nadd rax, 20h ; ' '\nshufps xmm0, xmm3, 88h\npcmpeqd xmm0, xmm2\npsubd xmm1, xmm0\ncmp rbp, rax\njnz short loc_13D0\nmovdqa xmm0, xmm1\npsrldq xmm0, 8\npaddd xmm1, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm0, 4\npaddd xmm1, xmm0\nmovd eax, xmm1\nadd ebx, eax\nmov eax, edx\nand eax, 0FFFFFFFCh\nadd eax, ecx\nloc_1415:\nmovsxd rbp, eax\nlea rdx, ds:0[rbp*8]\ncmp edi, [r8+rbp*8]\njnz short loc_1429\nadd ebx, 1\nloc_1429:\nlea ebp, [rax+1]\ncmp esi, ebp\njle short loc_145C\ncmp edi, [r8+rdx+8]\njnz short loc_143A\nadd ebx, 1\nloc_143A:\nlea ebp, [rax+2]\ncmp esi, ebp\njle short loc_145C\ncmp edi, [r8+rdx+10h]\njnz short loc_144B\nadd ebx, 1\nloc_144B:\nadd eax, 3\ncmp esi, eax\njle short loc_145C\ncmp edi, [r8+rdx+18h]\njnz short loc_145C\nadd ebx, 1\nloc_145C:\nadd ecx, 1\nadd r9, 8\ncmp esi, ecx\njnz loc_1388\nloc_146B:\nmov edi, 0Ch; size\ncall _malloc\nmov r8d, ebx\nmov edx, 0Ch\nlea rcx, unk_2004\nmov rbp, rax\nmov rdi, rax\nmov esi, 2\nxor eax, eax\ncall ___sprintf_chk\nadd rsp, 8\nmov rax, rbp\npop rbx\npop rbp\nretn\nloc_14A0:\nmov eax, ecx\njmp loc_1415\nloc_14A7:\nxor ebx, ebx\njmp short loc_146B", + "ida_pseudo": "void *__fastcall func0(__int64 a1, int a2)\n{\n const __m128i *v3; // r9\n unsigned int v4; // ebx\n int i; // ecx\n unsigned int v6; // edi\n int v7; // eax\n unsigned int v8; // edx\n __m128i v9; // xmm1\n const __m128i *v10; // rax\n __m128i v11; // xmm2\n __m128 v12; // xmm0\n __m128 v13; // xmm3\n __m128i v14; // xmm1\n int v15; // eax\n __int64 v16; // rdx\n void *v17; // rbp\n\n if ( a2 < 2 )\n {\n v4 = 0;\n }\n else\n {\n v3 = (const __m128i *)(a1 + 8);\n v4 = 0;\n for ( i = 1; i != a2; ++i )\n {\n v6 = v3[-1].m128i_u32[3];\n v7 = a2 - i;\n if ( a2 <= i )\n v7 = 1;\n if ( (unsigned int)(a2 - 1 - i) <= 3 || a2 <= i )\n {\n v15 = i;\n }\n else\n {\n v8 = v7 - 1;\n v9 = 0LL;\n v10 = v3;\n v11 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v6), 0);\n do\n {\n v12 = (__m128)_mm_loadu_si128(v10);\n v13 = (__m128)_mm_loadu_si128(v10 + 1);\n v10 += 2;\n v9 = _mm_sub_epi32(v9, _mm_cmpeq_epi32((__m128i)_mm_shuffle_ps(v12, v13, 136), v11));\n }\n while ( &v3[2 * (v8 >> 2)] != v10 );\n v14 = _mm_add_epi32(v9, _mm_srli_si128(v9, 8));\n v4 += _mm_cvtsi128_si32(_mm_add_epi32(v14, _mm_srli_si128(v14, 4)));\n v15 = i + (v8 & 0xFFFFFFFC);\n }\n v16 = 8LL * v15;\n if ( v6 == *(_DWORD *)(a1 + v16) )\n ++v4;\n if ( a2 > v15 + 1 )\n {\n if ( v6 == *(_DWORD *)(a1 + v16 + 8) )\n ++v4;\n if ( a2 > v15 + 2 )\n {\n if ( v6 == *(_DWORD *)(a1 + v16 + 16) )\n ++v4;\n if ( a2 > v15 + 3 && v6 == *(_DWORD *)(a1 + v16 + 24) )\n ++v4;\n }\n }\n v3 = (const __m128i *)((char *)v3 + 8);\n }\n }\n v17 = malloc(0xCuLL);\n __sprintf_chk(v17, 2LL, 12LL, &unk_2004, v4);\n return v17;\n}", + "ida_strip_asm": "sub_1350:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\ntest esi, esi\njle loc_14A7\ncmp esi, 1\njz loc_14A7\nmov r8, rdi\nlea r9, [rdi+8]\nxor ebx, ebx\nmov ecx, 1\nlea r11d, [rsi-1]\nmov r10d, 1\nnop dword ptr [rax+rax+00h]\nloc_1388:\nmov eax, esi\nmov edx, r11d\nmov edi, [r9-4]\nsub eax, ecx\ncmp esi, ecx\ncmovle eax, r10d\nsub edx, ecx\ncmp edx, 3\njbe loc_14A0\ncmp esi, ecx\njle loc_14A0\nlea edx, [rax-1]\nmovd xmm4, edi\npxor xmm1, xmm1\nmov rax, r9\nmov ebp, edx\npshufd xmm2, xmm4, 0\nshr ebp, 2\nshl rbp, 5\nadd rbp, r9\nnop dword ptr [rax+rax+00h]\nloc_13D0:\nmovdqu xmm0, xmmword ptr [rax]\nmovdqu xmm3, xmmword ptr [rax+10h]\nadd rax, 20h ; ' '\nshufps xmm0, xmm3, 88h\npcmpeqd xmm0, xmm2\npsubd xmm1, xmm0\ncmp rbp, rax\njnz short loc_13D0\nmovdqa xmm0, xmm1\npsrldq xmm0, 8\npaddd xmm1, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm0, 4\npaddd xmm1, xmm0\nmovd eax, xmm1\nadd ebx, eax\nmov eax, edx\nand eax, 0FFFFFFFCh\nadd eax, ecx\nloc_1415:\nmovsxd rbp, eax\nlea rdx, ds:0[rbp*8]\ncmp edi, [r8+rbp*8]\njnz short loc_1429\nadd ebx, 1\nloc_1429:\nlea ebp, [rax+1]\ncmp esi, ebp\njle short loc_145C\ncmp edi, [r8+rdx+8]\njnz short loc_143A\nadd ebx, 1\nloc_143A:\nlea ebp, [rax+2]\ncmp esi, ebp\njle short loc_145C\ncmp edi, [r8+rdx+10h]\njnz short loc_144B\nadd ebx, 1\nloc_144B:\nadd eax, 3\ncmp esi, eax\njle short loc_145C\ncmp edi, [r8+rdx+18h]\njnz short loc_145C\nadd ebx, 1\nloc_145C:\nadd ecx, 1\nadd r9, 8\ncmp esi, ecx\njnz loc_1388\nloc_146B:\nmov edi, 0Ch; size\ncall _malloc\nmov r8d, ebx\nmov edx, 0Ch\nlea rcx, unk_2004\nmov rbp, rax\nmov rdi, rax\nmov esi, 2\nxor eax, eax\ncall ___sprintf_chk\nadd rsp, 8\nmov rax, rbp\npop rbx\npop rbp\nretn\nloc_14A0:\nmov eax, ecx\njmp loc_1415\nloc_14A7:\nxor ebx, ebx\njmp short loc_146B", + "ida_strip_pseudo": "void *__fastcall sub_1350(__int64 a1, int a2)\n{\n const __m128i *v3; // r9\n unsigned int v4; // ebx\n int i; // ecx\n unsigned int v6; // edi\n int v7; // eax\n unsigned int v8; // edx\n __m128i v9; // xmm1\n const __m128i *v10; // rax\n __m128i v11; // xmm2\n __m128 v12; // xmm0\n __m128 v13; // xmm3\n __m128i v14; // xmm1\n int v15; // eax\n __int64 v16; // rdx\n void *v17; // rbp\n\n if ( a2 < 2 )\n {\n v4 = 0;\n }\n else\n {\n v3 = (const __m128i *)(a1 + 8);\n v4 = 0;\n for ( i = 1; i != a2; ++i )\n {\n v6 = v3[-1].m128i_u32[3];\n v7 = a2 - i;\n if ( a2 <= i )\n v7 = 1;\n if ( (unsigned int)(a2 - 1 - i) <= 3 || a2 <= i )\n {\n v15 = i;\n }\n else\n {\n v8 = v7 - 1;\n v9 = 0LL;\n v10 = v3;\n v11 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v6), 0);\n do\n {\n v12 = (__m128)_mm_loadu_si128(v10);\n v13 = (__m128)_mm_loadu_si128(v10 + 1);\n v10 += 2;\n v9 = _mm_sub_epi32(v9, _mm_cmpeq_epi32((__m128i)_mm_shuffle_ps(v12, v13, 136), v11));\n }\n while ( &v3[2 * (v8 >> 2)] != v10 );\n v14 = _mm_add_epi32(v9, _mm_srli_si128(v9, 8));\n v4 += _mm_cvtsi128_si32(_mm_add_epi32(v14, _mm_srli_si128(v14, 4)));\n v15 = i + (v8 & 0xFFFFFFFC);\n }\n v16 = 8LL * v15;\n if ( v6 == *(_DWORD *)(a1 + v16) )\n ++v4;\n if ( a2 > v15 + 1 )\n {\n if ( v6 == *(_DWORD *)(a1 + v16 + 8) )\n ++v4;\n if ( a2 > v15 + 2 )\n {\n if ( v6 == *(_DWORD *)(a1 + v16 + 16) )\n ++v4;\n if ( a2 > v15 + 3 && v6 == *(_DWORD *)(a1 + v16 + 24) )\n ++v4;\n }\n }\n v3 = (const __m128i *)((char *)v3 + 8);\n }\n }\n v17 = malloc(0xCuLL);\n __sprintf_chk(v17, 2LL, 12LL, &unk_2004, v4);\n return v17;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1350(long long a1, int a2) {\n const __m128i *v3;\n unsigned int v4;\n int i;\n unsigned int v6;\n int v7;\n unsigned int v8;\n __m128i v9;\n const __m128i *v10;\n __m128i v11;\n __m128 v12;\n __m128 v13;\n __m128i v14;\n int v15;\n long long v16;\n void *v17;\n if (a2 < 2) {\n v4 = 0;\n } else {\n v3 = (const __m128i *)(a1 + 8);\n v4 = 0;\n for (i = 1; i != a2; ++i) {\n v6 = v3[-1].m128i_u32[3];\n v7 = a2 - i;\n if (a2 <= i) v7 = 1;\n if ((unsigned int)(a2 - 1 - i) <= 3 || a2 <= i) {\n v15 = i;\n } else {\n v8 = v7 - 1;\n v9 = 0LL;\n v10 = v3;\n v11 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v6), 0);\n do {\n v12 = (__m128)_mm_loadu_si128(v10);\n v13 = (__m128)_mm_loadu_si128(v10 + 1);\n v10 += 2;\n v9 = _mm_sub_epi32(\n v9, _mm_cmpeq_epi32((__m128i)_mm_shuffle_ps(v12, v13, 136), v11));\n } while (&v3[2 * (v8 >> 2)] != v10);\n v14 = _mm_add_epi32(v9, _mm_srli_si128(v9, 8));\n v4 += _mm_cvtsi128_si32(_mm_add_epi32(v14, _mm_srli_si128(v14, 4)));\n v15 = i + (v8 & 4294967292);\n }\n v16 = 8LL * v15;\n if (v6 == *(uint32_t *)(a1 + v16)) ++v4;\n if (a2 > v15 + 1) {\n if (v6 == *(uint32_t *)(a1 + v16 + 8)) ++v4;\n if (a2 > v15 + 2) {\n if (v6 == *(uint32_t *)(a1 + v16 + 16)) ++v4;\n if (a2 > v15 + 3 && v6 == *(uint32_t *)(a1 + v16 + 24)) ++v4;\n }\n }\n v3 = (const __m128i *)((char *)v3 + 8);\n }\n }\n v17 = malloc(12uLL);\n __sprintf_chk(v17, 2LL, 12LL, &unk_2004, v4);\n return v17;\n}", + "ida_pseudo_norm": "void *func0(long long a1, int a2) {\n const __m128i *v3;\n unsigned int v4;\n int i;\n unsigned int v6;\n int v7;\n unsigned int v8;\n __m128i v9;\n const __m128i *v10;\n __m128i v11;\n __m128 v12;\n __m128 v13;\n __m128i v14;\n int v15;\n long long v16;\n void *v17;\n if (a2 < 2) {\n v4 = 0;\n } else {\n v3 = (const __m128i *)(a1 + 8);\n v4 = 0;\n for (i = 1; i != a2; ++i) {\n v6 = v3[-1].m128i_u32[3];\n v7 = a2 - i;\n if (a2 <= i) v7 = 1;\n if ((unsigned int)(a2 - 1 - i) <= 3 || a2 <= i) {\n v15 = i;\n } else {\n v8 = v7 - 1;\n v9 = 0LL;\n v10 = v3;\n v11 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v6), 0);\n do {\n v12 = (__m128)_mm_loadu_si128(v10);\n v13 = (__m128)_mm_loadu_si128(v10 + 1);\n v10 += 2;\n v9 = _mm_sub_epi32(\n v9, _mm_cmpeq_epi32((__m128i)_mm_shuffle_ps(v12, v13, 136), v11));\n } while (&v3[2 * (v8 >> 2)] != v10);\n v14 = _mm_add_epi32(v9, _mm_srli_si128(v9, 8));\n v4 += _mm_cvtsi128_si32(_mm_add_epi32(v14, _mm_srli_si128(v14, 4)));\n v15 = i + (v8 & 4294967292);\n }\n v16 = 8LL * v15;\n if (v6 == *(uint32_t *)(a1 + v16)) ++v4;\n if (a2 > v15 + 1) {\n if (v6 == *(uint32_t *)(a1 + v16 + 8)) ++v4;\n if (a2 > v15 + 2) {\n if (v6 == *(uint32_t *)(a1 + v16 + 16)) ++v4;\n if (a2 > v15 + 3 && v6 == *(uint32_t *)(a1 + v16 + 24)) ++v4;\n }\n }\n v3 = (const __m128i *)((char *)v3 + 8);\n }\n }\n v17 = malloc(12uLL);\n __sprintf_chk(v17, 2LL, 12LL, &unk_2004, v4);\n return v17;\n}" + }, + { + "index": 439, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int* L, int size) {\n char temp[256] = {0};\n char numStr[20];\n for (int i = 0; i < size; i++) {\n sprintf(numStr, \"%d\", L[i]);\n strcat(temp, numStr);\n }\n return atoi(temp);\n}", + "test": "int main() {\n\n int arr1[] = {11, 33, 50};\n\n assert(func0(arr1, 3) == 113350);\n\n\n\n int arr2[] = {-1, 2, 3, 4, 5, 6};\n\n assert(func0(arr2, 6) == -123456);\n\n\n\n int arr3[] = {10, 15, 20, 25};\n\n assert(func0(arr3, 4) == 10152025);\n\n\n\n printf(\"All test cases passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x150,%rsp\nmov %rdi,-0x148(%rbp)\nmov %esi,-0x14c(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovq $0x0,-0x110(%rbp)\nmovq $0x0,-0x108(%rbp)\nmovq $0x0,-0x100(%rbp)\nmovq $0x0,-0xf8(%rbp)\nmovq $0x0,-0xf0(%rbp)\nmovq $0x0,-0xe8(%rbp)\nmovq $0x0,-0xe0(%rbp)\nmovq $0x0,-0xd8(%rbp)\nmovq $0x0,-0xd0(%rbp)\nmovq $0x0,-0xc8(%rbp)\nmovq $0x0,-0xc0(%rbp)\nmovq $0x0,-0xb8(%rbp)\nmovq $0x0,-0xb0(%rbp)\nmovq $0x0,-0xa8(%rbp)\nmovq $0x0,-0xa0(%rbp)\nmovq $0x0,-0x98(%rbp)\nmovq $0x0,-0x90(%rbp)\nmovq $0x0,-0x88(%rbp)\nmovq $0x0,-0x80(%rbp)\nmovq $0x0,-0x78(%rbp)\nmovq $0x0,-0x70(%rbp)\nmovq $0x0,-0x68(%rbp)\nmovq $0x0,-0x60(%rbp)\nmovq $0x0,-0x58(%rbp)\nmovq $0x0,-0x50(%rbp)\nmovq $0x0,-0x48(%rbp)\nmovq $0x0,-0x40(%rbp)\nmovq $0x0,-0x38(%rbp)\nmovq $0x0,-0x30(%rbp)\nmovq $0x0,-0x28(%rbp)\nmovq $0x0,-0x20(%rbp)\nmovq $0x0,-0x18(%rbp)\nmovl $0x0,-0x134(%rbp)\njmp 13ad \nmov -0x134(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x148(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nlea -0x130(%rbp),%rax\nlea 0xc88(%rip),%rsi\nmov %rax,%rdi\nmov $0x0,%eax\ncallq 10f0 \nlea -0x130(%rbp),%rdx\nlea -0x110(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10e0 \naddl $0x1,-0x134(%rbp)\nmov -0x134(%rbp),%eax\ncmp -0x14c(%rbp),%eax\njl 1356 \nlea -0x110(%rbp),%rax\nmov %rax,%rdi\ncallq 10d0 \nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 13de \ncallq 10b0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 150h\nmov [rbp+var_148], rdi\nmov [rbp+var_14C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov qword ptr [rbp+dest], 0\nmov [rbp+var_108], 0\nmov [rbp+var_100], 0\nmov [rbp+var_F8], 0\nmov [rbp+var_F0], 0\nmov [rbp+var_E8], 0\nmov [rbp+var_E0], 0\nmov [rbp+var_D8], 0\nmov [rbp+var_D0], 0\nmov [rbp+var_C8], 0\nmov [rbp+var_C0], 0\nmov [rbp+var_B8], 0\nmov [rbp+var_B0], 0\nmov [rbp+var_A8], 0\nmov [rbp+var_A0], 0\nmov [rbp+var_98], 0\nmov [rbp+var_90], 0\nmov [rbp+var_88], 0\nmov [rbp+var_80], 0\nmov [rbp+var_78], 0\nmov [rbp+var_70], 0\nmov [rbp+var_68], 0\nmov [rbp+var_60], 0\nmov [rbp+var_58], 0\nmov [rbp+var_50], 0\nmov [rbp+var_48], 0\nmov [rbp+var_40], 0\nmov [rbp+var_38], 0\nmov [rbp+var_30], 0\nmov [rbp+var_28], 0\nmov [rbp+var_20], 0\nmov [rbp+var_18], 0\nmov [rbp+var_134], 0\njmp short loc_13B0\nloc_1356:\nmov eax, [rbp+var_134]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_148]\nadd rax, rdx\nmov edx, [rax]\nlea rax, [rbp+s]\nlea rcx, format; \"%d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rdx, [rbp+s]\nlea rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\nadd [rbp+var_134], 1\nloc_13B0:\nmov eax, [rbp+var_134]\ncmp eax, [rbp+var_14C]\njl short loc_1356\nlea rax, [rbp+dest]\nmov rdi, rax; nptr\ncall _atoi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_13E1\ncall ___stack_chk_fail\nlocret_13E1:\nleave\nretn", + "ida_pseudo": "int __fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+1Ch] [rbp-134h]\n char s[32]; // [rsp+20h] [rbp-130h] BYREF\n char dest[8]; // [rsp+40h] [rbp-110h] BYREF\n __int64 v6; // [rsp+48h] [rbp-108h]\n __int64 v7; // [rsp+50h] [rbp-100h]\n __int64 v8; // [rsp+58h] [rbp-F8h]\n __int64 v9; // [rsp+60h] [rbp-F0h]\n __int64 v10; // [rsp+68h] [rbp-E8h]\n __int64 v11; // [rsp+70h] [rbp-E0h]\n __int64 v12; // [rsp+78h] [rbp-D8h]\n __int64 v13; // [rsp+80h] [rbp-D0h]\n __int64 v14; // [rsp+88h] [rbp-C8h]\n __int64 v15; // [rsp+90h] [rbp-C0h]\n __int64 v16; // [rsp+98h] [rbp-B8h]\n __int64 v17; // [rsp+A0h] [rbp-B0h]\n __int64 v18; // [rsp+A8h] [rbp-A8h]\n __int64 v19; // [rsp+B0h] [rbp-A0h]\n __int64 v20; // [rsp+B8h] [rbp-98h]\n __int64 v21; // [rsp+C0h] [rbp-90h]\n __int64 v22; // [rsp+C8h] [rbp-88h]\n __int64 v23; // [rsp+D0h] [rbp-80h]\n __int64 v24; // [rsp+D8h] [rbp-78h]\n __int64 v25; // [rsp+E0h] [rbp-70h]\n __int64 v26; // [rsp+E8h] [rbp-68h]\n __int64 v27; // [rsp+F0h] [rbp-60h]\n __int64 v28; // [rsp+F8h] [rbp-58h]\n __int64 v29; // [rsp+100h] [rbp-50h]\n __int64 v30; // [rsp+108h] [rbp-48h]\n __int64 v31; // [rsp+110h] [rbp-40h]\n __int64 v32; // [rsp+118h] [rbp-38h]\n __int64 v33; // [rsp+120h] [rbp-30h]\n __int64 v34; // [rsp+128h] [rbp-28h]\n __int64 v35; // [rsp+130h] [rbp-20h]\n __int64 v36; // [rsp+138h] [rbp-18h]\n unsigned __int64 v37; // [rsp+148h] [rbp-8h]\n\n v37 = __readfsqword(0x28u);\n *(_QWORD *)dest = 0LL;\n v6 = 0LL;\n v7 = 0LL;\n v8 = 0LL;\n v9 = 0LL;\n v10 = 0LL;\n v11 = 0LL;\n v12 = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0LL;\n v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n v22 = 0LL;\n v23 = 0LL;\n v24 = 0LL;\n v25 = 0LL;\n v26 = 0LL;\n v27 = 0LL;\n v28 = 0LL;\n v29 = 0LL;\n v30 = 0LL;\n v31 = 0LL;\n v32 = 0LL;\n v33 = 0LL;\n v34 = 0LL;\n v35 = 0LL;\n v36 = 0LL;\n for ( i = 0; i < a2; ++i )\n {\n sprintf(s, \"%d\", *(_DWORD *)(4LL * i + a1));\n strcat(dest, s);\n }\n return atoi(dest);\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 150h\nmov [rbp+var_148], rdi\nmov [rbp+var_14C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov qword ptr [rbp+dest], 0\nmov [rbp+var_108], 0\nmov [rbp+var_100], 0\nmov [rbp+var_F8], 0\nmov [rbp+var_F0], 0\nmov [rbp+var_E8], 0\nmov [rbp+var_E0], 0\nmov [rbp+var_D8], 0\nmov [rbp+var_D0], 0\nmov [rbp+var_C8], 0\nmov [rbp+var_C0], 0\nmov [rbp+var_B8], 0\nmov [rbp+var_B0], 0\nmov [rbp+var_A8], 0\nmov [rbp+var_A0], 0\nmov [rbp+var_98], 0\nmov [rbp+var_90], 0\nmov [rbp+var_88], 0\nmov [rbp+var_80], 0\nmov [rbp+var_78], 0\nmov [rbp+var_70], 0\nmov [rbp+var_68], 0\nmov [rbp+var_60], 0\nmov [rbp+var_58], 0\nmov [rbp+var_50], 0\nmov [rbp+var_48], 0\nmov [rbp+var_40], 0\nmov [rbp+var_38], 0\nmov [rbp+var_30], 0\nmov [rbp+var_28], 0\nmov [rbp+var_20], 0\nmov [rbp+var_18], 0\nmov [rbp+var_134], 0\njmp short loc_13B0\nloc_1356:\nmov eax, [rbp+var_134]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_148]\nadd rax, rdx\nmov edx, [rax]\nlea rax, [rbp+s]\nlea rcx, format; \"%d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rdx, [rbp+s]\nlea rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\nadd [rbp+var_134], 1\nloc_13B0:\nmov eax, [rbp+var_134]\ncmp eax, [rbp+var_14C]\njl short loc_1356\nlea rax, [rbp+dest]\nmov rdi, rax; nptr\ncall _atoi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_13E1\ncall ___stack_chk_fail\nlocret_13E1:\nleave\nretn", + "ida_strip_pseudo": "int __fastcall sub_11E9(__int64 a1, int a2)\n{\n int i; // [rsp+1Ch] [rbp-134h]\n char s[32]; // [rsp+20h] [rbp-130h] BYREF\n char dest[8]; // [rsp+40h] [rbp-110h] BYREF\n __int64 v6; // [rsp+48h] [rbp-108h]\n __int64 v7; // [rsp+50h] [rbp-100h]\n __int64 v8; // [rsp+58h] [rbp-F8h]\n __int64 v9; // [rsp+60h] [rbp-F0h]\n __int64 v10; // [rsp+68h] [rbp-E8h]\n __int64 v11; // [rsp+70h] [rbp-E0h]\n __int64 v12; // [rsp+78h] [rbp-D8h]\n __int64 v13; // [rsp+80h] [rbp-D0h]\n __int64 v14; // [rsp+88h] [rbp-C8h]\n __int64 v15; // [rsp+90h] [rbp-C0h]\n __int64 v16; // [rsp+98h] [rbp-B8h]\n __int64 v17; // [rsp+A0h] [rbp-B0h]\n __int64 v18; // [rsp+A8h] [rbp-A8h]\n __int64 v19; // [rsp+B0h] [rbp-A0h]\n __int64 v20; // [rsp+B8h] [rbp-98h]\n __int64 v21; // [rsp+C0h] [rbp-90h]\n __int64 v22; // [rsp+C8h] [rbp-88h]\n __int64 v23; // [rsp+D0h] [rbp-80h]\n __int64 v24; // [rsp+D8h] [rbp-78h]\n __int64 v25; // [rsp+E0h] [rbp-70h]\n __int64 v26; // [rsp+E8h] [rbp-68h]\n __int64 v27; // [rsp+F0h] [rbp-60h]\n __int64 v28; // [rsp+F8h] [rbp-58h]\n __int64 v29; // [rsp+100h] [rbp-50h]\n __int64 v30; // [rsp+108h] [rbp-48h]\n __int64 v31; // [rsp+110h] [rbp-40h]\n __int64 v32; // [rsp+118h] [rbp-38h]\n __int64 v33; // [rsp+120h] [rbp-30h]\n __int64 v34; // [rsp+128h] [rbp-28h]\n __int64 v35; // [rsp+130h] [rbp-20h]\n __int64 v36; // [rsp+138h] [rbp-18h]\n unsigned __int64 v37; // [rsp+148h] [rbp-8h]\n\n v37 = __readfsqword(0x28u);\n *(_QWORD *)dest = 0LL;\n v6 = 0LL;\n v7 = 0LL;\n v8 = 0LL;\n v9 = 0LL;\n v10 = 0LL;\n v11 = 0LL;\n v12 = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0LL;\n v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n v22 = 0LL;\n v23 = 0LL;\n v24 = 0LL;\n v25 = 0LL;\n v26 = 0LL;\n v27 = 0LL;\n v28 = 0LL;\n v29 = 0LL;\n v30 = 0LL;\n v31 = 0LL;\n v32 = 0LL;\n v33 = 0LL;\n v34 = 0LL;\n v35 = 0LL;\n v36 = 0LL;\n for ( i = 0; i < a2; ++i )\n {\n sprintf(s, \"%d\", *(_DWORD *)(4LL * i + a1));\n strcat(dest, s);\n }\n return atoi(dest);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "int sub_11E9(long long a1, int a2) {\n int i;\n char s[32];\n char dest[8];\n long long v6;\n long long v7;\n long long v8;\n long long v9;\n long long v10;\n long long v11;\n long long v12;\n long long v13;\n long long v14;\n long long v15;\n long long v16;\n long long v17;\n long long v18;\n long long v19;\n long long v20;\n long long v21;\n long long v22;\n long long v23;\n long long v24;\n long long v25;\n long long v26;\n long long v27;\n long long v28;\n long long v29;\n long long v30;\n long long v31;\n long long v32;\n long long v33;\n long long v34;\n long long v35;\n long long v36;\n unsigned long long v37;\n v37 = __readfsqword(40u);\n *(uint64_t *)dest = 0LL;\n v6 = 0LL;\n v7 = 0LL;\n v8 = 0LL;\n v9 = 0LL;\n v10 = 0LL;\n v11 = 0LL;\n v12 = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0LL;\n v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n v22 = 0LL;\n v23 = 0LL;\n v24 = 0LL;\n v25 = 0LL;\n v26 = 0LL;\n v27 = 0LL;\n v28 = 0LL;\n v29 = 0LL;\n v30 = 0LL;\n v31 = 0LL;\n v32 = 0LL;\n v33 = 0LL;\n v34 = 0LL;\n v35 = 0LL;\n v36 = 0LL;\n for (i = 0; i < a2; ++i) {\n sprintf(s, \"%d\", *(uint32_t *)(4LL * i + a1));\n strcat(dest, s);\n }\n return atoi(dest);\n}", + "ida_pseudo_norm": "int func0(long long a1, int a2) {\n int i;\n char s[32];\n char dest[8];\n long long v6;\n long long v7;\n long long v8;\n long long v9;\n long long v10;\n long long v11;\n long long v12;\n long long v13;\n long long v14;\n long long v15;\n long long v16;\n long long v17;\n long long v18;\n long long v19;\n long long v20;\n long long v21;\n long long v22;\n long long v23;\n long long v24;\n long long v25;\n long long v26;\n long long v27;\n long long v28;\n long long v29;\n long long v30;\n long long v31;\n long long v32;\n long long v33;\n long long v34;\n long long v35;\n long long v36;\n unsigned long long v37;\n v37 = __readfsqword(40u);\n *(uint64_t *)dest = 0LL;\n v6 = 0LL;\n v7 = 0LL;\n v8 = 0LL;\n v9 = 0LL;\n v10 = 0LL;\n v11 = 0LL;\n v12 = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0LL;\n v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n v22 = 0LL;\n v23 = 0LL;\n v24 = 0LL;\n v25 = 0LL;\n v26 = 0LL;\n v27 = 0LL;\n v28 = 0LL;\n v29 = 0LL;\n v30 = 0LL;\n v31 = 0LL;\n v32 = 0LL;\n v33 = 0LL;\n v34 = 0LL;\n v35 = 0LL;\n v36 = 0LL;\n for (i = 0; i < a2; ++i) {\n sprintf(s, \"%d\", *(uint32_t *)(4LL * i + a1));\n strcat(dest, s);\n }\n return atoi(dest);\n}" + }, + { + "index": 439, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int* L, int size) {\n char temp[256] = {0};\n char numStr[20];\n for (int i = 0; i < size; i++) {\n sprintf(numStr, \"%d\", L[i]);\n strcat(temp, numStr);\n }\n return atoi(temp);\n}", + "test": "int main() {\n\n int arr1[] = {11, 33, 50};\n\n assert(func0(arr1, 3) == 113350);\n\n\n\n int arr2[] = {-1, 2, 3, 4, 5, 6};\n\n assert(func0(arr2, 6) == -123456);\n\n\n\n int arr3[] = {10, 15, 20, 25};\n\n assert(func0(arr3, 4) == 10152025);\n\n\n\n printf(\"All test cases passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nsub $0x130,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x128(%rsp)\nxor %eax,%eax\nmovq $0x0,0x20(%rsp)\nmovq $0x0,0x28(%rsp)\nmovq $0x0,0x30(%rsp)\nmovq $0x0,0x38(%rsp)\nmovq $0x0,0x40(%rsp)\nmovq $0x0,0x48(%rsp)\nmovq $0x0,0x50(%rsp)\nmovq $0x0,0x58(%rsp)\nmovq $0x0,0x60(%rsp)\nmovq $0x0,0x68(%rsp)\nmovq $0x0,0x70(%rsp)\nmovq $0x0,0x78(%rsp)\nmovq $0x0,0x80(%rsp)\nmovq $0x0,0x88(%rsp)\nmovq $0x0,0x90(%rsp)\nmovq $0x0,0x98(%rsp)\nmovq $0x0,0xa0(%rsp)\nmovq $0x0,0xa8(%rsp)\nmovq $0x0,0xb0(%rsp)\nmovq $0x0,0xb8(%rsp)\nmovq $0x0,0xc0(%rsp)\nmovq $0x0,0xc8(%rsp)\nmovq $0x0,0xd0(%rsp)\nmovq $0x0,0xd8(%rsp)\nmovq $0x0,0xe0(%rsp)\nmovq $0x0,0xe8(%rsp)\nmovq $0x0,0xf0(%rsp)\nmovq $0x0,0xf8(%rsp)\nmovq $0x0,0x100(%rsp)\nmovq $0x0,0x108(%rsp)\nmovq $0x0,0x110(%rsp)\nmovq $0x0,0x118(%rsp)\ntest %esi,%esi\njle 13b5 \nmov %rdi,%rbx\nlea -0x1(%rsi),%eax\nlea 0x4(%rdi,%rax,4),%r12\nmov %rsp,%rbp\nmov (%rbx),%r8d\nlea 0xc81(%rip),%rcx\nmov $0x14,%edx\nmov $0x1,%esi\nmov %rbp,%rdi\nmov $0x0,%eax\ncallq 10f0 <__sprintf_chk@plt>\nlea 0x20(%rsp),%rdi\nmov $0x100,%edx\nmov %rbp,%rsi\ncallq 10a0 <__strcat_chk@plt>\nadd $0x4,%rbx\ncmp %r12,%rbx\njne 1379 \nlea 0x20(%rsp),%rdi\nmov $0xa,%edx\nmov $0x0,%esi\ncallq 10e0 \nmov 0x128(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 13e8 \nadd $0x130,%rsp\npop %rbx\npop %rbp\npop %r12\nretq\ncallq 10c0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 138h\nmov rax, fs:28h\nmov [rsp+158h+var_30], rax\nxor eax, eax\nmov qword ptr [rsp+158h+nptr], 0\nmov [rsp+158h+var_130], 0\nmov [rsp+158h+var_128], 0\nmov [rsp+158h+var_120], 0\nmov [rsp+158h+var_118], 0\nmov [rsp+158h+var_110], 0\nmov [rsp+158h+var_108], 0\nmov [rsp+158h+var_100], 0\nmov [rsp+158h+var_F8], 0\nmov [rsp+158h+var_F0], 0\nmov [rsp+158h+var_E8], 0\nmov [rsp+158h+var_E0], 0\nmov [rsp+158h+var_D8], 0\nmov [rsp+158h+var_D0], 0\nmov [rsp+158h+var_C8], 0\nmov [rsp+158h+var_C0], 0\nmov [rsp+158h+var_B8], 0\nmov [rsp+158h+var_B0], 0\nmov [rsp+158h+var_A8], 0\nmov [rsp+158h+var_A0], 0\nmov [rsp+158h+var_98], 0\nmov [rsp+158h+var_90], 0\nmov [rsp+158h+var_88], 0\nmov [rsp+158h+var_80], 0\nmov [rsp+158h+var_78], 0\nmov [rsp+158h+var_70], 0\nmov [rsp+158h+var_68], 0\nmov [rsp+158h+var_60], 0\nmov [rsp+158h+var_58], 0\nmov [rsp+158h+var_50], 0\nmov [rsp+158h+var_48], 0\nmov [rsp+158h+var_40], 0\ntest esi, esi\njle short loc_13B9\nmov rbx, rdi\nmovsxd rsi, esi\nlea r13, [rdi+rsi*4]\nlea r12, unk_2004\nloc_137E:\nmov rbp, rsp\nmov r8d, [rbx]\nmov rcx, r12\nmov edx, 14h\nmov esi, 2\nmov rdi, rbp\nmov eax, 0\ncall ___sprintf_chk\nlea rdi, [rsp+158h+nptr]\nmov edx, 100h\nmov rsi, rbp\ncall ___strcat_chk\nadd rbx, 4\ncmp rbx, r13\njnz short loc_137E\nloc_13B9:\nlea rdi, [rsp+158h+nptr]; nptr\nmov edx, 0Ah; base\nmov esi, 0; endptr\ncall _strtol\nmov rdx, [rsp+158h+var_30]\nsub rdx, fs:28h\njnz short loc_13EE\nadd rsp, 138h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_13EE:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n unsigned int *v2; // rbx\n _BYTE v4[32]; // [rsp+0h] [rbp-158h] BYREF\n char nptr[8]; // [rsp+20h] [rbp-138h] BYREF\n __int64 v6; // [rsp+28h] [rbp-130h]\n __int64 v7; // [rsp+30h] [rbp-128h]\n __int64 v8; // [rsp+38h] [rbp-120h]\n __int64 v9; // [rsp+40h] [rbp-118h]\n __int64 v10; // [rsp+48h] [rbp-110h]\n __int64 v11; // [rsp+50h] [rbp-108h]\n __int64 v12; // [rsp+58h] [rbp-100h]\n __int64 v13; // [rsp+60h] [rbp-F8h]\n __int64 v14; // [rsp+68h] [rbp-F0h]\n __int64 v15; // [rsp+70h] [rbp-E8h]\n __int64 v16; // [rsp+78h] [rbp-E0h]\n __int64 v17; // [rsp+80h] [rbp-D8h]\n __int64 v18; // [rsp+88h] [rbp-D0h]\n __int64 v19; // [rsp+90h] [rbp-C8h]\n __int64 v20; // [rsp+98h] [rbp-C0h]\n __int64 v21; // [rsp+A0h] [rbp-B8h]\n __int64 v22; // [rsp+A8h] [rbp-B0h]\n __int64 v23; // [rsp+B0h] [rbp-A8h]\n __int64 v24; // [rsp+B8h] [rbp-A0h]\n __int64 v25; // [rsp+C0h] [rbp-98h]\n __int64 v26; // [rsp+C8h] [rbp-90h]\n __int64 v27; // [rsp+D0h] [rbp-88h]\n __int64 v28; // [rsp+D8h] [rbp-80h]\n __int64 v29; // [rsp+E0h] [rbp-78h]\n __int64 v30; // [rsp+E8h] [rbp-70h]\n __int64 v31; // [rsp+F0h] [rbp-68h]\n __int64 v32; // [rsp+F8h] [rbp-60h]\n __int64 v33; // [rsp+100h] [rbp-58h]\n __int64 v34; // [rsp+108h] [rbp-50h]\n __int64 v35; // [rsp+110h] [rbp-48h]\n __int64 v36; // [rsp+118h] [rbp-40h]\n unsigned __int64 v37; // [rsp+128h] [rbp-30h]\n\n v37 = __readfsqword(0x28u);\n *(_QWORD *)nptr = 0LL;\n v6 = 0LL;\n v7 = 0LL;\n v8 = 0LL;\n v9 = 0LL;\n v10 = 0LL;\n v11 = 0LL;\n v12 = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0LL;\n v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n v22 = 0LL;\n v23 = 0LL;\n v24 = 0LL;\n v25 = 0LL;\n v26 = 0LL;\n v27 = 0LL;\n v28 = 0LL;\n v29 = 0LL;\n v30 = 0LL;\n v31 = 0LL;\n v32 = 0LL;\n v33 = 0LL;\n v34 = 0LL;\n v35 = 0LL;\n v36 = 0LL;\n if ( a2 > 0 )\n {\n v2 = a1;\n do\n {\n __sprintf_chk(v4, 2LL, 20LL, &unk_2004, *v2);\n __strcat_chk(nptr, v4, 256LL);\n ++v2;\n }\n while ( v2 != &a1[a2] );\n }\n return strtol(nptr, 0LL, 10);\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 138h\nmov rax, fs:28h\nmov [rsp+158h+var_30], rax\nxor eax, eax\nmov qword ptr [rsp+158h+nptr], 0\nmov [rsp+158h+var_130], 0\nmov [rsp+158h+var_128], 0\nmov [rsp+158h+var_120], 0\nmov [rsp+158h+var_118], 0\nmov [rsp+158h+var_110], 0\nmov [rsp+158h+var_108], 0\nmov [rsp+158h+var_100], 0\nmov [rsp+158h+var_F8], 0\nmov [rsp+158h+var_F0], 0\nmov [rsp+158h+var_E8], 0\nmov [rsp+158h+var_E0], 0\nmov [rsp+158h+var_D8], 0\nmov [rsp+158h+var_D0], 0\nmov [rsp+158h+var_C8], 0\nmov [rsp+158h+var_C0], 0\nmov [rsp+158h+var_B8], 0\nmov [rsp+158h+var_B0], 0\nmov [rsp+158h+var_A8], 0\nmov [rsp+158h+var_A0], 0\nmov [rsp+158h+var_98], 0\nmov [rsp+158h+var_90], 0\nmov [rsp+158h+var_88], 0\nmov [rsp+158h+var_80], 0\nmov [rsp+158h+var_78], 0\nmov [rsp+158h+var_70], 0\nmov [rsp+158h+var_68], 0\nmov [rsp+158h+var_60], 0\nmov [rsp+158h+var_58], 0\nmov [rsp+158h+var_50], 0\nmov [rsp+158h+var_48], 0\nmov [rsp+158h+var_40], 0\ntest esi, esi\njle short loc_13B9\nmov rbx, rdi\nmovsxd rsi, esi\nlea r13, [rdi+rsi*4]\nlea r12, unk_2004\nloc_137E:\nmov rbp, rsp\nmov r8d, [rbx]\nmov rcx, r12\nmov edx, 14h\nmov esi, 2\nmov rdi, rbp\nmov eax, 0\ncall ___sprintf_chk\nlea rdi, [rsp+158h+nptr]\nmov edx, 100h\nmov rsi, rbp\ncall ___strcat_chk\nadd rbx, 4\ncmp rbx, r13\njnz short loc_137E\nloc_13B9:\nlea rdi, [rsp+158h+nptr]; nptr\nmov edx, 0Ah; base\nmov esi, 0; endptr\ncall _strtol\nmov rdx, [rsp+158h+var_30]\nsub rdx, fs:28h\njnz short loc_13EE\nadd rsp, 138h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_13EE:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_11E9(unsigned int *a1, int a2)\n{\n unsigned int *v2; // rbx\n _BYTE v4[32]; // [rsp+0h] [rbp-158h] BYREF\n char nptr[8]; // [rsp+20h] [rbp-138h] BYREF\n __int64 v6; // [rsp+28h] [rbp-130h]\n __int64 v7; // [rsp+30h] [rbp-128h]\n __int64 v8; // [rsp+38h] [rbp-120h]\n __int64 v9; // [rsp+40h] [rbp-118h]\n __int64 v10; // [rsp+48h] [rbp-110h]\n __int64 v11; // [rsp+50h] [rbp-108h]\n __int64 v12; // [rsp+58h] [rbp-100h]\n __int64 v13; // [rsp+60h] [rbp-F8h]\n __int64 v14; // [rsp+68h] [rbp-F0h]\n __int64 v15; // [rsp+70h] [rbp-E8h]\n __int64 v16; // [rsp+78h] [rbp-E0h]\n __int64 v17; // [rsp+80h] [rbp-D8h]\n __int64 v18; // [rsp+88h] [rbp-D0h]\n __int64 v19; // [rsp+90h] [rbp-C8h]\n __int64 v20; // [rsp+98h] [rbp-C0h]\n __int64 v21; // [rsp+A0h] [rbp-B8h]\n __int64 v22; // [rsp+A8h] [rbp-B0h]\n __int64 v23; // [rsp+B0h] [rbp-A8h]\n __int64 v24; // [rsp+B8h] [rbp-A0h]\n __int64 v25; // [rsp+C0h] [rbp-98h]\n __int64 v26; // [rsp+C8h] [rbp-90h]\n __int64 v27; // [rsp+D0h] [rbp-88h]\n __int64 v28; // [rsp+D8h] [rbp-80h]\n __int64 v29; // [rsp+E0h] [rbp-78h]\n __int64 v30; // [rsp+E8h] [rbp-70h]\n __int64 v31; // [rsp+F0h] [rbp-68h]\n __int64 v32; // [rsp+F8h] [rbp-60h]\n __int64 v33; // [rsp+100h] [rbp-58h]\n __int64 v34; // [rsp+108h] [rbp-50h]\n __int64 v35; // [rsp+110h] [rbp-48h]\n __int64 v36; // [rsp+118h] [rbp-40h]\n unsigned __int64 v37; // [rsp+128h] [rbp-30h]\n\n v37 = __readfsqword(0x28u);\n *(_QWORD *)nptr = 0LL;\n v6 = 0LL;\n v7 = 0LL;\n v8 = 0LL;\n v9 = 0LL;\n v10 = 0LL;\n v11 = 0LL;\n v12 = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0LL;\n v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n v22 = 0LL;\n v23 = 0LL;\n v24 = 0LL;\n v25 = 0LL;\n v26 = 0LL;\n v27 = 0LL;\n v28 = 0LL;\n v29 = 0LL;\n v30 = 0LL;\n v31 = 0LL;\n v32 = 0LL;\n v33 = 0LL;\n v34 = 0LL;\n v35 = 0LL;\n v36 = 0LL;\n if ( a2 > 0 )\n {\n v2 = a1;\n do\n {\n __sprintf_chk(v4, 2LL, 20LL, &unk_2004, *v2);\n __strcat_chk(nptr, v4, 256LL);\n ++v2;\n }\n while ( v2 != &a1[a2] );\n }\n return strtol(nptr, 0LL, 10);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11E9(unsigned int *a1, int a2) {\n unsigned int *v2;\n uint8_t v4[32];\n char nptr[8];\n long long v6;\n long long v7;\n long long v8;\n long long v9;\n long long v10;\n long long v11;\n long long v12;\n long long v13;\n long long v14;\n long long v15;\n long long v16;\n long long v17;\n long long v18;\n long long v19;\n long long v20;\n long long v21;\n long long v22;\n long long v23;\n long long v24;\n long long v25;\n long long v26;\n long long v27;\n long long v28;\n long long v29;\n long long v30;\n long long v31;\n long long v32;\n long long v33;\n long long v34;\n long long v35;\n long long v36;\n unsigned long long v37;\n v37 = __readfsqword(40u);\n *(uint64_t *)nptr = 0LL;\n v6 = 0LL;\n v7 = 0LL;\n v8 = 0LL;\n v9 = 0LL;\n v10 = 0LL;\n v11 = 0LL;\n v12 = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0LL;\n v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n v22 = 0LL;\n v23 = 0LL;\n v24 = 0LL;\n v25 = 0LL;\n v26 = 0LL;\n v27 = 0LL;\n v28 = 0LL;\n v29 = 0LL;\n v30 = 0LL;\n v31 = 0LL;\n v32 = 0LL;\n v33 = 0LL;\n v34 = 0LL;\n v35 = 0LL;\n v36 = 0LL;\n if (a2 > 0) {\n v2 = a1;\n do {\n __sprintf_chk(v4, 2LL, 20LL, &unk_2004, *v2);\n __strcat_chk(nptr, v4, 256LL);\n ++v2;\n } while (v2 != &a1[a2]);\n }\n return strtol(nptr, 0LL, 10);\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n unsigned int *v2;\n uint8_t v4[32];\n char nptr[8];\n long long v6;\n long long v7;\n long long v8;\n long long v9;\n long long v10;\n long long v11;\n long long v12;\n long long v13;\n long long v14;\n long long v15;\n long long v16;\n long long v17;\n long long v18;\n long long v19;\n long long v20;\n long long v21;\n long long v22;\n long long v23;\n long long v24;\n long long v25;\n long long v26;\n long long v27;\n long long v28;\n long long v29;\n long long v30;\n long long v31;\n long long v32;\n long long v33;\n long long v34;\n long long v35;\n long long v36;\n unsigned long long v37;\n v37 = __readfsqword(40u);\n *(uint64_t *)nptr = 0LL;\n v6 = 0LL;\n v7 = 0LL;\n v8 = 0LL;\n v9 = 0LL;\n v10 = 0LL;\n v11 = 0LL;\n v12 = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0LL;\n v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n v22 = 0LL;\n v23 = 0LL;\n v24 = 0LL;\n v25 = 0LL;\n v26 = 0LL;\n v27 = 0LL;\n v28 = 0LL;\n v29 = 0LL;\n v30 = 0LL;\n v31 = 0LL;\n v32 = 0LL;\n v33 = 0LL;\n v34 = 0LL;\n v35 = 0LL;\n v36 = 0LL;\n if (a2 > 0) {\n v2 = a1;\n do {\n __sprintf_chk(v4, 2LL, 20LL, &unk_2004, *v2);\n __strcat_chk(nptr, v4, 256LL);\n ++v2;\n } while (v2 != &a1[a2]);\n }\n return strtol(nptr, 0LL, 10);\n}" + }, + { + "index": 439, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int* L, int size) {\n char temp[256] = {0};\n char numStr[20];\n for (int i = 0; i < size; i++) {\n sprintf(numStr, \"%d\", L[i]);\n strcat(temp, numStr);\n }\n return atoi(temp);\n}", + "test": "int main() {\n\n int arr1[] = {11, 33, 50};\n\n assert(func0(arr1, 3) == 113350);\n\n\n\n int arr2[] = {-1, 2, 3, 4, 5, 6};\n\n assert(func0(arr2, 6) == -123456);\n\n\n\n int arr3[] = {10, 15, 20, 25};\n\n assert(func0(arr3, 4) == 10152025);\n\n\n\n printf(\"All test cases passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npxor %xmm0,%xmm0\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x130,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x128(%rsp)\nxor %eax,%eax\nlea 0x20(%rsp),%r12\nmovaps %xmm0,0x20(%rsp)\nmovaps %xmm0,0x30(%rsp)\nmovaps %xmm0,0x40(%rsp)\nmovaps %xmm0,0x50(%rsp)\nmovaps %xmm0,0x60(%rsp)\nmovaps %xmm0,0x70(%rsp)\nmovaps %xmm0,0x80(%rsp)\nmovaps %xmm0,0x90(%rsp)\nmovaps %xmm0,0xa0(%rsp)\nmovaps %xmm0,0xb0(%rsp)\nmovaps %xmm0,0xc0(%rsp)\nmovaps %xmm0,0xd0(%rsp)\nmovaps %xmm0,0xe0(%rsp)\nmovaps %xmm0,0xf0(%rsp)\nmovaps %xmm0,0x100(%rsp)\nmovaps %xmm0,0x110(%rsp)\ntest %esi,%esi\njle 1433 \nlea -0x1(%rsi),%eax\nmov %rdi,%rbx\nlea 0x20(%rsp),%r12\nmov %rsp,%rbp\nlea 0x4(%rdi,%rax,4),%r14\nlea 0xc09(%rip),%r13\nnopl 0x0(%rax,%rax,1)\nmov (%rbx),%r8d\nmov %r13,%rcx\nmov $0x14,%edx\nmov $0x1,%esi\nmov %rbp,%rdi\nxor %eax,%eax\nadd $0x4,%rbx\ncallq 10f0 <__sprintf_chk@plt>\nmov $0x100,%edx\nmov %rbp,%rsi\nmov %r12,%rdi\ncallq 10a0 <__strcat_chk@plt>\ncmp %r14,%rbx\njne 1400 \nxor %esi,%esi\nmov $0xa,%edx\nmov %r12,%rdi\ncallq 10e0 \nmov 0x128(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 1465 \nadd $0x130,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\ncallq 10c0 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\npxor xmm0, xmm0\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 130h\nmov rax, fs:28h\nmov [rsp+158h+var_30], rax\nxor eax, eax\nlea r12, [rsp+158h+nptr]\nmovaps xmmword ptr [rsp+158h+nptr], xmm0\nmovaps [rsp+158h+var_128], xmm0\nmovaps [rsp+158h+var_118], xmm0\nmovaps [rsp+158h+var_108], xmm0\nmovaps [rsp+158h+var_F8], xmm0\nmovaps [rsp+158h+var_E8], xmm0\nmovaps [rsp+158h+var_D8], xmm0\nmovaps [rsp+158h+var_C8], xmm0\nmovaps [rsp+158h+var_B8], xmm0\nmovaps [rsp+158h+var_A8], xmm0\nmovaps [rsp+158h+var_98], xmm0\nmovaps [rsp+158h+var_88], xmm0\nmovaps [rsp+158h+var_78], xmm0\nmovaps [rsp+158h+var_68], xmm0\nmovaps [rsp+158h+var_58], xmm0\nmovaps [rsp+158h+var_48], xmm0\ntest esi, esi\njle short loc_1403\nmovsxd rsi, esi\nmov rbx, rdi\nlea r13, unk_2004\nmov rbp, rsp\nlea r14, [rdi+rsi*4]\nlea r12, [rsp+158h+nptr]\nnop word ptr [rax+rax+00h]\nloc_13D0:\nmov r8d, [rbx]\nmov rcx, r13\nmov edx, 14h\nmov esi, 2\nmov rdi, rbp\nxor eax, eax\nadd rbx, 4\ncall ___sprintf_chk\nmov edx, 100h\nmov rsi, rbp\nmov rdi, r12\ncall ___strcat_chk\ncmp rbx, r14\njnz short loc_13D0\nloc_1403:\nmov edx, 0Ah; base\nxor esi, esi; endptr\nmov rdi, r12; nptr\ncall _strtol\nmov rdx, [rsp+158h+var_30]\nsub rdx, fs:28h\njnz short loc_1435\nadd rsp, 130h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1435:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n unsigned int *v2; // rbx\n __int64 v3; // r8\n _BYTE v5[32]; // [rsp-8h] [rbp-158h] BYREF\n char nptr[16]; // [rsp+18h] [rbp-138h] BYREF\n __int128 v7; // [rsp+28h] [rbp-128h]\n __int128 v8; // [rsp+38h] [rbp-118h]\n __int128 v9; // [rsp+48h] [rbp-108h]\n __int128 v10; // [rsp+58h] [rbp-F8h]\n __int128 v11; // [rsp+68h] [rbp-E8h]\n __int128 v12; // [rsp+78h] [rbp-D8h]\n __int128 v13; // [rsp+88h] [rbp-C8h]\n __int128 v14; // [rsp+98h] [rbp-B8h]\n __int128 v15; // [rsp+A8h] [rbp-A8h]\n __int128 v16; // [rsp+B8h] [rbp-98h]\n __int128 v17; // [rsp+C8h] [rbp-88h]\n __int128 v18; // [rsp+D8h] [rbp-78h]\n __int128 v19; // [rsp+E8h] [rbp-68h]\n __int128 v20; // [rsp+F8h] [rbp-58h]\n __int128 v21; // [rsp+108h] [rbp-48h]\n unsigned __int64 v22; // [rsp+120h] [rbp-30h]\n\n v22 = __readfsqword(0x28u);\n *(_OWORD *)nptr = 0LL;\n v7 = 0LL;\n v8 = 0LL;\n v9 = 0LL;\n v10 = 0LL;\n v11 = 0LL;\n v12 = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0LL;\n v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n if ( a2 > 0 )\n {\n v2 = a1;\n do\n {\n v3 = *v2++;\n __sprintf_chk(v5, 2LL, 20LL, &unk_2004, v3);\n __strcat_chk(nptr, v5, 256LL);\n }\n while ( v2 != &a1[a2] );\n }\n return strtol(nptr, 0LL, 10);\n}", + "ida_strip_asm": "sub_1310:\nendbr64\npush r14\npxor xmm0, xmm0\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 130h\nmov rax, fs:28h\nmov [rsp+158h+var_30], rax\nxor eax, eax\nlea r12, [rsp+158h+nptr]\nmovaps xmmword ptr [rsp+158h+nptr], xmm0\nmovaps [rsp+158h+var_128], xmm0\nmovaps [rsp+158h+var_118], xmm0\nmovaps [rsp+158h+var_108], xmm0\nmovaps [rsp+158h+var_F8], xmm0\nmovaps [rsp+158h+var_E8], xmm0\nmovaps [rsp+158h+var_D8], xmm0\nmovaps [rsp+158h+var_C8], xmm0\nmovaps [rsp+158h+var_B8], xmm0\nmovaps [rsp+158h+var_A8], xmm0\nmovaps [rsp+158h+var_98], xmm0\nmovaps [rsp+158h+var_88], xmm0\nmovaps [rsp+158h+var_78], xmm0\nmovaps [rsp+158h+var_68], xmm0\nmovaps [rsp+158h+var_58], xmm0\nmovaps [rsp+158h+var_48], xmm0\ntest esi, esi\njle short loc_1403\nmovsxd rsi, esi\nmov rbx, rdi\nlea r13, unk_2004\nmov rbp, rsp\nlea r14, [rdi+rsi*4]\nlea r12, [rsp+158h+nptr]\nnop word ptr [rax+rax+00h]\nloc_13D0:\nmov r8d, [rbx]\nmov rcx, r13\nmov edx, 14h\nmov esi, 2\nmov rdi, rbp\nxor eax, eax\nadd rbx, 4\ncall ___sprintf_chk\nmov edx, 100h\nmov rsi, rbp\nmov rdi, r12\ncall ___strcat_chk\ncmp rbx, r14\njnz short loc_13D0\nloc_1403:\nmov edx, 0Ah; base\nxor esi, esi; endptr\nmov rdi, r12; nptr\ncall _strtol\nmov rdx, [rsp+158h+var_30]\nsub rdx, fs:28h\njnz short loc_1435\nadd rsp, 130h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1435:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1310(unsigned int *a1, int a2)\n{\n unsigned int *v2; // rbx\n __int64 v3; // r8\n _BYTE v5[32]; // [rsp-8h] [rbp-158h] BYREF\n char nptr[16]; // [rsp+18h] [rbp-138h] BYREF\n __int128 v7; // [rsp+28h] [rbp-128h]\n __int128 v8; // [rsp+38h] [rbp-118h]\n __int128 v9; // [rsp+48h] [rbp-108h]\n __int128 v10; // [rsp+58h] [rbp-F8h]\n __int128 v11; // [rsp+68h] [rbp-E8h]\n __int128 v12; // [rsp+78h] [rbp-D8h]\n __int128 v13; // [rsp+88h] [rbp-C8h]\n __int128 v14; // [rsp+98h] [rbp-B8h]\n __int128 v15; // [rsp+A8h] [rbp-A8h]\n __int128 v16; // [rsp+B8h] [rbp-98h]\n __int128 v17; // [rsp+C8h] [rbp-88h]\n __int128 v18; // [rsp+D8h] [rbp-78h]\n __int128 v19; // [rsp+E8h] [rbp-68h]\n __int128 v20; // [rsp+F8h] [rbp-58h]\n __int128 v21; // [rsp+108h] [rbp-48h]\n unsigned __int64 v22; // [rsp+120h] [rbp-30h]\n\n v22 = __readfsqword(0x28u);\n *(_OWORD *)nptr = 0LL;\n v7 = 0LL;\n v8 = 0LL;\n v9 = 0LL;\n v10 = 0LL;\n v11 = 0LL;\n v12 = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0LL;\n v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n if ( a2 > 0 )\n {\n v2 = a1;\n do\n {\n v3 = *v2++;\n __sprintf_chk(v5, 2LL, 20LL, &unk_2004, v3);\n __strcat_chk(nptr, v5, 256LL);\n }\n while ( v2 != &a1[a2] );\n }\n return strtol(nptr, 0LL, 10);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1310(unsigned int *a1, int a2) {\n unsigned int *v2;\n long long v3;\n uint8_t v5[32];\n char nptr[16];\n __int128 v7;\n __int128 v8;\n __int128 v9;\n __int128 v10;\n __int128 v11;\n __int128 v12;\n __int128 v13;\n __int128 v14;\n __int128 v15;\n __int128 v16;\n __int128 v17;\n __int128 v18;\n __int128 v19;\n __int128 v20;\n __int128 v21;\n unsigned long long v22;\n v22 = __readfsqword(40u);\n *(long double *)nptr = 0LL;\n v7 = 0LL;\n v8 = 0LL;\n v9 = 0LL;\n v10 = 0LL;\n v11 = 0LL;\n v12 = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0LL;\n v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n if (a2 > 0) {\n v2 = a1;\n do {\n v3 = *v2++;\n __sprintf_chk(v5, 2LL, 20LL, &unk_2004, v3);\n __strcat_chk(nptr, v5, 256LL);\n } while (v2 != &a1[a2]);\n }\n return strtol(nptr, 0LL, 10);\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n unsigned int *v2;\n long long v3;\n uint8_t v5[32];\n char nptr[16];\n __int128 v7;\n __int128 v8;\n __int128 v9;\n __int128 v10;\n __int128 v11;\n __int128 v12;\n __int128 v13;\n __int128 v14;\n __int128 v15;\n __int128 v16;\n __int128 v17;\n __int128 v18;\n __int128 v19;\n __int128 v20;\n __int128 v21;\n unsigned long long v22;\n v22 = __readfsqword(40u);\n *(long double *)nptr = 0LL;\n v7 = 0LL;\n v8 = 0LL;\n v9 = 0LL;\n v10 = 0LL;\n v11 = 0LL;\n v12 = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0LL;\n v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n if (a2 > 0) {\n v2 = a1;\n do {\n v3 = *v2++;\n __sprintf_chk(v5, 2LL, 20LL, &unk_2004, v3);\n __strcat_chk(nptr, v5, 256LL);\n } while (v2 != &a1[a2]);\n }\n return strtol(nptr, 0LL, 10);\n}" + }, + { + "index": 439, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int* L, int size) {\n char temp[256] = {0};\n char numStr[20];\n for (int i = 0; i < size; i++) {\n sprintf(numStr, \"%d\", L[i]);\n strcat(temp, numStr);\n }\n return atoi(temp);\n}", + "test": "int main() {\n\n int arr1[] = {11, 33, 50};\n\n assert(func0(arr1, 3) == 113350);\n\n\n\n int arr2[] = {-1, 2, 3, 4, 5, 6};\n\n assert(func0(arr2, 6) == -123456);\n\n\n\n int arr3[] = {10, 15, 20, 25};\n\n assert(func0(arr3, 4) == 10152025);\n\n\n\n printf(\"All test cases passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npxor %xmm0,%xmm0\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x130,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x128(%rsp)\nxor %eax,%eax\nlea 0x20(%rsp),%r12\nmovaps %xmm0,0x20(%rsp)\nmovaps %xmm0,0x30(%rsp)\nmovaps %xmm0,0x40(%rsp)\nmovaps %xmm0,0x50(%rsp)\nmovaps %xmm0,0x60(%rsp)\nmovaps %xmm0,0x70(%rsp)\nmovaps %xmm0,0x80(%rsp)\nmovaps %xmm0,0x90(%rsp)\nmovaps %xmm0,0xa0(%rsp)\nmovaps %xmm0,0xb0(%rsp)\nmovaps %xmm0,0xc0(%rsp)\nmovaps %xmm0,0xd0(%rsp)\nmovaps %xmm0,0xe0(%rsp)\nmovaps %xmm0,0xf0(%rsp)\nmovaps %xmm0,0x100(%rsp)\nmovaps %xmm0,0x110(%rsp)\ntest %esi,%esi\njle 1413 \nlea -0x1(%rsi),%eax\nmov %rdi,%rbx\nlea 0x20(%rsp),%r12\nmov %rsp,%rbp\nlea 0x4(%rdi,%rax,4),%r14\nlea 0xc29(%rip),%r13\nnopl 0x0(%rax,%rax,1)\nmov (%rbx),%r8d\nmov %r13,%rcx\nmov $0x14,%edx\nmov $0x1,%esi\nmov %rbp,%rdi\nxor %eax,%eax\nadd $0x4,%rbx\ncallq 10f0 <__sprintf_chk@plt>\nmov $0x100,%edx\nmov %rbp,%rsi\nmov %r12,%rdi\ncallq 10a0 <__strcat_chk@plt>\ncmp %r14,%rbx\njne 13e0 \nxor %esi,%esi\nmov $0xa,%edx\nmov %r12,%rdi\ncallq 10e0 \nmov 0x128(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 1445 \nadd $0x130,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\ncallq 10c0 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\npxor xmm0, xmm0\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 130h\nmov rax, fs:28h\nmov [rsp+158h+var_30], rax\nxor eax, eax\nlea r12, [rsp+158h+nptr]\nmovaps xmmword ptr [rsp+158h+nptr], xmm0\nmovaps [rsp+158h+var_128], xmm0\nmovaps [rsp+158h+var_118], xmm0\nmovaps [rsp+158h+var_108], xmm0\nmovaps [rsp+158h+var_F8], xmm0\nmovaps [rsp+158h+var_E8], xmm0\nmovaps [rsp+158h+var_D8], xmm0\nmovaps [rsp+158h+var_C8], xmm0\nmovaps [rsp+158h+var_B8], xmm0\nmovaps [rsp+158h+var_A8], xmm0\nmovaps [rsp+158h+var_98], xmm0\nmovaps [rsp+158h+var_88], xmm0\nmovaps [rsp+158h+var_78], xmm0\nmovaps [rsp+158h+var_68], xmm0\nmovaps [rsp+158h+var_58], xmm0\nmovaps [rsp+158h+var_48], xmm0\ntest esi, esi\njle short loc_1403\nmovsxd rsi, esi\nmov rbx, rdi\nlea r13, unk_2004\nmov rbp, rsp\nlea r14, [rdi+rsi*4]\nlea r12, [rsp+158h+nptr]\nnop word ptr [rax+rax+00h]\nloc_13D0:\nmov r8d, [rbx]\nmov rcx, r13\nmov edx, 14h\nmov esi, 2\nmov rdi, rbp\nxor eax, eax\nadd rbx, 4\ncall ___sprintf_chk\nmov edx, 100h\nmov rsi, rbp\nmov rdi, r12\ncall ___strcat_chk\ncmp rbx, r14\njnz short loc_13D0\nloc_1403:\nmov edx, 0Ah; base\nxor esi, esi; endptr\nmov rdi, r12; nptr\ncall _strtol\nmov rdx, [rsp+158h+var_30]\nsub rdx, fs:28h\njnz short loc_1435\nadd rsp, 130h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1435:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n unsigned int *v2; // rbx\n __int64 v3; // r8\n _BYTE v5[32]; // [rsp-8h] [rbp-158h] BYREF\n char nptr[16]; // [rsp+18h] [rbp-138h] BYREF\n __int128 v7; // [rsp+28h] [rbp-128h]\n __int128 v8; // [rsp+38h] [rbp-118h]\n __int128 v9; // [rsp+48h] [rbp-108h]\n __int128 v10; // [rsp+58h] [rbp-F8h]\n __int128 v11; // [rsp+68h] [rbp-E8h]\n __int128 v12; // [rsp+78h] [rbp-D8h]\n __int128 v13; // [rsp+88h] [rbp-C8h]\n __int128 v14; // [rsp+98h] [rbp-B8h]\n __int128 v15; // [rsp+A8h] [rbp-A8h]\n __int128 v16; // [rsp+B8h] [rbp-98h]\n __int128 v17; // [rsp+C8h] [rbp-88h]\n __int128 v18; // [rsp+D8h] [rbp-78h]\n __int128 v19; // [rsp+E8h] [rbp-68h]\n __int128 v20; // [rsp+F8h] [rbp-58h]\n __int128 v21; // [rsp+108h] [rbp-48h]\n unsigned __int64 v22; // [rsp+120h] [rbp-30h]\n\n v22 = __readfsqword(0x28u);\n *(_OWORD *)nptr = 0LL;\n v7 = 0LL;\n v8 = 0LL;\n v9 = 0LL;\n v10 = 0LL;\n v11 = 0LL;\n v12 = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0LL;\n v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n if ( a2 > 0 )\n {\n v2 = a1;\n do\n {\n v3 = *v2++;\n __sprintf_chk(v5, 2LL, 20LL, &unk_2004, v3);\n __strcat_chk(nptr, v5, 256LL);\n }\n while ( v2 != &a1[a2] );\n }\n return strtol(nptr, 0LL, 10);\n}", + "ida_strip_asm": "sub_1310:\nendbr64\npush r14\npxor xmm0, xmm0\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 130h\nmov rax, fs:28h\nmov [rsp+158h+var_30], rax\nxor eax, eax\nlea r12, [rsp+158h+nptr]\nmovaps xmmword ptr [rsp+158h+nptr], xmm0\nmovaps [rsp+158h+var_128], xmm0\nmovaps [rsp+158h+var_118], xmm0\nmovaps [rsp+158h+var_108], xmm0\nmovaps [rsp+158h+var_F8], xmm0\nmovaps [rsp+158h+var_E8], xmm0\nmovaps [rsp+158h+var_D8], xmm0\nmovaps [rsp+158h+var_C8], xmm0\nmovaps [rsp+158h+var_B8], xmm0\nmovaps [rsp+158h+var_A8], xmm0\nmovaps [rsp+158h+var_98], xmm0\nmovaps [rsp+158h+var_88], xmm0\nmovaps [rsp+158h+var_78], xmm0\nmovaps [rsp+158h+var_68], xmm0\nmovaps [rsp+158h+var_58], xmm0\nmovaps [rsp+158h+var_48], xmm0\ntest esi, esi\njle short loc_1403\nmovsxd rsi, esi\nmov rbx, rdi\nlea r13, unk_2004\nmov rbp, rsp\nlea r14, [rdi+rsi*4]\nlea r12, [rsp+158h+nptr]\nnop word ptr [rax+rax+00h]\nloc_13D0:\nmov r8d, [rbx]\nmov rcx, r13\nmov edx, 14h\nmov esi, 2\nmov rdi, rbp\nxor eax, eax\nadd rbx, 4\ncall ___sprintf_chk\nmov edx, 100h\nmov rsi, rbp\nmov rdi, r12\ncall ___strcat_chk\ncmp rbx, r14\njnz short loc_13D0\nloc_1403:\nmov edx, 0Ah; base\nxor esi, esi; endptr\nmov rdi, r12; nptr\ncall _strtol\nmov rdx, [rsp+158h+var_30]\nsub rdx, fs:28h\njnz short loc_1435\nadd rsp, 130h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1435:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1310(unsigned int *a1, int a2)\n{\n unsigned int *v2; // rbx\n __int64 v3; // r8\n _BYTE v5[32]; // [rsp-8h] [rbp-158h] BYREF\n char nptr[16]; // [rsp+18h] [rbp-138h] BYREF\n __int128 v7; // [rsp+28h] [rbp-128h]\n __int128 v8; // [rsp+38h] [rbp-118h]\n __int128 v9; // [rsp+48h] [rbp-108h]\n __int128 v10; // [rsp+58h] [rbp-F8h]\n __int128 v11; // [rsp+68h] [rbp-E8h]\n __int128 v12; // [rsp+78h] [rbp-D8h]\n __int128 v13; // [rsp+88h] [rbp-C8h]\n __int128 v14; // [rsp+98h] [rbp-B8h]\n __int128 v15; // [rsp+A8h] [rbp-A8h]\n __int128 v16; // [rsp+B8h] [rbp-98h]\n __int128 v17; // [rsp+C8h] [rbp-88h]\n __int128 v18; // [rsp+D8h] [rbp-78h]\n __int128 v19; // [rsp+E8h] [rbp-68h]\n __int128 v20; // [rsp+F8h] [rbp-58h]\n __int128 v21; // [rsp+108h] [rbp-48h]\n unsigned __int64 v22; // [rsp+120h] [rbp-30h]\n\n v22 = __readfsqword(0x28u);\n *(_OWORD *)nptr = 0LL;\n v7 = 0LL;\n v8 = 0LL;\n v9 = 0LL;\n v10 = 0LL;\n v11 = 0LL;\n v12 = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0LL;\n v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n if ( a2 > 0 )\n {\n v2 = a1;\n do\n {\n v3 = *v2++;\n __sprintf_chk(v5, 2LL, 20LL, &unk_2004, v3);\n __strcat_chk(nptr, v5, 256LL);\n }\n while ( v2 != &a1[a2] );\n }\n return strtol(nptr, 0LL, 10);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1310(unsigned int *a1, int a2) {\n unsigned int *v2;\n long long v3;\n uint8_t v5[32];\n char nptr[16];\n __int128 v7;\n __int128 v8;\n __int128 v9;\n __int128 v10;\n __int128 v11;\n __int128 v12;\n __int128 v13;\n __int128 v14;\n __int128 v15;\n __int128 v16;\n __int128 v17;\n __int128 v18;\n __int128 v19;\n __int128 v20;\n __int128 v21;\n unsigned long long v22;\n v22 = __readfsqword(40u);\n *(long double *)nptr = 0LL;\n v7 = 0LL;\n v8 = 0LL;\n v9 = 0LL;\n v10 = 0LL;\n v11 = 0LL;\n v12 = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0LL;\n v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n if (a2 > 0) {\n v2 = a1;\n do {\n v3 = *v2++;\n __sprintf_chk(v5, 2LL, 20LL, &unk_2004, v3);\n __strcat_chk(nptr, v5, 256LL);\n } while (v2 != &a1[a2]);\n }\n return strtol(nptr, 0LL, 10);\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n unsigned int *v2;\n long long v3;\n uint8_t v5[32];\n char nptr[16];\n __int128 v7;\n __int128 v8;\n __int128 v9;\n __int128 v10;\n __int128 v11;\n __int128 v12;\n __int128 v13;\n __int128 v14;\n __int128 v15;\n __int128 v16;\n __int128 v17;\n __int128 v18;\n __int128 v19;\n __int128 v20;\n __int128 v21;\n unsigned long long v22;\n v22 = __readfsqword(40u);\n *(long double *)nptr = 0LL;\n v7 = 0LL;\n v8 = 0LL;\n v9 = 0LL;\n v10 = 0LL;\n v11 = 0LL;\n v12 = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0LL;\n v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n if (a2 > 0) {\n v2 = a1;\n do {\n v3 = *v2++;\n __sprintf_chk(v5, 2LL, 20LL, &unk_2004, v3);\n __strcat_chk(nptr, v5, 256LL);\n } while (v2 != &a1[a2]);\n }\n return strtol(nptr, 0LL, 10);\n}" + }, + { + "index": 440, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *text, int *start, int *end, char *matched) {\n regex_t regex;\n regmatch_t match;\n if (regcomp(®ex, \"\\\\w+ly\", REG_EXTENDED) != 0) {\n return 0;\n }\n if (regexec(®ex, text, 1, &match, 0) == 0) {\n *start = match.rm_so;\n *end = match.rm_eo;\n strncpy(matched, text + match.rm_so, match.rm_eo - match.rm_so);\n matched[match.rm_eo - match.rm_so] = '\\0';\n regfree(®ex);\n return 1;\n }\n regfree(®ex);\n return 0;\n}", + "test": "int main() {\n\n int start, end;\n\n char matched[100];\n\n \n\n assert(func0(\"clearly!! we can see the sky\", &start, &end, matched) && start == 0 && end == 7 && strcmp(matched, \"clearly\") == 0);\n\n assert(func0(\"seriously!! there are many roses\", &start, &end, matched) && start == 0 && end == 9 && strcmp(matched, \"seriously\") == 0);\n\n assert(func0(\"unfortunately!! sita is going to home\", &start, &end, matched) && start == 0 && end == 13 && strcmp(matched, \"unfortunately\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nadd $0xffffffffffffff80,%rsp\nmov %rdi,-0x68(%rbp)\nmov %rsi,-0x70(%rbp)\nmov %rdx,-0x78(%rbp)\nmov %rcx,-0x80(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea -0x50(%rbp),%rax\nmov $0x1,%edx\nlea 0xdc4(%rip),%rsi\nmov %rax,%rdi\ncallq 10f0 \ntest %eax,%eax\nje 125a \nmov $0x0,%eax\njmpq 12f6 \nlea -0x58(%rbp),%rdx\nmov -0x68(%rbp),%rsi\nlea -0x50(%rbp),%rax\nmov $0x0,%r8d\nmov %rdx,%rcx\nmov $0x1,%edx\nmov %rax,%rdi\ncallq 1110 \ntest %eax,%eax\njne 12e5 \nmov -0x58(%rbp),%edx\nmov -0x70(%rbp),%rax\nmov %edx,(%rax)\nmov -0x54(%rbp),%edx\nmov -0x78(%rbp),%rax\nmov %edx,(%rax)\nmov -0x54(%rbp),%edx\nmov -0x58(%rbp),%eax\nsub %eax,%edx\nmov %edx,%eax\nmovslq %eax,%rdx\nmov -0x58(%rbp),%eax\nmovslq %eax,%rcx\nmov -0x68(%rbp),%rax\nadd %rax,%rcx\nmov -0x80(%rbp),%rax\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 10b0 \nmov -0x54(%rbp),%edx\nmov -0x58(%rbp),%eax\nsub %eax,%edx\nmov %edx,%eax\nmovslq %eax,%rdx\nmov -0x80(%rbp),%rax\nadd %rdx,%rax\nmovb $0x0,(%rax)\nlea -0x50(%rbp),%rax\nmov %rax,%rdi\ncallq 10c0 \nmov $0x1,%eax\njmp 12f6 \nlea -0x50(%rbp),%rax\nmov %rax,%rdi\ncallq 10c0 \nmov $0x0,%eax\nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 130a \ncallq 10d0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nadd rsp, 0FFFFFFFFFFFFFF80h\nmov [rbp+string], rdi\nmov [rbp+var_70], rsi\nmov [rbp+var_78], rdx\nmov [rbp+dest], rcx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nlea rcx, pattern; \"\\\\w+ly\"\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\ntest eax, eax\njz short loc_125D\nmov eax, 0\njmp loc_12F5\nloc_125D:\nlea rdx, [rbp+pmatch]\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov rcx, rdx; pmatch\nmov edx, 1; nmatch\nmov rdi, rax; preg\ncall _regexec\ntest eax, eax\njnz short loc_12E4\nmov edx, [rbp+pmatch.rm_so]\nmov rax, [rbp+var_70]\nmov [rax], edx\nmov edx, [rbp+pmatch.rm_eo]\nmov rax, [rbp+var_78]\nmov [rax], edx\nmov edx, [rbp+pmatch.rm_eo]\nmov eax, [rbp+pmatch.rm_so]\nsub edx, eax\nmovsxd rdx, edx; n\nmov eax, [rbp+pmatch.rm_so]\nmovsxd rcx, eax\nmov rax, [rbp+string]\nadd rcx, rax\nmov rax, [rbp+dest]\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strncpy\nmov edx, [rbp+pmatch.rm_eo]\nmov eax, [rbp+pmatch.rm_so]\nsub edx, eax\nmovsxd rdx, edx\nmov rax, [rbp+dest]\nadd rax, rdx\nmov byte ptr [rax], 0\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nmov eax, 1\njmp short loc_12F5\nloc_12E4:\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nmov eax, 0\nloc_12F5:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1309\ncall ___stack_chk_fail\nlocret_1309:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, regoff_t *a2, regoff_t *a3, char *a4)\n{\n regmatch_t pmatch; // [rsp+28h] [rbp-58h] BYREF\n regex_t preg; // [rsp+30h] [rbp-50h] BYREF\n unsigned __int64 v9; // [rsp+78h] [rbp-8h]\n\n v9 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"\\\\w+ly\", 1) )\n return 0LL;\n if ( regexec(&preg, a1, 1uLL, &pmatch, 0) )\n {\n regfree(&preg);\n return 0LL;\n }\n else\n {\n *a2 = pmatch.rm_so;\n *a3 = pmatch.rm_eo;\n strncpy(a4, &a1[pmatch.rm_so], pmatch.rm_eo - pmatch.rm_so);\n a4[pmatch.rm_eo - pmatch.rm_so] = 0;\n regfree(&preg);\n return 1LL;\n }\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush rbp\nmov rbp, rsp\nadd rsp, 0FFFFFFFFFFFFFF80h\nmov [rbp+string], rdi\nmov [rbp+var_70], rsi\nmov [rbp+var_78], rdx\nmov [rbp+dest], rcx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nlea rcx, pattern; \"\\\\w+ly\"\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\ntest eax, eax\njz short loc_125D\nmov eax, 0\njmp loc_12F5\nloc_125D:\nlea rdx, [rbp+pmatch]\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov rcx, rdx; pmatch\nmov edx, 1; nmatch\nmov rdi, rax; preg\ncall _regexec\ntest eax, eax\njnz short loc_12E4\nmov edx, [rbp+pmatch.rm_so]\nmov rax, [rbp+var_70]\nmov [rax], edx\nmov edx, [rbp+pmatch.rm_eo]\nmov rax, [rbp+var_78]\nmov [rax], edx\nmov edx, [rbp+pmatch.rm_eo]\nmov eax, [rbp+pmatch.rm_so]\nsub edx, eax\nmovsxd rdx, edx; n\nmov eax, [rbp+pmatch.rm_so]\nmovsxd rcx, eax\nmov rax, [rbp+string]\nadd rcx, rax\nmov rax, [rbp+dest]\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strncpy\nmov edx, [rbp+pmatch.rm_eo]\nmov eax, [rbp+pmatch.rm_so]\nsub edx, eax\nmovsxd rdx, edx\nmov rax, [rbp+dest]\nadd rax, rdx\nmov byte ptr [rax], 0\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nmov eax, 1\njmp short loc_12F5\nloc_12E4:\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nmov eax, 0\nloc_12F5:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1309\ncall ___stack_chk_fail\nlocret_1309:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1209(const char *a1, regoff_t *a2, regoff_t *a3, char *a4)\n{\n regmatch_t pmatch; // [rsp+28h] [rbp-58h] BYREF\n regex_t preg; // [rsp+30h] [rbp-50h] BYREF\n unsigned __int64 v9; // [rsp+78h] [rbp-8h]\n\n v9 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"\\\\w+ly\", 1) )\n return 0LL;\n if ( regexec(&preg, a1, 1uLL, &pmatch, 0) )\n {\n regfree(&preg);\n return 0LL;\n }\n else\n {\n *a2 = pmatch.rm_so;\n *a3 = pmatch.rm_eo;\n strncpy(a4, &a1[pmatch.rm_so], pmatch.rm_eo - pmatch.rm_so);\n a4[pmatch.rm_eo - pmatch.rm_so] = 0;\n regfree(&preg);\n return 1LL;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1209(const char *a1, regoff_t *a2, regoff_t *a3, char *a4) {\n regmatch_t pmatch;\n regex_t preg;\n unsigned long long v9;\n v9 = __readfsqword(40u);\n if (regcomp(&preg, \"\\\\w+ly\", 1)) return 0LL;\n if (regexec(&preg, a1, 1uLL, &pmatch, 0)) {\n regfree(&preg);\n return 0LL;\n } else {\n *a2 = pmatch.rm_so;\n *a3 = pmatch.rm_eo;\n strncpy(a4, &a1[pmatch.rm_so], pmatch.rm_eo - pmatch.rm_so);\n a4[pmatch.rm_eo - pmatch.rm_so] = 0;\n regfree(&preg);\n return 1LL;\n }\n}", + "ida_pseudo_norm": "long long func0(const char *a1, regoff_t *a2, regoff_t *a3, char *a4) {\n regmatch_t pmatch;\n regex_t preg;\n unsigned long long v9;\n v9 = __readfsqword(40u);\n if (regcomp(&preg, \"\\\\w+ly\", 1)) return 0LL;\n if (regexec(&preg, a1, 1uLL, &pmatch, 0)) {\n regfree(&preg);\n return 0LL;\n } else {\n *a2 = pmatch.rm_so;\n *a3 = pmatch.rm_eo;\n strncpy(a4, &a1[pmatch.rm_so], pmatch.rm_eo - pmatch.rm_so);\n a4[pmatch.rm_eo - pmatch.rm_so] = 0;\n regfree(&preg);\n return 1LL;\n }\n}" + }, + { + "index": 440, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *text, int *start, int *end, char *matched) {\n regex_t regex;\n regmatch_t match;\n if (regcomp(®ex, \"\\\\w+ly\", REG_EXTENDED) != 0) {\n return 0;\n }\n if (regexec(®ex, text, 1, &match, 0) == 0) {\n *start = match.rm_so;\n *end = match.rm_eo;\n strncpy(matched, text + match.rm_so, match.rm_eo - match.rm_so);\n matched[match.rm_eo - match.rm_so] = '\\0';\n regfree(®ex);\n return 1;\n }\n regfree(®ex);\n return 0;\n}", + "test": "int main() {\n\n int start, end;\n\n char matched[100];\n\n \n\n assert(func0(\"clearly!! we can see the sky\", &start, &end, matched) && start == 0 && end == 7 && strcmp(matched, \"clearly\") == 0);\n\n assert(func0(\"seriously!! there are many roses\", &start, &end, matched) && start == 0 && end == 9 && strcmp(matched, \"seriously\") == 0);\n\n assert(func0(\"unfortunately!! sita is going to home\", &start, &end, matched) && start == 0 && end == 13 && strcmp(matched, \"unfortunately\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x60,%rsp\nmov %rdi,%rbp\nmov %rsi,%r14\nmov %rdx,%r13\nmov %rcx,%r12\nmov %fs:0x28,%rax\nmov %rax,0x58(%rsp)\nxor %eax,%eax\nlea 0x10(%rsp),%rdi\nmov $0x1,%edx\nlea 0xdde(%rip),%rsi\ncallq 10e0 \nmov $0x0,%ebx\ntest %eax,%eax\nje 1253 \nmov 0x58(%rsp),%rax\nxor %fs:0x28,%rax\njne 12c0 \nmov %ebx,%eax\nadd $0x60,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nmov %eax,%ebx\nlea 0x8(%rsp),%rcx\nlea 0x10(%rsp),%rdi\nmov $0x0,%r8d\nmov $0x1,%edx\nmov %rbp,%rsi\ncallq 10f0 \ntest %eax,%eax\nje 1282 \nlea 0x10(%rsp),%rdi\ncallq 10b0 \njmp 1234 \nmov 0x8(%rsp),%esi\nmov %esi,(%r14)\nmov 0xc(%rsp),%ebx\nmov %ebx,0x0(%r13)\nsub %esi,%ebx\nmovslq %ebx,%rbx\nmovslq %esi,%rsi\nadd %rbp,%rsi\nmov %rbx,%rdx\nmov %r12,%rdi\ncallq 10a0 \nmovb $0x0,(%r12,%rbx,1)\nlea 0x10(%rsp),%rdi\ncallq 10b0 \nmov $0x1,%ebx\njmpq 1234 \ncallq 10c0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 60h\nmov rbp, rdi\nmov r14, rsi\nmov r13, rdx\nmov r12, rcx\nmov rax, fs:28h\nmov [rsp+88h+var_30], rax\nxor eax, eax\nlea rdi, [rsp+88h+preg]; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"\\\\w+ly\"\ncall _regcomp\nmov ebx, 0\ntest eax, eax\njz short loc_1273\nloc_1254:\nmov rax, [rsp+88h+var_30]\nsub rax, fs:28h\njnz short loc_12E1\nmov eax, ebx\nadd rsp, 60h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1273:\nmov ebx, eax\nlea rcx, [rsp+88h+pmatch]; pmatch\nlea rdi, [rsp+88h+preg]; preg\nmov r8d, 0; eflags\nmov edx, 1; nmatch\nmov rsi, rbp; string\ncall _regexec\ntest eax, eax\njz short loc_12A2\nlea rdi, [rsp+88h+preg]; preg\ncall _regfree\njmp short loc_1254\nloc_12A2:\nmov eax, [rsp+88h+pmatch.rm_so]\nmov [r14], eax\nmov ebx, [rsp+88h+pmatch.rm_eo]\nmov [r13+0], ebx\nsub ebx, eax\nmovsxd rbx, ebx\ncdqe\nlea rsi, [rbp+rax+0]; src\nmov rdx, rbx; n\nmov rdi, r12; dest\ncall _strncpy\nmov byte ptr [r12+rbx], 0\nlea rdi, [rsp+88h+preg]; preg\ncall _regfree\nmov ebx, 1\njmp loc_1254\nloc_12E1:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(char *string, regoff_t *a2, regoff_t *a3, char *a4)\n{\n unsigned int v6; // ebx\n regoff_t rm_so; // eax\n regoff_t rm_eo; // ebx\n int v10; // ebx\n regmatch_t pmatch; // [rsp+8h] [rbp-80h] BYREF\n regex_t preg; // [rsp+10h] [rbp-78h] BYREF\n unsigned __int64 v13; // [rsp+58h] [rbp-30h]\n\n v13 = __readfsqword(0x28u);\n v6 = 0;\n if ( !regcomp(&preg, \"\\\\w+ly\", 1) )\n {\n v6 = 0;\n if ( regexec(&preg, string, 1uLL, &pmatch, 0) )\n {\n regfree(&preg);\n }\n else\n {\n rm_so = pmatch.rm_so;\n *a2 = pmatch.rm_so;\n rm_eo = pmatch.rm_eo;\n *a3 = pmatch.rm_eo;\n v10 = rm_eo - rm_so;\n strncpy(a4, &string[rm_so], v10);\n a4[v10] = 0;\n regfree(&preg);\n return 1;\n }\n }\n return v6;\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 60h\nmov rbp, rdi\nmov r14, rsi\nmov r13, rdx\nmov r12, rcx\nmov rax, fs:28h\nmov [rsp+88h+var_30], rax\nxor eax, eax\nlea rdi, [rsp+88h+preg]; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"\\\\w+ly\"\ncall _regcomp\nmov ebx, 0\ntest eax, eax\njz short loc_1273\nloc_1254:\nmov rax, [rsp+88h+var_30]\nsub rax, fs:28h\njnz short loc_12E1\nmov eax, ebx\nadd rsp, 60h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1273:\nmov ebx, eax\nlea rcx, [rsp+88h+pmatch]; pmatch\nlea rdi, [rsp+88h+preg]; preg\nmov r8d, 0; eflags\nmov edx, 1; nmatch\nmov rsi, rbp; string\ncall _regexec\ntest eax, eax\njz short loc_12A2\nlea rdi, [rsp+88h+preg]; preg\ncall _regfree\njmp short loc_1254\nloc_12A2:\nmov eax, [rsp+88h+pmatch.rm_so]\nmov [r14], eax\nmov ebx, [rsp+88h+pmatch.rm_eo]\nmov [r13+0], ebx\nsub ebx, eax\nmovsxd rbx, ebx\ncdqe\nlea rsi, [rbp+rax+0]; src\nmov rdx, rbx; n\nmov rdi, r12; dest\ncall _strncpy\nmov byte ptr [r12+rbx], 0\nlea rdi, [rsp+88h+preg]; preg\ncall _regfree\nmov ebx, 1\njmp loc_1254\nloc_12E1:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1209(char *string, regoff_t *a2, regoff_t *a3, char *a4)\n{\n unsigned int v6; // ebx\n regoff_t rm_so; // eax\n regoff_t rm_eo; // ebx\n int v10; // ebx\n regmatch_t pmatch; // [rsp+8h] [rbp-80h] BYREF\n regex_t preg; // [rsp+10h] [rbp-78h] BYREF\n unsigned __int64 v13; // [rsp+58h] [rbp-30h]\n\n v13 = __readfsqword(0x28u);\n v6 = 0;\n if ( !regcomp(&preg, \"\\\\w+ly\", 1) )\n {\n v6 = 0;\n if ( regexec(&preg, string, 1uLL, &pmatch, 0) )\n {\n regfree(&preg);\n }\n else\n {\n rm_so = pmatch.rm_so;\n *a2 = pmatch.rm_so;\n rm_eo = pmatch.rm_eo;\n *a3 = pmatch.rm_eo;\n v10 = rm_eo - rm_so;\n strncpy(a4, &string[rm_so], v10);\n a4[v10] = 0;\n regfree(&preg);\n return 1;\n }\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1209(char *string, regoff_t *a2, regoff_t *a3, char *a4) {\n unsigned int v6;\n regoff_t rm_so;\n regoff_t rm_eo;\n int v10;\n regmatch_t pmatch;\n regex_t preg;\n unsigned long long v13;\n v13 = __readfsqword(40u);\n v6 = 0;\n if (!regcomp(&preg, \"\\\\w+ly\", 1)) {\n v6 = 0;\n if (regexec(&preg, string, 1uLL, &pmatch, 0)) {\n regfree(&preg);\n } else {\n rm_so = pmatch.rm_so;\n *a2 = pmatch.rm_so;\n rm_eo = pmatch.rm_eo;\n *a3 = pmatch.rm_eo;\n v10 = rm_eo - rm_so;\n strncpy(a4, &string[rm_so], v10);\n a4[v10] = 0;\n regfree(&preg);\n return 1;\n }\n }\n return v6;\n}", + "ida_pseudo_norm": "long long func0(char *string, regoff_t *a2, regoff_t *a3, char *a4) {\n unsigned int v6;\n regoff_t rm_so;\n regoff_t rm_eo;\n int v10;\n regmatch_t pmatch;\n regex_t preg;\n unsigned long long v13;\n v13 = __readfsqword(40u);\n v6 = 0;\n if (!regcomp(&preg, \"\\\\w+ly\", 1)) {\n v6 = 0;\n if (regexec(&preg, string, 1uLL, &pmatch, 0)) {\n regfree(&preg);\n } else {\n rm_so = pmatch.rm_so;\n *a2 = pmatch.rm_so;\n rm_eo = pmatch.rm_eo;\n *a3 = pmatch.rm_eo;\n v10 = rm_eo - rm_so;\n strncpy(a4, &string[rm_so], v10);\n a4[v10] = 0;\n regfree(&preg);\n return 1;\n }\n }\n return v6;\n}" + }, + { + "index": 440, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *text, int *start, int *end, char *matched) {\n regex_t regex;\n regmatch_t match;\n if (regcomp(®ex, \"\\\\w+ly\", REG_EXTENDED) != 0) {\n return 0;\n }\n if (regexec(®ex, text, 1, &match, 0) == 0) {\n *start = match.rm_so;\n *end = match.rm_eo;\n strncpy(matched, text + match.rm_so, match.rm_eo - match.rm_so);\n matched[match.rm_eo - match.rm_so] = '\\0';\n regfree(®ex);\n return 1;\n }\n regfree(®ex);\n return 0;\n}", + "test": "int main() {\n\n int start, end;\n\n char matched[100];\n\n \n\n assert(func0(\"clearly!! we can see the sky\", &start, &end, matched) && start == 0 && end == 7 && strcmp(matched, \"clearly\") == 0);\n\n assert(func0(\"seriously!! there are many roses\", &start, &end, matched) && start == 0 && end == 9 && strcmp(matched, \"seriously\") == 0);\n\n assert(func0(\"unfortunately!! sita is going to home\", &start, &end, matched) && start == 0 && end == 13 && strcmp(matched, \"unfortunately\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\nmov %rsi,%r14\nlea 0xc92(%rip),%rsi\npush %r13\nmov %rdx,%r13\nmov $0x1,%edx\npush %r12\nxor %r12d,%r12d\npush %rbp\nmov %rcx,%rbp\npush %rbx\nmov %rdi,%rbx\nsub $0x68,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x58(%rsp)\nxor %eax,%eax\nlea 0x10(%rsp),%r15\nmov %r15,%rdi\ncallq 10e0 \ntest %eax,%eax\nje 13d8 \nmov 0x58(%rsp),%rax\nxor %fs:0x28,%rax\njne 1446 \nadd $0x68,%rsp\nmov %r12d,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\nxor %r8d,%r8d\nlea 0x8(%rsp),%rcx\nmov $0x1,%edx\nmov %rbx,%rsi\nmov %r15,%rdi\nmov %eax,%r12d\ncallq 10f0 \ntest %eax,%eax\nje 1408 \nmov %r15,%rdi\ncallq 10b0 \njmp 13ae \nnopl 0x0(%rax)\nmovslq 0x8(%rsp),%rsi\nmov 0xc(%rsp),%r12d\nmov %rbp,%rdi\nmov %esi,(%r14)\nmov %r12d,0x0(%r13)\nsub %esi,%r12d\nadd %rbx,%rsi\nmovslq %r12d,%r12\nmov %r12,%rdx\ncallq 10a0 \nmovb $0x0,0x0(%rbp,%r12,1)\nmov %r15,%rdi\nmov $0x1,%r12d\ncallq 10b0 \njmpq 13ae \ncallq 10c0 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\nmov r13, rsi\nlea rsi, pattern; \"\\\\w+ly\"\npush r12\nmov r12, rdx\nmov edx, 1; cflags\npush rbp\nmov rbp, rcx\npush rbx\nmov rbx, rdi\nsub rsp, 60h\nmov rax, fs:28h\nmov [rsp+88h+var_30], rax\nxor eax, eax\nlea r14, [rsp+88h+preg]\nmov rdi, r14; preg\ncall _regcomp\ntest eax, eax\njz short loc_13D0\nloc_13A9:\nxor eax, eax\nloc_13AB:\nmov rdx, [rsp+88h+var_30]\nsub rdx, fs:28h\njnz loc_143D\nadd rsp, 60h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_13D0:\nxor r8d, r8d; eflags\nlea rcx, [rsp+88h+pmatch]; pmatch\nmov edx, 1; nmatch\nmov rsi, rbx; string\nmov rdi, r14; preg\ncall _regexec\ntest eax, eax\njz short loc_1400\nmov rdi, r14; preg\ncall _regfree\njmp short loc_13A9\nloc_1400:\nmovsxd rdx, [rsp+88h+pmatch.rm_so]\nmov eax, [rsp+88h+pmatch.rm_eo]\nmov rdi, rbp; dest\nmov [r13+0], edx\nlea rsi, [rbx+rdx]; src\nmov [r12], eax\nsub eax, edx\nmovsxd r12, eax\nmov rdx, r12; n\ncall _strncpy\nmov byte ptr [rbp+r12+0], 0\nmov rdi, r14; preg\ncall _regfree\nmov eax, 1\njmp loc_13AB\nloc_143D:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(char *string, regoff_t *a2, regoff_t *a3, char *a4)\n{\n __int64 rm_so; // rdx\n regoff_t rm_eo; // eax\n size_t v9; // r12\n regmatch_t pmatch; // [rsp+8h] [rbp-80h] BYREF\n regex_t preg; // [rsp+10h] [rbp-78h] BYREF\n unsigned __int64 v12; // [rsp+58h] [rbp-30h]\n\n v12 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"\\\\w+ly\", 1) )\n return 0LL;\n if ( regexec(&preg, string, 1uLL, &pmatch, 0) )\n {\n regfree(&preg);\n return 0LL;\n }\n rm_so = pmatch.rm_so;\n rm_eo = pmatch.rm_eo;\n *a2 = pmatch.rm_so;\n *a3 = rm_eo;\n v9 = rm_eo - (int)rm_so;\n strncpy(a4, &string[rm_so], v9);\n a4[v9] = 0;\n regfree(&preg);\n return 1LL;\n}", + "ida_strip_asm": "sub_1360:\nendbr64\npush r14\npush r13\nmov r13, rsi\nlea rsi, pattern; \"\\\\w+ly\"\npush r12\nmov r12, rdx\nmov edx, 1; cflags\npush rbp\nmov rbp, rcx\npush rbx\nmov rbx, rdi\nsub rsp, 60h\nmov rax, fs:28h\nmov [rsp+88h+var_30], rax\nxor eax, eax\nlea r14, [rsp+88h+preg]\nmov rdi, r14; preg\ncall _regcomp\ntest eax, eax\njz short loc_13D0\nloc_13A9:\nxor eax, eax\nloc_13AB:\nmov rdx, [rsp+88h+var_30]\nsub rdx, fs:28h\njnz loc_143D\nadd rsp, 60h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_13D0:\nxor r8d, r8d; eflags\nlea rcx, [rsp+88h+pmatch]; pmatch\nmov edx, 1; nmatch\nmov rsi, rbx; string\nmov rdi, r14; preg\ncall _regexec\ntest eax, eax\njz short loc_1400\nmov rdi, r14; preg\ncall _regfree\njmp short loc_13A9\nloc_1400:\nmovsxd rdx, [rsp+88h+pmatch.rm_so]\nmov eax, [rsp+88h+pmatch.rm_eo]\nmov rdi, rbp; dest\nmov [r13+0], edx\nlea rsi, [rbx+rdx]; src\nmov [r12], eax\nsub eax, edx\nmovsxd r12, eax\nmov rdx, r12; n\ncall _strncpy\nmov byte ptr [rbp+r12+0], 0\nmov rdi, r14; preg\ncall _regfree\nmov eax, 1\njmp loc_13AB\nloc_143D:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1360(char *string, regoff_t *a2, regoff_t *a3, char *a4)\n{\n __int64 rm_so; // rdx\n regoff_t rm_eo; // eax\n size_t v9; // r12\n regmatch_t pmatch; // [rsp+8h] [rbp-80h] BYREF\n regex_t preg; // [rsp+10h] [rbp-78h] BYREF\n unsigned __int64 v12; // [rsp+58h] [rbp-30h]\n\n v12 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"\\\\w+ly\", 1) )\n return 0LL;\n if ( regexec(&preg, string, 1uLL, &pmatch, 0) )\n {\n regfree(&preg);\n return 0LL;\n }\n rm_so = pmatch.rm_so;\n rm_eo = pmatch.rm_eo;\n *a2 = pmatch.rm_so;\n *a3 = rm_eo;\n v9 = rm_eo - (int)rm_so;\n strncpy(a4, &string[rm_so], v9);\n a4[v9] = 0;\n regfree(&preg);\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1360(char *string, regoff_t *a2, regoff_t *a3, char *a4) {\n long long rm_so;\n regoff_t rm_eo;\n unsigned int v9;\n regmatch_t pmatch;\n regex_t preg;\n unsigned long long v12;\n v12 = __readfsqword(40u);\n if (regcomp(&preg, \"\\\\w+ly\", 1)) return 0LL;\n if (regexec(&preg, string, 1uLL, &pmatch, 0)) {\n regfree(&preg);\n return 0LL;\n }\n rm_so = pmatch.rm_so;\n rm_eo = pmatch.rm_eo;\n *a2 = pmatch.rm_so;\n *a3 = rm_eo;\n v9 = rm_eo - (int)rm_so;\n strncpy(a4, &string[rm_so], v9);\n a4[v9] = 0;\n regfree(&preg);\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(char *string, regoff_t *a2, regoff_t *a3, char *a4) {\n long long rm_so;\n regoff_t rm_eo;\n unsigned int v9;\n regmatch_t pmatch;\n regex_t preg;\n unsigned long long v12;\n v12 = __readfsqword(40u);\n if (regcomp(&preg, \"\\\\w+ly\", 1)) return 0LL;\n if (regexec(&preg, string, 1uLL, &pmatch, 0)) {\n regfree(&preg);\n return 0LL;\n }\n rm_so = pmatch.rm_so;\n rm_eo = pmatch.rm_eo;\n *a2 = pmatch.rm_so;\n *a3 = rm_eo;\n v9 = rm_eo - (int)rm_so;\n strncpy(a4, &string[rm_so], v9);\n a4[v9] = 0;\n regfree(&preg);\n return 1LL;\n}" + }, + { + "index": 440, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *text, int *start, int *end, char *matched) {\n regex_t regex;\n regmatch_t match;\n if (regcomp(®ex, \"\\\\w+ly\", REG_EXTENDED) != 0) {\n return 0;\n }\n if (regexec(®ex, text, 1, &match, 0) == 0) {\n *start = match.rm_so;\n *end = match.rm_eo;\n strncpy(matched, text + match.rm_so, match.rm_eo - match.rm_so);\n matched[match.rm_eo - match.rm_so] = '\\0';\n regfree(®ex);\n return 1;\n }\n regfree(®ex);\n return 0;\n}", + "test": "int main() {\n\n int start, end;\n\n char matched[100];\n\n \n\n assert(func0(\"clearly!! we can see the sky\", &start, &end, matched) && start == 0 && end == 7 && strcmp(matched, \"clearly\") == 0);\n\n assert(func0(\"seriously!! there are many roses\", &start, &end, matched) && start == 0 && end == 9 && strcmp(matched, \"seriously\") == 0);\n\n assert(func0(\"unfortunately!! sita is going to home\", &start, &end, matched) && start == 0 && end == 13 && strcmp(matched, \"unfortunately\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\nmov %rsi,%r14\nlea 0xc92(%rip),%rsi\npush %r13\nmov %rdx,%r13\nmov $0x1,%edx\npush %r12\nxor %r12d,%r12d\npush %rbp\nmov %rcx,%rbp\npush %rbx\nmov %rdi,%rbx\nsub $0x68,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x58(%rsp)\nxor %eax,%eax\nlea 0x10(%rsp),%r15\nmov %r15,%rdi\ncallq 10e0 \ntest %eax,%eax\nje 13d8 \nmov 0x58(%rsp),%rax\nxor %fs:0x28,%rax\njne 1446 \nadd $0x68,%rsp\nmov %r12d,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\nxor %r8d,%r8d\nlea 0x8(%rsp),%rcx\nmov $0x1,%edx\nmov %rbx,%rsi\nmov %r15,%rdi\nmov %eax,%r12d\ncallq 10f0 \ntest %eax,%eax\nje 1408 \nmov %r15,%rdi\ncallq 10b0 \njmp 13ae \nnopl 0x0(%rax)\nmovslq 0x8(%rsp),%rsi\nmov 0xc(%rsp),%r12d\nmov %rbp,%rdi\nmov %esi,(%r14)\nmov %r12d,0x0(%r13)\nsub %esi,%r12d\nadd %rbx,%rsi\nmovslq %r12d,%r12\nmov %r12,%rdx\ncallq 10a0 \nmovb $0x0,0x0(%rbp,%r12,1)\nmov %r15,%rdi\nmov $0x1,%r12d\ncallq 10b0 \njmpq 13ae \ncallq 10c0 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\nmov r13, rsi\nlea rsi, pattern; \"\\\\w+ly\"\npush r12\nmov r12, rdx\nmov edx, 1; cflags\npush rbp\nmov rbp, rcx\npush rbx\nmov rbx, rdi\nsub rsp, 60h\nmov rax, fs:28h\nmov [rsp+88h+var_30], rax\nxor eax, eax\nlea r14, [rsp+88h+preg]\nmov rdi, r14; preg\ncall _regcomp\ntest eax, eax\njz short loc_13D0\nloc_13A9:\nxor eax, eax\nloc_13AB:\nmov rdx, [rsp+88h+var_30]\nsub rdx, fs:28h\njnz loc_143D\nadd rsp, 60h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_13D0:\nxor r8d, r8d; eflags\nlea rcx, [rsp+88h+pmatch]; pmatch\nmov edx, 1; nmatch\nmov rsi, rbx; string\nmov rdi, r14; preg\ncall _regexec\ntest eax, eax\njz short loc_1400\nmov rdi, r14; preg\ncall _regfree\njmp short loc_13A9\nloc_1400:\nmovsxd rdx, [rsp+88h+pmatch.rm_so]\nmov eax, [rsp+88h+pmatch.rm_eo]\nmov rdi, rbp; dest\nmov [r13+0], edx\nlea rsi, [rbx+rdx]; src\nmov [r12], eax\nsub eax, edx\nmovsxd r12, eax\nmov rdx, r12; n\ncall _strncpy\nmov byte ptr [rbp+r12+0], 0\nmov rdi, r14; preg\ncall _regfree\nmov eax, 1\njmp loc_13AB\nloc_143D:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(char *string, regoff_t *a2, regoff_t *a3, char *a4)\n{\n __int64 rm_so; // rdx\n regoff_t rm_eo; // eax\n size_t v9; // r12\n regmatch_t pmatch; // [rsp+8h] [rbp-80h] BYREF\n regex_t preg; // [rsp+10h] [rbp-78h] BYREF\n unsigned __int64 v12; // [rsp+58h] [rbp-30h]\n\n v12 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"\\\\w+ly\", 1) )\n return 0LL;\n if ( regexec(&preg, string, 1uLL, &pmatch, 0) )\n {\n regfree(&preg);\n return 0LL;\n }\n rm_so = pmatch.rm_so;\n rm_eo = pmatch.rm_eo;\n *a2 = pmatch.rm_so;\n *a3 = rm_eo;\n v9 = rm_eo - (int)rm_so;\n strncpy(a4, &string[rm_so], v9);\n a4[v9] = 0;\n regfree(&preg);\n return 1LL;\n}", + "ida_strip_asm": "sub_1360:\nendbr64\npush r14\npush r13\nmov r13, rsi\nlea rsi, pattern; \"\\\\w+ly\"\npush r12\nmov r12, rdx\nmov edx, 1; cflags\npush rbp\nmov rbp, rcx\npush rbx\nmov rbx, rdi\nsub rsp, 60h\nmov rax, fs:28h\nmov [rsp+88h+var_30], rax\nxor eax, eax\nlea r14, [rsp+88h+preg]\nmov rdi, r14; preg\ncall _regcomp\ntest eax, eax\njz short loc_13D0\nloc_13A9:\nxor eax, eax\nloc_13AB:\nmov rdx, [rsp+88h+var_30]\nsub rdx, fs:28h\njnz loc_143D\nadd rsp, 60h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_13D0:\nxor r8d, r8d; eflags\nlea rcx, [rsp+88h+pmatch]; pmatch\nmov edx, 1; nmatch\nmov rsi, rbx; string\nmov rdi, r14; preg\ncall _regexec\ntest eax, eax\njz short loc_1400\nmov rdi, r14; preg\ncall _regfree\njmp short loc_13A9\nloc_1400:\nmovsxd rdx, [rsp+88h+pmatch.rm_so]\nmov eax, [rsp+88h+pmatch.rm_eo]\nmov rdi, rbp; dest\nmov [r13+0], edx\nlea rsi, [rbx+rdx]; src\nmov [r12], eax\nsub eax, edx\nmovsxd r12, eax\nmov rdx, r12; n\ncall _strncpy\nmov byte ptr [rbp+r12+0], 0\nmov rdi, r14; preg\ncall _regfree\nmov eax, 1\njmp loc_13AB\nloc_143D:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1360(char *string, regoff_t *a2, regoff_t *a3, char *a4)\n{\n __int64 rm_so; // rdx\n regoff_t rm_eo; // eax\n size_t v9; // r12\n regmatch_t pmatch; // [rsp+8h] [rbp-80h] BYREF\n regex_t preg; // [rsp+10h] [rbp-78h] BYREF\n unsigned __int64 v12; // [rsp+58h] [rbp-30h]\n\n v12 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"\\\\w+ly\", 1) )\n return 0LL;\n if ( regexec(&preg, string, 1uLL, &pmatch, 0) )\n {\n regfree(&preg);\n return 0LL;\n }\n rm_so = pmatch.rm_so;\n rm_eo = pmatch.rm_eo;\n *a2 = pmatch.rm_so;\n *a3 = rm_eo;\n v9 = rm_eo - (int)rm_so;\n strncpy(a4, &string[rm_so], v9);\n a4[v9] = 0;\n regfree(&preg);\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1360(char *string, regoff_t *a2, regoff_t *a3, char *a4) {\n long long rm_so;\n regoff_t rm_eo;\n unsigned int v9;\n regmatch_t pmatch;\n regex_t preg;\n unsigned long long v12;\n v12 = __readfsqword(40u);\n if (regcomp(&preg, \"\\\\w+ly\", 1)) return 0LL;\n if (regexec(&preg, string, 1uLL, &pmatch, 0)) {\n regfree(&preg);\n return 0LL;\n }\n rm_so = pmatch.rm_so;\n rm_eo = pmatch.rm_eo;\n *a2 = pmatch.rm_so;\n *a3 = rm_eo;\n v9 = rm_eo - (int)rm_so;\n strncpy(a4, &string[rm_so], v9);\n a4[v9] = 0;\n regfree(&preg);\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(char *string, regoff_t *a2, regoff_t *a3, char *a4) {\n long long rm_so;\n regoff_t rm_eo;\n unsigned int v9;\n regmatch_t pmatch;\n regex_t preg;\n unsigned long long v12;\n v12 = __readfsqword(40u);\n if (regcomp(&preg, \"\\\\w+ly\", 1)) return 0LL;\n if (regexec(&preg, string, 1uLL, &pmatch, 0)) {\n regfree(&preg);\n return 0LL;\n }\n rm_so = pmatch.rm_so;\n rm_eo = pmatch.rm_eo;\n *a2 = pmatch.rm_so;\n *a3 = rm_eo;\n v9 = rm_eo - (int)rm_so;\n strncpy(a4, &string[rm_so], v9);\n a4[v9] = 0;\n regfree(&preg);\n return 1LL;\n}" + }, + { + "index": 441, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int l) {\n int surfacearea = 6 * l * l;\n return surfacearea;\n}", + "test": "int main() {\n\n assert(func0(5) == 150);\n\n assert(func0(3) == 54);\n\n assert(func0(10) == 600);\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov -0x14(%rbp),%eax\nimul %eax,%eax\nmov %eax,%edx\nmov %edx,%eax\nadd %eax,%eax\nadd %edx,%eax\nadd %eax,%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov eax, [rbp+var_14]\nimul eax, eax\nmov edx, eax\nmov eax, edx\nadd eax, eax\nadd eax, edx\nadd eax, eax\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n return (unsigned int)(6 * a1 * a1);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov eax, [rbp+var_14]\nimul eax, eax\nmov edx, eax\nmov eax, edx\nadd eax, eax\nadd eax, edx\nadd eax, eax\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n return (unsigned int)(6 * a1 * a1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) { return (unsigned int)(6 * a1 * a1); }", + "ida_pseudo_norm": "long long func0(int a1) { return (unsigned int)(6 * a1 * a1); }" + }, + { + "index": 442, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int nums[], int n) {\n int n1 = 0;\n for (int i = 0; i < n; i++) {\n if (nums[i] > 0) {\n n1 += 1;\n }\n }\n double result = ((double)n1 / n);\n result = round(result * 100) / 100;\n return result;\n}", + "test": "int main() {\n\n int arr1[] = {0, 1, 2, -1, -5, 6, 0, -3, -2, 3, 4, 6, 8};\n\n assert(func0(arr1, 13) == 0.54);\n\n \n\n int arr2[] = {2, 1, 2, -1, -5, 6, 4, -3, -2, 3, 4, 6, 8};\n\n assert(func0(arr2, 13) == 0.69);\n\n \n\n int arr3[] = {2, 4, -6, -9, 11, -12, 14, -5, 17};\n\n assert(func0(arr3, 9) == 0.56);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 11ce \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ntest %eax,%eax\njle 11ca \naddl $0x1,-0x10(%rbp)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11ac \ncvtsi2sdl -0x10(%rbp),%xmm0\ncvtsi2sdl -0x1c(%rbp),%xmm1\ndivsd %xmm1,%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmovsd -0x8(%rbp),%xmm1\nmovsd 0xe9a(%rip),%xmm0\nmulsd %xmm1,%xmm0\ncallq 1070 \nmovsd 0xe89(%rip),%xmm1\ndivsd %xmm1,%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmovsd -0x8(%rbp),%xmm0\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp short loc_11CE\nloc_11AC:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njle short loc_11CA\nadd [rbp+var_10], 1\nloc_11CA:\nadd [rbp+var_C], 1\nloc_11CE:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_11AC\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_10]\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_1C]\ndivsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm1, [rbp+var_8]\nmovsd xmm0, cs:qword_2078\nmulsd xmm1, xmm0\nmovq rax, xmm1\nmovq xmm0, rax; x\ncall _round\nmovq rax, xmm0\nmovsd xmm1, cs:qword_2078\nmovq xmm0, rax\ndivsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "double __fastcall func0(__int64 a1, int a2)\n{\n int v3; // [rsp+10h] [rbp-10h]\n int i; // [rsp+14h] [rbp-Ch]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(int *)(4LL * i + a1) > 0 )\n ++v3;\n }\n return round((double)v3 / (double)a2 * 100.0) / 100.0;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp short loc_11CE\nloc_11AC:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njle short loc_11CA\nadd [rbp+var_10], 1\nloc_11CA:\nadd [rbp+var_C], 1\nloc_11CE:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_11AC\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_10]\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_1C]\ndivsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm1, [rbp+var_8]\nmovsd xmm0, cs:qword_2078\nmulsd xmm1, xmm0\nmovq rax, xmm1\nmovq xmm0, rax; x\ncall _round\nmovq rax, xmm0\nmovsd xmm1, cs:qword_2078\nmovq xmm0, rax\ndivsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "double __fastcall sub_1189(__int64 a1, int a2)\n{\n int v3; // [rsp+10h] [rbp-10h]\n int i; // [rsp+14h] [rbp-Ch]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(int *)(4LL * i + a1) > 0 )\n ++v3;\n }\n return round((double)v3 / (double)a2 * 100.0) / 100.0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1189(long long a1, int a2) {\n int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(int *)(4LL * i + a1) > 0) ++v3;\n }\n return round((double)v3 / (double)a2 * 100.0) / 100.0;\n}", + "ida_pseudo_norm": "double func0(long long a1, int a2) {\n int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(int *)(4LL * i + a1) > 0) ++v3;\n }\n return round((double)v3 / (double)a2 * 100.0) / 100.0;\n}" + }, + { + "index": 442, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int nums[], int n) {\n int n1 = 0;\n for (int i = 0; i < n; i++) {\n if (nums[i] > 0) {\n n1 += 1;\n }\n }\n double result = ((double)n1 / n);\n result = round(result * 100) / 100;\n return result;\n}", + "test": "int main() {\n\n int arr1[] = {0, 1, 2, -1, -5, 6, 0, -3, -2, 3, 4, 6, 8};\n\n assert(func0(arr1, 13) == 0.54);\n\n \n\n int arr2[] = {2, 1, 2, -1, -5, 6, 4, -3, -2, 3, 4, 6, 8};\n\n assert(func0(arr2, 13) == 0.69);\n\n \n\n int arr3[] = {2, 4, -6, -9, 11, -12, 14, -5, 17};\n\n assert(func0(arr3, 9) == 0.56);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x8,%rsp\ntest %esi,%esi\njle 11e7 \nmov %rdi,%rax\nlea -0x1(%rsi),%edx\nlea 0x4(%rdi,%rdx,4),%rdi\nmov $0x0,%edx\ncmpl $0x0,(%rax)\nsetg %cl\nmovzbl %cl,%ecx\nadd %ecx,%edx\nadd $0x4,%rax\ncmp %rdi,%rax\njne 11a5 \npxor %xmm0,%xmm0\ncvtsi2sd %edx,%xmm0\npxor %xmm1,%xmm1\ncvtsi2sd %esi,%xmm1\ndivsd %xmm1,%xmm0\nmulsd 0xebb(%rip),%xmm0\ncallq 1070 \ndivsd 0xeae(%rip),%xmm0\nadd $0x8,%rsp\nretq\nmov $0x0,%edx\njmp 11b9 \n", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\ntest esi, esi\njle short loc_11E6\nmov rax, rdi\nmovsxd rdx, esi\nlea rdi, [rdi+rdx*4]\nmov edx, 0\nloc_11A4:\ncmp dword ptr [rax], 0\nsetnle cl\nmovzx ecx, cl\nadd edx, ecx\nadd rax, 4\ncmp rax, rdi\njnz short loc_11A4\nloc_11B8:\npxor xmm0, xmm0\ncvtsi2sd xmm0, edx\npxor xmm1, xmm1\ncvtsi2sd xmm1, esi\ndivsd xmm0, xmm1\nmulsd xmm0, cs:qword_2078; x\ncall _round\ndivsd xmm0, cs:qword_2078\nadd rsp, 8\nretn\nloc_11E6:\nmov edx, 0\njmp short loc_11B8", + "ida_pseudo": "double __fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n _DWORD *v3; // rdi\n int v4; // edx\n\n if ( a2 <= 0 )\n {\n v4 = 0;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n v4 += *v2++ > 0;\n while ( v2 != v3 );\n }\n return round((double)v4 / (double)a2 * 100.0) / 100.0;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\nsub rsp, 8\ntest esi, esi\njle short loc_11E6\nmov rax, rdi\nmovsxd rdx, esi\nlea rdi, [rdi+rdx*4]\nmov edx, 0\nloc_11A4:\ncmp dword ptr [rax], 0\nsetnle cl\nmovzx ecx, cl\nadd edx, ecx\nadd rax, 4\ncmp rax, rdi\njnz short loc_11A4\nloc_11B8:\npxor xmm0, xmm0\ncvtsi2sd xmm0, edx\npxor xmm1, xmm1\ncvtsi2sd xmm1, esi\ndivsd xmm0, xmm1\nmulsd xmm0, cs:qword_2078; x\ncall _round\ndivsd xmm0, cs:qword_2078\nadd rsp, 8\nretn\nloc_11E6:\nmov edx, 0\njmp short loc_11B8", + "ida_strip_pseudo": "double __fastcall sub_1189(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n _DWORD *v3; // rdi\n int v4; // edx\n\n if ( a2 <= 0 )\n {\n v4 = 0;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n v4 += *v2++ > 0;\n while ( v2 != v3 );\n }\n return round((double)v4 / (double)a2 * 100.0) / 100.0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1189(uint32_t *a1, int a2) {\n uint32_t *v2;\n uint32_t *v3;\n int v4;\n if (a2 <= 0) {\n v4 = 0;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n v4 += *v2++ > 0;\n while (v2 != v3);\n }\n return round((double)v4 / (double)a2 * 100.0) / 100.0;\n}", + "ida_pseudo_norm": "double func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n uint32_t *v3;\n int v4;\n if (a2 <= 0) {\n v4 = 0;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n v4 += *v2++ > 0;\n while (v2 != v3);\n }\n return round((double)v4 / (double)a2 * 100.0) / 100.0;\n}" + }, + { + "index": 442, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int nums[], int n) {\n int n1 = 0;\n for (int i = 0; i < n; i++) {\n if (nums[i] > 0) {\n n1 += 1;\n }\n }\n double result = ((double)n1 / n);\n result = round(result * 100) / 100;\n return result;\n}", + "test": "int main() {\n\n int arr1[] = {0, 1, 2, -1, -5, 6, 0, -3, -2, 3, 4, 6, 8};\n\n assert(func0(arr1, 13) == 0.54);\n\n \n\n int arr2[] = {2, 1, 2, -1, -5, 6, 4, -3, -2, 3, 4, 6, 8};\n\n assert(func0(arr2, 13) == 0.69);\n\n \n\n int arr3[] = {2, 4, -6, -9, 11, -12, 14, -5, 17};\n\n assert(func0(arr3, 9) == 0.56);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x8,%rsp\ntest %esi,%esi\njle 13f8 \nlea -0x1(%rsi),%eax\nlea 0x4(%rdi,%rax,4),%rcx\nxor %eax,%eax\nnopw %cs:0x0(%rax,%rax,1)\nmov (%rdi),%r8d\nxor %edx,%edx\ntest %r8d,%r8d\nsetg %dl\nadd $0x4,%rdi\nadd %edx,%eax\ncmp %rdi,%rcx\njne 13b0 \npxor %xmm0,%xmm0\ncvtsi2sd %eax,%xmm0\npxor %xmm1,%xmm1\ncvtsi2sd %esi,%xmm1\ndivsd %xmm1,%xmm0\nmulsd 0xcae(%rip),%xmm0\ncallq 1070 \ndivsd 0xca1(%rip),%xmm0\nadd $0x8,%rsp\nretq\nnopl 0x0(%rax)\npxor %xmm0,%xmm0\njmp 13ce \nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\ntest esi, esi\njle short loc_1380\nmovsxd rax, esi\nlea rcx, [rdi+rax*4]\nxor eax, eax\nnop dword ptr [rax]\nloc_1338:\nmov r8d, [rdi]\nxor edx, edx\ntest r8d, r8d\nsetnle dl\nadd rdi, 4\nadd eax, edx\ncmp rdi, rcx\njnz short loc_1338\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nloc_1356:\npxor xmm1, xmm1\ncvtsi2sd xmm1, esi\ndivsd xmm0, xmm1\nmulsd xmm0, cs:qword_2078; x\ncall _round\ndivsd xmm0, cs:qword_2078\nadd rsp, 8\nretn\nloc_1380:\npxor xmm0, xmm0\njmp short loc_1356", + "ida_pseudo": "double __fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rcx\n int v3; // eax\n int v4; // edx\n double v5; // xmm0_8\n\n if ( a2 <= 0 )\n {\n v5 = 0.0;\n }\n else\n {\n v2 = &a1[a2];\n v3 = 0;\n do\n {\n v4 = *a1++ > 0;\n v3 += v4;\n }\n while ( a1 != v2 );\n v5 = (double)v3;\n }\n return round(v5 / (double)a2 * 100.0) / 100.0;\n}", + "ida_strip_asm": "sub_1320:\nendbr64\nsub rsp, 8\ntest esi, esi\njle short loc_1380\nmovsxd rax, esi\nlea rcx, [rdi+rax*4]\nxor eax, eax\nnop dword ptr [rax]\nloc_1338:\nmov r8d, [rdi]\nxor edx, edx\ntest r8d, r8d\nsetnle dl\nadd rdi, 4\nadd eax, edx\ncmp rdi, rcx\njnz short loc_1338\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nloc_1356:\npxor xmm1, xmm1\ncvtsi2sd xmm1, esi\ndivsd xmm0, xmm1\nmulsd xmm0, cs:qword_2078; x\ncall _round\ndivsd xmm0, cs:qword_2078\nadd rsp, 8\nretn\nloc_1380:\npxor xmm0, xmm0\njmp short loc_1356", + "ida_strip_pseudo": "double __fastcall sub_1320(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rcx\n int v3; // eax\n int v4; // edx\n double v5; // xmm0_8\n\n if ( a2 <= 0 )\n {\n v5 = 0.0;\n }\n else\n {\n v2 = &a1[a2];\n v3 = 0;\n do\n {\n v4 = *a1++ > 0;\n v3 += v4;\n }\n while ( a1 != v2 );\n v5 = (double)v3;\n }\n return round(v5 / (double)a2 * 100.0) / 100.0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1320(uint32_t *a1, int a2) {\n uint32_t *v2;\n int v3;\n int v4;\n double v5;\n if (a2 <= 0) {\n v5 = 0.0;\n } else {\n v2 = &a1[a2];\n v3 = 0;\n do {\n v4 = *a1++ > 0;\n v3 += v4;\n } while (a1 != v2);\n v5 = (double)v3;\n }\n return round(v5 / (double)a2 * 100.0) / 100.0;\n}", + "ida_pseudo_norm": "double func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n int v3;\n int v4;\n double v5;\n if (a2 <= 0) {\n v5 = 0.0;\n } else {\n v2 = &a1[a2];\n v3 = 0;\n do {\n v4 = *a1++ > 0;\n v3 += v4;\n } while (a1 != v2);\n v5 = (double)v3;\n }\n return round(v5 / (double)a2 * 100.0) / 100.0;\n}" + }, + { + "index": 442, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int nums[], int n) {\n int n1 = 0;\n for (int i = 0; i < n; i++) {\n if (nums[i] > 0) {\n n1 += 1;\n }\n }\n double result = ((double)n1 / n);\n result = round(result * 100) / 100;\n return result;\n}", + "test": "int main() {\n\n int arr1[] = {0, 1, 2, -1, -5, 6, 0, -3, -2, 3, 4, 6, 8};\n\n assert(func0(arr1, 13) == 0.54);\n\n \n\n int arr2[] = {2, 1, 2, -1, -5, 6, 4, -3, -2, 3, 4, 6, 8};\n\n assert(func0(arr2, 13) == 0.69);\n\n \n\n int arr3[] = {2, 4, -6, -9, 11, -12, 14, -5, 17};\n\n assert(func0(arr3, 9) == 0.56);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x8,%rsp\ntest %esi,%esi\njle 1418 \nlea -0x1(%rsi),%eax\ncmp $0x3,%eax\njbe 141e \nmov %esi,%edx\npxor %xmm0,%xmm0\nmov %rdi,%rax\nshr $0x2,%edx\nmovdqa %xmm0,%xmm2\nshl $0x4,%rdx\nadd %rdi,%rdx\nnopl 0x0(%rax,%rax,1)\nmovdqu (%rax),%xmm1\nadd $0x10,%rax\npcmpgtd %xmm2,%xmm1\npsubd %xmm1,%xmm0\ncmp %rdx,%rax\njne 1358 \nmovdqa %xmm0,%xmm1\nmov %esi,%edx\npsrldq $0x8,%xmm1\nand $0xfffffffc,%edx\npaddd %xmm1,%xmm0\nmovdqa %xmm0,%xmm1\npsrldq $0x4,%xmm1\npaddd %xmm1,%xmm0\nmovd %xmm0,%eax\ntest $0x3,%sil\nje 13e3 \nmovslq %edx,%rcx\nmov (%rdi,%rcx,4),%r9d\ntest %r9d,%r9d\njle 13a5 \nadd $0x1,%eax\nlea 0x1(%rdx),%ecx\ncmp %esi,%ecx\njge 13e3 \nmovslq %ecx,%rcx\nmov (%rdi,%rcx,4),%r8d\ntest %r8d,%r8d\njle 13bb \nadd $0x1,%eax\nlea 0x2(%rdx),%ecx\ncmp %ecx,%esi\njle 13e3 \nmovslq %ecx,%rcx\nmov (%rdi,%rcx,4),%ecx\ntest %ecx,%ecx\njle 13cf \nadd $0x1,%eax\nadd $0x3,%edx\ncmp %edx,%esi\njle 13e3 \nmovslq %edx,%rdx\nmov (%rdi,%rdx,4),%edx\ntest %edx,%edx\njle 13e3 \nadd $0x1,%eax\npxor %xmm0,%xmm0\ncvtsi2sd %eax,%xmm0\npxor %xmm1,%xmm1\ncvtsi2sd %esi,%xmm1\ndivsd %xmm1,%xmm0\nmulsd 0xc91(%rip),%xmm0\ncallq 1070 \ndivsd 0xc84(%rip),%xmm0\nadd $0x8,%rsp\nretq\nnopl 0x0(%rax)\npxor %xmm0,%xmm0\njmp 13eb \nxor %edx,%edx\nxor %eax,%eax\njmpq 1396 \nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\ntest esi, esi\njle loc_1410\nlea eax, [rsi-1]\nmov rcx, rdi\ncmp eax, 2\njbe loc_1416\nmov edx, esi\npxor xmm0, xmm0\nmov rax, rdi\nshr edx, 2\nmovdqa xmm2, xmm0\nshl rdx, 4\nadd rdx, rdi\nnop word ptr [rax+rax+00000000h]\nloc_1360:\nmovdqu xmm1, xmmword ptr [rax]\nadd rax, 10h\npcmpgtd xmm1, xmm2\npsubd xmm0, xmm1\ncmp rax, rdx\njnz short loc_1360\nmovdqa xmm1, xmm0\nmov edx, esi\npsrldq xmm1, 8\nand edx, 0FFFFFFFCh\npaddd xmm0, xmm1\nmovdqa xmm1, xmm0\npsrldq xmm1, 4\npaddd xmm0, xmm1\nmovd eax, xmm0\ntest sil, 3\njz short loc_13DB\nloc_139E:\nmovsxd rdi, edx\nmov r9d, [rcx+rdi*4]\nlea r8, ds:0[rdi*4]\ntest r9d, r9d\njle short loc_13B5\nadd eax, 1\nloc_13B5:\nlea edi, [rdx+1]\ncmp esi, edi\njle short loc_13DB\nmov edi, [rcx+r8+4]\ntest edi, edi\njle short loc_13C8\nadd eax, 1\nloc_13C8:\nadd edx, 2\ncmp esi, edx\njle short loc_13DB\nmov edx, [rcx+r8+8]\ntest edx, edx\njle short loc_13DB\nadd eax, 1\nloc_13DB:\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nloc_13E3:\npxor xmm1, xmm1\ncvtsi2sd xmm1, esi\ndivsd xmm0, xmm1\nmulsd xmm0, cs:qword_2078; x\ncall _round\ndivsd xmm0, cs:qword_2078\nadd rsp, 8\nretn\nloc_1410:\npxor xmm0, xmm0\njmp short loc_13E3\nloc_1416:\nxor edx, edx\nxor eax, eax\njmp short loc_139E", + "ida_pseudo": "double __fastcall func0(const __m128i *a1, int a2)\n{\n __m128i v2; // xmm0\n const __m128i *v3; // rax\n __m128i v4; // xmm1\n int v5; // edx\n __m128i v6; // xmm0\n int v7; // eax\n __int64 v8; // r8\n double v9; // xmm0_8\n\n if ( a2 <= 0 )\n {\n v9 = 0.0;\n return round(v9 / (double)a2 * 100.0) / 100.0;\n }\n if ( (unsigned int)(a2 - 1) <= 2 )\n {\n v5 = 0;\n v7 = 0;\nLABEL_6:\n v8 = v5;\n if ( a1->m128i_i32[v8] > 0 )\n ++v7;\n if ( a2 > v5 + 1 )\n {\n if ( a1->m128i_i32[v8 + 1] > 0 )\n ++v7;\n if ( a2 > v5 + 2 && a1->m128i_i32[v8 + 2] > 0 )\n ++v7;\n }\n goto LABEL_14;\n }\n v2 = 0LL;\n v3 = a1;\n do\n {\n v4 = _mm_loadu_si128(v3++);\n v2 = _mm_sub_epi32(v2, _mm_cmpgt_epi32(v4, (__m128i)0LL));\n }\n while ( v3 != &a1[(unsigned int)a2 >> 2] );\n v5 = a2 & 0x7FFFFFFC;\n v6 = _mm_add_epi32(v2, _mm_srli_si128(v2, 8));\n v7 = _mm_cvtsi128_si32(_mm_add_epi32(v6, _mm_srli_si128(v6, 4)));\n if ( (a2 & 3) != 0 )\n goto LABEL_6;\nLABEL_14:\n v9 = (double)v7;\n return round(v9 / (double)a2 * 100.0) / 100.0;\n}", + "ida_strip_asm": "sub_1320:\nendbr64\nsub rsp, 8\ntest esi, esi\njle loc_1410\nlea eax, [rsi-1]\nmov rcx, rdi\ncmp eax, 2\njbe loc_1416\nmov edx, esi\npxor xmm0, xmm0\nmov rax, rdi\nshr edx, 2\nmovdqa xmm2, xmm0\nshl rdx, 4\nadd rdx, rdi\nnop word ptr [rax+rax+00000000h]\nloc_1360:\nmovdqu xmm1, xmmword ptr [rax]\nadd rax, 10h\npcmpgtd xmm1, xmm2\npsubd xmm0, xmm1\ncmp rax, rdx\njnz short loc_1360\nmovdqa xmm1, xmm0\nmov edx, esi\npsrldq xmm1, 8\nand edx, 0FFFFFFFCh\npaddd xmm0, xmm1\nmovdqa xmm1, xmm0\npsrldq xmm1, 4\npaddd xmm0, xmm1\nmovd eax, xmm0\ntest sil, 3\njz short loc_13DB\nloc_139E:\nmovsxd rdi, edx\nmov r9d, [rcx+rdi*4]\nlea r8, ds:0[rdi*4]\ntest r9d, r9d\njle short loc_13B5\nadd eax, 1\nloc_13B5:\nlea edi, [rdx+1]\ncmp esi, edi\njle short loc_13DB\nmov edi, [rcx+r8+4]\ntest edi, edi\njle short loc_13C8\nadd eax, 1\nloc_13C8:\nadd edx, 2\ncmp esi, edx\njle short loc_13DB\nmov edx, [rcx+r8+8]\ntest edx, edx\njle short loc_13DB\nadd eax, 1\nloc_13DB:\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nloc_13E3:\npxor xmm1, xmm1\ncvtsi2sd xmm1, esi\ndivsd xmm0, xmm1\nmulsd xmm0, cs:qword_2078; x\ncall _round\ndivsd xmm0, cs:qword_2078\nadd rsp, 8\nretn\nloc_1410:\npxor xmm0, xmm0\njmp short loc_13E3\nloc_1416:\nxor edx, edx\nxor eax, eax\njmp short loc_139E", + "ida_strip_pseudo": "double __fastcall sub_1320(const __m128i *a1, int a2)\n{\n __m128i v2; // xmm0\n const __m128i *v3; // rax\n __m128i v4; // xmm1\n int v5; // edx\n __m128i v6; // xmm0\n int v7; // eax\n __int64 v8; // r8\n double v9; // xmm0_8\n\n if ( a2 <= 0 )\n {\n v9 = 0.0;\n return round(v9 / (double)a2 * 100.0) / 100.0;\n }\n if ( (unsigned int)(a2 - 1) <= 2 )\n {\n v5 = 0;\n v7 = 0;\nLABEL_6:\n v8 = v5;\n if ( a1->m128i_i32[v8] > 0 )\n ++v7;\n if ( a2 > v5 + 1 )\n {\n if ( a1->m128i_i32[v8 + 1] > 0 )\n ++v7;\n if ( a2 > v5 + 2 && a1->m128i_i32[v8 + 2] > 0 )\n ++v7;\n }\n goto LABEL_14;\n }\n v2 = 0LL;\n v3 = a1;\n do\n {\n v4 = _mm_loadu_si128(v3++);\n v2 = _mm_sub_epi32(v2, _mm_cmpgt_epi32(v4, (__m128i)0LL));\n }\n while ( v3 != &a1[(unsigned int)a2 >> 2] );\n v5 = a2 & 0x7FFFFFFC;\n v6 = _mm_add_epi32(v2, _mm_srli_si128(v2, 8));\n v7 = _mm_cvtsi128_si32(_mm_add_epi32(v6, _mm_srli_si128(v6, 4)));\n if ( (a2 & 3) != 0 )\n goto LABEL_6;\nLABEL_14:\n v9 = (double)v7;\n return round(v9 / (double)a2 * 100.0) / 100.0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1320(const __m128i *a1, int a2) {\n __m128i v2;\n const __m128i *v3;\n __m128i v4;\n int v5;\n __m128i v6;\n int v7;\n long long v8;\n double v9;\n if (a2 <= 0) {\n v9 = 0.0;\n return round(v9 / (double)a2 * 100.0) / 100.0;\n }\n if ((unsigned int)(a2 - 1) <= 2) {\n v5 = 0;\n v7 = 0;\n LABEL_6:\n v8 = v5;\n if (a1->m128i_i32[v8] > 0) ++v7;\n if (a2 > v5 + 1) {\n if (a1->m128i_i32[v8 + 1] > 0) ++v7;\n if (a2 > v5 + 2 && a1->m128i_i32[v8 + 2] > 0) ++v7;\n }\n goto LABEL_14;\n }\n v2 = 0LL;\n v3 = a1;\n do {\n v4 = _mm_loadu_si128(v3++);\n v2 = _mm_sub_epi32(v2, _mm_cmpgt_epi32(v4, (__m128i)0LL));\n } while (v3 != &a1[(unsigned int)a2 >> 2]);\n v5 = a2 & 2147483644;\n v6 = _mm_add_epi32(v2, _mm_srli_si128(v2, 8));\n v7 = _mm_cvtsi128_si32(_mm_add_epi32(v6, _mm_srli_si128(v6, 4)));\n if ((a2 & 3) != 0) goto LABEL_6;\nLABEL_14:\n v9 = (double)v7;\n return round(v9 / (double)a2 * 100.0) / 100.0;\n}", + "ida_pseudo_norm": "double func0(const __m128i *a1, int a2) {\n __m128i v2;\n const __m128i *v3;\n __m128i v4;\n int v5;\n __m128i v6;\n int v7;\n long long v8;\n double v9;\n if (a2 <= 0) {\n v9 = 0.0;\n return round(v9 / (double)a2 * 100.0) / 100.0;\n }\n if ((unsigned int)(a2 - 1) <= 2) {\n v5 = 0;\n v7 = 0;\n LABEL_6:\n v8 = v5;\n if (a1->m128i_i32[v8] > 0) ++v7;\n if (a2 > v5 + 1) {\n if (a1->m128i_i32[v8 + 1] > 0) ++v7;\n if (a2 > v5 + 2 && a1->m128i_i32[v8 + 2] > 0) ++v7;\n }\n goto LABEL_14;\n }\n v2 = 0LL;\n v3 = a1;\n do {\n v4 = _mm_loadu_si128(v3++);\n v2 = _mm_sub_epi32(v2, _mm_cmpgt_epi32(v4, (__m128i)0LL));\n } while (v3 != &a1[(unsigned int)a2 >> 2]);\n v5 = a2 & 2147483644;\n v6 = _mm_add_epi32(v2, _mm_srli_si128(v2, 8));\n v7 = _mm_cvtsi128_si32(_mm_add_epi32(v6, _mm_srli_si128(v6, 4)));\n if ((a2 & 3) != 0) goto LABEL_6;\nLABEL_14:\n v9 = (double)v7;\n return round(v9 / (double)a2 * 100.0) / 100.0;\n}" + }, + { + "index": 443, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int list1[], int size) {\n int max = list1[0];\n for (int i = 0; i < size; i++) {\n if (list1[i] < max) {\n max = list1[i];\n }\n }\n return max;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, -4, -6};\n\n int arr2[] = {1, 2, 3, -8, -9};\n\n int arr3[] = {1, 2, 3, 4, -1};\n\n\n\n assert(func0(arr1, 5) == -6);\n\n assert(func0(arr2, 5) == -9);\n\n assert(func0(arr3, 5) == -1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov -0x18(%rbp),%rax\nmov (%rax),%eax\nmov %eax,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11c2 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x8(%rbp)\njle 11be \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 118a \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov rax, [rbp+var_18]\nmov eax, [rax]\nmov [rbp+var_8], eax\nmov [rbp+var_4], 0\njmp short loc_11C2\nloc_118A:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_8], eax\njle short loc_11BE\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_8], eax\nloc_11BE:\nadd [rbp+var_4], 1\nloc_11C2:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_118A\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = *a1;\n for ( i = 0; i < a2; ++i )\n {\n if ( (int)v3 > (int)a1[i] )\n v3 = a1[i];\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov rax, [rbp+var_18]\nmov eax, [rax]\nmov [rbp+var_8], eax\nmov [rbp+var_4], 0\njmp short loc_11C2\nloc_118A:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_8], eax\njle short loc_11BE\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_8], eax\nloc_11BE:\nadd [rbp+var_4], 1\nloc_11C2:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_118A\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(unsigned int *a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = *a1;\n for ( i = 0; i < a2; ++i )\n {\n if ( (int)v3 > (int)a1[i] )\n v3 = a1[i];\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(unsigned int *a1, int a2) {\n unsigned int v3;\n int i;\n v3 = *a1;\n for (i = 0; i < a2; ++i) {\n if ((int)v3 > (int)a1[i]) v3 = a1[i];\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n unsigned int v3;\n int i;\n v3 = *a1;\n for (i = 0; i < a2; ++i) {\n if ((int)v3 > (int)a1[i]) v3 = a1[i];\n }\n return v3;\n}" + }, + { + "index": 443, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int list1[], int size) {\n int max = list1[0];\n for (int i = 0; i < size; i++) {\n if (list1[i] < max) {\n max = list1[i];\n }\n }\n return max;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, -4, -6};\n\n int arr2[] = {1, 2, 3, -8, -9};\n\n int arr3[] = {1, 2, 3, 4, -1};\n\n\n\n assert(func0(arr1, 5) == -6);\n\n assert(func0(arr2, 5) == -9);\n\n assert(func0(arr3, 5) == -1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov (%rdi),%edx\ntest %esi,%esi\njle 118e \nmov %rdi,%rax\nlea -0x1(%rsi),%ecx\nlea 0x4(%rdi,%rcx,4),%rsi\nmov (%rax),%ecx\ncmp %ecx,%edx\ncmovg %ecx,%edx\nadd $0x4,%rax\ncmp %rsi,%rax\njne 117e \nmov %edx,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov edx, [rdi]\ntest esi, esi\njle short loc_118D\nmov rax, rdi\nmovsxd rsi, esi\nlea rsi, [rdi+rsi*4]\nloc_117D:\nmov ecx, [rax]\ncmp edx, ecx\ncmovg edx, ecx\nadd rax, 4\ncmp rax, rsi\njnz short loc_117D\nloc_118D:\nmov eax, edx\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n unsigned int v2; // edx\n unsigned int *v3; // rax\n unsigned int *v4; // rsi\n\n v2 = *a1;\n if ( a2 > 0 )\n {\n v3 = a1;\n v4 = &a1[a2];\n do\n {\n if ( (int)v2 > (int)*v3 )\n v2 = *v3;\n ++v3;\n }\n while ( v3 != v4 );\n }\n return v2;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov edx, [rdi]\ntest esi, esi\njle short loc_118D\nmov rax, rdi\nmovsxd rsi, esi\nlea rsi, [rdi+rsi*4]\nloc_117D:\nmov ecx, [rax]\ncmp edx, ecx\ncmovg edx, ecx\nadd rax, 4\ncmp rax, rsi\njnz short loc_117D\nloc_118D:\nmov eax, edx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(unsigned int *a1, int a2)\n{\n unsigned int v2; // edx\n unsigned int *v3; // rax\n unsigned int *v4; // rsi\n\n v2 = *a1;\n if ( a2 > 0 )\n {\n v3 = a1;\n v4 = &a1[a2];\n do\n {\n if ( (int)v2 > (int)*v3 )\n v2 = *v3;\n ++v3;\n }\n while ( v3 != v4 );\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(unsigned int *a1, int a2) {\n unsigned int v2;\n unsigned int *v3;\n unsigned int *v4;\n v2 = *a1;\n if (a2 > 0) {\n v3 = a1;\n v4 = &a1[a2];\n do {\n if ((int)v2 > (int)*v3) v2 = *v3;\n ++v3;\n } while (v3 != v4);\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n unsigned int v2;\n unsigned int *v3;\n unsigned int *v4;\n v2 = *a1;\n if (a2 > 0) {\n v3 = a1;\n v4 = &a1[a2];\n do {\n if ((int)v2 > (int)*v3) v2 = *v3;\n ++v3;\n } while (v3 != v4);\n }\n return v2;\n}" + }, + { + "index": 444, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(int test_list[][5], int rows, int K, int N) {\n char* result = (char*)malloc(1000 * sizeof(char));\n strcpy(result, \"\");\n strcat(result, \"[\");\n for (int i = 0; i < rows; i++) {\n strcat(result, \"(\");\n for (int j = K; j < N - K; j++) {\n char num_str[10];\n sprintf(num_str, \"%d\", test_list[i][j]);\n strcat(result, num_str);\n if (j < N - K - 1) strcat(result, \", \");\n }\n strcat(result, \")\");\n if (i < rows - 1) strcat(result, \", \");\n }\n strcat(result, \"]\");\n return result;\n}", + "test": "int main() {\n\n int list1[4][5] = {{5, 3, 2, 1, 4}, {3, 4, 9, 2, 1}, {9, 1, 2, 3, 5}, {4, 8, 2, 1, 7}};\n\n int list2[4][5] = {{7, 8, 4, 9}, {11, 8, 12, 4}, {4, 1, 7, 8}, {3, 6, 9, 7}};\n\n\n\n char* res1 = func0(list1, 4, 2, 5);\n\n char* res2 = func0(list1, 4, 1, 5);\n\n char* res3 = func0(list2, 4, 1, 4);\n\n\n\n assert(strcmp(res1, \"[(2), (9), (2), (2)]\") == 0);\n\n assert(strcmp(res2, \"[(3, 2, 1), (4, 9, 2), (1, 2, 3), (8, 2, 1)]\") == 0);\n\n assert(strcmp(res3, \"[(8, 4), (8, 12), (1, 7), (6, 9)]\") == 0);\n\n \n\n free(res1);\n\n free(res2);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x50,%rsp\nmov %rdi,-0x38(%rbp)\nmov %esi,-0x3c(%rbp)\nmov %edx,-0x40(%rbp)\nmov %ecx,-0x44(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmov $0x3e8,%edi\ncallq 10f0 \nmov %rax,-0x20(%rbp)\nmov -0x20(%rbp),%rax\nmovb $0x0,(%rax)\nmov -0x20(%rbp),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmovw $0x5b,(%rax)\nmovl $0x0,-0x28(%rbp)\njmpq 13cc \nmov -0x20(%rbp),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmovw $0x28,(%rax)\nmov -0x40(%rbp),%eax\nmov %eax,-0x24(%rbp)\njmpq 134e \nmov -0x28(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x38(%rbp),%rax\nadd %rax,%rdx\nmov -0x24(%rbp),%eax\ncltq\nmov (%rdx,%rax,4),%edx\nlea -0x12(%rbp),%rax\nlea 0xd1e(%rip),%rsi\nmov %rax,%rdi\nmov $0x0,%eax\ncallq 1110 \nlea -0x12(%rbp),%rdx\nmov -0x20(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1100 \nmov -0x44(%rbp),%eax\nsub -0x40(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x24(%rbp)\njge 134a \nmov -0x20(%rbp),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmovw $0x202c,(%rax)\nmovb $0x0,0x2(%rax)\naddl $0x1,-0x24(%rbp)\nmov -0x44(%rbp),%eax\nsub -0x40(%rbp),%eax\ncmp %eax,-0x24(%rbp)\njl 12b9 \nmov -0x20(%rbp),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmovw $0x29,(%rax)\nmov -0x3c(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x28(%rbp)\njge 13c8 \nmov -0x20(%rbp),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmovw $0x202c,(%rax)\nmovb $0x0,0x2(%rax)\naddl $0x1,-0x28(%rbp)\nmov -0x28(%rbp),%eax\ncmp -0x3c(%rbp),%eax\njl 1280 \nmov -0x20(%rbp),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmovw $0x5d,(%rax)\nmov -0x20(%rbp),%rax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 141e \ncallq 10c0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov [rbp+var_40], edx\nmov [rbp+var_44], ecx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov edi, 3E8h; size\ncall _malloc\nmov [rbp+s], rax\nmov rax, [rbp+s]\nmov byte ptr [rax], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+s]\nadd rax, rdx\nmov word ptr [rax], 5Bh ; '['\nmov [rbp+var_28], 0\njmp loc_1390\nloc_128D:\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+s]\nadd rax, rdx\nmov word ptr [rax], 28h ; '('\nmov eax, [rbp+var_40]\nmov [rbp+var_24], eax\njmp loc_1338\nloc_12B3:\nmov eax, [rbp+var_28]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_38]\nadd rdx, rax\nmov eax, [rbp+var_24]\ncdqe\nmov edx, [rdx+rax*4]\nlea rax, [rbp+src]\nlea rcx, format; \"%d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rdx, [rbp+src]\nmov rax, [rbp+s]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\nmov eax, [rbp+var_44]\nsub eax, [rbp+var_40]\nsub eax, 1\ncmp [rbp+var_24], eax\njge short loc_1334\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+s]\nadd rax, rdx\nmov word ptr [rax], 202Ch\nmov byte ptr [rax+2], 0\nloc_1334:\nadd [rbp+var_24], 1\nloc_1338:\nmov eax, [rbp+var_44]\nsub eax, [rbp+var_40]\ncmp [rbp+var_24], eax\njl loc_12B3\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+s]\nadd rax, rdx\nmov word ptr [rax], 29h ; ')'\nmov eax, [rbp+var_3C]\nsub eax, 1\ncmp [rbp+var_28], eax\njge short loc_138C\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+s]\nadd rax, rdx\nmov word ptr [rax], 202Ch\nmov byte ptr [rax+2], 0\nloc_138C:\nadd [rbp+var_28], 1\nloc_1390:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_3C]\njl loc_128D\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+s]\nadd rax, rdx\nmov word ptr [rax], 5Dh ; ']'\nmov rax, [rbp+s]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_13CF\ncall ___stack_chk_fail\nlocret_13CF:\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2, int a3, int a4)\n{\n int i; // [rsp+28h] [rbp-28h]\n int j; // [rsp+2Ch] [rbp-24h]\n char *s; // [rsp+30h] [rbp-20h]\n char src[10]; // [rsp+3Eh] [rbp-12h] BYREF\n unsigned __int64 v11; // [rsp+48h] [rbp-8h]\n\n v11 = __readfsqword(0x28u);\n s = (char *)malloc(0x3E8uLL);\n *s = 0;\n *(_WORD *)&s[strlen(s)] = 91;\n for ( i = 0; i < a2; ++i )\n {\n *(_WORD *)&s[strlen(s)] = 40;\n for ( j = a3; j < a4 - a3; ++j )\n {\n sprintf(src, \"%d\", *(_DWORD *)(a1 + 20LL * i + 4LL * j));\n strcat(s, src);\n if ( j < a4 - a3 - 1 )\n strcpy(&s[strlen(s)], \", \");\n }\n *(_WORD *)&s[strlen(s)] = 41;\n if ( i < a2 - 1 )\n strcpy(&s[strlen(s)], \", \");\n }\n *(_WORD *)&s[strlen(s)] = 93;\n return s;\n}", + "ida_strip_asm": "sub_1229:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov [rbp+var_40], edx\nmov [rbp+var_44], ecx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov edi, 3E8h; size\ncall _malloc\nmov [rbp+s], rax\nmov rax, [rbp+s]\nmov byte ptr [rax], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+s]\nadd rax, rdx\nmov word ptr [rax], 5Bh ; '['\nmov [rbp+var_28], 0\njmp loc_1390\nloc_128D:\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+s]\nadd rax, rdx\nmov word ptr [rax], 28h ; '('\nmov eax, [rbp+var_40]\nmov [rbp+var_24], eax\njmp loc_1338\nloc_12B3:\nmov eax, [rbp+var_28]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_38]\nadd rdx, rax\nmov eax, [rbp+var_24]\ncdqe\nmov edx, [rdx+rax*4]\nlea rax, [rbp+src]\nlea rcx, format; \"%d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rdx, [rbp+src]\nmov rax, [rbp+s]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\nmov eax, [rbp+var_44]\nsub eax, [rbp+var_40]\nsub eax, 1\ncmp [rbp+var_24], eax\njge short loc_1334\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+s]\nadd rax, rdx\nmov word ptr [rax], 202Ch\nmov byte ptr [rax+2], 0\nloc_1334:\nadd [rbp+var_24], 1\nloc_1338:\nmov eax, [rbp+var_44]\nsub eax, [rbp+var_40]\ncmp [rbp+var_24], eax\njl loc_12B3\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+s]\nadd rax, rdx\nmov word ptr [rax], 29h ; ')'\nmov eax, [rbp+var_3C]\nsub eax, 1\ncmp [rbp+var_28], eax\njge short loc_138C\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+s]\nadd rax, rdx\nmov word ptr [rax], 202Ch\nmov byte ptr [rax+2], 0\nloc_138C:\nadd [rbp+var_28], 1\nloc_1390:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_3C]\njl loc_128D\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+s]\nadd rax, rdx\nmov word ptr [rax], 5Dh ; ']'\nmov rax, [rbp+s]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_13CF\ncall ___stack_chk_fail\nlocret_13CF:\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1229(__int64 a1, int a2, int a3, int a4)\n{\n int i; // [rsp+28h] [rbp-28h]\n int j; // [rsp+2Ch] [rbp-24h]\n char *s; // [rsp+30h] [rbp-20h]\n char src[10]; // [rsp+3Eh] [rbp-12h] BYREF\n unsigned __int64 v11; // [rsp+48h] [rbp-8h]\n\n v11 = __readfsqword(0x28u);\n s = (char *)malloc(0x3E8uLL);\n *s = 0;\n *(_WORD *)&s[strlen(s)] = 91;\n for ( i = 0; i < a2; ++i )\n {\n *(_WORD *)&s[strlen(s)] = 40;\n for ( j = a3; j < a4 - a3; ++j )\n {\n sprintf(src, \"%d\", *(_DWORD *)(a1 + 20LL * i + 4LL * j));\n strcat(s, src);\n if ( j < a4 - a3 - 1 )\n strcpy(&s[strlen(s)], \", \");\n }\n *(_WORD *)&s[strlen(s)] = 41;\n if ( i < a2 - 1 )\n strcpy(&s[strlen(s)], \", \");\n }\n *(_WORD *)&s[strlen(s)] = 93;\n return s;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1229(long long a1, int a2, int a3, int a4) {\n int i;\n int j;\n char *s;\n char src[10];\n unsigned long long v11;\n v11 = __readfsqword(40u);\n s = (char *)malloc(1000uLL);\n *s = 0;\n *(unsigned short *)&s[strlen(s)] = 91;\n for (i = 0; i < a2; ++i) {\n *(unsigned short *)&s[strlen(s)] = 40;\n for (j = a3; j < a4 - a3; ++j) {\n sprintf(src, \"%d\", *(uint32_t *)(a1 + 20LL * i + 4LL * j));\n strcat(s, src);\n if (j < a4 - a3 - 1) strcpy(&s[strlen(s)], \", \");\n }\n *(unsigned short *)&s[strlen(s)] = 41;\n if (i < a2 - 1) strcpy(&s[strlen(s)], \", \");\n }\n *(unsigned short *)&s[strlen(s)] = 93;\n return s;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2, int a3, int a4) {\n int i;\n int j;\n char *s;\n char src[10];\n unsigned long long v11;\n v11 = __readfsqword(40u);\n s = (char *)malloc(1000uLL);\n *s = 0;\n *(unsigned short *)&s[strlen(s)] = 91;\n for (i = 0; i < a2; ++i) {\n *(unsigned short *)&s[strlen(s)] = 40;\n for (j = a3; j < a4 - a3; ++j) {\n sprintf(src, \"%d\", *(uint32_t *)(a1 + 20LL * i + 4LL * j));\n strcat(s, src);\n if (j < a4 - a3 - 1) strcpy(&s[strlen(s)], \", \");\n }\n *(unsigned short *)&s[strlen(s)] = 41;\n if (i < a2 - 1) strcpy(&s[strlen(s)], \", \");\n }\n *(unsigned short *)&s[strlen(s)] = 93;\n return s;\n}" + }, + { + "index": 444, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(int test_list[][5], int rows, int K, int N) {\n char* result = (char*)malloc(1000 * sizeof(char));\n strcpy(result, \"\");\n strcat(result, \"[\");\n for (int i = 0; i < rows; i++) {\n strcat(result, \"(\");\n for (int j = K; j < N - K; j++) {\n char num_str[10];\n sprintf(num_str, \"%d\", test_list[i][j]);\n strcat(result, num_str);\n if (j < N - K - 1) strcat(result, \", \");\n }\n strcat(result, \")\");\n if (i < rows - 1) strcat(result, \", \");\n }\n strcat(result, \"]\");\n return result;\n}", + "test": "int main() {\n\n int list1[4][5] = {{5, 3, 2, 1, 4}, {3, 4, 9, 2, 1}, {9, 1, 2, 3, 5}, {4, 8, 2, 1, 7}};\n\n int list2[4][5] = {{7, 8, 4, 9}, {11, 8, 12, 4}, {4, 1, 7, 8}, {3, 6, 9, 7}};\n\n\n\n char* res1 = func0(list1, 4, 2, 5);\n\n char* res2 = func0(list1, 4, 1, 5);\n\n char* res3 = func0(list2, 4, 1, 4);\n\n\n\n assert(strcmp(res1, \"[(2), (9), (2), (2)]\") == 0);\n\n assert(strcmp(res2, \"[(3, 2, 1), (4, 9, 2), (1, 2, 3), (8, 2, 1)]\") == 0);\n\n assert(strcmp(res3, \"[(8, 4), (8, 12), (1, 7), (6, 9)]\") == 0);\n\n \n\n free(res1);\n\n free(res2);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x38,%rsp\nmov %rdi,%rbx\nmov %esi,%r15d\nmov %esi,0x8(%rsp)\nmov %edx,%r14d\nmov %edx,0xc(%rsp)\nmov %ecx,%ebp\nmov %fs:0x28,%rax\nmov %rax,0x28(%rsp)\nxor %eax,%eax\nmov $0x3e8,%edi\ncallq 10e0 \nmov %rax,%r13\nmovb $0x0,(%rax)\nmov $0x3e8,%edx\nlea 0xdca(%rip),%rsi\nmov %rax,%rdi\ncallq 10a0 <__strcat_chk@plt>\ntest %r15d,%r15d\njle 1327 \nmov %rbx,(%rsp)\nmov $0x0,%r15d\nsub %r14d,%ebp\njmpq 12e4 \nmov $0x3e8,%edx\nlea 0xda2(%rip),%rsi\nmov %r13,%rdi\ncallq 10a0 <__strcat_chk@plt>\nadd $0x1,%rbx\ncmp %ebx,%ebp\njle 12b4 \nmov (%r14,%rbx,4),%r8d\nlea 0xd84(%rip),%rcx\nmov $0xa,%edx\nmov $0x1,%esi\nmov %r12,%rdi\nmov $0x0,%eax\ncallq 10f0 <__sprintf_chk@plt>\nmov $0x3e8,%edx\nmov %r12,%rsi\nmov %r13,%rdi\ncallq 10a0 <__strcat_chk@plt>\nlea -0x1(%rbp),%eax\ncmp %ebx,%eax\njle 1271 \njmp 125d \nmov $0x3e8,%edx\nlea 0xd4e(%rip),%rsi\nmov %r13,%rdi\ncallq 10a0 <__strcat_chk@plt>\nmov 0x8(%rsp),%eax\nsub $0x1,%eax\ncmp %r15d,%eax\njg 1311 \nadd $0x1,%r15d\naddq $0x14,(%rsp)\ncmp %r15d,0x8(%rsp)\nje 1327 \nmov $0x3e8,%edx\nlea 0xd16(%rip),%rsi\nmov %r13,%rdi\ncallq 10a0 <__strcat_chk@plt>\nmov 0xc(%rsp),%eax\ncmp %ebp,%eax\njge 12b4 \nmov (%rsp),%r14\nmovslq %eax,%rbx\nlea 0x1e(%rsp),%r12\njmpq 1279 \nmov $0x3e8,%edx\nlea 0xcee(%rip),%rsi\nmov %r13,%rdi\ncallq 10a0 <__strcat_chk@plt>\njmp 12d4 \nmov $0x3e8,%edx\nlea 0xcf0(%rip),%rsi\nmov %r13,%rdi\ncallq 10a0 <__strcat_chk@plt>\nmov 0x28(%rsp),%rax\nxor %fs:0x28,%rax\njne 135d \nmov %r13,%rax\nadd $0x38,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\ncallq 10c0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 48h\nmov rbx, rdi\nmov r14d, esi\nmov [rsp+78h+var_6C], esi\nmov [rsp+78h+var_60], edx\nmov [rsp+78h+var_5C], ecx\nmov rax, fs:28h\nmov [rsp+78h+var_40], rax\nxor eax, eax\nmov edi, 3E8h; size\ncall _malloc\nmov r12, rax\nmov byte ptr [rax], 0\nmov edx, 3E8h\nlea rsi, unk_2004\nmov rdi, rax\ncall ___strcat_chk\ntest r14d, r14d\njle loc_135B\nmov [rsp+78h+var_68], rbx\nmov [rsp+78h+var_70], 0\njmp loc_130A\nloc_127C:\nadd rbx, 1\ncmp r15d, ebx\njle short loc_12D2\nloc_1285:\nmov r8d, [r14+rbx*4]\nlea rcx, unk_2008\nmov edx, 0Ah\nmov esi, 2\nmov rdi, rbp\nmov eax, 0\ncall ___sprintf_chk\nmov edx, 3E8h\nmov rsi, rbp\nmov rdi, r12\ncall ___strcat_chk\ncmp r13d, ebx\njle short loc_127C\nmov edx, 3E8h\nlea rsi, unk_200B\nmov rdi, r12\ncall ___strcat_chk\njmp short loc_127C\nloc_12D2:\nmov edx, 3E8h\nlea rsi, unk_200E\nmov rdi, r12\ncall ___strcat_chk\nmov eax, [rsp+78h+var_6C]\nsub eax, 1\nmov ecx, [rsp+78h+var_70]\ncmp eax, ecx\njg short loc_1345\nloc_12F5:\nadd [rsp+78h+var_70], 1\nmov eax, [rsp+78h+var_70]\nadd [rsp+78h+var_68], 14h\ncmp [rsp+78h+var_6C], eax\njz short loc_135B\nloc_130A:\nmov edx, 3E8h\nlea rsi, unk_2006\nmov rdi, r12\ncall ___strcat_chk\nmov r15d, [rsp+78h+var_5C]\nmov eax, [rsp+78h+var_60]\nsub r15d, eax\ncmp r15d, eax\njle short loc_12D2\nmov r14, [rsp+78h+var_68]\nmovsxd rbx, eax\nlea rbp, [rsp+78h+var_4A]\nlea r13d, [r15-1]\njmp loc_1285\nloc_1345:\nmov edx, 3E8h\nlea rsi, unk_200B\nmov rdi, r12\ncall ___strcat_chk\njmp short loc_12F5\nloc_135B:\nmov edx, 3E8h\nlea rsi, s2+13h; \"]\"\nmov rdi, r12\ncall ___strcat_chk\nmov rax, [rsp+78h+var_40]\nsub rax, fs:28h\njnz short loc_1391\nmov rax, r12\nadd rsp, 48h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1391:\ncall ___stack_chk_fail", + "ida_pseudo": "_BYTE *__fastcall func0(__int64 a1, int a2, int a3, int a4)\n{\n _BYTE *v4; // r12\n __int64 v5; // rbx\n int v6; // r15d\n int i; // [rsp+8h] [rbp-70h]\n _BYTE v12[10]; // [rsp+2Eh] [rbp-4Ah] BYREF\n unsigned __int64 v13; // [rsp+38h] [rbp-40h]\n\n v13 = __readfsqword(0x28u);\n v4 = malloc(0x3E8uLL);\n *v4 = 0;\n __strcat_chk(v4, &unk_2004, 1000LL);\n if ( a2 > 0 )\n {\n for ( i = 0; i != a2; ++i )\n {\n __strcat_chk(v4, &unk_2006, 1000LL);\n v6 = a4 - a3;\n if ( a4 - a3 > a3 )\n {\n v5 = a3;\n do\n {\n __sprintf_chk(v12, 2LL, 10LL, &unk_2008, *(unsigned int *)(a1 + 4 * v5));\n __strcat_chk(v4, v12, 1000LL);\n if ( v6 - 1 > (int)v5 )\n __strcat_chk(v4, &unk_200B, 1000LL);\n ++v5;\n }\n while ( v6 > (int)v5 );\n }\n __strcat_chk(v4, &unk_200E, 1000LL);\n if ( a2 - 1 > i )\n __strcat_chk(v4, &unk_200B, 1000LL);\n a1 += 20LL;\n }\n }\n __strcat_chk(v4, \"]\", 1000LL);\n return v4;\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 48h\nmov rbx, rdi\nmov r14d, esi\nmov [rsp+78h+var_6C], esi\nmov [rsp+78h+var_60], edx\nmov [rsp+78h+var_5C], ecx\nmov rax, fs:28h\nmov [rsp+78h+var_40], rax\nxor eax, eax\nmov edi, 3E8h; size\ncall _malloc\nmov r12, rax\nmov byte ptr [rax], 0\nmov edx, 3E8h\nlea rsi, unk_2004\nmov rdi, rax\ncall ___strcat_chk\ntest r14d, r14d\njle loc_135B\nmov [rsp+78h+var_68], rbx\nmov [rsp+78h+var_70], 0\njmp loc_130A\nloc_127C:\nadd rbx, 1\ncmp r15d, ebx\njle short loc_12D2\nloc_1285:\nmov r8d, [r14+rbx*4]\nlea rcx, unk_2008\nmov edx, 0Ah\nmov esi, 2\nmov rdi, rbp\nmov eax, 0\ncall ___sprintf_chk\nmov edx, 3E8h\nmov rsi, rbp\nmov rdi, r12\ncall ___strcat_chk\ncmp r13d, ebx\njle short loc_127C\nmov edx, 3E8h\nlea rsi, unk_200B\nmov rdi, r12\ncall ___strcat_chk\njmp short loc_127C\nloc_12D2:\nmov edx, 3E8h\nlea rsi, unk_200E\nmov rdi, r12\ncall ___strcat_chk\nmov eax, [rsp+78h+var_6C]\nsub eax, 1\nmov ecx, [rsp+78h+var_70]\ncmp eax, ecx\njg short loc_1345\nloc_12F5:\nadd [rsp+78h+var_70], 1\nmov eax, [rsp+78h+var_70]\nadd [rsp+78h+var_68], 14h\ncmp [rsp+78h+var_6C], eax\njz short loc_135B\nloc_130A:\nmov edx, 3E8h\nlea rsi, unk_2006\nmov rdi, r12\ncall ___strcat_chk\nmov r15d, [rsp+78h+var_5C]\nmov eax, [rsp+78h+var_60]\nsub r15d, eax\ncmp r15d, eax\njle short loc_12D2\nmov r14, [rsp+78h+var_68]\nmovsxd rbx, eax\nlea rbp, [rsp+78h+var_4A]\nlea r13d, [r15-1]\njmp loc_1285\nloc_1345:\nmov edx, 3E8h\nlea rsi, unk_200B\nmov rdi, r12\ncall ___strcat_chk\njmp short loc_12F5\nloc_135B:\nmov edx, 3E8h\nlea rsi, s2+13h; \"]\"\nmov rdi, r12\ncall ___strcat_chk\nmov rax, [rsp+78h+var_40]\nsub rax, fs:28h\njnz short loc_1391\nmov rax, r12\nadd rsp, 48h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1391:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1209(__int64 a1, int a2, int a3, int a4)\n{\n _BYTE *v4; // r12\n __int64 v5; // rbx\n int v6; // r15d\n int i; // [rsp+8h] [rbp-70h]\n _BYTE v12[10]; // [rsp+2Eh] [rbp-4Ah] BYREF\n unsigned __int64 v13; // [rsp+38h] [rbp-40h]\n\n v13 = __readfsqword(0x28u);\n v4 = malloc(0x3E8uLL);\n *v4 = 0;\n __strcat_chk(v4, &unk_2004, 1000LL);\n if ( a2 > 0 )\n {\n for ( i = 0; i != a2; ++i )\n {\n __strcat_chk(v4, &unk_2006, 1000LL);\n v6 = a4 - a3;\n if ( a4 - a3 > a3 )\n {\n v5 = a3;\n do\n {\n __sprintf_chk(v12, 2LL, 10LL, &unk_2008, *(unsigned int *)(a1 + 4 * v5));\n __strcat_chk(v4, v12, 1000LL);\n if ( v6 - 1 > (int)v5 )\n __strcat_chk(v4, &unk_200B, 1000LL);\n ++v5;\n }\n while ( v6 > (int)v5 );\n }\n __strcat_chk(v4, &unk_200E, 1000LL);\n if ( a2 - 1 > i )\n __strcat_chk(v4, &unk_200B, 1000LL);\n a1 += 20LL;\n }\n }\n __strcat_chk(v4, \"]\", 1000LL);\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1209(long long a1, int a2, int a3, int a4) {\n uint8_t *v4;\n long long v5;\n int v6;\n int i;\n uint8_t v12[10];\n unsigned long long v13;\n v13 = __readfsqword(40u);\n v4 = malloc(1000uLL);\n *v4 = 0;\n __strcat_chk(v4, &unk_2004, 1000LL);\n if (a2 > 0) {\n for (i = 0; i != a2; ++i) {\n __strcat_chk(v4, &unk_2006, 1000LL);\n v6 = a4 - a3;\n if (a4 - a3 > a3) {\n v5 = a3;\n do {\n __sprintf_chk(v12, 2LL, 10LL, &unk_2008,\n *(unsigned int *)(a1 + 4 * v5));\n __strcat_chk(v4, v12, 1000LL);\n if (v6 - 1 > (int)v5) __strcat_chk(v4, &unk_200B, 1000LL);\n ++v5;\n } while (v6 > (int)v5);\n }\n __strcat_chk(v4, &unk_200E, 1000LL);\n if (a2 - 1 > i) __strcat_chk(v4, &unk_200B, 1000LL);\n a1 += 20LL;\n }\n }\n __strcat_chk(v4, \"]\", 1000LL);\n return v4;\n}", + "ida_pseudo_norm": "uint8_t *func0(long long a1, int a2, int a3, int a4) {\n uint8_t *v4;\n long long v5;\n int v6;\n int i;\n uint8_t v12[10];\n unsigned long long v13;\n v13 = __readfsqword(40u);\n v4 = malloc(1000uLL);\n *v4 = 0;\n __strcat_chk(v4, &unk_2004, 1000LL);\n if (a2 > 0) {\n for (i = 0; i != a2; ++i) {\n __strcat_chk(v4, &unk_2006, 1000LL);\n v6 = a4 - a3;\n if (a4 - a3 > a3) {\n v5 = a3;\n do {\n __sprintf_chk(v12, 2LL, 10LL, &unk_2008,\n *(unsigned int *)(a1 + 4 * v5));\n __strcat_chk(v4, v12, 1000LL);\n if (v6 - 1 > (int)v5) __strcat_chk(v4, &unk_200B, 1000LL);\n ++v5;\n } while (v6 > (int)v5);\n }\n __strcat_chk(v4, &unk_200E, 1000LL);\n if (a2 - 1 > i) __strcat_chk(v4, &unk_200B, 1000LL);\n a1 += 20LL;\n }\n }\n __strcat_chk(v4, \"]\", 1000LL);\n return v4;\n}" + }, + { + "index": 444, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(int test_list[][5], int rows, int K, int N) {\n char* result = (char*)malloc(1000 * sizeof(char));\n strcpy(result, \"\");\n strcat(result, \"[\");\n for (int i = 0; i < rows; i++) {\n strcat(result, \"(\");\n for (int j = K; j < N - K; j++) {\n char num_str[10];\n sprintf(num_str, \"%d\", test_list[i][j]);\n strcat(result, num_str);\n if (j < N - K - 1) strcat(result, \", \");\n }\n strcat(result, \")\");\n if (i < rows - 1) strcat(result, \", \");\n }\n strcat(result, \"]\");\n return result;\n}", + "test": "int main() {\n\n int list1[4][5] = {{5, 3, 2, 1, 4}, {3, 4, 9, 2, 1}, {9, 1, 2, 3, 5}, {4, 8, 2, 1, 7}};\n\n int list2[4][5] = {{7, 8, 4, 9}, {11, 8, 12, 4}, {4, 1, 7, 8}, {3, 6, 9, 7}};\n\n\n\n char* res1 = func0(list1, 4, 2, 5);\n\n char* res2 = func0(list1, 4, 1, 5);\n\n char* res3 = func0(list2, 4, 1, 4);\n\n\n\n assert(strcmp(res1, \"[(2), (9), (2), (2)]\") == 0);\n\n assert(strcmp(res2, \"[(3, 2, 1), (4, 9, 2), (1, 2, 3), (8, 2, 1)]\") == 0);\n\n assert(strcmp(res3, \"[(8, 4), (8, 12), (1, 7), (6, 9)]\") == 0);\n\n \n\n free(res1);\n\n free(res2);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\nmov %ecx,%r14d\npush %r13\nmov %rdi,%r13\nmov $0x3e8,%edi\npush %r12\npush %rbp\npush %rbx\nmov %esi,%ebx\nsub $0x48,%rsp\nmov %edx,0x14(%rsp)\nmov %esi,0x1c(%rsp)\nmov %fs:0x28,%rax\nmov %rax,0x38(%rsp)\nxor %eax,%eax\ncallq 1120 \nmov $0x5b,%edx\nmov %dx,(%rax)\nmov %rax,%r12\ntest %ebx,%ebx\njle 167d \nmov 0x1c(%rsp),%eax\nmovl $0x0,0x10(%rsp)\nlea 0xaf4(%rip),%r15\nsub 0x14(%rsp),%r14d\nsub $0x1,%eax\nmov %eax,0x18(%rsp)\nxchg %ax,%ax\nmov $0x3e8,%edx\nlea 0xad8(%rip),%rsi\nmov %r12,%rdi\ncallq 10c0 <__strcat_chk@plt>\ncmp 0x14(%rsp),%r14d\njle 15fa \nlea -0x1(%r14),%eax\nmovslq 0x14(%rsp),%rbx\nlea 0x2e(%rsp),%rbp\nmov %eax,0xc(%rsp)\njmp 1565 \nnopl 0x0(%rax,%rax,1)\nadd $0x1,%rbx\ncmp %ebx,%r14d\njle 15fa \nmov 0x0(%r13,%rbx,4),%r8d\nmov %rbp,%rdi\nmov %r15,%rcx\nmov $0xa,%edx\nmov $0x1,%esi\nxor %eax,%eax\ncallq 1130 <__sprintf_chk@plt>\nmov %r12,%rdi\nmov (%rdi),%edx\nadd $0x4,%rdi\nlea -0x1010101(%rdx),%eax\nnot %edx\nand %edx,%eax\nand $0x80808080,%eax\nje 1584 \nmov %eax,%edx\nshr $0x10,%edx\ntest $0x8080,%eax\ncmove %edx,%eax\nlea 0x2(%rdi),%rdx\ncmove %rdx,%rdi\nmov $0x3e8,%edx\nmov %eax,%esi\nadd %al,%sil\nmov %rbp,%rsi\nsbb $0x3,%rdi\ncallq 1110 <__stpcpy_chk@plt>\ncmp %ebx,0xc(%rsp)\njle 1558 \nmov %r12,%rcx\nmov $0x3,%edx\nmov %rax,%rdi\nadd $0x1,%rbx\nsub %rax,%rcx\nlea 0xa24(%rip),%rsi\nadd $0x3e8,%rcx\ncallq 1100 <__memcpy_chk@plt>\ncmp %ebx,%r14d\njg 1565 \nmov %r12,%rdi\nmov (%rdi),%edx\nadd $0x4,%rdi\nlea -0x1010101(%rdx),%eax\nnot %edx\nand %edx,%eax\nand $0x80808080,%eax\nje 15fd \nmov %eax,%edx\nshr $0x10,%edx\ntest $0x8080,%eax\ncmove %edx,%eax\nlea 0x2(%rdi),%rdx\ncmove %rdx,%rdi\nmov %eax,%esi\nadd %al,%sil\nmov $0x29,%eax\nmov 0x18(%rsp),%esi\nsbb $0x3,%rdi\nmov %ax,(%rdi)\nadd $0x1,%rdi\ncmp %esi,0x10(%rsp)\njge 1666 \nmov %r12,%rcx\nmov $0x3,%edx\nlea 0x9b2(%rip),%rsi\nsub %rdi,%rcx\nadd $0x3e8,%rcx\ncallq 1100 <__memcpy_chk@plt>\naddl $0x1,0x10(%rsp)\nadd $0x14,%r13\nmov 0x10(%rsp),%eax\ncmp %eax,0x1c(%rsp)\njne 1520 \nmov $0x3e8,%edx\nlea 0x996(%rip),%rsi\nmov %r12,%rdi\ncallq 10c0 <__strcat_chk@plt>\nmov 0x38(%rsp),%rax\nxor %fs:0x28,%rax\njne 16b3 \nadd $0x48,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\ncallq 10e0 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14d, esi\npush r13\npush r12\nmov r12d, ecx\npush rbp\nmov rbp, rdi\nmov edi, 3E8h; size\npush rbx\nsub rsp, 38h\nmov [rsp+68h+var_64], esi\nmov [rsp+68h+var_60], edx\nmov rax, fs:28h\nmov [rsp+68h+var_40], rax\nxor eax, eax\ncall _malloc\nmov ecx, 5Bh ; '['\nmov [rax], cx\nmov rbx, rax\ntest r14d, r14d\njle loc_15BC\nmov eax, [rsp+68h+var_64]\nmov [rsp+68h+var_68], 0\nsub eax, 1\nmov [rsp+68h+var_5C], eax\nmov eax, [rsp+68h+var_60]\nsub r12d, eax\nlea r14d, [r12-1]\nnop\nloc_14D0:\nmov edx, 3E8h\nlea rsi, unk_2004\nmov rdi, rbx\ncall ___strcat_chk\nmovsxd r13, [rsp+68h+var_60]\nlea r15, [rsp+68h+var_4A]\ncmp r12d, r13d\njg short loc_1501\njmp short loc_1569\nloc_14F8:\nadd r13, 1\ncmp r12d, r13d\njle short loc_1569\nloc_1501:\nmov r8d, [rbp+r13*4+0]\nmov edx, 0Ah\nmov rdi, r15\nxor eax, eax\nmov esi, 2\nlea rcx, unk_2006\ncall ___sprintf_chk\nmov rdi, rbx; s\ncall _strlen\nmov edx, 3E8h\nmov rsi, r15\nlea rdi, [rbx+rax]\ncall ___stpcpy_chk\ncmp r14d, r13d\njle short loc_14F8\nmov rcx, rbx\nmov edx, 3\nmov rdi, rax\nadd r13, 1\nsub rcx, rax\nlea rsi, unk_2009\nadd rcx, 3E8h\ncall ___memcpy_chk\ncmp r12d, r13d\njg short loc_1501\nloc_1569:\nmov rdi, rbx; s\ncall _strlen\nmov edx, 29h ; ')'\nmov esi, [rsp+68h+var_5C]\nadd rax, rbx\nmov [rax], dx\ncmp [rsp+68h+var_68], esi\njge short loc_15A7\nlea rdi, [rax+1]\nmov rcx, rbx\nmov edx, 3\nsub rcx, rdi\nlea rsi, unk_2009\nadd rcx, 3E8h\ncall ___memcpy_chk\nloc_15A7:\nadd [rsp+68h+var_68], 1\nadd rbp, 14h\nmov eax, [rsp+68h+var_68]\ncmp [rsp+68h+var_64], eax\njnz loc_14D0\nloc_15BC:\nmov edx, 3E8h\nlea rsi, s2+13h; \"]\"\nmov rdi, rbx\ncall ___strcat_chk\nmov rax, [rsp+68h+var_40]\nsub rax, fs:28h\njnz short loc_15F2\nadd rsp, 38h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15F2:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(__int64 a1, int a2, int a3, int a4)\n{\n char *v6; // rax\n const char *v7; // rbx\n int v8; // r12d\n __int64 v9; // r13\n size_t v10; // rax\n __int64 v11; // rax\n char *v12; // rax\n int v14; // [rsp+0h] [rbp-68h]\n _BYTE v16[10]; // [rsp+1Eh] [rbp-4Ah] BYREF\n unsigned __int64 v17; // [rsp+28h] [rbp-40h]\n\n v17 = __readfsqword(0x28u);\n v6 = (char *)malloc(0x3E8uLL);\n *(_WORD *)v6 = 91;\n v7 = v6;\n if ( a2 > 0 )\n {\n v14 = 0;\n v8 = a4 - a3;\n do\n {\n __strcat_chk(v7, &unk_2004, 1000LL);\n v9 = a3;\n if ( v8 > a3 )\n {\n do\n {\n while ( 1 )\n {\n __sprintf_chk(v16, 2LL, 10LL, &unk_2006, *(unsigned int *)(a1 + 4 * v9));\n v10 = strlen(v7);\n v11 = __stpcpy_chk(&v7[v10], v16, 1000LL);\n if ( v8 - 1 > (int)v9 )\n break;\n if ( v8 <= (int)++v9 )\n goto LABEL_8;\n }\n ++v9;\n __memcpy_chk(v11, &unk_2009, 3LL, &v7[-v11 + 1000]);\n }\n while ( v8 > (int)v9 );\n }\nLABEL_8:\n v12 = (char *)&v7[strlen(v7)];\n *(_WORD *)v12 = 41;\n if ( v14 < a2 - 1 )\n __memcpy_chk(v12 + 1, &unk_2009, 3LL, v7 - (v12 + 1) + 1000);\n ++v14;\n a1 += 20LL;\n }\n while ( a2 != v14 );\n }\n __strcat_chk(v7, \"]\", 1000LL);\n return v7;\n}", + "ida_strip_asm": "sub_1460:\nendbr64\npush r15\npush r14\nmov r14d, esi\npush r13\npush r12\nmov r12d, ecx\npush rbp\nmov rbp, rdi\nmov edi, 3E8h; size\npush rbx\nsub rsp, 38h\nmov [rsp+68h+var_64], esi\nmov [rsp+68h+var_60], edx\nmov rax, fs:28h\nmov [rsp+68h+var_40], rax\nxor eax, eax\ncall _malloc\nmov ecx, 5Bh ; '['\nmov [rax], cx\nmov rbx, rax\ntest r14d, r14d\njle loc_15BC\nmov eax, [rsp+68h+var_64]\nmov [rsp+68h+var_68], 0\nsub eax, 1\nmov [rsp+68h+var_5C], eax\nmov eax, [rsp+68h+var_60]\nsub r12d, eax\nlea r14d, [r12-1]\nnop\nloc_14D0:\nmov edx, 3E8h\nlea rsi, unk_2004\nmov rdi, rbx\ncall ___strcat_chk\nmovsxd r13, [rsp+68h+var_60]\nlea r15, [rsp+68h+var_4A]\ncmp r12d, r13d\njg short loc_1501\njmp short loc_1569\nloc_14F8:\nadd r13, 1\ncmp r12d, r13d\njle short loc_1569\nloc_1501:\nmov r8d, [rbp+r13*4+0]\nmov edx, 0Ah\nmov rdi, r15\nxor eax, eax\nmov esi, 2\nlea rcx, unk_2006\ncall ___sprintf_chk\nmov rdi, rbx; s\ncall _strlen\nmov edx, 3E8h\nmov rsi, r15\nlea rdi, [rbx+rax]\ncall ___stpcpy_chk\ncmp r14d, r13d\njle short loc_14F8\nmov rcx, rbx\nmov edx, 3\nmov rdi, rax\nadd r13, 1\nsub rcx, rax\nlea rsi, unk_2009\nadd rcx, 3E8h\ncall ___memcpy_chk\ncmp r12d, r13d\njg short loc_1501\nloc_1569:\nmov rdi, rbx; s\ncall _strlen\nmov edx, 29h ; ')'\nmov esi, [rsp+68h+var_5C]\nadd rax, rbx\nmov [rax], dx\ncmp [rsp+68h+var_68], esi\njge short loc_15A7\nlea rdi, [rax+1]\nmov rcx, rbx\nmov edx, 3\nsub rcx, rdi\nlea rsi, unk_2009\nadd rcx, 3E8h\ncall ___memcpy_chk\nloc_15A7:\nadd [rsp+68h+var_68], 1\nadd rbp, 14h\nmov eax, [rsp+68h+var_68]\ncmp [rsp+68h+var_64], eax\njnz loc_14D0\nloc_15BC:\nmov edx, 3E8h\nlea rsi, s2+13h; \"]\"\nmov rdi, rbx\ncall ___strcat_chk\nmov rax, [rsp+68h+var_40]\nsub rax, fs:28h\njnz short loc_15F2\nadd rsp, 38h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15F2:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_1460(__int64 a1, int a2, int a3, int a4)\n{\n char *v6; // rax\n const char *v7; // rbx\n int v8; // r12d\n __int64 v9; // r13\n size_t v10; // rax\n __int64 v11; // rax\n char *v12; // rax\n int v14; // [rsp+0h] [rbp-68h]\n _BYTE v16[10]; // [rsp+1Eh] [rbp-4Ah] BYREF\n unsigned __int64 v17; // [rsp+28h] [rbp-40h]\n\n v17 = __readfsqword(0x28u);\n v6 = (char *)malloc(0x3E8uLL);\n *(_WORD *)v6 = 91;\n v7 = v6;\n if ( a2 > 0 )\n {\n v14 = 0;\n v8 = a4 - a3;\n do\n {\n __strcat_chk(v7, &unk_2004, 1000LL);\n v9 = a3;\n if ( v8 > a3 )\n {\n do\n {\n while ( 1 )\n {\n __sprintf_chk(v16, 2LL, 10LL, &unk_2006, *(unsigned int *)(a1 + 4 * v9));\n v10 = strlen(v7);\n v11 = __stpcpy_chk(&v7[v10], v16, 1000LL);\n if ( v8 - 1 > (int)v9 )\n break;\n if ( v8 <= (int)++v9 )\n goto LABEL_8;\n }\n ++v9;\n __memcpy_chk(v11, &unk_2009, 3LL, &v7[-v11 + 1000]);\n }\n while ( v8 > (int)v9 );\n }\nLABEL_8:\n v12 = (char *)&v7[strlen(v7)];\n *(_WORD *)v12 = 41;\n if ( v14 < a2 - 1 )\n __memcpy_chk(v12 + 1, &unk_2009, 3LL, v7 - (v12 + 1) + 1000);\n ++v14;\n a1 += 20LL;\n }\n while ( a2 != v14 );\n }\n __strcat_chk(v7, \"]\", 1000LL);\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1460(long long a1, int a2, int a3, int a4) {\n char *v6;\n const char *v7;\n int v8;\n long long v9;\n unsigned int v10;\n long long v11;\n char *v12;\n int v14;\n uint8_t v16[10];\n unsigned long long v17;\n v17 = __readfsqword(40u);\n v6 = (char *)malloc(1000uLL);\n *(unsigned short *)v6 = 91;\n v7 = v6;\n if (a2 > 0) {\n v14 = 0;\n v8 = a4 - a3;\n do {\n __strcat_chk(v7, &unk_2004, 1000LL);\n v9 = a3;\n if (v8 > a3) {\n do {\n while (1) {\n __sprintf_chk(v16, 2LL, 10LL, &unk_2006,\n *(unsigned int *)(a1 + 4 * v9));\n v10 = strlen(v7);\n v11 = __stpcpy_chk(&v7[v10], v16, 1000LL);\n if (v8 - 1 > (int)v9) break;\n if (v8 <= (int)++v9) goto LABEL_8;\n }\n ++v9;\n __memcpy_chk(v11, &unk_2009, 3LL, &v7[-v11 + 1000]);\n } while (v8 > (int)v9);\n }\n LABEL_8:\n v12 = (char *)&v7[strlen(v7)];\n *(unsigned short *)v12 = 41;\n if (v14 < a2 - 1)\n __memcpy_chk(v12 + 1, &unk_2009, 3LL, v7 - (v12 + 1) + 1000);\n ++v14;\n a1 += 20LL;\n } while (a2 != v14);\n }\n __strcat_chk(v7, \"]\", 1000LL);\n return v7;\n}", + "ida_pseudo_norm": "const char *func0(long long a1, int a2, int a3, int a4) {\n char *v6;\n const char *v7;\n int v8;\n long long v9;\n unsigned int v10;\n long long v11;\n char *v12;\n int v14;\n uint8_t v16[10];\n unsigned long long v17;\n v17 = __readfsqword(40u);\n v6 = (char *)malloc(1000uLL);\n *(unsigned short *)v6 = 91;\n v7 = v6;\n if (a2 > 0) {\n v14 = 0;\n v8 = a4 - a3;\n do {\n __strcat_chk(v7, &unk_2004, 1000LL);\n v9 = a3;\n if (v8 > a3) {\n do {\n while (1) {\n __sprintf_chk(v16, 2LL, 10LL, &unk_2006,\n *(unsigned int *)(a1 + 4 * v9));\n v10 = strlen(v7);\n v11 = __stpcpy_chk(&v7[v10], v16, 1000LL);\n if (v8 - 1 > (int)v9) break;\n if (v8 <= (int)++v9) goto LABEL_8;\n }\n ++v9;\n __memcpy_chk(v11, &unk_2009, 3LL, &v7[-v11 + 1000]);\n } while (v8 > (int)v9);\n }\n LABEL_8:\n v12 = (char *)&v7[strlen(v7)];\n *(unsigned short *)v12 = 41;\n if (v14 < a2 - 1)\n __memcpy_chk(v12 + 1, &unk_2009, 3LL, v7 - (v12 + 1) + 1000);\n ++v14;\n a1 += 20LL;\n } while (a2 != v14);\n }\n __strcat_chk(v7, \"]\", 1000LL);\n return v7;\n}" + }, + { + "index": 444, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(int test_list[][5], int rows, int K, int N) {\n char* result = (char*)malloc(1000 * sizeof(char));\n strcpy(result, \"\");\n strcat(result, \"[\");\n for (int i = 0; i < rows; i++) {\n strcat(result, \"(\");\n for (int j = K; j < N - K; j++) {\n char num_str[10];\n sprintf(num_str, \"%d\", test_list[i][j]);\n strcat(result, num_str);\n if (j < N - K - 1) strcat(result, \", \");\n }\n strcat(result, \")\");\n if (i < rows - 1) strcat(result, \", \");\n }\n strcat(result, \"]\");\n return result;\n}", + "test": "int main() {\n\n int list1[4][5] = {{5, 3, 2, 1, 4}, {3, 4, 9, 2, 1}, {9, 1, 2, 3, 5}, {4, 8, 2, 1, 7}};\n\n int list2[4][5] = {{7, 8, 4, 9}, {11, 8, 12, 4}, {4, 1, 7, 8}, {3, 6, 9, 7}};\n\n\n\n char* res1 = func0(list1, 4, 2, 5);\n\n char* res2 = func0(list1, 4, 1, 5);\n\n char* res3 = func0(list2, 4, 1, 4);\n\n\n\n assert(strcmp(res1, \"[(2), (9), (2), (2)]\") == 0);\n\n assert(strcmp(res2, \"[(3, 2, 1), (4, 9, 2), (1, 2, 3), (8, 2, 1)]\") == 0);\n\n assert(strcmp(res3, \"[(8, 4), (8, 12), (1, 7), (6, 9)]\") == 0);\n\n \n\n free(res1);\n\n free(res2);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\nmov %ecx,%r14d\npush %r13\npush %r12\npush %rbp\nmov %rdi,%rbp\nmov $0x3e8,%edi\npush %rbx\nmov %esi,%ebx\nsub $0x48,%rsp\nmov %edx,0xc(%rsp)\nmov %esi,0x14(%rsp)\nmov %fs:0x28,%rax\nmov %rax,0x38(%rsp)\nxor %eax,%eax\ncallq 1120 \nmov $0x5b,%edx\nmov %dx,(%rax)\nmov %rax,%r12\ntest %ebx,%ebx\njle 17e3 \nmov 0xc(%rsp),%esi\nmov 0x14(%rsp),%ebx\nmov %r14d,%eax\nmovl $0x0,0x4(%rsp)\nsub %esi,%eax\nsub $0x1,%ebx\nmov %eax,0x8(%rsp)\nmov %ebx,0x10(%rsp)\nlea -0x1(%rax),%ebx\nsub %esi,%eax\nsub $0x2,%eax\nmov %ebx,0x18(%rsp)\nlea 0x2e(%rsp),%rbx\nmov %eax,0x1c(%rsp)\nnopl 0x0(%rax)\nlea 0xb45(%rip),%rsi\nmov $0x3e8,%edx\nmov %r12,%rdi\ncallq 10c0 <__strcat_chk@plt>\nmov 0x8(%rsp),%esi\ncmp %esi,0xc(%rsp)\njge 1760 \nmov 0xc(%rsp),%esi\ncmp %esi,0x18(%rsp)\njle 1820 \nmov 0x1c(%rsp),%eax\nlea 0x1(%rsi),%r9d\nmovslq %esi,%rdx\nlea 0xb0c(%rip),%r14\nmovslq %r9d,%r13\nlea 0x2(%rax,%rdx,1),%rax\nmov %r13,%r15\nmov %rax,%r13\nnopl 0x0(%rax,%rax,1)\nmov -0x4(%rbp,%r15,4),%r8d\nmov %rbx,%rdi\nmov %r14,%rcx\nmov $0xa,%edx\nmov $0x1,%esi\nxor %eax,%eax\ncallq 1130 <__sprintf_chk@plt>\nmov %r12,%rdi\nmov (%rdi),%edx\nadd $0x4,%rdi\nlea -0x1010101(%rdx),%eax\nnot %edx\nand %edx,%eax\nand $0x80808080,%eax\nje 152f \nmov %eax,%edx\nshr $0x10,%edx\ntest $0x8080,%eax\ncmove %edx,%eax\nlea 0x2(%rdi),%rdx\ncmove %rdx,%rdi\nmov $0x3e8,%edx\nmov %eax,%esi\nadd %al,%sil\nmov %rbx,%rsi\nsbb $0x3,%rdi\ncallq 1110 <__stpcpy_chk@plt>\nmov %r12,%rcx\nmov $0x3,%edx\nlea 0xa89(%rip),%rsi\nsub %rax,%rcx\nmov %rax,%rdi\nadd $0x3e8,%rcx\ncallq 1100 <__memcpy_chk@plt>\nmov %r15d,%eax\nadd $0x1,%r15\ncmp %r13,%r15\njne 1510 \nmov %eax,%r15d\ncmp %eax,0x8(%rsp)\njle 1760 \nmovslq %r15d,%rax\nmov $0xa,%edx\nmov $0x1,%esi\nmov %rbx,%rdi\nlea 0x0(%rbp,%rax,4),%r13\nlea 0xa3b(%rip),%rcx\nxor %eax,%eax\nmov 0x0(%r13),%r8d\ncallq 1130 <__sprintf_chk@plt>\nmov $0x3e8,%edx\nmov %rbx,%rsi\nmov %r12,%rdi\ncallq 10c0 <__strcat_chk@plt>\nmov 0x8(%rsp),%r14d\nlea 0x1(%r15),%eax\ncmp %eax,%r14d\njle 1760 \nmov 0x4(%r13),%r8d\nlea 0xa03(%rip),%rcx\nmov %rbx,%rdi\nxor %eax,%eax\nmov $0xa,%edx\nmov $0x1,%esi\ncallq 1130 <__sprintf_chk@plt>\nmov $0x3e8,%edx\nmov %rbx,%rsi\nmov %r12,%rdi\ncallq 10c0 <__strcat_chk@plt>\nlea 0x2(%r15),%eax\ncmp %eax,%r14d\njle 1760 \nmov 0x8(%r13),%r8d\nlea 0x9c7(%rip),%rcx\nmov %rbx,%rdi\nxor %eax,%eax\nmov $0xa,%edx\nmov $0x1,%esi\ncallq 1130 <__sprintf_chk@plt>\nmov $0x3e8,%edx\nmov %rbx,%rsi\nmov %r12,%rdi\ncallq 10c0 <__strcat_chk@plt>\nlea 0x3(%r15),%eax\ncmp %eax,%r14d\njle 1760 \nmov 0xc(%r13),%r8d\nlea 0x98b(%rip),%rcx\nmov %rbx,%rdi\nxor %eax,%eax\nmov $0xa,%edx\nmov $0x1,%esi\ncallq 1130 <__sprintf_chk@plt>\nmov $0x3e8,%edx\nmov %rbx,%rsi\nmov %r12,%rdi\ncallq 10c0 <__strcat_chk@plt>\nlea 0x4(%r15),%eax\ncmp %eax,%r14d\njle 1760 \nmov 0x10(%r13),%r8d\nlea 0x94f(%rip),%rcx\nmov %rbx,%rdi\nxor %eax,%eax\nmov $0xa,%edx\nmov $0x1,%esi\ncallq 1130 <__sprintf_chk@plt>\nmov $0x3e8,%edx\nmov %rbx,%rsi\nmov %r12,%rdi\ncallq 10c0 <__strcat_chk@plt>\nlea 0x5(%r15),%eax\ncmp %eax,%r14d\njle 1760 \nmov 0x14(%r13),%r8d\nlea 0x917(%rip),%rcx\nmov %rbx,%rdi\nxor %eax,%eax\nmov $0xa,%edx\nmov $0x1,%esi\ncallq 1130 <__sprintf_chk@plt>\nmov $0x3e8,%edx\nmov %rbx,%rsi\nmov %r12,%rdi\ncallq 10c0 <__strcat_chk@plt>\nlea 0x6(%r15),%r10d\ncmp %r10d,%r14d\njle 1760 \nmovslq %r10d,%r13\nlea 0x8e0(%rip),%r14\nmov 0x0(%rbp,%r13,4),%r8d\nmov %r14,%rcx\nmov $0xa,%edx\nmov %rbx,%rdi\nmov $0x1,%esi\nxor %eax,%eax\nadd $0x1,%r13\ncallq 1130 <__sprintf_chk@plt>\nmov $0x3e8,%edx\nmov %rbx,%rsi\nmov %r12,%rdi\ncallq 10c0 <__strcat_chk@plt>\ncmp %r13d,0x8(%rsp)\njg 1726 \nnopl (%rax)\nmov %r12,%rdi\nmov (%rdi),%edx\nadd $0x4,%rdi\nlea -0x1010101(%rdx),%eax\nnot %edx\nand %edx,%eax\nand $0x80808080,%eax\nje 1763 \nmov %eax,%edx\nshr $0x10,%edx\ntest $0x8080,%eax\ncmove %edx,%eax\nlea 0x2(%rdi),%rdx\ncmove %rdx,%rdi\nmov %eax,%esi\nadd %al,%sil\nmov $0x29,%eax\nmov 0x10(%rsp),%esi\nsbb $0x3,%rdi\nmov %ax,(%rdi)\nadd $0x1,%rdi\ncmp %esi,0x4(%rsp)\njge 17cc \nmov %r12,%rcx\nmov $0x3,%edx\nlea 0x84c(%rip),%rsi\nsub %rdi,%rcx\nadd $0x3e8,%rcx\ncallq 1100 <__memcpy_chk@plt>\naddl $0x1,0x4(%rsp)\nadd $0x14,%rbp\nmov 0x4(%rsp),%eax\ncmp %eax,0x14(%rsp)\njne 14b8 \nmov $0x3e8,%edx\nlea 0x830(%rip),%rsi\nmov %r12,%rdi\ncallq 10c0 <__strcat_chk@plt>\nmov 0x38(%rsp),%rax\nxor %fs:0x28,%rax\njne 1828 \nadd $0x48,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\nmov %esi,%r15d\njmpq 15af \ncallq 10e0 <__stack_chk_fail@plt>\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\nmov r13d, ecx\npush r12\nmov r12, rdi\nmov edi, 3E8h; size\npush rbp\npush rbx\nmov ebx, esi\nsub rsp, 48h\nmov [rsp+78h+var_6C], esi\nmov [rsp+78h+var_70], edx\nmov rax, fs:28h\nmov [rsp+78h+var_40], rax\nxor eax, eax\ncall _malloc\nmov ecx, 5Bh ; '['\nmov [rax], cx\nmov r14, rax\ntest ebx, ebx\njle loc_1706\nmov eax, [rsp+78h+var_70]\nmov edx, [rsp+78h+var_6C]\nmov [rsp+78h+var_74], 0\nsub r13d, eax\nlea ebx, [rdx-1]\nadd eax, 1\nmov [rsp+78h+var_68], ebx\ncdqe\nlea ebx, [r13-1]\nmov [rsp+78h+var_64], ebx\nmov [rsp+78h+var_60], rax\nnop dword ptr [rax+rax+00h]\nloc_14E0:\nmov edx, 3E8h\nlea rsi, unk_2004\nmov rdi, r14\ncall ___strcat_chk\nmov eax, [rsp+78h+var_70]\ncmp r13d, eax\njle loc_16B0\nmov ebp, eax\nlea rbx, [rsp+78h+var_4A]\ncmp [rsp+78h+var_64], eax\njg loc_1740\nloc_1512:\nmovsxd rax, ebp\nmov edx, 0Ah\nmov esi, 2\nmov rdi, rbx\nlea r15, [r12+rax*4]\nlea rcx, unk_2006\nxor eax, eax\nmov r8d, [r15]\ncall ___sprintf_chk\nmov edx, 3E8h\nmov rsi, rbx\nmov rdi, r14\ncall ___strcat_chk\nlea eax, [rbp+1]\ncmp r13d, eax\njle loc_16B0\nmov r8d, [r15+4]\nlea rcx, unk_2006\nmov rdi, rbx\nxor eax, eax\nmov edx, 0Ah\nmov esi, 2\ncall ___sprintf_chk\nmov edx, 3E8h\nmov rsi, rbx\nmov rdi, r14\ncall ___strcat_chk\nlea eax, [rbp+2]\ncmp r13d, eax\njle loc_16B0\nmov r8d, [r15+8]\nlea rcx, unk_2006\nmov rdi, rbx\nxor eax, eax\nmov edx, 0Ah\nmov esi, 2\ncall ___sprintf_chk\nmov edx, 3E8h\nmov rsi, rbx\nmov rdi, r14\ncall ___strcat_chk\nlea eax, [rbp+3]\ncmp r13d, eax\njle loc_16B0\nmov r8d, [r15+0Ch]\nlea rcx, unk_2006\nmov rdi, rbx\nxor eax, eax\nmov edx, 0Ah\nmov esi, 2\ncall ___sprintf_chk\nmov edx, 3E8h\nmov rsi, rbx\nmov rdi, r14\ncall ___strcat_chk\nlea eax, [rbp+4]\ncmp r13d, eax\njle loc_16B0\nmov r8d, [r15+10h]\nlea rcx, unk_2006\nmov rdi, rbx\nxor eax, eax\nmov edx, 0Ah\nmov esi, 2\ncall ___sprintf_chk\nmov edx, 3E8h\nmov rsi, rbx\nmov rdi, r14\ncall ___strcat_chk\nlea eax, [rbp+5]\ncmp r13d, eax\njle short loc_16B0\nmov r8d, [r15+14h]\nlea rcx, unk_2006\nmov rdi, rbx\nxor eax, eax\nmov edx, 0Ah\nmov esi, 2\nadd ebp, 6\ncall ___sprintf_chk\nmov edx, 3E8h\nmov rsi, rbx\nmov rdi, r14\ncall ___strcat_chk\ncmp r13d, ebp\njle short loc_16B0\nmovsxd rbp, ebp\nloc_1675:\nmov r8d, [r12+rbp*4]\nlea rcx, unk_2006\nmov rdi, rbx\nxor eax, eax\nmov edx, 0Ah\nmov esi, 2\nadd rbp, 1\ncall ___sprintf_chk\nmov edx, 3E8h\nmov rsi, rbx\nmov rdi, r14\ncall ___strcat_chk\ncmp r13d, ebp\njg short loc_1675\nnop dword ptr [rax]\nloc_16B0:\nmov rdi, r14; s\ncall _strlen\nmov edx, 29h ; ')'\nmov esi, [rsp+78h+var_68]\nadd rax, r14\nmov [rax], dx\ncmp [rsp+78h+var_74], esi\njge short loc_16EF\nlea rdi, [rax+1]\nmov rcx, r14\nmov edx, 3\nsub rcx, rdi\nlea rsi, unk_2009\nadd rcx, 3E8h\ncall ___memcpy_chk\nloc_16EF:\nadd [rsp+78h+var_74], 1\nadd r12, 14h\nmov eax, [rsp+78h+var_74]\ncmp [rsp+78h+var_6C], eax\njnz loc_14E0\nloc_1706:\nmov edx, 3E8h\nlea rsi, s2+13h; \"]\"\nmov rdi, r14\ncall ___strcat_chk\nmov rax, [rsp+78h+var_40]\nsub rax, fs:28h\njnz loc_17D5\nadd rsp, 48h\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1740:\nmov eax, r13d\nmov r15, [rsp+78h+var_60]\nsub eax, ebp\nlea edx, [rax-2]\nmovsxd rax, ebp\nlea rbp, [rdx+rax+2]\nloc_1755:\nmov r8d, [r12+r15*4-4]\nmov edx, 0Ah\nmov rdi, rbx\nxor eax, eax\nlea rcx, unk_2006\nmov esi, 2\ncall ___sprintf_chk\nmov rdi, r14; s\ncall _strlen\nmov edx, 3E8h\nmov rsi, rbx\nlea rdi, [r14+rax]\ncall ___stpcpy_chk\nmov rcx, r14\nmov edx, 3\nlea rsi, unk_2009\nsub rcx, rax\nmov rdi, rax\nadd rcx, 3E8h\ncall ___memcpy_chk\nlea rax, [r15+1]\ncmp rax, rbp\njnz short loc_17D0\nmov ebp, r15d\ncmp r13d, r15d\njg loc_1512\njmp loc_16B0\nloc_17D0:\nmov r15, rax\njmp short loc_1755\nloc_17D5:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(__int64 a1, int a2, int a3, int a4)\n{\n char *v6; // rax\n const char *v7; // r14\n int v8; // r13d\n int v9; // ebp\n unsigned int *v10; // r15\n __int64 v11; // rbp\n __int64 v12; // r8\n char *v13; // rax\n __int64 i; // r15\n size_t v16; // rax\n __int64 v17; // rax\n int v18; // [rsp+4h] [rbp-74h]\n _BYTE v20[10]; // [rsp+2Eh] [rbp-4Ah] BYREF\n unsigned __int64 v21; // [rsp+38h] [rbp-40h]\n\n v21 = __readfsqword(0x28u);\n v6 = (char *)malloc(0x3E8uLL);\n *(_WORD *)v6 = 91;\n v7 = v6;\n if ( a2 > 0 )\n {\n v18 = 0;\n v8 = a4 - a3;\n do\n {\n __strcat_chk(v7, &unk_2004, 1000LL);\n if ( v8 > a3 )\n {\n v9 = a3;\n if ( v8 - 1 <= a3 )\n goto LABEL_24;\n for ( i = a3 + 1; ; ++i )\n {\n __sprintf_chk(v20, 2LL, 10LL, &unk_2006, *(unsigned int *)(a1 + 4 * i - 4));\n v16 = strlen(v7);\n v17 = __stpcpy_chk(&v7[v16], v20, 1000LL);\n __memcpy_chk(v17, &unk_2009, 3LL, &v7[-v17 + 1000]);\n if ( i + 1 == (unsigned int)(v8 - a3 - 2) + (__int64)a3 + 2 )\n break;\n }\n v9 = i;\n if ( v8 > (int)i )\n {\nLABEL_24:\n v10 = (unsigned int *)(a1 + 4LL * v9);\n __sprintf_chk(v20, 2LL, 10LL, &unk_2006, *v10);\n __strcat_chk(v7, v20, 1000LL);\n if ( v8 > v9 + 1 )\n {\n __sprintf_chk(v20, 2LL, 10LL, &unk_2006, v10[1]);\n __strcat_chk(v7, v20, 1000LL);\n if ( v8 > v9 + 2 )\n {\n __sprintf_chk(v20, 2LL, 10LL, &unk_2006, v10[2]);\n __strcat_chk(v7, v20, 1000LL);\n if ( v8 > v9 + 3 )\n {\n __sprintf_chk(v20, 2LL, 10LL, &unk_2006, v10[3]);\n __strcat_chk(v7, v20, 1000LL);\n if ( v8 > v9 + 4 )\n {\n __sprintf_chk(v20, 2LL, 10LL, &unk_2006, v10[4]);\n __strcat_chk(v7, v20, 1000LL);\n if ( v8 > v9 + 5 )\n {\n LODWORD(v11) = v9 + 6;\n __sprintf_chk(v20, 2LL, 10LL, &unk_2006, v10[5]);\n __strcat_chk(v7, v20, 1000LL);\n if ( v8 > (int)v11 )\n {\n v11 = (int)v11;\n do\n {\n v12 = *(unsigned int *)(a1 + 4 * v11++);\n __sprintf_chk(v20, 2LL, 10LL, &unk_2006, v12);\n __strcat_chk(v7, v20, 1000LL);\n }\n while ( v8 > (int)v11 );\n }\n }\n }\n }\n }\n }\n }\n }\n v13 = (char *)&v7[strlen(v7)];\n *(_WORD *)v13 = 41;\n if ( v18 < a2 - 1 )\n __memcpy_chk(v13 + 1, &unk_2009, 3LL, v7 - (v13 + 1) + 1000);\n ++v18;\n a1 += 20LL;\n }\n while ( a2 != v18 );\n }\n __strcat_chk(v7, \"]\", 1000LL);\n return v7;\n}", + "ida_strip_asm": "sub_1460:\nendbr64\npush r15\npush r14\npush r13\nmov r13d, ecx\npush r12\nmov r12, rdi\nmov edi, 3E8h; size\npush rbp\npush rbx\nmov ebx, esi\nsub rsp, 48h\nmov [rsp+78h+var_6C], esi\nmov [rsp+78h+var_70], edx\nmov rax, fs:28h\nmov [rsp+78h+var_40], rax\nxor eax, eax\ncall _malloc\nmov ecx, 5Bh ; '['\nmov [rax], cx\nmov r14, rax\ntest ebx, ebx\njle loc_1706\nmov eax, [rsp+78h+var_70]\nmov edx, [rsp+78h+var_6C]\nmov [rsp+78h+var_74], 0\nsub r13d, eax\nlea ebx, [rdx-1]\nadd eax, 1\nmov [rsp+78h+var_68], ebx\ncdqe\nlea ebx, [r13-1]\nmov [rsp+78h+var_64], ebx\nmov [rsp+78h+var_60], rax\nnop dword ptr [rax+rax+00h]\nloc_14E0:\nmov edx, 3E8h\nlea rsi, unk_2004\nmov rdi, r14\ncall ___strcat_chk\nmov eax, [rsp+78h+var_70]\ncmp r13d, eax\njle loc_16B0\nmov ebp, eax\nlea rbx, [rsp+78h+var_4A]\ncmp [rsp+78h+var_64], eax\njg loc_1740\nloc_1512:\nmovsxd rax, ebp\nmov edx, 0Ah\nmov esi, 2\nmov rdi, rbx\nlea r15, [r12+rax*4]\nlea rcx, unk_2006\nxor eax, eax\nmov r8d, [r15]\ncall ___sprintf_chk\nmov edx, 3E8h\nmov rsi, rbx\nmov rdi, r14\ncall ___strcat_chk\nlea eax, [rbp+1]\ncmp r13d, eax\njle loc_16B0\nmov r8d, [r15+4]\nlea rcx, unk_2006\nmov rdi, rbx\nxor eax, eax\nmov edx, 0Ah\nmov esi, 2\ncall ___sprintf_chk\nmov edx, 3E8h\nmov rsi, rbx\nmov rdi, r14\ncall ___strcat_chk\nlea eax, [rbp+2]\ncmp r13d, eax\njle loc_16B0\nmov r8d, [r15+8]\nlea rcx, unk_2006\nmov rdi, rbx\nxor eax, eax\nmov edx, 0Ah\nmov esi, 2\ncall ___sprintf_chk\nmov edx, 3E8h\nmov rsi, rbx\nmov rdi, r14\ncall ___strcat_chk\nlea eax, [rbp+3]\ncmp r13d, eax\njle loc_16B0\nmov r8d, [r15+0Ch]\nlea rcx, unk_2006\nmov rdi, rbx\nxor eax, eax\nmov edx, 0Ah\nmov esi, 2\ncall ___sprintf_chk\nmov edx, 3E8h\nmov rsi, rbx\nmov rdi, r14\ncall ___strcat_chk\nlea eax, [rbp+4]\ncmp r13d, eax\njle loc_16B0\nmov r8d, [r15+10h]\nlea rcx, unk_2006\nmov rdi, rbx\nxor eax, eax\nmov edx, 0Ah\nmov esi, 2\ncall ___sprintf_chk\nmov edx, 3E8h\nmov rsi, rbx\nmov rdi, r14\ncall ___strcat_chk\nlea eax, [rbp+5]\ncmp r13d, eax\njle short loc_16B0\nmov r8d, [r15+14h]\nlea rcx, unk_2006\nmov rdi, rbx\nxor eax, eax\nmov edx, 0Ah\nmov esi, 2\nadd ebp, 6\ncall ___sprintf_chk\nmov edx, 3E8h\nmov rsi, rbx\nmov rdi, r14\ncall ___strcat_chk\ncmp r13d, ebp\njle short loc_16B0\nmovsxd rbp, ebp\nloc_1675:\nmov r8d, [r12+rbp*4]\nlea rcx, unk_2006\nmov rdi, rbx\nxor eax, eax\nmov edx, 0Ah\nmov esi, 2\nadd rbp, 1\ncall ___sprintf_chk\nmov edx, 3E8h\nmov rsi, rbx\nmov rdi, r14\ncall ___strcat_chk\ncmp r13d, ebp\njg short loc_1675\nnop dword ptr [rax]\nloc_16B0:\nmov rdi, r14; s\ncall _strlen\nmov edx, 29h ; ')'\nmov esi, [rsp+78h+var_68]\nadd rax, r14\nmov [rax], dx\ncmp [rsp+78h+var_74], esi\njge short loc_16EF\nlea rdi, [rax+1]\nmov rcx, r14\nmov edx, 3\nsub rcx, rdi\nlea rsi, unk_2009\nadd rcx, 3E8h\ncall ___memcpy_chk\nloc_16EF:\nadd [rsp+78h+var_74], 1\nadd r12, 14h\nmov eax, [rsp+78h+var_74]\ncmp [rsp+78h+var_6C], eax\njnz loc_14E0\nloc_1706:\nmov edx, 3E8h\nlea rsi, s2+13h; \"]\"\nmov rdi, r14\ncall ___strcat_chk\nmov rax, [rsp+78h+var_40]\nsub rax, fs:28h\njnz loc_17D5\nadd rsp, 48h\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1740:\nmov eax, r13d\nmov r15, [rsp+78h+var_60]\nsub eax, ebp\nlea edx, [rax-2]\nmovsxd rax, ebp\nlea rbp, [rdx+rax+2]\nloc_1755:\nmov r8d, [r12+r15*4-4]\nmov edx, 0Ah\nmov rdi, rbx\nxor eax, eax\nlea rcx, unk_2006\nmov esi, 2\ncall ___sprintf_chk\nmov rdi, r14; s\ncall _strlen\nmov edx, 3E8h\nmov rsi, rbx\nlea rdi, [r14+rax]\ncall ___stpcpy_chk\nmov rcx, r14\nmov edx, 3\nlea rsi, unk_2009\nsub rcx, rax\nmov rdi, rax\nadd rcx, 3E8h\ncall ___memcpy_chk\nlea rax, [r15+1]\ncmp rax, rbp\njnz short loc_17D0\nmov ebp, r15d\ncmp r13d, r15d\njg loc_1512\njmp loc_16B0\nloc_17D0:\nmov r15, rax\njmp short loc_1755\nloc_17D5:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_1460(__int64 a1, int a2, int a3, int a4)\n{\n char *v6; // rax\n const char *v7; // r14\n int v8; // r13d\n int v9; // ebp\n unsigned int *v10; // r15\n __int64 v11; // rbp\n __int64 v12; // r8\n char *v13; // rax\n __int64 i; // r15\n size_t v16; // rax\n __int64 v17; // rax\n int v18; // [rsp+4h] [rbp-74h]\n _BYTE v20[10]; // [rsp+2Eh] [rbp-4Ah] BYREF\n unsigned __int64 v21; // [rsp+38h] [rbp-40h]\n\n v21 = __readfsqword(0x28u);\n v6 = (char *)malloc(0x3E8uLL);\n *(_WORD *)v6 = 91;\n v7 = v6;\n if ( a2 > 0 )\n {\n v18 = 0;\n v8 = a4 - a3;\n do\n {\n __strcat_chk(v7, &unk_2004, 1000LL);\n if ( v8 > a3 )\n {\n v9 = a3;\n if ( v8 - 1 <= a3 )\n goto LABEL_24;\n for ( i = a3 + 1; ; ++i )\n {\n __sprintf_chk(v20, 2LL, 10LL, &unk_2006, *(unsigned int *)(a1 + 4 * i - 4));\n v16 = strlen(v7);\n v17 = __stpcpy_chk(&v7[v16], v20, 1000LL);\n __memcpy_chk(v17, &unk_2009, 3LL, &v7[-v17 + 1000]);\n if ( i + 1 == (unsigned int)(v8 - a3 - 2) + (__int64)a3 + 2 )\n break;\n }\n v9 = i;\n if ( v8 > (int)i )\n {\nLABEL_24:\n v10 = (unsigned int *)(a1 + 4LL * v9);\n __sprintf_chk(v20, 2LL, 10LL, &unk_2006, *v10);\n __strcat_chk(v7, v20, 1000LL);\n if ( v8 > v9 + 1 )\n {\n __sprintf_chk(v20, 2LL, 10LL, &unk_2006, v10[1]);\n __strcat_chk(v7, v20, 1000LL);\n if ( v8 > v9 + 2 )\n {\n __sprintf_chk(v20, 2LL, 10LL, &unk_2006, v10[2]);\n __strcat_chk(v7, v20, 1000LL);\n if ( v8 > v9 + 3 )\n {\n __sprintf_chk(v20, 2LL, 10LL, &unk_2006, v10[3]);\n __strcat_chk(v7, v20, 1000LL);\n if ( v8 > v9 + 4 )\n {\n __sprintf_chk(v20, 2LL, 10LL, &unk_2006, v10[4]);\n __strcat_chk(v7, v20, 1000LL);\n if ( v8 > v9 + 5 )\n {\n LODWORD(v11) = v9 + 6;\n __sprintf_chk(v20, 2LL, 10LL, &unk_2006, v10[5]);\n __strcat_chk(v7, v20, 1000LL);\n if ( v8 > (int)v11 )\n {\n v11 = (int)v11;\n do\n {\n v12 = *(unsigned int *)(a1 + 4 * v11++);\n __sprintf_chk(v20, 2LL, 10LL, &unk_2006, v12);\n __strcat_chk(v7, v20, 1000LL);\n }\n while ( v8 > (int)v11 );\n }\n }\n }\n }\n }\n }\n }\n }\n v13 = (char *)&v7[strlen(v7)];\n *(_WORD *)v13 = 41;\n if ( v18 < a2 - 1 )\n __memcpy_chk(v13 + 1, &unk_2009, 3LL, v7 - (v13 + 1) + 1000);\n ++v18;\n a1 += 20LL;\n }\n while ( a2 != v18 );\n }\n __strcat_chk(v7, \"]\", 1000LL);\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1460(long long a1, int a2, int a3, int a4) {\n char *v6;\n const char *v7;\n int v8;\n int v9;\n unsigned int *v10;\n long long v11;\n long long v12;\n char *v13;\n long long i;\n unsigned int v16;\n long long v17;\n int v18;\n uint8_t v20[10];\n unsigned long long v21;\n v21 = __readfsqword(40u);\n v6 = (char *)malloc(1000uLL);\n *(unsigned short *)v6 = 91;\n v7 = v6;\n if (a2 > 0) {\n v18 = 0;\n v8 = a4 - a3;\n do {\n __strcat_chk(v7, &unk_2004, 1000LL);\n if (v8 > a3) {\n v9 = a3;\n if (v8 - 1 <= a3) goto LABEL_24;\n for (i = a3 + 1;; ++i) {\n __sprintf_chk(v20, 2LL, 10LL, &unk_2006,\n *(unsigned int *)(a1 + 4 * i - 4));\n v16 = strlen(v7);\n v17 = __stpcpy_chk(&v7[v16], v20, 1000LL);\n __memcpy_chk(v17, &unk_2009, 3LL, &v7[-v17 + 1000]);\n if (i + 1 == (unsigned int)(v8 - a3 - 2) + (long long)a3 + 2) break;\n }\n v9 = i;\n if (v8 > (int)i) {\n LABEL_24:\n v10 = (unsigned int *)(a1 + 4LL * v9);\n __sprintf_chk(v20, 2LL, 10LL, &unk_2006, *v10);\n __strcat_chk(v7, v20, 1000LL);\n if (v8 > v9 + 1) {\n __sprintf_chk(v20, 2LL, 10LL, &unk_2006, v10[1]);\n __strcat_chk(v7, v20, 1000LL);\n if (v8 > v9 + 2) {\n __sprintf_chk(v20, 2LL, 10LL, &unk_2006, v10[2]);\n __strcat_chk(v7, v20, 1000LL);\n if (v8 > v9 + 3) {\n __sprintf_chk(v20, 2LL, 10LL, &unk_2006, v10[3]);\n __strcat_chk(v7, v20, 1000LL);\n if (v8 > v9 + 4) {\n __sprintf_chk(v20, 2LL, 10LL, &unk_2006, v10[4]);\n __strcat_chk(v7, v20, 1000LL);\n if (v8 > v9 + 5) {\n LODWORD(v11) = v9 + 6;\n __sprintf_chk(v20, 2LL, 10LL, &unk_2006, v10[5]);\n __strcat_chk(v7, v20, 1000LL);\n if (v8 > (int)v11) {\n v11 = (int)v11;\n do {\n v12 = *(unsigned int *)(a1 + 4 * v11++);\n __sprintf_chk(v20, 2LL, 10LL, &unk_2006, v12);\n __strcat_chk(v7, v20, 1000LL);\n } while (v8 > (int)v11);\n }\n }\n }\n }\n }\n }\n }\n }\n v13 = (char *)&v7[strlen(v7)];\n *(unsigned short *)v13 = 41;\n if (v18 < a2 - 1)\n __memcpy_chk(v13 + 1, &unk_2009, 3LL, v7 - (v13 + 1) + 1000);\n ++v18;\n a1 += 20LL;\n } while (a2 != v18);\n }\n __strcat_chk(v7, \"]\", 1000LL);\n return v7;\n}", + "ida_pseudo_norm": "const char *func0(long long a1, int a2, int a3, int a4) {\n char *v6;\n const char *v7;\n int v8;\n int v9;\n unsigned int *v10;\n long long v11;\n long long v12;\n char *v13;\n long long i;\n unsigned int v16;\n long long v17;\n int v18;\n uint8_t v20[10];\n unsigned long long v21;\n v21 = __readfsqword(40u);\n v6 = (char *)malloc(1000uLL);\n *(unsigned short *)v6 = 91;\n v7 = v6;\n if (a2 > 0) {\n v18 = 0;\n v8 = a4 - a3;\n do {\n __strcat_chk(v7, &unk_2004, 1000LL);\n if (v8 > a3) {\n v9 = a3;\n if (v8 - 1 <= a3) goto LABEL_24;\n for (i = a3 + 1;; ++i) {\n __sprintf_chk(v20, 2LL, 10LL, &unk_2006,\n *(unsigned int *)(a1 + 4 * i - 4));\n v16 = strlen(v7);\n v17 = __stpcpy_chk(&v7[v16], v20, 1000LL);\n __memcpy_chk(v17, &unk_2009, 3LL, &v7[-v17 + 1000]);\n if (i + 1 == (unsigned int)(v8 - a3 - 2) + (long long)a3 + 2) break;\n }\n v9 = i;\n if (v8 > (int)i) {\n LABEL_24:\n v10 = (unsigned int *)(a1 + 4LL * v9);\n __sprintf_chk(v20, 2LL, 10LL, &unk_2006, *v10);\n __strcat_chk(v7, v20, 1000LL);\n if (v8 > v9 + 1) {\n __sprintf_chk(v20, 2LL, 10LL, &unk_2006, v10[1]);\n __strcat_chk(v7, v20, 1000LL);\n if (v8 > v9 + 2) {\n __sprintf_chk(v20, 2LL, 10LL, &unk_2006, v10[2]);\n __strcat_chk(v7, v20, 1000LL);\n if (v8 > v9 + 3) {\n __sprintf_chk(v20, 2LL, 10LL, &unk_2006, v10[3]);\n __strcat_chk(v7, v20, 1000LL);\n if (v8 > v9 + 4) {\n __sprintf_chk(v20, 2LL, 10LL, &unk_2006, v10[4]);\n __strcat_chk(v7, v20, 1000LL);\n if (v8 > v9 + 5) {\n LODWORD(v11) = v9 + 6;\n __sprintf_chk(v20, 2LL, 10LL, &unk_2006, v10[5]);\n __strcat_chk(v7, v20, 1000LL);\n if (v8 > (int)v11) {\n v11 = (int)v11;\n do {\n v12 = *(unsigned int *)(a1 + 4 * v11++);\n __sprintf_chk(v20, 2LL, 10LL, &unk_2006, v12);\n __strcat_chk(v7, v20, 1000LL);\n } while (v8 > (int)v11);\n }\n }\n }\n }\n }\n }\n }\n }\n v13 = (char *)&v7[strlen(v7)];\n *(unsigned short *)v13 = 41;\n if (v18 < a2 - 1)\n __memcpy_chk(v13 + 1, &unk_2009, 3LL, v7 - (v13 + 1) + 1000);\n ++v18;\n a1 += 20LL;\n } while (a2 != v18);\n }\n __strcat_chk(v7, \"]\", 1000LL);\n return v7;\n}" + }, + { + "index": 445, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "void func0(int test_tup1[][2], int test_tup2[][2], int res[][2],\n int num_tuples) {\n for (int i = 0; i < num_tuples; i++) {\n for (int j = 0; j < 2; j++) {\n res[i][j] = test_tup1[i][j] * test_tup2[i][j];\n }\n }\n}", + "test": "int main() {\n\n int res[4][2];\n\n \n\n int test_tup1[4][2] = {{1, 3}, {4, 5}, {2, 9}, {1, 10}};\n\n int test_tup2[4][2] = {{6, 7}, {3, 9}, {1, 1}, {7, 3}};\n\n int expected[4][2] = {{6, 21}, {12, 45}, {2, 9}, {7, 30}};\n\n func0(test_tup1, test_tup2, res, 4);\n\n for (int i = 0; i < 4; i++) {\n\n for (int j = 0; j < 2; j++) {\n\n assert(res[i][j] == expected[i][j]);\n\n }\n\n }\n\n \n\n int test_tup3[4][2] = {{2, 4}, {5, 6}, {3, 10}, {2, 11}};\n\n int test_tup4[4][2] = {{7, 8}, {4, 10}, {2, 2}, {8, 4}};\n\n int expected2[4][2] = {{14, 32}, {20, 60}, {6, 20}, {16, 44}};\n\n func0(test_tup3, test_tup4, res, 4);\n\n for (int i = 0; i < 4; i++) {\n\n for (int j = 0; j < 2; j++) {\n\n assert(res[i][j] == expected2[i][j]);\n\n }\n\n }\n\n \n\n int test_tup5[4][2] = {{3, 5}, {6, 7}, {4, 11}, {3, 12}};\n\n int test_tup6[4][2] = {{8, 9}, {5, 11}, {3, 3}, {9, 5}};\n\n int expected3[4][2] = {{24, 45}, {30, 77}, {12, 33}, {27, 60}};\n\n func0(test_tup5, test_tup6, res, 4);\n\n for (int i = 0; i < 4; i++) {\n\n for (int j = 0; j < 2; j++) {\n\n assert(res[i][j] == expected3[i][j]);\n\n }\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %ecx,-0x2c(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11f8 \nmovl $0x0,-0x4(%rbp)\njmp 11ee \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0x4(%rbp),%eax\ncltq\nmov (%rdx,%rax,4),%edx\nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x20(%rbp),%rax\nadd %rax,%rcx\nmov -0x4(%rbp),%eax\ncltq\nmov (%rcx,%rax,4),%eax\nmov -0x8(%rbp),%ecx\nmovslq %ecx,%rcx\nlea 0x0(,%rcx,8),%rsi\nmov -0x28(%rbp),%rcx\nadd %rsi,%rcx\nimul %eax,%edx\nmov -0x4(%rbp),%eax\ncltq\nmov %edx,(%rcx,%rax,4)\naddl $0x1,-0x4(%rbp)\ncmpl $0x1,-0x4(%rbp)\njle 1192 \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 1189 \npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_28], rdx\nmov [rbp+var_2C], ecx\nmov [rbp+var_8], 0\njmp short loc_11F8\nloc_1189:\nmov [rbp+var_4], 0\njmp short loc_11EE\nloc_1192:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\ncdqe\nmov edx, [rdx+rax*4]\nmov eax, [rbp+var_8]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_20]\nadd rcx, rax\nmov eax, [rbp+var_4]\ncdqe\nmov eax, [rcx+rax*4]\nmov ecx, [rbp+var_8]\nmovsxd rcx, ecx\nlea rsi, ds:0[rcx*8]\nmov rcx, [rbp+var_28]\nadd rcx, rsi\nimul edx, eax\nmov eax, [rbp+var_4]\ncdqe\nmov [rcx+rax*4], edx\nadd [rbp+var_4], 1\nloc_11EE:\ncmp [rbp+var_4], 1\njle short loc_1192\nadd [rbp+var_8], 1\nloc_11F8:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_2C]\njl short loc_1189\nnop\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+24h] [rbp-8h]\n int j; // [rsp+28h] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a4 )\n break;\n for ( j = 0; j <= 1; ++j )\n *(_DWORD *)(8LL * (int)i + a3 + 4LL * j) = *(_DWORD *)(a2 + 8LL * (int)i + 4LL * j)\n * *(_DWORD *)(a1 + 8LL * (int)i + 4LL * j);\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_28], rdx\nmov [rbp+var_2C], ecx\nmov [rbp+var_8], 0\njmp short loc_11F8\nloc_1189:\nmov [rbp+var_4], 0\njmp short loc_11EE\nloc_1192:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\ncdqe\nmov edx, [rdx+rax*4]\nmov eax, [rbp+var_8]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_20]\nadd rcx, rax\nmov eax, [rbp+var_4]\ncdqe\nmov eax, [rcx+rax*4]\nmov ecx, [rbp+var_8]\nmovsxd rcx, ecx\nlea rsi, ds:0[rcx*8]\nmov rcx, [rbp+var_28]\nadd rcx, rsi\nimul edx, eax\nmov eax, [rbp+var_4]\ncdqe\nmov [rcx+rax*4], edx\nadd [rbp+var_4], 1\nloc_11EE:\ncmp [rbp+var_4], 1\njle short loc_1192\nadd [rbp+var_8], 1\nloc_11F8:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_2C]\njl short loc_1189\nnop\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+24h] [rbp-8h]\n int j; // [rsp+28h] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a4 )\n break;\n for ( j = 0; j <= 1; ++j )\n *(_DWORD *)(8LL * (int)i + a3 + 4LL * j) = *(_DWORD *)(a2 + 8LL * (int)i + 4LL * j)\n * *(_DWORD *)(a1 + 8LL * (int)i + 4LL * j);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, long long a3, int a4) {\n long long result;\n unsigned int i;\n int j;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a4) break;\n for (j = 0; j <= 1; ++j)\n *(uint32_t *)(8LL * (int)i + a3 + 4LL * j) =\n *(uint32_t *)(a2 + 8LL * (int)i + 4LL * j) *\n *(uint32_t *)(a1 + 8LL * (int)i + 4LL * j);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, long long a3, int a4) {\n long long result;\n unsigned int i;\n int j;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a4) break;\n for (j = 0; j <= 1; ++j)\n *(uint32_t *)(8LL * (int)i + a3 + 4LL * j) =\n *(uint32_t *)(a2 + 8LL * (int)i + 4LL * j) *\n *(uint32_t *)(a1 + 8LL * (int)i + 4LL * j);\n }\n return result;\n}" + }, + { + "index": 445, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "void func0(int test_tup1[][2], int test_tup2[][2], int res[][2],\n int num_tuples) {\n for (int i = 0; i < num_tuples; i++) {\n for (int j = 0; j < 2; j++) {\n res[i][j] = test_tup1[i][j] * test_tup2[i][j];\n }\n }\n}", + "test": "int main() {\n\n int res[4][2];\n\n \n\n int test_tup1[4][2] = {{1, 3}, {4, 5}, {2, 9}, {1, 10}};\n\n int test_tup2[4][2] = {{6, 7}, {3, 9}, {1, 1}, {7, 3}};\n\n int expected[4][2] = {{6, 21}, {12, 45}, {2, 9}, {7, 30}};\n\n func0(test_tup1, test_tup2, res, 4);\n\n for (int i = 0; i < 4; i++) {\n\n for (int j = 0; j < 2; j++) {\n\n assert(res[i][j] == expected[i][j]);\n\n }\n\n }\n\n \n\n int test_tup3[4][2] = {{2, 4}, {5, 6}, {3, 10}, {2, 11}};\n\n int test_tup4[4][2] = {{7, 8}, {4, 10}, {2, 2}, {8, 4}};\n\n int expected2[4][2] = {{14, 32}, {20, 60}, {6, 20}, {16, 44}};\n\n func0(test_tup3, test_tup4, res, 4);\n\n for (int i = 0; i < 4; i++) {\n\n for (int j = 0; j < 2; j++) {\n\n assert(res[i][j] == expected2[i][j]);\n\n }\n\n }\n\n \n\n int test_tup5[4][2] = {{3, 5}, {6, 7}, {4, 11}, {3, 12}};\n\n int test_tup6[4][2] = {{8, 9}, {5, 11}, {3, 3}, {9, 5}};\n\n int expected3[4][2] = {{24, 45}, {30, 77}, {12, 33}, {27, 60}};\n\n func0(test_tup5, test_tup6, res, 4);\n\n for (int i = 0; i < 4; i++) {\n\n for (int j = 0; j < 2; j++) {\n\n assert(res[i][j] == expected3[i][j]);\n\n }\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %ecx,%ecx\njle 119d \nlea -0x1(%rcx),%r8d\nmov $0x0,%eax\nmov (%rdi,%rax,8),%ecx\nimul (%rsi,%rax,8),%ecx\nmov %ecx,(%rdx,%rax,8)\nmov 0x4(%rdi,%rax,8),%ecx\nimul 0x4(%rsi,%rax,8),%ecx\nmov %ecx,0x4(%rdx,%rax,8)\nmov %rax,%rcx\nadd $0x1,%rax\ncmp %r8,%rcx\njne 117a \nretq\n", + "ida_asm": "func0:\nendbr64\ntest ecx, ecx\njle short locret_11A1\nmovsxd rcx, ecx\nlea r8, ds:0[rcx*8]\nmov eax, 0\nloc_1181:\nmov ecx, [rsi+rax]\nimul ecx, [rdi+rax]\nmov [rdx+rax], ecx\nmov ecx, [rdi+rax+4]\nimul ecx, [rsi+rax+4]\nmov [rdx+rax+4], ecx\nadd rax, 8\ncmp r8, rax\njnz short loc_1181\nlocret_11A1:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 v4; // rax\n\n if ( a4 > 0 )\n {\n v4 = 0LL;\n do\n {\n *(_DWORD *)(a3 + v4) = *(_DWORD *)(a1 + v4) * *(_DWORD *)(a2 + v4);\n *(_DWORD *)(a3 + v4 + 4) = *(_DWORD *)(a2 + v4 + 4) * *(_DWORD *)(a1 + v4 + 4);\n v4 += 8LL;\n }\n while ( 8LL * a4 != v4 );\n }\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest ecx, ecx\njle short locret_11A1\nmovsxd rcx, ecx\nlea r8, ds:0[rcx*8]\nmov eax, 0\nloc_1181:\nmov ecx, [rsi+rax]\nimul ecx, [rdi+rax]\nmov [rdx+rax], ecx\nmov ecx, [rdi+rax+4]\nimul ecx, [rsi+rax+4]\nmov [rdx+rax+4], ecx\nadd rax, 8\ncmp r8, rax\njnz short loc_1181\nlocret_11A1:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1169(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 v4; // rax\n\n if ( a4 > 0 )\n {\n v4 = 0LL;\n do\n {\n *(_DWORD *)(a3 + v4) = *(_DWORD *)(a1 + v4) * *(_DWORD *)(a2 + v4);\n *(_DWORD *)(a3 + v4 + 4) = *(_DWORD *)(a2 + v4 + 4) * *(_DWORD *)(a1 + v4 + 4);\n v4 += 8LL;\n }\n while ( 8LL * a4 != v4 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1169(long long a1, long long a2, long long a3, int a4) {\n long long v4;\n if (a4 > 0) {\n v4 = 0LL;\n do {\n *(uint32_t *)(a3 + v4) = *(uint32_t *)(a1 + v4) * *(uint32_t *)(a2 + v4);\n *(uint32_t *)(a3 + v4 + 4) =\n *(uint32_t *)(a2 + v4 + 4) * *(uint32_t *)(a1 + v4 + 4);\n v4 += 8LL;\n } while (8LL * a4 != v4);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, long long a2, long long a3, int a4) {\n long long v4;\n if (a4 > 0) {\n v4 = 0LL;\n do {\n *(uint32_t *)(a3 + v4) = *(uint32_t *)(a1 + v4) * *(uint32_t *)(a2 + v4);\n *(uint32_t *)(a3 + v4 + 4) =\n *(uint32_t *)(a2 + v4 + 4) * *(uint32_t *)(a1 + v4 + 4);\n v4 += 8LL;\n } while (8LL * a4 != v4);\n }\n}" + }, + { + "index": 445, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "void func0(int test_tup1[][2], int test_tup2[][2], int res[][2],\n int num_tuples) {\n for (int i = 0; i < num_tuples; i++) {\n for (int j = 0; j < 2; j++) {\n res[i][j] = test_tup1[i][j] * test_tup2[i][j];\n }\n }\n}", + "test": "int main() {\n\n int res[4][2];\n\n \n\n int test_tup1[4][2] = {{1, 3}, {4, 5}, {2, 9}, {1, 10}};\n\n int test_tup2[4][2] = {{6, 7}, {3, 9}, {1, 1}, {7, 3}};\n\n int expected[4][2] = {{6, 21}, {12, 45}, {2, 9}, {7, 30}};\n\n func0(test_tup1, test_tup2, res, 4);\n\n for (int i = 0; i < 4; i++) {\n\n for (int j = 0; j < 2; j++) {\n\n assert(res[i][j] == expected[i][j]);\n\n }\n\n }\n\n \n\n int test_tup3[4][2] = {{2, 4}, {5, 6}, {3, 10}, {2, 11}};\n\n int test_tup4[4][2] = {{7, 8}, {4, 10}, {2, 2}, {8, 4}};\n\n int expected2[4][2] = {{14, 32}, {20, 60}, {6, 20}, {16, 44}};\n\n func0(test_tup3, test_tup4, res, 4);\n\n for (int i = 0; i < 4; i++) {\n\n for (int j = 0; j < 2; j++) {\n\n assert(res[i][j] == expected2[i][j]);\n\n }\n\n }\n\n \n\n int test_tup5[4][2] = {{3, 5}, {6, 7}, {4, 11}, {3, 12}};\n\n int test_tup6[4][2] = {{8, 9}, {5, 11}, {3, 3}, {9, 5}};\n\n int expected3[4][2] = {{24, 45}, {30, 77}, {12, 33}, {27, 60}};\n\n func0(test_tup5, test_tup6, res, 4);\n\n for (int i = 0; i < 4; i++) {\n\n for (int j = 0; j < 2; j++) {\n\n assert(res[i][j] == expected3[i][j]);\n\n }\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %ecx,%ecx\njle 1583 \nlea -0x1(%rcx),%r8d\nxor %eax,%eax\nxchg %ax,%ax\nmov (%rdi,%rax,8),%ecx\nimul (%rsi,%rax,8),%ecx\nmov %ecx,(%rdx,%rax,8)\nmov 0x4(%rdi,%rax,8),%ecx\nimul 0x4(%rsi,%rax,8),%ecx\nmov %ecx,0x4(%rdx,%rax,8)\nmov %rax,%rcx\nadd $0x1,%rax\ncmp %rcx,%r8\njne 1560 \nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\ntest ecx, ecx\njle short locret_1438\nmovsxd rcx, ecx\nxor eax, eax\nlea r8, ds:0[rcx*8]\nnop dword ptr [rax]\nloc_1418:\nmov ecx, [rdi+rax]\nimul ecx, [rsi+rax]\nmov [rdx+rax], ecx\nmov ecx, [rdi+rax+4]\nimul ecx, [rsi+rax+4]\nmov [rdx+rax+4], ecx\nadd rax, 8\ncmp r8, rax\njnz short loc_1418\nlocret_1438:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 v4; // rax\n\n if ( a4 > 0 )\n {\n v4 = 0LL;\n do\n {\n *(_DWORD *)(a3 + v4) = *(_DWORD *)(a2 + v4) * *(_DWORD *)(a1 + v4);\n *(_DWORD *)(a3 + v4 + 4) = *(_DWORD *)(a2 + v4 + 4) * *(_DWORD *)(a1 + v4 + 4);\n v4 += 8LL;\n }\n while ( 8LL * a4 != v4 );\n }\n}", + "ida_strip_asm": "sub_1400:\nendbr64\ntest ecx, ecx\njle short locret_1438\nmovsxd rcx, ecx\nxor eax, eax\nlea r8, ds:0[rcx*8]\nnop dword ptr [rax]\nloc_1418:\nmov ecx, [rdi+rax]\nimul ecx, [rsi+rax]\nmov [rdx+rax], ecx\nmov ecx, [rdi+rax+4]\nimul ecx, [rsi+rax+4]\nmov [rdx+rax+4], ecx\nadd rax, 8\ncmp r8, rax\njnz short loc_1418\nlocret_1438:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1400(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 v4; // rax\n\n if ( a4 > 0 )\n {\n v4 = 0LL;\n do\n {\n *(_DWORD *)(a3 + v4) = *(_DWORD *)(a2 + v4) * *(_DWORD *)(a1 + v4);\n *(_DWORD *)(a3 + v4 + 4) = *(_DWORD *)(a2 + v4 + 4) * *(_DWORD *)(a1 + v4 + 4);\n v4 += 8LL;\n }\n while ( 8LL * a4 != v4 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1400(long long a1, long long a2, long long a3, int a4) {\n long long v4;\n if (a4 > 0) {\n v4 = 0LL;\n do {\n *(uint32_t *)(a3 + v4) = *(uint32_t *)(a2 + v4) * *(uint32_t *)(a1 + v4);\n *(uint32_t *)(a3 + v4 + 4) =\n *(uint32_t *)(a2 + v4 + 4) * *(uint32_t *)(a1 + v4 + 4);\n v4 += 8LL;\n } while (8LL * a4 != v4);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, long long a2, long long a3, int a4) {\n long long v4;\n if (a4 > 0) {\n v4 = 0LL;\n do {\n *(uint32_t *)(a3 + v4) = *(uint32_t *)(a2 + v4) * *(uint32_t *)(a1 + v4);\n *(uint32_t *)(a3 + v4 + 4) =\n *(uint32_t *)(a2 + v4 + 4) * *(uint32_t *)(a1 + v4 + 4);\n v4 += 8LL;\n } while (8LL * a4 != v4);\n }\n}" + }, + { + "index": 446, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(const int *tup, int tup_size, const int *lst, int lst_size) {\n int count = 0;\n for (int i = 0; i < tup_size; i++) {\n for (int j = 0; j < lst_size; j++) {\n if (tup[i] == lst[j]) {\n count++;\n break;\n }\n }\n }\n return count;\n}", + "test": "int main() {\n\n int tup1[] = {'a', 'a', 'c', 'b', 'd'};\n\n int lst1[] = {'a', 'b'};\n\n assert(func0(tup1, 5, lst1, 2) == 3);\n\n\n\n int tup2[] = {1, 2, 3, 1, 4, 6, 7, 1, 4};\n\n int lst2[] = {1, 4, 7};\n\n assert(func0(tup2, 9, lst2, 3) == 6);\n\n\n\n int tup3[] = {1, 2, 3, 4, 5, 6};\n\n int lst3[] = {1, 2};\n\n assert(func0(tup3, 6, lst3, 2) == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %ecx,-0x20(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11de \nmovl $0x0,-0x4(%rbp)\njmp 11d2 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 11ce \naddl $0x1,-0xc(%rbp)\njmp 11da \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x20(%rbp),%eax\njl 1198 \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 118f \nmov -0xc(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_11DE\nloc_118F:\nmov [rbp+var_4], 0\njmp short loc_11D2\nloc_1198:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11CE\nadd [rbp+var_C], 1\njmp short loc_11DA\nloc_11CE:\nadd [rbp+var_4], 1\nloc_11D2:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_20]\njl short loc_1198\nloc_11DA:\nadd [rbp+var_8], 1\nloc_11DE:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_118F\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3, int a4)\n{\n unsigned int v5; // [rsp+1Ch] [rbp-Ch]\n int i; // [rsp+20h] [rbp-8h]\n int j; // [rsp+24h] [rbp-4h]\n\n v5 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = 0; j < a4; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4LL * j + a3) )\n {\n ++v5;\n break;\n }\n }\n }\n return v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_11DE\nloc_118F:\nmov [rbp+var_4], 0\njmp short loc_11D2\nloc_1198:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11CE\nadd [rbp+var_C], 1\njmp short loc_11DA\nloc_11CE:\nadd [rbp+var_4], 1\nloc_11D2:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_20]\njl short loc_1198\nloc_11DA:\nadd [rbp+var_8], 1\nloc_11DE:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_118F\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, __int64 a3, int a4)\n{\n unsigned int v5; // [rsp+1Ch] [rbp-Ch]\n int i; // [rsp+20h] [rbp-8h]\n int j; // [rsp+24h] [rbp-4h]\n\n v5 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = 0; j < a4; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4LL * j + a3) )\n {\n ++v5;\n break;\n }\n }\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, long long a3, int a4) {\n unsigned int v5;\n int i;\n int j;\n v5 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = 0; j < a4; ++j) {\n if (*(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4LL * j + a3)) {\n ++v5;\n break;\n }\n }\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3, int a4) {\n unsigned int v5;\n int i;\n int j;\n v5 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = 0; j < a4; ++j) {\n if (*(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4LL * j + a3)) {\n ++v5;\n break;\n }\n }\n }\n return v5;\n}" + }, + { + "index": 446, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(const int *tup, int tup_size, const int *lst, int lst_size) {\n int count = 0;\n for (int i = 0; i < tup_size; i++) {\n for (int j = 0; j < lst_size; j++) {\n if (tup[i] == lst[j]) {\n count++;\n break;\n }\n }\n }\n return count;\n}", + "test": "int main() {\n\n int tup1[] = {'a', 'a', 'c', 'b', 'd'};\n\n int lst1[] = {'a', 'b'};\n\n assert(func0(tup1, 5, lst1, 2) == 3);\n\n\n\n int tup2[] = {1, 2, 3, 1, 4, 6, 7, 1, 4};\n\n int lst2[] = {1, 4, 7};\n\n assert(func0(tup2, 9, lst2, 3) == 6);\n\n\n\n int tup3[] = {1, 2, 3, 4, 5, 6};\n\n int lst3[] = {1, 2};\n\n assert(func0(tup3, 6, lst3, 2) == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11b3 \nmov %rdi,%r8\nlea -0x1(%rsi),%eax\nlea 0x4(%rdi,%rax,4),%r9\nmov %rdx,%r10\nlea -0x1(%rcx),%eax\nlea 0x4(%rdx,%rax,4),%rsi\nmov $0x0,%edi\njmp 119a \nadd $0x1,%edi\nadd $0x4,%r8\ncmp %r9,%r8\nje 11b8 \ntest %ecx,%ecx\njle 1191 \nmov (%r8),%edx\nmov %r10,%rax\ncmp (%rax),%edx\nje 118e \nadd $0x4,%rax\ncmp %rsi,%rax\njne 11a4 \njmp 1191 \nmov $0x0,%edi\nmov %edi,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11B0\nmov r8, rdi\nmovsxd rsi, esi\nlea r10, [rdi+rsi*4]\nmovsxd rax, ecx\nlea rdi, [rdx+rax*4]\nmov r9d, 0\njmp short loc_1197\nloc_118A:\nadd r9d, 1\nloc_118E:\nadd r8, 4\ncmp r8, r10\njz short loc_11B6\nloc_1197:\ntest ecx, ecx\njle short loc_118E\nmov esi, [r8]\nmov rax, rdx\nloc_11A1:\ncmp esi, [rax]\njz short loc_118A\nadd rax, 4\ncmp rax, rdi\njnz short loc_11A1\njmp short loc_118E\nloc_11B0:\nmov r9d, 0\nloc_11B6:\nmov eax, r9d\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2, _DWORD *a3, int a4)\n{\n _DWORD *v4; // r8\n unsigned int v5; // r9d\n _DWORD *v6; // rax\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v4 = a1;\n v5 = 0;\n do\n {\n if ( a4 > 0 )\n {\n v6 = a3;\n while ( *v4 != *v6 )\n {\n if ( ++v6 == &a3[a4] )\n goto LABEL_4;\n }\n ++v5;\n }\nLABEL_4:\n ++v4;\n }\n while ( v4 != &a1[a2] );\n }\n return v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11B0\nmov r8, rdi\nmovsxd rsi, esi\nlea r10, [rdi+rsi*4]\nmovsxd rax, ecx\nlea rdi, [rdx+rax*4]\nmov r9d, 0\njmp short loc_1197\nloc_118A:\nadd r9d, 1\nloc_118E:\nadd r8, 4\ncmp r8, r10\njz short loc_11B6\nloc_1197:\ntest ecx, ecx\njle short loc_118E\nmov esi, [r8]\nmov rax, rdx\nloc_11A1:\ncmp esi, [rax]\njz short loc_118A\nadd rax, 4\ncmp rax, rdi\njnz short loc_11A1\njmp short loc_118E\nloc_11B0:\nmov r9d, 0\nloc_11B6:\nmov eax, r9d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2, _DWORD *a3, int a4)\n{\n _DWORD *v4; // r8\n unsigned int v5; // r9d\n _DWORD *v6; // rax\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v4 = a1;\n v5 = 0;\n do\n {\n if ( a4 > 0 )\n {\n v6 = a3;\n while ( *v4 != *v6 )\n {\n if ( ++v6 == &a3[a4] )\n goto LABEL_4;\n }\n ++v5;\n }\nLABEL_4:\n ++v4;\n }\n while ( v4 != &a1[a2] );\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2, uint32_t *a3, int a4) {\n uint32_t *v4;\n unsigned int v5;\n uint32_t *v6;\n if (a2 <= 0) {\n return 0;\n } else {\n v4 = a1;\n v5 = 0;\n do {\n if (a4 > 0) {\n v6 = a3;\n while (*v4 != *v6) {\n if (++v6 == &a3[a4]) goto LABEL_4;\n }\n ++v5;\n }\n LABEL_4:\n ++v4;\n } while (v4 != &a1[a2]);\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2, uint32_t *a3, int a4) {\n uint32_t *v4;\n unsigned int v5;\n uint32_t *v6;\n if (a2 <= 0) {\n return 0;\n } else {\n v4 = a1;\n v5 = 0;\n do {\n if (a4 > 0) {\n v6 = a3;\n while (*v4 != *v6) {\n if (++v6 == &a3[a4]) goto LABEL_4;\n }\n ++v5;\n }\n LABEL_4:\n ++v4;\n } while (v4 != &a1[a2]);\n }\n return v5;\n}" + }, + { + "index": 446, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(const int *tup, int tup_size, const int *lst, int lst_size) {\n int count = 0;\n for (int i = 0; i < tup_size; i++) {\n for (int j = 0; j < lst_size; j++) {\n if (tup[i] == lst[j]) {\n count++;\n break;\n }\n }\n }\n return count;\n}", + "test": "int main() {\n\n int tup1[] = {'a', 'a', 'c', 'b', 'd'};\n\n int lst1[] = {'a', 'b'};\n\n assert(func0(tup1, 5, lst1, 2) == 3);\n\n\n\n int tup2[] = {1, 2, 3, 1, 4, 6, 7, 1, 4};\n\n int lst2[] = {1, 4, 7};\n\n assert(func0(tup2, 9, lst2, 3) == 6);\n\n\n\n int tup3[] = {1, 2, 3, 4, 5, 6};\n\n int lst3[] = {1, 2};\n\n assert(func0(tup3, 6, lst3, 2) == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 139e \nlea -0x1(%rsi),%eax\nmov %rdi,%r8\nxor %r9d,%r9d\nlea 0x4(%rdi,%rax,4),%r10\nlea -0x1(%rcx),%eax\nlea 0x4(%rdx,%rax,4),%rdi\nxchg %ax,%ax\ntest %ecx,%ecx\njle 1391 \nmov (%r8),%esi\nmov %rdx,%rax\njmp 1389 \nnopl 0x0(%rax)\nadd $0x4,%rax\ncmp %rdi,%rax\nje 1391 \ncmp (%rax),%esi\njne 1380 \nadd $0x1,%r9d\nadd $0x4,%r8\ncmp %r10,%r8\njne 1370 \nmov %r9d,%eax\nretq\nxor %r9d,%r9d\nmov %r9d,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_130C\nmovsxd rsi, esi\nlea r9, [rdi+rsi*4]\nloc_12FF:\ntest ecx, ecx\njg short loc_1313\nadd rdi, 4\ncmp rdi, r9\njnz short loc_12FF\nloc_130C:\nxor r8d, r8d\nmov eax, r8d\nretn\nloc_1313:\nmovsxd rcx, ecx\nxor r8d, r8d\nlea rsi, [rdx+rcx*4]\nnop dword ptr [rax]\nloc_1320:\nmov ecx, [rdi]\nmov rax, rdx\njmp short loc_1339\nloc_1330:\nadd rax, 4\ncmp rax, rsi\njz short loc_1350\nloc_1339:\ncmp ecx, [rax]\njnz short loc_1330\nadd rdi, 4\nadd r8d, 1\ncmp rdi, r9\njnz short loc_1320\nmov eax, r8d\nretn\nloc_1350:\nadd rdi, 4\ncmp rdi, r9\njnz short loc_1320\nmov eax, r8d\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2, _DWORD *a3, int a4)\n{\n _DWORD *v4; // r9\n unsigned int v6; // r8d\n _DWORD *v7; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v4 = &a1[a2];\n while ( a4 <= 0 )\n {\n if ( ++a1 == v4 )\n return 0LL;\n }\n v6 = 0;\nLABEL_7:\n while ( 2 )\n {\n v7 = a3;\n do\n {\n if ( *a1 == *v7 )\n {\n ++a1;\n ++v6;\n if ( a1 != v4 )\n goto LABEL_7;\n return v6;\n }\n ++v7;\n }\n while ( v7 != &a3[a4] );\n if ( ++a1 != v4 )\n continue;\n return v6;\n }\n}", + "ida_strip_asm": "sub_12F0:\nendbr64\ntest esi, esi\njle short loc_130C\nmovsxd rsi, esi\nlea r9, [rdi+rsi*4]\nloc_12FF:\ntest ecx, ecx\njg short loc_1313\nadd rdi, 4\ncmp rdi, r9\njnz short loc_12FF\nloc_130C:\nxor r8d, r8d\nmov eax, r8d\nretn\nloc_1313:\nmovsxd rcx, ecx\nxor r8d, r8d\nlea rsi, [rdx+rcx*4]\nnop dword ptr [rax]\nloc_1320:\nmov ecx, [rdi]\nmov rax, rdx\njmp short loc_1339\nloc_1330:\nadd rax, 4\ncmp rax, rsi\njz short loc_1350\nloc_1339:\ncmp ecx, [rax]\njnz short loc_1330\nadd rdi, 4\nadd r8d, 1\ncmp rdi, r9\njnz short loc_1320\nmov eax, r8d\nretn\nloc_1350:\nadd rdi, 4\ncmp rdi, r9\njnz short loc_1320\nmov eax, r8d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12F0(_DWORD *a1, int a2, _DWORD *a3, int a4)\n{\n _DWORD *v4; // r9\n unsigned int v6; // r8d\n _DWORD *v7; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v4 = &a1[a2];\n while ( a4 <= 0 )\n {\n if ( ++a1 == v4 )\n return 0LL;\n }\n v6 = 0;\nLABEL_7:\n while ( 2 )\n {\n v7 = a3;\n do\n {\n if ( *a1 == *v7 )\n {\n ++a1;\n ++v6;\n if ( a1 != v4 )\n goto LABEL_7;\n return v6;\n }\n ++v7;\n }\n while ( v7 != &a3[a4] );\n if ( ++a1 != v4 )\n continue;\n return v6;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12F0(uint32_t *a1, int a2, uint32_t *a3, int a4) {\n uint32_t *v4;\n unsigned int v6;\n uint32_t *v7;\n if (a2 <= 0) return 0LL;\n v4 = &a1[a2];\n while (a4 <= 0) {\n if (++a1 == v4) return 0LL;\n }\n v6 = 0;\nLABEL_7:\n while (2) {\n v7 = a3;\n do {\n if (*a1 == *v7) {\n ++a1;\n ++v6;\n if (a1 != v4) goto LABEL_7;\n return v6;\n }\n ++v7;\n } while (v7 != &a3[a4]);\n if (++a1 != v4) continue;\n return v6;\n }\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2, uint32_t *a3, int a4) {\n uint32_t *v4;\n unsigned int v6;\n uint32_t *v7;\n if (a2 <= 0) return 0LL;\n v4 = &a1[a2];\n while (a4 <= 0) {\n if (++a1 == v4) return 0LL;\n }\n v6 = 0;\nLABEL_7:\n while (2) {\n v7 = a3;\n do {\n if (*a1 == *v7) {\n ++a1;\n ++v6;\n if (a1 != v4) goto LABEL_7;\n return v6;\n }\n ++v7;\n } while (v7 != &a3[a4]);\n if (++a1 != v4) continue;\n return v6;\n }\n}" + }, + { + "index": 447, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int* func0(int nums[], int size) {\n static int cubes[100];\n for (int i = 0; i < size; i++) {\n cubes[i] = nums[i] * nums[i] * nums[i];\n }\n return cubes;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n int expected1[] = {1, 8, 27, 64, 125, 216, 343, 512, 729, 1000};\n\n int* result1 = func0(arr1, 10);\n\n for (int i = 0; i < 10; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n \n\n int arr2[] = {10, 20, 30};\n\n int expected2[] = {1000, 8000, 27000};\n\n int* result2 = func0(arr2, 3);\n\n for (int i = 0; i < 3; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n\n\n int arr3[] = {12, 15};\n\n int expected3[] = {1728, 3375};\n\n int* result3 = func0(arr3, 2);\n\n for (int i = 0; i < 2; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n\n\n printf(\"All test cases passed successfully!\\n\");\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 1205 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\nimul %eax,%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\nimul %edx,%eax\nmov -0x4(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nlea 0x2e42(%rip),%rdx\nmov %eax,(%rcx,%rdx,1)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11a1 \nlea 0x2e2c(%rip),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 0\njmp short loc_1205\nloc_11A1:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nimul edx, eax\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nimul eax, edx\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nlea rdx, cubes_1\nmov [rcx+rdx], eax\nadd [rbp+var_4], 1\nloc_1205:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11A1\nlea rax, cubes_1\npop rbp\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n cubes_1[i] = *(_DWORD *)(4LL * i + a1) * *(_DWORD *)(4LL * i + a1) * *(_DWORD *)(4LL * i + a1);\n return cubes_1;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 0\njmp short loc_1205\nloc_11A1:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nimul edx, eax\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nimul eax, edx\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nlea rdx, unk_4040\nmov [rcx+rdx], eax\nadd [rbp+var_4], 1\nloc_1205:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11A1\nlea rax, unk_4040\npop rbp\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1189(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n dword_4040[i] = *(_DWORD *)(4LL * i + a1) * *(_DWORD *)(4LL * i + a1) * *(_DWORD *)(4LL * i + a1);\n return dword_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1189(long long a1, int a2) {\n int i;\n for (i = 0; i < a2; ++i)\n dword_4040[i] = *(uint32_t *)(4LL * i + a1) * *(uint32_t *)(4LL * i + a1) *\n *(uint32_t *)(4LL * i + a1);\n return dword_4040;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2) {\n int i;\n for (i = 0; i < a2; ++i)\n cubes_1[i] = *(uint32_t *)(4LL * i + a1) * *(uint32_t *)(4LL * i + a1) *\n *(uint32_t *)(4LL * i + a1);\n return cubes_1;\n}" + }, + { + "index": 447, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int* func0(int nums[], int size) {\n static int cubes[100];\n for (int i = 0; i < size; i++) {\n cubes[i] = nums[i] * nums[i] * nums[i];\n }\n return cubes;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n int expected1[] = {1, 8, 27, 64, 125, 216, 343, 512, 729, 1000};\n\n int* result1 = func0(arr1, 10);\n\n for (int i = 0; i < 10; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n \n\n int arr2[] = {10, 20, 30};\n\n int expected2[] = {1000, 8000, 27000};\n\n int* result2 = func0(arr2, 3);\n\n for (int i = 0; i < 3; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n\n\n int arr3[] = {12, 15};\n\n int expected3[] = {1728, 3375};\n\n int* result3 = func0(arr3, 2);\n\n for (int i = 0; i < 2; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n\n\n printf(\"All test cases passed successfully!\\n\");\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11bb \nlea -0x1(%rsi),%r8d\nmov $0x0,%eax\nlea 0x2e9f(%rip),%rsi\nmov (%rdi,%rax,4),%ecx\nmov %ecx,%edx\nimul %ecx,%edx\nimul %ecx,%edx\nmov %edx,(%rsi,%rax,4)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %r8,%rdx\njne 11a1 \nlea 0x2e7e(%rip),%rax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11BC\nmovsxd rsi, esi\nshl rsi, 2\nmov eax, 0\nlea r8, cubes_1\nloc_11A4:\nmov ecx, [rdi+rax]\nmov edx, ecx\nimul edx, ecx\nimul edx, ecx\nmov [r8+rax], edx\nadd rax, 4\ncmp rax, rsi\njnz short loc_11A4\nloc_11BC:\nlea rax, cubes_1\nretn", + "ida_pseudo": "void *__fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // rsi\n __int64 v3; // rax\n\n if ( a2 > 0 )\n {\n v2 = 4LL * a2;\n v3 = 0LL;\n do\n {\n *(_DWORD *)((char *)&cubes_1 + v3) = *(_DWORD *)(a1 + v3) * *(_DWORD *)(a1 + v3) * *(_DWORD *)(a1 + v3);\n v3 += 4LL;\n }\n while ( v3 != v2 );\n }\n return &cubes_1;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\ntest esi, esi\njle short loc_11BC\nmovsxd rsi, esi\nshl rsi, 2\nmov eax, 0\nlea r8, unk_4040\nloc_11A4:\nmov ecx, [rdi+rax]\nmov edx, ecx\nimul edx, ecx\nimul edx, ecx\nmov [r8+rax], edx\nadd rax, 4\ncmp rax, rsi\njnz short loc_11A4\nloc_11BC:\nlea rax, unk_4040\nretn", + "ida_strip_pseudo": "void *__fastcall sub_1189(__int64 a1, int a2)\n{\n __int64 v2; // rsi\n __int64 v3; // rax\n\n if ( a2 > 0 )\n {\n v2 = 4LL * a2;\n v3 = 0LL;\n do\n {\n *(_DWORD *)((char *)&unk_4040 + v3) = *(_DWORD *)(a1 + v3) * *(_DWORD *)(a1 + v3) * *(_DWORD *)(a1 + v3);\n v3 += 4LL;\n }\n while ( v3 != v2 );\n }\n return &unk_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1189(long long a1, int a2) {\n long long v2;\n long long v3;\n if (a2 > 0) {\n v2 = 4LL * a2;\n v3 = 0LL;\n do {\n *(uint32_t *)((char *)&unk_4040 + v3) = *(uint32_t *)(a1 + v3) *\n *(uint32_t *)(a1 + v3) *\n *(uint32_t *)(a1 + v3);\n v3 += 4LL;\n } while (v3 != v2);\n }\n return &unk_4040;\n}", + "ida_pseudo_norm": "void *func0(long long a1, int a2) {\n long long v2;\n long long v3;\n if (a2 > 0) {\n v2 = 4LL * a2;\n v3 = 0LL;\n do {\n *(uint32_t *)((char *)&cubes_1 + v3) = *(uint32_t *)(a1 + v3) *\n *(uint32_t *)(a1 + v3) *\n *(uint32_t *)(a1 + v3);\n v3 += 4LL;\n } while (v3 != v2);\n }\n return &cubes_1;\n}" + }, + { + "index": 448, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int n) {\n int a = 3, b = 0, c = 2;\n if (n == 0) return 3;\n if (n == 1) return 3;\n if (n == 2) return 5;\n int sum = 5;\n while (n > 2) {\n int d = a + b;\n sum += d;\n a = b;\n b = c;\n c = d;\n n--;\n }\n return sum;\n}", + "test": "int main() {\n\n assert(func0(9) == 49);\n\n assert(func0(10) == 66);\n\n assert(func0(11) == 88);\n\n \n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x24(%rbp)\nmovl $0x3,-0x14(%rbp)\nmovl $0x0,-0x10(%rbp)\nmovl $0x2,-0xc(%rbp)\ncmpl $0x0,-0x24(%rbp)\njne 1176 \nmov $0x3,%eax\njmp 11c9 \ncmpl $0x1,-0x24(%rbp)\njne 1183 \nmov $0x3,%eax\njmp 11c9 \ncmpl $0x2,-0x24(%rbp)\njne 1190 \nmov $0x5,%eax\njmp 11c9 \nmovl $0x5,-0x8(%rbp)\njmp 11c0 \nmov -0x14(%rbp),%edx\nmov -0x10(%rbp),%eax\nadd %edx,%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nadd %eax,-0x8(%rbp)\nmov -0x10(%rbp),%eax\nmov %eax,-0x14(%rbp)\nmov -0xc(%rbp),%eax\nmov %eax,-0x10(%rbp)\nmov -0x4(%rbp),%eax\nmov %eax,-0xc(%rbp)\nsubl $0x1,-0x24(%rbp)\ncmpl $0x2,-0x24(%rbp)\njg 1199 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_24], edi\nmov [rbp+var_14], 3\nmov [rbp+var_10], 0\nmov [rbp+var_C], 2\ncmp [rbp+var_24], 0\njnz short loc_1176\nmov eax, 3\njmp short loc_11C9\nloc_1176:\ncmp [rbp+var_24], 1\njnz short loc_1183\nmov eax, 3\njmp short loc_11C9\nloc_1183:\ncmp [rbp+var_24], 2\njnz short loc_1190\nmov eax, 5\njmp short loc_11C9\nloc_1190:\nmov [rbp+var_8], 5\njmp short loc_11C0\nloc_1199:\nmov edx, [rbp+var_14]\nmov eax, [rbp+var_10]\nadd eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\nadd [rbp+var_8], eax\nmov eax, [rbp+var_10]\nmov [rbp+var_14], eax\nmov eax, [rbp+var_C]\nmov [rbp+var_10], eax\nmov eax, [rbp+var_4]\nmov [rbp+var_C], eax\nsub [rbp+var_24], 1\nloc_11C0:\ncmp [rbp+var_24], 2\njg short loc_1199\nmov eax, [rbp+var_8]\nloc_11C9:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v2; // [rsp+0h] [rbp-24h]\n int v3; // [rsp+10h] [rbp-14h]\n int v4; // [rsp+14h] [rbp-10h]\n int v5; // [rsp+18h] [rbp-Ch]\n unsigned int v6; // [rsp+1Ch] [rbp-8h]\n int v7; // [rsp+20h] [rbp-4h]\n\n v2 = a1;\n v3 = 3;\n v4 = 0;\n v5 = 2;\n switch ( a1 )\n {\n case 0:\n return 3LL;\n case 1:\n return 3LL;\n case 2:\n return 5LL;\n }\n v6 = 5;\n while ( v2 > 2 )\n {\n v7 = v3 + v4;\n v6 += v3 + v4;\n v3 = v4;\n v4 = v5;\n v5 = v7;\n --v2;\n }\n return v6;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_24], edi\nmov [rbp+var_14], 3\nmov [rbp+var_10], 0\nmov [rbp+var_C], 2\ncmp [rbp+var_24], 0\njnz short loc_1176\nmov eax, 3\njmp short loc_11C9\nloc_1176:\ncmp [rbp+var_24], 1\njnz short loc_1183\nmov eax, 3\njmp short loc_11C9\nloc_1183:\ncmp [rbp+var_24], 2\njnz short loc_1190\nmov eax, 5\njmp short loc_11C9\nloc_1190:\nmov [rbp+var_8], 5\njmp short loc_11C0\nloc_1199:\nmov edx, [rbp+var_14]\nmov eax, [rbp+var_10]\nadd eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\nadd [rbp+var_8], eax\nmov eax, [rbp+var_10]\nmov [rbp+var_14], eax\nmov eax, [rbp+var_C]\nmov [rbp+var_10], eax\nmov eax, [rbp+var_4]\nmov [rbp+var_C], eax\nsub [rbp+var_24], 1\nloc_11C0:\ncmp [rbp+var_24], 2\njg short loc_1199\nmov eax, [rbp+var_8]\nloc_11C9:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v2; // [rsp+0h] [rbp-24h]\n int v3; // [rsp+10h] [rbp-14h]\n int v4; // [rsp+14h] [rbp-10h]\n int v5; // [rsp+18h] [rbp-Ch]\n unsigned int v6; // [rsp+1Ch] [rbp-8h]\n int v7; // [rsp+20h] [rbp-4h]\n\n v2 = a1;\n v3 = 3;\n v4 = 0;\n v5 = 2;\n switch ( a1 )\n {\n case 0:\n return 3LL;\n case 1:\n return 3LL;\n case 2:\n return 5LL;\n }\n v6 = 5;\n while ( v2 > 2 )\n {\n v7 = v3 + v4;\n v6 += v3 + v4;\n v3 = v4;\n v4 = v5;\n v5 = v7;\n --v2;\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v2;\n int v3;\n int v4;\n int v5;\n unsigned int v6;\n int v7;\n v2 = a1;\n v3 = 3;\n v4 = 0;\n v5 = 2;\n switch (a1) {\n case 0:\n return 3LL;\n case 1:\n return 3LL;\n case 2:\n return 5LL;\n }\n v6 = 5;\n while (v2 > 2) {\n v7 = v3 + v4;\n v6 += v3 + v4;\n v3 = v4;\n v4 = v5;\n v5 = v7;\n --v2;\n }\n return v6;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v2;\n int v3;\n int v4;\n int v5;\n unsigned int v6;\n int v7;\n v2 = a1;\n v3 = 3;\n v4 = 0;\n v5 = 2;\n switch (a1) {\n case 0:\n return 3LL;\n case 1:\n return 3LL;\n case 2:\n return 5LL;\n }\n v6 = 5;\n while (v2 > 2) {\n v7 = v3 + v4;\n v6 += v3 + v4;\n v3 = v4;\n v4 = v5;\n v5 = v7;\n --v2;\n }\n return v6;\n}" + }, + { + "index": 448, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int n) {\n int a = 3, b = 0, c = 2;\n if (n == 0) return 3;\n if (n == 1) return 3;\n if (n == 2) return 5;\n int sum = 5;\n while (n > 2) {\n int d = a + b;\n sum += d;\n a = b;\n b = c;\n c = d;\n n--;\n }\n return sum;\n}", + "test": "int main() {\n\n assert(func0(9) == 49);\n\n assert(func0(10) == 66);\n\n assert(func0(11) == 88);\n\n \n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x3,%ecx\ncmp $0x1,%edi\njbe 1188 \ncmp $0x2,%edi\njle 118b \nmov $0x5,%ecx\nmov $0x2,%r8d\nmov $0x0,%eax\nmov $0x3,%esi\njmp 1176 \nmov %edx,%r8d\nlea (%rsi,%rax,1),%edx\nadd %edx,%ecx\nsub $0x1,%edi\nmov %eax,%esi\nmov %r8d,%eax\ncmp $0x2,%edi\njne 1173 \nmov %ecx,%eax\nretq\nmov $0x5,%ecx\njmp 1188 \n", + "ida_asm": "func0:\nendbr64\nmov ecx, 3\ncmp edi, 1\njbe short loc_1188\ncmp edi, 2\njle short loc_118B\nmov ecx, 5\nmov r8d, 2\nmov eax, 0\nmov esi, 3\njmp short loc_1176\nloc_1173:\nmov r8d, edx\nloc_1176:\nlea edx, [rsi+rax]\nadd ecx, edx\nsub edi, 1\nmov esi, eax\nmov eax, r8d\ncmp edi, 2\njnz short loc_1173\nloc_1188:\nmov eax, ecx\nretn\nloc_118B:\nmov ecx, 5\njmp short loc_1188", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v1; // ecx\n int v2; // r8d\n int v3; // eax\n int v4; // esi\n int v5; // edx\n\n v1 = 3;\n if ( (unsigned int)a1 > 1 )\n {\n if ( a1 <= 2 )\n {\n return 5;\n }\n else\n {\n v1 = 5;\n v2 = 2;\n v3 = 0;\n v4 = 3;\n while ( 1 )\n {\n v5 = v4 + v3;\n v1 += v4 + v3;\n --a1;\n v4 = v3;\n v3 = v2;\n if ( a1 == 2 )\n break;\n v2 = v5;\n }\n }\n }\n return v1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmov ecx, 3\ncmp edi, 1\njbe short loc_1188\ncmp edi, 2\njle short loc_118B\nmov ecx, 5\nmov r8d, 2\nmov eax, 0\nmov esi, 3\njmp short loc_1176\nloc_1173:\nmov r8d, edx\nloc_1176:\nlea edx, [rsi+rax]\nadd ecx, edx\nsub edi, 1\nmov esi, eax\nmov eax, r8d\ncmp edi, 2\njnz short loc_1173\nloc_1188:\nmov eax, ecx\nretn\nloc_118B:\nmov ecx, 5\njmp short loc_1188", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n unsigned int v1; // ecx\n int v2; // r8d\n int v3; // eax\n int v4; // esi\n int v5; // edx\n\n v1 = 3;\n if ( (unsigned int)a1 > 1 )\n {\n if ( a1 <= 2 )\n {\n return 5;\n }\n else\n {\n v1 = 5;\n v2 = 2;\n v3 = 0;\n v4 = 3;\n while ( 1 )\n {\n v5 = v4 + v3;\n v1 += v4 + v3;\n --a1;\n v4 = v3;\n v3 = v2;\n if ( a1 == 2 )\n break;\n v2 = v5;\n }\n }\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n unsigned int v1;\n int v2;\n int v3;\n int v4;\n int v5;\n v1 = 3;\n if ((unsigned int)a1 > 1) {\n if (a1 <= 2) {\n return 5;\n } else {\n v1 = 5;\n v2 = 2;\n v3 = 0;\n v4 = 3;\n while (1) {\n v5 = v4 + v3;\n v1 += v4 + v3;\n --a1;\n v4 = v3;\n v3 = v2;\n if (a1 == 2) break;\n v2 = v5;\n }\n }\n }\n return v1;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v1;\n int v2;\n int v3;\n int v4;\n int v5;\n v1 = 3;\n if ((unsigned int)a1 > 1) {\n if (a1 <= 2) {\n return 5;\n } else {\n v1 = 5;\n v2 = 2;\n v3 = 0;\n v4 = 3;\n while (1) {\n v5 = v4 + v3;\n v1 += v4 + v3;\n --a1;\n v4 = v3;\n v3 = v2;\n if (a1 == 2) break;\n v2 = v5;\n }\n }\n }\n return v1;\n}" + }, + { + "index": 449, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "char* func0(int x1, int y1, int x2, int y2, int x3, int y3) {\n int a = (x1 * (y2 - y3) + x2 * (y3 - y1) + x3 * (y1 - y2));\n if (a == 0) {\n return \"No\";\n } else {\n return \"Yes\";\n }\n}", + "test": "int main() {\n\n assert(func0(1, 5, 2, 5, 4, 6) == \"Yes\");\n\n assert(func0(1, 1, 1, 4, 1, 5) == \"No\");\n\n assert(func0(1, 1, 1, 1, 1, 1) == \"No\");\n\n \n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov %edx,-0x1c(%rbp)\nmov %ecx,-0x20(%rbp)\nmov %r8d,-0x24(%rbp)\nmov %r9d,-0x28(%rbp)\nmov -0x20(%rbp),%eax\nsub -0x28(%rbp),%eax\nimul -0x14(%rbp),%eax\nmov %eax,%edx\nmov -0x28(%rbp),%eax\nsub -0x18(%rbp),%eax\nimul -0x1c(%rbp),%eax\nadd %eax,%edx\nmov -0x18(%rbp),%eax\nsub -0x20(%rbp),%eax\nimul -0x24(%rbp),%eax\nadd %edx,%eax\nmov %eax,-0x4(%rbp)\ncmpl $0x0,-0x4(%rbp)\njne 119b \nlea 0xe6f(%rip),%rax\njmp 11a2 \nlea 0xe69(%rip),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov [rbp+var_20], ecx\nmov [rbp+var_24], r8d\nmov [rbp+var_28], r9d\nmov eax, [rbp+var_20]\nsub eax, [rbp+var_28]\nimul eax, [rbp+var_14]\nmov edx, eax\nmov eax, [rbp+var_28]\nsub eax, [rbp+var_18]\nimul eax, [rbp+var_1C]\nadd edx, eax\nmov eax, [rbp+var_18]\nsub eax, [rbp+var_20]\nimul eax, [rbp+var_24]\nadd eax, edx\nmov [rbp+var_4], eax\ncmp [rbp+var_4], 0\njnz short loc_119B\nlea rax, unk_2008\njmp short loc_11A2\nloc_119B:\nlea rax, unk_200B\nloc_11A2:\npop rbp\nretn", + "ida_pseudo": "void *__fastcall func0(int a1, int a2, int a3, int a4, int a5, int a6)\n{\n if ( a3 * (a6 - a2) + a1 * (a4 - a6) + a5 * (a2 - a4) )\n return &unk_200B;\n else\n return &unk_2008;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov [rbp+var_20], ecx\nmov [rbp+var_24], r8d\nmov [rbp+var_28], r9d\nmov eax, [rbp+var_20]\nsub eax, [rbp+var_28]\nimul eax, [rbp+var_14]\nmov edx, eax\nmov eax, [rbp+var_28]\nsub eax, [rbp+var_18]\nimul eax, [rbp+var_1C]\nadd edx, eax\nmov eax, [rbp+var_18]\nsub eax, [rbp+var_20]\nimul eax, [rbp+var_24]\nadd eax, edx\nmov [rbp+var_4], eax\ncmp [rbp+var_4], 0\njnz short loc_119B\nlea rax, unk_2008\njmp short loc_11A2\nloc_119B:\nlea rax, unk_200B\nloc_11A2:\npop rbp\nretn", + "ida_strip_pseudo": "void *__fastcall sub_1149(int a1, int a2, int a3, int a4, int a5, int a6)\n{\n if ( a3 * (a6 - a2) + a1 * (a4 - a6) + a5 * (a2 - a4) )\n return &unk_200B;\n else\n return &unk_2008;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void* sub_1149(int a1, int a2, int a3, int a4, int a5, int a6) {\n if (a3 * (a6 - a2) + a1 * (a4 - a6) + a5 * (a2 - a4))\n return &unk_200B;\n else\n return &unk_2008;\n}", + "ida_pseudo_norm": "void* func0(int a1, int a2, int a3, int a4, int a5, int a6) {\n if (a3 * (a6 - a2) + a1 * (a4 - a6) + a5 * (a2 - a4))\n return &unk_200B;\n else\n return &unk_2008;\n}" + }, + { + "index": 450, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char **func0(char *str[], int n, int l, int *size) {\n static char *result[100];\n int count = 0;\n for (int i = 0; i < n; ++i) {\n if (strlen(str[i]) == l) {\n result[count++] = str[i];\n }\n }\n *size = count;\n return result;\n}", + "test": "int main() {\n\n char *testData1[] = {\"Python\", \"list\", \"exercises\", \"practice\", \"solution\"};\n\n int size;\n\n\n\n char **result = func0(testData1, 5, 8, &size);\n\n assert(size == 2);\n\n assert(strcmp(result[0], \"practice\") == 0);\n\n assert(strcmp(result[1], \"solution\") == 0);\n\n\n\n result = func0(testData1, 5, 6, &size);\n\n assert(size == 1);\n\n assert(strcmp(result[0], \"Python\") == 0);\n\n\n\n result = func0(testData1, 5, 9, &size);\n\n assert(size == 1);\n\n assert(strcmp(result[0], \"exercises\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmov %rcx,-0x28(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 1237 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov %rax,%rdi\ncallq 1080 \nmov -0x20(%rbp),%edx\nmovslq %edx,%rdx\ncmp %rdx,%rax\njne 1233 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x8(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x8(%rbp)\nmov (%rcx),%rdx\ncltq\nlea 0x0(,%rax,8),%rcx\nlea 0x2e11(%rip),%rax\nmov %rdx,(%rcx,%rax,1)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11d3 \nmov -0x28(%rbp),%rax\nmov -0x8(%rbp),%edx\nmov %edx,(%rax)\nlea 0x2df1(%rip),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_28], rcx\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_1239\nloc_11D3:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov eax, [rbp+var_20]\ncdqe\ncmp rdx, rax\njnz short loc_1235\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_8]\nlea edx, [rax+1]\nmov [rbp+var_8], edx\nmov rdx, [rcx]\ncdqe\nlea rcx, ds:0[rax*8]\nlea rax, result_1\nmov [rcx+rax], rdx\nloc_1235:\nadd [rbp+var_4], 1\nloc_1239:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11D3\nmov rax, [rbp+var_28]\nmov edx, [rbp+var_8]\nmov [rax], edx\nlea rax, result_1\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, int a2, int a3, _DWORD *a4)\n{\n int v4; // eax\n int v8; // [rsp+28h] [rbp-8h]\n int i; // [rsp+2Ch] [rbp-4h]\n\n v8 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( strlen(*(const char **)(8LL * i + a1)) == a3 )\n {\n v4 = v8++;\n result_1[v4] = *(_QWORD *)(8LL * i + a1);\n }\n }\n *a4 = v8;\n return result_1;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_28], rcx\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_1239\nloc_11D3:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov eax, [rbp+var_20]\ncdqe\ncmp rdx, rax\njnz short loc_1235\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_8]\nlea edx, [rax+1]\nmov [rbp+var_8], edx\nmov rdx, [rcx]\ncdqe\nlea rcx, ds:0[rax*8]\nlea rax, unk_4040\nmov [rcx+rax], rdx\nloc_1235:\nadd [rbp+var_4], 1\nloc_1239:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11D3\nmov rax, [rbp+var_28]\nmov edx, [rbp+var_8]\nmov [rax], edx\nlea rax, unk_4040\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11A9(__int64 a1, int a2, int a3, _DWORD *a4)\n{\n int v4; // eax\n int v8; // [rsp+28h] [rbp-8h]\n int i; // [rsp+2Ch] [rbp-4h]\n\n v8 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( strlen(*(const char **)(8LL * i + a1)) == a3 )\n {\n v4 = v8++;\n qword_4040[v4] = *(_QWORD *)(8LL * i + a1);\n }\n }\n *a4 = v8;\n return qword_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11A9(long long a1, int a2, int a3, uint32_t *a4) {\n int v4;\n int v8;\n int i;\n v8 = 0;\n for (i = 0; i < a2; ++i) {\n if (strlen(*(const char **)(8LL * i + a1)) == a3) {\n v4 = v8++;\n qword_4040[v4] = *(uint64_t *)(8LL * i + a1);\n }\n }\n *a4 = v8;\n return qword_4040;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, int a2, int a3, uint32_t *a4) {\n int v4;\n int v8;\n int i;\n v8 = 0;\n for (i = 0; i < a2; ++i) {\n if (strlen(*(const char **)(8LL * i + a1)) == a3) {\n v4 = v8++;\n result_1[v4] = *(uint64_t *)(8LL * i + a1);\n }\n }\n *a4 = v8;\n return result_1;\n}" + }, + { + "index": 450, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char **func0(char *str[], int n, int l, int *size) {\n static char *result[100];\n int count = 0;\n for (int i = 0; i < n; ++i) {\n if (strlen(str[i]) == l) {\n result[count++] = str[i];\n }\n }\n *size = count;\n return result;\n}", + "test": "int main() {\n\n char *testData1[] = {\"Python\", \"list\", \"exercises\", \"practice\", \"solution\"};\n\n int size;\n\n\n\n char **result = func0(testData1, 5, 8, &size);\n\n assert(size == 2);\n\n assert(strcmp(result[0], \"practice\") == 0);\n\n assert(strcmp(result[1], \"solution\") == 0);\n\n\n\n result = func0(testData1, 5, 6, &size);\n\n assert(size == 1);\n\n assert(strcmp(result[0], \"Python\") == 0);\n\n\n\n result = func0(testData1, 5, 9, &size);\n\n assert(size == 1);\n\n assert(strcmp(result[0], \"exercises\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nmov %rcx,%rbx\ntest %esi,%esi\njle 11cd \nmov %rdi,%r8\nlea -0x1(%rsi),%eax\nlea 0x8(%rdi,%rax,8),%r11\nmov $0x0,%r9d\nmov $0xffffffffffffffff,%r10\nmov $0x0,%eax\nmovslq %edx,%rsi\nlea 0x2ea3(%rip),%rbp\njmp 11a8 \nadd $0x8,%r8\ncmp %r11,%r8\nje 11d3 \nmov (%r8),%rdx\nmov %r10,%rcx\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nnot %rcx\nsub $0x1,%rcx\ncmp %rsi,%rcx\njne 119f \nmovslq %r9d,%rcx\nmov %rdx,0x0(%rbp,%rcx,8)\nlea 0x1(%r9),%r9d\njmp 119f \nmov $0x0,%r9d\nmov %r9d,(%rbx)\nlea 0x2e63(%rip),%rax\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rcx\ntest esi, esi\njle short loc_1206\nmov rbx, rdi\nmovsxd rsi, esi\nlea r14, [rdi+rsi*8]\nmov r13d, 0\nmovsxd r12, edx\nlea r15, result_1\njmp short loc_11E9\nloc_11E0:\nadd rbx, 8\ncmp rbx, r14\njz short loc_120C\nloc_11E9:\nmov rbp, [rbx]\nmov rdi, rbp; s\ncall _strlen\ncmp rax, r12\njnz short loc_11E0\nmovsxd rax, r13d\nmov [r15+rax*8], rbp\nlea r13d, [r13+1]\njmp short loc_11E0\nloc_1206:\nmov r13d, 0\nloc_120C:\nmov rax, [rsp+48h+var_40]\nmov [rax], r13d\nlea rax, result_1\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(const char **a1, int a2, int a3, _DWORD *a4)\n{\n const char **v4; // rbx\n int v5; // r13d\n __int64 v6; // r12\n const char *v7; // rbp\n\n if ( a2 <= 0 )\n {\n v5 = 0;\n }\n else\n {\n v4 = a1;\n v5 = 0;\n v6 = a3;\n do\n {\n v7 = *v4;\n if ( strlen(*v4) == v6 )\n result_1[v5++] = v7;\n ++v4;\n }\n while ( v4 != &a1[a2] );\n }\n *a4 = v5;\n return result_1;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rcx\ntest esi, esi\njle short loc_1206\nmov rbx, rdi\nmovsxd rsi, esi\nlea r14, [rdi+rsi*8]\nmov r13d, 0\nmovsxd r12, edx\nlea r15, unk_4040\njmp short loc_11E9\nloc_11E0:\nadd rbx, 8\ncmp rbx, r14\njz short loc_120C\nloc_11E9:\nmov rbp, [rbx]\nmov rdi, rbp; s\ncall _strlen\ncmp rax, r12\njnz short loc_11E0\nmovsxd rax, r13d\nmov [r15+rax*8], rbp\nlea r13d, [r13+1]\njmp short loc_11E0\nloc_1206:\nmov r13d, 0\nloc_120C:\nmov rax, [rsp+48h+var_40]\nmov [rax], r13d\nlea rax, unk_4040\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11A9(const char **a1, int a2, int a3, _DWORD *a4)\n{\n const char **v4; // rbx\n int v5; // r13d\n __int64 v6; // r12\n const char *v7; // rbp\n\n if ( a2 <= 0 )\n {\n v5 = 0;\n }\n else\n {\n v4 = a1;\n v5 = 0;\n v6 = a3;\n do\n {\n v7 = *v4;\n if ( strlen(*v4) == v6 )\n qword_4040[v5++] = v7;\n ++v4;\n }\n while ( v4 != &a1[a2] );\n }\n *a4 = v5;\n return qword_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11A9(const char **a1, int a2, int a3, uint32_t *a4) {\n const char **v4;\n int v5;\n long long v6;\n const char *v7;\n if (a2 <= 0) {\n v5 = 0;\n } else {\n v4 = a1;\n v5 = 0;\n v6 = a3;\n do {\n v7 = *v4;\n if (strlen(*v4) == v6) qword_4040[v5++] = v7;\n ++v4;\n } while (v4 != &a1[a2]);\n }\n *a4 = v5;\n return qword_4040;\n}", + "ida_pseudo_norm": "uint64_t *func0(const char **a1, int a2, int a3, uint32_t *a4) {\n const char **v4;\n int v5;\n long long v6;\n const char *v7;\n if (a2 <= 0) {\n v5 = 0;\n } else {\n v4 = a1;\n v5 = 0;\n v6 = a3;\n do {\n v7 = *v4;\n if (strlen(*v4) == v6) result_1[v5++] = v7;\n ++v4;\n } while (v4 != &a1[a2]);\n }\n *a4 = v5;\n return result_1;\n}" + }, + { + "index": 450, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char **func0(char *str[], int n, int l, int *size) {\n static char *result[100];\n int count = 0;\n for (int i = 0; i < n; ++i) {\n if (strlen(str[i]) == l) {\n result[count++] = str[i];\n }\n }\n *size = count;\n return result;\n}", + "test": "int main() {\n\n char *testData1[] = {\"Python\", \"list\", \"exercises\", \"practice\", \"solution\"};\n\n int size;\n\n\n\n char **result = func0(testData1, 5, 8, &size);\n\n assert(size == 2);\n\n assert(strcmp(result[0], \"practice\") == 0);\n\n assert(strcmp(result[1], \"solution\") == 0);\n\n\n\n result = func0(testData1, 5, 6, &size);\n\n assert(size == 1);\n\n assert(strcmp(result[0], \"Python\") == 0);\n\n\n\n result = func0(testData1, 5, 9, &size);\n\n assert(size == 1);\n\n assert(strcmp(result[0], \"exercises\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov %rcx,0x8(%rsp)\ntest %esi,%esi\njle 1440 \nlea -0x1(%rsi),%eax\nmovslq %edx,%rbp\nmov %rdi,%rbx\nxor %r12d,%r12d\nlea 0x8(%rdi,%rax,8),%r13\nlea 0x2c4d(%rip),%r15\nnopl 0x0(%rax,%rax,1)\nmov (%rbx),%r14\nmov %r14,%rdi\ncallq 1070 \ncmp %rbp,%rax\njne 1413 \nmovslq %r12d,%rax\nadd $0x1,%r12d\nmov %r14,(%r15,%rax,8)\nadd $0x8,%rbx\ncmp %r13,%rbx\njne 13f8 \nmov 0x8(%rsp),%rax\nmov %r12d,(%rax)\nadd $0x18,%rsp\nlea 0x2c11(%rip),%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw 0x0(%rax,%rax,1)\nxor %r12d,%r12d\njmp 141c \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rcx\ntest esi, esi\njle short loc_1450\nmovsxd rsi, esi\nmovsxd rbp, edx\nmov rbx, rdi\nxor r12d, r12d\nlea r13, [rdi+rsi*8]\nlea r15, result_1\nnop word ptr [rax+rax+00h]\nloc_1408:\nmov r14, [rbx]\nmov rdi, r14; s\ncall _strlen\ncmp rax, rbp\njnz short loc_1423\nmovsxd rax, r12d\nadd r12d, 1\nmov [r15+rax*8], r14\nloc_1423:\nadd rbx, 8\ncmp rbx, r13\njnz short loc_1408\nloc_142C:\nmov rax, [rsp+48h+var_40]\nmov [rax], r12d\nadd rsp, 18h\nmov rax, r15\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1450:\nxor r12d, r12d\nlea r15, result_1\njmp short loc_142C", + "ida_pseudo": "_QWORD *__fastcall func0(const char **a1, int a2, int a3, _DWORD *a4)\n{\n __int64 v4; // rbp\n const char **v5; // rbx\n int v6; // r12d\n const char *v7; // r14\n __int64 v8; // rax\n\n if ( a2 <= 0 )\n {\n v6 = 0;\n }\n else\n {\n v4 = a3;\n v5 = a1;\n v6 = 0;\n do\n {\n v7 = *v5;\n if ( strlen(*v5) == v4 )\n {\n v8 = v6++;\n result_1[v8] = v7;\n }\n ++v5;\n }\n while ( v5 != &a1[a2] );\n }\n *a4 = v6;\n return result_1;\n}", + "ida_strip_asm": "sub_13D0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rcx\ntest esi, esi\njle short loc_1450\nmovsxd rsi, esi\nmovsxd rbp, edx\nmov rbx, rdi\nxor r12d, r12d\nlea r13, [rdi+rsi*8]\nlea r15, unk_4040\nnop word ptr [rax+rax+00h]\nloc_1408:\nmov r14, [rbx]\nmov rdi, r14; s\ncall _strlen\ncmp rax, rbp\njnz short loc_1423\nmovsxd rax, r12d\nadd r12d, 1\nmov [r15+rax*8], r14\nloc_1423:\nadd rbx, 8\ncmp rbx, r13\njnz short loc_1408\nloc_142C:\nmov rax, [rsp+48h+var_40]\nmov [rax], r12d\nadd rsp, 18h\nmov rax, r15\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1450:\nxor r12d, r12d\nlea r15, unk_4040\njmp short loc_142C", + "ida_strip_pseudo": "_QWORD *__fastcall sub_13D0(const char **a1, int a2, int a3, _DWORD *a4)\n{\n __int64 v4; // rbp\n const char **v5; // rbx\n int v6; // r12d\n const char *v7; // r14\n __int64 v8; // rax\n\n if ( a2 <= 0 )\n {\n v6 = 0;\n }\n else\n {\n v4 = a3;\n v5 = a1;\n v6 = 0;\n do\n {\n v7 = *v5;\n if ( strlen(*v5) == v4 )\n {\n v8 = v6++;\n qword_4040[v8] = v7;\n }\n ++v5;\n }\n while ( v5 != &a1[a2] );\n }\n *a4 = v6;\n return qword_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_13D0(const char **a1, int a2, int a3, uint32_t *a4) {\n long long v4;\n const char **v5;\n int v6;\n const char *v7;\n long long v8;\n if (a2 <= 0) {\n v6 = 0;\n } else {\n v4 = a3;\n v5 = a1;\n v6 = 0;\n do {\n v7 = *v5;\n if (strlen(*v5) == v4) {\n v8 = v6++;\n qword_4040[v8] = v7;\n }\n ++v5;\n } while (v5 != &a1[a2]);\n }\n *a4 = v6;\n return qword_4040;\n}", + "ida_pseudo_norm": "uint64_t *func0(const char **a1, int a2, int a3, uint32_t *a4) {\n long long v4;\n const char **v5;\n int v6;\n const char *v7;\n long long v8;\n if (a2 <= 0) {\n v6 = 0;\n } else {\n v4 = a3;\n v5 = a1;\n v6 = 0;\n do {\n v7 = *v5;\n if (strlen(*v5) == v4) {\n v8 = v6++;\n result_1[v8] = v7;\n }\n ++v5;\n } while (v5 != &a1[a2]);\n }\n *a4 = v6;\n return result_1;\n}" + }, + { + "index": 450, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char **func0(char *str[], int n, int l, int *size) {\n static char *result[100];\n int count = 0;\n for (int i = 0; i < n; ++i) {\n if (strlen(str[i]) == l) {\n result[count++] = str[i];\n }\n }\n *size = count;\n return result;\n}", + "test": "int main() {\n\n char *testData1[] = {\"Python\", \"list\", \"exercises\", \"practice\", \"solution\"};\n\n int size;\n\n\n\n char **result = func0(testData1, 5, 8, &size);\n\n assert(size == 2);\n\n assert(strcmp(result[0], \"practice\") == 0);\n\n assert(strcmp(result[1], \"solution\") == 0);\n\n\n\n result = func0(testData1, 5, 6, &size);\n\n assert(size == 1);\n\n assert(strcmp(result[0], \"Python\") == 0);\n\n\n\n result = func0(testData1, 5, 9, &size);\n\n assert(size == 1);\n\n assert(strcmp(result[0], \"exercises\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov %rcx,0x8(%rsp)\ntest %esi,%esi\njle 1450 \nlea -0x1(%rsi),%eax\nmovslq %edx,%rbp\nmov %rdi,%rbx\nxor %r12d,%r12d\nlea 0x8(%rdi,%rax,8),%r13\nlea 0x2c3d(%rip),%r15\nnopl 0x0(%rax,%rax,1)\nmov (%rbx),%r14\nmov %r14,%rdi\ncallq 1070 \ncmp %rbp,%rax\njne 1423 \nmovslq %r12d,%rax\nadd $0x1,%r12d\nmov %r14,(%r15,%rax,8)\nadd $0x8,%rbx\ncmp %r13,%rbx\njne 1408 \nmov 0x8(%rsp),%rax\nmov %r12d,(%rax)\nadd $0x18,%rsp\nlea 0x2c01(%rip),%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw 0x0(%rax,%rax,1)\nxor %r12d,%r12d\njmp 142c \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rcx\ntest esi, esi\njle short loc_1450\nmovsxd rsi, esi\nmovsxd rbp, edx\nmov rbx, rdi\nxor r12d, r12d\nlea r13, [rdi+rsi*8]\nlea r15, result_1\nnop word ptr [rax+rax+00h]\nloc_1408:\nmov r14, [rbx]\nmov rdi, r14; s\ncall _strlen\ncmp rax, rbp\njnz short loc_1423\nmovsxd rax, r12d\nadd r12d, 1\nmov [r15+rax*8], r14\nloc_1423:\nadd rbx, 8\ncmp rbx, r13\njnz short loc_1408\nloc_142C:\nmov rax, [rsp+48h+var_40]\nmov [rax], r12d\nadd rsp, 18h\nmov rax, r15\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1450:\nxor r12d, r12d\nlea r15, result_1\njmp short loc_142C", + "ida_pseudo": "_QWORD *__fastcall func0(const char **a1, int a2, int a3, _DWORD *a4)\n{\n __int64 v4; // rbp\n const char **v5; // rbx\n int v6; // r12d\n const char *v7; // r14\n __int64 v8; // rax\n\n if ( a2 <= 0 )\n {\n v6 = 0;\n }\n else\n {\n v4 = a3;\n v5 = a1;\n v6 = 0;\n do\n {\n v7 = *v5;\n if ( strlen(*v5) == v4 )\n {\n v8 = v6++;\n result_1[v8] = v7;\n }\n ++v5;\n }\n while ( v5 != &a1[a2] );\n }\n *a4 = v6;\n return result_1;\n}", + "ida_strip_asm": "sub_13D0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rcx\ntest esi, esi\njle short loc_1450\nmovsxd rsi, esi\nmovsxd rbp, edx\nmov rbx, rdi\nxor r12d, r12d\nlea r13, [rdi+rsi*8]\nlea r15, unk_4040\nnop word ptr [rax+rax+00h]\nloc_1408:\nmov r14, [rbx]\nmov rdi, r14; s\ncall _strlen\ncmp rax, rbp\njnz short loc_1423\nmovsxd rax, r12d\nadd r12d, 1\nmov [r15+rax*8], r14\nloc_1423:\nadd rbx, 8\ncmp rbx, r13\njnz short loc_1408\nloc_142C:\nmov rax, [rsp+48h+var_40]\nmov [rax], r12d\nadd rsp, 18h\nmov rax, r15\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1450:\nxor r12d, r12d\nlea r15, unk_4040\njmp short loc_142C", + "ida_strip_pseudo": "_QWORD *__fastcall sub_13D0(const char **a1, int a2, int a3, _DWORD *a4)\n{\n __int64 v4; // rbp\n const char **v5; // rbx\n int v6; // r12d\n const char *v7; // r14\n __int64 v8; // rax\n\n if ( a2 <= 0 )\n {\n v6 = 0;\n }\n else\n {\n v4 = a3;\n v5 = a1;\n v6 = 0;\n do\n {\n v7 = *v5;\n if ( strlen(*v5) == v4 )\n {\n v8 = v6++;\n qword_4040[v8] = v7;\n }\n ++v5;\n }\n while ( v5 != &a1[a2] );\n }\n *a4 = v6;\n return qword_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_13D0(const char **a1, int a2, int a3, uint32_t *a4) {\n long long v4;\n const char **v5;\n int v6;\n const char *v7;\n long long v8;\n if (a2 <= 0) {\n v6 = 0;\n } else {\n v4 = a3;\n v5 = a1;\n v6 = 0;\n do {\n v7 = *v5;\n if (strlen(*v5) == v4) {\n v8 = v6++;\n qword_4040[v8] = v7;\n }\n ++v5;\n } while (v5 != &a1[a2]);\n }\n *a4 = v6;\n return qword_4040;\n}", + "ida_pseudo_norm": "uint64_t *func0(const char **a1, int a2, int a3, uint32_t *a4) {\n long long v4;\n const char **v5;\n int v6;\n const char *v7;\n long long v8;\n if (a2 <= 0) {\n v6 = 0;\n } else {\n v4 = a3;\n v5 = a1;\n v6 = 0;\n do {\n v7 = *v5;\n if (strlen(*v5) == v4) {\n v8 = v6++;\n result_1[v8] = v7;\n }\n ++v5;\n } while (v5 != &a1[a2]);\n }\n *a4 = v6;\n return result_1;\n}" + }, + { + "index": 451, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* text1) {\n int i = 0, j = 0;\n while (text1[i]) {\n if (!isspace((unsigned char)text1[i])) {\n text1[j++] = text1[i];\n }\n i++;\n }\n text1[j] = '\\0';\n return text1;\n}", + "test": "int main() {\n\n char text1[] = \" Google Flutter \";\n\n char text2[] = \" Google Dart \";\n\n char text3[] = \" iOS Swift \";\n\n\n\n assert(strcmp(func0(text1), \"GoogleFlutter\") == 0);\n\n assert(strcmp(func0(text2), \"GoogleDart\") == 0);\n\n assert(strcmp(func0(text3), \"iOSSwift\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 1223 \ncallq 10b0 <__ctype_b_loc@plt>\nmov (%rax),%rax\nmov -0x8(%rbp),%edx\nmovslq %edx,%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rdx),%edx\nmovzbl %dl,%edx\nadd %rdx,%rdx\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x2000,%eax\ntest %eax,%eax\njne 121f \nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x4(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x4(%rbp)\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmovzbl (%rcx),%eax\nmov %al,(%rdx)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 11c9 \nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovb $0x0,(%rax)\nmov -0x18(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_1223\nloc_11C9:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_8]\nmovsxd rcx, edx\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovzx edx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 2000h\ntest eax, eax\njnz short loc_121F\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_4]\nlea edx, [rax+1]\nmov [rbp+var_4], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmovzx eax, byte ptr [rcx]\nmov [rdx], al\nloc_121F:\nadd [rbp+var_8], 1\nloc_1223:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_11C9\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+var_18]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1)\n{\n int v1; // eax\n int v3; // [rsp+18h] [rbp-8h]\n int v4; // [rsp+1Ch] [rbp-4h]\n\n v3 = 0;\n v4 = 0;\n while ( *(_BYTE *)(v3 + a1) )\n {\n if ( ((*__ctype_b_loc())[*(unsigned __int8 *)(v3 + a1)] & 0x2000) == 0 )\n {\n v1 = v4++;\n *(_BYTE *)(a1 + v1) = *(_BYTE *)(v3 + a1);\n }\n ++v3;\n }\n *(_BYTE *)(v4 + a1) = 0;\n return a1;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_1223\nloc_11C9:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_8]\nmovsxd rcx, edx\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovzx edx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 2000h\ntest eax, eax\njnz short loc_121F\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_4]\nlea edx, [rax+1]\nmov [rbp+var_4], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmovzx eax, byte ptr [rcx]\nmov [rdx], al\nloc_121F:\nadd [rbp+var_8], 1\nloc_1223:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_11C9\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+var_18]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(__int64 a1)\n{\n int v1; // eax\n int v3; // [rsp+18h] [rbp-8h]\n int v4; // [rsp+1Ch] [rbp-4h]\n\n v3 = 0;\n v4 = 0;\n while ( *(_BYTE *)(v3 + a1) )\n {\n if ( ((*__ctype_b_loc())[*(unsigned __int8 *)(v3 + a1)] & 0x2000) == 0 )\n {\n v1 = v4++;\n *(_BYTE *)(a1 + v1) = *(_BYTE *)(v3 + a1);\n }\n ++v3;\n }\n *(_BYTE *)(v4 + a1) = 0;\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(long long a1) {\n int v1;\n int v3;\n int v4;\n v3 = 0;\n v4 = 0;\n while (*(uint8_t *)(v3 + a1)) {\n if (((*__ctype_b_loc())[*(unsigned char *)(v3 + a1)] & 8192) == 0) {\n v1 = v4++;\n *(uint8_t *)(a1 + v1) = *(uint8_t *)(v3 + a1);\n }\n ++v3;\n }\n *(uint8_t *)(v4 + a1) = 0;\n return a1;\n}", + "ida_pseudo_norm": "long long func0(long long a1) {\n int v1;\n int v3;\n int v4;\n v3 = 0;\n v4 = 0;\n while (*(uint8_t *)(v3 + a1)) {\n if (((*__ctype_b_loc())[*(unsigned char *)(v3 + a1)] & 8192) == 0) {\n v1 = v4++;\n *(uint8_t *)(a1 + v1) = *(uint8_t *)(v3 + a1);\n }\n ++v3;\n }\n *(uint8_t *)(v4 + a1) = 0;\n return a1;\n}" + }, + { + "index": 451, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* text1) {\n int i = 0, j = 0;\n while (text1[i]) {\n if (!isspace((unsigned char)text1[i])) {\n text1[j++] = text1[i];\n }\n i++;\n }\n text1[j] = '\\0';\n return text1;\n}", + "test": "int main() {\n\n char text1[] = \" Google Flutter \";\n\n char text2[] = \" Google Dart \";\n\n char text3[] = \" iOS Swift \";\n\n\n\n assert(strcmp(func0(text1), \"GoogleFlutter\") == 0);\n\n assert(strcmp(func0(text2), \"GoogleDart\") == 0);\n\n assert(strcmp(func0(text3), \"iOSSwift\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbp\nmovzbl (%rdi),%ebx\ntest %bl,%bl\nje 11d2 \ncallq 1090 <__ctype_b_loc@plt>\nlea 0x1(%rbp),%rcx\nmov $0x0,%edi\njmp 11b9 \nadd $0x1,%rcx\nmovzbl -0x1(%rcx),%ebx\ntest %bl,%bl\nje 11d7 \nmovzbl %bl,%edx\nmov (%rax),%rsi\ntestb $0x20,0x1(%rsi,%rdx,2)\njne 11ad \nmovslq %edi,%rdx\nmov %bl,0x0(%rbp,%rdx,1)\nlea 0x1(%rdi),%edi\njmp 11ad \nmov $0x0,%edi\nmovslq %edi,%rdi\nmovb $0x0,0x0(%rbp,%rdi,1)\nmov %rbp,%rax\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_11F2\ncall ___ctype_b_loc\nlea rcx, [rbp+1]\nmov edi, 0\njmp short loc_11D9\nloc_11CD:\nadd rcx, 1\nmovzx ebx, byte ptr [rcx-1]\ntest bl, bl\njz short loc_11F7\nloc_11D9:\nmovzx edx, bl\nmov rsi, [rax]\ntest byte ptr [rsi+rdx*2+1], 20h\njnz short loc_11CD\nmovsxd rdx, edi\nmov [rbp+rdx+0], bl\nlea edi, [rdi+1]\njmp short loc_11CD\nloc_11F2:\nmov edi, 0\nloc_11F7:\nmovsxd rdi, edi\nmov byte ptr [rbp+rdi+0], 0\nmov rax, rbp\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_pseudo": "unsigned __int8 *__fastcall func0(unsigned __int8 *a1)\n{\n unsigned __int8 v2; // bl\n const unsigned __int16 **v3; // rax\n unsigned __int8 *v4; // rcx\n int v5; // edi\n\n v2 = *a1;\n if ( *a1 )\n {\n v3 = __ctype_b_loc();\n v4 = a1 + 1;\n v5 = 0;\n do\n {\n if ( ((*v3)[v2] & 0x2000) == 0 )\n a1[v5++] = v2;\n v2 = *v4++;\n }\n while ( v2 );\n }\n else\n {\n v5 = 0;\n }\n a1[v5] = 0;\n return a1;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_11F2\ncall ___ctype_b_loc\nlea rcx, [rbp+1]\nmov edi, 0\njmp short loc_11D9\nloc_11CD:\nadd rcx, 1\nmovzx ebx, byte ptr [rcx-1]\ntest bl, bl\njz short loc_11F7\nloc_11D9:\nmovzx edx, bl\nmov rsi, [rax]\ntest byte ptr [rsi+rdx*2+1], 20h\njnz short loc_11CD\nmovsxd rdx, edi\nmov [rbp+rdx+0], bl\nlea edi, [rdi+1]\njmp short loc_11CD\nloc_11F2:\nmov edi, 0\nloc_11F7:\nmovsxd rdi, edi\nmov byte ptr [rbp+rdi+0], 0\nmov rax, rbp\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "unsigned __int8 *__fastcall sub_11A9(unsigned __int8 *a1)\n{\n unsigned __int8 v2; // bl\n const unsigned __int16 **v3; // rax\n unsigned __int8 *v4; // rcx\n int v5; // edi\n\n v2 = *a1;\n if ( *a1 )\n {\n v3 = __ctype_b_loc();\n v4 = a1 + 1;\n v5 = 0;\n do\n {\n if ( ((*v3)[v2] & 0x2000) == 0 )\n a1[v5++] = v2;\n v2 = *v4++;\n }\n while ( v2 );\n }\n else\n {\n v5 = 0;\n }\n a1[v5] = 0;\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned char *sub_11A9(unsigned char *a1) {\n unsigned char v2;\n const unsigned short **v3;\n unsigned char *v4;\n int v5;\n v2 = *a1;\n if (*a1) {\n v3 = __ctype_b_loc();\n v4 = a1 + 1;\n v5 = 0;\n do {\n if (((*v3)[v2] & 8192) == 0) a1[v5++] = v2;\n v2 = *v4++;\n } while (v2);\n } else {\n v5 = 0;\n }\n a1[v5] = 0;\n return a1;\n}", + "ida_pseudo_norm": "unsigned char *func0(unsigned char *a1) {\n unsigned char v2;\n const unsigned short **v3;\n unsigned char *v4;\n int v5;\n v2 = *a1;\n if (*a1) {\n v3 = __ctype_b_loc();\n v4 = a1 + 1;\n v5 = 0;\n do {\n if (((*v3)[v2] & 8192) == 0) a1[v5++] = v2;\n v2 = *v4++;\n } while (v2);\n } else {\n v5 = 0;\n }\n a1[v5] = 0;\n return a1;\n}" + }, + { + "index": 451, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* text1) {\n int i = 0, j = 0;\n while (text1[i]) {\n if (!isspace((unsigned char)text1[i])) {\n text1[j++] = text1[i];\n }\n i++;\n }\n text1[j] = '\\0';\n return text1;\n}", + "test": "int main() {\n\n char text1[] = \" Google Flutter \";\n\n char text2[] = \" Google Dart \";\n\n char text3[] = \" iOS Swift \";\n\n\n\n assert(strcmp(func0(text1), \"GoogleFlutter\") == 0);\n\n assert(strcmp(func0(text2), \"GoogleDart\") == 0);\n\n assert(strcmp(func0(text3), \"iOSSwift\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %rdi,%r12\npush %rbx\nsub $0x8,%rsp\nmovzbl (%rdi),%ebx\ntest %bl,%bl\nje 1340 \ncallq 1090 <__ctype_b_loc@plt>\nlea 0x1(%r12),%rcx\nxor %r9d,%r9d\nxor %edi,%edi\nnopl 0x0(%rax)\nmov (%rax),%r8\nmovzbl %bl,%edx\nlea (%r12,%rdi,1),%rsi\ntestb $0x20,0x1(%r8,%rdx,2)\njne 1327 \nadd $0x1,%r9d\nmov %bl,(%rsi)\nmovslq %r9d,%rdi\nlea (%r12,%rdi,1),%rsi\nmovzbl (%rcx),%ebx\nadd $0x1,%rcx\ntest %bl,%bl\njne 1308 \nmovb $0x0,(%rsi)\nadd $0x8,%rsp\nmov %r12,%rax\npop %rbx\npop %r12\nretq\nmov %rdi,%rsi\nmov %r12,%rax\nmovb $0x0,(%rsi)\nadd $0x8,%rsp\npop %rbx\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 8\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_1340\ncall ___ctype_b_loc\nlea rcx, [rbp+1]\nxor esi, esi\nnop\nloc_1300:\nmov r8, [rax]\nmovzx edx, bl\ntest byte ptr [r8+rdx*2+1], 20h\njnz short loc_1318\nmovsxd rdx, esi\nadd esi, 1\nmov [rbp+rdx+0], bl\nloc_1318:\nmovzx ebx, byte ptr [rcx]\nadd rcx, 1\ntest bl, bl\njnz short loc_1300\nmovsxd rsi, esi\nmov rax, rbp\nadd rsi, rbp\nmov byte ptr [rsi], 0\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1340:\nmov rsi, rdi\nmov rax, rbp\nmov byte ptr [rsi], 0\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_pseudo": "unsigned __int8 *__fastcall func0(unsigned __int8 *a1)\n{\n unsigned __int8 v1; // bl\n const unsigned __int16 **v2; // rax\n unsigned __int8 *v3; // rcx\n int v4; // esi\n __int64 v5; // rdx\n unsigned __int8 *result; // rax\n\n v1 = *a1;\n if ( *a1 )\n {\n v2 = __ctype_b_loc();\n v3 = a1 + 1;\n v4 = 0;\n do\n {\n if ( ((*v2)[v1] & 0x2000) == 0 )\n {\n v5 = v4++;\n a1[v5] = v1;\n }\n v1 = *v3++;\n }\n while ( v1 );\n result = a1;\n a1[v4] = 0;\n }\n else\n {\n result = a1;\n *a1 = 0;\n }\n return result;\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 8\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_1340\ncall ___ctype_b_loc\nlea rcx, [rbp+1]\nxor esi, esi\nnop\nloc_1300:\nmov r8, [rax]\nmovzx edx, bl\ntest byte ptr [r8+rdx*2+1], 20h\njnz short loc_1318\nmovsxd rdx, esi\nadd esi, 1\nmov [rbp+rdx+0], bl\nloc_1318:\nmovzx ebx, byte ptr [rcx]\nadd rcx, 1\ntest bl, bl\njnz short loc_1300\nmovsxd rsi, esi\nmov rax, rbp\nadd rsi, rbp\nmov byte ptr [rsi], 0\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1340:\nmov rsi, rdi\nmov rax, rbp\nmov byte ptr [rsi], 0\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "unsigned __int8 *__fastcall sub_12E0(unsigned __int8 *a1)\n{\n unsigned __int8 v1; // bl\n const unsigned __int16 **v2; // rax\n unsigned __int8 *v3; // rcx\n int v4; // esi\n __int64 v5; // rdx\n unsigned __int8 *result; // rax\n\n v1 = *a1;\n if ( *a1 )\n {\n v2 = __ctype_b_loc();\n v3 = a1 + 1;\n v4 = 0;\n do\n {\n if ( ((*v2)[v1] & 0x2000) == 0 )\n {\n v5 = v4++;\n a1[v5] = v1;\n }\n v1 = *v3++;\n }\n while ( v1 );\n result = a1;\n a1[v4] = 0;\n }\n else\n {\n result = a1;\n *a1 = 0;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned char *sub_12E0(unsigned char *a1) {\n unsigned char v1;\n const unsigned short **v2;\n unsigned char *v3;\n int v4;\n long long v5;\n unsigned char *result;\n v1 = *a1;\n if (*a1) {\n v2 = __ctype_b_loc();\n v3 = a1 + 1;\n v4 = 0;\n do {\n if (((*v2)[v1] & 8192) == 0) {\n v5 = v4++;\n a1[v5] = v1;\n }\n v1 = *v3++;\n } while (v1);\n result = a1;\n a1[v4] = 0;\n } else {\n result = a1;\n *a1 = 0;\n }\n return result;\n}", + "ida_pseudo_norm": "unsigned char *func0(unsigned char *a1) {\n unsigned char v1;\n const unsigned short **v2;\n unsigned char *v3;\n int v4;\n long long v5;\n unsigned char *result;\n v1 = *a1;\n if (*a1) {\n v2 = __ctype_b_loc();\n v3 = a1 + 1;\n v4 = 0;\n do {\n if (((*v2)[v1] & 8192) == 0) {\n v5 = v4++;\n a1[v5] = v1;\n }\n v1 = *v3++;\n } while (v1);\n result = a1;\n a1[v4] = 0;\n } else {\n result = a1;\n *a1 = 0;\n }\n return result;\n}" + }, + { + "index": 451, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* text1) {\n int i = 0, j = 0;\n while (text1[i]) {\n if (!isspace((unsigned char)text1[i])) {\n text1[j++] = text1[i];\n }\n i++;\n }\n text1[j] = '\\0';\n return text1;\n}", + "test": "int main() {\n\n char text1[] = \" Google Flutter \";\n\n char text2[] = \" Google Dart \";\n\n char text3[] = \" iOS Swift \";\n\n\n\n assert(strcmp(func0(text1), \"GoogleFlutter\") == 0);\n\n assert(strcmp(func0(text2), \"GoogleDart\") == 0);\n\n assert(strcmp(func0(text3), \"iOSSwift\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %rdi,%r12\npush %rbx\nsub $0x8,%rsp\nmovzbl (%rdi),%ebx\ntest %bl,%bl\nje 1358 \ncallq 1090 <__ctype_b_loc@plt>\nlea 0x1(%r12),%rdx\nxor %r8d,%r8d\nxor %esi,%esi\njmp 1329 \nnopw %cs:0x0(%rax,%rax,1)\nadd $0x1,%rdx\nmov %bl,(%rcx)\nadd $0x1,%r8d\nmovzbl -0x1(%rdx),%ebx\nmovslq %r8d,%rsi\nlea (%r12,%rsi,1),%rcx\ntest %bl,%bl\nje 1346 \nmov (%rax),%r9\nmovzbl %bl,%edi\nlea (%r12,%rsi,1),%rcx\ntestb $0x20,0x1(%r9,%rdi,2)\nje 1310 \nmovzbl (%rdx),%ebx\nadd $0x1,%rdx\ntest %bl,%bl\njne 132c \nmovb $0x0,(%rcx)\nadd $0x8,%rsp\nmov %r12,%rax\npop %rbx\npop %r12\nretq\nnopl 0x0(%rax)\nmov %rdi,%rcx\nmov %r12,%rax\nmovb $0x0,(%rcx)\nadd $0x8,%rsp\npop %rbx\npop %r12\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 8\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_1350\ncall ___ctype_b_loc\nlea rcx, [rbp+1]\nxor edx, edx\njmp short loc_131E\nloc_1308:\nadd rcx, 1\nmov [rbp+rdx+0], bl\nlea esi, [rdx+1]\nmovzx ebx, byte ptr [rcx-1]\nmovsxd rdx, esi\ntest bl, bl\njz short loc_1337\nloc_131E:\nmov r8, [rax]\nloc_1321:\nmovzx esi, bl\ntest byte ptr [r8+rsi*2+1], 20h\njz short loc_1308\nmovzx ebx, byte ptr [rcx]\nadd rcx, 1\ntest bl, bl\njnz short loc_1321\nloc_1337:\nadd rdx, rbp\nmov rax, rbp\nmov byte ptr [rdx], 0\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1350:\nmov rdx, rdi\nmov rax, rbp\nmov byte ptr [rdx], 0\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_pseudo": "unsigned __int8 *__fastcall func0(unsigned __int8 *a1)\n{\n unsigned __int8 v1; // bl\n const unsigned __int16 **v2; // rax\n unsigned __int8 *v3; // rcx\n __int64 v4; // rdx\n unsigned __int8 *result; // rax\n\n v1 = *a1;\n if ( *a1 )\n {\n v2 = __ctype_b_loc();\n v3 = a1 + 1;\n v4 = 0LL;\n do\n {\n while ( ((*v2)[v1] & 0x2000) == 0 )\n {\n ++v3;\n a1[v4] = v1;\n v1 = *(v3 - 1);\n v4 = (int)v4 + 1;\n if ( !v1 )\n goto LABEL_6;\n }\n v1 = *v3++;\n }\n while ( v1 );\nLABEL_6:\n result = a1;\n a1[v4] = 0;\n }\n else\n {\n result = a1;\n *a1 = 0;\n }\n return result;\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 8\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_1350\ncall ___ctype_b_loc\nlea rcx, [rbp+1]\nxor edx, edx\njmp short loc_131E\nloc_1308:\nadd rcx, 1\nmov [rbp+rdx+0], bl\nlea esi, [rdx+1]\nmovzx ebx, byte ptr [rcx-1]\nmovsxd rdx, esi\ntest bl, bl\njz short loc_1337\nloc_131E:\nmov r8, [rax]\nloc_1321:\nmovzx esi, bl\ntest byte ptr [r8+rsi*2+1], 20h\njz short loc_1308\nmovzx ebx, byte ptr [rcx]\nadd rcx, 1\ntest bl, bl\njnz short loc_1321\nloc_1337:\nadd rdx, rbp\nmov rax, rbp\nmov byte ptr [rdx], 0\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1350:\nmov rdx, rdi\nmov rax, rbp\nmov byte ptr [rdx], 0\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "unsigned __int8 *__fastcall sub_12E0(unsigned __int8 *a1)\n{\n unsigned __int8 v1; // bl\n const unsigned __int16 **v2; // rax\n unsigned __int8 *v3; // rcx\n __int64 v4; // rdx\n unsigned __int8 *result; // rax\n\n v1 = *a1;\n if ( *a1 )\n {\n v2 = __ctype_b_loc();\n v3 = a1 + 1;\n v4 = 0LL;\n do\n {\n while ( ((*v2)[v1] & 0x2000) == 0 )\n {\n ++v3;\n a1[v4] = v1;\n v1 = *(v3 - 1);\n v4 = (int)v4 + 1;\n if ( !v1 )\n goto LABEL_6;\n }\n v1 = *v3++;\n }\n while ( v1 );\nLABEL_6:\n result = a1;\n a1[v4] = 0;\n }\n else\n {\n result = a1;\n *a1 = 0;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned char *sub_12E0(unsigned char *a1) {\n unsigned char v1;\n const unsigned short **v2;\n unsigned char *v3;\n long long v4;\n unsigned char *result;\n v1 = *a1;\n if (*a1) {\n v2 = __ctype_b_loc();\n v3 = a1 + 1;\n v4 = 0LL;\n do {\n while (((*v2)[v1] & 8192) == 0) {\n ++v3;\n a1[v4] = v1;\n v1 = *(v3 - 1);\n v4 = (int)v4 + 1;\n if (!v1) goto LABEL_6;\n }\n v1 = *v3++;\n } while (v1);\n LABEL_6:\n result = a1;\n a1[v4] = 0;\n } else {\n result = a1;\n *a1 = 0;\n }\n return result;\n}", + "ida_pseudo_norm": "unsigned char *func0(unsigned char *a1) {\n unsigned char v1;\n const unsigned short **v2;\n unsigned char *v3;\n long long v4;\n unsigned char *result;\n v1 = *a1;\n if (*a1) {\n v2 = __ctype_b_loc();\n v3 = a1 + 1;\n v4 = 0LL;\n do {\n while (((*v2)[v1] & 8192) == 0) {\n ++v3;\n a1[v4] = v1;\n v1 = *(v3 - 1);\n v4 = (int)v4 + 1;\n if (!v1) goto LABEL_6;\n }\n v1 = *v3++;\n } while (v1);\n LABEL_6:\n result = a1;\n a1[v4] = 0;\n } else {\n result = a1;\n *a1 = 0;\n }\n return result;\n}" + }, + { + "index": 452, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int actual_cost, int sale_amount) {\n if (sale_amount > actual_cost) {\n int amount = sale_amount - actual_cost;\n return amount;\n } else {\n return 0;\n }\n}", + "test": "int main() {\n\n assert(func0(1500, 1200) == 0);\n\n assert(func0(100, 200) == 100);\n\n assert(func0(2000, 5000) == 3000);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov -0x18(%rbp),%eax\ncmp -0x14(%rbp),%eax\njle 116d \nmov -0x18(%rbp),%eax\nsub -0x14(%rbp),%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\njmp 1172 \nmov $0x0,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_14]\njle short loc_116D\nmov eax, [rbp+var_18]\nsub eax, [rbp+var_14]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\njmp short loc_1172\nloc_116D:\nmov eax, 0\nloc_1172:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n if ( a2 <= a1 )\n return 0LL;\n else\n return (unsigned int)(a2 - a1);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_14]\njle short loc_116D\nmov eax, [rbp+var_18]\nsub eax, [rbp+var_14]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\njmp short loc_1172\nloc_116D:\nmov eax, 0\nloc_1172:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2)\n{\n if ( a2 <= a1 )\n return 0LL;\n else\n return (unsigned int)(a2 - a1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2) {\n if (a2 <= a1)\n return 0LL;\n else\n return (unsigned int)(a2 - a1);\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n if (a2 <= a1)\n return 0LL;\n else\n return (unsigned int)(a2 - a1);\n}" + }, + { + "index": 453, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n % 2 != 0) {\n return 0;\n }\n int res = 1;\n for (int i = 2; i <= (int)(sqrt(n)) + 1; i++) {\n int count = 0;\n int curr_sum = 1;\n int curr_term = 1;\n while (n % i == 0) {\n count += 1;\n n = n / i;\n if (i == 2 && count == 1) {\n curr_sum = 0;\n }\n curr_term = curr_term * i;\n curr_sum = curr_sum + curr_term;\n }\n res = res * curr_sum;\n }\n if (n >= 2) {\n res = res * (1 + n);\n }\n return res;\n}", + "test": "int main() {\n\n assert(func0(18) == 26);\n\n assert(func0(30) == 48);\n\n assert(func0(6) == 8);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %edi,-0x24(%rbp)\nmov -0x24(%rbp),%eax\nand $0x1,%eax\ntest %eax,%eax\nje 118c \nmov $0x0,%eax\njmpq 122d \nmovl $0x1,-0x14(%rbp)\nmovl $0x2,-0x10(%rbp)\njmp 11ff \nmovl $0x0,-0xc(%rbp)\nmovl $0x1,-0x8(%rbp)\nmovl $0x1,-0x4(%rbp)\njmp 11e4 \naddl $0x1,-0xc(%rbp)\nmov -0x24(%rbp),%eax\ncltd\nidivl -0x10(%rbp)\nmov %eax,-0x24(%rbp)\ncmpl $0x2,-0x10(%rbp)\njne 11d4 \ncmpl $0x1,-0xc(%rbp)\njne 11d4 \nmovl $0x0,-0x8(%rbp)\nmov -0x4(%rbp),%eax\nimul -0x10(%rbp),%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nadd %eax,-0x8(%rbp)\nmov -0x24(%rbp),%eax\ncltd\nidivl -0x10(%rbp)\nmov %edx,%eax\ntest %eax,%eax\nje 11b3 \nmov -0x14(%rbp),%eax\nimul -0x8(%rbp),%eax\nmov %eax,-0x14(%rbp)\naddl $0x1,-0x10(%rbp)\ncvtsi2sdl -0x24(%rbp),%xmm0\ncallq 1070 \ncvttsd2si %xmm0,%eax\nadd $0x1,%eax\ncmp %eax,-0x10(%rbp)\njle 119c \ncmpl $0x1,-0x24(%rbp)\njle 122a \nmov -0x24(%rbp),%eax\nlea 0x1(%rax),%edx\nmov -0x14(%rbp),%eax\nimul %edx,%eax\nmov %eax,-0x14(%rbp)\nmov -0x14(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_24], edi\nmov eax, [rbp+var_24]\nand eax, 1\ntest eax, eax\njz short loc_118C\nmov eax, 0\njmp locret_123F\nloc_118C:\nmov [rbp+var_14], 1\nmov [rbp+var_10], 2\njmp short loc_11FF\nloc_119C:\nmov [rbp+var_C], 0\nmov [rbp+var_8], 1\nmov [rbp+var_4], 1\njmp short loc_11E4\nloc_11B3:\nadd [rbp+var_C], 1\nmov eax, [rbp+var_24]\ncdq\nidiv [rbp+var_10]\nmov [rbp+var_24], eax\ncmp [rbp+var_10], 2\njnz short loc_11D4\ncmp [rbp+var_C], 1\njnz short loc_11D4\nmov [rbp+var_8], 0\nloc_11D4:\nmov eax, [rbp+var_4]\nimul eax, [rbp+var_10]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\nadd [rbp+var_8], eax\nloc_11E4:\nmov eax, [rbp+var_24]\ncdq\nidiv [rbp+var_10]\nmov eax, edx\ntest eax, eax\njz short loc_11B3\nmov eax, [rbp+var_14]\nimul eax, [rbp+var_8]\nmov [rbp+var_14], eax\nadd [rbp+var_10], 1\nloc_11FF:\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_24]\nmovq rax, xmm1\nmovq xmm0, rax; x\ncall _sqrt\ncvttsd2si eax, xmm0\nadd eax, 1\ncmp [rbp+var_10], eax\njle loc_119C\ncmp [rbp+var_24], 1\njle short loc_123C\nmov eax, [rbp+var_24]\nlea edx, [rax+1]\nmov eax, [rbp+var_14]\nimul eax, edx\nmov [rbp+var_14], eax\nloc_123C:\nmov eax, [rbp+var_14]\nlocret_123F:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v2; // [rsp+Ch] [rbp-24h]\n unsigned int v3; // [rsp+1Ch] [rbp-14h]\n int i; // [rsp+20h] [rbp-10h]\n int v5; // [rsp+24h] [rbp-Ch]\n int v6; // [rsp+28h] [rbp-8h]\n int v7; // [rsp+2Ch] [rbp-4h]\n\n v2 = a1;\n if ( (a1 & 1) != 0 )\n return 0LL;\n v3 = 1;\n for ( i = 2; i <= (int)sqrt((double)v2) + 1; ++i )\n {\n v5 = 0;\n v6 = 1;\n v7 = 1;\n while ( !(v2 % i) )\n {\n ++v5;\n v2 /= i;\n if ( i == 2 && v5 == 1 )\n v6 = 0;\n v7 *= i;\n v6 += v7;\n }\n v3 *= v6;\n }\n if ( v2 > 1 )\n v3 *= v2 + 1;\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_24], edi\nmov eax, [rbp+var_24]\nand eax, 1\ntest eax, eax\njz short loc_118C\nmov eax, 0\njmp locret_123F\nloc_118C:\nmov [rbp+var_14], 1\nmov [rbp+var_10], 2\njmp short loc_11FF\nloc_119C:\nmov [rbp+var_C], 0\nmov [rbp+var_8], 1\nmov [rbp+var_4], 1\njmp short loc_11E4\nloc_11B3:\nadd [rbp+var_C], 1\nmov eax, [rbp+var_24]\ncdq\nidiv [rbp+var_10]\nmov [rbp+var_24], eax\ncmp [rbp+var_10], 2\njnz short loc_11D4\ncmp [rbp+var_C], 1\njnz short loc_11D4\nmov [rbp+var_8], 0\nloc_11D4:\nmov eax, [rbp+var_4]\nimul eax, [rbp+var_10]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\nadd [rbp+var_8], eax\nloc_11E4:\nmov eax, [rbp+var_24]\ncdq\nidiv [rbp+var_10]\nmov eax, edx\ntest eax, eax\njz short loc_11B3\nmov eax, [rbp+var_14]\nimul eax, [rbp+var_8]\nmov [rbp+var_14], eax\nadd [rbp+var_10], 1\nloc_11FF:\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_24]\nmovq rax, xmm1\nmovq xmm0, rax; x\ncall _sqrt\ncvttsd2si eax, xmm0\nadd eax, 1\ncmp [rbp+var_10], eax\njle loc_119C\ncmp [rbp+var_24], 1\njle short loc_123C\nmov eax, [rbp+var_24]\nlea edx, [rax+1]\nmov eax, [rbp+var_14]\nimul eax, edx\nmov [rbp+var_14], eax\nloc_123C:\nmov eax, [rbp+var_14]\nlocret_123F:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n int v2; // [rsp+Ch] [rbp-24h]\n unsigned int v3; // [rsp+1Ch] [rbp-14h]\n int i; // [rsp+20h] [rbp-10h]\n int v5; // [rsp+24h] [rbp-Ch]\n int v6; // [rsp+28h] [rbp-8h]\n int v7; // [rsp+2Ch] [rbp-4h]\n\n v2 = a1;\n if ( (a1 & 1) != 0 )\n return 0LL;\n v3 = 1;\n for ( i = 2; i <= (int)sqrt((double)v2) + 1; ++i )\n {\n v5 = 0;\n v6 = 1;\n v7 = 1;\n while ( !(v2 % i) )\n {\n ++v5;\n v2 /= i;\n if ( i == 2 && v5 == 1 )\n v6 = 0;\n v7 *= i;\n v6 += v7;\n }\n v3 *= v6;\n }\n if ( v2 > 1 )\n v3 *= v2 + 1;\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n int v2;\n unsigned int v3;\n int i;\n int v5;\n int v6;\n int v7;\n v2 = a1;\n if ((a1 & 1) != 0) return 0LL;\n v3 = 1;\n for (i = 2; i <= (int)sqrt((double)v2) + 1; ++i) {\n v5 = 0;\n v6 = 1;\n v7 = 1;\n while (!(v2 % i)) {\n ++v5;\n v2 /= i;\n if (i == 2 && v5 == 1) v6 = 0;\n v7 *= i;\n v6 += v7;\n }\n v3 *= v6;\n }\n if (v2 > 1) v3 *= v2 + 1;\n return v3;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v2;\n unsigned int v3;\n int i;\n int v5;\n int v6;\n int v7;\n v2 = a1;\n if ((a1 & 1) != 0) return 0LL;\n v3 = 1;\n for (i = 2; i <= (int)sqrt((double)v2) + 1; ++i) {\n v5 = 0;\n v6 = 1;\n v7 = 1;\n while (!(v2 % i)) {\n ++v5;\n v2 /= i;\n if (i == 2 && v5 == 1) v6 = 0;\n v7 *= i;\n v6 += v7;\n }\n v3 *= v6;\n }\n if (v2 > 1) v3 *= v2 + 1;\n return v3;\n}" + }, + { + "index": 453, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n % 2 != 0) {\n return 0;\n }\n int res = 1;\n for (int i = 2; i <= (int)(sqrt(n)) + 1; i++) {\n int count = 0;\n int curr_sum = 1;\n int curr_term = 1;\n while (n % i == 0) {\n count += 1;\n n = n / i;\n if (i == 2 && count == 1) {\n curr_sum = 0;\n }\n curr_term = curr_term * i;\n curr_sum = curr_sum + curr_term;\n }\n res = res * curr_sum;\n }\n if (n >= 2) {\n res = res * (1 + n);\n }\n return res;\n}", + "test": "int main() {\n\n assert(func0(18) == 26);\n\n assert(func0(30) == 48);\n\n assert(func0(6) == 8);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nsub $0x10,%rsp\nmov $0x0,%r12d\ntest $0x1,%dil\njne 121b \nmov %edi,%ebp\nmov $0x2,%ebx\nmov $0x1,%r12d\njmp 11c1 \nimul %ebx,%esi\nadd %esi,%ecx\nmov %ebp,%eax\ncltd\nidiv %ebx\ntest %edx,%edx\njne 11ba \nadd $0x1,%edi\nmov %ebp,%eax\ncltd\nidiv %ebx\nmov %eax,%ebp\ncmp $0x2,%ebx\njne 1194 \ncmp $0x1,%edi\ncmove %r8d,%ecx\njmp 1194 \nimul %ecx,%r12d\nadd $0x1,%ebx\npxor %xmm0,%xmm0\ncvtsi2sd %ebp,%xmm0\nmovapd %xmm0,%xmm1\nsqrtsd %xmm1,%xmm1\nmovsd %xmm1,0x8(%rsp)\npxor %xmm2,%xmm2\nucomisd %xmm0,%xmm2\nja 1208 \ncvttsd2si 0x8(%rsp),%eax\nadd $0x1,%eax\ncmp %ebx,%eax\njl 120f \nmov %ebp,%eax\ncltd\nidiv %ebx\nmov %edx,%r8d\nmov %edx,%edi\nmov $0x1,%esi\nmov $0x1,%ecx\ntest %edx,%edx\nje 11a2 \njmp 11ba \ncallq 1070 \njmp 11e1 \ncmp $0x1,%ebp\njle 121b \nadd $0x1,%ebp\nimul %ebp,%r12d\nmov %r12d,%eax\nadd $0x10,%rsp\npop %rbx\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12d, 0\ntest dil, 1\njnz loc_1218\nmov ebp, edi\nmov ebx, 2\nmov r12d, 1\nmov r13d, 0\njmp short loc_11C9\nloc_119C:\nimul esi, ebx\nadd ecx, esi\nmov eax, ebp\ncdq\nidiv ebx\ntest edx, edx\njnz short loc_11C2\nloc_11AA:\nadd edi, 1\nmov eax, ebp\ncdq\nidiv ebx\nmov ebp, eax\ncmp ebx, 2\njnz short loc_119C\ncmp edi, 1\ncmovz ecx, r8d\njmp short loc_119C\nloc_11C2:\nimul r12d, ecx\nadd ebx, 1\nloc_11C9:\npxor xmm0, xmm0\ncvtsi2sd xmm0, ebp; x\nmovq xmm1, r13\nucomisd xmm1, xmm0\nja short loc_1205\nsqrtsd xmm0, xmm0\nloc_11E0:\ncvttsd2si eax, xmm0\nadd eax, 1\ncmp eax, ebx\njl short loc_120C\nmov eax, ebp\ncdq\nidiv ebx\nmov r8d, edx\nmov edi, edx\nmov esi, 1\nmov ecx, 1\ntest edx, edx\njz short loc_11AA\njmp short loc_11C2\nloc_1205:\ncall _sqrt\njmp short loc_11E0\nloc_120C:\ncmp ebp, 1\njle short loc_1218\nadd ebp, 1\nimul r12d, ebp\nloc_1218:\nmov eax, r12d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v1; // r12d\n int v2; // ebp\n int v3; // ebx\n int v4; // esi\n int i; // ecx\n int v6; // edi\n double v7; // xmm0_8\n double v8; // xmm0_8\n int v9; // r8d\n\n v1 = 0;\n if ( (a1 & 1) == 0 )\n {\n v2 = a1;\n v3 = 2;\n v1 = 1;\n while ( 1 )\n {\n v7 = (double)v2;\n v8 = (double)v2 < 0.0 ? sqrt(v7) : sqrt(v7);\n if ( (int)v8 + 1 < v3 )\n break;\n v9 = v2 % v3;\n v6 = v2 % v3;\n v4 = 1;\n for ( i = 1; !(v2 % v3); i += v4 )\n {\n ++v6;\n v2 /= v3;\n if ( v3 == 2 && v6 == 1 )\n i = v9;\n v4 *= v3;\n }\n v1 *= i;\n ++v3;\n }\n if ( v2 > 1 )\n v1 *= v2 + 1;\n }\n return v1;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12d, 0\ntest dil, 1\njnz loc_1218\nmov ebp, edi\nmov ebx, 2\nmov r12d, 1\nmov r13d, 0\njmp short loc_11C9\nloc_119C:\nimul esi, ebx\nadd ecx, esi\nmov eax, ebp\ncdq\nidiv ebx\ntest edx, edx\njnz short loc_11C2\nloc_11AA:\nadd edi, 1\nmov eax, ebp\ncdq\nidiv ebx\nmov ebp, eax\ncmp ebx, 2\njnz short loc_119C\ncmp edi, 1\ncmovz ecx, r8d\njmp short loc_119C\nloc_11C2:\nimul r12d, ecx\nadd ebx, 1\nloc_11C9:\npxor xmm0, xmm0\ncvtsi2sd xmm0, ebp; x\nmovq xmm1, r13\nucomisd xmm1, xmm0\nja short loc_1205\nsqrtsd xmm0, xmm0\nloc_11E0:\ncvttsd2si eax, xmm0\nadd eax, 1\ncmp eax, ebx\njl short loc_120C\nmov eax, ebp\ncdq\nidiv ebx\nmov r8d, edx\nmov edi, edx\nmov esi, 1\nmov ecx, 1\ntest edx, edx\njz short loc_11AA\njmp short loc_11C2\nloc_1205:\ncall _sqrt\njmp short loc_11E0\nloc_120C:\ncmp ebp, 1\njle short loc_1218\nadd ebp, 1\nimul r12d, ebp\nloc_1218:\nmov eax, r12d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n unsigned int v1; // r12d\n int v2; // ebp\n int v3; // ebx\n int v4; // esi\n int i; // ecx\n int v6; // edi\n double v7; // xmm0_8\n double v8; // xmm0_8\n int v9; // r8d\n\n v1 = 0;\n if ( (a1 & 1) == 0 )\n {\n v2 = a1;\n v3 = 2;\n v1 = 1;\n while ( 1 )\n {\n v7 = (double)v2;\n v8 = (double)v2 < 0.0 ? sqrt(v7) : sqrt(v7);\n if ( (int)v8 + 1 < v3 )\n break;\n v9 = v2 % v3;\n v6 = v2 % v3;\n v4 = 1;\n for ( i = 1; !(v2 % v3); i += v4 )\n {\n ++v6;\n v2 /= v3;\n if ( v3 == 2 && v6 == 1 )\n i = v9;\n v4 *= v3;\n }\n v1 *= i;\n ++v3;\n }\n if ( v2 > 1 )\n v1 *= v2 + 1;\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n unsigned int v1;\n int v2;\n int v3;\n int v4;\n int i;\n int v6;\n double v7;\n double v8;\n int v9;\n v1 = 0;\n if ((a1 & 1) == 0) {\n v2 = a1;\n v3 = 2;\n v1 = 1;\n while (1) {\n v7 = (double)v2;\n v8 = (double)v2 < 0.0 ? sqrt(v7) : sqrt(v7);\n if ((int)v8 + 1 < v3) break;\n v9 = v2 % v3;\n v6 = v2 % v3;\n v4 = 1;\n for (i = 1; !(v2 % v3); i += v4) {\n ++v6;\n v2 /= v3;\n if (v3 == 2 && v6 == 1) i = v9;\n v4 *= v3;\n }\n v1 *= i;\n ++v3;\n }\n if (v2 > 1) v1 *= v2 + 1;\n }\n return v1;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v1;\n int v2;\n int v3;\n int v4;\n int i;\n int v6;\n double v7;\n double v8;\n int v9;\n v1 = 0;\n if ((a1 & 1) == 0) {\n v2 = a1;\n v3 = 2;\n v1 = 1;\n while (1) {\n v7 = (double)v2;\n v8 = (double)v2 < 0.0 ? sqrt(v7) : sqrt(v7);\n if ((int)v8 + 1 < v3) break;\n v9 = v2 % v3;\n v6 = v2 % v3;\n v4 = 1;\n for (i = 1; !(v2 % v3); i += v4) {\n ++v6;\n v2 /= v3;\n if (v3 == 2 && v6 == 1) i = v9;\n v4 *= v3;\n }\n v1 *= i;\n ++v3;\n }\n if (v2 > 1) v1 *= v2 + 1;\n }\n return v1;\n}" + }, + { + "index": 453, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n % 2 != 0) {\n return 0;\n }\n int res = 1;\n for (int i = 2; i <= (int)(sqrt(n)) + 1; i++) {\n int count = 0;\n int curr_sum = 1;\n int curr_term = 1;\n while (n % i == 0) {\n count += 1;\n n = n / i;\n if (i == 2 && count == 1) {\n curr_sum = 0;\n }\n curr_term = curr_term * i;\n curr_sum = curr_sum + curr_term;\n }\n res = res * curr_sum;\n }\n if (n >= 2) {\n res = res * (1 + n);\n }\n return res;\n}", + "test": "int main() {\n\n assert(func0(18) == 26);\n\n assert(func0(30) == 48);\n\n assert(func0(6) == 8);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest $0x1,%dil\njne 1320 \njmpq 1210 \nxor %eax,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0_part_0:\npxor xmm1, xmm1\npush r13\npxor xmm2, xmm2\nmov r13d, 1\npush r12\ncvtsi2sd xmm1, edi\nxor r12d, r12d\npush rbp\nmov ebp, edi\npush rbx\nmov ebx, 2\nsub rsp, 18h\nnop word ptr [rax+rax+00000000h]\nloc_1240:\nucomisd xmm2, xmm1\nmovapd xmm0, xmm1; x\nja loc_12DA\nsqrtsd xmm0, xmm0\nloc_1252:\ncvttsd2si eax, xmm0\nadd eax, 1\ncmp ebx, eax\njg short loc_12C0\nmov eax, ebp\ncdq\nidiv ebx\ntest edx, edx\njnz short loc_12B4\ncmp ebx, 2\nmov esi, 1\nmov edi, 1\nsetz r9b\nxor r8d, r8d\nnop word ptr [rax+rax+00h]\nloc_1280:\nmov eax, ebp\nadd r8d, 1\ncdq\nidiv ebx\nmov ecx, eax\nmov ebp, eax\ncmp r8d, 1\njnz short loc_129A\ntest r9b, r9b\ncmovnz esi, r12d\nloc_129A:\nimul edi, ebx\nmov eax, ecx\ncdq\nidiv ebx\nadd esi, edi\ntest edx, edx\njz short loc_1280\npxor xmm1, xmm1\nimul r13d, esi\ncvtsi2sd xmm1, ecx\nloc_12B4:\nadd ebx, 1\njmp short loc_1240\nloc_12C0:\ncmp ebp, 1\njle short loc_12CC\nadd ebp, 1\nimul r13d, ebp\nloc_12CC:\nadd rsp, 18h\nmov eax, r13d\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_12DA:\nmovsd [rsp+38h+var_30], xmm1\ncall _sqrt\nmovsd xmm1, [rsp+38h+var_30]\npxor xmm2, xmm2\njmp loc_1252", + "ida_pseudo": "__int64 __fastcall func0_part_0(int a1)\n{\n unsigned int v1; // r13d\n double v2; // xmm1_8\n int v3; // ebp\n int i; // ebx\n double v5; // xmm0_8\n int v6; // esi\n int v7; // edi\n int v8; // r8d\n int v9; // ecx\n\n v1 = 1;\n v2 = (double)a1;\n v3 = a1;\n for ( i = 2; ; ++i )\n {\n v5 = v2 < 0.0 ? sqrt(v2) : sqrt(v2);\n if ( i > (int)v5 + 1 )\n break;\n if ( !(v3 % i) )\n {\n v6 = 1;\n v7 = 1;\n v8 = 0;\n do\n {\n ++v8;\n v9 = v3 / i;\n v3 /= i;\n if ( v8 == 1 && i == 2 )\n v6 = 0;\n v7 *= i;\n v6 += v7;\n }\n while ( !(v9 % i) );\n v1 *= v6;\n v2 = (double)v9;\n }\n }\n if ( v3 > 1 )\n v1 *= v3 + 1;\n return v1;\n}", + "ida_strip_asm": "sub_1210:\npxor xmm1, xmm1\npush r13\npxor xmm2, xmm2\nmov r13d, 1\npush r12\ncvtsi2sd xmm1, edi\nxor r12d, r12d\npush rbp\nmov ebp, edi\npush rbx\nmov ebx, 2\nsub rsp, 18h\nnop word ptr [rax+rax+00000000h]\nloc_1240:\nucomisd xmm2, xmm1\nmovapd xmm0, xmm1; x\nja loc_12DA\nsqrtsd xmm0, xmm0\nloc_1252:\ncvttsd2si eax, xmm0\nadd eax, 1\ncmp ebx, eax\njg short loc_12C0\nmov eax, ebp\ncdq\nidiv ebx\ntest edx, edx\njnz short loc_12B4\ncmp ebx, 2\nmov esi, 1\nmov edi, 1\nsetz r9b\nxor r8d, r8d\nnop word ptr [rax+rax+00h]\nloc_1280:\nmov eax, ebp\nadd r8d, 1\ncdq\nidiv ebx\nmov ecx, eax\nmov ebp, eax\ncmp r8d, 1\njnz short loc_129A\ntest r9b, r9b\ncmovnz esi, r12d\nloc_129A:\nimul edi, ebx\nmov eax, ecx\ncdq\nidiv ebx\nadd esi, edi\ntest edx, edx\njz short loc_1280\npxor xmm1, xmm1\nimul r13d, esi\ncvtsi2sd xmm1, ecx\nloc_12B4:\nadd ebx, 1\njmp short loc_1240\nloc_12C0:\ncmp ebp, 1\njle short loc_12CC\nadd ebp, 1\nimul r13d, ebp\nloc_12CC:\nadd rsp, 18h\nmov eax, r13d\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_12DA:\nmovsd [rsp+38h+var_30], xmm1\ncall _sqrt\nmovsd xmm1, [rsp+38h+var_30]\npxor xmm2, xmm2\njmp loc_1252", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(int a1)\n{\n unsigned int v1; // r13d\n double v2; // xmm1_8\n int v3; // ebp\n int i; // ebx\n double v5; // xmm0_8\n int v6; // esi\n int v7; // edi\n int v8; // r8d\n int v9; // ecx\n\n v1 = 1;\n v2 = (double)a1;\n v3 = a1;\n for ( i = 2; ; ++i )\n {\n v5 = v2 < 0.0 ? sqrt(v2) : sqrt(v2);\n if ( i > (int)v5 + 1 )\n break;\n if ( !(v3 % i) )\n {\n v6 = 1;\n v7 = 1;\n v8 = 0;\n do\n {\n ++v8;\n v9 = v3 / i;\n v3 /= i;\n if ( v8 == 1 && i == 2 )\n v6 = 0;\n v7 *= i;\n v6 += v7;\n }\n while ( !(v9 % i) );\n v1 *= v6;\n v2 = (double)v9;\n }\n }\n if ( v3 > 1 )\n v1 *= v3 + 1;\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(int a1) {\n unsigned int v1;\n double v2;\n int v3;\n int i;\n double v5;\n int v6;\n int v7;\n int v8;\n int v9;\n v1 = 1;\n v2 = (double)a1;\n v3 = a1;\n for (i = 2;; ++i) {\n v5 = v2 < 0.0 ? sqrt(v2) : sqrt(v2);\n if (i > (int)v5 + 1) break;\n if (!(v3 % i)) {\n v6 = 1;\n v7 = 1;\n v8 = 0;\n do {\n ++v8;\n v9 = v3 / i;\n v3 /= i;\n if (v8 == 1 && i == 2) v6 = 0;\n v7 *= i;\n v6 += v7;\n } while (!(v9 % i));\n v1 *= v6;\n v2 = (double)v9;\n }\n }\n if (v3 > 1) v1 *= v3 + 1;\n return v1;\n}", + "ida_pseudo_norm": "long long func0_part_0(int a1) {\n unsigned int v1;\n double v2;\n int v3;\n int i;\n double v5;\n int v6;\n int v7;\n int v8;\n int v9;\n v1 = 1;\n v2 = (double)a1;\n v3 = a1;\n for (i = 2;; ++i) {\n v5 = v2 < 0.0 ? sqrt(v2) : sqrt(v2);\n if (i > (int)v5 + 1) break;\n if (!(v3 % i)) {\n v6 = 1;\n v7 = 1;\n v8 = 0;\n do {\n ++v8;\n v9 = v3 / i;\n v3 /= i;\n if (v8 == 1 && i == 2) v6 = 0;\n v7 *= i;\n v6 += v7;\n } while (!(v9 % i));\n v1 *= v6;\n v2 = (double)v9;\n }\n }\n if (v3 > 1) v1 *= v3 + 1;\n return v1;\n}" + }, + { + "index": 453, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n % 2 != 0) {\n return 0;\n }\n int res = 1;\n for (int i = 2; i <= (int)(sqrt(n)) + 1; i++) {\n int count = 0;\n int curr_sum = 1;\n int curr_term = 1;\n while (n % i == 0) {\n count += 1;\n n = n / i;\n if (i == 2 && count == 1) {\n curr_sum = 0;\n }\n curr_term = curr_term * i;\n curr_sum = curr_sum + curr_term;\n }\n res = res * curr_sum;\n }\n if (n >= 2) {\n res = res * (1 + n);\n }\n return res;\n}", + "test": "int main() {\n\n assert(func0(18) == 26);\n\n assert(func0(30) == 48);\n\n assert(func0(6) == 8);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nxor %r12d,%r12d\npush %rbx\nsub $0x28,%rsp\ntest $0x1,%dil\njne 13dc \npxor %xmm1,%xmm1\nmov $0x2,%ebx\nmov $0x1,%r12d\ncvtsi2sd %edi,%xmm1\npxor %xmm3,%xmm3\nucomisd %xmm1,%xmm3\nmovapd %xmm1,%xmm2\nsqrtsd %xmm2,%xmm2\nja 13e7 \ncvttsd2si %xmm2,%eax\nadd $0x1,%eax\ncmp %eax,%ebx\njg 13d0 \nmov %edi,%eax\ncltd\nidiv %ebx\nmov %edx,%esi\ntest %edx,%edx\njne 13c7 \ncmp $0x2,%ebx\nmov $0x1,%r9d\nmov $0x1,%r8d\nsete %r10b\nnopl 0x0(%rax,%rax,1)\nmov %edi,%eax\nadd $0x1,%esi\ncltd\nidiv %ebx\nmov %eax,%ecx\nmov %eax,%edi\ncmp $0x1,%esi\njne 13a8 \ntest %r10b,%r10b\nje 13a8 \nadd %r8d,%r8d\ntest $0x1,%al\njne 13bb \nmov %r8d,%r9d\njmp 1380 \nnopw 0x0(%rax,%rax,1)\nmov %ecx,%eax\nimul %ebx,%r8d\ncltd\nidiv %ebx\nadd %r8d,%r9d\ntest %edx,%edx\nje 1380 \nmov %r9d,%r8d\npxor %xmm1,%xmm1\nimul %r8d,%r12d\ncvtsi2sd %ecx,%xmm1\nadd $0x1,%ebx\njmpq 1340 \ncmp $0x1,%edi\njle 13dc \nadd $0x1,%edi\nimul %edi,%r12d\nadd $0x28,%rsp\nmov %r12d,%eax\npop %rbx\npop %r12\nretq\nmovapd %xmm1,%xmm0\nmov %edi,0x1c(%rsp)\nmovsd %xmm2,0x10(%rsp)\nmovsd %xmm1,0x8(%rsp)\ncallq 1070 \nmov 0x1c(%rsp),%edi\nmovsd 0x10(%rsp),%xmm2\npxor %xmm3,%xmm3\nmovsd 0x8(%rsp),%xmm1\njmpq 1352 \nnopl 0x0(%rax)\n", + "ida_asm": "func0_part_0:\npxor xmm1, xmm1\npush r12\npxor xmm2, xmm2\nmov r12d, 1\npush rbp\ncvtsi2sd xmm1, edi\nmov ebp, edi\npush rbx\nmov ebx, 2\nsub rsp, 10h\nnop dword ptr [rax+00000000h]\nloc_1238:\nucomisd xmm2, xmm1\nmovapd xmm0, xmm1; x\nja loc_12E0\nsqrtsd xmm0, xmm0\nloc_124A:\ncvttsd2si eax, xmm0\nadd eax, 1\ncmp ebx, eax\njg short loc_12C8\nmov eax, ebp\ncdq\nidiv ebx\nmov ecx, edx\ntest edx, edx\njnz short loc_12BB\ncmp ebx, 2\nmov r8d, 1\nmov edi, 1\nsetz r9b\nnop word ptr [rax+rax+00h]\nloc_1278:\nmov eax, ebp\nadd ecx, 1\ncdq\nidiv ebx\nmov esi, eax\nmov ebp, eax\ncmp ecx, 1\njnz short loc_12A0\ntest r9b, r9b\njz short loc_12A0\nlea r8d, [rdi+rdi]\ntest al, 1\njnz short loc_12AF\nmov edi, r8d\njmp short loc_1278\nloc_12A0:\nmov eax, esi\nimul edi, ebx\ncdq\nidiv ebx\nadd r8d, edi\ntest edx, edx\njz short loc_1278\nloc_12AF:\npxor xmm1, xmm1\nimul r12d, r8d\ncvtsi2sd xmm1, esi\nloc_12BB:\nadd ebx, 1\njmp loc_1238\nloc_12C8:\ncmp ebp, 1\njle short loc_12D4\nadd ebp, 1\nimul r12d, ebp\nloc_12D4:\nadd rsp, 10h\nmov eax, r12d\npop rbx\npop rbp\npop r12\nretn\nloc_12E0:\nmovsd [rsp+28h+var_20], xmm1\ncall _sqrt\nmovsd xmm1, [rsp+28h+var_20]\npxor xmm2, xmm2\njmp loc_124A", + "ida_pseudo": "__int64 __fastcall func0_part_0(int a1)\n{\n unsigned int v1; // r12d\n double v2; // xmm1_8\n int v3; // ebp\n int i; // ebx\n double v5; // xmm0_8\n int v6; // ecx\n int v7; // r8d\n int v8; // edi\n int v9; // eax\n int v10; // esi\n\n v1 = 1;\n v2 = (double)a1;\n v3 = a1;\n for ( i = 2; ; ++i )\n {\n v5 = v2 < 0.0 ? sqrt(v2) : sqrt(v2);\n if ( i > (int)v5 + 1 )\n break;\n v6 = v3 % i;\n if ( !(v3 % i) )\n {\n v7 = 1;\n v8 = 1;\n do\n {\n while ( 1 )\n {\n ++v6;\n v9 = v3 / i;\n v10 = v3 / i;\n v3 /= i;\n if ( v6 != 1 || i != 2 )\n break;\n v7 = 2 * v8;\n if ( (v9 & 1) != 0 )\n goto LABEL_12;\n v8 *= 2;\n }\n v8 *= i;\n v7 += v8;\n }\n while ( !(v10 % i) );\nLABEL_12:\n v1 *= v7;\n v2 = (double)v10;\n }\n }\n if ( v3 > 1 )\n v1 *= v3 + 1;\n return v1;\n}", + "ida_strip_asm": "sub_1210:\npxor xmm1, xmm1\npush r12\npxor xmm2, xmm2\nmov r12d, 1\npush rbp\ncvtsi2sd xmm1, edi\nmov ebp, edi\npush rbx\nmov ebx, 2\nsub rsp, 10h\nnop dword ptr [rax+00000000h]\nloc_1238:\nucomisd xmm2, xmm1\nmovapd xmm0, xmm1; x\nja loc_12E0\nsqrtsd xmm0, xmm0\nloc_124A:\ncvttsd2si eax, xmm0\nadd eax, 1\ncmp ebx, eax\njg short loc_12C8\nmov eax, ebp\ncdq\nidiv ebx\nmov ecx, edx\ntest edx, edx\njnz short loc_12BB\ncmp ebx, 2\nmov r8d, 1\nmov edi, 1\nsetz r9b\nnop word ptr [rax+rax+00h]\nloc_1278:\nmov eax, ebp\nadd ecx, 1\ncdq\nidiv ebx\nmov esi, eax\nmov ebp, eax\ncmp ecx, 1\njnz short loc_12A0\ntest r9b, r9b\njz short loc_12A0\nlea r8d, [rdi+rdi]\ntest al, 1\njnz short loc_12AF\nmov edi, r8d\njmp short loc_1278\nloc_12A0:\nmov eax, esi\nimul edi, ebx\ncdq\nidiv ebx\nadd r8d, edi\ntest edx, edx\njz short loc_1278\nloc_12AF:\npxor xmm1, xmm1\nimul r12d, r8d\ncvtsi2sd xmm1, esi\nloc_12BB:\nadd ebx, 1\njmp loc_1238\nloc_12C8:\ncmp ebp, 1\njle short loc_12D4\nadd ebp, 1\nimul r12d, ebp\nloc_12D4:\nadd rsp, 10h\nmov eax, r12d\npop rbx\npop rbp\npop r12\nretn\nloc_12E0:\nmovsd [rsp+28h+var_20], xmm1\ncall _sqrt\nmovsd xmm1, [rsp+28h+var_20]\npxor xmm2, xmm2\njmp loc_124A", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(int a1)\n{\n unsigned int v1; // r12d\n double v2; // xmm1_8\n int v3; // ebp\n int i; // ebx\n double v5; // xmm0_8\n int v6; // ecx\n int v7; // r8d\n int v8; // edi\n int v9; // eax\n int v10; // esi\n\n v1 = 1;\n v2 = (double)a1;\n v3 = a1;\n for ( i = 2; ; ++i )\n {\n v5 = v2 < 0.0 ? sqrt(v2) : sqrt(v2);\n if ( i > (int)v5 + 1 )\n break;\n v6 = v3 % i;\n if ( !(v3 % i) )\n {\n v7 = 1;\n v8 = 1;\n do\n {\n while ( 1 )\n {\n ++v6;\n v9 = v3 / i;\n v10 = v3 / i;\n v3 /= i;\n if ( v6 != 1 || i != 2 )\n break;\n v7 = 2 * v8;\n if ( (v9 & 1) != 0 )\n goto LABEL_12;\n v8 *= 2;\n }\n v8 *= i;\n v7 += v8;\n }\n while ( !(v10 % i) );\nLABEL_12:\n v1 *= v7;\n v2 = (double)v10;\n }\n }\n if ( v3 > 1 )\n v1 *= v3 + 1;\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(int a1) {\n unsigned int v1;\n double v2;\n int v3;\n int i;\n double v5;\n int v6;\n int v7;\n int v8;\n int v9;\n int v10;\n v1 = 1;\n v2 = (double)a1;\n v3 = a1;\n for (i = 2;; ++i) {\n v5 = v2 < 0.0 ? sqrt(v2) : sqrt(v2);\n if (i > (int)v5 + 1) break;\n v6 = v3 % i;\n if (!(v3 % i)) {\n v7 = 1;\n v8 = 1;\n do {\n while (1) {\n ++v6;\n v9 = v3 / i;\n v10 = v3 / i;\n v3 /= i;\n if (v6 != 1 || i != 2) break;\n v7 = 2 * v8;\n if ((v9 & 1) != 0) goto LABEL_12;\n v8 *= 2;\n }\n v8 *= i;\n v7 += v8;\n } while (!(v10 % i));\n LABEL_12:\n v1 *= v7;\n v2 = (double)v10;\n }\n }\n if (v3 > 1) v1 *= v3 + 1;\n return v1;\n}", + "ida_pseudo_norm": "long long func0_part_0(int a1) {\n unsigned int v1;\n double v2;\n int v3;\n int i;\n double v5;\n int v6;\n int v7;\n int v8;\n int v9;\n int v10;\n v1 = 1;\n v2 = (double)a1;\n v3 = a1;\n for (i = 2;; ++i) {\n v5 = v2 < 0.0 ? sqrt(v2) : sqrt(v2);\n if (i > (int)v5 + 1) break;\n v6 = v3 % i;\n if (!(v3 % i)) {\n v7 = 1;\n v8 = 1;\n do {\n while (1) {\n ++v6;\n v9 = v3 / i;\n v10 = v3 / i;\n v3 /= i;\n if (v6 != 1 || i != 2) break;\n v7 = 2 * v8;\n if ((v9 & 1) != 0) goto LABEL_12;\n v8 *= 2;\n }\n v8 *= i;\n v7 += v8;\n } while (!(v10 % i));\n LABEL_12:\n v1 *= v7;\n v2 = (double)v10;\n }\n }\n if (v3 > 1) v1 *= v3 + 1;\n return v1;\n}" + }, + { + "index": 454, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "const char* func0(const char* text) {\n regex_t regex;\n int reti;\n char* pattern = \"\\\\w*z.\\\\w*\";\n reti = regcomp(®ex, pattern, REG_EXTENDED);\n if (reti) {\n fprintf(stderr, \"Could not compile regex\\n\");\n return \"Regex compile error\";\n }\n reti = regexec(®ex, text, 0, NULL, 0);\n regfree(®ex);\n if (!reti) {\n return \"Found a match!\";\n } else if (reti == REG_NOMATCH) {\n return \"Not matched!\";\n } else {\n char error_message[100];\n regerror(reti, ®ex, error_message, sizeof(error_message));\n fprintf(stderr, \"Regex match failed: %s\\n\", error_message);\n return \"Regex match error\";\n }\n}", + "test": "int main() {\n\n // Assert statements\n\n assert(func0(\"pythonz.\") == \"Found a match!\");\n\n assert(func0(\"xyz.\") == \"Found a match!\");\n\n assert(func0(\" lang .\") == \"Not matched!\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0xd0,%rsp\nmov %rdi,-0xc8(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0xdb3(%rip),%rax\nmov %rax,-0xb8(%rbp)\nmov -0xb8(%rbp),%rcx\nlea -0xb0(%rbp),%rax\nmov $0x1,%edx\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 10f0 \nmov %eax,-0xbc(%rbp)\ncmpl $0x0,-0xbc(%rbp)\nje 12b5 \nmov 0x2d90(%rip),%rax\nmov %rax,%rcx\nmov $0x18,%edx\nmov $0x1,%esi\nlea 0xd6d(%rip),%rdi\ncallq 1130 \nlea 0xd7a(%rip),%rax\njmpq 1357 \nmov -0xc8(%rbp),%rsi\nlea -0xb0(%rbp),%rax\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rax,%rdi\ncallq 1120 \nmov %eax,-0xbc(%rbp)\nlea -0xb0(%rbp),%rax\nmov %rax,%rdi\ncallq 10c0 \ncmpl $0x0,-0xbc(%rbp)\njne 1302 \nlea 0xd3e(%rip),%rax\njmp 1357 \ncmpl $0x1,-0xbc(%rbp)\njne 1314 \nlea 0xd3b(%rip),%rax\njmp 1357 \nlea -0x70(%rbp),%rdx\nlea -0xb0(%rbp),%rsi\nmov -0xbc(%rbp),%eax\nmov $0x64,%ecx\nmov %eax,%edi\ncallq 1110 \nmov 0x2ce8(%rip),%rax\nlea -0x70(%rbp),%rdx\nlea 0xd17(%rip),%rsi\nmov %rax,%rdi\nmov $0x0,%eax\ncallq 1100 \nlea 0xd1b(%rip),%rax\nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 136b \ncallq 10d0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0D0h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aWZW; \"\\\\w*z.\\\\w*\"\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+errcode], eax\ncmp [rbp+errcode], 0\njz short loc_12B8\nmov rax, cs:__bss_start\nmov rcx, rax; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rax, aCouldNotCompil; \"Could not compile regex\\n\"\nmov rdi, rax; ptr\ncall _fwrite\nlea rax, aRegexCompileEr; \"Regex compile error\"\njmp loc_135D\nloc_12B8:\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+errcode], eax\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\ncmp [rbp+errcode], 0\njnz short loc_1305\nlea rax, aFoundAMatch; \"Found a match!\"\njmp short loc_135D\nloc_1305:\ncmp [rbp+errcode], 1\njnz short loc_1317\nlea rax, aNotMatched; \"Not matched!\"\njmp short loc_135D\nloc_1317:\nlea rdx, [rbp+errbuf]; errbuf\nlea rsi, [rbp+preg]; preg\nmov eax, [rbp+errcode]\nmov ecx, 64h ; 'd'; errbuf_size\nmov edi, eax; errcode\ncall _regerror\nmov rax, cs:__bss_start\nlea rdx, [rbp+errbuf]\nlea rcx, format; \"Regex match failed: %s\\n\"\nmov rsi, rcx; format\nmov rdi, rax; stream\nmov eax, 0\ncall _fprintf\nlea rax, aRegexMatchErro; \"Regex match error\"\nloc_135D:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1371\ncall ___stack_chk_fail\nlocret_1371:\nleave\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n int errcode; // [rsp+14h] [rbp-BCh]\n regex_t preg; // [rsp+20h] [rbp-B0h] BYREF\n char errbuf[104]; // [rsp+60h] [rbp-70h] BYREF\n unsigned __int64 v5; // [rsp+C8h] [rbp-8h]\n\n v5 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"\\\\w*z.\\\\w*\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n return \"Regex compile error\";\n }\n else\n {\n errcode = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if ( errcode )\n {\n if ( errcode == 1 )\n {\n return \"Not matched!\";\n }\n else\n {\n regerror(errcode, &preg, errbuf, 0x64uLL);\n fprintf(_bss_start, \"Regex match failed: %s\\n\", errbuf);\n return \"Regex match error\";\n }\n }\n else\n {\n return \"Found a match!\";\n }\n }\n}", + "ida_strip_asm": "sub_1229:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0D0h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aWZW; \"\\\\w*z.\\\\w*\"\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+errcode], eax\ncmp [rbp+errcode], 0\njz short loc_12B8\nmov rax, cs:stderr\nmov rcx, rax; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rax, aCouldNotCompil; \"Could not compile regex\\n\"\nmov rdi, rax; ptr\ncall _fwrite\nlea rax, aRegexCompileEr; \"Regex compile error\"\njmp loc_135D\nloc_12B8:\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+errcode], eax\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\ncmp [rbp+errcode], 0\njnz short loc_1305\nlea rax, aFoundAMatch; \"Found a match!\"\njmp short loc_135D\nloc_1305:\ncmp [rbp+errcode], 1\njnz short loc_1317\nlea rax, aNotMatched; \"Not matched!\"\njmp short loc_135D\nloc_1317:\nlea rdx, [rbp+errbuf]; errbuf\nlea rsi, [rbp+preg]; preg\nmov eax, [rbp+errcode]\nmov ecx, 64h ; 'd'; errbuf_size\nmov edi, eax; errcode\ncall _regerror\nmov rax, cs:stderr\nlea rdx, [rbp+errbuf]\nlea rcx, format; \"Regex match failed: %s\\n\"\nmov rsi, rcx; format\nmov rdi, rax; stream\nmov eax, 0\ncall _fprintf\nlea rax, aRegexMatchErro; \"Regex match error\"\nloc_135D:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1371\ncall ___stack_chk_fail\nlocret_1371:\nleave\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1229(const char *a1)\n{\n int errcode; // [rsp+14h] [rbp-BCh]\n regex_t preg; // [rsp+20h] [rbp-B0h] BYREF\n char errbuf[104]; // [rsp+60h] [rbp-70h] BYREF\n unsigned __int64 v5; // [rsp+C8h] [rbp-8h]\n\n v5 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"\\\\w*z.\\\\w*\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n return \"Regex compile error\";\n }\n else\n {\n errcode = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if ( errcode )\n {\n if ( errcode == 1 )\n {\n return \"Not matched!\";\n }\n else\n {\n regerror(errcode, &preg, errbuf, 0x64uLL);\n fprintf(stderr, \"Regex match failed: %s\\n\", errbuf);\n return \"Regex match error\";\n }\n }\n else\n {\n return \"Found a match!\";\n }\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1229(const char *a1) {\n int errcode;\n regex_t preg;\n char errbuf[104];\n unsigned long long v5;\n v5 = __readfsqword(40u);\n if (regcomp(&preg, \"\\\\w*z.\\\\w*\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n return \"Regex compile error\";\n } else {\n errcode = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if (errcode) {\n if (errcode == 1) {\n return \"Not matched!\";\n } else {\n regerror(errcode, &preg, errbuf, 100uLL);\n fprintf(stderr, \"Regex match failed: %s\\n\", errbuf);\n return \"Regex match error\";\n }\n } else {\n return \"Found a match!\";\n }\n }\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n int errcode;\n regex_t preg;\n char errbuf[104];\n unsigned long long v5;\n v5 = __readfsqword(40u);\n if (regcomp(&preg, \"\\\\w*z.\\\\w*\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n return \"Regex compile error\";\n } else {\n errcode = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if (errcode) {\n if (errcode == 1) {\n return \"Not matched!\";\n } else {\n regerror(errcode, &preg, errbuf, 100uLL);\n fprintf(_bss_start, \"Regex match failed: %s\\n\", errbuf);\n return \"Regex match error\";\n }\n } else {\n return \"Found a match!\";\n }\n }\n}" + }, + { + "index": 454, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "const char* func0(const char* text) {\n regex_t regex;\n int reti;\n char* pattern = \"\\\\w*z.\\\\w*\";\n reti = regcomp(®ex, pattern, REG_EXTENDED);\n if (reti) {\n fprintf(stderr, \"Could not compile regex\\n\");\n return \"Regex compile error\";\n }\n reti = regexec(®ex, text, 0, NULL, 0);\n regfree(®ex);\n if (!reti) {\n return \"Found a match!\";\n } else if (reti == REG_NOMATCH) {\n return \"Not matched!\";\n } else {\n char error_message[100];\n regerror(reti, ®ex, error_message, sizeof(error_message));\n fprintf(stderr, \"Regex match failed: %s\\n\", error_message);\n return \"Regex match error\";\n }\n}", + "test": "int main() {\n\n // Assert statements\n\n assert(func0(\"pythonz.\") == \"Found a match!\");\n\n assert(func0(\"xyz.\") == \"Found a match!\");\n\n assert(func0(\" lang .\") == \"Not matched!\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0xb8,%rsp\nmov %rdi,%rbx\nmov %fs:0x28,%rax\nmov %rax,0xa8(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nmov $0x1,%edx\nlea 0xdeb(%rip),%rsi\ncallq 10f0 \ntest %eax,%eax\njne 12e3 \nmov %rsp,%rbp\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rbx,%rsi\nmov %rbp,%rdi\ncallq 1110 \nmov %eax,%ebx\nmov %rbp,%rdi\ncallq 10c0 \nlea 0xd97(%rip),%rax\ntest %ebx,%ebx\nje 1307 \nlea 0xd9b(%rip),%rax\ncmp $0x1,%ebx\nje 1307 \nlea 0x40(%rsp),%rbp\nmov %rsp,%rsi\nmov $0x64,%ecx\nmov %rbp,%rdx\nmov %ebx,%edi\ncallq 1100 \nmov %rbp,%rcx\nlea 0xda4(%rip),%rdx\nmov $0x1,%esi\nmov 0x2d50(%rip),%rdi\nmov $0x0,%eax\ncallq 1130 <__fprintf_chk@plt>\nlea 0xd37(%rip),%rax\njmp 1307 \nmov 0x2d36(%rip),%rcx\nmov $0x18,%edx\nmov $0x1,%esi\nlea 0xd54(%rip),%rdi\ncallq 1120 \nlea 0xcfd(%rip),%rax\nmov 0xa8(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 1324 \nadd $0xb8,%rsp\npop %rbx\npop %rbp\nretq\ncallq 10d0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 0B8h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+0C8h+var_20], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"\\\\w*z.\\\\w*\"\ncall _regcomp\ntest eax, eax\njnz short loc_12E3\nmov rbp, rsp\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov ebx, eax\nmov rdi, rbp; preg\ncall _regfree\nlea rax, aFoundAMatch; \"Found a match!\"\ntest ebx, ebx\njz short loc_1307\nlea rax, aNotMatched; \"Not matched!\"\ncmp ebx, 1\njz short loc_1307\nlea rbp, [rsp+0C8h+errbuf]\nmov rsi, rsp; preg\nmov ecx, 64h ; 'd'; errbuf_size\nmov rdx, rbp; errbuf\nmov edi, ebx; errcode\ncall _regerror\nmov rcx, rbp\nlea rdx, aRegexMatchFail; \"Regex match failed: %s\\n\"\nmov esi, 2\nmov rdi, cs:__bss_start\nmov eax, 0\ncall ___fprintf_chk\nlea rax, aRegexMatchErro; \"Regex match error\"\njmp short loc_1307\nloc_12E3:\nmov rcx, cs:__bss_start; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nlea rax, aRegexCompileEr; \"Regex compile error\"\nloc_1307:\nmov rdx, [rsp+0C8h+var_20]\nsub rdx, fs:28h\njnz short loc_1324\nadd rsp, 0B8h\npop rbx\npop rbp\nretn\nloc_1324:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // ebx\n const char *result; // rax\n regex_t v3; // [rsp+0h] [rbp-C8h] BYREF\n char errbuf[104]; // [rsp+40h] [rbp-88h] BYREF\n unsigned __int64 v5; // [rsp+A8h] [rbp-20h]\n\n v5 = __readfsqword(0x28u);\n if ( regcomp(&v3, \"\\\\w*z.\\\\w*\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n return \"Regex compile error\";\n }\n else\n {\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n regfree(&v3);\n result = \"Found a match!\";\n if ( v1 )\n {\n result = \"Not matched!\";\n if ( v1 != 1 )\n {\n regerror(v1, &v3, errbuf, 0x64uLL);\n __fprintf_chk(_bss_start, 2LL, \"Regex match failed: %s\\n\", errbuf);\n return \"Regex match error\";\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1229:\nendbr64\npush rbp\npush rbx\nsub rsp, 0B8h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+0C8h+var_20], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"\\\\w*z.\\\\w*\"\ncall _regcomp\ntest eax, eax\njnz short loc_12E3\nmov rbp, rsp\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov ebx, eax\nmov rdi, rbp; preg\ncall _regfree\nlea rax, aFoundAMatch; \"Found a match!\"\ntest ebx, ebx\njz short loc_1307\nlea rax, aNotMatched; \"Not matched!\"\ncmp ebx, 1\njz short loc_1307\nlea rbp, [rsp+0C8h+errbuf]\nmov rsi, rsp; preg\nmov ecx, 64h ; 'd'; errbuf_size\nmov rdx, rbp; errbuf\nmov edi, ebx; errcode\ncall _regerror\nmov rcx, rbp\nlea rdx, aRegexMatchFail; \"Regex match failed: %s\\n\"\nmov esi, 2\nmov rdi, cs:stderr\nmov eax, 0\ncall ___fprintf_chk\nlea rax, aRegexMatchErro; \"Regex match error\"\njmp short loc_1307\nloc_12E3:\nmov rcx, cs:stderr; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nlea rax, aRegexCompileEr; \"Regex compile error\"\nloc_1307:\nmov rdx, [rsp+0C8h+var_20]\nsub rdx, fs:28h\njnz short loc_1324\nadd rsp, 0B8h\npop rbx\npop rbp\nretn\nloc_1324:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_1229(char *string)\n{\n int v1; // ebx\n const char *result; // rax\n regex_t v3; // [rsp+0h] [rbp-C8h] BYREF\n char errbuf[104]; // [rsp+40h] [rbp-88h] BYREF\n unsigned __int64 v5; // [rsp+A8h] [rbp-20h]\n\n v5 = __readfsqword(0x28u);\n if ( regcomp(&v3, \"\\\\w*z.\\\\w*\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n return \"Regex compile error\";\n }\n else\n {\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n regfree(&v3);\n result = \"Found a match!\";\n if ( v1 )\n {\n result = \"Not matched!\";\n if ( v1 != 1 )\n {\n regerror(v1, &v3, errbuf, 0x64uLL);\n __fprintf_chk(stderr, 2LL, \"Regex match failed: %s\\n\", errbuf);\n return \"Regex match error\";\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1229(char *string) {\n int v1;\n const char *result;\n regex_t v3;\n char errbuf[104];\n unsigned long long v5;\n v5 = __readfsqword(40u);\n if (regcomp(&v3, \"\\\\w*z.\\\\w*\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n return \"Regex compile error\";\n } else {\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n regfree(&v3);\n result = \"Found a match!\";\n if (v1) {\n result = \"Not matched!\";\n if (v1 != 1) {\n regerror(v1, &v3, errbuf, 100uLL);\n __fprintf_chk(stderr, 2LL, \"Regex match failed: %s\\n\", errbuf);\n return \"Regex match error\";\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n const char *result;\n regex_t v3;\n char errbuf[104];\n unsigned long long v5;\n v5 = __readfsqword(40u);\n if (regcomp(&v3, \"\\\\w*z.\\\\w*\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n return \"Regex compile error\";\n } else {\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n regfree(&v3);\n result = \"Found a match!\";\n if (v1) {\n result = \"Not matched!\";\n if (v1 != 1) {\n regerror(v1, &v3, errbuf, 100uLL);\n __fprintf_chk(_bss_start, 2LL, \"Regex match failed: %s\\n\", errbuf);\n return \"Regex match error\";\n }\n }\n }\n return result;\n}" + }, + { + "index": 454, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "const char* func0(const char* text) {\n regex_t regex;\n int reti;\n char* pattern = \"\\\\w*z.\\\\w*\";\n reti = regcomp(®ex, pattern, REG_EXTENDED);\n if (reti) {\n fprintf(stderr, \"Could not compile regex\\n\");\n return \"Regex compile error\";\n }\n reti = regexec(®ex, text, 0, NULL, 0);\n regfree(®ex);\n if (!reti) {\n return \"Found a match!\";\n } else if (reti == REG_NOMATCH) {\n return \"Not matched!\";\n } else {\n char error_message[100];\n regerror(reti, ®ex, error_message, sizeof(error_message));\n fprintf(stderr, \"Regex match failed: %s\\n\", error_message);\n return \"Regex match error\";\n }\n}", + "test": "int main() {\n\n // Assert statements\n\n assert(func0(\"pythonz.\") == \"Found a match!\");\n\n assert(func0(\"xyz.\") == \"Found a match!\");\n\n assert(func0(\" lang .\") == \"Not matched!\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov $0x1,%edx\nlea 0xd54(%rip),%rsi\npush %r12\npush %rbp\nmov %rdi,%rbp\nsub $0xb0,%rsp\nmov %fs:0x28,%rax\nmov %rax,0xa8(%rsp)\nxor %eax,%eax\nmov %rsp,%r12\nmov %r12,%rdi\ncallq 10f0 \ntest %eax,%eax\njne 13b8 \nmov %rbp,%rsi\nxor %r8d,%r8d\nxor %ecx,%ecx\nxor %edx,%edx\nmov %r12,%rdi\ncallq 1110 \nmov %r12,%rdi\nmov %eax,%ebp\ncallq 10c0 \nlea 0xce2(%rip),%rax\ntest %ebp,%ebp\nje 1393 \nlea 0xce6(%rip),%rax\ncmp $0x1,%ebp\nje 1393 \nlea 0x40(%rsp),%r13\nmov $0x64,%ecx\nmov %r12,%rsi\nmov %ebp,%edi\nmov %r13,%rdx\ncallq 1100 \nmov %r13,%rcx\nmov $0x1,%esi\nxor %eax,%eax\nmov 0x2ca0(%rip),%rdi\nlea 0xce1(%rip),%rdx\ncallq 1130 <__fprintf_chk@plt>\nlea 0xc85(%rip),%rax\nmov 0xa8(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 13de \nadd $0xb0,%rsp\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax,%rax,1)\nmov 0x2c61(%rip),%rcx\nmov $0x18,%edx\nmov $0x1,%esi\nlea 0xc7f(%rip),%rdi\ncallq 1120 \nlea 0xc28(%rip),%rax\njmp 1393 \ncallq 10d0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r12\nmov edx, 1; cflags\nlea rsi, pattern; \"\\\\w*z.\\\\w*\"\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 0B0h\nmov rax, fs:28h\nmov [rsp+var_sA8], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njnz loc_13B8\nmov rsi, rbx; string\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\nlea rax, aFoundAMatch; \"Found a match!\"\ntest ebx, ebx\njz short loc_1392\nlea rax, aNotMatched; \"Not matched!\"\ncmp ebx, 1\njz short loc_1392\nlea r12, [rsp+errbuf]\nmov ecx, 64h ; 'd'; errbuf_size\nmov rsi, rbp; preg\nmov edi, ebx; errcode\nmov rdx, r12; errbuf\ncall _regerror\nmov rcx, r12\nmov esi, 2\nxor eax, eax\nmov rdi, cs:__bss_start\nlea rdx, aRegexMatchFail; \"Regex match failed: %s\\n\"\ncall ___fprintf_chk\nlea rax, aRegexMatchErro; \"Regex match error\"\nloc_1392:\nmov rdx, [rsp+var_sA8]\nsub rdx, fs:28h\njnz short loc_13DE\nadd rsp, 0B0h\npop rbx\npop rbp\npop r12\nretn\nloc_13B8:\nmov rcx, cs:__bss_start; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nlea rax, aRegexCompileEr; \"Regex compile error\"\njmp short loc_1392\nloc_13DE:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // ebx\n const char *result; // rax\n regex_t vars0; // [rsp+0h] [rbp+0h] BYREF\n char errbuf[104]; // [rsp+40h] [rbp+40h] BYREF\n unsigned __int64 varsA8; // [rsp+A8h] [rbp+A8h]\n\n varsA8 = __readfsqword(0x28u);\n if ( regcomp(&vars0, \"\\\\w*z.\\\\w*\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n return \"Regex compile error\";\n }\n else\n {\n v1 = regexec(&vars0, string, 0LL, 0LL, 0);\n regfree(&vars0);\n result = \"Found a match!\";\n if ( v1 )\n {\n result = \"Not matched!\";\n if ( v1 != 1 )\n {\n regerror(v1, &vars0, errbuf, 0x64uLL);\n __fprintf_chk(_bss_start, 2LL, \"Regex match failed: %s\\n\", errbuf);\n return \"Regex match error\";\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\npush r12\nmov edx, 1; cflags\nlea rsi, pattern; \"\\\\w*z.\\\\w*\"\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 0B0h\nmov rax, fs:28h\nmov [rsp+var_sA8], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njnz loc_13B8\nmov rsi, rbx; string\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\nlea rax, aFoundAMatch; \"Found a match!\"\ntest ebx, ebx\njz short loc_1392\nlea rax, aNotMatched; \"Not matched!\"\ncmp ebx, 1\njz short loc_1392\nlea r12, [rsp+errbuf]\nmov ecx, 64h ; 'd'; errbuf_size\nmov rsi, rbp; preg\nmov edi, ebx; errcode\nmov rdx, r12; errbuf\ncall _regerror\nmov rcx, r12\nmov esi, 2\nxor eax, eax\nmov rdi, cs:stderr\nlea rdx, aRegexMatchFail; \"Regex match failed: %s\\n\"\ncall ___fprintf_chk\nlea rax, aRegexMatchErro; \"Regex match error\"\nloc_1392:\nmov rdx, [rsp+var_sA8]\nsub rdx, fs:28h\njnz short loc_13DE\nadd rsp, 0B0h\npop rbx\npop rbp\npop r12\nretn\nloc_13B8:\nmov rcx, cs:stderr; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nlea rax, aRegexCompileEr; \"Regex compile error\"\njmp short loc_1392\nloc_13DE:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_12E0(char *string)\n{\n int v1; // ebx\n const char *result; // rax\n regex_t vars0; // [rsp+0h] [rbp+0h] BYREF\n char errbuf[104]; // [rsp+40h] [rbp+40h] BYREF\n unsigned __int64 varsA8; // [rsp+A8h] [rbp+A8h]\n\n varsA8 = __readfsqword(0x28u);\n if ( regcomp(&vars0, \"\\\\w*z.\\\\w*\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n return \"Regex compile error\";\n }\n else\n {\n v1 = regexec(&vars0, string, 0LL, 0LL, 0);\n regfree(&vars0);\n result = \"Found a match!\";\n if ( v1 )\n {\n result = \"Not matched!\";\n if ( v1 != 1 )\n {\n regerror(v1, &vars0, errbuf, 0x64uLL);\n __fprintf_chk(stderr, 2LL, \"Regex match failed: %s\\n\", errbuf);\n return \"Regex match error\";\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_12E0(char *string) {\n int v1;\n const char *result;\n regex_t vars0;\n char errbuf[104];\n unsigned long long varsA8;\n varsA8 = __readfsqword(40u);\n if (regcomp(&vars0, \"\\\\w*z.\\\\w*\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n return \"Regex compile error\";\n } else {\n v1 = regexec(&vars0, string, 0LL, 0LL, 0);\n regfree(&vars0);\n result = \"Found a match!\";\n if (v1) {\n result = \"Not matched!\";\n if (v1 != 1) {\n regerror(v1, &vars0, errbuf, 100uLL);\n __fprintf_chk(stderr, 2LL, \"Regex match failed: %s\\n\", errbuf);\n return \"Regex match error\";\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n const char *result;\n regex_t vars0;\n char errbuf[104];\n unsigned long long varsA8;\n varsA8 = __readfsqword(40u);\n if (regcomp(&vars0, \"\\\\w*z.\\\\w*\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n return \"Regex compile error\";\n } else {\n v1 = regexec(&vars0, string, 0LL, 0LL, 0);\n regfree(&vars0);\n result = \"Found a match!\";\n if (v1) {\n result = \"Not matched!\";\n if (v1 != 1) {\n regerror(v1, &vars0, errbuf, 100uLL);\n __fprintf_chk(_bss_start, 2LL, \"Regex match failed: %s\\n\", errbuf);\n return \"Regex match error\";\n }\n }\n }\n return result;\n}" + }, + { + "index": 454, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "const char* func0(const char* text) {\n regex_t regex;\n int reti;\n char* pattern = \"\\\\w*z.\\\\w*\";\n reti = regcomp(®ex, pattern, REG_EXTENDED);\n if (reti) {\n fprintf(stderr, \"Could not compile regex\\n\");\n return \"Regex compile error\";\n }\n reti = regexec(®ex, text, 0, NULL, 0);\n regfree(®ex);\n if (!reti) {\n return \"Found a match!\";\n } else if (reti == REG_NOMATCH) {\n return \"Not matched!\";\n } else {\n char error_message[100];\n regerror(reti, ®ex, error_message, sizeof(error_message));\n fprintf(stderr, \"Regex match failed: %s\\n\", error_message);\n return \"Regex match error\";\n }\n}", + "test": "int main() {\n\n // Assert statements\n\n assert(func0(\"pythonz.\") == \"Found a match!\");\n\n assert(func0(\"xyz.\") == \"Found a match!\");\n\n assert(func0(\" lang .\") == \"Not matched!\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov $0x1,%edx\nlea 0xd54(%rip),%rsi\npush %r12\npush %rbp\nmov %rdi,%rbp\nsub $0xb0,%rsp\nmov %fs:0x28,%rax\nmov %rax,0xa8(%rsp)\nxor %eax,%eax\nmov %rsp,%r12\nmov %r12,%rdi\ncallq 10f0 \ntest %eax,%eax\njne 13b8 \nmov %rbp,%rsi\nxor %r8d,%r8d\nxor %ecx,%ecx\nxor %edx,%edx\nmov %r12,%rdi\ncallq 1110 \nmov %r12,%rdi\nmov %eax,%ebp\ncallq 10c0 \nlea 0xce2(%rip),%rax\ntest %ebp,%ebp\nje 1393 \nlea 0xce6(%rip),%rax\ncmp $0x1,%ebp\nje 1393 \nlea 0x40(%rsp),%r13\nmov $0x64,%ecx\nmov %r12,%rsi\nmov %ebp,%edi\nmov %r13,%rdx\ncallq 1100 \nmov %r13,%rcx\nmov $0x1,%esi\nxor %eax,%eax\nmov 0x2ca0(%rip),%rdi\nlea 0xce1(%rip),%rdx\ncallq 1130 <__fprintf_chk@plt>\nlea 0xc85(%rip),%rax\nmov 0xa8(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 13de \nadd $0xb0,%rsp\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax,%rax,1)\nmov 0x2c61(%rip),%rcx\nmov $0x18,%edx\nmov $0x1,%esi\nlea 0xc7f(%rip),%rdi\ncallq 1120 \nlea 0xc28(%rip),%rax\njmp 1393 \ncallq 10d0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r12\nmov edx, 1; cflags\nlea rsi, pattern; \"\\\\w*z.\\\\w*\"\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 0B0h\nmov rax, fs:28h\nmov [rsp+var_sA8], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njnz loc_13B8\nmov rsi, rbx; string\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\nlea rax, aFoundAMatch; \"Found a match!\"\ntest ebx, ebx\njz short loc_1392\nlea rax, aNotMatched; \"Not matched!\"\ncmp ebx, 1\njz short loc_1392\nlea r12, [rsp+errbuf]\nmov ecx, 64h ; 'd'; errbuf_size\nmov rsi, rbp; preg\nmov edi, ebx; errcode\nmov rdx, r12; errbuf\ncall _regerror\nmov rcx, r12\nmov esi, 2\nxor eax, eax\nmov rdi, cs:__bss_start\nlea rdx, aRegexMatchFail; \"Regex match failed: %s\\n\"\ncall ___fprintf_chk\nlea rax, aRegexMatchErro; \"Regex match error\"\nloc_1392:\nmov rdx, [rsp+var_sA8]\nsub rdx, fs:28h\njnz short loc_13DE\nadd rsp, 0B0h\npop rbx\npop rbp\npop r12\nretn\nloc_13B8:\nmov rcx, cs:__bss_start; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nlea rax, aRegexCompileEr; \"Regex compile error\"\njmp short loc_1392\nloc_13DE:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // ebx\n const char *result; // rax\n regex_t vars0; // [rsp+0h] [rbp+0h] BYREF\n char errbuf[104]; // [rsp+40h] [rbp+40h] BYREF\n unsigned __int64 varsA8; // [rsp+A8h] [rbp+A8h]\n\n varsA8 = __readfsqword(0x28u);\n if ( regcomp(&vars0, \"\\\\w*z.\\\\w*\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n return \"Regex compile error\";\n }\n else\n {\n v1 = regexec(&vars0, string, 0LL, 0LL, 0);\n regfree(&vars0);\n result = \"Found a match!\";\n if ( v1 )\n {\n result = \"Not matched!\";\n if ( v1 != 1 )\n {\n regerror(v1, &vars0, errbuf, 0x64uLL);\n __fprintf_chk(_bss_start, 2LL, \"Regex match failed: %s\\n\", errbuf);\n return \"Regex match error\";\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\npush r12\nmov edx, 1; cflags\nlea rsi, pattern; \"\\\\w*z.\\\\w*\"\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 0B0h\nmov rax, fs:28h\nmov [rsp+var_sA8], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njnz loc_13B8\nmov rsi, rbx; string\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\nlea rax, aFoundAMatch; \"Found a match!\"\ntest ebx, ebx\njz short loc_1392\nlea rax, aNotMatched; \"Not matched!\"\ncmp ebx, 1\njz short loc_1392\nlea r12, [rsp+errbuf]\nmov ecx, 64h ; 'd'; errbuf_size\nmov rsi, rbp; preg\nmov edi, ebx; errcode\nmov rdx, r12; errbuf\ncall _regerror\nmov rcx, r12\nmov esi, 2\nxor eax, eax\nmov rdi, cs:stderr\nlea rdx, aRegexMatchFail; \"Regex match failed: %s\\n\"\ncall ___fprintf_chk\nlea rax, aRegexMatchErro; \"Regex match error\"\nloc_1392:\nmov rdx, [rsp+var_sA8]\nsub rdx, fs:28h\njnz short loc_13DE\nadd rsp, 0B0h\npop rbx\npop rbp\npop r12\nretn\nloc_13B8:\nmov rcx, cs:stderr; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nlea rax, aRegexCompileEr; \"Regex compile error\"\njmp short loc_1392\nloc_13DE:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_12E0(char *string)\n{\n int v1; // ebx\n const char *result; // rax\n regex_t vars0; // [rsp+0h] [rbp+0h] BYREF\n char errbuf[104]; // [rsp+40h] [rbp+40h] BYREF\n unsigned __int64 varsA8; // [rsp+A8h] [rbp+A8h]\n\n varsA8 = __readfsqword(0x28u);\n if ( regcomp(&vars0, \"\\\\w*z.\\\\w*\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n return \"Regex compile error\";\n }\n else\n {\n v1 = regexec(&vars0, string, 0LL, 0LL, 0);\n regfree(&vars0);\n result = \"Found a match!\";\n if ( v1 )\n {\n result = \"Not matched!\";\n if ( v1 != 1 )\n {\n regerror(v1, &vars0, errbuf, 0x64uLL);\n __fprintf_chk(stderr, 2LL, \"Regex match failed: %s\\n\", errbuf);\n return \"Regex match error\";\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_12E0(char *string) {\n int v1;\n const char *result;\n regex_t vars0;\n char errbuf[104];\n unsigned long long varsA8;\n varsA8 = __readfsqword(40u);\n if (regcomp(&vars0, \"\\\\w*z.\\\\w*\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n return \"Regex compile error\";\n } else {\n v1 = regexec(&vars0, string, 0LL, 0LL, 0);\n regfree(&vars0);\n result = \"Found a match!\";\n if (v1) {\n result = \"Not matched!\";\n if (v1 != 1) {\n regerror(v1, &vars0, errbuf, 100uLL);\n __fprintf_chk(stderr, 2LL, \"Regex match failed: %s\\n\", errbuf);\n return \"Regex match error\";\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n const char *result;\n regex_t vars0;\n char errbuf[104];\n unsigned long long varsA8;\n varsA8 = __readfsqword(40u);\n if (regcomp(&vars0, \"\\\\w*z.\\\\w*\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n return \"Regex compile error\";\n } else {\n v1 = regexec(&vars0, string, 0LL, 0LL, 0);\n regfree(&vars0);\n result = \"Found a match!\";\n if (v1) {\n result = \"Not matched!\";\n if (v1 != 1) {\n regerror(v1, &vars0, errbuf, 100uLL);\n __fprintf_chk(_bss_start, 2LL, \"Regex match failed: %s\\n\", errbuf);\n return \"Regex match error\";\n }\n }\n }\n return result;\n}" + }, + { + "index": 455, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int monthnum2) {\n if (monthnum2 == 1 || monthnum2 == 3 || monthnum2 == 5 || monthnum2 == 7 ||\n monthnum2 == 8 || monthnum2 == 10 || monthnum2 == 12) {\n return true;\n } else {\n return false;\n }\n}", + "test": "int main() {\n\n assert(func0(5) == true);\n\n assert(func0(2) == false);\n\n assert(func0(6) == false);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\ncmpl $0x1,-0x4(%rbp)\nje 117e \ncmpl $0x3,-0x4(%rbp)\nje 117e \ncmpl $0x5,-0x4(%rbp)\nje 117e \ncmpl $0x7,-0x4(%rbp)\nje 117e \ncmpl $0x8,-0x4(%rbp)\nje 117e \ncmpl $0xa,-0x4(%rbp)\nje 117e \ncmpl $0xc,-0x4(%rbp)\njne 1185 \nmov $0x1,%eax\njmp 118a \nmov $0x0,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\ncmp [rbp+var_4], 1\njz short loc_117E\ncmp [rbp+var_4], 3\njz short loc_117E\ncmp [rbp+var_4], 5\njz short loc_117E\ncmp [rbp+var_4], 7\njz short loc_117E\ncmp [rbp+var_4], 8\njz short loc_117E\ncmp [rbp+var_4], 0Ah\njz short loc_117E\ncmp [rbp+var_4], 0Ch\njnz short loc_1185\nloc_117E:\nmov eax, 1\njmp short loc_118A\nloc_1185:\nmov eax, 0\nloc_118A:\npop rbp\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(int a1)\n{\n return a1 == 1 || a1 == 3 || a1 == 5 || a1 == 7 || a1 == 8 || a1 == 10 || a1 == 12;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\ncmp [rbp+var_4], 1\njz short loc_117E\ncmp [rbp+var_4], 3\njz short loc_117E\ncmp [rbp+var_4], 5\njz short loc_117E\ncmp [rbp+var_4], 7\njz short loc_117E\ncmp [rbp+var_4], 8\njz short loc_117E\ncmp [rbp+var_4], 0Ah\njz short loc_117E\ncmp [rbp+var_4], 0Ch\njnz short loc_1185\nloc_117E:\nmov eax, 1\njmp short loc_118A\nloc_1185:\nmov eax, 0\nloc_118A:\npop rbp\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1149(int a1)\n{\n return a1 == 1 || a1 == 3 || a1 == 5 || a1 == 7 || a1 == 8 || a1 == 10 || a1 == 12;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1149(int a1) {\n return a1 == 1 || a1 == 3 || a1 == 5 || a1 == 7 || a1 == 8 || a1 == 10 ||\n a1 == 12;\n}", + "ida_pseudo_norm": "uint8_t func0(int a1) {\n return a1 == 1 || a1 == 3 || a1 == 5 || a1 == 7 || a1 == 8 || a1 == 10 ||\n a1 == 12;\n}" + }, + { + "index": 456, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nvoid reverse_string(char* str) {\n\n int n = strlen(str);\n\n for (int i = 0; i < n / 2; i++) {\n\n char temp = str[i];\n\n str[i] = str[n - i - 1];\n\n str[n - i - 1] = temp;\n\n }\n\n}\n\n\n\n", + "func": "void func0(char stringlist[][50], int size) {\n for (int i = 0; i < size; i++) {\n reverse_string(stringlist[i]);\n }\n}", + "test": "int main() {\n\n char list1[][50] = {\"Red\", \"Green\", \"Blue\", \"White\", \"Black\"};\n\n char list2[][50] = {\"john\", \"amal\", \"joel\", \"george\"};\n\n char list3[][50] = {\"jack\", \"john\", \"mary\"};\n\n\n\n func0(list1, 5);\n\n assert(strcmp(list1[0], \"deR\") == 0);\n\n assert(strcmp(list1[1], \"neerG\") == 0);\n\n assert(strcmp(list1[2], \"eulB\") == 0);\n\n assert(strcmp(list1[3], \"etihW\") == 0);\n\n assert(strcmp(list1[4], \"kcalB\") == 0);\n\n\n\n func0(list2, 4);\n\n assert(strcmp(list2[0], \"nhoj\") == 0);\n\n assert(strcmp(list2[1], \"lama\") == 0);\n\n assert(strcmp(list2[2], \"leoj\") == 0);\n\n assert(strcmp(list2[3], \"egroeg\") == 0);\n\n\n\n func0(list3, 3);\n\n assert(strcmp(list3[0], \"kcaj\") == 0);\n\n assert(strcmp(list3[1], \"nhoj\") == 0);\n\n assert(strcmp(list3[2], \"yram\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 128b \nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nadd %rax,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov %rax,%rdi\ncallq 11a9 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1257 \nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 0\njmp short loc_128B\nloc_1257:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nadd rax, rax\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rdi, rax\ncall reverse_string\nadd [rbp+var_4], 1\nloc_128B:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1257\nnop\nnop\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+1Ch] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a2 )\n break;\n reverse_string(50LL * (int)i + a1);\n }\n return result;\n}", + "ida_strip_asm": "sub_123B:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 0\njmp short loc_128B\nloc_1257:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nadd rax, rax\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rdi, rax\ncall sub_11A9\nadd [rbp+var_4], 1\nloc_128B:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1257\nnop\nnop\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_123B(__int64 a1, int a2)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+1Ch] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a2 )\n break;\n sub_11A9(50LL * (int)i + a1);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_123B(long long a1, int a2) {\n long long result;\n unsigned int i;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a2) break;\n sub_11A9(50LL * (int)i + a1);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long result;\n unsigned int i;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a2) break;\n reverse_string(50LL * (int)i + a1);\n }\n return result;\n}" + }, + { + "index": 456, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nvoid reverse_string(char* str) {\n\n int n = strlen(str);\n\n for (int i = 0; i < n / 2; i++) {\n\n char temp = str[i];\n\n str[i] = str[n - i - 1];\n\n str[n - i - 1] = temp;\n\n }\n\n}\n\n\n\n", + "func": "void func0(char stringlist[][50], int size) {\n for (int i = 0; i < size; i++) {\n reverse_string(stringlist[i]);\n }\n}", + "test": "int main() {\n\n char list1[][50] = {\"Red\", \"Green\", \"Blue\", \"White\", \"Black\"};\n\n char list2[][50] = {\"john\", \"amal\", \"joel\", \"george\"};\n\n char list3[][50] = {\"jack\", \"john\", \"mary\"};\n\n\n\n func0(list1, 5);\n\n assert(strcmp(list1[0], \"deR\") == 0);\n\n assert(strcmp(list1[1], \"neerG\") == 0);\n\n assert(strcmp(list1[2], \"eulB\") == 0);\n\n assert(strcmp(list1[3], \"etihW\") == 0);\n\n assert(strcmp(list1[4], \"kcalB\") == 0);\n\n\n\n func0(list2, 4);\n\n assert(strcmp(list2[0], \"nhoj\") == 0);\n\n assert(strcmp(list2[1], \"lama\") == 0);\n\n assert(strcmp(list2[2], \"leoj\") == 0);\n\n assert(strcmp(list2[3], \"egroeg\") == 0);\n\n\n\n func0(list3, 3);\n\n assert(strcmp(list3[0], \"kcaj\") == 0);\n\n assert(strcmp(list3[1], \"nhoj\") == 0);\n\n assert(strcmp(list3[2], \"yram\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11f0 \npush %rbp\npush %rbx\nmov %rdi,%rbx\nlea -0x1(%rsi),%eax\nlea (%rax,%rax,4),%rax\nlea (%rax,%rax,4),%rax\nlea 0x32(%rdi,%rax,2),%rbp\nmov %rbx,%rdi\ncallq 1169 \nadd $0x32,%rbx\ncmp %rbp,%rbx\njne 11dc \npop %rbx\npop %rbp\nretq\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short locret_1223\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmovsxd rsi, esi\nlea rax, [rsi+rsi*4]\nlea rax, [rax+rax*4]\nlea rbp, [rdi+rax*2]\nloc_120B:\nmov rdi, rbx\ncall reverse_string\nadd rbx, 32h ; '2'\ncmp rbx, rbp\njnz short loc_120B\nadd rsp, 8\npop rbx\npop rbp\nretn\nlocret_1223:\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // rbx\n __int64 result; // rax\n\n if ( a2 > 0 )\n {\n v2 = a1;\n do\n {\n result = reverse_string(v2);\n v2 += 50LL;\n }\n while ( v2 != a1 + 50LL * a2 );\n }\n return result;\n}", + "ida_strip_asm": "sub_11EB:\nendbr64\ntest esi, esi\njle short locret_1223\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmovsxd rsi, esi\nlea rax, [rsi+rsi*4]\nlea rax, [rax+rax*4]\nlea rbp, [rdi+rax*2]\nloc_120B:\nmov rdi, rbx\ncall sub_11A9\nadd rbx, 32h ; '2'\ncmp rbx, rbp\njnz short loc_120B\nadd rsp, 8\npop rbx\npop rbp\nretn\nlocret_1223:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11EB(__int64 a1, int a2)\n{\n __int64 v2; // rbx\n __int64 result; // rax\n\n if ( a2 > 0 )\n {\n v2 = a1;\n do\n {\n result = sub_11A9(v2);\n v2 += 50LL;\n }\n while ( v2 != a1 + 50LL * a2 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11EB(long long a1, int a2) {\n long long v2;\n long long result;\n if (a2 > 0) {\n v2 = a1;\n do {\n result = sub_11A9(v2);\n v2 += 50LL;\n } while (v2 != a1 + 50LL * a2);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n long long result;\n if (a2 > 0) {\n v2 = a1;\n do {\n result = reverse_string(v2);\n v2 += 50LL;\n } while (v2 != a1 + 50LL * a2);\n }\n return result;\n}" + }, + { + "index": 456, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nvoid reverse_string(char* str) {\n\n int n = strlen(str);\n\n for (int i = 0; i < n / 2; i++) {\n\n char temp = str[i];\n\n str[i] = str[n - i - 1];\n\n str[n - i - 1] = temp;\n\n }\n\n}\n\n\n\n", + "func": "void func0(char stringlist[][50], int size) {\n for (int i = 0; i < size; i++) {\n reverse_string(stringlist[i]);\n }\n}", + "test": "int main() {\n\n char list1[][50] = {\"Red\", \"Green\", \"Blue\", \"White\", \"Black\"};\n\n char list2[][50] = {\"john\", \"amal\", \"joel\", \"george\"};\n\n char list3[][50] = {\"jack\", \"john\", \"mary\"};\n\n\n\n func0(list1, 5);\n\n assert(strcmp(list1[0], \"deR\") == 0);\n\n assert(strcmp(list1[1], \"neerG\") == 0);\n\n assert(strcmp(list1[2], \"eulB\") == 0);\n\n assert(strcmp(list1[3], \"etihW\") == 0);\n\n assert(strcmp(list1[4], \"kcalB\") == 0);\n\n\n\n func0(list2, 4);\n\n assert(strcmp(list2[0], \"nhoj\") == 0);\n\n assert(strcmp(list2[1], \"lama\") == 0);\n\n assert(strcmp(list2[2], \"leoj\") == 0);\n\n assert(strcmp(list2[3], \"egroeg\") == 0);\n\n\n\n func0(list3, 3);\n\n assert(strcmp(list3[0], \"kcaj\") == 0);\n\n assert(strcmp(list3[1], \"nhoj\") == 0);\n\n assert(strcmp(list3[2], \"yram\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1730 \npush %rbp\nlea -0x1(%rsi),%eax\npush %rbx\nlea (%rax,%rax,4),%rax\nmov %rdi,%rbx\nlea (%rax,%rax,4),%rax\nlea 0x32(%rdi,%rax,2),%rbp\nsub $0x8,%rsp\nnopl 0x0(%rax)\nmov %rbx,%rdi\nadd $0x32,%rbx\ncallq 16a0 \ncmp %rbp,%rbx\njne 1718 \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short locret_177A\npush rbp\nmovsxd rsi, esi\npush rbx\nlea rax, [rsi+rsi*4]\nmov rbx, rdi\nlea rax, [rax+rax*4]\nlea rbp, [rdi+rax*2]\nsub rsp, 8\nloc_1730:\nmov rdi, rbx; s\ncall _strlen\nmov edi, eax\nshr edi, 1Fh\nadd edi, eax\nsar edi, 1\ncmp eax, 1\njle short loc_176A\ncdqe\nlea rdx, [rbx+rax-1]\nxor eax, eax\nnop\nloc_1750:\nmovzx esi, byte ptr [rdx]\nmovzx ecx, byte ptr [rbx+rax]\nsub rdx, 1\nmov [rbx+rax], sil\nadd rax, 1\nmov [rdx+1], cl\ncmp edi, eax\njg short loc_1750\nloc_176A:\nadd rbx, 32h ; '2'\ncmp rbx, rbp\njnz short loc_1730\nadd rsp, 8\npop rbx\npop rbp\nretn\nlocret_177A:\nretn", + "ida_pseudo": "void __fastcall func0(char *s, int a2)\n{\n const char *v2; // rbx\n char *v3; // rbp\n int v4; // eax\n int v5; // edi\n const char *v6; // rdx\n __int64 v7; // rax\n char v8; // si\n char v9; // cl\n\n if ( a2 > 0 )\n {\n v2 = s;\n v3 = &s[50 * a2];\n do\n {\n v4 = strlen(v2);\n v5 = v4 / 2;\n if ( v4 > 1 )\n {\n v6 = &v2[v4 - 1];\n v7 = 0LL;\n do\n {\n v8 = *v6;\n v9 = v2[v7];\n --v6;\n v2[v7++] = v8;\n *((_BYTE *)v6 + 1) = v9;\n }\n while ( v5 > (int)v7 );\n }\n v2 += 50;\n }\n while ( v2 != v3 );\n }\n}", + "ida_strip_asm": "sub_1710:\nendbr64\ntest esi, esi\njle short locret_177A\npush rbp\nmovsxd rsi, esi\npush rbx\nlea rax, [rsi+rsi*4]\nmov rbx, rdi\nlea rax, [rax+rax*4]\nlea rbp, [rdi+rax*2]\nsub rsp, 8\nloc_1730:\nmov rdi, rbx; s\ncall _strlen\nmov edi, eax\nshr edi, 1Fh\nadd edi, eax\nsar edi, 1\ncmp eax, 1\njle short loc_176A\ncdqe\nlea rdx, [rbx+rax-1]\nxor eax, eax\nnop\nloc_1750:\nmovzx esi, byte ptr [rdx]\nmovzx ecx, byte ptr [rbx+rax]\nsub rdx, 1\nmov [rbx+rax], sil\nadd rax, 1\nmov [rdx+1], cl\ncmp edi, eax\njg short loc_1750\nloc_176A:\nadd rbx, 32h ; '2'\ncmp rbx, rbp\njnz short loc_1730\nadd rsp, 8\npop rbx\npop rbp\nretn\nlocret_177A:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1710(char *s, int a2)\n{\n const char *v2; // rbx\n char *v3; // rbp\n int v4; // eax\n int v5; // edi\n const char *v6; // rdx\n __int64 v7; // rax\n char v8; // si\n char v9; // cl\n\n if ( a2 > 0 )\n {\n v2 = s;\n v3 = &s[50 * a2];\n do\n {\n v4 = strlen(v2);\n v5 = v4 / 2;\n if ( v4 > 1 )\n {\n v6 = &v2[v4 - 1];\n v7 = 0LL;\n do\n {\n v8 = *v6;\n v9 = v2[v7];\n --v6;\n v2[v7++] = v8;\n *((_BYTE *)v6 + 1) = v9;\n }\n while ( v5 > (int)v7 );\n }\n v2 += 50;\n }\n while ( v2 != v3 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1710(char *s, int a2) {\n const char *v2;\n char *v3;\n int v4;\n int v5;\n const char *v6;\n long long v7;\n char v8;\n char v9;\n if (a2 > 0) {\n v2 = s;\n v3 = &s[50 * a2];\n do {\n v4 = strlen(v2);\n v5 = v4 / 2;\n if (v4 > 1) {\n v6 = &v2[v4 - 1];\n v7 = 0LL;\n do {\n v8 = *v6;\n v9 = v2[v7];\n --v6;\n v2[v7++] = v8;\n *((uint8_t *)v6 + 1) = v9;\n } while (v5 > (int)v7);\n }\n v2 += 50;\n } while (v2 != v3);\n }\n}", + "ida_pseudo_norm": "void func0(char *s, int a2) {\n const char *v2;\n char *v3;\n int v4;\n int v5;\n const char *v6;\n long long v7;\n char v8;\n char v9;\n if (a2 > 0) {\n v2 = s;\n v3 = &s[50 * a2];\n do {\n v4 = strlen(v2);\n v5 = v4 / 2;\n if (v4 > 1) {\n v6 = &v2[v4 - 1];\n v7 = 0LL;\n do {\n v8 = *v6;\n v9 = v2[v7];\n --v6;\n v2[v7++] = v8;\n *((uint8_t *)v6 + 1) = v9;\n } while (v5 > (int)v7);\n }\n v2 += 50;\n } while (v2 != v3);\n }\n}" + }, + { + "index": 457, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n// Define a struct to deal with list of strings\n\ntypedef struct {\n\n char **elems;\n\n int size;\n\n} StringList;\n\n\n\n", + "func": "StringList func0(StringList lst) {\n int minIndex = 0;\n for (int i = 1; i < lst.size; i++) {\n if (strcmp(lst.elems[i], lst.elems[minIndex]) < 0) {\n minIndex = i;\n }\n }\n StringList result = {.elems = &lst.elems[minIndex], .size = 1};\n return result;\n}", + "test": "int main() {\n\n // Test 1\n\n char *list1[] = {\"1\", \"1,2\", \"1,2,3\"};\n\n StringList lst1 = { list1, 3 };\n\n StringList result1 = func0(lst1);\n\n assert(strcmp(result1.elems[0], \"1\") == 0);\n\n\n\n // Test 2\n\n char *list2[] = {\"1,1\", \"1,1,1\", \"1,2,7,8\"};\n\n StringList lst2 = { list2, 3 };\n\n StringList result2 = func0(lst2);\n\n assert(strcmp(result2.elems[0], \"1,1\") == 0);\n\n\n\n // Test 3\n\n char *list3[] = {\"x\", \"x,y\", \"x,y,z\"};\n\n StringList lst3 = { list3, 3 };\n\n StringList result3 = func0(lst3);\n\n assert(strcmp(result3.elems[0], \"x\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,%rax\nmov %rsi,%rcx\nmov %rcx,%rdx\nmov %rax,-0x30(%rbp)\nmov %rdx,-0x28(%rbp)\nmovl $0x0,-0x18(%rbp)\nmovl $0x1,-0x14(%rbp)\njmp 11f7 \nmov -0x30(%rbp),%rax\nmov -0x18(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x3,%rdx\nadd %rdx,%rax\nmov (%rax),%rdx\nmov -0x30(%rbp),%rax\nmov -0x14(%rbp),%ecx\nmovslq %ecx,%rcx\nshl $0x3,%rcx\nadd %rcx,%rax\nmov (%rax),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1090 \ntest %eax,%eax\njns 11f3 \nmov -0x14(%rbp),%eax\nmov %eax,-0x18(%rbp)\naddl $0x1,-0x14(%rbp)\nmov -0x28(%rbp),%eax\ncmp %eax,-0x14(%rbp)\njl 11b6 \nmov -0x30(%rbp),%rax\nmov -0x18(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x3,%rdx\nadd %rdx,%rax\nmov %rax,-0x10(%rbp)\nmovl $0x1,-0x8(%rbp)\nmov -0x10(%rbp),%rax\nmov -0x8(%rbp),%rdx\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov rax, rdi\nmov rcx, rsi\nmov rdx, rcx\nmov [rbp+var_30], rax\nmov [rbp+var_28], rdx\nmov [rbp+var_18], 0\nmov [rbp+var_14], 1\njmp short loc_11F7\nloc_11B6:\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_18]\nmovsxd rdx, edx\nshl rdx, 3\nadd rax, rdx\nmov rdx, [rax]\nmov rax, [rbp+var_30]\nmov ecx, [rbp+var_14]\nmovsxd rcx, ecx\nshl rcx, 3\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njns short loc_11F3\nmov eax, [rbp+var_14]\nmov [rbp+var_18], eax\nloc_11F3:\nadd [rbp+var_14], 1\nloc_11F7:\nmov eax, dword ptr [rbp+var_28]\ncmp [rbp+var_14], eax\njl short loc_11B6\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_18]\nmovsxd rdx, edx\nshl rdx, 3\nadd rax, rdx\nmov [rbp+var_10], rax\nmov dword ptr [rbp+var_8], 1\nmov rax, [rbp+var_10]\nmov rdx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int v3; // [rsp+18h] [rbp-18h]\n int i; // [rsp+1Ch] [rbp-14h]\n\n v3 = 0;\n for ( i = 1; i < a2; ++i )\n {\n if ( strcmp(*(const char **)(8LL * i + a1), *(const char **)(8LL * v3 + a1)) < 0 )\n v3 = i;\n }\n return 8LL * v3 + a1;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov rax, rdi\nmov rcx, rsi\nmov rdx, rcx\nmov [rbp+var_30], rax\nmov [rbp+var_28], rdx\nmov [rbp+var_18], 0\nmov [rbp+var_14], 1\njmp short loc_11F7\nloc_11B6:\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_18]\nmovsxd rdx, edx\nshl rdx, 3\nadd rax, rdx\nmov rdx, [rax]\nmov rax, [rbp+var_30]\nmov ecx, [rbp+var_14]\nmovsxd rcx, ecx\nshl rcx, 3\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njns short loc_11F3\nmov eax, [rbp+var_14]\nmov [rbp+var_18], eax\nloc_11F3:\nadd [rbp+var_14], 1\nloc_11F7:\nmov eax, dword ptr [rbp+var_28]\ncmp [rbp+var_14], eax\njl short loc_11B6\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_18]\nmovsxd rdx, edx\nshl rdx, 3\nadd rax, rdx\nmov [rbp+var_10], rax\nmov dword ptr [rbp+var_8], 1\nmov rax, [rbp+var_10]\nmov rdx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2)\n{\n int v3; // [rsp+18h] [rbp-18h]\n int i; // [rsp+1Ch] [rbp-14h]\n\n v3 = 0;\n for ( i = 1; i < a2; ++i )\n {\n if ( strcmp(*(const char **)(8LL * i + a1), *(const char **)(8LL * v3 + a1)) < 0 )\n v3 = i;\n }\n return 8LL * v3 + a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2) {\n int v3;\n int i;\n v3 = 0;\n for (i = 1; i < a2; ++i) {\n if (strcmp(*(const char **)(8LL * i + a1),\n *(const char **)(8LL * v3 + a1)) < 0)\n v3 = i;\n }\n return 8LL * v3 + a1;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int v3;\n int i;\n v3 = 0;\n for (i = 1; i < a2; ++i) {\n if (strcmp(*(const char **)(8LL * i + a1),\n *(const char **)(8LL * v3 + a1)) < 0)\n v3 = i;\n }\n return 8LL * v3 + a1;\n}" + }, + { + "index": 457, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n// Define a struct to deal with list of strings\n\ntypedef struct {\n\n char **elems;\n\n int size;\n\n} StringList;\n\n\n\n", + "func": "StringList func0(StringList lst) {\n int minIndex = 0;\n for (int i = 1; i < lst.size; i++) {\n if (strcmp(lst.elems[i], lst.elems[minIndex]) < 0) {\n minIndex = i;\n }\n }\n StringList result = {.elems = &lst.elems[minIndex], .size = 1};\n return result;\n}", + "test": "int main() {\n\n // Test 1\n\n char *list1[] = {\"1\", \"1,2\", \"1,2,3\"};\n\n StringList lst1 = { list1, 3 };\n\n StringList result1 = func0(lst1);\n\n assert(strcmp(result1.elems[0], \"1\") == 0);\n\n\n\n // Test 2\n\n char *list2[] = {\"1,1\", \"1,1,1\", \"1,2,7,8\"};\n\n StringList lst2 = { list2, 3 };\n\n StringList result2 = func0(lst2);\n\n assert(strcmp(result2.elems[0], \"1,1\") == 0);\n\n\n\n // Test 3\n\n char *list3[] = {\"x\", \"x,y\", \"x,y,z\"};\n\n StringList lst3 = { list3, 3 };\n\n StringList result3 = func0(lst3);\n\n assert(strcmp(result3.elems[0], \"x\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%r13\ncmp $0x1,%esi\njle 11e6 \nmov %rdi,%r12\nlea -0x2(%rsi),%r14d\nadd $0x2,%r14\nmov $0x1,%ebx\nmov $0x0,%ebp\nmovslq %ebp,%rax\nmov (%r12,%rax,8),%rsi\nmov (%r12,%rbx,8),%rdi\ncallq 1090 \ntest %eax,%eax\ncmovs %ebx,%ebp\nadd $0x1,%rbx\ncmp %r14,%rbx\njne 11b2 \nmovslq %ebp,%rbp\nlea 0x0(%r13,%rbp,8),%rax\nmov $0x1,%edx\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nmov $0x0,%ebp\njmp 11d0 \n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12, rdi\ncmp esi, 1\njle short loc_11E1\nmov r13d, esi\nmov ebx, 1\nmov ebp, 0\nloc_11AC:\nmovsxd rax, ebp\nmov rsi, [r12+rax*8]; s2\nmov rdi, [r12+rbx*8]; s1\ncall _strcmp\ntest eax, eax\ncmovs ebp, ebx\nadd rbx, 1\ncmp rbx, r13\njnz short loc_11AC\nloc_11CA:\nmovsxd rbp, ebp\nlea rax, [r12+rbp*8]\nmov edx, 1\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_11E1:\nmov ebp, 0\njmp short loc_11CA", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // rbx\n int v3; // ebp\n\n if ( a2 <= 1 )\n {\n v3 = 0;\n }\n else\n {\n v2 = 1LL;\n v3 = 0;\n do\n {\n if ( strcmp(*(const char **)(a1 + 8 * v2), *(const char **)(a1 + 8LL * v3)) < 0 )\n v3 = v2;\n ++v2;\n }\n while ( v2 != a2 );\n }\n return a1 + 8LL * v3;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12, rdi\ncmp esi, 1\njle short loc_11E1\nmov r13d, esi\nmov ebx, 1\nmov ebp, 0\nloc_11AC:\nmovsxd rax, ebp\nmov rsi, [r12+rax*8]; s2\nmov rdi, [r12+rbx*8]; s1\ncall _strcmp\ntest eax, eax\ncmovs ebp, ebx\nadd rbx, 1\ncmp rbx, r13\njnz short loc_11AC\nloc_11CA:\nmovsxd rbp, ebp\nlea rax, [r12+rbp*8]\nmov edx, 1\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_11E1:\nmov ebp, 0\njmp short loc_11CA", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2)\n{\n __int64 v2; // rbx\n int v3; // ebp\n\n if ( a2 <= 1 )\n {\n v3 = 0;\n }\n else\n {\n v2 = 1LL;\n v3 = 0;\n do\n {\n if ( strcmp(*(const char **)(a1 + 8 * v2), *(const char **)(a1 + 8LL * v3)) < 0 )\n v3 = v2;\n ++v2;\n }\n while ( v2 != a2 );\n }\n return a1 + 8LL * v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2) {\n long long v2;\n int v3;\n if (a2 <= 1) {\n v3 = 0;\n } else {\n v2 = 1LL;\n v3 = 0;\n do {\n if (strcmp(*(const char **)(a1 + 8 * v2),\n *(const char **)(a1 + 8LL * v3)) < 0)\n v3 = v2;\n ++v2;\n } while (v2 != a2);\n }\n return a1 + 8LL * v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n int v3;\n if (a2 <= 1) {\n v3 = 0;\n } else {\n v2 = 1LL;\n v3 = 0;\n do {\n if (strcmp(*(const char **)(a1 + 8 * v2),\n *(const char **)(a1 + 8LL * v3)) < 0)\n v3 = v2;\n ++v2;\n } while (v2 != a2);\n }\n return a1 + 8LL * v3;\n}" + }, + { + "index": 457, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n// Define a struct to deal with list of strings\n\ntypedef struct {\n\n char **elems;\n\n int size;\n\n} StringList;\n\n\n\n", + "func": "StringList func0(StringList lst) {\n int minIndex = 0;\n for (int i = 1; i < lst.size; i++) {\n if (strcmp(lst.elems[i], lst.elems[minIndex]) < 0) {\n minIndex = i;\n }\n }\n StringList result = {.elems = &lst.elems[minIndex], .size = 1};\n return result;\n}", + "test": "int main() {\n\n // Test 1\n\n char *list1[] = {\"1\", \"1,2\", \"1,2,3\"};\n\n StringList lst1 = { list1, 3 };\n\n StringList result1 = func0(lst1);\n\n assert(strcmp(result1.elems[0], \"1\") == 0);\n\n\n\n // Test 2\n\n char *list2[] = {\"1,1\", \"1,1,1\", \"1,2,7,8\"};\n\n StringList lst2 = { list2, 3 };\n\n StringList result2 = func0(lst2);\n\n assert(strcmp(result2.elems[0], \"1,1\") == 0);\n\n\n\n // Test 3\n\n char *list3[] = {\"x\", \"x,y\", \"x,y,z\"};\n\n StringList lst3 = { list3, 3 };\n\n StringList result3 = func0(lst3);\n\n assert(strcmp(result3.elems[0], \"x\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\nmov %rdi,%rbp\npush %rbx\nsub $0x8,%rsp\ncmp $0x1,%esi\njle 1368 \nmov %esi,%r13d\nlea 0x8(%rdi),%r14\nmov $0x1,%ebx\nxor %r15d,%r15d\nnopl 0x0(%rax)\nmovslq %r15d,%rax\nmov (%r14),%rdi\nlea 0x0(%rbp,%rax,8),%r12\nmov (%r12),%rsi\ncallq 1090 \ntest %eax,%eax\ncmovs %r14,%r12\ncmovs %ebx,%r15d\nadd $0x1,%ebx\nadd $0x8,%r14\ncmp %ebx,%r13d\njne 1320 \nadd $0x8,%rsp\nmov %r12,%rax\nmov $0x1,%edx\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\nmov %rdi,%r12\njmp 134a \nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\nmov r13, rdi\npush r12\npush rbp\npush rbx\nsub rsp, 8\ncmp esi, 1\njle short loc_1388\nmov r14d, esi\nlea r12, [rdi+8]\nmov ebp, 1\nxor r15d, r15d\nnop dword ptr [rax+00000000h]\nloc_1340:\nmovsxd rax, r15d\nmov rdi, [r12]; s1\nlea rbx, [r13+rax*8+0]\nmov rsi, [rbx]; s2\ncall _strcmp\ntest eax, eax\nmov rax, rbx\ncmovs rax, r12\ncmovs r15d, ebp\nadd ebp, 1\nadd r12, 8\ncmp r14d, ebp\njnz short loc_1340\nloc_136D:\nadd rsp, 8\nmov edx, 1\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1388:\nmov rax, rdi\njmp short loc_136D", + "ida_pseudo": "const char **__fastcall func0(__int64 a1, int a2)\n{\n const char **v2; // r12\n int v3; // ebp\n int v4; // r15d\n bool v5; // sf\n const char **result; // rax\n\n if ( a2 <= 1 )\n return (const char **)a1;\n v2 = (const char **)(a1 + 8);\n v3 = 1;\n v4 = 0;\n do\n {\n v5 = strcmp(*v2, *(const char **)(a1 + 8LL * v4)) < 0;\n result = (const char **)(a1 + 8LL * v4);\n if ( v5 )\n {\n result = v2;\n v4 = v3;\n }\n ++v3;\n ++v2;\n }\n while ( a2 != v3 );\n return result;\n}", + "ida_strip_asm": "sub_1310:\nendbr64\npush r15\npush r14\npush r13\nmov r13, rdi\npush r12\npush rbp\npush rbx\nsub rsp, 8\ncmp esi, 1\njle short loc_1388\nmov r14d, esi\nlea r12, [rdi+8]\nmov ebp, 1\nxor r15d, r15d\nnop dword ptr [rax+00000000h]\nloc_1340:\nmovsxd rax, r15d\nmov rdi, [r12]; s1\nlea rbx, [r13+rax*8+0]\nmov rsi, [rbx]; s2\ncall _strcmp\ntest eax, eax\nmov rax, rbx\ncmovs rax, r12\ncmovs r15d, ebp\nadd ebp, 1\nadd r12, 8\ncmp r14d, ebp\njnz short loc_1340\nloc_136D:\nadd rsp, 8\nmov edx, 1\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1388:\nmov rax, rdi\njmp short loc_136D", + "ida_strip_pseudo": "const char **__fastcall sub_1310(__int64 a1, int a2)\n{\n const char **v2; // r12\n int v3; // ebp\n int v4; // r15d\n bool v5; // sf\n const char **result; // rax\n\n if ( a2 <= 1 )\n return (const char **)a1;\n v2 = (const char **)(a1 + 8);\n v3 = 1;\n v4 = 0;\n do\n {\n v5 = strcmp(*v2, *(const char **)(a1 + 8LL * v4)) < 0;\n result = (const char **)(a1 + 8LL * v4);\n if ( v5 )\n {\n result = v2;\n v4 = v3;\n }\n ++v3;\n ++v2;\n }\n while ( a2 != v3 );\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char **sub_1310(long long a1, int a2) {\n const char **v2;\n int v3;\n int v4;\n bool v5;\n const char **result;\n if (a2 <= 1) return (const char **)a1;\n v2 = (const char **)(a1 + 8);\n v3 = 1;\n v4 = 0;\n do {\n v5 = strcmp(*v2, *(const char **)(a1 + 8LL * v4)) < 0;\n result = (const char **)(a1 + 8LL * v4);\n if (v5) {\n result = v2;\n v4 = v3;\n }\n ++v3;\n ++v2;\n } while (a2 != v3);\n return result;\n}", + "ida_pseudo_norm": "const char **func0(long long a1, int a2) {\n const char **v2;\n int v3;\n int v4;\n bool v5;\n const char **result;\n if (a2 <= 1) return (const char **)a1;\n v2 = (const char **)(a1 + 8);\n v3 = 1;\n v4 = 0;\n do {\n v5 = strcmp(*v2, *(const char **)(a1 + 8LL * v4)) < 0;\n result = (const char **)(a1 + 8LL * v4);\n if (v5) {\n result = v2;\n v4 = v3;\n }\n ++v3;\n ++v2;\n } while (a2 != v3);\n return result;\n}" + }, + { + "index": 457, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n// Define a struct to deal with list of strings\n\ntypedef struct {\n\n char **elems;\n\n int size;\n\n} StringList;\n\n\n\n", + "func": "StringList func0(StringList lst) {\n int minIndex = 0;\n for (int i = 1; i < lst.size; i++) {\n if (strcmp(lst.elems[i], lst.elems[minIndex]) < 0) {\n minIndex = i;\n }\n }\n StringList result = {.elems = &lst.elems[minIndex], .size = 1};\n return result;\n}", + "test": "int main() {\n\n // Test 1\n\n char *list1[] = {\"1\", \"1,2\", \"1,2,3\"};\n\n StringList lst1 = { list1, 3 };\n\n StringList result1 = func0(lst1);\n\n assert(strcmp(result1.elems[0], \"1\") == 0);\n\n\n\n // Test 2\n\n char *list2[] = {\"1,1\", \"1,1,1\", \"1,2,7,8\"};\n\n StringList lst2 = { list2, 3 };\n\n StringList result2 = func0(lst2);\n\n assert(strcmp(result2.elems[0], \"1,1\") == 0);\n\n\n\n // Test 3\n\n char *list3[] = {\"x\", \"x,y\", \"x,y,z\"};\n\n StringList lst3 = { list3, 3 };\n\n StringList result3 = func0(lst3);\n\n assert(strcmp(result3.elems[0], \"x\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\nmov %rdi,%rbp\npush %rbx\nsub $0x18,%rsp\ncmp $0x1,%esi\njle 13a0 \nlea -0x2(%rsi),%r14d\nmovl $0x0,0xc(%rsp)\nmov (%rdi),%r15\nmov $0x1,%ebx\nadd $0x2,%r14\njmp 135b \nnopl 0x0(%rax)\nmovslq 0xc(%rsp),%rax\nadd $0x1,%rbx\nlea 0x0(%rbp,%rax,8),%r13\ncmp %rbx,%r14\nje 1384 \nmov 0x0(%rbp,%rbx,8),%r12\nmov %r15,%rsi\nlea 0x0(%rbp,%rbx,8),%r13\nmov %r12,%rdi\ncallq 1090 \ntest %eax,%eax\njns 1348 \nmov %ebx,0xc(%rsp)\nadd $0x1,%rbx\nmov %r12,%r15\ncmp %rbx,%r14\njne 135b \nadd $0x18,%rsp\nmov %r13,%rax\nmov $0x1,%edx\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax,%rax,1)\nmov %rdi,%r13\njmp 1384 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 8\ncmp esi, 1\njle short loc_1390\nmov r14, [rdi]\nmov r13d, esi\nmov ebx, 1\nxor r15d, r15d\njmp short loc_1351\nloc_1340:\nmovsxd rax, r15d\nadd rbx, 1\nlea rax, [rbp+rax*8+0]\ncmp r13, rbx\njz short loc_1379\nloc_1351:\nmov r12, [rbp+rbx*8+0]\nmov rsi, r14; s2\nmov rdi, r12; s1\ncall _strcmp\ntest eax, eax\njns short loc_1340\nmov r15d, ebx\nlea rax, [rbp+rbx*8+0]\nadd rbx, 1\nmov r14, r12\ncmp r13, rbx\njnz short loc_1351\nloc_1379:\nadd rsp, 8\nmov edx, 1\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1390:\nmov rax, rdi\njmp short loc_1379", + "ida_pseudo": "const char **__fastcall func0(const char **a1, int a2)\n{\n const char *v2; // r14\n __int64 v3; // rbx\n int v4; // r15d\n const char **result; // rax\n const char *v6; // r12\n\n if ( a2 <= 1 )\n return a1;\n v2 = *a1;\n v3 = 1LL;\n v4 = 0;\n do\n {\n while ( 1 )\n {\n v6 = a1[v3];\n if ( strcmp(v6, v2) < 0 )\n break;\n ++v3;\n result = &a1[v4];\n if ( a2 == v3 )\n return result;\n }\n v4 = v3;\n result = &a1[v3++];\n v2 = v6;\n }\n while ( a2 != v3 );\n return result;\n}", + "ida_strip_asm": "sub_1310:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 8\ncmp esi, 1\njle short loc_1390\nmov r14, [rdi]\nmov r13d, esi\nmov ebx, 1\nxor r15d, r15d\njmp short loc_1351\nloc_1340:\nmovsxd rax, r15d\nadd rbx, 1\nlea rax, [rbp+rax*8+0]\ncmp r13, rbx\njz short loc_1379\nloc_1351:\nmov r12, [rbp+rbx*8+0]\nmov rsi, r14; s2\nmov rdi, r12; s1\ncall _strcmp\ntest eax, eax\njns short loc_1340\nmov r15d, ebx\nlea rax, [rbp+rbx*8+0]\nadd rbx, 1\nmov r14, r12\ncmp r13, rbx\njnz short loc_1351\nloc_1379:\nadd rsp, 8\nmov edx, 1\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1390:\nmov rax, rdi\njmp short loc_1379", + "ida_strip_pseudo": "const char **__fastcall sub_1310(const char **a1, int a2)\n{\n const char *v2; // r14\n __int64 v3; // rbx\n int v4; // r15d\n const char **result; // rax\n const char *v6; // r12\n\n if ( a2 <= 1 )\n return a1;\n v2 = *a1;\n v3 = 1LL;\n v4 = 0;\n do\n {\n while ( 1 )\n {\n v6 = a1[v3];\n if ( strcmp(v6, v2) < 0 )\n break;\n ++v3;\n result = &a1[v4];\n if ( a2 == v3 )\n return result;\n }\n v4 = v3;\n result = &a1[v3++];\n v2 = v6;\n }\n while ( a2 != v3 );\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char **sub_1310(const char **a1, int a2) {\n const char *v2;\n long long v3;\n int v4;\n const char **result;\n const char *v6;\n if (a2 <= 1) return a1;\n v2 = *a1;\n v3 = 1LL;\n v4 = 0;\n do {\n while (1) {\n v6 = a1[v3];\n if (strcmp(v6, v2) < 0) break;\n ++v3;\n result = &a1[v4];\n if (a2 == v3) return result;\n }\n v4 = v3;\n result = &a1[v3++];\n v2 = v6;\n } while (a2 != v3);\n return result;\n}", + "ida_pseudo_norm": "const char **func0(const char **a1, int a2) {\n const char *v2;\n long long v3;\n int v4;\n const char **result;\n const char *v6;\n if (a2 <= 1) return a1;\n v2 = *a1;\n v3 = 1LL;\n v4 = 0;\n do {\n while (1) {\n v6 = a1[v3];\n if (strcmp(v6, v2) < 0) break;\n ++v3;\n result = &a1[v4];\n if (a2 == v3) return result;\n }\n v4 = v3;\n result = &a1[v3++];\n v2 = v6;\n } while (a2 != v3);\n return result;\n}" + }, + { + "index": 458, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int l, int b) {\n int area = l * b;\n return area;\n}", + "test": "int main() {\n\n assert(func0(10, 20) == 200);\n\n assert(func0(10, 5) == 50);\n\n assert(func0(4, 2) == 8);\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov -0x14(%rbp),%eax\nimul -0x18(%rbp),%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov eax, [rbp+var_14]\nimul eax, [rbp+var_18]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n return (unsigned int)(a2 * a1);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov eax, [rbp+var_14]\nimul eax, [rbp+var_18]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2)\n{\n return (unsigned int)(a2 * a1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2) { return (unsigned int)(a2 * a1); }", + "ida_pseudo_norm": "long long func0(int a1, int a2) { return (unsigned int)(a2 * a1); }" + }, + { + "index": 459, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* str1) {\n size_t len = strlen(str1);\n char* result = malloc(len + 1);\n if (!result) return NULL;\n size_t j = 0;\n for (size_t i = 0; i < len; i++) {\n if (!isupper((unsigned char)str1[i])) {\n result[j++] = str1[i];\n }\n }\n result[j] = '\\0';\n return result;\n}", + "test": "int main() {\n\n char* res1 = func0(\"cAstyoUrFavoRitETVshoWs\");\n\n assert(strcmp(res1, \"cstyoravoitshos\") == 0);\n\n free(res1);\n\n\n\n char* res2 = func0(\"wAtchTheinTernEtrAdIo\");\n\n assert(strcmp(res2, \"wtchheinerntrdo\") == 0);\n\n free(res2);\n\n\n\n char* res3 = func0(\"VoicESeaRchAndreComMendaTionS\");\n\n assert(strcmp(res3, \"oiceachndreomendaion\") == 0);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x28(%rbp)\nmov -0x28(%rbp),%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x10(%rbp)\nmov -0x10(%rbp),%rax\nadd $0x1,%rax\nmov %rax,%rdi\ncallq 10e0 \nmov %rax,-0x8(%rbp)\ncmpq $0x0,-0x8(%rbp)\njne 122e \nmov $0x0,%eax\njmpq 12b3 \nmovq $0x0,-0x20(%rbp)\nmovq $0x0,-0x18(%rbp)\njmp 1297 \ncallq 10f0 <__ctype_b_loc@plt>\nmov (%rax),%rax\nmov -0x28(%rbp),%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rdx),%edx\nmovzbl %dl,%edx\nadd %rdx,%rdx\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x100,%eax\ntest %eax,%eax\njne 1292 \nmov -0x28(%rbp),%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x20(%rbp),%rax\nlea 0x1(%rax),%rdx\nmov %rdx,-0x20(%rbp)\nmov -0x8(%rbp),%rdx\nadd %rax,%rdx\nmovzbl (%rcx),%eax\nmov %al,(%rdx)\naddq $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%rax\ncmp -0x10(%rbp),%rax\njb 1240 \nmov -0x8(%rbp),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmovb $0x0,(%rax)\nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_10], rax\nmov rax, [rbp+var_10]\nadd rax, 1\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\ncmp [rbp+var_8], 0\njnz short loc_122E\nmov eax, 0\njmp locret_12B3\nloc_122E:\nmov [rbp+var_20], 0\nmov [rbp+var_18], 0\njmp short loc_1297\nloc_1240:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov rcx, [rbp+s]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovzx edx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 100h\ntest eax, eax\njnz short loc_1292\nmov rdx, [rbp+s]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov rax, [rbp+var_20]\nlea rdx, [rax+1]\nmov [rbp+var_20], rdx\nmov rdx, [rbp+var_8]\nadd rdx, rax\nmovzx eax, byte ptr [rcx]\nmov [rdx], al\nloc_1292:\nadd [rbp+var_18], 1\nloc_1297:\nmov rax, [rbp+var_18]\ncmp rax, [rbp+var_10]\njb short loc_1240\nmov rdx, [rbp+var_8]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+var_8]\nlocret_12B3:\nleave\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1)\n{\n __int64 v2; // rax\n __int64 v3; // [rsp+10h] [rbp-20h]\n size_t i; // [rsp+18h] [rbp-18h]\n size_t v5; // [rsp+20h] [rbp-10h]\n _BYTE *v6; // [rsp+28h] [rbp-8h]\n\n v5 = strlen(a1);\n v6 = malloc(v5 + 1);\n if ( !v6 )\n return 0LL;\n v3 = 0LL;\n for ( i = 0LL; i < v5; ++i )\n {\n if ( ((*__ctype_b_loc())[(unsigned __int8)a1[i]] & 0x100) == 0 )\n {\n v2 = v3++;\n v6[v2] = a1[i];\n }\n }\n v6[v3] = 0;\n return v6;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_10], rax\nmov rax, [rbp+var_10]\nadd rax, 1\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\ncmp [rbp+var_8], 0\njnz short loc_122E\nmov eax, 0\njmp locret_12B3\nloc_122E:\nmov [rbp+var_20], 0\nmov [rbp+var_18], 0\njmp short loc_1297\nloc_1240:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov rcx, [rbp+s]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovzx edx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 100h\ntest eax, eax\njnz short loc_1292\nmov rdx, [rbp+s]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov rax, [rbp+var_20]\nlea rdx, [rax+1]\nmov [rbp+var_20], rdx\nmov rdx, [rbp+var_8]\nadd rdx, rax\nmovzx eax, byte ptr [rcx]\nmov [rdx], al\nloc_1292:\nadd [rbp+var_18], 1\nloc_1297:\nmov rax, [rbp+var_18]\ncmp rax, [rbp+var_10]\njb short loc_1240\nmov rdx, [rbp+var_8]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+var_8]\nlocret_12B3:\nleave\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_11E9(const char *a1)\n{\n __int64 v2; // rax\n __int64 v3; // [rsp+10h] [rbp-20h]\n size_t i; // [rsp+18h] [rbp-18h]\n size_t v5; // [rsp+20h] [rbp-10h]\n _BYTE *v6; // [rsp+28h] [rbp-8h]\n\n v5 = strlen(a1);\n v6 = malloc(v5 + 1);\n if ( !v6 )\n return 0LL;\n v3 = 0LL;\n for ( i = 0LL; i < v5; ++i )\n {\n if ( ((*__ctype_b_loc())[(unsigned __int8)a1[i]] & 0x100) == 0 )\n {\n v2 = v3++;\n v6[v2] = a1[i];\n }\n }\n v6[v3] = 0;\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_11E9(const char *a1) {\n long long v2;\n long long v3;\n unsigned int i;\n unsigned int v5;\n uint8_t *v6;\n v5 = strlen(a1);\n v6 = malloc(v5 + 1);\n if (!v6) return 0LL;\n v3 = 0LL;\n for (i = 0LL; i < v5; ++i) {\n if (((*__ctype_b_loc())[(unsigned char)a1[i]] & 256) == 0) {\n v2 = v3++;\n v6[v2] = a1[i];\n }\n }\n v6[v3] = 0;\n return v6;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1) {\n long long v2;\n long long v3;\n unsigned int i;\n unsigned int v5;\n uint8_t *v6;\n v5 = strlen(a1);\n v6 = malloc(v5 + 1);\n if (!v6) return 0LL;\n v3 = 0LL;\n for (i = 0LL; i < v5; ++i) {\n if (((*__ctype_b_loc())[(unsigned char)a1[i]] & 256) == 0) {\n v2 = v3++;\n v6[v2] = a1[i];\n }\n }\n v6[v3] = 0;\n return v6;\n}" + }, + { + "index": 459, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* str1) {\n size_t len = strlen(str1);\n char* result = malloc(len + 1);\n if (!result) return NULL;\n size_t j = 0;\n for (size_t i = 0; i < len; i++) {\n if (!isupper((unsigned char)str1[i])) {\n result[j++] = str1[i];\n }\n }\n result[j] = '\\0';\n return result;\n}", + "test": "int main() {\n\n char* res1 = func0(\"cAstyoUrFavoRitETVshoWs\");\n\n assert(strcmp(res1, \"cstyoravoitshos\") == 0);\n\n free(res1);\n\n\n\n char* res2 = func0(\"wAtchTheinTernEtrAdIo\");\n\n assert(strcmp(res2, \"wtchheinerntrdo\") == 0);\n\n free(res2);\n\n\n\n char* res3 = func0(\"VoicESeaRchAndreComMendaTionS\");\n\n assert(strcmp(res3, \"oiceachndreomendaion\") == 0);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%r12\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rdi\nnot %rdi\nlea -0x1(%rdi),%rbx\ncallq 10a0 \nmov %rax,%rbp\ntest %rax,%rax\nje 1219 \ntest %rbx,%rbx\nje 1214 \ncallq 10b0 <__ctype_b_loc@plt>\nmov (%rax),%rsi\nmov %r12,%rax\nlea (%r12,%rbx,1),%rdi\nmov $0x0,%ebx\njmp 11fd \nadd $0x1,%rax\ncmp %rdi,%rax\nje 1214 \nmovzbl (%rax),%edx\nmovzbl %dl,%ecx\ntestb $0x1,0x1(%rsi,%rcx,2)\njne 11f4 \nmov %dl,0x0(%rbp,%rbx,1)\nlea 0x1(%rbx),%rbx\njmp 11f4 \nmovb $0x0,0x0(%rbp,%rbx,1)\nmov %rbp,%rax\npop %rbx\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12, rdi\ncall _strlen\nmov r13, rax\nmov rbx, rax\nlea rdi, [rax+1]; size\ncall _malloc\nmov rbp, rax\ntest rax, rax\njz short loc_1256\ntest r13, r13\njz short loc_1251\ncall ___ctype_b_loc\nmov rdi, [rax]\nmov rax, r12\nlea rsi, [r12+r13]\nmov ebx, 0\njmp short loc_123A\nloc_1231:\nadd rax, 1\ncmp rax, rsi\njz short loc_1251\nloc_123A:\nmovzx edx, byte ptr [rax]\nmovzx ecx, dl\ntest byte ptr [rdi+rcx*2+1], 1\njnz short loc_1231\nmov [rbp+rbx+0], dl\nlea rbx, [rbx+1]\njmp short loc_1231\nloc_1251:\nmov byte ptr [rbp+rbx+0], 0\nloc_1256:\nmov rax, rbp\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1)\n{\n size_t v2; // r13\n size_t v3; // rbx\n _BYTE *v4; // rbp\n const unsigned __int16 *v5; // rdi\n const char *v6; // rax\n\n v2 = strlen(a1);\n v3 = v2;\n v4 = malloc(v2 + 1);\n if ( v4 )\n {\n if ( v2 )\n {\n v5 = *__ctype_b_loc();\n v6 = a1;\n v3 = 0LL;\n do\n {\n if ( (v5[*(unsigned __int8 *)v6] & 0x100) == 0 )\n v4[v3++] = *v6;\n ++v6;\n }\n while ( v6 != &a1[v2] );\n }\n v4[v3] = 0;\n }\n return v4;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12, rdi\ncall _strlen\nmov r13, rax\nmov rbx, rax\nlea rdi, [rax+1]; size\ncall _malloc\nmov rbp, rax\ntest rax, rax\njz short loc_1256\ntest r13, r13\njz short loc_1251\ncall ___ctype_b_loc\nmov rdi, [rax]\nmov rax, r12\nlea rsi, [r12+r13]\nmov ebx, 0\njmp short loc_123A\nloc_1231:\nadd rax, 1\ncmp rax, rsi\njz short loc_1251\nloc_123A:\nmovzx edx, byte ptr [rax]\nmovzx ecx, dl\ntest byte ptr [rdi+rcx*2+1], 1\njnz short loc_1231\nmov [rbp+rbx+0], dl\nlea rbx, [rbx+1]\njmp short loc_1231\nloc_1251:\nmov byte ptr [rbp+rbx+0], 0\nloc_1256:\nmov rax, rbp\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_11E9(const char *a1)\n{\n size_t v2; // r13\n size_t v3; // rbx\n _BYTE *v4; // rbp\n const unsigned __int16 *v5; // rdi\n const char *v6; // rax\n\n v2 = strlen(a1);\n v3 = v2;\n v4 = malloc(v2 + 1);\n if ( v4 )\n {\n if ( v2 )\n {\n v5 = *__ctype_b_loc();\n v6 = a1;\n v3 = 0LL;\n do\n {\n if ( (v5[*(unsigned __int8 *)v6] & 0x100) == 0 )\n v4[v3++] = *v6;\n ++v6;\n }\n while ( v6 != &a1[v2] );\n }\n v4[v3] = 0;\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_11E9(const char *a1) {\n unsigned int v2;\n unsigned int v3;\n uint8_t *v4;\n const unsigned short *v5;\n const char *v6;\n v2 = strlen(a1);\n v3 = v2;\n v4 = malloc(v2 + 1);\n if (v4) {\n if (v2) {\n v5 = *__ctype_b_loc();\n v6 = a1;\n v3 = 0LL;\n do {\n if ((v5[*(unsigned char *)v6] & 256) == 0) v4[v3++] = *v6;\n ++v6;\n } while (v6 != &a1[v2]);\n }\n v4[v3] = 0;\n }\n return v4;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1) {\n unsigned int v2;\n unsigned int v3;\n uint8_t *v4;\n const unsigned short *v5;\n const char *v6;\n v2 = strlen(a1);\n v3 = v2;\n v4 = malloc(v2 + 1);\n if (v4) {\n if (v2) {\n v5 = *__ctype_b_loc();\n v6 = a1;\n v3 = 0LL;\n do {\n if ((v5[*(unsigned char *)v6] & 256) == 0) v4[v3++] = *v6;\n ++v6;\n } while (v6 != &a1[v2]);\n }\n v4[v3] = 0;\n }\n return v4;\n}" + }, + { + "index": 459, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* str1) {\n size_t len = strlen(str1);\n char* result = malloc(len + 1);\n if (!result) return NULL;\n size_t j = 0;\n for (size_t i = 0; i < len; i++) {\n if (!isupper((unsigned char)str1[i])) {\n result[j++] = str1[i];\n }\n }\n result[j] = '\\0';\n return result;\n}", + "test": "int main() {\n\n char* res1 = func0(\"cAstyoUrFavoRitETVshoWs\");\n\n assert(strcmp(res1, \"cstyoravoitshos\") == 0);\n\n free(res1);\n\n\n\n char* res2 = func0(\"wAtchTheinTernEtrAdIo\");\n\n assert(strcmp(res2, \"wtchheinerntrdo\") == 0);\n\n free(res2);\n\n\n\n char* res3 = func0(\"VoicESeaRchAndreComMendaTionS\");\n\n assert(strcmp(res3, \"oiceachndreomendaion\") == 0);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\ncallq 10a0 \nlea 0x1(%rax),%rdi\nmov %rax,%rbp\ncallq 10c0 \nmov %rax,%r12\ntest %rax,%rax\nje 1337 \ntest %rbp,%rbp\nje 1340 \ncallq 10d0 <__ctype_b_loc@plt>\nmov %rbx,%rdi\nlea (%rbx,%rbp,1),%r9\nxor %r8d,%r8d\nmov (%rax),%r10\nmov %r12,%rax\nxchg %ax,%ax\nmovzbl (%rdi),%ecx\nmov %rax,%rsi\ntestb $0x1,0x1(%r10,%rcx,2)\njne 132b \nadd $0x1,%r8\nmov %cl,(%rax)\nlea (%r12,%r8,1),%rax\nmov %rax,%rsi\nadd $0x1,%rdi\ncmp %rdi,%r9\njne 1310 \nmovb $0x0,(%rsi)\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\nretq\nmov %rax,%rsi\njmp 1334 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbx, rdi\ncall _strlen\nlea rdi, [rax+1]; size\nmov rbp, rax\ncall _malloc\nmov r12, rax\ntest rax, rax\njz short loc_1342\ntest rbp, rbp\njz short loc_1350\ncall ___ctype_b_loc\nlea rdi, [rbx+rbp]\nxor esi, esi\nmov r8, [rax]\nmov rax, rbx\nnop word ptr [rax+rax+00h]\nloc_1320:\nmovzx ecx, byte ptr [rax]\ntest byte ptr [r8+rcx*2+1], 1\njnz short loc_1333\nmov [r12+rsi], cl\nadd rsi, 1\nloc_1333:\nadd rax, 1\ncmp rdi, rax\njnz short loc_1320\nadd rsi, r12\nloc_133F:\nmov byte ptr [rsi], 0\nloc_1342:\nmov rax, r12\npop rbx\npop rbp\npop r12\nretn\nloc_1350:\nmov rsi, rax\njmp short loc_133F", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1)\n{\n size_t v2; // rbp\n _BYTE *v3; // rax\n _BYTE *v4; // r12\n unsigned __int8 *v5; // rdi\n __int64 v6; // rsi\n const unsigned __int16 *v7; // r8\n const char *v8; // rax\n __int64 v9; // rcx\n _BYTE *v10; // rsi\n\n v2 = strlen(a1);\n v3 = malloc(v2 + 1);\n v4 = v3;\n if ( v3 )\n {\n if ( v2 )\n {\n v5 = (unsigned __int8 *)&a1[v2];\n v6 = 0LL;\n v7 = *__ctype_b_loc();\n v8 = a1;\n do\n {\n v9 = *(unsigned __int8 *)v8;\n if ( (v7[v9] & 0x100) == 0 )\n v4[v6++] = v9;\n ++v8;\n }\n while ( v5 != (unsigned __int8 *)v8 );\n v10 = &v4[v6];\n }\n else\n {\n v10 = v3;\n }\n *v10 = 0;\n }\n return v4;\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbx, rdi\ncall _strlen\nlea rdi, [rax+1]; size\nmov rbp, rax\ncall _malloc\nmov r12, rax\ntest rax, rax\njz short loc_1342\ntest rbp, rbp\njz short loc_1350\ncall ___ctype_b_loc\nlea rdi, [rbx+rbp]\nxor esi, esi\nmov r8, [rax]\nmov rax, rbx\nnop word ptr [rax+rax+00h]\nloc_1320:\nmovzx ecx, byte ptr [rax]\ntest byte ptr [r8+rcx*2+1], 1\njnz short loc_1333\nmov [r12+rsi], cl\nadd rsi, 1\nloc_1333:\nadd rax, 1\ncmp rdi, rax\njnz short loc_1320\nadd rsi, r12\nloc_133F:\nmov byte ptr [rsi], 0\nloc_1342:\nmov rax, r12\npop rbx\npop rbp\npop r12\nretn\nloc_1350:\nmov rsi, rax\njmp short loc_133F", + "ida_strip_pseudo": "_BYTE *__fastcall sub_12E0(const char *a1)\n{\n size_t v2; // rbp\n _BYTE *v3; // rax\n _BYTE *v4; // r12\n unsigned __int8 *v5; // rdi\n __int64 v6; // rsi\n const unsigned __int16 *v7; // r8\n const char *v8; // rax\n __int64 v9; // rcx\n _BYTE *v10; // rsi\n\n v2 = strlen(a1);\n v3 = malloc(v2 + 1);\n v4 = v3;\n if ( v3 )\n {\n if ( v2 )\n {\n v5 = (unsigned __int8 *)&a1[v2];\n v6 = 0LL;\n v7 = *__ctype_b_loc();\n v8 = a1;\n do\n {\n v9 = *(unsigned __int8 *)v8;\n if ( (v7[v9] & 0x100) == 0 )\n v4[v6++] = v9;\n ++v8;\n }\n while ( v5 != (unsigned __int8 *)v8 );\n v10 = &v4[v6];\n }\n else\n {\n v10 = v3;\n }\n *v10 = 0;\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_12E0(const char *a1) {\n unsigned int v2;\n uint8_t *v3;\n uint8_t *v4;\n unsigned char *v5;\n long long v6;\n const unsigned short *v7;\n const char *v8;\n long long v9;\n uint8_t *v10;\n v2 = strlen(a1);\n v3 = malloc(v2 + 1);\n v4 = v3;\n if (v3) {\n if (v2) {\n v5 = (unsigned char *)&a1[v2];\n v6 = 0LL;\n v7 = *__ctype_b_loc();\n v8 = a1;\n do {\n v9 = *(unsigned char *)v8;\n if ((v7[v9] & 256) == 0) v4[v6++] = v9;\n ++v8;\n } while (v5 != (unsigned char *)v8);\n v10 = &v4[v6];\n } else {\n v10 = v3;\n }\n *v10 = 0;\n }\n return v4;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1) {\n unsigned int v2;\n uint8_t *v3;\n uint8_t *v4;\n unsigned char *v5;\n long long v6;\n const unsigned short *v7;\n const char *v8;\n long long v9;\n uint8_t *v10;\n v2 = strlen(a1);\n v3 = malloc(v2 + 1);\n v4 = v3;\n if (v3) {\n if (v2) {\n v5 = (unsigned char *)&a1[v2];\n v6 = 0LL;\n v7 = *__ctype_b_loc();\n v8 = a1;\n do {\n v9 = *(unsigned char *)v8;\n if ((v7[v9] & 256) == 0) v4[v6++] = v9;\n ++v8;\n } while (v5 != (unsigned char *)v8);\n v10 = &v4[v6];\n } else {\n v10 = v3;\n }\n *v10 = 0;\n }\n return v4;\n}" + }, + { + "index": 459, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* str1) {\n size_t len = strlen(str1);\n char* result = malloc(len + 1);\n if (!result) return NULL;\n size_t j = 0;\n for (size_t i = 0; i < len; i++) {\n if (!isupper((unsigned char)str1[i])) {\n result[j++] = str1[i];\n }\n }\n result[j] = '\\0';\n return result;\n}", + "test": "int main() {\n\n char* res1 = func0(\"cAstyoUrFavoRitETVshoWs\");\n\n assert(strcmp(res1, \"cstyoravoitshos\") == 0);\n\n free(res1);\n\n\n\n char* res2 = func0(\"wAtchTheinTernEtrAdIo\");\n\n assert(strcmp(res2, \"wtchheinerntrdo\") == 0);\n\n free(res2);\n\n\n\n char* res3 = func0(\"VoicESeaRchAndreComMendaTionS\");\n\n assert(strcmp(res3, \"oiceachndreomendaion\") == 0);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\ncallq 10a0 \nlea 0x1(%rax),%rdi\nmov %rax,%rbp\ncallq 10c0 \nmov %rax,%r12\ntest %rax,%rax\nje 1337 \ntest %rbp,%rbp\nje 1340 \ncallq 10d0 <__ctype_b_loc@plt>\nmov %rbx,%rdi\nlea (%rbx,%rbp,1),%r9\nxor %r8d,%r8d\nmov (%rax),%r10\nmov %r12,%rax\nxchg %ax,%ax\nmovzbl (%rdi),%ecx\nmov %rax,%rsi\ntestb $0x1,0x1(%r10,%rcx,2)\njne 132b \nadd $0x1,%r8\nmov %cl,(%rax)\nlea (%r12,%r8,1),%rax\nmov %rax,%rsi\nadd $0x1,%rdi\ncmp %rdi,%r9\njne 1310 \nmovb $0x0,(%rsi)\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\nretq\nmov %rax,%rsi\njmp 1334 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbx, rdi\ncall _strlen\nlea rdi, [rax+1]; size\nmov rbp, rax\ncall _malloc\nmov r12, rax\ntest rax, rax\njz short loc_1342\ntest rbp, rbp\njz short loc_1350\ncall ___ctype_b_loc\nlea rdi, [rbx+rbp]\nxor esi, esi\nmov r8, [rax]\nmov rax, rbx\nnop word ptr [rax+rax+00h]\nloc_1320:\nmovzx ecx, byte ptr [rax]\ntest byte ptr [r8+rcx*2+1], 1\njnz short loc_1333\nmov [r12+rsi], cl\nadd rsi, 1\nloc_1333:\nadd rax, 1\ncmp rdi, rax\njnz short loc_1320\nadd rsi, r12\nloc_133F:\nmov byte ptr [rsi], 0\nloc_1342:\nmov rax, r12\npop rbx\npop rbp\npop r12\nretn\nloc_1350:\nmov rsi, rax\njmp short loc_133F", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1)\n{\n size_t v2; // rbp\n _BYTE *v3; // rax\n _BYTE *v4; // r12\n unsigned __int8 *v5; // rdi\n __int64 v6; // rsi\n const unsigned __int16 *v7; // r8\n const char *v8; // rax\n __int64 v9; // rcx\n _BYTE *v10; // rsi\n\n v2 = strlen(a1);\n v3 = malloc(v2 + 1);\n v4 = v3;\n if ( v3 )\n {\n if ( v2 )\n {\n v5 = (unsigned __int8 *)&a1[v2];\n v6 = 0LL;\n v7 = *__ctype_b_loc();\n v8 = a1;\n do\n {\n v9 = *(unsigned __int8 *)v8;\n if ( (v7[v9] & 0x100) == 0 )\n v4[v6++] = v9;\n ++v8;\n }\n while ( v5 != (unsigned __int8 *)v8 );\n v10 = &v4[v6];\n }\n else\n {\n v10 = v3;\n }\n *v10 = 0;\n }\n return v4;\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbx, rdi\ncall _strlen\nlea rdi, [rax+1]; size\nmov rbp, rax\ncall _malloc\nmov r12, rax\ntest rax, rax\njz short loc_1342\ntest rbp, rbp\njz short loc_1350\ncall ___ctype_b_loc\nlea rdi, [rbx+rbp]\nxor esi, esi\nmov r8, [rax]\nmov rax, rbx\nnop word ptr [rax+rax+00h]\nloc_1320:\nmovzx ecx, byte ptr [rax]\ntest byte ptr [r8+rcx*2+1], 1\njnz short loc_1333\nmov [r12+rsi], cl\nadd rsi, 1\nloc_1333:\nadd rax, 1\ncmp rdi, rax\njnz short loc_1320\nadd rsi, r12\nloc_133F:\nmov byte ptr [rsi], 0\nloc_1342:\nmov rax, r12\npop rbx\npop rbp\npop r12\nretn\nloc_1350:\nmov rsi, rax\njmp short loc_133F", + "ida_strip_pseudo": "_BYTE *__fastcall sub_12E0(const char *a1)\n{\n size_t v2; // rbp\n _BYTE *v3; // rax\n _BYTE *v4; // r12\n unsigned __int8 *v5; // rdi\n __int64 v6; // rsi\n const unsigned __int16 *v7; // r8\n const char *v8; // rax\n __int64 v9; // rcx\n _BYTE *v10; // rsi\n\n v2 = strlen(a1);\n v3 = malloc(v2 + 1);\n v4 = v3;\n if ( v3 )\n {\n if ( v2 )\n {\n v5 = (unsigned __int8 *)&a1[v2];\n v6 = 0LL;\n v7 = *__ctype_b_loc();\n v8 = a1;\n do\n {\n v9 = *(unsigned __int8 *)v8;\n if ( (v7[v9] & 0x100) == 0 )\n v4[v6++] = v9;\n ++v8;\n }\n while ( v5 != (unsigned __int8 *)v8 );\n v10 = &v4[v6];\n }\n else\n {\n v10 = v3;\n }\n *v10 = 0;\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_12E0(const char *a1) {\n unsigned int v2;\n uint8_t *v3;\n uint8_t *v4;\n unsigned char *v5;\n long long v6;\n const unsigned short *v7;\n const char *v8;\n long long v9;\n uint8_t *v10;\n v2 = strlen(a1);\n v3 = malloc(v2 + 1);\n v4 = v3;\n if (v3) {\n if (v2) {\n v5 = (unsigned char *)&a1[v2];\n v6 = 0LL;\n v7 = *__ctype_b_loc();\n v8 = a1;\n do {\n v9 = *(unsigned char *)v8;\n if ((v7[v9] & 256) == 0) v4[v6++] = v9;\n ++v8;\n } while (v5 != (unsigned char *)v8);\n v10 = &v4[v6];\n } else {\n v10 = v3;\n }\n *v10 = 0;\n }\n return v4;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1) {\n unsigned int v2;\n uint8_t *v3;\n uint8_t *v4;\n unsigned char *v5;\n long long v6;\n const unsigned short *v7;\n const char *v8;\n long long v9;\n uint8_t *v10;\n v2 = strlen(a1);\n v3 = malloc(v2 + 1);\n v4 = v3;\n if (v3) {\n if (v2) {\n v5 = (unsigned char *)&a1[v2];\n v6 = 0LL;\n v7 = *__ctype_b_loc();\n v8 = a1;\n do {\n v9 = *(unsigned char *)v8;\n if ((v7[v9] & 256) == 0) v4[v6++] = v9;\n ++v8;\n } while (v5 != (unsigned char *)v8);\n v10 = &v4[v6];\n } else {\n v10 = v3;\n }\n *v10 = 0;\n }\n return v4;\n}" + }, + { + "index": 460, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int** lst, int* sizes, int count) {\n int* result = malloc(count * sizeof(int));\n for (int i = 0; i < count; i++) {\n result[i] = lst[i][0];\n }\n return result;\n}", + "test": "int main() {\n\n // First test case\n\n int arr1_0[] = {1, 2};\n\n int arr1_1[] = {3, 4, 5};\n\n int arr1_2[] = {6, 7, 8, 9};\n\n int* lst1[] = {arr1_0, arr1_1, arr1_2};\n\n int sizes1[] = {2, 3, 4};\n\n int expected1[] = {1, 3, 6};\n\n int* res1 = func0(lst1, sizes1, 3);\n\n assert(memcmp(res1, expected1, 3 * sizeof(int)) == 0);\n\n free(res1);\n\n\n\n // Second test case\n\n int arr2_0[] = {1, 2, 3};\n\n int arr2_1[] = {4, 5};\n\n int* lst2[] = {arr2_0, arr2_1};\n\n int sizes2[] = {3, 2};\n\n int expected2[] = {1, 4};\n\n int* res2 = func0(lst2, sizes2, 2);\n\n assert(memcmp(res2, expected2, 2 * sizeof(int)) == 0);\n\n free(res2);\n\n\n\n // Third test case\n\n int arr3_0[] = {9, 8, 1};\n\n int arr3_1[] = {1, 2};\n\n int* lst3[] = {arr3_0, arr3_1};\n\n int sizes3[] = {3, 2};\n\n int expected3[] = {9, 1};\n\n int* res3 = func0(lst3, sizes3, 2);\n\n assert(memcmp(res3, expected3, 2 * sizeof(int)) == 0);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %edx,-0x24(%rbp)\nmov -0x24(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 1232 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0xc(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x24(%rbp),%eax\njl 11fe \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov eax, [rbp+var_24]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp short loc_1232\nloc_11FE:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_C], 1\nloc_1232:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_24]\njl short loc_11FE\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n int i; // [rsp+24h] [rbp-Ch]\n _DWORD *v6; // [rsp+28h] [rbp-8h]\n\n v6 = malloc(4LL * a3);\n for ( i = 0; i < a3; ++i )\n v6[i] = **(_DWORD **)(8LL * i + a1);\n return v6;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov eax, [rbp+var_24]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp short loc_1232\nloc_11FE:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_C], 1\nloc_1232:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_24]\njl short loc_11FE\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11C9(__int64 a1, __int64 a2, int a3)\n{\n int i; // [rsp+24h] [rbp-Ch]\n _DWORD *v6; // [rsp+28h] [rbp-8h]\n\n v6 = malloc(4LL * a3);\n for ( i = 0; i < a3; ++i )\n v6[i] = **(_DWORD **)(8LL * i + a1);\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11C9(long long a1, long long a2, int a3) {\n int i;\n uint32_t *v6;\n v6 = malloc(4LL * a3);\n for (i = 0; i < a3; ++i) v6[i] = **(uint32_t **)(8LL * i + a1);\n return v6;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, long long a2, int a3) {\n int i;\n uint32_t *v6;\n v6 = malloc(4LL * a3);\n for (i = 0; i < a3; ++i) v6[i] = **(uint32_t **)(8LL * i + a1);\n return v6;\n}" + }, + { + "index": 460, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int** lst, int* sizes, int count) {\n int* result = malloc(count * sizeof(int));\n for (int i = 0; i < count; i++) {\n result[i] = lst[i][0];\n }\n return result;\n}", + "test": "int main() {\n\n // First test case\n\n int arr1_0[] = {1, 2};\n\n int arr1_1[] = {3, 4, 5};\n\n int arr1_2[] = {6, 7, 8, 9};\n\n int* lst1[] = {arr1_0, arr1_1, arr1_2};\n\n int sizes1[] = {2, 3, 4};\n\n int expected1[] = {1, 3, 6};\n\n int* res1 = func0(lst1, sizes1, 3);\n\n assert(memcmp(res1, expected1, 3 * sizeof(int)) == 0);\n\n free(res1);\n\n\n\n // Second test case\n\n int arr2_0[] = {1, 2, 3};\n\n int arr2_1[] = {4, 5};\n\n int* lst2[] = {arr2_0, arr2_1};\n\n int sizes2[] = {3, 2};\n\n int expected2[] = {1, 4};\n\n int* res2 = func0(lst2, sizes2, 2);\n\n assert(memcmp(res2, expected2, 2 * sizeof(int)) == 0);\n\n free(res2);\n\n\n\n // Third test case\n\n int arr3_0[] = {9, 8, 1};\n\n int arr3_1[] = {1, 2};\n\n int* lst3[] = {arr3_0, arr3_1};\n\n int sizes3[] = {3, 2};\n\n int expected3[] = {9, 1};\n\n int* res3 = func0(lst3, sizes3, 2);\n\n assert(memcmp(res3, expected3, 2 * sizeof(int)) == 0);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbx\nmov %edx,%ebp\nmovslq %edx,%rdi\nshl $0x2,%rdi\ncallq 10d0 \ntest %ebp,%ebp\njle 1205 \nlea -0x1(%rbp),%esi\nmov $0x0,%edx\nmov (%rbx,%rdx,8),%rcx\nmov (%rcx),%ecx\nmov %ecx,(%rax,%rdx,4)\nmov %rdx,%rcx\nadd $0x1,%rdx\ncmp %rsi,%rcx\njne 11f0 \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nmov r12d, edx\nmovsxd rbp, edx\nlea rdi, ds:0[rbp*4]; size\ncall _malloc\ntest r12d, r12d\njle short loc_1203\nmov edx, 0\nloc_11F1:\nmov rcx, [rbx+rdx*8]\nmov ecx, [rcx]\nmov [rax+rdx*4], ecx\nadd rdx, 1\ncmp rbp, rdx\njnz short loc_11F1\nloc_1203:\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n __int64 v4; // rbp\n _DWORD *result; // rax\n __int64 v6; // rdx\n\n v4 = a3;\n result = malloc(4LL * a3);\n if ( a3 > 0 )\n {\n v6 = 0LL;\n do\n {\n result[v6] = **(_DWORD **)(a1 + 8 * v6);\n ++v6;\n }\n while ( v4 != v6 );\n }\n return result;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nmov r12d, edx\nmovsxd rbp, edx\nlea rdi, ds:0[rbp*4]; size\ncall _malloc\ntest r12d, r12d\njle short loc_1203\nmov edx, 0\nloc_11F1:\nmov rcx, [rbx+rdx*8]\nmov ecx, [rcx]\nmov [rax+rdx*4], ecx\nadd rdx, 1\ncmp rbp, rdx\njnz short loc_11F1\nloc_1203:\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11C9(__int64 a1, __int64 a2, int a3)\n{\n __int64 v4; // rbp\n _DWORD *result; // rax\n __int64 v6; // rdx\n\n v4 = a3;\n result = malloc(4LL * a3);\n if ( a3 > 0 )\n {\n v6 = 0LL;\n do\n {\n result[v6] = **(_DWORD **)(a1 + 8 * v6);\n ++v6;\n }\n while ( v4 != v6 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11C9(long long a1, long long a2, int a3) {\n long long v4;\n uint32_t *result;\n long long v6;\n v4 = a3;\n result = malloc(4LL * a3);\n if (a3 > 0) {\n v6 = 0LL;\n do {\n result[v6] = **(uint32_t **)(a1 + 8 * v6);\n ++v6;\n } while (v4 != v6);\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, long long a2, int a3) {\n long long v4;\n uint32_t *result;\n long long v6;\n v4 = a3;\n result = malloc(4LL * a3);\n if (a3 > 0) {\n v6 = 0LL;\n do {\n result[v6] = **(uint32_t **)(a1 + 8 * v6);\n ++v6;\n } while (v4 != v6);\n }\n return result;\n}" + }, + { + "index": 460, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int** lst, int* sizes, int count) {\n int* result = malloc(count * sizeof(int));\n for (int i = 0; i < count; i++) {\n result[i] = lst[i][0];\n }\n return result;\n}", + "test": "int main() {\n\n // First test case\n\n int arr1_0[] = {1, 2};\n\n int arr1_1[] = {3, 4, 5};\n\n int arr1_2[] = {6, 7, 8, 9};\n\n int* lst1[] = {arr1_0, arr1_1, arr1_2};\n\n int sizes1[] = {2, 3, 4};\n\n int expected1[] = {1, 3, 6};\n\n int* res1 = func0(lst1, sizes1, 3);\n\n assert(memcmp(res1, expected1, 3 * sizeof(int)) == 0);\n\n free(res1);\n\n\n\n // Second test case\n\n int arr2_0[] = {1, 2, 3};\n\n int arr2_1[] = {4, 5};\n\n int* lst2[] = {arr2_0, arr2_1};\n\n int sizes2[] = {3, 2};\n\n int expected2[] = {1, 4};\n\n int* res2 = func0(lst2, sizes2, 2);\n\n assert(memcmp(res2, expected2, 2 * sizeof(int)) == 0);\n\n free(res2);\n\n\n\n // Third test case\n\n int arr3_0[] = {9, 8, 1};\n\n int arr3_1[] = {1, 2};\n\n int* lst3[] = {arr3_0, arr3_1};\n\n int sizes3[] = {3, 2};\n\n int expected3[] = {9, 1};\n\n int* res3 = func0(lst3, sizes3, 2);\n\n assert(memcmp(res3, expected3, 2 * sizeof(int)) == 0);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nmov %rdi,%rbx\nmovslq %edx,%rdi\nmov %rdi,%rbp\nshl $0x2,%rdi\nsub $0x8,%rsp\ncallq 10b0 \ntest %ebp,%ebp\njle 145d \nlea -0x1(%rbp),%esi\nxor %edx,%edx\nnopl (%rax)\nmov (%rbx,%rdx,8),%rcx\nmov (%rcx),%ecx\nmov %ecx,(%rax,%rdx,4)\nmov %rdx,%rcx\nadd $0x1,%rdx\ncmp %rcx,%rsi\njne 1448 \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\nmovsxd rbp, edx\npush rbx\nmov rbx, rdi\nlea rdi, ds:0[rbp*4]; size\ncall _malloc\ntest ebp, ebp\njle short loc_141A\nxor edx, edx\nnop dword ptr [rax+00000000h]\nloc_1408:\nmov rcx, [rbx+rdx*8]\nmov ecx, [rcx]\nmov [rax+rdx*4], ecx\nadd rdx, 1\ncmp rbp, rdx\njnz short loc_1408\nloc_141A:\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n __int64 v3; // rbp\n _DWORD *result; // rax\n __int64 i; // rdx\n\n v3 = a3;\n result = malloc(4LL * a3);\n if ( (int)v3 > 0 )\n {\n for ( i = 0LL; i != v3; ++i )\n result[i] = **(_DWORD **)(a1 + 8 * i);\n }\n return result;\n}", + "ida_strip_asm": "sub_13E0:\nendbr64\npush r12\npush rbp\nmovsxd rbp, edx\npush rbx\nmov rbx, rdi\nlea rdi, ds:0[rbp*4]; size\ncall _malloc\ntest ebp, ebp\njle short loc_141A\nxor edx, edx\nnop dword ptr [rax+00000000h]\nloc_1408:\nmov rcx, [rbx+rdx*8]\nmov ecx, [rcx]\nmov [rax+rdx*4], ecx\nadd rdx, 1\ncmp rbp, rdx\njnz short loc_1408\nloc_141A:\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_13E0(__int64 a1, __int64 a2, int a3)\n{\n __int64 v3; // rbp\n _DWORD *result; // rax\n __int64 i; // rdx\n\n v3 = a3;\n result = malloc(4LL * a3);\n if ( (int)v3 > 0 )\n {\n for ( i = 0LL; i != v3; ++i )\n result[i] = **(_DWORD **)(a1 + 8 * i);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_13E0(long long a1, long long a2, int a3) {\n long long v3;\n uint32_t *result;\n long long i;\n v3 = a3;\n result = malloc(4LL * a3);\n if ((int)v3 > 0) {\n for (i = 0LL; i != v3; ++i) result[i] = **(uint32_t **)(a1 + 8 * i);\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, long long a2, int a3) {\n long long v3;\n uint32_t *result;\n long long i;\n v3 = a3;\n result = malloc(4LL * a3);\n if ((int)v3 > 0) {\n for (i = 0LL; i != v3; ++i) result[i] = **(uint32_t **)(a1 + 8 * i);\n }\n return result;\n}" + }, + { + "index": 460, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int** lst, int* sizes, int count) {\n int* result = malloc(count * sizeof(int));\n for (int i = 0; i < count; i++) {\n result[i] = lst[i][0];\n }\n return result;\n}", + "test": "int main() {\n\n // First test case\n\n int arr1_0[] = {1, 2};\n\n int arr1_1[] = {3, 4, 5};\n\n int arr1_2[] = {6, 7, 8, 9};\n\n int* lst1[] = {arr1_0, arr1_1, arr1_2};\n\n int sizes1[] = {2, 3, 4};\n\n int expected1[] = {1, 3, 6};\n\n int* res1 = func0(lst1, sizes1, 3);\n\n assert(memcmp(res1, expected1, 3 * sizeof(int)) == 0);\n\n free(res1);\n\n\n\n // Second test case\n\n int arr2_0[] = {1, 2, 3};\n\n int arr2_1[] = {4, 5};\n\n int* lst2[] = {arr2_0, arr2_1};\n\n int sizes2[] = {3, 2};\n\n int expected2[] = {1, 4};\n\n int* res2 = func0(lst2, sizes2, 2);\n\n assert(memcmp(res2, expected2, 2 * sizeof(int)) == 0);\n\n free(res2);\n\n\n\n // Third test case\n\n int arr3_0[] = {9, 8, 1};\n\n int arr3_1[] = {1, 2};\n\n int* lst3[] = {arr3_0, arr3_1};\n\n int sizes3[] = {3, 2};\n\n int expected3[] = {9, 1};\n\n int* res3 = func0(lst3, sizes3, 2);\n\n assert(memcmp(res3, expected3, 2 * sizeof(int)) == 0);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nmov %rdi,%rbx\nmovslq %edx,%rdi\nmov %rdi,%rbp\nshl $0x2,%rdi\nsub $0x8,%rsp\ncallq 10b0 \ntest %ebp,%ebp\njle 145d \nlea -0x1(%rbp),%esi\nxor %edx,%edx\nnopl (%rax)\nmov (%rbx,%rdx,8),%rcx\nmov (%rcx),%ecx\nmov %ecx,(%rax,%rdx,4)\nmov %rdx,%rcx\nadd $0x1,%rdx\ncmp %rsi,%rcx\njne 1448 \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\nmovsxd rbp, edx\npush rbx\nmov rbx, rdi\nlea rdi, ds:0[rbp*4]; size\ncall _malloc\ntest ebp, ebp\njle short loc_141A\nxor edx, edx\nnop dword ptr [rax+00000000h]\nloc_1408:\nmov rcx, [rbx+rdx*8]\nmov ecx, [rcx]\nmov [rax+rdx*4], ecx\nadd rdx, 1\ncmp rbp, rdx\njnz short loc_1408\nloc_141A:\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n __int64 v3; // rbp\n _DWORD *result; // rax\n __int64 i; // rdx\n\n v3 = a3;\n result = malloc(4LL * a3);\n if ( (int)v3 > 0 )\n {\n for ( i = 0LL; i != v3; ++i )\n result[i] = **(_DWORD **)(a1 + 8 * i);\n }\n return result;\n}", + "ida_strip_asm": "sub_13E0:\nendbr64\npush r12\npush rbp\nmovsxd rbp, edx\npush rbx\nmov rbx, rdi\nlea rdi, ds:0[rbp*4]; size\ncall _malloc\ntest ebp, ebp\njle short loc_141A\nxor edx, edx\nnop dword ptr [rax+00000000h]\nloc_1408:\nmov rcx, [rbx+rdx*8]\nmov ecx, [rcx]\nmov [rax+rdx*4], ecx\nadd rdx, 1\ncmp rbp, rdx\njnz short loc_1408\nloc_141A:\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_13E0(__int64 a1, __int64 a2, int a3)\n{\n __int64 v3; // rbp\n _DWORD *result; // rax\n __int64 i; // rdx\n\n v3 = a3;\n result = malloc(4LL * a3);\n if ( (int)v3 > 0 )\n {\n for ( i = 0LL; i != v3; ++i )\n result[i] = **(_DWORD **)(a1 + 8 * i);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_13E0(long long a1, long long a2, int a3) {\n long long v3;\n uint32_t *result;\n long long i;\n v3 = a3;\n result = malloc(4LL * a3);\n if ((int)v3 > 0) {\n for (i = 0LL; i != v3; ++i) result[i] = **(uint32_t **)(a1 + 8 * i);\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, long long a2, int a3) {\n long long v3;\n uint32_t *result;\n long long i;\n v3 = a3;\n result = malloc(4LL * a3);\n if ((int)v3 > 0) {\n for (i = 0LL; i != v3; ++i) result[i] = **(uint32_t **)(a1 + 8 * i);\n }\n return result;\n}" + }, + { + "index": 461, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n", + "func": "int func0(const char *str) {\n int upper_ctr = 0;\n for (int i = 0; i < strlen(str); i++) {\n if (str[i] >= 'A' && str[i] <= 'Z') upper_ctr += 1;\n return upper_ctr;\n }\n}", + "test": "int main() {\n\n assert(func0(\"PYthon\") == 1);\n\n assert(func0(\"BigData\") == 1);\n\n assert(func0(\"program\") == 0);\n\n return 0;\n\n} \n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x28,%rsp\nmov %rdi,-0x28(%rbp)\nmovl $0x0,-0x18(%rbp)\nmovl $0x0,-0x14(%rbp)\nmov -0x14(%rbp),%eax\nmovslq %eax,%rbx\nmov -0x28(%rbp),%rax\nmov %rax,%rdi\ncallq 1060 \ncmp %rax,%rbx\njae 11d1 \nmov -0x14(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x40,%al\njle 11cc \nmov -0x14(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x5a,%al\njg 11cc \naddl $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%eax\njmp 11d1 \nadd $0x28,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+s], rdi\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\nnop\nmov eax, [rbp+var_14]\nmovsxd rbx, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rbx, rax\njnb short loc_11D1\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 40h ; '@'\njle short loc_11CC\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 5Ah ; 'Z'\njg short loc_11CC\nadd [rbp+var_18], 1\nloc_11CC:\nmov eax, [rbp+var_18]\njmp short $+2\nloc_11D1:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "size_t __fastcall func0(const char *a1)\n{\n size_t result; // rax\n unsigned int v2; // [rsp+18h] [rbp-18h]\n\n v2 = 0;\n result = strlen(a1);\n if ( result )\n {\n if ( *a1 > 64 )\n return *a1 <= 90;\n return v2;\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+s], rdi\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\nnop\nmov eax, [rbp+var_14]\nmovsxd rbx, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rbx, rax\njnb short loc_11D1\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 40h ; '@'\njle short loc_11CC\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 5Ah ; 'Z'\njg short loc_11CC\nadd [rbp+var_18], 1\nloc_11CC:\nmov eax, [rbp+var_18]\njmp short $+2\nloc_11D1:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "size_t __fastcall sub_1169(const char *a1)\n{\n size_t result; // rax\n unsigned int v2; // [rsp+18h] [rbp-18h]\n\n v2 = 0;\n result = strlen(a1);\n if ( result )\n {\n if ( *a1 > 64 )\n return *a1 <= 90;\n return v2;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned int sub_1169(const char *a1) {\n unsigned int result;\n unsigned int v2;\n v2 = 0;\n result = strlen(a1);\n if (result) {\n if (*a1 > 64) return *a1 <= 90;\n return v2;\n }\n return result;\n}", + "ida_pseudo_norm": "unsigned int func0(const char *a1) {\n unsigned int result;\n unsigned int v2;\n v2 = 0;\n result = strlen(a1);\n if (result) {\n if (*a1 > 64) return *a1 <= 90;\n return v2;\n }\n return result;\n}" + }, + { + "index": 461, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n", + "func": "int func0(const char *str) {\n int upper_ctr = 0;\n for (int i = 0; i < strlen(str); i++) {\n if (str[i] >= 'A' && str[i] <= 'Z') upper_ctr += 1;\n return upper_ctr;\n }\n}", + "test": "int main() {\n\n assert(func0(\"PYthon\") == 1);\n\n assert(func0(\"BigData\") == 1);\n\n assert(func0(\"program\") == 0);\n\n return 0;\n\n} \n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%rdx\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\ncmp $0xfffffffffffffffe,%rcx\nje 1173 \nmovzbl (%rdx),%eax\nsub $0x41,%eax\ncmp $0x19,%al\nsetbe %al\nmovzbl %al,%eax\nretq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest rax, rax\njz short loc_1189\nmovzx eax, byte ptr [rbx]\nsub eax, 41h ; 'A'\ncmp al, 19h\nsetbe al\nmovzx eax, al\nloc_1189:\npop rbx\nretn", + "ida_pseudo": "size_t __fastcall func0(const char *a1)\n{\n size_t result; // rax\n\n result = strlen(a1);\n if ( result )\n return (unsigned __int8)(*a1 - 65) <= 0x19u;\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest rax, rax\njz short loc_1189\nmovzx eax, byte ptr [rbx]\nsub eax, 41h ; 'A'\ncmp al, 19h\nsetbe al\nmovzx eax, al\nloc_1189:\npop rbx\nretn", + "ida_strip_pseudo": "size_t __fastcall sub_1169(const char *a1)\n{\n size_t result; // rax\n\n result = strlen(a1);\n if ( result )\n return (unsigned __int8)(*a1 - 65) <= 0x19u;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned int sub_1169(const char *a1) {\n unsigned int result;\n result = strlen(a1);\n if (result) return (unsigned char)(*a1 - 65) <= 25u;\n return result;\n}", + "ida_pseudo_norm": "unsigned int func0(const char *a1) {\n unsigned int result;\n result = strlen(a1);\n if (result) return (unsigned char)(*a1 - 65) <= 25u;\n return result;\n}" + }, + { + "index": 461, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n", + "func": "int func0(const char *str) {\n int upper_ctr = 0;\n for (int i = 0; i < strlen(str); i++) {\n if (str[i] >= 'A' && str[i] <= 'Z') upper_ctr += 1;\n return upper_ctr;\n }\n}", + "test": "int main() {\n\n assert(func0(\"PYthon\") == 1);\n\n assert(func0(\"BigData\") == 1);\n\n assert(func0(\"program\") == 0);\n\n return 0;\n\n} \n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\ncallq 1060 \ntest %rax,%rax\nje 1230 \nmovzbl (%rbx),%eax\nsub $0x41,%eax\ncmp $0x19,%al\nsetbe %al\nmovzbl %al,%eax\npop %rbx\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest rax, rax\njz short loc_1230\nmovzx eax, byte ptr [rbx]\nsub eax, 41h ; 'A'\ncmp al, 19h\nsetbe al\nmovzx eax, al\nloc_1230:\npop rbx\nretn", + "ida_pseudo": "size_t __fastcall func0(const char *a1)\n{\n size_t result; // rax\n\n result = strlen(a1);\n if ( result )\n return (unsigned __int8)(*a1 - 65) <= 0x19u;\n return result;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest rax, rax\njz short loc_1230\nmovzx eax, byte ptr [rbx]\nsub eax, 41h ; 'A'\ncmp al, 19h\nsetbe al\nmovzx eax, al\nloc_1230:\npop rbx\nretn", + "ida_strip_pseudo": "size_t __fastcall sub_1210(const char *a1)\n{\n size_t result; // rax\n\n result = strlen(a1);\n if ( result )\n return (unsigned __int8)(*a1 - 65) <= 0x19u;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned int sub_1210(const char *a1) {\n unsigned int result;\n result = strlen(a1);\n if (result) return (unsigned char)(*a1 - 65) <= 25u;\n return result;\n}", + "ida_pseudo_norm": "unsigned int func0(const char *a1) {\n unsigned int result;\n result = strlen(a1);\n if (result) return (unsigned char)(*a1 - 65) <= 25u;\n return result;\n}" + }, + { + "index": 461, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n", + "func": "int func0(const char *str) {\n int upper_ctr = 0;\n for (int i = 0; i < strlen(str); i++) {\n if (str[i] >= 'A' && str[i] <= 'Z') upper_ctr += 1;\n return upper_ctr;\n }\n}", + "test": "int main() {\n\n assert(func0(\"PYthon\") == 1);\n\n assert(func0(\"BigData\") == 1);\n\n assert(func0(\"program\") == 0);\n\n return 0;\n\n} \n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\ncallq 1060 \ntest %rax,%rax\nje 1230 \nmovzbl (%rbx),%eax\nsub $0x41,%eax\ncmp $0x19,%al\nsetbe %al\nmovzbl %al,%eax\npop %rbx\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest rax, rax\njz short loc_1230\nmovzx eax, byte ptr [rbx]\nsub eax, 41h ; 'A'\ncmp al, 19h\nsetbe al\nmovzx eax, al\nloc_1230:\npop rbx\nretn", + "ida_pseudo": "size_t __fastcall func0(const char *a1)\n{\n size_t result; // rax\n\n result = strlen(a1);\n if ( result )\n return (unsigned __int8)(*a1 - 65) <= 0x19u;\n return result;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest rax, rax\njz short loc_1230\nmovzx eax, byte ptr [rbx]\nsub eax, 41h ; 'A'\ncmp al, 19h\nsetbe al\nmovzx eax, al\nloc_1230:\npop rbx\nretn", + "ida_strip_pseudo": "size_t __fastcall sub_1210(const char *a1)\n{\n size_t result; // rax\n\n result = strlen(a1);\n if ( result )\n return (unsigned __int8)(*a1 - 65) <= 0x19u;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned int sub_1210(const char *a1) {\n unsigned int result;\n result = strlen(a1);\n if (result) return (unsigned char)(*a1 - 65) <= 25u;\n return result;\n}", + "ida_pseudo_norm": "unsigned int func0(const char *a1) {\n unsigned int result;\n result = strlen(a1);\n if (result) return (unsigned char)(*a1 - 65) <= 25u;\n return result;\n}" + }, + { + "index": 462, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n#define MAX_COMBINATIONS 64\n\n#define MAX_ELEMENTS 6\n\n#define MAX_STRING_LENGTH 10\n\n\n\ntypedef struct {\n\n char elements[MAX_ELEMENTS][MAX_STRING_LENGTH];\n\n int size;\n\n} Combination;\n\n\n\ntypedef struct {\n\n Combination combinations[MAX_COMBINATIONS];\n\n int count;\n\n} CombinationList;\n\n\n\n// Function to generate combinations\n\nCombinationList combinations_list(char *list1[], int n) {\n\n CombinationList cl;\n\n cl.count = 0;\n\n int total = 1 << n; // 2^n combinations\n\n\n\n for(int i = 0; i < total; i++) {\n\n Combination comb;\n\n comb.size = 0;\n\n for(int j = 0; j < n; j++) {\n\n if(i & (1 << j)) {\n\n strcpy(comb.elements[comb.size++], list1[j]);\n\n }\n\n }\n\n cl.combinations[cl.count++] = comb;\n\n }\n\n return cl;\n\n}\n\n\n\n// Function to compare two CombinationLists\n\n", + "func": "int func0(CombinationList a, CombinationList b) {\n if (a.count != b.count) return 0;\n for (int i = 0; i < a.count; i++) {\n if (a.combinations[i].size != b.combinations[i].size) return 0;\n for (int j = 0; j < a.combinations[i].size; j++) {\n if (strcmp(a.combinations[i].elements[j],\n b.combinations[i].elements[j]) != 0)\n return 0;\n }\n }\n return 1;\n}", + "test": "int main() {\n\n // First assert\n\n char *list1[] = {\"orange\", \"red\", \"green\", \"blue\"};\n\n CombinationList result1 = combinations_list(list1, 4);\n\n CombinationList expected1;\n\n expected1.count = 16;\n\n // []\n\n expected1.combinations[0].size = 0;\n\n // ['orange']\n\n strcpy(expected1.combinations[1].elements[0], \"orange\");\n\n expected1.combinations[1].size = 1;\n\n // ['red']\n\n strcpy(expected1.combinations[2].elements[0], \"red\");\n\n expected1.combinations[2].size = 1;\n\n // ['red', 'orange']\n\n strcpy(expected1.combinations[3].elements[0], \"orange\");\n\n strcpy(expected1.combinations[3].elements[1], \"red\");\n\n expected1.combinations[3].size = 2;\n\n // ['green']\n\n strcpy(expected1.combinations[4].elements[0], \"green\");\n\n expected1.combinations[4].size = 1;\n\n // ['green', 'orange']\n\n strcpy(expected1.combinations[5].elements[0], \"orange\");\n\n strcpy(expected1.combinations[5].elements[1], \"green\");\n\n expected1.combinations[5].size = 2;\n\n // ['green', 'red']\n\n strcpy(expected1.combinations[6].elements[0], \"red\");\n\n strcpy(expected1.combinations[6].elements[1], \"green\");\n\n expected1.combinations[6].size = 2;\n\n // ['green', 'red', 'orange']\n\n strcpy(expected1.combinations[7].elements[0], \"orange\");\n\n strcpy(expected1.combinations[7].elements[1], \"red\");\n\n strcpy(expected1.combinations[7].elements[2], \"green\");\n\n expected1.combinations[7].size = 3;\n\n // ['blue']\n\n strcpy(expected1.combinations[8].elements[0], \"blue\");\n\n expected1.combinations[8].size = 1;\n\n // ['blue', 'orange']\n\n strcpy(expected1.combinations[9].elements[0], \"orange\");\n\n strcpy(expected1.combinations[9].elements[1], \"blue\");\n\n expected1.combinations[9].size = 2;\n\n // ['blue', 'red']\n\n strcpy(expected1.combinations[10].elements[0], \"red\");\n\n strcpy(expected1.combinations[10].elements[1], \"blue\");\n\n expected1.combinations[10].size = 2;\n\n // ['blue', 'red', 'orange']\n\n strcpy(expected1.combinations[11].elements[0], \"orange\");\n\n strcpy(expected1.combinations[11].elements[1], \"red\");\n\n strcpy(expected1.combinations[11].elements[2], \"blue\");\n\n expected1.combinations[11].size = 3;\n\n // ['blue', 'green']\n\n strcpy(expected1.combinations[12].elements[0], \"green\");\n\n strcpy(expected1.combinations[12].elements[1], \"blue\");\n\n expected1.combinations[12].size = 2;\n\n // ['blue', 'green', 'orange']\n\n strcpy(expected1.combinations[13].elements[0], \"orange\");\n\n strcpy(expected1.combinations[13].elements[1], \"green\");\n\n strcpy(expected1.combinations[13].elements[2], \"blue\");\n\n expected1.combinations[13].size = 3;\n\n // ['blue', 'green', 'red']\n\n strcpy(expected1.combinations[14].elements[0], \"red\");\n\n strcpy(expected1.combinations[14].elements[1], \"green\");\n\n strcpy(expected1.combinations[14].elements[2], \"blue\");\n\n expected1.combinations[14].size = 3;\n\n // ['blue', 'green', 'red', 'orange']\n\n strcpy(expected1.combinations[15].elements[0], \"orange\");\n\n strcpy(expected1.combinations[15].elements[1], \"red\");\n\n strcpy(expected1.combinations[15].elements[2], \"green\");\n\n strcpy(expected1.combinations[15].elements[3], \"blue\");\n\n expected1.combinations[15].size = 4;\n\n\n\n assert(func0(result1, expected1));\n\n\n\n // Second assert\n\n char *list2[] = {\"red\", \"green\", \"blue\", \"white\", \"black\", \"orange\"};\n\n CombinationList result2 = combinations_list(list2, 6);\n\n CombinationList expected2;\n\n expected2.count = 64;\n\n // Due to length, this part is omitted. In practice, you would fill expected2 with all 64 combinations.\n\n // For brevity, we'll assume it's correctly filled.\n\n // You need to manually fill each combination as per the Python assert.\n\n // ...\n\n\n\n // Third assert\n\n char *list3[] = {\"red\", \"green\", \"black\", \"orange\"};\n\n CombinationList result3 = combinations_list(list3, 4);\n\n CombinationList expected3;\n\n expected3.count = 16;\n\n // []\n\n expected3.combinations[0].size = 0;\n\n // ['red']\n\n strcpy(expected3.combinations[1].elements[0], \"red\");\n\n expected3.combinations[1].size = 1;\n\n // ['green']\n\n strcpy(expected3.combinations[2].elements[0], \"green\");\n\n expected3.combinations[2].size = 1;\n\n // ['green', 'red']\n\n strcpy(expected3.combinations[3].elements[0], \"red\");\n\n strcpy(expected3.combinations[3].elements[1], \"green\");\n\n expected3.combinations[3].size = 2;\n\n // ['black']\n\n strcpy(expected3.combinations[4].elements[0], \"black\");\n\n expected3.combinations[4].size = 1;\n\n // ['black', 'red']\n\n strcpy(expected3.combinations[5].elements[0], \"red\");\n\n strcpy(expected3.combinations[5].elements[1], \"black\");\n\n expected3.combinations[5].size = 2;\n\n // ['black', 'green']\n\n strcpy(expected3.combinations[6].elements[0], \"green\");\n\n strcpy(expected3.combinations[6].elements[1], \"black\");\n\n expected3.combinations[6].size = 2;\n\n // ['black', 'green', 'red']\n\n strcpy(expected3.combinations[7].elements[0], \"red\");\n\n strcpy(expected3.combinations[7].elements[1], \"green\");\n\n strcpy(expected3.combinations[7].elements[2], \"black\");\n\n expected3.combinations[7].size = 3;\n\n // ['orange']\n\n strcpy(expected3.combinations[8].elements[0], \"orange\");\n\n expected3.combinations[8].size = 1;\n\n // ['orange', 'red']\n\n strcpy(expected3.combinations[9].elements[0], \"red\");\n\n strcpy(expected3.combinations[9].elements[1], \"orange\");\n\n expected3.combinations[9].size = 2;\n\n // ['orange', 'green']\n\n strcpy(expected3.combinations[10].elements[0], \"green\");\n\n strcpy(expected3.combinations[10].elements[1], \"orange\");\n\n expected3.combinations[10].size = 2;\n\n // ['orange', 'green', 'red']\n\n strcpy(expected3.combinations[11].elements[0], \"red\");\n\n strcpy(expected3.combinations[11].elements[1], \"green\");\n\n strcpy(expected3.combinations[11].elements[2], \"orange\");\n\n expected3.combinations[11].size = 3;\n\n // ['orange', 'black']\n\n strcpy(expected3.combinations[12].elements[0], \"black\");\n\n strcpy(expected3.combinations[12].elements[1], \"orange\");\n\n expected3.combinations[12].size = 2;\n\n // ['orange', 'black', 'red']\n\n strcpy(expected3.combinations[13].elements[0], \"red\");\n\n strcpy(expected3.combinations[13].elements[1], \"black\");\n\n strcpy(expected3.combinations[13].elements[2], \"orange\");\n\n expected3.combinations[13].size = 3;\n\n // ['orange', 'black', 'green']\n\n strcpy(expected3.combinations[14].elements[0], \"green\");\n\n strcpy(expected3.combinations[14].elements[1], \"black\");\n\n strcpy(expected3.combinations[14].elements[2], \"orange\");\n\n expected3.combinations[14].size = 3;\n\n // ['orange', 'black', 'green', 'red']\n\n strcpy(expected3.combinations[15].elements[0], \"red\");\n\n strcpy(expected3.combinations[15].elements[1], \"green\");\n\n strcpy(expected3.combinations[15].elements[2], \"black\");\n\n strcpy(expected3.combinations[15].elements[3], \"orange\");\n\n expected3.combinations[15].size = 4;\n\n\n\n assert(func0(result3, expected3));\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov 0x1010(%rbp),%edx\nmov 0x2018(%rbp),%eax\ncmp %eax,%edx\nje 13da \nmov $0x0,%eax\njmpq 14cd \nmovl $0x0,-0x8(%rbp)\njmpq 14b9 \nmov -0x8(%rbp),%eax\ncltq\nshl $0x6,%rax\nlea 0x10(%rbp),%rsi\nadd %rsi,%rax\nadd $0x3c,%rax\nmov (%rax),%edx\nmov -0x8(%rbp),%eax\ncltq\nshl $0x6,%rax\nlea 0x10(%rbp),%rdi\nadd %rdi,%rax\nadd $0x1044,%rax\nmov (%rax),%eax\ncmp %eax,%edx\nje 1422 \nmov $0x0,%eax\njmpq 14cd \nmovl $0x0,-0x4(%rbp)\njmp 1496 \nlea 0x1018(%rbp),%rcx\nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nadd %rax,%rax\nmov -0x8(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x6,%rdx\nadd %rdx,%rax\nadd %rax,%rcx\nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nadd %rax,%rax\nmov -0x8(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x6,%rdx\nadd %rdx,%rax\nlea 0x10(%rbp),%rsi\nadd %rsi,%rax\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 10b0 \ntest %eax,%eax\nje 1492 \nmov $0x0,%eax\njmp 14cd \naddl $0x1,-0x4(%rbp)\nmov -0x8(%rbp),%eax\ncltq\nshl $0x6,%rax\nlea 0x10(%rbp),%rdi\nadd %rdi,%rax\nadd $0x3c,%rax\nmov (%rax),%eax\ncmp %eax,-0x4(%rbp)\njl 142b \naddl $0x1,-0x8(%rbp)\nmov 0x1010(%rbp),%eax\ncmp %eax,-0x8(%rbp)\njl 13e6 \nmov $0x1,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov edx, [rbp+arg_1000]\nmov eax, [rbp+arg_2008]\ncmp edx, eax\njz short loc_13D6\nmov eax, 0\njmp locret_14C9\nloc_13D6:\nmov [rbp+var_8], 0\njmp loc_14B5\nloc_13E2:\nmov eax, [rbp+var_8]\ncdqe\nshl rax, 6\nlea rax, [rax+10h]\nadd rax, rbp\nadd rax, 3Ch ; '<'\nmov edx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nshl rax, 6\nlea rax, [rax+10h]\nadd rax, rbp\nadd rax, 1044h\nmov eax, [rax]\ncmp edx, eax\njz short loc_141E\nmov eax, 0\njmp locret_14C9\nloc_141E:\nmov [rbp+var_4], 0\njmp short loc_1492\nloc_1427:\nlea rcx, [rbp+arg_1008]\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nadd rax, rax\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nshl rdx, 6\nadd rax, rdx\nadd rcx, rax\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nadd rax, rax\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nshl rdx, 6\nadd rax, rdx\nlea rax, [rax+10h]\nadd rax, rbp\nmov rsi, rcx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_148E\nmov eax, 0\njmp short locret_14C9\nloc_148E:\nadd [rbp+var_4], 1\nloc_1492:\nmov eax, [rbp+var_8]\ncdqe\nshl rax, 6\nlea rax, [rax+10h]\nadd rax, rbp\nadd rax, 3Ch ; '<'\nmov eax, [rax]\ncmp [rbp+var_4], eax\njl loc_1427\nadd [rbp+var_8], 1\nloc_14B5:\nmov eax, [rbp+arg_1000]\ncmp [rbp+var_8], eax\njl loc_13E2\nmov eax, 1\nlocret_14C9:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(\n __int64 a1,\n __int64 a2,\n __int64 a3,\n __int64 a4,\n __int64 a5,\n __int64 a6,\n __int64 a7,\n __int64 a8,\n __int64 a9,\n __int64 a10,\n __int64 a11,\n __int64 a12)\n{\n int i; // [rsp+8h] [rbp-8h]\n int j; // [rsp+Ch] [rbp-4h]\n __int64 savedregs; // [rsp+10h] [rbp+0h] BYREF\n\n if ( LODWORD(STACK[0x1020]) != LODWORD(STACK[0x2028]) )\n return 0LL;\n for ( i = 0; i < SLODWORD(STACK[0x1020]); ++i )\n {\n if ( *((_DWORD *)&a12 + 16 * (__int64)i + 5) != *((_DWORD *)&STACK[0x1054] + 16 * (__int64)i + 4) )\n return 0LL;\n for ( j = 0; j < *((_DWORD *)&a12 + 16 * (__int64)i + 5); ++j )\n {\n if ( strcmp(\n (const char *)&savedregs + 64 * (__int64)i + 10 * j + 16,\n (const char *)&STACK[0x1028] + 64 * (__int64)i + 10 * j) )\n {\n return 0LL;\n }\n }\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_13B0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov edx, [rbp+arg_1000]\nmov eax, [rbp+arg_2008]\ncmp edx, eax\njz short loc_13D6\nmov eax, 0\njmp locret_14C9\nloc_13D6:\nmov [rbp+var_8], 0\njmp loc_14B5\nloc_13E2:\nmov eax, [rbp+var_8]\ncdqe\nshl rax, 6\nlea rax, [rax+10h]\nadd rax, rbp\nadd rax, 3Ch ; '<'\nmov edx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nshl rax, 6\nlea rax, [rax+10h]\nadd rax, rbp\nadd rax, 1044h\nmov eax, [rax]\ncmp edx, eax\njz short loc_141E\nmov eax, 0\njmp locret_14C9\nloc_141E:\nmov [rbp+var_4], 0\njmp short loc_1492\nloc_1427:\nlea rcx, [rbp+arg_1008]\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nadd rax, rax\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nshl rdx, 6\nadd rax, rdx\nadd rcx, rax\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nadd rax, rax\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nshl rdx, 6\nadd rax, rdx\nlea rax, [rax+10h]\nadd rax, rbp\nmov rsi, rcx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_148E\nmov eax, 0\njmp short locret_14C9\nloc_148E:\nadd [rbp+var_4], 1\nloc_1492:\nmov eax, [rbp+var_8]\ncdqe\nshl rax, 6\nlea rax, [rax+10h]\nadd rax, rbp\nadd rax, 3Ch ; '<'\nmov eax, [rax]\ncmp [rbp+var_4], eax\njl loc_1427\nadd [rbp+var_8], 1\nloc_14B5:\nmov eax, [rbp+arg_1000]\ncmp [rbp+var_8], eax\njl loc_13E2\nmov eax, 1\nlocret_14C9:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_13B0(\n __int64 a1,\n __int64 a2,\n __int64 a3,\n __int64 a4,\n __int64 a5,\n __int64 a6,\n __int64 a7,\n __int64 a8,\n __int64 a9,\n __int64 a10,\n __int64 a11,\n __int64 a12)\n{\n int i; // [rsp+8h] [rbp-8h]\n int j; // [rsp+Ch] [rbp-4h]\n __int64 savedregs; // [rsp+10h] [rbp+0h] BYREF\n\n if ( LODWORD(STACK[0x1020]) != LODWORD(STACK[0x2028]) )\n return 0LL;\n for ( i = 0; i < SLODWORD(STACK[0x1020]); ++i )\n {\n if ( *((_DWORD *)&a12 + 16 * (__int64)i + 5) != *((_DWORD *)&STACK[0x1054] + 16 * (__int64)i + 4) )\n return 0LL;\n for ( j = 0; j < *((_DWORD *)&a12 + 16 * (__int64)i + 5); ++j )\n {\n if ( strcmp(\n (const char *)&savedregs + 64 * (__int64)i + 10 * j + 16,\n (const char *)&STACK[0x1028] + 64 * (__int64)i + 10 * j) )\n {\n return 0LL;\n }\n }\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_13B0(long long a1, long long a2, long long a3, long long a4,\n long long a5, long long a6, long long a7, long long a8,\n long long a9, long long a10, long long a11, long long a12) {\n int i;\n int j;\n long long savedregs;\n if (LODWORD(STACK[4128]) != LODWORD(STACK[8232])) return 0LL;\n for (i = 0; i < SLODWORD(STACK[4128]); ++i) {\n if (*((uint32_t *)&a12 + 16 * (long long)i + 5) !=\n *((uint32_t *)&STACK[4180] + 16 * (long long)i + 4))\n return 0LL;\n for (j = 0; j < *((uint32_t *)&a12 + 16 * (long long)i + 5); ++j) {\n if (strcmp((const char *)&savedregs + 64 * (long long)i + 10 * j + 16,\n (const char *)&STACK[4136] + 64 * (long long)i + 10 * j)) {\n return 0LL;\n }\n }\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, long long a3, long long a4,\n long long a5, long long a6, long long a7, long long a8,\n long long a9, long long a10, long long a11, long long a12) {\n int i;\n int j;\n long long savedregs;\n if (LODWORD(STACK[4128]) != LODWORD(STACK[8232])) return 0LL;\n for (i = 0; i < SLODWORD(STACK[4128]); ++i) {\n if (*((uint32_t *)&a12 + 16 * (long long)i + 5) !=\n *((uint32_t *)&STACK[4180] + 16 * (long long)i + 4))\n return 0LL;\n for (j = 0; j < *((uint32_t *)&a12 + 16 * (long long)i + 5); ++j) {\n if (strcmp((const char *)&savedregs + 64 * (long long)i + 10 * j + 16,\n (const char *)&STACK[4136] + 64 * (long long)i + 10 * j)) {\n return 0LL;\n }\n }\n }\n return 1LL;\n}" + }, + { + "index": 462, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n#define MAX_COMBINATIONS 64\n\n#define MAX_ELEMENTS 6\n\n#define MAX_STRING_LENGTH 10\n\n\n\ntypedef struct {\n\n char elements[MAX_ELEMENTS][MAX_STRING_LENGTH];\n\n int size;\n\n} Combination;\n\n\n\ntypedef struct {\n\n Combination combinations[MAX_COMBINATIONS];\n\n int count;\n\n} CombinationList;\n\n\n\n// Function to generate combinations\n\nCombinationList combinations_list(char *list1[], int n) {\n\n CombinationList cl;\n\n cl.count = 0;\n\n int total = 1 << n; // 2^n combinations\n\n\n\n for(int i = 0; i < total; i++) {\n\n Combination comb;\n\n comb.size = 0;\n\n for(int j = 0; j < n; j++) {\n\n if(i & (1 << j)) {\n\n strcpy(comb.elements[comb.size++], list1[j]);\n\n }\n\n }\n\n cl.combinations[cl.count++] = comb;\n\n }\n\n return cl;\n\n}\n\n\n\n// Function to compare two CombinationLists\n\n", + "func": "int func0(CombinationList a, CombinationList b) {\n if (a.count != b.count) return 0;\n for (int i = 0; i < a.count; i++) {\n if (a.combinations[i].size != b.combinations[i].size) return 0;\n for (int j = 0; j < a.combinations[i].size; j++) {\n if (strcmp(a.combinations[i].elements[j],\n b.combinations[i].elements[j]) != 0)\n return 0;\n }\n }\n return 1;\n}", + "test": "int main() {\n\n // First assert\n\n char *list1[] = {\"orange\", \"red\", \"green\", \"blue\"};\n\n CombinationList result1 = combinations_list(list1, 4);\n\n CombinationList expected1;\n\n expected1.count = 16;\n\n // []\n\n expected1.combinations[0].size = 0;\n\n // ['orange']\n\n strcpy(expected1.combinations[1].elements[0], \"orange\");\n\n expected1.combinations[1].size = 1;\n\n // ['red']\n\n strcpy(expected1.combinations[2].elements[0], \"red\");\n\n expected1.combinations[2].size = 1;\n\n // ['red', 'orange']\n\n strcpy(expected1.combinations[3].elements[0], \"orange\");\n\n strcpy(expected1.combinations[3].elements[1], \"red\");\n\n expected1.combinations[3].size = 2;\n\n // ['green']\n\n strcpy(expected1.combinations[4].elements[0], \"green\");\n\n expected1.combinations[4].size = 1;\n\n // ['green', 'orange']\n\n strcpy(expected1.combinations[5].elements[0], \"orange\");\n\n strcpy(expected1.combinations[5].elements[1], \"green\");\n\n expected1.combinations[5].size = 2;\n\n // ['green', 'red']\n\n strcpy(expected1.combinations[6].elements[0], \"red\");\n\n strcpy(expected1.combinations[6].elements[1], \"green\");\n\n expected1.combinations[6].size = 2;\n\n // ['green', 'red', 'orange']\n\n strcpy(expected1.combinations[7].elements[0], \"orange\");\n\n strcpy(expected1.combinations[7].elements[1], \"red\");\n\n strcpy(expected1.combinations[7].elements[2], \"green\");\n\n expected1.combinations[7].size = 3;\n\n // ['blue']\n\n strcpy(expected1.combinations[8].elements[0], \"blue\");\n\n expected1.combinations[8].size = 1;\n\n // ['blue', 'orange']\n\n strcpy(expected1.combinations[9].elements[0], \"orange\");\n\n strcpy(expected1.combinations[9].elements[1], \"blue\");\n\n expected1.combinations[9].size = 2;\n\n // ['blue', 'red']\n\n strcpy(expected1.combinations[10].elements[0], \"red\");\n\n strcpy(expected1.combinations[10].elements[1], \"blue\");\n\n expected1.combinations[10].size = 2;\n\n // ['blue', 'red', 'orange']\n\n strcpy(expected1.combinations[11].elements[0], \"orange\");\n\n strcpy(expected1.combinations[11].elements[1], \"red\");\n\n strcpy(expected1.combinations[11].elements[2], \"blue\");\n\n expected1.combinations[11].size = 3;\n\n // ['blue', 'green']\n\n strcpy(expected1.combinations[12].elements[0], \"green\");\n\n strcpy(expected1.combinations[12].elements[1], \"blue\");\n\n expected1.combinations[12].size = 2;\n\n // ['blue', 'green', 'orange']\n\n strcpy(expected1.combinations[13].elements[0], \"orange\");\n\n strcpy(expected1.combinations[13].elements[1], \"green\");\n\n strcpy(expected1.combinations[13].elements[2], \"blue\");\n\n expected1.combinations[13].size = 3;\n\n // ['blue', 'green', 'red']\n\n strcpy(expected1.combinations[14].elements[0], \"red\");\n\n strcpy(expected1.combinations[14].elements[1], \"green\");\n\n strcpy(expected1.combinations[14].elements[2], \"blue\");\n\n expected1.combinations[14].size = 3;\n\n // ['blue', 'green', 'red', 'orange']\n\n strcpy(expected1.combinations[15].elements[0], \"orange\");\n\n strcpy(expected1.combinations[15].elements[1], \"red\");\n\n strcpy(expected1.combinations[15].elements[2], \"green\");\n\n strcpy(expected1.combinations[15].elements[3], \"blue\");\n\n expected1.combinations[15].size = 4;\n\n\n\n assert(func0(result1, expected1));\n\n\n\n // Second assert\n\n char *list2[] = {\"red\", \"green\", \"blue\", \"white\", \"black\", \"orange\"};\n\n CombinationList result2 = combinations_list(list2, 6);\n\n CombinationList expected2;\n\n expected2.count = 64;\n\n // Due to length, this part is omitted. In practice, you would fill expected2 with all 64 combinations.\n\n // For brevity, we'll assume it's correctly filled.\n\n // You need to manually fill each combination as per the Python assert.\n\n // ...\n\n\n\n // Third assert\n\n char *list3[] = {\"red\", \"green\", \"black\", \"orange\"};\n\n CombinationList result3 = combinations_list(list3, 4);\n\n CombinationList expected3;\n\n expected3.count = 16;\n\n // []\n\n expected3.combinations[0].size = 0;\n\n // ['red']\n\n strcpy(expected3.combinations[1].elements[0], \"red\");\n\n expected3.combinations[1].size = 1;\n\n // ['green']\n\n strcpy(expected3.combinations[2].elements[0], \"green\");\n\n expected3.combinations[2].size = 1;\n\n // ['green', 'red']\n\n strcpy(expected3.combinations[3].elements[0], \"red\");\n\n strcpy(expected3.combinations[3].elements[1], \"green\");\n\n expected3.combinations[3].size = 2;\n\n // ['black']\n\n strcpy(expected3.combinations[4].elements[0], \"black\");\n\n expected3.combinations[4].size = 1;\n\n // ['black', 'red']\n\n strcpy(expected3.combinations[5].elements[0], \"red\");\n\n strcpy(expected3.combinations[5].elements[1], \"black\");\n\n expected3.combinations[5].size = 2;\n\n // ['black', 'green']\n\n strcpy(expected3.combinations[6].elements[0], \"green\");\n\n strcpy(expected3.combinations[6].elements[1], \"black\");\n\n expected3.combinations[6].size = 2;\n\n // ['black', 'green', 'red']\n\n strcpy(expected3.combinations[7].elements[0], \"red\");\n\n strcpy(expected3.combinations[7].elements[1], \"green\");\n\n strcpy(expected3.combinations[7].elements[2], \"black\");\n\n expected3.combinations[7].size = 3;\n\n // ['orange']\n\n strcpy(expected3.combinations[8].elements[0], \"orange\");\n\n expected3.combinations[8].size = 1;\n\n // ['orange', 'red']\n\n strcpy(expected3.combinations[9].elements[0], \"red\");\n\n strcpy(expected3.combinations[9].elements[1], \"orange\");\n\n expected3.combinations[9].size = 2;\n\n // ['orange', 'green']\n\n strcpy(expected3.combinations[10].elements[0], \"green\");\n\n strcpy(expected3.combinations[10].elements[1], \"orange\");\n\n expected3.combinations[10].size = 2;\n\n // ['orange', 'green', 'red']\n\n strcpy(expected3.combinations[11].elements[0], \"red\");\n\n strcpy(expected3.combinations[11].elements[1], \"green\");\n\n strcpy(expected3.combinations[11].elements[2], \"orange\");\n\n expected3.combinations[11].size = 3;\n\n // ['orange', 'black']\n\n strcpy(expected3.combinations[12].elements[0], \"black\");\n\n strcpy(expected3.combinations[12].elements[1], \"orange\");\n\n expected3.combinations[12].size = 2;\n\n // ['orange', 'black', 'red']\n\n strcpy(expected3.combinations[13].elements[0], \"red\");\n\n strcpy(expected3.combinations[13].elements[1], \"black\");\n\n strcpy(expected3.combinations[13].elements[2], \"orange\");\n\n expected3.combinations[13].size = 3;\n\n // ['orange', 'black', 'green']\n\n strcpy(expected3.combinations[14].elements[0], \"green\");\n\n strcpy(expected3.combinations[14].elements[1], \"black\");\n\n strcpy(expected3.combinations[14].elements[2], \"orange\");\n\n expected3.combinations[14].size = 3;\n\n // ['orange', 'black', 'green', 'red']\n\n strcpy(expected3.combinations[15].elements[0], \"red\");\n\n strcpy(expected3.combinations[15].elements[1], \"green\");\n\n strcpy(expected3.combinations[15].elements[2], \"black\");\n\n strcpy(expected3.combinations[15].elements[3], \"orange\");\n\n expected3.combinations[15].size = 4;\n\n\n\n assert(func0(result3, expected3));\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov 0x1050(%rsp),%eax\nmov $0x0,%edx\ncmp 0x2058(%rsp),%eax\njne 13ff \ntest %eax,%eax\njle 13ec \nlea -0x1(%rax),%eax\nadd $0x1,%rax\nshl $0x6,%rax\nmov %rax,0x8(%rsp)\nmov $0x0,%r13d\nlea 0x8c(%rsp),%r15\nlea 0x1094(%rsp),%r14\nlea 0x1058(%rsp),%rax\nmov %rax,(%rsp)\nmov (%r15,%r13,1),%eax\ncmp (%r14,%r13,1),%eax\njne 13f3 \ntest %eax,%eax\njle 13da \nlea 0x50(%rsp),%rcx\nlea (%rcx,%r13,1),%rbx\nmov (%rsp),%rcx\nlea (%rcx,%r13,1),%rbp\nlea -0x1(%rax),%eax\nlea (%rax,%rax,4),%rax\nlea 0xa(%rbx,%rax,2),%r12\nmov %rbp,%rsi\nmov %rbx,%rdi\ncallq 10b0 \ntest %eax,%eax\njne 13fa \nadd $0xa,%rbx\nadd $0xa,%rbp\ncmp %r12,%rbx\njne 13be \nadd $0x40,%r13\ncmp 0x8(%rsp),%r13\njne 1393 \nmov $0x1,%edx\njmp 13ff \nmov $0x1,%edx\njmp 13ff \nmov $0x0,%edx\njmp 13ff \nmov $0x0,%edx\nmov %edx,%eax\nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov eax, [rsp+48h+arg_1000]\nmov edx, 0\ncmp eax, [rsp+48h+arg_2008]\njnz loc_13F5\ntest eax, eax\njle short loc_13E2\ncdqe\nshl rax, 6\nmov [rsp+48h+var_40], rax\nmov r13d, 0\nlea r15, [rsp+48h+arg_3C]\nlea r14, [rsp+48h+arg_1044]\nlea rbp, [rsp+48h+arg_1008]\nloc_1392:\nmov eax, [r15+r13]\ncmp eax, [r14+r13]\njnz short loc_13E9\ntest eax, eax\njle short loc_13CD\ncdqe\nlea rax, [rax+rax*4]\nlea r12, [r13+rax*2+0]\nmov rbx, r13\nloc_13AE:\nlea rsi, [rbp+rbx+0]; s2\nlea rax, [rbx+50h]\nlea rdi, [rsp+rax+48h+s1]; s1\ncall _strcmp\ntest eax, eax\njnz short loc_13F0\nadd rbx, 0Ah\ncmp rbx, r12\njnz short loc_13AE\nloc_13CD:\nadd r13, 40h ; '@'\nmov rax, [rsp+48h+var_40]\ncmp r13, rax\njnz short loc_1392\nmov edx, 1\njmp short loc_13F5\nloc_13E2:\nmov edx, 1\njmp short loc_13F5\nloc_13E9:\nmov edx, 0\njmp short loc_13F5\nloc_13F0:\nmov edx, 0\nloc_13F5:\nmov eax, edx\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "__int64 __fastcall func0(\n __int64 a1,\n __int64 a2,\n __int64 a3,\n __int64 a4,\n __int64 a5,\n __int64 a6,\n __int64 a7,\n __int64 a8,\n __int64 a9,\n __int64 a10,\n __int64 a11,\n __int64 a12,\n __int64 a13,\n __int64 a14)\n{\n int v14; // eax\n unsigned int v15; // edx\n __int64 v16; // r13\n int v17; // eax\n __int64 v18; // r12\n __int64 v19; // rbx\n char s1[8]; // [rsp+0h] [rbp-48h] BYREF\n __int64 v22; // [rsp+8h] [rbp-40h]\n\n v14 = STACK[0x1050];\n v15 = 0;\n if ( LODWORD(STACK[0x1050]) == LODWORD(STACK[0x2058]) )\n {\n if ( v14 <= 0 )\n {\n return 1;\n }\n else\n {\n v22 = (__int64)v14 << 6;\n v16 = 0LL;\n while ( 1 )\n {\n v17 = *(_DWORD *)((char *)&a14 + v16 + 4);\n if ( v17 != *(_DWORD *)((char *)&STACK[0x1094] + v16) )\n return 0;\n if ( v17 > 0 )\n break;\nLABEL_9:\n v16 += 64LL;\n if ( v16 == v22 )\n return 1;\n }\n v18 = v16 + 10LL * v17;\n v19 = v16;\n while ( !strcmp(&s1[v19 + 80], (const char *)&STACK[0x1058] + v19) )\n {\n v19 += 10LL;\n if ( v19 == v18 )\n goto LABEL_9;\n }\n return 0;\n }\n }\n return v15;\n}", + "ida_strip_asm": "sub_133A:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov eax, [rsp+48h+arg_1000]\nmov edx, 0\ncmp eax, [rsp+48h+arg_2008]\njnz loc_13F5\ntest eax, eax\njle short loc_13E2\ncdqe\nshl rax, 6\nmov [rsp+48h+var_40], rax\nmov r13d, 0\nlea r15, [rsp+48h+arg_3C]\nlea r14, [rsp+48h+arg_1044]\nlea rbp, [rsp+48h+arg_1008]\nloc_1392:\nmov eax, [r15+r13]\ncmp eax, [r14+r13]\njnz short loc_13E9\ntest eax, eax\njle short loc_13CD\ncdqe\nlea rax, [rax+rax*4]\nlea r12, [r13+rax*2+0]\nmov rbx, r13\nloc_13AE:\nlea rsi, [rbp+rbx+0]; s2\nlea rax, [rbx+50h]\nlea rdi, [rsp+rax+48h+s1]; s1\ncall _strcmp\ntest eax, eax\njnz short loc_13F0\nadd rbx, 0Ah\ncmp rbx, r12\njnz short loc_13AE\nloc_13CD:\nadd r13, 40h ; '@'\nmov rax, [rsp+48h+var_40]\ncmp r13, rax\njnz short loc_1392\nmov edx, 1\njmp short loc_13F5\nloc_13E2:\nmov edx, 1\njmp short loc_13F5\nloc_13E9:\nmov edx, 0\njmp short loc_13F5\nloc_13F0:\nmov edx, 0\nloc_13F5:\nmov eax, edx\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_133A(\n __int64 a1,\n __int64 a2,\n __int64 a3,\n __int64 a4,\n __int64 a5,\n __int64 a6,\n __int64 a7,\n __int64 a8,\n __int64 a9,\n __int64 a10,\n __int64 a11,\n __int64 a12,\n __int64 a13,\n __int64 a14)\n{\n int v14; // eax\n unsigned int v15; // edx\n __int64 v16; // r13\n int v17; // eax\n __int64 v18; // r12\n __int64 v19; // rbx\n char s1[8]; // [rsp+0h] [rbp-48h] BYREF\n __int64 v22; // [rsp+8h] [rbp-40h]\n\n v14 = STACK[0x1050];\n v15 = 0;\n if ( LODWORD(STACK[0x1050]) == LODWORD(STACK[0x2058]) )\n {\n if ( v14 <= 0 )\n {\n return 1;\n }\n else\n {\n v22 = (__int64)v14 << 6;\n v16 = 0LL;\n while ( 1 )\n {\n v17 = *(_DWORD *)((char *)&a14 + v16 + 4);\n if ( v17 != *(_DWORD *)((char *)&STACK[0x1094] + v16) )\n return 0;\n if ( v17 > 0 )\n break;\nLABEL_9:\n v16 += 64LL;\n if ( v16 == v22 )\n return 1;\n }\n v18 = v16 + 10LL * v17;\n v19 = v16;\n while ( !strcmp(&s1[v19 + 80], (const char *)&STACK[0x1058] + v19) )\n {\n v19 += 10LL;\n if ( v19 == v18 )\n goto LABEL_9;\n }\n return 0;\n }\n }\n return v15;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_133A(long long a1, long long a2, long long a3, long long a4,\n long long a5, long long a6, long long a7, long long a8,\n long long a9, long long a10, long long a11, long long a12,\n long long a13, long long a14) {\n int v14;\n unsigned int v15;\n long long v16;\n int v17;\n long long v18;\n long long v19;\n char s1[8];\n long long v22;\n v14 = STACK[4176];\n v15 = 0;\n if (LODWORD(STACK[4176]) == LODWORD(STACK[8280])) {\n if (v14 <= 0) {\n return 1;\n } else {\n v22 = (long long)v14 << 6;\n v16 = 0LL;\n while (1) {\n v17 = *(uint32_t *)((char *)&a14 + v16 + 4);\n if (v17 != *(uint32_t *)((char *)&STACK[4244] + v16)) return 0;\n if (v17 > 0) break;\n LABEL_9:\n v16 += 64LL;\n if (v16 == v22) return 1;\n }\n v18 = v16 + 10LL * v17;\n v19 = v16;\n while (!strcmp(&s1[v19 + 80], (const char *)&STACK[4184] + v19)) {\n v19 += 10LL;\n if (v19 == v18) goto LABEL_9;\n }\n return 0;\n }\n }\n return v15;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, long long a3, long long a4,\n long long a5, long long a6, long long a7, long long a8,\n long long a9, long long a10, long long a11, long long a12,\n long long a13, long long a14) {\n int v14;\n unsigned int v15;\n long long v16;\n int v17;\n long long v18;\n long long v19;\n char s1[8];\n long long v22;\n v14 = STACK[4176];\n v15 = 0;\n if (LODWORD(STACK[4176]) == LODWORD(STACK[8280])) {\n if (v14 <= 0) {\n return 1;\n } else {\n v22 = (long long)v14 << 6;\n v16 = 0LL;\n while (1) {\n v17 = *(uint32_t *)((char *)&a14 + v16 + 4);\n if (v17 != *(uint32_t *)((char *)&STACK[4244] + v16)) return 0;\n if (v17 > 0) break;\n LABEL_9:\n v16 += 64LL;\n if (v16 == v22) return 1;\n }\n v18 = v16 + 10LL * v17;\n v19 = v16;\n while (!strcmp(&s1[v19 + 80], (const char *)&STACK[4184] + v19)) {\n v19 += 10LL;\n if (v19 == v18) goto LABEL_9;\n }\n return 0;\n }\n }\n return v15;\n}" + }, + { + "index": 462, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n#define MAX_COMBINATIONS 64\n\n#define MAX_ELEMENTS 6\n\n#define MAX_STRING_LENGTH 10\n\n\n\ntypedef struct {\n\n char elements[MAX_ELEMENTS][MAX_STRING_LENGTH];\n\n int size;\n\n} Combination;\n\n\n\ntypedef struct {\n\n Combination combinations[MAX_COMBINATIONS];\n\n int count;\n\n} CombinationList;\n\n\n\n// Function to generate combinations\n\nCombinationList combinations_list(char *list1[], int n) {\n\n CombinationList cl;\n\n cl.count = 0;\n\n int total = 1 << n; // 2^n combinations\n\n\n\n for(int i = 0; i < total; i++) {\n\n Combination comb;\n\n comb.size = 0;\n\n for(int j = 0; j < n; j++) {\n\n if(i & (1 << j)) {\n\n strcpy(comb.elements[comb.size++], list1[j]);\n\n }\n\n }\n\n cl.combinations[cl.count++] = comb;\n\n }\n\n return cl;\n\n}\n\n\n\n// Function to compare two CombinationLists\n\n", + "func": "int func0(CombinationList a, CombinationList b) {\n if (a.count != b.count) return 0;\n for (int i = 0; i < a.count; i++) {\n if (a.combinations[i].size != b.combinations[i].size) return 0;\n for (int j = 0; j < a.combinations[i].size; j++) {\n if (strcmp(a.combinations[i].elements[j],\n b.combinations[i].elements[j]) != 0)\n return 0;\n }\n }\n return 1;\n}", + "test": "int main() {\n\n // First assert\n\n char *list1[] = {\"orange\", \"red\", \"green\", \"blue\"};\n\n CombinationList result1 = combinations_list(list1, 4);\n\n CombinationList expected1;\n\n expected1.count = 16;\n\n // []\n\n expected1.combinations[0].size = 0;\n\n // ['orange']\n\n strcpy(expected1.combinations[1].elements[0], \"orange\");\n\n expected1.combinations[1].size = 1;\n\n // ['red']\n\n strcpy(expected1.combinations[2].elements[0], \"red\");\n\n expected1.combinations[2].size = 1;\n\n // ['red', 'orange']\n\n strcpy(expected1.combinations[3].elements[0], \"orange\");\n\n strcpy(expected1.combinations[3].elements[1], \"red\");\n\n expected1.combinations[3].size = 2;\n\n // ['green']\n\n strcpy(expected1.combinations[4].elements[0], \"green\");\n\n expected1.combinations[4].size = 1;\n\n // ['green', 'orange']\n\n strcpy(expected1.combinations[5].elements[0], \"orange\");\n\n strcpy(expected1.combinations[5].elements[1], \"green\");\n\n expected1.combinations[5].size = 2;\n\n // ['green', 'red']\n\n strcpy(expected1.combinations[6].elements[0], \"red\");\n\n strcpy(expected1.combinations[6].elements[1], \"green\");\n\n expected1.combinations[6].size = 2;\n\n // ['green', 'red', 'orange']\n\n strcpy(expected1.combinations[7].elements[0], \"orange\");\n\n strcpy(expected1.combinations[7].elements[1], \"red\");\n\n strcpy(expected1.combinations[7].elements[2], \"green\");\n\n expected1.combinations[7].size = 3;\n\n // ['blue']\n\n strcpy(expected1.combinations[8].elements[0], \"blue\");\n\n expected1.combinations[8].size = 1;\n\n // ['blue', 'orange']\n\n strcpy(expected1.combinations[9].elements[0], \"orange\");\n\n strcpy(expected1.combinations[9].elements[1], \"blue\");\n\n expected1.combinations[9].size = 2;\n\n // ['blue', 'red']\n\n strcpy(expected1.combinations[10].elements[0], \"red\");\n\n strcpy(expected1.combinations[10].elements[1], \"blue\");\n\n expected1.combinations[10].size = 2;\n\n // ['blue', 'red', 'orange']\n\n strcpy(expected1.combinations[11].elements[0], \"orange\");\n\n strcpy(expected1.combinations[11].elements[1], \"red\");\n\n strcpy(expected1.combinations[11].elements[2], \"blue\");\n\n expected1.combinations[11].size = 3;\n\n // ['blue', 'green']\n\n strcpy(expected1.combinations[12].elements[0], \"green\");\n\n strcpy(expected1.combinations[12].elements[1], \"blue\");\n\n expected1.combinations[12].size = 2;\n\n // ['blue', 'green', 'orange']\n\n strcpy(expected1.combinations[13].elements[0], \"orange\");\n\n strcpy(expected1.combinations[13].elements[1], \"green\");\n\n strcpy(expected1.combinations[13].elements[2], \"blue\");\n\n expected1.combinations[13].size = 3;\n\n // ['blue', 'green', 'red']\n\n strcpy(expected1.combinations[14].elements[0], \"red\");\n\n strcpy(expected1.combinations[14].elements[1], \"green\");\n\n strcpy(expected1.combinations[14].elements[2], \"blue\");\n\n expected1.combinations[14].size = 3;\n\n // ['blue', 'green', 'red', 'orange']\n\n strcpy(expected1.combinations[15].elements[0], \"orange\");\n\n strcpy(expected1.combinations[15].elements[1], \"red\");\n\n strcpy(expected1.combinations[15].elements[2], \"green\");\n\n strcpy(expected1.combinations[15].elements[3], \"blue\");\n\n expected1.combinations[15].size = 4;\n\n\n\n assert(func0(result1, expected1));\n\n\n\n // Second assert\n\n char *list2[] = {\"red\", \"green\", \"blue\", \"white\", \"black\", \"orange\"};\n\n CombinationList result2 = combinations_list(list2, 6);\n\n CombinationList expected2;\n\n expected2.count = 64;\n\n // Due to length, this part is omitted. In practice, you would fill expected2 with all 64 combinations.\n\n // For brevity, we'll assume it's correctly filled.\n\n // You need to manually fill each combination as per the Python assert.\n\n // ...\n\n\n\n // Third assert\n\n char *list3[] = {\"red\", \"green\", \"black\", \"orange\"};\n\n CombinationList result3 = combinations_list(list3, 4);\n\n CombinationList expected3;\n\n expected3.count = 16;\n\n // []\n\n expected3.combinations[0].size = 0;\n\n // ['red']\n\n strcpy(expected3.combinations[1].elements[0], \"red\");\n\n expected3.combinations[1].size = 1;\n\n // ['green']\n\n strcpy(expected3.combinations[2].elements[0], \"green\");\n\n expected3.combinations[2].size = 1;\n\n // ['green', 'red']\n\n strcpy(expected3.combinations[3].elements[0], \"red\");\n\n strcpy(expected3.combinations[3].elements[1], \"green\");\n\n expected3.combinations[3].size = 2;\n\n // ['black']\n\n strcpy(expected3.combinations[4].elements[0], \"black\");\n\n expected3.combinations[4].size = 1;\n\n // ['black', 'red']\n\n strcpy(expected3.combinations[5].elements[0], \"red\");\n\n strcpy(expected3.combinations[5].elements[1], \"black\");\n\n expected3.combinations[5].size = 2;\n\n // ['black', 'green']\n\n strcpy(expected3.combinations[6].elements[0], \"green\");\n\n strcpy(expected3.combinations[6].elements[1], \"black\");\n\n expected3.combinations[6].size = 2;\n\n // ['black', 'green', 'red']\n\n strcpy(expected3.combinations[7].elements[0], \"red\");\n\n strcpy(expected3.combinations[7].elements[1], \"green\");\n\n strcpy(expected3.combinations[7].elements[2], \"black\");\n\n expected3.combinations[7].size = 3;\n\n // ['orange']\n\n strcpy(expected3.combinations[8].elements[0], \"orange\");\n\n expected3.combinations[8].size = 1;\n\n // ['orange', 'red']\n\n strcpy(expected3.combinations[9].elements[0], \"red\");\n\n strcpy(expected3.combinations[9].elements[1], \"orange\");\n\n expected3.combinations[9].size = 2;\n\n // ['orange', 'green']\n\n strcpy(expected3.combinations[10].elements[0], \"green\");\n\n strcpy(expected3.combinations[10].elements[1], \"orange\");\n\n expected3.combinations[10].size = 2;\n\n // ['orange', 'green', 'red']\n\n strcpy(expected3.combinations[11].elements[0], \"red\");\n\n strcpy(expected3.combinations[11].elements[1], \"green\");\n\n strcpy(expected3.combinations[11].elements[2], \"orange\");\n\n expected3.combinations[11].size = 3;\n\n // ['orange', 'black']\n\n strcpy(expected3.combinations[12].elements[0], \"black\");\n\n strcpy(expected3.combinations[12].elements[1], \"orange\");\n\n expected3.combinations[12].size = 2;\n\n // ['orange', 'black', 'red']\n\n strcpy(expected3.combinations[13].elements[0], \"red\");\n\n strcpy(expected3.combinations[13].elements[1], \"black\");\n\n strcpy(expected3.combinations[13].elements[2], \"orange\");\n\n expected3.combinations[13].size = 3;\n\n // ['orange', 'black', 'green']\n\n strcpy(expected3.combinations[14].elements[0], \"green\");\n\n strcpy(expected3.combinations[14].elements[1], \"black\");\n\n strcpy(expected3.combinations[14].elements[2], \"orange\");\n\n expected3.combinations[14].size = 3;\n\n // ['orange', 'black', 'green', 'red']\n\n strcpy(expected3.combinations[15].elements[0], \"red\");\n\n strcpy(expected3.combinations[15].elements[1], \"green\");\n\n strcpy(expected3.combinations[15].elements[2], \"black\");\n\n strcpy(expected3.combinations[15].elements[3], \"orange\");\n\n expected3.combinations[15].size = 4;\n\n\n\n assert(func0(result3, expected3));\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nxor %r8d,%r8d\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov 0x1050(%rsp),%eax\ncmp 0x2058(%rsp),%eax\njne 1d52 \ntest %eax,%eax\njle 1d73 \nlea -0x1(%rax),%r13d\nxor %r12d,%r12d\nlea 0x8c(%rsp),%r15\nadd $0x1,%r13\nlea 0x1094(%rsp),%r14\nlea 0x1058(%rsp),%rbx\nshl $0x6,%r13\nmov %r13,0x8(%rsp)\nmov (%r15,%r12,1),%eax\ncmp (%r14,%r12,1),%eax\njne 1d4f \ntest %eax,%eax\njle 1d68 \nsub $0x1,%eax\nmov %r12,%r13\nlea (%rax,%rax,4),%rax\nlea 0xa(%r12,%rax,2),%rbp\njmp 1d39 \nnopl 0x0(%rax,%rax,1)\nadd $0xa,%r13\ncmp %r13,%rbp\nje 1d68 \nlea 0x50(%rsp),%rax\nlea (%rbx,%r13,1),%rsi\nlea (%rax,%r13,1),%rdi\ncallq 10b0 \ntest %eax,%eax\nje 1d30 \nxor %r8d,%r8d\nadd $0x18,%rsp\nmov %r8d,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\nadd $0x40,%r12\ncmp 0x8(%rsp),%r12\njne 1d09 \nmov $0x1,%r8d\njmp 1d52 \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\nxor eax, eax\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmovsxd r13, [rsp+48h+arg_1000]\ncmp r13d, [rsp+48h+arg_2008]\njnz short loc_1CA0\ntest r13d, r13d\njle loc_1CBE\nshl r13, 6\nxor r12d, r12d\nlea r15, [rsp+48h+arg_3C]\nmov [rsp+48h+var_40], r13\nlea r14, [rsp+48h+arg_1044]\nlea rbx, [rsp+48h+arg_1008]\nloc_1C63:\nmovsxd rax, dword ptr [r15+r12]\ncmp eax, [r14+r12]\njnz short loc_1C9E\ntest eax, eax\njle short loc_1CB0\nlea rax, [rax+rax*4]\nmov r13, r12\nlea rbp, [r12+rax*2]\njmp short loc_1C89\nloc_1C80:\nadd r13, 0Ah\ncmp r13, rbp\njz short loc_1CB0\nloc_1C89:\nlea rax, [r13+50h]\nlea rsi, [rbx+r13]; s2\nlea rdi, [rsp+rax+48h+s1]; s1\ncall _strcmp\ntest eax, eax\njz short loc_1C80\nloc_1C9E:\nxor eax, eax\nloc_1CA0:\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1CB0:\nmov rax, [rsp+48h+var_40]\nadd r12, 40h ; '@'\ncmp r12, rax\njnz short loc_1C63\nloc_1CBE:\nmov eax, 1\njmp short loc_1CA0", + "ida_pseudo": "__int64 __fastcall func0(\n __int64 a1,\n __int64 a2,\n __int64 a3,\n __int64 a4,\n __int64 a5,\n __int64 a6,\n __int64 a7,\n __int64 a8,\n __int64 a9,\n __int64 a10,\n __int64 a11,\n __int64 a12,\n __int64 a13,\n __int64 a14)\n{\n __int64 result; // rax\n __int64 v15; // r13\n __int64 v16; // r12\n __int64 v17; // rax\n __int64 v18; // r13\n __int64 v19; // rbp\n char s1[8]; // [rsp+0h] [rbp-48h] BYREF\n __int64 v21; // [rsp+8h] [rbp-40h]\n\n result = 0LL;\n v15 = SLODWORD(STACK[0x1050]);\n if ( (_DWORD)v15 == LODWORD(STACK[0x2058]) )\n {\n if ( (int)v15 <= 0 )\n {\n return 1LL;\n }\n else\n {\n v16 = 0LL;\n v21 = v15 << 6;\n while ( 1 )\n {\n v17 = *(int *)((char *)&a14 + v16 + 4);\n if ( (_DWORD)v17 != *(_DWORD *)((char *)&STACK[0x1094] + v16) )\n return 0LL;\n if ( (int)v17 > 0 )\n {\n v18 = v16;\n v19 = v16 + 10 * v17;\n while ( !strcmp(&s1[v18 + 80], (const char *)&STACK[0x1058] + v18) )\n {\n v18 += 10LL;\n if ( v18 == v19 )\n goto LABEL_11;\n }\n return 0LL;\n }\nLABEL_11:\n v16 += 64LL;\n if ( v16 == v21 )\n return 1LL;\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1C10:\nendbr64\npush r15\nxor eax, eax\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmovsxd r13, [rsp+48h+arg_1000]\ncmp r13d, [rsp+48h+arg_2008]\njnz short loc_1CA0\ntest r13d, r13d\njle loc_1CBE\nshl r13, 6\nxor r12d, r12d\nlea r15, [rsp+48h+arg_3C]\nmov [rsp+48h+var_40], r13\nlea r14, [rsp+48h+arg_1044]\nlea rbx, [rsp+48h+arg_1008]\nloc_1C63:\nmovsxd rax, dword ptr [r15+r12]\ncmp eax, [r14+r12]\njnz short loc_1C9E\ntest eax, eax\njle short loc_1CB0\nlea rax, [rax+rax*4]\nmov r13, r12\nlea rbp, [r12+rax*2]\njmp short loc_1C89\nloc_1C80:\nadd r13, 0Ah\ncmp r13, rbp\njz short loc_1CB0\nloc_1C89:\nlea rax, [r13+50h]\nlea rsi, [rbx+r13]; s2\nlea rdi, [rsp+rax+48h+s1]; s1\ncall _strcmp\ntest eax, eax\njz short loc_1C80\nloc_1C9E:\nxor eax, eax\nloc_1CA0:\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1CB0:\nmov rax, [rsp+48h+var_40]\nadd r12, 40h ; '@'\ncmp r12, rax\njnz short loc_1C63\nloc_1CBE:\nmov eax, 1\njmp short loc_1CA0", + "ida_strip_pseudo": "__int64 __fastcall sub_1C10(\n __int64 a1,\n __int64 a2,\n __int64 a3,\n __int64 a4,\n __int64 a5,\n __int64 a6,\n __int64 a7,\n __int64 a8,\n __int64 a9,\n __int64 a10,\n __int64 a11,\n __int64 a12,\n __int64 a13,\n __int64 a14)\n{\n __int64 result; // rax\n __int64 v15; // r13\n __int64 v16; // r12\n __int64 v17; // rax\n __int64 v18; // r13\n __int64 v19; // rbp\n char s1[8]; // [rsp+0h] [rbp-48h] BYREF\n __int64 v21; // [rsp+8h] [rbp-40h]\n\n result = 0LL;\n v15 = SLODWORD(STACK[0x1050]);\n if ( (_DWORD)v15 == LODWORD(STACK[0x2058]) )\n {\n if ( (int)v15 <= 0 )\n {\n return 1LL;\n }\n else\n {\n v16 = 0LL;\n v21 = v15 << 6;\n while ( 1 )\n {\n v17 = *(int *)((char *)&a14 + v16 + 4);\n if ( (_DWORD)v17 != *(_DWORD *)((char *)&STACK[0x1094] + v16) )\n return 0LL;\n if ( (int)v17 > 0 )\n {\n v18 = v16;\n v19 = v16 + 10 * v17;\n while ( !strcmp(&s1[v18 + 80], (const char *)&STACK[0x1058] + v18) )\n {\n v18 += 10LL;\n if ( v18 == v19 )\n goto LABEL_11;\n }\n return 0LL;\n }\nLABEL_11:\n v16 += 64LL;\n if ( v16 == v21 )\n return 1LL;\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1C10(long long a1, long long a2, long long a3, long long a4,\n long long a5, long long a6, long long a7, long long a8,\n long long a9, long long a10, long long a11, long long a12,\n long long a13, long long a14) {\n long long result;\n long long v15;\n long long v16;\n long long v17;\n long long v18;\n long long v19;\n char s1[8];\n long long v21;\n result = 0LL;\n v15 = SLODWORD(STACK[4176]);\n if ((uint32_t)v15 == LODWORD(STACK[8280])) {\n if ((int)v15 <= 0) {\n return 1LL;\n } else {\n v16 = 0LL;\n v21 = v15 << 6;\n while (1) {\n v17 = *(int *)((char *)&a14 + v16 + 4);\n if ((uint32_t)v17 != *(uint32_t *)((char *)&STACK[4244] + v16))\n return 0LL;\n if ((int)v17 > 0) {\n v18 = v16;\n v19 = v16 + 10 * v17;\n while (!strcmp(&s1[v18 + 80], (const char *)&STACK[4184] + v18)) {\n v18 += 10LL;\n if (v18 == v19) goto LABEL_11;\n }\n return 0LL;\n }\n LABEL_11:\n v16 += 64LL;\n if (v16 == v21) return 1LL;\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, long long a3, long long a4,\n long long a5, long long a6, long long a7, long long a8,\n long long a9, long long a10, long long a11, long long a12,\n long long a13, long long a14) {\n long long result;\n long long v15;\n long long v16;\n long long v17;\n long long v18;\n long long v19;\n char s1[8];\n long long v21;\n result = 0LL;\n v15 = SLODWORD(STACK[4176]);\n if ((uint32_t)v15 == LODWORD(STACK[8280])) {\n if ((int)v15 <= 0) {\n return 1LL;\n } else {\n v16 = 0LL;\n v21 = v15 << 6;\n while (1) {\n v17 = *(int *)((char *)&a14 + v16 + 4);\n if ((uint32_t)v17 != *(uint32_t *)((char *)&STACK[4244] + v16))\n return 0LL;\n if ((int)v17 > 0) {\n v18 = v16;\n v19 = v16 + 10 * v17;\n while (!strcmp(&s1[v18 + 80], (const char *)&STACK[4184] + v18)) {\n v18 += 10LL;\n if (v18 == v19) goto LABEL_11;\n }\n return 0LL;\n }\n LABEL_11:\n v16 += 64LL;\n if (v16 == v21) return 1LL;\n }\n }\n }\n return result;\n}" + }, + { + "index": 462, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n#define MAX_COMBINATIONS 64\n\n#define MAX_ELEMENTS 6\n\n#define MAX_STRING_LENGTH 10\n\n\n\ntypedef struct {\n\n char elements[MAX_ELEMENTS][MAX_STRING_LENGTH];\n\n int size;\n\n} Combination;\n\n\n\ntypedef struct {\n\n Combination combinations[MAX_COMBINATIONS];\n\n int count;\n\n} CombinationList;\n\n\n\n// Function to generate combinations\n\nCombinationList combinations_list(char *list1[], int n) {\n\n CombinationList cl;\n\n cl.count = 0;\n\n int total = 1 << n; // 2^n combinations\n\n\n\n for(int i = 0; i < total; i++) {\n\n Combination comb;\n\n comb.size = 0;\n\n for(int j = 0; j < n; j++) {\n\n if(i & (1 << j)) {\n\n strcpy(comb.elements[comb.size++], list1[j]);\n\n }\n\n }\n\n cl.combinations[cl.count++] = comb;\n\n }\n\n return cl;\n\n}\n\n\n\n// Function to compare two CombinationLists\n\n", + "func": "int func0(CombinationList a, CombinationList b) {\n if (a.count != b.count) return 0;\n for (int i = 0; i < a.count; i++) {\n if (a.combinations[i].size != b.combinations[i].size) return 0;\n for (int j = 0; j < a.combinations[i].size; j++) {\n if (strcmp(a.combinations[i].elements[j],\n b.combinations[i].elements[j]) != 0)\n return 0;\n }\n }\n return 1;\n}", + "test": "int main() {\n\n // First assert\n\n char *list1[] = {\"orange\", \"red\", \"green\", \"blue\"};\n\n CombinationList result1 = combinations_list(list1, 4);\n\n CombinationList expected1;\n\n expected1.count = 16;\n\n // []\n\n expected1.combinations[0].size = 0;\n\n // ['orange']\n\n strcpy(expected1.combinations[1].elements[0], \"orange\");\n\n expected1.combinations[1].size = 1;\n\n // ['red']\n\n strcpy(expected1.combinations[2].elements[0], \"red\");\n\n expected1.combinations[2].size = 1;\n\n // ['red', 'orange']\n\n strcpy(expected1.combinations[3].elements[0], \"orange\");\n\n strcpy(expected1.combinations[3].elements[1], \"red\");\n\n expected1.combinations[3].size = 2;\n\n // ['green']\n\n strcpy(expected1.combinations[4].elements[0], \"green\");\n\n expected1.combinations[4].size = 1;\n\n // ['green', 'orange']\n\n strcpy(expected1.combinations[5].elements[0], \"orange\");\n\n strcpy(expected1.combinations[5].elements[1], \"green\");\n\n expected1.combinations[5].size = 2;\n\n // ['green', 'red']\n\n strcpy(expected1.combinations[6].elements[0], \"red\");\n\n strcpy(expected1.combinations[6].elements[1], \"green\");\n\n expected1.combinations[6].size = 2;\n\n // ['green', 'red', 'orange']\n\n strcpy(expected1.combinations[7].elements[0], \"orange\");\n\n strcpy(expected1.combinations[7].elements[1], \"red\");\n\n strcpy(expected1.combinations[7].elements[2], \"green\");\n\n expected1.combinations[7].size = 3;\n\n // ['blue']\n\n strcpy(expected1.combinations[8].elements[0], \"blue\");\n\n expected1.combinations[8].size = 1;\n\n // ['blue', 'orange']\n\n strcpy(expected1.combinations[9].elements[0], \"orange\");\n\n strcpy(expected1.combinations[9].elements[1], \"blue\");\n\n expected1.combinations[9].size = 2;\n\n // ['blue', 'red']\n\n strcpy(expected1.combinations[10].elements[0], \"red\");\n\n strcpy(expected1.combinations[10].elements[1], \"blue\");\n\n expected1.combinations[10].size = 2;\n\n // ['blue', 'red', 'orange']\n\n strcpy(expected1.combinations[11].elements[0], \"orange\");\n\n strcpy(expected1.combinations[11].elements[1], \"red\");\n\n strcpy(expected1.combinations[11].elements[2], \"blue\");\n\n expected1.combinations[11].size = 3;\n\n // ['blue', 'green']\n\n strcpy(expected1.combinations[12].elements[0], \"green\");\n\n strcpy(expected1.combinations[12].elements[1], \"blue\");\n\n expected1.combinations[12].size = 2;\n\n // ['blue', 'green', 'orange']\n\n strcpy(expected1.combinations[13].elements[0], \"orange\");\n\n strcpy(expected1.combinations[13].elements[1], \"green\");\n\n strcpy(expected1.combinations[13].elements[2], \"blue\");\n\n expected1.combinations[13].size = 3;\n\n // ['blue', 'green', 'red']\n\n strcpy(expected1.combinations[14].elements[0], \"red\");\n\n strcpy(expected1.combinations[14].elements[1], \"green\");\n\n strcpy(expected1.combinations[14].elements[2], \"blue\");\n\n expected1.combinations[14].size = 3;\n\n // ['blue', 'green', 'red', 'orange']\n\n strcpy(expected1.combinations[15].elements[0], \"orange\");\n\n strcpy(expected1.combinations[15].elements[1], \"red\");\n\n strcpy(expected1.combinations[15].elements[2], \"green\");\n\n strcpy(expected1.combinations[15].elements[3], \"blue\");\n\n expected1.combinations[15].size = 4;\n\n\n\n assert(func0(result1, expected1));\n\n\n\n // Second assert\n\n char *list2[] = {\"red\", \"green\", \"blue\", \"white\", \"black\", \"orange\"};\n\n CombinationList result2 = combinations_list(list2, 6);\n\n CombinationList expected2;\n\n expected2.count = 64;\n\n // Due to length, this part is omitted. In practice, you would fill expected2 with all 64 combinations.\n\n // For brevity, we'll assume it's correctly filled.\n\n // You need to manually fill each combination as per the Python assert.\n\n // ...\n\n\n\n // Third assert\n\n char *list3[] = {\"red\", \"green\", \"black\", \"orange\"};\n\n CombinationList result3 = combinations_list(list3, 4);\n\n CombinationList expected3;\n\n expected3.count = 16;\n\n // []\n\n expected3.combinations[0].size = 0;\n\n // ['red']\n\n strcpy(expected3.combinations[1].elements[0], \"red\");\n\n expected3.combinations[1].size = 1;\n\n // ['green']\n\n strcpy(expected3.combinations[2].elements[0], \"green\");\n\n expected3.combinations[2].size = 1;\n\n // ['green', 'red']\n\n strcpy(expected3.combinations[3].elements[0], \"red\");\n\n strcpy(expected3.combinations[3].elements[1], \"green\");\n\n expected3.combinations[3].size = 2;\n\n // ['black']\n\n strcpy(expected3.combinations[4].elements[0], \"black\");\n\n expected3.combinations[4].size = 1;\n\n // ['black', 'red']\n\n strcpy(expected3.combinations[5].elements[0], \"red\");\n\n strcpy(expected3.combinations[5].elements[1], \"black\");\n\n expected3.combinations[5].size = 2;\n\n // ['black', 'green']\n\n strcpy(expected3.combinations[6].elements[0], \"green\");\n\n strcpy(expected3.combinations[6].elements[1], \"black\");\n\n expected3.combinations[6].size = 2;\n\n // ['black', 'green', 'red']\n\n strcpy(expected3.combinations[7].elements[0], \"red\");\n\n strcpy(expected3.combinations[7].elements[1], \"green\");\n\n strcpy(expected3.combinations[7].elements[2], \"black\");\n\n expected3.combinations[7].size = 3;\n\n // ['orange']\n\n strcpy(expected3.combinations[8].elements[0], \"orange\");\n\n expected3.combinations[8].size = 1;\n\n // ['orange', 'red']\n\n strcpy(expected3.combinations[9].elements[0], \"red\");\n\n strcpy(expected3.combinations[9].elements[1], \"orange\");\n\n expected3.combinations[9].size = 2;\n\n // ['orange', 'green']\n\n strcpy(expected3.combinations[10].elements[0], \"green\");\n\n strcpy(expected3.combinations[10].elements[1], \"orange\");\n\n expected3.combinations[10].size = 2;\n\n // ['orange', 'green', 'red']\n\n strcpy(expected3.combinations[11].elements[0], \"red\");\n\n strcpy(expected3.combinations[11].elements[1], \"green\");\n\n strcpy(expected3.combinations[11].elements[2], \"orange\");\n\n expected3.combinations[11].size = 3;\n\n // ['orange', 'black']\n\n strcpy(expected3.combinations[12].elements[0], \"black\");\n\n strcpy(expected3.combinations[12].elements[1], \"orange\");\n\n expected3.combinations[12].size = 2;\n\n // ['orange', 'black', 'red']\n\n strcpy(expected3.combinations[13].elements[0], \"red\");\n\n strcpy(expected3.combinations[13].elements[1], \"black\");\n\n strcpy(expected3.combinations[13].elements[2], \"orange\");\n\n expected3.combinations[13].size = 3;\n\n // ['orange', 'black', 'green']\n\n strcpy(expected3.combinations[14].elements[0], \"green\");\n\n strcpy(expected3.combinations[14].elements[1], \"black\");\n\n strcpy(expected3.combinations[14].elements[2], \"orange\");\n\n expected3.combinations[14].size = 3;\n\n // ['orange', 'black', 'green', 'red']\n\n strcpy(expected3.combinations[15].elements[0], \"red\");\n\n strcpy(expected3.combinations[15].elements[1], \"green\");\n\n strcpy(expected3.combinations[15].elements[2], \"black\");\n\n strcpy(expected3.combinations[15].elements[3], \"orange\");\n\n expected3.combinations[15].size = 4;\n\n\n\n assert(func0(result3, expected3));\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nxor %r8d,%r8d\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov 0x1050(%rsp),%eax\ncmp 0x2058(%rsp),%eax\njne 1d62 \ntest %eax,%eax\njle 1d83 \nlea -0x1(%rax),%r13d\nxor %r12d,%r12d\nlea 0x8c(%rsp),%r15\nadd $0x1,%r13\nlea 0x1094(%rsp),%r14\nlea 0x1058(%rsp),%rbx\nshl $0x6,%r13\nmov %r13,0x8(%rsp)\nmov (%r15,%r12,1),%eax\ncmp (%r14,%r12,1),%eax\njne 1d5f \ntest %eax,%eax\njle 1d78 \nsub $0x1,%eax\nmov %r12,%r13\nlea (%rax,%rax,4),%rax\nlea 0xa(%r12,%rax,2),%rbp\njmp 1d49 \nnopl 0x0(%rax,%rax,1)\nadd $0xa,%r13\ncmp %r13,%rbp\nje 1d78 \nlea 0x50(%rsp),%rax\nlea (%rbx,%r13,1),%rsi\nlea (%rax,%r13,1),%rdi\ncallq 10b0 \ntest %eax,%eax\nje 1d40 \nxor %r8d,%r8d\nadd $0x18,%rsp\nmov %r8d,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\nadd $0x40,%r12\ncmp 0x8(%rsp),%r12\njne 1d19 \nmov $0x1,%r8d\njmp 1d62 \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\nxor eax, eax\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmovsxd r13, [rsp+48h+arg_1000]\ncmp r13d, [rsp+48h+arg_2008]\njnz short loc_1CA0\ntest r13d, r13d\njle loc_1CBB\nshl r13, 6\nxor r12d, r12d\nlea r15, [rsp+48h+arg_3C]\nmov [rsp+48h+var_40], r13\nlea r14, [rsp+48h+arg_1044]\nlea rbx, [rsp+48h+arg_1008]\nloc_1C63:\nmovsxd rax, dword ptr [r15+r12]\ncmp eax, [r14+r12]\njnz short loc_1C9E\ntest eax, eax\njle short loc_1CB0\nlea rax, [rax+rax*4]\nmov r13, r12\nlea rbp, [r12+rax*2]\njmp short loc_1C89\nloc_1C80:\nadd r13, 0Ah\ncmp rbp, r13\njz short loc_1CB0\nloc_1C89:\nlea rax, [r13+50h]\nlea rsi, [rbx+r13]; s2\nlea rdi, [rsp+rax+48h+s1]; s1\ncall _strcmp\ntest eax, eax\njz short loc_1C80\nloc_1C9E:\nxor eax, eax\nloc_1CA0:\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1CB0:\nadd r12, 40h ; '@'\ncmp [rsp+48h+var_40], r12\njnz short loc_1C63\nloc_1CBB:\nmov eax, 1\njmp short loc_1CA0", + "ida_pseudo": "__int64 __fastcall func0(\n __int64 a1,\n __int64 a2,\n __int64 a3,\n __int64 a4,\n __int64 a5,\n __int64 a6,\n __int64 a7,\n __int64 a8,\n __int64 a9,\n __int64 a10,\n __int64 a11,\n __int64 a12,\n __int64 a13,\n __int64 a14)\n{\n __int64 result; // rax\n __int64 v15; // r13\n __int64 v16; // r12\n __int64 v17; // rax\n __int64 v18; // r13\n __int64 v19; // rbp\n char s1[8]; // [rsp+0h] [rbp-48h] BYREF\n __int64 v21; // [rsp+8h] [rbp-40h]\n\n result = 0LL;\n v15 = SLODWORD(STACK[0x1050]);\n if ( (_DWORD)v15 == LODWORD(STACK[0x2058]) )\n {\n if ( (int)v15 <= 0 )\n {\n return 1LL;\n }\n else\n {\n v16 = 0LL;\n v21 = v15 << 6;\n while ( 1 )\n {\n v17 = *(int *)((char *)&a14 + v16 + 4);\n if ( (_DWORD)v17 != *(_DWORD *)((char *)&STACK[0x1094] + v16) )\n return 0LL;\n if ( (int)v17 > 0 )\n {\n v18 = v16;\n v19 = v16 + 10 * v17;\n while ( !strcmp(&s1[v18 + 80], (const char *)&STACK[0x1058] + v18) )\n {\n v18 += 10LL;\n if ( v19 == v18 )\n goto LABEL_11;\n }\n return 0LL;\n }\nLABEL_11:\n v16 += 64LL;\n if ( v21 == v16 )\n return 1LL;\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1C10:\nendbr64\npush r15\nxor eax, eax\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmovsxd r13, [rsp+48h+arg_1000]\ncmp r13d, [rsp+48h+arg_2008]\njnz short loc_1CA0\ntest r13d, r13d\njle loc_1CBB\nshl r13, 6\nxor r12d, r12d\nlea r15, [rsp+48h+arg_3C]\nmov [rsp+48h+var_40], r13\nlea r14, [rsp+48h+arg_1044]\nlea rbx, [rsp+48h+arg_1008]\nloc_1C63:\nmovsxd rax, dword ptr [r15+r12]\ncmp eax, [r14+r12]\njnz short loc_1C9E\ntest eax, eax\njle short loc_1CB0\nlea rax, [rax+rax*4]\nmov r13, r12\nlea rbp, [r12+rax*2]\njmp short loc_1C89\nloc_1C80:\nadd r13, 0Ah\ncmp rbp, r13\njz short loc_1CB0\nloc_1C89:\nlea rax, [r13+50h]\nlea rsi, [rbx+r13]; s2\nlea rdi, [rsp+rax+48h+s1]; s1\ncall _strcmp\ntest eax, eax\njz short loc_1C80\nloc_1C9E:\nxor eax, eax\nloc_1CA0:\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1CB0:\nadd r12, 40h ; '@'\ncmp [rsp+48h+var_40], r12\njnz short loc_1C63\nloc_1CBB:\nmov eax, 1\njmp short loc_1CA0", + "ida_strip_pseudo": "__int64 __fastcall sub_1C10(\n __int64 a1,\n __int64 a2,\n __int64 a3,\n __int64 a4,\n __int64 a5,\n __int64 a6,\n __int64 a7,\n __int64 a8,\n __int64 a9,\n __int64 a10,\n __int64 a11,\n __int64 a12,\n __int64 a13,\n __int64 a14)\n{\n __int64 result; // rax\n __int64 v15; // r13\n __int64 v16; // r12\n __int64 v17; // rax\n __int64 v18; // r13\n __int64 v19; // rbp\n char s1[8]; // [rsp+0h] [rbp-48h] BYREF\n __int64 v21; // [rsp+8h] [rbp-40h]\n\n result = 0LL;\n v15 = SLODWORD(STACK[0x1050]);\n if ( (_DWORD)v15 == LODWORD(STACK[0x2058]) )\n {\n if ( (int)v15 <= 0 )\n {\n return 1LL;\n }\n else\n {\n v16 = 0LL;\n v21 = v15 << 6;\n while ( 1 )\n {\n v17 = *(int *)((char *)&a14 + v16 + 4);\n if ( (_DWORD)v17 != *(_DWORD *)((char *)&STACK[0x1094] + v16) )\n return 0LL;\n if ( (int)v17 > 0 )\n {\n v18 = v16;\n v19 = v16 + 10 * v17;\n while ( !strcmp(&s1[v18 + 80], (const char *)&STACK[0x1058] + v18) )\n {\n v18 += 10LL;\n if ( v19 == v18 )\n goto LABEL_11;\n }\n return 0LL;\n }\nLABEL_11:\n v16 += 64LL;\n if ( v21 == v16 )\n return 1LL;\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1C10(long long a1, long long a2, long long a3, long long a4,\n long long a5, long long a6, long long a7, long long a8,\n long long a9, long long a10, long long a11, long long a12,\n long long a13, long long a14) {\n long long result;\n long long v15;\n long long v16;\n long long v17;\n long long v18;\n long long v19;\n char s1[8];\n long long v21;\n result = 0LL;\n v15 = SLODWORD(STACK[4176]);\n if ((uint32_t)v15 == LODWORD(STACK[8280])) {\n if ((int)v15 <= 0) {\n return 1LL;\n } else {\n v16 = 0LL;\n v21 = v15 << 6;\n while (1) {\n v17 = *(int *)((char *)&a14 + v16 + 4);\n if ((uint32_t)v17 != *(uint32_t *)((char *)&STACK[4244] + v16))\n return 0LL;\n if ((int)v17 > 0) {\n v18 = v16;\n v19 = v16 + 10 * v17;\n while (!strcmp(&s1[v18 + 80], (const char *)&STACK[4184] + v18)) {\n v18 += 10LL;\n if (v19 == v18) goto LABEL_11;\n }\n return 0LL;\n }\n LABEL_11:\n v16 += 64LL;\n if (v21 == v16) return 1LL;\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, long long a3, long long a4,\n long long a5, long long a6, long long a7, long long a8,\n long long a9, long long a10, long long a11, long long a12,\n long long a13, long long a14) {\n long long result;\n long long v15;\n long long v16;\n long long v17;\n long long v18;\n long long v19;\n char s1[8];\n long long v21;\n result = 0LL;\n v15 = SLODWORD(STACK[4176]);\n if ((uint32_t)v15 == LODWORD(STACK[8280])) {\n if ((int)v15 <= 0) {\n return 1LL;\n } else {\n v16 = 0LL;\n v21 = v15 << 6;\n while (1) {\n v17 = *(int *)((char *)&a14 + v16 + 4);\n if ((uint32_t)v17 != *(uint32_t *)((char *)&STACK[4244] + v16))\n return 0LL;\n if ((int)v17 > 0) {\n v18 = v16;\n v19 = v16 + 10 * v17;\n while (!strcmp(&s1[v18 + 80], (const char *)&STACK[4184] + v18)) {\n v18 += 10LL;\n if (v19 == v18) goto LABEL_11;\n }\n return 0LL;\n }\n LABEL_11:\n v16 += 64LL;\n if (v21 == v16) return 1LL;\n }\n }\n }\n return result;\n}" + }, + { + "index": 463, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int max_ending_here = 1;\n int min_ending_here = 1;\n int max_so_far = 0;\n int flag = 0;\n for (int i = 0; i < n; i++) {\n if (arr[i] > 0) {\n max_ending_here = max_ending_here * arr[i];\n min_ending_here =\n (min_ending_here * arr[i] < 1) ? min_ending_here * arr[i] : 1;\n flag = 1;\n } else if (arr[i] == 0) {\n max_ending_here = 1;\n min_ending_here = 1;\n } else {\n int temp = max_ending_here;\n max_ending_here =\n (min_ending_here * arr[i] > 1) ? min_ending_here * arr[i] : 1;\n min_ending_here = temp * arr[i];\n }\n if (max_so_far < max_ending_here) {\n max_so_far = max_ending_here;\n }\n }\n if (flag == 0 && max_so_far == 0) {\n return 0;\n }\n return max_so_far;\n}", + "test": "int main() {\n\n int arr1[] = {1, -2, -3, 0, 7, -8, -2};\n\n int n1 = sizeof(arr1) / sizeof(arr1[0]);\n\n assert(func0(arr1, n1) == 112);\n\n\n\n int arr2[] = {6, -3, -10, 0, 2};\n\n int n2 = sizeof(arr2) / sizeof(arr2[0]);\n\n assert(func0(arr2, n2) == 180);\n\n\n\n int arr3[] = {-2, -40, 0, -2, -3};\n\n int n3 = sizeof(arr3) / sizeof(arr3[0]);\n\n assert(func0(arr3, n3) == 80);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmovl $0x1,-0x18(%rbp)\nmovl $0x1,-0x14(%rbp)\nmovl $0x0,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\njmpq 1291 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ntest %eax,%eax\njle 1209 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov -0x18(%rbp),%edx\nimul %edx,%eax\nmov %eax,-0x18(%rbp)\nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nimul -0x14(%rbp),%eax\nmov $0x1,%edx\ntest %eax,%eax\ncmovg %edx,%eax\nmov %eax,-0x14(%rbp)\nmovl $0x1,-0xc(%rbp)\njmp 127f \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ntest %eax,%eax\njne 1233 \nmovl $0x1,-0x18(%rbp)\nmovl $0x1,-0x14(%rbp)\njmp 127f \nmov -0x18(%rbp),%eax\nmov %eax,-0x4(%rbp)\nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nimul -0x14(%rbp),%eax\nmov $0x1,%edx\ntest %eax,%eax\ncmovle %edx,%eax\nmov %eax,-0x18(%rbp)\nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov -0x4(%rbp),%edx\nimul %edx,%eax\nmov %eax,-0x14(%rbp)\nmov -0x10(%rbp),%eax\ncmp -0x18(%rbp),%eax\njge 128d \nmov -0x18(%rbp),%eax\nmov %eax,-0x10(%rbp)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 11a0 \ncmpl $0x0,-0xc(%rbp)\njne 12b0 \ncmpl $0x0,-0x10(%rbp)\njne 12b0 \nmov $0x0,%eax\njmp 12b3 \nmov -0x10(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_18], 1\nmov [rbp+var_14], 1\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp loc_1291\nloc_11A0:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njle short loc_1209\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_18]\nimul eax, edx\nmov [rbp+var_18], eax\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nimul eax, [rbp+var_14]\nmov edx, 1\ntest eax, eax\ncmovg eax, edx\nmov [rbp+var_14], eax\nmov [rbp+var_C], 1\njmp short loc_127F\nloc_1209:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njnz short loc_1233\nmov [rbp+var_18], 1\nmov [rbp+var_14], 1\njmp short loc_127F\nloc_1233:\nmov eax, [rbp+var_18]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nimul eax, [rbp+var_14]\nmov edx, 1\ntest eax, eax\ncmovle eax, edx\nmov [rbp+var_18], eax\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_4]\nimul eax, edx\nmov [rbp+var_14], eax\nloc_127F:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_18]\njge short loc_128D\nmov eax, [rbp+var_18]\nmov [rbp+var_10], eax\nloc_128D:\nadd [rbp+var_8], 1\nloc_1291:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_2C]\njl loc_11A0\ncmp [rbp+var_C], 0\njnz short loc_12B0\ncmp [rbp+var_10], 0\njnz short loc_12B0\nmov eax, 0\njmp short loc_12B3\nloc_12B0:\nmov eax, [rbp+var_10]\nloc_12B3:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int v2; // eax\n int v3; // eax\n int v5; // [rsp+14h] [rbp-18h]\n int v6; // [rsp+18h] [rbp-14h]\n int v7; // [rsp+1Ch] [rbp-10h]\n int v8; // [rsp+20h] [rbp-Ch]\n int i; // [rsp+24h] [rbp-8h]\n int v10; // [rsp+28h] [rbp-4h]\n\n v5 = 1;\n v6 = 1;\n v7 = 0;\n v8 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(int *)(4LL * i + a1) <= 0 )\n {\n if ( *(_DWORD *)(4LL * i + a1) )\n {\n v10 = v5;\n v3 = v6 * *(_DWORD *)(4LL * i + a1);\n if ( v3 <= 0 )\n v3 = 1;\n v5 = v3;\n v6 = v10 * *(_DWORD *)(4LL * i + a1);\n }\n else\n {\n v5 = 1;\n v6 = 1;\n }\n }\n else\n {\n v5 *= *(_DWORD *)(4LL * i + a1);\n v2 = v6 * *(_DWORD *)(4LL * i + a1);\n if ( v2 > 0 )\n v2 = 1;\n v6 = v2;\n v8 = 1;\n }\n if ( v7 < v5 )\n v7 = v5;\n }\n if ( v8 || v7 )\n return (unsigned int)v7;\n else\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_18], 1\nmov [rbp+var_14], 1\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp loc_1291\nloc_11A0:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njle short loc_1209\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_18]\nimul eax, edx\nmov [rbp+var_18], eax\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nimul eax, [rbp+var_14]\nmov edx, 1\ntest eax, eax\ncmovg eax, edx\nmov [rbp+var_14], eax\nmov [rbp+var_C], 1\njmp short loc_127F\nloc_1209:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njnz short loc_1233\nmov [rbp+var_18], 1\nmov [rbp+var_14], 1\njmp short loc_127F\nloc_1233:\nmov eax, [rbp+var_18]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nimul eax, [rbp+var_14]\nmov edx, 1\ntest eax, eax\ncmovle eax, edx\nmov [rbp+var_18], eax\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_4]\nimul eax, edx\nmov [rbp+var_14], eax\nloc_127F:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_18]\njge short loc_128D\nmov eax, [rbp+var_18]\nmov [rbp+var_10], eax\nloc_128D:\nadd [rbp+var_8], 1\nloc_1291:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_2C]\njl loc_11A0\ncmp [rbp+var_C], 0\njnz short loc_12B0\ncmp [rbp+var_10], 0\njnz short loc_12B0\nmov eax, 0\njmp short loc_12B3\nloc_12B0:\nmov eax, [rbp+var_10]\nloc_12B3:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int v2; // eax\n int v3; // eax\n int v5; // [rsp+14h] [rbp-18h]\n int v6; // [rsp+18h] [rbp-14h]\n int v7; // [rsp+1Ch] [rbp-10h]\n int v8; // [rsp+20h] [rbp-Ch]\n int i; // [rsp+24h] [rbp-8h]\n int v10; // [rsp+28h] [rbp-4h]\n\n v5 = 1;\n v6 = 1;\n v7 = 0;\n v8 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(int *)(4LL * i + a1) <= 0 )\n {\n if ( *(_DWORD *)(4LL * i + a1) )\n {\n v10 = v5;\n v3 = v6 * *(_DWORD *)(4LL * i + a1);\n if ( v3 <= 0 )\n v3 = 1;\n v5 = v3;\n v6 = v10 * *(_DWORD *)(4LL * i + a1);\n }\n else\n {\n v5 = 1;\n v6 = 1;\n }\n }\n else\n {\n v5 *= *(_DWORD *)(4LL * i + a1);\n v2 = v6 * *(_DWORD *)(4LL * i + a1);\n if ( v2 > 0 )\n v2 = 1;\n v6 = v2;\n v8 = 1;\n }\n if ( v7 < v5 )\n v7 = v5;\n }\n if ( v8 || v7 )\n return (unsigned int)v7;\n else\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int v2;\n int v3;\n int v5;\n int v6;\n int v7;\n int v8;\n int i;\n int v10;\n v5 = 1;\n v6 = 1;\n v7 = 0;\n v8 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(int *)(4LL * i + a1) <= 0) {\n if (*(uint32_t *)(4LL * i + a1)) {\n v10 = v5;\n v3 = v6 * *(uint32_t *)(4LL * i + a1);\n if (v3 <= 0) v3 = 1;\n v5 = v3;\n v6 = v10 * *(uint32_t *)(4LL * i + a1);\n } else {\n v5 = 1;\n v6 = 1;\n }\n } else {\n v5 *= *(uint32_t *)(4LL * i + a1);\n v2 = v6 * *(uint32_t *)(4LL * i + a1);\n if (v2 > 0) v2 = 1;\n v6 = v2;\n v8 = 1;\n }\n if (v7 < v5) v7 = v5;\n }\n if (v8 || v7)\n return (unsigned int)v7;\n else\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int v2;\n int v3;\n int v5;\n int v6;\n int v7;\n int v8;\n int i;\n int v10;\n v5 = 1;\n v6 = 1;\n v7 = 0;\n v8 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(int *)(4LL * i + a1) <= 0) {\n if (*(uint32_t *)(4LL * i + a1)) {\n v10 = v5;\n v3 = v6 * *(uint32_t *)(4LL * i + a1);\n if (v3 <= 0) v3 = 1;\n v5 = v3;\n v6 = v10 * *(uint32_t *)(4LL * i + a1);\n } else {\n v5 = 1;\n v6 = 1;\n }\n } else {\n v5 *= *(uint32_t *)(4LL * i + a1);\n v2 = v6 * *(uint32_t *)(4LL * i + a1);\n if (v2 > 0) v2 = 1;\n v6 = v2;\n v8 = 1;\n }\n if (v7 < v5) v7 = v5;\n }\n if (v8 || v7)\n return (unsigned int)v7;\n else\n return 0LL;\n}" + }, + { + "index": 463, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int max_ending_here = 1;\n int min_ending_here = 1;\n int max_so_far = 0;\n int flag = 0;\n for (int i = 0; i < n; i++) {\n if (arr[i] > 0) {\n max_ending_here = max_ending_here * arr[i];\n min_ending_here =\n (min_ending_here * arr[i] < 1) ? min_ending_here * arr[i] : 1;\n flag = 1;\n } else if (arr[i] == 0) {\n max_ending_here = 1;\n min_ending_here = 1;\n } else {\n int temp = max_ending_here;\n max_ending_here =\n (min_ending_here * arr[i] > 1) ? min_ending_here * arr[i] : 1;\n min_ending_here = temp * arr[i];\n }\n if (max_so_far < max_ending_here) {\n max_so_far = max_ending_here;\n }\n }\n if (flag == 0 && max_so_far == 0) {\n return 0;\n }\n return max_so_far;\n}", + "test": "int main() {\n\n int arr1[] = {1, -2, -3, 0, 7, -8, -2};\n\n int n1 = sizeof(arr1) / sizeof(arr1[0]);\n\n assert(func0(arr1, n1) == 112);\n\n\n\n int arr2[] = {6, -3, -10, 0, 2};\n\n int n2 = sizeof(arr2) / sizeof(arr2[0]);\n\n assert(func0(arr2, n2) == 180);\n\n\n\n int arr3[] = {-2, -40, 0, -2, -3};\n\n int n3 = sizeof(arr3) / sizeof(arr3[0]);\n\n assert(func0(arr3, n3) == 80);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11ea \nmov %rdi,%rax\nlea -0x1(%rsi),%edx\nlea 0x4(%rdi,%rdx,4),%r10\nmov $0x0,%r9d\nmov $0x0,%esi\nmov $0x1,%edi\nmov $0x1,%ecx\nmov $0x1,%r8d\njmp 11bd \nje 11d6 \nimul %edx,%edi\nmov %edi,%r11d\ntest %edi,%edi\ncmovle %r8d,%r11d\nmov %edx,%edi\nimul %ecx,%edi\nmov %r11d,%ecx\ncmp %ecx,%esi\ncmovl %ecx,%esi\nadd $0x4,%rax\ncmp %r10,%rax\nje 11e0 \nmov (%rax),%edx\ntest %edx,%edx\njle 1199 \nimul %edx,%ecx\nimul %edi,%edx\ntest %edx,%edx\nmov %edx,%edi\ncmovg %r8d,%edi\nmov %r8d,%r9d\njmp 11af \nmov %r8d,%edi\nmov $0x1,%ecx\njmp 11af \nor %esi,%r9d\ncmove %r9d,%esi\nmov %esi,%eax\nretq\nmov $0x0,%esi\njmp 11e7 \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11EE\nmov rdx, rdi\nmovsxd rsi, esi\nlea r9, [rdi+rsi*4]\nmov r8d, 0\nmov esi, 0\nmov edi, 1\nmov eax, 1\nmov r10d, 1\njmp short loc_11B9\nloc_1198:\nimul eax, ecx\nimul edi, ecx\ntest edi, edi\nmov ecx, 1\ncmovg edi, ecx\nmov r8d, r10d\nloc_11AB:\ncmp esi, eax\ncmovl esi, eax\nadd rdx, 4\ncmp r9, rdx\njz short loc_11E4\nloc_11B9:\nmov ecx, [rdx]\ntest ecx, ecx\njg short loc_1198\njz short loc_11DA\nimul edi, ecx\nmov r11d, edi\nmov edi, ecx\nimul edi, eax\ntest r11d, r11d\nmov eax, 1\ncmovg eax, r11d\njmp short loc_11AB\nloc_11DA:\nmov edi, r10d\nmov eax, 1\njmp short loc_11AB\nloc_11E4:\nor r8d, esi\ncmovz esi, r8d\nloc_11EB:\nmov eax, esi\nretn\nloc_11EE:\nmov esi, 0\njmp short loc_11EB", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int *v2; // rdx\n int *v3; // r9\n int v4; // r8d\n int v5; // esi\n int v6; // edi\n int v7; // eax\n int v8; // ecx\n int v9; // r11d\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n v5 = 0;\n v6 = 1;\n v7 = 1;\n do\n {\n v8 = *v2;\n if ( *v2 > 0 )\n {\n v7 *= v8;\n v6 *= v8;\n if ( v6 > 0 )\n v6 = 1;\n v4 = 1;\n }\n else if ( v8 )\n {\n v9 = v8 * v6;\n v6 = v7 * v8;\n v7 = 1;\n if ( v9 > 0 )\n v7 = v9;\n }\n else\n {\n v6 = 1;\n v7 = 1;\n }\n if ( v5 < v7 )\n v5 = v7;\n ++v2;\n }\n while ( v3 != v2 );\n if ( !(v5 | v4) )\n return 0;\n }\n return (unsigned int)v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11EE\nmov rdx, rdi\nmovsxd rsi, esi\nlea r9, [rdi+rsi*4]\nmov r8d, 0\nmov esi, 0\nmov edi, 1\nmov eax, 1\nmov r10d, 1\njmp short loc_11B9\nloc_1198:\nimul eax, ecx\nimul edi, ecx\ntest edi, edi\nmov ecx, 1\ncmovg edi, ecx\nmov r8d, r10d\nloc_11AB:\ncmp esi, eax\ncmovl esi, eax\nadd rdx, 4\ncmp r9, rdx\njz short loc_11E4\nloc_11B9:\nmov ecx, [rdx]\ntest ecx, ecx\njg short loc_1198\njz short loc_11DA\nimul edi, ecx\nmov r11d, edi\nmov edi, ecx\nimul edi, eax\ntest r11d, r11d\nmov eax, 1\ncmovg eax, r11d\njmp short loc_11AB\nloc_11DA:\nmov edi, r10d\nmov eax, 1\njmp short loc_11AB\nloc_11E4:\nor r8d, esi\ncmovz esi, r8d\nloc_11EB:\nmov eax, esi\nretn\nloc_11EE:\nmov esi, 0\njmp short loc_11EB", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int *a1, int a2)\n{\n int *v2; // rdx\n int *v3; // r9\n int v4; // r8d\n int v5; // esi\n int v6; // edi\n int v7; // eax\n int v8; // ecx\n int v9; // r11d\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n v5 = 0;\n v6 = 1;\n v7 = 1;\n do\n {\n v8 = *v2;\n if ( *v2 > 0 )\n {\n v7 *= v8;\n v6 *= v8;\n if ( v6 > 0 )\n v6 = 1;\n v4 = 1;\n }\n else if ( v8 )\n {\n v9 = v8 * v6;\n v6 = v7 * v8;\n v7 = 1;\n if ( v9 > 0 )\n v7 = v9;\n }\n else\n {\n v6 = 1;\n v7 = 1;\n }\n if ( v5 < v7 )\n v5 = v7;\n ++v2;\n }\n while ( v3 != v2 );\n if ( !(v5 | v4) )\n return 0;\n }\n return (unsigned int)v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int *a1, int a2) {\n int *v2;\n int *v3;\n int v4;\n int v5;\n int v6;\n int v7;\n int v8;\n int v9;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n v5 = 0;\n v6 = 1;\n v7 = 1;\n do {\n v8 = *v2;\n if (*v2 > 0) {\n v7 *= v8;\n v6 *= v8;\n if (v6 > 0) v6 = 1;\n v4 = 1;\n } else if (v8) {\n v9 = v8 * v6;\n v6 = v7 * v8;\n v7 = 1;\n if (v9 > 0) v7 = v9;\n } else {\n v6 = 1;\n v7 = 1;\n }\n if (v5 < v7) v5 = v7;\n ++v2;\n } while (v3 != v2);\n if (!(v5 | v4)) return 0;\n }\n return (unsigned int)v5;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int *v2;\n int *v3;\n int v4;\n int v5;\n int v6;\n int v7;\n int v8;\n int v9;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n v5 = 0;\n v6 = 1;\n v7 = 1;\n do {\n v8 = *v2;\n if (*v2 > 0) {\n v7 *= v8;\n v6 *= v8;\n if (v6 > 0) v6 = 1;\n v4 = 1;\n } else if (v8) {\n v9 = v8 * v6;\n v6 = v7 * v8;\n v7 = 1;\n if (v9 > 0) v7 = v9;\n } else {\n v6 = 1;\n v7 = 1;\n }\n if (v5 < v7) v5 = v7;\n ++v2;\n } while (v3 != v2);\n if (!(v5 | v4)) return 0;\n }\n return (unsigned int)v5;\n}" + }, + { + "index": 463, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int max_ending_here = 1;\n int min_ending_here = 1;\n int max_so_far = 0;\n int flag = 0;\n for (int i = 0; i < n; i++) {\n if (arr[i] > 0) {\n max_ending_here = max_ending_here * arr[i];\n min_ending_here =\n (min_ending_here * arr[i] < 1) ? min_ending_here * arr[i] : 1;\n flag = 1;\n } else if (arr[i] == 0) {\n max_ending_here = 1;\n min_ending_here = 1;\n } else {\n int temp = max_ending_here;\n max_ending_here =\n (min_ending_here * arr[i] > 1) ? min_ending_here * arr[i] : 1;\n min_ending_here = temp * arr[i];\n }\n if (max_so_far < max_ending_here) {\n max_so_far = max_ending_here;\n }\n }\n if (flag == 0 && max_so_far == 0) {\n return 0;\n }\n return max_so_far;\n}", + "test": "int main() {\n\n int arr1[] = {1, -2, -3, 0, 7, -8, -2};\n\n int n1 = sizeof(arr1) / sizeof(arr1[0]);\n\n assert(func0(arr1, n1) == 112);\n\n\n\n int arr2[] = {6, -3, -10, 0, 2};\n\n int n2 = sizeof(arr2) / sizeof(arr2[0]);\n\n assert(func0(arr2, n2) == 180);\n\n\n\n int arr3[] = {-2, -40, 0, -2, -3};\n\n int n3 = sizeof(arr3) / sizeof(arr3[0]);\n\n assert(func0(arr3, n3) == 80);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1350 \nlea -0x1(%rsi),%eax\nxor %r8d,%r8d\nmov $0x1,%edx\nmov $0x1,%r10d\nlea 0x4(%rdi,%rax,4),%rsi\nmov $0x1,%eax\njmp 130c \nnopl 0x0(%rax)\nimul %ecx,%edx\nimul %ecx,%eax\ntest %edx,%edx\ncmovg %r10d,%edx\ncmp %eax,%r8d\ncmovl %eax,%r8d\nadd $0x4,%rdi\ncmp %rsi,%rdi\nje 1338 \nmov (%rdi),%ecx\ntest %ecx,%ecx\njg 12f0 \nje 1340 \nimul %ecx,%edx\ntest %edx,%edx\nmov %edx,%r9d\ncmovle %r10d,%r9d\nimul %eax,%ecx\nmov %r9d,%eax\ncmp %eax,%r8d\nmov %ecx,%edx\ncmovl %eax,%r8d\nadd $0x4,%rdi\ncmp %rsi,%rdi\njne 130c \nmov %r8d,%eax\nretq\nnopl 0x0(%rax)\nmov $0x1,%edx\nmov $0x1,%eax\njmp 12fc \nnopl 0x0(%rax)\nxor %r8d,%r8d\nmov %r8d,%eax\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle loc_1330\nmovsxd rsi, esi\nxor r9d, r9d\nmov edx, 1\nmov eax, 1\nlea r8, [rdi+rsi*4]\nxor esi, esi\njmp short loc_12DC\nloc_12B8:\nimul edx, ecx\nmov r9d, 1\nimul eax, ecx\nmov ecx, 1\ntest edx, edx\ncmovg edx, ecx\nloc_12CE:\ncmp esi, eax\ncmovl esi, eax\nadd rdi, 4\ncmp r8, rdi\njz short loc_1309\nloc_12DC:\nmov ecx, [rdi]\ntest ecx, ecx\njg short loc_12B8\njz short loc_1320\nimul edx, ecx\nimul eax, ecx\nmov r10d, edx\ntest r10d, r10d\nmov edx, eax\nmov eax, 1\ncmovg eax, r10d\ncmp esi, eax\ncmovl esi, eax\nadd rdi, 4\ncmp r8, rdi\njnz short loc_12DC\nloc_1309:\nor r9d, esi\nmov eax, 0\ncmovz esi, eax\nmov eax, esi\nretn\nloc_1320:\nmov edx, 1\nmov eax, 1\njmp short loc_12CE\nloc_1330:\nxor esi, esi\nmov eax, esi\nretn", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int v2; // r9d\n int v3; // edx\n int v4; // eax\n int *v5; // r8\n int v6; // esi\n int v7; // ecx\n int v8; // r10d\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 0;\n v3 = 1;\n v4 = 1;\n v5 = &a1[a2];\n v6 = 0;\n do\n {\n while ( 1 )\n {\n v7 = *a1;\n if ( *a1 > 0 )\n break;\n if ( !v7 )\n {\n v3 = 1;\n v4 = 1;\n goto LABEL_5;\n }\n v8 = v7 * v3;\n v3 = v7 * v4;\n v4 = 1;\n if ( v8 > 0 )\n v4 = v8;\n if ( v6 < v4 )\n v6 = v4;\n if ( v5 == ++a1 )\n goto LABEL_15;\n }\n v3 *= v7;\n v2 = 1;\n v4 *= v7;\n if ( v3 > 0 )\n v3 = 1;\nLABEL_5:\n if ( v6 < v4 )\n v6 = v4;\n ++a1;\n }\n while ( v5 != a1 );\nLABEL_15:\n if ( !(v6 | v2) )\n return 0;\n return (unsigned int)v6;\n}", + "ida_strip_asm": "sub_1290:\nendbr64\ntest esi, esi\njle loc_1330\nmovsxd rsi, esi\nxor r9d, r9d\nmov edx, 1\nmov eax, 1\nlea r8, [rdi+rsi*4]\nxor esi, esi\njmp short loc_12DC\nloc_12B8:\nimul edx, ecx\nmov r9d, 1\nimul eax, ecx\nmov ecx, 1\ntest edx, edx\ncmovg edx, ecx\nloc_12CE:\ncmp esi, eax\ncmovl esi, eax\nadd rdi, 4\ncmp r8, rdi\njz short loc_1309\nloc_12DC:\nmov ecx, [rdi]\ntest ecx, ecx\njg short loc_12B8\njz short loc_1320\nimul edx, ecx\nimul eax, ecx\nmov r10d, edx\ntest r10d, r10d\nmov edx, eax\nmov eax, 1\ncmovg eax, r10d\ncmp esi, eax\ncmovl esi, eax\nadd rdi, 4\ncmp r8, rdi\njnz short loc_12DC\nloc_1309:\nor r9d, esi\nmov eax, 0\ncmovz esi, eax\nmov eax, esi\nretn\nloc_1320:\nmov edx, 1\nmov eax, 1\njmp short loc_12CE\nloc_1330:\nxor esi, esi\nmov eax, esi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1290(int *a1, int a2)\n{\n int v2; // r9d\n int v3; // edx\n int v4; // eax\n int *v5; // r8\n int v6; // esi\n int v7; // ecx\n int v8; // r10d\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 0;\n v3 = 1;\n v4 = 1;\n v5 = &a1[a2];\n v6 = 0;\n do\n {\n while ( 1 )\n {\n v7 = *a1;\n if ( *a1 > 0 )\n break;\n if ( !v7 )\n {\n v3 = 1;\n v4 = 1;\n goto LABEL_5;\n }\n v8 = v7 * v3;\n v3 = v7 * v4;\n v4 = 1;\n if ( v8 > 0 )\n v4 = v8;\n if ( v6 < v4 )\n v6 = v4;\n if ( v5 == ++a1 )\n goto LABEL_15;\n }\n v3 *= v7;\n v2 = 1;\n v4 *= v7;\n if ( v3 > 0 )\n v3 = 1;\nLABEL_5:\n if ( v6 < v4 )\n v6 = v4;\n ++a1;\n }\n while ( v5 != a1 );\nLABEL_15:\n if ( !(v6 | v2) )\n return 0;\n return (unsigned int)v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1290(int *a1, int a2) {\n int v2;\n int v3;\n int v4;\n int *v5;\n int v6;\n int v7;\n int v8;\n if (a2 <= 0) return 0LL;\n v2 = 0;\n v3 = 1;\n v4 = 1;\n v5 = &a1[a2];\n v6 = 0;\n do {\n while (1) {\n v7 = *a1;\n if (*a1 > 0) break;\n if (!v7) {\n v3 = 1;\n v4 = 1;\n goto LABEL_5;\n }\n v8 = v7 * v3;\n v3 = v7 * v4;\n v4 = 1;\n if (v8 > 0) v4 = v8;\n if (v6 < v4) v6 = v4;\n if (v5 == ++a1) goto LABEL_15;\n }\n v3 *= v7;\n v2 = 1;\n v4 *= v7;\n if (v3 > 0) v3 = 1;\n LABEL_5:\n if (v6 < v4) v6 = v4;\n ++a1;\n } while (v5 != a1);\nLABEL_15:\n if (!(v6 | v2)) return 0;\n return (unsigned int)v6;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int v2;\n int v3;\n int v4;\n int *v5;\n int v6;\n int v7;\n int v8;\n if (a2 <= 0) return 0LL;\n v2 = 0;\n v3 = 1;\n v4 = 1;\n v5 = &a1[a2];\n v6 = 0;\n do {\n while (1) {\n v7 = *a1;\n if (*a1 > 0) break;\n if (!v7) {\n v3 = 1;\n v4 = 1;\n goto LABEL_5;\n }\n v8 = v7 * v3;\n v3 = v7 * v4;\n v4 = 1;\n if (v8 > 0) v4 = v8;\n if (v6 < v4) v6 = v4;\n if (v5 == ++a1) goto LABEL_15;\n }\n v3 *= v7;\n v2 = 1;\n v4 *= v7;\n if (v3 > 0) v3 = 1;\n LABEL_5:\n if (v6 < v4) v6 = v4;\n ++a1;\n } while (v5 != a1);\nLABEL_15:\n if (!(v6 | v2)) return 0;\n return (unsigned int)v6;\n}" + }, + { + "index": 463, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int max_ending_here = 1;\n int min_ending_here = 1;\n int max_so_far = 0;\n int flag = 0;\n for (int i = 0; i < n; i++) {\n if (arr[i] > 0) {\n max_ending_here = max_ending_here * arr[i];\n min_ending_here =\n (min_ending_here * arr[i] < 1) ? min_ending_here * arr[i] : 1;\n flag = 1;\n } else if (arr[i] == 0) {\n max_ending_here = 1;\n min_ending_here = 1;\n } else {\n int temp = max_ending_here;\n max_ending_here =\n (min_ending_here * arr[i] > 1) ? min_ending_here * arr[i] : 1;\n min_ending_here = temp * arr[i];\n }\n if (max_so_far < max_ending_here) {\n max_so_far = max_ending_here;\n }\n }\n if (flag == 0 && max_so_far == 0) {\n return 0;\n }\n return max_so_far;\n}", + "test": "int main() {\n\n int arr1[] = {1, -2, -3, 0, 7, -8, -2};\n\n int n1 = sizeof(arr1) / sizeof(arr1[0]);\n\n assert(func0(arr1, n1) == 112);\n\n\n\n int arr2[] = {6, -3, -10, 0, 2};\n\n int n2 = sizeof(arr2) / sizeof(arr2[0]);\n\n assert(func0(arr2, n2) == 180);\n\n\n\n int arr3[] = {-2, -40, 0, -2, -3};\n\n int n3 = sizeof(arr3) / sizeof(arr3[0]);\n\n assert(func0(arr3, n3) == 80);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1320 \nlea -0x1(%rsi),%eax\nxor %r8d,%r8d\nmov $0x1,%edx\nmov $0x1,%r10d\nlea 0x4(%rdi,%rax,4),%rsi\nmov $0x1,%eax\njmp 12dc \nnopl 0x0(%rax)\nimul %ecx,%edx\nimul %ecx,%eax\ntest %edx,%edx\ncmovg %r10d,%edx\ncmp %eax,%r8d\ncmovl %eax,%r8d\nadd $0x4,%rdi\ncmp %rdi,%rsi\nje 1308 \nmov (%rdi),%ecx\ntest %ecx,%ecx\njg 12c0 \nje 1310 \nimul %ecx,%edx\ntest %edx,%edx\nmov %edx,%r9d\ncmovle %r10d,%r9d\nimul %eax,%ecx\nmov %r9d,%eax\ncmp %eax,%r8d\nmov %ecx,%edx\ncmovl %eax,%r8d\nadd $0x4,%rdi\ncmp %rdi,%rsi\njne 12dc \nmov %r8d,%eax\nretq\nnopl 0x0(%rax)\nmov $0x1,%edx\nmov $0x1,%eax\njmp 12cc \nnopl 0x0(%rax)\nxor %r8d,%r8d\nmov %r8d,%eax\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle loc_1330\nmovsxd rsi, esi\nxor r9d, r9d\nmov edx, 1\nmov eax, 1\nlea r8, [rdi+rsi*4]\nxor esi, esi\njmp short loc_12DC\nloc_12B8:\nimul edx, ecx\nmov r9d, 1\nimul eax, ecx\nmov ecx, 1\ntest edx, edx\ncmovg edx, ecx\nloc_12CE:\ncmp esi, eax\ncmovl esi, eax\nadd rdi, 4\ncmp r8, rdi\njz short loc_1309\nloc_12DC:\nmov ecx, [rdi]\ntest ecx, ecx\njg short loc_12B8\njz short loc_1320\nimul edx, ecx\nimul eax, ecx\nmov r10d, edx\ntest r10d, r10d\nmov edx, eax\nmov eax, 1\ncmovg eax, r10d\ncmp esi, eax\ncmovl esi, eax\nadd rdi, 4\ncmp r8, rdi\njnz short loc_12DC\nloc_1309:\nor r9d, esi\nmov eax, 0\ncmovz esi, eax\nmov eax, esi\nretn\nloc_1320:\nmov edx, 1\nmov eax, 1\njmp short loc_12CE\nloc_1330:\nxor esi, esi\nmov eax, esi\nretn", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int v2; // r9d\n int v3; // edx\n int v4; // eax\n int *v5; // r8\n int v6; // esi\n int v7; // ecx\n int v8; // r10d\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 0;\n v3 = 1;\n v4 = 1;\n v5 = &a1[a2];\n v6 = 0;\n do\n {\n while ( 1 )\n {\n v7 = *a1;\n if ( *a1 > 0 )\n break;\n if ( !v7 )\n {\n v3 = 1;\n v4 = 1;\n goto LABEL_5;\n }\n v8 = v7 * v3;\n v3 = v7 * v4;\n v4 = 1;\n if ( v8 > 0 )\n v4 = v8;\n if ( v6 < v4 )\n v6 = v4;\n if ( v5 == ++a1 )\n goto LABEL_15;\n }\n v3 *= v7;\n v2 = 1;\n v4 *= v7;\n if ( v3 > 0 )\n v3 = 1;\nLABEL_5:\n if ( v6 < v4 )\n v6 = v4;\n ++a1;\n }\n while ( v5 != a1 );\nLABEL_15:\n if ( !(v6 | v2) )\n return 0;\n return (unsigned int)v6;\n}", + "ida_strip_asm": "sub_1290:\nendbr64\ntest esi, esi\njle loc_1330\nmovsxd rsi, esi\nxor r9d, r9d\nmov edx, 1\nmov eax, 1\nlea r8, [rdi+rsi*4]\nxor esi, esi\njmp short loc_12DC\nloc_12B8:\nimul edx, ecx\nmov r9d, 1\nimul eax, ecx\nmov ecx, 1\ntest edx, edx\ncmovg edx, ecx\nloc_12CE:\ncmp esi, eax\ncmovl esi, eax\nadd rdi, 4\ncmp r8, rdi\njz short loc_1309\nloc_12DC:\nmov ecx, [rdi]\ntest ecx, ecx\njg short loc_12B8\njz short loc_1320\nimul edx, ecx\nimul eax, ecx\nmov r10d, edx\ntest r10d, r10d\nmov edx, eax\nmov eax, 1\ncmovg eax, r10d\ncmp esi, eax\ncmovl esi, eax\nadd rdi, 4\ncmp r8, rdi\njnz short loc_12DC\nloc_1309:\nor r9d, esi\nmov eax, 0\ncmovz esi, eax\nmov eax, esi\nretn\nloc_1320:\nmov edx, 1\nmov eax, 1\njmp short loc_12CE\nloc_1330:\nxor esi, esi\nmov eax, esi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1290(int *a1, int a2)\n{\n int v2; // r9d\n int v3; // edx\n int v4; // eax\n int *v5; // r8\n int v6; // esi\n int v7; // ecx\n int v8; // r10d\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 0;\n v3 = 1;\n v4 = 1;\n v5 = &a1[a2];\n v6 = 0;\n do\n {\n while ( 1 )\n {\n v7 = *a1;\n if ( *a1 > 0 )\n break;\n if ( !v7 )\n {\n v3 = 1;\n v4 = 1;\n goto LABEL_5;\n }\n v8 = v7 * v3;\n v3 = v7 * v4;\n v4 = 1;\n if ( v8 > 0 )\n v4 = v8;\n if ( v6 < v4 )\n v6 = v4;\n if ( v5 == ++a1 )\n goto LABEL_15;\n }\n v3 *= v7;\n v2 = 1;\n v4 *= v7;\n if ( v3 > 0 )\n v3 = 1;\nLABEL_5:\n if ( v6 < v4 )\n v6 = v4;\n ++a1;\n }\n while ( v5 != a1 );\nLABEL_15:\n if ( !(v6 | v2) )\n return 0;\n return (unsigned int)v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1290(int *a1, int a2) {\n int v2;\n int v3;\n int v4;\n int *v5;\n int v6;\n int v7;\n int v8;\n if (a2 <= 0) return 0LL;\n v2 = 0;\n v3 = 1;\n v4 = 1;\n v5 = &a1[a2];\n v6 = 0;\n do {\n while (1) {\n v7 = *a1;\n if (*a1 > 0) break;\n if (!v7) {\n v3 = 1;\n v4 = 1;\n goto LABEL_5;\n }\n v8 = v7 * v3;\n v3 = v7 * v4;\n v4 = 1;\n if (v8 > 0) v4 = v8;\n if (v6 < v4) v6 = v4;\n if (v5 == ++a1) goto LABEL_15;\n }\n v3 *= v7;\n v2 = 1;\n v4 *= v7;\n if (v3 > 0) v3 = 1;\n LABEL_5:\n if (v6 < v4) v6 = v4;\n ++a1;\n } while (v5 != a1);\nLABEL_15:\n if (!(v6 | v2)) return 0;\n return (unsigned int)v6;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int v2;\n int v3;\n int v4;\n int *v5;\n int v6;\n int v7;\n int v8;\n if (a2 <= 0) return 0LL;\n v2 = 0;\n v3 = 1;\n v4 = 1;\n v5 = &a1[a2];\n v6 = 0;\n do {\n while (1) {\n v7 = *a1;\n if (*a1 > 0) break;\n if (!v7) {\n v3 = 1;\n v4 = 1;\n goto LABEL_5;\n }\n v8 = v7 * v3;\n v3 = v7 * v4;\n v4 = 1;\n if (v8 > 0) v4 = v8;\n if (v6 < v4) v6 = v4;\n if (v5 == ++a1) goto LABEL_15;\n }\n v3 *= v7;\n v2 = 1;\n v4 *= v7;\n if (v3 > 0) v3 = 1;\n LABEL_5:\n if (v6 < v4) v6 = v4;\n ++a1;\n } while (v5 != a1);\nLABEL_15:\n if (!(v6 | v2)) return 0;\n return (unsigned int)v6;\n}" + }, + { + "index": 464, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int dict[], int size, int n) {\n for (int i = 0; i < size; i++) {\n if (dict[i] != n) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n int dict1[] = {12, 12, 12, 12};\n\n int dictSize1 = sizeof(dict1) / sizeof(dict1[0]);\n\n \n\n assert(func0(dict1, dictSize1, 10) == false);\n\n assert(func0(dict1, dictSize1, 12) == true);\n\n assert(func0(dict1, dictSize1, 5) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11aa \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x20(%rbp)\nje 11a6 \nmov $0x0,%eax\njmp 11b7 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1184 \nmov $0x1,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_4], 0\njmp short loc_11AA\nloc_1184:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njz short loc_11A6\nmov eax, 0\njmp short loc_11B7\nloc_11A6:\nadd [rbp+var_4], 1\nloc_11AA:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1184\nmov eax, 1\nloc_11B7:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n int i; // [rsp+1Ch] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n if ( a3 != *(_DWORD *)(4LL * i + a1) )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_4], 0\njmp short loc_11AA\nloc_1184:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njz short loc_11A6\nmov eax, 0\njmp short loc_11B7\nloc_11A6:\nadd [rbp+var_4], 1\nloc_11AA:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1184\nmov eax, 1\nloc_11B7:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n int i; // [rsp+1Ch] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n if ( a3 != *(_DWORD *)(4LL * i + a1) )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n int i;\n for (i = 0; i < a2; ++i) {\n if (a3 != *(uint32_t *)(4LL * i + a1)) return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n int i;\n for (i = 0; i < a2; ++i) {\n if (a3 != *(uint32_t *)(4LL * i + a1)) return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": 464, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int dict[], int size, int n) {\n for (int i = 0; i < size; i++) {\n if (dict[i] != n) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n int dict1[] = {12, 12, 12, 12};\n\n int dictSize1 = sizeof(dict1) / sizeof(dict1[0]);\n\n \n\n assert(func0(dict1, dictSize1, 10) == false);\n\n assert(func0(dict1, dictSize1, 12) == true);\n\n assert(func0(dict1, dictSize1, 5) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 118f \nmov %rdi,%rax\nlea -0x1(%rsi),%ecx\nlea 0x4(%rdi,%rcx,4),%rcx\ncmp %edx,(%rax)\njne 1195 \nadd $0x4,%rax\ncmp %rcx,%rax\njne 117c \nmov $0x1,%eax\nretq\nmov $0x1,%eax\nretq\nmov $0x0,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_118E\nmov rax, rdi\nmovsxd rsi, esi\nlea rcx, [rdi+rsi*4]\nloc_117B:\ncmp [rax], edx\njnz short loc_1194\nadd rax, 4\ncmp rax, rcx\njnz short loc_117B\nmov eax, 1\nretn\nloc_118E:\nmov eax, 1\nretn\nloc_1194:\nmov eax, 0\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2, int a3)\n{\n _DWORD *v3; // rax\n\n if ( a2 <= 0 )\n return 1LL;\n v3 = a1;\n while ( *v3 == a3 )\n {\n if ( ++v3 == &a1[a2] )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_118E\nmov rax, rdi\nmovsxd rsi, esi\nlea rcx, [rdi+rsi*4]\nloc_117B:\ncmp [rax], edx\njnz short loc_1194\nadd rax, 4\ncmp rax, rcx\njnz short loc_117B\nmov eax, 1\nretn\nloc_118E:\nmov eax, 1\nretn\nloc_1194:\nmov eax, 0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2, int a3)\n{\n _DWORD *v3; // rax\n\n if ( a2 <= 0 )\n return 1LL;\n v3 = a1;\n while ( *v3 == a3 )\n {\n if ( ++v3 == &a1[a2] )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2, int a3) {\n uint32_t *v3;\n if (a2 <= 0) return 1LL;\n v3 = a1;\n while (*v3 == a3) {\n if (++v3 == &a1[a2]) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2, int a3) {\n uint32_t *v3;\n if (a2 <= 0) return 1LL;\n v3 = a1;\n while (*v3 == a3) {\n if (++v3 == &a1[a2]) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 465, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char *key;\n\n char *value;\n\n} Entry;\n\n\n\ntypedef struct {\n\n Entry *entries;\n\n int size;\n\n} Dictionary;\n\n\n\nDictionary drop_empty(Dictionary dict1) {\n\n Dictionary result;\n\n result.entries = (Entry *)malloc(sizeof(Entry) * dict1.size);\n\n result.size = 0;\n\n\n\n for (int i = 0; i < dict1.size; i++) {\n\n if (dict1.entries[i].value != NULL) {\n\n result.entries[result.size].key = dict1.entries[i].key;\n\n result.entries[result.size].value = dict1.entries[i].value;\n\n result.size++;\n\n }\n\n }\n\n\n\n return result;\n\n}\n\n\n\n", + "func": "int func0(Dictionary dict1, Dictionary dict2) {\n if (dict1.size != dict2.size) return 0;\n for (int i = 0; i < dict1.size; i++) {\n int found = 0;\n for (int j = 0; j < dict2.size; j++) {\n if (dict1.entries[i].key == dict2.entries[j].key &&\n dict1.entries[i].value == dict2.entries[j].value) {\n found = 1;\n break;\n }\n }\n if (!found) return 0;\n }\n return 1;\n}", + "test": "int main() {\n\n Dictionary dict1, result, expected;\n\n\n\n dict1.size = 3;\n\n dict1.entries = (Entry[]){{\"c1\", \"Red\"}, {\"c2\", \"Green\"}, {\"c3\", NULL}};\n\n expected.size = 2;\n\n expected.entries = (Entry[]){{\"c1\", \"Red\"}, {\"c2\", \"Green\"}};\n\n result = drop_empty(dict1);\n\n assert(func0(result, expected));\n\n\n\n dict1.size = 3;\n\n dict1.entries = (Entry[]){{\"c1\", \"Red\"}, {\"c2\", NULL}, {\"c3\", NULL}};\n\n expected.size = 1;\n\n expected.entries = (Entry[]){{\"c1\", \"Red\"}};\n\n result = drop_empty(dict1);\n\n assert(func0(result, expected));\n\n\n\n dict1.size = 3;\n\n dict1.entries = (Entry[]){{\"c1\", NULL}, {\"c2\", \"Green\"}, {\"c3\", NULL}};\n\n expected.size = 1;\n\n expected.entries = (Entry[]){{\"c2\", \"Green\"}};\n\n result = drop_empty(dict1);\n\n assert(func0(result, expected));\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rsi,%rax\nmov %rdi,%r8\nmov %r8,%rsi\nmov %r9,%rdi\nmov %rax,%rdi\nmov %rsi,-0x20(%rbp)\nmov %rdi,-0x18(%rbp)\nmov %rdx,-0x30(%rbp)\nmov %rcx,-0x28(%rbp)\nmov -0x18(%rbp),%edx\nmov -0x28(%rbp),%eax\ncmp %eax,%edx\nje 1295 \nmov $0x0,%eax\njmpq 1344 \nmovl $0x0,-0xc(%rbp)\njmpq 1333 \nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 131a \nmov -0x20(%rbp),%rax\nmov -0xc(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x4,%rdx\nadd %rdx,%rax\nmov (%rax),%rdx\nmov -0x30(%rbp),%rax\nmov -0x4(%rbp),%ecx\nmovslq %ecx,%rcx\nshl $0x4,%rcx\nadd %rcx,%rax\nmov (%rax),%rax\ncmp %rax,%rdx\njne 1316 \nmov -0x20(%rbp),%rax\nmov -0xc(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x4,%rdx\nadd %rdx,%rax\nmov 0x8(%rax),%rdx\nmov -0x30(%rbp),%rax\nmov -0x4(%rbp),%ecx\nmovslq %ecx,%rcx\nshl $0x4,%rcx\nadd %rcx,%rax\nmov 0x8(%rax),%rax\ncmp %rax,%rdx\njne 1316 \nmovl $0x1,-0x8(%rbp)\njmp 1322 \naddl $0x1,-0x4(%rbp)\nmov -0x28(%rbp),%eax\ncmp %eax,-0x4(%rbp)\njl 12b1 \ncmpl $0x0,-0x8(%rbp)\njne 132f \nmov $0x0,%eax\njmp 1344 \naddl $0x1,-0xc(%rbp)\nmov -0x18(%rbp),%eax\ncmp %eax,-0xc(%rbp)\njl 12a1 \nmov $0x1,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov rax, rdi\nmov r8, rsi\nmov rsi, rax\nmov rdi, rdx\nmov rdi, r8\nmov [rbp+var_20], rsi\nmov [rbp+var_18], rdi\nmov [rbp+var_30], rdx\nmov [rbp+var_28], rcx\nmov edx, dword ptr [rbp+var_18]\nmov eax, dword ptr [rbp+var_28]\ncmp edx, eax\njz short loc_1295\nmov eax, 0\njmp loc_1344\nloc_1295:\nmov [rbp+var_C], 0\njmp loc_1333\nloc_12A1:\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_131A\nloc_12B1:\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nshl rdx, 4\nadd rax, rdx\nmov rdx, [rax]\nmov rax, [rbp+var_30]\nmov ecx, [rbp+var_4]\nmovsxd rcx, ecx\nshl rcx, 4\nadd rax, rcx\nmov rax, [rax]\ncmp rdx, rax\njnz short loc_1316\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nshl rdx, 4\nadd rax, rdx\nmov rdx, [rax+8]\nmov rax, [rbp+var_30]\nmov ecx, [rbp+var_4]\nmovsxd rcx, ecx\nshl rcx, 4\nadd rax, rcx\nmov rax, [rax+8]\ncmp rdx, rax\njnz short loc_1316\nmov [rbp+var_8], 1\njmp short loc_1322\nloc_1316:\nadd [rbp+var_4], 1\nloc_131A:\nmov eax, dword ptr [rbp+var_28]\ncmp [rbp+var_4], eax\njl short loc_12B1\nloc_1322:\ncmp [rbp+var_8], 0\njnz short loc_132F\nmov eax, 0\njmp short loc_1344\nloc_132F:\nadd [rbp+var_C], 1\nloc_1333:\nmov eax, dword ptr [rbp+var_18]\ncmp [rbp+var_C], eax\njl loc_12A1\nmov eax, 1\nloc_1344:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3, int a4)\n{\n int i; // [rsp+24h] [rbp-Ch]\n int v6; // [rsp+28h] [rbp-8h]\n int j; // [rsp+2Ch] [rbp-4h]\n\n if ( a2 != a4 )\n return 0LL;\n for ( i = 0; i < a2; ++i )\n {\n v6 = 0;\n for ( j = 0; j < a4; ++j )\n {\n if ( *(_QWORD *)(16LL * i + a1) == *(_QWORD *)(16LL * j + a3)\n && *(_QWORD *)(16LL * i + a1 + 8) == *(_QWORD *)(16LL * j + a3 + 8) )\n {\n v6 = 1;\n break;\n }\n }\n if ( !v6 )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_125A:\nendbr64\npush rbp\nmov rbp, rsp\nmov rax, rdi\nmov r8, rsi\nmov rsi, rax\nmov rdi, rdx\nmov rdi, r8\nmov [rbp+var_20], rsi\nmov [rbp+var_18], rdi\nmov [rbp+var_30], rdx\nmov [rbp+var_28], rcx\nmov edx, dword ptr [rbp+var_18]\nmov eax, dword ptr [rbp+var_28]\ncmp edx, eax\njz short loc_1295\nmov eax, 0\njmp loc_1344\nloc_1295:\nmov [rbp+var_C], 0\njmp loc_1333\nloc_12A1:\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_131A\nloc_12B1:\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nshl rdx, 4\nadd rax, rdx\nmov rdx, [rax]\nmov rax, [rbp+var_30]\nmov ecx, [rbp+var_4]\nmovsxd rcx, ecx\nshl rcx, 4\nadd rax, rcx\nmov rax, [rax]\ncmp rdx, rax\njnz short loc_1316\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nshl rdx, 4\nadd rax, rdx\nmov rdx, [rax+8]\nmov rax, [rbp+var_30]\nmov ecx, [rbp+var_4]\nmovsxd rcx, ecx\nshl rcx, 4\nadd rax, rcx\nmov rax, [rax+8]\ncmp rdx, rax\njnz short loc_1316\nmov [rbp+var_8], 1\njmp short loc_1322\nloc_1316:\nadd [rbp+var_4], 1\nloc_131A:\nmov eax, dword ptr [rbp+var_28]\ncmp [rbp+var_4], eax\njl short loc_12B1\nloc_1322:\ncmp [rbp+var_8], 0\njnz short loc_132F\nmov eax, 0\njmp short loc_1344\nloc_132F:\nadd [rbp+var_C], 1\nloc_1333:\nmov eax, dword ptr [rbp+var_18]\ncmp [rbp+var_C], eax\njl loc_12A1\nmov eax, 1\nloc_1344:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_125A(__int64 a1, int a2, __int64 a3, int a4)\n{\n int i; // [rsp+24h] [rbp-Ch]\n int v6; // [rsp+28h] [rbp-8h]\n int j; // [rsp+2Ch] [rbp-4h]\n\n if ( a2 != a4 )\n return 0LL;\n for ( i = 0; i < a2; ++i )\n {\n v6 = 0;\n for ( j = 0; j < a4; ++j )\n {\n if ( *(_QWORD *)(16LL * i + a1) == *(_QWORD *)(16LL * j + a3)\n && *(_QWORD *)(16LL * i + a1 + 8) == *(_QWORD *)(16LL * j + a3 + 8) )\n {\n v6 = 1;\n break;\n }\n }\n if ( !v6 )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_125A(long long a1, int a2, long long a3, int a4) {\n int i;\n int v6;\n int j;\n if (a2 != a4) return 0LL;\n for (i = 0; i < a2; ++i) {\n v6 = 0;\n for (j = 0; j < a4; ++j) {\n if (*(uint64_t *)(16LL * i + a1) == *(uint64_t *)(16LL * j + a3) &&\n *(uint64_t *)(16LL * i + a1 + 8) ==\n *(uint64_t *)(16LL * j + a3 + 8)) {\n v6 = 1;\n break;\n }\n }\n if (!v6) return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3, int a4) {\n int i;\n int v6;\n int j;\n if (a2 != a4) return 0LL;\n for (i = 0; i < a2; ++i) {\n v6 = 0;\n for (j = 0; j < a4; ++j) {\n if (*(uint64_t *)(16LL * i + a1) == *(uint64_t *)(16LL * j + a3) &&\n *(uint64_t *)(16LL * i + a1 + 8) ==\n *(uint64_t *)(16LL * j + a3 + 8)) {\n v6 = 1;\n break;\n }\n }\n if (!v6) return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": 465, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char *key;\n\n char *value;\n\n} Entry;\n\n\n\ntypedef struct {\n\n Entry *entries;\n\n int size;\n\n} Dictionary;\n\n\n\nDictionary drop_empty(Dictionary dict1) {\n\n Dictionary result;\n\n result.entries = (Entry *)malloc(sizeof(Entry) * dict1.size);\n\n result.size = 0;\n\n\n\n for (int i = 0; i < dict1.size; i++) {\n\n if (dict1.entries[i].value != NULL) {\n\n result.entries[result.size].key = dict1.entries[i].key;\n\n result.entries[result.size].value = dict1.entries[i].value;\n\n result.size++;\n\n }\n\n }\n\n\n\n return result;\n\n}\n\n\n\n", + "func": "int func0(Dictionary dict1, Dictionary dict2) {\n if (dict1.size != dict2.size) return 0;\n for (int i = 0; i < dict1.size; i++) {\n int found = 0;\n for (int j = 0; j < dict2.size; j++) {\n if (dict1.entries[i].key == dict2.entries[j].key &&\n dict1.entries[i].value == dict2.entries[j].value) {\n found = 1;\n break;\n }\n }\n if (!found) return 0;\n }\n return 1;\n}", + "test": "int main() {\n\n Dictionary dict1, result, expected;\n\n\n\n dict1.size = 3;\n\n dict1.entries = (Entry[]){{\"c1\", \"Red\"}, {\"c2\", \"Green\"}, {\"c3\", NULL}};\n\n expected.size = 2;\n\n expected.entries = (Entry[]){{\"c1\", \"Red\"}, {\"c2\", \"Green\"}};\n\n result = drop_empty(dict1);\n\n assert(func0(result, expected));\n\n\n\n dict1.size = 3;\n\n dict1.entries = (Entry[]){{\"c1\", \"Red\"}, {\"c2\", NULL}, {\"c3\", NULL}};\n\n expected.size = 1;\n\n expected.entries = (Entry[]){{\"c1\", \"Red\"}};\n\n result = drop_empty(dict1);\n\n assert(func0(result, expected));\n\n\n\n dict1.size = 3;\n\n dict1.entries = (Entry[]){{\"c1\", NULL}, {\"c2\", \"Green\"}, {\"c3\", NULL}};\n\n expected.size = 1;\n\n expected.entries = (Entry[]){{\"c2\", \"Green\"}};\n\n result = drop_empty(dict1);\n\n assert(func0(result, expected));\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %ecx,%r9d\nmov $0x0,%eax\ncmp %ecx,%esi\njne 1274 \ntest %esi,%esi\njle 122c \nmov %rdi,%r8\nlea -0x1(%rsi),%eax\nshl $0x4,%rax\nlea 0x10(%rdi,%rax,1),%r10\nmov %rdx,%rdi\nlea -0x1(%rcx),%eax\nshl $0x4,%rax\nlea 0x10(%rax,%rdx,1),%rcx\njmp 1253 \nmov $0x1,%eax\nretq\nadd $0x10,%rax\ncmp %rcx,%rax\nje 1263 \ncmp (%rax),%rdx\njne 1232 \nmov 0x8(%rax),%r11\ncmp %r11,0x8(%rsi)\njne 1232 \nadd $0x10,%r8\ncmp %r10,%r8\nje 126f \ntest %r9d,%r9d\njle 1269 \nmov %r8,%rsi\nmov (%r8),%rdx\nmov %rdi,%rax\njmp 123b \nmov $0x0,%eax\nretq\nmov $0x0,%eax\nretq\nmov $0x1,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov r10, rdx\nmov r8d, ecx\nmov eax, 0\ncmp esi, ecx\njnz short locret_125E\ntest esi, esi\njle short loc_1253\nmov r9, rdi\nmovsxd rsi, esi\nshl rsi, 4\nadd rdi, rsi\njmp short loc_123D\nloc_1219:\nadd edx, 1\nadd rax, 10h\ncmp r8d, edx\njle short loc_124D\nloc_1225:\ncmp rcx, [rax]\njnz short loc_1219\nmov r11, [rax+8]\ncmp [rsi+8], r11\njnz short loc_1219\nadd r9, 10h\ncmp r9, rdi\njz short loc_1259\nloc_123D:\nmov rsi, r9\nmov rcx, [r9]\nmov rax, r10\nmov edx, 0\njmp short loc_1225\nloc_124D:\nmov eax, 0\nretn\nloc_1253:\nmov eax, 1\nretn\nloc_1259:\nmov eax, 1\nlocret_125E:\nretn", + "ida_pseudo": "__int64 __fastcall func0(_QWORD *a1, int a2, _QWORD *a3, int a4)\n{\n __int64 result; // rax\n _QWORD *v6; // r9\n _QWORD *v7; // rdi\n int v8; // edx\n _QWORD *v9; // rax\n\n result = 0LL;\n if ( a2 == a4 )\n {\n if ( a2 <= 0 )\n {\n return 1LL;\n }\n else\n {\n v6 = a1;\n v7 = &a1[2 * a2];\n while ( 2 )\n {\n v9 = a3;\n v8 = 0;\n while ( *v6 != *v9 || v6[1] != v9[1] )\n {\n ++v8;\n v9 += 2;\n if ( a4 <= v8 )\n return 0LL;\n }\n v6 += 2;\n if ( v6 != v7 )\n continue;\n break;\n }\n return 1LL;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_11F3:\nendbr64\nmov r10, rdx\nmov r8d, ecx\nmov eax, 0\ncmp esi, ecx\njnz short locret_125E\ntest esi, esi\njle short loc_1253\nmov r9, rdi\nmovsxd rsi, esi\nshl rsi, 4\nadd rdi, rsi\njmp short loc_123D\nloc_1219:\nadd edx, 1\nadd rax, 10h\ncmp r8d, edx\njle short loc_124D\nloc_1225:\ncmp rcx, [rax]\njnz short loc_1219\nmov r11, [rax+8]\ncmp [rsi+8], r11\njnz short loc_1219\nadd r9, 10h\ncmp r9, rdi\njz short loc_1259\nloc_123D:\nmov rsi, r9\nmov rcx, [r9]\nmov rax, r10\nmov edx, 0\njmp short loc_1225\nloc_124D:\nmov eax, 0\nretn\nloc_1253:\nmov eax, 1\nretn\nloc_1259:\nmov eax, 1\nlocret_125E:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11F3(_QWORD *a1, int a2, _QWORD *a3, int a4)\n{\n __int64 result; // rax\n _QWORD *v6; // r9\n _QWORD *v7; // rdi\n int v8; // edx\n _QWORD *v9; // rax\n\n result = 0LL;\n if ( a2 == a4 )\n {\n if ( a2 <= 0 )\n {\n return 1LL;\n }\n else\n {\n v6 = a1;\n v7 = &a1[2 * a2];\n while ( 2 )\n {\n v9 = a3;\n v8 = 0;\n while ( *v6 != *v9 || v6[1] != v9[1] )\n {\n ++v8;\n v9 += 2;\n if ( a4 <= v8 )\n return 0LL;\n }\n v6 += 2;\n if ( v6 != v7 )\n continue;\n break;\n }\n return 1LL;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11F3(uint64_t *a1, int a2, uint64_t *a3, int a4) {\n long long result;\n uint64_t *v6;\n uint64_t *v7;\n int v8;\n uint64_t *v9;\n result = 0LL;\n if (a2 == a4) {\n if (a2 <= 0) {\n return 1LL;\n } else {\n v6 = a1;\n v7 = &a1[2 * a2];\n while (2) {\n v9 = a3;\n v8 = 0;\n while (*v6 != *v9 || v6[1] != v9[1]) {\n ++v8;\n v9 += 2;\n if (a4 <= v8) return 0LL;\n }\n v6 += 2;\n if (v6 != v7) continue;\n break;\n }\n return 1LL;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(uint64_t *a1, int a2, uint64_t *a3, int a4) {\n long long result;\n uint64_t *v6;\n uint64_t *v7;\n int v8;\n uint64_t *v9;\n result = 0LL;\n if (a2 == a4) {\n if (a2 <= 0) {\n return 1LL;\n } else {\n v6 = a1;\n v7 = &a1[2 * a2];\n while (2) {\n v9 = a3;\n v8 = 0;\n while (*v6 != *v9 || v6[1] != v9[1]) {\n ++v8;\n v9 += 2;\n if (a4 <= v8) return 0LL;\n }\n v6 += 2;\n if (v6 != v7) continue;\n break;\n }\n return 1LL;\n }\n }\n return result;\n}" + }, + { + "index": 465, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char *key;\n\n char *value;\n\n} Entry;\n\n\n\ntypedef struct {\n\n Entry *entries;\n\n int size;\n\n} Dictionary;\n\n\n\nDictionary drop_empty(Dictionary dict1) {\n\n Dictionary result;\n\n result.entries = (Entry *)malloc(sizeof(Entry) * dict1.size);\n\n result.size = 0;\n\n\n\n for (int i = 0; i < dict1.size; i++) {\n\n if (dict1.entries[i].value != NULL) {\n\n result.entries[result.size].key = dict1.entries[i].key;\n\n result.entries[result.size].value = dict1.entries[i].value;\n\n result.size++;\n\n }\n\n }\n\n\n\n return result;\n\n}\n\n\n\n", + "func": "int func0(Dictionary dict1, Dictionary dict2) {\n if (dict1.size != dict2.size) return 0;\n for (int i = 0; i < dict1.size; i++) {\n int found = 0;\n for (int j = 0; j < dict2.size; j++) {\n if (dict1.entries[i].key == dict2.entries[j].key &&\n dict1.entries[i].value == dict2.entries[j].value) {\n found = 1;\n break;\n }\n }\n if (!found) return 0;\n }\n return 1;\n}", + "test": "int main() {\n\n Dictionary dict1, result, expected;\n\n\n\n dict1.size = 3;\n\n dict1.entries = (Entry[]){{\"c1\", \"Red\"}, {\"c2\", \"Green\"}, {\"c3\", NULL}};\n\n expected.size = 2;\n\n expected.entries = (Entry[]){{\"c1\", \"Red\"}, {\"c2\", \"Green\"}};\n\n result = drop_empty(dict1);\n\n assert(func0(result, expected));\n\n\n\n dict1.size = 3;\n\n dict1.entries = (Entry[]){{\"c1\", \"Red\"}, {\"c2\", NULL}, {\"c3\", NULL}};\n\n expected.size = 1;\n\n expected.entries = (Entry[]){{\"c1\", \"Red\"}};\n\n result = drop_empty(dict1);\n\n assert(func0(result, expected));\n\n\n\n dict1.size = 3;\n\n dict1.entries = (Entry[]){{\"c1\", NULL}, {\"c2\", \"Green\"}, {\"c3\", NULL}};\n\n expected.size = 1;\n\n expected.entries = (Entry[]){{\"c2\", \"Green\"}};\n\n result = drop_empty(dict1);\n\n assert(func0(result, expected));\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov %ecx,%r8d\nxor %eax,%eax\ncmp %ecx,%esi\njne 149e \ntest %ecx,%ecx\njle 1499 \nlea -0x1(%rcx),%eax\nshl $0x4,%rax\nlea 0x10(%rdi,%rax,1),%r9\nlea 0x10(%rax,%rdx,1),%rsi\nnopw 0x0(%rax,%rax,1)\ntest %r8d,%r8d\njle 14a0 \nmov (%rdi),%rcx\nmov %rdx,%rax\njmp 1481 \nnopl (%rax)\nadd $0x10,%rax\ncmp %rsi,%rax\nje 14a0 \ncmp (%rax),%rcx\njne 1478 \nmov 0x8(%rax),%r10\ncmp %r10,0x8(%rdi)\njne 1478 \nadd $0x10,%rdi\ncmp %r9,%rdi\njne 1468 \nmov $0x1,%eax\nretq\nxor %eax,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\nmov r8d, ecx\nxor eax, eax\ncmp esi, ecx\njnz short locret_14A9\ntest ecx, ecx\njle short loc_14A4\nmovsxd rcx, ecx\nshl rcx, 4\nlea r9, [rcx+rdi]\nnop dword ptr [rax+00h]\nloc_1470:\nmov rsi, [rdi]\nmov rax, rdx\nxor ecx, ecx\njmp short loc_148C\nloc_1480:\nadd ecx, 1\nadd rax, 10h\ncmp r8d, ecx\njle short loc_14B0\nloc_148C:\ncmp rsi, [rax]\njnz short loc_1480\nmov r10, [rax+8]\ncmp [rdi+8], r10\njnz short loc_1480\nadd rdi, 10h\ncmp rdi, r9\njnz short loc_1470\nloc_14A4:\nmov eax, 1\nlocret_14A9:\nretn\nloc_14B0:\nxor eax, eax\nretn", + "ida_pseudo": "__int64 __fastcall func0(_QWORD *a1, int a2, _QWORD *a3, int a4)\n{\n __int64 result; // rax\n _QWORD *v6; // r9\n _QWORD *v7; // rax\n int v8; // ecx\n\n result = 0LL;\n if ( a2 == a4 )\n {\n if ( a4 > 0 )\n {\n v6 = &a1[2 * a4];\n while ( 2 )\n {\n v7 = a3;\n v8 = 0;\n while ( *a1 != *v7 || a1[1] != v7[1] )\n {\n ++v8;\n v7 += 2;\n if ( a4 <= v8 )\n return 0LL;\n }\n a1 += 2;\n if ( a1 != v6 )\n continue;\n break;\n }\n }\n return 1LL;\n }\n return result;\n}", + "ida_strip_asm": "sub_1450:\nendbr64\nmov r8d, ecx\nxor eax, eax\ncmp esi, ecx\njnz short locret_14A9\ntest ecx, ecx\njle short loc_14A4\nmovsxd rcx, ecx\nshl rcx, 4\nlea r9, [rcx+rdi]\nnop dword ptr [rax+00h]\nloc_1470:\nmov rsi, [rdi]\nmov rax, rdx\nxor ecx, ecx\njmp short loc_148C\nloc_1480:\nadd ecx, 1\nadd rax, 10h\ncmp r8d, ecx\njle short loc_14B0\nloc_148C:\ncmp rsi, [rax]\njnz short loc_1480\nmov r10, [rax+8]\ncmp [rdi+8], r10\njnz short loc_1480\nadd rdi, 10h\ncmp rdi, r9\njnz short loc_1470\nloc_14A4:\nmov eax, 1\nlocret_14A9:\nretn\nloc_14B0:\nxor eax, eax\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1450(_QWORD *a1, int a2, _QWORD *a3, int a4)\n{\n __int64 result; // rax\n _QWORD *v6; // r9\n _QWORD *v7; // rax\n int v8; // ecx\n\n result = 0LL;\n if ( a2 == a4 )\n {\n if ( a4 > 0 )\n {\n v6 = &a1[2 * a4];\n while ( 2 )\n {\n v7 = a3;\n v8 = 0;\n while ( *a1 != *v7 || a1[1] != v7[1] )\n {\n ++v8;\n v7 += 2;\n if ( a4 <= v8 )\n return 0LL;\n }\n a1 += 2;\n if ( a1 != v6 )\n continue;\n break;\n }\n }\n return 1LL;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1450(uint64_t *a1, int a2, uint64_t *a3, int a4) {\n long long result;\n uint64_t *v6;\n uint64_t *v7;\n int v8;\n result = 0LL;\n if (a2 == a4) {\n if (a4 > 0) {\n v6 = &a1[2 * a4];\n while (2) {\n v7 = a3;\n v8 = 0;\n while (*a1 != *v7 || a1[1] != v7[1]) {\n ++v8;\n v7 += 2;\n if (a4 <= v8) return 0LL;\n }\n a1 += 2;\n if (a1 != v6) continue;\n break;\n }\n }\n return 1LL;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(uint64_t *a1, int a2, uint64_t *a3, int a4) {\n long long result;\n uint64_t *v6;\n uint64_t *v7;\n int v8;\n result = 0LL;\n if (a2 == a4) {\n if (a4 > 0) {\n v6 = &a1[2 * a4];\n while (2) {\n v7 = a3;\n v8 = 0;\n while (*a1 != *v7 || a1[1] != v7[1]) {\n ++v8;\n v7 += 2;\n if (a4 <= v8) return 0LL;\n }\n a1 += 2;\n if (a1 != v6) continue;\n break;\n }\n }\n return 1LL;\n }\n return result;\n}" + }, + { + "index": 465, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char *key;\n\n char *value;\n\n} Entry;\n\n\n\ntypedef struct {\n\n Entry *entries;\n\n int size;\n\n} Dictionary;\n\n\n\nDictionary drop_empty(Dictionary dict1) {\n\n Dictionary result;\n\n result.entries = (Entry *)malloc(sizeof(Entry) * dict1.size);\n\n result.size = 0;\n\n\n\n for (int i = 0; i < dict1.size; i++) {\n\n if (dict1.entries[i].value != NULL) {\n\n result.entries[result.size].key = dict1.entries[i].key;\n\n result.entries[result.size].value = dict1.entries[i].value;\n\n result.size++;\n\n }\n\n }\n\n\n\n return result;\n\n}\n\n\n\n", + "func": "int func0(Dictionary dict1, Dictionary dict2) {\n if (dict1.size != dict2.size) return 0;\n for (int i = 0; i < dict1.size; i++) {\n int found = 0;\n for (int j = 0; j < dict2.size; j++) {\n if (dict1.entries[i].key == dict2.entries[j].key &&\n dict1.entries[i].value == dict2.entries[j].value) {\n found = 1;\n break;\n }\n }\n if (!found) return 0;\n }\n return 1;\n}", + "test": "int main() {\n\n Dictionary dict1, result, expected;\n\n\n\n dict1.size = 3;\n\n dict1.entries = (Entry[]){{\"c1\", \"Red\"}, {\"c2\", \"Green\"}, {\"c3\", NULL}};\n\n expected.size = 2;\n\n expected.entries = (Entry[]){{\"c1\", \"Red\"}, {\"c2\", \"Green\"}};\n\n result = drop_empty(dict1);\n\n assert(func0(result, expected));\n\n\n\n dict1.size = 3;\n\n dict1.entries = (Entry[]){{\"c1\", \"Red\"}, {\"c2\", NULL}, {\"c3\", NULL}};\n\n expected.size = 1;\n\n expected.entries = (Entry[]){{\"c1\", \"Red\"}};\n\n result = drop_empty(dict1);\n\n assert(func0(result, expected));\n\n\n\n dict1.size = 3;\n\n dict1.entries = (Entry[]){{\"c1\", NULL}, {\"c2\", \"Green\"}, {\"c3\", NULL}};\n\n expected.size = 1;\n\n expected.entries = (Entry[]){{\"c2\", \"Green\"}};\n\n result = drop_empty(dict1);\n\n assert(func0(result, expected));\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nmov %ecx,%r8d\nxor %eax,%eax\ncmp %ecx,%esi\njne 14ae \ntest %ecx,%ecx\njle 14a9 \nlea -0x1(%rcx),%eax\nshl $0x4,%rax\nlea 0x10(%rdi,%rax,1),%r9\nlea 0x10(%rax,%rdx,1),%rsi\nnopw 0x0(%rax,%rax,1)\ntest %r8d,%r8d\njle 14b0 \nmov (%rdi),%rcx\nmov %rdx,%rax\njmp 1491 \nnopl (%rax)\nadd $0x10,%rax\ncmp %rsi,%rax\nje 14b0 \ncmp (%rax),%rcx\njne 1488 \nmov 0x8(%rax),%r10\ncmp %r10,0x8(%rdi)\njne 1488 \nadd $0x10,%rdi\ncmp %r9,%rdi\njne 1478 \nmov $0x1,%eax\nretq\nxor %eax,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\nmov r8d, ecx\nxor eax, eax\ncmp esi, ecx\njnz short locret_14A9\ntest ecx, ecx\njle short loc_14A4\nmovsxd rcx, ecx\nshl rcx, 4\nlea r9, [rcx+rdi]\nnop dword ptr [rax+00h]\nloc_1470:\nmov rsi, [rdi]\nmov rax, rdx\nxor ecx, ecx\njmp short loc_148C\nloc_1480:\nadd ecx, 1\nadd rax, 10h\ncmp r8d, ecx\njle short loc_14B0\nloc_148C:\ncmp rsi, [rax]\njnz short loc_1480\nmov r10, [rax+8]\ncmp [rdi+8], r10\njnz short loc_1480\nadd rdi, 10h\ncmp rdi, r9\njnz short loc_1470\nloc_14A4:\nmov eax, 1\nlocret_14A9:\nretn\nloc_14B0:\nxor eax, eax\nretn", + "ida_pseudo": "__int64 __fastcall func0(_QWORD *a1, int a2, _QWORD *a3, int a4)\n{\n __int64 result; // rax\n _QWORD *v6; // r9\n _QWORD *v7; // rax\n int v8; // ecx\n\n result = 0LL;\n if ( a2 == a4 )\n {\n if ( a4 > 0 )\n {\n v6 = &a1[2 * a4];\n while ( 2 )\n {\n v7 = a3;\n v8 = 0;\n while ( *a1 != *v7 || a1[1] != v7[1] )\n {\n ++v8;\n v7 += 2;\n if ( a4 <= v8 )\n return 0LL;\n }\n a1 += 2;\n if ( a1 != v6 )\n continue;\n break;\n }\n }\n return 1LL;\n }\n return result;\n}", + "ida_strip_asm": "sub_1450:\nendbr64\nmov r8d, ecx\nxor eax, eax\ncmp esi, ecx\njnz short locret_14A9\ntest ecx, ecx\njle short loc_14A4\nmovsxd rcx, ecx\nshl rcx, 4\nlea r9, [rcx+rdi]\nnop dword ptr [rax+00h]\nloc_1470:\nmov rsi, [rdi]\nmov rax, rdx\nxor ecx, ecx\njmp short loc_148C\nloc_1480:\nadd ecx, 1\nadd rax, 10h\ncmp r8d, ecx\njle short loc_14B0\nloc_148C:\ncmp rsi, [rax]\njnz short loc_1480\nmov r10, [rax+8]\ncmp [rdi+8], r10\njnz short loc_1480\nadd rdi, 10h\ncmp rdi, r9\njnz short loc_1470\nloc_14A4:\nmov eax, 1\nlocret_14A9:\nretn\nloc_14B0:\nxor eax, eax\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1450(_QWORD *a1, int a2, _QWORD *a3, int a4)\n{\n __int64 result; // rax\n _QWORD *v6; // r9\n _QWORD *v7; // rax\n int v8; // ecx\n\n result = 0LL;\n if ( a2 == a4 )\n {\n if ( a4 > 0 )\n {\n v6 = &a1[2 * a4];\n while ( 2 )\n {\n v7 = a3;\n v8 = 0;\n while ( *a1 != *v7 || a1[1] != v7[1] )\n {\n ++v8;\n v7 += 2;\n if ( a4 <= v8 )\n return 0LL;\n }\n a1 += 2;\n if ( a1 != v6 )\n continue;\n break;\n }\n }\n return 1LL;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1450(uint64_t *a1, int a2, uint64_t *a3, int a4) {\n long long result;\n uint64_t *v6;\n uint64_t *v7;\n int v8;\n result = 0LL;\n if (a2 == a4) {\n if (a4 > 0) {\n v6 = &a1[2 * a4];\n while (2) {\n v7 = a3;\n v8 = 0;\n while (*a1 != *v7 || a1[1] != v7[1]) {\n ++v8;\n v7 += 2;\n if (a4 <= v8) return 0LL;\n }\n a1 += 2;\n if (a1 != v6) continue;\n break;\n }\n }\n return 1LL;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(uint64_t *a1, int a2, uint64_t *a3, int a4) {\n long long result;\n uint64_t *v6;\n uint64_t *v7;\n int v8;\n result = 0LL;\n if (a2 == a4) {\n if (a4 > 0) {\n v6 = &a1[2 * a4];\n while (2) {\n v7 = a3;\n v8 = 0;\n while (*a1 != *v7 || a1[1] != v7[1]) {\n ++v8;\n v7 += 2;\n if (a4 <= v8) return 0LL;\n }\n a1 += 2;\n if (a1 != v6) continue;\n break;\n }\n }\n return 1LL;\n }\n return result;\n}" + }, + { + "index": 466, + "func_name": "func0", + "func_dep": "#include \n\n\n\nint find_peak_util(int arr[], int low, int high, int n) {\n\n int mid = low + (high - low) / 2;\n\n if ((mid == 0 || arr[mid - 1] <= arr[mid]) &&\n\n (mid == n - 1 || arr[mid + 1] <= arr[mid])) {\n\n return mid;\n\n } else if (mid > 0 && arr[mid - 1] > arr[mid]) {\n\n return find_peak_util(arr, low, mid - 1, n);\n\n } else {\n\n return find_peak_util(arr, mid + 1, high, n);\n\n }\n\n}\n\n\n\n", + "func": "int func0(int arr[], int n) { return find_peak_util(arr, 0, n - 1, n); }", + "test": "int main() {\n\n int arr1[6] = {1, 3, 20, 4, 1, 0};\n\n int arr2[5] = {2, 3, 4, 5, 6};\n\n int arr3[6] = {8, 9, 11, 12, 14, 15};\n\n\n\n assert(func0(arr1, 6) == 2);\n\n assert(func0(arr2, 5) == 4);\n\n assert(func0(arr3, 6) == 5);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %rdi,-0x8(%rbp)\nmov %esi,-0xc(%rbp)\nmov -0xc(%rbp),%eax\nlea -0x1(%rax),%esi\nmov -0xc(%rbp),%edx\nmov -0x8(%rbp),%rax\nmov %edx,%ecx\nmov %esi,%edx\nmov $0x0,%esi\nmov %rax,%rdi\ncallq 1169 \nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+var_8], rdi\nmov [rbp+var_C], esi\nmov eax, [rbp+var_C]\nlea esi, [rax-1]\nmov edx, [rbp+var_C]\nmov rax, [rbp+var_8]\nmov ecx, edx\nmov edx, esi\nmov esi, 0\nmov rdi, rax\ncall find_peak_util\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, unsigned int a2)\n{\n return find_peak_util(a1, 0LL, a2 - 1, a2);\n}", + "ida_strip_asm": "sub_1283:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+var_8], rdi\nmov [rbp+var_C], esi\nmov eax, [rbp+var_C]\nlea esi, [rax-1]\nmov edx, [rbp+var_C]\nmov rax, [rbp+var_8]\nmov ecx, edx\nmov edx, esi\nmov esi, 0\nmov rdi, rax\ncall sub_1169\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1283(__int64 a1, unsigned int a2)\n{\n return sub_1169(a1, 0LL, a2 - 1, a2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1283(long long a1, unsigned int a2) {\n return sub_1169(a1, 0LL, a2 - 1, a2);\n}", + "ida_pseudo_norm": "long long func0(long long a1, unsigned int a2) {\n return find_peak_util(a1, 0LL, a2 - 1, a2);\n}" + }, + { + "index": 466, + "func_name": "func0", + "func_dep": "#include \n\n\n\nint find_peak_util(int arr[], int low, int high, int n) {\n\n int mid = low + (high - low) / 2;\n\n if ((mid == 0 || arr[mid - 1] <= arr[mid]) &&\n\n (mid == n - 1 || arr[mid + 1] <= arr[mid])) {\n\n return mid;\n\n } else if (mid > 0 && arr[mid - 1] > arr[mid]) {\n\n return find_peak_util(arr, low, mid - 1, n);\n\n } else {\n\n return find_peak_util(arr, mid + 1, high, n);\n\n }\n\n}\n\n\n\n", + "func": "int func0(int arr[], int n) { return find_peak_util(arr, 0, n - 1, n); }", + "test": "int main() {\n\n int arr1[6] = {1, 3, 20, 4, 1, 0};\n\n int arr2[5] = {2, 3, 4, 5, 6};\n\n int arr3[6] = {8, 9, 11, 12, 14, 15};\n\n\n\n assert(func0(arr1, 6) == 2);\n\n assert(func0(arr2, 5) == 4);\n\n assert(func0(arr3, 6) == 5);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x8,%rsp\nmov %esi,%ecx\nlea -0x1(%rsi),%edx\nmov $0x0,%esi\ncallq 1169 \nadd $0x8,%rsp\nretq\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\nmov ecx, esi\nlea edx, [rsi-1]\nmov esi, 0\ncall find_peak_util\nadd rsp, 8\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, unsigned int a2)\n{\n return find_peak_util(a1, 0LL, a2 - 1, a2);\n}", + "ida_strip_asm": "sub_11D1:\nendbr64\nsub rsp, 8\nmov ecx, esi\nlea edx, [rsi-1]\nmov esi, 0\ncall sub_1169\nadd rsp, 8\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11D1(__int64 a1, unsigned int a2)\n{\n return sub_1169(a1, 0LL, a2 - 1, a2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11D1(long long a1, unsigned int a2) {\n return sub_1169(a1, 0LL, a2 - 1, a2);\n}", + "ida_pseudo_norm": "long long func0(long long a1, unsigned int a2) {\n return find_peak_util(a1, 0LL, a2 - 1, a2);\n}" + }, + { + "index": 467, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int deciNum) {\n int octalNum = 0;\n int countval = 1;\n int remainder;\n while (deciNum != 0) {\n remainder = deciNum % 8;\n octalNum += remainder * countval;\n countval *= 10;\n deciNum /= 8;\n }\n return octalNum;\n}", + "test": "int main() {\n\n assert(func0(10) == 12);\n\n assert(func0(2) == 2);\n\n assert(func0(33) == 41);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x1,-0x8(%rbp)\njmp 119f \nmov -0x14(%rbp),%eax\ncltd\nshr $0x1d,%edx\nadd %edx,%eax\nand $0x7,%eax\nsub %edx,%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nimul -0x8(%rbp),%eax\nadd %eax,-0xc(%rbp)\nmov -0x8(%rbp),%edx\nmov %edx,%eax\nshl $0x2,%eax\nadd %edx,%eax\nadd %eax,%eax\nmov %eax,-0x8(%rbp)\nmov -0x14(%rbp),%eax\nlea 0x7(%rax),%edx\ntest %eax,%eax\ncmovs %edx,%eax\nsar $0x3,%eax\nmov %eax,-0x14(%rbp)\ncmpl $0x0,-0x14(%rbp)\njne 1164 \nmov -0xc(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 1\njmp short loc_11A3\nloc_1164:\nmov edx, [rbp+var_14]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Dh\nadd edx, eax\nand edx, 7\nsub edx, eax\nmov [rbp+var_4], edx\nmov eax, [rbp+var_4]\nimul eax, [rbp+var_8]\nadd [rbp+var_C], eax\nmov edx, [rbp+var_8]\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nmov [rbp+var_8], eax\nmov eax, [rbp+var_14]\nlea edx, [rax+7]\ntest eax, eax\ncmovs eax, edx\nsar eax, 3\nmov [rbp+var_14], eax\nloc_11A3:\ncmp [rbp+var_14], 0\njnz short loc_1164\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v3; // [rsp+8h] [rbp-Ch]\n int v4; // [rsp+Ch] [rbp-8h]\n\n v3 = 0;\n v4 = 1;\n while ( a1 )\n {\n v3 += v4 * (a1 % 8);\n v4 *= 10;\n a1 /= 8;\n }\n return v3;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 1\njmp short loc_11A3\nloc_1164:\nmov edx, [rbp+var_14]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Dh\nadd edx, eax\nand edx, 7\nsub edx, eax\nmov [rbp+var_4], edx\nmov eax, [rbp+var_4]\nimul eax, [rbp+var_8]\nadd [rbp+var_C], eax\nmov edx, [rbp+var_8]\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nmov [rbp+var_8], eax\nmov eax, [rbp+var_14]\nlea edx, [rax+7]\ntest eax, eax\ncmovs eax, edx\nsar eax, 3\nmov [rbp+var_14], eax\nloc_11A3:\ncmp [rbp+var_14], 0\njnz short loc_1164\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n unsigned int v3; // [rsp+8h] [rbp-Ch]\n int v4; // [rsp+Ch] [rbp-8h]\n\n v3 = 0;\n v4 = 1;\n while ( a1 )\n {\n v3 += v4 * (a1 % 8);\n v4 *= 10;\n a1 /= 8;\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n unsigned int v3;\n int v4;\n v3 = 0;\n v4 = 1;\n while (a1) {\n v3 += v4 * (a1 % 8);\n v4 *= 10;\n a1 /= 8;\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v3;\n int v4;\n v3 = 0;\n v4 = 1;\n while (a1) {\n v3 += v4 * (a1 % 8);\n v4 *= 10;\n a1 /= 8;\n }\n return v3;\n}" + }, + { + "index": 467, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int deciNum) {\n int octalNum = 0;\n int countval = 1;\n int remainder;\n while (deciNum != 0) {\n remainder = deciNum % 8;\n octalNum += remainder * countval;\n countval *= 10;\n deciNum /= 8;\n }\n return octalNum;\n}", + "test": "int main() {\n\n assert(func0(10) == 12);\n\n assert(func0(2) == 2);\n\n assert(func0(33) == 41);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %edi,%edx\ntest %edi,%edi\nje 118c \nmov $0x1,%ecx\nmov $0x0,%r8d\nmov %edx,%esi\nsar $0x1f,%esi\nshr $0x1d,%esi\nlea (%rdx,%rsi,1),%eax\nand $0x7,%eax\nsub %esi,%eax\nimul %ecx,%eax\nadd %eax,%r8d\nlea (%rcx,%rcx,4),%ecx\nadd %ecx,%ecx\nlea 0x7(%rdx),%edi\ntest %edx,%edx\ncmovns %edx,%edi\nsar $0x3,%edi\nmov %edi,%edx\njne 115e \nmov %r8d,%eax\nretq\nmov %edi,%r8d\njmp 1188 \n", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njz short loc_1187\nmov edx, 1\nmov esi, 0\nloc_115B:\nmov ecx, edi\nsar ecx, 1Fh\nshr ecx, 1Dh\nlea eax, [rdi+rcx]\nand eax, 7\nsub eax, ecx\nimul eax, edx\nadd esi, eax\nlea edx, [rdx+rdx*4]\nadd edx, edx\nlea eax, [rdi+7]\ntest edi, edi\ncmovns eax, edi\nsar eax, 3\nmov edi, eax\njnz short loc_115B\nloc_1184:\nmov eax, esi\nretn\nloc_1187:\nmov esi, edi\njmp short loc_1184", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // eax\n int v2; // edx\n unsigned int v3; // esi\n\n if ( a1 )\n {\n v2 = 1;\n v3 = 0;\n do\n {\n v3 += v2 * (a1 % 8);\n v2 *= 10;\n a1 /= 8;\n }\n while ( v1 >> 3 );\n }\n else\n {\n return 0;\n }\n return v3;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ntest edi, edi\njz short loc_1187\nmov edx, 1\nmov esi, 0\nloc_115B:\nmov ecx, edi\nsar ecx, 1Fh\nshr ecx, 1Dh\nlea eax, [rdi+rcx]\nand eax, 7\nsub eax, ecx\nimul eax, edx\nadd esi, eax\nlea edx, [rdx+rdx*4]\nadd edx, edx\nlea eax, [rdi+7]\ntest edi, edi\ncmovns eax, edi\nsar eax, 3\nmov edi, eax\njnz short loc_115B\nloc_1184:\nmov eax, esi\nretn\nloc_1187:\nmov esi, edi\njmp short loc_1184", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v1; // eax\n int v2; // edx\n unsigned int v3; // esi\n\n if ( a1 )\n {\n v2 = 1;\n v3 = 0;\n do\n {\n v3 += v2 * (a1 % 8);\n v2 *= 10;\n a1 /= 8;\n }\n while ( v1 >> 3 );\n }\n else\n {\n return 0;\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v1;\n int v2;\n unsigned int v3;\n if (a1) {\n v2 = 1;\n v3 = 0;\n do {\n v3 += v2 * (a1 % 8);\n v2 *= 10;\n a1 /= 8;\n } while (v1 >> 3);\n } else {\n return 0;\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v2;\n unsigned int v3;\n if (a1) {\n v2 = 1;\n v3 = 0;\n do {\n v3 += v2 * (a1 % 8);\n v2 *= 10;\n a1 /= 8;\n } while (v1 >> 3);\n } else {\n return 0;\n }\n return v3;\n}" + }, + { + "index": 468, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int mpis[n];\n for (int i = 0; i < n; i++) {\n mpis[i] = arr[i];\n }\n for (int i = 1; i < n; i++) {\n for (int j = 0; j < i; j++) {\n if (arr[i] > arr[j] && mpis[i] < (mpis[j] * arr[i])) {\n mpis[i] = mpis[j] * arr[i];\n }\n }\n }\n int maxVal = mpis[0];\n for (int i = 1; i < n; i++) {\n if (mpis[i] > maxVal) {\n maxVal = mpis[i];\n }\n }\n return maxVal;\n}", + "test": "int main() {\n\n int arr1[] = {3, 100, 4, 5, 150, 6};\n\n int arr2[] = {4, 42, 55, 68, 80};\n\n int arr3[] = {10, 22, 9, 33, 21, 50, 41, 60};\n\n\n\n assert(func0(arr1, 6) == 45000);\n\n assert(func0(arr2, 5) == 50265600);\n\n assert(func0(arr3, 8) == 21780000);\n\n\n\n printf(\"All tests passed!\\n\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x48,%rsp\nmov %rdi,-0x48(%rbp)\nmov %esi,-0x4c(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmov %rsp,%rax\nmov %rax,%rdi\nmov -0x4c(%rbp),%eax\nmovslq %eax,%rdx\nsub $0x1,%rdx\nmov %rdx,-0x28(%rbp)\nmovslq %eax,%rdx\nmov %rdx,%r8\nmov $0x0,%r9d\nmovslq %eax,%rdx\nmov %rdx,%rcx\nmov $0x0,%ebx\ncltq\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%ebx\nmov $0x0,%edx\ndiv %rbx\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rbx\nsub %rdx,%rbx\nmov %rbx,%rdx\ncmp %rdx,%rsp\nje 1228 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 1211 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 1252 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x20(%rbp)\nmovl $0x0,-0x30(%rbp)\njmp 1295 \nmov -0x30(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%ecx\nmov -0x20(%rbp),%rax\nmov -0x30(%rbp),%edx\nmovslq %edx,%rdx\nmov %ecx,(%rax,%rdx,4)\naddl $0x1,-0x30(%rbp)\nmov -0x30(%rbp),%eax\ncmp -0x4c(%rbp),%eax\njl 126e \nmovl $0x1,-0x34(%rbp)\njmpq 1365 \nmovl $0x0,-0x38(%rbp)\njmpq 1355 \nmov -0x34(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x38(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x48(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njle 1351 \nmov -0x20(%rbp),%rax\nmov -0x34(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%ecx\nmov -0x20(%rbp),%rax\nmov -0x38(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%edx\nmov -0x34(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rsi\nmov -0x48(%rbp),%rax\nadd %rsi,%rax\nmov (%rax),%eax\nimul %edx,%eax\ncmp %eax,%ecx\njge 1351 \nmov -0x20(%rbp),%rax\nmov -0x38(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%edx\nmov -0x34(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x48(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\nmov %edx,%ecx\nimul %eax,%ecx\nmov -0x20(%rbp),%rax\nmov -0x34(%rbp),%edx\nmovslq %edx,%rdx\nmov %ecx,(%rax,%rdx,4)\naddl $0x1,-0x38(%rbp)\nmov -0x38(%rbp),%eax\ncmp -0x34(%rbp),%eax\njl 12b5 \naddl $0x1,-0x34(%rbp)\nmov -0x34(%rbp),%eax\ncmp -0x4c(%rbp),%eax\njl 12a9 \nmov -0x20(%rbp),%rax\nmov (%rax),%eax\nmov %eax,-0x3c(%rbp)\nmovl $0x1,-0x2c(%rbp)\njmp 13a9 \nmov -0x20(%rbp),%rax\nmov -0x2c(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\ncmp %eax,-0x3c(%rbp)\njge 13a5 \nmov -0x20(%rbp),%rax\nmov -0x2c(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nmov %eax,-0x3c(%rbp)\naddl $0x1,-0x2c(%rbp)\nmov -0x2c(%rbp),%eax\ncmp -0x4c(%rbp),%eax\njl 1383 \nmov -0x3c(%rbp),%eax\nmov %rdi,%rsp\nmov -0x18(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 13cb \ncallq 1080 <__stack_chk_fail@plt>\nmov -0x8(%rbp),%rbx\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rdi, rax\nmov eax, [rbp+var_3C]\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov esi, 10h\nmov edx, 0\ndiv rsi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11F6:\ncmp rsp, rdx\njz short loc_120D\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_11F6\nloc_120D:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1237\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1237:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov [rbp+var_2C], 0\njmp short loc_127A\nloc_1253:\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov ecx, [rax]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_2C]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nadd [rbp+var_2C], 1\nloc_127A:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_3C]\njl short loc_1253\nmov [rbp+var_28], 1\njmp loc_134A\nloc_128E:\nmov [rbp+var_24], 0\njmp loc_133A\nloc_129A:\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_24]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_1336\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov edx, [rax+rdx*4]\nmov eax, [rbp+var_28]\ncdqe\nlea rsi, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rsi\nmov eax, [rax]\nimul eax, edx\ncmp ecx, eax\njge short loc_1336\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov edx, [rax+rdx*4]\nmov eax, [rbp+var_28]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov eax, [rax]\nmov ecx, edx\nimul ecx, eax\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nloc_1336:\nadd [rbp+var_24], 1\nloc_133A:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_28]\njl loc_129A\nadd [rbp+var_28], 1\nloc_134A:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_3C]\njl loc_128E\nmov rax, [rbp+var_10]\nmov eax, [rax]\nmov [rbp+var_20], eax\nmov [rbp+var_1C], 1\njmp short loc_138E\nloc_1368:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ncmp [rbp+var_20], eax\njge short loc_138A\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov [rbp+var_20], eax\nloc_138A:\nadd [rbp+var_1C], 1\nloc_138E:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_3C]\njl short loc_1368\nmov eax, [rbp+var_20]\nmov rsp, rdi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_13B0\ncall ___stack_chk_fail\nlocret_13B0:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned __int64 v2; // rax\n void *v3; // rsp\n _BYTE v5[4]; // [rsp+8h] [rbp-40h] BYREF\n int v6; // [rsp+Ch] [rbp-3Ch]\n __int64 v7; // [rsp+10h] [rbp-38h]\n int i; // [rsp+1Ch] [rbp-2Ch]\n int j; // [rsp+20h] [rbp-28h]\n int k; // [rsp+24h] [rbp-24h]\n unsigned int v11; // [rsp+28h] [rbp-20h]\n int m; // [rsp+2Ch] [rbp-1Ch]\n __int64 v13; // [rsp+30h] [rbp-18h]\n unsigned int *v14; // [rsp+38h] [rbp-10h]\n unsigned __int64 v15; // [rsp+40h] [rbp-8h]\n\n v7 = a1;\n v6 = a2;\n v15 = __readfsqword(0x28u);\n v13 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 0x10uLL);\n while ( v5 != &v5[-(v2 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = alloca(v2 & 0xFFF);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)&v5[(v2 & 0xFFF) - 8] = *(_QWORD *)&v5[(v2 & 0xFFF) - 8];\n v14 = (unsigned int *)v5;\n for ( i = 0; i < v6; ++i )\n v14[i] = *(_DWORD *)(4LL * i + v7);\n for ( j = 1; j < v6; ++j )\n {\n for ( k = 0; k < j; ++k )\n {\n if ( *(_DWORD *)(4LL * j + v7) > *(_DWORD *)(4LL * k + v7)\n && (int)v14[j] < (int)(v14[k] * *(_DWORD *)(4LL * j + v7)) )\n {\n v14[j] = *(_DWORD *)(4LL * j + v7) * v14[k];\n }\n }\n }\n v11 = *v14;\n for ( m = 1; m < v6; ++m )\n {\n if ( (int)v11 < (int)v14[m] )\n v11 = v14[m];\n }\n return v11;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rdi, rax\nmov eax, [rbp+var_3C]\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov esi, 10h\nmov edx, 0\ndiv rsi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11F6:\ncmp rsp, rdx\njz short loc_120D\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_11F6\nloc_120D:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1237\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1237:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov [rbp+var_2C], 0\njmp short loc_127A\nloc_1253:\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov ecx, [rax]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_2C]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nadd [rbp+var_2C], 1\nloc_127A:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_3C]\njl short loc_1253\nmov [rbp+var_28], 1\njmp loc_134A\nloc_128E:\nmov [rbp+var_24], 0\njmp loc_133A\nloc_129A:\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_24]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_1336\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov edx, [rax+rdx*4]\nmov eax, [rbp+var_28]\ncdqe\nlea rsi, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rsi\nmov eax, [rax]\nimul eax, edx\ncmp ecx, eax\njge short loc_1336\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov edx, [rax+rdx*4]\nmov eax, [rbp+var_28]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov eax, [rax]\nmov ecx, edx\nimul ecx, eax\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nloc_1336:\nadd [rbp+var_24], 1\nloc_133A:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_28]\njl loc_129A\nadd [rbp+var_28], 1\nloc_134A:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_3C]\njl loc_128E\nmov rax, [rbp+var_10]\nmov eax, [rax]\nmov [rbp+var_20], eax\nmov [rbp+var_1C], 1\njmp short loc_138E\nloc_1368:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ncmp [rbp+var_20], eax\njge short loc_138A\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov [rbp+var_20], eax\nloc_138A:\nadd [rbp+var_1C], 1\nloc_138E:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_3C]\njl short loc_1368\nmov eax, [rbp+var_20]\nmov rsp, rdi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_13B0\ncall ___stack_chk_fail\nlocret_13B0:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2)\n{\n unsigned __int64 v2; // rax\n void *v3; // rsp\n _BYTE v5[4]; // [rsp+8h] [rbp-40h] BYREF\n int v6; // [rsp+Ch] [rbp-3Ch]\n __int64 v7; // [rsp+10h] [rbp-38h]\n int i; // [rsp+1Ch] [rbp-2Ch]\n int j; // [rsp+20h] [rbp-28h]\n int k; // [rsp+24h] [rbp-24h]\n unsigned int v11; // [rsp+28h] [rbp-20h]\n int m; // [rsp+2Ch] [rbp-1Ch]\n __int64 v13; // [rsp+30h] [rbp-18h]\n unsigned int *v14; // [rsp+38h] [rbp-10h]\n unsigned __int64 v15; // [rsp+40h] [rbp-8h]\n\n v7 = a1;\n v6 = a2;\n v15 = __readfsqword(0x28u);\n v13 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 0x10uLL);\n while ( v5 != &v5[-(v2 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = alloca(v2 & 0xFFF);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)&v5[(v2 & 0xFFF) - 8] = *(_QWORD *)&v5[(v2 & 0xFFF) - 8];\n v14 = (unsigned int *)v5;\n for ( i = 0; i < v6; ++i )\n v14[i] = *(_DWORD *)(4LL * i + v7);\n for ( j = 1; j < v6; ++j )\n {\n for ( k = 0; k < j; ++k )\n {\n if ( *(_DWORD *)(4LL * j + v7) > *(_DWORD *)(4LL * k + v7)\n && (int)v14[j] < (int)(v14[k] * *(_DWORD *)(4LL * j + v7)) )\n {\n v14[j] = *(_DWORD *)(4LL * j + v7) * v14[k];\n }\n }\n }\n v11 = *v14;\n for ( m = 1; m < v6; ++m )\n {\n if ( (int)v11 < (int)v14[m] )\n v11 = v14[m];\n }\n return v11;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2) {\n unsigned long long v2;\n void *v3;\n uint8_t v5[4];\n int v6;\n long long v7;\n int i;\n int j;\n int k;\n unsigned int v11;\n int m;\n long long v13;\n unsigned int *v14;\n unsigned long long v15;\n v7 = a1;\n v6 = a2;\n v15 = __readfsqword(40u);\n v13 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 16uLL);\n while (v5 != &v5[-(v2 & 18446744073709547520LL)])\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)&v5[(v2 & 4095) - 8] = *(uint64_t *)&v5[(v2 & 4095) - 8];\n v14 = (unsigned int *)v5;\n for (i = 0; i < v6; ++i) v14[i] = *(uint32_t *)(4LL * i + v7);\n for (j = 1; j < v6; ++j) {\n for (k = 0; k < j; ++k) {\n if (*(uint32_t *)(4LL * j + v7) > *(uint32_t *)(4LL * k + v7) &&\n (int)v14[j] < (int)(v14[k] * *(uint32_t *)(4LL * j + v7))) {\n v14[j] = *(uint32_t *)(4LL * j + v7) * v14[k];\n }\n }\n }\n v11 = *v14;\n for (m = 1; m < v6; ++m) {\n if ((int)v11 < (int)v14[m]) v11 = v14[m];\n }\n return v11;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned long long v2;\n void *v3;\n uint8_t v5[4];\n int v6;\n long long v7;\n int i;\n int j;\n int k;\n unsigned int v11;\n int m;\n long long v13;\n unsigned int *v14;\n unsigned long long v15;\n v7 = a1;\n v6 = a2;\n v15 = __readfsqword(40u);\n v13 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 16uLL);\n while (v5 != &v5[-(v2 & 18446744073709547520LL)])\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)&v5[(v2 & 4095) - 8] = *(uint64_t *)&v5[(v2 & 4095) - 8];\n v14 = (unsigned int *)v5;\n for (i = 0; i < v6; ++i) v14[i] = *(uint32_t *)(4LL * i + v7);\n for (j = 1; j < v6; ++j) {\n for (k = 0; k < j; ++k) {\n if (*(uint32_t *)(4LL * j + v7) > *(uint32_t *)(4LL * k + v7) &&\n (int)v14[j] < (int)(v14[k] * *(uint32_t *)(4LL * j + v7))) {\n v14[j] = *(uint32_t *)(4LL * j + v7) * v14[k];\n }\n }\n }\n v11 = *v14;\n for (m = 1; m < v6; ++m) {\n if ((int)v11 < (int)v14[m]) v11 = v14[m];\n }\n return v11;\n}" + }, + { + "index": 468, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int mpis[n];\n for (int i = 0; i < n; i++) {\n mpis[i] = arr[i];\n }\n for (int i = 1; i < n; i++) {\n for (int j = 0; j < i; j++) {\n if (arr[i] > arr[j] && mpis[i] < (mpis[j] * arr[i])) {\n mpis[i] = mpis[j] * arr[i];\n }\n }\n }\n int maxVal = mpis[0];\n for (int i = 1; i < n; i++) {\n if (mpis[i] > maxVal) {\n maxVal = mpis[i];\n }\n }\n return maxVal;\n}", + "test": "int main() {\n\n int arr1[] = {3, 100, 4, 5, 150, 6};\n\n int arr2[] = {4, 42, 55, 68, 80};\n\n int arr3[] = {10, 22, 9, 33, 21, 50, 41, 60};\n\n\n\n assert(func0(arr1, 6) == 45000);\n\n assert(func0(arr2, 5) == 50265600);\n\n assert(func0(arr3, 8) == 21780000);\n\n\n\n printf(\"All tests passed!\\n\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x18,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmovslq %esi,%rax\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffffff0,%rdx\nand $0xfffffffffffff000,%rax\nmov %rsp,%rbx\nsub %rax,%rbx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 11dd \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11c6 \nmov %rdx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 11f3 \norq $0x0,-0x8(%rsp,%rax,1)\nlea 0x3(%rsp),%r10\nmov %r10,%r11\nshr $0x2,%r11\nand $0xfffffffffffffffc,%r10\nmov %r10,%r8\ntest %esi,%esi\njle 1225 \nlea -0x1(%rsi),%ecx\nmov $0x0,%eax\nmov (%rdi,%rax,4),%edx\nmov %edx,(%r8,%rax,4)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rcx,%rdx\njne 1212 \ncmp $0x1,%esi\njle 12a8 \nlea -0x2(%rsi),%ebx\nlea 0x2(%rbx),%r9\nmov $0x1,%edx\njmp 1262 \nadd $0x1,%rax\ncmp %rdx,%rax\nje 1259 \ncmp (%rdi,%rax,4),%ecx\njle 1238 \nmov %ecx,%esi\nimul (%r8,%rax,4),%esi\ncmp %esi,(%r8,%rdx,4)\njge 1238 \nmov %esi,(%r8,%rdx,4)\njmp 1238 \nadd $0x1,%rdx\ncmp %r9,%rdx\nje 1270 \ntest %edx,%edx\njle 1259 \nmov (%rdi,%rdx,4),%ecx\nmov $0x0,%eax\njmp 1241 \nmov 0x0(,%r11,4),%edx\nlea 0x4(%r10),%rax\nlea 0x8(%r10,%rbx,4),%rsi\nmov (%rax),%ecx\ncmp %ecx,%edx\ncmovl %ecx,%edx\nadd $0x4,%rax\ncmp %rsi,%rax\njne 1281 \nmov -0x18(%rbp),%rax\nxor %fs:0x28,%rax\njne 12b2 \nmov %edx,%eax\nmov -0x8(%rbp),%rbx\nleaveq\nretq\nmov 0x0(,%r11,4),%edx\njmp 1291 \ncallq 1080 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov r10d, esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmovsxd rcx, esi\nshl rcx, 2\nlea rax, [rcx+0Fh]\nmov rsi, rax\nand rsi, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11C5:\ncmp rsp, rdx\njz short loc_11DC\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11C5\nloc_11DC:\nmov rax, rsi\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11F2\nor [rsp+rax+10h+var_18], 0\nloc_11F2:\nlea rsi, [rsp+10h+var_D]\nmov r11, rsi\nshr r11, 2\nand rsi, 0FFFFFFFFFFFFFFFCh\ntest r10d, r10d\njle loc_12AF\nmov eax, 0\nloc_1210:\nmov edx, [rdi+rax]\nmov [rsi+rax], edx\nadd rax, 4\ncmp rcx, rax\njnz short loc_1210\ncmp r10d, 1\njle loc_12AF\nmov edx, 4\nmov r9d, 1\njmp short loc_1268\nloc_1236:\nadd rax, 4\ncmp rax, rdx\njz short loc_1258\nloc_123F:\ncmp ecx, [rdi+rax]\njle short loc_1236\nmov r8d, ecx\nimul r8d, [rsi+rax]\ncmp [rsi+rdx], r8d\njge short loc_1236\nmov [rsi+rdx], r8d\njmp short loc_1236\nloc_1258:\nlea eax, [r9+1]\nadd rdx, 4\ncmp r10d, eax\njz short loc_1277\nloc_1265:\nmov r9d, eax\nloc_1268:\ntest r9d, r9d\njle short loc_12B9\nmov ecx, [rdi+rdx]\nmov eax, 0\njmp short loc_123F\nloc_1277:\nmov edx, ds:dword_0[r11*4]\nlea rax, [rsi+4]\nlea ecx, [r9-1]\nlea rsi, [rsi+rcx*4+8]\nloc_128C:\nmov ecx, [rax]\ncmp edx, ecx\ncmovl edx, ecx\nadd rax, 4\ncmp rax, rsi\njnz short loc_128C\nloc_129C:\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njnz short loc_12C3\nmov eax, edx\nleave\nretn\nloc_12AF:\nmov edx, ds:dword_0[r11*4]\njmp short loc_129C\nloc_12B9:\nlea eax, [r9+1]\nadd rdx, 4\njmp short loc_1265\nloc_12C3:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // rcx\n signed __int64 v3; // rax\n void *v4; // rsp\n __int64 v5; // rax\n __int64 v6; // rdx\n int i; // r9d\n __int64 v8; // rax\n int v9; // r8d\n int v10; // eax\n int v11; // ecx\n unsigned int v12; // edx\n int *v13; // rax\n __int64 v15; // [rsp+0h] [rbp-18h]\n unsigned int v16; // [rsp+8h] [rbp-10h] BYREF\n int v17; // [rsp+Ch] [rbp-Ch] BYREF\n unsigned __int64 v18; // [rsp+10h] [rbp-8h] BYREF\n\n v18 = __readfsqword(0x28u);\n v2 = 4LL * a2;\n while ( &v16 != (unsigned int *)((char *)&v16 - ((v2 + 15) & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v3 = ((_WORD)v2 + 15) & 0xFF0;\n v4 = alloca(v3);\n if ( (((_WORD)v2 + 15) & 0xFF0) != 0 )\n *(__int64 *)((char *)&v15 + v3) = *(__int64 *)((char *)&v15 + v3);\n if ( a2 <= 0 )\n return v16;\n v5 = 0LL;\n do\n {\n *(unsigned int *)((char *)&v16 + v5) = *(_DWORD *)(a1 + v5);\n v5 += 4LL;\n }\n while ( v2 != v5 );\n if ( a2 <= 1 )\n return v16;\n v6 = 4LL;\n for ( i = 1; ; i = v10 )\n {\n if ( i <= 0 )\n {\n v10 = i + 1;\n v6 += 4LL;\n continue;\n }\n v11 = *(_DWORD *)(a1 + v6);\n v8 = 0LL;\n do\n {\n if ( v11 > *(_DWORD *)(a1 + v8) )\n {\n v9 = *(unsigned int *)((char *)&v16 + v8) * v11;\n if ( *(int *)((char *)&v16 + v6) < v9 )\n *(unsigned int *)((char *)&v16 + v6) = v9;\n }\n v8 += 4LL;\n }\n while ( v8 != v6 );\n v10 = i + 1;\n v6 += 4LL;\n if ( a2 == i + 1 )\n break;\n }\n v12 = v16;\n v13 = &v17;\n do\n {\n if ( (int)v12 < *v13 )\n v12 = *v13;\n ++v13;\n }\n while ( v13 != (int *)((char *)&v18 + 4 * (unsigned int)(i - 1)) );\n return v12;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov r10d, esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmovsxd rcx, esi\nshl rcx, 2\nlea rax, [rcx+0Fh]\nmov rsi, rax\nand rsi, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11C5:\ncmp rsp, rdx\njz short loc_11DC\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11C5\nloc_11DC:\nmov rax, rsi\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11F2\nor [rsp+rax+10h+var_18], 0\nloc_11F2:\nlea rsi, [rsp+10h+var_D]\nmov r11, rsi\nshr r11, 2\nand rsi, 0FFFFFFFFFFFFFFFCh\ntest r10d, r10d\njle loc_12AF\nmov eax, 0\nloc_1210:\nmov edx, [rdi+rax]\nmov [rsi+rax], edx\nadd rax, 4\ncmp rcx, rax\njnz short loc_1210\ncmp r10d, 1\njle loc_12AF\nmov edx, 4\nmov r9d, 1\njmp short loc_1268\nloc_1236:\nadd rax, 4\ncmp rax, rdx\njz short loc_1258\nloc_123F:\ncmp ecx, [rdi+rax]\njle short loc_1236\nmov r8d, ecx\nimul r8d, [rsi+rax]\ncmp [rsi+rdx], r8d\njge short loc_1236\nmov [rsi+rdx], r8d\njmp short loc_1236\nloc_1258:\nlea eax, [r9+1]\nadd rdx, 4\ncmp r10d, eax\njz short loc_1277\nloc_1265:\nmov r9d, eax\nloc_1268:\ntest r9d, r9d\njle short loc_12B9\nmov ecx, [rdi+rdx]\nmov eax, 0\njmp short loc_123F\nloc_1277:\nmov edx, ds:dword_0[r11*4]\nlea rax, [rsi+4]\nlea ecx, [r9-1]\nlea rsi, [rsi+rcx*4+8]\nloc_128C:\nmov ecx, [rax]\ncmp edx, ecx\ncmovl edx, ecx\nadd rax, 4\ncmp rax, rsi\njnz short loc_128C\nloc_129C:\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njnz short loc_12C3\nmov eax, edx\nleave\nretn\nloc_12AF:\nmov edx, ds:dword_0[r11*4]\njmp short loc_129C\nloc_12B9:\nlea eax, [r9+1]\nadd rdx, 4\njmp short loc_1265\nloc_12C3:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2)\n{\n __int64 v2; // rcx\n signed __int64 v3; // rax\n void *v4; // rsp\n __int64 v5; // rax\n __int64 v6; // rdx\n int i; // r9d\n __int64 v8; // rax\n int v9; // r8d\n int v10; // eax\n int v11; // ecx\n unsigned int v12; // edx\n int *v13; // rax\n __int64 v15; // [rsp+0h] [rbp-18h]\n unsigned int v16; // [rsp+8h] [rbp-10h] BYREF\n int v17; // [rsp+Ch] [rbp-Ch] BYREF\n unsigned __int64 v18; // [rsp+10h] [rbp-8h] BYREF\n\n v18 = __readfsqword(0x28u);\n v2 = 4LL * a2;\n while ( &v16 != (unsigned int *)((char *)&v16 - ((v2 + 15) & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v3 = ((_WORD)v2 + 15) & 0xFF0;\n v4 = alloca(v3);\n if ( (((_WORD)v2 + 15) & 0xFF0) != 0 )\n *(__int64 *)((char *)&v15 + v3) = *(__int64 *)((char *)&v15 + v3);\n if ( a2 <= 0 )\n return v16;\n v5 = 0LL;\n do\n {\n *(unsigned int *)((char *)&v16 + v5) = *(_DWORD *)(a1 + v5);\n v5 += 4LL;\n }\n while ( v2 != v5 );\n if ( a2 <= 1 )\n return v16;\n v6 = 4LL;\n for ( i = 1; ; i = v10 )\n {\n if ( i <= 0 )\n {\n v10 = i + 1;\n v6 += 4LL;\n continue;\n }\n v11 = *(_DWORD *)(a1 + v6);\n v8 = 0LL;\n do\n {\n if ( v11 > *(_DWORD *)(a1 + v8) )\n {\n v9 = *(unsigned int *)((char *)&v16 + v8) * v11;\n if ( *(int *)((char *)&v16 + v6) < v9 )\n *(unsigned int *)((char *)&v16 + v6) = v9;\n }\n v8 += 4LL;\n }\n while ( v8 != v6 );\n v10 = i + 1;\n v6 += 4LL;\n if ( a2 == i + 1 )\n break;\n }\n v12 = v16;\n v13 = &v17;\n do\n {\n if ( (int)v12 < *v13 )\n v12 = *v13;\n ++v13;\n }\n while ( v13 != (int *)((char *)&v18 + 4 * (unsigned int)(i - 1)) );\n return v12;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2) {\n long long v2;\n signed long long v3;\n void *v4;\n long long v5;\n long long v6;\n int i;\n long long v8;\n int v9;\n int v10;\n int v11;\n unsigned int v12;\n int *v13;\n long long v15;\n unsigned int v16;\n int v17;\n unsigned long long v18;\n v18 = __readfsqword(40u);\n v2 = 4LL * a2;\n while (&v16 !=\n (unsigned int *)((char *)&v16 - ((v2 + 15) & 18446744073709547520LL)))\n ;\n v3 = ((unsigned short)v2 + 15) & 4080;\n v4 = alloca(v3);\n if ((((unsigned short)v2 + 15) & 4080) != 0)\n *(long long *)((char *)&v15 + v3) = *(long long *)((char *)&v15 + v3);\n if (a2 <= 0) return v16;\n v5 = 0LL;\n do {\n *(unsigned int *)((char *)&v16 + v5) = *(uint32_t *)(a1 + v5);\n v5 += 4LL;\n } while (v2 != v5);\n if (a2 <= 1) return v16;\n v6 = 4LL;\n for (i = 1;; i = v10) {\n if (i <= 0) {\n v10 = i + 1;\n v6 += 4LL;\n continue;\n }\n v11 = *(uint32_t *)(a1 + v6);\n v8 = 0LL;\n do {\n if (v11 > *(uint32_t *)(a1 + v8)) {\n v9 = *(unsigned int *)((char *)&v16 + v8) * v11;\n if (*(int *)((char *)&v16 + v6) < v9)\n *(unsigned int *)((char *)&v16 + v6) = v9;\n }\n v8 += 4LL;\n } while (v8 != v6);\n v10 = i + 1;\n v6 += 4LL;\n if (a2 == i + 1) break;\n }\n v12 = v16;\n v13 = &v17;\n do {\n if ((int)v12 < *v13) v12 = *v13;\n ++v13;\n } while (v13 != (int *)((char *)&v18 + 4 * (unsigned int)(i - 1)));\n return v12;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n signed long long v3;\n void *v4;\n long long v5;\n long long v6;\n int i;\n long long v8;\n int v9;\n int v10;\n int v11;\n unsigned int v12;\n int *v13;\n long long v15;\n unsigned int v16;\n int v17;\n unsigned long long v18;\n v18 = __readfsqword(40u);\n v2 = 4LL * a2;\n while (&v16 !=\n (unsigned int *)((char *)&v16 - ((v2 + 15) & 18446744073709547520LL)))\n ;\n v3 = ((unsigned short)v2 + 15) & 4080;\n v4 = alloca(v3);\n if ((((unsigned short)v2 + 15) & 4080) != 0)\n *(long long *)((char *)&v15 + v3) = *(long long *)((char *)&v15 + v3);\n if (a2 <= 0) return v16;\n v5 = 0LL;\n do {\n *(unsigned int *)((char *)&v16 + v5) = *(uint32_t *)(a1 + v5);\n v5 += 4LL;\n } while (v2 != v5);\n if (a2 <= 1) return v16;\n v6 = 4LL;\n for (i = 1;; i = v10) {\n if (i <= 0) {\n v10 = i + 1;\n v6 += 4LL;\n continue;\n }\n v11 = *(uint32_t *)(a1 + v6);\n v8 = 0LL;\n do {\n if (v11 > *(uint32_t *)(a1 + v8)) {\n v9 = *(unsigned int *)((char *)&v16 + v8) * v11;\n if (*(int *)((char *)&v16 + v6) < v9)\n *(unsigned int *)((char *)&v16 + v6) = v9;\n }\n v8 += 4LL;\n } while (v8 != v6);\n v10 = i + 1;\n v6 += 4LL;\n if (a2 == i + 1) break;\n }\n v12 = v16;\n v13 = &v17;\n do {\n if ((int)v12 < *v13) v12 = *v13;\n ++v13;\n } while (v13 != (int *)((char *)&v18 + 4 * (unsigned int)(i - 1)));\n return v12;\n}" + }, + { + "index": 468, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int mpis[n];\n for (int i = 0; i < n; i++) {\n mpis[i] = arr[i];\n }\n for (int i = 1; i < n; i++) {\n for (int j = 0; j < i; j++) {\n if (arr[i] > arr[j] && mpis[i] < (mpis[j] * arr[i])) {\n mpis[i] = mpis[j] * arr[i];\n }\n }\n }\n int maxVal = mpis[0];\n for (int i = 1; i < n; i++) {\n if (mpis[i] > maxVal) {\n maxVal = mpis[i];\n }\n }\n return maxVal;\n}", + "test": "int main() {\n\n int arr1[] = {3, 100, 4, 5, 150, 6};\n\n int arr2[] = {4, 42, 55, 68, 80};\n\n int arr3[] = {10, 22, 9, 33, 21, 50, 41, 60};\n\n\n\n assert(func0(arr1, 6) == 45000);\n\n assert(func0(arr2, 5) == 50265600);\n\n assert(func0(arr3, 8) == 21780000);\n\n\n\n printf(\"All tests passed!\\n\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovslq %esi,%rax\nmov %rsp,%rcx\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rcx\nand $0xfffffffffffffff0,%rdx\nmov %rcx,%rax\ncmp %rax,%rsp\nje 1356 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 1341 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 141e \nlea 0x3(%rsp),%r8\nlea -0x1(%rsi),%ecx\nxor %eax,%eax\nmov %r8,%r9\nand $0xfffffffffffffffc,%r8\nshr $0x2,%r9\ntest %esi,%esi\njle 1429 \nnopl (%rax)\nmov (%rdi,%rax,4),%edx\nmov %edx,(%r8,%rax,4)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rcx,%rdx\njne 1388 \nmov 0x0(,%r9,4),%r9d\ncmp $0x1,%esi\njle 140a \nlea -0x2(%rsi),%r11d\nmov $0x1,%edx\nlea 0x2(%r11),%r10\nnopl (%rax)\nmov (%rdi,%rdx,4),%ecx\nxor %eax,%eax\nnopl (%rax)\ncmp (%rdi,%rax,4),%ecx\njle 13d6 \nmov (%r8,%rax,4),%esi\nimul %ecx,%esi\ncmp %esi,(%r8,%rdx,4)\njge 13d6 \nmov %esi,(%r8,%rdx,4)\nadd $0x1,%rax\ncmp %rdx,%rax\njne 13c0 \nlea 0x1(%rax),%rdx\ncmp %rdx,%r10\njne 13b8 \nlea 0x4(%r8),%rax\nlea 0x8(%r8,%r11,4),%rcx\nnopl 0x0(%rax)\nmov (%rax),%edx\ncmp %edx,%r9d\ncmovl %edx,%r9d\nadd $0x4,%rax\ncmp %rax,%rcx\njne 13f8 \nmov -0x8(%rbp),%rax\nxor %fs:0x28,%rax\njne 1433 \nleaveq\nmov %r9d,%eax\nretq\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 1368 \nmov 0x0(,%r9,4),%r9d\njmp 140a \ncallq 1080 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r14\nmov r14d, esi\npush r13\npush r12\npush rbx\nmov rbx, rdi\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nmovsxd rax, esi\nmov rcx, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_1340\nloc_132B:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rcx\njnz short loc_132B\nloc_1340:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1433\nloc_1352:\nlea rdi, [rsp+1030h+var_102D]\nmov r13, rdi\nand rdi, 0FFFFFFFFFFFFFFFCh; dest\nshr r13, 2\ntest r14d, r14d\njle loc_143E\nmov r12d, r14d\nmov rsi, rbx; src\nshl r12, 2\nmov rdx, r12; n\ncall _memcpy\nmov r8d, ds:dword_0[r13*4]\nmov rdi, rax\ncmp r14d, 1\njz loc_1414\nlea r9d, [r14-2]\nmov edx, 4\nnop dword ptr [rax+rax+00h]\nloc_13A0:\nmov ecx, [rbx+rdx]\nxor eax, eax\nnop dword ptr [rax]\nloc_13A8:\ncmp ecx, [rbx+rax]\njle short loc_13BB\nmov esi, [rdi+rax]\nimul esi, ecx\ncmp [rdi+rdx], esi\njge short loc_13BB\nmov [rdi+rdx], esi\nloc_13BB:\nadd rax, 4\ncmp rax, rdx\njnz short loc_13A8\nlea rdx, [rax+4]\ncmp rdx, r12\njnz short loc_13A0\nlea rcx, [rdi+r9*4+8]\nlea rax, [rdi+4]\nmov rdx, rcx\nsub rdx, rax\nand edx, 4\njz short loc_13F8\nmov eax, [rax]\ncmp r8d, eax\ncmovl r8d, eax\nlea rax, [rdi+8]\ncmp rax, rcx\njz short loc_1414\nnop dword ptr [rax+rax+00h]\nloc_13F8:\nmov edx, [rax]\ncmp r8d, edx\ncmovl r8d, edx\nmov edx, [rax+4]\ncmp r8d, edx\ncmovl r8d, edx\nadd rax, 8\ncmp rax, rcx\njnz short loc_13F8\nloc_1414:\nmov rax, [rbp+var_28]\nsub rax, fs:28h\njnz short loc_1448\nlea rsp, [rbp-20h]\nmov eax, r8d\npop rbx\npop r12\npop r13\npop r14\npop rbp\nretn\nloc_1433:\nor [rsp+rdx+1030h+var_1038], 0\njmp loc_1352\nloc_143E:\nmov r8d, ds:dword_0[r13*4]\njmp short loc_1414\nloc_1448:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(char *src, int a2)\n{\n __int64 v4; // rdx\n _DWORD *v5; // rcx\n __int16 v6; // dx\n signed __int64 v7; // rdx\n void *v8; // rsp\n char *v9; // rax\n signed int v10; // r8d\n char *v11; // rdi\n __int64 v12; // rdx\n int v13; // ecx\n __int64 v14; // rax\n int v15; // esi\n __int64 v16; // rcx\n signed int *v17; // rax\n int v18; // eax\n _DWORD v21[1022]; // [rsp+8h] [rbp-1030h] BYREF\n _QWORD v22[6]; // [rsp+1008h] [rbp-30h] BYREF\n\n v22[1] = __readfsqword(0x28u);\n v4 = 4LL * a2 + 15;\n v5 = (_DWORD *)((char *)v22 - (v4 & 0xFFFFFFFFFFFFF000LL));\n v6 = v4 & 0xFFF0;\n if ( v22 != (_QWORD *)v5 )\n {\n while ( v21 != v5 )\n ;\n }\n v7 = v6 & 0xFFF;\n v8 = alloca(v7);\n if ( v7 )\n *(_QWORD *)((char *)&v21[-2] + v7) = *(_QWORD *)((char *)&v21[-2] + v7);\n if ( a2 <= 0 )\n {\n return (unsigned int)v21[0];\n }\n else\n {\n v9 = (char *)memcpy(v21, src, 4LL * (unsigned int)a2);\n v10 = v21[0];\n v11 = v9;\n if ( a2 != 1 )\n {\n v12 = 4LL;\n do\n {\n v13 = *(_DWORD *)&src[v12];\n v14 = 0LL;\n do\n {\n if ( v13 > *(_DWORD *)&src[v14] )\n {\n v15 = v13 * *(_DWORD *)&v11[v14];\n if ( *(_DWORD *)&v11[v12] < v15 )\n *(_DWORD *)&v11[v12] = v15;\n }\n v14 += 4LL;\n }\n while ( v14 != v12 );\n v12 = v14 + 4;\n }\n while ( v14 + 4 != 4LL * (unsigned int)a2 );\n v16 = (__int64)&v11[4 * (a2 - 2) + 8];\n v17 = (signed int *)(v11 + 4);\n if ( ((4 * ((_BYTE)a2 - 2) + 4) & 4) == 0 )\n goto LABEL_27;\n v18 = *v17;\n if ( v10 < v18 )\n v10 = v18;\n v17 = (signed int *)(v11 + 8);\n if ( v11 + 8 != (char *)v16 )\n {\nLABEL_27:\n do\n {\n if ( v10 < *v17 )\n v10 = *v17;\n if ( v10 < v17[1] )\n v10 = v17[1];\n v17 += 2;\n }\n while ( v17 != (signed int *)v16 );\n }\n }\n }\n return (unsigned int)v10;\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\npush rbp\nmov rbp, rsp\npush r14\nmov r14d, esi\npush r13\npush r12\npush rbx\nmov rbx, rdi\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nmovsxd rax, esi\nmov rcx, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_1340\nloc_132B:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rcx\njnz short loc_132B\nloc_1340:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1433\nloc_1352:\nlea rdi, [rsp+1030h+var_102D]\nmov r13, rdi\nand rdi, 0FFFFFFFFFFFFFFFCh; dest\nshr r13, 2\ntest r14d, r14d\njle loc_143E\nmov r12d, r14d\nmov rsi, rbx; src\nshl r12, 2\nmov rdx, r12; n\ncall _memcpy\nmov r8d, ds:dword_0[r13*4]\nmov rdi, rax\ncmp r14d, 1\njz loc_1414\nlea r9d, [r14-2]\nmov edx, 4\nnop dword ptr [rax+rax+00h]\nloc_13A0:\nmov ecx, [rbx+rdx]\nxor eax, eax\nnop dword ptr [rax]\nloc_13A8:\ncmp ecx, [rbx+rax]\njle short loc_13BB\nmov esi, [rdi+rax]\nimul esi, ecx\ncmp [rdi+rdx], esi\njge short loc_13BB\nmov [rdi+rdx], esi\nloc_13BB:\nadd rax, 4\ncmp rax, rdx\njnz short loc_13A8\nlea rdx, [rax+4]\ncmp rdx, r12\njnz short loc_13A0\nlea rcx, [rdi+r9*4+8]\nlea rax, [rdi+4]\nmov rdx, rcx\nsub rdx, rax\nand edx, 4\njz short loc_13F8\nmov eax, [rax]\ncmp r8d, eax\ncmovl r8d, eax\nlea rax, [rdi+8]\ncmp rax, rcx\njz short loc_1414\nnop dword ptr [rax+rax+00h]\nloc_13F8:\nmov edx, [rax]\ncmp r8d, edx\ncmovl r8d, edx\nmov edx, [rax+4]\ncmp r8d, edx\ncmovl r8d, edx\nadd rax, 8\ncmp rax, rcx\njnz short loc_13F8\nloc_1414:\nmov rax, [rbp+var_28]\nsub rax, fs:28h\njnz short loc_1448\nlea rsp, [rbp-20h]\nmov eax, r8d\npop rbx\npop r12\npop r13\npop r14\npop rbp\nretn\nloc_1433:\nor [rsp+rdx+1030h+var_1038], 0\njmp loc_1352\nloc_143E:\nmov r8d, ds:dword_0[r13*4]\njmp short loc_1414\nloc_1448:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12E0(char *src, int a2)\n{\n __int64 v4; // rdx\n _DWORD *v5; // rcx\n __int16 v6; // dx\n signed __int64 v7; // rdx\n void *v8; // rsp\n char *v9; // rax\n signed int v10; // r8d\n char *v11; // rdi\n __int64 v12; // rdx\n int v13; // ecx\n __int64 v14; // rax\n int v15; // esi\n __int64 v16; // rcx\n signed int *v17; // rax\n int v18; // eax\n _DWORD v21[1022]; // [rsp+8h] [rbp-1030h] BYREF\n _QWORD v22[6]; // [rsp+1008h] [rbp-30h] BYREF\n\n v22[1] = __readfsqword(0x28u);\n v4 = 4LL * a2 + 15;\n v5 = (_DWORD *)((char *)v22 - (v4 & 0xFFFFFFFFFFFFF000LL));\n v6 = v4 & 0xFFF0;\n if ( v22 != (_QWORD *)v5 )\n {\n while ( v21 != v5 )\n ;\n }\n v7 = v6 & 0xFFF;\n v8 = alloca(v7);\n if ( v7 )\n *(_QWORD *)((char *)&v21[-2] + v7) = *(_QWORD *)((char *)&v21[-2] + v7);\n if ( a2 <= 0 )\n {\n return (unsigned int)v21[0];\n }\n else\n {\n v9 = (char *)memcpy(v21, src, 4LL * (unsigned int)a2);\n v10 = v21[0];\n v11 = v9;\n if ( a2 != 1 )\n {\n v12 = 4LL;\n do\n {\n v13 = *(_DWORD *)&src[v12];\n v14 = 0LL;\n do\n {\n if ( v13 > *(_DWORD *)&src[v14] )\n {\n v15 = v13 * *(_DWORD *)&v11[v14];\n if ( *(_DWORD *)&v11[v12] < v15 )\n *(_DWORD *)&v11[v12] = v15;\n }\n v14 += 4LL;\n }\n while ( v14 != v12 );\n v12 = v14 + 4;\n }\n while ( v14 + 4 != 4LL * (unsigned int)a2 );\n v16 = (__int64)&v11[4 * (a2 - 2) + 8];\n v17 = (signed int *)(v11 + 4);\n if ( ((4 * ((_BYTE)a2 - 2) + 4) & 4) == 0 )\n goto LABEL_27;\n v18 = *v17;\n if ( v10 < v18 )\n v10 = v18;\n v17 = (signed int *)(v11 + 8);\n if ( v11 + 8 != (char *)v16 )\n {\nLABEL_27:\n do\n {\n if ( v10 < *v17 )\n v10 = *v17;\n if ( v10 < v17[1] )\n v10 = v17[1];\n v17 += 2;\n }\n while ( v17 != (signed int *)v16 );\n }\n }\n }\n return (unsigned int)v10;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12E0(char *src, int a2) {\n long long v4;\n uint32_t *v5;\n short v6;\n signed long long v7;\n void *v8;\n char *v9;\n signed int v10;\n char *v11;\n long long v12;\n int v13;\n long long v14;\n int v15;\n long long v16;\n signed int *v17;\n int v18;\n uint32_t v21[1022];\n uint64_t v22[6];\n v22[1] = __readfsqword(40u);\n v4 = 4LL * a2 + 15;\n v5 = (uint32_t *)((char *)v22 - (v4 & 18446744073709547520LL));\n v6 = v4 & 65520;\n if (v22 != (uint64_t *)v5) {\n while (v21 != v5)\n ;\n }\n v7 = v6 & 4095;\n v8 = alloca(v7);\n if (v7)\n *(uint64_t *)((char *)&v21[-2] + v7) = *(uint64_t *)((char *)&v21[-2] + v7);\n if (a2 <= 0) {\n return (unsigned int)v21[0];\n } else {\n v9 = (char *)memcpy(v21, src, 4LL * (unsigned int)a2);\n v10 = v21[0];\n v11 = v9;\n if (a2 != 1) {\n v12 = 4LL;\n do {\n v13 = *(uint32_t *)&src[v12];\n v14 = 0LL;\n do {\n if (v13 > *(uint32_t *)&src[v14]) {\n v15 = v13 * *(uint32_t *)&v11[v14];\n if (*(uint32_t *)&v11[v12] < v15) *(uint32_t *)&v11[v12] = v15;\n }\n v14 += 4LL;\n } while (v14 != v12);\n v12 = v14 + 4;\n } while (v14 + 4 != 4LL * (unsigned int)a2);\n v16 = (long long)&v11[4 * (a2 - 2) + 8];\n v17 = (signed int *)(v11 + 4);\n if (((4 * ((uint8_t)a2 - 2) + 4) & 4) == 0) goto LABEL_27;\n v18 = *v17;\n if (v10 < v18) v10 = v18;\n v17 = (signed int *)(v11 + 8);\n if (v11 + 8 != (char *)v16) {\n LABEL_27:\n do {\n if (v10 < *v17) v10 = *v17;\n if (v10 < v17[1]) v10 = v17[1];\n v17 += 2;\n } while (v17 != (signed int *)v16);\n }\n }\n }\n return (unsigned int)v10;\n}", + "ida_pseudo_norm": "long long func0(char *src, int a2) {\n long long v4;\n uint32_t *v5;\n short v6;\n signed long long v7;\n void *v8;\n char *v9;\n signed int v10;\n char *v11;\n long long v12;\n int v13;\n long long v14;\n int v15;\n long long v16;\n signed int *v17;\n int v18;\n uint32_t v21[1022];\n uint64_t v22[6];\n v22[1] = __readfsqword(40u);\n v4 = 4LL * a2 + 15;\n v5 = (uint32_t *)((char *)v22 - (v4 & 18446744073709547520LL));\n v6 = v4 & 65520;\n if (v22 != (uint64_t *)v5) {\n while (v21 != v5)\n ;\n }\n v7 = v6 & 4095;\n v8 = alloca(v7);\n if (v7)\n *(uint64_t *)((char *)&v21[-2] + v7) = *(uint64_t *)((char *)&v21[-2] + v7);\n if (a2 <= 0) {\n return (unsigned int)v21[0];\n } else {\n v9 = (char *)memcpy(v21, src, 4LL * (unsigned int)a2);\n v10 = v21[0];\n v11 = v9;\n if (a2 != 1) {\n v12 = 4LL;\n do {\n v13 = *(uint32_t *)&src[v12];\n v14 = 0LL;\n do {\n if (v13 > *(uint32_t *)&src[v14]) {\n v15 = v13 * *(uint32_t *)&v11[v14];\n if (*(uint32_t *)&v11[v12] < v15) *(uint32_t *)&v11[v12] = v15;\n }\n v14 += 4LL;\n } while (v14 != v12);\n v12 = v14 + 4;\n } while (v14 + 4 != 4LL * (unsigned int)a2);\n v16 = (long long)&v11[4 * (a2 - 2) + 8];\n v17 = (signed int *)(v11 + 4);\n if (((4 * ((uint8_t)a2 - 2) + 4) & 4) == 0) goto LABEL_27;\n v18 = *v17;\n if (v10 < v18) v10 = v18;\n v17 = (signed int *)(v11 + 8);\n if (v11 + 8 != (char *)v16) {\n LABEL_27:\n do {\n if (v10 < *v17) v10 = *v17;\n if (v10 < v17[1]) v10 = v17[1];\n v17 += 2;\n } while (v17 != (signed int *)v16);\n }\n }\n }\n return (unsigned int)v10;\n}" + }, + { + "index": 468, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int mpis[n];\n for (int i = 0; i < n; i++) {\n mpis[i] = arr[i];\n }\n for (int i = 1; i < n; i++) {\n for (int j = 0; j < i; j++) {\n if (arr[i] > arr[j] && mpis[i] < (mpis[j] * arr[i])) {\n mpis[i] = mpis[j] * arr[i];\n }\n }\n }\n int maxVal = mpis[0];\n for (int i = 1; i < n; i++) {\n if (mpis[i] > maxVal) {\n maxVal = mpis[i];\n }\n }\n return maxVal;\n}", + "test": "int main() {\n\n int arr1[] = {3, 100, 4, 5, 150, 6};\n\n int arr2[] = {4, 42, 55, 68, 80};\n\n int arr3[] = {10, 22, 9, 33, 21, 50, 41, 60};\n\n\n\n assert(func0(arr1, 6) == 45000);\n\n assert(func0(arr2, 5) == 50265600);\n\n assert(func0(arr3, 8) == 21780000);\n\n\n\n printf(\"All tests passed!\\n\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r14\npush %r13\npush %r12\nmov %esi,%r12d\npush %rbx\nmov %rdi,%rbx\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x28(%rbp)\nxor %eax,%eax\nmovslq %esi,%rax\nmov %rsp,%rdi\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rdi\nand $0xfffffffffffffff0,%rdx\nmov %rdi,%rax\ncmp %rax,%rsp\nje 1343 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 132e \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 14d8 \nlea 0x3(%rsp),%rdi\nmov %rdi,%r14\nand $0xfffffffffffffffc,%rdi\nshr $0x2,%r14\ntest %r12d,%r12d\njle 14e3 \nlea -0x1(%r12),%eax\nmov %rbx,%rsi\nlea 0x4(,%rax,4),%rdx\nmov %rax,%r13\ncallq 10b0 \nmov 0x0(,%r14,4),%r8d\nmov %rax,%rdi\ncmp $0x1,%r12d\njle 14b9 \nlea -0x2(%r12),%r9d\nmov $0x1,%edx\nmov %r9,%r10\nadd $0x2,%r9\nnopl 0x0(%rax)\nmov (%rbx,%rdx,4),%ecx\nxor %eax,%eax\nnopl (%rax)\ncmp (%rbx,%rax,4),%ecx\njle 13cb \nmov (%rdi,%rax,4),%esi\nimul %ecx,%esi\ncmp %esi,(%rdi,%rdx,4)\njge 13cb \nmov %esi,(%rdi,%rdx,4)\nadd $0x1,%rax\ncmp %rdx,%rax\njne 13b8 \nlea 0x1(%rax),%rdx\ncmp %r9,%rdx\njne 13b0 \ncmp $0x2,%r10d\njbe 14ed \nmov %r13d,%edx\nmovd %r8d,%xmm4\nmov %rdi,%rax\nshr $0x2,%edx\npshufd $0x0,%xmm4,%xmm2\nshl $0x4,%rdx\nadd %rdi,%rdx\nnopl 0x0(%rax)\nmovdqu 0x4(%rax),%xmm0\nadd $0x10,%rax\nmovdqa %xmm0,%xmm1\npcmpgtd %xmm2,%xmm1\npand %xmm1,%xmm0\npandn %xmm2,%xmm1\nmovdqa %xmm1,%xmm2\npor %xmm0,%xmm2\ncmp %rdx,%rax\njne 1408 \nmovdqa %xmm2,%xmm0\nmov %r13d,%edx\npsrldq $0x8,%xmm0\nand $0xfffffffc,%edx\nmovdqa %xmm0,%xmm1\nmovdqa %xmm0,%xmm3\nlea 0x1(%rdx),%eax\npcmpgtd %xmm2,%xmm1\nmovdqa %xmm1,%xmm0\npand %xmm1,%xmm3\npandn %xmm2,%xmm0\npor %xmm3,%xmm0\nmovdqa %xmm0,%xmm2\npsrldq $0x4,%xmm2\nmovdqa %xmm2,%xmm1\npcmpgtd %xmm0,%xmm1\npand %xmm1,%xmm2\npandn %xmm0,%xmm1\npor %xmm2,%xmm1\nmovd %xmm1,%r8d\ncmp %r13d,%edx\nje 14b9 \nmovslq %eax,%rdx\nmov (%rdi,%rdx,4),%edx\ncmp %edx,%r8d\ncmovl %edx,%r8d\nlea 0x1(%rax),%edx\ncmp %edx,%r12d\njle 14b9 \nmovslq %edx,%rdx\nmov (%rdi,%rdx,4),%edx\ncmp %edx,%r8d\ncmovl %edx,%r8d\nadd $0x2,%eax\ncmp %eax,%r12d\njle 14b9 \ncltq\nmov (%rdi,%rax,4),%eax\ncmp %eax,%r8d\ncmovl %eax,%r8d\nmov -0x28(%rbp),%rax\nxor %fs:0x28,%rax\njne 14f4 \nlea -0x20(%rbp),%rsp\nmov %r8d,%eax\npop %rbx\npop %r12\npop %r13\npop %r14\npop %rbp\nretq\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 1355 \nmov 0x0(,%r14,4),%r8d\njmp 14b9 \nmov $0x1,%eax\njmp 1483 \ncallq 1090 <__stack_chk_fail@plt>\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\nmov r12d, esi\npush rbx\nmov rbx, rdi\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nmovsxd rax, esi\nmov rcx, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_1342\nloc_132D:\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\ncmp rsp, rcx\njnz short loc_132D\nloc_1342:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_14C9\nloc_1354:\nlea rdi, [rsp+1040h+var_103D]\nmov r14, rdi\nand rdi, 0FFFFFFFFFFFFFFFCh; dest\nshr r14, 2\ntest r12d, r12d\njle loc_14DB\nmov r15d, r12d\nmov rsi, rbx; src\nlea r13d, [r12-1]\nshl r15, 2\nmov rdx, r15; n\ncall _memcpy\nmov r8d, ds:dword_0[r14*4]\nmov rdi, rax\ncmp r12d, 1\njz loc_14A8\nlea r9d, [r12-2]\nmov edx, 4\nnop dword ptr [rax+rax+00h]\nloc_13A8:\nmov ecx, [rbx+rdx]\nxor eax, eax\nnop dword ptr [rax]\nloc_13B0:\ncmp ecx, [rbx+rax]\njle short loc_13C3\nmov esi, [rdi+rax]\nimul esi, ecx\ncmp [rdi+rdx], esi\njge short loc_13C3\nmov [rdi+rdx], esi\nloc_13C3:\nadd rax, 4\ncmp rax, rdx\njnz short loc_13B0\nlea rdx, [rax+4]\ncmp rdx, r15\njnz short loc_13A8\ncmp r9d, 2\njbe loc_14D4\nmov edx, r13d\nmovd xmm3, r8d\nmov rax, rdi\nshr edx, 2\npshufd xmm2, xmm3, 0\nshl rdx, 4\nadd rdx, rdi\nnop dword ptr [rax+00000000h]\nloc_1400:\nmovdqu xmm0, xmmword ptr [rax+4]\nadd rax, 10h\nmovdqa xmm1, xmm0\npcmpgtd xmm1, xmm2\npand xmm0, xmm1\npandn xmm1, xmm2\nmovdqa xmm2, xmm1\npor xmm2, xmm0\ncmp rdx, rax\njnz short loc_1400\nmovdqa xmm1, xmm2\nmov eax, r13d\npsrldq xmm1, 8\nand eax, 0FFFFFFFCh\nmovdqa xmm0, xmm1\nadd eax, 1\nand r13d, 3\npcmpgtd xmm0, xmm2\npand xmm1, xmm0\npandn xmm0, xmm2\npor xmm0, xmm1\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\nmovdqa xmm1, xmm2\npcmpgtd xmm1, xmm0\npand xmm2, xmm1\npandn xmm1, xmm0\npor xmm1, xmm2\nmovd r8d, xmm1\njz short loc_14A8\nloc_1474:\nmovsxd rdx, eax\nlea rdx, [rdi+rdx*4]\nmov ecx, [rdx]\ncmp r8d, ecx\ncmovl r8d, ecx\nlea ecx, [rax+1]\ncmp r12d, ecx\njle short loc_14A8\nmov ecx, [rdx+4]\ncmp r8d, ecx\ncmovl r8d, ecx\nadd eax, 2\ncmp r12d, eax\njle short loc_14A8\nmov eax, [rdx+8]\ncmp r8d, eax\ncmovl r8d, eax\nloc_14A8:\nmov rax, [rbp+var_38]\nsub rax, fs:28h\njnz short loc_14E5\nlea rsp, [rbp-28h]\nmov eax, r8d\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_14C9:\nor [rsp+rdx+1040h+var_1048], 0\njmp loc_1354\nloc_14D4:\nmov eax, 1\njmp short loc_1474\nloc_14DB:\nmov r8d, ds:dword_0[r14*4]\njmp short loc_14A8\nloc_14E5:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(char *src, int a2)\n{\n __int64 v4; // rdx\n _DWORD *v5; // rcx\n __int16 v6; // dx\n signed __int64 v7; // rdx\n void *v8; // rsp\n unsigned int v9; // r13d\n char *v10; // rax\n signed int v11; // r8d\n char *v12; // rdi\n __int64 v13; // rdx\n int v14; // ecx\n __int64 v15; // rax\n int v16; // esi\n char *v17; // rax\n __m128i v18; // xmm2\n __m128i v19; // xmm0\n __m128i v20; // xmm1\n __m128i v21; // xmm1\n signed int v22; // eax\n __m128i v23; // xmm0\n __m128i v24; // xmm0\n __m128i v25; // xmm2\n __m128i v26; // xmm1\n signed int *v27; // rdx\n _DWORD v30[1022]; // [rsp+8h] [rbp-1040h] BYREF\n _QWORD v31[8]; // [rsp+1008h] [rbp-40h] BYREF\n\n v31[1] = __readfsqword(0x28u);\n v4 = 4LL * a2 + 15;\n v5 = (_DWORD *)((char *)v31 - (v4 & 0xFFFFFFFFFFFFF000LL));\n v6 = v4 & 0xFFF0;\n if ( v31 != (_QWORD *)v5 )\n {\n while ( v30 != v5 )\n ;\n }\n v7 = v6 & 0xFFF;\n v8 = alloca(v7);\n if ( v7 )\n *(_QWORD *)((char *)&v30[-2] + v7) = *(_QWORD *)((char *)&v30[-2] + v7);\n if ( a2 <= 0 )\n return (unsigned int)v30[0];\n v9 = a2 - 1;\n v10 = (char *)memcpy(v30, src, 4LL * (unsigned int)a2);\n v11 = v30[0];\n v12 = v10;\n if ( a2 != 1 )\n {\n v13 = 4LL;\n do\n {\n v14 = *(_DWORD *)&src[v13];\n v15 = 0LL;\n do\n {\n if ( v14 > *(_DWORD *)&src[v15] )\n {\n v16 = v14 * *(_DWORD *)&v12[v15];\n if ( *(_DWORD *)&v12[v13] < v16 )\n *(_DWORD *)&v12[v13] = v16;\n }\n v15 += 4LL;\n }\n while ( v15 != v13 );\n v13 = v15 + 4;\n }\n while ( v15 + 4 != 4LL * (unsigned int)a2 );\n if ( (unsigned int)(a2 - 2) <= 2 )\n {\n v22 = 1;\n }\n else\n {\n v17 = v12;\n v18 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v11), 0);\n do\n {\n v19 = _mm_loadu_si128((const __m128i *)(v17 + 4));\n v17 += 16;\n v20 = _mm_cmpgt_epi32(v19, v18);\n v18 = _mm_or_si128(_mm_andnot_si128(v20, v18), _mm_and_si128(v19, v20));\n }\n while ( &v12[16 * (v9 >> 2)] != v17 );\n v21 = _mm_srli_si128(v18, 8);\n v22 = (v9 & 0xFFFFFFFC) + 1;\n v23 = _mm_cmpgt_epi32(v21, v18);\n v24 = _mm_or_si128(_mm_andnot_si128(v23, v18), _mm_and_si128(v21, v23));\n v25 = _mm_srli_si128(v24, 4);\n v26 = _mm_cmpgt_epi32(v25, v24);\n v11 = _mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v26, v24), _mm_and_si128(v25, v26)));\n if ( (v9 & 3) == 0 )\n return (unsigned int)v11;\n }\n v27 = (signed int *)&v12[4 * v22];\n if ( v11 < *v27 )\n v11 = *v27;\n if ( a2 > v22 + 1 )\n {\n if ( v11 < v27[1] )\n v11 = v27[1];\n if ( a2 > v22 + 2 && v11 < v27[2] )\n return (unsigned int)v27[2];\n }\n }\n return (unsigned int)v11;\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\nmov r12d, esi\npush rbx\nmov rbx, rdi\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nmovsxd rax, esi\nmov rcx, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_1342\nloc_132D:\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\ncmp rsp, rcx\njnz short loc_132D\nloc_1342:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_14C9\nloc_1354:\nlea rdi, [rsp+1040h+var_103D]\nmov r14, rdi\nand rdi, 0FFFFFFFFFFFFFFFCh; dest\nshr r14, 2\ntest r12d, r12d\njle loc_14DB\nmov r15d, r12d\nmov rsi, rbx; src\nlea r13d, [r12-1]\nshl r15, 2\nmov rdx, r15; n\ncall _memcpy\nmov r8d, ds:dword_0[r14*4]\nmov rdi, rax\ncmp r12d, 1\njz loc_14A8\nlea r9d, [r12-2]\nmov edx, 4\nnop dword ptr [rax+rax+00h]\nloc_13A8:\nmov ecx, [rbx+rdx]\nxor eax, eax\nnop dword ptr [rax]\nloc_13B0:\ncmp ecx, [rbx+rax]\njle short loc_13C3\nmov esi, [rdi+rax]\nimul esi, ecx\ncmp [rdi+rdx], esi\njge short loc_13C3\nmov [rdi+rdx], esi\nloc_13C3:\nadd rax, 4\ncmp rax, rdx\njnz short loc_13B0\nlea rdx, [rax+4]\ncmp rdx, r15\njnz short loc_13A8\ncmp r9d, 2\njbe loc_14D4\nmov edx, r13d\nmovd xmm3, r8d\nmov rax, rdi\nshr edx, 2\npshufd xmm2, xmm3, 0\nshl rdx, 4\nadd rdx, rdi\nnop dword ptr [rax+00000000h]\nloc_1400:\nmovdqu xmm0, xmmword ptr [rax+4]\nadd rax, 10h\nmovdqa xmm1, xmm0\npcmpgtd xmm1, xmm2\npand xmm0, xmm1\npandn xmm1, xmm2\nmovdqa xmm2, xmm1\npor xmm2, xmm0\ncmp rdx, rax\njnz short loc_1400\nmovdqa xmm1, xmm2\nmov eax, r13d\npsrldq xmm1, 8\nand eax, 0FFFFFFFCh\nmovdqa xmm0, xmm1\nadd eax, 1\nand r13d, 3\npcmpgtd xmm0, xmm2\npand xmm1, xmm0\npandn xmm0, xmm2\npor xmm0, xmm1\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\nmovdqa xmm1, xmm2\npcmpgtd xmm1, xmm0\npand xmm2, xmm1\npandn xmm1, xmm0\npor xmm1, xmm2\nmovd r8d, xmm1\njz short loc_14A8\nloc_1474:\nmovsxd rdx, eax\nlea rdx, [rdi+rdx*4]\nmov ecx, [rdx]\ncmp r8d, ecx\ncmovl r8d, ecx\nlea ecx, [rax+1]\ncmp r12d, ecx\njle short loc_14A8\nmov ecx, [rdx+4]\ncmp r8d, ecx\ncmovl r8d, ecx\nadd eax, 2\ncmp r12d, eax\njle short loc_14A8\nmov eax, [rdx+8]\ncmp r8d, eax\ncmovl r8d, eax\nloc_14A8:\nmov rax, [rbp+var_38]\nsub rax, fs:28h\njnz short loc_14E5\nlea rsp, [rbp-28h]\nmov eax, r8d\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_14C9:\nor [rsp+rdx+1040h+var_1048], 0\njmp loc_1354\nloc_14D4:\nmov eax, 1\njmp short loc_1474\nloc_14DB:\nmov r8d, ds:dword_0[r14*4]\njmp short loc_14A8\nloc_14E5:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12E0(char *src, int a2)\n{\n __int64 v4; // rdx\n _DWORD *v5; // rcx\n __int16 v6; // dx\n signed __int64 v7; // rdx\n void *v8; // rsp\n unsigned int v9; // r13d\n char *v10; // rax\n signed int v11; // r8d\n char *v12; // rdi\n __int64 v13; // rdx\n int v14; // ecx\n __int64 v15; // rax\n int v16; // esi\n char *v17; // rax\n __m128i v18; // xmm2\n __m128i v19; // xmm0\n __m128i v20; // xmm1\n __m128i v21; // xmm1\n signed int v22; // eax\n __m128i v23; // xmm0\n __m128i v24; // xmm0\n __m128i v25; // xmm2\n __m128i v26; // xmm1\n signed int *v27; // rdx\n _DWORD v30[1022]; // [rsp+8h] [rbp-1040h] BYREF\n _QWORD v31[8]; // [rsp+1008h] [rbp-40h] BYREF\n\n v31[1] = __readfsqword(0x28u);\n v4 = 4LL * a2 + 15;\n v5 = (_DWORD *)((char *)v31 - (v4 & 0xFFFFFFFFFFFFF000LL));\n v6 = v4 & 0xFFF0;\n if ( v31 != (_QWORD *)v5 )\n {\n while ( v30 != v5 )\n ;\n }\n v7 = v6 & 0xFFF;\n v8 = alloca(v7);\n if ( v7 )\n *(_QWORD *)((char *)&v30[-2] + v7) = *(_QWORD *)((char *)&v30[-2] + v7);\n if ( a2 <= 0 )\n return (unsigned int)v30[0];\n v9 = a2 - 1;\n v10 = (char *)memcpy(v30, src, 4LL * (unsigned int)a2);\n v11 = v30[0];\n v12 = v10;\n if ( a2 != 1 )\n {\n v13 = 4LL;\n do\n {\n v14 = *(_DWORD *)&src[v13];\n v15 = 0LL;\n do\n {\n if ( v14 > *(_DWORD *)&src[v15] )\n {\n v16 = v14 * *(_DWORD *)&v12[v15];\n if ( *(_DWORD *)&v12[v13] < v16 )\n *(_DWORD *)&v12[v13] = v16;\n }\n v15 += 4LL;\n }\n while ( v15 != v13 );\n v13 = v15 + 4;\n }\n while ( v15 + 4 != 4LL * (unsigned int)a2 );\n if ( (unsigned int)(a2 - 2) <= 2 )\n {\n v22 = 1;\n }\n else\n {\n v17 = v12;\n v18 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v11), 0);\n do\n {\n v19 = _mm_loadu_si128((const __m128i *)(v17 + 4));\n v17 += 16;\n v20 = _mm_cmpgt_epi32(v19, v18);\n v18 = _mm_or_si128(_mm_andnot_si128(v20, v18), _mm_and_si128(v19, v20));\n }\n while ( &v12[16 * (v9 >> 2)] != v17 );\n v21 = _mm_srli_si128(v18, 8);\n v22 = (v9 & 0xFFFFFFFC) + 1;\n v23 = _mm_cmpgt_epi32(v21, v18);\n v24 = _mm_or_si128(_mm_andnot_si128(v23, v18), _mm_and_si128(v21, v23));\n v25 = _mm_srli_si128(v24, 4);\n v26 = _mm_cmpgt_epi32(v25, v24);\n v11 = _mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v26, v24), _mm_and_si128(v25, v26)));\n if ( (v9 & 3) == 0 )\n return (unsigned int)v11;\n }\n v27 = (signed int *)&v12[4 * v22];\n if ( v11 < *v27 )\n v11 = *v27;\n if ( a2 > v22 + 1 )\n {\n if ( v11 < v27[1] )\n v11 = v27[1];\n if ( a2 > v22 + 2 && v11 < v27[2] )\n return (unsigned int)v27[2];\n }\n }\n return (unsigned int)v11;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12E0(char *src, int a2) {\n long long v4;\n uint32_t *v5;\n short v6;\n signed long long v7;\n void *v8;\n unsigned int v9;\n char *v10;\n signed int v11;\n char *v12;\n long long v13;\n int v14;\n long long v15;\n int v16;\n char *v17;\n __m128i v18;\n __m128i v19;\n __m128i v20;\n __m128i v21;\n signed int v22;\n __m128i v23;\n __m128i v24;\n __m128i v25;\n __m128i v26;\n signed int *v27;\n uint32_t v30[1022];\n uint64_t v31[8];\n v31[1] = __readfsqword(40u);\n v4 = 4LL * a2 + 15;\n v5 = (uint32_t *)((char *)v31 - (v4 & 18446744073709547520LL));\n v6 = v4 & 65520;\n if (v31 != (uint64_t *)v5) {\n while (v30 != v5)\n ;\n }\n v7 = v6 & 4095;\n v8 = alloca(v7);\n if (v7)\n *(uint64_t *)((char *)&v30[-2] + v7) = *(uint64_t *)((char *)&v30[-2] + v7);\n if (a2 <= 0) return (unsigned int)v30[0];\n v9 = a2 - 1;\n v10 = (char *)memcpy(v30, src, 4LL * (unsigned int)a2);\n v11 = v30[0];\n v12 = v10;\n if (a2 != 1) {\n v13 = 4LL;\n do {\n v14 = *(uint32_t *)&src[v13];\n v15 = 0LL;\n do {\n if (v14 > *(uint32_t *)&src[v15]) {\n v16 = v14 * *(uint32_t *)&v12[v15];\n if (*(uint32_t *)&v12[v13] < v16) *(uint32_t *)&v12[v13] = v16;\n }\n v15 += 4LL;\n } while (v15 != v13);\n v13 = v15 + 4;\n } while (v15 + 4 != 4LL * (unsigned int)a2);\n if ((unsigned int)(a2 - 2) <= 2) {\n v22 = 1;\n } else {\n v17 = v12;\n v18 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v11), 0);\n do {\n v19 = _mm_loadu_si128((const __m128i *)(v17 + 4));\n v17 += 16;\n v20 = _mm_cmpgt_epi32(v19, v18);\n v18 = _mm_or_si128(_mm_andnot_si128(v20, v18), _mm_and_si128(v19, v20));\n } while (&v12[16 * (v9 >> 2)] != v17);\n v21 = _mm_srli_si128(v18, 8);\n v22 = (v9 & 4294967292) + 1;\n v23 = _mm_cmpgt_epi32(v21, v18);\n v24 = _mm_or_si128(_mm_andnot_si128(v23, v18), _mm_and_si128(v21, v23));\n v25 = _mm_srli_si128(v24, 4);\n v26 = _mm_cmpgt_epi32(v25, v24);\n v11 = _mm_cvtsi128_si32(\n _mm_or_si128(_mm_andnot_si128(v26, v24), _mm_and_si128(v25, v26)));\n if ((v9 & 3) == 0) return (unsigned int)v11;\n }\n v27 = (signed int *)&v12[4 * v22];\n if (v11 < *v27) v11 = *v27;\n if (a2 > v22 + 1) {\n if (v11 < v27[1]) v11 = v27[1];\n if (a2 > v22 + 2 && v11 < v27[2]) return (unsigned int)v27[2];\n }\n }\n return (unsigned int)v11;\n}", + "ida_pseudo_norm": "long long func0(char *src, int a2) {\n long long v4;\n uint32_t *v5;\n short v6;\n signed long long v7;\n void *v8;\n unsigned int v9;\n char *v10;\n signed int v11;\n char *v12;\n long long v13;\n int v14;\n long long v15;\n int v16;\n char *v17;\n __m128i v18;\n __m128i v19;\n __m128i v20;\n __m128i v21;\n signed int v22;\n __m128i v23;\n __m128i v24;\n __m128i v25;\n __m128i v26;\n signed int *v27;\n uint32_t v30[1022];\n uint64_t v31[8];\n v31[1] = __readfsqword(40u);\n v4 = 4LL * a2 + 15;\n v5 = (uint32_t *)((char *)v31 - (v4 & 18446744073709547520LL));\n v6 = v4 & 65520;\n if (v31 != (uint64_t *)v5) {\n while (v30 != v5)\n ;\n }\n v7 = v6 & 4095;\n v8 = alloca(v7);\n if (v7)\n *(uint64_t *)((char *)&v30[-2] + v7) = *(uint64_t *)((char *)&v30[-2] + v7);\n if (a2 <= 0) return (unsigned int)v30[0];\n v9 = a2 - 1;\n v10 = (char *)memcpy(v30, src, 4LL * (unsigned int)a2);\n v11 = v30[0];\n v12 = v10;\n if (a2 != 1) {\n v13 = 4LL;\n do {\n v14 = *(uint32_t *)&src[v13];\n v15 = 0LL;\n do {\n if (v14 > *(uint32_t *)&src[v15]) {\n v16 = v14 * *(uint32_t *)&v12[v15];\n if (*(uint32_t *)&v12[v13] < v16) *(uint32_t *)&v12[v13] = v16;\n }\n v15 += 4LL;\n } while (v15 != v13);\n v13 = v15 + 4;\n } while (v15 + 4 != 4LL * (unsigned int)a2);\n if ((unsigned int)(a2 - 2) <= 2) {\n v22 = 1;\n } else {\n v17 = v12;\n v18 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v11), 0);\n do {\n v19 = _mm_loadu_si128((const __m128i *)(v17 + 4));\n v17 += 16;\n v20 = _mm_cmpgt_epi32(v19, v18);\n v18 = _mm_or_si128(_mm_andnot_si128(v20, v18), _mm_and_si128(v19, v20));\n } while (&v12[16 * (v9 >> 2)] != v17);\n v21 = _mm_srli_si128(v18, 8);\n v22 = (v9 & 4294967292) + 1;\n v23 = _mm_cmpgt_epi32(v21, v18);\n v24 = _mm_or_si128(_mm_andnot_si128(v23, v18), _mm_and_si128(v21, v23));\n v25 = _mm_srli_si128(v24, 4);\n v26 = _mm_cmpgt_epi32(v25, v24);\n v11 = _mm_cvtsi128_si32(\n _mm_or_si128(_mm_andnot_si128(v26, v24), _mm_and_si128(v25, v26)));\n if ((v9 & 3) == 0) return (unsigned int)v11;\n }\n v27 = (signed int *)&v12[4 * v22];\n if (v11 < *v27) v11 = *v27;\n if (a2 > v22 + 1) {\n if (v11 < v27[1]) v11 = v27[1];\n if (a2 > v22 + 2 && v11 < v27[2]) return (unsigned int)v27[2];\n }\n }\n return (unsigned int)v11;\n}" + }, + { + "index": 469, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n\n\n", + "func": "int func0(int price[], int n, int k) {\n int final_profit[k + 1][n];\n for (int i = 0; i <= k; i++) {\n for (int j = 0; j < n; j++) {\n if (i == 0 || j == 0) {\n final_profit[i][j] = 0;\n } else {\n int max_so_far = 0;\n for (int x = 0; x < j; x++) {\n int curr_price = price[j] - price[x] + final_profit[i - 1][x];\n if (max_so_far < curr_price) {\n max_so_far = curr_price;\n }\n }\n final_profit[i][j] = (final_profit[i][j - 1] > max_so_far)\n ? final_profit[i][j - 1]\n : max_so_far;\n }\n }\n }\n return final_profit[k][n - 1];\n}", + "test": "int main() {\n\n int prices1[] = {1, 5, 2, 3, 7, 6, 4, 5};\n\n int n1 = sizeof(prices1) / sizeof(prices1[0]);\n\n assert(func0(prices1, n1, 3) == 10);\n\n\n\n int prices2[] = {2, 4, 7, 5, 4, 3, 5};\n\n int n2 = sizeof(prices2) / sizeof(prices2[0]);\n\n assert(func0(prices2, n2, 2) == 7);\n\n\n\n int prices3[] = {10, 6, 8, 4, 2};\n\n int n3 = sizeof(prices3) / sizeof(prices3[0]);\n\n assert(func0(prices3, n3, 2) == 2);\n\n\n\n printf(\"All tests passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0x78,%rsp\nmov %rdi,-0x78(%rbp)\nmov %esi,-0x7c(%rbp)\nmov %edx,-0x80(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nmov %rsp,%rax\nmov %rax,-0x98(%rbp)\nmov -0x7c(%rbp),%ecx\nmov -0x80(%rbp),%eax\nlea 0x1(%rax),%edi\nmovslq %ecx,%rax\nsub $0x1,%rax\nmov %rax,-0x50(%rbp)\nmovslq %ecx,%rax\nmov %rax,-0x90(%rbp)\nmovq $0x0,-0x88(%rbp)\nmovslq %ecx,%rax\nlea 0x0(,%rax,4),%rsi\nmovslq %edi,%rax\nsub $0x1,%rax\nmov %rax,-0x48(%rbp)\nmovslq %ecx,%rax\nmov %rax,%r14\nmov $0x0,%r15d\nmovslq %edi,%rax\nmov %rax,%r12\nmov $0x0,%r13d\nmov %r15,%rdx\nimul %r12,%rdx\nmov %r13,%rax\nimul %r14,%rax\nlea (%rdx,%rax,1),%rbx\nmov %r14,%rax\nmul %r12\nadd %rdx,%rbx\nmov %rbx,%rdx\nmovslq %ecx,%rax\nmov %rax,%r10\nmov $0x0,%r11d\nmovslq %edi,%rax\nmov %rax,%r8\nmov $0x0,%r9d\nmov %r11,%rdx\nimul %r8,%rdx\nmov %r9,%rax\nimul %r10,%rax\nlea (%rdx,%rax,1),%rbx\nmov %r10,%rax\nmul %r8\nlea (%rbx,%rdx,1),%r8\nmov %r8,%rdx\nmovslq %ecx,%rdx\nmovslq %edi,%rax\nimul %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%ebx\nmov $0x0,%edx\ndiv %rbx\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rbx\nsub %rdx,%rbx\nmov %rbx,%rdx\ncmp %rdx,%rsp\nje 12c6 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 12af \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 12f0 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x40(%rbp)\nmovl $0x0,-0x58(%rbp)\njmpq 1437 \nmovl $0x0,-0x5c(%rbp)\njmpq 1427 \ncmpl $0x0,-0x58(%rbp)\nje 1327 \ncmpl $0x0,-0x5c(%rbp)\njne 1351 \nmov %rsi,%rdi\nshr $0x2,%rdi\nmov -0x40(%rbp),%rax\nmov -0x5c(%rbp),%edx\nmovslq %edx,%rcx\nmov -0x58(%rbp),%edx\nmovslq %edx,%rdx\nimul %rdi,%rdx\nadd %rcx,%rdx\nmovl $0x0,(%rax,%rdx,4)\njmpq 1423 \nmovl $0x0,-0x60(%rbp)\nmovl $0x0,-0x64(%rbp)\njmp 13cd \nmov -0x5c(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x78(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x64(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x78(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\nmov %edx,%edi\nsub %eax,%edi\nmov %rsi,%r8\nshr $0x2,%r8\nmov -0x58(%rbp),%eax\nlea -0x1(%rax),%r9d\nmov -0x40(%rbp),%rax\nmov -0x64(%rbp),%edx\nmovslq %edx,%rcx\nmovslq %r9d,%rdx\nimul %r8,%rdx\nadd %rcx,%rdx\nmov (%rax,%rdx,4),%eax\nadd %edi,%eax\nmov %eax,-0x54(%rbp)\nmov -0x60(%rbp),%eax\ncmp -0x54(%rbp),%eax\njge 13c9 \nmov -0x54(%rbp),%eax\nmov %eax,-0x60(%rbp)\naddl $0x1,-0x64(%rbp)\nmov -0x64(%rbp),%eax\ncmp -0x5c(%rbp),%eax\njl 1361 \nmov %rsi,%rdi\nshr $0x2,%rdi\nmov -0x5c(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x40(%rbp),%rax\nmovslq %edx,%rcx\nmov -0x58(%rbp),%edx\nmovslq %edx,%rdx\nimul %rdi,%rdx\nadd %rcx,%rdx\nmov (%rax,%rdx,4),%eax\nmov %rsi,%r8\nshr $0x2,%r8\ncmp %eax,-0x60(%rbp)\ncmovge -0x60(%rbp),%eax\nmov %eax,%edx\nmov -0x40(%rbp),%rax\nmov -0x5c(%rbp),%ecx\nmovslq %ecx,%rdi\nmov -0x58(%rbp),%ecx\nmovslq %ecx,%rcx\nimul %r8,%rcx\nadd %rdi,%rcx\nmov %edx,(%rax,%rcx,4)\naddl $0x1,-0x5c(%rbp)\nmov -0x5c(%rbp),%eax\ncmp -0x7c(%rbp),%eax\njl 131b \naddl $0x1,-0x58(%rbp)\nmov -0x58(%rbp),%eax\ncmp -0x80(%rbp),%eax\njle 130f \nshr $0x2,%rsi\nmov -0x7c(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x40(%rbp),%rax\nmovslq %edx,%rcx\nmov -0x80(%rbp),%edx\nmovslq %edx,%rdx\nimul %rsi,%rdx\nadd %rcx,%rdx\nmov (%rax,%rdx,4),%eax\nmov -0x98(%rbp),%rsp\nmov -0x38(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 147f \ncallq 1080 <__stack_chk_fail@plt>\nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 58h\nmov [rbp+var_58], rdi\nmov [rbp+var_5C], esi\nmov [rbp+var_60], edx\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov rax, rsp\nmov r11, rax\nmov esi, [rbp+var_5C]\nmov eax, [rbp+var_60]\nlea r8d, [rax+1]\nmovsxd rax, esi\nsub rax, 1\nmov [rbp+var_30], rax\nmovsxd rax, esi\nlea rdi, ds:0[rax*4]\nmovsxd rax, r8d\nsub rax, 1\nmov [rbp+var_28], rax\nmovsxd rax, esi\nmov rcx, rax\nmov ebx, 0\nmovsxd rax, r8d\nmov rax, rax\nmov edx, 0\nmov r10, rbx\nimul r10, rax\nmov r9, rdx\nimul r9, rcx\nadd r9, r10\nmul rcx\nlea rcx, [r9+rdx]\nmov rdx, rcx\nmovsxd rax, esi\nmov rcx, rax\nmov ebx, 0\nmovsxd rax, r8d\nmov rax, rax\nmov edx, 0\nmov r10, rbx\nimul r10, rax\nmov r9, rdx\nimul r9, rcx\nadd r9, r10\nmul rcx\nlea rcx, [r9+rdx]\nmov rdx, rcx\nmovsxd rdx, esi\nmovsxd rax, r8d\nimul rax, rdx\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov ebx, 10h\nmov edx, 0\ndiv rbx\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_1281:\ncmp rsp, rdx\njz short loc_1298\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\njmp short loc_1281\nloc_1298:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_12C2\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_12C2:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_20], rax\nmov [rbp+var_44], 0\njmp loc_140A\nloc_12E1:\nmov [rbp+var_40], 0\njmp loc_13FA\nloc_12ED:\ncmp [rbp+var_44], 0\njz short loc_12F9\ncmp [rbp+var_40], 0\njnz short loc_1323\nloc_12F9:\nmov rsi, rdi\nshr rsi, 2\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_40]\nmovsxd rcx, edx\nmov edx, [rbp+var_44]\nmovsxd rdx, edx\nimul rdx, rsi\nadd rdx, rcx\nmov dword ptr [rax+rdx*4], 0\njmp loc_13F6\nloc_1323:\nmov [rbp+var_3C], 0\nmov [rbp+var_38], 0\njmp short loc_13A1\nloc_1333:\nmov eax, [rbp+var_40]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_38]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rcx\nmov eax, [rax]\nsub edx, eax\nmov r8d, edx\nmov rsi, rdi\nshr rsi, 2\nmov eax, [rbp+var_44]\nlea r9d, [rax-1]\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_38]\nmovsxd rcx, edx\nmovsxd rdx, r9d\nimul rdx, rsi\nadd rdx, rcx\nmov eax, [rax+rdx*4]\nadd eax, r8d\nmov [rbp+var_34], eax\nmov eax, [rbp+var_3C]\ncmp eax, [rbp+var_34]\njge short loc_139D\nmov eax, [rbp+var_34]\nmov [rbp+var_3C], eax\nloc_139D:\nadd [rbp+var_38], 1\nloc_13A1:\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_40]\njl short loc_1333\nmov rsi, rdi\nshr rsi, 2\nmov eax, [rbp+var_40]\nlea edx, [rax-1]\nmov rax, [rbp+var_20]\nmovsxd rcx, edx\nmov edx, [rbp+var_44]\nmovsxd rdx, edx\nimul rdx, rsi\nadd rdx, rcx\nmov edx, [rax+rdx*4]\nmov r8, rdi\nshr r8, 2\nmov eax, [rbp+var_3C]\ncmp edx, eax\ncmovl edx, eax\nmov rax, [rbp+var_20]\nmov ecx, [rbp+var_40]\nmovsxd rsi, ecx\nmov ecx, [rbp+var_44]\nmovsxd rcx, ecx\nimul rcx, r8\nadd rcx, rsi\nmov [rax+rcx*4], edx\nloc_13F6:\nadd [rbp+var_40], 1\nloc_13FA:\nmov eax, [rbp+var_40]\ncmp eax, [rbp+var_5C]\njl loc_12ED\nadd [rbp+var_44], 1\nloc_140A:\nmov eax, [rbp+var_44]\ncmp eax, [rbp+var_60]\njle loc_12E1\nshr rdi, 2\nmov rsi, rdi\nmov eax, [rbp+var_5C]\nlea edx, [rax-1]\nmov rax, [rbp+var_20]\nmovsxd rcx, edx\nmov edx, [rbp+var_60]\nmovsxd rdx, edx\nimul rdx, rsi\nadd rdx, rcx\nmov eax, [rax+rdx*4]\nmov rsp, r11\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njz short loc_1451\ncall ___stack_chk_fail\nloc_1451:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n unsigned __int64 v3; // rdi\n unsigned __int64 v4; // rax\n void *v5; // rsp\n int v6; // edx\n int v8; // [rsp+8h] [rbp-60h] BYREF\n int v9; // [rsp+Ch] [rbp-5Ch]\n __int64 v10; // [rsp+10h] [rbp-58h]\n int i; // [rsp+24h] [rbp-44h]\n int j; // [rsp+28h] [rbp-40h]\n int v13; // [rsp+2Ch] [rbp-3Ch]\n int k; // [rsp+30h] [rbp-38h]\n int v15; // [rsp+34h] [rbp-34h]\n __int64 v16; // [rsp+38h] [rbp-30h]\n __int64 v17; // [rsp+40h] [rbp-28h]\n int *v18; // [rsp+48h] [rbp-20h]\n unsigned __int64 v19; // [rsp+50h] [rbp-18h]\n\n v10 = a1;\n v9 = a2;\n v8 = a3;\n v19 = __readfsqword(0x28u);\n v16 = a2 - 1LL;\n v3 = 4LL * a2;\n v17 = a3 + 1 - 1LL;\n v4 = 16 * ((4 * a2 * (__int64)(a3 + 1) + 15) / 0x10uLL);\n while ( &v8 != (int *)((char *)&v8 - (v4 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v5 = alloca(v4 & 0xFFF);\n if ( (v4 & 0xFFF) != 0 )\n *(_QWORD *)((char *)&v8 + (v4 & 0xFFF) - 8) = *(_QWORD *)((char *)&v8 + (v4 & 0xFFF) - 8);\n v18 = &v8;\n for ( i = 0; i <= v8; ++i )\n {\n for ( j = 0; j < v9; ++j )\n {\n if ( i && j )\n {\n v13 = 0;\n for ( k = 0; k < j; ++k )\n {\n v15 = *(_DWORD *)(4LL * j + v10) - *(_DWORD *)(4LL * k + v10) + v18[k + (v3 >> 2) * (i - 1)];\n if ( v13 < v15 )\n v13 = v15;\n }\n v6 = v18[j - 1 + (v3 >> 2) * i];\n if ( v6 < v13 )\n v6 = v13;\n v18[j + (v3 >> 2) * i] = v6;\n }\n else\n {\n v18[j + (v3 >> 2) * i] = 0;\n }\n }\n }\n return (unsigned int)v18[v9 - 1 + (v3 >> 2) * v8];\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 58h\nmov [rbp+var_58], rdi\nmov [rbp+var_5C], esi\nmov [rbp+var_60], edx\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov rax, rsp\nmov r11, rax\nmov esi, [rbp+var_5C]\nmov eax, [rbp+var_60]\nlea r8d, [rax+1]\nmovsxd rax, esi\nsub rax, 1\nmov [rbp+var_30], rax\nmovsxd rax, esi\nlea rdi, ds:0[rax*4]\nmovsxd rax, r8d\nsub rax, 1\nmov [rbp+var_28], rax\nmovsxd rax, esi\nmov rcx, rax\nmov ebx, 0\nmovsxd rax, r8d\nmov rax, rax\nmov edx, 0\nmov r10, rbx\nimul r10, rax\nmov r9, rdx\nimul r9, rcx\nadd r9, r10\nmul rcx\nlea rcx, [r9+rdx]\nmov rdx, rcx\nmovsxd rax, esi\nmov rcx, rax\nmov ebx, 0\nmovsxd rax, r8d\nmov rax, rax\nmov edx, 0\nmov r10, rbx\nimul r10, rax\nmov r9, rdx\nimul r9, rcx\nadd r9, r10\nmul rcx\nlea rcx, [r9+rdx]\nmov rdx, rcx\nmovsxd rdx, esi\nmovsxd rax, r8d\nimul rax, rdx\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov ebx, 10h\nmov edx, 0\ndiv rbx\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_1281:\ncmp rsp, rdx\njz short loc_1298\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\njmp short loc_1281\nloc_1298:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_12C2\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_12C2:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_20], rax\nmov [rbp+var_44], 0\njmp loc_140A\nloc_12E1:\nmov [rbp+var_40], 0\njmp loc_13FA\nloc_12ED:\ncmp [rbp+var_44], 0\njz short loc_12F9\ncmp [rbp+var_40], 0\njnz short loc_1323\nloc_12F9:\nmov rsi, rdi\nshr rsi, 2\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_40]\nmovsxd rcx, edx\nmov edx, [rbp+var_44]\nmovsxd rdx, edx\nimul rdx, rsi\nadd rdx, rcx\nmov dword ptr [rax+rdx*4], 0\njmp loc_13F6\nloc_1323:\nmov [rbp+var_3C], 0\nmov [rbp+var_38], 0\njmp short loc_13A1\nloc_1333:\nmov eax, [rbp+var_40]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_38]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rcx\nmov eax, [rax]\nsub edx, eax\nmov r8d, edx\nmov rsi, rdi\nshr rsi, 2\nmov eax, [rbp+var_44]\nlea r9d, [rax-1]\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_38]\nmovsxd rcx, edx\nmovsxd rdx, r9d\nimul rdx, rsi\nadd rdx, rcx\nmov eax, [rax+rdx*4]\nadd eax, r8d\nmov [rbp+var_34], eax\nmov eax, [rbp+var_3C]\ncmp eax, [rbp+var_34]\njge short loc_139D\nmov eax, [rbp+var_34]\nmov [rbp+var_3C], eax\nloc_139D:\nadd [rbp+var_38], 1\nloc_13A1:\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_40]\njl short loc_1333\nmov rsi, rdi\nshr rsi, 2\nmov eax, [rbp+var_40]\nlea edx, [rax-1]\nmov rax, [rbp+var_20]\nmovsxd rcx, edx\nmov edx, [rbp+var_44]\nmovsxd rdx, edx\nimul rdx, rsi\nadd rdx, rcx\nmov edx, [rax+rdx*4]\nmov r8, rdi\nshr r8, 2\nmov eax, [rbp+var_3C]\ncmp edx, eax\ncmovl edx, eax\nmov rax, [rbp+var_20]\nmov ecx, [rbp+var_40]\nmovsxd rsi, ecx\nmov ecx, [rbp+var_44]\nmovsxd rcx, ecx\nimul rcx, r8\nadd rcx, rsi\nmov [rax+rcx*4], edx\nloc_13F6:\nadd [rbp+var_40], 1\nloc_13FA:\nmov eax, [rbp+var_40]\ncmp eax, [rbp+var_5C]\njl loc_12ED\nadd [rbp+var_44], 1\nloc_140A:\nmov eax, [rbp+var_44]\ncmp eax, [rbp+var_60]\njle loc_12E1\nshr rdi, 2\nmov rsi, rdi\nmov eax, [rbp+var_5C]\nlea edx, [rax-1]\nmov rax, [rbp+var_20]\nmovsxd rcx, edx\nmov edx, [rbp+var_60]\nmovsxd rdx, edx\nimul rdx, rsi\nadd rdx, rcx\nmov eax, [rax+rdx*4]\nmov rsp, r11\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njz short loc_1451\ncall ___stack_chk_fail\nloc_1451:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2, int a3)\n{\n unsigned __int64 v3; // rdi\n unsigned __int64 v4; // rax\n void *v5; // rsp\n int v6; // edx\n int v8; // [rsp+8h] [rbp-60h] BYREF\n int v9; // [rsp+Ch] [rbp-5Ch]\n __int64 v10; // [rsp+10h] [rbp-58h]\n int i; // [rsp+24h] [rbp-44h]\n int j; // [rsp+28h] [rbp-40h]\n int v13; // [rsp+2Ch] [rbp-3Ch]\n int k; // [rsp+30h] [rbp-38h]\n int v15; // [rsp+34h] [rbp-34h]\n __int64 v16; // [rsp+38h] [rbp-30h]\n __int64 v17; // [rsp+40h] [rbp-28h]\n int *v18; // [rsp+48h] [rbp-20h]\n unsigned __int64 v19; // [rsp+50h] [rbp-18h]\n\n v10 = a1;\n v9 = a2;\n v8 = a3;\n v19 = __readfsqword(0x28u);\n v16 = a2 - 1LL;\n v3 = 4LL * a2;\n v17 = a3 + 1 - 1LL;\n v4 = 16 * ((4 * a2 * (__int64)(a3 + 1) + 15) / 0x10uLL);\n while ( &v8 != (int *)((char *)&v8 - (v4 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v5 = alloca(v4 & 0xFFF);\n if ( (v4 & 0xFFF) != 0 )\n *(_QWORD *)((char *)&v8 + (v4 & 0xFFF) - 8) = *(_QWORD *)((char *)&v8 + (v4 & 0xFFF) - 8);\n v18 = &v8;\n for ( i = 0; i <= v8; ++i )\n {\n for ( j = 0; j < v9; ++j )\n {\n if ( i && j )\n {\n v13 = 0;\n for ( k = 0; k < j; ++k )\n {\n v15 = *(_DWORD *)(4LL * j + v10) - *(_DWORD *)(4LL * k + v10) + v18[k + (v3 >> 2) * (i - 1)];\n if ( v13 < v15 )\n v13 = v15;\n }\n v6 = v18[j - 1 + (v3 >> 2) * i];\n if ( v6 < v13 )\n v6 = v13;\n v18[j + (v3 >> 2) * i] = v6;\n }\n else\n {\n v18[j + (v3 >> 2) * i] = 0;\n }\n }\n }\n return (unsigned int)v18[v9 - 1 + (v3 >> 2) * v8];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2, int a3) {\n unsigned long long v3;\n unsigned long long v4;\n void *v5;\n int v6;\n int v8;\n int v9;\n long long v10;\n int i;\n int j;\n int v13;\n int k;\n int v15;\n long long v16;\n long long v17;\n int *v18;\n unsigned long long v19;\n v10 = a1;\n v9 = a2;\n v8 = a3;\n v19 = __readfsqword(40u);\n v16 = a2 - 1LL;\n v3 = 4LL * a2;\n v17 = a3 + 1 - 1LL;\n v4 = 16 * ((4 * a2 * (long long)(a3 + 1) + 15) / 16uLL);\n while (&v8 != (int *)((char *)&v8 - (v4 & 18446744073709547520LL)))\n ;\n v5 = alloca(v4 & 4095);\n if ((v4 & 4095) != 0)\n *(uint64_t *)((char *)&v8 + (v4 & 4095) - 8) =\n *(uint64_t *)((char *)&v8 + (v4 & 4095) - 8);\n v18 = &v8;\n for (i = 0; i <= v8; ++i) {\n for (j = 0; j < v9; ++j) {\n if (i && j) {\n v13 = 0;\n for (k = 0; k < j; ++k) {\n v15 = *(uint32_t *)(4LL * j + v10) - *(uint32_t *)(4LL * k + v10) +\n v18[k + (v3 >> 2) * (i - 1)];\n if (v13 < v15) v13 = v15;\n }\n v6 = v18[j - 1 + (v3 >> 2) * i];\n if (v6 < v13) v6 = v13;\n v18[j + (v3 >> 2) * i] = v6;\n } else {\n v18[j + (v3 >> 2) * i] = 0;\n }\n }\n }\n return (unsigned int)v18[v9 - 1 + (v3 >> 2) * v8];\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n unsigned long long v3;\n unsigned long long v4;\n void *v5;\n int v6;\n int v8;\n int v9;\n long long v10;\n int i;\n int j;\n int v13;\n int k;\n int v15;\n long long v16;\n long long v17;\n int *v18;\n unsigned long long v19;\n v10 = a1;\n v9 = a2;\n v8 = a3;\n v19 = __readfsqword(40u);\n v16 = a2 - 1LL;\n v3 = 4LL * a2;\n v17 = a3 + 1 - 1LL;\n v4 = 16 * ((4 * a2 * (long long)(a3 + 1) + 15) / 16uLL);\n while (&v8 != (int *)((char *)&v8 - (v4 & 18446744073709547520LL)))\n ;\n v5 = alloca(v4 & 4095);\n if ((v4 & 4095) != 0)\n *(uint64_t *)((char *)&v8 + (v4 & 4095) - 8) =\n *(uint64_t *)((char *)&v8 + (v4 & 4095) - 8);\n v18 = &v8;\n for (i = 0; i <= v8; ++i) {\n for (j = 0; j < v9; ++j) {\n if (i && j) {\n v13 = 0;\n for (k = 0; k < j; ++k) {\n v15 = *(uint32_t *)(4LL * j + v10) - *(uint32_t *)(4LL * k + v10) +\n v18[k + (v3 >> 2) * (i - 1)];\n if (v13 < v15) v13 = v15;\n }\n v6 = v18[j - 1 + (v3 >> 2) * i];\n if (v6 < v13) v6 = v13;\n v18[j + (v3 >> 2) * i] = v6;\n } else {\n v18[j + (v3 >> 2) * i] = 0;\n }\n }\n }\n return (unsigned int)v18[v9 - 1 + (v3 >> 2) * v8];\n}" + }, + { + "index": 469, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n\n\n", + "func": "int func0(int price[], int n, int k) {\n int final_profit[k + 1][n];\n for (int i = 0; i <= k; i++) {\n for (int j = 0; j < n; j++) {\n if (i == 0 || j == 0) {\n final_profit[i][j] = 0;\n } else {\n int max_so_far = 0;\n for (int x = 0; x < j; x++) {\n int curr_price = price[j] - price[x] + final_profit[i - 1][x];\n if (max_so_far < curr_price) {\n max_so_far = curr_price;\n }\n }\n final_profit[i][j] = (final_profit[i][j - 1] > max_so_far)\n ? final_profit[i][j - 1]\n : max_so_far;\n }\n }\n }\n return final_profit[k][n - 1];\n}", + "test": "int main() {\n\n int prices1[] = {1, 5, 2, 3, 7, 6, 4, 5};\n\n int n1 = sizeof(prices1) / sizeof(prices1[0]);\n\n assert(func0(prices1, n1, 3) == 10);\n\n\n\n int prices2[] = {2, 4, 7, 5, 4, 3, 5};\n\n int n2 = sizeof(prices2) / sizeof(prices2[0]);\n\n assert(func0(prices2, n2, 2) == 7);\n\n\n\n int prices3[] = {10, 6, 8, 4, 2};\n\n int n3 = sizeof(prices3) / sizeof(prices3[0]);\n\n assert(func0(prices3, n3, 2) == 2);\n\n\n\n printf(\"All tests passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0x28,%rsp\nmov %esi,%r14d\nmov %edx,%eax\nmov %edx,-0x48(%rbp)\nmov %fs:0x28,%rbx\nmov %rbx,-0x38(%rbp)\nxor %ebx,%ebx\nmovslq %esi,%rdx\nlea 0x0(,%rdx,4),%r15\nadd $0x1,%eax\ncltq\nimul %rdx,%rax\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffffff0,%rdx\nand $0xfffffffffffff000,%rax\nmov %rsp,%rbx\nsub %rax,%rbx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 11fe \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11e7 \nmov %rdx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 1214 \norq $0x0,-0x8(%rsp,%rax,1)\nmov %rsp,%rbx\nmov %rbx,-0x50(%rbp)\nmov -0x48(%rbp),%eax\ntest %eax,%eax\njs 12c2 \nmov %rbx,%r13\nmov %rbx,%r8\nsub %r15,%r8\nadd $0x1,%eax\nmov %eax,-0x44(%rbp)\nmov $0x0,%r11d\nlea -0x1(%r14),%r12d\njmp 12b6 \nmovl $0x0,0x0(%r13,%rsi,4)\nlea 0x1(%rsi),%rax\ncmp %r12,%rsi\nje 12a3 \nmov %rax,%rsi\ntest %r11d,%r11d\nje 1241 \ntest %esi,%esi\nje 1241 \nmov $0x0,%ecx\ntest %esi,%esi\njle 1295 \nmov (%rdi,%rsi,4),%r10d\nlea -0x1(%rsi),%r9d\nmov $0x0,%eax\nmov $0x0,%ecx\nmov %r10d,%edx\nsub (%rdi,%rax,4),%edx\nadd (%r8,%rax,4),%edx\ncmp %edx,%ecx\ncmovl %edx,%ecx\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %r9,%rdx\njne 127a \ncmp %ecx,-0x4(%rbx,%rsi,4)\ncmovge -0x4(%rbx,%rsi,4),%ecx\nmov %ecx,(%rbx,%rsi,4)\njmp 124a \nadd $0x1,%r11d\nadd %r15,%r13\nadd %r15,%rbx\nadd %r15,%r8\ncmp -0x44(%rbp),%r11d\nje 12c2 \nmov $0x0,%esi\ntest %r14d,%r14d\njg 1256 \njmp 12a3 \nlea -0x1(%r14),%eax\nmovslq %eax,%rdx\nmovslq -0x48(%rbp),%rax\nshr $0x2,%r15\nimul %rax,%r15\nlea (%rdx,%r15,1),%rax\nmov -0x50(%rbp),%rbx\nmov (%rbx,%rax,4),%eax\nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\njne 12fe \nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\ncallq 1080 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 28h\nmov r8, rdi\nmov ebx, esi\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nmovsxd rsi, esi\nlea rax, ds:0[rsi*4]\nlea ecx, [rdx+1]\nmovsxd rcx, ecx\nimul rcx, rsi\nlea rcx, ds:0Fh[rcx*4]\nmov rdi, rcx\nand rdi, 0FFFFFFFFFFFFFFF0h\nand rcx, 0FFFFFFFFFFFFF000h\nmov rsi, rsp\nsub rsi, rcx\nloc_11E3:\ncmp rsp, rsi\njz short loc_11FA\nsub rsp, 1000h\nor [rsp+1050h+var_58], 0\njmp short loc_11E3\nloc_11FA:\nmov rcx, rdi\nand ecx, 0FFFh\nsub rsp, rcx\ntest rcx, rcx\njz short loc_1211\nor [rsp+rcx+50h+var_58], 0\nloc_1211:\nmov rcx, rsp\ntest edx, edx\njs loc_12CA\nmov r12, rcx\nmov r9, rcx\nsub r9, rax\nlea r10d, [rdx+1]\nmov r13, rcx\nmov r11d, 0\nmov [rbp+var_4C], r10d\njmp short loc_12B5\nloc_1238:\nmov dword ptr [r12+rdi], 0\nloc_1240:\nadd r14d, 1\nadd rdi, 4\ncmp ebx, r14d\njz short loc_129C\nloc_124D:\ntest r11d, r11d\njz short loc_1238\ntest r14d, r14d\njz short loc_1238\nmov r10d, 0\njle short loc_1289\nmov r15d, [r8+rdi]\nmov eax, 0\nmov r10d, 0\nloc_126E:\nmov esi, r15d\nsub esi, [r8+rax]\nadd esi, [r9+rax]\ncmp r10d, esi\ncmovl r10d, esi\nadd rax, 4\ncmp rax, rdi\njnz short loc_126E\nloc_1289:\nmov eax, [r13+rdi-4]\ncmp eax, r10d\ncmovl eax, r10d\nmov [r13+rdi+0], eax\njmp short loc_1240\nloc_129C:\nmov rax, [rbp+var_48]\nloc_12A0:\nadd r11d, 1\nadd r12, rax\nadd r13, rax\nadd r9, rax\nmov edi, [rbp+var_4C]\ncmp r11d, edi\njz short loc_12CA\nloc_12B5:\nmov edi, 0\nmov r14d, 0\ntest ebx, ebx\njle short loc_12A0\nmov [rbp+var_48], rax\njmp short loc_124D\nloc_12CA:\nlea esi, [rbx-1]\nmovsxd rsi, esi\nmovsxd rdx, edx\nshr rax, 2\nimul rdx, rax\nlea rax, [rsi+rdx]\nmov eax, [rcx+rax*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_1300\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1300:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n unsigned __int64 v5; // rax\n __int16 v6; // di\n _BYTE *v7; // rsi\n signed __int64 v8; // rcx\n void *v9; // rsp\n _BYTE *v10; // r12\n _BYTE *v11; // r9\n _BYTE *v12; // r13\n int v13; // r11d\n int v14; // r14d\n __int64 v15; // rdi\n int v16; // r10d\n int v17; // r15d\n __int64 v18; // rax\n int v19; // eax\n _BYTE v22[4]; // [rsp+8h] [rbp-50h] BYREF\n int v23; // [rsp+Ch] [rbp-4Ch]\n unsigned __int64 v24; // [rsp+10h] [rbp-48h]\n unsigned __int64 v25; // [rsp+20h] [rbp-38h]\n\n v25 = __readfsqword(0x28u);\n v5 = 4LL * a2;\n v6 = (4 * a2 * (a3 + 1) + 15) & 0xFFF0;\n v7 = &v22[-((4 * a2 * (__int64)(a3 + 1) + 15) & 0xFFFFFFFFFFFFF000LL)];\n while ( v22 != v7 )\n ;\n v8 = v6 & 0xFFF;\n v9 = alloca(v8);\n if ( (v6 & 0xFFF) != 0 )\n *(_QWORD *)&v22[v8 - 8] = *(_QWORD *)&v22[v8 - 8];\n if ( a3 >= 0 )\n {\n v10 = v22;\n v11 = &v22[-v5];\n v12 = v22;\n v13 = 0;\n v23 = a3 + 1;\n do\n {\n v15 = 0LL;\n v14 = 0;\n if ( a2 > 0 )\n {\n v24 = v5;\n do\n {\n if ( v13 && v14 )\n {\n v16 = 0;\n if ( v14 > 0 )\n {\n v18 = 0LL;\n v16 = 0;\n do\n {\n v17 = *(_DWORD *)(a1 + v15);\n if ( v16 < *(_DWORD *)&v11[v18] + v17 - *(_DWORD *)(a1 + v18) )\n v16 = *(_DWORD *)&v11[v18] + v17 - *(_DWORD *)(a1 + v18);\n v18 += 4LL;\n }\n while ( v18 != v15 );\n }\n v19 = *(_DWORD *)&v12[v15 - 4];\n if ( v19 < v16 )\n v19 = v16;\n *(_DWORD *)&v12[v15] = v19;\n }\n else\n {\n *(_DWORD *)&v10[v15] = 0;\n }\n ++v14;\n v15 += 4LL;\n }\n while ( a2 != v14 );\n v5 = v24;\n }\n ++v13;\n v10 += v5;\n v12 += v5;\n v11 += v5;\n }\n while ( v13 != v23 );\n }\n return *(unsigned int *)&v22[4 * a2 - 4 + 4 * (v5 >> 2) * a3];\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 28h\nmov r8, rdi\nmov ebx, esi\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nmovsxd rsi, esi\nlea rax, ds:0[rsi*4]\nlea ecx, [rdx+1]\nmovsxd rcx, ecx\nimul rcx, rsi\nlea rcx, ds:0Fh[rcx*4]\nmov rdi, rcx\nand rdi, 0FFFFFFFFFFFFFFF0h\nand rcx, 0FFFFFFFFFFFFF000h\nmov rsi, rsp\nsub rsi, rcx\nloc_11E3:\ncmp rsp, rsi\njz short loc_11FA\nsub rsp, 1000h\nor [rsp+1050h+var_58], 0\njmp short loc_11E3\nloc_11FA:\nmov rcx, rdi\nand ecx, 0FFFh\nsub rsp, rcx\ntest rcx, rcx\njz short loc_1211\nor [rsp+rcx+50h+var_58], 0\nloc_1211:\nmov rcx, rsp\ntest edx, edx\njs loc_12CA\nmov r12, rcx\nmov r9, rcx\nsub r9, rax\nlea r10d, [rdx+1]\nmov r13, rcx\nmov r11d, 0\nmov [rbp+var_4C], r10d\njmp short loc_12B5\nloc_1238:\nmov dword ptr [r12+rdi], 0\nloc_1240:\nadd r14d, 1\nadd rdi, 4\ncmp ebx, r14d\njz short loc_129C\nloc_124D:\ntest r11d, r11d\njz short loc_1238\ntest r14d, r14d\njz short loc_1238\nmov r10d, 0\njle short loc_1289\nmov r15d, [r8+rdi]\nmov eax, 0\nmov r10d, 0\nloc_126E:\nmov esi, r15d\nsub esi, [r8+rax]\nadd esi, [r9+rax]\ncmp r10d, esi\ncmovl r10d, esi\nadd rax, 4\ncmp rax, rdi\njnz short loc_126E\nloc_1289:\nmov eax, [r13+rdi-4]\ncmp eax, r10d\ncmovl eax, r10d\nmov [r13+rdi+0], eax\njmp short loc_1240\nloc_129C:\nmov rax, [rbp+var_48]\nloc_12A0:\nadd r11d, 1\nadd r12, rax\nadd r13, rax\nadd r9, rax\nmov edi, [rbp+var_4C]\ncmp r11d, edi\njz short loc_12CA\nloc_12B5:\nmov edi, 0\nmov r14d, 0\ntest ebx, ebx\njle short loc_12A0\nmov [rbp+var_48], rax\njmp short loc_124D\nloc_12CA:\nlea esi, [rbx-1]\nmovsxd rsi, esi\nmovsxd rdx, edx\nshr rax, 2\nimul rdx, rax\nlea rax, [rsi+rdx]\nmov eax, [rcx+rax*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_1300\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1300:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2, int a3)\n{\n unsigned __int64 v5; // rax\n __int16 v6; // di\n _BYTE *v7; // rsi\n signed __int64 v8; // rcx\n void *v9; // rsp\n _BYTE *v10; // r12\n _BYTE *v11; // r9\n _BYTE *v12; // r13\n int v13; // r11d\n int v14; // r14d\n __int64 v15; // rdi\n int v16; // r10d\n int v17; // r15d\n __int64 v18; // rax\n int v19; // eax\n _BYTE v22[4]; // [rsp+8h] [rbp-50h] BYREF\n int v23; // [rsp+Ch] [rbp-4Ch]\n unsigned __int64 v24; // [rsp+10h] [rbp-48h]\n unsigned __int64 v25; // [rsp+20h] [rbp-38h]\n\n v25 = __readfsqword(0x28u);\n v5 = 4LL * a2;\n v6 = (4 * a2 * (a3 + 1) + 15) & 0xFFF0;\n v7 = &v22[-((4 * a2 * (__int64)(a3 + 1) + 15) & 0xFFFFFFFFFFFFF000LL)];\n while ( v22 != v7 )\n ;\n v8 = v6 & 0xFFF;\n v9 = alloca(v8);\n if ( (v6 & 0xFFF) != 0 )\n *(_QWORD *)&v22[v8 - 8] = *(_QWORD *)&v22[v8 - 8];\n if ( a3 >= 0 )\n {\n v10 = v22;\n v11 = &v22[-v5];\n v12 = v22;\n v13 = 0;\n v23 = a3 + 1;\n do\n {\n v15 = 0LL;\n v14 = 0;\n if ( a2 > 0 )\n {\n v24 = v5;\n do\n {\n if ( v13 && v14 )\n {\n v16 = 0;\n if ( v14 > 0 )\n {\n v18 = 0LL;\n v16 = 0;\n do\n {\n v17 = *(_DWORD *)(a1 + v15);\n if ( v16 < *(_DWORD *)&v11[v18] + v17 - *(_DWORD *)(a1 + v18) )\n v16 = *(_DWORD *)&v11[v18] + v17 - *(_DWORD *)(a1 + v18);\n v18 += 4LL;\n }\n while ( v18 != v15 );\n }\n v19 = *(_DWORD *)&v12[v15 - 4];\n if ( v19 < v16 )\n v19 = v16;\n *(_DWORD *)&v12[v15] = v19;\n }\n else\n {\n *(_DWORD *)&v10[v15] = 0;\n }\n ++v14;\n v15 += 4LL;\n }\n while ( a2 != v14 );\n v5 = v24;\n }\n ++v13;\n v10 += v5;\n v12 += v5;\n v11 += v5;\n }\n while ( v13 != v23 );\n }\n return *(unsigned int *)&v22[4 * a2 - 4 + 4 * (v5 >> 2) * a3];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2, int a3) {\n unsigned long long v5;\n short v6;\n uint8_t *v7;\n signed long long v8;\n void *v9;\n uint8_t *v10;\n uint8_t *v11;\n uint8_t *v12;\n int v13;\n int v14;\n long long v15;\n int v16;\n int v17;\n long long v18;\n int v19;\n uint8_t v22[4];\n int v23;\n unsigned long long v24;\n unsigned long long v25;\n v25 = __readfsqword(40u);\n v5 = 4LL * a2;\n v6 = (4 * a2 * (a3 + 1) + 15) & 65520;\n v7 = &v22[-((4 * a2 * (long long)(a3 + 1) + 15) & 18446744073709547520LL)];\n while (v22 != v7)\n ;\n v8 = v6 & 4095;\n v9 = alloca(v8);\n if ((v6 & 4095) != 0) *(uint64_t *)&v22[v8 - 8] = *(uint64_t *)&v22[v8 - 8];\n if (a3 >= 0) {\n v10 = v22;\n v11 = &v22[-v5];\n v12 = v22;\n v13 = 0;\n v23 = a3 + 1;\n do {\n v15 = 0LL;\n v14 = 0;\n if (a2 > 0) {\n v24 = v5;\n do {\n if (v13 && v14) {\n v16 = 0;\n if (v14 > 0) {\n v18 = 0LL;\n v16 = 0;\n do {\n v17 = *(uint32_t *)(a1 + v15);\n if (v16 <\n *(uint32_t *)&v11[v18] + v17 - *(uint32_t *)(a1 + v18))\n v16 = *(uint32_t *)&v11[v18] + v17 - *(uint32_t *)(a1 + v18);\n v18 += 4LL;\n } while (v18 != v15);\n }\n v19 = *(uint32_t *)&v12[v15 - 4];\n if (v19 < v16) v19 = v16;\n *(uint32_t *)&v12[v15] = v19;\n } else {\n *(uint32_t *)&v10[v15] = 0;\n }\n ++v14;\n v15 += 4LL;\n } while (a2 != v14);\n v5 = v24;\n }\n ++v13;\n v10 += v5;\n v12 += v5;\n v11 += v5;\n } while (v13 != v23);\n }\n return *(unsigned int *)&v22[4 * a2 - 4 + 4 * (v5 >> 2) * a3];\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n unsigned long long v5;\n short v6;\n uint8_t *v7;\n signed long long v8;\n void *v9;\n uint8_t *v10;\n uint8_t *v11;\n uint8_t *v12;\n int v13;\n int v14;\n long long v15;\n int v16;\n int v17;\n long long v18;\n int v19;\n uint8_t v22[4];\n int v23;\n unsigned long long v24;\n unsigned long long v25;\n v25 = __readfsqword(40u);\n v5 = 4LL * a2;\n v6 = (4 * a2 * (a3 + 1) + 15) & 65520;\n v7 = &v22[-((4 * a2 * (long long)(a3 + 1) + 15) & 18446744073709547520LL)];\n while (v22 != v7)\n ;\n v8 = v6 & 4095;\n v9 = alloca(v8);\n if ((v6 & 4095) != 0) *(uint64_t *)&v22[v8 - 8] = *(uint64_t *)&v22[v8 - 8];\n if (a3 >= 0) {\n v10 = v22;\n v11 = &v22[-v5];\n v12 = v22;\n v13 = 0;\n v23 = a3 + 1;\n do {\n v15 = 0LL;\n v14 = 0;\n if (a2 > 0) {\n v24 = v5;\n do {\n if (v13 && v14) {\n v16 = 0;\n if (v14 > 0) {\n v18 = 0LL;\n v16 = 0;\n do {\n v17 = *(uint32_t *)(a1 + v15);\n if (v16 <\n *(uint32_t *)&v11[v18] + v17 - *(uint32_t *)(a1 + v18))\n v16 = *(uint32_t *)&v11[v18] + v17 - *(uint32_t *)(a1 + v18);\n v18 += 4LL;\n } while (v18 != v15);\n }\n v19 = *(uint32_t *)&v12[v15 - 4];\n if (v19 < v16) v19 = v16;\n *(uint32_t *)&v12[v15] = v19;\n } else {\n *(uint32_t *)&v10[v15] = 0;\n }\n ++v14;\n v15 += 4LL;\n } while (a2 != v14);\n v5 = v24;\n }\n ++v13;\n v10 += v5;\n v12 += v5;\n v11 += v5;\n } while (v13 != v23);\n }\n return *(unsigned int *)&v22[4 * a2 - 4 + 4 * (v5 >> 2) * a3];\n}" + }, + { + "index": 469, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n\n\n", + "func": "int func0(int price[], int n, int k) {\n int final_profit[k + 1][n];\n for (int i = 0; i <= k; i++) {\n for (int j = 0; j < n; j++) {\n if (i == 0 || j == 0) {\n final_profit[i][j] = 0;\n } else {\n int max_so_far = 0;\n for (int x = 0; x < j; x++) {\n int curr_price = price[j] - price[x] + final_profit[i - 1][x];\n if (max_so_far < curr_price) {\n max_so_far = curr_price;\n }\n }\n final_profit[i][j] = (final_profit[i][j - 1] > max_so_far)\n ? final_profit[i][j - 1]\n : max_so_far;\n }\n }\n }\n return final_profit[k][n - 1];\n}", + "test": "int main() {\n\n int prices1[] = {1, 5, 2, 3, 7, 6, 4, 5};\n\n int n1 = sizeof(prices1) / sizeof(prices1[0]);\n\n assert(func0(prices1, n1, 3) == 10);\n\n\n\n int prices2[] = {2, 4, 7, 5, 4, 3, 5};\n\n int n2 = sizeof(prices2) / sizeof(prices2[0]);\n\n assert(func0(prices2, n2, 2) == 7);\n\n\n\n int prices3[] = {10, 6, 8, 4, 2};\n\n int n3 = sizeof(prices3) / sizeof(prices3[0]);\n\n assert(func0(prices3, n3, 2) == 2);\n\n\n\n printf(\"All tests passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %edx,%eax\nmov %rdi,%r9\nadd $0x1,%eax\nmov %rsp,%rbp\npush %r15\npush %r14\nmov %esi,%r14d\npush %r13\npush %r12\npush %rbx\nsub $0x48,%rsp\nmov %edx,-0x50(%rbp)\nmovslq %esi,%rdx\nmov %fs:0x28,%rbx\nmov %rbx,-0x38(%rbp)\nxor %ebx,%ebx\nmov %eax,-0x4c(%rbp)\ncltq\nlea 0x0(,%rdx,4),%rbx\nimul %rdx,%rax\nmov %rbx,-0x48(%rbp)\nmov %rsp,%rbx\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rbx\nand $0xfffffffffffffff0,%rdx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 13a2 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 138d \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 14be \nmov -0x48(%rbp),%rax\nmov %rsp,-0x60(%rbp)\nshr $0x2,%rax\nmov %rax,-0x58(%rbp)\nmov -0x50(%rbp),%eax\ntest %eax,%eax\njs 14c9 \nmov -0x58(%rbp),%rax\nmov -0x60(%rbp),%rbx\nxor %r13d,%r13d\nneg %rax\nlea (%rbx,%rax,4),%r11\nlea -0x1(%r14),%ebx\nmov %ebx,-0x64(%rbp)\nnopl 0x0(%rax,%rax,1)\nmov -0x48(%rbp),%rax\nlea (%r11,%rax,1),%r15\ntest %r14d,%r14d\njle 1478 \nmov -0x48(%rbp),%rax\ntest %r13d,%r13d\nsete %r12b\nxor %esi,%esi\nlea (%r11,%rax,1),%r15\nmov %r15,%rdi\njmp 142e \nnopl 0x0(%rax,%rax,1)\nmovl $0x0,(%rdi)\nlea 0x1(%rsi),%rax\nadd $0x4,%rdi\ncmp %rbx,%rsi\nje 1478 \nmov %rax,%rsi\nmov %esi,%r8d\ntest %esi,%esi\nje 1418 \ntest %r12b,%r12b\njne 1418 \nmov (%r9,%rsi,4),%r10d\nxor %eax,%eax\nxor %ecx,%ecx\nnopw 0x0(%rax,%rax,1)\nmov %r10d,%edx\nsub (%r9,%rax,4),%edx\nadd (%r11,%rax,4),%edx\ncmp %edx,%ecx\ncmovl %edx,%ecx\nadd $0x1,%rax\ncmp %eax,%r8d\njg 1448 \ncmp %ecx,-0x4(%rdi)\ncmovge -0x4(%rdi),%ecx\nlea 0x1(%rsi),%rax\nadd $0x4,%rdi\nmov %ecx,-0x4(%rdi)\ncmp %rbx,%rsi\njne 142b \nadd $0x1,%r13d\nmov %r15,%r11\ncmp -0x4c(%rbp),%r13d\njne 13f0 \nmovslq -0x50(%rbp),%rax\nimul -0x58(%rbp),%rax\nmovslq -0x64(%rbp),%rdx\nmov -0x60(%rbp),%rbx\nadd %rdx,%rax\nmov (%rbx,%rax,4),%eax\nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\njne 14d2 \nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 13b4 \nlea -0x1(%r14),%eax\nmov %eax,-0x64(%rbp)\njmp 1489 \ncallq 1080 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov r8, rdi\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nmovsxd rbx, esi\nmov rdi, rbx\nlea r9, ds:0[rbx*4]\nsub rsp, 38h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nlea eax, [rdx+1]\nmov rcx, rsp\ncdqe\nimul rax, rbx\nlea rax, ds:0Fh[rax*4]\nmov rsi, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rsi, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_1343\nloc_132E:\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\ncmp rsp, rcx\njnz short loc_132E\nloc_1343:\nand esi, 0FFFh\nsub rsp, rsi\ntest rsi, rsi\njnz loc_1457\nloc_1355:\nmov r13, r9\nmov r12, rsp\nshr r13, 2\ntest edx, edx\njs loc_1426\nmov rax, r13\nmov [rbp+var_58], r13\nmov r11, r12\nmov rcx, r12\nneg rax\nlea r10, [r12+rax*4]\nxor eax, eax\nnop dword ptr [rax]\nloc_1380:\ntest eax, eax\nsetz r15b\nxor r12d, r12d\ntest edi, edi\njle short loc_140B\nmov [rbp+var_48], r9\nmov [rbp+var_4C], eax\njmp short loc_13B0\nloc_13A0:\nxor r9d, r9d\nmov [r11+r12*4], r9d\nadd r12, 1\ncmp rbx, r12\njz short loc_1404\nloc_13B0:\nmov r13d, r12d\ntest r12d, r12d\njz short loc_13A0\ntest r15b, r15b\njnz short loc_13A0\nmov r14d, [r8+r12*4]\nxor eax, eax\nxor r9d, r9d\nnop word ptr [rax+rax+00000000h]\nloc_13D0:\nmov esi, r14d\nsub esi, [r8+rax*4]\nadd esi, [r10+rax*4]\ncmp r9d, esi\ncmovl r9d, esi\nadd rax, 1\ncmp r13d, eax\njg short loc_13D0\nmov eax, [r11+r12*4-4]\ncmp r9d, eax\ncmovl r9d, eax\nmov [r11+r12*4], r9d\nadd r12, 1\ncmp rbx, r12\njnz short loc_13B0\nloc_1404:\nmov r9, [rbp+var_48]\nmov eax, [rbp+var_4C]\nloc_140B:\nlea esi, [rax+1]\nadd r11, r9\nadd r10, r9\ncmp edx, eax\njz short loc_141F\nmov eax, esi\njmp loc_1380\nloc_141F:\nmov r13, [rbp+var_58]\nmov r12, rcx\nloc_1426:\nmovsxd rdx, edx\nlea eax, [rdi-1]\nimul rdx, r13\ncdqe\nadd rax, rdx\nmov eax, [r12+rax*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_1462\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1457:\nor [rsp+rsi+1060h+var_1068], 0\njmp loc_1355\nloc_1462:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n __int64 v4; // rbx\n unsigned __int64 v6; // r9\n __int64 v7; // rsi\n __int64 *v8; // rcx\n __int16 v9; // si\n signed __int64 v10; // rsi\n void *v11; // rsp\n unsigned __int64 v12; // r13\n _DWORD *v13; // r11\n _DWORD *v14; // r10\n int i; // eax\n bool v16; // r15\n __int64 v17; // r12\n int v18; // r14d\n __int64 v19; // rax\n int v20; // r9d\n _DWORD v23[1022]; // [rsp+8h] [rbp-1060h] BYREF\n __int64 v24; // [rsp+1008h] [rbp-60h] BYREF\n unsigned __int64 v25; // [rsp+1010h] [rbp-58h]\n int v26; // [rsp+101Ch] [rbp-4Ch]\n unsigned __int64 v27; // [rsp+1020h] [rbp-48h]\n unsigned __int64 v28; // [rsp+1030h] [rbp-38h]\n\n v4 = a2;\n v6 = 4LL * a2;\n v28 = __readfsqword(0x28u);\n v7 = 4 * a2 * (__int64)(a3 + 1) + 15;\n v8 = (__int64 *)((char *)&v24 - (v7 & 0xFFFFFFFFFFFFF000LL));\n v9 = v7 & 0xFFF0;\n if ( &v24 != v8 )\n {\n while ( v23 != (_DWORD *)v8 )\n ;\n }\n v10 = v9 & 0xFFF;\n v11 = alloca(v10);\n if ( v10 )\n *(_QWORD *)((char *)&v23[-2] + v10) = *(_QWORD *)((char *)&v23[-2] + v10);\n v12 = v6 >> 2;\n if ( a3 >= 0 )\n {\n v25 = v6 >> 2;\n v13 = v23;\n v14 = &v23[-v12];\n for ( i = 0; ; ++i )\n {\n v16 = i == 0;\n v17 = 0LL;\n if ( a2 > 0 )\n {\n v27 = v6;\n v26 = i;\n do\n {\n while ( !(_DWORD)v17 || v16 )\n {\n v13[v17++] = 0;\n if ( v4 == v17 )\n goto LABEL_19;\n }\n v19 = 0LL;\n v20 = 0;\n do\n {\n v18 = *(_DWORD *)(a1 + 4 * v17);\n if ( v20 < v14[v19] + v18 - *(_DWORD *)(a1 + 4 * v19) )\n v20 = v14[v19] + v18 - *(_DWORD *)(a1 + 4 * v19);\n ++v19;\n }\n while ( (int)v17 > (int)v19 );\n if ( v20 < v13[v17 - 1] )\n v20 = v13[v17 - 1];\n v13[v17++] = v20;\n }\n while ( v4 != v17 );\nLABEL_19:\n v6 = v27;\n i = v26;\n }\n v13 = (_DWORD *)((char *)v13 + v6);\n v14 = (_DWORD *)((char *)v14 + v6);\n if ( a3 == i )\n break;\n }\n v12 = v25;\n }\n return (unsigned int)v23[v12 * a3 - 1 + a2];\n}", + "ida_strip_asm": "sub_12D0:\nendbr64\npush rbp\nmov r8, rdi\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nmovsxd rbx, esi\nmov rdi, rbx\nlea r9, ds:0[rbx*4]\nsub rsp, 38h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nlea eax, [rdx+1]\nmov rcx, rsp\ncdqe\nimul rax, rbx\nlea rax, ds:0Fh[rax*4]\nmov rsi, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rsi, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_1343\nloc_132E:\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\ncmp rsp, rcx\njnz short loc_132E\nloc_1343:\nand esi, 0FFFh\nsub rsp, rsi\ntest rsi, rsi\njnz loc_1457\nloc_1355:\nmov r13, r9\nmov r12, rsp\nshr r13, 2\ntest edx, edx\njs loc_1426\nmov rax, r13\nmov [rbp+var_58], r13\nmov r11, r12\nmov rcx, r12\nneg rax\nlea r10, [r12+rax*4]\nxor eax, eax\nnop dword ptr [rax]\nloc_1380:\ntest eax, eax\nsetz r15b\nxor r12d, r12d\ntest edi, edi\njle short loc_140B\nmov [rbp+var_48], r9\nmov [rbp+var_4C], eax\njmp short loc_13B0\nloc_13A0:\nxor r9d, r9d\nmov [r11+r12*4], r9d\nadd r12, 1\ncmp rbx, r12\njz short loc_1404\nloc_13B0:\nmov r13d, r12d\ntest r12d, r12d\njz short loc_13A0\ntest r15b, r15b\njnz short loc_13A0\nmov r14d, [r8+r12*4]\nxor eax, eax\nxor r9d, r9d\nnop word ptr [rax+rax+00000000h]\nloc_13D0:\nmov esi, r14d\nsub esi, [r8+rax*4]\nadd esi, [r10+rax*4]\ncmp r9d, esi\ncmovl r9d, esi\nadd rax, 1\ncmp r13d, eax\njg short loc_13D0\nmov eax, [r11+r12*4-4]\ncmp r9d, eax\ncmovl r9d, eax\nmov [r11+r12*4], r9d\nadd r12, 1\ncmp rbx, r12\njnz short loc_13B0\nloc_1404:\nmov r9, [rbp+var_48]\nmov eax, [rbp+var_4C]\nloc_140B:\nlea esi, [rax+1]\nadd r11, r9\nadd r10, r9\ncmp edx, eax\njz short loc_141F\nmov eax, esi\njmp loc_1380\nloc_141F:\nmov r13, [rbp+var_58]\nmov r12, rcx\nloc_1426:\nmovsxd rdx, edx\nlea eax, [rdi-1]\nimul rdx, r13\ncdqe\nadd rax, rdx\nmov eax, [r12+rax*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_1462\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1457:\nor [rsp+rsi+1060h+var_1068], 0\njmp loc_1355\nloc_1462:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12D0(__int64 a1, int a2, int a3)\n{\n __int64 v4; // rbx\n unsigned __int64 v6; // r9\n __int64 v7; // rsi\n __int64 *v8; // rcx\n __int16 v9; // si\n signed __int64 v10; // rsi\n void *v11; // rsp\n unsigned __int64 v12; // r13\n _DWORD *v13; // r11\n _DWORD *v14; // r10\n int i; // eax\n bool v16; // r15\n __int64 v17; // r12\n int v18; // r14d\n __int64 v19; // rax\n int v20; // r9d\n _DWORD v23[1022]; // [rsp+8h] [rbp-1060h] BYREF\n __int64 v24; // [rsp+1008h] [rbp-60h] BYREF\n unsigned __int64 v25; // [rsp+1010h] [rbp-58h]\n int v26; // [rsp+101Ch] [rbp-4Ch]\n unsigned __int64 v27; // [rsp+1020h] [rbp-48h]\n unsigned __int64 v28; // [rsp+1030h] [rbp-38h]\n\n v4 = a2;\n v6 = 4LL * a2;\n v28 = __readfsqword(0x28u);\n v7 = 4 * a2 * (__int64)(a3 + 1) + 15;\n v8 = (__int64 *)((char *)&v24 - (v7 & 0xFFFFFFFFFFFFF000LL));\n v9 = v7 & 0xFFF0;\n if ( &v24 != v8 )\n {\n while ( v23 != (_DWORD *)v8 )\n ;\n }\n v10 = v9 & 0xFFF;\n v11 = alloca(v10);\n if ( v10 )\n *(_QWORD *)((char *)&v23[-2] + v10) = *(_QWORD *)((char *)&v23[-2] + v10);\n v12 = v6 >> 2;\n if ( a3 >= 0 )\n {\n v25 = v6 >> 2;\n v13 = v23;\n v14 = &v23[-v12];\n for ( i = 0; ; ++i )\n {\n v16 = i == 0;\n v17 = 0LL;\n if ( a2 > 0 )\n {\n v27 = v6;\n v26 = i;\n do\n {\n while ( !(_DWORD)v17 || v16 )\n {\n v13[v17++] = 0;\n if ( v4 == v17 )\n goto LABEL_19;\n }\n v19 = 0LL;\n v20 = 0;\n do\n {\n v18 = *(_DWORD *)(a1 + 4 * v17);\n if ( v20 < v14[v19] + v18 - *(_DWORD *)(a1 + 4 * v19) )\n v20 = v14[v19] + v18 - *(_DWORD *)(a1 + 4 * v19);\n ++v19;\n }\n while ( (int)v17 > (int)v19 );\n if ( v20 < v13[v17 - 1] )\n v20 = v13[v17 - 1];\n v13[v17++] = v20;\n }\n while ( v4 != v17 );\nLABEL_19:\n v6 = v27;\n i = v26;\n }\n v13 = (_DWORD *)((char *)v13 + v6);\n v14 = (_DWORD *)((char *)v14 + v6);\n if ( a3 == i )\n break;\n }\n v12 = v25;\n }\n return (unsigned int)v23[v12 * a3 - 1 + a2];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12D0(long long a1, int a2, int a3) {\n long long v4;\n unsigned long long v6;\n long long v7;\n long long *v8;\n short v9;\n signed long long v10;\n void *v11;\n unsigned long long v12;\n uint32_t *v13;\n uint32_t *v14;\n int i;\n bool v16;\n long long v17;\n int v18;\n long long v19;\n int v20;\n uint32_t v23[1022];\n long long v24;\n unsigned long long v25;\n int v26;\n unsigned long long v27;\n unsigned long long v28;\n v4 = a2;\n v6 = 4LL * a2;\n v28 = __readfsqword(40u);\n v7 = 4 * a2 * (long long)(a3 + 1) + 15;\n v8 = (long long *)((char *)&v24 - (v7 & 18446744073709547520LL));\n v9 = v7 & 65520;\n if (&v24 != v8) {\n while (v23 != (uint32_t *)v8)\n ;\n }\n v10 = v9 & 4095;\n v11 = alloca(v10);\n if (v10)\n *(uint64_t *)((char *)&v23[-2] + v10) =\n *(uint64_t *)((char *)&v23[-2] + v10);\n v12 = v6 >> 2;\n if (a3 >= 0) {\n v25 = v6 >> 2;\n v13 = v23;\n v14 = &v23[-v12];\n for (i = 0;; ++i) {\n v16 = i == 0;\n v17 = 0LL;\n if (a2 > 0) {\n v27 = v6;\n v26 = i;\n do {\n while (!(uint32_t)v17 || v16) {\n v13[v17++] = 0;\n if (v4 == v17) goto LABEL_19;\n }\n v19 = 0LL;\n v20 = 0;\n do {\n v18 = *(uint32_t *)(a1 + 4 * v17);\n if (v20 < v14[v19] + v18 - *(uint32_t *)(a1 + 4 * v19))\n v20 = v14[v19] + v18 - *(uint32_t *)(a1 + 4 * v19);\n ++v19;\n } while ((int)v17 > (int)v19);\n if (v20 < v13[v17 - 1]) v20 = v13[v17 - 1];\n v13[v17++] = v20;\n } while (v4 != v17);\n LABEL_19:\n v6 = v27;\n i = v26;\n }\n v13 = (uint32_t *)((char *)v13 + v6);\n v14 = (uint32_t *)((char *)v14 + v6);\n if (a3 == i) break;\n }\n v12 = v25;\n }\n return (unsigned int)v23[v12 * a3 - 1 + a2];\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n long long v4;\n unsigned long long v6;\n long long v7;\n long long *v8;\n short v9;\n signed long long v10;\n void *v11;\n unsigned long long v12;\n uint32_t *v13;\n uint32_t *v14;\n int i;\n bool v16;\n long long v17;\n int v18;\n long long v19;\n int v20;\n uint32_t v23[1022];\n long long v24;\n unsigned long long v25;\n int v26;\n unsigned long long v27;\n unsigned long long v28;\n v4 = a2;\n v6 = 4LL * a2;\n v28 = __readfsqword(40u);\n v7 = 4 * a2 * (long long)(a3 + 1) + 15;\n v8 = (long long *)((char *)&v24 - (v7 & 18446744073709547520LL));\n v9 = v7 & 65520;\n if (&v24 != v8) {\n while (v23 != (uint32_t *)v8)\n ;\n }\n v10 = v9 & 4095;\n v11 = alloca(v10);\n if (v10)\n *(uint64_t *)((char *)&v23[-2] + v10) =\n *(uint64_t *)((char *)&v23[-2] + v10);\n v12 = v6 >> 2;\n if (a3 >= 0) {\n v25 = v6 >> 2;\n v13 = v23;\n v14 = &v23[-v12];\n for (i = 0;; ++i) {\n v16 = i == 0;\n v17 = 0LL;\n if (a2 > 0) {\n v27 = v6;\n v26 = i;\n do {\n while (!(uint32_t)v17 || v16) {\n v13[v17++] = 0;\n if (v4 == v17) goto LABEL_19;\n }\n v19 = 0LL;\n v20 = 0;\n do {\n v18 = *(uint32_t *)(a1 + 4 * v17);\n if (v20 < v14[v19] + v18 - *(uint32_t *)(a1 + 4 * v19))\n v20 = v14[v19] + v18 - *(uint32_t *)(a1 + 4 * v19);\n ++v19;\n } while ((int)v17 > (int)v19);\n if (v20 < v13[v17 - 1]) v20 = v13[v17 - 1];\n v13[v17++] = v20;\n } while (v4 != v17);\n LABEL_19:\n v6 = v27;\n i = v26;\n }\n v13 = (uint32_t *)((char *)v13 + v6);\n v14 = (uint32_t *)((char *)v14 + v6);\n if (a3 == i) break;\n }\n v12 = v25;\n }\n return (unsigned int)v23[v12 * a3 - 1 + a2];\n}" + }, + { + "index": 469, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n\n\n", + "func": "int func0(int price[], int n, int k) {\n int final_profit[k + 1][n];\n for (int i = 0; i <= k; i++) {\n for (int j = 0; j < n; j++) {\n if (i == 0 || j == 0) {\n final_profit[i][j] = 0;\n } else {\n int max_so_far = 0;\n for (int x = 0; x < j; x++) {\n int curr_price = price[j] - price[x] + final_profit[i - 1][x];\n if (max_so_far < curr_price) {\n max_so_far = curr_price;\n }\n }\n final_profit[i][j] = (final_profit[i][j - 1] > max_so_far)\n ? final_profit[i][j - 1]\n : max_so_far;\n }\n }\n }\n return final_profit[k][n - 1];\n}", + "test": "int main() {\n\n int prices1[] = {1, 5, 2, 3, 7, 6, 4, 5};\n\n int n1 = sizeof(prices1) / sizeof(prices1[0]);\n\n assert(func0(prices1, n1, 3) == 10);\n\n\n\n int prices2[] = {2, 4, 7, 5, 4, 3, 5};\n\n int n2 = sizeof(prices2) / sizeof(prices2[0]);\n\n assert(func0(prices2, n2, 2) == 7);\n\n\n\n int prices3[] = {10, 6, 8, 4, 2};\n\n int n3 = sizeof(prices3) / sizeof(prices3[0]);\n\n assert(func0(prices3, n3, 2) == 2);\n\n\n\n printf(\"All tests passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %edx,%eax\nadd $0x1,%eax\ncltq\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0x58,%rsp\nmov %edx,-0x58(%rbp)\nmovslq %esi,%rdx\nimul %rdx,%rax\nmov %fs:0x28,%rbx\nmov %rbx,-0x38(%rbp)\nxor %ebx,%ebx\nlea 0x0(,%rdx,4),%rbx\nlea 0xf(,%rax,4),%rax\nmov %rbx,-0x70(%rbp)\nmov %rsp,%rbx\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rbx\nand $0xfffffffffffffff0,%rdx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 1349 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 1334 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 159a \nmov -0x70(%rbp),%rax\nmov -0x58(%rbp),%edx\nmov %rsp,%r15\nshr $0x2,%rax\nmov %rax,-0x68(%rbp)\ntest %edx,%edx\njs 15a5 \ntest %esi,%esi\njle 15a5 \nneg %rax\nlea -0x1(%rsi),%r12d\nmovl $0xffffffff,-0x54(%rbp)\nlea (%r15,%rax,4),%rax\nmov %r12d,-0x74(%rbp)\nmov %rax,-0x60(%rbp)\nnopw 0x0(%rax,%rax,1)\nmov -0x54(%rbp),%eax\nmov -0x70(%rbp),%rsi\nmovslq %eax,%rcx\nadd $0x1,%eax\nsete %r13b\nmov %eax,-0x54(%rbp)\nimul -0x68(%rbp),%rcx\nmov -0x60(%rbp),%rax\nmov %rax,%r10\nadd %rsi,%rax\nmov %rcx,%r14\nmov %rax,-0x60(%rbp)\nmov %rax,%rdx\nxor %eax,%eax\nmov %r10,-0x48(%rbp)\njmp 13f2 \nnopl (%rax)\nmovl $0x0,(%rdx)\nlea 0x1(%rax),%rcx\nadd $0x4,%rdx\ncmp %r12,%rax\nje 154c \nmov %rcx,%rax\nmov %eax,%esi\ntest %eax,%eax\nje 13d8 \ntest %r13b,%r13b\njne 13d8 \ntest %eax,%eax\nmov $0x1,%r11d\nmov (%rdi,%rax,4),%r9d\ncmovg %eax,%r11d\ncmp $0x3,%eax\njle 1590 \nmov %r11d,%r8d\nmovd %r9d,%xmm6\nmov -0x48(%rbp),%r10\nxor %ecx,%ecx\nshr $0x2,%r8d\npshufd $0x0,%xmm6,%xmm3\npxor %xmm0,%xmm0\nshl $0x4,%r8\nnopl (%rax)\nmovdqu (%rdi,%rcx,1),%xmm4\nmovdqu (%r10,%rcx,1),%xmm5\nmovdqa %xmm3,%xmm2\nadd $0x10,%rcx\npsubd %xmm4,%xmm2\npaddd %xmm5,%xmm2\nmovdqa %xmm2,%xmm1\npcmpgtd %xmm0,%xmm1\npand %xmm1,%xmm2\npandn %xmm0,%xmm1\nmovdqa %xmm1,%xmm0\npor %xmm2,%xmm0\ncmp %r8,%rcx\njne 1438 \nmovdqa %xmm0,%xmm2\nmov %r11d,%r8d\nmov %r10,-0x48(%rbp)\npsrldq $0x8,%xmm2\nand $0xfffffffc,%r8d\nand $0x3,%r11d\nmovdqa %xmm2,%xmm1\npcmpgtd %xmm0,%xmm1\npand %xmm1,%xmm2\npandn %xmm0,%xmm1\nmovdqa %xmm1,%xmm0\npor %xmm2,%xmm0\nmovdqa %xmm0,%xmm2\npsrldq $0x4,%xmm2\nmovdqa %xmm2,%xmm1\npcmpgtd %xmm0,%xmm1\npand %xmm1,%xmm2\npandn %xmm0,%xmm1\npor %xmm2,%xmm1\nmovd %xmm1,%ecx\nje 1531 \nmovslq %r8d,%r11\nlea 0x0(,%r11,4),%rbx\nmov %rbx,%r10\nmov %r9d,%ebx\nsub (%rdi,%r11,4),%ebx\nadd %r14,%r11\nadd (%r15,%r11,4),%ebx\nlea 0x1(%r8),%r11d\ncmp %ebx,%ecx\ncmovl %ebx,%ecx\ncmp %esi,%r11d\njge 1531 \nmov %r10,%rbx\nmovslq %r11d,%r11\nmov %r10,-0x50(%rbp)\nmov %r9d,%r10d\nadd %r14,%r11\nsub 0x4(%rdi,%rbx,1),%r10d\nmov %r10d,%ebx\nadd (%r15,%r11,4),%ebx\ncmp %ebx,%ecx\ncmovl %ebx,%ecx\nadd $0x2,%r8d\ncmp %esi,%r8d\njge 1531 \nmov -0x50(%rbp),%rbx\nmovslq %r8d,%r8\nadd %r14,%r8\nsub 0x8(%rdi,%rbx,1),%r9d\nadd (%r15,%r8,4),%r9d\ncmp %r9d,%ecx\ncmovl %r9d,%ecx\ncmp %ecx,-0x4(%rdx)\ncmovge -0x4(%rdx),%ecx\nadd $0x4,%rdx\nmov %ecx,-0x4(%rdx)\nlea 0x1(%rax),%rcx\ncmp %r12,%rax\njne 13ef \nmov -0x58(%rbp),%esi\ncmp %esi,-0x54(%rbp)\njne 13a0 \nmovslq -0x58(%rbp),%rax\nimul -0x68(%rbp),%rax\nmovslq -0x74(%rbp),%rdx\nadd %rdx,%rax\nmov -0x38(%rbp),%rsi\nxor %fs:0x28,%rsi\nmov (%r15,%rax,4),%eax\njne 15ad \nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\nnopw 0x0(%rax,%rax,1)\nxor %ecx,%ecx\nxor %r8d,%r8d\njmpq 14c3 \norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 135b \nlea -0x1(%rsi),%eax\nmov %eax,-0x74(%rbp)\njmp 1558 \ncallq 1080 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rcx, rdi\nmov rbp, rsp\npush r15\npush r14\npush r13\nmovsxd r13, edx\npush r12\nmovsxd r12, esi\npush rbx\nmov rax, r12\nlea r11, ds:0[r12*4]\nsub rsp, 48h\nmov rdx, fs:28h\nmov [rbp+var_38], rdx\nxor edx, edx\nlea edx, [r13+1]\nmov rsi, rsp\nmovsxd rdx, edx\nimul rdx, r12\nlea rdx, ds:0Fh[rdx*4]\nmov rdi, rdx\nand rdx, 0FFFFFFFFFFFFF000h\nsub rsi, rdx\nand rdi, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rsi\njz short loc_1349\nloc_1334:\nsub rsp, 1000h\nor [rsp+1070h+var_78], 0\ncmp rsp, rsi\njnz short loc_1334\nloc_1349:\nand edi, 0FFFh\nsub rsp, rdi\ntest rdi, rdi\njnz loc_1576\nloc_135B:\nmov rsi, r11\nmov r15, rsp\nshr rsi, 2\ntest r13d, r13d\njs loc_140B\ntest eax, eax\njle loc_140B\nmov rdx, rsi\nmov [rbp+var_68], rsi\nmov r10, r15\nmov r9d, 0FFFFFFFFh\nmov [rbp+var_6C], eax\nneg rdx\nmov [rbp+var_60], r13d\nlea r8, [r15+rdx*4]\nmov [rbp+var_50], r15\nnop dword ptr [rax+rax+00000000h]\nloc_13A0:\nmov rdi, [rbp+var_68]\nmovsxd rbx, r9d\nadd r9d, 1\nmov [rbp+var_58], r11\nsetz r14b\nmov [rbp+var_5C], r9d\nxor eax, eax\nimul rbx, rdi\nmov [rbp+var_48], r8\nnop dword ptr [rax+00000000h]\nloc_13C8:\nmov r9d, eax\ntest eax, eax\njz short loc_13D4\ntest r14b, r14b\njz short loc_1440\nloc_13D4:\nxor edx, edx\nloc_13D6:\nmov [r10+rax*4], edx\nadd rax, 1\ncmp r12, rax\njnz short loc_13C8\nmov r11, [rbp+var_58]\nmov r8, [rbp+var_48]\nmov r9d, [rbp+var_5C]\nmov eax, [rbp+var_60]\nadd r10, r11\nadd r8, r11\ncmp r9d, eax\njnz short loc_13A0\nmovsxd r13, eax\nmov rsi, [rbp+var_68]\nmov eax, [rbp+var_6C]\nmov r15, [rbp+var_50]\nloc_140B:\nimul r13, rsi\nsub eax, 1\ncdqe\nadd rax, r13\nmov eax, [r15+rax*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz loc_1581\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1440:\nmov edi, [rcx+rax*4]\nmov r11d, eax\ncmp rax, 3\njbe loc_1570\nmov esi, eax\nmovd xmm6, edi\nmov r8, [rbp+var_48]\nxor edx, edx\nshr esi, 2\npshufd xmm3, xmm6, 0\npxor xmm2, xmm2\nshl rsi, 4\nnop dword ptr [rax+00h]\nloc_1470:\nmovdqu xmm4, xmmword ptr [rcx+rdx]\nmovdqu xmm5, xmmword ptr [r8+rdx]\nmovdqa xmm0, xmm3\nadd rdx, 10h\npsubd xmm0, xmm4\npaddd xmm0, xmm5\nmovdqa xmm1, xmm0\npcmpgtd xmm1, xmm2\npand xmm0, xmm1\npandn xmm1, xmm2\nmovdqa xmm2, xmm1\npor xmm2, xmm0\ncmp rsi, rdx\njnz short loc_1470\nmovdqa xmm1, xmm2\nmov esi, r11d\nmov [rbp+var_48], r8\npsrldq xmm1, 8\nand esi, 0FFFFFFFCh\nand r11d, 3\nmovdqa xmm0, xmm1\npcmpgtd xmm0, xmm2\npand xmm1, xmm0\npandn xmm0, xmm2\npor xmm0, xmm1\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\nmovdqa xmm1, xmm2\npcmpgtd xmm1, xmm0\npand xmm2, xmm1\npandn xmm1, xmm0\npor xmm1, xmm2\nmovd edx, xmm1\njz short loc_1558\nloc_14F6:\nmovsxd r11, esi\nmov r8, [rbp+var_50]\nmov r13d, edi\nlea r15, ds:0[r11*4]\nsub r13d, [rcx+r11*4]\nadd r11, rbx\nadd r13d, [r8+r11*4]\nlea r11d, [rsi+1]\ncmp edx, r13d\ncmovl edx, r13d\ncmp r11d, r9d\njge short loc_1558\nmovsxd r11, r11d\nmov r13d, edi\nsub r13d, [rcx+r15+4]\nadd r11, rbx\nadd r13d, [r8+r11*4]\ncmp edx, r13d\ncmovl edx, r13d\nadd esi, 2\ncmp esi, r9d\njge short loc_1558\nmovsxd rsi, esi\nsub edi, [rcx+r15+8]\nadd rsi, rbx\nadd edi, [r8+rsi*4]\ncmp edx, edi\ncmovl edx, edi\nloc_1558:\nmov esi, [r10+rax*4-4]\ncmp edx, esi\ncmovl edx, esi\njmp loc_13D6\nloc_1570:\nxor esi, esi\nxor edx, edx\njmp short loc_14F6\nloc_1576:\nor [rsp+rdi+1070h+var_1078], 0\njmp loc_135B\nloc_1581:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n __int64 v4; // r13\n __int64 v5; // r12\n int v6; // eax\n unsigned __int64 v7; // r11\n __int64 v8; // rdi\n _BYTE *v9; // rsi\n __int16 v10; // di\n signed __int64 v11; // rdi\n void *v12; // rsp\n _BYTE *v13; // r15\n unsigned __int64 v14; // rsi\n _BYTE *v15; // r10\n int v16; // r9d\n _BYTE *v17; // r8\n unsigned __int64 v18; // rax\n unsigned __int64 v19; // rbx\n int v20; // edx\n unsigned int v22; // edi\n __int64 v23; // rdx\n __m128i v24; // xmm3\n __m128i v25; // xmm2\n __m128i v26; // xmm4\n __m128i v27; // xmm5\n __m128i v28; // xmm0\n __m128i v29; // xmm1\n __m128i v30; // xmm1\n int v31; // esi\n __m128i v32; // xmm0\n __m128i v33; // xmm0\n __m128i v34; // xmm2\n __m128i v35; // xmm1\n __int64 v36; // r15\n int v37; // r11d\n int v38; // esi\n int v39; // edi\n _BYTE v41[4088]; // [rsp+8h] [rbp-1070h] BYREF\n _BYTE v42[4]; // [rsp+1008h] [rbp-70h] BYREF\n int v43; // [rsp+100Ch] [rbp-6Ch]\n unsigned __int64 v44; // [rsp+1010h] [rbp-68h]\n int v45; // [rsp+1018h] [rbp-60h]\n int v46; // [rsp+101Ch] [rbp-5Ch]\n unsigned __int64 v47; // [rsp+1020h] [rbp-58h]\n _BYTE *v48; // [rsp+1028h] [rbp-50h]\n _BYTE *v49; // [rsp+1030h] [rbp-48h]\n unsigned __int64 v50; // [rsp+1040h] [rbp-38h]\n\n v4 = a3;\n v5 = a2;\n v6 = a2;\n v7 = 4LL * a2;\n v50 = __readfsqword(0x28u);\n v8 = 4 * a2 * (__int64)(a3 + 1) + 15;\n v9 = &v42[-(v8 & 0xFFFFFFFFFFFFF000LL)];\n v10 = v8 & 0xFFF0;\n if ( v42 != v9 )\n {\n while ( v41 != v9 )\n ;\n }\n v11 = v10 & 0xFFF;\n v12 = alloca(v11);\n if ( v11 )\n *(_QWORD *)&v41[v11 - 8] = *(_QWORD *)&v41[v11 - 8];\n v13 = v41;\n v14 = v7 >> 2;\n if ( a3 >= 0 && v6 > 0 )\n {\n v44 = v7 >> 2;\n v15 = v41;\n v16 = -1;\n v43 = v6;\n v45 = a3;\n v17 = &v41[-4 * v14];\n v48 = v41;\n while ( 1 )\n {\n v47 = v7;\n v46 = v16 + 1;\n v18 = 0LL;\n v19 = v44 * v16;\n v49 = v17;\n do\n {\n if ( !(_DWORD)v18 || v16 == -1 )\n {\n v20 = 0;\n goto LABEL_12;\n }\n v22 = *(_DWORD *)(a1 + 4 * v18);\n if ( v18 <= 3 )\n {\n v31 = 0;\n v20 = 0;\nLABEL_20:\n v36 = 4LL * v31;\n v37 = v31 + 1;\n if ( v20 < (int)(*(_DWORD *)&v48[4 * v19 + 4 * v31] + v22 - *(_DWORD *)(a1 + v36)) )\n v20 = *(_DWORD *)&v48[4 * v19 + 4 * v31] + v22 - *(_DWORD *)(a1 + 4LL * v31);\n if ( v37 < (int)v18 )\n {\n if ( v20 < (int)(*(_DWORD *)&v48[4 * v19 + 4 * v37] + v22 - *(_DWORD *)(a1 + v36 + 4)) )\n v20 = *(_DWORD *)&v48[4 * v19 + 4 * v37] + v22 - *(_DWORD *)(a1 + v36 + 4);\n v38 = v31 + 2;\n if ( v38 < (int)v18 )\n {\n v39 = *(_DWORD *)&v48[4 * v19 + 4 * v38] + v22 - *(_DWORD *)(a1 + v36 + 8);\n if ( v20 < v39 )\n v20 = v39;\n }\n }\n goto LABEL_28;\n }\n v23 = 0LL;\n v24 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v22), 0);\n v25 = 0LL;\n do\n {\n v26 = _mm_loadu_si128((const __m128i *)(a1 + v23));\n v27 = _mm_loadu_si128((const __m128i *)&v49[v23]);\n v23 += 16LL;\n v28 = _mm_add_epi32(_mm_sub_epi32(v24, v26), v27);\n v29 = _mm_cmpgt_epi32(v28, v25);\n v25 = _mm_or_si128(_mm_andnot_si128(v29, v25), _mm_and_si128(v28, v29));\n }\n while ( 16LL * ((unsigned int)v18 >> 2) != v23 );\n v30 = _mm_srli_si128(v25, 8);\n v31 = v18 & 0xFFFFFFFC;\n v32 = _mm_cmpgt_epi32(v30, v25);\n v33 = _mm_or_si128(_mm_andnot_si128(v32, v25), _mm_and_si128(v30, v32));\n v34 = _mm_srli_si128(v33, 4);\n v35 = _mm_cmpgt_epi32(v34, v33);\n v20 = _mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v35, v33), _mm_and_si128(v34, v35)));\n if ( (v18 & 3) != 0 )\n goto LABEL_20;\nLABEL_28:\n if ( v20 < *(_DWORD *)&v15[4 * v18 - 4] )\n v20 = *(_DWORD *)&v15[4 * v18 - 4];\nLABEL_12:\n *(_DWORD *)&v15[4 * v18++] = v20;\n }\n while ( v5 != v18 );\n v7 = v47;\n v16 = v46;\n v15 += v47;\n v17 = &v49[v47];\n if ( v46 == v45 )\n {\n v4 = v45;\n v14 = v44;\n v6 = v43;\n v13 = v48;\n return *(unsigned int *)&v13[4 * v14 * v4 - 4 + 4 * v6];\n }\n }\n }\n return *(unsigned int *)&v13[4 * v14 * v4 - 4 + 4 * v6];\n}", + "ida_strip_asm": "sub_12D0:\nendbr64\npush rbp\nmov rcx, rdi\nmov rbp, rsp\npush r15\npush r14\npush r13\nmovsxd r13, edx\npush r12\nmovsxd r12, esi\npush rbx\nmov rax, r12\nlea r11, ds:0[r12*4]\nsub rsp, 48h\nmov rdx, fs:28h\nmov [rbp+var_38], rdx\nxor edx, edx\nlea edx, [r13+1]\nmov rsi, rsp\nmovsxd rdx, edx\nimul rdx, r12\nlea rdx, ds:0Fh[rdx*4]\nmov rdi, rdx\nand rdx, 0FFFFFFFFFFFFF000h\nsub rsi, rdx\nand rdi, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rsi\njz short loc_1349\nloc_1334:\nsub rsp, 1000h\nor [rsp+1070h+var_78], 0\ncmp rsp, rsi\njnz short loc_1334\nloc_1349:\nand edi, 0FFFh\nsub rsp, rdi\ntest rdi, rdi\njnz loc_1576\nloc_135B:\nmov rsi, r11\nmov r15, rsp\nshr rsi, 2\ntest r13d, r13d\njs loc_140B\ntest eax, eax\njle loc_140B\nmov rdx, rsi\nmov [rbp+var_68], rsi\nmov r10, r15\nmov r9d, 0FFFFFFFFh\nmov [rbp+var_6C], eax\nneg rdx\nmov [rbp+var_60], r13d\nlea r8, [r15+rdx*4]\nmov [rbp+var_50], r15\nnop dword ptr [rax+rax+00000000h]\nloc_13A0:\nmov rdi, [rbp+var_68]\nmovsxd rbx, r9d\nadd r9d, 1\nmov [rbp+var_58], r11\nsetz r14b\nmov [rbp+var_5C], r9d\nxor eax, eax\nimul rbx, rdi\nmov [rbp+var_48], r8\nnop dword ptr [rax+00000000h]\nloc_13C8:\nmov r9d, eax\ntest eax, eax\njz short loc_13D4\ntest r14b, r14b\njz short loc_1440\nloc_13D4:\nxor edx, edx\nloc_13D6:\nmov [r10+rax*4], edx\nadd rax, 1\ncmp r12, rax\njnz short loc_13C8\nmov r11, [rbp+var_58]\nmov r8, [rbp+var_48]\nmov r9d, [rbp+var_5C]\nmov eax, [rbp+var_60]\nadd r10, r11\nadd r8, r11\ncmp r9d, eax\njnz short loc_13A0\nmovsxd r13, eax\nmov rsi, [rbp+var_68]\nmov eax, [rbp+var_6C]\nmov r15, [rbp+var_50]\nloc_140B:\nimul r13, rsi\nsub eax, 1\ncdqe\nadd rax, r13\nmov eax, [r15+rax*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz loc_1581\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1440:\nmov edi, [rcx+rax*4]\nmov r11d, eax\ncmp rax, 3\njbe loc_1570\nmov esi, eax\nmovd xmm6, edi\nmov r8, [rbp+var_48]\nxor edx, edx\nshr esi, 2\npshufd xmm3, xmm6, 0\npxor xmm2, xmm2\nshl rsi, 4\nnop dword ptr [rax+00h]\nloc_1470:\nmovdqu xmm4, xmmword ptr [rcx+rdx]\nmovdqu xmm5, xmmword ptr [r8+rdx]\nmovdqa xmm0, xmm3\nadd rdx, 10h\npsubd xmm0, xmm4\npaddd xmm0, xmm5\nmovdqa xmm1, xmm0\npcmpgtd xmm1, xmm2\npand xmm0, xmm1\npandn xmm1, xmm2\nmovdqa xmm2, xmm1\npor xmm2, xmm0\ncmp rsi, rdx\njnz short loc_1470\nmovdqa xmm1, xmm2\nmov esi, r11d\nmov [rbp+var_48], r8\npsrldq xmm1, 8\nand esi, 0FFFFFFFCh\nand r11d, 3\nmovdqa xmm0, xmm1\npcmpgtd xmm0, xmm2\npand xmm1, xmm0\npandn xmm0, xmm2\npor xmm0, xmm1\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\nmovdqa xmm1, xmm2\npcmpgtd xmm1, xmm0\npand xmm2, xmm1\npandn xmm1, xmm0\npor xmm1, xmm2\nmovd edx, xmm1\njz short loc_1558\nloc_14F6:\nmovsxd r11, esi\nmov r8, [rbp+var_50]\nmov r13d, edi\nlea r15, ds:0[r11*4]\nsub r13d, [rcx+r11*4]\nadd r11, rbx\nadd r13d, [r8+r11*4]\nlea r11d, [rsi+1]\ncmp edx, r13d\ncmovl edx, r13d\ncmp r11d, r9d\njge short loc_1558\nmovsxd r11, r11d\nmov r13d, edi\nsub r13d, [rcx+r15+4]\nadd r11, rbx\nadd r13d, [r8+r11*4]\ncmp edx, r13d\ncmovl edx, r13d\nadd esi, 2\ncmp esi, r9d\njge short loc_1558\nmovsxd rsi, esi\nsub edi, [rcx+r15+8]\nadd rsi, rbx\nadd edi, [r8+rsi*4]\ncmp edx, edi\ncmovl edx, edi\nloc_1558:\nmov esi, [r10+rax*4-4]\ncmp edx, esi\ncmovl edx, esi\njmp loc_13D6\nloc_1570:\nxor esi, esi\nxor edx, edx\njmp short loc_14F6\nloc_1576:\nor [rsp+rdi+1070h+var_1078], 0\njmp loc_135B\nloc_1581:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12D0(__int64 a1, int a2, int a3)\n{\n __int64 v4; // r13\n __int64 v5; // r12\n int v6; // eax\n unsigned __int64 v7; // r11\n __int64 v8; // rdi\n _BYTE *v9; // rsi\n __int16 v10; // di\n signed __int64 v11; // rdi\n void *v12; // rsp\n _BYTE *v13; // r15\n unsigned __int64 v14; // rsi\n _BYTE *v15; // r10\n int v16; // r9d\n _BYTE *v17; // r8\n unsigned __int64 v18; // rax\n unsigned __int64 v19; // rbx\n int v20; // edx\n unsigned int v22; // edi\n __int64 v23; // rdx\n __m128i v24; // xmm3\n __m128i v25; // xmm2\n __m128i v26; // xmm4\n __m128i v27; // xmm5\n __m128i v28; // xmm0\n __m128i v29; // xmm1\n __m128i v30; // xmm1\n int v31; // esi\n __m128i v32; // xmm0\n __m128i v33; // xmm0\n __m128i v34; // xmm2\n __m128i v35; // xmm1\n __int64 v36; // r15\n int v37; // r11d\n int v38; // esi\n int v39; // edi\n _BYTE v41[4088]; // [rsp+8h] [rbp-1070h] BYREF\n _BYTE v42[4]; // [rsp+1008h] [rbp-70h] BYREF\n int v43; // [rsp+100Ch] [rbp-6Ch]\n unsigned __int64 v44; // [rsp+1010h] [rbp-68h]\n int v45; // [rsp+1018h] [rbp-60h]\n int v46; // [rsp+101Ch] [rbp-5Ch]\n unsigned __int64 v47; // [rsp+1020h] [rbp-58h]\n _BYTE *v48; // [rsp+1028h] [rbp-50h]\n _BYTE *v49; // [rsp+1030h] [rbp-48h]\n unsigned __int64 v50; // [rsp+1040h] [rbp-38h]\n\n v4 = a3;\n v5 = a2;\n v6 = a2;\n v7 = 4LL * a2;\n v50 = __readfsqword(0x28u);\n v8 = 4 * a2 * (__int64)(a3 + 1) + 15;\n v9 = &v42[-(v8 & 0xFFFFFFFFFFFFF000LL)];\n v10 = v8 & 0xFFF0;\n if ( v42 != v9 )\n {\n while ( v41 != v9 )\n ;\n }\n v11 = v10 & 0xFFF;\n v12 = alloca(v11);\n if ( v11 )\n *(_QWORD *)&v41[v11 - 8] = *(_QWORD *)&v41[v11 - 8];\n v13 = v41;\n v14 = v7 >> 2;\n if ( a3 >= 0 && v6 > 0 )\n {\n v44 = v7 >> 2;\n v15 = v41;\n v16 = -1;\n v43 = v6;\n v45 = a3;\n v17 = &v41[-4 * v14];\n v48 = v41;\n while ( 1 )\n {\n v47 = v7;\n v46 = v16 + 1;\n v18 = 0LL;\n v19 = v44 * v16;\n v49 = v17;\n do\n {\n if ( !(_DWORD)v18 || v16 == -1 )\n {\n v20 = 0;\n goto LABEL_12;\n }\n v22 = *(_DWORD *)(a1 + 4 * v18);\n if ( v18 <= 3 )\n {\n v31 = 0;\n v20 = 0;\nLABEL_20:\n v36 = 4LL * v31;\n v37 = v31 + 1;\n if ( v20 < (int)(*(_DWORD *)&v48[4 * v19 + 4 * v31] + v22 - *(_DWORD *)(a1 + v36)) )\n v20 = *(_DWORD *)&v48[4 * v19 + 4 * v31] + v22 - *(_DWORD *)(a1 + 4LL * v31);\n if ( v37 < (int)v18 )\n {\n if ( v20 < (int)(*(_DWORD *)&v48[4 * v19 + 4 * v37] + v22 - *(_DWORD *)(a1 + v36 + 4)) )\n v20 = *(_DWORD *)&v48[4 * v19 + 4 * v37] + v22 - *(_DWORD *)(a1 + v36 + 4);\n v38 = v31 + 2;\n if ( v38 < (int)v18 )\n {\n v39 = *(_DWORD *)&v48[4 * v19 + 4 * v38] + v22 - *(_DWORD *)(a1 + v36 + 8);\n if ( v20 < v39 )\n v20 = v39;\n }\n }\n goto LABEL_28;\n }\n v23 = 0LL;\n v24 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v22), 0);\n v25 = 0LL;\n do\n {\n v26 = _mm_loadu_si128((const __m128i *)(a1 + v23));\n v27 = _mm_loadu_si128((const __m128i *)&v49[v23]);\n v23 += 16LL;\n v28 = _mm_add_epi32(_mm_sub_epi32(v24, v26), v27);\n v29 = _mm_cmpgt_epi32(v28, v25);\n v25 = _mm_or_si128(_mm_andnot_si128(v29, v25), _mm_and_si128(v28, v29));\n }\n while ( 16LL * ((unsigned int)v18 >> 2) != v23 );\n v30 = _mm_srli_si128(v25, 8);\n v31 = v18 & 0xFFFFFFFC;\n v32 = _mm_cmpgt_epi32(v30, v25);\n v33 = _mm_or_si128(_mm_andnot_si128(v32, v25), _mm_and_si128(v30, v32));\n v34 = _mm_srli_si128(v33, 4);\n v35 = _mm_cmpgt_epi32(v34, v33);\n v20 = _mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v35, v33), _mm_and_si128(v34, v35)));\n if ( (v18 & 3) != 0 )\n goto LABEL_20;\nLABEL_28:\n if ( v20 < *(_DWORD *)&v15[4 * v18 - 4] )\n v20 = *(_DWORD *)&v15[4 * v18 - 4];\nLABEL_12:\n *(_DWORD *)&v15[4 * v18++] = v20;\n }\n while ( v5 != v18 );\n v7 = v47;\n v16 = v46;\n v15 += v47;\n v17 = &v49[v47];\n if ( v46 == v45 )\n {\n v4 = v45;\n v14 = v44;\n v6 = v43;\n v13 = v48;\n return *(unsigned int *)&v13[4 * v14 * v4 - 4 + 4 * v6];\n }\n }\n }\n return *(unsigned int *)&v13[4 * v14 * v4 - 4 + 4 * v6];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12D0(long long a1, int a2, int a3) {\n long long v4;\n long long v5;\n int v6;\n unsigned long long v7;\n long long v8;\n uint8_t *v9;\n short v10;\n signed long long v11;\n void *v12;\n uint8_t *v13;\n unsigned long long v14;\n uint8_t *v15;\n int v16;\n uint8_t *v17;\n unsigned long long v18;\n unsigned long long v19;\n int v20;\n unsigned int v22;\n long long v23;\n __m128i v24;\n __m128i v25;\n __m128i v26;\n __m128i v27;\n __m128i v28;\n __m128i v29;\n __m128i v30;\n int v31;\n __m128i v32;\n __m128i v33;\n __m128i v34;\n __m128i v35;\n long long v36;\n int v37;\n int v38;\n int v39;\n uint8_t v41[4088];\n uint8_t v42[4];\n int v43;\n unsigned long long v44;\n int v45;\n int v46;\n unsigned long long v47;\n uint8_t *v48;\n uint8_t *v49;\n unsigned long long v50;\n v4 = a3;\n v5 = a2;\n v6 = a2;\n v7 = 4LL * a2;\n v50 = __readfsqword(40u);\n v8 = 4 * a2 * (long long)(a3 + 1) + 15;\n v9 = &v42[-(v8 & 18446744073709547520LL)];\n v10 = v8 & 65520;\n if (v42 != v9) {\n while (v41 != v9)\n ;\n }\n v11 = v10 & 4095;\n v12 = alloca(v11);\n if (v11) *(uint64_t *)&v41[v11 - 8] = *(uint64_t *)&v41[v11 - 8];\n v13 = v41;\n v14 = v7 >> 2;\n if (a3 >= 0 && v6 > 0) {\n v44 = v7 >> 2;\n v15 = v41;\n v16 = -1;\n v43 = v6;\n v45 = a3;\n v17 = &v41[-4 * v14];\n v48 = v41;\n while (1) {\n v47 = v7;\n v46 = v16 + 1;\n v18 = 0LL;\n v19 = v44 * v16;\n v49 = v17;\n do {\n if (!(uint32_t)v18 || v16 == -1) {\n v20 = 0;\n goto LABEL_12;\n }\n v22 = *(uint32_t *)(a1 + 4 * v18);\n if (v18 <= 3) {\n v31 = 0;\n v20 = 0;\n LABEL_20:\n v36 = 4LL * v31;\n v37 = v31 + 1;\n if (v20 < (int)(*(uint32_t *)&v48[4 * v19 + 4 * v31] + v22 -\n *(uint32_t *)(a1 + v36)))\n v20 = *(uint32_t *)&v48[4 * v19 + 4 * v31] + v22 -\n *(uint32_t *)(a1 + 4LL * v31);\n if (v37 < (int)v18) {\n if (v20 < (int)(*(uint32_t *)&v48[4 * v19 + 4 * v37] + v22 -\n *(uint32_t *)(a1 + v36 + 4)))\n v20 = *(uint32_t *)&v48[4 * v19 + 4 * v37] + v22 -\n *(uint32_t *)(a1 + v36 + 4);\n v38 = v31 + 2;\n if (v38 < (int)v18) {\n v39 = *(uint32_t *)&v48[4 * v19 + 4 * v38] + v22 -\n *(uint32_t *)(a1 + v36 + 8);\n if (v20 < v39) v20 = v39;\n }\n }\n goto LABEL_28;\n }\n v23 = 0LL;\n v24 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v22), 0);\n v25 = 0LL;\n do {\n v26 = _mm_loadu_si128((const __m128i *)(a1 + v23));\n v27 = _mm_loadu_si128((const __m128i *)&v49[v23]);\n v23 += 16LL;\n v28 = _mm_add_epi32(_mm_sub_epi32(v24, v26), v27);\n v29 = _mm_cmpgt_epi32(v28, v25);\n v25 =\n _mm_or_si128(_mm_andnot_si128(v29, v25), _mm_and_si128(v28, v29));\n } while (16LL * ((unsigned int)v18 >> 2) != v23);\n v30 = _mm_srli_si128(v25, 8);\n v31 = v18 & 4294967292;\n v32 = _mm_cmpgt_epi32(v30, v25);\n v33 = _mm_or_si128(_mm_andnot_si128(v32, v25), _mm_and_si128(v30, v32));\n v34 = _mm_srli_si128(v33, 4);\n v35 = _mm_cmpgt_epi32(v34, v33);\n v20 = _mm_cvtsi128_si32(\n _mm_or_si128(_mm_andnot_si128(v35, v33), _mm_and_si128(v34, v35)));\n if ((v18 & 3) != 0) goto LABEL_20;\n LABEL_28:\n if (v20 < *(uint32_t *)&v15[4 * v18 - 4])\n v20 = *(uint32_t *)&v15[4 * v18 - 4];\n LABEL_12:\n *(uint32_t *)&v15[4 * v18++] = v20;\n } while (v5 != v18);\n v7 = v47;\n v16 = v46;\n v15 += v47;\n v17 = &v49[v47];\n if (v46 == v45) {\n v4 = v45;\n v14 = v44;\n v6 = v43;\n v13 = v48;\n return *(unsigned int *)&v13[4 * v14 * v4 - 4 + 4 * v6];\n }\n }\n }\n return *(unsigned int *)&v13[4 * v14 * v4 - 4 + 4 * v6];\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n long long v4;\n long long v5;\n int v6;\n unsigned long long v7;\n long long v8;\n uint8_t *v9;\n short v10;\n signed long long v11;\n void *v12;\n uint8_t *v13;\n unsigned long long v14;\n uint8_t *v15;\n int v16;\n uint8_t *v17;\n unsigned long long v18;\n unsigned long long v19;\n int v20;\n unsigned int v22;\n long long v23;\n __m128i v24;\n __m128i v25;\n __m128i v26;\n __m128i v27;\n __m128i v28;\n __m128i v29;\n __m128i v30;\n int v31;\n __m128i v32;\n __m128i v33;\n __m128i v34;\n __m128i v35;\n long long v36;\n int v37;\n int v38;\n int v39;\n uint8_t v41[4088];\n uint8_t v42[4];\n int v43;\n unsigned long long v44;\n int v45;\n int v46;\n unsigned long long v47;\n uint8_t *v48;\n uint8_t *v49;\n unsigned long long v50;\n v4 = a3;\n v5 = a2;\n v6 = a2;\n v7 = 4LL * a2;\n v50 = __readfsqword(40u);\n v8 = 4 * a2 * (long long)(a3 + 1) + 15;\n v9 = &v42[-(v8 & 18446744073709547520LL)];\n v10 = v8 & 65520;\n if (v42 != v9) {\n while (v41 != v9)\n ;\n }\n v11 = v10 & 4095;\n v12 = alloca(v11);\n if (v11) *(uint64_t *)&v41[v11 - 8] = *(uint64_t *)&v41[v11 - 8];\n v13 = v41;\n v14 = v7 >> 2;\n if (a3 >= 0 && v6 > 0) {\n v44 = v7 >> 2;\n v15 = v41;\n v16 = -1;\n v43 = v6;\n v45 = a3;\n v17 = &v41[-4 * v14];\n v48 = v41;\n while (1) {\n v47 = v7;\n v46 = v16 + 1;\n v18 = 0LL;\n v19 = v44 * v16;\n v49 = v17;\n do {\n if (!(uint32_t)v18 || v16 == -1) {\n v20 = 0;\n goto LABEL_12;\n }\n v22 = *(uint32_t *)(a1 + 4 * v18);\n if (v18 <= 3) {\n v31 = 0;\n v20 = 0;\n LABEL_20:\n v36 = 4LL * v31;\n v37 = v31 + 1;\n if (v20 < (int)(*(uint32_t *)&v48[4 * v19 + 4 * v31] + v22 -\n *(uint32_t *)(a1 + v36)))\n v20 = *(uint32_t *)&v48[4 * v19 + 4 * v31] + v22 -\n *(uint32_t *)(a1 + 4LL * v31);\n if (v37 < (int)v18) {\n if (v20 < (int)(*(uint32_t *)&v48[4 * v19 + 4 * v37] + v22 -\n *(uint32_t *)(a1 + v36 + 4)))\n v20 = *(uint32_t *)&v48[4 * v19 + 4 * v37] + v22 -\n *(uint32_t *)(a1 + v36 + 4);\n v38 = v31 + 2;\n if (v38 < (int)v18) {\n v39 = *(uint32_t *)&v48[4 * v19 + 4 * v38] + v22 -\n *(uint32_t *)(a1 + v36 + 8);\n if (v20 < v39) v20 = v39;\n }\n }\n goto LABEL_28;\n }\n v23 = 0LL;\n v24 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v22), 0);\n v25 = 0LL;\n do {\n v26 = _mm_loadu_si128((const __m128i *)(a1 + v23));\n v27 = _mm_loadu_si128((const __m128i *)&v49[v23]);\n v23 += 16LL;\n v28 = _mm_add_epi32(_mm_sub_epi32(v24, v26), v27);\n v29 = _mm_cmpgt_epi32(v28, v25);\n v25 =\n _mm_or_si128(_mm_andnot_si128(v29, v25), _mm_and_si128(v28, v29));\n } while (16LL * ((unsigned int)v18 >> 2) != v23);\n v30 = _mm_srli_si128(v25, 8);\n v31 = v18 & 4294967292;\n v32 = _mm_cmpgt_epi32(v30, v25);\n v33 = _mm_or_si128(_mm_andnot_si128(v32, v25), _mm_and_si128(v30, v32));\n v34 = _mm_srli_si128(v33, 4);\n v35 = _mm_cmpgt_epi32(v34, v33);\n v20 = _mm_cvtsi128_si32(\n _mm_or_si128(_mm_andnot_si128(v35, v33), _mm_and_si128(v34, v35)));\n if ((v18 & 3) != 0) goto LABEL_20;\n LABEL_28:\n if (v20 < *(uint32_t *)&v15[4 * v18 - 4])\n v20 = *(uint32_t *)&v15[4 * v18 - 4];\n LABEL_12:\n *(uint32_t *)&v15[4 * v18++] = v20;\n } while (v5 != v18);\n v7 = v47;\n v16 = v46;\n v15 += v47;\n v17 = &v49[v47];\n if (v46 == v45) {\n v4 = v45;\n v14 = v44;\n v6 = v43;\n v13 = v48;\n return *(unsigned int *)&v13[4 * v14 * v4 - 4 + 4 * v6];\n }\n }\n }\n return *(unsigned int *)&v13[4 * v14 * v4 - 4 + 4 * v6];\n}" + }, + { + "index": 470, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(const int test_tup[], int size, int result[]) {\n for (int i = 0; i < size - 1; i++) {\n result[i] = test_tup[i] + test_tup[i + 1];\n }\n}", + "test": "int main() {\n\n int result[4];\n\n\n\n int test1[] = {1, 5, 7, 8, 10};\n\n func0(test1, 5, result);\n\n assert(result[0] == 6 && result[1] == 12 && result[2] == 15 && result[3] == 18);\n\n\n\n int test2[] = {2, 6, 8, 9, 11};\n\n func0(test2, 5, result);\n\n assert(result[0] == 8 && result[1] == 14 && result[2] == 17 && result[3] == 20);\n\n\n\n int test3[] = {3, 7, 9, 10, 12};\n\n func0(test3, 5, result);\n\n assert(result[0] == 10 && result[1] == 16 && result[2] == 19 && result[3] == 22);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11d1 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%ecx\nmov -0x4(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rsi\nmov -0x28(%rbp),%rax\nadd %rsi,%rax\nadd %ecx,%edx\nmov %edx,(%rax)\naddl $0x1,-0x4(%rbp)\nmov -0x1c(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x4(%rbp)\njl 1185 \npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_4], 0\njmp short loc_11D1\nloc_1185:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov ecx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rsi, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rsi\nadd edx, ecx\nmov [rax], edx\nadd [rbp+var_4], 1\nloc_11D1:\nmov eax, [rbp+var_1C]\nsub eax, 1\ncmp [rbp+var_4], eax\njl short loc_1185\nnop\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3)\n{\n __int64 result; // rax\n int i; // [rsp+24h] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = (unsigned int)(a2 - 1);\n if ( i >= (int)result )\n break;\n *(_DWORD *)(4LL * i + a3) = *(_DWORD *)(4LL * i + a1) + *(_DWORD *)(4 * (i + 1LL) + a1);\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_4], 0\njmp short loc_11D1\nloc_1185:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov ecx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rsi, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rsi\nadd edx, ecx\nmov [rax], edx\nadd [rbp+var_4], 1\nloc_11D1:\nmov eax, [rbp+var_1C]\nsub eax, 1\ncmp [rbp+var_4], eax\njl short loc_1185\nnop\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, __int64 a3)\n{\n __int64 result; // rax\n int i; // [rsp+24h] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = (unsigned int)(a2 - 1);\n if ( i >= (int)result )\n break;\n *(_DWORD *)(4LL * i + a3) = *(_DWORD *)(4LL * i + a1) + *(_DWORD *)(4 * (i + 1LL) + a1);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, long long a3) {\n long long result;\n int i;\n for (i = 0;; ++i) {\n result = (unsigned int)(a2 - 1);\n if (i >= (int)result) break;\n *(uint32_t *)(4LL * i + a3) =\n *(uint32_t *)(4LL * i + a1) + *(uint32_t *)(4 * (i + 1LL) + a1);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3) {\n long long result;\n int i;\n for (i = 0;; ++i) {\n result = (unsigned int)(a2 - 1);\n if (i >= (int)result) break;\n *(uint32_t *)(4LL * i + a3) =\n *(uint32_t *)(4LL * i + a1) + *(uint32_t *)(4 * (i + 1LL) + a1);\n }\n return result;\n}" + }, + { + "index": 470, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(const int test_tup[], int size, int result[]) {\n for (int i = 0; i < size - 1; i++) {\n result[i] = test_tup[i] + test_tup[i + 1];\n }\n}", + "test": "int main() {\n\n int result[4];\n\n\n\n int test1[] = {1, 5, 7, 8, 10};\n\n func0(test1, 5, result);\n\n assert(result[0] == 6 && result[1] == 12 && result[2] == 15 && result[3] == 18);\n\n\n\n int test2[] = {2, 6, 8, 9, 11};\n\n func0(test2, 5, result);\n\n assert(result[0] == 8 && result[1] == 14 && result[2] == 17 && result[3] == 20);\n\n\n\n int test3[] = {3, 7, 9, 10, 12};\n\n func0(test3, 5, result);\n\n assert(result[0] == 10 && result[1] == 16 && result[2] == 19 && result[3] == 22);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%esi\njle 1190 \nlea -0x2(%rsi),%esi\nmov $0x0,%eax\nmov 0x4(%rdi,%rax,4),%ecx\nadd (%rdi,%rax,4),%ecx\nmov %ecx,(%rdx,%rax,4)\nmov %rax,%rcx\nadd $0x1,%rax\ncmp %rsi,%rcx\njne 117a \nretq\n", + "ida_asm": "func0:\nendbr64\ncmp esi, 1\njle short locret_118D\nlea esi, [rsi-1]\nmov eax, 0\nloc_117A:\nmov ecx, [rdi+rax*4+4]\nadd ecx, [rdi+rax*4]\nmov [rdx+rax*4], ecx\nadd rax, 1\ncmp rax, rsi\njnz short loc_117A\nlocret_118D:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2, __int64 a3)\n{\n __int64 v3; // rsi\n __int64 v4; // rax\n\n if ( a2 > 1 )\n {\n v3 = (unsigned int)(a2 - 1);\n v4 = 0LL;\n do\n {\n *(_DWORD *)(a3 + 4 * v4) = *(_DWORD *)(a1 + 4 * v4) + *(_DWORD *)(a1 + 4 * v4 + 4);\n ++v4;\n }\n while ( v4 != v3 );\n }\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ncmp esi, 1\njle short locret_118D\nlea esi, [rsi-1]\nmov eax, 0\nloc_117A:\nmov ecx, [rdi+rax*4+4]\nadd ecx, [rdi+rax*4]\nmov [rdx+rax*4], ecx\nadd rax, 1\ncmp rax, rsi\njnz short loc_117A\nlocret_118D:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1169(__int64 a1, int a2, __int64 a3)\n{\n __int64 v3; // rsi\n __int64 v4; // rax\n\n if ( a2 > 1 )\n {\n v3 = (unsigned int)(a2 - 1);\n v4 = 0LL;\n do\n {\n *(_DWORD *)(a3 + 4 * v4) = *(_DWORD *)(a1 + 4 * v4) + *(_DWORD *)(a1 + 4 * v4 + 4);\n ++v4;\n }\n while ( v4 != v3 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1169(long long a1, int a2, long long a3) {\n long long v3;\n long long v4;\n if (a2 > 1) {\n v3 = (unsigned int)(a2 - 1);\n v4 = 0LL;\n do {\n *(uint32_t *)(a3 + 4 * v4) =\n *(uint32_t *)(a1 + 4 * v4) + *(uint32_t *)(a1 + 4 * v4 + 4);\n ++v4;\n } while (v4 != v3);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2, long long a3) {\n long long v3;\n long long v4;\n if (a2 > 1) {\n v3 = (unsigned int)(a2 - 1);\n v4 = 0LL;\n do {\n *(uint32_t *)(a3 + 4 * v4) =\n *(uint32_t *)(a1 + 4 * v4) + *(uint32_t *)(a1 + 4 * v4 + 4);\n ++v4;\n } while (v4 != v3);\n }\n}" + }, + { + "index": 470, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(const int test_tup[], int size, int result[]) {\n for (int i = 0; i < size - 1; i++) {\n result[i] = test_tup[i] + test_tup[i + 1];\n }\n}", + "test": "int main() {\n\n int result[4];\n\n\n\n int test1[] = {1, 5, 7, 8, 10};\n\n func0(test1, 5, result);\n\n assert(result[0] == 6 && result[1] == 12 && result[2] == 15 && result[3] == 18);\n\n\n\n int test2[] = {2, 6, 8, 9, 11};\n\n func0(test2, 5, result);\n\n assert(result[0] == 8 && result[1] == 14 && result[2] == 17 && result[3] == 20);\n\n\n\n int test3[] = {3, 7, 9, 10, 12};\n\n func0(test3, 5, result);\n\n assert(result[0] == 10 && result[1] == 16 && result[2] == 19 && result[3] == 22);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%esi\njle 1166 \nsub $0x2,%esi\nxor %eax,%eax\nxchg %ax,%ax\nmov 0x4(%rdi,%rax,4),%ecx\nadd (%rdi,%rax,4),%ecx\nmov %ecx,(%rdx,%rax,4)\nmov %rax,%rcx\nadd $0x1,%rax\ncmp %rsi,%rcx\njne 1150 \nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ncmp esi, 1\njle short locret_1313\nsub esi, 1\nxor eax, eax\nxchg ax, ax\nloc_1300:\nmov ecx, [rdi+rax*4+4]\nadd ecx, [rdi+rax*4]\nmov [rdx+rax*4], ecx\nadd rax, 1\ncmp rsi, rax\njnz short loc_1300\nlocret_1313:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2, __int64 a3)\n{\n __int64 v3; // rsi\n __int64 v4; // rax\n\n if ( a2 > 1 )\n {\n v3 = (unsigned int)(a2 - 1);\n v4 = 0LL;\n do\n {\n *(_DWORD *)(a3 + 4 * v4) = *(_DWORD *)(a1 + 4 * v4) + *(_DWORD *)(a1 + 4 * v4 + 4);\n ++v4;\n }\n while ( v3 != v4 );\n }\n}", + "ida_strip_asm": "sub_12F0:\nendbr64\ncmp esi, 1\njle short locret_1313\nsub esi, 1\nxor eax, eax\nxchg ax, ax\nloc_1300:\nmov ecx, [rdi+rax*4+4]\nadd ecx, [rdi+rax*4]\nmov [rdx+rax*4], ecx\nadd rax, 1\ncmp rsi, rax\njnz short loc_1300\nlocret_1313:\nretn", + "ida_strip_pseudo": "void __fastcall sub_12F0(__int64 a1, int a2, __int64 a3)\n{\n __int64 v3; // rsi\n __int64 v4; // rax\n\n if ( a2 > 1 )\n {\n v3 = (unsigned int)(a2 - 1);\n v4 = 0LL;\n do\n {\n *(_DWORD *)(a3 + 4 * v4) = *(_DWORD *)(a1 + 4 * v4) + *(_DWORD *)(a1 + 4 * v4 + 4);\n ++v4;\n }\n while ( v3 != v4 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_12F0(long long a1, int a2, long long a3) {\n long long v3;\n long long v4;\n if (a2 > 1) {\n v3 = (unsigned int)(a2 - 1);\n v4 = 0LL;\n do {\n *(uint32_t *)(a3 + 4 * v4) =\n *(uint32_t *)(a1 + 4 * v4) + *(uint32_t *)(a1 + 4 * v4 + 4);\n ++v4;\n } while (v3 != v4);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2, long long a3) {\n long long v3;\n long long v4;\n if (a2 > 1) {\n v3 = (unsigned int)(a2 - 1);\n v4 = 0LL;\n do {\n *(uint32_t *)(a3 + 4 * v4) =\n *(uint32_t *)(a1 + 4 * v4) + *(uint32_t *)(a1 + 4 * v4 + 4);\n ++v4;\n } while (v3 != v4);\n }\n}" + }, + { + "index": 471, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int lens, int n) {\n int mul = 1;\n for (int i = 0; i < lens; i++) {\n mul = (mul * (arr[i] % n)) % n;\n }\n return mul % n;\n}", + "test": "int main() {\n\n int arr1[] = {100, 10, 5, 25, 35, 14};\n\n assert(func0(arr1, 6, 11) == 9);\n\n \n\n int arr2[] = {1, 1, 1};\n\n assert(func0(arr2, 3, 1) == 0);\n\n \n\n int arr3[] = {1, 2, 1};\n\n assert(func0(arr3, 3, 2) == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmovl $0x1,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11b6 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncltd\nidivl -0x20(%rbp)\nmov %edx,%eax\nimul -0x8(%rbp),%eax\ncltd\nidivl -0x20(%rbp)\nmov %edx,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 118b \nmov -0x8(%rbp),%eax\ncltd\nidivl -0x20(%rbp)\nmov %edx,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_8], 1\nmov [rbp+var_4], 0\njmp short loc_11B6\nloc_118B:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncdq\nidiv [rbp+var_20]\nmov eax, edx\nimul eax, [rbp+var_8]\ncdq\nidiv [rbp+var_20]\nmov [rbp+var_8], edx\nadd [rbp+var_4], 1\nloc_11B6:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_118B\nmov eax, [rbp+var_8]\ncdq\nidiv [rbp+var_20]\nmov eax, edx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n int v4; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v4 = 1;\n for ( i = 0; i < a2; ++i )\n v4 = v4 * (*(_DWORD *)(4LL * i + a1) % a3) % a3;\n return (unsigned int)(v4 % a3);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_8], 1\nmov [rbp+var_4], 0\njmp short loc_11B6\nloc_118B:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncdq\nidiv [rbp+var_20]\nmov eax, edx\nimul eax, [rbp+var_8]\ncdq\nidiv [rbp+var_20]\nmov [rbp+var_8], edx\nadd [rbp+var_4], 1\nloc_11B6:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_118B\nmov eax, [rbp+var_8]\ncdq\nidiv [rbp+var_20]\nmov eax, edx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n int v4; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v4 = 1;\n for ( i = 0; i < a2; ++i )\n v4 = v4 * (*(_DWORD *)(4LL * i + a1) % a3) % a3;\n return (unsigned int)(v4 % a3);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n int v4;\n int i;\n v4 = 1;\n for (i = 0; i < a2; ++i) v4 = v4 * (*(uint32_t *)(4LL * i + a1) % a3) % a3;\n return (unsigned int)(v4 % a3);\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n int v4;\n int i;\n v4 = 1;\n for (i = 0; i < a2; ++i) v4 = v4 * (*(uint32_t *)(4LL * i + a1) % a3) % a3;\n return (unsigned int)(v4 % a3);\n}" + }, + { + "index": 471, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int lens, int n) {\n int mul = 1;\n for (int i = 0; i < lens; i++) {\n mul = (mul * (arr[i] % n)) % n;\n }\n return mul % n;\n}", + "test": "int main() {\n\n int arr1[] = {100, 10, 5, 25, 35, 14};\n\n assert(func0(arr1, 6, 11) == 9);\n\n \n\n int arr2[] = {1, 1, 1};\n\n assert(func0(arr2, 3, 1) == 0);\n\n \n\n int arr3[] = {1, 2, 1};\n\n assert(func0(arr3, 3, 2) == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %edx,%r8d\ntest %esi,%esi\njle 11a8 \nmov %rdi,%r9\nlea -0x1(%rsi),%eax\nlea 0x4(%rdi,%rax,4),%rsi\nmov $0x1,%ecx\nmov (%r9),%eax\ncltd\nidiv %r8d\nmov %edx,%eax\nimul %ecx,%eax\ncltd\nidiv %r8d\nmov %edx,%ecx\nadd $0x4,%r9\ncmp %rsi,%r9\njne 1184 \nmov %ecx,%eax\ncltd\nidiv %r8d\nmov %edx,%eax\nretq\nmov $0x1,%ecx\njmp 119f \n", + "ida_asm": "func0:\nendbr64\nmov ecx, edx\ntest esi, esi\njle short loc_11A3\nmov r8, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*4]\nmov esi, 1\nloc_1182:\nmov eax, [r8]\ncdq\nidiv ecx\nmov eax, edx\nimul eax, esi\ncdq\nidiv ecx\nmov esi, edx\nadd r8, 4\ncmp r8, rdi\njnz short loc_1182\nloc_119B:\nmov eax, esi\ncdq\nidiv ecx\nmov eax, edx\nretn\nloc_11A3:\nmov esi, 1\njmp short loc_119B", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2, int a3)\n{\n _DWORD *v3; // r8\n _DWORD *v4; // rdi\n int v5; // esi\n\n if ( a2 <= 0 )\n {\n v5 = 1;\n }\n else\n {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 1;\n do\n v5 = v5 * (*v3++ % a3) % a3;\n while ( v3 != v4 );\n }\n return (unsigned int)(v5 % a3);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov ecx, edx\ntest esi, esi\njle short loc_11A3\nmov r8, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*4]\nmov esi, 1\nloc_1182:\nmov eax, [r8]\ncdq\nidiv ecx\nmov eax, edx\nimul eax, esi\ncdq\nidiv ecx\nmov esi, edx\nadd r8, 4\ncmp r8, rdi\njnz short loc_1182\nloc_119B:\nmov eax, esi\ncdq\nidiv ecx\nmov eax, edx\nretn\nloc_11A3:\nmov esi, 1\njmp short loc_119B", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2, int a3)\n{\n _DWORD *v3; // r8\n _DWORD *v4; // rdi\n int v5; // esi\n\n if ( a2 <= 0 )\n {\n v5 = 1;\n }\n else\n {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 1;\n do\n v5 = v5 * (*v3++ % a3) % a3;\n while ( v3 != v4 );\n }\n return (unsigned int)(v5 % a3);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2, int a3) {\n uint32_t *v3;\n uint32_t *v4;\n int v5;\n if (a2 <= 0) {\n v5 = 1;\n } else {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 1;\n do\n v5 = v5 * (*v3++ % a3) % a3;\n while (v3 != v4);\n }\n return (unsigned int)(v5 % a3);\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2, int a3) {\n uint32_t *v3;\n uint32_t *v4;\n int v5;\n if (a2 <= 0) {\n v5 = 1;\n } else {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 1;\n do\n v5 = v5 * (*v3++ % a3) % a3;\n while (v3 != v4);\n }\n return (unsigned int)(v5 % a3);\n}" + }, + { + "index": 472, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int *l, int size) {\n int *sorted = malloc(size * sizeof(int));\n for (int i = 0; i < size; i++) {\n sorted[i] = l[i];\n }\n for (int i = 0; i < size; i++) {\n for (int j = i + 1; j < size; j++) {\n if (sorted[i] > sorted[j]) {\n int temp = sorted[i];\n sorted[i] = sorted[j];\n sorted[j] = temp;\n }\n }\n }\n bool result = true;\n for (int i = 1; i < size; i++) {\n if (sorted[i] != sorted[i - 1] + 1) {\n result = false;\n break;\n }\n }\n free(sorted);\n return result;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4, 5};\n\n int arr2[] = {1, 2, 3, 5, 6};\n\n int arr3[] = {1, 2, 1};\n\n\n\n assert(func0(arr1, sizeof(arr1) / sizeof(arr1[0])) == true);\n\n assert(func0(arr2, sizeof(arr2) / sizeof(arr2[0])) == false);\n\n assert(func0(arr3, sizeof(arr3) / sizeof(arr3[0])) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmov -0x2c(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0x1c(%rbp)\njmp 120b \nmov -0x1c(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov -0x1c(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x1c(%rbp)\nmov -0x1c(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 11da \nmovl $0x0,-0x18(%rbp)\njmpq 12d0 \nmov -0x18(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x14(%rbp)\njmpq 12c0 \nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x8(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njle 12bc \nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0xc(%rbp)\nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov -0x18(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov -0xc(%rbp),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 122d \naddl $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 121f \nmovb $0x1,-0x1d(%rbp)\nmovl $0x1,-0x10(%rbp)\njmp 1327 \nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov -0x10(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x2,%rdx\nlea -0x4(%rdx),%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rdx),%edx\nadd $0x1,%edx\ncmp %edx,%eax\nje 1323 \nmovb $0x0,-0x1d(%rbp)\njmp 132f \naddl $0x1,-0x10(%rbp)\nmov -0x10(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 12e9 \nmov -0x8(%rbp),%rax\nmov %rax,%rdi\ncallq 1080 \nmovzbl -0x1d(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov [rbp+var_1C], 0\njmp short loc_120B\nloc_11DA:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+ptr]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_1C], 1\nloc_120B:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_2C]\njl short loc_11DA\nmov [rbp+var_18], 0\njmp loc_12D0\nloc_121F:\nmov eax, [rbp+var_18]\nadd eax, 1\nmov [rbp+var_14], eax\njmp loc_12C0\nloc_122D:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_14]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_12BC\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rbp+var_18]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+ptr]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov eax, [rbp+var_C]\nmov [rdx], eax\nloc_12BC:\nadd [rbp+var_14], 1\nloc_12C0:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl loc_122D\nadd [rbp+var_18], 1\nloc_12D0:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_2C]\njl loc_121F\nmov [rbp+var_1D], 1\nmov [rbp+var_10], 1\njmp short loc_1326\nloc_12E9:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nshl rax, 2\nlea rcx, [rax-4]\nmov rax, [rbp+ptr]\nadd rax, rcx\nmov eax, [rax]\nadd eax, 1\ncmp edx, eax\njz short loc_1322\nmov [rbp+var_1D], 0\njmp short loc_132E\nloc_1322:\nadd [rbp+var_10], 1\nloc_1326:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_2C]\njl short loc_12E9\nloc_132E:\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmovzx eax, [rbp+var_1D]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned __int8 v3; // [rsp+13h] [rbp-1Dh]\n int i; // [rsp+14h] [rbp-1Ch]\n int j; // [rsp+18h] [rbp-18h]\n int k; // [rsp+1Ch] [rbp-14h]\n int m; // [rsp+20h] [rbp-10h]\n int v8; // [rsp+24h] [rbp-Ch]\n _DWORD *ptr; // [rsp+28h] [rbp-8h]\n\n ptr = malloc(4LL * a2);\n for ( i = 0; i < a2; ++i )\n ptr[i] = *(_DWORD *)(4LL * i + a1);\n for ( j = 0; j < a2; ++j )\n {\n for ( k = j + 1; k < a2; ++k )\n {\n if ( ptr[j] > ptr[k] )\n {\n v8 = ptr[j];\n ptr[j] = ptr[k];\n ptr[k] = v8;\n }\n }\n }\n v3 = 1;\n for ( m = 1; m < a2; ++m )\n {\n if ( ptr[m] != ptr[m - 1] + 1 )\n {\n v3 = 0;\n break;\n }\n }\n free(ptr);\n return v3;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov [rbp+var_1C], 0\njmp short loc_120B\nloc_11DA:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+ptr]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_1C], 1\nloc_120B:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_2C]\njl short loc_11DA\nmov [rbp+var_18], 0\njmp loc_12D0\nloc_121F:\nmov eax, [rbp+var_18]\nadd eax, 1\nmov [rbp+var_14], eax\njmp loc_12C0\nloc_122D:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_14]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_12BC\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rbp+var_18]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+ptr]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov eax, [rbp+var_C]\nmov [rdx], eax\nloc_12BC:\nadd [rbp+var_14], 1\nloc_12C0:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl loc_122D\nadd [rbp+var_18], 1\nloc_12D0:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_2C]\njl loc_121F\nmov [rbp+var_1D], 1\nmov [rbp+var_10], 1\njmp short loc_1326\nloc_12E9:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nshl rax, 2\nlea rcx, [rax-4]\nmov rax, [rbp+ptr]\nadd rax, rcx\nmov eax, [rax]\nadd eax, 1\ncmp edx, eax\njz short loc_1322\nmov [rbp+var_1D], 0\njmp short loc_132E\nloc_1322:\nadd [rbp+var_10], 1\nloc_1326:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_2C]\njl short loc_12E9\nloc_132E:\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmovzx eax, [rbp+var_1D]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(__int64 a1, int a2)\n{\n unsigned __int8 v3; // [rsp+13h] [rbp-1Dh]\n int i; // [rsp+14h] [rbp-1Ch]\n int j; // [rsp+18h] [rbp-18h]\n int k; // [rsp+1Ch] [rbp-14h]\n int m; // [rsp+20h] [rbp-10h]\n int v8; // [rsp+24h] [rbp-Ch]\n _DWORD *ptr; // [rsp+28h] [rbp-8h]\n\n ptr = malloc(4LL * a2);\n for ( i = 0; i < a2; ++i )\n ptr[i] = *(_DWORD *)(4LL * i + a1);\n for ( j = 0; j < a2; ++j )\n {\n for ( k = j + 1; k < a2; ++k )\n {\n if ( ptr[j] > ptr[k] )\n {\n v8 = ptr[j];\n ptr[j] = ptr[k];\n ptr[k] = v8;\n }\n }\n }\n v3 = 1;\n for ( m = 1; m < a2; ++m )\n {\n if ( ptr[m] != ptr[m - 1] + 1 )\n {\n v3 = 0;\n break;\n }\n }\n free(ptr);\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(long long a1, int a2) {\n unsigned char v3;\n int i;\n int j;\n int k;\n int m;\n int v8;\n uint32_t *ptr;\n ptr = malloc(4LL * a2);\n for (i = 0; i < a2; ++i) ptr[i] = *(uint32_t *)(4LL * i + a1);\n for (j = 0; j < a2; ++j) {\n for (k = j + 1; k < a2; ++k) {\n if (ptr[j] > ptr[k]) {\n v8 = ptr[j];\n ptr[j] = ptr[k];\n ptr[k] = v8;\n }\n }\n }\n v3 = 1;\n for (m = 1; m < a2; ++m) {\n if (ptr[m] != ptr[m - 1] + 1) {\n v3 = 0;\n break;\n }\n }\n free(ptr);\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned char v3;\n int i;\n int j;\n int k;\n int m;\n int v8;\n uint32_t *ptr;\n ptr = malloc(4LL * a2);\n for (i = 0; i < a2; ++i) ptr[i] = *(uint32_t *)(4LL * i + a1);\n for (j = 0; j < a2; ++j) {\n for (k = j + 1; k < a2; ++k) {\n if (ptr[j] > ptr[k]) {\n v8 = ptr[j];\n ptr[j] = ptr[k];\n ptr[k] = v8;\n }\n }\n }\n v3 = 1;\n for (m = 1; m < a2; ++m) {\n if (ptr[m] != ptr[m - 1] + 1) {\n v3 = 0;\n break;\n }\n }\n free(ptr);\n return v3;\n}" + }, + { + "index": 472, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int *l, int size) {\n int *sorted = malloc(size * sizeof(int));\n for (int i = 0; i < size; i++) {\n sorted[i] = l[i];\n }\n for (int i = 0; i < size; i++) {\n for (int j = i + 1; j < size; j++) {\n if (sorted[i] > sorted[j]) {\n int temp = sorted[i];\n sorted[i] = sorted[j];\n sorted[j] = temp;\n }\n }\n }\n bool result = true;\n for (int i = 1; i < size; i++) {\n if (sorted[i] != sorted[i - 1] + 1) {\n result = false;\n break;\n }\n }\n free(sorted);\n return result;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4, 5};\n\n int arr2[] = {1, 2, 3, 5, 6};\n\n int arr3[] = {1, 2, 1};\n\n\n\n assert(func0(arr1, sizeof(arr1) / sizeof(arr1[0])) == true);\n\n assert(func0(arr2, sizeof(arr2) / sizeof(arr2[0])) == false);\n\n assert(func0(arr3, sizeof(arr3) / sizeof(arr3[0])) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbp\nmov %esi,%ebx\nmovslq %esi,%rdi\nshl $0x2,%rdi\ncallq 10b0 \ntest %ebx,%ebx\njle 121c \nlea -0x1(%rbx),%esi\nlea 0x1(%rsi),%r9\nmov $0x0,%edx\nmov 0x0(%rbp,%rdx,4),%ecx\nmov %ecx,(%rax,%rdx,4)\nmov %rdx,%rcx\nadd $0x1,%rdx\ncmp %rsi,%rcx\njne 11d4 \nmov %rax,%rdi\nmov $0x1,%r8d\njmp 1212 \nadd $0x1,%rdx\ncmp %edx,%ebx\njle 120a \nmov (%rdi),%ecx\nmov (%rax,%rdx,4),%esi\ncmp %esi,%ecx\njle 11f2 \nmov %esi,(%rdi)\nmov %ecx,(%rax,%rdx,4)\njmp 11f2 \nadd $0x1,%r8\nadd $0x4,%rdi\ncmp %r9,%r8\nje 121c \nmov %r8,%rdx\njmp 11fa \ncmp $0x1,%ebx\njle 1246 \nmov %rax,%rdx\nlea -0x2(%rbx),%ecx\nlea 0x4(%rax,%rcx,4),%rsi\nmov (%rdx),%ebx\nlea 0x1(%rbx),%ecx\ncmp %ecx,0x4(%rdx)\njne 124d \nadd $0x4,%rdx\ncmp %rsi,%rdx\njne 122c \nmov $0x1,%ebx\njmp 1252 \nmov $0x1,%ebx\njmp 1252 \nmov $0x0,%ebx\nmov %rax,%rdi\ncallq 1080 \nmov %ebx,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12, rdi\nmov ebp, esi\nmovsxd rbx, esi\nlea r13, ds:0[rbx*4]\nmov rdi, r13; size\ncall _malloc\nmov r9, rax\ntest ebp, ebp\njle loc_1272\nmov eax, 0\nloc_11DF:\nmov edx, [r12+rax]\nmov [r9+rax], edx\nadd rax, 4\ncmp r13, rax\njnz short loc_11DF\nlea rsi, [r9+4]\nlea r12d, [rbp-1]\nmov r10d, ebp\nmov r8d, 1\nlea r11, [r9+8]\njmp short loc_1230\nloc_1207:\nadd rax, 4\ncmp rax, rdi\njz short loc_1220\nloc_1210:\nmov edx, [rsi-4]\nmov ecx, [rax]\ncmp edx, ecx\njle short loc_1207\nmov [rsi-4], ecx\nmov [rax], edx\njmp short loc_1207\nloc_1220:\nlea rax, [r8+1]\nadd rsi, 4\ncmp rbx, r8\njz short loc_1249\nmov r8, rax\nloc_1230:\ncmp r8, r10\njz short loc_1249\nmov eax, r12d\nsub eax, r8d\nlea rax, [r8+rax-1]\nlea rdi, [r11+rax*4]\nmov rax, rsi\njmp short loc_1210\nloc_1249:\ncmp ebp, 1\njle short loc_1279\nmov rax, r9\nlea edx, [rbp-1]\nlea rcx, [r9+rdx*4]\nloc_1258:\nmov ebx, [rax]\nlea edx, [rbx+1]\ncmp [rax+4], edx\njnz short loc_1280\nadd rax, 4\ncmp rax, rcx\njnz short loc_1258\nmov ebx, 1\njmp short loc_1285\nloc_1272:\nmov ebx, 1\njmp short loc_1285\nloc_1279:\nmov ebx, 1\njmp short loc_1285\nloc_1280:\nmov ebx, 0\nloc_1285:\nmov rdi, r9; ptr\ncall _free\nmov eax, ebx\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v3; // rbx\n _DWORD *v4; // r9\n __int64 i; // rax\n _DWORD *v6; // rsi\n __int64 j; // r8\n _DWORD *v8; // rax\n int v9; // edx\n _DWORD *v10; // rax\n unsigned int v11; // ebx\n\n v3 = a2;\n v4 = malloc(4LL * a2);\n if ( a2 <= 0 )\n {\n v11 = 1;\n }\n else\n {\n for ( i = 0LL; i != a2; ++i )\n v4[i] = *(_DWORD *)(a1 + i * 4);\n v6 = v4 + 1;\n for ( j = 1LL; j != a2; ++j )\n {\n v8 = v6;\n do\n {\n v9 = *(v6 - 1);\n if ( v9 > *v8 )\n {\n *(v6 - 1) = *v8;\n *v8 = v9;\n }\n ++v8;\n }\n while ( v8 != &v4[j + 1 + (unsigned int)(a2 - 1 - j)] );\n ++v6;\n if ( v3 == j )\n break;\n }\n if ( a2 <= 1 )\n {\n v11 = 1;\n }\n else\n {\n v10 = v4;\n while ( v10[1] == *v10 + 1 )\n {\n if ( ++v10 == &v4[a2 - 1] )\n {\n v11 = 1;\n goto LABEL_20;\n }\n }\n v11 = 0;\n }\n }\nLABEL_20:\n free(v4);\n return v11;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12, rdi\nmov ebp, esi\nmovsxd rbx, esi\nlea r13, ds:0[rbx*4]\nmov rdi, r13; size\ncall _malloc\nmov r9, rax\ntest ebp, ebp\njle loc_1272\nmov eax, 0\nloc_11DF:\nmov edx, [r12+rax]\nmov [r9+rax], edx\nadd rax, 4\ncmp r13, rax\njnz short loc_11DF\nlea rsi, [r9+4]\nlea r12d, [rbp-1]\nmov r10d, ebp\nmov r8d, 1\nlea r11, [r9+8]\njmp short loc_1230\nloc_1207:\nadd rax, 4\ncmp rax, rdi\njz short loc_1220\nloc_1210:\nmov edx, [rsi-4]\nmov ecx, [rax]\ncmp edx, ecx\njle short loc_1207\nmov [rsi-4], ecx\nmov [rax], edx\njmp short loc_1207\nloc_1220:\nlea rax, [r8+1]\nadd rsi, 4\ncmp rbx, r8\njz short loc_1249\nmov r8, rax\nloc_1230:\ncmp r8, r10\njz short loc_1249\nmov eax, r12d\nsub eax, r8d\nlea rax, [r8+rax-1]\nlea rdi, [r11+rax*4]\nmov rax, rsi\njmp short loc_1210\nloc_1249:\ncmp ebp, 1\njle short loc_1279\nmov rax, r9\nlea edx, [rbp-1]\nlea rcx, [r9+rdx*4]\nloc_1258:\nmov ebx, [rax]\nlea edx, [rbx+1]\ncmp [rax+4], edx\njnz short loc_1280\nadd rax, 4\ncmp rax, rcx\njnz short loc_1258\nmov ebx, 1\njmp short loc_1285\nloc_1272:\nmov ebx, 1\njmp short loc_1285\nloc_1279:\nmov ebx, 1\njmp short loc_1285\nloc_1280:\nmov ebx, 0\nloc_1285:\nmov rdi, r9; ptr\ncall _free\nmov eax, ebx\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(__int64 a1, int a2)\n{\n __int64 v3; // rbx\n _DWORD *v4; // r9\n __int64 i; // rax\n _DWORD *v6; // rsi\n __int64 j; // r8\n _DWORD *v8; // rax\n int v9; // edx\n _DWORD *v10; // rax\n unsigned int v11; // ebx\n\n v3 = a2;\n v4 = malloc(4LL * a2);\n if ( a2 <= 0 )\n {\n v11 = 1;\n }\n else\n {\n for ( i = 0LL; i != a2; ++i )\n v4[i] = *(_DWORD *)(a1 + i * 4);\n v6 = v4 + 1;\n for ( j = 1LL; j != a2; ++j )\n {\n v8 = v6;\n do\n {\n v9 = *(v6 - 1);\n if ( v9 > *v8 )\n {\n *(v6 - 1) = *v8;\n *v8 = v9;\n }\n ++v8;\n }\n while ( v8 != &v4[j + 1 + (unsigned int)(a2 - 1 - j)] );\n ++v6;\n if ( v3 == j )\n break;\n }\n if ( a2 <= 1 )\n {\n v11 = 1;\n }\n else\n {\n v10 = v4;\n while ( v10[1] == *v10 + 1 )\n {\n if ( ++v10 == &v4[a2 - 1] )\n {\n v11 = 1;\n goto LABEL_20;\n }\n }\n v11 = 0;\n }\n }\nLABEL_20:\n free(v4);\n return v11;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(long long a1, int a2) {\n long long v3;\n uint32_t *v4;\n long long i;\n uint32_t *v6;\n long long j;\n uint32_t *v8;\n int v9;\n uint32_t *v10;\n unsigned int v11;\n v3 = a2;\n v4 = malloc(4LL * a2);\n if (a2 <= 0) {\n v11 = 1;\n } else {\n for (i = 0LL; i != a2; ++i) v4[i] = *(uint32_t *)(a1 + i * 4);\n v6 = v4 + 1;\n for (j = 1LL; j != a2; ++j) {\n v8 = v6;\n do {\n v9 = *(v6 - 1);\n if (v9 > *v8) {\n *(v6 - 1) = *v8;\n *v8 = v9;\n }\n ++v8;\n } while (v8 != &v4[j + 1 + (unsigned int)(a2 - 1 - j)]);\n ++v6;\n if (v3 == j) break;\n }\n if (a2 <= 1) {\n v11 = 1;\n } else {\n v10 = v4;\n while (v10[1] == *v10 + 1) {\n if (++v10 == &v4[a2 - 1]) {\n v11 = 1;\n goto LABEL_20;\n }\n }\n v11 = 0;\n }\n }\nLABEL_20:\n free(v4);\n return v11;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v3;\n uint32_t *v4;\n long long i;\n uint32_t *v6;\n long long j;\n uint32_t *v8;\n int v9;\n uint32_t *v10;\n unsigned int v11;\n v3 = a2;\n v4 = malloc(4LL * a2);\n if (a2 <= 0) {\n v11 = 1;\n } else {\n for (i = 0LL; i != a2; ++i) v4[i] = *(uint32_t *)(a1 + i * 4);\n v6 = v4 + 1;\n for (j = 1LL; j != a2; ++j) {\n v8 = v6;\n do {\n v9 = *(v6 - 1);\n if (v9 > *v8) {\n *(v6 - 1) = *v8;\n *v8 = v9;\n }\n ++v8;\n } while (v8 != &v4[j + 1 + (unsigned int)(a2 - 1 - j)]);\n ++v6;\n if (v3 == j) break;\n }\n if (a2 <= 1) {\n v11 = 1;\n } else {\n v10 = v4;\n while (v10[1] == *v10 + 1) {\n if (++v10 == &v4[a2 - 1]) {\n v11 = 1;\n goto LABEL_20;\n }\n }\n v11 = 0;\n }\n }\nLABEL_20:\n free(v4);\n return v11;\n}" + }, + { + "index": 472, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int *l, int size) {\n int *sorted = malloc(size * sizeof(int));\n for (int i = 0; i < size; i++) {\n sorted[i] = l[i];\n }\n for (int i = 0; i < size; i++) {\n for (int j = i + 1; j < size; j++) {\n if (sorted[i] > sorted[j]) {\n int temp = sorted[i];\n sorted[i] = sorted[j];\n sorted[j] = temp;\n }\n }\n }\n bool result = true;\n for (int i = 1; i < size; i++) {\n if (sorted[i] != sorted[i - 1] + 1) {\n result = false;\n break;\n }\n }\n free(sorted);\n return result;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4, 5};\n\n int arr2[] = {1, 2, 3, 5, 6};\n\n int arr3[] = {1, 2, 1};\n\n\n\n assert(func0(arr1, sizeof(arr1) / sizeof(arr1[0])) == true);\n\n assert(func0(arr2, sizeof(arr2) / sizeof(arr2[0])) == false);\n\n assert(func0(arr3, sizeof(arr3) / sizeof(arr3[0])) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\nmov %rdi,%rbp\nmovslq %esi,%rdi\npush %rbx\nmov %rdi,%rbx\nshl $0x2,%rdi\ncallq 10b0 \nmov %rax,%r9\ntest %ebx,%ebx\njle 1396 \nlea -0x1(%rbx),%ecx\nxor %eax,%eax\nlea 0x1(%rcx),%rsi\nxchg %ax,%ax\nmov 0x0(%rbp,%rax,4),%edx\nmov %edx,(%r9,%rax,4)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rcx,%rdx\njne 1300 \nmov $0x1,%eax\nmov %r9,%r8\ncmp %rsi,%rax\nje 1357 \nnopl 0x0(%rax)\nmov %rax,%rdx\nnopl 0x0(%rax,%rax,1)\nmov (%r8),%ecx\nmov (%r9,%rdx,4),%edi\ncmp %edi,%ecx\njle 1342 \nmov %edi,(%r8)\nmov %ecx,(%r9,%rdx,4)\nadd $0x1,%rdx\ncmp %edx,%ebx\njg 1330 \nadd $0x1,%rax\nadd $0x4,%r8\ncmp %rsi,%rax\njne 1328 \ncmp $0x1,%ebx\njle 1396 \nlea -0x2(%rbx),%edx\nmov %r9,%rax\nlea 0x4(%r9,%rdx,4),%rcx\njmp 1379 \nnopl 0x0(%rax)\nadd $0x4,%rax\ncmp %rax,%rcx\nje 1396 \nmov (%rax),%esi\nlea 0x1(%rsi),%edx\ncmp %edx,0x4(%rax)\nje 1370 \nxor %r12d,%r12d\nmov %r9,%rdi\ncallq 1080 \nmov %r12d,%eax\npop %rbx\npop %rbp\npop %r12\nretq\nmov $0x1,%r12d\nmov %r9,%rdi\ncallq 1080 \nmov %r12d,%eax\npop %rbx\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r12\nmov r12, rdi\nmovsxd rdi, esi\npush rbp\npush rbx\nmov rbx, rdi\nshl rdi, 2; size\ncall _malloc\nmov rdi, rax; ptr\ntest ebx, ebx\njle loc_1392\nmov ebp, ebx\nmov rsi, r12; src\nlea rdx, ds:0[rbp*4]; n\ncall _memcpy\nmov rdi, rax; ptr\ncmp ebx, 1\njz short loc_1392\nlea r9d, [rbx-2]\nmov rsi, rax\nmov r8d, 1\nnop dword ptr [rax+00h]\nloc_1330:\nmov rax, r8\nnop dword ptr [rax+rax+00h]\nloc_1338:\nmov edx, [rsi]\nmov ecx, [rdi+rax*4]\ncmp edx, ecx\njle short loc_1346\nmov [rsi], ecx\nmov [rdi+rax*4], edx\nloc_1346:\nadd rax, 1\ncmp ebx, eax\njg short loc_1338\nadd r8, 1\nadd rsi, 4\ncmp r8, rbp\njnz short loc_1330\nmov ecx, [rdi]\nlea rdx, [rdi+4]\nlea rsi, [rdi+r9*4+8]\njmp short loc_1379\nloc_1370:\nadd rdx, 4\ncmp rsi, rdx\njz short loc_1392\nloc_1379:\nmov eax, ecx\nmov ecx, [rdx]\nadd eax, 1\ncmp ecx, eax\njz short loc_1370\ncall _free\nxor ebx, ebx\nmov eax, ebx\npop rbx\npop rbp\npop r12\nretn\nloc_1392:\ncall _free\nmov ebx, 1\nmov eax, ebx\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "__int64 __fastcall func0(void *src, int a2)\n{\n int *v4; // rdi\n int *v5; // rax\n int *v6; // rsi\n __int64 v7; // r8\n __int64 v8; // rax\n int v9; // edx\n int v10; // ecx\n int v11; // ecx\n int *v12; // rdx\n int v13; // eax\n\n v4 = (int *)malloc(4LL * a2);\n if ( a2 <= 0 || (v5 = (int *)memcpy(v4, src, 4LL * (unsigned int)a2), v4 = v5, a2 == 1) )\n {\nLABEL_13:\n free(v4);\n return 1LL;\n }\n else\n {\n v6 = v5;\n v7 = 1LL;\n do\n {\n v8 = v7;\n do\n {\n v9 = *v6;\n v10 = v4[v8];\n if ( *v6 > v10 )\n {\n *v6 = v10;\n v4[v8] = v9;\n }\n ++v8;\n }\n while ( a2 > (int)v8 );\n ++v7;\n ++v6;\n }\n while ( v7 != a2 );\n v11 = *v4;\n v12 = v4 + 1;\n while ( 1 )\n {\n v13 = v11;\n v11 = *v12;\n if ( *v12 != v13 + 1 )\n break;\n if ( &v4[a2 - 2 + 2] == ++v12 )\n goto LABEL_13;\n }\n free(v4);\n return 0LL;\n }\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\npush r12\nmov r12, rdi\nmovsxd rdi, esi\npush rbp\npush rbx\nmov rbx, rdi\nshl rdi, 2; size\ncall _malloc\nmov rdi, rax; ptr\ntest ebx, ebx\njle loc_1392\nmov ebp, ebx\nmov rsi, r12; src\nlea rdx, ds:0[rbp*4]; n\ncall _memcpy\nmov rdi, rax; ptr\ncmp ebx, 1\njz short loc_1392\nlea r9d, [rbx-2]\nmov rsi, rax\nmov r8d, 1\nnop dword ptr [rax+00h]\nloc_1330:\nmov rax, r8\nnop dword ptr [rax+rax+00h]\nloc_1338:\nmov edx, [rsi]\nmov ecx, [rdi+rax*4]\ncmp edx, ecx\njle short loc_1346\nmov [rsi], ecx\nmov [rdi+rax*4], edx\nloc_1346:\nadd rax, 1\ncmp ebx, eax\njg short loc_1338\nadd r8, 1\nadd rsi, 4\ncmp r8, rbp\njnz short loc_1330\nmov ecx, [rdi]\nlea rdx, [rdi+4]\nlea rsi, [rdi+r9*4+8]\njmp short loc_1379\nloc_1370:\nadd rdx, 4\ncmp rsi, rdx\njz short loc_1392\nloc_1379:\nmov eax, ecx\nmov ecx, [rdx]\nadd eax, 1\ncmp ecx, eax\njz short loc_1370\ncall _free\nxor ebx, ebx\nmov eax, ebx\npop rbx\npop rbp\npop r12\nretn\nloc_1392:\ncall _free\nmov ebx, 1\nmov eax, ebx\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12E0(void *src, int a2)\n{\n int *v4; // rdi\n int *v5; // rax\n int *v6; // rsi\n __int64 v7; // r8\n __int64 v8; // rax\n int v9; // edx\n int v10; // ecx\n int v11; // ecx\n int *v12; // rdx\n int v13; // eax\n\n v4 = (int *)malloc(4LL * a2);\n if ( a2 <= 0 || (v5 = (int *)memcpy(v4, src, 4LL * (unsigned int)a2), v4 = v5, a2 == 1) )\n {\nLABEL_13:\n free(v4);\n return 1LL;\n }\n else\n {\n v6 = v5;\n v7 = 1LL;\n do\n {\n v8 = v7;\n do\n {\n v9 = *v6;\n v10 = v4[v8];\n if ( *v6 > v10 )\n {\n *v6 = v10;\n v4[v8] = v9;\n }\n ++v8;\n }\n while ( a2 > (int)v8 );\n ++v7;\n ++v6;\n }\n while ( v7 != a2 );\n v11 = *v4;\n v12 = v4 + 1;\n while ( 1 )\n {\n v13 = v11;\n v11 = *v12;\n if ( *v12 != v13 + 1 )\n break;\n if ( &v4[a2 - 2 + 2] == ++v12 )\n goto LABEL_13;\n }\n free(v4);\n return 0LL;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12E0(void *src, int a2) {\n int *v4;\n int *v5;\n int *v6;\n long long v7;\n long long v8;\n int v9;\n int v10;\n int v11;\n int *v12;\n int v13;\n v4 = (int *)malloc(4LL * a2);\n if (a2 <= 0 ||\n (v5 = (int *)memcpy(v4, src, 4LL * (unsigned int)a2), v4 = v5, a2 == 1)) {\n LABEL_13:\n free(v4);\n return 1LL;\n } else {\n v6 = v5;\n v7 = 1LL;\n do {\n v8 = v7;\n do {\n v9 = *v6;\n v10 = v4[v8];\n if (*v6 > v10) {\n *v6 = v10;\n v4[v8] = v9;\n }\n ++v8;\n } while (a2 > (int)v8);\n ++v7;\n ++v6;\n } while (v7 != a2);\n v11 = *v4;\n v12 = v4 + 1;\n while (1) {\n v13 = v11;\n v11 = *v12;\n if (*v12 != v13 + 1) break;\n if (&v4[a2 - 2 + 2] == ++v12) goto LABEL_13;\n }\n free(v4);\n return 0LL;\n }\n}", + "ida_pseudo_norm": "long long func0(void *src, int a2) {\n int *v4;\n int *v5;\n int *v6;\n long long v7;\n long long v8;\n int v9;\n int v10;\n int v11;\n int *v12;\n int v13;\n v4 = (int *)malloc(4LL * a2);\n if (a2 <= 0 ||\n (v5 = (int *)memcpy(v4, src, 4LL * (unsigned int)a2), v4 = v5, a2 == 1)) {\n LABEL_13:\n free(v4);\n return 1LL;\n } else {\n v6 = v5;\n v7 = 1LL;\n do {\n v8 = v7;\n do {\n v9 = *v6;\n v10 = v4[v8];\n if (*v6 > v10) {\n *v6 = v10;\n v4[v8] = v9;\n }\n ++v8;\n } while (a2 > (int)v8);\n ++v7;\n ++v6;\n } while (v7 != a2);\n v11 = *v4;\n v12 = v4 + 1;\n while (1) {\n v13 = v11;\n v11 = *v12;\n if (*v12 != v13 + 1) break;\n if (&v4[a2 - 2 + 2] == ++v12) goto LABEL_13;\n }\n free(v4);\n return 0LL;\n }\n}" + }, + { + "index": 472, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int *l, int size) {\n int *sorted = malloc(size * sizeof(int));\n for (int i = 0; i < size; i++) {\n sorted[i] = l[i];\n }\n for (int i = 0; i < size; i++) {\n for (int j = i + 1; j < size; j++) {\n if (sorted[i] > sorted[j]) {\n int temp = sorted[i];\n sorted[i] = sorted[j];\n sorted[j] = temp;\n }\n }\n }\n bool result = true;\n for (int i = 1; i < size; i++) {\n if (sorted[i] != sorted[i - 1] + 1) {\n result = false;\n break;\n }\n }\n free(sorted);\n return result;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4, 5};\n\n int arr2[] = {1, 2, 3, 5, 6};\n\n int arr3[] = {1, 2, 1};\n\n\n\n assert(func0(arr1, sizeof(arr1) / sizeof(arr1[0])) == true);\n\n assert(func0(arr2, sizeof(arr2) / sizeof(arr2[0])) == false);\n\n assert(func0(arr3, sizeof(arr3) / sizeof(arr3[0])) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\nmov %rdi,%rbp\nmovslq %esi,%rdi\npush %rbx\nmov %rdi,%rbx\nshl $0x2,%rdi\ncallq 10d0 \nmov %rax,%rdi\ntest %ebx,%ebx\njle 1394 \nlea -0x1(%rbx),%eax\nmov %rbp,%rsi\nlea 0x4(,%rax,4),%rdx\ncallq 10c0 \nmov %rax,%rdi\ncmp $0x1,%ebx\nje 1394 \nlea -0x2(%rbx),%r9d\nmov %rax,%rsi\nmov $0x1,%r8d\nmov %r9,%r10\nadd $0x2,%r9\nnopl 0x0(%rax)\nmov %r8,%rax\nnopl 0x0(%rax,%rax,1)\nmov (%rsi),%edx\nmov (%rdi,%rax,4),%ecx\ncmp %ecx,%edx\njle 134e \nmov %ecx,(%rsi)\nmov %edx,(%rdi,%rax,4)\nadd $0x1,%rax\ncmp %eax,%ebx\njg 1340 \nadd $0x1,%r8\nadd $0x4,%rsi\ncmp %r9,%r8\njne 1338 \nmov (%rdi),%ecx\nlea 0x4(%rdi),%rdx\nlea 0x8(%rdi,%r10,4),%rsi\njmp 1379 \nadd $0x4,%rdx\ncmp %rsi,%rdx\nje 1394 \nmov %ecx,%eax\nmov (%rdx),%ecx\nadd $0x1,%eax\ncmp %eax,%ecx\nje 1370 \ncallq 1090 \nxor %r12d,%r12d\npop %rbx\npop %rbp\nmov %r12d,%eax\npop %r12\nretq\ncallq 1090 \nmov $0x1,%r12d\npop %rbx\npop %rbp\nmov %r12d,%eax\npop %r12\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r12\nmov r12, rdi\nmovsxd rdi, esi\npush rbp\npush rbx\nmov rbx, rdi\nshl rdi, 2; size\ncall _malloc\nmov rdi, rax; ptr\ntest ebx, ebx\njle loc_1392\nmov ebp, ebx\nmov rsi, r12; src\nlea rdx, ds:0[rbp*4]; n\ncall _memcpy\nmov rdi, rax; ptr\ncmp ebx, 1\njz short loc_1392\nlea r9d, [rbx-2]\nmov rsi, rax\nmov r8d, 1\nnop dword ptr [rax+00h]\nloc_1330:\nmov rax, r8\nnop dword ptr [rax+rax+00h]\nloc_1338:\nmov edx, [rsi]\nmov ecx, [rdi+rax*4]\ncmp edx, ecx\njle short loc_1346\nmov [rsi], ecx\nmov [rdi+rax*4], edx\nloc_1346:\nadd rax, 1\ncmp ebx, eax\njg short loc_1338\nadd r8, 1\nadd rsi, 4\ncmp r8, rbp\njnz short loc_1330\nmov ecx, [rdi]\nlea rdx, [rdi+4]\nlea rsi, [rdi+r9*4+8]\njmp short loc_1379\nloc_1370:\nadd rdx, 4\ncmp rsi, rdx\njz short loc_1392\nloc_1379:\nmov eax, ecx\nmov ecx, [rdx]\nadd eax, 1\ncmp ecx, eax\njz short loc_1370\ncall _free\nxor ebx, ebx\nmov eax, ebx\npop rbx\npop rbp\npop r12\nretn\nloc_1392:\ncall _free\nmov ebx, 1\nmov eax, ebx\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "__int64 __fastcall func0(void *src, int a2)\n{\n int *v4; // rdi\n int *v5; // rax\n int *v6; // rsi\n __int64 v7; // r8\n __int64 v8; // rax\n int v9; // edx\n int v10; // ecx\n int v11; // ecx\n int *v12; // rdx\n int v13; // eax\n\n v4 = (int *)malloc(4LL * a2);\n if ( a2 <= 0 || (v5 = (int *)memcpy(v4, src, 4LL * (unsigned int)a2), v4 = v5, a2 == 1) )\n {\nLABEL_13:\n free(v4);\n return 1LL;\n }\n else\n {\n v6 = v5;\n v7 = 1LL;\n do\n {\n v8 = v7;\n do\n {\n v9 = *v6;\n v10 = v4[v8];\n if ( *v6 > v10 )\n {\n *v6 = v10;\n v4[v8] = v9;\n }\n ++v8;\n }\n while ( a2 > (int)v8 );\n ++v7;\n ++v6;\n }\n while ( v7 != a2 );\n v11 = *v4;\n v12 = v4 + 1;\n while ( 1 )\n {\n v13 = v11;\n v11 = *v12;\n if ( *v12 != v13 + 1 )\n break;\n if ( &v4[a2 - 2 + 2] == ++v12 )\n goto LABEL_13;\n }\n free(v4);\n return 0LL;\n }\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\npush r12\nmov r12, rdi\nmovsxd rdi, esi\npush rbp\npush rbx\nmov rbx, rdi\nshl rdi, 2; size\ncall _malloc\nmov rdi, rax; ptr\ntest ebx, ebx\njle loc_1392\nmov ebp, ebx\nmov rsi, r12; src\nlea rdx, ds:0[rbp*4]; n\ncall _memcpy\nmov rdi, rax; ptr\ncmp ebx, 1\njz short loc_1392\nlea r9d, [rbx-2]\nmov rsi, rax\nmov r8d, 1\nnop dword ptr [rax+00h]\nloc_1330:\nmov rax, r8\nnop dword ptr [rax+rax+00h]\nloc_1338:\nmov edx, [rsi]\nmov ecx, [rdi+rax*4]\ncmp edx, ecx\njle short loc_1346\nmov [rsi], ecx\nmov [rdi+rax*4], edx\nloc_1346:\nadd rax, 1\ncmp ebx, eax\njg short loc_1338\nadd r8, 1\nadd rsi, 4\ncmp r8, rbp\njnz short loc_1330\nmov ecx, [rdi]\nlea rdx, [rdi+4]\nlea rsi, [rdi+r9*4+8]\njmp short loc_1379\nloc_1370:\nadd rdx, 4\ncmp rsi, rdx\njz short loc_1392\nloc_1379:\nmov eax, ecx\nmov ecx, [rdx]\nadd eax, 1\ncmp ecx, eax\njz short loc_1370\ncall _free\nxor ebx, ebx\nmov eax, ebx\npop rbx\npop rbp\npop r12\nretn\nloc_1392:\ncall _free\nmov ebx, 1\nmov eax, ebx\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12E0(void *src, int a2)\n{\n int *v4; // rdi\n int *v5; // rax\n int *v6; // rsi\n __int64 v7; // r8\n __int64 v8; // rax\n int v9; // edx\n int v10; // ecx\n int v11; // ecx\n int *v12; // rdx\n int v13; // eax\n\n v4 = (int *)malloc(4LL * a2);\n if ( a2 <= 0 || (v5 = (int *)memcpy(v4, src, 4LL * (unsigned int)a2), v4 = v5, a2 == 1) )\n {\nLABEL_13:\n free(v4);\n return 1LL;\n }\n else\n {\n v6 = v5;\n v7 = 1LL;\n do\n {\n v8 = v7;\n do\n {\n v9 = *v6;\n v10 = v4[v8];\n if ( *v6 > v10 )\n {\n *v6 = v10;\n v4[v8] = v9;\n }\n ++v8;\n }\n while ( a2 > (int)v8 );\n ++v7;\n ++v6;\n }\n while ( v7 != a2 );\n v11 = *v4;\n v12 = v4 + 1;\n while ( 1 )\n {\n v13 = v11;\n v11 = *v12;\n if ( *v12 != v13 + 1 )\n break;\n if ( &v4[a2 - 2 + 2] == ++v12 )\n goto LABEL_13;\n }\n free(v4);\n return 0LL;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12E0(void *src, int a2) {\n int *v4;\n int *v5;\n int *v6;\n long long v7;\n long long v8;\n int v9;\n int v10;\n int v11;\n int *v12;\n int v13;\n v4 = (int *)malloc(4LL * a2);\n if (a2 <= 0 ||\n (v5 = (int *)memcpy(v4, src, 4LL * (unsigned int)a2), v4 = v5, a2 == 1)) {\n LABEL_13:\n free(v4);\n return 1LL;\n } else {\n v6 = v5;\n v7 = 1LL;\n do {\n v8 = v7;\n do {\n v9 = *v6;\n v10 = v4[v8];\n if (*v6 > v10) {\n *v6 = v10;\n v4[v8] = v9;\n }\n ++v8;\n } while (a2 > (int)v8);\n ++v7;\n ++v6;\n } while (v7 != a2);\n v11 = *v4;\n v12 = v4 + 1;\n while (1) {\n v13 = v11;\n v11 = *v12;\n if (*v12 != v13 + 1) break;\n if (&v4[a2 - 2 + 2] == ++v12) goto LABEL_13;\n }\n free(v4);\n return 0LL;\n }\n}", + "ida_pseudo_norm": "long long func0(void *src, int a2) {\n int *v4;\n int *v5;\n int *v6;\n long long v7;\n long long v8;\n int v9;\n int v10;\n int v11;\n int *v12;\n int v13;\n v4 = (int *)malloc(4LL * a2);\n if (a2 <= 0 ||\n (v5 = (int *)memcpy(v4, src, 4LL * (unsigned int)a2), v4 = v5, a2 == 1)) {\n LABEL_13:\n free(v4);\n return 1LL;\n } else {\n v6 = v5;\n v7 = 1LL;\n do {\n v8 = v7;\n do {\n v9 = *v6;\n v10 = v4[v8];\n if (*v6 > v10) {\n *v6 = v10;\n v4[v8] = v9;\n }\n ++v8;\n } while (a2 > (int)v8);\n ++v7;\n ++v6;\n } while (v7 != a2);\n v11 = *v4;\n v12 = v4 + 1;\n while (1) {\n v13 = v11;\n v11 = *v12;\n if (*v12 != v13 + 1) break;\n if (&v4[a2 - 2 + 2] == ++v12) goto LABEL_13;\n }\n free(v4);\n return 0LL;\n }\n}" + }, + { + "index": 473, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n} tuple;\n\n\n\n// Compare two tuples for qsort and bsearch\n\nint tuple_compare(const void *a, const void *b) {\n\n tuple *t1 = (tuple *)a;\n\n tuple *t2 = (tuple *)b;\n\n if (t1->first != t2->first)\n\n return t1->first - t2->first;\n\n return t1->second - t2->second;\n\n}\n\n\n\n// Function to perform tuple intersection\n\n", + "func": "tuple *func0(tuple *list1, int size1, tuple *list2, int size2, int *res_size) {\n for (int i = 0; i < size1; i++) {\n if (list1[i].first > list1[i].second) {\n int temp = list1[i].first;\n list1[i].first = list1[i].second;\n list1[i].second = temp;\n }\n }\n for (int i = 0; i < size2; i++) {\n if (list2[i].first > list2[i].second) {\n int temp = list2[i].first;\n list2[i].first = list2[i].second;\n list2[i].second = temp;\n }\n }\n qsort(list1, size1, sizeof(tuple), tuple_compare);\n qsort(list2, size2, sizeof(tuple), tuple_compare);\n int unique1 = 0;\n for (int i = 0; i < size1; i++) {\n if (i == 0 || tuple_compare(&list1[i], &list1[i - 1]) != 0) {\n list1[unique1++] = list1[i];\n }\n }\n int unique2 = 0;\n for (int i = 0; i < size2; i++) {\n if (i == 0 || tuple_compare(&list2[i], &list2[i - 1]) != 0) {\n list2[unique2++] = list2[i];\n }\n }\n tuple *res = malloc(sizeof(tuple) * (unique1 < unique2 ? unique1 : unique2));\n int count = 0, i_idx = 0, j_idx = 0;\n while (i_idx < unique1 && j_idx < unique2) {\n int cmp = tuple_compare(&list1[i_idx], &list2[j_idx]);\n if (cmp == 0) {\n res[count++] = list1[i_idx];\n i_idx++;\n j_idx++;\n }\n else if (cmp < 0)\n i_idx++;\n else\n j_idx++;\n }\n *res_size = count;\n return res;\n}", + "test": "int main() {\n\n // First test\n\n tuple list1_1[] = { {3,4}, {5,6}, {9,10}, {4,5} };\n\n int size1_1 = 4;\n\n tuple list2_1[] = { {5,4}, {3,4}, {6,5}, {9,11} };\n\n int size2_1 = 4;\n\n int res_size_1;\n\n tuple *res1 = func0(list1_1, size1_1, list2_1, size2_1, &res_size_1);\n\n tuple expected1[] = { {3,4}, {4,5}, {5,6} };\n\n int expected_size1 = 3;\n\n assert(res_size_1 == expected_size1);\n\n for(int i=0;i\nmov -0x38(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x38(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x48(%rbp),%rax\nadd %rcx,%rax\nmov 0x4(%rax),%eax\ncmp %eax,%edx\njle 12db \nmov -0x38(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0xc(%rbp)\nmov -0x38(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov -0x38(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x48(%rbp),%rdx\nadd %rcx,%rdx\nmov 0x4(%rax),%eax\nmov %eax,(%rdx)\nmov -0x38(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x48(%rbp),%rax\nadd %rax,%rdx\nmov -0xc(%rbp),%eax\nmov %eax,0x4(%rdx)\naddl $0x1,-0x38(%rbp)\nmov -0x38(%rbp),%eax\ncmp -0x4c(%rbp),%eax\njl 1249 \nmovl $0x0,-0x34(%rbp)\njmpq 138d \nmov -0x34(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x58(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x34(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x58(%rbp),%rax\nadd %rcx,%rax\nmov 0x4(%rax),%eax\ncmp %eax,%edx\njle 1389 \nmov -0x34(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x58(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x10(%rbp)\nmov -0x34(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x58(%rbp),%rax\nadd %rdx,%rax\nmov -0x34(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x58(%rbp),%rdx\nadd %rcx,%rdx\nmov 0x4(%rax),%eax\nmov %eax,(%rdx)\nmov -0x34(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x58(%rbp),%rax\nadd %rax,%rdx\nmov -0x10(%rbp),%eax\nmov %eax,0x4(%rdx)\naddl $0x1,-0x34(%rbp)\nmov -0x34(%rbp),%eax\ncmp -0x50(%rbp),%eax\njl 12f7 \nmov -0x4c(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x48(%rbp),%rax\nlea -0x1e1(%rip),%rcx\nmov $0x8,%edx\nmov %rax,%rdi\ncallq 10a0 \nmov -0x50(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x58(%rbp),%rax\nlea -0x1ff(%rip),%rcx\nmov $0x8,%edx\nmov %rax,%rdi\ncallq 10a0 \nmovl $0x0,-0x30(%rbp)\nmovl $0x0,-0x2c(%rbp)\njmp 145b \ncmpl $0x0,-0x2c(%rbp)\nje 1422 \nmov -0x2c(%rbp),%eax\ncltq\nshl $0x3,%rax\nlea -0x8(%rax),%rdx\nmov -0x48(%rbp),%rax\nadd %rax,%rdx\nmov -0x2c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x48(%rbp),%rax\nadd %rcx,%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 11c9 \ntest %eax,%eax\nje 1457 \nmov -0x2c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x48(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x30(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x30(%rbp)\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x48(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%rax\nmov %rax,(%rdx)\naddl $0x1,-0x2c(%rbp)\nmov -0x2c(%rbp),%eax\ncmp -0x4c(%rbp),%eax\njl 13e5 \nmovl $0x0,-0x28(%rbp)\nmovl $0x0,-0x24(%rbp)\njmp 14e9 \ncmpl $0x0,-0x24(%rbp)\nje 14b0 \nmov -0x24(%rbp),%eax\ncltq\nshl $0x3,%rax\nlea -0x8(%rax),%rdx\nmov -0x58(%rbp),%rax\nadd %rax,%rdx\nmov -0x24(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x58(%rbp),%rax\nadd %rcx,%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 11c9 \ntest %eax,%eax\nje 14e5 \nmov -0x24(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x58(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x28(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x28(%rbp)\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x58(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%rax\nmov %rax,(%rdx)\naddl $0x1,-0x24(%rbp)\nmov -0x24(%rbp),%eax\ncmp -0x50(%rbp),%eax\njl 1473 \nmov -0x30(%rbp),%eax\ncmp %eax,-0x28(%rbp)\ncmovle -0x28(%rbp),%eax\ncltq\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0x20(%rbp)\nmovl $0x0,-0x1c(%rbp)\nmovl $0x0,-0x18(%rbp)\njmpq 15b2 \nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x58(%rbp),%rax\nadd %rax,%rdx\nmov -0x1c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x48(%rbp),%rax\nadd %rcx,%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 11c9 \nmov %eax,-0x14(%rbp)\ncmpl $0x0,-0x14(%rbp)\njne 15a2 \nmov -0x1c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x48(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x20(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x20(%rbp)\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%rax\nmov %rax,(%rdx)\naddl $0x1,-0x1c(%rbp)\naddl $0x1,-0x18(%rbp)\njmp 15b2 \ncmpl $0x0,-0x14(%rbp)\njns 15ae \naddl $0x1,-0x1c(%rbp)\njmp 15b2 \naddl $0x1,-0x18(%rbp)\nmov -0x1c(%rbp),%eax\ncmp -0x30(%rbp),%eax\njge 15c6 \nmov -0x18(%rbp),%eax\ncmp -0x28(%rbp),%eax\njl 1527 \nmov -0x60(%rbp),%rax\nmov -0x20(%rbp),%edx\nmov %edx,(%rax)\nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 60h\nmov [rbp+base], rdi\nmov [rbp+var_4C], esi\nmov [rbp+var_58], rdx\nmov [rbp+var_50], ecx\nmov [rbp+var_60], r8\nmov [rbp+var_38], 0\njmp loc_12DF\nloc_1249:\nmov eax, [rbp+var_38]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_38]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rax, rcx\nmov eax, [rax+4]\ncmp edx, eax\njle short loc_12DB\nmov eax, [rbp+var_38]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nmov eax, [rbp+var_38]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+base]\nadd rdx, rcx\nmov eax, [rax+4]\nmov [rdx], eax\nmov eax, [rbp+var_38]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rdx, rax\nmov eax, [rbp+var_C]\nmov [rdx+4], eax\nloc_12DB:\nadd [rbp+var_38], 1\nloc_12DF:\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_4C]\njl loc_1249\nmov [rbp+var_34], 0\njmp loc_138D\nloc_12F7:\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_34]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_58]\nadd rax, rcx\nmov eax, [rax+4]\ncmp edx, eax\njle short loc_1389\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_10], eax\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov edx, [rbp+var_34]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_58]\nadd rdx, rcx\nmov eax, [rax+4]\nmov [rdx], eax\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_58]\nadd rdx, rax\nmov eax, [rbp+var_10]\nmov [rdx+4], eax\nloc_1389:\nadd [rbp+var_34], 1\nloc_138D:\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_50]\njl loc_12F7\nmov eax, [rbp+var_4C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, tuple_compare\nmov rcx, rdx; compar\nmov edx, 8; size\nmov rdi, rax; base\ncall _qsort\nmov eax, [rbp+var_50]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+var_58]\nlea rdx, tuple_compare\nmov rcx, rdx; compar\nmov edx, 8; size\nmov rdi, rax; base\ncall _qsort\nmov [rbp+var_30], 0\nmov [rbp+var_2C], 0\njmp short loc_1461\nloc_13EB:\ncmp [rbp+var_2C], 0\njz short loc_1428\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 3\nlea rdx, [rax-8]\nmov rax, [rbp+base]\nadd rdx, rax\nmov eax, [rbp+var_2C]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rax, rcx\nmov rsi, rdx; void *\nmov rdi, rax; void *\ncall tuple_compare\ntest eax, eax\njz short loc_145D\nloc_1428:\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+base]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_30]\nlea edx, [rax+1]\nmov [rbp+var_30], edx\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rdx, rax\nmov rax, [rcx]\nmov [rdx], rax\nloc_145D:\nadd [rbp+var_2C], 1\nloc_1461:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_4C]\njl short loc_13EB\nmov [rbp+var_28], 0\nmov [rbp+var_24], 0\njmp short loc_14EF\nloc_1479:\ncmp [rbp+var_24], 0\njz short loc_14B6\nmov eax, [rbp+var_24]\ncdqe\nshl rax, 3\nlea rdx, [rax-8]\nmov rax, [rbp+var_58]\nadd rdx, rax\nmov eax, [rbp+var_24]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_58]\nadd rax, rcx\nmov rsi, rdx; void *\nmov rdi, rax; void *\ncall tuple_compare\ntest eax, eax\njz short loc_14EB\nloc_14B6:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_58]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_28]\nlea edx, [rax+1]\nmov [rbp+var_28], edx\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_58]\nadd rdx, rax\nmov rax, [rcx]\nmov [rdx], rax\nloc_14EB:\nadd [rbp+var_24], 1\nloc_14EF:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_50]\njl short loc_1479\nmov edx, [rbp+var_28]\nmov eax, [rbp+var_30]\ncmp edx, eax\ncmovle eax, edx\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_20], 0\nmov [rbp+var_1C], 0\nmov [rbp+var_18], 0\njmp loc_15B9\nloc_152E:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_58]\nadd rdx, rax\nmov eax, [rbp+var_1C]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rax, rcx\nmov rsi, rdx; void *\nmov rdi, rax; void *\ncall tuple_compare\nmov [rbp+var_14], eax\ncmp [rbp+var_14], 0\njnz short loc_15A9\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+base]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_20]\nlea edx, [rax+1]\nmov [rbp+var_20], edx\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov rax, [rcx]\nmov [rdx], rax\nadd [rbp+var_1C], 1\nadd [rbp+var_18], 1\njmp short loc_15B9\nloc_15A9:\ncmp [rbp+var_14], 0\njns short loc_15B5\nadd [rbp+var_1C], 1\njmp short loc_15B9\nloc_15B5:\nadd [rbp+var_18], 1\nloc_15B9:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_30]\njge short loc_15CD\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_28]\njl loc_152E\nloc_15CD:\nmov rax, [rbp+var_60]\nmov edx, [rbp+var_20]\nmov [rax], edx\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(_DWORD *a1, int a2, _DWORD *a3, int a4, _DWORD *a5)\n{\n int v5; // eax\n int v6; // eax\n int v7; // eax\n int v8; // eax\n int i; // [rsp+28h] [rbp-38h]\n int j; // [rsp+2Ch] [rbp-34h]\n int v15; // [rsp+30h] [rbp-30h]\n int k; // [rsp+34h] [rbp-2Ch]\n int v17; // [rsp+38h] [rbp-28h]\n int m; // [rsp+3Ch] [rbp-24h]\n int v19; // [rsp+40h] [rbp-20h]\n int v20; // [rsp+44h] [rbp-1Ch]\n int v21; // [rsp+48h] [rbp-18h]\n int v22; // [rsp+4Ch] [rbp-14h]\n int v23; // [rsp+50h] [rbp-10h]\n int v24; // [rsp+54h] [rbp-Ch]\n _QWORD *v25; // [rsp+58h] [rbp-8h]\n\n for ( i = 0; i < a2; ++i )\n {\n if ( a1[2 * i] > a1[2 * i + 1] )\n {\n v24 = a1[2 * i];\n a1[2 * i] = a1[2 * i + 1];\n a1[2 * i + 1] = v24;\n }\n }\n for ( j = 0; j < a4; ++j )\n {\n if ( a3[2 * j] > a3[2 * j + 1] )\n {\n v23 = a3[2 * j];\n a3[2 * j] = a3[2 * j + 1];\n a3[2 * j + 1] = v23;\n }\n }\n qsort(a1, a2, 8uLL, tuple_compare);\n qsort(a3, a4, 8uLL, tuple_compare);\n v15 = 0;\n for ( k = 0; k < a2; ++k )\n {\n if ( !k || tuple_compare(&a1[2 * k], &a1[2 * k - 2]) )\n {\n v5 = v15++;\n *(_QWORD *)&a1[2 * v5] = *(_QWORD *)&a1[2 * k];\n }\n }\n v17 = 0;\n for ( m = 0; m < a4; ++m )\n {\n if ( !m || tuple_compare(&a3[2 * m], &a3[2 * m - 2]) )\n {\n v6 = v17++;\n *(_QWORD *)&a3[2 * v6] = *(_QWORD *)&a3[2 * m];\n }\n }\n v7 = v15;\n if ( v17 <= v15 )\n v7 = v17;\n v25 = malloc(8LL * v7);\n v19 = 0;\n v20 = 0;\n v21 = 0;\n while ( v20 < v15 && v21 < v17 )\n {\n v22 = tuple_compare(&a1[2 * v20], &a3[2 * v21]);\n if ( v22 )\n {\n if ( v22 >= 0 )\n ++v21;\n else\n ++v20;\n }\n else\n {\n v8 = v19++;\n v25[v8] = *(_QWORD *)&a1[2 * v20++];\n ++v21;\n }\n }\n *a5 = v19;\n return v25;\n}", + "ida_strip_asm": "sub_121F:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 60h\nmov [rbp+base], rdi\nmov [rbp+var_4C], esi\nmov [rbp+var_58], rdx\nmov [rbp+var_50], ecx\nmov [rbp+var_60], r8\nmov [rbp+var_38], 0\njmp loc_12DF\nloc_1249:\nmov eax, [rbp+var_38]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_38]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rax, rcx\nmov eax, [rax+4]\ncmp edx, eax\njle short loc_12DB\nmov eax, [rbp+var_38]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nmov eax, [rbp+var_38]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+base]\nadd rdx, rcx\nmov eax, [rax+4]\nmov [rdx], eax\nmov eax, [rbp+var_38]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rdx, rax\nmov eax, [rbp+var_C]\nmov [rdx+4], eax\nloc_12DB:\nadd [rbp+var_38], 1\nloc_12DF:\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_4C]\njl loc_1249\nmov [rbp+var_34], 0\njmp loc_138D\nloc_12F7:\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_34]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_58]\nadd rax, rcx\nmov eax, [rax+4]\ncmp edx, eax\njle short loc_1389\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_10], eax\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov edx, [rbp+var_34]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_58]\nadd rdx, rcx\nmov eax, [rax+4]\nmov [rdx], eax\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_58]\nadd rdx, rax\nmov eax, [rbp+var_10]\nmov [rdx+4], eax\nloc_1389:\nadd [rbp+var_34], 1\nloc_138D:\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_50]\njl loc_12F7\nmov eax, [rbp+var_4C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 8; size\nmov rdi, rax; base\ncall _qsort\nmov eax, [rbp+var_50]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+var_58]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 8; size\nmov rdi, rax; base\ncall _qsort\nmov [rbp+var_30], 0\nmov [rbp+var_2C], 0\njmp short loc_1461\nloc_13EB:\ncmp [rbp+var_2C], 0\njz short loc_1428\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 3\nlea rdx, [rax-8]\nmov rax, [rbp+base]\nadd rdx, rax\nmov eax, [rbp+var_2C]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rax, rcx\nmov rsi, rdx; void *\nmov rdi, rax; void *\ncall compar\ntest eax, eax\njz short loc_145D\nloc_1428:\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+base]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_30]\nlea edx, [rax+1]\nmov [rbp+var_30], edx\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rdx, rax\nmov rax, [rcx]\nmov [rdx], rax\nloc_145D:\nadd [rbp+var_2C], 1\nloc_1461:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_4C]\njl short loc_13EB\nmov [rbp+var_28], 0\nmov [rbp+var_24], 0\njmp short loc_14EF\nloc_1479:\ncmp [rbp+var_24], 0\njz short loc_14B6\nmov eax, [rbp+var_24]\ncdqe\nshl rax, 3\nlea rdx, [rax-8]\nmov rax, [rbp+var_58]\nadd rdx, rax\nmov eax, [rbp+var_24]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_58]\nadd rax, rcx\nmov rsi, rdx; void *\nmov rdi, rax; void *\ncall compar\ntest eax, eax\njz short loc_14EB\nloc_14B6:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_58]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_28]\nlea edx, [rax+1]\nmov [rbp+var_28], edx\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_58]\nadd rdx, rax\nmov rax, [rcx]\nmov [rdx], rax\nloc_14EB:\nadd [rbp+var_24], 1\nloc_14EF:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_50]\njl short loc_1479\nmov edx, [rbp+var_28]\nmov eax, [rbp+var_30]\ncmp edx, eax\ncmovle eax, edx\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_20], 0\nmov [rbp+var_1C], 0\nmov [rbp+var_18], 0\njmp loc_15B9\nloc_152E:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_58]\nadd rdx, rax\nmov eax, [rbp+var_1C]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rax, rcx\nmov rsi, rdx; void *\nmov rdi, rax; void *\ncall compar\nmov [rbp+var_14], eax\ncmp [rbp+var_14], 0\njnz short loc_15A9\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+base]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_20]\nlea edx, [rax+1]\nmov [rbp+var_20], edx\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov rax, [rcx]\nmov [rdx], rax\nadd [rbp+var_1C], 1\nadd [rbp+var_18], 1\njmp short loc_15B9\nloc_15A9:\ncmp [rbp+var_14], 0\njns short loc_15B5\nadd [rbp+var_1C], 1\njmp short loc_15B9\nloc_15B5:\nadd [rbp+var_18], 1\nloc_15B9:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_30]\njge short loc_15CD\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_28]\njl loc_152E\nloc_15CD:\nmov rax, [rbp+var_60]\nmov edx, [rbp+var_20]\nmov [rax], edx\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_121F(_DWORD *a1, int a2, _DWORD *a3, int a4, _DWORD *a5)\n{\n int v5; // eax\n int v6; // eax\n int v7; // eax\n int v8; // eax\n int i; // [rsp+28h] [rbp-38h]\n int j; // [rsp+2Ch] [rbp-34h]\n int v15; // [rsp+30h] [rbp-30h]\n int k; // [rsp+34h] [rbp-2Ch]\n int v17; // [rsp+38h] [rbp-28h]\n int m; // [rsp+3Ch] [rbp-24h]\n int v19; // [rsp+40h] [rbp-20h]\n int v20; // [rsp+44h] [rbp-1Ch]\n int v21; // [rsp+48h] [rbp-18h]\n int v22; // [rsp+4Ch] [rbp-14h]\n int v23; // [rsp+50h] [rbp-10h]\n int v24; // [rsp+54h] [rbp-Ch]\n _QWORD *v25; // [rsp+58h] [rbp-8h]\n\n for ( i = 0; i < a2; ++i )\n {\n if ( a1[2 * i] > a1[2 * i + 1] )\n {\n v24 = a1[2 * i];\n a1[2 * i] = a1[2 * i + 1];\n a1[2 * i + 1] = v24;\n }\n }\n for ( j = 0; j < a4; ++j )\n {\n if ( a3[2 * j] > a3[2 * j + 1] )\n {\n v23 = a3[2 * j];\n a3[2 * j] = a3[2 * j + 1];\n a3[2 * j + 1] = v23;\n }\n }\n qsort(a1, a2, 8uLL, compar);\n qsort(a3, a4, 8uLL, compar);\n v15 = 0;\n for ( k = 0; k < a2; ++k )\n {\n if ( !k || compar(&a1[2 * k], &a1[2 * k - 2]) )\n {\n v5 = v15++;\n *(_QWORD *)&a1[2 * v5] = *(_QWORD *)&a1[2 * k];\n }\n }\n v17 = 0;\n for ( m = 0; m < a4; ++m )\n {\n if ( !m || compar(&a3[2 * m], &a3[2 * m - 2]) )\n {\n v6 = v17++;\n *(_QWORD *)&a3[2 * v6] = *(_QWORD *)&a3[2 * m];\n }\n }\n v7 = v15;\n if ( v17 <= v15 )\n v7 = v17;\n v25 = malloc(8LL * v7);\n v19 = 0;\n v20 = 0;\n v21 = 0;\n while ( v20 < v15 && v21 < v17 )\n {\n v22 = compar(&a1[2 * v20], &a3[2 * v21]);\n if ( v22 )\n {\n if ( v22 >= 0 )\n ++v21;\n else\n ++v20;\n }\n else\n {\n v8 = v19++;\n v25[v8] = *(_QWORD *)&a1[2 * v20++];\n ++v21;\n }\n }\n *a5 = v19;\n return v25;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_121F(uint32_t *a1, int a2, uint32_t *a3, int a4, uint32_t *a5) {\n int v5;\n int v6;\n int v7;\n int v8;\n int i;\n int j;\n int v15;\n int k;\n int v17;\n int m;\n int v19;\n int v20;\n int v21;\n int v22;\n int v23;\n int v24;\n uint64_t *v25;\n for (i = 0; i < a2; ++i) {\n if (a1[2 * i] > a1[2 * i + 1]) {\n v24 = a1[2 * i];\n a1[2 * i] = a1[2 * i + 1];\n a1[2 * i + 1] = v24;\n }\n }\n for (j = 0; j < a4; ++j) {\n if (a3[2 * j] > a3[2 * j + 1]) {\n v23 = a3[2 * j];\n a3[2 * j] = a3[2 * j + 1];\n a3[2 * j + 1] = v23;\n }\n }\n qsort(a1, a2, 8uLL, compar);\n qsort(a3, a4, 8uLL, compar);\n v15 = 0;\n for (k = 0; k < a2; ++k) {\n if (!k || compar(&a1[2 * k], &a1[2 * k - 2])) {\n v5 = v15++;\n *(uint64_t *)&a1[2 * v5] = *(uint64_t *)&a1[2 * k];\n }\n }\n v17 = 0;\n for (m = 0; m < a4; ++m) {\n if (!m || compar(&a3[2 * m], &a3[2 * m - 2])) {\n v6 = v17++;\n *(uint64_t *)&a3[2 * v6] = *(uint64_t *)&a3[2 * m];\n }\n }\n v7 = v15;\n if (v17 <= v15) v7 = v17;\n v25 = malloc(8LL * v7);\n v19 = 0;\n v20 = 0;\n v21 = 0;\n while (v20 < v15 && v21 < v17) {\n v22 = compar(&a1[2 * v20], &a3[2 * v21]);\n if (v22) {\n if (v22 >= 0)\n ++v21;\n else\n ++v20;\n } else {\n v8 = v19++;\n v25[v8] = *(uint64_t *)&a1[2 * v20++];\n ++v21;\n }\n }\n *a5 = v19;\n return v25;\n}", + "ida_pseudo_norm": "uint64_t *func0(uint32_t *a1, int a2, uint32_t *a3, int a4, uint32_t *a5) {\n int v5;\n int v6;\n int v7;\n int v8;\n int i;\n int j;\n int v15;\n int k;\n int v17;\n int m;\n int v19;\n int v20;\n int v21;\n int v22;\n int v23;\n int v24;\n uint64_t *v25;\n for (i = 0; i < a2; ++i) {\n if (a1[2 * i] > a1[2 * i + 1]) {\n v24 = a1[2 * i];\n a1[2 * i] = a1[2 * i + 1];\n a1[2 * i + 1] = v24;\n }\n }\n for (j = 0; j < a4; ++j) {\n if (a3[2 * j] > a3[2 * j + 1]) {\n v23 = a3[2 * j];\n a3[2 * j] = a3[2 * j + 1];\n a3[2 * j + 1] = v23;\n }\n }\n qsort(a1, a2, 8uLL, tuple_compare);\n qsort(a3, a4, 8uLL, tuple_compare);\n v15 = 0;\n for (k = 0; k < a2; ++k) {\n if (!k || tuple_compare(&a1[2 * k], &a1[2 * k - 2])) {\n v5 = v15++;\n *(uint64_t *)&a1[2 * v5] = *(uint64_t *)&a1[2 * k];\n }\n }\n v17 = 0;\n for (m = 0; m < a4; ++m) {\n if (!m || tuple_compare(&a3[2 * m], &a3[2 * m - 2])) {\n v6 = v17++;\n *(uint64_t *)&a3[2 * v6] = *(uint64_t *)&a3[2 * m];\n }\n }\n v7 = v15;\n if (v17 <= v15) v7 = v17;\n v25 = malloc(8LL * v7);\n v19 = 0;\n v20 = 0;\n v21 = 0;\n while (v20 < v15 && v21 < v17) {\n v22 = tuple_compare(&a1[2 * v20], &a3[2 * v21]);\n if (v22) {\n if (v22 >= 0)\n ++v21;\n else\n ++v20;\n } else {\n v8 = v19++;\n v25[v8] = *(uint64_t *)&a1[2 * v20++];\n ++v21;\n }\n }\n *a5 = v19;\n return v25;\n}" + }, + { + "index": 473, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n} tuple;\n\n\n\n// Compare two tuples for qsort and bsearch\n\nint tuple_compare(const void *a, const void *b) {\n\n tuple *t1 = (tuple *)a;\n\n tuple *t2 = (tuple *)b;\n\n if (t1->first != t2->first)\n\n return t1->first - t2->first;\n\n return t1->second - t2->second;\n\n}\n\n\n\n// Function to perform tuple intersection\n\n", + "func": "tuple *func0(tuple *list1, int size1, tuple *list2, int size2, int *res_size) {\n for (int i = 0; i < size1; i++) {\n if (list1[i].first > list1[i].second) {\n int temp = list1[i].first;\n list1[i].first = list1[i].second;\n list1[i].second = temp;\n }\n }\n for (int i = 0; i < size2; i++) {\n if (list2[i].first > list2[i].second) {\n int temp = list2[i].first;\n list2[i].first = list2[i].second;\n list2[i].second = temp;\n }\n }\n qsort(list1, size1, sizeof(tuple), tuple_compare);\n qsort(list2, size2, sizeof(tuple), tuple_compare);\n int unique1 = 0;\n for (int i = 0; i < size1; i++) {\n if (i == 0 || tuple_compare(&list1[i], &list1[i - 1]) != 0) {\n list1[unique1++] = list1[i];\n }\n }\n int unique2 = 0;\n for (int i = 0; i < size2; i++) {\n if (i == 0 || tuple_compare(&list2[i], &list2[i - 1]) != 0) {\n list2[unique2++] = list2[i];\n }\n }\n tuple *res = malloc(sizeof(tuple) * (unique1 < unique2 ? unique1 : unique2));\n int count = 0, i_idx = 0, j_idx = 0;\n while (i_idx < unique1 && j_idx < unique2) {\n int cmp = tuple_compare(&list1[i_idx], &list2[j_idx]);\n if (cmp == 0) {\n res[count++] = list1[i_idx];\n i_idx++;\n j_idx++;\n }\n else if (cmp < 0)\n i_idx++;\n else\n j_idx++;\n }\n *res_size = count;\n return res;\n}", + "test": "int main() {\n\n // First test\n\n tuple list1_1[] = { {3,4}, {5,6}, {9,10}, {4,5} };\n\n int size1_1 = 4;\n\n tuple list2_1[] = { {5,4}, {3,4}, {6,5}, {9,11} };\n\n int size2_1 = 4;\n\n int res_size_1;\n\n tuple *res1 = func0(list1_1, size1_1, list2_1, size2_1, &res_size_1);\n\n tuple expected1[] = { {3,4}, {4,5}, {5,6} };\n\n int expected_size1 = 3;\n\n assert(res_size_1 == expected_size1);\n\n for(int i=0;i\nmov %rdi,%rax\nlea -0x1(%rsi),%edx\nlea 0x8(%rdi,%rdx,8),%rsi\njmp 121d \nadd $0x8,%rax\ncmp %rsi,%rax\nje 122d \nmov (%rax),%edx\nmov 0x4(%rax),%ecx\ncmp %ecx,%edx\njle 1214 \nmov %ecx,(%rax)\nmov %edx,0x4(%rax)\njmp 1214 \ntest %r15d,%r15d\njle 13d9 \nmov (%rsp),%rdi\nmov %rdi,%rax\nlea -0x1(%r15),%edx\nlea 0x8(%rdi,%rdx,8),%rsi\njmp 1255 \nadd $0x8,%rax\ncmp %rsi,%rax\nje 1388 \nmov (%rax),%edx\nmov 0x4(%rax),%ecx\ncmp %ecx,%edx\njle 1248 \nmov %ecx,(%rax)\nmov %edx,0x4(%rax)\njmp 1248 \nmovslq %r12d,%rax\nmov 0x0(%rbp),%rdx\nmov %rdx,(%r14,%rax,8)\nlea 0x1(%r12),%r12d\nadd $0x1,%ebx\nadd $0x8,%rbp\ncmp %ebx,%r13d\nje 1297 \ntest %ebx,%ebx\nje 1265 \nlea -0x8(%rbp),%rsi\nmov %rbp,%rdi\ncallq 11c9 \ntest %eax,%eax\nje 1275 \njmp 1265 \ntest %r15d,%r15d\njle 1413 \nmov (%rsp),%rbp\nmov $0x0,%ebx\nmov $0x0,%r13d\njmp 12d0 \nmovslq %r13d,%rax\nmov 0x0(%rbp),%rdx\nmov (%rsp),%rdi\nmov %rdx,(%rdi,%rax,8)\nlea 0x1(%r13),%r13d\nadd $0x1,%ebx\nadd $0x8,%rbp\ncmp %ebx,%r15d\nje 12e6 \ntest %ebx,%ebx\nje 12b1 \nlea -0x8(%rbp),%rsi\nmov %rbp,%rdi\ncallq 11c9 \ntest %eax,%eax\nje 12c4 \njmp 12b1 \ncmp %r13d,%r12d\nmov %r13d,%edi\ncmovle %r12d,%edi\nmovslq %edi,%rdi\nshl $0x3,%rdi\ncallq 10d0 \nmov %rax,0x10(%rsp)\ntest %r12d,%r12d\njle 137b \ntest %r13d,%r13d\njle 137b \nmov $0x0,%ebx\nmov $0x0,%ebp\nmovl $0x0,0xc(%rsp)\njmp 1336 \njs 1376 \nadd $0x1,%ebx\ncmp %ebp,%r12d\njle 1438 \ncmp %r13d,%ebx\njge 1438 \nmovslq %ebp,%rax\nlea (%r14,%rax,8),%r15\nmovslq %ebx,%rax\nmov (%rsp),%rdi\nlea (%rdi,%rax,8),%rsi\nmov %r15,%rdi\ncallq 11c9 \ntest %eax,%eax\njne 131f \nmov 0xc(%rsp),%ecx\nmovslq %ecx,%rax\nmov (%r15),%rdx\nmov 0x10(%rsp),%rdi\nmov %rdx,(%rdi,%rax,8)\nadd $0x1,%ebp\nadd $0x1,%ebx\nlea 0x1(%rcx),%eax\nmov %eax,0xc(%rsp)\njmp 1324 \nadd $0x1,%ebp\njmp 1324 \nmovl $0x0,0xc(%rsp)\njmpq 1438 \nmovslq %r13d,%rsi\nlea -0x1c9(%rip),%rcx\nmov $0x8,%edx\nmov %r14,%rdi\ncallq 10a0 \nmovslq %r15d,%rsi\nlea -0x1e0(%rip),%rcx\nmov $0x8,%edx\nmov (%rsp),%rdi\ncallq 10a0 \nmov $0x0,%r12d\ntest %r13d,%r13d\njle 12a0 \nmov %r14,%rbp\nmov $0x0,%ebx\nmov $0x0,%r12d\njmpq 1281 \nmovslq %r13d,%rsi\nlea -0x21a(%rip),%rcx\nmov $0x8,%edx\nmov %r14,%rdi\ncallq 10a0 \nmovslq %r15d,%rsi\nlea -0x231(%rip),%rcx\nmov $0x8,%edx\nmov (%rsp),%rdi\ncallq 10a0 \nmov $0x0,%r12d\ntest %r13d,%r13d\njg 13c6 \ntest %r12d,%r12d\nmov $0x0,%edi\ncmovle %r12d,%edi\nmovslq %edi,%rdi\nshl $0x3,%rdi\ncallq 10d0 \nmov %rax,0x10(%rsp)\nmovl $0x0,0xc(%rsp)\nmov 0x18(%rsp),%rax\nmov 0xc(%rsp),%edi\nmov %edi,(%rax)\nmov 0x10(%rsp),%rax\nadd $0x28,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov [rsp+58h+base], rdi\nmov r13d, esi\nmov r14, rdx\nmov r15d, ecx\nmov [rsp+58h+var_40], r8\ntest esi, esi\njle short loc_122C\nmov rax, rdi\nmovsxd rdx, esi\nlea rsi, [rdi+rdx*8]\njmp short loc_121C\nloc_1213:\nadd rax, 8\ncmp rax, rsi\njz short loc_122C\nloc_121C:\nmov edx, [rax]\nmov ecx, [rax+4]\ncmp edx, ecx\njle short loc_1213\nmov [rax], ecx\nmov [rax+4], edx\njmp short loc_1213\nloc_122C:\ntest r15d, r15d\njle loc_137D\nmov rax, r14\nmovsxd rdx, r15d\nlea rsi, [r14+rdx*8]\njmp short loc_124E\nloc_1241:\nadd rax, 8\ncmp rax, rsi\njz loc_13FE\nloc_124E:\nmov edx, [rax]\nmov ecx, [rax+4]\ncmp edx, ecx\njle short loc_1241\nmov [rax], ecx\nmov [rax+4], edx\njmp short loc_1241\nloc_125E:\nmovsxd rax, r12d\nmov rdx, [rbp+0]\nmov rdi, [rsp+58h+base]\nmov [rdi+rax*8], rdx\nlea r12d, [r12+1]\nloc_1272:\nadd ebx, 1\nadd rbp, 8\ncmp r13d, ebx\njz short loc_1294\nloc_127E:\ntest ebx, ebx\njz short loc_125E\nlea rsi, [rbp-8]; void *\nmov rdi, rbp; void *\ncall tuple_compare\ntest eax, eax\njz short loc_1272\njmp short loc_125E\nloc_1294:\ntest r15d, r15d\njle loc_13BA\nloc_129D:\nmov rbp, r14\nmov ebx, 0\nmov r13d, 0\njmp short loc_12C8\nloc_12AD:\nmovsxd rax, r13d\nmov rdx, [rbp+0]\nmov [r14+rax*8], rdx\nlea r13d, [r13+1]\nloc_12BC:\nadd ebx, 1\nadd rbp, 8\ncmp r15d, ebx\njz short loc_12DE\nloc_12C8:\ntest ebx, ebx\njz short loc_12AD\nlea rsi, [rbp-8]; void *\nmov rdi, rbp; void *\ncall tuple_compare\ntest eax, eax\njz short loc_12BC\njmp short loc_12AD\nloc_12DE:\ncmp r12d, r13d\nmov edi, r13d\ncmovle edi, r12d\nmovsxd rdi, edi\nshl rdi, 3; size\ncall _malloc\nmov [rsp+58h+var_48], rax\ntest r12d, r12d\njle short loc_1373\ntest r13d, r13d\njle short loc_1373\nmov ebx, 0\nmov ebp, 0\nmov [rsp+58h+var_4C], 0\njmp short loc_132E\nloc_1317:\njs short loc_136E\nadd ebx, 1\nloc_131C:\ncmp r12d, ebp\njle loc_13DF\ncmp ebx, r13d\njge loc_13DF\nloc_132E:\nmovsxd rax, ebp\nmov rdi, [rsp+58h+base]\nlea r15, [rdi+rax*8]\nmovsxd rax, ebx\nlea rsi, [r14+rax*8]; void *\nmov rdi, r15; void *\ncall tuple_compare\ntest eax, eax\njnz short loc_1317\nmov ecx, [rsp+58h+var_4C]\nmovsxd rax, ecx\nmov rdx, [r15]\nmov rdi, [rsp+58h+var_48]\nmov [rdi+rax*8], rdx\nadd ebp, 1\nadd ebx, 1\nlea eax, [rcx+1]\nmov [rsp+58h+var_4C], eax\njmp short loc_131C\nloc_136E:\nadd ebp, 1\njmp short loc_131C\nloc_1373:\nmov [rsp+58h+var_4C], 0\njmp short loc_13DF\nloc_137D:\nmovsxd rsi, r13d; nmemb\nlea rbx, tuple_compare\nmov rcx, rbx; compar\nmov edx, 8; size\nmov rdi, [rsp+58h+base]; base\ncall _qsort\nmovsxd rsi, r15d; nmemb\nmov rcx, rbx; compar\nmov edx, 8; size\nmov rdi, r14; base\ncall _qsort\nmov r12d, 0\ntest r13d, r13d\njg loc_143B\nloc_13BA:\ntest r12d, r12d\nmov edi, 0\ncmovle edi, r12d\nmovsxd rdi, edi\nshl rdi, 3; size\ncall _malloc\nmov [rsp+58h+var_48], rax\nmov [rsp+58h+var_4C], 0\nloc_13DF:\nmov rax, [rsp+58h+var_40]\nmov ecx, [rsp+58h+var_4C]\nmov [rax], ecx\nmov rax, [rsp+58h+var_48]\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_13FE:\nmovsxd rsi, r13d; nmemb\nlea rbx, tuple_compare\nmov rcx, rbx; compar\nmov edx, 8; size\nmov rdi, [rsp+58h+base]; base\ncall _qsort\nmovsxd rsi, r15d; nmemb\nmov rcx, rbx; compar\nmov edx, 8; size\nmov rdi, r14; base\ncall _qsort\nmov r12d, 0\ntest r13d, r13d\njle loc_129D\nloc_143B:\nmov rbp, [rsp+58h+base]\nmov ebx, 0\nmov r12d, 0\njmp loc_127E", + "ida_pseudo": "_QWORD *__fastcall func0(int *a1, int a2, char *a3, int a4, _DWORD *a5)\n{\n int *v8; // rax\n int *v9; // rsi\n int v10; // edx\n int v11; // ecx\n char *v12; // rax\n int v13; // edx\n int v14; // ecx\n int v15; // r12d\n int v16; // ebx\n int *v17; // rbp\n _QWORD *v18; // rbp\n int v19; // ebx\n int v20; // r13d\n int v21; // edi\n int v22; // ebx\n int v23; // ebp\n int v24; // eax\n int v25; // edi\n int v28; // [rsp+Ch] [rbp-4Ch]\n _QWORD *v29; // [rsp+10h] [rbp-48h]\n\n if ( a2 > 0 )\n {\n v8 = a1;\n v9 = &a1[2 * a2];\n do\n {\n v10 = *v8;\n v11 = v8[1];\n if ( *v8 > v11 )\n {\n *v8 = v11;\n v8[1] = v10;\n }\n v8 += 2;\n }\n while ( v8 != v9 );\n }\n if ( a4 <= 0 )\n {\n qsort(a1, a2, 8uLL, tuple_compare);\n qsort(a3, a4, 8uLL, tuple_compare);\n v15 = 0;\n if ( a2 <= 0 )\n goto LABEL_37;\n }\n else\n {\n v12 = a3;\n do\n {\n v13 = *(_DWORD *)v12;\n v14 = *((_DWORD *)v12 + 1);\n if ( *(_DWORD *)v12 > v14 )\n {\n *(_DWORD *)v12 = v14;\n *((_DWORD *)v12 + 1) = v13;\n }\n v12 += 8;\n }\n while ( v12 != &a3[8 * a4] );\n qsort(a1, a2, 8uLL, tuple_compare);\n qsort(a3, a4, 8uLL, tuple_compare);\n v15 = 0;\n if ( a2 <= 0 )\n goto LABEL_17;\n }\n v17 = a1;\n v16 = 0;\n v15 = 0;\n do\n {\n if ( !v16 || tuple_compare(v17, v17 - 2) )\n *(_QWORD *)&a1[2 * v15++] = *(_QWORD *)v17;\n ++v16;\n v17 += 2;\n }\n while ( a2 != v16 );\n if ( a4 > 0 )\n {\nLABEL_17:\n v18 = a3;\n v19 = 0;\n v20 = 0;\n do\n {\n if ( !v19 || tuple_compare(v18, v18 - 1) )\n *(_QWORD *)&a3[8 * v20++] = *v18;\n ++v19;\n ++v18;\n }\n while ( a4 != v19 );\n v21 = v20;\n if ( v15 <= v20 )\n v21 = v15;\n v29 = malloc(8LL * v21);\n if ( v15 <= 0 || v20 <= 0 )\n {\n v28 = 0;\n }\n else\n {\n v22 = 0;\n v23 = 0;\n v28 = 0;\n do\n {\n v24 = tuple_compare(&a1[2 * v23], &a3[8 * v22]);\n if ( v24 )\n {\n if ( v24 < 0 )\n ++v23;\n else\n ++v22;\n }\n else\n {\n v29[v28] = *(_QWORD *)&a1[2 * v23++];\n ++v22;\n ++v28;\n }\n }\n while ( v15 > v23 && v22 < v20 );\n }\n goto LABEL_40;\n }\nLABEL_37:\n v25 = 0;\n if ( v15 <= 0 )\n v25 = v15;\n v29 = malloc(8LL * v25);\n v28 = 0;\nLABEL_40:\n *a5 = v28;\n return v29;\n}", + "ida_strip_asm": "sub_11DF:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov [rsp+58h+base], rdi\nmov r13d, esi\nmov r14, rdx\nmov r15d, ecx\nmov [rsp+58h+var_40], r8\ntest esi, esi\njle short loc_122C\nmov rax, rdi\nmovsxd rdx, esi\nlea rsi, [rdi+rdx*8]\njmp short loc_121C\nloc_1213:\nadd rax, 8\ncmp rax, rsi\njz short loc_122C\nloc_121C:\nmov edx, [rax]\nmov ecx, [rax+4]\ncmp edx, ecx\njle short loc_1213\nmov [rax], ecx\nmov [rax+4], edx\njmp short loc_1213\nloc_122C:\ntest r15d, r15d\njle loc_137D\nmov rax, r14\nmovsxd rdx, r15d\nlea rsi, [r14+rdx*8]\njmp short loc_124E\nloc_1241:\nadd rax, 8\ncmp rax, rsi\njz loc_13FE\nloc_124E:\nmov edx, [rax]\nmov ecx, [rax+4]\ncmp edx, ecx\njle short loc_1241\nmov [rax], ecx\nmov [rax+4], edx\njmp short loc_1241\nloc_125E:\nmovsxd rax, r12d\nmov rdx, [rbp+0]\nmov rdi, [rsp+58h+base]\nmov [rdi+rax*8], rdx\nlea r12d, [r12+1]\nloc_1272:\nadd ebx, 1\nadd rbp, 8\ncmp r13d, ebx\njz short loc_1294\nloc_127E:\ntest ebx, ebx\njz short loc_125E\nlea rsi, [rbp-8]; void *\nmov rdi, rbp; void *\ncall compar\ntest eax, eax\njz short loc_1272\njmp short loc_125E\nloc_1294:\ntest r15d, r15d\njle loc_13BA\nloc_129D:\nmov rbp, r14\nmov ebx, 0\nmov r13d, 0\njmp short loc_12C8\nloc_12AD:\nmovsxd rax, r13d\nmov rdx, [rbp+0]\nmov [r14+rax*8], rdx\nlea r13d, [r13+1]\nloc_12BC:\nadd ebx, 1\nadd rbp, 8\ncmp r15d, ebx\njz short loc_12DE\nloc_12C8:\ntest ebx, ebx\njz short loc_12AD\nlea rsi, [rbp-8]; void *\nmov rdi, rbp; void *\ncall compar\ntest eax, eax\njz short loc_12BC\njmp short loc_12AD\nloc_12DE:\ncmp r12d, r13d\nmov edi, r13d\ncmovle edi, r12d\nmovsxd rdi, edi\nshl rdi, 3; size\ncall _malloc\nmov [rsp+58h+var_48], rax\ntest r12d, r12d\njle short loc_1373\ntest r13d, r13d\njle short loc_1373\nmov ebx, 0\nmov ebp, 0\nmov [rsp+58h+var_4C], 0\njmp short loc_132E\nloc_1317:\njs short loc_136E\nadd ebx, 1\nloc_131C:\ncmp r12d, ebp\njle loc_13DF\ncmp ebx, r13d\njge loc_13DF\nloc_132E:\nmovsxd rax, ebp\nmov rdi, [rsp+58h+base]\nlea r15, [rdi+rax*8]\nmovsxd rax, ebx\nlea rsi, [r14+rax*8]; void *\nmov rdi, r15; void *\ncall compar\ntest eax, eax\njnz short loc_1317\nmov ecx, [rsp+58h+var_4C]\nmovsxd rax, ecx\nmov rdx, [r15]\nmov rdi, [rsp+58h+var_48]\nmov [rdi+rax*8], rdx\nadd ebp, 1\nadd ebx, 1\nlea eax, [rcx+1]\nmov [rsp+58h+var_4C], eax\njmp short loc_131C\nloc_136E:\nadd ebp, 1\njmp short loc_131C\nloc_1373:\nmov [rsp+58h+var_4C], 0\njmp short loc_13DF\nloc_137D:\nmovsxd rsi, r13d; nmemb\nlea rbx, compar\nmov rcx, rbx; compar\nmov edx, 8; size\nmov rdi, [rsp+58h+base]; base\ncall _qsort\nmovsxd rsi, r15d; nmemb\nmov rcx, rbx; compar\nmov edx, 8; size\nmov rdi, r14; base\ncall _qsort\nmov r12d, 0\ntest r13d, r13d\njg loc_143B\nloc_13BA:\ntest r12d, r12d\nmov edi, 0\ncmovle edi, r12d\nmovsxd rdi, edi\nshl rdi, 3; size\ncall _malloc\nmov [rsp+58h+var_48], rax\nmov [rsp+58h+var_4C], 0\nloc_13DF:\nmov rax, [rsp+58h+var_40]\nmov ecx, [rsp+58h+var_4C]\nmov [rax], ecx\nmov rax, [rsp+58h+var_48]\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_13FE:\nmovsxd rsi, r13d; nmemb\nlea rbx, compar\nmov rcx, rbx; compar\nmov edx, 8; size\nmov rdi, [rsp+58h+base]; base\ncall _qsort\nmovsxd rsi, r15d; nmemb\nmov rcx, rbx; compar\nmov edx, 8; size\nmov rdi, r14; base\ncall _qsort\nmov r12d, 0\ntest r13d, r13d\njle loc_129D\nloc_143B:\nmov rbp, [rsp+58h+base]\nmov ebx, 0\nmov r12d, 0\njmp loc_127E", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11DF(int *a1, int a2, char *a3, int a4, _DWORD *a5)\n{\n int *v8; // rax\n int *v9; // rsi\n int v10; // edx\n int v11; // ecx\n char *v12; // rax\n int v13; // edx\n int v14; // ecx\n int v15; // r12d\n int v16; // ebx\n int *v17; // rbp\n _QWORD *v18; // rbp\n int v19; // ebx\n int v20; // r13d\n int v21; // edi\n int v22; // ebx\n int v23; // ebp\n int v24; // eax\n int v25; // edi\n int v28; // [rsp+Ch] [rbp-4Ch]\n _QWORD *v29; // [rsp+10h] [rbp-48h]\n\n if ( a2 > 0 )\n {\n v8 = a1;\n v9 = &a1[2 * a2];\n do\n {\n v10 = *v8;\n v11 = v8[1];\n if ( *v8 > v11 )\n {\n *v8 = v11;\n v8[1] = v10;\n }\n v8 += 2;\n }\n while ( v8 != v9 );\n }\n if ( a4 <= 0 )\n {\n qsort(a1, a2, 8uLL, compar);\n qsort(a3, a4, 8uLL, compar);\n v15 = 0;\n if ( a2 <= 0 )\n goto LABEL_37;\n }\n else\n {\n v12 = a3;\n do\n {\n v13 = *(_DWORD *)v12;\n v14 = *((_DWORD *)v12 + 1);\n if ( *(_DWORD *)v12 > v14 )\n {\n *(_DWORD *)v12 = v14;\n *((_DWORD *)v12 + 1) = v13;\n }\n v12 += 8;\n }\n while ( v12 != &a3[8 * a4] );\n qsort(a1, a2, 8uLL, compar);\n qsort(a3, a4, 8uLL, compar);\n v15 = 0;\n if ( a2 <= 0 )\n goto LABEL_17;\n }\n v17 = a1;\n v16 = 0;\n v15 = 0;\n do\n {\n if ( !v16 || compar(v17, v17 - 2) )\n *(_QWORD *)&a1[2 * v15++] = *(_QWORD *)v17;\n ++v16;\n v17 += 2;\n }\n while ( a2 != v16 );\n if ( a4 > 0 )\n {\nLABEL_17:\n v18 = a3;\n v19 = 0;\n v20 = 0;\n do\n {\n if ( !v19 || compar(v18, v18 - 1) )\n *(_QWORD *)&a3[8 * v20++] = *v18;\n ++v19;\n ++v18;\n }\n while ( a4 != v19 );\n v21 = v20;\n if ( v15 <= v20 )\n v21 = v15;\n v29 = malloc(8LL * v21);\n if ( v15 <= 0 || v20 <= 0 )\n {\n v28 = 0;\n }\n else\n {\n v22 = 0;\n v23 = 0;\n v28 = 0;\n do\n {\n v24 = compar(&a1[2 * v23], &a3[8 * v22]);\n if ( v24 )\n {\n if ( v24 < 0 )\n ++v23;\n else\n ++v22;\n }\n else\n {\n v29[v28] = *(_QWORD *)&a1[2 * v23++];\n ++v22;\n ++v28;\n }\n }\n while ( v15 > v23 && v22 < v20 );\n }\n goto LABEL_40;\n }\nLABEL_37:\n v25 = 0;\n if ( v15 <= 0 )\n v25 = v15;\n v29 = malloc(8LL * v25);\n v28 = 0;\nLABEL_40:\n *a5 = v28;\n return v29;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11DF(int *a1, int a2, char *a3, int a4, uint32_t *a5) {\n int *v8;\n int *v9;\n int v10;\n int v11;\n char *v12;\n int v13;\n int v14;\n int v15;\n int v16;\n int *v17;\n uint64_t *v18;\n int v19;\n int v20;\n int v21;\n int v22;\n int v23;\n int v24;\n int v25;\n int v28;\n uint64_t *v29;\n if (a2 > 0) {\n v8 = a1;\n v9 = &a1[2 * a2];\n do {\n v10 = *v8;\n v11 = v8[1];\n if (*v8 > v11) {\n *v8 = v11;\n v8[1] = v10;\n }\n v8 += 2;\n } while (v8 != v9);\n }\n if (a4 <= 0) {\n qsort(a1, a2, 8uLL, compar);\n qsort(a3, a4, 8uLL, compar);\n v15 = 0;\n if (a2 <= 0) goto LABEL_37;\n } else {\n v12 = a3;\n do {\n v13 = *(uint32_t *)v12;\n v14 = *((uint32_t *)v12 + 1);\n if (*(uint32_t *)v12 > v14) {\n *(uint32_t *)v12 = v14;\n *((uint32_t *)v12 + 1) = v13;\n }\n v12 += 8;\n } while (v12 != &a3[8 * a4]);\n qsort(a1, a2, 8uLL, compar);\n qsort(a3, a4, 8uLL, compar);\n v15 = 0;\n if (a2 <= 0) goto LABEL_17;\n }\n v17 = a1;\n v16 = 0;\n v15 = 0;\n do {\n if (!v16 || compar(v17, v17 - 2))\n *(uint64_t *)&a1[2 * v15++] = *(uint64_t *)v17;\n ++v16;\n v17 += 2;\n } while (a2 != v16);\n if (a4 > 0) {\n LABEL_17:\n v18 = a3;\n v19 = 0;\n v20 = 0;\n do {\n if (!v19 || compar(v18, v18 - 1)) *(uint64_t *)&a3[8 * v20++] = *v18;\n ++v19;\n ++v18;\n } while (a4 != v19);\n v21 = v20;\n if (v15 <= v20) v21 = v15;\n v29 = malloc(8LL * v21);\n if (v15 <= 0 || v20 <= 0) {\n v28 = 0;\n } else {\n v22 = 0;\n v23 = 0;\n v28 = 0;\n do {\n v24 = compar(&a1[2 * v23], &a3[8 * v22]);\n if (v24) {\n if (v24 < 0)\n ++v23;\n else\n ++v22;\n } else {\n v29[v28] = *(uint64_t *)&a1[2 * v23++];\n ++v22;\n ++v28;\n }\n } while (v15 > v23 && v22 < v20);\n }\n goto LABEL_40;\n }\nLABEL_37:\n v25 = 0;\n if (v15 <= 0) v25 = v15;\n v29 = malloc(8LL * v25);\n v28 = 0;\nLABEL_40:\n *a5 = v28;\n return v29;\n}", + "ida_pseudo_norm": "uint64_t *func0(int *a1, int a2, char *a3, int a4, uint32_t *a5) {\n int *v8;\n int *v9;\n int v10;\n int v11;\n char *v12;\n int v13;\n int v14;\n int v15;\n int v16;\n int *v17;\n uint64_t *v18;\n int v19;\n int v20;\n int v21;\n int v22;\n int v23;\n int v24;\n int v25;\n int v28;\n uint64_t *v29;\n if (a2 > 0) {\n v8 = a1;\n v9 = &a1[2 * a2];\n do {\n v10 = *v8;\n v11 = v8[1];\n if (*v8 > v11) {\n *v8 = v11;\n v8[1] = v10;\n }\n v8 += 2;\n } while (v8 != v9);\n }\n if (a4 <= 0) {\n qsort(a1, a2, 8uLL, tuple_compare);\n qsort(a3, a4, 8uLL, tuple_compare);\n v15 = 0;\n if (a2 <= 0) goto LABEL_37;\n } else {\n v12 = a3;\n do {\n v13 = *(uint32_t *)v12;\n v14 = *((uint32_t *)v12 + 1);\n if (*(uint32_t *)v12 > v14) {\n *(uint32_t *)v12 = v14;\n *((uint32_t *)v12 + 1) = v13;\n }\n v12 += 8;\n } while (v12 != &a3[8 * a4]);\n qsort(a1, a2, 8uLL, tuple_compare);\n qsort(a3, a4, 8uLL, tuple_compare);\n v15 = 0;\n if (a2 <= 0) goto LABEL_17;\n }\n v17 = a1;\n v16 = 0;\n v15 = 0;\n do {\n if (!v16 || tuple_compare(v17, v17 - 2))\n *(uint64_t *)&a1[2 * v15++] = *(uint64_t *)v17;\n ++v16;\n v17 += 2;\n } while (a2 != v16);\n if (a4 > 0) {\n LABEL_17:\n v18 = a3;\n v19 = 0;\n v20 = 0;\n do {\n if (!v19 || tuple_compare(v18, v18 - 1))\n *(uint64_t *)&a3[8 * v20++] = *v18;\n ++v19;\n ++v18;\n } while (a4 != v19);\n v21 = v20;\n if (v15 <= v20) v21 = v15;\n v29 = malloc(8LL * v21);\n if (v15 <= 0 || v20 <= 0) {\n v28 = 0;\n } else {\n v22 = 0;\n v23 = 0;\n v28 = 0;\n do {\n v24 = tuple_compare(&a1[2 * v23], &a3[8 * v22]);\n if (v24) {\n if (v24 < 0)\n ++v23;\n else\n ++v22;\n } else {\n v29[v28] = *(uint64_t *)&a1[2 * v23++];\n ++v22;\n ++v28;\n }\n } while (v15 > v23 && v22 < v20);\n }\n goto LABEL_40;\n }\nLABEL_37:\n v25 = 0;\n if (v15 <= 0) v25 = v15;\n v29 = malloc(8LL * v25);\n v28 = 0;\nLABEL_40:\n *a5 = v28;\n return v29;\n}" + }, + { + "index": 473, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n} tuple;\n\n\n\n// Compare two tuples for qsort and bsearch\n\nint tuple_compare(const void *a, const void *b) {\n\n tuple *t1 = (tuple *)a;\n\n tuple *t2 = (tuple *)b;\n\n if (t1->first != t2->first)\n\n return t1->first - t2->first;\n\n return t1->second - t2->second;\n\n}\n\n\n\n// Function to perform tuple intersection\n\n", + "func": "tuple *func0(tuple *list1, int size1, tuple *list2, int size2, int *res_size) {\n for (int i = 0; i < size1; i++) {\n if (list1[i].first > list1[i].second) {\n int temp = list1[i].first;\n list1[i].first = list1[i].second;\n list1[i].second = temp;\n }\n }\n for (int i = 0; i < size2; i++) {\n if (list2[i].first > list2[i].second) {\n int temp = list2[i].first;\n list2[i].first = list2[i].second;\n list2[i].second = temp;\n }\n }\n qsort(list1, size1, sizeof(tuple), tuple_compare);\n qsort(list2, size2, sizeof(tuple), tuple_compare);\n int unique1 = 0;\n for (int i = 0; i < size1; i++) {\n if (i == 0 || tuple_compare(&list1[i], &list1[i - 1]) != 0) {\n list1[unique1++] = list1[i];\n }\n }\n int unique2 = 0;\n for (int i = 0; i < size2; i++) {\n if (i == 0 || tuple_compare(&list2[i], &list2[i - 1]) != 0) {\n list2[unique2++] = list2[i];\n }\n }\n tuple *res = malloc(sizeof(tuple) * (unique1 < unique2 ? unique1 : unique2));\n int count = 0, i_idx = 0, j_idx = 0;\n while (i_idx < unique1 && j_idx < unique2) {\n int cmp = tuple_compare(&list1[i_idx], &list2[j_idx]);\n if (cmp == 0) {\n res[count++] = list1[i_idx];\n i_idx++;\n j_idx++;\n }\n else if (cmp < 0)\n i_idx++;\n else\n j_idx++;\n }\n *res_size = count;\n return res;\n}", + "test": "int main() {\n\n // First test\n\n tuple list1_1[] = { {3,4}, {5,6}, {9,10}, {4,5} };\n\n int size1_1 = 4;\n\n tuple list2_1[] = { {5,4}, {3,4}, {6,5}, {9,11} };\n\n int size2_1 = 4;\n\n int res_size_1;\n\n tuple *res1 = func0(list1_1, size1_1, list2_1, size2_1, &res_size_1);\n\n tuple expected1[] = { {3,4}, {4,5}, {5,6} };\n\n int expected_size1 = 3;\n\n assert(res_size_1 == expected_size1);\n\n for(int i=0;i\nlea -0x1(%rsi),%edx\nmov %rdi,%rax\nlea 0x8(%rdi,%rdx,8),%rsi\nmov (%rax),%edx\nmov 0x4(%rax),%ecx\ncmp %ecx,%edx\njle 162e \nmov %ecx,(%rax)\nmov %edx,0x4(%rax)\nadd $0x8,%rax\ncmp %rax,%rsi\njne 1620 \ntest %r14d,%r14d\njle 17f0 \nlea -0x1(%r14),%edx\nmov %rbp,%rax\nmov %rdx,%r15\nlea 0x8(%rbp,%rdx,8),%rsi\nmov (%rax),%edx\nmov 0x4(%rax),%ecx\ncmp %ecx,%edx\njle 165e \nmov %ecx,(%rax)\nmov %edx,0x4(%rax)\nadd $0x8,%rax\ncmp %rax,%rsi\njne 1650 \nmovslq %r13d,%rsi\nlea -0xa1(%rip),%rcx\nmov $0x8,%edx\nmov %r12,%rdi\ncallq 10a0 \nmovslq %r14d,%rsi\nmov $0x8,%edx\nmov %rbp,%rdi\nlea -0xc0(%rip),%rcx\ncallq 10a0 \ntest %r13d,%r13d\njle 1840 \nlea -0x1(%r13),%esi\nxor %eax,%eax\nxor %r13d,%r13d\njmp 16d3 \nnopl 0x0(%rax)\nmov -0x8(%r12,%rax,8),%edi\ncmp %edi,(%r12,%rax,8)\njne 16d8 \nmov -0x4(%r12,%rax,8),%edi\ncmp %edi,0x4(%r12,%rax,8)\njne 16d8 \nlea 0x1(%rax),%rdx\ncmp %rax,%rsi\nje 16f0 \nmov %rdx,%rax\ntest %rax,%rax\njne 16b0 \nmov (%r12,%rax,8),%rcx\nmovslq %r13d,%rdx\nadd $0x1,%r13d\nmov %rcx,(%r12,%rdx,8)\nlea 0x1(%rax),%rdx\ncmp %rax,%rsi\njne 16d0 \ntest %r14d,%r14d\njle 1830 \nlea -0x1(%r14),%r15d\nmov %r15d,%esi\nxor %eax,%eax\nxor %r14d,%r14d\njmp 1730 \nnopw 0x0(%rax,%rax,1)\nmov -0x8(%rbp,%rax,8),%edi\ncmp %edi,0x0(%rbp,%rax,8)\njne 1735 \nmov -0x4(%rbp,%rax,8),%edi\ncmp %edi,0x4(%rbp,%rax,8)\njne 1735 \nlea 0x1(%rax),%rdx\ncmp %rsi,%rax\nje 174f \nmov %rdx,%rax\ntest %rax,%rax\njne 1710 \nmov 0x0(%rbp,%rax,8),%rcx\nmovslq %r14d,%rdx\nadd $0x1,%r14d\nmov %rcx,0x0(%rbp,%rdx,8)\nlea 0x1(%rax),%rdx\ncmp %rsi,%rax\njne 172d \ncmp %r14d,%r13d\nmov %r14d,%edi\ncmovle %r13d,%edi\nmovslq %edi,%rdi\nshl $0x3,%rdi\ncallq 10d0 \ntest %r13d,%r13d\njle 1848 \ntest %r14d,%r14d\njle 1848 \nxor %ecx,%ecx\nxor %esi,%esi\nxor %r10d,%r10d\njmp 1794 \nsub %r9d,%edx\ntest %edx,%edx\njs 17e8 \nadd $0x1,%ecx\ncmp %esi,%r13d\njle 17cf \ncmp %r14d,%ecx\njge 17cf \nmovslq %ecx,%rdx\nlea 0x0(%rbp,%rdx,8),%r8\nmovslq %esi,%rdx\nlea (%r12,%rdx,8),%rdi\nmov (%r8),%r9d\nmov (%rdi),%edx\ncmp %r9d,%edx\njne 1780 \nmov 0x4(%rdi),%edx\nsub 0x4(%r8),%edx\njne 1783 \nmov (%rdi),%rdi\nmovslq %r10d,%rdx\nadd $0x1,%esi\nadd $0x1,%ecx\nadd $0x1,%r10d\nmov %rdi,(%rax,%rdx,8)\ncmp %esi,%r13d\njg 178f \nmov %r10d,(%rbx)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\nadd $0x1,%esi\njmp 178a \nnopl (%rax)\nmovslq %r13d,%rsi\nlea -0x22a(%rip),%rcx\nmov $0x8,%edx\nmov %r12,%rdi\ncallq 10a0 \nmovslq %r14d,%rsi\nmov $0x8,%edx\nmov %rbp,%rdi\nlea -0x249(%rip),%rcx\ncallq 10a0 \ntest %r13d,%r13d\njg 169e \nnopw 0x0(%rax,%rax,1)\nxor %edi,%edi\ncallq 10d0 \nxor %r10d,%r10d\njmp 17cf \nnopl 0x0(%rax)\nxor %r13d,%r13d\njmpq 16fd \nxor %r10d,%r10d\njmp 17cf \nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14d, esi\npush r13\nmov r13d, ecx\npush r12\nmov r12, rdx\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_48], r8\ntest esi, esi\njle loc_1758\nmovsxd r15, esi\nmov rax, rdi\nlea rsi, [rdi+r15*8]\nnop dword ptr [rax+00h]\nloc_1568:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd edx, xmm0\nmovd ecx, xmm1\ncmp ecx, edx\njge short loc_1586\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_1586:\nadd rax, 8\ncmp rsi, rax\njnz short loc_1568\nmovsxd rbx, r13d\ntest r13d, r13d\njle short loc_15CF\nloc_1597:\nmovsxd rbx, r13d\nmov rax, r12\nlea rsi, [r12+rbx*8]\nnop dword ptr [rax+00000000h]\nloc_15A8:\nmovq xmm0, qword ptr [rax]\npshufd xmm2, xmm0, 0E5h\nmovd ecx, xmm0\nmovd edx, xmm2\ncmp ecx, edx\njle short loc_15C6\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_15C6:\nadd rax, 8\ncmp rax, rsi\njnz short loc_15A8\nloc_15CF:\nlea rcx, tuple_compare; compar\nmov edx, 8; size\nmov rsi, r15; nmemb\nmov rdi, rbp; base\ncall _qsort\nmov edx, 8; size\nmov rsi, rbx; nmemb\nmov rdi, r12; base\nlea rcx, tuple_compare; compar\ncall _qsort\nxor eax, eax\nxor edx, edx\ntest r14d, r14d\njg short loc_162D\njmp short loc_164B\nloc_1610:\nmov edi, [rbp+rax*8-8]\ncmp [rbp+rax*8+0], edi\njnz short loc_1632\nmov edi, [rbp+rax*8-4]\ncmp [rbp+rax*8+4], edi\njnz short loc_1632\nadd rax, 1\ncmp r15, rax\njz short loc_164B\nloc_162D:\ntest rax, rax\njnz short loc_1610\nloc_1632:\nmov rsi, [rbp+rax*8+0]\nmovsxd rcx, edx\nadd rax, 1\nadd edx, 1\nmov [rbp+rcx*8+0], rsi\ncmp r15, rax\njnz short loc_162D\nloc_164B:\ntest r13d, r13d\njle loc_1798\nxor eax, eax\nxor r13d, r13d\njmp short loc_1680\nloc_1660:\nmov edi, [r12+rax*8-8]\ncmp [r12+rax*8], edi\njnz short loc_1685\nmov esi, [r12+rax*8-4]\ncmp [r12+rax*8+4], esi\njnz short loc_1685\nadd rax, 1\ncmp rbx, rax\njz short loc_169D\nloc_1680:\ntest rax, rax\njnz short loc_1660\nloc_1685:\nmov rsi, [r12+rax*8]\nmovsxd rcx, r13d\nadd rax, 1\nadd r13d, 1\nmov [r12+rcx*8], rsi\ncmp rbx, rax\njnz short loc_1680\nloc_169D:\ncmp r13d, edx\nmov edi, edx\nmov [rsp+48h+var_3C], edx\ncmovle edi, r13d\nmovsxd rdi, edi\nshl rdi, 3; size\ncall _malloc\nmov r11, rax\ntest r13d, r13d\njle loc_17AE\nmov edx, [rsp+48h+var_3C]\ntest edx, edx\njle loc_17AE\nxor ecx, ecx\nxor esi, esi\nxor r10d, r10d\njmp short loc_16F3\nloc_16E0:\nsub eax, r9d\nloc_16E3:\ntest eax, eax\njs short loc_1750\nadd ecx, 1\nloc_16EA:\ncmp esi, edx\njge short loc_172D\nloc_16EE:\ncmp ecx, r13d\njge short loc_172D\nloc_16F3:\nmovsxd rax, ecx\nlea r8, [r12+rax*8]\nmovsxd rax, esi\nlea rdi, [rbp+rax*8+0]\nmov r9d, [r8]\nmov eax, [rdi]\ncmp eax, r9d\njnz short loc_16E0\nmov eax, [rdi+4]\nsub eax, [r8+4]\njnz short loc_16E3\nmov rdi, [rdi]\nmovsxd rax, r10d\nadd esi, 1\nadd ecx, 1\nadd r10d, 1\nmov [r11+rax*8], rdi\ncmp esi, edx\njl short loc_16EE\nloc_172D:\nmov rax, [rsp+48h+var_48]\nmov [rax], r10d\nadd rsp, 18h\nmov rax, r11\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1750:\nadd esi, 1\njmp short loc_16EA\nloc_1758:\nmovsxd r15, esi\ntest ecx, ecx\njg loc_1597\nlea r14, tuple_compare\nmov edx, 8; size\nmov rsi, r15; nmemb\nmov rdi, rbp; base\nmov rcx, r14; compar\ncall _qsort\nmov edx, 8; size\nmovsxd rsi, r13d; nmemb\nmov rcx, r14; compar\nmov rdi, r12; base\ncall _qsort\nxor edx, edx\nnop word ptr [rax+rax+00h]\nloc_1798:\nxor edi, edi\ntest edx, edx\ncmovle edi, edx\nmovsxd rdi, edi\nshl rdi, 3; size\ncall _malloc\nmov r11, rax\nloc_17AE:\nxor r10d, r10d\njmp loc_172D", + "ida_pseudo": "_QWORD *__fastcall func0(__m128i *base, int a2, __m128i *a3, int a4, _DWORD *a5)\n{\n size_t v9; // r15\n __m128i *v10; // rax\n __m128i *v11; // rsi\n __m128i v12; // xmm0\n size_t v13; // rbx\n __m128i *v14; // rax\n __m128i v15; // xmm0\n __int64 v16; // rax\n int v17; // edx\n __int64 v18; // rsi\n __int64 v19; // rcx\n __int64 v20; // rax\n int v21; // r13d\n __int64 v22; // rsi\n __int64 v23; // rcx\n int v24; // edi\n _QWORD *v25; // r11\n int v26; // ecx\n int v27; // esi\n int v28; // r10d\n int v29; // eax\n __int32 *v30; // r8\n char *v31; // rdi\n __int64 v32; // rax\n int v34; // edi\n int v36; // [rsp+Ch] [rbp-3Ch]\n\n if ( a2 <= 0 )\n {\n v9 = a2;\n if ( a4 <= 0 )\n {\n qsort(base, a2, 8uLL, tuple_compare);\n qsort(a3, a4, 8uLL, tuple_compare);\n v17 = 0;\nLABEL_42:\n v34 = 0;\n if ( v17 <= 0 )\n v34 = v17;\n v25 = malloc(8LL * v34);\n goto LABEL_45;\n }\n goto LABEL_7;\n }\n v9 = a2;\n v10 = base;\n v11 = (__m128i *)((char *)base + 8 * a2);\n do\n {\n v12 = _mm_loadl_epi64(v10);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v12, 229)) < _mm_cvtsi128_si32(v12) )\n v10->m128i_i64[0] = _mm_shuffle_epi32(v12, 225).m128i_u64[0];\n v10 = (__m128i *)((char *)v10 + 8);\n }\n while ( v11 != v10 );\n v13 = a4;\n if ( a4 > 0 )\n {\nLABEL_7:\n v13 = a4;\n v14 = a3;\n do\n {\n v15 = _mm_loadl_epi64(v14);\n if ( _mm_cvtsi128_si32(v15) > _mm_cvtsi128_si32(_mm_shuffle_epi32(v15, 229)) )\n v14->m128i_i64[0] = _mm_shuffle_epi32(v15, 225).m128i_u64[0];\n v14 = (__m128i *)((char *)v14 + 8);\n }\n while ( v14 != (__m128i *)((char *)a3 + 8 * a4) );\n }\n qsort(base, v9, 8uLL, tuple_compare);\n qsort(a3, v13, 8uLL, tuple_compare);\n v16 = 0LL;\n v17 = 0;\n if ( a2 > 0 )\n {\n do\n {\n while ( v16\n && base->m128i_i32[2 * v16] == base->m128i_i32[2 * v16 - 2]\n && base->m128i_i32[2 * v16 + 1] == base->m128i_i32[2 * v16 - 1] )\n {\n if ( v9 == ++v16 )\n goto LABEL_18;\n }\n v18 = base->m128i_i64[v16];\n v19 = v17;\n ++v16;\n ++v17;\n base->m128i_i64[v19] = v18;\n }\n while ( v9 != v16 );\n }\nLABEL_18:\n if ( a4 <= 0 )\n goto LABEL_42;\n v20 = 0LL;\n v21 = 0;\n do\n {\n while ( v20\n && a3->m128i_i32[2 * v20] == a3->m128i_i32[2 * v20 - 2]\n && a3->m128i_i32[2 * v20 + 1] == a3->m128i_i32[2 * v20 - 1] )\n {\n if ( v13 == ++v20 )\n goto LABEL_25;\n }\n v22 = a3->m128i_i64[v20];\n v23 = v21;\n ++v20;\n ++v21;\n a3->m128i_i64[v23] = v22;\n }\n while ( v13 != v20 );\nLABEL_25:\n v24 = v17;\n v36 = v17;\n if ( v21 <= v17 )\n v24 = v21;\n v25 = malloc(8LL * v24);\n if ( v21 > 0 && v36 > 0 )\n {\n v26 = 0;\n v27 = 0;\n v28 = 0;\n while ( 1 )\n {\n v30 = &a3->m128i_i32[2 * v26];\n v31 = &base->m128i_i8[8 * v27];\n if ( *(_DWORD *)v31 == *v30 )\n {\n v29 = *((_DWORD *)v31 + 1) - v30[1];\n if ( !v29 )\n {\n v32 = v28;\n ++v27;\n ++v26;\n ++v28;\n v25[v32] = *(_QWORD *)v31;\n if ( v27 >= v36 )\n goto LABEL_38;\n goto LABEL_34;\n }\n }\n else\n {\n v29 = *(_DWORD *)v31 - *v30;\n }\n if ( v29 < 0 )\n ++v27;\n else\n ++v26;\n if ( v27 >= v36 )\n goto LABEL_38;\nLABEL_34:\n if ( v26 >= v21 )\n goto LABEL_38;\n }\n }\nLABEL_45:\n v28 = 0;\nLABEL_38:\n *a5 = v28;\n return v25;\n}", + "ida_strip_asm": "sub_1530:\nendbr64\npush r15\npush r14\nmov r14d, esi\npush r13\nmov r13d, ecx\npush r12\nmov r12, rdx\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_48], r8\ntest esi, esi\njle loc_1758\nmovsxd r15, esi\nmov rax, rdi\nlea rsi, [rdi+r15*8]\nnop dword ptr [rax+00h]\nloc_1568:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd edx, xmm0\nmovd ecx, xmm1\ncmp ecx, edx\njge short loc_1586\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_1586:\nadd rax, 8\ncmp rsi, rax\njnz short loc_1568\nmovsxd rbx, r13d\ntest r13d, r13d\njle short loc_15CF\nloc_1597:\nmovsxd rbx, r13d\nmov rax, r12\nlea rsi, [r12+rbx*8]\nnop dword ptr [rax+00000000h]\nloc_15A8:\nmovq xmm0, qword ptr [rax]\npshufd xmm2, xmm0, 0E5h\nmovd ecx, xmm0\nmovd edx, xmm2\ncmp ecx, edx\njle short loc_15C6\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_15C6:\nadd rax, 8\ncmp rax, rsi\njnz short loc_15A8\nloc_15CF:\nlea rcx, compar; compar\nmov edx, 8; size\nmov rsi, r15; nmemb\nmov rdi, rbp; base\ncall _qsort\nmov edx, 8; size\nmov rsi, rbx; nmemb\nmov rdi, r12; base\nlea rcx, compar; compar\ncall _qsort\nxor eax, eax\nxor edx, edx\ntest r14d, r14d\njg short loc_162D\njmp short loc_164B\nloc_1610:\nmov edi, [rbp+rax*8-8]\ncmp [rbp+rax*8+0], edi\njnz short loc_1632\nmov edi, [rbp+rax*8-4]\ncmp [rbp+rax*8+4], edi\njnz short loc_1632\nadd rax, 1\ncmp r15, rax\njz short loc_164B\nloc_162D:\ntest rax, rax\njnz short loc_1610\nloc_1632:\nmov rsi, [rbp+rax*8+0]\nmovsxd rcx, edx\nadd rax, 1\nadd edx, 1\nmov [rbp+rcx*8+0], rsi\ncmp r15, rax\njnz short loc_162D\nloc_164B:\ntest r13d, r13d\njle loc_1798\nxor eax, eax\nxor r13d, r13d\njmp short loc_1680\nloc_1660:\nmov edi, [r12+rax*8-8]\ncmp [r12+rax*8], edi\njnz short loc_1685\nmov esi, [r12+rax*8-4]\ncmp [r12+rax*8+4], esi\njnz short loc_1685\nadd rax, 1\ncmp rbx, rax\njz short loc_169D\nloc_1680:\ntest rax, rax\njnz short loc_1660\nloc_1685:\nmov rsi, [r12+rax*8]\nmovsxd rcx, r13d\nadd rax, 1\nadd r13d, 1\nmov [r12+rcx*8], rsi\ncmp rbx, rax\njnz short loc_1680\nloc_169D:\ncmp r13d, edx\nmov edi, edx\nmov [rsp+48h+var_3C], edx\ncmovle edi, r13d\nmovsxd rdi, edi\nshl rdi, 3; size\ncall _malloc\nmov r11, rax\ntest r13d, r13d\njle loc_17AE\nmov edx, [rsp+48h+var_3C]\ntest edx, edx\njle loc_17AE\nxor ecx, ecx\nxor esi, esi\nxor r10d, r10d\njmp short loc_16F3\nloc_16E0:\nsub eax, r9d\nloc_16E3:\ntest eax, eax\njs short loc_1750\nadd ecx, 1\nloc_16EA:\ncmp esi, edx\njge short loc_172D\nloc_16EE:\ncmp ecx, r13d\njge short loc_172D\nloc_16F3:\nmovsxd rax, ecx\nlea r8, [r12+rax*8]\nmovsxd rax, esi\nlea rdi, [rbp+rax*8+0]\nmov r9d, [r8]\nmov eax, [rdi]\ncmp eax, r9d\njnz short loc_16E0\nmov eax, [rdi+4]\nsub eax, [r8+4]\njnz short loc_16E3\nmov rdi, [rdi]\nmovsxd rax, r10d\nadd esi, 1\nadd ecx, 1\nadd r10d, 1\nmov [r11+rax*8], rdi\ncmp esi, edx\njl short loc_16EE\nloc_172D:\nmov rax, [rsp+48h+var_48]\nmov [rax], r10d\nadd rsp, 18h\nmov rax, r11\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1750:\nadd esi, 1\njmp short loc_16EA\nloc_1758:\nmovsxd r15, esi\ntest ecx, ecx\njg loc_1597\nlea r14, compar\nmov edx, 8; size\nmov rsi, r15; nmemb\nmov rdi, rbp; base\nmov rcx, r14; compar\ncall _qsort\nmov edx, 8; size\nmovsxd rsi, r13d; nmemb\nmov rcx, r14; compar\nmov rdi, r12; base\ncall _qsort\nxor edx, edx\nnop word ptr [rax+rax+00h]\nloc_1798:\nxor edi, edi\ntest edx, edx\ncmovle edi, edx\nmovsxd rdi, edi\nshl rdi, 3; size\ncall _malloc\nmov r11, rax\nloc_17AE:\nxor r10d, r10d\njmp loc_172D", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1530(__m128i *base, int a2, __m128i *a3, int a4, _DWORD *a5)\n{\n size_t v9; // r15\n __m128i *v10; // rax\n __m128i *v11; // rsi\n __m128i v12; // xmm0\n size_t v13; // rbx\n __m128i *v14; // rax\n __m128i v15; // xmm0\n __int64 v16; // rax\n int v17; // edx\n __int64 v18; // rsi\n __int64 v19; // rcx\n __int64 v20; // rax\n int v21; // r13d\n __int64 v22; // rsi\n __int64 v23; // rcx\n int v24; // edi\n _QWORD *v25; // r11\n int v26; // ecx\n int v27; // esi\n int v28; // r10d\n int v29; // eax\n __int32 *v30; // r8\n char *v31; // rdi\n __int64 v32; // rax\n int v34; // edi\n int v36; // [rsp+Ch] [rbp-3Ch]\n\n if ( a2 <= 0 )\n {\n v9 = a2;\n if ( a4 <= 0 )\n {\n qsort(base, a2, 8uLL, compar);\n qsort(a3, a4, 8uLL, compar);\n v17 = 0;\nLABEL_42:\n v34 = 0;\n if ( v17 <= 0 )\n v34 = v17;\n v25 = malloc(8LL * v34);\n goto LABEL_45;\n }\n goto LABEL_7;\n }\n v9 = a2;\n v10 = base;\n v11 = (__m128i *)((char *)base + 8 * a2);\n do\n {\n v12 = _mm_loadl_epi64(v10);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v12, 229)) < _mm_cvtsi128_si32(v12) )\n v10->m128i_i64[0] = _mm_shuffle_epi32(v12, 225).m128i_u64[0];\n v10 = (__m128i *)((char *)v10 + 8);\n }\n while ( v11 != v10 );\n v13 = a4;\n if ( a4 > 0 )\n {\nLABEL_7:\n v13 = a4;\n v14 = a3;\n do\n {\n v15 = _mm_loadl_epi64(v14);\n if ( _mm_cvtsi128_si32(v15) > _mm_cvtsi128_si32(_mm_shuffle_epi32(v15, 229)) )\n v14->m128i_i64[0] = _mm_shuffle_epi32(v15, 225).m128i_u64[0];\n v14 = (__m128i *)((char *)v14 + 8);\n }\n while ( v14 != (__m128i *)((char *)a3 + 8 * a4) );\n }\n qsort(base, v9, 8uLL, compar);\n qsort(a3, v13, 8uLL, compar);\n v16 = 0LL;\n v17 = 0;\n if ( a2 > 0 )\n {\n do\n {\n while ( v16\n && base->m128i_i32[2 * v16] == base->m128i_i32[2 * v16 - 2]\n && base->m128i_i32[2 * v16 + 1] == base->m128i_i32[2 * v16 - 1] )\n {\n if ( v9 == ++v16 )\n goto LABEL_18;\n }\n v18 = base->m128i_i64[v16];\n v19 = v17;\n ++v16;\n ++v17;\n base->m128i_i64[v19] = v18;\n }\n while ( v9 != v16 );\n }\nLABEL_18:\n if ( a4 <= 0 )\n goto LABEL_42;\n v20 = 0LL;\n v21 = 0;\n do\n {\n while ( v20\n && a3->m128i_i32[2 * v20] == a3->m128i_i32[2 * v20 - 2]\n && a3->m128i_i32[2 * v20 + 1] == a3->m128i_i32[2 * v20 - 1] )\n {\n if ( v13 == ++v20 )\n goto LABEL_25;\n }\n v22 = a3->m128i_i64[v20];\n v23 = v21;\n ++v20;\n ++v21;\n a3->m128i_i64[v23] = v22;\n }\n while ( v13 != v20 );\nLABEL_25:\n v24 = v17;\n v36 = v17;\n if ( v21 <= v17 )\n v24 = v21;\n v25 = malloc(8LL * v24);\n if ( v21 > 0 && v36 > 0 )\n {\n v26 = 0;\n v27 = 0;\n v28 = 0;\n while ( 1 )\n {\n v30 = &a3->m128i_i32[2 * v26];\n v31 = &base->m128i_i8[8 * v27];\n if ( *(_DWORD *)v31 == *v30 )\n {\n v29 = *((_DWORD *)v31 + 1) - v30[1];\n if ( !v29 )\n {\n v32 = v28;\n ++v27;\n ++v26;\n ++v28;\n v25[v32] = *(_QWORD *)v31;\n if ( v27 >= v36 )\n goto LABEL_38;\n goto LABEL_34;\n }\n }\n else\n {\n v29 = *(_DWORD *)v31 - *v30;\n }\n if ( v29 < 0 )\n ++v27;\n else\n ++v26;\n if ( v27 >= v36 )\n goto LABEL_38;\nLABEL_34:\n if ( v26 >= v21 )\n goto LABEL_38;\n }\n }\nLABEL_45:\n v28 = 0;\nLABEL_38:\n *a5 = v28;\n return v25;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1530(__m128i *base, int a2, __m128i *a3, int a4, uint32_t *a5) {\n unsigned int v9;\n __m128i *v10;\n __m128i *v11;\n __m128i v12;\n unsigned int v13;\n __m128i *v14;\n __m128i v15;\n long long v16;\n int v17;\n long long v18;\n long long v19;\n long long v20;\n int v21;\n long long v22;\n long long v23;\n int v24;\n uint64_t *v25;\n int v26;\n int v27;\n int v28;\n int v29;\n int *v30;\n char *v31;\n long long v32;\n int v34;\n int v36;\n if (a2 <= 0) {\n v9 = a2;\n if (a4 <= 0) {\n qsort(base, a2, 8uLL, compar);\n qsort(a3, a4, 8uLL, compar);\n v17 = 0;\n LABEL_42:\n v34 = 0;\n if (v17 <= 0) v34 = v17;\n v25 = malloc(8LL * v34);\n goto LABEL_45;\n }\n goto LABEL_7;\n }\n v9 = a2;\n v10 = base;\n v11 = (__m128i *)((char *)base + 8 * a2);\n do {\n v12 = _mm_loadl_epi64(v10);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v12, 229)) < _mm_cvtsi128_si32(v12))\n v10->m128i_i64[0] = _mm_shuffle_epi32(v12, 225).m128i_u64[0];\n v10 = (__m128i *)((char *)v10 + 8);\n } while (v11 != v10);\n v13 = a4;\n if (a4 > 0) {\n LABEL_7:\n v13 = a4;\n v14 = a3;\n do {\n v15 = _mm_loadl_epi64(v14);\n if (_mm_cvtsi128_si32(v15) >\n _mm_cvtsi128_si32(_mm_shuffle_epi32(v15, 229)))\n v14->m128i_i64[0] = _mm_shuffle_epi32(v15, 225).m128i_u64[0];\n v14 = (__m128i *)((char *)v14 + 8);\n } while (v14 != (__m128i *)((char *)a3 + 8 * a4));\n }\n qsort(base, v9, 8uLL, compar);\n qsort(a3, v13, 8uLL, compar);\n v16 = 0LL;\n v17 = 0;\n if (a2 > 0) {\n do {\n while (v16 && base->m128i_i32[2 * v16] == base->m128i_i32[2 * v16 - 2] &&\n base->m128i_i32[2 * v16 + 1] == base->m128i_i32[2 * v16 - 1]) {\n if (v9 == ++v16) goto LABEL_18;\n }\n v18 = base->m128i_i64[v16];\n v19 = v17;\n ++v16;\n ++v17;\n base->m128i_i64[v19] = v18;\n } while (v9 != v16);\n }\nLABEL_18:\n if (a4 <= 0) goto LABEL_42;\n v20 = 0LL;\n v21 = 0;\n do {\n while (v20 && a3->m128i_i32[2 * v20] == a3->m128i_i32[2 * v20 - 2] &&\n a3->m128i_i32[2 * v20 + 1] == a3->m128i_i32[2 * v20 - 1]) {\n if (v13 == ++v20) goto LABEL_25;\n }\n v22 = a3->m128i_i64[v20];\n v23 = v21;\n ++v20;\n ++v21;\n a3->m128i_i64[v23] = v22;\n } while (v13 != v20);\nLABEL_25:\n v24 = v17;\n v36 = v17;\n if (v21 <= v17) v24 = v21;\n v25 = malloc(8LL * v24);\n if (v21 > 0 && v36 > 0) {\n v26 = 0;\n v27 = 0;\n v28 = 0;\n while (1) {\n v30 = &a3->m128i_i32[2 * v26];\n v31 = &base->m128i_i8[8 * v27];\n if (*(uint32_t *)v31 == *v30) {\n v29 = *((uint32_t *)v31 + 1) - v30[1];\n if (!v29) {\n v32 = v28;\n ++v27;\n ++v26;\n ++v28;\n v25[v32] = *(uint64_t *)v31;\n if (v27 >= v36) goto LABEL_38;\n goto LABEL_34;\n }\n } else {\n v29 = *(uint32_t *)v31 - *v30;\n }\n if (v29 < 0)\n ++v27;\n else\n ++v26;\n if (v27 >= v36) goto LABEL_38;\n LABEL_34:\n if (v26 >= v21) goto LABEL_38;\n }\n }\nLABEL_45:\n v28 = 0;\nLABEL_38:\n *a5 = v28;\n return v25;\n}", + "ida_pseudo_norm": "uint64_t *func0(__m128i *base, int a2, __m128i *a3, int a4, uint32_t *a5) {\n unsigned int v9;\n __m128i *v10;\n __m128i *v11;\n __m128i v12;\n unsigned int v13;\n __m128i *v14;\n __m128i v15;\n long long v16;\n int v17;\n long long v18;\n long long v19;\n long long v20;\n int v21;\n long long v22;\n long long v23;\n int v24;\n uint64_t *v25;\n int v26;\n int v27;\n int v28;\n int v29;\n int *v30;\n char *v31;\n long long v32;\n int v34;\n int v36;\n if (a2 <= 0) {\n v9 = a2;\n if (a4 <= 0) {\n qsort(base, a2, 8uLL, tuple_compare);\n qsort(a3, a4, 8uLL, tuple_compare);\n v17 = 0;\n LABEL_42:\n v34 = 0;\n if (v17 <= 0) v34 = v17;\n v25 = malloc(8LL * v34);\n goto LABEL_45;\n }\n goto LABEL_7;\n }\n v9 = a2;\n v10 = base;\n v11 = (__m128i *)((char *)base + 8 * a2);\n do {\n v12 = _mm_loadl_epi64(v10);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v12, 229)) < _mm_cvtsi128_si32(v12))\n v10->m128i_i64[0] = _mm_shuffle_epi32(v12, 225).m128i_u64[0];\n v10 = (__m128i *)((char *)v10 + 8);\n } while (v11 != v10);\n v13 = a4;\n if (a4 > 0) {\n LABEL_7:\n v13 = a4;\n v14 = a3;\n do {\n v15 = _mm_loadl_epi64(v14);\n if (_mm_cvtsi128_si32(v15) >\n _mm_cvtsi128_si32(_mm_shuffle_epi32(v15, 229)))\n v14->m128i_i64[0] = _mm_shuffle_epi32(v15, 225).m128i_u64[0];\n v14 = (__m128i *)((char *)v14 + 8);\n } while (v14 != (__m128i *)((char *)a3 + 8 * a4));\n }\n qsort(base, v9, 8uLL, tuple_compare);\n qsort(a3, v13, 8uLL, tuple_compare);\n v16 = 0LL;\n v17 = 0;\n if (a2 > 0) {\n do {\n while (v16 && base->m128i_i32[2 * v16] == base->m128i_i32[2 * v16 - 2] &&\n base->m128i_i32[2 * v16 + 1] == base->m128i_i32[2 * v16 - 1]) {\n if (v9 == ++v16) goto LABEL_18;\n }\n v18 = base->m128i_i64[v16];\n v19 = v17;\n ++v16;\n ++v17;\n base->m128i_i64[v19] = v18;\n } while (v9 != v16);\n }\nLABEL_18:\n if (a4 <= 0) goto LABEL_42;\n v20 = 0LL;\n v21 = 0;\n do {\n while (v20 && a3->m128i_i32[2 * v20] == a3->m128i_i32[2 * v20 - 2] &&\n a3->m128i_i32[2 * v20 + 1] == a3->m128i_i32[2 * v20 - 1]) {\n if (v13 == ++v20) goto LABEL_25;\n }\n v22 = a3->m128i_i64[v20];\n v23 = v21;\n ++v20;\n ++v21;\n a3->m128i_i64[v23] = v22;\n } while (v13 != v20);\nLABEL_25:\n v24 = v17;\n v36 = v17;\n if (v21 <= v17) v24 = v21;\n v25 = malloc(8LL * v24);\n if (v21 > 0 && v36 > 0) {\n v26 = 0;\n v27 = 0;\n v28 = 0;\n while (1) {\n v30 = &a3->m128i_i32[2 * v26];\n v31 = &base->m128i_i8[8 * v27];\n if (*(uint32_t *)v31 == *v30) {\n v29 = *((uint32_t *)v31 + 1) - v30[1];\n if (!v29) {\n v32 = v28;\n ++v27;\n ++v26;\n ++v28;\n v25[v32] = *(uint64_t *)v31;\n if (v27 >= v36) goto LABEL_38;\n goto LABEL_34;\n }\n } else {\n v29 = *(uint32_t *)v31 - *v30;\n }\n if (v29 < 0)\n ++v27;\n else\n ++v26;\n if (v27 >= v36) goto LABEL_38;\n LABEL_34:\n if (v26 >= v21) goto LABEL_38;\n }\n }\nLABEL_45:\n v28 = 0;\nLABEL_38:\n *a5 = v28;\n return v25;\n}" + }, + { + "index": 473, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n} tuple;\n\n\n\n// Compare two tuples for qsort and bsearch\n\nint tuple_compare(const void *a, const void *b) {\n\n tuple *t1 = (tuple *)a;\n\n tuple *t2 = (tuple *)b;\n\n if (t1->first != t2->first)\n\n return t1->first - t2->first;\n\n return t1->second - t2->second;\n\n}\n\n\n\n// Function to perform tuple intersection\n\n", + "func": "tuple *func0(tuple *list1, int size1, tuple *list2, int size2, int *res_size) {\n for (int i = 0; i < size1; i++) {\n if (list1[i].first > list1[i].second) {\n int temp = list1[i].first;\n list1[i].first = list1[i].second;\n list1[i].second = temp;\n }\n }\n for (int i = 0; i < size2; i++) {\n if (list2[i].first > list2[i].second) {\n int temp = list2[i].first;\n list2[i].first = list2[i].second;\n list2[i].second = temp;\n }\n }\n qsort(list1, size1, sizeof(tuple), tuple_compare);\n qsort(list2, size2, sizeof(tuple), tuple_compare);\n int unique1 = 0;\n for (int i = 0; i < size1; i++) {\n if (i == 0 || tuple_compare(&list1[i], &list1[i - 1]) != 0) {\n list1[unique1++] = list1[i];\n }\n }\n int unique2 = 0;\n for (int i = 0; i < size2; i++) {\n if (i == 0 || tuple_compare(&list2[i], &list2[i - 1]) != 0) {\n list2[unique2++] = list2[i];\n }\n }\n tuple *res = malloc(sizeof(tuple) * (unique1 < unique2 ? unique1 : unique2));\n int count = 0, i_idx = 0, j_idx = 0;\n while (i_idx < unique1 && j_idx < unique2) {\n int cmp = tuple_compare(&list1[i_idx], &list2[j_idx]);\n if (cmp == 0) {\n res[count++] = list1[i_idx];\n i_idx++;\n j_idx++;\n }\n else if (cmp < 0)\n i_idx++;\n else\n j_idx++;\n }\n *res_size = count;\n return res;\n}", + "test": "int main() {\n\n // First test\n\n tuple list1_1[] = { {3,4}, {5,6}, {9,10}, {4,5} };\n\n int size1_1 = 4;\n\n tuple list2_1[] = { {5,4}, {3,4}, {6,5}, {9,11} };\n\n int size2_1 = 4;\n\n int res_size_1;\n\n tuple *res1 = func0(list1_1, size1_1, list2_1, size2_1, &res_size_1);\n\n tuple expected1[] = { {3,4}, {4,5}, {5,6} };\n\n int expected_size1 = 3;\n\n assert(res_size_1 == expected_size1);\n\n for(int i=0;i\nlea -0x1(%rsi),%edx\nmov %rdi,%rax\nlea 0x8(%rdi,%rdx,8),%rsi\nmov (%rax),%edx\nmov 0x4(%rax),%ecx\ncmp %ecx,%edx\njle 157e \nmov %ecx,(%rax)\nmov %edx,0x4(%rax)\nadd $0x8,%rax\ncmp %rsi,%rax\njne 1570 \ntest %r14d,%r14d\njle 1740 \nlea -0x1(%r14),%edx\nmov %rbp,%rax\nmov %rdx,%r15\nlea 0x8(%rbp,%rdx,8),%rsi\nmov (%rax),%edx\nmov 0x4(%rax),%ecx\ncmp %ecx,%edx\njle 15ae \nmov %ecx,(%rax)\nmov %edx,0x4(%rax)\nadd $0x8,%rax\ncmp %rsi,%rax\njne 15a0 \nmovslq %r13d,%rsi\nlea -0xa1(%rip),%rcx\nmov $0x8,%edx\nmov %r12,%rdi\ncallq 10a0 \nmovslq %r14d,%rsi\nmov $0x8,%edx\nmov %rbp,%rdi\nlea -0xc0(%rip),%rcx\ncallq 10a0 \ntest %r13d,%r13d\njle 1790 \nlea -0x1(%r13),%esi\nxor %eax,%eax\nxor %r13d,%r13d\njmp 1623 \nnopl 0x0(%rax)\nmov -0x8(%r12,%rax,8),%edi\ncmp %edi,(%r12,%rax,8)\njne 1628 \nmov -0x4(%r12,%rax,8),%edi\ncmp %edi,0x4(%r12,%rax,8)\njne 1628 \nlea 0x1(%rax),%rdx\ncmp %rsi,%rax\nje 1640 \nmov %rdx,%rax\ntest %rax,%rax\njne 1600 \nmov (%r12,%rax,8),%rcx\nmovslq %r13d,%rdx\nadd $0x1,%r13d\nmov %rcx,(%r12,%rdx,8)\nlea 0x1(%rax),%rdx\ncmp %rsi,%rax\njne 1620 \ntest %r14d,%r14d\njle 1780 \nlea -0x1(%r14),%r15d\nmov %r15d,%esi\nxor %eax,%eax\nxor %r14d,%r14d\njmp 1680 \nnopw 0x0(%rax,%rax,1)\nmov -0x8(%rbp,%rax,8),%edi\ncmp %edi,0x0(%rbp,%rax,8)\njne 1685 \nmov -0x4(%rbp,%rax,8),%edi\ncmp %edi,0x4(%rbp,%rax,8)\njne 1685 \nlea 0x1(%rax),%rdx\ncmp %rsi,%rax\nje 169f \nmov %rdx,%rax\ntest %rax,%rax\njne 1660 \nmov 0x0(%rbp,%rax,8),%rcx\nmovslq %r14d,%rdx\nadd $0x1,%r14d\nmov %rcx,0x0(%rbp,%rdx,8)\nlea 0x1(%rax),%rdx\ncmp %rsi,%rax\njne 167d \ncmp %r14d,%r13d\nmov %r14d,%edi\ncmovle %r13d,%edi\nmovslq %edi,%rdi\nshl $0x3,%rdi\ncallq 10d0 \ntest %r13d,%r13d\njle 1798 \ntest %r14d,%r14d\njle 1798 \nxor %ecx,%ecx\nxor %esi,%esi\nxor %r10d,%r10d\njmp 16e4 \nsub %r9d,%edx\ntest %edx,%edx\njs 1738 \nadd $0x1,%ecx\ncmp %esi,%r13d\njle 171f \ncmp %r14d,%ecx\njge 171f \nmovslq %ecx,%rdx\nlea 0x0(%rbp,%rdx,8),%r8\nmovslq %esi,%rdx\nlea (%r12,%rdx,8),%rdi\nmov (%r8),%r9d\nmov (%rdi),%edx\ncmp %r9d,%edx\njne 16d0 \nmov 0x4(%rdi),%edx\nsub 0x4(%r8),%edx\njne 16d3 \nmov (%rdi),%rdi\nmovslq %r10d,%rdx\nadd $0x1,%esi\nadd $0x1,%ecx\nadd $0x1,%r10d\nmov %rdi,(%rax,%rdx,8)\ncmp %esi,%r13d\njg 16df \nmov %r10d,(%rbx)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\nadd $0x1,%esi\njmp 16da \nnopl (%rax)\nmovslq %r13d,%rsi\nlea -0x22a(%rip),%rcx\nmov $0x8,%edx\nmov %r12,%rdi\ncallq 10a0 \nmovslq %r14d,%rsi\nmov $0x8,%edx\nmov %rbp,%rdi\nlea -0x249(%rip),%rcx\ncallq 10a0 \ntest %r13d,%r13d\njg 15ee \nnopw 0x0(%rax,%rax,1)\nxor %edi,%edi\ncallq 10d0 \nxor %r10d,%r10d\njmp 171f \nnopl 0x0(%rax)\nxor %r13d,%r13d\njmpq 164d \nxor %r10d,%r10d\njmp 171f \nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14d, esi\npush r13\nmov r13d, ecx\npush r12\nmov r12, rdx\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_48], r8\ntest esi, esi\njle loc_1748\nmovsxd r15, esi\nmov rax, rdi\nlea rsi, [rdi+r15*8]\nnop dword ptr [rax+00h]\nloc_1558:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd ecx, xmm0\nmovd edx, xmm1\ncmp ecx, edx\njle short loc_1576\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_1576:\nadd rax, 8\ncmp rax, rsi\njnz short loc_1558\nmovsxd rbx, r13d\ntest r13d, r13d\njle short loc_15BF\nloc_1587:\nmovsxd rbx, r13d\nmov rax, r12\nlea rsi, [r12+rbx*8]\nnop dword ptr [rax+00000000h]\nloc_1598:\nmovq xmm0, qword ptr [rax]\npshufd xmm2, xmm0, 0E5h\nmovd ecx, xmm0\nmovd edx, xmm2\ncmp ecx, edx\njle short loc_15B6\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_15B6:\nadd rax, 8\ncmp rsi, rax\njnz short loc_1598\nloc_15BF:\nlea rcx, tuple_compare; compar\nmov edx, 8; size\nmov rsi, r15; nmemb\nmov rdi, rbp; base\ncall _qsort\nmov edx, 8; size\nmov rsi, rbx; nmemb\nmov rdi, r12; base\nlea rcx, tuple_compare; compar\ncall _qsort\nxor eax, eax\nxor edx, edx\ntest r14d, r14d\njg short loc_161D\njmp short loc_163B\nloc_1600:\nmov edi, [rbp+rax*8-8]\ncmp [rbp+rax*8+0], edi\njnz short loc_1622\nmov edi, [rbp+rax*8-4]\ncmp [rbp+rax*8+4], edi\njnz short loc_1622\nadd rax, 1\ncmp r15, rax\njz short loc_163B\nloc_161D:\ntest rax, rax\njnz short loc_1600\nloc_1622:\nmov rsi, [rbp+rax*8+0]\nmovsxd rcx, edx\nadd rax, 1\nadd edx, 1\nmov [rbp+rcx*8+0], rsi\ncmp r15, rax\njnz short loc_161D\nloc_163B:\ntest r13d, r13d\njle loc_1788\nxor eax, eax\nxor r13d, r13d\njmp short loc_1670\nloc_1650:\nmov edi, [r12+rax*8-8]\ncmp [r12+rax*8], edi\njnz short loc_1675\nmov esi, [r12+rax*8-4]\ncmp [r12+rax*8+4], esi\njnz short loc_1675\nadd rax, 1\ncmp rbx, rax\njz short loc_168D\nloc_1670:\ntest rax, rax\njnz short loc_1650\nloc_1675:\nmov rsi, [r12+rax*8]\nmovsxd rcx, r13d\nadd rax, 1\nadd r13d, 1\nmov [r12+rcx*8], rsi\ncmp rbx, rax\njnz short loc_1670\nloc_168D:\ncmp r13d, edx\nmov edi, edx\nmov [rsp+48h+var_3C], edx\ncmovle edi, r13d\nmovsxd rdi, edi\nshl rdi, 3; size\ncall _malloc\nmov r11, rax\ntest r13d, r13d\njle loc_179E\nmov edx, [rsp+48h+var_3C]\ntest edx, edx\njle loc_179E\nxor ecx, ecx\nxor esi, esi\nxor r10d, r10d\njmp short loc_16E3\nloc_16D0:\nsub eax, r9d\nloc_16D3:\ntest eax, eax\njs short loc_1740\nadd ecx, 1\nloc_16DA:\ncmp esi, edx\njge short loc_171D\nloc_16DE:\ncmp ecx, r13d\njge short loc_171D\nloc_16E3:\nmovsxd rax, ecx\nlea r8, [r12+rax*8]\nmovsxd rax, esi\nlea rdi, [rbp+rax*8+0]\nmov r9d, [r8]\nmov eax, [rdi]\ncmp eax, r9d\njnz short loc_16D0\nmov eax, [rdi+4]\nsub eax, [r8+4]\njnz short loc_16D3\nmov rdi, [rdi]\nmovsxd rax, r10d\nadd esi, 1\nadd ecx, 1\nadd r10d, 1\nmov [r11+rax*8], rdi\ncmp esi, edx\njl short loc_16DE\nloc_171D:\nmov rax, [rsp+48h+var_48]\nmov [rax], r10d\nadd rsp, 18h\nmov rax, r11\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1740:\nadd esi, 1\njmp short loc_16DA\nloc_1748:\nmovsxd r15, esi\ntest ecx, ecx\njg loc_1587\nlea r14, tuple_compare\nmov edx, 8; size\nmov rsi, r15; nmemb\nmov rdi, rbp; base\nmov rcx, r14; compar\ncall _qsort\nmov edx, 8; size\nmovsxd rsi, r13d; nmemb\nmov rcx, r14; compar\nmov rdi, r12; base\ncall _qsort\nxor edx, edx\nnop word ptr [rax+rax+00h]\nloc_1788:\nxor edi, edi\ntest edx, edx\ncmovle edi, edx\nmovsxd rdi, edi\nshl rdi, 3; size\ncall _malloc\nmov r11, rax\nloc_179E:\nxor r10d, r10d\njmp loc_171D", + "ida_pseudo": "_QWORD *__fastcall func0(__m128i *base, int a2, __m128i *a3, int a4, _DWORD *a5)\n{\n size_t v9; // r15\n __m128i *v10; // rax\n __m128i *v11; // rsi\n __m128i v12; // xmm0\n size_t v13; // rbx\n __m128i *v14; // rax\n __m128i v15; // xmm0\n __int64 v16; // rax\n int v17; // edx\n __int64 v18; // rsi\n __int64 v19; // rcx\n __int64 v20; // rax\n int v21; // r13d\n __int64 v22; // rsi\n __int64 v23; // rcx\n int v24; // edi\n _QWORD *v25; // r11\n int v26; // ecx\n int v27; // esi\n int v28; // r10d\n int v29; // eax\n __int32 *v30; // r8\n char *v31; // rdi\n __int64 v32; // rax\n int v34; // edi\n int v36; // [rsp+Ch] [rbp-3Ch]\n\n if ( a2 <= 0 )\n {\n v9 = a2;\n if ( a4 <= 0 )\n {\n qsort(base, a2, 8uLL, tuple_compare);\n qsort(a3, a4, 8uLL, tuple_compare);\n v17 = 0;\nLABEL_42:\n v34 = 0;\n if ( v17 <= 0 )\n v34 = v17;\n v25 = malloc(8LL * v34);\n goto LABEL_45;\n }\n goto LABEL_7;\n }\n v9 = a2;\n v10 = base;\n v11 = (__m128i *)((char *)base + 8 * a2);\n do\n {\n v12 = _mm_loadl_epi64(v10);\n if ( _mm_cvtsi128_si32(v12) > _mm_cvtsi128_si32(_mm_shuffle_epi32(v12, 229)) )\n v10->m128i_i64[0] = _mm_shuffle_epi32(v12, 225).m128i_u64[0];\n v10 = (__m128i *)((char *)v10 + 8);\n }\n while ( v10 != v11 );\n v13 = a4;\n if ( a4 > 0 )\n {\nLABEL_7:\n v13 = a4;\n v14 = a3;\n do\n {\n v15 = _mm_loadl_epi64(v14);\n if ( _mm_cvtsi128_si32(v15) > _mm_cvtsi128_si32(_mm_shuffle_epi32(v15, 229)) )\n v14->m128i_i64[0] = _mm_shuffle_epi32(v15, 225).m128i_u64[0];\n v14 = (__m128i *)((char *)v14 + 8);\n }\n while ( (__m128i *)((char *)a3 + 8 * a4) != v14 );\n }\n qsort(base, v9, 8uLL, tuple_compare);\n qsort(a3, v13, 8uLL, tuple_compare);\n v16 = 0LL;\n v17 = 0;\n if ( a2 > 0 )\n {\n do\n {\n while ( v16\n && base->m128i_i32[2 * v16] == base->m128i_i32[2 * v16 - 2]\n && base->m128i_i32[2 * v16 + 1] == base->m128i_i32[2 * v16 - 1] )\n {\n if ( v9 == ++v16 )\n goto LABEL_18;\n }\n v18 = base->m128i_i64[v16];\n v19 = v17;\n ++v16;\n ++v17;\n base->m128i_i64[v19] = v18;\n }\n while ( v9 != v16 );\n }\nLABEL_18:\n if ( a4 <= 0 )\n goto LABEL_42;\n v20 = 0LL;\n v21 = 0;\n do\n {\n while ( v20\n && a3->m128i_i32[2 * v20] == a3->m128i_i32[2 * v20 - 2]\n && a3->m128i_i32[2 * v20 + 1] == a3->m128i_i32[2 * v20 - 1] )\n {\n if ( v13 == ++v20 )\n goto LABEL_25;\n }\n v22 = a3->m128i_i64[v20];\n v23 = v21;\n ++v20;\n ++v21;\n a3->m128i_i64[v23] = v22;\n }\n while ( v13 != v20 );\nLABEL_25:\n v24 = v17;\n v36 = v17;\n if ( v21 <= v17 )\n v24 = v21;\n v25 = malloc(8LL * v24);\n if ( v21 > 0 && v36 > 0 )\n {\n v26 = 0;\n v27 = 0;\n v28 = 0;\n while ( 1 )\n {\n v30 = &a3->m128i_i32[2 * v26];\n v31 = &base->m128i_i8[8 * v27];\n if ( *(_DWORD *)v31 == *v30 )\n {\n v29 = *((_DWORD *)v31 + 1) - v30[1];\n if ( !v29 )\n {\n v32 = v28;\n ++v27;\n ++v26;\n ++v28;\n v25[v32] = *(_QWORD *)v31;\n if ( v27 >= v36 )\n goto LABEL_38;\n goto LABEL_34;\n }\n }\n else\n {\n v29 = *(_DWORD *)v31 - *v30;\n }\n if ( v29 < 0 )\n ++v27;\n else\n ++v26;\n if ( v27 >= v36 )\n goto LABEL_38;\nLABEL_34:\n if ( v26 >= v21 )\n goto LABEL_38;\n }\n }\nLABEL_45:\n v28 = 0;\nLABEL_38:\n *a5 = v28;\n return v25;\n}", + "ida_strip_asm": "sub_1520:\nendbr64\npush r15\npush r14\nmov r14d, esi\npush r13\nmov r13d, ecx\npush r12\nmov r12, rdx\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_48], r8\ntest esi, esi\njle loc_1748\nmovsxd r15, esi\nmov rax, rdi\nlea rsi, [rdi+r15*8]\nnop dword ptr [rax+00h]\nloc_1558:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd ecx, xmm0\nmovd edx, xmm1\ncmp ecx, edx\njle short loc_1576\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_1576:\nadd rax, 8\ncmp rax, rsi\njnz short loc_1558\nmovsxd rbx, r13d\ntest r13d, r13d\njle short loc_15BF\nloc_1587:\nmovsxd rbx, r13d\nmov rax, r12\nlea rsi, [r12+rbx*8]\nnop dword ptr [rax+00000000h]\nloc_1598:\nmovq xmm0, qword ptr [rax]\npshufd xmm2, xmm0, 0E5h\nmovd ecx, xmm0\nmovd edx, xmm2\ncmp ecx, edx\njle short loc_15B6\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_15B6:\nadd rax, 8\ncmp rsi, rax\njnz short loc_1598\nloc_15BF:\nlea rcx, compar; compar\nmov edx, 8; size\nmov rsi, r15; nmemb\nmov rdi, rbp; base\ncall _qsort\nmov edx, 8; size\nmov rsi, rbx; nmemb\nmov rdi, r12; base\nlea rcx, compar; compar\ncall _qsort\nxor eax, eax\nxor edx, edx\ntest r14d, r14d\njg short loc_161D\njmp short loc_163B\nloc_1600:\nmov edi, [rbp+rax*8-8]\ncmp [rbp+rax*8+0], edi\njnz short loc_1622\nmov edi, [rbp+rax*8-4]\ncmp [rbp+rax*8+4], edi\njnz short loc_1622\nadd rax, 1\ncmp r15, rax\njz short loc_163B\nloc_161D:\ntest rax, rax\njnz short loc_1600\nloc_1622:\nmov rsi, [rbp+rax*8+0]\nmovsxd rcx, edx\nadd rax, 1\nadd edx, 1\nmov [rbp+rcx*8+0], rsi\ncmp r15, rax\njnz short loc_161D\nloc_163B:\ntest r13d, r13d\njle loc_1788\nxor eax, eax\nxor r13d, r13d\njmp short loc_1670\nloc_1650:\nmov edi, [r12+rax*8-8]\ncmp [r12+rax*8], edi\njnz short loc_1675\nmov esi, [r12+rax*8-4]\ncmp [r12+rax*8+4], esi\njnz short loc_1675\nadd rax, 1\ncmp rbx, rax\njz short loc_168D\nloc_1670:\ntest rax, rax\njnz short loc_1650\nloc_1675:\nmov rsi, [r12+rax*8]\nmovsxd rcx, r13d\nadd rax, 1\nadd r13d, 1\nmov [r12+rcx*8], rsi\ncmp rbx, rax\njnz short loc_1670\nloc_168D:\ncmp r13d, edx\nmov edi, edx\nmov [rsp+48h+var_3C], edx\ncmovle edi, r13d\nmovsxd rdi, edi\nshl rdi, 3; size\ncall _malloc\nmov r11, rax\ntest r13d, r13d\njle loc_179E\nmov edx, [rsp+48h+var_3C]\ntest edx, edx\njle loc_179E\nxor ecx, ecx\nxor esi, esi\nxor r10d, r10d\njmp short loc_16E3\nloc_16D0:\nsub eax, r9d\nloc_16D3:\ntest eax, eax\njs short loc_1740\nadd ecx, 1\nloc_16DA:\ncmp esi, edx\njge short loc_171D\nloc_16DE:\ncmp ecx, r13d\njge short loc_171D\nloc_16E3:\nmovsxd rax, ecx\nlea r8, [r12+rax*8]\nmovsxd rax, esi\nlea rdi, [rbp+rax*8+0]\nmov r9d, [r8]\nmov eax, [rdi]\ncmp eax, r9d\njnz short loc_16D0\nmov eax, [rdi+4]\nsub eax, [r8+4]\njnz short loc_16D3\nmov rdi, [rdi]\nmovsxd rax, r10d\nadd esi, 1\nadd ecx, 1\nadd r10d, 1\nmov [r11+rax*8], rdi\ncmp esi, edx\njl short loc_16DE\nloc_171D:\nmov rax, [rsp+48h+var_48]\nmov [rax], r10d\nadd rsp, 18h\nmov rax, r11\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1740:\nadd esi, 1\njmp short loc_16DA\nloc_1748:\nmovsxd r15, esi\ntest ecx, ecx\njg loc_1587\nlea r14, compar\nmov edx, 8; size\nmov rsi, r15; nmemb\nmov rdi, rbp; base\nmov rcx, r14; compar\ncall _qsort\nmov edx, 8; size\nmovsxd rsi, r13d; nmemb\nmov rcx, r14; compar\nmov rdi, r12; base\ncall _qsort\nxor edx, edx\nnop word ptr [rax+rax+00h]\nloc_1788:\nxor edi, edi\ntest edx, edx\ncmovle edi, edx\nmovsxd rdi, edi\nshl rdi, 3; size\ncall _malloc\nmov r11, rax\nloc_179E:\nxor r10d, r10d\njmp loc_171D", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1520(__m128i *base, int a2, __m128i *a3, int a4, _DWORD *a5)\n{\n size_t v9; // r15\n __m128i *v10; // rax\n __m128i *v11; // rsi\n __m128i v12; // xmm0\n size_t v13; // rbx\n __m128i *v14; // rax\n __m128i v15; // xmm0\n __int64 v16; // rax\n int v17; // edx\n __int64 v18; // rsi\n __int64 v19; // rcx\n __int64 v20; // rax\n int v21; // r13d\n __int64 v22; // rsi\n __int64 v23; // rcx\n int v24; // edi\n _QWORD *v25; // r11\n int v26; // ecx\n int v27; // esi\n int v28; // r10d\n int v29; // eax\n __int32 *v30; // r8\n char *v31; // rdi\n __int64 v32; // rax\n int v34; // edi\n int v36; // [rsp+Ch] [rbp-3Ch]\n\n if ( a2 <= 0 )\n {\n v9 = a2;\n if ( a4 <= 0 )\n {\n qsort(base, a2, 8uLL, compar);\n qsort(a3, a4, 8uLL, compar);\n v17 = 0;\nLABEL_42:\n v34 = 0;\n if ( v17 <= 0 )\n v34 = v17;\n v25 = malloc(8LL * v34);\n goto LABEL_45;\n }\n goto LABEL_7;\n }\n v9 = a2;\n v10 = base;\n v11 = (__m128i *)((char *)base + 8 * a2);\n do\n {\n v12 = _mm_loadl_epi64(v10);\n if ( _mm_cvtsi128_si32(v12) > _mm_cvtsi128_si32(_mm_shuffle_epi32(v12, 229)) )\n v10->m128i_i64[0] = _mm_shuffle_epi32(v12, 225).m128i_u64[0];\n v10 = (__m128i *)((char *)v10 + 8);\n }\n while ( v10 != v11 );\n v13 = a4;\n if ( a4 > 0 )\n {\nLABEL_7:\n v13 = a4;\n v14 = a3;\n do\n {\n v15 = _mm_loadl_epi64(v14);\n if ( _mm_cvtsi128_si32(v15) > _mm_cvtsi128_si32(_mm_shuffle_epi32(v15, 229)) )\n v14->m128i_i64[0] = _mm_shuffle_epi32(v15, 225).m128i_u64[0];\n v14 = (__m128i *)((char *)v14 + 8);\n }\n while ( (__m128i *)((char *)a3 + 8 * a4) != v14 );\n }\n qsort(base, v9, 8uLL, compar);\n qsort(a3, v13, 8uLL, compar);\n v16 = 0LL;\n v17 = 0;\n if ( a2 > 0 )\n {\n do\n {\n while ( v16\n && base->m128i_i32[2 * v16] == base->m128i_i32[2 * v16 - 2]\n && base->m128i_i32[2 * v16 + 1] == base->m128i_i32[2 * v16 - 1] )\n {\n if ( v9 == ++v16 )\n goto LABEL_18;\n }\n v18 = base->m128i_i64[v16];\n v19 = v17;\n ++v16;\n ++v17;\n base->m128i_i64[v19] = v18;\n }\n while ( v9 != v16 );\n }\nLABEL_18:\n if ( a4 <= 0 )\n goto LABEL_42;\n v20 = 0LL;\n v21 = 0;\n do\n {\n while ( v20\n && a3->m128i_i32[2 * v20] == a3->m128i_i32[2 * v20 - 2]\n && a3->m128i_i32[2 * v20 + 1] == a3->m128i_i32[2 * v20 - 1] )\n {\n if ( v13 == ++v20 )\n goto LABEL_25;\n }\n v22 = a3->m128i_i64[v20];\n v23 = v21;\n ++v20;\n ++v21;\n a3->m128i_i64[v23] = v22;\n }\n while ( v13 != v20 );\nLABEL_25:\n v24 = v17;\n v36 = v17;\n if ( v21 <= v17 )\n v24 = v21;\n v25 = malloc(8LL * v24);\n if ( v21 > 0 && v36 > 0 )\n {\n v26 = 0;\n v27 = 0;\n v28 = 0;\n while ( 1 )\n {\n v30 = &a3->m128i_i32[2 * v26];\n v31 = &base->m128i_i8[8 * v27];\n if ( *(_DWORD *)v31 == *v30 )\n {\n v29 = *((_DWORD *)v31 + 1) - v30[1];\n if ( !v29 )\n {\n v32 = v28;\n ++v27;\n ++v26;\n ++v28;\n v25[v32] = *(_QWORD *)v31;\n if ( v27 >= v36 )\n goto LABEL_38;\n goto LABEL_34;\n }\n }\n else\n {\n v29 = *(_DWORD *)v31 - *v30;\n }\n if ( v29 < 0 )\n ++v27;\n else\n ++v26;\n if ( v27 >= v36 )\n goto LABEL_38;\nLABEL_34:\n if ( v26 >= v21 )\n goto LABEL_38;\n }\n }\nLABEL_45:\n v28 = 0;\nLABEL_38:\n *a5 = v28;\n return v25;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1520(__m128i *base, int a2, __m128i *a3, int a4, uint32_t *a5) {\n unsigned int v9;\n __m128i *v10;\n __m128i *v11;\n __m128i v12;\n unsigned int v13;\n __m128i *v14;\n __m128i v15;\n long long v16;\n int v17;\n long long v18;\n long long v19;\n long long v20;\n int v21;\n long long v22;\n long long v23;\n int v24;\n uint64_t *v25;\n int v26;\n int v27;\n int v28;\n int v29;\n int *v30;\n char *v31;\n long long v32;\n int v34;\n int v36;\n if (a2 <= 0) {\n v9 = a2;\n if (a4 <= 0) {\n qsort(base, a2, 8uLL, compar);\n qsort(a3, a4, 8uLL, compar);\n v17 = 0;\n LABEL_42:\n v34 = 0;\n if (v17 <= 0) v34 = v17;\n v25 = malloc(8LL * v34);\n goto LABEL_45;\n }\n goto LABEL_7;\n }\n v9 = a2;\n v10 = base;\n v11 = (__m128i *)((char *)base + 8 * a2);\n do {\n v12 = _mm_loadl_epi64(v10);\n if (_mm_cvtsi128_si32(v12) > _mm_cvtsi128_si32(_mm_shuffle_epi32(v12, 229)))\n v10->m128i_i64[0] = _mm_shuffle_epi32(v12, 225).m128i_u64[0];\n v10 = (__m128i *)((char *)v10 + 8);\n } while (v10 != v11);\n v13 = a4;\n if (a4 > 0) {\n LABEL_7:\n v13 = a4;\n v14 = a3;\n do {\n v15 = _mm_loadl_epi64(v14);\n if (_mm_cvtsi128_si32(v15) >\n _mm_cvtsi128_si32(_mm_shuffle_epi32(v15, 229)))\n v14->m128i_i64[0] = _mm_shuffle_epi32(v15, 225).m128i_u64[0];\n v14 = (__m128i *)((char *)v14 + 8);\n } while ((__m128i *)((char *)a3 + 8 * a4) != v14);\n }\n qsort(base, v9, 8uLL, compar);\n qsort(a3, v13, 8uLL, compar);\n v16 = 0LL;\n v17 = 0;\n if (a2 > 0) {\n do {\n while (v16 && base->m128i_i32[2 * v16] == base->m128i_i32[2 * v16 - 2] &&\n base->m128i_i32[2 * v16 + 1] == base->m128i_i32[2 * v16 - 1]) {\n if (v9 == ++v16) goto LABEL_18;\n }\n v18 = base->m128i_i64[v16];\n v19 = v17;\n ++v16;\n ++v17;\n base->m128i_i64[v19] = v18;\n } while (v9 != v16);\n }\nLABEL_18:\n if (a4 <= 0) goto LABEL_42;\n v20 = 0LL;\n v21 = 0;\n do {\n while (v20 && a3->m128i_i32[2 * v20] == a3->m128i_i32[2 * v20 - 2] &&\n a3->m128i_i32[2 * v20 + 1] == a3->m128i_i32[2 * v20 - 1]) {\n if (v13 == ++v20) goto LABEL_25;\n }\n v22 = a3->m128i_i64[v20];\n v23 = v21;\n ++v20;\n ++v21;\n a3->m128i_i64[v23] = v22;\n } while (v13 != v20);\nLABEL_25:\n v24 = v17;\n v36 = v17;\n if (v21 <= v17) v24 = v21;\n v25 = malloc(8LL * v24);\n if (v21 > 0 && v36 > 0) {\n v26 = 0;\n v27 = 0;\n v28 = 0;\n while (1) {\n v30 = &a3->m128i_i32[2 * v26];\n v31 = &base->m128i_i8[8 * v27];\n if (*(uint32_t *)v31 == *v30) {\n v29 = *((uint32_t *)v31 + 1) - v30[1];\n if (!v29) {\n v32 = v28;\n ++v27;\n ++v26;\n ++v28;\n v25[v32] = *(uint64_t *)v31;\n if (v27 >= v36) goto LABEL_38;\n goto LABEL_34;\n }\n } else {\n v29 = *(uint32_t *)v31 - *v30;\n }\n if (v29 < 0)\n ++v27;\n else\n ++v26;\n if (v27 >= v36) goto LABEL_38;\n LABEL_34:\n if (v26 >= v21) goto LABEL_38;\n }\n }\nLABEL_45:\n v28 = 0;\nLABEL_38:\n *a5 = v28;\n return v25;\n}", + "ida_pseudo_norm": "uint64_t *func0(__m128i *base, int a2, __m128i *a3, int a4, uint32_t *a5) {\n unsigned int v9;\n __m128i *v10;\n __m128i *v11;\n __m128i v12;\n unsigned int v13;\n __m128i *v14;\n __m128i v15;\n long long v16;\n int v17;\n long long v18;\n long long v19;\n long long v20;\n int v21;\n long long v22;\n long long v23;\n int v24;\n uint64_t *v25;\n int v26;\n int v27;\n int v28;\n int v29;\n int *v30;\n char *v31;\n long long v32;\n int v34;\n int v36;\n if (a2 <= 0) {\n v9 = a2;\n if (a4 <= 0) {\n qsort(base, a2, 8uLL, tuple_compare);\n qsort(a3, a4, 8uLL, tuple_compare);\n v17 = 0;\n LABEL_42:\n v34 = 0;\n if (v17 <= 0) v34 = v17;\n v25 = malloc(8LL * v34);\n goto LABEL_45;\n }\n goto LABEL_7;\n }\n v9 = a2;\n v10 = base;\n v11 = (__m128i *)((char *)base + 8 * a2);\n do {\n v12 = _mm_loadl_epi64(v10);\n if (_mm_cvtsi128_si32(v12) > _mm_cvtsi128_si32(_mm_shuffle_epi32(v12, 229)))\n v10->m128i_i64[0] = _mm_shuffle_epi32(v12, 225).m128i_u64[0];\n v10 = (__m128i *)((char *)v10 + 8);\n } while (v10 != v11);\n v13 = a4;\n if (a4 > 0) {\n LABEL_7:\n v13 = a4;\n v14 = a3;\n do {\n v15 = _mm_loadl_epi64(v14);\n if (_mm_cvtsi128_si32(v15) >\n _mm_cvtsi128_si32(_mm_shuffle_epi32(v15, 229)))\n v14->m128i_i64[0] = _mm_shuffle_epi32(v15, 225).m128i_u64[0];\n v14 = (__m128i *)((char *)v14 + 8);\n } while ((__m128i *)((char *)a3 + 8 * a4) != v14);\n }\n qsort(base, v9, 8uLL, tuple_compare);\n qsort(a3, v13, 8uLL, tuple_compare);\n v16 = 0LL;\n v17 = 0;\n if (a2 > 0) {\n do {\n while (v16 && base->m128i_i32[2 * v16] == base->m128i_i32[2 * v16 - 2] &&\n base->m128i_i32[2 * v16 + 1] == base->m128i_i32[2 * v16 - 1]) {\n if (v9 == ++v16) goto LABEL_18;\n }\n v18 = base->m128i_i64[v16];\n v19 = v17;\n ++v16;\n ++v17;\n base->m128i_i64[v19] = v18;\n } while (v9 != v16);\n }\nLABEL_18:\n if (a4 <= 0) goto LABEL_42;\n v20 = 0LL;\n v21 = 0;\n do {\n while (v20 && a3->m128i_i32[2 * v20] == a3->m128i_i32[2 * v20 - 2] &&\n a3->m128i_i32[2 * v20 + 1] == a3->m128i_i32[2 * v20 - 1]) {\n if (v13 == ++v20) goto LABEL_25;\n }\n v22 = a3->m128i_i64[v20];\n v23 = v21;\n ++v20;\n ++v21;\n a3->m128i_i64[v23] = v22;\n } while (v13 != v20);\nLABEL_25:\n v24 = v17;\n v36 = v17;\n if (v21 <= v17) v24 = v21;\n v25 = malloc(8LL * v24);\n if (v21 > 0 && v36 > 0) {\n v26 = 0;\n v27 = 0;\n v28 = 0;\n while (1) {\n v30 = &a3->m128i_i32[2 * v26];\n v31 = &base->m128i_i8[8 * v27];\n if (*(uint32_t *)v31 == *v30) {\n v29 = *((uint32_t *)v31 + 1) - v30[1];\n if (!v29) {\n v32 = v28;\n ++v27;\n ++v26;\n ++v28;\n v25[v32] = *(uint64_t *)v31;\n if (v27 >= v36) goto LABEL_38;\n goto LABEL_34;\n }\n } else {\n v29 = *(uint32_t *)v31 - *v30;\n }\n if (v29 < 0)\n ++v27;\n else\n ++v26;\n if (v27 >= v36) goto LABEL_38;\n LABEL_34:\n if (v26 >= v21) goto LABEL_38;\n }\n }\nLABEL_45:\n v28 = 0;\nLABEL_38:\n *a5 = v28;\n return v25;\n}" + }, + { + "index": 474, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* str1, char ch, char newch) {\n static char str2[100];\n strcpy(str2, str1);\n for (int i = 0; i < strlen(str2); i++) {\n if (str2[i] == ch) {\n str2[i] = newch;\n }\n }\n return str2;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"polygon\", 'y', 'l'), \"pollgon\") == 0);\n\n assert(strcmp(func0(\"character\", 'c', 'a'), \"aharaater\") == 0);\n\n assert(strcmp(func0(\"python\", 'l', 'a'), \"python\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x28,%rsp\nmov %rdi,-0x28(%rbp)\nmov %esi,%ecx\nmov %edx,%eax\nmov %ecx,%edx\nmov %dl,-0x2c(%rbp)\nmov %al,-0x30(%rbp)\nmov -0x28(%rbp),%rax\nmov %rax,%rsi\nlea 0x2e6c(%rip),%rdi\ncallq 1080 \nmovl $0x0,-0x14(%rbp)\njmp 120e \nmov -0x14(%rbp),%eax\ncltq\nlea 0x2e52(%rip),%rdx\nmovzbl (%rax,%rdx,1),%eax\ncmp %al,-0x2c(%rbp)\njne 120a \nmov -0x14(%rbp),%eax\ncltq\nlea 0x2e3d(%rip),%rcx\nmovzbl -0x30(%rbp),%edx\nmov %dl,(%rax,%rcx,1)\naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\nmovslq %eax,%rbx\nlea 0x2e25(%rip),%rdi\ncallq 1090 \ncmp %rax,%rbx\njb 11e2 \nlea 0x2e14(%rip),%rax\nadd $0x28,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+src], rdi\nmov ecx, esi\nmov eax, edx\nmov edx, ecx\nmov [rbp+var_2C], dl\nmov [rbp+var_30], al\nmov rax, [rbp+src]\nmov rsi, rax; src\nlea rax, str2_1\nmov rdi, rax; dest\ncall _strcpy\nmov [rbp+var_14], 0\njmp short loc_1211\nloc_11E5:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, str2_1\nmovzx eax, byte ptr [rax+rdx]\ncmp [rbp+var_2C], al\njnz short loc_120D\nmov eax, [rbp+var_14]\ncdqe\nlea rcx, str2_1\nmovzx edx, [rbp+var_30]\nmov [rax+rcx], dl\nloc_120D:\nadd [rbp+var_14], 1\nloc_1211:\nmov eax, [rbp+var_14]\nmovsxd rbx, eax\nlea rax, str2_1\nmov rdi, rax; s\ncall _strlen\ncmp rbx, rax\njb short loc_11E5\nlea rax, str2_1\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(const char *a1, char a2, char a3)\n{\n int i; // [rsp+1Ch] [rbp-14h]\n\n strcpy(str2_1, a1);\n for ( i = 0; i < strlen(str2_1); ++i )\n {\n if ( a2 == str2_1[i] )\n str2_1[i] = a3;\n }\n return str2_1;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+src], rdi\nmov ecx, esi\nmov eax, edx\nmov edx, ecx\nmov [rbp+var_2C], dl\nmov [rbp+var_30], al\nmov rax, [rbp+src]\nmov rsi, rax; src\nlea rax, s\nmov rdi, rax; dest\ncall _strcpy\nmov [rbp+var_14], 0\njmp short loc_1211\nloc_11E5:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, s\nmovzx eax, byte ptr [rax+rdx]\ncmp [rbp+var_2C], al\njnz short loc_120D\nmov eax, [rbp+var_14]\ncdqe\nlea rcx, s\nmovzx edx, [rbp+var_30]\nmov [rax+rcx], dl\nloc_120D:\nadd [rbp+var_14], 1\nloc_1211:\nmov eax, [rbp+var_14]\nmovsxd rbx, eax\nlea rax, s\nmov rdi, rax; s\ncall _strlen\ncmp rbx, rax\njb short loc_11E5\nlea rax, s\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11A9(const char *a1, char a2, char a3)\n{\n int i; // [rsp+1Ch] [rbp-14h]\n\n strcpy(s, a1);\n for ( i = 0; i < strlen(s); ++i )\n {\n if ( a2 == s[i] )\n s[i] = a3;\n }\n return s;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11A9(const char *a1, char a2, char a3) {\n int i;\n strcpy(s, a1);\n for (i = 0; i < strlen(s); ++i) {\n if (a2 == s[i]) s[i] = a3;\n }\n return s;\n}", + "ida_pseudo_norm": "char *func0(const char *a1, char a2, char a3) {\n int i;\n strcpy(str2_1, a1);\n for (i = 0; i < strlen(str2_1); ++i) {\n if (a2 == str2_1[i]) str2_1[i] = a3;\n }\n return str2_1;\n}" + }, + { + "index": 474, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* str1, char ch, char newch) {\n static char str2[100];\n strcpy(str2, str1);\n for (int i = 0; i < strlen(str2); i++) {\n if (str2[i] == ch) {\n str2[i] = newch;\n }\n }\n return str2;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"polygon\", 'y', 'l'), \"pollgon\") == 0);\n\n assert(strcmp(func0(\"character\", 'c', 'a'), \"aharaater\") == 0);\n\n assert(strcmp(func0(\"python\", 'l', 'a'), \"python\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %esi,%ebx\nmov %edx,%ebp\nmov $0x64,%edx\nmov %rdi,%rsi\nlea 0x2eba(%rip),%rdi\ncallq 1070 <__strcpy_chk@plt>\nmov $0x0,%edx\nlea 0x2ea9(%rip),%rsi\nmov $0xffffffffffffffff,%r8\nmov $0x0,%eax\njmp 11a9 \nadd $0x1,%rdx\nmov %r8,%rcx\nmov %rsi,%rdi\nrepnz scas %es:(%rdi),%al\nnot %rcx\nsub $0x1,%rcx\ncmp %rdx,%rcx\njbe 11c8 \ncmp %bl,(%rsi,%rdx,1)\njne 11a5 \nmov %bpl,(%rsi,%rdx,1)\njmp 11a5 \nlea 0x2e71(%rip),%rax\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12d, esi\nmov r13d, edx\nmov edx, 64h ; 'd'\nmov rsi, rdi\nlea rdi, str2_1\ncall ___strcpy_chk\nmov ebx, 0\nlea rbp, str2_1\njmp short loc_11E3\nloc_11DF:\nadd rbx, 1\nloc_11E3:\nmov rdi, rbp; s\ncall _strlen\ncmp rbx, rax\njnb short loc_11FE\ncmp [rbp+rbx+0], r12b\njnz short loc_11DF\nmov [rbp+rbx+0], r13b\njmp short loc_11DF\nloc_11FE:\nlea rax, str2_1\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, char a2, char a3)\n{\n size_t i; // rbx\n\n __strcpy_chk(str2_1, a1, 100LL);\n for ( i = 0LL; i < strlen(str2_1); ++i )\n {\n if ( str2_1[i] == a2 )\n str2_1[i] = a3;\n }\n return str2_1;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12d, esi\nmov r13d, edx\nmov edx, 64h ; 'd'\nmov rsi, rdi\nlea rdi, s\ncall ___strcpy_chk\nmov ebx, 0\nlea rbp, s\njmp short loc_11E3\nloc_11DF:\nadd rbx, 1\nloc_11E3:\nmov rdi, rbp; s\ncall _strlen\ncmp rbx, rax\njnb short loc_11FE\ncmp [rbp+rbx+0], r12b\njnz short loc_11DF\nmov [rbp+rbx+0], r13b\njmp short loc_11DF\nloc_11FE:\nlea rax, s\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11A9(__int64 a1, char a2, char a3)\n{\n size_t i; // rbx\n\n __strcpy_chk(s, a1, 100LL);\n for ( i = 0LL; i < strlen(s); ++i )\n {\n if ( s[i] == a2 )\n s[i] = a3;\n }\n return s;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char* sub_11A9(long long a1, char a2, char a3) {\n unsigned int i;\n __strcpy_chk(s, a1, 100LL);\n for (i = 0LL; i < strlen(s); ++i) {\n if (s[i] == a2) s[i] = a3;\n }\n return s;\n}", + "ida_pseudo_norm": "char* func0(long long a1, char a2, char a3) {\n unsigned int i;\n __strcpy_chk(str2_1, a1, 100LL);\n for (i = 0LL; i < strlen(str2_1); ++i) {\n if (str2_1[i] == a2) str2_1[i] = a3;\n }\n return str2_1;\n}" + }, + { + "index": 474, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* str1, char ch, char newch) {\n static char str2[100];\n strcpy(str2, str1);\n for (int i = 0; i < strlen(str2); i++) {\n if (str2[i] == ch) {\n str2[i] = newch;\n }\n }\n return str2;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"polygon\", 'y', 'l'), \"pollgon\") == 0);\n\n assert(strcmp(func0(\"character\", 'c', 'a'), \"aharaater\") == 0);\n\n assert(strcmp(func0(\"python\", 'l', 'a'), \"python\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %edx,%ebp\nmov $0x64,%edx\npush %rbx\nmov %esi,%ebx\nmov %rdi,%rsi\nlea 0x2db7(%rip),%rdi\nsub $0x8,%rsp\ncallq 1070 <__stpcpy_chk@plt>\nlea 0x2da7(%rip),%rdi\nxor %esi,%esi\nsub %rdi,%rax\nmov %rdi,%r8\njmp 12ac \nnopl 0x0(%rax,%rax,1)\nadd $0x1,%rsi\ncmp %rax,%rsi\njae 1300 \ncmp %bl,(%rdi,%rsi,1)\njne 12a8 \nmov %bpl,(%rdi,%rsi,1)\nlea 0x2d7f(%rip),%rax\nmov %r8,%rdi\nmov (%rax),%ecx\nadd $0x4,%rax\nlea -0x1010101(%rcx),%edx\nnot %ecx\nand %ecx,%edx\nand $0x80808080,%edx\nje 12c4 \nmov %edx,%ecx\nshr $0x10,%ecx\ntest $0x8080,%edx\ncmove %ecx,%edx\nlea 0x2(%rax),%rcx\ncmove %rcx,%rax\nmov %edx,%ecx\nadd %dl,%cl\nsbb $0x3,%rax\nsub %r8,%rax\njmp 12a8 \nadd $0x8,%rsp\nlea 0x2d35(%rip),%rax\npop %rbx\npop %rbp\nretq\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r13\nmov r13d, edx\nmov edx, 64h ; 'd'\npush r12\nmov r12d, esi\nmov rsi, rdi\npush rbp\nlea rbp, str2_1\npush rbx\nmov rdi, rbp\nxor ebx, ebx\nsub rsp, 8\ncall ___strcpy_chk\njmp short loc_12D0\nloc_12C0:\ncmp [rbp+rbx+0], r12b\njnz short loc_12CC\nmov [rbp+rbx+0], r13b\nloc_12CC:\nadd rbx, 1\nloc_12D0:\nmov rdi, rbp; s\ncall _strlen\ncmp rbx, rax\njb short loc_12C0\nadd rsp, 8\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, char a2, char a3)\n{\n size_t v4; // rbx\n\n v4 = 0LL;\n __strcpy_chk(str2_1, a1, 100LL);\n while ( v4 < strlen(str2_1) )\n {\n if ( str2_1[v4] == a2 )\n str2_1[v4] = a3;\n ++v4;\n }\n return str2_1;\n}", + "ida_strip_asm": "sub_1290:\nendbr64\npush r13\nmov r13d, edx\nmov edx, 64h ; 'd'\npush r12\nmov r12d, esi\nmov rsi, rdi\npush rbp\nlea rbp, s\npush rbx\nmov rdi, rbp\nxor ebx, ebx\nsub rsp, 8\ncall ___strcpy_chk\njmp short loc_12D0\nloc_12C0:\ncmp [rbp+rbx+0], r12b\njnz short loc_12CC\nmov [rbp+rbx+0], r13b\nloc_12CC:\nadd rbx, 1\nloc_12D0:\nmov rdi, rbp; s\ncall _strlen\ncmp rbx, rax\njb short loc_12C0\nadd rsp, 8\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1290(__int64 a1, char a2, char a3)\n{\n size_t v4; // rbx\n\n v4 = 0LL;\n __strcpy_chk(s, a1, 100LL);\n while ( v4 < strlen(s) )\n {\n if ( s[v4] == a2 )\n s[v4] = a3;\n ++v4;\n }\n return s;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char* sub_1290(long long a1, char a2, char a3) {\n unsigned int v4;\n v4 = 0LL;\n __strcpy_chk(s, a1, 100LL);\n while (v4 < strlen(s)) {\n if (s[v4] == a2) s[v4] = a3;\n ++v4;\n }\n return s;\n}", + "ida_pseudo_norm": "char* func0(long long a1, char a2, char a3) {\n unsigned int v4;\n v4 = 0LL;\n __strcpy_chk(str2_1, a1, 100LL);\n while (v4 < strlen(str2_1)) {\n if (str2_1[v4] == a2) str2_1[v4] = a3;\n ++v4;\n }\n return str2_1;\n}" + }, + { + "index": 474, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* str1, char ch, char newch) {\n static char str2[100];\n strcpy(str2, str1);\n for (int i = 0; i < strlen(str2); i++) {\n if (str2[i] == ch) {\n str2[i] = newch;\n }\n }\n return str2;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"polygon\", 'y', 'l'), \"pollgon\") == 0);\n\n assert(strcmp(func0(\"character\", 'c', 'a'), \"aharaater\") == 0);\n\n assert(strcmp(func0(\"python\", 'l', 'a'), \"python\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %edx,%ebp\nmov $0x64,%edx\npush %rbx\nmov %esi,%ebx\nmov %rdi,%rsi\nlea 0x2db7(%rip),%rdi\nsub $0x8,%rsp\ncallq 1070 <__stpcpy_chk@plt>\nlea 0x2da7(%rip),%rdi\nsub %rdi,%rax\nje 12b6 \nxor %esi,%esi\nmov %rdi,%r8\nnopl 0x0(%rax,%rax,1)\ncmp %bl,(%rdi,%rsi,1)\nje 12c8 \nadd $0x1,%rsi\ncmp %rax,%rsi\njb 12a8 \nadd $0x8,%rsp\nlea 0x2d7f(%rip),%rax\npop %rbx\npop %rbp\nretq\nnopl 0x0(%rax)\nmov %bpl,(%rdi,%rsi,1)\nlea 0x2d6d(%rip),%rax\nmov %r8,%rdi\nmov (%rax),%ecx\nadd $0x4,%rax\nlea -0x1010101(%rcx),%edx\nnot %ecx\nand %ecx,%edx\nand $0x80808080,%edx\nje 12d6 \nmov %edx,%ecx\nshr $0x10,%ecx\ntest $0x8080,%edx\ncmove %ecx,%edx\nlea 0x2(%rax),%rcx\ncmove %rcx,%rax\nmov %edx,%ecx\nadd %dl,%cl\nsbb $0x3,%rax\nadd $0x1,%rsi\nsub %r8,%rax\ncmp %rax,%rsi\njb 12a8 \nadd $0x8,%rsp\nlea 0x2d1d(%rip),%rax\npop %rbx\npop %rbp\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r13\nmov r13d, edx\nmov edx, 64h ; 'd'\npush r12\nmov r12d, esi\nmov rsi, rdi\npush rbp\nlea rbp, str2_1\npush rbx\nmov rdi, rbp\nxor ebx, ebx\nsub rsp, 8\ncall ___strcpy_chk\njmp short loc_12D0\nloc_12C0:\ncmp [rbp+rbx+0], r12b\njnz short loc_12CC\nmov [rbp+rbx+0], r13b\nloc_12CC:\nadd rbx, 1\nloc_12D0:\nmov rdi, rbp; s\ncall _strlen\ncmp rbx, rax\njb short loc_12C0\nadd rsp, 8\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, char a2, char a3)\n{\n size_t v4; // rbx\n\n v4 = 0LL;\n __strcpy_chk(str2_1, a1, 100LL);\n while ( v4 < strlen(str2_1) )\n {\n if ( str2_1[v4] == a2 )\n str2_1[v4] = a3;\n ++v4;\n }\n return str2_1;\n}", + "ida_strip_asm": "sub_1290:\nendbr64\npush r13\nmov r13d, edx\nmov edx, 64h ; 'd'\npush r12\nmov r12d, esi\nmov rsi, rdi\npush rbp\nlea rbp, s\npush rbx\nmov rdi, rbp\nxor ebx, ebx\nsub rsp, 8\ncall ___strcpy_chk\njmp short loc_12D0\nloc_12C0:\ncmp [rbp+rbx+0], r12b\njnz short loc_12CC\nmov [rbp+rbx+0], r13b\nloc_12CC:\nadd rbx, 1\nloc_12D0:\nmov rdi, rbp; s\ncall _strlen\ncmp rbx, rax\njb short loc_12C0\nadd rsp, 8\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1290(__int64 a1, char a2, char a3)\n{\n size_t v4; // rbx\n\n v4 = 0LL;\n __strcpy_chk(s, a1, 100LL);\n while ( v4 < strlen(s) )\n {\n if ( s[v4] == a2 )\n s[v4] = a3;\n ++v4;\n }\n return s;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char* sub_1290(long long a1, char a2, char a3) {\n unsigned int v4;\n v4 = 0LL;\n __strcpy_chk(s, a1, 100LL);\n while (v4 < strlen(s)) {\n if (s[v4] == a2) s[v4] = a3;\n ++v4;\n }\n return s;\n}", + "ida_pseudo_norm": "char* func0(long long a1, char a2, char a3) {\n unsigned int v4;\n v4 = 0LL;\n __strcpy_chk(str2_1, a1, 100LL);\n while (v4 < strlen(str2_1)) {\n if (str2_1[v4] == a2) str2_1[v4] = a3;\n ++v4;\n }\n return str2_1;\n}" + }, + { + "index": 475, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char key[50];\n\n int value;\n\n} Item;\n\n\n\nint cmp(const void *a, const void *b) {\n\n Item *itemA = (Item *)a;\n\n Item *itemB = (Item *)b;\n\n return (itemB->value - itemA->value);\n\n}\n\n\n\n", + "func": "Item* func0(char keys[][50], int values[], int length) {\n Item* items = malloc(length * sizeof(Item));\n for (int i = 0; i < length; i++) {\n strcpy(items[i].key, keys[i]);\n items[i].value = values[i];\n }\n qsort(items, length, sizeof(Item), cmp);\n return items;\n}", + "test": "int main() {\n\n char keys1[][50] = {\"Math\", \"Physics\", \"Chemistry\"};\n\n int values1[] = {81, 83, 87};\n\n Item *result1 = func0(keys1, values1, 3);\n\n assert(strcmp(result1[0].key, \"Chemistry\") == 0 && result1[0].value == 87);\n\n assert(strcmp(result1[1].key, \"Physics\") == 0 && result1[1].value == 83);\n\n assert(strcmp(result1[2].key, \"Math\") == 0 && result1[2].value == 81);\n\n free(result1);\n\n\n\n char keys2[][50] = {\"Math\", \"Physics\", \"Chemistry\"};\n\n int values2[] = {400, 300, 250};\n\n Item *result2 = func0(keys2, values2, 3);\n\n assert(strcmp(result2[0].key, \"Math\") == 0 && result2[0].value == 400);\n\n assert(strcmp(result2[1].key, \"Physics\") == 0 && result2[1].value == 300);\n\n assert(strcmp(result2[2].key, \"Chemistry\") == 0 && result2[2].value == 250);\n\n free(result2);\n\n\n\n char keys3[][50] = {\"Math\", \"Physics\", \"Chemistry\"};\n\n int values3[] = {900, 1000, 1250};\n\n Item *result3 = func0(keys3, values3, 3);\n\n assert(strcmp(result3[0].key, \"Chemistry\") == 0 && result3[0].value == 1250);\n\n assert(strcmp(result3[1].key, \"Physics\") == 0 && result3[1].value == 1000);\n\n assert(strcmp(result3[2].key, \"Math\") == 0 && result3[2].value == 900);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %edx,-0x24(%rbp)\nmov -0x24(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x3,%rax\nsub %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 1110 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0xc(%rbp)\njmpq 130e \nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nadd %rax,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x3,%rax\nsub %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 10c0 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x20(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x3,%rax\nsub %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,0x34(%rdx)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x24(%rbp),%eax\njl 1280 \nmov -0x24(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x8(%rbp),%rax\nlea -0x122(%rip),%rcx\nmov $0x38,%edx\nmov %rax,%rdi\ncallq 10d0 \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+base], rax\nmov [rbp+var_C], 0\njmp loc_130E\nloc_1280:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nadd rax, rax\nmov rdx, rax\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+base]\nadd rax, rdx\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strcpy\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+base]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx+34h], eax\nadd [rbp+var_C], 1\nloc_130E:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_24]\njl loc_1280\nmov eax, [rbp+var_24]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, cmp\nmov rcx, rdx; compar\nmov edx, 38h ; '8'; size\nmov rdi, rax; base\ncall _qsort\nmov rax, [rbp+base]\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n int i; // [rsp+24h] [rbp-Ch]\n char *base; // [rsp+28h] [rbp-8h]\n\n base = (char *)malloc(56LL * a3);\n for ( i = 0; i < a3; ++i )\n {\n strcpy(&base[56 * i], (const char *)(50LL * i + a1));\n *(_DWORD *)&base[56 * i + 52] = *(_DWORD *)(4LL * i + a2);\n }\n qsort(base, a3, 0x38uLL, cmp);\n return base;\n}", + "ida_strip_asm": "sub_123D:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+base], rax\nmov [rbp+var_C], 0\njmp loc_130E\nloc_1280:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nadd rax, rax\nmov rdx, rax\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+base]\nadd rax, rdx\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strcpy\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nsub rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+base]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx+34h], eax\nadd [rbp+var_C], 1\nloc_130E:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_24]\njl loc_1280\nmov eax, [rbp+var_24]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 38h ; '8'; size\nmov rdi, rax; base\ncall _qsort\nmov rax, [rbp+base]\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_123D(__int64 a1, __int64 a2, int a3)\n{\n int i; // [rsp+24h] [rbp-Ch]\n char *base; // [rsp+28h] [rbp-8h]\n\n base = (char *)malloc(56LL * a3);\n for ( i = 0; i < a3; ++i )\n {\n strcpy(&base[56 * i], (const char *)(50LL * i + a1));\n *(_DWORD *)&base[56 * i + 52] = *(_DWORD *)(4LL * i + a2);\n }\n qsort(base, a3, 0x38uLL, compar);\n return base;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_123D(long long a1, long long a2, int a3) {\n int i;\n char *base;\n base = (char *)malloc(56LL * a3);\n for (i = 0; i < a3; ++i) {\n strcpy(&base[56 * i], (const char *)(50LL * i + a1));\n *(uint32_t *)&base[56 * i + 52] = *(uint32_t *)(4LL * i + a2);\n }\n qsort(base, a3, 56uLL, compar);\n return base;\n}", + "ida_pseudo_norm": "char *func0(long long a1, long long a2, int a3) {\n int i;\n char *base;\n base = (char *)malloc(56LL * a3);\n for (i = 0; i < a3; ++i) {\n strcpy(&base[56 * i], (const char *)(50LL * i + a1));\n *(uint32_t *)&base[56 * i + 52] = *(uint32_t *)(4LL * i + a2);\n }\n qsort(base, a3, 56uLL, cmp);\n return base;\n}" + }, + { + "index": 475, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char key[50];\n\n int value;\n\n} Item;\n\n\n\nint cmp(const void *a, const void *b) {\n\n Item *itemA = (Item *)a;\n\n Item *itemB = (Item *)b;\n\n return (itemB->value - itemA->value);\n\n}\n\n\n\n", + "func": "Item* func0(char keys[][50], int values[], int length) {\n Item* items = malloc(length * sizeof(Item));\n for (int i = 0; i < length; i++) {\n strcpy(items[i].key, keys[i]);\n items[i].value = values[i];\n }\n qsort(items, length, sizeof(Item), cmp);\n return items;\n}", + "test": "int main() {\n\n char keys1[][50] = {\"Math\", \"Physics\", \"Chemistry\"};\n\n int values1[] = {81, 83, 87};\n\n Item *result1 = func0(keys1, values1, 3);\n\n assert(strcmp(result1[0].key, \"Chemistry\") == 0 && result1[0].value == 87);\n\n assert(strcmp(result1[1].key, \"Physics\") == 0 && result1[1].value == 83);\n\n assert(strcmp(result1[2].key, \"Math\") == 0 && result1[2].value == 81);\n\n free(result1);\n\n\n\n char keys2[][50] = {\"Math\", \"Physics\", \"Chemistry\"};\n\n int values2[] = {400, 300, 250};\n\n Item *result2 = func0(keys2, values2, 3);\n\n assert(strcmp(result2[0].key, \"Math\") == 0 && result2[0].value == 400);\n\n assert(strcmp(result2[1].key, \"Physics\") == 0 && result2[1].value == 300);\n\n assert(strcmp(result2[2].key, \"Chemistry\") == 0 && result2[2].value == 250);\n\n free(result2);\n\n\n\n char keys3[][50] = {\"Math\", \"Physics\", \"Chemistry\"};\n\n int values3[] = {900, 1000, 1250};\n\n Item *result3 = func0(keys3, values3, 3);\n\n assert(strcmp(result3[0].key, \"Chemistry\") == 0 && result3[0].value == 1250);\n\n assert(strcmp(result3[1].key, \"Physics\") == 0 && result3[1].value == 1000);\n\n assert(strcmp(result3[2].key, \"Math\") == 0 && result3[2].value == 900);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%r12\nmov %rsi,%rbx\nmov %edx,%r14d\nmovslq %edx,%r15\nlea 0x0(,%r15,8),%rdi\nsub %r15,%rdi\nshl $0x3,%rdi\ncallq 10e0 \nmov %rax,%r13\ntest %r14d,%r14d\njle 1260 \nmov %rax,%rbp\nlea -0x1(%r14),%eax\nlea 0x4(%rbx,%rax,4),%r14\nmov $0x32,%edx\nmov %r12,%rsi\nmov %rbp,%rdi\ncallq 10f0 <__strcpy_chk@plt>\nmov (%rbx),%eax\nmov %eax,0x34(%rbp)\nadd $0x38,%rbp\nadd $0x32,%r12\nadd $0x4,%rbx\ncmp %r14,%rbx\njne 123a \nlea -0x7e(%rip),%rcx\nmov $0x38,%edx\nmov %r15,%rsi\nmov %r13,%rdi\ncallq 10b0 \nmov %r13,%rax\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov r13, rdi\nmov rbx, rsi\nmov ebp, edx\nmovsxd r15, edx\nmov [rsp+48h+nmemb], r15\nlea r14, ds:0[r15*8]\nsub r14, r15\nshl r14, 3\nmov rdi, r14; size\ncall _malloc\nmov [rsp+48h+base], rax\ntest ebp, ebp\njle short loc_12A5\nmov r12, rax\nmov rbp, rbx\nlea r15, [rbx+r15*4]\nmov ebx, 0\nloc_1264:\ncmp r14, rbx\nmov rdx, rbx\ncmovnb rdx, r14\nsub rdx, rbx\nmov eax, 32h ; '2'\ncmp rdx, rax\ncmova rdx, rax\nmov rsi, r13\nmov rdi, r12\ncall ___strcpy_chk\nmov eax, [rbp+0]\nmov [r12+34h], eax\nadd rbx, 38h ; '8'\nadd r12, 38h ; '8'\nadd r13, 32h ; '2'\nadd rbp, 4\ncmp rbp, r15\njnz short loc_1264\nloc_12A5:\nlea rcx, cmp; compar\nmov edx, 38h ; '8'; size\nmov rsi, [rsp+48h+nmemb]; nmemb\nmov rbx, [rsp+48h+base]\nmov rdi, rbx; base\ncall _qsort\nmov rax, rbx\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "void *__fastcall func0(__int64 a1, _DWORD *a2, int a3)\n{\n __int64 v5; // r15\n size_t v6; // r14\n void *v7; // rax\n _DWORD *v8; // r12\n _DWORD *v9; // rbp\n _DWORD *v10; // r15\n size_t v11; // rbx\n size_t v12; // rdx\n unsigned __int64 v13; // rdx\n size_t nmemb; // [rsp+0h] [rbp-48h]\n void *base; // [rsp+8h] [rbp-40h]\n\n v5 = a3;\n nmemb = a3;\n v6 = 56LL * a3;\n v7 = malloc(v6);\n base = v7;\n if ( a3 > 0 )\n {\n v8 = v7;\n v9 = a2;\n v10 = &a2[v5];\n v11 = 0LL;\n do\n {\n v12 = v11;\n if ( v6 >= v11 )\n v12 = v6;\n v13 = v12 - v11;\n if ( v13 > 0x32 )\n v13 = 50LL;\n __strcpy_chk(v8, a1, v13);\n v8[13] = *v9;\n v11 += 56LL;\n v8 += 14;\n a1 += 50LL;\n ++v9;\n }\n while ( v9 != v10 );\n }\n qsort(base, nmemb, 0x38uLL, cmp);\n return base;\n}", + "ida_strip_asm": "sub_1214:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov r13, rdi\nmov rbx, rsi\nmov ebp, edx\nmovsxd r15, edx\nmov [rsp+48h+nmemb], r15\nlea r14, ds:0[r15*8]\nsub r14, r15\nshl r14, 3\nmov rdi, r14; size\ncall _malloc\nmov [rsp+48h+base], rax\ntest ebp, ebp\njle short loc_12A5\nmov r12, rax\nmov rbp, rbx\nlea r15, [rbx+r15*4]\nmov ebx, 0\nloc_1264:\ncmp r14, rbx\nmov rdx, rbx\ncmovnb rdx, r14\nsub rdx, rbx\nmov eax, 32h ; '2'\ncmp rdx, rax\ncmova rdx, rax\nmov rsi, r13\nmov rdi, r12\ncall ___strcpy_chk\nmov eax, [rbp+0]\nmov [r12+34h], eax\nadd rbx, 38h ; '8'\nadd r12, 38h ; '8'\nadd r13, 32h ; '2'\nadd rbp, 4\ncmp rbp, r15\njnz short loc_1264\nloc_12A5:\nlea rcx, compar; compar\nmov edx, 38h ; '8'; size\nmov rsi, [rsp+48h+nmemb]; nmemb\nmov rbx, [rsp+48h+base]\nmov rdi, rbx; base\ncall _qsort\nmov rax, rbx\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "void *__fastcall sub_1214(__int64 a1, _DWORD *a2, int a3)\n{\n __int64 v5; // r15\n size_t v6; // r14\n void *v7; // rax\n _DWORD *v8; // r12\n _DWORD *v9; // rbp\n _DWORD *v10; // r15\n size_t v11; // rbx\n size_t v12; // rdx\n unsigned __int64 v13; // rdx\n size_t nmemb; // [rsp+0h] [rbp-48h]\n void *base; // [rsp+8h] [rbp-40h]\n\n v5 = a3;\n nmemb = a3;\n v6 = 56LL * a3;\n v7 = malloc(v6);\n base = v7;\n if ( a3 > 0 )\n {\n v8 = v7;\n v9 = a2;\n v10 = &a2[v5];\n v11 = 0LL;\n do\n {\n v12 = v11;\n if ( v6 >= v11 )\n v12 = v6;\n v13 = v12 - v11;\n if ( v13 > 0x32 )\n v13 = 50LL;\n __strcpy_chk(v8, a1, v13);\n v8[13] = *v9;\n v11 += 56LL;\n v8 += 14;\n a1 += 50LL;\n ++v9;\n }\n while ( v9 != v10 );\n }\n qsort(base, nmemb, 0x38uLL, compar);\n return base;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1214(long long a1, uint32_t *a2, int a3) {\n long long v5;\n unsigned int v6;\n void *v7;\n uint32_t *v8;\n uint32_t *v9;\n uint32_t *v10;\n unsigned int v11;\n unsigned int v12;\n unsigned long long v13;\n unsigned int nmemb;\n void *base;\n v5 = a3;\n nmemb = a3;\n v6 = 56LL * a3;\n v7 = malloc(v6);\n base = v7;\n if (a3 > 0) {\n v8 = v7;\n v9 = a2;\n v10 = &a2[v5];\n v11 = 0LL;\n do {\n v12 = v11;\n if (v6 >= v11) v12 = v6;\n v13 = v12 - v11;\n if (v13 > 50) v13 = 50LL;\n __strcpy_chk(v8, a1, v13);\n v8[13] = *v9;\n v11 += 56LL;\n v8 += 14;\n a1 += 50LL;\n ++v9;\n } while (v9 != v10);\n }\n qsort(base, nmemb, 56uLL, compar);\n return base;\n}", + "ida_pseudo_norm": "void *func0(long long a1, uint32_t *a2, int a3) {\n long long v5;\n unsigned int v6;\n void *v7;\n uint32_t *v8;\n uint32_t *v9;\n uint32_t *v10;\n unsigned int v11;\n unsigned int v12;\n unsigned long long v13;\n unsigned int nmemb;\n void *base;\n v5 = a3;\n nmemb = a3;\n v6 = 56LL * a3;\n v7 = malloc(v6);\n base = v7;\n if (a3 > 0) {\n v8 = v7;\n v9 = a2;\n v10 = &a2[v5];\n v11 = 0LL;\n do {\n v12 = v11;\n if (v6 >= v11) v12 = v6;\n v13 = v12 - v11;\n if (v13 > 50) v13 = 50LL;\n __strcpy_chk(v8, a1, v13);\n v8[13] = *v9;\n v11 += 56LL;\n v8 += 14;\n a1 += 50LL;\n ++v9;\n } while (v9 != v10);\n }\n qsort(base, nmemb, 56uLL, cmp);\n return base;\n}" + }, + { + "index": 475, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char key[50];\n\n int value;\n\n} Item;\n\n\n\nint cmp(const void *a, const void *b) {\n\n Item *itemA = (Item *)a;\n\n Item *itemB = (Item *)b;\n\n return (itemB->value - itemA->value);\n\n}\n\n\n\n", + "func": "Item* func0(char keys[][50], int values[], int length) {\n Item* items = malloc(length * sizeof(Item));\n for (int i = 0; i < length; i++) {\n strcpy(items[i].key, keys[i]);\n items[i].value = values[i];\n }\n qsort(items, length, sizeof(Item), cmp);\n return items;\n}", + "test": "int main() {\n\n char keys1[][50] = {\"Math\", \"Physics\", \"Chemistry\"};\n\n int values1[] = {81, 83, 87};\n\n Item *result1 = func0(keys1, values1, 3);\n\n assert(strcmp(result1[0].key, \"Chemistry\") == 0 && result1[0].value == 87);\n\n assert(strcmp(result1[1].key, \"Physics\") == 0 && result1[1].value == 83);\n\n assert(strcmp(result1[2].key, \"Math\") == 0 && result1[2].value == 81);\n\n free(result1);\n\n\n\n char keys2[][50] = {\"Math\", \"Physics\", \"Chemistry\"};\n\n int values2[] = {400, 300, 250};\n\n Item *result2 = func0(keys2, values2, 3);\n\n assert(strcmp(result2[0].key, \"Math\") == 0 && result2[0].value == 400);\n\n assert(strcmp(result2[1].key, \"Physics\") == 0 && result2[1].value == 300);\n\n assert(strcmp(result2[2].key, \"Chemistry\") == 0 && result2[2].value == 250);\n\n free(result2);\n\n\n\n char keys3[][50] = {\"Math\", \"Physics\", \"Chemistry\"};\n\n int values3[] = {900, 1000, 1250};\n\n Item *result3 = func0(keys3, values3, 3);\n\n assert(strcmp(result3[0].key, \"Chemistry\") == 0 && result3[0].value == 1250);\n\n assert(strcmp(result3[1].key, \"Physics\") == 0 && result3[1].value == 1000);\n\n assert(strcmp(result3[2].key, \"Math\") == 0 && result3[2].value == 900);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\nmovslq %edx,%r13\npush %r12\npush %rbp\nmov %rdi,%rbp\nlea 0x0(,%r13,8),%rdi\npush %rbx\nsub %r13,%rdi\nmov %rsi,%rbx\nshl $0x3,%rdi\ncallq 10e0 \nmov %rax,%r12\ntest %r13d,%r13d\njle 16fa \nmov %rax,%rcx\nlea -0x1(%r13),%eax\nlea 0x4(%rbx,%rax,4),%r14\nnopl (%rax)\nmov %rbp,%rsi\nmov %rcx,%rdi\nmov $0x32,%edx\nadd $0x4,%rbx\ncallq 10f0 <__strcpy_chk@plt>\nadd $0x32,%rbp\nmov %rax,%rcx\nmov -0x4(%rbx),%eax\nadd $0x38,%rcx\nmov %eax,-0x4(%rcx)\ncmp %r14,%rbx\njne 16d0 \nmov %r13,%rsi\nmov %r12,%rdi\nmov $0x38,%edx\nlea -0x8c(%rip),%rcx\ncallq 10b0 \npop %rbx\nmov %r12,%rax\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov r15, rsi\npush r14\npush r13\nmovsxd r13, edx\npush r12\nmov r12, rdi\npush rbp\npush rbx\nlea rbx, ds:0[r13*8]\nsub rbx, r13\nshl rbx, 3\nsub rsp, 18h\nmov rdi, rbx; size\ncall _malloc\nmov [rsp+48h+base], rax\ntest r13d, r13d\njle short loc_1743\nmov rcx, rax\nlea rbp, [r15+r13*4]\nxor r14d, r14d\nnop word ptr [rax+rax+00000000h]\nloc_1700:\ncmp rbx, r14\nmov rdx, r14\nmov eax, 32h ; '2'\nmov rsi, r12\ncmovnb rdx, rbx\nmov rdi, rcx\nsub rdx, r14\ncmp rdx, rax\ncmova rdx, rax\nadd r15, 4\nadd r14, 38h ; '8'\nadd r12, 32h ; '2'\ncall ___strcpy_chk\nmov rcx, rax\nmov eax, [r15-4]\nadd rcx, 38h ; '8'\nmov [rcx-4], eax\ncmp r15, rbp\njnz short loc_1700\nloc_1743:\nmov rbx, [rsp+48h+base]\nmov rsi, r13; nmemb\nmov edx, 38h ; '8'; size\nlea rcx, cmp; compar\nmov rdi, rbx; base\ncall _qsort\nadd rsp, 18h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "void *__fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n __int64 v3; // r15\n size_t v4; // r13\n size_t v6; // rbx\n void *v7; // rax\n void *v8; // rcx\n size_t v9; // rbp\n size_t v10; // r14\n size_t v11; // rdx\n __int64 v12; // rsi\n unsigned __int64 v13; // rdx\n __int64 v14; // rax\n void *base; // [rsp+8h] [rbp-40h]\n\n v3 = a2;\n v4 = a3;\n v6 = 56LL * a3;\n v7 = malloc(v6);\n base = v7;\n if ( (int)v4 > 0 )\n {\n v8 = v7;\n v9 = a2 + 4 * v4;\n v10 = 0LL;\n do\n {\n v11 = v10;\n v12 = a1;\n if ( v6 >= v10 )\n v11 = v6;\n v13 = v11 - v10;\n if ( v13 > 0x32 )\n v13 = 50LL;\n v3 += 4LL;\n v10 += 56LL;\n a1 += 50LL;\n v14 = __strcpy_chk(v8, v12, v13);\n v8 = (void *)(v14 + 56);\n *(_DWORD *)(v14 + 52) = *(_DWORD *)(v3 - 4);\n }\n while ( v3 != v9 );\n }\n qsort(base, v4, 0x38uLL, cmp);\n return base;\n}", + "ida_strip_asm": "sub_16B0:\nendbr64\npush r15\nmov r15, rsi\npush r14\npush r13\nmovsxd r13, edx\npush r12\nmov r12, rdi\npush rbp\npush rbx\nlea rbx, ds:0[r13*8]\nsub rbx, r13\nshl rbx, 3\nsub rsp, 18h\nmov rdi, rbx; size\ncall _malloc\nmov [rsp+48h+base], rax\ntest r13d, r13d\njle short loc_1743\nmov rcx, rax\nlea rbp, [r15+r13*4]\nxor r14d, r14d\nnop word ptr [rax+rax+00000000h]\nloc_1700:\ncmp rbx, r14\nmov rdx, r14\nmov eax, 32h ; '2'\nmov rsi, r12\ncmovnb rdx, rbx\nmov rdi, rcx\nsub rdx, r14\ncmp rdx, rax\ncmova rdx, rax\nadd r15, 4\nadd r14, 38h ; '8'\nadd r12, 32h ; '2'\ncall ___strcpy_chk\nmov rcx, rax\nmov eax, [r15-4]\nadd rcx, 38h ; '8'\nmov [rcx-4], eax\ncmp r15, rbp\njnz short loc_1700\nloc_1743:\nmov rbx, [rsp+48h+base]\nmov rsi, r13; nmemb\nmov edx, 38h ; '8'; size\nlea rcx, compar; compar\nmov rdi, rbx; base\ncall _qsort\nadd rsp, 18h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "void *__fastcall sub_16B0(__int64 a1, __int64 a2, int a3)\n{\n __int64 v3; // r15\n size_t v4; // r13\n size_t v6; // rbx\n void *v7; // rax\n void *v8; // rcx\n size_t v9; // rbp\n size_t v10; // r14\n size_t v11; // rdx\n __int64 v12; // rsi\n unsigned __int64 v13; // rdx\n __int64 v14; // rax\n void *base; // [rsp+8h] [rbp-40h]\n\n v3 = a2;\n v4 = a3;\n v6 = 56LL * a3;\n v7 = malloc(v6);\n base = v7;\n if ( (int)v4 > 0 )\n {\n v8 = v7;\n v9 = a2 + 4 * v4;\n v10 = 0LL;\n do\n {\n v11 = v10;\n v12 = a1;\n if ( v6 >= v10 )\n v11 = v6;\n v13 = v11 - v10;\n if ( v13 > 0x32 )\n v13 = 50LL;\n v3 += 4LL;\n v10 += 56LL;\n a1 += 50LL;\n v14 = __strcpy_chk(v8, v12, v13);\n v8 = (void *)(v14 + 56);\n *(_DWORD *)(v14 + 52) = *(_DWORD *)(v3 - 4);\n }\n while ( v3 != v9 );\n }\n qsort(base, v4, 0x38uLL, compar);\n return base;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_16B0(long long a1, long long a2, int a3) {\n long long v3;\n unsigned int v4;\n unsigned int v6;\n void *v7;\n void *v8;\n unsigned int v9;\n unsigned int v10;\n unsigned int v11;\n long long v12;\n unsigned long long v13;\n long long v14;\n void *base;\n v3 = a2;\n v4 = a3;\n v6 = 56LL * a3;\n v7 = malloc(v6);\n base = v7;\n if ((int)v4 > 0) {\n v8 = v7;\n v9 = a2 + 4 * v4;\n v10 = 0LL;\n do {\n v11 = v10;\n v12 = a1;\n if (v6 >= v10) v11 = v6;\n v13 = v11 - v10;\n if (v13 > 50) v13 = 50LL;\n v3 += 4LL;\n v10 += 56LL;\n a1 += 50LL;\n v14 = __strcpy_chk(v8, v12, v13);\n v8 = (void *)(v14 + 56);\n *(uint32_t *)(v14 + 52) = *(uint32_t *)(v3 - 4);\n } while (v3 != v9);\n }\n qsort(base, v4, 56uLL, compar);\n return base;\n}", + "ida_pseudo_norm": "void *func0(long long a1, long long a2, int a3) {\n long long v3;\n unsigned int v4;\n unsigned int v6;\n void *v7;\n void *v8;\n unsigned int v9;\n unsigned int v10;\n unsigned int v11;\n long long v12;\n unsigned long long v13;\n long long v14;\n void *base;\n v3 = a2;\n v4 = a3;\n v6 = 56LL * a3;\n v7 = malloc(v6);\n base = v7;\n if ((int)v4 > 0) {\n v8 = v7;\n v9 = a2 + 4 * v4;\n v10 = 0LL;\n do {\n v11 = v10;\n v12 = a1;\n if (v6 >= v10) v11 = v6;\n v13 = v11 - v10;\n if (v13 > 50) v13 = 50LL;\n v3 += 4LL;\n v10 += 56LL;\n a1 += 50LL;\n v14 = __strcpy_chk(v8, v12, v13);\n v8 = (void *)(v14 + 56);\n *(uint32_t *)(v14 + 52) = *(uint32_t *)(v3 - 4);\n } while (v3 != v9);\n }\n qsort(base, v4, 56uLL, cmp);\n return base;\n}" + }, + { + "index": 475, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char key[50];\n\n int value;\n\n} Item;\n\n\n\nint cmp(const void *a, const void *b) {\n\n Item *itemA = (Item *)a;\n\n Item *itemB = (Item *)b;\n\n return (itemB->value - itemA->value);\n\n}\n\n\n\n", + "func": "Item* func0(char keys[][50], int values[], int length) {\n Item* items = malloc(length * sizeof(Item));\n for (int i = 0; i < length; i++) {\n strcpy(items[i].key, keys[i]);\n items[i].value = values[i];\n }\n qsort(items, length, sizeof(Item), cmp);\n return items;\n}", + "test": "int main() {\n\n char keys1[][50] = {\"Math\", \"Physics\", \"Chemistry\"};\n\n int values1[] = {81, 83, 87};\n\n Item *result1 = func0(keys1, values1, 3);\n\n assert(strcmp(result1[0].key, \"Chemistry\") == 0 && result1[0].value == 87);\n\n assert(strcmp(result1[1].key, \"Physics\") == 0 && result1[1].value == 83);\n\n assert(strcmp(result1[2].key, \"Math\") == 0 && result1[2].value == 81);\n\n free(result1);\n\n\n\n char keys2[][50] = {\"Math\", \"Physics\", \"Chemistry\"};\n\n int values2[] = {400, 300, 250};\n\n Item *result2 = func0(keys2, values2, 3);\n\n assert(strcmp(result2[0].key, \"Math\") == 0 && result2[0].value == 400);\n\n assert(strcmp(result2[1].key, \"Physics\") == 0 && result2[1].value == 300);\n\n assert(strcmp(result2[2].key, \"Chemistry\") == 0 && result2[2].value == 250);\n\n free(result2);\n\n\n\n char keys3[][50] = {\"Math\", \"Physics\", \"Chemistry\"};\n\n int values3[] = {900, 1000, 1250};\n\n Item *result3 = func0(keys3, values3, 3);\n\n assert(strcmp(result3[0].key, \"Chemistry\") == 0 && result3[0].value == 1250);\n\n assert(strcmp(result3[1].key, \"Physics\") == 0 && result3[1].value == 1000);\n\n assert(strcmp(result3[2].key, \"Math\") == 0 && result3[2].value == 900);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\nmovslq %edx,%r13\npush %r12\npush %rbp\nmov %rdi,%rbp\nlea 0x0(,%r13,8),%rdi\npush %rbx\nsub %r13,%rdi\nmov %rsi,%rbx\nshl $0x3,%rdi\ncallq 10e0 \nmov %rax,%r12\ntest %r13d,%r13d\njle 16fa \nmov %rax,%rcx\nlea -0x1(%r13),%eax\nlea 0x4(%rbx,%rax,4),%r14\nnopl (%rax)\nmov %rbp,%rsi\nmov %rcx,%rdi\nmov $0x32,%edx\nadd $0x4,%rbx\ncallq 10f0 <__strcpy_chk@plt>\nadd $0x32,%rbp\nmov %rax,%rcx\nmov -0x4(%rbx),%eax\nadd $0x38,%rcx\nmov %eax,-0x4(%rcx)\ncmp %r14,%rbx\njne 16d0 \nmov %r13,%rsi\nmov %r12,%rdi\nmov $0x38,%edx\nlea -0x8c(%rip),%rcx\ncallq 10b0 \npop %rbx\nmov %r12,%rax\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov r15, rsi\npush r14\npush r13\nmovsxd r13, edx\npush r12\nmov r12, rdi\npush rbp\npush rbx\nlea rbx, ds:0[r13*8]\nsub rbx, r13\nshl rbx, 3\nsub rsp, 18h\nmov rdi, rbx; size\ncall _malloc\nmov [rsp+48h+base], rax\ntest r13d, r13d\njle short loc_1743\nmov rcx, rax\nlea rbp, [r15+r13*4]\nxor r14d, r14d\nnop word ptr [rax+rax+00000000h]\nloc_1700:\ncmp rbx, r14\nmov rdx, r14\nmov eax, 32h ; '2'\nmov rsi, r12\ncmovnb rdx, rbx\nmov rdi, rcx\nsub rdx, r14\ncmp rdx, rax\ncmova rdx, rax\nadd r15, 4\nadd r14, 38h ; '8'\nadd r12, 32h ; '2'\ncall ___strcpy_chk\nmov rcx, rax\nmov eax, [r15-4]\nadd rcx, 38h ; '8'\nmov [rcx-4], eax\ncmp r15, rbp\njnz short loc_1700\nloc_1743:\nmov rbx, [rsp+48h+base]\nmov rsi, r13; nmemb\nmov edx, 38h ; '8'; size\nlea rcx, cmp; compar\nmov rdi, rbx; base\ncall _qsort\nadd rsp, 18h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "void *__fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n __int64 v3; // r15\n size_t v4; // r13\n size_t v6; // rbx\n void *v7; // rax\n void *v8; // rcx\n size_t v9; // rbp\n size_t v10; // r14\n size_t v11; // rdx\n __int64 v12; // rsi\n unsigned __int64 v13; // rdx\n __int64 v14; // rax\n void *base; // [rsp+8h] [rbp-40h]\n\n v3 = a2;\n v4 = a3;\n v6 = 56LL * a3;\n v7 = malloc(v6);\n base = v7;\n if ( (int)v4 > 0 )\n {\n v8 = v7;\n v9 = a2 + 4 * v4;\n v10 = 0LL;\n do\n {\n v11 = v10;\n v12 = a1;\n if ( v6 >= v10 )\n v11 = v6;\n v13 = v11 - v10;\n if ( v13 > 0x32 )\n v13 = 50LL;\n v3 += 4LL;\n v10 += 56LL;\n a1 += 50LL;\n v14 = __strcpy_chk(v8, v12, v13);\n v8 = (void *)(v14 + 56);\n *(_DWORD *)(v14 + 52) = *(_DWORD *)(v3 - 4);\n }\n while ( v3 != v9 );\n }\n qsort(base, v4, 0x38uLL, cmp);\n return base;\n}", + "ida_strip_asm": "sub_16B0:\nendbr64\npush r15\nmov r15, rsi\npush r14\npush r13\nmovsxd r13, edx\npush r12\nmov r12, rdi\npush rbp\npush rbx\nlea rbx, ds:0[r13*8]\nsub rbx, r13\nshl rbx, 3\nsub rsp, 18h\nmov rdi, rbx; size\ncall _malloc\nmov [rsp+48h+base], rax\ntest r13d, r13d\njle short loc_1743\nmov rcx, rax\nlea rbp, [r15+r13*4]\nxor r14d, r14d\nnop word ptr [rax+rax+00000000h]\nloc_1700:\ncmp rbx, r14\nmov rdx, r14\nmov eax, 32h ; '2'\nmov rsi, r12\ncmovnb rdx, rbx\nmov rdi, rcx\nsub rdx, r14\ncmp rdx, rax\ncmova rdx, rax\nadd r15, 4\nadd r14, 38h ; '8'\nadd r12, 32h ; '2'\ncall ___strcpy_chk\nmov rcx, rax\nmov eax, [r15-4]\nadd rcx, 38h ; '8'\nmov [rcx-4], eax\ncmp r15, rbp\njnz short loc_1700\nloc_1743:\nmov rbx, [rsp+48h+base]\nmov rsi, r13; nmemb\nmov edx, 38h ; '8'; size\nlea rcx, compar; compar\nmov rdi, rbx; base\ncall _qsort\nadd rsp, 18h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "void *__fastcall sub_16B0(__int64 a1, __int64 a2, int a3)\n{\n __int64 v3; // r15\n size_t v4; // r13\n size_t v6; // rbx\n void *v7; // rax\n void *v8; // rcx\n size_t v9; // rbp\n size_t v10; // r14\n size_t v11; // rdx\n __int64 v12; // rsi\n unsigned __int64 v13; // rdx\n __int64 v14; // rax\n void *base; // [rsp+8h] [rbp-40h]\n\n v3 = a2;\n v4 = a3;\n v6 = 56LL * a3;\n v7 = malloc(v6);\n base = v7;\n if ( (int)v4 > 0 )\n {\n v8 = v7;\n v9 = a2 + 4 * v4;\n v10 = 0LL;\n do\n {\n v11 = v10;\n v12 = a1;\n if ( v6 >= v10 )\n v11 = v6;\n v13 = v11 - v10;\n if ( v13 > 0x32 )\n v13 = 50LL;\n v3 += 4LL;\n v10 += 56LL;\n a1 += 50LL;\n v14 = __strcpy_chk(v8, v12, v13);\n v8 = (void *)(v14 + 56);\n *(_DWORD *)(v14 + 52) = *(_DWORD *)(v3 - 4);\n }\n while ( v3 != v9 );\n }\n qsort(base, v4, 0x38uLL, compar);\n return base;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_16B0(long long a1, long long a2, int a3) {\n long long v3;\n unsigned int v4;\n unsigned int v6;\n void *v7;\n void *v8;\n unsigned int v9;\n unsigned int v10;\n unsigned int v11;\n long long v12;\n unsigned long long v13;\n long long v14;\n void *base;\n v3 = a2;\n v4 = a3;\n v6 = 56LL * a3;\n v7 = malloc(v6);\n base = v7;\n if ((int)v4 > 0) {\n v8 = v7;\n v9 = a2 + 4 * v4;\n v10 = 0LL;\n do {\n v11 = v10;\n v12 = a1;\n if (v6 >= v10) v11 = v6;\n v13 = v11 - v10;\n if (v13 > 50) v13 = 50LL;\n v3 += 4LL;\n v10 += 56LL;\n a1 += 50LL;\n v14 = __strcpy_chk(v8, v12, v13);\n v8 = (void *)(v14 + 56);\n *(uint32_t *)(v14 + 52) = *(uint32_t *)(v3 - 4);\n } while (v3 != v9);\n }\n qsort(base, v4, 56uLL, compar);\n return base;\n}", + "ida_pseudo_norm": "void *func0(long long a1, long long a2, int a3) {\n long long v3;\n unsigned int v4;\n unsigned int v6;\n void *v7;\n void *v8;\n unsigned int v9;\n unsigned int v10;\n unsigned int v11;\n long long v12;\n unsigned long long v13;\n long long v14;\n void *base;\n v3 = a2;\n v4 = a3;\n v6 = 56LL * a3;\n v7 = malloc(v6);\n base = v7;\n if ((int)v4 > 0) {\n v8 = v7;\n v9 = a2 + 4 * v4;\n v10 = 0LL;\n do {\n v11 = v10;\n v12 = a1;\n if (v6 >= v10) v11 = v6;\n v13 = v11 - v10;\n if (v13 > 50) v13 = 50LL;\n v3 += 4LL;\n v10 += 56LL;\n a1 += 50LL;\n v14 = __strcpy_chk(v8, v12, v13);\n v8 = (void *)(v14 + 56);\n *(uint32_t *)(v14 + 52) = *(uint32_t *)(v3 - 4);\n } while (v3 != v9);\n }\n qsort(base, v4, 56uLL, cmp);\n return base;\n}" + }, + { + "index": 476, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int nums[], int size) {\n int max_num = INT_MIN;\n int min_num = INT_MAX;\n for (int i = 0; i < size; i++) {\n if (nums[i] > max_num) {\n max_num = nums[i];\n }\n if (nums[i] < min_num) {\n min_num = nums[i];\n }\n }\n return max_num + min_num;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3};\n\n int arr2[] = {-1, 2, 3, 4};\n\n int arr3[] = {2, 3, 6};\n\n \n\n assert(func0(arr1, 3) == 4);\n\n assert(func0(arr2, 4) == 3);\n\n assert(func0(arr3, 3) == 8);\n\n \n\n printf(\"All test cases passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x80000000,-0xc(%rbp)\nmovl $0x7fffffff,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 121b \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0xc(%rbp)\njge 11e3 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0xc(%rbp)\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x8(%rbp)\njle 1217 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11af \nmov -0xc(%rbp),%edx\nmov -0x8(%rbp),%eax\nadd %edx,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 80000000h\nmov [rbp+var_8], 7FFFFFFFh\nmov [rbp+var_4], 0\njmp short loc_121B\nloc_11AF:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_C], eax\njge short loc_11E3\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nloc_11E3:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_8], eax\njle short loc_1217\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_8], eax\nloc_1217:\nadd [rbp+var_4], 1\nloc_121B:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11AF\nmov edx, [rbp+var_C]\nmov eax, [rbp+var_8]\nadd eax, edx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n signed int v3; // [rsp+10h] [rbp-Ch]\n int v4; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0x80000000;\n v4 = 0x7FFFFFFF;\n for ( i = 0; i < a2; ++i )\n {\n if ( v3 < *(_DWORD *)(4LL * i + a1) )\n v3 = *(_DWORD *)(4LL * i + a1);\n if ( v4 > *(_DWORD *)(4LL * i + a1) )\n v4 = *(_DWORD *)(4LL * i + a1);\n }\n return (unsigned int)(v3 + v4);\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 80000000h\nmov [rbp+var_8], 7FFFFFFFh\nmov [rbp+var_4], 0\njmp short loc_121B\nloc_11AF:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_C], eax\njge short loc_11E3\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nloc_11E3:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_8], eax\njle short loc_1217\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_8], eax\nloc_1217:\nadd [rbp+var_4], 1\nloc_121B:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11AF\nmov edx, [rbp+var_C]\nmov eax, [rbp+var_8]\nadd eax, edx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2)\n{\n signed int v3; // [rsp+10h] [rbp-Ch]\n int v4; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0x80000000;\n v4 = 0x7FFFFFFF;\n for ( i = 0; i < a2; ++i )\n {\n if ( v3 < *(_DWORD *)(4LL * i + a1) )\n v3 = *(_DWORD *)(4LL * i + a1);\n if ( v4 > *(_DWORD *)(4LL * i + a1) )\n v4 = *(_DWORD *)(4LL * i + a1);\n }\n return (unsigned int)(v3 + v4);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2) {\n signed int v3;\n int v4;\n int i;\n v3 = 2147483648;\n v4 = 2147483647;\n for (i = 0; i < a2; ++i) {\n if (v3 < *(uint32_t *)(4LL * i + a1)) v3 = *(uint32_t *)(4LL * i + a1);\n if (v4 > *(uint32_t *)(4LL * i + a1)) v4 = *(uint32_t *)(4LL * i + a1);\n }\n return (unsigned int)(v3 + v4);\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n signed int v3;\n int v4;\n int i;\n v3 = 2147483648;\n v4 = 2147483647;\n for (i = 0; i < a2; ++i) {\n if (v3 < *(uint32_t *)(4LL * i + a1)) v3 = *(uint32_t *)(4LL * i + a1);\n if (v4 > *(uint32_t *)(4LL * i + a1)) v4 = *(uint32_t *)(4LL * i + a1);\n }\n return (unsigned int)(v3 + v4);\n}" + }, + { + "index": 476, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int nums[], int size) {\n int max_num = INT_MIN;\n int min_num = INT_MAX;\n for (int i = 0; i < size; i++) {\n if (nums[i] > max_num) {\n max_num = nums[i];\n }\n if (nums[i] < min_num) {\n min_num = nums[i];\n }\n }\n return max_num + min_num;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3};\n\n int arr2[] = {-1, 2, 3, 4};\n\n int arr3[] = {2, 3, 6};\n\n \n\n assert(func0(arr1, 3) == 4);\n\n assert(func0(arr2, 4) == 3);\n\n assert(func0(arr3, 3) == 8);\n\n \n\n printf(\"All test cases passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11be \nmov %rdi,%rcx\nlea -0x1(%rsi),%eax\nlea 0x4(%rdi,%rax,4),%rdi\nmov $0x7fffffff,%esi\nmov $0x80000000,%eax\nmov (%rcx),%edx\ncmp %edx,%eax\ncmovl %edx,%eax\ncmp %edx,%esi\ncmovg %edx,%esi\nadd $0x4,%rcx\ncmp %rdi,%rcx\njne 11a6 \nadd %esi,%eax\nretq\nmov $0x7fffffff,%esi\nmov $0x80000000,%eax\njmp 11bb \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11BD\nmov rcx, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*4]\nmov esi, 7FFFFFFFh\nmov eax, 80000000h\nloc_11A5:\nmov edx, [rcx]\ncmp eax, edx\ncmovl eax, edx\ncmp esi, edx\ncmovg esi, edx\nadd rcx, 4\ncmp rcx, rdi\njnz short loc_11A5\nloc_11BA:\nadd eax, esi\nretn\nloc_11BD:\nmov esi, 7FFFFFFFh\nmov eax, 80000000h\njmp short loc_11BA", + "ida_pseudo": "__int64 __fastcall func0(signed int *a1, int a2)\n{\n signed int *v2; // rcx\n signed int *v3; // rdi\n int v4; // esi\n signed int v5; // eax\n\n if ( a2 <= 0 )\n {\n v4 = 0x7FFFFFFF;\n v5 = 0x80000000;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0x7FFFFFFF;\n v5 = 0x80000000;\n do\n {\n if ( v5 < *v2 )\n v5 = *v2;\n if ( v4 > *v2 )\n v4 = *v2;\n ++v2;\n }\n while ( v2 != v3 );\n }\n return (unsigned int)(v4 + v5);\n}", + "ida_strip_asm": "sub_1189:\nendbr64\ntest esi, esi\njle short loc_11BD\nmov rcx, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*4]\nmov esi, 7FFFFFFFh\nmov eax, 80000000h\nloc_11A5:\nmov edx, [rcx]\ncmp eax, edx\ncmovl eax, edx\ncmp esi, edx\ncmovg esi, edx\nadd rcx, 4\ncmp rcx, rdi\njnz short loc_11A5\nloc_11BA:\nadd eax, esi\nretn\nloc_11BD:\nmov esi, 7FFFFFFFh\nmov eax, 80000000h\njmp short loc_11BA", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(signed int *a1, int a2)\n{\n signed int *v2; // rcx\n signed int *v3; // rdi\n int v4; // esi\n signed int v5; // eax\n\n if ( a2 <= 0 )\n {\n v4 = 0x7FFFFFFF;\n v5 = 0x80000000;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0x7FFFFFFF;\n v5 = 0x80000000;\n do\n {\n if ( v5 < *v2 )\n v5 = *v2;\n if ( v4 > *v2 )\n v4 = *v2;\n ++v2;\n }\n while ( v2 != v3 );\n }\n return (unsigned int)(v4 + v5);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(signed int *a1, int a2) {\n signed int *v2;\n signed int *v3;\n int v4;\n signed int v5;\n if (a2 <= 0) {\n v4 = 2147483647;\n v5 = 2147483648;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 2147483647;\n v5 = 2147483648;\n do {\n if (v5 < *v2) v5 = *v2;\n if (v4 > *v2) v4 = *v2;\n ++v2;\n } while (v2 != v3);\n }\n return (unsigned int)(v4 + v5);\n}", + "ida_pseudo_norm": "long long func0(signed int *a1, int a2) {\n signed int *v2;\n signed int *v3;\n int v4;\n signed int v5;\n if (a2 <= 0) {\n v4 = 2147483647;\n v5 = 2147483648;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 2147483647;\n v5 = 2147483648;\n do {\n if (v5 < *v2) v5 = *v2;\n if (v4 > *v2) v4 = *v2;\n ++v2;\n } while (v2 != v3);\n }\n return (unsigned int)(v4 + v5);\n}" + }, + { + "index": 477, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(char* input, char* output) {\n int i = 0;\n while (input[i]) {\n output[i] = tolower((unsigned char)input[i]);\n i++;\n }\n output[i] = '\\0';\n}", + "test": "int main() {\n\n char result[100];\n\n\n\n func0(\"InValid\", result);\n\n assert(strcmp(result, \"invalid\") == 0);\n\n\n\n func0(\"TruE\", result);\n\n assert(strcmp(result, \"true\") == 0);\n\n\n\n func0(\"SenTenCE\", result);\n\n assert(strcmp(result, \"sentence\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11f7 \nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmovzbl %al,%eax\nmov %eax,%edi\ncallq 10b0 \nmov %eax,%ecx\nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov %ecx,%edx\nmov %dl,(%rax)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 11c6 \nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmovb $0x0,(%rax)\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_4], 0\njmp short loc_11F7\nloc_11C6:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovzx eax, al\nmov edi, eax; c\ncall _tolower\nmov ecx, eax\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov edx, ecx\nmov [rax], dl\nadd [rbp+var_4], 1\nloc_11F7:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_11C6\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov byte ptr [rax], 0\nnop\nleave\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(__int64 a1, __int64 a2)\n{\n _BYTE *result; // rax\n int i; // [rsp+1Ch] [rbp-4h]\n\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n *(_BYTE *)(i + a2) = tolower(*(unsigned __int8 *)(i + a1));\n result = (_BYTE *)(i + a2);\n *result = 0;\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_4], 0\njmp short loc_11F7\nloc_11C6:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovzx eax, al\nmov edi, eax; c\ncall _tolower\nmov ecx, eax\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov edx, ecx\nmov [rax], dl\nadd [rbp+var_4], 1\nloc_11F7:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_11C6\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov byte ptr [rax], 0\nnop\nleave\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_11A9(__int64 a1, __int64 a2)\n{\n _BYTE *result; // rax\n int i; // [rsp+1Ch] [rbp-4h]\n\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n *(_BYTE *)(i + a2) = tolower(*(unsigned __int8 *)(i + a1));\n result = (_BYTE *)(i + a2);\n *result = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_11A9(long long a1, long long a2) {\n uint8_t *result;\n int i;\n for (i = 0; *(uint8_t *)(i + a1); ++i)\n *(uint8_t *)(i + a2) = tolower(*(unsigned char *)(i + a1));\n result = (uint8_t *)(i + a2);\n *result = 0;\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(long long a1, long long a2) {\n uint8_t *result;\n int i;\n for (i = 0; *(uint8_t *)(i + a1); ++i)\n *(uint8_t *)(i + a2) = tolower(*(unsigned char *)(i + a1));\n result = (uint8_t *)(i + a2);\n *result = 0;\n return result;\n}" + }, + { + "index": 477, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(char* input, char* output) {\n int i = 0;\n while (input[i]) {\n output[i] = tolower((unsigned char)input[i]);\n i++;\n }\n output[i] = '\\0';\n}", + "test": "int main() {\n\n char result[100];\n\n\n\n func0(\"InValid\", result);\n\n assert(strcmp(result, \"invalid\") == 0);\n\n\n\n func0(\"TruE\", result);\n\n assert(strcmp(result, \"true\") == 0);\n\n\n\n func0(\"SenTenCE\", result);\n\n assert(strcmp(result, \"sentence\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmov %rsi,%rbp\nmovzbl (%rdi),%ebx\ntest %bl,%bl\nje 11cc \nmov %rdi,%r12\ncallq 1090 <__ctype_tolower_loc@plt>\nmov $0x0,%edx\nmovzbl %bl,%ebx\nmov (%rax),%rcx\nmov (%rcx,%rbx,4),%ecx\nmov %cl,0x0(%rbp,%rdx,1)\nadd $0x1,%rdx\nmovzbl (%r12,%rdx,1),%ebx\ntest %bl,%bl\njne 11a8 \nmovb $0x0,0x0(%rbp,%rdx,1)\npop %rbx\npop %rbp\npop %r12\nretq\nmov $0x0,%edx\njmp 11c2 \n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbp, rsi\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_11EC\nmov r12, rdi\ncall ___ctype_tolower_loc\nmov edx, 0\nloc_11C8:\nmovzx ebx, bl\nmov rcx, [rax]\nmov ecx, [rcx+rbx*4]\nmov [rbp+rdx+0], cl\nadd rdx, 1\nmovzx ebx, byte ptr [r12+rdx]\ntest bl, bl\njnz short loc_11C8\nloc_11E2:\nmov byte ptr [rbp+rdx+0], 0\npop rbx\npop rbp\npop r12\nretn\nloc_11EC:\nmov edx, 0\njmp short loc_11E2", + "ida_pseudo": "void __fastcall func0(unsigned __int8 *a1, __int64 a2)\n{\n unsigned __int8 v2; // bl\n const __int32_t **v3; // rax\n __int64 v4; // rdx\n\n v2 = *a1;\n if ( *a1 )\n {\n v3 = __ctype_tolower_loc();\n v4 = 0LL;\n do\n {\n *(_BYTE *)(a2 + v4++) = (*v3)[v2];\n v2 = a1[v4];\n }\n while ( v2 );\n }\n else\n {\n v4 = 0LL;\n }\n *(_BYTE *)(a2 + v4) = 0;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbp, rsi\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_11EC\nmov r12, rdi\ncall ___ctype_tolower_loc\nmov edx, 0\nloc_11C8:\nmovzx ebx, bl\nmov rcx, [rax]\nmov ecx, [rcx+rbx*4]\nmov [rbp+rdx+0], cl\nadd rdx, 1\nmovzx ebx, byte ptr [r12+rdx]\ntest bl, bl\njnz short loc_11C8\nloc_11E2:\nmov byte ptr [rbp+rdx+0], 0\npop rbx\npop rbp\npop r12\nretn\nloc_11EC:\nmov edx, 0\njmp short loc_11E2", + "ida_strip_pseudo": "void __fastcall sub_11A9(unsigned __int8 *a1, __int64 a2)\n{\n unsigned __int8 v2; // bl\n const __int32_t **v3; // rax\n __int64 v4; // rdx\n\n v2 = *a1;\n if ( *a1 )\n {\n v3 = __ctype_tolower_loc();\n v4 = 0LL;\n do\n {\n *(_BYTE *)(a2 + v4++) = (*v3)[v2];\n v2 = a1[v4];\n }\n while ( v2 );\n }\n else\n {\n v4 = 0LL;\n }\n *(_BYTE *)(a2 + v4) = 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_11A9(unsigned char *a1, long long a2) {\n unsigned char v2;\n const __int32_t **v3;\n long long v4;\n v2 = *a1;\n if (*a1) {\n v3 = __ctype_tolower_loc();\n v4 = 0LL;\n do {\n *(uint8_t *)(a2 + v4++) = (*v3)[v2];\n v2 = a1[v4];\n } while (v2);\n } else {\n v4 = 0LL;\n }\n *(uint8_t *)(a2 + v4) = 0;\n}", + "ida_pseudo_norm": "void func0(unsigned char *a1, long long a2) {\n unsigned char v2;\n const __int32_t **v3;\n long long v4;\n v2 = *a1;\n if (*a1) {\n v3 = __ctype_tolower_loc();\n v4 = 0LL;\n do {\n *(uint8_t *)(a2 + v4++) = (*v3)[v2];\n v2 = a1[v4];\n } while (v2);\n } else {\n v4 = 0LL;\n }\n *(uint8_t *)(a2 + v4) = 0;\n}" + }, + { + "index": 477, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(char* input, char* output) {\n int i = 0;\n while (input[i]) {\n output[i] = tolower((unsigned char)input[i]);\n i++;\n }\n output[i] = '\\0';\n}", + "test": "int main() {\n\n char result[100];\n\n\n\n func0(\"InValid\", result);\n\n assert(strcmp(result, \"invalid\") == 0);\n\n\n\n func0(\"TruE\", result);\n\n assert(strcmp(result, \"true\") == 0);\n\n\n\n func0(\"SenTenCE\", result);\n\n assert(strcmp(result, \"sentence\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\nmov %rsi,%rbp\npush %rbx\nmovzbl (%rdi),%ebx\ntest %bl,%bl\nje 12cd \nmov %rdi,%r12\ncallq 1090 <__ctype_tolower_loc@plt>\nxor %edx,%edx\nnopl 0x0(%rax)\nmov (%rax),%rcx\nmovzbl %bl,%ebx\nmov (%rcx,%rbx,4),%ecx\nmov %cl,0x0(%rbp,%rdx,1)\nadd $0x1,%rdx\nmovzbl (%r12,%rdx,1),%ebx\ntest %bl,%bl\njne 12b0 \nadd %rdx,%rbp\npop %rbx\nmovb $0x0,0x0(%rbp)\npop %rbp\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\nmov rbp, rsi\npush rbx\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_12CA\nmov r12, rdi\ncall ___ctype_tolower_loc\nxor edx, edx\nnop dword ptr [rax+00h]\nloc_12B0:\nmov rcx, [rax]\nmov ecx, [rcx+rbx*4]\nmov [rbp+rdx+0], cl\nadd rdx, 1\nmovzx ebx, byte ptr [r12+rdx]\ntest bl, bl\njnz short loc_12B0\nadd rbp, rdx\nloc_12CA:\nmov byte ptr [rbp+0], 0\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "void __fastcall func0(unsigned __int8 *a1, _BYTE *a2)\n{\n _BYTE *v2; // rbp\n __int64 v3; // rbx\n const __int32_t **v4; // rax\n __int64 v5; // rdx\n\n v2 = a2;\n v3 = *a1;\n if ( (_BYTE)v3 )\n {\n v4 = __ctype_tolower_loc();\n v5 = 0LL;\n do\n {\n a2[v5++] = (*v4)[v3];\n v3 = a1[v5];\n }\n while ( (_BYTE)v3 );\n v2 = &a2[v5];\n }\n *v2 = 0;\n}", + "ida_strip_asm": "sub_1290:\nendbr64\npush r12\npush rbp\nmov rbp, rsi\npush rbx\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_12CA\nmov r12, rdi\ncall ___ctype_tolower_loc\nxor edx, edx\nnop dword ptr [rax+00h]\nloc_12B0:\nmov rcx, [rax]\nmov ecx, [rcx+rbx*4]\nmov [rbp+rdx+0], cl\nadd rdx, 1\nmovzx ebx, byte ptr [r12+rdx]\ntest bl, bl\njnz short loc_12B0\nadd rbp, rdx\nloc_12CA:\nmov byte ptr [rbp+0], 0\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "void __fastcall sub_1290(unsigned __int8 *a1, _BYTE *a2)\n{\n _BYTE *v2; // rbp\n __int64 v3; // rbx\n const __int32_t **v4; // rax\n __int64 v5; // rdx\n\n v2 = a2;\n v3 = *a1;\n if ( (_BYTE)v3 )\n {\n v4 = __ctype_tolower_loc();\n v5 = 0LL;\n do\n {\n a2[v5++] = (*v4)[v3];\n v3 = a1[v5];\n }\n while ( (_BYTE)v3 );\n v2 = &a2[v5];\n }\n *v2 = 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1290(unsigned char *a1, uint8_t *a2) {\n uint8_t *v2;\n long long v3;\n const __int32_t **v4;\n long long v5;\n v2 = a2;\n v3 = *a1;\n if ((uint8_t)v3) {\n v4 = __ctype_tolower_loc();\n v5 = 0LL;\n do {\n a2[v5++] = (*v4)[v3];\n v3 = a1[v5];\n } while ((uint8_t)v3);\n v2 = &a2[v5];\n }\n *v2 = 0;\n}", + "ida_pseudo_norm": "void func0(unsigned char *a1, uint8_t *a2) {\n uint8_t *v2;\n long long v3;\n const __int32_t **v4;\n long long v5;\n v2 = a2;\n v3 = *a1;\n if ((uint8_t)v3) {\n v4 = __ctype_tolower_loc();\n v5 = 0LL;\n do {\n a2[v5++] = (*v4)[v3];\n v3 = a1[v5];\n } while ((uint8_t)v3);\n v2 = &a2[v5];\n }\n *v2 = 0;\n}" + }, + { + "index": 477, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(char* input, char* output) {\n int i = 0;\n while (input[i]) {\n output[i] = tolower((unsigned char)input[i]);\n i++;\n }\n output[i] = '\\0';\n}", + "test": "int main() {\n\n char result[100];\n\n\n\n func0(\"InValid\", result);\n\n assert(strcmp(result, \"invalid\") == 0);\n\n\n\n func0(\"TruE\", result);\n\n assert(strcmp(result, \"true\") == 0);\n\n\n\n func0(\"SenTenCE\", result);\n\n assert(strcmp(result, \"sentence\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\nmov %rsi,%rbp\npush %rbx\nmovzbl (%rdi),%ebx\ntest %bl,%bl\nje 12cd \nmov %rdi,%r12\ncallq 1090 <__ctype_tolower_loc@plt>\nxor %edx,%edx\nnopl 0x0(%rax)\nmov (%rax),%rcx\nmovzbl %bl,%ebx\nmov (%rcx,%rbx,4),%ecx\nmov %cl,0x0(%rbp,%rdx,1)\nadd $0x1,%rdx\nmovzbl (%r12,%rdx,1),%ebx\ntest %bl,%bl\njne 12b0 \nadd %rdx,%rbp\npop %rbx\nmovb $0x0,0x0(%rbp)\npop %rbp\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\nmov rbp, rsi\npush rbx\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_12CA\nmov r12, rdi\ncall ___ctype_tolower_loc\nxor edx, edx\nnop dword ptr [rax+00h]\nloc_12B0:\nmov rcx, [rax]\nmov ecx, [rcx+rbx*4]\nmov [rbp+rdx+0], cl\nadd rdx, 1\nmovzx ebx, byte ptr [r12+rdx]\ntest bl, bl\njnz short loc_12B0\nadd rbp, rdx\nloc_12CA:\nmov byte ptr [rbp+0], 0\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "void __fastcall func0(unsigned __int8 *a1, _BYTE *a2)\n{\n _BYTE *v2; // rbp\n __int64 v3; // rbx\n const __int32_t **v4; // rax\n __int64 v5; // rdx\n\n v2 = a2;\n v3 = *a1;\n if ( (_BYTE)v3 )\n {\n v4 = __ctype_tolower_loc();\n v5 = 0LL;\n do\n {\n a2[v5++] = (*v4)[v3];\n v3 = a1[v5];\n }\n while ( (_BYTE)v3 );\n v2 = &a2[v5];\n }\n *v2 = 0;\n}", + "ida_strip_asm": "sub_1290:\nendbr64\npush r12\npush rbp\nmov rbp, rsi\npush rbx\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_12CA\nmov r12, rdi\ncall ___ctype_tolower_loc\nxor edx, edx\nnop dword ptr [rax+00h]\nloc_12B0:\nmov rcx, [rax]\nmov ecx, [rcx+rbx*4]\nmov [rbp+rdx+0], cl\nadd rdx, 1\nmovzx ebx, byte ptr [r12+rdx]\ntest bl, bl\njnz short loc_12B0\nadd rbp, rdx\nloc_12CA:\nmov byte ptr [rbp+0], 0\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "void __fastcall sub_1290(unsigned __int8 *a1, _BYTE *a2)\n{\n _BYTE *v2; // rbp\n __int64 v3; // rbx\n const __int32_t **v4; // rax\n __int64 v5; // rdx\n\n v2 = a2;\n v3 = *a1;\n if ( (_BYTE)v3 )\n {\n v4 = __ctype_tolower_loc();\n v5 = 0LL;\n do\n {\n a2[v5++] = (*v4)[v3];\n v3 = a1[v5];\n }\n while ( (_BYTE)v3 );\n v2 = &a2[v5];\n }\n *v2 = 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1290(unsigned char *a1, uint8_t *a2) {\n uint8_t *v2;\n long long v3;\n const __int32_t **v4;\n long long v5;\n v2 = a2;\n v3 = *a1;\n if ((uint8_t)v3) {\n v4 = __ctype_tolower_loc();\n v5 = 0LL;\n do {\n a2[v5++] = (*v4)[v3];\n v3 = a1[v5];\n } while ((uint8_t)v3);\n v2 = &a2[v5];\n }\n *v2 = 0;\n}", + "ida_pseudo_norm": "void func0(unsigned char *a1, uint8_t *a2) {\n uint8_t *v2;\n long long v3;\n const __int32_t **v4;\n long long v5;\n v2 = a2;\n v3 = *a1;\n if ((uint8_t)v3) {\n v4 = __ctype_tolower_loc();\n v5 = 0LL;\n do {\n a2[v5++] = (*v4)[v3];\n v3 = a1[v5];\n } while ((uint8_t)v3);\n v2 = &a2[v5];\n }\n *v2 = 0;\n}" + }, + { + "index": 478, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* str1) {\n static char result[100];\n int i, j = 0;\n for (i = 0; str1[i] != '\\0'; i++) {\n if (!islower(str1[i])) {\n result[j++] = str1[i];\n }\n }\n result[j] = '\\0';\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"PYTHon\"), \"PYTH\") == 0);\n\n assert(strcmp(func0(\"FInD\"), \"FID\") == 0);\n\n assert(strcmp(func0(\"STRinG\"), \"STRG\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmovl $0x0,-0x4(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 1204 \ncallq 1090 <__ctype_b_loc@plt>\nmov (%rax),%rax\nmov -0x8(%rbp),%edx\nmovslq %edx,%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rdx),%edx\nmovsbq %dl,%rdx\nadd %rdx,%rdx\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x200,%eax\ntest %eax,%eax\njne 1200 \nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x4(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x4(%rbp)\nmovzbl (%rcx),%edx\ncltq\nlea 0x2e43(%rip),%rcx\nmov %dl,(%rax,%rcx,1)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 11a9 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x2e1c(%rip),%rdx\nmovb $0x0,(%rax,%rdx,1)\nlea 0x2e11(%rip),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_4], 0\nmov [rbp+var_8], 0\njmp short loc_1204\nloc_11A9:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_8]\nmovsxd rcx, edx\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 200h\ntest eax, eax\njnz short loc_1200\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_4]\nlea edx, [rax+1]\nmov [rbp+var_4], edx\nmovzx edx, byte ptr [rcx]\ncdqe\nlea rcx, result_1\nmov [rax+rcx], dl\nloc_1200:\nadd [rbp+var_8], 1\nloc_1204:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_11A9\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, result_1\nmov byte ptr [rax+rdx], 0\nlea rax, result_1\nleave\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(__int64 a1)\n{\n int v1; // eax\n int i; // [rsp+18h] [rbp-8h]\n int v4; // [rsp+1Ch] [rbp-4h]\n\n v4 = 0;\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n {\n if ( ((*__ctype_b_loc())[*(char *)(i + a1)] & 0x200) == 0 )\n {\n v1 = v4++;\n result_1[v1] = *(_BYTE *)(i + a1);\n }\n }\n result_1[v4] = 0;\n return result_1;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_4], 0\nmov [rbp+var_8], 0\njmp short loc_1204\nloc_11A9:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_8]\nmovsxd rcx, edx\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 200h\ntest eax, eax\njnz short loc_1200\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_4]\nlea edx, [rax+1]\nmov [rbp+var_4], edx\nmovzx edx, byte ptr [rcx]\ncdqe\nlea rcx, unk_4040\nmov [rax+rcx], dl\nloc_1200:\nadd [rbp+var_8], 1\nloc_1204:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_11A9\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, unk_4040\nmov byte ptr [rax+rdx], 0\nlea rax, unk_4040\nleave\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1189(__int64 a1)\n{\n int v1; // eax\n int i; // [rsp+18h] [rbp-8h]\n int v4; // [rsp+1Ch] [rbp-4h]\n\n v4 = 0;\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n {\n if ( ((*__ctype_b_loc())[*(char *)(i + a1)] & 0x200) == 0 )\n {\n v1 = v4++;\n byte_4040[v1] = *(_BYTE *)(i + a1);\n }\n }\n byte_4040[v4] = 0;\n return byte_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1189(long long a1) {\n int v1;\n int i;\n int v4;\n v4 = 0;\n for (i = 0; *(uint8_t *)(i + a1); ++i) {\n if (((*__ctype_b_loc())[*(char *)(i + a1)] & 512) == 0) {\n v1 = v4++;\n byte_4040[v1] = *(uint8_t *)(i + a1);\n }\n }\n byte_4040[v4] = 0;\n return byte_4040;\n}", + "ida_pseudo_norm": "uint8_t *func0(long long a1) {\n int v1;\n int i;\n int v4;\n v4 = 0;\n for (i = 0; *(uint8_t *)(i + a1); ++i) {\n if (((*__ctype_b_loc())[*(char *)(i + a1)] & 512) == 0) {\n v1 = v4++;\n result_1[v1] = *(uint8_t *)(i + a1);\n }\n }\n result_1[v4] = 0;\n return result_1;\n}" + }, + { + "index": 478, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* str1) {\n static char result[100];\n int i, j = 0;\n for (i = 0; str1[i] != '\\0'; i++) {\n if (!islower(str1[i])) {\n result[j++] = str1[i];\n }\n }\n result[j] = '\\0';\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"PYTHon\"), \"PYTH\") == 0);\n\n assert(strcmp(func0(\"FInD\"), \"FID\") == 0);\n\n assert(strcmp(func0(\"STRinG\"), \"STRG\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmovzbl (%rdi),%ebx\ntest %bl,%bl\nje 11ba \nmov %rdi,%rbp\ncallq 1070 <__ctype_b_loc@plt>\nlea 0x1(%rbp),%rdi\nmov $0x0,%esi\nlea 0x2eae(%rip),%r8\njmp 11a0 \nadd $0x1,%rdi\nmovzbl -0x1(%rdi),%ebx\ntest %bl,%bl\nje 11bf \nmovsbq %bl,%rdx\nmov (%rax),%rcx\ntestb $0x2,0x1(%rcx,%rdx,2)\njne 1194 \nmovslq %esi,%rdx\nmov %bl,(%r8,%rdx,1)\nlea 0x1(%rsi),%esi\njmp 1194 \nmov $0x0,%esi\nlea 0x2e7a(%rip),%rax\nmovslq %esi,%rsi\nmovb $0x0,(%rax,%rsi,1)\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_11DA\nmov rbp, rdi\ncall ___ctype_b_loc\nlea rdi, [rbp+1]\nmov esi, 0\nlea r8, result_1\njmp short loc_11C0\nloc_11B4:\nadd rdi, 1\nmovzx ebx, byte ptr [rdi-1]\ntest bl, bl\njz short loc_11DF\nloc_11C0:\nmovsx rdx, bl\nmov rcx, [rax]\ntest byte ptr [rcx+rdx*2+1], 2\njnz short loc_11B4\nmovsxd rdx, esi\nmov [r8+rdx], bl\nlea esi, [rsi+1]\njmp short loc_11B4\nloc_11DA:\nmov esi, 0\nloc_11DF:\nlea rax, result_1\nmovsxd rsi, esi\nmov byte ptr [rax+rsi], 0\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(char *a1)\n{\n char v1; // bl\n const unsigned __int16 **v2; // rax\n char *v3; // rdi\n int v4; // esi\n _BYTE *result; // rax\n\n v1 = *a1;\n if ( *a1 )\n {\n v2 = __ctype_b_loc();\n v3 = a1 + 1;\n v4 = 0;\n do\n {\n if ( ((*v2)[v1] & 0x200) == 0 )\n result_1[v4++] = v1;\n v1 = *v3++;\n }\n while ( v1 );\n }\n else\n {\n v4 = 0;\n }\n result = result_1;\n result_1[v4] = 0;\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_11DA\nmov rbp, rdi\ncall ___ctype_b_loc\nlea rdi, [rbp+1]\nmov esi, 0\nlea r8, unk_4040\njmp short loc_11C0\nloc_11B4:\nadd rdi, 1\nmovzx ebx, byte ptr [rdi-1]\ntest bl, bl\njz short loc_11DF\nloc_11C0:\nmovsx rdx, bl\nmov rcx, [rax]\ntest byte ptr [rcx+rdx*2+1], 2\njnz short loc_11B4\nmovsxd rdx, esi\nmov [r8+rdx], bl\nlea esi, [rsi+1]\njmp short loc_11B4\nloc_11DA:\nmov esi, 0\nloc_11DF:\nlea rax, unk_4040\nmovsxd rsi, esi\nmov byte ptr [rax+rsi], 0\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1189(char *a1)\n{\n char v1; // bl\n const unsigned __int16 **v2; // rax\n char *v3; // rdi\n int v4; // esi\n _BYTE *result; // rax\n\n v1 = *a1;\n if ( *a1 )\n {\n v2 = __ctype_b_loc();\n v3 = a1 + 1;\n v4 = 0;\n do\n {\n if ( ((*v2)[v1] & 0x200) == 0 )\n byte_4040[v4++] = v1;\n v1 = *v3++;\n }\n while ( v1 );\n }\n else\n {\n v4 = 0;\n }\n result = byte_4040;\n byte_4040[v4] = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1189(char *a1) {\n char v1;\n const unsigned short **v2;\n char *v3;\n int v4;\n uint8_t *result;\n v1 = *a1;\n if (*a1) {\n v2 = __ctype_b_loc();\n v3 = a1 + 1;\n v4 = 0;\n do {\n if (((*v2)[v1] & 512) == 0) byte_4040[v4++] = v1;\n v1 = *v3++;\n } while (v1);\n } else {\n v4 = 0;\n }\n result = byte_4040;\n byte_4040[v4] = 0;\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(char *a1) {\n char v1;\n const unsigned short **v2;\n char *v3;\n int v4;\n uint8_t *result;\n v1 = *a1;\n if (*a1) {\n v2 = __ctype_b_loc();\n v3 = a1 + 1;\n v4 = 0;\n do {\n if (((*v2)[v1] & 512) == 0) result_1[v4++] = v1;\n v1 = *v3++;\n } while (v1);\n } else {\n v4 = 0;\n }\n result = result_1;\n result_1[v4] = 0;\n return result;\n}" + }, + { + "index": 478, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* str1) {\n static char result[100];\n int i, j = 0;\n for (i = 0; str1[i] != '\\0'; i++) {\n if (!islower(str1[i])) {\n result[j++] = str1[i];\n }\n }\n result[j] = '\\0';\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"PYTHon\"), \"PYTH\") == 0);\n\n assert(strcmp(func0(\"FInD\"), \"FID\") == 0);\n\n assert(strcmp(func0(\"STRinG\"), \"STRG\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmovzbl (%rdi),%ebx\ntest %bl,%bl\nje 12c0 \nmov %rdi,%rbp\ncallq 1070 <__ctype_b_loc@plt>\nlea 0x1(%rbp),%rdi\nxor %esi,%esi\nlea 0x2dca(%rip),%r8\nnopw %cs:0x0(%rax,%rax,1)\nmov (%rax),%rcx\nmovsbq %bl,%rdx\ntestb $0x2,0x1(%rcx,%rdx,2)\njne 1298 \nmovslq %esi,%rdx\nadd $0x1,%esi\nmov %bl,(%r8,%rdx,1)\nmovzbl (%rdi),%ebx\nadd $0x1,%rdi\ntest %bl,%bl\njne 1280 \nmovslq %esi,%rsi\nlea 0x2d93(%rip),%rax\nmovb $0x0,(%r8,%rsi,1)\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopl 0x0(%rax)\nxor %esi,%esi\nlea 0x2d77(%rip),%r8\njmp 12a3 \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_12C8\nmov rbp, rdi\ncall ___ctype_b_loc\nlea rdi, [rbp+1]\nxor esi, esi\nlea r8, result_1\nnop word ptr [rax+rax+00000000h]\nloc_1290:\nmov rcx, [rax]\nmovsx rdx, bl\ntest byte ptr [rcx+rdx*2+1], 2\njnz short loc_12A8\nmovsxd rdx, esi\nadd esi, 1\nmov [r8+rdx], bl\nloc_12A8:\nmovzx ebx, byte ptr [rdi]\nadd rdi, 1\ntest bl, bl\njnz short loc_1290\nloc_12B3:\nmovsxd rsi, esi\nmov rax, r8\nmov byte ptr [r8+rsi], 0\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_12C8:\nxor esi, esi\nlea r8, result_1\njmp short loc_12B3", + "ida_pseudo": "_BYTE *__fastcall func0(char *a1)\n{\n char v1; // bl\n const unsigned __int16 **v2; // rax\n char *v3; // rdi\n int v4; // esi\n __int64 v5; // rdx\n _BYTE *result; // rax\n\n v1 = *a1;\n if ( *a1 )\n {\n v2 = __ctype_b_loc();\n v3 = a1 + 1;\n v4 = 0;\n do\n {\n if ( ((*v2)[v1] & 0x200) == 0 )\n {\n v5 = v4++;\n result_1[v5] = v1;\n }\n v1 = *v3++;\n }\n while ( v1 );\n }\n else\n {\n v4 = 0;\n }\n result = result_1;\n result_1[v4] = 0;\n return result;\n}", + "ida_strip_asm": "sub_1260:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_12C8\nmov rbp, rdi\ncall ___ctype_b_loc\nlea rdi, [rbp+1]\nxor esi, esi\nlea r8, unk_4040\nnop word ptr [rax+rax+00000000h]\nloc_1290:\nmov rcx, [rax]\nmovsx rdx, bl\ntest byte ptr [rcx+rdx*2+1], 2\njnz short loc_12A8\nmovsxd rdx, esi\nadd esi, 1\nmov [r8+rdx], bl\nloc_12A8:\nmovzx ebx, byte ptr [rdi]\nadd rdi, 1\ntest bl, bl\njnz short loc_1290\nloc_12B3:\nmovsxd rsi, esi\nmov rax, r8\nmov byte ptr [r8+rsi], 0\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_12C8:\nxor esi, esi\nlea r8, unk_4040\njmp short loc_12B3", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1260(char *a1)\n{\n char v1; // bl\n const unsigned __int16 **v2; // rax\n char *v3; // rdi\n int v4; // esi\n __int64 v5; // rdx\n _BYTE *result; // rax\n\n v1 = *a1;\n if ( *a1 )\n {\n v2 = __ctype_b_loc();\n v3 = a1 + 1;\n v4 = 0;\n do\n {\n if ( ((*v2)[v1] & 0x200) == 0 )\n {\n v5 = v4++;\n byte_4040[v5] = v1;\n }\n v1 = *v3++;\n }\n while ( v1 );\n }\n else\n {\n v4 = 0;\n }\n result = byte_4040;\n byte_4040[v4] = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1260(char *a1) {\n char v1;\n const unsigned short **v2;\n char *v3;\n int v4;\n long long v5;\n uint8_t *result;\n v1 = *a1;\n if (*a1) {\n v2 = __ctype_b_loc();\n v3 = a1 + 1;\n v4 = 0;\n do {\n if (((*v2)[v1] & 512) == 0) {\n v5 = v4++;\n byte_4040[v5] = v1;\n }\n v1 = *v3++;\n } while (v1);\n } else {\n v4 = 0;\n }\n result = byte_4040;\n byte_4040[v4] = 0;\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(char *a1) {\n char v1;\n const unsigned short **v2;\n char *v3;\n int v4;\n long long v5;\n uint8_t *result;\n v1 = *a1;\n if (*a1) {\n v2 = __ctype_b_loc();\n v3 = a1 + 1;\n v4 = 0;\n do {\n if (((*v2)[v1] & 512) == 0) {\n v5 = v4++;\n result_1[v5] = v1;\n }\n v1 = *v3++;\n } while (v1);\n } else {\n v4 = 0;\n }\n result = result_1;\n result_1[v4] = 0;\n return result;\n}" + }, + { + "index": 478, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* str1) {\n static char result[100];\n int i, j = 0;\n for (i = 0; str1[i] != '\\0'; i++) {\n if (!islower(str1[i])) {\n result[j++] = str1[i];\n }\n }\n result[j] = '\\0';\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"PYTHon\"), \"PYTH\") == 0);\n\n assert(strcmp(func0(\"FInD\"), \"FID\") == 0);\n\n assert(strcmp(func0(\"STRinG\"), \"STRG\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmovzbl (%rdi),%ebx\ntest %bl,%bl\nje 12d8 \nmov %rdi,%rbp\ncallq 1070 <__ctype_b_loc@plt>\nlea 0x1(%rbp),%rdi\nxor %edx,%edx\nlea 0x2dca(%rip),%r8\nmov (%rax),%rsi\nnopl 0x0(%rax)\nmovsbq %bl,%rcx\ntestb $0x2,0x1(%rsi,%rcx,2)\njne 12af \nadd $0x1,%rdi\nmov %bl,(%r8,%rdx,1)\nlea 0x1(%rdx),%ecx\nmovzbl -0x1(%rdi),%ebx\ntest %bl,%bl\nje 12bc \nmov (%rax),%rsi\nmovslq %ecx,%rdx\nmovsbq %bl,%rcx\ntestb $0x2,0x1(%rsi,%rcx,2)\nje 128b \nmovzbl (%rdi),%ebx\nadd $0x1,%rdi\ntest %bl,%bl\njne 1280 \nmov %edx,%ecx\nmovslq %ecx,%rcx\nlea 0x2d7a(%rip),%rax\nmovb $0x0,(%r8,%rcx,1)\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopw 0x0(%rax,%rax,1)\nxor %ecx,%ecx\nlea 0x2d5f(%rip),%r8\njmp 12bc \nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_12E0\nmov rbp, rdi\ncall ___ctype_b_loc\nlea rdi, [rbp+1]\nxor edx, edx\nlea r8, result_1\nmov rsi, [rax]\nnop dword ptr [rax+00000000h]\nloc_1290:\nmovsx rcx, bl\ntest byte ptr [rsi+rcx*2+1], 2\njnz short loc_12BF\nloc_129B:\nadd rdi, 1\nmov [r8+rdx], bl\nlea ecx, [rdx+1]\nmovzx ebx, byte ptr [rdi-1]\nmovsxd rdx, ecx\ntest bl, bl\njz short loc_12CA\nmov rsi, [rax]\nmovsx rcx, bl\ntest byte ptr [rsi+rcx*2+1], 2\njz short loc_129B\nloc_12BF:\nmovzx ebx, byte ptr [rdi]\nadd rdi, 1\ntest bl, bl\njnz short loc_1290\nloc_12CA:\nmov byte ptr [r8+rdx], 0\nadd rsp, 8\nmov rax, r8\npop rbx\npop rbp\nretn\nloc_12E0:\nlea r8, result_1\nxor edx, edx\nmov byte ptr [r8+rdx], 0\nadd rsp, 8\nmov rax, r8\npop rbx\npop rbp\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(char *a1)\n{\n char v1; // bl\n const unsigned __int16 **v2; // rax\n char *v3; // rdi\n __int64 v4; // rdx\n const unsigned __int16 *v5; // rsi\n\n v1 = *a1;\n if ( *a1 )\n {\n v2 = __ctype_b_loc();\n v3 = a1 + 1;\n v4 = 0LL;\n v5 = *v2;\n while ( (v5[v1] & 0x200) != 0 )\n {\nLABEL_6:\n v1 = *v3++;\n if ( !v1 )\n goto LABEL_7;\n }\n while ( 1 )\n {\n ++v3;\n result_1[v4] = v1;\n v1 = *(v3 - 1);\n v4 = (int)v4 + 1;\n if ( !v1 )\n break;\n v5 = *v2;\n if ( ((*v2)[v1] & 0x200) != 0 )\n goto LABEL_6;\n }\nLABEL_7:\n result_1[v4] = 0;\n return result_1;\n }\n else\n {\n result_1[0] = 0;\n return result_1;\n }\n}", + "ida_strip_asm": "sub_1260:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_12E0\nmov rbp, rdi\ncall ___ctype_b_loc\nlea rdi, [rbp+1]\nxor edx, edx\nlea r8, unk_4040\nmov rsi, [rax]\nnop dword ptr [rax+00000000h]\nloc_1290:\nmovsx rcx, bl\ntest byte ptr [rsi+rcx*2+1], 2\njnz short loc_12BF\nloc_129B:\nadd rdi, 1\nmov [r8+rdx], bl\nlea ecx, [rdx+1]\nmovzx ebx, byte ptr [rdi-1]\nmovsxd rdx, ecx\ntest bl, bl\njz short loc_12CA\nmov rsi, [rax]\nmovsx rcx, bl\ntest byte ptr [rsi+rcx*2+1], 2\njz short loc_129B\nloc_12BF:\nmovzx ebx, byte ptr [rdi]\nadd rdi, 1\ntest bl, bl\njnz short loc_1290\nloc_12CA:\nmov byte ptr [r8+rdx], 0\nadd rsp, 8\nmov rax, r8\npop rbx\npop rbp\nretn\nloc_12E0:\nlea r8, unk_4040\nxor edx, edx\nmov byte ptr [r8+rdx], 0\nadd rsp, 8\nmov rax, r8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1260(char *a1)\n{\n char v1; // bl\n const unsigned __int16 **v2; // rax\n char *v3; // rdi\n __int64 v4; // rdx\n const unsigned __int16 *v5; // rsi\n\n v1 = *a1;\n if ( *a1 )\n {\n v2 = __ctype_b_loc();\n v3 = a1 + 1;\n v4 = 0LL;\n v5 = *v2;\n while ( (v5[v1] & 0x200) != 0 )\n {\nLABEL_6:\n v1 = *v3++;\n if ( !v1 )\n goto LABEL_7;\n }\n while ( 1 )\n {\n ++v3;\n byte_4040[v4] = v1;\n v1 = *(v3 - 1);\n v4 = (int)v4 + 1;\n if ( !v1 )\n break;\n v5 = *v2;\n if ( ((*v2)[v1] & 0x200) != 0 )\n goto LABEL_6;\n }\nLABEL_7:\n byte_4040[v4] = 0;\n return byte_4040;\n }\n else\n {\n byte_4040[0] = 0;\n return byte_4040;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1260(char *a1) {\n char v1;\n const unsigned short **v2;\n char *v3;\n long long v4;\n const unsigned short *v5;\n v1 = *a1;\n if (*a1) {\n v2 = __ctype_b_loc();\n v3 = a1 + 1;\n v4 = 0LL;\n v5 = *v2;\n while ((v5[v1] & 512) != 0) {\n LABEL_6:\n v1 = *v3++;\n if (!v1) goto LABEL_7;\n }\n while (1) {\n ++v3;\n byte_4040[v4] = v1;\n v1 = *(v3 - 1);\n v4 = (int)v4 + 1;\n if (!v1) break;\n v5 = *v2;\n if (((*v2)[v1] & 512) != 0) goto LABEL_6;\n }\n LABEL_7:\n byte_4040[v4] = 0;\n return byte_4040;\n } else {\n byte_4040[0] = 0;\n return byte_4040;\n }\n}", + "ida_pseudo_norm": "uint8_t *func0(char *a1) {\n char v1;\n const unsigned short **v2;\n char *v3;\n long long v4;\n const unsigned short *v5;\n v1 = *a1;\n if (*a1) {\n v2 = __ctype_b_loc();\n v3 = a1 + 1;\n v4 = 0LL;\n v5 = *v2;\n while ((v5[v1] & 512) != 0) {\n LABEL_6:\n v1 = *v3++;\n if (!v1) goto LABEL_7;\n }\n while (1) {\n ++v3;\n result_1[v4] = v1;\n v1 = *(v3 - 1);\n v4 = (int)v4 + 1;\n if (!v1) break;\n v5 = *v2;\n if (((*v2)[v1] & 512) != 0) goto LABEL_6;\n }\n LABEL_7:\n result_1[v4] = 0;\n return result_1;\n } else {\n result_1[0] = 0;\n return result_1;\n }\n}" + }, + { + "index": 479, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n while (n >= 10) {\n n = n / 10;\n }\n return n;\n}", + "test": "int main() {\n\n assert(func0(123) == 1);\n\n assert(func0(456) == 4);\n\n assert(func0(12) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\njmp 1174 \nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nimul $0x66666667,%rdx,%rdx\nshr $0x20,%rdx\nsar $0x2,%edx\nsar $0x1f,%eax\nsub %eax,%edx\nmov %edx,%eax\nmov %eax,-0x4(%rbp)\ncmpl $0x9,-0x4(%rbp)\njg 1156 \nmov -0x4(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\njmp short loc_1174\nloc_1156:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_4], eax\nloc_1174:\ncmp [rbp+var_4], 9\njg short loc_1156\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n while ( a1 > 9 )\n a1 /= 10;\n return (unsigned int)a1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\njmp short loc_1174\nloc_1156:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_4], eax\nloc_1174:\ncmp [rbp+var_4], 9\njg short loc_1156\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n while ( a1 > 9 )\n a1 /= 10;\n return (unsigned int)a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n while (a1 > 9) a1 /= 10;\n return (unsigned int)a1;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n while (a1 > 9) a1 /= 10;\n return (unsigned int)a1;\n}" + }, + { + "index": 480, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "char func0(const char* str1) {\n int ASCII_SIZE = 256;\n int ctr[256] = {0};\n int max = -1;\n char ch = '\\0';\n int length = strlen(str1);\n for (int i = 0; i < length; i++) {\n ctr[(int)str1[i]]++;\n }\n for (int i = 0; i < length; i++) {\n if (max < ctr[(int)str1[i]]) {\n max = ctr[(int)str1[i]];\n ch = str1[i];\n }\n }\n return ch;\n}", + "test": "int main() {\n\n assert(func0(\"data\") == 'a');\n\n assert(func0(\"create\") == 'e');\n\n assert(func0(\"brilliant girl\") == 'i');\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x440,%rsp\nmov %rdi,-0x438(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovl $0x100,-0x418(%rbp)\nlea -0x410(%rbp),%rdx\nmov $0x0,%eax\nmov $0x80,%ecx\nmov %rdx,%rdi\nrep stos %rax,%es:(%rdi)\nmovl $0xffffffff,-0x424(%rbp)\nmovb $0x0,-0x425(%rbp)\nmov -0x438(%rbp),%rax\nmov %rax,%rdi\ncallq 1070 \nmov %eax,-0x414(%rbp)\nmovl $0x0,-0x420(%rbp)\njmp 1237 \nmov -0x420(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x438(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmovsbl %al,%eax\nmovslq %eax,%rdx\nmov -0x410(%rbp,%rdx,4),%edx\nadd $0x1,%edx\ncltq\nmov %edx,-0x410(%rbp,%rax,4)\naddl $0x1,-0x420(%rbp)\nmov -0x420(%rbp),%eax\ncmp -0x414(%rbp),%eax\njl 1201 \nmovl $0x0,-0x41c(%rbp)\njmp 12c6 \nmov -0x41c(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x438(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmovsbl %al,%eax\ncltq\nmov -0x410(%rbp,%rax,4),%eax\ncmp %eax,-0x424(%rbp)\njge 12bf \nmov -0x41c(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x438(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmovsbl %al,%eax\ncltq\nmov -0x410(%rbp,%rax,4),%eax\nmov %eax,-0x424(%rbp)\nmov -0x41c(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x438(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmov %al,-0x425(%rbp)\naddl $0x1,-0x41c(%rbp)\nmov -0x41c(%rbp),%eax\ncmp -0x414(%rbp),%eax\njl 1251 \nmovzbl -0x425(%rbp),%eax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 12f3 \ncallq 1080 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 440h\nmov [rbp+s], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_418], 100h\nlea rdx, [rbp+var_410]\nmov eax, 0\nmov ecx, 80h\nmov rdi, rdx\nrep stosq\nmov [rbp+var_424], 0FFFFFFFFh\nmov [rbp+var_425], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_414], eax\nmov [rbp+var_420], 0\njmp short loc_1237\nloc_1201:\nmov eax, [rbp+var_420]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nmovsxd rdx, eax\nmov edx, [rbp+rdx*4+var_410]\nadd edx, 1\ncdqe\nmov [rbp+rax*4+var_410], edx\nadd [rbp+var_420], 1\nloc_1237:\nmov eax, [rbp+var_420]\ncmp eax, [rbp+var_414]\njl short loc_1201\nmov [rbp+var_41C], 0\njmp short loc_12C6\nloc_1251:\nmov eax, [rbp+var_41C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\ncdqe\nmov eax, [rbp+rax*4+var_410]\ncmp [rbp+var_424], eax\njge short loc_12BF\nmov eax, [rbp+var_41C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\ncdqe\nmov eax, [rbp+rax*4+var_410]\nmov [rbp+var_424], eax\nmov eax, [rbp+var_41C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_425], al\nloc_12BF:\nadd [rbp+var_41C], 1\nloc_12C6:\nmov eax, [rbp+var_41C]\ncmp eax, [rbp+var_414]\njl loc_1251\nmovzx eax, [rbp+var_425]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12F3\ncall ___stack_chk_fail\nlocret_12F3:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n unsigned __int8 v2; // [rsp+1Bh] [rbp-425h]\n int v3; // [rsp+1Ch] [rbp-424h]\n int i; // [rsp+20h] [rbp-420h]\n int j; // [rsp+24h] [rbp-41Ch]\n int v6; // [rsp+2Ch] [rbp-414h]\n _DWORD v7[258]; // [rsp+30h] [rbp-410h] BYREF\n unsigned __int64 v8; // [rsp+438h] [rbp-8h]\n\n v8 = __readfsqword(0x28u);\n memset(v7, 0, 0x400uLL);\n v3 = -1;\n v2 = 0;\n v6 = strlen(a1);\n for ( i = 0; i < v6; ++i )\n ++v7[a1[i]];\n for ( j = 0; j < v6; ++j )\n {\n if ( v3 < v7[a1[j]] )\n {\n v3 = v7[a1[j]];\n v2 = a1[j];\n }\n }\n return v2;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 440h\nmov [rbp+s], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_418], 100h\nlea rdx, [rbp+var_410]\nmov eax, 0\nmov ecx, 80h\nmov rdi, rdx\nrep stosq\nmov [rbp+var_424], 0FFFFFFFFh\nmov [rbp+var_425], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_414], eax\nmov [rbp+var_420], 0\njmp short loc_1237\nloc_1201:\nmov eax, [rbp+var_420]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nmovsxd rdx, eax\nmov edx, [rbp+rdx*4+var_410]\nadd edx, 1\ncdqe\nmov [rbp+rax*4+var_410], edx\nadd [rbp+var_420], 1\nloc_1237:\nmov eax, [rbp+var_420]\ncmp eax, [rbp+var_414]\njl short loc_1201\nmov [rbp+var_41C], 0\njmp short loc_12C6\nloc_1251:\nmov eax, [rbp+var_41C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\ncdqe\nmov eax, [rbp+rax*4+var_410]\ncmp [rbp+var_424], eax\njge short loc_12BF\nmov eax, [rbp+var_41C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\ncdqe\nmov eax, [rbp+rax*4+var_410]\nmov [rbp+var_424], eax\nmov eax, [rbp+var_41C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_425], al\nloc_12BF:\nadd [rbp+var_41C], 1\nloc_12C6:\nmov eax, [rbp+var_41C]\ncmp eax, [rbp+var_414]\njl loc_1251\nmovzx eax, [rbp+var_425]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12F3\ncall ___stack_chk_fail\nlocret_12F3:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(const char *a1)\n{\n unsigned __int8 v2; // [rsp+1Bh] [rbp-425h]\n int v3; // [rsp+1Ch] [rbp-424h]\n int i; // [rsp+20h] [rbp-420h]\n int j; // [rsp+24h] [rbp-41Ch]\n int v6; // [rsp+2Ch] [rbp-414h]\n _DWORD v7[258]; // [rsp+30h] [rbp-410h] BYREF\n unsigned __int64 v8; // [rsp+438h] [rbp-8h]\n\n v8 = __readfsqword(0x28u);\n memset(v7, 0, 0x400uLL);\n v3 = -1;\n v2 = 0;\n v6 = strlen(a1);\n for ( i = 0; i < v6; ++i )\n ++v7[a1[i]];\n for ( j = 0; j < v6; ++j )\n {\n if ( v3 < v7[a1[j]] )\n {\n v3 = v7[a1[j]];\n v2 = a1[j];\n }\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(const char *a1) {\n unsigned char v2;\n int v3;\n int i;\n int j;\n int v6;\n uint32_t v7[258];\n unsigned long long v8;\n v8 = __readfsqword(40u);\n memset(v7, 0, 1024uLL);\n v3 = -1;\n v2 = 0;\n v6 = strlen(a1);\n for (i = 0; i < v6; ++i) ++v7[a1[i]];\n for (j = 0; j < v6; ++j) {\n if (v3 < v7[a1[j]]) {\n v3 = v7[a1[j]];\n v2 = a1[j];\n }\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n unsigned char v2;\n int v3;\n int i;\n int j;\n int v6;\n uint32_t v7[258];\n unsigned long long v8;\n v8 = __readfsqword(40u);\n memset(v7, 0, 1024uLL);\n v3 = -1;\n v2 = 0;\n v6 = strlen(a1);\n for (i = 0; i < v6; ++i) ++v7[a1[i]];\n for (j = 0; j < v6; ++j) {\n if (v3 < v7[a1[j]]) {\n v3 = v7[a1[j]];\n v2 = a1[j];\n }\n }\n return v2;\n}" + }, + { + "index": 480, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "char func0(const char* str1) {\n int ASCII_SIZE = 256;\n int ctr[256] = {0};\n int max = -1;\n char ch = '\\0';\n int length = strlen(str1);\n for (int i = 0; i < length; i++) {\n ctr[(int)str1[i]]++;\n }\n for (int i = 0; i < length; i++) {\n if (max < ctr[(int)str1[i]]) {\n max = ctr[(int)str1[i]];\n ch = str1[i];\n }\n }\n return ch;\n}", + "test": "int main() {\n\n assert(func0(\"data\") == 'a');\n\n assert(func0(\"create\") == 'e');\n\n assert(func0(\"brilliant girl\") == 'i');\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x418,%rsp\nmov %rdi,%rdx\nmov %fs:0x28,%rax\nmov %rax,0x408(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nmov $0x80,%ecx\nrep stos %rax,%es:(%rdi)\nmov $0xffffffffffffffff,%rcx\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nnot %rcx\nsub $0x1,%rcx\ntest %ecx,%ecx\njle 11f6 \nmov %rdx,%rax\nlea -0x1(%rcx),%ecx\nlea 0x1(%rdx,%rcx,1),%rsi\nmov %rdx,%rdi\nmovsbq (%rdi),%rdx\naddl $0x1,(%rsp,%rdx,4)\nadd $0x1,%rdi\ncmp %rsi,%rdi\njne 11ba \nmov $0x0,%r8d\nmov $0xffffffff,%edi\njmp 11e1 \nadd $0x1,%rax\ncmp %rsi,%rax\nje 11fc \nmovzbl (%rax),%ecx\nmovsbq %cl,%rdx\nmov (%rsp,%rdx,4),%edx\ncmp %edi,%edx\njle 11d8 \nmov %ecx,%r8d\nmov %edx,%edi\njmp 11d8 \nmov $0x0,%r8d\nmov 0x408(%rsp),%rax\nxor %fs:0x28,%rax\njne 121a \nmov %r8d,%eax\nadd $0x418,%rsp\nretq\ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbx\nsub rsp, 410h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+418h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nmov ecx, 80h\nrep stosq\nmov rdi, rbx; s\ncall _strlen\ntest eax, eax\njle short loc_120C\nmov rdx, rbx\nlea eax, [rax-1]\nlea rsi, [rbx+rax+1]\nmov rax, rbx\nloc_11D0:\nmovsx rcx, byte ptr [rax]\nadd [rsp+rcx*4+418h+var_418], 1\nadd rax, 1\ncmp rax, rsi\njnz short loc_11D0\nmov r8d, 0\nmov edi, 0FFFFFFFFh\njmp short loc_11F7\nloc_11EE:\nadd rdx, 1\ncmp rdx, rsi\njz short loc_1212\nloc_11F7:\nmovzx ecx, byte ptr [rdx]\nmovsx rax, cl\nmov eax, [rsp+rax*4+418h+var_418]\ncmp eax, edi\njle short loc_11EE\nmov r8d, ecx\nmov edi, eax\njmp short loc_11EE\nloc_120C:\nmov r8d, 0\nloc_1212:\nmov rax, [rsp+418h+var_10]\nsub rax, fs:28h\njnz short loc_1231\nmov eax, r8d\nadd rsp, 410h\npop rbx\nretn\nloc_1231:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(char *s)\n{\n int v1; // eax\n char *v2; // rdx\n char *v3; // rsi\n char *v4; // rax\n unsigned int v5; // r8d\n int v6; // edi\n _DWORD v8[258]; // [rsp+0h] [rbp-418h] BYREF\n unsigned __int64 v9; // [rsp+408h] [rbp-10h]\n\n v9 = __readfsqword(0x28u);\n memset(v8, 0, 0x400uLL);\n v1 = strlen(s);\n if ( v1 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = s;\n v3 = &s[v1 - 1 + 1];\n v4 = s;\n do\n ++v8[*v4++];\n while ( v4 != v3 );\n v5 = 0;\n v6 = -1;\n do\n {\n if ( v8[*v2] > v6 )\n {\n v5 = (unsigned __int8)*v2;\n v6 = v8[*v2];\n }\n ++v2;\n }\n while ( v2 != v3 );\n }\n return v5;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbx\nsub rsp, 410h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+418h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nmov ecx, 80h\nrep stosq\nmov rdi, rbx; s\ncall _strlen\ntest eax, eax\njle short loc_120C\nmov rdx, rbx\nlea eax, [rax-1]\nlea rsi, [rbx+rax+1]\nmov rax, rbx\nloc_11D0:\nmovsx rcx, byte ptr [rax]\nadd [rsp+rcx*4+418h+var_418], 1\nadd rax, 1\ncmp rax, rsi\njnz short loc_11D0\nmov r8d, 0\nmov edi, 0FFFFFFFFh\njmp short loc_11F7\nloc_11EE:\nadd rdx, 1\ncmp rdx, rsi\njz short loc_1212\nloc_11F7:\nmovzx ecx, byte ptr [rdx]\nmovsx rax, cl\nmov eax, [rsp+rax*4+418h+var_418]\ncmp eax, edi\njle short loc_11EE\nmov r8d, ecx\nmov edi, eax\njmp short loc_11EE\nloc_120C:\nmov r8d, 0\nloc_1212:\nmov rax, [rsp+418h+var_10]\nsub rax, fs:28h\njnz short loc_1231\nmov eax, r8d\nadd rsp, 410h\npop rbx\nretn\nloc_1231:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(char *s)\n{\n int v1; // eax\n char *v2; // rdx\n char *v3; // rsi\n char *v4; // rax\n unsigned int v5; // r8d\n int v6; // edi\n _DWORD v8[258]; // [rsp+0h] [rbp-418h] BYREF\n unsigned __int64 v9; // [rsp+408h] [rbp-10h]\n\n v9 = __readfsqword(0x28u);\n memset(v8, 0, 0x400uLL);\n v1 = strlen(s);\n if ( v1 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = s;\n v3 = &s[v1 - 1 + 1];\n v4 = s;\n do\n ++v8[*v4++];\n while ( v4 != v3 );\n v5 = 0;\n v6 = -1;\n do\n {\n if ( v8[*v2] > v6 )\n {\n v5 = (unsigned __int8)*v2;\n v6 = v8[*v2];\n }\n ++v2;\n }\n while ( v2 != v3 );\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(char *s) {\n int v1;\n char *v2;\n char *v3;\n char *v4;\n unsigned int v5;\n int v6;\n uint32_t v8[258];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n memset(v8, 0, 1024uLL);\n v1 = strlen(s);\n if (v1 <= 0) {\n return 0;\n } else {\n v2 = s;\n v3 = &s[v1 - 1 + 1];\n v4 = s;\n do\n ++v8[*v4++];\n while (v4 != v3);\n v5 = 0;\n v6 = -1;\n do {\n if (v8[*v2] > v6) {\n v5 = (unsigned char)*v2;\n v6 = v8[*v2];\n }\n ++v2;\n } while (v2 != v3);\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(char *s) {\n int v1;\n char *v2;\n char *v3;\n char *v4;\n unsigned int v5;\n int v6;\n uint32_t v8[258];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n memset(v8, 0, 1024uLL);\n v1 = strlen(s);\n if (v1 <= 0) {\n return 0;\n } else {\n v2 = s;\n v3 = &s[v1 - 1 + 1];\n v4 = s;\n do\n ++v8[*v4++];\n while (v4 != v3);\n v5 = 0;\n v6 = -1;\n do {\n if (v8[*v2] > v6) {\n v5 = (unsigned char)*v2;\n v6 = v8[*v2];\n }\n ++v2;\n } while (v2 != v3);\n }\n return v5;\n}" + }, + { + "index": 480, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "char func0(const char* str1) {\n int ASCII_SIZE = 256;\n int ctr[256] = {0};\n int max = -1;\n char ch = '\\0';\n int length = strlen(str1);\n for (int i = 0; i < length; i++) {\n ctr[(int)str1[i]]++;\n }\n for (int i = 0; i < length; i++) {\n if (max < ctr[(int)str1[i]]) {\n max = ctr[(int)str1[i]];\n ch = str1[i];\n }\n }\n return ch;\n}", + "test": "int main() {\n\n assert(func0(\"data\") == 'a');\n\n assert(func0(\"create\") == 'e');\n\n assert(func0(\"brilliant girl\") == 'i');\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov $0x80,%ecx\nmov %rdi,%rbx\nsub $0x410,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x408(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nrep stos %rax,%es:(%rdi)\nmov %rbx,%rdi\ncallq 1070 \ntest %eax,%eax\njle 12e0 \nsub $0x1,%eax\nmov %rbx,%rdi\nlea 0x1(%rbx,%rax,1),%rcx\nmov %rbx,%rax\nnopw 0x0(%rax,%rax,1)\nmovsbq (%rax),%rdx\nadd $0x1,%rax\naddl $0x1,(%rsp,%rdx,4)\ncmp %rcx,%rax\njne 1280 \nxor %r8d,%r8d\nmov $0xffffffff,%esi\nnopl 0x0(%rax)\nmovsbq (%rdi),%rax\nmov %rax,%rdx\nmov (%rsp,%rax,4),%eax\ncmp %esi,%eax\njle 12b3 \nmov %edx,%r8d\nmov %eax,%esi\nadd $0x1,%rdi\ncmp %rcx,%rdi\njne 12a0 \nmov 0x408(%rsp),%rax\nxor %fs:0x28,%rax\njne 12e5 \nadd $0x410,%rsp\nmov %r8d,%eax\npop %rbx\nretq\nnopl 0x0(%rax,%rax,1)\nxor %r8d,%r8d\njmp 12bc \ncallq 1080 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov ecx, 80h\nmov rbx, rdi\nsub rsp, 410h\nmov rax, fs:28h\nmov [rsp+418h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\nmov rdi, rbx; s\ncall _strlen\ntest eax, eax\njle short loc_12E0\nsub eax, 1\nmov rdi, rbx\nlea rcx, [rbx+rax+1]\nmov rax, rbx\nnop word ptr [rax+rax+00000000h]\nloc_1280:\nmovsx rdx, byte ptr [rax]\nadd rax, 1\nadd [rsp+rdx*4+418h+var_418], 1\ncmp rax, rcx\njnz short loc_1280\nxor r8d, r8d\nmov esi, 0FFFFFFFFh\nnop dword ptr [rax+00000000h]\nloc_12A0:\nmovsx rax, byte ptr [rdi]\nmov rdx, rax\nmov eax, [rsp+rax*4+418h+var_418]\ncmp eax, esi\njle short loc_12B3\nmov r8d, edx\nmov esi, eax\nloc_12B3:\nadd rdi, 1\ncmp rdi, rcx\njnz short loc_12A0\nloc_12BC:\nmov rax, [rsp+418h+var_10]\nsub rax, fs:28h\njnz short loc_12E5\nadd rsp, 410h\nmov eax, r8d\npop rbx\nretn\nloc_12E0:\nxor r8d, r8d\njmp short loc_12BC\nloc_12E5:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(char *s)\n{\n int v1; // eax\n char *v2; // rcx\n char *v3; // rax\n __int64 v4; // rdx\n unsigned int v5; // r8d\n int v6; // esi\n __int64 v7; // rdx\n _DWORD v9[258]; // [rsp+0h] [rbp-418h] BYREF\n unsigned __int64 v10; // [rsp+408h] [rbp-10h]\n\n v10 = __readfsqword(0x28u);\n memset(v9, 0, 0x400uLL);\n v1 = strlen(s);\n if ( v1 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = &s[v1 - 1 + 1];\n v3 = s;\n do\n {\n v4 = *v3++;\n ++v9[v4];\n }\n while ( v3 != v2 );\n v5 = 0;\n v6 = -1;\n do\n {\n v7 = *s;\n if ( v9[v7] > v6 )\n {\n v5 = *s;\n v6 = v9[v7];\n }\n ++s;\n }\n while ( s != v2 );\n }\n return v5;\n}", + "ida_strip_asm": "sub_1230:\nendbr64\npush rbx\nmov ecx, 80h\nmov rbx, rdi\nsub rsp, 410h\nmov rax, fs:28h\nmov [rsp+418h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\nmov rdi, rbx; s\ncall _strlen\ntest eax, eax\njle short loc_12E0\nsub eax, 1\nmov rdi, rbx\nlea rcx, [rbx+rax+1]\nmov rax, rbx\nnop word ptr [rax+rax+00000000h]\nloc_1280:\nmovsx rdx, byte ptr [rax]\nadd rax, 1\nadd [rsp+rdx*4+418h+var_418], 1\ncmp rax, rcx\njnz short loc_1280\nxor r8d, r8d\nmov esi, 0FFFFFFFFh\nnop dword ptr [rax+00000000h]\nloc_12A0:\nmovsx rax, byte ptr [rdi]\nmov rdx, rax\nmov eax, [rsp+rax*4+418h+var_418]\ncmp eax, esi\njle short loc_12B3\nmov r8d, edx\nmov esi, eax\nloc_12B3:\nadd rdi, 1\ncmp rdi, rcx\njnz short loc_12A0\nloc_12BC:\nmov rax, [rsp+418h+var_10]\nsub rax, fs:28h\njnz short loc_12E5\nadd rsp, 410h\nmov eax, r8d\npop rbx\nretn\nloc_12E0:\nxor r8d, r8d\njmp short loc_12BC\nloc_12E5:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1230(char *s)\n{\n int v1; // eax\n char *v2; // rcx\n char *v3; // rax\n __int64 v4; // rdx\n unsigned int v5; // r8d\n int v6; // esi\n __int64 v7; // rdx\n _DWORD v9[258]; // [rsp+0h] [rbp-418h] BYREF\n unsigned __int64 v10; // [rsp+408h] [rbp-10h]\n\n v10 = __readfsqword(0x28u);\n memset(v9, 0, 0x400uLL);\n v1 = strlen(s);\n if ( v1 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = &s[v1 - 1 + 1];\n v3 = s;\n do\n {\n v4 = *v3++;\n ++v9[v4];\n }\n while ( v3 != v2 );\n v5 = 0;\n v6 = -1;\n do\n {\n v7 = *s;\n if ( v9[v7] > v6 )\n {\n v5 = *s;\n v6 = v9[v7];\n }\n ++s;\n }\n while ( s != v2 );\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1230(char *s) {\n int v1;\n char *v2;\n char *v3;\n long long v4;\n unsigned int v5;\n int v6;\n long long v7;\n uint32_t v9[258];\n unsigned long long v10;\n v10 = __readfsqword(40u);\n memset(v9, 0, 1024uLL);\n v1 = strlen(s);\n if (v1 <= 0) {\n return 0;\n } else {\n v2 = &s[v1 - 1 + 1];\n v3 = s;\n do {\n v4 = *v3++;\n ++v9[v4];\n } while (v3 != v2);\n v5 = 0;\n v6 = -1;\n do {\n v7 = *s;\n if (v9[v7] > v6) {\n v5 = *s;\n v6 = v9[v7];\n }\n ++s;\n } while (s != v2);\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(char *s) {\n int v1;\n char *v2;\n char *v3;\n long long v4;\n unsigned int v5;\n int v6;\n long long v7;\n uint32_t v9[258];\n unsigned long long v10;\n v10 = __readfsqword(40u);\n memset(v9, 0, 1024uLL);\n v1 = strlen(s);\n if (v1 <= 0) {\n return 0;\n } else {\n v2 = &s[v1 - 1 + 1];\n v3 = s;\n do {\n v4 = *v3++;\n ++v9[v4];\n } while (v3 != v2);\n v5 = 0;\n v6 = -1;\n do {\n v7 = *s;\n if (v9[v7] > v6) {\n v5 = *s;\n v6 = v9[v7];\n }\n ++s;\n } while (s != v2);\n }\n return v5;\n}" + }, + { + "index": 480, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "char func0(const char* str1) {\n int ASCII_SIZE = 256;\n int ctr[256] = {0};\n int max = -1;\n char ch = '\\0';\n int length = strlen(str1);\n for (int i = 0; i < length; i++) {\n ctr[(int)str1[i]]++;\n }\n for (int i = 0; i < length; i++) {\n if (max < ctr[(int)str1[i]]) {\n max = ctr[(int)str1[i]];\n ch = str1[i];\n }\n }\n return ch;\n}", + "test": "int main() {\n\n assert(func0(\"data\") == 'a');\n\n assert(func0(\"create\") == 'e');\n\n assert(func0(\"brilliant girl\") == 'i');\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov $0x80,%ecx\nmov %rdi,%rbx\nsub $0x410,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x408(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nrep stos %rax,%es:(%rdi)\nmov %rbx,%rdi\ncallq 1070 \ntest %eax,%eax\njle 12e0 \nsub $0x1,%eax\nmov %rbx,%rdi\nlea 0x1(%rbx,%rax,1),%rcx\nmov %rbx,%rax\nnopw 0x0(%rax,%rax,1)\nmovsbq (%rax),%rdx\nadd $0x1,%rax\naddl $0x1,(%rsp,%rdx,4)\ncmp %rcx,%rax\njne 1280 \nxor %r8d,%r8d\nmov $0xffffffff,%esi\nnopl 0x0(%rax)\nmovsbq (%rdi),%rax\nmov %rax,%rdx\nmov (%rsp,%rax,4),%eax\ncmp %esi,%eax\njle 12b3 \nmov %edx,%r8d\nmov %eax,%esi\nadd $0x1,%rdi\ncmp %rcx,%rdi\njne 12a0 \nmov 0x408(%rsp),%rax\nxor %fs:0x28,%rax\njne 12e5 \nadd $0x410,%rsp\nmov %r8d,%eax\npop %rbx\nretq\nnopl 0x0(%rax,%rax,1)\nxor %r8d,%r8d\njmp 12bc \ncallq 1080 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov ecx, 80h\nmov rbx, rdi\nsub rsp, 410h\nmov rax, fs:28h\nmov [rsp+418h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\nmov rdi, rbx; s\ncall _strlen\ntest eax, eax\njle short loc_12E0\nsub eax, 1\nmov rdi, rbx\nlea rcx, [rbx+rax+1]\nmov rax, rbx\nnop word ptr [rax+rax+00000000h]\nloc_1280:\nmovsx rdx, byte ptr [rax]\nadd rax, 1\nadd [rsp+rdx*4+418h+var_418], 1\ncmp rax, rcx\njnz short loc_1280\nxor r8d, r8d\nmov esi, 0FFFFFFFFh\nnop dword ptr [rax+00000000h]\nloc_12A0:\nmovsx rax, byte ptr [rdi]\nmov rdx, rax\nmov eax, [rsp+rax*4+418h+var_418]\ncmp eax, esi\njle short loc_12B3\nmov r8d, edx\nmov esi, eax\nloc_12B3:\nadd rdi, 1\ncmp rdi, rcx\njnz short loc_12A0\nloc_12BC:\nmov rax, [rsp+418h+var_10]\nsub rax, fs:28h\njnz short loc_12E5\nadd rsp, 410h\nmov eax, r8d\npop rbx\nretn\nloc_12E0:\nxor r8d, r8d\njmp short loc_12BC\nloc_12E5:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(char *s)\n{\n int v1; // eax\n char *v2; // rcx\n char *v3; // rax\n __int64 v4; // rdx\n unsigned int v5; // r8d\n int v6; // esi\n __int64 v7; // rdx\n _DWORD v9[258]; // [rsp+0h] [rbp-418h] BYREF\n unsigned __int64 v10; // [rsp+408h] [rbp-10h]\n\n v10 = __readfsqword(0x28u);\n memset(v9, 0, 0x400uLL);\n v1 = strlen(s);\n if ( v1 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = &s[v1 - 1 + 1];\n v3 = s;\n do\n {\n v4 = *v3++;\n ++v9[v4];\n }\n while ( v3 != v2 );\n v5 = 0;\n v6 = -1;\n do\n {\n v7 = *s;\n if ( v9[v7] > v6 )\n {\n v5 = *s;\n v6 = v9[v7];\n }\n ++s;\n }\n while ( s != v2 );\n }\n return v5;\n}", + "ida_strip_asm": "sub_1230:\nendbr64\npush rbx\nmov ecx, 80h\nmov rbx, rdi\nsub rsp, 410h\nmov rax, fs:28h\nmov [rsp+418h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\nmov rdi, rbx; s\ncall _strlen\ntest eax, eax\njle short loc_12E0\nsub eax, 1\nmov rdi, rbx\nlea rcx, [rbx+rax+1]\nmov rax, rbx\nnop word ptr [rax+rax+00000000h]\nloc_1280:\nmovsx rdx, byte ptr [rax]\nadd rax, 1\nadd [rsp+rdx*4+418h+var_418], 1\ncmp rax, rcx\njnz short loc_1280\nxor r8d, r8d\nmov esi, 0FFFFFFFFh\nnop dword ptr [rax+00000000h]\nloc_12A0:\nmovsx rax, byte ptr [rdi]\nmov rdx, rax\nmov eax, [rsp+rax*4+418h+var_418]\ncmp eax, esi\njle short loc_12B3\nmov r8d, edx\nmov esi, eax\nloc_12B3:\nadd rdi, 1\ncmp rdi, rcx\njnz short loc_12A0\nloc_12BC:\nmov rax, [rsp+418h+var_10]\nsub rax, fs:28h\njnz short loc_12E5\nadd rsp, 410h\nmov eax, r8d\npop rbx\nretn\nloc_12E0:\nxor r8d, r8d\njmp short loc_12BC\nloc_12E5:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1230(char *s)\n{\n int v1; // eax\n char *v2; // rcx\n char *v3; // rax\n __int64 v4; // rdx\n unsigned int v5; // r8d\n int v6; // esi\n __int64 v7; // rdx\n _DWORD v9[258]; // [rsp+0h] [rbp-418h] BYREF\n unsigned __int64 v10; // [rsp+408h] [rbp-10h]\n\n v10 = __readfsqword(0x28u);\n memset(v9, 0, 0x400uLL);\n v1 = strlen(s);\n if ( v1 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = &s[v1 - 1 + 1];\n v3 = s;\n do\n {\n v4 = *v3++;\n ++v9[v4];\n }\n while ( v3 != v2 );\n v5 = 0;\n v6 = -1;\n do\n {\n v7 = *s;\n if ( v9[v7] > v6 )\n {\n v5 = *s;\n v6 = v9[v7];\n }\n ++s;\n }\n while ( s != v2 );\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1230(char *s) {\n int v1;\n char *v2;\n char *v3;\n long long v4;\n unsigned int v5;\n int v6;\n long long v7;\n uint32_t v9[258];\n unsigned long long v10;\n v10 = __readfsqword(40u);\n memset(v9, 0, 1024uLL);\n v1 = strlen(s);\n if (v1 <= 0) {\n return 0;\n } else {\n v2 = &s[v1 - 1 + 1];\n v3 = s;\n do {\n v4 = *v3++;\n ++v9[v4];\n } while (v3 != v2);\n v5 = 0;\n v6 = -1;\n do {\n v7 = *s;\n if (v9[v7] > v6) {\n v5 = *s;\n v6 = v9[v7];\n }\n ++s;\n } while (s != v2);\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(char *s) {\n int v1;\n char *v2;\n char *v3;\n long long v4;\n unsigned int v5;\n int v6;\n long long v7;\n uint32_t v9[258];\n unsigned long long v10;\n v10 = __readfsqword(40u);\n memset(v9, 0, 1024uLL);\n v1 = strlen(s);\n if (v1 <= 0) {\n return 0;\n } else {\n v2 = &s[v1 - 1 + 1];\n v3 = s;\n do {\n v4 = *v3++;\n ++v9[v4];\n } while (v3 != v2);\n v5 = 0;\n v6 = -1;\n do {\n v7 = *s;\n if (v9[v7] > v6) {\n v5 = *s;\n v6 = v9[v7];\n }\n ++s;\n } while (s != v2);\n }\n return v5;\n}" + }, + { + "index": 481, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int set[], int n, int sum) {\n if (sum == 0) return true;\n if (n == 0) return false;\n if (set[n - 1] > sum) return func0(set, n - 1, sum);\n return func0(set, n - 1, sum) || func0(set, n - 1, sum - set[n - 1]);\n}", + "test": "int main() {\n\n int set1[] = {3, 34, 4, 12, 5, 2};\n\n int set2[] = {3, 34, 4, 12, 5, 2};\n\n int set3[] = {3, 34, 4, 12, 5, 2};\n\n\n\n assert(func0(set1, 6, 9) == true);\n\n assert(func0(set2, 6, 30) == false);\n\n assert(func0(set3, 6, 15) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %rdi,-0x8(%rbp)\nmov %esi,-0xc(%rbp)\nmov %edx,-0x10(%rbp)\ncmpl $0x0,-0x10(%rbp)\njne 118f \nmov $0x1,%eax\njmpq 1230 \ncmpl $0x0,-0xc(%rbp)\njne 119f \nmov $0x0,%eax\njmpq 1230 \nmov -0xc(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x10(%rbp)\njge 11d3 \nmov -0xc(%rbp),%eax\nlea -0x1(%rax),%ecx\nmov -0x10(%rbp),%edx\nmov -0x8(%rbp),%rax\nmov %ecx,%esi\nmov %rax,%rdi\ncallq 1169 \njmp 1230 \nmov -0xc(%rbp),%eax\nlea -0x1(%rax),%ecx\nmov -0x10(%rbp),%edx\nmov -0x8(%rbp),%rax\nmov %ecx,%esi\nmov %rax,%rdi\ncallq 1169 \ntest %al,%al\njne 1221 \nmov -0xc(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov -0x10(%rbp),%edx\nsub %eax,%edx\nmov -0xc(%rbp),%eax\nlea -0x1(%rax),%ecx\nmov -0x8(%rbp),%rax\nmov %ecx,%esi\nmov %rax,%rdi\ncallq 1169 \ntest %al,%al\nje 1228 \nmov $0x1,%eax\njmp 122d \nmov $0x0,%eax\nand $0x1,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+var_8], rdi\nmov [rbp+var_C], esi\nmov [rbp+var_10], edx\ncmp [rbp+var_10], 0\njnz short loc_118F\nmov eax, 1\njmp locret_1230\nloc_118F:\ncmp [rbp+var_C], 0\njnz short loc_119F\nmov eax, 0\njmp locret_1230\nloc_119F:\nmov eax, [rbp+var_C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_10], eax\njge short loc_11D3\nmov eax, [rbp+var_C]\nlea ecx, [rax-1]\nmov edx, [rbp+var_10]\nmov rax, [rbp+var_8]\nmov esi, ecx\nmov rdi, rax\ncall func0\njmp short locret_1230\nloc_11D3:\nmov eax, [rbp+var_C]\nlea ecx, [rax-1]\nmov edx, [rbp+var_10]\nmov rax, [rbp+var_8]\nmov esi, ecx\nmov rdi, rax\ncall func0\ntest al, al\njnz short loc_1221\nmov eax, [rbp+var_C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_10]\nsub edx, eax\nmov eax, [rbp+var_C]\nlea ecx, [rax-1]\nmov rax, [rbp+var_8]\nmov esi, ecx\nmov rdi, rax\ncall func0\ntest al, al\njz short loc_1228\nloc_1221:\nmov eax, 1\njmp short loc_122D\nloc_1228:\nmov eax, 0\nloc_122D:\nand eax, 1\nlocret_1230:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, unsigned int a3)\n{\n if ( !a3 )\n return 1LL;\n if ( !a2 )\n return 0LL;\n if ( (signed int)a3 < *(_DWORD *)(4LL * a2 - 4 + a1) )\n return func0(a1, (unsigned int)(a2 - 1), a3);\n return (unsigned __int8)func0(a1, (unsigned int)(a2 - 1), a3)\n || (unsigned __int8)func0(a1, (unsigned int)(a2 - 1), a3 - *(_DWORD *)(4LL * a2 - 4 + a1));\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+var_8], rdi\nmov [rbp+var_C], esi\nmov [rbp+var_10], edx\ncmp [rbp+var_10], 0\njnz short loc_118F\nmov eax, 1\njmp locret_1230\nloc_118F:\ncmp [rbp+var_C], 0\njnz short loc_119F\nmov eax, 0\njmp locret_1230\nloc_119F:\nmov eax, [rbp+var_C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_10], eax\njge short loc_11D3\nmov eax, [rbp+var_C]\nlea ecx, [rax-1]\nmov edx, [rbp+var_10]\nmov rax, [rbp+var_8]\nmov esi, ecx\nmov rdi, rax\ncall sub_1169\njmp short locret_1230\nloc_11D3:\nmov eax, [rbp+var_C]\nlea ecx, [rax-1]\nmov edx, [rbp+var_10]\nmov rax, [rbp+var_8]\nmov esi, ecx\nmov rdi, rax\ncall sub_1169\ntest al, al\njnz short loc_1221\nmov eax, [rbp+var_C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_10]\nsub edx, eax\nmov eax, [rbp+var_C]\nlea ecx, [rax-1]\nmov rax, [rbp+var_8]\nmov esi, ecx\nmov rdi, rax\ncall sub_1169\ntest al, al\njz short loc_1228\nloc_1221:\nmov eax, 1\njmp short loc_122D\nloc_1228:\nmov eax, 0\nloc_122D:\nand eax, 1\nlocret_1230:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, unsigned int a3)\n{\n if ( !a3 )\n return 1LL;\n if ( !a2 )\n return 0LL;\n if ( (signed int)a3 < *(_DWORD *)(4LL * a2 - 4 + a1) )\n return sub_1169(a1, (unsigned int)(a2 - 1), a3);\n return (unsigned __int8)sub_1169(a1, (unsigned int)(a2 - 1), a3)\n || (unsigned __int8)sub_1169(a1, (unsigned int)(a2 - 1), a3 - *(_DWORD *)(4LL * a2 - 4 + a1));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, unsigned int a3) {\n if (!a3) return 1LL;\n if (!a2) return 0LL;\n if ((signed int)a3 < *(uint32_t *)(4LL * a2 - 4 + a1))\n return sub_1169(a1, (unsigned int)(a2 - 1), a3);\n return (unsigned char)sub_1169(a1, (unsigned int)(a2 - 1), a3) ||\n (unsigned char)sub_1169(a1, (unsigned int)(a2 - 1),\n a3 - *(uint32_t *)(4LL * a2 - 4 + a1));\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, unsigned int a3) {\n if (!a3) return 1LL;\n if (!a2) return 0LL;\n if ((signed int)a3 < *(uint32_t *)(4LL * a2 - 4 + a1))\n return func0(a1, (unsigned int)(a2 - 1), a3);\n return (unsigned char)func0(a1, (unsigned int)(a2 - 1), a3) ||\n (unsigned char)func0(a1, (unsigned int)(a2 - 1),\n a3 - *(uint32_t *)(4LL * a2 - 4 + a1));\n}" + }, + { + "index": 481, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int set[], int n, int sum) {\n if (sum == 0) return true;\n if (n == 0) return false;\n if (set[n - 1] > sum) return func0(set, n - 1, sum);\n return func0(set, n - 1, sum) || func0(set, n - 1, sum - set[n - 1]);\n}", + "test": "int main() {\n\n int set1[] = {3, 34, 4, 12, 5, 2};\n\n int set2[] = {3, 34, 4, 12, 5, 2};\n\n int set3[] = {3, 34, 4, 12, 5, 2};\n\n\n\n assert(func0(set1, 6, 9) == true);\n\n assert(func0(set2, 6, 30) == false);\n\n assert(func0(set3, 6, 15) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x1,%eax\ntest %edx,%edx\nje 11dc \npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%r12\nmov %edx,%ebp\nmov $0x0,%eax\ntest %esi,%esi\nje 11b3 \nmovslq %esi,%rax\nmov -0x4(%rdi,%rax,4),%r13d\ncmp %edx,%r13d\njg 11be \nlea -0x1(%rsi),%ebx\nmov %ebx,%esi\ncallq 1169 \nmov %eax,%edx\nmov $0x1,%eax\ntest %dl,%dl\nje 11c8 \nand $0x1,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nsub $0x1,%esi\ncallq 1169 \njmp 11b3 \nmov %ebp,%edx\nsub %r13d,%edx\nmov %ebx,%esi\nmov %r12,%rdi\ncallq 1169 \nmovzbl %al,%eax\njmp 11b0 \nretq\n", + "ida_asm": "func0:\nendbr64\nmov eax, 1\ntest edx, edx\njz short locret_11DC\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12, rdi\nmov ebp, edx\nmov eax, 0\ntest esi, esi\njz short loc_11B3\nmovsxd rax, esi\nmov r13d, [rdi+rax*4-4]\ncmp r13d, edx\njg short loc_11BE\nlea ebx, [rsi-1]\nmov esi, ebx\ncall func0\nmov edx, eax\nmov eax, 1\ntest dl, dl\njz short loc_11C8\nloc_11B0:\nand eax, 1\nloc_11B3:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_11BE:\nsub esi, 1\ncall func0\njmp short loc_11B3\nloc_11C8:\nmov edx, ebp\nsub edx, r13d\nmov esi, ebx\nmov rdi, r12\ncall func0\nmovzx eax, al\njmp short loc_11B0\nlocret_11DC:\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n __int64 result; // rax\n char v4; // dl\n char v5; // al\n\n result = 1LL;\n if ( a3 )\n {\n result = 0LL;\n if ( a2 )\n {\n if ( *(_DWORD *)(a1 + 4LL * a2 - 4) > a3 )\n {\n return func0(a1, (unsigned int)(a2 - 1));\n }\n else\n {\n v4 = func0(a1, (unsigned int)(a2 - 1));\n v5 = 1;\n if ( !v4 )\n v5 = func0(a1, (unsigned int)(a2 - 1));\n return v5 & 1;\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov eax, 1\ntest edx, edx\njz short locret_11DC\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12, rdi\nmov ebp, edx\nmov eax, 0\ntest esi, esi\njz short loc_11B3\nmovsxd rax, esi\nmov r13d, [rdi+rax*4-4]\ncmp r13d, edx\njg short loc_11BE\nlea ebx, [rsi-1]\nmov esi, ebx\ncall sub_1169\nmov edx, eax\nmov eax, 1\ntest dl, dl\njz short loc_11C8\nloc_11B0:\nand eax, 1\nloc_11B3:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_11BE:\nsub esi, 1\ncall sub_1169\njmp short loc_11B3\nloc_11C8:\nmov edx, ebp\nsub edx, r13d\nmov esi, ebx\nmov rdi, r12\ncall sub_1169\nmovzx eax, al\njmp short loc_11B0\nlocret_11DC:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n __int64 result; // rax\n char v4; // dl\n char v5; // al\n\n result = 1LL;\n if ( a3 )\n {\n result = 0LL;\n if ( a2 )\n {\n if ( *(_DWORD *)(a1 + 4LL * a2 - 4) > a3 )\n {\n return sub_1169(a1, (unsigned int)(a2 - 1));\n }\n else\n {\n v4 = sub_1169(a1, (unsigned int)(a2 - 1));\n v5 = 1;\n if ( !v4 )\n v5 = sub_1169(a1, (unsigned int)(a2 - 1));\n return v5 & 1;\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n long long result;\n char v4;\n char v5;\n result = 1LL;\n if (a3) {\n result = 0LL;\n if (a2) {\n if (*(uint32_t *)(a1 + 4LL * a2 - 4) > a3) {\n return sub_1169(a1, (unsigned int)(a2 - 1));\n } else {\n v4 = sub_1169(a1, (unsigned int)(a2 - 1));\n v5 = 1;\n if (!v4) v5 = sub_1169(a1, (unsigned int)(a2 - 1));\n return v5 & 1;\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n long long result;\n char v4;\n char v5;\n result = 1LL;\n if (a3) {\n result = 0LL;\n if (a2) {\n if (*(uint32_t *)(a1 + 4LL * a2 - 4) > a3) {\n return func0(a1, (unsigned int)(a2 - 1));\n } else {\n v4 = func0(a1, (unsigned int)(a2 - 1));\n v5 = 1;\n if (!v4) v5 = func0(a1, (unsigned int)(a2 - 1));\n return v5 & 1;\n }\n }\n }\n return result;\n}" + }, + { + "index": 481, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int set[], int n, int sum) {\n if (sum == 0) return true;\n if (n == 0) return false;\n if (set[n - 1] > sum) return func0(set, n - 1, sum);\n return func0(set, n - 1, sum) || func0(set, n - 1, sum - set[n - 1]);\n}", + "test": "int main() {\n\n int set1[] = {3, 34, 4, 12, 5, 2};\n\n int set2[] = {3, 34, 4, 12, 5, 2};\n\n int set3[] = {3, 34, 4, 12, 5, 2};\n\n\n\n assert(func0(set1, 6, 9) == true);\n\n assert(func0(set2, 6, 30) == false);\n\n assert(func0(set3, 6, 15) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov %rdi,%r13\npush %r12\nmov %edx,%r12d\npush %rbp\nmovslq %esi,%rbp\npush %rbx\nsub $0x8,%rsp\ntest %r12d,%r12d\nje 1325 \ntest %ebp,%ebp\nje 1310 \nlea -0x1(%rbp),%edx\nlea -0x2(%rbp),%rax\nmovslq %edx,%rsi\nmov %edx,%edx\nsub %rdx,%rax\njmp 12e1 \nnopl 0x0(%rax)\nsub $0x1,%rsi\ncmp %rsi,%rax\nje 1310 \nmov 0x0(%r13,%rsi,4),%ebx\nmovslq %esi,%rbp\ncmp %r12d,%ebx\njg 12d8 \nmov %r12d,%edx\nmov %r13,%rdi\ncallq 12a0 \ntest %al,%al\nje 1320 \nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax,%rax,1)\nadd $0x8,%rsp\nxor %eax,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopl (%rax)\nsub %ebx,%r12d\njmp 12b7 \nmov $0x1,%eax\njmp 12fd \nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r13\nmov r13, rdi\npush r12\nmov r12d, edx\npush rbp\npush rbx\nmov ebx, esi\nsub rsp, 8\nloc_1296:\ntest r12d, r12d\njz short loc_1305\ntest ebx, ebx\njz short loc_12F0\nlea edx, [rbx-1]\nmovsxd rcx, ebx\nmovsxd rax, edx\nsub rcx, 2\nmov edx, edx\nsub rcx, rdx\njmp short loc_12C1\nloc_12B8:\nsub rax, 1\ncmp rcx, rax\njz short loc_12F0\nloc_12C1:\nmov ebp, [r13+rax*4+0]\ncmp ebp, r12d\njg short loc_12B8\nmov edx, r12d\nmov esi, eax\nmov rdi, r13\nmov ebx, eax\ncall func0\ntest al, al\njz short loc_1300\nloc_12DE:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_12F0:\nadd rsp, 8\nxor eax, eax\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1300:\nsub r12d, ebp\njmp short loc_1296\nloc_1305:\nmov eax, 1\njmp short loc_12DE", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, unsigned int a3)\n{\n __int64 v5; // rax\n __int64 v6; // rcx\n int v7; // ebp\n __int64 result; // rax\n\n while ( a3 )\n {\n if ( !a2 )\n return 0LL;\n v5 = a2 - 1;\n v6 = a2 - 2LL - (unsigned int)(a2 - 1);\n while ( 1 )\n {\n v7 = *(_DWORD *)(a1 + 4 * v5);\n if ( v7 <= (int)a3 )\n break;\n if ( v6 == --v5 )\n return 0LL;\n }\n a2 = v5;\n result = func0(a1, (unsigned int)v5, a3, v6);\n if ( (_BYTE)result )\n return result;\n a3 -= v7;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\npush r13\nmov r13, rdi\npush r12\nmov r12d, edx\npush rbp\npush rbx\nmov ebx, esi\nsub rsp, 8\nloc_1296:\ntest r12d, r12d\njz short loc_1305\ntest ebx, ebx\njz short loc_12F0\nlea edx, [rbx-1]\nmovsxd rcx, ebx\nmovsxd rax, edx\nsub rcx, 2\nmov edx, edx\nsub rcx, rdx\njmp short loc_12C1\nloc_12B8:\nsub rax, 1\ncmp rcx, rax\njz short loc_12F0\nloc_12C1:\nmov ebp, [r13+rax*4+0]\ncmp ebp, r12d\njg short loc_12B8\nmov edx, r12d\nmov esi, eax\nmov rdi, r13\nmov ebx, eax\ncall sub_1280\ntest al, al\njz short loc_1300\nloc_12DE:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_12F0:\nadd rsp, 8\nxor eax, eax\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1300:\nsub r12d, ebp\njmp short loc_1296\nloc_1305:\nmov eax, 1\njmp short loc_12DE", + "ida_strip_pseudo": "__int64 __fastcall sub_1280(__int64 a1, int a2, unsigned int a3)\n{\n __int64 v5; // rax\n __int64 v6; // rcx\n int v7; // ebp\n __int64 result; // rax\n\n while ( a3 )\n {\n if ( !a2 )\n return 0LL;\n v5 = a2 - 1;\n v6 = a2 - 2LL - (unsigned int)(a2 - 1);\n while ( 1 )\n {\n v7 = *(_DWORD *)(a1 + 4 * v5);\n if ( v7 <= (int)a3 )\n break;\n if ( v6 == --v5 )\n return 0LL;\n }\n a2 = v5;\n result = sub_1280(a1, (unsigned int)v5, a3, v6);\n if ( (_BYTE)result )\n return result;\n a3 -= v7;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1280(long long a1, int a2, unsigned int a3) {\n long long v5;\n long long v6;\n int v7;\n long long result;\n while (a3) {\n if (!a2) return 0LL;\n v5 = a2 - 1;\n v6 = a2 - 2LL - (unsigned int)(a2 - 1);\n while (1) {\n v7 = *(uint32_t *)(a1 + 4 * v5);\n if (v7 <= (int)a3) break;\n if (v6 == --v5) return 0LL;\n }\n a2 = v5;\n result = sub_1280(a1, (unsigned int)v5, a3, v6);\n if ((uint8_t)result) return result;\n a3 -= v7;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, unsigned int a3) {\n long long v5;\n long long v6;\n int v7;\n long long result;\n while (a3) {\n if (!a2) return 0LL;\n v5 = a2 - 1;\n v6 = a2 - 2LL - (unsigned int)(a2 - 1);\n while (1) {\n v7 = *(uint32_t *)(a1 + 4 * v5);\n if (v7 <= (int)a3) break;\n if (v6 == --v5) return 0LL;\n }\n a2 = v5;\n result = func0(a1, (unsigned int)v5, a3, v6);\n if ((uint8_t)result) return result;\n a3 -= v7;\n }\n return 1LL;\n}" + }, + { + "index": 481, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int set[], int n, int sum) {\n if (sum == 0) return true;\n if (n == 0) return false;\n if (set[n - 1] > sum) return func0(set, n - 1, sum);\n return func0(set, n - 1, sum) || func0(set, n - 1, sum - set[n - 1]);\n}", + "test": "int main() {\n\n int set1[] = {3, 34, 4, 12, 5, 2};\n\n int set2[] = {3, 34, 4, 12, 5, 2};\n\n int set3[] = {3, 34, 4, 12, 5, 2};\n\n\n\n assert(func0(set1, 6, 9) == true);\n\n assert(func0(set2, 6, 30) == false);\n\n assert(func0(set3, 6, 15) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov %rdi,%r13\npush %r12\nmov %edx,%r12d\npush %rbp\nmovslq %esi,%rbp\npush %rbx\nsub $0x8,%rsp\ntest %r12d,%r12d\nje 1305 \ntest %ebp,%ebp\nje 12f0 \nlea -0x1(%rbp),%edx\nlea -0x2(%rbp),%rax\nmovslq %edx,%rsi\nmov %edx,%edx\nsub %rdx,%rax\njmp 12c1 \nnopl 0x0(%rax)\nsub $0x1,%rsi\ncmp %rsi,%rax\nje 12f0 \nmov 0x0(%r13,%rsi,4),%ebx\nmovslq %esi,%rbp\ncmp %r12d,%ebx\njg 12b8 \nmov %r12d,%edx\nmov %r13,%rdi\ncallq 1280 \ntest %al,%al\nje 1300 \nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax,%rax,1)\nadd $0x8,%rsp\nxor %eax,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopl (%rax)\nsub %ebx,%r12d\njmp 1297 \nmov $0x1,%eax\njmp 12dd \nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\nmov ebp, edx\npush rbx\nmov ebx, esi\nsub rsp, 18h\nloc_1286:\ntest ebp, ebp\njz loc_13D1\ntest ebx, ebx\njz loc_13C0\nmovsxd rax, ebx\nlea rax, [rdi+rax*4]\njmp short loc_12AC\nloc_12A0:\nsub rax, 4\ntest ebx, ebx\njz loc_13C0\nloc_12AC:\nmov r12d, [rax-4]\nmov r14d, ebx\nsub ebx, 1\ncmp r12d, ebp\njg short loc_12A0\ncmp r14d, 1\njz loc_13D8\nmovsxd r15, ebx\nlea rax, [rdi+r15*4]\njmp short loc_12DC\nloc_12D0:\nsub rax, 4\ntest ebx, ebx\njz loc_1370\nloc_12DC:\nmov r13d, [rax-4]\nmov edx, ebx\nsub ebx, 1\ncmp ebp, r13d\njl short loc_12D0\ncmp edx, 1\njz short loc_1357\nsub edx, 2\nmovsxd rsi, ebx\nmovsxd rax, edx\nsub rsi, 2\nmov edx, edx\nsub rsi, rdx\njmp short loc_1311\nloc_1308:\nsub rax, 1\ncmp rsi, rax\njz short loc_1357\nloc_1311:\nmov r8d, [rdi+rax*4]\ncmp ebp, r8d\njl short loc_1308\nmov esi, eax\nmov edx, ebp\nmov [rsp+48h+var_3C], r8d\nmov [rsp+48h+var_48], rdi\nmov [rsp+48h+var_40], eax\ncall func0\nmov rdi, [rsp+48h+var_48]\nmov esi, [rsp+48h+var_40]\ntest al, al\nmov r8d, [rsp+48h+var_3C]\njnz loc_13C2\nmov edx, ebp\nsub edx, r8d\ncall func0\nmov rdi, [rsp+48h+var_48]\ntest al, al\njnz short loc_13C2\nloc_1357:\nmov edx, ebp\nmov esi, ebx\nmov [rsp+48h+var_48], rdi\nsub edx, r13d\ncall func0\nmov rdi, [rsp+48h+var_48]\ntest al, al\njnz short loc_13C2\nnop\nloc_1370:\nsub ebp, r12d\njz short loc_13D1\nlea eax, [r14-2]\nlea rcx, [r15-2]\nmovsxd rbx, eax\nmov eax, eax\nsub rcx, rax\njmp short loc_1399\nloc_1390:\nsub rbx, 1\ncmp rcx, rbx\njz short loc_13C0\nloc_1399:\nmov r12d, [rdi+rbx*4]\ncmp ebp, r12d\njl short loc_1390\nmov edx, ebp\nmov esi, ebx\nmov [rsp+48h+var_48], rdi\ncall func0\nmov rdi, [rsp+48h+var_48]\ntest al, al\njnz short loc_13C2\nsub ebp, r12d\njmp loc_1286\nloc_13C0:\nxor eax, eax\nloc_13C2:\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_13D1:\nmov eax, 1\njmp short loc_13C2\nloc_13D8:\ncmp r12d, ebp\nsetz al\njmp short loc_13C2", + "ida_pseudo": "char __fastcall func0(__int64 a1, int a2, signed int a3)\n{\n __int64 v4; // rbx\n __int64 i; // rax\n int v6; // r12d\n int v7; // r14d\n __int64 v8; // r15\n __int64 v9; // rax\n int v10; // r13d\n int v11; // edx\n unsigned int v12; // edx\n __int64 v13; // rax\n char result; // al\n unsigned int v15; // ebp\n int v16; // r12d\n unsigned int v17; // [rsp+8h] [rbp-40h]\n int v18; // [rsp+Ch] [rbp-3Ch]\n\n LODWORD(v4) = a2;\n while ( 2 )\n {\n if ( !a3 )\n return 1;\n if ( !(_DWORD)v4 )\n return 0;\n for ( i = a1 + 4LL * (int)v4; ; i -= 4LL )\n {\n v6 = *(_DWORD *)(i - 4);\n v7 = v4;\n LODWORD(v4) = v4 - 1;\n if ( v6 <= a3 )\n break;\n if ( !(_DWORD)v4 )\n return 0;\n }\n if ( v7 == 1 )\n return v6 == a3;\n v8 = (int)v4;\n v9 = a1 + 4LL * (int)v4;\n while ( 1 )\n {\n v10 = *(_DWORD *)(v9 - 4);\n v11 = v4;\n LODWORD(v4) = v4 - 1;\n if ( a3 >= v10 )\n break;\n v9 -= 4LL;\n if ( !(_DWORD)v4 )\n goto LABEL_18;\n }\n if ( v11 != 1 )\n {\n v12 = v11 - 2;\n v13 = (int)v12;\n while ( a3 < *(_DWORD *)(a1 + 4 * v13) )\n {\n if ( (int)v4 - 2LL - v12 == --v13 )\n goto LABEL_17;\n }\n v18 = *(_DWORD *)(a1 + 4 * v13);\n v17 = v13;\n result = func0(a1, (unsigned int)v13, (unsigned int)a3);\n if ( result )\n return result;\n result = func0(a1, v17, (unsigned int)(a3 - v18));\n if ( result )\n return result;\n }\nLABEL_17:\n result = func0(a1, (unsigned int)v4, (unsigned int)(a3 - v10));\n if ( result )\n return result;\nLABEL_18:\n v15 = a3 - v6;\n if ( !v15 )\n return 1;\n v4 = v7 - 2;\n while ( 1 )\n {\n v16 = *(_DWORD *)(a1 + 4 * v4);\n if ( (int)v15 >= v16 )\n break;\n if ( v8 - 2 - (unsigned int)(v7 - 2) == --v4 )\n return 0;\n }\n result = func0(a1, (unsigned int)v4, v15);\n if ( !result )\n {\n a3 = v15 - v16;\n continue;\n }\n return result;\n }\n}", + "ida_strip_asm": "sub_1270:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\nmov ebp, edx\npush rbx\nmov ebx, esi\nsub rsp, 18h\nloc_1286:\ntest ebp, ebp\njz loc_13D1\ntest ebx, ebx\njz loc_13C0\nmovsxd rax, ebx\nlea rax, [rdi+rax*4]\njmp short loc_12AC\nloc_12A0:\nsub rax, 4\ntest ebx, ebx\njz loc_13C0\nloc_12AC:\nmov r12d, [rax-4]\nmov r14d, ebx\nsub ebx, 1\ncmp r12d, ebp\njg short loc_12A0\ncmp r14d, 1\njz loc_13D8\nmovsxd r15, ebx\nlea rax, [rdi+r15*4]\njmp short loc_12DC\nloc_12D0:\nsub rax, 4\ntest ebx, ebx\njz loc_1370\nloc_12DC:\nmov r13d, [rax-4]\nmov edx, ebx\nsub ebx, 1\ncmp ebp, r13d\njl short loc_12D0\ncmp edx, 1\njz short loc_1357\nsub edx, 2\nmovsxd rsi, ebx\nmovsxd rax, edx\nsub rsi, 2\nmov edx, edx\nsub rsi, rdx\njmp short loc_1311\nloc_1308:\nsub rax, 1\ncmp rsi, rax\njz short loc_1357\nloc_1311:\nmov r8d, [rdi+rax*4]\ncmp ebp, r8d\njl short loc_1308\nmov esi, eax\nmov edx, ebp\nmov [rsp+48h+var_3C], r8d\nmov [rsp+48h+var_48], rdi\nmov [rsp+48h+var_40], eax\ncall sub_1270\nmov rdi, [rsp+48h+var_48]\nmov esi, [rsp+48h+var_40]\ntest al, al\nmov r8d, [rsp+48h+var_3C]\njnz loc_13C2\nmov edx, ebp\nsub edx, r8d\ncall sub_1270\nmov rdi, [rsp+48h+var_48]\ntest al, al\njnz short loc_13C2\nloc_1357:\nmov edx, ebp\nmov esi, ebx\nmov [rsp+48h+var_48], rdi\nsub edx, r13d\ncall sub_1270\nmov rdi, [rsp+48h+var_48]\ntest al, al\njnz short loc_13C2\nnop\nloc_1370:\nsub ebp, r12d\njz short loc_13D1\nlea eax, [r14-2]\nlea rcx, [r15-2]\nmovsxd rbx, eax\nmov eax, eax\nsub rcx, rax\njmp short loc_1399\nloc_1390:\nsub rbx, 1\ncmp rcx, rbx\njz short loc_13C0\nloc_1399:\nmov r12d, [rdi+rbx*4]\ncmp ebp, r12d\njl short loc_1390\nmov edx, ebp\nmov esi, ebx\nmov [rsp+48h+var_48], rdi\ncall sub_1270\nmov rdi, [rsp+48h+var_48]\ntest al, al\njnz short loc_13C2\nsub ebp, r12d\njmp loc_1286\nloc_13C0:\nxor eax, eax\nloc_13C2:\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_13D1:\nmov eax, 1\njmp short loc_13C2\nloc_13D8:\ncmp r12d, ebp\nsetz al\njmp short loc_13C2", + "ida_strip_pseudo": "char __fastcall sub_1270(__int64 a1, int a2, signed int a3)\n{\n __int64 v4; // rbx\n __int64 i; // rax\n int v6; // r12d\n int v7; // r14d\n __int64 v8; // r15\n __int64 v9; // rax\n int v10; // r13d\n int v11; // edx\n unsigned int v12; // edx\n __int64 v13; // rax\n char result; // al\n unsigned int v15; // ebp\n int v16; // r12d\n unsigned int v17; // [rsp+8h] [rbp-40h]\n int v18; // [rsp+Ch] [rbp-3Ch]\n\n LODWORD(v4) = a2;\n while ( 2 )\n {\n if ( !a3 )\n return 1;\n if ( !(_DWORD)v4 )\n return 0;\n for ( i = a1 + 4LL * (int)v4; ; i -= 4LL )\n {\n v6 = *(_DWORD *)(i - 4);\n v7 = v4;\n LODWORD(v4) = v4 - 1;\n if ( v6 <= a3 )\n break;\n if ( !(_DWORD)v4 )\n return 0;\n }\n if ( v7 == 1 )\n return v6 == a3;\n v8 = (int)v4;\n v9 = a1 + 4LL * (int)v4;\n while ( 1 )\n {\n v10 = *(_DWORD *)(v9 - 4);\n v11 = v4;\n LODWORD(v4) = v4 - 1;\n if ( a3 >= v10 )\n break;\n v9 -= 4LL;\n if ( !(_DWORD)v4 )\n goto LABEL_18;\n }\n if ( v11 != 1 )\n {\n v12 = v11 - 2;\n v13 = (int)v12;\n while ( a3 < *(_DWORD *)(a1 + 4 * v13) )\n {\n if ( (int)v4 - 2LL - v12 == --v13 )\n goto LABEL_17;\n }\n v18 = *(_DWORD *)(a1 + 4 * v13);\n v17 = v13;\n result = sub_1270(a1, (unsigned int)v13, (unsigned int)a3);\n if ( result )\n return result;\n result = sub_1270(a1, v17, (unsigned int)(a3 - v18));\n if ( result )\n return result;\n }\nLABEL_17:\n result = sub_1270(a1, (unsigned int)v4, (unsigned int)(a3 - v10));\n if ( result )\n return result;\nLABEL_18:\n v15 = a3 - v6;\n if ( !v15 )\n return 1;\n v4 = v7 - 2;\n while ( 1 )\n {\n v16 = *(_DWORD *)(a1 + 4 * v4);\n if ( (int)v15 >= v16 )\n break;\n if ( v8 - 2 - (unsigned int)(v7 - 2) == --v4 )\n return 0;\n }\n result = sub_1270(a1, (unsigned int)v4, v15);\n if ( !result )\n {\n a3 = v15 - v16;\n continue;\n }\n return result;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char sub_1270(long long a1, int a2, signed int a3) {\n long long v4;\n long long i;\n int v6;\n int v7;\n long long v8;\n long long v9;\n int v10;\n int v11;\n unsigned int v12;\n long long v13;\n char result;\n unsigned int v15;\n int v16;\n unsigned int v17;\n int v18;\n LODWORD(v4) = a2;\n while (2) {\n if (!a3) return 1;\n if (!(uint32_t)v4) return 0;\n for (i = a1 + 4LL * (int)v4;; i -= 4LL) {\n v6 = *(uint32_t *)(i - 4);\n v7 = v4;\n LODWORD(v4) = v4 - 1;\n if (v6 <= a3) break;\n if (!(uint32_t)v4) return 0;\n }\n if (v7 == 1) return v6 == a3;\n v8 = (int)v4;\n v9 = a1 + 4LL * (int)v4;\n while (1) {\n v10 = *(uint32_t *)(v9 - 4);\n v11 = v4;\n LODWORD(v4) = v4 - 1;\n if (a3 >= v10) break;\n v9 -= 4LL;\n if (!(uint32_t)v4) goto LABEL_18;\n }\n if (v11 != 1) {\n v12 = v11 - 2;\n v13 = (int)v12;\n while (a3 < *(uint32_t *)(a1 + 4 * v13)) {\n if ((int)v4 - 2LL - v12 == --v13) goto LABEL_17;\n }\n v18 = *(uint32_t *)(a1 + 4 * v13);\n v17 = v13;\n result = sub_1270(a1, (unsigned int)v13, (unsigned int)a3);\n if (result) return result;\n result = sub_1270(a1, v17, (unsigned int)(a3 - v18));\n if (result) return result;\n }\n LABEL_17:\n result = sub_1270(a1, (unsigned int)v4, (unsigned int)(a3 - v10));\n if (result) return result;\n LABEL_18:\n v15 = a3 - v6;\n if (!v15) return 1;\n v4 = v7 - 2;\n while (1) {\n v16 = *(uint32_t *)(a1 + 4 * v4);\n if ((int)v15 >= v16) break;\n if (v8 - 2 - (unsigned int)(v7 - 2) == --v4) return 0;\n }\n result = sub_1270(a1, (unsigned int)v4, v15);\n if (!result) {\n a3 = v15 - v16;\n continue;\n }\n return result;\n }\n}", + "ida_pseudo_norm": "char func0(long long a1, int a2, signed int a3) {\n long long v4;\n long long i;\n int v6;\n int v7;\n long long v8;\n long long v9;\n int v10;\n int v11;\n unsigned int v12;\n long long v13;\n char result;\n unsigned int v15;\n int v16;\n unsigned int v17;\n int v18;\n LODWORD(v4) = a2;\n while (2) {\n if (!a3) return 1;\n if (!(uint32_t)v4) return 0;\n for (i = a1 + 4LL * (int)v4;; i -= 4LL) {\n v6 = *(uint32_t *)(i - 4);\n v7 = v4;\n LODWORD(v4) = v4 - 1;\n if (v6 <= a3) break;\n if (!(uint32_t)v4) return 0;\n }\n if (v7 == 1) return v6 == a3;\n v8 = (int)v4;\n v9 = a1 + 4LL * (int)v4;\n while (1) {\n v10 = *(uint32_t *)(v9 - 4);\n v11 = v4;\n LODWORD(v4) = v4 - 1;\n if (a3 >= v10) break;\n v9 -= 4LL;\n if (!(uint32_t)v4) goto LABEL_18;\n }\n if (v11 != 1) {\n v12 = v11 - 2;\n v13 = (int)v12;\n while (a3 < *(uint32_t *)(a1 + 4 * v13)) {\n if ((int)v4 - 2LL - v12 == --v13) goto LABEL_17;\n }\n v18 = *(uint32_t *)(a1 + 4 * v13);\n v17 = v13;\n result = func0(a1, (unsigned int)v13, (unsigned int)a3);\n if (result) return result;\n result = func0(a1, v17, (unsigned int)(a3 - v18));\n if (result) return result;\n }\n LABEL_17:\n result = func0(a1, (unsigned int)v4, (unsigned int)(a3 - v10));\n if (result) return result;\n LABEL_18:\n v15 = a3 - v6;\n if (!v15) return 1;\n v4 = v7 - 2;\n while (1) {\n v16 = *(uint32_t *)(a1 + 4 * v4);\n if ((int)v15 >= v16) break;\n if (v8 - 2 - (unsigned int)(v7 - 2) == --v4) return 0;\n }\n result = func0(a1, (unsigned int)v4, v15);\n if (!result) {\n a3 = v15 - v16;\n continue;\n }\n return result;\n }\n}" + }, + { + "index": 482, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* text) {\n regex_t regex;\n int result;\n char* pattern = \"[A-Z]+[a-z]+$\";\n regcomp(®ex, pattern, REG_EXTENDED);\n result = regexec(®ex, text, 0, NULL, 0);\n regfree(®ex);\n if (result == 0) {\n return \"Yes\";\n } else {\n return \"No\";\n }\n}", + "test": "int main() {\n\n assert(func0(\"Geeks\") == \"Yes\");\n\n assert(func0(\"geeksforGeeks\") == \"Yes\");\n\n assert(func0(\"geeks\") == \"No\");\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x70,%rsp\nmov %rdi,-0x68(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0xe19(%rip),%rax\nmov %rax,-0x58(%rbp)\nmov -0x58(%rbp),%rcx\nlea -0x50(%rbp),%rax\nmov $0x1,%edx\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 10c0 \nmov -0x68(%rbp),%rsi\nlea -0x50(%rbp),%rax\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rax,%rdi\ncallq 10d0 \nmov %eax,-0x5c(%rbp)\nlea -0x50(%rbp),%rax\nmov %rax,%rdi\ncallq 1090 \ncmpl $0x0,-0x5c(%rbp)\njne 1249 \nlea 0xdcf(%rip),%rax\njmp 1250 \nlea 0xdca(%rip),%rax\nmov -0x8(%rbp),%rdx\nxor %fs:0x28,%rdx\nje 1264 \ncallq 10a0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aAZAZ; \"[A-Z]+[a-z]+$\"\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_5C], eax\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\ncmp [rbp+var_5C], 0\njnz short loc_1249\nlea rax, aYes; \"Yes\"\njmp short loc_1250\nloc_1249:\nlea rax, aNo; \"No\"\nloc_1250:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1264\ncall ___stack_chk_fail\nlocret_1264:\nleave\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n int v2; // [rsp+14h] [rbp-5Ch]\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n unsigned __int64 v4; // [rsp+68h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n regcomp(&preg, \"[A-Z]+[a-z]+$\", 1);\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if ( v2 )\n return \"No\";\n else\n return \"Yes\";\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aAZAZ; \"[A-Z]+[a-z]+$\"\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_5C], eax\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\ncmp [rbp+var_5C], 0\njnz short loc_1249\nlea rax, aYes; \"Yes\"\njmp short loc_1250\nloc_1249:\nlea rax, aNo; \"No\"\nloc_1250:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1264\ncall ___stack_chk_fail\nlocret_1264:\nleave\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_11C9(const char *a1)\n{\n int v2; // [rsp+14h] [rbp-5Ch]\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n unsigned __int64 v4; // [rsp+68h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n regcomp(&preg, \"[A-Z]+[a-z]+$\", 1);\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if ( v2 )\n return \"No\";\n else\n return \"Yes\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_11C9(const char *a1) {\n int v2;\n regex_t preg;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n regcomp(&preg, \"[A-Z]+[a-z]+$\", 1);\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if (v2)\n return \"No\";\n else\n return \"Yes\";\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n int v2;\n regex_t preg;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n regcomp(&preg, \"[A-Z]+[a-z]+$\", 1);\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if (v2)\n return \"No\";\n else\n return \"Yes\";\n}" + }, + { + "index": 482, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* text) {\n regex_t regex;\n int result;\n char* pattern = \"[A-Z]+[a-z]+$\";\n regcomp(®ex, pattern, REG_EXTENDED);\n result = regexec(®ex, text, 0, NULL, 0);\n regfree(®ex);\n if (result == 0) {\n return \"Yes\";\n } else {\n return \"No\";\n }\n}", + "test": "int main() {\n\n assert(func0(\"Geeks\") == \"Yes\");\n\n assert(func0(\"geeksforGeeks\") == \"Yes\");\n\n assert(func0(\"geeks\") == \"No\");\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x58,%rsp\nmov %rdi,%rbx\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%rbp\nmov $0x1,%edx\nlea 0xe16(%rip),%rsi\nmov %rbp,%rdi\ncallq 10c0 \nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rbx,%rsi\nmov %rbp,%rdi\ncallq 10d0 \nmov %eax,%ebx\nmov %rbp,%rdi\ncallq 1090 \ntest %ebx,%ebx\nlea 0xdd9(%rip),%rax\nlea 0xdd6(%rip),%rdx\ncmovne %rdx,%rax\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 124d \nadd $0x58,%rsp\npop %rbx\npop %rbp\nretq\ncallq 10a0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov edx, 1; cflags\nlea rsi, pattern; \"[A-Z]+[a-z]+$\"\nmov rdi, rbp; preg\ncall _regcomp\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov ebx, eax\nmov rdi, rbp; preg\ncall _regfree\ntest ebx, ebx\nlea rax, unk_2008\nlea rdx, unk_2004\ncmovz rax, rdx\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_124D\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_124D:\ncall ___stack_chk_fail", + "ida_pseudo": "void *__fastcall func0(char *string)\n{\n int v1; // ebx\n void *result; // rax\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \"[A-Z]+[a-z]+$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = &unk_2008;\n if ( !v1 )\n return &unk_2004;\n return result;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov edx, 1; cflags\nlea rsi, pattern; \"[A-Z]+[a-z]+$\"\nmov rdi, rbp; preg\ncall _regcomp\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov ebx, eax\nmov rdi, rbp; preg\ncall _regfree\ntest ebx, ebx\nlea rax, unk_2008\nlea rdx, unk_2004\ncmovz rax, rdx\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_124D\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_124D:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "void *__fastcall sub_11C9(char *string)\n{\n int v1; // ebx\n void *result; // rax\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \"[A-Z]+[a-z]+$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = &unk_2008;\n if ( !v1 )\n return &unk_2004;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_11C9(char *string) {\n int v1;\n void *result;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \"[A-Z]+[a-z]+$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = &unk_2008;\n if (!v1) return &unk_2004;\n return result;\n}", + "ida_pseudo_norm": "void *func0(char *string) {\n int v1;\n void *result;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \"[A-Z]+[a-z]+$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = &unk_2008;\n if (!v1) return &unk_2004;\n return result;\n}" + }, + { + "index": 482, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* text) {\n regex_t regex;\n int result;\n char* pattern = \"[A-Z]+[a-z]+$\";\n regcomp(®ex, pattern, REG_EXTENDED);\n result = regexec(®ex, text, 0, NULL, 0);\n regfree(®ex);\n if (result == 0) {\n return \"Yes\";\n } else {\n return \"No\";\n }\n}", + "test": "int main() {\n\n assert(func0(\"Geeks\") == \"Yes\");\n\n assert(func0(\"geeksforGeeks\") == \"Yes\");\n\n assert(func0(\"geeks\") == \"No\");\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov $0x1,%edx\nmov %rdi,%r12\nlea 0xd76(%rip),%rsi\npush %rbp\npush %rbx\nsub $0x50,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%rbp\nmov %rbp,%rdi\ncallq 10c0 \nxor %ecx,%ecx\nxor %edx,%edx\nxor %r8d,%r8d\nmov %r12,%rsi\nmov %rbp,%rdi\ncallq 10d0 \nmov %rbp,%rdi\nmov %eax,%ebx\ncallq 1090 \ntest %ebx,%ebx\nlea 0xd29(%rip),%rax\nlea 0xd26(%rip),%rdx\ncmovne %rdx,%rax\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 12ff \nadd $0x50,%rsp\npop %rbx\npop %rbp\npop %r12\nretq\ncallq 10a0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"[A-Z]+[a-z]+$\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, unk_2008\nlea rdx, unk_2004\ncmovz rax, rdx\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_12FB\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_12FB:\ncall ___stack_chk_fail", + "ida_pseudo": "void *__fastcall func0(char *string)\n{\n int v1; // ebx\n void *result; // rax\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \"[A-Z]+[a-z]+$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = &unk_2008;\n if ( !v1 )\n return &unk_2004;\n return result;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"[A-Z]+[a-z]+$\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, unk_2008\nlea rdx, unk_2004\ncmovz rax, rdx\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_12FB\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_12FB:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "void *__fastcall sub_1280(char *string)\n{\n int v1; // ebx\n void *result; // rax\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \"[A-Z]+[a-z]+$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = &unk_2008;\n if ( !v1 )\n return &unk_2004;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1280(char *string) {\n int v1;\n void *result;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \"[A-Z]+[a-z]+$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = &unk_2008;\n if (!v1) return &unk_2004;\n return result;\n}", + "ida_pseudo_norm": "void *func0(char *string) {\n int v1;\n void *result;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \"[A-Z]+[a-z]+$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = &unk_2008;\n if (!v1) return &unk_2004;\n return result;\n}" + }, + { + "index": 482, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* text) {\n regex_t regex;\n int result;\n char* pattern = \"[A-Z]+[a-z]+$\";\n regcomp(®ex, pattern, REG_EXTENDED);\n result = regexec(®ex, text, 0, NULL, 0);\n regfree(®ex);\n if (result == 0) {\n return \"Yes\";\n } else {\n return \"No\";\n }\n}", + "test": "int main() {\n\n assert(func0(\"Geeks\") == \"Yes\");\n\n assert(func0(\"geeksforGeeks\") == \"Yes\");\n\n assert(func0(\"geeks\") == \"No\");\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov $0x1,%edx\nmov %rdi,%r12\nlea 0xd76(%rip),%rsi\npush %rbp\npush %rbx\nsub $0x50,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%rbp\nmov %rbp,%rdi\ncallq 10c0 \nxor %ecx,%ecx\nxor %edx,%edx\nxor %r8d,%r8d\nmov %r12,%rsi\nmov %rbp,%rdi\ncallq 10d0 \nmov %rbp,%rdi\nmov %eax,%ebx\ncallq 1090 \ntest %ebx,%ebx\nlea 0xd29(%rip),%rax\nlea 0xd26(%rip),%rdx\ncmovne %rdx,%rax\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 12ff \nadd $0x50,%rsp\npop %rbx\npop %rbp\npop %r12\nretq\ncallq 10a0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"[A-Z]+[a-z]+$\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, unk_2008\nlea rdx, unk_2004\ncmovz rax, rdx\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_12FB\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_12FB:\ncall ___stack_chk_fail", + "ida_pseudo": "void *__fastcall func0(char *string)\n{\n int v1; // ebx\n void *result; // rax\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \"[A-Z]+[a-z]+$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = &unk_2008;\n if ( !v1 )\n return &unk_2004;\n return result;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"[A-Z]+[a-z]+$\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, unk_2008\nlea rdx, unk_2004\ncmovz rax, rdx\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_12FB\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_12FB:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "void *__fastcall sub_1280(char *string)\n{\n int v1; // ebx\n void *result; // rax\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \"[A-Z]+[a-z]+$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = &unk_2008;\n if ( !v1 )\n return &unk_2004;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1280(char *string) {\n int v1;\n void *result;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \"[A-Z]+[a-z]+$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = &unk_2008;\n if (!v1) return &unk_2004;\n return result;\n}", + "ida_pseudo_norm": "void *func0(char *string) {\n int v1;\n void *result;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \"[A-Z]+[a-z]+$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = &unk_2008;\n if (!v1) return &unk_2004;\n return result;\n}" + }, + { + "index": 483, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int x) {\n int i = 1;\n int fact = 1;\n for (i = 1; i < x; i++) {\n fact = fact * i;\n if (fact % x == 0) {\n return i;\n }\n }\n return i - 1;\n}", + "test": "int main() {\n\n assert(func0(10) == 5);\n\n assert(func0(15) == 5);\n\n assert(func0(5) == 4);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmovl $0x1,-0x8(%rbp)\nmovl $0x1,-0x4(%rbp)\nmovl $0x1,-0x8(%rbp)\njmp 118b \nmov -0x4(%rbp),%eax\nimul -0x8(%rbp),%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncltd\nidivl -0x14(%rbp)\nmov %edx,%eax\ntest %eax,%eax\njne 1187 \nmov -0x8(%rbp),%eax\njmp 1199 \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x14(%rbp),%eax\njl 116b \nmov -0x8(%rbp),%eax\nsub $0x1,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_8], 1\nmov [rbp+var_4], 1\nmov [rbp+var_8], 1\njmp short loc_118B\nloc_116B:\nmov eax, [rbp+var_4]\nimul eax, [rbp+var_8]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncdq\nidiv [rbp+var_14]\nmov eax, edx\ntest eax, eax\njnz short loc_1187\nmov eax, [rbp+var_8]\njmp short loc_1199\nloc_1187:\nadd [rbp+var_8], 1\nloc_118B:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_14]\njl short loc_116B\nmov eax, [rbp+var_8]\nsub eax, 1\nloc_1199:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int i; // [rsp+Ch] [rbp-8h]\n int v3; // [rsp+10h] [rbp-4h]\n\n v3 = 1;\n for ( i = 1; i < a1; ++i )\n {\n v3 *= i;\n if ( !(v3 % a1) )\n return (unsigned int)i;\n }\n return (unsigned int)(i - 1);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_8], 1\nmov [rbp+var_4], 1\nmov [rbp+var_8], 1\njmp short loc_118B\nloc_116B:\nmov eax, [rbp+var_4]\nimul eax, [rbp+var_8]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncdq\nidiv [rbp+var_14]\nmov eax, edx\ntest eax, eax\njnz short loc_1187\nmov eax, [rbp+var_8]\njmp short loc_1199\nloc_1187:\nadd [rbp+var_8], 1\nloc_118B:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_14]\njl short loc_116B\nmov eax, [rbp+var_8]\nsub eax, 1\nloc_1199:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int i; // [rsp+Ch] [rbp-8h]\n int v3; // [rsp+10h] [rbp-4h]\n\n v3 = 1;\n for ( i = 1; i < a1; ++i )\n {\n v3 *= i;\n if ( !(v3 % a1) )\n return (unsigned int)i;\n }\n return (unsigned int)(i - 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int i;\n int v3;\n v3 = 1;\n for (i = 1; i < a1; ++i) {\n v3 *= i;\n if (!(v3 % a1)) return (unsigned int)i;\n }\n return (unsigned int)(i - 1);\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int i;\n int v3;\n v3 = 1;\n for (i = 1; i < a1; ++i) {\n v3 *= i;\n if (!(v3 % a1)) return (unsigned int)i;\n }\n return (unsigned int)(i - 1);\n}" + }, + { + "index": 483, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int x) {\n int i = 1;\n int fact = 1;\n for (i = 1; i < x; i++) {\n fact = fact * i;\n if (fact % x == 0) {\n return i;\n }\n }\n return i - 1;\n}", + "test": "int main() {\n\n assert(func0(10) == 5);\n\n assert(func0(15) == 5);\n\n assert(func0(5) == 4);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%edi\njle 1177 \nmov $0x1,%eax\ncltd\nidiv %edi\nmov %edx,%esi\ntest %edx,%edx\nje 1182 \nmov %edx,%ecx\nadd $0x1,%esi\ncmp %esi,%edi\nje 117c \nimul %esi,%ecx\nmov %ecx,%eax\ncltd\nidiv %edi\ntest %edx,%edx\njne 1162 \njmp 117f \nmov $0x1,%esi\nsub $0x1,%esi\nmov %esi,%eax\nretq\nmov $0x1,%esi\njmp 117f \n", + "ida_asm": "func0:\nendbr64\ncmp edi, 1\njle short loc_117B\nmov eax, 1\nmov edx, 0\nidiv edi\nmov esi, edx\ntest edx, edx\njz short loc_1186\nmov ecx, edx\nloc_1166:\nadd esi, 1\ncmp edi, esi\njz short loc_1180\nimul ecx, esi\nmov eax, ecx\ncdq\nidiv edi\ntest edx, edx\njnz short loc_1166\njmp short loc_1183\nloc_117B:\nmov edi, 1\nloc_1180:\nlea esi, [rdi-1]\nloc_1183:\nmov eax, esi\nretn\nloc_1186:\nmov esi, 1\njmp short loc_1183", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v1; // esi\n int v2; // ecx\n\n if ( a1 <= 1 )\n {\n a1 = 1;\n }\n else\n {\n v1 = 1 % a1;\n if ( !(1 % a1) )\n return 1;\n v2 = 1 % a1;\n while ( a1 != ++v1 )\n {\n v2 *= v1;\n if ( !(v2 % a1) )\n return v1;\n }\n }\n return (unsigned int)(a1 - 1);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ncmp edi, 1\njle short loc_117B\nmov eax, 1\nmov edx, 0\nidiv edi\nmov esi, edx\ntest edx, edx\njz short loc_1186\nmov ecx, edx\nloc_1166:\nadd esi, 1\ncmp edi, esi\njz short loc_1180\nimul ecx, esi\nmov eax, ecx\ncdq\nidiv edi\ntest edx, edx\njnz short loc_1166\njmp short loc_1183\nloc_117B:\nmov edi, 1\nloc_1180:\nlea esi, [rdi-1]\nloc_1183:\nmov eax, esi\nretn\nloc_1186:\nmov esi, 1\njmp short loc_1183", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n unsigned int v1; // esi\n int v2; // ecx\n\n if ( a1 <= 1 )\n {\n a1 = 1;\n }\n else\n {\n v1 = 1 % a1;\n if ( !(1 % a1) )\n return 1;\n v2 = 1 % a1;\n while ( a1 != ++v1 )\n {\n v2 *= v1;\n if ( !(v2 % a1) )\n return v1;\n }\n }\n return (unsigned int)(a1 - 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n unsigned int v1;\n int v2;\n if (a1 <= 1) {\n a1 = 1;\n } else {\n v1 = 1 % a1;\n if (!(1 % a1)) return 1;\n v2 = 1 % a1;\n while (a1 != ++v1) {\n v2 *= v1;\n if (!(v2 % a1)) return v1;\n }\n }\n return (unsigned int)(a1 - 1);\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v1;\n int v2;\n if (a1 <= 1) {\n a1 = 1;\n } else {\n v1 = 1 % a1;\n if (!(1 % a1)) return 1;\n v2 = 1 % a1;\n while (a1 != ++v1) {\n v2 *= v1;\n if (!(v2 % a1)) return v1;\n }\n }\n return (unsigned int)(a1 - 1);\n}" + }, + { + "index": 484, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char* first;\n\n char* second;\n\n} Tuple;\n\n\n\n", + "func": "Tuple* func0(Tuple* test_list1, int size1, Tuple* test_list2, int size2,\n int* res_size) {\n Tuple* res = malloc(size1 * sizeof(Tuple));\n int count = 0;\n for (int i = 0; i < size1; i++) {\n int found = 0;\n for (int j = 0; j < size2; j++) {\n if (strcmp(test_list1[i].first, test_list2[j].first) == 0 &&\n strcmp(test_list1[i].second, test_list2[j].second) == 0) {\n found = 1;\n break;\n }\n }\n if (!found) {\n res[count++] = test_list1[i];\n }\n }\n *res_size = count;\n return res;\n}", + "test": "int main(){\n\n // Test case 1\n\n Tuple test1_1[] = { {\"Hello\", \"dude\"}, {\"How\", \"are\"}, {\"you\", \"?\"} };\n\n Tuple test2_1[] = { {\"Hello\", \"dude\"}, {\"How\", \"are\"} };\n\n int res_size1;\n\n Tuple* res1 = func0(test1_1, 3, test2_1, 2, &res_size1);\n\n Tuple expected1[] = { {\"you\", \"?\"} };\n\n assert(res_size1 == 1);\n\n assert(strcmp(res1[0].first, expected1[0].first) == 0);\n\n assert(strcmp(res1[0].second, expected1[0].second) == 0);\n\n free(res1);\n\n \n\n // Test case 2\n\n Tuple test1_2[] = { {\"Part\", \"of\"}, {\"the\", \"journey\"}, {\"is \", \"end\"} };\n\n Tuple test2_2[] = { {\"Journey\", \"the\"}, {\"is\", \"end\"} };\n\n int res_size2;\n\n Tuple* res2 = func0(test1_2, 3, test2_2, 2, &res_size2);\n\n Tuple expected2[] = { {\"Part\", \"of\"}, {\"the\", \"journey\"}, {\"is \", \"end\"} };\n\n assert(res_size2 == 3);\n\n for(int i = 0; i < res_size2; i++) {\n\n assert(strcmp(res2[i].first, expected2[i].first) == 0);\n\n assert(strcmp(res2[i].second, expected2[i].second) == 0);\n\n }\n\n free(res2);\n\n \n\n // Test case 3\n\n Tuple test1_3[] = { {\"Its\", \"been\"}, {\"a\", \"long\"}, {\"day\", \"without\"} };\n\n Tuple test2_3[] = { {\"a\", \"long\"}, {\"my\", \"friend\"} };\n\n int res_size3;\n\n Tuple* res3 = func0(test1_3, 3, test2_3, 2, &res_size3);\n\n Tuple expected3[] = { {\"Its\", \"been\"}, {\"day\", \"without\"} };\n\n assert(res_size3 == 2);\n\n for(int i = 0; i < res_size3; i++) {\n\n assert(strcmp(res3[i].first, expected3[i].first) == 0);\n\n assert(strcmp(res3[i].second, expected3[i].second) == 0);\n\n }\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x40,%rsp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmov %rdx,-0x38(%rbp)\nmov %ecx,-0x30(%rbp)\nmov %r8,-0x40(%rbp)\nmov -0x2c(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0x18(%rbp)\nmovl $0x0,-0x14(%rbp)\njmpq 12f9 \nmovl $0x0,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\njmpq 12a7 \nmov -0xc(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rdx\nmov -0x14(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10c0 \ntest %eax,%eax\njne 12a3 \nmov -0xc(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov 0x8(%rax),%rdx\nmov -0x14(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov 0x8(%rax),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10c0 \ntest %eax,%eax\njne 12a3 \nmovl $0x1,-0x10(%rbp)\njmp 12b3 \naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x30(%rbp),%eax\njl 1222 \ncmpl $0x0,-0x10(%rbp)\njne 12f5 \nmov -0x14(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x28(%rbp),%rax\nlea (%rdx,%rax,1),%rsi\nmov -0x18(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x18(%rbp)\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x8(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov (%rsi),%rax\nmov 0x8(%rsi),%rdx\nmov %rax,(%rcx)\nmov %rdx,0x8(%rcx)\naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 120f \nmov -0x40(%rbp),%rax\nmov -0x18(%rbp),%edx\nmov %edx,(%rax)\nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmov [rbp+var_30], ecx\nmov [rbp+var_40], r8\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 4\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp loc_12F9\nloc_120F:\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp loc_12A7\nloc_1222:\nmov eax, [rbp+var_C]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_14]\ncdqe\nshl rax, 4\nmov rcx, rax\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_12A3\nmov eax, [rbp+var_C]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rdx, [rax+8]\nmov eax, [rbp+var_14]\ncdqe\nshl rax, 4\nmov rcx, rax\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov rax, [rax+8]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_12A3\nmov [rbp+var_10], 1\njmp short loc_12B3\nloc_12A3:\nadd [rbp+var_C], 1\nloc_12A7:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_30]\njl loc_1222\nloc_12B3:\ncmp [rbp+var_10], 0\njnz short loc_12F5\nmov eax, [rbp+var_14]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_28]\nlea rsi, [rdx+rax]\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_8]\nlea rcx, [rdx+rax]\nmov rax, [rsi]\nmov rdx, [rsi+8]\nmov [rcx], rax\nmov [rcx+8], rdx\nloc_12F5:\nadd [rbp+var_14], 1\nloc_12F9:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl loc_120F\nmov rax, [rbp+var_40]\nmov edx, [rbp+var_18]\nmov [rax], edx\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2, __int64 a3, int a4, _DWORD *a5)\n{\n _QWORD *v5; // rsi\n int v6; // eax\n char *v7; // rcx\n __int64 v8; // rdx\n int v14; // [rsp+28h] [rbp-18h]\n int i; // [rsp+2Ch] [rbp-14h]\n int v16; // [rsp+30h] [rbp-10h]\n int j; // [rsp+34h] [rbp-Ch]\n char *v18; // [rsp+38h] [rbp-8h]\n\n v18 = (char *)malloc(16LL * a2);\n v14 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v16 = 0;\n for ( j = 0; j < a4; ++j )\n {\n if ( !strcmp(*(const char **)(16LL * i + a1), *(const char **)(16LL * j + a3))\n && !strcmp(*(const char **)(16LL * i + a1 + 8), *(const char **)(16LL * j + a3 + 8)) )\n {\n v16 = 1;\n break;\n }\n }\n if ( !v16 )\n {\n v5 = (_QWORD *)(16LL * i + a1);\n v6 = v14++;\n v7 = &v18[16 * v6];\n v8 = v5[1];\n *(_QWORD *)v7 = *v5;\n *((_QWORD *)v7 + 1) = v8;\n }\n }\n *a5 = v14;\n return v18;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmov [rbp+var_30], ecx\nmov [rbp+var_40], r8\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 4\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp loc_12F9\nloc_120F:\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp loc_12A7\nloc_1222:\nmov eax, [rbp+var_C]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_14]\ncdqe\nshl rax, 4\nmov rcx, rax\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_12A3\nmov eax, [rbp+var_C]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rdx, [rax+8]\nmov eax, [rbp+var_14]\ncdqe\nshl rax, 4\nmov rcx, rax\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov rax, [rax+8]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_12A3\nmov [rbp+var_10], 1\njmp short loc_12B3\nloc_12A3:\nadd [rbp+var_C], 1\nloc_12A7:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_30]\njl loc_1222\nloc_12B3:\ncmp [rbp+var_10], 0\njnz short loc_12F5\nmov eax, [rbp+var_14]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_28]\nlea rsi, [rdx+rax]\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_8]\nlea rcx, [rdx+rax]\nmov rax, [rsi]\nmov rdx, [rsi+8]\nmov [rcx], rax\nmov [rcx+8], rdx\nloc_12F5:\nadd [rbp+var_14], 1\nloc_12F9:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl loc_120F\nmov rax, [rbp+var_40]\nmov edx, [rbp+var_18]\nmov [rax], edx\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11C9(__int64 a1, int a2, __int64 a3, int a4, _DWORD *a5)\n{\n _QWORD *v5; // rsi\n int v6; // eax\n char *v7; // rcx\n __int64 v8; // rdx\n int v14; // [rsp+28h] [rbp-18h]\n int i; // [rsp+2Ch] [rbp-14h]\n int v16; // [rsp+30h] [rbp-10h]\n int j; // [rsp+34h] [rbp-Ch]\n char *v18; // [rsp+38h] [rbp-8h]\n\n v18 = (char *)malloc(16LL * a2);\n v14 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v16 = 0;\n for ( j = 0; j < a4; ++j )\n {\n if ( !strcmp(*(const char **)(16LL * i + a1), *(const char **)(16LL * j + a3))\n && !strcmp(*(const char **)(16LL * i + a1 + 8), *(const char **)(16LL * j + a3 + 8)) )\n {\n v16 = 1;\n break;\n }\n }\n if ( !v16 )\n {\n v5 = (_QWORD *)(16LL * i + a1);\n v6 = v14++;\n v7 = &v18[16 * v6];\n v8 = v5[1];\n *(_QWORD *)v7 = *v5;\n *((_QWORD *)v7 + 1) = v8;\n }\n }\n *a5 = v14;\n return v18;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11C9(long long a1, int a2, long long a3, int a4, uint32_t *a5) {\n uint64_t *v5;\n int v6;\n char *v7;\n long long v8;\n int v14;\n int i;\n int v16;\n int j;\n char *v18;\n v18 = (char *)malloc(16LL * a2);\n v14 = 0;\n for (i = 0; i < a2; ++i) {\n v16 = 0;\n for (j = 0; j < a4; ++j) {\n if (!strcmp(*(const char **)(16LL * i + a1),\n *(const char **)(16LL * j + a3)) &&\n !strcmp(*(const char **)(16LL * i + a1 + 8),\n *(const char **)(16LL * j + a3 + 8))) {\n v16 = 1;\n break;\n }\n }\n if (!v16) {\n v5 = (uint64_t *)(16LL * i + a1);\n v6 = v14++;\n v7 = &v18[16 * v6];\n v8 = v5[1];\n *(uint64_t *)v7 = *v5;\n *((uint64_t *)v7 + 1) = v8;\n }\n }\n *a5 = v14;\n return v18;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2, long long a3, int a4, uint32_t *a5) {\n uint64_t *v5;\n int v6;\n char *v7;\n long long v8;\n int v14;\n int i;\n int v16;\n int j;\n char *v18;\n v18 = (char *)malloc(16LL * a2);\n v14 = 0;\n for (i = 0; i < a2; ++i) {\n v16 = 0;\n for (j = 0; j < a4; ++j) {\n if (!strcmp(*(const char **)(16LL * i + a1),\n *(const char **)(16LL * j + a3)) &&\n !strcmp(*(const char **)(16LL * i + a1 + 8),\n *(const char **)(16LL * j + a3 + 8))) {\n v16 = 1;\n break;\n }\n }\n if (!v16) {\n v5 = (uint64_t *)(16LL * i + a1);\n v6 = v14++;\n v7 = &v18[16 * v6];\n v8 = v5[1];\n *(uint64_t *)v7 = *v5;\n *((uint64_t *)v7 + 1) = v8;\n }\n }\n *a5 = v14;\n return v18;\n}" + }, + { + "index": 484, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char* first;\n\n char* second;\n\n} Tuple;\n\n\n\n", + "func": "Tuple* func0(Tuple* test_list1, int size1, Tuple* test_list2, int size2,\n int* res_size) {\n Tuple* res = malloc(size1 * sizeof(Tuple));\n int count = 0;\n for (int i = 0; i < size1; i++) {\n int found = 0;\n for (int j = 0; j < size2; j++) {\n if (strcmp(test_list1[i].first, test_list2[j].first) == 0 &&\n strcmp(test_list1[i].second, test_list2[j].second) == 0) {\n found = 1;\n break;\n }\n }\n if (!found) {\n res[count++] = test_list1[i];\n }\n }\n *res_size = count;\n return res;\n}", + "test": "int main(){\n\n // Test case 1\n\n Tuple test1_1[] = { {\"Hello\", \"dude\"}, {\"How\", \"are\"}, {\"you\", \"?\"} };\n\n Tuple test2_1[] = { {\"Hello\", \"dude\"}, {\"How\", \"are\"} };\n\n int res_size1;\n\n Tuple* res1 = func0(test1_1, 3, test2_1, 2, &res_size1);\n\n Tuple expected1[] = { {\"you\", \"?\"} };\n\n assert(res_size1 == 1);\n\n assert(strcmp(res1[0].first, expected1[0].first) == 0);\n\n assert(strcmp(res1[0].second, expected1[0].second) == 0);\n\n free(res1);\n\n \n\n // Test case 2\n\n Tuple test1_2[] = { {\"Part\", \"of\"}, {\"the\", \"journey\"}, {\"is \", \"end\"} };\n\n Tuple test2_2[] = { {\"Journey\", \"the\"}, {\"is\", \"end\"} };\n\n int res_size2;\n\n Tuple* res2 = func0(test1_2, 3, test2_2, 2, &res_size2);\n\n Tuple expected2[] = { {\"Part\", \"of\"}, {\"the\", \"journey\"}, {\"is \", \"end\"} };\n\n assert(res_size2 == 3);\n\n for(int i = 0; i < res_size2; i++) {\n\n assert(strcmp(res2[i].first, expected2[i].first) == 0);\n\n assert(strcmp(res2[i].second, expected2[i].second) == 0);\n\n }\n\n free(res2);\n\n \n\n // Test case 3\n\n Tuple test1_3[] = { {\"Its\", \"been\"}, {\"a\", \"long\"}, {\"day\", \"without\"} };\n\n Tuple test2_3[] = { {\"a\", \"long\"}, {\"my\", \"friend\"} };\n\n int res_size3;\n\n Tuple* res3 = func0(test1_3, 3, test2_3, 2, &res_size3);\n\n Tuple expected3[] = { {\"Its\", \"been\"}, {\"day\", \"without\"} };\n\n assert(res_size3 == 2);\n\n for(int i = 0; i < res_size3; i++) {\n\n assert(strcmp(res3[i].first, expected3[i].first) == 0);\n\n assert(strcmp(res3[i].second, expected3[i].second) == 0);\n\n }\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x38,%rsp\nmov %rdi,%r12\nmov %esi,%ebp\nmov %rdx,%rbx\nmov %ecx,%r15d\nmov %ecx,0xc(%rsp)\nmov %r8,0x28(%rsp)\nmovslq %esi,%rdi\nshl $0x4,%rdi\ncallq 10d0 \nmov %rax,0x20(%rsp)\ntest %ebp,%ebp\njle 125d \nmov %r12,%r14\nlea -0x1(%rbp),%eax\nshl $0x4,%rax\nlea 0x10(%r12,%rax,1),%rax\nmov %rax,0x10(%rsp)\nmov %rbx,0x18(%rsp)\nlea -0x1(%r15),%eax\nshl $0x4,%rax\nlea 0x10(%rbx,%rax,1),%r12\nmov $0x0,%r15d\njmp 12a3 \nadd $0x10,%rbx\ncmp %r12,%rbx\nje 127f \nmov (%rbx),%rsi\nmov %rbp,%rdi\ncallq 10c0 \ntest %eax,%eax\njne 1232 \nmov 0x8(%rbx),%rsi\nmov 0x8(%r13),%rdi\ncallq 10c0 \ntest %eax,%eax\njne 1232 \njmp 1298 \nmov $0x0,%r15d\nmov 0x28(%rsp),%rax\nmov %r15d,(%rax)\nmov 0x20(%rsp),%rax\nadd $0x38,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmovslq %r15d,%rax\nshl $0x4,%rax\nmov 0x20(%rsp),%rdx\nmovdqu (%r14),%xmm0\nmovups %xmm0,(%rdx,%rax,1)\nlea 0x1(%r15),%r15d\nadd $0x10,%r14\ncmp 0x10(%rsp),%r14\nje 1263 \ncmpl $0x0,0xc(%rsp)\njle 127f \nmov %r14,%r13\nmov (%r14),%rbp\nmov 0x18(%rsp),%rbx\njmp 123b \n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 38h\nmov rbp, rdi\nmov r12d, esi\nmov r13, rdx\nmov [rsp+68h+var_50], rdx\nmov r15d, ecx\nmov [rsp+68h+var_5C], ecx\nmov [rsp+68h+var_40], r8\nmovsxd rbx, esi\nshl rbx, 4\nmov rdi, rbx; size\ncall _malloc\nmov [rsp+68h+var_48], rax\ntest r12d, r12d\njle loc_1297\nmov r14, rbp\nlea rax, [rbp+rbx+0]\nmov [rsp+68h+var_58], rax\nmovsxd r12, r15d\nshl r12, 4\nadd r12, r13\nmov r15d, 0\njmp short loc_1283\nloc_1231:\nadd rbx, 10h\ncmp rbx, r12\njz short loc_125C\nloc_123A:\nmov rsi, [rbx]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1231\nmov rsi, [rbx+8]; s2\nmov rdi, [r13+8]; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1231\njmp short loc_1275\nloc_125C:\nmovsxd rax, r15d\nshl rax, 4\nmov rdx, [rsp+68h+var_48]\nmovdqu xmm0, xmmword ptr [r14]\nmovups xmmword ptr [rdx+rax], xmm0\nlea r15d, [r15+1]\nloc_1275:\nadd r14, 10h\nmov rax, [rsp+68h+var_58]\ncmp r14, rax\njz short loc_129D\nloc_1283:\ncmp [rsp+68h+var_5C], 0\njle short loc_125C\nmov r13, r14\nmov rbp, [r14]\nmov rbx, [rsp+68h+var_50]\njmp short loc_123A\nloc_1297:\nmov r15d, 0\nloc_129D:\nmov rax, [rsp+68h+var_40]\nmov [rax], r15d\nmov rax, [rsp+68h+var_48]\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "__m128i *__fastcall func0(__int64 a1, int a2, const char **a3, int a4, _DWORD *a5)\n{\n __int64 v7; // r14\n const char **v8; // r12\n int v9; // r15d\n const char **v10; // rbx\n const char *v11; // rbp\n __m128i *v15; // [rsp+20h] [rbp-48h]\n\n v15 = (__m128i *)malloc(16LL * a2);\n if ( a2 <= 0 )\n {\n v9 = 0;\n }\n else\n {\n v7 = a1;\n v8 = &a3[2 * a4];\n v9 = 0;\n do\n {\n if ( a4 <= 0 )\n {\nLABEL_7:\n v15[v9++] = _mm_loadu_si128((const __m128i *)v7);\n }\n else\n {\n v11 = *(const char **)v7;\n v10 = a3;\n while ( strcmp(v11, *v10) || strcmp(*(const char **)(v7 + 8), v10[1]) )\n {\n v10 += 2;\n if ( v10 == v8 )\n goto LABEL_7;\n }\n }\n v7 += 16LL;\n }\n while ( v7 != a1 + 16LL * a2 );\n }\n *a5 = v9;\n return v15;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 38h\nmov rbp, rdi\nmov r12d, esi\nmov r13, rdx\nmov [rsp+68h+var_50], rdx\nmov r15d, ecx\nmov [rsp+68h+var_5C], ecx\nmov [rsp+68h+var_40], r8\nmovsxd rbx, esi\nshl rbx, 4\nmov rdi, rbx; size\ncall _malloc\nmov [rsp+68h+var_48], rax\ntest r12d, r12d\njle loc_1297\nmov r14, rbp\nlea rax, [rbp+rbx+0]\nmov [rsp+68h+var_58], rax\nmovsxd r12, r15d\nshl r12, 4\nadd r12, r13\nmov r15d, 0\njmp short loc_1283\nloc_1231:\nadd rbx, 10h\ncmp rbx, r12\njz short loc_125C\nloc_123A:\nmov rsi, [rbx]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1231\nmov rsi, [rbx+8]; s2\nmov rdi, [r13+8]; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1231\njmp short loc_1275\nloc_125C:\nmovsxd rax, r15d\nshl rax, 4\nmov rdx, [rsp+68h+var_48]\nmovdqu xmm0, xmmword ptr [r14]\nmovups xmmword ptr [rdx+rax], xmm0\nlea r15d, [r15+1]\nloc_1275:\nadd r14, 10h\nmov rax, [rsp+68h+var_58]\ncmp r14, rax\njz short loc_129D\nloc_1283:\ncmp [rsp+68h+var_5C], 0\njle short loc_125C\nmov r13, r14\nmov rbp, [r14]\nmov rbx, [rsp+68h+var_50]\njmp short loc_123A\nloc_1297:\nmov r15d, 0\nloc_129D:\nmov rax, [rsp+68h+var_40]\nmov [rax], r15d\nmov rax, [rsp+68h+var_48]\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "__m128i *__fastcall sub_11C9(__int64 a1, int a2, const char **a3, int a4, _DWORD *a5)\n{\n __int64 v7; // r14\n const char **v8; // r12\n int v9; // r15d\n const char **v10; // rbx\n const char *v11; // rbp\n __m128i *v15; // [rsp+20h] [rbp-48h]\n\n v15 = (__m128i *)malloc(16LL * a2);\n if ( a2 <= 0 )\n {\n v9 = 0;\n }\n else\n {\n v7 = a1;\n v8 = &a3[2 * a4];\n v9 = 0;\n do\n {\n if ( a4 <= 0 )\n {\nLABEL_7:\n v15[v9++] = _mm_loadu_si128((const __m128i *)v7);\n }\n else\n {\n v11 = *(const char **)v7;\n v10 = a3;\n while ( strcmp(v11, *v10) || strcmp(*(const char **)(v7 + 8), v10[1]) )\n {\n v10 += 2;\n if ( v10 == v8 )\n goto LABEL_7;\n }\n }\n v7 += 16LL;\n }\n while ( v7 != a1 + 16LL * a2 );\n }\n *a5 = v9;\n return v15;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__m128i *sub_11C9(long long a1, int a2, const char **a3, int a4, uint32_t *a5) {\n long long v7;\n const char **v8;\n int v9;\n const char **v10;\n const char *v11;\n __m128i *v15;\n v15 = (__m128i *)malloc(16LL * a2);\n if (a2 <= 0) {\n v9 = 0;\n } else {\n v7 = a1;\n v8 = &a3[2 * a4];\n v9 = 0;\n do {\n if (a4 <= 0) {\n LABEL_7:\n v15[v9++] = _mm_loadu_si128((const __m128i *)v7);\n } else {\n v11 = *(const char **)v7;\n v10 = a3;\n while (strcmp(v11, *v10) || strcmp(*(const char **)(v7 + 8), v10[1])) {\n v10 += 2;\n if (v10 == v8) goto LABEL_7;\n }\n }\n v7 += 16LL;\n } while (v7 != a1 + 16LL * a2);\n }\n *a5 = v9;\n return v15;\n}", + "ida_pseudo_norm": "__m128i *func0(long long a1, int a2, const char **a3, int a4, uint32_t *a5) {\n long long v7;\n const char **v8;\n int v9;\n const char **v10;\n const char *v11;\n __m128i *v15;\n v15 = (__m128i *)malloc(16LL * a2);\n if (a2 <= 0) {\n v9 = 0;\n } else {\n v7 = a1;\n v8 = &a3[2 * a4];\n v9 = 0;\n do {\n if (a4 <= 0) {\n LABEL_7:\n v15[v9++] = _mm_loadu_si128((const __m128i *)v7);\n } else {\n v11 = *(const char **)v7;\n v10 = a3;\n while (strcmp(v11, *v10) || strcmp(*(const char **)(v7 + 8), v10[1])) {\n v10 += 2;\n if (v10 == v8) goto LABEL_7;\n }\n }\n v7 += 16LL;\n } while (v7 != a1 + 16LL * a2);\n }\n *a5 = v9;\n return v15;\n}" + }, + { + "index": 484, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char* first;\n\n char* second;\n\n} Tuple;\n\n\n\n", + "func": "Tuple* func0(Tuple* test_list1, int size1, Tuple* test_list2, int size2,\n int* res_size) {\n Tuple* res = malloc(size1 * sizeof(Tuple));\n int count = 0;\n for (int i = 0; i < size1; i++) {\n int found = 0;\n for (int j = 0; j < size2; j++) {\n if (strcmp(test_list1[i].first, test_list2[j].first) == 0 &&\n strcmp(test_list1[i].second, test_list2[j].second) == 0) {\n found = 1;\n break;\n }\n }\n if (!found) {\n res[count++] = test_list1[i];\n }\n }\n *res_size = count;\n return res;\n}", + "test": "int main(){\n\n // Test case 1\n\n Tuple test1_1[] = { {\"Hello\", \"dude\"}, {\"How\", \"are\"}, {\"you\", \"?\"} };\n\n Tuple test2_1[] = { {\"Hello\", \"dude\"}, {\"How\", \"are\"} };\n\n int res_size1;\n\n Tuple* res1 = func0(test1_1, 3, test2_1, 2, &res_size1);\n\n Tuple expected1[] = { {\"you\", \"?\"} };\n\n assert(res_size1 == 1);\n\n assert(strcmp(res1[0].first, expected1[0].first) == 0);\n\n assert(strcmp(res1[0].second, expected1[0].second) == 0);\n\n free(res1);\n\n \n\n // Test case 2\n\n Tuple test1_2[] = { {\"Part\", \"of\"}, {\"the\", \"journey\"}, {\"is \", \"end\"} };\n\n Tuple test2_2[] = { {\"Journey\", \"the\"}, {\"is\", \"end\"} };\n\n int res_size2;\n\n Tuple* res2 = func0(test1_2, 3, test2_2, 2, &res_size2);\n\n Tuple expected2[] = { {\"Part\", \"of\"}, {\"the\", \"journey\"}, {\"is \", \"end\"} };\n\n assert(res_size2 == 3);\n\n for(int i = 0; i < res_size2; i++) {\n\n assert(strcmp(res2[i].first, expected2[i].first) == 0);\n\n assert(strcmp(res2[i].second, expected2[i].second) == 0);\n\n }\n\n free(res2);\n\n \n\n // Test case 3\n\n Tuple test1_3[] = { {\"Its\", \"been\"}, {\"a\", \"long\"}, {\"day\", \"without\"} };\n\n Tuple test2_3[] = { {\"a\", \"long\"}, {\"my\", \"friend\"} };\n\n int res_size3;\n\n Tuple* res3 = func0(test1_3, 3, test2_3, 2, &res_size3);\n\n Tuple expected3[] = { {\"Its\", \"been\"}, {\"day\", \"without\"} };\n\n assert(res_size3 == 2);\n\n for(int i = 0; i < res_size3; i++) {\n\n assert(strcmp(res3[i].first, expected3[i].first) == 0);\n\n assert(strcmp(res3[i].second, expected3[i].second) == 0);\n\n }\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmov %rdx,%r15\npush %r14\nmov %ecx,%r14d\npush %r13\npush %r12\nmov %rdi,%r12\nmovslq %esi,%rdi\npush %rbp\npush %rbx\nmov %rdi,%rbx\nshl $0x4,%rdi\nsub $0x28,%rsp\nmov %rdx,0x8(%rsp)\nmov %r8,0x18(%rsp)\ncallq 10d0 \nmov %rax,0x10(%rsp)\ntest %ebx,%ebx\njle 174a \nlea -0x1(%rbx),%eax\nxor %r13d,%r13d\nshl $0x4,%rax\nlea 0x10(%r12,%rax,1),%rax\nmov %rax,(%rsp)\nlea -0x1(%r14),%eax\nshl $0x4,%rax\nlea 0x10(%r15,%rax,1),%rbp\nnopl 0x0(%rax)\ntest %r14d,%r14d\njle 170a \nmov (%r12),%rbx\nmov 0x8(%rsp),%r15\nnopw %cs:0x0(%rax,%rax,1)\nmov (%r15),%rsi\nmov %rbx,%rdi\ncallq 10c0 \ntest %eax,%eax\njne 1701 \nmov 0x8(%r15),%rsi\nmov 0x8(%r12),%rdi\ncallq 10c0 \ntest %eax,%eax\nje 1724 \nadd $0x10,%r15\ncmp %rbp,%r15\njne 16e0 \nmovslq %r13d,%rax\nmov 0x10(%rsp),%rdx\nmovdqu (%r12),%xmm0\nadd $0x1,%r13d\nshl $0x4,%rax\nmovups %xmm0,(%rdx,%rax,1)\nadd $0x10,%r12\ncmp (%rsp),%r12\njne 16c8 \nmov 0x18(%rsp),%rax\nmov %r13d,(%rax)\nmov 0x10(%rsp),%rax\nadd $0x28,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nxor %r13d,%r13d\njmp 172e \n", + "ida_asm": "func0:\nendbr64\npush r15\nmov r15d, ecx\npush r14\nmovsxd r14, esi\npush r13\nmov r13, rdx\npush r12\nmov r12, rdi\npush rbp\npush rbx\nmov rbx, r14\nshl r14, 4\nmov rdi, r14; size\nsub rsp, 28h\nmov [rsp+58h+var_58], rdx\nmov [rsp+58h+var_44], ecx\nmov [rsp+58h+var_40], r8\ncall _malloc\nmov [rsp+58h+var_50], rax\ntest ebx, ebx\njle loc_17D7\nmovsxd rbp, r15d\nadd r14, r12\nshl rbp, 4\nadd rbp, r13\nxor r13d, r13d\nnop word ptr [rax+rax+00000000h]\nloc_1750:\nmov eax, [rsp+58h+var_44]\ntest eax, eax\njle short loc_178A\nloc_1758:\nmov rbx, [r12]\nmov r15, [rsp+58h+var_58]\nloc_1760:\nmov rsi, [r15]; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1781\nmov rsi, [r15+8]; s2\nmov rdi, [r12+8]; s1\ncall _strcmp\ntest eax, eax\njz short loc_17B0\nloc_1781:\nadd r15, 10h\ncmp r15, rbp\njnz short loc_1760\nloc_178A:\nmovdqu xmm0, xmmword ptr [r12]\nmov rdx, [rsp+58h+var_50]\nlea eax, [r13+1]\nadd r12, 10h\nshl r13, 4\nmovups xmmword ptr [rdx+r13], xmm0\ncmp r12, r14\njz short loc_17BC\nmovsxd r13, eax\njmp short loc_1750\nloc_17B0:\nadd r12, 10h\ncmp r12, r14\njnz short loc_1758\nmov eax, r13d\nloc_17BC:\nmov rcx, [rsp+58h+var_40]\nmov [rcx], eax\nmov rax, [rsp+58h+var_50]\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_17D7:\nxor eax, eax\njmp short loc_17BC", + "ida_pseudo": "__m128i *__fastcall func0(__int64 a1, int a2, const char **a3, int a4, _DWORD *a5)\n{\n __int64 v7; // r12\n __int64 v8; // r14\n const char **v9; // rbp\n __int64 v10; // r13\n const char *v11; // rbx\n const char **v12; // r15\n __m128i v13; // xmm0\n int v14; // eax\n __m128i *v17; // [rsp+8h] [rbp-50h]\n\n v7 = a1;\n v17 = (__m128i *)malloc(16LL * a2);\n if ( a2 <= 0 )\n {\n v14 = 0;\n }\n else\n {\n v8 = a1 + 16LL * a2;\n v9 = &a3[2 * a4];\n v10 = 0LL;\n while ( a4 <= 0 )\n {\nLABEL_8:\n v13 = _mm_loadu_si128((const __m128i *)v7);\n v14 = v10 + 1;\n v7 += 16LL;\n v17[v10] = v13;\n if ( v7 == v8 )\n goto LABEL_12;\n v10 = v14;\n }\n do\n {\n v11 = *(const char **)v7;\n v12 = a3;\n while ( strcmp(v11, *v12) || strcmp(*(const char **)(v7 + 8), v12[1]) )\n {\n v12 += 2;\n if ( v12 == v9 )\n goto LABEL_8;\n }\n v7 += 16LL;\n }\n while ( v7 != v8 );\n v14 = v10;\n }\nLABEL_12:\n *a5 = v14;\n return v17;\n}", + "ida_strip_asm": "sub_16F0:\nendbr64\npush r15\nmov r15d, ecx\npush r14\nmovsxd r14, esi\npush r13\nmov r13, rdx\npush r12\nmov r12, rdi\npush rbp\npush rbx\nmov rbx, r14\nshl r14, 4\nmov rdi, r14; size\nsub rsp, 28h\nmov [rsp+58h+var_58], rdx\nmov [rsp+58h+var_44], ecx\nmov [rsp+58h+var_40], r8\ncall _malloc\nmov [rsp+58h+var_50], rax\ntest ebx, ebx\njle loc_17D7\nmovsxd rbp, r15d\nadd r14, r12\nshl rbp, 4\nadd rbp, r13\nxor r13d, r13d\nnop word ptr [rax+rax+00000000h]\nloc_1750:\nmov eax, [rsp+58h+var_44]\ntest eax, eax\njle short loc_178A\nloc_1758:\nmov rbx, [r12]\nmov r15, [rsp+58h+var_58]\nloc_1760:\nmov rsi, [r15]; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1781\nmov rsi, [r15+8]; s2\nmov rdi, [r12+8]; s1\ncall _strcmp\ntest eax, eax\njz short loc_17B0\nloc_1781:\nadd r15, 10h\ncmp r15, rbp\njnz short loc_1760\nloc_178A:\nmovdqu xmm0, xmmword ptr [r12]\nmov rdx, [rsp+58h+var_50]\nlea eax, [r13+1]\nadd r12, 10h\nshl r13, 4\nmovups xmmword ptr [rdx+r13], xmm0\ncmp r12, r14\njz short loc_17BC\nmovsxd r13, eax\njmp short loc_1750\nloc_17B0:\nadd r12, 10h\ncmp r12, r14\njnz short loc_1758\nmov eax, r13d\nloc_17BC:\nmov rcx, [rsp+58h+var_40]\nmov [rcx], eax\nmov rax, [rsp+58h+var_50]\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_17D7:\nxor eax, eax\njmp short loc_17BC", + "ida_strip_pseudo": "__m128i *__fastcall sub_16F0(__int64 a1, int a2, const char **a3, int a4, _DWORD *a5)\n{\n __int64 v7; // r12\n __int64 v8; // r14\n const char **v9; // rbp\n __int64 v10; // r13\n const char *v11; // rbx\n const char **v12; // r15\n __m128i v13; // xmm0\n int v14; // eax\n __m128i *v17; // [rsp+8h] [rbp-50h]\n\n v7 = a1;\n v17 = (__m128i *)malloc(16LL * a2);\n if ( a2 <= 0 )\n {\n v14 = 0;\n }\n else\n {\n v8 = a1 + 16LL * a2;\n v9 = &a3[2 * a4];\n v10 = 0LL;\n while ( a4 <= 0 )\n {\nLABEL_8:\n v13 = _mm_loadu_si128((const __m128i *)v7);\n v14 = v10 + 1;\n v7 += 16LL;\n v17[v10] = v13;\n if ( v7 == v8 )\n goto LABEL_12;\n v10 = v14;\n }\n do\n {\n v11 = *(const char **)v7;\n v12 = a3;\n while ( strcmp(v11, *v12) || strcmp(*(const char **)(v7 + 8), v12[1]) )\n {\n v12 += 2;\n if ( v12 == v9 )\n goto LABEL_8;\n }\n v7 += 16LL;\n }\n while ( v7 != v8 );\n v14 = v10;\n }\nLABEL_12:\n *a5 = v14;\n return v17;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__m128i *sub_16F0(long long a1, int a2, const char **a3, int a4, uint32_t *a5) {\n long long v7;\n long long v8;\n const char **v9;\n long long v10;\n const char *v11;\n const char **v12;\n __m128i v13;\n int v14;\n __m128i *v17;\n v7 = a1;\n v17 = (__m128i *)malloc(16LL * a2);\n if (a2 <= 0) {\n v14 = 0;\n } else {\n v8 = a1 + 16LL * a2;\n v9 = &a3[2 * a4];\n v10 = 0LL;\n while (a4 <= 0) {\n LABEL_8:\n v13 = _mm_loadu_si128((const __m128i *)v7);\n v14 = v10 + 1;\n v7 += 16LL;\n v17[v10] = v13;\n if (v7 == v8) goto LABEL_12;\n v10 = v14;\n }\n do {\n v11 = *(const char **)v7;\n v12 = a3;\n while (strcmp(v11, *v12) || strcmp(*(const char **)(v7 + 8), v12[1])) {\n v12 += 2;\n if (v12 == v9) goto LABEL_8;\n }\n v7 += 16LL;\n } while (v7 != v8);\n v14 = v10;\n }\nLABEL_12:\n *a5 = v14;\n return v17;\n}", + "ida_pseudo_norm": "__m128i *func0(long long a1, int a2, const char **a3, int a4, uint32_t *a5) {\n long long v7;\n long long v8;\n const char **v9;\n long long v10;\n const char *v11;\n const char **v12;\n __m128i v13;\n int v14;\n __m128i *v17;\n v7 = a1;\n v17 = (__m128i *)malloc(16LL * a2);\n if (a2 <= 0) {\n v14 = 0;\n } else {\n v8 = a1 + 16LL * a2;\n v9 = &a3[2 * a4];\n v10 = 0LL;\n while (a4 <= 0) {\n LABEL_8:\n v13 = _mm_loadu_si128((const __m128i *)v7);\n v14 = v10 + 1;\n v7 += 16LL;\n v17[v10] = v13;\n if (v7 == v8) goto LABEL_12;\n v10 = v14;\n }\n do {\n v11 = *(const char **)v7;\n v12 = a3;\n while (strcmp(v11, *v12) || strcmp(*(const char **)(v7 + 8), v12[1])) {\n v12 += 2;\n if (v12 == v9) goto LABEL_8;\n }\n v7 += 16LL;\n } while (v7 != v8);\n v14 = v10;\n }\nLABEL_12:\n *a5 = v14;\n return v17;\n}" + }, + { + "index": 484, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char* first;\n\n char* second;\n\n} Tuple;\n\n\n\n", + "func": "Tuple* func0(Tuple* test_list1, int size1, Tuple* test_list2, int size2,\n int* res_size) {\n Tuple* res = malloc(size1 * sizeof(Tuple));\n int count = 0;\n for (int i = 0; i < size1; i++) {\n int found = 0;\n for (int j = 0; j < size2; j++) {\n if (strcmp(test_list1[i].first, test_list2[j].first) == 0 &&\n strcmp(test_list1[i].second, test_list2[j].second) == 0) {\n found = 1;\n break;\n }\n }\n if (!found) {\n res[count++] = test_list1[i];\n }\n }\n *res_size = count;\n return res;\n}", + "test": "int main(){\n\n // Test case 1\n\n Tuple test1_1[] = { {\"Hello\", \"dude\"}, {\"How\", \"are\"}, {\"you\", \"?\"} };\n\n Tuple test2_1[] = { {\"Hello\", \"dude\"}, {\"How\", \"are\"} };\n\n int res_size1;\n\n Tuple* res1 = func0(test1_1, 3, test2_1, 2, &res_size1);\n\n Tuple expected1[] = { {\"you\", \"?\"} };\n\n assert(res_size1 == 1);\n\n assert(strcmp(res1[0].first, expected1[0].first) == 0);\n\n assert(strcmp(res1[0].second, expected1[0].second) == 0);\n\n free(res1);\n\n \n\n // Test case 2\n\n Tuple test1_2[] = { {\"Part\", \"of\"}, {\"the\", \"journey\"}, {\"is \", \"end\"} };\n\n Tuple test2_2[] = { {\"Journey\", \"the\"}, {\"is\", \"end\"} };\n\n int res_size2;\n\n Tuple* res2 = func0(test1_2, 3, test2_2, 2, &res_size2);\n\n Tuple expected2[] = { {\"Part\", \"of\"}, {\"the\", \"journey\"}, {\"is \", \"end\"} };\n\n assert(res_size2 == 3);\n\n for(int i = 0; i < res_size2; i++) {\n\n assert(strcmp(res2[i].first, expected2[i].first) == 0);\n\n assert(strcmp(res2[i].second, expected2[i].second) == 0);\n\n }\n\n free(res2);\n\n \n\n // Test case 3\n\n Tuple test1_3[] = { {\"Its\", \"been\"}, {\"a\", \"long\"}, {\"day\", \"without\"} };\n\n Tuple test2_3[] = { {\"a\", \"long\"}, {\"my\", \"friend\"} };\n\n int res_size3;\n\n Tuple* res3 = func0(test1_3, 3, test2_3, 2, &res_size3);\n\n Tuple expected3[] = { {\"Its\", \"been\"}, {\"day\", \"without\"} };\n\n assert(res_size3 == 2);\n\n for(int i = 0; i < res_size3; i++) {\n\n assert(strcmp(res3[i].first, expected3[i].first) == 0);\n\n assert(strcmp(res3[i].second, expected3[i].second) == 0);\n\n }\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmov %rdx,%r15\npush %r14\nmov %ecx,%r14d\npush %r13\npush %r12\nmov %rdi,%r12\nmovslq %esi,%rdi\npush %rbp\npush %rbx\nmov %rdi,%rbx\nshl $0x4,%rdi\nsub $0x28,%rsp\nmov %rdx,0x8(%rsp)\nmov %r8,0x18(%rsp)\ncallq 10d0 \nmov %rax,0x10(%rsp)\ntest %ebx,%ebx\njle 180a \nlea -0x1(%rbx),%eax\nxor %r13d,%r13d\nshl $0x4,%rax\nlea 0x10(%r12,%rax,1),%rax\nmov %rax,(%rsp)\nlea -0x1(%r14),%eax\nshl $0x4,%rax\nlea 0x10(%r15,%rax,1),%rbp\nnopl 0x0(%rax)\ntest %r14d,%r14d\njle 17ca \nmov (%r12),%rbx\nmov 0x8(%rsp),%r15\nnopw %cs:0x0(%rax,%rax,1)\nmov (%r15),%rsi\nmov %rbx,%rdi\ncallq 10c0 \ntest %eax,%eax\njne 17c1 \nmov 0x8(%r15),%rsi\nmov 0x8(%r12),%rdi\ncallq 10c0 \ntest %eax,%eax\nje 17e4 \nadd $0x10,%r15\ncmp %r15,%rbp\njne 17a0 \nmovslq %r13d,%rax\nmov 0x10(%rsp),%rdx\nmovdqu (%r12),%xmm0\nadd $0x1,%r13d\nshl $0x4,%rax\nmovups %xmm0,(%rdx,%rax,1)\nadd $0x10,%r12\ncmp %r12,(%rsp)\njne 1788 \nmov 0x18(%rsp),%rax\nmov %r13d,(%rax)\nmov 0x10(%rsp),%rax\nadd $0x28,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nxor %r13d,%r13d\njmp 17ee \n", + "ida_asm": "func0:\nendbr64\npush r15\nmov r15, rdx\npush r14\nmovsxd r14, esi\npush r13\npush r12\nmov r12, rdi\npush rbp\nmovsxd rbp, ecx\npush rbx\nmov rbx, r14\nshl r14, 4\nmov rdi, r14; size\nsub rsp, 28h\nmov [rsp+58h+var_44], ebp\nmov [rsp+58h+var_40], r8\ncall _malloc\nmov [rsp+58h+var_50], rax\ntest ebx, ebx\njle loc_17D0\nlea rax, [r12+r14]\nshl rbp, 4\nxor r13d, r13d\nmov [rsp+58h+var_58], rax\nadd rbp, r15\nnop dword ptr [rax]\nloc_1738:\nmov eax, [rsp+58h+var_44]\ntest eax, eax\njle short loc_177A\nloc_1740:\nmov rbx, [r12]\nmov r14, r15\nnop word ptr [rax+rax+00000000h]\nloc_1750:\nmov rsi, [r14]; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1771\nmov rsi, [r14+8]; s2\nmov rdi, [r12+8]; s1\ncall _strcmp\ntest eax, eax\njz short loc_17A8\nloc_1771:\nadd r14, 10h\ncmp rbp, r14\njnz short loc_1750\nloc_177A:\nmovdqu xmm0, xmmword ptr [r12]\nmov rdx, [rsp+58h+var_50]\nlea eax, [r13+1]\nshl r13, 4\nadd r12, 10h\nmovups xmmword ptr [rdx+r13], xmm0\ncmp [rsp+58h+var_58], r12\njz short loc_17B5\nmovsxd r13, eax\njmp short loc_1738\nloc_17A8:\nadd r12, 10h\ncmp [rsp+58h+var_58], r12\njnz short loc_1740\nmov eax, r13d\nloc_17B5:\nmov rdx, [rsp+58h+var_40]\nmov [rdx], eax\nmov rax, [rsp+58h+var_50]\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_17D0:\nxor eax, eax\njmp short loc_17B5", + "ida_pseudo": "__m128i *__fastcall func0(__int64 a1, int a2, const char **a3, int a4, _DWORD *a5)\n{\n __int64 v6; // r12\n __int64 v7; // rbp\n __int64 v8; // r13\n const char **v9; // rbp\n const char *v10; // rbx\n const char **v11; // r14\n __m128i v12; // xmm0\n int v13; // eax\n __int64 v15; // [rsp+0h] [rbp-58h]\n __m128i *v16; // [rsp+8h] [rbp-50h]\n\n v6 = a1;\n v7 = a4;\n v16 = (__m128i *)malloc(16LL * a2);\n if ( a2 <= 0 )\n {\n v13 = 0;\n }\n else\n {\n v8 = 0LL;\n v15 = a1 + 16LL * a2;\n v9 = &a3[2 * v7];\n while ( a4 <= 0 )\n {\nLABEL_8:\n v12 = _mm_loadu_si128((const __m128i *)v6);\n v13 = v8 + 1;\n v6 += 16LL;\n v16[v8] = v12;\n if ( v15 == v6 )\n goto LABEL_12;\n v8 = v13;\n }\n do\n {\n v10 = *(const char **)v6;\n v11 = a3;\n while ( strcmp(v10, *v11) || strcmp(*(const char **)(v6 + 8), v11[1]) )\n {\n v11 += 2;\n if ( v9 == v11 )\n goto LABEL_8;\n }\n v6 += 16LL;\n }\n while ( v15 != v6 );\n v13 = v8;\n }\nLABEL_12:\n *a5 = v13;\n return v16;\n}", + "ida_strip_asm": "sub_16E0:\nendbr64\npush r15\nmov r15, rdx\npush r14\nmovsxd r14, esi\npush r13\npush r12\nmov r12, rdi\npush rbp\nmovsxd rbp, ecx\npush rbx\nmov rbx, r14\nshl r14, 4\nmov rdi, r14; size\nsub rsp, 28h\nmov [rsp+58h+var_44], ebp\nmov [rsp+58h+var_40], r8\ncall _malloc\nmov [rsp+58h+var_50], rax\ntest ebx, ebx\njle loc_17D0\nlea rax, [r12+r14]\nshl rbp, 4\nxor r13d, r13d\nmov [rsp+58h+var_58], rax\nadd rbp, r15\nnop dword ptr [rax]\nloc_1738:\nmov eax, [rsp+58h+var_44]\ntest eax, eax\njle short loc_177A\nloc_1740:\nmov rbx, [r12]\nmov r14, r15\nnop word ptr [rax+rax+00000000h]\nloc_1750:\nmov rsi, [r14]; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1771\nmov rsi, [r14+8]; s2\nmov rdi, [r12+8]; s1\ncall _strcmp\ntest eax, eax\njz short loc_17A8\nloc_1771:\nadd r14, 10h\ncmp rbp, r14\njnz short loc_1750\nloc_177A:\nmovdqu xmm0, xmmword ptr [r12]\nmov rdx, [rsp+58h+var_50]\nlea eax, [r13+1]\nshl r13, 4\nadd r12, 10h\nmovups xmmword ptr [rdx+r13], xmm0\ncmp [rsp+58h+var_58], r12\njz short loc_17B5\nmovsxd r13, eax\njmp short loc_1738\nloc_17A8:\nadd r12, 10h\ncmp [rsp+58h+var_58], r12\njnz short loc_1740\nmov eax, r13d\nloc_17B5:\nmov rdx, [rsp+58h+var_40]\nmov [rdx], eax\nmov rax, [rsp+58h+var_50]\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_17D0:\nxor eax, eax\njmp short loc_17B5", + "ida_strip_pseudo": "__m128i *__fastcall sub_16E0(__int64 a1, int a2, const char **a3, int a4, _DWORD *a5)\n{\n __int64 v6; // r12\n __int64 v7; // rbp\n __int64 v8; // r13\n const char **v9; // rbp\n const char *v10; // rbx\n const char **v11; // r14\n __m128i v12; // xmm0\n int v13; // eax\n __int64 v15; // [rsp+0h] [rbp-58h]\n __m128i *v16; // [rsp+8h] [rbp-50h]\n\n v6 = a1;\n v7 = a4;\n v16 = (__m128i *)malloc(16LL * a2);\n if ( a2 <= 0 )\n {\n v13 = 0;\n }\n else\n {\n v8 = 0LL;\n v15 = a1 + 16LL * a2;\n v9 = &a3[2 * v7];\n while ( a4 <= 0 )\n {\nLABEL_8:\n v12 = _mm_loadu_si128((const __m128i *)v6);\n v13 = v8 + 1;\n v6 += 16LL;\n v16[v8] = v12;\n if ( v15 == v6 )\n goto LABEL_12;\n v8 = v13;\n }\n do\n {\n v10 = *(const char **)v6;\n v11 = a3;\n while ( strcmp(v10, *v11) || strcmp(*(const char **)(v6 + 8), v11[1]) )\n {\n v11 += 2;\n if ( v9 == v11 )\n goto LABEL_8;\n }\n v6 += 16LL;\n }\n while ( v15 != v6 );\n v13 = v8;\n }\nLABEL_12:\n *a5 = v13;\n return v16;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__m128i *sub_16E0(long long a1, int a2, const char **a3, int a4, uint32_t *a5) {\n long long v6;\n long long v7;\n long long v8;\n const char **v9;\n const char *v10;\n const char **v11;\n __m128i v12;\n int v13;\n long long v15;\n __m128i *v16;\n v6 = a1;\n v7 = a4;\n v16 = (__m128i *)malloc(16LL * a2);\n if (a2 <= 0) {\n v13 = 0;\n } else {\n v8 = 0LL;\n v15 = a1 + 16LL * a2;\n v9 = &a3[2 * v7];\n while (a4 <= 0) {\n LABEL_8:\n v12 = _mm_loadu_si128((const __m128i *)v6);\n v13 = v8 + 1;\n v6 += 16LL;\n v16[v8] = v12;\n if (v15 == v6) goto LABEL_12;\n v8 = v13;\n }\n do {\n v10 = *(const char **)v6;\n v11 = a3;\n while (strcmp(v10, *v11) || strcmp(*(const char **)(v6 + 8), v11[1])) {\n v11 += 2;\n if (v9 == v11) goto LABEL_8;\n }\n v6 += 16LL;\n } while (v15 != v6);\n v13 = v8;\n }\nLABEL_12:\n *a5 = v13;\n return v16;\n}", + "ida_pseudo_norm": "__m128i *func0(long long a1, int a2, const char **a3, int a4, uint32_t *a5) {\n long long v6;\n long long v7;\n long long v8;\n const char **v9;\n const char *v10;\n const char **v11;\n __m128i v12;\n int v13;\n long long v15;\n __m128i *v16;\n v6 = a1;\n v7 = a4;\n v16 = (__m128i *)malloc(16LL * a2);\n if (a2 <= 0) {\n v13 = 0;\n } else {\n v8 = 0LL;\n v15 = a1 + 16LL * a2;\n v9 = &a3[2 * v7];\n while (a4 <= 0) {\n LABEL_8:\n v12 = _mm_loadu_si128((const __m128i *)v6);\n v13 = v8 + 1;\n v6 += 16LL;\n v16[v8] = v12;\n if (v15 == v6) goto LABEL_12;\n v8 = v13;\n }\n do {\n v10 = *(const char **)v6;\n v11 = a3;\n while (strcmp(v10, *v11) || strcmp(*(const char **)(v6 + 8), v11[1])) {\n v11 += 2;\n if (v9 == v11) goto LABEL_8;\n }\n v6 += 16LL;\n } while (v15 != v6);\n v13 = v8;\n }\nLABEL_12:\n *a5 = v13;\n return v16;\n}" + }, + { + "index": 485, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nbool is_palindrome(int n) {\n\n int divisor = 1;\n\n while (n / divisor >= 10) {\n\n divisor *= 10;\n\n }\n\n while (n != 0) {\n\n int leading = n / divisor;\n\n int trailing = n % 10;\n\n if (leading != trailing) {\n\n return false;\n\n }\n\n n = (n % divisor) / 10;\n\n divisor = divisor / 100;\n\n }\n\n return true;\n\n}\n\n\n\n", + "func": "int func0(int A[], int n) {\n int i, j, temp;\n for (i = 0; i < n; i++) {\n for (j = i + 1; j < n; j++) {\n if (A[i] > A[j]) {\n temp = A[j];\n A[j] = A[i];\n A[i] = temp;\n }\n }\n }\n for (i = n - 1; i >= 0; i--) {\n if (is_palindrome(A[i])) {\n return A[i];\n }\n }\n return -1;\n}", + "test": "int main() {\n\n int arr1[4] = {1, 232, 54545, 999991};\n\n int arr2[6] = {1, 2, 3, 4, 5, 50};\n\n int arr3[5] = {1, 3, 7, 9, 45};\n\n\n\n assert(func0(arr1, 4) == 54545);\n\n assert(func0(arr2, 6) == 5);\n\n assert(func0(arr3, 5) == 9);\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0xc(%rbp)\njmpq 1326 \nmov -0xc(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x8(%rbp)\njmpq 1316 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njle 1312 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x4(%rbp)\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0x8(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0x4(%rbp),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1283 \naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1275 \nmov -0x1c(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0xc(%rbp)\njmp 137a \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,%edi\ncallq 1189 \ntest %al,%al\nje 1376 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\njmp 1385 \nsubl $0x1,-0xc(%rbp)\ncmpl $0x0,-0xc(%rbp)\njns 133d \nmov $0xffffffff,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0\njmp loc_1324\nloc_1273:\nmov eax, [rbp+var_C]\nadd eax, 1\nmov [rbp+var_8], eax\njmp loc_1314\nloc_1281:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_1310\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nloc_1310:\nadd [rbp+var_8], 1\nloc_1314:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl loc_1281\nadd [rbp+var_C], 1\nloc_1324:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl loc_1273\nmov eax, [rbp+var_1C]\nsub eax, 1\nmov [rbp+var_C], eax\njmp short loc_1378\nloc_133B:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov edi, eax\ncall is_palindrome\ntest al, al\njz short loc_1374\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\njmp short locret_1383\nloc_1374:\nsub [rbp+var_C], 1\nloc_1378:\ncmp [rbp+var_C], 0\njns short loc_133B\nmov eax, 0FFFFFFFFh\nlocret_1383:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+14h] [rbp-Ch]\n int k; // [rsp+14h] [rbp-Ch]\n int j; // [rsp+18h] [rbp-8h]\n int v6; // [rsp+1Ch] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a1) > *(_DWORD *)(4LL * j + a1) )\n {\n v6 = *(_DWORD *)(4LL * j + a1);\n *(_DWORD *)(4LL * j + a1) = *(_DWORD *)(4LL * i + a1);\n *(_DWORD *)(a1 + 4LL * i) = v6;\n }\n }\n }\n for ( k = a2 - 1; k >= 0; --k )\n {\n if ( (unsigned __int8)is_palindrome(*(unsigned int *)(4LL * k + a1)) )\n return *(unsigned int *)(4LL * k + a1);\n }\n return 0xFFFFFFFFLL;\n}", + "ida_strip_asm": "sub_1254:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0\njmp loc_1324\nloc_1273:\nmov eax, [rbp+var_C]\nadd eax, 1\nmov [rbp+var_8], eax\njmp loc_1314\nloc_1281:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_1310\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nloc_1310:\nadd [rbp+var_8], 1\nloc_1314:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl loc_1281\nadd [rbp+var_C], 1\nloc_1324:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl loc_1273\nmov eax, [rbp+var_1C]\nsub eax, 1\nmov [rbp+var_C], eax\njmp short loc_1378\nloc_133B:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov edi, eax\ncall sub_1189\ntest al, al\njz short loc_1374\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\njmp short locret_1383\nloc_1374:\nsub [rbp+var_C], 1\nloc_1378:\ncmp [rbp+var_C], 0\njns short loc_133B\nmov eax, 0FFFFFFFFh\nlocret_1383:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1254(__int64 a1, int a2)\n{\n int i; // [rsp+14h] [rbp-Ch]\n int k; // [rsp+14h] [rbp-Ch]\n int j; // [rsp+18h] [rbp-8h]\n int v6; // [rsp+1Ch] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a1) > *(_DWORD *)(4LL * j + a1) )\n {\n v6 = *(_DWORD *)(4LL * j + a1);\n *(_DWORD *)(4LL * j + a1) = *(_DWORD *)(4LL * i + a1);\n *(_DWORD *)(a1 + 4LL * i) = v6;\n }\n }\n }\n for ( k = a2 - 1; k >= 0; --k )\n {\n if ( (unsigned __int8)sub_1189(*(unsigned int *)(4LL * k + a1)) )\n return *(unsigned int *)(4LL * k + a1);\n }\n return 0xFFFFFFFFLL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1254(long long a1, int a2) {\n int i;\n int k;\n int j;\n int v6;\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if (*(uint32_t *)(4LL * i + a1) > *(uint32_t *)(4LL * j + a1)) {\n v6 = *(uint32_t *)(4LL * j + a1);\n *(uint32_t *)(4LL * j + a1) = *(uint32_t *)(4LL * i + a1);\n *(uint32_t *)(a1 + 4LL * i) = v6;\n }\n }\n }\n for (k = a2 - 1; k >= 0; --k) {\n if ((unsigned char)sub_1189(*(unsigned int *)(4LL * k + a1)))\n return *(unsigned int *)(4LL * k + a1);\n }\n return 4294967295LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int i;\n int k;\n int j;\n int v6;\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if (*(uint32_t *)(4LL * i + a1) > *(uint32_t *)(4LL * j + a1)) {\n v6 = *(uint32_t *)(4LL * j + a1);\n *(uint32_t *)(4LL * j + a1) = *(uint32_t *)(4LL * i + a1);\n *(uint32_t *)(a1 + 4LL * i) = v6;\n }\n }\n }\n for (k = a2 - 1; k >= 0; --k) {\n if ((unsigned char)is_palindrome(*(unsigned int *)(4LL * k + a1)))\n return *(unsigned int *)(4LL * k + a1);\n }\n return 4294967295LL;\n}" + }, + { + "index": 485, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nbool is_palindrome(int n) {\n\n int divisor = 1;\n\n while (n / divisor >= 10) {\n\n divisor *= 10;\n\n }\n\n while (n != 0) {\n\n int leading = n / divisor;\n\n int trailing = n % 10;\n\n if (leading != trailing) {\n\n return false;\n\n }\n\n n = (n % divisor) / 10;\n\n divisor = divisor / 100;\n\n }\n\n return true;\n\n}\n\n\n\n", + "func": "int func0(int A[], int n) {\n int i, j, temp;\n for (i = 0; i < n; i++) {\n for (j = i + 1; j < n; j++) {\n if (A[i] > A[j]) {\n temp = A[j];\n A[j] = A[i];\n A[i] = temp;\n }\n }\n }\n for (i = n - 1; i >= 0; i--) {\n if (is_palindrome(A[i])) {\n return A[i];\n }\n }\n return -1;\n}", + "test": "int main() {\n\n int arr1[4] = {1, 232, 54545, 999991};\n\n int arr2[6] = {1, 2, 3, 4, 5, 50};\n\n int arr3[5] = {1, 3, 7, 9, 45};\n\n\n\n assert(func0(arr1, 4) == 54545);\n\n assert(func0(arr2, 6) == 5);\n\n assert(func0(arr3, 5) == 9);\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\ntest %esi,%esi\njle 1295 \nmov %rdi,%rbx\nlea -0x1(%rsi),%r9d\nadd $0x1,%r9\nmov $0x1,%r8d\njmp 128b \nadd $0x1,%rax\ncmp %eax,%esi\njle 1283 \nmov (%rdi),%ecx\nmov (%rbx,%rax,4),%edx\ncmp %edx,%ecx\njle 126b \nmov %ecx,(%rbx,%rax,4)\nmov %edx,(%rdi)\njmp 126b \nadd $0x1,%r8\nadd $0x4,%rdi\ncmp %r9,%r8\nje 129d \nmov %r8,%rax\njmp 1273 \nmov $0xffffffff,%r12d\njmp 12c1 \nsub $0x1,%esi\nmovslq %esi,%rbp\nmov (%rbx,%rbp,4),%r12d\nmov %r12d,%edi\ncallq 1189 \ntest %al,%al\njne 12c1 \nsub $0x1,%rbp\ntest %ebp,%ebp\njns 12a3 \nmov $0xffffffff,%r12d\nmov %r12d,%eax\npop %rbx\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\ntest esi, esi\njle loc_12EB\nmov rbx, rdi\nlea rdi, [rdi+4]\nlea r12d, [rsi-1]\nmov r10d, esi\nmovsxd rbp, esi\nmov r9d, 1\nlea r11, [rbx+8]\njmp short loc_12A6\nloc_127D:\nadd rax, 4\ncmp rax, r8\njz short loc_1296\nloc_1286:\nmov ecx, [rdi-4]\nmov edx, [rax]\ncmp ecx, edx\njle short loc_127D\nmov [rax], ecx\nmov [rdi-4], edx\njmp short loc_127D\nloc_1296:\nlea rax, [r9+1]\nadd rdi, 4\ncmp r9, rbp\njz short loc_12BF\nmov r9, rax\nloc_12A6:\ncmp r9, r10\njz short loc_12BF\nmov eax, r12d\nsub eax, r9d\nlea rax, [r9+rax-1]\nlea r8, [r11+rax*4]\nmov rax, rdi\njmp short loc_1286\nloc_12BF:\nsub esi, 1\nmovsxd rbp, esi\nloc_12C5:\nmov r12d, [rbx+rbp*4]\nmov edi, r12d\ncall is_palindrome\ntest al, al\njnz short loc_12E3\nsub rbp, 1\ntest ebp, ebp\njns short loc_12C5\nmov r12d, 0FFFFFFFFh\nloc_12E3:\nmov eax, r12d\npop rbx\npop rbp\npop r12\nretn\nloc_12EB:\nmov r12d, 0FFFFFFFFh\njmp short loc_12E3", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int *v3; // rdi\n __int64 i; // r9\n int *v5; // rax\n int v6; // ecx\n int v7; // edx\n __int64 v8; // rbp\n unsigned int v9; // r12d\n\n if ( a2 <= 0 )\n {\n return (unsigned int)-1;\n }\n else\n {\n v3 = (int *)(a1 + 4);\n for ( i = 1LL; i != a2; ++i )\n {\n v5 = v3;\n do\n {\n v6 = *(v3 - 1);\n v7 = *v5;\n if ( v6 > *v5 )\n {\n *v5 = v6;\n *(v3 - 1) = v7;\n }\n ++v5;\n }\n while ( v5 != (int *)(a1 + 8 + 4 * (i + (unsigned int)(a2 - 1 - i) - 1)) );\n ++v3;\n if ( i == a2 )\n break;\n }\n v8 = a2 - 1;\n while ( 1 )\n {\n v9 = *(_DWORD *)(a1 + 4 * v8);\n if ( (unsigned __int8)is_palindrome(v9) )\n break;\n if ( (int)--v8 < 0 )\n return (unsigned int)-1;\n }\n }\n return v9;\n}", + "ida_strip_asm": "sub_1250:\nendbr64\npush r12\npush rbp\npush rbx\ntest esi, esi\njle loc_12EB\nmov rbx, rdi\nlea rdi, [rdi+4]\nlea r12d, [rsi-1]\nmov r10d, esi\nmovsxd rbp, esi\nmov r9d, 1\nlea r11, [rbx+8]\njmp short loc_12A6\nloc_127D:\nadd rax, 4\ncmp rax, r8\njz short loc_1296\nloc_1286:\nmov ecx, [rdi-4]\nmov edx, [rax]\ncmp ecx, edx\njle short loc_127D\nmov [rax], ecx\nmov [rdi-4], edx\njmp short loc_127D\nloc_1296:\nlea rax, [r9+1]\nadd rdi, 4\ncmp r9, rbp\njz short loc_12BF\nmov r9, rax\nloc_12A6:\ncmp r9, r10\njz short loc_12BF\nmov eax, r12d\nsub eax, r9d\nlea rax, [r9+rax-1]\nlea r8, [r11+rax*4]\nmov rax, rdi\njmp short loc_1286\nloc_12BF:\nsub esi, 1\nmovsxd rbp, esi\nloc_12C5:\nmov r12d, [rbx+rbp*4]\nmov edi, r12d\ncall sub_1189\ntest al, al\njnz short loc_12E3\nsub rbp, 1\ntest ebp, ebp\njns short loc_12C5\nmov r12d, 0FFFFFFFFh\nloc_12E3:\nmov eax, r12d\npop rbx\npop rbp\npop r12\nretn\nloc_12EB:\nmov r12d, 0FFFFFFFFh\njmp short loc_12E3", + "ida_strip_pseudo": "__int64 __fastcall sub_1250(__int64 a1, int a2)\n{\n int *v3; // rdi\n __int64 i; // r9\n int *v5; // rax\n int v6; // ecx\n int v7; // edx\n __int64 v8; // rbp\n unsigned int v9; // r12d\n\n if ( a2 <= 0 )\n {\n return (unsigned int)-1;\n }\n else\n {\n v3 = (int *)(a1 + 4);\n for ( i = 1LL; i != a2; ++i )\n {\n v5 = v3;\n do\n {\n v6 = *(v3 - 1);\n v7 = *v5;\n if ( v6 > *v5 )\n {\n *v5 = v6;\n *(v3 - 1) = v7;\n }\n ++v5;\n }\n while ( v5 != (int *)(a1 + 8 + 4 * (i + (unsigned int)(a2 - 1 - i) - 1)) );\n ++v3;\n if ( i == a2 )\n break;\n }\n v8 = a2 - 1;\n while ( 1 )\n {\n v9 = *(_DWORD *)(a1 + 4 * v8);\n if ( (unsigned __int8)sub_1189(v9) )\n break;\n if ( (int)--v8 < 0 )\n return (unsigned int)-1;\n }\n }\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1250(long long a1, int a2) {\n int *v3;\n long long i;\n int *v5;\n int v6;\n int v7;\n long long v8;\n unsigned int v9;\n if (a2 <= 0) {\n return (unsigned int)-1;\n } else {\n v3 = (int *)(a1 + 4);\n for (i = 1LL; i != a2; ++i) {\n v5 = v3;\n do {\n v6 = *(v3 - 1);\n v7 = *v5;\n if (v6 > *v5) {\n *v5 = v6;\n *(v3 - 1) = v7;\n }\n ++v5;\n } while (v5 !=\n (int *)(a1 + 8 + 4 * (i + (unsigned int)(a2 - 1 - i) - 1)));\n ++v3;\n if (i == a2) break;\n }\n v8 = a2 - 1;\n while (1) {\n v9 = *(uint32_t *)(a1 + 4 * v8);\n if ((unsigned char)sub_1189(v9)) break;\n if ((int)--v8 < 0) return (unsigned int)-1;\n }\n }\n return v9;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int *v3;\n long long i;\n int *v5;\n int v6;\n int v7;\n long long v8;\n unsigned int v9;\n if (a2 <= 0) {\n return (unsigned int)-1;\n } else {\n v3 = (int *)(a1 + 4);\n for (i = 1LL; i != a2; ++i) {\n v5 = v3;\n do {\n v6 = *(v3 - 1);\n v7 = *v5;\n if (v6 > *v5) {\n *v5 = v6;\n *(v3 - 1) = v7;\n }\n ++v5;\n } while (v5 !=\n (int *)(a1 + 8 + 4 * (i + (unsigned int)(a2 - 1 - i) - 1)));\n ++v3;\n if (i == a2) break;\n }\n v8 = a2 - 1;\n while (1) {\n v9 = *(uint32_t *)(a1 + 4 * v8);\n if ((unsigned char)is_palindrome(v9)) break;\n if ((int)--v8 < 0) return (unsigned int)-1;\n }\n }\n return v9;\n}" + }, + { + "index": 485, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nbool is_palindrome(int n) {\n\n int divisor = 1;\n\n while (n / divisor >= 10) {\n\n divisor *= 10;\n\n }\n\n while (n != 0) {\n\n int leading = n / divisor;\n\n int trailing = n % 10;\n\n if (leading != trailing) {\n\n return false;\n\n }\n\n n = (n % divisor) / 10;\n\n divisor = divisor / 100;\n\n }\n\n return true;\n\n}\n\n\n\n", + "func": "int func0(int A[], int n) {\n int i, j, temp;\n for (i = 0; i < n; i++) {\n for (j = i + 1; j < n; j++) {\n if (A[i] > A[j]) {\n temp = A[j];\n A[j] = A[i];\n A[i] = temp;\n }\n }\n }\n for (i = n - 1; i >= 0; i--) {\n if (is_palindrome(A[i])) {\n return A[i];\n }\n }\n return -1;\n}", + "test": "int main() {\n\n int arr1[4] = {1, 232, 54545, 999991};\n\n int arr2[6] = {1, 2, 3, 4, 5, 50};\n\n int arr3[5] = {1, 3, 7, 9, 45};\n\n\n\n assert(func0(arr1, 4) == 54545);\n\n assert(func0(arr2, 6) == 5);\n\n assert(func0(arr3, 5) == 9);\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nlea -0x1(%rsi),%r10d\ntest %esi,%esi\njle 14ee \nmov %r10d,%r11d\nmov $0x1,%r9d\nmov %rdi,%r8\nadd $0x1,%r11\ncmp %r11,%r9\nje 1405 \nnopl (%rax)\nmov %r9,%rax\nnopl 0x0(%rax,%rax,1)\nmov (%r8),%ecx\nmov (%rdi,%rax,4),%edx\ncmp %edx,%ecx\njle 13f0 \nmov %ecx,(%rdi,%rax,4)\nmov %edx,(%r8)\nadd $0x1,%rax\ncmp %eax,%esi\njg 13e0 \nadd $0x1,%r9\nadd $0x4,%r8\ncmp %r11,%r9\njne 13d8 \nmovslq %r10d,%r10\nmov $0xcccccccd,%r9d\nxchg %ax,%ax\nmov (%rdi,%r10,4),%r8d\ncmp $0x9,%r8d\njle 14c0 \nmov $0x1,%ecx\nnopl 0x0(%rax,%rax,1)\nmov %r8d,%eax\nlea (%rcx,%rcx,4),%ecx\nadd %ecx,%ecx\ncltd\nidiv %ecx\ncmp $0x9,%eax\njg 1428 \nmovslq %r8d,%rdx\nmov %r8d,%esi\nimul $0x66666667,%rdx,%rdx\nsar $0x1f,%esi\nsar $0x22,%rdx\nsub %esi,%edx\nmov %r8d,%esi\nlea (%rdx,%rdx,4),%edx\nadd %edx,%edx\nsub %edx,%esi\ncmp %esi,%eax\njne 14a0 \nmov %r8d,%esi\nmov %esi,%eax\ncltd\nidiv %ecx\nmov %ecx,%ecx\nimul $0x51eb851f,%rcx,%rcx\nshr $0x25,%rcx\nmov %rdx,%rsi\nimul %r9,%rsi\nshr $0x23,%rsi\ntest %esi,%esi\nje 14b3 \nmov %esi,%eax\nmov %esi,%r11d\ncltd\nidiv %ecx\nmov %esi,%edx\nimul %r9,%rdx\nshr $0x23,%rdx\nlea (%rdx,%rdx,4),%edx\nadd %edx,%edx\nsub %edx,%r11d\ncmp %r11d,%eax\nje 1460 \nsub $0x1,%r10\ntest %r10d,%r10d\njns 1410 \nmov $0xffffffff,%r8d\nmov %r8d,%eax\nretq\nnopw 0x0(%rax,%rax,1)\ntest %r8d,%r8d\nje 14b3 \nmovslq %r8d,%rax\nmov %r8d,%edx\nmov %r8d,%esi\nimul $0x66666667,%rax,%rax\nsar $0x1f,%edx\nsar $0x22,%rax\nsub %edx,%eax\nlea (%rax,%rax,4),%eax\nadd %eax,%eax\nsub %eax,%esi\ncmp %r8d,%esi\njne 14a0 \nmov %r8d,%eax\nretq\ntest %r10d,%r10d\njns 1405 \njmp 14ad \nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\nmov r8, rdi\ntest esi, esi\njle loc_147D\ncmp esi, 1\njz short loc_13AD\nmov r10d, esi\nmov r9d, 1\nnop dword ptr [rax]\nloc_1380:\nmov rax, r9\nnop dword ptr [rax+rax+00h]\nloc_1388:\nmov ecx, [rdi]\nmov edx, [r8+rax*4]\ncmp ecx, edx\njle short loc_1398\nmov [r8+rax*4], ecx\nmov [rdi], edx\nloc_1398:\nadd rax, 1\ncmp esi, eax\njg short loc_1388\nadd r9, 1\nadd rdi, 4\ncmp r9, r10\njnz short loc_1380\nloc_13AD:\nsub esi, 1\nmovsxd r9, esi\nnop dword ptr [rax+rax+00h]\nloc_13B8:\nmov edi, [r8+r9*4]\ncmp edi, 9\njle loc_1488\nmov esi, 1\nnop word ptr [rax+rax+00h]\nloc_13D0:\nmov eax, edi\nlea esi, [rsi+rsi*4]\nadd esi, esi\ncdq\nidiv esi\ncmp eax, 9\njg short loc_13D0\nloc_13DF:\nmov eax, edi\nmov ecx, edi\ncdq\nsar ecx, 1Fh\nidiv esi\nmovsxd rdx, edi\nimul rdx, 66666667h\nsar rdx, 22h\nsub edx, ecx\nmov ecx, edi\nlea edx, [rdx+rdx*4]\nadd edx, edx\nsub ecx, edx\ncmp eax, ecx\njnz short loc_1470\nmov ecx, edi\njmp short loc_143D\nloc_1410:\nmov eax, ecx\nmov r10d, ecx\ncdq\nsar r10d, 1Fh\nidiv esi\nmovsxd rdx, ecx\nimul rdx, 66666667h\nsar rdx, 22h\nsub edx, r10d\nmov r10d, ecx\nlea edx, [rdx+rdx*4]\nadd edx, edx\nsub r10d, edx\ncmp eax, r10d\njnz short loc_1470\nloc_143D:\nmov eax, ecx\ncdq\nidiv esi\nmovsxd rax, esi\nsar esi, 1Fh\nimul rax, 51EB851Fh\nsar rax, 25h\nsub eax, esi\nmov esi, eax\nmovsxd rcx, edx\nsar edx, 1Fh\nimul rcx, 66666667h\nsar rcx, 22h\nsub ecx, edx\njnz short loc_1410\nloc_146C:\nmov eax, edi\nretn\nloc_1470:\nsub r9, 1\ntest r9d, r9d\njns loc_13B8\nloc_147D:\nmov edi, 0FFFFFFFFh\nmov eax, edi\nretn\nloc_1488:\ntest edi, edi\njz short loc_146C\nmov esi, 1\njmp loc_13DF", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // r8\n __int64 i; // r9\n __int64 v4; // rax\n int v5; // edx\n __int64 v6; // r9\n int v7; // edi\n int v8; // esi\n int v9; // ecx\n int v10; // edx\n\n v2 = a1;\n if ( a2 <= 0 )\n return 0xFFFFFFFFLL;\n if ( a2 != 1 )\n {\n for ( i = 1LL; i != a2; ++i )\n {\n v4 = i;\n do\n {\n v5 = v2[v4];\n if ( *a1 > v5 )\n {\n v2[v4] = *a1;\n *a1 = v5;\n }\n ++v4;\n }\n while ( a2 > (int)v4 );\n ++a1;\n }\n }\n v6 = a2 - 1;\n while ( 1 )\n {\n v7 = v2[v6];\n if ( v7 <= 9 )\n {\n if ( !v7 )\n return (unsigned int)v7;\n v8 = 1;\n }\n else\n {\n v8 = 1;\n do\n v8 *= 10;\n while ( v7 / v8 > 9 );\n }\n if ( v7 / v8 == v7 % 10 )\n break;\nLABEL_18:\n if ( (int)--v6 < 0 )\n return 0xFFFFFFFFLL;\n }\n v9 = v2[v6];\n while ( 1 )\n {\n v10 = v9 % v8;\n v8 /= 100;\n v9 = v10 / 10;\n if ( !(v10 / 10) )\n return (unsigned int)v7;\n if ( v9 / v8 != v9 % 10 )\n goto LABEL_18;\n }\n}", + "ida_strip_asm": "sub_1360:\nendbr64\nmov r8, rdi\ntest esi, esi\njle loc_147D\ncmp esi, 1\njz short loc_13AD\nmov r10d, esi\nmov r9d, 1\nnop dword ptr [rax]\nloc_1380:\nmov rax, r9\nnop dword ptr [rax+rax+00h]\nloc_1388:\nmov ecx, [rdi]\nmov edx, [r8+rax*4]\ncmp ecx, edx\njle short loc_1398\nmov [r8+rax*4], ecx\nmov [rdi], edx\nloc_1398:\nadd rax, 1\ncmp esi, eax\njg short loc_1388\nadd r9, 1\nadd rdi, 4\ncmp r9, r10\njnz short loc_1380\nloc_13AD:\nsub esi, 1\nmovsxd r9, esi\nnop dword ptr [rax+rax+00h]\nloc_13B8:\nmov edi, [r8+r9*4]\ncmp edi, 9\njle loc_1488\nmov esi, 1\nnop word ptr [rax+rax+00h]\nloc_13D0:\nmov eax, edi\nlea esi, [rsi+rsi*4]\nadd esi, esi\ncdq\nidiv esi\ncmp eax, 9\njg short loc_13D0\nloc_13DF:\nmov eax, edi\nmov ecx, edi\ncdq\nsar ecx, 1Fh\nidiv esi\nmovsxd rdx, edi\nimul rdx, 66666667h\nsar rdx, 22h\nsub edx, ecx\nmov ecx, edi\nlea edx, [rdx+rdx*4]\nadd edx, edx\nsub ecx, edx\ncmp eax, ecx\njnz short loc_1470\nmov ecx, edi\njmp short loc_143D\nloc_1410:\nmov eax, ecx\nmov r10d, ecx\ncdq\nsar r10d, 1Fh\nidiv esi\nmovsxd rdx, ecx\nimul rdx, 66666667h\nsar rdx, 22h\nsub edx, r10d\nmov r10d, ecx\nlea edx, [rdx+rdx*4]\nadd edx, edx\nsub r10d, edx\ncmp eax, r10d\njnz short loc_1470\nloc_143D:\nmov eax, ecx\ncdq\nidiv esi\nmovsxd rax, esi\nsar esi, 1Fh\nimul rax, 51EB851Fh\nsar rax, 25h\nsub eax, esi\nmov esi, eax\nmovsxd rcx, edx\nsar edx, 1Fh\nimul rcx, 66666667h\nsar rcx, 22h\nsub ecx, edx\njnz short loc_1410\nloc_146C:\nmov eax, edi\nretn\nloc_1470:\nsub r9, 1\ntest r9d, r9d\njns loc_13B8\nloc_147D:\nmov edi, 0FFFFFFFFh\nmov eax, edi\nretn\nloc_1488:\ntest edi, edi\njz short loc_146C\nmov esi, 1\njmp loc_13DF", + "ida_strip_pseudo": "__int64 __fastcall sub_1360(_DWORD *a1, int a2)\n{\n _DWORD *v2; // r8\n __int64 i; // r9\n __int64 v4; // rax\n int v5; // edx\n __int64 v6; // r9\n int v7; // edi\n int v8; // esi\n int v9; // ecx\n int v10; // edx\n\n v2 = a1;\n if ( a2 <= 0 )\n return 0xFFFFFFFFLL;\n if ( a2 != 1 )\n {\n for ( i = 1LL; i != a2; ++i )\n {\n v4 = i;\n do\n {\n v5 = v2[v4];\n if ( *a1 > v5 )\n {\n v2[v4] = *a1;\n *a1 = v5;\n }\n ++v4;\n }\n while ( a2 > (int)v4 );\n ++a1;\n }\n }\n v6 = a2 - 1;\n while ( 1 )\n {\n v7 = v2[v6];\n if ( v7 <= 9 )\n {\n if ( !v7 )\n return (unsigned int)v7;\n v8 = 1;\n }\n else\n {\n v8 = 1;\n do\n v8 *= 10;\n while ( v7 / v8 > 9 );\n }\n if ( v7 / v8 == v7 % 10 )\n break;\nLABEL_18:\n if ( (int)--v6 < 0 )\n return 0xFFFFFFFFLL;\n }\n v9 = v2[v6];\n while ( 1 )\n {\n v10 = v9 % v8;\n v8 /= 100;\n v9 = v10 / 10;\n if ( !(v10 / 10) )\n return (unsigned int)v7;\n if ( v9 / v8 != v9 % 10 )\n goto LABEL_18;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1360(uint32_t *a1, int a2) {\n uint32_t *v2;\n long long i;\n long long v4;\n int v5;\n long long v6;\n int v7;\n int v8;\n int v9;\n int v10;\n v2 = a1;\n if (a2 <= 0) return 4294967295LL;\n if (a2 != 1) {\n for (i = 1LL; i != a2; ++i) {\n v4 = i;\n do {\n v5 = v2[v4];\n if (*a1 > v5) {\n v2[v4] = *a1;\n *a1 = v5;\n }\n ++v4;\n } while (a2 > (int)v4);\n ++a1;\n }\n }\n v6 = a2 - 1;\n while (1) {\n v7 = v2[v6];\n if (v7 <= 9) {\n if (!v7) return (unsigned int)v7;\n v8 = 1;\n } else {\n v8 = 1;\n do\n v8 *= 10;\n while (v7 / v8 > 9);\n }\n if (v7 / v8 == v7 % 10) break;\n LABEL_18:\n if ((int)--v6 < 0) return 4294967295LL;\n }\n v9 = v2[v6];\n while (1) {\n v10 = v9 % v8;\n v8 /= 100;\n v9 = v10 / 10;\n if (!(v10 / 10)) return (unsigned int)v7;\n if (v9 / v8 != v9 % 10) goto LABEL_18;\n }\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n long long i;\n long long v4;\n int v5;\n long long v6;\n int v7;\n int v8;\n int v9;\n int v10;\n v2 = a1;\n if (a2 <= 0) return 4294967295LL;\n if (a2 != 1) {\n for (i = 1LL; i != a2; ++i) {\n v4 = i;\n do {\n v5 = v2[v4];\n if (*a1 > v5) {\n v2[v4] = *a1;\n *a1 = v5;\n }\n ++v4;\n } while (a2 > (int)v4);\n ++a1;\n }\n }\n v6 = a2 - 1;\n while (1) {\n v7 = v2[v6];\n if (v7 <= 9) {\n if (!v7) return (unsigned int)v7;\n v8 = 1;\n } else {\n v8 = 1;\n do\n v8 *= 10;\n while (v7 / v8 > 9);\n }\n if (v7 / v8 == v7 % 10) break;\n LABEL_18:\n if ((int)--v6 < 0) return 4294967295LL;\n }\n v9 = v2[v6];\n while (1) {\n v10 = v9 % v8;\n v8 /= 100;\n v9 = v10 / 10;\n if (!(v10 / 10)) return (unsigned int)v7;\n if (v9 / v8 != v9 % 10) goto LABEL_18;\n }\n}" + }, + { + "index": 485, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nbool is_palindrome(int n) {\n\n int divisor = 1;\n\n while (n / divisor >= 10) {\n\n divisor *= 10;\n\n }\n\n while (n != 0) {\n\n int leading = n / divisor;\n\n int trailing = n % 10;\n\n if (leading != trailing) {\n\n return false;\n\n }\n\n n = (n % divisor) / 10;\n\n divisor = divisor / 100;\n\n }\n\n return true;\n\n}\n\n\n\n", + "func": "int func0(int A[], int n) {\n int i, j, temp;\n for (i = 0; i < n; i++) {\n for (j = i + 1; j < n; j++) {\n if (A[i] > A[j]) {\n temp = A[j];\n A[j] = A[i];\n A[i] = temp;\n }\n }\n }\n for (i = n - 1; i >= 0; i--) {\n if (is_palindrome(A[i])) {\n return A[i];\n }\n }\n return -1;\n}", + "test": "int main() {\n\n int arr1[4] = {1, 232, 54545, 999991};\n\n int arr2[6] = {1, 2, 3, 4, 5, 50};\n\n int arr3[5] = {1, 3, 7, 9, 45};\n\n\n\n assert(func0(arr1, 4) == 54545);\n\n assert(func0(arr2, 6) == 5);\n\n assert(func0(arr3, 5) == 9);\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nlea -0x1(%rsi),%r10d\ntest %esi,%esi\njle 14be \ncmp $0x1,%esi\nje 13d2 \nlea -0x2(%rsi),%r9d\nmov $0x1,%r8d\nadd $0x2,%r9\nnopl 0x0(%rax,%rax,1)\nmov -0x4(%rdi,%r8,4),%ecx\nmov %r8,%rax\nmov (%rdi,%rax,4),%edx\ncmp %ecx,%edx\njge 13c1 \nmov %ecx,(%rdi,%rax,4)\nmov %edx,%ecx\nmov %edx,-0x4(%rdi,%r8,4)\nadd $0x1,%rax\ncmp %eax,%esi\njg 13b0 \nadd $0x1,%r8\ncmp %r8,%r9\njne 13a8 \nmovslq %r10d,%r10\nmov $0xcccccccd,%r9d\nnopl 0x0(%rax,%rax,1)\nmov (%rdi,%r10,4),%r8d\ncmp $0x9,%r8d\njle 1490 \nmov $0x1,%ecx\nnopl 0x0(%rax,%rax,1)\nmov %r8d,%eax\nlea (%rcx,%rcx,4),%ecx\nadd %ecx,%ecx\ncltd\nidiv %ecx\ncmp $0x9,%eax\njg 13f8 \nmovslq %r8d,%rdx\nmov %r8d,%esi\nimul $0x66666667,%rdx,%rdx\nsar $0x1f,%esi\nsar $0x22,%rdx\nsub %esi,%edx\nmov %r8d,%esi\nlea (%rdx,%rdx,4),%edx\nadd %edx,%edx\nsub %edx,%esi\ncmp %esi,%eax\njne 1470 \nmov %r8d,%esi\nmov %esi,%eax\ncltd\nidiv %ecx\nmov %ecx,%ecx\nimul $0x51eb851f,%rcx,%rcx\nshr $0x25,%rcx\nmov %rdx,%rsi\nimul %r9,%rsi\nshr $0x23,%rsi\ntest %esi,%esi\nje 1483 \nmov %esi,%eax\nmov %esi,%r11d\ncltd\nidiv %ecx\nmov %esi,%edx\nimul %r9,%rdx\nshr $0x23,%rdx\nlea (%rdx,%rdx,4),%edx\nadd %edx,%edx\nsub %edx,%r11d\ncmp %r11d,%eax\nje 1430 \nsub $0x1,%r10\ntest %r10d,%r10d\njns 13e0 \nmov $0xffffffff,%r8d\nmov %r8d,%eax\nretq\nnopw 0x0(%rax,%rax,1)\ntest %r8d,%r8d\nje 1483 \nmovslq %r8d,%rax\nmov %r8d,%edx\nmov %r8d,%esi\nimul $0x66666667,%rax,%rax\nsar $0x1f,%edx\nsar $0x22,%rax\nsub %edx,%eax\nlea (%rax,%rax,4),%eax\nadd %eax,%eax\nsub %eax,%esi\ncmp %r8d,%esi\njne 1470 \nmov %r8d,%eax\nretq\ntest %r10d,%r10d\njns 13d2 \njmp 147d \nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\nmov r8, rdi\ntest esi, esi\njle loc_149D\ncmp esi, 1\njz short loc_13D4\nmov r9d, esi\nmov edi, 1\nnop dword ptr [rax+00h]\nloc_13A0:\nmov ecx, [r8+rdi*4-4]\nmov rax, rdi\nnop dword ptr [rax+rax+00000000h]\nloc_13B0:\nmov edx, [r8+rax*4]\ncmp edx, ecx\njge short loc_13C3\nmov [r8+rax*4], ecx\nmov ecx, edx\nmov [r8+rdi*4-4], edx\nloc_13C3:\nadd rax, 1\ncmp esi, eax\njg short loc_13B0\nadd rdi, 1\ncmp r9, rdi\njnz short loc_13A0\nloc_13D4:\nsub esi, 1\nmovsxd r9, esi\nnop word ptr [rax+rax+00h]\nloc_13E0:\nmov edi, [r8+r9*4]\ncmp edi, 9\njle loc_14A8\nmov esi, 1\nnop word ptr [rax+rax+00h]\nloc_13F8:\nmov eax, edi\nlea esi, [rsi+rsi*4]\nadd esi, esi\ncdq\nidiv esi\ncmp eax, 9\njg short loc_13F8\nloc_1407:\nmovsxd rdx, edi\nmov ecx, edi\nimul rdx, 66666667h\nsar ecx, 1Fh\nsar rdx, 22h\nsub edx, ecx\nmov ecx, edi\nlea edx, [rdx+rdx*4]\nadd edx, edx\nsub ecx, edx\ncmp ecx, eax\njnz short loc_1490\nmov ecx, edi\njmp short loc_145D\nloc_1430:\nmov eax, ecx\nmov r10d, ecx\ncdq\nsar r10d, 1Fh\nidiv esi\nmovsxd rdx, ecx\nimul rdx, 66666667h\nsar rdx, 22h\nsub edx, r10d\nmov r10d, ecx\nlea edx, [rdx+rdx*4]\nadd edx, edx\nsub r10d, edx\ncmp eax, r10d\njnz short loc_1490\nloc_145D:\nmov eax, ecx\ncdq\nidiv esi\nmovsxd rax, esi\nsar esi, 1Fh\nimul rax, 51EB851Fh\nsar rax, 25h\nsub eax, esi\nmov esi, eax\nmovsxd rcx, edx\nsar edx, 1Fh\nimul rcx, 66666667h\nsar rcx, 22h\nsub ecx, edx\njnz short loc_1430\nloc_148C:\nmov eax, edi\nretn\nloc_1490:\nsub r9, 1\ntest r9d, r9d\njns loc_13E0\nloc_149D:\nmov edi, 0FFFFFFFFh\nmov eax, edi\nretn\nloc_14A8:\ntest edi, edi\njz short loc_148C\nmov eax, edi\nmov esi, 1\njmp loc_1407", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 i; // rdi\n int v4; // ecx\n __int64 v5; // rax\n int v6; // edx\n __int64 v7; // r9\n int v8; // edi\n int v9; // esi\n int v10; // eax\n int v11; // ecx\n int v12; // edx\n\n if ( a2 <= 0 )\n return 0xFFFFFFFFLL;\n if ( a2 != 1 )\n {\n for ( i = 1LL; i != a2; ++i )\n {\n v4 = *(_DWORD *)(a1 + 4 * i - 4);\n v5 = i;\n do\n {\n v6 = *(_DWORD *)(a1 + 4 * v5);\n if ( v6 < v4 )\n {\n *(_DWORD *)(a1 + 4 * v5) = v4;\n v4 = v6;\n *(_DWORD *)(a1 + 4 * i - 4) = v6;\n }\n ++v5;\n }\n while ( a2 > (int)v5 );\n }\n }\n v7 = a2 - 1;\n while ( 1 )\n {\n v8 = *(_DWORD *)(a1 + 4 * v7);\n if ( v8 <= 9 )\n {\n if ( !v8 )\n return (unsigned int)v8;\n v10 = *(_DWORD *)(a1 + 4 * v7);\n v9 = 1;\n }\n else\n {\n v9 = 1;\n do\n {\n v9 *= 10;\n v10 = v8 / v9;\n }\n while ( v8 / v9 > 9 );\n }\n if ( v8 % 10 == v10 )\n break;\nLABEL_18:\n if ( (int)--v7 < 0 )\n return 0xFFFFFFFFLL;\n }\n v11 = *(_DWORD *)(a1 + 4 * v7);\n while ( 1 )\n {\n v12 = v11 % v9;\n v9 /= 100;\n v11 = v12 / 10;\n if ( !(v12 / 10) )\n return (unsigned int)v8;\n if ( v11 / v9 != v11 % 10 )\n goto LABEL_18;\n }\n}", + "ida_strip_asm": "sub_1380:\nendbr64\nmov r8, rdi\ntest esi, esi\njle loc_149D\ncmp esi, 1\njz short loc_13D4\nmov r9d, esi\nmov edi, 1\nnop dword ptr [rax+00h]\nloc_13A0:\nmov ecx, [r8+rdi*4-4]\nmov rax, rdi\nnop dword ptr [rax+rax+00000000h]\nloc_13B0:\nmov edx, [r8+rax*4]\ncmp edx, ecx\njge short loc_13C3\nmov [r8+rax*4], ecx\nmov ecx, edx\nmov [r8+rdi*4-4], edx\nloc_13C3:\nadd rax, 1\ncmp esi, eax\njg short loc_13B0\nadd rdi, 1\ncmp r9, rdi\njnz short loc_13A0\nloc_13D4:\nsub esi, 1\nmovsxd r9, esi\nnop word ptr [rax+rax+00h]\nloc_13E0:\nmov edi, [r8+r9*4]\ncmp edi, 9\njle loc_14A8\nmov esi, 1\nnop word ptr [rax+rax+00h]\nloc_13F8:\nmov eax, edi\nlea esi, [rsi+rsi*4]\nadd esi, esi\ncdq\nidiv esi\ncmp eax, 9\njg short loc_13F8\nloc_1407:\nmovsxd rdx, edi\nmov ecx, edi\nimul rdx, 66666667h\nsar ecx, 1Fh\nsar rdx, 22h\nsub edx, ecx\nmov ecx, edi\nlea edx, [rdx+rdx*4]\nadd edx, edx\nsub ecx, edx\ncmp ecx, eax\njnz short loc_1490\nmov ecx, edi\njmp short loc_145D\nloc_1430:\nmov eax, ecx\nmov r10d, ecx\ncdq\nsar r10d, 1Fh\nidiv esi\nmovsxd rdx, ecx\nimul rdx, 66666667h\nsar rdx, 22h\nsub edx, r10d\nmov r10d, ecx\nlea edx, [rdx+rdx*4]\nadd edx, edx\nsub r10d, edx\ncmp eax, r10d\njnz short loc_1490\nloc_145D:\nmov eax, ecx\ncdq\nidiv esi\nmovsxd rax, esi\nsar esi, 1Fh\nimul rax, 51EB851Fh\nsar rax, 25h\nsub eax, esi\nmov esi, eax\nmovsxd rcx, edx\nsar edx, 1Fh\nimul rcx, 66666667h\nsar rcx, 22h\nsub ecx, edx\njnz short loc_1430\nloc_148C:\nmov eax, edi\nretn\nloc_1490:\nsub r9, 1\ntest r9d, r9d\njns loc_13E0\nloc_149D:\nmov edi, 0FFFFFFFFh\nmov eax, edi\nretn\nloc_14A8:\ntest edi, edi\njz short loc_148C\nmov eax, edi\nmov esi, 1\njmp loc_1407", + "ida_strip_pseudo": "__int64 __fastcall sub_1380(__int64 a1, int a2)\n{\n __int64 i; // rdi\n int v4; // ecx\n __int64 v5; // rax\n int v6; // edx\n __int64 v7; // r9\n int v8; // edi\n int v9; // esi\n int v10; // eax\n int v11; // ecx\n int v12; // edx\n\n if ( a2 <= 0 )\n return 0xFFFFFFFFLL;\n if ( a2 != 1 )\n {\n for ( i = 1LL; i != a2; ++i )\n {\n v4 = *(_DWORD *)(a1 + 4 * i - 4);\n v5 = i;\n do\n {\n v6 = *(_DWORD *)(a1 + 4 * v5);\n if ( v6 < v4 )\n {\n *(_DWORD *)(a1 + 4 * v5) = v4;\n v4 = v6;\n *(_DWORD *)(a1 + 4 * i - 4) = v6;\n }\n ++v5;\n }\n while ( a2 > (int)v5 );\n }\n }\n v7 = a2 - 1;\n while ( 1 )\n {\n v8 = *(_DWORD *)(a1 + 4 * v7);\n if ( v8 <= 9 )\n {\n if ( !v8 )\n return (unsigned int)v8;\n v10 = *(_DWORD *)(a1 + 4 * v7);\n v9 = 1;\n }\n else\n {\n v9 = 1;\n do\n {\n v9 *= 10;\n v10 = v8 / v9;\n }\n while ( v8 / v9 > 9 );\n }\n if ( v8 % 10 == v10 )\n break;\nLABEL_18:\n if ( (int)--v7 < 0 )\n return 0xFFFFFFFFLL;\n }\n v11 = *(_DWORD *)(a1 + 4 * v7);\n while ( 1 )\n {\n v12 = v11 % v9;\n v9 /= 100;\n v11 = v12 / 10;\n if ( !(v12 / 10) )\n return (unsigned int)v8;\n if ( v11 / v9 != v11 % 10 )\n goto LABEL_18;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1380(long long a1, int a2) {\n long long i;\n int v4;\n long long v5;\n int v6;\n long long v7;\n int v8;\n int v9;\n int v10;\n int v11;\n int v12;\n if (a2 <= 0) return 4294967295LL;\n if (a2 != 1) {\n for (i = 1LL; i != a2; ++i) {\n v4 = *(uint32_t *)(a1 + 4 * i - 4);\n v5 = i;\n do {\n v6 = *(uint32_t *)(a1 + 4 * v5);\n if (v6 < v4) {\n *(uint32_t *)(a1 + 4 * v5) = v4;\n v4 = v6;\n *(uint32_t *)(a1 + 4 * i - 4) = v6;\n }\n ++v5;\n } while (a2 > (int)v5);\n }\n }\n v7 = a2 - 1;\n while (1) {\n v8 = *(uint32_t *)(a1 + 4 * v7);\n if (v8 <= 9) {\n if (!v8) return (unsigned int)v8;\n v10 = *(uint32_t *)(a1 + 4 * v7);\n v9 = 1;\n } else {\n v9 = 1;\n do {\n v9 *= 10;\n v10 = v8 / v9;\n } while (v8 / v9 > 9);\n }\n if (v8 % 10 == v10) break;\n LABEL_18:\n if ((int)--v7 < 0) return 4294967295LL;\n }\n v11 = *(uint32_t *)(a1 + 4 * v7);\n while (1) {\n v12 = v11 % v9;\n v9 /= 100;\n v11 = v12 / 10;\n if (!(v12 / 10)) return (unsigned int)v8;\n if (v11 / v9 != v11 % 10) goto LABEL_18;\n }\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long i;\n int v4;\n long long v5;\n int v6;\n long long v7;\n int v8;\n int v9;\n int v10;\n int v11;\n int v12;\n if (a2 <= 0) return 4294967295LL;\n if (a2 != 1) {\n for (i = 1LL; i != a2; ++i) {\n v4 = *(uint32_t *)(a1 + 4 * i - 4);\n v5 = i;\n do {\n v6 = *(uint32_t *)(a1 + 4 * v5);\n if (v6 < v4) {\n *(uint32_t *)(a1 + 4 * v5) = v4;\n v4 = v6;\n *(uint32_t *)(a1 + 4 * i - 4) = v6;\n }\n ++v5;\n } while (a2 > (int)v5);\n }\n }\n v7 = a2 - 1;\n while (1) {\n v8 = *(uint32_t *)(a1 + 4 * v7);\n if (v8 <= 9) {\n if (!v8) return (unsigned int)v8;\n v10 = *(uint32_t *)(a1 + 4 * v7);\n v9 = 1;\n } else {\n v9 = 1;\n do {\n v9 *= 10;\n v10 = v8 / v9;\n } while (v8 / v9 > 9);\n }\n if (v8 % 10 == v10) break;\n LABEL_18:\n if ((int)--v7 < 0) return 4294967295LL;\n }\n v11 = *(uint32_t *)(a1 + 4 * v7);\n while (1) {\n v12 = v11 % v9;\n v9 /= 100;\n v11 = v12 / 10;\n if (!(v12 / 10)) return (unsigned int)v8;\n if (v11 / v9 != v11 % 10) goto LABEL_18;\n }\n}" + }, + { + "index": 486, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "double func0(int n, int r, double p) {\n int r0 = r;\n if (r > n / 2) r = n - r;\n double answer = 1.0;\n for (int i = 1; i <= r; i++) {\n answer *= (n - r + i);\n answer /= i;\n }\n return answer * pow(p, r0) * pow(1 - p, n - r0);\n}", + "test": "int main() {\n\n assert(fabs(func0(10, 5, 1.0 / 3) - 0.13656454808718185) < 0.0000001);\n\n assert(fabs(func0(11, 6, 2.0 / 4) - 0.2255859375) < 0.0000001);\n\n assert(fabs(func0(12, 7, 3.0 / 5) - 0.227030335488) < 0.0000001);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmovsd %xmm0,-0x20(%rbp)\nmov -0x18(%rbp),%eax\nmov %eax,-0xc(%rbp)\nmov -0x14(%rbp),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\ncmp %eax,-0x18(%rbp)\njle 11a0 \nmov -0x14(%rbp),%eax\nsub -0x18(%rbp),%eax\nmov %eax,-0x18(%rbp)\nmovsd 0xf60(%rip),%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmovl $0x1,-0x10(%rbp)\njmp 11ec \nmov -0x14(%rbp),%eax\nsub -0x18(%rbp),%eax\nmov %eax,%edx\nmov -0x10(%rbp),%eax\nadd %edx,%eax\ncvtsi2sd %eax,%xmm0\nmovsd -0x8(%rbp),%xmm1\nmulsd %xmm1,%xmm0\nmovsd %xmm0,-0x8(%rbp)\ncvtsi2sdl -0x10(%rbp),%xmm1\nmovsd -0x8(%rbp),%xmm0\ndivsd %xmm1,%xmm0\nmovsd %xmm0,-0x8(%rbp)\naddl $0x1,-0x10(%rbp)\nmov -0x10(%rbp),%eax\ncmp -0x18(%rbp),%eax\njle 11b6 \ncvtsi2sdl -0xc(%rbp),%xmm0\nmov -0x20(%rbp),%rax\nmovapd %xmm0,%xmm1\nmovq %rax,%xmm0\ncallq 1060 \nmulsd -0x8(%rbp),%xmm0\nmovsd %xmm0,-0x28(%rbp)\nmov -0x14(%rbp),%eax\nsub -0xc(%rbp),%eax\ncvtsi2sd %eax,%xmm1\nmovsd 0xee1(%rip),%xmm0\nsubsd -0x20(%rbp),%xmm0\ncallq 1060 \nmulsd -0x28(%rbp),%xmm0\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmovsd [rbp+x], xmm0\nmov eax, [rbp+var_18]\nmov [rbp+var_C], eax\nmov eax, [rbp+var_14]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\ncmp [rbp+var_18], eax\njle short loc_11A0\nmov eax, [rbp+var_14]\nsub eax, [rbp+var_18]\nmov [rbp+var_18], eax\nloc_11A0:\nmovsd xmm0, cs:qword_20E8\nmovsd [rbp+var_8], xmm0\nmov [rbp+var_10], 1\njmp short loc_11F4\nloc_11B6:\nmov eax, [rbp+var_14]\nsub eax, [rbp+var_18]\nmov edx, eax\nmov eax, [rbp+var_10]\nadd eax, edx\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmovsd xmm1, [rbp+var_8]\nmulsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_10]\nmovsd xmm0, [rbp+var_8]\ndivsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nadd [rbp+var_10], 1\nloc_11F4:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_18]\njle short loc_11B6\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_C]\nmov rax, [rbp+x]\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\nmovq rax, xmm0\nmovq xmm2, rax\nmulsd xmm2, [rbp+var_8]\nmovsd [rbp+var_28], xmm2\nmov eax, [rbp+var_14]\nsub eax, [rbp+var_C]\npxor xmm1, xmm1\ncvtsi2sd xmm1, eax; y\nmovsd xmm0, cs:qword_20E8\nsubsd xmm0, [rbp+x]\nmovq rax, xmm0\nmovq xmm0, rax; x\ncall _pow\nmulsd xmm0, [rbp+var_28]\nleave\nretn", + "ida_pseudo": "double __fastcall func0(int a1, int a2, double a3)\n{\n double v4; // [rsp+8h] [rbp-28h]\n int v6; // [rsp+18h] [rbp-18h]\n int i; // [rsp+20h] [rbp-10h]\n double v8; // [rsp+28h] [rbp-8h]\n\n v6 = a2;\n if ( a2 > a1 / 2 )\n v6 = a1 - a2;\n v8 = 1.0;\n for ( i = 1; i <= v6; ++i )\n v8 = (double)(a1 - v6 + i) * v8 / (double)i;\n v4 = pow(a3, (double)a2) * v8;\n return pow(1.0 - a3, (double)(a1 - a2)) * v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmovsd [rbp+x], xmm0\nmov eax, [rbp+var_18]\nmov [rbp+var_C], eax\nmov eax, [rbp+var_14]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\ncmp [rbp+var_18], eax\njle short loc_11A0\nmov eax, [rbp+var_14]\nsub eax, [rbp+var_18]\nmov [rbp+var_18], eax\nloc_11A0:\nmovsd xmm0, cs:qword_20E8\nmovsd [rbp+var_8], xmm0\nmov [rbp+var_10], 1\njmp short loc_11F4\nloc_11B6:\nmov eax, [rbp+var_14]\nsub eax, [rbp+var_18]\nmov edx, eax\nmov eax, [rbp+var_10]\nadd eax, edx\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmovsd xmm1, [rbp+var_8]\nmulsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_10]\nmovsd xmm0, [rbp+var_8]\ndivsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nadd [rbp+var_10], 1\nloc_11F4:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_18]\njle short loc_11B6\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_C]\nmov rax, [rbp+x]\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\nmovq rax, xmm0\nmovq xmm2, rax\nmulsd xmm2, [rbp+var_8]\nmovsd [rbp+var_28], xmm2\nmov eax, [rbp+var_14]\nsub eax, [rbp+var_C]\npxor xmm1, xmm1\ncvtsi2sd xmm1, eax; y\nmovsd xmm0, cs:qword_20E8\nsubsd xmm0, [rbp+x]\nmovq rax, xmm0\nmovq xmm0, rax; x\ncall _pow\nmulsd xmm0, [rbp+var_28]\nleave\nretn", + "ida_strip_pseudo": "double __fastcall sub_1169(int a1, int a2, double a3)\n{\n double v4; // [rsp+8h] [rbp-28h]\n int v6; // [rsp+18h] [rbp-18h]\n int i; // [rsp+20h] [rbp-10h]\n double v8; // [rsp+28h] [rbp-8h]\n\n v6 = a2;\n if ( a2 > a1 / 2 )\n v6 = a1 - a2;\n v8 = 1.0;\n for ( i = 1; i <= v6; ++i )\n v8 = (double)(a1 - v6 + i) * v8 / (double)i;\n v4 = pow(a3, (double)a2) * v8;\n return pow(1.0 - a3, (double)(a1 - a2)) * v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1169(int a1, int a2, double a3) {\n double v4;\n int v6;\n int i;\n double v8;\n v6 = a2;\n if (a2 > a1 / 2) v6 = a1 - a2;\n v8 = 1.0;\n for (i = 1; i <= v6; ++i) v8 = (double)(a1 - v6 + i) * v8 / (double)i;\n v4 = pow(a3, (double)a2) * v8;\n return pow(1.0 - a3, (double)(a1 - a2)) * v4;\n}", + "ida_pseudo_norm": "double func0(int a1, int a2, double a3) {\n double v4;\n int v6;\n int i;\n double v8;\n v6 = a2;\n if (a2 > a1 / 2) v6 = a1 - a2;\n v8 = 1.0;\n for (i = 1; i <= v6; ++i) v8 = (double)(a1 - v6 + i) * v8 / (double)i;\n v4 = pow(a3, (double)a2) * v8;\n return pow(1.0 - a3, (double)(a1 - a2)) * v4;\n}" + }, + { + "index": 486, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "double func0(int n, int r, double p) {\n int r0 = r;\n if (r > n / 2) r = n - r;\n double answer = 1.0;\n for (int i = 1; i <= r; i++) {\n answer *= (n - r + i);\n answer /= i;\n }\n return answer * pow(p, r0) * pow(1 - p, n - r0);\n}", + "test": "int main() {\n\n assert(fabs(func0(10, 5, 1.0 / 3) - 0.13656454808718185) < 0.0000001);\n\n assert(fabs(func0(11, 6, 2.0 / 4) - 0.2255859375) < 0.0000001);\n\n assert(fabs(func0(12, 7, 3.0 / 5) - 0.227030335488) < 0.0000001);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x28,%rsp\nmov %edi,%ebx\nmov %esi,%ebp\nmovsd %xmm0,0x10(%rsp)\nmov %edi,%eax\nshr $0x1f,%eax\nadd %edi,%eax\nsar %eax\nmov %edi,%edx\nsub %esi,%edx\ncmp %esi,%eax\nmov %edx,%eax\ncmovge %esi,%eax\ntest %eax,%eax\njle 122e \nlea 0x1(%rax),%esi\nmov $0x1,%edx\nmovsd 0xf57(%rip),%xmm5\nmovsd %xmm5,0x8(%rsp)\nmov %edi,%ecx\nsub %eax,%ecx\nlea (%rcx,%rdx,1),%eax\npxor %xmm0,%xmm0\ncvtsi2sd %eax,%xmm0\nmulsd 0x8(%rsp),%xmm0\npxor %xmm1,%xmm1\ncvtsi2sd %edx,%xmm1\ndivsd %xmm1,%xmm0\nmovsd %xmm0,0x8(%rsp)\nadd $0x1,%edx\ncmp %esi,%edx\njne 11b3 \npxor %xmm1,%xmm1\ncvtsi2sd %ebp,%xmm1\nmovsd 0x10(%rsp),%xmm0\ncallq 1060 \nmovsd %xmm0,0x18(%rsp)\nsub %ebp,%ebx\nmovsd 0xf00(%rip),%xmm0\nsubsd 0x10(%rsp),%xmm0\npxor %xmm1,%xmm1\ncvtsi2sd %ebx,%xmm1\ncallq 1060 \nmovapd %xmm0,%xmm1\nmovsd 0x18(%rsp),%xmm0\nmulsd 0x8(%rsp),%xmm0\nmulsd %xmm1,%xmm0\nadd $0x28,%rsp\npop %rbx\npop %rbp\nretq\nmovsd 0xeca(%rip),%xmm6\nmovsd %xmm6,0x8(%rsp)\njmp 11dd \n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 28h\nmov ebx, edi\nmov ebp, esi\nmovsd [rsp+38h+x], xmm0\nmov eax, edi\nshr eax, 1Fh\nadd eax, edi\nsar eax, 1\nmov edx, edi\nsub edx, esi\ncmp eax, esi\ncmovge edx, esi\ntest edx, edx\njle loc_122C\nlea esi, [rdx+1]\nmov eax, 1\nmovsd xmm5, cs:qword_20E0\nmovsd [rsp+38h+var_30], xmm5\nmov ecx, edi\nsub ecx, edx\nloc_11B1:\nlea edx, [rcx+rax]\npxor xmm0, xmm0\ncvtsi2sd xmm0, edx\nmulsd xmm0, [rsp+38h+var_30]\npxor xmm1, xmm1\ncvtsi2sd xmm1, eax\ndivsd xmm0, xmm1\nmovsd [rsp+38h+var_30], xmm0\nadd eax, 1\ncmp eax, esi\njnz short loc_11B1\nloc_11DB:\npxor xmm1, xmm1\ncvtsi2sd xmm1, ebp; y\nmovsd xmm0, [rsp+38h+x]; x\ncall _pow\nmovsd [rsp+38h+var_20], xmm0\nsub ebx, ebp\nmovsd xmm0, cs:qword_20E0\nsubsd xmm0, [rsp+38h+x]; x\npxor xmm1, xmm1\ncvtsi2sd xmm1, ebx; y\ncall _pow\nmovapd xmm1, xmm0\nmovsd xmm0, [rsp+38h+var_20]\nmulsd xmm0, [rsp+38h+var_30]\nmulsd xmm0, xmm1\nadd rsp, 28h\npop rbx\npop rbp\nretn\nloc_122C:\nmovsd xmm6, cs:qword_20E0\nmovsd [rsp+38h+var_30], xmm6\njmp short loc_11DB", + "ida_pseudo": "double __fastcall func0(int a1, int a2, double a3)\n{\n int v3; // edx\n int v4; // eax\n double v6; // [rsp+8h] [rbp-30h]\n double v8; // [rsp+18h] [rbp-20h]\n\n v3 = a1 - a2;\n if ( a1 / 2 >= a2 )\n v3 = a2;\n if ( v3 <= 0 )\n {\n v6 = 1.0;\n }\n else\n {\n v4 = 1;\n v6 = 1.0;\n do\n {\n v6 = (double)(a1 - v3 + v4) * v6 / (double)v4;\n ++v4;\n }\n while ( v4 != v3 + 1 );\n }\n v8 = pow(a3, (double)a2);\n return v8 * v6 * pow(1.0 - a3, (double)(a1 - a2));\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\npush rbx\nsub rsp, 28h\nmov ebx, edi\nmov ebp, esi\nmovsd [rsp+38h+x], xmm0\nmov eax, edi\nshr eax, 1Fh\nadd eax, edi\nsar eax, 1\nmov edx, edi\nsub edx, esi\ncmp eax, esi\ncmovge edx, esi\ntest edx, edx\njle loc_122C\nlea esi, [rdx+1]\nmov eax, 1\nmovsd xmm5, cs:qword_20E0\nmovsd [rsp+38h+var_30], xmm5\nmov ecx, edi\nsub ecx, edx\nloc_11B1:\nlea edx, [rcx+rax]\npxor xmm0, xmm0\ncvtsi2sd xmm0, edx\nmulsd xmm0, [rsp+38h+var_30]\npxor xmm1, xmm1\ncvtsi2sd xmm1, eax\ndivsd xmm0, xmm1\nmovsd [rsp+38h+var_30], xmm0\nadd eax, 1\ncmp eax, esi\njnz short loc_11B1\nloc_11DB:\npxor xmm1, xmm1\ncvtsi2sd xmm1, ebp; y\nmovsd xmm0, [rsp+38h+x]; x\ncall _pow\nmovsd [rsp+38h+var_20], xmm0\nsub ebx, ebp\nmovsd xmm0, cs:qword_20E0\nsubsd xmm0, [rsp+38h+x]; x\npxor xmm1, xmm1\ncvtsi2sd xmm1, ebx; y\ncall _pow\nmovapd xmm1, xmm0\nmovsd xmm0, [rsp+38h+var_20]\nmulsd xmm0, [rsp+38h+var_30]\nmulsd xmm0, xmm1\nadd rsp, 28h\npop rbx\npop rbp\nretn\nloc_122C:\nmovsd xmm6, cs:qword_20E0\nmovsd [rsp+38h+var_30], xmm6\njmp short loc_11DB", + "ida_strip_pseudo": "double __fastcall sub_1169(int a1, int a2, double a3)\n{\n int v3; // edx\n int v4; // eax\n double v6; // [rsp+8h] [rbp-30h]\n double v8; // [rsp+18h] [rbp-20h]\n\n v3 = a1 - a2;\n if ( a1 / 2 >= a2 )\n v3 = a2;\n if ( v3 <= 0 )\n {\n v6 = 1.0;\n }\n else\n {\n v4 = 1;\n v6 = 1.0;\n do\n {\n v6 = (double)(a1 - v3 + v4) * v6 / (double)v4;\n ++v4;\n }\n while ( v4 != v3 + 1 );\n }\n v8 = pow(a3, (double)a2);\n return v8 * v6 * pow(1.0 - a3, (double)(a1 - a2));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1169(int a1, int a2, double a3) {\n int v3;\n int v4;\n double v6;\n double v8;\n v3 = a1 - a2;\n if (a1 / 2 >= a2) v3 = a2;\n if (v3 <= 0) {\n v6 = 1.0;\n } else {\n v4 = 1;\n v6 = 1.0;\n do {\n v6 = (double)(a1 - v3 + v4) * v6 / (double)v4;\n ++v4;\n } while (v4 != v3 + 1);\n }\n v8 = pow(a3, (double)a2);\n return v8 * v6 * pow(1.0 - a3, (double)(a1 - a2));\n}", + "ida_pseudo_norm": "double func0(int a1, int a2, double a3) {\n int v3;\n int v4;\n double v6;\n double v8;\n v3 = a1 - a2;\n if (a1 / 2 >= a2) v3 = a2;\n if (v3 <= 0) {\n v6 = 1.0;\n } else {\n v4 = 1;\n v6 = 1.0;\n do {\n v6 = (double)(a1 - v3 + v4) * v6 / (double)v4;\n ++v4;\n } while (v4 != v3 + 1);\n }\n v8 = pow(a3, (double)a2);\n return v8 * v6 * pow(1.0 - a3, (double)(a1 - a2));\n}" + }, + { + "index": 486, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "double func0(int n, int r, double p) {\n int r0 = r;\n if (r > n / 2) r = n - r;\n double answer = 1.0;\n for (int i = 1; i <= r; i++) {\n answer *= (n - r + i);\n answer /= i;\n }\n return answer * pow(p, r0) * pow(1 - p, n - r0);\n}", + "test": "int main() {\n\n assert(fabs(func0(10, 5, 1.0 / 3) - 0.13656454808718185) < 0.0000001);\n\n assert(fabs(func0(11, 6, 2.0 / 4) - 0.2255859375) < 0.0000001);\n\n assert(fabs(func0(12, 7, 3.0 / 5) - 0.227030335488) < 0.0000001);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov %edi,%eax\npush %rbx\nmov %edi,%ebx\nmov %esi,%ecx\nshr $0x1f,%eax\nsub %esi,%ebx\nmovapd %xmm0,%xmm3\nadd %edi,%eax\nsar %eax\nsub $0x20,%rsp\ncmp %esi,%eax\ncmovl %ebx,%ecx\ntest %ecx,%ecx\njle 1340 \nmovsd 0xe4f(%rip),%xmm4\nsub %ecx,%edi\nmov $0x1,%eax\nadd $0x1,%ecx\nmovapd %xmm4,%xmm2\nlea (%rax,%rdi,1),%edx\npxor %xmm0,%xmm0\ncvtsi2sd %edx,%xmm0\nmulsd %xmm0,%xmm2\npxor %xmm0,%xmm0\ncvtsi2sd %eax,%xmm0\nadd $0x1,%eax\ndivsd %xmm0,%xmm2\ncmp %ecx,%eax\njne 12c0 \npxor %xmm1,%xmm1\nmovapd %xmm3,%xmm0\nmovsd %xmm2,0x10(%rsp)\ncvtsi2sd %esi,%xmm1\nmovsd %xmm4,0x18(%rsp)\nmovsd %xmm3,0x8(%rsp)\ncallq 1060 \nmovsd 0x18(%rsp),%xmm4\nmovsd 0x8(%rsp),%xmm3\npxor %xmm1,%xmm1\ncvtsi2sd %ebx,%xmm1\nmovsd %xmm0,(%rsp)\nsubsd %xmm3,%xmm4\nmovapd %xmm4,%xmm0\ncallq 1060 \nmovsd 0x10(%rsp),%xmm2\nmulsd (%rsp),%xmm2\nadd $0x20,%rsp\npop %rbx\nmulsd %xmm2,%xmm0\nretq\nmovsd 0xdb8(%rip),%xmm4\nmovapd %xmm4,%xmm2\njmp 12e2 \nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\nmov eax, edi\npush rbx\nmov ebx, edi\nmov ecx, esi\nshr eax, 1Fh\nsub ebx, esi\nmovapd xmm3, xmm0\nadd eax, edi\nsar eax, 1\nsub rsp, 20h\ncmp eax, esi\ncmovl ecx, ebx\ntest ecx, ecx\njle loc_1350\nmovsd xmm4, cs:qword_20E0\nsub edi, ecx\nmov eax, 1\nadd ecx, 1\nmovapd xmm2, xmm4\nnop\nloc_12C0:\nlea edx, [rax+rdi]\npxor xmm1, xmm1\ncvtsi2sd xmm1, edx\nmulsd xmm2, xmm1\npxor xmm1, xmm1\ncvtsi2sd xmm1, eax\nadd eax, 1\ndivsd xmm2, xmm1\ncmp eax, ecx\njnz short loc_12C0\nloc_12E2:\npxor xmm1, xmm1\nmovapd xmm0, xmm3; x\nmovsd [rsp+28h+var_18], xmm2\ncvtsi2sd xmm1, esi; y\nmovsd [rsp+28h+var_10], xmm4\nmovsd [rsp+28h+var_20], xmm3\ncall _pow\nmovsd xmm4, [rsp+28h+var_10]\nmovsd xmm3, [rsp+28h+var_20]\npxor xmm1, xmm1\ncvtsi2sd xmm1, ebx; y\nmovsd [rsp+28h+var_28], xmm0\nsubsd xmm4, xmm3\nmovapd xmm0, xmm4; x\ncall _pow\nmovsd xmm2, [rsp+28h+var_18]\nmovapd xmm1, xmm0\nmovsd xmm0, [rsp+28h+var_28]\nadd rsp, 20h\npop rbx\nmulsd xmm0, xmm2\nmulsd xmm0, xmm1\nretn\nloc_1350:\nmovsd xmm4, cs:qword_20E0\nmovapd xmm2, xmm4\njmp short loc_12E2", + "ida_pseudo": "double __fastcall func0(int a1, int a2, double a3)\n{\n int v3; // ecx\n int v4; // ebx\n int v5; // edi\n int v6; // eax\n int v7; // ecx\n double v8; // xmm2_8\n int v9; // edx\n double v10; // xmm1_8\n double v12; // [rsp+0h] [rbp-28h]\n\n v3 = a2;\n v4 = a1 - a2;\n if ( a1 / 2 < a2 )\n v3 = a1 - a2;\n if ( v3 <= 0 )\n {\n v8 = 1.0;\n }\n else\n {\n v5 = a1 - v3;\n v6 = 1;\n v7 = v3 + 1;\n v8 = 1.0;\n do\n {\n v9 = v6 + v5;\n v10 = (double)v6++;\n v8 = v8 * (double)v9 / v10;\n }\n while ( v6 != v7 );\n }\n v12 = pow(a3, (double)a2);\n return v12 * v8 * pow(1.0 - a3, (double)v4);\n}", + "ida_strip_asm": "sub_1280:\nendbr64\nmov eax, edi\npush rbx\nmov ebx, edi\nmov ecx, esi\nshr eax, 1Fh\nsub ebx, esi\nmovapd xmm3, xmm0\nadd eax, edi\nsar eax, 1\nsub rsp, 20h\ncmp eax, esi\ncmovl ecx, ebx\ntest ecx, ecx\njle loc_1350\nmovsd xmm4, cs:qword_20E0\nsub edi, ecx\nmov eax, 1\nadd ecx, 1\nmovapd xmm2, xmm4\nnop\nloc_12C0:\nlea edx, [rax+rdi]\npxor xmm1, xmm1\ncvtsi2sd xmm1, edx\nmulsd xmm2, xmm1\npxor xmm1, xmm1\ncvtsi2sd xmm1, eax\nadd eax, 1\ndivsd xmm2, xmm1\ncmp eax, ecx\njnz short loc_12C0\nloc_12E2:\npxor xmm1, xmm1\nmovapd xmm0, xmm3; x\nmovsd [rsp+28h+var_18], xmm2\ncvtsi2sd xmm1, esi; y\nmovsd [rsp+28h+var_10], xmm4\nmovsd [rsp+28h+var_20], xmm3\ncall _pow\nmovsd xmm4, [rsp+28h+var_10]\nmovsd xmm3, [rsp+28h+var_20]\npxor xmm1, xmm1\ncvtsi2sd xmm1, ebx; y\nmovsd [rsp+28h+var_28], xmm0\nsubsd xmm4, xmm3\nmovapd xmm0, xmm4; x\ncall _pow\nmovsd xmm2, [rsp+28h+var_18]\nmovapd xmm1, xmm0\nmovsd xmm0, [rsp+28h+var_28]\nadd rsp, 20h\npop rbx\nmulsd xmm0, xmm2\nmulsd xmm0, xmm1\nretn\nloc_1350:\nmovsd xmm4, cs:qword_20E0\nmovapd xmm2, xmm4\njmp short loc_12E2", + "ida_strip_pseudo": "double __fastcall sub_1280(int a1, int a2, double a3)\n{\n int v3; // ecx\n int v4; // ebx\n int v5; // edi\n int v6; // eax\n int v7; // ecx\n double v8; // xmm2_8\n int v9; // edx\n double v10; // xmm1_8\n double v12; // [rsp+0h] [rbp-28h]\n\n v3 = a2;\n v4 = a1 - a2;\n if ( a1 / 2 < a2 )\n v3 = a1 - a2;\n if ( v3 <= 0 )\n {\n v8 = 1.0;\n }\n else\n {\n v5 = a1 - v3;\n v6 = 1;\n v7 = v3 + 1;\n v8 = 1.0;\n do\n {\n v9 = v6 + v5;\n v10 = (double)v6++;\n v8 = v8 * (double)v9 / v10;\n }\n while ( v6 != v7 );\n }\n v12 = pow(a3, (double)a2);\n return v12 * v8 * pow(1.0 - a3, (double)v4);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1280(int a1, int a2, double a3) {\n int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n double v8;\n int v9;\n double v10;\n double v12;\n v3 = a2;\n v4 = a1 - a2;\n if (a1 / 2 < a2) v3 = a1 - a2;\n if (v3 <= 0) {\n v8 = 1.0;\n } else {\n v5 = a1 - v3;\n v6 = 1;\n v7 = v3 + 1;\n v8 = 1.0;\n do {\n v9 = v6 + v5;\n v10 = (double)v6++;\n v8 = v8 * (double)v9 / v10;\n } while (v6 != v7);\n }\n v12 = pow(a3, (double)a2);\n return v12 * v8 * pow(1.0 - a3, (double)v4);\n}", + "ida_pseudo_norm": "double func0(int a1, int a2, double a3) {\n int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n double v8;\n int v9;\n double v10;\n double v12;\n v3 = a2;\n v4 = a1 - a2;\n if (a1 / 2 < a2) v3 = a1 - a2;\n if (v3 <= 0) {\n v8 = 1.0;\n } else {\n v5 = a1 - v3;\n v6 = 1;\n v7 = v3 + 1;\n v8 = 1.0;\n do {\n v9 = v6 + v5;\n v10 = (double)v6++;\n v8 = v8 * (double)v9 / v10;\n } while (v6 != v7);\n }\n v12 = pow(a3, (double)a2);\n return v12 * v8 * pow(1.0 - a3, (double)v4);\n}" + }, + { + "index": 486, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "double func0(int n, int r, double p) {\n int r0 = r;\n if (r > n / 2) r = n - r;\n double answer = 1.0;\n for (int i = 1; i <= r; i++) {\n answer *= (n - r + i);\n answer /= i;\n }\n return answer * pow(p, r0) * pow(1 - p, n - r0);\n}", + "test": "int main() {\n\n assert(fabs(func0(10, 5, 1.0 / 3) - 0.13656454808718185) < 0.0000001);\n\n assert(fabs(func0(11, 6, 2.0 / 4) - 0.2255859375) < 0.0000001);\n\n assert(fabs(func0(12, 7, 3.0 / 5) - 0.227030335488) < 0.0000001);\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %edi,%eax\nmov %edi,%ebx\nshr $0x1f,%edi\nadd %eax,%edi\nmovapd %xmm0,%xmm3\nsub %esi,%ebx\nsar %edi\nsub $0x20,%rsp\ncmp %esi,%edi\njl 1350 \nmov %esi,%ecx\nmov %ebx,%edi\ntest %ecx,%ecx\njle 135c \nmovsd 0xe4a(%rip),%xmm4\nadd $0x1,%ecx\nmov $0x1,%eax\nmovapd %xmm4,%xmm2\nnopw 0x0(%rax,%rax,1)\nlea (%rax,%rdi,1),%edx\npxor %xmm0,%xmm0\ncvtsi2sd %edx,%xmm0\nmulsd %xmm0,%xmm2\npxor %xmm0,%xmm0\ncvtsi2sd %eax,%xmm0\nadd $0x1,%eax\ndivsd %xmm0,%xmm2\ncmp %eax,%ecx\njne 12c8 \npxor %xmm1,%xmm1\nmovapd %xmm3,%xmm0\nmovsd %xmm2,0x10(%rsp)\ncvtsi2sd %esi,%xmm1\nmovsd %xmm4,0x18(%rsp)\nmovsd %xmm3,0x8(%rsp)\ncallq 1060 \nmovsd 0x18(%rsp),%xmm4\nmovsd 0x8(%rsp),%xmm3\npxor %xmm1,%xmm1\ncvtsi2sd %ebx,%xmm1\nmovsd %xmm0,(%rsp)\nsubsd %xmm3,%xmm4\nmovapd %xmm4,%xmm0\ncallq 1060 \nmovsd 0x10(%rsp),%xmm2\nmulsd (%rsp),%xmm2\nadd $0x20,%rsp\npop %rbx\nmulsd %xmm2,%xmm0\nretq\nnopl 0x0(%rax,%rax,1)\nmov %ebx,%ecx\nmov %esi,%edi\ntest %ecx,%ecx\njg 12ae \nmovsd 0xd9c(%rip),%xmm4\nmovapd %xmm4,%xmm2\njmp 12ea \nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmov eax, edi\npush rbx\nmov ebx, edi\nmovapd xmm3, xmm0\nshr eax, 1Fh\nsub ebx, esi\nadd eax, edi\nsar eax, 1\nsub rsp, 20h\ncmp eax, esi\njl loc_1350\nmov ecx, esi\nmov edi, ebx\ntest ecx, ecx\njle loc_135C\nloc_12AE:\nmovsd xmm4, cs:qword_20E0\nadd ecx, 1\nmov eax, 1\nmovapd xmm2, xmm4\nnop word ptr [rax+rax+00h]\nloc_12C8:\nlea edx, [rax+rdi]\npxor xmm1, xmm1\ncvtsi2sd xmm1, edx\nmulsd xmm2, xmm1\npxor xmm1, xmm1\ncvtsi2sd xmm1, eax\nadd eax, 1\ndivsd xmm2, xmm1\ncmp eax, ecx\njnz short loc_12C8\nloc_12EA:\npxor xmm1, xmm1\nmovapd xmm0, xmm3; x\nmovsd [rsp+28h+var_18], xmm2\ncvtsi2sd xmm1, esi; y\nmovsd [rsp+28h+var_10], xmm4\nmovsd [rsp+28h+var_20], xmm3\ncall _pow\nmovsd xmm4, [rsp+28h+var_10]\nmovsd xmm3, [rsp+28h+var_20]\npxor xmm1, xmm1\ncvtsi2sd xmm1, ebx; y\nmovsd [rsp+28h+var_28], xmm0\nsubsd xmm4, xmm3\nmovapd xmm0, xmm4; x\ncall _pow\nmovsd xmm2, [rsp+28h+var_18]\nmovapd xmm1, xmm0\nmovsd xmm0, [rsp+28h+var_28]\nadd rsp, 20h\npop rbx\nmulsd xmm0, xmm2\nmulsd xmm0, xmm1\nretn\nloc_1350:\nmov ecx, ebx\nmov edi, esi\ntest ecx, ecx\njg loc_12AE\nloc_135C:\nmovsd xmm4, cs:qword_20E0\nmovapd xmm2, xmm4\njmp short loc_12EA", + "ida_pseudo": "double __fastcall func0(int a1, int a2, double a3)\n{\n int v3; // ebx\n int v4; // ecx\n int v5; // edi\n int v6; // ecx\n int v7; // eax\n double v8; // xmm2_8\n int v9; // edx\n double v10; // xmm1_8\n double v12; // [rsp+0h] [rbp-28h]\n\n v3 = a1 - a2;\n if ( a1 / 2 >= a2 )\n {\n v4 = a2;\n v5 = a1 - a2;\n if ( a2 > 0 )\n goto LABEL_3;\nLABEL_7:\n v8 = 1.0;\n goto LABEL_5;\n }\n v4 = a1 - a2;\n v5 = a2;\n if ( v3 <= 0 )\n goto LABEL_7;\nLABEL_3:\n v6 = v4 + 1;\n v7 = 1;\n v8 = 1.0;\n do\n {\n v9 = v7 + v5;\n v10 = (double)v7++;\n v8 = v8 * (double)v9 / v10;\n }\n while ( v7 != v6 );\nLABEL_5:\n v12 = pow(a3, (double)a2);\n return v12 * v8 * pow(1.0 - a3, (double)v3);\n}", + "ida_strip_asm": "sub_1280:\nendbr64\nmov eax, edi\npush rbx\nmov ebx, edi\nmovapd xmm3, xmm0\nshr eax, 1Fh\nsub ebx, esi\nadd eax, edi\nsar eax, 1\nsub rsp, 20h\ncmp eax, esi\njl loc_1350\nmov ecx, esi\nmov edi, ebx\ntest ecx, ecx\njle loc_135C\nloc_12AE:\nmovsd xmm4, cs:qword_20E0\nadd ecx, 1\nmov eax, 1\nmovapd xmm2, xmm4\nnop word ptr [rax+rax+00h]\nloc_12C8:\nlea edx, [rax+rdi]\npxor xmm1, xmm1\ncvtsi2sd xmm1, edx\nmulsd xmm2, xmm1\npxor xmm1, xmm1\ncvtsi2sd xmm1, eax\nadd eax, 1\ndivsd xmm2, xmm1\ncmp eax, ecx\njnz short loc_12C8\nloc_12EA:\npxor xmm1, xmm1\nmovapd xmm0, xmm3; x\nmovsd [rsp+28h+var_18], xmm2\ncvtsi2sd xmm1, esi; y\nmovsd [rsp+28h+var_10], xmm4\nmovsd [rsp+28h+var_20], xmm3\ncall _pow\nmovsd xmm4, [rsp+28h+var_10]\nmovsd xmm3, [rsp+28h+var_20]\npxor xmm1, xmm1\ncvtsi2sd xmm1, ebx; y\nmovsd [rsp+28h+var_28], xmm0\nsubsd xmm4, xmm3\nmovapd xmm0, xmm4; x\ncall _pow\nmovsd xmm2, [rsp+28h+var_18]\nmovapd xmm1, xmm0\nmovsd xmm0, [rsp+28h+var_28]\nadd rsp, 20h\npop rbx\nmulsd xmm0, xmm2\nmulsd xmm0, xmm1\nretn\nloc_1350:\nmov ecx, ebx\nmov edi, esi\ntest ecx, ecx\njg loc_12AE\nloc_135C:\nmovsd xmm4, cs:qword_20E0\nmovapd xmm2, xmm4\njmp short loc_12EA", + "ida_strip_pseudo": "double __fastcall sub_1280(int a1, int a2, double a3)\n{\n int v3; // ebx\n int v4; // ecx\n int v5; // edi\n int v6; // ecx\n int v7; // eax\n double v8; // xmm2_8\n int v9; // edx\n double v10; // xmm1_8\n double v12; // [rsp+0h] [rbp-28h]\n\n v3 = a1 - a2;\n if ( a1 / 2 >= a2 )\n {\n v4 = a2;\n v5 = a1 - a2;\n if ( a2 > 0 )\n goto LABEL_3;\nLABEL_7:\n v8 = 1.0;\n goto LABEL_5;\n }\n v4 = a1 - a2;\n v5 = a2;\n if ( v3 <= 0 )\n goto LABEL_7;\nLABEL_3:\n v6 = v4 + 1;\n v7 = 1;\n v8 = 1.0;\n do\n {\n v9 = v7 + v5;\n v10 = (double)v7++;\n v8 = v8 * (double)v9 / v10;\n }\n while ( v7 != v6 );\nLABEL_5:\n v12 = pow(a3, (double)a2);\n return v12 * v8 * pow(1.0 - a3, (double)v3);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1280(int a1, int a2, double a3) {\n int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n double v8;\n int v9;\n double v10;\n double v12;\n v3 = a1 - a2;\n if (a1 / 2 >= a2) {\n v4 = a2;\n v5 = a1 - a2;\n if (a2 > 0) goto LABEL_3;\n LABEL_7:\n v8 = 1.0;\n goto LABEL_5;\n }\n v4 = a1 - a2;\n v5 = a2;\n if (v3 <= 0) goto LABEL_7;\nLABEL_3:\n v6 = v4 + 1;\n v7 = 1;\n v8 = 1.0;\n do {\n v9 = v7 + v5;\n v10 = (double)v7++;\n v8 = v8 * (double)v9 / v10;\n } while (v7 != v6);\nLABEL_5:\n v12 = pow(a3, (double)a2);\n return v12 * v8 * pow(1.0 - a3, (double)v3);\n}", + "ida_pseudo_norm": "double func0(int a1, int a2, double a3) {\n int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n double v8;\n int v9;\n double v10;\n double v12;\n v3 = a1 - a2;\n if (a1 / 2 >= a2) {\n v4 = a2;\n v5 = a1 - a2;\n if (a2 > 0) goto LABEL_3;\n LABEL_7:\n v8 = 1.0;\n goto LABEL_5;\n }\n v4 = a1 - a2;\n v5 = a2;\n if (v3 <= 0) goto LABEL_7;\nLABEL_3:\n v6 = v4 + 1;\n v7 = 1;\n v8 = 1.0;\n do {\n v9 = v7 + v5;\n v10 = (double)v7++;\n v8 = v8 * (double)v9 / v10;\n } while (v7 != v6);\nLABEL_5:\n v12 = pow(a3, (double)a2);\n return v12 * v8 * pow(1.0 - a3, (double)v3);\n}" + }, + { + "index": 487, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int tuples[][2], int n) {\n int i, j;\n for (i = 0; i < n; i++) {\n for (j = 0; j < n - i - 1; j++) {\n if (tuples[j][1] > tuples[j + 1][1]) {\n int temp0 = tuples[j][0], temp1 = tuples[j][1];\n tuples[j][0] = tuples[j + 1][0];\n tuples[j][1] = tuples[j + 1][1];\n tuples[j + 1][0] = temp0;\n tuples[j + 1][1] = temp1;\n }\n }\n }\n}", + "test": "int main() {\n\n int t1[3][2] = {{1, 3}, {3, 2}, {2, 1}};\n\n int r1[3][2] = {{2, 1}, {3, 2}, {1, 3}};\n\n func0(t1, 3);\n\n assert(memcmp(t1, r1, sizeof(t1)) == 0);\n\n\n\n int t2[3][2] = {{2, 4}, {3, 3}, {1, 1}};\n\n int r2[3][2] = {{1, 1}, {3, 3}, {2, 4}};\n\n func0(t2, 3);\n\n assert(memcmp(t2, r2, sizeof(t2)) == 0);\n\n\n\n int t3[3][2] = {{3, 9}, {6, 7}, {4, 3}};\n\n int r3[3][2] = {{4, 3}, {6, 7}, {3, 9}};\n\n func0(t3, 3);\n\n assert(memcmp(t3, r3, sizeof(t3)) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x10(%rbp)\njmpq 12d6 \nmovl $0x0,-0xc(%rbp)\njmpq 12c0 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov 0x4(%rax),%edx\nmov -0xc(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,8),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov 0x4(%rax),%eax\ncmp %eax,%edx\njle 12bc \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x8(%rbp)\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov 0x4(%rax),%eax\nmov %eax,-0x4(%rbp)\nmov -0xc(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0xc(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\nmov -0xc(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0xc(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmov 0x4(%rax),%eax\nmov %eax,0x4(%rdx)\nmov -0xc(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0x8(%rbp),%eax\nmov %eax,(%rdx)\nmov -0xc(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0x4(%rbp),%eax\nmov %eax,0x4(%rdx)\naddl $0x1,-0xc(%rbp)\nmov -0x1c(%rbp),%eax\nsub -0x10(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0xc(%rbp)\njl 11b0 \naddl $0x1,-0x10(%rbp)\nmov -0x10(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11a4 \npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_10], 0\njmp loc_12D6\nloc_11A4:\nmov [rbp+var_C], 0\njmp loc_12C0\nloc_11B0:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax+4]\nmov eax, [rbp+var_C]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax+4]\ncmp edx, eax\njle loc_12BC\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_8], eax\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax+4]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_C]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_C]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov eax, [rax+4]\nmov [rdx+4], eax\nmov eax, [rbp+var_C]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_8]\nmov [rdx], eax\nmov eax, [rbp+var_C]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx+4], eax\nloc_12BC:\nadd [rbp+var_C], 1\nloc_12C0:\nmov eax, [rbp+var_1C]\nsub eax, [rbp+var_10]\nsub eax, 1\ncmp [rbp+var_C], eax\njl loc_11B0\nadd [rbp+var_10], 1\nloc_12D6:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_1C]\njl loc_11A4\nnop\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+Ch] [rbp-10h]\n int j; // [rsp+10h] [rbp-Ch]\n int v5; // [rsp+14h] [rbp-8h]\n int v6; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a2 )\n break;\n for ( j = 0; j < (int)(a2 - i - 1); ++j )\n {\n if ( *(_DWORD *)(8LL * j + a1 + 4) > *(_DWORD *)(8 * (j + 1LL) + a1 + 4) )\n {\n v5 = *(_DWORD *)(8LL * j + a1);\n v6 = *(_DWORD *)(8LL * j + a1 + 4);\n *(_DWORD *)(8LL * j + a1) = *(_DWORD *)(8 * (j + 1LL) + a1);\n *(_DWORD *)(8LL * j + a1 + 4) = *(_DWORD *)(8 * (j + 1LL) + a1 + 4);\n *(_DWORD *)(a1 + 8 * (j + 1LL)) = v5;\n *(_DWORD *)(a1 + 8 * (j + 1LL) + 4) = v6;\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_10], 0\njmp loc_12D6\nloc_11A4:\nmov [rbp+var_C], 0\njmp loc_12C0\nloc_11B0:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax+4]\nmov eax, [rbp+var_C]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax+4]\ncmp edx, eax\njle loc_12BC\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_8], eax\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax+4]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_C]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_C]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov eax, [rax+4]\nmov [rdx+4], eax\nmov eax, [rbp+var_C]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_8]\nmov [rdx], eax\nmov eax, [rbp+var_C]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx+4], eax\nloc_12BC:\nadd [rbp+var_C], 1\nloc_12C0:\nmov eax, [rbp+var_1C]\nsub eax, [rbp+var_10]\nsub eax, 1\ncmp [rbp+var_C], eax\njl loc_11B0\nadd [rbp+var_10], 1\nloc_12D6:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_1C]\njl loc_11A4\nnop\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+Ch] [rbp-10h]\n int j; // [rsp+10h] [rbp-Ch]\n int v5; // [rsp+14h] [rbp-8h]\n int v6; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a2 )\n break;\n for ( j = 0; j < (int)(a2 - i - 1); ++j )\n {\n if ( *(_DWORD *)(8LL * j + a1 + 4) > *(_DWORD *)(8 * (j + 1LL) + a1 + 4) )\n {\n v5 = *(_DWORD *)(8LL * j + a1);\n v6 = *(_DWORD *)(8LL * j + a1 + 4);\n *(_DWORD *)(8LL * j + a1) = *(_DWORD *)(8 * (j + 1LL) + a1);\n *(_DWORD *)(8LL * j + a1 + 4) = *(_DWORD *)(8 * (j + 1LL) + a1 + 4);\n *(_DWORD *)(a1 + 8 * (j + 1LL)) = v5;\n *(_DWORD *)(a1 + 8 * (j + 1LL) + 4) = v6;\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2) {\n long long result;\n unsigned int i;\n int j;\n int v5;\n int v6;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a2) break;\n for (j = 0; j < (int)(a2 - i - 1); ++j) {\n if (*(uint32_t *)(8LL * j + a1 + 4) >\n *(uint32_t *)(8 * (j + 1LL) + a1 + 4)) {\n v5 = *(uint32_t *)(8LL * j + a1);\n v6 = *(uint32_t *)(8LL * j + a1 + 4);\n *(uint32_t *)(8LL * j + a1) = *(uint32_t *)(8 * (j + 1LL) + a1);\n *(uint32_t *)(8LL * j + a1 + 4) = *(uint32_t *)(8 * (j + 1LL) + a1 + 4);\n *(uint32_t *)(a1 + 8 * (j + 1LL)) = v5;\n *(uint32_t *)(a1 + 8 * (j + 1LL) + 4) = v6;\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long result;\n unsigned int i;\n int j;\n int v5;\n int v6;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a2) break;\n for (j = 0; j < (int)(a2 - i - 1); ++j) {\n if (*(uint32_t *)(8LL * j + a1 + 4) >\n *(uint32_t *)(8 * (j + 1LL) + a1 + 4)) {\n v5 = *(uint32_t *)(8LL * j + a1);\n v6 = *(uint32_t *)(8LL * j + a1 + 4);\n *(uint32_t *)(8LL * j + a1) = *(uint32_t *)(8 * (j + 1LL) + a1);\n *(uint32_t *)(8LL * j + a1 + 4) = *(uint32_t *)(8 * (j + 1LL) + a1 + 4);\n *(uint32_t *)(a1 + 8 * (j + 1LL)) = v5;\n *(uint32_t *)(a1 + 8 * (j + 1LL) + 4) = v6;\n }\n }\n }\n return result;\n}" + }, + { + "index": 487, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int tuples[][2], int n) {\n int i, j;\n for (i = 0; i < n; i++) {\n for (j = 0; j < n - i - 1; j++) {\n if (tuples[j][1] > tuples[j + 1][1]) {\n int temp0 = tuples[j][0], temp1 = tuples[j][1];\n tuples[j][0] = tuples[j + 1][0];\n tuples[j][1] = tuples[j + 1][1];\n tuples[j + 1][0] = temp0;\n tuples[j + 1][1] = temp1;\n }\n }\n }\n}", + "test": "int main() {\n\n int t1[3][2] = {{1, 3}, {3, 2}, {2, 1}};\n\n int r1[3][2] = {{2, 1}, {3, 2}, {1, 3}};\n\n func0(t1, 3);\n\n assert(memcmp(t1, r1, sizeof(t1)) == 0);\n\n\n\n int t2[3][2] = {{2, 4}, {3, 3}, {1, 1}};\n\n int r2[3][2] = {{1, 1}, {3, 3}, {2, 4}};\n\n func0(t2, 3);\n\n assert(memcmp(t2, r2, sizeof(t2)) == 0);\n\n\n\n int t3[3][2] = {{3, 9}, {6, 7}, {4, 3}};\n\n int r3[3][2] = {{4, 3}, {6, 7}, {3, 9}};\n\n func0(t3, 3);\n\n assert(memcmp(t3, r3, sizeof(t3)) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11ce \nlea -0x1(%rsi),%r10d\nlea 0x8(%rdi),%r11\njmp 11d3 \nadd $0x8,%rax\ncmp %rsi,%rax\nje 11cf \nmov 0x4(%rax),%edx\nmov 0xc(%rax),%ecx\ncmp %ecx,%edx\njle 119b \nmov (%rax),%r8d\nmov 0x8(%rax),%r9d\nmov %r9d,(%rax)\nmov %ecx,0x4(%rax)\nmov %r8d,0x8(%rax)\nmov %edx,0xc(%rax)\njmp 119b \nsub $0x1,%r10d\ncmp $0xffffffff,%r10d\njne 11d3 \nretq\nsub $0x1,%r10d\ntest %r10d,%r10d\njle 11c4 \nmov %rdi,%rax\nlea -0x1(%r10),%edx\nlea (%r11,%rdx,8),%rsi\njmp 11a4 \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short locret_11C5\nlea r11, [rdi+8]\njmp short loc_11C9\nloc_1197:\nadd rax, 8\ncmp rax, r8\njz short loc_11C6\nloc_11A0:\nmov edx, [rax+4]\nmov ecx, [rax+0Ch]\ncmp edx, ecx\njle short loc_1197\nmov r9d, [rax]\nmov r10d, [rax+8]\nmov [rax], r10d\nmov [rax+4], ecx\nmov [rax+8], r9d\nmov [rax+0Ch], edx\njmp short loc_1197\nloc_11C0:\nsub esi, 1\njnz short loc_11C9\nlocret_11C5:\nretn\nloc_11C6:\nsub esi, 1\nloc_11C9:\ncmp esi, 1\njle short loc_11C0\nmov rax, rdi\nlea edx, [rsi-2]\nlea r8, [r11+rdx*8]\njmp short loc_11A0", + "ida_pseudo": "void __fastcall func0(int *a1, int a2)\n{\n int *v2; // rax\n int v3; // edx\n int v4; // ecx\n int v5; // r9d\n\n if ( a2 > 0 )\n {\n do\n {\n while ( a2 > 1 )\n {\n v2 = a1;\n do\n {\n v3 = v2[1];\n v4 = v2[3];\n if ( v3 > v4 )\n {\n v5 = *v2;\n *v2 = v2[2];\n v2[1] = v4;\n v2[2] = v5;\n v2[3] = v3;\n }\n v2 += 2;\n }\n while ( v2 != &a1[2 * (a2 - 2) + 2] );\n --a2;\n }\n --a2;\n }\n while ( a2 );\n }\n}", + "ida_strip_asm": "sub_1189:\nendbr64\ntest esi, esi\njle short locret_11C5\nlea r11, [rdi+8]\njmp short loc_11C9\nloc_1197:\nadd rax, 8\ncmp rax, r8\njz short loc_11C6\nloc_11A0:\nmov edx, [rax+4]\nmov ecx, [rax+0Ch]\ncmp edx, ecx\njle short loc_1197\nmov r9d, [rax]\nmov r10d, [rax+8]\nmov [rax], r10d\nmov [rax+4], ecx\nmov [rax+8], r9d\nmov [rax+0Ch], edx\njmp short loc_1197\nloc_11C0:\nsub esi, 1\njnz short loc_11C9\nlocret_11C5:\nretn\nloc_11C6:\nsub esi, 1\nloc_11C9:\ncmp esi, 1\njle short loc_11C0\nmov rax, rdi\nlea edx, [rsi-2]\nlea r8, [r11+rdx*8]\njmp short loc_11A0", + "ida_strip_pseudo": "void __fastcall sub_1189(int *a1, int a2)\n{\n int *v2; // rax\n int v3; // edx\n int v4; // ecx\n int v5; // r9d\n\n if ( a2 > 0 )\n {\n do\n {\n while ( a2 > 1 )\n {\n v2 = a1;\n do\n {\n v3 = v2[1];\n v4 = v2[3];\n if ( v3 > v4 )\n {\n v5 = *v2;\n *v2 = v2[2];\n v2[1] = v4;\n v2[2] = v5;\n v2[3] = v3;\n }\n v2 += 2;\n }\n while ( v2 != &a1[2 * (a2 - 2) + 2] );\n --a2;\n }\n --a2;\n }\n while ( a2 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1189(int *a1, int a2) {\n int *v2;\n int v3;\n int v4;\n int v5;\n if (a2 > 0) {\n do {\n while (a2 > 1) {\n v2 = a1;\n do {\n v3 = v2[1];\n v4 = v2[3];\n if (v3 > v4) {\n v5 = *v2;\n *v2 = v2[2];\n v2[1] = v4;\n v2[2] = v5;\n v2[3] = v3;\n }\n v2 += 2;\n } while (v2 != &a1[2 * (a2 - 2) + 2]);\n --a2;\n }\n --a2;\n } while (a2);\n }\n}", + "ida_pseudo_norm": "void func0(int *a1, int a2) {\n int *v2;\n int v3;\n int v4;\n int v5;\n if (a2 > 0) {\n do {\n while (a2 > 1) {\n v2 = a1;\n do {\n v3 = v2[1];\n v4 = v2[3];\n if (v3 > v4) {\n v5 = *v2;\n *v2 = v2[2];\n v2[1] = v4;\n v2[2] = v5;\n v2[3] = v3;\n }\n v2 += 2;\n } while (v2 != &a1[2 * (a2 - 2) + 2]);\n --a2;\n }\n --a2;\n } while (a2);\n }\n}" + }, + { + "index": 487, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int tuples[][2], int n) {\n int i, j;\n for (i = 0; i < n; i++) {\n for (j = 0; j < n - i - 1; j++) {\n if (tuples[j][1] > tuples[j + 1][1]) {\n int temp0 = tuples[j][0], temp1 = tuples[j][1];\n tuples[j][0] = tuples[j + 1][0];\n tuples[j][1] = tuples[j + 1][1];\n tuples[j + 1][0] = temp0;\n tuples[j + 1][1] = temp1;\n }\n }\n }\n}", + "test": "int main() {\n\n int t1[3][2] = {{1, 3}, {3, 2}, {2, 1}};\n\n int r1[3][2] = {{2, 1}, {3, 2}, {1, 3}};\n\n func0(t1, 3);\n\n assert(memcmp(t1, r1, sizeof(t1)) == 0);\n\n\n\n int t2[3][2] = {{2, 4}, {3, 3}, {1, 1}};\n\n int r2[3][2] = {{1, 1}, {3, 3}, {2, 4}};\n\n func0(t2, 3);\n\n assert(memcmp(t2, r2, sizeof(t2)) == 0);\n\n\n\n int t3[3][2] = {{3, 9}, {6, 7}, {4, 3}};\n\n int r3[3][2] = {{4, 3}, {6, 7}, {3, 9}};\n\n func0(t3, 3);\n\n assert(memcmp(t3, r3, sizeof(t3)) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 13d7 \nlea -0x1(%rsi),%edx\nlea 0x8(%rdi),%r11\ntest %edx,%edx\nje 13d6 \nnopl 0x0(%rax,%rax,1)\nsub $0x1,%edx\nmov %rdi,%rax\nmov %rdx,%r10\nlea (%r11,%rdx,8),%rsi\nnopl (%rax)\nmov 0x4(%rax),%edx\nmov 0xc(%rax),%ecx\ncmp %ecx,%edx\njle 13c6 \nmov (%rax),%r8d\nmov 0x8(%rax),%r9d\nmov %ecx,0x4(%rax)\nmov %edx,0xc(%rax)\nmov %r9d,(%rax)\nmov %r8d,0x8(%rax)\nadd $0x8,%rax\ncmp %rsi,%rax\njne 13a8 \nmov %r10d,%edx\ntest %edx,%edx\njne 1398 \nretq\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short locret_13C8\nlea r9, [rdi+8]\nloc_136C:\ncmp esi, 1\njle short loc_13C3\nnop dword ptr [rax+00000000h]\nloc_1378:\nlea edx, [rsi-2]\nmov rax, rdi\nlea r8, [r9+rdx*8]\nnop word ptr [rax+rax+00h]\nloc_1388:\nmov ecx, [rax+4]\nmov edx, [rax+0Ch]\ncmp ecx, edx\njle short loc_13B2\nmovd xmm1, dword ptr [rax]\nmovd xmm0, dword ptr [rax+8]\nmovd xmm2, ecx\nmovd xmm3, edx\npunpckldq xmm1, xmm2\npunpckldq xmm0, xmm3\npunpcklqdq xmm0, xmm1\nmovups xmmword ptr [rax], xmm0\nloc_13B2:\nadd rax, 8\ncmp rax, r8\njnz short loc_1388\nsub esi, 1\ncmp esi, 1\njg short loc_1378\nloc_13C3:\nsub esi, 1\njnz short loc_136C\nlocret_13C8:\nretn", + "ida_pseudo": "void __fastcall func0(unsigned int *a1, int a2)\n{\n unsigned int *v2; // rax\n signed int v3; // ecx\n signed int v4; // edx\n\n if ( a2 > 0 )\n {\n do\n {\n for ( ; a2 > 1; --a2 )\n {\n v2 = a1;\n do\n {\n v3 = v2[1];\n v4 = v2[3];\n if ( v3 > v4 )\n *(__m128i *)v2 = _mm_unpacklo_epi64(\n _mm_unpacklo_epi32(_mm_cvtsi32_si128(v2[2]), _mm_cvtsi32_si128(v4)),\n _mm_unpacklo_epi32(_mm_cvtsi32_si128(*v2), _mm_cvtsi32_si128(v3)));\n v2 += 2;\n }\n while ( v2 != &a1[2 * (a2 - 2) + 2] );\n }\n --a2;\n }\n while ( a2 );\n }\n}", + "ida_strip_asm": "sub_1360:\nendbr64\ntest esi, esi\njle short locret_13C8\nlea r9, [rdi+8]\nloc_136C:\ncmp esi, 1\njle short loc_13C3\nnop dword ptr [rax+00000000h]\nloc_1378:\nlea edx, [rsi-2]\nmov rax, rdi\nlea r8, [r9+rdx*8]\nnop word ptr [rax+rax+00h]\nloc_1388:\nmov ecx, [rax+4]\nmov edx, [rax+0Ch]\ncmp ecx, edx\njle short loc_13B2\nmovd xmm1, dword ptr [rax]\nmovd xmm0, dword ptr [rax+8]\nmovd xmm2, ecx\nmovd xmm3, edx\npunpckldq xmm1, xmm2\npunpckldq xmm0, xmm3\npunpcklqdq xmm0, xmm1\nmovups xmmword ptr [rax], xmm0\nloc_13B2:\nadd rax, 8\ncmp rax, r8\njnz short loc_1388\nsub esi, 1\ncmp esi, 1\njg short loc_1378\nloc_13C3:\nsub esi, 1\njnz short loc_136C\nlocret_13C8:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1360(unsigned int *a1, int a2)\n{\n unsigned int *v2; // rax\n signed int v3; // ecx\n signed int v4; // edx\n\n if ( a2 > 0 )\n {\n do\n {\n for ( ; a2 > 1; --a2 )\n {\n v2 = a1;\n do\n {\n v3 = v2[1];\n v4 = v2[3];\n if ( v3 > v4 )\n *(__m128i *)v2 = _mm_unpacklo_epi64(\n _mm_unpacklo_epi32(_mm_cvtsi32_si128(v2[2]), _mm_cvtsi32_si128(v4)),\n _mm_unpacklo_epi32(_mm_cvtsi32_si128(*v2), _mm_cvtsi32_si128(v3)));\n v2 += 2;\n }\n while ( v2 != &a1[2 * (a2 - 2) + 2] );\n }\n --a2;\n }\n while ( a2 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1360(unsigned int *a1, int a2) {\n unsigned int *v2;\n signed int v3;\n signed int v4;\n if (a2 > 0) {\n do {\n for (; a2 > 1; --a2) {\n v2 = a1;\n do {\n v3 = v2[1];\n v4 = v2[3];\n if (v3 > v4)\n *(__m128i *)v2 =\n _mm_unpacklo_epi64(_mm_unpacklo_epi32(_mm_cvtsi32_si128(v2[2]),\n _mm_cvtsi32_si128(v4)),\n _mm_unpacklo_epi32(_mm_cvtsi32_si128(*v2),\n _mm_cvtsi32_si128(v3)));\n v2 += 2;\n } while (v2 != &a1[2 * (a2 - 2) + 2]);\n }\n --a2;\n } while (a2);\n }\n}", + "ida_pseudo_norm": "void func0(unsigned int *a1, int a2) {\n unsigned int *v2;\n signed int v3;\n signed int v4;\n if (a2 > 0) {\n do {\n for (; a2 > 1; --a2) {\n v2 = a1;\n do {\n v3 = v2[1];\n v4 = v2[3];\n if (v3 > v4)\n *(__m128i *)v2 =\n _mm_unpacklo_epi64(_mm_unpacklo_epi32(_mm_cvtsi32_si128(v2[2]),\n _mm_cvtsi32_si128(v4)),\n _mm_unpacklo_epi32(_mm_cvtsi32_si128(*v2),\n _mm_cvtsi32_si128(v3)));\n v2 += 2;\n } while (v2 != &a1[2 * (a2 - 2) + 2]);\n }\n --a2;\n } while (a2);\n }\n}" + }, + { + "index": 487, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int tuples[][2], int n) {\n int i, j;\n for (i = 0; i < n; i++) {\n for (j = 0; j < n - i - 1; j++) {\n if (tuples[j][1] > tuples[j + 1][1]) {\n int temp0 = tuples[j][0], temp1 = tuples[j][1];\n tuples[j][0] = tuples[j + 1][0];\n tuples[j][1] = tuples[j + 1][1];\n tuples[j + 1][0] = temp0;\n tuples[j + 1][1] = temp1;\n }\n }\n }\n}", + "test": "int main() {\n\n int t1[3][2] = {{1, 3}, {3, 2}, {2, 1}};\n\n int r1[3][2] = {{2, 1}, {3, 2}, {1, 3}};\n\n func0(t1, 3);\n\n assert(memcmp(t1, r1, sizeof(t1)) == 0);\n\n\n\n int t2[3][2] = {{2, 4}, {3, 3}, {1, 1}};\n\n int r2[3][2] = {{1, 1}, {3, 3}, {2, 4}};\n\n func0(t2, 3);\n\n assert(memcmp(t2, r2, sizeof(t2)) == 0);\n\n\n\n int t3[3][2] = {{3, 9}, {6, 7}, {4, 3}};\n\n int r3[3][2] = {{4, 3}, {6, 7}, {3, 9}};\n\n func0(t3, 3);\n\n assert(memcmp(t3, r3, sizeof(t3)) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 13c7 \nlea -0x1(%rsi),%edx\nlea 0x8(%rdi),%r11\ntest %edx,%edx\nje 13c6 \nnopl 0x0(%rax,%rax,1)\nsub $0x1,%edx\nmov %rdi,%rax\nmov %rdx,%r10\nlea (%r11,%rdx,8),%rsi\nnopl (%rax)\nmov 0x4(%rax),%edx\nmov 0xc(%rax),%ecx\ncmp %ecx,%edx\njle 13b6 \nmov (%rax),%r8d\nmov 0x8(%rax),%r9d\nmov %ecx,0x4(%rax)\nmov %edx,0xc(%rax)\nmov %r9d,(%rax)\nmov %r8d,0x8(%rax)\nadd $0x8,%rax\ncmp %rsi,%rax\njne 1398 \nmov %r10d,%edx\ntest %edx,%edx\njne 1388 \nretq\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short locret_13C8\nlea r9, [rdi+8]\nloc_136C:\ncmp esi, 1\njle short loc_13C3\nnop dword ptr [rax+00000000h]\nloc_1378:\nlea edx, [rsi-2]\nmov rax, rdi\nlea r8, [r9+rdx*8]\nnop word ptr [rax+rax+00h]\nloc_1388:\nmov ecx, [rax+4]\nmov edx, [rax+0Ch]\ncmp ecx, edx\njle short loc_13B2\nmovd xmm1, dword ptr [rax]\nmovd xmm0, dword ptr [rax+8]\nmovd xmm2, ecx\nmovd xmm3, edx\npunpckldq xmm1, xmm2\npunpckldq xmm0, xmm3\npunpcklqdq xmm0, xmm1\nmovups xmmword ptr [rax], xmm0\nloc_13B2:\nadd rax, 8\ncmp rax, r8\njnz short loc_1388\nsub esi, 1\ncmp esi, 1\njg short loc_1378\nloc_13C3:\nsub esi, 1\njnz short loc_136C\nlocret_13C8:\nretn", + "ida_pseudo": "void __fastcall func0(unsigned int *a1, int a2)\n{\n unsigned int *v2; // rax\n signed int v3; // ecx\n signed int v4; // edx\n\n if ( a2 > 0 )\n {\n do\n {\n for ( ; a2 > 1; --a2 )\n {\n v2 = a1;\n do\n {\n v3 = v2[1];\n v4 = v2[3];\n if ( v3 > v4 )\n *(__m128i *)v2 = _mm_unpacklo_epi64(\n _mm_unpacklo_epi32(_mm_cvtsi32_si128(v2[2]), _mm_cvtsi32_si128(v4)),\n _mm_unpacklo_epi32(_mm_cvtsi32_si128(*v2), _mm_cvtsi32_si128(v3)));\n v2 += 2;\n }\n while ( v2 != &a1[2 * (a2 - 2) + 2] );\n }\n --a2;\n }\n while ( a2 );\n }\n}", + "ida_strip_asm": "sub_1360:\nendbr64\ntest esi, esi\njle short locret_13C8\nlea r9, [rdi+8]\nloc_136C:\ncmp esi, 1\njle short loc_13C3\nnop dword ptr [rax+00000000h]\nloc_1378:\nlea edx, [rsi-2]\nmov rax, rdi\nlea r8, [r9+rdx*8]\nnop word ptr [rax+rax+00h]\nloc_1388:\nmov ecx, [rax+4]\nmov edx, [rax+0Ch]\ncmp ecx, edx\njle short loc_13B2\nmovd xmm1, dword ptr [rax]\nmovd xmm0, dword ptr [rax+8]\nmovd xmm2, ecx\nmovd xmm3, edx\npunpckldq xmm1, xmm2\npunpckldq xmm0, xmm3\npunpcklqdq xmm0, xmm1\nmovups xmmword ptr [rax], xmm0\nloc_13B2:\nadd rax, 8\ncmp rax, r8\njnz short loc_1388\nsub esi, 1\ncmp esi, 1\njg short loc_1378\nloc_13C3:\nsub esi, 1\njnz short loc_136C\nlocret_13C8:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1360(unsigned int *a1, int a2)\n{\n unsigned int *v2; // rax\n signed int v3; // ecx\n signed int v4; // edx\n\n if ( a2 > 0 )\n {\n do\n {\n for ( ; a2 > 1; --a2 )\n {\n v2 = a1;\n do\n {\n v3 = v2[1];\n v4 = v2[3];\n if ( v3 > v4 )\n *(__m128i *)v2 = _mm_unpacklo_epi64(\n _mm_unpacklo_epi32(_mm_cvtsi32_si128(v2[2]), _mm_cvtsi32_si128(v4)),\n _mm_unpacklo_epi32(_mm_cvtsi32_si128(*v2), _mm_cvtsi32_si128(v3)));\n v2 += 2;\n }\n while ( v2 != &a1[2 * (a2 - 2) + 2] );\n }\n --a2;\n }\n while ( a2 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1360(unsigned int *a1, int a2) {\n unsigned int *v2;\n signed int v3;\n signed int v4;\n if (a2 > 0) {\n do {\n for (; a2 > 1; --a2) {\n v2 = a1;\n do {\n v3 = v2[1];\n v4 = v2[3];\n if (v3 > v4)\n *(__m128i *)v2 =\n _mm_unpacklo_epi64(_mm_unpacklo_epi32(_mm_cvtsi32_si128(v2[2]),\n _mm_cvtsi32_si128(v4)),\n _mm_unpacklo_epi32(_mm_cvtsi32_si128(*v2),\n _mm_cvtsi32_si128(v3)));\n v2 += 2;\n } while (v2 != &a1[2 * (a2 - 2) + 2]);\n }\n --a2;\n } while (a2);\n }\n}", + "ida_pseudo_norm": "void func0(unsigned int *a1, int a2) {\n unsigned int *v2;\n signed int v3;\n signed int v4;\n if (a2 > 0) {\n do {\n for (; a2 > 1; --a2) {\n v2 = a1;\n do {\n v3 = v2[1];\n v4 = v2[3];\n if (v3 > v4)\n *(__m128i *)v2 =\n _mm_unpacklo_epi64(_mm_unpacklo_epi32(_mm_cvtsi32_si128(v2[2]),\n _mm_cvtsi32_si128(v4)),\n _mm_unpacklo_epi32(_mm_cvtsi32_si128(*v2),\n _mm_cvtsi32_si128(v3)));\n v2 += 2;\n } while (v2 != &a1[2 * (a2 - 2) + 2]);\n }\n --a2;\n } while (a2);\n }\n}" + }, + { + "index": 488, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "double func0(double a) {\n double area = (sqrt(5 * (5 + 2 * sqrt(5))) * pow(a, 2)) / 4.0;\n return area;\n}", + "test": "int main() {\n\n assert(func0(5) == 43.01193501472417);\n\n assert(func0(10) == 172.0477400588967);\n\n assert(func0(15) == 387.10741513251753);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmovsd %xmm0,-0x18(%rbp)\nmovsd 0xf2e(%rip),%xmm0\nmov -0x18(%rbp),%rax\nmovapd %xmm0,%xmm1\nmovq %rax,%xmm0\ncallq 1060 \nmovsd 0xf1c(%rip),%xmm1\nmulsd %xmm1,%xmm0\nmovsd 0xf18(%rip),%xmm1\ndivsd %xmm1,%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmovsd -0x8(%rbp),%xmm0\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmovsd [rbp+x], xmm0\nmovsd xmm0, cs:y\nmov rax, [rbp+x]\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\nmovsd xmm1, cs:qword_2098\nmulsd xmm0, xmm1\nmovsd xmm1, cs:qword_20A0\ndivsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "double __fastcall func0(double a1)\n{\n return pow(a1, 2.0) * 6.881909602355868 / 4.0;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmovsd [rbp+x], xmm0\nmovsd xmm0, cs:y\nmov rax, [rbp+x]\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\nmovsd xmm1, cs:qword_2098\nmulsd xmm0, xmm1\nmovsd xmm1, cs:qword_20A0\ndivsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "double __fastcall sub_1169(double a1)\n{\n return pow(a1, 2.0) * 6.881909602355868 / 4.0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1169(double a1) { return pow(a1, 2.0) * 6.881909602355868 / 4.0; }", + "ida_pseudo_norm": "double func0(double a1) { return pow(a1, 2.0) * 6.881909602355868 / 4.0; }" + }, + { + "index": 489, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int n, int arr[]) {\n int mn = arr[0];\n int freq = 1;\n for (int i = 1; i < n; i++) {\n if (arr[i] > mn) {\n mn = arr[i];\n freq = 1;\n } else if (arr[i] == mn) {\n freq += 1;\n }\n }\n return freq;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4, 4};\n\n int arr2[] = {5, 6, 5};\n\n int arr3[] = {2, 7, 7, 7};\n\n\n\n assert(func0(5, arr1) == 2);\n\n assert(func0(3, arr2) == 1);\n\n assert(func0(4, arr3) == 3);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %rsi,-0x20(%rbp)\nmov -0x20(%rbp),%rax\nmov (%rax),%eax\nmov %eax,-0xc(%rbp)\nmovl $0x1,-0x8(%rbp)\nmovl $0x1,-0x4(%rbp)\njmp 11f1 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0xc(%rbp)\njge 11ce \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0xc(%rbp)\nmovl $0x1,-0x8(%rbp)\njmp 11ed \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0xc(%rbp)\njne 11ed \naddl $0x1,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x14(%rbp),%eax\njl 1191 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_20], rsi\nmov rax, [rbp+var_20]\nmov eax, [rax]\nmov [rbp+var_C], eax\nmov [rbp+var_8], 1\nmov [rbp+var_4], 1\njmp short loc_11F1\nloc_1191:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_C], eax\njge short loc_11CE\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nmov [rbp+var_8], 1\njmp short loc_11ED\nloc_11CE:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_C], eax\njnz short loc_11ED\nadd [rbp+var_8], 1\nloc_11ED:\nadd [rbp+var_4], 1\nloc_11F1:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_14]\njl short loc_1191\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int *a2)\n{\n int v3; // [rsp+14h] [rbp-Ch]\n unsigned int v4; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v3 = *a2;\n v4 = 1;\n for ( i = 1; i < a1; ++i )\n {\n if ( v3 >= a2[i] )\n {\n if ( v3 == a2[i] )\n ++v4;\n }\n else\n {\n v3 = a2[i];\n v4 = 1;\n }\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_20], rsi\nmov rax, [rbp+var_20]\nmov eax, [rax]\nmov [rbp+var_C], eax\nmov [rbp+var_8], 1\nmov [rbp+var_4], 1\njmp short loc_11F1\nloc_1191:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_C], eax\njge short loc_11CE\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nmov [rbp+var_8], 1\njmp short loc_11ED\nloc_11CE:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_C], eax\njnz short loc_11ED\nadd [rbp+var_8], 1\nloc_11ED:\nadd [rbp+var_4], 1\nloc_11F1:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_14]\njl short loc_1191\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1, int *a2)\n{\n int v3; // [rsp+14h] [rbp-Ch]\n unsigned int v4; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v3 = *a2;\n v4 = 1;\n for ( i = 1; i < a1; ++i )\n {\n if ( v3 >= a2[i] )\n {\n if ( v3 == a2[i] )\n ++v4;\n }\n else\n {\n v3 = a2[i];\n v4 = 1;\n }\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1, int *a2) {\n int v3;\n unsigned int v4;\n int i;\n v3 = *a2;\n v4 = 1;\n for (i = 1; i < a1; ++i) {\n if (v3 >= a2[i]) {\n if (v3 == a2[i]) ++v4;\n } else {\n v3 = a2[i];\n v4 = 1;\n }\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(int a1, int *a2) {\n int v3;\n unsigned int v4;\n int i;\n v3 = *a2;\n v4 = 1;\n for (i = 1; i < a1; ++i) {\n if (v3 >= a2[i]) {\n if (v3 == a2[i]) ++v4;\n } else {\n v3 = a2[i];\n v4 = 1;\n }\n }\n return v4;\n}" + }, + { + "index": 489, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int n, int arr[]) {\n int mn = arr[0];\n int freq = 1;\n for (int i = 1; i < n; i++) {\n if (arr[i] > mn) {\n mn = arr[i];\n freq = 1;\n } else if (arr[i] == mn) {\n freq += 1;\n }\n }\n return freq;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4, 4};\n\n int arr2[] = {5, 6, 5};\n\n int arr3[] = {2, 7, 7, 7};\n\n\n\n assert(func0(5, arr1) == 2);\n\n assert(func0(3, arr2) == 1);\n\n assert(func0(4, arr3) == 3);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov (%rsi),%ecx\ncmp $0x1,%edi\njle 11a7 \nlea 0x4(%rsi),%rax\nlea -0x2(%rdi),%edx\nlea 0x8(%rsi,%rdx,4),%rdi\nmov $0x1,%esi\njmp 1197 \nmov %edx,%ecx\nmov $0x1,%esi\nadd $0x4,%rax\ncmp %rdi,%rax\nje 11ac \nmov (%rax),%edx\ncmp %ecx,%edx\njg 1187 \nsete %dl\nmovzbl %dl,%edx\nadd %edx,%esi\njmp 118e \nmov $0x1,%esi\nmov %esi,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov ecx, [rsi]\ncmp edi, 1\njle short loc_11A7\nlea rax, [rsi+4]\nlea edx, [rdi-2]\nlea rdi, [rsi+rdx*4+8]\nmov esi, 1\njmp short loc_1197\nloc_1187:\nmov ecx, edx\nmov esi, 1\nloc_118E:\nadd rax, 4\ncmp rax, rdi\njz short loc_11AC\nloc_1197:\nmov edx, [rax]\ncmp edx, ecx\njg short loc_1187\nsetz dl\nmovzx edx, dl\nadd esi, edx\njmp short loc_118E\nloc_11A7:\nmov esi, 1\nloc_11AC:\nmov eax, esi\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int *a2)\n{\n int v2; // ecx\n int *v3; // rax\n __int64 v4; // rdi\n unsigned int v5; // esi\n\n v2 = *a2;\n if ( a1 <= 1 )\n {\n return 1;\n }\n else\n {\n v3 = a2 + 1;\n v4 = (__int64)&a2[a1 - 2 + 2];\n v5 = 1;\n do\n {\n if ( *v3 > v2 )\n {\n v2 = *v3;\n v5 = 1;\n }\n else\n {\n v5 += *v3 == v2;\n }\n ++v3;\n }\n while ( v3 != (int *)v4 );\n }\n return v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov ecx, [rsi]\ncmp edi, 1\njle short loc_11A7\nlea rax, [rsi+4]\nlea edx, [rdi-2]\nlea rdi, [rsi+rdx*4+8]\nmov esi, 1\njmp short loc_1197\nloc_1187:\nmov ecx, edx\nmov esi, 1\nloc_118E:\nadd rax, 4\ncmp rax, rdi\njz short loc_11AC\nloc_1197:\nmov edx, [rax]\ncmp edx, ecx\njg short loc_1187\nsetz dl\nmovzx edx, dl\nadd esi, edx\njmp short loc_118E\nloc_11A7:\nmov esi, 1\nloc_11AC:\nmov eax, esi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1, int *a2)\n{\n int v2; // ecx\n int *v3; // rax\n __int64 v4; // rdi\n unsigned int v5; // esi\n\n v2 = *a2;\n if ( a1 <= 1 )\n {\n return 1;\n }\n else\n {\n v3 = a2 + 1;\n v4 = (__int64)&a2[a1 - 2 + 2];\n v5 = 1;\n do\n {\n if ( *v3 > v2 )\n {\n v2 = *v3;\n v5 = 1;\n }\n else\n {\n v5 += *v3 == v2;\n }\n ++v3;\n }\n while ( v3 != (int *)v4 );\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1, int *a2) {\n int v2;\n int *v3;\n long long v4;\n unsigned int v5;\n v2 = *a2;\n if (a1 <= 1) {\n return 1;\n } else {\n v3 = a2 + 1;\n v4 = (long long)&a2[a1 - 2 + 2];\n v5 = 1;\n do {\n if (*v3 > v2) {\n v2 = *v3;\n v5 = 1;\n } else {\n v5 += *v3 == v2;\n }\n ++v3;\n } while (v3 != (int *)v4);\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(int a1, int *a2) {\n int v2;\n int *v3;\n long long v4;\n unsigned int v5;\n v2 = *a2;\n if (a1 <= 1) {\n return 1;\n } else {\n v3 = a2 + 1;\n v4 = (long long)&a2[a1 - 2 + 2];\n v5 = 1;\n do {\n if (*v3 > v2) {\n v2 = *v3;\n v5 = 1;\n } else {\n v5 += *v3 == v2;\n }\n ++v3;\n } while (v3 != (int *)v4);\n }\n return v5;\n}" + }, + { + "index": 489, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int n, int arr[]) {\n int mn = arr[0];\n int freq = 1;\n for (int i = 1; i < n; i++) {\n if (arr[i] > mn) {\n mn = arr[i];\n freq = 1;\n } else if (arr[i] == mn) {\n freq += 1;\n }\n }\n return freq;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4, 4};\n\n int arr2[] = {5, 6, 5};\n\n int arr3[] = {2, 7, 7, 7};\n\n\n\n assert(func0(5, arr1) == 2);\n\n assert(func0(3, arr2) == 1);\n\n assert(func0(4, arr3) == 3);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov (%rsi),%ecx\ncmp $0x1,%edi\njle 1280 \nlea -0x2(%rdi),%edx\nlea 0x4(%rsi),%rax\nmov $0x1,%r8d\nlea 0x8(%rsi,%rdx,4),%rsi\njmp 1262 \nsete %dl\nadd $0x4,%rax\nmovzbl %dl,%edx\nadd %edx,%r8d\ncmp %rsi,%rax\nje 1279 \nmov (%rax),%edx\ncmp %ecx,%edx\njle 1250 \nadd $0x4,%rax\nmov %edx,%ecx\nmov $0x1,%r8d\ncmp %rsi,%rax\njne 1262 \nmov %r8d,%eax\nretq\nnopl (%rax)\nmov $0x1,%r8d\nmov %r8d,%eax\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmov r8d, [rsi]\ncmp edi, 1\njle short loc_12C0\nlea edx, [rdi-2]\nlea rax, [rsi+4]\nmov ecx, 1\nlea rsi, [rsi+rdx*4+8]\njmp short loc_12A1\nloc_1290:\nsetz dl\nadd rax, 4\nmovzx edx, dl\nadd ecx, edx\ncmp rsi, rax\njz short loc_12B9\nloc_12A1:\nmov edx, [rax]\ncmp r8d, edx\njge short loc_1290\nadd rax, 4\nmov r8d, edx\nmov ecx, 1\ncmp rsi, rax\njnz short loc_12A1\nloc_12B9:\nmov eax, ecx\nretn\nloc_12C0:\nmov ecx, 1\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int *a2)\n{\n int v2; // r8d\n int *v3; // rax\n unsigned int v4; // ecx\n __int64 v5; // rsi\n int v6; // edx\n bool v7; // zf\n\n v2 = *a2;\n if ( a1 <= 1 )\n return 1LL;\n v3 = a2 + 1;\n v4 = 1;\n v5 = (__int64)&a2[a1 - 2 + 2];\n do\n {\n while ( 1 )\n {\n v6 = *v3;\n v7 = v2 == *v3;\n if ( v2 < *v3 )\n break;\n ++v3;\n v4 += v7;\n if ( (int *)v5 == v3 )\n return v4;\n }\n ++v3;\n v2 = v6;\n v4 = 1;\n }\n while ( (int *)v5 != v3 );\n return v4;\n}", + "ida_strip_asm": "sub_1270:\nendbr64\nmov r8d, [rsi]\ncmp edi, 1\njle short loc_12C0\nlea edx, [rdi-2]\nlea rax, [rsi+4]\nmov ecx, 1\nlea rsi, [rsi+rdx*4+8]\njmp short loc_12A1\nloc_1290:\nsetz dl\nadd rax, 4\nmovzx edx, dl\nadd ecx, edx\ncmp rsi, rax\njz short loc_12B9\nloc_12A1:\nmov edx, [rax]\ncmp r8d, edx\njge short loc_1290\nadd rax, 4\nmov r8d, edx\nmov ecx, 1\ncmp rsi, rax\njnz short loc_12A1\nloc_12B9:\nmov eax, ecx\nretn\nloc_12C0:\nmov ecx, 1\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1270(int a1, int *a2)\n{\n int v2; // r8d\n int *v3; // rax\n unsigned int v4; // ecx\n __int64 v5; // rsi\n int v6; // edx\n bool v7; // zf\n\n v2 = *a2;\n if ( a1 <= 1 )\n return 1LL;\n v3 = a2 + 1;\n v4 = 1;\n v5 = (__int64)&a2[a1 - 2 + 2];\n do\n {\n while ( 1 )\n {\n v6 = *v3;\n v7 = v2 == *v3;\n if ( v2 < *v3 )\n break;\n ++v3;\n v4 += v7;\n if ( (int *)v5 == v3 )\n return v4;\n }\n ++v3;\n v2 = v6;\n v4 = 1;\n }\n while ( (int *)v5 != v3 );\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1270(int a1, int *a2) {\n int v2;\n int *v3;\n unsigned int v4;\n long long v5;\n int v6;\n bool v7;\n v2 = *a2;\n if (a1 <= 1) return 1LL;\n v3 = a2 + 1;\n v4 = 1;\n v5 = (long long)&a2[a1 - 2 + 2];\n do {\n while (1) {\n v6 = *v3;\n v7 = v2 == *v3;\n if (v2 < *v3) break;\n ++v3;\n v4 += v7;\n if ((int *)v5 == v3) return v4;\n }\n ++v3;\n v2 = v6;\n v4 = 1;\n } while ((int *)v5 != v3);\n return v4;\n}", + "ida_pseudo_norm": "long long func0(int a1, int *a2) {\n int v2;\n int *v3;\n unsigned int v4;\n long long v5;\n int v6;\n bool v7;\n v2 = *a2;\n if (a1 <= 1) return 1LL;\n v3 = a2 + 1;\n v4 = 1;\n v5 = (long long)&a2[a1 - 2 + 2];\n do {\n while (1) {\n v6 = *v3;\n v7 = v2 == *v3;\n if (v2 < *v3) break;\n ++v3;\n v4 += v7;\n if ((int *)v5 == v3) return v4;\n }\n ++v3;\n v2 = v6;\n v4 = 1;\n } while ((int *)v5 != v3);\n return v4;\n}" + }, + { + "index": 490, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct Pair {\n\n int first;\n\n int second;\n\n} Pair;\n\n\n\nint pair_comparator(const void *v1, const void *v2) {\n\n const Pair *p1 = (const Pair *)v1;\n\n const Pair *p2 = (const Pair *)v2;\n\n if (p1->first != p2->first)\n\n return p1->first - p2->first;\n\n return p1->second - p2->second;\n\n}\n\n\n\n", + "func": "Pair *func0(Pair test_list[], size_t size, size_t *result_size) {\n Pair *res = malloc(size * sizeof(Pair));\n if (!res) return NULL;\n int res_count = 0;\n for (int i = 0; i < size; i++) {\n for (int j = 0; j < size; j++) {\n if (test_list[i].first == test_list[j].second &&\n test_list[i].second == test_list[j].first) {\n if (test_list[i].first < test_list[i].second) {\n res[res_count++] = test_list[i];\n }\n }\n }\n }\n *result_size = res_count;\n return res;\n}", + "test": "int main() {\n\n Pair test1[] = {{6, 7}, {2, 3}, {7, 6}, {9, 8}, {10, 2}, {8, 9}};\n\n Pair result1_exp[] = {{6, 7}, {8, 9}};\n\n size_t res1_size;\n\n Pair *result1 = func0(test1, 6, &res1_size);\n\n qsort(result1, res1_size, sizeof(Pair), pair_comparator);\n\n assert(res1_size == 2 && memcmp(result1, result1_exp, 2 * sizeof(Pair)) == 0);\n\n free(result1);\n\n\n\n Pair test2[] = {{7, 8}, {3, 4}, {8, 7}, {10, 9}, {11, 3}, {9, 10}};\n\n Pair result2_exp[] = {{7, 8}, {9, 10}};\n\n size_t res2_size;\n\n Pair *result2 = func0(test2, 6, &res2_size);\n\n qsort(result2, res2_size, sizeof(Pair), pair_comparator);\n\n assert(res2_size == 2 && memcmp(result2, result2_exp, 2 * sizeof(Pair)) == 0);\n\n free(result2);\n\n\n\n Pair test3[] = {{8, 9}, {4, 5}, {9, 8}, {11, 10}, {12, 4}, {10, 11}};\n\n Pair result3_exp[] = {{8, 9}, {10, 11}};\n\n size_t res3_size;\n\n Pair *result3 = func0(test3, 6, &res3_size);\n\n qsort(result3, res3_size, sizeof(Pair), pair_comparator);\n\n assert(res3_size == 2 && memcmp(result3, result3_exp, 2 * sizeof(Pair)) == 0);\n\n free(result3);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x40,%rsp\nmov %rdi,-0x28(%rbp)\nmov %rsi,-0x30(%rbp)\nmov %rdx,-0x38(%rbp)\nmov -0x30(%rbp),%rax\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 10f0 \nmov %rax,-0x8(%rbp)\ncmpq $0x0,-0x8(%rbp)\njne 127c \nmov $0x0,%eax\njmpq 139e \nmovl $0x0,-0x14(%rbp)\nmovl $0x0,-0x10(%rbp)\njmpq 137e \nmovl $0x0,-0xc(%rbp)\njmpq 136b \nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov 0x4(%rax),%eax\ncmp %eax,%edx\njne 1367 \nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov 0x4(%rax),%edx\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 1367 \nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov 0x4(%rax),%eax\ncmp %eax,%edx\njge 1367 \nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x28(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x14(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x14(%rbp)\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%rax\nmov %rax,(%rdx)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncltq\ncmp %rax,-0x30(%rbp)\nja 129b \naddl $0x1,-0x10(%rbp)\nmov -0x10(%rbp),%eax\ncltq\ncmp %rax,-0x30(%rbp)\nja 128f \nmov -0x14(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x38(%rbp),%rax\nmov %rdx,(%rax)\nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_30], rsi\nmov [rbp+var_38], rdx\nmov rax, [rbp+var_30]\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\ncmp [rbp+var_8], 0\njnz short loc_127C\nmov eax, 0\njmp locret_139E\nloc_127C:\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\njmp loc_137E\nloc_128F:\nmov [rbp+var_C], 0\njmp loc_136B\nloc_129B:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax+4]\ncmp edx, eax\njnz loc_1367\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax+4]\nmov eax, [rbp+var_C]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_1367\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax+4]\ncmp edx, eax\njge short loc_1367\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_14]\nlea edx, [rax+1]\nmov [rbp+var_14], edx\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov rax, [rcx]\nmov [rdx], rax\nloc_1367:\nadd [rbp+var_C], 1\nloc_136B:\nmov eax, [rbp+var_C]\ncdqe\ncmp rax, [rbp+var_30]\njb loc_129B\nadd [rbp+var_10], 1\nloc_137E:\nmov eax, [rbp+var_10]\ncdqe\ncmp rax, [rbp+var_30]\njb loc_128F\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+var_38]\nmov [rax], rdx\nmov rax, [rbp+var_8]\nlocret_139E:\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, unsigned __int64 a2, _QWORD *a3)\n{\n int v4; // eax\n int v6; // [rsp+2Ch] [rbp-14h]\n int i; // [rsp+30h] [rbp-10h]\n int j; // [rsp+34h] [rbp-Ch]\n _QWORD *v9; // [rsp+38h] [rbp-8h]\n\n v9 = malloc(8 * a2);\n if ( !v9 )\n return 0LL;\n v6 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = 0; j < a2; ++j )\n {\n if ( *(_DWORD *)(8LL * i + a1) == *(_DWORD *)(8LL * j + a1 + 4)\n && *(_DWORD *)(8LL * i + a1 + 4) == *(_DWORD *)(8LL * j + a1)\n && *(_DWORD *)(8LL * i + a1) < *(_DWORD *)(8LL * i + a1 + 4) )\n {\n v4 = v6++;\n v9[v4] = *(_QWORD *)(8LL * i + a1);\n }\n }\n }\n *a3 = v6;\n return v9;\n}", + "ida_strip_asm": "sub_123F:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_30], rsi\nmov [rbp+var_38], rdx\nmov rax, [rbp+var_30]\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\ncmp [rbp+var_8], 0\njnz short loc_127C\nmov eax, 0\njmp locret_139E\nloc_127C:\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\njmp loc_137E\nloc_128F:\nmov [rbp+var_C], 0\njmp loc_136B\nloc_129B:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax+4]\ncmp edx, eax\njnz loc_1367\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax+4]\nmov eax, [rbp+var_C]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_1367\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax+4]\ncmp edx, eax\njge short loc_1367\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_14]\nlea edx, [rax+1]\nmov [rbp+var_14], edx\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov rax, [rcx]\nmov [rdx], rax\nloc_1367:\nadd [rbp+var_C], 1\nloc_136B:\nmov eax, [rbp+var_C]\ncdqe\ncmp rax, [rbp+var_30]\njb loc_129B\nadd [rbp+var_10], 1\nloc_137E:\nmov eax, [rbp+var_10]\ncdqe\ncmp rax, [rbp+var_30]\njb loc_128F\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+var_38]\nmov [rax], rdx\nmov rax, [rbp+var_8]\nlocret_139E:\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_123F(__int64 a1, unsigned __int64 a2, _QWORD *a3)\n{\n int v4; // eax\n int v6; // [rsp+2Ch] [rbp-14h]\n int i; // [rsp+30h] [rbp-10h]\n int j; // [rsp+34h] [rbp-Ch]\n _QWORD *v9; // [rsp+38h] [rbp-8h]\n\n v9 = malloc(8 * a2);\n if ( !v9 )\n return 0LL;\n v6 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = 0; j < a2; ++j )\n {\n if ( *(_DWORD *)(8LL * i + a1) == *(_DWORD *)(8LL * j + a1 + 4)\n && *(_DWORD *)(8LL * i + a1 + 4) == *(_DWORD *)(8LL * j + a1)\n && *(_DWORD *)(8LL * i + a1) < *(_DWORD *)(8LL * i + a1 + 4) )\n {\n v4 = v6++;\n v9[v4] = *(_QWORD *)(8LL * i + a1);\n }\n }\n }\n *a3 = v6;\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_123F(long long a1, unsigned long long a2, uint64_t *a3) {\n int v4;\n int v6;\n int i;\n int j;\n uint64_t *v9;\n v9 = malloc(8 * a2);\n if (!v9) return 0LL;\n v6 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = 0; j < a2; ++j) {\n if (*(uint32_t *)(8LL * i + a1) == *(uint32_t *)(8LL * j + a1 + 4) &&\n *(uint32_t *)(8LL * i + a1 + 4) == *(uint32_t *)(8LL * j + a1) &&\n *(uint32_t *)(8LL * i + a1) < *(uint32_t *)(8LL * i + a1 + 4)) {\n v4 = v6++;\n v9[v4] = *(uint64_t *)(8LL * i + a1);\n }\n }\n }\n *a3 = v6;\n return v9;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, unsigned long long a2, uint64_t *a3) {\n int v4;\n int v6;\n int i;\n int j;\n uint64_t *v9;\n v9 = malloc(8 * a2);\n if (!v9) return 0LL;\n v6 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = 0; j < a2; ++j) {\n if (*(uint32_t *)(8LL * i + a1) == *(uint32_t *)(8LL * j + a1 + 4) &&\n *(uint32_t *)(8LL * i + a1 + 4) == *(uint32_t *)(8LL * j + a1) &&\n *(uint32_t *)(8LL * i + a1) < *(uint32_t *)(8LL * i + a1 + 4)) {\n v4 = v6++;\n v9[v4] = *(uint64_t *)(8LL * i + a1);\n }\n }\n }\n *a3 = v6;\n return v9;\n}" + }, + { + "index": 490, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct Pair {\n\n int first;\n\n int second;\n\n} Pair;\n\n\n\nint pair_comparator(const void *v1, const void *v2) {\n\n const Pair *p1 = (const Pair *)v1;\n\n const Pair *p2 = (const Pair *)v2;\n\n if (p1->first != p2->first)\n\n return p1->first - p2->first;\n\n return p1->second - p2->second;\n\n}\n\n\n\n", + "func": "Pair *func0(Pair test_list[], size_t size, size_t *result_size) {\n Pair *res = malloc(size * sizeof(Pair));\n if (!res) return NULL;\n int res_count = 0;\n for (int i = 0; i < size; i++) {\n for (int j = 0; j < size; j++) {\n if (test_list[i].first == test_list[j].second &&\n test_list[i].second == test_list[j].first) {\n if (test_list[i].first < test_list[i].second) {\n res[res_count++] = test_list[i];\n }\n }\n }\n }\n *result_size = res_count;\n return res;\n}", + "test": "int main() {\n\n Pair test1[] = {{6, 7}, {2, 3}, {7, 6}, {9, 8}, {10, 2}, {8, 9}};\n\n Pair result1_exp[] = {{6, 7}, {8, 9}};\n\n size_t res1_size;\n\n Pair *result1 = func0(test1, 6, &res1_size);\n\n qsort(result1, res1_size, sizeof(Pair), pair_comparator);\n\n assert(res1_size == 2 && memcmp(result1, result1_exp, 2 * sizeof(Pair)) == 0);\n\n free(result1);\n\n\n\n Pair test2[] = {{7, 8}, {3, 4}, {8, 7}, {10, 9}, {11, 3}, {9, 10}};\n\n Pair result2_exp[] = {{7, 8}, {9, 10}};\n\n size_t res2_size;\n\n Pair *result2 = func0(test2, 6, &res2_size);\n\n qsort(result2, res2_size, sizeof(Pair), pair_comparator);\n\n assert(res2_size == 2 && memcmp(result2, result2_exp, 2 * sizeof(Pair)) == 0);\n\n free(result2);\n\n\n\n Pair test3[] = {{8, 9}, {4, 5}, {9, 8}, {11, 10}, {12, 4}, {10, 11}};\n\n Pair result3_exp[] = {{8, 9}, {10, 11}};\n\n size_t res3_size;\n\n Pair *result3 = func0(test3, 6, &res3_size);\n\n qsort(result3, res3_size, sizeof(Pair), pair_comparator);\n\n assert(res3_size == 2 && memcmp(result3, result3_exp, 2 * sizeof(Pair)) == 0);\n\n free(result3);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbx\nmov %rsi,%r13\nmov %rdx,%rbp\nlea 0x0(,%rsi,8),%r12\nmov %r12,%rdi\ncallq 10f0 \ntest %rax,%rax\nje 128b \ntest %r13,%r13\nje 127e \nmov %rbx,%r11\nlea (%rbx,%r12,1),%rsi\nmov %rbx,%rdi\nmov $0x0,%r10d\njmp 1279 \nadd $0x8,%rdx\ncmp %rdx,%rsi\nje 1270 \nmov (%rdi),%ecx\ncmp 0x4(%rdx),%ecx\njne 1242 \nmov 0x4(%rdi),%r9d\ncmp %r9d,(%rdx)\njne 1242 \ncmp %r9d,%ecx\njge 1242 \nmovslq %r10d,%rcx\nmov (%rdi),%r8\nmov %r8,(%rax,%rcx,8)\nlea 0x1(%r10),%r10d\njmp 1242 \nadd $0x8,%rdi\ncmp %rdi,%rsi\nje 1284 \nmov %r11,%rdx\njmp 124b \nmov $0x0,%r10d\nmovslq %r10d,%r10\nmov %r10,0x0(%rbp)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov r13, rsi\nmov r12, rdx\nlea rbx, ds:0[rsi*8]\nmov rdi, rbx; size\ncall _malloc\ntest rax, rax\njz short loc_128B\ntest r13, r13\njz short loc_127E\nlea rsi, [rbp+rbx+0]\nmov r8, rbp\nmov r10d, 0\njmp short loc_1273\nloc_1240:\nadd rdx, 8\ncmp rdx, rsi\njz short loc_126A\nloc_1249:\ncmp ecx, [rdx+4]\njnz short loc_1240\nmov edi, [r9+4]\ncmp [rdx], edi\njnz short loc_1240\ncmp ecx, edi\njge short loc_1240\nmovsxd rdi, r10d\nmov r11, [r9]\nmov [rax+rdi*8], r11\nlea r10d, [r10+1]\njmp short loc_1240\nloc_126A:\nadd r8, 8\ncmp r8, rsi\njz short loc_1284\nloc_1273:\nmov r9, r8\nmov ecx, [r8]\nmov rdx, rbp\njmp short loc_1249\nloc_127E:\nmov r10d, 0\nloc_1284:\nmovsxd r10, r10d\nmov [r12], r10\nloc_128B:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(int *a1, __int64 a2, _QWORD *a3)\n{\n _QWORD *result; // rax\n int *v6; // rsi\n int *v7; // r8\n int v8; // r10d\n int *v9; // rdx\n int v10; // edi\n int v11; // ecx\n\n result = malloc(8 * a2);\n if ( result )\n {\n if ( a2 )\n {\n v6 = &a1[2 * a2];\n v7 = a1;\n v8 = 0;\n do\n {\n v11 = *v7;\n v9 = a1;\n do\n {\n if ( v11 == v9[1] )\n {\n v10 = v7[1];\n if ( *v9 == v10 && v11 < v10 )\n result[v8++] = *(_QWORD *)v7;\n }\n v9 += 2;\n }\n while ( v9 != v6 );\n v7 += 2;\n }\n while ( v7 != v6 );\n }\n else\n {\n v8 = 0;\n }\n *a3 = v8;\n }\n return result;\n}", + "ida_strip_asm": "sub_11FF:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov r13, rsi\nmov r12, rdx\nlea rbx, ds:0[rsi*8]\nmov rdi, rbx; size\ncall _malloc\ntest rax, rax\njz short loc_128B\ntest r13, r13\njz short loc_127E\nlea rsi, [rbp+rbx+0]\nmov r8, rbp\nmov r10d, 0\njmp short loc_1273\nloc_1240:\nadd rdx, 8\ncmp rdx, rsi\njz short loc_126A\nloc_1249:\ncmp ecx, [rdx+4]\njnz short loc_1240\nmov edi, [r9+4]\ncmp [rdx], edi\njnz short loc_1240\ncmp ecx, edi\njge short loc_1240\nmovsxd rdi, r10d\nmov r11, [r9]\nmov [rax+rdi*8], r11\nlea r10d, [r10+1]\njmp short loc_1240\nloc_126A:\nadd r8, 8\ncmp r8, rsi\njz short loc_1284\nloc_1273:\nmov r9, r8\nmov ecx, [r8]\nmov rdx, rbp\njmp short loc_1249\nloc_127E:\nmov r10d, 0\nloc_1284:\nmovsxd r10, r10d\nmov [r12], r10\nloc_128B:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11FF(int *a1, __int64 a2, _QWORD *a3)\n{\n _QWORD *result; // rax\n int *v6; // rsi\n int *v7; // r8\n int v8; // r10d\n int *v9; // rdx\n int v10; // edi\n int v11; // ecx\n\n result = malloc(8 * a2);\n if ( result )\n {\n if ( a2 )\n {\n v6 = &a1[2 * a2];\n v7 = a1;\n v8 = 0;\n do\n {\n v11 = *v7;\n v9 = a1;\n do\n {\n if ( v11 == v9[1] )\n {\n v10 = v7[1];\n if ( *v9 == v10 && v11 < v10 )\n result[v8++] = *(_QWORD *)v7;\n }\n v9 += 2;\n }\n while ( v9 != v6 );\n v7 += 2;\n }\n while ( v7 != v6 );\n }\n else\n {\n v8 = 0;\n }\n *a3 = v8;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11FF(int *a1, long long a2, uint64_t *a3) {\n uint64_t *result;\n int *v6;\n int *v7;\n int v8;\n int *v9;\n int v10;\n int v11;\n result = malloc(8 * a2);\n if (result) {\n if (a2) {\n v6 = &a1[2 * a2];\n v7 = a1;\n v8 = 0;\n do {\n v11 = *v7;\n v9 = a1;\n do {\n if (v11 == v9[1]) {\n v10 = v7[1];\n if (*v9 == v10 && v11 < v10) result[v8++] = *(uint64_t *)v7;\n }\n v9 += 2;\n } while (v9 != v6);\n v7 += 2;\n } while (v7 != v6);\n } else {\n v8 = 0;\n }\n *a3 = v8;\n }\n return result;\n}", + "ida_pseudo_norm": "uint64_t *func0(int *a1, long long a2, uint64_t *a3) {\n uint64_t *result;\n int *v6;\n int *v7;\n int v8;\n int *v9;\n int v10;\n int v11;\n result = malloc(8 * a2);\n if (result) {\n if (a2) {\n v6 = &a1[2 * a2];\n v7 = a1;\n v8 = 0;\n do {\n v11 = *v7;\n v9 = a1;\n do {\n if (v11 == v9[1]) {\n v10 = v7[1];\n if (*v9 == v10 && v11 < v10) result[v8++] = *(uint64_t *)v7;\n }\n v9 += 2;\n } while (v9 != v6);\n v7 += 2;\n } while (v7 != v6);\n } else {\n v8 = 0;\n }\n *a3 = v8;\n }\n return result;\n}" + }, + { + "index": 490, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct Pair {\n\n int first;\n\n int second;\n\n} Pair;\n\n\n\nint pair_comparator(const void *v1, const void *v2) {\n\n const Pair *p1 = (const Pair *)v1;\n\n const Pair *p2 = (const Pair *)v2;\n\n if (p1->first != p2->first)\n\n return p1->first - p2->first;\n\n return p1->second - p2->second;\n\n}\n\n\n\n", + "func": "Pair *func0(Pair test_list[], size_t size, size_t *result_size) {\n Pair *res = malloc(size * sizeof(Pair));\n if (!res) return NULL;\n int res_count = 0;\n for (int i = 0; i < size; i++) {\n for (int j = 0; j < size; j++) {\n if (test_list[i].first == test_list[j].second &&\n test_list[i].second == test_list[j].first) {\n if (test_list[i].first < test_list[i].second) {\n res[res_count++] = test_list[i];\n }\n }\n }\n }\n *result_size = res_count;\n return res;\n}", + "test": "int main() {\n\n Pair test1[] = {{6, 7}, {2, 3}, {7, 6}, {9, 8}, {10, 2}, {8, 9}};\n\n Pair result1_exp[] = {{6, 7}, {8, 9}};\n\n size_t res1_size;\n\n Pair *result1 = func0(test1, 6, &res1_size);\n\n qsort(result1, res1_size, sizeof(Pair), pair_comparator);\n\n assert(res1_size == 2 && memcmp(result1, result1_exp, 2 * sizeof(Pair)) == 0);\n\n free(result1);\n\n\n\n Pair test2[] = {{7, 8}, {3, 4}, {8, 7}, {10, 9}, {11, 3}, {9, 10}};\n\n Pair result2_exp[] = {{7, 8}, {9, 10}};\n\n size_t res2_size;\n\n Pair *result2 = func0(test2, 6, &res2_size);\n\n qsort(result2, res2_size, sizeof(Pair), pair_comparator);\n\n assert(res2_size == 2 && memcmp(result2, result2_exp, 2 * sizeof(Pair)) == 0);\n\n free(result2);\n\n\n\n Pair test3[] = {{8, 9}, {4, 5}, {9, 8}, {11, 10}, {12, 4}, {10, 11}};\n\n Pair result3_exp[] = {{8, 9}, {10, 11}};\n\n size_t res3_size;\n\n Pair *result3 = func0(test3, 6, &res3_size);\n\n qsort(result3, res3_size, sizeof(Pair), pair_comparator);\n\n assert(res3_size == 2 && memcmp(result3, result3_exp, 2 * sizeof(Pair)) == 0);\n\n free(result3);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov %rdx,%r13\npush %r12\nmov %rdi,%r12\npush %rbp\nmov %rsi,%rbp\npush %rbx\nlea 0x0(,%rsi,8),%rbx\nmov %rbx,%rdi\nsub $0x8,%rsp\ncallq 10d0 \ntest %rax,%rax\nje 158d \ntest %rbp,%rbp\nje 1589 \nlea (%r12,%rbx,1),%r9\nmov %r12,%rsi\nxor %r11d,%r11d\nxor %r8d,%r8d\nxchg %ax,%ax\nmov (%rsi),%edi\nmov %r12,%rcx\njmp 1549 \nnopw 0x0(%rax,%rax,1)\nadd $0x8,%rcx\ncmp %r9,%rcx\nje 1580 \nmov %r8,%rbp\ncmp %edi,0x4(%rcx)\njne 1540 \nmov 0x4(%rsi),%r10d\ncmp %r10d,(%rcx)\njne 1540 \ncmp %edi,%r10d\njle 1540 \nmov (%rsi),%rdx\nadd $0x1,%r11d\nadd $0x8,%rcx\nmov %rdx,(%rax,%r8,8)\nmovslq %r11d,%r8\nmov %r8,%rbp\ncmp %r9,%rcx\njne 1549 \nnopl 0x0(%rax)\nadd $0x8,%rsi\ncmp %r9,%rsi\njne 1530 \nmov %rbp,0x0(%r13)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r13\nmov r13, rsi\npush r12\nmov r12, rdx\npush rbp\nmov rbp, rdi\npush rbx\nlea rbx, ds:0[rsi*8]\nmov rdi, rbx; size\nsub rsp, 8\ncall _malloc\ntest rax, rax\njz short loc_14E8\nlea rdi, [rbp+rbx+0]\nmov r8, rbp\nxor r9d, r9d\ntest r13, r13\njz short loc_14E4\nnop dword ptr [rax+00h]\nloc_1490:\nmov ecx, [r8]\nmov rdx, rbp\njmp short loc_14A9\nloc_14A0:\nadd rdx, 8\ncmp rdx, rdi\njz short loc_14D8\nloc_14A9:\ncmp ecx, [rdx+4]\njnz short loc_14A0\nmov esi, [r8+4]\ncmp [rdx], esi\njnz short loc_14A0\ncmp ecx, esi\njge short loc_14A0\nmov r10, [r8]\nmovsxd rsi, r9d\nadd rdx, 8\nadd r9d, 1\nmov [rax+rsi*8], r10\ncmp rdx, rdi\njnz short loc_14A9\nnop dword ptr [rax+00000000h]\nloc_14D8:\nadd r8, 8\ncmp r8, rdx\njnz short loc_1490\nmovsxd r13, r9d\nloc_14E4:\nmov [r12], r13\nloc_14E8:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(int *a1, __int64 a2, _QWORD *a3)\n{\n __int64 v3; // r13\n _QWORD *result; // rax\n int *v7; // rdi\n int *v8; // r8\n int v9; // r9d\n int v10; // ecx\n int *v11; // rdx\n int v12; // esi\n __int64 v13; // rsi\n\n v3 = a2;\n result = malloc(8 * a2);\n if ( result )\n {\n v7 = &a1[2 * a2];\n v8 = a1;\n v9 = 0;\n if ( a2 )\n {\n do\n {\n v10 = *v8;\n v11 = a1;\n do\n {\n while ( 1 )\n {\n if ( v10 == v11[1] )\n {\n v12 = v8[1];\n if ( *v11 == v12 && v10 < v12 )\n break;\n }\n v11 += 2;\n if ( v11 == v7 )\n goto LABEL_9;\n }\n v13 = v9;\n v11 += 2;\n ++v9;\n result[v13] = *(_QWORD *)v8;\n }\n while ( v11 != v7 );\nLABEL_9:\n v8 += 2;\n }\n while ( v8 != v11 );\n v3 = v9;\n }\n *a3 = v3;\n }\n return result;\n}", + "ida_strip_asm": "sub_1450:\nendbr64\npush r13\nmov r13, rsi\npush r12\nmov r12, rdx\npush rbp\nmov rbp, rdi\npush rbx\nlea rbx, ds:0[rsi*8]\nmov rdi, rbx; size\nsub rsp, 8\ncall _malloc\ntest rax, rax\njz short loc_14E8\nlea rdi, [rbp+rbx+0]\nmov r8, rbp\nxor r9d, r9d\ntest r13, r13\njz short loc_14E4\nnop dword ptr [rax+00h]\nloc_1490:\nmov ecx, [r8]\nmov rdx, rbp\njmp short loc_14A9\nloc_14A0:\nadd rdx, 8\ncmp rdx, rdi\njz short loc_14D8\nloc_14A9:\ncmp ecx, [rdx+4]\njnz short loc_14A0\nmov esi, [r8+4]\ncmp [rdx], esi\njnz short loc_14A0\ncmp ecx, esi\njge short loc_14A0\nmov r10, [r8]\nmovsxd rsi, r9d\nadd rdx, 8\nadd r9d, 1\nmov [rax+rsi*8], r10\ncmp rdx, rdi\njnz short loc_14A9\nnop dword ptr [rax+00000000h]\nloc_14D8:\nadd r8, 8\ncmp r8, rdx\njnz short loc_1490\nmovsxd r13, r9d\nloc_14E4:\nmov [r12], r13\nloc_14E8:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1450(int *a1, __int64 a2, _QWORD *a3)\n{\n __int64 v3; // r13\n _QWORD *result; // rax\n int *v7; // rdi\n int *v8; // r8\n int v9; // r9d\n int v10; // ecx\n int *v11; // rdx\n int v12; // esi\n __int64 v13; // rsi\n\n v3 = a2;\n result = malloc(8 * a2);\n if ( result )\n {\n v7 = &a1[2 * a2];\n v8 = a1;\n v9 = 0;\n if ( a2 )\n {\n do\n {\n v10 = *v8;\n v11 = a1;\n do\n {\n while ( 1 )\n {\n if ( v10 == v11[1] )\n {\n v12 = v8[1];\n if ( *v11 == v12 && v10 < v12 )\n break;\n }\n v11 += 2;\n if ( v11 == v7 )\n goto LABEL_9;\n }\n v13 = v9;\n v11 += 2;\n ++v9;\n result[v13] = *(_QWORD *)v8;\n }\n while ( v11 != v7 );\nLABEL_9:\n v8 += 2;\n }\n while ( v8 != v11 );\n v3 = v9;\n }\n *a3 = v3;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1450(int *a1, long long a2, uint64_t *a3) {\n long long v3;\n uint64_t *result;\n int *v7;\n int *v8;\n int v9;\n int v10;\n int *v11;\n int v12;\n long long v13;\n v3 = a2;\n result = malloc(8 * a2);\n if (result) {\n v7 = &a1[2 * a2];\n v8 = a1;\n v9 = 0;\n if (a2) {\n do {\n v10 = *v8;\n v11 = a1;\n do {\n while (1) {\n if (v10 == v11[1]) {\n v12 = v8[1];\n if (*v11 == v12 && v10 < v12) break;\n }\n v11 += 2;\n if (v11 == v7) goto LABEL_9;\n }\n v13 = v9;\n v11 += 2;\n ++v9;\n result[v13] = *(uint64_t *)v8;\n } while (v11 != v7);\n LABEL_9:\n v8 += 2;\n } while (v8 != v11);\n v3 = v9;\n }\n *a3 = v3;\n }\n return result;\n}", + "ida_pseudo_norm": "uint64_t *func0(int *a1, long long a2, uint64_t *a3) {\n long long v3;\n uint64_t *result;\n int *v7;\n int *v8;\n int v9;\n int v10;\n int *v11;\n int v12;\n long long v13;\n v3 = a2;\n result = malloc(8 * a2);\n if (result) {\n v7 = &a1[2 * a2];\n v8 = a1;\n v9 = 0;\n if (a2) {\n do {\n v10 = *v8;\n v11 = a1;\n do {\n while (1) {\n if (v10 == v11[1]) {\n v12 = v8[1];\n if (*v11 == v12 && v10 < v12) break;\n }\n v11 += 2;\n if (v11 == v7) goto LABEL_9;\n }\n v13 = v9;\n v11 += 2;\n ++v9;\n result[v13] = *(uint64_t *)v8;\n } while (v11 != v7);\n LABEL_9:\n v8 += 2;\n } while (v8 != v11);\n v3 = v9;\n }\n *a3 = v3;\n }\n return result;\n}" + }, + { + "index": 490, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct Pair {\n\n int first;\n\n int second;\n\n} Pair;\n\n\n\nint pair_comparator(const void *v1, const void *v2) {\n\n const Pair *p1 = (const Pair *)v1;\n\n const Pair *p2 = (const Pair *)v2;\n\n if (p1->first != p2->first)\n\n return p1->first - p2->first;\n\n return p1->second - p2->second;\n\n}\n\n\n\n", + "func": "Pair *func0(Pair test_list[], size_t size, size_t *result_size) {\n Pair *res = malloc(size * sizeof(Pair));\n if (!res) return NULL;\n int res_count = 0;\n for (int i = 0; i < size; i++) {\n for (int j = 0; j < size; j++) {\n if (test_list[i].first == test_list[j].second &&\n test_list[i].second == test_list[j].first) {\n if (test_list[i].first < test_list[i].second) {\n res[res_count++] = test_list[i];\n }\n }\n }\n }\n *result_size = res_count;\n return res;\n}", + "test": "int main() {\n\n Pair test1[] = {{6, 7}, {2, 3}, {7, 6}, {9, 8}, {10, 2}, {8, 9}};\n\n Pair result1_exp[] = {{6, 7}, {8, 9}};\n\n size_t res1_size;\n\n Pair *result1 = func0(test1, 6, &res1_size);\n\n qsort(result1, res1_size, sizeof(Pair), pair_comparator);\n\n assert(res1_size == 2 && memcmp(result1, result1_exp, 2 * sizeof(Pair)) == 0);\n\n free(result1);\n\n\n\n Pair test2[] = {{7, 8}, {3, 4}, {8, 7}, {10, 9}, {11, 3}, {9, 10}};\n\n Pair result2_exp[] = {{7, 8}, {9, 10}};\n\n size_t res2_size;\n\n Pair *result2 = func0(test2, 6, &res2_size);\n\n qsort(result2, res2_size, sizeof(Pair), pair_comparator);\n\n assert(res2_size == 2 && memcmp(result2, result2_exp, 2 * sizeof(Pair)) == 0);\n\n free(result2);\n\n\n\n Pair test3[] = {{8, 9}, {4, 5}, {9, 8}, {11, 10}, {12, 4}, {10, 11}};\n\n Pair result3_exp[] = {{8, 9}, {10, 11}};\n\n size_t res3_size;\n\n Pair *result3 = func0(test3, 6, &res3_size);\n\n qsort(result3, res3_size, sizeof(Pair), pair_comparator);\n\n assert(res3_size == 2 && memcmp(result3, result3_exp, 2 * sizeof(Pair)) == 0);\n\n free(result3);\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov %rdx,%r13\npush %r12\nmov %rdi,%r12\npush %rbp\nmov %rsi,%rbp\npush %rbx\nlea 0x0(,%rsi,8),%rbx\nmov %rbx,%rdi\nsub $0x8,%rsp\ncallq 10d0 \ntest %rax,%rax\nje 14ed \ntest %rbp,%rbp\nje 14e9 \nlea (%r12,%rbx,1),%r9\nmov %r12,%rsi\nxor %r11d,%r11d\nxor %r8d,%r8d\nxchg %ax,%ax\nmov (%rsi),%edi\nmov %r12,%rcx\njmp 14a9 \nnopw 0x0(%rax,%rax,1)\nadd $0x8,%rcx\ncmp %rcx,%r9\nje 14e0 \nmov %r8,%rbp\ncmp %edi,0x4(%rcx)\njne 14a0 \nmov 0x4(%rsi),%r10d\ncmp %r10d,(%rcx)\njne 14a0 \ncmp %edi,%r10d\njle 14a0 \nmov (%rsi),%rdx\nadd $0x1,%r11d\nadd $0x8,%rcx\nmov %rdx,(%rax,%r8,8)\nmovslq %r11d,%r8\nmov %r8,%rbp\ncmp %rcx,%r9\njne 14a9 \nnopl 0x0(%rax)\nadd $0x8,%rsi\ncmp %rsi,%r9\njne 1490 \nmov %rbp,0x0(%r13)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r13\nmov r13, rsi\npush r12\nmov r12, rdx\npush rbp\nmov rbp, rdi\npush rbx\nlea rbx, ds:0[rsi*8]\nmov rdi, rbx; size\nsub rsp, 8\ncall _malloc\ntest rax, rax\njz short loc_14E8\nlea rdi, [rbp+rbx+0]\nmov r8, rbp\nxor r9d, r9d\ntest r13, r13\njz short loc_14E4\nnop dword ptr [rax+00h]\nloc_1490:\nmov ecx, [r8]\nmov rdx, rbp\njmp short loc_14A9\nloc_14A0:\nadd rdx, 8\ncmp rdx, rdi\njz short loc_14D8\nloc_14A9:\ncmp ecx, [rdx+4]\njnz short loc_14A0\nmov esi, [r8+4]\ncmp [rdx], esi\njnz short loc_14A0\ncmp ecx, esi\njge short loc_14A0\nmov r10, [r8]\nmovsxd rsi, r9d\nadd rdx, 8\nadd r9d, 1\nmov [rax+rsi*8], r10\ncmp rdx, rdi\njnz short loc_14A9\nnop dword ptr [rax+00000000h]\nloc_14D8:\nadd r8, 8\ncmp r8, rdx\njnz short loc_1490\nmovsxd r13, r9d\nloc_14E4:\nmov [r12], r13\nloc_14E8:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(int *a1, __int64 a2, _QWORD *a3)\n{\n __int64 v3; // r13\n _QWORD *result; // rax\n int *v7; // rdi\n int *v8; // r8\n int v9; // r9d\n int v10; // ecx\n int *v11; // rdx\n int v12; // esi\n __int64 v13; // rsi\n\n v3 = a2;\n result = malloc(8 * a2);\n if ( result )\n {\n v7 = &a1[2 * a2];\n v8 = a1;\n v9 = 0;\n if ( a2 )\n {\n do\n {\n v10 = *v8;\n v11 = a1;\n do\n {\n while ( 1 )\n {\n if ( v10 == v11[1] )\n {\n v12 = v8[1];\n if ( *v11 == v12 && v10 < v12 )\n break;\n }\n v11 += 2;\n if ( v11 == v7 )\n goto LABEL_9;\n }\n v13 = v9;\n v11 += 2;\n ++v9;\n result[v13] = *(_QWORD *)v8;\n }\n while ( v11 != v7 );\nLABEL_9:\n v8 += 2;\n }\n while ( v8 != v11 );\n v3 = v9;\n }\n *a3 = v3;\n }\n return result;\n}", + "ida_strip_asm": "sub_1450:\nendbr64\npush r13\nmov r13, rsi\npush r12\nmov r12, rdx\npush rbp\nmov rbp, rdi\npush rbx\nlea rbx, ds:0[rsi*8]\nmov rdi, rbx; size\nsub rsp, 8\ncall _malloc\ntest rax, rax\njz short loc_14E8\nlea rdi, [rbp+rbx+0]\nmov r8, rbp\nxor r9d, r9d\ntest r13, r13\njz short loc_14E4\nnop dword ptr [rax+00h]\nloc_1490:\nmov ecx, [r8]\nmov rdx, rbp\njmp short loc_14A9\nloc_14A0:\nadd rdx, 8\ncmp rdx, rdi\njz short loc_14D8\nloc_14A9:\ncmp ecx, [rdx+4]\njnz short loc_14A0\nmov esi, [r8+4]\ncmp [rdx], esi\njnz short loc_14A0\ncmp ecx, esi\njge short loc_14A0\nmov r10, [r8]\nmovsxd rsi, r9d\nadd rdx, 8\nadd r9d, 1\nmov [rax+rsi*8], r10\ncmp rdx, rdi\njnz short loc_14A9\nnop dword ptr [rax+00000000h]\nloc_14D8:\nadd r8, 8\ncmp r8, rdx\njnz short loc_1490\nmovsxd r13, r9d\nloc_14E4:\nmov [r12], r13\nloc_14E8:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1450(int *a1, __int64 a2, _QWORD *a3)\n{\n __int64 v3; // r13\n _QWORD *result; // rax\n int *v7; // rdi\n int *v8; // r8\n int v9; // r9d\n int v10; // ecx\n int *v11; // rdx\n int v12; // esi\n __int64 v13; // rsi\n\n v3 = a2;\n result = malloc(8 * a2);\n if ( result )\n {\n v7 = &a1[2 * a2];\n v8 = a1;\n v9 = 0;\n if ( a2 )\n {\n do\n {\n v10 = *v8;\n v11 = a1;\n do\n {\n while ( 1 )\n {\n if ( v10 == v11[1] )\n {\n v12 = v8[1];\n if ( *v11 == v12 && v10 < v12 )\n break;\n }\n v11 += 2;\n if ( v11 == v7 )\n goto LABEL_9;\n }\n v13 = v9;\n v11 += 2;\n ++v9;\n result[v13] = *(_QWORD *)v8;\n }\n while ( v11 != v7 );\nLABEL_9:\n v8 += 2;\n }\n while ( v8 != v11 );\n v3 = v9;\n }\n *a3 = v3;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1450(int *a1, long long a2, uint64_t *a3) {\n long long v3;\n uint64_t *result;\n int *v7;\n int *v8;\n int v9;\n int v10;\n int *v11;\n int v12;\n long long v13;\n v3 = a2;\n result = malloc(8 * a2);\n if (result) {\n v7 = &a1[2 * a2];\n v8 = a1;\n v9 = 0;\n if (a2) {\n do {\n v10 = *v8;\n v11 = a1;\n do {\n while (1) {\n if (v10 == v11[1]) {\n v12 = v8[1];\n if (*v11 == v12 && v10 < v12) break;\n }\n v11 += 2;\n if (v11 == v7) goto LABEL_9;\n }\n v13 = v9;\n v11 += 2;\n ++v9;\n result[v13] = *(uint64_t *)v8;\n } while (v11 != v7);\n LABEL_9:\n v8 += 2;\n } while (v8 != v11);\n v3 = v9;\n }\n *a3 = v3;\n }\n return result;\n}", + "ida_pseudo_norm": "uint64_t *func0(int *a1, long long a2, uint64_t *a3) {\n long long v3;\n uint64_t *result;\n int *v7;\n int *v8;\n int v9;\n int v10;\n int *v11;\n int v12;\n long long v13;\n v3 = a2;\n result = malloc(8 * a2);\n if (result) {\n v7 = &a1[2 * a2];\n v8 = a1;\n v9 = 0;\n if (a2) {\n do {\n v10 = *v8;\n v11 = a1;\n do {\n while (1) {\n if (v10 == v11[1]) {\n v12 = v8[1];\n if (*v11 == v12 && v10 < v12) break;\n }\n v11 += 2;\n if (v11 == v7) goto LABEL_9;\n }\n v13 = v9;\n v11 += 2;\n ++v9;\n result[v13] = *(uint64_t *)v8;\n } while (v11 != v7);\n LABEL_9:\n v8 += 2;\n } while (v8 != v11);\n v3 = v9;\n }\n *a3 = v3;\n }\n return result;\n}" + }, + { + "index": 491, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "double func0(double a, int n, double r) {\n double total = (a * (1 - pow(r, n))) / (1 - r);\n return total;\n}", + "test": "int main() {\n\n assert(func0(1,5,2)==31);\n\n assert(func0(1,5,4)==341);\n\n assert(func0(2,6,3)==728);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmovsd %xmm0,-0x18(%rbp)\nmov %edi,-0x1c(%rbp)\nmovsd %xmm1,-0x28(%rbp)\ncvtsi2sdl -0x1c(%rbp),%xmm0\nmov -0x28(%rbp),%rax\nmovapd %xmm0,%xmm1\nmovq %rax,%xmm0\ncallq 1060 \nmovsd 0xedf(%rip),%xmm1\nsubsd %xmm0,%xmm1\nmovapd %xmm1,%xmm0\nmulsd -0x18(%rbp),%xmm0\nmovsd 0xeca(%rip),%xmm1\nsubsd -0x28(%rbp),%xmm1\ndivsd %xmm1,%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmovsd -0x8(%rbp),%xmm0\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmovsd [rbp+var_18], xmm0\nmov [rbp+var_1C], edi\nmovsd [rbp+x], xmm1\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_1C]\nmov rax, [rbp+x]\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\nmovapd xmm1, xmm0\nmovsd xmm0, cs:qword_2068\nsubsd xmm0, xmm1\nmulsd xmm0, [rbp+var_18]\nmovsd xmm1, cs:qword_2068\nsubsd xmm1, [rbp+x]\ndivsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "double __fastcall func0(int a1, double a2, double a3)\n{\n return (1.0 - pow(a3, (double)a1)) * a2 / (1.0 - a3);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmovsd [rbp+var_18], xmm0\nmov [rbp+var_1C], edi\nmovsd [rbp+x], xmm1\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_1C]\nmov rax, [rbp+x]\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\nmovapd xmm1, xmm0\nmovsd xmm0, cs:qword_2068\nsubsd xmm0, xmm1\nmulsd xmm0, [rbp+var_18]\nmovsd xmm1, cs:qword_2068\nsubsd xmm1, [rbp+x]\ndivsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "double __fastcall sub_1169(int a1, double a2, double a3)\n{\n return (1.0 - pow(a3, (double)a1)) * a2 / (1.0 - a3);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1169(int a1, double a2, double a3) {\n return (1.0 - pow(a3, (double)a1)) * a2 / (1.0 - a3);\n}", + "ida_pseudo_norm": "double func0(int a1, double a2, double a3) {\n return (1.0 - pow(a3, (double)a1)) * a2 / (1.0 - a3);\n}" + }, + { + "index": 491, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "double func0(double a, int n, double r) {\n double total = (a * (1 - pow(r, n))) / (1 - r);\n return total;\n}", + "test": "int main() {\n\n assert(func0(1,5,2)==31);\n\n assert(func0(1,5,4)==341);\n\n assert(func0(2,6,3)==728);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x18,%rsp\nmovsd %xmm0,(%rsp)\nmovapd %xmm1,%xmm3\npxor %xmm1,%xmm1\ncvtsi2sd %edi,%xmm1\nmovsd %xmm3,0x8(%rsp)\nmovapd %xmm3,%xmm0\ncallq 1060 \nmovsd 0xee7(%rip),%xmm1\nmovapd %xmm1,%xmm2\nsubsd %xmm0,%xmm2\nmovapd %xmm2,%xmm0\nmulsd (%rsp),%xmm0\nsubsd 0x8(%rsp),%xmm1\ndivsd %xmm1,%xmm0\nadd $0x18,%rsp\nretq\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 18h\nmovsd [rsp+18h+var_18], xmm0\nmovapd xmm4, xmm1\npxor xmm1, xmm1\ncvtsi2sd xmm1, edi; y\nmovsd [rsp+18h+var_10], xmm4\nmovapd xmm0, xmm4; x\ncall _pow\nmovsd xmm1, cs:qword_2068\nmovapd xmm3, xmm1\nsubsd xmm3, xmm0\nmovapd xmm0, xmm3\nmulsd xmm0, [rsp+18h+var_18]\nsubsd xmm1, [rsp+18h+var_10]\ndivsd xmm0, xmm1\nadd rsp, 18h\nretn", + "ida_pseudo": "double __fastcall func0(int a1, double a2, double a3)\n{\n return (1.0 - pow(a3, (double)a1)) * a2 / (1.0 - a3);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nsub rsp, 18h\nmovsd [rsp+18h+var_18], xmm0\nmovapd xmm4, xmm1\npxor xmm1, xmm1\ncvtsi2sd xmm1, edi; y\nmovsd [rsp+18h+var_10], xmm4\nmovapd xmm0, xmm4; x\ncall _pow\nmovsd xmm1, cs:qword_2068\nmovapd xmm3, xmm1\nsubsd xmm3, xmm0\nmovapd xmm0, xmm3\nmulsd xmm0, [rsp+18h+var_18]\nsubsd xmm1, [rsp+18h+var_10]\ndivsd xmm0, xmm1\nadd rsp, 18h\nretn", + "ida_strip_pseudo": "double __fastcall sub_1169(int a1, double a2, double a3)\n{\n return (1.0 - pow(a3, (double)a1)) * a2 / (1.0 - a3);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1169(int a1, double a2, double a3) {\n return (1.0 - pow(a3, (double)a1)) * a2 / (1.0 - a3);\n}", + "ida_pseudo_norm": "double func0(int a1, double a2, double a3) {\n return (1.0 - pow(a3, (double)a1)) * a2 / (1.0 - a3);\n}" + }, + { + "index": 491, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "double func0(double a, int n, double r) {\n double total = (a * (1 - pow(r, n))) / (1 - r);\n return total;\n}", + "test": "int main() {\n\n assert(func0(1,5,2)==31);\n\n assert(func0(1,5,4)==341);\n\n assert(func0(2,6,3)==728);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmovapd %xmm1,%xmm3\npxor %xmm1,%xmm1\nsub $0x18,%rsp\ncvtsi2sd %edi,%xmm1\nmovsd %xmm0,(%rsp)\nmovapd %xmm3,%xmm0\nmovsd %xmm3,0x8(%rsp)\ncallq 1050 \nmovsd 0xe78(%rip),%xmm2\nmovsd 0x8(%rsp),%xmm3\nmovapd %xmm2,%xmm4\nsubsd %xmm3,%xmm2\nsubsd %xmm0,%xmm4\nmovsd (%rsp),%xmm0\nadd $0x18,%rsp\nmulsd %xmm4,%xmm0\ndivsd %xmm2,%xmm0\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\nmovapd xmm3, xmm1\npxor xmm1, xmm1\nsub rsp, 18h\ncvtsi2sd xmm1, edi; y\nmovsd [rsp+18h+var_18], xmm0\nmovapd xmm0, xmm3; x\nmovsd [rsp+18h+var_10], xmm3\ncall _pow\nmovsd xmm2, cs:qword_2008\nmovsd xmm3, [rsp+18h+var_10]\nmovapd xmm4, xmm2\nsubsd xmm2, xmm3\nsubsd xmm4, xmm0\nmovsd xmm0, [rsp+18h+var_18]\nadd rsp, 18h\nmulsd xmm0, xmm4\ndivsd xmm0, xmm2\nretn", + "ida_pseudo": "double __fastcall func0(int a1, double a2, double a3)\n{\n return a2 * (1.0 - pow(a3, (double)a1)) / (1.0 - a3);\n}", + "ida_strip_asm": "sub_1160:\nendbr64\nmovapd xmm3, xmm1\npxor xmm1, xmm1\nsub rsp, 18h\ncvtsi2sd xmm1, edi; y\nmovsd [rsp+18h+var_18], xmm0\nmovapd xmm0, xmm3; x\nmovsd [rsp+18h+var_10], xmm3\ncall _pow\nmovsd xmm2, cs:qword_2008\nmovsd xmm3, [rsp+18h+var_10]\nmovapd xmm4, xmm2\nsubsd xmm2, xmm3\nsubsd xmm4, xmm0\nmovsd xmm0, [rsp+18h+var_18]\nadd rsp, 18h\nmulsd xmm0, xmm4\ndivsd xmm0, xmm2\nretn", + "ida_strip_pseudo": "double __fastcall sub_1160(int a1, double a2, double a3)\n{\n return a2 * (1.0 - pow(a3, (double)a1)) / (1.0 - a3);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1160(int a1, double a2, double a3) {\n return a2 * (1.0 - pow(a3, (double)a1)) / (1.0 - a3);\n}", + "ida_pseudo_norm": "double func0(int a1, double a2, double a3) {\n return a2 * (1.0 - pow(a3, (double)a1)) / (1.0 - a3);\n}" + }, + { + "index": 491, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "double func0(double a, int n, double r) {\n double total = (a * (1 - pow(r, n))) / (1 - r);\n return total;\n}", + "test": "int main() {\n\n assert(func0(1,5,2)==31);\n\n assert(func0(1,5,4)==341);\n\n assert(func0(2,6,3)==728);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nmovapd %xmm1,%xmm3\npxor %xmm1,%xmm1\nsub $0x18,%rsp\ncvtsi2sd %edi,%xmm1\nmovsd %xmm0,(%rsp)\nmovapd %xmm3,%xmm0\nmovsd %xmm3,0x8(%rsp)\ncallq 1050 \nmovsd 0xe78(%rip),%xmm2\nmovsd 0x8(%rsp),%xmm3\nmovapd %xmm2,%xmm4\nsubsd %xmm3,%xmm2\nsubsd %xmm0,%xmm4\nmovsd (%rsp),%xmm0\nadd $0x18,%rsp\nmulsd %xmm4,%xmm0\ndivsd %xmm2,%xmm0\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\nmovapd xmm3, xmm1\npxor xmm1, xmm1\nsub rsp, 18h\ncvtsi2sd xmm1, edi; y\nmovsd [rsp+18h+var_18], xmm0\nmovapd xmm0, xmm3; x\nmovsd [rsp+18h+var_10], xmm3\ncall _pow\nmovsd xmm2, cs:qword_2008\nmovsd xmm3, [rsp+18h+var_10]\nmovapd xmm4, xmm2\nsubsd xmm2, xmm3\nsubsd xmm4, xmm0\nmovsd xmm0, [rsp+18h+var_18]\nadd rsp, 18h\nmulsd xmm0, xmm4\ndivsd xmm0, xmm2\nretn", + "ida_pseudo": "double __fastcall func0(int a1, double a2, double a3)\n{\n return a2 * (1.0 - pow(a3, (double)a1)) / (1.0 - a3);\n}", + "ida_strip_asm": "sub_1160:\nendbr64\nmovapd xmm3, xmm1\npxor xmm1, xmm1\nsub rsp, 18h\ncvtsi2sd xmm1, edi; y\nmovsd [rsp+18h+var_18], xmm0\nmovapd xmm0, xmm3; x\nmovsd [rsp+18h+var_10], xmm3\ncall _pow\nmovsd xmm2, cs:qword_2008\nmovsd xmm3, [rsp+18h+var_10]\nmovapd xmm4, xmm2\nsubsd xmm2, xmm3\nsubsd xmm4, xmm0\nmovsd xmm0, [rsp+18h+var_18]\nadd rsp, 18h\nmulsd xmm0, xmm4\ndivsd xmm0, xmm2\nretn", + "ida_strip_pseudo": "double __fastcall sub_1160(int a1, double a2, double a3)\n{\n return a2 * (1.0 - pow(a3, (double)a1)) / (1.0 - a3);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1160(int a1, double a2, double a3) {\n return a2 * (1.0 - pow(a3, (double)a1)) / (1.0 - a3);\n}", + "ida_pseudo_norm": "double func0(int a1, double a2, double a3) {\n return a2 * (1.0 - pow(a3, (double)a1)) / (1.0 - a3);\n}" + }, + { + "index": 492, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int item_list[], int size, int item) {\n int first = 0;\n int last = size - 1;\n int found = 0;\n while (first <= last && !found) {\n int mid = (first + last) / 2;\n if (item_list[mid] == item) {\n found = 1;\n } else {\n if (item < item_list[mid]) {\n last = mid - 1;\n } else {\n first = mid + 1;\n }\n }\n }\n return found;\n}", + "test": "int main() {\n\n int list1[] = {1, 2, 3, 5, 8};\n\n int size1 = sizeof(list1) / sizeof(list1[0]);\n\n int list2[] = {7, 8, 9, 10, 13};\n\n int size2 = sizeof(list2) / sizeof(list2[0]);\n\n int list3[] = {11, 13, 14, 19, 22, 36};\n\n int size3 = sizeof(list3) / sizeof(list3[0]);\n\n\n\n assert(func0(list1, size1, 6) == 0);\n\n assert(func0(list2, size2, 10) == 1);\n\n assert(func0(list3, size3, 23) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmovl $0x0,-0x10(%rbp)\nmov -0x1c(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11fb \nmov -0x10(%rbp),%edx\nmov -0xc(%rbp),%eax\nadd %edx,%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x20(%rbp)\njne 11cc \nmovl $0x1,-0x8(%rbp)\njmp 11fb \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x20(%rbp)\njge 11f2 \nmov -0x4(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0xc(%rbp)\njmp 11fb \nmov -0x4(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x10(%rbp)\nmov -0x10(%rbp),%eax\ncmp -0xc(%rbp),%eax\njg 1209 \ncmpl $0x0,-0x8(%rbp)\nje 1194 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_10], 0\nmov eax, [rbp+var_1C]\nsub eax, 1\nmov [rbp+var_C], eax\nmov [rbp+var_8], 0\njmp short loc_11FB\nloc_1194:\nmov edx, [rbp+var_10]\nmov eax, [rbp+var_C]\nadd eax, edx\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njnz short loc_11CC\nmov [rbp+var_8], 1\njmp short loc_11FB\nloc_11CC:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njge short loc_11F2\nmov eax, [rbp+var_4]\nsub eax, 1\nmov [rbp+var_C], eax\njmp short loc_11FB\nloc_11F2:\nmov eax, [rbp+var_4]\nadd eax, 1\nmov [rbp+var_10], eax\nloc_11FB:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_C]\njg short loc_1209\ncmp [rbp+var_8], 0\njz short loc_1194\nloc_1209:\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n int v4; // [rsp+10h] [rbp-10h]\n int v5; // [rsp+14h] [rbp-Ch]\n unsigned int v6; // [rsp+18h] [rbp-8h]\n int v7; // [rsp+1Ch] [rbp-4h]\n\n v4 = 0;\n v5 = a2 - 1;\n v6 = 0;\n while ( v4 <= v5 && !v6 )\n {\n v7 = (v4 + v5) / 2;\n if ( a3 == *(_DWORD *)(4LL * v7 + a1) )\n {\n v6 = 1;\n }\n else if ( a3 >= *(_DWORD *)(4LL * v7 + a1) )\n {\n v4 = v7 + 1;\n }\n else\n {\n v5 = v7 - 1;\n }\n }\n return v6;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_10], 0\nmov eax, [rbp+var_1C]\nsub eax, 1\nmov [rbp+var_C], eax\nmov [rbp+var_8], 0\njmp short loc_11FB\nloc_1194:\nmov edx, [rbp+var_10]\nmov eax, [rbp+var_C]\nadd eax, edx\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njnz short loc_11CC\nmov [rbp+var_8], 1\njmp short loc_11FB\nloc_11CC:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njge short loc_11F2\nmov eax, [rbp+var_4]\nsub eax, 1\nmov [rbp+var_C], eax\njmp short loc_11FB\nloc_11F2:\nmov eax, [rbp+var_4]\nadd eax, 1\nmov [rbp+var_10], eax\nloc_11FB:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_C]\njg short loc_1209\ncmp [rbp+var_8], 0\njz short loc_1194\nloc_1209:\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n int v4; // [rsp+10h] [rbp-10h]\n int v5; // [rsp+14h] [rbp-Ch]\n unsigned int v6; // [rsp+18h] [rbp-8h]\n int v7; // [rsp+1Ch] [rbp-4h]\n\n v4 = 0;\n v5 = a2 - 1;\n v6 = 0;\n while ( v4 <= v5 && !v6 )\n {\n v7 = (v4 + v5) / 2;\n if ( a3 == *(_DWORD *)(4LL * v7 + a1) )\n {\n v6 = 1;\n }\n else if ( a3 >= *(_DWORD *)(4LL * v7 + a1) )\n {\n v4 = v7 + 1;\n }\n else\n {\n v5 = v7 - 1;\n }\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n int v4;\n int v5;\n unsigned int v6;\n int v7;\n v4 = 0;\n v5 = a2 - 1;\n v6 = 0;\n while (v4 <= v5 && !v6) {\n v7 = (v4 + v5) / 2;\n if (a3 == *(uint32_t *)(4LL * v7 + a1)) {\n v6 = 1;\n } else if (a3 >= *(uint32_t *)(4LL * v7 + a1)) {\n v4 = v7 + 1;\n } else {\n v5 = v7 - 1;\n }\n }\n return v6;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n int v4;\n int v5;\n unsigned int v6;\n int v7;\n v4 = 0;\n v5 = a2 - 1;\n v6 = 0;\n while (v4 <= v5 && !v6) {\n v7 = (v4 + v5) / 2;\n if (a3 == *(uint32_t *)(4LL * v7 + a1)) {\n v6 = 1;\n } else if (a3 >= *(uint32_t *)(4LL * v7 + a1)) {\n v4 = v7 + 1;\n } else {\n v5 = v7 - 1;\n }\n }\n return v6;\n}" + }, + { + "index": 492, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int item_list[], int size, int item) {\n int first = 0;\n int last = size - 1;\n int found = 0;\n while (first <= last && !found) {\n int mid = (first + last) / 2;\n if (item_list[mid] == item) {\n found = 1;\n } else {\n if (item < item_list[mid]) {\n last = mid - 1;\n } else {\n first = mid + 1;\n }\n }\n }\n return found;\n}", + "test": "int main() {\n\n int list1[] = {1, 2, 3, 5, 8};\n\n int size1 = sizeof(list1) / sizeof(list1[0]);\n\n int list2[] = {7, 8, 9, 10, 13};\n\n int size2 = sizeof(list2) / sizeof(list2[0]);\n\n int list3[] = {11, 13, 14, 19, 22, 36};\n\n int size3 = sizeof(list3) / sizeof(list3[0]);\n\n\n\n assert(func0(list1, size1, 6) == 0);\n\n assert(func0(list2, size2, 10) == 1);\n\n assert(func0(list3, size3, 23) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nsub $0x1,%esi\nmov $0x0,%r8d\nmov $0x0,%ebx\nmov $0x1,%r10d\nlea (%r8,%rsi,1),%eax\nmov %eax,%r11d\nshr $0x1f,%r11d\nadd %eax,%r11d\nsar %r11d\nmovslq %r11d,%rax\nlea (%rdi,%rax,4),%r9\nmov %ebx,%eax\ncmp %esi,%r8d\njg 11bd \ntest %eax,%eax\njne 11bd \nmov (%r9),%ecx\nmov %r10d,%eax\ncmp %edx,%ecx\nje 119c \njle 11b7 \nlea -0x1(%r11),%esi\njmp 1182 \nlea 0x1(%r11),%r8d\njmp 1182 \npop %rbx\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov r11, rdi\nsub esi, 1\nmov edi, 0\nmov ebx, 0\nmov r9d, 1\nloc_1184:\nlea eax, [rdi+rsi]\nmov r10d, eax\nshr r10d, 1Fh\nadd r10d, eax\nsar r10d, 1\nmovsxd rax, r10d\nlea r8, [r11+rax*4]\nmov eax, ebx\nloc_119D:\ncmp edi, esi\njg short loc_11BD\ntest eax, eax\njnz short loc_11BD\nmov ecx, [r8]\nmov eax, r9d\ncmp ecx, edx\njz short loc_119D\njle short loc_11B7\nlea esi, [r10-1]\njmp short loc_1184\nloc_11B7:\nlea edi, [r10+1]\njmp short loc_1184\nloc_11BD:\npop rbx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n int v4; // esi\n int v5; // edi\n int v6; // r10d\n __int64 result; // rax\n int v8; // ecx\n\n v4 = a2 - 1;\n v5 = 0;\nLABEL_2:\n v6 = (v5 + v4) / 2;\n result = 0LL;\n while ( v5 <= v4 && !(_DWORD)result )\n {\n v8 = *(_DWORD *)(a1 + 4LL * v6);\n result = 1LL;\n if ( v8 != a3 )\n {\n if ( v8 <= a3 )\n v5 = v6 + 1;\n else\n v4 = v6 - 1;\n goto LABEL_2;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbx\nmov r11, rdi\nsub esi, 1\nmov edi, 0\nmov ebx, 0\nmov r9d, 1\nloc_1184:\nlea eax, [rdi+rsi]\nmov r10d, eax\nshr r10d, 1Fh\nadd r10d, eax\nsar r10d, 1\nmovsxd rax, r10d\nlea r8, [r11+rax*4]\nmov eax, ebx\nloc_119D:\ncmp edi, esi\njg short loc_11BD\ntest eax, eax\njnz short loc_11BD\nmov ecx, [r8]\nmov eax, r9d\ncmp ecx, edx\njz short loc_119D\njle short loc_11B7\nlea esi, [r10-1]\njmp short loc_1184\nloc_11B7:\nlea edi, [r10+1]\njmp short loc_1184\nloc_11BD:\npop rbx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n int v4; // esi\n int v5; // edi\n int v6; // r10d\n __int64 result; // rax\n int v8; // ecx\n\n v4 = a2 - 1;\n v5 = 0;\nLABEL_2:\n v6 = (v5 + v4) / 2;\n result = 0LL;\n while ( v5 <= v4 && !(_DWORD)result )\n {\n v8 = *(_DWORD *)(a1 + 4LL * v6);\n result = 1LL;\n if ( v8 != a3 )\n {\n if ( v8 <= a3 )\n v5 = v6 + 1;\n else\n v4 = v6 - 1;\n goto LABEL_2;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n int v4;\n int v5;\n int v6;\n long long result;\n int v8;\n v4 = a2 - 1;\n v5 = 0;\nLABEL_2:\n v6 = (v5 + v4) / 2;\n result = 0LL;\n while (v5 <= v4 && !(uint32_t)result) {\n v8 = *(uint32_t *)(a1 + 4LL * v6);\n result = 1LL;\n if (v8 != a3) {\n if (v8 <= a3)\n v5 = v6 + 1;\n else\n v4 = v6 - 1;\n goto LABEL_2;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n int v4;\n int v5;\n int v6;\n long long result;\n int v8;\n v4 = a2 - 1;\n v5 = 0;\nLABEL_2:\n v6 = (v5 + v4) / 2;\n result = 0LL;\n while (v5 <= v4 && !(uint32_t)result) {\n v8 = *(uint32_t *)(a1 + 4LL * v6);\n result = 1LL;\n if (v8 != a3) {\n if (v8 <= a3)\n v5 = v6 + 1;\n else\n v4 = v6 - 1;\n goto LABEL_2;\n }\n }\n return result;\n}" + }, + { + "index": 492, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int item_list[], int size, int item) {\n int first = 0;\n int last = size - 1;\n int found = 0;\n while (first <= last && !found) {\n int mid = (first + last) / 2;\n if (item_list[mid] == item) {\n found = 1;\n } else {\n if (item < item_list[mid]) {\n last = mid - 1;\n } else {\n first = mid + 1;\n }\n }\n }\n return found;\n}", + "test": "int main() {\n\n int list1[] = {1, 2, 3, 5, 8};\n\n int size1 = sizeof(list1) / sizeof(list1[0]);\n\n int list2[] = {7, 8, 9, 10, 13};\n\n int size2 = sizeof(list2) / sizeof(list2[0]);\n\n int list3[] = {11, 13, 14, 19, 22, 36};\n\n int size3 = sizeof(list3) / sizeof(list3[0]);\n\n\n\n assert(func0(list1, size1, 6) == 0);\n\n assert(func0(list2, size2, 10) == 1);\n\n assert(func0(list3, size3, 23) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nlea -0x1(%rsi),%r9d\nxor %r10d,%r10d\nlea (%r10,%r9,1),%r8d\nsar %r8d\ncmp %r10d,%r9d\nmovslq %r8d,%rax\nsetge %cl\nlea (%rdi,%rax,4),%rsi\nxor %eax,%eax\nnopl 0x0(%rax)\ntest %eax,%eax\njne 13b8 \ntest %cl,%cl\nje 13b8 \nmov $0x1,%eax\ncmp %edx,(%rsi)\nje 1398 \njle 13c0 \nlea -0x1(%r8),%r9d\njmp 137b \nnopl 0x0(%rax)\nretq\nnopl 0x0(%rax)\nlea 0x1(%r8),%r10d\njmp 137b \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nsub esi, 1\nxor r8d, r8d\nloc_129A:\nlea eax, [rsi+r8]\nmov ecx, eax\nshr ecx, 1Fh\nadd ecx, eax\nsar ecx, 1\nmovsxd rax, ecx\nlea rax, [rdi+rax*4]\ncmp r8d, esi\njg short loc_12D6\ncmp [rax], edx\njnz short loc_12C0\nmov eax, 1\nretn\nloc_12C0:\njle short loc_12D0\nlea esi, [rcx-1]\njmp short loc_129A\nloc_12D0:\nlea r8d, [rcx+1]\njmp short loc_129A\nloc_12D6:\nxor eax, eax\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n int v3; // esi\n int v4; // r8d\n int v5; // ecx\n _DWORD *v6; // rax\n\n v3 = a2 - 1;\n v4 = 0;\n while ( 1 )\n {\n v5 = (v3 + v4) / 2;\n v6 = (_DWORD *)(a1 + 4LL * v5);\n if ( v4 > v3 )\n break;\n if ( *v6 == a3 )\n return 1LL;\n if ( *v6 <= a3 )\n v4 = v5 + 1;\n else\n v3 = v5 - 1;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1290:\nendbr64\nsub esi, 1\nxor r8d, r8d\nloc_129A:\nlea eax, [rsi+r8]\nmov ecx, eax\nshr ecx, 1Fh\nadd ecx, eax\nsar ecx, 1\nmovsxd rax, ecx\nlea rax, [rdi+rax*4]\ncmp r8d, esi\njg short loc_12D6\ncmp [rax], edx\njnz short loc_12C0\nmov eax, 1\nretn\nloc_12C0:\njle short loc_12D0\nlea esi, [rcx-1]\njmp short loc_129A\nloc_12D0:\nlea r8d, [rcx+1]\njmp short loc_129A\nloc_12D6:\nxor eax, eax\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1290(__int64 a1, int a2, int a3)\n{\n int v3; // esi\n int v4; // r8d\n int v5; // ecx\n _DWORD *v6; // rax\n\n v3 = a2 - 1;\n v4 = 0;\n while ( 1 )\n {\n v5 = (v3 + v4) / 2;\n v6 = (_DWORD *)(a1 + 4LL * v5);\n if ( v4 > v3 )\n break;\n if ( *v6 == a3 )\n return 1LL;\n if ( *v6 <= a3 )\n v4 = v5 + 1;\n else\n v3 = v5 - 1;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1290(long long a1, int a2, int a3) {\n int v3;\n int v4;\n int v5;\n uint32_t *v6;\n v3 = a2 - 1;\n v4 = 0;\n while (1) {\n v5 = (v3 + v4) / 2;\n v6 = (uint32_t *)(a1 + 4LL * v5);\n if (v4 > v3) break;\n if (*v6 == a3) return 1LL;\n if (*v6 <= a3)\n v4 = v5 + 1;\n else\n v3 = v5 - 1;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n int v3;\n int v4;\n int v5;\n uint32_t *v6;\n v3 = a2 - 1;\n v4 = 0;\n while (1) {\n v5 = (v3 + v4) / 2;\n v6 = (uint32_t *)(a1 + 4LL * v5);\n if (v4 > v3) break;\n if (*v6 == a3) return 1LL;\n if (*v6 <= a3)\n v4 = v5 + 1;\n else\n v3 = v5 - 1;\n }\n return 0LL;\n}" + }, + { + "index": 493, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "double** func0(double startx, double starty, double endx, double endy,\n double radius) {\n double sl = (2 * radius) * tan(M_PI / 6);\n double p = sl * 0.5;\n double b = sl * cos(M_PI / 6);\n double w = b * 2;\n double h = 2 * sl;\n startx = startx - w;\n starty = starty - h;\n endx = endx + w;\n endy = endy + h;\n double origx = startx;\n double origy = starty;\n double xoffset = b;\n double yoffset = 3 * p;\n int index = 0;\n int polygons_size = 100;\n double** polygons = malloc(polygons_size * sizeof(double*));\n int row = 1;\n while (starty < endy) {\n if (row % 2 == 0) {\n startx = origx + xoffset;\n } else {\n startx = origx;\n }\n while (startx < endx) {\n double* poly = (double*)malloc(14 * sizeof(double));\n poly[0] = startx;\n poly[1] = starty + p;\n poly[2] = startx;\n poly[3] = starty + (3 * p);\n poly[4] = startx + b;\n poly[5] = starty + h;\n poly[6] = startx + w;\n poly[7] = starty + (3 * p);\n poly[8] = startx + w;\n poly[9] = starty + p;\n poly[10] = startx + b;\n poly[11] = starty;\n poly[12] = startx;\n poly[13] = starty + p;\n polygons[index++] = poly;\n startx += w;\n }\n starty += yoffset;\n row += 1;\n }\n return polygons;\n}", + "test": "int main() {\n\n double** res;\n\n\n\n // Tests would compare the structures generated, which would require setup of expected values;\n\n // for simplicity, I'm keeping the main just as a basic structure call.\n\n res = func0(1, 1, 4, 4, 3);\n\n // Assume a function `compare_polygons` to check if returned polygons are correct\n\n\n\n res = func0(5, 4, 7, 9, 8);\n\n // Assume a check\n\n\n\n res = func0(9, 6, 4, 3, 2);\n\n // Assume a check\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n return 0;\n\n}\n\n\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0xa0,%rsp\nmovsd %xmm0,-0x78(%rbp)\nmovsd %xmm1,-0x80(%rbp)\nmovsd %xmm2,-0x88(%rbp)\nmovsd %xmm3,-0x90(%rbp)\nmovsd %xmm4,-0x98(%rbp)\nmovsd -0x98(%rbp),%xmm0\nmovapd %xmm0,%xmm1\naddsd %xmm0,%xmm1\nmovsd 0xe76(%rip),%xmm0\nmulsd %xmm1,%xmm0\nmovsd %xmm0,-0x58(%rbp)\nmovsd -0x58(%rbp),%xmm1\nmovsd 0xe68(%rip),%xmm0\nmulsd %xmm1,%xmm0\nmovsd %xmm0,-0x50(%rbp)\nmovsd -0x58(%rbp),%xmm1\nmovsd 0xe5a(%rip),%xmm0\nmulsd %xmm1,%xmm0\nmovsd %xmm0,-0x48(%rbp)\nmovsd -0x48(%rbp),%xmm0\naddsd %xmm0,%xmm0\nmovsd %xmm0,-0x40(%rbp)\nmovsd -0x58(%rbp),%xmm0\naddsd %xmm0,%xmm0\nmovsd %xmm0,-0x38(%rbp)\nmovsd -0x78(%rbp),%xmm0\nsubsd -0x40(%rbp),%xmm0\nmovsd %xmm0,-0x78(%rbp)\nmovsd -0x80(%rbp),%xmm0\nsubsd -0x38(%rbp),%xmm0\nmovsd %xmm0,-0x80(%rbp)\nmovsd -0x88(%rbp),%xmm0\naddsd -0x40(%rbp),%xmm0\nmovsd %xmm0,-0x88(%rbp)\nmovsd -0x90(%rbp),%xmm0\naddsd -0x38(%rbp),%xmm0\nmovsd %xmm0,-0x90(%rbp)\nmovsd -0x78(%rbp),%xmm0\nmovsd %xmm0,-0x30(%rbp)\nmovsd -0x80(%rbp),%xmm0\nmovsd %xmm0,-0x28(%rbp)\nmovsd -0x48(%rbp),%xmm0\nmovsd %xmm0,-0x20(%rbp)\nmovsd -0x50(%rbp),%xmm1\nmovsd 0xdca(%rip),%xmm0\nmulsd %xmm1,%xmm0\nmovsd %xmm0,-0x18(%rbp)\nmovl $0x0,-0x64(%rbp)\nmovl $0x64,-0x5c(%rbp)\nmov -0x5c(%rbp),%eax\ncltq\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 1070 \nmov %rax,-0x10(%rbp)\nmovl $0x1,-0x60(%rbp)\njmpq 1473 \nmov -0x60(%rbp),%eax\nand $0x1,%eax\ntest %eax,%eax\njne 12cc \nmovsd -0x30(%rbp),%xmm0\naddsd -0x20(%rbp),%xmm0\nmovsd %xmm0,-0x78(%rbp)\njmpq 144d \nmovsd -0x30(%rbp),%xmm0\nmovsd %xmm0,-0x78(%rbp)\njmpq 144d \nmov $0x70,%edi\ncallq 1070 \nmov %rax,-0x8(%rbp)\nmov -0x8(%rbp),%rax\nmovsd -0x78(%rbp),%xmm0\nmovsd %xmm0,(%rax)\nmov -0x8(%rbp),%rax\nadd $0x8,%rax\nmovsd -0x80(%rbp),%xmm0\naddsd -0x50(%rbp),%xmm0\nmovsd %xmm0,(%rax)\nmov -0x8(%rbp),%rax\nadd $0x10,%rax\nmovsd -0x78(%rbp),%xmm0\nmovsd %xmm0,(%rax)\nmovsd -0x50(%rbp),%xmm1\nmovsd 0xd16(%rip),%xmm0\nmulsd %xmm1,%xmm0\nmov -0x8(%rbp),%rax\nadd $0x18,%rax\naddsd -0x80(%rbp),%xmm0\nmovsd %xmm0,(%rax)\nmov -0x8(%rbp),%rax\nadd $0x20,%rax\nmovsd -0x78(%rbp),%xmm0\naddsd -0x48(%rbp),%xmm0\nmovsd %xmm0,(%rax)\nmov -0x8(%rbp),%rax\nadd $0x28,%rax\nmovsd -0x80(%rbp),%xmm0\naddsd -0x38(%rbp),%xmm0\nmovsd %xmm0,(%rax)\nmov -0x8(%rbp),%rax\nadd $0x30,%rax\nmovsd -0x78(%rbp),%xmm0\naddsd -0x40(%rbp),%xmm0\nmovsd %xmm0,(%rax)\nmovsd -0x50(%rbp),%xmm1\nmovsd 0xcb2(%rip),%xmm0\nmulsd %xmm1,%xmm0\nmov -0x8(%rbp),%rax\nadd $0x38,%rax\naddsd -0x80(%rbp),%xmm0\nmovsd %xmm0,(%rax)\nmov -0x8(%rbp),%rax\nadd $0x40,%rax\nmovsd -0x78(%rbp),%xmm0\naddsd -0x40(%rbp),%xmm0\nmovsd %xmm0,(%rax)\nmov -0x8(%rbp),%rax\nadd $0x48,%rax\nmovsd -0x80(%rbp),%xmm0\naddsd -0x50(%rbp),%xmm0\nmovsd %xmm0,(%rax)\nmov -0x8(%rbp),%rax\nadd $0x50,%rax\nmovsd -0x78(%rbp),%xmm0\naddsd -0x48(%rbp),%xmm0\nmovsd %xmm0,(%rax)\nmov -0x8(%rbp),%rax\nadd $0x58,%rax\nmovsd -0x80(%rbp),%xmm0\nmovsd %xmm0,(%rax)\nmov -0x8(%rbp),%rax\nadd $0x60,%rax\nmovsd -0x78(%rbp),%xmm0\nmovsd %xmm0,(%rax)\nmov -0x8(%rbp),%rax\nadd $0x68,%rax\nmovsd -0x80(%rbp),%xmm0\naddsd -0x50(%rbp),%xmm0\nmovsd %xmm0,(%rax)\nmov -0x64(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x64(%rbp)\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x10(%rbp),%rax\nadd %rax,%rdx\nmov -0x8(%rbp),%rax\nmov %rax,(%rdx)\nmovsd -0x78(%rbp),%xmm0\naddsd -0x40(%rbp),%xmm0\nmovsd %xmm0,-0x78(%rbp)\nmovsd -0x88(%rbp),%xmm0\ncomisd -0x78(%rbp),%xmm0\nja 12db \nmovsd -0x80(%rbp),%xmm0\naddsd -0x18(%rbp),%xmm0\nmovsd %xmm0,-0x80(%rbp)\naddl $0x1,-0x60(%rbp)\nmovsd -0x90(%rbp),%xmm0\ncomisd -0x80(%rbp),%xmm0\nja 12ae \nmov -0x10(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0A0h\nmovsd [rbp+var_78], xmm0\nmovsd [rbp+var_80], xmm1\nmovsd [rbp+var_88], xmm2\nmovsd [rbp+var_90], xmm3\nmovsd [rbp+var_98], xmm4\nmovsd xmm0, [rbp+var_98]\nmovapd xmm1, xmm0\naddsd xmm1, xmm0\nmovsd xmm0, cs:qword_2028\nmulsd xmm0, xmm1\nmovsd [rbp+var_58], xmm0\nmovsd xmm1, [rbp+var_58]\nmovsd xmm0, cs:qword_2030\nmulsd xmm0, xmm1\nmovsd [rbp+var_50], xmm0\nmovsd xmm1, [rbp+var_58]\nmovsd xmm0, cs:qword_2038\nmulsd xmm0, xmm1\nmovsd [rbp+var_48], xmm0\nmovsd xmm0, [rbp+var_48]\naddsd xmm0, xmm0\nmovsd [rbp+var_40], xmm0\nmovsd xmm0, [rbp+var_58]\naddsd xmm0, xmm0\nmovsd [rbp+var_38], xmm0\nmovsd xmm0, [rbp+var_78]\nsubsd xmm0, [rbp+var_40]\nmovsd [rbp+var_78], xmm0\nmovsd xmm0, [rbp+var_80]\nsubsd xmm0, [rbp+var_38]\nmovsd [rbp+var_80], xmm0\nmovsd xmm0, [rbp+var_88]\naddsd xmm0, [rbp+var_40]\nmovsd [rbp+var_88], xmm0\nmovsd xmm0, [rbp+var_90]\naddsd xmm0, [rbp+var_38]\nmovsd [rbp+var_90], xmm0\nmovsd xmm0, [rbp+var_78]\nmovsd [rbp+var_30], xmm0\nmovsd xmm0, [rbp+var_80]\nmovsd [rbp+var_28], xmm0\nmovsd xmm0, [rbp+var_48]\nmovsd [rbp+var_20], xmm0\nmovsd xmm1, [rbp+var_50]\nmovsd xmm0, cs:qword_2040\nmulsd xmm0, xmm1\nmovsd [rbp+var_18], xmm0\nmov [rbp+var_64], 0\nmov [rbp+var_5C], 64h ; 'd'\nmov eax, [rbp+var_5C]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_10], rax\nmov [rbp+var_60], 1\njmp loc_1473\nloc_12AE:\nmov eax, [rbp+var_60]\nand eax, 1\ntest eax, eax\njnz short loc_12CC\nmovsd xmm0, [rbp+var_30]\naddsd xmm0, [rbp+var_20]\nmovsd [rbp+var_78], xmm0\njmp loc_144D\nloc_12CC:\nmovsd xmm0, [rbp+var_30]\nmovsd [rbp+var_78], xmm0\njmp loc_144D\nloc_12DB:\nmov edi, 70h ; 'p'; size\ncall _malloc\nmov [rbp+var_8], rax\nmov rax, [rbp+var_8]\nmovsd xmm0, [rbp+var_78]\nmovsd qword ptr [rax], xmm0\nmov rax, [rbp+var_8]\nadd rax, 8\nmovsd xmm0, [rbp+var_80]\naddsd xmm0, [rbp+var_50]\nmovsd qword ptr [rax], xmm0\nmov rax, [rbp+var_8]\nadd rax, 10h\nmovsd xmm0, [rbp+var_78]\nmovsd qword ptr [rax], xmm0\nmovsd xmm1, [rbp+var_50]\nmovsd xmm0, cs:qword_2040\nmulsd xmm0, xmm1\nmov rax, [rbp+var_8]\nadd rax, 18h\naddsd xmm0, [rbp+var_80]\nmovsd qword ptr [rax], xmm0\nmov rax, [rbp+var_8]\nadd rax, 20h ; ' '\nmovsd xmm0, [rbp+var_78]\naddsd xmm0, [rbp+var_48]\nmovsd qword ptr [rax], xmm0\nmov rax, [rbp+var_8]\nadd rax, 28h ; '('\nmovsd xmm0, [rbp+var_80]\naddsd xmm0, [rbp+var_38]\nmovsd qword ptr [rax], xmm0\nmov rax, [rbp+var_8]\nadd rax, 30h ; '0'\nmovsd xmm0, [rbp+var_78]\naddsd xmm0, [rbp+var_40]\nmovsd qword ptr [rax], xmm0\nmovsd xmm1, [rbp+var_50]\nmovsd xmm0, cs:qword_2040\nmulsd xmm0, xmm1\nmov rax, [rbp+var_8]\nadd rax, 38h ; '8'\naddsd xmm0, [rbp+var_80]\nmovsd qword ptr [rax], xmm0\nmov rax, [rbp+var_8]\nadd rax, 40h ; '@'\nmovsd xmm0, [rbp+var_78]\naddsd xmm0, [rbp+var_40]\nmovsd qword ptr [rax], xmm0\nmov rax, [rbp+var_8]\nadd rax, 48h ; 'H'\nmovsd xmm0, [rbp+var_80]\naddsd xmm0, [rbp+var_50]\nmovsd qword ptr [rax], xmm0\nmov rax, [rbp+var_8]\nadd rax, 50h ; 'P'\nmovsd xmm0, [rbp+var_78]\naddsd xmm0, [rbp+var_48]\nmovsd qword ptr [rax], xmm0\nmov rax, [rbp+var_8]\nadd rax, 58h ; 'X'\nmovsd xmm0, [rbp+var_80]\nmovsd qword ptr [rax], xmm0\nmov rax, [rbp+var_8]\nadd rax, 60h ; '`'\nmovsd xmm0, [rbp+var_78]\nmovsd qword ptr [rax], xmm0\nmov rax, [rbp+var_8]\nadd rax, 68h ; 'h'\nmovsd xmm0, [rbp+var_80]\naddsd xmm0, [rbp+var_50]\nmovsd qword ptr [rax], xmm0\nmov eax, [rbp+var_64]\nlea edx, [rax+1]\nmov [rbp+var_64], edx\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_10]\nadd rdx, rax\nmov rax, [rbp+var_8]\nmov [rdx], rax\nmovsd xmm0, [rbp+var_78]\naddsd xmm0, [rbp+var_40]\nmovsd [rbp+var_78], xmm0\nloc_144D:\nmovsd xmm0, [rbp+var_88]\ncomisd xmm0, [rbp+var_78]\nja loc_12DB\nmovsd xmm0, [rbp+var_80]\naddsd xmm0, [rbp+var_18]\nmovsd [rbp+var_80], xmm0\nadd [rbp+var_60], 1\nloc_1473:\nmovsd xmm0, [rbp+var_90]\ncomisd xmm0, [rbp+var_80]\nja loc_12AE\nmov rax, [rbp+var_10]\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(double a1, double a2, double a3, double a4, double a5)\n{\n int v5; // eax\n double v7; // [rsp+20h] [rbp-80h]\n double v8; // [rsp+28h] [rbp-78h]\n int v9; // [rsp+3Ch] [rbp-64h]\n char v10; // [rsp+40h] [rbp-60h]\n double v11; // [rsp+50h] [rbp-50h]\n double v12; // [rsp+58h] [rbp-48h]\n double v13; // [rsp+60h] [rbp-40h]\n double v14; // [rsp+68h] [rbp-38h]\n _QWORD *v15; // [rsp+90h] [rbp-10h]\n double *v16; // [rsp+98h] [rbp-8h]\n\n v11 = 0.5 * (0.5773502691896257 * (a5 + a5));\n v12 = 0.8660254037844387 * (0.5773502691896257 * (a5 + a5));\n v13 = v12 + v12;\n v14 = 0.5773502691896257 * (a5 + a5) + 0.5773502691896257 * (a5 + a5);\n v7 = a2 - v14;\n v9 = 0;\n v15 = malloc(0x320uLL);\n v10 = 1;\n while ( a4 + v14 > v7 )\n {\n if ( (v10 & 1) != 0 )\n v8 = a1 - v13;\n else\n v8 = a1 - v13 + v12;\n while ( a3 + v13 > v8 )\n {\n v16 = (double *)malloc(0x70uLL);\n *v16 = v8;\n v16[1] = v7 + v11;\n v16[2] = v8;\n v16[3] = 3.0 * v11 + v7;\n v16[4] = v8 + v12;\n v16[5] = v7 + v14;\n v16[6] = v8 + v13;\n v16[7] = 3.0 * v11 + v7;\n v16[8] = v8 + v13;\n v16[9] = v7 + v11;\n v16[10] = v8 + v12;\n v16[11] = v7;\n v16[12] = v8;\n v16[13] = v7 + v11;\n v5 = v9++;\n v15[v5] = v16;\n v8 = v8 + v13;\n }\n v7 = v7 + 3.0 * v11;\n ++v10;\n }\n return v15;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0A0h\nmovsd [rbp+var_78], xmm0\nmovsd [rbp+var_80], xmm1\nmovsd [rbp+var_88], xmm2\nmovsd [rbp+var_90], xmm3\nmovsd [rbp+var_98], xmm4\nmovsd xmm0, [rbp+var_98]\nmovapd xmm1, xmm0\naddsd xmm1, xmm0\nmovsd xmm0, cs:qword_2028\nmulsd xmm0, xmm1\nmovsd [rbp+var_58], xmm0\nmovsd xmm1, [rbp+var_58]\nmovsd xmm0, cs:qword_2030\nmulsd xmm0, xmm1\nmovsd [rbp+var_50], xmm0\nmovsd xmm1, [rbp+var_58]\nmovsd xmm0, cs:qword_2038\nmulsd xmm0, xmm1\nmovsd [rbp+var_48], xmm0\nmovsd xmm0, [rbp+var_48]\naddsd xmm0, xmm0\nmovsd [rbp+var_40], xmm0\nmovsd xmm0, [rbp+var_58]\naddsd xmm0, xmm0\nmovsd [rbp+var_38], xmm0\nmovsd xmm0, [rbp+var_78]\nsubsd xmm0, [rbp+var_40]\nmovsd [rbp+var_78], xmm0\nmovsd xmm0, [rbp+var_80]\nsubsd xmm0, [rbp+var_38]\nmovsd [rbp+var_80], xmm0\nmovsd xmm0, [rbp+var_88]\naddsd xmm0, [rbp+var_40]\nmovsd [rbp+var_88], xmm0\nmovsd xmm0, [rbp+var_90]\naddsd xmm0, [rbp+var_38]\nmovsd [rbp+var_90], xmm0\nmovsd xmm0, [rbp+var_78]\nmovsd [rbp+var_30], xmm0\nmovsd xmm0, [rbp+var_80]\nmovsd [rbp+var_28], xmm0\nmovsd xmm0, [rbp+var_48]\nmovsd [rbp+var_20], xmm0\nmovsd xmm1, [rbp+var_50]\nmovsd xmm0, cs:qword_2040\nmulsd xmm0, xmm1\nmovsd [rbp+var_18], xmm0\nmov [rbp+var_64], 0\nmov [rbp+var_5C], 64h ; 'd'\nmov eax, [rbp+var_5C]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_10], rax\nmov [rbp+var_60], 1\njmp loc_1473\nloc_12AE:\nmov eax, [rbp+var_60]\nand eax, 1\ntest eax, eax\njnz short loc_12CC\nmovsd xmm0, [rbp+var_30]\naddsd xmm0, [rbp+var_20]\nmovsd [rbp+var_78], xmm0\njmp loc_144D\nloc_12CC:\nmovsd xmm0, [rbp+var_30]\nmovsd [rbp+var_78], xmm0\njmp loc_144D\nloc_12DB:\nmov edi, 70h ; 'p'; size\ncall _malloc\nmov [rbp+var_8], rax\nmov rax, [rbp+var_8]\nmovsd xmm0, [rbp+var_78]\nmovsd qword ptr [rax], xmm0\nmov rax, [rbp+var_8]\nadd rax, 8\nmovsd xmm0, [rbp+var_80]\naddsd xmm0, [rbp+var_50]\nmovsd qword ptr [rax], xmm0\nmov rax, [rbp+var_8]\nadd rax, 10h\nmovsd xmm0, [rbp+var_78]\nmovsd qword ptr [rax], xmm0\nmovsd xmm1, [rbp+var_50]\nmovsd xmm0, cs:qword_2040\nmulsd xmm0, xmm1\nmov rax, [rbp+var_8]\nadd rax, 18h\naddsd xmm0, [rbp+var_80]\nmovsd qword ptr [rax], xmm0\nmov rax, [rbp+var_8]\nadd rax, 20h ; ' '\nmovsd xmm0, [rbp+var_78]\naddsd xmm0, [rbp+var_48]\nmovsd qword ptr [rax], xmm0\nmov rax, [rbp+var_8]\nadd rax, 28h ; '('\nmovsd xmm0, [rbp+var_80]\naddsd xmm0, [rbp+var_38]\nmovsd qword ptr [rax], xmm0\nmov rax, [rbp+var_8]\nadd rax, 30h ; '0'\nmovsd xmm0, [rbp+var_78]\naddsd xmm0, [rbp+var_40]\nmovsd qword ptr [rax], xmm0\nmovsd xmm1, [rbp+var_50]\nmovsd xmm0, cs:qword_2040\nmulsd xmm0, xmm1\nmov rax, [rbp+var_8]\nadd rax, 38h ; '8'\naddsd xmm0, [rbp+var_80]\nmovsd qword ptr [rax], xmm0\nmov rax, [rbp+var_8]\nadd rax, 40h ; '@'\nmovsd xmm0, [rbp+var_78]\naddsd xmm0, [rbp+var_40]\nmovsd qword ptr [rax], xmm0\nmov rax, [rbp+var_8]\nadd rax, 48h ; 'H'\nmovsd xmm0, [rbp+var_80]\naddsd xmm0, [rbp+var_50]\nmovsd qword ptr [rax], xmm0\nmov rax, [rbp+var_8]\nadd rax, 50h ; 'P'\nmovsd xmm0, [rbp+var_78]\naddsd xmm0, [rbp+var_48]\nmovsd qword ptr [rax], xmm0\nmov rax, [rbp+var_8]\nadd rax, 58h ; 'X'\nmovsd xmm0, [rbp+var_80]\nmovsd qword ptr [rax], xmm0\nmov rax, [rbp+var_8]\nadd rax, 60h ; '`'\nmovsd xmm0, [rbp+var_78]\nmovsd qword ptr [rax], xmm0\nmov rax, [rbp+var_8]\nadd rax, 68h ; 'h'\nmovsd xmm0, [rbp+var_80]\naddsd xmm0, [rbp+var_50]\nmovsd qword ptr [rax], xmm0\nmov eax, [rbp+var_64]\nlea edx, [rax+1]\nmov [rbp+var_64], edx\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_10]\nadd rdx, rax\nmov rax, [rbp+var_8]\nmov [rdx], rax\nmovsd xmm0, [rbp+var_78]\naddsd xmm0, [rbp+var_40]\nmovsd [rbp+var_78], xmm0\nloc_144D:\nmovsd xmm0, [rbp+var_88]\ncomisd xmm0, [rbp+var_78]\nja loc_12DB\nmovsd xmm0, [rbp+var_80]\naddsd xmm0, [rbp+var_18]\nmovsd [rbp+var_80], xmm0\nadd [rbp+var_60], 1\nloc_1473:\nmovsd xmm0, [rbp+var_90]\ncomisd xmm0, [rbp+var_80]\nja loc_12AE\nmov rax, [rbp+var_10]\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1169(double a1, double a2, double a3, double a4, double a5)\n{\n int v5; // eax\n double v7; // [rsp+20h] [rbp-80h]\n double v8; // [rsp+28h] [rbp-78h]\n int v9; // [rsp+3Ch] [rbp-64h]\n char v10; // [rsp+40h] [rbp-60h]\n double v11; // [rsp+50h] [rbp-50h]\n double v12; // [rsp+58h] [rbp-48h]\n double v13; // [rsp+60h] [rbp-40h]\n double v14; // [rsp+68h] [rbp-38h]\n _QWORD *v15; // [rsp+90h] [rbp-10h]\n double *v16; // [rsp+98h] [rbp-8h]\n\n v11 = 0.5 * (0.5773502691896257 * (a5 + a5));\n v12 = 0.8660254037844387 * (0.5773502691896257 * (a5 + a5));\n v13 = v12 + v12;\n v14 = 0.5773502691896257 * (a5 + a5) + 0.5773502691896257 * (a5 + a5);\n v7 = a2 - v14;\n v9 = 0;\n v15 = malloc(0x320uLL);\n v10 = 1;\n while ( a4 + v14 > v7 )\n {\n if ( (v10 & 1) != 0 )\n v8 = a1 - v13;\n else\n v8 = a1 - v13 + v12;\n while ( a3 + v13 > v8 )\n {\n v16 = (double *)malloc(0x70uLL);\n *v16 = v8;\n v16[1] = v7 + v11;\n v16[2] = v8;\n v16[3] = 3.0 * v11 + v7;\n v16[4] = v8 + v12;\n v16[5] = v7 + v14;\n v16[6] = v8 + v13;\n v16[7] = 3.0 * v11 + v7;\n v16[8] = v8 + v13;\n v16[9] = v7 + v11;\n v16[10] = v8 + v12;\n v16[11] = v7;\n v16[12] = v8;\n v16[13] = v7 + v11;\n v5 = v9++;\n v15[v5] = v16;\n v8 = v8 + v13;\n }\n v7 = v7 + 3.0 * v11;\n ++v10;\n }\n return v15;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1169(double a1, double a2, double a3, double a4, double a5) {\n int v5;\n double v7;\n double v8;\n int v9;\n char v10;\n double v11;\n double v12;\n double v13;\n double v14;\n uint64_t *v15;\n double *v16;\n v11 = 0.5 * (0.5773502691896257 * (a5 + a5));\n v12 = 0.8660254037844387 * (0.5773502691896257 * (a5 + a5));\n v13 = v12 + v12;\n v14 = 0.5773502691896257 * (a5 + a5) + 0.5773502691896257 * (a5 + a5);\n v7 = a2 - v14;\n v9 = 0;\n v15 = malloc(800uLL);\n v10 = 1;\n while (a4 + v14 > v7) {\n if ((v10 & 1) != 0)\n v8 = a1 - v13;\n else\n v8 = a1 - v13 + v12;\n while (a3 + v13 > v8) {\n v16 = (double *)malloc(112uLL);\n *v16 = v8;\n v16[1] = v7 + v11;\n v16[2] = v8;\n v16[3] = 3.0 * v11 + v7;\n v16[4] = v8 + v12;\n v16[5] = v7 + v14;\n v16[6] = v8 + v13;\n v16[7] = 3.0 * v11 + v7;\n v16[8] = v8 + v13;\n v16[9] = v7 + v11;\n v16[10] = v8 + v12;\n v16[11] = v7;\n v16[12] = v8;\n v16[13] = v7 + v11;\n v5 = v9++;\n v15[v5] = v16;\n v8 = v8 + v13;\n }\n v7 = v7 + 3.0 * v11;\n ++v10;\n }\n return v15;\n}", + "ida_pseudo_norm": "uint64_t *func0(double a1, double a2, double a3, double a4, double a5) {\n int v5;\n double v7;\n double v8;\n int v9;\n char v10;\n double v11;\n double v12;\n double v13;\n double v14;\n uint64_t *v15;\n double *v16;\n v11 = 0.5 * (0.5773502691896257 * (a5 + a5));\n v12 = 0.8660254037844387 * (0.5773502691896257 * (a5 + a5));\n v13 = v12 + v12;\n v14 = 0.5773502691896257 * (a5 + a5) + 0.5773502691896257 * (a5 + a5);\n v7 = a2 - v14;\n v9 = 0;\n v15 = malloc(800uLL);\n v10 = 1;\n while (a4 + v14 > v7) {\n if ((v10 & 1) != 0)\n v8 = a1 - v13;\n else\n v8 = a1 - v13 + v12;\n while (a3 + v13 > v8) {\n v16 = (double *)malloc(112uLL);\n *v16 = v8;\n v16[1] = v7 + v11;\n v16[2] = v8;\n v16[3] = 3.0 * v11 + v7;\n v16[4] = v8 + v12;\n v16[5] = v7 + v14;\n v16[6] = v8 + v13;\n v16[7] = 3.0 * v11 + v7;\n v16[8] = v8 + v13;\n v16[9] = v7 + v11;\n v16[10] = v8 + v12;\n v16[11] = v7;\n v16[12] = v8;\n v16[13] = v7 + v11;\n v5 = v9++;\n v15[v5] = v16;\n v8 = v8 + v13;\n }\n v7 = v7 + 3.0 * v11;\n ++v10;\n }\n return v15;\n}" + }, + { + "index": 493, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "double** func0(double startx, double starty, double endx, double endy,\n double radius) {\n double sl = (2 * radius) * tan(M_PI / 6);\n double p = sl * 0.5;\n double b = sl * cos(M_PI / 6);\n double w = b * 2;\n double h = 2 * sl;\n startx = startx - w;\n starty = starty - h;\n endx = endx + w;\n endy = endy + h;\n double origx = startx;\n double origy = starty;\n double xoffset = b;\n double yoffset = 3 * p;\n int index = 0;\n int polygons_size = 100;\n double** polygons = malloc(polygons_size * sizeof(double*));\n int row = 1;\n while (starty < endy) {\n if (row % 2 == 0) {\n startx = origx + xoffset;\n } else {\n startx = origx;\n }\n while (startx < endx) {\n double* poly = (double*)malloc(14 * sizeof(double));\n poly[0] = startx;\n poly[1] = starty + p;\n poly[2] = startx;\n poly[3] = starty + (3 * p);\n poly[4] = startx + b;\n poly[5] = starty + h;\n poly[6] = startx + w;\n poly[7] = starty + (3 * p);\n poly[8] = startx + w;\n poly[9] = starty + p;\n poly[10] = startx + b;\n poly[11] = starty;\n poly[12] = startx;\n poly[13] = starty + p;\n polygons[index++] = poly;\n startx += w;\n }\n starty += yoffset;\n row += 1;\n }\n return polygons;\n}", + "test": "int main() {\n\n double** res;\n\n\n\n // Tests would compare the structures generated, which would require setup of expected values;\n\n // for simplicity, I'm keeping the main just as a basic structure call.\n\n res = func0(1, 1, 4, 4, 3);\n\n // Assume a function `compare_polygons` to check if returned polygons are correct\n\n\n\n res = func0(5, 4, 7, 9, 8);\n\n // Assume a check\n\n\n\n res = func0(9, 6, 4, 3, 2);\n\n // Assume a check\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n return 0;\n\n}\n\n\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x58,%rsp\naddsd %xmm4,%xmm4\nmulsd 0xea5(%rip),%xmm4\nmovapd %xmm4,%xmm5\nmulsd 0xea1(%rip),%xmm5\nmovsd %xmm5,0x28(%rsp)\nmovapd %xmm4,%xmm6\nmulsd 0xe97(%rip),%xmm6\nmovsd %xmm6,0x20(%rsp)\naddsd %xmm6,%xmm6\nmovsd %xmm6,0x30(%rsp)\naddsd %xmm4,%xmm4\nmovsd %xmm4,0x38(%rsp)\nsubsd %xmm6,%xmm0\nmovsd %xmm0,0x48(%rsp)\nsubsd %xmm4,%xmm1\nmovsd %xmm1,0x8(%rsp)\naddsd %xmm6,%xmm2\nmovsd %xmm2,0x10(%rsp)\naddsd %xmm4,%xmm3\nmovsd %xmm3,0x40(%rsp)\nmulsd 0xe55(%rip),%xmm5\nmovsd %xmm5,0x18(%rsp)\nmov $0x320,%edi\ncallq 1070 \nmov %rax,%r12\nmov 0x48(%rsp),%rbx\nmov $0x1,%r13d\nmov $0x0,%edx\nmovsd 0x40(%rsp),%xmm3\ncomisd 0x8(%rsp),%xmm3\njbe 1337 \nlea 0x1(%rdx),%ebp\nmovslq %ebp,%rbp\nmovsd 0x10(%rsp),%xmm7\nmovq %rbx,%xmm1\ncomisd %xmm1,%xmm7\njbe 12ec \nmov $0x70,%edi\ncallq 1070 \nmov %rbx,(%rax)\nmovsd 0x8(%rsp),%xmm5\nmovapd %xmm5,%xmm0\naddsd 0x28(%rsp),%xmm0\nmovsd %xmm0,0x8(%rax)\nmov %rbx,0x10(%rax)\nmovapd %xmm5,%xmm2\naddsd 0x18(%rsp),%xmm2\nmovsd %xmm2,0x18(%rax)\nmovq %rbx,%xmm1\naddsd 0x20(%rsp),%xmm1\nmovsd %xmm1,0x20(%rax)\nmovapd %xmm5,%xmm3\naddsd 0x38(%rsp),%xmm3\nmovsd %xmm3,0x28(%rax)\nmovq %rbx,%xmm3\nmovq %rbx,%xmm6\naddsd 0x30(%rsp),%xmm6\nmovq %xmm6,%rbx\nmovsd %xmm6,0x30(%rax)\nmovsd %xmm2,0x38(%rax)\nmovsd %xmm6,0x40(%rax)\nmovsd %xmm0,0x48(%rax)\nmovsd %xmm1,0x50(%rax)\nmovsd %xmm5,0x58(%rax)\nmovsd %xmm3,0x60(%rax)\nmovsd %xmm0,0x68(%rax)\nmov %ebp,%edx\nmov %rax,-0x8(%r12,%rbp,8)\nadd $0x1,%rbp\nmovsd 0x10(%rsp),%xmm6\nmovq %rbx,%xmm4\ncomisd %xmm4,%xmm6\nja 123b \nmovsd 0x8(%rsp),%xmm6\naddsd 0x18(%rsp),%xmm6\nmovsd %xmm6,0x8(%rsp)\nadd $0x1,%r13d\nmovsd 0x40(%rsp),%xmm4\ncomisd %xmm6,%xmm4\njbe 1337 \nmovsd 0x48(%rsp),%xmm6\nmovq %xmm6,%rbx\ntest $0x1,%r13b\njne 1220 \nmovsd 0x20(%rsp),%xmm7\naddsd %xmm6,%xmm7\nmovq %xmm7,%rbx\njmpq 1220 \nmov %r12,%rax\nadd $0x58,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 48h\naddsd xmm4, xmm4\nmulsd xmm4, cs:qword_2028\nmovapd xmm5, xmm4\nmulsd xmm5, cs:qword_2030\nmovsd [rsp+78h+var_60], xmm5\nmovapd xmm7, xmm4\nmulsd xmm7, cs:qword_2038\nmovsd [rsp+78h+var_68], xmm7\naddsd xmm7, xmm7\nmovsd [rsp+78h+var_58], xmm7\naddsd xmm4, xmm4\nmovsd [rsp+78h+var_50], xmm4\nsubsd xmm0, xmm7\nmovsd [rsp+78h+var_40], xmm0\nsubsd xmm1, xmm4\nmovq rbp, xmm1\naddsd xmm2, xmm7\nmovq r15, xmm2\naddsd xmm3, xmm4\nmovsd [rsp+78h+var_48], xmm3\nmulsd xmm5, cs:qword_2040\nmovsd [rsp+78h+var_70], xmm5\nmov edi, 320h; size\ncall _malloc\nmov r13, rax\nmov r14d, 1\nmov eax, 0\nmovsd xmm3, [rsp+78h+var_48]\nmovq xmm6, rbp\ncomisd xmm3, xmm6\nja loc_1319\nloc_1220:\nmov rax, r13\nadd rsp, 48h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1232:\nlea r12d, [rax+1]\nmovsxd r12, r12d\nmovq xmm4, r15\nmovq xmm6, rbx\ncomisd xmm4, xmm6\njbe loc_12F5\nloc_124D:\nmov edi, 70h ; 'p'; size\ncall _malloc\nmov [rax], rbx\nmovq xmm0, rbp\naddsd xmm0, [rsp+78h+var_60]\nmovsd qword ptr [rax+8], xmm0\nmov [rax+10h], rbx\nmovq xmm2, rbp\naddsd xmm2, [rsp+78h+var_70]\nmovsd qword ptr [rax+18h], xmm2\nmovq xmm1, rbx\naddsd xmm1, [rsp+78h+var_68]\nmovsd qword ptr [rax+20h], xmm1\nmovq xmm3, rbp\naddsd xmm3, [rsp+78h+var_50]\nmovsd qword ptr [rax+28h], xmm3\nmovq xmm3, rbx\nmovq xmm5, rbx\naddsd xmm5, [rsp+78h+var_58]\nmovq rbx, xmm5\nmovsd qword ptr [rax+30h], xmm5\nmovsd qword ptr [rax+38h], xmm2\nmovsd qword ptr [rax+40h], xmm5\nmovsd qword ptr [rax+48h], xmm0\nmovsd qword ptr [rax+50h], xmm1\nmov [rax+58h], rbp\nmovsd qword ptr [rax+60h], xmm3\nmovsd qword ptr [rax+68h], xmm0\nmov [r13+r12*8-8], rax\nmov rax, r12\nadd r12, 1\nmovq xmm4, r15\ncomisd xmm4, xmm5\nja loc_124D\nloc_12F5:\nmovq xmm6, rbp\naddsd xmm6, [rsp+78h+var_70]\nmovq rbp, xmm6\nadd r14d, 1\nmovsd xmm7, [rsp+78h+var_48]\ncomisd xmm7, xmm6\njbe loc_1220\nloc_1319:\nmovsd xmm7, [rsp+78h+var_40]\nmovq rbx, xmm7\ntest r14b, 1\njnz loc_1232\nmovsd xmm4, [rsp+78h+var_68]\naddsd xmm4, xmm7\nmovq rbx, xmm4\njmp loc_1232", + "ida_pseudo": "_QWORD *__fastcall func0(double a1, double a2, double a3, double a4, double a5)\n{\n double v5; // xmm4_8\n double v6; // rbp\n double v7; // r15\n _QWORD *v8; // r13\n char v9; // r14\n int i; // eax\n __int64 j; // r12\n double *v13; // rax\n double v14; // xmm1_8\n double v15; // xmm3_8\n double v16; // rbx\n double v17; // [rsp+8h] [rbp-70h]\n double v18; // [rsp+10h] [rbp-68h]\n double v19; // [rsp+18h] [rbp-60h]\n double v20; // [rsp+28h] [rbp-50h]\n double v21; // [rsp+30h] [rbp-48h]\n\n v5 = (a5 + a5) * 0.5773502691896257;\n v19 = v5 * 0.5;\n v18 = v5 * 0.8660254037844387;\n v20 = v5 + v5;\n v6 = a2 - (v5 + v5);\n v7 = a3 + v18 + v18;\n v21 = a4 + v5 + v5;\n v17 = v5 * 0.5 * 3.0;\n v8 = malloc(0x320uLL);\n v9 = 1;\n for ( i = 0; v21 > v6; ++v9 )\n {\n v16 = a1 - (v18 + v18);\n if ( (v9 & 1) == 0 )\n v16 = v18 + a1 - (v18 + v18);\n for ( j = i + 1; v7 > v16; ++j )\n {\n v13 = (double *)malloc(0x70uLL);\n *v13 = v16;\n v13[1] = v6 + v19;\n v13[2] = v16;\n v13[3] = v6 + v17;\n v14 = v16 + v18;\n v13[4] = v16 + v18;\n v13[5] = v6 + v20;\n v15 = v16;\n v16 = v16 + v18 + v18;\n v13[6] = v16;\n v13[7] = v6 + v17;\n v13[8] = v16;\n v13[9] = v6 + v19;\n v13[10] = v14;\n v13[11] = v6;\n v13[12] = v15;\n v13[13] = v6 + v19;\n v8[j - 1] = v13;\n i = j;\n }\n v6 = v6 + v17;\n }\n return v8;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 48h\naddsd xmm4, xmm4\nmulsd xmm4, cs:qword_2028\nmovapd xmm5, xmm4\nmulsd xmm5, cs:qword_2030\nmovsd [rsp+78h+var_60], xmm5\nmovapd xmm7, xmm4\nmulsd xmm7, cs:qword_2038\nmovsd [rsp+78h+var_68], xmm7\naddsd xmm7, xmm7\nmovsd [rsp+78h+var_58], xmm7\naddsd xmm4, xmm4\nmovsd [rsp+78h+var_50], xmm4\nsubsd xmm0, xmm7\nmovsd [rsp+78h+var_40], xmm0\nsubsd xmm1, xmm4\nmovq rbp, xmm1\naddsd xmm2, xmm7\nmovq r15, xmm2\naddsd xmm3, xmm4\nmovsd [rsp+78h+var_48], xmm3\nmulsd xmm5, cs:qword_2040\nmovsd [rsp+78h+var_70], xmm5\nmov edi, 320h; size\ncall _malloc\nmov r13, rax\nmov r14d, 1\nmov eax, 0\nmovsd xmm3, [rsp+78h+var_48]\nmovq xmm6, rbp\ncomisd xmm3, xmm6\nja loc_1319\nloc_1220:\nmov rax, r13\nadd rsp, 48h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1232:\nlea r12d, [rax+1]\nmovsxd r12, r12d\nmovq xmm4, r15\nmovq xmm6, rbx\ncomisd xmm4, xmm6\njbe loc_12F5\nloc_124D:\nmov edi, 70h ; 'p'; size\ncall _malloc\nmov [rax], rbx\nmovq xmm0, rbp\naddsd xmm0, [rsp+78h+var_60]\nmovsd qword ptr [rax+8], xmm0\nmov [rax+10h], rbx\nmovq xmm2, rbp\naddsd xmm2, [rsp+78h+var_70]\nmovsd qword ptr [rax+18h], xmm2\nmovq xmm1, rbx\naddsd xmm1, [rsp+78h+var_68]\nmovsd qword ptr [rax+20h], xmm1\nmovq xmm3, rbp\naddsd xmm3, [rsp+78h+var_50]\nmovsd qword ptr [rax+28h], xmm3\nmovq xmm3, rbx\nmovq xmm5, rbx\naddsd xmm5, [rsp+78h+var_58]\nmovq rbx, xmm5\nmovsd qword ptr [rax+30h], xmm5\nmovsd qword ptr [rax+38h], xmm2\nmovsd qword ptr [rax+40h], xmm5\nmovsd qword ptr [rax+48h], xmm0\nmovsd qword ptr [rax+50h], xmm1\nmov [rax+58h], rbp\nmovsd qword ptr [rax+60h], xmm3\nmovsd qword ptr [rax+68h], xmm0\nmov [r13+r12*8-8], rax\nmov rax, r12\nadd r12, 1\nmovq xmm4, r15\ncomisd xmm4, xmm5\nja loc_124D\nloc_12F5:\nmovq xmm6, rbp\naddsd xmm6, [rsp+78h+var_70]\nmovq rbp, xmm6\nadd r14d, 1\nmovsd xmm7, [rsp+78h+var_48]\ncomisd xmm7, xmm6\njbe loc_1220\nloc_1319:\nmovsd xmm7, [rsp+78h+var_40]\nmovq rbx, xmm7\ntest r14b, 1\njnz loc_1232\nmovsd xmm4, [rsp+78h+var_68]\naddsd xmm4, xmm7\nmovq rbx, xmm4\njmp loc_1232", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1169(double a1, double a2, double a3, double a4, double a5)\n{\n double v5; // xmm4_8\n double v6; // rbp\n double v7; // r15\n _QWORD *v8; // r13\n char v9; // r14\n int i; // eax\n __int64 j; // r12\n double *v13; // rax\n double v14; // xmm1_8\n double v15; // xmm3_8\n double v16; // rbx\n double v17; // [rsp+8h] [rbp-70h]\n double v18; // [rsp+10h] [rbp-68h]\n double v19; // [rsp+18h] [rbp-60h]\n double v20; // [rsp+28h] [rbp-50h]\n double v21; // [rsp+30h] [rbp-48h]\n\n v5 = (a5 + a5) * 0.5773502691896257;\n v19 = v5 * 0.5;\n v18 = v5 * 0.8660254037844387;\n v20 = v5 + v5;\n v6 = a2 - (v5 + v5);\n v7 = a3 + v18 + v18;\n v21 = a4 + v5 + v5;\n v17 = v5 * 0.5 * 3.0;\n v8 = malloc(0x320uLL);\n v9 = 1;\n for ( i = 0; v21 > v6; ++v9 )\n {\n v16 = a1 - (v18 + v18);\n if ( (v9 & 1) == 0 )\n v16 = v18 + a1 - (v18 + v18);\n for ( j = i + 1; v7 > v16; ++j )\n {\n v13 = (double *)malloc(0x70uLL);\n *v13 = v16;\n v13[1] = v6 + v19;\n v13[2] = v16;\n v13[3] = v6 + v17;\n v14 = v16 + v18;\n v13[4] = v16 + v18;\n v13[5] = v6 + v20;\n v15 = v16;\n v16 = v16 + v18 + v18;\n v13[6] = v16;\n v13[7] = v6 + v17;\n v13[8] = v16;\n v13[9] = v6 + v19;\n v13[10] = v14;\n v13[11] = v6;\n v13[12] = v15;\n v13[13] = v6 + v19;\n v8[j - 1] = v13;\n i = j;\n }\n v6 = v6 + v17;\n }\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1169(double a1, double a2, double a3, double a4, double a5) {\n double v5;\n double v6;\n double v7;\n uint64_t *v8;\n char v9;\n int i;\n long long j;\n double *v13;\n double v14;\n double v15;\n double v16;\n double v17;\n double v18;\n double v19;\n double v20;\n double v21;\n v5 = (a5 + a5) * 0.5773502691896257;\n v19 = v5 * 0.5;\n v18 = v5 * 0.8660254037844387;\n v20 = v5 + v5;\n v6 = a2 - (v5 + v5);\n v7 = a3 + v18 + v18;\n v21 = a4 + v5 + v5;\n v17 = v5 * 0.5 * 3.0;\n v8 = malloc(800uLL);\n v9 = 1;\n for (i = 0; v21 > v6; ++v9) {\n v16 = a1 - (v18 + v18);\n if ((v9 & 1) == 0) v16 = v18 + a1 - (v18 + v18);\n for (j = i + 1; v7 > v16; ++j) {\n v13 = (double *)malloc(112uLL);\n *v13 = v16;\n v13[1] = v6 + v19;\n v13[2] = v16;\n v13[3] = v6 + v17;\n v14 = v16 + v18;\n v13[4] = v16 + v18;\n v13[5] = v6 + v20;\n v15 = v16;\n v16 = v16 + v18 + v18;\n v13[6] = v16;\n v13[7] = v6 + v17;\n v13[8] = v16;\n v13[9] = v6 + v19;\n v13[10] = v14;\n v13[11] = v6;\n v13[12] = v15;\n v13[13] = v6 + v19;\n v8[j - 1] = v13;\n i = j;\n }\n v6 = v6 + v17;\n }\n return v8;\n}", + "ida_pseudo_norm": "uint64_t *func0(double a1, double a2, double a3, double a4, double a5) {\n double v5;\n double v6;\n double v7;\n uint64_t *v8;\n char v9;\n int i;\n long long j;\n double *v13;\n double v14;\n double v15;\n double v16;\n double v17;\n double v18;\n double v19;\n double v20;\n double v21;\n v5 = (a5 + a5) * 0.5773502691896257;\n v19 = v5 * 0.5;\n v18 = v5 * 0.8660254037844387;\n v20 = v5 + v5;\n v6 = a2 - (v5 + v5);\n v7 = a3 + v18 + v18;\n v21 = a4 + v5 + v5;\n v17 = v5 * 0.5 * 3.0;\n v8 = malloc(800uLL);\n v9 = 1;\n for (i = 0; v21 > v6; ++v9) {\n v16 = a1 - (v18 + v18);\n if ((v9 & 1) == 0) v16 = v18 + a1 - (v18 + v18);\n for (j = i + 1; v7 > v16; ++j) {\n v13 = (double *)malloc(112uLL);\n *v13 = v16;\n v13[1] = v6 + v19;\n v13[2] = v16;\n v13[3] = v6 + v17;\n v14 = v16 + v18;\n v13[4] = v16 + v18;\n v13[5] = v6 + v20;\n v15 = v16;\n v16 = v16 + v18 + v18;\n v13[6] = v16;\n v13[7] = v6 + v17;\n v13[8] = v16;\n v13[9] = v6 + v19;\n v13[10] = v14;\n v13[11] = v6;\n v13[12] = v15;\n v13[13] = v6 + v19;\n v8[j - 1] = v13;\n i = j;\n }\n v6 = v6 + v17;\n }\n return v8;\n}" + }, + { + "index": 493, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "double** func0(double startx, double starty, double endx, double endy,\n double radius) {\n double sl = (2 * radius) * tan(M_PI / 6);\n double p = sl * 0.5;\n double b = sl * cos(M_PI / 6);\n double w = b * 2;\n double h = 2 * sl;\n startx = startx - w;\n starty = starty - h;\n endx = endx + w;\n endy = endy + h;\n double origx = startx;\n double origy = starty;\n double xoffset = b;\n double yoffset = 3 * p;\n int index = 0;\n int polygons_size = 100;\n double** polygons = malloc(polygons_size * sizeof(double*));\n int row = 1;\n while (starty < endy) {\n if (row % 2 == 0) {\n startx = origx + xoffset;\n } else {\n startx = origx;\n }\n while (startx < endx) {\n double* poly = (double*)malloc(14 * sizeof(double));\n poly[0] = startx;\n poly[1] = starty + p;\n poly[2] = startx;\n poly[3] = starty + (3 * p);\n poly[4] = startx + b;\n poly[5] = starty + h;\n poly[6] = startx + w;\n poly[7] = starty + (3 * p);\n poly[8] = startx + w;\n poly[9] = starty + p;\n poly[10] = startx + b;\n poly[11] = starty;\n poly[12] = startx;\n poly[13] = starty + p;\n polygons[index++] = poly;\n startx += w;\n }\n starty += yoffset;\n row += 1;\n }\n return polygons;\n}", + "test": "int main() {\n\n double** res;\n\n\n\n // Tests would compare the structures generated, which would require setup of expected values;\n\n // for simplicity, I'm keeping the main just as a basic structure call.\n\n res = func0(1, 1, 4, 4, 3);\n\n // Assume a function `compare_polygons` to check if returned polygons are correct\n\n\n\n res = func0(5, 4, 7, 9, 8);\n\n // Assume a check\n\n\n\n res = func0(9, 6, 4, 3, 2);\n\n // Assume a check\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n return 0;\n\n}\n\n\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\naddsd %xmm4,%xmm4\nmov $0x320,%edi\npush %rbp\nmov $0x1,%ebp\npush %rbx\nsub $0x70,%rsp\nmovsd 0xde6(%rip),%xmm6\nmovsd 0xdd6(%rip),%xmm5\nmulsd 0xdc6(%rip),%xmm4\nmulsd %xmm4,%xmm6\nmulsd %xmm4,%xmm5\naddsd %xmm4,%xmm4\naddsd %xmm4,%xmm3\nsubsd %xmm4,%xmm1\nmovsd %xmm4,0x68(%rsp)\nmovsd %xmm6,0x30(%rsp)\naddsd %xmm6,%xmm6\nmovsd %xmm5,0x60(%rsp)\nmulsd 0xdac(%rip),%xmm5\nmovsd %xmm3,0x48(%rsp)\nsubsd %xmm6,%xmm0\naddsd %xmm6,%xmm2\nmovsd %xmm6,0x38(%rsp)\nmovsd %xmm1,0x18(%rsp)\nmovsd %xmm0,0x50(%rsp)\nmovsd %xmm2,0x20(%rsp)\nmovsd %xmm5,0x58(%rsp)\ncallq 1070 \nmovsd 0x48(%rsp),%xmm3\nxor %edx,%edx\ncomisd 0x18(%rsp),%xmm3\nmovsd 0x50(%rsp),%xmm0\nmov %rax,%r12\njbe 1440 \nmovsd 0x20(%rsp),%xmm4\ncomisd %xmm0,%xmm4\njbe 1423 \nnopw 0x0(%rax,%rax,1)\nmovsd 0x18(%rsp),%xmm6\nmovsd 0x60(%rsp),%xmm1\nlea 0x1(%rdx),%ebx\nmovsd 0x58(%rsp),%xmm3\nmovslq %ebx,%rbx\naddsd %xmm6,%xmm1\naddsd %xmm6,%xmm3\naddsd 0x68(%rsp),%xmm6\nmovsd %xmm3,0x40(%rsp)\nmovsd %xmm6,0x28(%rsp)\nnopw 0x0(%rax,%rax,1)\nmov $0x70,%edi\nmovsd %xmm3,0x10(%rsp)\nmovsd %xmm1,0x8(%rsp)\nmovsd %xmm0,(%rsp)\ncallq 1070 \nmovsd (%rsp),%xmm0\nmovsd 0x30(%rsp),%xmm2\nmov %ebx,%edx\nmovsd 0x28(%rsp),%xmm5\nmov %rax,-0x8(%r12,%rbx,8)\nadd $0x1,%rbx\naddsd %xmm0,%xmm2\nmovapd %xmm0,%xmm4\nmovsd %xmm0,(%rax)\nmovsd 0x8(%rsp),%xmm1\nmovsd %xmm0,0x10(%rax)\naddsd 0x38(%rsp),%xmm0\nmovsd 0x10(%rsp),%xmm3\nmovsd %xmm5,0x28(%rax)\nmovsd 0x20(%rsp),%xmm5\nmovsd 0x18(%rsp),%xmm7\nmovsd %xmm1,0x8(%rax)\ncomisd %xmm0,%xmm5\nmovsd %xmm3,0x18(%rax)\nmovsd %xmm2,0x20(%rax)\nmovsd %xmm0,0x30(%rax)\nmovsd %xmm3,0x38(%rax)\nmovsd %xmm0,0x40(%rax)\nmovsd %xmm1,0x48(%rax)\nmovsd %xmm2,0x50(%rax)\nmovsd %xmm7,0x58(%rax)\nmovsd %xmm4,0x60(%rax)\nmovsd %xmm1,0x68(%rax)\nja 1330 \nmovsd 0x48(%rsp),%xmm4\nadd $0x1,%ebp\ncomisd 0x40(%rsp),%xmm4\njbe 1440 \nmovsd 0x50(%rsp),%xmm7\nmovapd %xmm7,%xmm0\ntest $0x1,%bpl\njne 1407 \nmovsd 0x30(%rsp),%xmm0\naddsd %xmm7,%xmm0\nmovsd 0x40(%rsp),%xmm4\nmovsd %xmm4,0x18(%rsp)\nmovsd 0x20(%rsp),%xmm4\ncomisd %xmm0,%xmm4\nja 12f8 \nmovsd 0x18(%rsp),%xmm7\naddsd 0x58(%rsp),%xmm7\nmovsd %xmm7,0x40(%rsp)\njmp 13dc \nnopw 0x0(%rax,%rax,1)\nadd $0x70,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\naddsd xmm4, xmm4\nmov edi, 320h; size\npush r14\npush r12\npush rbp\npush rbx\nsub rsp, 60h\nmovsd xmm7, cs:qword_2038\nmovsd xmm5, cs:qword_2030\nmulsd xmm4, cs:qword_2028\nmulsd xmm7, xmm4\nmovapd xmm6, xmm4\nmulsd xmm5, xmm4\naddsd xmm6, xmm4\naddsd xmm3, xmm6\nsubsd xmm1, xmm6\nmovsd [rsp+88h+var_30], xmm6\nmovsd [rsp+88h+var_60], xmm7\naddsd xmm7, xmm7\nmovsd [rsp+88h+var_38], xmm5\nmulsd xmm5, cs:qword_2040\nmovsd [rsp+88h+var_50], xmm3\nsubsd xmm0, xmm7\naddsd xmm2, xmm7\nmovsd [rsp+88h+var_58], xmm7\nmovsd [rsp+88h+var_68], xmm1\nmovsd [rsp+88h+var_48], xmm0\nmovq r14, xmm2\nmovsd [rsp+88h+var_40], xmm5\ncall _malloc\nmovsd xmm3, [rsp+88h+var_50]\ncomisd xmm3, [rsp+88h+var_68]\nmov rbx, rax\njbe loc_13E2\nmov ebp, 1\nxor eax, eax\nnop dword ptr [rax+rax+00h]\nloc_12C8:\nmovsd xmm7, [rsp+88h+var_48]\nmovapd xmm0, xmm7\ntest bpl, 1\njnz short loc_12E2\nmovsd xmm0, [rsp+88h+var_60]\naddsd xmm0, xmm7\nloc_12E2:\nmovq xmm7, r14\ncomisd xmm7, xmm0\njbe loc_13F8\nmovsd xmm6, [rsp+88h+var_68]\nmovsd xmm7, [rsp+88h+var_30]\nadd eax, 1\nmovsd xmm4, [rsp+88h+var_38]\nmovsd xmm3, [rsp+88h+var_40]\nmovsxd r12, eax\naddsd xmm7, xmm6\naddsd xmm4, xmm6\naddsd xmm3, xmm6\nmovq r15, xmm7\nloc_1320:\nmov edi, 70h ; 'p'; size\nmovsd [rsp+88h+var_70], xmm3\nmovsd [rsp+88h+var_78], xmm4\nmovsd [rsp+88h+var_80], xmm0\ncall _malloc\nmovsd xmm0, [rsp+88h+var_80]\nmovsd xmm1, [rsp+88h+var_60]\nmovq xmm6, r15\nmovsd xmm3, [rsp+88h+var_70]\nmovsd xmm4, [rsp+88h+var_78]\nmovq xmm7, r14\nmov [rbx+r12*8-8], rax\naddsd xmm1, xmm0\nmovapd xmm5, xmm0\nmovapd xmm2, xmm0\nunpcklpd xmm5, xmm3\naddsd xmm0, [rsp+88h+var_58]\nunpcklpd xmm2, xmm4\nmovups xmmword ptr [rax+10h], xmm5\nmovapd xmm5, xmm1\nmovhpd xmm1, [rsp+88h+var_68]\nmovups xmmword ptr [rax], xmm2\nunpcklpd xmm5, xmm6\nmovups xmmword ptr [rax+50h], xmm1\nmovups xmmword ptr [rax+20h], xmm5\nmovapd xmm5, xmm0\nunpcklpd xmm5, xmm3\nmovups xmmword ptr [rax+60h], xmm2\nmovups xmmword ptr [rax+30h], xmm5\nmovapd xmm5, xmm0\nunpcklpd xmm5, xmm4\nmovups xmmword ptr [rax+40h], xmm5\nmov rax, r12\nadd r12, 1\ncomisd xmm7, xmm0\nja loc_1320\nmovsd [rsp+88h+var_68], xmm3\nloc_13CD:\nmovsd xmm7, [rsp+88h+var_50]\nadd ebp, 1\ncomisd xmm7, [rsp+88h+var_68]\nja loc_12C8\nloc_13E2:\nadd rsp, 60h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r14\npop r15\nretn\nloc_13F8:\nmovsd xmm7, [rsp+88h+var_68]\naddsd xmm7, [rsp+88h+var_40]\nmovsd [rsp+88h+var_68], xmm7\njmp short loc_13CD", + "ida_pseudo": "_QWORD *__fastcall func0(double a1, double a2, double a3, double a4, double a5)\n{\n double v5; // xmm4_8\n double v6; // r14\n _QWORD *v7; // rbx\n char v8; // bp\n int v9; // eax\n __m128d v10; // xmm0\n __int64 v11; // r12\n double v12; // xmm4_8\n double v13; // xmm3_8\n __m128d *v14; // rax\n __m128d v15; // xmm1\n __m128d v16; // xmm2\n __m128d v17; // xmm5\n double v19; // [rsp+0h] [rbp-80h]\n double v20; // [rsp+8h] [rbp-78h]\n double v21; // [rsp+18h] [rbp-68h]\n double v22; // [rsp+20h] [rbp-60h]\n double v23; // [rsp+28h] [rbp-58h]\n double v24; // [rsp+30h] [rbp-50h]\n double v25; // [rsp+38h] [rbp-48h]\n double v26; // [rsp+40h] [rbp-40h]\n double v27; // [rsp+48h] [rbp-38h]\n double v28; // [rsp+50h] [rbp-30h]\n\n v5 = (a5 + a5) * 0.5773502691896257;\n v28 = v5 + v5;\n v22 = 0.8660254037844387 * v5;\n v27 = 0.5 * v5;\n v24 = a4 + v5 + v5;\n v23 = v22 + v22;\n v21 = a2 - (v5 + v5);\n v25 = a1 - (v22 + v22);\n v6 = a3 + v22 + v22;\n v26 = 0.5 * v5 * 3.0;\n v7 = malloc(0x320uLL);\n if ( v24 > v21 )\n {\n v8 = 1;\n v9 = 0;\n do\n {\n v10.m128d_f64[0] = v25;\n if ( (v8 & 1) == 0 )\n v10.m128d_f64[0] = v22 + v25;\n if ( v6 <= v10.m128d_f64[0] )\n {\n v21 = v21 + v26;\n }\n else\n {\n v11 = v9 + 1;\n v12 = v27 + v21;\n v13 = v26 + v21;\n do\n {\n v20 = v12;\n v19 = v10.m128d_f64[0];\n v14 = (__m128d *)malloc(0x70uLL);\n v10 = (__m128d)*(unsigned __int64 *)&v10.m128d_f64[0];\n v15 = (__m128d)*(unsigned __int64 *)&v22;\n v12 = v20;\n v7[v11 - 1] = v14;\n v15.m128d_f64[0] = v22 + v10.m128d_f64[0];\n v10.m128d_f64[0] = v10.m128d_f64[0] + v23;\n v16 = _mm_unpacklo_pd((__m128d)*(unsigned __int64 *)&v19, (__m128d)*(unsigned __int64 *)&v20);\n v14[1] = _mm_unpacklo_pd((__m128d)*(unsigned __int64 *)&v19, (__m128d)*(unsigned __int64 *)&v13);\n v17 = v15;\n v15.m128d_f64[1] = v21;\n *v14 = v16;\n v14[5] = v15;\n v14[2] = _mm_unpacklo_pd(v17, (__m128d)COERCE_UNSIGNED_INT64(v28 + v21));\n v14[6] = v16;\n v14[3] = _mm_unpacklo_pd(v10, (__m128d)*(unsigned __int64 *)&v13);\n v14[4] = _mm_unpacklo_pd(v10, (__m128d)*(unsigned __int64 *)&v20);\n v9 = v11++;\n }\n while ( v6 > v19 + v23 );\n v21 = v26 + v21;\n }\n ++v8;\n }\n while ( v24 > v21 );\n }\n return v7;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush r15\naddsd xmm4, xmm4\nmov edi, 320h; size\npush r14\npush r12\npush rbp\npush rbx\nsub rsp, 60h\nmovsd xmm7, cs:qword_2038\nmovsd xmm5, cs:qword_2030\nmulsd xmm4, cs:qword_2028\nmulsd xmm7, xmm4\nmovapd xmm6, xmm4\nmulsd xmm5, xmm4\naddsd xmm6, xmm4\naddsd xmm3, xmm6\nsubsd xmm1, xmm6\nmovsd [rsp+88h+var_30], xmm6\nmovsd [rsp+88h+var_60], xmm7\naddsd xmm7, xmm7\nmovsd [rsp+88h+var_38], xmm5\nmulsd xmm5, cs:qword_2040\nmovsd [rsp+88h+var_50], xmm3\nsubsd xmm0, xmm7\naddsd xmm2, xmm7\nmovsd [rsp+88h+var_58], xmm7\nmovsd [rsp+88h+var_68], xmm1\nmovsd [rsp+88h+var_48], xmm0\nmovq r14, xmm2\nmovsd [rsp+88h+var_40], xmm5\ncall _malloc\nmovsd xmm3, [rsp+88h+var_50]\ncomisd xmm3, [rsp+88h+var_68]\nmov rbx, rax\njbe loc_13E2\nmov ebp, 1\nxor eax, eax\nnop dword ptr [rax+rax+00h]\nloc_12C8:\nmovsd xmm7, [rsp+88h+var_48]\nmovapd xmm0, xmm7\ntest bpl, 1\njnz short loc_12E2\nmovsd xmm0, [rsp+88h+var_60]\naddsd xmm0, xmm7\nloc_12E2:\nmovq xmm7, r14\ncomisd xmm7, xmm0\njbe loc_13F8\nmovsd xmm6, [rsp+88h+var_68]\nmovsd xmm7, [rsp+88h+var_30]\nadd eax, 1\nmovsd xmm4, [rsp+88h+var_38]\nmovsd xmm3, [rsp+88h+var_40]\nmovsxd r12, eax\naddsd xmm7, xmm6\naddsd xmm4, xmm6\naddsd xmm3, xmm6\nmovq r15, xmm7\nloc_1320:\nmov edi, 70h ; 'p'; size\nmovsd [rsp+88h+var_70], xmm3\nmovsd [rsp+88h+var_78], xmm4\nmovsd [rsp+88h+var_80], xmm0\ncall _malloc\nmovsd xmm0, [rsp+88h+var_80]\nmovsd xmm1, [rsp+88h+var_60]\nmovq xmm6, r15\nmovsd xmm3, [rsp+88h+var_70]\nmovsd xmm4, [rsp+88h+var_78]\nmovq xmm7, r14\nmov [rbx+r12*8-8], rax\naddsd xmm1, xmm0\nmovapd xmm5, xmm0\nmovapd xmm2, xmm0\nunpcklpd xmm5, xmm3\naddsd xmm0, [rsp+88h+var_58]\nunpcklpd xmm2, xmm4\nmovups xmmword ptr [rax+10h], xmm5\nmovapd xmm5, xmm1\nmovhpd xmm1, [rsp+88h+var_68]\nmovups xmmword ptr [rax], xmm2\nunpcklpd xmm5, xmm6\nmovups xmmword ptr [rax+50h], xmm1\nmovups xmmword ptr [rax+20h], xmm5\nmovapd xmm5, xmm0\nunpcklpd xmm5, xmm3\nmovups xmmword ptr [rax+60h], xmm2\nmovups xmmword ptr [rax+30h], xmm5\nmovapd xmm5, xmm0\nunpcklpd xmm5, xmm4\nmovups xmmword ptr [rax+40h], xmm5\nmov rax, r12\nadd r12, 1\ncomisd xmm7, xmm0\nja loc_1320\nmovsd [rsp+88h+var_68], xmm3\nloc_13CD:\nmovsd xmm7, [rsp+88h+var_50]\nadd ebp, 1\ncomisd xmm7, [rsp+88h+var_68]\nja loc_12C8\nloc_13E2:\nadd rsp, 60h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r14\npop r15\nretn\nloc_13F8:\nmovsd xmm7, [rsp+88h+var_68]\naddsd xmm7, [rsp+88h+var_40]\nmovsd [rsp+88h+var_68], xmm7\njmp short loc_13CD", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1210(double a1, double a2, double a3, double a4, double a5)\n{\n double v5; // xmm4_8\n double v6; // r14\n _QWORD *v7; // rbx\n char v8; // bp\n int v9; // eax\n __m128d v10; // xmm0\n __int64 v11; // r12\n double v12; // xmm4_8\n double v13; // xmm3_8\n __m128d *v14; // rax\n __m128d v15; // xmm1\n __m128d v16; // xmm2\n __m128d v17; // xmm5\n double v19; // [rsp+0h] [rbp-80h]\n double v20; // [rsp+8h] [rbp-78h]\n double v21; // [rsp+18h] [rbp-68h]\n double v22; // [rsp+20h] [rbp-60h]\n double v23; // [rsp+28h] [rbp-58h]\n double v24; // [rsp+30h] [rbp-50h]\n double v25; // [rsp+38h] [rbp-48h]\n double v26; // [rsp+40h] [rbp-40h]\n double v27; // [rsp+48h] [rbp-38h]\n double v28; // [rsp+50h] [rbp-30h]\n\n v5 = (a5 + a5) * 0.5773502691896257;\n v28 = v5 + v5;\n v22 = 0.8660254037844387 * v5;\n v27 = 0.5 * v5;\n v24 = a4 + v5 + v5;\n v23 = v22 + v22;\n v21 = a2 - (v5 + v5);\n v25 = a1 - (v22 + v22);\n v6 = a3 + v22 + v22;\n v26 = 0.5 * v5 * 3.0;\n v7 = malloc(0x320uLL);\n if ( v24 > v21 )\n {\n v8 = 1;\n v9 = 0;\n do\n {\n v10.m128d_f64[0] = v25;\n if ( (v8 & 1) == 0 )\n v10.m128d_f64[0] = v22 + v25;\n if ( v6 <= v10.m128d_f64[0] )\n {\n v21 = v21 + v26;\n }\n else\n {\n v11 = v9 + 1;\n v12 = v27 + v21;\n v13 = v26 + v21;\n do\n {\n v20 = v12;\n v19 = v10.m128d_f64[0];\n v14 = (__m128d *)malloc(0x70uLL);\n v10 = (__m128d)*(unsigned __int64 *)&v10.m128d_f64[0];\n v15 = (__m128d)*(unsigned __int64 *)&v22;\n v12 = v20;\n v7[v11 - 1] = v14;\n v15.m128d_f64[0] = v22 + v10.m128d_f64[0];\n v10.m128d_f64[0] = v10.m128d_f64[0] + v23;\n v16 = _mm_unpacklo_pd((__m128d)*(unsigned __int64 *)&v19, (__m128d)*(unsigned __int64 *)&v20);\n v14[1] = _mm_unpacklo_pd((__m128d)*(unsigned __int64 *)&v19, (__m128d)*(unsigned __int64 *)&v13);\n v17 = v15;\n v15.m128d_f64[1] = v21;\n *v14 = v16;\n v14[5] = v15;\n v14[2] = _mm_unpacklo_pd(v17, (__m128d)COERCE_UNSIGNED_INT64(v28 + v21));\n v14[6] = v16;\n v14[3] = _mm_unpacklo_pd(v10, (__m128d)*(unsigned __int64 *)&v13);\n v14[4] = _mm_unpacklo_pd(v10, (__m128d)*(unsigned __int64 *)&v20);\n v9 = v11++;\n }\n while ( v6 > v19 + v23 );\n v21 = v26 + v21;\n }\n ++v8;\n }\n while ( v24 > v21 );\n }\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1210(double a1, double a2, double a3, double a4, double a5) {\n double v5;\n double v6;\n uint64_t *v7;\n char v8;\n int v9;\n __m128d v10;\n long long v11;\n double v12;\n double v13;\n __m128d *v14;\n __m128d v15;\n __m128d v16;\n __m128d v17;\n double v19;\n double v20;\n double v21;\n double v22;\n double v23;\n double v24;\n double v25;\n double v26;\n double v27;\n double v28;\n v5 = (a5 + a5) * 0.5773502691896257;\n v28 = v5 + v5;\n v22 = 0.8660254037844387 * v5;\n v27 = 0.5 * v5;\n v24 = a4 + v5 + v5;\n v23 = v22 + v22;\n v21 = a2 - (v5 + v5);\n v25 = a1 - (v22 + v22);\n v6 = a3 + v22 + v22;\n v26 = 0.5 * v5 * 3.0;\n v7 = malloc(800uLL);\n if (v24 > v21) {\n v8 = 1;\n v9 = 0;\n do {\n v10.m128d_f64[0] = v25;\n if ((v8 & 1) == 0) v10.m128d_f64[0] = v22 + v25;\n if (v6 <= v10.m128d_f64[0]) {\n v21 = v21 + v26;\n } else {\n v11 = v9 + 1;\n v12 = v27 + v21;\n v13 = v26 + v21;\n do {\n v20 = v12;\n v19 = v10.m128d_f64[0];\n v14 = (__m128d *)malloc(112uLL);\n v10 = (__m128d) * (unsigned long long *)&v10.m128d_f64[0];\n v15 = (__m128d) * (unsigned long long *)&v22;\n v12 = v20;\n v7[v11 - 1] = v14;\n v15.m128d_f64[0] = v22 + v10.m128d_f64[0];\n v10.m128d_f64[0] = v10.m128d_f64[0] + v23;\n v16 = _mm_unpacklo_pd((__m128d) * (unsigned long long *)&v19,\n (__m128d) * (unsigned long long *)&v20);\n v14[1] = _mm_unpacklo_pd((__m128d) * (unsigned long long *)&v19,\n (__m128d) * (unsigned long long *)&v13);\n v17 = v15;\n v15.m128d_f64[1] = v21;\n *v14 = v16;\n v14[5] = v15;\n v14[2] =\n _mm_unpacklo_pd(v17, (__m128d)COERCE_UNSIGNED_INT64(v28 + v21));\n v14[6] = v16;\n v14[3] = _mm_unpacklo_pd(v10, (__m128d) * (unsigned long long *)&v13);\n v14[4] = _mm_unpacklo_pd(v10, (__m128d) * (unsigned long long *)&v20);\n v9 = v11++;\n } while (v6 > v19 + v23);\n v21 = v26 + v21;\n }\n ++v8;\n } while (v24 > v21);\n }\n return v7;\n}", + "ida_pseudo_norm": "uint64_t *func0(double a1, double a2, double a3, double a4, double a5) {\n double v5;\n double v6;\n uint64_t *v7;\n char v8;\n int v9;\n __m128d v10;\n long long v11;\n double v12;\n double v13;\n __m128d *v14;\n __m128d v15;\n __m128d v16;\n __m128d v17;\n double v19;\n double v20;\n double v21;\n double v22;\n double v23;\n double v24;\n double v25;\n double v26;\n double v27;\n double v28;\n v5 = (a5 + a5) * 0.5773502691896257;\n v28 = v5 + v5;\n v22 = 0.8660254037844387 * v5;\n v27 = 0.5 * v5;\n v24 = a4 + v5 + v5;\n v23 = v22 + v22;\n v21 = a2 - (v5 + v5);\n v25 = a1 - (v22 + v22);\n v6 = a3 + v22 + v22;\n v26 = 0.5 * v5 * 3.0;\n v7 = malloc(800uLL);\n if (v24 > v21) {\n v8 = 1;\n v9 = 0;\n do {\n v10.m128d_f64[0] = v25;\n if ((v8 & 1) == 0) v10.m128d_f64[0] = v22 + v25;\n if (v6 <= v10.m128d_f64[0]) {\n v21 = v21 + v26;\n } else {\n v11 = v9 + 1;\n v12 = v27 + v21;\n v13 = v26 + v21;\n do {\n v20 = v12;\n v19 = v10.m128d_f64[0];\n v14 = (__m128d *)malloc(112uLL);\n v10 = (__m128d) * (unsigned long long *)&v10.m128d_f64[0];\n v15 = (__m128d) * (unsigned long long *)&v22;\n v12 = v20;\n v7[v11 - 1] = v14;\n v15.m128d_f64[0] = v22 + v10.m128d_f64[0];\n v10.m128d_f64[0] = v10.m128d_f64[0] + v23;\n v16 = _mm_unpacklo_pd((__m128d) * (unsigned long long *)&v19,\n (__m128d) * (unsigned long long *)&v20);\n v14[1] = _mm_unpacklo_pd((__m128d) * (unsigned long long *)&v19,\n (__m128d) * (unsigned long long *)&v13);\n v17 = v15;\n v15.m128d_f64[1] = v21;\n *v14 = v16;\n v14[5] = v15;\n v14[2] =\n _mm_unpacklo_pd(v17, (__m128d)COERCE_UNSIGNED_INT64(v28 + v21));\n v14[6] = v16;\n v14[3] = _mm_unpacklo_pd(v10, (__m128d) * (unsigned long long *)&v13);\n v14[4] = _mm_unpacklo_pd(v10, (__m128d) * (unsigned long long *)&v20);\n v9 = v11++;\n } while (v6 > v19 + v23);\n v21 = v26 + v21;\n }\n ++v8;\n } while (v24 > v21);\n }\n return v7;\n}" + }, + { + "index": 493, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "double** func0(double startx, double starty, double endx, double endy,\n double radius) {\n double sl = (2 * radius) * tan(M_PI / 6);\n double p = sl * 0.5;\n double b = sl * cos(M_PI / 6);\n double w = b * 2;\n double h = 2 * sl;\n startx = startx - w;\n starty = starty - h;\n endx = endx + w;\n endy = endy + h;\n double origx = startx;\n double origy = starty;\n double xoffset = b;\n double yoffset = 3 * p;\n int index = 0;\n int polygons_size = 100;\n double** polygons = malloc(polygons_size * sizeof(double*));\n int row = 1;\n while (starty < endy) {\n if (row % 2 == 0) {\n startx = origx + xoffset;\n } else {\n startx = origx;\n }\n while (startx < endx) {\n double* poly = (double*)malloc(14 * sizeof(double));\n poly[0] = startx;\n poly[1] = starty + p;\n poly[2] = startx;\n poly[3] = starty + (3 * p);\n poly[4] = startx + b;\n poly[5] = starty + h;\n poly[6] = startx + w;\n poly[7] = starty + (3 * p);\n poly[8] = startx + w;\n poly[9] = starty + p;\n poly[10] = startx + b;\n poly[11] = starty;\n poly[12] = startx;\n poly[13] = starty + p;\n polygons[index++] = poly;\n startx += w;\n }\n starty += yoffset;\n row += 1;\n }\n return polygons;\n}", + "test": "int main() {\n\n double** res;\n\n\n\n // Tests would compare the structures generated, which would require setup of expected values;\n\n // for simplicity, I'm keeping the main just as a basic structure call.\n\n res = func0(1, 1, 4, 4, 3);\n\n // Assume a function `compare_polygons` to check if returned polygons are correct\n\n\n\n res = func0(5, 4, 7, 9, 8);\n\n // Assume a check\n\n\n\n res = func0(9, 6, 4, 3, 2);\n\n // Assume a check\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n return 0;\n\n}\n\n\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\naddsd %xmm4,%xmm4\nmov $0x320,%edi\npush %rbp\nmov $0x1,%ebp\npush %rbx\nsub $0x70,%rsp\nmovsd 0xde6(%rip),%xmm6\nmovsd 0xdd6(%rip),%xmm5\nmulsd 0xdc6(%rip),%xmm4\nmulsd %xmm4,%xmm6\nmulsd %xmm4,%xmm5\naddsd %xmm4,%xmm4\naddsd %xmm4,%xmm3\nsubsd %xmm4,%xmm1\nmovsd %xmm4,0x68(%rsp)\nmovsd %xmm6,0x30(%rsp)\naddsd %xmm6,%xmm6\nmovsd %xmm5,0x60(%rsp)\nmulsd 0xdac(%rip),%xmm5\nmovsd %xmm3,0x48(%rsp)\nsubsd %xmm6,%xmm0\naddsd %xmm6,%xmm2\nmovsd %xmm6,0x38(%rsp)\nmovsd %xmm1,0x18(%rsp)\nmovsd %xmm0,0x50(%rsp)\nmovsd %xmm2,0x20(%rsp)\nmovsd %xmm5,0x58(%rsp)\ncallq 1070 \nmovsd 0x48(%rsp),%xmm3\nxor %edx,%edx\ncomisd 0x18(%rsp),%xmm3\nmovsd 0x50(%rsp),%xmm0\nmov %rax,%r12\njbe 1440 \nmovsd 0x20(%rsp),%xmm4\ncomisd %xmm0,%xmm4\njbe 1423 \nnopw 0x0(%rax,%rax,1)\nmovsd 0x18(%rsp),%xmm6\nmovsd 0x60(%rsp),%xmm1\nlea 0x1(%rdx),%ebx\nmovsd 0x58(%rsp),%xmm3\nmovslq %ebx,%rbx\naddsd %xmm6,%xmm1\naddsd %xmm6,%xmm3\naddsd 0x68(%rsp),%xmm6\nmovsd %xmm3,0x40(%rsp)\nmovsd %xmm6,0x28(%rsp)\nnopw 0x0(%rax,%rax,1)\nmov $0x70,%edi\nmovsd %xmm3,0x10(%rsp)\nmovsd %xmm1,0x8(%rsp)\nmovsd %xmm0,(%rsp)\ncallq 1070 \nmovsd (%rsp),%xmm0\nmovsd 0x30(%rsp),%xmm2\nmov %ebx,%edx\nmovsd 0x28(%rsp),%xmm5\nmov %rax,-0x8(%r12,%rbx,8)\nadd $0x1,%rbx\naddsd %xmm0,%xmm2\nmovapd %xmm0,%xmm4\nmovsd %xmm0,(%rax)\nmovsd 0x8(%rsp),%xmm1\nmovsd %xmm0,0x10(%rax)\naddsd 0x38(%rsp),%xmm0\nmovsd 0x10(%rsp),%xmm3\nmovsd %xmm5,0x28(%rax)\nmovsd 0x20(%rsp),%xmm5\nmovsd 0x18(%rsp),%xmm7\nmovsd %xmm1,0x8(%rax)\ncomisd %xmm0,%xmm5\nmovsd %xmm3,0x18(%rax)\nmovsd %xmm2,0x20(%rax)\nmovsd %xmm0,0x30(%rax)\nmovsd %xmm3,0x38(%rax)\nmovsd %xmm0,0x40(%rax)\nmovsd %xmm1,0x48(%rax)\nmovsd %xmm2,0x50(%rax)\nmovsd %xmm7,0x58(%rax)\nmovsd %xmm4,0x60(%rax)\nmovsd %xmm1,0x68(%rax)\nja 1330 \nmovsd 0x48(%rsp),%xmm4\nadd $0x1,%ebp\ncomisd 0x40(%rsp),%xmm4\njbe 1440 \nmovsd 0x50(%rsp),%xmm7\nmovapd %xmm7,%xmm0\ntest $0x1,%bpl\njne 1407 \nmovsd 0x30(%rsp),%xmm0\naddsd %xmm7,%xmm0\nmovsd 0x40(%rsp),%xmm4\nmovsd %xmm4,0x18(%rsp)\nmovsd 0x20(%rsp),%xmm4\ncomisd %xmm0,%xmm4\nja 12f8 \nmovsd 0x18(%rsp),%xmm7\naddsd 0x58(%rsp),%xmm7\nmovsd %xmm7,0x40(%rsp)\njmp 13dc \nnopw 0x0(%rax,%rax,1)\nadd $0x70,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\naddsd xmm4, xmm4\nmov edi, 320h; size\npush r14\npush r12\npush rbp\npush rbx\nsub rsp, 60h\nmovsd xmm7, cs:qword_2038\nmovsd xmm5, cs:qword_2030\nmulsd xmm4, cs:qword_2028\nmulsd xmm7, xmm4\nmovapd xmm6, xmm4\nmulsd xmm5, xmm4\naddsd xmm6, xmm4\naddsd xmm3, xmm6\nsubsd xmm1, xmm6\nmovsd [rsp+88h+var_30], xmm6\nmovsd [rsp+88h+var_60], xmm7\naddsd xmm7, xmm7\nmovsd [rsp+88h+var_38], xmm5\nmulsd xmm5, cs:qword_2040\nmovsd [rsp+88h+var_50], xmm3\nsubsd xmm0, xmm7\naddsd xmm2, xmm7\nmovsd [rsp+88h+var_58], xmm7\nmovsd [rsp+88h+var_68], xmm1\nmovsd [rsp+88h+var_48], xmm0\nmovq r14, xmm2\nmovsd [rsp+88h+var_40], xmm5\ncall _malloc\nmovsd xmm3, [rsp+88h+var_50]\ncomisd xmm3, [rsp+88h+var_68]\nmov rbx, rax\njbe loc_13E2\nmov ebp, 1\nxor eax, eax\nnop dword ptr [rax+rax+00h]\nloc_12C8:\nmovsd xmm7, [rsp+88h+var_48]\nmovapd xmm0, xmm7\ntest bpl, 1\njnz short loc_12E2\nmovsd xmm0, [rsp+88h+var_60]\naddsd xmm0, xmm7\nloc_12E2:\nmovq xmm7, r14\ncomisd xmm7, xmm0\njbe loc_13F8\nmovsd xmm6, [rsp+88h+var_68]\nmovsd xmm7, [rsp+88h+var_30]\nadd eax, 1\nmovsd xmm4, [rsp+88h+var_38]\nmovsd xmm3, [rsp+88h+var_40]\nmovsxd r12, eax\naddsd xmm7, xmm6\naddsd xmm4, xmm6\naddsd xmm3, xmm6\nmovq r15, xmm7\nloc_1320:\nmov edi, 70h ; 'p'; size\nmovsd [rsp+88h+var_70], xmm3\nmovsd [rsp+88h+var_78], xmm4\nmovsd [rsp+88h+var_80], xmm0\ncall _malloc\nmovsd xmm0, [rsp+88h+var_80]\nmovsd xmm1, [rsp+88h+var_60]\nmovq xmm6, r15\nmovsd xmm3, [rsp+88h+var_70]\nmovsd xmm4, [rsp+88h+var_78]\nmovq xmm7, r14\nmov [rbx+r12*8-8], rax\naddsd xmm1, xmm0\nmovapd xmm5, xmm0\nmovapd xmm2, xmm0\nunpcklpd xmm5, xmm3\naddsd xmm0, [rsp+88h+var_58]\nunpcklpd xmm2, xmm4\nmovups xmmword ptr [rax+10h], xmm5\nmovapd xmm5, xmm1\nmovhpd xmm1, [rsp+88h+var_68]\nmovups xmmword ptr [rax], xmm2\nunpcklpd xmm5, xmm6\nmovups xmmword ptr [rax+50h], xmm1\nmovups xmmword ptr [rax+20h], xmm5\nmovapd xmm5, xmm0\nunpcklpd xmm5, xmm3\nmovups xmmword ptr [rax+60h], xmm2\nmovups xmmword ptr [rax+30h], xmm5\nmovapd xmm5, xmm0\nunpcklpd xmm5, xmm4\nmovups xmmword ptr [rax+40h], xmm5\nmov rax, r12\nadd r12, 1\ncomisd xmm7, xmm0\nja loc_1320\nmovsd [rsp+88h+var_68], xmm3\nloc_13CD:\nmovsd xmm7, [rsp+88h+var_50]\nadd ebp, 1\ncomisd xmm7, [rsp+88h+var_68]\nja loc_12C8\nloc_13E2:\nadd rsp, 60h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r14\npop r15\nretn\nloc_13F8:\nmovsd xmm7, [rsp+88h+var_68]\naddsd xmm7, [rsp+88h+var_40]\nmovsd [rsp+88h+var_68], xmm7\njmp short loc_13CD", + "ida_pseudo": "_QWORD *__fastcall func0(double a1, double a2, double a3, double a4, double a5)\n{\n double v5; // xmm4_8\n double v6; // r14\n _QWORD *v7; // rbx\n char v8; // bp\n int v9; // eax\n __m128d v10; // xmm0\n __int64 v11; // r12\n double v12; // xmm4_8\n double v13; // xmm3_8\n __m128d *v14; // rax\n __m128d v15; // xmm1\n __m128d v16; // xmm2\n __m128d v17; // xmm5\n double v19; // [rsp+0h] [rbp-80h]\n double v20; // [rsp+8h] [rbp-78h]\n double v21; // [rsp+18h] [rbp-68h]\n double v22; // [rsp+20h] [rbp-60h]\n double v23; // [rsp+28h] [rbp-58h]\n double v24; // [rsp+30h] [rbp-50h]\n double v25; // [rsp+38h] [rbp-48h]\n double v26; // [rsp+40h] [rbp-40h]\n double v27; // [rsp+48h] [rbp-38h]\n double v28; // [rsp+50h] [rbp-30h]\n\n v5 = (a5 + a5) * 0.5773502691896257;\n v28 = v5 + v5;\n v22 = 0.8660254037844387 * v5;\n v27 = 0.5 * v5;\n v24 = a4 + v5 + v5;\n v23 = v22 + v22;\n v21 = a2 - (v5 + v5);\n v25 = a1 - (v22 + v22);\n v6 = a3 + v22 + v22;\n v26 = 0.5 * v5 * 3.0;\n v7 = malloc(0x320uLL);\n if ( v24 > v21 )\n {\n v8 = 1;\n v9 = 0;\n do\n {\n v10.m128d_f64[0] = v25;\n if ( (v8 & 1) == 0 )\n v10.m128d_f64[0] = v22 + v25;\n if ( v6 <= v10.m128d_f64[0] )\n {\n v21 = v21 + v26;\n }\n else\n {\n v11 = v9 + 1;\n v12 = v27 + v21;\n v13 = v26 + v21;\n do\n {\n v20 = v12;\n v19 = v10.m128d_f64[0];\n v14 = (__m128d *)malloc(0x70uLL);\n v10 = (__m128d)*(unsigned __int64 *)&v10.m128d_f64[0];\n v15 = (__m128d)*(unsigned __int64 *)&v22;\n v12 = v20;\n v7[v11 - 1] = v14;\n v15.m128d_f64[0] = v22 + v10.m128d_f64[0];\n v10.m128d_f64[0] = v10.m128d_f64[0] + v23;\n v16 = _mm_unpacklo_pd((__m128d)*(unsigned __int64 *)&v19, (__m128d)*(unsigned __int64 *)&v20);\n v14[1] = _mm_unpacklo_pd((__m128d)*(unsigned __int64 *)&v19, (__m128d)*(unsigned __int64 *)&v13);\n v17 = v15;\n v15.m128d_f64[1] = v21;\n *v14 = v16;\n v14[5] = v15;\n v14[2] = _mm_unpacklo_pd(v17, (__m128d)COERCE_UNSIGNED_INT64(v28 + v21));\n v14[6] = v16;\n v14[3] = _mm_unpacklo_pd(v10, (__m128d)*(unsigned __int64 *)&v13);\n v14[4] = _mm_unpacklo_pd(v10, (__m128d)*(unsigned __int64 *)&v20);\n v9 = v11++;\n }\n while ( v6 > v19 + v23 );\n v21 = v26 + v21;\n }\n ++v8;\n }\n while ( v24 > v21 );\n }\n return v7;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush r15\naddsd xmm4, xmm4\nmov edi, 320h; size\npush r14\npush r12\npush rbp\npush rbx\nsub rsp, 60h\nmovsd xmm7, cs:qword_2038\nmovsd xmm5, cs:qword_2030\nmulsd xmm4, cs:qword_2028\nmulsd xmm7, xmm4\nmovapd xmm6, xmm4\nmulsd xmm5, xmm4\naddsd xmm6, xmm4\naddsd xmm3, xmm6\nsubsd xmm1, xmm6\nmovsd [rsp+88h+var_30], xmm6\nmovsd [rsp+88h+var_60], xmm7\naddsd xmm7, xmm7\nmovsd [rsp+88h+var_38], xmm5\nmulsd xmm5, cs:qword_2040\nmovsd [rsp+88h+var_50], xmm3\nsubsd xmm0, xmm7\naddsd xmm2, xmm7\nmovsd [rsp+88h+var_58], xmm7\nmovsd [rsp+88h+var_68], xmm1\nmovsd [rsp+88h+var_48], xmm0\nmovq r14, xmm2\nmovsd [rsp+88h+var_40], xmm5\ncall _malloc\nmovsd xmm3, [rsp+88h+var_50]\ncomisd xmm3, [rsp+88h+var_68]\nmov rbx, rax\njbe loc_13E2\nmov ebp, 1\nxor eax, eax\nnop dword ptr [rax+rax+00h]\nloc_12C8:\nmovsd xmm7, [rsp+88h+var_48]\nmovapd xmm0, xmm7\ntest bpl, 1\njnz short loc_12E2\nmovsd xmm0, [rsp+88h+var_60]\naddsd xmm0, xmm7\nloc_12E2:\nmovq xmm7, r14\ncomisd xmm7, xmm0\njbe loc_13F8\nmovsd xmm6, [rsp+88h+var_68]\nmovsd xmm7, [rsp+88h+var_30]\nadd eax, 1\nmovsd xmm4, [rsp+88h+var_38]\nmovsd xmm3, [rsp+88h+var_40]\nmovsxd r12, eax\naddsd xmm7, xmm6\naddsd xmm4, xmm6\naddsd xmm3, xmm6\nmovq r15, xmm7\nloc_1320:\nmov edi, 70h ; 'p'; size\nmovsd [rsp+88h+var_70], xmm3\nmovsd [rsp+88h+var_78], xmm4\nmovsd [rsp+88h+var_80], xmm0\ncall _malloc\nmovsd xmm0, [rsp+88h+var_80]\nmovsd xmm1, [rsp+88h+var_60]\nmovq xmm6, r15\nmovsd xmm3, [rsp+88h+var_70]\nmovsd xmm4, [rsp+88h+var_78]\nmovq xmm7, r14\nmov [rbx+r12*8-8], rax\naddsd xmm1, xmm0\nmovapd xmm5, xmm0\nmovapd xmm2, xmm0\nunpcklpd xmm5, xmm3\naddsd xmm0, [rsp+88h+var_58]\nunpcklpd xmm2, xmm4\nmovups xmmword ptr [rax+10h], xmm5\nmovapd xmm5, xmm1\nmovhpd xmm1, [rsp+88h+var_68]\nmovups xmmword ptr [rax], xmm2\nunpcklpd xmm5, xmm6\nmovups xmmword ptr [rax+50h], xmm1\nmovups xmmword ptr [rax+20h], xmm5\nmovapd xmm5, xmm0\nunpcklpd xmm5, xmm3\nmovups xmmword ptr [rax+60h], xmm2\nmovups xmmword ptr [rax+30h], xmm5\nmovapd xmm5, xmm0\nunpcklpd xmm5, xmm4\nmovups xmmword ptr [rax+40h], xmm5\nmov rax, r12\nadd r12, 1\ncomisd xmm7, xmm0\nja loc_1320\nmovsd [rsp+88h+var_68], xmm3\nloc_13CD:\nmovsd xmm7, [rsp+88h+var_50]\nadd ebp, 1\ncomisd xmm7, [rsp+88h+var_68]\nja loc_12C8\nloc_13E2:\nadd rsp, 60h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r14\npop r15\nretn\nloc_13F8:\nmovsd xmm7, [rsp+88h+var_68]\naddsd xmm7, [rsp+88h+var_40]\nmovsd [rsp+88h+var_68], xmm7\njmp short loc_13CD", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1210(double a1, double a2, double a3, double a4, double a5)\n{\n double v5; // xmm4_8\n double v6; // r14\n _QWORD *v7; // rbx\n char v8; // bp\n int v9; // eax\n __m128d v10; // xmm0\n __int64 v11; // r12\n double v12; // xmm4_8\n double v13; // xmm3_8\n __m128d *v14; // rax\n __m128d v15; // xmm1\n __m128d v16; // xmm2\n __m128d v17; // xmm5\n double v19; // [rsp+0h] [rbp-80h]\n double v20; // [rsp+8h] [rbp-78h]\n double v21; // [rsp+18h] [rbp-68h]\n double v22; // [rsp+20h] [rbp-60h]\n double v23; // [rsp+28h] [rbp-58h]\n double v24; // [rsp+30h] [rbp-50h]\n double v25; // [rsp+38h] [rbp-48h]\n double v26; // [rsp+40h] [rbp-40h]\n double v27; // [rsp+48h] [rbp-38h]\n double v28; // [rsp+50h] [rbp-30h]\n\n v5 = (a5 + a5) * 0.5773502691896257;\n v28 = v5 + v5;\n v22 = 0.8660254037844387 * v5;\n v27 = 0.5 * v5;\n v24 = a4 + v5 + v5;\n v23 = v22 + v22;\n v21 = a2 - (v5 + v5);\n v25 = a1 - (v22 + v22);\n v6 = a3 + v22 + v22;\n v26 = 0.5 * v5 * 3.0;\n v7 = malloc(0x320uLL);\n if ( v24 > v21 )\n {\n v8 = 1;\n v9 = 0;\n do\n {\n v10.m128d_f64[0] = v25;\n if ( (v8 & 1) == 0 )\n v10.m128d_f64[0] = v22 + v25;\n if ( v6 <= v10.m128d_f64[0] )\n {\n v21 = v21 + v26;\n }\n else\n {\n v11 = v9 + 1;\n v12 = v27 + v21;\n v13 = v26 + v21;\n do\n {\n v20 = v12;\n v19 = v10.m128d_f64[0];\n v14 = (__m128d *)malloc(0x70uLL);\n v10 = (__m128d)*(unsigned __int64 *)&v10.m128d_f64[0];\n v15 = (__m128d)*(unsigned __int64 *)&v22;\n v12 = v20;\n v7[v11 - 1] = v14;\n v15.m128d_f64[0] = v22 + v10.m128d_f64[0];\n v10.m128d_f64[0] = v10.m128d_f64[0] + v23;\n v16 = _mm_unpacklo_pd((__m128d)*(unsigned __int64 *)&v19, (__m128d)*(unsigned __int64 *)&v20);\n v14[1] = _mm_unpacklo_pd((__m128d)*(unsigned __int64 *)&v19, (__m128d)*(unsigned __int64 *)&v13);\n v17 = v15;\n v15.m128d_f64[1] = v21;\n *v14 = v16;\n v14[5] = v15;\n v14[2] = _mm_unpacklo_pd(v17, (__m128d)COERCE_UNSIGNED_INT64(v28 + v21));\n v14[6] = v16;\n v14[3] = _mm_unpacklo_pd(v10, (__m128d)*(unsigned __int64 *)&v13);\n v14[4] = _mm_unpacklo_pd(v10, (__m128d)*(unsigned __int64 *)&v20);\n v9 = v11++;\n }\n while ( v6 > v19 + v23 );\n v21 = v26 + v21;\n }\n ++v8;\n }\n while ( v24 > v21 );\n }\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1210(double a1, double a2, double a3, double a4, double a5) {\n double v5;\n double v6;\n uint64_t *v7;\n char v8;\n int v9;\n __m128d v10;\n long long v11;\n double v12;\n double v13;\n __m128d *v14;\n __m128d v15;\n __m128d v16;\n __m128d v17;\n double v19;\n double v20;\n double v21;\n double v22;\n double v23;\n double v24;\n double v25;\n double v26;\n double v27;\n double v28;\n v5 = (a5 + a5) * 0.5773502691896257;\n v28 = v5 + v5;\n v22 = 0.8660254037844387 * v5;\n v27 = 0.5 * v5;\n v24 = a4 + v5 + v5;\n v23 = v22 + v22;\n v21 = a2 - (v5 + v5);\n v25 = a1 - (v22 + v22);\n v6 = a3 + v22 + v22;\n v26 = 0.5 * v5 * 3.0;\n v7 = malloc(800uLL);\n if (v24 > v21) {\n v8 = 1;\n v9 = 0;\n do {\n v10.m128d_f64[0] = v25;\n if ((v8 & 1) == 0) v10.m128d_f64[0] = v22 + v25;\n if (v6 <= v10.m128d_f64[0]) {\n v21 = v21 + v26;\n } else {\n v11 = v9 + 1;\n v12 = v27 + v21;\n v13 = v26 + v21;\n do {\n v20 = v12;\n v19 = v10.m128d_f64[0];\n v14 = (__m128d *)malloc(112uLL);\n v10 = (__m128d) * (unsigned long long *)&v10.m128d_f64[0];\n v15 = (__m128d) * (unsigned long long *)&v22;\n v12 = v20;\n v7[v11 - 1] = v14;\n v15.m128d_f64[0] = v22 + v10.m128d_f64[0];\n v10.m128d_f64[0] = v10.m128d_f64[0] + v23;\n v16 = _mm_unpacklo_pd((__m128d) * (unsigned long long *)&v19,\n (__m128d) * (unsigned long long *)&v20);\n v14[1] = _mm_unpacklo_pd((__m128d) * (unsigned long long *)&v19,\n (__m128d) * (unsigned long long *)&v13);\n v17 = v15;\n v15.m128d_f64[1] = v21;\n *v14 = v16;\n v14[5] = v15;\n v14[2] =\n _mm_unpacklo_pd(v17, (__m128d)COERCE_UNSIGNED_INT64(v28 + v21));\n v14[6] = v16;\n v14[3] = _mm_unpacklo_pd(v10, (__m128d) * (unsigned long long *)&v13);\n v14[4] = _mm_unpacklo_pd(v10, (__m128d) * (unsigned long long *)&v20);\n v9 = v11++;\n } while (v6 > v19 + v23);\n v21 = v26 + v21;\n }\n ++v8;\n } while (v24 > v21);\n }\n return v7;\n}", + "ida_pseudo_norm": "uint64_t *func0(double a1, double a2, double a3, double a4, double a5) {\n double v5;\n double v6;\n uint64_t *v7;\n char v8;\n int v9;\n __m128d v10;\n long long v11;\n double v12;\n double v13;\n __m128d *v14;\n __m128d v15;\n __m128d v16;\n __m128d v17;\n double v19;\n double v20;\n double v21;\n double v22;\n double v23;\n double v24;\n double v25;\n double v26;\n double v27;\n double v28;\n v5 = (a5 + a5) * 0.5773502691896257;\n v28 = v5 + v5;\n v22 = 0.8660254037844387 * v5;\n v27 = 0.5 * v5;\n v24 = a4 + v5 + v5;\n v23 = v22 + v22;\n v21 = a2 - (v5 + v5);\n v25 = a1 - (v22 + v22);\n v6 = a3 + v22 + v22;\n v26 = 0.5 * v5 * 3.0;\n v7 = malloc(800uLL);\n if (v24 > v21) {\n v8 = 1;\n v9 = 0;\n do {\n v10.m128d_f64[0] = v25;\n if ((v8 & 1) == 0) v10.m128d_f64[0] = v22 + v25;\n if (v6 <= v10.m128d_f64[0]) {\n v21 = v21 + v26;\n } else {\n v11 = v9 + 1;\n v12 = v27 + v21;\n v13 = v26 + v21;\n do {\n v20 = v12;\n v19 = v10.m128d_f64[0];\n v14 = (__m128d *)malloc(112uLL);\n v10 = (__m128d) * (unsigned long long *)&v10.m128d_f64[0];\n v15 = (__m128d) * (unsigned long long *)&v22;\n v12 = v20;\n v7[v11 - 1] = v14;\n v15.m128d_f64[0] = v22 + v10.m128d_f64[0];\n v10.m128d_f64[0] = v10.m128d_f64[0] + v23;\n v16 = _mm_unpacklo_pd((__m128d) * (unsigned long long *)&v19,\n (__m128d) * (unsigned long long *)&v20);\n v14[1] = _mm_unpacklo_pd((__m128d) * (unsigned long long *)&v19,\n (__m128d) * (unsigned long long *)&v13);\n v17 = v15;\n v15.m128d_f64[1] = v21;\n *v14 = v16;\n v14[5] = v15;\n v14[2] =\n _mm_unpacklo_pd(v17, (__m128d)COERCE_UNSIGNED_INT64(v28 + v21));\n v14[6] = v16;\n v14[3] = _mm_unpacklo_pd(v10, (__m128d) * (unsigned long long *)&v13);\n v14[4] = _mm_unpacklo_pd(v10, (__m128d) * (unsigned long long *)&v20);\n v9 = v11++;\n } while (v6 > v19 + v23);\n v21 = v26 + v21;\n }\n ++v8;\n } while (v24 > v21);\n }\n return v7;\n}" + }, + { + "index": 494, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(int* test_tup, int size) {\n int res = 0;\n for (int i = 0; i < size; i++) {\n res += test_tup[i] * pow(2, size - 1 - i);\n }\n char* result_str = (char*)malloc(sizeof(char) * 12);\n sprintf(result_str, \"%d\", res);\n return result_str;\n}", + "test": "int main() {\n\n int arr1[] = {1, 1, 0, 1, 0, 0, 1};\n\n int arr1_size = sizeof(arr1)/sizeof(arr1[0]);\n\n char* result1 = func0(arr1, arr1_size);\n\n assert(strcmp(result1, \"105\") == 0);\n\n free(result1);\n\n\n\n int arr2[] = {0, 1, 1, 0, 0, 1, 0, 1};\n\n int arr2_size = sizeof(arr2)/sizeof(arr2[0]);\n\n char* result2 = func0(arr2, arr2_size);\n\n assert(strcmp(result2, \"101\") == 0);\n\n free(result2);\n\n\n\n int arr3[] = {1, 1, 0, 1, 0, 1};\n\n int arr3_size = sizeof(arr3)/sizeof(arr3[0]);\n\n char* result3 = func0(arr3, arr3_size);\n\n assert(strcmp(result3, \"53\") == 0);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 128a \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncvtsi2sd %eax,%xmm2\nmovsd %xmm2,-0x28(%rbp)\nmov -0x1c(%rbp),%eax\nsub $0x1,%eax\nsub -0xc(%rbp),%eax\ncvtsi2sd %eax,%xmm0\nmov 0xe51(%rip),%rax\nmovapd %xmm0,%xmm1\nmovq %rax,%xmm0\ncallq 10c0 \nmovsd -0x28(%rbp),%xmm1\nmulsd %xmm0,%xmm1\ncvtsi2sdl -0x10(%rbp),%xmm0\naddsd %xmm1,%xmm0\ncvttsd2si %xmm0,%eax\nmov %eax,-0x10(%rbp)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 122c \nmov $0xc,%edi\ncallq 1100 \nmov %rax,-0x8(%rbp)\nmov -0x10(%rbp),%edx\nmov -0x8(%rbp),%rax\nlea 0xd5a(%rip),%rsi\nmov %rax,%rdi\nmov $0x0,%eax\ncallq 1110 \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp short loc_1296\nloc_122C:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\npxor xmm2, xmm2\ncvtsi2sd xmm2, eax\nmovsd [rbp+var_28], xmm2\nmov eax, [rbp+var_1C]\nsub eax, 1\nsub eax, [rbp+var_C]\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmov rax, cs:x\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\nmovsd xmm1, [rbp+var_28]\nmulsd xmm1, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_10]\naddsd xmm0, xmm1\ncvttsd2si eax, xmm0\nmov [rbp+var_10], eax\nadd [rbp+var_C], 1\nloc_1296:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_122C\nmov edi, 0Ch; size\ncall _malloc\nmov [rbp+s], rax\nmov edx, [rbp+var_10]\nmov rax, [rbp+s]\nlea rcx, format; \"%d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nmov rax, [rbp+s]\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2)\n{\n double v3; // [rsp+8h] [rbp-28h]\n int v4; // [rsp+20h] [rbp-10h]\n int i; // [rsp+24h] [rbp-Ch]\n char *s; // [rsp+28h] [rbp-8h]\n\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v3 = (double)*(int *)(4LL * i + a1);\n v4 = (int)((double)v4 + v3 * pow(2.0, (double)(a2 - 1 - i)));\n }\n s = (char *)malloc(0xCuLL);\n sprintf(s, \"%d\", v4);\n return s;\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp short loc_1296\nloc_122C:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\npxor xmm2, xmm2\ncvtsi2sd xmm2, eax\nmovsd [rbp+var_28], xmm2\nmov eax, [rbp+var_1C]\nsub eax, 1\nsub eax, [rbp+var_C]\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmov rax, cs:x\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\nmovsd xmm1, [rbp+var_28]\nmulsd xmm1, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_10]\naddsd xmm0, xmm1\ncvttsd2si eax, xmm0\nmov [rbp+var_10], eax\nadd [rbp+var_C], 1\nloc_1296:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_122C\nmov edi, 0Ch; size\ncall _malloc\nmov [rbp+s], rax\nmov edx, [rbp+var_10]\nmov rax, [rbp+s]\nlea rcx, format; \"%d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nmov rax, [rbp+s]\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1209(__int64 a1, int a2)\n{\n double v3; // [rsp+8h] [rbp-28h]\n int v4; // [rsp+20h] [rbp-10h]\n int i; // [rsp+24h] [rbp-Ch]\n char *s; // [rsp+28h] [rbp-8h]\n\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v3 = (double)*(int *)(4LL * i + a1);\n v4 = (int)((double)v4 + v3 * pow(2.0, (double)(a2 - 1 - i)));\n }\n s = (char *)malloc(0xCuLL);\n sprintf(s, \"%d\", v4);\n return s;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1209(long long a1, int a2) {\n double v3;\n int v4;\n int i;\n char *s;\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n v3 = (double)*(int *)(4LL * i + a1);\n v4 = (int)((double)v4 + v3 * pow(2.0, (double)(a2 - 1 - i)));\n }\n s = (char *)malloc(12uLL);\n sprintf(s, \"%d\", v4);\n return s;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2) {\n double v3;\n int v4;\n int i;\n char *s;\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n v3 = (double)*(int *)(4LL * i + a1);\n v4 = (int)((double)v4 + v3 * pow(2.0, (double)(a2 - 1 - i)));\n }\n s = (char *)malloc(12uLL);\n sprintf(s, \"%d\", v4);\n return s;\n}" + }, + { + "index": 494, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(int* test_tup, int size) {\n int res = 0;\n for (int i = 0; i < size; i++) {\n res += test_tup[i] * pow(2, size - 1 - i);\n }\n char* result_str = (char*)malloc(sizeof(char) * 12);\n sprintf(result_str, \"%d\", res);\n return result_str;\n}", + "test": "int main() {\n\n int arr1[] = {1, 1, 0, 1, 0, 0, 1};\n\n int arr1_size = sizeof(arr1)/sizeof(arr1[0]);\n\n char* result1 = func0(arr1, arr1_size);\n\n assert(strcmp(result1, \"105\") == 0);\n\n free(result1);\n\n\n\n int arr2[] = {0, 1, 1, 0, 0, 1, 0, 1};\n\n int arr2_size = sizeof(arr2)/sizeof(arr2[0]);\n\n char* result2 = func0(arr2, arr2_size);\n\n assert(strcmp(result2, \"101\") == 0);\n\n free(result2);\n\n\n\n int arr3[] = {1, 1, 0, 1, 0, 1};\n\n int arr3_size = sizeof(arr3)/sizeof(arr3[0]);\n\n char* result3 = func0(arr3, arr3_size);\n\n assert(strcmp(result3, \"53\") == 0);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x10,%rsp\ntest %esi,%esi\njle 12a5 \nmov %rdi,%r12\nmov %esi,%r14d\nlea -0x1(%rsi),%r13d\nadd $0x2,%r13\nmov $0x1,%ebp\nmov $0x0,%ebx\npxor %xmm2,%xmm2\ncvtsi2sdl -0x4(%r12,%rbp,4),%xmm2\nmovsd %xmm2,0x8(%rsp)\nmov %r14d,%eax\nsub %ebp,%eax\npxor %xmm1,%xmm1\ncvtsi2sd %eax,%xmm1\nmov 0xe72(%rip),%rax\nmovq %rax,%xmm0\ncallq 10b0 \npxor %xmm1,%xmm1\ncvtsi2sd %ebx,%xmm1\nmulsd 0x8(%rsp),%xmm0\naddsd %xmm0,%xmm1\ncvttsd2si %xmm1,%ebx\nadd $0x1,%rbp\ncmp %r13,%rbp\njne 1219 \nmov $0xc,%edi\ncallq 10e0 \nmov %rax,%rbp\nmov %ebx,%r8d\nlea 0xd86(%rip),%rcx\nmov $0xc,%edx\nmov $0x1,%esi\nmov %rax,%rdi\nmov $0x0,%eax\ncallq 10f0 <__sprintf_chk@plt>\nmov %rbp,%rax\nadd $0x10,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nmov $0x0,%ebx\njmp 1267 \n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 10h\ntest esi, esi\njle loc_12C3\nmov r13, rdi\nmov r12d, esi\nmovsxd r14, esi\nmov ebx, 1\nmov ebp, 0\nloc_1234:\npxor xmm2, xmm2\ncvtsi2sd xmm2, dword ptr [r13+rbx*4-4]\nmovsd [rsp+38h+var_30], xmm2\nmov eax, r12d\nsub eax, ebx\npxor xmm1, xmm1\ncvtsi2sd xmm1, eax; y\nmovsd xmm0, cs:x; x\ncall _pow\nmovapd xmm1, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, ebp\nmulsd xmm1, [rsp+38h+var_30]\naddsd xmm0, xmm1\ncvttsd2si ebp, xmm0\nmov rax, rbx\nadd rbx, 1\ncmp rax, r14\njnz short loc_1234\nloc_1285:\nmov edi, 0Ch; size\ncall _malloc\nmov rbx, rax\nmov r8d, ebp\nlea rcx, unk_2004\nmov edx, 0Ch\nmov esi, 2\nmov rdi, rax\nmov eax, 0\ncall ___sprintf_chk\nmov rax, rbx\nadd rsp, 10h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_12C3:\nmov ebp, 0\njmp short loc_1285", + "ida_pseudo": "void *__fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // rbx\n int v3; // ebp\n __int64 v4; // rax\n void *v5; // rbx\n double v7; // [rsp+8h] [rbp-30h]\n\n if ( a2 <= 0 )\n {\n v3 = 0;\n }\n else\n {\n v2 = 1LL;\n v3 = 0;\n do\n {\n v7 = (double)*(int *)(a1 + 4 * v2 - 4);\n v3 = (int)((double)v3 + pow(2.0, (double)(a2 - (int)v2)) * v7);\n v4 = v2++;\n }\n while ( v4 != a2 );\n }\n v5 = malloc(0xCuLL);\n __sprintf_chk(v5, 2LL, 12LL, &unk_2004, (unsigned int)v3);\n return v5;\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 10h\ntest esi, esi\njle loc_12C3\nmov r13, rdi\nmov r12d, esi\nmovsxd r14, esi\nmov ebx, 1\nmov ebp, 0\nloc_1234:\npxor xmm2, xmm2\ncvtsi2sd xmm2, dword ptr [r13+rbx*4-4]\nmovsd [rsp+38h+var_30], xmm2\nmov eax, r12d\nsub eax, ebx\npxor xmm1, xmm1\ncvtsi2sd xmm1, eax; y\nmovsd xmm0, cs:x; x\ncall _pow\nmovapd xmm1, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, ebp\nmulsd xmm1, [rsp+38h+var_30]\naddsd xmm0, xmm1\ncvttsd2si ebp, xmm0\nmov rax, rbx\nadd rbx, 1\ncmp rax, r14\njnz short loc_1234\nloc_1285:\nmov edi, 0Ch; size\ncall _malloc\nmov rbx, rax\nmov r8d, ebp\nlea rcx, unk_2004\nmov edx, 0Ch\nmov esi, 2\nmov rdi, rax\nmov eax, 0\ncall ___sprintf_chk\nmov rax, rbx\nadd rsp, 10h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_12C3:\nmov ebp, 0\njmp short loc_1285", + "ida_strip_pseudo": "void *__fastcall sub_1209(__int64 a1, int a2)\n{\n __int64 v2; // rbx\n int v3; // ebp\n __int64 v4; // rax\n void *v5; // rbx\n double v7; // [rsp+8h] [rbp-30h]\n\n if ( a2 <= 0 )\n {\n v3 = 0;\n }\n else\n {\n v2 = 1LL;\n v3 = 0;\n do\n {\n v7 = (double)*(int *)(a1 + 4 * v2 - 4);\n v3 = (int)((double)v3 + pow(2.0, (double)(a2 - (int)v2)) * v7);\n v4 = v2++;\n }\n while ( v4 != a2 );\n }\n v5 = malloc(0xCuLL);\n __sprintf_chk(v5, 2LL, 12LL, &unk_2004, (unsigned int)v3);\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1209(long long a1, int a2) {\n long long v2;\n int v3;\n long long v4;\n void *v5;\n double v7;\n if (a2 <= 0) {\n v3 = 0;\n } else {\n v2 = 1LL;\n v3 = 0;\n do {\n v7 = (double)*(int *)(a1 + 4 * v2 - 4);\n v3 = (int)((double)v3 + pow(2.0, (double)(a2 - (int)v2)) * v7);\n v4 = v2++;\n } while (v4 != a2);\n }\n v5 = malloc(12uLL);\n __sprintf_chk(v5, 2LL, 12LL, &unk_2004, (unsigned int)v3);\n return v5;\n}", + "ida_pseudo_norm": "void *func0(long long a1, int a2) {\n long long v2;\n int v3;\n long long v4;\n void *v5;\n double v7;\n if (a2 <= 0) {\n v3 = 0;\n } else {\n v2 = 1LL;\n v3 = 0;\n do {\n v7 = (double)*(int *)(a1 + 4 * v2 - 4);\n v3 = (int)((double)v3 + pow(2.0, (double)(a2 - (int)v2)) * v7);\n v4 = v2++;\n } while (v4 != a2);\n }\n v5 = malloc(12uLL);\n __sprintf_chk(v5, 2LL, 12LL, &unk_2004, (unsigned int)v3);\n return v5;\n}" + }, + { + "index": 494, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(int* test_tup, int size) {\n int res = 0;\n for (int i = 0; i < size; i++) {\n res += test_tup[i] * pow(2, size - 1 - i);\n }\n char* result_str = (char*)malloc(sizeof(char) * 12);\n sprintf(result_str, \"%d\", res);\n return result_str;\n}", + "test": "int main() {\n\n int arr1[] = {1, 1, 0, 1, 0, 0, 1};\n\n int arr1_size = sizeof(arr1)/sizeof(arr1[0]);\n\n char* result1 = func0(arr1, arr1_size);\n\n assert(strcmp(result1, \"105\") == 0);\n\n free(result1);\n\n\n\n int arr2[] = {0, 1, 1, 0, 0, 1, 0, 1};\n\n int arr2_size = sizeof(arr2)/sizeof(arr2[0]);\n\n char* result2 = func0(arr2, arr2_size);\n\n assert(strcmp(result2, \"101\") == 0);\n\n free(result2);\n\n\n\n int arr3[] = {1, 1, 0, 1, 0, 1};\n\n int arr3_size = sizeof(arr3)/sizeof(arr3[0]);\n\n char* result3 = func0(arr3, arr3_size);\n\n assert(strcmp(result3, \"53\") == 0);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nsub $0x10,%rsp\ntest %esi,%esi\njle 1418 \nmov %rdi,%r12\nlea -0x1(%rsi),%ebp\nxor %ebx,%ebx\nnopl 0x0(%rax)\npxor %xmm2,%xmm2\npxor %xmm1,%xmm1\nmov 0xd11(%rip),%rax\nadd $0x4,%r12\ncvtsi2sd %ebp,%xmm1\nsub $0x1,%ebp\ncvtsi2sdl -0x4(%r12),%xmm2\nmovq %rax,%xmm0\nmovsd %xmm2,0x8(%rsp)\ncallq 10b0 \nmulsd 0x8(%rsp),%xmm0\npxor %xmm1,%xmm1\ncvtsi2sd %ebx,%xmm1\naddsd %xmm0,%xmm1\ncvttsd2si %xmm1,%ebx\ncmp $0xffffffff,%ebp\njne 1390 \nmov $0xc,%edi\ncallq 10e0 \nmov %ebx,%r8d\nmov $0xc,%edx\nlea 0xc0f(%rip),%rcx\nmov %rax,%r12\nmov %rax,%rdi\nmov $0x1,%esi\nxor %eax,%eax\ncallq 10f0 <__sprintf_chk@plt>\nadd $0x10,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax,%rax,1)\nxor %ebx,%ebx\njmp 13dc \nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 10h\ntest esi, esi\njle loc_1420\nmov rbp, rdi\nlea ebx, [rsi-1]\nxor r12d, r12d\nnop dword ptr [rax]\nloc_13A0:\npxor xmm2, xmm2\npxor xmm1, xmm1\nmovsd xmm0, cs:x; x\nadd rbp, 4\ncvtsi2sd xmm2, dword ptr [rbp-4]\ncvtsi2sd xmm1, ebx; y\nmovsd [rsp+28h+var_20], xmm2\ncall _pow\nmovapd xmm1, xmm0\npxor xmm0, xmm0\nmulsd xmm1, [rsp+28h+var_20]\ncvtsi2sd xmm0, r12d\naddsd xmm0, xmm1\ncvttsd2si r12d, xmm0\nsub ebx, 1\njnb short loc_13A0\nloc_13E9:\nmov edi, 0Ch; size\ncall _malloc\nmov r8d, r12d\nmov edx, 0Ch\nlea rcx, unk_2004\nmov rbx, rax\nmov rdi, rax\nmov esi, 2\nxor eax, eax\ncall ___sprintf_chk\nadd rsp, 10h\nmov rax, rbx\npop rbx\npop rbp\npop r12\nretn\nloc_1420:\nxor r12d, r12d\njmp short loc_13E9", + "ida_pseudo": "void *__fastcall func0(__int64 a1, int a2)\n{\n int v3; // ebx\n int v4; // r12d\n void *v6; // rbx\n double v8; // [rsp+8h] [rbp-20h]\n\n if ( a2 <= 0 )\n {\n v4 = 0;\n }\n else\n {\n v3 = a2 - 1;\n v4 = 0;\n do\n {\n a1 += 4LL;\n v8 = (double)*(int *)(a1 - 4);\n v4 = (int)((double)v4 + pow(2.0, (double)v3) * v8);\n }\n while ( v3-- != 0 );\n }\n v6 = malloc(0xCuLL);\n __sprintf_chk(v6, 2LL, 12LL, &unk_2004, (unsigned int)v4);\n return v6;\n}", + "ida_strip_asm": "sub_1380:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 10h\ntest esi, esi\njle loc_1420\nmov rbp, rdi\nlea ebx, [rsi-1]\nxor r12d, r12d\nnop dword ptr [rax]\nloc_13A0:\npxor xmm2, xmm2\npxor xmm1, xmm1\nmovsd xmm0, cs:x; x\nadd rbp, 4\ncvtsi2sd xmm2, dword ptr [rbp-4]\ncvtsi2sd xmm1, ebx; y\nmovsd [rsp+28h+var_20], xmm2\ncall _pow\nmovapd xmm1, xmm0\npxor xmm0, xmm0\nmulsd xmm1, [rsp+28h+var_20]\ncvtsi2sd xmm0, r12d\naddsd xmm0, xmm1\ncvttsd2si r12d, xmm0\nsub ebx, 1\njnb short loc_13A0\nloc_13E9:\nmov edi, 0Ch; size\ncall _malloc\nmov r8d, r12d\nmov edx, 0Ch\nlea rcx, unk_2004\nmov rbx, rax\nmov rdi, rax\nmov esi, 2\nxor eax, eax\ncall ___sprintf_chk\nadd rsp, 10h\nmov rax, rbx\npop rbx\npop rbp\npop r12\nretn\nloc_1420:\nxor r12d, r12d\njmp short loc_13E9", + "ida_strip_pseudo": "void *__fastcall sub_1380(__int64 a1, int a2)\n{\n int v3; // ebx\n int v4; // r12d\n void *v6; // rbx\n double v8; // [rsp+8h] [rbp-20h]\n\n if ( a2 <= 0 )\n {\n v4 = 0;\n }\n else\n {\n v3 = a2 - 1;\n v4 = 0;\n do\n {\n a1 += 4LL;\n v8 = (double)*(int *)(a1 - 4);\n v4 = (int)((double)v4 + pow(2.0, (double)v3) * v8);\n }\n while ( v3-- != 0 );\n }\n v6 = malloc(0xCuLL);\n __sprintf_chk(v6, 2LL, 12LL, &unk_2004, (unsigned int)v4);\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1380(long long a1, int a2) {\n int v3;\n int v4;\n void *v6;\n double v8;\n if (a2 <= 0) {\n v4 = 0;\n } else {\n v3 = a2 - 1;\n v4 = 0;\n do {\n a1 += 4LL;\n v8 = (double)*(int *)(a1 - 4);\n v4 = (int)((double)v4 + pow(2.0, (double)v3) * v8);\n } while (v3-- != 0);\n }\n v6 = malloc(12uLL);\n __sprintf_chk(v6, 2LL, 12LL, &unk_2004, (unsigned int)v4);\n return v6;\n}", + "ida_pseudo_norm": "void *func0(long long a1, int a2) {\n int v3;\n int v4;\n void *v6;\n double v8;\n if (a2 <= 0) {\n v4 = 0;\n } else {\n v3 = a2 - 1;\n v4 = 0;\n do {\n a1 += 4LL;\n v8 = (double)*(int *)(a1 - 4);\n v4 = (int)((double)v4 + pow(2.0, (double)v3) * v8);\n } while (v3-- != 0);\n }\n v6 = malloc(12uLL);\n __sprintf_chk(v6, 2LL, 12LL, &unk_2004, (unsigned int)v4);\n return v6;\n}" + }, + { + "index": 494, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(int* test_tup, int size) {\n int res = 0;\n for (int i = 0; i < size; i++) {\n res += test_tup[i] * pow(2, size - 1 - i);\n }\n char* result_str = (char*)malloc(sizeof(char) * 12);\n sprintf(result_str, \"%d\", res);\n return result_str;\n}", + "test": "int main() {\n\n int arr1[] = {1, 1, 0, 1, 0, 0, 1};\n\n int arr1_size = sizeof(arr1)/sizeof(arr1[0]);\n\n char* result1 = func0(arr1, arr1_size);\n\n assert(strcmp(result1, \"105\") == 0);\n\n free(result1);\n\n\n\n int arr2[] = {0, 1, 1, 0, 0, 1, 0, 1};\n\n int arr2_size = sizeof(arr2)/sizeof(arr2[0]);\n\n char* result2 = func0(arr2, arr2_size);\n\n assert(strcmp(result2, \"101\") == 0);\n\n free(result2);\n\n\n\n int arr3[] = {1, 1, 0, 1, 0, 1};\n\n int arr3_size = sizeof(arr3)/sizeof(arr3[0]);\n\n char* result3 = func0(arr3, arr3_size);\n\n assert(strcmp(result3, \"53\") == 0);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nsub $0x10,%rsp\ntest %esi,%esi\njle 1418 \nmov %rdi,%r12\nlea -0x1(%rsi),%ebp\nxor %ebx,%ebx\nnopl 0x0(%rax)\npxor %xmm2,%xmm2\npxor %xmm1,%xmm1\nmov 0xd11(%rip),%rax\nadd $0x4,%r12\ncvtsi2sd %ebp,%xmm1\nsub $0x1,%ebp\ncvtsi2sdl -0x4(%r12),%xmm2\nmovq %rax,%xmm0\nmovsd %xmm2,0x8(%rsp)\ncallq 10b0 \nmulsd 0x8(%rsp),%xmm0\npxor %xmm1,%xmm1\ncvtsi2sd %ebx,%xmm1\naddsd %xmm0,%xmm1\ncvttsd2si %xmm1,%ebx\ncmp $0xffffffff,%ebp\njne 1390 \nmov $0xc,%edi\ncallq 10e0 \nmov %ebx,%r8d\nmov $0xc,%edx\nlea 0xc0f(%rip),%rcx\nmov %rax,%r12\nmov %rax,%rdi\nmov $0x1,%esi\nxor %eax,%eax\ncallq 10f0 <__sprintf_chk@plt>\nadd $0x10,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax,%rax,1)\nxor %ebx,%ebx\njmp 13dc \nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 10h\ntest esi, esi\njle loc_1420\nmov rbp, rdi\nlea ebx, [rsi-1]\nxor r12d, r12d\nnop dword ptr [rax]\nloc_13A0:\npxor xmm2, xmm2\npxor xmm1, xmm1\nmovsd xmm0, cs:x; x\nadd rbp, 4\ncvtsi2sd xmm2, dword ptr [rbp-4]\ncvtsi2sd xmm1, ebx; y\nmovsd [rsp+28h+var_20], xmm2\ncall _pow\nmovapd xmm1, xmm0\npxor xmm0, xmm0\nmulsd xmm1, [rsp+28h+var_20]\ncvtsi2sd xmm0, r12d\naddsd xmm0, xmm1\ncvttsd2si r12d, xmm0\nsub ebx, 1\njnb short loc_13A0\nloc_13E9:\nmov edi, 0Ch; size\ncall _malloc\nmov r8d, r12d\nmov edx, 0Ch\nlea rcx, unk_2004\nmov rbx, rax\nmov rdi, rax\nmov esi, 2\nxor eax, eax\ncall ___sprintf_chk\nadd rsp, 10h\nmov rax, rbx\npop rbx\npop rbp\npop r12\nretn\nloc_1420:\nxor r12d, r12d\njmp short loc_13E9", + "ida_pseudo": "void *__fastcall func0(__int64 a1, int a2)\n{\n int v3; // ebx\n int v4; // r12d\n void *v6; // rbx\n double v8; // [rsp+8h] [rbp-20h]\n\n if ( a2 <= 0 )\n {\n v4 = 0;\n }\n else\n {\n v3 = a2 - 1;\n v4 = 0;\n do\n {\n a1 += 4LL;\n v8 = (double)*(int *)(a1 - 4);\n v4 = (int)((double)v4 + pow(2.0, (double)v3) * v8);\n }\n while ( v3-- != 0 );\n }\n v6 = malloc(0xCuLL);\n __sprintf_chk(v6, 2LL, 12LL, &unk_2004, (unsigned int)v4);\n return v6;\n}", + "ida_strip_asm": "sub_1380:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 10h\ntest esi, esi\njle loc_1420\nmov rbp, rdi\nlea ebx, [rsi-1]\nxor r12d, r12d\nnop dword ptr [rax]\nloc_13A0:\npxor xmm2, xmm2\npxor xmm1, xmm1\nmovsd xmm0, cs:x; x\nadd rbp, 4\ncvtsi2sd xmm2, dword ptr [rbp-4]\ncvtsi2sd xmm1, ebx; y\nmovsd [rsp+28h+var_20], xmm2\ncall _pow\nmovapd xmm1, xmm0\npxor xmm0, xmm0\nmulsd xmm1, [rsp+28h+var_20]\ncvtsi2sd xmm0, r12d\naddsd xmm0, xmm1\ncvttsd2si r12d, xmm0\nsub ebx, 1\njnb short loc_13A0\nloc_13E9:\nmov edi, 0Ch; size\ncall _malloc\nmov r8d, r12d\nmov edx, 0Ch\nlea rcx, unk_2004\nmov rbx, rax\nmov rdi, rax\nmov esi, 2\nxor eax, eax\ncall ___sprintf_chk\nadd rsp, 10h\nmov rax, rbx\npop rbx\npop rbp\npop r12\nretn\nloc_1420:\nxor r12d, r12d\njmp short loc_13E9", + "ida_strip_pseudo": "void *__fastcall sub_1380(__int64 a1, int a2)\n{\n int v3; // ebx\n int v4; // r12d\n void *v6; // rbx\n double v8; // [rsp+8h] [rbp-20h]\n\n if ( a2 <= 0 )\n {\n v4 = 0;\n }\n else\n {\n v3 = a2 - 1;\n v4 = 0;\n do\n {\n a1 += 4LL;\n v8 = (double)*(int *)(a1 - 4);\n v4 = (int)((double)v4 + pow(2.0, (double)v3) * v8);\n }\n while ( v3-- != 0 );\n }\n v6 = malloc(0xCuLL);\n __sprintf_chk(v6, 2LL, 12LL, &unk_2004, (unsigned int)v4);\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1380(long long a1, int a2) {\n int v3;\n int v4;\n void *v6;\n double v8;\n if (a2 <= 0) {\n v4 = 0;\n } else {\n v3 = a2 - 1;\n v4 = 0;\n do {\n a1 += 4LL;\n v8 = (double)*(int *)(a1 - 4);\n v4 = (int)((double)v4 + pow(2.0, (double)v3) * v8);\n } while (v3-- != 0);\n }\n v6 = malloc(12uLL);\n __sprintf_chk(v6, 2LL, 12LL, &unk_2004, (unsigned int)v4);\n return v6;\n}", + "ida_pseudo_norm": "void *func0(long long a1, int a2) {\n int v3;\n int v4;\n void *v6;\n double v8;\n if (a2 <= 0) {\n v4 = 0;\n } else {\n v3 = a2 - 1;\n v4 = 0;\n do {\n a1 += 4LL;\n v8 = (double)*(int *)(a1 - 4);\n v4 = (int)((double)v4 + pow(2.0, (double)v3) * v8);\n } while (v3-- != 0);\n }\n v6 = malloc(12uLL);\n __sprintf_chk(v6, 2LL, 12LL, &unk_2004, (unsigned int)v4);\n return v6;\n}" + }, + { + "index": 495, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* str1) {\n static char result[100];\n int i, j = 0;\n for (i = 0; str1[i] != '\\0'; i++) {\n if (str1[i] < 'a' || str1[i] > 'z') {\n result[j++] = str1[i];\n }\n }\n result[j] = '\\0';\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"KDeoALOklOOHserfLoAJSIskdsf\"), \"KDALOOOHLAJSI\") == 0);\n\n assert(strcmp(func0(\"ProducTnamEstreAmIngMediAplAYer\"), \"PTEAIMAAY\") == 0);\n\n assert(strcmp(func0(\"maNufacTuredbYSheZenTechNolOGIes\"), \"NTYSZTNOGI\") == 0);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmovl $0x0,-0x4(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11d7 \nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x60,%al\njle 11ad \nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x7a,%al\njle 11d3 \nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x4(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x4(%rbp)\nmovzbl (%rcx),%edx\ncltq\nlea 0x2e70(%rip),%rcx\nmov %dl,(%rax,%rcx,1)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 1185 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x2e49(%rip),%rdx\nmovb $0x0,(%rax,%rdx,1)\nlea 0x2e3e(%rip),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_4], 0\nmov [rbp+var_8], 0\njmp short loc_11D7\nloc_1185:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 60h ; '`'\njle short loc_11AD\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 7Ah ; 'z'\njle short loc_11D3\nloc_11AD:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_4]\nlea edx, [rax+1]\nmov [rbp+var_4], edx\nmovzx edx, byte ptr [rcx]\ncdqe\nlea rcx, result_1\nmov [rax+rcx], dl\nloc_11D3:\nadd [rbp+var_8], 1\nloc_11D7:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1185\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, result_1\nmov byte ptr [rax+rdx], 0\nlea rax, result_1\npop rbp\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(__int64 a1)\n{\n int v1; // eax\n int i; // [rsp+10h] [rbp-8h]\n int v4; // [rsp+14h] [rbp-4h]\n\n v4 = 0;\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n {\n if ( *(char *)(i + a1) <= 96 || *(char *)(i + a1) > 122 )\n {\n v1 = v4++;\n result_1[v1] = *(_BYTE *)(i + a1);\n }\n }\n result_1[v4] = 0;\n return result_1;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_4], 0\nmov [rbp+var_8], 0\njmp short loc_11D7\nloc_1185:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 60h ; '`'\njle short loc_11AD\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 7Ah ; 'z'\njle short loc_11D3\nloc_11AD:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_4]\nlea edx, [rax+1]\nmov [rbp+var_4], edx\nmovzx edx, byte ptr [rcx]\ncdqe\nlea rcx, unk_4040\nmov [rax+rcx], dl\nloc_11D3:\nadd [rbp+var_8], 1\nloc_11D7:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1185\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, unk_4040\nmov byte ptr [rax+rdx], 0\nlea rax, unk_4040\npop rbp\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1169(__int64 a1)\n{\n int v1; // eax\n int i; // [rsp+10h] [rbp-8h]\n int v4; // [rsp+14h] [rbp-4h]\n\n v4 = 0;\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n {\n if ( *(char *)(i + a1) <= 96 || *(char *)(i + a1) > 122 )\n {\n v1 = v4++;\n byte_4040[v1] = *(_BYTE *)(i + a1);\n }\n }\n byte_4040[v4] = 0;\n return byte_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1169(long long a1) {\n int v1;\n int i;\n int v4;\n v4 = 0;\n for (i = 0; *(uint8_t *)(i + a1); ++i) {\n if (*(char *)(i + a1) <= 96 || *(char *)(i + a1) > 122) {\n v1 = v4++;\n byte_4040[v1] = *(uint8_t *)(i + a1);\n }\n }\n byte_4040[v4] = 0;\n return byte_4040;\n}", + "ida_pseudo_norm": "uint8_t *func0(long long a1) {\n int v1;\n int i;\n int v4;\n v4 = 0;\n for (i = 0; *(uint8_t *)(i + a1); ++i) {\n if (*(char *)(i + a1) <= 96 || *(char *)(i + a1) > 122) {\n v1 = v4++;\n result_1[v1] = *(uint8_t *)(i + a1);\n }\n }\n result_1[v4] = 0;\n return result_1;\n}" + }, + { + "index": 495, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* str1) {\n static char result[100];\n int i, j = 0;\n for (i = 0; str1[i] != '\\0'; i++) {\n if (str1[i] < 'a' || str1[i] > 'z') {\n result[j++] = str1[i];\n }\n }\n result[j] = '\\0';\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"KDeoALOklOOHserfLoAJSIskdsf\"), \"KDALOOOHLAJSI\") == 0);\n\n assert(strcmp(func0(\"ProducTnamEstreAmIngMediAplAYer\"), \"PTEAIMAAY\") == 0);\n\n assert(strcmp(func0(\"maNufacTuredbYSheZenTechNolOGIes\"), \"NTYSZTNOGI\") == 0);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmovzbl (%rdi),%eax\ntest %al,%al\nje 1185 \nadd $0x1,%rdi\nmov $0x0,%ecx\nlea 0x2edc(%rip),%rsi\njmp 1172 \nadd $0x1,%rdi\nmovzbl -0x1(%rdi),%eax\ntest %al,%al\nje 118a \nlea -0x61(%rax),%edx\ncmp $0x19,%dl\njbe 1166 \nmovslq %ecx,%rdx\nmov %al,(%rsi,%rdx,1)\nlea 0x1(%rcx),%ecx\njmp 1166 \nmov $0x0,%ecx\nlea 0x2eaf(%rip),%rax\nmovslq %ecx,%rcx\nmovb $0x0,(%rax,%rcx,1)\nretq\n", + "ida_asm": "func0:\nendbr64\nmovzx eax, byte ptr [rdi]\ntest al, al\njz short loc_11A5\nadd rdi, 1\nmov ecx, 0\nlea rsi, result_1\njmp short loc_1192\nloc_1186:\nadd rdi, 1\nmovzx eax, byte ptr [rdi-1]\ntest al, al\njz short loc_11AA\nloc_1192:\nlea edx, [rax-61h]\ncmp dl, 19h\njbe short loc_1186\nmovsxd rdx, ecx\nmov [rsi+rdx], al\nlea ecx, [rcx+1]\njmp short loc_1186\nloc_11A5:\nmov ecx, 0\nloc_11AA:\nlea rax, result_1\nmovsxd rcx, ecx\nmov byte ptr [rax+rcx], 0\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(char *a1)\n{\n char v1; // al\n char *v2; // rdi\n int v3; // ecx\n _BYTE *result; // rax\n\n v1 = *a1;\n if ( *a1 )\n {\n v2 = a1 + 1;\n v3 = 0;\n do\n {\n if ( (unsigned __int8)(v1 - 97) > 0x19u )\n result_1[v3++] = v1;\n v1 = *v2++;\n }\n while ( v1 );\n }\n else\n {\n v3 = 0;\n }\n result = result_1;\n result_1[v3] = 0;\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmovzx eax, byte ptr [rdi]\ntest al, al\njz short loc_11A5\nadd rdi, 1\nmov ecx, 0\nlea rsi, unk_4040\njmp short loc_1192\nloc_1186:\nadd rdi, 1\nmovzx eax, byte ptr [rdi-1]\ntest al, al\njz short loc_11AA\nloc_1192:\nlea edx, [rax-61h]\ncmp dl, 19h\njbe short loc_1186\nmovsxd rdx, ecx\nmov [rsi+rdx], al\nlea ecx, [rcx+1]\njmp short loc_1186\nloc_11A5:\nmov ecx, 0\nloc_11AA:\nlea rax, unk_4040\nmovsxd rcx, ecx\nmov byte ptr [rax+rcx], 0\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1169(char *a1)\n{\n char v1; // al\n char *v2; // rdi\n int v3; // ecx\n _BYTE *result; // rax\n\n v1 = *a1;\n if ( *a1 )\n {\n v2 = a1 + 1;\n v3 = 0;\n do\n {\n if ( (unsigned __int8)(v1 - 97) > 0x19u )\n byte_4040[v3++] = v1;\n v1 = *v2++;\n }\n while ( v1 );\n }\n else\n {\n v3 = 0;\n }\n result = byte_4040;\n byte_4040[v3] = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1169(char *a1) {\n char v1;\n char *v2;\n int v3;\n uint8_t *result;\n v1 = *a1;\n if (*a1) {\n v2 = a1 + 1;\n v3 = 0;\n do {\n if ((unsigned char)(v1 - 97) > 25u) byte_4040[v3++] = v1;\n v1 = *v2++;\n } while (v1);\n } else {\n v3 = 0;\n }\n result = byte_4040;\n byte_4040[v3] = 0;\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(char *a1) {\n char v1;\n char *v2;\n int v3;\n uint8_t *result;\n v1 = *a1;\n if (*a1) {\n v2 = a1 + 1;\n v3 = 0;\n do {\n if ((unsigned char)(v1 - 97) > 25u) result_1[v3++] = v1;\n v1 = *v2++;\n } while (v1);\n } else {\n v3 = 0;\n }\n result = result_1;\n result_1[v3] = 0;\n return result;\n}" + }, + { + "index": 495, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* str1) {\n static char result[100];\n int i, j = 0;\n for (i = 0; str1[i] != '\\0'; i++) {\n if (str1[i] < 'a' || str1[i] > 'z') {\n result[j++] = str1[i];\n }\n }\n result[j] = '\\0';\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"KDeoALOklOOHserfLoAJSIskdsf\"), \"KDALOOOHLAJSI\") == 0);\n\n assert(strcmp(func0(\"ProducTnamEstreAmIngMediAplAYer\"), \"PTEAIMAAY\") == 0);\n\n assert(strcmp(func0(\"maNufacTuredbYSheZenTechNolOGIes\"), \"NTYSZTNOGI\") == 0);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmovzbl (%rdi),%eax\ntest %al,%al\nje 1330 \nadd $0x1,%rdi\nxor %ecx,%ecx\nlea 0x2d48(%rip),%rsi\nnopl 0x0(%rax,%rax,1)\nlea -0x61(%rax),%edx\ncmp $0x19,%dl\njbe 1311 \nmovslq %ecx,%rdx\nadd $0x1,%ecx\nmov %al,(%rsi,%rdx,1)\nmovzbl (%rdi),%eax\nadd $0x1,%rdi\ntest %al,%al\njne 1300 \nmovslq %ecx,%rcx\nlea 0x2d1a(%rip),%rax\nmovb $0x0,(%rsi,%rcx,1)\nretq\nnopl 0x0(%rax,%rax,1)\nxor %ecx,%ecx\nlea 0x2d07(%rip),%rsi\nlea 0x2d00(%rip),%rax\nmovslq %ecx,%rcx\nmovb $0x0,(%rsi,%rcx,1)\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmovzx eax, byte ptr [rdi]\ntest al, al\njz short loc_1290\nadd rdi, 1\nxor ecx, ecx\nlea rsi, result_1\nnop dword ptr [rax+rax+00000000h]\nloc_1260:\nlea edx, [rax-61h]\ncmp dl, 19h\njbe short loc_1271\nmovsxd rdx, ecx\nadd ecx, 1\nmov [rsi+rdx], al\nloc_1271:\nmovzx eax, byte ptr [rdi]\nadd rdi, 1\ntest al, al\njnz short loc_1260\nmovsxd rcx, ecx\nmov rax, rsi\nmov byte ptr [rsi+rcx], 0\nretn\nloc_1290:\nxor ecx, ecx\nlea rsi, result_1\nmovsxd rcx, ecx\nmov rax, rsi\nmov byte ptr [rsi+rcx], 0\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(char *a1)\n{\n char v1; // al\n char *v2; // rdi\n int v3; // ecx\n __int64 v4; // rdx\n _BYTE *result; // rax\n\n v1 = *a1;\n if ( *a1 )\n {\n v2 = a1 + 1;\n v3 = 0;\n do\n {\n if ( (unsigned __int8)(v1 - 97) > 0x19u )\n {\n v4 = v3++;\n result_1[v4] = v1;\n }\n v1 = *v2++;\n }\n while ( v1 );\n result = result_1;\n result_1[v3] = 0;\n }\n else\n {\n result = result_1;\n result_1[0] = 0;\n }\n return result;\n}", + "ida_strip_asm": "sub_1240:\nendbr64\nmovzx eax, byte ptr [rdi]\ntest al, al\njz short loc_1290\nadd rdi, 1\nxor ecx, ecx\nlea rsi, unk_4040\nnop dword ptr [rax+rax+00000000h]\nloc_1260:\nlea edx, [rax-61h]\ncmp dl, 19h\njbe short loc_1271\nmovsxd rdx, ecx\nadd ecx, 1\nmov [rsi+rdx], al\nloc_1271:\nmovzx eax, byte ptr [rdi]\nadd rdi, 1\ntest al, al\njnz short loc_1260\nmovsxd rcx, ecx\nmov rax, rsi\nmov byte ptr [rsi+rcx], 0\nretn\nloc_1290:\nxor ecx, ecx\nlea rsi, unk_4040\nmovsxd rcx, ecx\nmov rax, rsi\nmov byte ptr [rsi+rcx], 0\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1240(char *a1)\n{\n char v1; // al\n char *v2; // rdi\n int v3; // ecx\n __int64 v4; // rdx\n _BYTE *result; // rax\n\n v1 = *a1;\n if ( *a1 )\n {\n v2 = a1 + 1;\n v3 = 0;\n do\n {\n if ( (unsigned __int8)(v1 - 97) > 0x19u )\n {\n v4 = v3++;\n byte_4040[v4] = v1;\n }\n v1 = *v2++;\n }\n while ( v1 );\n result = byte_4040;\n byte_4040[v3] = 0;\n }\n else\n {\n result = byte_4040;\n byte_4040[0] = 0;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1240(char *a1) {\n char v1;\n char *v2;\n int v3;\n long long v4;\n uint8_t *result;\n v1 = *a1;\n if (*a1) {\n v2 = a1 + 1;\n v3 = 0;\n do {\n if ((unsigned char)(v1 - 97) > 25u) {\n v4 = v3++;\n byte_4040[v4] = v1;\n }\n v1 = *v2++;\n } while (v1);\n result = byte_4040;\n byte_4040[v3] = 0;\n } else {\n result = byte_4040;\n byte_4040[0] = 0;\n }\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(char *a1) {\n char v1;\n char *v2;\n int v3;\n long long v4;\n uint8_t *result;\n v1 = *a1;\n if (*a1) {\n v2 = a1 + 1;\n v3 = 0;\n do {\n if ((unsigned char)(v1 - 97) > 25u) {\n v4 = v3++;\n result_1[v4] = v1;\n }\n v1 = *v2++;\n } while (v1);\n result = result_1;\n result_1[v3] = 0;\n } else {\n result = result_1;\n result_1[0] = 0;\n }\n return result;\n}" + }, + { + "index": 496, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\nint compare(const void *a, const void *b) {\n\n return (*(int*)a - *(int*)b);\n\n}\n\n\n\n", + "func": "void func0(int nums[], int len, int n, int result[]) {\n qsort(nums, len, sizeof(int), compare);\n for (int i = 0; i < n; i++) {\n result[i] = nums[i];\n }\n}", + "test": "int main() {\n\n int nums1[] = {25, 35, 22, 85, 14, 65, 75, 25, 58};\n\n int result1[3];\n\n int expected1[3] = {14, 22, 25};\n\n func0(nums1, 9, 3, result1);\n\n assert(memcmp(result1, expected1, 3 * sizeof(int)) == 0);\n\n\n\n int nums2[] = {25, 35, 22, 85, 14, 65, 75, 25, 58};\n\n int result2[2];\n\n int expected2[2] = {14, 22};\n\n func0(nums2, 9, 2, result2);\n\n assert(memcmp(result2, expected2, 2 * sizeof(int)) == 0);\n\n\n\n int nums3[] = {25, 35, 22, 85, 14, 65, 75, 22, 58};\n\n int result3[5];\n\n int expected3[5] = {14, 22, 22, 25, 35};\n\n func0(nums3, 9, 5, result3);\n\n assert(memcmp(result3, expected3, 5 * sizeof(int)) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmov %rcx,-0x28(%rbp)\nmov -0x1c(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x18(%rbp),%rax\nlea -0x4d(%rip),%rcx\nmov $0x4,%edx\nmov %rax,%rdi\ncallq 1080 \nmovl $0x0,-0x4(%rbp)\njmp 123d \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0x4(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x28(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x20(%rbp),%eax\njl 120c \nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+base], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_28], rcx\nmov eax, [rbp+var_1C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compare\nmov rcx, rdx; compar\nmov edx, 4; size\nmov rdi, rax; base\ncall _qsort\nmov [rbp+var_4], 0\njmp short loc_1240\nloc_120F:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_4], 1\nloc_1240:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_20]\njl short loc_120F\nnop\nnop\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(void *a1, int a2, int a3, __int64 a4)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+2Ch] [rbp-4h]\n\n qsort(a1, a2, 4uLL, compare);\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a3 )\n break;\n *(_DWORD *)(4LL * (int)i + a4) = *((_DWORD *)a1 + (int)i);\n }\n return result;\n}", + "ida_strip_asm": "sub_11CB:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+base], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_28], rcx\nmov eax, [rbp+var_1C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 4; size\nmov rdi, rax; base\ncall _qsort\nmov [rbp+var_4], 0\njmp short loc_1240\nloc_120F:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_4], 1\nloc_1240:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_20]\njl short loc_120F\nnop\nnop\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11CB(void *a1, int a2, int a3, __int64 a4)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+2Ch] [rbp-4h]\n\n qsort(a1, a2, 4uLL, compar);\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a3 )\n break;\n *(_DWORD *)(4LL * (int)i + a4) = *((_DWORD *)a1 + (int)i);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11CB(void *a1, int a2, int a3, long long a4) {\n long long result;\n unsigned int i;\n qsort(a1, a2, 4uLL, compar);\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a3) break;\n *(uint32_t *)(4LL * (int)i + a4) = *((uint32_t *)a1 + (int)i);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(void *a1, int a2, int a3, long long a4) {\n long long result;\n unsigned int i;\n qsort(a1, a2, 4uLL, compare);\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a3) break;\n *(uint32_t *)(4LL * (int)i + a4) = *((uint32_t *)a1 + (int)i);\n }\n return result;\n}" + }, + { + "index": 496, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\nint compare(const void *a, const void *b) {\n\n return (*(int*)a - *(int*)b);\n\n}\n\n\n\n", + "func": "void func0(int nums[], int len, int n, int result[]) {\n qsort(nums, len, sizeof(int), compare);\n for (int i = 0; i < n; i++) {\n result[i] = nums[i];\n }\n}", + "test": "int main() {\n\n int nums1[] = {25, 35, 22, 85, 14, 65, 75, 25, 58};\n\n int result1[3];\n\n int expected1[3] = {14, 22, 25};\n\n func0(nums1, 9, 3, result1);\n\n assert(memcmp(result1, expected1, 3 * sizeof(int)) == 0);\n\n\n\n int nums2[] = {25, 35, 22, 85, 14, 65, 75, 25, 58};\n\n int result2[2];\n\n int expected2[2] = {14, 22};\n\n func0(nums2, 9, 2, result2);\n\n assert(memcmp(result2, expected2, 2 * sizeof(int)) == 0);\n\n\n\n int nums3[] = {25, 35, 22, 85, 14, 65, 75, 22, 58};\n\n int result3[5];\n\n int expected3[5] = {14, 22, 22, 25, 35};\n\n func0(nums3, 9, 5, result3);\n\n assert(memcmp(result3, expected3, 5 * sizeof(int)) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nmov %edx,%r12d\nmov %rcx,%rbp\nmovslq %esi,%rsi\nlea -0x24(%rip),%rcx\nmov $0x4,%edx\ncallq 1080 \ntest %r12d,%r12d\njle 11f9 \nlea -0x1(%r12),%ecx\nmov $0x0,%eax\nmov (%rbx,%rax,4),%edx\nmov %edx,0x0(%rbp,%rax,4)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rcx,%rdx\njne 11e6 \npop %rbx\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbp, rdi\nmov ebx, edx\nmov r12, rcx\nmovsxd rsi, esi; nmemb\nlea rcx, compare; compar\nmov edx, 4; size\ncall _qsort\ntest ebx, ebx\njle short loc_11F7\nmovsxd rcx, ebx\nshl rcx, 2\nmov eax, 0\nloc_11E6:\nmov edx, [rbp+rax+0]\nmov [r12+rax], edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_11E6\nloc_11F7:\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "void __fastcall func0(char *a1, int a2, int a3, __int64 a4)\n{\n __int64 v6; // rax\n\n qsort(a1, a2, 4uLL, compare);\n if ( a3 > 0 )\n {\n v6 = 0LL;\n do\n {\n *(_DWORD *)(a4 + v6) = *(_DWORD *)&a1[v6];\n v6 += 4LL;\n }\n while ( v6 != 4LL * a3 );\n }\n}", + "ida_strip_asm": "sub_11B2:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbp, rdi\nmov ebx, edx\nmov r12, rcx\nmovsxd rsi, esi; nmemb\nlea rcx, compar; compar\nmov edx, 4; size\ncall _qsort\ntest ebx, ebx\njle short loc_11F7\nmovsxd rcx, ebx\nshl rcx, 2\nmov eax, 0\nloc_11E6:\nmov edx, [rbp+rax+0]\nmov [r12+rax], edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_11E6\nloc_11F7:\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "void __fastcall sub_11B2(char *a1, int a2, int a3, __int64 a4)\n{\n __int64 v6; // rax\n\n qsort(a1, a2, 4uLL, compar);\n if ( a3 > 0 )\n {\n v6 = 0LL;\n do\n {\n *(_DWORD *)(a4 + v6) = *(_DWORD *)&a1[v6];\n v6 += 4LL;\n }\n while ( v6 != 4LL * a3 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_11B2(char *a1, int a2, int a3, long long a4) {\n long long v6;\n qsort(a1, a2, 4uLL, compar);\n if (a3 > 0) {\n v6 = 0LL;\n do {\n *(uint32_t *)(a4 + v6) = *(uint32_t *)&a1[v6];\n v6 += 4LL;\n } while (v6 != 4LL * a3);\n }\n}", + "ida_pseudo_norm": "void func0(char *a1, int a2, int a3, long long a4) {\n long long v6;\n qsort(a1, a2, 4uLL, compare);\n if (a3 > 0) {\n v6 = 0LL;\n do {\n *(uint32_t *)(a4 + v6) = *(uint32_t *)&a1[v6];\n v6 += 4LL;\n } while (v6 != 4LL * a3);\n }\n}" + }, + { + "index": 496, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\nint compare(const void *a, const void *b) {\n\n return (*(int*)a - *(int*)b);\n\n}\n\n\n\n", + "func": "void func0(int nums[], int len, int n, int result[]) {\n qsort(nums, len, sizeof(int), compare);\n for (int i = 0; i < n; i++) {\n result[i] = nums[i];\n }\n}", + "test": "int main() {\n\n int nums1[] = {25, 35, 22, 85, 14, 65, 75, 25, 58};\n\n int result1[3];\n\n int expected1[3] = {14, 22, 25};\n\n func0(nums1, 9, 3, result1);\n\n assert(memcmp(result1, expected1, 3 * sizeof(int)) == 0);\n\n\n\n int nums2[] = {25, 35, 22, 85, 14, 65, 75, 25, 58};\n\n int result2[2];\n\n int expected2[2] = {14, 22};\n\n func0(nums2, 9, 2, result2);\n\n assert(memcmp(result2, expected2, 2 * sizeof(int)) == 0);\n\n\n\n int nums3[] = {25, 35, 22, 85, 14, 65, 75, 22, 58};\n\n int result3[5];\n\n int expected3[5] = {14, 22, 22, 25, 35};\n\n func0(nums3, 9, 5, result3);\n\n assert(memcmp(result3, expected3, 5 * sizeof(int)) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmovslq %esi,%rsi\nmov %edx,%r12d\nmov $0x4,%edx\npush %rbp\nmov %rcx,%rbp\nlea -0x2c(%rip),%rcx\npush %rbx\nmov %rdi,%rbx\ncallq 1070 \ntest %r12d,%r12d\njle 141b \nlea -0x1(%r12),%ecx\nxor %eax,%eax\nnopl 0x0(%rax)\nmov (%rbx,%rax,4),%edx\nmov %edx,0x0(%rbp,%rax,4)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rcx,%rdx\njne 1408 \npop %rbx\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\npush r12\nmovsxd rsi, esi; nmemb\nmov r12, rcx\nlea rcx, compare; compar\npush rbp\nmov rbp, rdi\npush rbx\nmov ebx, edx\nmov edx, 4; size\ncall _qsort\ntest ebx, ebx\njle short loc_13C9\nmovsxd rcx, ebx\nxor eax, eax\nshl rcx, 2\nnop dword ptr [rax+00000000h]\nloc_13B8:\nmov edx, [rbp+rax+0]\nmov [r12+rax], edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_13B8\nloc_13C9:\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "void __fastcall func0(char *a1, int a2, int a3, __int64 a4)\n{\n __int64 v6; // rax\n\n qsort(a1, a2, 4uLL, compare);\n if ( a3 > 0 )\n {\n v6 = 0LL;\n do\n {\n *(_DWORD *)(a4 + v6) = *(_DWORD *)&a1[v6];\n v6 += 4LL;\n }\n while ( v6 != 4LL * a3 );\n }\n}", + "ida_strip_asm": "sub_1380:\nendbr64\npush r12\nmovsxd rsi, esi; nmemb\nmov r12, rcx\nlea rcx, compar; compar\npush rbp\nmov rbp, rdi\npush rbx\nmov ebx, edx\nmov edx, 4; size\ncall _qsort\ntest ebx, ebx\njle short loc_13C9\nmovsxd rcx, ebx\nxor eax, eax\nshl rcx, 2\nnop dword ptr [rax+00000000h]\nloc_13B8:\nmov edx, [rbp+rax+0]\nmov [r12+rax], edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_13B8\nloc_13C9:\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "void __fastcall sub_1380(char *a1, int a2, int a3, __int64 a4)\n{\n __int64 v6; // rax\n\n qsort(a1, a2, 4uLL, compar);\n if ( a3 > 0 )\n {\n v6 = 0LL;\n do\n {\n *(_DWORD *)(a4 + v6) = *(_DWORD *)&a1[v6];\n v6 += 4LL;\n }\n while ( v6 != 4LL * a3 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1380(char *a1, int a2, int a3, long long a4) {\n long long v6;\n qsort(a1, a2, 4uLL, compar);\n if (a3 > 0) {\n v6 = 0LL;\n do {\n *(uint32_t *)(a4 + v6) = *(uint32_t *)&a1[v6];\n v6 += 4LL;\n } while (v6 != 4LL * a3);\n }\n}", + "ida_pseudo_norm": "void func0(char *a1, int a2, int a3, long long a4) {\n long long v6;\n qsort(a1, a2, 4uLL, compare);\n if (a3 > 0) {\n v6 = 0LL;\n do {\n *(uint32_t *)(a4 + v6) = *(uint32_t *)&a1[v6];\n v6 += 4LL;\n } while (v6 != 4LL * a3);\n }\n}" + }, + { + "index": 496, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\nint compare(const void *a, const void *b) {\n\n return (*(int*)a - *(int*)b);\n\n}\n\n\n\n", + "func": "void func0(int nums[], int len, int n, int result[]) {\n qsort(nums, len, sizeof(int), compare);\n for (int i = 0; i < n; i++) {\n result[i] = nums[i];\n }\n}", + "test": "int main() {\n\n int nums1[] = {25, 35, 22, 85, 14, 65, 75, 25, 58};\n\n int result1[3];\n\n int expected1[3] = {14, 22, 25};\n\n func0(nums1, 9, 3, result1);\n\n assert(memcmp(result1, expected1, 3 * sizeof(int)) == 0);\n\n\n\n int nums2[] = {25, 35, 22, 85, 14, 65, 75, 25, 58};\n\n int result2[2];\n\n int expected2[2] = {14, 22};\n\n func0(nums2, 9, 2, result2);\n\n assert(memcmp(result2, expected2, 2 * sizeof(int)) == 0);\n\n\n\n int nums3[] = {25, 35, 22, 85, 14, 65, 75, 22, 58};\n\n int result3[5];\n\n int expected3[5] = {14, 22, 22, 25, 35};\n\n func0(nums3, 9, 5, result3);\n\n assert(memcmp(result3, expected3, 5 * sizeof(int)) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmovslq %esi,%rsi\nmov %edx,%r12d\nmov $0x4,%edx\npush %rbp\nmov %rcx,%rbp\nlea -0x2c(%rip),%rcx\npush %rbx\nmov %rdi,%rbx\ncallq 1070 \ntest %r12d,%r12d\njle 142b \nlea 0xf(%rbx),%rdx\nlea -0x1(%r12),%eax\nsub %rbp,%rdx\ncmp $0x1e,%rdx\njbe 1430 \ncmp $0x3,%eax\njbe 1430 \nmov %r12d,%edx\nxor %eax,%eax\nshr $0x2,%edx\nshl $0x4,%rdx\nnopl (%rax)\nmovdqu (%rbx,%rax,1),%xmm0\nmovups %xmm0,0x0(%rbp,%rax,1)\nadd $0x10,%rax\ncmp %rdx,%rax\njne 13e0 \nmov %r12d,%eax\nand $0xfffffffc,%eax\ntest $0x3,%r12b\nje 142b \nmov %eax,%edx\nmov (%rbx,%rdx,4),%ecx\nmov %ecx,0x0(%rbp,%rdx,4)\nlea 0x1(%rax),%edx\ncmp %edx,%r12d\njle 142b \nmovslq %edx,%rdx\nadd $0x2,%eax\nmov (%rbx,%rdx,4),%ecx\nmov %ecx,0x0(%rbp,%rdx,4)\ncmp %eax,%r12d\njle 142b \ncltq\nmov (%rbx,%rax,4),%edx\nmov %edx,0x0(%rbp,%rax,4)\npop %rbx\npop %rbp\npop %r12\nretq\nmov %eax,%edx\nxor %eax,%eax\nnopl 0x0(%rax)\nmov (%rbx,%rax,4),%ecx\nmov %ecx,0x0(%rbp,%rax,4)\nmov %rax,%rcx\nadd $0x1,%rax\ncmp %rdx,%rcx\njne 1438 \npop %rbx\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\npush r12\nmovsxd rsi, esi; nmemb\nmov r12, rcx\nlea rcx, compare; compar\npush rbp\nmov rbp, rdi\npush rbx\nmovsxd rbx, edx\nmov edx, 4; size\ncall _qsort\ntest ebx, ebx\njle short loc_13E1\nlea eax, [rbx-1]\ncmp eax, 2\njbe short loc_13C1\nlea rdx, [rbp+4]\nmov rax, r12\nsub rax, rdx\ncmp rax, 8\nja short loc_13F0\nloc_13C1:\nshl rbx, 2\nxor eax, eax\nnop word ptr [rax+rax+00000000h]\nloc_13D0:\nmov edx, [rbp+rax+0]\nmov [r12+rax], edx\nadd rax, 4\ncmp rbx, rax\njnz short loc_13D0\nloc_13E1:\npop rbx\npop rbp\npop r12\nretn\nloc_13F0:\nmov edx, ebx\nxor eax, eax\nshr edx, 2\nshl rdx, 4\nnop dword ptr [rax+rax+00h]\nloc_1400:\nmovdqu xmm0, xmmword ptr [rbp+rax+0]\nmovups xmmword ptr [r12+rax], xmm0\nadd rax, 10h\ncmp rax, rdx\njnz short loc_1400\nmov eax, ebx\nand eax, 0FFFFFFFCh\ntest bl, 3\njz short loc_13E1\nmov ecx, eax\nmov esi, [rbp+rcx*4+0]\nlea rdx, ds:0[rcx*4]\nmov [r12+rcx*4], esi\nlea ecx, [rax+1]\ncmp ebx, ecx\njle short loc_13E1\nmov ecx, [rbp+rdx+4]\nadd eax, 2\nmov [r12+rdx+4], ecx\ncmp ebx, eax\njle short loc_13E1\nmov eax, [rbp+rdx+8]\nmov [r12+rdx+8], eax\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "void __fastcall func0(char *a1, int a2, int a3, __int64 a4)\n{\n __int64 v5; // rbx\n __int64 v6; // rbx\n __int64 v7; // rax\n __int64 v8; // rax\n unsigned int v9; // eax\n __int64 v10; // rdx\n\n v5 = a3;\n qsort(a1, a2, 4uLL, compare);\n if ( (int)v5 > 0 )\n {\n if ( (unsigned int)(v5 - 1) > 2 && (unsigned __int64)(a4 - (_QWORD)(a1 + 4)) > 8 )\n {\n v8 = 0LL;\n do\n {\n *(__m128i *)(a4 + v8) = _mm_loadu_si128((const __m128i *)&a1[v8]);\n v8 += 16LL;\n }\n while ( v8 != 16LL * ((unsigned int)v5 >> 2) );\n v9 = v5 & 0xFFFFFFFC;\n if ( (v5 & 3) != 0 )\n {\n v10 = 4LL * v9;\n *(_DWORD *)(a4 + v10) = *(_DWORD *)&a1[v10];\n if ( (int)v5 > (int)(v9 + 1) )\n {\n *(_DWORD *)(a4 + v10 + 4) = *(_DWORD *)&a1[v10 + 4];\n if ( (int)v5 > (int)(v9 + 2) )\n *(_DWORD *)(a4 + v10 + 8) = *(_DWORD *)&a1[v10 + 8];\n }\n }\n }\n else\n {\n v6 = 4 * v5;\n v7 = 0LL;\n do\n {\n *(_DWORD *)(a4 + v7) = *(_DWORD *)&a1[v7];\n v7 += 4LL;\n }\n while ( v6 != v7 );\n }\n }\n}", + "ida_strip_asm": "sub_1380:\nendbr64\npush r12\nmovsxd rsi, esi; nmemb\nmov r12, rcx\nlea rcx, compar; compar\npush rbp\nmov rbp, rdi\npush rbx\nmovsxd rbx, edx\nmov edx, 4; size\ncall _qsort\ntest ebx, ebx\njle short loc_13E1\nlea eax, [rbx-1]\ncmp eax, 2\njbe short loc_13C1\nlea rdx, [rbp+4]\nmov rax, r12\nsub rax, rdx\ncmp rax, 8\nja short loc_13F0\nloc_13C1:\nshl rbx, 2\nxor eax, eax\nnop word ptr [rax+rax+00000000h]\nloc_13D0:\nmov edx, [rbp+rax+0]\nmov [r12+rax], edx\nadd rax, 4\ncmp rbx, rax\njnz short loc_13D0\nloc_13E1:\npop rbx\npop rbp\npop r12\nretn\nloc_13F0:\nmov edx, ebx\nxor eax, eax\nshr edx, 2\nshl rdx, 4\nnop dword ptr [rax+rax+00h]\nloc_1400:\nmovdqu xmm0, xmmword ptr [rbp+rax+0]\nmovups xmmword ptr [r12+rax], xmm0\nadd rax, 10h\ncmp rax, rdx\njnz short loc_1400\nmov eax, ebx\nand eax, 0FFFFFFFCh\ntest bl, 3\njz short loc_13E1\nmov ecx, eax\nmov esi, [rbp+rcx*4+0]\nlea rdx, ds:0[rcx*4]\nmov [r12+rcx*4], esi\nlea ecx, [rax+1]\ncmp ebx, ecx\njle short loc_13E1\nmov ecx, [rbp+rdx+4]\nadd eax, 2\nmov [r12+rdx+4], ecx\ncmp ebx, eax\njle short loc_13E1\nmov eax, [rbp+rdx+8]\nmov [r12+rdx+8], eax\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "void __fastcall sub_1380(char *a1, int a2, int a3, __int64 a4)\n{\n __int64 v5; // rbx\n __int64 v6; // rbx\n __int64 v7; // rax\n __int64 v8; // rax\n unsigned int v9; // eax\n __int64 v10; // rdx\n\n v5 = a3;\n qsort(a1, a2, 4uLL, compar);\n if ( (int)v5 > 0 )\n {\n if ( (unsigned int)(v5 - 1) > 2 && (unsigned __int64)(a4 - (_QWORD)(a1 + 4)) > 8 )\n {\n v8 = 0LL;\n do\n {\n *(__m128i *)(a4 + v8) = _mm_loadu_si128((const __m128i *)&a1[v8]);\n v8 += 16LL;\n }\n while ( v8 != 16LL * ((unsigned int)v5 >> 2) );\n v9 = v5 & 0xFFFFFFFC;\n if ( (v5 & 3) != 0 )\n {\n v10 = 4LL * v9;\n *(_DWORD *)(a4 + v10) = *(_DWORD *)&a1[v10];\n if ( (int)v5 > (int)(v9 + 1) )\n {\n *(_DWORD *)(a4 + v10 + 4) = *(_DWORD *)&a1[v10 + 4];\n if ( (int)v5 > (int)(v9 + 2) )\n *(_DWORD *)(a4 + v10 + 8) = *(_DWORD *)&a1[v10 + 8];\n }\n }\n }\n else\n {\n v6 = 4 * v5;\n v7 = 0LL;\n do\n {\n *(_DWORD *)(a4 + v7) = *(_DWORD *)&a1[v7];\n v7 += 4LL;\n }\n while ( v6 != v7 );\n }\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1380(char *a1, int a2, int a3, long long a4) {\n long long v5;\n long long v6;\n long long v7;\n long long v8;\n unsigned int v9;\n long long v10;\n v5 = a3;\n qsort(a1, a2, 4uLL, compar);\n if ((int)v5 > 0) {\n if ((unsigned int)(v5 - 1) > 2 &&\n (unsigned long long)(a4 - (uint64_t)(a1 + 4)) > 8) {\n v8 = 0LL;\n do {\n *(__m128i *)(a4 + v8) = _mm_loadu_si128((const __m128i *)&a1[v8]);\n v8 += 16LL;\n } while (v8 != 16LL * ((unsigned int)v5 >> 2));\n v9 = v5 & 4294967292;\n if ((v5 & 3) != 0) {\n v10 = 4LL * v9;\n *(uint32_t *)(a4 + v10) = *(uint32_t *)&a1[v10];\n if ((int)v5 > (int)(v9 + 1)) {\n *(uint32_t *)(a4 + v10 + 4) = *(uint32_t *)&a1[v10 + 4];\n if ((int)v5 > (int)(v9 + 2))\n *(uint32_t *)(a4 + v10 + 8) = *(uint32_t *)&a1[v10 + 8];\n }\n }\n } else {\n v6 = 4 * v5;\n v7 = 0LL;\n do {\n *(uint32_t *)(a4 + v7) = *(uint32_t *)&a1[v7];\n v7 += 4LL;\n } while (v6 != v7);\n }\n }\n}", + "ida_pseudo_norm": "void func0(char *a1, int a2, int a3, long long a4) {\n long long v5;\n long long v6;\n long long v7;\n long long v8;\n unsigned int v9;\n long long v10;\n v5 = a3;\n qsort(a1, a2, 4uLL, compare);\n if ((int)v5 > 0) {\n if ((unsigned int)(v5 - 1) > 2 &&\n (unsigned long long)(a4 - (uint64_t)(a1 + 4)) > 8) {\n v8 = 0LL;\n do {\n *(__m128i *)(a4 + v8) = _mm_loadu_si128((const __m128i *)&a1[v8]);\n v8 += 16LL;\n } while (v8 != 16LL * ((unsigned int)v5 >> 2));\n v9 = v5 & 4294967292;\n if ((v5 & 3) != 0) {\n v10 = 4LL * v9;\n *(uint32_t *)(a4 + v10) = *(uint32_t *)&a1[v10];\n if ((int)v5 > (int)(v9 + 1)) {\n *(uint32_t *)(a4 + v10 + 4) = *(uint32_t *)&a1[v10 + 4];\n if ((int)v5 > (int)(v9 + 2))\n *(uint32_t *)(a4 + v10 + 8) = *(uint32_t *)&a1[v10 + 8];\n }\n }\n } else {\n v6 = 4 * v5;\n v7 = 0LL;\n do {\n *(uint32_t *)(a4 + v7) = *(uint32_t *)&a1[v7];\n v7 += 4LL;\n } while (v6 != v7);\n }\n }\n}" + }, + { + "index": 497, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(double r, double h) {\n double l = sqrt(r * r + h * h);\n double SA = M_PI * r * (r + l);\n return SA;\n}", + "test": "int main() {\n\n assert(func0(5, 12) == 282.7433388230814);\n\n assert(func0(10, 15) == 880.5179353159282);\n\n assert(func0(19, 17) == 2655.923961165254);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmovsd %xmm0,-0x18(%rbp)\nmovsd %xmm1,-0x20(%rbp)\nmovsd -0x18(%rbp),%xmm0\nmovapd %xmm0,%xmm1\nmulsd %xmm0,%xmm1\nmovsd -0x20(%rbp),%xmm0\nmulsd %xmm0,%xmm0\naddsd %xmm1,%xmm0\ncallq 1070 \nmovq %xmm0,%rax\nmov %rax,-0x10(%rbp)\nmovsd -0x18(%rbp),%xmm1\nmovsd 0xf0c(%rip),%xmm0\nmulsd %xmm0,%xmm1\nmovsd -0x18(%rbp),%xmm0\naddsd -0x10(%rbp),%xmm0\nmulsd %xmm1,%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmovsd -0x8(%rbp),%xmm0\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmovsd [rbp+var_18], xmm0\nmovsd [rbp+var_20], xmm1\nmovsd xmm0, [rbp+var_18]\nmovapd xmm1, xmm0\nmulsd xmm1, xmm0\nmovsd xmm0, [rbp+var_20]\nmulsd xmm0, xmm0\naddsd xmm1, xmm0\nmovq rax, xmm1\nmovq xmm0, rax; x\ncall _sqrt\nmovq rax, xmm0\nmov [rbp+var_10], rax\nmovsd xmm1, [rbp+var_18]\nmovsd xmm0, cs:qword_20A0\nmulsd xmm1, xmm0\nmovsd xmm0, [rbp+var_18]\naddsd xmm0, [rbp+var_10]\nmulsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "double __fastcall func0(double a1, double a2)\n{\n return (a1 + sqrt(a1 * a1 + a2 * a2)) * (a1 * 3.141592653589793);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmovsd [rbp+var_18], xmm0\nmovsd [rbp+var_20], xmm1\nmovsd xmm0, [rbp+var_18]\nmovapd xmm1, xmm0\nmulsd xmm1, xmm0\nmovsd xmm0, [rbp+var_20]\nmulsd xmm0, xmm0\naddsd xmm1, xmm0\nmovq rax, xmm1\nmovq xmm0, rax; x\ncall _sqrt\nmovq rax, xmm0\nmov [rbp+var_10], rax\nmovsd xmm1, [rbp+var_18]\nmovsd xmm0, cs:qword_20A0\nmulsd xmm1, xmm0\nmovsd xmm0, [rbp+var_18]\naddsd xmm0, [rbp+var_10]\nmulsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "double __fastcall sub_1169(double a1, double a2)\n{\n return (a1 + sqrt(a1 * a1 + a2 * a2)) * (a1 * 3.141592653589793);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1169(double a1, double a2) {\n return (a1 + sqrt(a1 * a1 + a2 * a2)) * (a1 * 3.141592653589793);\n}", + "ida_pseudo_norm": "double func0(double a1, double a2) {\n return (a1 + sqrt(a1 * a1 + a2 * a2)) * (a1 * 3.141592653589793);\n}" + }, + { + "index": 497, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(double r, double h) {\n double l = sqrt(r * r + h * h);\n double SA = M_PI * r * (r + l);\n return SA;\n}", + "test": "int main() {\n\n assert(func0(5, 12) == 282.7433388230814);\n\n assert(func0(10, 15) == 880.5179353159282);\n\n assert(func0(19, 17) == 2655.923961165254);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x18,%rsp\nmovsd %xmm0,0x8(%rsp)\nmulsd %xmm0,%xmm0\nmulsd %xmm1,%xmm1\naddsd %xmm1,%xmm0\nmovapd %xmm0,%xmm3\nsqrtsd %xmm3,%xmm3\nmovsd %xmm3,(%rsp)\npxor %xmm1,%xmm1\nucomisd %xmm0,%xmm1\nja 11ba \nmovsd 0x8(%rsp),%xmm0\nmovapd %xmm0,%xmm1\nmulsd 0xf14(%rip),%xmm1\naddsd (%rsp),%xmm0\nmulsd %xmm1,%xmm0\nadd $0x18,%rsp\nretq\ncallq 1070 \njmp 119a \n", + "ida_asm": "func0:\nendbr64\nmovapd xmm2, xmm0\nmulsd xmm0, xmm0\nmulsd xmm1, xmm1\naddsd xmm0, xmm1\nsqrtsd xmm0, xmm0\nmovapd xmm1, xmm2\nmulsd xmm1, cs:qword_20A8\naddsd xmm2, xmm0\nmulsd xmm1, xmm2\nmovapd xmm0, xmm1\nretn", + "ida_pseudo": "__int128 __usercall func0@(__m128 a1@, double a2@)\n{\n __int128 v2; // xmm1\n\n *((_QWORD *)&v2 + 1) = a1.m128_u64[1];\n *(double *)&v2 = *(double *)a1.m128_u64\n * 3.141592653589793\n * (*(double *)a1.m128_u64 + sqrt(*(double *)a1.m128_u64 * *(double *)a1.m128_u64 + a2 * a2));\n return v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmovapd xmm2, xmm0\nmulsd xmm0, xmm0\nmulsd xmm1, xmm1\naddsd xmm0, xmm1\nsqrtsd xmm0, xmm0\nmovapd xmm1, xmm2\nmulsd xmm1, cs:qword_20A8\naddsd xmm2, xmm0\nmulsd xmm1, xmm2\nmovapd xmm0, xmm1\nretn", + "ida_strip_pseudo": "__int128 __usercall sub_1149@(__m128 a1@, double a2@)\n{\n __int128 v2; // xmm1\n\n *((_QWORD *)&v2 + 1) = a1.m128_u64[1];\n *(double *)&v2 = *(double *)a1.m128_u64\n * 3.141592653589793\n * (*(double *)a1.m128_u64 + sqrt(*(double *)a1.m128_u64 * *(double *)a1.m128_u64 + a2 * a2));\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__int128 __usercall sub_1149 @(__m128 a1 @, double a2 @) {\n __int128 v2;\n *((uint64_t *)&v2 + 1) = a1.m128_u64[1];\n *(double *)&v2 =\n *(double *)a1.m128_u64 * 3.141592653589793 *\n (*(double *)a1.m128_u64 +\n sqrt(*(double *)a1.m128_u64 * *(double *)a1.m128_u64 + a2 * a2));\n return v2;\n}", + "ida_pseudo_norm": "__int128 __usercall func0 @(__m128 a1 @, double a2 @) {\n __int128 v2;\n *((uint64_t *)&v2 + 1) = a1.m128_u64[1];\n *(double *)&v2 =\n *(double *)a1.m128_u64 * 3.141592653589793 *\n (*(double *)a1.m128_u64 +\n sqrt(*(double *)a1.m128_u64 * *(double *)a1.m128_u64 + a2 * a2));\n return v2;\n}" + }, + { + "index": 498, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int x, int y) {\n int gcd = 1;\n if (x % y == 0) {\n return y;\n }\n for (int k = y / 2; k > 0; k--) {\n if (x % k == 0 && y % k == 0) {\n gcd = k;\n break;\n }\n }\n return gcd;\n}", + "test": "int main() {\n\n assert(func0(12, 17) == 1);\n\n assert(func0(4, 6) == 2);\n\n assert(func0(2, 9) == 1);\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmovl $0x1,-0x8(%rbp)\nmov -0x14(%rbp),%eax\ncltd\nidivl -0x18(%rbp)\nmov %edx,%eax\ntest %eax,%eax\njne 1170 \nmov -0x18(%rbp),%eax\njmp 11b0 \nmov -0x18(%rbp),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nmov %eax,-0x4(%rbp)\njmp 11a7 \nmov -0x14(%rbp),%eax\ncltd\nidivl -0x4(%rbp)\nmov %edx,%eax\ntest %eax,%eax\njne 11a3 \nmov -0x18(%rbp),%eax\ncltd\nidivl -0x4(%rbp)\nmov %edx,%eax\ntest %eax,%eax\njne 11a3 \nmov -0x4(%rbp),%eax\nmov %eax,-0x8(%rbp)\njmp 11ad \nsubl $0x1,-0x4(%rbp)\ncmpl $0x0,-0x4(%rbp)\njg 1181 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_8], 1\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_18]\nmov eax, edx\ntest eax, eax\njnz short loc_1170\nmov eax, [rbp+var_18]\njmp short loc_11B0\nloc_1170:\nmov eax, [rbp+var_18]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_4], eax\njmp short loc_11A7\nloc_1181:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njnz short loc_11A3\nmov eax, [rbp+var_18]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njnz short loc_11A3\nmov eax, [rbp+var_4]\nmov [rbp+var_8], eax\njmp short loc_11AD\nloc_11A3:\nsub [rbp+var_4], 1\nloc_11A7:\ncmp [rbp+var_4], 0\njg short loc_1181\nloc_11AD:\nmov eax, [rbp+var_8]\nloc_11B0:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, signed int a2)\n{\n unsigned int v3; // [rsp+10h] [rbp-8h]\n int i; // [rsp+14h] [rbp-4h]\n\n v3 = 1;\n if ( !(a1 % a2) )\n return (unsigned int)a2;\n for ( i = a2 / 2; i > 0; --i )\n {\n if ( !(a1 % i) && !(a2 % i) )\n return (unsigned int)i;\n }\n return v3;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_8], 1\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_18]\nmov eax, edx\ntest eax, eax\njnz short loc_1170\nmov eax, [rbp+var_18]\njmp short loc_11B0\nloc_1170:\nmov eax, [rbp+var_18]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_4], eax\njmp short loc_11A7\nloc_1181:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njnz short loc_11A3\nmov eax, [rbp+var_18]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njnz short loc_11A3\nmov eax, [rbp+var_4]\nmov [rbp+var_8], eax\njmp short loc_11AD\nloc_11A3:\nsub [rbp+var_4], 1\nloc_11A7:\ncmp [rbp+var_4], 0\njg short loc_1181\nloc_11AD:\nmov eax, [rbp+var_8]\nloc_11B0:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, signed int a2)\n{\n unsigned int v3; // [rsp+10h] [rbp-8h]\n int i; // [rsp+14h] [rbp-4h]\n\n v3 = 1;\n if ( !(a1 % a2) )\n return (unsigned int)a2;\n for ( i = a2 / 2; i > 0; --i )\n {\n if ( !(a1 % i) && !(a2 % i) )\n return (unsigned int)i;\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, signed int a2) {\n unsigned int v3;\n int i;\n v3 = 1;\n if (!(a1 % a2)) return (unsigned int)a2;\n for (i = a2 / 2; i > 0; --i) {\n if (!(a1 % i) && !(a2 % i)) return (unsigned int)i;\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(int a1, signed int a2) {\n unsigned int v3;\n int i;\n v3 = 1;\n if (!(a1 % a2)) return (unsigned int)a2;\n for (i = a2 / 2; i > 0; --i) {\n if (!(a1 % i) && !(a2 % i)) return (unsigned int)i;\n }\n return v3;\n}" + }, + { + "index": 498, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int x, int y) {\n int gcd = 1;\n if (x % y == 0) {\n return y;\n }\n for (int k = y / 2; k > 0; k--) {\n if (x % k == 0 && y % k == 0) {\n gcd = k;\n break;\n }\n }\n return gcd;\n}", + "test": "int main() {\n\n assert(func0(12, 17) == 1);\n\n assert(func0(4, 6) == 2);\n\n assert(func0(2, 9) == 1);\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %edi,%eax\ncltd\nidiv %esi\nmov %esi,%ecx\ntest %edx,%edx\nje 118b \nshr $0x1f,%ecx\nadd %esi,%ecx\nsar %ecx\ncmp $0x1,%esi\njg 1172 \nmov $0x1,%ecx\njmp 118b \nsub $0x1,%ecx\ntest %ecx,%ecx\njle 1186 \nmov %edi,%eax\ncltd\nidiv %ecx\ntest %edx,%edx\njne 116b \nmov %esi,%eax\ncltd\nidiv %ecx\ntest %edx,%edx\njne 116b \njmp 118b \nmov $0x1,%ecx\nmov %ecx,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov eax, edi\ncdq\nidiv esi\nmov ecx, esi\ntest edx, edx\njz short loc_118C\nshr ecx, 1Fh\nadd ecx, esi\nsar ecx, 1\ncmp esi, 1\njg short loc_1170\nmov ecx, 1\njmp short loc_118C\nloc_116B:\nsub ecx, 1\njz short loc_1187\nloc_1170:\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_116B\nmov eax, esi\ncdq\nidiv ecx\ntest edx, edx\njz short loc_118C\nsub ecx, 1\njmp short loc_1170\nloc_1187:\nmov ecx, 1\nloc_118C:\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n int v2; // ecx\n\n v2 = a2;\n if ( a1 % a2 )\n {\n v2 = a2 / 2;\n if ( a2 > 1 )\n {\n do\n {\n while ( !(a1 % v2) )\n {\n if ( !(a2 % v2) )\n return (unsigned int)v2;\n --v2;\n }\n --v2;\n }\n while ( v2 );\n return 1;\n }\n else\n {\n return 1;\n }\n }\n return (unsigned int)v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmov eax, edi\ncdq\nidiv esi\nmov ecx, esi\ntest edx, edx\njz short loc_118C\nshr ecx, 1Fh\nadd ecx, esi\nsar ecx, 1\ncmp esi, 1\njg short loc_1170\nmov ecx, 1\njmp short loc_118C\nloc_116B:\nsub ecx, 1\njz short loc_1187\nloc_1170:\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_116B\nmov eax, esi\ncdq\nidiv ecx\ntest edx, edx\njz short loc_118C\nsub ecx, 1\njmp short loc_1170\nloc_1187:\nmov ecx, 1\nloc_118C:\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2)\n{\n int v2; // ecx\n\n v2 = a2;\n if ( a1 % a2 )\n {\n v2 = a2 / 2;\n if ( a2 > 1 )\n {\n do\n {\n while ( !(a1 % v2) )\n {\n if ( !(a2 % v2) )\n return (unsigned int)v2;\n --v2;\n }\n --v2;\n }\n while ( v2 );\n return 1;\n }\n else\n {\n return 1;\n }\n }\n return (unsigned int)v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2) {\n int v2;\n v2 = a2;\n if (a1 % a2) {\n v2 = a2 / 2;\n if (a2 > 1) {\n do {\n while (!(a1 % v2)) {\n if (!(a2 % v2)) return (unsigned int)v2;\n --v2;\n }\n --v2;\n } while (v2);\n return 1;\n } else {\n return 1;\n }\n }\n return (unsigned int)v2;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n int v2;\n v2 = a2;\n if (a1 % a2) {\n v2 = a2 / 2;\n if (a2 > 1) {\n do {\n while (!(a1 % v2)) {\n if (!(a2 % v2)) return (unsigned int)v2;\n --v2;\n }\n --v2;\n } while (v2);\n return 1;\n } else {\n return 1;\n }\n }\n return (unsigned int)v2;\n}" + }, + { + "index": 498, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int x, int y) {\n int gcd = 1;\n if (x % y == 0) {\n return y;\n }\n for (int k = y / 2; k > 0; k--) {\n if (x % k == 0 && y % k == 0) {\n gcd = k;\n break;\n }\n }\n return gcd;\n}", + "test": "int main() {\n\n assert(func0(12, 17) == 1);\n\n assert(func0(4, 6) == 2);\n\n assert(func0(2, 9) == 1);\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov %edi,%eax\ncltd\nidiv %esi\ntest %edx,%edx\nje 1250 \njmp 1200 \nmov %esi,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0_part_0:\nmov ecx, esi\nshr ecx, 1Fh\nadd ecx, esi\nsar ecx, 1\ncmp esi, 1\njle short loc_1233\nxchg ax, ax\nloc_1210:\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_122E\nloc_1219:\nmov eax, esi\ncdq\nidiv ecx\ntest edx, edx\njz short loc_1238\nmov eax, edi\nsub ecx, 1\ncdq\nidiv ecx\ntest edx, edx\njz short loc_1219\nloc_122E:\nsub ecx, 1\njnz short loc_1210\nloc_1233:\nmov ecx, 1\nloc_1238:\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0_part_0(int a1, int a2)\n{\n int v2; // ecx\n\n v2 = a2 / 2;\n if ( a2 <= 1 )\n {\n return 1;\n }\n else\n {\n while ( a1 % v2 )\n {\nLABEL_5:\n if ( !--v2 )\n return 1;\n }\n while ( a2 % v2 )\n {\n --v2;\n if ( a1 % v2 )\n goto LABEL_5;\n }\n }\n return (unsigned int)v2;\n}", + "ida_strip_asm": "sub_1200:\nmov ecx, esi\nshr ecx, 1Fh\nadd ecx, esi\nsar ecx, 1\ncmp esi, 1\njle short loc_1233\nxchg ax, ax\nloc_1210:\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_122E\nloc_1219:\nmov eax, esi\ncdq\nidiv ecx\ntest edx, edx\njz short loc_1238\nmov eax, edi\nsub ecx, 1\ncdq\nidiv ecx\ntest edx, edx\njz short loc_1219\nloc_122E:\nsub ecx, 1\njnz short loc_1210\nloc_1233:\nmov ecx, 1\nloc_1238:\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1200(int a1, int a2)\n{\n int v2; // ecx\n\n v2 = a2 / 2;\n if ( a2 <= 1 )\n {\n return 1;\n }\n else\n {\n while ( a1 % v2 )\n {\nLABEL_5:\n if ( !--v2 )\n return 1;\n }\n while ( a2 % v2 )\n {\n --v2;\n if ( a1 % v2 )\n goto LABEL_5;\n }\n }\n return (unsigned int)v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1200(int a1, int a2) {\n int v2;\n v2 = a2 / 2;\n if (a2 <= 1) {\n return 1;\n } else {\n while (a1 % v2) {\n LABEL_5:\n if (!--v2) return 1;\n }\n while (a2 % v2) {\n --v2;\n if (a1 % v2) goto LABEL_5;\n }\n }\n return (unsigned int)v2;\n}", + "ida_pseudo_norm": "long long func0_part_0(int a1, int a2) {\n int v2;\n v2 = a2 / 2;\n if (a2 <= 1) {\n return 1;\n } else {\n while (a1 % v2) {\n LABEL_5:\n if (!--v2) return 1;\n }\n while (a2 % v2) {\n --v2;\n if (a1 % v2) goto LABEL_5;\n }\n }\n return (unsigned int)v2;\n}" + }, + { + "index": 498, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int x, int y) {\n int gcd = 1;\n if (x % y == 0) {\n return y;\n }\n for (int k = y / 2; k > 0; k--) {\n if (x % k == 0 && y % k == 0) {\n gcd = k;\n break;\n }\n }\n return gcd;\n}", + "test": "int main() {\n\n assert(func0(12, 17) == 1);\n\n assert(func0(4, 6) == 2);\n\n assert(func0(2, 9) == 1);\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nmov %edi,%eax\nmov %esi,%r8d\ncltd\nidiv %esi\ntest %edx,%edx\nje 1280 \nmov %esi,%eax\nshr $0x1f,%eax\nadd %eax,%r8d\nsar %r8d\ncmp $0x1,%esi\njle 127a \nmov %edi,%eax\ncltd\nidiv %r8d\ntest %edx,%edx\njne 1274 \nmov %esi,%eax\ncltd\nidiv %r8d\ntest %edx,%edx\nje 1280 \nsub $0x1,%r8d\njne 1260 \nmov $0x1,%r8d\nmov %r8d,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0_part_0:\nmov ecx, esi\nshr ecx, 1Fh\nadd ecx, esi\nsar ecx, 1\ncmp esi, 1\njle short loc_1233\nxchg ax, ax\nloc_1210:\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_122E\nloc_1219:\nmov eax, esi\ncdq\nidiv ecx\ntest edx, edx\njz short loc_1238\nmov eax, edi\nsub ecx, 1\ncdq\nidiv ecx\ntest edx, edx\njz short loc_1219\nloc_122E:\nsub ecx, 1\njnz short loc_1210\nloc_1233:\nmov ecx, 1\nloc_1238:\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0_part_0(int a1, int a2)\n{\n int v2; // ecx\n\n v2 = a2 / 2;\n if ( a2 <= 1 )\n {\n return 1;\n }\n else\n {\n while ( a1 % v2 )\n {\nLABEL_5:\n if ( !--v2 )\n return 1;\n }\n while ( a2 % v2 )\n {\n --v2;\n if ( a1 % v2 )\n goto LABEL_5;\n }\n }\n return (unsigned int)v2;\n}", + "ida_strip_asm": "sub_1200:\nmov ecx, esi\nshr ecx, 1Fh\nadd ecx, esi\nsar ecx, 1\ncmp esi, 1\njle short loc_1233\nxchg ax, ax\nloc_1210:\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_122E\nloc_1219:\nmov eax, esi\ncdq\nidiv ecx\ntest edx, edx\njz short loc_1238\nmov eax, edi\nsub ecx, 1\ncdq\nidiv ecx\ntest edx, edx\njz short loc_1219\nloc_122E:\nsub ecx, 1\njnz short loc_1210\nloc_1233:\nmov ecx, 1\nloc_1238:\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1200(int a1, int a2)\n{\n int v2; // ecx\n\n v2 = a2 / 2;\n if ( a2 <= 1 )\n {\n return 1;\n }\n else\n {\n while ( a1 % v2 )\n {\nLABEL_5:\n if ( !--v2 )\n return 1;\n }\n while ( a2 % v2 )\n {\n --v2;\n if ( a1 % v2 )\n goto LABEL_5;\n }\n }\n return (unsigned int)v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1200(int a1, int a2) {\n int v2;\n v2 = a2 / 2;\n if (a2 <= 1) {\n return 1;\n } else {\n while (a1 % v2) {\n LABEL_5:\n if (!--v2) return 1;\n }\n while (a2 % v2) {\n --v2;\n if (a1 % v2) goto LABEL_5;\n }\n }\n return (unsigned int)v2;\n}", + "ida_pseudo_norm": "long long func0_part_0(int a1, int a2) {\n int v2;\n v2 = a2 / 2;\n if (a2 <= 1) {\n return 1;\n } else {\n while (a1 % v2) {\n LABEL_5:\n if (!--v2) return 1;\n }\n while (a2 % v2) {\n --v2;\n if (a1 % v2) goto LABEL_5;\n }\n }\n return (unsigned int)v2;\n}" + }, + { + "index": 499, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int r) {\n int diameter = 2 * r;\n return diameter;\n}", + "test": "int main() {\n\n assert(func0(10) == 20);\n\n assert(func0(40) == 80);\n\n assert(func0(15) == 30);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov -0x14(%rbp),%eax\nadd %eax,%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov eax, [rbp+var_14]\nadd eax, eax\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n return (unsigned int)(2 * a1);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov eax, [rbp+var_14]\nadd eax, eax\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n return (unsigned int)(2 * a1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) { return (unsigned int)(2 * a1); }", + "ida_pseudo_norm": "long long func0(int a1) { return (unsigned int)(2 * a1); }" + }, + { + "index": 500, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* arr[], int size) {\n static char ans[1000] = \"\";\n strcpy(ans, \" \");\n for (int i = 0; i < size; i++) {\n strcat(ans, \" \");\n strcat(ans, arr[i]);\n }\n return ans;\n}", + "test": "int main() {\n\n char* list1[] = {\"hello\", \"there\", \"have\", \"a\", \"rocky\", \"day\"};\n\n char* list2[] = {\"Hi\", \"there\", \"How\", \"are\", \"you\"};\n\n char* list3[] = {\"Part\", \"of\", \"the\", \"journey\", \"is\", \"end\"};\n\n\n\n assert(strcmp(func0(list1, 6), \" hello there have a rocky day\") == 0);\n\n assert(strcmp(func0(list2, 5), \" Hi there How are you\") == 0);\n\n assert(strcmp(func0(list3, 6), \" Part of the journey is end\") == 0);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovw $0x20,0x2e7b(%rip)\nmovl $0x0,-0x4(%rbp)\njmp 122c \nlea 0x2e6b(%rip),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nlea 0x2e46(%rip),%rax\nadd %rdx,%rax\nmovw $0x20,(%rax)\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov %rax,%rsi\nlea 0x2e1d(%rip),%rdi\ncallq 10b0 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11ce \nlea 0x2e05(%rip),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov cs:ans_1, 20h ; ' '\nmov [rbp+var_4], 0\njmp short loc_123C\nloc_11EE:\nlea rax, ans_1\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nlea rax, ans_1\nadd rax, rdx\nmov word ptr [rax], 20h ; ' '\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov rsi, rax; src\nlea rax, ans_1\nmov rdi, rax; dest\ncall _strcat\nadd [rbp+var_4], 1\nloc_123C:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11EE\nlea rax, ans_1\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+1Ch] [rbp-4h]\n\n strcpy(ans_1, \" \");\n for ( i = 0; i < a2; ++i )\n {\n *(_WORD *)&ans_1[strlen(ans_1)] = 32;\n strcat(ans_1, *(const char **)(8LL * i + a1));\n }\n return ans_1;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov cs:dest, 20h ; ' '\nmov [rbp+var_4], 0\njmp short loc_123C\nloc_11EE:\nlea rax, dest\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nlea rax, dest\nadd rax, rdx\nmov word ptr [rax], 20h ; ' '\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov rsi, rax; src\nlea rax, dest\nmov rdi, rax; dest\ncall _strcat\nadd [rbp+var_4], 1\nloc_123C:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11EE\nlea rax, dest\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11C9(__int64 a1, int a2)\n{\n int i; // [rsp+1Ch] [rbp-4h]\n\n strcpy(dest, \" \");\n for ( i = 0; i < a2; ++i )\n {\n *(_WORD *)&dest[strlen(dest)] = 32;\n strcat(dest, *(const char **)(8LL * i + a1));\n }\n return dest;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11C9(long long a1, int a2) {\n int i;\n strcpy(dest, \" \");\n for (i = 0; i < a2; ++i) {\n *(unsigned short *)&dest[strlen(dest)] = 32;\n strcat(dest, *(const char **)(8LL * i + a1));\n }\n return dest;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2) {\n int i;\n strcpy(ans_1, \" \");\n for (i = 0; i < a2; ++i) {\n *(unsigned short *)&ans_1[strlen(ans_1)] = 32;\n strcat(ans_1, *(const char **)(8LL * i + a1));\n }\n return ans_1;\n}" + }, + { + "index": 500, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* arr[], int size) {\n static char ans[1000] = \"\";\n strcpy(ans, \" \");\n for (int i = 0; i < size; i++) {\n strcat(ans, \" \");\n strcat(ans, arr[i]);\n }\n return ans;\n}", + "test": "int main() {\n\n char* list1[] = {\"hello\", \"there\", \"have\", \"a\", \"rocky\", \"day\"};\n\n char* list2[] = {\"Hi\", \"there\", \"How\", \"are\", \"you\"};\n\n char* list3[] = {\"Part\", \"of\", \"the\", \"journey\", \"is\", \"end\"};\n\n\n\n assert(strcmp(func0(list1, 6), \" hello there have a rocky day\") == 0);\n\n assert(strcmp(func0(list2, 5), \" Hi there How are you\") == 0);\n\n assert(strcmp(func0(list3, 6), \" Part of the journey is end\") == 0);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmovw $0x20,0x2eaa(%rip)\ntest %esi,%esi\njle 11e9 \npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nlea -0x1(%rsi),%eax\nlea 0x8(%rdi,%rax,8),%r12\nlea 0x2e90(%rip),%rbp\nmov $0x3e8,%edx\nlea 0xe48(%rip),%rsi\nmov %rbp,%rdi\ncallq 1070 <__strcat_chk@plt>\nmov $0x3e8,%edx\nmov (%rbx),%rsi\nmov %rbp,%rdi\ncallq 1070 <__strcat_chk@plt>\nadd $0x8,%rbx\ncmp %r12,%rbx\njne 11b0 \nlea 0x2e5c(%rip),%rax\npop %rbx\npop %rbp\npop %r12\nretq\nlea 0x2e50(%rip),%rax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov cs:ans_1, 20h ; ' '\ntest esi, esi\njle short loc_1217\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmovsxd rsi, esi\nlea r13, [rdi+rsi*8]\nlea r12, unk_2004\nlea rbp, ans_1\nloc_11DC:\nmov edx, 3E8h\nmov rsi, r12\nmov rdi, rbp\ncall ___strcat_chk\nmov rsi, [rbx]\nmov edx, 3E8h\nmov rdi, rbp\ncall ___strcat_chk\nadd rbx, 8\ncmp rbx, r13\njnz short loc_11DC\nlea rax, ans_1\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1217:\nlea rax, ans_1\nretn", + "ida_pseudo": "__int16 *__fastcall func0(_QWORD *a1, int a2)\n{\n _QWORD *v2; // rbx\n\n ans_1 = 32;\n if ( a2 <= 0 )\n return &ans_1;\n v2 = a1;\n do\n {\n __strcat_chk(&ans_1, &unk_2004, 1000LL);\n __strcat_chk(&ans_1, *v2++, 1000LL);\n }\n while ( v2 != &a1[a2] );\n return &ans_1;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\nmov cs:word_4040, 20h ; ' '\ntest esi, esi\njle short loc_1217\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmovsxd rsi, esi\nlea r13, [rdi+rsi*8]\nlea r12, unk_2004\nlea rbp, word_4040\nloc_11DC:\nmov edx, 3E8h\nmov rsi, r12\nmov rdi, rbp\ncall ___strcat_chk\nmov rsi, [rbx]\nmov edx, 3E8h\nmov rdi, rbp\ncall ___strcat_chk\nadd rbx, 8\ncmp rbx, r13\njnz short loc_11DC\nlea rax, word_4040\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1217:\nlea rax, word_4040\nretn", + "ida_strip_pseudo": "__int16 *__fastcall sub_11A9(_QWORD *a1, int a2)\n{\n _QWORD *v2; // rbx\n\n word_4040 = 32;\n if ( a2 <= 0 )\n return &word_4040;\n v2 = a1;\n do\n {\n __strcat_chk(&word_4040, &unk_2004, 1000LL);\n __strcat_chk(&word_4040, *v2++, 1000LL);\n }\n while ( v2 != &a1[a2] );\n return &word_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "short *sub_11A9(uint64_t *a1, int a2) {\n uint64_t *v2;\n word_4040 = 32;\n if (a2 <= 0) return &word_4040;\n v2 = a1;\n do {\n __strcat_chk(&word_4040, &unk_2004, 1000LL);\n __strcat_chk(&word_4040, *v2++, 1000LL);\n } while (v2 != &a1[a2]);\n return &word_4040;\n}", + "ida_pseudo_norm": "short *func0(uint64_t *a1, int a2) {\n uint64_t *v2;\n ans_1 = 32;\n if (a2 <= 0) return &ans_1;\n v2 = a1;\n do {\n __strcat_chk(&ans_1, &unk_2004, 1000LL);\n __strcat_chk(&ans_1, *v2++, 1000LL);\n } while (v2 != &a1[a2]);\n return &ans_1;\n}" + }, + { + "index": 500, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* arr[], int size) {\n static char ans[1000] = \"\";\n strcpy(ans, \" \");\n for (int i = 0; i < size; i++) {\n strcat(ans, \" \");\n strcat(ans, arr[i]);\n }\n return ans;\n}", + "test": "int main() {\n\n char* list1[] = {\"hello\", \"there\", \"have\", \"a\", \"rocky\", \"day\"};\n\n char* list2[] = {\"Hi\", \"there\", \"How\", \"are\", \"you\"};\n\n char* list3[] = {\"Part\", \"of\", \"the\", \"journey\", \"is\", \"end\"};\n\n\n\n assert(strcmp(func0(list1, 6), \" hello there have a rocky day\") == 0);\n\n assert(strcmp(func0(list2, 5), \" Hi there How are you\") == 0);\n\n assert(strcmp(func0(list3, 6), \" Part of the journey is end\") == 0);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x20,%edx\nmov %dx,0x2cb0(%rip)\ntest %esi,%esi\njle 1420 \nlea -0x1(%rsi),%eax\npush %r12\nmov %rdi,%r12\npush %rbp\nlea 0x8(%rdi,%rax,8),%rbp\npush %rbx\nlea 0x307a(%rip),%rbx\nxchg %ax,%ax\nlea 0x2c89(%rip),%rdi\nmov (%rdi),%edx\nadd $0x4,%rdi\nlea -0x1010101(%rdx),%eax\nnot %edx\nand %edx,%eax\nand $0x80808080,%eax\nje 13b7 \nmov %eax,%edx\nshr $0x10,%edx\ntest $0x8080,%eax\ncmove %edx,%eax\nlea 0x2(%rdi),%rdx\ncmove %rdx,%rdi\nmov %rbx,%rdx\nmov %eax,%ecx\nadd %al,%cl\nmov $0x20,%eax\nsbb $0x3,%rdi\nadd $0x8,%r12\nmov %ax,(%rdi)\nadd $0x1,%rdi\nmov -0x8(%r12),%rsi\nsub %rdi,%rdx\ncallq 1090 <__strcpy_chk@plt>\ncmp %rbp,%r12\njne 13b0 \npop %rbx\nlea 0x2c28(%rip),%rax\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax)\nlea 0x2c19(%rip),%rax\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r13\nmov edx, 20h ; ' '\npush r12\npush rbp\npush rbx\nlea rbx, ans_1\nsub rsp, 8\nmov cs:ans_1, dx\ntest esi, esi\njle short loc_1450\nmovsxd rsi, esi\nmov r13, rdi\nlea rbp, [rbx+3E8h]\nlea r12, [rdi+rsi*8]\nnop word ptr [rax+rax+00000000h]\nloc_1420:\nmov rdi, rbx; s\nadd r13, 8\ncall _strlen\nmov rdx, rbp\nlea rdi, [rbx+rax]\nmov eax, 20h ; ' '\nmov [rdi], ax\nadd rdi, 1\nmov rsi, [r13-8]\nsub rdx, rdi\ncall ___strcpy_chk\ncmp r13, r12\njnz short loc_1420\nloc_1450:\nadd rsp, 8\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // r13\n size_t v3; // rax\n\n strcpy(ans_1, \" \");\n if ( a2 > 0 )\n {\n v2 = a1;\n do\n {\n v2 += 8LL;\n v3 = strlen(ans_1);\n *(_WORD *)&ans_1[v3] = 32;\n __strcpy_chk(&ans_1[v3 + 1], *(_QWORD *)(v2 - 8), 1000 - (v3 + 1));\n }\n while ( v2 != a1 + 8LL * a2 );\n }\n return ans_1;\n}", + "ida_strip_asm": "sub_13E0:\nendbr64\npush r13\nmov edx, 20h ; ' '\npush r12\npush rbp\npush rbx\nlea rbx, s\nsub rsp, 8\nmov cs:s, dx\ntest esi, esi\njle short loc_1450\nmovsxd rsi, esi\nmov r13, rdi\nlea rbp, [rbx+3E8h]\nlea r12, [rdi+rsi*8]\nnop word ptr [rax+rax+00000000h]\nloc_1420:\nmov rdi, rbx; s\nadd r13, 8\ncall _strlen\nmov rdx, rbp\nlea rdi, [rbx+rax]\nmov eax, 20h ; ' '\nmov [rdi], ax\nadd rdi, 1\nmov rsi, [r13-8]\nsub rdx, rdi\ncall ___strcpy_chk\ncmp r13, r12\njnz short loc_1420\nloc_1450:\nadd rsp, 8\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "char *__fastcall sub_13E0(__int64 a1, int a2)\n{\n __int64 v2; // r13\n size_t v3; // rax\n\n strcpy(s, \" \");\n if ( a2 > 0 )\n {\n v2 = a1;\n do\n {\n v2 += 8LL;\n v3 = strlen(s);\n *(_WORD *)&s[v3] = 32;\n __strcpy_chk(&s[v3 + 1], *(_QWORD *)(v2 - 8), 1000 - (v3 + 1));\n }\n while ( v2 != a1 + 8LL * a2 );\n }\n return s;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_13E0(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n strcpy(s, \" \");\n if (a2 > 0) {\n v2 = a1;\n do {\n v2 += 8LL;\n v3 = strlen(s);\n *(unsigned short *)&s[v3] = 32;\n __strcpy_chk(&s[v3 + 1], *(uint64_t *)(v2 - 8), 1000 - (v3 + 1));\n } while (v2 != a1 + 8LL * a2);\n }\n return s;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n strcpy(ans_1, \" \");\n if (a2 > 0) {\n v2 = a1;\n do {\n v2 += 8LL;\n v3 = strlen(ans_1);\n *(unsigned short *)&ans_1[v3] = 32;\n __strcpy_chk(&ans_1[v3 + 1], *(uint64_t *)(v2 - 8), 1000 - (v3 + 1));\n } while (v2 != a1 + 8LL * a2);\n }\n return ans_1;\n}" + }, + { + "index": 500, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* arr[], int size) {\n static char ans[1000] = \"\";\n strcpy(ans, \" \");\n for (int i = 0; i < size; i++) {\n strcat(ans, \" \");\n strcat(ans, arr[i]);\n }\n return ans;\n}", + "test": "int main() {\n\n char* list1[] = {\"hello\", \"there\", \"have\", \"a\", \"rocky\", \"day\"};\n\n char* list2[] = {\"Hi\", \"there\", \"How\", \"are\", \"you\"};\n\n char* list3[] = {\"Part\", \"of\", \"the\", \"journey\", \"is\", \"end\"};\n\n\n\n assert(strcmp(func0(list1, 6), \" hello there have a rocky day\") == 0);\n\n assert(strcmp(func0(list2, 5), \" Hi there How are you\") == 0);\n\n assert(strcmp(func0(list3, 6), \" Part of the journey is end\") == 0);\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x20,%edx\nmov %dx,0x2c80(%rip)\ntest %esi,%esi\njle 1450 \nlea -0x1(%rsi),%eax\npush %r12\nmov %rdi,%r12\npush %rbp\nlea 0x8(%rdi,%rax,8),%rbp\npush %rbx\nlea 0x304a(%rip),%rbx\nxchg %ax,%ax\nlea 0x2c59(%rip),%rdi\nmov (%rdi),%edx\nadd $0x4,%rdi\nlea -0x1010101(%rdx),%eax\nnot %edx\nand %edx,%eax\nand $0x80808080,%eax\nje 13e7 \nmov %eax,%edx\nshr $0x10,%edx\ntest $0x8080,%eax\ncmove %edx,%eax\nlea 0x2(%rdi),%rdx\ncmove %rdx,%rdi\nmov %rbx,%rdx\nmov %eax,%ecx\nadd %al,%cl\nmov $0x20,%eax\nsbb $0x3,%rdi\nadd $0x8,%r12\nmov %ax,(%rdi)\nadd $0x1,%rdi\nmov -0x8(%r12),%rsi\nsub %rdi,%rdx\ncallq 1090 <__strcpy_chk@plt>\ncmp %rbp,%r12\njne 13e0 \npop %rbx\nlea 0x2bf8(%rip),%rax\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax)\nlea 0x2be9(%rip),%rax\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r13\nmov edx, 20h ; ' '\npush r12\npush rbp\npush rbx\nlea rbx, ans_1\nsub rsp, 8\nmov cs:ans_1, dx\ntest esi, esi\njle short loc_1450\nmovsxd rsi, esi\nmov r13, rdi\nlea rbp, [rbx+3E8h]\nlea r12, [rdi+rsi*8]\nnop word ptr [rax+rax+00000000h]\nloc_1420:\nmov rdi, rbx; s\nadd r13, 8\ncall _strlen\nmov rdx, rbp\nlea rdi, [rbx+rax]\nmov eax, 20h ; ' '\nmov [rdi], ax\nadd rdi, 1\nmov rsi, [r13-8]\nsub rdx, rdi\ncall ___strcpy_chk\ncmp r13, r12\njnz short loc_1420\nloc_1450:\nadd rsp, 8\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // r13\n size_t v3; // rax\n\n strcpy(ans_1, \" \");\n if ( a2 > 0 )\n {\n v2 = a1;\n do\n {\n v2 += 8LL;\n v3 = strlen(ans_1);\n *(_WORD *)&ans_1[v3] = 32;\n __strcpy_chk(&ans_1[v3 + 1], *(_QWORD *)(v2 - 8), 1000 - (v3 + 1));\n }\n while ( v2 != a1 + 8LL * a2 );\n }\n return ans_1;\n}", + "ida_strip_asm": "sub_13E0:\nendbr64\npush r13\nmov edx, 20h ; ' '\npush r12\npush rbp\npush rbx\nlea rbx, s\nsub rsp, 8\nmov cs:s, dx\ntest esi, esi\njle short loc_1450\nmovsxd rsi, esi\nmov r13, rdi\nlea rbp, [rbx+3E8h]\nlea r12, [rdi+rsi*8]\nnop word ptr [rax+rax+00000000h]\nloc_1420:\nmov rdi, rbx; s\nadd r13, 8\ncall _strlen\nmov rdx, rbp\nlea rdi, [rbx+rax]\nmov eax, 20h ; ' '\nmov [rdi], ax\nadd rdi, 1\nmov rsi, [r13-8]\nsub rdx, rdi\ncall ___strcpy_chk\ncmp r13, r12\njnz short loc_1420\nloc_1450:\nadd rsp, 8\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "char *__fastcall sub_13E0(__int64 a1, int a2)\n{\n __int64 v2; // r13\n size_t v3; // rax\n\n strcpy(s, \" \");\n if ( a2 > 0 )\n {\n v2 = a1;\n do\n {\n v2 += 8LL;\n v3 = strlen(s);\n *(_WORD *)&s[v3] = 32;\n __strcpy_chk(&s[v3 + 1], *(_QWORD *)(v2 - 8), 1000 - (v3 + 1));\n }\n while ( v2 != a1 + 8LL * a2 );\n }\n return s;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_13E0(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n strcpy(s, \" \");\n if (a2 > 0) {\n v2 = a1;\n do {\n v2 += 8LL;\n v3 = strlen(s);\n *(unsigned short *)&s[v3] = 32;\n __strcpy_chk(&s[v3 + 1], *(uint64_t *)(v2 - 8), 1000 - (v3 + 1));\n } while (v2 != a1 + 8LL * a2);\n }\n return s;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n strcpy(ans_1, \" \");\n if (a2 > 0) {\n v2 = a1;\n do {\n v2 += 8LL;\n v3 = strlen(ans_1);\n *(unsigned short *)&ans_1[v3] = 32;\n __strcpy_chk(&ans_1[v3 + 1], *(uint64_t *)(v2 - 8), 1000 - (v3 + 1));\n } while (v2 != a1 + 8LL * a2);\n }\n return ans_1;\n}" + }, + { + "index": 501, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\nint ngcd(int x, int y) {\n\n int gcd = 1;\n\n int i = 1;\n\n while (i <= x && i <= y) {\n\n if (x % i == 0 && y % i == 0) {\n\n gcd = i;\n\n }\n\n i++;\n\n }\n\n return gcd;\n\n}\n\n\n\n", + "func": "int func0(int x, int y) {\n int n = ngcd(x, y);\n int result = 0;\n int z = (int)sqrt(n);\n int i = 1;\n while (i <= z) {\n if (n % i == 0) {\n result += 2;\n if (i == n / i) {\n result -= 1;\n }\n }\n i++;\n }\n return result;\n}", + "test": "int main() {\n\n assert(func0(2, 4) == 2);\n\n assert(func0(2, 8) == 2);\n\n assert(func0(12, 24) == 6);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov -0x18(%rbp),%edx\nmov -0x14(%rbp),%eax\nmov %edx,%esi\nmov %eax,%edi\ncallq 1169 \nmov %eax,-0x8(%rbp)\nmovl $0x0,-0x10(%rbp)\ncvtsi2sdl -0x8(%rbp),%xmm0\ncallq 1070 \ncvttsd2si %xmm0,%eax\nmov %eax,-0x4(%rbp)\nmovl $0x1,-0xc(%rbp)\njmp 122a \nmov -0x8(%rbp),%eax\ncltd\nidivl -0xc(%rbp)\nmov %edx,%eax\ntest %eax,%eax\njne 1226 \naddl $0x2,-0x10(%rbp)\nmov -0x8(%rbp),%eax\ncltd\nidivl -0xc(%rbp)\ncmp %eax,-0xc(%rbp)\njne 1226 \nsubl $0x1,-0x10(%rbp)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x4(%rbp),%eax\njle 1205 \nmov -0x10(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov edx, [rbp+var_18]\nmov eax, [rbp+var_14]\nmov esi, edx\nmov edi, eax\ncall ngcd\nmov [rbp+var_8], eax\nmov [rbp+var_10], 0\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_8]\nmovq rax, xmm1\nmovq xmm0, rax; x\ncall _sqrt\ncvttsd2si eax, xmm0\nmov [rbp+var_4], eax\nmov [rbp+var_C], 1\njmp short loc_1238\nloc_1213:\nmov eax, [rbp+var_8]\ncdq\nidiv [rbp+var_C]\nmov eax, edx\ntest eax, eax\njnz short loc_1234\nadd [rbp+var_10], 2\nmov eax, [rbp+var_8]\ncdq\nidiv [rbp+var_C]\ncmp [rbp+var_C], eax\njnz short loc_1234\nsub [rbp+var_10], 1\nloc_1234:\nadd [rbp+var_C], 1\nloc_1238:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_4]\njle short loc_1213\nmov eax, [rbp+var_10]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1, unsigned int a2)\n{\n unsigned int v3; // [rsp+10h] [rbp-10h]\n int i; // [rsp+14h] [rbp-Ch]\n int v5; // [rsp+18h] [rbp-8h]\n int v6; // [rsp+1Ch] [rbp-4h]\n\n v5 = ngcd(a1, a2);\n v3 = 0;\n v6 = (int)sqrt((double)v5);\n for ( i = 1; i <= v6; ++i )\n {\n if ( !(v5 % i) )\n {\n v3 += 2;\n if ( i == v5 / i )\n --v3;\n }\n }\n return v3;\n}", + "ida_strip_asm": "sub_11C0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov edx, [rbp+var_18]\nmov eax, [rbp+var_14]\nmov esi, edx\nmov edi, eax\ncall sub_1169\nmov [rbp+var_8], eax\nmov [rbp+var_10], 0\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_8]\nmovq rax, xmm1\nmovq xmm0, rax; x\ncall _sqrt\ncvttsd2si eax, xmm0\nmov [rbp+var_4], eax\nmov [rbp+var_C], 1\njmp short loc_1238\nloc_1213:\nmov eax, [rbp+var_8]\ncdq\nidiv [rbp+var_C]\nmov eax, edx\ntest eax, eax\njnz short loc_1234\nadd [rbp+var_10], 2\nmov eax, [rbp+var_8]\ncdq\nidiv [rbp+var_C]\ncmp [rbp+var_C], eax\njnz short loc_1234\nsub [rbp+var_10], 1\nloc_1234:\nadd [rbp+var_C], 1\nloc_1238:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_4]\njle short loc_1213\nmov eax, [rbp+var_10]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11C0(unsigned int a1, unsigned int a2)\n{\n unsigned int v3; // [rsp+10h] [rbp-10h]\n int i; // [rsp+14h] [rbp-Ch]\n int v5; // [rsp+18h] [rbp-8h]\n int v6; // [rsp+1Ch] [rbp-4h]\n\n v5 = sub_1169(a1, a2);\n v3 = 0;\n v6 = (int)sqrt((double)v5);\n for ( i = 1; i <= v6; ++i )\n {\n if ( !(v5 % i) )\n {\n v3 += 2;\n if ( i == v5 / i )\n --v3;\n }\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11C0(unsigned int a1, unsigned int a2) {\n unsigned int v3;\n int i;\n int v5;\n int v6;\n v5 = sub_1169(a1, a2);\n v3 = 0;\n v6 = (int)sqrt((double)v5);\n for (i = 1; i <= v6; ++i) {\n if (!(v5 % i)) {\n v3 += 2;\n if (i == v5 / i) --v3;\n }\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(unsigned int a1, unsigned int a2) {\n unsigned int v3;\n int i;\n int v5;\n int v6;\n v5 = ngcd(a1, a2);\n v3 = 0;\n v6 = (int)sqrt((double)v5);\n for (i = 1; i <= v6; ++i) {\n if (!(v5 % i)) {\n v3 += 2;\n if (i == v5 / i) --v3;\n }\n }\n return v3;\n}" + }, + { + "index": 501, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\nint ngcd(int x, int y) {\n\n int gcd = 1;\n\n int i = 1;\n\n while (i <= x && i <= y) {\n\n if (x % i == 0 && y % i == 0) {\n\n gcd = i;\n\n }\n\n i++;\n\n }\n\n return gcd;\n\n}\n\n\n\n", + "func": "int func0(int x, int y) {\n int n = ngcd(x, y);\n int result = 0;\n int z = (int)sqrt(n);\n int i = 1;\n while (i <= z) {\n if (n % i == 0) {\n result += 2;\n if (i == n / i) {\n result -= 1;\n }\n }\n i++;\n }\n return result;\n}", + "test": "int main() {\n\n assert(func0(2, 4) == 2);\n\n assert(func0(2, 8) == 2);\n\n assert(func0(12, 24) == 6);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nsub $0x10,%rsp\ncallq 1169 \nmov %eax,%ebx\npxor %xmm0,%xmm0\ncvtsi2sd %eax,%xmm0\nmovapd %xmm0,%xmm2\nsqrtsd %xmm2,%xmm2\nmovsd %xmm2,0x8(%rsp)\npxor %xmm1,%xmm1\nucomisd %xmm0,%xmm1\nja 11fd \ncvttsd2si 0x8(%rsp),%edi\ntest %edi,%edi\njle 122b \nadd $0x1,%edi\nmov $0x1,%ecx\nmov $0x0,%esi\njmp 120b \ncallq 1070 \njmp 11e4 \nadd $0x1,%ecx\ncmp %edi,%ecx\nje 1230 \nmov %ebx,%eax\ncltd\nidiv %ecx\ntest %edx,%edx\njne 1204 \nmov %ebx,%eax\ncltd\nidiv %ecx\nmov %esi,%edx\ncmp %ecx,%eax\nsetne %sil\nmovzbl %sil,%esi\nlea 0x1(%rsi,%rdx,1),%esi\njmp 1204 \nmov $0x0,%esi\nmov %esi,%eax\nadd $0x10,%rsp\npop %rbx\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbx\ncall ngcd\nmov ebx, eax\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax; x\npxor xmm1, xmm1\nucomisd xmm1, xmm0\nja short loc_11ED\nsqrtsd xmm0, xmm0\nloc_11D6:\ncvttsd2si edi, xmm0\ntest edi, edi\njle short loc_121B\nadd edi, 1\nmov ecx, 1\nmov esi, 0\njmp short loc_11FB\nloc_11ED:\ncall _sqrt\njmp short loc_11D6\nloc_11F4:\nadd ecx, 1\ncmp ecx, edi\njz short loc_1220\nloc_11FB:\nmov eax, ebx\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_11F4\nmov eax, ebx\ncdq\nidiv ecx\nmov edx, esi\ncmp eax, ecx\nsetnz sil\nmovzx esi, sil\nlea esi, [rsi+rdx+1]\njmp short loc_11F4\nloc_121B:\nmov esi, 0\nloc_1220:\nmov eax, esi\npop rbx\nretn", + "ida_pseudo": "__int64 func0()\n{\n int v0; // ebx\n double v1; // xmm0_8\n double v2; // xmm0_8\n int v3; // ecx\n unsigned int v4; // esi\n\n v0 = ngcd();\n v1 = (double)v0;\n if ( (double)v0 < 0.0 )\n v2 = sqrt(v1);\n else\n v2 = sqrt(v1);\n if ( (int)v2 <= 0 )\n {\n return 0;\n }\n else\n {\n v3 = 1;\n v4 = 0;\n do\n {\n if ( !(v0 % v3) )\n v4 += (v0 / v3 != v3) + 1;\n ++v3;\n }\n while ( v3 != (int)v2 + 1 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_11B4:\nendbr64\npush rbx\ncall sub_1169\nmov ebx, eax\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax; x\npxor xmm1, xmm1\nucomisd xmm1, xmm0\nja short loc_11ED\nsqrtsd xmm0, xmm0\nloc_11D6:\ncvttsd2si edi, xmm0\ntest edi, edi\njle short loc_121B\nadd edi, 1\nmov ecx, 1\nmov esi, 0\njmp short loc_11FB\nloc_11ED:\ncall _sqrt\njmp short loc_11D6\nloc_11F4:\nadd ecx, 1\ncmp ecx, edi\njz short loc_1220\nloc_11FB:\nmov eax, ebx\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_11F4\nmov eax, ebx\ncdq\nidiv ecx\nmov edx, esi\ncmp eax, ecx\nsetnz sil\nmovzx esi, sil\nlea esi, [rsi+rdx+1]\njmp short loc_11F4\nloc_121B:\nmov esi, 0\nloc_1220:\nmov eax, esi\npop rbx\nretn", + "ida_strip_pseudo": "__int64 sub_11B4()\n{\n int v0; // ebx\n double v1; // xmm0_8\n double v2; // xmm0_8\n int v3; // ecx\n unsigned int v4; // esi\n\n v0 = sub_1169();\n v1 = (double)v0;\n if ( (double)v0 < 0.0 )\n v2 = sqrt(v1);\n else\n v2 = sqrt(v1);\n if ( (int)v2 <= 0 )\n {\n return 0;\n }\n else\n {\n v3 = 1;\n v4 = 0;\n do\n {\n if ( !(v0 % v3) )\n v4 += (v0 / v3 != v3) + 1;\n ++v3;\n }\n while ( v3 != (int)v2 + 1 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11B4() {\n int v0;\n double v1;\n double v2;\n int v3;\n unsigned int v4;\n v0 = sub_1169();\n v1 = (double)v0;\n if ((double)v0 < 0.0)\n v2 = sqrt(v1);\n else\n v2 = sqrt(v1);\n if ((int)v2 <= 0) {\n return 0;\n } else {\n v3 = 1;\n v4 = 0;\n do {\n if (!(v0 % v3)) v4 += (v0 / v3 != v3) + 1;\n ++v3;\n } while (v3 != (int)v2 + 1);\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0() {\n int v0;\n double v1;\n double v2;\n int v3;\n unsigned int v4;\n v0 = ngcd();\n v1 = (double)v0;\n if ((double)v0 < 0.0)\n v2 = sqrt(v1);\n else\n v2 = sqrt(v1);\n if ((int)v2 <= 0) {\n return 0;\n } else {\n v3 = 1;\n v4 = 0;\n do {\n if (!(v0 % v3)) v4 += (v0 / v3 != v3) + 1;\n ++v3;\n } while (v3 != (int)v2 + 1);\n }\n return v4;\n}" + }, + { + "index": 501, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\nint ngcd(int x, int y) {\n\n int gcd = 1;\n\n int i = 1;\n\n while (i <= x && i <= y) {\n\n if (x % i == 0 && y % i == 0) {\n\n gcd = i;\n\n }\n\n i++;\n\n }\n\n return gcd;\n\n}\n\n\n\n", + "func": "int func0(int x, int y) {\n int n = ngcd(x, y);\n int result = 0;\n int z = (int)sqrt(n);\n int i = 1;\n while (i <= z) {\n if (n % i == 0) {\n result += 2;\n if (i == n / i) {\n result -= 1;\n }\n }\n i++;\n }\n return result;\n}", + "test": "int main() {\n\n assert(func0(2, 4) == 2);\n\n assert(func0(2, 8) == 2);\n\n assert(func0(12, 24) == 6);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %esi,%r8d\nsub $0x10,%rsp\ncmp %esi,%edi\ncmovle %edi,%r8d\ntest %r8d,%r8d\njle 1340 \nadd $0x1,%r8d\nmov $0x1,%ebx\nmov $0x1,%ecx\nnopl 0x0(%rax)\nmov %edi,%eax\ncltd\nidiv %ecx\ntest %edx,%edx\njne 12c3 \nmov %esi,%eax\ncltd\nidiv %ecx\ntest %edx,%edx\ncmove %ecx,%ebx\nadd $0x1,%ecx\ncmp %r8d,%ecx\njne 12b0 \npxor %xmm0,%xmm0\npxor %xmm2,%xmm2\ncvtsi2sd %ebx,%xmm0\nucomisd %xmm0,%xmm2\nmovapd %xmm0,%xmm1\nsqrtsd %xmm1,%xmm1\nja 134c \ncvttsd2si %xmm1,%esi\ntest %esi,%esi\njle 1330 \nadd $0x1,%esi\nmov $0x1,%ecx\nxor %r8d,%r8d\nnopl 0x0(%rax,%rax,1)\nmov %ebx,%eax\ncltd\nidiv %ecx\ntest %edx,%edx\njne 131a \nmov %r8d,%edx\nxor %r8d,%r8d\ncmp %ecx,%eax\nsetne %r8b\nlea 0x1(%r8,%rdx,1),%r8d\nadd $0x1,%ecx\ncmp %ecx,%esi\njne 1300 \nadd $0x10,%rsp\nmov %r8d,%eax\npop %rbx\nretq\nnopw 0x0(%rax,%rax,1)\nxor %r8d,%r8d\nadd $0x10,%rsp\nmov %r8d,%eax\npop %rbx\nretq\nnopl 0x0(%rax)\nmov $0x1,%ebx\nmov $0x1,%esi\njmp 12ed \nmovsd %xmm1,0x8(%rsp)\ncallq 1070 \nmovsd 0x8(%rsp),%xmm1\njmp 12e5 \n", + "ida_asm": "func0:\nendbr64\ncmp edi, esi\nmov r8d, esi\npush rbx\ncmovle r8d, edi\ntest r8d, r8d\njle loc_1320\nadd r8d, 1\nmov ebx, 1\nmov ecx, 1\nnop dword ptr [rax]\nloc_12A8:\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_12BB\nmov eax, esi\ncdq\nidiv ecx\ntest edx, edx\ncmovz ebx, ecx\nloc_12BB:\nadd ecx, 1\ncmp ecx, r8d\njnz short loc_12A8\npxor xmm0, xmm0\npxor xmm1, xmm1\ncvtsi2sd xmm0, ebx; x\nucomisd xmm1, xmm0\nja short loc_132C\nsqrtsd xmm0, xmm0\ncvttsd2si edi, xmm0\nloc_12DD:\ntest edi, edi\njle short loc_1318\nloc_12E1:\nadd edi, 1\nmov ecx, 1\nxor esi, esi\nnop dword ptr [rax+rax+00h]\nloc_12F0:\nmov eax, ebx\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_1307\nmov edx, esi\nxor esi, esi\ncmp eax, ecx\nsetnz sil\nlea esi, [rsi+rdx+1]\nloc_1307:\nadd ecx, 1\ncmp ecx, edi\njnz short loc_12F0\nmov eax, esi\npop rbx\nretn\nloc_1318:\nxor esi, esi\npop rbx\nmov eax, esi\nretn\nloc_1320:\nmov edi, 1\nmov ebx, 1\njmp short loc_12E1\nloc_132C:\ncall _sqrt\ncvttsd2si edi, xmm0\njmp short loc_12DD", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n int v2; // r8d\n int v3; // r8d\n int v4; // ebx\n int v5; // ecx\n double v6; // xmm0_8\n int v7; // edi\n int v8; // edi\n int v9; // ecx\n unsigned int v10; // esi\n\n v2 = a2;\n if ( a1 <= a2 )\n v2 = a1;\n if ( v2 <= 0 )\n {\n v7 = 1;\n v4 = 1;\n }\n else\n {\n v3 = v2 + 1;\n v4 = 1;\n v5 = 1;\n do\n {\n if ( !(a1 % v5) && !(a2 % v5) )\n v4 = v5;\n ++v5;\n }\n while ( v5 != v3 );\n v6 = (double)v4;\n if ( (double)v4 < 0.0 )\n v7 = (int)sqrt(v6);\n else\n v7 = (int)sqrt(v6);\n if ( v7 <= 0 )\n return 0LL;\n }\n v8 = v7 + 1;\n v9 = 1;\n v10 = 0;\n do\n {\n if ( !(v4 % v9) )\n v10 += (v4 / v9 != v9) + 1;\n ++v9;\n }\n while ( v9 != v8 );\n return v10;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\ncmp edi, esi\nmov r8d, esi\npush rbx\ncmovle r8d, edi\ntest r8d, r8d\njle loc_1320\nadd r8d, 1\nmov ebx, 1\nmov ecx, 1\nnop dword ptr [rax]\nloc_12A8:\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_12BB\nmov eax, esi\ncdq\nidiv ecx\ntest edx, edx\ncmovz ebx, ecx\nloc_12BB:\nadd ecx, 1\ncmp ecx, r8d\njnz short loc_12A8\npxor xmm0, xmm0\npxor xmm1, xmm1\ncvtsi2sd xmm0, ebx; x\nucomisd xmm1, xmm0\nja short loc_132C\nsqrtsd xmm0, xmm0\ncvttsd2si edi, xmm0\nloc_12DD:\ntest edi, edi\njle short loc_1318\nloc_12E1:\nadd edi, 1\nmov ecx, 1\nxor esi, esi\nnop dword ptr [rax+rax+00h]\nloc_12F0:\nmov eax, ebx\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_1307\nmov edx, esi\nxor esi, esi\ncmp eax, ecx\nsetnz sil\nlea esi, [rsi+rdx+1]\nloc_1307:\nadd ecx, 1\ncmp ecx, edi\njnz short loc_12F0\nmov eax, esi\npop rbx\nretn\nloc_1318:\nxor esi, esi\npop rbx\nmov eax, esi\nretn\nloc_1320:\nmov edi, 1\nmov ebx, 1\njmp short loc_12E1\nloc_132C:\ncall _sqrt\ncvttsd2si edi, xmm0\njmp short loc_12DD", + "ida_strip_pseudo": "__int64 __fastcall sub_1280(int a1, int a2)\n{\n int v2; // r8d\n int v3; // r8d\n int v4; // ebx\n int v5; // ecx\n double v6; // xmm0_8\n int v7; // edi\n int v8; // edi\n int v9; // ecx\n unsigned int v10; // esi\n\n v2 = a2;\n if ( a1 <= a2 )\n v2 = a1;\n if ( v2 <= 0 )\n {\n v7 = 1;\n v4 = 1;\n }\n else\n {\n v3 = v2 + 1;\n v4 = 1;\n v5 = 1;\n do\n {\n if ( !(a1 % v5) && !(a2 % v5) )\n v4 = v5;\n ++v5;\n }\n while ( v5 != v3 );\n v6 = (double)v4;\n if ( (double)v4 < 0.0 )\n v7 = (int)sqrt(v6);\n else\n v7 = (int)sqrt(v6);\n if ( v7 <= 0 )\n return 0LL;\n }\n v8 = v7 + 1;\n v9 = 1;\n v10 = 0;\n do\n {\n if ( !(v4 % v9) )\n v10 += (v4 / v9 != v9) + 1;\n ++v9;\n }\n while ( v9 != v8 );\n return v10;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1280(int a1, int a2) {\n int v2;\n int v3;\n int v4;\n int v5;\n double v6;\n int v7;\n int v8;\n int v9;\n unsigned int v10;\n v2 = a2;\n if (a1 <= a2) v2 = a1;\n if (v2 <= 0) {\n v7 = 1;\n v4 = 1;\n } else {\n v3 = v2 + 1;\n v4 = 1;\n v5 = 1;\n do {\n if (!(a1 % v5) && !(a2 % v5)) v4 = v5;\n ++v5;\n } while (v5 != v3);\n v6 = (double)v4;\n if ((double)v4 < 0.0)\n v7 = (int)sqrt(v6);\n else\n v7 = (int)sqrt(v6);\n if (v7 <= 0) return 0LL;\n }\n v8 = v7 + 1;\n v9 = 1;\n v10 = 0;\n do {\n if (!(v4 % v9)) v10 += (v4 / v9 != v9) + 1;\n ++v9;\n } while (v9 != v8);\n return v10;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n int v2;\n int v3;\n int v4;\n int v5;\n double v6;\n int v7;\n int v8;\n int v9;\n unsigned int v10;\n v2 = a2;\n if (a1 <= a2) v2 = a1;\n if (v2 <= 0) {\n v7 = 1;\n v4 = 1;\n } else {\n v3 = v2 + 1;\n v4 = 1;\n v5 = 1;\n do {\n if (!(a1 % v5) && !(a2 % v5)) v4 = v5;\n ++v5;\n } while (v5 != v3);\n v6 = (double)v4;\n if ((double)v4 < 0.0)\n v7 = (int)sqrt(v6);\n else\n v7 = (int)sqrt(v6);\n if (v7 <= 0) return 0LL;\n }\n v8 = v7 + 1;\n v9 = 1;\n v10 = 0;\n do {\n if (!(v4 % v9)) v10 += (v4 / v9 != v9) + 1;\n ++v9;\n } while (v9 != v8);\n return v10;\n}" + }, + { + "index": 501, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\nint ngcd(int x, int y) {\n\n int gcd = 1;\n\n int i = 1;\n\n while (i <= x && i <= y) {\n\n if (x % i == 0 && y % i == 0) {\n\n gcd = i;\n\n }\n\n i++;\n\n }\n\n return gcd;\n\n}\n\n\n\n", + "func": "int func0(int x, int y) {\n int n = ngcd(x, y);\n int result = 0;\n int z = (int)sqrt(n);\n int i = 1;\n while (i <= z) {\n if (n % i == 0) {\n result += 2;\n if (i == n / i) {\n result -= 1;\n }\n }\n i++;\n }\n return result;\n}", + "test": "int main() {\n\n assert(func0(2, 4) == 2);\n\n assert(func0(2, 8) == 2);\n\n assert(func0(12, 24) == 6);\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %esi,%r8d\nsub $0x10,%rsp\ncmp %esi,%edi\ncmovle %edi,%r8d\ntest %r8d,%r8d\njle 1340 \nadd $0x1,%r8d\nmov $0x1,%ebx\nmov $0x1,%ecx\nnopl 0x0(%rax)\nmov %edi,%eax\ncltd\nidiv %ecx\ntest %edx,%edx\njne 12c3 \nmov %esi,%eax\ncltd\nidiv %ecx\ntest %edx,%edx\ncmove %ecx,%ebx\nadd $0x1,%ecx\ncmp %r8d,%ecx\njne 12b0 \npxor %xmm0,%xmm0\npxor %xmm2,%xmm2\ncvtsi2sd %ebx,%xmm0\nucomisd %xmm0,%xmm2\nmovapd %xmm0,%xmm1\nsqrtsd %xmm1,%xmm1\nja 134c \ncvttsd2si %xmm1,%esi\ntest %esi,%esi\njle 1330 \nadd $0x1,%esi\nmov $0x1,%ecx\nxor %r8d,%r8d\nnopl 0x0(%rax,%rax,1)\nmov %ebx,%eax\ncltd\nidiv %ecx\ntest %edx,%edx\njne 131a \nmov %r8d,%edx\nxor %r8d,%r8d\ncmp %ecx,%eax\nsetne %r8b\nlea 0x1(%r8,%rdx,1),%r8d\nadd $0x1,%ecx\ncmp %esi,%ecx\njne 1300 \nadd $0x10,%rsp\nmov %r8d,%eax\npop %rbx\nretq\nnopw 0x0(%rax,%rax,1)\nxor %r8d,%r8d\nadd $0x10,%rsp\nmov %r8d,%eax\npop %rbx\nretq\nnopl 0x0(%rax)\nmov $0x1,%ebx\nmov $0x1,%esi\njmp 12ed \nmovsd %xmm1,0x8(%rsp)\ncallq 1070 \nmovsd 0x8(%rsp),%xmm1\njmp 12e5 \n", + "ida_asm": "func0:\nendbr64\ncmp edi, esi\nmov r8d, esi\npush rbx\ncmovle r8d, edi\ntest r8d, r8d\njle loc_1320\nadd r8d, 1\nmov ebx, 1\nmov ecx, 1\nnop dword ptr [rax]\nloc_12A8:\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_12BB\nmov eax, esi\ncdq\nidiv ecx\ntest edx, edx\ncmovz ebx, ecx\nloc_12BB:\nadd ecx, 1\ncmp r8d, ecx\njnz short loc_12A8\npxor xmm0, xmm0\npxor xmm1, xmm1\ncvtsi2sd xmm0, ebx; x\nucomisd xmm1, xmm0\nja short loc_132C\nsqrtsd xmm0, xmm0\ncvttsd2si edi, xmm0\nloc_12DD:\ntest edi, edi\njle short loc_1318\nloc_12E1:\nadd edi, 1\nmov ecx, 1\nxor esi, esi\nnop dword ptr [rax+rax+00h]\nloc_12F0:\nmov eax, ebx\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_1307\nmov edx, esi\nxor esi, esi\ncmp eax, ecx\nsetnz sil\nlea esi, [rsi+rdx+1]\nloc_1307:\nadd ecx, 1\ncmp edi, ecx\njnz short loc_12F0\nmov eax, esi\npop rbx\nretn\nloc_1318:\nxor esi, esi\npop rbx\nmov eax, esi\nretn\nloc_1320:\nmov edi, 1\nmov ebx, 1\njmp short loc_12E1\nloc_132C:\ncall _sqrt\ncvttsd2si edi, xmm0\njmp short loc_12DD", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n int v2; // r8d\n int v3; // r8d\n int v4; // ebx\n int v5; // ecx\n double v6; // xmm0_8\n int v7; // edi\n int v8; // edi\n int v9; // ecx\n unsigned int v10; // esi\n\n v2 = a2;\n if ( a1 <= a2 )\n v2 = a1;\n if ( v2 <= 0 )\n {\n v7 = 1;\n v4 = 1;\n }\n else\n {\n v3 = v2 + 1;\n v4 = 1;\n v5 = 1;\n do\n {\n if ( !(a1 % v5) && !(a2 % v5) )\n v4 = v5;\n ++v5;\n }\n while ( v3 != v5 );\n v6 = (double)v4;\n if ( (double)v4 < 0.0 )\n v7 = (int)sqrt(v6);\n else\n v7 = (int)sqrt(v6);\n if ( v7 <= 0 )\n return 0LL;\n }\n v8 = v7 + 1;\n v9 = 1;\n v10 = 0;\n do\n {\n if ( !(v4 % v9) )\n v10 += (v4 / v9 != v9) + 1;\n ++v9;\n }\n while ( v8 != v9 );\n return v10;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\ncmp edi, esi\nmov r8d, esi\npush rbx\ncmovle r8d, edi\ntest r8d, r8d\njle loc_1320\nadd r8d, 1\nmov ebx, 1\nmov ecx, 1\nnop dword ptr [rax]\nloc_12A8:\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_12BB\nmov eax, esi\ncdq\nidiv ecx\ntest edx, edx\ncmovz ebx, ecx\nloc_12BB:\nadd ecx, 1\ncmp r8d, ecx\njnz short loc_12A8\npxor xmm0, xmm0\npxor xmm1, xmm1\ncvtsi2sd xmm0, ebx; x\nucomisd xmm1, xmm0\nja short loc_132C\nsqrtsd xmm0, xmm0\ncvttsd2si edi, xmm0\nloc_12DD:\ntest edi, edi\njle short loc_1318\nloc_12E1:\nadd edi, 1\nmov ecx, 1\nxor esi, esi\nnop dword ptr [rax+rax+00h]\nloc_12F0:\nmov eax, ebx\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_1307\nmov edx, esi\nxor esi, esi\ncmp eax, ecx\nsetnz sil\nlea esi, [rsi+rdx+1]\nloc_1307:\nadd ecx, 1\ncmp edi, ecx\njnz short loc_12F0\nmov eax, esi\npop rbx\nretn\nloc_1318:\nxor esi, esi\npop rbx\nmov eax, esi\nretn\nloc_1320:\nmov edi, 1\nmov ebx, 1\njmp short loc_12E1\nloc_132C:\ncall _sqrt\ncvttsd2si edi, xmm0\njmp short loc_12DD", + "ida_strip_pseudo": "__int64 __fastcall sub_1280(int a1, int a2)\n{\n int v2; // r8d\n int v3; // r8d\n int v4; // ebx\n int v5; // ecx\n double v6; // xmm0_8\n int v7; // edi\n int v8; // edi\n int v9; // ecx\n unsigned int v10; // esi\n\n v2 = a2;\n if ( a1 <= a2 )\n v2 = a1;\n if ( v2 <= 0 )\n {\n v7 = 1;\n v4 = 1;\n }\n else\n {\n v3 = v2 + 1;\n v4 = 1;\n v5 = 1;\n do\n {\n if ( !(a1 % v5) && !(a2 % v5) )\n v4 = v5;\n ++v5;\n }\n while ( v3 != v5 );\n v6 = (double)v4;\n if ( (double)v4 < 0.0 )\n v7 = (int)sqrt(v6);\n else\n v7 = (int)sqrt(v6);\n if ( v7 <= 0 )\n return 0LL;\n }\n v8 = v7 + 1;\n v9 = 1;\n v10 = 0;\n do\n {\n if ( !(v4 % v9) )\n v10 += (v4 / v9 != v9) + 1;\n ++v9;\n }\n while ( v8 != v9 );\n return v10;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1280(int a1, int a2) {\n int v2;\n int v3;\n int v4;\n int v5;\n double v6;\n int v7;\n int v8;\n int v9;\n unsigned int v10;\n v2 = a2;\n if (a1 <= a2) v2 = a1;\n if (v2 <= 0) {\n v7 = 1;\n v4 = 1;\n } else {\n v3 = v2 + 1;\n v4 = 1;\n v5 = 1;\n do {\n if (!(a1 % v5) && !(a2 % v5)) v4 = v5;\n ++v5;\n } while (v3 != v5);\n v6 = (double)v4;\n if ((double)v4 < 0.0)\n v7 = (int)sqrt(v6);\n else\n v7 = (int)sqrt(v6);\n if (v7 <= 0) return 0LL;\n }\n v8 = v7 + 1;\n v9 = 1;\n v10 = 0;\n do {\n if (!(v4 % v9)) v10 += (v4 / v9 != v9) + 1;\n ++v9;\n } while (v8 != v9);\n return v10;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n int v2;\n int v3;\n int v4;\n int v5;\n double v6;\n int v7;\n int v8;\n int v9;\n unsigned int v10;\n v2 = a2;\n if (a1 <= a2) v2 = a1;\n if (v2 <= 0) {\n v7 = 1;\n v4 = 1;\n } else {\n v3 = v2 + 1;\n v4 = 1;\n v5 = 1;\n do {\n if (!(a1 % v5) && !(a2 % v5)) v4 = v5;\n ++v5;\n } while (v3 != v5);\n v6 = (double)v4;\n if ((double)v4 < 0.0)\n v7 = (int)sqrt(v6);\n else\n v7 = (int)sqrt(v6);\n if (v7 <= 0) return 0LL;\n }\n v8 = v7 + 1;\n v9 = 1;\n v10 = 0;\n do {\n if (!(v4 % v9)) v10 += (v4 / v9 != v9) + 1;\n ++v9;\n } while (v8 != v9);\n return v10;\n}" + }, + { + "index": 502, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n, int m) {\n int r = n % m;\n return r;\n}", + "test": "int main() {\n\n assert(func0(3, 3) == 0);\n\n assert(func0(10, 3) == 1);\n\n assert(func0(16, 5) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov -0x14(%rbp),%eax\ncltd\nidivl -0x18(%rbp)\nmov %edx,-0x4(%rbp)\nmov -0x4(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_18]\nmov [rbp+var_4], edx\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n return (unsigned int)(a1 % a2);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_18]\nmov [rbp+var_4], edx\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2)\n{\n return (unsigned int)(a1 % a2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2) { return (unsigned int)(a1 % a2); }", + "ida_pseudo_norm": "long long func0(int a1, int a2) { return (unsigned int)(a1 % a2); }" + }, + { + "index": 503, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int nums[], int size, int result[]) {\n for (int i = 0; i < size - 1; i++) {\n result[i] = nums[i] + nums[i + 1];\n }\n}", + "test": "int main() {\n\n int result1[7];\n\n int nums1[] = {1, 1, 3, 4, 4, 5, 6, 7};\n\n func0(nums1, 8, result1);\n\n int exp1[] = {2, 4, 7, 8, 9, 11, 13};\n\n for (int i = 0; i < 7; i++) {\n\n assert(result1[i] == exp1[i]);\n\n }\n\n\n\n int result2[5];\n\n int nums2[] = {4, 5, 8, 9, 6, 10};\n\n func0(nums2, 6, result2);\n\n int exp2[] = {9, 13, 17, 15, 16};\n\n for (int i = 0; i < 5; i++) {\n\n assert(result2[i] == exp2[i]);\n\n }\n\n\n\n int result3[9];\n\n int nums3[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n func0(nums3, 10, result3);\n\n int exp3[] = {3, 5, 7, 9, 11, 13, 15, 17, 19};\n\n for (int i = 0; i < 9; i++) {\n\n assert(result3[i] == exp3[i]);\n\n }\n\n\n\n printf(\"All assertions passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11f1 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%ecx\nmov -0x4(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rsi\nmov -0x28(%rbp),%rax\nadd %rsi,%rax\nadd %ecx,%edx\nmov %edx,(%rax)\naddl $0x1,-0x4(%rbp)\nmov -0x1c(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x4(%rbp)\njl 11a5 \npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_4], 0\njmp short loc_11F1\nloc_11A5:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov ecx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rsi, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rsi\nadd edx, ecx\nmov [rax], edx\nadd [rbp+var_4], 1\nloc_11F1:\nmov eax, [rbp+var_1C]\nsub eax, 1\ncmp [rbp+var_4], eax\njl short loc_11A5\nnop\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3)\n{\n __int64 result; // rax\n int i; // [rsp+24h] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = (unsigned int)(a2 - 1);\n if ( i >= (int)result )\n break;\n *(_DWORD *)(4LL * i + a3) = *(_DWORD *)(4LL * i + a1) + *(_DWORD *)(4 * (i + 1LL) + a1);\n }\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_4], 0\njmp short loc_11F1\nloc_11A5:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov ecx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rsi, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rsi\nadd edx, ecx\nmov [rax], edx\nadd [rbp+var_4], 1\nloc_11F1:\nmov eax, [rbp+var_1C]\nsub eax, 1\ncmp [rbp+var_4], eax\njl short loc_11A5\nnop\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2, __int64 a3)\n{\n __int64 result; // rax\n int i; // [rsp+24h] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = (unsigned int)(a2 - 1);\n if ( i >= (int)result )\n break;\n *(_DWORD *)(4LL * i + a3) = *(_DWORD *)(4LL * i + a1) + *(_DWORD *)(4 * (i + 1LL) + a1);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2, long long a3) {\n long long result;\n int i;\n for (i = 0;; ++i) {\n result = (unsigned int)(a2 - 1);\n if (i >= (int)result) break;\n *(uint32_t *)(4LL * i + a3) =\n *(uint32_t *)(4LL * i + a1) + *(uint32_t *)(4 * (i + 1LL) + a1);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3) {\n long long result;\n int i;\n for (i = 0;; ++i) {\n result = (unsigned int)(a2 - 1);\n if (i >= (int)result) break;\n *(uint32_t *)(4LL * i + a3) =\n *(uint32_t *)(4LL * i + a1) + *(uint32_t *)(4 * (i + 1LL) + a1);\n }\n return result;\n}" + }, + { + "index": 503, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int nums[], int size, int result[]) {\n for (int i = 0; i < size - 1; i++) {\n result[i] = nums[i] + nums[i + 1];\n }\n}", + "test": "int main() {\n\n int result1[7];\n\n int nums1[] = {1, 1, 3, 4, 4, 5, 6, 7};\n\n func0(nums1, 8, result1);\n\n int exp1[] = {2, 4, 7, 8, 9, 11, 13};\n\n for (int i = 0; i < 7; i++) {\n\n assert(result1[i] == exp1[i]);\n\n }\n\n\n\n int result2[5];\n\n int nums2[] = {4, 5, 8, 9, 6, 10};\n\n func0(nums2, 6, result2);\n\n int exp2[] = {9, 13, 17, 15, 16};\n\n for (int i = 0; i < 5; i++) {\n\n assert(result2[i] == exp2[i]);\n\n }\n\n\n\n int result3[9];\n\n int nums3[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n func0(nums3, 10, result3);\n\n int exp3[] = {3, 5, 7, 9, 11, 13, 15, 17, 19};\n\n for (int i = 0; i < 9; i++) {\n\n assert(result3[i] == exp3[i]);\n\n }\n\n\n\n printf(\"All assertions passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%esi\njle 11b0 \nlea -0x2(%rsi),%esi\nmov $0x0,%eax\nmov 0x4(%rdi,%rax,4),%ecx\nadd (%rdi,%rax,4),%ecx\nmov %ecx,(%rdx,%rax,4)\nmov %rax,%rcx\nadd $0x1,%rax\ncmp %rsi,%rcx\njne 119a \nretq\n", + "ida_asm": "func0:\nendbr64\ncmp esi, 1\njle short locret_11AD\nlea esi, [rsi-1]\nmov eax, 0\nloc_119A:\nmov ecx, [rdi+rax*4+4]\nadd ecx, [rdi+rax*4]\nmov [rdx+rax*4], ecx\nadd rax, 1\ncmp rax, rsi\njnz short loc_119A\nlocret_11AD:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2, __int64 a3)\n{\n __int64 v3; // rsi\n __int64 v4; // rax\n\n if ( a2 > 1 )\n {\n v3 = (unsigned int)(a2 - 1);\n v4 = 0LL;\n do\n {\n *(_DWORD *)(a3 + 4 * v4) = *(_DWORD *)(a1 + 4 * v4) + *(_DWORD *)(a1 + 4 * v4 + 4);\n ++v4;\n }\n while ( v4 != v3 );\n }\n}", + "ida_strip_asm": "sub_1189:\nendbr64\ncmp esi, 1\njle short locret_11AD\nlea esi, [rsi-1]\nmov eax, 0\nloc_119A:\nmov ecx, [rdi+rax*4+4]\nadd ecx, [rdi+rax*4]\nmov [rdx+rax*4], ecx\nadd rax, 1\ncmp rax, rsi\njnz short loc_119A\nlocret_11AD:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1189(__int64 a1, int a2, __int64 a3)\n{\n __int64 v3; // rsi\n __int64 v4; // rax\n\n if ( a2 > 1 )\n {\n v3 = (unsigned int)(a2 - 1);\n v4 = 0LL;\n do\n {\n *(_DWORD *)(a3 + 4 * v4) = *(_DWORD *)(a1 + 4 * v4) + *(_DWORD *)(a1 + 4 * v4 + 4);\n ++v4;\n }\n while ( v4 != v3 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1189(long long a1, int a2, long long a3) {\n long long v3;\n long long v4;\n if (a2 > 1) {\n v3 = (unsigned int)(a2 - 1);\n v4 = 0LL;\n do {\n *(uint32_t *)(a3 + 4 * v4) =\n *(uint32_t *)(a1 + 4 * v4) + *(uint32_t *)(a1 + 4 * v4 + 4);\n ++v4;\n } while (v4 != v3);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2, long long a3) {\n long long v3;\n long long v4;\n if (a2 > 1) {\n v3 = (unsigned int)(a2 - 1);\n v4 = 0LL;\n do {\n *(uint32_t *)(a3 + 4 * v4) =\n *(uint32_t *)(a1 + 4 * v4) + *(uint32_t *)(a1 + 4 * v4 + 4);\n ++v4;\n } while (v4 != v3);\n }\n}" + }, + { + "index": 503, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int nums[], int size, int result[]) {\n for (int i = 0; i < size - 1; i++) {\n result[i] = nums[i] + nums[i + 1];\n }\n}", + "test": "int main() {\n\n int result1[7];\n\n int nums1[] = {1, 1, 3, 4, 4, 5, 6, 7};\n\n func0(nums1, 8, result1);\n\n int exp1[] = {2, 4, 7, 8, 9, 11, 13};\n\n for (int i = 0; i < 7; i++) {\n\n assert(result1[i] == exp1[i]);\n\n }\n\n\n\n int result2[5];\n\n int nums2[] = {4, 5, 8, 9, 6, 10};\n\n func0(nums2, 6, result2);\n\n int exp2[] = {9, 13, 17, 15, 16};\n\n for (int i = 0; i < 5; i++) {\n\n assert(result2[i] == exp2[i]);\n\n }\n\n\n\n int result3[9];\n\n int nums3[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n func0(nums3, 10, result3);\n\n int exp3[] = {3, 5, 7, 9, 11, 13, 15, 17, 19};\n\n for (int i = 0; i < 9; i++) {\n\n assert(result3[i] == exp3[i]);\n\n }\n\n\n\n printf(\"All assertions passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%esi\njle 1496 \nsub $0x2,%esi\nxor %eax,%eax\nxchg %ax,%ax\nmov 0x4(%rdi,%rax,4),%ecx\nadd (%rdi,%rax,4),%ecx\nmov %ecx,(%rdx,%rax,4)\nmov %rax,%rcx\nadd $0x1,%rax\ncmp %rsi,%rcx\njne 1480 \nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ncmp esi, 1\njle short locret_13E3\nsub esi, 1\nxor eax, eax\nxchg ax, ax\nloc_13D0:\nmov ecx, [rdi+rax*4+4]\nadd ecx, [rdi+rax*4]\nmov [rdx+rax*4], ecx\nadd rax, 1\ncmp rsi, rax\njnz short loc_13D0\nlocret_13E3:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2, __int64 a3)\n{\n __int64 v3; // rsi\n __int64 v4; // rax\n\n if ( a2 > 1 )\n {\n v3 = (unsigned int)(a2 - 1);\n v4 = 0LL;\n do\n {\n *(_DWORD *)(a3 + 4 * v4) = *(_DWORD *)(a1 + 4 * v4) + *(_DWORD *)(a1 + 4 * v4 + 4);\n ++v4;\n }\n while ( v3 != v4 );\n }\n}", + "ida_strip_asm": "sub_13C0:\nendbr64\ncmp esi, 1\njle short locret_13E3\nsub esi, 1\nxor eax, eax\nxchg ax, ax\nloc_13D0:\nmov ecx, [rdi+rax*4+4]\nadd ecx, [rdi+rax*4]\nmov [rdx+rax*4], ecx\nadd rax, 1\ncmp rsi, rax\njnz short loc_13D0\nlocret_13E3:\nretn", + "ida_strip_pseudo": "void __fastcall sub_13C0(__int64 a1, int a2, __int64 a3)\n{\n __int64 v3; // rsi\n __int64 v4; // rax\n\n if ( a2 > 1 )\n {\n v3 = (unsigned int)(a2 - 1);\n v4 = 0LL;\n do\n {\n *(_DWORD *)(a3 + 4 * v4) = *(_DWORD *)(a1 + 4 * v4) + *(_DWORD *)(a1 + 4 * v4 + 4);\n ++v4;\n }\n while ( v3 != v4 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_13C0(long long a1, int a2, long long a3) {\n long long v3;\n long long v4;\n if (a2 > 1) {\n v3 = (unsigned int)(a2 - 1);\n v4 = 0LL;\n do {\n *(uint32_t *)(a3 + 4 * v4) =\n *(uint32_t *)(a1 + 4 * v4) + *(uint32_t *)(a1 + 4 * v4 + 4);\n ++v4;\n } while (v3 != v4);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2, long long a3) {\n long long v3;\n long long v4;\n if (a2 > 1) {\n v3 = (unsigned int)(a2 - 1);\n v4 = 0LL;\n do {\n *(uint32_t *)(a3 + 4 * v4) =\n *(uint32_t *)(a1 + 4 * v4) + *(uint32_t *)(a1 + 4 * v4 + 4);\n ++v4;\n } while (v3 != v4);\n }\n}" + }, + { + "index": 504, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int sum = 0;\n for (int i = 1; i <= n; i++) {\n sum += i * i * i;\n }\n return sum;\n}", + "test": "int main() {\n\n assert(func0(5) == 225);\n\n assert(func0(2) == 9);\n\n assert(func0(3) == 36);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x1,-0x4(%rbp)\njmp 1175 \nmov -0x4(%rbp),%eax\nimul %eax,%eax\nimul -0x4(%rbp),%eax\nadd %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x14(%rbp),%eax\njle 1164 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 1\njmp short loc_1175\nloc_1164:\nmov eax, [rbp+var_4]\nimul eax, eax\nimul eax, [rbp+var_4]\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_1175:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_14]\njle short loc_1164\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v2; // [rsp+Ch] [rbp-8h]\n int i; // [rsp+10h] [rbp-4h]\n\n v2 = 0;\n for ( i = 1; i <= a1; ++i )\n v2 += i * i * i;\n return v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 1\njmp short loc_1175\nloc_1164:\nmov eax, [rbp+var_4]\nimul eax, eax\nimul eax, [rbp+var_4]\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_1175:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_14]\njle short loc_1164\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n unsigned int v2; // [rsp+Ch] [rbp-8h]\n int i; // [rsp+10h] [rbp-4h]\n\n v2 = 0;\n for ( i = 1; i <= a1; ++i )\n v2 += i * i * i;\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n unsigned int v2;\n int i;\n v2 = 0;\n for (i = 1; i <= a1; ++i) v2 += i * i * i;\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v2;\n int i;\n v2 = 0;\n for (i = 1; i <= a1; ++i) v2 += i * i * i;\n return v2;\n}" + }, + { + "index": 504, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int sum = 0;\n for (int i = 1; i <= n; i++) {\n sum += i * i * i;\n }\n return sum;\n}", + "test": "int main() {\n\n assert(func0(5) == 225);\n\n assert(func0(2) == 9);\n\n assert(func0(3) == 36);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\njle 1172 \nadd $0x1,%edi\nmov $0x1,%eax\nmov $0x0,%ecx\nmov %eax,%edx\nimul %eax,%edx\nimul %eax,%edx\nadd %edx,%ecx\nadd $0x1,%eax\ncmp %edi,%eax\njne 115e \nmov %ecx,%eax\nretq\nmov $0x0,%ecx\njmp 116f \n", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njle short loc_1172\nadd edi, 1\nmov eax, 1\nmov ecx, 0\nloc_115E:\nmov edx, eax\nimul edx, eax\nimul edx, eax\nadd ecx, edx\nadd eax, 1\ncmp eax, edi\njnz short loc_115E\nloc_116F:\nmov eax, ecx\nretn\nloc_1172:\nmov ecx, 0\njmp short loc_116F", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // edi\n int v2; // eax\n unsigned int v3; // ecx\n\n if ( a1 <= 0 )\n {\n return 0;\n }\n else\n {\n v1 = a1 + 1;\n v2 = 1;\n v3 = 0;\n do\n {\n v3 += v2 * v2 * v2;\n ++v2;\n }\n while ( v2 != v1 );\n }\n return v3;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ntest edi, edi\njle short loc_1172\nadd edi, 1\nmov eax, 1\nmov ecx, 0\nloc_115E:\nmov edx, eax\nimul edx, eax\nimul edx, eax\nadd ecx, edx\nadd eax, 1\ncmp eax, edi\njnz short loc_115E\nloc_116F:\nmov eax, ecx\nretn\nloc_1172:\nmov ecx, 0\njmp short loc_116F", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v1; // edi\n int v2; // eax\n unsigned int v3; // ecx\n\n if ( a1 <= 0 )\n {\n return 0;\n }\n else\n {\n v1 = a1 + 1;\n v2 = 1;\n v3 = 0;\n do\n {\n v3 += v2 * v2 * v2;\n ++v2;\n }\n while ( v2 != v1 );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v1;\n int v2;\n unsigned int v3;\n if (a1 <= 0) {\n return 0;\n } else {\n v1 = a1 + 1;\n v2 = 1;\n v3 = 0;\n do {\n v3 += v2 * v2 * v2;\n ++v2;\n } while (v2 != v1);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v2;\n unsigned int v3;\n if (a1 <= 0) {\n return 0;\n } else {\n v1 = a1 + 1;\n v2 = 1;\n v3 = 0;\n do {\n v3 += v2 * v2 * v2;\n ++v2;\n } while (v2 != v1);\n }\n return v3;\n}" + }, + { + "index": 505, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int *A, int length) {\n int k = 0;\n for (int i = 0; i < length; i++) {\n if (A[i]) {\n A[k] = A[i];\n k++;\n }\n }\n for (int i = k; i < length; i++) {\n A[i] = 0;\n }\n}", + "test": "int main() {\n\n int array1[9] = {6, 0, 8, 2, 3, 0, 4, 0, 1};\n\n int result1[9] = {6, 8, 2, 3, 4, 1, 0, 0, 0};\n\n func0(array1, 9);\n\n assert(memcmp(array1, result1, 9 * sizeof(int)) == 0);\n\n\n\n int array2[9] = {4, 0, 2, 7, 0, 9, 0, 12, 0};\n\n int result2[9] = {4, 2, 7, 9, 12, 0, 0, 0, 0};\n\n func0(array2, 9);\n\n assert(memcmp(array2, result2, 9 * sizeof(int)) == 0);\n\n\n\n int array3[9] = {3, 11, 0, 74, 14, 0, 1, 0, 2};\n\n int result3[9] = {3, 11, 74, 14, 1, 2, 0, 0, 0};\n\n func0(array3, 9);\n\n assert(memcmp(array3, result3, 9 * sizeof(int)) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11f7 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ntest %eax,%eax\nje 11f3 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0xc(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0xc(%rbp)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11a8 \nmov -0xc(%rbp),%eax\nmov %eax,-0x4(%rbp)\njmp 1225 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovl $0x0,(%rax)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1207 \npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_11F7\nloc_11A8:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njz short loc_11F3\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_C], 1\nloc_11F3:\nadd [rbp+var_8], 1\nloc_11F7:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_11A8\nmov eax, [rbp+var_C]\nmov [rbp+var_4], eax\njmp short loc_1225\nloc_1207:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov dword ptr [rax], 0\nadd [rbp+var_4], 1\nloc_1225:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1207\nnop\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 result; // rax\n unsigned int v3; // [rsp+10h] [rbp-Ch]\n int i; // [rsp+14h] [rbp-8h]\n unsigned int j; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) )\n *(_DWORD *)(4LL * (int)v3++ + a1) = *(_DWORD *)(4LL * i + a1);\n }\n for ( j = v3; ; ++j )\n {\n result = j;\n if ( (int)j >= a2 )\n break;\n *(_DWORD *)(4LL * (int)j + a1) = 0;\n }\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_11F7\nloc_11A8:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njz short loc_11F3\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_C], 1\nloc_11F3:\nadd [rbp+var_8], 1\nloc_11F7:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_11A8\nmov eax, [rbp+var_C]\nmov [rbp+var_4], eax\njmp short loc_1225\nloc_1207:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov dword ptr [rax], 0\nadd [rbp+var_4], 1\nloc_1225:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1207\nnop\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2)\n{\n __int64 result; // rax\n unsigned int v3; // [rsp+10h] [rbp-Ch]\n int i; // [rsp+14h] [rbp-8h]\n unsigned int j; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) )\n *(_DWORD *)(4LL * (int)v3++ + a1) = *(_DWORD *)(4LL * i + a1);\n }\n for ( j = v3; ; ++j )\n {\n result = j;\n if ( (int)j >= a2 )\n break;\n *(_DWORD *)(4LL * (int)j + a1) = 0;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2) {\n long long result;\n unsigned int v3;\n int i;\n unsigned int j;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(uint32_t *)(4LL * i + a1))\n *(uint32_t *)(4LL * (int)v3++ + a1) = *(uint32_t *)(4LL * i + a1);\n }\n for (j = v3;; ++j) {\n result = j;\n if ((int)j >= a2) break;\n *(uint32_t *)(4LL * (int)j + a1) = 0;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long result;\n unsigned int v3;\n int i;\n unsigned int j;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(uint32_t *)(4LL * i + a1))\n *(uint32_t *)(4LL * (int)v3++ + a1) = *(uint32_t *)(4LL * i + a1);\n }\n for (j = v3;; ++j) {\n result = j;\n if ((int)j >= a2) break;\n *(uint32_t *)(4LL * (int)j + a1) = 0;\n }\n return result;\n}" + }, + { + "index": 505, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int *A, int length) {\n int k = 0;\n for (int i = 0; i < length; i++) {\n if (A[i]) {\n A[k] = A[i];\n k++;\n }\n }\n for (int i = k; i < length; i++) {\n A[i] = 0;\n }\n}", + "test": "int main() {\n\n int array1[9] = {6, 0, 8, 2, 3, 0, 4, 0, 1};\n\n int result1[9] = {6, 8, 2, 3, 4, 1, 0, 0, 0};\n\n func0(array1, 9);\n\n assert(memcmp(array1, result1, 9 * sizeof(int)) == 0);\n\n\n\n int array2[9] = {4, 0, 2, 7, 0, 9, 0, 12, 0};\n\n int result2[9] = {4, 2, 7, 9, 12, 0, 0, 0, 0};\n\n func0(array2, 9);\n\n assert(memcmp(array2, result2, 9 * sizeof(int)) == 0);\n\n\n\n int array3[9] = {3, 11, 0, 74, 14, 0, 1, 0, 2};\n\n int result3[9] = {3, 11, 74, 14, 1, 2, 0, 0, 0};\n\n func0(array3, 9);\n\n assert(memcmp(array3, result3, 9 * sizeof(int)) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11e9 \nmov %rdi,%rax\nlea -0x1(%rsi),%r10d\nlea 0x4(%rdi),%r11\nmov %r10d,%edx\nlea (%r11,%rdx,4),%r8\nmov $0x0,%ecx\njmp 11b3 \nadd $0x4,%rax\ncmp %r8,%rax\nje 11c5 \nmov (%rax),%edx\ntest %edx,%edx\nje 11aa \nmovslq %ecx,%r9\nmov %edx,(%rdi,%r9,4)\nadd $0x1,%ecx\njmp 11aa \ncmp %esi,%ecx\njge 11e9 \nmovslq %ecx,%rdx\nlea (%rdi,%rdx,4),%rax\nsub %ecx,%r10d\nadd %rdx,%r10\nlea (%r11,%r10,4),%rdx\nmovl $0x0,(%rax)\nadd $0x4,%rax\ncmp %rdx,%rax\njne 11da \nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short locret_11E0\nmovsxd rax, esi\nlea r8, [rdi+rax*4]\nmov rax, rdi\nmov ecx, 0\njmp short loc_11AB\nloc_11A2:\nadd rax, 4\ncmp rax, r8\njz short loc_11BD\nloc_11AB:\nmov edx, [rax]\ntest edx, edx\njz short loc_11A2\nmovsxd r9, ecx\nmov [rdi+r9*4], edx\nadd ecx, 1\njmp short loc_11A2\nloc_11BD:\ncmp ecx, esi\njge short locret_11E0\nmovsxd rdx, ecx\nlea rax, [rdi+rdx*4]\nsub esi, ecx\nadd rsi, rdx\nlea rdx, [rdi+rsi*4]\nloc_11D1:\nmov dword ptr [rax], 0\nadd rax, 4\ncmp rax, rdx\njnz short loc_11D1\nlocret_11E0:\nretn", + "ida_pseudo": "void __fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n int v3; // ecx\n _DWORD *v4; // rax\n\n if ( a2 > 0 )\n {\n v2 = a1;\n v3 = 0;\n do\n {\n if ( *v2 )\n a1[v3++] = *v2;\n ++v2;\n }\n while ( v2 != &a1[a2] );\n if ( v3 < a2 )\n {\n v4 = &a1[v3];\n do\n *v4++ = 0;\n while ( v4 != &a1[v3 + (unsigned __int64)(unsigned int)(a2 - v3)] );\n }\n }\n}", + "ida_strip_asm": "sub_1189:\nendbr64\ntest esi, esi\njle short locret_11E0\nmovsxd rax, esi\nlea r8, [rdi+rax*4]\nmov rax, rdi\nmov ecx, 0\njmp short loc_11AB\nloc_11A2:\nadd rax, 4\ncmp rax, r8\njz short loc_11BD\nloc_11AB:\nmov edx, [rax]\ntest edx, edx\njz short loc_11A2\nmovsxd r9, ecx\nmov [rdi+r9*4], edx\nadd ecx, 1\njmp short loc_11A2\nloc_11BD:\ncmp ecx, esi\njge short locret_11E0\nmovsxd rdx, ecx\nlea rax, [rdi+rdx*4]\nsub esi, ecx\nadd rsi, rdx\nlea rdx, [rdi+rsi*4]\nloc_11D1:\nmov dword ptr [rax], 0\nadd rax, 4\ncmp rax, rdx\njnz short loc_11D1\nlocret_11E0:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1189(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n int v3; // ecx\n _DWORD *v4; // rax\n\n if ( a2 > 0 )\n {\n v2 = a1;\n v3 = 0;\n do\n {\n if ( *v2 )\n a1[v3++] = *v2;\n ++v2;\n }\n while ( v2 != &a1[a2] );\n if ( v3 < a2 )\n {\n v4 = &a1[v3];\n do\n *v4++ = 0;\n while ( v4 != &a1[v3 + (unsigned __int64)(unsigned int)(a2 - v3)] );\n }\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1189(uint32_t *a1, int a2) {\n uint32_t *v2;\n int v3;\n uint32_t *v4;\n if (a2 > 0) {\n v2 = a1;\n v3 = 0;\n do {\n if (*v2) a1[v3++] = *v2;\n ++v2;\n } while (v2 != &a1[a2]);\n if (v3 < a2) {\n v4 = &a1[v3];\n do\n *v4++ = 0;\n while (v4 != &a1[v3 + (unsigned long long)(unsigned int)(a2 - v3)]);\n }\n }\n}", + "ida_pseudo_norm": "void func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n int v3;\n uint32_t *v4;\n if (a2 > 0) {\n v2 = a1;\n v3 = 0;\n do {\n if (*v2) a1[v3++] = *v2;\n ++v2;\n } while (v2 != &a1[a2]);\n if (v3 < a2) {\n v4 = &a1[v3];\n do\n *v4++ = 0;\n while (v4 != &a1[v3 + (unsigned long long)(unsigned int)(a2 - v3)]);\n }\n }\n}" + }, + { + "index": 505, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int *A, int length) {\n int k = 0;\n for (int i = 0; i < length; i++) {\n if (A[i]) {\n A[k] = A[i];\n k++;\n }\n }\n for (int i = k; i < length; i++) {\n A[i] = 0;\n }\n}", + "test": "int main() {\n\n int array1[9] = {6, 0, 8, 2, 3, 0, 4, 0, 1};\n\n int result1[9] = {6, 8, 2, 3, 4, 1, 0, 0, 0};\n\n func0(array1, 9);\n\n assert(memcmp(array1, result1, 9 * sizeof(int)) == 0);\n\n\n\n int array2[9] = {4, 0, 2, 7, 0, 9, 0, 12, 0};\n\n int result2[9] = {4, 2, 7, 9, 12, 0, 0, 0, 0};\n\n func0(array2, 9);\n\n assert(memcmp(array2, result2, 9 * sizeof(int)) == 0);\n\n\n\n int array3[9] = {3, 11, 0, 74, 14, 0, 1, 0, 2};\n\n int result3[9] = {3, 11, 74, 14, 1, 2, 0, 0, 0};\n\n func0(array3, 9);\n\n assert(memcmp(array3, result3, 9 * sizeof(int)) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 151f \nlea -0x1(%rsi),%edx\nlea 0x4(%rdi),%r11\nmov %rdi,%rax\nxor %ecx,%ecx\nmov %rdx,%r10\nlea (%r11,%rdx,4),%r8\nnopl 0x0(%rax,%rax,1)\nmov (%rax),%edx\ntest %edx,%edx\nje 14f0 \nmovslq %ecx,%r9\nadd $0x1,%ecx\nmov %edx,(%rdi,%r9,4)\nadd $0x4,%rax\ncmp %r8,%rax\njne 14e0 \ncmp %esi,%ecx\njge 151f \nmovslq %ecx,%rdx\nsub %ecx,%r10d\nadd %rdx,%r10\nlea (%rdi,%rdx,4),%rax\nlea (%r11,%r10,4),%rdx\nxchg %ax,%ax\nmovl $0x0,(%rax)\nadd $0x4,%rax\ncmp %rdx,%rax\njne 1510 \nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short locret_1480\nmovsxd rdx, esi\nmov rax, rdi\nxor ecx, ecx\nlea r8, [rdi+rdx*4]\nnop dword ptr [rax+00h]\nloc_1448:\nmov edx, [rax]\ntest edx, edx\njz short loc_1458\nmovsxd r9, ecx\nadd ecx, 1\nmov [rdi+r9*4], edx\nloc_1458:\nadd rax, 4\ncmp r8, rax\njnz short loc_1448\ncmp ecx, esi\njge short locret_1480\nsub esi, 1\nsub esi, ecx\nmovsxd rcx, ecx\nlea rdx, ds:4[rsi*4]; n\nlea rdi, [rdi+rcx*4]; s\nxor esi, esi; c\njmp _memset\nlocret_1480:\nretn", + "ida_pseudo": "void __fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n int v3; // ecx\n __int64 v4; // r9\n\n if ( a2 > 0 )\n {\n v2 = a1;\n v3 = 0;\n do\n {\n if ( *v2 )\n {\n v4 = v3++;\n a1[v4] = *v2;\n }\n ++v2;\n }\n while ( &a1[a2] != v2 );\n if ( v3 < a2 )\n memset(&a1[v3], 0, 4LL * (unsigned int)(a2 - 1 - v3) + 4);\n }\n}", + "ida_strip_asm": "sub_1430:\nendbr64\ntest esi, esi\njle short locret_1480\nmovsxd rdx, esi\nmov rax, rdi\nxor ecx, ecx\nlea r8, [rdi+rdx*4]\nnop dword ptr [rax+00h]\nloc_1448:\nmov edx, [rax]\ntest edx, edx\njz short loc_1458\nmovsxd r9, ecx\nadd ecx, 1\nmov [rdi+r9*4], edx\nloc_1458:\nadd rax, 4\ncmp r8, rax\njnz short loc_1448\ncmp ecx, esi\njge short locret_1480\nsub esi, 1\nsub esi, ecx\nmovsxd rcx, ecx\nlea rdx, ds:4[rsi*4]; n\nlea rdi, [rdi+rcx*4]; s\nxor esi, esi; c\njmp _memset\nlocret_1480:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1430(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n int v3; // ecx\n __int64 v4; // r9\n\n if ( a2 > 0 )\n {\n v2 = a1;\n v3 = 0;\n do\n {\n if ( *v2 )\n {\n v4 = v3++;\n a1[v4] = *v2;\n }\n ++v2;\n }\n while ( &a1[a2] != v2 );\n if ( v3 < a2 )\n memset(&a1[v3], 0, 4LL * (unsigned int)(a2 - 1 - v3) + 4);\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1430(uint32_t *a1, int a2) {\n uint32_t *v2;\n int v3;\n long long v4;\n if (a2 > 0) {\n v2 = a1;\n v3 = 0;\n do {\n if (*v2) {\n v4 = v3++;\n a1[v4] = *v2;\n }\n ++v2;\n } while (&a1[a2] != v2);\n if (v3 < a2) memset(&a1[v3], 0, 4LL * (unsigned int)(a2 - 1 - v3) + 4);\n }\n}", + "ida_pseudo_norm": "void func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n int v3;\n long long v4;\n if (a2 > 0) {\n v2 = a1;\n v3 = 0;\n do {\n if (*v2) {\n v4 = v3++;\n a1[v4] = *v2;\n }\n ++v2;\n } while (&a1[a2] != v2);\n if (v3 < a2) memset(&a1[v3], 0, 4LL * (unsigned int)(a2 - 1 - v3) + 4);\n }\n}" + }, + { + "index": 505, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int *A, int length) {\n int k = 0;\n for (int i = 0; i < length; i++) {\n if (A[i]) {\n A[k] = A[i];\n k++;\n }\n }\n for (int i = k; i < length; i++) {\n A[i] = 0;\n }\n}", + "test": "int main() {\n\n int array1[9] = {6, 0, 8, 2, 3, 0, 4, 0, 1};\n\n int result1[9] = {6, 8, 2, 3, 4, 1, 0, 0, 0};\n\n func0(array1, 9);\n\n assert(memcmp(array1, result1, 9 * sizeof(int)) == 0);\n\n\n\n int array2[9] = {4, 0, 2, 7, 0, 9, 0, 12, 0};\n\n int result2[9] = {4, 2, 7, 9, 12, 0, 0, 0, 0};\n\n func0(array2, 9);\n\n assert(memcmp(array2, result2, 9 * sizeof(int)) == 0);\n\n\n\n int array3[9] = {3, 11, 0, 74, 14, 0, 1, 0, 2};\n\n int result3[9] = {3, 11, 74, 14, 1, 2, 0, 0, 0};\n\n func0(array3, 9);\n\n assert(memcmp(array3, result3, 9 * sizeof(int)) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 14b0 \nlea -0x1(%rsi),%edx\nmov %rdi,%rax\nxor %ecx,%ecx\nmov %rdx,%r10\nlea 0x4(%rdi,%rdx,4),%r8\nnopl 0x0(%rax,%rax,1)\nmov (%rax),%edx\ntest %edx,%edx\nje 1480 \nmovslq %ecx,%r9\nadd $0x1,%ecx\nmov %edx,(%rdi,%r9,4)\nadd $0x4,%rax\ncmp %rax,%r8\njne 1470 \ncmp %esi,%ecx\njge 14b0 \nsub %ecx,%r10d\nmovslq %ecx,%rcx\nxor %esi,%esi\nlea 0x4(,%r10,4),%rdx\nlea (%rdi,%rcx,4),%rdi\njmpq 1090 \nnopw %cs:0x0(%rax,%rax,1)\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short locret_1480\nmovsxd rdx, esi\nmov rax, rdi\nxor ecx, ecx\nlea r8, [rdi+rdx*4]\nnop dword ptr [rax+00h]\nloc_1448:\nmov edx, [rax]\ntest edx, edx\njz short loc_1458\nmovsxd r9, ecx\nadd ecx, 1\nmov [rdi+r9*4], edx\nloc_1458:\nadd rax, 4\ncmp r8, rax\njnz short loc_1448\ncmp ecx, esi\njge short locret_1480\nsub esi, 1\nsub esi, ecx\nmovsxd rcx, ecx\nlea rdx, ds:4[rsi*4]; n\nlea rdi, [rdi+rcx*4]; s\nxor esi, esi; c\njmp _memset\nlocret_1480:\nretn", + "ida_pseudo": "void __fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n int v3; // ecx\n __int64 v4; // r9\n\n if ( a2 > 0 )\n {\n v2 = a1;\n v3 = 0;\n do\n {\n if ( *v2 )\n {\n v4 = v3++;\n a1[v4] = *v2;\n }\n ++v2;\n }\n while ( &a1[a2] != v2 );\n if ( v3 < a2 )\n memset(&a1[v3], 0, 4LL * (unsigned int)(a2 - 1 - v3) + 4);\n }\n}", + "ida_strip_asm": "sub_1430:\nendbr64\ntest esi, esi\njle short locret_1480\nmovsxd rdx, esi\nmov rax, rdi\nxor ecx, ecx\nlea r8, [rdi+rdx*4]\nnop dword ptr [rax+00h]\nloc_1448:\nmov edx, [rax]\ntest edx, edx\njz short loc_1458\nmovsxd r9, ecx\nadd ecx, 1\nmov [rdi+r9*4], edx\nloc_1458:\nadd rax, 4\ncmp r8, rax\njnz short loc_1448\ncmp ecx, esi\njge short locret_1480\nsub esi, 1\nsub esi, ecx\nmovsxd rcx, ecx\nlea rdx, ds:4[rsi*4]; n\nlea rdi, [rdi+rcx*4]; s\nxor esi, esi; c\njmp _memset\nlocret_1480:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1430(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n int v3; // ecx\n __int64 v4; // r9\n\n if ( a2 > 0 )\n {\n v2 = a1;\n v3 = 0;\n do\n {\n if ( *v2 )\n {\n v4 = v3++;\n a1[v4] = *v2;\n }\n ++v2;\n }\n while ( &a1[a2] != v2 );\n if ( v3 < a2 )\n memset(&a1[v3], 0, 4LL * (unsigned int)(a2 - 1 - v3) + 4);\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1430(uint32_t *a1, int a2) {\n uint32_t *v2;\n int v3;\n long long v4;\n if (a2 > 0) {\n v2 = a1;\n v3 = 0;\n do {\n if (*v2) {\n v4 = v3++;\n a1[v4] = *v2;\n }\n ++v2;\n } while (&a1[a2] != v2);\n if (v3 < a2) memset(&a1[v3], 0, 4LL * (unsigned int)(a2 - 1 - v3) + 4);\n }\n}", + "ida_pseudo_norm": "void func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n int v3;\n long long v4;\n if (a2 > 0) {\n v2 = a1;\n v3 = 0;\n do {\n if (*v2) {\n v4 = v3++;\n a1[v4] = *v2;\n }\n ++v2;\n } while (&a1[a2] != v2);\n if (v3 < a2) memset(&a1[v3], 0, 4LL * (unsigned int)(a2 - 1 - v3) + 4);\n }\n}" + }, + { + "index": 506, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n, int k) {\n int P[n + 1][k + 1];\n for (int i = 0; i <= n; i++) {\n int minValue = (i < k) ? i : k;\n for (int j = 0; j <= minValue; j++) {\n if (j == 0) {\n P[i][j] = 1;\n } else {\n P[i][j] = P[i - 1][j] + j * P[i - 1][j - 1];\n }\n if (j < k) {\n P[i][j + 1] = 0;\n }\n }\n }\n return P[n][k];\n}", + "test": "int main() {\n\n assert(func0(10, 2) == 90);\n\n assert(func0(10, 3) == 720);\n\n assert(func0(10, 1) == 10);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0x58,%rsp\nmov %edi,-0x64(%rbp)\nmov %esi,-0x68(%rbp)\nmov %fs:0x28,%rbx\nmov %rbx,-0x38(%rbp)\nxor %ebx,%ebx\nmov %rsp,%rcx\nmov %rcx,%r15\nmov -0x68(%rbp),%ecx\nlea 0x1(%rcx),%esi\nmov -0x64(%rbp),%ecx\nlea 0x1(%rcx),%edi\nmovslq %esi,%rcx\nsub $0x1,%rcx\nmov %rcx,-0x50(%rbp)\nmovslq %esi,%rcx\nmov %rcx,-0x80(%rbp)\nmovq $0x0,-0x78(%rbp)\nmovslq %esi,%rcx\nshl $0x2,%rcx\nmovslq %edi,%rbx\nsub $0x1,%rbx\nmov %rbx,-0x48(%rbp)\nmovslq %esi,%rbx\nmov %rbx,%r12\nmov $0x0,%r13d\nmovslq %edi,%rbx\nmov %rbx,%rax\nmov $0x0,%edx\nmov %r13,%r14\nimul %rax,%r14\nmov %rdx,%rbx\nimul %r12,%rbx\nadd %r14,%rbx\nmul %r12\nadd %rdx,%rbx\nmov %rbx,%rdx\nmovslq %esi,%rax\nmov %rax,%r10\nmov $0x0,%r11d\nmovslq %edi,%rax\nmov %rax,%r8\nmov $0x0,%r9d\nmov %r11,%rdx\nimul %r8,%rdx\nmov %r9,%rax\nimul %r10,%rax\nlea (%rdx,%rax,1),%rbx\nmov %r10,%rax\nmul %r8\nlea (%rbx,%rdx,1),%r8\nmov %r8,%rdx\nmovslq %esi,%rdx\nmovslq %edi,%rax\nimul %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%ebx\nmov $0x0,%edx\ndiv %rbx\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rdi\nsub %rdx,%rdi\nmov %rdi,%rdx\ncmp %rdx,%rsp\nje 1292 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 127b \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 12bc \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x40(%rbp)\nmovl $0x0,-0x58(%rbp)\njmpq 13d9 \nmov -0x58(%rbp),%eax\ncmp %eax,-0x68(%rbp)\ncmovle -0x68(%rbp),%eax\nmov %eax,-0x54(%rbp)\nmovl $0x0,-0x5c(%rbp)\njmpq 13c9 \ncmpl $0x0,-0x5c(%rbp)\njne 1321 \nmov %rcx,%rdi\nshr $0x2,%rdi\nmov -0x40(%rbp),%rax\nmov -0x5c(%rbp),%edx\nmovslq %edx,%rsi\nmov -0x58(%rbp),%edx\nmovslq %edx,%rdx\nimul %rdi,%rdx\nadd %rsi,%rdx\nmovl $0x1,(%rax,%rdx,4)\njmp 1395 \nmov %rcx,%rdi\nshr $0x2,%rdi\nmov -0x58(%rbp),%eax\nlea -0x1(%rax),%r8d\nmov -0x40(%rbp),%rax\nmov -0x5c(%rbp),%edx\nmovslq %edx,%rsi\nmovslq %r8d,%rdx\nimul %rdi,%rdx\nadd %rsi,%rdx\nmov (%rax,%rdx,4),%edx\nmov %rcx,%r8\nshr $0x2,%r8\nmov -0x58(%rbp),%eax\nlea -0x1(%rax),%esi\nmov -0x5c(%rbp),%eax\nlea -0x1(%rax),%edi\nmov -0x40(%rbp),%rax\nmovslq %edi,%rdi\nmovslq %esi,%rsi\nimul %r8,%rsi\nadd %rdi,%rsi\nmov (%rax,%rsi,4),%eax\nimul -0x5c(%rbp),%eax\nmov %rcx,%r8\nshr $0x2,%r8\nlea (%rdx,%rax,1),%esi\nmov -0x40(%rbp),%rax\nmov -0x5c(%rbp),%edx\nmovslq %edx,%rdi\nmov -0x58(%rbp),%edx\nmovslq %edx,%rdx\nimul %r8,%rdx\nadd %rdi,%rdx\nmov %esi,(%rax,%rdx,4)\nmov -0x5c(%rbp),%eax\ncmp -0x68(%rbp),%eax\njge 13c5 \nmov %rcx,%rdi\nshr $0x2,%rdi\nmov -0x5c(%rbp),%eax\nlea 0x1(%rax),%edx\nmov -0x40(%rbp),%rax\nmovslq %edx,%rsi\nmov -0x58(%rbp),%edx\nmovslq %edx,%rdx\nimul %rdi,%rdx\nadd %rsi,%rdx\nmovl $0x0,(%rax,%rdx,4)\naddl $0x1,-0x5c(%rbp)\nmov -0x5c(%rbp),%eax\ncmp -0x54(%rbp),%eax\njle 12f4 \naddl $0x1,-0x58(%rbp)\nmov -0x58(%rbp),%eax\ncmp -0x64(%rbp),%eax\njle 12db \nshr $0x2,%rcx\nmov %rcx,%rsi\nmov -0x40(%rbp),%rax\nmov -0x68(%rbp),%edx\nmovslq %edx,%rcx\nmov -0x64(%rbp),%edx\nmovslq %edx,%rdx\nimul %rsi,%rdx\nadd %rcx,%rdx\nmov (%rax,%rdx,4),%eax\nmov %r15,%rsp\nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\nje 141d \ncallq 1060 <__stack_chk_fail@plt>\nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 48h\nmov [rbp+var_44], edi\nmov [rbp+var_48], esi\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov rax, rsp\nmov r11, rax\nmov eax, [rbp+var_48]\nlea edi, [rax+1]\nmov eax, [rbp+var_44]\nlea r8d, [rax+1]\nmovsxd rax, edi\nsub rax, 1\nmov [rbp+var_30], rax\nmovsxd rax, edi\nlea rsi, ds:0[rax*4]\nmovsxd rax, r8d\nsub rax, 1\nmov [rbp+var_28], rax\nmovsxd rax, edi\nmov rcx, rax\nmov ebx, 0\nmovsxd rax, r8d\nmov rax, rax\nmov edx, 0\nmov r10, rbx\nimul r10, rax\nmov r9, rdx\nimul r9, rcx\nadd r9, r10\nmul rcx\nlea rcx, [r9+rdx]\nmov rdx, rcx\nmovsxd rax, edi\nmov rcx, rax\nmov ebx, 0\nmovsxd rax, r8d\nmov rax, rax\nmov edx, 0\nmov r10, rbx\nimul r10, rax\nmov r9, rdx\nimul r9, rcx\nadd r9, r10\nmul rcx\nlea rcx, [r9+rdx]\nmov rdx, rcx\nmovsxd rdx, edi\nmovsxd rax, r8d\nimul rax, rdx\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov ebx, 10h\nmov edx, 0\ndiv rbx\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_1260:\ncmp rsp, rdx\njz short loc_1277\nsub rsp, 1000h\nor [rsp+1050h+var_58], 0\njmp short loc_1260\nloc_1277:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_12A1\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_12A1:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_20], rax\nmov [rbp+var_3C], 0\njmp loc_13BE\nloc_12C0:\nmov edx, [rbp+var_48]\nmov eax, [rbp+var_3C]\ncmp edx, eax\ncmovle eax, edx\nmov [rbp+var_34], eax\nmov [rbp+var_38], 0\njmp loc_13AE\nloc_12DA:\ncmp [rbp+var_38], 0\njnz short loc_1307\nmov rdi, rsi\nshr rdi, 2\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_38]\nmovsxd rcx, edx\nmov edx, [rbp+var_3C]\nmovsxd rdx, edx\nimul rdx, rdi\nadd rdx, rcx\nmov dword ptr [rax+rdx*4], 1\njmp short loc_137A\nloc_1307:\nmov rdi, rsi\nshr rdi, 2\nmov eax, [rbp+var_3C]\nlea r8d, [rax-1]\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_38]\nmovsxd rcx, edx\nmovsxd rdx, r8d\nimul rdx, rdi\nadd rdx, rcx\nmov ecx, [rax+rdx*4]\nmov r8, rsi\nshr r8, 2\nmov eax, [rbp+var_3C]\nlea edx, [rax-1]\nmov eax, [rbp+var_38]\nlea edi, [rax-1]\nmov rax, [rbp+var_20]\nmovsxd rdi, edi\nmovsxd rdx, edx\nimul rdx, r8\nadd rdx, rdi\nmov eax, [rax+rdx*4]\nimul eax, [rbp+var_38]\nmov r8, rsi\nshr r8, 2\nadd ecx, eax\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_38]\nmovsxd rdi, edx\nmov edx, [rbp+var_3C]\nmovsxd rdx, edx\nimul rdx, r8\nadd rdx, rdi\nmov [rax+rdx*4], ecx\nloc_137A:\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_48]\njge short loc_13AA\nmov rdi, rsi\nshr rdi, 2\nmov eax, [rbp+var_38]\nlea edx, [rax+1]\nmov rax, [rbp+var_20]\nmovsxd rcx, edx\nmov edx, [rbp+var_3C]\nmovsxd rdx, edx\nimul rdx, rdi\nadd rdx, rcx\nmov dword ptr [rax+rdx*4], 0\nloc_13AA:\nadd [rbp+var_38], 1\nloc_13AE:\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_34]\njle loc_12DA\nadd [rbp+var_3C], 1\nloc_13BE:\nmov eax, [rbp+var_3C]\ncmp eax, [rbp+var_44]\njle loc_12C0\nshr rsi, 2\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_48]\nmovsxd rcx, edx\nmov edx, [rbp+var_44]\nmovsxd rdx, edx\nimul rdx, rsi\nadd rdx, rcx\nmov eax, [rax+rdx*4]\nmov rsp, r11\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njz short loc_13FF\ncall ___stack_chk_fail\nloc_13FF:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n int v2; // edi\n unsigned __int64 v3; // rsi\n unsigned __int64 v4; // rax\n void *v5; // rsp\n int v6; // eax\n _BYTE v8[8]; // [rsp+8h] [rbp-50h] BYREF\n int v9; // [rsp+10h] [rbp-48h]\n int v10; // [rsp+14h] [rbp-44h]\n int i; // [rsp+1Ch] [rbp-3Ch]\n int j; // [rsp+20h] [rbp-38h]\n int v13; // [rsp+24h] [rbp-34h]\n __int64 v14; // [rsp+28h] [rbp-30h]\n __int64 v15; // [rsp+30h] [rbp-28h]\n _BYTE *v16; // [rsp+38h] [rbp-20h]\n unsigned __int64 v17; // [rsp+40h] [rbp-18h]\n\n v10 = a1;\n v9 = a2;\n v17 = __readfsqword(0x28u);\n v2 = a2 + 1;\n v14 = a2 + 1 - 1LL;\n v3 = 4LL * (a2 + 1);\n v15 = v10 + 1 - 1LL;\n v4 = 16 * ((4 * v2 * (__int64)(v10 + 1) + 15) / 0x10uLL);\n while ( v8 != &v8[-(v4 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v5 = alloca(v4 & 0xFFF);\n if ( (v4 & 0xFFF) != 0 )\n *(_QWORD *)&v8[(v4 & 0xFFF) - 8] = *(_QWORD *)&v8[(v4 & 0xFFF) - 8];\n v16 = v8;\n for ( i = 0; i <= v10; ++i )\n {\n v6 = i;\n if ( v9 <= i )\n v6 = v9;\n v13 = v6;\n for ( j = 0; j <= v13; ++j )\n {\n if ( j )\n *(_DWORD *)&v16[4 * j + 4 * (v3 >> 2) * i] = j * *(_DWORD *)&v16[4 * j - 4 + 4 * (v3 >> 2) * (i - 1)]\n + *(_DWORD *)&v16[4 * j + 4 * (v3 >> 2) * (i - 1)];\n else\n *(_DWORD *)&v16[4 * (v3 >> 2) * i] = 1;\n if ( j < v9 )\n *(_DWORD *)&v16[4 * j + 4 + 4 * (v3 >> 2) * i] = 0;\n }\n }\n return *(unsigned int *)&v16[4 * v9 + 4 * (v3 >> 2) * v10];\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 48h\nmov [rbp+var_44], edi\nmov [rbp+var_48], esi\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov rax, rsp\nmov r11, rax\nmov eax, [rbp+var_48]\nlea edi, [rax+1]\nmov eax, [rbp+var_44]\nlea r8d, [rax+1]\nmovsxd rax, edi\nsub rax, 1\nmov [rbp+var_30], rax\nmovsxd rax, edi\nlea rsi, ds:0[rax*4]\nmovsxd rax, r8d\nsub rax, 1\nmov [rbp+var_28], rax\nmovsxd rax, edi\nmov rcx, rax\nmov ebx, 0\nmovsxd rax, r8d\nmov rax, rax\nmov edx, 0\nmov r10, rbx\nimul r10, rax\nmov r9, rdx\nimul r9, rcx\nadd r9, r10\nmul rcx\nlea rcx, [r9+rdx]\nmov rdx, rcx\nmovsxd rax, edi\nmov rcx, rax\nmov ebx, 0\nmovsxd rax, r8d\nmov rax, rax\nmov edx, 0\nmov r10, rbx\nimul r10, rax\nmov r9, rdx\nimul r9, rcx\nadd r9, r10\nmul rcx\nlea rcx, [r9+rdx]\nmov rdx, rcx\nmovsxd rdx, edi\nmovsxd rax, r8d\nimul rax, rdx\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov ebx, 10h\nmov edx, 0\ndiv rbx\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_1260:\ncmp rsp, rdx\njz short loc_1277\nsub rsp, 1000h\nor [rsp+1050h+var_58], 0\njmp short loc_1260\nloc_1277:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_12A1\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_12A1:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_20], rax\nmov [rbp+var_3C], 0\njmp loc_13BE\nloc_12C0:\nmov edx, [rbp+var_48]\nmov eax, [rbp+var_3C]\ncmp edx, eax\ncmovle eax, edx\nmov [rbp+var_34], eax\nmov [rbp+var_38], 0\njmp loc_13AE\nloc_12DA:\ncmp [rbp+var_38], 0\njnz short loc_1307\nmov rdi, rsi\nshr rdi, 2\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_38]\nmovsxd rcx, edx\nmov edx, [rbp+var_3C]\nmovsxd rdx, edx\nimul rdx, rdi\nadd rdx, rcx\nmov dword ptr [rax+rdx*4], 1\njmp short loc_137A\nloc_1307:\nmov rdi, rsi\nshr rdi, 2\nmov eax, [rbp+var_3C]\nlea r8d, [rax-1]\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_38]\nmovsxd rcx, edx\nmovsxd rdx, r8d\nimul rdx, rdi\nadd rdx, rcx\nmov ecx, [rax+rdx*4]\nmov r8, rsi\nshr r8, 2\nmov eax, [rbp+var_3C]\nlea edx, [rax-1]\nmov eax, [rbp+var_38]\nlea edi, [rax-1]\nmov rax, [rbp+var_20]\nmovsxd rdi, edi\nmovsxd rdx, edx\nimul rdx, r8\nadd rdx, rdi\nmov eax, [rax+rdx*4]\nimul eax, [rbp+var_38]\nmov r8, rsi\nshr r8, 2\nadd ecx, eax\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_38]\nmovsxd rdi, edx\nmov edx, [rbp+var_3C]\nmovsxd rdx, edx\nimul rdx, r8\nadd rdx, rdi\nmov [rax+rdx*4], ecx\nloc_137A:\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_48]\njge short loc_13AA\nmov rdi, rsi\nshr rdi, 2\nmov eax, [rbp+var_38]\nlea edx, [rax+1]\nmov rax, [rbp+var_20]\nmovsxd rcx, edx\nmov edx, [rbp+var_3C]\nmovsxd rdx, edx\nimul rdx, rdi\nadd rdx, rcx\nmov dword ptr [rax+rdx*4], 0\nloc_13AA:\nadd [rbp+var_38], 1\nloc_13AE:\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_34]\njle loc_12DA\nadd [rbp+var_3C], 1\nloc_13BE:\nmov eax, [rbp+var_3C]\ncmp eax, [rbp+var_44]\njle loc_12C0\nshr rsi, 2\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_48]\nmovsxd rcx, edx\nmov edx, [rbp+var_44]\nmovsxd rdx, edx\nimul rdx, rsi\nadd rdx, rcx\nmov eax, [rax+rdx*4]\nmov rsp, r11\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njz short loc_13FF\ncall ___stack_chk_fail\nloc_13FF:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1, int a2)\n{\n int v2; // edi\n unsigned __int64 v3; // rsi\n unsigned __int64 v4; // rax\n void *v5; // rsp\n int v6; // eax\n _BYTE v8[8]; // [rsp+8h] [rbp-50h] BYREF\n int v9; // [rsp+10h] [rbp-48h]\n int v10; // [rsp+14h] [rbp-44h]\n int i; // [rsp+1Ch] [rbp-3Ch]\n int j; // [rsp+20h] [rbp-38h]\n int v13; // [rsp+24h] [rbp-34h]\n __int64 v14; // [rsp+28h] [rbp-30h]\n __int64 v15; // [rsp+30h] [rbp-28h]\n _BYTE *v16; // [rsp+38h] [rbp-20h]\n unsigned __int64 v17; // [rsp+40h] [rbp-18h]\n\n v10 = a1;\n v9 = a2;\n v17 = __readfsqword(0x28u);\n v2 = a2 + 1;\n v14 = a2 + 1 - 1LL;\n v3 = 4LL * (a2 + 1);\n v15 = v10 + 1 - 1LL;\n v4 = 16 * ((4 * v2 * (__int64)(v10 + 1) + 15) / 0x10uLL);\n while ( v8 != &v8[-(v4 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v5 = alloca(v4 & 0xFFF);\n if ( (v4 & 0xFFF) != 0 )\n *(_QWORD *)&v8[(v4 & 0xFFF) - 8] = *(_QWORD *)&v8[(v4 & 0xFFF) - 8];\n v16 = v8;\n for ( i = 0; i <= v10; ++i )\n {\n v6 = i;\n if ( v9 <= i )\n v6 = v9;\n v13 = v6;\n for ( j = 0; j <= v13; ++j )\n {\n if ( j )\n *(_DWORD *)&v16[4 * j + 4 * (v3 >> 2) * i] = j * *(_DWORD *)&v16[4 * j - 4 + 4 * (v3 >> 2) * (i - 1)]\n + *(_DWORD *)&v16[4 * j + 4 * (v3 >> 2) * (i - 1)];\n else\n *(_DWORD *)&v16[4 * (v3 >> 2) * i] = 1;\n if ( j < v9 )\n *(_DWORD *)&v16[4 * j + 4 + 4 * (v3 >> 2) * i] = 0;\n }\n }\n return *(unsigned int *)&v16[4 * v9 + 4 * (v3 >> 2) * v10];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1, int a2) {\n int v2;\n unsigned long long v3;\n unsigned long long v4;\n void *v5;\n int v6;\n uint8_t v8[8];\n int v9;\n int v10;\n int i;\n int j;\n int v13;\n long long v14;\n long long v15;\n uint8_t *v16;\n unsigned long long v17;\n v10 = a1;\n v9 = a2;\n v17 = __readfsqword(40u);\n v2 = a2 + 1;\n v14 = a2 + 1 - 1LL;\n v3 = 4LL * (a2 + 1);\n v15 = v10 + 1 - 1LL;\n v4 = 16 * ((4 * v2 * (long long)(v10 + 1) + 15) / 16uLL);\n while (v8 != &v8[-(v4 & 18446744073709547520LL)])\n ;\n v5 = alloca(v4 & 4095);\n if ((v4 & 4095) != 0)\n *(uint64_t *)&v8[(v4 & 4095) - 8] = *(uint64_t *)&v8[(v4 & 4095) - 8];\n v16 = v8;\n for (i = 0; i <= v10; ++i) {\n v6 = i;\n if (v9 <= i) v6 = v9;\n v13 = v6;\n for (j = 0; j <= v13; ++j) {\n if (j)\n *(uint32_t *)&v16[4 * j + 4 * (v3 >> 2) * i] =\n j * *(uint32_t *)&v16[4 * j - 4 + 4 * (v3 >> 2) * (i - 1)] +\n *(uint32_t *)&v16[4 * j + 4 * (v3 >> 2) * (i - 1)];\n else\n *(uint32_t *)&v16[4 * (v3 >> 2) * i] = 1;\n if (j < v9) *(uint32_t *)&v16[4 * j + 4 + 4 * (v3 >> 2) * i] = 0;\n }\n }\n return *(unsigned int *)&v16[4 * v9 + 4 * (v3 >> 2) * v10];\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n int v2;\n unsigned long long v3;\n unsigned long long v4;\n void *v5;\n int v6;\n uint8_t v8[8];\n int v9;\n int v10;\n int i;\n int j;\n int v13;\n long long v14;\n long long v15;\n uint8_t *v16;\n unsigned long long v17;\n v10 = a1;\n v9 = a2;\n v17 = __readfsqword(40u);\n v2 = a2 + 1;\n v14 = a2 + 1 - 1LL;\n v3 = 4LL * (a2 + 1);\n v15 = v10 + 1 - 1LL;\n v4 = 16 * ((4 * v2 * (long long)(v10 + 1) + 15) / 16uLL);\n while (v8 != &v8[-(v4 & 18446744073709547520LL)])\n ;\n v5 = alloca(v4 & 4095);\n if ((v4 & 4095) != 0)\n *(uint64_t *)&v8[(v4 & 4095) - 8] = *(uint64_t *)&v8[(v4 & 4095) - 8];\n v16 = v8;\n for (i = 0; i <= v10; ++i) {\n v6 = i;\n if (v9 <= i) v6 = v9;\n v13 = v6;\n for (j = 0; j <= v13; ++j) {\n if (j)\n *(uint32_t *)&v16[4 * j + 4 * (v3 >> 2) * i] =\n j * *(uint32_t *)&v16[4 * j - 4 + 4 * (v3 >> 2) * (i - 1)] +\n *(uint32_t *)&v16[4 * j + 4 * (v3 >> 2) * (i - 1)];\n else\n *(uint32_t *)&v16[4 * (v3 >> 2) * i] = 1;\n if (j < v9) *(uint32_t *)&v16[4 * j + 4 + 4 * (v3 >> 2) * i] = 0;\n }\n }\n return *(unsigned int *)&v16[4 * v9 + 4 * (v3 >> 2) * v10];\n}" + }, + { + "index": 506, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n, int k) {\n int P[n + 1][k + 1];\n for (int i = 0; i <= n; i++) {\n int minValue = (i < k) ? i : k;\n for (int j = 0; j <= minValue; j++) {\n if (j == 0) {\n P[i][j] = 1;\n } else {\n P[i][j] = P[i - 1][j] + j * P[i - 1][j - 1];\n }\n if (j < k) {\n P[i][j + 1] = 0;\n }\n }\n }\n return P[n][k];\n}", + "test": "int main() {\n\n assert(func0(10, 2) == 90);\n\n assert(func0(10, 3) == 720);\n\n assert(func0(10, 1) == 10);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0x28,%rsp\nmov %edi,-0x44(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nlea 0x1(%rsi),%eax\nmovslq %eax,%rcx\nlea 0x0(,%rcx,4),%r12\nlea 0x1(%rdi),%edx\nmovslq %edx,%rax\nimul %rcx,%rax\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffffff0,%rdx\nand $0xfffffffffffff000,%rax\nmov %rsp,%rbx\nsub %rax,%rbx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 11dd \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11c6 \nmov %rdx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 11f3 \norq $0x0,-0x8(%rsp,%rax,1)\nmov %rsp,%r9\nmov %r9,-0x50(%rbp)\nmov %r9,%r13\nmov -0x44(%rbp),%eax\ntest %eax,%eax\njs 1290 \nmov %r9,%r10\nmov %r12,%r15\nshr $0x2,%r15\nmov %r9,%rdi\nsub %r12,%rdi\nlea 0x1(%rax),%r14d\nmov $0x0,%r11d\njmp 1270 \nmovl $0x1,0x0(%r13,%rbx,4)\njmp 124f \nlea 0x1(%rax),%rdx\ncmp %r8,%rax\nje 125e \nmov %rdx,%rax\nmov %eax,%ecx\ntest %eax,%eax\nje 1224 \nmov %eax,%edx\nimul -0x4(%rdi,%rax,4),%edx\nadd (%rdi,%rax,4),%edx\nmov %edx,(%r9,%rax,4)\ncmp %esi,%ecx\njge 122f \nmovl $0x0,0x4(%r10,%rax,4)\njmp 122f \nadd $0x1,%r11d\nadd %r12,%r10\nadd %r12,%rdi\nadd %r12,%r9\ncmp %r14d,%r11d\nje 1290 \ncmp %r11d,%esi\nmov %r11d,%r8d\ncmovle %esi,%r8d\ntest %r8d,%r8d\njs 125e \nmov %r8d,%r8d\nmov $0x0,%eax\nmovslq %r11d,%rbx\nimul %r15,%rbx\njmp 123b \nmovslq %esi,%rsi\nmovslq -0x44(%rbp),%rax\nshr $0x2,%r12\nimul %rax,%r12\nlea (%rsi,%r12,1),%rax\nmov -0x50(%rbp),%rbx\nmov (%rbx,%rax,4),%eax\nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\njne 12c8 \nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 28h\nmov ebx, edi\nmov [rbp+var_44], edi\nmov edi, esi\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nlea edx, [rsi+1]\nmovsxd rdx, edx\nlea r12, ds:0[rdx*4]\nlea eax, [rbx+1]\ncdqe\nimul rax, rdx\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11C6:\ncmp rsp, rdx\njz short loc_11DD\nsub rsp, 1000h\nor [rsp+1050h+var_58], 0\njmp short loc_11C6\nloc_11DD:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11F3\nor [rsp+rax+50h+var_58], 0\nloc_11F3:\nmov r13, rsp\nmov eax, [rbp+var_44]\ntest eax, eax\njs loc_1288\nmov r10, r13\nmov r15, r12\nshr r15, 2\nmov rsi, r13\nsub rsi, r12\nlea r14d, [rax+1]\nmov r9, r13\nmov r11d, 0\njmp short loc_1269\nloc_1220:\nmov dword ptr [r13+rbx*4+0], 1\njmp short loc_1248\nloc_122B:\nadd rax, 1\ncmp rax, r8\njz short loc_1257\nloc_1234:\nmov ecx, eax\ntest eax, eax\njz short loc_1220\nmov edx, eax\nimul edx, [rsi+rax*4-4]\nadd edx, [rsi+rax*4]\nmov [r9+rax*4], edx\nloc_1248:\ncmp edi, ecx\njle short loc_122B\nmov dword ptr [r10+rax*4+4], 0\njmp short loc_122B\nloc_1257:\nadd r11d, 1\nadd r10, r12\nadd rsi, r12\nadd r9, r12\ncmp r11d, r14d\njz short loc_1288\nloc_1269:\ncmp edi, r11d\nmov eax, r11d\ncmovle eax, edi\ntest eax, eax\njs short loc_1257\nlea r8d, [rax+1]\nmov eax, 0\nmovsxd rbx, r11d\nimul rbx, r15\njmp short loc_1234\nloc_1288:\nmovsxd rax, edi\nmovsxd rdx, [rbp+var_44]\nshr r12, 2\nimul rdx, r12\nadd rax, rdx\nmov eax, [r13+rax*4+0]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_12BD\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_12BD:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n __int64 v4; // rdx\n unsigned __int64 v5; // r12\n _DWORD *v6; // rdx\n signed __int64 v7; // rax\n void *v8; // rsp\n _DWORD *v9; // r10\n _DWORD *v10; // rsi\n int v11; // r14d\n _DWORD *v12; // r9\n int v13; // r11d\n __int64 v14; // rax\n int v15; // eax\n __int64 v16; // r8\n _DWORD v19[3]; // [rsp+8h] [rbp-50h] BYREF\n int v20; // [rsp+14h] [rbp-44h]\n unsigned __int64 v21; // [rsp+20h] [rbp-38h]\n\n v20 = a1;\n v21 = __readfsqword(0x28u);\n v4 = a2 + 1;\n v5 = 4 * v4;\n v6 = (_DWORD *)((char *)v19 - ((4 * v4 * (a1 + 1) + 15) & 0xFFFFFFFFFFFFF000LL));\n while ( v19 != v6 )\n ;\n v7 = (4 * ((_WORD)a2 + 1) * ((_WORD)a1 + 1) + 15) & 0xFF0;\n v8 = alloca(v7);\n if ( ((4 * ((_WORD)a2 + 1) * ((_WORD)a1 + 1) + 15) & 0xFF0) != 0 )\n *(_QWORD *)((char *)&v19[-2] + v7) = *(_QWORD *)((char *)&v19[-2] + v7);\n if ( v20 >= 0 )\n {\n v9 = v19;\n v10 = &v19[v5 / 0xFFFFFFFFFFFFFFFCLL];\n v11 = v20 + 1;\n v12 = v19;\n v13 = 0;\n do\n {\n v15 = v13;\n if ( a2 <= v13 )\n v15 = a2;\n if ( v15 >= 0 )\n {\n v16 = (unsigned int)(v15 + 1);\n v14 = 0LL;\n do\n {\n if ( (_DWORD)v14 )\n v12[v14] = v10[v14] + v10[v14 - 1] * v14;\n else\n v19[(v5 >> 2) * v13] = 1;\n if ( a2 > (int)v14 )\n v9[v14 + 1] = 0;\n ++v14;\n }\n while ( v14 != v16 );\n }\n ++v13;\n v9 = (_DWORD *)((char *)v9 + v5);\n v10 = (_DWORD *)((char *)v10 + v5);\n v12 = (_DWORD *)((char *)v12 + v5);\n }\n while ( v13 != v11 );\n }\n return (unsigned int)v19[(v5 >> 2) * v20 + a2];\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 28h\nmov ebx, edi\nmov [rbp+var_44], edi\nmov edi, esi\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nlea edx, [rsi+1]\nmovsxd rdx, edx\nlea r12, ds:0[rdx*4]\nlea eax, [rbx+1]\ncdqe\nimul rax, rdx\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11C6:\ncmp rsp, rdx\njz short loc_11DD\nsub rsp, 1000h\nor [rsp+1050h+var_58], 0\njmp short loc_11C6\nloc_11DD:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11F3\nor [rsp+rax+50h+var_58], 0\nloc_11F3:\nmov r13, rsp\nmov eax, [rbp+var_44]\ntest eax, eax\njs loc_1288\nmov r10, r13\nmov r15, r12\nshr r15, 2\nmov rsi, r13\nsub rsi, r12\nlea r14d, [rax+1]\nmov r9, r13\nmov r11d, 0\njmp short loc_1269\nloc_1220:\nmov dword ptr [r13+rbx*4+0], 1\njmp short loc_1248\nloc_122B:\nadd rax, 1\ncmp rax, r8\njz short loc_1257\nloc_1234:\nmov ecx, eax\ntest eax, eax\njz short loc_1220\nmov edx, eax\nimul edx, [rsi+rax*4-4]\nadd edx, [rsi+rax*4]\nmov [r9+rax*4], edx\nloc_1248:\ncmp edi, ecx\njle short loc_122B\nmov dword ptr [r10+rax*4+4], 0\njmp short loc_122B\nloc_1257:\nadd r11d, 1\nadd r10, r12\nadd rsi, r12\nadd r9, r12\ncmp r11d, r14d\njz short loc_1288\nloc_1269:\ncmp edi, r11d\nmov eax, r11d\ncmovle eax, edi\ntest eax, eax\njs short loc_1257\nlea r8d, [rax+1]\nmov eax, 0\nmovsxd rbx, r11d\nimul rbx, r15\njmp short loc_1234\nloc_1288:\nmovsxd rax, edi\nmovsxd rdx, [rbp+var_44]\nshr r12, 2\nimul rdx, r12\nadd rax, rdx\nmov eax, [r13+rax*4+0]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_12BD\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_12BD:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1, int a2)\n{\n __int64 v4; // rdx\n unsigned __int64 v5; // r12\n _DWORD *v6; // rdx\n signed __int64 v7; // rax\n void *v8; // rsp\n _DWORD *v9; // r10\n _DWORD *v10; // rsi\n int v11; // r14d\n _DWORD *v12; // r9\n int v13; // r11d\n __int64 v14; // rax\n int v15; // eax\n __int64 v16; // r8\n _DWORD v19[3]; // [rsp+8h] [rbp-50h] BYREF\n int v20; // [rsp+14h] [rbp-44h]\n unsigned __int64 v21; // [rsp+20h] [rbp-38h]\n\n v20 = a1;\n v21 = __readfsqword(0x28u);\n v4 = a2 + 1;\n v5 = 4 * v4;\n v6 = (_DWORD *)((char *)v19 - ((4 * v4 * (a1 + 1) + 15) & 0xFFFFFFFFFFFFF000LL));\n while ( v19 != v6 )\n ;\n v7 = (4 * ((_WORD)a2 + 1) * ((_WORD)a1 + 1) + 15) & 0xFF0;\n v8 = alloca(v7);\n if ( ((4 * ((_WORD)a2 + 1) * ((_WORD)a1 + 1) + 15) & 0xFF0) != 0 )\n *(_QWORD *)((char *)&v19[-2] + v7) = *(_QWORD *)((char *)&v19[-2] + v7);\n if ( v20 >= 0 )\n {\n v9 = v19;\n v10 = &v19[v5 / 0xFFFFFFFFFFFFFFFCLL];\n v11 = v20 + 1;\n v12 = v19;\n v13 = 0;\n do\n {\n v15 = v13;\n if ( a2 <= v13 )\n v15 = a2;\n if ( v15 >= 0 )\n {\n v16 = (unsigned int)(v15 + 1);\n v14 = 0LL;\n do\n {\n if ( (_DWORD)v14 )\n v12[v14] = v10[v14] + v10[v14 - 1] * v14;\n else\n v19[(v5 >> 2) * v13] = 1;\n if ( a2 > (int)v14 )\n v9[v14 + 1] = 0;\n ++v14;\n }\n while ( v14 != v16 );\n }\n ++v13;\n v9 = (_DWORD *)((char *)v9 + v5);\n v10 = (_DWORD *)((char *)v10 + v5);\n v12 = (_DWORD *)((char *)v12 + v5);\n }\n while ( v13 != v11 );\n }\n return (unsigned int)v19[(v5 >> 2) * v20 + a2];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1, int a2) {\n long long v4;\n unsigned long long v5;\n uint32_t *v6;\n signed long long v7;\n void *v8;\n uint32_t *v9;\n uint32_t *v10;\n int v11;\n uint32_t *v12;\n int v13;\n long long v14;\n int v15;\n long long v16;\n uint32_t v19[3];\n int v20;\n unsigned long long v21;\n v20 = a1;\n v21 = __readfsqword(40u);\n v4 = a2 + 1;\n v5 = 4 * v4;\n v6 = (uint32_t *)((char *)v19 -\n ((4 * v4 * (a1 + 1) + 15) & 18446744073709547520LL));\n while (v19 != v6)\n ;\n v7 = (4 * ((unsigned short)a2 + 1) * ((unsigned short)a1 + 1) + 15) & 4080;\n v8 = alloca(v7);\n if (((4 * ((unsigned short)a2 + 1) * ((unsigned short)a1 + 1) + 15) & 4080) !=\n 0)\n *(uint64_t *)((char *)&v19[-2] + v7) = *(uint64_t *)((char *)&v19[-2] + v7);\n if (v20 >= 0) {\n v9 = v19;\n v10 = &v19[v5 / 18446744073709551612LL];\n v11 = v20 + 1;\n v12 = v19;\n v13 = 0;\n do {\n v15 = v13;\n if (a2 <= v13) v15 = a2;\n if (v15 >= 0) {\n v16 = (unsigned int)(v15 + 1);\n v14 = 0LL;\n do {\n if ((uint32_t)v14)\n v12[v14] = v10[v14] + v10[v14 - 1] * v14;\n else\n v19[(v5 >> 2) * v13] = 1;\n if (a2 > (int)v14) v9[v14 + 1] = 0;\n ++v14;\n } while (v14 != v16);\n }\n ++v13;\n v9 = (uint32_t *)((char *)v9 + v5);\n v10 = (uint32_t *)((char *)v10 + v5);\n v12 = (uint32_t *)((char *)v12 + v5);\n } while (v13 != v11);\n }\n return (unsigned int)v19[(v5 >> 2) * v20 + a2];\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n long long v4;\n unsigned long long v5;\n uint32_t *v6;\n signed long long v7;\n void *v8;\n uint32_t *v9;\n uint32_t *v10;\n int v11;\n uint32_t *v12;\n int v13;\n long long v14;\n int v15;\n long long v16;\n uint32_t v19[3];\n int v20;\n unsigned long long v21;\n v20 = a1;\n v21 = __readfsqword(40u);\n v4 = a2 + 1;\n v5 = 4 * v4;\n v6 = (uint32_t *)((char *)v19 -\n ((4 * v4 * (a1 + 1) + 15) & 18446744073709547520LL));\n while (v19 != v6)\n ;\n v7 = (4 * ((unsigned short)a2 + 1) * ((unsigned short)a1 + 1) + 15) & 4080;\n v8 = alloca(v7);\n if (((4 * ((unsigned short)a2 + 1) * ((unsigned short)a1 + 1) + 15) & 4080) !=\n 0)\n *(uint64_t *)((char *)&v19[-2] + v7) = *(uint64_t *)((char *)&v19[-2] + v7);\n if (v20 >= 0) {\n v9 = v19;\n v10 = &v19[v5 / 18446744073709551612LL];\n v11 = v20 + 1;\n v12 = v19;\n v13 = 0;\n do {\n v15 = v13;\n if (a2 <= v13) v15 = a2;\n if (v15 >= 0) {\n v16 = (unsigned int)(v15 + 1);\n v14 = 0LL;\n do {\n if ((uint32_t)v14)\n v12[v14] = v10[v14] + v10[v14 - 1] * v14;\n else\n v19[(v5 >> 2) * v13] = 1;\n if (a2 > (int)v14) v9[v14 + 1] = 0;\n ++v14;\n } while (v14 != v16);\n }\n ++v13;\n v9 = (uint32_t *)((char *)v9 + v5);\n v10 = (uint32_t *)((char *)v10 + v5);\n v12 = (uint32_t *)((char *)v12 + v5);\n } while (v13 != v11);\n }\n return (unsigned int)v19[(v5 >> 2) * v20 + a2];\n}" + }, + { + "index": 506, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n, int k) {\n int P[n + 1][k + 1];\n for (int i = 0; i <= n; i++) {\n int minValue = (i < k) ? i : k;\n for (int j = 0; j <= minValue; j++) {\n if (j == 0) {\n P[i][j] = 1;\n } else {\n P[i][j] = P[i - 1][j] + j * P[i - 1][j - 1];\n }\n if (j < k) {\n P[i][j + 1] = 0;\n }\n }\n }\n return P[n][k];\n}", + "test": "int main() {\n\n assert(func0(10, 2) == 90);\n\n assert(func0(10, 3) == 720);\n\n assert(func0(10, 1) == 10);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\nmov %edi,%r14d\npush %r13\nlea 0x1(%rdi),%r13d\npush %r12\nmovslq %r13d,%rdx\npush %rbx\nsub $0x18,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nlea 0x1(%rsi),%eax\nmov %rsp,%rbx\ncltq\nlea 0x0(,%rax,4),%r12\nimul %rdx,%rax\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rbx\nand $0xfffffffffffffff0,%rdx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 1297 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 1282 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 136e \nmov %r12,%r15\nmov %rsp,%rbx\nshr $0x2,%r15\ntest %r14d,%r14d\njs 133f \nmov %r15,%rax\nmov %rbx,%r9\nxor %r11d,%r11d\nneg %rax\nlea (%rbx,%rax,4),%r8\nnopl 0x0(%rax)\ncmp %r11d,%esi\nmov %r11d,%edx\ncmovle %esi,%edx\nxor %eax,%eax\nmovslq %edx,%r10\ntest %edx,%edx\njs 1330 \nmovslq %r11d,%rdi\nimul %r15,%rdi\njmp 1319 \nnopl 0x0(%rax,%rax,1)\nmov -0x4(%r8,%rax,4),%edx\nimul %eax,%edx\nadd (%r8,%rax,4),%edx\nmov %edx,(%r9,%rax,4)\ncmp %ecx,%esi\njle 130d \nmovl $0x0,0x4(%r9,%rax,4)\nlea 0x1(%rax),%rdx\ncmp %r10,%rax\nje 1330 \nmov %rdx,%rax\nmov %eax,%ecx\ntest %rax,%rax\njne 12f0 \nmovl $0x1,(%rbx,%rdi,4)\njmp 1300 \nnopl 0x0(%rax)\nadd $0x1,%r11d\nadd %r12,%r9\nadd %r12,%r8\ncmp %r13d,%r11d\njne 12d0 \nmovslq %r14d,%rax\nmovslq %esi,%rsi\nimul %rax,%r15\nlea (%rsi,%r15,1),%rax\nmov (%rbx,%rax,4),%eax\nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\njne 1379 \nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 12a9 \ncallq 1060 <__stack_chk_fail@plt>\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\nlea edx, [rsi+1]\nmov r8d, esi\nmovsxd rdx, edx\nmov rbp, rsp\npush r14\npush r13\nmovsxd r13, edi\npush r12\nlea r12, ds:0[rdx*4]\npush rbx\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nlea eax, [r13+1]\nmov rcx, rsp\ncdqe\nimul rax, rdx\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_1295\nloc_1280:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rcx\njnz short loc_1280\nloc_1295:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1369\nloc_12A7:\nmov r14, r12\nmov rbx, rsp\nshr r14, 2\ntest r13d, r13d\njs loc_1340\nmov rax, r14\nmov rdi, rbx\nxor r10d, r10d\nneg rax\nlea rsi, [rbx+rax*4]\nnop word ptr [rax+rax+00h]\nloc_12D0:\ncmp r8d, r10d\nmov edx, r10d\ncmovle edx, r8d\nxor eax, eax\nlea r9d, [rdx+1]\nmovsxd r9, r9d\ntest edx, edx\njs short loc_1328\nmovsxd r11, r10d\nimul r11, r14\njmp short loc_1313\nloc_12F0:\nmov edx, [rsi+rax*4-4]\nimul edx, eax\nadd edx, [rsi+rax*4]\nmov [rdi+rax*4], edx\nloc_12FD:\ncmp ecx, r8d\njge short loc_130A\nmov dword ptr [rdi+rax*4+4], 0\nloc_130A:\nadd rax, 1\ncmp rax, r9\njz short loc_1328\nloc_1313:\nmov ecx, eax\ntest rax, rax\njnz short loc_12F0\nmov dword ptr [rbx+r11*4], 1\njmp short loc_12FD\nloc_1328:\nlea eax, [r10+1]\nadd rdi, r12\nadd rsi, r12\ncmp r13d, r10d\njz short loc_1340\nmov r10d, eax\njmp short loc_12D0\nloc_1340:\nimul r13, r14\nmovsxd rax, r8d\nadd rax, r13\nmov eax, [rbx+rax*4]\nmov rdx, [rbp+var_28]\nsub rdx, fs:28h\njnz short loc_1374\nlea rsp, [rbp-20h]\npop rbx\npop r12\npop r13\npop r14\npop rbp\nretn\nloc_1369:\nor [rsp+rdx+1030h+var_1038], 0\njmp loc_12A7\nloc_1374:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n __int64 v3; // rdx\n __int64 v4; // r13\n unsigned __int64 v5; // r12\n __int64 v6; // rdx\n _DWORD *v7; // rcx\n __int16 v8; // dx\n signed __int64 v9; // rdx\n void *v10; // rsp\n unsigned __int64 v11; // r14\n _DWORD *v12; // rdi\n int v13; // r10d\n _DWORD *v14; // rsi\n int v15; // edx\n __int64 v16; // rax\n _DWORD v19[1022]; // [rsp+8h] [rbp-1030h] BYREF\n _QWORD v20[6]; // [rsp+1008h] [rbp-30h] BYREF\n\n v3 = a2 + 1;\n v4 = a1;\n v5 = 4 * v3;\n v20[1] = __readfsqword(0x28u);\n v6 = 4 * v3 * (a1 + 1) + 15;\n v7 = (_DWORD *)((char *)v20 - (v6 & 0xFFFFFFFFFFFFF000LL));\n v8 = v6 & 0xFFF0;\n if ( v20 != (_QWORD *)v7 )\n {\n while ( v19 != v7 )\n ;\n }\n v9 = v8 & 0xFFF;\n v10 = alloca(v9);\n if ( v9 )\n *(_QWORD *)((char *)&v19[-2] + v9) = *(_QWORD *)((char *)&v19[-2] + v9);\n v11 = v5 >> 2;\n if ( a1 >= 0 )\n {\n v12 = v19;\n v13 = 0;\n v14 = &v19[-v11];\n while ( 1 )\n {\n v15 = v13;\n if ( a2 <= v13 )\n v15 = a2;\n v16 = 0LL;\n if ( v15 >= 0 )\n {\n do\n {\n if ( v16 )\n v12[v16] = v14[v16] + v16 * v14[v16 - 1];\n else\n v19[v11 * v13] = 1;\n if ( (int)v16 < a2 )\n v12[v16 + 1] = 0;\n ++v16;\n }\n while ( v16 != v15 + 1 );\n }\n v12 = (_DWORD *)((char *)v12 + v5);\n v14 = (_DWORD *)((char *)v14 + v5);\n if ( (_DWORD)v4 == v13 )\n break;\n ++v13;\n }\n }\n return (unsigned int)v19[v11 * v4 + a2];\n}", + "ida_strip_asm": "sub_1220:\nendbr64\npush rbp\nlea edx, [rsi+1]\nmov r8d, esi\nmovsxd rdx, edx\nmov rbp, rsp\npush r14\npush r13\nmovsxd r13, edi\npush r12\nlea r12, ds:0[rdx*4]\npush rbx\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nlea eax, [r13+1]\nmov rcx, rsp\ncdqe\nimul rax, rdx\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_1295\nloc_1280:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rcx\njnz short loc_1280\nloc_1295:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1369\nloc_12A7:\nmov r14, r12\nmov rbx, rsp\nshr r14, 2\ntest r13d, r13d\njs loc_1340\nmov rax, r14\nmov rdi, rbx\nxor r10d, r10d\nneg rax\nlea rsi, [rbx+rax*4]\nnop word ptr [rax+rax+00h]\nloc_12D0:\ncmp r8d, r10d\nmov edx, r10d\ncmovle edx, r8d\nxor eax, eax\nlea r9d, [rdx+1]\nmovsxd r9, r9d\ntest edx, edx\njs short loc_1328\nmovsxd r11, r10d\nimul r11, r14\njmp short loc_1313\nloc_12F0:\nmov edx, [rsi+rax*4-4]\nimul edx, eax\nadd edx, [rsi+rax*4]\nmov [rdi+rax*4], edx\nloc_12FD:\ncmp ecx, r8d\njge short loc_130A\nmov dword ptr [rdi+rax*4+4], 0\nloc_130A:\nadd rax, 1\ncmp rax, r9\njz short loc_1328\nloc_1313:\nmov ecx, eax\ntest rax, rax\njnz short loc_12F0\nmov dword ptr [rbx+r11*4], 1\njmp short loc_12FD\nloc_1328:\nlea eax, [r10+1]\nadd rdi, r12\nadd rsi, r12\ncmp r13d, r10d\njz short loc_1340\nmov r10d, eax\njmp short loc_12D0\nloc_1340:\nimul r13, r14\nmovsxd rax, r8d\nadd rax, r13\nmov eax, [rbx+rax*4]\nmov rdx, [rbp+var_28]\nsub rdx, fs:28h\njnz short loc_1374\nlea rsp, [rbp-20h]\npop rbx\npop r12\npop r13\npop r14\npop rbp\nretn\nloc_1369:\nor [rsp+rdx+1030h+var_1038], 0\njmp loc_12A7\nloc_1374:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1220(int a1, int a2)\n{\n __int64 v3; // rdx\n __int64 v4; // r13\n unsigned __int64 v5; // r12\n __int64 v6; // rdx\n _DWORD *v7; // rcx\n __int16 v8; // dx\n signed __int64 v9; // rdx\n void *v10; // rsp\n unsigned __int64 v11; // r14\n _DWORD *v12; // rdi\n int v13; // r10d\n _DWORD *v14; // rsi\n int v15; // edx\n __int64 v16; // rax\n _DWORD v19[1022]; // [rsp+8h] [rbp-1030h] BYREF\n _QWORD v20[6]; // [rsp+1008h] [rbp-30h] BYREF\n\n v3 = a2 + 1;\n v4 = a1;\n v5 = 4 * v3;\n v20[1] = __readfsqword(0x28u);\n v6 = 4 * v3 * (a1 + 1) + 15;\n v7 = (_DWORD *)((char *)v20 - (v6 & 0xFFFFFFFFFFFFF000LL));\n v8 = v6 & 0xFFF0;\n if ( v20 != (_QWORD *)v7 )\n {\n while ( v19 != v7 )\n ;\n }\n v9 = v8 & 0xFFF;\n v10 = alloca(v9);\n if ( v9 )\n *(_QWORD *)((char *)&v19[-2] + v9) = *(_QWORD *)((char *)&v19[-2] + v9);\n v11 = v5 >> 2;\n if ( a1 >= 0 )\n {\n v12 = v19;\n v13 = 0;\n v14 = &v19[-v11];\n while ( 1 )\n {\n v15 = v13;\n if ( a2 <= v13 )\n v15 = a2;\n v16 = 0LL;\n if ( v15 >= 0 )\n {\n do\n {\n if ( v16 )\n v12[v16] = v14[v16] + v16 * v14[v16 - 1];\n else\n v19[v11 * v13] = 1;\n if ( (int)v16 < a2 )\n v12[v16 + 1] = 0;\n ++v16;\n }\n while ( v16 != v15 + 1 );\n }\n v12 = (_DWORD *)((char *)v12 + v5);\n v14 = (_DWORD *)((char *)v14 + v5);\n if ( (_DWORD)v4 == v13 )\n break;\n ++v13;\n }\n }\n return (unsigned int)v19[v11 * v4 + a2];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1220(int a1, int a2) {\n long long v3;\n long long v4;\n unsigned long long v5;\n long long v6;\n uint32_t *v7;\n short v8;\n signed long long v9;\n void *v10;\n unsigned long long v11;\n uint32_t *v12;\n int v13;\n uint32_t *v14;\n int v15;\n long long v16;\n uint32_t v19[1022];\n uint64_t v20[6];\n v3 = a2 + 1;\n v4 = a1;\n v5 = 4 * v3;\n v20[1] = __readfsqword(40u);\n v6 = 4 * v3 * (a1 + 1) + 15;\n v7 = (uint32_t *)((char *)v20 - (v6 & 18446744073709547520LL));\n v8 = v6 & 65520;\n if (v20 != (uint64_t *)v7) {\n while (v19 != v7)\n ;\n }\n v9 = v8 & 4095;\n v10 = alloca(v9);\n if (v9)\n *(uint64_t *)((char *)&v19[-2] + v9) = *(uint64_t *)((char *)&v19[-2] + v9);\n v11 = v5 >> 2;\n if (a1 >= 0) {\n v12 = v19;\n v13 = 0;\n v14 = &v19[-v11];\n while (1) {\n v15 = v13;\n if (a2 <= v13) v15 = a2;\n v16 = 0LL;\n if (v15 >= 0) {\n do {\n if (v16)\n v12[v16] = v14[v16] + v16 * v14[v16 - 1];\n else\n v19[v11 * v13] = 1;\n if ((int)v16 < a2) v12[v16 + 1] = 0;\n ++v16;\n } while (v16 != v15 + 1);\n }\n v12 = (uint32_t *)((char *)v12 + v5);\n v14 = (uint32_t *)((char *)v14 + v5);\n if ((uint32_t)v4 == v13) break;\n ++v13;\n }\n }\n return (unsigned int)v19[v11 * v4 + a2];\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n long long v3;\n long long v4;\n unsigned long long v5;\n long long v6;\n uint32_t *v7;\n short v8;\n signed long long v9;\n void *v10;\n unsigned long long v11;\n uint32_t *v12;\n int v13;\n uint32_t *v14;\n int v15;\n long long v16;\n uint32_t v19[1022];\n uint64_t v20[6];\n v3 = a2 + 1;\n v4 = a1;\n v5 = 4 * v3;\n v20[1] = __readfsqword(40u);\n v6 = 4 * v3 * (a1 + 1) + 15;\n v7 = (uint32_t *)((char *)v20 - (v6 & 18446744073709547520LL));\n v8 = v6 & 65520;\n if (v20 != (uint64_t *)v7) {\n while (v19 != v7)\n ;\n }\n v9 = v8 & 4095;\n v10 = alloca(v9);\n if (v9)\n *(uint64_t *)((char *)&v19[-2] + v9) = *(uint64_t *)((char *)&v19[-2] + v9);\n v11 = v5 >> 2;\n if (a1 >= 0) {\n v12 = v19;\n v13 = 0;\n v14 = &v19[-v11];\n while (1) {\n v15 = v13;\n if (a2 <= v13) v15 = a2;\n v16 = 0LL;\n if (v15 >= 0) {\n do {\n if (v16)\n v12[v16] = v14[v16] + v16 * v14[v16 - 1];\n else\n v19[v11 * v13] = 1;\n if ((int)v16 < a2) v12[v16 + 1] = 0;\n ++v16;\n } while (v16 != v15 + 1);\n }\n v12 = (uint32_t *)((char *)v12 + v5);\n v14 = (uint32_t *)((char *)v14 + v5);\n if ((uint32_t)v4 == v13) break;\n ++v13;\n }\n }\n return (unsigned int)v19[v11 * v4 + a2];\n}" + }, + { + "index": 506, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n, int k) {\n int P[n + 1][k + 1];\n for (int i = 0; i <= n; i++) {\n int minValue = (i < k) ? i : k;\n for (int j = 0; j <= minValue; j++) {\n if (j == 0) {\n P[i][j] = 1;\n } else {\n P[i][j] = P[i - 1][j] + j * P[i - 1][j - 1];\n }\n if (j < k) {\n P[i][j + 1] = 0;\n }\n }\n }\n return P[n][k];\n}", + "test": "int main() {\n\n assert(func0(10, 2) == 90);\n\n assert(func0(10, 3) == 720);\n\n assert(func0(10, 1) == 10);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nlea 0x1(%rdi),%edx\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\nmov %esi,%r13d\npush %r12\npush %rbx\nsub $0x38,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nlea 0x1(%rsi),%eax\nmov %rsp,%rbx\nmovslq %eax,%rcx\nlea 0x0(,%rcx,4),%rax\nmov %rax,-0x58(%rbp)\nmovslq %edx,%rax\nimul %rcx,%rax\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rbx\nand $0xfffffffffffffff0,%rdx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 129b \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 1286 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 141f \nmov -0x58(%rbp),%rax\nmov %rsp,%r10\nshr $0x2,%rax\nmov %rax,-0x60(%rbp)\ntest %edi,%edi\njs 142a \nmov %rax,%r14\nneg %rax\nmov %r10,%rsi\nmov $0xffffffffffffffff,%r15\nlea (%r10,%rax,4),%rbx\nmovslq %edi,%rax\nxor %r12d,%r12d\nmov %rax,-0x50(%rbp)\nnopw 0x0(%rax,%rax,1)\ncmp %r12d,%r13d\nmov %r12d,%r8d\nmov %r12d,-0x44(%rbp)\ncmovle %r13d,%r8d\ntest %r8d,%r8d\njs 13c8 \ntest %r13d,%r13d\njle 1418 \nlea 0x1(%r8),%r9d\nmovslq -0x44(%rbp),%r11\nmov %r15,%rdi\nmov %rsi,%rdx\ncmp %r13d,%r9d\ncmovg %r13d,%r9d\nimul %r14,%r11\nsub %r12,%rdi\nxor %eax,%eax\nimul %r14,%rdi\nnopw 0x0(%rax,%rax,1)\ntest %eax,%eax\njne 1351 \nmovl $0x1,(%r10,%r11,4)\nadd $0x4,%rdx\nmov $0x1,%eax\nmovl $0x0,(%rdx)\ncmp $0x1,%r9d\nje 1370 \nmov -0x4(%rdx,%rdi,4),%ecx\nimul %eax,%ecx\nadd $0x1,%eax\nadd (%rdx,%rdi,4),%ecx\nmovl $0x0,0x4(%rdx)\nmov %ecx,(%rdx)\nadd $0x4,%rdx\ncmp %r9d,%eax\njl 1330 \ncmp %eax,%r8d\njl 13c8 \nmovslq -0x44(%rbp),%rdi\nmovslq %r15d,%rcx\ncltq\nimul %r14,%rcx\nimul %r14,%rdi\njmp 13b3 \nnopl 0x0(%rax,%rax,1)\nlea -0x1(%rax),%edx\nmovslq %edx,%rdx\nadd %rcx,%rdx\nmov (%r10,%rdx,4),%r11d\nmov (%rbx,%rax,4),%edx\nimul %eax,%r11d\nadd %r11d,%edx\nmov %edx,(%rsi,%rax,4)\nadd $0x1,%rax\ncmp %eax,%r8d\njl 13c8 \ntest %eax,%eax\njne 1390 \nadd $0x1,%rax\nmovl $0x1,(%r10,%rdi,4)\ncmp %eax,%r8d\njge 13b3 \nmov -0x58(%rbp),%rax\nadd $0x1,%r12\nadd $0x1,%r15\nadd %rax,%rsi\nadd %rax,%rbx\ncmp -0x50(%rbp),%r15\njne 12e8 \nmov -0x50(%rbp),%rdx\nimul -0x60(%rbp),%rdx\nmovslq %r13d,%rax\nadd %rdx,%rax\nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\nmov (%r10,%rax,4),%eax\njne 1433 \nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\nnopl (%rax)\nxor %eax,%eax\njmpq 1375 \norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 12ad \nmovslq %edi,%rax\nmov %rax,-0x50(%rbp)\njmp 13e4 \ncallq 1060 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nlea ecx, [rsi+1]\nmov r10d, esi\nmov edx, edi\nmovsxd rcx, ecx\nmov rbp, rsp\npush r15\nlea r15, ds:0[rcx*4]\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 28h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nlea eax, [rdi+1]\nmov rsi, rsp\ncdqe\nimul rax, rcx\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rsi, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rsi\njz short loc_1295\nloc_1280:\nsub rsp, 1000h\nor [rsp+1050h+var_58], 0\ncmp rsp, rsi\njnz short loc_1280\nloc_1295:\nand ecx, 0FFFh\nsub rsp, rcx\ntest rcx, rcx\njnz loc_1422\nloc_12A7:\nmov rsi, r15\nmov r9, rsp\nshr rsi, 2\ntest edx, edx\njs loc_142D\nmov rax, rsi\nmov r8, r9\nmov r14, 0FFFFFFFFFFFFFFFFh\nxor r13d, r13d\nneg rax\nlea rbx, [r9+rax*4]\nmovsxd rax, edx\nmov [rbp+var_50], rax\nnop word ptr [rax+rax+00000000h]\nloc_12E0:\nmov ecx, r13d\ncmp r10d, r13d\nmovsxd rdi, r13d\ncmovle ecx, r10d\ntest ecx, ecx\njs loc_137F\ntest r10d, r10d\njle loc_13D0\nlea r12d, [rcx+1]\nmovsxd rax, edi\ncmp r12d, r10d\ncmovg r12d, r10d\nimul rax, rsi\nmov dword ptr [r9+rax*4], 1\nmov eax, 1\nmov dword ptr [r8+4], 0\ncmp r12d, 1\njnz loc_13E0\nnop\nloc_1330:\ncmp ecx, eax\njl short loc_137F\nloc_1334:\nmovsxd r11, r14d\nimul rdi, rsi\ncdqe\nimul r11, rsi\njmp short loc_136B\nloc_1348:\nlea edx, [rax-1]\nmovsxd rdx, edx\nadd rdx, r11\nmov r12d, [r9+rdx*4]\nmov edx, [rbx+rax*4]\nimul r12d, eax\nadd edx, r12d\nmov [r8+rax*4], edx\nadd rax, 1\ncmp ecx, eax\njl short loc_137F\nloc_136B:\ntest eax, eax\njnz short loc_1348\nadd rax, 1\nmov dword ptr [r9+rdi*4], 1\ncmp ecx, eax\njge short loc_136B\nloc_137F:\nmov rax, [rbp+var_50]\nadd r14, 1\nadd r13, 1\nadd rbx, r15\nadd r8, r15\ncmp r14, rax\njnz loc_12E0\nloc_139A:\nmov rdx, rax\nmovsxd rax, r10d\nimul rdx, rsi\nadd rax, rdx\nmov eax, [r9+rax*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_1439\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_13D0:\nxor eax, eax\njmp loc_1334\nloc_13E0:\nmov r11, r14\nmov [rbp+var_44], ecx\nlea rdx, [r8+4]\nmov ecx, r12d\nsub r11, r13\nimul r11, rsi\nnop dword ptr [rax+00h]\nloc_13F8:\nmov r12d, [rdx+r11*4-4]\nimul r12d, eax\nadd eax, 1\nadd r12d, [rdx+r11*4]\nadd rdx, 4\nmov [rdx-4], r12d\nmov dword ptr [rdx], 0\ncmp eax, ecx\njl short loc_13F8\nmov ecx, [rbp+var_44]\njmp loc_1330\nloc_1422:\nor [rsp+rcx+1050h+var_1058], 0\njmp loc_12A7\nloc_142D:\nmovsxd rax, edx\nmov [rbp+var_50], rax\njmp loc_139A\nloc_1439:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n __int64 v3; // rcx\n unsigned __int64 v4; // r15\n __int64 v5; // rcx\n __int64 *v6; // rsi\n __int16 v7; // cx\n signed __int64 v8; // rcx\n void *v9; // rsp\n unsigned __int64 v10; // rsi\n _DWORD *v11; // r8\n __int64 v12; // r14\n __int64 v13; // r13\n _DWORD *v14; // rbx\n int v15; // ecx\n int v16; // r12d\n __int64 v17; // rax\n __int64 v18; // rax\n _DWORD *v20; // rdx\n int v21; // ecx\n __int64 v22; // r11\n int v23; // r12d\n unsigned int v24; // r12d\n _DWORD v26[1022]; // [rsp+8h] [rbp-1050h] BYREF\n __int64 v27; // [rsp+1008h] [rbp-50h] BYREF\n int v28; // [rsp+1014h] [rbp-44h]\n unsigned __int64 v29; // [rsp+1020h] [rbp-38h]\n\n v3 = a2 + 1;\n v4 = 4 * v3;\n v29 = __readfsqword(0x28u);\n v5 = 4 * v3 * (a1 + 1) + 15;\n v6 = (__int64 *)((char *)&v27 - (v5 & 0xFFFFFFFFFFFFF000LL));\n v7 = v5 & 0xFFF0;\n if ( &v27 != v6 )\n {\n while ( v26 != (_DWORD *)v6 )\n ;\n }\n v8 = v7 & 0xFFF;\n v9 = alloca(v8);\n if ( v8 )\n *(_QWORD *)((char *)&v26[-2] + v8) = *(_QWORD *)((char *)&v26[-2] + v8);\n v10 = v4 >> 2;\n if ( a1 >= 0 )\n {\n v11 = v26;\n v12 = -1LL;\n v13 = 0LL;\n v14 = &v26[-v10];\n v27 = a1;\n while ( 1 )\n {\n v15 = v13;\n if ( a2 <= (int)v13 )\n v15 = a2;\n if ( v15 >= 0 )\n {\n if ( a2 <= 0 )\n {\n LODWORD(v17) = 0;\nLABEL_15:\n v17 = (int)v17;\n do\n {\n while ( (_DWORD)v17 )\n {\n v11[v17] = v17 * v26[v10 * (int)v12 - 1 + (int)v17] + v14[v17];\n if ( v15 < (int)++v17 )\n goto LABEL_19;\n }\n ++v17;\n v26[v10 * (int)v13] = 1;\n }\n while ( v15 >= (int)v17 );\n goto LABEL_19;\n }\n v16 = v15 + 1;\n if ( v15 + 1 > a2 )\n v16 = a2;\n v26[v10 * (int)v13] = 1;\n LODWORD(v17) = 1;\n v11[1] = 0;\n if ( v16 != 1 )\n {\n v28 = v15;\n v20 = v11 + 1;\n v21 = v16;\n v22 = v10 * (v12 - v13);\n do\n {\n v23 = v17 * v20[v22 - 1];\n LODWORD(v17) = v17 + 1;\n v24 = v20[v22] + v23;\n *(_QWORD *)v20++ = v24;\n }\n while ( (int)v17 < v21 );\n v15 = v28;\n }\n if ( v15 >= (int)v17 )\n goto LABEL_15;\n }\nLABEL_19:\n v18 = v27;\n ++v12;\n ++v13;\n v14 = (_DWORD *)((char *)v14 + v4);\n v11 = (_DWORD *)((char *)v11 + v4);\n if ( v12 == v27 )\n return (unsigned int)v26[v10 * v18 + a2];\n }\n }\n v18 = a1;\n v27 = a1;\n return (unsigned int)v26[v10 * v18 + a2];\n}", + "ida_strip_asm": "sub_1220:\nendbr64\npush rbp\nlea ecx, [rsi+1]\nmov r10d, esi\nmov edx, edi\nmovsxd rcx, ecx\nmov rbp, rsp\npush r15\nlea r15, ds:0[rcx*4]\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 28h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nlea eax, [rdi+1]\nmov rsi, rsp\ncdqe\nimul rax, rcx\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rsi, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rsi\njz short loc_1295\nloc_1280:\nsub rsp, 1000h\nor [rsp+1050h+var_58], 0\ncmp rsp, rsi\njnz short loc_1280\nloc_1295:\nand ecx, 0FFFh\nsub rsp, rcx\ntest rcx, rcx\njnz loc_1422\nloc_12A7:\nmov rsi, r15\nmov r9, rsp\nshr rsi, 2\ntest edx, edx\njs loc_142D\nmov rax, rsi\nmov r8, r9\nmov r14, 0FFFFFFFFFFFFFFFFh\nxor r13d, r13d\nneg rax\nlea rbx, [r9+rax*4]\nmovsxd rax, edx\nmov [rbp+var_50], rax\nnop word ptr [rax+rax+00000000h]\nloc_12E0:\nmov ecx, r13d\ncmp r10d, r13d\nmovsxd rdi, r13d\ncmovle ecx, r10d\ntest ecx, ecx\njs loc_137F\ntest r10d, r10d\njle loc_13D0\nlea r12d, [rcx+1]\nmovsxd rax, edi\ncmp r12d, r10d\ncmovg r12d, r10d\nimul rax, rsi\nmov dword ptr [r9+rax*4], 1\nmov eax, 1\nmov dword ptr [r8+4], 0\ncmp r12d, 1\njnz loc_13E0\nnop\nloc_1330:\ncmp ecx, eax\njl short loc_137F\nloc_1334:\nmovsxd r11, r14d\nimul rdi, rsi\ncdqe\nimul r11, rsi\njmp short loc_136B\nloc_1348:\nlea edx, [rax-1]\nmovsxd rdx, edx\nadd rdx, r11\nmov r12d, [r9+rdx*4]\nmov edx, [rbx+rax*4]\nimul r12d, eax\nadd edx, r12d\nmov [r8+rax*4], edx\nadd rax, 1\ncmp ecx, eax\njl short loc_137F\nloc_136B:\ntest eax, eax\njnz short loc_1348\nadd rax, 1\nmov dword ptr [r9+rdi*4], 1\ncmp ecx, eax\njge short loc_136B\nloc_137F:\nmov rax, [rbp+var_50]\nadd r14, 1\nadd r13, 1\nadd rbx, r15\nadd r8, r15\ncmp r14, rax\njnz loc_12E0\nloc_139A:\nmov rdx, rax\nmovsxd rax, r10d\nimul rdx, rsi\nadd rax, rdx\nmov eax, [r9+rax*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_1439\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_13D0:\nxor eax, eax\njmp loc_1334\nloc_13E0:\nmov r11, r14\nmov [rbp+var_44], ecx\nlea rdx, [r8+4]\nmov ecx, r12d\nsub r11, r13\nimul r11, rsi\nnop dword ptr [rax+00h]\nloc_13F8:\nmov r12d, [rdx+r11*4-4]\nimul r12d, eax\nadd eax, 1\nadd r12d, [rdx+r11*4]\nadd rdx, 4\nmov [rdx-4], r12d\nmov dword ptr [rdx], 0\ncmp eax, ecx\njl short loc_13F8\nmov ecx, [rbp+var_44]\njmp loc_1330\nloc_1422:\nor [rsp+rcx+1050h+var_1058], 0\njmp loc_12A7\nloc_142D:\nmovsxd rax, edx\nmov [rbp+var_50], rax\njmp loc_139A\nloc_1439:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1220(int a1, int a2)\n{\n __int64 v3; // rcx\n unsigned __int64 v4; // r15\n __int64 v5; // rcx\n __int64 *v6; // rsi\n __int16 v7; // cx\n signed __int64 v8; // rcx\n void *v9; // rsp\n unsigned __int64 v10; // rsi\n _DWORD *v11; // r8\n __int64 v12; // r14\n __int64 v13; // r13\n _DWORD *v14; // rbx\n int v15; // ecx\n int v16; // r12d\n __int64 v17; // rax\n __int64 v18; // rax\n _DWORD *v20; // rdx\n int v21; // ecx\n __int64 v22; // r11\n int v23; // r12d\n unsigned int v24; // r12d\n _DWORD v26[1022]; // [rsp+8h] [rbp-1050h] BYREF\n __int64 v27; // [rsp+1008h] [rbp-50h] BYREF\n int v28; // [rsp+1014h] [rbp-44h]\n unsigned __int64 v29; // [rsp+1020h] [rbp-38h]\n\n v3 = a2 + 1;\n v4 = 4 * v3;\n v29 = __readfsqword(0x28u);\n v5 = 4 * v3 * (a1 + 1) + 15;\n v6 = (__int64 *)((char *)&v27 - (v5 & 0xFFFFFFFFFFFFF000LL));\n v7 = v5 & 0xFFF0;\n if ( &v27 != v6 )\n {\n while ( v26 != (_DWORD *)v6 )\n ;\n }\n v8 = v7 & 0xFFF;\n v9 = alloca(v8);\n if ( v8 )\n *(_QWORD *)((char *)&v26[-2] + v8) = *(_QWORD *)((char *)&v26[-2] + v8);\n v10 = v4 >> 2;\n if ( a1 >= 0 )\n {\n v11 = v26;\n v12 = -1LL;\n v13 = 0LL;\n v14 = &v26[-v10];\n v27 = a1;\n while ( 1 )\n {\n v15 = v13;\n if ( a2 <= (int)v13 )\n v15 = a2;\n if ( v15 >= 0 )\n {\n if ( a2 <= 0 )\n {\n LODWORD(v17) = 0;\nLABEL_15:\n v17 = (int)v17;\n do\n {\n while ( (_DWORD)v17 )\n {\n v11[v17] = v17 * v26[v10 * (int)v12 - 1 + (int)v17] + v14[v17];\n if ( v15 < (int)++v17 )\n goto LABEL_19;\n }\n ++v17;\n v26[v10 * (int)v13] = 1;\n }\n while ( v15 >= (int)v17 );\n goto LABEL_19;\n }\n v16 = v15 + 1;\n if ( v15 + 1 > a2 )\n v16 = a2;\n v26[v10 * (int)v13] = 1;\n LODWORD(v17) = 1;\n v11[1] = 0;\n if ( v16 != 1 )\n {\n v28 = v15;\n v20 = v11 + 1;\n v21 = v16;\n v22 = v10 * (v12 - v13);\n do\n {\n v23 = v17 * v20[v22 - 1];\n LODWORD(v17) = v17 + 1;\n v24 = v20[v22] + v23;\n *(_QWORD *)v20++ = v24;\n }\n while ( (int)v17 < v21 );\n v15 = v28;\n }\n if ( v15 >= (int)v17 )\n goto LABEL_15;\n }\nLABEL_19:\n v18 = v27;\n ++v12;\n ++v13;\n v14 = (_DWORD *)((char *)v14 + v4);\n v11 = (_DWORD *)((char *)v11 + v4);\n if ( v12 == v27 )\n return (unsigned int)v26[v10 * v18 + a2];\n }\n }\n v18 = a1;\n v27 = a1;\n return (unsigned int)v26[v10 * v18 + a2];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1220(int a1, int a2) {\n long long v3;\n unsigned long long v4;\n long long v5;\n long long *v6;\n short v7;\n signed long long v8;\n void *v9;\n unsigned long long v10;\n uint32_t *v11;\n long long v12;\n long long v13;\n uint32_t *v14;\n int v15;\n int v16;\n long long v17;\n long long v18;\n uint32_t *v20;\n int v21;\n long long v22;\n int v23;\n unsigned int v24;\n uint32_t v26[1022];\n long long v27;\n int v28;\n unsigned long long v29;\n v3 = a2 + 1;\n v4 = 4 * v3;\n v29 = __readfsqword(40u);\n v5 = 4 * v3 * (a1 + 1) + 15;\n v6 = (long long *)((char *)&v27 - (v5 & 18446744073709547520LL));\n v7 = v5 & 65520;\n if (&v27 != v6) {\n while (v26 != (uint32_t *)v6)\n ;\n }\n v8 = v7 & 4095;\n v9 = alloca(v8);\n if (v8)\n *(uint64_t *)((char *)&v26[-2] + v8) = *(uint64_t *)((char *)&v26[-2] + v8);\n v10 = v4 >> 2;\n if (a1 >= 0) {\n v11 = v26;\n v12 = -1LL;\n v13 = 0LL;\n v14 = &v26[-v10];\n v27 = a1;\n while (1) {\n v15 = v13;\n if (a2 <= (int)v13) v15 = a2;\n if (v15 >= 0) {\n if (a2 <= 0) {\n LODWORD(v17) = 0;\n LABEL_15:\n v17 = (int)v17;\n do {\n while ((uint32_t)v17) {\n v11[v17] = v17 * v26[v10 * (int)v12 - 1 + (int)v17] + v14[v17];\n if (v15 < (int)++v17) goto LABEL_19;\n }\n ++v17;\n v26[v10 * (int)v13] = 1;\n } while (v15 >= (int)v17);\n goto LABEL_19;\n }\n v16 = v15 + 1;\n if (v15 + 1 > a2) v16 = a2;\n v26[v10 * (int)v13] = 1;\n LODWORD(v17) = 1;\n v11[1] = 0;\n if (v16 != 1) {\n v28 = v15;\n v20 = v11 + 1;\n v21 = v16;\n v22 = v10 * (v12 - v13);\n do {\n v23 = v17 * v20[v22 - 1];\n LODWORD(v17) = v17 + 1;\n v24 = v20[v22] + v23;\n *(uint64_t *)v20++ = v24;\n } while ((int)v17 < v21);\n v15 = v28;\n }\n if (v15 >= (int)v17) goto LABEL_15;\n }\n LABEL_19:\n v18 = v27;\n ++v12;\n ++v13;\n v14 = (uint32_t *)((char *)v14 + v4);\n v11 = (uint32_t *)((char *)v11 + v4);\n if (v12 == v27) return (unsigned int)v26[v10 * v18 + a2];\n }\n }\n v18 = a1;\n v27 = a1;\n return (unsigned int)v26[v10 * v18 + a2];\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n long long v3;\n unsigned long long v4;\n long long v5;\n long long *v6;\n short v7;\n signed long long v8;\n void *v9;\n unsigned long long v10;\n uint32_t *v11;\n long long v12;\n long long v13;\n uint32_t *v14;\n int v15;\n int v16;\n long long v17;\n long long v18;\n uint32_t *v20;\n int v21;\n long long v22;\n int v23;\n unsigned int v24;\n uint32_t v26[1022];\n long long v27;\n int v28;\n unsigned long long v29;\n v3 = a2 + 1;\n v4 = 4 * v3;\n v29 = __readfsqword(40u);\n v5 = 4 * v3 * (a1 + 1) + 15;\n v6 = (long long *)((char *)&v27 - (v5 & 18446744073709547520LL));\n v7 = v5 & 65520;\n if (&v27 != v6) {\n while (v26 != (uint32_t *)v6)\n ;\n }\n v8 = v7 & 4095;\n v9 = alloca(v8);\n if (v8)\n *(uint64_t *)((char *)&v26[-2] + v8) = *(uint64_t *)((char *)&v26[-2] + v8);\n v10 = v4 >> 2;\n if (a1 >= 0) {\n v11 = v26;\n v12 = -1LL;\n v13 = 0LL;\n v14 = &v26[-v10];\n v27 = a1;\n while (1) {\n v15 = v13;\n if (a2 <= (int)v13) v15 = a2;\n if (v15 >= 0) {\n if (a2 <= 0) {\n LODWORD(v17) = 0;\n LABEL_15:\n v17 = (int)v17;\n do {\n while ((uint32_t)v17) {\n v11[v17] = v17 * v26[v10 * (int)v12 - 1 + (int)v17] + v14[v17];\n if (v15 < (int)++v17) goto LABEL_19;\n }\n ++v17;\n v26[v10 * (int)v13] = 1;\n } while (v15 >= (int)v17);\n goto LABEL_19;\n }\n v16 = v15 + 1;\n if (v15 + 1 > a2) v16 = a2;\n v26[v10 * (int)v13] = 1;\n LODWORD(v17) = 1;\n v11[1] = 0;\n if (v16 != 1) {\n v28 = v15;\n v20 = v11 + 1;\n v21 = v16;\n v22 = v10 * (v12 - v13);\n do {\n v23 = v17 * v20[v22 - 1];\n LODWORD(v17) = v17 + 1;\n v24 = v20[v22] + v23;\n *(uint64_t *)v20++ = v24;\n } while ((int)v17 < v21);\n v15 = v28;\n }\n if (v15 >= (int)v17) goto LABEL_15;\n }\n LABEL_19:\n v18 = v27;\n ++v12;\n ++v13;\n v14 = (uint32_t *)((char *)v14 + v4);\n v11 = (uint32_t *)((char *)v11 + v4);\n if (v12 == v27) return (unsigned int)v26[v10 * v18 + a2];\n }\n }\n v18 = a1;\n v27 = a1;\n return (unsigned int)v26[v10 * v18 + a2];\n}" + }, + { + "index": 507, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(char *list1[], int list1_size, char *removewords[],\n int removewords_size) {\n int i, j;\n for (i = 0; i < list1_size; i++) {\n for (j = 0; j < removewords_size; j++) {\n if (strcmp(list1[i], removewords[j]) == 0) {\n memmove(&list1[i], &list1[i + 1],\n (list1_size - i - 1) * sizeof(char *));\n list1_size--;\n i--;\n break;\n }\n }\n }\n list1[list1_size] = NULL;\n}", + "test": "int main() {\n\n char *test_list1[] = {\"red\", \"green\", \"blue\", \"white\", \"black\", \"orange\", NULL};\n\n char *remove1[] = {\"white\", \"orange\", NULL};\n\n char *expected1[] = {\"red\", \"green\", \"blue\", \"black\", NULL};\n\n\n\n char *test_list2[] = {\"red\", \"green\", \"blue\", \"white\", \"black\", \"orange\", NULL};\n\n char *remove2[] = {\"black\", \"orange\", NULL};\n\n char *expected2[] = {\"red\", \"green\", \"blue\", \"white\", NULL};\n\n\n\n char *test_list3[] = {\"red\", \"green\", \"blue\", \"white\", \"black\", \"orange\", NULL};\n\n char *remove3[] = {\"blue\", \"white\", NULL};\n\n char *expected3[] = {\"red\", \"green\", \"black\", \"orange\", NULL};\n\n\n\n func0(test_list1, 6, remove1, 2);\n\n for (int i = 0; test_list1[i] != NULL; i++) {\n\n assert(strcmp(test_list1[i], expected1[i]) == 0);\n\n }\n\n\n\n func0(test_list2, 6, remove2, 2);\n\n for (int i = 0; test_list2[i] != NULL; i++) {\n\n assert(strcmp(test_list2[i], expected2[i]) == 0);\n\n }\n\n\n\n func0(test_list3, 6, remove3, 2);\n\n for (int i = 0; test_list3[i] != NULL; i++) {\n\n assert(strcmp(test_list3[i], expected3[i]) == 0);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %ecx,-0x20(%rbp)\nmovl $0x0,-0x8(%rbp)\njmpq 1280 \nmovl $0x0,-0x4(%rbp)\njmpq 1270 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rdx\nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10a0 \ntest %eax,%eax\njne 126c \nmov -0x1c(%rbp),%eax\nsub -0x8(%rbp),%eax\nsub $0x1,%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x8(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,8),%rcx\nmov -0x18(%rbp),%rax\nadd %rax,%rcx\nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rsi\nmov -0x18(%rbp),%rax\nadd %rsi,%rax\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 10b0 \nsubl $0x1,-0x1c(%rbp)\nsubl $0x1,-0x8(%rbp)\njmp 127c \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x20(%rbp),%eax\njl 11db \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11cf \nmov -0x1c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovq $0x0,(%rax)\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov [rbp+var_8], 0\njmp loc_1280\nloc_11CF:\nmov [rbp+var_4], 0\njmp loc_1270\nloc_11DB:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_126C\nmov eax, [rbp+var_1C]\nsub eax, [rbp+var_8]\nsub eax, 1\ncdqe\nlea rdx, ds:0[rax*8]; n\nmov eax, [rbp+var_8]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rcx, rax\nmov eax, [rbp+var_8]\ncdqe\nlea rsi, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rsi\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _memmove\nsub [rbp+var_1C], 1\nsub [rbp+var_8], 1\njmp short loc_127C\nloc_126C:\nadd [rbp+var_4], 1\nloc_1270:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_20]\njl loc_11DB\nloc_127C:\nadd [rbp+var_8], 1\nloc_1280:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl loc_11CF\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov qword ptr [rax], 0\nnop\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, int a2, __int64 a3, int a4)\n{\n _QWORD *result; // rax\n int i; // [rsp+28h] [rbp-8h]\n int j; // [rsp+2Ch] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n for ( j = 0; j < a4; ++j )\n {\n if ( !strcmp(*(const char **)(8LL * i + a1), *(const char **)(8LL * j + a3)) )\n {\n memmove((void *)(8LL * i + a1), (const void *)(a1 + 8 * (i + 1LL)), 8LL * (a2 - i - 1));\n --a2;\n --i;\n break;\n }\n }\n }\n result = (_QWORD *)(8LL * a2 + a1);\n *result = 0LL;\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov [rbp+var_8], 0\njmp loc_1280\nloc_11CF:\nmov [rbp+var_4], 0\njmp loc_1270\nloc_11DB:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_126C\nmov eax, [rbp+var_1C]\nsub eax, [rbp+var_8]\nsub eax, 1\ncdqe\nlea rdx, ds:0[rax*8]; n\nmov eax, [rbp+var_8]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rcx, rax\nmov eax, [rbp+var_8]\ncdqe\nlea rsi, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rsi\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _memmove\nsub [rbp+var_1C], 1\nsub [rbp+var_8], 1\njmp short loc_127C\nloc_126C:\nadd [rbp+var_4], 1\nloc_1270:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_20]\njl loc_11DB\nloc_127C:\nadd [rbp+var_8], 1\nloc_1280:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl loc_11CF\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov qword ptr [rax], 0\nnop\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11A9(__int64 a1, int a2, __int64 a3, int a4)\n{\n _QWORD *result; // rax\n int i; // [rsp+28h] [rbp-8h]\n int j; // [rsp+2Ch] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n for ( j = 0; j < a4; ++j )\n {\n if ( !strcmp(*(const char **)(8LL * i + a1), *(const char **)(8LL * j + a3)) )\n {\n memmove((void *)(8LL * i + a1), (const void *)(a1 + 8 * (i + 1LL)), 8LL * (a2 - i - 1));\n --a2;\n --i;\n break;\n }\n }\n }\n result = (_QWORD *)(8LL * a2 + a1);\n *result = 0LL;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11A9(long long a1, int a2, long long a3, int a4) {\n uint64_t *result;\n int i;\n int j;\n for (i = 0; i < a2; ++i) {\n for (j = 0; j < a4; ++j) {\n if (!strcmp(*(const char **)(8LL * i + a1),\n *(const char **)(8LL * j + a3))) {\n memmove((void *)(8LL * i + a1), (const void *)(a1 + 8 * (i + 1LL)),\n 8LL * (a2 - i - 1));\n --a2;\n --i;\n break;\n }\n }\n }\n result = (uint64_t *)(8LL * a2 + a1);\n *result = 0LL;\n return result;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, int a2, long long a3, int a4) {\n uint64_t *result;\n int i;\n int j;\n for (i = 0; i < a2; ++i) {\n for (j = 0; j < a4; ++j) {\n if (!strcmp(*(const char **)(8LL * i + a1),\n *(const char **)(8LL * j + a3))) {\n memmove((void *)(8LL * i + a1), (const void *)(a1 + 8 * (i + 1LL)),\n 8LL * (a2 - i - 1));\n --a2;\n --i;\n break;\n }\n }\n }\n result = (uint64_t *)(8LL * a2 + a1);\n *result = 0LL;\n return result;\n}" + }, + { + "index": 507, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(char *list1[], int list1_size, char *removewords[],\n int removewords_size) {\n int i, j;\n for (i = 0; i < list1_size; i++) {\n for (j = 0; j < removewords_size; j++) {\n if (strcmp(list1[i], removewords[j]) == 0) {\n memmove(&list1[i], &list1[i + 1],\n (list1_size - i - 1) * sizeof(char *));\n list1_size--;\n i--;\n break;\n }\n }\n }\n list1[list1_size] = NULL;\n}", + "test": "int main() {\n\n char *test_list1[] = {\"red\", \"green\", \"blue\", \"white\", \"black\", \"orange\", NULL};\n\n char *remove1[] = {\"white\", \"orange\", NULL};\n\n char *expected1[] = {\"red\", \"green\", \"blue\", \"black\", NULL};\n\n\n\n char *test_list2[] = {\"red\", \"green\", \"blue\", \"white\", \"black\", \"orange\", NULL};\n\n char *remove2[] = {\"black\", \"orange\", NULL};\n\n char *expected2[] = {\"red\", \"green\", \"blue\", \"white\", NULL};\n\n\n\n char *test_list3[] = {\"red\", \"green\", \"blue\", \"white\", \"black\", \"orange\", NULL};\n\n char *remove3[] = {\"blue\", \"white\", NULL};\n\n char *expected3[] = {\"red\", \"green\", \"black\", \"orange\", NULL};\n\n\n\n func0(test_list1, 6, remove1, 2);\n\n for (int i = 0; test_list1[i] != NULL; i++) {\n\n assert(strcmp(test_list1[i], expected1[i]) == 0);\n\n }\n\n\n\n func0(test_list2, 6, remove2, 2);\n\n for (int i = 0; test_list2[i] != NULL; i++) {\n\n assert(strcmp(test_list2[i], expected2[i]) == 0);\n\n }\n\n\n\n func0(test_list3, 6, remove3, 2);\n\n for (int i = 0; test_list3[i] != NULL; i++) {\n\n assert(strcmp(test_list3[i], expected3[i]) == 0);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x28,%rsp\nmov %rdi,(%rsp)\nmov %esi,%r15d\nmov %ecx,0x14(%rsp)\ntest %esi,%esi\njle 1253 \nmov %rdx,0x18(%rsp)\nlea -0x1(%rcx),%eax\nlea 0x8(%rdx,%rax,8),%r12\nmov $0x0,%r13d\njmp 1217 \nmov %r15d,%edx\nsub %r13d,%edx\nsub $0x1,%edx\nmovslq %edx,%rdx\nshl $0x3,%rdx\nmov (%rsp),%rax\nlea 0x8(%rax,%r14,1),%rsi\nmov 0x8(%rsp),%rdi\ncallq 10b0 \nsub $0x1,%r15d\nsub $0x1,%r13d\nadd $0x1,%r13d\ncmp %r13d,%r15d\njle 1253 \ncmpl $0x0,0x14(%rsp)\njle 120e \nmovslq %r13d,%r14\nshl $0x3,%r14\nmov (%rsp),%rax\nadd %r14,%rax\nmov %rax,0x8(%rsp)\nmov (%rax),%rbp\nmov 0x18(%rsp),%rbx\nmov (%rbx),%rsi\nmov %rbp,%rdi\ncallq 10a0 \ntest %eax,%eax\nje 11e3 \nadd $0x8,%rbx\ncmp %r12,%rbx\njne 1239 \njmp 120e \nmovslq %r15d,%r15\nmov (%rsp),%rax\nmovq $0x0,(%rax,%r15,8)\nadd $0x28,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov [rsp+58h+var_58], rdi\nmov r15d, esi\nmov [rsp+58h+var_40], rdx\nmov [rsp+58h+var_44], ecx\ntest esi, esi\njle loc_1253\nmov eax, ecx\ncdqe\nlea r12, [rdx+rax*8]\nmov r13d, 0\njmp short loc_1217\nloc_11E3:\nmov edx, r15d\nsub edx, r13d\nsub edx, 1\nmovsxd rdx, edx\nshl rdx, 3; n\nmov rax, [rsp+58h+var_58]\nlea rsi, [rax+r14+8]; src\nmov rdi, [rsp+58h+dest]; dest\ncall _memmove\nsub r15d, 1\nsub r13d, 1\nloc_120E:\nadd r13d, 1\ncmp r15d, r13d\njle short loc_1253\nloc_1217:\ncmp [rsp+58h+var_44], 0\njle short loc_120E\nmovsxd r14, r13d\nshl r14, 3\nmov rax, [rsp+58h+var_58]\nadd rax, r14\nmov [rsp+58h+dest], rax\nmov rbp, [rax]\nmov rbx, [rsp+58h+var_40]\nloc_1239:\nmov rsi, [rbx]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njz short loc_11E3\nadd rbx, 8\ncmp rbx, r12\njnz short loc_1239\njmp short loc_120E\nloc_1253:\nmovsxd r15, r15d\nmov rax, [rsp+58h+var_58]\nmov qword ptr [rax+r15*8], 0\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, const char **a3, int a4)\n{\n int v4; // r15d\n const char **v5; // r12\n int v6; // r13d\n __int64 v7; // r14\n const char *v8; // rbp\n const char **v9; // rbx\n __int64 result; // rax\n\n v4 = a2;\n if ( a2 > 0 )\n {\n v5 = &a3[a4];\n v6 = 0;\n do\n {\n if ( a4 > 0 )\n {\n v7 = 8LL * v6;\n v8 = *(const char **)(v7 + a1);\n v9 = a3;\n while ( strcmp(v8, *v9) )\n {\n if ( ++v9 == v5 )\n goto LABEL_4;\n }\n memmove((void *)(v7 + a1), (const void *)(a1 + v7 + 8), 8LL * (v4 - v6 - 1));\n --v4;\n --v6;\n }\nLABEL_4:\n ++v6;\n }\n while ( v4 > v6 );\n }\n result = a1;\n *(_QWORD *)(a1 + 8LL * v4) = 0LL;\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov [rsp+58h+var_58], rdi\nmov r15d, esi\nmov [rsp+58h+var_40], rdx\nmov [rsp+58h+var_44], ecx\ntest esi, esi\njle loc_1253\nmov eax, ecx\ncdqe\nlea r12, [rdx+rax*8]\nmov r13d, 0\njmp short loc_1217\nloc_11E3:\nmov edx, r15d\nsub edx, r13d\nsub edx, 1\nmovsxd rdx, edx\nshl rdx, 3; n\nmov rax, [rsp+58h+var_58]\nlea rsi, [rax+r14+8]; src\nmov rdi, [rsp+58h+dest]; dest\ncall _memmove\nsub r15d, 1\nsub r13d, 1\nloc_120E:\nadd r13d, 1\ncmp r15d, r13d\njle short loc_1253\nloc_1217:\ncmp [rsp+58h+var_44], 0\njle short loc_120E\nmovsxd r14, r13d\nshl r14, 3\nmov rax, [rsp+58h+var_58]\nadd rax, r14\nmov [rsp+58h+dest], rax\nmov rbp, [rax]\nmov rbx, [rsp+58h+var_40]\nloc_1239:\nmov rsi, [rbx]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njz short loc_11E3\nadd rbx, 8\ncmp rbx, r12\njnz short loc_1239\njmp short loc_120E\nloc_1253:\nmovsxd r15, r15d\nmov rax, [rsp+58h+var_58]\nmov qword ptr [rax+r15*8], 0\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(__int64 a1, int a2, const char **a3, int a4)\n{\n int v4; // r15d\n const char **v5; // r12\n int v6; // r13d\n __int64 v7; // r14\n const char *v8; // rbp\n const char **v9; // rbx\n __int64 result; // rax\n\n v4 = a2;\n if ( a2 > 0 )\n {\n v5 = &a3[a4];\n v6 = 0;\n do\n {\n if ( a4 > 0 )\n {\n v7 = 8LL * v6;\n v8 = *(const char **)(v7 + a1);\n v9 = a3;\n while ( strcmp(v8, *v9) )\n {\n if ( ++v9 == v5 )\n goto LABEL_4;\n }\n memmove((void *)(v7 + a1), (const void *)(a1 + v7 + 8), 8LL * (v4 - v6 - 1));\n --v4;\n --v6;\n }\nLABEL_4:\n ++v6;\n }\n while ( v4 > v6 );\n }\n result = a1;\n *(_QWORD *)(a1 + 8LL * v4) = 0LL;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(long long a1, int a2, const char **a3, int a4) {\n int v4;\n const char **v5;\n int v6;\n long long v7;\n const char *v8;\n const char **v9;\n long long result;\n v4 = a2;\n if (a2 > 0) {\n v5 = &a3[a4];\n v6 = 0;\n do {\n if (a4 > 0) {\n v7 = 8LL * v6;\n v8 = *(const char **)(v7 + a1);\n v9 = a3;\n while (strcmp(v8, *v9)) {\n if (++v9 == v5) goto LABEL_4;\n }\n memmove((void *)(v7 + a1), (const void *)(a1 + v7 + 8),\n 8LL * (v4 - v6 - 1));\n --v4;\n --v6;\n }\n LABEL_4:\n ++v6;\n } while (v4 > v6);\n }\n result = a1;\n *(uint64_t *)(a1 + 8LL * v4) = 0LL;\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, const char **a3, int a4) {\n int v4;\n const char **v5;\n int v6;\n long long v7;\n const char *v8;\n const char **v9;\n long long result;\n v4 = a2;\n if (a2 > 0) {\n v5 = &a3[a4];\n v6 = 0;\n do {\n if (a4 > 0) {\n v7 = 8LL * v6;\n v8 = *(const char **)(v7 + a1);\n v9 = a3;\n while (strcmp(v8, *v9)) {\n if (++v9 == v5) goto LABEL_4;\n }\n memmove((void *)(v7 + a1), (const void *)(a1 + v7 + 8),\n 8LL * (v4 - v6 - 1));\n --v4;\n --v6;\n }\n LABEL_4:\n ++v6;\n } while (v4 > v6);\n }\n result = a1;\n *(uint64_t *)(a1 + 8LL * v4) = 0LL;\n return result;\n}" + }, + { + "index": 507, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(char *list1[], int list1_size, char *removewords[],\n int removewords_size) {\n int i, j;\n for (i = 0; i < list1_size; i++) {\n for (j = 0; j < removewords_size; j++) {\n if (strcmp(list1[i], removewords[j]) == 0) {\n memmove(&list1[i], &list1[i + 1],\n (list1_size - i - 1) * sizeof(char *));\n list1_size--;\n i--;\n break;\n }\n }\n }\n list1[list1_size] = NULL;\n}", + "test": "int main() {\n\n char *test_list1[] = {\"red\", \"green\", \"blue\", \"white\", \"black\", \"orange\", NULL};\n\n char *remove1[] = {\"white\", \"orange\", NULL};\n\n char *expected1[] = {\"red\", \"green\", \"blue\", \"black\", NULL};\n\n\n\n char *test_list2[] = {\"red\", \"green\", \"blue\", \"white\", \"black\", \"orange\", NULL};\n\n char *remove2[] = {\"black\", \"orange\", NULL};\n\n char *expected2[] = {\"red\", \"green\", \"blue\", \"white\", NULL};\n\n\n\n char *test_list3[] = {\"red\", \"green\", \"blue\", \"white\", \"black\", \"orange\", NULL};\n\n char *remove3[] = {\"blue\", \"white\", NULL};\n\n char *expected3[] = {\"red\", \"green\", \"black\", \"orange\", NULL};\n\n\n\n func0(test_list1, 6, remove1, 2);\n\n for (int i = 0; test_list1[i] != NULL; i++) {\n\n assert(strcmp(test_list1[i], expected1[i]) == 0);\n\n }\n\n\n\n func0(test_list2, 6, remove2, 2);\n\n for (int i = 0; test_list2[i] != NULL; i++) {\n\n assert(strcmp(test_list2[i], expected2[i]) == 0);\n\n }\n\n\n\n func0(test_list3, 6, remove3, 2);\n\n for (int i = 0; test_list3[i] != NULL; i++) {\n\n assert(strcmp(test_list3[i], expected3[i]) == 0);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\nmov %esi,%r14d\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x28,%rsp\nmov %rdi,(%rsp)\nmov %rdx,0x18(%rsp)\nmov %ecx,0x14(%rsp)\ntest %esi,%esi\njle 15a8 \nmov %ecx,%eax\nxor %r13d,%r13d\nsub $0x1,%eax\nlea 0x8(%rdx,%rax,8),%rbp\nnopw 0x0(%rax,%rax,1)\nmov 0x14(%rsp),%eax\ntest %eax,%eax\njle 15d0 \nmovslq %r13d,%r12\nmov (%rsp),%r15\nlea 0x0(,%r12,8),%rax\nmov 0x18(%rsp),%r12\nadd %rax,%r15\nmov %rax,0x8(%rsp)\nmov (%r15),%rbx\njmp 1569 \nnopl (%rax)\nadd $0x8,%r12\ncmp %r12,%rbp\nje 15d0 \nmov (%r12),%rsi\nmov %rbx,%rdi\ncallq 10a0 \ntest %eax,%eax\njne 1560 \nmov %r14d,%edx\nmov (%rsp),%rax\nmov 0x8(%rsp),%rcx\nmov %r15,%rdi\nsub %r13d,%edx\nsub $0x1,%r14d\nsub $0x1,%edx\nlea 0x8(%rax,%rcx,1),%rsi\nmovslq %edx,%rdx\nshl $0x3,%rdx\ncallq 10b0 \ncmp %r13d,%r14d\njg 1530 \nmov (%rsp),%rax\nmovslq %r14d,%r14\nmovq $0x0,(%rax,%r14,8)\nadd $0x28,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw %cs:0x0(%rax,%rax,1)\nadd $0x1,%r13d\njmp 15a3 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12d, esi\npush rbp\npush rbx\nsub rsp, 28h\nmov [rsp+58h+var_58], rdi\nmov [rsp+58h+var_40], rdx\ntest esi, esi\njle loc_1554\ntest ecx, ecx\njle loc_1554\nmov [rsp+58h+var_48], 0\nmovsxd rcx, ecx\nxor r13d, r13d\nlea rbp, [rdx+rcx*8]\nnop dword ptr [rax+00000000h]\nloc_14E8:\nmov rax, [rsp+58h+var_48]\nmov r14, [rsp+58h+var_40]\nlea r15, ds:0[rax*8]\nmov rax, [rsp+58h+var_58]\nadd rax, r15\nmov [rsp+58h+dest], rax\nmov rbx, [rax]\njmp short loc_1519\nloc_1510:\nadd r14, 8\ncmp rbp, r14\njz short loc_1578\nloc_1519:\nmov rsi, [r14]; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1510\nmov edx, r12d\nmov rax, [rsp+58h+var_58]\nmov rdi, [rsp+58h+dest]; dest\nsub r12d, 1\nsub edx, r13d\nsub edx, 1\nlea rsi, [rax+r15+8]; src\nmovsxd rdx, edx\nshl rdx, 3; n\ncall _memmove\ncmp r12d, r13d\njg short loc_14E8\nloc_1554:\nmov rax, [rsp+58h+var_58]\nmovsxd r12, r12d\nmov qword ptr [rax+r12*8], 0\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1578:\nadd r13d, 1\ncmp r13d, r12d\njge short loc_1554\nmovsxd rax, r13d\nmov [rsp+58h+var_48], rax\njmp loc_14E8", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, const char **a3, int a4)\n{\n int v4; // r12d\n int v5; // r13d\n const char **v6; // rbp\n const char **v7; // r14\n const char *v8; // rbx\n int v9; // edx\n __int64 result; // rax\n const char **dest; // [rsp+8h] [rbp-50h]\n __int64 v12; // [rsp+10h] [rbp-48h]\n\n v4 = a2;\n if ( a2 > 0 && a4 > 0 )\n {\n v12 = 0LL;\n v5 = 0;\n v6 = &a3[a4];\nLABEL_4:\n while ( 2 )\n {\n v7 = a3;\n dest = (const char **)(8 * v12 + a1);\n v8 = *dest;\n while ( strcmp(v8, *v7) )\n {\n if ( v6 == ++v7 )\n {\n if ( ++v5 >= v4 )\n goto LABEL_8;\n v12 = v5;\n goto LABEL_4;\n }\n }\n v9 = v4--;\n memmove(dest, (const void *)(a1 + 8 * v12 + 8), 8LL * (v9 - v5 - 1));\n if ( v4 > v5 )\n continue;\n break;\n }\n }\nLABEL_8:\n result = a1;\n *(_QWORD *)(a1 + 8LL * v4) = 0LL;\n return result;\n}", + "ida_strip_asm": "sub_14A0:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12d, esi\npush rbp\npush rbx\nsub rsp, 28h\nmov [rsp+58h+var_58], rdi\nmov [rsp+58h+var_40], rdx\ntest esi, esi\njle loc_1554\ntest ecx, ecx\njle loc_1554\nmov [rsp+58h+var_48], 0\nmovsxd rcx, ecx\nxor r13d, r13d\nlea rbp, [rdx+rcx*8]\nnop dword ptr [rax+00000000h]\nloc_14E8:\nmov rax, [rsp+58h+var_48]\nmov r14, [rsp+58h+var_40]\nlea r15, ds:0[rax*8]\nmov rax, [rsp+58h+var_58]\nadd rax, r15\nmov [rsp+58h+dest], rax\nmov rbx, [rax]\njmp short loc_1519\nloc_1510:\nadd r14, 8\ncmp rbp, r14\njz short loc_1578\nloc_1519:\nmov rsi, [r14]; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1510\nmov edx, r12d\nmov rax, [rsp+58h+var_58]\nmov rdi, [rsp+58h+dest]; dest\nsub r12d, 1\nsub edx, r13d\nsub edx, 1\nlea rsi, [rax+r15+8]; src\nmovsxd rdx, edx\nshl rdx, 3; n\ncall _memmove\ncmp r12d, r13d\njg short loc_14E8\nloc_1554:\nmov rax, [rsp+58h+var_58]\nmovsxd r12, r12d\nmov qword ptr [rax+r12*8], 0\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1578:\nadd r13d, 1\ncmp r13d, r12d\njge short loc_1554\nmovsxd rax, r13d\nmov [rsp+58h+var_48], rax\njmp loc_14E8", + "ida_strip_pseudo": "__int64 __fastcall sub_14A0(__int64 a1, int a2, const char **a3, int a4)\n{\n int v4; // r12d\n int v5; // r13d\n const char **v6; // rbp\n const char **v7; // r14\n const char *v8; // rbx\n int v9; // edx\n __int64 result; // rax\n const char **dest; // [rsp+8h] [rbp-50h]\n __int64 v12; // [rsp+10h] [rbp-48h]\n\n v4 = a2;\n if ( a2 > 0 && a4 > 0 )\n {\n v12 = 0LL;\n v5 = 0;\n v6 = &a3[a4];\nLABEL_4:\n while ( 2 )\n {\n v7 = a3;\n dest = (const char **)(8 * v12 + a1);\n v8 = *dest;\n while ( strcmp(v8, *v7) )\n {\n if ( v6 == ++v7 )\n {\n if ( ++v5 >= v4 )\n goto LABEL_8;\n v12 = v5;\n goto LABEL_4;\n }\n }\n v9 = v4--;\n memmove(dest, (const void *)(a1 + 8 * v12 + 8), 8LL * (v9 - v5 - 1));\n if ( v4 > v5 )\n continue;\n break;\n }\n }\nLABEL_8:\n result = a1;\n *(_QWORD *)(a1 + 8LL * v4) = 0LL;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_14A0(long long a1, int a2, const char **a3, int a4) {\n int v4;\n int v5;\n const char **v6;\n const char **v7;\n const char *v8;\n int v9;\n long long result;\n const char **dest;\n long long v12;\n v4 = a2;\n if (a2 > 0 && a4 > 0) {\n v12 = 0LL;\n v5 = 0;\n v6 = &a3[a4];\n LABEL_4:\n while (2) {\n v7 = a3;\n dest = (const char **)(8 * v12 + a1);\n v8 = *dest;\n while (strcmp(v8, *v7)) {\n if (v6 == ++v7) {\n if (++v5 >= v4) goto LABEL_8;\n v12 = v5;\n goto LABEL_4;\n }\n }\n v9 = v4--;\n memmove(dest, (const void *)(a1 + 8 * v12 + 8), 8LL * (v9 - v5 - 1));\n if (v4 > v5) continue;\n break;\n }\n }\nLABEL_8:\n result = a1;\n *(uint64_t *)(a1 + 8LL * v4) = 0LL;\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, const char **a3, int a4) {\n int v4;\n int v5;\n const char **v6;\n const char **v7;\n const char *v8;\n int v9;\n long long result;\n const char **dest;\n long long v12;\n v4 = a2;\n if (a2 > 0 && a4 > 0) {\n v12 = 0LL;\n v5 = 0;\n v6 = &a3[a4];\n LABEL_4:\n while (2) {\n v7 = a3;\n dest = (const char **)(8 * v12 + a1);\n v8 = *dest;\n while (strcmp(v8, *v7)) {\n if (v6 == ++v7) {\n if (++v5 >= v4) goto LABEL_8;\n v12 = v5;\n goto LABEL_4;\n }\n }\n v9 = v4--;\n memmove(dest, (const void *)(a1 + 8 * v12 + 8), 8LL * (v9 - v5 - 1));\n if (v4 > v5) continue;\n break;\n }\n }\nLABEL_8:\n result = a1;\n *(uint64_t *)(a1 + 8LL * v4) = 0LL;\n return result;\n}" + }, + { + "index": 507, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(char *list1[], int list1_size, char *removewords[],\n int removewords_size) {\n int i, j;\n for (i = 0; i < list1_size; i++) {\n for (j = 0; j < removewords_size; j++) {\n if (strcmp(list1[i], removewords[j]) == 0) {\n memmove(&list1[i], &list1[i + 1],\n (list1_size - i - 1) * sizeof(char *));\n list1_size--;\n i--;\n break;\n }\n }\n }\n list1[list1_size] = NULL;\n}", + "test": "int main() {\n\n char *test_list1[] = {\"red\", \"green\", \"blue\", \"white\", \"black\", \"orange\", NULL};\n\n char *remove1[] = {\"white\", \"orange\", NULL};\n\n char *expected1[] = {\"red\", \"green\", \"blue\", \"black\", NULL};\n\n\n\n char *test_list2[] = {\"red\", \"green\", \"blue\", \"white\", \"black\", \"orange\", NULL};\n\n char *remove2[] = {\"black\", \"orange\", NULL};\n\n char *expected2[] = {\"red\", \"green\", \"blue\", \"white\", NULL};\n\n\n\n char *test_list3[] = {\"red\", \"green\", \"blue\", \"white\", \"black\", \"orange\", NULL};\n\n char *remove3[] = {\"blue\", \"white\", NULL};\n\n char *expected3[] = {\"red\", \"green\", \"black\", \"orange\", NULL};\n\n\n\n func0(test_list1, 6, remove1, 2);\n\n for (int i = 0; test_list1[i] != NULL; i++) {\n\n assert(strcmp(test_list1[i], expected1[i]) == 0);\n\n }\n\n\n\n func0(test_list2, 6, remove2, 2);\n\n for (int i = 0; test_list2[i] != NULL; i++) {\n\n assert(strcmp(test_list2[i], expected2[i]) == 0);\n\n }\n\n\n\n func0(test_list3, 6, remove3, 2);\n\n for (int i = 0; test_list3[i] != NULL; i++) {\n\n assert(strcmp(test_list3[i], expected3[i]) == 0);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\nmov %esi,%r14d\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x28,%rsp\nmov %rdi,(%rsp)\nmov %rdx,0x18(%rsp)\nmov %ecx,0x14(%rsp)\ntest %esi,%esi\njle 1688 \nmov %ecx,%eax\nxor %r13d,%r13d\nsub $0x1,%eax\nlea 0x8(%rdx,%rax,8),%rbp\nnopw 0x0(%rax,%rax,1)\nmov 0x14(%rsp),%eax\ntest %eax,%eax\njle 16b0 \nmovslq %r13d,%r12\nmov (%rsp),%r15\nlea 0x0(,%r12,8),%rax\nmov 0x18(%rsp),%r12\nadd %rax,%r15\nmov %rax,0x8(%rsp)\nmov (%r15),%rbx\njmp 1649 \nnopl (%rax)\nadd $0x8,%r12\ncmp %rbp,%r12\nje 16b0 \nmov (%r12),%rsi\nmov %rbx,%rdi\ncallq 10a0 \ntest %eax,%eax\njne 1640 \nmov %r14d,%edx\nmov (%rsp),%rax\nmov 0x8(%rsp),%rcx\nmov %r15,%rdi\nsub %r13d,%edx\nsub $0x1,%r14d\nsub $0x1,%edx\nlea 0x8(%rax,%rcx,1),%rsi\nmovslq %edx,%rdx\nshl $0x3,%rdx\ncallq 10b0 \ncmp %r13d,%r14d\njg 1610 \nmov (%rsp),%rax\nmovslq %r14d,%r14\nmovq $0x0,(%rax,%r14,8)\nadd $0x28,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw %cs:0x0(%rax,%rax,1)\nadd $0x1,%r13d\njmp 1683 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12d, esi\npush rbp\npush rbx\nsub rsp, 28h\nmov [rsp+58h+var_58], rdi\nmov [rsp+58h+var_40], rdx\ntest esi, esi\njle loc_15F4\ntest ecx, ecx\njle loc_15F4\nmov [rsp+58h+var_48], 0\nmovsxd rcx, ecx\nxor r13d, r13d\nlea rbp, [rdx+rcx*8]\nnop dword ptr [rax+00000000h]\nloc_1588:\nmov rax, [rsp+58h+var_48]\nmov r14, [rsp+58h+var_40]\nlea r15, ds:0[rax*8]\nmov rax, [rsp+58h+var_58]\nadd rax, r15\nmov [rsp+58h+dest], rax\nmov rbx, [rax]\njmp short loc_15B9\nloc_15B0:\nadd r14, 8\ncmp rbp, r14\njz short loc_1618\nloc_15B9:\nmov rsi, [r14]; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_15B0\nmov edx, r12d\nmov rax, [rsp+58h+var_58]\nmov rdi, [rsp+58h+dest]; dest\nsub r12d, 1\nsub edx, r13d\nsub edx, 1\nlea rsi, [rax+r15+8]; src\nmovsxd rdx, edx\nshl rdx, 3; n\ncall _memmove\ncmp r13d, r12d\njl short loc_1588\nloc_15F4:\nmov rax, [rsp+58h+var_58]\nmovsxd r12, r12d\nmov qword ptr [rax+r12*8], 0\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1618:\nadd r13d, 1\ncmp r12d, r13d\njle short loc_15F4\nmovsxd rax, r13d\nmov [rsp+58h+var_48], rax\njmp loc_1588", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, const char **a3, int a4)\n{\n int v4; // r12d\n int v5; // r13d\n const char **v6; // rbp\n const char **v7; // r14\n const char *v8; // rbx\n int v9; // edx\n __int64 result; // rax\n const char **dest; // [rsp+8h] [rbp-50h]\n __int64 v12; // [rsp+10h] [rbp-48h]\n\n v4 = a2;\n if ( a2 > 0 && a4 > 0 )\n {\n v12 = 0LL;\n v5 = 0;\n v6 = &a3[a4];\nLABEL_4:\n while ( 2 )\n {\n v7 = a3;\n dest = (const char **)(8 * v12 + a1);\n v8 = *dest;\n while ( strcmp(v8, *v7) )\n {\n if ( v6 == ++v7 )\n {\n if ( v4 <= ++v5 )\n goto LABEL_8;\n v12 = v5;\n goto LABEL_4;\n }\n }\n v9 = v4--;\n memmove(dest, (const void *)(a1 + 8 * v12 + 8), 8LL * (v9 - v5 - 1));\n if ( v5 < v4 )\n continue;\n break;\n }\n }\nLABEL_8:\n result = a1;\n *(_QWORD *)(a1 + 8LL * v4) = 0LL;\n return result;\n}", + "ida_strip_asm": "sub_1540:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12d, esi\npush rbp\npush rbx\nsub rsp, 28h\nmov [rsp+58h+var_58], rdi\nmov [rsp+58h+var_40], rdx\ntest esi, esi\njle loc_15F4\ntest ecx, ecx\njle loc_15F4\nmov [rsp+58h+var_48], 0\nmovsxd rcx, ecx\nxor r13d, r13d\nlea rbp, [rdx+rcx*8]\nnop dword ptr [rax+00000000h]\nloc_1588:\nmov rax, [rsp+58h+var_48]\nmov r14, [rsp+58h+var_40]\nlea r15, ds:0[rax*8]\nmov rax, [rsp+58h+var_58]\nadd rax, r15\nmov [rsp+58h+dest], rax\nmov rbx, [rax]\njmp short loc_15B9\nloc_15B0:\nadd r14, 8\ncmp rbp, r14\njz short loc_1618\nloc_15B9:\nmov rsi, [r14]; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_15B0\nmov edx, r12d\nmov rax, [rsp+58h+var_58]\nmov rdi, [rsp+58h+dest]; dest\nsub r12d, 1\nsub edx, r13d\nsub edx, 1\nlea rsi, [rax+r15+8]; src\nmovsxd rdx, edx\nshl rdx, 3; n\ncall _memmove\ncmp r13d, r12d\njl short loc_1588\nloc_15F4:\nmov rax, [rsp+58h+var_58]\nmovsxd r12, r12d\nmov qword ptr [rax+r12*8], 0\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1618:\nadd r13d, 1\ncmp r12d, r13d\njle short loc_15F4\nmovsxd rax, r13d\nmov [rsp+58h+var_48], rax\njmp loc_1588", + "ida_strip_pseudo": "__int64 __fastcall sub_1540(__int64 a1, int a2, const char **a3, int a4)\n{\n int v4; // r12d\n int v5; // r13d\n const char **v6; // rbp\n const char **v7; // r14\n const char *v8; // rbx\n int v9; // edx\n __int64 result; // rax\n const char **dest; // [rsp+8h] [rbp-50h]\n __int64 v12; // [rsp+10h] [rbp-48h]\n\n v4 = a2;\n if ( a2 > 0 && a4 > 0 )\n {\n v12 = 0LL;\n v5 = 0;\n v6 = &a3[a4];\nLABEL_4:\n while ( 2 )\n {\n v7 = a3;\n dest = (const char **)(8 * v12 + a1);\n v8 = *dest;\n while ( strcmp(v8, *v7) )\n {\n if ( v6 == ++v7 )\n {\n if ( v4 <= ++v5 )\n goto LABEL_8;\n v12 = v5;\n goto LABEL_4;\n }\n }\n v9 = v4--;\n memmove(dest, (const void *)(a1 + 8 * v12 + 8), 8LL * (v9 - v5 - 1));\n if ( v5 < v4 )\n continue;\n break;\n }\n }\nLABEL_8:\n result = a1;\n *(_QWORD *)(a1 + 8LL * v4) = 0LL;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1540(long long a1, int a2, const char **a3, int a4) {\n int v4;\n int v5;\n const char **v6;\n const char **v7;\n const char *v8;\n int v9;\n long long result;\n const char **dest;\n long long v12;\n v4 = a2;\n if (a2 > 0 && a4 > 0) {\n v12 = 0LL;\n v5 = 0;\n v6 = &a3[a4];\n LABEL_4:\n while (2) {\n v7 = a3;\n dest = (const char **)(8 * v12 + a1);\n v8 = *dest;\n while (strcmp(v8, *v7)) {\n if (v6 == ++v7) {\n if (v4 <= ++v5) goto LABEL_8;\n v12 = v5;\n goto LABEL_4;\n }\n }\n v9 = v4--;\n memmove(dest, (const void *)(a1 + 8 * v12 + 8), 8LL * (v9 - v5 - 1));\n if (v5 < v4) continue;\n break;\n }\n }\nLABEL_8:\n result = a1;\n *(uint64_t *)(a1 + 8LL * v4) = 0LL;\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, const char **a3, int a4) {\n int v4;\n int v5;\n const char **v6;\n const char **v7;\n const char *v8;\n int v9;\n long long result;\n const char **dest;\n long long v12;\n v4 = a2;\n if (a2 > 0 && a4 > 0) {\n v12 = 0LL;\n v5 = 0;\n v6 = &a3[a4];\n LABEL_4:\n while (2) {\n v7 = a3;\n dest = (const char **)(8 * v12 + a1);\n v8 = *dest;\n while (strcmp(v8, *v7)) {\n if (v6 == ++v7) {\n if (v4 <= ++v5) goto LABEL_8;\n v12 = v5;\n goto LABEL_4;\n }\n }\n v9 = v4--;\n memmove(dest, (const void *)(a1 + 8 * v12 + 8), 8LL * (v9 - v5 - 1));\n if (v5 < v4) continue;\n break;\n }\n }\nLABEL_8:\n result = a1;\n *(uint64_t *)(a1 + 8LL * v4) = 0LL;\n return result;\n}" + }, + { + "index": 508, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(char *l1[], char *l2[], int size1, int size2) {\n int common_elements_size = 0;\n char *common_elements[100];\n for (int i = 0; i < size1; i++) {\n for (int j = 0; j < size2; j++) {\n if (strcmp(l1[i], l2[j]) == 0) {\n bool is_unique = true;\n for (int k = 0; k < common_elements_size; k++) {\n if (strcmp(common_elements[k], l1[i]) == 0) {\n is_unique = false;\n break;\n }\n }\n if (is_unique) {\n common_elements[common_elements_size++] = l1[i];\n }\n }\n }\n }\n int index1 = 0;\n int index2 = 0;\n char *ordered_l1[100];\n char *ordered_l2[100];\n for (int i = 0; i < size1; i++) {\n for (int j = 0; j < common_elements_size; j++) {\n if (strcmp(l1[i], common_elements[j]) == 0) {\n ordered_l1[index1++] = l1[i];\n }\n }\n }\n for (int i = 0; i < size2; i++) {\n for (int j = 0; j < common_elements_size; j++) {\n if (strcmp(l2[i], common_elements[j]) == 0) {\n ordered_l2[index2++] = l2[i];\n }\n }\n }\n if (index1 != index2) {\n return false;\n }\n for (int i = 0; i < index1; i++) {\n if (strcmp(ordered_l1[i], ordered_l2[i]) != 0) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n char *list1a[] = {\"red\", \"green\", \"black\", \"orange\"};\n\n char *list2a[] = {\"red\", \"pink\", \"green\", \"white\", \"black\"};\n\n char *list1b[] = {\"red\", \"pink\", \"green\", \"white\", \"black\"};\n\n char *list2b[] = {\"white\", \"orange\", \"pink\", \"black\"};\n\n char *list1c[] = {\"red\", \"green\", \"black\", \"orange\"};\n\n char *list2c[] = {\"red\", \"pink\", \"green\", \"white\", \"black\"};\n\n\n\n assert(func0(list1a, list2a, 4, 5) == true);\n\n assert(func0(list1b, list2b, 5, 4) == false);\n\n assert(func0(list1c, list2c, 4, 5) == true);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x9c0,%rsp\nmov %rdi,-0x9a8(%rbp)\nmov %rsi,-0x9b0(%rbp)\nmov %edx,-0x9b4(%rbp)\nmov %ecx,-0x9b8(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovl $0x0,-0x99c(%rbp)\nmovl $0x0,-0x998(%rbp)\njmpq 1323 \nmovl $0x0,-0x994(%rbp)\njmpq 130a \nmov -0x994(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x9b0(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rdx\nmov -0x998(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x9a8(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10b0 \ntest %eax,%eax\njne 1303 \nmovb $0x1,-0x99d(%rbp)\nmovl $0x0,-0x990(%rbp)\njmp 12b5 \nmov -0x998(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x9a8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rdx\nmov -0x990(%rbp),%eax\ncltq\nmov -0x970(%rbp,%rax,8),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10b0 \ntest %eax,%eax\njne 12ae \nmovb $0x0,-0x99d(%rbp)\njmp 12c3 \naddl $0x1,-0x990(%rbp)\nmov -0x990(%rbp),%eax\ncmp -0x99c(%rbp),%eax\njl 1269 \ncmpb $0x0,-0x99d(%rbp)\nje 1303 \nmov -0x998(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x9a8(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x99c(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x99c(%rbp)\nmov (%rcx),%rdx\ncltq\nmov %rdx,-0x970(%rbp,%rax,8)\naddl $0x1,-0x994(%rbp)\nmov -0x994(%rbp),%eax\ncmp -0x9b8(%rbp),%eax\njl 1209 \naddl $0x1,-0x998(%rbp)\nmov -0x998(%rbp),%eax\ncmp -0x9b4(%rbp),%eax\njl 11fa \nmovl $0x0,-0x98c(%rbp)\nmovl $0x0,-0x988(%rbp)\nmovl $0x0,-0x984(%rbp)\njmpq 13f7 \nmovl $0x0,-0x980(%rbp)\njmp 13de \nmov -0x980(%rbp),%eax\ncltq\nmov -0x970(%rbp,%rax,8),%rdx\nmov -0x984(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x9a8(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10b0 \ntest %eax,%eax\njne 13d7 \nmov -0x984(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x9a8(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x98c(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x98c(%rbp)\nmov (%rcx),%rdx\ncltq\nmov %rdx,-0x650(%rbp,%rax,8)\naddl $0x1,-0x980(%rbp)\nmov -0x980(%rbp),%eax\ncmp -0x99c(%rbp),%eax\njl 1364 \naddl $0x1,-0x984(%rbp)\nmov -0x984(%rbp),%eax\ncmp -0x9b4(%rbp),%eax\njl 1358 \nmovl $0x0,-0x97c(%rbp)\njmpq 14b7 \nmovl $0x0,-0x978(%rbp)\njmp 149e \nmov -0x978(%rbp),%eax\ncltq\nmov -0x970(%rbp,%rax,8),%rdx\nmov -0x97c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x9b0(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10b0 \ntest %eax,%eax\njne 1497 \nmov -0x97c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x9b0(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x988(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x988(%rbp)\nmov (%rcx),%rdx\ncltq\nmov %rdx,-0x330(%rbp,%rax,8)\naddl $0x1,-0x978(%rbp)\nmov -0x978(%rbp),%eax\ncmp -0x99c(%rbp),%eax\njl 1424 \naddl $0x1,-0x97c(%rbp)\nmov -0x97c(%rbp),%eax\ncmp -0x9b8(%rbp),%eax\njl 1418 \nmov -0x98c(%rbp),%eax\ncmp -0x988(%rbp),%eax\nje 14de \nmov $0x0,%eax\njmp 153a \nmovl $0x0,-0x974(%rbp)\njmp 1527 \nmov -0x974(%rbp),%eax\ncltq\nmov -0x330(%rbp,%rax,8),%rdx\nmov -0x974(%rbp),%eax\ncltq\nmov -0x650(%rbp,%rax,8),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10b0 \ntest %eax,%eax\nje 1520 \nmov $0x0,%eax\njmp 153a \naddl $0x1,-0x974(%rbp)\nmov -0x974(%rbp),%eax\ncmp -0x98c(%rbp),%eax\njl 14ea \nmov $0x1,%eax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 154e \ncallq 1090 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 9C0h\nmov [rbp+var_9A8], rdi\nmov [rbp+var_9B0], rsi\nmov [rbp+var_9B4], edx\nmov [rbp+var_9B8], ecx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_99C], 0\nmov [rbp+var_998], 0\njmp loc_1323\nloc_11FA:\nmov [rbp+var_994], 0\njmp loc_130A\nloc_1209:\nmov eax, [rbp+var_994]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_9B0]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_998]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_9A8]\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz loc_1303\nmov [rbp+var_99D], 1\nmov [rbp+var_990], 0\njmp short loc_12B5\nloc_1269:\nmov eax, [rbp+var_998]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_9A8]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_990]\ncdqe\nmov rax, [rbp+rax*8+s1]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_12AE\nmov [rbp+var_99D], 0\njmp short loc_12C3\nloc_12AE:\nadd [rbp+var_990], 1\nloc_12B5:\nmov eax, [rbp+var_990]\ncmp eax, [rbp+var_99C]\njl short loc_1269\nloc_12C3:\ncmp [rbp+var_99D], 0\njz short loc_1303\nmov eax, [rbp+var_998]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_9A8]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_99C]\nlea edx, [rax+1]\nmov [rbp+var_99C], edx\nmov rdx, [rcx]\ncdqe\nmov [rbp+rax*8+s1], rdx\nloc_1303:\nadd [rbp+var_994], 1\nloc_130A:\nmov eax, [rbp+var_994]\ncmp eax, [rbp+var_9B8]\njl loc_1209\nadd [rbp+var_998], 1\nloc_1323:\nmov eax, [rbp+var_998]\ncmp eax, [rbp+var_9B4]\njl loc_11FA\nmov [rbp+var_98C], 0\nmov [rbp+var_988], 0\nmov [rbp+var_984], 0\njmp loc_13F7\nloc_1358:\nmov [rbp+var_980], 0\njmp short loc_13DE\nloc_1364:\nmov eax, [rbp+var_980]\ncdqe\nmov rdx, [rbp+rax*8+s1]\nmov eax, [rbp+var_984]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_9A8]\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_13D7\nmov eax, [rbp+var_984]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_9A8]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_98C]\nlea edx, [rax+1]\nmov [rbp+var_98C], edx\nmov rdx, [rcx]\ncdqe\nmov [rbp+rax*8+var_650], rdx\nloc_13D7:\nadd [rbp+var_980], 1\nloc_13DE:\nmov eax, [rbp+var_980]\ncmp eax, [rbp+var_99C]\njl loc_1364\nadd [rbp+var_984], 1\nloc_13F7:\nmov eax, [rbp+var_984]\ncmp eax, [rbp+var_9B4]\njl loc_1358\nmov [rbp+var_97C], 0\njmp loc_14B7\nloc_1418:\nmov [rbp+var_978], 0\njmp short loc_149E\nloc_1424:\nmov eax, [rbp+var_978]\ncdqe\nmov rdx, [rbp+rax*8+s1]\nmov eax, [rbp+var_97C]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_9B0]\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1497\nmov eax, [rbp+var_97C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_9B0]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_988]\nlea edx, [rax+1]\nmov [rbp+var_988], edx\nmov rdx, [rcx]\ncdqe\nmov [rbp+rax*8+s2], rdx\nloc_1497:\nadd [rbp+var_978], 1\nloc_149E:\nmov eax, [rbp+var_978]\ncmp eax, [rbp+var_99C]\njl loc_1424\nadd [rbp+var_97C], 1\nloc_14B7:\nmov eax, [rbp+var_97C]\ncmp eax, [rbp+var_9B8]\njl loc_1418\nmov eax, [rbp+var_98C]\ncmp eax, [rbp+var_988]\njz short loc_14DE\nmov eax, 0\njmp short loc_153A\nloc_14DE:\nmov [rbp+var_974], 0\njmp short loc_1527\nloc_14EA:\nmov eax, [rbp+var_974]\ncdqe\nmov rdx, [rbp+rax*8+s2]\nmov eax, [rbp+var_974]\ncdqe\nmov rax, [rbp+rax*8+var_650]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_1520\nmov eax, 0\njmp short loc_153A\nloc_1520:\nadd [rbp+var_974], 1\nloc_1527:\nmov eax, [rbp+var_974]\ncmp eax, [rbp+var_98C]\njl short loc_14EA\nmov eax, 1\nloc_153A:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_154E\ncall ___stack_chk_fail\nlocret_154E:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3, int a4)\n{\n int v4; // eax\n int v5; // eax\n int v6; // eax\n char v10; // [rsp+23h] [rbp-99Dh]\n int v11; // [rsp+24h] [rbp-99Ch]\n int i; // [rsp+28h] [rbp-998h]\n int j; // [rsp+2Ch] [rbp-994h]\n int k; // [rsp+30h] [rbp-990h]\n int v15; // [rsp+34h] [rbp-98Ch]\n int v16; // [rsp+38h] [rbp-988h]\n int m; // [rsp+3Ch] [rbp-984h]\n int n; // [rsp+40h] [rbp-980h]\n int ii; // [rsp+44h] [rbp-97Ch]\n int jj; // [rsp+48h] [rbp-978h]\n int kk; // [rsp+4Ch] [rbp-974h]\n char *s1[302]; // [rsp+50h] [rbp-970h]\n\n s1[301] = (char *)__readfsqword(0x28u);\n v11 = 0;\n for ( i = 0; i < a3; ++i )\n {\n for ( j = 0; j < a4; ++j )\n {\n if ( !strcmp(*(const char **)(8LL * i + a1), *(const char **)(8LL * j + a2)) )\n {\n v10 = 1;\n for ( k = 0; k < v11; ++k )\n {\n if ( !strcmp(s1[k], *(const char **)(8LL * i + a1)) )\n {\n v10 = 0;\n break;\n }\n }\n if ( v10 )\n {\n v4 = v11++;\n s1[v4] = *(char **)(8LL * i + a1);\n }\n }\n }\n }\n v15 = 0;\n v16 = 0;\n for ( m = 0; m < a3; ++m )\n {\n for ( n = 0; n < v11; ++n )\n {\n if ( !strcmp(*(const char **)(8LL * m + a1), s1[n]) )\n {\n v5 = v15++;\n s1[v5 + 100] = *(char **)(8LL * m + a1);\n }\n }\n }\n for ( ii = 0; ii < a4; ++ii )\n {\n for ( jj = 0; jj < v11; ++jj )\n {\n if ( !strcmp(*(const char **)(8LL * ii + a2), s1[jj]) )\n {\n v6 = v16++;\n s1[v6 + 200] = *(char **)(8LL * ii + a2);\n }\n }\n }\n if ( v15 != v16 )\n return 0LL;\n for ( kk = 0; kk < v15; ++kk )\n {\n if ( strcmp(s1[kk + 100], s1[kk + 200]) )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 9C0h\nmov [rbp+var_9A8], rdi\nmov [rbp+var_9B0], rsi\nmov [rbp+var_9B4], edx\nmov [rbp+var_9B8], ecx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_99C], 0\nmov [rbp+var_998], 0\njmp loc_1323\nloc_11FA:\nmov [rbp+var_994], 0\njmp loc_130A\nloc_1209:\nmov eax, [rbp+var_994]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_9B0]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_998]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_9A8]\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz loc_1303\nmov [rbp+var_99D], 1\nmov [rbp+var_990], 0\njmp short loc_12B5\nloc_1269:\nmov eax, [rbp+var_998]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_9A8]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_990]\ncdqe\nmov rax, [rbp+rax*8+s1]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_12AE\nmov [rbp+var_99D], 0\njmp short loc_12C3\nloc_12AE:\nadd [rbp+var_990], 1\nloc_12B5:\nmov eax, [rbp+var_990]\ncmp eax, [rbp+var_99C]\njl short loc_1269\nloc_12C3:\ncmp [rbp+var_99D], 0\njz short loc_1303\nmov eax, [rbp+var_998]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_9A8]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_99C]\nlea edx, [rax+1]\nmov [rbp+var_99C], edx\nmov rdx, [rcx]\ncdqe\nmov [rbp+rax*8+s1], rdx\nloc_1303:\nadd [rbp+var_994], 1\nloc_130A:\nmov eax, [rbp+var_994]\ncmp eax, [rbp+var_9B8]\njl loc_1209\nadd [rbp+var_998], 1\nloc_1323:\nmov eax, [rbp+var_998]\ncmp eax, [rbp+var_9B4]\njl loc_11FA\nmov [rbp+var_98C], 0\nmov [rbp+var_988], 0\nmov [rbp+var_984], 0\njmp loc_13F7\nloc_1358:\nmov [rbp+var_980], 0\njmp short loc_13DE\nloc_1364:\nmov eax, [rbp+var_980]\ncdqe\nmov rdx, [rbp+rax*8+s1]\nmov eax, [rbp+var_984]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_9A8]\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_13D7\nmov eax, [rbp+var_984]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_9A8]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_98C]\nlea edx, [rax+1]\nmov [rbp+var_98C], edx\nmov rdx, [rcx]\ncdqe\nmov [rbp+rax*8+var_650], rdx\nloc_13D7:\nadd [rbp+var_980], 1\nloc_13DE:\nmov eax, [rbp+var_980]\ncmp eax, [rbp+var_99C]\njl loc_1364\nadd [rbp+var_984], 1\nloc_13F7:\nmov eax, [rbp+var_984]\ncmp eax, [rbp+var_9B4]\njl loc_1358\nmov [rbp+var_97C], 0\njmp loc_14B7\nloc_1418:\nmov [rbp+var_978], 0\njmp short loc_149E\nloc_1424:\nmov eax, [rbp+var_978]\ncdqe\nmov rdx, [rbp+rax*8+s1]\nmov eax, [rbp+var_97C]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_9B0]\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1497\nmov eax, [rbp+var_97C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_9B0]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_988]\nlea edx, [rax+1]\nmov [rbp+var_988], edx\nmov rdx, [rcx]\ncdqe\nmov [rbp+rax*8+s2], rdx\nloc_1497:\nadd [rbp+var_978], 1\nloc_149E:\nmov eax, [rbp+var_978]\ncmp eax, [rbp+var_99C]\njl loc_1424\nadd [rbp+var_97C], 1\nloc_14B7:\nmov eax, [rbp+var_97C]\ncmp eax, [rbp+var_9B8]\njl loc_1418\nmov eax, [rbp+var_98C]\ncmp eax, [rbp+var_988]\njz short loc_14DE\nmov eax, 0\njmp short loc_153A\nloc_14DE:\nmov [rbp+var_974], 0\njmp short loc_1527\nloc_14EA:\nmov eax, [rbp+var_974]\ncdqe\nmov rdx, [rbp+rax*8+s2]\nmov eax, [rbp+var_974]\ncdqe\nmov rax, [rbp+rax*8+var_650]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_1520\nmov eax, 0\njmp short loc_153A\nloc_1520:\nadd [rbp+var_974], 1\nloc_1527:\nmov eax, [rbp+var_974]\ncmp eax, [rbp+var_98C]\njl short loc_14EA\nmov eax, 1\nloc_153A:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_154E\ncall ___stack_chk_fail\nlocret_154E:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(__int64 a1, __int64 a2, int a3, int a4)\n{\n int v4; // eax\n int v5; // eax\n int v6; // eax\n char v10; // [rsp+23h] [rbp-99Dh]\n int v11; // [rsp+24h] [rbp-99Ch]\n int i; // [rsp+28h] [rbp-998h]\n int j; // [rsp+2Ch] [rbp-994h]\n int k; // [rsp+30h] [rbp-990h]\n int v15; // [rsp+34h] [rbp-98Ch]\n int v16; // [rsp+38h] [rbp-988h]\n int m; // [rsp+3Ch] [rbp-984h]\n int n; // [rsp+40h] [rbp-980h]\n int ii; // [rsp+44h] [rbp-97Ch]\n int jj; // [rsp+48h] [rbp-978h]\n int kk; // [rsp+4Ch] [rbp-974h]\n char *s1[302]; // [rsp+50h] [rbp-970h]\n\n s1[301] = (char *)__readfsqword(0x28u);\n v11 = 0;\n for ( i = 0; i < a3; ++i )\n {\n for ( j = 0; j < a4; ++j )\n {\n if ( !strcmp(*(const char **)(8LL * i + a1), *(const char **)(8LL * j + a2)) )\n {\n v10 = 1;\n for ( k = 0; k < v11; ++k )\n {\n if ( !strcmp(s1[k], *(const char **)(8LL * i + a1)) )\n {\n v10 = 0;\n break;\n }\n }\n if ( v10 )\n {\n v4 = v11++;\n s1[v4] = *(char **)(8LL * i + a1);\n }\n }\n }\n }\n v15 = 0;\n v16 = 0;\n for ( m = 0; m < a3; ++m )\n {\n for ( n = 0; n < v11; ++n )\n {\n if ( !strcmp(*(const char **)(8LL * m + a1), s1[n]) )\n {\n v5 = v15++;\n s1[v5 + 100] = *(char **)(8LL * m + a1);\n }\n }\n }\n for ( ii = 0; ii < a4; ++ii )\n {\n for ( jj = 0; jj < v11; ++jj )\n {\n if ( !strcmp(*(const char **)(8LL * ii + a2), s1[jj]) )\n {\n v6 = v16++;\n s1[v6 + 200] = *(char **)(8LL * ii + a2);\n }\n }\n }\n if ( v15 != v16 )\n return 0LL;\n for ( kk = 0; kk < v15; ++kk )\n {\n if ( strcmp(s1[kk + 100], s1[kk + 200]) )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(long long a1, long long a2, int a3, int a4) {\n int v4;\n int v5;\n int v6;\n char v10;\n int v11;\n int i;\n int j;\n int k;\n int v15;\n int v16;\n int m;\n int n;\n int ii;\n int jj;\n int kk;\n char *s1[302];\n s1[301] = (char *)__readfsqword(40u);\n v11 = 0;\n for (i = 0; i < a3; ++i) {\n for (j = 0; j < a4; ++j) {\n if (!strcmp(*(const char **)(8LL * i + a1),\n *(const char **)(8LL * j + a2))) {\n v10 = 1;\n for (k = 0; k < v11; ++k) {\n if (!strcmp(s1[k], *(const char **)(8LL * i + a1))) {\n v10 = 0;\n break;\n }\n }\n if (v10) {\n v4 = v11++;\n s1[v4] = *(char **)(8LL * i + a1);\n }\n }\n }\n }\n v15 = 0;\n v16 = 0;\n for (m = 0; m < a3; ++m) {\n for (n = 0; n < v11; ++n) {\n if (!strcmp(*(const char **)(8LL * m + a1), s1[n])) {\n v5 = v15++;\n s1[v5 + 100] = *(char **)(8LL * m + a1);\n }\n }\n }\n for (ii = 0; ii < a4; ++ii) {\n for (jj = 0; jj < v11; ++jj) {\n if (!strcmp(*(const char **)(8LL * ii + a2), s1[jj])) {\n v6 = v16++;\n s1[v6 + 200] = *(char **)(8LL * ii + a2);\n }\n }\n }\n if (v15 != v16) return 0LL;\n for (kk = 0; kk < v15; ++kk) {\n if (strcmp(s1[kk + 100], s1[kk + 200])) return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3, int a4) {\n int v4;\n int v5;\n int v6;\n char v10;\n int v11;\n int i;\n int j;\n int k;\n int v15;\n int v16;\n int m;\n int n;\n int ii;\n int jj;\n int kk;\n char *s1[302];\n s1[301] = (char *)__readfsqword(40u);\n v11 = 0;\n for (i = 0; i < a3; ++i) {\n for (j = 0; j < a4; ++j) {\n if (!strcmp(*(const char **)(8LL * i + a1),\n *(const char **)(8LL * j + a2))) {\n v10 = 1;\n for (k = 0; k < v11; ++k) {\n if (!strcmp(s1[k], *(const char **)(8LL * i + a1))) {\n v10 = 0;\n break;\n }\n }\n if (v10) {\n v4 = v11++;\n s1[v4] = *(char **)(8LL * i + a1);\n }\n }\n }\n }\n v15 = 0;\n v16 = 0;\n for (m = 0; m < a3; ++m) {\n for (n = 0; n < v11; ++n) {\n if (!strcmp(*(const char **)(8LL * m + a1), s1[n])) {\n v5 = v15++;\n s1[v5 + 100] = *(char **)(8LL * m + a1);\n }\n }\n }\n for (ii = 0; ii < a4; ++ii) {\n for (jj = 0; jj < v11; ++jj) {\n if (!strcmp(*(const char **)(8LL * ii + a2), s1[jj])) {\n v6 = v16++;\n s1[v6 + 200] = *(char **)(8LL * ii + a2);\n }\n }\n }\n if (v15 != v16) return 0LL;\n for (kk = 0; kk < v15; ++kk) {\n if (strcmp(s1[kk + 100], s1[kk + 200])) return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": 508, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(char *l1[], char *l2[], int size1, int size2) {\n int common_elements_size = 0;\n char *common_elements[100];\n for (int i = 0; i < size1; i++) {\n for (int j = 0; j < size2; j++) {\n if (strcmp(l1[i], l2[j]) == 0) {\n bool is_unique = true;\n for (int k = 0; k < common_elements_size; k++) {\n if (strcmp(common_elements[k], l1[i]) == 0) {\n is_unique = false;\n break;\n }\n }\n if (is_unique) {\n common_elements[common_elements_size++] = l1[i];\n }\n }\n }\n }\n int index1 = 0;\n int index2 = 0;\n char *ordered_l1[100];\n char *ordered_l2[100];\n for (int i = 0; i < size1; i++) {\n for (int j = 0; j < common_elements_size; j++) {\n if (strcmp(l1[i], common_elements[j]) == 0) {\n ordered_l1[index1++] = l1[i];\n }\n }\n }\n for (int i = 0; i < size2; i++) {\n for (int j = 0; j < common_elements_size; j++) {\n if (strcmp(l2[i], common_elements[j]) == 0) {\n ordered_l2[index2++] = l2[i];\n }\n }\n }\n if (index1 != index2) {\n return false;\n }\n for (int i = 0; i < index1; i++) {\n if (strcmp(ordered_l1[i], ordered_l2[i]) != 0) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n char *list1a[] = {\"red\", \"green\", \"black\", \"orange\"};\n\n char *list2a[] = {\"red\", \"pink\", \"green\", \"white\", \"black\"};\n\n char *list1b[] = {\"red\", \"pink\", \"green\", \"white\", \"black\"};\n\n char *list2b[] = {\"white\", \"orange\", \"pink\", \"black\"};\n\n char *list1c[] = {\"red\", \"green\", \"black\", \"orange\"};\n\n char *list2c[] = {\"red\", \"pink\", \"green\", \"white\", \"black\"};\n\n\n\n assert(func0(list1a, list2a, 4, 5) == true);\n\n assert(func0(list1b, list2b, 5, 4) == false);\n\n assert(func0(list1c, list2c, 4, 5) == true);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x9b8,%rsp\nmov %rsi,0x30(%rsp)\nmov %ecx,0x1c(%rsp)\nmov %fs:0x28,%rax\nmov %rax,0x9a8(%rsp)\nxor %eax,%eax\ntest %edx,%edx\njle 13b3 \nmov %rdi,0x8(%rsp)\nlea -0x1(%rdx),%eax\nlea 0x8(%rdi,%rax,8),%rax\nmov %rax,0x28(%rsp)\nmov 0x30(%rsp),%rdx\nmov %rdx,0x38(%rsp)\nmov 0x1c(%rsp),%eax\nlea -0x1(%rax),%eax\nlea 0x8(%rdx,%rax,8),%r15\nmov %rdi,0x10(%rsp)\nmov $0x0,%r14d\nlea 0x48(%rsp),%rax\nmov %rax,0x20(%rsp)\njmp 1233 \naddq $0x8,0x10(%rsp)\nmov 0x10(%rsp),%rax\ncmp 0x28(%rsp),%rax\nje 124c \ncmpl $0x0,0x1c(%rsp)\njle 1221 \nmov 0x10(%rsp),%rax\nmov (%rax),%r12\nmov 0x38(%rsp),%rbp\njmpq 13ed \nlea 0x40(%rsp),%r15\nlea -0x1(%r14),%eax\nlea 0x48(%rsp,%rax,8),%r13\nmov $0x0,%r12d\njmp 129e \nadd $0x8,%rbx\ncmp %r13,%rbx\nje 128c \nmov (%rbx),%rsi\nmov %rbp,%rdi\ncallq 10b0 \ntest %eax,%eax\njne 1262 \nmovslq %r12d,%rax\nmov %rbp,0x360(%rsp,%rax,8)\nlea 0x1(%r12),%r12d\njmp 1262 \naddq $0x8,0x8(%rsp)\nmov 0x8(%rsp),%rax\ncmp 0x28(%rsp),%rax\nje 12b0 \ntest %r14d,%r14d\njle 128c \nmov 0x8(%rsp),%rax\nmov (%rax),%rbp\nmov %r15,%rbx\njmp 126b \ncmpl $0x0,0x1c(%rsp)\njle 132f \nlea 0x40(%rsp),%rax\nmov %rax,0x10(%rsp)\nlea -0x1(%r14),%eax\nlea 0x48(%rsp,%rax,8),%r15\nmovq $0x0,0x8(%rsp)\nmov $0x0,%r13d\njmp 1315 \nadd $0x8,%rbx\ncmp %rbx,%r15\nje 1304 \nmov (%rbx),%rsi\nmov %rbp,%rdi\ncallq 10b0 \ntest %eax,%eax\njne 12db \nmovslq %r13d,%rax\nmov %rbp,0x680(%rsp,%rax,8)\nlea 0x1(%r13),%r13d\njmp 12db \naddq $0x1,0x8(%rsp)\nmov 0x8(%rsp),%rax\ncmp %eax,0x1c(%rsp)\njle 1335 \ntest %r14d,%r14d\njle 1304 \nmov 0x30(%rsp),%rax\nmov 0x8(%rsp),%rdx\nmov (%rax,%rdx,8),%rbp\nmov 0x10(%rsp),%rbx\njmp 12e4 \nmov $0x0,%r13d\nmov $0x0,%eax\ncmp %r13d,%r12d\nje 1368 \nmov 0x9a8(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 142e \nadd $0x9b8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\ntest %r12d,%r12d\njle 13a5 \nlea -0x1(%r12),%ebp\nmov $0x0,%ebx\njmp 137c \nmov %rax,%rbx\nmov 0x680(%rsp,%rbx,8),%rsi\nmov 0x360(%rsp,%rbx,8),%rdi\ncallq 10b0 \ntest %eax,%eax\njne 13ac \nlea 0x1(%rbx),%rax\ncmp %rbp,%rbx\njne 1379 \nmov $0x1,%eax\njmp 133f \nmov $0x1,%eax\njmp 133f \nmov $0x0,%eax\njmp 133f \nmov $0x0,%r12d\nmov $0x0,%r14d\nmov $0x1,%eax\ncmpl $0x0,0x1c(%rsp)\njg 12b7 \njmpq 133f \nmovslq %r14d,%rax\nmov %r12,0x40(%rsp,%rax,8)\nlea 0x1(%r14),%r14d\nadd $0x8,%rbp\ncmp %r15,%rbp\nje 1221 \nmov 0x0(%rbp),%rsi\nmov %r12,%rdi\ncallq 10b0 \ntest %eax,%eax\njne 13e0 \ntest %r14d,%r14d\njle 13d4 \nlea 0x40(%rsp),%rbx\nlea -0x1(%r14),%eax\nmov 0x20(%rsp),%rcx\nlea (%rcx,%rax,8),%r13\nmov %r12,%rsi\nmov (%rbx),%rdi\ncallq 10b0 \ntest %eax,%eax\nje 13e0 \nadd $0x8,%rbx\ncmp %r13,%rbx\njne 1414 \njmp 13d4 \ncallq 1090 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 9A8h\nmov rax, rdi\nmov [rsp+9D8h+var_9B0], rsi\nmov edi, ecx\nmov [rsp+9D8h+var_9B4], ecx\nmov rcx, fs:28h\nmov [rsp+9D8h+var_40], rcx\nxor ecx, ecx\ntest edx, edx\njle loc_12E9\nmov [rsp+9D8h+var_9D0], rax\nmovsxd rdx, edx\nlea rdx, [rax+rdx*8]\nmov [rsp+9D8h+var_9C0], rdx\nmovsxd rdx, edi\nlea r15, [rsi+rdx*8]\nmov [rsp+9D8h+var_9C8], rax\nmov r14d, 0\njmp short loc_1271\nloc_120C:\nmovsxd rax, r14d\nmov [rsp+rax*8+9D8h+var_9A8], r12\nlea r14d, [r14+1]\nloc_1218:\nadd rbp, 8\ncmp rbp, r15\njz short loc_125C\nloc_1221:\nmov rsi, [rbp+0]; s2\nmov rdi, r12; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1218\ntest r14d, r14d\njle short loc_120C\nlea rbx, [rsp+9D8h+var_9A8]\nmovsxd rax, r14d\nlea r13, [rbx+rax*8]\nloc_1242:\nmov rdi, [rbx]; s1\nmov rsi, r12; s2\ncall _strcmp\ntest eax, eax\njz short loc_1218\nadd rbx, 8\ncmp rbx, r13\njnz short loc_1242\njmp short loc_120C\nloc_125C:\nadd [rsp+9D8h+var_9C8], 8\nmov rax, [rsp+9D8h+var_9C8]\nmov rcx, [rsp+9D8h+var_9C0]\ncmp rax, rcx\njz short loc_1287\nloc_1271:\ncmp [rsp+9D8h+var_9B4], 0\njle short loc_125C\nmov rax, [rsp+9D8h+var_9C8]\nmov r12, [rax]\nmov rbp, [rsp+9D8h+var_9B0]\njmp short loc_1221\nloc_1287:\nlea r15, [rsp+9D8h+var_9A8]\nmovsxd rax, r14d\nlea r13, [r15+rax*8]\nmov ebp, 0\njmp short loc_12D7\nloc_129A:\nadd rbx, 8\ncmp r13, rbx\njz short loc_12C2\nloc_12A3:\nmov rsi, [rbx]; s2\nmov rdi, r12; s1\ncall _strcmp\ntest eax, eax\njnz short loc_129A\nmovsxd rax, ebp\nmov [rsp+rax*8+9D8h+s1], r12\nlea ebp, [rbp+1]\njmp short loc_129A\nloc_12C2:\nadd [rsp+9D8h+var_9D0], 8\nmov rax, [rsp+9D8h+var_9D0]\nmov rdx, [rsp+9D8h+var_9C0]\ncmp rax, rdx\njz short loc_12F4\nloc_12D7:\ntest r14d, r14d\njle short loc_12C2\nmov rax, [rsp+9D8h+var_9D0]\nmov r12, [rax]\nmov rbx, r15\njmp short loc_12A3\nloc_12E9:\nmov r14d, 0\nmov ebp, 0\nloc_12F4:\nmov eax, [rsp+9D8h+var_9B4]\ntest eax, eax\njle loc_1380\nmov rdx, [rsp+9D8h+var_9B0]\nmov [rsp+9D8h+var_9D0], rdx\ncdqe\nlea rax, [rdx+rax*8]\nmov [rsp+9D8h+var_9C8], rax\nlea rdx, [rsp+9D8h+var_9A8]\nmov [rsp+9D8h+var_9C0], rdx\nmovsxd rax, r14d\nlea r15, [rdx+rax*8]\nmov r13d, 0\njmp short loc_136C\nloc_132E:\nadd rbx, 8\ncmp r15, rbx\njz short loc_1357\nloc_1337:\nmov rsi, [rbx]; s2\nmov rdi, r12; s1\ncall _strcmp\ntest eax, eax\njnz short loc_132E\nmovsxd rax, r13d\nmov [rsp+rax*8+9D8h+s2], r12\nlea r13d, [r13+1]\njmp short loc_132E\nloc_1357:\nadd [rsp+9D8h+var_9D0], 8\nmov rax, [rsp+9D8h+var_9D0]\nmov rcx, [rsp+9D8h+var_9C8]\ncmp rax, rcx\njz short loc_1386\nloc_136C:\ntest r14d, r14d\njle short loc_1357\nmov rax, [rsp+9D8h+var_9D0]\nmov r12, [rax]\nmov rbx, [rsp+9D8h+var_9C0]\njmp short loc_1337\nloc_1380:\nmov r13d, 0\nloc_1386:\nmov eax, 0\ncmp ebp, r13d\njnz short loc_13D5\ntest ebp, ebp\njle short loc_13C9\nmovsxd rbx, ebp\nshl rbx, 3\nmov ebp, 0\nloc_13A0:\nmov rsi, [rsp+rbp+9D8h+s2]; s2\nmov rdi, [rsp+rbp+9D8h+s1]; s1\ncall _strcmp\ntest eax, eax\njnz short loc_13D0\nadd rbp, 8\ncmp rbx, rbp\njnz short loc_13A0\nmov eax, 1\njmp short loc_13D5\nloc_13C9:\nmov eax, 1\njmp short loc_13D5\nloc_13D0:\nmov eax, 0\nloc_13D5:\nmov rdx, [rsp+9D8h+var_40]\nsub rdx, fs:28h\njnz short loc_13FA\nadd rsp, 9A8h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_13FA:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(char **a1, const char **a2, int a3, int a4)\n{\n const char **v4; // r15\n int v5; // r14d\n const char **v6; // rbp\n char **v7; // rbx\n char *v8; // r12\n int v9; // ebp\n char **v10; // rbx\n char *v11; // r12\n int v12; // r13d\n char **v13; // rbx\n char *v14; // r12\n __int64 result; // rax\n __int64 v16; // rbx\n unsigned __int64 v17; // rbp\n char **v18; // [rsp+8h] [rbp-9D0h]\n char **v19; // [rsp+8h] [rbp-9D0h]\n char **v20; // [rsp+10h] [rbp-9C8h]\n char **v21; // [rsp+18h] [rbp-9C0h]\n char *v23[309]; // [rsp+30h] [rbp-9A8h] BYREF\n\n v23[301] = (char *)__readfsqword(0x28u);\n if ( a3 <= 0 )\n {\n v5 = 0;\n v9 = 0;\n }\n else\n {\n v18 = a1;\n v21 = &a1[a3];\n v4 = &a2[a4];\n v20 = a1;\n v5 = 0;\n do\n {\n if ( a4 > 0 )\n {\n v8 = *v20;\n v6 = a2;\n do\n {\n if ( !strcmp(v8, *v6) )\n {\n if ( v5 <= 0 )\n {\nLABEL_3:\n v23[v5++] = v8;\n }\n else\n {\n v7 = v23;\n while ( strcmp(*v7, v8) )\n {\n if ( ++v7 == &v23[v5] )\n goto LABEL_3;\n }\n }\n }\n ++v6;\n }\n while ( v6 != v4 );\n }\n ++v20;\n }\n while ( v20 != v21 );\n v9 = 0;\n do\n {\n if ( v5 > 0 )\n {\n v11 = *v18;\n v10 = v23;\n do\n {\n if ( !strcmp(v11, *v10) )\n v23[v9++ + 100] = v11;\n ++v10;\n }\n while ( &v23[v5] != v10 );\n }\n ++v18;\n }\n while ( v18 != v21 );\n }\n if ( a4 <= 0 )\n {\n v12 = 0;\n }\n else\n {\n v19 = (char **)a2;\n v12 = 0;\n do\n {\n if ( v5 > 0 )\n {\n v14 = *v19;\n v13 = v23;\n do\n {\n if ( !strcmp(v14, *v13) )\n v23[v12++ + 200] = v14;\n ++v13;\n }\n while ( &v23[v5] != v13 );\n }\n ++v19;\n }\n while ( v19 != (char **)&a2[a4] );\n }\n result = 0LL;\n if ( v9 == v12 )\n {\n if ( v9 <= 0 )\n {\n return 1LL;\n }\n else\n {\n v16 = 8LL * v9;\n v17 = 0LL;\n while ( !strcmp(v23[v17 / 8 + 100], v23[v17 / 8 + 200]) )\n {\n v17 += 8LL;\n if ( v16 == v17 )\n return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 9A8h\nmov rax, rdi\nmov [rsp+9D8h+var_9B0], rsi\nmov edi, ecx\nmov [rsp+9D8h+var_9B4], ecx\nmov rcx, fs:28h\nmov [rsp+9D8h+var_40], rcx\nxor ecx, ecx\ntest edx, edx\njle loc_12E9\nmov [rsp+9D8h+var_9D0], rax\nmovsxd rdx, edx\nlea rdx, [rax+rdx*8]\nmov [rsp+9D8h+var_9C0], rdx\nmovsxd rdx, edi\nlea r15, [rsi+rdx*8]\nmov [rsp+9D8h+var_9C8], rax\nmov r14d, 0\njmp short loc_1271\nloc_120C:\nmovsxd rax, r14d\nmov [rsp+rax*8+9D8h+var_9A8], r12\nlea r14d, [r14+1]\nloc_1218:\nadd rbp, 8\ncmp rbp, r15\njz short loc_125C\nloc_1221:\nmov rsi, [rbp+0]; s2\nmov rdi, r12; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1218\ntest r14d, r14d\njle short loc_120C\nlea rbx, [rsp+9D8h+var_9A8]\nmovsxd rax, r14d\nlea r13, [rbx+rax*8]\nloc_1242:\nmov rdi, [rbx]; s1\nmov rsi, r12; s2\ncall _strcmp\ntest eax, eax\njz short loc_1218\nadd rbx, 8\ncmp rbx, r13\njnz short loc_1242\njmp short loc_120C\nloc_125C:\nadd [rsp+9D8h+var_9C8], 8\nmov rax, [rsp+9D8h+var_9C8]\nmov rcx, [rsp+9D8h+var_9C0]\ncmp rax, rcx\njz short loc_1287\nloc_1271:\ncmp [rsp+9D8h+var_9B4], 0\njle short loc_125C\nmov rax, [rsp+9D8h+var_9C8]\nmov r12, [rax]\nmov rbp, [rsp+9D8h+var_9B0]\njmp short loc_1221\nloc_1287:\nlea r15, [rsp+9D8h+var_9A8]\nmovsxd rax, r14d\nlea r13, [r15+rax*8]\nmov ebp, 0\njmp short loc_12D7\nloc_129A:\nadd rbx, 8\ncmp r13, rbx\njz short loc_12C2\nloc_12A3:\nmov rsi, [rbx]; s2\nmov rdi, r12; s1\ncall _strcmp\ntest eax, eax\njnz short loc_129A\nmovsxd rax, ebp\nmov [rsp+rax*8+9D8h+s1], r12\nlea ebp, [rbp+1]\njmp short loc_129A\nloc_12C2:\nadd [rsp+9D8h+var_9D0], 8\nmov rax, [rsp+9D8h+var_9D0]\nmov rdx, [rsp+9D8h+var_9C0]\ncmp rax, rdx\njz short loc_12F4\nloc_12D7:\ntest r14d, r14d\njle short loc_12C2\nmov rax, [rsp+9D8h+var_9D0]\nmov r12, [rax]\nmov rbx, r15\njmp short loc_12A3\nloc_12E9:\nmov r14d, 0\nmov ebp, 0\nloc_12F4:\nmov eax, [rsp+9D8h+var_9B4]\ntest eax, eax\njle loc_1380\nmov rdx, [rsp+9D8h+var_9B0]\nmov [rsp+9D8h+var_9D0], rdx\ncdqe\nlea rax, [rdx+rax*8]\nmov [rsp+9D8h+var_9C8], rax\nlea rdx, [rsp+9D8h+var_9A8]\nmov [rsp+9D8h+var_9C0], rdx\nmovsxd rax, r14d\nlea r15, [rdx+rax*8]\nmov r13d, 0\njmp short loc_136C\nloc_132E:\nadd rbx, 8\ncmp r15, rbx\njz short loc_1357\nloc_1337:\nmov rsi, [rbx]; s2\nmov rdi, r12; s1\ncall _strcmp\ntest eax, eax\njnz short loc_132E\nmovsxd rax, r13d\nmov [rsp+rax*8+9D8h+s2], r12\nlea r13d, [r13+1]\njmp short loc_132E\nloc_1357:\nadd [rsp+9D8h+var_9D0], 8\nmov rax, [rsp+9D8h+var_9D0]\nmov rcx, [rsp+9D8h+var_9C8]\ncmp rax, rcx\njz short loc_1386\nloc_136C:\ntest r14d, r14d\njle short loc_1357\nmov rax, [rsp+9D8h+var_9D0]\nmov r12, [rax]\nmov rbx, [rsp+9D8h+var_9C0]\njmp short loc_1337\nloc_1380:\nmov r13d, 0\nloc_1386:\nmov eax, 0\ncmp ebp, r13d\njnz short loc_13D5\ntest ebp, ebp\njle short loc_13C9\nmovsxd rbx, ebp\nshl rbx, 3\nmov ebp, 0\nloc_13A0:\nmov rsi, [rsp+rbp+9D8h+s2]; s2\nmov rdi, [rsp+rbp+9D8h+s1]; s1\ncall _strcmp\ntest eax, eax\njnz short loc_13D0\nadd rbp, 8\ncmp rbx, rbp\njnz short loc_13A0\nmov eax, 1\njmp short loc_13D5\nloc_13C9:\nmov eax, 1\njmp short loc_13D5\nloc_13D0:\nmov eax, 0\nloc_13D5:\nmov rdx, [rsp+9D8h+var_40]\nsub rdx, fs:28h\njnz short loc_13FA\nadd rsp, 9A8h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_13FA:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(char **a1, const char **a2, int a3, int a4)\n{\n const char **v4; // r15\n int v5; // r14d\n const char **v6; // rbp\n char **v7; // rbx\n char *v8; // r12\n int v9; // ebp\n char **v10; // rbx\n char *v11; // r12\n int v12; // r13d\n char **v13; // rbx\n char *v14; // r12\n __int64 result; // rax\n __int64 v16; // rbx\n unsigned __int64 v17; // rbp\n char **v18; // [rsp+8h] [rbp-9D0h]\n char **v19; // [rsp+8h] [rbp-9D0h]\n char **v20; // [rsp+10h] [rbp-9C8h]\n char **v21; // [rsp+18h] [rbp-9C0h]\n char *v23[309]; // [rsp+30h] [rbp-9A8h] BYREF\n\n v23[301] = (char *)__readfsqword(0x28u);\n if ( a3 <= 0 )\n {\n v5 = 0;\n v9 = 0;\n }\n else\n {\n v18 = a1;\n v21 = &a1[a3];\n v4 = &a2[a4];\n v20 = a1;\n v5 = 0;\n do\n {\n if ( a4 > 0 )\n {\n v8 = *v20;\n v6 = a2;\n do\n {\n if ( !strcmp(v8, *v6) )\n {\n if ( v5 <= 0 )\n {\nLABEL_3:\n v23[v5++] = v8;\n }\n else\n {\n v7 = v23;\n while ( strcmp(*v7, v8) )\n {\n if ( ++v7 == &v23[v5] )\n goto LABEL_3;\n }\n }\n }\n ++v6;\n }\n while ( v6 != v4 );\n }\n ++v20;\n }\n while ( v20 != v21 );\n v9 = 0;\n do\n {\n if ( v5 > 0 )\n {\n v11 = *v18;\n v10 = v23;\n do\n {\n if ( !strcmp(v11, *v10) )\n v23[v9++ + 100] = v11;\n ++v10;\n }\n while ( &v23[v5] != v10 );\n }\n ++v18;\n }\n while ( v18 != v21 );\n }\n if ( a4 <= 0 )\n {\n v12 = 0;\n }\n else\n {\n v19 = (char **)a2;\n v12 = 0;\n do\n {\n if ( v5 > 0 )\n {\n v14 = *v19;\n v13 = v23;\n do\n {\n if ( !strcmp(v14, *v13) )\n v23[v12++ + 200] = v14;\n ++v13;\n }\n while ( &v23[v5] != v13 );\n }\n ++v19;\n }\n while ( v19 != (char **)&a2[a4] );\n }\n result = 0LL;\n if ( v9 == v12 )\n {\n if ( v9 <= 0 )\n {\n return 1LL;\n }\n else\n {\n v16 = 8LL * v9;\n v17 = 0LL;\n while ( !strcmp(v23[v17 / 8 + 100], v23[v17 / 8 + 200]) )\n {\n v17 += 8LL;\n if ( v16 == v17 )\n return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(char **a1, const char **a2, int a3, int a4) {\n const char **v4;\n int v5;\n const char **v6;\n char **v7;\n char *v8;\n int v9;\n char **v10;\n char *v11;\n int v12;\n char **v13;\n char *v14;\n long long result;\n long long v16;\n unsigned long long v17;\n char **v18;\n char **v19;\n char **v20;\n char **v21;\n char *v23[309];\n v23[301] = (char *)__readfsqword(40u);\n if (a3 <= 0) {\n v5 = 0;\n v9 = 0;\n } else {\n v18 = a1;\n v21 = &a1[a3];\n v4 = &a2[a4];\n v20 = a1;\n v5 = 0;\n do {\n if (a4 > 0) {\n v8 = *v20;\n v6 = a2;\n do {\n if (!strcmp(v8, *v6)) {\n if (v5 <= 0) {\n LABEL_3:\n v23[v5++] = v8;\n } else {\n v7 = v23;\n while (strcmp(*v7, v8)) {\n if (++v7 == &v23[v5]) goto LABEL_3;\n }\n }\n }\n ++v6;\n } while (v6 != v4);\n }\n ++v20;\n } while (v20 != v21);\n v9 = 0;\n do {\n if (v5 > 0) {\n v11 = *v18;\n v10 = v23;\n do {\n if (!strcmp(v11, *v10)) v23[v9++ + 100] = v11;\n ++v10;\n } while (&v23[v5] != v10);\n }\n ++v18;\n } while (v18 != v21);\n }\n if (a4 <= 0) {\n v12 = 0;\n } else {\n v19 = (char **)a2;\n v12 = 0;\n do {\n if (v5 > 0) {\n v14 = *v19;\n v13 = v23;\n do {\n if (!strcmp(v14, *v13)) v23[v12++ + 200] = v14;\n ++v13;\n } while (&v23[v5] != v13);\n }\n ++v19;\n } while (v19 != (char **)&a2[a4]);\n }\n result = 0LL;\n if (v9 == v12) {\n if (v9 <= 0) {\n return 1LL;\n } else {\n v16 = 8LL * v9;\n v17 = 0LL;\n while (!strcmp(v23[v17 / 8 + 100], v23[v17 / 8 + 200])) {\n v17 += 8LL;\n if (v16 == v17) return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(char **a1, const char **a2, int a3, int a4) {\n const char **v4;\n int v5;\n const char **v6;\n char **v7;\n char *v8;\n int v9;\n char **v10;\n char *v11;\n int v12;\n char **v13;\n char *v14;\n long long result;\n long long v16;\n unsigned long long v17;\n char **v18;\n char **v19;\n char **v20;\n char **v21;\n char *v23[309];\n v23[301] = (char *)__readfsqword(40u);\n if (a3 <= 0) {\n v5 = 0;\n v9 = 0;\n } else {\n v18 = a1;\n v21 = &a1[a3];\n v4 = &a2[a4];\n v20 = a1;\n v5 = 0;\n do {\n if (a4 > 0) {\n v8 = *v20;\n v6 = a2;\n do {\n if (!strcmp(v8, *v6)) {\n if (v5 <= 0) {\n LABEL_3:\n v23[v5++] = v8;\n } else {\n v7 = v23;\n while (strcmp(*v7, v8)) {\n if (++v7 == &v23[v5]) goto LABEL_3;\n }\n }\n }\n ++v6;\n } while (v6 != v4);\n }\n ++v20;\n } while (v20 != v21);\n v9 = 0;\n do {\n if (v5 > 0) {\n v11 = *v18;\n v10 = v23;\n do {\n if (!strcmp(v11, *v10)) v23[v9++ + 100] = v11;\n ++v10;\n } while (&v23[v5] != v10);\n }\n ++v18;\n } while (v18 != v21);\n }\n if (a4 <= 0) {\n v12 = 0;\n } else {\n v19 = (char **)a2;\n v12 = 0;\n do {\n if (v5 > 0) {\n v14 = *v19;\n v13 = v23;\n do {\n if (!strcmp(v14, *v13)) v23[v12++ + 200] = v14;\n ++v13;\n } while (&v23[v5] != v13);\n }\n ++v19;\n } while (v19 != (char **)&a2[a4]);\n }\n result = 0LL;\n if (v9 == v12) {\n if (v9 <= 0) {\n return 1LL;\n } else {\n v16 = 8LL * v9;\n v17 = 0LL;\n while (!strcmp(v23[v17 / 8 + 100], v23[v17 / 8 + 200])) {\n v17 += 8LL;\n if (v16 == v17) return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}" + }, + { + "index": 508, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(char *l1[], char *l2[], int size1, int size2) {\n int common_elements_size = 0;\n char *common_elements[100];\n for (int i = 0; i < size1; i++) {\n for (int j = 0; j < size2; j++) {\n if (strcmp(l1[i], l2[j]) == 0) {\n bool is_unique = true;\n for (int k = 0; k < common_elements_size; k++) {\n if (strcmp(common_elements[k], l1[i]) == 0) {\n is_unique = false;\n break;\n }\n }\n if (is_unique) {\n common_elements[common_elements_size++] = l1[i];\n }\n }\n }\n }\n int index1 = 0;\n int index2 = 0;\n char *ordered_l1[100];\n char *ordered_l2[100];\n for (int i = 0; i < size1; i++) {\n for (int j = 0; j < common_elements_size; j++) {\n if (strcmp(l1[i], common_elements[j]) == 0) {\n ordered_l1[index1++] = l1[i];\n }\n }\n }\n for (int i = 0; i < size2; i++) {\n for (int j = 0; j < common_elements_size; j++) {\n if (strcmp(l2[i], common_elements[j]) == 0) {\n ordered_l2[index2++] = l2[i];\n }\n }\n }\n if (index1 != index2) {\n return false;\n }\n for (int i = 0; i < index1; i++) {\n if (strcmp(ordered_l1[i], ordered_l2[i]) != 0) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n char *list1a[] = {\"red\", \"green\", \"black\", \"orange\"};\n\n char *list2a[] = {\"red\", \"pink\", \"green\", \"white\", \"black\"};\n\n char *list1b[] = {\"red\", \"pink\", \"green\", \"white\", \"black\"};\n\n char *list2b[] = {\"white\", \"orange\", \"pink\", \"black\"};\n\n char *list1c[] = {\"red\", \"green\", \"black\", \"orange\"};\n\n char *list2c[] = {\"red\", \"pink\", \"green\", \"white\", \"black\"};\n\n\n\n assert(func0(list1a, list2a, 4, 5) == true);\n\n assert(func0(list1b, list2b, 5, 4) == false);\n\n assert(func0(list1c, list2c, 4, 5) == true);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x9b8,%rsp\nmov %rsi,0x38(%rsp)\nmov %ecx,0x2c(%rsp)\nmov %fs:0x28,%rax\nmov %rax,0x9a8(%rsp)\nxor %eax,%eax\ntest %edx,%edx\njle 15fc \nlea -0x1(%rdx),%eax\nmov 0x38(%rsp),%rcx\nmov %rdi,0x8(%rsp)\nxor %r13d,%r13d\nlea 0x8(%rdi,%rax,8),%rax\nmov %rdi,0x10(%rsp)\nmov %rax,0x30(%rsp)\nmov 0x2c(%rsp),%eax\nsub $0x1,%eax\nlea 0x8(%rcx,%rax,8),%r14\nlea 0x40(%rsp),%rax\nmov %rax,0x18(%rsp)\nlea 0x48(%rsp),%rax\nmov %rax,0x20(%rsp)\nnopl 0x0(%rax,%rax,1)\nmov 0x2c(%rsp),%ecx\ntest %ecx,%ecx\njle 1490 \nmov 0x10(%rsp),%rax\nmov 0x38(%rsp),%rbx\nmov (%rax),%rbp\njmp 1439 \nnopw 0x0(%rax,%rax,1)\nadd $0x8,%rbx\ncmp %r14,%rbx\nje 1490 \nmov (%rbx),%rsi\nmov %rbp,%rdi\ncallq 10b0 \ntest %eax,%eax\njne 1430 \ntest %r13d,%r13d\nje 1478 \nmov 0x20(%rsp),%rcx\nlea -0x1(%r13),%eax\nmov 0x18(%rsp),%r15\nlea (%rcx,%rax,8),%r12\nmov (%r15),%rdi\nmov %rbp,%rsi\ncallq 10b0 \ntest %eax,%eax\nje 1430 \nadd $0x8,%r15\ncmp %r12,%r15\njne 1460 \nmovslq %r13d,%rax\nadd $0x8,%rbx\nadd $0x1,%r13d\nmov %rbp,0x40(%rsp,%rax,8)\ncmp %r14,%rbx\njne 1439 \nnopl (%rax)\naddq $0x8,0x10(%rsp)\nmov 0x10(%rsp),%rax\ncmp 0x30(%rsp),%rax\njne 1410 \nmov 0x20(%rsp),%rcx\nlea -0x1(%r13),%eax\nxor %ebx,%ebx\nmov %rax,%r15\nlea (%rcx,%rax,8),%rbp\nnopl 0x0(%rax,%rax,1)\ntest %r13d,%r13d\nje 14fe \nmov 0x8(%rsp),%rax\nmov 0x18(%rsp),%r14\nmov (%rax),%r12\nnopw 0x0(%rax,%rax,1)\nmov (%r14),%rsi\nmov %r12,%rdi\ncallq 10b0 \ntest %eax,%eax\njne 14f5 \nmovslq %ebx,%rax\nadd $0x1,%ebx\nmov %r12,0x360(%rsp,%rax,8)\nadd $0x8,%r14\ncmp %r14,%rbp\njne 14d8 \naddq $0x8,0x8(%rsp)\nmov 0x8(%rsp),%rax\ncmp 0x30(%rsp),%rax\njne 14c0 \nmov 0x2c(%rsp),%edx\ntest %edx,%edx\njle 1628 \nmov 0x20(%rsp),%rax\nmov %r15d,%r12d\nxor %ebp,%ebp\nmovq $0x0,0x8(%rsp)\nlea (%rax,%r12,8),%r12\nnopl 0x0(%rax,%rax,1)\ntest %r13d,%r13d\nje 1576 \nmov 0x38(%rsp),%rax\nmov 0x8(%rsp),%rdx\nmov 0x18(%rsp),%r15\nmov (%rax,%rdx,8),%r14\nmov (%r15),%rsi\nmov %r14,%rdi\ncallq 10b0 \ntest %eax,%eax\njne 156d \nmovslq %ebp,%rax\nadd $0x1,%ebp\nmov %r14,0x680(%rsp,%rax,8)\nadd $0x8,%r15\ncmp %r15,%r12\njne 1550 \naddq $0x1,0x8(%rsp)\nmov 0x8(%rsp),%rax\ncmp %eax,0x2c(%rsp)\njg 1538 \nxor %eax,%eax\ncmp %ebp,%ebx\njne 15d0 \ntest %ebx,%ebx\nje 15f5 \nlea -0x1(%rbx),%ebp\nlea 0x680(%rsp),%r13\nxor %ebx,%ebx\nlea 0x360(%rsp),%r12\njmp 15bc \nnopl 0x0(%rax,%rax,1)\nlea 0x1(%rbx),%rax\ncmp %rbx,%rbp\nje 15f5 \nmov %rax,%rbx\nmov 0x0(%r13,%rbx,8),%rsi\nmov (%r12,%rbx,8),%rdi\ncallq 10b0 \ntest %eax,%eax\nje 15b0 \nxor %eax,%eax\nmov 0x9a8(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 162f \nadd $0x9b8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmov $0x1,%eax\njmp 15d0 \nmov 0x2c(%rsp),%eax\ntest %eax,%eax\njle 15f5 \nlea 0x40(%rsp),%rax\nxor %r13d,%r13d\nxor %ebx,%ebx\nmov $0xffffffff,%r15d\nmov %rax,0x18(%rsp)\nlea 0x48(%rsp),%rax\nmov %rax,0x20(%rsp)\njmpq 151c \nxor %ebp,%ebp\njmpq 1587 \ncallq 1090 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 9B8h\nmov [rsp+9E8h+var_9B8], rsi\nmov [rsp+9E8h+var_9AC], ecx\nmov rax, fs:28h\nmov [rsp+9E8h+var_40], rax\nxor eax, eax\ntest edx, edx\njle loc_166F\nmovsxd rdx, edx\nmov [rsp+9E8h+var_9C8], rdi\nlea rax, [rdi+rdx*8]\nmov [rsp+9E8h+var_9D0], rdi\nmov rdx, [rsp+9E8h+var_9B8]\nmov [rsp+9E8h+var_9C0], rax\nmovsxd rax, [rsp+9E8h+var_9AC]\nlea r13, [rdx+rax*8]\nloc_13ED:\nmov ecx, [rsp+9E8h+var_9AC]\ntest ecx, ecx\njle loc_1631\nlea rax, [rsp+9E8h+var_9A8]\nxor r15d, r15d\nmov [rsp+9E8h+var_9E0], 0\nmov [rsp+9E8h+var_9D8], rax\nnop\nloc_1410:\nmov rax, [rsp+9E8h+var_9D0]\nmov rbx, [rsp+9E8h+var_9B8]\nmov rbp, [rax]\njmp short loc_1429\nloc_1420:\nadd rbx, 8\ncmp rbx, r13\njz short loc_1490\nloc_1429:\nmov rsi, [rbx]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1420\ntest r15d, r15d\njle short loc_1468\nmov rax, [rsp+9E8h+var_9D8]\nmov rcx, [rsp+9E8h+var_9E0]\nmov r14, rax\nlea r12, [rax+rcx*8]\nxchg ax, ax\nloc_1450:\nmov rdi, [r14]; s1\nmov rsi, rbp; s2\ncall _strcmp\ntest eax, eax\njz short loc_1420\nadd r14, 8\ncmp r14, r12\njnz short loc_1450\nloc_1468:\nmov rax, [rsp+9E8h+var_9E0]\nadd r15d, 1\nadd rbx, 8\nmov [rsp+rax*8+9E8h+var_9A8], rbp\nmovsxd rax, r15d\nmov [rsp+9E8h+var_9E0], rax\ncmp rbx, r13\njnz short loc_1429\nnop word ptr [rax+rax+00000000h]\nloc_1490:\nadd [rsp+9E8h+var_9D0], 8\nmov rdx, [rsp+9E8h+var_9C0]\nmov rax, [rsp+9E8h+var_9D0]\ncmp rax, rdx\njnz loc_1410\nloc_14A9:\nmov rax, [rsp+9E8h+var_9D8]\nmov rdx, [rsp+9E8h+var_9E0]\nlea r12, [rax+rdx*8]\nloc_14B7:\ntest r15d, r15d\njle loc_1611\nxor ebx, ebx\nnop word ptr [rax+rax+00h]\nloc_14C8:\nmov rax, [rsp+9E8h+var_9C8]\nmov r13, [rsp+9E8h+var_9D8]\nmov rbp, [rax]\nnop dword ptr [rax]\nloc_14D8:\nmov rsi, [r13+0]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njnz short loc_14F6\nmovsxd rax, ebx\nadd ebx, 1\nmov [rsp+rax*8+9E8h+var_688], rbp\nloc_14F6:\nadd r13, 8\ncmp r12, r13\njnz short loc_14D8\nadd [rsp+9E8h+var_9C8], 8\nmov rdx, [rsp+9E8h+var_9C0]\nmov rax, [rsp+9E8h+var_9C8]\ncmp rax, rdx\njnz short loc_14C8\nloc_1514:\nmov eax, [rsp+9E8h+var_9AC]\ntest eax, eax\njle loc_1694\nloc_1520:\nmov rax, [rsp+9E8h+var_9D8]\nmov rdx, [rsp+9E8h+var_9E0]\nxor r14d, r14d\nlea r12, [rax+rdx*8]\nloc_1531:\ntest r15d, r15d\njle loc_15FA\nxor r15d, r15d\nnop dword ptr [rax]\nloc_1540:\nmov rax, [rsp+9E8h+var_9B8]\nmov r13, [rsp+9E8h+var_9D8]\nmov rbp, [rax+r14*8]\nxchg ax, ax\nloc_1550:\nmov rsi, [r13+0]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njnz short loc_156F\nmovsxd rax, r15d\nadd r15d, 1\nmov [rsp+rax*8+9E8h+var_368], rbp\nloc_156F:\nadd r13, 8\ncmp r12, r13\njnz short loc_1550\nadd r14, 1\ncmp [rsp+9E8h+var_9AC], r14d\njg short loc_1540\nloc_1583:\nxor eax, eax\ncmp ebx, r15d\njnz short loc_15D1\ntest ebx, ebx\njle loc_1665\nmovsxd rbx, ebx\nxor ebp, ebp\nlea r13, [rsp+9E8h+var_368]\nshl rbx, 3\nlea r12, [rsp+9E8h+var_688]\njmp short loc_15BD\nloc_15B0:\nadd rbp, 8\ncmp rbp, rbx\njz loc_1665\nloc_15BD:\nmov rsi, [r13+rbp+0]; s2\nmov rdi, [r12+rbp]; s1\ncall _strcmp\ntest eax, eax\njz short loc_15B0\nxor eax, eax\nloc_15D1:\nmov rdx, [rsp+9E8h+var_40]\nsub rdx, fs:28h\njnz loc_169E\nadd rsp, 9B8h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15FA:\nadd r14, 1\ncmp [rsp+9E8h+var_9AC], r14d\njg loc_1531\nxor r15d, r15d\njmp loc_1583\nloc_1611:\nadd [rsp+9E8h+var_9C8], 8\nmov rdx, [rsp+9E8h+var_9C0]\nmov rax, [rsp+9E8h+var_9C8]\ncmp rax, rdx\njnz loc_14B7\nxor ebx, ebx\njmp loc_1514\nloc_1631:\nadd [rsp+9E8h+var_9D0], 8\nmov rdx, [rsp+9E8h+var_9C0]\nmov rax, [rsp+9E8h+var_9D0]\ncmp rax, rdx\njnz loc_13ED\nlea rax, [rsp+9E8h+var_9A8]\nxor r15d, r15d\nmov [rsp+9E8h+var_9E0], 0\nmov [rsp+9E8h+var_9D8], rax\njmp loc_14A9\nloc_1665:\nmov eax, 1\njmp loc_15D1\nloc_166F:\nmov edx, [rsp+9E8h+var_9AC]\ntest edx, edx\njle short loc_1665\nlea rax, [rsp+9E8h+var_9A8]\nxor ebx, ebx\nxor r15d, r15d\nmov [rsp+9E8h+var_9E0], 0\nmov [rsp+9E8h+var_9D8], rax\njmp loc_1520\nloc_1694:\ntest ebx, ebx\nsetz al\njmp loc_15D1\nloc_169E:\ncall ___stack_chk_fail", + "ida_pseudo": "bool __fastcall func0(const char **a1, const char **a2, int a3, int a4)\n{\n const char **v4; // r13\n int v5; // r15d\n const char **v6; // rbx\n const char *v7; // rbp\n const char **v8; // r14\n int v9; // ebx\n const char **v10; // r13\n const char *v11; // rbp\n __int64 v12; // rax\n __int64 v13; // r14\n int v14; // r15d\n const char **v15; // r13\n const char *v16; // rbp\n __int64 v17; // rax\n bool result; // al\n unsigned __int64 v19; // rbp\n __int64 v20; // rbx\n __int64 v21; // [rsp+8h] [rbp-9E0h]\n const char **v22; // [rsp+18h] [rbp-9D0h]\n const char **v23; // [rsp+20h] [rbp-9C8h]\n const char **v24; // [rsp+28h] [rbp-9C0h]\n _QWORD v26[309]; // [rsp+40h] [rbp-9A8h] BYREF\n\n v26[301] = __readfsqword(0x28u);\n if ( a3 <= 0 )\n {\n if ( a4 > 0 )\n {\n v9 = 0;\n v5 = 0;\n v21 = 0LL;\n goto LABEL_22;\n }\n return 1;\n }\n v23 = a1;\n v22 = a1;\n v24 = &a1[a3];\n v4 = &a2[a4];\n do\n {\n if ( a4 > 0 )\n {\n v5 = 0;\n v21 = 0LL;\n while ( 1 )\n {\n v6 = a2;\n v7 = *v22;\n do\n {\n while ( strcmp(v7, *v6) )\n {\nLABEL_6:\n if ( ++v6 == v4 )\n goto LABEL_13;\n }\n if ( v5 > 0 )\n {\n v8 = (const char **)v26;\n while ( strcmp(*v8, v7) )\n {\n if ( ++v8 == &v26[v21] )\n goto LABEL_12;\n }\n goto LABEL_6;\n }\nLABEL_12:\n ++v5;\n ++v6;\n v26[v21] = v7;\n v21 = v5;\n }\n while ( v6 != v4 );\nLABEL_13:\n if ( ++v22 == v24 )\n goto LABEL_14;\n }\n }\n ++v22;\n }\n while ( v22 != v24 );\n v5 = 0;\n v21 = 0LL;\nLABEL_14:\n while ( v5 <= 0 )\n {\n if ( ++v23 == v24 )\n {\n v9 = 0;\n goto LABEL_21;\n }\n }\n v9 = 0;\n do\n {\n v10 = (const char **)v26;\n v11 = *v23;\n do\n {\n if ( !strcmp(v11, *v10) )\n {\n v12 = v9++;\n v26[v12 + 100] = v11;\n }\n ++v10;\n }\n while ( &v26[v21] != v10 );\n ++v23;\n }\n while ( v23 != v24 );\nLABEL_21:\n if ( a4 <= 0 )\n return v9 == 0;\nLABEL_22:\n v13 = 0LL;\n while ( v5 <= 0 )\n {\n if ( a4 <= (int)++v13 )\n {\n v14 = 0;\n goto LABEL_30;\n }\n }\n v14 = 0;\n do\n {\n v15 = (const char **)v26;\n v16 = a2[v13];\n do\n {\n if ( !strcmp(v16, *v15) )\n {\n v17 = v14++;\n v26[v17 + 200] = v16;\n }\n ++v15;\n }\n while ( &v26[v21] != v15 );\n ++v13;\n }\n while ( a4 > (int)v13 );\nLABEL_30:\n result = 0;\n if ( v9 == v14 )\n {\n if ( v9 > 0 )\n {\n v19 = 0LL;\n v20 = 8LL * v9;\n while ( !strcmp((const char *)v26[v19 / 8 + 100], (const char *)v26[v19 / 8 + 200]) )\n {\n v19 += 8LL;\n if ( v19 == v20 )\n return 1;\n }\n return 0;\n }\n return 1;\n }\n return result;\n}", + "ida_strip_asm": "sub_1390:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 9B8h\nmov [rsp+9E8h+var_9B8], rsi\nmov [rsp+9E8h+var_9AC], ecx\nmov rax, fs:28h\nmov [rsp+9E8h+var_40], rax\nxor eax, eax\ntest edx, edx\njle loc_166F\nmovsxd rdx, edx\nmov [rsp+9E8h+var_9C8], rdi\nlea rax, [rdi+rdx*8]\nmov [rsp+9E8h+var_9D0], rdi\nmov rdx, [rsp+9E8h+var_9B8]\nmov [rsp+9E8h+var_9C0], rax\nmovsxd rax, [rsp+9E8h+var_9AC]\nlea r13, [rdx+rax*8]\nloc_13ED:\nmov ecx, [rsp+9E8h+var_9AC]\ntest ecx, ecx\njle loc_1631\nlea rax, [rsp+9E8h+var_9A8]\nxor r15d, r15d\nmov [rsp+9E8h+var_9E0], 0\nmov [rsp+9E8h+var_9D8], rax\nnop\nloc_1410:\nmov rax, [rsp+9E8h+var_9D0]\nmov rbx, [rsp+9E8h+var_9B8]\nmov rbp, [rax]\njmp short loc_1429\nloc_1420:\nadd rbx, 8\ncmp rbx, r13\njz short loc_1490\nloc_1429:\nmov rsi, [rbx]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1420\ntest r15d, r15d\njle short loc_1468\nmov rax, [rsp+9E8h+var_9D8]\nmov rcx, [rsp+9E8h+var_9E0]\nmov r14, rax\nlea r12, [rax+rcx*8]\nxchg ax, ax\nloc_1450:\nmov rdi, [r14]; s1\nmov rsi, rbp; s2\ncall _strcmp\ntest eax, eax\njz short loc_1420\nadd r14, 8\ncmp r14, r12\njnz short loc_1450\nloc_1468:\nmov rax, [rsp+9E8h+var_9E0]\nadd r15d, 1\nadd rbx, 8\nmov [rsp+rax*8+9E8h+var_9A8], rbp\nmovsxd rax, r15d\nmov [rsp+9E8h+var_9E0], rax\ncmp rbx, r13\njnz short loc_1429\nnop word ptr [rax+rax+00000000h]\nloc_1490:\nadd [rsp+9E8h+var_9D0], 8\nmov rdx, [rsp+9E8h+var_9C0]\nmov rax, [rsp+9E8h+var_9D0]\ncmp rax, rdx\njnz loc_1410\nloc_14A9:\nmov rax, [rsp+9E8h+var_9D8]\nmov rdx, [rsp+9E8h+var_9E0]\nlea r12, [rax+rdx*8]\nloc_14B7:\ntest r15d, r15d\njle loc_1611\nxor ebx, ebx\nnop word ptr [rax+rax+00h]\nloc_14C8:\nmov rax, [rsp+9E8h+var_9C8]\nmov r13, [rsp+9E8h+var_9D8]\nmov rbp, [rax]\nnop dword ptr [rax]\nloc_14D8:\nmov rsi, [r13+0]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njnz short loc_14F6\nmovsxd rax, ebx\nadd ebx, 1\nmov [rsp+rax*8+9E8h+var_688], rbp\nloc_14F6:\nadd r13, 8\ncmp r12, r13\njnz short loc_14D8\nadd [rsp+9E8h+var_9C8], 8\nmov rdx, [rsp+9E8h+var_9C0]\nmov rax, [rsp+9E8h+var_9C8]\ncmp rax, rdx\njnz short loc_14C8\nloc_1514:\nmov eax, [rsp+9E8h+var_9AC]\ntest eax, eax\njle loc_1694\nloc_1520:\nmov rax, [rsp+9E8h+var_9D8]\nmov rdx, [rsp+9E8h+var_9E0]\nxor r14d, r14d\nlea r12, [rax+rdx*8]\nloc_1531:\ntest r15d, r15d\njle loc_15FA\nxor r15d, r15d\nnop dword ptr [rax]\nloc_1540:\nmov rax, [rsp+9E8h+var_9B8]\nmov r13, [rsp+9E8h+var_9D8]\nmov rbp, [rax+r14*8]\nxchg ax, ax\nloc_1550:\nmov rsi, [r13+0]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njnz short loc_156F\nmovsxd rax, r15d\nadd r15d, 1\nmov [rsp+rax*8+9E8h+var_368], rbp\nloc_156F:\nadd r13, 8\ncmp r12, r13\njnz short loc_1550\nadd r14, 1\ncmp [rsp+9E8h+var_9AC], r14d\njg short loc_1540\nloc_1583:\nxor eax, eax\ncmp ebx, r15d\njnz short loc_15D1\ntest ebx, ebx\njle loc_1665\nmovsxd rbx, ebx\nxor ebp, ebp\nlea r13, [rsp+9E8h+var_368]\nshl rbx, 3\nlea r12, [rsp+9E8h+var_688]\njmp short loc_15BD\nloc_15B0:\nadd rbp, 8\ncmp rbp, rbx\njz loc_1665\nloc_15BD:\nmov rsi, [r13+rbp+0]; s2\nmov rdi, [r12+rbp]; s1\ncall _strcmp\ntest eax, eax\njz short loc_15B0\nxor eax, eax\nloc_15D1:\nmov rdx, [rsp+9E8h+var_40]\nsub rdx, fs:28h\njnz loc_169E\nadd rsp, 9B8h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15FA:\nadd r14, 1\ncmp [rsp+9E8h+var_9AC], r14d\njg loc_1531\nxor r15d, r15d\njmp loc_1583\nloc_1611:\nadd [rsp+9E8h+var_9C8], 8\nmov rdx, [rsp+9E8h+var_9C0]\nmov rax, [rsp+9E8h+var_9C8]\ncmp rax, rdx\njnz loc_14B7\nxor ebx, ebx\njmp loc_1514\nloc_1631:\nadd [rsp+9E8h+var_9D0], 8\nmov rdx, [rsp+9E8h+var_9C0]\nmov rax, [rsp+9E8h+var_9D0]\ncmp rax, rdx\njnz loc_13ED\nlea rax, [rsp+9E8h+var_9A8]\nxor r15d, r15d\nmov [rsp+9E8h+var_9E0], 0\nmov [rsp+9E8h+var_9D8], rax\njmp loc_14A9\nloc_1665:\nmov eax, 1\njmp loc_15D1\nloc_166F:\nmov edx, [rsp+9E8h+var_9AC]\ntest edx, edx\njle short loc_1665\nlea rax, [rsp+9E8h+var_9A8]\nxor ebx, ebx\nxor r15d, r15d\nmov [rsp+9E8h+var_9E0], 0\nmov [rsp+9E8h+var_9D8], rax\njmp loc_1520\nloc_1694:\ntest ebx, ebx\nsetz al\njmp loc_15D1\nloc_169E:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "bool __fastcall sub_1390(const char **a1, const char **a2, int a3, int a4)\n{\n const char **v4; // r13\n int v5; // r15d\n const char **v6; // rbx\n const char *v7; // rbp\n const char **v8; // r14\n int v9; // ebx\n const char **v10; // r13\n const char *v11; // rbp\n __int64 v12; // rax\n __int64 v13; // r14\n int v14; // r15d\n const char **v15; // r13\n const char *v16; // rbp\n __int64 v17; // rax\n bool result; // al\n unsigned __int64 v19; // rbp\n __int64 v20; // rbx\n __int64 v21; // [rsp+8h] [rbp-9E0h]\n const char **v22; // [rsp+18h] [rbp-9D0h]\n const char **v23; // [rsp+20h] [rbp-9C8h]\n const char **v24; // [rsp+28h] [rbp-9C0h]\n _QWORD v26[309]; // [rsp+40h] [rbp-9A8h] BYREF\n\n v26[301] = __readfsqword(0x28u);\n if ( a3 <= 0 )\n {\n if ( a4 > 0 )\n {\n v9 = 0;\n v5 = 0;\n v21 = 0LL;\n goto LABEL_22;\n }\n return 1;\n }\n v23 = a1;\n v22 = a1;\n v24 = &a1[a3];\n v4 = &a2[a4];\n do\n {\n if ( a4 > 0 )\n {\n v5 = 0;\n v21 = 0LL;\n while ( 1 )\n {\n v6 = a2;\n v7 = *v22;\n do\n {\n while ( strcmp(v7, *v6) )\n {\nLABEL_6:\n if ( ++v6 == v4 )\n goto LABEL_13;\n }\n if ( v5 > 0 )\n {\n v8 = (const char **)v26;\n while ( strcmp(*v8, v7) )\n {\n if ( ++v8 == &v26[v21] )\n goto LABEL_12;\n }\n goto LABEL_6;\n }\nLABEL_12:\n ++v5;\n ++v6;\n v26[v21] = v7;\n v21 = v5;\n }\n while ( v6 != v4 );\nLABEL_13:\n if ( ++v22 == v24 )\n goto LABEL_14;\n }\n }\n ++v22;\n }\n while ( v22 != v24 );\n v5 = 0;\n v21 = 0LL;\nLABEL_14:\n while ( v5 <= 0 )\n {\n if ( ++v23 == v24 )\n {\n v9 = 0;\n goto LABEL_21;\n }\n }\n v9 = 0;\n do\n {\n v10 = (const char **)v26;\n v11 = *v23;\n do\n {\n if ( !strcmp(v11, *v10) )\n {\n v12 = v9++;\n v26[v12 + 100] = v11;\n }\n ++v10;\n }\n while ( &v26[v21] != v10 );\n ++v23;\n }\n while ( v23 != v24 );\nLABEL_21:\n if ( a4 <= 0 )\n return v9 == 0;\nLABEL_22:\n v13 = 0LL;\n while ( v5 <= 0 )\n {\n if ( a4 <= (int)++v13 )\n {\n v14 = 0;\n goto LABEL_30;\n }\n }\n v14 = 0;\n do\n {\n v15 = (const char **)v26;\n v16 = a2[v13];\n do\n {\n if ( !strcmp(v16, *v15) )\n {\n v17 = v14++;\n v26[v17 + 200] = v16;\n }\n ++v15;\n }\n while ( &v26[v21] != v15 );\n ++v13;\n }\n while ( a4 > (int)v13 );\nLABEL_30:\n result = 0;\n if ( v9 == v14 )\n {\n if ( v9 > 0 )\n {\n v19 = 0LL;\n v20 = 8LL * v9;\n while ( !strcmp((const char *)v26[v19 / 8 + 100], (const char *)v26[v19 / 8 + 200]) )\n {\n v19 += 8LL;\n if ( v19 == v20 )\n return 1;\n }\n return 0;\n }\n return 1;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_1390(const char **a1, const char **a2, int a3, int a4) {\n const char **v4;\n int v5;\n const char **v6;\n const char *v7;\n const char **v8;\n int v9;\n const char **v10;\n const char *v11;\n long long v12;\n long long v13;\n int v14;\n const char **v15;\n const char *v16;\n long long v17;\n bool result;\n unsigned long long v19;\n long long v20;\n long long v21;\n const char **v22;\n const char **v23;\n const char **v24;\n uint64_t v26[309];\n v26[301] = __readfsqword(40u);\n if (a3 <= 0) {\n if (a4 > 0) {\n v9 = 0;\n v5 = 0;\n v21 = 0LL;\n goto LABEL_22;\n }\n return 1;\n }\n v23 = a1;\n v22 = a1;\n v24 = &a1[a3];\n v4 = &a2[a4];\n do {\n if (a4 > 0) {\n v5 = 0;\n v21 = 0LL;\n while (1) {\n v6 = a2;\n v7 = *v22;\n do {\n while (strcmp(v7, *v6)) {\n LABEL_6:\n if (++v6 == v4) goto LABEL_13;\n }\n if (v5 > 0) {\n v8 = (const char **)v26;\n while (strcmp(*v8, v7)) {\n if (++v8 == &v26[v21]) goto LABEL_12;\n }\n goto LABEL_6;\n }\n LABEL_12:\n ++v5;\n ++v6;\n v26[v21] = v7;\n v21 = v5;\n } while (v6 != v4);\n LABEL_13:\n if (++v22 == v24) goto LABEL_14;\n }\n }\n ++v22;\n } while (v22 != v24);\n v5 = 0;\n v21 = 0LL;\nLABEL_14:\n while (v5 <= 0) {\n if (++v23 == v24) {\n v9 = 0;\n goto LABEL_21;\n }\n }\n v9 = 0;\n do {\n v10 = (const char **)v26;\n v11 = *v23;\n do {\n if (!strcmp(v11, *v10)) {\n v12 = v9++;\n v26[v12 + 100] = v11;\n }\n ++v10;\n } while (&v26[v21] != v10);\n ++v23;\n } while (v23 != v24);\nLABEL_21:\n if (a4 <= 0) return v9 == 0;\nLABEL_22:\n v13 = 0LL;\n while (v5 <= 0) {\n if (a4 <= (int)++v13) {\n v14 = 0;\n goto LABEL_30;\n }\n }\n v14 = 0;\n do {\n v15 = (const char **)v26;\n v16 = a2[v13];\n do {\n if (!strcmp(v16, *v15)) {\n v17 = v14++;\n v26[v17 + 200] = v16;\n }\n ++v15;\n } while (&v26[v21] != v15);\n ++v13;\n } while (a4 > (int)v13);\nLABEL_30:\n result = 0;\n if (v9 == v14) {\n if (v9 > 0) {\n v19 = 0LL;\n v20 = 8LL * v9;\n while (!strcmp((const char *)v26[v19 / 8 + 100],\n (const char *)v26[v19 / 8 + 200])) {\n v19 += 8LL;\n if (v19 == v20) return 1;\n }\n return 0;\n }\n return 1;\n }\n return result;\n}", + "ida_pseudo_norm": "bool func0(const char **a1, const char **a2, int a3, int a4) {\n const char **v4;\n int v5;\n const char **v6;\n const char *v7;\n const char **v8;\n int v9;\n const char **v10;\n const char *v11;\n long long v12;\n long long v13;\n int v14;\n const char **v15;\n const char *v16;\n long long v17;\n bool result;\n unsigned long long v19;\n long long v20;\n long long v21;\n const char **v22;\n const char **v23;\n const char **v24;\n uint64_t v26[309];\n v26[301] = __readfsqword(40u);\n if (a3 <= 0) {\n if (a4 > 0) {\n v9 = 0;\n v5 = 0;\n v21 = 0LL;\n goto LABEL_22;\n }\n return 1;\n }\n v23 = a1;\n v22 = a1;\n v24 = &a1[a3];\n v4 = &a2[a4];\n do {\n if (a4 > 0) {\n v5 = 0;\n v21 = 0LL;\n while (1) {\n v6 = a2;\n v7 = *v22;\n do {\n while (strcmp(v7, *v6)) {\n LABEL_6:\n if (++v6 == v4) goto LABEL_13;\n }\n if (v5 > 0) {\n v8 = (const char **)v26;\n while (strcmp(*v8, v7)) {\n if (++v8 == &v26[v21]) goto LABEL_12;\n }\n goto LABEL_6;\n }\n LABEL_12:\n ++v5;\n ++v6;\n v26[v21] = v7;\n v21 = v5;\n } while (v6 != v4);\n LABEL_13:\n if (++v22 == v24) goto LABEL_14;\n }\n }\n ++v22;\n } while (v22 != v24);\n v5 = 0;\n v21 = 0LL;\nLABEL_14:\n while (v5 <= 0) {\n if (++v23 == v24) {\n v9 = 0;\n goto LABEL_21;\n }\n }\n v9 = 0;\n do {\n v10 = (const char **)v26;\n v11 = *v23;\n do {\n if (!strcmp(v11, *v10)) {\n v12 = v9++;\n v26[v12 + 100] = v11;\n }\n ++v10;\n } while (&v26[v21] != v10);\n ++v23;\n } while (v23 != v24);\nLABEL_21:\n if (a4 <= 0) return v9 == 0;\nLABEL_22:\n v13 = 0LL;\n while (v5 <= 0) {\n if (a4 <= (int)++v13) {\n v14 = 0;\n goto LABEL_30;\n }\n }\n v14 = 0;\n do {\n v15 = (const char **)v26;\n v16 = a2[v13];\n do {\n if (!strcmp(v16, *v15)) {\n v17 = v14++;\n v26[v17 + 200] = v16;\n }\n ++v15;\n } while (&v26[v21] != v15);\n ++v13;\n } while (a4 > (int)v13);\nLABEL_30:\n result = 0;\n if (v9 == v14) {\n if (v9 > 0) {\n v19 = 0LL;\n v20 = 8LL * v9;\n while (!strcmp((const char *)v26[v19 / 8 + 100],\n (const char *)v26[v19 / 8 + 200])) {\n v19 += 8LL;\n if (v19 == v20) return 1;\n }\n return 0;\n }\n return 1;\n }\n return result;\n}" + }, + { + "index": 508, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(char *l1[], char *l2[], int size1, int size2) {\n int common_elements_size = 0;\n char *common_elements[100];\n for (int i = 0; i < size1; i++) {\n for (int j = 0; j < size2; j++) {\n if (strcmp(l1[i], l2[j]) == 0) {\n bool is_unique = true;\n for (int k = 0; k < common_elements_size; k++) {\n if (strcmp(common_elements[k], l1[i]) == 0) {\n is_unique = false;\n break;\n }\n }\n if (is_unique) {\n common_elements[common_elements_size++] = l1[i];\n }\n }\n }\n }\n int index1 = 0;\n int index2 = 0;\n char *ordered_l1[100];\n char *ordered_l2[100];\n for (int i = 0; i < size1; i++) {\n for (int j = 0; j < common_elements_size; j++) {\n if (strcmp(l1[i], common_elements[j]) == 0) {\n ordered_l1[index1++] = l1[i];\n }\n }\n }\n for (int i = 0; i < size2; i++) {\n for (int j = 0; j < common_elements_size; j++) {\n if (strcmp(l2[i], common_elements[j]) == 0) {\n ordered_l2[index2++] = l2[i];\n }\n }\n }\n if (index1 != index2) {\n return false;\n }\n for (int i = 0; i < index1; i++) {\n if (strcmp(ordered_l1[i], ordered_l2[i]) != 0) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n char *list1a[] = {\"red\", \"green\", \"black\", \"orange\"};\n\n char *list2a[] = {\"red\", \"pink\", \"green\", \"white\", \"black\"};\n\n char *list1b[] = {\"red\", \"pink\", \"green\", \"white\", \"black\"};\n\n char *list2b[] = {\"white\", \"orange\", \"pink\", \"black\"};\n\n char *list1c[] = {\"red\", \"green\", \"black\", \"orange\"};\n\n char *list2c[] = {\"red\", \"pink\", \"green\", \"white\", \"black\"};\n\n\n\n assert(func0(list1a, list2a, 4, 5) == true);\n\n assert(func0(list1b, list2b, 5, 4) == false);\n\n assert(func0(list1c, list2c, 4, 5) == true);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x9b8,%rsp\nmov %rsi,0x38(%rsp)\nmov %ecx,0x2c(%rsp)\nmov %fs:0x28,%rax\nmov %rax,0x9a8(%rsp)\nxor %eax,%eax\ntest %edx,%edx\njle 15dc \nlea -0x1(%rdx),%eax\nmov %rdi,0x8(%rsp)\nxor %r13d,%r13d\nlea 0x8(%rdi,%rax,8),%rax\nmov %rdi,0x10(%rsp)\nmov %rax,0x30(%rsp)\nmov 0x2c(%rsp),%eax\nsub $0x1,%eax\nlea 0x8(%rsi,%rax,8),%r14\nlea 0x40(%rsp),%rax\nmov %rax,0x18(%rsp)\nlea 0x48(%rsp),%rax\nmov %rax,0x20(%rsp)\nnopl 0x0(%rax,%rax,1)\nmov 0x2c(%rsp),%ecx\ntest %ecx,%ecx\njle 1470 \nmov 0x10(%rsp),%rax\nmov 0x38(%rsp),%rbx\nmov (%rax),%rbp\njmp 1419 \nadd $0x8,%rbx\ncmp %r14,%rbx\nje 1470 \nmov (%rbx),%rsi\nmov %rbp,%rdi\ncallq 10b0 \ntest %eax,%eax\njne 1410 \ntest %r13d,%r13d\nje 1458 \nmov 0x20(%rsp),%rcx\nlea -0x1(%r13),%eax\nmov 0x18(%rsp),%r15\nlea (%rcx,%rax,8),%r12\nmov (%r15),%rdi\nmov %rbp,%rsi\ncallq 10b0 \ntest %eax,%eax\nje 1410 \nadd $0x8,%r15\ncmp %r12,%r15\njne 1440 \nmovslq %r13d,%rax\nadd $0x8,%rbx\nadd $0x1,%r13d\nmov %rbp,0x40(%rsp,%rax,8)\ncmp %r14,%rbx\njne 1419 \nnopl (%rax)\naddq $0x8,0x10(%rsp)\nmov 0x10(%rsp),%rax\ncmp 0x30(%rsp),%rax\njne 13f8 \nmov 0x20(%rsp),%rcx\nlea -0x1(%r13),%eax\nxor %ebx,%ebx\nmov %rax,%r15\nlea (%rcx,%rax,8),%rbp\nnopl 0x0(%rax,%rax,1)\ntest %r13d,%r13d\nje 14de \nmov 0x8(%rsp),%rax\nmov 0x18(%rsp),%r14\nmov (%rax),%r12\nnopw 0x0(%rax,%rax,1)\nmov (%r14),%rsi\nmov %r12,%rdi\ncallq 10b0 \ntest %eax,%eax\njne 14d5 \nmovslq %ebx,%rax\nadd $0x1,%ebx\nmov %r12,0x360(%rsp,%rax,8)\nadd $0x8,%r14\ncmp %r14,%rbp\njne 14b8 \naddq $0x8,0x8(%rsp)\nmov 0x8(%rsp),%rax\ncmp 0x30(%rsp),%rax\njne 14a0 \nmov 0x2c(%rsp),%edx\ntest %edx,%edx\njle 1608 \nmov 0x20(%rsp),%rax\nmov %r15d,%r12d\nxor %ebp,%ebp\nmovq $0x0,0x8(%rsp)\nlea (%rax,%r12,8),%r12\nnopl 0x0(%rax,%rax,1)\ntest %r13d,%r13d\nje 1556 \nmov 0x38(%rsp),%rax\nmov 0x8(%rsp),%rdx\nmov 0x18(%rsp),%r15\nmov (%rax,%rdx,8),%r14\nmov (%r15),%rsi\nmov %r14,%rdi\ncallq 10b0 \ntest %eax,%eax\njne 154d \nmovslq %ebp,%rax\nadd $0x1,%ebp\nmov %r14,0x680(%rsp,%rax,8)\nadd $0x8,%r15\ncmp %r15,%r12\njne 1530 \naddq $0x1,0x8(%rsp)\nmov 0x8(%rsp),%rax\ncmp %eax,0x2c(%rsp)\njg 1518 \nxor %eax,%eax\ncmp %ebp,%ebx\njne 15b0 \ntest %ebx,%ebx\nje 15d5 \nlea -0x1(%rbx),%ebp\nlea 0x680(%rsp),%r13\nxor %ebx,%ebx\nlea 0x360(%rsp),%r12\njmp 159c \nnopl 0x0(%rax,%rax,1)\nlea 0x1(%rbx),%rax\ncmp %rbx,%rbp\nje 15d5 \nmov %rax,%rbx\nmov 0x0(%r13,%rbx,8),%rsi\nmov (%r12,%rbx,8),%rdi\ncallq 10b0 \ntest %eax,%eax\nje 1590 \nxor %eax,%eax\nmov 0x9a8(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 160f \nadd $0x9b8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmov $0x1,%eax\njmp 15b0 \nmov 0x2c(%rsp),%eax\ntest %eax,%eax\njle 15d5 \nlea 0x40(%rsp),%rax\nxor %r13d,%r13d\nxor %ebx,%ebx\nmov $0xffffffff,%r15d\nmov %rax,0x18(%rsp)\nlea 0x48(%rsp),%rax\nmov %rax,0x20(%rsp)\njmpq 14fc \nxor %ebp,%ebp\njmpq 1567 \ncallq 1090 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 9B8h\nmov [rsp+9E8h+var_9B8], rsi\nmov [rsp+9E8h+var_9AC], ecx\nmov rax, fs:28h\nmov [rsp+9E8h+var_40], rax\nxor eax, eax\ntest edx, edx\njle loc_166F\nmovsxd rdx, edx\nmov [rsp+9E8h+var_9C8], rdi\nlea rax, [rdi+rdx*8]\nmov [rsp+9E8h+var_9D0], rdi\nmov rdx, [rsp+9E8h+var_9B8]\nmov [rsp+9E8h+var_9C0], rax\nmovsxd rax, [rsp+9E8h+var_9AC]\nlea r13, [rdx+rax*8]\nloc_13ED:\nmov ecx, [rsp+9E8h+var_9AC]\ntest ecx, ecx\njle loc_1631\nlea rax, [rsp+9E8h+var_9A8]\nxor r15d, r15d\nmov [rsp+9E8h+var_9E0], 0\nmov [rsp+9E8h+var_9D8], rax\nnop\nloc_1410:\nmov rax, [rsp+9E8h+var_9D0]\nmov rbx, [rsp+9E8h+var_9B8]\nmov rbp, [rax]\njmp short loc_1429\nloc_1420:\nadd rbx, 8\ncmp rbx, r13\njz short loc_1490\nloc_1429:\nmov rsi, [rbx]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1420\ntest r15d, r15d\njle short loc_1468\nmov rax, [rsp+9E8h+var_9D8]\nmov rcx, [rsp+9E8h+var_9E0]\nmov r14, rax\nlea r12, [rax+rcx*8]\nxchg ax, ax\nloc_1450:\nmov rdi, [r14]; s1\nmov rsi, rbp; s2\ncall _strcmp\ntest eax, eax\njz short loc_1420\nadd r14, 8\ncmp r14, r12\njnz short loc_1450\nloc_1468:\nmov rax, [rsp+9E8h+var_9E0]\nadd r15d, 1\nadd rbx, 8\nmov [rsp+rax*8+9E8h+var_9A8], rbp\nmovsxd rax, r15d\nmov [rsp+9E8h+var_9E0], rax\ncmp rbx, r13\njnz short loc_1429\nnop word ptr [rax+rax+00000000h]\nloc_1490:\nadd [rsp+9E8h+var_9D0], 8\nmov rdx, [rsp+9E8h+var_9C0]\nmov rax, [rsp+9E8h+var_9D0]\ncmp rax, rdx\njnz loc_1410\nloc_14A9:\nmov rax, [rsp+9E8h+var_9D8]\nmov rdx, [rsp+9E8h+var_9E0]\nlea r12, [rax+rdx*8]\nloc_14B7:\ntest r15d, r15d\njle loc_1611\nxor ebx, ebx\nnop word ptr [rax+rax+00h]\nloc_14C8:\nmov rax, [rsp+9E8h+var_9C8]\nmov r13, [rsp+9E8h+var_9D8]\nmov rbp, [rax]\nnop dword ptr [rax]\nloc_14D8:\nmov rsi, [r13+0]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njnz short loc_14F6\nmovsxd rax, ebx\nadd ebx, 1\nmov [rsp+rax*8+9E8h+var_688], rbp\nloc_14F6:\nadd r13, 8\ncmp r12, r13\njnz short loc_14D8\nadd [rsp+9E8h+var_9C8], 8\nmov rdx, [rsp+9E8h+var_9C0]\nmov rax, [rsp+9E8h+var_9C8]\ncmp rax, rdx\njnz short loc_14C8\nloc_1514:\nmov eax, [rsp+9E8h+var_9AC]\ntest eax, eax\njle loc_1694\nloc_1520:\nmov rax, [rsp+9E8h+var_9D8]\nmov rdx, [rsp+9E8h+var_9E0]\nxor r14d, r14d\nlea r12, [rax+rdx*8]\nloc_1531:\ntest r15d, r15d\njle loc_15FA\nxor r15d, r15d\nnop dword ptr [rax]\nloc_1540:\nmov rax, [rsp+9E8h+var_9B8]\nmov r13, [rsp+9E8h+var_9D8]\nmov rbp, [rax+r14*8]\nxchg ax, ax\nloc_1550:\nmov rsi, [r13+0]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njnz short loc_156F\nmovsxd rax, r15d\nadd r15d, 1\nmov [rsp+rax*8+9E8h+var_368], rbp\nloc_156F:\nadd r13, 8\ncmp r12, r13\njnz short loc_1550\nadd r14, 1\ncmp [rsp+9E8h+var_9AC], r14d\njg short loc_1540\nloc_1583:\nxor eax, eax\ncmp ebx, r15d\njnz short loc_15D1\ntest ebx, ebx\njle loc_1665\nmovsxd rbx, ebx\nxor ebp, ebp\nlea r13, [rsp+9E8h+var_368]\nshl rbx, 3\nlea r12, [rsp+9E8h+var_688]\njmp short loc_15BD\nloc_15B0:\nadd rbp, 8\ncmp rbx, rbp\njz loc_1665\nloc_15BD:\nmov rsi, [r13+rbp+0]; s2\nmov rdi, [r12+rbp]; s1\ncall _strcmp\ntest eax, eax\njz short loc_15B0\nxor eax, eax\nloc_15D1:\nmov rdx, [rsp+9E8h+var_40]\nsub rdx, fs:28h\njnz loc_169E\nadd rsp, 9B8h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15FA:\nadd r14, 1\ncmp [rsp+9E8h+var_9AC], r14d\njg loc_1531\nxor r15d, r15d\njmp loc_1583\nloc_1611:\nadd [rsp+9E8h+var_9C8], 8\nmov rdx, [rsp+9E8h+var_9C0]\nmov rax, [rsp+9E8h+var_9C8]\ncmp rax, rdx\njnz loc_14B7\nxor ebx, ebx\njmp loc_1514\nloc_1631:\nadd [rsp+9E8h+var_9D0], 8\nmov rdx, [rsp+9E8h+var_9C0]\nmov rax, [rsp+9E8h+var_9D0]\ncmp rax, rdx\njnz loc_13ED\nlea rax, [rsp+9E8h+var_9A8]\nxor r15d, r15d\nmov [rsp+9E8h+var_9E0], 0\nmov [rsp+9E8h+var_9D8], rax\njmp loc_14A9\nloc_1665:\nmov eax, 1\njmp loc_15D1\nloc_166F:\nmov edx, [rsp+9E8h+var_9AC]\ntest edx, edx\njle short loc_1665\nlea rax, [rsp+9E8h+var_9A8]\nxor ebx, ebx\nxor r15d, r15d\nmov [rsp+9E8h+var_9E0], 0\nmov [rsp+9E8h+var_9D8], rax\njmp loc_1520\nloc_1694:\ntest ebx, ebx\nsetz al\njmp loc_15D1\nloc_169E:\ncall ___stack_chk_fail", + "ida_pseudo": "bool __fastcall func0(const char **a1, const char **a2, int a3, int a4)\n{\n const char **v4; // r13\n int v5; // r15d\n const char **v6; // rbx\n const char *v7; // rbp\n const char **v8; // r14\n int v9; // ebx\n const char **v10; // r13\n const char *v11; // rbp\n __int64 v12; // rax\n __int64 v13; // r14\n int v14; // r15d\n const char **v15; // r13\n const char *v16; // rbp\n __int64 v17; // rax\n bool result; // al\n unsigned __int64 v19; // rbp\n __int64 v20; // rbx\n __int64 v21; // [rsp+8h] [rbp-9E0h]\n const char **v22; // [rsp+18h] [rbp-9D0h]\n const char **v23; // [rsp+20h] [rbp-9C8h]\n const char **v24; // [rsp+28h] [rbp-9C0h]\n _QWORD v26[309]; // [rsp+40h] [rbp-9A8h] BYREF\n\n v26[301] = __readfsqword(0x28u);\n if ( a3 <= 0 )\n {\n if ( a4 > 0 )\n {\n v9 = 0;\n v5 = 0;\n v21 = 0LL;\n goto LABEL_22;\n }\n return 1;\n }\n v23 = a1;\n v22 = a1;\n v24 = &a1[a3];\n v4 = &a2[a4];\n do\n {\n if ( a4 > 0 )\n {\n v5 = 0;\n v21 = 0LL;\n while ( 1 )\n {\n v6 = a2;\n v7 = *v22;\n do\n {\n while ( strcmp(v7, *v6) )\n {\nLABEL_6:\n if ( ++v6 == v4 )\n goto LABEL_13;\n }\n if ( v5 > 0 )\n {\n v8 = (const char **)v26;\n while ( strcmp(*v8, v7) )\n {\n if ( ++v8 == &v26[v21] )\n goto LABEL_12;\n }\n goto LABEL_6;\n }\nLABEL_12:\n ++v5;\n ++v6;\n v26[v21] = v7;\n v21 = v5;\n }\n while ( v6 != v4 );\nLABEL_13:\n if ( ++v22 == v24 )\n goto LABEL_14;\n }\n }\n ++v22;\n }\n while ( v22 != v24 );\n v5 = 0;\n v21 = 0LL;\nLABEL_14:\n while ( v5 <= 0 )\n {\n if ( ++v23 == v24 )\n {\n v9 = 0;\n goto LABEL_21;\n }\n }\n v9 = 0;\n do\n {\n v10 = (const char **)v26;\n v11 = *v23;\n do\n {\n if ( !strcmp(v11, *v10) )\n {\n v12 = v9++;\n v26[v12 + 100] = v11;\n }\n ++v10;\n }\n while ( &v26[v21] != v10 );\n ++v23;\n }\n while ( v23 != v24 );\nLABEL_21:\n if ( a4 <= 0 )\n return v9 == 0;\nLABEL_22:\n v13 = 0LL;\n while ( v5 <= 0 )\n {\n if ( a4 <= (int)++v13 )\n {\n v14 = 0;\n goto LABEL_30;\n }\n }\n v14 = 0;\n do\n {\n v15 = (const char **)v26;\n v16 = a2[v13];\n do\n {\n if ( !strcmp(v16, *v15) )\n {\n v17 = v14++;\n v26[v17 + 200] = v16;\n }\n ++v15;\n }\n while ( &v26[v21] != v15 );\n ++v13;\n }\n while ( a4 > (int)v13 );\nLABEL_30:\n result = 0;\n if ( v9 == v14 )\n {\n if ( v9 > 0 )\n {\n v19 = 0LL;\n v20 = 8LL * v9;\n while ( !strcmp((const char *)v26[v19 / 8 + 100], (const char *)v26[v19 / 8 + 200]) )\n {\n v19 += 8LL;\n if ( v20 == v19 )\n return 1;\n }\n return 0;\n }\n return 1;\n }\n return result;\n}", + "ida_strip_asm": "sub_1390:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 9B8h\nmov [rsp+9E8h+var_9B8], rsi\nmov [rsp+9E8h+var_9AC], ecx\nmov rax, fs:28h\nmov [rsp+9E8h+var_40], rax\nxor eax, eax\ntest edx, edx\njle loc_166F\nmovsxd rdx, edx\nmov [rsp+9E8h+var_9C8], rdi\nlea rax, [rdi+rdx*8]\nmov [rsp+9E8h+var_9D0], rdi\nmov rdx, [rsp+9E8h+var_9B8]\nmov [rsp+9E8h+var_9C0], rax\nmovsxd rax, [rsp+9E8h+var_9AC]\nlea r13, [rdx+rax*8]\nloc_13ED:\nmov ecx, [rsp+9E8h+var_9AC]\ntest ecx, ecx\njle loc_1631\nlea rax, [rsp+9E8h+var_9A8]\nxor r15d, r15d\nmov [rsp+9E8h+var_9E0], 0\nmov [rsp+9E8h+var_9D8], rax\nnop\nloc_1410:\nmov rax, [rsp+9E8h+var_9D0]\nmov rbx, [rsp+9E8h+var_9B8]\nmov rbp, [rax]\njmp short loc_1429\nloc_1420:\nadd rbx, 8\ncmp rbx, r13\njz short loc_1490\nloc_1429:\nmov rsi, [rbx]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1420\ntest r15d, r15d\njle short loc_1468\nmov rax, [rsp+9E8h+var_9D8]\nmov rcx, [rsp+9E8h+var_9E0]\nmov r14, rax\nlea r12, [rax+rcx*8]\nxchg ax, ax\nloc_1450:\nmov rdi, [r14]; s1\nmov rsi, rbp; s2\ncall _strcmp\ntest eax, eax\njz short loc_1420\nadd r14, 8\ncmp r14, r12\njnz short loc_1450\nloc_1468:\nmov rax, [rsp+9E8h+var_9E0]\nadd r15d, 1\nadd rbx, 8\nmov [rsp+rax*8+9E8h+var_9A8], rbp\nmovsxd rax, r15d\nmov [rsp+9E8h+var_9E0], rax\ncmp rbx, r13\njnz short loc_1429\nnop word ptr [rax+rax+00000000h]\nloc_1490:\nadd [rsp+9E8h+var_9D0], 8\nmov rdx, [rsp+9E8h+var_9C0]\nmov rax, [rsp+9E8h+var_9D0]\ncmp rax, rdx\njnz loc_1410\nloc_14A9:\nmov rax, [rsp+9E8h+var_9D8]\nmov rdx, [rsp+9E8h+var_9E0]\nlea r12, [rax+rdx*8]\nloc_14B7:\ntest r15d, r15d\njle loc_1611\nxor ebx, ebx\nnop word ptr [rax+rax+00h]\nloc_14C8:\nmov rax, [rsp+9E8h+var_9C8]\nmov r13, [rsp+9E8h+var_9D8]\nmov rbp, [rax]\nnop dword ptr [rax]\nloc_14D8:\nmov rsi, [r13+0]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njnz short loc_14F6\nmovsxd rax, ebx\nadd ebx, 1\nmov [rsp+rax*8+9E8h+var_688], rbp\nloc_14F6:\nadd r13, 8\ncmp r12, r13\njnz short loc_14D8\nadd [rsp+9E8h+var_9C8], 8\nmov rdx, [rsp+9E8h+var_9C0]\nmov rax, [rsp+9E8h+var_9C8]\ncmp rax, rdx\njnz short loc_14C8\nloc_1514:\nmov eax, [rsp+9E8h+var_9AC]\ntest eax, eax\njle loc_1694\nloc_1520:\nmov rax, [rsp+9E8h+var_9D8]\nmov rdx, [rsp+9E8h+var_9E0]\nxor r14d, r14d\nlea r12, [rax+rdx*8]\nloc_1531:\ntest r15d, r15d\njle loc_15FA\nxor r15d, r15d\nnop dword ptr [rax]\nloc_1540:\nmov rax, [rsp+9E8h+var_9B8]\nmov r13, [rsp+9E8h+var_9D8]\nmov rbp, [rax+r14*8]\nxchg ax, ax\nloc_1550:\nmov rsi, [r13+0]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njnz short loc_156F\nmovsxd rax, r15d\nadd r15d, 1\nmov [rsp+rax*8+9E8h+var_368], rbp\nloc_156F:\nadd r13, 8\ncmp r12, r13\njnz short loc_1550\nadd r14, 1\ncmp [rsp+9E8h+var_9AC], r14d\njg short loc_1540\nloc_1583:\nxor eax, eax\ncmp ebx, r15d\njnz short loc_15D1\ntest ebx, ebx\njle loc_1665\nmovsxd rbx, ebx\nxor ebp, ebp\nlea r13, [rsp+9E8h+var_368]\nshl rbx, 3\nlea r12, [rsp+9E8h+var_688]\njmp short loc_15BD\nloc_15B0:\nadd rbp, 8\ncmp rbx, rbp\njz loc_1665\nloc_15BD:\nmov rsi, [r13+rbp+0]; s2\nmov rdi, [r12+rbp]; s1\ncall _strcmp\ntest eax, eax\njz short loc_15B0\nxor eax, eax\nloc_15D1:\nmov rdx, [rsp+9E8h+var_40]\nsub rdx, fs:28h\njnz loc_169E\nadd rsp, 9B8h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15FA:\nadd r14, 1\ncmp [rsp+9E8h+var_9AC], r14d\njg loc_1531\nxor r15d, r15d\njmp loc_1583\nloc_1611:\nadd [rsp+9E8h+var_9C8], 8\nmov rdx, [rsp+9E8h+var_9C0]\nmov rax, [rsp+9E8h+var_9C8]\ncmp rax, rdx\njnz loc_14B7\nxor ebx, ebx\njmp loc_1514\nloc_1631:\nadd [rsp+9E8h+var_9D0], 8\nmov rdx, [rsp+9E8h+var_9C0]\nmov rax, [rsp+9E8h+var_9D0]\ncmp rax, rdx\njnz loc_13ED\nlea rax, [rsp+9E8h+var_9A8]\nxor r15d, r15d\nmov [rsp+9E8h+var_9E0], 0\nmov [rsp+9E8h+var_9D8], rax\njmp loc_14A9\nloc_1665:\nmov eax, 1\njmp loc_15D1\nloc_166F:\nmov edx, [rsp+9E8h+var_9AC]\ntest edx, edx\njle short loc_1665\nlea rax, [rsp+9E8h+var_9A8]\nxor ebx, ebx\nxor r15d, r15d\nmov [rsp+9E8h+var_9E0], 0\nmov [rsp+9E8h+var_9D8], rax\njmp loc_1520\nloc_1694:\ntest ebx, ebx\nsetz al\njmp loc_15D1\nloc_169E:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "bool __fastcall sub_1390(const char **a1, const char **a2, int a3, int a4)\n{\n const char **v4; // r13\n int v5; // r15d\n const char **v6; // rbx\n const char *v7; // rbp\n const char **v8; // r14\n int v9; // ebx\n const char **v10; // r13\n const char *v11; // rbp\n __int64 v12; // rax\n __int64 v13; // r14\n int v14; // r15d\n const char **v15; // r13\n const char *v16; // rbp\n __int64 v17; // rax\n bool result; // al\n unsigned __int64 v19; // rbp\n __int64 v20; // rbx\n __int64 v21; // [rsp+8h] [rbp-9E0h]\n const char **v22; // [rsp+18h] [rbp-9D0h]\n const char **v23; // [rsp+20h] [rbp-9C8h]\n const char **v24; // [rsp+28h] [rbp-9C0h]\n _QWORD v26[309]; // [rsp+40h] [rbp-9A8h] BYREF\n\n v26[301] = __readfsqword(0x28u);\n if ( a3 <= 0 )\n {\n if ( a4 > 0 )\n {\n v9 = 0;\n v5 = 0;\n v21 = 0LL;\n goto LABEL_22;\n }\n return 1;\n }\n v23 = a1;\n v22 = a1;\n v24 = &a1[a3];\n v4 = &a2[a4];\n do\n {\n if ( a4 > 0 )\n {\n v5 = 0;\n v21 = 0LL;\n while ( 1 )\n {\n v6 = a2;\n v7 = *v22;\n do\n {\n while ( strcmp(v7, *v6) )\n {\nLABEL_6:\n if ( ++v6 == v4 )\n goto LABEL_13;\n }\n if ( v5 > 0 )\n {\n v8 = (const char **)v26;\n while ( strcmp(*v8, v7) )\n {\n if ( ++v8 == &v26[v21] )\n goto LABEL_12;\n }\n goto LABEL_6;\n }\nLABEL_12:\n ++v5;\n ++v6;\n v26[v21] = v7;\n v21 = v5;\n }\n while ( v6 != v4 );\nLABEL_13:\n if ( ++v22 == v24 )\n goto LABEL_14;\n }\n }\n ++v22;\n }\n while ( v22 != v24 );\n v5 = 0;\n v21 = 0LL;\nLABEL_14:\n while ( v5 <= 0 )\n {\n if ( ++v23 == v24 )\n {\n v9 = 0;\n goto LABEL_21;\n }\n }\n v9 = 0;\n do\n {\n v10 = (const char **)v26;\n v11 = *v23;\n do\n {\n if ( !strcmp(v11, *v10) )\n {\n v12 = v9++;\n v26[v12 + 100] = v11;\n }\n ++v10;\n }\n while ( &v26[v21] != v10 );\n ++v23;\n }\n while ( v23 != v24 );\nLABEL_21:\n if ( a4 <= 0 )\n return v9 == 0;\nLABEL_22:\n v13 = 0LL;\n while ( v5 <= 0 )\n {\n if ( a4 <= (int)++v13 )\n {\n v14 = 0;\n goto LABEL_30;\n }\n }\n v14 = 0;\n do\n {\n v15 = (const char **)v26;\n v16 = a2[v13];\n do\n {\n if ( !strcmp(v16, *v15) )\n {\n v17 = v14++;\n v26[v17 + 200] = v16;\n }\n ++v15;\n }\n while ( &v26[v21] != v15 );\n ++v13;\n }\n while ( a4 > (int)v13 );\nLABEL_30:\n result = 0;\n if ( v9 == v14 )\n {\n if ( v9 > 0 )\n {\n v19 = 0LL;\n v20 = 8LL * v9;\n while ( !strcmp((const char *)v26[v19 / 8 + 100], (const char *)v26[v19 / 8 + 200]) )\n {\n v19 += 8LL;\n if ( v20 == v19 )\n return 1;\n }\n return 0;\n }\n return 1;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_1390(const char **a1, const char **a2, int a3, int a4) {\n const char **v4;\n int v5;\n const char **v6;\n const char *v7;\n const char **v8;\n int v9;\n const char **v10;\n const char *v11;\n long long v12;\n long long v13;\n int v14;\n const char **v15;\n const char *v16;\n long long v17;\n bool result;\n unsigned long long v19;\n long long v20;\n long long v21;\n const char **v22;\n const char **v23;\n const char **v24;\n uint64_t v26[309];\n v26[301] = __readfsqword(40u);\n if (a3 <= 0) {\n if (a4 > 0) {\n v9 = 0;\n v5 = 0;\n v21 = 0LL;\n goto LABEL_22;\n }\n return 1;\n }\n v23 = a1;\n v22 = a1;\n v24 = &a1[a3];\n v4 = &a2[a4];\n do {\n if (a4 > 0) {\n v5 = 0;\n v21 = 0LL;\n while (1) {\n v6 = a2;\n v7 = *v22;\n do {\n while (strcmp(v7, *v6)) {\n LABEL_6:\n if (++v6 == v4) goto LABEL_13;\n }\n if (v5 > 0) {\n v8 = (const char **)v26;\n while (strcmp(*v8, v7)) {\n if (++v8 == &v26[v21]) goto LABEL_12;\n }\n goto LABEL_6;\n }\n LABEL_12:\n ++v5;\n ++v6;\n v26[v21] = v7;\n v21 = v5;\n } while (v6 != v4);\n LABEL_13:\n if (++v22 == v24) goto LABEL_14;\n }\n }\n ++v22;\n } while (v22 != v24);\n v5 = 0;\n v21 = 0LL;\nLABEL_14:\n while (v5 <= 0) {\n if (++v23 == v24) {\n v9 = 0;\n goto LABEL_21;\n }\n }\n v9 = 0;\n do {\n v10 = (const char **)v26;\n v11 = *v23;\n do {\n if (!strcmp(v11, *v10)) {\n v12 = v9++;\n v26[v12 + 100] = v11;\n }\n ++v10;\n } while (&v26[v21] != v10);\n ++v23;\n } while (v23 != v24);\nLABEL_21:\n if (a4 <= 0) return v9 == 0;\nLABEL_22:\n v13 = 0LL;\n while (v5 <= 0) {\n if (a4 <= (int)++v13) {\n v14 = 0;\n goto LABEL_30;\n }\n }\n v14 = 0;\n do {\n v15 = (const char **)v26;\n v16 = a2[v13];\n do {\n if (!strcmp(v16, *v15)) {\n v17 = v14++;\n v26[v17 + 200] = v16;\n }\n ++v15;\n } while (&v26[v21] != v15);\n ++v13;\n } while (a4 > (int)v13);\nLABEL_30:\n result = 0;\n if (v9 == v14) {\n if (v9 > 0) {\n v19 = 0LL;\n v20 = 8LL * v9;\n while (!strcmp((const char *)v26[v19 / 8 + 100],\n (const char *)v26[v19 / 8 + 200])) {\n v19 += 8LL;\n if (v20 == v19) return 1;\n }\n return 0;\n }\n return 1;\n }\n return result;\n}", + "ida_pseudo_norm": "bool func0(const char **a1, const char **a2, int a3, int a4) {\n const char **v4;\n int v5;\n const char **v6;\n const char *v7;\n const char **v8;\n int v9;\n const char **v10;\n const char *v11;\n long long v12;\n long long v13;\n int v14;\n const char **v15;\n const char *v16;\n long long v17;\n bool result;\n unsigned long long v19;\n long long v20;\n long long v21;\n const char **v22;\n const char **v23;\n const char **v24;\n uint64_t v26[309];\n v26[301] = __readfsqword(40u);\n if (a3 <= 0) {\n if (a4 > 0) {\n v9 = 0;\n v5 = 0;\n v21 = 0LL;\n goto LABEL_22;\n }\n return 1;\n }\n v23 = a1;\n v22 = a1;\n v24 = &a1[a3];\n v4 = &a2[a4];\n do {\n if (a4 > 0) {\n v5 = 0;\n v21 = 0LL;\n while (1) {\n v6 = a2;\n v7 = *v22;\n do {\n while (strcmp(v7, *v6)) {\n LABEL_6:\n if (++v6 == v4) goto LABEL_13;\n }\n if (v5 > 0) {\n v8 = (const char **)v26;\n while (strcmp(*v8, v7)) {\n if (++v8 == &v26[v21]) goto LABEL_12;\n }\n goto LABEL_6;\n }\n LABEL_12:\n ++v5;\n ++v6;\n v26[v21] = v7;\n v21 = v5;\n } while (v6 != v4);\n LABEL_13:\n if (++v22 == v24) goto LABEL_14;\n }\n }\n ++v22;\n } while (v22 != v24);\n v5 = 0;\n v21 = 0LL;\nLABEL_14:\n while (v5 <= 0) {\n if (++v23 == v24) {\n v9 = 0;\n goto LABEL_21;\n }\n }\n v9 = 0;\n do {\n v10 = (const char **)v26;\n v11 = *v23;\n do {\n if (!strcmp(v11, *v10)) {\n v12 = v9++;\n v26[v12 + 100] = v11;\n }\n ++v10;\n } while (&v26[v21] != v10);\n ++v23;\n } while (v23 != v24);\nLABEL_21:\n if (a4 <= 0) return v9 == 0;\nLABEL_22:\n v13 = 0LL;\n while (v5 <= 0) {\n if (a4 <= (int)++v13) {\n v14 = 0;\n goto LABEL_30;\n }\n }\n v14 = 0;\n do {\n v15 = (const char **)v26;\n v16 = a2[v13];\n do {\n if (!strcmp(v16, *v15)) {\n v17 = v14++;\n v26[v17 + 200] = v16;\n }\n ++v15;\n } while (&v26[v21] != v15);\n ++v13;\n } while (a4 > (int)v13);\nLABEL_30:\n result = 0;\n if (v9 == v14) {\n if (v9 > 0) {\n v19 = 0LL;\n v20 = 8LL * v9;\n while (!strcmp((const char *)v26[v19 / 8 + 100],\n (const char *)v26[v19 / 8 + 200])) {\n v19 += 8LL;\n if (v20 == v19) return 1;\n }\n return 0;\n }\n return 1;\n }\n return result;\n}" + }, + { + "index": 509, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n % 2 == 0) {\n printf(\"Invalid Input\\n\");\n return -1;\n }\n int sm = 0;\n int count = 0;\n while (n >= 1) {\n count++;\n sm += n;\n n -= 2;\n }\n return sm / count;\n}", + "test": "int main() {\n\n assert(func0(9) == 5);\n\n assert(func0(5) == 3);\n\n assert(func0(11) == 6);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %edi,-0x14(%rbp)\nmov -0x14(%rbp),%eax\nand $0x1,%eax\ntest %eax,%eax\njne 1195 \nlea 0xe7f(%rip),%rdi\ncallq 1060 \nmov $0xffffffff,%eax\njmp 11c0 \nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11b3 \naddl $0x1,-0x4(%rbp)\nmov -0x14(%rbp),%eax\nadd %eax,-0x8(%rbp)\nsubl $0x2,-0x14(%rbp)\ncmpl $0x0,-0x14(%rbp)\njg 11a5 \nmov -0x8(%rbp),%eax\ncltd\nidivl -0x4(%rbp)\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov eax, [rbp+var_14]\nand eax, 1\ntest eax, eax\njnz short loc_1198\nlea rax, s; \"Invalid Input\"\nmov rdi, rax; s\ncall _puts\nmov eax, 0FFFFFFFFh\njmp short locret_11C3\nloc_1198:\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11B6\nloc_11A8:\nadd [rbp+var_4], 1\nmov eax, [rbp+var_14]\nadd [rbp+var_8], eax\nsub [rbp+var_14], 2\nloc_11B6:\ncmp [rbp+var_14], 0\njg short loc_11A8\nmov eax, [rbp+var_8]\ncdq\nidiv [rbp+var_4]\nlocret_11C3:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v2; // [rsp+Ch] [rbp-14h]\n int v3; // [rsp+18h] [rbp-8h]\n int v4; // [rsp+1Ch] [rbp-4h]\n\n v2 = a1;\n if ( (a1 & 1) != 0 )\n {\n v3 = 0;\n v4 = 0;\n while ( v2 > 0 )\n {\n ++v4;\n v3 += v2;\n v2 -= 2;\n }\n return (unsigned int)(v3 / v4);\n }\n else\n {\n puts(\"Invalid Input\");\n return 0xFFFFFFFFLL;\n }\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov eax, [rbp+var_14]\nand eax, 1\ntest eax, eax\njnz short loc_1198\nlea rax, s; \"Invalid Input\"\nmov rdi, rax; s\ncall _puts\nmov eax, 0FFFFFFFFh\njmp short locret_11C3\nloc_1198:\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11B6\nloc_11A8:\nadd [rbp+var_4], 1\nmov eax, [rbp+var_14]\nadd [rbp+var_8], eax\nsub [rbp+var_14], 2\nloc_11B6:\ncmp [rbp+var_14], 0\njg short loc_11A8\nmov eax, [rbp+var_8]\ncdq\nidiv [rbp+var_4]\nlocret_11C3:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n int v2; // [rsp+Ch] [rbp-14h]\n int v3; // [rsp+18h] [rbp-8h]\n int v4; // [rsp+1Ch] [rbp-4h]\n\n v2 = a1;\n if ( (a1 & 1) != 0 )\n {\n v3 = 0;\n v4 = 0;\n while ( v2 > 0 )\n {\n ++v4;\n v3 += v2;\n v2 -= 2;\n }\n return (unsigned int)(v3 / v4);\n }\n else\n {\n puts(\"Invalid Input\");\n return 0xFFFFFFFFLL;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n int v2;\n int v3;\n int v4;\n v2 = a1;\n if ((a1 & 1) != 0) {\n v3 = 0;\n v4 = 0;\n while (v2 > 0) {\n ++v4;\n v3 += v2;\n v2 -= 2;\n }\n return (unsigned int)(v3 / v4);\n } else {\n puts(\"Invalid Input\");\n return 4294967295LL;\n }\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v2;\n int v3;\n int v4;\n v2 = a1;\n if ((a1 & 1) != 0) {\n v3 = 0;\n v4 = 0;\n while (v2 > 0) {\n ++v4;\n v3 += v2;\n v2 -= 2;\n }\n return (unsigned int)(v3 / v4);\n } else {\n puts(\"Invalid Input\");\n return 4294967295LL;\n }\n}" + }, + { + "index": 509, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n % 2 == 0) {\n printf(\"Invalid Input\\n\");\n return -1;\n }\n int sm = 0;\n int count = 0;\n while (n >= 1) {\n count++;\n sm += n;\n n -= 2;\n }\n return sm / count;\n}", + "test": "int main() {\n\n assert(func0(9) == 5);\n\n assert(func0(5) == 3);\n\n assert(func0(11) == 6);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest $0x1,%dil\nje 11a7 \nmov %edi,%edx\nmov $0x0,%ecx\nmov $0x0,%eax\ntest %edi,%edi\njle 11a3 \nlea -0x1(%rdi),%ecx\nsub $0x2,%edx\nmov %ecx,%eax\nand $0xfffffffe,%eax\nsub %eax,%edx\nmov $0x0,%eax\nadd %edi,%eax\nsub $0x2,%edi\ncmp %edx,%edi\njne 1195 \nshr %ecx\nadd $0x1,%ecx\ncltd\nidiv %ecx\nretq\nsub $0x8,%rsp\nlea 0xe52(%rip),%rdi\ncallq 1060 \nmov $0xffffffff,%eax\nadd $0x8,%rsp\nretq\n", + "ida_asm": "func0:\nendbr64\ntest dil, 1\njz short loc_11A5\nmov ecx, 0\nmov eax, 0\ntest edi, edi\njle short loc_11A1\nlea ecx, [rdi-1]\nlea edx, [rdi-2]\nmov eax, ecx\nand eax, 0FFFFFFFEh\nsub edx, eax\nmov eax, 0\nloc_1193:\nadd eax, edi\nsub edi, 2\ncmp edi, edx\njnz short loc_1193\nshr ecx, 1\nadd ecx, 1\nloc_11A1:\ncdq\nidiv ecx\nretn\nloc_11A5:\nsub rsp, 8\nlea rdi, s; \"Invalid Input\"\ncall _puts\nmov eax, 0FFFFFFFFh\nadd rsp, 8\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // ecx\n int v2; // eax\n unsigned int v3; // ecx\n unsigned int v4; // edx\n\n if ( (a1 & 1) != 0 )\n {\n v1 = 0;\n v2 = 0;\n if ( a1 > 0 )\n {\n v3 = a1 - 1;\n v4 = a1 - 2 - ((a1 - 1) & 0xFFFFFFFE);\n v2 = 0;\n do\n {\n v2 += a1;\n a1 -= 2;\n }\n while ( a1 != v4 );\n v1 = (v3 >> 1) + 1;\n }\n return (unsigned int)(v2 / v1);\n }\n else\n {\n puts(\"Invalid Input\");\n return 0xFFFFFFFFLL;\n }\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest dil, 1\njz short loc_11A5\nmov ecx, 0\nmov eax, 0\ntest edi, edi\njle short loc_11A1\nlea ecx, [rdi-1]\nlea edx, [rdi-2]\nmov eax, ecx\nand eax, 0FFFFFFFEh\nsub edx, eax\nmov eax, 0\nloc_1193:\nadd eax, edi\nsub edi, 2\ncmp edi, edx\njnz short loc_1193\nshr ecx, 1\nadd ecx, 1\nloc_11A1:\ncdq\nidiv ecx\nretn\nloc_11A5:\nsub rsp, 8\nlea rdi, s; \"Invalid Input\"\ncall _puts\nmov eax, 0FFFFFFFFh\nadd rsp, 8\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n int v1; // ecx\n int v2; // eax\n unsigned int v3; // ecx\n unsigned int v4; // edx\n\n if ( (a1 & 1) != 0 )\n {\n v1 = 0;\n v2 = 0;\n if ( a1 > 0 )\n {\n v3 = a1 - 1;\n v4 = a1 - 2 - ((a1 - 1) & 0xFFFFFFFE);\n v2 = 0;\n do\n {\n v2 += a1;\n a1 -= 2;\n }\n while ( a1 != v4 );\n v1 = (v3 >> 1) + 1;\n }\n return (unsigned int)(v2 / v1);\n }\n else\n {\n puts(\"Invalid Input\");\n return 0xFFFFFFFFLL;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n int v1;\n int v2;\n unsigned int v3;\n unsigned int v4;\n if ((a1 & 1) != 0) {\n v1 = 0;\n v2 = 0;\n if (a1 > 0) {\n v3 = a1 - 1;\n v4 = a1 - 2 - ((a1 - 1) & 4294967294);\n v2 = 0;\n do {\n v2 += a1;\n a1 -= 2;\n } while (a1 != v4);\n v1 = (v3 >> 1) + 1;\n }\n return (unsigned int)(v2 / v1);\n } else {\n puts(\"Invalid Input\");\n return 4294967295LL;\n }\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v2;\n unsigned int v3;\n unsigned int v4;\n if ((a1 & 1) != 0) {\n v1 = 0;\n v2 = 0;\n if (a1 > 0) {\n v3 = a1 - 1;\n v4 = a1 - 2 - ((a1 - 1) & 4294967294);\n v2 = 0;\n do {\n v2 += a1;\n a1 -= 2;\n } while (a1 != v4);\n v1 = (v3 >> 1) + 1;\n }\n return (unsigned int)(v2 / v1);\n } else {\n puts(\"Invalid Input\");\n return 4294967295LL;\n }\n}" + }, + { + "index": 510, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n, int k) {\n int dp[k + 1][n + 1];\n for (int i = 0; i <= k; i++) {\n for (int j = 0; j <= n; j++) {\n dp[i][j] = 0;\n }\n }\n for (int i = 1; i <= k; i++) {\n for (int j = 1; j <= n; j++) {\n dp[i][j] = dp[i][j - 1];\n if (arr[j - 1] <= i && arr[j - 1] > 0) {\n dp[i][j] += dp[i / arr[j - 1]][j - 1] + 1;\n }\n }\n }\n return dp[k][n];\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4};\n\n int arr2[] = {4, 8, 7, 2};\n\n int arr3[] = {5, 6, 7, 8};\n\n\n\n assert(func0(arr1, 4, 10) == 11);\n\n assert(func0(arr2, 4, 50) == 9);\n\n assert(func0(arr3, 4, 15) == 4);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0x58,%rsp\nmov %rdi,-0x68(%rbp)\nmov %esi,-0x6c(%rbp)\nmov %edx,-0x70(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nmov %rsp,%rax\nmov %rax,-0x78(%rbp)\nmov -0x6c(%rbp),%eax\nlea 0x1(%rax),%esi\nmov -0x70(%rbp),%eax\nlea 0x1(%rax),%edi\nmovslq %esi,%rax\nsub $0x1,%rax\nmov %rax,-0x50(%rbp)\nmovslq %esi,%rax\nmov %rax,%rcx\nmov $0x0,%ebx\nmovslq %esi,%rax\nlea 0x0(,%rax,4),%rcx\nmovslq %edi,%rax\nsub $0x1,%rax\nmov %rax,-0x48(%rbp)\nmovslq %esi,%rax\nmov %rax,%r14\nmov $0x0,%r15d\nmovslq %edi,%rax\nmov %rax,%r12\nmov $0x0,%r13d\nmov %r15,%rdx\nimul %r12,%rdx\nmov %r13,%rax\nimul %r14,%rax\nlea (%rdx,%rax,1),%rbx\nmov %r14,%rax\nmul %r12\nadd %rdx,%rbx\nmov %rbx,%rdx\nmovslq %esi,%rax\nmov %rax,%r10\nmov $0x0,%r11d\nmovslq %edi,%rax\nmov %rax,%r8\nmov $0x0,%r9d\nmov %r11,%rdx\nimul %r8,%rdx\nmov %r9,%rax\nimul %r10,%rax\nlea (%rdx,%rax,1),%rbx\nmov %r10,%rax\nmul %r8\nlea (%rbx,%rdx,1),%r8\nmov %r8,%rdx\nmovslq %esi,%rdx\nmovslq %edi,%rax\nimul %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%ebx\nmov $0x0,%edx\ndiv %rbx\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rbx\nsub %rdx,%rbx\nmov %rbx,%rdx\ncmp %rdx,%rsp\nje 129c \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 1285 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 12c6 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x40(%rbp)\nmovl $0x0,-0x54(%rbp)\njmp 1320 \nmovl $0x0,-0x58(%rbp)\njmp 1314 \nmov %rcx,%rdi\nshr $0x2,%rdi\nmov -0x40(%rbp),%rax\nmov -0x58(%rbp),%edx\nmovslq %edx,%rsi\nmov -0x54(%rbp),%edx\nmovslq %edx,%rdx\nimul %rdi,%rdx\nadd %rsi,%rdx\nmovl $0x0,(%rax,%rdx,4)\naddl $0x1,-0x58(%rbp)\nmov -0x58(%rbp),%eax\ncmp -0x6c(%rbp),%eax\njle 12eb \naddl $0x1,-0x54(%rbp)\nmov -0x54(%rbp),%eax\ncmp -0x70(%rbp),%eax\njle 12e2 \nmovl $0x1,-0x5c(%rbp)\njmpq 145d \nmovl $0x1,-0x60(%rbp)\njmpq 144d \nmov %rcx,%rdi\nshr $0x2,%rdi\nmov -0x60(%rbp),%eax\nlea -0x1(%rax),%edx\nmov %rcx,%r8\nshr $0x2,%r8\nmov -0x40(%rbp),%rax\nmovslq %edx,%rsi\nmov -0x5c(%rbp),%edx\nmovslq %edx,%rdx\nimul %rdi,%rdx\nadd %rsi,%rdx\nmov (%rax,%rdx,4),%edx\nmov -0x40(%rbp),%rax\nmov -0x60(%rbp),%esi\nmovslq %esi,%rdi\nmov -0x5c(%rbp),%esi\nmovslq %esi,%rsi\nimul %r8,%rsi\nadd %rdi,%rsi\nmov %edx,(%rax,%rsi,4)\nmov -0x60(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rdx\nmov -0x68(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x5c(%rbp)\njl 1449 \nmov -0x60(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rdx\nmov -0x68(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ntest %eax,%eax\njle 1449 \nmov %rcx,%rdi\nshr $0x2,%rdi\nmov -0x40(%rbp),%rax\nmov -0x60(%rbp),%edx\nmovslq %edx,%rsi\nmov -0x5c(%rbp),%edx\nmovslq %edx,%rdx\nimul %rdi,%rdx\nadd %rsi,%rdx\nmov (%rax,%rdx,4),%esi\nmov %rcx,%r8\nshr $0x2,%r8\nmov -0x60(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rdx\nmov -0x68(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%ebx\nmov -0x5c(%rbp),%eax\ncltd\nidiv %ebx\nmov %eax,%r9d\nmov -0x60(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x40(%rbp),%rax\nmovslq %edx,%rdi\nmovslq %r9d,%rdx\nimul %r8,%rdx\nadd %rdi,%rdx\nmov (%rax,%rdx,4),%eax\nadd $0x1,%eax\nmov %rcx,%r8\nshr $0x2,%r8\nadd %eax,%esi\nmov -0x40(%rbp),%rax\nmov -0x60(%rbp),%edx\nmovslq %edx,%rdi\nmov -0x5c(%rbp),%edx\nmovslq %edx,%rdx\nimul %r8,%rdx\nadd %rdi,%rdx\nmov %esi,(%rax,%rdx,4)\naddl $0x1,-0x60(%rbp)\nmov -0x60(%rbp),%eax\ncmp -0x6c(%rbp),%eax\njle 1340 \naddl $0x1,-0x5c(%rbp)\nmov -0x5c(%rbp),%eax\ncmp -0x70(%rbp),%eax\njle 1334 \nshr $0x2,%rcx\nmov %rcx,%rsi\nmov -0x40(%rbp),%rax\nmov -0x6c(%rbp),%edx\nmovslq %edx,%rcx\nmov -0x70(%rbp),%edx\nmovslq %edx,%rdx\nimul %rsi,%rdx\nadd %rcx,%rdx\nmov (%rax,%rdx,4),%eax\nmov -0x78(%rbp),%rsp\nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\nje 14a2 \ncallq 1060 <__stack_chk_fail@plt>\nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 48h\nmov [rbp+var_48], rdi\nmov [rbp+var_4C], esi\nmov [rbp+var_50], edx\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov rax, rsp\nmov rbx, rax\nmov eax, [rbp+var_4C]\nlea r8d, [rax+1]\nmov eax, [rbp+var_50]\nlea r9d, [rax+1]\nmovsxd rax, r8d\nsub rax, 1\nmov [rbp+var_30], rax\nmovsxd rax, r8d\nlea rcx, ds:0[rax*4]\nmovsxd rax, r9d\nsub rax, 1\nmov [rbp+var_28], rax\nmovsxd rax, r8d\nmov rsi, rax\nmov edi, 0\nmovsxd rax, r9d\nmov rax, rax\nmov edx, 0\nmov r11, rdi\nimul r11, rax\nmov r10, rdx\nimul r10, rsi\nadd r10, r11\nmul rsi\nlea rsi, [r10+rdx]\nmov rdx, rsi\nmovsxd rax, r8d\nmov rsi, rax\nmov edi, 0\nmovsxd rax, r9d\nmov rax, rax\nmov edx, 0\nmov r11, rdi\nimul r11, rax\nmov r10, rdx\nimul r10, rsi\nadd r10, r11\nmul rsi\nlea rsi, [r10+rdx]\nmov rdx, rsi\nmovsxd rdx, r8d\nmovsxd rax, r9d\nimul rax, rdx\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rsi, rax\nand rsi, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rsi\nloc_1265:\ncmp rsp, rdx\njz short loc_127C\nsub rsp, 1000h\nor [rsp+1050h+var_58], 0\njmp short loc_1265\nloc_127C:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_12A6\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_12A6:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_20], rax\nmov [rbp+var_40], 0\njmp short loc_1300\nloc_12C2:\nmov [rbp+var_3C], 0\njmp short loc_12F4\nloc_12CB:\nmov rdi, rcx\nshr rdi, 2\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_3C]\nmovsxd rsi, edx\nmov edx, [rbp+var_40]\nmovsxd rdx, edx\nimul rdx, rdi\nadd rdx, rsi\nmov dword ptr [rax+rdx*4], 0\nadd [rbp+var_3C], 1\nloc_12F4:\nmov eax, [rbp+var_3C]\ncmp eax, [rbp+var_4C]\njle short loc_12CB\nadd [rbp+var_40], 1\nloc_1300:\nmov eax, [rbp+var_40]\ncmp eax, [rbp+var_50]\njle short loc_12C2\nmov [rbp+var_38], 1\njmp loc_143D\nloc_1314:\nmov [rbp+var_34], 1\njmp loc_142D\nloc_1320:\nmov rdi, rcx\nshr rdi, 2\nmov eax, [rbp+var_34]\nlea edx, [rax-1]\nmov r8, rcx\nshr r8, 2\nmov rax, [rbp+var_20]\nmovsxd rsi, edx\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nimul rdx, rdi\nadd rdx, rsi\nmov edx, [rax+rdx*4]\nmov rax, [rbp+var_20]\nmov esi, [rbp+var_34]\nmovsxd rdi, esi\nmov esi, [rbp+var_38]\nmovsxd rsi, esi\nimul rsi, r8\nadd rsi, rdi\nmov [rax+rsi*4], edx\nmov eax, [rbp+var_34]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_38], eax\njl loc_1429\nmov eax, [rbp+var_34]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njle loc_1429\nmov rdi, rcx\nshr rdi, 2\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_34]\nmovsxd rsi, edx\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nimul rdx, rdi\nadd rdx, rsi\nmov esi, [rax+rdx*4]\nmov r8, rcx\nshr r8, 2\nmov eax, [rbp+var_34]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov edi, [rax]\nmov eax, [rbp+var_38]\ncdq\nidiv edi\nmov r9d, eax\nmov eax, [rbp+var_34]\nlea edx, [rax-1]\nmov rax, [rbp+var_20]\nmovsxd rdi, edx\nmovsxd rdx, r9d\nimul rdx, r8\nadd rdx, rdi\nmov eax, [rax+rdx*4]\nadd eax, 1\nmov r8, rcx\nshr r8, 2\nadd esi, eax\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_34]\nmovsxd rdi, edx\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nimul rdx, r8\nadd rdx, rdi\nmov [rax+rdx*4], esi\nloc_1429:\nadd [rbp+var_34], 1\nloc_142D:\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_4C]\njle loc_1320\nadd [rbp+var_38], 1\nloc_143D:\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_50]\njle loc_1314\nshr rcx, 2\nmov rsi, rcx\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_4C]\nmovsxd rcx, edx\nmov edx, [rbp+var_50]\nmovsxd rdx, edx\nimul rdx, rsi\nadd rdx, rcx\nmov eax, [rax+rdx*4]\nmov rsp, rbx\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njz short loc_1481\ncall ___stack_chk_fail\nloc_1481:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n unsigned __int64 v3; // rcx\n unsigned __int64 v4; // rax\n void *v5; // rsp\n int v7; // [rsp+8h] [rbp-50h] BYREF\n int v8; // [rsp+Ch] [rbp-4Ch]\n __int64 v9; // [rsp+10h] [rbp-48h]\n int i; // [rsp+18h] [rbp-40h]\n int j; // [rsp+1Ch] [rbp-3Ch]\n int k; // [rsp+20h] [rbp-38h]\n int m; // [rsp+24h] [rbp-34h]\n __int64 v14; // [rsp+28h] [rbp-30h]\n __int64 v15; // [rsp+30h] [rbp-28h]\n int *v16; // [rsp+38h] [rbp-20h]\n unsigned __int64 v17; // [rsp+40h] [rbp-18h]\n\n v9 = a1;\n v8 = a2;\n v7 = a3;\n v17 = __readfsqword(0x28u);\n v14 = a2 + 1 - 1LL;\n v3 = 4LL * (a2 + 1);\n v15 = a3 + 1 - 1LL;\n v4 = 16 * ((4 * (a2 + 1) * (__int64)(a3 + 1) + 15) / 0x10uLL);\n while ( &v7 != (int *)((char *)&v7 - (v4 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v5 = alloca(v4 & 0xFFF);\n if ( (v4 & 0xFFF) != 0 )\n *(_QWORD *)((char *)&v7 + (v4 & 0xFFF) - 8) = *(_QWORD *)((char *)&v7 + (v4 & 0xFFF) - 8);\n v16 = &v7;\n for ( i = 0; i <= v7; ++i )\n {\n for ( j = 0; j <= v8; ++j )\n v16[j + (v3 >> 2) * i] = 0;\n }\n for ( k = 1; k <= v7; ++k )\n {\n for ( m = 1; m <= v8; ++m )\n {\n v16[m + (v3 >> 2) * k] = v16[m - 1 + (v3 >> 2) * k];\n if ( k >= *(_DWORD *)(4LL * m - 4 + v9) && *(int *)(4LL * m - 4 + v9) > 0 )\n v16[m + (v3 >> 2) * k] += v16[m - 1 + (v3 >> 2) * (k / *(_DWORD *)(4LL * m - 4 + v9))] + 1;\n }\n }\n return (unsigned int)v16[v8 + (v3 >> 2) * v7];\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 48h\nmov [rbp+var_48], rdi\nmov [rbp+var_4C], esi\nmov [rbp+var_50], edx\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov rax, rsp\nmov rbx, rax\nmov eax, [rbp+var_4C]\nlea r8d, [rax+1]\nmov eax, [rbp+var_50]\nlea r9d, [rax+1]\nmovsxd rax, r8d\nsub rax, 1\nmov [rbp+var_30], rax\nmovsxd rax, r8d\nlea rcx, ds:0[rax*4]\nmovsxd rax, r9d\nsub rax, 1\nmov [rbp+var_28], rax\nmovsxd rax, r8d\nmov rsi, rax\nmov edi, 0\nmovsxd rax, r9d\nmov rax, rax\nmov edx, 0\nmov r11, rdi\nimul r11, rax\nmov r10, rdx\nimul r10, rsi\nadd r10, r11\nmul rsi\nlea rsi, [r10+rdx]\nmov rdx, rsi\nmovsxd rax, r8d\nmov rsi, rax\nmov edi, 0\nmovsxd rax, r9d\nmov rax, rax\nmov edx, 0\nmov r11, rdi\nimul r11, rax\nmov r10, rdx\nimul r10, rsi\nadd r10, r11\nmul rsi\nlea rsi, [r10+rdx]\nmov rdx, rsi\nmovsxd rdx, r8d\nmovsxd rax, r9d\nimul rax, rdx\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rsi, rax\nand rsi, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rsi\nloc_1265:\ncmp rsp, rdx\njz short loc_127C\nsub rsp, 1000h\nor [rsp+1050h+var_58], 0\njmp short loc_1265\nloc_127C:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_12A6\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_12A6:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_20], rax\nmov [rbp+var_40], 0\njmp short loc_1300\nloc_12C2:\nmov [rbp+var_3C], 0\njmp short loc_12F4\nloc_12CB:\nmov rdi, rcx\nshr rdi, 2\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_3C]\nmovsxd rsi, edx\nmov edx, [rbp+var_40]\nmovsxd rdx, edx\nimul rdx, rdi\nadd rdx, rsi\nmov dword ptr [rax+rdx*4], 0\nadd [rbp+var_3C], 1\nloc_12F4:\nmov eax, [rbp+var_3C]\ncmp eax, [rbp+var_4C]\njle short loc_12CB\nadd [rbp+var_40], 1\nloc_1300:\nmov eax, [rbp+var_40]\ncmp eax, [rbp+var_50]\njle short loc_12C2\nmov [rbp+var_38], 1\njmp loc_143D\nloc_1314:\nmov [rbp+var_34], 1\njmp loc_142D\nloc_1320:\nmov rdi, rcx\nshr rdi, 2\nmov eax, [rbp+var_34]\nlea edx, [rax-1]\nmov r8, rcx\nshr r8, 2\nmov rax, [rbp+var_20]\nmovsxd rsi, edx\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nimul rdx, rdi\nadd rdx, rsi\nmov edx, [rax+rdx*4]\nmov rax, [rbp+var_20]\nmov esi, [rbp+var_34]\nmovsxd rdi, esi\nmov esi, [rbp+var_38]\nmovsxd rsi, esi\nimul rsi, r8\nadd rsi, rdi\nmov [rax+rsi*4], edx\nmov eax, [rbp+var_34]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_38], eax\njl loc_1429\nmov eax, [rbp+var_34]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njle loc_1429\nmov rdi, rcx\nshr rdi, 2\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_34]\nmovsxd rsi, edx\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nimul rdx, rdi\nadd rdx, rsi\nmov esi, [rax+rdx*4]\nmov r8, rcx\nshr r8, 2\nmov eax, [rbp+var_34]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov edi, [rax]\nmov eax, [rbp+var_38]\ncdq\nidiv edi\nmov r9d, eax\nmov eax, [rbp+var_34]\nlea edx, [rax-1]\nmov rax, [rbp+var_20]\nmovsxd rdi, edx\nmovsxd rdx, r9d\nimul rdx, r8\nadd rdx, rdi\nmov eax, [rax+rdx*4]\nadd eax, 1\nmov r8, rcx\nshr r8, 2\nadd esi, eax\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_34]\nmovsxd rdi, edx\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nimul rdx, r8\nadd rdx, rdi\nmov [rax+rdx*4], esi\nloc_1429:\nadd [rbp+var_34], 1\nloc_142D:\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_4C]\njle loc_1320\nadd [rbp+var_38], 1\nloc_143D:\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_50]\njle loc_1314\nshr rcx, 2\nmov rsi, rcx\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_4C]\nmovsxd rcx, edx\nmov edx, [rbp+var_50]\nmovsxd rdx, edx\nimul rdx, rsi\nadd rdx, rcx\nmov eax, [rax+rdx*4]\nmov rsp, rbx\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njz short loc_1481\ncall ___stack_chk_fail\nloc_1481:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n unsigned __int64 v3; // rcx\n unsigned __int64 v4; // rax\n void *v5; // rsp\n int v7; // [rsp+8h] [rbp-50h] BYREF\n int v8; // [rsp+Ch] [rbp-4Ch]\n __int64 v9; // [rsp+10h] [rbp-48h]\n int i; // [rsp+18h] [rbp-40h]\n int j; // [rsp+1Ch] [rbp-3Ch]\n int k; // [rsp+20h] [rbp-38h]\n int m; // [rsp+24h] [rbp-34h]\n __int64 v14; // [rsp+28h] [rbp-30h]\n __int64 v15; // [rsp+30h] [rbp-28h]\n int *v16; // [rsp+38h] [rbp-20h]\n unsigned __int64 v17; // [rsp+40h] [rbp-18h]\n\n v9 = a1;\n v8 = a2;\n v7 = a3;\n v17 = __readfsqword(0x28u);\n v14 = a2 + 1 - 1LL;\n v3 = 4LL * (a2 + 1);\n v15 = a3 + 1 - 1LL;\n v4 = 16 * ((4 * (a2 + 1) * (__int64)(a3 + 1) + 15) / 0x10uLL);\n while ( &v7 != (int *)((char *)&v7 - (v4 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v5 = alloca(v4 & 0xFFF);\n if ( (v4 & 0xFFF) != 0 )\n *(_QWORD *)((char *)&v7 + (v4 & 0xFFF) - 8) = *(_QWORD *)((char *)&v7 + (v4 & 0xFFF) - 8);\n v16 = &v7;\n for ( i = 0; i <= v7; ++i )\n {\n for ( j = 0; j <= v8; ++j )\n v16[j + (v3 >> 2) * i] = 0;\n }\n for ( k = 1; k <= v7; ++k )\n {\n for ( m = 1; m <= v8; ++m )\n {\n v16[m + (v3 >> 2) * k] = v16[m - 1 + (v3 >> 2) * k];\n if ( k >= *(_DWORD *)(4LL * m - 4 + v9) && *(int *)(4LL * m - 4 + v9) > 0 )\n v16[m + (v3 >> 2) * k] += v16[m - 1 + (v3 >> 2) * (k / *(_DWORD *)(4LL * m - 4 + v9))] + 1;\n }\n }\n return (unsigned int)v16[v8 + (v3 >> 2) * v7];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n unsigned long long v3;\n unsigned long long v4;\n void *v5;\n int v7;\n int v8;\n long long v9;\n int i;\n int j;\n int k;\n int m;\n long long v14;\n long long v15;\n int *v16;\n unsigned long long v17;\n v9 = a1;\n v8 = a2;\n v7 = a3;\n v17 = __readfsqword(40u);\n v14 = a2 + 1 - 1LL;\n v3 = 4LL * (a2 + 1);\n v15 = a3 + 1 - 1LL;\n v4 = 16 * ((4 * (a2 + 1) * (long long)(a3 + 1) + 15) / 16uLL);\n while (&v7 != (int *)((char *)&v7 - (v4 & 18446744073709547520LL)))\n ;\n v5 = alloca(v4 & 4095);\n if ((v4 & 4095) != 0)\n *(uint64_t *)((char *)&v7 + (v4 & 4095) - 8) =\n *(uint64_t *)((char *)&v7 + (v4 & 4095) - 8);\n v16 = &v7;\n for (i = 0; i <= v7; ++i) {\n for (j = 0; j <= v8; ++j) v16[j + (v3 >> 2) * i] = 0;\n }\n for (k = 1; k <= v7; ++k) {\n for (m = 1; m <= v8; ++m) {\n v16[m + (v3 >> 2) * k] = v16[m - 1 + (v3 >> 2) * k];\n if (k >= *(uint32_t *)(4LL * m - 4 + v9) &&\n *(int *)(4LL * m - 4 + v9) > 0)\n v16[m + (v3 >> 2) * k] +=\n v16[m - 1 + (v3 >> 2) * (k / *(uint32_t *)(4LL * m - 4 + v9))] + 1;\n }\n }\n return (unsigned int)v16[v8 + (v3 >> 2) * v7];\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n unsigned long long v3;\n unsigned long long v4;\n void *v5;\n int v7;\n int v8;\n long long v9;\n int i;\n int j;\n int k;\n int m;\n long long v14;\n long long v15;\n int *v16;\n unsigned long long v17;\n v9 = a1;\n v8 = a2;\n v7 = a3;\n v17 = __readfsqword(40u);\n v14 = a2 + 1 - 1LL;\n v3 = 4LL * (a2 + 1);\n v15 = a3 + 1 - 1LL;\n v4 = 16 * ((4 * (a2 + 1) * (long long)(a3 + 1) + 15) / 16uLL);\n while (&v7 != (int *)((char *)&v7 - (v4 & 18446744073709547520LL)))\n ;\n v5 = alloca(v4 & 4095);\n if ((v4 & 4095) != 0)\n *(uint64_t *)((char *)&v7 + (v4 & 4095) - 8) =\n *(uint64_t *)((char *)&v7 + (v4 & 4095) - 8);\n v16 = &v7;\n for (i = 0; i <= v7; ++i) {\n for (j = 0; j <= v8; ++j) v16[j + (v3 >> 2) * i] = 0;\n }\n for (k = 1; k <= v7; ++k) {\n for (m = 1; m <= v8; ++m) {\n v16[m + (v3 >> 2) * k] = v16[m - 1 + (v3 >> 2) * k];\n if (k >= *(uint32_t *)(4LL * m - 4 + v9) &&\n *(int *)(4LL * m - 4 + v9) > 0)\n v16[m + (v3 >> 2) * k] +=\n v16[m - 1 + (v3 >> 2) * (k / *(uint32_t *)(4LL * m - 4 + v9))] + 1;\n }\n }\n return (unsigned int)v16[v8 + (v3 >> 2) * v7];\n}" + }, + { + "index": 510, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n, int k) {\n int dp[k + 1][n + 1];\n for (int i = 0; i <= k; i++) {\n for (int j = 0; j <= n; j++) {\n dp[i][j] = 0;\n }\n }\n for (int i = 1; i <= k; i++) {\n for (int j = 1; j <= n; j++) {\n dp[i][j] = dp[i][j - 1];\n if (arr[j - 1] <= i && arr[j - 1] > 0) {\n dp[i][j] += dp[i / arr[j - 1]][j - 1] + 1;\n }\n }\n }\n return dp[k][n];\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4};\n\n int arr2[] = {4, 8, 7, 2};\n\n int arr3[] = {5, 6, 7, 8};\n\n\n\n assert(func0(arr1, 4, 10) == 11);\n\n assert(func0(arr2, 4, 50) == 9);\n\n assert(func0(arr3, 4, 15) == 4);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0x38,%rsp\nmov %rdi,%rbx\nmov %esi,%r13d\nmov %edx,-0x54(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nlea 0x1(%rsi),%eax\nmovslq %eax,%rcx\nlea 0x0(,%rcx,4),%rax\nmov %rax,-0x48(%rbp)\nadd $0x1,%edx\nmovslq %edx,%rax\nimul %rcx,%rax\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffffff0,%rdx\nand $0xfffffffffffff000,%rax\nmov %rsp,%rsi\nsub %rax,%rsi\nmov %rsi,%rax\ncmp %rax,%rsp\nje 11e7 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11d0 \nmov %rdx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 11fd \norq $0x0,-0x8(%rsp,%rax,1)\nmov %rsp,%rax\nmov %rax,-0x60(%rbp)\nmov %rax,%r15\nmov -0x54(%rbp),%ecx\ntest %ecx,%ecx\njs 124f \nmov %r13d,%esi\nlea 0x4(%rax,%rsi,4),%rdx\nlea 0x1(%rcx),%edi\nmov $0x0,%ecx\nnot %rsi\nshl $0x2,%rsi\nmov -0x48(%rbp),%r8\njmp 1235 \nadd $0x1,%ecx\nadd %r8,%rdx\ncmp %edi,%ecx\nje 124f \nlea (%rsi,%rdx,1),%rax\ntest %r13d,%r13d\njs 122b \nmovl $0x0,(%rax)\nadd $0x4,%rax\ncmp %rdx,%rax\njne 123e \njmp 122b \nmov -0x54(%rbp),%esi\ntest %esi,%esi\njle 12ea \nmov -0x48(%rbp),%rdx\nmov %rdx,%rax\nshr $0x2,%rax\nmov -0x60(%rbp),%rcx\nlea 0x4(%rcx,%rdx,1),%r14\nlea 0x1(%rsi),%edx\nmov %edx,-0x50(%rbp)\nmov $0x1,%esi\nlea -0x1(%r13),%r12d\nmov %r13d,-0x4c(%rbp)\nmov %rax,%r13\njmp 12d6 \nlea 0x1(%rdi),%rax\nadd $0x4,%rcx\ncmp %rdi,%r12\nje 12ca \nmov %rax,%rdi\nmov -0x4(%rcx),%r10d\nmov %r10d,(%rcx)\nmov (%rbx,%rdi,4),%r8d\ntest %r8d,%r8d\njle 1286 \ncmp %esi,%r8d\njg 1286 \nmovslq %edi,%r9\nmov %esi,%eax\ncltd\nidiv %r8d\ncltq\nimul %r13,%rax\nadd %r9,%rax\nmov (%r15,%rax,4),%eax\nlea 0x1(%r10,%rax,1),%eax\nmov %eax,(%rcx)\njmp 1286 \nadd $0x1,%esi\nadd -0x48(%rbp),%r14\ncmp -0x50(%rbp),%esi\nje 12e6 \nmov %r14,%rcx\nmov $0x0,%edi\ncmpl $0x0,-0x4c(%rbp)\njg 1296 \njmp 12ca \nmov -0x4c(%rbp),%r13d\nmovslq %r13d,%r13\nmovslq -0x54(%rbp),%rdx\nmov -0x48(%rbp),%rax\nshr $0x2,%rax\nimul %rdx,%rax\nadd %r13,%rax\nmov -0x60(%rbp),%rbx\nmov (%rbx,%rax,4),%eax\nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\njne 1325 \nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 38h\nmov rbx, rdi\nmov edi, esi\nmov ecx, edx\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nlea edx, [rsi+1]\nmovsxd rdx, edx\nlea r8, ds:0[rdx*4]\nlea eax, [rcx+1]\ncdqe\nimul rax, rdx\nlea rax, ds:0Fh[rax*4]\nmov rsi, rax\nand rsi, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11C6:\ncmp rsp, rdx\njz short loc_11DD\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\njmp short loc_11C6\nloc_11DD:\nmov rax, rsi\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11F3\nor [rsp+rax+60h+var_68], 0\nloc_11F3:\nmov r13, rsp\ntest ecx, ecx\njs loc_12E2\nmov r14, r8\nshr r14, 2\nmov esi, edi\nlea rdx, [r13+rsi*4+4]\nlea r10d, [rcx+1]\nmov r9d, 0\nnot rsi\nshl rsi, 2\njmp short loc_123D\nloc_121F:\nmov dword ptr [rax], 0\nadd rax, 4\ncmp rax, rdx\njnz short loc_121F\nloc_122E:\nlea eax, [r9+1]\nadd rdx, r8\ncmp eax, r10d\njz short loc_1247\nmov r9d, eax\nloc_123D:\nlea rax, [rsi+rdx]\ntest edi, edi\njns short loc_121F\njmp short loc_122E\nloc_1247:\ntest ecx, ecx\njle loc_12E2\nlea r15, [r13+r8+4]\nmov r10d, 1\nmov r12d, edi\nmov [rbp+var_50], r8\nmov [rbp+var_54], r9d\nmov r8d, edi\nmov [rbp+var_58], ecx\njmp short loc_12C5\nloc_126D:\nadd rsi, 1\nadd rcx, 4\ncmp rsi, r12\njz short loc_12AD\nloc_127A:\nmov r9d, [rcx-4]\nmov [rcx], r9d\nmov edi, [rbx+rsi*4]\ntest edi, edi\njle short loc_126D\ncmp edi, r10d\njg short loc_126D\nmovsxd r11, esi\nmov eax, r10d\ncdq\nidiv edi\ncdqe\nimul rax, r14\nadd r11, rax\nmov eax, [r13+r11*4+0]\nlea eax, [r9+rax+1]\nmov [rcx], eax\njmp short loc_126D\nloc_12AD:\nmov r15, [rbp+var_48]\nloc_12B1:\nlea eax, [r10+1]\nmov rdx, [rbp+var_50]\nadd r15, rdx\ncmp [rbp+var_54], r10d\njz short loc_12D8\nmov r10d, eax\nloc_12C5:\nmov rcx, r15\nmov esi, 0\ntest r8d, r8d\njle short loc_12B1\nmov [rbp+var_48], r15\njmp short loc_127A\nloc_12D8:\nmov edi, r8d\nmov r8, [rbp+var_50]\nmov ecx, [rbp+var_58]\nloc_12E2:\nmovsxd rax, edi\nmovsxd rcx, ecx\nshr r8, 2\nimul rcx, r8\nadd rax, rcx\nmov eax, [r13+rax*4+0]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_1316\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1316:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n int v4; // edi\n __int64 v6; // rdx\n unsigned __int64 v7; // r8\n __int16 v8; // si\n _BYTE *v9; // rdx\n signed __int64 v10; // rax\n void *v11; // rsp\n unsigned __int64 v12; // r14\n _BYTE *v13; // rdx\n int i; // r9d\n _DWORD *v15; // rax\n _BYTE *v16; // r15\n int v17; // r10d\n __int64 v18; // r12\n int v19; // r8d\n __int64 v20; // rsi\n _DWORD *v21; // rcx\n int v22; // r9d\n int v23; // edi\n _BYTE v26[8]; // [rsp+8h] [rbp-60h] BYREF\n int v27; // [rsp+10h] [rbp-58h]\n int v28; // [rsp+14h] [rbp-54h]\n unsigned __int64 v29; // [rsp+18h] [rbp-50h]\n _BYTE *v30; // [rsp+20h] [rbp-48h]\n unsigned __int64 v31; // [rsp+30h] [rbp-38h]\n\n v4 = a2;\n v31 = __readfsqword(0x28u);\n v6 = a2 + 1;\n v7 = 4 * v6;\n v8 = (4 * (a2 + 1) * (a3 + 1) + 15) & 0xFFF0;\n v9 = &v26[-((4 * v6 * (a3 + 1) + 15) & 0xFFFFFFFFFFFFF000LL)];\n while ( v26 != v9 )\n ;\n v10 = v8 & 0xFFF;\n v11 = alloca(v10);\n if ( (v8 & 0xFFF) != 0 )\n *(_QWORD *)&v26[v10 - 8] = *(_QWORD *)&v26[v10 - 8];\n if ( a3 >= 0 )\n {\n v12 = v7 >> 2;\n v13 = &v26[4 * v4 + 4];\n for ( i = 0; ; ++i )\n {\n v15 = &v13[4 * ~(unsigned __int64)(unsigned int)v4];\n if ( v4 >= 0 )\n {\n do\n *v15++ = 0;\n while ( v15 != (_DWORD *)v13 );\n }\n v13 += v7;\n if ( i + 1 == a3 + 1 )\n break;\n }\n if ( a3 > 0 )\n {\n v16 = &v26[v7 + 4];\n v17 = 1;\n v18 = (unsigned int)v4;\n v29 = v7;\n v28 = i;\n v19 = v4;\n v27 = a3;\n while ( 1 )\n {\n v21 = v16;\n v20 = 0LL;\n if ( v19 > 0 )\n {\n v30 = v16;\n do\n {\n v22 = *(v21 - 1);\n *v21 = v22;\n v23 = *(_DWORD *)(a1 + 4 * v20);\n if ( v23 > 0 && v23 <= v17 )\n *v21 = v22 + *(_DWORD *)&v26[4 * v12 * (v17 / v23) + 4 * (int)v20] + 1;\n ++v20;\n ++v21;\n }\n while ( v20 != v18 );\n v16 = v30;\n }\n v16 += v29;\n if ( v28 == v17 )\n break;\n ++v17;\n }\n v4 = v19;\n v7 = v29;\n a3 = v27;\n }\n }\n return *(unsigned int *)&v26[4 * (v7 >> 2) * a3 + 4 * v4];\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 38h\nmov rbx, rdi\nmov edi, esi\nmov ecx, edx\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nlea edx, [rsi+1]\nmovsxd rdx, edx\nlea r8, ds:0[rdx*4]\nlea eax, [rcx+1]\ncdqe\nimul rax, rdx\nlea rax, ds:0Fh[rax*4]\nmov rsi, rax\nand rsi, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11C6:\ncmp rsp, rdx\njz short loc_11DD\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\njmp short loc_11C6\nloc_11DD:\nmov rax, rsi\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11F3\nor [rsp+rax+60h+var_68], 0\nloc_11F3:\nmov r13, rsp\ntest ecx, ecx\njs loc_12E2\nmov r14, r8\nshr r14, 2\nmov esi, edi\nlea rdx, [r13+rsi*4+4]\nlea r10d, [rcx+1]\nmov r9d, 0\nnot rsi\nshl rsi, 2\njmp short loc_123D\nloc_121F:\nmov dword ptr [rax], 0\nadd rax, 4\ncmp rax, rdx\njnz short loc_121F\nloc_122E:\nlea eax, [r9+1]\nadd rdx, r8\ncmp eax, r10d\njz short loc_1247\nmov r9d, eax\nloc_123D:\nlea rax, [rsi+rdx]\ntest edi, edi\njns short loc_121F\njmp short loc_122E\nloc_1247:\ntest ecx, ecx\njle loc_12E2\nlea r15, [r13+r8+4]\nmov r10d, 1\nmov r12d, edi\nmov [rbp+var_50], r8\nmov [rbp+var_54], r9d\nmov r8d, edi\nmov [rbp+var_58], ecx\njmp short loc_12C5\nloc_126D:\nadd rsi, 1\nadd rcx, 4\ncmp rsi, r12\njz short loc_12AD\nloc_127A:\nmov r9d, [rcx-4]\nmov [rcx], r9d\nmov edi, [rbx+rsi*4]\ntest edi, edi\njle short loc_126D\ncmp edi, r10d\njg short loc_126D\nmovsxd r11, esi\nmov eax, r10d\ncdq\nidiv edi\ncdqe\nimul rax, r14\nadd r11, rax\nmov eax, [r13+r11*4+0]\nlea eax, [r9+rax+1]\nmov [rcx], eax\njmp short loc_126D\nloc_12AD:\nmov r15, [rbp+var_48]\nloc_12B1:\nlea eax, [r10+1]\nmov rdx, [rbp+var_50]\nadd r15, rdx\ncmp [rbp+var_54], r10d\njz short loc_12D8\nmov r10d, eax\nloc_12C5:\nmov rcx, r15\nmov esi, 0\ntest r8d, r8d\njle short loc_12B1\nmov [rbp+var_48], r15\njmp short loc_127A\nloc_12D8:\nmov edi, r8d\nmov r8, [rbp+var_50]\nmov ecx, [rbp+var_58]\nloc_12E2:\nmovsxd rax, edi\nmovsxd rcx, ecx\nshr r8, 2\nimul rcx, r8\nadd rax, rcx\nmov eax, [r13+rax*4+0]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_1316\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1316:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n int v4; // edi\n __int64 v6; // rdx\n unsigned __int64 v7; // r8\n __int16 v8; // si\n _BYTE *v9; // rdx\n signed __int64 v10; // rax\n void *v11; // rsp\n unsigned __int64 v12; // r14\n _BYTE *v13; // rdx\n int i; // r9d\n _DWORD *v15; // rax\n _BYTE *v16; // r15\n int v17; // r10d\n __int64 v18; // r12\n int v19; // r8d\n __int64 v20; // rsi\n _DWORD *v21; // rcx\n int v22; // r9d\n int v23; // edi\n _BYTE v26[8]; // [rsp+8h] [rbp-60h] BYREF\n int v27; // [rsp+10h] [rbp-58h]\n int v28; // [rsp+14h] [rbp-54h]\n unsigned __int64 v29; // [rsp+18h] [rbp-50h]\n _BYTE *v30; // [rsp+20h] [rbp-48h]\n unsigned __int64 v31; // [rsp+30h] [rbp-38h]\n\n v4 = a2;\n v31 = __readfsqword(0x28u);\n v6 = a2 + 1;\n v7 = 4 * v6;\n v8 = (4 * (a2 + 1) * (a3 + 1) + 15) & 0xFFF0;\n v9 = &v26[-((4 * v6 * (a3 + 1) + 15) & 0xFFFFFFFFFFFFF000LL)];\n while ( v26 != v9 )\n ;\n v10 = v8 & 0xFFF;\n v11 = alloca(v10);\n if ( (v8 & 0xFFF) != 0 )\n *(_QWORD *)&v26[v10 - 8] = *(_QWORD *)&v26[v10 - 8];\n if ( a3 >= 0 )\n {\n v12 = v7 >> 2;\n v13 = &v26[4 * v4 + 4];\n for ( i = 0; ; ++i )\n {\n v15 = &v13[4 * ~(unsigned __int64)(unsigned int)v4];\n if ( v4 >= 0 )\n {\n do\n *v15++ = 0;\n while ( v15 != (_DWORD *)v13 );\n }\n v13 += v7;\n if ( i + 1 == a3 + 1 )\n break;\n }\n if ( a3 > 0 )\n {\n v16 = &v26[v7 + 4];\n v17 = 1;\n v18 = (unsigned int)v4;\n v29 = v7;\n v28 = i;\n v19 = v4;\n v27 = a3;\n while ( 1 )\n {\n v21 = v16;\n v20 = 0LL;\n if ( v19 > 0 )\n {\n v30 = v16;\n do\n {\n v22 = *(v21 - 1);\n *v21 = v22;\n v23 = *(_DWORD *)(a1 + 4 * v20);\n if ( v23 > 0 && v23 <= v17 )\n *v21 = v22 + *(_DWORD *)&v26[4 * v12 * (v17 / v23) + 4 * (int)v20] + 1;\n ++v20;\n ++v21;\n }\n while ( v20 != v18 );\n v16 = v30;\n }\n v16 += v29;\n if ( v28 == v17 )\n break;\n ++v17;\n }\n v4 = v19;\n v7 = v29;\n a3 = v27;\n }\n }\n return *(unsigned int *)&v26[4 * (v7 >> 2) * a3 + 4 * v4];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n int v4;\n long long v6;\n unsigned long long v7;\n short v8;\n uint8_t *v9;\n signed long long v10;\n void *v11;\n unsigned long long v12;\n uint8_t *v13;\n int i;\n uint32_t *v15;\n uint8_t *v16;\n int v17;\n long long v18;\n int v19;\n long long v20;\n uint32_t *v21;\n int v22;\n int v23;\n uint8_t v26[8];\n int v27;\n int v28;\n unsigned long long v29;\n uint8_t *v30;\n unsigned long long v31;\n v4 = a2;\n v31 = __readfsqword(40u);\n v6 = a2 + 1;\n v7 = 4 * v6;\n v8 = (4 * (a2 + 1) * (a3 + 1) + 15) & 65520;\n v9 = &v26[-((4 * v6 * (a3 + 1) + 15) & 18446744073709547520LL)];\n while (v26 != v9)\n ;\n v10 = v8 & 4095;\n v11 = alloca(v10);\n if ((v8 & 4095) != 0) *(uint64_t *)&v26[v10 - 8] = *(uint64_t *)&v26[v10 - 8];\n if (a3 >= 0) {\n v12 = v7 >> 2;\n v13 = &v26[4 * v4 + 4];\n for (i = 0;; ++i) {\n v15 = &v13[4 * ~(unsigned long long)(unsigned int)v4];\n if (v4 >= 0) {\n do\n *v15++ = 0;\n while (v15 != (uint32_t *)v13);\n }\n v13 += v7;\n if (i + 1 == a3 + 1) break;\n }\n if (a3 > 0) {\n v16 = &v26[v7 + 4];\n v17 = 1;\n v18 = (unsigned int)v4;\n v29 = v7;\n v28 = i;\n v19 = v4;\n v27 = a3;\n while (1) {\n v21 = v16;\n v20 = 0LL;\n if (v19 > 0) {\n v30 = v16;\n do {\n v22 = *(v21 - 1);\n *v21 = v22;\n v23 = *(uint32_t *)(a1 + 4 * v20);\n if (v23 > 0 && v23 <= v17)\n *v21 = v22 +\n *(uint32_t *)&v26[4 * v12 * (v17 / v23) + 4 * (int)v20] +\n 1;\n ++v20;\n ++v21;\n } while (v20 != v18);\n v16 = v30;\n }\n v16 += v29;\n if (v28 == v17) break;\n ++v17;\n }\n v4 = v19;\n v7 = v29;\n a3 = v27;\n }\n }\n return *(unsigned int *)&v26[4 * (v7 >> 2) * a3 + 4 * v4];\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n int v4;\n long long v6;\n unsigned long long v7;\n short v8;\n uint8_t *v9;\n signed long long v10;\n void *v11;\n unsigned long long v12;\n uint8_t *v13;\n int i;\n uint32_t *v15;\n uint8_t *v16;\n int v17;\n long long v18;\n int v19;\n long long v20;\n uint32_t *v21;\n int v22;\n int v23;\n uint8_t v26[8];\n int v27;\n int v28;\n unsigned long long v29;\n uint8_t *v30;\n unsigned long long v31;\n v4 = a2;\n v31 = __readfsqword(40u);\n v6 = a2 + 1;\n v7 = 4 * v6;\n v8 = (4 * (a2 + 1) * (a3 + 1) + 15) & 65520;\n v9 = &v26[-((4 * v6 * (a3 + 1) + 15) & 18446744073709547520LL)];\n while (v26 != v9)\n ;\n v10 = v8 & 4095;\n v11 = alloca(v10);\n if ((v8 & 4095) != 0) *(uint64_t *)&v26[v10 - 8] = *(uint64_t *)&v26[v10 - 8];\n if (a3 >= 0) {\n v12 = v7 >> 2;\n v13 = &v26[4 * v4 + 4];\n for (i = 0;; ++i) {\n v15 = &v13[4 * ~(unsigned long long)(unsigned int)v4];\n if (v4 >= 0) {\n do\n *v15++ = 0;\n while (v15 != (uint32_t *)v13);\n }\n v13 += v7;\n if (i + 1 == a3 + 1) break;\n }\n if (a3 > 0) {\n v16 = &v26[v7 + 4];\n v17 = 1;\n v18 = (unsigned int)v4;\n v29 = v7;\n v28 = i;\n v19 = v4;\n v27 = a3;\n while (1) {\n v21 = v16;\n v20 = 0LL;\n if (v19 > 0) {\n v30 = v16;\n do {\n v22 = *(v21 - 1);\n *v21 = v22;\n v23 = *(uint32_t *)(a1 + 4 * v20);\n if (v23 > 0 && v23 <= v17)\n *v21 = v22 +\n *(uint32_t *)&v26[4 * v12 * (v17 / v23) + 4 * (int)v20] +\n 1;\n ++v20;\n ++v21;\n } while (v20 != v18);\n v16 = v30;\n }\n v16 += v29;\n if (v28 == v17) break;\n ++v17;\n }\n v4 = v19;\n v7 = v29;\n a3 = v27;\n }\n }\n return *(unsigned int *)&v26[4 * (v7 >> 2) * a3 + 4 * v4];\n}" + }, + { + "index": 510, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n, int k) {\n int dp[k + 1][n + 1];\n for (int i = 0; i <= k; i++) {\n for (int j = 0; j <= n; j++) {\n dp[i][j] = 0;\n }\n }\n for (int i = 1; i <= k; i++) {\n for (int j = 1; j <= n; j++) {\n dp[i][j] = dp[i][j - 1];\n if (arr[j - 1] <= i && arr[j - 1] > 0) {\n dp[i][j] += dp[i / arr[j - 1]][j - 1] + 1;\n }\n }\n }\n return dp[k][n];\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4};\n\n int arr2[] = {4, 8, 7, 2};\n\n int arr3[] = {5, 6, 7, 8};\n\n\n\n assert(func0(arr1, 4, 10) == 11);\n\n assert(func0(arr2, 4, 50) == 9);\n\n assert(func0(arr3, 4, 15) == 4);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\npush %r12\nmov %esi,%r12d\npush %rbx\nsub $0x28,%rsp\nmov %edx,-0x50(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nlea 0x1(%rsi),%eax\ncltq\nlea 0x0(,%rax,4),%rbx\nmov %rbx,-0x48(%rbp)\nlea 0x1(%rdx),%ebx\nmovslq %ebx,%rdx\nmov %ebx,-0x4c(%rbp)\nmov %rsp,%rbx\nimul %rdx,%rax\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rbx\nand $0xfffffffffffffff0,%rdx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 1330 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 131b \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 1450 \nmov -0x48(%rbp),%r8\nmov -0x50(%rbp),%edx\nmov %rsp,%r14\nmov %r8,%r15\nshr $0x2,%r15\ntest %edx,%edx\njs 141f \nmov %r12d,%esi\nmov -0x4c(%rbp),%r9d\nxor %ecx,%ecx\nadd $0x1,%rsi\nlea (%r14,%rsi,4),%rdx\nneg %rsi\nshl $0x2,%rsi\nnopl 0x0(%rax,%rax,1)\nlea (%rsi,%rdx,1),%rax\ntest %r12d,%r12d\njs 1397 \nnopl 0x0(%rax)\nmovl $0x0,(%rax)\nadd $0x4,%rax\ncmp %rdx,%rax\njne 1388 \nadd $0x1,%ecx\nadd %r8,%rdx\ncmp %r9d,%ecx\njne 1378 \nmov -0x50(%rbp),%eax\ntest %eax,%eax\njle 141f \nmov -0x48(%rbp),%rax\nmov $0x1,%esi\nlea -0x1(%r12),%ebx\nlea 0x4(%r14,%rax,1),%r13\nnopl 0x0(%rax)\nmov %r13,%r8\nxor %ecx,%ecx\ntest %r12d,%r12d\njg 13d3 \njmp 1413 \nnopl 0x0(%rax)\nmov %rax,%rcx\nmov -0x4(%r8),%r11d\nmov (%rdi,%rcx,4),%r9d\nmovslq %ecx,%r10\nmov %r11d,(%r8)\ncmp %esi,%r9d\njg 1406 \ntest %r9d,%r9d\njle 1406 \nmov %esi,%eax\ncltd\nidiv %r9d\ncltq\nimul %r15,%rax\nadd %r10,%rax\nmov (%r14,%rax,4),%eax\nlea 0x1(%r11,%rax,1),%eax\nmov %eax,(%r8)\nlea 0x1(%rcx),%rax\nadd $0x4,%r8\ncmp %rcx,%rbx\njne 13d0 \nadd $0x1,%esi\nadd -0x48(%rbp),%r13\ncmp %esi,-0x4c(%rbp)\njne 13c0 \nmovslq -0x50(%rbp),%rax\nmovslq %r12d,%r12\nimul %rax,%r15\nmov -0x38(%rbp),%rdi\nxor %fs:0x28,%rdi\nlea (%r12,%r15,1),%rax\nmov (%r14,%rax,4),%eax\njne 145b \nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 1342 \ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\nmovsxd r13, edx\nlea edx, [rsi+1]\npush r12\nmovsxd rdx, edx\npush rbx\nmov rbx, rdi\nsub rsp, 38h\nmov [rbp+var_50], esi\nmov rcx, rsp\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nlea rax, ds:0[rdx*4]\nmov [rbp+var_48], rax\nlea eax, [r13+1]\ncdqe\nimul rax, rdx\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_130E\nloc_12F9:\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\ncmp rsp, rcx\njnz short loc_12F9\nloc_130E:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_145F\nloc_1320:\nmov r15, [rbp+var_48]\nmov r14, rsp\nshr r15, 2\ntest r13d, r13d\njs loc_1400\nmov r12d, [rbp+var_50]\nmov rdi, r14; s\nxor ecx, ecx\nlea rax, ds:4[r12*4]\nmov [rbp+n], rax\nloc_1349:\nmov edx, [rbp+var_50]\ntest edx, edx\njs loc_1445\nnop dword ptr [rax+00h]\nloc_1358:\nmov rdx, [rbp+n]; n\nxor esi, esi; c\nmov [rbp+var_4C], ecx\ncall _memset\nmov ecx, [rbp+var_4C]\nmov rdx, [rbp+var_48]\nmov rdi, rax\nmov eax, ecx\nadd rdi, rdx\nadd ecx, 1\ncmp eax, r13d\njnz short loc_1358\nloc_137D:\ntest r13d, r13d\njz short loc_1400\nmov rax, [rbp+var_48]\nmov r10d, 1\nlea r11, [r14+rax+4]\nloc_1391:\nmov eax, [rbp+var_50]\ntest eax, eax\njle loc_142D\nnop dword ptr [rax+00h]\nloc_13A0:\nmov rsi, r11\nxor ecx, ecx\nnop dword ptr [rax]\nloc_13A8:\nmov r8d, [rsi-4]\nmov edi, [rbx+rcx*4]\nmov [rsi], r8d\ntest edi, edi\njle short loc_13D8\ncmp edi, r10d\njg short loc_13D8\nmov eax, r10d\nmovsxd r9, ecx\ncdq\nidiv edi\ncdqe\nimul rax, r15\nadd r9, rax\nmov eax, [r14+r9*4]\nlea eax, [r8+rax+1]\nmov [rsi], eax\nloc_13D8:\nadd rcx, 1\nadd rsi, 4\ncmp rcx, r12\njnz short loc_13A8\nmov rdx, [rbp+var_48]\nlea eax, [r10+1]\nadd r11, rdx\ncmp r13d, r10d\njz short loc_1400\nmov r10d, eax\njmp short loc_13A0\nloc_1400:\nimul r13, r15\nmovsxd rax, [rbp+var_50]\nadd rax, r13\nmov eax, [r14+rax*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_146A\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_142D:\nmov rdx, [rbp+var_48]\nlea eax, [r10+1]\nadd r11, rdx\ncmp r13d, r10d\njz short loc_1400\nmov r10d, eax\njmp loc_1391\nloc_1445:\nmov rdx, [rbp+var_48]\nlea eax, [rcx+1]\nadd rdi, rdx\ncmp r13d, ecx\njz loc_137D\nmov ecx, eax\njmp loc_1349\nloc_145F:\nor [rsp+rdx+1060h+var_1068], 0\njmp loc_1320\nloc_146A:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n __int64 v3; // r13\n __int64 v4; // rdx\n __int64 v6; // rdx\n __int64 *v7; // rcx\n __int16 v8; // dx\n signed __int64 v9; // rdx\n void *v10; // rsp\n unsigned __int64 v11; // r15\n __int64 v12; // r12\n char *v13; // rdi\n int v14; // ecx\n char *v15; // rax\n int v16; // r10d\n _BYTE *v17; // r11\n _DWORD *v18; // rsi\n __int64 v19; // rcx\n int v20; // r8d\n int v21; // edi\n _BYTE v24[4088]; // [rsp+8h] [rbp-1060h] BYREF\n __int64 v25; // [rsp+1008h] [rbp-60h] BYREF\n size_t n; // [rsp+1010h] [rbp-58h]\n int v27; // [rsp+1018h] [rbp-50h]\n int v28; // [rsp+101Ch] [rbp-4Ch]\n unsigned __int64 v29; // [rsp+1020h] [rbp-48h]\n unsigned __int64 v30; // [rsp+1030h] [rbp-38h]\n\n v3 = a3;\n v4 = a2 + 1;\n v27 = a2;\n v30 = __readfsqword(0x28u);\n v29 = 4 * v4;\n v6 = 4 * v4 * ((int)v3 + 1) + 15;\n v7 = (__int64 *)((char *)&v25 - (v6 & 0xFFFFFFFFFFFFF000LL));\n v8 = v6 & 0xFFF0;\n if ( &v25 != v7 )\n {\n while ( v24 != (_BYTE *)v7 )\n ;\n }\n v9 = v8 & 0xFFF;\n v10 = alloca(v9);\n if ( v9 )\n *(_QWORD *)&v24[v9 - 8] = *(_QWORD *)&v24[v9 - 8];\n v11 = v29 >> 2;\n if ( (int)v3 >= 0 )\n {\n v12 = (unsigned int)v27;\n v13 = v24;\n v14 = 0;\n n = 4LL * (unsigned int)v27 + 4;\n while ( v27 < 0 )\n {\n v13 += v29;\n if ( (_DWORD)v3 == v14 )\n goto LABEL_9;\n ++v14;\n }\n do\n {\n v28 = v14;\n v15 = (char *)memset(v13, 0, n);\n v13 = &v15[v29];\n v14 = v28 + 1;\n }\n while ( v28 != (_DWORD)v3 );\nLABEL_9:\n if ( (_DWORD)v3 )\n {\n v16 = 1;\n v17 = &v24[v29 + 4];\n while ( v27 <= 0 )\n {\n v17 += v29;\n if ( (_DWORD)v3 == v16 )\n return *(unsigned int *)&v24[4 * v11 * v3 + 4 * v27];\n ++v16;\n }\n while ( 1 )\n {\n v18 = v17;\n v19 = 0LL;\n do\n {\n v20 = *(v18 - 1);\n v21 = *(_DWORD *)(a1 + 4 * v19);\n *v18 = v20;\n if ( v21 > 0 && v21 <= v16 )\n *v18 = v20 + *(_DWORD *)&v24[4 * v11 * (v16 / v21) + 4 * (int)v19] + 1;\n ++v19;\n ++v18;\n }\n while ( v19 != v12 );\n v17 += v29;\n if ( (_DWORD)v3 == v16 )\n break;\n ++v16;\n }\n }\n }\n return *(unsigned int *)&v24[4 * v11 * v3 + 4 * v27];\n}", + "ida_strip_asm": "sub_1290:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\nmovsxd r13, edx\nlea edx, [rsi+1]\npush r12\nmovsxd rdx, edx\npush rbx\nmov rbx, rdi\nsub rsp, 38h\nmov [rbp+var_50], esi\nmov rcx, rsp\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nlea rax, ds:0[rdx*4]\nmov [rbp+var_48], rax\nlea eax, [r13+1]\ncdqe\nimul rax, rdx\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_130E\nloc_12F9:\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\ncmp rsp, rcx\njnz short loc_12F9\nloc_130E:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_145F\nloc_1320:\nmov r15, [rbp+var_48]\nmov r14, rsp\nshr r15, 2\ntest r13d, r13d\njs loc_1400\nmov r12d, [rbp+var_50]\nmov rdi, r14; s\nxor ecx, ecx\nlea rax, ds:4[r12*4]\nmov [rbp+n], rax\nloc_1349:\nmov edx, [rbp+var_50]\ntest edx, edx\njs loc_1445\nnop dword ptr [rax+00h]\nloc_1358:\nmov rdx, [rbp+n]; n\nxor esi, esi; c\nmov [rbp+var_4C], ecx\ncall _memset\nmov ecx, [rbp+var_4C]\nmov rdx, [rbp+var_48]\nmov rdi, rax\nmov eax, ecx\nadd rdi, rdx\nadd ecx, 1\ncmp eax, r13d\njnz short loc_1358\nloc_137D:\ntest r13d, r13d\njz short loc_1400\nmov rax, [rbp+var_48]\nmov r10d, 1\nlea r11, [r14+rax+4]\nloc_1391:\nmov eax, [rbp+var_50]\ntest eax, eax\njle loc_142D\nnop dword ptr [rax+00h]\nloc_13A0:\nmov rsi, r11\nxor ecx, ecx\nnop dword ptr [rax]\nloc_13A8:\nmov r8d, [rsi-4]\nmov edi, [rbx+rcx*4]\nmov [rsi], r8d\ntest edi, edi\njle short loc_13D8\ncmp edi, r10d\njg short loc_13D8\nmov eax, r10d\nmovsxd r9, ecx\ncdq\nidiv edi\ncdqe\nimul rax, r15\nadd r9, rax\nmov eax, [r14+r9*4]\nlea eax, [r8+rax+1]\nmov [rsi], eax\nloc_13D8:\nadd rcx, 1\nadd rsi, 4\ncmp rcx, r12\njnz short loc_13A8\nmov rdx, [rbp+var_48]\nlea eax, [r10+1]\nadd r11, rdx\ncmp r13d, r10d\njz short loc_1400\nmov r10d, eax\njmp short loc_13A0\nloc_1400:\nimul r13, r15\nmovsxd rax, [rbp+var_50]\nadd rax, r13\nmov eax, [r14+rax*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_146A\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_142D:\nmov rdx, [rbp+var_48]\nlea eax, [r10+1]\nadd r11, rdx\ncmp r13d, r10d\njz short loc_1400\nmov r10d, eax\njmp loc_1391\nloc_1445:\nmov rdx, [rbp+var_48]\nlea eax, [rcx+1]\nadd rdi, rdx\ncmp r13d, ecx\njz loc_137D\nmov ecx, eax\njmp loc_1349\nloc_145F:\nor [rsp+rdx+1060h+var_1068], 0\njmp loc_1320\nloc_146A:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1290(__int64 a1, int a2, int a3)\n{\n __int64 v3; // r13\n __int64 v4; // rdx\n __int64 v6; // rdx\n __int64 *v7; // rcx\n __int16 v8; // dx\n signed __int64 v9; // rdx\n void *v10; // rsp\n unsigned __int64 v11; // r15\n __int64 v12; // r12\n char *v13; // rdi\n int v14; // ecx\n char *v15; // rax\n int v16; // r10d\n _BYTE *v17; // r11\n _DWORD *v18; // rsi\n __int64 v19; // rcx\n int v20; // r8d\n int v21; // edi\n _BYTE v24[4088]; // [rsp+8h] [rbp-1060h] BYREF\n __int64 v25; // [rsp+1008h] [rbp-60h] BYREF\n size_t n; // [rsp+1010h] [rbp-58h]\n int v27; // [rsp+1018h] [rbp-50h]\n int v28; // [rsp+101Ch] [rbp-4Ch]\n unsigned __int64 v29; // [rsp+1020h] [rbp-48h]\n unsigned __int64 v30; // [rsp+1030h] [rbp-38h]\n\n v3 = a3;\n v4 = a2 + 1;\n v27 = a2;\n v30 = __readfsqword(0x28u);\n v29 = 4 * v4;\n v6 = 4 * v4 * ((int)v3 + 1) + 15;\n v7 = (__int64 *)((char *)&v25 - (v6 & 0xFFFFFFFFFFFFF000LL));\n v8 = v6 & 0xFFF0;\n if ( &v25 != v7 )\n {\n while ( v24 != (_BYTE *)v7 )\n ;\n }\n v9 = v8 & 0xFFF;\n v10 = alloca(v9);\n if ( v9 )\n *(_QWORD *)&v24[v9 - 8] = *(_QWORD *)&v24[v9 - 8];\n v11 = v29 >> 2;\n if ( (int)v3 >= 0 )\n {\n v12 = (unsigned int)v27;\n v13 = v24;\n v14 = 0;\n n = 4LL * (unsigned int)v27 + 4;\n while ( v27 < 0 )\n {\n v13 += v29;\n if ( (_DWORD)v3 == v14 )\n goto LABEL_9;\n ++v14;\n }\n do\n {\n v28 = v14;\n v15 = (char *)memset(v13, 0, n);\n v13 = &v15[v29];\n v14 = v28 + 1;\n }\n while ( v28 != (_DWORD)v3 );\nLABEL_9:\n if ( (_DWORD)v3 )\n {\n v16 = 1;\n v17 = &v24[v29 + 4];\n while ( v27 <= 0 )\n {\n v17 += v29;\n if ( (_DWORD)v3 == v16 )\n return *(unsigned int *)&v24[4 * v11 * v3 + 4 * v27];\n ++v16;\n }\n while ( 1 )\n {\n v18 = v17;\n v19 = 0LL;\n do\n {\n v20 = *(v18 - 1);\n v21 = *(_DWORD *)(a1 + 4 * v19);\n *v18 = v20;\n if ( v21 > 0 && v21 <= v16 )\n *v18 = v20 + *(_DWORD *)&v24[4 * v11 * (v16 / v21) + 4 * (int)v19] + 1;\n ++v19;\n ++v18;\n }\n while ( v19 != v12 );\n v17 += v29;\n if ( (_DWORD)v3 == v16 )\n break;\n ++v16;\n }\n }\n }\n return *(unsigned int *)&v24[4 * v11 * v3 + 4 * v27];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1290(long long a1, int a2, int a3) {\n long long v3;\n long long v4;\n long long v6;\n long long *v7;\n short v8;\n signed long long v9;\n void *v10;\n unsigned long long v11;\n long long v12;\n char *v13;\n int v14;\n char *v15;\n int v16;\n uint8_t *v17;\n uint32_t *v18;\n long long v19;\n int v20;\n int v21;\n uint8_t v24[4088];\n long long v25;\n unsigned int n;\n int v27;\n int v28;\n unsigned long long v29;\n unsigned long long v30;\n v3 = a3;\n v4 = a2 + 1;\n v27 = a2;\n v30 = __readfsqword(40u);\n v29 = 4 * v4;\n v6 = 4 * v4 * ((int)v3 + 1) + 15;\n v7 = (long long *)((char *)&v25 - (v6 & 18446744073709547520LL));\n v8 = v6 & 65520;\n if (&v25 != v7) {\n while (v24 != (uint8_t *)v7)\n ;\n }\n v9 = v8 & 4095;\n v10 = alloca(v9);\n if (v9) *(uint64_t *)&v24[v9 - 8] = *(uint64_t *)&v24[v9 - 8];\n v11 = v29 >> 2;\n if ((int)v3 >= 0) {\n v12 = (unsigned int)v27;\n v13 = v24;\n v14 = 0;\n n = 4LL * (unsigned int)v27 + 4;\n while (v27 < 0) {\n v13 += v29;\n if ((uint32_t)v3 == v14) goto LABEL_9;\n ++v14;\n }\n do {\n v28 = v14;\n v15 = (char *)memset(v13, 0, n);\n v13 = &v15[v29];\n v14 = v28 + 1;\n } while (v28 != (uint32_t)v3);\n LABEL_9:\n if ((uint32_t)v3) {\n v16 = 1;\n v17 = &v24[v29 + 4];\n while (v27 <= 0) {\n v17 += v29;\n if ((uint32_t)v3 == v16)\n return *(unsigned int *)&v24[4 * v11 * v3 + 4 * v27];\n ++v16;\n }\n while (1) {\n v18 = v17;\n v19 = 0LL;\n do {\n v20 = *(v18 - 1);\n v21 = *(uint32_t *)(a1 + 4 * v19);\n *v18 = v20;\n if (v21 > 0 && v21 <= v16)\n *v18 = v20 +\n *(uint32_t *)&v24[4 * v11 * (v16 / v21) + 4 * (int)v19] + 1;\n ++v19;\n ++v18;\n } while (v19 != v12);\n v17 += v29;\n if ((uint32_t)v3 == v16) break;\n ++v16;\n }\n }\n }\n return *(unsigned int *)&v24[4 * v11 * v3 + 4 * v27];\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n long long v3;\n long long v4;\n long long v6;\n long long *v7;\n short v8;\n signed long long v9;\n void *v10;\n unsigned long long v11;\n long long v12;\n char *v13;\n int v14;\n char *v15;\n int v16;\n uint8_t *v17;\n uint32_t *v18;\n long long v19;\n int v20;\n int v21;\n uint8_t v24[4088];\n long long v25;\n unsigned int n;\n int v27;\n int v28;\n unsigned long long v29;\n unsigned long long v30;\n v3 = a3;\n v4 = a2 + 1;\n v27 = a2;\n v30 = __readfsqword(40u);\n v29 = 4 * v4;\n v6 = 4 * v4 * ((int)v3 + 1) + 15;\n v7 = (long long *)((char *)&v25 - (v6 & 18446744073709547520LL));\n v8 = v6 & 65520;\n if (&v25 != v7) {\n while (v24 != (uint8_t *)v7)\n ;\n }\n v9 = v8 & 4095;\n v10 = alloca(v9);\n if (v9) *(uint64_t *)&v24[v9 - 8] = *(uint64_t *)&v24[v9 - 8];\n v11 = v29 >> 2;\n if ((int)v3 >= 0) {\n v12 = (unsigned int)v27;\n v13 = v24;\n v14 = 0;\n n = 4LL * (unsigned int)v27 + 4;\n while (v27 < 0) {\n v13 += v29;\n if ((uint32_t)v3 == v14) goto LABEL_9;\n ++v14;\n }\n do {\n v28 = v14;\n v15 = (char *)memset(v13, 0, n);\n v13 = &v15[v29];\n v14 = v28 + 1;\n } while (v28 != (uint32_t)v3);\n LABEL_9:\n if ((uint32_t)v3) {\n v16 = 1;\n v17 = &v24[v29 + 4];\n while (v27 <= 0) {\n v17 += v29;\n if ((uint32_t)v3 == v16)\n return *(unsigned int *)&v24[4 * v11 * v3 + 4 * v27];\n ++v16;\n }\n while (1) {\n v18 = v17;\n v19 = 0LL;\n do {\n v20 = *(v18 - 1);\n v21 = *(uint32_t *)(a1 + 4 * v19);\n *v18 = v20;\n if (v21 > 0 && v21 <= v16)\n *v18 = v20 +\n *(uint32_t *)&v24[4 * v11 * (v16 / v21) + 4 * (int)v19] + 1;\n ++v19;\n ++v18;\n } while (v19 != v12);\n v17 += v29;\n if ((uint32_t)v3 == v16) break;\n ++v16;\n }\n }\n }\n return *(unsigned int *)&v24[4 * v11 * v3 + 4 * v27];\n}" + }, + { + "index": 510, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n, int k) {\n int dp[k + 1][n + 1];\n for (int i = 0; i <= k; i++) {\n for (int j = 0; j <= n; j++) {\n dp[i][j] = 0;\n }\n }\n for (int i = 1; i <= k; i++) {\n for (int j = 1; j <= n; j++) {\n dp[i][j] = dp[i][j - 1];\n if (arr[j - 1] <= i && arr[j - 1] > 0) {\n dp[i][j] += dp[i / arr[j - 1]][j - 1] + 1;\n }\n }\n }\n return dp[k][n];\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4};\n\n int arr2[] = {4, 8, 7, 2};\n\n int arr3[] = {5, 6, 7, 8};\n\n\n\n assert(func0(arr1, 4, 10) == 11);\n\n assert(func0(arr2, 4, 50) == 9);\n\n assert(func0(arr3, 4, 15) == 4);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\npush %r12\nmov %rdi,%r12\npush %rbx\nsub $0x48,%rsp\nmov %edx,-0x50(%rbp)\nadd $0x1,%edx\nmov %esi,-0x4c(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nlea 0x1(%rsi),%eax\nmov %edx,-0x54(%rbp)\nmovslq %edx,%rdx\ncltq\nlea 0x0(,%rax,4),%rbx\nimul %rdx,%rax\nmov %rbx,-0x48(%rbp)\nmov %rsp,%rbx\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rbx\nand $0xfffffffffffffff0,%rdx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 1313 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 12fe \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 1451 \nmov -0x48(%rbp),%rbx\nmov -0x50(%rbp),%ecx\nmov %rsp,%r13\nshr $0x2,%rbx\ntest %ecx,%ecx\njs 1469 \nmov -0x4c(%rbp),%edx\ntest %edx,%edx\njs 145c \nmovslq -0x4c(%rbp),%rax\nxor %r15d,%r15d\nmov %rbx,-0x68(%rbp)\nmov %r13,%rdi\nmov %r12,-0x70(%rbp)\nmov -0x48(%rbp),%rbx\nmov %r15d,%r12d\nmov %rax,-0x60(%rbp)\nmov -0x54(%rbp),%r15d\nlea 0x4(,%rax,4),%r14\nmov %r14,%rdx\nxor %esi,%esi\nadd $0x1,%r12d\ncallq 1090 \nmov %rax,%rdi\nadd %rbx,%rdi\ncmp %r15d,%r12d\njne 1370 \nmov -0x68(%rbp),%rbx\nmov -0x70(%rbp),%r12\nmov -0x50(%rbp),%eax\ntest %eax,%eax\njle 141f \nmov -0x4c(%rbp),%eax\ntest %eax,%eax\njle 141f \nmov -0x48(%rbp),%rdx\nmov -0x54(%rbp),%r10d\nmov $0x1,%r11d\nlea -0x1(%rax),%r15d\nlea 0x4(%r13,%rdx,1),%r14\nnopw 0x0(%rax,%rax,1)\nmov %r14,%rsi\nxor %ecx,%ecx\njmp 13d3 \nnopw 0x0(%rax,%rax,1)\nmov %rax,%rcx\nmov -0x4(%rsi),%r9d\nmov (%r12,%rcx,4),%edi\nmovslq %ecx,%r8\nmov %r9d,(%rsi)\ncmp %r11d,%edi\njg 1405 \ntest %edi,%edi\njle 1405 \nmov %r11d,%eax\ncltd\nidiv %edi\ncltq\nimul %rbx,%rax\nadd %r8,%rax\nmov 0x0(%r13,%rax,4),%eax\nlea 0x1(%r9,%rax,1),%eax\nmov %eax,(%rsi)\nlea 0x1(%rcx),%rax\nadd $0x4,%rsi\ncmp %r15,%rcx\njne 13d0 \nadd $0x1,%r11d\nadd -0x48(%rbp),%r14\ncmp %r10d,%r11d\njne 13c0 \nmovslq -0x50(%rbp),%rax\nmov -0x60(%rbp),%r9\nimul %rbx,%rax\nadd %rax,%r9\nmov -0x38(%rbp),%rdx\nxor %fs:0x28,%rdx\nmov 0x0(%r13,%r9,4),%eax\njne 1473 \nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 1325 \nmovslq -0x4c(%rbp),%rax\nmov %rax,-0x60(%rbp)\njmpq 1391 \nmovslq -0x4c(%rbp),%rax\nmov %rax,-0x60(%rbp)\njmp 141f \ncallq 1070 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov ecx, edx\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nmov rbx, rdi\nsub rsp, 38h\nmov [rbp+var_44], edx\nlea edx, [rsi+1]\nmov [rbp+var_48], esi\nmovsxd rdx, edx\nlea r14, ds:0[rdx*4]\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nlea eax, [rcx+1]\nmov rcx, rsp\ncdqe\nimul rax, rdx\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_130B\nloc_12F6:\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\ncmp rsp, rcx\njnz short loc_12F6\nloc_130B:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1431\nloc_131D:\nmov ecx, [rbp+var_44]\nmov r13, r14\nmov r12, rsp\nshr r13, 2\ntest ecx, ecx\njs loc_13F7\nmov edx, [rbp+var_48]\ntest edx, edx\njs loc_13F7\nmovsxd rax, [rbp+var_48]\nmov rdi, r12; s\nxor r15d, r15d\nmov [rbp+var_58], rax\nlea rax, ds:4[rax*4]\nmov [rbp+n], rax\nnop word ptr [rax+rax+00000000h]\nloc_1360:\nmov rdx, [rbp+n]; n\nxor esi, esi; c\ncall _memset\nmov rdi, rax\nmov eax, r15d\nadd r15d, 1\nadd rdi, r14\ncmp [rbp+var_44], eax\njnz short loc_1360\nmov eax, [rbp+var_44]\ntest eax, eax\njz short loc_1400\nmov eax, [rbp+var_48]\ntest eax, eax\njz short loc_1400\nlea r15, [r12+r14+4]\nmov r10d, 1\nmov r11d, eax\nnop dword ptr [rax+00000000h]\nloc_13A0:\nmov rsi, r15\nxor ecx, ecx\nnop dword ptr [rax]\nloc_13A8:\nmov r8d, [rsi-4]\nmov edi, [rbx+rcx*4]\nmov [rsi], r8d\ntest edi, edi\njle short loc_13D8\ncmp edi, r10d\njg short loc_13D8\nmov eax, r10d\nmovsxd r9, ecx\ncdq\nidiv edi\ncdqe\nimul rax, r13\nadd r9, rax\nmov eax, [r12+r9*4]\nlea eax, [r8+rax+1]\nmov [rsi], eax\nloc_13D8:\nadd rcx, 1\nadd rsi, 4\ncmp r11, rcx\njnz short loc_13A8\nlea eax, [r10+1]\nadd r15, r14\ncmp [rbp+var_44], r10d\njz short loc_1400\nmov r10d, eax\njmp short loc_13A0\nloc_13F7:\nmovsxd rax, [rbp+var_48]\nmov [rbp+var_58], rax\nnop\nloc_1400:\nmovsxd rax, [rbp+var_44]\nmov rdx, [rbp+var_58]\nimul rax, r13\nadd rdx, rax\nmov eax, [r12+rdx*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_143C\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1431:\nor [rsp+rdx+1060h+var_1068], 0\njmp loc_131D\nloc_143C:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n __int64 v5; // rdx\n unsigned __int64 v6; // r14\n __int64 v7; // rdx\n __int64 *v8; // rcx\n __int16 v9; // dx\n signed __int64 v10; // rdx\n void *v11; // rsp\n unsigned __int64 v12; // r13\n char *v13; // rdi\n int v14; // r15d\n char *v15; // rdi\n int v16; // eax\n _BYTE *v17; // r15\n int v18; // r10d\n __int64 v19; // r11\n _DWORD *v20; // rsi\n __int64 i; // rcx\n int v22; // r8d\n int v23; // edi\n _BYTE v26[4088]; // [rsp+8h] [rbp-1060h] BYREF\n __int64 v27; // [rsp+1008h] [rbp-60h] BYREF\n __int64 v28; // [rsp+1010h] [rbp-58h]\n size_t n; // [rsp+1018h] [rbp-50h]\n int v30; // [rsp+1020h] [rbp-48h]\n int v31; // [rsp+1024h] [rbp-44h]\n unsigned __int64 v32; // [rsp+1030h] [rbp-38h]\n\n v31 = a3;\n v30 = a2;\n v5 = a2 + 1;\n v6 = 4 * v5;\n v32 = __readfsqword(0x28u);\n v7 = 4 * v5 * (a3 + 1) + 15;\n v8 = (__int64 *)((char *)&v27 - (v7 & 0xFFFFFFFFFFFFF000LL));\n v9 = v7 & 0xFFF0;\n if ( &v27 != v8 )\n {\n while ( v26 != (_BYTE *)v8 )\n ;\n }\n v10 = v9 & 0xFFF;\n v11 = alloca(v10);\n if ( v10 )\n *(_QWORD *)&v26[v10 - 8] = *(_QWORD *)&v26[v10 - 8];\n v12 = v6 >> 2;\n if ( v31 < 0 || v30 < 0 )\n {\n v28 = v30;\n }\n else\n {\n v13 = v26;\n v14 = 0;\n v28 = v30;\n n = 4LL * v30 + 4;\n do\n {\n v15 = (char *)memset(v13, 0, n);\n v16 = v14++;\n v13 = &v15[v6];\n }\n while ( v31 != v16 );\n if ( v31 && v30 )\n {\n v17 = &v26[v6 + 4];\n v18 = 1;\n v19 = (unsigned int)v30;\n while ( 1 )\n {\n v20 = v17;\n for ( i = 0LL; i != v19; ++i )\n {\n v22 = *(v20 - 1);\n v23 = *(_DWORD *)(a1 + 4 * i);\n *v20 = v22;\n if ( v23 > 0 && v23 <= v18 )\n *v20 = v22 + *(_DWORD *)&v26[4 * v12 * (v18 / v23) + 4 * (int)i] + 1;\n ++v20;\n }\n v17 += v6;\n if ( v31 == v18 )\n break;\n ++v18;\n }\n }\n }\n return *(unsigned int *)&v26[4 * v12 * v31 + 4 * v28];\n}", + "ida_strip_asm": "sub_1290:\nendbr64\npush rbp\nmov ecx, edx\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nmov rbx, rdi\nsub rsp, 38h\nmov [rbp+var_44], edx\nlea edx, [rsi+1]\nmov [rbp+var_48], esi\nmovsxd rdx, edx\nlea r14, ds:0[rdx*4]\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nlea eax, [rcx+1]\nmov rcx, rsp\ncdqe\nimul rax, rdx\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_130B\nloc_12F6:\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\ncmp rsp, rcx\njnz short loc_12F6\nloc_130B:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1431\nloc_131D:\nmov ecx, [rbp+var_44]\nmov r13, r14\nmov r12, rsp\nshr r13, 2\ntest ecx, ecx\njs loc_13F7\nmov edx, [rbp+var_48]\ntest edx, edx\njs loc_13F7\nmovsxd rax, [rbp+var_48]\nmov rdi, r12; s\nxor r15d, r15d\nmov [rbp+var_58], rax\nlea rax, ds:4[rax*4]\nmov [rbp+n], rax\nnop word ptr [rax+rax+00000000h]\nloc_1360:\nmov rdx, [rbp+n]; n\nxor esi, esi; c\ncall _memset\nmov rdi, rax\nmov eax, r15d\nadd r15d, 1\nadd rdi, r14\ncmp [rbp+var_44], eax\njnz short loc_1360\nmov eax, [rbp+var_44]\ntest eax, eax\njz short loc_1400\nmov eax, [rbp+var_48]\ntest eax, eax\njz short loc_1400\nlea r15, [r12+r14+4]\nmov r10d, 1\nmov r11d, eax\nnop dword ptr [rax+00000000h]\nloc_13A0:\nmov rsi, r15\nxor ecx, ecx\nnop dword ptr [rax]\nloc_13A8:\nmov r8d, [rsi-4]\nmov edi, [rbx+rcx*4]\nmov [rsi], r8d\ntest edi, edi\njle short loc_13D8\ncmp edi, r10d\njg short loc_13D8\nmov eax, r10d\nmovsxd r9, ecx\ncdq\nidiv edi\ncdqe\nimul rax, r13\nadd r9, rax\nmov eax, [r12+r9*4]\nlea eax, [r8+rax+1]\nmov [rsi], eax\nloc_13D8:\nadd rcx, 1\nadd rsi, 4\ncmp r11, rcx\njnz short loc_13A8\nlea eax, [r10+1]\nadd r15, r14\ncmp [rbp+var_44], r10d\njz short loc_1400\nmov r10d, eax\njmp short loc_13A0\nloc_13F7:\nmovsxd rax, [rbp+var_48]\nmov [rbp+var_58], rax\nnop\nloc_1400:\nmovsxd rax, [rbp+var_44]\nmov rdx, [rbp+var_58]\nimul rax, r13\nadd rdx, rax\nmov eax, [r12+rdx*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_143C\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1431:\nor [rsp+rdx+1060h+var_1068], 0\njmp loc_131D\nloc_143C:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1290(__int64 a1, int a2, int a3)\n{\n __int64 v5; // rdx\n unsigned __int64 v6; // r14\n __int64 v7; // rdx\n __int64 *v8; // rcx\n __int16 v9; // dx\n signed __int64 v10; // rdx\n void *v11; // rsp\n unsigned __int64 v12; // r13\n char *v13; // rdi\n int v14; // r15d\n char *v15; // rdi\n int v16; // eax\n _BYTE *v17; // r15\n int v18; // r10d\n __int64 v19; // r11\n _DWORD *v20; // rsi\n __int64 i; // rcx\n int v22; // r8d\n int v23; // edi\n _BYTE v26[4088]; // [rsp+8h] [rbp-1060h] BYREF\n __int64 v27; // [rsp+1008h] [rbp-60h] BYREF\n __int64 v28; // [rsp+1010h] [rbp-58h]\n size_t n; // [rsp+1018h] [rbp-50h]\n int v30; // [rsp+1020h] [rbp-48h]\n int v31; // [rsp+1024h] [rbp-44h]\n unsigned __int64 v32; // [rsp+1030h] [rbp-38h]\n\n v31 = a3;\n v30 = a2;\n v5 = a2 + 1;\n v6 = 4 * v5;\n v32 = __readfsqword(0x28u);\n v7 = 4 * v5 * (a3 + 1) + 15;\n v8 = (__int64 *)((char *)&v27 - (v7 & 0xFFFFFFFFFFFFF000LL));\n v9 = v7 & 0xFFF0;\n if ( &v27 != v8 )\n {\n while ( v26 != (_BYTE *)v8 )\n ;\n }\n v10 = v9 & 0xFFF;\n v11 = alloca(v10);\n if ( v10 )\n *(_QWORD *)&v26[v10 - 8] = *(_QWORD *)&v26[v10 - 8];\n v12 = v6 >> 2;\n if ( v31 < 0 || v30 < 0 )\n {\n v28 = v30;\n }\n else\n {\n v13 = v26;\n v14 = 0;\n v28 = v30;\n n = 4LL * v30 + 4;\n do\n {\n v15 = (char *)memset(v13, 0, n);\n v16 = v14++;\n v13 = &v15[v6];\n }\n while ( v31 != v16 );\n if ( v31 && v30 )\n {\n v17 = &v26[v6 + 4];\n v18 = 1;\n v19 = (unsigned int)v30;\n while ( 1 )\n {\n v20 = v17;\n for ( i = 0LL; i != v19; ++i )\n {\n v22 = *(v20 - 1);\n v23 = *(_DWORD *)(a1 + 4 * i);\n *v20 = v22;\n if ( v23 > 0 && v23 <= v18 )\n *v20 = v22 + *(_DWORD *)&v26[4 * v12 * (v18 / v23) + 4 * (int)i] + 1;\n ++v20;\n }\n v17 += v6;\n if ( v31 == v18 )\n break;\n ++v18;\n }\n }\n }\n return *(unsigned int *)&v26[4 * v12 * v31 + 4 * v28];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1290(long long a1, int a2, int a3) {\n long long v5;\n unsigned long long v6;\n long long v7;\n long long *v8;\n short v9;\n signed long long v10;\n void *v11;\n unsigned long long v12;\n char *v13;\n int v14;\n char *v15;\n int v16;\n uint8_t *v17;\n int v18;\n long long v19;\n uint32_t *v20;\n long long i;\n int v22;\n int v23;\n uint8_t v26[4088];\n long long v27;\n long long v28;\n unsigned int n;\n int v30;\n int v31;\n unsigned long long v32;\n v31 = a3;\n v30 = a2;\n v5 = a2 + 1;\n v6 = 4 * v5;\n v32 = __readfsqword(40u);\n v7 = 4 * v5 * (a3 + 1) + 15;\n v8 = (long long *)((char *)&v27 - (v7 & 18446744073709547520LL));\n v9 = v7 & 65520;\n if (&v27 != v8) {\n while (v26 != (uint8_t *)v8)\n ;\n }\n v10 = v9 & 4095;\n v11 = alloca(v10);\n if (v10) *(uint64_t *)&v26[v10 - 8] = *(uint64_t *)&v26[v10 - 8];\n v12 = v6 >> 2;\n if (v31 < 0 || v30 < 0) {\n v28 = v30;\n } else {\n v13 = v26;\n v14 = 0;\n v28 = v30;\n n = 4LL * v30 + 4;\n do {\n v15 = (char *)memset(v13, 0, n);\n v16 = v14++;\n v13 = &v15[v6];\n } while (v31 != v16);\n if (v31 && v30) {\n v17 = &v26[v6 + 4];\n v18 = 1;\n v19 = (unsigned int)v30;\n while (1) {\n v20 = v17;\n for (i = 0LL; i != v19; ++i) {\n v22 = *(v20 - 1);\n v23 = *(uint32_t *)(a1 + 4 * i);\n *v20 = v22;\n if (v23 > 0 && v23 <= v18)\n *v20 =\n v22 + *(uint32_t *)&v26[4 * v12 * (v18 / v23) + 4 * (int)i] + 1;\n ++v20;\n }\n v17 += v6;\n if (v31 == v18) break;\n ++v18;\n }\n }\n }\n return *(unsigned int *)&v26[4 * v12 * v31 + 4 * v28];\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n long long v5;\n unsigned long long v6;\n long long v7;\n long long *v8;\n short v9;\n signed long long v10;\n void *v11;\n unsigned long long v12;\n char *v13;\n int v14;\n char *v15;\n int v16;\n uint8_t *v17;\n int v18;\n long long v19;\n uint32_t *v20;\n long long i;\n int v22;\n int v23;\n uint8_t v26[4088];\n long long v27;\n long long v28;\n unsigned int n;\n int v30;\n int v31;\n unsigned long long v32;\n v31 = a3;\n v30 = a2;\n v5 = a2 + 1;\n v6 = 4 * v5;\n v32 = __readfsqword(40u);\n v7 = 4 * v5 * (a3 + 1) + 15;\n v8 = (long long *)((char *)&v27 - (v7 & 18446744073709547520LL));\n v9 = v7 & 65520;\n if (&v27 != v8) {\n while (v26 != (uint8_t *)v8)\n ;\n }\n v10 = v9 & 4095;\n v11 = alloca(v10);\n if (v10) *(uint64_t *)&v26[v10 - 8] = *(uint64_t *)&v26[v10 - 8];\n v12 = v6 >> 2;\n if (v31 < 0 || v30 < 0) {\n v28 = v30;\n } else {\n v13 = v26;\n v14 = 0;\n v28 = v30;\n n = 4LL * v30 + 4;\n do {\n v15 = (char *)memset(v13, 0, n);\n v16 = v14++;\n v13 = &v15[v6];\n } while (v31 != v16);\n if (v31 && v30) {\n v17 = &v26[v6 + 4];\n v18 = 1;\n v19 = (unsigned int)v30;\n while (1) {\n v20 = v17;\n for (i = 0LL; i != v19; ++i) {\n v22 = *(v20 - 1);\n v23 = *(uint32_t *)(a1 + 4 * i);\n *v20 = v22;\n if (v23 > 0 && v23 <= v18)\n *v20 =\n v22 + *(uint32_t *)&v26[4 * v12 * (v18 / v23) + 4 * (int)i] + 1;\n ++v20;\n }\n v17 += v6;\n if (v31 == v18) break;\n ++v18;\n }\n }\n }\n return *(unsigned int *)&v26[4 * v12 * v31 + 4 * v28];\n}" + }, + { + "index": 511, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int num) {\n int sum = 0;\n int i = 2;\n while (i * i <= num) {\n while (num % i == 0) {\n sum += i;\n num /= i;\n }\n i++;\n }\n sum += num;\n return sum;\n}", + "test": "int main() {\n\n assert(func0(12) == 7);\n\n assert(func0(105) == 15);\n\n assert(func0(2) == 2);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x2,-0x4(%rbp)\njmp 1185 \nmov -0x4(%rbp),%eax\nadd %eax,-0x8(%rbp)\nmov -0x14(%rbp),%eax\ncltd\nidivl -0x4(%rbp)\nmov %eax,-0x14(%rbp)\nmov -0x14(%rbp),%eax\ncltd\nidivl -0x4(%rbp)\nmov %edx,%eax\ntest %eax,%eax\nje 1164 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nimul %eax,%eax\ncmp %eax,-0x14(%rbp)\njge 1174 \nmov -0x14(%rbp),%eax\nadd %eax,-0x8(%rbp)\nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 2\njmp short loc_1185\nloc_1164:\nmov eax, [rbp+var_4]\nadd [rbp+var_8], eax\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\nmov [rbp+var_14], eax\nloc_1174:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njz short loc_1164\nadd [rbp+var_4], 1\nloc_1185:\nmov eax, [rbp+var_4]\nimul eax, eax\ncmp [rbp+var_14], eax\njge short loc_1174\nmov eax, [rbp+var_14]\nadd [rbp+var_8], eax\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v3; // [rsp+Ch] [rbp-8h]\n int i; // [rsp+10h] [rbp-4h]\n\n v3 = 0;\n for ( i = 2; a1 >= i * i; ++i )\n {\n while ( !(a1 % i) )\n {\n v3 += i;\n a1 /= i;\n }\n }\n return (unsigned int)(a1 + v3);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 2\njmp short loc_1185\nloc_1164:\nmov eax, [rbp+var_4]\nadd [rbp+var_8], eax\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\nmov [rbp+var_14], eax\nloc_1174:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njz short loc_1164\nadd [rbp+var_4], 1\nloc_1185:\nmov eax, [rbp+var_4]\nimul eax, eax\ncmp [rbp+var_14], eax\njge short loc_1174\nmov eax, [rbp+var_14]\nadd [rbp+var_8], eax\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v3; // [rsp+Ch] [rbp-8h]\n int i; // [rsp+10h] [rbp-4h]\n\n v3 = 0;\n for ( i = 2; a1 >= i * i; ++i )\n {\n while ( !(a1 % i) )\n {\n v3 += i;\n a1 /= i;\n }\n }\n return (unsigned int)(a1 + v3);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v3;\n int i;\n v3 = 0;\n for (i = 2; a1 >= i * i; ++i) {\n while (!(a1 % i)) {\n v3 += i;\n a1 /= i;\n }\n }\n return (unsigned int)(a1 + v3);\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v3;\n int i;\n v3 = 0;\n for (i = 2; a1 >= i * i; ++i) {\n while (!(a1 % i)) {\n v3 += i;\n a1 /= i;\n }\n }\n return (unsigned int)(a1 + v3);\n}" + }, + { + "index": 511, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int num) {\n int sum = 0;\n int i = 2;\n while (i * i <= num) {\n while (num % i == 0) {\n sum += i;\n num /= i;\n }\n i++;\n }\n sum += num;\n return sum;\n}", + "test": "int main() {\n\n assert(func0(12) == 7);\n\n assert(func0(105) == 15);\n\n assert(func0(2) == 2);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x2,%ecx\nmov $0x0,%esi\ncmp $0x3,%edi\njg 117c \nlea (%rdi,%rsi,1),%eax\nretq\nadd %ecx,%esi\nmov %edi,%eax\ncltd\nidiv %ecx\nmov %eax,%edi\ncltd\nidiv %ecx\ntest %edx,%edx\nje 1160 \nadd $0x1,%ecx\nmov %ecx,%eax\nimul %ecx,%eax\ncmp %edi,%eax\njg 115c \nmov %edi,%eax\ncltd\nidiv %ecx\ntest %edx,%edx\nje 1160 \njmp 1170 \n", + "ida_asm": "func0:\nendbr64\nmov ecx, 2\nmov esi, 0\ncmp edi, 3\njg short loc_117C\nloc_115C:\nlea eax, [rdi+rsi]\nretn\nloc_1160:\nadd esi, ecx\nmov eax, edi\ncdq\nidiv ecx\nmov edi, eax\ncdq\nidiv ecx\ntest edx, edx\njz short loc_1160\nloc_1170:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, edi\njg short loc_115C\nloc_117C:\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njz short loc_1160\njmp short loc_1170", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // ecx\n int v2; // esi\n\n v1 = 2;\n v2 = 0;\n if ( a1 > 3 )\n {\n do\n {\n for ( ; !(a1 % v1); a1 /= v1 )\n v2 += v1;\n ++v1;\n }\n while ( v1 * v1 <= a1 );\n }\n return (unsigned int)(a1 + v2);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmov ecx, 2\nmov esi, 0\ncmp edi, 3\njg short loc_117C\nloc_115C:\nlea eax, [rdi+rsi]\nretn\nloc_1160:\nadd esi, ecx\nmov eax, edi\ncdq\nidiv ecx\nmov edi, eax\ncdq\nidiv ecx\ntest edx, edx\njz short loc_1160\nloc_1170:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, edi\njg short loc_115C\nloc_117C:\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njz short loc_1160\njmp short loc_1170", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v1; // ecx\n int v2; // esi\n\n v1 = 2;\n v2 = 0;\n if ( a1 > 3 )\n {\n do\n {\n for ( ; !(a1 % v1); a1 /= v1 )\n v2 += v1;\n ++v1;\n }\n while ( v1 * v1 <= a1 );\n }\n return (unsigned int)(a1 + v2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v1;\n int v2;\n v1 = 2;\n v2 = 0;\n if (a1 > 3) {\n do {\n for (; !(a1 % v1); a1 /= v1) v2 += v1;\n ++v1;\n } while (v1 * v1 <= a1);\n }\n return (unsigned int)(a1 + v2);\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v2;\n v1 = 2;\n v2 = 0;\n if (a1 > 3) {\n do {\n for (; !(a1 % v1); a1 /= v1) v2 += v1;\n ++v1;\n } while (v1 * v1 <= a1);\n }\n return (unsigned int)(a1 + v2);\n}" + }, + { + "index": 511, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int num) {\n int sum = 0;\n int i = 2;\n while (i * i <= num) {\n while (num % i == 0) {\n sum += i;\n num /= i;\n }\n i++;\n }\n sum += num;\n return sum;\n}", + "test": "int main() {\n\n assert(func0(12) == 7);\n\n assert(func0(105) == 15);\n\n assert(func0(2) == 2);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x2,%ecx\nxor %esi,%esi\ncmp $0x3,%edi\njle 1210 \nmov %edi,%eax\ncltd\nidiv %ecx\ntest %edx,%edx\njne 1200 \nnopl 0x0(%rax)\nmov %edi,%eax\nadd %ecx,%esi\ncltd\nidiv %ecx\ncltd\nmov %eax,%edi\nidiv %ecx\ntest %edx,%edx\nje 11f0 \nadd $0x1,%ecx\nmov %ecx,%eax\nimul %ecx,%eax\ncmp %edi,%eax\njle 11e0 \nlea (%rdi,%rsi,1),%eax\nretq\nmov %edi,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\nmov ecx, 2\nxor esi, esi\ncmp edi, 3\njle short loc_1230\nloc_1200:\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_1220\nnop dword ptr [rax+00000000h]\nloc_1210:\nmov eax, edi\nadd esi, ecx\ncdq\nidiv ecx\ncdq\nmov edi, eax\nidiv ecx\ntest edx, edx\njz short loc_1210\nloc_1220:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, edi\njle short loc_1200\nlea eax, [rdi+rsi]\nretn\nloc_1230:\nmov eax, edi\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // ecx\n int v2; // esi\n int v3; // edx\n\n v1 = 2;\n v2 = 0;\n if ( a1 <= 3 )\n return (unsigned int)a1;\n do\n {\n if ( !(a1 % v1) )\n {\n do\n {\n v2 += v1;\n v3 = (a1 / v1) >> 31;\n a1 /= v1;\n }\n while ( !(unsigned int)(__SPAIR64__(v3, a1) % v1) );\n }\n ++v1;\n }\n while ( v1 * v1 <= a1 );\n return (unsigned int)(a1 + v2);\n}", + "ida_strip_asm": "sub_11F0:\nendbr64\nmov ecx, 2\nxor esi, esi\ncmp edi, 3\njle short loc_1230\nloc_1200:\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_1220\nnop dword ptr [rax+00000000h]\nloc_1210:\nmov eax, edi\nadd esi, ecx\ncdq\nidiv ecx\ncdq\nmov edi, eax\nidiv ecx\ntest edx, edx\njz short loc_1210\nloc_1220:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, edi\njle short loc_1200\nlea eax, [rdi+rsi]\nretn\nloc_1230:\nmov eax, edi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11F0(int a1)\n{\n int v1; // ecx\n int v2; // esi\n int v3; // edx\n\n v1 = 2;\n v2 = 0;\n if ( a1 <= 3 )\n return (unsigned int)a1;\n do\n {\n if ( !(a1 % v1) )\n {\n do\n {\n v2 += v1;\n v3 = (a1 / v1) >> 31;\n a1 /= v1;\n }\n while ( !(unsigned int)(__SPAIR64__(v3, a1) % v1) );\n }\n ++v1;\n }\n while ( v1 * v1 <= a1 );\n return (unsigned int)(a1 + v2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11F0(int a1) {\n int v1;\n int v2;\n int v3;\n v1 = 2;\n v2 = 0;\n if (a1 <= 3) return (unsigned int)a1;\n do {\n if (!(a1 % v1)) {\n do {\n v2 += v1;\n v3 = (a1 / v1) >> 31;\n a1 /= v1;\n } while (!(unsigned int)(__SPAIR64__(v3, a1) % v1));\n }\n ++v1;\n } while (v1 * v1 <= a1);\n return (unsigned int)(a1 + v2);\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v2;\n int v3;\n v1 = 2;\n v2 = 0;\n if (a1 <= 3) return (unsigned int)a1;\n do {\n if (!(a1 % v1)) {\n do {\n v2 += v1;\n v3 = (a1 / v1) >> 31;\n a1 /= v1;\n } while (!(unsigned int)(__SPAIR64__(v3, a1) % v1));\n }\n ++v1;\n } while (v1 * v1 <= a1);\n return (unsigned int)(a1 + v2);\n}" + }, + { + "index": 512, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int key;\n\n int value;\n\n} KeyValue;\n\n\n\nvoid flatten(int *tup_array, int *flat_array, int *index, int size) {\n\n for (int i = 0; i < size; i++) {\n\n int curr = tup_array[i];\n\n if (curr == -1) { // assuming -1 as the marker for nested tuple start\n\n // calculate the size of the nested tuple\n\n int nested_size = 0;\n\n i++; // move to the first element of the nested tuple\n\n while (tup_array[i + nested_size] != -2) { // assuming -2 as the marker for nested tuple end\n\n nested_size++;\n\n }\n\n flatten(tup_array + i, flat_array, index, nested_size);\n\n i += nested_size; // skip over the nested tuple\n\n } else if (curr != -2) {\n\n flat_array[(*index)++] = curr;\n\n }\n\n }\n\n}\n\n\n\n", + "func": "int *func0(int *tup_array, int size, int *result_size) {\n int *flat_array = malloc(100 * sizeof(int));\n int index = 0;\n flatten(tup_array, flat_array, &index, size);\n KeyValue *res = malloc(100 * sizeof(KeyValue));\n *result_size = 0;\n for (int i = 0; i < index; i++) {\n int ele = flat_array[i];\n int found = 0;\n for (int j = 0; j < *result_size; j++) {\n if (res[j].key == ele) {\n res[j].value++;\n found = 1;\n break;\n }\n }\n if (!found) {\n res[*result_size].key = ele;\n res[*result_size].value = 1;\n (*result_size)++;\n }\n }\n free(flat_array);\n return (int *)res;\n}", + "test": "int main() {\n\n int test1[] = {5, 6, -1, 5, 6, -2, 7, -1, 8, 9, -2, 9, -2};\n\n int test2[] = {6, 7, -1, 6, 7, -2, 8, -1, 9, 10, -2, 10, -2};\n\n int test3[] = {7, 8, -1, 7, 8, -2, 9, -1, 10, 11, -2, 11, -2};\n\n\n\n int result_size = 0;\n\n KeyValue *result1 = (KeyValue *)func0(test1, sizeof(test1) / sizeof(test1[0]), &result_size);\n\n KeyValue *result2 = (KeyValue *)func0(test2, sizeof(test2) / sizeof(test2[0]), &result_size);\n\n KeyValue *result3 = (KeyValue *)func0(test3, sizeof(test3) / sizeof(test3[0]), &result_size);\n\n\n\n assert(result1[0].value == 2 && result1[1].value == 2 && result1[2].value == 1 && result1[3].value == 1 && result1[4].value == 2);\n\n assert(result2[0].value == 2 && result2[1].value == 2 && result2[2].value == 1 && result2[3].value == 1 && result2[4].value == 2);\n\n assert(result3[0].value == 2 && result3[1].value == 2 && result3[2].value == 1 && result3[3].value == 1 && result3[4].value == 2);\n\n \n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n \n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x50,%rsp\nmov %rdi,-0x38(%rbp)\nmov %esi,-0x3c(%rbp)\nmov %rdx,-0x48(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmov $0x190,%edi\ncallq 10b0 \nmov %rax,-0x18(%rbp)\nmovl $0x0,-0x2c(%rbp)\nmov -0x3c(%rbp),%ecx\nlea -0x2c(%rbp),%rdx\nmov -0x18(%rbp),%rsi\nmov -0x38(%rbp),%rax\nmov %rax,%rdi\ncallq 11a9 \nmov $0x320,%edi\ncallq 10b0 \nmov %rax,-0x10(%rbp)\nmov -0x48(%rbp),%rax\nmovl $0x0,(%rax)\nmovl $0x0,-0x28(%rbp)\njmpq 13d1 \nmov -0x28(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x1c(%rbp)\nmovl $0x0,-0x24(%rbp)\nmovl $0x0,-0x20(%rbp)\njmp 1373 \nmov -0x20(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x10(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x1c(%rbp)\njne 136f \nmov -0x20(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x10(%rbp),%rax\nadd %rdx,%rax\nmov 0x4(%rax),%edx\nadd $0x1,%edx\nmov %edx,0x4(%rax)\nmovl $0x1,-0x24(%rbp)\njmp 137e \naddl $0x1,-0x20(%rbp)\nmov -0x48(%rbp),%rax\nmov (%rax),%eax\ncmp %eax,-0x20(%rbp)\njl 132e \ncmpl $0x0,-0x24(%rbp)\njne 13cd \nmov -0x48(%rbp),%rax\nmov (%rax),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x10(%rbp),%rax\nadd %rax,%rdx\nmov -0x1c(%rbp),%eax\nmov %eax,(%rdx)\nmov -0x48(%rbp),%rax\nmov (%rax),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x10(%rbp),%rax\nadd %rdx,%rax\nmovl $0x1,0x4(%rax)\nmov -0x48(%rbp),%rax\nmov (%rax),%eax\nlea 0x1(%rax),%edx\nmov -0x48(%rbp),%rax\nmov %edx,(%rax)\naddl $0x1,-0x28(%rbp)\nmov -0x2c(%rbp),%eax\ncmp %eax,-0x28(%rbp)\njl 1305 \nmov -0x18(%rbp),%rax\nmov %rax,%rdi\ncallq 1080 \nmov -0x10(%rbp),%rax\nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 1401 \ncallq 1090 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov [rbp+var_48], rdx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov edi, 190h; size\ncall _malloc\nmov [rbp+ptr], rax\nmov [rbp+var_2C], 0\nmov ecx, [rbp+var_3C]\nlea rdx, [rbp+var_2C]\nmov rsi, [rbp+ptr]\nmov rax, [rbp+var_38]\nmov rdi, rax\ncall flatten\nmov edi, 320h; size\ncall _malloc\nmov [rbp+var_10], rax\nmov rax, [rbp+var_48]\nmov dword ptr [rax], 0\nmov [rbp+var_28], 0\njmp loc_13D1\nloc_1305:\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_1C], eax\nmov [rbp+var_24], 0\nmov [rbp+var_20], 0\njmp short loc_1373\nloc_132E:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_10]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_1C], eax\njnz short loc_136F\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_10]\nadd rax, rdx\nmov edx, [rax+4]\nadd edx, 1\nmov [rax+4], edx\nmov [rbp+var_24], 1\njmp short loc_137E\nloc_136F:\nadd [rbp+var_20], 1\nloc_1373:\nmov rax, [rbp+var_48]\nmov eax, [rax]\ncmp [rbp+var_20], eax\njl short loc_132E\nloc_137E:\ncmp [rbp+var_24], 0\njnz short loc_13CD\nmov rax, [rbp+var_48]\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_10]\nadd rdx, rax\nmov eax, [rbp+var_1C]\nmov [rdx], eax\nmov rax, [rbp+var_48]\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_10]\nadd rax, rdx\nmov dword ptr [rax+4], 1\nmov rax, [rbp+var_48]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_48]\nmov [rax], edx\nloc_13CD:\nadd [rbp+var_28], 1\nloc_13D1:\nmov eax, [rbp+var_2C]\ncmp [rbp+var_28], eax\njl loc_1305\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_10]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1401\ncall ___stack_chk_fail\nlocret_1401:\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, unsigned int a2, int *a3)\n{\n int v5; // [rsp+24h] [rbp-2Ch] BYREF\n int i; // [rsp+28h] [rbp-28h]\n int v7; // [rsp+2Ch] [rbp-24h]\n int j; // [rsp+30h] [rbp-20h]\n int v9; // [rsp+34h] [rbp-1Ch]\n void *ptr; // [rsp+38h] [rbp-18h]\n _DWORD *v11; // [rsp+40h] [rbp-10h]\n unsigned __int64 v12; // [rsp+48h] [rbp-8h]\n\n v12 = __readfsqword(0x28u);\n ptr = malloc(0x190uLL);\n v5 = 0;\n flatten(a1, ptr, &v5, a2);\n v11 = malloc(0x320uLL);\n *a3 = 0;\n for ( i = 0; i < v5; ++i )\n {\n v9 = *((_DWORD *)ptr + i);\n v7 = 0;\n for ( j = 0; j < *a3; ++j )\n {\n if ( v9 == v11[2 * j] )\n {\n ++v11[2 * j + 1];\n v7 = 1;\n break;\n }\n }\n if ( !v7 )\n {\n v11[2 * *a3] = v9;\n v11[2 * (*a3)++ + 1] = 1;\n }\n }\n free(ptr);\n return v11;\n}", + "ida_strip_asm": "sub_128F:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov [rbp+var_48], rdx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov edi, 190h; size\ncall _malloc\nmov [rbp+ptr], rax\nmov [rbp+var_2C], 0\nmov ecx, [rbp+var_3C]\nlea rdx, [rbp+var_2C]\nmov rsi, [rbp+ptr]\nmov rax, [rbp+var_38]\nmov rdi, rax\ncall sub_11A9\nmov edi, 320h; size\ncall _malloc\nmov [rbp+var_10], rax\nmov rax, [rbp+var_48]\nmov dword ptr [rax], 0\nmov [rbp+var_28], 0\njmp loc_13D1\nloc_1305:\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_1C], eax\nmov [rbp+var_24], 0\nmov [rbp+var_20], 0\njmp short loc_1373\nloc_132E:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_10]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_1C], eax\njnz short loc_136F\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_10]\nadd rax, rdx\nmov edx, [rax+4]\nadd edx, 1\nmov [rax+4], edx\nmov [rbp+var_24], 1\njmp short loc_137E\nloc_136F:\nadd [rbp+var_20], 1\nloc_1373:\nmov rax, [rbp+var_48]\nmov eax, [rax]\ncmp [rbp+var_20], eax\njl short loc_132E\nloc_137E:\ncmp [rbp+var_24], 0\njnz short loc_13CD\nmov rax, [rbp+var_48]\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_10]\nadd rdx, rax\nmov eax, [rbp+var_1C]\nmov [rdx], eax\nmov rax, [rbp+var_48]\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_10]\nadd rax, rdx\nmov dword ptr [rax+4], 1\nmov rax, [rbp+var_48]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_48]\nmov [rax], edx\nloc_13CD:\nadd [rbp+var_28], 1\nloc_13D1:\nmov eax, [rbp+var_2C]\ncmp [rbp+var_28], eax\njl loc_1305\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_10]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1401\ncall ___stack_chk_fail\nlocret_1401:\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_128F(__int64 a1, unsigned int a2, int *a3)\n{\n int v5; // [rsp+24h] [rbp-2Ch] BYREF\n int i; // [rsp+28h] [rbp-28h]\n int v7; // [rsp+2Ch] [rbp-24h]\n int j; // [rsp+30h] [rbp-20h]\n int v9; // [rsp+34h] [rbp-1Ch]\n void *ptr; // [rsp+38h] [rbp-18h]\n _DWORD *v11; // [rsp+40h] [rbp-10h]\n unsigned __int64 v12; // [rsp+48h] [rbp-8h]\n\n v12 = __readfsqword(0x28u);\n ptr = malloc(0x190uLL);\n v5 = 0;\n sub_11A9(a1, ptr, &v5, a2);\n v11 = malloc(0x320uLL);\n *a3 = 0;\n for ( i = 0; i < v5; ++i )\n {\n v9 = *((_DWORD *)ptr + i);\n v7 = 0;\n for ( j = 0; j < *a3; ++j )\n {\n if ( v9 == v11[2 * j] )\n {\n ++v11[2 * j + 1];\n v7 = 1;\n break;\n }\n }\n if ( !v7 )\n {\n v11[2 * *a3] = v9;\n v11[2 * (*a3)++ + 1] = 1;\n }\n }\n free(ptr);\n return v11;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_128F(long long a1, unsigned int a2, int *a3) {\n int v5;\n int i;\n int v7;\n int j;\n int v9;\n void *ptr;\n uint32_t *v11;\n unsigned long long v12;\n v12 = __readfsqword(40u);\n ptr = malloc(400uLL);\n v5 = 0;\n sub_11A9(a1, ptr, &v5, a2);\n v11 = malloc(800uLL);\n *a3 = 0;\n for (i = 0; i < v5; ++i) {\n v9 = *((uint32_t *)ptr + i);\n v7 = 0;\n for (j = 0; j < *a3; ++j) {\n if (v9 == v11[2 * j]) {\n ++v11[2 * j + 1];\n v7 = 1;\n break;\n }\n }\n if (!v7) {\n v11[2 * *a3] = v9;\n v11[2 * (*a3)++ + 1] = 1;\n }\n }\n free(ptr);\n return v11;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, unsigned int a2, int *a3) {\n int v5;\n int i;\n int v7;\n int j;\n int v9;\n void *ptr;\n uint32_t *v11;\n unsigned long long v12;\n v12 = __readfsqword(40u);\n ptr = malloc(400uLL);\n v5 = 0;\n flatten(a1, ptr, &v5, a2);\n v11 = malloc(800uLL);\n *a3 = 0;\n for (i = 0; i < v5; ++i) {\n v9 = *((uint32_t *)ptr + i);\n v7 = 0;\n for (j = 0; j < *a3; ++j) {\n if (v9 == v11[2 * j]) {\n ++v11[2 * j + 1];\n v7 = 1;\n break;\n }\n }\n if (!v7) {\n v11[2 * *a3] = v9;\n v11[2 * (*a3)++ + 1] = 1;\n }\n }\n free(ptr);\n return v11;\n}" + }, + { + "index": 512, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int key;\n\n int value;\n\n} KeyValue;\n\n\n\nvoid flatten(int *tup_array, int *flat_array, int *index, int size) {\n\n for (int i = 0; i < size; i++) {\n\n int curr = tup_array[i];\n\n if (curr == -1) { // assuming -1 as the marker for nested tuple start\n\n // calculate the size of the nested tuple\n\n int nested_size = 0;\n\n i++; // move to the first element of the nested tuple\n\n while (tup_array[i + nested_size] != -2) { // assuming -2 as the marker for nested tuple end\n\n nested_size++;\n\n }\n\n flatten(tup_array + i, flat_array, index, nested_size);\n\n i += nested_size; // skip over the nested tuple\n\n } else if (curr != -2) {\n\n flat_array[(*index)++] = curr;\n\n }\n\n }\n\n}\n\n\n\n", + "func": "int *func0(int *tup_array, int size, int *result_size) {\n int *flat_array = malloc(100 * sizeof(int));\n int index = 0;\n flatten(tup_array, flat_array, &index, size);\n KeyValue *res = malloc(100 * sizeof(KeyValue));\n *result_size = 0;\n for (int i = 0; i < index; i++) {\n int ele = flat_array[i];\n int found = 0;\n for (int j = 0; j < *result_size; j++) {\n if (res[j].key == ele) {\n res[j].value++;\n found = 1;\n break;\n }\n }\n if (!found) {\n res[*result_size].key = ele;\n res[*result_size].value = 1;\n (*result_size)++;\n }\n }\n free(flat_array);\n return (int *)res;\n}", + "test": "int main() {\n\n int test1[] = {5, 6, -1, 5, 6, -2, 7, -1, 8, 9, -2, 9, -2};\n\n int test2[] = {6, 7, -1, 6, 7, -2, 8, -1, 9, 10, -2, 10, -2};\n\n int test3[] = {7, 8, -1, 7, 8, -2, 9, -1, 10, 11, -2, 11, -2};\n\n\n\n int result_size = 0;\n\n KeyValue *result1 = (KeyValue *)func0(test1, sizeof(test1) / sizeof(test1[0]), &result_size);\n\n KeyValue *result2 = (KeyValue *)func0(test2, sizeof(test2) / sizeof(test2[0]), &result_size);\n\n KeyValue *result3 = (KeyValue *)func0(test3, sizeof(test3) / sizeof(test3[0]), &result_size);\n\n\n\n assert(result1[0].value == 2 && result1[1].value == 2 && result1[2].value == 1 && result1[3].value == 1 && result1[4].value == 2);\n\n assert(result2[0].value == 2 && result2[1].value == 2 && result2[2].value == 1 && result2[3].value == 1 && result2[4].value == 2);\n\n assert(result3[0].value == 2 && result3[1].value == 2 && result3[2].value == 1 && result3[3].value == 1 && result3[4].value == 2);\n\n \n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n \n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov %rdi,%rbx\nmov %esi,%r13d\nmov %rdx,%rbp\nmov %fs:0x28,%rax\nmov %rax,0x8(%rsp)\nxor %eax,%eax\nmov $0x190,%edi\ncallq 10b0 \nmov %rax,%r12\nmovl $0x0,0x4(%rsp)\nlea 0x4(%rsp),%rdx\nmov %r13d,%ecx\nmov %rax,%rsi\nmov %rbx,%rdi\ncallq 11a9 \nmov $0x320,%edi\ncallq 10b0 \nmov %rax,%rbx\nmovl $0x0,0x0(%rbp)\nmov 0x4(%rsp),%eax\ntest %eax,%eax\njle 1316 \nmov %r12,%r8\nlea -0x1(%rax),%eax\nlea 0x4(%r12,%rax,4),%r9\njmp 12f2 \naddl $0x1,0x4(%rax)\njmp 12e9 \nmovslq %edi,%rax\nlea (%rbx,%rax,8),%rax\nmov %edx,(%rax)\nmovl $0x1,0x4(%rax)\nadd $0x1,%edi\nmov %edi,0x0(%rbp)\nadd $0x4,%r8\ncmp %r9,%r8\nje 1316 \nmov (%r8),%edx\nmov 0x0(%rbp),%edi\ntest %edi,%edi\njle 12d3 \nmov %rbx,%rax\nlea -0x1(%rdi),%ecx\nlea 0x8(%rbx,%rcx,8),%rsi\ncmp %edx,(%rax)\nje 12cd \nadd $0x8,%rax\ncmp %rsi,%rax\njne 1307 \njmp 12d3 \nmov %r12,%rdi\ncallq 1080 \nmov 0x8(%rsp),%rax\nxor %fs:0x28,%rax\njne 133c \nmov %rbx,%rax\nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\ncallq 1090 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov rbx, rdi\nmov r13d, esi\nmov rbp, rdx\nmov rax, fs:28h\nmov [rsp+38h+var_30], rax\nxor eax, eax\nmov edi, 190h; size\ncall _malloc\nmov r12, rax\nmov [rsp+38h+var_34], 0\nlea rdx, [rsp+38h+var_34]\nmov ecx, r13d\nmov rsi, rax\nmov rdi, rbx\ncall flatten\nmov edi, 320h; size\ncall _malloc\nmov rbx, rax\nmov dword ptr [rbp+0], 0\nmov eax, [rsp+38h+var_34]\ntest eax, eax\njle short loc_12FF\nmov rdi, r12\ncdqe\nlea r8, [r12+rax*4]\njmp short loc_12DD\nloc_12B8:\nadd dword ptr [rax+4], 1\njmp short loc_12D4\nloc_12BE:\nmovsxd rax, esi\nlea rax, [rbx+rax*8]\nmov [rax], edx\nmov dword ptr [rax+4], 1\nadd esi, 1\nmov [rbp+0], esi\nloc_12D4:\nadd rdi, 4\ncmp rdi, r8\njz short loc_12FF\nloc_12DD:\nmov edx, [rdi]\nmov esi, [rbp+0]\ntest esi, esi\njle short loc_12BE\nmov rax, rbx\nmovsxd rcx, esi\nlea rcx, [rbx+rcx*8]\nloc_12F0:\ncmp [rax], edx\njz short loc_12B8\nadd rax, 8\ncmp rax, rcx\njnz short loc_12F0\njmp short loc_12BE\nloc_12FF:\nmov rdi, r12; ptr\ncall _free\nmov rax, [rsp+38h+var_30]\nsub rax, fs:28h\njnz short loc_1325\nmov rax, rbx\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1325:\ncall ___stack_chk_fail", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, unsigned int a2, int *a3)\n{\n int *v4; // r12\n _DWORD *v5; // rbx\n int *v6; // rdi\n int *v7; // r8\n _DWORD *v8; // rax\n int v9; // edx\n int v10; // esi\n _DWORD *v11; // rax\n int v13; // [rsp+4h] [rbp-34h] BYREF\n unsigned __int64 v14; // [rsp+8h] [rbp-30h]\n\n v14 = __readfsqword(0x28u);\n v4 = (int *)malloc(0x190uLL);\n v13 = 0;\n flatten(a1, v4, &v13, a2);\n v5 = malloc(0x320uLL);\n *a3 = 0;\n if ( v13 > 0 )\n {\n v6 = v4;\n v7 = &v4[v13];\n do\n {\n v9 = *v6;\n v10 = *a3;\n if ( *a3 <= 0 )\n {\nLABEL_4:\n v8 = &v5[2 * v10];\n *v8 = v9;\n v8[1] = 1;\n *a3 = v10 + 1;\n }\n else\n {\n v11 = v5;\n while ( *v11 != v9 )\n {\n v11 += 2;\n if ( v11 == &v5[2 * v10] )\n goto LABEL_4;\n }\n ++v11[1];\n }\n ++v6;\n }\n while ( v6 != v7 );\n }\n free(v4);\n return v5;\n}", + "ida_strip_asm": "sub_1242:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov rbx, rdi\nmov r13d, esi\nmov rbp, rdx\nmov rax, fs:28h\nmov [rsp+38h+var_30], rax\nxor eax, eax\nmov edi, 190h; size\ncall _malloc\nmov r12, rax\nmov [rsp+38h+var_34], 0\nlea rdx, [rsp+38h+var_34]\nmov ecx, r13d\nmov rsi, rax\nmov rdi, rbx\ncall sub_11A9\nmov edi, 320h; size\ncall _malloc\nmov rbx, rax\nmov dword ptr [rbp+0], 0\nmov eax, [rsp+38h+var_34]\ntest eax, eax\njle short loc_12FF\nmov rdi, r12\ncdqe\nlea r8, [r12+rax*4]\njmp short loc_12DD\nloc_12B8:\nadd dword ptr [rax+4], 1\njmp short loc_12D4\nloc_12BE:\nmovsxd rax, esi\nlea rax, [rbx+rax*8]\nmov [rax], edx\nmov dword ptr [rax+4], 1\nadd esi, 1\nmov [rbp+0], esi\nloc_12D4:\nadd rdi, 4\ncmp rdi, r8\njz short loc_12FF\nloc_12DD:\nmov edx, [rdi]\nmov esi, [rbp+0]\ntest esi, esi\njle short loc_12BE\nmov rax, rbx\nmovsxd rcx, esi\nlea rcx, [rbx+rcx*8]\nloc_12F0:\ncmp [rax], edx\njz short loc_12B8\nadd rax, 8\ncmp rax, rcx\njnz short loc_12F0\njmp short loc_12BE\nloc_12FF:\nmov rdi, r12; ptr\ncall _free\nmov rax, [rsp+38h+var_30]\nsub rax, fs:28h\njnz short loc_1325\nmov rax, rbx\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1325:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1242(__int64 a1, unsigned int a2, int *a3)\n{\n int *v4; // r12\n _DWORD *v5; // rbx\n int *v6; // rdi\n int *v7; // r8\n _DWORD *v8; // rax\n int v9; // edx\n int v10; // esi\n _DWORD *v11; // rax\n int v13; // [rsp+4h] [rbp-34h] BYREF\n unsigned __int64 v14; // [rsp+8h] [rbp-30h]\n\n v14 = __readfsqword(0x28u);\n v4 = (int *)malloc(0x190uLL);\n v13 = 0;\n sub_11A9(a1, v4, &v13, a2);\n v5 = malloc(0x320uLL);\n *a3 = 0;\n if ( v13 > 0 )\n {\n v6 = v4;\n v7 = &v4[v13];\n do\n {\n v9 = *v6;\n v10 = *a3;\n if ( *a3 <= 0 )\n {\nLABEL_4:\n v8 = &v5[2 * v10];\n *v8 = v9;\n v8[1] = 1;\n *a3 = v10 + 1;\n }\n else\n {\n v11 = v5;\n while ( *v11 != v9 )\n {\n v11 += 2;\n if ( v11 == &v5[2 * v10] )\n goto LABEL_4;\n }\n ++v11[1];\n }\n ++v6;\n }\n while ( v6 != v7 );\n }\n free(v4);\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1242(long long a1, unsigned int a2, int *a3) {\n int *v4;\n uint32_t *v5;\n int *v6;\n int *v7;\n uint32_t *v8;\n int v9;\n int v10;\n uint32_t *v11;\n int v13;\n unsigned long long v14;\n v14 = __readfsqword(40u);\n v4 = (int *)malloc(400uLL);\n v13 = 0;\n sub_11A9(a1, v4, &v13, a2);\n v5 = malloc(800uLL);\n *a3 = 0;\n if (v13 > 0) {\n v6 = v4;\n v7 = &v4[v13];\n do {\n v9 = *v6;\n v10 = *a3;\n if (*a3 <= 0) {\n LABEL_4:\n v8 = &v5[2 * v10];\n *v8 = v9;\n v8[1] = 1;\n *a3 = v10 + 1;\n } else {\n v11 = v5;\n while (*v11 != v9) {\n v11 += 2;\n if (v11 == &v5[2 * v10]) goto LABEL_4;\n }\n ++v11[1];\n }\n ++v6;\n } while (v6 != v7);\n }\n free(v4);\n return v5;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, unsigned int a2, int *a3) {\n int *v4;\n uint32_t *v5;\n int *v6;\n int *v7;\n uint32_t *v8;\n int v9;\n int v10;\n uint32_t *v11;\n int v13;\n unsigned long long v14;\n v14 = __readfsqword(40u);\n v4 = (int *)malloc(400uLL);\n v13 = 0;\n flatten(a1, v4, &v13, a2);\n v5 = malloc(800uLL);\n *a3 = 0;\n if (v13 > 0) {\n v6 = v4;\n v7 = &v4[v13];\n do {\n v9 = *v6;\n v10 = *a3;\n if (*a3 <= 0) {\n LABEL_4:\n v8 = &v5[2 * v10];\n *v8 = v9;\n v8[1] = 1;\n *a3 = v10 + 1;\n } else {\n v11 = v5;\n while (*v11 != v9) {\n v11 += 2;\n if (v11 == &v5[2 * v10]) goto LABEL_4;\n }\n ++v11[1];\n }\n ++v6;\n } while (v6 != v7);\n }\n free(v4);\n return v5;\n}" + }, + { + "index": 512, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int key;\n\n int value;\n\n} KeyValue;\n\n\n\nvoid flatten(int *tup_array, int *flat_array, int *index, int size) {\n\n for (int i = 0; i < size; i++) {\n\n int curr = tup_array[i];\n\n if (curr == -1) { // assuming -1 as the marker for nested tuple start\n\n // calculate the size of the nested tuple\n\n int nested_size = 0;\n\n i++; // move to the first element of the nested tuple\n\n while (tup_array[i + nested_size] != -2) { // assuming -2 as the marker for nested tuple end\n\n nested_size++;\n\n }\n\n flatten(tup_array + i, flat_array, index, nested_size);\n\n i += nested_size; // skip over the nested tuple\n\n } else if (curr != -2) {\n\n flat_array[(*index)++] = curr;\n\n }\n\n }\n\n}\n\n\n\n", + "func": "int *func0(int *tup_array, int size, int *result_size) {\n int *flat_array = malloc(100 * sizeof(int));\n int index = 0;\n flatten(tup_array, flat_array, &index, size);\n KeyValue *res = malloc(100 * sizeof(KeyValue));\n *result_size = 0;\n for (int i = 0; i < index; i++) {\n int ele = flat_array[i];\n int found = 0;\n for (int j = 0; j < *result_size; j++) {\n if (res[j].key == ele) {\n res[j].value++;\n found = 1;\n break;\n }\n }\n if (!found) {\n res[*result_size].key = ele;\n res[*result_size].value = 1;\n (*result_size)++;\n }\n }\n free(flat_array);\n return (int *)res;\n}", + "test": "int main() {\n\n int test1[] = {5, 6, -1, 5, 6, -2, 7, -1, 8, 9, -2, 9, -2};\n\n int test2[] = {6, 7, -1, 6, 7, -2, 8, -1, 9, 10, -2, 10, -2};\n\n int test3[] = {7, 8, -1, 7, 8, -2, 9, -1, 10, 11, -2, 11, -2};\n\n\n\n int result_size = 0;\n\n KeyValue *result1 = (KeyValue *)func0(test1, sizeof(test1) / sizeof(test1[0]), &result_size);\n\n KeyValue *result2 = (KeyValue *)func0(test2, sizeof(test2) / sizeof(test2[0]), &result_size);\n\n KeyValue *result3 = (KeyValue *)func0(test3, sizeof(test3) / sizeof(test3[0]), &result_size);\n\n\n\n assert(result1[0].value == 2 && result1[1].value == 2 && result1[2].value == 1 && result1[3].value == 1 && result1[4].value == 2);\n\n assert(result2[0].value == 2 && result2[1].value == 2 && result2[2].value == 1 && result2[3].value == 1 && result2[4].value == 2);\n\n assert(result3[0].value == 2 && result3[1].value == 2 && result3[2].value == 1 && result3[3].value == 1 && result3[4].value == 2);\n\n \n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n \n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov %esi,%r13d\npush %r12\nmov %rdi,%r12\nmov $0x190,%edi\npush %rbp\npush %rbx\nmov %rdx,%rbx\nsub $0x18,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x8(%rsp)\nxor %eax,%eax\ncallq 10b0 \nmov %r12,%rdi\nlea 0x4(%rsp),%rdx\nmov %r13d,%ecx\nmov %rax,%rsi\nmov %rax,%rbp\nmovl $0x0,0x4(%rsp)\ncallq 1480 \nmov $0x320,%edi\ncallq 10b0 \nmovl $0x0,(%rbx)\nmov %rax,%r12\nmov 0x4(%rsp),%eax\ntest %eax,%eax\njle 160e \nmov %rbp,%r8\nsub $0x1,%eax\nlea 0x8(%r12),%r10\nxor %edi,%edi\nmov (%r8),%ecx\nlea 0x4(%rbp,%rax,4),%r9\ntest %edi,%edi\njle 15f0 \nnopl 0x0(%rax,%rax,1)\nlea -0x1(%rdi),%eax\nmov %r12,%rdx\nlea (%r10,%rax,8),%rsi\njmp 15d1 \nnopl 0x0(%rax)\nadd $0x8,%rdx\ncmp %rsi,%rdx\nje 15f0 \ncmp %ecx,(%rdx)\njne 15c8 \nadd $0x4,%r8\naddl $0x1,0x4(%rdx)\ncmp %r9,%r8\nje 160e \nmov (%rbx),%edi\nmov (%r8),%ecx\ntest %edi,%edi\njg 15b8 \nnopl 0x0(%rax,%rax,1)\nmovslq %edi,%rax\nadd $0x4,%r8\nadd $0x1,%edi\nlea (%r12,%rax,8),%rax\nmov %edi,(%rbx)\nmov %ecx,(%rax)\nmovl $0x1,0x4(%rax)\ncmp %r9,%r8\njne 15e2 \nmov %rbp,%rdi\ncallq 1080 \nmov 0x8(%rsp),%rax\nxor %fs:0x28,%rax\njne 1634 \nadd $0x18,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\ncallq 1090 <__stack_chk_fail@plt>\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r13\nmov r13, rdi\nmov edi, 190h; size\npush r12\npush rbp\nmov rbp, rdx\npush rbx\nmov ebx, esi\nsub rsp, 18h\nmov rax, fs:28h\nmov [rsp+38h+var_30], rax\nxor eax, eax\ncall _malloc\nmov ecx, ebx\nlea rdx, [rsp+38h+var_34]\nmov rdi, r13\nmov rsi, rax\nmov r12, rax\nmov [rsp+38h+var_34], 0\ncall flatten\nmov edi, 320h; size\ncall _malloc\nmov dword ptr [rbp+0], 0\nmov rbx, rax\nmovsxd rax, [rsp+38h+var_34]\ntest eax, eax\njle short loc_155C\nmov rdi, r12\nxor esi, esi\nlea r9, [r12+rax*4]\nmov edx, [rdi]\nmovsxd r8, esi\ntest esi, esi\njle short loc_1540\nnop dword ptr [rax+00h]\nloc_1500:\nmovsxd r8, esi\nmov rax, rbx\nlea rcx, [rbx+r8*8]\njmp short loc_1519\nloc_1510:\nadd rax, 8\ncmp rax, rcx\njz short loc_1540\nloc_1519:\ncmp [rax], edx\njnz short loc_1510\nadd rdi, 4\nadd dword ptr [rax+4], 1\ncmp rdi, r9\njz short loc_155C\nloc_152A:\nmov esi, [rbp+0]\nmov edx, [rdi]\nmovsxd r8, esi\ntest esi, esi\njg short loc_1500\nnop word ptr [rax+rax+00000000h]\nloc_1540:\nlea rax, [rbx+r8*8]\nadd esi, 1\nadd rdi, 4\nmov [rax], edx\nmov dword ptr [rax+4], 1\nmov [rbp+0], esi\ncmp rdi, r9\njnz short loc_152A\nloc_155C:\nmov rdi, r12; ptr\ncall _free\nmov rax, [rsp+38h+var_30]\nsub rax, fs:28h\njnz short loc_1582\nadd rsp, 18h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1582:\ncall ___stack_chk_fail", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, unsigned int a2, int *a3)\n{\n int *v4; // r12\n _DWORD *v5; // rax\n _DWORD *v6; // rbx\n int *v7; // rdi\n int v8; // esi\n int *v9; // r9\n int v10; // edx\n __int64 v11; // r8\n _DWORD *v12; // rax\n _DWORD *v13; // rax\n int v15; // [rsp+4h] [rbp-34h] BYREF\n unsigned __int64 v16; // [rsp+8h] [rbp-30h]\n\n v16 = __readfsqword(0x28u);\n v4 = (int *)malloc(0x190uLL);\n v15 = 0;\n flatten(a1, v4, &v15, a2);\n v5 = malloc(0x320uLL);\n *a3 = 0;\n v6 = v5;\n if ( v15 > 0 )\n {\n v7 = v4;\n v8 = 0;\n v9 = &v4[v15];\n v10 = *v4;\n v11 = 0LL;\nLABEL_8:\n while ( 1 )\n {\n v13 = &v6[2 * v11];\n ++v7;\n *v13 = v10;\n v13[1] = 1;\n *a3 = v8 + 1;\n if ( v7 == v9 )\n break;\n while ( 1 )\n {\n v8 = *a3;\n v10 = *v7;\n v11 = *a3;\n if ( *a3 <= 0 )\n break;\n v11 = v8;\n v12 = v6;\n while ( *v12 != v10 )\n {\n v12 += 2;\n if ( v12 == &v6[2 * v8] )\n goto LABEL_8;\n }\n ++v7;\n ++v12[1];\n if ( v7 == v9 )\n goto LABEL_9;\n }\n }\n }\nLABEL_9:\n free(v4);\n return v6;\n}", + "ida_strip_asm": "sub_1480:\nendbr64\npush r13\nmov r13, rdi\nmov edi, 190h; size\npush r12\npush rbp\nmov rbp, rdx\npush rbx\nmov ebx, esi\nsub rsp, 18h\nmov rax, fs:28h\nmov [rsp+38h+var_30], rax\nxor eax, eax\ncall _malloc\nmov ecx, ebx\nlea rdx, [rsp+38h+var_34]\nmov rdi, r13\nmov rsi, rax\nmov r12, rax\nmov [rsp+38h+var_34], 0\ncall sub_13E0\nmov edi, 320h; size\ncall _malloc\nmov dword ptr [rbp+0], 0\nmov rbx, rax\nmovsxd rax, [rsp+38h+var_34]\ntest eax, eax\njle short loc_155C\nmov rdi, r12\nxor esi, esi\nlea r9, [r12+rax*4]\nmov edx, [rdi]\nmovsxd r8, esi\ntest esi, esi\njle short loc_1540\nnop dword ptr [rax+00h]\nloc_1500:\nmovsxd r8, esi\nmov rax, rbx\nlea rcx, [rbx+r8*8]\njmp short loc_1519\nloc_1510:\nadd rax, 8\ncmp rax, rcx\njz short loc_1540\nloc_1519:\ncmp [rax], edx\njnz short loc_1510\nadd rdi, 4\nadd dword ptr [rax+4], 1\ncmp rdi, r9\njz short loc_155C\nloc_152A:\nmov esi, [rbp+0]\nmov edx, [rdi]\nmovsxd r8, esi\ntest esi, esi\njg short loc_1500\nnop word ptr [rax+rax+00000000h]\nloc_1540:\nlea rax, [rbx+r8*8]\nadd esi, 1\nadd rdi, 4\nmov [rax], edx\nmov dword ptr [rax+4], 1\nmov [rbp+0], esi\ncmp rdi, r9\njnz short loc_152A\nloc_155C:\nmov rdi, r12; ptr\ncall _free\nmov rax, [rsp+38h+var_30]\nsub rax, fs:28h\njnz short loc_1582\nadd rsp, 18h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1582:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1480(__int64 a1, unsigned int a2, int *a3)\n{\n int *v4; // r12\n _DWORD *v5; // rax\n _DWORD *v6; // rbx\n int *v7; // rdi\n int v8; // esi\n int *v9; // r9\n int v10; // edx\n __int64 v11; // r8\n _DWORD *v12; // rax\n _DWORD *v13; // rax\n int v15; // [rsp+4h] [rbp-34h] BYREF\n unsigned __int64 v16; // [rsp+8h] [rbp-30h]\n\n v16 = __readfsqword(0x28u);\n v4 = (int *)malloc(0x190uLL);\n v15 = 0;\n sub_13E0(a1, v4, &v15, a2);\n v5 = malloc(0x320uLL);\n *a3 = 0;\n v6 = v5;\n if ( v15 > 0 )\n {\n v7 = v4;\n v8 = 0;\n v9 = &v4[v15];\n v10 = *v4;\n v11 = 0LL;\nLABEL_8:\n while ( 1 )\n {\n v13 = &v6[2 * v11];\n ++v7;\n *v13 = v10;\n v13[1] = 1;\n *a3 = v8 + 1;\n if ( v7 == v9 )\n break;\n while ( 1 )\n {\n v8 = *a3;\n v10 = *v7;\n v11 = *a3;\n if ( *a3 <= 0 )\n break;\n v11 = v8;\n v12 = v6;\n while ( *v12 != v10 )\n {\n v12 += 2;\n if ( v12 == &v6[2 * v8] )\n goto LABEL_8;\n }\n ++v7;\n ++v12[1];\n if ( v7 == v9 )\n goto LABEL_9;\n }\n }\n }\nLABEL_9:\n free(v4);\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1480(long long a1, unsigned int a2, int *a3) {\n int *v4;\n uint32_t *v5;\n uint32_t *v6;\n int *v7;\n int v8;\n int *v9;\n int v10;\n long long v11;\n uint32_t *v12;\n uint32_t *v13;\n int v15;\n unsigned long long v16;\n v16 = __readfsqword(40u);\n v4 = (int *)malloc(400uLL);\n v15 = 0;\n sub_13E0(a1, v4, &v15, a2);\n v5 = malloc(800uLL);\n *a3 = 0;\n v6 = v5;\n if (v15 > 0) {\n v7 = v4;\n v8 = 0;\n v9 = &v4[v15];\n v10 = *v4;\n v11 = 0LL;\n LABEL_8:\n while (1) {\n v13 = &v6[2 * v11];\n ++v7;\n *v13 = v10;\n v13[1] = 1;\n *a3 = v8 + 1;\n if (v7 == v9) break;\n while (1) {\n v8 = *a3;\n v10 = *v7;\n v11 = *a3;\n if (*a3 <= 0) break;\n v11 = v8;\n v12 = v6;\n while (*v12 != v10) {\n v12 += 2;\n if (v12 == &v6[2 * v8]) goto LABEL_8;\n }\n ++v7;\n ++v12[1];\n if (v7 == v9) goto LABEL_9;\n }\n }\n }\nLABEL_9:\n free(v4);\n return v6;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, unsigned int a2, int *a3) {\n int *v4;\n uint32_t *v5;\n uint32_t *v6;\n int *v7;\n int v8;\n int *v9;\n int v10;\n long long v11;\n uint32_t *v12;\n uint32_t *v13;\n int v15;\n unsigned long long v16;\n v16 = __readfsqword(40u);\n v4 = (int *)malloc(400uLL);\n v15 = 0;\n flatten(a1, v4, &v15, a2);\n v5 = malloc(800uLL);\n *a3 = 0;\n v6 = v5;\n if (v15 > 0) {\n v7 = v4;\n v8 = 0;\n v9 = &v4[v15];\n v10 = *v4;\n v11 = 0LL;\n LABEL_8:\n while (1) {\n v13 = &v6[2 * v11];\n ++v7;\n *v13 = v10;\n v13[1] = 1;\n *a3 = v8 + 1;\n if (v7 == v9) break;\n while (1) {\n v8 = *a3;\n v10 = *v7;\n v11 = *a3;\n if (*a3 <= 0) break;\n v11 = v8;\n v12 = v6;\n while (*v12 != v10) {\n v12 += 2;\n if (v12 == &v6[2 * v8]) goto LABEL_8;\n }\n ++v7;\n ++v12[1];\n if (v7 == v9) goto LABEL_9;\n }\n }\n }\nLABEL_9:\n free(v4);\n return v6;\n}" + }, + { + "index": 512, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int key;\n\n int value;\n\n} KeyValue;\n\n\n\nvoid flatten(int *tup_array, int *flat_array, int *index, int size) {\n\n for (int i = 0; i < size; i++) {\n\n int curr = tup_array[i];\n\n if (curr == -1) { // assuming -1 as the marker for nested tuple start\n\n // calculate the size of the nested tuple\n\n int nested_size = 0;\n\n i++; // move to the first element of the nested tuple\n\n while (tup_array[i + nested_size] != -2) { // assuming -2 as the marker for nested tuple end\n\n nested_size++;\n\n }\n\n flatten(tup_array + i, flat_array, index, nested_size);\n\n i += nested_size; // skip over the nested tuple\n\n } else if (curr != -2) {\n\n flat_array[(*index)++] = curr;\n\n }\n\n }\n\n}\n\n\n\n", + "func": "int *func0(int *tup_array, int size, int *result_size) {\n int *flat_array = malloc(100 * sizeof(int));\n int index = 0;\n flatten(tup_array, flat_array, &index, size);\n KeyValue *res = malloc(100 * sizeof(KeyValue));\n *result_size = 0;\n for (int i = 0; i < index; i++) {\n int ele = flat_array[i];\n int found = 0;\n for (int j = 0; j < *result_size; j++) {\n if (res[j].key == ele) {\n res[j].value++;\n found = 1;\n break;\n }\n }\n if (!found) {\n res[*result_size].key = ele;\n res[*result_size].value = 1;\n (*result_size)++;\n }\n }\n free(flat_array);\n return (int *)res;\n}", + "test": "int main() {\n\n int test1[] = {5, 6, -1, 5, 6, -2, 7, -1, 8, 9, -2, 9, -2};\n\n int test2[] = {6, 7, -1, 6, 7, -2, 8, -1, 9, 10, -2, 10, -2};\n\n int test3[] = {7, 8, -1, 7, 8, -2, 9, -1, 10, 11, -2, 11, -2};\n\n\n\n int result_size = 0;\n\n KeyValue *result1 = (KeyValue *)func0(test1, sizeof(test1) / sizeof(test1[0]), &result_size);\n\n KeyValue *result2 = (KeyValue *)func0(test2, sizeof(test2) / sizeof(test2[0]), &result_size);\n\n KeyValue *result3 = (KeyValue *)func0(test3, sizeof(test3) / sizeof(test3[0]), &result_size);\n\n\n\n assert(result1[0].value == 2 && result1[1].value == 2 && result1[2].value == 1 && result1[3].value == 1 && result1[4].value == 2);\n\n assert(result2[0].value == 2 && result2[1].value == 2 && result2[2].value == 1 && result2[3].value == 1 && result2[4].value == 2);\n\n assert(result3[0].value == 2 && result3[1].value == 2 && result3[2].value == 1 && result3[3].value == 1 && result3[4].value == 2);\n\n \n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n \n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\nmov %rdx,%r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x68,%rsp\nmov %rdi,0x8(%rsp)\nmov $0x190,%edi\nmov %esi,(%rsp)\nmov %fs:0x28,%rax\nmov %rax,0x58(%rsp)\nxor %eax,%eax\ncallq 10b0 \nmov (%rsp),%r9d\nmov 0x8(%rsp),%r8\nmovl $0x0,0x54(%rsp)\nmov %rax,%r15\nlea 0x54(%rsp),%rax\ntest %r9d,%r9d\nmov %rax,0x10(%rsp)\njle 1548 \nmov %r14,(%rsp)\nmov %r9d,%eax\nxor %r10d,%r10d\nmov %r15,%r9\nmov %eax,%r15d\nmovslq %r10d,%rax\nlea 0x1(%r10),%esi\nshl $0x2,%rax\nlea (%r8,%rax,1),%rcx\nmov (%rcx),%edx\ncmp $0xffffffff,%edx\nje 15f8 \nmov %esi,%r10d\ncmp $0xfffffffe,%edx\nje 153c \nmovslq 0x54(%rsp),%rax\nlea 0x1(%rax),%ecx\nmov %edx,(%r9,%rax,4)\nmov %ecx,0x54(%rsp)\ncmp %r10d,%r15d\njg 150a \nmov (%rsp),%r14\nmov %r9,%r15\nmov $0x320,%edi\ncallq 10b0 \nmovl $0x0,(%r14)\nmov %rax,%r12\nmov 0x54(%rsp),%eax\ntest %eax,%eax\njle 15b2 \nsub $0x1,%eax\nmov %r15,%r8\nlea 0x8(%r12),%r10\nxor %edi,%edi\nlea 0x4(%r15,%rax,4),%r9\nnopw %cs:0x0(%rax,%rax,1)\nmov (%r8),%edx\ntest %edi,%edi\nje 15e0 \nlea -0x1(%rdi),%ecx\nmov %r12,%rax\nlea (%r10,%rcx,8),%rcx\njmp 15a1 \nnopl 0x0(%rax,%rax,1)\nadd $0x8,%rax\ncmp %rcx,%rax\nje 15e0 \ncmp %edx,(%rax)\njne 1598 \naddl $0x1,0x4(%rax)\nadd $0x4,%r8\ncmp %r8,%r9\njne 1580 \nmov %r15,%rdi\ncallq 1080 \nmov 0x58(%rsp),%rax\nxor %fs:0x28,%rax\njne 1990 \nadd $0x68,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmovslq %edi,%rax\nadd $0x1,%edi\nlea (%r12,%rax,8),%rax\nmov %edi,(%r14)\nmov %edx,(%rax)\nmovl $0x1,0x4(%rax)\njmp 15a9 \nlea 0x4(%r8,%rax,1),%r13\nadd $0x2,%r10d\nxor %eax,%eax\nmov 0x0(%r13),%edx\ncmp $0xfffffffe,%edx\nje 153c \nmov %eax,%r12d\nlea (%r10,%rax,1),%r14d\nadd $0x1,%rax\ncmpl $0xfffffffe,0x4(%rcx,%rax,4)\njne 1610 \nxor %r10d,%r10d\nmov %r8,0x18(%rsp)\nmov %r13,%r8\nmov %r15d,0x28(%rsp)\nlea 0x1(%r10),%eax\nmov %r12d,%r15d\nmov %r14d,0x8(%rsp)\ncmp $0xffffffff,%edx\nje 1674 \ncmp $0xfffffffe,%edx\nje 1658 \nmovslq 0x54(%rsp),%rcx\nlea 0x1(%rcx),%esi\nmov %edx,(%r9,%rcx,4)\nmov %esi,0x54(%rsp)\ncmp %r15d,%r10d\njge 18e0 \nmovslq %eax,%rdx\nmov %eax,%r10d\nmov (%r8,%rdx,4),%edx\nlea 0x1(%r10),%eax\ncmp $0xffffffff,%edx\njne 1643 \nmovslq %eax,%rcx\nshl $0x2,%rcx\nlea (%r8,%rcx,1),%r13\nmov 0x0(%r13),%edx\ncmp $0xfffffffe,%edx\nje 194f \nlea -0x4(%r8,%rcx,1),%rsi\nxor %eax,%eax\nlea 0x2(%r10),%ecx\nnopw 0x0(%rax,%rax,1)\nmov %eax,%r12d\nlea (%rcx,%rax,1),%r14d\nadd $0x1,%rax\ncmpl $0xfffffffe,0x4(%rsi,%rax,4)\njne 16a0 \nxor %r10d,%r10d\nmov %r8,0x20(%rsp)\nmov %r12d,%r8d\nmov %r15d,0x2c(%rsp)\nlea 0x1(%r10),%eax\nmov %r14d,0x38(%rsp)\ncmp $0xffffffff,%edx\nje 1702 \ncmp $0xfffffffe,%edx\nje 16e5 \nmovslq 0x54(%rsp),%rcx\nlea 0x1(%rcx),%esi\nmov %edx,(%r9,%rcx,4)\nmov %esi,0x54(%rsp)\ncmp %r8d,%r10d\njge 18f8 \nmovslq %eax,%rdx\nmov %eax,%r10d\nmov 0x0(%r13,%rdx,4),%edx\nlea 0x1(%r10),%eax\ncmp $0xffffffff,%edx\njne 16d0 \nmovslq %eax,%rcx\nshl $0x2,%rcx\nlea 0x0(%r13,%rcx,1),%r14\nmov (%r14),%edx\ncmp $0xfffffffe,%edx\nje 195d \nlea -0x4(%r13,%rcx,1),%rsi\nxor %eax,%eax\nlea 0x2(%r10),%ecx\nnopl (%rax)\nmov %eax,%r11d\nlea (%rcx,%rax,1),%r15d\nadd $0x1,%rax\ncmpl $0xfffffffe,0x4(%rsi,%rax,4)\njne 1728 \nxor %r10d,%r10d\nmov %r13,0x30(%rsp)\nmov %r9,%r13\nmov %r8d,0x3c(%rsp)\nlea 0x1(%r10),%eax\nmov %r15d,0x48(%rsp)\ncmp $0xffffffff,%edx\nje 178a \ncmp $0xfffffffe,%edx\nje 176e \nmovslq 0x54(%rsp),%rcx\nlea 0x1(%rcx),%esi\nmov %edx,0x0(%r13,%rcx,4)\nmov %esi,0x54(%rsp)\ncmp %r11d,%r10d\njge 1913 \nmovslq %eax,%rdx\nmov %eax,%r10d\nmov (%r14,%rdx,4),%edx\nlea 0x1(%r10),%eax\ncmp $0xffffffff,%edx\njne 1758 \nmovslq %eax,%rcx\nshl $0x2,%rcx\nlea (%r14,%rcx,1),%r8\nmov (%r8),%edx\ncmp $0xfffffffe,%edx\nje 196b \nlea -0x4(%r14,%rcx,1),%rsi\nxor %eax,%eax\nlea 0x2(%r10),%ecx\nnopl 0x0(%rax)\nmov %eax,%ebp\nlea (%rcx,%rax,1),%r10d\nadd $0x1,%rax\ncmpl $0xfffffffe,0x4(%rsi,%rax,4)\njne 17b0 \nxor %ebx,%ebx\nmov %r8,%r15\nlea 0x1(%rbx),%eax\ncmp $0xffffffff,%edx\nje 17fd \ncmp $0xfffffffe,%edx\nje 17e4 \nmovslq 0x54(%rsp),%rcx\nlea 0x1(%rcx),%esi\nmov %edx,0x0(%r13,%rcx,4)\nmov %esi,0x54(%rsp)\ncmp %ebp,%ebx\njge 1931 \nmovslq %eax,%rdx\nmov %eax,%ebx\nmov (%r15,%rdx,4),%edx\nlea 0x1(%rbx),%eax\ncmp $0xffffffff,%edx\njne 17ce \nmovslq %eax,%rcx\nshl $0x2,%rcx\nlea (%r15,%rcx,1),%r12\nmov (%r12),%edx\ncmp $0xfffffffe,%edx\nje 1979 \nlea -0x4(%r15,%rcx,1),%rsi\nxor %eax,%eax\nlea 0x2(%rbx),%ecx\nmov %eax,%r8d\nlea (%rcx,%rax,1),%ebx\nadd $0x1,%rax\ncmpl $0xfffffffe,0x4(%rsi,%rax,4)\njne 181f \nxor %r9d,%r9d\nmov %ebx,%eax\nmov %r13,%rsi\nmov %r11d,%ebx\nlea 0x1(%r9),%ecx\nmov %r8d,%r11d\nmov %r10d,%r13d\nmov %eax,%r8d\nmov %ecx,%eax\ncmp $0xffffffff,%edx\nje 1881 \ncmp $0xfffffffe,%edx\nje 1863 \nmovslq 0x54(%rsp),%rcx\nlea 0x1(%rcx),%edi\nmov %edx,(%rsi,%rcx,4)\nmov %edi,0x54(%rsp)\ncmp %r11d,%r9d\njge 193a \nmovslq %eax,%rdx\nmov %eax,%r9d\nmov (%r12,%rdx,4),%edx\nlea 0x1(%r9),%ecx\nmov %ecx,%eax\ncmp $0xffffffff,%edx\njne 184f \nmovslq %ecx,%rax\nshl $0x2,%rax\nlea (%r12,%rax,1),%rdi\ncmpl $0xfffffffe,(%rdi)\nje 1985 \nlea -0x4(%r12,%rax,1),%rdx\nmov $0x1,%eax\nmov %eax,%r9d\nlea (%rcx,%rax,1),%r10d\nadd $0x1,%rax\ncmpl $0xfffffffe,(%rdx,%rax,4)\njne 189f \nmov 0x10(%rsp),%rdx\nmov %r9d,%ecx\nmov %r8d,0x4c(%rsp)\nmov %rsi,0x40(%rsp)\ncallq 13f0 \nmov 0x40(%rsp),%rsi\nmov 0x4c(%rsp),%r8d\nlea 0x1(%r10),%eax\nmov %r10d,%r9d\njmp 1863 \nnopw 0x0(%rax,%rax,1)\nmov 0x8(%rsp),%r14d\nmov 0x18(%rsp),%r8\nmov 0x28(%rsp),%r15d\nlea 0x1(%r14),%r10d\njmpq 153c \nmov 0x38(%rsp),%r14d\nmov 0x20(%rsp),%r8\nmov 0x2c(%rsp),%r15d\nlea 0x1(%r14),%eax\nmov %r14d,%r10d\njmpq 1658 \nmov 0x48(%rsp),%r15d\nmov %r13,%r9\nmov 0x3c(%rsp),%r8d\nmov 0x30(%rsp),%r13\nlea 0x1(%r15),%eax\nmov %r15d,%r10d\njmpq 16e5 \nlea 0x1(%r10),%eax\njmpq 176e \nmov %ebx,%r11d\nmov %r13d,%r10d\nmov %r8d,%ebx\nmov %rsi,%r13\nlea 0x1(%r8),%eax\njmpq 17e4 \nlea 0x2(%r10),%edx\nmov %eax,%r10d\nmov %edx,%eax\njmpq 1658 \nlea 0x2(%r10),%edx\nmov %eax,%r10d\nmov %edx,%eax\njmpq 16e5 \nlea 0x2(%r10),%edx\nmov %eax,%r10d\nmov %edx,%eax\njmpq 176e \nlea 0x2(%rbx),%edx\nmov %eax,%ebx\nmov %edx,%eax\njmpq 17e4 \nmov %ecx,%r10d\nxor %r9d,%r9d\njmpq 18b0 \ncallq 1090 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov r15d, esi\npush r14\npush r13\nmov r13, rdi\nmov edi, 190h; size\npush r12\npush rbp\nxor ebp, ebp\npush rbx\nmov rbx, rdx\nmov r14, rbx\nsub rsp, 88h\nmov rax, fs:28h\nmov [rsp+0B8h+var_40], rax\nxor eax, eax\ncall _malloc\nmov [rsp+0B8h+var_44], 0\nmov r11, rax\ntest r15d, r15d\njle loc_1B19\nloc_17D1:\nmovsxd rax, ebp\nshl rax, 2\nlea rsi, [r13+rax+0]\nmov edx, [rsi]\ncmp edx, 0FFFFFFFFh\njz loc_18CF\ncmp edx, 0FFFFFFFEh\njz short loc_17FD\nmovsxd rax, [rsp+0B8h+var_44]\nlea ecx, [rax+1]\nmov [r11+rax*4], edx\nmov [rsp+0B8h+var_44], ecx\nloc_17FD:\nadd ebp, 1\ncmp r15d, ebp\njg short loc_17D1\nmovsxd r12, [rsp+0B8h+var_44]\nmov edi, 320h; size\nmov [rsp+0B8h+ptr], r11\nmov rbx, r14\ncall _malloc\nmov dword ptr [r14], 0\nmov r11, [rsp+0B8h+ptr]\ntest r12d, r12d\nmov rbp, rax\njle short loc_189E\nmov rdi, r11\nlea r9, [r11+r12*4]\nxor r8d, r8d\nnop word ptr [rax+rax+00h]\nloc_1840:\nmovsxd rsi, r8d\nmov edx, [rdi]\nlea rcx, [rbp+rsi*8+0]\ntest r8d, r8d\njle short loc_1880\nloc_184F:\nmov rax, rbp\njmp short loc_1861\nloc_1858:\nadd rax, 8\ncmp rax, rcx\njz short loc_1880\nloc_1861:\ncmp [rax], edx\njnz short loc_1858\nadd rdi, 4\nadd dword ptr [rax+4], 1\ncmp rdi, r9\njz short loc_189E\nmov edx, [rdi]\njmp short loc_184F\nloc_1880:\nlea rax, [rbp+rsi*8+0]\nadd r8d, 1\nadd rdi, 4\nmov [rax], edx\nmov dword ptr [rax+4], 1\nmov [rbx], r8d\ncmp rdi, r9\njnz short loc_1840\nloc_189E:\nmov rdi, r11; ptr\ncall _free\nmov rax, [rsp+0B8h+var_40]\nsub rax, fs:28h\njnz loc_1C0E\nadd rsp, 88h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_18CF:\nlea rcx, [r13+rax+4]\nxor eax, eax\nmov edx, [rcx]\ncmp edx, 0FFFFFFFEh\njz loc_1C02\nnop dword ptr [rax+00000000h]\nloc_18E8:\nmov rbx, rax\nlea rax, [rax+1]\ncmp dword ptr [rsi+rbx*4+8], 0FFFFFFFEh\njnz short loc_18E8\nmov rsi, r13\nmov r9d, ebx\nmov r13d, ebp\nxor eax, eax\nmov rdi, rbx\nmov ebp, r15d\ncmp edx, 0FFFFFFFFh\njz short loc_193D\nloc_190C:\ncmp edx, 0FFFFFFFEh\njz short loc_1922\nmovsxd r8, [rsp+0B8h+var_44]\nlea ebx, [r8+1]\nmov [r11+r8*4], edx\nmov [rsp+0B8h+var_44], ebx\nloc_1922:\nmov r8d, eax\nloc_1925:\nlea eax, [r8+1]\ncmp r8d, r9d\njge loc_1ADE\nmovsxd rdx, eax\nmov edx, [rcx+rdx*4]\ncmp edx, 0FFFFFFFFh\njnz short loc_190C\nloc_193D:\nlea r8d, [rax+1]\nmovsxd rbx, r8d\nshl rbx, 2\nlea r15, [rcx+rbx]\nmov edx, [r15]\ncmp edx, 0FFFFFFFEh\njz short loc_1925\nlea r12, [rcx+rbx-4]\nxor r8d, r8d\nnop dword ptr [rax+00h]\nloc_1960:\nmov rbx, r8\nlea r8, [r8+1]\ncmp dword ptr [r12+rbx*4+8], 0FFFFFFFEh\njnz short loc_1960\nmov [rsp+0B8h+var_A8], rcx\nmov r8, rsi\nxor r12d, r12d\nmov rcx, rbx\nmov [rsp+0B8h+var_9C], r9d\nmov esi, r13d\nmov r9, rdi\nmov edi, ebp\nmov dword ptr [rsp+0B8h+ptr], eax\nmov rbp, r14\nmov r14d, ebx\ncmp edx, 0FFFFFFFFh\njz short loc_19CC\nloc_1999:\ncmp edx, 0FFFFFFFEh\njz short loc_19B0\nmovsxd rax, [rsp+0B8h+var_44]\nlea r10d, [rax+1]\nmov [r11+rax*4], edx\nmov [rsp+0B8h+var_44], r10d\nloc_19B0:\nmov r10d, r12d\nloc_19B3:\nlea r12d, [r10+1]\ncmp r10d, r14d\njge loc_1AF0\nmovsxd rax, r12d\nmov edx, [r15+rax*4]\ncmp edx, 0FFFFFFFFh\njnz short loc_1999\nloc_19CC:\nlea r10d, [r12+1]\nmovsxd rbx, r10d\nshl rbx, 2\nlea rax, [r15+rbx]\nmov edx, [rax]\ncmp edx, 0FFFFFFFEh\njz short loc_19B3\nlea r13, [r15+rbx-4]\nxor r10d, r10d\nnop dword ptr [rax+rax+00h]\nloc_19F0:\nmov rbx, r10\nlea r10, [r10+1]\ncmp dword ptr [r13+rbx*4+8], 0FFFFFFFEh\njnz short loc_19F0\nmov [rsp+0B8h+var_90], esi\nmov r10d, ebx\nmov rsi, rbp\nxor r13d, r13d\nmov [rsp+0B8h+var_88], r9\nmov ebp, r12d\nmov r9d, edi\nmov [rsp+0B8h+var_80], r8\nmov r8, rbx\nmov [rsp+0B8h+var_98], rcx\nmov [rsp+0B8h+var_8C], r14d\ncmp edx, 0FFFFFFFFh\njz short loc_1A5E\nloc_1A2E:\ncmp edx, 0FFFFFFFEh\njz short loc_1A43\nmovsxd rcx, [rsp+0B8h+var_44]\nlea edi, [rcx+1]\nmov [r11+rcx*4], edx\nmov [rsp+0B8h+var_44], edi\nloc_1A43:\nmov ecx, r13d\nloc_1A46:\nlea r13d, [rcx+1]\ncmp ecx, r10d\njge loc_1B3B\nmovsxd rdx, r13d\nmov edx, [rax+rdx*4]\ncmp edx, 0FFFFFFFFh\njnz short loc_1A2E\nloc_1A5E:\nlea ecx, [r13+1]\nmovsxd rdi, ecx\nshl rdi, 2\nlea r12, [rax+rdi]\nmov edx, [r12]\ncmp edx, 0FFFFFFFEh\njz short loc_1A46\nlea rdi, [rax+rdi-4]\nxor ecx, ecx\nnop dword ptr [rax]\nloc_1A80:\nmov rbx, rcx\nlea rcx, [rcx+1]\ncmp dword ptr [rdi+rbx*4+8], 0FFFFFFFEh\njnz short loc_1A80\nmov [rsp+0B8h+var_70], rsi\nmov rdi, r15\nmov r14d, ebx\nmov r15, rax\nmov [rsp+0B8h+var_78], r8\nxor ecx, ecx\nmov r8, rbx\nmov rax, rdi\nloc_1AA9:\ncmp edx, 0FFFFFFFFh\njz loc_1B89\ncmp edx, 0FFFFFFFEh\njz short loc_1AC7\nmovsxd rsi, [rsp+0B8h+var_44]\nlea edi, [rsi+1]\nmov [r11+rsi*4], edx\nmov [rsp+0B8h+var_44], edi\nloc_1AC7:\nmov ebx, ecx\nloc_1AC9:\nlea ecx, [rbx+1]\ncmp ebx, r14d\njge loc_1B69\nmovsxd rdx, ecx\nmov edx, [r12+rdx*4]\njmp short loc_1AA9\nloc_1ADE:\nmov r15d, ebp\nmov ebp, r13d\nmov r13, rsi\nlea ebp, [rbp+rdi+2]\njmp loc_17FD\nloc_1AF0:\nmov eax, dword ptr [rsp+0B8h+ptr]\nmov rbx, rcx\nmov r13d, esi\nmov r14, rbp\nmov rsi, r8\nmov ebp, edi\nmov rcx, [rsp+0B8h+var_A8]\nmov rdi, r9\nlea r8d, [rax+rbx+2]\nmov r9d, [rsp+0B8h+var_9C]\njmp loc_1925\nloc_1B19:\nmov edi, 320h; size\nmov [rsp+0B8h+ptr], rax\ncall _malloc\nmov dword ptr [rbx], 0\nmov r11, [rsp+0B8h+ptr]\nmov rbp, rax\njmp loc_189E\nloc_1B3B:\nmov rbx, r8\nmov r12d, ebp\nmov edi, r9d\nmov rbp, rsi\nmov rcx, [rsp+0B8h+var_98]\nmov r14d, [rsp+0B8h+var_8C]\nlea r10d, [r12+rbx+2]\nmov r8, [rsp+0B8h+var_80]\nmov r9, [rsp+0B8h+var_88]\nmov esi, [rsp+0B8h+var_90]\njmp loc_19B3\nloc_1B69:\nmov rdi, rax\nmov rbx, r8\nmov rax, r15\nmov r8, [rsp+0B8h+var_78]\nmov rsi, [rsp+0B8h+var_70]\nmov r15, rdi\nlea ecx, [r13+rbx+2]\njmp loc_1A46\nloc_1B89:\nadd ecx, 1\nmovsxd rdx, ecx\nmov ebx, ecx\nshl rdx, 2\nlea rdi, [r12+rdx]\ncmp dword ptr [rdi], 0FFFFFFFEh\njz short loc_1C0A\nlea rsi, [r12+rdx-4]\nmov edx, 1\nloc_1BA8:\nmov rbx, rdx\nadd rdx, 1\ncmp dword ptr [rsi+rdx*4], 0FFFFFFFEh\njnz short loc_1BA8\nmov edx, ebx\nadd ebx, ecx\nloc_1BB9:\nlea rsi, [rsp+0B8h+var_44]\nmov ecx, edx\nmov [rsp+0B8h+var_4C], r9d\nmov rdx, rsi\nmov rsi, r11\nmov [rsp+0B8h+var_58], r8\nmov [rsp+0B8h+var_50], r10d\nmov [rsp+0B8h+var_60], rax\nmov [rsp+0B8h+var_68], r11\ncall flatten\nmov r11, [rsp+0B8h+var_68]\nmov rax, [rsp+0B8h+var_60]\nmov r10d, [rsp+0B8h+var_50]\nmov r8, [rsp+0B8h+var_58]\nmov r9d, [rsp+0B8h+var_4C]\njmp loc_1AC9\nloc_1C02:\nadd ebp, 1\njmp loc_17FD\nloc_1C0A:\nxor edx, edx\njmp short loc_1BB9\nloc_1C0E:\ncall ___stack_chk_fail", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, int *a3)\n{\n int v3; // r15d\n int v5; // ebp\n int *v7; // r14\n _DWORD *v8; // rax\n _DWORD *v9; // r11\n __int64 v10; // rax\n __int64 v11; // rsi\n int v12; // edx\n int v13; // ecx\n __int64 v14; // r12\n _DWORD *v15; // rax\n void *v16; // r11\n _DWORD *v17; // rbp\n char *v18; // rdi\n char *v19; // r9\n int v20; // r8d\n int v21; // edx\n _DWORD *v22; // rax\n _DWORD *v23; // rax\n _DWORD *v25; // rcx\n __int64 v26; // rax\n int v27; // edx\n __int64 v28; // rbx\n __int64 v29; // rsi\n int v30; // r9d\n int v31; // r13d\n int v32; // eax\n __int64 v33; // rdi\n int v34; // ebp\n int v35; // ebx\n int v36; // r8d\n __int64 v37; // rbx\n _DWORD *v38; // r15\n int v39; // edx\n __int64 v40; // r12\n __int64 v41; // r8\n __int64 v42; // rbx\n __int64 v43; // r8\n int v44; // r12d\n __int64 v45; // rcx\n int v46; // esi\n __int64 v47; // r9\n int v48; // edi\n int *v49; // rbp\n int v50; // r14d\n int v51; // r10d\n int v52; // r10d\n __int64 v53; // rbx\n _DWORD *v54; // rax\n int v55; // edx\n __int64 v56; // r13\n __int64 v57; // r10\n __int64 v58; // rbx\n int v59; // r10d\n int *v60; // rsi\n int v61; // r13d\n int v62; // ebp\n int v63; // r9d\n __int64 v64; // r8\n int v65; // edi\n int v66; // ecx\n __int64 v67; // rdi\n _DWORD *v68; // r12\n int v69; // edx\n __int64 v70; // rdi\n __int64 v71; // rcx\n __int64 v72; // rbx\n _DWORD *v73; // rdi\n int v74; // r14d\n _DWORD *v75; // r15\n int v76; // ecx\n __int64 v77; // r8\n _DWORD *v78; // rax\n int v79; // edi\n int v80; // ebx\n int v81; // ebp\n int v82; // ebx\n _DWORD *v83; // rax\n int v84; // r12d\n _DWORD *v85; // rdi\n int v86; // ebx\n int v87; // ecx\n __int64 v88; // rdx\n _DWORD *v89; // rdi\n __int64 v90; // rsi\n __int64 v91; // rdx\n unsigned int v92; // ebx\n unsigned int v93; // edx\n char *ptr; // [rsp+8h] [rbp-B0h]\n int ptra; // [rsp+8h] [rbp-B0h]\n void *ptrb; // [rsp+8h] [rbp-B0h]\n _DWORD *v97; // [rsp+10h] [rbp-A8h]\n int v98; // [rsp+1Ch] [rbp-9Ch]\n __int64 v99; // [rsp+20h] [rbp-98h]\n int v100; // [rsp+28h] [rbp-90h]\n int v101; // [rsp+2Ch] [rbp-8Ch]\n __int64 v102; // [rsp+30h] [rbp-88h]\n __int64 v103; // [rsp+38h] [rbp-80h]\n __int64 v104; // [rsp+40h] [rbp-78h]\n int *v105; // [rsp+48h] [rbp-70h]\n _DWORD *v106; // [rsp+50h] [rbp-68h]\n _DWORD *v107; // [rsp+58h] [rbp-60h]\n __int64 v108; // [rsp+60h] [rbp-58h]\n int v109; // [rsp+68h] [rbp-50h]\n int v110; // [rsp+6Ch] [rbp-4Ch]\n int v111; // [rsp+74h] [rbp-44h] BYREF\n unsigned __int64 v112; // [rsp+78h] [rbp-40h]\n\n v3 = a2;\n v5 = 0;\n v7 = a3;\n v112 = __readfsqword(0x28u);\n v8 = malloc(0x190uLL);\n v111 = 0;\n v9 = v8;\n if ( a2 <= 0 )\n {\n ptrb = v8;\n v83 = malloc(0x320uLL);\n *a3 = 0;\n v16 = ptrb;\n v17 = v83;\n }\n else\n {\n do\n {\n v10 = 4LL * v5;\n v11 = a1 + v10;\n v12 = *(_DWORD *)(a1 + v10);\n if ( v12 == -1 )\n {\n v25 = (_DWORD *)(a1 + v10 + 4);\n v26 = 0LL;\n v27 = *v25;\n if ( *v25 == -2 )\n {\n ++v5;\n }\n else\n {\n do\n v28 = v26++;\n while ( *(_DWORD *)(v11 + 4 * v28 + 8) != -2 );\n v29 = a1;\n v30 = v28;\n v31 = v5;\n v32 = 0;\n v33 = v28;\n v34 = v3;\n if ( v27 != -1 )\n {\nLABEL_19:\n if ( v27 != -2 )\n {\n v35 = v111 + 1;\n v9[v111] = v27;\n v111 = v35;\n }\n v36 = v32;\n goto LABEL_22;\n }\n while ( 1 )\n {\n v36 = v32 + 1;\n v37 = v32 + 1;\n v38 = &v25[v37];\n v39 = v25[v37];\n if ( v39 != -2 )\n {\n v40 = (__int64)&v25[v37 - 1];\n v41 = 0LL;\n do\n v42 = v41++;\n while ( *(_DWORD *)(v40 + 4 * v42 + 8) != -2 );\n v97 = v25;\n v43 = v29;\n v44 = 0;\n v45 = v42;\n v98 = v30;\n v46 = v31;\n v47 = v33;\n v48 = v34;\n ptra = v32;\n v49 = v7;\n v50 = v42;\n if ( v39 != -1 )\n {\nLABEL_28:\n if ( v39 != -2 )\n {\n v51 = v111 + 1;\n v9[v111] = v39;\n v111 = v51;\n }\n v52 = v44;\n goto LABEL_31;\n }\n while ( 1 )\n {\n v52 = v44 + 1;\n v53 = v44 + 1;\n v54 = &v38[v53];\n v55 = v38[v53];\n if ( v55 != -2 )\n {\n v56 = (__int64)&v38[v53 - 1];\n v57 = 0LL;\n do\n v58 = v57++;\n while ( *(_DWORD *)(v56 + 4 * v58 + 8) != -2 );\n v100 = v46;\n v59 = v58;\n v60 = v49;\n v61 = 0;\n v102 = v47;\n v62 = v44;\n v63 = v48;\n v103 = v43;\n v64 = v58;\n v99 = v45;\n v101 = v50;\n if ( v55 != -1 )\n {\nLABEL_37:\n if ( v55 != -2 )\n {\n v65 = v111 + 1;\n v9[v111] = v55;\n v111 = v65;\n }\n v66 = v61;\n goto LABEL_40;\n }\n while ( 1 )\n {\n v66 = v61 + 1;\n v67 = v61 + 1;\n v68 = &v54[v67];\n v69 = v54[v67];\n if ( v69 != -2 )\n {\n v70 = (__int64)&v54[v67 - 1];\n v71 = 0LL;\n do\n v72 = v71++;\n while ( *(_DWORD *)(v70 + 4 * v72 + 8) != -2 );\n v105 = v60;\n v73 = v38;\n v74 = v72;\n v75 = v54;\n v104 = v64;\n v76 = 0;\n v77 = v72;\n v78 = v73;\n while ( 1 )\n {\n if ( v69 == -1 )\n {\n v87 = v76 + 1;\n v80 = v87;\n v88 = v87;\n v89 = &v68[v88];\n if ( v68[v88] == -2 )\n {\n v93 = 0;\n }\n else\n {\n v90 = (__int64)&v68[v88 - 1];\n v91 = 1LL;\n do\n v92 = v91++;\n while ( *(_DWORD *)(v90 + 4 * v91) != -2 );\n v93 = v92;\n v80 = v87 + v92;\n }\n v110 = v63;\n v108 = v77;\n v109 = v59;\n v107 = v78;\n v106 = v9;\n flatten(v89, v9, &v111, v93);\n v9 = v106;\n v78 = v107;\n v59 = v109;\n v77 = v108;\n v63 = v110;\n }\n else\n {\n if ( v69 != -2 )\n {\n v79 = v111 + 1;\n v9[v111] = v69;\n v111 = v79;\n }\n v80 = v76;\n }\n v76 = v80 + 1;\n if ( v80 >= v74 )\n break;\n v69 = v68[v76];\n }\n v85 = v78;\n v86 = v77;\n v54 = v75;\n v64 = v104;\n v60 = v105;\n v38 = v85;\n v66 = v61 + v86 + 2;\n }\nLABEL_40:\n v61 = v66 + 1;\n if ( v66 >= v59 )\n break;\n v55 = v54[v61];\n if ( v55 != -1 )\n goto LABEL_37;\n }\n v84 = v62;\n v48 = v63;\n v49 = v60;\n v45 = v99;\n v50 = v101;\n v52 = v84 + v64 + 2;\n v43 = v103;\n v47 = v102;\n v46 = v100;\n }\nLABEL_31:\n v44 = v52 + 1;\n if ( v52 >= v50 )\n break;\n v39 = v38[v44];\n if ( v39 != -1 )\n goto LABEL_28;\n }\n v82 = v45;\n v31 = v46;\n v7 = v49;\n v29 = v43;\n v34 = v48;\n v25 = v97;\n v33 = v47;\n v36 = ptra + v82 + 2;\n v30 = v98;\n }\nLABEL_22:\n v32 = v36 + 1;\n if ( v36 >= v30 )\n break;\n v27 = v25[v32];\n if ( v27 != -1 )\n goto LABEL_19;\n }\n v3 = v34;\n v81 = v31;\n a1 = v29;\n v5 = v81 + v33 + 2;\n }\n }\n else if ( v12 != -2 )\n {\n v13 = v111 + 1;\n v9[v111] = v12;\n v111 = v13;\n }\n ++v5;\n }\n while ( v3 > v5 );\n v14 = v111;\n ptr = (char *)v9;\n v15 = malloc(0x320uLL);\n *v7 = 0;\n v16 = ptr;\n v17 = v15;\n if ( (int)v14 > 0 )\n {\n v18 = ptr;\n v19 = &ptr[4 * v14];\n v20 = 0;\n while ( 1 )\n {\n v21 = *(_DWORD *)v18;\n if ( v20 > 0 )\n break;\nLABEL_14:\n v23 = &v17[2 * v20++];\n v18 += 4;\n *v23 = v21;\n v23[1] = 1;\n *v7 = v20;\n if ( v18 == v19 )\n goto LABEL_15;\n }\n while ( 1 )\n {\n v22 = v17;\n while ( *v22 != v21 )\n {\n v22 += 2;\n if ( v22 == &v17[2 * v20] )\n goto LABEL_14;\n }\n v18 += 4;\n ++v22[1];\n if ( v18 == v19 )\n break;\n v21 = *(_DWORD *)v18;\n }\n }\n }\nLABEL_15:\n free(v16);\n return v17;\n}", + "ida_strip_asm": "sub_1780:\nendbr64\npush r15\nmov r15d, esi\npush r14\npush r13\nmov r13, rdi\nmov edi, 190h; size\npush r12\npush rbp\nxor ebp, ebp\npush rbx\nmov rbx, rdx\nmov r14, rbx\nsub rsp, 88h\nmov rax, fs:28h\nmov [rsp+0B8h+var_40], rax\nxor eax, eax\ncall _malloc\nmov [rsp+0B8h+var_44], 0\nmov r11, rax\ntest r15d, r15d\njle loc_1B19\nloc_17D1:\nmovsxd rax, ebp\nshl rax, 2\nlea rsi, [r13+rax+0]\nmov edx, [rsi]\ncmp edx, 0FFFFFFFFh\njz loc_18CF\ncmp edx, 0FFFFFFFEh\njz short loc_17FD\nmovsxd rax, [rsp+0B8h+var_44]\nlea ecx, [rax+1]\nmov [r11+rax*4], edx\nmov [rsp+0B8h+var_44], ecx\nloc_17FD:\nadd ebp, 1\ncmp r15d, ebp\njg short loc_17D1\nmovsxd r12, [rsp+0B8h+var_44]\nmov edi, 320h; size\nmov [rsp+0B8h+ptr], r11\nmov rbx, r14\ncall _malloc\nmov dword ptr [r14], 0\nmov r11, [rsp+0B8h+ptr]\ntest r12d, r12d\nmov rbp, rax\njle short loc_189E\nmov rdi, r11\nlea r9, [r11+r12*4]\nxor r8d, r8d\nnop word ptr [rax+rax+00h]\nloc_1840:\nmovsxd rsi, r8d\nmov edx, [rdi]\nlea rcx, [rbp+rsi*8+0]\ntest r8d, r8d\njle short loc_1880\nloc_184F:\nmov rax, rbp\njmp short loc_1861\nloc_1858:\nadd rax, 8\ncmp rax, rcx\njz short loc_1880\nloc_1861:\ncmp [rax], edx\njnz short loc_1858\nadd rdi, 4\nadd dword ptr [rax+4], 1\ncmp rdi, r9\njz short loc_189E\nmov edx, [rdi]\njmp short loc_184F\nloc_1880:\nlea rax, [rbp+rsi*8+0]\nadd r8d, 1\nadd rdi, 4\nmov [rax], edx\nmov dword ptr [rax+4], 1\nmov [rbx], r8d\ncmp rdi, r9\njnz short loc_1840\nloc_189E:\nmov rdi, r11; ptr\ncall _free\nmov rax, [rsp+0B8h+var_40]\nsub rax, fs:28h\njnz loc_1C0E\nadd rsp, 88h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_18CF:\nlea rcx, [r13+rax+4]\nxor eax, eax\nmov edx, [rcx]\ncmp edx, 0FFFFFFFEh\njz loc_1C02\nnop dword ptr [rax+00000000h]\nloc_18E8:\nmov rbx, rax\nlea rax, [rax+1]\ncmp dword ptr [rsi+rbx*4+8], 0FFFFFFFEh\njnz short loc_18E8\nmov rsi, r13\nmov r9d, ebx\nmov r13d, ebp\nxor eax, eax\nmov rdi, rbx\nmov ebp, r15d\ncmp edx, 0FFFFFFFFh\njz short loc_193D\nloc_190C:\ncmp edx, 0FFFFFFFEh\njz short loc_1922\nmovsxd r8, [rsp+0B8h+var_44]\nlea ebx, [r8+1]\nmov [r11+r8*4], edx\nmov [rsp+0B8h+var_44], ebx\nloc_1922:\nmov r8d, eax\nloc_1925:\nlea eax, [r8+1]\ncmp r8d, r9d\njge loc_1ADE\nmovsxd rdx, eax\nmov edx, [rcx+rdx*4]\ncmp edx, 0FFFFFFFFh\njnz short loc_190C\nloc_193D:\nlea r8d, [rax+1]\nmovsxd rbx, r8d\nshl rbx, 2\nlea r15, [rcx+rbx]\nmov edx, [r15]\ncmp edx, 0FFFFFFFEh\njz short loc_1925\nlea r12, [rcx+rbx-4]\nxor r8d, r8d\nnop dword ptr [rax+00h]\nloc_1960:\nmov rbx, r8\nlea r8, [r8+1]\ncmp dword ptr [r12+rbx*4+8], 0FFFFFFFEh\njnz short loc_1960\nmov [rsp+0B8h+var_A8], rcx\nmov r8, rsi\nxor r12d, r12d\nmov rcx, rbx\nmov [rsp+0B8h+var_9C], r9d\nmov esi, r13d\nmov r9, rdi\nmov edi, ebp\nmov dword ptr [rsp+0B8h+ptr], eax\nmov rbp, r14\nmov r14d, ebx\ncmp edx, 0FFFFFFFFh\njz short loc_19CC\nloc_1999:\ncmp edx, 0FFFFFFFEh\njz short loc_19B0\nmovsxd rax, [rsp+0B8h+var_44]\nlea r10d, [rax+1]\nmov [r11+rax*4], edx\nmov [rsp+0B8h+var_44], r10d\nloc_19B0:\nmov r10d, r12d\nloc_19B3:\nlea r12d, [r10+1]\ncmp r10d, r14d\njge loc_1AF0\nmovsxd rax, r12d\nmov edx, [r15+rax*4]\ncmp edx, 0FFFFFFFFh\njnz short loc_1999\nloc_19CC:\nlea r10d, [r12+1]\nmovsxd rbx, r10d\nshl rbx, 2\nlea rax, [r15+rbx]\nmov edx, [rax]\ncmp edx, 0FFFFFFFEh\njz short loc_19B3\nlea r13, [r15+rbx-4]\nxor r10d, r10d\nnop dword ptr [rax+rax+00h]\nloc_19F0:\nmov rbx, r10\nlea r10, [r10+1]\ncmp dword ptr [r13+rbx*4+8], 0FFFFFFFEh\njnz short loc_19F0\nmov [rsp+0B8h+var_90], esi\nmov r10d, ebx\nmov rsi, rbp\nxor r13d, r13d\nmov [rsp+0B8h+var_88], r9\nmov ebp, r12d\nmov r9d, edi\nmov [rsp+0B8h+var_80], r8\nmov r8, rbx\nmov [rsp+0B8h+var_98], rcx\nmov [rsp+0B8h+var_8C], r14d\ncmp edx, 0FFFFFFFFh\njz short loc_1A5E\nloc_1A2E:\ncmp edx, 0FFFFFFFEh\njz short loc_1A43\nmovsxd rcx, [rsp+0B8h+var_44]\nlea edi, [rcx+1]\nmov [r11+rcx*4], edx\nmov [rsp+0B8h+var_44], edi\nloc_1A43:\nmov ecx, r13d\nloc_1A46:\nlea r13d, [rcx+1]\ncmp ecx, r10d\njge loc_1B3B\nmovsxd rdx, r13d\nmov edx, [rax+rdx*4]\ncmp edx, 0FFFFFFFFh\njnz short loc_1A2E\nloc_1A5E:\nlea ecx, [r13+1]\nmovsxd rdi, ecx\nshl rdi, 2\nlea r12, [rax+rdi]\nmov edx, [r12]\ncmp edx, 0FFFFFFFEh\njz short loc_1A46\nlea rdi, [rax+rdi-4]\nxor ecx, ecx\nnop dword ptr [rax]\nloc_1A80:\nmov rbx, rcx\nlea rcx, [rcx+1]\ncmp dword ptr [rdi+rbx*4+8], 0FFFFFFFEh\njnz short loc_1A80\nmov [rsp+0B8h+var_70], rsi\nmov rdi, r15\nmov r14d, ebx\nmov r15, rax\nmov [rsp+0B8h+var_78], r8\nxor ecx, ecx\nmov r8, rbx\nmov rax, rdi\nloc_1AA9:\ncmp edx, 0FFFFFFFFh\njz loc_1B89\ncmp edx, 0FFFFFFFEh\njz short loc_1AC7\nmovsxd rsi, [rsp+0B8h+var_44]\nlea edi, [rsi+1]\nmov [r11+rsi*4], edx\nmov [rsp+0B8h+var_44], edi\nloc_1AC7:\nmov ebx, ecx\nloc_1AC9:\nlea ecx, [rbx+1]\ncmp ebx, r14d\njge loc_1B69\nmovsxd rdx, ecx\nmov edx, [r12+rdx*4]\njmp short loc_1AA9\nloc_1ADE:\nmov r15d, ebp\nmov ebp, r13d\nmov r13, rsi\nlea ebp, [rbp+rdi+2]\njmp loc_17FD\nloc_1AF0:\nmov eax, dword ptr [rsp+0B8h+ptr]\nmov rbx, rcx\nmov r13d, esi\nmov r14, rbp\nmov rsi, r8\nmov ebp, edi\nmov rcx, [rsp+0B8h+var_A8]\nmov rdi, r9\nlea r8d, [rax+rbx+2]\nmov r9d, [rsp+0B8h+var_9C]\njmp loc_1925\nloc_1B19:\nmov edi, 320h; size\nmov [rsp+0B8h+ptr], rax\ncall _malloc\nmov dword ptr [rbx], 0\nmov r11, [rsp+0B8h+ptr]\nmov rbp, rax\njmp loc_189E\nloc_1B3B:\nmov rbx, r8\nmov r12d, ebp\nmov edi, r9d\nmov rbp, rsi\nmov rcx, [rsp+0B8h+var_98]\nmov r14d, [rsp+0B8h+var_8C]\nlea r10d, [r12+rbx+2]\nmov r8, [rsp+0B8h+var_80]\nmov r9, [rsp+0B8h+var_88]\nmov esi, [rsp+0B8h+var_90]\njmp loc_19B3\nloc_1B69:\nmov rdi, rax\nmov rbx, r8\nmov rax, r15\nmov r8, [rsp+0B8h+var_78]\nmov rsi, [rsp+0B8h+var_70]\nmov r15, rdi\nlea ecx, [r13+rbx+2]\njmp loc_1A46\nloc_1B89:\nadd ecx, 1\nmovsxd rdx, ecx\nmov ebx, ecx\nshl rdx, 2\nlea rdi, [r12+rdx]\ncmp dword ptr [rdi], 0FFFFFFFEh\njz short loc_1C0A\nlea rsi, [r12+rdx-4]\nmov edx, 1\nloc_1BA8:\nmov rbx, rdx\nadd rdx, 1\ncmp dword ptr [rsi+rdx*4], 0FFFFFFFEh\njnz short loc_1BA8\nmov edx, ebx\nadd ebx, ecx\nloc_1BB9:\nlea rsi, [rsp+0B8h+var_44]\nmov ecx, edx\nmov [rsp+0B8h+var_4C], r9d\nmov rdx, rsi\nmov rsi, r11\nmov [rsp+0B8h+var_58], r8\nmov [rsp+0B8h+var_50], r10d\nmov [rsp+0B8h+var_60], rax\nmov [rsp+0B8h+var_68], r11\ncall sub_13E0\nmov r11, [rsp+0B8h+var_68]\nmov rax, [rsp+0B8h+var_60]\nmov r10d, [rsp+0B8h+var_50]\nmov r8, [rsp+0B8h+var_58]\nmov r9d, [rsp+0B8h+var_4C]\njmp loc_1AC9\nloc_1C02:\nadd ebp, 1\njmp loc_17FD\nloc_1C0A:\nxor edx, edx\njmp short loc_1BB9\nloc_1C0E:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1780(__int64 a1, int a2, int *a3)\n{\n int v3; // r15d\n int v5; // ebp\n int *v7; // r14\n _DWORD *v8; // rax\n _DWORD *v9; // r11\n __int64 v10; // rax\n __int64 v11; // rsi\n int v12; // edx\n int v13; // ecx\n __int64 v14; // r12\n _DWORD *v15; // rax\n void *v16; // r11\n _DWORD *v17; // rbp\n char *v18; // rdi\n char *v19; // r9\n int v20; // r8d\n int v21; // edx\n _DWORD *v22; // rax\n _DWORD *v23; // rax\n _DWORD *v25; // rcx\n __int64 v26; // rax\n int v27; // edx\n __int64 v28; // rbx\n __int64 v29; // rsi\n int v30; // r9d\n int v31; // r13d\n int v32; // eax\n __int64 v33; // rdi\n int v34; // ebp\n int v35; // ebx\n int v36; // r8d\n __int64 v37; // rbx\n _DWORD *v38; // r15\n int v39; // edx\n __int64 v40; // r12\n __int64 v41; // r8\n __int64 v42; // rbx\n __int64 v43; // r8\n int v44; // r12d\n __int64 v45; // rcx\n int v46; // esi\n __int64 v47; // r9\n int v48; // edi\n int *v49; // rbp\n int v50; // r14d\n int v51; // r10d\n int v52; // r10d\n __int64 v53; // rbx\n _DWORD *v54; // rax\n int v55; // edx\n __int64 v56; // r13\n __int64 v57; // r10\n __int64 v58; // rbx\n int v59; // r10d\n int *v60; // rsi\n int v61; // r13d\n int v62; // ebp\n int v63; // r9d\n __int64 v64; // r8\n int v65; // edi\n int v66; // ecx\n __int64 v67; // rdi\n _DWORD *v68; // r12\n int v69; // edx\n __int64 v70; // rdi\n __int64 v71; // rcx\n __int64 v72; // rbx\n _DWORD *v73; // rdi\n int v74; // r14d\n _DWORD *v75; // r15\n int v76; // ecx\n __int64 v77; // r8\n _DWORD *v78; // rax\n int v79; // edi\n int v80; // ebx\n int v81; // ebp\n int v82; // ebx\n _DWORD *v83; // rax\n int v84; // r12d\n _DWORD *v85; // rdi\n int v86; // ebx\n int v87; // ecx\n __int64 v88; // rdx\n _DWORD *v89; // rdi\n __int64 v90; // rsi\n __int64 v91; // rdx\n unsigned int v92; // ebx\n unsigned int v93; // edx\n char *ptr; // [rsp+8h] [rbp-B0h]\n int ptra; // [rsp+8h] [rbp-B0h]\n void *ptrb; // [rsp+8h] [rbp-B0h]\n _DWORD *v97; // [rsp+10h] [rbp-A8h]\n int v98; // [rsp+1Ch] [rbp-9Ch]\n __int64 v99; // [rsp+20h] [rbp-98h]\n int v100; // [rsp+28h] [rbp-90h]\n int v101; // [rsp+2Ch] [rbp-8Ch]\n __int64 v102; // [rsp+30h] [rbp-88h]\n __int64 v103; // [rsp+38h] [rbp-80h]\n __int64 v104; // [rsp+40h] [rbp-78h]\n int *v105; // [rsp+48h] [rbp-70h]\n _DWORD *v106; // [rsp+50h] [rbp-68h]\n _DWORD *v107; // [rsp+58h] [rbp-60h]\n __int64 v108; // [rsp+60h] [rbp-58h]\n int v109; // [rsp+68h] [rbp-50h]\n int v110; // [rsp+6Ch] [rbp-4Ch]\n int v111; // [rsp+74h] [rbp-44h] BYREF\n unsigned __int64 v112; // [rsp+78h] [rbp-40h]\n\n v3 = a2;\n v5 = 0;\n v7 = a3;\n v112 = __readfsqword(0x28u);\n v8 = malloc(0x190uLL);\n v111 = 0;\n v9 = v8;\n if ( a2 <= 0 )\n {\n ptrb = v8;\n v83 = malloc(0x320uLL);\n *a3 = 0;\n v16 = ptrb;\n v17 = v83;\n }\n else\n {\n do\n {\n v10 = 4LL * v5;\n v11 = a1 + v10;\n v12 = *(_DWORD *)(a1 + v10);\n if ( v12 == -1 )\n {\n v25 = (_DWORD *)(a1 + v10 + 4);\n v26 = 0LL;\n v27 = *v25;\n if ( *v25 == -2 )\n {\n ++v5;\n }\n else\n {\n do\n v28 = v26++;\n while ( *(_DWORD *)(v11 + 4 * v28 + 8) != -2 );\n v29 = a1;\n v30 = v28;\n v31 = v5;\n v32 = 0;\n v33 = v28;\n v34 = v3;\n if ( v27 != -1 )\n {\nLABEL_19:\n if ( v27 != -2 )\n {\n v35 = v111 + 1;\n v9[v111] = v27;\n v111 = v35;\n }\n v36 = v32;\n goto LABEL_22;\n }\n while ( 1 )\n {\n v36 = v32 + 1;\n v37 = v32 + 1;\n v38 = &v25[v37];\n v39 = v25[v37];\n if ( v39 != -2 )\n {\n v40 = (__int64)&v25[v37 - 1];\n v41 = 0LL;\n do\n v42 = v41++;\n while ( *(_DWORD *)(v40 + 4 * v42 + 8) != -2 );\n v97 = v25;\n v43 = v29;\n v44 = 0;\n v45 = v42;\n v98 = v30;\n v46 = v31;\n v47 = v33;\n v48 = v34;\n ptra = v32;\n v49 = v7;\n v50 = v42;\n if ( v39 != -1 )\n {\nLABEL_28:\n if ( v39 != -2 )\n {\n v51 = v111 + 1;\n v9[v111] = v39;\n v111 = v51;\n }\n v52 = v44;\n goto LABEL_31;\n }\n while ( 1 )\n {\n v52 = v44 + 1;\n v53 = v44 + 1;\n v54 = &v38[v53];\n v55 = v38[v53];\n if ( v55 != -2 )\n {\n v56 = (__int64)&v38[v53 - 1];\n v57 = 0LL;\n do\n v58 = v57++;\n while ( *(_DWORD *)(v56 + 4 * v58 + 8) != -2 );\n v100 = v46;\n v59 = v58;\n v60 = v49;\n v61 = 0;\n v102 = v47;\n v62 = v44;\n v63 = v48;\n v103 = v43;\n v64 = v58;\n v99 = v45;\n v101 = v50;\n if ( v55 != -1 )\n {\nLABEL_37:\n if ( v55 != -2 )\n {\n v65 = v111 + 1;\n v9[v111] = v55;\n v111 = v65;\n }\n v66 = v61;\n goto LABEL_40;\n }\n while ( 1 )\n {\n v66 = v61 + 1;\n v67 = v61 + 1;\n v68 = &v54[v67];\n v69 = v54[v67];\n if ( v69 != -2 )\n {\n v70 = (__int64)&v54[v67 - 1];\n v71 = 0LL;\n do\n v72 = v71++;\n while ( *(_DWORD *)(v70 + 4 * v72 + 8) != -2 );\n v105 = v60;\n v73 = v38;\n v74 = v72;\n v75 = v54;\n v104 = v64;\n v76 = 0;\n v77 = v72;\n v78 = v73;\n while ( 1 )\n {\n if ( v69 == -1 )\n {\n v87 = v76 + 1;\n v80 = v87;\n v88 = v87;\n v89 = &v68[v88];\n if ( v68[v88] == -2 )\n {\n v93 = 0;\n }\n else\n {\n v90 = (__int64)&v68[v88 - 1];\n v91 = 1LL;\n do\n v92 = v91++;\n while ( *(_DWORD *)(v90 + 4 * v91) != -2 );\n v93 = v92;\n v80 = v87 + v92;\n }\n v110 = v63;\n v108 = v77;\n v109 = v59;\n v107 = v78;\n v106 = v9;\n sub_13E0(v89, v9, &v111, v93);\n v9 = v106;\n v78 = v107;\n v59 = v109;\n v77 = v108;\n v63 = v110;\n }\n else\n {\n if ( v69 != -2 )\n {\n v79 = v111 + 1;\n v9[v111] = v69;\n v111 = v79;\n }\n v80 = v76;\n }\n v76 = v80 + 1;\n if ( v80 >= v74 )\n break;\n v69 = v68[v76];\n }\n v85 = v78;\n v86 = v77;\n v54 = v75;\n v64 = v104;\n v60 = v105;\n v38 = v85;\n v66 = v61 + v86 + 2;\n }\nLABEL_40:\n v61 = v66 + 1;\n if ( v66 >= v59 )\n break;\n v55 = v54[v61];\n if ( v55 != -1 )\n goto LABEL_37;\n }\n v84 = v62;\n v48 = v63;\n v49 = v60;\n v45 = v99;\n v50 = v101;\n v52 = v84 + v64 + 2;\n v43 = v103;\n v47 = v102;\n v46 = v100;\n }\nLABEL_31:\n v44 = v52 + 1;\n if ( v52 >= v50 )\n break;\n v39 = v38[v44];\n if ( v39 != -1 )\n goto LABEL_28;\n }\n v82 = v45;\n v31 = v46;\n v7 = v49;\n v29 = v43;\n v34 = v48;\n v25 = v97;\n v33 = v47;\n v36 = ptra + v82 + 2;\n v30 = v98;\n }\nLABEL_22:\n v32 = v36 + 1;\n if ( v36 >= v30 )\n break;\n v27 = v25[v32];\n if ( v27 != -1 )\n goto LABEL_19;\n }\n v3 = v34;\n v81 = v31;\n a1 = v29;\n v5 = v81 + v33 + 2;\n }\n }\n else if ( v12 != -2 )\n {\n v13 = v111 + 1;\n v9[v111] = v12;\n v111 = v13;\n }\n ++v5;\n }\n while ( v3 > v5 );\n v14 = v111;\n ptr = (char *)v9;\n v15 = malloc(0x320uLL);\n *v7 = 0;\n v16 = ptr;\n v17 = v15;\n if ( (int)v14 > 0 )\n {\n v18 = ptr;\n v19 = &ptr[4 * v14];\n v20 = 0;\n while ( 1 )\n {\n v21 = *(_DWORD *)v18;\n if ( v20 > 0 )\n break;\nLABEL_14:\n v23 = &v17[2 * v20++];\n v18 += 4;\n *v23 = v21;\n v23[1] = 1;\n *v7 = v20;\n if ( v18 == v19 )\n goto LABEL_15;\n }\n while ( 1 )\n {\n v22 = v17;\n while ( *v22 != v21 )\n {\n v22 += 2;\n if ( v22 == &v17[2 * v20] )\n goto LABEL_14;\n }\n v18 += 4;\n ++v22[1];\n if ( v18 == v19 )\n break;\n v21 = *(_DWORD *)v18;\n }\n }\n }\nLABEL_15:\n free(v16);\n return v17;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1780(long long a1, int a2, int *a3) {\n int v3;\n int v5;\n int *v7;\n uint32_t *v8;\n uint32_t *v9;\n long long v10;\n long long v11;\n int v12;\n int v13;\n long long v14;\n uint32_t *v15;\n void *v16;\n uint32_t *v17;\n char *v18;\n char *v19;\n int v20;\n int v21;\n uint32_t *v22;\n uint32_t *v23;\n uint32_t *v25;\n long long v26;\n int v27;\n long long v28;\n long long v29;\n int v30;\n int v31;\n int v32;\n long long v33;\n int v34;\n int v35;\n int v36;\n long long v37;\n uint32_t *v38;\n int v39;\n long long v40;\n long long v41;\n long long v42;\n long long v43;\n int v44;\n long long v45;\n int v46;\n long long v47;\n int v48;\n int *v49;\n int v50;\n int v51;\n int v52;\n long long v53;\n uint32_t *v54;\n int v55;\n long long v56;\n long long v57;\n long long v58;\n int v59;\n int *v60;\n int v61;\n int v62;\n int v63;\n long long v64;\n int v65;\n int v66;\n long long v67;\n uint32_t *v68;\n int v69;\n long long v70;\n long long v71;\n long long v72;\n uint32_t *v73;\n int v74;\n uint32_t *v75;\n int v76;\n long long v77;\n uint32_t *v78;\n int v79;\n int v80;\n int v81;\n int v82;\n uint32_t *v83;\n int v84;\n uint32_t *v85;\n int v86;\n int v87;\n long long v88;\n uint32_t *v89;\n long long v90;\n long long v91;\n unsigned int v92;\n unsigned int v93;\n char *ptr;\n int ptra;\n void *ptrb;\n uint32_t *v97;\n int v98;\n long long v99;\n int v100;\n int v101;\n long long v102;\n long long v103;\n long long v104;\n int *v105;\n uint32_t *v106;\n uint32_t *v107;\n long long v108;\n int v109;\n int v110;\n int v111;\n unsigned long long v112;\n v3 = a2;\n v5 = 0;\n v7 = a3;\n v112 = __readfsqword(40u);\n v8 = malloc(400uLL);\n v111 = 0;\n v9 = v8;\n if (a2 <= 0) {\n ptrb = v8;\n v83 = malloc(800uLL);\n *a3 = 0;\n v16 = ptrb;\n v17 = v83;\n } else {\n do {\n v10 = 4LL * v5;\n v11 = a1 + v10;\n v12 = *(uint32_t *)(a1 + v10);\n if (v12 == -1) {\n v25 = (uint32_t *)(a1 + v10 + 4);\n v26 = 0LL;\n v27 = *v25;\n if (*v25 == -2) {\n ++v5;\n } else {\n do\n v28 = v26++;\n while (*(uint32_t *)(v11 + 4 * v28 + 8) != -2);\n v29 = a1;\n v30 = v28;\n v31 = v5;\n v32 = 0;\n v33 = v28;\n v34 = v3;\n if (v27 != -1) {\n LABEL_19:\n if (v27 != -2) {\n v35 = v111 + 1;\n v9[v111] = v27;\n v111 = v35;\n }\n v36 = v32;\n goto LABEL_22;\n }\n while (1) {\n v36 = v32 + 1;\n v37 = v32 + 1;\n v38 = &v25[v37];\n v39 = v25[v37];\n if (v39 != -2) {\n v40 = (long long)&v25[v37 - 1];\n v41 = 0LL;\n do\n v42 = v41++;\n while (*(uint32_t *)(v40 + 4 * v42 + 8) != -2);\n v97 = v25;\n v43 = v29;\n v44 = 0;\n v45 = v42;\n v98 = v30;\n v46 = v31;\n v47 = v33;\n v48 = v34;\n ptra = v32;\n v49 = v7;\n v50 = v42;\n if (v39 != -1) {\n LABEL_28:\n if (v39 != -2) {\n v51 = v111 + 1;\n v9[v111] = v39;\n v111 = v51;\n }\n v52 = v44;\n goto LABEL_31;\n }\n while (1) {\n v52 = v44 + 1;\n v53 = v44 + 1;\n v54 = &v38[v53];\n v55 = v38[v53];\n if (v55 != -2) {\n v56 = (long long)&v38[v53 - 1];\n v57 = 0LL;\n do\n v58 = v57++;\n while (*(uint32_t *)(v56 + 4 * v58 + 8) != -2);\n v100 = v46;\n v59 = v58;\n v60 = v49;\n v61 = 0;\n v102 = v47;\n v62 = v44;\n v63 = v48;\n v103 = v43;\n v64 = v58;\n v99 = v45;\n v101 = v50;\n if (v55 != -1) {\n LABEL_37:\n if (v55 != -2) {\n v65 = v111 + 1;\n v9[v111] = v55;\n v111 = v65;\n }\n v66 = v61;\n goto LABEL_40;\n }\n while (1) {\n v66 = v61 + 1;\n v67 = v61 + 1;\n v68 = &v54[v67];\n v69 = v54[v67];\n if (v69 != -2) {\n v70 = (long long)&v54[v67 - 1];\n v71 = 0LL;\n do\n v72 = v71++;\n while (*(uint32_t *)(v70 + 4 * v72 + 8) != -2);\n v105 = v60;\n v73 = v38;\n v74 = v72;\n v75 = v54;\n v104 = v64;\n v76 = 0;\n v77 = v72;\n v78 = v73;\n while (1) {\n if (v69 == -1) {\n v87 = v76 + 1;\n v80 = v87;\n v88 = v87;\n v89 = &v68[v88];\n if (v68[v88] == -2) {\n v93 = 0;\n } else {\n v90 = (long long)&v68[v88 - 1];\n v91 = 1LL;\n do\n v92 = v91++;\n while (*(uint32_t *)(v90 + 4 * v91) != -2);\n v93 = v92;\n v80 = v87 + v92;\n }\n v110 = v63;\n v108 = v77;\n v109 = v59;\n v107 = v78;\n v106 = v9;\n sub_13E0(v89, v9, &v111, v93);\n v9 = v106;\n v78 = v107;\n v59 = v109;\n v77 = v108;\n v63 = v110;\n } else {\n if (v69 != -2) {\n v79 = v111 + 1;\n v9[v111] = v69;\n v111 = v79;\n }\n v80 = v76;\n }\n v76 = v80 + 1;\n if (v80 >= v74) break;\n v69 = v68[v76];\n }\n v85 = v78;\n v86 = v77;\n v54 = v75;\n v64 = v104;\n v60 = v105;\n v38 = v85;\n v66 = v61 + v86 + 2;\n }\n LABEL_40:\n v61 = v66 + 1;\n if (v66 >= v59) break;\n v55 = v54[v61];\n if (v55 != -1) goto LABEL_37;\n }\n v84 = v62;\n v48 = v63;\n v49 = v60;\n v45 = v99;\n v50 = v101;\n v52 = v84 + v64 + 2;\n v43 = v103;\n v47 = v102;\n v46 = v100;\n }\n LABEL_31:\n v44 = v52 + 1;\n if (v52 >= v50) break;\n v39 = v38[v44];\n if (v39 != -1) goto LABEL_28;\n }\n v82 = v45;\n v31 = v46;\n v7 = v49;\n v29 = v43;\n v34 = v48;\n v25 = v97;\n v33 = v47;\n v36 = ptra + v82 + 2;\n v30 = v98;\n }\n LABEL_22:\n v32 = v36 + 1;\n if (v36 >= v30) break;\n v27 = v25[v32];\n if (v27 != -1) goto LABEL_19;\n }\n v3 = v34;\n v81 = v31;\n a1 = v29;\n v5 = v81 + v33 + 2;\n }\n } else if (v12 != -2) {\n v13 = v111 + 1;\n v9[v111] = v12;\n v111 = v13;\n }\n ++v5;\n } while (v3 > v5);\n v14 = v111;\n ptr = (char *)v9;\n v15 = malloc(800uLL);\n *v7 = 0;\n v16 = ptr;\n v17 = v15;\n if ((int)v14 > 0) {\n v18 = ptr;\n v19 = &ptr[4 * v14];\n v20 = 0;\n while (1) {\n v21 = *(uint32_t *)v18;\n if (v20 > 0) break;\n LABEL_14:\n v23 = &v17[2 * v20++];\n v18 += 4;\n *v23 = v21;\n v23[1] = 1;\n *v7 = v20;\n if (v18 == v19) goto LABEL_15;\n }\n while (1) {\n v22 = v17;\n while (*v22 != v21) {\n v22 += 2;\n if (v22 == &v17[2 * v20]) goto LABEL_14;\n }\n v18 += 4;\n ++v22[1];\n if (v18 == v19) break;\n v21 = *(uint32_t *)v18;\n }\n }\n }\nLABEL_15:\n free(v16);\n return v17;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, int *a3) {\n int v3;\n int v5;\n int *v7;\n uint32_t *v8;\n uint32_t *v9;\n long long v10;\n long long v11;\n int v12;\n int v13;\n long long v14;\n uint32_t *v15;\n void *v16;\n uint32_t *v17;\n char *v18;\n char *v19;\n int v20;\n int v21;\n uint32_t *v22;\n uint32_t *v23;\n uint32_t *v25;\n long long v26;\n int v27;\n long long v28;\n long long v29;\n int v30;\n int v31;\n int v32;\n long long v33;\n int v34;\n int v35;\n int v36;\n long long v37;\n uint32_t *v38;\n int v39;\n long long v40;\n long long v41;\n long long v42;\n long long v43;\n int v44;\n long long v45;\n int v46;\n long long v47;\n int v48;\n int *v49;\n int v50;\n int v51;\n int v52;\n long long v53;\n uint32_t *v54;\n int v55;\n long long v56;\n long long v57;\n long long v58;\n int v59;\n int *v60;\n int v61;\n int v62;\n int v63;\n long long v64;\n int v65;\n int v66;\n long long v67;\n uint32_t *v68;\n int v69;\n long long v70;\n long long v71;\n long long v72;\n uint32_t *v73;\n int v74;\n uint32_t *v75;\n int v76;\n long long v77;\n uint32_t *v78;\n int v79;\n int v80;\n int v81;\n int v82;\n uint32_t *v83;\n int v84;\n uint32_t *v85;\n int v86;\n int v87;\n long long v88;\n uint32_t *v89;\n long long v90;\n long long v91;\n unsigned int v92;\n unsigned int v93;\n char *ptr;\n int ptra;\n void *ptrb;\n uint32_t *v97;\n int v98;\n long long v99;\n int v100;\n int v101;\n long long v102;\n long long v103;\n long long v104;\n int *v105;\n uint32_t *v106;\n uint32_t *v107;\n long long v108;\n int v109;\n int v110;\n int v111;\n unsigned long long v112;\n v3 = a2;\n v5 = 0;\n v7 = a3;\n v112 = __readfsqword(40u);\n v8 = malloc(400uLL);\n v111 = 0;\n v9 = v8;\n if (a2 <= 0) {\n ptrb = v8;\n v83 = malloc(800uLL);\n *a3 = 0;\n v16 = ptrb;\n v17 = v83;\n } else {\n do {\n v10 = 4LL * v5;\n v11 = a1 + v10;\n v12 = *(uint32_t *)(a1 + v10);\n if (v12 == -1) {\n v25 = (uint32_t *)(a1 + v10 + 4);\n v26 = 0LL;\n v27 = *v25;\n if (*v25 == -2) {\n ++v5;\n } else {\n do\n v28 = v26++;\n while (*(uint32_t *)(v11 + 4 * v28 + 8) != -2);\n v29 = a1;\n v30 = v28;\n v31 = v5;\n v32 = 0;\n v33 = v28;\n v34 = v3;\n if (v27 != -1) {\n LABEL_19:\n if (v27 != -2) {\n v35 = v111 + 1;\n v9[v111] = v27;\n v111 = v35;\n }\n v36 = v32;\n goto LABEL_22;\n }\n while (1) {\n v36 = v32 + 1;\n v37 = v32 + 1;\n v38 = &v25[v37];\n v39 = v25[v37];\n if (v39 != -2) {\n v40 = (long long)&v25[v37 - 1];\n v41 = 0LL;\n do\n v42 = v41++;\n while (*(uint32_t *)(v40 + 4 * v42 + 8) != -2);\n v97 = v25;\n v43 = v29;\n v44 = 0;\n v45 = v42;\n v98 = v30;\n v46 = v31;\n v47 = v33;\n v48 = v34;\n ptra = v32;\n v49 = v7;\n v50 = v42;\n if (v39 != -1) {\n LABEL_28:\n if (v39 != -2) {\n v51 = v111 + 1;\n v9[v111] = v39;\n v111 = v51;\n }\n v52 = v44;\n goto LABEL_31;\n }\n while (1) {\n v52 = v44 + 1;\n v53 = v44 + 1;\n v54 = &v38[v53];\n v55 = v38[v53];\n if (v55 != -2) {\n v56 = (long long)&v38[v53 - 1];\n v57 = 0LL;\n do\n v58 = v57++;\n while (*(uint32_t *)(v56 + 4 * v58 + 8) != -2);\n v100 = v46;\n v59 = v58;\n v60 = v49;\n v61 = 0;\n v102 = v47;\n v62 = v44;\n v63 = v48;\n v103 = v43;\n v64 = v58;\n v99 = v45;\n v101 = v50;\n if (v55 != -1) {\n LABEL_37:\n if (v55 != -2) {\n v65 = v111 + 1;\n v9[v111] = v55;\n v111 = v65;\n }\n v66 = v61;\n goto LABEL_40;\n }\n while (1) {\n v66 = v61 + 1;\n v67 = v61 + 1;\n v68 = &v54[v67];\n v69 = v54[v67];\n if (v69 != -2) {\n v70 = (long long)&v54[v67 - 1];\n v71 = 0LL;\n do\n v72 = v71++;\n while (*(uint32_t *)(v70 + 4 * v72 + 8) != -2);\n v105 = v60;\n v73 = v38;\n v74 = v72;\n v75 = v54;\n v104 = v64;\n v76 = 0;\n v77 = v72;\n v78 = v73;\n while (1) {\n if (v69 == -1) {\n v87 = v76 + 1;\n v80 = v87;\n v88 = v87;\n v89 = &v68[v88];\n if (v68[v88] == -2) {\n v93 = 0;\n } else {\n v90 = (long long)&v68[v88 - 1];\n v91 = 1LL;\n do\n v92 = v91++;\n while (*(uint32_t *)(v90 + 4 * v91) != -2);\n v93 = v92;\n v80 = v87 + v92;\n }\n v110 = v63;\n v108 = v77;\n v109 = v59;\n v107 = v78;\n v106 = v9;\n flatten(v89, v9, &v111, v93);\n v9 = v106;\n v78 = v107;\n v59 = v109;\n v77 = v108;\n v63 = v110;\n } else {\n if (v69 != -2) {\n v79 = v111 + 1;\n v9[v111] = v69;\n v111 = v79;\n }\n v80 = v76;\n }\n v76 = v80 + 1;\n if (v80 >= v74) break;\n v69 = v68[v76];\n }\n v85 = v78;\n v86 = v77;\n v54 = v75;\n v64 = v104;\n v60 = v105;\n v38 = v85;\n v66 = v61 + v86 + 2;\n }\n LABEL_40:\n v61 = v66 + 1;\n if (v66 >= v59) break;\n v55 = v54[v61];\n if (v55 != -1) goto LABEL_37;\n }\n v84 = v62;\n v48 = v63;\n v49 = v60;\n v45 = v99;\n v50 = v101;\n v52 = v84 + v64 + 2;\n v43 = v103;\n v47 = v102;\n v46 = v100;\n }\n LABEL_31:\n v44 = v52 + 1;\n if (v52 >= v50) break;\n v39 = v38[v44];\n if (v39 != -1) goto LABEL_28;\n }\n v82 = v45;\n v31 = v46;\n v7 = v49;\n v29 = v43;\n v34 = v48;\n v25 = v97;\n v33 = v47;\n v36 = ptra + v82 + 2;\n v30 = v98;\n }\n LABEL_22:\n v32 = v36 + 1;\n if (v36 >= v30) break;\n v27 = v25[v32];\n if (v27 != -1) goto LABEL_19;\n }\n v3 = v34;\n v81 = v31;\n a1 = v29;\n v5 = v81 + v33 + 2;\n }\n } else if (v12 != -2) {\n v13 = v111 + 1;\n v9[v111] = v12;\n v111 = v13;\n }\n ++v5;\n } while (v3 > v5);\n v14 = v111;\n ptr = (char *)v9;\n v15 = malloc(800uLL);\n *v7 = 0;\n v16 = ptr;\n v17 = v15;\n if ((int)v14 > 0) {\n v18 = ptr;\n v19 = &ptr[4 * v14];\n v20 = 0;\n while (1) {\n v21 = *(uint32_t *)v18;\n if (v20 > 0) break;\n LABEL_14:\n v23 = &v17[2 * v20++];\n v18 += 4;\n *v23 = v21;\n v23[1] = 1;\n *v7 = v20;\n if (v18 == v19) goto LABEL_15;\n }\n while (1) {\n v22 = v17;\n while (*v22 != v21) {\n v22 += 2;\n if (v22 == &v17[2 * v20]) goto LABEL_14;\n }\n v18 += 4;\n ++v22[1];\n if (v18 == v19) break;\n v21 = *(uint32_t *)v18;\n }\n }\n }\nLABEL_15:\n free(v16);\n return v17;\n}" + }, + { + "index": 513, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n", + "func": "char** func0(int* test_tup, int size, char* K) {\n char** res = malloc(2 * size * sizeof(char*));\n int j = 0;\n for (int i = 0; i < size; i++) {\n asprintf(&res[j++], \"%d\", test_tup[i]);\n res[j++] = K;\n }\n return res;\n}", + "test": "int main() {\n\n int test_tup1[] = {5, 6, 7, 4, 9};\n\n int test_tup1_size = sizeof(test_tup1) / sizeof(test_tup1[0]);\n\n char** result1 = func0(test_tup1, test_tup1_size, \"FDF\");\n\n assert(strcmp(result1[0], \"5\") == 0 && strcmp(result1[1], \"FDF\") == 0 && strcmp(result1[2], \"6\") == 0);\n\n \n\n int test_tup2[] = {7, 8, 9, 10};\n\n int test_tup2_size = sizeof(test_tup2) / sizeof(test_tup2[0]);\n\n char** result2 = func0(test_tup2, test_tup2_size, \"PF\");\n\n assert(strcmp(result2[0], \"7\") == 0 && strcmp(result2[1], \"PF\") == 0 && strcmp(result2[2], \"8\") == 0);\n\n \n\n int test_tup3[] = {11, 14, 12, 1, 4};\n\n int test_tup3_size = sizeof(test_tup3) / sizeof(test_tup3[0]);\n\n char** result3 = func0(test_tup3, test_tup3_size, \"JH\");\n\n assert(strcmp(result3[0], \"11\") == 0 && strcmp(result3[1], \"JH\") == 0 && strcmp(result3[2], \"14\") == 0);\n\n \n\n printf(\"All tests passed!\\n\");\n\n\n\n // freeing allocated memory\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmov -0x1c(%rbp),%eax\nadd %eax,%eax\ncltq\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 1100 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 12b0 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x10(%rbp),%eax\nlea 0x1(%rax),%ecx\nmov %ecx,-0x10(%rbp)\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x8(%rbp),%rax\nadd %rcx,%rax\nlea 0xd8a(%rip),%rsi\nmov %rax,%rdi\nmov $0x0,%eax\ncallq 1110 \nmov -0x10(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x10(%rbp)\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov -0x28(%rbp),%rax\nmov %rax,(%rdx)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1247 \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov eax, [rbp+var_1C]\nadd eax, eax\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp short loc_12B3\nloc_1247:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\nlea ecx, [rax+1]\nmov [rbp+var_10], ecx\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rcx\nlea rcx, fmt; \"%d\"\nmov rsi, rcx; fmt\nmov rdi, rax; ptr\nmov eax, 0\ncall _asprintf\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov rax, [rbp+var_28]\nmov [rdx], rax\nadd [rbp+var_C], 1\nloc_12B3:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_1247\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "char **__fastcall func0(__int64 a1, int a2, char *a3)\n{\n int v3; // eax\n int v6; // [rsp+20h] [rbp-10h]\n int i; // [rsp+24h] [rbp-Ch]\n char **v8; // [rsp+28h] [rbp-8h]\n\n v8 = (char **)malloc(16LL * a2);\n v6 = 0;\n for ( i = 0; i < a2; ++i )\n {\n asprintf(&v8[v6], \"%d\", *(_DWORD *)(4LL * i + a1));\n v3 = v6 + 1;\n v6 += 2;\n v8[v3] = a3;\n }\n return v8;\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov eax, [rbp+var_1C]\nadd eax, eax\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp short loc_12B3\nloc_1247:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\nlea ecx, [rax+1]\nmov [rbp+var_10], ecx\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rcx\nlea rcx, fmt; \"%d\"\nmov rsi, rcx; fmt\nmov rdi, rax; ptr\nmov eax, 0\ncall _asprintf\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov rax, [rbp+var_28]\nmov [rdx], rax\nadd [rbp+var_C], 1\nloc_12B3:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_1247\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "char **__fastcall sub_1209(__int64 a1, int a2, char *a3)\n{\n int v3; // eax\n int v6; // [rsp+20h] [rbp-10h]\n int i; // [rsp+24h] [rbp-Ch]\n char **v8; // [rsp+28h] [rbp-8h]\n\n v8 = (char **)malloc(16LL * a2);\n v6 = 0;\n for ( i = 0; i < a2; ++i )\n {\n asprintf(&v8[v6], \"%d\", *(_DWORD *)(4LL * i + a1));\n v3 = v6 + 1;\n v6 += 2;\n v8[v3] = a3;\n }\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char **sub_1209(long long a1, int a2, char *a3) {\n int v3;\n int v6;\n int i;\n char **v8;\n v8 = (char **)malloc(16LL * a2);\n v6 = 0;\n for (i = 0; i < a2; ++i) {\n asprintf(&v8[v6], \"%d\", *(uint32_t *)(4LL * i + a1));\n v3 = v6 + 1;\n v6 += 2;\n v8[v3] = a3;\n }\n return v8;\n}", + "ida_pseudo_norm": "char **func0(long long a1, int a2, char *a3) {\n int v3;\n int v6;\n int i;\n char **v8;\n v8 = (char **)malloc(16LL * a2);\n v6 = 0;\n for (i = 0; i < a2; ++i) {\n asprintf(&v8[v6], \"%d\", *(uint32_t *)(4LL * i + a1));\n v3 = v6 + 1;\n v6 += 2;\n v8[v3] = a3;\n }\n return v8;\n}" + }, + { + "index": 513, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n", + "func": "char** func0(int* test_tup, int size, char* K) {\n char** res = malloc(2 * size * sizeof(char*));\n int j = 0;\n for (int i = 0; i < size; i++) {\n asprintf(&res[j++], \"%d\", test_tup[i]);\n res[j++] = K;\n }\n return res;\n}", + "test": "int main() {\n\n int test_tup1[] = {5, 6, 7, 4, 9};\n\n int test_tup1_size = sizeof(test_tup1) / sizeof(test_tup1[0]);\n\n char** result1 = func0(test_tup1, test_tup1_size, \"FDF\");\n\n assert(strcmp(result1[0], \"5\") == 0 && strcmp(result1[1], \"FDF\") == 0 && strcmp(result1[2], \"6\") == 0);\n\n \n\n int test_tup2[] = {7, 8, 9, 10};\n\n int test_tup2_size = sizeof(test_tup2) / sizeof(test_tup2[0]);\n\n char** result2 = func0(test_tup2, test_tup2_size, \"PF\");\n\n assert(strcmp(result2[0], \"7\") == 0 && strcmp(result2[1], \"PF\") == 0 && strcmp(result2[2], \"8\") == 0);\n\n \n\n int test_tup3[] = {11, 14, 12, 1, 4};\n\n int test_tup3_size = sizeof(test_tup3) / sizeof(test_tup3[0]);\n\n char** result3 = func0(test_tup3, test_tup3_size, \"JH\");\n\n assert(strcmp(result3[0], \"11\") == 0 && strcmp(result3[1], \"JH\") == 0 && strcmp(result3[2], \"14\") == 0);\n\n \n\n printf(\"All tests passed!\\n\");\n\n\n\n // freeing allocated memory\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbp\nmov %esi,%r12d\nmov %rdx,%r13\nlea (%rsi,%rsi,1),%edi\nmovslq %edi,%rdi\nshl $0x3,%rdi\ncallq 10e0 \nmov %rax,%r14\ntest %r12d,%r12d\njle 1259 \nmov %rax,%rbx\nlea -0x1(%r12),%r12d\nadd $0x1,%r12\nshl $0x4,%r12\nadd %rax,%r12\nlea 0xdcf(%rip),%r15\nmov 0x0(%rbp),%edx\nmov %r15,%rsi\nmov %rbx,%rdi\nmov $0x0,%eax\ncallq 10f0 \nmov %r13,0x8(%rbx)\nadd $0x4,%rbp\nadd $0x10,%rbx\ncmp %r12,%rbx\njne 1235 \nmov %r14,%rax\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov ebx, esi\nmov r13, rdx\nlea r12d, [rsi+rsi]\nmovsxd r12, r12d\nshl r12, 3\nmov rdi, r12; size\ncall _malloc\nmov r14, rax\ntest ebx, ebx\njle short loc_126E\nmov rbx, rax\nadd r12, rax\nlea r15, fmt; \"%d\"\nloc_124A:\nmov edx, [rbp+0]\nmov rsi, r15; fmt\nmov rdi, rbx; ptr\nmov eax, 0\ncall _asprintf\nmov [rbx+8], r13\nadd rbp, 4\nadd rbx, 10h\ncmp rbx, r12\njnz short loc_124A\nloc_126E:\nmov rax, r14\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "char *__fastcall func0(_DWORD *a1, int a2, char *a3)\n{\n char *v5; // rax\n char *v6; // r14\n char **v7; // rbx\n char *v8; // r12\n\n v5 = (char *)malloc(16LL * a2);\n v6 = v5;\n if ( a2 > 0 )\n {\n v7 = (char **)v5;\n v8 = &v5[16 * a2];\n do\n {\n asprintf(v7, \"%d\", *a1);\n v7[1] = a3;\n ++a1;\n v7 += 2;\n }\n while ( v7 != (char **)v8 );\n }\n return v6;\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov ebx, esi\nmov r13, rdx\nlea r12d, [rsi+rsi]\nmovsxd r12, r12d\nshl r12, 3\nmov rdi, r12; size\ncall _malloc\nmov r14, rax\ntest ebx, ebx\njle short loc_126E\nmov rbx, rax\nadd r12, rax\nlea r15, fmt; \"%d\"\nloc_124A:\nmov edx, [rbp+0]\nmov rsi, r15; fmt\nmov rdi, rbx; ptr\nmov eax, 0\ncall _asprintf\nmov [rbx+8], r13\nadd rbp, 4\nadd rbx, 10h\ncmp rbx, r12\njnz short loc_124A\nloc_126E:\nmov rax, r14\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1209(_DWORD *a1, int a2, char *a3)\n{\n char *v5; // rax\n char *v6; // r14\n char **v7; // rbx\n char *v8; // r12\n\n v5 = (char *)malloc(16LL * a2);\n v6 = v5;\n if ( a2 > 0 )\n {\n v7 = (char **)v5;\n v8 = &v5[16 * a2];\n do\n {\n asprintf(v7, \"%d\", *a1);\n v7[1] = a3;\n ++a1;\n v7 += 2;\n }\n while ( v7 != (char **)v8 );\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1209(uint32_t *a1, int a2, char *a3) {\n char *v5;\n char *v6;\n char **v7;\n char *v8;\n v5 = (char *)malloc(16LL * a2);\n v6 = v5;\n if (a2 > 0) {\n v7 = (char **)v5;\n v8 = &v5[16 * a2];\n do {\n asprintf(v7, \"%d\", *a1);\n v7[1] = a3;\n ++a1;\n v7 += 2;\n } while (v7 != (char **)v8);\n }\n return v6;\n}", + "ida_pseudo_norm": "char *func0(uint32_t *a1, int a2, char *a3) {\n char *v5;\n char *v6;\n char **v7;\n char *v8;\n v5 = (char *)malloc(16LL * a2);\n v6 = v5;\n if (a2 > 0) {\n v7 = (char **)v5;\n v8 = &v5[16 * a2];\n do {\n asprintf(v7, \"%d\", *a1);\n v7[1] = a3;\n ++a1;\n v7 += 2;\n } while (v7 != (char **)v8);\n }\n return v6;\n}" + }, + { + "index": 513, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n", + "func": "char** func0(int* test_tup, int size, char* K) {\n char** res = malloc(2 * size * sizeof(char*));\n int j = 0;\n for (int i = 0; i < size; i++) {\n asprintf(&res[j++], \"%d\", test_tup[i]);\n res[j++] = K;\n }\n return res;\n}", + "test": "int main() {\n\n int test_tup1[] = {5, 6, 7, 4, 9};\n\n int test_tup1_size = sizeof(test_tup1) / sizeof(test_tup1[0]);\n\n char** result1 = func0(test_tup1, test_tup1_size, \"FDF\");\n\n assert(strcmp(result1[0], \"5\") == 0 && strcmp(result1[1], \"FDF\") == 0 && strcmp(result1[2], \"6\") == 0);\n\n \n\n int test_tup2[] = {7, 8, 9, 10};\n\n int test_tup2_size = sizeof(test_tup2) / sizeof(test_tup2[0]);\n\n char** result2 = func0(test_tup2, test_tup2_size, \"PF\");\n\n assert(strcmp(result2[0], \"7\") == 0 && strcmp(result2[1], \"PF\") == 0 && strcmp(result2[2], \"8\") == 0);\n\n \n\n int test_tup3[] = {11, 14, 12, 1, 4};\n\n int test_tup3_size = sizeof(test_tup3) / sizeof(test_tup3[0]);\n\n char** result3 = func0(test_tup3, test_tup3_size, \"JH\");\n\n assert(strcmp(result3[0], \"11\") == 0 && strcmp(result3[1], \"JH\") == 0 && strcmp(result3[2], \"14\") == 0);\n\n \n\n printf(\"All tests passed!\\n\");\n\n\n\n // freeing allocated memory\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\nmov %rdx,%r13\npush %r12\nmov %esi,%r12d\npush %rbp\nmov %rdi,%rbp\nlea (%rsi,%rsi,1),%edi\npush %rbx\nmovslq %edi,%rdi\nshl $0x3,%rdi\nsub $0x8,%rsp\ncallq 10e0 \nmov %rax,%r14\ntest %r12d,%r12d\njle 1481 \nsub $0x1,%r12d\nmov %rax,%rbx\nlea 0xbb4(%rip),%r15\nadd $0x1,%r12\nshl $0x4,%r12\nadd %rax,%r12\nnopl 0x0(%rax,%rax,1)\nmov 0x0(%rbp),%edx\nmov %rbx,%rdi\nmov %r15,%rsi\nxor %eax,%eax\nadd $0x10,%rbx\nadd $0x4,%rbp\ncallq 10f0 \nmov %r13,-0x8(%rbx)\ncmp %r12,%rbx\njne 1460 \nadd $0x8,%rsp\nmov %r14,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\nmov r13, rdx\npush r12\nlea r12d, [rsi+rsi]\npush rbp\nmovsxd r12, r12d\nmov rbp, rdi\npush rbx\nshl r12, 3\nmov ebx, esi\nmov rdi, r12; size\nsub rsp, 8\ncall _malloc\nmov r14, rax\ntest ebx, ebx\njle short loc_1459\nmov rbx, rax\nadd r12, rax\nlea r15, fmt; \"%d\"\nnop dword ptr [rax+00000000h]\nloc_1438:\nmov edx, [rbp+0]\nmov rdi, rbx; ptr\nmov rsi, r15; fmt\nxor eax, eax\nadd rbx, 10h\nadd rbp, 4\ncall _asprintf\nmov [rbx-8], r13\ncmp rbx, r12\njnz short loc_1438\nloc_1459:\nadd rsp, 8\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "char **__fastcall func0(int *a1, int a2, char *a3)\n{\n char **v5; // rax\n char **v6; // r14\n char **v7; // rbx\n char **v8; // r12\n int v9; // edx\n char **v10; // rdi\n\n v5 = (char **)malloc(16LL * a2);\n v6 = v5;\n if ( a2 > 0 )\n {\n v7 = v5;\n v8 = &v5[2 * a2];\n do\n {\n v9 = *a1;\n v10 = v7;\n v7 += 2;\n ++a1;\n asprintf(v10, \"%d\", v9);\n *(v7 - 1) = a3;\n }\n while ( v7 != v8 );\n }\n return v6;\n}", + "ida_strip_asm": "sub_13F0:\nendbr64\npush r15\npush r14\npush r13\nmov r13, rdx\npush r12\nlea r12d, [rsi+rsi]\npush rbp\nmovsxd r12, r12d\nmov rbp, rdi\npush rbx\nshl r12, 3\nmov ebx, esi\nmov rdi, r12; size\nsub rsp, 8\ncall _malloc\nmov r14, rax\ntest ebx, ebx\njle short loc_1459\nmov rbx, rax\nadd r12, rax\nlea r15, fmt; \"%d\"\nnop dword ptr [rax+00000000h]\nloc_1438:\nmov edx, [rbp+0]\nmov rdi, rbx; ptr\nmov rsi, r15; fmt\nxor eax, eax\nadd rbx, 10h\nadd rbp, 4\ncall _asprintf\nmov [rbx-8], r13\ncmp rbx, r12\njnz short loc_1438\nloc_1459:\nadd rsp, 8\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "char **__fastcall sub_13F0(int *a1, int a2, char *a3)\n{\n char **v5; // rax\n char **v6; // r14\n char **v7; // rbx\n char **v8; // r12\n int v9; // edx\n char **v10; // rdi\n\n v5 = (char **)malloc(16LL * a2);\n v6 = v5;\n if ( a2 > 0 )\n {\n v7 = v5;\n v8 = &v5[2 * a2];\n do\n {\n v9 = *a1;\n v10 = v7;\n v7 += 2;\n ++a1;\n asprintf(v10, \"%d\", v9);\n *(v7 - 1) = a3;\n }\n while ( v7 != v8 );\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char **sub_13F0(int *a1, int a2, char *a3) {\n char **v5;\n char **v6;\n char **v7;\n char **v8;\n int v9;\n char **v10;\n v5 = (char **)malloc(16LL * a2);\n v6 = v5;\n if (a2 > 0) {\n v7 = v5;\n v8 = &v5[2 * a2];\n do {\n v9 = *a1;\n v10 = v7;\n v7 += 2;\n ++a1;\n asprintf(v10, \"%d\", v9);\n *(v7 - 1) = a3;\n } while (v7 != v8);\n }\n return v6;\n}", + "ida_pseudo_norm": "char **func0(int *a1, int a2, char *a3) {\n char **v5;\n char **v6;\n char **v7;\n char **v8;\n int v9;\n char **v10;\n v5 = (char **)malloc(16LL * a2);\n v6 = v5;\n if (a2 > 0) {\n v7 = v5;\n v8 = &v5[2 * a2];\n do {\n v9 = *a1;\n v10 = v7;\n v7 += 2;\n ++a1;\n asprintf(v10, \"%d\", v9);\n *(v7 - 1) = a3;\n } while (v7 != v8);\n }\n return v6;\n}" + }, + { + "index": 513, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n", + "func": "char** func0(int* test_tup, int size, char* K) {\n char** res = malloc(2 * size * sizeof(char*));\n int j = 0;\n for (int i = 0; i < size; i++) {\n asprintf(&res[j++], \"%d\", test_tup[i]);\n res[j++] = K;\n }\n return res;\n}", + "test": "int main() {\n\n int test_tup1[] = {5, 6, 7, 4, 9};\n\n int test_tup1_size = sizeof(test_tup1) / sizeof(test_tup1[0]);\n\n char** result1 = func0(test_tup1, test_tup1_size, \"FDF\");\n\n assert(strcmp(result1[0], \"5\") == 0 && strcmp(result1[1], \"FDF\") == 0 && strcmp(result1[2], \"6\") == 0);\n\n \n\n int test_tup2[] = {7, 8, 9, 10};\n\n int test_tup2_size = sizeof(test_tup2) / sizeof(test_tup2[0]);\n\n char** result2 = func0(test_tup2, test_tup2_size, \"PF\");\n\n assert(strcmp(result2[0], \"7\") == 0 && strcmp(result2[1], \"PF\") == 0 && strcmp(result2[2], \"8\") == 0);\n\n \n\n int test_tup3[] = {11, 14, 12, 1, 4};\n\n int test_tup3_size = sizeof(test_tup3) / sizeof(test_tup3[0]);\n\n char** result3 = func0(test_tup3, test_tup3_size, \"JH\");\n\n assert(strcmp(result3[0], \"11\") == 0 && strcmp(result3[1], \"JH\") == 0 && strcmp(result3[2], \"14\") == 0);\n\n \n\n printf(\"All tests passed!\\n\");\n\n\n\n // freeing allocated memory\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\nmov %rdx,%r13\npush %r12\nmov %esi,%r12d\npush %rbp\nmov %rdi,%rbp\nlea (%rsi,%rsi,1),%edi\npush %rbx\nmovslq %edi,%rdi\nshl $0x3,%rdi\nsub $0x8,%rsp\ncallq 10e0 \nmov %rax,%r14\ntest %r12d,%r12d\njle 1451 \nsub $0x1,%r12d\nmov %rax,%rbx\nlea 0xbe4(%rip),%r15\nadd $0x1,%r12\nshl $0x4,%r12\nadd %rax,%r12\nnopl 0x0(%rax,%rax,1)\nmov 0x0(%rbp),%edx\nmov %rbx,%rdi\nmov %r15,%rsi\nxor %eax,%eax\nadd $0x10,%rbx\nadd $0x4,%rbp\ncallq 10f0 \nmov %r13,-0x8(%rbx)\ncmp %rbx,%r12\njne 1430 \nadd $0x8,%rsp\nmov %r14,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\nmov r13, rdx\npush r12\nlea r12d, [rsi+rsi]\npush rbp\nmovsxd r12, r12d\nmov rbp, rdi\npush rbx\nshl r12, 3\nmov ebx, esi\nmov rdi, r12; size\nsub rsp, 8\ncall _malloc\nmov r14, rax\ntest ebx, ebx\njle short loc_1459\nmov rbx, rax\nadd r12, rax\nlea r15, fmt; \"%d\"\nnop dword ptr [rax+00000000h]\nloc_1438:\nmov edx, [rbp+0]\nmov rdi, rbx; ptr\nmov rsi, r15; fmt\nxor eax, eax\nadd rbx, 10h\nadd rbp, 4\ncall _asprintf\nmov [rbx-8], r13\ncmp r12, rbx\njnz short loc_1438\nloc_1459:\nadd rsp, 8\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "char **__fastcall func0(int *a1, int a2, char *a3)\n{\n char **v5; // rax\n char **v6; // r14\n char **v7; // rbx\n char **v8; // r12\n int v9; // edx\n char **v10; // rdi\n\n v5 = (char **)malloc(16LL * a2);\n v6 = v5;\n if ( a2 > 0 )\n {\n v7 = v5;\n v8 = &v5[2 * a2];\n do\n {\n v9 = *a1;\n v10 = v7;\n v7 += 2;\n ++a1;\n asprintf(v10, \"%d\", v9);\n *(v7 - 1) = a3;\n }\n while ( v8 != v7 );\n }\n return v6;\n}", + "ida_strip_asm": "sub_13F0:\nendbr64\npush r15\npush r14\npush r13\nmov r13, rdx\npush r12\nlea r12d, [rsi+rsi]\npush rbp\nmovsxd r12, r12d\nmov rbp, rdi\npush rbx\nshl r12, 3\nmov ebx, esi\nmov rdi, r12; size\nsub rsp, 8\ncall _malloc\nmov r14, rax\ntest ebx, ebx\njle short loc_1459\nmov rbx, rax\nadd r12, rax\nlea r15, fmt; \"%d\"\nnop dword ptr [rax+00000000h]\nloc_1438:\nmov edx, [rbp+0]\nmov rdi, rbx; ptr\nmov rsi, r15; fmt\nxor eax, eax\nadd rbx, 10h\nadd rbp, 4\ncall _asprintf\nmov [rbx-8], r13\ncmp r12, rbx\njnz short loc_1438\nloc_1459:\nadd rsp, 8\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "char **__fastcall sub_13F0(int *a1, int a2, char *a3)\n{\n char **v5; // rax\n char **v6; // r14\n char **v7; // rbx\n char **v8; // r12\n int v9; // edx\n char **v10; // rdi\n\n v5 = (char **)malloc(16LL * a2);\n v6 = v5;\n if ( a2 > 0 )\n {\n v7 = v5;\n v8 = &v5[2 * a2];\n do\n {\n v9 = *a1;\n v10 = v7;\n v7 += 2;\n ++a1;\n asprintf(v10, \"%d\", v9);\n *(v7 - 1) = a3;\n }\n while ( v8 != v7 );\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char **sub_13F0(int *a1, int a2, char *a3) {\n char **v5;\n char **v6;\n char **v7;\n char **v8;\n int v9;\n char **v10;\n v5 = (char **)malloc(16LL * a2);\n v6 = v5;\n if (a2 > 0) {\n v7 = v5;\n v8 = &v5[2 * a2];\n do {\n v9 = *a1;\n v10 = v7;\n v7 += 2;\n ++a1;\n asprintf(v10, \"%d\", v9);\n *(v7 - 1) = a3;\n } while (v8 != v7);\n }\n return v6;\n}", + "ida_pseudo_norm": "char **func0(int *a1, int a2, char *a3) {\n char **v5;\n char **v6;\n char **v7;\n char **v8;\n int v9;\n char **v10;\n v5 = (char **)malloc(16LL * a2);\n v6 = v5;\n if (a2 > 0) {\n v7 = v5;\n v8 = &v5[2 * a2];\n do {\n v9 = *a1;\n v10 = v7;\n v7 += 2;\n ++a1;\n asprintf(v10, \"%d\", v9);\n *(v7 - 1) = a3;\n } while (v8 != v7);\n }\n return v6;\n}" + }, + { + "index": 514, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int *arr, int len) {\n int sum = 0;\n for (int i = 0; i < len; i++) {\n sum += arr[i];\n }\n return sum;\n}", + "test": "int main() {\n\n int arr1[] = {7, 8, 9, 1, 10, 7};\n\n int arr2[] = {1, 2, 3, 4, 5, 6};\n\n int arr3[] = {11, 12, 13, 45, 14};\n\n\n\n assert(func0(arr1, 6) == 42);\n\n assert(func0(arr2, 6) == 21);\n\n assert(func0(arr3, 5) == 95);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11a5 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nadd %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1188 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11A5\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_11A5:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n v3 += *(_DWORD *)(4LL * i + a1);\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11A5\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_11A5:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n v3 += *(_DWORD *)(4LL * i + a1);\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) v3 += *(uint32_t *)(4LL * i + a1);\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) v3 += *(uint32_t *)(4LL * i + a1);\n return v3;\n}" + }, + { + "index": 514, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int *arr, int len) {\n int sum = 0;\n for (int i = 0; i < len; i++) {\n sum += arr[i];\n }\n return sum;\n}", + "test": "int main() {\n\n int arr1[] = {7, 8, 9, 1, 10, 7};\n\n int arr2[] = {1, 2, 3, 4, 5, 6};\n\n int arr3[] = {11, 12, 13, 45, 14};\n\n\n\n assert(func0(arr1, 6) == 42);\n\n assert(func0(arr2, 6) == 21);\n\n assert(func0(arr3, 5) == 95);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 118f \nmov %rdi,%rax\nlea -0x1(%rsi),%edx\nlea 0x4(%rdi,%rdx,4),%rcx\nmov $0x0,%edx\nadd (%rax),%edx\nadd $0x4,%rax\ncmp %rcx,%rax\njne 1181 \nmov %edx,%eax\nretq\nmov $0x0,%edx\njmp 118c \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_118E\nmov rax, rdi\nmovsxd rsi, esi\nlea rcx, [rdi+rsi*4]\nmov edx, 0\nloc_1180:\nadd edx, [rax]\nadd rax, 4\ncmp rax, rcx\njnz short loc_1180\nloc_118B:\nmov eax, edx\nretn\nloc_118E:\nmov edx, 0\njmp short loc_118B", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n unsigned int v3; // edx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = 0;\n do\n v3 += *v2++;\n while ( v2 != &a1[a2] );\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_118E\nmov rax, rdi\nmovsxd rsi, esi\nlea rcx, [rdi+rsi*4]\nmov edx, 0\nloc_1180:\nadd edx, [rax]\nadd rax, 4\ncmp rax, rcx\njnz short loc_1180\nloc_118B:\nmov eax, edx\nretn\nloc_118E:\nmov edx, 0\njmp short loc_118B", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n unsigned int v3; // edx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = 0;\n do\n v3 += *v2++;\n while ( v2 != &a1[a2] );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2) {\n uint32_t *v2;\n unsigned int v3;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = 0;\n do\n v3 += *v2++;\n while (v2 != &a1[a2]);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n unsigned int v3;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = 0;\n do\n v3 += *v2++;\n while (v2 != &a1[a2]);\n }\n return v3;\n}" + }, + { + "index": 515, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int arr[], int n, int m) {\n if (n > m) {\n return true;\n }\n bool DP[m];\n for (int i = 0; i < m; i++) {\n DP[i] = false;\n }\n for (int i = 0; i < n; i++) {\n if (DP[0]) {\n return true;\n }\n bool temp[m];\n for (int k = 0; k < m; k++) {\n temp[k] = false;\n }\n for (int j = 0; j < m; j++) {\n if (DP[j]) {\n if (!DP[(j + arr[i]) % m]) {\n temp[(j + arr[i]) % m] = true;\n }\n }\n }\n for (int j = 0; j < m; j++) {\n if (temp[j]) {\n DP[j] = true;\n }\n }\n DP[arr[i] % m] = true;\n }\n return DP[0];\n}", + "test": "int main() {\n\n int arr1[] = {3, 1, 7, 5};\n\n int arr2[] = {1, 7};\n\n int arr3[] = {1, 6};\n\n\n\n assert(func0(arr1, 4, 6) == true);\n\n assert(func0(arr2, 2, 5) == false);\n\n assert(func0(arr3, 2, 5) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r13\npush %r12\npush %rbx\nsub $0x58,%rsp\nmov %rdi,-0x68(%rbp)\nmov %esi,-0x6c(%rbp)\nmov %edx,-0x70(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x28(%rbp)\nxor %eax,%eax\nmov %rsp,%rax\nmov %rax,%rsi\nmov -0x6c(%rbp),%eax\ncmp -0x70(%rbp),%eax\njle 11ab \nmov $0x1,%eax\njmpq 1456 \nmov -0x70(%rbp),%eax\nmovslq %eax,%rdx\nsub $0x1,%rdx\nmov %rdx,-0x48(%rbp)\nmovslq %eax,%rdx\nmov %rdx,%r12\nmov $0x0,%r13d\nmovslq %eax,%rdx\nmov %rdx,%rcx\nmov $0x0,%ebx\ncltq\nmov $0x10,%edx\nsub $0x1,%rdx\nadd %rdx,%rax\nmov $0x10,%ebx\nmov $0x0,%edx\ndiv %rbx\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rbx\nsub %rdx,%rbx\nmov %rbx,%rdx\ncmp %rdx,%rsp\nje 1219 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 1202 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 1243 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x0,%rax\nmov %rax,-0x40(%rbp)\nmovl $0x0,-0x4c(%rbp)\njmp 1268 \nmov -0x40(%rbp),%rdx\nmov -0x4c(%rbp),%eax\ncltq\nmovb $0x0,(%rdx,%rax,1)\naddl $0x1,-0x4c(%rbp)\nmov -0x4c(%rbp),%eax\ncmp -0x70(%rbp),%eax\njl 1257 \nmovl $0x0,-0x50(%rbp)\njmpq 1443 \nmov %rsp,%rax\nmov %rax,%rcx\nmov -0x40(%rbp),%rax\nmovzbl (%rax),%eax\ntest %al,%al\nje 129a \nmov $0x1,%eax\nmov %rcx,%rsp\njmpq 1456 \nmov -0x70(%rbp),%eax\nmovslq %eax,%rdx\nsub $0x1,%rdx\nmov %rdx,-0x38(%rbp)\nmovslq %eax,%rdx\nmov %rdx,%r8\nmov $0x0,%r9d\nmovslq %eax,%rdx\nmov %rdx,%r10\nmov $0x0,%r11d\ncltq\nmov $0x10,%edx\nsub $0x1,%rdx\nadd %rdx,%rax\nmov $0x10,%edi\nmov $0x0,%edx\ndiv %rdi\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rdi\nsub %rdx,%rdi\nmov %rdi,%rdx\ncmp %rdx,%rsp\nje 1309 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 12f2 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 1333 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x0,%rax\nmov %rax,-0x30(%rbp)\nmovl $0x0,-0x54(%rbp)\njmp 1358 \nmov -0x30(%rbp),%rdx\nmov -0x54(%rbp),%eax\ncltq\nmovb $0x0,(%rdx,%rax,1)\naddl $0x1,-0x54(%rbp)\nmov -0x54(%rbp),%eax\ncmp -0x70(%rbp),%eax\njl 1347 \nmovl $0x0,-0x58(%rbp)\njmp 13db \nmov -0x40(%rbp),%rdx\nmov -0x58(%rbp),%eax\ncltq\nmovzbl (%rdx,%rax,1),%eax\ntest %al,%al\nje 13d7 \nmov -0x50(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x68(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x58(%rbp),%eax\nadd %edx,%eax\ncltd\nidivl -0x70(%rbp)\nmov %edx,%eax\nmov -0x40(%rbp),%rdx\ncltq\nmovzbl (%rdx,%rax,1),%eax\nxor $0x1,%eax\ntest %al,%al\nje 13d7 \nmov -0x50(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x68(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x58(%rbp),%eax\nadd %edx,%eax\ncltd\nidivl -0x70(%rbp)\nmov %edx,%eax\nmov -0x30(%rbp),%rdx\ncltq\nmovb $0x1,(%rdx,%rax,1)\naddl $0x1,-0x58(%rbp)\nmov -0x58(%rbp),%eax\ncmp -0x70(%rbp),%eax\njl 1369 \nmovl $0x0,-0x5c(%rbp)\njmp 140e \nmov -0x30(%rbp),%rdx\nmov -0x5c(%rbp),%eax\ncltq\nmovzbl (%rdx,%rax,1),%eax\ntest %al,%al\nje 140a \nmov -0x40(%rbp),%rdx\nmov -0x5c(%rbp),%eax\ncltq\nmovb $0x1,(%rdx,%rax,1)\naddl $0x1,-0x5c(%rbp)\nmov -0x5c(%rbp),%eax\ncmp -0x70(%rbp),%eax\njl 13ec \nmov -0x50(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x68(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncltd\nidivl -0x70(%rbp)\nmov %edx,%eax\nmov -0x40(%rbp),%rdx\ncltq\nmovb $0x1,(%rdx,%rax,1)\nmov %rcx,%rsp\naddl $0x1,-0x50(%rbp)\nmov -0x50(%rbp),%eax\ncmp -0x6c(%rbp),%eax\njl 127c \nmov -0x40(%rbp),%rax\nmovzbl (%rax),%eax\nmov %rsi,%rsp\nmov -0x28(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 146d \ncallq 1060 <__stack_chk_fail@plt>\nlea -0x18(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+var_48], rdi\nmov [rbp+var_4C], esi\nmov [rbp+var_50], edx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rdi, rax\nmov eax, [rbp+var_4C]\ncmp eax, [rbp+var_50]\njle short loc_11A6\nmov eax, 1\njmp loc_141C\nloc_11A6:\nmov eax, [rbp+var_50]\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_28], rdx\ncdqe\nmov edx, 10h\nsub rdx, 1\nadd rax, rdx\nmov esi, 10h\nmov edx, 0\ndiv rsi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11E3:\ncmp rsp, rdx\njz short loc_11FA\nsub rsp, 1000h\nor [rsp+1050h+var_58], 0\njmp short loc_11E3\nloc_11FA:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1224\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1224:\nmov rax, rsp\nadd rax, 0\nmov [rbp+var_20], rax\nmov [rbp+var_3C], 0\njmp short loc_1249\nloc_1238:\nmov rdx, [rbp+var_20]\nmov eax, [rbp+var_3C]\ncdqe\nmov byte ptr [rdx+rax], 0\nadd [rbp+var_3C], 1\nloc_1249:\nmov eax, [rbp+var_3C]\ncmp eax, [rbp+var_50]\njl short loc_1238\nmov [rbp+var_38], 0\njmp loc_1409\nloc_125D:\nmov rax, rsp\nmov rsi, rax\nmov rax, [rbp+var_20]\nmovzx eax, byte ptr [rax]\ntest al, al\njz short loc_127B\nmov eax, 1\nmov rsp, rsi\njmp loc_141C\nloc_127B:\nmov eax, [rbp+var_50]\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nmov edx, 10h\nsub rdx, 1\nadd rax, rdx\nmov ecx, 10h\nmov edx, 0\ndiv rcx\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_12B8:\ncmp rsp, rdx\njz short loc_12CF\nsub rsp, 1000h\nor [rsp+1050h+var_58], 0\njmp short loc_12B8\nloc_12CF:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_12F9\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_12F9:\nmov rax, rsp\nadd rax, 0\nmov [rbp+var_10], rax\nmov [rbp+var_34], 0\njmp short loc_131E\nloc_130D:\nmov rdx, [rbp+var_10]\nmov eax, [rbp+var_34]\ncdqe\nmov byte ptr [rdx+rax], 0\nadd [rbp+var_34], 1\nloc_131E:\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_50]\njl short loc_130D\nmov [rbp+var_30], 0\njmp short loc_13A1\nloc_132F:\nmov rdx, [rbp+var_20]\nmov eax, [rbp+var_30]\ncdqe\nmovzx eax, byte ptr [rdx+rax]\ntest al, al\njz short loc_139D\nmov eax, [rbp+var_38]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_30]\nadd eax, edx\ncdq\nidiv [rbp+var_50]\nmov eax, edx\nmov rdx, [rbp+var_20]\ncdqe\nmovzx eax, byte ptr [rdx+rax]\nxor eax, 1\ntest al, al\njz short loc_139D\nmov eax, [rbp+var_38]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_30]\nadd eax, edx\ncdq\nidiv [rbp+var_50]\nmov eax, edx\nmov rdx, [rbp+var_10]\ncdqe\nmov byte ptr [rdx+rax], 1\nloc_139D:\nadd [rbp+var_30], 1\nloc_13A1:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_50]\njl short loc_132F\nmov [rbp+var_2C], 0\njmp short loc_13D4\nloc_13B2:\nmov rdx, [rbp+var_10]\nmov eax, [rbp+var_2C]\ncdqe\nmovzx eax, byte ptr [rdx+rax]\ntest al, al\njz short loc_13D0\nmov rdx, [rbp+var_20]\nmov eax, [rbp+var_2C]\ncdqe\nmov byte ptr [rdx+rax], 1\nloc_13D0:\nadd [rbp+var_2C], 1\nloc_13D4:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_50]\njl short loc_13B2\nmov eax, [rbp+var_38]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax]\ncdq\nidiv [rbp+var_50]\nmov eax, edx\nmov rdx, [rbp+var_20]\ncdqe\nmov byte ptr [rdx+rax], 1\nmov rsp, rsi\nadd [rbp+var_38], 1\nloc_1409:\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_4C]\njl loc_125D\nmov rax, [rbp+var_20]\nmovzx eax, byte ptr [rax]\nloc_141C:\nmov rsp, rdi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1433\ncall ___stack_chk_fail\nlocret_1433:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n unsigned __int64 v4; // rax\n void *v5; // rsp\n unsigned __int64 v6; // rax\n void *v7; // rsp\n int v8; // [rsp+8h] [rbp-50h] BYREF\n int v9; // [rsp+Ch] [rbp-4Ch]\n __int64 v10; // [rsp+10h] [rbp-48h]\n int i; // [rsp+1Ch] [rbp-3Ch]\n int j; // [rsp+20h] [rbp-38h]\n int k; // [rsp+24h] [rbp-34h]\n int m; // [rsp+28h] [rbp-30h]\n int n; // [rsp+2Ch] [rbp-2Ch]\n __int64 v16; // [rsp+30h] [rbp-28h]\n unsigned __int8 *v17; // [rsp+38h] [rbp-20h]\n __int64 v18; // [rsp+40h] [rbp-18h]\n int *v19; // [rsp+48h] [rbp-10h]\n unsigned __int64 v20; // [rsp+50h] [rbp-8h]\n\n v10 = a1;\n v9 = a2;\n v8 = a3;\n v20 = __readfsqword(0x28u);\n if ( a2 > a3 )\n return 1LL;\n v16 = v8 - 1LL;\n v4 = 16 * ((v8 + 15LL) / 0x10uLL);\n while ( &v8 != (int *)((char *)&v8 - (v4 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v5 = alloca(v4 & 0xFFF);\n if ( (v4 & 0xFFF) != 0 )\n *(_QWORD *)((char *)&v8 + (v4 & 0xFFF) - 8) = *(_QWORD *)((char *)&v8 + (v4 & 0xFFF) - 8);\n v17 = (unsigned __int8 *)&v8;\n for ( i = 0; i < v8; ++i )\n v17[i] = 0;\n for ( j = 0; j < v9; ++j )\n {\n if ( *v17 )\n return 1LL;\n v18 = v8 - 1LL;\n v6 = 16 * ((v8 + 15LL) / 0x10uLL);\n while ( &v8 != (int *)((char *)&v8 - (v6 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v7 = alloca(v6 & 0xFFF);\n if ( (v6 & 0xFFF) != 0 )\n *(_QWORD *)((char *)&v8 + (v6 & 0xFFF) - 8) = *(_QWORD *)((char *)&v8 + (v6 & 0xFFF) - 8);\n v19 = &v8;\n for ( k = 0; k < v8; ++k )\n *((_BYTE *)v19 + k) = 0;\n for ( m = 0; m < v8; ++m )\n {\n if ( v17[m] && v17[(*(_DWORD *)(4LL * j + v10) + m) % v8] != 1 )\n *((_BYTE *)v19 + (*(_DWORD *)(4LL * j + v10) + m) % v8) = 1;\n }\n for ( n = 0; n < v8; ++n )\n {\n if ( *((_BYTE *)v19 + n) )\n v17[n] = 1;\n }\n v17[*(_DWORD *)(4LL * j + v10) % v8] = 1;\n }\n return *v17;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+var_48], rdi\nmov [rbp+var_4C], esi\nmov [rbp+var_50], edx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rdi, rax\nmov eax, [rbp+var_4C]\ncmp eax, [rbp+var_50]\njle short loc_11A6\nmov eax, 1\njmp loc_141C\nloc_11A6:\nmov eax, [rbp+var_50]\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_28], rdx\ncdqe\nmov edx, 10h\nsub rdx, 1\nadd rax, rdx\nmov esi, 10h\nmov edx, 0\ndiv rsi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11E3:\ncmp rsp, rdx\njz short loc_11FA\nsub rsp, 1000h\nor [rsp+1050h+var_58], 0\njmp short loc_11E3\nloc_11FA:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1224\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1224:\nmov rax, rsp\nadd rax, 0\nmov [rbp+var_20], rax\nmov [rbp+var_3C], 0\njmp short loc_1249\nloc_1238:\nmov rdx, [rbp+var_20]\nmov eax, [rbp+var_3C]\ncdqe\nmov byte ptr [rdx+rax], 0\nadd [rbp+var_3C], 1\nloc_1249:\nmov eax, [rbp+var_3C]\ncmp eax, [rbp+var_50]\njl short loc_1238\nmov [rbp+var_38], 0\njmp loc_1409\nloc_125D:\nmov rax, rsp\nmov rsi, rax\nmov rax, [rbp+var_20]\nmovzx eax, byte ptr [rax]\ntest al, al\njz short loc_127B\nmov eax, 1\nmov rsp, rsi\njmp loc_141C\nloc_127B:\nmov eax, [rbp+var_50]\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nmov edx, 10h\nsub rdx, 1\nadd rax, rdx\nmov ecx, 10h\nmov edx, 0\ndiv rcx\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_12B8:\ncmp rsp, rdx\njz short loc_12CF\nsub rsp, 1000h\nor [rsp+1050h+var_58], 0\njmp short loc_12B8\nloc_12CF:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_12F9\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_12F9:\nmov rax, rsp\nadd rax, 0\nmov [rbp+var_10], rax\nmov [rbp+var_34], 0\njmp short loc_131E\nloc_130D:\nmov rdx, [rbp+var_10]\nmov eax, [rbp+var_34]\ncdqe\nmov byte ptr [rdx+rax], 0\nadd [rbp+var_34], 1\nloc_131E:\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_50]\njl short loc_130D\nmov [rbp+var_30], 0\njmp short loc_13A1\nloc_132F:\nmov rdx, [rbp+var_20]\nmov eax, [rbp+var_30]\ncdqe\nmovzx eax, byte ptr [rdx+rax]\ntest al, al\njz short loc_139D\nmov eax, [rbp+var_38]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_30]\nadd eax, edx\ncdq\nidiv [rbp+var_50]\nmov eax, edx\nmov rdx, [rbp+var_20]\ncdqe\nmovzx eax, byte ptr [rdx+rax]\nxor eax, 1\ntest al, al\njz short loc_139D\nmov eax, [rbp+var_38]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_30]\nadd eax, edx\ncdq\nidiv [rbp+var_50]\nmov eax, edx\nmov rdx, [rbp+var_10]\ncdqe\nmov byte ptr [rdx+rax], 1\nloc_139D:\nadd [rbp+var_30], 1\nloc_13A1:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_50]\njl short loc_132F\nmov [rbp+var_2C], 0\njmp short loc_13D4\nloc_13B2:\nmov rdx, [rbp+var_10]\nmov eax, [rbp+var_2C]\ncdqe\nmovzx eax, byte ptr [rdx+rax]\ntest al, al\njz short loc_13D0\nmov rdx, [rbp+var_20]\nmov eax, [rbp+var_2C]\ncdqe\nmov byte ptr [rdx+rax], 1\nloc_13D0:\nadd [rbp+var_2C], 1\nloc_13D4:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_50]\njl short loc_13B2\nmov eax, [rbp+var_38]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax]\ncdq\nidiv [rbp+var_50]\nmov eax, edx\nmov rdx, [rbp+var_20]\ncdqe\nmov byte ptr [rdx+rax], 1\nmov rsp, rsi\nadd [rbp+var_38], 1\nloc_1409:\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_4C]\njl loc_125D\nmov rax, [rbp+var_20]\nmovzx eax, byte ptr [rax]\nloc_141C:\nmov rsp, rdi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1433\ncall ___stack_chk_fail\nlocret_1433:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n unsigned __int64 v4; // rax\n void *v5; // rsp\n unsigned __int64 v6; // rax\n void *v7; // rsp\n int v8; // [rsp+8h] [rbp-50h] BYREF\n int v9; // [rsp+Ch] [rbp-4Ch]\n __int64 v10; // [rsp+10h] [rbp-48h]\n int i; // [rsp+1Ch] [rbp-3Ch]\n int j; // [rsp+20h] [rbp-38h]\n int k; // [rsp+24h] [rbp-34h]\n int m; // [rsp+28h] [rbp-30h]\n int n; // [rsp+2Ch] [rbp-2Ch]\n __int64 v16; // [rsp+30h] [rbp-28h]\n unsigned __int8 *v17; // [rsp+38h] [rbp-20h]\n __int64 v18; // [rsp+40h] [rbp-18h]\n int *v19; // [rsp+48h] [rbp-10h]\n unsigned __int64 v20; // [rsp+50h] [rbp-8h]\n\n v10 = a1;\n v9 = a2;\n v8 = a3;\n v20 = __readfsqword(0x28u);\n if ( a2 > a3 )\n return 1LL;\n v16 = v8 - 1LL;\n v4 = 16 * ((v8 + 15LL) / 0x10uLL);\n while ( &v8 != (int *)((char *)&v8 - (v4 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v5 = alloca(v4 & 0xFFF);\n if ( (v4 & 0xFFF) != 0 )\n *(_QWORD *)((char *)&v8 + (v4 & 0xFFF) - 8) = *(_QWORD *)((char *)&v8 + (v4 & 0xFFF) - 8);\n v17 = (unsigned __int8 *)&v8;\n for ( i = 0; i < v8; ++i )\n v17[i] = 0;\n for ( j = 0; j < v9; ++j )\n {\n if ( *v17 )\n return 1LL;\n v18 = v8 - 1LL;\n v6 = 16 * ((v8 + 15LL) / 0x10uLL);\n while ( &v8 != (int *)((char *)&v8 - (v6 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v7 = alloca(v6 & 0xFFF);\n if ( (v6 & 0xFFF) != 0 )\n *(_QWORD *)((char *)&v8 + (v6 & 0xFFF) - 8) = *(_QWORD *)((char *)&v8 + (v6 & 0xFFF) - 8);\n v19 = &v8;\n for ( k = 0; k < v8; ++k )\n *((_BYTE *)v19 + k) = 0;\n for ( m = 0; m < v8; ++m )\n {\n if ( v17[m] && v17[(*(_DWORD *)(4LL * j + v10) + m) % v8] != 1 )\n *((_BYTE *)v19 + (*(_DWORD *)(4LL * j + v10) + m) % v8) = 1;\n }\n for ( n = 0; n < v8; ++n )\n {\n if ( *((_BYTE *)v19 + n) )\n v17[n] = 1;\n }\n v17[*(_DWORD *)(4LL * j + v10) % v8] = 1;\n }\n return *v17;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n unsigned long long v4;\n void *v5;\n unsigned long long v6;\n void *v7;\n int v8;\n int v9;\n long long v10;\n int i;\n int j;\n int k;\n int m;\n int n;\n long long v16;\n unsigned char *v17;\n long long v18;\n int *v19;\n unsigned long long v20;\n v10 = a1;\n v9 = a2;\n v8 = a3;\n v20 = __readfsqword(40u);\n if (a2 > a3) return 1LL;\n v16 = v8 - 1LL;\n v4 = 16 * ((v8 + 15LL) / 16uLL);\n while (&v8 != (int *)((char *)&v8 - (v4 & 18446744073709547520LL)))\n ;\n v5 = alloca(v4 & 4095);\n if ((v4 & 4095) != 0)\n *(uint64_t *)((char *)&v8 + (v4 & 4095) - 8) =\n *(uint64_t *)((char *)&v8 + (v4 & 4095) - 8);\n v17 = (unsigned char *)&v8;\n for (i = 0; i < v8; ++i) v17[i] = 0;\n for (j = 0; j < v9; ++j) {\n if (*v17) return 1LL;\n v18 = v8 - 1LL;\n v6 = 16 * ((v8 + 15LL) / 16uLL);\n while (&v8 != (int *)((char *)&v8 - (v6 & 18446744073709547520LL)))\n ;\n v7 = alloca(v6 & 4095);\n if ((v6 & 4095) != 0)\n *(uint64_t *)((char *)&v8 + (v6 & 4095) - 8) =\n *(uint64_t *)((char *)&v8 + (v6 & 4095) - 8);\n v19 = &v8;\n for (k = 0; k < v8; ++k) *((uint8_t *)v19 + k) = 0;\n for (m = 0; m < v8; ++m) {\n if (v17[m] && v17[(*(uint32_t *)(4LL * j + v10) + m) % v8] != 1)\n *((uint8_t *)v19 + (*(uint32_t *)(4LL * j + v10) + m) % v8) = 1;\n }\n for (n = 0; n < v8; ++n) {\n if (*((uint8_t *)v19 + n)) v17[n] = 1;\n }\n v17[*(uint32_t *)(4LL * j + v10) % v8] = 1;\n }\n return *v17;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n unsigned long long v4;\n void *v5;\n unsigned long long v6;\n void *v7;\n int v8;\n int v9;\n long long v10;\n int i;\n int j;\n int k;\n int m;\n int n;\n long long v16;\n unsigned char *v17;\n long long v18;\n int *v19;\n unsigned long long v20;\n v10 = a1;\n v9 = a2;\n v8 = a3;\n v20 = __readfsqword(40u);\n if (a2 > a3) return 1LL;\n v16 = v8 - 1LL;\n v4 = 16 * ((v8 + 15LL) / 16uLL);\n while (&v8 != (int *)((char *)&v8 - (v4 & 18446744073709547520LL)))\n ;\n v5 = alloca(v4 & 4095);\n if ((v4 & 4095) != 0)\n *(uint64_t *)((char *)&v8 + (v4 & 4095) - 8) =\n *(uint64_t *)((char *)&v8 + (v4 & 4095) - 8);\n v17 = (unsigned char *)&v8;\n for (i = 0; i < v8; ++i) v17[i] = 0;\n for (j = 0; j < v9; ++j) {\n if (*v17) return 1LL;\n v18 = v8 - 1LL;\n v6 = 16 * ((v8 + 15LL) / 16uLL);\n while (&v8 != (int *)((char *)&v8 - (v6 & 18446744073709547520LL)))\n ;\n v7 = alloca(v6 & 4095);\n if ((v6 & 4095) != 0)\n *(uint64_t *)((char *)&v8 + (v6 & 4095) - 8) =\n *(uint64_t *)((char *)&v8 + (v6 & 4095) - 8);\n v19 = &v8;\n for (k = 0; k < v8; ++k) *((uint8_t *)v19 + k) = 0;\n for (m = 0; m < v8; ++m) {\n if (v17[m] && v17[(*(uint32_t *)(4LL * j + v10) + m) % v8] != 1)\n *((uint8_t *)v19 + (*(uint32_t *)(4LL * j + v10) + m) % v8) = 1;\n }\n for (n = 0; n < v8; ++n) {\n if (*((uint8_t *)v19 + n)) v17[n] = 1;\n }\n v17[*(uint32_t *)(4LL * j + v10) % v8] = 1;\n }\n return *v17;\n}" + }, + { + "index": 515, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int arr[], int n, int m) {\n if (n > m) {\n return true;\n }\n bool DP[m];\n for (int i = 0; i < m; i++) {\n DP[i] = false;\n }\n for (int i = 0; i < n; i++) {\n if (DP[0]) {\n return true;\n }\n bool temp[m];\n for (int k = 0; k < m; k++) {\n temp[k] = false;\n }\n for (int j = 0; j < m; j++) {\n if (DP[j]) {\n if (!DP[(j + arr[i]) % m]) {\n temp[(j + arr[i]) % m] = true;\n }\n }\n }\n for (int j = 0; j < m; j++) {\n if (temp[j]) {\n DP[j] = true;\n }\n }\n DP[arr[i] % m] = true;\n }\n return DP[0];\n}", + "test": "int main() {\n\n int arr1[] = {3, 1, 7, 5};\n\n int arr2[] = {1, 7};\n\n int arr3[] = {1, 6};\n\n\n\n assert(func0(arr1, 4, 6) == true);\n\n assert(func0(arr2, 2, 5) == false);\n\n assert(func0(arr3, 2, 5) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0x18,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nmov $0x1,%eax\ncmp %edx,%esi\njg 1326 \nmov %edx,%r8d\nmovslq %edx,%r10\nlea 0xf(%r10),%rax\nmov %rax,%rdx\nand $0xfffffffffffffff0,%rdx\nand $0xfffffffffffff000,%rax\nmov %rsp,%rbx\nsub %rax,%rbx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 11d1 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11ba \nmov %rdx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 11e7 \norq $0x0,-0x8(%rsp,%rax,1)\nmov %rsp,%rcx\ntest %r8d,%r8d\njle 1207 \nmov %rcx,%rax\nlea -0x1(%r8),%edx\nlea 0x1(%rcx,%rdx,1),%rdx\nmovb $0x0,(%rax)\nadd $0x1,%rax\ncmp %rdx,%rax\njne 11fb \ntest %esi,%esi\njle 1323 \nmov %rdi,%r9\nlea -0x1(%rsi),%eax\nlea 0x4(%rdi,%rax,4),%r13\nmov $0x10,%ebx\nadd $0xf,%r10\nlea -0x1(%r8),%esi\nlea 0x1(%rsi),%r14\nmov $0x0,%r12d\njmpq 12d8 \nmov %r11,%rsp\njmpq 1326 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\nje 1255 \norq $0x0,-0x8(%rsp,%rdx,1)\nmov %rsp,%rdi\ntest %r8d,%r8d\njle 12be \nmov %rdi,%rax\nlea (%r14,%rdi,1),%rdx\nmovb $0x0,(%rax)\nadd $0x1,%rax\ncmp %rdx,%rax\njne 1264 \nmov %r12,%r15\njmp 1281 \nlea 0x1(%r15),%rax\ncmp %rsi,%r15\nje 12a1 \nmov %rax,%r15\ncmpb $0x0,(%rcx,%r15,1)\nje 1275 \nmov %r15d,%eax\nadd (%r9),%eax\ncltd\nidiv %r8d\nmovslq %edx,%rax\ncmpb $0x0,(%rcx,%rax,1)\njne 1275 \nmovb $0x1,(%rdi,%rax,1)\njmp 1275 \nmov %r12,%rax\njmp 12b2 \nlea 0x1(%rax),%rdx\ncmp %rsi,%rax\nje 12be \nmov %rdx,%rax\ncmpb $0x0,(%rdi,%rax,1)\nje 12a6 \nmovb $0x1,(%rcx,%rax,1)\njmp 12a6 \nmov (%r9),%eax\ncltd\nidiv %r8d\nmovslq %edx,%rdx\nmovb $0x1,(%rcx,%rdx,1)\nmov %r11,%rsp\nadd $0x4,%r9\ncmp %r13,%r9\nje 1323 \nmov %rsp,%r11\nmovzbl (%rcx),%eax\ntest %al,%al\njne 1236 \nmov %r10,%rax\nmov $0x0,%edx\ndiv %rbx\nshl $0x4,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rdi\nsub %rdx,%rdi\nmov %rdi,%rdx\ncmp %rdx,%rsp\nje 123e \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 1308 \nmovzbl (%rcx),%eax\nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\njne 1344 \nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nmov eax, 1\ncmp esi, edx\njg loc_1311\nmov ecx, esi\nmov r8d, edx\nmovsxd r9, edx\nlea rax, [r9+0Fh]\nmov rsi, rax\nand rsi, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11B7:\ncmp rsp, rdx\njz short loc_11CE\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\njmp short loc_11B7\nloc_11CE:\nmov rax, rsi\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11E4\nor [rsp+rax+30h+var_38], 0\nloc_11E4:\nmov rsi, rsp\ntest r8d, r8d\njle short loc_11FF\nmov rax, rsi\nlea rdx, [r9+rsi]\nloc_11F3:\nmov byte ptr [rax], 0\nadd rax, 1\ncmp rax, rdx\njnz short loc_11F3\nloc_11FF:\ntest ecx, ecx\njle loc_130E\nmov r10, rdi\nmovsxd rcx, ecx\nlea r14, [rdi+rcx*4]\nmov r12d, 10h\nlea rbx, [r9+0Fh]\nmov r13d, 0\njmp loc_12C6\nloc_1226:\nmov rsp, r11\njmp loc_1311\nloc_122E:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njz short loc_1245\nor [rsp+rdx+30h+var_38], 0\nloc_1245:\nmov rdi, rsp\ntest r8d, r8d\njle short loc_12AC\nmov rax, rdi\nlea rdx, [r9+rdi]\nloc_1254:\nmov byte ptr [rax], 0\nadd rax, 1\ncmp rdx, rax\njnz short loc_1254\nmov rcx, r13\njmp short loc_1271\nloc_1265:\nlea rax, [rcx+1]\ncmp r9, rax\njz short loc_128F\nmov rcx, rax\nloc_1271:\ncmp byte ptr [rsi+rcx], 0\njz short loc_1265\nmov eax, ecx\nadd eax, [r10]\ncdq\nidiv r8d\nmovsxd rax, edx\ncmp byte ptr [rsi+rax], 0\njnz short loc_1265\nmov byte ptr [rdi+rax], 1\njmp short loc_1265\nloc_128F:\nmov rax, r13\njmp short loc_12A0\nloc_1294:\nlea rdx, [rax+1]\ncmp rax, rcx\njz short loc_12AC\nmov rax, rdx\nloc_12A0:\ncmp byte ptr [rdi+rax], 0\njz short loc_1294\nmov byte ptr [rsi+rax], 1\njmp short loc_1294\nloc_12AC:\nmov eax, [r10]\ncdq\nidiv r8d\nmovsxd rdx, edx\nmov byte ptr [rsi+rdx], 1\nmov rsp, r11\nadd r10, 4\ncmp r10, r14\njz short loc_130E\nloc_12C6:\nmov r11, rsp\nmovzx eax, byte ptr [rsi]\ntest al, al\njnz loc_1226\nmov rax, rbx\nmov edx, 0\ndiv r12\nshl rax, 4\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_12F3:\ncmp rsp, rdx\njz loc_122E\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\njmp short loc_12F3\nloc_130E:\nmovzx eax, byte ptr [rsi]\nloc_1311:\nmov rdx, [rbp+var_28]\nsub rdx, fs:28h\njnz short loc_132D\nlea rsp, [rbp-20h]\npop rbx\npop r12\npop r13\npop r14\npop rbp\nretn\nloc_132D:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2, int a3)\n{\n __int64 result; // rax\n __int64 v6; // r9\n __int16 v7; // si\n _BYTE *v8; // rdx\n signed __int64 v9; // rax\n void *v10; // rsp\n _BYTE *v11; // rax\n _DWORD *v12; // r10\n _DWORD *v13; // r14\n signed __int64 v14; // rdx\n void *v15; // rsp\n _BYTE *v16; // rax\n __int64 i; // rcx\n int v18; // edx\n __int64 j; // rax\n unsigned __int64 v20; // rax\n _BYTE v22[8]; // [rsp+8h] [rbp-30h] BYREF\n unsigned __int64 v23; // [rsp+10h] [rbp-28h]\n\n v23 = __readfsqword(0x28u);\n result = 1LL;\n if ( a2 <= a3 )\n {\n v6 = a3;\n v7 = (a3 + 15) & 0xFFF0;\n v8 = &v22[-((a3 + 15LL) & 0xFFFFFFFFFFFFF000LL)];\n while ( v22 != v8 )\n ;\n v9 = v7 & 0xFFF;\n v10 = alloca(v9);\n if ( (v7 & 0xFFF) != 0 )\n *(_QWORD *)&v22[v9 - 8] = *(_QWORD *)&v22[v9 - 8];\n if ( a3 > 0 )\n {\n v11 = v22;\n do\n *v11++ = 0;\n while ( v11 != &v22[v6] );\n }\n if ( a2 <= 0 )\n {\n return v22[0];\n }\n else\n {\n v12 = a1;\n v13 = &a1[a2];\n while ( 1 )\n {\n result = v22[0];\n if ( v22[0] )\n break;\n v20 = 16 * ((v6 + 15) / 0x10uLL);\n while ( v22 != &v22[-(v20 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v14 = v20 & 0xFFF;\n v15 = alloca(v14);\n if ( (v20 & 0xFFF) != 0 )\n *(_QWORD *)&v22[v14 - 8] = *(_QWORD *)&v22[v14 - 8];\n if ( a3 > 0 )\n {\n v16 = v22;\n do\n *v16++ = 0;\n while ( &v22[v6] != v16 );\n for ( i = 0LL; ; ++i )\n {\n if ( v22[i] )\n {\n v18 = (*v12 + (int)i) % a3;\n if ( !v22[v18] )\n v22[v18] = 1;\n }\n if ( v6 == i + 1 )\n break;\n }\n for ( j = 0LL; ; ++j )\n {\n if ( v22[j] )\n v22[j] = 1;\n if ( j == i )\n break;\n }\n }\n v22[*v12++ % a3] = 1;\n if ( v12 == v13 )\n return v22[0];\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nmov eax, 1\ncmp esi, edx\njg loc_1311\nmov ecx, esi\nmov r8d, edx\nmovsxd r9, edx\nlea rax, [r9+0Fh]\nmov rsi, rax\nand rsi, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11B7:\ncmp rsp, rdx\njz short loc_11CE\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\njmp short loc_11B7\nloc_11CE:\nmov rax, rsi\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11E4\nor [rsp+rax+30h+var_38], 0\nloc_11E4:\nmov rsi, rsp\ntest r8d, r8d\njle short loc_11FF\nmov rax, rsi\nlea rdx, [r9+rsi]\nloc_11F3:\nmov byte ptr [rax], 0\nadd rax, 1\ncmp rax, rdx\njnz short loc_11F3\nloc_11FF:\ntest ecx, ecx\njle loc_130E\nmov r10, rdi\nmovsxd rcx, ecx\nlea r14, [rdi+rcx*4]\nmov r12d, 10h\nlea rbx, [r9+0Fh]\nmov r13d, 0\njmp loc_12C6\nloc_1226:\nmov rsp, r11\njmp loc_1311\nloc_122E:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njz short loc_1245\nor [rsp+rdx+30h+var_38], 0\nloc_1245:\nmov rdi, rsp\ntest r8d, r8d\njle short loc_12AC\nmov rax, rdi\nlea rdx, [r9+rdi]\nloc_1254:\nmov byte ptr [rax], 0\nadd rax, 1\ncmp rdx, rax\njnz short loc_1254\nmov rcx, r13\njmp short loc_1271\nloc_1265:\nlea rax, [rcx+1]\ncmp r9, rax\njz short loc_128F\nmov rcx, rax\nloc_1271:\ncmp byte ptr [rsi+rcx], 0\njz short loc_1265\nmov eax, ecx\nadd eax, [r10]\ncdq\nidiv r8d\nmovsxd rax, edx\ncmp byte ptr [rsi+rax], 0\njnz short loc_1265\nmov byte ptr [rdi+rax], 1\njmp short loc_1265\nloc_128F:\nmov rax, r13\njmp short loc_12A0\nloc_1294:\nlea rdx, [rax+1]\ncmp rax, rcx\njz short loc_12AC\nmov rax, rdx\nloc_12A0:\ncmp byte ptr [rdi+rax], 0\njz short loc_1294\nmov byte ptr [rsi+rax], 1\njmp short loc_1294\nloc_12AC:\nmov eax, [r10]\ncdq\nidiv r8d\nmovsxd rdx, edx\nmov byte ptr [rsi+rdx], 1\nmov rsp, r11\nadd r10, 4\ncmp r10, r14\njz short loc_130E\nloc_12C6:\nmov r11, rsp\nmovzx eax, byte ptr [rsi]\ntest al, al\njnz loc_1226\nmov rax, rbx\nmov edx, 0\ndiv r12\nshl rax, 4\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_12F3:\ncmp rsp, rdx\njz loc_122E\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\njmp short loc_12F3\nloc_130E:\nmovzx eax, byte ptr [rsi]\nloc_1311:\nmov rdx, [rbp+var_28]\nsub rdx, fs:28h\njnz short loc_132D\nlea rsp, [rbp-20h]\npop rbx\npop r12\npop r13\npop r14\npop rbp\nretn\nloc_132D:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2, int a3)\n{\n __int64 result; // rax\n __int64 v6; // r9\n __int16 v7; // si\n _BYTE *v8; // rdx\n signed __int64 v9; // rax\n void *v10; // rsp\n _BYTE *v11; // rax\n _DWORD *v12; // r10\n _DWORD *v13; // r14\n signed __int64 v14; // rdx\n void *v15; // rsp\n _BYTE *v16; // rax\n __int64 i; // rcx\n int v18; // edx\n __int64 j; // rax\n unsigned __int64 v20; // rax\n _BYTE v22[8]; // [rsp+8h] [rbp-30h] BYREF\n unsigned __int64 v23; // [rsp+10h] [rbp-28h]\n\n v23 = __readfsqword(0x28u);\n result = 1LL;\n if ( a2 <= a3 )\n {\n v6 = a3;\n v7 = (a3 + 15) & 0xFFF0;\n v8 = &v22[-((a3 + 15LL) & 0xFFFFFFFFFFFFF000LL)];\n while ( v22 != v8 )\n ;\n v9 = v7 & 0xFFF;\n v10 = alloca(v9);\n if ( (v7 & 0xFFF) != 0 )\n *(_QWORD *)&v22[v9 - 8] = *(_QWORD *)&v22[v9 - 8];\n if ( a3 > 0 )\n {\n v11 = v22;\n do\n *v11++ = 0;\n while ( v11 != &v22[v6] );\n }\n if ( a2 <= 0 )\n {\n return v22[0];\n }\n else\n {\n v12 = a1;\n v13 = &a1[a2];\n while ( 1 )\n {\n result = v22[0];\n if ( v22[0] )\n break;\n v20 = 16 * ((v6 + 15) / 0x10uLL);\n while ( v22 != &v22[-(v20 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v14 = v20 & 0xFFF;\n v15 = alloca(v14);\n if ( (v20 & 0xFFF) != 0 )\n *(_QWORD *)&v22[v14 - 8] = *(_QWORD *)&v22[v14 - 8];\n if ( a3 > 0 )\n {\n v16 = v22;\n do\n *v16++ = 0;\n while ( &v22[v6] != v16 );\n for ( i = 0LL; ; ++i )\n {\n if ( v22[i] )\n {\n v18 = (*v12 + (int)i) % a3;\n if ( !v22[v18] )\n v22[v18] = 1;\n }\n if ( v6 == i + 1 )\n break;\n }\n for ( j = 0LL; ; ++j )\n {\n if ( v22[j] )\n v22[j] = 1;\n if ( j == i )\n break;\n }\n }\n v22[*v12++ % a3] = 1;\n if ( v12 == v13 )\n return v22[0];\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2, int a3) {\n long long result;\n long long v6;\n short v7;\n uint8_t *v8;\n signed long long v9;\n void *v10;\n uint8_t *v11;\n uint32_t *v12;\n uint32_t *v13;\n signed long long v14;\n void *v15;\n uint8_t *v16;\n long long i;\n int v18;\n long long j;\n unsigned long long v20;\n uint8_t v22[8];\n unsigned long long v23;\n v23 = __readfsqword(40u);\n result = 1LL;\n if (a2 <= a3) {\n v6 = a3;\n v7 = (a3 + 15) & 65520;\n v8 = &v22[-((a3 + 15LL) & 18446744073709547520LL)];\n while (v22 != v8)\n ;\n v9 = v7 & 4095;\n v10 = alloca(v9);\n if ((v7 & 4095) != 0) *(uint64_t *)&v22[v9 - 8] = *(uint64_t *)&v22[v9 - 8];\n if (a3 > 0) {\n v11 = v22;\n do\n *v11++ = 0;\n while (v11 != &v22[v6]);\n }\n if (a2 <= 0) {\n return v22[0];\n } else {\n v12 = a1;\n v13 = &a1[a2];\n while (1) {\n result = v22[0];\n if (v22[0]) break;\n v20 = 16 * ((v6 + 15) / 16uLL);\n while (v22 != &v22[-(v20 & 18446744073709547520LL)])\n ;\n v14 = v20 & 4095;\n v15 = alloca(v14);\n if ((v20 & 4095) != 0)\n *(uint64_t *)&v22[v14 - 8] = *(uint64_t *)&v22[v14 - 8];\n if (a3 > 0) {\n v16 = v22;\n do\n *v16++ = 0;\n while (&v22[v6] != v16);\n for (i = 0LL;; ++i) {\n if (v22[i]) {\n v18 = (*v12 + (int)i) % a3;\n if (!v22[v18]) v22[v18] = 1;\n }\n if (v6 == i + 1) break;\n }\n for (j = 0LL;; ++j) {\n if (v22[j]) v22[j] = 1;\n if (j == i) break;\n }\n }\n v22[*v12++ % a3] = 1;\n if (v12 == v13) return v22[0];\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2, int a3) {\n long long result;\n long long v6;\n short v7;\n uint8_t *v8;\n signed long long v9;\n void *v10;\n uint8_t *v11;\n uint32_t *v12;\n uint32_t *v13;\n signed long long v14;\n void *v15;\n uint8_t *v16;\n long long i;\n int v18;\n long long j;\n unsigned long long v20;\n uint8_t v22[8];\n unsigned long long v23;\n v23 = __readfsqword(40u);\n result = 1LL;\n if (a2 <= a3) {\n v6 = a3;\n v7 = (a3 + 15) & 65520;\n v8 = &v22[-((a3 + 15LL) & 18446744073709547520LL)];\n while (v22 != v8)\n ;\n v9 = v7 & 4095;\n v10 = alloca(v9);\n if ((v7 & 4095) != 0) *(uint64_t *)&v22[v9 - 8] = *(uint64_t *)&v22[v9 - 8];\n if (a3 > 0) {\n v11 = v22;\n do\n *v11++ = 0;\n while (v11 != &v22[v6]);\n }\n if (a2 <= 0) {\n return v22[0];\n } else {\n v12 = a1;\n v13 = &a1[a2];\n while (1) {\n result = v22[0];\n if (v22[0]) break;\n v20 = 16 * ((v6 + 15) / 16uLL);\n while (v22 != &v22[-(v20 & 18446744073709547520LL)])\n ;\n v14 = v20 & 4095;\n v15 = alloca(v14);\n if ((v20 & 4095) != 0)\n *(uint64_t *)&v22[v14 - 8] = *(uint64_t *)&v22[v14 - 8];\n if (a3 > 0) {\n v16 = v22;\n do\n *v16++ = 0;\n while (&v22[v6] != v16);\n for (i = 0LL;; ++i) {\n if (v22[i]) {\n v18 = (*v12 + (int)i) % a3;\n if (!v22[v18]) v22[v18] = 1;\n }\n if (v6 == i + 1) break;\n }\n for (j = 0LL;; ++j) {\n if (v22[j]) v22[j] = 1;\n if (j == i) break;\n }\n }\n v22[*v12++ % a3] = 1;\n if (v12 == v13) return v22[0];\n }\n }\n }\n return result;\n}" + }, + { + "index": 515, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int arr[], int n, int m) {\n if (n > m) {\n return true;\n }\n bool DP[m];\n for (int i = 0; i < m; i++) {\n DP[i] = false;\n }\n for (int i = 0; i < n; i++) {\n if (DP[0]) {\n return true;\n }\n bool temp[m];\n for (int k = 0; k < m; k++) {\n temp[k] = false;\n }\n for (int j = 0; j < m; j++) {\n if (DP[j]) {\n if (!DP[(j + arr[i]) % m]) {\n temp[(j + arr[i]) % m] = true;\n }\n }\n }\n for (int j = 0; j < m; j++) {\n if (temp[j]) {\n DP[j] = true;\n }\n }\n DP[arr[i] % m] = true;\n }\n return DP[0];\n}", + "test": "int main() {\n\n int arr1[] = {3, 1, 7, 5};\n\n int arr2[] = {1, 7};\n\n int arr3[] = {1, 6};\n\n\n\n assert(func0(arr1, 4, 6) == true);\n\n assert(func0(arr2, 2, 5) == false);\n\n assert(func0(arr3, 2, 5) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0x38,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nmov $0x1,%eax\ncmp %edx,%esi\njg 1469 \nmovslq %edx,%rcx\nmov %edx,%r9d\nmov %rsp,%rbx\nadd $0xf,%rcx\nmov %rcx,%rdx\nmov %rcx,%rax\nand $0xfffffffffffff000,%rdx\nand $0xfffffffffffffff0,%rax\nsub %rdx,%rbx\nmov %rbx,%rdx\ncmp %rdx,%rsp\nje 12ff \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rdx,%rsp\njne 12ea \nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 1312 \norq $0x0,-0x8(%rsp,%rax,1)\nmov %rsp,%r8\ntest %r9d,%r9d\njle 133c \nlea -0x1(%r9),%edx\nmov %rsp,%rax\nlea 0x1(%rsp,%rdx,1),%rdx\nnopw %cs:0x0(%rax,%rax,1)\nmovb $0x0,(%rax)\nadd $0x1,%rax\ncmp %rdx,%rax\njne 1330 \ntest %esi,%esi\njle 1465 \nlea -0x1(%rsi),%eax\nmov %rcx,%r14\nand $0xff0,%ecx\nmov %rdi,%r12\nlea 0x4(%rdi,%rax,4),%r15\nlea -0x8(%rcx),%rax\nmov %rcx,-0x48(%rbp)\nand $0xfffffffffffff000,%r14\nlea -0x1(%r9),%edi\nmov %rax,-0x58(%rbp)\nlea 0x1(%rdi),%rax\nlea (%r8,%rdi,1),%r10\nmov %rax,-0x50(%rbp)\nnopl 0x0(%rax,%rax,1)\nmovzbl (%r8),%eax\nmov %rsp,%r13\ntest %al,%al\njne 1469 \nmov %rsp,%rax\nsub %r14,%rax\ncmp %rax,%rsp\nje 13af \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 139a \nmov -0x48(%rbp),%rax\nsub %rax,%rsp\ntest %rax,%rax\nje 13c4 \nmov -0x58(%rbp),%rax\norq $0x0,(%rsp,%rax,1)\nmov -0x50(%rbp),%rcx\nmov (%r12),%ebx\nmov %rsp,%rsi\nmov %rsp,%rax\nlea (%rsp,%rcx,1),%rdx\ntest %r9d,%r9d\njle 1447 \nnopl 0x0(%rax,%rax,1)\nmovb $0x0,(%rax)\nadd $0x1,%rax\ncmp %rdx,%rax\njne 13e0 \nmov %ebx,%r11d\nmov %r8,%rcx\nsub %r8d,%r11d\nnopl (%rax)\ncmp %rcx,%r10\nje 1424 \nmovzbl 0x1(%rcx),%eax\nadd $0x1,%rcx\ntest %al,%al\nje 13f8 \nlea (%r11,%rcx,1),%eax\ncltd\nidiv %r9d\nmovslq %edx,%rdx\ncmpb $0x0,(%r8,%rdx,1)\njne 13f8 \nmovb $0x1,(%rsi,%rdx,1)\ncmp %rcx,%r10\njne 13fd \nxor %eax,%eax\njmp 1433 \nnopl 0x0(%rax,%rax,1)\nmov %rdx,%rax\ncmpb $0x0,(%rsi,%rax,1)\nje 143e \nmovb $0x1,(%r8,%rax,1)\nlea 0x1(%rax),%rdx\ncmp %rdi,%rax\njne 1430 \nmov %ebx,%eax\nadd $0x4,%r12\ncltd\nidiv %r9d\nmovslq %edx,%rdx\nmovb $0x1,(%r8,%rdx,1)\nmov %r13,%rsp\ncmp %r15,%r12\njne 1380 \nmovzbl (%r8),%eax\nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\njne 1487 \nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\ncallq 1060 <__stack_chk_fail@plt>\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nmovsxd rbx, esi\nsub rsp, 48h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\ncmp ebx, edx\njg loc_1450\nmovsxd r12, edx\nmov r15d, edx\nmov rdx, rsp\nmov r13, rdi\nlea rcx, [r12+0Fh]\nmov rsi, rcx\nmov rax, rcx\nand rsi, 0FFFFFFFFFFFFF000h\nand rax, 0FFFFFFFFFFFFFFF0h\nsub rdx, rsi\ncmp rsp, rdx\njz short loc_12FE\nloc_12E9:\nsub rsp, 1000h\nor [rsp+1070h+var_78], 0\ncmp rsp, rdx\njnz short loc_12E9\nloc_12FE:\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_1311\nor [rsp+rax+1070h+var_1078], 0\nloc_1311:\nmov r14, rsp\ntest r15d, r15d\njle short loc_132E\nmov edx, r15d; n\nxor esi, esi; c\nmov rdi, rsp; s\nmov [rbp+var_48], rcx\ncall _memset\nmov rcx, [rbp+var_48]\nloc_132E:\ntest ebx, ebx\njle loc_1448\nlea rax, [r13+rbx*4+0]\nmov [rbp+var_50], rax\nmov rax, rcx\nand ecx, 0FF0h\nand rax, 0FFFFFFFFFFFFFFF0h\nmov [rbp+var_60], rcx\nmov [rbp+var_58], rax\nlea rax, [rcx-8]\nmov [rbp+var_68], rax\nmov rax, r13\nmov r13, r12\nmov r12, rax\nnop dword ptr [rax]\nloc_1368:\ncmp byte ptr [r14], 0\nmov [rbp+var_48], rsp\njnz loc_1450\nmov rdx, [rbp+var_58]\nmov rax, rsp\nand rdx, 0FFFFFFFFFFFFF000h\nsub rax, rdx\ncmp rsp, rax\njz short loc_13A1\nloc_138C:\nsub rsp, 1000h\nor [rsp+2070h+var_1078], 0\ncmp rsp, rax\njnz short loc_138C\nloc_13A1:\nmov rax, [rbp+var_60]\nsub rsp, rax\ntest rax, rax\njz short loc_13B6\nmov rax, [rbp+var_68]\nor [rsp+rax+2070h+var_2070], 0\nloc_13B6:\nmov rbx, rsp\ntest r15d, r15d\njle loc_1473\nxor esi, esi; c\nmov rdi, rsp; s\nmov edx, r15d; n\ncall _memset\nmov r11d, [r12]\nlea rsi, [r13+r14+0]\nmov rcx, r14\nmov edi, r11d\nsub edi, r14d\nnop dword ptr [rax+00000000h]\nloc_13E8:\ncmp byte ptr [rcx], 0\njz short loc_1402\nlea eax, [rdi+rcx]\ncdq\nidiv r15d\nmovsxd rdx, edx\ncmp byte ptr [r14+rdx], 0\njnz short loc_1402\nmov byte ptr [rbx+rdx], 1\nloc_1402:\nadd rcx, 1\ncmp rcx, rsi\njnz short loc_13E8\nxor eax, eax\nnop dword ptr [rax]\nloc_1410:\ncmp byte ptr [rbx+rax], 0\njz short loc_141B\nmov byte ptr [r14+rax], 1\nloc_141B:\nadd rax, 1\ncmp r13, rax\njnz short loc_1410\nloc_1424:\nmov eax, r11d\nadd r12, 4\ncdq\nidiv r15d\nmovsxd rdx, edx\nmov byte ptr [r14+rdx], 1\nmov rax, [rbp+var_50]\nmov rsp, [rbp+var_48]\ncmp r12, rax\njnz loc_1368\nloc_1448:\nmovzx eax, byte ptr [r14]\njmp short loc_1455\nloc_1450:\nmov eax, 1\nloc_1455:\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_1479\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1473:\nmov r11d, [r12]\njmp short loc_1424\nloc_1479:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2, int a3)\n{\n __int64 v3; // r12\n __int64 v5; // rcx\n __int16 v6; // ax\n __int64 *v7; // rdx\n signed __int64 v8; // rax\n void *v9; // rsp\n __int64 v10; // r13\n int *v11; // r12\n _QWORD *v12; // rax\n void *v13; // rsp\n int v14; // r11d\n _BYTE *v15; // rcx\n unsigned int v16; // edi\n __int64 v17; // rdx\n __int64 v18; // rax\n _QWORD v20[512]; // [rsp+0h] [rbp-2070h] BYREF\n _BYTE v21[4088]; // [rsp+1000h] [rbp-1070h] BYREF\n __int64 v22; // [rsp+2000h] [rbp-70h] BYREF\n __int64 v23; // [rsp+2008h] [rbp-68h]\n signed __int64 v24; // [rsp+2010h] [rbp-60h]\n unsigned __int64 v25; // [rsp+2018h] [rbp-58h]\n int *v26; // [rsp+2020h] [rbp-50h]\n _BYTE *v27; // [rsp+2028h] [rbp-48h]\n unsigned __int64 v28; // [rsp+2038h] [rbp-38h]\n\n v28 = __readfsqword(0x28u);\n if ( a2 <= a3 )\n {\n v3 = a3;\n v5 = a3 + 15LL;\n v6 = (a3 + 15) & 0xFFF0;\n v7 = (__int64 *)((char *)&v22 - (v5 & 0xFFFFFFFFFFFFF000LL));\n if ( &v22 != v7 )\n {\n while ( v21 != (_BYTE *)v7 )\n ;\n }\n v8 = v6 & 0xFFF;\n v9 = alloca(v8);\n if ( v8 )\n *(_QWORD *)((char *)&v20[511] + v8) = *(_QWORD *)((char *)&v20[511] + v8);\n if ( a3 > 0 )\n {\n v27 = (_BYTE *)v5;\n memset(v21, 0, (unsigned int)a3);\n v5 = (__int64)v27;\n }\n if ( a2 <= 0 )\n return v21[0];\n v26 = &a1[a2];\n v24 = v5 & 0xFF0;\n v25 = v5 & 0xFFFFFFFFFFFFFFF0LL;\n v23 = v24 - 8;\n v10 = v3;\n v11 = a1;\n while ( 1 )\n {\n v27 = v21;\n if ( v21[0] )\n break;\n v12 = &v21[-(v25 & 0xFFFFFFFFFFFFF000LL)];\n if ( v21 != (_BYTE *)v12 )\n {\n while ( v20 != v12 )\n ;\n }\n v13 = alloca(v24);\n if ( v24 )\n *(_QWORD *)((char *)v20 + v23) = *(_QWORD *)((char *)v20 + v23);\n if ( a3 <= 0 )\n {\n v14 = *v11;\n }\n else\n {\n memset(v20, 0, (unsigned int)a3);\n v14 = *v11;\n v15 = v21;\n v16 = *v11 - (unsigned int)v21;\n do\n {\n if ( *v15 )\n {\n v17 = (int)(v16 + (_DWORD)v15) % a3;\n if ( !v21[v17] )\n *((_BYTE *)v20 + v17) = 1;\n }\n ++v15;\n }\n while ( v15 != &v21[v10] );\n v18 = 0LL;\n do\n {\n if ( *((_BYTE *)v20 + v18) )\n v21[v18] = 1;\n ++v18;\n }\n while ( v10 != v18 );\n }\n ++v11;\n v21[v14 % a3] = 1;\n if ( v11 == v26 )\n return v21[0];\n }\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1290:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nmovsxd rbx, esi\nsub rsp, 48h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\ncmp ebx, edx\njg loc_1450\nmovsxd r12, edx\nmov r15d, edx\nmov rdx, rsp\nmov r13, rdi\nlea rcx, [r12+0Fh]\nmov rsi, rcx\nmov rax, rcx\nand rsi, 0FFFFFFFFFFFFF000h\nand rax, 0FFFFFFFFFFFFFFF0h\nsub rdx, rsi\ncmp rsp, rdx\njz short loc_12FE\nloc_12E9:\nsub rsp, 1000h\nor [rsp+1070h+var_78], 0\ncmp rsp, rdx\njnz short loc_12E9\nloc_12FE:\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_1311\nor [rsp+rax+1070h+var_1078], 0\nloc_1311:\nmov r14, rsp\ntest r15d, r15d\njle short loc_132E\nmov edx, r15d; n\nxor esi, esi; c\nmov rdi, rsp; s\nmov [rbp+var_48], rcx\ncall _memset\nmov rcx, [rbp+var_48]\nloc_132E:\ntest ebx, ebx\njle loc_1448\nlea rax, [r13+rbx*4+0]\nmov [rbp+var_50], rax\nmov rax, rcx\nand ecx, 0FF0h\nand rax, 0FFFFFFFFFFFFFFF0h\nmov [rbp+var_60], rcx\nmov [rbp+var_58], rax\nlea rax, [rcx-8]\nmov [rbp+var_68], rax\nmov rax, r13\nmov r13, r12\nmov r12, rax\nnop dword ptr [rax]\nloc_1368:\ncmp byte ptr [r14], 0\nmov [rbp+var_48], rsp\njnz loc_1450\nmov rdx, [rbp+var_58]\nmov rax, rsp\nand rdx, 0FFFFFFFFFFFFF000h\nsub rax, rdx\ncmp rsp, rax\njz short loc_13A1\nloc_138C:\nsub rsp, 1000h\nor [rsp+2070h+var_1078], 0\ncmp rsp, rax\njnz short loc_138C\nloc_13A1:\nmov rax, [rbp+var_60]\nsub rsp, rax\ntest rax, rax\njz short loc_13B6\nmov rax, [rbp+var_68]\nor [rsp+rax+2070h+var_2070], 0\nloc_13B6:\nmov rbx, rsp\ntest r15d, r15d\njle loc_1473\nxor esi, esi; c\nmov rdi, rsp; s\nmov edx, r15d; n\ncall _memset\nmov r11d, [r12]\nlea rsi, [r13+r14+0]\nmov rcx, r14\nmov edi, r11d\nsub edi, r14d\nnop dword ptr [rax+00000000h]\nloc_13E8:\ncmp byte ptr [rcx], 0\njz short loc_1402\nlea eax, [rdi+rcx]\ncdq\nidiv r15d\nmovsxd rdx, edx\ncmp byte ptr [r14+rdx], 0\njnz short loc_1402\nmov byte ptr [rbx+rdx], 1\nloc_1402:\nadd rcx, 1\ncmp rcx, rsi\njnz short loc_13E8\nxor eax, eax\nnop dword ptr [rax]\nloc_1410:\ncmp byte ptr [rbx+rax], 0\njz short loc_141B\nmov byte ptr [r14+rax], 1\nloc_141B:\nadd rax, 1\ncmp r13, rax\njnz short loc_1410\nloc_1424:\nmov eax, r11d\nadd r12, 4\ncdq\nidiv r15d\nmovsxd rdx, edx\nmov byte ptr [r14+rdx], 1\nmov rax, [rbp+var_50]\nmov rsp, [rbp+var_48]\ncmp r12, rax\njnz loc_1368\nloc_1448:\nmovzx eax, byte ptr [r14]\njmp short loc_1455\nloc_1450:\nmov eax, 1\nloc_1455:\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_1479\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1473:\nmov r11d, [r12]\njmp short loc_1424\nloc_1479:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1290(int *a1, int a2, int a3)\n{\n __int64 v3; // r12\n __int64 v5; // rcx\n __int16 v6; // ax\n __int64 *v7; // rdx\n signed __int64 v8; // rax\n void *v9; // rsp\n __int64 v10; // r13\n int *v11; // r12\n _QWORD *v12; // rax\n void *v13; // rsp\n int v14; // r11d\n _BYTE *v15; // rcx\n unsigned int v16; // edi\n __int64 v17; // rdx\n __int64 v18; // rax\n _QWORD v20[512]; // [rsp+0h] [rbp-2070h] BYREF\n _BYTE v21[4088]; // [rsp+1000h] [rbp-1070h] BYREF\n __int64 v22; // [rsp+2000h] [rbp-70h] BYREF\n __int64 v23; // [rsp+2008h] [rbp-68h]\n signed __int64 v24; // [rsp+2010h] [rbp-60h]\n unsigned __int64 v25; // [rsp+2018h] [rbp-58h]\n int *v26; // [rsp+2020h] [rbp-50h]\n _BYTE *v27; // [rsp+2028h] [rbp-48h]\n unsigned __int64 v28; // [rsp+2038h] [rbp-38h]\n\n v28 = __readfsqword(0x28u);\n if ( a2 <= a3 )\n {\n v3 = a3;\n v5 = a3 + 15LL;\n v6 = (a3 + 15) & 0xFFF0;\n v7 = (__int64 *)((char *)&v22 - (v5 & 0xFFFFFFFFFFFFF000LL));\n if ( &v22 != v7 )\n {\n while ( v21 != (_BYTE *)v7 )\n ;\n }\n v8 = v6 & 0xFFF;\n v9 = alloca(v8);\n if ( v8 )\n *(_QWORD *)((char *)&v20[511] + v8) = *(_QWORD *)((char *)&v20[511] + v8);\n if ( a3 > 0 )\n {\n v27 = (_BYTE *)v5;\n memset(v21, 0, (unsigned int)a3);\n v5 = (__int64)v27;\n }\n if ( a2 <= 0 )\n return v21[0];\n v26 = &a1[a2];\n v24 = v5 & 0xFF0;\n v25 = v5 & 0xFFFFFFFFFFFFFFF0LL;\n v23 = v24 - 8;\n v10 = v3;\n v11 = a1;\n while ( 1 )\n {\n v27 = v21;\n if ( v21[0] )\n break;\n v12 = &v21[-(v25 & 0xFFFFFFFFFFFFF000LL)];\n if ( v21 != (_BYTE *)v12 )\n {\n while ( v20 != v12 )\n ;\n }\n v13 = alloca(v24);\n if ( v24 )\n *(_QWORD *)((char *)v20 + v23) = *(_QWORD *)((char *)v20 + v23);\n if ( a3 <= 0 )\n {\n v14 = *v11;\n }\n else\n {\n memset(v20, 0, (unsigned int)a3);\n v14 = *v11;\n v15 = v21;\n v16 = *v11 - (unsigned int)v21;\n do\n {\n if ( *v15 )\n {\n v17 = (int)(v16 + (_DWORD)v15) % a3;\n if ( !v21[v17] )\n *((_BYTE *)v20 + v17) = 1;\n }\n ++v15;\n }\n while ( v15 != &v21[v10] );\n v18 = 0LL;\n do\n {\n if ( *((_BYTE *)v20 + v18) )\n v21[v18] = 1;\n ++v18;\n }\n while ( v10 != v18 );\n }\n ++v11;\n v21[v14 % a3] = 1;\n if ( v11 == v26 )\n return v21[0];\n }\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1290(int *a1, int a2, int a3) {\n long long v3;\n long long v5;\n short v6;\n long long *v7;\n signed long long v8;\n void *v9;\n long long v10;\n int *v11;\n uint64_t *v12;\n void *v13;\n int v14;\n uint8_t *v15;\n unsigned int v16;\n long long v17;\n long long v18;\n uint64_t v20[512];\n uint8_t v21[4088];\n long long v22;\n long long v23;\n signed long long v24;\n unsigned long long v25;\n int *v26;\n uint8_t *v27;\n unsigned long long v28;\n v28 = __readfsqword(40u);\n if (a2 <= a3) {\n v3 = a3;\n v5 = a3 + 15LL;\n v6 = (a3 + 15) & 65520;\n v7 = (long long *)((char *)&v22 - (v5 & 18446744073709547520LL));\n if (&v22 != v7) {\n while (v21 != (uint8_t *)v7)\n ;\n }\n v8 = v6 & 4095;\n v9 = alloca(v8);\n if (v8)\n *(uint64_t *)((char *)&v20[511] + v8) =\n *(uint64_t *)((char *)&v20[511] + v8);\n if (a3 > 0) {\n v27 = (uint8_t *)v5;\n memset(v21, 0, (unsigned int)a3);\n v5 = (long long)v27;\n }\n if (a2 <= 0) return v21[0];\n v26 = &a1[a2];\n v24 = v5 & 4080;\n v25 = v5 & 18446744073709551600LL;\n v23 = v24 - 8;\n v10 = v3;\n v11 = a1;\n while (1) {\n v27 = v21;\n if (v21[0]) break;\n v12 = &v21[-(v25 & 18446744073709547520LL)];\n if (v21 != (uint8_t *)v12) {\n while (v20 != v12)\n ;\n }\n v13 = alloca(v24);\n if (v24)\n *(uint64_t *)((char *)v20 + v23) = *(uint64_t *)((char *)v20 + v23);\n if (a3 <= 0) {\n v14 = *v11;\n } else {\n memset(v20, 0, (unsigned int)a3);\n v14 = *v11;\n v15 = v21;\n v16 = *v11 - (unsigned int)v21;\n do {\n if (*v15) {\n v17 = (int)(v16 + (uint32_t)v15) % a3;\n if (!v21[v17]) *((uint8_t *)v20 + v17) = 1;\n }\n ++v15;\n } while (v15 != &v21[v10]);\n v18 = 0LL;\n do {\n if (*((uint8_t *)v20 + v18)) v21[v18] = 1;\n ++v18;\n } while (v10 != v18);\n }\n ++v11;\n v21[v14 % a3] = 1;\n if (v11 == v26) return v21[0];\n }\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2, int a3) {\n long long v3;\n long long v5;\n short v6;\n long long *v7;\n signed long long v8;\n void *v9;\n long long v10;\n int *v11;\n uint64_t *v12;\n void *v13;\n int v14;\n uint8_t *v15;\n unsigned int v16;\n long long v17;\n long long v18;\n uint64_t v20[512];\n uint8_t v21[4088];\n long long v22;\n long long v23;\n signed long long v24;\n unsigned long long v25;\n int *v26;\n uint8_t *v27;\n unsigned long long v28;\n v28 = __readfsqword(40u);\n if (a2 <= a3) {\n v3 = a3;\n v5 = a3 + 15LL;\n v6 = (a3 + 15) & 65520;\n v7 = (long long *)((char *)&v22 - (v5 & 18446744073709547520LL));\n if (&v22 != v7) {\n while (v21 != (uint8_t *)v7)\n ;\n }\n v8 = v6 & 4095;\n v9 = alloca(v8);\n if (v8)\n *(uint64_t *)((char *)&v20[511] + v8) =\n *(uint64_t *)((char *)&v20[511] + v8);\n if (a3 > 0) {\n v27 = (uint8_t *)v5;\n memset(v21, 0, (unsigned int)a3);\n v5 = (long long)v27;\n }\n if (a2 <= 0) return v21[0];\n v26 = &a1[a2];\n v24 = v5 & 4080;\n v25 = v5 & 18446744073709551600LL;\n v23 = v24 - 8;\n v10 = v3;\n v11 = a1;\n while (1) {\n v27 = v21;\n if (v21[0]) break;\n v12 = &v21[-(v25 & 18446744073709547520LL)];\n if (v21 != (uint8_t *)v12) {\n while (v20 != v12)\n ;\n }\n v13 = alloca(v24);\n if (v24)\n *(uint64_t *)((char *)v20 + v23) = *(uint64_t *)((char *)v20 + v23);\n if (a3 <= 0) {\n v14 = *v11;\n } else {\n memset(v20, 0, (unsigned int)a3);\n v14 = *v11;\n v15 = v21;\n v16 = *v11 - (unsigned int)v21;\n do {\n if (*v15) {\n v17 = (int)(v16 + (uint32_t)v15) % a3;\n if (!v21[v17]) *((uint8_t *)v20 + v17) = 1;\n }\n ++v15;\n } while (v15 != &v21[v10]);\n v18 = 0LL;\n do {\n if (*((uint8_t *)v20 + v18)) v21[v18] = 1;\n ++v18;\n } while (v10 != v18);\n }\n ++v11;\n v21[v14 % a3] = 1;\n if (v11 == v26) return v21[0];\n }\n }\n return 1LL;\n}" + }, + { + "index": 515, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int arr[], int n, int m) {\n if (n > m) {\n return true;\n }\n bool DP[m];\n for (int i = 0; i < m; i++) {\n DP[i] = false;\n }\n for (int i = 0; i < n; i++) {\n if (DP[0]) {\n return true;\n }\n bool temp[m];\n for (int k = 0; k < m; k++) {\n temp[k] = false;\n }\n for (int j = 0; j < m; j++) {\n if (DP[j]) {\n if (!DP[(j + arr[i]) % m]) {\n temp[(j + arr[i]) % m] = true;\n }\n }\n }\n for (int j = 0; j < m; j++) {\n if (temp[j]) {\n DP[j] = true;\n }\n }\n DP[arr[i] % m] = true;\n }\n return DP[0];\n}", + "test": "int main() {\n\n int arr1[] = {3, 1, 7, 5};\n\n int arr2[] = {1, 7};\n\n int arr3[] = {1, 6};\n\n\n\n assert(func0(arr1, 4, 6) == true);\n\n assert(func0(arr2, 2, 5) == false);\n\n assert(func0(arr3, 2, 5) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0x58,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nmov $0x1,%eax\ncmp %edx,%esi\njg 1479 \nmovslq %edx,%rcx\nmov %edx,%r15d\nmov %esi,%r12d\nmov %rsp,%rsi\nadd $0xf,%rcx\nmov %rdi,%r13\nmov %rcx,%rdx\nmov %rcx,%rax\nand $0xfffffffffffff000,%rdx\nand $0xfffffffffffffff0,%rax\nsub %rdx,%rsi\nmov %rsi,%rdx\ncmp %rdx,%rsp\nje 1315 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rdx,%rsp\njne 1300 \nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 1328 \norq $0x0,-0x8(%rsp,%rax,1)\nmov %rsp,%rbx\ntest %r15d,%r15d\njle 134a \nlea -0x1(%r15),%edx\nxor %esi,%esi\nmov %rsp,%rdi\nmov %rcx,-0x48(%rbp)\nadd $0x1,%rdx\ncallq 1090 \nmov -0x48(%rbp),%rcx\ntest %r12d,%r12d\njle 1476 \nlea -0x1(%r12),%eax\nlea 0x4(%r13,%rax,4),%rax\nmov %rax,-0x60(%rbp)\nmov %rcx,%rax\nand $0xff0,%ecx\nand $0xfffffffffffffff0,%rax\nmov %rcx,-0x70(%rbp)\nmov %rax,-0x68(%rbp)\nlea -0x8(%rcx),%rax\nmov %rax,-0x78(%rbp)\nxchg %ax,%ax\nmovzbl (%rbx),%eax\nmov %rsp,%r14\ntest %al,%al\njne 1479 \nmov -0x68(%rbp),%rax\nmov %rsp,%rdi\nand $0xfffffffffffff000,%rax\nsub %rax,%rdi\nmov %rdi,%rax\ncmp %rax,%rsp\nje 13bb \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 13a6 \nmov -0x70(%rbp),%rax\nsub %rax,%rsp\ntest %rax,%rax\nje 13d0 \nmov -0x78(%rbp),%rax\norq $0x0,(%rsp,%rax,1)\nmov 0x0(%r13),%eax\nmov %rsp,%r12\nmov %eax,-0x48(%rbp)\ntest %r15d,%r15d\njle 1457 \nlea -0x1(%r15),%r9d\nxor %esi,%esi\nmov %rsp,%rdi\nlea 0x1(%r9),%rdx\nmov %r9,-0x58(%rbp)\nmov %rdx,-0x50(%rbp)\ncallq 1090 \nmov -0x50(%rbp),%rdx\nmov -0x48(%rbp),%edi\nmov %rbx,%rcx\nmov -0x58(%rbp),%r9\nlea (%rbx,%rdx,1),%rsi\nsub %ebx,%edi\nnopl (%rax)\ncmpb $0x0,(%rcx)\nje 142a \nlea (%rdi,%rcx,1),%eax\ncltd\nidiv %r15d\nmovslq %edx,%rdx\ncmpb $0x0,(%rbx,%rdx,1)\njne 142a \nmovb $0x1,(%r12,%rdx,1)\nadd $0x1,%rcx\ncmp %rcx,%rsi\njne 1410 \nxor %eax,%eax\njmp 1443 \nnopw 0x0(%rax,%rax,1)\nmov %rdx,%rax\ncmpb $0x0,(%r12,%rax,1)\nje 144e \nmovb $0x1,(%rbx,%rax,1)\nlea 0x1(%rax),%rdx\ncmp %r9,%rax\njne 1440 \nmov -0x48(%rbp),%eax\nadd $0x4,%r13\ncltd\nidiv %r15d\nmovslq %edx,%rdx\nmovb $0x1,(%rbx,%rdx,1)\nmov %r14,%rsp\ncmp -0x60(%rbp),%r13\njne 1380 \nmovzbl (%rbx),%eax\nmov -0x38(%rbp),%rsi\nxor %fs:0x28,%rsi\njne 1497 \nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\ncallq 1070 <__stack_chk_fail@plt>\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nmovsxd rbx, esi\nsub rsp, 48h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\ncmp ebx, edx\njg loc_1450\nmovsxd r12, edx\nmov r15d, edx\nmov rdx, rsp\nmov r13, rdi\nlea rcx, [r12+0Fh]\nmov rsi, rcx\nmov rax, rcx\nand rsi, 0FFFFFFFFFFFFF000h\nand rax, 0FFFFFFFFFFFFFFF0h\nsub rdx, rsi\ncmp rsp, rdx\njz short loc_12FE\nloc_12E9:\nsub rsp, 1000h\nor [rsp+1070h+var_78], 0\ncmp rsp, rdx\njnz short loc_12E9\nloc_12FE:\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_1311\nor [rsp+rax+1070h+var_1078], 0\nloc_1311:\nmov r14, rsp\ntest r15d, r15d\njle short loc_132E\nmov edx, r15d; n\nxor esi, esi; c\nmov rdi, rsp; s\nmov [rbp+var_48], rcx\ncall _memset\nmov rcx, [rbp+var_48]\nloc_132E:\ntest ebx, ebx\njle loc_1448\nlea rax, [r13+rbx*4+0]\nmov [rbp+var_50], rax\nmov rax, rcx\nand ecx, 0FF0h\nand rax, 0FFFFFFFFFFFFFFF0h\nmov [rbp+var_60], rcx\nmov [rbp+var_58], rax\nlea rax, [rcx-8]\nmov [rbp+var_68], rax\nmov rax, r13\nmov r13, r12\nmov r12, rax\nnop dword ptr [rax]\nloc_1368:\ncmp byte ptr [r14], 0\nmov [rbp+var_48], rsp\njnz loc_1450\nmov rdx, [rbp+var_58]\nmov rax, rsp\nand rdx, 0FFFFFFFFFFFFF000h\nsub rax, rdx\ncmp rsp, rax\njz short loc_13A1\nloc_138C:\nsub rsp, 1000h\nor [rsp+2070h+var_1078], 0\ncmp rsp, rax\njnz short loc_138C\nloc_13A1:\nmov rax, [rbp+var_60]\nsub rsp, rax\ntest rax, rax\njz short loc_13B6\nmov rax, [rbp+var_68]\nor [rsp+rax+2070h+var_2070], 0\nloc_13B6:\nmov rbx, rsp\ntest r15d, r15d\njle loc_1473\nxor esi, esi; c\nmov rdi, rsp; s\nmov edx, r15d; n\ncall _memset\nmov r11d, [r12]\nlea rsi, [r13+r14+0]\nmov rcx, r14\nmov edi, r11d\nsub edi, r14d\nnop dword ptr [rax+00000000h]\nloc_13E8:\ncmp byte ptr [rcx], 0\njz short loc_1402\nlea eax, [rdi+rcx]\ncdq\nidiv r15d\nmovsxd rdx, edx\ncmp byte ptr [r14+rdx], 0\njnz short loc_1402\nmov byte ptr [rbx+rdx], 1\nloc_1402:\nadd rcx, 1\ncmp rcx, rsi\njnz short loc_13E8\nxor eax, eax\nnop dword ptr [rax]\nloc_1410:\ncmp byte ptr [rbx+rax], 0\njz short loc_141B\nmov byte ptr [r14+rax], 1\nloc_141B:\nadd rax, 1\ncmp r13, rax\njnz short loc_1410\nloc_1424:\nmov eax, r11d\nadd r12, 4\ncdq\nidiv r15d\nmovsxd rdx, edx\nmov byte ptr [r14+rdx], 1\nmov rax, [rbp+var_50]\nmov rsp, [rbp+var_48]\ncmp r12, rax\njnz loc_1368\nloc_1448:\nmovzx eax, byte ptr [r14]\njmp short loc_1455\nloc_1450:\nmov eax, 1\nloc_1455:\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_1479\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1473:\nmov r11d, [r12]\njmp short loc_1424\nloc_1479:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2, int a3)\n{\n __int64 v3; // r12\n __int64 v5; // rcx\n __int16 v6; // ax\n __int64 *v7; // rdx\n signed __int64 v8; // rax\n void *v9; // rsp\n __int64 v10; // r13\n int *v11; // r12\n _QWORD *v12; // rax\n void *v13; // rsp\n int v14; // r11d\n _BYTE *v15; // rcx\n unsigned int v16; // edi\n __int64 v17; // rdx\n __int64 v18; // rax\n _QWORD v20[512]; // [rsp+0h] [rbp-2070h] BYREF\n _BYTE v21[4088]; // [rsp+1000h] [rbp-1070h] BYREF\n __int64 v22; // [rsp+2000h] [rbp-70h] BYREF\n __int64 v23; // [rsp+2008h] [rbp-68h]\n signed __int64 v24; // [rsp+2010h] [rbp-60h]\n unsigned __int64 v25; // [rsp+2018h] [rbp-58h]\n int *v26; // [rsp+2020h] [rbp-50h]\n _BYTE *v27; // [rsp+2028h] [rbp-48h]\n unsigned __int64 v28; // [rsp+2038h] [rbp-38h]\n\n v28 = __readfsqword(0x28u);\n if ( a2 <= a3 )\n {\n v3 = a3;\n v5 = a3 + 15LL;\n v6 = (a3 + 15) & 0xFFF0;\n v7 = (__int64 *)((char *)&v22 - (v5 & 0xFFFFFFFFFFFFF000LL));\n if ( &v22 != v7 )\n {\n while ( v21 != (_BYTE *)v7 )\n ;\n }\n v8 = v6 & 0xFFF;\n v9 = alloca(v8);\n if ( v8 )\n *(_QWORD *)((char *)&v20[511] + v8) = *(_QWORD *)((char *)&v20[511] + v8);\n if ( a3 > 0 )\n {\n v27 = (_BYTE *)v5;\n memset(v21, 0, (unsigned int)a3);\n v5 = (__int64)v27;\n }\n if ( a2 <= 0 )\n return v21[0];\n v26 = &a1[a2];\n v24 = v5 & 0xFF0;\n v25 = v5 & 0xFFFFFFFFFFFFFFF0LL;\n v23 = v24 - 8;\n v10 = v3;\n v11 = a1;\n while ( 1 )\n {\n v27 = v21;\n if ( v21[0] )\n break;\n v12 = &v21[-(v25 & 0xFFFFFFFFFFFFF000LL)];\n if ( v21 != (_BYTE *)v12 )\n {\n while ( v20 != v12 )\n ;\n }\n v13 = alloca(v24);\n if ( v24 )\n *(_QWORD *)((char *)v20 + v23) = *(_QWORD *)((char *)v20 + v23);\n if ( a3 <= 0 )\n {\n v14 = *v11;\n }\n else\n {\n memset(v20, 0, (unsigned int)a3);\n v14 = *v11;\n v15 = v21;\n v16 = *v11 - (unsigned int)v21;\n do\n {\n if ( *v15 )\n {\n v17 = (int)(v16 + (_DWORD)v15) % a3;\n if ( !v21[v17] )\n *((_BYTE *)v20 + v17) = 1;\n }\n ++v15;\n }\n while ( v15 != &v21[v10] );\n v18 = 0LL;\n do\n {\n if ( *((_BYTE *)v20 + v18) )\n v21[v18] = 1;\n ++v18;\n }\n while ( v10 != v18 );\n }\n ++v11;\n v21[v14 % a3] = 1;\n if ( v11 == v26 )\n return v21[0];\n }\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1290:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nmovsxd rbx, esi\nsub rsp, 48h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\ncmp ebx, edx\njg loc_1450\nmovsxd r12, edx\nmov r15d, edx\nmov rdx, rsp\nmov r13, rdi\nlea rcx, [r12+0Fh]\nmov rsi, rcx\nmov rax, rcx\nand rsi, 0FFFFFFFFFFFFF000h\nand rax, 0FFFFFFFFFFFFFFF0h\nsub rdx, rsi\ncmp rsp, rdx\njz short loc_12FE\nloc_12E9:\nsub rsp, 1000h\nor [rsp+1070h+var_78], 0\ncmp rsp, rdx\njnz short loc_12E9\nloc_12FE:\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_1311\nor [rsp+rax+1070h+var_1078], 0\nloc_1311:\nmov r14, rsp\ntest r15d, r15d\njle short loc_132E\nmov edx, r15d; n\nxor esi, esi; c\nmov rdi, rsp; s\nmov [rbp+var_48], rcx\ncall _memset\nmov rcx, [rbp+var_48]\nloc_132E:\ntest ebx, ebx\njle loc_1448\nlea rax, [r13+rbx*4+0]\nmov [rbp+var_50], rax\nmov rax, rcx\nand ecx, 0FF0h\nand rax, 0FFFFFFFFFFFFFFF0h\nmov [rbp+var_60], rcx\nmov [rbp+var_58], rax\nlea rax, [rcx-8]\nmov [rbp+var_68], rax\nmov rax, r13\nmov r13, r12\nmov r12, rax\nnop dword ptr [rax]\nloc_1368:\ncmp byte ptr [r14], 0\nmov [rbp+var_48], rsp\njnz loc_1450\nmov rdx, [rbp+var_58]\nmov rax, rsp\nand rdx, 0FFFFFFFFFFFFF000h\nsub rax, rdx\ncmp rsp, rax\njz short loc_13A1\nloc_138C:\nsub rsp, 1000h\nor [rsp+2070h+var_1078], 0\ncmp rsp, rax\njnz short loc_138C\nloc_13A1:\nmov rax, [rbp+var_60]\nsub rsp, rax\ntest rax, rax\njz short loc_13B6\nmov rax, [rbp+var_68]\nor [rsp+rax+2070h+var_2070], 0\nloc_13B6:\nmov rbx, rsp\ntest r15d, r15d\njle loc_1473\nxor esi, esi; c\nmov rdi, rsp; s\nmov edx, r15d; n\ncall _memset\nmov r11d, [r12]\nlea rsi, [r13+r14+0]\nmov rcx, r14\nmov edi, r11d\nsub edi, r14d\nnop dword ptr [rax+00000000h]\nloc_13E8:\ncmp byte ptr [rcx], 0\njz short loc_1402\nlea eax, [rdi+rcx]\ncdq\nidiv r15d\nmovsxd rdx, edx\ncmp byte ptr [r14+rdx], 0\njnz short loc_1402\nmov byte ptr [rbx+rdx], 1\nloc_1402:\nadd rcx, 1\ncmp rcx, rsi\njnz short loc_13E8\nxor eax, eax\nnop dword ptr [rax]\nloc_1410:\ncmp byte ptr [rbx+rax], 0\njz short loc_141B\nmov byte ptr [r14+rax], 1\nloc_141B:\nadd rax, 1\ncmp r13, rax\njnz short loc_1410\nloc_1424:\nmov eax, r11d\nadd r12, 4\ncdq\nidiv r15d\nmovsxd rdx, edx\nmov byte ptr [r14+rdx], 1\nmov rax, [rbp+var_50]\nmov rsp, [rbp+var_48]\ncmp r12, rax\njnz loc_1368\nloc_1448:\nmovzx eax, byte ptr [r14]\njmp short loc_1455\nloc_1450:\nmov eax, 1\nloc_1455:\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_1479\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1473:\nmov r11d, [r12]\njmp short loc_1424\nloc_1479:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1290(int *a1, int a2, int a3)\n{\n __int64 v3; // r12\n __int64 v5; // rcx\n __int16 v6; // ax\n __int64 *v7; // rdx\n signed __int64 v8; // rax\n void *v9; // rsp\n __int64 v10; // r13\n int *v11; // r12\n _QWORD *v12; // rax\n void *v13; // rsp\n int v14; // r11d\n _BYTE *v15; // rcx\n unsigned int v16; // edi\n __int64 v17; // rdx\n __int64 v18; // rax\n _QWORD v20[512]; // [rsp+0h] [rbp-2070h] BYREF\n _BYTE v21[4088]; // [rsp+1000h] [rbp-1070h] BYREF\n __int64 v22; // [rsp+2000h] [rbp-70h] BYREF\n __int64 v23; // [rsp+2008h] [rbp-68h]\n signed __int64 v24; // [rsp+2010h] [rbp-60h]\n unsigned __int64 v25; // [rsp+2018h] [rbp-58h]\n int *v26; // [rsp+2020h] [rbp-50h]\n _BYTE *v27; // [rsp+2028h] [rbp-48h]\n unsigned __int64 v28; // [rsp+2038h] [rbp-38h]\n\n v28 = __readfsqword(0x28u);\n if ( a2 <= a3 )\n {\n v3 = a3;\n v5 = a3 + 15LL;\n v6 = (a3 + 15) & 0xFFF0;\n v7 = (__int64 *)((char *)&v22 - (v5 & 0xFFFFFFFFFFFFF000LL));\n if ( &v22 != v7 )\n {\n while ( v21 != (_BYTE *)v7 )\n ;\n }\n v8 = v6 & 0xFFF;\n v9 = alloca(v8);\n if ( v8 )\n *(_QWORD *)((char *)&v20[511] + v8) = *(_QWORD *)((char *)&v20[511] + v8);\n if ( a3 > 0 )\n {\n v27 = (_BYTE *)v5;\n memset(v21, 0, (unsigned int)a3);\n v5 = (__int64)v27;\n }\n if ( a2 <= 0 )\n return v21[0];\n v26 = &a1[a2];\n v24 = v5 & 0xFF0;\n v25 = v5 & 0xFFFFFFFFFFFFFFF0LL;\n v23 = v24 - 8;\n v10 = v3;\n v11 = a1;\n while ( 1 )\n {\n v27 = v21;\n if ( v21[0] )\n break;\n v12 = &v21[-(v25 & 0xFFFFFFFFFFFFF000LL)];\n if ( v21 != (_BYTE *)v12 )\n {\n while ( v20 != v12 )\n ;\n }\n v13 = alloca(v24);\n if ( v24 )\n *(_QWORD *)((char *)v20 + v23) = *(_QWORD *)((char *)v20 + v23);\n if ( a3 <= 0 )\n {\n v14 = *v11;\n }\n else\n {\n memset(v20, 0, (unsigned int)a3);\n v14 = *v11;\n v15 = v21;\n v16 = *v11 - (unsigned int)v21;\n do\n {\n if ( *v15 )\n {\n v17 = (int)(v16 + (_DWORD)v15) % a3;\n if ( !v21[v17] )\n *((_BYTE *)v20 + v17) = 1;\n }\n ++v15;\n }\n while ( v15 != &v21[v10] );\n v18 = 0LL;\n do\n {\n if ( *((_BYTE *)v20 + v18) )\n v21[v18] = 1;\n ++v18;\n }\n while ( v10 != v18 );\n }\n ++v11;\n v21[v14 % a3] = 1;\n if ( v11 == v26 )\n return v21[0];\n }\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1290(int *a1, int a2, int a3) {\n long long v3;\n long long v5;\n short v6;\n long long *v7;\n signed long long v8;\n void *v9;\n long long v10;\n int *v11;\n uint64_t *v12;\n void *v13;\n int v14;\n uint8_t *v15;\n unsigned int v16;\n long long v17;\n long long v18;\n uint64_t v20[512];\n uint8_t v21[4088];\n long long v22;\n long long v23;\n signed long long v24;\n unsigned long long v25;\n int *v26;\n uint8_t *v27;\n unsigned long long v28;\n v28 = __readfsqword(40u);\n if (a2 <= a3) {\n v3 = a3;\n v5 = a3 + 15LL;\n v6 = (a3 + 15) & 65520;\n v7 = (long long *)((char *)&v22 - (v5 & 18446744073709547520LL));\n if (&v22 != v7) {\n while (v21 != (uint8_t *)v7)\n ;\n }\n v8 = v6 & 4095;\n v9 = alloca(v8);\n if (v8)\n *(uint64_t *)((char *)&v20[511] + v8) =\n *(uint64_t *)((char *)&v20[511] + v8);\n if (a3 > 0) {\n v27 = (uint8_t *)v5;\n memset(v21, 0, (unsigned int)a3);\n v5 = (long long)v27;\n }\n if (a2 <= 0) return v21[0];\n v26 = &a1[a2];\n v24 = v5 & 4080;\n v25 = v5 & 18446744073709551600LL;\n v23 = v24 - 8;\n v10 = v3;\n v11 = a1;\n while (1) {\n v27 = v21;\n if (v21[0]) break;\n v12 = &v21[-(v25 & 18446744073709547520LL)];\n if (v21 != (uint8_t *)v12) {\n while (v20 != v12)\n ;\n }\n v13 = alloca(v24);\n if (v24)\n *(uint64_t *)((char *)v20 + v23) = *(uint64_t *)((char *)v20 + v23);\n if (a3 <= 0) {\n v14 = *v11;\n } else {\n memset(v20, 0, (unsigned int)a3);\n v14 = *v11;\n v15 = v21;\n v16 = *v11 - (unsigned int)v21;\n do {\n if (*v15) {\n v17 = (int)(v16 + (uint32_t)v15) % a3;\n if (!v21[v17]) *((uint8_t *)v20 + v17) = 1;\n }\n ++v15;\n } while (v15 != &v21[v10]);\n v18 = 0LL;\n do {\n if (*((uint8_t *)v20 + v18)) v21[v18] = 1;\n ++v18;\n } while (v10 != v18);\n }\n ++v11;\n v21[v14 % a3] = 1;\n if (v11 == v26) return v21[0];\n }\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2, int a3) {\n long long v3;\n long long v5;\n short v6;\n long long *v7;\n signed long long v8;\n void *v9;\n long long v10;\n int *v11;\n uint64_t *v12;\n void *v13;\n int v14;\n uint8_t *v15;\n unsigned int v16;\n long long v17;\n long long v18;\n uint64_t v20[512];\n uint8_t v21[4088];\n long long v22;\n long long v23;\n signed long long v24;\n unsigned long long v25;\n int *v26;\n uint8_t *v27;\n unsigned long long v28;\n v28 = __readfsqword(40u);\n if (a2 <= a3) {\n v3 = a3;\n v5 = a3 + 15LL;\n v6 = (a3 + 15) & 65520;\n v7 = (long long *)((char *)&v22 - (v5 & 18446744073709547520LL));\n if (&v22 != v7) {\n while (v21 != (uint8_t *)v7)\n ;\n }\n v8 = v6 & 4095;\n v9 = alloca(v8);\n if (v8)\n *(uint64_t *)((char *)&v20[511] + v8) =\n *(uint64_t *)((char *)&v20[511] + v8);\n if (a3 > 0) {\n v27 = (uint8_t *)v5;\n memset(v21, 0, (unsigned int)a3);\n v5 = (long long)v27;\n }\n if (a2 <= 0) return v21[0];\n v26 = &a1[a2];\n v24 = v5 & 4080;\n v25 = v5 & 18446744073709551600LL;\n v23 = v24 - 8;\n v10 = v3;\n v11 = a1;\n while (1) {\n v27 = v21;\n if (v21[0]) break;\n v12 = &v21[-(v25 & 18446744073709547520LL)];\n if (v21 != (uint8_t *)v12) {\n while (v20 != v12)\n ;\n }\n v13 = alloca(v24);\n if (v24)\n *(uint64_t *)((char *)v20 + v23) = *(uint64_t *)((char *)v20 + v23);\n if (a3 <= 0) {\n v14 = *v11;\n } else {\n memset(v20, 0, (unsigned int)a3);\n v14 = *v11;\n v15 = v21;\n v16 = *v11 - (unsigned int)v21;\n do {\n if (*v15) {\n v17 = (int)(v16 + (uint32_t)v15) % a3;\n if (!v21[v17]) *((uint8_t *)v20 + v17) = 1;\n }\n ++v15;\n } while (v15 != &v21[v10]);\n v18 = 0LL;\n do {\n if (*((uint8_t *)v20 + v18)) v21[v18] = 1;\n ++v18;\n } while (v10 != v18);\n }\n ++v11;\n v21[v14 % a3] = 1;\n if (v11 == v26) return v21[0];\n }\n }\n return 1LL;\n}" + }, + { + "index": 516, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n#define RADIX 10\n\n\n\n", + "func": "void func0(int *nums, int size) {\n int placement = 1;\n int max_digit = nums[0];\n for (int i = 1; i < size; i++) {\n if (nums[i] > max_digit) {\n max_digit = nums[i];\n }\n }\n int *output = (int *)malloc(size * sizeof(int));\n int *count = (int *)malloc(RADIX * sizeof(int));\n while (placement <= max_digit) {\n for (int i = 0; i < RADIX; i++) {\n count[i] = 0;\n }\n for (int i = 0; i < size; i++) {\n int index = (nums[i] / placement) % RADIX;\n count[index]++;\n }\n for (int i = 1; i < RADIX; i++) {\n count[i] += count[i - 1];\n }\n for (int i = size - 1; i >= 0; i--) {\n int index = (nums[i] / placement) % RADIX;\n output[count[index] - 1] = nums[i];\n count[index]--;\n }\n for (int i = 0; i < size; i++) {\n nums[i] = output[i];\n }\n placement *= RADIX;\n }\n free(output);\n free(count);\n}", + "test": "int main() {\n\n int nums1[] = {15, 79, 25, 68, 37};\n\n int size1 = sizeof(nums1) / sizeof(nums1[0]);\n\n func0(nums1, size1);\n\n int sorted1[] = {15, 25, 37, 68, 79};\n\n for (int i = 0; i < size1; i++) {\n\n assert(nums1[i] == sorted1[i]);\n\n }\n\n\n\n int nums2[] = {9, 11, 8, 7, 3, 2};\n\n int size2 = sizeof(nums2) / sizeof(nums2[0]);\n\n func0(nums2, size2);\n\n int sorted2[] = {2, 3, 7, 8, 9, 11};\n\n for (int i = 0; i < size2; i++) {\n\n assert(nums2[i] == sorted2[i]);\n\n }\n\n\n\n int nums3[] = {36, 12, 24, 26, 29};\n\n int size3 = sizeof(nums3) / sizeof(nums3[0]);\n\n func0(nums3, size3);\n\n int sorted3[] = {12, 24, 26, 29, 36};\n\n for (int i = 0; i < size3; i++) {\n\n assert(nums3[i] == sorted3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x50,%rsp\nmov %rdi,-0x48(%rbp)\nmov %esi,-0x4c(%rbp)\nmovl $0x1,-0x38(%rbp)\nmov -0x48(%rbp),%rax\nmov (%rax),%eax\nmov %eax,-0x34(%rbp)\nmovl $0x1,-0x30(%rbp)\njmp 120d \nmov -0x30(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x34(%rbp)\njge 1209 \nmov -0x30(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x34(%rbp)\naddl $0x1,-0x30(%rbp)\nmov -0x30(%rbp),%eax\ncmp -0x4c(%rbp),%eax\njl 11d5 \nmov -0x4c(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x10(%rbp)\nmov $0x28,%edi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\njmpq 1456 \nmovl $0x0,-0x2c(%rbp)\njmp 1264 \nmov -0x2c(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmovl $0x0,(%rax)\naddl $0x1,-0x2c(%rbp)\ncmpl $0x9,-0x2c(%rbp)\njle 1246 \nmovl $0x0,-0x28(%rbp)\njmp 12e0 \nmov -0x28(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncltd\nidivl -0x38(%rbp)\nmov %eax,%edx\nmovslq %edx,%rax\nimul $0x66666667,%rax,%rax\nshr $0x20,%rax\nmov %eax,%ecx\nsar $0x2,%ecx\nmov %edx,%eax\nsar $0x1f,%eax\nsub %eax,%ecx\nmov %ecx,%eax\nmov %eax,-0x14(%rbp)\nmov -0x14(%rbp),%ecx\nmov %ecx,%eax\nshl $0x2,%eax\nadd %ecx,%eax\nadd %eax,%eax\nsub %eax,%edx\nmov %edx,%eax\nmov %eax,-0x14(%rbp)\nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nadd $0x1,%edx\nmov %edx,(%rax)\naddl $0x1,-0x28(%rbp)\nmov -0x28(%rbp),%eax\ncmp -0x4c(%rbp),%eax\njl 1273 \nmovl $0x1,-0x24(%rbp)\njmp 1339 \nmov -0x24(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%ecx\nmov -0x24(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x24(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rsi\nmov -0x8(%rbp),%rax\nadd %rsi,%rax\nadd %ecx,%edx\nmov %edx,(%rax)\naddl $0x1,-0x24(%rbp)\ncmpl $0x9,-0x24(%rbp)\njle 12f1 \nmov -0x4c(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0x20(%rbp)\njmpq 13fb \nmov -0x20(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncltd\nidivl -0x38(%rbp)\nmov %eax,%edx\nmovslq %edx,%rax\nimul $0x66666667,%rax,%rax\nshr $0x20,%rax\nmov %eax,%ecx\nsar $0x2,%ecx\nmov %edx,%eax\nsar $0x1f,%eax\nsub %eax,%ecx\nmov %ecx,%eax\nmov %eax,-0x18(%rbp)\nmov -0x18(%rbp),%ecx\nmov %ecx,%eax\nshl $0x2,%eax\nadd %ecx,%eax\nadd %eax,%eax\nsub %eax,%edx\nmov %edx,%eax\nmov %eax,-0x18(%rbp)\nmov -0x20(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov -0x18(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rdx),%edx\nmovslq %edx,%rdx\nshl $0x2,%rdx\nlea -0x4(%rdx),%rcx\nmov -0x10(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nsub $0x1,%edx\nmov %edx,(%rax)\nsubl $0x1,-0x20(%rbp)\ncmpl $0x0,-0x20(%rbp)\njns 134d \nmovl $0x0,-0x1c(%rbp)\njmp 143f \nmov -0x1c(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x10(%rbp),%rax\nadd %rdx,%rax\nmov -0x1c(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x48(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x1c(%rbp)\nmov -0x1c(%rbp),%eax\ncmp -0x4c(%rbp),%eax\njl 140e \nmov -0x38(%rbp),%edx\nmov %edx,%eax\nshl $0x2,%eax\nadd %edx,%eax\nadd %eax,%eax\nmov %eax,-0x38(%rbp)\nmov -0x38(%rbp),%eax\ncmp -0x34(%rbp),%eax\njle 123d \nmov -0x10(%rbp),%rax\nmov %rax,%rdi\ncallq 1080 \nmov -0x8(%rbp),%rax\nmov %rax,%rdi\ncallq 1080 \nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+var_48], rdi\nmov [rbp+var_4C], esi\nmov [rbp+var_38], 1\nmov rax, [rbp+var_48]\nmov eax, [rax]\nmov [rbp+var_34], eax\nmov [rbp+var_30], 1\njmp short loc_120D\nloc_11D5:\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_34], eax\njge short loc_1209\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_34], eax\nloc_1209:\nadd [rbp+var_30], 1\nloc_120D:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_4C]\njl short loc_11D5\nmov eax, [rbp+var_4C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov edi, 28h ; '('; size\ncall _malloc\nmov [rbp+var_8], rax\njmp loc_144A\nloc_123D:\nmov [rbp+var_2C], 0\njmp short loc_1264\nloc_1246:\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov dword ptr [rax], 0\nadd [rbp+var_2C], 1\nloc_1264:\ncmp [rbp+var_2C], 9\njle short loc_1246\nmov [rbp+var_28], 0\njmp short loc_12DA\nloc_1273:\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax]\ncdq\nidiv [rbp+var_38]\nmov edx, eax\nmovsxd rax, edx\nimul rax, 66666667h\nshr rax, 20h\nsar eax, 2\nmov ecx, edx\nsar ecx, 1Fh\nsub eax, ecx\nmov [rbp+var_14], eax\nmov ecx, [rbp+var_14]\nmov eax, ecx\nshl eax, 2\nadd eax, ecx\nadd eax, eax\nsub edx, eax\nmov [rbp+var_14], edx\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rax]\nadd edx, 1\nmov [rax], edx\nadd [rbp+var_28], 1\nloc_12DA:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_4C]\njl short loc_1273\nmov [rbp+var_24], 1\njmp short loc_1333\nloc_12EB:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov ecx, [rax]\nmov eax, [rbp+var_24]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_24]\ncdqe\nlea rsi, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rsi\nadd edx, ecx\nmov [rax], edx\nadd [rbp+var_24], 1\nloc_1333:\ncmp [rbp+var_24], 9\njle short loc_12EB\nmov eax, [rbp+var_4C]\nsub eax, 1\nmov [rbp+var_20], eax\njmp loc_13EF\nloc_1347:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax]\ncdq\nidiv [rbp+var_38]\nmov edx, eax\nmovsxd rax, edx\nimul rax, 66666667h\nshr rax, 20h\nsar eax, 2\nmov ecx, edx\nsar ecx, 1Fh\nsub eax, ecx\nmov [rbp+var_18], eax\nmov ecx, [rbp+var_18]\nmov eax, ecx\nshl eax, 2\nadd eax, ecx\nadd eax, eax\nsub edx, eax\nmov [rbp+var_18], edx\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov edx, [rbp+var_18]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov edx, [rdx]\nmovsxd rdx, edx\nshl rdx, 2\nlea rcx, [rdx-4]\nmov rdx, [rbp+ptr]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rax]\nsub edx, 1\nmov [rax], edx\nsub [rbp+var_20], 1\nloc_13EF:\ncmp [rbp+var_20], 0\njns loc_1347\nmov [rbp+var_1C], 0\njmp short loc_1433\nloc_1402:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_48]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_1C], 1\nloc_1433:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_4C]\njl short loc_1402\nmov edx, [rbp+var_38]\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nmov [rbp+var_38], eax\nloc_144A:\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_34]\njle loc_123D\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_8]\nmov rdi, rax; ptr\ncall _free\nnop\nleave\nretn", + "ida_pseudo": "void __fastcall func0(int *a1, int a2)\n{\n int v2; // [rsp+18h] [rbp-38h]\n int v3; // [rsp+1Ch] [rbp-34h]\n int i; // [rsp+20h] [rbp-30h]\n int j; // [rsp+24h] [rbp-2Ch]\n int k; // [rsp+28h] [rbp-28h]\n int m; // [rsp+2Ch] [rbp-24h]\n int n; // [rsp+30h] [rbp-20h]\n int ii; // [rsp+34h] [rbp-1Ch]\n int v10; // [rsp+38h] [rbp-18h]\n int v11; // [rsp+3Ch] [rbp-14h]\n _DWORD *ptr; // [rsp+40h] [rbp-10h]\n _DWORD *v13; // [rsp+48h] [rbp-8h]\n\n v2 = 1;\n v3 = *a1;\n for ( i = 1; i < a2; ++i )\n {\n if ( v3 < a1[i] )\n v3 = a1[i];\n }\n ptr = malloc(4LL * a2);\n v13 = malloc(0x28uLL);\n while ( v2 <= v3 )\n {\n for ( j = 0; j <= 9; ++j )\n v13[j] = 0;\n for ( k = 0; k < a2; ++k )\n {\n v11 = a1[k] / v2 % 10;\n ++v13[v11];\n }\n for ( m = 1; m <= 9; ++m )\n v13[m] += v13[m - 1];\n for ( n = a2 - 1; n >= 0; --n )\n {\n v10 = a1[n] / v2 % 10;\n ptr[--v13[v10]] = a1[n];\n }\n for ( ii = 0; ii < a2; ++ii )\n a1[ii] = ptr[ii];\n v2 *= 10;\n }\n free(ptr);\n free(v13);\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+var_48], rdi\nmov [rbp+var_4C], esi\nmov [rbp+var_38], 1\nmov rax, [rbp+var_48]\nmov eax, [rax]\nmov [rbp+var_34], eax\nmov [rbp+var_30], 1\njmp short loc_120D\nloc_11D5:\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_34], eax\njge short loc_1209\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_34], eax\nloc_1209:\nadd [rbp+var_30], 1\nloc_120D:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_4C]\njl short loc_11D5\nmov eax, [rbp+var_4C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov edi, 28h ; '('; size\ncall _malloc\nmov [rbp+var_8], rax\njmp loc_144A\nloc_123D:\nmov [rbp+var_2C], 0\njmp short loc_1264\nloc_1246:\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov dword ptr [rax], 0\nadd [rbp+var_2C], 1\nloc_1264:\ncmp [rbp+var_2C], 9\njle short loc_1246\nmov [rbp+var_28], 0\njmp short loc_12DA\nloc_1273:\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax]\ncdq\nidiv [rbp+var_38]\nmov edx, eax\nmovsxd rax, edx\nimul rax, 66666667h\nshr rax, 20h\nsar eax, 2\nmov ecx, edx\nsar ecx, 1Fh\nsub eax, ecx\nmov [rbp+var_14], eax\nmov ecx, [rbp+var_14]\nmov eax, ecx\nshl eax, 2\nadd eax, ecx\nadd eax, eax\nsub edx, eax\nmov [rbp+var_14], edx\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rax]\nadd edx, 1\nmov [rax], edx\nadd [rbp+var_28], 1\nloc_12DA:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_4C]\njl short loc_1273\nmov [rbp+var_24], 1\njmp short loc_1333\nloc_12EB:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov ecx, [rax]\nmov eax, [rbp+var_24]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_24]\ncdqe\nlea rsi, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rsi\nadd edx, ecx\nmov [rax], edx\nadd [rbp+var_24], 1\nloc_1333:\ncmp [rbp+var_24], 9\njle short loc_12EB\nmov eax, [rbp+var_4C]\nsub eax, 1\nmov [rbp+var_20], eax\njmp loc_13EF\nloc_1347:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax]\ncdq\nidiv [rbp+var_38]\nmov edx, eax\nmovsxd rax, edx\nimul rax, 66666667h\nshr rax, 20h\nsar eax, 2\nmov ecx, edx\nsar ecx, 1Fh\nsub eax, ecx\nmov [rbp+var_18], eax\nmov ecx, [rbp+var_18]\nmov eax, ecx\nshl eax, 2\nadd eax, ecx\nadd eax, eax\nsub edx, eax\nmov [rbp+var_18], edx\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov edx, [rbp+var_18]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov edx, [rdx]\nmovsxd rdx, edx\nshl rdx, 2\nlea rcx, [rdx-4]\nmov rdx, [rbp+ptr]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rax]\nsub edx, 1\nmov [rax], edx\nsub [rbp+var_20], 1\nloc_13EF:\ncmp [rbp+var_20], 0\njns loc_1347\nmov [rbp+var_1C], 0\njmp short loc_1433\nloc_1402:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_48]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_1C], 1\nloc_1433:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_4C]\njl short loc_1402\nmov edx, [rbp+var_38]\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nmov [rbp+var_38], eax\nloc_144A:\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_34]\njle loc_123D\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_8]\nmov rdi, rax; ptr\ncall _free\nnop\nleave\nretn", + "ida_strip_pseudo": "void __fastcall sub_11A9(int *a1, int a2)\n{\n int v2; // [rsp+18h] [rbp-38h]\n int v3; // [rsp+1Ch] [rbp-34h]\n int i; // [rsp+20h] [rbp-30h]\n int j; // [rsp+24h] [rbp-2Ch]\n int k; // [rsp+28h] [rbp-28h]\n int m; // [rsp+2Ch] [rbp-24h]\n int n; // [rsp+30h] [rbp-20h]\n int ii; // [rsp+34h] [rbp-1Ch]\n int v10; // [rsp+38h] [rbp-18h]\n int v11; // [rsp+3Ch] [rbp-14h]\n _DWORD *ptr; // [rsp+40h] [rbp-10h]\n _DWORD *v13; // [rsp+48h] [rbp-8h]\n\n v2 = 1;\n v3 = *a1;\n for ( i = 1; i < a2; ++i )\n {\n if ( v3 < a1[i] )\n v3 = a1[i];\n }\n ptr = malloc(4LL * a2);\n v13 = malloc(0x28uLL);\n while ( v2 <= v3 )\n {\n for ( j = 0; j <= 9; ++j )\n v13[j] = 0;\n for ( k = 0; k < a2; ++k )\n {\n v11 = a1[k] / v2 % 10;\n ++v13[v11];\n }\n for ( m = 1; m <= 9; ++m )\n v13[m] += v13[m - 1];\n for ( n = a2 - 1; n >= 0; --n )\n {\n v10 = a1[n] / v2 % 10;\n ptr[--v13[v10]] = a1[n];\n }\n for ( ii = 0; ii < a2; ++ii )\n a1[ii] = ptr[ii];\n v2 *= 10;\n }\n free(ptr);\n free(v13);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_11A9(int *a1, int a2) {\n int v2;\n int v3;\n int i;\n int j;\n int k;\n int m;\n int n;\n int ii;\n int v10;\n int v11;\n uint32_t *ptr;\n uint32_t *v13;\n v2 = 1;\n v3 = *a1;\n for (i = 1; i < a2; ++i) {\n if (v3 < a1[i]) v3 = a1[i];\n }\n ptr = malloc(4LL * a2);\n v13 = malloc(40uLL);\n while (v2 <= v3) {\n for (j = 0; j <= 9; ++j) v13[j] = 0;\n for (k = 0; k < a2; ++k) {\n v11 = a1[k] / v2 % 10;\n ++v13[v11];\n }\n for (m = 1; m <= 9; ++m) v13[m] += v13[m - 1];\n for (n = a2 - 1; n >= 0; --n) {\n v10 = a1[n] / v2 % 10;\n ptr[--v13[v10]] = a1[n];\n }\n for (ii = 0; ii < a2; ++ii) a1[ii] = ptr[ii];\n v2 *= 10;\n }\n free(ptr);\n free(v13);\n}", + "ida_pseudo_norm": "void func0(int *a1, int a2) {\n int v2;\n int v3;\n int i;\n int j;\n int k;\n int m;\n int n;\n int ii;\n int v10;\n int v11;\n uint32_t *ptr;\n uint32_t *v13;\n v2 = 1;\n v3 = *a1;\n for (i = 1; i < a2; ++i) {\n if (v3 < a1[i]) v3 = a1[i];\n }\n ptr = malloc(4LL * a2);\n v13 = malloc(40uLL);\n while (v2 <= v3) {\n for (j = 0; j <= 9; ++j) v13[j] = 0;\n for (k = 0; k < a2; ++k) {\n v11 = a1[k] / v2 % 10;\n ++v13[v11];\n }\n for (m = 1; m <= 9; ++m) v13[m] += v13[m - 1];\n for (n = a2 - 1; n >= 0; --n) {\n v10 = a1[n] / v2 % 10;\n ptr[--v13[v10]] = a1[n];\n }\n for (ii = 0; ii < a2; ++ii) a1[ii] = ptr[ii];\n v2 *= 10;\n }\n free(ptr);\n free(v13);\n}" + }, + { + "index": 516, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n#define RADIX 10\n\n\n\n", + "func": "void func0(int *nums, int size) {\n int placement = 1;\n int max_digit = nums[0];\n for (int i = 1; i < size; i++) {\n if (nums[i] > max_digit) {\n max_digit = nums[i];\n }\n }\n int *output = (int *)malloc(size * sizeof(int));\n int *count = (int *)malloc(RADIX * sizeof(int));\n while (placement <= max_digit) {\n for (int i = 0; i < RADIX; i++) {\n count[i] = 0;\n }\n for (int i = 0; i < size; i++) {\n int index = (nums[i] / placement) % RADIX;\n count[index]++;\n }\n for (int i = 1; i < RADIX; i++) {\n count[i] += count[i - 1];\n }\n for (int i = size - 1; i >= 0; i--) {\n int index = (nums[i] / placement) % RADIX;\n output[count[index] - 1] = nums[i];\n count[index]--;\n }\n for (int i = 0; i < size; i++) {\n nums[i] = output[i];\n }\n placement *= RADIX;\n }\n free(output);\n free(count);\n}", + "test": "int main() {\n\n int nums1[] = {15, 79, 25, 68, 37};\n\n int size1 = sizeof(nums1) / sizeof(nums1[0]);\n\n func0(nums1, size1);\n\n int sorted1[] = {15, 25, 37, 68, 79};\n\n for (int i = 0; i < size1; i++) {\n\n assert(nums1[i] == sorted1[i]);\n\n }\n\n\n\n int nums2[] = {9, 11, 8, 7, 3, 2};\n\n int size2 = sizeof(nums2) / sizeof(nums2[0]);\n\n func0(nums2, size2);\n\n int sorted2[] = {2, 3, 7, 8, 9, 11};\n\n for (int i = 0; i < size2; i++) {\n\n assert(nums2[i] == sorted2[i]);\n\n }\n\n\n\n int nums3[] = {36, 12, 24, 26, 29};\n\n int size3 = sizeof(nums3) / sizeof(nums3[0]);\n\n func0(nums3, size3);\n\n int sorted3[] = {12, 24, 26, 29, 36};\n\n for (int i = 0; i < size3; i++) {\n\n assert(nums3[i] == sorted3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov %rdi,%rbp\nmov %esi,%r14d\nmov (%rdi),%r13d\ncmp $0x1,%esi\njle 11e7 \nlea 0x4(%rdi),%rax\nlea -0x2(%rsi),%edx\nlea 0x8(%rdi,%rdx,4),%rcx\nmov (%rax),%edx\ncmp %edx,%r13d\ncmovl %edx,%r13d\nadd $0x4,%rax\ncmp %rcx,%rax\njne 11d5 \nmovslq %r14d,%rdi\nshl $0x2,%rdi\ncallq 10b0 \nmov %rax,%r12\nmov $0x28,%edi\ncallq 10b0 \nmov %rax,%rbx\ntest %r13d,%r13d\njle 130b \nlea -0x1(%r14),%r9d\nmov %rbp,0x8(%rsp)\nlea 0x4(%rbp,%r9,4),%r10\nmov $0x1,%ecx\nlea 0x28(%rax),%r8\nlea -0x1(%r14),%r11d\njmp 124d \nmov (%r12,%rax,4),%edx\nmov %edx,0x0(%rbp,%rax,4)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %r9,%rdx\njne 1229 \nlea (%rcx,%rcx,4),%eax\nadd %eax,%eax\nmov %eax,%ecx\ncmp %r13d,%eax\njg 130b \nmov %rbx,%rax\nmovl $0x0,(%rax)\nadd $0x4,%rax\ncmp %r8,%rax\njne 1250 \ntest %r14d,%r14d\njle 1299 \nmov 0x8(%rsp),%rsi\nmov (%rsi),%eax\ncltd\nidiv %ecx\nmovslq %eax,%rdx\nimul $0x66666667,%rdx,%rdx\nsar $0x22,%rdx\nmov %eax,%edi\nsar $0x1f,%edi\nsub %edi,%edx\nlea (%rdx,%rdx,4),%edx\nadd %edx,%edx\nsub %edx,%eax\ncltq\naddl $0x1,(%rbx,%rax,4)\nadd $0x4,%rsi\ncmp %r10,%rsi\njne 1269 \nlea 0x4(%rbx),%rax\nmov -0x4(%rax),%edx\nadd %edx,(%rax)\nadd $0x4,%rax\ncmp %r8,%rax\njne 129d \ntest %r11d,%r11d\njs 12f8 \nmovslq %r11d,%rsi\nmov 0x0(%rbp,%rsi,4),%edi\nmov %edi,%eax\ncltd\nidiv %ecx\nmovslq %eax,%rdx\nimul $0x66666667,%rdx,%rdx\nsar $0x22,%rdx\nmov %eax,%r15d\nsar $0x1f,%r15d\nsub %r15d,%edx\nlea (%rdx,%rdx,4),%edx\nadd %edx,%edx\nsub %edx,%eax\ncltq\nlea (%rbx,%rax,4),%rdx\nmov (%rdx),%eax\nmovslq %eax,%r15\nmov %edi,-0x4(%r12,%r15,4)\nsub $0x1,%eax\nmov %eax,(%rdx)\nsub $0x1,%rsi\ntest %esi,%esi\njns 12b3 \ntest %r14d,%r14d\njle 123d \nmov $0x0,%eax\njmpq 1229 \nmov %r12,%rdi\ncallq 1080 \nmov %rbx,%rdi\ncallq 1080 \nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov r15d, esi\nmov r14d, [rdi]\ncmp esi, 1\njle short loc_11E7\nlea rax, [rdi+4]\nlea edx, [rsi-2]\nlea rcx, [rdi+rdx*4+8]\nloc_11D5:\nmov edx, [rax]\ncmp r14d, edx\ncmovl r14d, edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_11D5\nloc_11E7:\nmovsxd r13, r15d\nshl r13, 2\nmov rdi, r13; size\ncall _malloc\nmov r12, rax\nmov edi, 28h ; '('; size\ncall _malloc\nmov rbx, rax\ntest r14d, r14d\njle loc_12F5\nlea r8, [r13+rbp+0]\nmov ecx, 1\nlea rdi, [rax+28h]\nlea r9d, [r15-1]\nloc_1221:\nmov rax, rbx\nloc_1224:\nmov dword ptr [rax], 0\nadd rax, 4\ncmp rax, rdi\njnz short loc_1224\ntest r15d, r15d\njle short loc_126E\nmov rsi, rbp\nloc_123B:\nmov eax, [rsi]\ncdq\nidiv ecx\nmovsxd rdx, eax\nimul rdx, 66666667h\nsar rdx, 22h\nmov r10d, eax\nsar r10d, 1Fh\nsub edx, r10d\nlea edx, [rdx+rdx*4]\nadd edx, edx\nsub eax, edx\ncdqe\nadd dword ptr [rbx+rax*4], 1\nadd rsi, 4\ncmp rsi, r8\njnz short loc_123B\nloc_126E:\nlea rax, [rbx+4]\nloc_1272:\nmov edx, [rax-4]\nadd [rax], edx\nadd rax, 4\ncmp rax, rdi\njnz short loc_1272\ntest r9d, r9d\njs short loc_12E5\nmovsxd rsi, r9d\nloc_1288:\nmov r10d, [rbp+rsi*4+0]\nmov eax, r10d\ncdq\nidiv ecx\nmovsxd rdx, eax\nimul rdx, 66666667h\nsar rdx, 22h\nmov r11d, eax\nsar r11d, 1Fh\nsub edx, r11d\nlea edx, [rdx+rdx*4]\nadd edx, edx\nsub eax, edx\ncdqe\nlea rdx, [rbx+rax*4]\nmov eax, [rdx]\nmovsxd r11, eax\nmov [r12+r11*4-4], r10d\nsub eax, 1\nmov [rdx], eax\nsub rsi, 1\ntest esi, esi\njns short loc_1288\nmov eax, 0\nloc_12D4:\nmov edx, [r12+rax]\nmov [rbp+rax+0], edx\nadd rax, 4\ncmp r13, rax\njnz short loc_12D4\nloc_12E5:\nlea eax, [rcx+rcx*4]\nadd eax, eax\nmov ecx, eax\ncmp eax, r14d\njle loc_1221\nloc_12F5:\nmov rdi, r12; ptr\ncall _free\nmov rdi, rbx; ptr\ncall _free\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "void __fastcall func0(int *a1, int a2)\n{\n int v4; // r14d\n int *v5; // rax\n size_t v6; // r13\n _DWORD *v7; // r12\n char *v8; // rax\n _DWORD *v9; // rbx\n int v10; // ecx\n _DWORD *v11; // rdi\n int v12; // r9d\n _DWORD *v13; // rax\n int *v14; // rsi\n _DWORD *v15; // rax\n __int64 v16; // rsi\n int *v17; // rdx\n int v18; // eax\n unsigned __int64 v19; // rax\n\n v4 = *a1;\n if ( a2 > 1 )\n {\n v5 = a1 + 1;\n do\n {\n if ( v4 < *v5 )\n v4 = *v5;\n ++v5;\n }\n while ( v5 != &a1[a2 - 2 + 2] );\n }\n v6 = 4LL * a2;\n v7 = malloc(v6);\n v8 = (char *)malloc(0x28uLL);\n v9 = v8;\n if ( v4 > 0 )\n {\n v10 = 1;\n v11 = v8 + 40;\n v12 = a2 - 1;\n do\n {\n v13 = v9;\n do\n *v13++ = 0;\n while ( v13 != v11 );\n if ( a2 > 0 )\n {\n v14 = a1;\n do\n ++v9[*v14++ / v10 % 10];\n while ( v14 != &a1[v6 / 4] );\n }\n v15 = v9 + 1;\n do\n {\n *v15 += *(v15 - 1);\n ++v15;\n }\n while ( v15 != v11 );\n if ( v12 >= 0 )\n {\n v16 = v12;\n do\n {\n v17 = &v9[a1[v16] / v10 % 10];\n v18 = *v17;\n v7[*v17 - 1] = a1[v16];\n *v17 = v18 - 1;\n --v16;\n }\n while ( (int)v16 >= 0 );\n v19 = 0LL;\n do\n {\n a1[v19 / 4] = v7[v19 / 4];\n v19 += 4LL;\n }\n while ( v6 != v19 );\n }\n v10 *= 10;\n }\n while ( v10 <= v4 );\n }\n free(v7);\n free(v9);\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov r15d, esi\nmov r14d, [rdi]\ncmp esi, 1\njle short loc_11E7\nlea rax, [rdi+4]\nlea edx, [rsi-2]\nlea rcx, [rdi+rdx*4+8]\nloc_11D5:\nmov edx, [rax]\ncmp r14d, edx\ncmovl r14d, edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_11D5\nloc_11E7:\nmovsxd r13, r15d\nshl r13, 2\nmov rdi, r13; size\ncall _malloc\nmov r12, rax\nmov edi, 28h ; '('; size\ncall _malloc\nmov rbx, rax\ntest r14d, r14d\njle loc_12F5\nlea r8, [r13+rbp+0]\nmov ecx, 1\nlea rdi, [rax+28h]\nlea r9d, [r15-1]\nloc_1221:\nmov rax, rbx\nloc_1224:\nmov dword ptr [rax], 0\nadd rax, 4\ncmp rax, rdi\njnz short loc_1224\ntest r15d, r15d\njle short loc_126E\nmov rsi, rbp\nloc_123B:\nmov eax, [rsi]\ncdq\nidiv ecx\nmovsxd rdx, eax\nimul rdx, 66666667h\nsar rdx, 22h\nmov r10d, eax\nsar r10d, 1Fh\nsub edx, r10d\nlea edx, [rdx+rdx*4]\nadd edx, edx\nsub eax, edx\ncdqe\nadd dword ptr [rbx+rax*4], 1\nadd rsi, 4\ncmp rsi, r8\njnz short loc_123B\nloc_126E:\nlea rax, [rbx+4]\nloc_1272:\nmov edx, [rax-4]\nadd [rax], edx\nadd rax, 4\ncmp rax, rdi\njnz short loc_1272\ntest r9d, r9d\njs short loc_12E5\nmovsxd rsi, r9d\nloc_1288:\nmov r10d, [rbp+rsi*4+0]\nmov eax, r10d\ncdq\nidiv ecx\nmovsxd rdx, eax\nimul rdx, 66666667h\nsar rdx, 22h\nmov r11d, eax\nsar r11d, 1Fh\nsub edx, r11d\nlea edx, [rdx+rdx*4]\nadd edx, edx\nsub eax, edx\ncdqe\nlea rdx, [rbx+rax*4]\nmov eax, [rdx]\nmovsxd r11, eax\nmov [r12+r11*4-4], r10d\nsub eax, 1\nmov [rdx], eax\nsub rsi, 1\ntest esi, esi\njns short loc_1288\nmov eax, 0\nloc_12D4:\nmov edx, [r12+rax]\nmov [rbp+rax+0], edx\nadd rax, 4\ncmp r13, rax\njnz short loc_12D4\nloc_12E5:\nlea eax, [rcx+rcx*4]\nadd eax, eax\nmov ecx, eax\ncmp eax, r14d\njle loc_1221\nloc_12F5:\nmov rdi, r12; ptr\ncall _free\nmov rdi, rbx; ptr\ncall _free\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "void __fastcall sub_11A9(int *a1, int a2)\n{\n int v4; // r14d\n int *v5; // rax\n size_t v6; // r13\n _DWORD *v7; // r12\n char *v8; // rax\n _DWORD *v9; // rbx\n int v10; // ecx\n _DWORD *v11; // rdi\n int v12; // r9d\n _DWORD *v13; // rax\n int *v14; // rsi\n _DWORD *v15; // rax\n __int64 v16; // rsi\n int *v17; // rdx\n int v18; // eax\n unsigned __int64 v19; // rax\n\n v4 = *a1;\n if ( a2 > 1 )\n {\n v5 = a1 + 1;\n do\n {\n if ( v4 < *v5 )\n v4 = *v5;\n ++v5;\n }\n while ( v5 != &a1[a2 - 2 + 2] );\n }\n v6 = 4LL * a2;\n v7 = malloc(v6);\n v8 = (char *)malloc(0x28uLL);\n v9 = v8;\n if ( v4 > 0 )\n {\n v10 = 1;\n v11 = v8 + 40;\n v12 = a2 - 1;\n do\n {\n v13 = v9;\n do\n *v13++ = 0;\n while ( v13 != v11 );\n if ( a2 > 0 )\n {\n v14 = a1;\n do\n ++v9[*v14++ / v10 % 10];\n while ( v14 != &a1[v6 / 4] );\n }\n v15 = v9 + 1;\n do\n {\n *v15 += *(v15 - 1);\n ++v15;\n }\n while ( v15 != v11 );\n if ( v12 >= 0 )\n {\n v16 = v12;\n do\n {\n v17 = &v9[a1[v16] / v10 % 10];\n v18 = *v17;\n v7[*v17 - 1] = a1[v16];\n *v17 = v18 - 1;\n --v16;\n }\n while ( (int)v16 >= 0 );\n v19 = 0LL;\n do\n {\n a1[v19 / 4] = v7[v19 / 4];\n v19 += 4LL;\n }\n while ( v6 != v19 );\n }\n v10 *= 10;\n }\n while ( v10 <= v4 );\n }\n free(v7);\n free(v9);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_11A9(int *a1, int a2) {\n int v4;\n int *v5;\n unsigned int v6;\n uint32_t *v7;\n char *v8;\n uint32_t *v9;\n int v10;\n uint32_t *v11;\n int v12;\n uint32_t *v13;\n int *v14;\n uint32_t *v15;\n long long v16;\n int *v17;\n int v18;\n unsigned long long v19;\n v4 = *a1;\n if (a2 > 1) {\n v5 = a1 + 1;\n do {\n if (v4 < *v5) v4 = *v5;\n ++v5;\n } while (v5 != &a1[a2 - 2 + 2]);\n }\n v6 = 4LL * a2;\n v7 = malloc(v6);\n v8 = (char *)malloc(40uLL);\n v9 = v8;\n if (v4 > 0) {\n v10 = 1;\n v11 = v8 + 40;\n v12 = a2 - 1;\n do {\n v13 = v9;\n do\n *v13++ = 0;\n while (v13 != v11);\n if (a2 > 0) {\n v14 = a1;\n do\n ++v9[*v14++ / v10 % 10];\n while (v14 != &a1[v6 / 4]);\n }\n v15 = v9 + 1;\n do {\n *v15 += *(v15 - 1);\n ++v15;\n } while (v15 != v11);\n if (v12 >= 0) {\n v16 = v12;\n do {\n v17 = &v9[a1[v16] / v10 % 10];\n v18 = *v17;\n v7[*v17 - 1] = a1[v16];\n *v17 = v18 - 1;\n --v16;\n } while ((int)v16 >= 0);\n v19 = 0LL;\n do {\n a1[v19 / 4] = v7[v19 / 4];\n v19 += 4LL;\n } while (v6 != v19);\n }\n v10 *= 10;\n } while (v10 <= v4);\n }\n free(v7);\n free(v9);\n}", + "ida_pseudo_norm": "void func0(int *a1, int a2) {\n int v4;\n int *v5;\n unsigned int v6;\n uint32_t *v7;\n char *v8;\n uint32_t *v9;\n int v10;\n uint32_t *v11;\n int v12;\n uint32_t *v13;\n int *v14;\n uint32_t *v15;\n long long v16;\n int *v17;\n int v18;\n unsigned long long v19;\n v4 = *a1;\n if (a2 > 1) {\n v5 = a1 + 1;\n do {\n if (v4 < *v5) v4 = *v5;\n ++v5;\n } while (v5 != &a1[a2 - 2 + 2]);\n }\n v6 = 4LL * a2;\n v7 = malloc(v6);\n v8 = (char *)malloc(40uLL);\n v9 = v8;\n if (v4 > 0) {\n v10 = 1;\n v11 = v8 + 40;\n v12 = a2 - 1;\n do {\n v13 = v9;\n do\n *v13++ = 0;\n while (v13 != v11);\n if (a2 > 0) {\n v14 = a1;\n do\n ++v9[*v14++ / v10 % 10];\n while (v14 != &a1[v6 / 4]);\n }\n v15 = v9 + 1;\n do {\n *v15 += *(v15 - 1);\n ++v15;\n } while (v15 != v11);\n if (v12 >= 0) {\n v16 = v12;\n do {\n v17 = &v9[a1[v16] / v10 % 10];\n v18 = *v17;\n v7[*v17 - 1] = a1[v16];\n *v17 = v18 - 1;\n --v16;\n } while ((int)v16 >= 0);\n v19 = 0LL;\n do {\n a1[v19 / 4] = v7[v19 / 4];\n v19 += 4LL;\n } while (v6 != v19);\n }\n v10 *= 10;\n } while (v10 <= v4);\n }\n free(v7);\n free(v9);\n}" + }, + { + "index": 516, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n#define RADIX 10\n\n\n\n", + "func": "void func0(int *nums, int size) {\n int placement = 1;\n int max_digit = nums[0];\n for (int i = 1; i < size; i++) {\n if (nums[i] > max_digit) {\n max_digit = nums[i];\n }\n }\n int *output = (int *)malloc(size * sizeof(int));\n int *count = (int *)malloc(RADIX * sizeof(int));\n while (placement <= max_digit) {\n for (int i = 0; i < RADIX; i++) {\n count[i] = 0;\n }\n for (int i = 0; i < size; i++) {\n int index = (nums[i] / placement) % RADIX;\n count[index]++;\n }\n for (int i = 1; i < RADIX; i++) {\n count[i] += count[i - 1];\n }\n for (int i = size - 1; i >= 0; i--) {\n int index = (nums[i] / placement) % RADIX;\n output[count[index] - 1] = nums[i];\n count[index]--;\n }\n for (int i = 0; i < size; i++) {\n nums[i] = output[i];\n }\n placement *= RADIX;\n }\n free(output);\n free(count);\n}", + "test": "int main() {\n\n int nums1[] = {15, 79, 25, 68, 37};\n\n int size1 = sizeof(nums1) / sizeof(nums1[0]);\n\n func0(nums1, size1);\n\n int sorted1[] = {15, 25, 37, 68, 79};\n\n for (int i = 0; i < size1; i++) {\n\n assert(nums1[i] == sorted1[i]);\n\n }\n\n\n\n int nums2[] = {9, 11, 8, 7, 3, 2};\n\n int size2 = sizeof(nums2) / sizeof(nums2[0]);\n\n func0(nums2, size2);\n\n int sorted2[] = {2, 3, 7, 8, 9, 11};\n\n for (int i = 0; i < size2; i++) {\n\n assert(nums2[i] == sorted2[i]);\n\n }\n\n\n\n int nums3[] = {36, 12, 24, 26, 29};\n\n int size3 = sizeof(nums3) / sizeof(nums3[0]);\n\n func0(nums3, size3);\n\n int sorted3[] = {12, 24, 26, 29, 36};\n\n for (int i = 0; i < size3; i++) {\n\n assert(nums3[i] == sorted3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\nmov %esi,%r14d\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nsub $0x18,%rsp\nmov (%rdi),%r13d\ncmp $0x1,%esi\njle 1422 \nlea -0x2(%rsi),%edx\nlea 0x4(%rdi),%rax\nlea 0x8(%rdi,%rdx,4),%rcx\nnopl 0x0(%rax)\nmov (%rax),%edx\ncmp %edx,%r13d\ncmovl %edx,%r13d\nadd $0x4,%rax\ncmp %rax,%rcx\njne 1410 \nmovslq %r14d,%rdi\nshl $0x2,%rdi\ncallq 10b0 \nmov $0x28,%edi\nmov %rax,%r12\ncallq 10b0 \nmov %rax,%rbp\ntest %r13d,%r13d\njle 1561 \nlea 0x28(%rax),%r9\nlea 0x4(%rax),%rax\nmov $0x1,%ecx\nmov %rax,0x8(%rsp)\nlea -0x1(%r14),%r10d\nmov %r10,%rsi\nlea 0x4(%rbx,%r10,4),%r11\nnopl (%rax)\nmov %rbp,%rax\nnopl 0x0(%rax,%rax,1)\nmovl $0x0,(%rax)\nadd $0x4,%rax\ncmp %rax,%r9\njne 1470 \nmov %rbx,%rdi\ntest %r14d,%r14d\njle 14c4 \nnopw 0x0(%rax,%rax,1)\nmov (%rdi),%eax\nadd $0x4,%rdi\ncltd\nidiv %ecx\nmovslq %eax,%rdx\nmov %eax,%r8d\nimul $0x66666667,%rdx,%rdx\nsar $0x1f,%r8d\nsar $0x22,%rdx\nsub %r8d,%edx\nlea (%rdx,%rdx,4),%edx\nadd %edx,%edx\nsub %edx,%eax\ncltq\naddl $0x1,0x0(%rbp,%rax,4)\ncmp %rdi,%r11\njne 1490 \nmov 0x8(%rsp),%rax\nnopl 0x0(%rax)\nmov -0x4(%rax),%edx\nadd %edx,(%rax)\nadd $0x4,%rax\ncmp %rax,%r9\njne 14d0 \nmovslq %esi,%rdi\ntest %esi,%esi\njs 1530 \nnopl (%rax)\nmov (%rbx,%rdi,4),%r8d\nsub $0x1,%rdi\nmov %r8d,%eax\ncltd\nidiv %ecx\nmovslq %eax,%rdx\nmov %eax,%r15d\nimul $0x66666667,%rdx,%rdx\nsar $0x1f,%r15d\nsar $0x22,%rdx\nsub %r15d,%edx\nlea (%rdx,%rdx,4),%edx\nadd %edx,%edx\nsub %edx,%eax\ncltq\nlea 0x0(%rbp,%rax,4),%rdx\nmovslq (%rdx),%r15\nmov %r15,%rax\nmov %r8d,-0x4(%r12,%r15,4)\nsub $0x1,%eax\nmov %eax,(%rdx)\ntest %edi,%edi\njns 14e8 \nxor %eax,%eax\ntest %r14d,%r14d\njle 1553 \nnopw 0x0(%rax,%rax,1)\nmov (%r12,%rax,4),%edx\nmov %edx,(%rbx,%rax,4)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rdx,%r10\njne 1540 \nlea (%rcx,%rcx,4),%ecx\nadd %ecx,%ecx\ncmp %r13d,%ecx\njle 1468 \nmov %r12,%rdi\ncallq 1080 \nadd $0x18,%rsp\nmov %rbp,%rdi\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\njmpq 1080 \n", + "ida_asm": "func0:\nendbr64\npush r15\nmov r8d, esi\npush r14\npush r13\nmov r13, rdi\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov ebp, [rdi]\ncmp esi, 1\njle short loc_1408\nlea edx, [rsi-2]\nlea rax, [rdi+4]\nlea rcx, [rdi+rdx*4+8]\nmov rdx, rcx\nsub rdx, rax\nand edx, 4\njz short loc_13F0\nmov eax, [rax]\ncmp ebp, eax\ncmovl ebp, eax\nlea rax, [rdi+8]\ncmp rcx, rax\njz short loc_1408\nnop word ptr [rax+rax+00000000h]\nloc_13F0:\nmov edx, [rax]\ncmp ebp, edx\ncmovl ebp, edx\nmov edx, [rax+4]\ncmp ebp, edx\ncmovl ebp, edx\nadd rax, 8\ncmp rcx, rax\njnz short loc_13F0\nloc_1408:\nmovsxd r15, r8d\nmov [rsp+58h+var_48], r8d\nshl r15, 2\nmov rdi, r15; size\ncall _malloc\nmov edi, 28h ; '('; size\nmov [rsp+58h+src], rax\ncall _malloc\ntest ebp, ebp\nmov r9, [rsp+58h+src]\nmov r12, rax\njle loc_1580\nmov r8d, [rsp+58h+var_48]\nadd r15, r13\nlea r14, [r12+28h]\nmov rcx, r13\nmov [rsp+58h+var_48], ebp\nmov r13, r15\nmov ebx, 1\nmov r15, r14\nlea eax, [r8-1]\npxor xmm0, xmm0\nmov ebp, r8d\nmov r14, r9\nmov rdi, rax\nlea rax, ds:4[rax*4]\nmov [rsp+58h+n], rax\nlea rax, [r12+4]\nmov [rsp+58h+src], rax\nmov [rsp+58h+var_44], edi\nnop word ptr [rax+rax+00000000h]\nloc_1490:\nmov qword ptr [r12+20h], 0\nmov rsi, rcx\nmovups xmmword ptr [r12], xmm0\nmovups xmmword ptr [r12+10h], xmm0\ntest ebp, ebp\njle short loc_14E1\nnop dword ptr [rax+rax+00h]\nloc_14B0:\nmov eax, [rsi]\nadd rsi, 4\ncdq\nidiv ebx\nmovsxd rdx, eax\nmov edi, eax\nimul rdx, 66666667h\nsar edi, 1Fh\nsar rdx, 22h\nsub edx, edi\nlea edx, [rdx+rdx*4]\nadd edx, edx\nsub eax, edx\ncdqe\nadd dword ptr [r12+rax*4], 1\ncmp rsi, r13\njnz short loc_14B0\nloc_14E1:\nmov edx, [r12]\nmov rax, [rsp+58h+src]\nnop word ptr [rax+rax+00h]\nloc_14F0:\nadd edx, [rax]\nadd rax, 4\nmov [rax-4], edx\ncmp rax, r15\njnz short loc_14F0\nmovsxd rdi, [rsp+58h+var_44]\ntest ebp, ebp\njle short loc_156C\nnop word ptr [rax+rax+00000000h]\nloc_1510:\nmov esi, [rcx+rdi*4]\nsub rdi, 1\nmov eax, esi\ncdq\nidiv ebx\nmovsxd rdx, eax\nmov r8d, eax\nimul rdx, 66666667h\nsar r8d, 1Fh\nsar rdx, 22h\nsub edx, r8d\nlea edx, [rdx+rdx*4]\nadd edx, edx\nsub eax, edx\ncdqe\nlea rdx, [r12+rax*4]\nmovsxd r8, dword ptr [rdx]\nmov rax, r8\nmov [r14+r8*4-4], esi\nsub eax, 1\nmov [rdx], eax\ntest edi, edi\njns short loc_1510\nmov rdx, [rsp+58h+n]; n\nmov rdi, rcx; dest\nmov rsi, r14; src\ncall _memcpy\npxor xmm0, xmm0\nmov rcx, rax\nloc_156C:\nlea ebx, [rbx+rbx*4]\nmov eax, [rsp+58h+var_48]\nadd ebx, ebx\ncmp ebx, eax\njle loc_1490\nmov r9, r14\nloc_1580:\nmov rdi, r9; ptr\ncall _free\nadd rsp, 28h\nmov rdi, r12; ptr\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\njmp _free", + "ida_pseudo": "void __fastcall func0(char *dest, int a2)\n{\n int v2; // ebp\n char *v3; // rax\n char *v4; // rcx\n int v5; // eax\n char *v6; // rax\n void *v7; // r9\n char *v8; // r12\n char *v9; // rcx\n char *v10; // r13\n int v11; // ebx\n _DWORD *v12; // r15\n __int128 v13; // xmm0\n char *v15; // rsi\n int v16; // eax\n int v17; // edx\n _DWORD *v18; // rax\n __int64 v19; // rdi\n int v20; // esi\n char *v21; // rdx\n int v22; // eax\n void *src; // [rsp+8h] [rbp-50h]\n int v24; // [rsp+10h] [rbp-48h]\n int v25; // [rsp+14h] [rbp-44h]\n __int64 n; // [rsp+18h] [rbp-40h]\n\n v2 = *(_DWORD *)dest;\n if ( a2 > 1 )\n {\n v3 = dest + 4;\n v4 = &dest[4 * (a2 - 2) + 8];\n if ( ((4 * ((_BYTE)a2 - 2) + 4) & 4) == 0 )\n goto LABEL_25;\n v5 = *(_DWORD *)v3;\n if ( v2 < v5 )\n v2 = v5;\n v3 = dest + 8;\n if ( v4 != dest + 8 )\n {\nLABEL_25:\n do\n {\n if ( v2 < *(_DWORD *)v3 )\n v2 = *(_DWORD *)v3;\n if ( v2 < *((_DWORD *)v3 + 1) )\n v2 = *((_DWORD *)v3 + 1);\n v3 += 8;\n }\n while ( v4 != v3 );\n }\n }\n src = malloc(4LL * a2);\n v6 = (char *)malloc(0x28uLL);\n v7 = src;\n v8 = v6;\n if ( v2 > 0 )\n {\n v9 = dest;\n v24 = v2;\n v10 = &dest[4 * a2];\n v11 = 1;\n v12 = v6 + 40;\n v13 = 0LL;\n n = 4LL * (unsigned int)(a2 - 1) + 4;\n v25 = a2 - 1;\n do\n {\n *((_QWORD *)v8 + 4) = 0LL;\n v15 = v9;\n *(_OWORD *)v8 = v13;\n *((_OWORD *)v8 + 1) = v13;\n if ( a2 > 0 )\n {\n do\n {\n v16 = *(_DWORD *)v15;\n v15 += 4;\n ++*(_DWORD *)&v8[4 * (v16 / v11 % 10)];\n }\n while ( v15 != v10 );\n }\n v17 = *(_DWORD *)v8;\n v18 = v8 + 4;\n do\n {\n v17 += *v18++;\n *(v18 - 1) = v17;\n }\n while ( v18 != v12 );\n v19 = v25;\n if ( a2 > 0 )\n {\n do\n {\n v20 = *(_DWORD *)&v9[4 * v19--];\n v21 = &v8[4 * (v20 / v11 % 10)];\n v22 = *(_DWORD *)v21;\n *((_DWORD *)src + *(int *)v21 - 1) = v20;\n *(_DWORD *)v21 = v22 - 1;\n }\n while ( (int)v19 >= 0 );\n v13 = 0LL;\n v9 = (char *)memcpy(v9, src, n);\n }\n v11 *= 10;\n }\n while ( v11 <= v24 );\n v7 = src;\n }\n free(v7);\n free(v8);\n}", + "ida_strip_asm": "sub_13A0:\nendbr64\npush r15\nmov r8d, esi\npush r14\npush r13\nmov r13, rdi\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov ebp, [rdi]\ncmp esi, 1\njle short loc_1408\nlea edx, [rsi-2]\nlea rax, [rdi+4]\nlea rcx, [rdi+rdx*4+8]\nmov rdx, rcx\nsub rdx, rax\nand edx, 4\njz short loc_13F0\nmov eax, [rax]\ncmp ebp, eax\ncmovl ebp, eax\nlea rax, [rdi+8]\ncmp rcx, rax\njz short loc_1408\nnop word ptr [rax+rax+00000000h]\nloc_13F0:\nmov edx, [rax]\ncmp ebp, edx\ncmovl ebp, edx\nmov edx, [rax+4]\ncmp ebp, edx\ncmovl ebp, edx\nadd rax, 8\ncmp rcx, rax\njnz short loc_13F0\nloc_1408:\nmovsxd r15, r8d\nmov [rsp+58h+var_48], r8d\nshl r15, 2\nmov rdi, r15; size\ncall _malloc\nmov edi, 28h ; '('; size\nmov [rsp+58h+src], rax\ncall _malloc\ntest ebp, ebp\nmov r9, [rsp+58h+src]\nmov r12, rax\njle loc_1580\nmov r8d, [rsp+58h+var_48]\nadd r15, r13\nlea r14, [r12+28h]\nmov rcx, r13\nmov [rsp+58h+var_48], ebp\nmov r13, r15\nmov ebx, 1\nmov r15, r14\nlea eax, [r8-1]\npxor xmm0, xmm0\nmov ebp, r8d\nmov r14, r9\nmov rdi, rax\nlea rax, ds:4[rax*4]\nmov [rsp+58h+n], rax\nlea rax, [r12+4]\nmov [rsp+58h+src], rax\nmov [rsp+58h+var_44], edi\nnop word ptr [rax+rax+00000000h]\nloc_1490:\nmov qword ptr [r12+20h], 0\nmov rsi, rcx\nmovups xmmword ptr [r12], xmm0\nmovups xmmword ptr [r12+10h], xmm0\ntest ebp, ebp\njle short loc_14E1\nnop dword ptr [rax+rax+00h]\nloc_14B0:\nmov eax, [rsi]\nadd rsi, 4\ncdq\nidiv ebx\nmovsxd rdx, eax\nmov edi, eax\nimul rdx, 66666667h\nsar edi, 1Fh\nsar rdx, 22h\nsub edx, edi\nlea edx, [rdx+rdx*4]\nadd edx, edx\nsub eax, edx\ncdqe\nadd dword ptr [r12+rax*4], 1\ncmp rsi, r13\njnz short loc_14B0\nloc_14E1:\nmov edx, [r12]\nmov rax, [rsp+58h+src]\nnop word ptr [rax+rax+00h]\nloc_14F0:\nadd edx, [rax]\nadd rax, 4\nmov [rax-4], edx\ncmp rax, r15\njnz short loc_14F0\nmovsxd rdi, [rsp+58h+var_44]\ntest ebp, ebp\njle short loc_156C\nnop word ptr [rax+rax+00000000h]\nloc_1510:\nmov esi, [rcx+rdi*4]\nsub rdi, 1\nmov eax, esi\ncdq\nidiv ebx\nmovsxd rdx, eax\nmov r8d, eax\nimul rdx, 66666667h\nsar r8d, 1Fh\nsar rdx, 22h\nsub edx, r8d\nlea edx, [rdx+rdx*4]\nadd edx, edx\nsub eax, edx\ncdqe\nlea rdx, [r12+rax*4]\nmovsxd r8, dword ptr [rdx]\nmov rax, r8\nmov [r14+r8*4-4], esi\nsub eax, 1\nmov [rdx], eax\ntest edi, edi\njns short loc_1510\nmov rdx, [rsp+58h+n]; n\nmov rdi, rcx; dest\nmov rsi, r14; src\ncall _memcpy\npxor xmm0, xmm0\nmov rcx, rax\nloc_156C:\nlea ebx, [rbx+rbx*4]\nmov eax, [rsp+58h+var_48]\nadd ebx, ebx\ncmp ebx, eax\njle loc_1490\nmov r9, r14\nloc_1580:\nmov rdi, r9; ptr\ncall _free\nadd rsp, 28h\nmov rdi, r12; ptr\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\njmp _free", + "ida_strip_pseudo": "void __fastcall sub_13A0(char *dest, int a2)\n{\n int v2; // ebp\n char *v3; // rax\n char *v4; // rcx\n int v5; // eax\n char *v6; // rax\n void *v7; // r9\n char *v8; // r12\n char *v9; // rcx\n char *v10; // r13\n int v11; // ebx\n _DWORD *v12; // r15\n __int128 v13; // xmm0\n char *v15; // rsi\n int v16; // eax\n int v17; // edx\n _DWORD *v18; // rax\n __int64 v19; // rdi\n int v20; // esi\n char *v21; // rdx\n int v22; // eax\n void *src; // [rsp+8h] [rbp-50h]\n int v24; // [rsp+10h] [rbp-48h]\n int v25; // [rsp+14h] [rbp-44h]\n __int64 n; // [rsp+18h] [rbp-40h]\n\n v2 = *(_DWORD *)dest;\n if ( a2 > 1 )\n {\n v3 = dest + 4;\n v4 = &dest[4 * (a2 - 2) + 8];\n if ( ((4 * ((_BYTE)a2 - 2) + 4) & 4) == 0 )\n goto LABEL_25;\n v5 = *(_DWORD *)v3;\n if ( v2 < v5 )\n v2 = v5;\n v3 = dest + 8;\n if ( v4 != dest + 8 )\n {\nLABEL_25:\n do\n {\n if ( v2 < *(_DWORD *)v3 )\n v2 = *(_DWORD *)v3;\n if ( v2 < *((_DWORD *)v3 + 1) )\n v2 = *((_DWORD *)v3 + 1);\n v3 += 8;\n }\n while ( v4 != v3 );\n }\n }\n src = malloc(4LL * a2);\n v6 = (char *)malloc(0x28uLL);\n v7 = src;\n v8 = v6;\n if ( v2 > 0 )\n {\n v9 = dest;\n v24 = v2;\n v10 = &dest[4 * a2];\n v11 = 1;\n v12 = v6 + 40;\n v13 = 0LL;\n n = 4LL * (unsigned int)(a2 - 1) + 4;\n v25 = a2 - 1;\n do\n {\n *((_QWORD *)v8 + 4) = 0LL;\n v15 = v9;\n *(_OWORD *)v8 = v13;\n *((_OWORD *)v8 + 1) = v13;\n if ( a2 > 0 )\n {\n do\n {\n v16 = *(_DWORD *)v15;\n v15 += 4;\n ++*(_DWORD *)&v8[4 * (v16 / v11 % 10)];\n }\n while ( v15 != v10 );\n }\n v17 = *(_DWORD *)v8;\n v18 = v8 + 4;\n do\n {\n v17 += *v18++;\n *(v18 - 1) = v17;\n }\n while ( v18 != v12 );\n v19 = v25;\n if ( a2 > 0 )\n {\n do\n {\n v20 = *(_DWORD *)&v9[4 * v19--];\n v21 = &v8[4 * (v20 / v11 % 10)];\n v22 = *(_DWORD *)v21;\n *((_DWORD *)src + *(int *)v21 - 1) = v20;\n *(_DWORD *)v21 = v22 - 1;\n }\n while ( (int)v19 >= 0 );\n v13 = 0LL;\n v9 = (char *)memcpy(v9, src, n);\n }\n v11 *= 10;\n }\n while ( v11 <= v24 );\n v7 = src;\n }\n free(v7);\n free(v8);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_13A0(char *dest, int a2) {\n int v2;\n char *v3;\n char *v4;\n int v5;\n char *v6;\n void *v7;\n char *v8;\n char *v9;\n char *v10;\n int v11;\n uint32_t *v12;\n __int128 v13;\n char *v15;\n int v16;\n int v17;\n uint32_t *v18;\n long long v19;\n int v20;\n char *v21;\n int v22;\n void *src;\n int v24;\n int v25;\n long long n;\n v2 = *(uint32_t *)dest;\n if (a2 > 1) {\n v3 = dest + 4;\n v4 = &dest[4 * (a2 - 2) + 8];\n if (((4 * ((uint8_t)a2 - 2) + 4) & 4) == 0) goto LABEL_25;\n v5 = *(uint32_t *)v3;\n if (v2 < v5) v2 = v5;\n v3 = dest + 8;\n if (v4 != dest + 8) {\n LABEL_25:\n do {\n if (v2 < *(uint32_t *)v3) v2 = *(uint32_t *)v3;\n if (v2 < *((uint32_t *)v3 + 1)) v2 = *((uint32_t *)v3 + 1);\n v3 += 8;\n } while (v4 != v3);\n }\n }\n src = malloc(4LL * a2);\n v6 = (char *)malloc(40uLL);\n v7 = src;\n v8 = v6;\n if (v2 > 0) {\n v9 = dest;\n v24 = v2;\n v10 = &dest[4 * a2];\n v11 = 1;\n v12 = v6 + 40;\n v13 = 0LL;\n n = 4LL * (unsigned int)(a2 - 1) + 4;\n v25 = a2 - 1;\n do {\n *((uint64_t *)v8 + 4) = 0LL;\n v15 = v9;\n *(long double *)v8 = v13;\n *((long double *)v8 + 1) = v13;\n if (a2 > 0) {\n do {\n v16 = *(uint32_t *)v15;\n v15 += 4;\n ++*(uint32_t *)&v8[4 * (v16 / v11 % 10)];\n } while (v15 != v10);\n }\n v17 = *(uint32_t *)v8;\n v18 = v8 + 4;\n do {\n v17 += *v18++;\n *(v18 - 1) = v17;\n } while (v18 != v12);\n v19 = v25;\n if (a2 > 0) {\n do {\n v20 = *(uint32_t *)&v9[4 * v19--];\n v21 = &v8[4 * (v20 / v11 % 10)];\n v22 = *(uint32_t *)v21;\n *((uint32_t *)src + *(int *)v21 - 1) = v20;\n *(uint32_t *)v21 = v22 - 1;\n } while ((int)v19 >= 0);\n v13 = 0LL;\n v9 = (char *)memcpy(v9, src, n);\n }\n v11 *= 10;\n } while (v11 <= v24);\n v7 = src;\n }\n free(v7);\n free(v8);\n}", + "ida_pseudo_norm": "void func0(char *dest, int a2) {\n int v2;\n char *v3;\n char *v4;\n int v5;\n char *v6;\n void *v7;\n char *v8;\n char *v9;\n char *v10;\n int v11;\n uint32_t *v12;\n __int128 v13;\n char *v15;\n int v16;\n int v17;\n uint32_t *v18;\n long long v19;\n int v20;\n char *v21;\n int v22;\n void *src;\n int v24;\n int v25;\n long long n;\n v2 = *(uint32_t *)dest;\n if (a2 > 1) {\n v3 = dest + 4;\n v4 = &dest[4 * (a2 - 2) + 8];\n if (((4 * ((uint8_t)a2 - 2) + 4) & 4) == 0) goto LABEL_25;\n v5 = *(uint32_t *)v3;\n if (v2 < v5) v2 = v5;\n v3 = dest + 8;\n if (v4 != dest + 8) {\n LABEL_25:\n do {\n if (v2 < *(uint32_t *)v3) v2 = *(uint32_t *)v3;\n if (v2 < *((uint32_t *)v3 + 1)) v2 = *((uint32_t *)v3 + 1);\n v3 += 8;\n } while (v4 != v3);\n }\n }\n src = malloc(4LL * a2);\n v6 = (char *)malloc(40uLL);\n v7 = src;\n v8 = v6;\n if (v2 > 0) {\n v9 = dest;\n v24 = v2;\n v10 = &dest[4 * a2];\n v11 = 1;\n v12 = v6 + 40;\n v13 = 0LL;\n n = 4LL * (unsigned int)(a2 - 1) + 4;\n v25 = a2 - 1;\n do {\n *((uint64_t *)v8 + 4) = 0LL;\n v15 = v9;\n *(long double *)v8 = v13;\n *((long double *)v8 + 1) = v13;\n if (a2 > 0) {\n do {\n v16 = *(uint32_t *)v15;\n v15 += 4;\n ++*(uint32_t *)&v8[4 * (v16 / v11 % 10)];\n } while (v15 != v10);\n }\n v17 = *(uint32_t *)v8;\n v18 = v8 + 4;\n do {\n v17 += *v18++;\n *(v18 - 1) = v17;\n } while (v18 != v12);\n v19 = v25;\n if (a2 > 0) {\n do {\n v20 = *(uint32_t *)&v9[4 * v19--];\n v21 = &v8[4 * (v20 / v11 % 10)];\n v22 = *(uint32_t *)v21;\n *((uint32_t *)src + *(int *)v21 - 1) = v20;\n *(uint32_t *)v21 = v22 - 1;\n } while ((int)v19 >= 0);\n v13 = 0LL;\n v9 = (char *)memcpy(v9, src, n);\n }\n v11 *= 10;\n } while (v11 <= v24);\n v7 = src;\n }\n free(v7);\n free(v8);\n}" + }, + { + "index": 516, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n#define RADIX 10\n\n\n\n", + "func": "void func0(int *nums, int size) {\n int placement = 1;\n int max_digit = nums[0];\n for (int i = 1; i < size; i++) {\n if (nums[i] > max_digit) {\n max_digit = nums[i];\n }\n }\n int *output = (int *)malloc(size * sizeof(int));\n int *count = (int *)malloc(RADIX * sizeof(int));\n while (placement <= max_digit) {\n for (int i = 0; i < RADIX; i++) {\n count[i] = 0;\n }\n for (int i = 0; i < size; i++) {\n int index = (nums[i] / placement) % RADIX;\n count[index]++;\n }\n for (int i = 1; i < RADIX; i++) {\n count[i] += count[i - 1];\n }\n for (int i = size - 1; i >= 0; i--) {\n int index = (nums[i] / placement) % RADIX;\n output[count[index] - 1] = nums[i];\n count[index]--;\n }\n for (int i = 0; i < size; i++) {\n nums[i] = output[i];\n }\n placement *= RADIX;\n }\n free(output);\n free(count);\n}", + "test": "int main() {\n\n int nums1[] = {15, 79, 25, 68, 37};\n\n int size1 = sizeof(nums1) / sizeof(nums1[0]);\n\n func0(nums1, size1);\n\n int sorted1[] = {15, 25, 37, 68, 79};\n\n for (int i = 0; i < size1; i++) {\n\n assert(nums1[i] == sorted1[i]);\n\n }\n\n\n\n int nums2[] = {9, 11, 8, 7, 3, 2};\n\n int size2 = sizeof(nums2) / sizeof(nums2[0]);\n\n func0(nums2, size2);\n\n int sorted2[] = {2, 3, 7, 8, 9, 11};\n\n for (int i = 0; i < size2; i++) {\n\n assert(nums2[i] == sorted2[i]);\n\n }\n\n\n\n int nums3[] = {36, 12, 24, 26, 29};\n\n int size3 = sizeof(nums3) / sizeof(nums3[0]);\n\n func0(nums3, size3);\n\n int sorted3[] = {12, 24, 26, 29, 36};\n\n for (int i = 0; i < size3; i++) {\n\n assert(nums3[i] == sorted3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmov %esi,%r15d\npush %r14\npush %r13\npush %r12\nmov %rdi,%r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov (%rdi),%ebx\nmov %ebx,(%rsp)\ncmp $0x1,%esi\njle 14f6 \nlea -0x2(%rsi),%eax\nlea -0x1(%rsi),%ecx\ncmp $0x2,%eax\njbe 16c4 \nmov %ecx,%edx\nmovd %ebx,%xmm7\nmov %rdi,%rax\nshr $0x2,%edx\npshufd $0x0,%xmm7,%xmm0\nshl $0x4,%rdx\nadd %rdi,%rdx\nnopl (%rax)\nmovdqu 0x4(%rax),%xmm2\nadd $0x10,%rax\nmovdqa %xmm2,%xmm1\npcmpgtd %xmm0,%xmm1\npand %xmm1,%xmm2\npandn %xmm0,%xmm1\nmovdqa %xmm1,%xmm0\npor %xmm2,%xmm0\ncmp %rax,%rdx\njne 1440 \nmovdqa %xmm0,%xmm2\nmov %ecx,%edx\npsrldq $0x8,%xmm2\nand $0xfffffffc,%edx\nmovdqa %xmm2,%xmm1\nlea 0x1(%rdx),%eax\npcmpgtd %xmm0,%xmm1\npand %xmm1,%xmm2\npandn %xmm0,%xmm1\nmovdqa %xmm1,%xmm0\npor %xmm2,%xmm0\nmovdqa %xmm0,%xmm2\npsrldq $0x4,%xmm2\nmovdqa %xmm2,%xmm1\npcmpgtd %xmm0,%xmm1\npand %xmm1,%xmm2\npandn %xmm0,%xmm1\npor %xmm2,%xmm1\nmovd %xmm1,(%rsp)\ncmp %edx,%ecx\nje 14f6 \nmovslq %eax,%rdx\nmov (%rsp),%ecx\nmov (%r12,%rdx,4),%edx\ncmp %edx,%ecx\nmov %edx,%ebx\nlea 0x1(%rax),%edx\ncmovge %ecx,%ebx\nmov %ebx,(%rsp)\ncmp %edx,%r15d\njle 14f6 \nmovslq %edx,%rdx\nmov (%r12,%rdx,4),%edx\ncmp %edx,%ebx\ncmovge %ebx,%edx\nadd $0x2,%eax\nmov %edx,(%rsp)\ncmp %eax,%r15d\njle 14f6 \ncltq\nmov (%r12,%rax,4),%eax\ncmp %eax,%edx\ncmovge %edx,%eax\nmov %eax,(%rsp)\nmovslq %r15d,%rdi\nshl $0x2,%rdi\ncallq 10d0 \nmov $0x28,%edi\nmov %rax,%r13\ncallq 10d0 \nmov %rax,%rbp\nmov (%rsp),%eax\ntest %eax,%eax\njle 168b \nlea -0x1(%r15),%eax\nmov $0x1,%ebx\npxor %xmm1,%xmm1\nmov %eax,0x4(%rsp)\nlea 0x4(%r12,%rax,4),%r14\nlea 0x4(,%rax,4),%rax\nmov %rax,0x8(%rsp)\nmovq $0x0,0x20(%rbp)\nmov %r12,%rcx\nmovups %xmm1,0x0(%rbp)\nmovups %xmm1,0x10(%rbp)\ntest %r15d,%r15d\njle 16a9 \nnopl 0x0(%rax)\nmov (%rcx),%eax\nadd $0x4,%rcx\ncltd\nidiv %ebx\nmovslq %eax,%rdx\nmov %eax,%esi\nimul $0x66666667,%rdx,%rdx\nsar $0x1f,%esi\nsar $0x22,%rdx\nsub %esi,%edx\nlea (%rdx,%rdx,4),%edx\nadd %edx,%edx\nsub %edx,%eax\ncltq\naddl $0x1,0x0(%rbp,%rax,4)\ncmp %r14,%rcx\njne 1560 \nmov 0x8(%rbp),%esi\nmov 0x0(%rbp),%eax\nmov 0xc(%rbp),%edx\nadd 0x4(%rbp),%eax\nmov 0x10(%rbp),%edi\nadd %eax,%esi\nmov 0x14(%rbp),%r8d\nadd %esi,%edx\nmov 0x18(%rbp),%r9d\nmov 0x1c(%rbp),%ecx\nadd %edx,%edi\nmov 0x20(%rbp),%r10d\nmov 0x24(%rbp),%r11d\nadd %edi,%r8d\nadd %r8d,%r9d\nadd %r9d,%ecx\nadd %ecx,%r10d\nadd %r10d,%r11d\nmovd %edx,%xmm2\nmovd %edi,%xmm3\nmovd %eax,%xmm0\nmov %r11d,0x24(%rbp)\nmovd %esi,%xmm4\npunpckldq %xmm3,%xmm2\nmovd %r10d,%xmm5\npunpckldq %xmm4,%xmm0\nmovd %r9d,%xmm6\npunpcklqdq %xmm2,%xmm0\nmovd %ecx,%xmm2\nmovslq 0x4(%rsp),%rcx\nmovups %xmm0,0x4(%rbp)\nmovd %r8d,%xmm0\npunpckldq %xmm5,%xmm2\npunpckldq %xmm6,%xmm0\npunpcklqdq %xmm2,%xmm0\nmovups %xmm0,0x14(%rbp)\ntest %ecx,%ecx\njs 1664 \nnopl 0x0(%rax,%rax,1)\nmov (%r12,%rcx,4),%esi\nsub $0x1,%rcx\nmov %esi,%eax\ncltd\nidiv %ebx\nmovslq %eax,%rdx\nmov %eax,%edi\nimul $0x66666667,%rdx,%rdx\nsar $0x1f,%edi\nsar $0x22,%rdx\nsub %edi,%edx\nlea (%rdx,%rdx,4),%edx\nadd %edx,%edx\nsub %edx,%eax\ncltq\nlea 0x0(%rbp,%rax,4),%rdx\nmovslq (%rdx),%rdi\nmov %rdi,%rax\nmov %esi,-0x4(%r13,%rdi,4)\nsub $0x1,%eax\nmov %eax,(%rdx)\ntest %ecx,%ecx\njns 1620 \ntest %r15d,%r15d\njle 167d \nmov 0x8(%rsp),%rdx\nmov %r13,%rsi\nmov %r12,%rdi\ncallq 10c0 \npxor %xmm1,%xmm1\nlea (%rbx,%rbx,4),%ebx\nadd %ebx,%ebx\ncmp (%rsp),%ebx\njle 1540 \nmov %r13,%rdi\ncallq 1090 \nadd $0x18,%rsp\nmov %rbp,%rdi\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\njmpq 1090 \nxor %r11d,%r11d\nxor %r10d,%r10d\nxor %ecx,%ecx\nxor %r9d,%r9d\nxor %r8d,%r8d\nxor %edi,%edi\nxor %edx,%edx\nxor %esi,%esi\nxor %eax,%eax\njmpq 15c8 \nmov $0x1,%eax\njmpq 14b5 \nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov r9d, esi\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 18h\nmov r15d, [rdi]\ncmp esi, 1\njle loc_1470\nlea eax, [rsi-2]\nlea ecx, [rsi-1]\ncmp eax, 2\njbe loc_161D\nmov edx, ecx\nmovd xmm3, r15d\nmov rax, rdi\nshr edx, 2\npshufd xmm2, xmm3, 0\nshl rdx, 4\nadd rdx, rdi\nnop dword ptr [rax+00h]\nloc_13C0:\nmovdqu xmm0, xmmword ptr [rax+4]\nadd rax, 10h\nmovdqa xmm1, xmm0\npcmpgtd xmm1, xmm2\npand xmm0, xmm1\npandn xmm1, xmm2\nmovdqa xmm2, xmm1\npor xmm2, xmm0\ncmp rdx, rax\njnz short loc_13C0\nmovdqa xmm1, xmm2\nmov eax, ecx\npsrldq xmm1, 8\nand eax, 0FFFFFFFCh\nmovdqa xmm0, xmm1\nadd eax, 1\nand ecx, 3\npcmpgtd xmm0, xmm2\npand xmm1, xmm0\npandn xmm0, xmm2\npor xmm0, xmm1\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\nmovdqa xmm1, xmm2\npcmpgtd xmm1, xmm0\npand xmm2, xmm1\npandn xmm1, xmm0\npor xmm1, xmm2\nmovd r15d, xmm1\njz short loc_1470\nloc_1432:\nmovsxd rdx, eax\nlea rcx, ds:0[rdx*4]\nmov edx, [r12+rdx*4]\ncmp r15d, edx\ncmovl r15d, edx\nlea edx, [rax+1]\ncmp r9d, edx\njle short loc_1470\nmov edx, [r12+rcx+4]\ncmp r15d, edx\ncmovl r15d, edx\nadd eax, 2\ncmp r9d, eax\njle short loc_1470\nmov eax, [r12+rcx+8]\ncmp r15d, eax\ncmovl r15d, eax\nloc_1470:\nmovsxd r14, r9d\nmov [rsp+48h+var_48], r9d\nshl r14, 2\nmov rdi, r14; size\ncall _malloc\nmov edi, 28h ; '('; size\nmov r13, rax\ncall _malloc\nmov rbx, rax\ntest r15d, r15d\njle loc_15D6\nmov r9d, [rsp+48h+var_48]\nadd r14, r12\nmov ebp, 1\npxor xmm0, xmm0\nlea eax, [r9-1]\nmov [rsp+48h+var_44], eax\nlea rax, ds:4[rax*4]\nmov [rsp+48h+n], rax\nnop dword ptr [rax+00000000h]\nloc_14C8:\nmov eax, [rsp+48h+var_48]\nmov qword ptr [rbx+20h], 0\nmov rsi, r12\nmovups xmmword ptr [rbx], xmm0\nmovups xmmword ptr [rbx+10h], xmm0\ntest eax, eax\njle loc_15F4\nnop dword ptr [rax]\nloc_14E8:\nmov eax, [rsi]\nadd rsi, 4\ncdq\nidiv ebp\nmovsxd rdx, eax\nmov ecx, eax\nimul rdx, 66666667h\nsar ecx, 1Fh\nsar rdx, 22h\nsub edx, ecx\nlea edx, [rdx+rdx*4]\nadd edx, edx\nsub eax, edx\ncdqe\nadd dword ptr [rbx+rax*4], 1\ncmp rsi, r14\njnz short loc_14E8\nmov r11d, [rbx+8]\nmov r10d, [rbx+0Ch]\nmov eax, [rbx]\nadd eax, [rbx+4]\nmov r9d, [rbx+10h]\nadd r11d, eax\nmov r8d, [rbx+14h]\nmov [rbx+4], eax\nadd r10d, r11d\nmov edi, [rbx+18h]\nmov esi, [rbx+1Ch]\nmov [rbx+8], r11d\nadd r9d, r10d\nmov edx, [rbx+20h]\nmov [rbx+0Ch], r10d\nadd r8d, r9d\nmov [rbx+10h], r9d\nadd edi, r8d\nmov [rbx+14h], r8d\nadd esi, edi\nmov [rbx+18h], edi\nadd edx, esi\nadd [rbx+24h], edx\nmov [rbx+20h], edx\nmov [rbx+1Ch], esi\nmovsxd rsi, [rsp+48h+var_44]\nnop dword ptr [rax]\nloc_1570:\nmov ecx, [r12+rsi*4]\nsub rsi, 1\nmov eax, ecx\ncdq\nidiv ebp\nmovsxd rdx, eax\nmov edi, eax\nimul rdx, 66666667h\nsar edi, 1Fh\nsar rdx, 22h\nsub edx, edi\nlea edx, [rdx+rdx*4]\nadd edx, edx\nsub eax, edx\ncdqe\nlea rdx, [rbx+rax*4]\nmovsxd rdi, dword ptr [rdx]\nmov rax, rdi\nmov [r13+rdi*4-4], ecx\nsub eax, 1\nmov [rdx], eax\ntest esi, esi\njns short loc_1570\nmov rdx, [rsp+48h+n]; n\nmov rsi, r13; src\nmov rdi, r12; dest\ncall _memcpy\npxor xmm0, xmm0\nloc_15C7:\nlea ebp, [rbp+rbp*4+0]\nadd ebp, ebp\ncmp ebp, r15d\njle loc_14C8\nloc_15D6:\nmov rdi, r13; ptr\ncall _free\nadd rsp, 18h\nmov rdi, rbx; ptr\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\njmp _free\nloc_15F4:\nmov dword ptr [rbx+4], 0\nmov qword ptr [rbx+8], 0\nmov qword ptr [rbx+10h], 0\nmov qword ptr [rbx+18h], 0\nmov qword ptr [rbx+20h], 0\njmp short loc_15C7\nloc_161D:\nmov eax, 1\njmp loc_1432", + "ida_pseudo": "void __fastcall func0(signed int *dest, int a2)\n{\n signed int v3; // r15d\n unsigned int v4; // ecx\n signed int *v5; // rax\n __m128i v6; // xmm2\n __m128i v7; // xmm0\n __m128i v8; // xmm1\n __m128i v9; // xmm1\n signed int v10; // eax\n __m128i v11; // xmm0\n __m128i v12; // xmm0\n __m128i v13; // xmm2\n __m128i v14; // xmm1\n __int64 v15; // rcx\n _DWORD *v16; // r13\n _QWORD *v17; // rbx\n signed int *v18; // r14\n int v19; // ebp\n __int128 v20; // xmm0\n signed int *v21; // rsi\n int v22; // eax\n int v23; // r10d\n int v24; // eax\n int v25; // r9d\n int v26; // r11d\n int v27; // r8d\n int v28; // r10d\n int v29; // edi\n int v30; // esi\n int v31; // r9d\n int v32; // edx\n int v33; // r8d\n int v34; // edi\n int v35; // esi\n int v36; // edx\n __int64 v37; // rsi\n signed int v38; // ecx\n int *v39; // rdx\n int v40; // eax\n\n v3 = *dest;\n if ( a2 > 1 )\n {\n v4 = a2 - 1;\n if ( (unsigned int)(a2 - 2) <= 2 )\n {\n v10 = 1;\n }\n else\n {\n v5 = dest;\n v6 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v3), 0);\n do\n {\n v7 = _mm_loadu_si128((const __m128i *)(v5 + 1));\n v5 += 4;\n v8 = _mm_cmpgt_epi32(v7, v6);\n v6 = _mm_or_si128(_mm_andnot_si128(v8, v6), _mm_and_si128(v7, v8));\n }\n while ( &dest[4 * (v4 >> 2)] != v5 );\n v9 = _mm_srli_si128(v6, 8);\n v10 = (v4 & 0xFFFFFFFC) + 1;\n v11 = _mm_cmpgt_epi32(v9, v6);\n v12 = _mm_or_si128(_mm_andnot_si128(v11, v6), _mm_and_si128(v9, v11));\n v13 = _mm_srli_si128(v12, 4);\n v14 = _mm_cmpgt_epi32(v13, v12);\n v3 = _mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v14, v12), _mm_and_si128(v13, v14)));\n if ( (v4 & 3) == 0 )\n goto LABEL_14;\n }\n v15 = v10;\n if ( v3 < dest[v15] )\n v3 = dest[v10];\n if ( a2 > v10 + 1 )\n {\n if ( v3 < dest[v15 + 1] )\n v3 = dest[v15 + 1];\n if ( a2 > v10 + 2 && v3 < dest[v15 + 2] )\n v3 = dest[v15 + 2];\n }\n }\nLABEL_14:\n v16 = malloc(4LL * a2);\n v17 = malloc(0x28uLL);\n if ( v3 > 0 )\n {\n v18 = &dest[a2];\n v19 = 1;\n v20 = 0LL;\n do\n {\n v17[4] = 0LL;\n v21 = dest;\n *(_OWORD *)v17 = v20;\n *((_OWORD *)v17 + 1) = v20;\n if ( a2 <= 0 )\n {\n *((_DWORD *)v17 + 1) = 0;\n v17[1] = 0LL;\n v17[2] = 0LL;\n v17[3] = 0LL;\n v17[4] = 0LL;\n }\n else\n {\n do\n {\n v22 = *v21++;\n ++*((_DWORD *)v17 + v22 / v19 % 10);\n }\n while ( v21 != v18 );\n v23 = *((_DWORD *)v17 + 3);\n v24 = *((_DWORD *)v17 + 1) + *(_DWORD *)v17;\n v25 = *((_DWORD *)v17 + 4);\n v26 = v24 + *((_DWORD *)v17 + 2);\n v27 = *((_DWORD *)v17 + 5);\n *((_DWORD *)v17 + 1) = v24;\n v28 = v26 + v23;\n v29 = *((_DWORD *)v17 + 6);\n v30 = *((_DWORD *)v17 + 7);\n *((_DWORD *)v17 + 2) = v26;\n v31 = v28 + v25;\n v32 = *((_DWORD *)v17 + 8);\n *((_DWORD *)v17 + 3) = v28;\n v33 = v31 + v27;\n *((_DWORD *)v17 + 4) = v31;\n v34 = v33 + v29;\n *((_DWORD *)v17 + 5) = v33;\n v35 = v34 + v30;\n *((_DWORD *)v17 + 6) = v34;\n v36 = v35 + v32;\n *((_DWORD *)v17 + 9) += v36;\n *((_DWORD *)v17 + 8) = v36;\n *((_DWORD *)v17 + 7) = v35;\n v37 = a2 - 1;\n do\n {\n v38 = dest[v37--];\n v39 = (int *)v17 + v38 / v19 % 10;\n v40 = *v39;\n v16[*v39 - 1] = v38;\n *v39 = v40 - 1;\n }\n while ( (int)v37 >= 0 );\n memcpy(dest, v16, 4LL * (unsigned int)(a2 - 1) + 4);\n v20 = 0LL;\n }\n v19 *= 10;\n }\n while ( v19 <= v3 );\n }\n free(v16);\n free(v17);\n}", + "ida_strip_asm": "sub_1370:\nendbr64\npush r15\nmov r9d, esi\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 18h\nmov r15d, [rdi]\ncmp esi, 1\njle loc_1470\nlea eax, [rsi-2]\nlea ecx, [rsi-1]\ncmp eax, 2\njbe loc_161D\nmov edx, ecx\nmovd xmm3, r15d\nmov rax, rdi\nshr edx, 2\npshufd xmm2, xmm3, 0\nshl rdx, 4\nadd rdx, rdi\nnop dword ptr [rax+00h]\nloc_13C0:\nmovdqu xmm0, xmmword ptr [rax+4]\nadd rax, 10h\nmovdqa xmm1, xmm0\npcmpgtd xmm1, xmm2\npand xmm0, xmm1\npandn xmm1, xmm2\nmovdqa xmm2, xmm1\npor xmm2, xmm0\ncmp rdx, rax\njnz short loc_13C0\nmovdqa xmm1, xmm2\nmov eax, ecx\npsrldq xmm1, 8\nand eax, 0FFFFFFFCh\nmovdqa xmm0, xmm1\nadd eax, 1\nand ecx, 3\npcmpgtd xmm0, xmm2\npand xmm1, xmm0\npandn xmm0, xmm2\npor xmm0, xmm1\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\nmovdqa xmm1, xmm2\npcmpgtd xmm1, xmm0\npand xmm2, xmm1\npandn xmm1, xmm0\npor xmm1, xmm2\nmovd r15d, xmm1\njz short loc_1470\nloc_1432:\nmovsxd rdx, eax\nlea rcx, ds:0[rdx*4]\nmov edx, [r12+rdx*4]\ncmp r15d, edx\ncmovl r15d, edx\nlea edx, [rax+1]\ncmp r9d, edx\njle short loc_1470\nmov edx, [r12+rcx+4]\ncmp r15d, edx\ncmovl r15d, edx\nadd eax, 2\ncmp r9d, eax\njle short loc_1470\nmov eax, [r12+rcx+8]\ncmp r15d, eax\ncmovl r15d, eax\nloc_1470:\nmovsxd r14, r9d\nmov [rsp+48h+var_48], r9d\nshl r14, 2\nmov rdi, r14; size\ncall _malloc\nmov edi, 28h ; '('; size\nmov r13, rax\ncall _malloc\nmov rbx, rax\ntest r15d, r15d\njle loc_15D6\nmov r9d, [rsp+48h+var_48]\nadd r14, r12\nmov ebp, 1\npxor xmm0, xmm0\nlea eax, [r9-1]\nmov [rsp+48h+var_44], eax\nlea rax, ds:4[rax*4]\nmov [rsp+48h+n], rax\nnop dword ptr [rax+00000000h]\nloc_14C8:\nmov eax, [rsp+48h+var_48]\nmov qword ptr [rbx+20h], 0\nmov rsi, r12\nmovups xmmword ptr [rbx], xmm0\nmovups xmmword ptr [rbx+10h], xmm0\ntest eax, eax\njle loc_15F4\nnop dword ptr [rax]\nloc_14E8:\nmov eax, [rsi]\nadd rsi, 4\ncdq\nidiv ebp\nmovsxd rdx, eax\nmov ecx, eax\nimul rdx, 66666667h\nsar ecx, 1Fh\nsar rdx, 22h\nsub edx, ecx\nlea edx, [rdx+rdx*4]\nadd edx, edx\nsub eax, edx\ncdqe\nadd dword ptr [rbx+rax*4], 1\ncmp rsi, r14\njnz short loc_14E8\nmov r11d, [rbx+8]\nmov r10d, [rbx+0Ch]\nmov eax, [rbx]\nadd eax, [rbx+4]\nmov r9d, [rbx+10h]\nadd r11d, eax\nmov r8d, [rbx+14h]\nmov [rbx+4], eax\nadd r10d, r11d\nmov edi, [rbx+18h]\nmov esi, [rbx+1Ch]\nmov [rbx+8], r11d\nadd r9d, r10d\nmov edx, [rbx+20h]\nmov [rbx+0Ch], r10d\nadd r8d, r9d\nmov [rbx+10h], r9d\nadd edi, r8d\nmov [rbx+14h], r8d\nadd esi, edi\nmov [rbx+18h], edi\nadd edx, esi\nadd [rbx+24h], edx\nmov [rbx+20h], edx\nmov [rbx+1Ch], esi\nmovsxd rsi, [rsp+48h+var_44]\nnop dword ptr [rax]\nloc_1570:\nmov ecx, [r12+rsi*4]\nsub rsi, 1\nmov eax, ecx\ncdq\nidiv ebp\nmovsxd rdx, eax\nmov edi, eax\nimul rdx, 66666667h\nsar edi, 1Fh\nsar rdx, 22h\nsub edx, edi\nlea edx, [rdx+rdx*4]\nadd edx, edx\nsub eax, edx\ncdqe\nlea rdx, [rbx+rax*4]\nmovsxd rdi, dword ptr [rdx]\nmov rax, rdi\nmov [r13+rdi*4-4], ecx\nsub eax, 1\nmov [rdx], eax\ntest esi, esi\njns short loc_1570\nmov rdx, [rsp+48h+n]; n\nmov rsi, r13; src\nmov rdi, r12; dest\ncall _memcpy\npxor xmm0, xmm0\nloc_15C7:\nlea ebp, [rbp+rbp*4+0]\nadd ebp, ebp\ncmp ebp, r15d\njle loc_14C8\nloc_15D6:\nmov rdi, r13; ptr\ncall _free\nadd rsp, 18h\nmov rdi, rbx; ptr\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\njmp _free\nloc_15F4:\nmov dword ptr [rbx+4], 0\nmov qword ptr [rbx+8], 0\nmov qword ptr [rbx+10h], 0\nmov qword ptr [rbx+18h], 0\nmov qword ptr [rbx+20h], 0\njmp short loc_15C7\nloc_161D:\nmov eax, 1\njmp loc_1432", + "ida_strip_pseudo": "void __fastcall sub_1370(signed int *dest, int a2)\n{\n signed int v3; // r15d\n unsigned int v4; // ecx\n signed int *v5; // rax\n __m128i v6; // xmm2\n __m128i v7; // xmm0\n __m128i v8; // xmm1\n __m128i v9; // xmm1\n signed int v10; // eax\n __m128i v11; // xmm0\n __m128i v12; // xmm0\n __m128i v13; // xmm2\n __m128i v14; // xmm1\n __int64 v15; // rcx\n _DWORD *v16; // r13\n _QWORD *v17; // rbx\n signed int *v18; // r14\n int v19; // ebp\n __int128 v20; // xmm0\n signed int *v21; // rsi\n int v22; // eax\n int v23; // r10d\n int v24; // eax\n int v25; // r9d\n int v26; // r11d\n int v27; // r8d\n int v28; // r10d\n int v29; // edi\n int v30; // esi\n int v31; // r9d\n int v32; // edx\n int v33; // r8d\n int v34; // edi\n int v35; // esi\n int v36; // edx\n __int64 v37; // rsi\n signed int v38; // ecx\n int *v39; // rdx\n int v40; // eax\n\n v3 = *dest;\n if ( a2 > 1 )\n {\n v4 = a2 - 1;\n if ( (unsigned int)(a2 - 2) <= 2 )\n {\n v10 = 1;\n }\n else\n {\n v5 = dest;\n v6 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v3), 0);\n do\n {\n v7 = _mm_loadu_si128((const __m128i *)(v5 + 1));\n v5 += 4;\n v8 = _mm_cmpgt_epi32(v7, v6);\n v6 = _mm_or_si128(_mm_andnot_si128(v8, v6), _mm_and_si128(v7, v8));\n }\n while ( &dest[4 * (v4 >> 2)] != v5 );\n v9 = _mm_srli_si128(v6, 8);\n v10 = (v4 & 0xFFFFFFFC) + 1;\n v11 = _mm_cmpgt_epi32(v9, v6);\n v12 = _mm_or_si128(_mm_andnot_si128(v11, v6), _mm_and_si128(v9, v11));\n v13 = _mm_srli_si128(v12, 4);\n v14 = _mm_cmpgt_epi32(v13, v12);\n v3 = _mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v14, v12), _mm_and_si128(v13, v14)));\n if ( (v4 & 3) == 0 )\n goto LABEL_14;\n }\n v15 = v10;\n if ( v3 < dest[v15] )\n v3 = dest[v10];\n if ( a2 > v10 + 1 )\n {\n if ( v3 < dest[v15 + 1] )\n v3 = dest[v15 + 1];\n if ( a2 > v10 + 2 && v3 < dest[v15 + 2] )\n v3 = dest[v15 + 2];\n }\n }\nLABEL_14:\n v16 = malloc(4LL * a2);\n v17 = malloc(0x28uLL);\n if ( v3 > 0 )\n {\n v18 = &dest[a2];\n v19 = 1;\n v20 = 0LL;\n do\n {\n v17[4] = 0LL;\n v21 = dest;\n *(_OWORD *)v17 = v20;\n *((_OWORD *)v17 + 1) = v20;\n if ( a2 <= 0 )\n {\n *((_DWORD *)v17 + 1) = 0;\n v17[1] = 0LL;\n v17[2] = 0LL;\n v17[3] = 0LL;\n v17[4] = 0LL;\n }\n else\n {\n do\n {\n v22 = *v21++;\n ++*((_DWORD *)v17 + v22 / v19 % 10);\n }\n while ( v21 != v18 );\n v23 = *((_DWORD *)v17 + 3);\n v24 = *((_DWORD *)v17 + 1) + *(_DWORD *)v17;\n v25 = *((_DWORD *)v17 + 4);\n v26 = v24 + *((_DWORD *)v17 + 2);\n v27 = *((_DWORD *)v17 + 5);\n *((_DWORD *)v17 + 1) = v24;\n v28 = v26 + v23;\n v29 = *((_DWORD *)v17 + 6);\n v30 = *((_DWORD *)v17 + 7);\n *((_DWORD *)v17 + 2) = v26;\n v31 = v28 + v25;\n v32 = *((_DWORD *)v17 + 8);\n *((_DWORD *)v17 + 3) = v28;\n v33 = v31 + v27;\n *((_DWORD *)v17 + 4) = v31;\n v34 = v33 + v29;\n *((_DWORD *)v17 + 5) = v33;\n v35 = v34 + v30;\n *((_DWORD *)v17 + 6) = v34;\n v36 = v35 + v32;\n *((_DWORD *)v17 + 9) += v36;\n *((_DWORD *)v17 + 8) = v36;\n *((_DWORD *)v17 + 7) = v35;\n v37 = a2 - 1;\n do\n {\n v38 = dest[v37--];\n v39 = (int *)v17 + v38 / v19 % 10;\n v40 = *v39;\n v16[*v39 - 1] = v38;\n *v39 = v40 - 1;\n }\n while ( (int)v37 >= 0 );\n memcpy(dest, v16, 4LL * (unsigned int)(a2 - 1) + 4);\n v20 = 0LL;\n }\n v19 *= 10;\n }\n while ( v19 <= v3 );\n }\n free(v16);\n free(v17);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1370(signed int *dest, int a2) {\n signed int v3;\n unsigned int v4;\n signed int *v5;\n __m128i v6;\n __m128i v7;\n __m128i v8;\n __m128i v9;\n signed int v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n long long v15;\n uint32_t *v16;\n uint64_t *v17;\n signed int *v18;\n int v19;\n __int128 v20;\n signed int *v21;\n int v22;\n int v23;\n int v24;\n int v25;\n int v26;\n int v27;\n int v28;\n int v29;\n int v30;\n int v31;\n int v32;\n int v33;\n int v34;\n int v35;\n int v36;\n long long v37;\n signed int v38;\n int *v39;\n int v40;\n v3 = *dest;\n if (a2 > 1) {\n v4 = a2 - 1;\n if ((unsigned int)(a2 - 2) <= 2) {\n v10 = 1;\n } else {\n v5 = dest;\n v6 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v3), 0);\n do {\n v7 = _mm_loadu_si128((const __m128i *)(v5 + 1));\n v5 += 4;\n v8 = _mm_cmpgt_epi32(v7, v6);\n v6 = _mm_or_si128(_mm_andnot_si128(v8, v6), _mm_and_si128(v7, v8));\n } while (&dest[4 * (v4 >> 2)] != v5);\n v9 = _mm_srli_si128(v6, 8);\n v10 = (v4 & 4294967292) + 1;\n v11 = _mm_cmpgt_epi32(v9, v6);\n v12 = _mm_or_si128(_mm_andnot_si128(v11, v6), _mm_and_si128(v9, v11));\n v13 = _mm_srli_si128(v12, 4);\n v14 = _mm_cmpgt_epi32(v13, v12);\n v3 = _mm_cvtsi128_si32(\n _mm_or_si128(_mm_andnot_si128(v14, v12), _mm_and_si128(v13, v14)));\n if ((v4 & 3) == 0) goto LABEL_14;\n }\n v15 = v10;\n if (v3 < dest[v15]) v3 = dest[v10];\n if (a2 > v10 + 1) {\n if (v3 < dest[v15 + 1]) v3 = dest[v15 + 1];\n if (a2 > v10 + 2 && v3 < dest[v15 + 2]) v3 = dest[v15 + 2];\n }\n }\nLABEL_14:\n v16 = malloc(4LL * a2);\n v17 = malloc(40uLL);\n if (v3 > 0) {\n v18 = &dest[a2];\n v19 = 1;\n v20 = 0LL;\n do {\n v17[4] = 0LL;\n v21 = dest;\n *(long double *)v17 = v20;\n *((long double *)v17 + 1) = v20;\n if (a2 <= 0) {\n *((uint32_t *)v17 + 1) = 0;\n v17[1] = 0LL;\n v17[2] = 0LL;\n v17[3] = 0LL;\n v17[4] = 0LL;\n } else {\n do {\n v22 = *v21++;\n ++*((uint32_t *)v17 + v22 / v19 % 10);\n } while (v21 != v18);\n v23 = *((uint32_t *)v17 + 3);\n v24 = *((uint32_t *)v17 + 1) + *(uint32_t *)v17;\n v25 = *((uint32_t *)v17 + 4);\n v26 = v24 + *((uint32_t *)v17 + 2);\n v27 = *((uint32_t *)v17 + 5);\n *((uint32_t *)v17 + 1) = v24;\n v28 = v26 + v23;\n v29 = *((uint32_t *)v17 + 6);\n v30 = *((uint32_t *)v17 + 7);\n *((uint32_t *)v17 + 2) = v26;\n v31 = v28 + v25;\n v32 = *((uint32_t *)v17 + 8);\n *((uint32_t *)v17 + 3) = v28;\n v33 = v31 + v27;\n *((uint32_t *)v17 + 4) = v31;\n v34 = v33 + v29;\n *((uint32_t *)v17 + 5) = v33;\n v35 = v34 + v30;\n *((uint32_t *)v17 + 6) = v34;\n v36 = v35 + v32;\n *((uint32_t *)v17 + 9) += v36;\n *((uint32_t *)v17 + 8) = v36;\n *((uint32_t *)v17 + 7) = v35;\n v37 = a2 - 1;\n do {\n v38 = dest[v37--];\n v39 = (int *)v17 + v38 / v19 % 10;\n v40 = *v39;\n v16[*v39 - 1] = v38;\n *v39 = v40 - 1;\n } while ((int)v37 >= 0);\n memcpy(dest, v16, 4LL * (unsigned int)(a2 - 1) + 4);\n v20 = 0LL;\n }\n v19 *= 10;\n } while (v19 <= v3);\n }\n free(v16);\n free(v17);\n}", + "ida_pseudo_norm": "void func0(signed int *dest, int a2) {\n signed int v3;\n unsigned int v4;\n signed int *v5;\n __m128i v6;\n __m128i v7;\n __m128i v8;\n __m128i v9;\n signed int v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n long long v15;\n uint32_t *v16;\n uint64_t *v17;\n signed int *v18;\n int v19;\n __int128 v20;\n signed int *v21;\n int v22;\n int v23;\n int v24;\n int v25;\n int v26;\n int v27;\n int v28;\n int v29;\n int v30;\n int v31;\n int v32;\n int v33;\n int v34;\n int v35;\n int v36;\n long long v37;\n signed int v38;\n int *v39;\n int v40;\n v3 = *dest;\n if (a2 > 1) {\n v4 = a2 - 1;\n if ((unsigned int)(a2 - 2) <= 2) {\n v10 = 1;\n } else {\n v5 = dest;\n v6 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v3), 0);\n do {\n v7 = _mm_loadu_si128((const __m128i *)(v5 + 1));\n v5 += 4;\n v8 = _mm_cmpgt_epi32(v7, v6);\n v6 = _mm_or_si128(_mm_andnot_si128(v8, v6), _mm_and_si128(v7, v8));\n } while (&dest[4 * (v4 >> 2)] != v5);\n v9 = _mm_srli_si128(v6, 8);\n v10 = (v4 & 4294967292) + 1;\n v11 = _mm_cmpgt_epi32(v9, v6);\n v12 = _mm_or_si128(_mm_andnot_si128(v11, v6), _mm_and_si128(v9, v11));\n v13 = _mm_srli_si128(v12, 4);\n v14 = _mm_cmpgt_epi32(v13, v12);\n v3 = _mm_cvtsi128_si32(\n _mm_or_si128(_mm_andnot_si128(v14, v12), _mm_and_si128(v13, v14)));\n if ((v4 & 3) == 0) goto LABEL_14;\n }\n v15 = v10;\n if (v3 < dest[v15]) v3 = dest[v10];\n if (a2 > v10 + 1) {\n if (v3 < dest[v15 + 1]) v3 = dest[v15 + 1];\n if (a2 > v10 + 2 && v3 < dest[v15 + 2]) v3 = dest[v15 + 2];\n }\n }\nLABEL_14:\n v16 = malloc(4LL * a2);\n v17 = malloc(40uLL);\n if (v3 > 0) {\n v18 = &dest[a2];\n v19 = 1;\n v20 = 0LL;\n do {\n v17[4] = 0LL;\n v21 = dest;\n *(long double *)v17 = v20;\n *((long double *)v17 + 1) = v20;\n if (a2 <= 0) {\n *((uint32_t *)v17 + 1) = 0;\n v17[1] = 0LL;\n v17[2] = 0LL;\n v17[3] = 0LL;\n v17[4] = 0LL;\n } else {\n do {\n v22 = *v21++;\n ++*((uint32_t *)v17 + v22 / v19 % 10);\n } while (v21 != v18);\n v23 = *((uint32_t *)v17 + 3);\n v24 = *((uint32_t *)v17 + 1) + *(uint32_t *)v17;\n v25 = *((uint32_t *)v17 + 4);\n v26 = v24 + *((uint32_t *)v17 + 2);\n v27 = *((uint32_t *)v17 + 5);\n *((uint32_t *)v17 + 1) = v24;\n v28 = v26 + v23;\n v29 = *((uint32_t *)v17 + 6);\n v30 = *((uint32_t *)v17 + 7);\n *((uint32_t *)v17 + 2) = v26;\n v31 = v28 + v25;\n v32 = *((uint32_t *)v17 + 8);\n *((uint32_t *)v17 + 3) = v28;\n v33 = v31 + v27;\n *((uint32_t *)v17 + 4) = v31;\n v34 = v33 + v29;\n *((uint32_t *)v17 + 5) = v33;\n v35 = v34 + v30;\n *((uint32_t *)v17 + 6) = v34;\n v36 = v35 + v32;\n *((uint32_t *)v17 + 9) += v36;\n *((uint32_t *)v17 + 8) = v36;\n *((uint32_t *)v17 + 7) = v35;\n v37 = a2 - 1;\n do {\n v38 = dest[v37--];\n v39 = (int *)v17 + v38 / v19 % 10;\n v40 = *v39;\n v16[*v39 - 1] = v38;\n *v39 = v40 - 1;\n } while ((int)v37 >= 0);\n memcpy(dest, v16, 4LL * (unsigned int)(a2 - 1) + 4);\n v20 = 0LL;\n }\n v19 *= 10;\n } while (v19 <= v3);\n }\n free(v16);\n free(v17);\n}" + }, + { + "index": 517, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int list1[], int size) {\n int max = list1[0];\n for (int i = 0; i < size; i++) {\n if (list1[i] > max) {\n max = list1[i];\n }\n }\n return max;\n}", + "test": "int main() {\n\n int array1[] = {1,2,3,4,-1};\n\n int array2[] = {0,1,2,-5,-1,6};\n\n int array3[] = {0,0,1,0};\n\n \n\n assert(func0(array1, 5) == 4);\n\n assert(func0(array2, 6) == 6);\n\n assert(func0(array3, 4) == 1);\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov -0x18(%rbp),%rax\nmov (%rax),%eax\nmov %eax,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11e2 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x8(%rbp)\njge 11de \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11aa \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov rax, [rbp+var_18]\nmov eax, [rax]\nmov [rbp+var_8], eax\nmov [rbp+var_4], 0\njmp short loc_11E2\nloc_11AA:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_8], eax\njge short loc_11DE\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_8], eax\nloc_11DE:\nadd [rbp+var_4], 1\nloc_11E2:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11AA\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = *a1;\n for ( i = 0; i < a2; ++i )\n {\n if ( (int)v3 < (int)a1[i] )\n v3 = a1[i];\n }\n return v3;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov rax, [rbp+var_18]\nmov eax, [rax]\nmov [rbp+var_8], eax\nmov [rbp+var_4], 0\njmp short loc_11E2\nloc_11AA:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_8], eax\njge short loc_11DE\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_8], eax\nloc_11DE:\nadd [rbp+var_4], 1\nloc_11E2:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11AA\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(unsigned int *a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = *a1;\n for ( i = 0; i < a2; ++i )\n {\n if ( (int)v3 < (int)a1[i] )\n v3 = a1[i];\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(unsigned int *a1, int a2) {\n unsigned int v3;\n int i;\n v3 = *a1;\n for (i = 0; i < a2; ++i) {\n if ((int)v3 < (int)a1[i]) v3 = a1[i];\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n unsigned int v3;\n int i;\n v3 = *a1;\n for (i = 0; i < a2; ++i) {\n if ((int)v3 < (int)a1[i]) v3 = a1[i];\n }\n return v3;\n}" + }, + { + "index": 517, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int list1[], int size) {\n int max = list1[0];\n for (int i = 0; i < size; i++) {\n if (list1[i] > max) {\n max = list1[i];\n }\n }\n return max;\n}", + "test": "int main() {\n\n int array1[] = {1,2,3,4,-1};\n\n int array2[] = {0,1,2,-5,-1,6};\n\n int array3[] = {0,0,1,0};\n\n \n\n assert(func0(array1, 5) == 4);\n\n assert(func0(array2, 6) == 6);\n\n assert(func0(array3, 4) == 1);\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov (%rdi),%edx\ntest %esi,%esi\njle 11ae \nmov %rdi,%rax\nlea -0x1(%rsi),%ecx\nlea 0x4(%rdi,%rcx,4),%rsi\nmov (%rax),%ecx\ncmp %ecx,%edx\ncmovl %ecx,%edx\nadd $0x4,%rax\ncmp %rsi,%rax\njne 119e \nmov %edx,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov edx, [rdi]\ntest esi, esi\njle short loc_11AD\nmov rax, rdi\nmovsxd rsi, esi\nlea rsi, [rdi+rsi*4]\nloc_119D:\nmov ecx, [rax]\ncmp edx, ecx\ncmovl edx, ecx\nadd rax, 4\ncmp rax, rsi\njnz short loc_119D\nloc_11AD:\nmov eax, edx\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n unsigned int v2; // edx\n unsigned int *v3; // rax\n unsigned int *v4; // rsi\n\n v2 = *a1;\n if ( a2 > 0 )\n {\n v3 = a1;\n v4 = &a1[a2];\n do\n {\n if ( (int)v2 < (int)*v3 )\n v2 = *v3;\n ++v3;\n }\n while ( v3 != v4 );\n }\n return v2;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\nmov edx, [rdi]\ntest esi, esi\njle short loc_11AD\nmov rax, rdi\nmovsxd rsi, esi\nlea rsi, [rdi+rsi*4]\nloc_119D:\nmov ecx, [rax]\ncmp edx, ecx\ncmovl edx, ecx\nadd rax, 4\ncmp rax, rsi\njnz short loc_119D\nloc_11AD:\nmov eax, edx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(unsigned int *a1, int a2)\n{\n unsigned int v2; // edx\n unsigned int *v3; // rax\n unsigned int *v4; // rsi\n\n v2 = *a1;\n if ( a2 > 0 )\n {\n v3 = a1;\n v4 = &a1[a2];\n do\n {\n if ( (int)v2 < (int)*v3 )\n v2 = *v3;\n ++v3;\n }\n while ( v3 != v4 );\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(unsigned int *a1, int a2) {\n unsigned int v2;\n unsigned int *v3;\n unsigned int *v4;\n v2 = *a1;\n if (a2 > 0) {\n v3 = a1;\n v4 = &a1[a2];\n do {\n if ((int)v2 < (int)*v3) v2 = *v3;\n ++v3;\n } while (v3 != v4);\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n unsigned int v2;\n unsigned int *v3;\n unsigned int *v4;\n v2 = *a1;\n if (a2 > 0) {\n v3 = a1;\n v4 = &a1[a2];\n do {\n if ((int)v2 < (int)*v3) v2 = *v3;\n ++v3;\n } while (v3 != v4);\n }\n return v2;\n}" + }, + { + "index": 518, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(double num) {\n double sqrt_root = pow(num, 0.5);\n return sqrt_root;\n}", + "test": "int main() {\n\n assert(func0(4) == 2);\n\n assert(func0(16) == 4);\n\n assert(func0(400) == 20);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmovsd %xmm0,-0x18(%rbp)\nmovsd 0xef6(%rip),%xmm0\nmov -0x18(%rbp),%rax\nmovapd %xmm0,%xmm1\nmovq %rax,%xmm0\ncallq 1060 \nmovq %xmm0,%rax\nmov %rax,-0x8(%rbp)\nmovsd -0x8(%rbp),%xmm0\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmovsd [rbp+x], xmm0\nmovsd xmm0, cs:y\nmov rax, [rbp+x]\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\nmovq rax, xmm0\nmov [rbp+var_8], rax\nmovsd xmm0, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(double a1)\n{\n return pow(a1, 0.5);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmovsd [rbp+x], xmm0\nmovsd xmm0, cs:y\nmov rax, [rbp+x]\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\nmovq rax, xmm0\nmov [rbp+var_8], rax\nmovsd xmm0, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(double a1)\n{\n return pow(a1, 0.5);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(double a1) { return pow(a1, 0.5); }", + "ida_pseudo_norm": "long long func0(double a1) { return pow(a1, 0.5); }" + }, + { + "index": 518, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(double num) {\n double sqrt_root = pow(num, 0.5);\n return sqrt_root;\n}", + "test": "int main() {\n\n assert(func0(4) == 2);\n\n assert(func0(16) == 4);\n\n assert(func0(400) == 20);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x8,%rsp\nmovsd 0xeff(%rip),%xmm1\ncallq 1060 \nadd $0x8,%rsp\nretq\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\nmovsd xmm1, cs:y; y\ncall _pow\nadd rsp, 8\nretn", + "ida_pseudo": "double __fastcall func0(double a1)\n{\n return pow(a1, 0.5);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nsub rsp, 8\nmovsd xmm1, cs:y; y\ncall _pow\nadd rsp, 8\nretn", + "ida_strip_pseudo": "double __fastcall sub_1169(double a1)\n{\n return pow(a1, 0.5);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1169(double a1) { return pow(a1, 0.5); }", + "ida_pseudo_norm": "double func0(double a1) { return pow(a1, 0.5); }" + }, + { + "index": 519, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int num) {\n double volume = (pow(num, 3) / (6 * sqrt(2)));\n return round(volume * 100) / 100;\n}", + "test": "int main() {\n\n assert(func0(10) == 117.85);\n\n assert(func0(15) == 397.75);\n\n assert(func0(20) == 942.81);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %edi,-0x14(%rbp)\ncvtsi2sdl -0x14(%rbp),%xmm0\nmovsd 0xee3(%rip),%xmm1\ncallq 1080 \nmovsd 0xede(%rip),%xmm1\ndivsd %xmm1,%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmovsd -0x8(%rbp),%xmm1\nmovsd 0xed0(%rip),%xmm0\nmulsd %xmm1,%xmm0\ncallq 1070 \nmovsd 0xebf(%rip),%xmm1\ndivsd %xmm1,%xmm0\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\npxor xmm2, xmm2\ncvtsi2sd xmm2, [rbp+var_14]\nmovq rax, xmm2\nmovsd xmm0, cs:y\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\nmovq rax, xmm0\nmovsd xmm1, cs:qword_2070\nmovq xmm0, rax\ndivsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm1, [rbp+var_8]\nmovsd xmm0, cs:qword_2078\nmulsd xmm1, xmm0\nmovq rax, xmm1\nmovq xmm0, rax; x\ncall _round\nmovq rax, xmm0\nmovsd xmm0, cs:qword_2078\nmovq xmm1, rax\ndivsd xmm1, xmm0\nmovapd xmm0, xmm1\nleave\nretn", + "ida_pseudo": "__int128 __usercall func0@(int a1@)\n{\n double v1; // rax\n __int128 v2; // xmm1\n double v4; // [rsp+18h] [rbp-8h]\n\n v4 = pow((double)a1, 3.0) / 8.485281374238571;\n v1 = round(v4 * 100.0);\n v2 = *(unsigned __int64 *)&v1;\n *(double *)&v2 = v1 / 100.0;\n return v2;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\npxor xmm2, xmm2\ncvtsi2sd xmm2, [rbp+var_14]\nmovq rax, xmm2\nmovsd xmm0, cs:y\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\nmovq rax, xmm0\nmovsd xmm1, cs:qword_2070\nmovq xmm0, rax\ndivsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm1, [rbp+var_8]\nmovsd xmm0, cs:qword_2078\nmulsd xmm1, xmm0\nmovq rax, xmm1\nmovq xmm0, rax; x\ncall _round\nmovq rax, xmm0\nmovsd xmm0, cs:qword_2078\nmovq xmm1, rax\ndivsd xmm1, xmm0\nmovapd xmm0, xmm1\nleave\nretn", + "ida_strip_pseudo": "__int128 __usercall sub_1189@(int a1@)\n{\n double v1; // rax\n __int128 v2; // xmm1\n double v4; // [rsp+18h] [rbp-8h]\n\n v4 = pow((double)a1, 3.0) / 8.485281374238571;\n v1 = round(v4 * 100.0);\n v2 = *(unsigned __int64 *)&v1;\n *(double *)&v2 = v1 / 100.0;\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__int128 __usercall sub_1189 @(int a1 @) {\n double v1;\n __int128 v2;\n double v4;\n v4 = pow((double)a1, 3.0) / 8.485281374238571;\n v1 = round(v4 * 100.0);\n v2 = *(unsigned long long *)&v1;\n *(double *)&v2 = v1 / 100.0;\n return v2;\n}", + "ida_pseudo_norm": "__int128 __usercall func0 @(int a1 @) {\n double v1;\n __int128 v2;\n double v4;\n v4 = pow((double)a1, 3.0) / 8.485281374238571;\n v1 = round(v4 * 100.0);\n v2 = *(unsigned long long *)&v1;\n *(double *)&v2 = v1 / 100.0;\n return v2;\n}" + }, + { + "index": 519, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int num) {\n double volume = (pow(num, 3) / (6 * sqrt(2)));\n return round(volume * 100) / 100;\n}", + "test": "int main() {\n\n assert(func0(10) == 117.85);\n\n assert(func0(15) == 397.75);\n\n assert(func0(20) == 942.81);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x8,%rsp\npxor %xmm0,%xmm0\ncvtsi2sd %edi,%xmm0\nmovsd 0xee7(%rip),%xmm1\ncallq 1080 \ndivsd 0xee2(%rip),%xmm0\nmulsd 0xee2(%rip),%xmm0\ncallq 1070 \ndivsd 0xed5(%rip),%xmm0\nadd $0x8,%rsp\nretq\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\npxor xmm0, xmm0\ncvtsi2sd xmm0, edi; x\nmovsd xmm1, cs:y; y\ncall _pow\ndivsd xmm0, cs:qword_2070\nmulsd xmm0, cs:qword_2078; x\ncall _round\ndivsd xmm0, cs:qword_2078\nadd rsp, 8\nretn", + "ida_pseudo": "double __fastcall func0(int a1)\n{\n double v1; // xmm0_8\n\n v1 = pow((double)a1, 3.0);\n return round(v1 / 8.485281374238571 * 100.0) / 100.0;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\nsub rsp, 8\npxor xmm0, xmm0\ncvtsi2sd xmm0, edi; x\nmovsd xmm1, cs:y; y\ncall _pow\ndivsd xmm0, cs:qword_2070\nmulsd xmm0, cs:qword_2078; x\ncall _round\ndivsd xmm0, cs:qword_2078\nadd rsp, 8\nretn", + "ida_strip_pseudo": "double __fastcall sub_1189(int a1)\n{\n double v1; // xmm0_8\n\n v1 = pow((double)a1, 3.0);\n return round(v1 / 8.485281374238571 * 100.0) / 100.0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1189(int a1) {\n double v1;\n v1 = pow((double)a1, 3.0);\n return round(v1 / 8.485281374238571 * 100.0) / 100.0;\n}", + "ida_pseudo_norm": "double func0(int a1) {\n double v1;\n v1 = pow((double)a1, 3.0);\n return round(v1 / 8.485281374238571 * 100.0) / 100.0;\n}" + }, + { + "index": 519, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int num) {\n double volume = (pow(num, 3) / (6 * sqrt(2)));\n return round(volume * 100) / 100;\n}", + "test": "int main() {\n\n assert(func0(10) == 117.85);\n\n assert(func0(15) == 397.75);\n\n assert(func0(20) == 942.81);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npxor %xmm0,%xmm0\nsub $0x8,%rsp\nmovsd 0xe34(%rip),%xmm1\ncvtsi2sd %edi,%xmm0\ncallq 1080 \ndivsd 0xe2b(%rip),%xmm0\nmulsd 0xe2b(%rip),%xmm0\ncallq 1070 \ndivsd 0xe1e(%rip),%xmm0\nadd $0x8,%rsp\nretq\n", + "ida_asm": "func0:\nendbr64\npxor xmm0, xmm0\nsub rsp, 8\nmovsd xmm1, cs:y; y\ncvtsi2sd xmm0, edi; x\ncall _pow\ndivsd xmm0, cs:qword_2070\nmulsd xmm0, cs:qword_2078; x\ncall _round\ndivsd xmm0, cs:qword_2078\nadd rsp, 8\nretn", + "ida_pseudo": "double __fastcall func0(int a1)\n{\n double v1; // xmm0_8\n\n v1 = pow((double)a1, 3.0);\n return round(v1 / 8.485281374238571 * 100.0) / 100.0;\n}", + "ida_strip_asm": "sub_1240:\nendbr64\npxor xmm0, xmm0\nsub rsp, 8\nmovsd xmm1, cs:y; y\ncvtsi2sd xmm0, edi; x\ncall _pow\ndivsd xmm0, cs:qword_2070\nmulsd xmm0, cs:qword_2078; x\ncall _round\ndivsd xmm0, cs:qword_2078\nadd rsp, 8\nretn", + "ida_strip_pseudo": "double __fastcall sub_1240(int a1)\n{\n double v1; // xmm0_8\n\n v1 = pow((double)a1, 3.0);\n return round(v1 / 8.485281374238571 * 100.0) / 100.0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1240(int a1) {\n double v1;\n v1 = pow((double)a1, 3.0);\n return round(v1 / 8.485281374238571 * 100.0) / 100.0;\n}", + "ida_pseudo_norm": "double func0(int a1) {\n double v1;\n v1 = pow((double)a1, 3.0);\n return round(v1 / 8.485281374238571 * 100.0) / 100.0;\n}" + }, + { + "index": 519, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int num) {\n double volume = (pow(num, 3) / (6 * sqrt(2)));\n return round(volume * 100) / 100;\n}", + "test": "int main() {\n\n assert(func0(10) == 117.85);\n\n assert(func0(15) == 397.75);\n\n assert(func0(20) == 942.81);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npxor %xmm0,%xmm0\nsub $0x8,%rsp\nmovsd 0xe34(%rip),%xmm1\ncvtsi2sd %edi,%xmm0\ncallq 1080 \ndivsd 0xe2b(%rip),%xmm0\nmulsd 0xe2b(%rip),%xmm0\ncallq 1070 \ndivsd 0xe1e(%rip),%xmm0\nadd $0x8,%rsp\nretq\n", + "ida_asm": "func0:\nendbr64\npxor xmm0, xmm0\nsub rsp, 8\nmovsd xmm1, cs:y; y\ncvtsi2sd xmm0, edi; x\ncall _pow\ndivsd xmm0, cs:qword_2070\nmulsd xmm0, cs:qword_2078; x\ncall _round\ndivsd xmm0, cs:qword_2078\nadd rsp, 8\nretn", + "ida_pseudo": "double __fastcall func0(int a1)\n{\n double v1; // xmm0_8\n\n v1 = pow((double)a1, 3.0);\n return round(v1 / 8.485281374238571 * 100.0) / 100.0;\n}", + "ida_strip_asm": "sub_1240:\nendbr64\npxor xmm0, xmm0\nsub rsp, 8\nmovsd xmm1, cs:y; y\ncvtsi2sd xmm0, edi; x\ncall _pow\ndivsd xmm0, cs:qword_2070\nmulsd xmm0, cs:qword_2078; x\ncall _round\ndivsd xmm0, cs:qword_2078\nadd rsp, 8\nretn", + "ida_strip_pseudo": "double __fastcall sub_1240(int a1)\n{\n double v1; // xmm0_8\n\n v1 = pow((double)a1, 3.0);\n return round(v1 / 8.485281374238571 * 100.0) / 100.0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1240(int a1) {\n double v1;\n v1 = pow((double)a1, 3.0);\n return round(v1 / 8.485281374238571 * 100.0) / 100.0;\n}", + "ida_pseudo_norm": "double func0(int a1) {\n double v1;\n v1 = pow((double)a1, 3.0);\n return round(v1 / 8.485281374238571 * 100.0) / 100.0;\n}" + }, + { + "index": 520, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nint find_lcm(int num1, int num2) {\n\n int num, den, rem, gcd, lcm;\n\n if (num1 > num2) {\n\n num = num1;\n\n den = num2;\n\n } else {\n\n num = num2;\n\n den = num1;\n\n }\n\n rem = num % den;\n\n while (rem != 0) {\n\n num = den;\n\n den = rem;\n\n rem = num % den;\n\n }\n\n gcd = den;\n\n lcm = (num1 * num2) / gcd;\n\n return lcm;\n\n}\n\n\n\n", + "func": "int func0(int *l, int size) {\n int num1 = l[0];\n int num2 = l[1];\n int lcm = find_lcm(num1, num2);\n for (int i = 2; i < size; i++) {\n lcm = find_lcm(lcm, l[i]);\n }\n return lcm;\n}", + "test": "int main() {\n\n int list1[] = {2, 7, 3, 9, 4};\n\n int list2[] = {1, 2, 8, 3};\n\n int list3[] = {3, 8, 4, 10, 5};\n\n\n\n assert(func0(list1, 5) == 252);\n\n assert(func0(list2, 4) == 24);\n\n assert(func0(list3, 5) == 120);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov -0x18(%rbp),%rax\nmov (%rax),%eax\nmov %eax,-0x8(%rbp)\nmov -0x18(%rbp),%rax\nmov 0x4(%rax),%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%edx\nmov -0x8(%rbp),%eax\nmov %edx,%esi\nmov %eax,%edi\ncallq 1169 \nmov %eax,-0x10(%rbp)\nmovl $0x2,-0xc(%rbp)\njmp 1244 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x10(%rbp),%eax\nmov %edx,%esi\nmov %eax,%edi\ncallq 1169 \nmov %eax,-0x10(%rbp)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 121b \nmov -0x10(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov rax, [rbp+var_18]\nmov eax, [rax]\nmov [rbp+var_8], eax\nmov rax, [rbp+var_18]\nmov eax, [rax+4]\nmov [rbp+var_4], eax\nmov edx, [rbp+var_4]\nmov eax, [rbp+var_8]\nmov esi, edx\nmov edi, eax\ncall find_lcm\nmov [rbp+var_10], eax\nmov [rbp+var_C], 2\njmp short loc_1244\nloc_121B:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\nmov esi, edx\nmov edi, eax\ncall find_lcm\nmov [rbp+var_10], eax\nadd [rbp+var_C], 1\nloc_1244:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_121B\nmov eax, [rbp+var_10]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n unsigned int lcm; // [rsp+10h] [rbp-10h]\n int i; // [rsp+14h] [rbp-Ch]\n\n lcm = find_lcm(*a1, a1[1]);\n for ( i = 2; i < a2; ++i )\n lcm = find_lcm(lcm, a1[i]);\n return lcm;\n}", + "ida_strip_asm": "sub_11DA:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov rax, [rbp+var_18]\nmov eax, [rax]\nmov [rbp+var_8], eax\nmov rax, [rbp+var_18]\nmov eax, [rax+4]\nmov [rbp+var_4], eax\nmov edx, [rbp+var_4]\nmov eax, [rbp+var_8]\nmov esi, edx\nmov edi, eax\ncall sub_1169\nmov [rbp+var_10], eax\nmov [rbp+var_C], 2\njmp short loc_1244\nloc_121B:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\nmov esi, edx\nmov edi, eax\ncall sub_1169\nmov [rbp+var_10], eax\nadd [rbp+var_C], 1\nloc_1244:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_121B\nmov eax, [rbp+var_10]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11DA(unsigned int *a1, int a2)\n{\n unsigned int v3; // [rsp+10h] [rbp-10h]\n int i; // [rsp+14h] [rbp-Ch]\n\n v3 = sub_1169(*a1, a1[1]);\n for ( i = 2; i < a2; ++i )\n v3 = sub_1169(v3, a1[i]);\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11DA(unsigned int *a1, int a2) {\n unsigned int v3;\n int i;\n v3 = sub_1169(*a1, a1[1]);\n for (i = 2; i < a2; ++i) v3 = sub_1169(v3, a1[i]);\n return v3;\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n unsigned int lcm;\n int i;\n lcm = find_lcm(*a1, a1[1]);\n for (i = 2; i < a2; ++i) lcm = find_lcm(lcm, a1[i]);\n return lcm;\n}" + }, + { + "index": 520, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nint find_lcm(int num1, int num2) {\n\n int num, den, rem, gcd, lcm;\n\n if (num1 > num2) {\n\n num = num1;\n\n den = num2;\n\n } else {\n\n num = num2;\n\n den = num1;\n\n }\n\n rem = num % den;\n\n while (rem != 0) {\n\n num = den;\n\n den = rem;\n\n rem = num % den;\n\n }\n\n gcd = den;\n\n lcm = (num1 * num2) / gcd;\n\n return lcm;\n\n}\n\n\n\n", + "func": "int func0(int *l, int size) {\n int num1 = l[0];\n int num2 = l[1];\n int lcm = find_lcm(num1, num2);\n for (int i = 2; i < size; i++) {\n lcm = find_lcm(lcm, l[i]);\n }\n return lcm;\n}", + "test": "int main() {\n\n int list1[] = {2, 7, 3, 9, 4};\n\n int list2[] = {1, 2, 8, 3};\n\n int list3[] = {3, 8, 4, 10, 5};\n\n\n\n assert(func0(list1, 5) == 252);\n\n assert(func0(list2, 4) == 24);\n\n assert(func0(list3, 5) == 120);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbp\nmov %esi,%r12d\nmov 0x4(%rdi),%esi\nmov (%rdi),%edi\ncallq 1169 \nmov %eax,%edi\ncmp $0x2,%r12d\njle 11e7 \nlea 0x8(%rbp),%rbx\nlea -0x3(%r12),%eax\nlea 0xc(%rbp,%rax,4),%rbp\nmov (%rbx),%esi\ncallq 1169 \nmov %eax,%edi\nadd $0x4,%rbx\ncmp %rbp,%rbx\njne 11d5 \nmov %edi,%eax\npop %rbx\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbp, rdi\nmov r12d, esi\nmov esi, [rdi+4]\nmov edi, [rdi]\ncall find_lcm\nmov edi, eax\ncmp r12d, 2\njle short loc_11E7\nlea rbx, [rbp+8]\nlea eax, [r12-3]\nlea rbp, [rbp+rax*4+0Ch]\nloc_11D5:\nmov esi, [rbx]\ncall find_lcm\nmov edi, eax\nadd rbx, 4\ncmp rbx, rbp\njnz short loc_11D5\nloc_11E7:\nmov eax, edi\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n __int64 lcm; // rdi\n unsigned int *v4; // rbx\n __int64 v5; // rbp\n\n lcm = (unsigned int)find_lcm(*a1, a1[1]);\n if ( a2 > 2 )\n {\n v4 = a1 + 2;\n v5 = (__int64)&a1[a2 - 3 + 3];\n do\n LODWORD(lcm) = find_lcm(lcm, *v4++);\n while ( v4 != (unsigned int *)v5 );\n }\n return (unsigned int)lcm;\n}", + "ida_strip_asm": "sub_11A7:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbp, rdi\nmov r12d, esi\nmov esi, [rdi+4]\nmov edi, [rdi]\ncall sub_1169\nmov edi, eax\ncmp r12d, 2\njle short loc_11E7\nlea rbx, [rbp+8]\nlea eax, [r12-3]\nlea rbp, [rbp+rax*4+0Ch]\nloc_11D5:\nmov esi, [rbx]\ncall sub_1169\nmov edi, eax\nadd rbx, 4\ncmp rbx, rbp\njnz short loc_11D5\nloc_11E7:\nmov eax, edi\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11A7(unsigned int *a1, int a2)\n{\n __int64 v3; // rdi\n unsigned int *v4; // rbx\n __int64 v5; // rbp\n\n v3 = (unsigned int)sub_1169(*a1, a1[1]);\n if ( a2 > 2 )\n {\n v4 = a1 + 2;\n v5 = (__int64)&a1[a2 - 3 + 3];\n do\n LODWORD(v3) = sub_1169(v3, *v4++);\n while ( v4 != (unsigned int *)v5 );\n }\n return (unsigned int)v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A7(unsigned int *a1, int a2) {\n long long v3;\n unsigned int *v4;\n long long v5;\n v3 = (unsigned int)sub_1169(*a1, a1[1]);\n if (a2 > 2) {\n v4 = a1 + 2;\n v5 = (long long)&a1[a2 - 3 + 3];\n do\n LODWORD(v3) = sub_1169(v3, *v4++);\n while (v4 != (unsigned int *)v5);\n }\n return (unsigned int)v3;\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n long long lcm;\n unsigned int *v4;\n long long v5;\n lcm = (unsigned int)find_lcm(*a1, a1[1]);\n if (a2 > 2) {\n v4 = a1 + 2;\n v5 = (long long)&a1[a2 - 3 + 3];\n do\n LODWORD(lcm) = find_lcm(lcm, *v4++);\n while (v4 != (unsigned int *)v5);\n }\n return (unsigned int)lcm;\n}" + }, + { + "index": 520, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nint find_lcm(int num1, int num2) {\n\n int num, den, rem, gcd, lcm;\n\n if (num1 > num2) {\n\n num = num1;\n\n den = num2;\n\n } else {\n\n num = num2;\n\n den = num1;\n\n }\n\n rem = num % den;\n\n while (rem != 0) {\n\n num = den;\n\n den = rem;\n\n rem = num % den;\n\n }\n\n gcd = den;\n\n lcm = (num1 * num2) / gcd;\n\n return lcm;\n\n}\n\n\n\n", + "func": "int func0(int *l, int size) {\n int num1 = l[0];\n int num2 = l[1];\n int lcm = find_lcm(num1, num2);\n for (int i = 2; i < size; i++) {\n lcm = find_lcm(lcm, l[i]);\n }\n return lcm;\n}", + "test": "int main() {\n\n int list1[] = {2, 7, 3, 9, 4};\n\n int list2[] = {1, 2, 8, 3};\n\n int list3[] = {3, 8, 4, 10, 5};\n\n\n\n assert(func0(list1, 5) == 252);\n\n assert(func0(list2, 4) == 24);\n\n assert(func0(list3, 5) == 120);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov (%rdi),%r8d\nmov 0x4(%rdi),%r10d\ncmp %r10d,%r8d\njg 13b0 \nmov %r10d,%eax\nmov %r8d,%ecx\ncltd\nidiv %ecx\ntest %edx,%edx\nje 13c1 \nnopl (%rax)\nmov %ecx,%eax\nmov %edx,%r9d\nmov %edx,%ecx\ncltd\nidiv %r9d\ntest %edx,%edx\njne 1328 \nimul %r10d,%r8d\nmov %r8d,%eax\ncltd\nidiv %r9d\nmov %eax,%r8d\ncmp $0x2,%esi\njle 139b \nlea -0x3(%rsi),%eax\nlea 0x8(%rdi),%r9\nlea 0xc(%rdi,%rax,4),%r10\nnopw %cs:0x0(%rax,%rax,1)\nmov (%r9),%edi\ncmp %r8d,%edi\njl 13a0 \nmov %edi,%eax\nmov %r8d,%ecx\ncltd\nidiv %ecx\ntest %edx,%edx\nje 13ac \nnopl 0x0(%rax)\nmov %ecx,%eax\nmov %edx,%esi\nmov %edx,%ecx\ncltd\nidiv %esi\ntest %edx,%edx\njne 1378 \nimul %edi,%r8d\nadd $0x4,%r9\nmov %r8d,%eax\ncltd\nidiv %esi\nmov %eax,%r8d\ncmp %r10,%r9\njne 1360 \nmov %r8d,%eax\nretq\nmov %r8d,%eax\nmov %edi,%ecx\ncltd\nidiv %ecx\ntest %edx,%edx\njne 1378 \nmov %ecx,%esi\njmp 1385 \nmov %r8d,%eax\nmov %r10d,%ecx\ncltd\nidiv %ecx\ntest %edx,%edx\njne 1328 \nmov %ecx,%r9d\njmpq 1337 \nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\nmov r8d, [rdi]\nmov r10d, [rdi+4]\nmov r9d, esi\ncmp r8d, r10d\njle loc_1380\nmov eax, r8d\nmov ecx, r10d\ncdq\nidiv ecx\ntest edx, edx\njz loc_1391\nnop dword ptr [rax+rax+00000000h]\nloc_1300:\nmov eax, ecx\nmov esi, edx\nmov ecx, edx\ncdq\nidiv esi\ntest edx, edx\njnz short loc_1300\nloc_130D:\nimul r8d, r10d\nmov eax, r8d\ncdq\nidiv esi\nmov r8d, eax\ncmp r9d, 2\njle short loc_136B\nlea eax, [r9-3]\nlea r10, [rdi+8]\nlea r9, [rdi+rax*4+0Ch]\nnop dword ptr [rax]\nloc_1330:\nmov edi, [r10]\ncmp edi, r8d\njge short loc_1370\nmov eax, r8d\nmov ecx, edi\ncdq\nidiv ecx\ntest edx, edx\njz short loc_137C\nnop dword ptr [rax+00h]\nloc_1348:\nmov eax, ecx\nmov esi, edx\nmov ecx, edx\ncdq\nidiv esi\ntest edx, edx\njnz short loc_1348\nloc_1355:\nimul r8d, edi\nadd r10, 4\nmov eax, r8d\ncdq\nidiv esi\nmov r8d, eax\ncmp r10, r9\njnz short loc_1330\nloc_136B:\nmov eax, r8d\nretn\nloc_1370:\nmov eax, edi\nmov ecx, r8d\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_1348\nloc_137C:\nmov esi, ecx\njmp short loc_1355\nloc_1380:\nmov eax, r10d\nmov ecx, r8d\ncdq\nidiv ecx\ntest edx, edx\njnz loc_1300\nloc_1391:\nmov esi, ecx\njmp loc_130D", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int v2; // r8d\n int v3; // r10d\n int v5; // ecx\n int v6; // edx\n int v7; // eax\n int v8; // esi\n int v9; // r8d\n int *v10; // r10\n __int64 v11; // r9\n int v12; // edi\n int v13; // ecx\n int v14; // edx\n int v15; // eax\n int v16; // esi\n\n v2 = *a1;\n v3 = a1[1];\n if ( *a1 > v3 )\n {\n v5 = a1[1];\n v6 = v2 % v3;\n if ( v2 % v3 )\n goto LABEL_3;\nLABEL_14:\n v8 = v5;\n goto LABEL_4;\n }\n v5 = *a1;\n v6 = v3 % v2;\n if ( !(v3 % v2) )\n goto LABEL_14;\n do\n {\nLABEL_3:\n v7 = v5;\n v8 = v6;\n v5 = v6;\n v6 = v7 % v6;\n }\n while ( v6 );\nLABEL_4:\n v9 = v3 * v2 / v8;\n if ( a2 > 2 )\n {\n v10 = a1 + 2;\n v11 = (__int64)&a1[a2 - 3 + 3];\n do\n {\n v12 = *v10;\n if ( *v10 >= v9 )\n {\n v13 = v9;\n v14 = v12 % v9;\n if ( v12 % v9 )\n {\n do\n {\nLABEL_8:\n v15 = v13;\n v16 = v14;\n v13 = v14;\n v14 = v15 % v14;\n }\n while ( v14 );\n goto LABEL_9;\n }\n }\n else\n {\n v13 = *v10;\n v14 = v9 % v12;\n if ( v9 % v12 )\n goto LABEL_8;\n }\n v16 = v13;\nLABEL_9:\n ++v10;\n v9 = v12 * v9 / v16;\n }\n while ( v10 != (int *)v11 );\n }\n return (unsigned int)v9;\n}", + "ida_strip_asm": "sub_12D0:\nendbr64\nmov r8d, [rdi]\nmov r10d, [rdi+4]\nmov r9d, esi\ncmp r8d, r10d\njle loc_1380\nmov eax, r8d\nmov ecx, r10d\ncdq\nidiv ecx\ntest edx, edx\njz loc_1391\nnop dword ptr [rax+rax+00000000h]\nloc_1300:\nmov eax, ecx\nmov esi, edx\nmov ecx, edx\ncdq\nidiv esi\ntest edx, edx\njnz short loc_1300\nloc_130D:\nimul r8d, r10d\nmov eax, r8d\ncdq\nidiv esi\nmov r8d, eax\ncmp r9d, 2\njle short loc_136B\nlea eax, [r9-3]\nlea r10, [rdi+8]\nlea r9, [rdi+rax*4+0Ch]\nnop dword ptr [rax]\nloc_1330:\nmov edi, [r10]\ncmp edi, r8d\njge short loc_1370\nmov eax, r8d\nmov ecx, edi\ncdq\nidiv ecx\ntest edx, edx\njz short loc_137C\nnop dword ptr [rax+00h]\nloc_1348:\nmov eax, ecx\nmov esi, edx\nmov ecx, edx\ncdq\nidiv esi\ntest edx, edx\njnz short loc_1348\nloc_1355:\nimul r8d, edi\nadd r10, 4\nmov eax, r8d\ncdq\nidiv esi\nmov r8d, eax\ncmp r10, r9\njnz short loc_1330\nloc_136B:\nmov eax, r8d\nretn\nloc_1370:\nmov eax, edi\nmov ecx, r8d\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_1348\nloc_137C:\nmov esi, ecx\njmp short loc_1355\nloc_1380:\nmov eax, r10d\nmov ecx, r8d\ncdq\nidiv ecx\ntest edx, edx\njnz loc_1300\nloc_1391:\nmov esi, ecx\njmp loc_130D", + "ida_strip_pseudo": "__int64 __fastcall sub_12D0(int *a1, int a2)\n{\n int v2; // r8d\n int v3; // r10d\n int v5; // ecx\n int v6; // edx\n int v7; // eax\n int v8; // esi\n int v9; // r8d\n int *v10; // r10\n __int64 v11; // r9\n int v12; // edi\n int v13; // ecx\n int v14; // edx\n int v15; // eax\n int v16; // esi\n\n v2 = *a1;\n v3 = a1[1];\n if ( *a1 > v3 )\n {\n v5 = a1[1];\n v6 = v2 % v3;\n if ( v2 % v3 )\n goto LABEL_3;\nLABEL_14:\n v8 = v5;\n goto LABEL_4;\n }\n v5 = *a1;\n v6 = v3 % v2;\n if ( !(v3 % v2) )\n goto LABEL_14;\n do\n {\nLABEL_3:\n v7 = v5;\n v8 = v6;\n v5 = v6;\n v6 = v7 % v6;\n }\n while ( v6 );\nLABEL_4:\n v9 = v3 * v2 / v8;\n if ( a2 > 2 )\n {\n v10 = a1 + 2;\n v11 = (__int64)&a1[a2 - 3 + 3];\n do\n {\n v12 = *v10;\n if ( *v10 >= v9 )\n {\n v13 = v9;\n v14 = v12 % v9;\n if ( v12 % v9 )\n {\n do\n {\nLABEL_8:\n v15 = v13;\n v16 = v14;\n v13 = v14;\n v14 = v15 % v14;\n }\n while ( v14 );\n goto LABEL_9;\n }\n }\n else\n {\n v13 = *v10;\n v14 = v9 % v12;\n if ( v9 % v12 )\n goto LABEL_8;\n }\n v16 = v13;\nLABEL_9:\n ++v10;\n v9 = v12 * v9 / v16;\n }\n while ( v10 != (int *)v11 );\n }\n return (unsigned int)v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12D0(int *a1, int a2) {\n int v2;\n int v3;\n int v5;\n int v6;\n int v7;\n int v8;\n int v9;\n int *v10;\n long long v11;\n int v12;\n int v13;\n int v14;\n int v15;\n int v16;\n v2 = *a1;\n v3 = a1[1];\n if (*a1 > v3) {\n v5 = a1[1];\n v6 = v2 % v3;\n if (v2 % v3) goto LABEL_3;\n LABEL_14:\n v8 = v5;\n goto LABEL_4;\n }\n v5 = *a1;\n v6 = v3 % v2;\n if (!(v3 % v2)) goto LABEL_14;\n do {\n LABEL_3:\n v7 = v5;\n v8 = v6;\n v5 = v6;\n v6 = v7 % v6;\n } while (v6);\nLABEL_4:\n v9 = v3 * v2 / v8;\n if (a2 > 2) {\n v10 = a1 + 2;\n v11 = (long long)&a1[a2 - 3 + 3];\n do {\n v12 = *v10;\n if (*v10 >= v9) {\n v13 = v9;\n v14 = v12 % v9;\n if (v12 % v9) {\n do {\n LABEL_8:\n v15 = v13;\n v16 = v14;\n v13 = v14;\n v14 = v15 % v14;\n } while (v14);\n goto LABEL_9;\n }\n } else {\n v13 = *v10;\n v14 = v9 % v12;\n if (v9 % v12) goto LABEL_8;\n }\n v16 = v13;\n LABEL_9:\n ++v10;\n v9 = v12 * v9 / v16;\n } while (v10 != (int *)v11);\n }\n return (unsigned int)v9;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int v2;\n int v3;\n int v5;\n int v6;\n int v7;\n int v8;\n int v9;\n int *v10;\n long long v11;\n int v12;\n int v13;\n int v14;\n int v15;\n int v16;\n v2 = *a1;\n v3 = a1[1];\n if (*a1 > v3) {\n v5 = a1[1];\n v6 = v2 % v3;\n if (v2 % v3) goto LABEL_3;\n LABEL_14:\n v8 = v5;\n goto LABEL_4;\n }\n v5 = *a1;\n v6 = v3 % v2;\n if (!(v3 % v2)) goto LABEL_14;\n do {\n LABEL_3:\n v7 = v5;\n v8 = v6;\n v5 = v6;\n v6 = v7 % v6;\n } while (v6);\nLABEL_4:\n v9 = v3 * v2 / v8;\n if (a2 > 2) {\n v10 = a1 + 2;\n v11 = (long long)&a1[a2 - 3 + 3];\n do {\n v12 = *v10;\n if (*v10 >= v9) {\n v13 = v9;\n v14 = v12 % v9;\n if (v12 % v9) {\n do {\n LABEL_8:\n v15 = v13;\n v16 = v14;\n v13 = v14;\n v14 = v15 % v14;\n } while (v14);\n goto LABEL_9;\n }\n } else {\n v13 = *v10;\n v14 = v9 % v12;\n if (v9 % v12) goto LABEL_8;\n }\n v16 = v13;\n LABEL_9:\n ++v10;\n v9 = v12 * v9 / v16;\n } while (v10 != (int *)v11);\n }\n return (unsigned int)v9;\n}" + }, + { + "index": 520, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nint find_lcm(int num1, int num2) {\n\n int num, den, rem, gcd, lcm;\n\n if (num1 > num2) {\n\n num = num1;\n\n den = num2;\n\n } else {\n\n num = num2;\n\n den = num1;\n\n }\n\n rem = num % den;\n\n while (rem != 0) {\n\n num = den;\n\n den = rem;\n\n rem = num % den;\n\n }\n\n gcd = den;\n\n lcm = (num1 * num2) / gcd;\n\n return lcm;\n\n}\n\n\n\n", + "func": "int func0(int *l, int size) {\n int num1 = l[0];\n int num2 = l[1];\n int lcm = find_lcm(num1, num2);\n for (int i = 2; i < size; i++) {\n lcm = find_lcm(lcm, l[i]);\n }\n return lcm;\n}", + "test": "int main() {\n\n int list1[] = {2, 7, 3, 9, 4};\n\n int list2[] = {1, 2, 8, 3};\n\n int list3[] = {3, 8, 4, 10, 5};\n\n\n\n assert(func0(list1, 5) == 252);\n\n assert(func0(list2, 4) == 24);\n\n assert(func0(list3, 5) == 120);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nmov (%rdi),%r8d\nmov 0x4(%rdi),%r9d\nmov %rdi,%r10\ncmp %r9d,%r8d\njg 1387 \nmov %r8d,%ecx\nmov %r9d,%edi\nmov %edi,%eax\nimul %r8d,%r9d\ncltd\nidiv %ecx\ntest %edx,%edx\nje 1319 \nnopw 0x0(%rax,%rax,1)\nmov %ecx,%eax\nmov %edx,%r8d\ncltd\nmov %r8d,%ecx\nidiv %r8d\ntest %edx,%edx\njne 1300 \nmov %r9d,%eax\ncltd\nidiv %r8d\nmov %eax,%edi\ncmp $0x2,%esi\njle 136b \nlea -0x3(%rsi),%eax\nlea 0x8(%r10),%r8\nlea 0xc(%r10,%rax,4),%r10\nnopw 0x0(%rax,%rax,1)\nmov (%r8),%esi\ncmp %edi,%esi\njl 1370 \nmov %esi,%r9d\nmov %edi,%ecx\nmov %r9d,%eax\nimul %esi,%edi\ncltd\nidiv %ecx\ntest %edx,%edx\nje 1382 \nnopl 0x0(%rax)\nmov %ecx,%eax\nmov %edx,%ecx\ncltd\nidiv %ecx\ntest %edx,%edx\njne 1350 \nmov %edi,%eax\ncltd\nidiv %ecx\nmov %eax,%edi\nadd $0x4,%r8\ncmp %r8,%r10\njne 1330 \nmov %edi,%eax\nretq\nxchg %ax,%ax\nmov %edi,%r9d\nimul %esi,%edi\nmov %esi,%ecx\nmov %r9d,%eax\ncltd\nidiv %ecx\ntest %edx,%edx\njne 1350 \nmov %r9d,%edi\njmp 1362 \nmov %r9d,%ecx\nmov %r8d,%edi\njmpq 12ed \nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\nmov r8d, [rdi]\nmov r10d, [rdi+4]\nmov r9, rdi\ncmp r8d, r10d\njle loc_1387\nmov ecx, r10d\nmov edi, r8d\nloc_12ED:\nmov eax, edi\nimul r8d, r10d\ncdq\nidiv ecx\ntest edx, edx\njz short loc_1313\nnop word ptr [rax+rax+00h]\nloc_1300:\nmov eax, ecx\nmov ecx, edx\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_1300\nmov eax, r8d\ncdq\nidiv ecx\nmov edi, eax\nloc_1313:\ncmp esi, 2\njle short loc_1363\nlea eax, [rsi-3]\nlea r8, [r9+8]\nlea r10, [r9+rax*4+0Ch]\nnop dword ptr [rax+00h]\nloc_1328:\nmov esi, [r8]\ncmp esi, edi\njge short loc_1370\nmov r9d, edi\nimul edi, esi\nmov ecx, esi\nmov eax, r9d\ncdq\nidiv ecx\ntest edx, edx\njz short loc_1382\nnop dword ptr [rax+00000000h]\nloc_1348:\nmov eax, ecx\nmov ecx, edx\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_1348\nmov eax, edi\ncdq\nidiv ecx\nmov edi, eax\nloc_135A:\nadd r8, 4\ncmp r10, r8\njnz short loc_1328\nloc_1363:\nmov eax, edi\nretn\nloc_1370:\nmov r9d, esi\nmov ecx, edi\nmov eax, r9d\nimul edi, esi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_1348\nloc_1382:\nmov edi, r9d\njmp short loc_135A\nloc_1387:\nmov ecx, r8d\nmov edi, r10d\njmp loc_12ED", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int v2; // r8d\n int v3; // r10d\n int v5; // ecx\n int v6; // edi\n int v7; // r8d\n int v8; // edx\n int v9; // eax\n int *v10; // r8\n __int64 v11; // r10\n int v12; // esi\n int v13; // r9d\n int v14; // edi\n int v15; // ecx\n int v16; // edx\n int v17; // eax\n\n v2 = *a1;\n v3 = a1[1];\n if ( *a1 <= v3 )\n {\n v5 = *a1;\n v6 = a1[1];\n }\n else\n {\n v5 = a1[1];\n v6 = *a1;\n }\n v7 = v3 * v2;\n v8 = v6 % v5;\n if ( v6 % v5 )\n {\n do\n {\n v9 = v5;\n v5 = v8;\n v8 = v9 % v8;\n }\n while ( v8 );\n v6 = v7 / v5;\n }\n if ( a2 > 2 )\n {\n v10 = a1 + 2;\n v11 = (__int64)&a1[a2 - 3 + 3];\n do\n {\n v12 = *v10;\n if ( *v10 >= v6 )\n {\n v13 = *v10;\n v15 = v6;\n v14 = v12 * v6;\n v16 = v12 % v15;\n if ( v12 % v15 )\n {\n do\n {\nLABEL_10:\n v17 = v15;\n v15 = v16;\n v16 = v17 % v16;\n }\n while ( v16 );\n v6 = v14 / v15;\n goto LABEL_12;\n }\n }\n else\n {\n v13 = v6;\n v14 = v12 * v6;\n v15 = *v10;\n v16 = v13 % v12;\n if ( v13 % v12 )\n goto LABEL_10;\n }\n v6 = v13;\nLABEL_12:\n ++v10;\n }\n while ( (int *)v11 != v10 );\n }\n return (unsigned int)v6;\n}", + "ida_strip_asm": "sub_12D0:\nendbr64\nmov r8d, [rdi]\nmov r10d, [rdi+4]\nmov r9, rdi\ncmp r8d, r10d\njle loc_1387\nmov ecx, r10d\nmov edi, r8d\nloc_12ED:\nmov eax, edi\nimul r8d, r10d\ncdq\nidiv ecx\ntest edx, edx\njz short loc_1313\nnop word ptr [rax+rax+00h]\nloc_1300:\nmov eax, ecx\nmov ecx, edx\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_1300\nmov eax, r8d\ncdq\nidiv ecx\nmov edi, eax\nloc_1313:\ncmp esi, 2\njle short loc_1363\nlea eax, [rsi-3]\nlea r8, [r9+8]\nlea r10, [r9+rax*4+0Ch]\nnop dword ptr [rax+00h]\nloc_1328:\nmov esi, [r8]\ncmp esi, edi\njge short loc_1370\nmov r9d, edi\nimul edi, esi\nmov ecx, esi\nmov eax, r9d\ncdq\nidiv ecx\ntest edx, edx\njz short loc_1382\nnop dword ptr [rax+00000000h]\nloc_1348:\nmov eax, ecx\nmov ecx, edx\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_1348\nmov eax, edi\ncdq\nidiv ecx\nmov edi, eax\nloc_135A:\nadd r8, 4\ncmp r10, r8\njnz short loc_1328\nloc_1363:\nmov eax, edi\nretn\nloc_1370:\nmov r9d, esi\nmov ecx, edi\nmov eax, r9d\nimul edi, esi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_1348\nloc_1382:\nmov edi, r9d\njmp short loc_135A\nloc_1387:\nmov ecx, r8d\nmov edi, r10d\njmp loc_12ED", + "ida_strip_pseudo": "__int64 __fastcall sub_12D0(int *a1, int a2)\n{\n int v2; // r8d\n int v3; // r10d\n int v5; // ecx\n int v6; // edi\n int v7; // r8d\n int v8; // edx\n int v9; // eax\n int *v10; // r8\n __int64 v11; // r10\n int v12; // esi\n int v13; // r9d\n int v14; // edi\n int v15; // ecx\n int v16; // edx\n int v17; // eax\n\n v2 = *a1;\n v3 = a1[1];\n if ( *a1 <= v3 )\n {\n v5 = *a1;\n v6 = a1[1];\n }\n else\n {\n v5 = a1[1];\n v6 = *a1;\n }\n v7 = v3 * v2;\n v8 = v6 % v5;\n if ( v6 % v5 )\n {\n do\n {\n v9 = v5;\n v5 = v8;\n v8 = v9 % v8;\n }\n while ( v8 );\n v6 = v7 / v5;\n }\n if ( a2 > 2 )\n {\n v10 = a1 + 2;\n v11 = (__int64)&a1[a2 - 3 + 3];\n do\n {\n v12 = *v10;\n if ( *v10 >= v6 )\n {\n v13 = *v10;\n v15 = v6;\n v14 = v12 * v6;\n v16 = v12 % v15;\n if ( v12 % v15 )\n {\n do\n {\nLABEL_10:\n v17 = v15;\n v15 = v16;\n v16 = v17 % v16;\n }\n while ( v16 );\n v6 = v14 / v15;\n goto LABEL_12;\n }\n }\n else\n {\n v13 = v6;\n v14 = v12 * v6;\n v15 = *v10;\n v16 = v13 % v12;\n if ( v13 % v12 )\n goto LABEL_10;\n }\n v6 = v13;\nLABEL_12:\n ++v10;\n }\n while ( (int *)v11 != v10 );\n }\n return (unsigned int)v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12D0(int *a1, int a2) {\n int v2;\n int v3;\n int v5;\n int v6;\n int v7;\n int v8;\n int v9;\n int *v10;\n long long v11;\n int v12;\n int v13;\n int v14;\n int v15;\n int v16;\n int v17;\n v2 = *a1;\n v3 = a1[1];\n if (*a1 <= v3) {\n v5 = *a1;\n v6 = a1[1];\n } else {\n v5 = a1[1];\n v6 = *a1;\n }\n v7 = v3 * v2;\n v8 = v6 % v5;\n if (v6 % v5) {\n do {\n v9 = v5;\n v5 = v8;\n v8 = v9 % v8;\n } while (v8);\n v6 = v7 / v5;\n }\n if (a2 > 2) {\n v10 = a1 + 2;\n v11 = (long long)&a1[a2 - 3 + 3];\n do {\n v12 = *v10;\n if (*v10 >= v6) {\n v13 = *v10;\n v15 = v6;\n v14 = v12 * v6;\n v16 = v12 % v15;\n if (v12 % v15) {\n do {\n LABEL_10:\n v17 = v15;\n v15 = v16;\n v16 = v17 % v16;\n } while (v16);\n v6 = v14 / v15;\n goto LABEL_12;\n }\n } else {\n v13 = v6;\n v14 = v12 * v6;\n v15 = *v10;\n v16 = v13 % v12;\n if (v13 % v12) goto LABEL_10;\n }\n v6 = v13;\n LABEL_12:\n ++v10;\n } while ((int *)v11 != v10);\n }\n return (unsigned int)v6;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int v2;\n int v3;\n int v5;\n int v6;\n int v7;\n int v8;\n int v9;\n int *v10;\n long long v11;\n int v12;\n int v13;\n int v14;\n int v15;\n int v16;\n int v17;\n v2 = *a1;\n v3 = a1[1];\n if (*a1 <= v3) {\n v5 = *a1;\n v6 = a1[1];\n } else {\n v5 = a1[1];\n v6 = *a1;\n }\n v7 = v3 * v2;\n v8 = v6 % v5;\n if (v6 % v5) {\n do {\n v9 = v5;\n v5 = v8;\n v8 = v9 % v8;\n } while (v8);\n v6 = v7 / v5;\n }\n if (a2 > 2) {\n v10 = a1 + 2;\n v11 = (long long)&a1[a2 - 3 + 3];\n do {\n v12 = *v10;\n if (*v10 >= v6) {\n v13 = *v10;\n v15 = v6;\n v14 = v12 * v6;\n v16 = v12 % v15;\n if (v12 % v15) {\n do {\n LABEL_10:\n v17 = v15;\n v15 = v16;\n v16 = v17 % v16;\n } while (v16);\n v6 = v14 / v15;\n goto LABEL_12;\n }\n } else {\n v13 = v6;\n v14 = v12 * v6;\n v15 = *v10;\n v16 = v13 % v12;\n if (v13 % v12) goto LABEL_10;\n }\n v6 = v13;\n LABEL_12:\n ++v10;\n } while ((int *)v11 != v10);\n }\n return (unsigned int)v6;\n}" + }, + { + "index": 521, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int x, int y, int z) {\n if (x != y && y != z && z != x) {\n return true;\n } else {\n return false;\n }\n}", + "test": "int main() {\n\n assert(func0(6, 8, 12) == true);\n\n assert(func0(6, 6, 12) == false);\n\n assert(func0(6, 15, 20) == true);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov %esi,-0x8(%rbp)\nmov %edx,-0xc(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x8(%rbp),%eax\nje 1179 \nmov -0x8(%rbp),%eax\ncmp -0xc(%rbp),%eax\nje 1179 \nmov -0xc(%rbp),%eax\ncmp -0x4(%rbp),%eax\nje 1179 \nmov $0x1,%eax\njmp 117e \nmov $0x0,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov [rbp+var_C], edx\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_8]\njz short loc_1179\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_C]\njz short loc_1179\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_4]\njz short loc_1179\nmov eax, 1\njmp short loc_117E\nloc_1179:\nmov eax, 0\nloc_117E:\npop rbp\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(int a1, int a2, int a3)\n{\n return a1 != a2 && a2 != a3 && a3 != a1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov [rbp+var_C], edx\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_8]\njz short loc_1179\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_C]\njz short loc_1179\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_4]\njz short loc_1179\nmov eax, 1\njmp short loc_117E\nloc_1179:\nmov eax, 0\nloc_117E:\npop rbp\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1149(int a1, int a2, int a3)\n{\n return a1 != a2 && a2 != a3 && a3 != a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1149(int a1, int a2, int a3) {\n return a1 != a2 && a2 != a3 && a3 != a1;\n}", + "ida_pseudo_norm": "uint8_t func0(int a1, int a2, int a3) {\n return a1 != a2 && a2 != a3 && a3 != a1;\n}" + }, + { + "index": 522, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int lis[n + 1];\n int lds[n + 1];\n int i, j, maximum;\n for (i = 0; i <= n; i++) {\n lis[i] = 1;\n }\n for (i = 1; i < n; i++) {\n for (j = 0; j < i; j++) {\n if (arr[i] > arr[j] && lis[i] < lis[j] + 1) {\n lis[i] = lis[j] + 1;\n }\n }\n }\n for (i = 0; i <= n; i++) {\n lds[i] = 1;\n }\n for (i = n - 2; i >= 0; i--) {\n for (j = n - 1; j > i; j--) {\n if (arr[i] > arr[j] && lds[i] < lds[j] + 1) {\n lds[i] = lds[j] + 1;\n }\n }\n }\n maximum = lis[0] + lds[0] - 1;\n for (i = 1; i < n; i++) {\n if ((lis[i] + lds[i] - 1) > maximum) {\n maximum = lis[i] + lds[i] - 1;\n }\n }\n return maximum;\n}", + "test": "int main() {\n\n int arr1[] = {0, 8, 4, 12, 2, 10, 6, 14, 1, 9, 5, 13, 3, 11, 7, 15};\n\n int arr2[] = {1, 11, 2, 10, 4, 5, 2, 1};\n\n int arr3[] = {80, 60, 30, 40, 20, 10};\n\n\n\n assert(func0(arr1, sizeof(arr1)/sizeof(arr1[0])) == 7);\n\n assert(func0(arr2, sizeof(arr2)/sizeof(arr2[0])) == 6);\n\n assert(func0(arr3, sizeof(arr3)/sizeof(arr3[0])) == 5);\n\n \n\n printf(\"All tests passed.\\n\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r13\npush %r12\npush %rbx\nsub $0x58,%rsp\nmov %rdi,-0x68(%rbp)\nmov %esi,-0x6c(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x28(%rbp)\nxor %eax,%eax\nmov %rsp,%rax\nmov %rax,%rsi\nmov -0x6c(%rbp),%eax\nadd $0x1,%eax\nmovslq %eax,%rdx\nsub $0x1,%rdx\nmov %rdx,-0x48(%rbp)\nmovslq %eax,%rdx\nmov %rdx,%r12\nmov $0x0,%r13d\nmovslq %eax,%rdx\nmov %rdx,%r10\nmov $0x0,%r11d\ncltq\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%edi\nmov $0x0,%edx\ndiv %rdi\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rdi\nsub %rdx,%rdi\nmov %rdi,%rdx\ncmp %rdx,%rsp\nje 1230 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 1219 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 125a \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x40(%rbp)\nmov -0x6c(%rbp),%eax\nadd $0x1,%eax\nmovslq %eax,%rdx\nsub $0x1,%rdx\nmov %rdx,-0x38(%rbp)\nmovslq %eax,%rdx\nmov %rdx,%r8\nmov $0x0,%r9d\nmovslq %eax,%rdx\nmov %rdx,%rcx\nmov $0x0,%ebx\ncltq\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%ebx\nmov $0x0,%edx\ndiv %rbx\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rbx\nsub %rdx,%rbx\nmov %rbx,%rdx\ncmp %rdx,%rsp\nje 12e6 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 12cf \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 1310 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x30(%rbp)\nmovl $0x0,-0x4c(%rbp)\njmp 1341 \nmov -0x40(%rbp),%rax\nmov -0x4c(%rbp),%edx\nmovslq %edx,%rdx\nmovl $0x1,(%rax,%rdx,4)\naddl $0x1,-0x4c(%rbp)\nmov -0x4c(%rbp),%eax\ncmp -0x6c(%rbp),%eax\njle 132c \nmovl $0x1,-0x4c(%rbp)\njmpq 13d9 \nmovl $0x0,-0x50(%rbp)\njmp 13cd \nmov -0x4c(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x68(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x50(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x68(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njle 13c9 \nmov -0x40(%rbp),%rax\nmov -0x50(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%ecx\nmov -0x40(%rbp),%rax\nmov -0x4c(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\ncmp %eax,%ecx\njl 13c9 \nmov -0x40(%rbp),%rax\nmov -0x50(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nlea 0x1(%rax),%ecx\nmov -0x40(%rbp),%rax\nmov -0x4c(%rbp),%edx\nmovslq %edx,%rdx\nmov %ecx,(%rax,%rdx,4)\naddl $0x1,-0x50(%rbp)\nmov -0x50(%rbp),%eax\ncmp -0x4c(%rbp),%eax\njl 135e \naddl $0x1,-0x4c(%rbp)\nmov -0x4c(%rbp),%eax\ncmp -0x6c(%rbp),%eax\njl 1355 \nmovl $0x0,-0x4c(%rbp)\njmp 1403 \nmov -0x30(%rbp),%rax\nmov -0x4c(%rbp),%edx\nmovslq %edx,%rdx\nmovl $0x1,(%rax,%rdx,4)\naddl $0x1,-0x4c(%rbp)\nmov -0x4c(%rbp),%eax\ncmp -0x6c(%rbp),%eax\njle 13ee \nmov -0x6c(%rbp),%eax\nsub $0x2,%eax\nmov %eax,-0x4c(%rbp)\njmpq 149f \nmov -0x6c(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0x50(%rbp)\njmp 1493 \nmov -0x4c(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x68(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x50(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x68(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njle 148f \nmov -0x30(%rbp),%rax\nmov -0x50(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%ecx\nmov -0x30(%rbp),%rax\nmov -0x4c(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\ncmp %eax,%ecx\njl 148f \nmov -0x30(%rbp),%rax\nmov -0x50(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nlea 0x1(%rax),%ecx\nmov -0x30(%rbp),%rax\nmov -0x4c(%rbp),%edx\nmovslq %edx,%rdx\nmov %ecx,(%rax,%rdx,4)\nsubl $0x1,-0x50(%rbp)\nmov -0x50(%rbp),%eax\ncmp -0x4c(%rbp),%eax\njg 1424 \nsubl $0x1,-0x4c(%rbp)\ncmpl $0x0,-0x4c(%rbp)\njns 1419 \nmov -0x40(%rbp),%rax\nmov (%rax),%edx\nmov -0x30(%rbp),%rax\nmov (%rax),%eax\nadd %edx,%eax\nsub $0x1,%eax\nmov %eax,-0x54(%rbp)\nmovl $0x1,-0x4c(%rbp)\njmp 1510 \nmov -0x40(%rbp),%rax\nmov -0x4c(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%ecx\nmov -0x30(%rbp),%rax\nmov -0x4c(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nadd %ecx,%eax\nsub $0x1,%eax\ncmp %eax,-0x54(%rbp)\njge 150c \nmov -0x40(%rbp),%rax\nmov -0x4c(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%ecx\nmov -0x30(%rbp),%rax\nmov -0x4c(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nadd %ecx,%eax\nsub $0x1,%eax\nmov %eax,-0x54(%rbp)\naddl $0x1,-0x4c(%rbp)\nmov -0x4c(%rbp),%eax\ncmp -0x6c(%rbp),%eax\njl 14c6 \nmov -0x54(%rbp),%eax\nmov %rsi,%rsp\nmov -0x28(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 1532 \ncallq 1080 <__stack_chk_fail@plt>\nlea -0x18(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+var_48], rdi\nmov [rbp+var_4C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov eax, [rbp+var_4C]\nadd eax, 1\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_28], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11F9:\ncmp rsp, rdx\njz short loc_1210\nsub rsp, 1000h\nor [rsp+1050h+var_58], 0\njmp short loc_11F9\nloc_1210:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_123A\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_123A:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_20], rax\nmov eax, [rbp+var_4C]\nadd eax, 1\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_1295:\ncmp rsp, rdx\njz short loc_12AC\nsub rsp, 1000h\nor [rsp+1050h+var_58], 0\njmp short loc_1295\nloc_12AC:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_12D6\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_12D6:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov [rbp+var_34], 0\njmp short loc_1307\nloc_12F2:\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_34]\nmovsxd rdx, edx\nmov dword ptr [rax+rdx*4], 1\nadd [rbp+var_34], 1\nloc_1307:\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_4C]\njle short loc_12F2\nmov [rbp+var_34], 1\njmp loc_139F\nloc_131B:\nmov [rbp+var_30], 0\njmp short loc_1393\nloc_1324:\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_30]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_138F\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_30]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_34]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ncmp ecx, eax\njl short loc_138F\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_30]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nlea ecx, [rax+1]\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_34]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nloc_138F:\nadd [rbp+var_30], 1\nloc_1393:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_34]\njl short loc_1324\nadd [rbp+var_34], 1\nloc_139F:\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_4C]\njl loc_131B\nmov [rbp+var_34], 0\njmp short loc_13C9\nloc_13B4:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_34]\nmovsxd rdx, edx\nmov dword ptr [rax+rdx*4], 1\nadd [rbp+var_34], 1\nloc_13C9:\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_4C]\njle short loc_13B4\nmov eax, [rbp+var_4C]\nsub eax, 2\nmov [rbp+var_34], eax\njmp loc_1465\nloc_13DF:\nmov eax, [rbp+var_4C]\nsub eax, 1\nmov [rbp+var_30], eax\njmp short loc_1459\nloc_13EA:\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_30]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_1455\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_30]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_34]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ncmp ecx, eax\njl short loc_1455\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_30]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nlea ecx, [rax+1]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_34]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nloc_1455:\nsub [rbp+var_30], 1\nloc_1459:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_34]\njg short loc_13EA\nsub [rbp+var_34], 1\nloc_1465:\ncmp [rbp+var_34], 0\njns loc_13DF\nmov rax, [rbp+var_20]\nmov edx, [rax]\nmov rax, [rbp+var_10]\nmov eax, [rax]\nadd eax, edx\nsub eax, 1\nmov [rbp+var_2C], eax\nmov [rbp+var_34], 1\njmp short loc_14D6\nloc_148C:\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_34]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_34]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nadd eax, ecx\nsub eax, 1\ncmp [rbp+var_2C], eax\njge short loc_14D2\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_34]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_34]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nadd eax, ecx\nsub eax, 1\nmov [rbp+var_2C], eax\nloc_14D2:\nadd [rbp+var_34], 1\nloc_14D6:\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_4C]\njl short loc_148C\nmov eax, [rbp+var_2C]\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_14F8\ncall ___stack_chk_fail\nlocret_14F8:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned __int64 v2; // rax\n void *v3; // rsp\n unsigned __int64 v4; // rax\n void *v5; // rsp\n _BYTE v7[4]; // [rsp+8h] [rbp-50h] BYREF\n int v8; // [rsp+Ch] [rbp-4Ch]\n __int64 v9; // [rsp+10h] [rbp-48h]\n int i; // [rsp+24h] [rbp-34h]\n int j; // [rsp+28h] [rbp-30h]\n int v12; // [rsp+2Ch] [rbp-2Ch]\n __int64 v13; // [rsp+30h] [rbp-28h]\n _DWORD *v14; // [rsp+38h] [rbp-20h]\n __int64 v15; // [rsp+40h] [rbp-18h]\n _DWORD *v16; // [rsp+48h] [rbp-10h]\n unsigned __int64 v17; // [rsp+50h] [rbp-8h]\n\n v9 = a1;\n v8 = a2;\n v17 = __readfsqword(0x28u);\n v13 = a2 + 1 - 1LL;\n v2 = 16 * ((4LL * (a2 + 1) + 15) / 0x10uLL);\n while ( v7 != &v7[-(v2 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = alloca(v2 & 0xFFF);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)&v7[(v2 & 0xFFF) - 8] = *(_QWORD *)&v7[(v2 & 0xFFF) - 8];\n v14 = v7;\n v15 = v8 + 1 - 1LL;\n v4 = 16 * ((4LL * (v8 + 1) + 15) / 0x10uLL);\n while ( v7 != &v7[-(v4 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v5 = alloca(v4 & 0xFFF);\n if ( (v4 & 0xFFF) != 0 )\n *(_QWORD *)&v7[(v4 & 0xFFF) - 8] = *(_QWORD *)&v7[(v4 & 0xFFF) - 8];\n v16 = v7;\n for ( i = 0; i <= v8; ++i )\n v14[i] = 1;\n for ( i = 1; i < v8; ++i )\n {\n for ( j = 0; j < i; ++j )\n {\n if ( *(_DWORD *)(4LL * i + v9) > *(_DWORD *)(4LL * j + v9) && v14[j] >= v14[i] )\n v14[i] = v14[j] + 1;\n }\n }\n for ( i = 0; i <= v8; ++i )\n v16[i] = 1;\n for ( i = v8 - 2; i >= 0; --i )\n {\n for ( j = v8 - 1; j > i; --j )\n {\n if ( *(_DWORD *)(4LL * i + v9) > *(_DWORD *)(4LL * j + v9) && v16[j] >= v16[i] )\n v16[i] = v16[j] + 1;\n }\n }\n v12 = *v14 + *v16 - 1;\n for ( i = 1; i < v8; ++i )\n {\n if ( v12 < v14[i] + v16[i] - 1 )\n v12 = v14[i] + v16[i] - 1;\n }\n return (unsigned int)v12;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+var_48], rdi\nmov [rbp+var_4C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov eax, [rbp+var_4C]\nadd eax, 1\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_28], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11F9:\ncmp rsp, rdx\njz short loc_1210\nsub rsp, 1000h\nor [rsp+1050h+var_58], 0\njmp short loc_11F9\nloc_1210:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_123A\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_123A:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_20], rax\nmov eax, [rbp+var_4C]\nadd eax, 1\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_1295:\ncmp rsp, rdx\njz short loc_12AC\nsub rsp, 1000h\nor [rsp+1050h+var_58], 0\njmp short loc_1295\nloc_12AC:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_12D6\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_12D6:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov [rbp+var_34], 0\njmp short loc_1307\nloc_12F2:\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_34]\nmovsxd rdx, edx\nmov dword ptr [rax+rdx*4], 1\nadd [rbp+var_34], 1\nloc_1307:\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_4C]\njle short loc_12F2\nmov [rbp+var_34], 1\njmp loc_139F\nloc_131B:\nmov [rbp+var_30], 0\njmp short loc_1393\nloc_1324:\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_30]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_138F\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_30]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_34]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ncmp ecx, eax\njl short loc_138F\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_30]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nlea ecx, [rax+1]\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_34]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nloc_138F:\nadd [rbp+var_30], 1\nloc_1393:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_34]\njl short loc_1324\nadd [rbp+var_34], 1\nloc_139F:\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_4C]\njl loc_131B\nmov [rbp+var_34], 0\njmp short loc_13C9\nloc_13B4:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_34]\nmovsxd rdx, edx\nmov dword ptr [rax+rdx*4], 1\nadd [rbp+var_34], 1\nloc_13C9:\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_4C]\njle short loc_13B4\nmov eax, [rbp+var_4C]\nsub eax, 2\nmov [rbp+var_34], eax\njmp loc_1465\nloc_13DF:\nmov eax, [rbp+var_4C]\nsub eax, 1\nmov [rbp+var_30], eax\njmp short loc_1459\nloc_13EA:\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_30]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_1455\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_30]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_34]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ncmp ecx, eax\njl short loc_1455\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_30]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nlea ecx, [rax+1]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_34]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nloc_1455:\nsub [rbp+var_30], 1\nloc_1459:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_34]\njg short loc_13EA\nsub [rbp+var_34], 1\nloc_1465:\ncmp [rbp+var_34], 0\njns loc_13DF\nmov rax, [rbp+var_20]\nmov edx, [rax]\nmov rax, [rbp+var_10]\nmov eax, [rax]\nadd eax, edx\nsub eax, 1\nmov [rbp+var_2C], eax\nmov [rbp+var_34], 1\njmp short loc_14D6\nloc_148C:\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_34]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_34]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nadd eax, ecx\nsub eax, 1\ncmp [rbp+var_2C], eax\njge short loc_14D2\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_34]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_34]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nadd eax, ecx\nsub eax, 1\nmov [rbp+var_2C], eax\nloc_14D2:\nadd [rbp+var_34], 1\nloc_14D6:\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_4C]\njl short loc_148C\nmov eax, [rbp+var_2C]\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_14F8\ncall ___stack_chk_fail\nlocret_14F8:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2)\n{\n unsigned __int64 v2; // rax\n void *v3; // rsp\n unsigned __int64 v4; // rax\n void *v5; // rsp\n _BYTE v7[4]; // [rsp+8h] [rbp-50h] BYREF\n int v8; // [rsp+Ch] [rbp-4Ch]\n __int64 v9; // [rsp+10h] [rbp-48h]\n int i; // [rsp+24h] [rbp-34h]\n int j; // [rsp+28h] [rbp-30h]\n int v12; // [rsp+2Ch] [rbp-2Ch]\n __int64 v13; // [rsp+30h] [rbp-28h]\n _DWORD *v14; // [rsp+38h] [rbp-20h]\n __int64 v15; // [rsp+40h] [rbp-18h]\n _DWORD *v16; // [rsp+48h] [rbp-10h]\n unsigned __int64 v17; // [rsp+50h] [rbp-8h]\n\n v9 = a1;\n v8 = a2;\n v17 = __readfsqword(0x28u);\n v13 = a2 + 1 - 1LL;\n v2 = 16 * ((4LL * (a2 + 1) + 15) / 0x10uLL);\n while ( v7 != &v7[-(v2 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = alloca(v2 & 0xFFF);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)&v7[(v2 & 0xFFF) - 8] = *(_QWORD *)&v7[(v2 & 0xFFF) - 8];\n v14 = v7;\n v15 = v8 + 1 - 1LL;\n v4 = 16 * ((4LL * (v8 + 1) + 15) / 0x10uLL);\n while ( v7 != &v7[-(v4 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v5 = alloca(v4 & 0xFFF);\n if ( (v4 & 0xFFF) != 0 )\n *(_QWORD *)&v7[(v4 & 0xFFF) - 8] = *(_QWORD *)&v7[(v4 & 0xFFF) - 8];\n v16 = v7;\n for ( i = 0; i <= v8; ++i )\n v14[i] = 1;\n for ( i = 1; i < v8; ++i )\n {\n for ( j = 0; j < i; ++j )\n {\n if ( *(_DWORD *)(4LL * i + v9) > *(_DWORD *)(4LL * j + v9) && v14[j] >= v14[i] )\n v14[i] = v14[j] + 1;\n }\n }\n for ( i = 0; i <= v8; ++i )\n v16[i] = 1;\n for ( i = v8 - 2; i >= 0; --i )\n {\n for ( j = v8 - 1; j > i; --j )\n {\n if ( *(_DWORD *)(4LL * i + v9) > *(_DWORD *)(4LL * j + v9) && v16[j] >= v16[i] )\n v16[i] = v16[j] + 1;\n }\n }\n v12 = *v14 + *v16 - 1;\n for ( i = 1; i < v8; ++i )\n {\n if ( v12 < v14[i] + v16[i] - 1 )\n v12 = v14[i] + v16[i] - 1;\n }\n return (unsigned int)v12;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2) {\n unsigned long long v2;\n void *v3;\n unsigned long long v4;\n void *v5;\n uint8_t v7[4];\n int v8;\n long long v9;\n int i;\n int j;\n int v12;\n long long v13;\n uint32_t *v14;\n long long v15;\n uint32_t *v16;\n unsigned long long v17;\n v9 = a1;\n v8 = a2;\n v17 = __readfsqword(40u);\n v13 = a2 + 1 - 1LL;\n v2 = 16 * ((4LL * (a2 + 1) + 15) / 16uLL);\n while (v7 != &v7[-(v2 & 18446744073709547520LL)])\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)&v7[(v2 & 4095) - 8] = *(uint64_t *)&v7[(v2 & 4095) - 8];\n v14 = v7;\n v15 = v8 + 1 - 1LL;\n v4 = 16 * ((4LL * (v8 + 1) + 15) / 16uLL);\n while (v7 != &v7[-(v4 & 18446744073709547520LL)])\n ;\n v5 = alloca(v4 & 4095);\n if ((v4 & 4095) != 0)\n *(uint64_t *)&v7[(v4 & 4095) - 8] = *(uint64_t *)&v7[(v4 & 4095) - 8];\n v16 = v7;\n for (i = 0; i <= v8; ++i) v14[i] = 1;\n for (i = 1; i < v8; ++i) {\n for (j = 0; j < i; ++j) {\n if (*(uint32_t *)(4LL * i + v9) > *(uint32_t *)(4LL * j + v9) &&\n v14[j] >= v14[i])\n v14[i] = v14[j] + 1;\n }\n }\n for (i = 0; i <= v8; ++i) v16[i] = 1;\n for (i = v8 - 2; i >= 0; --i) {\n for (j = v8 - 1; j > i; --j) {\n if (*(uint32_t *)(4LL * i + v9) > *(uint32_t *)(4LL * j + v9) &&\n v16[j] >= v16[i])\n v16[i] = v16[j] + 1;\n }\n }\n v12 = *v14 + *v16 - 1;\n for (i = 1; i < v8; ++i) {\n if (v12 < v14[i] + v16[i] - 1) v12 = v14[i] + v16[i] - 1;\n }\n return (unsigned int)v12;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned long long v2;\n void *v3;\n unsigned long long v4;\n void *v5;\n uint8_t v7[4];\n int v8;\n long long v9;\n int i;\n int j;\n int v12;\n long long v13;\n uint32_t *v14;\n long long v15;\n uint32_t *v16;\n unsigned long long v17;\n v9 = a1;\n v8 = a2;\n v17 = __readfsqword(40u);\n v13 = a2 + 1 - 1LL;\n v2 = 16 * ((4LL * (a2 + 1) + 15) / 16uLL);\n while (v7 != &v7[-(v2 & 18446744073709547520LL)])\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)&v7[(v2 & 4095) - 8] = *(uint64_t *)&v7[(v2 & 4095) - 8];\n v14 = v7;\n v15 = v8 + 1 - 1LL;\n v4 = 16 * ((4LL * (v8 + 1) + 15) / 16uLL);\n while (v7 != &v7[-(v4 & 18446744073709547520LL)])\n ;\n v5 = alloca(v4 & 4095);\n if ((v4 & 4095) != 0)\n *(uint64_t *)&v7[(v4 & 4095) - 8] = *(uint64_t *)&v7[(v4 & 4095) - 8];\n v16 = v7;\n for (i = 0; i <= v8; ++i) v14[i] = 1;\n for (i = 1; i < v8; ++i) {\n for (j = 0; j < i; ++j) {\n if (*(uint32_t *)(4LL * i + v9) > *(uint32_t *)(4LL * j + v9) &&\n v14[j] >= v14[i])\n v14[i] = v14[j] + 1;\n }\n }\n for (i = 0; i <= v8; ++i) v16[i] = 1;\n for (i = v8 - 2; i >= 0; --i) {\n for (j = v8 - 1; j > i; --j) {\n if (*(uint32_t *)(4LL * i + v9) > *(uint32_t *)(4LL * j + v9) &&\n v16[j] >= v16[i])\n v16[i] = v16[j] + 1;\n }\n }\n v12 = *v14 + *v16 - 1;\n for (i = 1; i < v8; ++i) {\n if (v12 < v14[i] + v16[i] - 1) v12 = v14[i] + v16[i] - 1;\n }\n return (unsigned int)v12;\n}" + }, + { + "index": 522, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int lis[n + 1];\n int lds[n + 1];\n int i, j, maximum;\n for (i = 0; i <= n; i++) {\n lis[i] = 1;\n }\n for (i = 1; i < n; i++) {\n for (j = 0; j < i; j++) {\n if (arr[i] > arr[j] && lis[i] < lis[j] + 1) {\n lis[i] = lis[j] + 1;\n }\n }\n }\n for (i = 0; i <= n; i++) {\n lds[i] = 1;\n }\n for (i = n - 2; i >= 0; i--) {\n for (j = n - 1; j > i; j--) {\n if (arr[i] > arr[j] && lds[i] < lds[j] + 1) {\n lds[i] = lds[j] + 1;\n }\n }\n }\n maximum = lis[0] + lds[0] - 1;\n for (i = 1; i < n; i++) {\n if ((lis[i] + lds[i] - 1) > maximum) {\n maximum = lis[i] + lds[i] - 1;\n }\n }\n return maximum;\n}", + "test": "int main() {\n\n int arr1[] = {0, 8, 4, 12, 2, 10, 6, 14, 1, 9, 5, 13, 3, 11, 7, 15};\n\n int arr2[] = {1, 11, 2, 10, 4, 5, 2, 1};\n\n int arr3[] = {80, 60, 30, 40, 20, 10};\n\n\n\n assert(func0(arr1, sizeof(arr1)/sizeof(arr1[0])) == 7);\n\n assert(func0(arr2, sizeof(arr2)/sizeof(arr2[0])) == 6);\n\n assert(func0(arr3, sizeof(arr3)/sizeof(arr3[0])) == 5);\n\n \n\n printf(\"All tests passed.\\n\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r13\npush %r12\npush %rbx\nsub $0x18,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x28(%rbp)\nxor %eax,%eax\nlea 0x1(%rsi),%eax\ncltq\nshl $0x2,%rax\nlea 0xf(%rax),%rdx\nmov %rdx,%rcx\nand $0xfffffffffffffff0,%rcx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rbx\nsub %rdx,%rbx\nmov %rbx,%rdx\ncmp %rdx,%rsp\nje 11e4 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11cd \nmov %rcx,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\nje 11fb \norq $0x0,-0x8(%rsp,%rdx,1)\nlea 0x3(%rsp),%rdx\nmov %rdx,%r10\nshr $0x2,%r10\nand $0xfffffffffffffffc,%rdx\nmov %rdx,%r9\nadd $0xf,%rax\nmov %rax,%rcx\nand $0xfffffffffffffff0,%rcx\nand $0xfffffffffffff000,%rax\nmov %rsp,%rbx\nsub %rax,%rbx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 123f \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 1228 \nmov %rcx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 1255 \norq $0x0,-0x8(%rsp,%rax,1)\nlea 0x3(%rsp),%r8\nmov %r8,%r11\nshr $0x2,%r11\nand $0xfffffffffffffffc,%r8\ntest %esi,%esi\njs 12a1 \nmov %rdx,%rax\nmov %esi,%ecx\nlea 0x4(%rdx,%rcx,4),%rdx\nmovl $0x1,(%rax)\nadd $0x4,%rax\ncmp %rdx,%rax\njne 1273 \nmov $0x1,%edx\ncmp $0x1,%esi\njg 12da \nmov $0x0,%eax\nmovl $0x1,(%r8,%rax,4)\nadd $0x1,%rax\ncmp %eax,%esi\njge 1291 \nmov %esi,%ecx\nsub $0x2,%ecx\njs 1321 \nmovslq %ecx,%rcx\nlea -0x1(%rsi),%r13d\njmp 1311 \nadd $0x1,%rax\ncmp %rdx,%rax\nje 12d2 \ncmp (%rdi,%rax,4),%ebx\njle 12b1 \nmov (%r9,%rax,4),%ecx\ncmp (%r9,%rdx,4),%ecx\njl 12b1 \nadd $0x1,%ecx\nmov %ecx,(%r9,%rdx,4)\njmp 12b1 \nadd $0x1,%rdx\ncmp %edx,%esi\njle 128c \ntest %edx,%edx\njle 12d2 \nmov (%rdi,%rdx,4),%ebx\nmov $0x0,%eax\njmp 12ba \nsub $0x1,%rax\ncmp %eax,%ebx\njge 1309 \ncmp (%rdi,%rax,4),%r12d\njle 12e8 \nmov (%r8,%rax,4),%edx\ncmp (%r8,%rcx,4),%edx\njl 12e8 \nadd $0x1,%edx\nmov %edx,(%r8,%rcx,4)\njmp 12e8 \nsub $0x1,%rcx\ntest %ecx,%ecx\njs 1321 \nmov %ecx,%ebx\ncmp %r13d,%ecx\njge 1309 \nmov (%rdi,%rcx,4),%r12d\nmovslq %r13d,%rax\njmp 12f0 \nmov 0x0(,%r11,4),%ecx\nadd 0x0(,%r10,4),%ecx\nsub $0x1,%ecx\ncmp $0x1,%esi\njle 135e \nlea -0x2(%rsi),%esi\nadd $0x2,%rsi\nmov $0x1,%edx\nmov (%r8,%rdx,4),%eax\nadd (%r9,%rdx,4),%eax\nsub $0x1,%eax\ncmp %eax,%ecx\ncmovl %eax,%ecx\nadd $0x1,%rdx\ncmp %rdx,%rsi\njne 1345 \nmov -0x28(%rbp),%rax\nxor %fs:0x28,%rax\njne 137a \nmov %ecx,%eax\nlea -0x18(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %rbp\nretq\ncallq 1080 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r13\npush r12\npush rbx\nsub rsp, 18h\nmov rdx, rdi\nmov r9d, esi\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nlea eax, [rsi+1]\ncdqe\nshl rax, 2\nlea rcx, [rax+0Fh]\nmov rdi, rcx\nand rdi, 0FFFFFFFFFFFFFFF0h\nand rcx, 0FFFFFFFFFFFFF000h\nmov rsi, rsp\nsub rsi, rcx\nloc_11D0:\ncmp rsp, rsi\njz short loc_11E7\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\njmp short loc_11D0\nloc_11E7:\nmov rcx, rdi\nand ecx, 0FFFh\nsub rsp, rcx\ntest rcx, rcx\njz short loc_11FE\nor [rsp+rcx+30h+var_38], 0\nloc_11FE:\nlea rdi, [rsp+30h+var_2D]\nmov r10, rdi\nshr r10, 2\nand rdi, 0FFFFFFFFFFFFFFFCh\nadd rax, 0Fh\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rsi, rsp\nsub rsi, rax\nloc_1225:\ncmp rsp, rsi\njz short loc_123C\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\njmp short loc_1225\nloc_123C:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_1252\nor [rsp+rax+30h+var_38], 0\nloc_1252:\nlea r8, [rsp+30h+var_2D]\nmov r11, r8\nshr r11, 2\nand r8, 0FFFFFFFFFFFFFFFCh\ntest r9d, r9d\njs loc_1366\nmov rax, rdi\nlea ecx, [r9+1]\nlea rcx, [rdi+rcx*4]\nloc_1276:\nmov dword ptr [rax], 1\nadd rax, 4\ncmp rax, rcx\njnz short loc_1276\ncmp r9d, 1\njle loc_137B\nmov ecx, 4\nmov r12d, 1\njmp short loc_12CB\nloc_129C:\nadd rax, 4\ncmp rax, rcx\njz short loc_12BA\nloc_12A5:\ncmp ebx, [rdx+rax]\njle short loc_129C\nmov esi, [rdi+rax]\ncmp esi, [rdi+rcx]\njl short loc_129C\nadd esi, 1\nmov [rdi+rcx], esi\njmp short loc_129C\nloc_12BA:\nadd r12d, 1\nadd rcx, 4\ncmp r9d, r12d\njz loc_137B\nloc_12CB:\ntest r12d, r12d\njle loc_13A9\nmov ebx, [rdx+rcx]\nmov eax, 0\njmp short loc_12A5\nloc_12DE:\nsub rax, 1\ncmp ebx, eax\njge short loc_12FF\nloc_12E6:\ncmp r12d, [rdx+rax*4]\njle short loc_12DE\nmov ecx, [r8+rax*4]\ncmp ecx, [r8+rsi*4]\njl short loc_12DE\nadd ecx, 1\nmov [r8+rsi*4], ecx\njmp short loc_12DE\nloc_12FF:\nsub rsi, 1\ntest esi, esi\njs short loc_1317\nloc_1307:\nmov ebx, esi\ncmp r13d, esi\njle short loc_12FF\nmov r12d, [rdx+rsi*4]\nmovsxd rax, r13d\njmp short loc_12E6\nloc_1317:\nmov ecx, ds:dword_0[r11*4]\nadd ecx, ds:dword_0[r10*4]\nsub ecx, 1\nmov r9d, r9d\nmov edx, 1\nloc_1332:\nmov eax, [r8+rdx*4]\nadd eax, [rdi+rdx*4]\nsub eax, 1\ncmp ecx, eax\ncmovl ecx, eax\nadd rdx, 1\ncmp r9, rdx\njnz short loc_1332\nloc_134A:\nmov rax, [rbp+var_28]\nsub rax, fs:28h\njnz short loc_13B6\nmov eax, ecx\nlea rsp, [rbp-18h]\npop rbx\npop r12\npop r13\npop rbp\nretn\nloc_1366:\nmov ecx, ds:dword_0[r10*4]\nadd ecx, ds:dword_0[r11*4]\nsub ecx, 1\njmp short loc_134A\nloc_137B:\nmov rax, r8\nlea ecx, [r9+1]\nlea rcx, [r8+rcx*4]\nloc_1386:\nmov dword ptr [rax], 1\nadd rax, 4\ncmp rax, rcx\njnz short loc_1386\nmov esi, r9d\nsub esi, 2\njs short loc_1366\nmovsxd rsi, esi\nlea r13d, [r9-1]\njmp loc_1307\nloc_13A9:\nadd r12d, 1\nadd rcx, 4\njmp loc_12CB\nloc_13B6:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v3; // rax\n signed __int64 v4; // rcx\n void *v5; // rsp\n __int64 v6; // rax\n __int16 v7; // cx\n signed __int64 v8; // rax\n void *v9; // rsp\n _DWORD *v10; // rax\n unsigned __int64 v11; // rcx\n int i; // r12d\n unsigned __int64 v13; // rax\n int v14; // esi\n int v15; // ebx\n __int64 v16; // rax\n int v17; // ecx\n __int64 v18; // rsi\n int v19; // r12d\n int v20; // ecx\n __int64 j; // rdx\n _DWORD *v23; // rax\n int v24; // r13d\n _DWORD v26[2]; // [rsp+8h] [rbp-30h] BYREF\n unsigned __int64 v27; // [rsp+10h] [rbp-28h]\n\n v27 = __readfsqword(0x28u);\n v3 = 4LL * (a2 + 1);\n while ( v26 != (_DWORD *)((char *)v26 - ((v3 + 15) & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v4 = ((_WORD)v3 + 15) & 0xFF0;\n v5 = alloca(v4);\n if ( (((_WORD)v3 + 15) & 0xFF0) != 0 )\n *(_QWORD *)((char *)&v26[-2] + v4) = *(_QWORD *)((char *)&v26[-2] + v4);\n v6 = v3 + 15;\n v7 = v6 & 0xFFF0;\n while ( v26 != (_DWORD *)((char *)v26 - (v6 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v8 = v6 & 0xFF0;\n v9 = alloca(v8);\n if ( (v7 & 0xFFF) != 0 )\n *(_QWORD *)((char *)&v26[-2] + v8) = *(_QWORD *)((char *)&v26[-2] + v8);\n if ( a2 < 0 )\n return (unsigned int)(2 * v26[0] - 1);\n v10 = v26;\n do\n *v10++ = 1;\n while ( v10 != &v26[a2 + 1] );\n if ( a2 > 1 )\n {\n v11 = 4LL;\n for ( i = 1; i != a2; ++i )\n {\n while ( i <= 0 )\n {\n ++i;\n v11 += 4LL;\n }\n v15 = *(_DWORD *)(a1 + v11);\n v13 = 0LL;\n do\n {\n if ( v15 > *(_DWORD *)(a1 + v13) )\n {\n v14 = v26[v13 / 4];\n if ( v14 >= v26[v11 / 4] )\n v26[v11 / 4] = v14 + 1;\n }\n v13 += 4LL;\n }\n while ( v13 != v11 );\n v11 += 4LL;\n }\n }\n v23 = v26;\n do\n *v23++ = 1;\n while ( v23 != &v26[a2 + 1] );\n LODWORD(v18) = a2 - 2;\n if ( a2 - 2 < 0 )\n {\n return (unsigned int)(2 * v26[0] - 1);\n }\n else\n {\n v18 = (int)v18;\n v24 = a2 - 1;\n do\n {\n if ( v24 > (int)v18 )\n {\n v19 = *(_DWORD *)(a1 + 4 * v18);\n v16 = v24;\n do\n {\n if ( v19 > *(_DWORD *)(a1 + 4 * v16) )\n {\n v17 = v26[v16];\n if ( v17 >= v26[v18] )\n v26[v18] = v17 + 1;\n }\n --v16;\n }\n while ( (int)v18 < (int)v16 );\n }\n --v18;\n }\n while ( (int)v18 >= 0 );\n v20 = 2 * v26[0] - 1;\n for ( j = 1LL; j != a2; ++j )\n {\n if ( v20 < 2 * v26[j] - 1 )\n v20 = 2 * v26[j] - 1;\n }\n }\n return (unsigned int)v20;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\npush r13\npush r12\npush rbx\nsub rsp, 18h\nmov rdx, rdi\nmov r9d, esi\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nlea eax, [rsi+1]\ncdqe\nshl rax, 2\nlea rcx, [rax+0Fh]\nmov rdi, rcx\nand rdi, 0FFFFFFFFFFFFFFF0h\nand rcx, 0FFFFFFFFFFFFF000h\nmov rsi, rsp\nsub rsi, rcx\nloc_11D0:\ncmp rsp, rsi\njz short loc_11E7\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\njmp short loc_11D0\nloc_11E7:\nmov rcx, rdi\nand ecx, 0FFFh\nsub rsp, rcx\ntest rcx, rcx\njz short loc_11FE\nor [rsp+rcx+30h+var_38], 0\nloc_11FE:\nlea rdi, [rsp+30h+var_2D]\nmov r10, rdi\nshr r10, 2\nand rdi, 0FFFFFFFFFFFFFFFCh\nadd rax, 0Fh\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rsi, rsp\nsub rsi, rax\nloc_1225:\ncmp rsp, rsi\njz short loc_123C\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\njmp short loc_1225\nloc_123C:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_1252\nor [rsp+rax+30h+var_38], 0\nloc_1252:\nlea r8, [rsp+30h+var_2D]\nmov r11, r8\nshr r11, 2\nand r8, 0FFFFFFFFFFFFFFFCh\ntest r9d, r9d\njs loc_1366\nmov rax, rdi\nlea ecx, [r9+1]\nlea rcx, [rdi+rcx*4]\nloc_1276:\nmov dword ptr [rax], 1\nadd rax, 4\ncmp rax, rcx\njnz short loc_1276\ncmp r9d, 1\njle loc_137B\nmov ecx, 4\nmov r12d, 1\njmp short loc_12CB\nloc_129C:\nadd rax, 4\ncmp rax, rcx\njz short loc_12BA\nloc_12A5:\ncmp ebx, [rdx+rax]\njle short loc_129C\nmov esi, [rdi+rax]\ncmp esi, [rdi+rcx]\njl short loc_129C\nadd esi, 1\nmov [rdi+rcx], esi\njmp short loc_129C\nloc_12BA:\nadd r12d, 1\nadd rcx, 4\ncmp r9d, r12d\njz loc_137B\nloc_12CB:\ntest r12d, r12d\njle loc_13A9\nmov ebx, [rdx+rcx]\nmov eax, 0\njmp short loc_12A5\nloc_12DE:\nsub rax, 1\ncmp ebx, eax\njge short loc_12FF\nloc_12E6:\ncmp r12d, [rdx+rax*4]\njle short loc_12DE\nmov ecx, [r8+rax*4]\ncmp ecx, [r8+rsi*4]\njl short loc_12DE\nadd ecx, 1\nmov [r8+rsi*4], ecx\njmp short loc_12DE\nloc_12FF:\nsub rsi, 1\ntest esi, esi\njs short loc_1317\nloc_1307:\nmov ebx, esi\ncmp r13d, esi\njle short loc_12FF\nmov r12d, [rdx+rsi*4]\nmovsxd rax, r13d\njmp short loc_12E6\nloc_1317:\nmov ecx, ds:dword_0[r11*4]\nadd ecx, ds:dword_0[r10*4]\nsub ecx, 1\nmov r9d, r9d\nmov edx, 1\nloc_1332:\nmov eax, [r8+rdx*4]\nadd eax, [rdi+rdx*4]\nsub eax, 1\ncmp ecx, eax\ncmovl ecx, eax\nadd rdx, 1\ncmp r9, rdx\njnz short loc_1332\nloc_134A:\nmov rax, [rbp+var_28]\nsub rax, fs:28h\njnz short loc_13B6\nmov eax, ecx\nlea rsp, [rbp-18h]\npop rbx\npop r12\npop r13\npop rbp\nretn\nloc_1366:\nmov ecx, ds:dword_0[r10*4]\nadd ecx, ds:dword_0[r11*4]\nsub ecx, 1\njmp short loc_134A\nloc_137B:\nmov rax, r8\nlea ecx, [r9+1]\nlea rcx, [r8+rcx*4]\nloc_1386:\nmov dword ptr [rax], 1\nadd rax, 4\ncmp rax, rcx\njnz short loc_1386\nmov esi, r9d\nsub esi, 2\njs short loc_1366\nmovsxd rsi, esi\nlea r13d, [r9-1]\njmp loc_1307\nloc_13A9:\nadd r12d, 1\nadd rcx, 4\njmp loc_12CB\nloc_13B6:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2)\n{\n __int64 v3; // rax\n signed __int64 v4; // rcx\n void *v5; // rsp\n __int64 v6; // rax\n __int16 v7; // cx\n signed __int64 v8; // rax\n void *v9; // rsp\n _DWORD *v10; // rax\n unsigned __int64 v11; // rcx\n int i; // r12d\n unsigned __int64 v13; // rax\n int v14; // esi\n int v15; // ebx\n __int64 v16; // rax\n int v17; // ecx\n __int64 v18; // rsi\n int v19; // r12d\n int v20; // ecx\n __int64 j; // rdx\n _DWORD *v23; // rax\n int v24; // r13d\n _DWORD v26[2]; // [rsp+8h] [rbp-30h] BYREF\n unsigned __int64 v27; // [rsp+10h] [rbp-28h]\n\n v27 = __readfsqword(0x28u);\n v3 = 4LL * (a2 + 1);\n while ( v26 != (_DWORD *)((char *)v26 - ((v3 + 15) & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v4 = ((_WORD)v3 + 15) & 0xFF0;\n v5 = alloca(v4);\n if ( (((_WORD)v3 + 15) & 0xFF0) != 0 )\n *(_QWORD *)((char *)&v26[-2] + v4) = *(_QWORD *)((char *)&v26[-2] + v4);\n v6 = v3 + 15;\n v7 = v6 & 0xFFF0;\n while ( v26 != (_DWORD *)((char *)v26 - (v6 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v8 = v6 & 0xFF0;\n v9 = alloca(v8);\n if ( (v7 & 0xFFF) != 0 )\n *(_QWORD *)((char *)&v26[-2] + v8) = *(_QWORD *)((char *)&v26[-2] + v8);\n if ( a2 < 0 )\n return (unsigned int)(2 * v26[0] - 1);\n v10 = v26;\n do\n *v10++ = 1;\n while ( v10 != &v26[a2 + 1] );\n if ( a2 > 1 )\n {\n v11 = 4LL;\n for ( i = 1; i != a2; ++i )\n {\n while ( i <= 0 )\n {\n ++i;\n v11 += 4LL;\n }\n v15 = *(_DWORD *)(a1 + v11);\n v13 = 0LL;\n do\n {\n if ( v15 > *(_DWORD *)(a1 + v13) )\n {\n v14 = v26[v13 / 4];\n if ( v14 >= v26[v11 / 4] )\n v26[v11 / 4] = v14 + 1;\n }\n v13 += 4LL;\n }\n while ( v13 != v11 );\n v11 += 4LL;\n }\n }\n v23 = v26;\n do\n *v23++ = 1;\n while ( v23 != &v26[a2 + 1] );\n LODWORD(v18) = a2 - 2;\n if ( a2 - 2 < 0 )\n {\n return (unsigned int)(2 * v26[0] - 1);\n }\n else\n {\n v18 = (int)v18;\n v24 = a2 - 1;\n do\n {\n if ( v24 > (int)v18 )\n {\n v19 = *(_DWORD *)(a1 + 4 * v18);\n v16 = v24;\n do\n {\n if ( v19 > *(_DWORD *)(a1 + 4 * v16) )\n {\n v17 = v26[v16];\n if ( v17 >= v26[v18] )\n v26[v18] = v17 + 1;\n }\n --v16;\n }\n while ( (int)v18 < (int)v16 );\n }\n --v18;\n }\n while ( (int)v18 >= 0 );\n v20 = 2 * v26[0] - 1;\n for ( j = 1LL; j != a2; ++j )\n {\n if ( v20 < 2 * v26[j] - 1 )\n v20 = 2 * v26[j] - 1;\n }\n }\n return (unsigned int)v20;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2) {\n long long v3;\n signed long long v4;\n void *v5;\n long long v6;\n short v7;\n signed long long v8;\n void *v9;\n uint32_t *v10;\n unsigned long long v11;\n int i;\n unsigned long long v13;\n int v14;\n int v15;\n long long v16;\n int v17;\n long long v18;\n int v19;\n int v20;\n long long j;\n uint32_t *v23;\n int v24;\n uint32_t v26[2];\n unsigned long long v27;\n v27 = __readfsqword(40u);\n v3 = 4LL * (a2 + 1);\n while (v26 !=\n (uint32_t *)((char *)v26 - ((v3 + 15) & 18446744073709547520LL)))\n ;\n v4 = ((unsigned short)v3 + 15) & 4080;\n v5 = alloca(v4);\n if ((((unsigned short)v3 + 15) & 4080) != 0)\n *(uint64_t *)((char *)&v26[-2] + v4) = *(uint64_t *)((char *)&v26[-2] + v4);\n v6 = v3 + 15;\n v7 = v6 & 65520;\n while (v26 != (uint32_t *)((char *)v26 - (v6 & 18446744073709547520LL)))\n ;\n v8 = v6 & 4080;\n v9 = alloca(v8);\n if ((v7 & 4095) != 0)\n *(uint64_t *)((char *)&v26[-2] + v8) = *(uint64_t *)((char *)&v26[-2] + v8);\n if (a2 < 0) return (unsigned int)(2 * v26[0] - 1);\n v10 = v26;\n do\n *v10++ = 1;\n while (v10 != &v26[a2 + 1]);\n if (a2 > 1) {\n v11 = 4LL;\n for (i = 1; i != a2; ++i) {\n while (i <= 0) {\n ++i;\n v11 += 4LL;\n }\n v15 = *(uint32_t *)(a1 + v11);\n v13 = 0LL;\n do {\n if (v15 > *(uint32_t *)(a1 + v13)) {\n v14 = v26[v13 / 4];\n if (v14 >= v26[v11 / 4]) v26[v11 / 4] = v14 + 1;\n }\n v13 += 4LL;\n } while (v13 != v11);\n v11 += 4LL;\n }\n }\n v23 = v26;\n do\n *v23++ = 1;\n while (v23 != &v26[a2 + 1]);\n LODWORD(v18) = a2 - 2;\n if (a2 - 2 < 0) {\n return (unsigned int)(2 * v26[0] - 1);\n } else {\n v18 = (int)v18;\n v24 = a2 - 1;\n do {\n if (v24 > (int)v18) {\n v19 = *(uint32_t *)(a1 + 4 * v18);\n v16 = v24;\n do {\n if (v19 > *(uint32_t *)(a1 + 4 * v16)) {\n v17 = v26[v16];\n if (v17 >= v26[v18]) v26[v18] = v17 + 1;\n }\n --v16;\n } while ((int)v18 < (int)v16);\n }\n --v18;\n } while ((int)v18 >= 0);\n v20 = 2 * v26[0] - 1;\n for (j = 1LL; j != a2; ++j) {\n if (v20 < 2 * v26[j] - 1) v20 = 2 * v26[j] - 1;\n }\n }\n return (unsigned int)v20;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v3;\n signed long long v4;\n void *v5;\n long long v6;\n short v7;\n signed long long v8;\n void *v9;\n uint32_t *v10;\n unsigned long long v11;\n int i;\n unsigned long long v13;\n int v14;\n int v15;\n long long v16;\n int v17;\n long long v18;\n int v19;\n int v20;\n long long j;\n uint32_t *v23;\n int v24;\n uint32_t v26[2];\n unsigned long long v27;\n v27 = __readfsqword(40u);\n v3 = 4LL * (a2 + 1);\n while (v26 !=\n (uint32_t *)((char *)v26 - ((v3 + 15) & 18446744073709547520LL)))\n ;\n v4 = ((unsigned short)v3 + 15) & 4080;\n v5 = alloca(v4);\n if ((((unsigned short)v3 + 15) & 4080) != 0)\n *(uint64_t *)((char *)&v26[-2] + v4) = *(uint64_t *)((char *)&v26[-2] + v4);\n v6 = v3 + 15;\n v7 = v6 & 65520;\n while (v26 != (uint32_t *)((char *)v26 - (v6 & 18446744073709547520LL)))\n ;\n v8 = v6 & 4080;\n v9 = alloca(v8);\n if ((v7 & 4095) != 0)\n *(uint64_t *)((char *)&v26[-2] + v8) = *(uint64_t *)((char *)&v26[-2] + v8);\n if (a2 < 0) return (unsigned int)(2 * v26[0] - 1);\n v10 = v26;\n do\n *v10++ = 1;\n while (v10 != &v26[a2 + 1]);\n if (a2 > 1) {\n v11 = 4LL;\n for (i = 1; i != a2; ++i) {\n while (i <= 0) {\n ++i;\n v11 += 4LL;\n }\n v15 = *(uint32_t *)(a1 + v11);\n v13 = 0LL;\n do {\n if (v15 > *(uint32_t *)(a1 + v13)) {\n v14 = v26[v13 / 4];\n if (v14 >= v26[v11 / 4]) v26[v11 / 4] = v14 + 1;\n }\n v13 += 4LL;\n } while (v13 != v11);\n v11 += 4LL;\n }\n }\n v23 = v26;\n do\n *v23++ = 1;\n while (v23 != &v26[a2 + 1]);\n LODWORD(v18) = a2 - 2;\n if (a2 - 2 < 0) {\n return (unsigned int)(2 * v26[0] - 1);\n } else {\n v18 = (int)v18;\n v24 = a2 - 1;\n do {\n if (v24 > (int)v18) {\n v19 = *(uint32_t *)(a1 + 4 * v18);\n v16 = v24;\n do {\n if (v19 > *(uint32_t *)(a1 + 4 * v16)) {\n v17 = v26[v16];\n if (v17 >= v26[v18]) v26[v18] = v17 + 1;\n }\n --v16;\n } while ((int)v18 < (int)v16);\n }\n --v18;\n } while ((int)v18 >= 0);\n v20 = 2 * v26[0] - 1;\n for (j = 1LL; j != a2; ++j) {\n if (v20 < 2 * v26[j] - 1) v20 = 2 * v26[j] - 1;\n }\n }\n return (unsigned int)v20;\n}" + }, + { + "index": 522, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int lis[n + 1];\n int lds[n + 1];\n int i, j, maximum;\n for (i = 0; i <= n; i++) {\n lis[i] = 1;\n }\n for (i = 1; i < n; i++) {\n for (j = 0; j < i; j++) {\n if (arr[i] > arr[j] && lis[i] < lis[j] + 1) {\n lis[i] = lis[j] + 1;\n }\n }\n }\n for (i = 0; i <= n; i++) {\n lds[i] = 1;\n }\n for (i = n - 2; i >= 0; i--) {\n for (j = n - 1; j > i; j--) {\n if (arr[i] > arr[j] && lds[i] < lds[j] + 1) {\n lds[i] = lds[j] + 1;\n }\n }\n }\n maximum = lis[0] + lds[0] - 1;\n for (i = 1; i < n; i++) {\n if ((lis[i] + lds[i] - 1) > maximum) {\n maximum = lis[i] + lds[i] - 1;\n }\n }\n return maximum;\n}", + "test": "int main() {\n\n int arr1[] = {0, 8, 4, 12, 2, 10, 6, 14, 1, 9, 5, 13, 3, 11, 7, 15};\n\n int arr2[] = {1, 11, 2, 10, 4, 5, 2, 1};\n\n int arr3[] = {80, 60, 30, 40, 20, 10};\n\n\n\n assert(func0(arr1, sizeof(arr1)/sizeof(arr1[0])) == 7);\n\n assert(func0(arr2, sizeof(arr2)/sizeof(arr2[0])) == 6);\n\n assert(func0(arr3, sizeof(arr3)/sizeof(arr3[0])) == 5);\n\n \n\n printf(\"All tests passed.\\n\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x28(%rbp)\nxor %eax,%eax\nlea 0x1(%rsi),%eax\nmov %rsp,%rbx\ncltq\nlea 0xf(,%rax,4),%rax\nmov %rax,%rcx\nmov %rax,%rdx\nand $0xfffffffffffff000,%rcx\nand $0xfffffffffffffff0,%rdx\nsub %rcx,%rbx\nmov %rbx,%rcx\ncmp %rcx,%rsp\nje 13b3 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rcx,%rsp\njne 139e \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 155a \nmov %rax,%rdx\nmov %rsp,%rbx\nand $0xfffffffffffff000,%rax\nlea 0x3(%rsp),%r9\nsub %rax,%rbx\nand $0xfffffffffffffff0,%rdx\nmov %r9,%r10\nmov %rbx,%rax\nand $0xfffffffffffffffc,%r9\nshr $0x2,%r10\ncmp %rax,%rsp\nje 1405 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 13f0 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 1565 \nlea 0x3(%rsp),%r8\nmov %r8,%r11\nand $0xfffffffffffffffc,%r8\nshr $0x2,%r11\ntest %esi,%esi\njs 14a8 \nmovslq %esi,%rdx\nmov %r9,%rax\nlea 0x4(%r9,%rdx,4),%rdx\nnopw %cs:0x0(%rax,%rax,1)\nmovl $0x1,(%rax)\nadd $0x4,%rax\ncmp %rdx,%rax\njne 1440 \ncmp $0x1,%esi\njle 148f \nmov $0x1,%edx\nnopl 0x0(%rax)\nmov (%rdi,%rdx,4),%ebx\nxor %eax,%eax\nnopl (%rax)\ncmp (%rdi,%rax,4),%ebx\njle 147e \nmov (%r9,%rax,4),%ecx\ncmp (%r9,%rdx,4),%ecx\njl 147e \nadd $0x1,%ecx\nmov %ecx,(%r9,%rdx,4)\nadd $0x1,%rax\ncmp %rax,%rdx\njne 1468 \nadd $0x1,%rdx\ncmp %edx,%esi\njg 1460 \nxor %eax,%eax\nnopl 0x0(%rax)\nmovl $0x1,(%r8,%rax,4)\nadd $0x1,%rax\ncmp %eax,%esi\njge 1498 \nlea -0x2(%rsi),%r13d\nlea -0x1(%rsi),%r14d\nmovslq %r13d,%rcx\ntest %r13d,%r13d\njs 14f7 \nnopl 0x0(%rax,%rax,1)\nmov %ecx,%ebx\ncmp %r14d,%ecx\njge 14ef \nmov (%rdi,%rcx,4),%r12d\nmovslq %r14d,%rax\nxchg %ax,%ax\ncmp (%rdi,%rax,4),%r12d\njle 14e7 \nmov (%r8,%rax,4),%edx\ncmp (%r8,%rcx,4),%edx\njl 14e7 \nadd $0x1,%edx\nmov %edx,(%r8,%rcx,4)\nsub $0x1,%rax\ncmp %eax,%ebx\njl 14d0 \nsub $0x1,%rcx\ntest %ecx,%ecx\njns 14c0 \nmov 0x0(,%r11,4),%eax\nmov %r13d,%ecx\nadd 0x0(,%r10,4),%eax\nmov $0x1,%edx\nmov %eax,%r10d\nadd $0x2,%rcx\nsub $0x1,%r10d\ncmp $0x1,%esi\njle 153b \nmov (%r8,%rdx,4),%eax\nadd (%r9,%rdx,4),%eax\nsub $0x1,%eax\ncmp %eax,%r10d\ncmovl %eax,%r10d\nadd $0x1,%rdx\ncmp %rcx,%rdx\njne 1520 \nmov -0x28(%rbp),%rax\nxor %fs:0x28,%rax\njne 1570 \nlea -0x20(%rbp),%rsp\nmov %r10d,%eax\npop %rbx\npop %r12\npop %r13\npop %r14\npop %rbp\nretq\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 13c5 \norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 1417 \ncallq 1080 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rdx, rdi\nmov r9d, esi\nmov rbp, rsp\npush r13\npush r12\npush rbx\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nlea eax, [rsi+1]\nmov rsi, rsp\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rdi, rax\nmov rcx, rax\nand rdi, 0FFFFFFFFFFFFF000h\nand rcx, 0FFFFFFFFFFFFFFF0h\nsub rsi, rdi\ncmp rsp, rsi\njz short loc_1344\nloc_132F:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rsi\njnz short loc_132F\nloc_1344:\nand ecx, 0FFFh\nsub rsp, rcx\ntest rcx, rcx\njnz loc_1524\nloc_1356:\nlea rdi, [rsp+1030h+var_102D]\nmov rcx, rax\nmov rsi, rsp\nand rax, 0FFFFFFFFFFFFF000h\nmov r12, rdi\nsub rsi, rax\nand rdi, 0FFFFFFFFFFFFFFFCh\nand rcx, 0FFFFFFFFFFFFFFF0h\nshr r12, 2\ncmp rsp, rsi\njz short loc_1393\nloc_137E:\nsub rsp, 1000h\nor [rsp+2030h+var_1038], 0\ncmp rsp, rsi\njnz short loc_137E\nloc_1393:\nand ecx, 0FFFh\nsub rsp, rcx\ntest rcx, rcx\njnz loc_1544\nloc_13A5:\nlea r8, [rsp+2030h+var_202D]\nmov r10, r8\nand r8, 0FFFFFFFFFFFFFFFCh\nshr r10, 2\ntest r9d, r9d\njs loc_152F\nmovsxd rcx, r9d\nmov rax, rdi\nlea rbx, ds:4[rcx*4]\nlea rcx, [rdi+rbx]\ntest bl, 4\njz short loc_13E8\nlea rax, [rdi+4]\nmov dword ptr [rdi], 1\ncmp rax, rcx\njz short loc_13FE\nnop dword ptr [rax+00h]\nloc_13E8:\nmov dword ptr [rax], 1\nadd rax, 8\nmov dword ptr [rax-4], 1\ncmp rax, rcx\njnz short loc_13E8\nloc_13FE:\ncmp r9d, 1\njle short loc_1446\nmov r13d, r9d\nmov ecx, 4\nshl r13, 2\nloc_1410:\nmov r11d, [rdx+rcx]\nxor eax, eax\nnop word ptr [rax+rax+00000000h]\nloc_1420:\ncmp r11d, [rdx+rax]\njle short loc_1434\nmov esi, [rdi+rax]\ncmp esi, [rdi+rcx]\njl short loc_1434\nadd esi, 1\nmov [rdi+rcx], esi\nloc_1434:\nadd rax, 4\ncmp rax, rcx\njnz short loc_1420\nadd rcx, 4\ncmp rcx, r13\njnz short loc_1410\nloc_1446:\nlea rcx, [r8+rbx]\nand ebx, 4\nmov rax, r8\njz short loc_1468\nlea rax, [r8+4]\nmov dword ptr [r8], 1\ncmp rax, rcx\njz short loc_147E\nnop word ptr [rax+rax+00h]\nloc_1468:\nmov dword ptr [rax], 1\nadd rax, 8\nmov dword ptr [rax-4], 1\ncmp rax, rcx\njnz short loc_1468\nloc_147E:\nmov esi, r9d\nmov r12d, ds:dword_0[r12*4]\nsub esi, 2\njs loc_154F\nlea r13d, [r9-1]\nmovsxd rsi, esi\nnop dword ptr [rax+00000000h]\nloc_14A0:\nmov r11d, esi\ncmp esi, r13d\njge short loc_14CF\nmov ebx, [rdx+rsi*4]\nmovsxd rax, r13d\nxchg ax, ax\nloc_14B0:\ncmp ebx, [rdx+rax*4]\njle short loc_14C6\nmov ecx, [r8+rax*4]\ncmp ecx, [r8+rsi*4]\njl short loc_14C6\nadd ecx, 1\nmov [r8+rsi*4], ecx\nloc_14C6:\nsub rax, 1\ncmp r11d, eax\njl short loc_14B0\nloc_14CF:\nsub rsi, 1\ntest esi, esi\njns short loc_14A0\nadd r12d, ds:dword_0[r10*4]\nmov r9d, r9d\nmov edx, 1\nlea ecx, [r12-1]\nnop dword ptr [rax+00h]\nloc_14F0:\nmov eax, [r8+rdx*4]\nadd eax, [rdi+rdx*4]\nsub eax, 1\ncmp ecx, eax\ncmovl ecx, eax\nadd rdx, 1\ncmp rdx, r9\njnz short loc_14F0\nloc_1508:\nmov rax, [rbp+var_28]\nsub rax, fs:28h\njnz short loc_155F\nlea rsp, [rbp-18h]\nmov eax, ecx\npop rbx\npop r12\npop r13\npop rbp\nretn\nloc_1524:\nor [rsp+rcx+1030h+var_1038], 0\njmp loc_1356\nloc_152F:\nmov ecx, ds:dword_0[r12*4]\nadd ecx, ds:dword_0[r10*4]\nsub ecx, 1\njmp short loc_1508\nloc_1544:\nor [rsp+rcx+2030h+var_2038], 0\njmp loc_13A5\nloc_154F:\nmov ecx, ds:dword_0[r10*4]\nadd ecx, r12d\nsub ecx, 1\njmp short loc_1508\nloc_155F:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v3; // rax\n int *v4; // rsi\n signed __int64 v5; // rcx\n void *v6; // rsp\n int *v7; // rsi\n signed __int64 v8; // rcx\n void *v9; // rsp\n int *v10; // rax\n __int64 v11; // rbx\n int *v12; // rcx\n __int64 v13; // rcx\n int v14; // r11d\n __int64 v15; // rax\n int v16; // esi\n int *v17; // rcx\n int *v18; // rax\n int v19; // r12d\n __int64 v20; // rsi\n int v21; // r13d\n int v22; // ebx\n __int64 v23; // rax\n int v24; // ecx\n __int64 v25; // rdx\n int v26; // ecx\n __int64 v28; // [rsp+0h] [rbp-2038h]\n int v29; // [rsp+8h] [rbp-2030h] BYREF\n _BYTE v30[4092]; // [rsp+Ch] [rbp-202Ch] BYREF\n int v31; // [rsp+1008h] [rbp-1030h] BYREF\n _BYTE v32[4084]; // [rsp+100Ch] [rbp-102Ch] BYREF\n _QWORD v33[6]; // [rsp+2008h] [rbp-30h] BYREF\n\n v33[1] = __readfsqword(0x28u);\n v3 = 4LL * (a2 + 1) + 15;\n v4 = (int *)((char *)v33 - (v3 & 0xFFFFFFFFFFFFF000LL));\n if ( v33 != (_QWORD *)v4 )\n {\n while ( &v31 != v4 )\n ;\n }\n v5 = v3 & 0xFF0;\n v6 = alloca(v5);\n if ( (v3 & 0xFF0) != 0 )\n *(_QWORD *)&v30[v5 + 4084] = *(_QWORD *)&v30[v5 + 4084];\n v7 = (int *)&v32[-(v3 & 0xFFFFFFFFFFFFF000LL) - 4];\n if ( &v31 != v7 )\n {\n while ( &v29 != v7 )\n ;\n }\n v8 = v3 & 0xFF0;\n v9 = alloca(v8);\n if ( (v3 & 0xFF0) != 0 )\n *(__int64 *)((char *)&v28 + v8) = *(__int64 *)((char *)&v28 + v8);\n if ( a2 < 0 )\n {\n return (unsigned int)(v29 + v31 - 1);\n }\n else\n {\n v10 = &v31;\n v11 = 4LL * a2 + 4;\n v12 = (int *)&v32[v11 - 4];\n if ( (v11 & 4) == 0 || (v10 = (int *)v32, v31 = 1, v32 != (_BYTE *)v12) )\n {\n do\n {\n *v10 = 1;\n v10 += 2;\n *(v10 - 1) = 1;\n }\n while ( v10 != v12 );\n }\n if ( a2 > 1 )\n {\n v13 = 4LL;\n do\n {\n v14 = *(_DWORD *)(a1 + v13);\n v15 = 0LL;\n do\n {\n if ( v14 > *(_DWORD *)(a1 + v15) )\n {\n v16 = *(_DWORD *)&v32[v15 - 4];\n if ( v16 >= *(_DWORD *)&v32[v13 - 4] )\n *(_DWORD *)&v32[v13 - 4] = v16 + 1;\n }\n v15 += 4LL;\n }\n while ( v15 != v13 );\n v13 += 4LL;\n }\n while ( v13 != 4LL * (unsigned int)a2 );\n }\n v17 = (int *)&v30[v11 - 4];\n v18 = &v29;\n if ( (v11 & 4) == 0 || (v18 = (int *)v30, v29 = 1, v30 != (_BYTE *)v17) )\n {\n do\n {\n *v18 = 1;\n v18 += 2;\n *(v18 - 1) = 1;\n }\n while ( v18 != v17 );\n }\n v19 = v31;\n LODWORD(v20) = a2 - 2;\n if ( a2 - 2 < 0 )\n {\n return (unsigned int)(v31 + v29 - 1);\n }\n else\n {\n v21 = a2 - 1;\n v20 = (int)v20;\n do\n {\n if ( (int)v20 < v21 )\n {\n v22 = *(_DWORD *)(a1 + 4 * v20);\n v23 = v21;\n do\n {\n if ( v22 > *(_DWORD *)(a1 + 4 * v23) )\n {\n v24 = *(_DWORD *)&v30[4 * v23 - 4];\n if ( v24 >= *(_DWORD *)&v30[4 * v20 - 4] )\n *(_DWORD *)&v30[4 * v20 - 4] = v24 + 1;\n }\n --v23;\n }\n while ( (int)v20 < (int)v23 );\n }\n --v20;\n }\n while ( (int)v20 >= 0 );\n v25 = 1LL;\n v26 = v29 + v19 - 1;\n do\n {\n if ( v26 < *(_DWORD *)&v32[4 * v25 - 4] + *(_DWORD *)&v30[4 * v25 - 4] - 1 )\n v26 = *(_DWORD *)&v32[4 * v25 - 4] + *(_DWORD *)&v30[4 * v25 - 4] - 1;\n ++v25;\n }\n while ( v25 != a2 );\n }\n }\n return (unsigned int)v26;\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\npush rbp\nmov rdx, rdi\nmov r9d, esi\nmov rbp, rsp\npush r13\npush r12\npush rbx\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nlea eax, [rsi+1]\nmov rsi, rsp\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rdi, rax\nmov rcx, rax\nand rdi, 0FFFFFFFFFFFFF000h\nand rcx, 0FFFFFFFFFFFFFFF0h\nsub rsi, rdi\ncmp rsp, rsi\njz short loc_1344\nloc_132F:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rsi\njnz short loc_132F\nloc_1344:\nand ecx, 0FFFh\nsub rsp, rcx\ntest rcx, rcx\njnz loc_1524\nloc_1356:\nlea rdi, [rsp+1030h+var_102D]\nmov rcx, rax\nmov rsi, rsp\nand rax, 0FFFFFFFFFFFFF000h\nmov r12, rdi\nsub rsi, rax\nand rdi, 0FFFFFFFFFFFFFFFCh\nand rcx, 0FFFFFFFFFFFFFFF0h\nshr r12, 2\ncmp rsp, rsi\njz short loc_1393\nloc_137E:\nsub rsp, 1000h\nor [rsp+2030h+var_1038], 0\ncmp rsp, rsi\njnz short loc_137E\nloc_1393:\nand ecx, 0FFFh\nsub rsp, rcx\ntest rcx, rcx\njnz loc_1544\nloc_13A5:\nlea r8, [rsp+2030h+var_202D]\nmov r10, r8\nand r8, 0FFFFFFFFFFFFFFFCh\nshr r10, 2\ntest r9d, r9d\njs loc_152F\nmovsxd rcx, r9d\nmov rax, rdi\nlea rbx, ds:4[rcx*4]\nlea rcx, [rdi+rbx]\ntest bl, 4\njz short loc_13E8\nlea rax, [rdi+4]\nmov dword ptr [rdi], 1\ncmp rax, rcx\njz short loc_13FE\nnop dword ptr [rax+00h]\nloc_13E8:\nmov dword ptr [rax], 1\nadd rax, 8\nmov dword ptr [rax-4], 1\ncmp rax, rcx\njnz short loc_13E8\nloc_13FE:\ncmp r9d, 1\njle short loc_1446\nmov r13d, r9d\nmov ecx, 4\nshl r13, 2\nloc_1410:\nmov r11d, [rdx+rcx]\nxor eax, eax\nnop word ptr [rax+rax+00000000h]\nloc_1420:\ncmp r11d, [rdx+rax]\njle short loc_1434\nmov esi, [rdi+rax]\ncmp esi, [rdi+rcx]\njl short loc_1434\nadd esi, 1\nmov [rdi+rcx], esi\nloc_1434:\nadd rax, 4\ncmp rax, rcx\njnz short loc_1420\nadd rcx, 4\ncmp rcx, r13\njnz short loc_1410\nloc_1446:\nlea rcx, [r8+rbx]\nand ebx, 4\nmov rax, r8\njz short loc_1468\nlea rax, [r8+4]\nmov dword ptr [r8], 1\ncmp rax, rcx\njz short loc_147E\nnop word ptr [rax+rax+00h]\nloc_1468:\nmov dword ptr [rax], 1\nadd rax, 8\nmov dword ptr [rax-4], 1\ncmp rax, rcx\njnz short loc_1468\nloc_147E:\nmov esi, r9d\nmov r12d, ds:dword_0[r12*4]\nsub esi, 2\njs loc_154F\nlea r13d, [r9-1]\nmovsxd rsi, esi\nnop dword ptr [rax+00000000h]\nloc_14A0:\nmov r11d, esi\ncmp esi, r13d\njge short loc_14CF\nmov ebx, [rdx+rsi*4]\nmovsxd rax, r13d\nxchg ax, ax\nloc_14B0:\ncmp ebx, [rdx+rax*4]\njle short loc_14C6\nmov ecx, [r8+rax*4]\ncmp ecx, [r8+rsi*4]\njl short loc_14C6\nadd ecx, 1\nmov [r8+rsi*4], ecx\nloc_14C6:\nsub rax, 1\ncmp r11d, eax\njl short loc_14B0\nloc_14CF:\nsub rsi, 1\ntest esi, esi\njns short loc_14A0\nadd r12d, ds:dword_0[r10*4]\nmov r9d, r9d\nmov edx, 1\nlea ecx, [r12-1]\nnop dword ptr [rax+00h]\nloc_14F0:\nmov eax, [r8+rdx*4]\nadd eax, [rdi+rdx*4]\nsub eax, 1\ncmp ecx, eax\ncmovl ecx, eax\nadd rdx, 1\ncmp rdx, r9\njnz short loc_14F0\nloc_1508:\nmov rax, [rbp+var_28]\nsub rax, fs:28h\njnz short loc_155F\nlea rsp, [rbp-18h]\nmov eax, ecx\npop rbx\npop r12\npop r13\npop rbp\nretn\nloc_1524:\nor [rsp+rcx+1030h+var_1038], 0\njmp loc_1356\nloc_152F:\nmov ecx, ds:dword_0[r12*4]\nadd ecx, ds:dword_0[r10*4]\nsub ecx, 1\njmp short loc_1508\nloc_1544:\nor [rsp+rcx+2030h+var_2038], 0\njmp loc_13A5\nloc_154F:\nmov ecx, ds:dword_0[r10*4]\nadd ecx, r12d\nsub ecx, 1\njmp short loc_1508\nloc_155F:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12E0(__int64 a1, int a2)\n{\n __int64 v3; // rax\n int *v4; // rsi\n signed __int64 v5; // rcx\n void *v6; // rsp\n int *v7; // rsi\n signed __int64 v8; // rcx\n void *v9; // rsp\n int *v10; // rax\n __int64 v11; // rbx\n int *v12; // rcx\n __int64 v13; // rcx\n int v14; // r11d\n __int64 v15; // rax\n int v16; // esi\n int *v17; // rcx\n int *v18; // rax\n int v19; // r12d\n __int64 v20; // rsi\n int v21; // r13d\n int v22; // ebx\n __int64 v23; // rax\n int v24; // ecx\n __int64 v25; // rdx\n int v26; // ecx\n __int64 v28; // [rsp+0h] [rbp-2038h]\n int v29; // [rsp+8h] [rbp-2030h] BYREF\n _BYTE v30[4092]; // [rsp+Ch] [rbp-202Ch] BYREF\n int v31; // [rsp+1008h] [rbp-1030h] BYREF\n _BYTE v32[4084]; // [rsp+100Ch] [rbp-102Ch] BYREF\n _QWORD v33[6]; // [rsp+2008h] [rbp-30h] BYREF\n\n v33[1] = __readfsqword(0x28u);\n v3 = 4LL * (a2 + 1) + 15;\n v4 = (int *)((char *)v33 - (v3 & 0xFFFFFFFFFFFFF000LL));\n if ( v33 != (_QWORD *)v4 )\n {\n while ( &v31 != v4 )\n ;\n }\n v5 = v3 & 0xFF0;\n v6 = alloca(v5);\n if ( (v3 & 0xFF0) != 0 )\n *(_QWORD *)&v30[v5 + 4084] = *(_QWORD *)&v30[v5 + 4084];\n v7 = (int *)&v32[-(v3 & 0xFFFFFFFFFFFFF000LL) - 4];\n if ( &v31 != v7 )\n {\n while ( &v29 != v7 )\n ;\n }\n v8 = v3 & 0xFF0;\n v9 = alloca(v8);\n if ( (v3 & 0xFF0) != 0 )\n *(__int64 *)((char *)&v28 + v8) = *(__int64 *)((char *)&v28 + v8);\n if ( a2 < 0 )\n {\n return (unsigned int)(v29 + v31 - 1);\n }\n else\n {\n v10 = &v31;\n v11 = 4LL * a2 + 4;\n v12 = (int *)&v32[v11 - 4];\n if ( (v11 & 4) == 0 || (v10 = (int *)v32, v31 = 1, v32 != (_BYTE *)v12) )\n {\n do\n {\n *v10 = 1;\n v10 += 2;\n *(v10 - 1) = 1;\n }\n while ( v10 != v12 );\n }\n if ( a2 > 1 )\n {\n v13 = 4LL;\n do\n {\n v14 = *(_DWORD *)(a1 + v13);\n v15 = 0LL;\n do\n {\n if ( v14 > *(_DWORD *)(a1 + v15) )\n {\n v16 = *(_DWORD *)&v32[v15 - 4];\n if ( v16 >= *(_DWORD *)&v32[v13 - 4] )\n *(_DWORD *)&v32[v13 - 4] = v16 + 1;\n }\n v15 += 4LL;\n }\n while ( v15 != v13 );\n v13 += 4LL;\n }\n while ( v13 != 4LL * (unsigned int)a2 );\n }\n v17 = (int *)&v30[v11 - 4];\n v18 = &v29;\n if ( (v11 & 4) == 0 || (v18 = (int *)v30, v29 = 1, v30 != (_BYTE *)v17) )\n {\n do\n {\n *v18 = 1;\n v18 += 2;\n *(v18 - 1) = 1;\n }\n while ( v18 != v17 );\n }\n v19 = v31;\n LODWORD(v20) = a2 - 2;\n if ( a2 - 2 < 0 )\n {\n return (unsigned int)(v31 + v29 - 1);\n }\n else\n {\n v21 = a2 - 1;\n v20 = (int)v20;\n do\n {\n if ( (int)v20 < v21 )\n {\n v22 = *(_DWORD *)(a1 + 4 * v20);\n v23 = v21;\n do\n {\n if ( v22 > *(_DWORD *)(a1 + 4 * v23) )\n {\n v24 = *(_DWORD *)&v30[4 * v23 - 4];\n if ( v24 >= *(_DWORD *)&v30[4 * v20 - 4] )\n *(_DWORD *)&v30[4 * v20 - 4] = v24 + 1;\n }\n --v23;\n }\n while ( (int)v20 < (int)v23 );\n }\n --v20;\n }\n while ( (int)v20 >= 0 );\n v25 = 1LL;\n v26 = v29 + v19 - 1;\n do\n {\n if ( v26 < *(_DWORD *)&v32[4 * v25 - 4] + *(_DWORD *)&v30[4 * v25 - 4] - 1 )\n v26 = *(_DWORD *)&v32[4 * v25 - 4] + *(_DWORD *)&v30[4 * v25 - 4] - 1;\n ++v25;\n }\n while ( v25 != a2 );\n }\n }\n return (unsigned int)v26;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12E0(long long a1, int a2) {\n long long v3;\n int *v4;\n signed long long v5;\n void *v6;\n int *v7;\n signed long long v8;\n void *v9;\n int *v10;\n long long v11;\n int *v12;\n long long v13;\n int v14;\n long long v15;\n int v16;\n int *v17;\n int *v18;\n int v19;\n long long v20;\n int v21;\n int v22;\n long long v23;\n int v24;\n long long v25;\n int v26;\n long long v28;\n int v29;\n uint8_t v30[4092];\n int v31;\n uint8_t v32[4084];\n uint64_t v33[6];\n v33[1] = __readfsqword(40u);\n v3 = 4LL * (a2 + 1) + 15;\n v4 = (int *)((char *)v33 - (v3 & 18446744073709547520LL));\n if (v33 != (uint64_t *)v4) {\n while (&v31 != v4)\n ;\n }\n v5 = v3 & 4080;\n v6 = alloca(v5);\n if ((v3 & 4080) != 0)\n *(uint64_t *)&v30[v5 + 4084] = *(uint64_t *)&v30[v5 + 4084];\n v7 = (int *)&v32[-(v3 & 18446744073709547520LL) - 4];\n if (&v31 != v7) {\n while (&v29 != v7)\n ;\n }\n v8 = v3 & 4080;\n v9 = alloca(v8);\n if ((v3 & 4080) != 0)\n *(long long *)((char *)&v28 + v8) = *(long long *)((char *)&v28 + v8);\n if (a2 < 0) {\n return (unsigned int)(v29 + v31 - 1);\n } else {\n v10 = &v31;\n v11 = 4LL * a2 + 4;\n v12 = (int *)&v32[v11 - 4];\n if ((v11 & 4) == 0 || (v10 = (int *)v32, v31 = 1, v32 != (uint8_t *)v12)) {\n do {\n *v10 = 1;\n v10 += 2;\n *(v10 - 1) = 1;\n } while (v10 != v12);\n }\n if (a2 > 1) {\n v13 = 4LL;\n do {\n v14 = *(uint32_t *)(a1 + v13);\n v15 = 0LL;\n do {\n if (v14 > *(uint32_t *)(a1 + v15)) {\n v16 = *(uint32_t *)&v32[v15 - 4];\n if (v16 >= *(uint32_t *)&v32[v13 - 4])\n *(uint32_t *)&v32[v13 - 4] = v16 + 1;\n }\n v15 += 4LL;\n } while (v15 != v13);\n v13 += 4LL;\n } while (v13 != 4LL * (unsigned int)a2);\n }\n v17 = (int *)&v30[v11 - 4];\n v18 = &v29;\n if ((v11 & 4) == 0 || (v18 = (int *)v30, v29 = 1, v30 != (uint8_t *)v17)) {\n do {\n *v18 = 1;\n v18 += 2;\n *(v18 - 1) = 1;\n } while (v18 != v17);\n }\n v19 = v31;\n LODWORD(v20) = a2 - 2;\n if (a2 - 2 < 0) {\n return (unsigned int)(v31 + v29 - 1);\n } else {\n v21 = a2 - 1;\n v20 = (int)v20;\n do {\n if ((int)v20 < v21) {\n v22 = *(uint32_t *)(a1 + 4 * v20);\n v23 = v21;\n do {\n if (v22 > *(uint32_t *)(a1 + 4 * v23)) {\n v24 = *(uint32_t *)&v30[4 * v23 - 4];\n if (v24 >= *(uint32_t *)&v30[4 * v20 - 4])\n *(uint32_t *)&v30[4 * v20 - 4] = v24 + 1;\n }\n --v23;\n } while ((int)v20 < (int)v23);\n }\n --v20;\n } while ((int)v20 >= 0);\n v25 = 1LL;\n v26 = v29 + v19 - 1;\n do {\n if (v26 <\n *(uint32_t *)&v32[4 * v25 - 4] + *(uint32_t *)&v30[4 * v25 - 4] - 1)\n v26 = *(uint32_t *)&v32[4 * v25 - 4] +\n *(uint32_t *)&v30[4 * v25 - 4] - 1;\n ++v25;\n } while (v25 != a2);\n }\n }\n return (unsigned int)v26;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v3;\n int *v4;\n signed long long v5;\n void *v6;\n int *v7;\n signed long long v8;\n void *v9;\n int *v10;\n long long v11;\n int *v12;\n long long v13;\n int v14;\n long long v15;\n int v16;\n int *v17;\n int *v18;\n int v19;\n long long v20;\n int v21;\n int v22;\n long long v23;\n int v24;\n long long v25;\n int v26;\n long long v28;\n int v29;\n uint8_t v30[4092];\n int v31;\n uint8_t v32[4084];\n uint64_t v33[6];\n v33[1] = __readfsqword(40u);\n v3 = 4LL * (a2 + 1) + 15;\n v4 = (int *)((char *)v33 - (v3 & 18446744073709547520LL));\n if (v33 != (uint64_t *)v4) {\n while (&v31 != v4)\n ;\n }\n v5 = v3 & 4080;\n v6 = alloca(v5);\n if ((v3 & 4080) != 0)\n *(uint64_t *)&v30[v5 + 4084] = *(uint64_t *)&v30[v5 + 4084];\n v7 = (int *)&v32[-(v3 & 18446744073709547520LL) - 4];\n if (&v31 != v7) {\n while (&v29 != v7)\n ;\n }\n v8 = v3 & 4080;\n v9 = alloca(v8);\n if ((v3 & 4080) != 0)\n *(long long *)((char *)&v28 + v8) = *(long long *)((char *)&v28 + v8);\n if (a2 < 0) {\n return (unsigned int)(v29 + v31 - 1);\n } else {\n v10 = &v31;\n v11 = 4LL * a2 + 4;\n v12 = (int *)&v32[v11 - 4];\n if ((v11 & 4) == 0 || (v10 = (int *)v32, v31 = 1, v32 != (uint8_t *)v12)) {\n do {\n *v10 = 1;\n v10 += 2;\n *(v10 - 1) = 1;\n } while (v10 != v12);\n }\n if (a2 > 1) {\n v13 = 4LL;\n do {\n v14 = *(uint32_t *)(a1 + v13);\n v15 = 0LL;\n do {\n if (v14 > *(uint32_t *)(a1 + v15)) {\n v16 = *(uint32_t *)&v32[v15 - 4];\n if (v16 >= *(uint32_t *)&v32[v13 - 4])\n *(uint32_t *)&v32[v13 - 4] = v16 + 1;\n }\n v15 += 4LL;\n } while (v15 != v13);\n v13 += 4LL;\n } while (v13 != 4LL * (unsigned int)a2);\n }\n v17 = (int *)&v30[v11 - 4];\n v18 = &v29;\n if ((v11 & 4) == 0 || (v18 = (int *)v30, v29 = 1, v30 != (uint8_t *)v17)) {\n do {\n *v18 = 1;\n v18 += 2;\n *(v18 - 1) = 1;\n } while (v18 != v17);\n }\n v19 = v31;\n LODWORD(v20) = a2 - 2;\n if (a2 - 2 < 0) {\n return (unsigned int)(v31 + v29 - 1);\n } else {\n v21 = a2 - 1;\n v20 = (int)v20;\n do {\n if ((int)v20 < v21) {\n v22 = *(uint32_t *)(a1 + 4 * v20);\n v23 = v21;\n do {\n if (v22 > *(uint32_t *)(a1 + 4 * v23)) {\n v24 = *(uint32_t *)&v30[4 * v23 - 4];\n if (v24 >= *(uint32_t *)&v30[4 * v20 - 4])\n *(uint32_t *)&v30[4 * v20 - 4] = v24 + 1;\n }\n --v23;\n } while ((int)v20 < (int)v23);\n }\n --v20;\n } while ((int)v20 >= 0);\n v25 = 1LL;\n v26 = v29 + v19 - 1;\n do {\n if (v26 <\n *(uint32_t *)&v32[4 * v25 - 4] + *(uint32_t *)&v30[4 * v25 - 4] - 1)\n v26 = *(uint32_t *)&v32[4 * v25 - 4] +\n *(uint32_t *)&v30[4 * v25 - 4] - 1;\n ++v25;\n } while (v25 != a2);\n }\n }\n return (unsigned int)v26;\n}" + }, + { + "index": 522, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int lis[n + 1];\n int lds[n + 1];\n int i, j, maximum;\n for (i = 0; i <= n; i++) {\n lis[i] = 1;\n }\n for (i = 1; i < n; i++) {\n for (j = 0; j < i; j++) {\n if (arr[i] > arr[j] && lis[i] < lis[j] + 1) {\n lis[i] = lis[j] + 1;\n }\n }\n }\n for (i = 0; i <= n; i++) {\n lds[i] = 1;\n }\n for (i = n - 2; i >= 0; i--) {\n for (j = n - 1; j > i; j--) {\n if (arr[i] > arr[j] && lds[i] < lds[j] + 1) {\n lds[i] = lds[j] + 1;\n }\n }\n }\n maximum = lis[0] + lds[0] - 1;\n for (i = 1; i < n; i++) {\n if ((lis[i] + lds[i] - 1) > maximum) {\n maximum = lis[i] + lds[i] - 1;\n }\n }\n return maximum;\n}", + "test": "int main() {\n\n int arr1[] = {0, 8, 4, 12, 2, 10, 6, 14, 1, 9, 5, 13, 3, 11, 7, 15};\n\n int arr2[] = {1, 11, 2, 10, 4, 5, 2, 1};\n\n int arr3[] = {80, 60, 30, 40, 20, 10};\n\n\n\n assert(func0(arr1, sizeof(arr1)/sizeof(arr1[0])) == 7);\n\n assert(func0(arr2, sizeof(arr2)/sizeof(arr2[0])) == 6);\n\n assert(func0(arr3, sizeof(arr3)/sizeof(arr3[0])) == 5);\n\n \n\n printf(\"All tests passed.\\n\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r13\npush %r12\nlea 0x1(%rsi),%r12d\npush %rbx\nsub $0x18,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x28(%rbp)\nxor %eax,%eax\nmovslq %r12d,%rax\nmov %rsp,%rbx\nlea 0xf(,%rax,4),%rax\nmov %rax,%rcx\nmov %rax,%rdx\nand $0xfffffffffffff000,%rcx\nand $0xfffffffffffffff0,%rdx\nsub %rcx,%rbx\nmov %rbx,%rcx\ncmp %rcx,%rsp\nje 1343 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rcx,%rsp\njne 132e \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 166e \nmov %rax,%rdx\nmov %rsp,%rbx\nand $0xfffffffffffff000,%rax\nlea 0x3(%rsp),%r8\nsub %rax,%rbx\nand $0xfffffffffffffff0,%rdx\nmov %r8,%r10\nmov %rbx,%rax\nand $0xfffffffffffffffc,%r8\nshr $0x2,%r10\ncmp %rax,%rsp\nje 1395 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 1380 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 16e8 \nlea 0x3(%rsp),%r9\nmov %r9,%r11\nand $0xfffffffffffffffc,%r9\nshr $0x2,%r11\ntest %esi,%esi\njs 1693 \ncmp $0x2,%esi\njle 16b2 \nmov %r12d,%edx\nmovdqa 0xd1d(%rip),%xmm0\nmov %r8,%rax\nshr $0x2,%edx\nshl $0x4,%rdx\nadd %r8,%rdx\nmovups %xmm0,(%rax)\nadd $0x10,%rax\ncmp %rdx,%rax\njne 13e0 \nmov %r12d,%eax\nand $0xfffffffc,%eax\ntest $0x3,%r12b\nje 142a \nmovslq %eax,%rdx\nadd $0x1,%eax\nmovl $0x1,(%r8,%rdx,4)\ncmp %eax,%esi\njl 142a \nmovslq %eax,%rdx\nadd $0x1,%eax\nmovl $0x1,(%r8,%rdx,4)\ncmp %eax,%esi\njl 16d3 \ncltq\nmovl $0x1,(%r8,%rax,4)\nmov $0x1,%edx\nmov (%rdi,%rdx,4),%ebx\nxor %eax,%eax\nnopl (%rax)\ncmp (%rdi,%rax,4),%ebx\njle 144e \nmov (%r8,%rax,4),%ecx\ncmp (%r8,%rdx,4),%ecx\njl 144e \nadd $0x1,%ecx\nmov %ecx,(%r8,%rdx,4)\nadd $0x1,%rax\ncmp %rdx,%rax\njne 1438 \nadd $0x1,%rdx\ncmp %edx,%esi\njg 1430 \ncmp $0x2,%esi\njle 16cc \nmov %r12d,%edx\nmovdqa 0xc7d(%rip),%xmm0\nmov %r9,%rax\nshr $0x2,%edx\nshl $0x4,%rdx\nadd %r9,%rdx\nmovups %xmm0,(%rax)\nadd $0x10,%rax\ncmp %rdx,%rax\njne 1480 \nmov %r12d,%eax\nand $0xfffffffc,%eax\nand $0x3,%r12d\nje 1693 \nmovslq %eax,%rdx\nmovl $0x1,(%r9,%rdx,4)\nlea 0x1(%rax),%edx\ncmp %edx,%esi\njl 1693 \nmovslq %edx,%rdx\nadd $0x2,%eax\nmovl $0x1,(%r9,%rdx,4)\ncmp %esi,%eax\njg 1693 \ncltq\nlea -0x2(%rsi),%r12d\nmovl $0x1,(%r9,%rax,4)\nmov %r12d,%edx\nlea -0x1(%rsi),%r13d\ncmp %r13d,%r12d\njge 1680 \nnopw %cs:0x0(%rax,%rax,1)\nmovslq %edx,%rdx\nmovslq %r13d,%r13\nnopw %cs:0x0(%rax,%rax,1)\nmov (%rdi,%rdx,4),%ebx\nmov %r13,%rax\nnopw %cs:0x0(%rax,%rax,1)\ncmp %ebx,(%rdi,%rax,4)\njge 1526 \nmov (%r9,%rax,4),%ecx\ncmp %ecx,(%r9,%rdx,4)\njg 1526 \nadd $0x1,%ecx\nmov %ecx,(%r9,%rdx,4)\nsub $0x1,%rax\ncmp %edx,%eax\njg 1510 \nsub $0x1,%rdx\ntest %edx,%edx\njns 1500 \nmov 0x0(,%r11,4),%eax\nadd 0x0(,%r10,4),%eax\nsub $0x1,%eax\ncmp $0x1,%esi\njle 1650 \nlea -0x1(%rsi),%ecx\ncmp $0x2,%r12d\njbe 16a8 \nmov %ecx,%edx\nmovd %eax,%xmm5\npcmpeqd %xmm3,%xmm3\nmov $0x4,%eax\nshr $0x2,%edx\npshufd $0x0,%xmm5,%xmm2\nshl $0x4,%rdx\nadd $0x4,%rdx\nxchg %ax,%ax\nmovdqu (%r9,%rax,1),%xmm0\nmovdqu (%r8,%rax,1),%xmm4\nadd $0x10,%rax\npaddd %xmm4,%xmm0\npaddd %xmm3,%xmm0\nmovdqa %xmm0,%xmm1\npcmpgtd %xmm2,%xmm1\npand %xmm1,%xmm0\npandn %xmm2,%xmm1\nmovdqa %xmm1,%xmm2\npor %xmm0,%xmm2\ncmp %rdx,%rax\njne 1580 \nmovdqa %xmm2,%xmm0\nmov %ecx,%edi\npsrldq $0x8,%xmm0\nand $0xfffffffc,%edi\nmovdqa %xmm0,%xmm1\nmovdqa %xmm0,%xmm3\nlea 0x1(%rdi),%edx\npcmpgtd %xmm2,%xmm1\npand %xmm1,%xmm3\npandn %xmm2,%xmm1\nmovdqa %xmm1,%xmm0\npor %xmm3,%xmm0\nmovdqa %xmm0,%xmm2\npsrldq $0x4,%xmm2\nmovdqa %xmm2,%xmm1\npcmpgtd %xmm0,%xmm1\npand %xmm1,%xmm2\npandn %xmm0,%xmm1\npor %xmm2,%xmm1\nmovd %xmm1,%eax\ncmp %ecx,%edi\nje 1650 \nmovslq %edx,%rdi\nmov (%r8,%rdi,4),%ecx\nadd (%r9,%rdi,4),%ecx\nsub $0x1,%ecx\ncmp %ecx,%eax\ncmovl %ecx,%eax\nlea 0x1(%rdx),%ecx\ncmp %ecx,%esi\njle 1650 \nmovslq %ecx,%rdi\nmov (%r9,%rdi,4),%ecx\nadd (%r8,%rdi,4),%ecx\nsub $0x1,%ecx\ncmp %ecx,%eax\ncmovl %ecx,%eax\nadd $0x2,%edx\ncmp %esi,%edx\njge 1650 \nmovslq %edx,%rdx\nmov (%r8,%rdx,4),%ecx\nadd (%r9,%rdx,4),%ecx\nmov %ecx,%edx\nsub $0x1,%edx\ncmp %edx,%eax\ncmovl %edx,%eax\nmov -0x28(%rbp),%rsi\nxor %fs:0x28,%rsi\njne 16f3 \nlea -0x18(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %rbp\nretq\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 1355 \nnopl 0x0(%rax)\nlea -0x1(%r12),%edx\ntest %r12d,%r12d\njne 14f0 \njmpq 1536 \nlea -0x2(%rsi),%r12d\nmov %r12d,%edx\ntest %r12d,%r12d\njns 14d9 \njmpq 1536 \nmov $0x1,%edx\njmpq 1607 \nmovl $0x1,0x0(,%r10,4)\ntest %esi,%esi\nje 16cc \nmov $0x1,%eax\njmpq 140a \nxor %eax,%eax\njmpq 149c \ncmp $0x1,%esi\njg 142a \njmpq 145f \nnopl 0x0(%rax)\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 13a7 \ncallq 1080 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov r10d, esi\nmov rbp, rsp\npush r14\npush r13\npush r12\npush rbx\nlea ebx, [rsi+1]\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nmovsxd rax, ebx\nmov rcx, rsp\nlea rax, ds:0Fh[rax*4]\nmov rsi, rax\nmov rdx, rax\nand rsi, 0FFFFFFFFFFFFF000h\nand rdx, 0FFFFFFFFFFFFFFF0h\nsub rcx, rsi\ncmp rsp, rcx\njz short loc_1344\nloc_132F:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rcx\njnz short loc_132F\nloc_1344:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1676\nloc_1356:\nlea rsi, [rsp+1030h+var_102D]\nmov rdx, rax\nmov rcx, rsp\nand rax, 0FFFFFFFFFFFFF000h\nmov r12, rsi\nsub rcx, rax\nand rsi, 0FFFFFFFFFFFFFFFCh\nand rdx, 0FFFFFFFFFFFFFFF0h\nshr r12, 2\ncmp rsp, rcx\njz short loc_1393\nloc_137E:\nsub rsp, 1000h\nor [rsp+2030h+var_1038], 0\ncmp rsp, rcx\njnz short loc_137E\nloc_1393:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1711\nloc_13A5:\nlea r9, [rsp+2030h+var_202D]\nmov r11, r9\nand r9, 0FFFFFFFFFFFFFFFCh\nshr r11, 2\ntest r10d, r10d\njs loc_1681\ncmp r10d, 2\njbe loc_1696\nmov edx, ebx\nmovdqa xmm0, cs:xmmword_20D0\nmov rax, rsi\nshr edx, 2\nshl rdx, 4\nlea rcx, [rsi+rdx]\nand edx, 10h\njz short loc_13F8\nlea rax, [rsi+10h]\nmovups xmmword ptr [rsi], xmm0\ncmp rax, rcx\njz short loc_1408\nnop dword ptr [rax+00000000h]\nloc_13F8:\nmovups xmmword ptr [rax], xmm0\nadd rax, 20h ; ' '\nmovups xmmword ptr [rax-10h], xmm0\ncmp rax, rcx\njnz short loc_13F8\nloc_1408:\nmov eax, ebx\nand eax, 0FFFFFFFCh\ntest bl, 3\njz short loc_143A\nmovsxd rdx, eax\nlea rdx, [rsi+rdx*4]\nmov dword ptr [rdx], 1\ncmp r10d, eax\njle short loc_143A\nadd eax, 2\nmov dword ptr [rdx+4], 1\ncmp r10d, eax\njl short loc_143A\nloc_1433:\nmov dword ptr [rdx+8], 1\nloc_143A:\nmov r13d, r10d\nmov edx, 4\nshl r13, 2\nnop word ptr [rax+rax+00000000h]\nloc_1450:\nmov r8d, [rdi+rdx]\nxor eax, eax\nnop word ptr [rax+rax+00000000h]\nloc_1460:\ncmp r8d, [rdi+rax]\njle short loc_1474\nmov ecx, [rsi+rax]\ncmp ecx, [rsi+rdx]\njl short loc_1474\nadd ecx, 1\nmov [rsi+rdx], ecx\nloc_1474:\nadd rax, 4\ncmp rax, rdx\njnz short loc_1460\nadd rdx, 4\ncmp rdx, r13\njnz short loc_1450\nloc_1486:\ncmp r10d, 2\njbe loc_16CF\nmov edx, ebx\nmovdqa xmm0, cs:xmmword_20D0\nmov rax, r9\nshr edx, 2\nshl rdx, 4\nlea rcx, [r9+rdx]\nand edx, 10h\njz short loc_14C0\nlea rax, [r9+10h]\nmovups xmmword ptr [r9], xmm0\ncmp rcx, rax\njz short loc_14D0\nnop word ptr [rax+rax+00h]\nloc_14C0:\nmovups xmmword ptr [rax], xmm0\nadd rax, 20h ; ' '\nmovups xmmword ptr [rax-10h], xmm0\ncmp rcx, rax\njnz short loc_14C0\nloc_14D0:\nmov eax, ebx\nand eax, 0FFFFFFFCh\nand ebx, 3\njz short loc_1502\nmovsxd rdx, eax\nlea rdx, [r9+rdx*4]\nmov dword ptr [rdx], 1\ncmp r10d, eax\njle short loc_1502\nadd eax, 2\nmov dword ptr [rdx+4], 1\ncmp r10d, eax\njl short loc_1502\nloc_14FB:\nmov dword ptr [rdx+8], 1\nloc_1502:\nlea r13d, [r10-2]\nlea r8d, [r10-1]\nmov r12d, ds:dword_0[r12*4]\nmovsxd rax, r13d\nmovsxd r14, r8d\nnop dword ptr [rax+rax+00000000h]\nloc_1520:\nmov ebx, [rdi+rax*4]\nmov rdx, r14\nnop word ptr [rax+rax+00000000h]\nloc_1530:\ncmp [rdi+rdx*4], ebx\njge short loc_1546\nmov ecx, [r9+rdx*4]\ncmp [r9+rax*4], ecx\njg short loc_1546\nadd ecx, 1\nmov [r9+rax*4], ecx\nloc_1546:\nsub rdx, 1\ncmp eax, edx\njl short loc_1530\nsub rax, 1\ntest eax, eax\njns short loc_1520\nadd r12d, ds:dword_0[r11*4]\nlea eax, [r12-1]\ncmp r13d, 2\njbe loc_16C5\nmov edx, r8d\nmovd xmm5, eax\npcmpeqd xmm3, xmm3\nmov eax, 4\nshr edx, 2\npshufd xmm2, xmm5, 0\nshl rdx, 4\nadd rdx, 4\nnop dword ptr [rax]\nloc_1590:\nmovdqu xmm0, xmmword ptr [r9+rax]\nmovdqu xmm4, xmmword ptr [rsi+rax]\nadd rax, 10h\npaddd xmm0, xmm4\npaddd xmm0, xmm3\nmovdqa xmm1, xmm0\npcmpgtd xmm1, xmm2\npand xmm0, xmm1\npandn xmm1, xmm2\nmovdqa xmm2, xmm1\npor xmm2, xmm0\ncmp rdx, rax\njnz short loc_1590\nmovdqa xmm1, xmm2\nmov ecx, r8d\npsrldq xmm1, 8\nand ecx, 0FFFFFFFCh\nmovdqa xmm0, xmm1\nadd ecx, 1\nand r8d, 3\npcmpgtd xmm0, xmm2\npand xmm1, xmm0\npandn xmm0, xmm2\npor xmm0, xmm1\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\nmovdqa xmm1, xmm2\npcmpgtd xmm1, xmm0\npand xmm2, xmm1\npandn xmm1, xmm0\npor xmm1, xmm2\nmovd eax, xmm1\njz short loc_1656\nloc_1611:\nmovsxd rdx, ecx\nshl rdx, 2\nadd rsi, rdx\nadd rdx, r9\nmov edi, [rsi]\nadd edi, [rdx]\nsub edi, 1\ncmp eax, edi\ncmovl eax, edi\nlea edi, [rcx+1]\ncmp r10d, edi\njle short loc_1656\nmov edi, [rdx+4]\nadd edi, [rsi+4]\nsub edi, 1\ncmp eax, edi\ncmovl eax, edi\nadd ecx, 2\ncmp r10d, ecx\njle short loc_1656\nmov edx, [rdx+8]\nadd edx, [rsi+8]\nsub edx, 1\ncmp eax, edx\ncmovl eax, edx\nloc_1656:\nmov rdx, [rbp+var_28]\nsub rdx, fs:28h\njnz loc_172A\nlea rsp, [rbp-20h]\npop rbx\npop r12\npop r13\npop r14\npop rbp\nretn\nloc_1676:\nor [rsp+rdx+1030h+var_1038], 0\njmp loc_1356\nloc_1681:\nmov eax, ds:dword_0[r12*4]\nadd eax, ds:dword_0[r11*4]\nsub eax, 1\njmp short loc_1656\nloc_1696:\nmov ds:dword_0[r12*4], 1\ntest r10d, r10d\njz short loc_171C\nmov dword ptr ds:byte_4[r12*4], 1\ncmp r10d, 2\njnz loc_1486\nmov rdx, rsi\njmp loc_1433\nloc_16C5:\nmov ecx, 1\njmp loc_1611\nloc_16CF:\nmov ds:dword_0[r11*4], 1\ntest r10d, r10d\njz short loc_16F9\nmov dword ptr ds:byte_4[r11*4], 1\nmov rdx, r9\ncmp r10d, 2\njz loc_14FB\nloc_16F9:\nmov eax, ds:dword_0[r12*4]\nadd eax, ds:dword_0[r11*4]\nsub eax, 1\njmp loc_1656\nloc_1711:\nor [rsp+rdx+2030h+var_2038], 0\njmp loc_13A5\nloc_171C:\nmov ds:dword_0[r11*4], 1\njmp short loc_16F9\nloc_172A:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // ebx\n __int64 v4; // rax\n __m128i *v5; // rcx\n signed __int64 v6; // rdx\n void *v7; // rsp\n __m128i *v8; // rcx\n signed __int64 v9; // rdx\n void *v10; // rsp\n __m128i si128; // xmm0\n __m128i *v12; // rax\n __int64 v13; // rdx\n __m128i *v14; // rcx\n signed int v15; // eax\n __m128i *v16; // rdx\n __int64 v17; // rdx\n int v18; // r8d\n unsigned __int64 v19; // rax\n __int32 v20; // ecx\n __m128i v21; // xmm0\n __m128i *v22; // rax\n __int64 v23; // rdx\n __m128i *v24; // rcx\n signed int v25; // eax\n __m128i *v26; // rdx\n int v27; // r8d\n __int32 v28; // r12d\n __int64 v29; // rax\n int v30; // ebx\n __int64 v31; // rdx\n __int32 v32; // ecx\n __int64 result; // rax\n __m128i v34; // xmm5\n __int64 v35; // rax\n __m128i v36; // xmm2\n __m128i v37; // xmm0\n __m128i v38; // xmm4\n __m128i v39; // xmm0\n __m128i v40; // xmm1\n __m128i v41; // xmm1\n signed int v42; // ecx\n __m128i v43; // xmm0\n __m128i v44; // xmm0\n __m128i v45; // xmm2\n __m128i v46; // xmm1\n __int64 v47; // rdx\n __int32 *v48; // rsi\n __int32 *v49; // rdx\n int v50; // edi\n int v51; // edi\n int v52; // edx\n __int64 v53; // [rsp+0h] [rbp-2038h]\n __m128i v54; // [rsp+8h] [rbp-2030h] BYREF\n _BYTE v55[4080]; // [rsp+18h] [rbp-2020h] BYREF\n __m128i v56; // [rsp+1008h] [rbp-1030h] BYREF\n _BYTE v57[4072]; // [rsp+1018h] [rbp-1020h] BYREF\n _QWORD v58[6]; // [rsp+2008h] [rbp-30h] BYREF\n\n v3 = a2 + 1;\n v58[1] = __readfsqword(0x28u);\n v4 = 4LL * (a2 + 1) + 15;\n v5 = (__m128i *)((char *)v58 - (v4 & 0xFFFFFFFFFFFFF000LL));\n if ( v58 != (_QWORD *)v5 )\n {\n while ( &v56 != v5 )\n ;\n }\n v6 = (4 * ((_WORD)a2 + 1) + 15) & 0xFF0;\n v7 = alloca(v6);\n if ( ((4 * ((_WORD)a2 + 1) + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v55[v6 + 4072] = *(_QWORD *)&v55[v6 + 4072];\n v8 = (__m128i *)((char *)&v56 - (v4 & 0xFFFFFFFFFFFFF000LL));\n if ( &v56 != v8 )\n {\n while ( &v54 != v8 )\n ;\n }\n v9 = (4 * (_WORD)v3 + 15) & 0xFF0;\n v10 = alloca(v9);\n if ( ((4 * (_WORD)v3 + 15) & 0xFF0) != 0 )\n *(__int64 *)((char *)&v53 + v9) = *(__int64 *)((char *)&v53 + v9);\n if ( a2 < 0 )\n return (unsigned int)(v54.m128i_i32[0] + v56.m128i_i32[0] - 1);\n if ( (unsigned int)a2 > 2 )\n {\n si128 = _mm_load_si128((const __m128i *)&xmmword_20D0);\n v12 = &v56;\n v13 = 16LL * (v3 >> 2);\n v14 = (__m128i *)((char *)&v56 + v13);\n if ( (v13 & 0x10) == 0 || (v12 = (__m128i *)v57, v56 = si128, v57 != (_BYTE *)v14) )\n {\n do\n {\n *v12 = si128;\n v12 += 2;\n v12[-1] = si128;\n }\n while ( v12 != v14 );\n }\n v15 = v3 & 0xFFFFFFFC;\n if ( (v3 & 3) == 0 )\n goto LABEL_18;\n v16 = (__m128i *)((char *)&v56 + 4 * v15);\n v16->m128i_i32[0] = 1;\n if ( a2 <= v15 )\n goto LABEL_18;\n v16->m128i_i32[1] = 1;\n if ( a2 < v15 + 2 )\n goto LABEL_18;\n goto LABEL_17;\n }\n v56.m128i_i32[0] = 1;\n if ( !a2 )\n {\n v54.m128i_i32[0] = 1;\n return (unsigned int)(v54.m128i_i32[0] + v56.m128i_i32[0] - 1);\n }\n v56.m128i_i32[1] = 1;\n if ( a2 == 2 )\n {\n v16 = &v56;\nLABEL_17:\n v16->m128i_i32[2] = 1;\nLABEL_18:\n v17 = 4LL;\n do\n {\n v18 = *(_DWORD *)(a1 + v17);\n v19 = 0LL;\n do\n {\n if ( v18 > *(_DWORD *)(a1 + v19) )\n {\n v20 = v56.m128i_i32[v19 / 4];\n if ( v20 >= v56.m128i_i32[(unsigned __int64)v17 / 4] )\n v56.m128i_i32[(unsigned __int64)v17 / 4] = v20 + 1;\n }\n v19 += 4LL;\n }\n while ( v19 != v17 );\n v17 += 4LL;\n }\n while ( v17 != 4LL * (unsigned int)a2 );\n }\n if ( (unsigned int)a2 <= 2 )\n {\n v54.m128i_i32[0] = 1;\n v54.m128i_i32[1] = 1;\n v26 = &v54;\n if ( a2 == 2 )\n {\nLABEL_32:\n v26->m128i_i32[2] = 1;\n goto LABEL_33;\n }\n return (unsigned int)(v54.m128i_i32[0] + v56.m128i_i32[0] - 1);\n }\n v21 = _mm_load_si128((const __m128i *)&xmmword_20D0);\n v22 = &v54;\n v23 = 16LL * (v3 >> 2);\n v24 = (__m128i *)((char *)&v54 + v23);\n if ( (v23 & 0x10) == 0 || (v22 = (__m128i *)v55, v54 = v21, v24 != (__m128i *)v55) )\n {\n do\n {\n *v22 = v21;\n v22 += 2;\n v22[-1] = v21;\n }\n while ( v24 != v22 );\n }\n v25 = v3 & 0xFFFFFFFC;\n if ( (v3 & 3) != 0 )\n {\n v26 = (__m128i *)((char *)&v54 + 4 * v25);\n v26->m128i_i32[0] = 1;\n if ( a2 > v25 )\n {\n v26->m128i_i32[1] = 1;\n if ( a2 >= v25 + 2 )\n goto LABEL_32;\n }\n }\nLABEL_33:\n v27 = a2 - 1;\n v28 = v56.m128i_i32[0];\n v29 = a2 - 2;\n do\n {\n v30 = *(_DWORD *)(a1 + 4 * v29);\n v31 = v27;\n do\n {\n if ( *(_DWORD *)(a1 + 4 * v31) < v30 )\n {\n v32 = v54.m128i_i32[v31];\n if ( v54.m128i_i32[v29] <= v32 )\n v54.m128i_i32[v29] = v32 + 1;\n }\n --v31;\n }\n while ( (int)v29 < (int)v31 );\n --v29;\n }\n while ( (int)v29 >= 0 );\n result = (unsigned int)(v54.m128i_i32[0] + v28 - 1);\n if ( (unsigned int)(a2 - 2) <= 2 )\n {\n v42 = 1;\n }\n else\n {\n v34 = _mm_cvtsi32_si128(result);\n v35 = 4LL;\n v36 = _mm_shuffle_epi32(v34, 0);\n do\n {\n v37 = _mm_loadu_si128((__m128i *)((char *)&v54 + v35));\n v38 = _mm_loadu_si128((__m128i *)((char *)&v56 + v35));\n v35 += 16LL;\n v39 = _mm_add_epi32(_mm_add_epi32(v37, v38), (__m128i)-1LL);\n v40 = _mm_cmpgt_epi32(v39, v36);\n v36 = _mm_or_si128(_mm_andnot_si128(v40, v36), _mm_and_si128(v39, v40));\n }\n while ( 16LL * ((unsigned int)v27 >> 2) + 4 != v35 );\n v41 = _mm_srli_si128(v36, 8);\n v42 = (v27 & 0xFFFFFFFC) + 1;\n v43 = _mm_cmpgt_epi32(v41, v36);\n v44 = _mm_or_si128(_mm_andnot_si128(v43, v36), _mm_and_si128(v41, v43));\n v45 = _mm_srli_si128(v44, 4);\n v46 = _mm_cmpgt_epi32(v45, v44);\n result = (unsigned int)_mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v46, v44), _mm_and_si128(v45, v46)));\n if ( (v27 & 3) == 0 )\n return result;\n }\n v47 = v42;\n v48 = &v56.m128i_i32[v47];\n v49 = &v54.m128i_i32[v47];\n v50 = *v49 + *v48 - 1;\n if ( (int)result < v50 )\n result = (unsigned int)v50;\n if ( a2 > v42 + 1 )\n {\n v51 = v48[1] + v49[1] - 1;\n if ( (int)result < v51 )\n result = (unsigned int)v51;\n if ( a2 > v42 + 2 )\n {\n v52 = v48[2] + v49[2] - 1;\n if ( (int)result < v52 )\n return (unsigned int)v52;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\npush rbp\nmov r10d, esi\nmov rbp, rsp\npush r14\npush r13\npush r12\npush rbx\nlea ebx, [rsi+1]\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nmovsxd rax, ebx\nmov rcx, rsp\nlea rax, ds:0Fh[rax*4]\nmov rsi, rax\nmov rdx, rax\nand rsi, 0FFFFFFFFFFFFF000h\nand rdx, 0FFFFFFFFFFFFFFF0h\nsub rcx, rsi\ncmp rsp, rcx\njz short loc_1344\nloc_132F:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rcx\njnz short loc_132F\nloc_1344:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1676\nloc_1356:\nlea rsi, [rsp+1030h+var_102D]\nmov rdx, rax\nmov rcx, rsp\nand rax, 0FFFFFFFFFFFFF000h\nmov r12, rsi\nsub rcx, rax\nand rsi, 0FFFFFFFFFFFFFFFCh\nand rdx, 0FFFFFFFFFFFFFFF0h\nshr r12, 2\ncmp rsp, rcx\njz short loc_1393\nloc_137E:\nsub rsp, 1000h\nor [rsp+2030h+var_1038], 0\ncmp rsp, rcx\njnz short loc_137E\nloc_1393:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1711\nloc_13A5:\nlea r9, [rsp+2030h+var_202D]\nmov r11, r9\nand r9, 0FFFFFFFFFFFFFFFCh\nshr r11, 2\ntest r10d, r10d\njs loc_1681\ncmp r10d, 2\njbe loc_1696\nmov edx, ebx\nmovdqa xmm0, cs:xmmword_20D0\nmov rax, rsi\nshr edx, 2\nshl rdx, 4\nlea rcx, [rsi+rdx]\nand edx, 10h\njz short loc_13F8\nlea rax, [rsi+10h]\nmovups xmmword ptr [rsi], xmm0\ncmp rax, rcx\njz short loc_1408\nnop dword ptr [rax+00000000h]\nloc_13F8:\nmovups xmmword ptr [rax], xmm0\nadd rax, 20h ; ' '\nmovups xmmword ptr [rax-10h], xmm0\ncmp rax, rcx\njnz short loc_13F8\nloc_1408:\nmov eax, ebx\nand eax, 0FFFFFFFCh\ntest bl, 3\njz short loc_143A\nmovsxd rdx, eax\nlea rdx, [rsi+rdx*4]\nmov dword ptr [rdx], 1\ncmp r10d, eax\njle short loc_143A\nadd eax, 2\nmov dword ptr [rdx+4], 1\ncmp r10d, eax\njl short loc_143A\nloc_1433:\nmov dword ptr [rdx+8], 1\nloc_143A:\nmov r13d, r10d\nmov edx, 4\nshl r13, 2\nnop word ptr [rax+rax+00000000h]\nloc_1450:\nmov r8d, [rdi+rdx]\nxor eax, eax\nnop word ptr [rax+rax+00000000h]\nloc_1460:\ncmp r8d, [rdi+rax]\njle short loc_1474\nmov ecx, [rsi+rax]\ncmp ecx, [rsi+rdx]\njl short loc_1474\nadd ecx, 1\nmov [rsi+rdx], ecx\nloc_1474:\nadd rax, 4\ncmp rax, rdx\njnz short loc_1460\nadd rdx, 4\ncmp rdx, r13\njnz short loc_1450\nloc_1486:\ncmp r10d, 2\njbe loc_16CF\nmov edx, ebx\nmovdqa xmm0, cs:xmmword_20D0\nmov rax, r9\nshr edx, 2\nshl rdx, 4\nlea rcx, [r9+rdx]\nand edx, 10h\njz short loc_14C0\nlea rax, [r9+10h]\nmovups xmmword ptr [r9], xmm0\ncmp rcx, rax\njz short loc_14D0\nnop word ptr [rax+rax+00h]\nloc_14C0:\nmovups xmmword ptr [rax], xmm0\nadd rax, 20h ; ' '\nmovups xmmword ptr [rax-10h], xmm0\ncmp rcx, rax\njnz short loc_14C0\nloc_14D0:\nmov eax, ebx\nand eax, 0FFFFFFFCh\nand ebx, 3\njz short loc_1502\nmovsxd rdx, eax\nlea rdx, [r9+rdx*4]\nmov dword ptr [rdx], 1\ncmp r10d, eax\njle short loc_1502\nadd eax, 2\nmov dword ptr [rdx+4], 1\ncmp r10d, eax\njl short loc_1502\nloc_14FB:\nmov dword ptr [rdx+8], 1\nloc_1502:\nlea r13d, [r10-2]\nlea r8d, [r10-1]\nmov r12d, ds:dword_0[r12*4]\nmovsxd rax, r13d\nmovsxd r14, r8d\nnop dword ptr [rax+rax+00000000h]\nloc_1520:\nmov ebx, [rdi+rax*4]\nmov rdx, r14\nnop word ptr [rax+rax+00000000h]\nloc_1530:\ncmp [rdi+rdx*4], ebx\njge short loc_1546\nmov ecx, [r9+rdx*4]\ncmp [r9+rax*4], ecx\njg short loc_1546\nadd ecx, 1\nmov [r9+rax*4], ecx\nloc_1546:\nsub rdx, 1\ncmp eax, edx\njl short loc_1530\nsub rax, 1\ntest eax, eax\njns short loc_1520\nadd r12d, ds:dword_0[r11*4]\nlea eax, [r12-1]\ncmp r13d, 2\njbe loc_16C5\nmov edx, r8d\nmovd xmm5, eax\npcmpeqd xmm3, xmm3\nmov eax, 4\nshr edx, 2\npshufd xmm2, xmm5, 0\nshl rdx, 4\nadd rdx, 4\nnop dword ptr [rax]\nloc_1590:\nmovdqu xmm0, xmmword ptr [r9+rax]\nmovdqu xmm4, xmmword ptr [rsi+rax]\nadd rax, 10h\npaddd xmm0, xmm4\npaddd xmm0, xmm3\nmovdqa xmm1, xmm0\npcmpgtd xmm1, xmm2\npand xmm0, xmm1\npandn xmm1, xmm2\nmovdqa xmm2, xmm1\npor xmm2, xmm0\ncmp rdx, rax\njnz short loc_1590\nmovdqa xmm1, xmm2\nmov ecx, r8d\npsrldq xmm1, 8\nand ecx, 0FFFFFFFCh\nmovdqa xmm0, xmm1\nadd ecx, 1\nand r8d, 3\npcmpgtd xmm0, xmm2\npand xmm1, xmm0\npandn xmm0, xmm2\npor xmm0, xmm1\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\nmovdqa xmm1, xmm2\npcmpgtd xmm1, xmm0\npand xmm2, xmm1\npandn xmm1, xmm0\npor xmm1, xmm2\nmovd eax, xmm1\njz short loc_1656\nloc_1611:\nmovsxd rdx, ecx\nshl rdx, 2\nadd rsi, rdx\nadd rdx, r9\nmov edi, [rsi]\nadd edi, [rdx]\nsub edi, 1\ncmp eax, edi\ncmovl eax, edi\nlea edi, [rcx+1]\ncmp r10d, edi\njle short loc_1656\nmov edi, [rdx+4]\nadd edi, [rsi+4]\nsub edi, 1\ncmp eax, edi\ncmovl eax, edi\nadd ecx, 2\ncmp r10d, ecx\njle short loc_1656\nmov edx, [rdx+8]\nadd edx, [rsi+8]\nsub edx, 1\ncmp eax, edx\ncmovl eax, edx\nloc_1656:\nmov rdx, [rbp+var_28]\nsub rdx, fs:28h\njnz loc_172A\nlea rsp, [rbp-20h]\npop rbx\npop r12\npop r13\npop r14\npop rbp\nretn\nloc_1676:\nor [rsp+rdx+1030h+var_1038], 0\njmp loc_1356\nloc_1681:\nmov eax, ds:dword_0[r12*4]\nadd eax, ds:dword_0[r11*4]\nsub eax, 1\njmp short loc_1656\nloc_1696:\nmov ds:dword_0[r12*4], 1\ntest r10d, r10d\njz short loc_171C\nmov dword ptr ds:byte_4[r12*4], 1\ncmp r10d, 2\njnz loc_1486\nmov rdx, rsi\njmp loc_1433\nloc_16C5:\nmov ecx, 1\njmp loc_1611\nloc_16CF:\nmov ds:dword_0[r11*4], 1\ntest r10d, r10d\njz short loc_16F9\nmov dword ptr ds:byte_4[r11*4], 1\nmov rdx, r9\ncmp r10d, 2\njz loc_14FB\nloc_16F9:\nmov eax, ds:dword_0[r12*4]\nadd eax, ds:dword_0[r11*4]\nsub eax, 1\njmp loc_1656\nloc_1711:\nor [rsp+rdx+2030h+var_2038], 0\njmp loc_13A5\nloc_171C:\nmov ds:dword_0[r11*4], 1\njmp short loc_16F9\nloc_172A:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12E0(__int64 a1, int a2)\n{\n unsigned int v3; // ebx\n __int64 v4; // rax\n __m128i *v5; // rcx\n signed __int64 v6; // rdx\n void *v7; // rsp\n __m128i *v8; // rcx\n signed __int64 v9; // rdx\n void *v10; // rsp\n __m128i si128; // xmm0\n __m128i *v12; // rax\n __int64 v13; // rdx\n __m128i *v14; // rcx\n signed int v15; // eax\n __m128i *v16; // rdx\n __int64 v17; // rdx\n int v18; // r8d\n unsigned __int64 v19; // rax\n __int32 v20; // ecx\n __m128i v21; // xmm0\n __m128i *v22; // rax\n __int64 v23; // rdx\n __m128i *v24; // rcx\n signed int v25; // eax\n __m128i *v26; // rdx\n int v27; // r8d\n __int32 v28; // r12d\n __int64 v29; // rax\n int v30; // ebx\n __int64 v31; // rdx\n __int32 v32; // ecx\n __int64 result; // rax\n __m128i v34; // xmm5\n __int64 v35; // rax\n __m128i v36; // xmm2\n __m128i v37; // xmm0\n __m128i v38; // xmm4\n __m128i v39; // xmm0\n __m128i v40; // xmm1\n __m128i v41; // xmm1\n signed int v42; // ecx\n __m128i v43; // xmm0\n __m128i v44; // xmm0\n __m128i v45; // xmm2\n __m128i v46; // xmm1\n __int64 v47; // rdx\n __int32 *v48; // rsi\n __int32 *v49; // rdx\n int v50; // edi\n int v51; // edi\n int v52; // edx\n __int64 v53; // [rsp+0h] [rbp-2038h]\n __m128i v54; // [rsp+8h] [rbp-2030h] BYREF\n _BYTE v55[4080]; // [rsp+18h] [rbp-2020h] BYREF\n __m128i v56; // [rsp+1008h] [rbp-1030h] BYREF\n _BYTE v57[4072]; // [rsp+1018h] [rbp-1020h] BYREF\n _QWORD v58[6]; // [rsp+2008h] [rbp-30h] BYREF\n\n v3 = a2 + 1;\n v58[1] = __readfsqword(0x28u);\n v4 = 4LL * (a2 + 1) + 15;\n v5 = (__m128i *)((char *)v58 - (v4 & 0xFFFFFFFFFFFFF000LL));\n if ( v58 != (_QWORD *)v5 )\n {\n while ( &v56 != v5 )\n ;\n }\n v6 = (4 * ((_WORD)a2 + 1) + 15) & 0xFF0;\n v7 = alloca(v6);\n if ( ((4 * ((_WORD)a2 + 1) + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v55[v6 + 4072] = *(_QWORD *)&v55[v6 + 4072];\n v8 = (__m128i *)((char *)&v56 - (v4 & 0xFFFFFFFFFFFFF000LL));\n if ( &v56 != v8 )\n {\n while ( &v54 != v8 )\n ;\n }\n v9 = (4 * (_WORD)v3 + 15) & 0xFF0;\n v10 = alloca(v9);\n if ( ((4 * (_WORD)v3 + 15) & 0xFF0) != 0 )\n *(__int64 *)((char *)&v53 + v9) = *(__int64 *)((char *)&v53 + v9);\n if ( a2 < 0 )\n return (unsigned int)(v54.m128i_i32[0] + v56.m128i_i32[0] - 1);\n if ( (unsigned int)a2 > 2 )\n {\n si128 = _mm_load_si128((const __m128i *)&xmmword_20D0);\n v12 = &v56;\n v13 = 16LL * (v3 >> 2);\n v14 = (__m128i *)((char *)&v56 + v13);\n if ( (v13 & 0x10) == 0 || (v12 = (__m128i *)v57, v56 = si128, v57 != (_BYTE *)v14) )\n {\n do\n {\n *v12 = si128;\n v12 += 2;\n v12[-1] = si128;\n }\n while ( v12 != v14 );\n }\n v15 = v3 & 0xFFFFFFFC;\n if ( (v3 & 3) == 0 )\n goto LABEL_18;\n v16 = (__m128i *)((char *)&v56 + 4 * v15);\n v16->m128i_i32[0] = 1;\n if ( a2 <= v15 )\n goto LABEL_18;\n v16->m128i_i32[1] = 1;\n if ( a2 < v15 + 2 )\n goto LABEL_18;\n goto LABEL_17;\n }\n v56.m128i_i32[0] = 1;\n if ( !a2 )\n {\n v54.m128i_i32[0] = 1;\n return (unsigned int)(v54.m128i_i32[0] + v56.m128i_i32[0] - 1);\n }\n v56.m128i_i32[1] = 1;\n if ( a2 == 2 )\n {\n v16 = &v56;\nLABEL_17:\n v16->m128i_i32[2] = 1;\nLABEL_18:\n v17 = 4LL;\n do\n {\n v18 = *(_DWORD *)(a1 + v17);\n v19 = 0LL;\n do\n {\n if ( v18 > *(_DWORD *)(a1 + v19) )\n {\n v20 = v56.m128i_i32[v19 / 4];\n if ( v20 >= v56.m128i_i32[(unsigned __int64)v17 / 4] )\n v56.m128i_i32[(unsigned __int64)v17 / 4] = v20 + 1;\n }\n v19 += 4LL;\n }\n while ( v19 != v17 );\n v17 += 4LL;\n }\n while ( v17 != 4LL * (unsigned int)a2 );\n }\n if ( (unsigned int)a2 <= 2 )\n {\n v54.m128i_i32[0] = 1;\n v54.m128i_i32[1] = 1;\n v26 = &v54;\n if ( a2 == 2 )\n {\nLABEL_32:\n v26->m128i_i32[2] = 1;\n goto LABEL_33;\n }\n return (unsigned int)(v54.m128i_i32[0] + v56.m128i_i32[0] - 1);\n }\n v21 = _mm_load_si128((const __m128i *)&xmmword_20D0);\n v22 = &v54;\n v23 = 16LL * (v3 >> 2);\n v24 = (__m128i *)((char *)&v54 + v23);\n if ( (v23 & 0x10) == 0 || (v22 = (__m128i *)v55, v54 = v21, v24 != (__m128i *)v55) )\n {\n do\n {\n *v22 = v21;\n v22 += 2;\n v22[-1] = v21;\n }\n while ( v24 != v22 );\n }\n v25 = v3 & 0xFFFFFFFC;\n if ( (v3 & 3) != 0 )\n {\n v26 = (__m128i *)((char *)&v54 + 4 * v25);\n v26->m128i_i32[0] = 1;\n if ( a2 > v25 )\n {\n v26->m128i_i32[1] = 1;\n if ( a2 >= v25 + 2 )\n goto LABEL_32;\n }\n }\nLABEL_33:\n v27 = a2 - 1;\n v28 = v56.m128i_i32[0];\n v29 = a2 - 2;\n do\n {\n v30 = *(_DWORD *)(a1 + 4 * v29);\n v31 = v27;\n do\n {\n if ( *(_DWORD *)(a1 + 4 * v31) < v30 )\n {\n v32 = v54.m128i_i32[v31];\n if ( v54.m128i_i32[v29] <= v32 )\n v54.m128i_i32[v29] = v32 + 1;\n }\n --v31;\n }\n while ( (int)v29 < (int)v31 );\n --v29;\n }\n while ( (int)v29 >= 0 );\n result = (unsigned int)(v54.m128i_i32[0] + v28 - 1);\n if ( (unsigned int)(a2 - 2) <= 2 )\n {\n v42 = 1;\n }\n else\n {\n v34 = _mm_cvtsi32_si128(result);\n v35 = 4LL;\n v36 = _mm_shuffle_epi32(v34, 0);\n do\n {\n v37 = _mm_loadu_si128((__m128i *)((char *)&v54 + v35));\n v38 = _mm_loadu_si128((__m128i *)((char *)&v56 + v35));\n v35 += 16LL;\n v39 = _mm_add_epi32(_mm_add_epi32(v37, v38), (__m128i)-1LL);\n v40 = _mm_cmpgt_epi32(v39, v36);\n v36 = _mm_or_si128(_mm_andnot_si128(v40, v36), _mm_and_si128(v39, v40));\n }\n while ( 16LL * ((unsigned int)v27 >> 2) + 4 != v35 );\n v41 = _mm_srli_si128(v36, 8);\n v42 = (v27 & 0xFFFFFFFC) + 1;\n v43 = _mm_cmpgt_epi32(v41, v36);\n v44 = _mm_or_si128(_mm_andnot_si128(v43, v36), _mm_and_si128(v41, v43));\n v45 = _mm_srli_si128(v44, 4);\n v46 = _mm_cmpgt_epi32(v45, v44);\n result = (unsigned int)_mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v46, v44), _mm_and_si128(v45, v46)));\n if ( (v27 & 3) == 0 )\n return result;\n }\n v47 = v42;\n v48 = &v56.m128i_i32[v47];\n v49 = &v54.m128i_i32[v47];\n v50 = *v49 + *v48 - 1;\n if ( (int)result < v50 )\n result = (unsigned int)v50;\n if ( a2 > v42 + 1 )\n {\n v51 = v48[1] + v49[1] - 1;\n if ( (int)result < v51 )\n result = (unsigned int)v51;\n if ( a2 > v42 + 2 )\n {\n v52 = v48[2] + v49[2] - 1;\n if ( (int)result < v52 )\n return (unsigned int)v52;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12E0(long long a1, int a2) {\n unsigned int v3;\n long long v4;\n __m128i *v5;\n signed long long v6;\n void *v7;\n __m128i *v8;\n signed long long v9;\n void *v10;\n __m128i si128;\n __m128i *v12;\n long long v13;\n __m128i *v14;\n signed int v15;\n __m128i *v16;\n long long v17;\n int v18;\n unsigned long long v19;\n int v20;\n __m128i v21;\n __m128i *v22;\n long long v23;\n __m128i *v24;\n signed int v25;\n __m128i *v26;\n int v27;\n int v28;\n long long v29;\n int v30;\n long long v31;\n int v32;\n long long result;\n __m128i v34;\n long long v35;\n __m128i v36;\n __m128i v37;\n __m128i v38;\n __m128i v39;\n __m128i v40;\n __m128i v41;\n signed int v42;\n __m128i v43;\n __m128i v44;\n __m128i v45;\n __m128i v46;\n long long v47;\n int *v48;\n int *v49;\n int v50;\n int v51;\n int v52;\n long long v53;\n __m128i v54;\n uint8_t v55[4080];\n __m128i v56;\n uint8_t v57[4072];\n uint64_t v58[6];\n v3 = a2 + 1;\n v58[1] = __readfsqword(40u);\n v4 = 4LL * (a2 + 1) + 15;\n v5 = (__m128i *)((char *)v58 - (v4 & 18446744073709547520LL));\n if (v58 != (uint64_t *)v5) {\n while (&v56 != v5)\n ;\n }\n v6 = (4 * ((unsigned short)a2 + 1) + 15) & 4080;\n v7 = alloca(v6);\n if (((4 * ((unsigned short)a2 + 1) + 15) & 4080) != 0)\n *(uint64_t *)&v55[v6 + 4072] = *(uint64_t *)&v55[v6 + 4072];\n v8 = (__m128i *)((char *)&v56 - (v4 & 18446744073709547520LL));\n if (&v56 != v8) {\n while (&v54 != v8)\n ;\n }\n v9 = (4 * (unsigned short)v3 + 15) & 4080;\n v10 = alloca(v9);\n if (((4 * (unsigned short)v3 + 15) & 4080) != 0)\n *(long long *)((char *)&v53 + v9) = *(long long *)((char *)&v53 + v9);\n if (a2 < 0) return (unsigned int)(v54.m128i_i32[0] + v56.m128i_i32[0] - 1);\n if ((unsigned int)a2 > 2) {\n si128 = _mm_load_si128((const __m128i *)&xmmword_20D0);\n v12 = &v56;\n v13 = 16LL * (v3 >> 2);\n v14 = (__m128i *)((char *)&v56 + v13);\n if ((v13 & 16) == 0 ||\n (v12 = (__m128i *)v57, v56 = si128, v57 != (uint8_t *)v14)) {\n do {\n *v12 = si128;\n v12 += 2;\n v12[-1] = si128;\n } while (v12 != v14);\n }\n v15 = v3 & 4294967292;\n if ((v3 & 3) == 0) goto LABEL_18;\n v16 = (__m128i *)((char *)&v56 + 4 * v15);\n v16->m128i_i32[0] = 1;\n if (a2 <= v15) goto LABEL_18;\n v16->m128i_i32[1] = 1;\n if (a2 < v15 + 2) goto LABEL_18;\n goto LABEL_17;\n }\n v56.m128i_i32[0] = 1;\n if (!a2) {\n v54.m128i_i32[0] = 1;\n return (unsigned int)(v54.m128i_i32[0] + v56.m128i_i32[0] - 1);\n }\n v56.m128i_i32[1] = 1;\n if (a2 == 2) {\n v16 = &v56;\n LABEL_17:\n v16->m128i_i32[2] = 1;\n LABEL_18:\n v17 = 4LL;\n do {\n v18 = *(uint32_t *)(a1 + v17);\n v19 = 0LL;\n do {\n if (v18 > *(uint32_t *)(a1 + v19)) {\n v20 = v56.m128i_i32[v19 / 4];\n if (v20 >= v56.m128i_i32[(unsigned long long)v17 / 4])\n v56.m128i_i32[(unsigned long long)v17 / 4] = v20 + 1;\n }\n v19 += 4LL;\n } while (v19 != v17);\n v17 += 4LL;\n } while (v17 != 4LL * (unsigned int)a2);\n }\n if ((unsigned int)a2 <= 2) {\n v54.m128i_i32[0] = 1;\n v54.m128i_i32[1] = 1;\n v26 = &v54;\n if (a2 == 2) {\n LABEL_32:\n v26->m128i_i32[2] = 1;\n goto LABEL_33;\n }\n return (unsigned int)(v54.m128i_i32[0] + v56.m128i_i32[0] - 1);\n }\n v21 = _mm_load_si128((const __m128i *)&xmmword_20D0);\n v22 = &v54;\n v23 = 16LL * (v3 >> 2);\n v24 = (__m128i *)((char *)&v54 + v23);\n if ((v23 & 16) == 0 ||\n (v22 = (__m128i *)v55, v54 = v21, v24 != (__m128i *)v55)) {\n do {\n *v22 = v21;\n v22 += 2;\n v22[-1] = v21;\n } while (v24 != v22);\n }\n v25 = v3 & 4294967292;\n if ((v3 & 3) != 0) {\n v26 = (__m128i *)((char *)&v54 + 4 * v25);\n v26->m128i_i32[0] = 1;\n if (a2 > v25) {\n v26->m128i_i32[1] = 1;\n if (a2 >= v25 + 2) goto LABEL_32;\n }\n }\nLABEL_33:\n v27 = a2 - 1;\n v28 = v56.m128i_i32[0];\n v29 = a2 - 2;\n do {\n v30 = *(uint32_t *)(a1 + 4 * v29);\n v31 = v27;\n do {\n if (*(uint32_t *)(a1 + 4 * v31) < v30) {\n v32 = v54.m128i_i32[v31];\n if (v54.m128i_i32[v29] <= v32) v54.m128i_i32[v29] = v32 + 1;\n }\n --v31;\n } while ((int)v29 < (int)v31);\n --v29;\n } while ((int)v29 >= 0);\n result = (unsigned int)(v54.m128i_i32[0] + v28 - 1);\n if ((unsigned int)(a2 - 2) <= 2) {\n v42 = 1;\n } else {\n v34 = _mm_cvtsi32_si128(result);\n v35 = 4LL;\n v36 = _mm_shuffle_epi32(v34, 0);\n do {\n v37 = _mm_loadu_si128((__m128i *)((char *)&v54 + v35));\n v38 = _mm_loadu_si128((__m128i *)((char *)&v56 + v35));\n v35 += 16LL;\n v39 = _mm_add_epi32(_mm_add_epi32(v37, v38), (__m128i)-1LL);\n v40 = _mm_cmpgt_epi32(v39, v36);\n v36 = _mm_or_si128(_mm_andnot_si128(v40, v36), _mm_and_si128(v39, v40));\n } while (16LL * ((unsigned int)v27 >> 2) + 4 != v35);\n v41 = _mm_srli_si128(v36, 8);\n v42 = (v27 & 4294967292) + 1;\n v43 = _mm_cmpgt_epi32(v41, v36);\n v44 = _mm_or_si128(_mm_andnot_si128(v43, v36), _mm_and_si128(v41, v43));\n v45 = _mm_srli_si128(v44, 4);\n v46 = _mm_cmpgt_epi32(v45, v44);\n result = (unsigned int)_mm_cvtsi128_si32(\n _mm_or_si128(_mm_andnot_si128(v46, v44), _mm_and_si128(v45, v46)));\n if ((v27 & 3) == 0) return result;\n }\n v47 = v42;\n v48 = &v56.m128i_i32[v47];\n v49 = &v54.m128i_i32[v47];\n v50 = *v49 + *v48 - 1;\n if ((int)result < v50) result = (unsigned int)v50;\n if (a2 > v42 + 1) {\n v51 = v48[1] + v49[1] - 1;\n if ((int)result < v51) result = (unsigned int)v51;\n if (a2 > v42 + 2) {\n v52 = v48[2] + v49[2] - 1;\n if ((int)result < v52) return (unsigned int)v52;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n long long v4;\n __m128i *v5;\n signed long long v6;\n void *v7;\n __m128i *v8;\n signed long long v9;\n void *v10;\n __m128i si128;\n __m128i *v12;\n long long v13;\n __m128i *v14;\n signed int v15;\n __m128i *v16;\n long long v17;\n int v18;\n unsigned long long v19;\n int v20;\n __m128i v21;\n __m128i *v22;\n long long v23;\n __m128i *v24;\n signed int v25;\n __m128i *v26;\n int v27;\n int v28;\n long long v29;\n int v30;\n long long v31;\n int v32;\n long long result;\n __m128i v34;\n long long v35;\n __m128i v36;\n __m128i v37;\n __m128i v38;\n __m128i v39;\n __m128i v40;\n __m128i v41;\n signed int v42;\n __m128i v43;\n __m128i v44;\n __m128i v45;\n __m128i v46;\n long long v47;\n int *v48;\n int *v49;\n int v50;\n int v51;\n int v52;\n long long v53;\n __m128i v54;\n uint8_t v55[4080];\n __m128i v56;\n uint8_t v57[4072];\n uint64_t v58[6];\n v3 = a2 + 1;\n v58[1] = __readfsqword(40u);\n v4 = 4LL * (a2 + 1) + 15;\n v5 = (__m128i *)((char *)v58 - (v4 & 18446744073709547520LL));\n if (v58 != (uint64_t *)v5) {\n while (&v56 != v5)\n ;\n }\n v6 = (4 * ((unsigned short)a2 + 1) + 15) & 4080;\n v7 = alloca(v6);\n if (((4 * ((unsigned short)a2 + 1) + 15) & 4080) != 0)\n *(uint64_t *)&v55[v6 + 4072] = *(uint64_t *)&v55[v6 + 4072];\n v8 = (__m128i *)((char *)&v56 - (v4 & 18446744073709547520LL));\n if (&v56 != v8) {\n while (&v54 != v8)\n ;\n }\n v9 = (4 * (unsigned short)v3 + 15) & 4080;\n v10 = alloca(v9);\n if (((4 * (unsigned short)v3 + 15) & 4080) != 0)\n *(long long *)((char *)&v53 + v9) = *(long long *)((char *)&v53 + v9);\n if (a2 < 0) return (unsigned int)(v54.m128i_i32[0] + v56.m128i_i32[0] - 1);\n if ((unsigned int)a2 > 2) {\n si128 = _mm_load_si128((const __m128i *)&xmmword_20D0);\n v12 = &v56;\n v13 = 16LL * (v3 >> 2);\n v14 = (__m128i *)((char *)&v56 + v13);\n if ((v13 & 16) == 0 ||\n (v12 = (__m128i *)v57, v56 = si128, v57 != (uint8_t *)v14)) {\n do {\n *v12 = si128;\n v12 += 2;\n v12[-1] = si128;\n } while (v12 != v14);\n }\n v15 = v3 & 4294967292;\n if ((v3 & 3) == 0) goto LABEL_18;\n v16 = (__m128i *)((char *)&v56 + 4 * v15);\n v16->m128i_i32[0] = 1;\n if (a2 <= v15) goto LABEL_18;\n v16->m128i_i32[1] = 1;\n if (a2 < v15 + 2) goto LABEL_18;\n goto LABEL_17;\n }\n v56.m128i_i32[0] = 1;\n if (!a2) {\n v54.m128i_i32[0] = 1;\n return (unsigned int)(v54.m128i_i32[0] + v56.m128i_i32[0] - 1);\n }\n v56.m128i_i32[1] = 1;\n if (a2 == 2) {\n v16 = &v56;\n LABEL_17:\n v16->m128i_i32[2] = 1;\n LABEL_18:\n v17 = 4LL;\n do {\n v18 = *(uint32_t *)(a1 + v17);\n v19 = 0LL;\n do {\n if (v18 > *(uint32_t *)(a1 + v19)) {\n v20 = v56.m128i_i32[v19 / 4];\n if (v20 >= v56.m128i_i32[(unsigned long long)v17 / 4])\n v56.m128i_i32[(unsigned long long)v17 / 4] = v20 + 1;\n }\n v19 += 4LL;\n } while (v19 != v17);\n v17 += 4LL;\n } while (v17 != 4LL * (unsigned int)a2);\n }\n if ((unsigned int)a2 <= 2) {\n v54.m128i_i32[0] = 1;\n v54.m128i_i32[1] = 1;\n v26 = &v54;\n if (a2 == 2) {\n LABEL_32:\n v26->m128i_i32[2] = 1;\n goto LABEL_33;\n }\n return (unsigned int)(v54.m128i_i32[0] + v56.m128i_i32[0] - 1);\n }\n v21 = _mm_load_si128((const __m128i *)&xmmword_20D0);\n v22 = &v54;\n v23 = 16LL * (v3 >> 2);\n v24 = (__m128i *)((char *)&v54 + v23);\n if ((v23 & 16) == 0 ||\n (v22 = (__m128i *)v55, v54 = v21, v24 != (__m128i *)v55)) {\n do {\n *v22 = v21;\n v22 += 2;\n v22[-1] = v21;\n } while (v24 != v22);\n }\n v25 = v3 & 4294967292;\n if ((v3 & 3) != 0) {\n v26 = (__m128i *)((char *)&v54 + 4 * v25);\n v26->m128i_i32[0] = 1;\n if (a2 > v25) {\n v26->m128i_i32[1] = 1;\n if (a2 >= v25 + 2) goto LABEL_32;\n }\n }\nLABEL_33:\n v27 = a2 - 1;\n v28 = v56.m128i_i32[0];\n v29 = a2 - 2;\n do {\n v30 = *(uint32_t *)(a1 + 4 * v29);\n v31 = v27;\n do {\n if (*(uint32_t *)(a1 + 4 * v31) < v30) {\n v32 = v54.m128i_i32[v31];\n if (v54.m128i_i32[v29] <= v32) v54.m128i_i32[v29] = v32 + 1;\n }\n --v31;\n } while ((int)v29 < (int)v31);\n --v29;\n } while ((int)v29 >= 0);\n result = (unsigned int)(v54.m128i_i32[0] + v28 - 1);\n if ((unsigned int)(a2 - 2) <= 2) {\n v42 = 1;\n } else {\n v34 = _mm_cvtsi32_si128(result);\n v35 = 4LL;\n v36 = _mm_shuffle_epi32(v34, 0);\n do {\n v37 = _mm_loadu_si128((__m128i *)((char *)&v54 + v35));\n v38 = _mm_loadu_si128((__m128i *)((char *)&v56 + v35));\n v35 += 16LL;\n v39 = _mm_add_epi32(_mm_add_epi32(v37, v38), (__m128i)-1LL);\n v40 = _mm_cmpgt_epi32(v39, v36);\n v36 = _mm_or_si128(_mm_andnot_si128(v40, v36), _mm_and_si128(v39, v40));\n } while (16LL * ((unsigned int)v27 >> 2) + 4 != v35);\n v41 = _mm_srli_si128(v36, 8);\n v42 = (v27 & 4294967292) + 1;\n v43 = _mm_cmpgt_epi32(v41, v36);\n v44 = _mm_or_si128(_mm_andnot_si128(v43, v36), _mm_and_si128(v41, v43));\n v45 = _mm_srli_si128(v44, 4);\n v46 = _mm_cmpgt_epi32(v45, v44);\n result = (unsigned int)_mm_cvtsi128_si32(\n _mm_or_si128(_mm_andnot_si128(v46, v44), _mm_and_si128(v45, v46)));\n if ((v27 & 3) == 0) return result;\n }\n v47 = v42;\n v48 = &v56.m128i_i32[v47];\n v49 = &v54.m128i_i32[v47];\n v50 = *v49 + *v48 - 1;\n if ((int)result < v50) result = (unsigned int)v50;\n if (a2 > v42 + 1) {\n v51 = v48[1] + v49[1] - 1;\n if ((int)result < v51) result = (unsigned int)v51;\n if (a2 > v42 + 2) {\n v52 = v48[2] + v49[2] - 1;\n if ((int)result < v52) return (unsigned int)v52;\n }\n }\n return result;\n}" + }, + { + "index": 523, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char *func0(const char *str1) {\n static char result[200];\n int has_upper = 0, has_lower = 0, has_digit = 0, is_valid = 1;\n int length = strlen(str1);\n for (int i = 0; i < length; i++) {\n if (isupper(str1[i])) {\n has_upper = 1;\n }\n if (islower(str1[i])) {\n has_lower = 1;\n }\n if (isdigit(str1[i])) {\n has_digit = 1;\n }\n }\n result[0] = '\\0';\n if (!has_upper) {\n strcat(result, \"String must have 1 upper case character,\");\n }\n if (!has_lower) {\n strcat(result, \"String must have 1 lower case character,\");\n }\n if (!has_digit) {\n strcat(result, \"String must have 1 number,\");\n }\n if (length < 8) {\n strcat(result, \"String length should be atleast 8,\");\n }\n if (has_upper && has_lower && has_digit && length >= 8) {\n strcpy(result, \"Valid string.\");\n } else {\n int lastIdx = strlen(result) - 1;\n if (result[lastIdx] == ',') {\n result[lastIdx] = '\\0';\n }\n }\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"python\"), \"String must have 1 upper case character,String must have 1 number,String length should be atleast 8\") == 0);\n\n assert(strcmp(func0(\"123python\"), \"String must have 1 upper case character\") == 0);\n\n assert(strcmp(func0(\"123Python\"), \"Valid string.\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x28(%rbp)\nmovl $0x0,-0x1c(%rbp)\nmovl $0x0,-0x18(%rbp)\nmovl $0x0,-0x14(%rbp)\nmovl $0x1,-0xc(%rbp)\nmov -0x28(%rbp),%rax\nmov %rax,%rdi\ncallq 1080 \nmov %eax,-0x8(%rbp)\nmovl $0x0,-0x10(%rbp)\njmpq 129c \ncallq 10b0 <__ctype_b_loc@plt>\nmov (%rax),%rax\nmov -0x10(%rbp),%edx\nmovslq %edx,%rcx\nmov -0x28(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rdx),%edx\nmovsbq %dl,%rdx\nadd %rdx,%rdx\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x100,%eax\ntest %eax,%eax\nje 1228 \nmovl $0x1,-0x1c(%rbp)\ncallq 10b0 <__ctype_b_loc@plt>\nmov (%rax),%rax\nmov -0x10(%rbp),%edx\nmovslq %edx,%rcx\nmov -0x28(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rdx),%edx\nmovsbq %dl,%rdx\nadd %rdx,%rdx\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x200,%eax\ntest %eax,%eax\nje 1260 \nmovl $0x1,-0x18(%rbp)\ncallq 10b0 <__ctype_b_loc@plt>\nmov (%rax),%rax\nmov -0x10(%rbp),%edx\nmovslq %edx,%rcx\nmov -0x28(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rdx),%edx\nmovsbq %dl,%rdx\nadd %rdx,%rdx\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x800,%eax\ntest %eax,%eax\nje 1298 \nmovl $0x1,-0x14(%rbp)\naddl $0x1,-0x10(%rbp)\nmov -0x10(%rbp),%eax\ncmp -0x8(%rbp),%eax\njl 11f0 \nmovb $0x0,0x2d91(%rip)\ncmpl $0x0,-0x1c(%rbp)\njne 132d \nlea 0x2d84(%rip),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nlea 0x2d5f(%rip),%rax\nadd %rdx,%rax\nmovabs $0x6d20676e69727453,%rsi\nmovabs $0x6576616820747375,%rdi\nmov %rsi,(%rax)\nmov %rdi,0x8(%rax)\nmovabs $0x7265707075203120,%rsi\nmovabs $0x6863206573616320,%rdi\nmov %rsi,0x10(%rax)\nmov %rdi,0x18(%rax)\nmovabs $0x2c72657463617261,%rsi\nmov %rsi,0x20(%rax)\nmovb $0x0,0x28(%rax)\ncmpl $0x0,-0x18(%rbp)\njne 13ab \nlea 0x2d06(%rip),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nlea 0x2ce1(%rip),%rax\nadd %rdx,%rax\nmovabs $0x6d20676e69727453,%rsi\nmovabs $0x6576616820747375,%rdi\nmov %rsi,(%rax)\nmov %rdi,0x8(%rax)\nmovabs $0x7265776f6c203120,%rsi\nmovabs $0x6863206573616320,%rdi\nmov %rsi,0x10(%rax)\nmov %rdi,0x18(%rax)\nmovabs $0x2c72657463617261,%rsi\nmov %rsi,0x20(%rax)\nmovb $0x0,0x28(%rax)\ncmpl $0x0,-0x14(%rbp)\njne 1413 \nlea 0x2c88(%rip),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nlea 0x2c63(%rip),%rax\nadd %rdx,%rax\nmovabs $0x6d20676e69727453,%rsi\nmovabs $0x6576616820747375,%rdi\nmov %rsi,(%rax)\nmov %rdi,0x8(%rax)\nmovabs $0x65626d756e203120,%rsi\nmov %rsi,0x10(%rax)\nmovw $0x2c72,0x18(%rax)\nmovb $0x0,0x1a(%rax)\ncmpl $0x7,-0x8(%rbp)\njg 1489 \nlea 0x2c20(%rip),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nlea 0x2bfb(%rip),%rax\nadd %rdx,%rax\nmovabs $0x6c20676e69727453,%rsi\nmovabs $0x6873206874676e65,%rdi\nmov %rsi,(%rax)\nmov %rdi,0x8(%rax)\nmovabs $0x20656220646c756f,%rsi\nmovabs $0x20747361656c7461,%rdi\nmov %rsi,0x10(%rax)\nmov %rdi,0x18(%rax)\nmovw $0x2c38,0x20(%rax)\nmovb $0x0,0x22(%rax)\ncmpl $0x0,-0x1c(%rbp)\nje 14c7 \ncmpl $0x0,-0x18(%rbp)\nje 14c7 \ncmpl $0x0,-0x14(%rbp)\nje 14c7 \ncmpl $0x7,-0x8(%rbp)\njle 14c7 \nmovabs $0x74732064696c6156,%rax\nmov %rax,0x2b8e(%rip)\nmovl $0x676e6972,0x2b8c(%rip)\nmovw $0x2e,0x2b87(%rip)\njmp 14fd \nlea 0x2b72(%rip),%rdi\ncallq 1080 \nsub $0x1,%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncltq\nlea 0x2b5b(%rip),%rdx\nmovzbl (%rax,%rdx,1),%eax\ncmp $0x2c,%al\njne 14fd \nmov -0x4(%rbp),%eax\ncltq\nlea 0x2b47(%rip),%rdx\nmovb $0x0,(%rax,%rdx,1)\nlea 0x2b3c(%rip),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov [rbp+var_1C], 0\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\nmov [rbp+var_C], 1\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_8], eax\nmov [rbp+var_10], 0\njmp loc_129C\nloc_11F0:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_10]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 100h\ntest eax, eax\njz short loc_1228\nmov [rbp+var_1C], 1\nloc_1228:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_10]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 200h\ntest eax, eax\njz short loc_1260\nmov [rbp+var_18], 1\nloc_1260:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_10]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 800h\ntest eax, eax\njz short loc_1298\nmov [rbp+var_14], 1\nloc_1298:\nadd [rbp+var_10], 1\nloc_129C:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_8]\njl loc_11F0\nmov byte ptr cs:result_1, 0\ncmp [rbp+var_1C], 0\njnz short loc_1324\nlea rax, result_1\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nlea rax, result_1\nadd rax, rdx\nmov rsi, 6D20676E69727453h\nmov rdi, 6576616820747375h\nmov [rax], rsi\nmov [rax+8], rdi\nmov rsi, 7265707075203120h\nmov rdi, 6863206573616320h\nmov [rax+10h], rsi\nmov [rax+18h], rdi\nmov rsi, 6168632065736163h\nmov rdi, 2C726574636172h\nmov [rax+19h], rsi\nmov [rax+21h], rdi\nloc_1324:\ncmp [rbp+var_18], 0\njnz short loc_1399\nlea rax, result_1\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nlea rax, result_1\nadd rax, rdx\nmov rsi, 6D20676E69727453h\nmov rdi, 6576616820747375h\nmov [rax], rsi\nmov [rax+8], rdi\nmov rsi, 7265776F6C203120h\nmov rdi, 6863206573616320h\nmov [rax+10h], rsi\nmov [rax+18h], rdi\nmov rsi, 6168632065736163h\nmov rdi, 2C726574636172h\nmov [rax+19h], rsi\nmov [rax+21h], rdi\nloc_1399:\ncmp [rbp+var_14], 0\njnz short loc_13F2\nlea rax, result_1\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nlea rax, result_1\nadd rax, rdx\nmov rsi, 6D20676E69727453h\nmov rdi, 6576616820747375h\nmov [rax], rsi\nmov [rax+8], rdi\nmov rsi, 2031206576616820h\nmov rdi, 2C7265626D756Eh\nmov [rax+0Bh], rsi\nmov [rax+13h], rdi\nloc_13F2:\ncmp [rbp+var_8], 7\njg short loc_1452\nlea rax, result_1\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nlea rax, result_1\nadd rax, rdx\nmov rsi, 6C20676E69727453h\nmov rdi, 6873206874676E65h\nmov [rax], rsi\nmov [rax+8], rdi\nmov rsi, 20656220646C756Fh\nmov rdi, 20747361656C7461h\nmov [rax+10h], rsi\nmov [rax+18h], rdi\nmov dword ptr [rax+1Fh], 2C3820h\nloc_1452:\ncmp [rbp+var_1C], 0\njz short loc_148E\ncmp [rbp+var_18], 0\njz short loc_148E\ncmp [rbp+var_14], 0\njz short loc_148E\ncmp [rbp+var_8], 7\njle short loc_148E\nmov rax, 74732064696C6156h\nmov cs:result_1, rax\nmov rax, 2E676E69727473h\nmov cs:result_1+6, rax\njmp short loc_14C7\nloc_148E:\nlea rax, result_1\nmov rdi, rax; s\ncall _strlen\nsub eax, 1\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, result_1\nmovzx eax, byte ptr [rax+rdx]\ncmp al, 2Ch ; ','\njnz short loc_14C7\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, result_1\nmov byte ptr [rax+rdx], 0\nloc_14C7:\nlea rax, result_1\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(const char *a1)\n{\n int v2; // [rsp+14h] [rbp-1Ch]\n int v3; // [rsp+18h] [rbp-18h]\n int v4; // [rsp+1Ch] [rbp-14h]\n int i; // [rsp+20h] [rbp-10h]\n int v6; // [rsp+28h] [rbp-8h]\n int v7; // [rsp+2Ch] [rbp-4h]\n\n v2 = 0;\n v3 = 0;\n v4 = 0;\n v6 = strlen(a1);\n for ( i = 0; i < v6; ++i )\n {\n if ( ((*__ctype_b_loc())[a1[i]] & 0x100) != 0 )\n v2 = 1;\n if ( ((*__ctype_b_loc())[a1[i]] & 0x200) != 0 )\n v3 = 1;\n if ( ((*__ctype_b_loc())[a1[i]] & 0x800) != 0 )\n v4 = 1;\n }\n result_1[0] = 0;\n if ( !v2 )\n strcpy(&result_1[strlen(result_1)], \"String must have 1 upper case character,\");\n if ( !v3 )\n strcpy(&result_1[strlen(result_1)], \"String must have 1 lower case character,\");\n if ( !v4 )\n strcpy(&result_1[strlen(result_1)], \"String must have 1 number,\");\n if ( v6 <= 7 )\n strcpy(&result_1[strlen(result_1)], \"String length should be atleast 8,\");\n if ( v2 && v3 && v4 && v6 > 7 )\n {\n strcpy(result_1, \"Valid string.\");\n }\n else\n {\n v7 = strlen(result_1) - 1;\n if ( result_1[v7] == 44 )\n result_1[v7] = 0;\n }\n return result_1;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov [rbp+var_1C], 0\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\nmov [rbp+var_C], 1\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_8], eax\nmov [rbp+var_10], 0\njmp loc_129C\nloc_11F0:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_10]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 100h\ntest eax, eax\njz short loc_1228\nmov [rbp+var_1C], 1\nloc_1228:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_10]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 200h\ntest eax, eax\njz short loc_1260\nmov [rbp+var_18], 1\nloc_1260:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_10]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 800h\ntest eax, eax\njz short loc_1298\nmov [rbp+var_14], 1\nloc_1298:\nadd [rbp+var_10], 1\nloc_129C:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_8]\njl loc_11F0\nmov byte ptr cs:s, 0\ncmp [rbp+var_1C], 0\njnz short loc_1324\nlea rax, s\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nlea rax, s\nadd rax, rdx\nmov rsi, 6D20676E69727453h\nmov rdi, 6576616820747375h\nmov [rax], rsi\nmov [rax+8], rdi\nmov rsi, 7265707075203120h\nmov rdi, 6863206573616320h\nmov [rax+10h], rsi\nmov [rax+18h], rdi\nmov rsi, 6168632065736163h\nmov rdi, 2C726574636172h\nmov [rax+19h], rsi\nmov [rax+21h], rdi\nloc_1324:\ncmp [rbp+var_18], 0\njnz short loc_1399\nlea rax, s\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nlea rax, s\nadd rax, rdx\nmov rsi, 6D20676E69727453h\nmov rdi, 6576616820747375h\nmov [rax], rsi\nmov [rax+8], rdi\nmov rsi, 7265776F6C203120h\nmov rdi, 6863206573616320h\nmov [rax+10h], rsi\nmov [rax+18h], rdi\nmov rsi, 6168632065736163h\nmov rdi, 2C726574636172h\nmov [rax+19h], rsi\nmov [rax+21h], rdi\nloc_1399:\ncmp [rbp+var_14], 0\njnz short loc_13F2\nlea rax, s\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nlea rax, s\nadd rax, rdx\nmov rsi, 6D20676E69727453h\nmov rdi, 6576616820747375h\nmov [rax], rsi\nmov [rax+8], rdi\nmov rsi, 2031206576616820h\nmov rdi, 2C7265626D756Eh\nmov [rax+0Bh], rsi\nmov [rax+13h], rdi\nloc_13F2:\ncmp [rbp+var_8], 7\njg short loc_1452\nlea rax, s\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nlea rax, s\nadd rax, rdx\nmov rsi, 6C20676E69727453h\nmov rdi, 6873206874676E65h\nmov [rax], rsi\nmov [rax+8], rdi\nmov rsi, 20656220646C756Fh\nmov rdi, 20747361656C7461h\nmov [rax+10h], rsi\nmov [rax+18h], rdi\nmov dword ptr [rax+1Fh], 2C3820h\nloc_1452:\ncmp [rbp+var_1C], 0\njz short loc_148E\ncmp [rbp+var_18], 0\njz short loc_148E\ncmp [rbp+var_14], 0\njz short loc_148E\ncmp [rbp+var_8], 7\njle short loc_148E\nmov rax, 74732064696C6156h\nmov cs:s, rax\nmov rax, 2E676E69727473h\nmov cs:s+6, rax\njmp short loc_14C7\nloc_148E:\nlea rax, s\nmov rdi, rax; s\ncall _strlen\nsub eax, 1\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, s\nmovzx eax, byte ptr [rax+rdx]\ncmp al, 2Ch ; ','\njnz short loc_14C7\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, s\nmov byte ptr [rax+rdx], 0\nloc_14C7:\nlea rax, s\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11A9(const char *a1)\n{\n int v2; // [rsp+14h] [rbp-1Ch]\n int v3; // [rsp+18h] [rbp-18h]\n int v4; // [rsp+1Ch] [rbp-14h]\n int i; // [rsp+20h] [rbp-10h]\n int v6; // [rsp+28h] [rbp-8h]\n int v7; // [rsp+2Ch] [rbp-4h]\n\n v2 = 0;\n v3 = 0;\n v4 = 0;\n v6 = strlen(a1);\n for ( i = 0; i < v6; ++i )\n {\n if ( ((*__ctype_b_loc())[a1[i]] & 0x100) != 0 )\n v2 = 1;\n if ( ((*__ctype_b_loc())[a1[i]] & 0x200) != 0 )\n v3 = 1;\n if ( ((*__ctype_b_loc())[a1[i]] & 0x800) != 0 )\n v4 = 1;\n }\n s[0] = 0;\n if ( !v2 )\n strcpy(&s[strlen(s)], \"String must have 1 upper case character,\");\n if ( !v3 )\n strcpy(&s[strlen(s)], \"String must have 1 lower case character,\");\n if ( !v4 )\n strcpy(&s[strlen(s)], \"String must have 1 number,\");\n if ( v6 <= 7 )\n strcpy(&s[strlen(s)], \"String length should be atleast 8,\");\n if ( v2 && v3 && v4 && v6 > 7 )\n {\n strcpy(s, \"Valid string.\");\n }\n else\n {\n v7 = strlen(s) - 1;\n if ( s[v7] == 44 )\n s[v7] = 0;\n }\n return s;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11A9(const char *a1) {\n int v2;\n int v3;\n int v4;\n int i;\n int v6;\n int v7;\n v2 = 0;\n v3 = 0;\n v4 = 0;\n v6 = strlen(a1);\n for (i = 0; i < v6; ++i) {\n if (((*__ctype_b_loc())[a1[i]] & 256) != 0) v2 = 1;\n if (((*__ctype_b_loc())[a1[i]] & 512) != 0) v3 = 1;\n if (((*__ctype_b_loc())[a1[i]] & 2048) != 0) v4 = 1;\n }\n s[0] = 0;\n if (!v2) strcpy(&s[strlen(s)], \"String must have 1 upper case character,\");\n if (!v3) strcpy(&s[strlen(s)], \"String must have 1 lower case character,\");\n if (!v4) strcpy(&s[strlen(s)], \"String must have 1 number,\");\n if (v6 <= 7) strcpy(&s[strlen(s)], \"String length should be atleast 8,\");\n if (v2 && v3 && v4 && v6 > 7) {\n strcpy(s, \"Valid string.\");\n } else {\n v7 = strlen(s) - 1;\n if (s[v7] == 44) s[v7] = 0;\n }\n return s;\n}", + "ida_pseudo_norm": "char *func0(const char *a1) {\n int v2;\n int v3;\n int v4;\n int i;\n int v6;\n int v7;\n v2 = 0;\n v3 = 0;\n v4 = 0;\n v6 = strlen(a1);\n for (i = 0; i < v6; ++i) {\n if (((*__ctype_b_loc())[a1[i]] & 256) != 0) v2 = 1;\n if (((*__ctype_b_loc())[a1[i]] & 512) != 0) v3 = 1;\n if (((*__ctype_b_loc())[a1[i]] & 2048) != 0) v4 = 1;\n }\n result_1[0] = 0;\n if (!v2)\n strcpy(&result_1[strlen(result_1)],\n \"String must have 1 upper case character,\");\n if (!v3)\n strcpy(&result_1[strlen(result_1)],\n \"String must have 1 lower case character,\");\n if (!v4) strcpy(&result_1[strlen(result_1)], \"String must have 1 number,\");\n if (v6 <= 7)\n strcpy(&result_1[strlen(result_1)], \"String length should be atleast 8,\");\n if (v2 && v3 && v4 && v6 > 7) {\n strcpy(result_1, \"Valid string.\");\n } else {\n v7 = strlen(result_1) - 1;\n if (result_1[v7] == 44) result_1[v7] = 0;\n }\n return result_1;\n}" + }, + { + "index": 523, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char *func0(const char *str1) {\n static char result[200];\n int has_upper = 0, has_lower = 0, has_digit = 0, is_valid = 1;\n int length = strlen(str1);\n for (int i = 0; i < length; i++) {\n if (isupper(str1[i])) {\n has_upper = 1;\n }\n if (islower(str1[i])) {\n has_lower = 1;\n }\n if (isdigit(str1[i])) {\n has_digit = 1;\n }\n }\n result[0] = '\\0';\n if (!has_upper) {\n strcat(result, \"String must have 1 upper case character,\");\n }\n if (!has_lower) {\n strcat(result, \"String must have 1 lower case character,\");\n }\n if (!has_digit) {\n strcat(result, \"String must have 1 number,\");\n }\n if (length < 8) {\n strcat(result, \"String length should be atleast 8,\");\n }\n if (has_upper && has_lower && has_digit && length >= 8) {\n strcpy(result, \"Valid string.\");\n } else {\n int lastIdx = strlen(result) - 1;\n if (result[lastIdx] == ',') {\n result[lastIdx] = '\\0';\n }\n }\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"python\"), \"String must have 1 upper case character,String must have 1 number,String length should be atleast 8\") == 0);\n\n assert(strcmp(func0(\"123python\"), \"String must have 1 upper case character\") == 0);\n\n assert(strcmp(func0(\"123Python\"), \"Valid string.\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbx\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nlea -0x1(%rcx),%r13\ntest %r13d,%r13d\njle 12e1 \ncallq 1090 <__ctype_b_loc@plt>\nmov (%rax),%rdi\nmov %rbx,%rax\nlea -0x1(%r13),%edx\nlea 0x1(%rbx,%rdx,1),%rsi\nmov $0x0,%r12d\nmov $0x0,%ebp\nmov $0x0,%ebx\nmov $0x1,%ecx\nmovsbq (%rax),%rdx\nmovzwl (%rdi,%rdx,2),%edx\ntest $0x1,%dh\ncmovne %ecx,%ebx\ntest $0x2,%dh\ncmovne %ecx,%ebp\ntest $0x8,%dh\ncmovne %ecx,%r12d\nadd $0x1,%rax\ncmp %rsi,%rax\njne 11e1 \nmovb $0x0,0x2e34(%rip)\ntest %ebx,%ebx\nje 12f8 \ntest %ebp,%ebp\nje 1256 \ntest %r12d,%r12d\nje 1270 \ncmp $0x7,%r13d\njle 128a \ntest %ebx,%ebx\nje 12a2 \ntest %ebp,%ebp\nje 12a2 \ntest %r12d,%r12d\nje 12a2 \nmovabs $0x74732064696c6156,%rax\nmov %rax,0x2dff(%rip)\nmovl $0x676e6972,0x2dfd(%rip)\nmovw $0x2e,0x2df8(%rip)\njmp 12c9 \nmov $0xc8,%edx\nlea 0xdd6(%rip),%rsi\nlea 0x2dd7(%rip),%rdi\ncallq 1070 <__strcat_chk@plt>\njmp 1218 \nmov $0xc8,%edx\nlea 0xfed(%rip),%rsi\nlea 0x2dbd(%rip),%rdi\ncallq 1070 <__strcat_chk@plt>\njmp 121d \nmov $0xc8,%edx\nlea 0xdd2(%rip),%rsi\nlea 0x2da3(%rip),%rdi\ncallq 1070 <__strcat_chk@plt>\nlea 0x2d97(%rip),%rdx\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nnot %rcx\nsub $0x2,%ecx\nmovslq %ecx,%rax\ncmpb $0x2c,(%rdx,%rax,1)\nje 12db \nlea 0x2d70(%rip),%rax\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nmovb $0x0,(%rdx,%rax,1)\njmp 12c9 \nmovb $0x0,0x2d58(%rip)\nmov $0x0,%r12d\nmov $0x0,%ebp\nmov $0x0,%ebx\nmov $0xc8,%edx\nlea 0xd04(%rip),%rsi\nlea 0x2d35(%rip),%rdi\ncallq 1070 <__strcat_chk@plt>\njmpq 1214 \n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\ncall _strlen\nmov r13, rax\ntest eax, eax\njle loc_1305\ncall ___ctype_b_loc\nmov rdi, [rax]\nmov rax, rbx\nlea edx, [r13-1]\nlea rsi, [rbx+rdx+1]\nmov r12d, 0\nmov ebp, 0\nmov ebx, 0\nmov ecx, 1\nloc_1213:\nmovsx rdx, byte ptr [rax]\nmovzx edx, word ptr [rdi+rdx*2]\ntest dh, 1\ncmovnz ebx, ecx\ntest dh, 2\ncmovnz ebp, ecx\ntest dh, 8\ncmovnz r12d, ecx\nadd rax, 1\ncmp rax, rsi\njnz short loc_1213\nmov byte ptr cs:result_1, 0\ntest ebx, ebx\njz loc_1317\nloc_1246:\ntest ebp, ebp\njz short loc_1286\nloc_124A:\ntest r12d, r12d\njz short loc_12A0\nloc_124F:\ncmp r13d, 7\njle short loc_12BA\ntest ebx, ebx\njz short loc_12D2\ntest ebp, ebp\njz short loc_12D2\ntest r12d, r12d\njz short loc_12D2\nmov rax, 74732064696C6156h\nmov cs:result_1, rax\nmov rax, 2E676E69727473h\nmov cs:result_1+6, rax\njmp short loc_12ED\nloc_1286:\nmov edx, 0C8h\nlea rsi, aStringMustHave; \"String must have 1 lower case character\"...\nlea rdi, result_1\ncall ___strcat_chk\njmp short loc_124A\nloc_12A0:\nmov edx, 0C8h\nlea rsi, aStringMustHave_0; \"String must have 1 number,\"\nlea rdi, result_1\ncall ___strcat_chk\njmp short loc_124F\nloc_12BA:\nmov edx, 0C8h\nlea rsi, aStringLengthSh; \"String length should be atleast 8,\"\nlea rdi, result_1\ncall ___strcat_chk\nloc_12D2:\nlea rbx, result_1\nmov rdi, rbx; s\ncall _strlen\nsub eax, 1\nmovsxd rdx, eax\ncmp byte ptr [rbx+rdx], 2Ch ; ','\njz short loc_12FF\nloc_12ED:\nlea rax, result_1\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_12FF:\nmov byte ptr [rbx+rdx], 0\njmp short loc_12ED\nloc_1305:\nmov byte ptr cs:result_1, 0\nmov r12d, 0\nmov ebp, 0\nloc_1317:\nmov edx, 0C8h\nlea rsi, aStringMustHave_1; \"String must have 1 upper case character\"...\nlea rdi, result_1\ncall ___strcat_chk\nmov ebx, 0\njmp loc_1246", + "ida_pseudo": "char *__fastcall func0(const char *a1)\n{\n __int64 v2; // rcx\n int v3; // r13d\n const unsigned __int16 *v4; // rdi\n const char *v5; // rax\n __int64 v6; // rsi\n int v7; // r12d\n int v8; // ebp\n int v9; // ebx\n unsigned __int16 v10; // dx\n __int64 v11; // rdx\n\n v3 = strlen(a1);\n if ( v3 <= 0 )\n {\n result_1[0] = 0;\n v7 = 0;\n v8 = 0;\nLABEL_25:\n __strcat_chk(result_1, \"String must have 1 upper case character,\", 200LL, v2);\n v9 = 0;\n goto LABEL_11;\n }\n v4 = *__ctype_b_loc();\n v5 = a1;\n v6 = (__int64)&a1[v3 - 1 + 1];\n v7 = 0;\n v8 = 0;\n v9 = 0;\n v2 = 1LL;\n do\n {\n v10 = v4[*v5];\n if ( (v10 & 0x100) != 0 )\n v9 = 1;\n if ( (v10 & 0x200) != 0 )\n v8 = 1;\n if ( (v10 & 0x800) != 0 )\n v7 = 1;\n ++v5;\n }\n while ( v5 != (const char *)v6 );\n result_1[0] = 0;\n if ( !v9 )\n goto LABEL_25;\nLABEL_11:\n if ( !v8 )\n __strcat_chk(result_1, \"String must have 1 lower case character,\", 200LL, v2);\n if ( !v7 )\n __strcat_chk(result_1, \"String must have 1 number,\", 200LL, v2);\n if ( v3 <= 7 )\n {\n __strcat_chk(result_1, \"String length should be atleast 8,\", 200LL, v2);\n }\n else if ( v9 && v8 && v7 )\n {\n strcpy(result_1, \"Valid string.\");\n return result_1;\n }\n v11 = (int)(strlen(result_1) - 1);\n if ( result_1[v11] == 44 )\n result_1[v11] = 0;\n return result_1;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\ncall _strlen\nmov r13, rax\ntest eax, eax\njle loc_1305\ncall ___ctype_b_loc\nmov rdi, [rax]\nmov rax, rbx\nlea edx, [r13-1]\nlea rsi, [rbx+rdx+1]\nmov r12d, 0\nmov ebp, 0\nmov ebx, 0\nmov ecx, 1\nloc_1213:\nmovsx rdx, byte ptr [rax]\nmovzx edx, word ptr [rdi+rdx*2]\ntest dh, 1\ncmovnz ebx, ecx\ntest dh, 2\ncmovnz ebp, ecx\ntest dh, 8\ncmovnz r12d, ecx\nadd rax, 1\ncmp rax, rsi\njnz short loc_1213\nmov byte ptr cs:s, 0\ntest ebx, ebx\njz loc_1317\nloc_1246:\ntest ebp, ebp\njz short loc_1286\nloc_124A:\ntest r12d, r12d\njz short loc_12A0\nloc_124F:\ncmp r13d, 7\njle short loc_12BA\ntest ebx, ebx\njz short loc_12D2\ntest ebp, ebp\njz short loc_12D2\ntest r12d, r12d\njz short loc_12D2\nmov rax, 74732064696C6156h\nmov cs:s, rax\nmov rax, 2E676E69727473h\nmov cs:s+6, rax\njmp short loc_12ED\nloc_1286:\nmov edx, 0C8h\nlea rsi, aStringMustHave; \"String must have 1 lower case character\"...\nlea rdi, s\ncall ___strcat_chk\njmp short loc_124A\nloc_12A0:\nmov edx, 0C8h\nlea rsi, aStringMustHave_0; \"String must have 1 number,\"\nlea rdi, s\ncall ___strcat_chk\njmp short loc_124F\nloc_12BA:\nmov edx, 0C8h\nlea rsi, aStringLengthSh; \"String length should be atleast 8,\"\nlea rdi, s\ncall ___strcat_chk\nloc_12D2:\nlea rbx, s\nmov rdi, rbx; s\ncall _strlen\nsub eax, 1\nmovsxd rdx, eax\ncmp byte ptr [rbx+rdx], 2Ch ; ','\njz short loc_12FF\nloc_12ED:\nlea rax, s\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_12FF:\nmov byte ptr [rbx+rdx], 0\njmp short loc_12ED\nloc_1305:\nmov byte ptr cs:s, 0\nmov r12d, 0\nmov ebp, 0\nloc_1317:\nmov edx, 0C8h\nlea rsi, aStringMustHave_1; \"String must have 1 upper case character\"...\nlea rdi, s\ncall ___strcat_chk\nmov ebx, 0\njmp loc_1246", + "ida_strip_pseudo": "char *__fastcall sub_11C9(const char *a1)\n{\n __int64 v2; // rcx\n int v3; // r13d\n const unsigned __int16 *v4; // rdi\n const char *v5; // rax\n __int64 v6; // rsi\n int v7; // r12d\n int v8; // ebp\n int v9; // ebx\n unsigned __int16 v10; // dx\n __int64 v11; // rdx\n\n v3 = strlen(a1);\n if ( v3 <= 0 )\n {\n s[0] = 0;\n v7 = 0;\n v8 = 0;\nLABEL_25:\n __strcat_chk(s, \"String must have 1 upper case character,\", 200LL, v2);\n v9 = 0;\n goto LABEL_11;\n }\n v4 = *__ctype_b_loc();\n v5 = a1;\n v6 = (__int64)&a1[v3 - 1 + 1];\n v7 = 0;\n v8 = 0;\n v9 = 0;\n v2 = 1LL;\n do\n {\n v10 = v4[*v5];\n if ( (v10 & 0x100) != 0 )\n v9 = 1;\n if ( (v10 & 0x200) != 0 )\n v8 = 1;\n if ( (v10 & 0x800) != 0 )\n v7 = 1;\n ++v5;\n }\n while ( v5 != (const char *)v6 );\n s[0] = 0;\n if ( !v9 )\n goto LABEL_25;\nLABEL_11:\n if ( !v8 )\n __strcat_chk(s, \"String must have 1 lower case character,\", 200LL, v2);\n if ( !v7 )\n __strcat_chk(s, \"String must have 1 number,\", 200LL, v2);\n if ( v3 <= 7 )\n {\n __strcat_chk(s, \"String length should be atleast 8,\", 200LL, v2);\n }\n else if ( v9 && v8 && v7 )\n {\n strcpy(s, \"Valid string.\");\n return s;\n }\n v11 = (int)(strlen(s) - 1);\n if ( s[v11] == 44 )\n s[v11] = 0;\n return s;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11C9(const char *a1) {\n long long v2;\n int v3;\n const unsigned short *v4;\n const char *v5;\n long long v6;\n int v7;\n int v8;\n int v9;\n unsigned short v10;\n long long v11;\n v3 = strlen(a1);\n if (v3 <= 0) {\n s[0] = 0;\n v7 = 0;\n v8 = 0;\n LABEL_25:\n __strcat_chk(s, \"String must have 1 upper case character,\", 200LL, v2);\n v9 = 0;\n goto LABEL_11;\n }\n v4 = *__ctype_b_loc();\n v5 = a1;\n v6 = (long long)&a1[v3 - 1 + 1];\n v7 = 0;\n v8 = 0;\n v9 = 0;\n v2 = 1LL;\n do {\n v10 = v4[*v5];\n if ((v10 & 256) != 0) v9 = 1;\n if ((v10 & 512) != 0) v8 = 1;\n if ((v10 & 2048) != 0) v7 = 1;\n ++v5;\n } while (v5 != (const char *)v6);\n s[0] = 0;\n if (!v9) goto LABEL_25;\nLABEL_11:\n if (!v8)\n __strcat_chk(s, \"String must have 1 lower case character,\", 200LL, v2);\n if (!v7) __strcat_chk(s, \"String must have 1 number,\", 200LL, v2);\n if (v3 <= 7) {\n __strcat_chk(s, \"String length should be atleast 8,\", 200LL, v2);\n } else if (v9 && v8 && v7) {\n strcpy(s, \"Valid string.\");\n return s;\n }\n v11 = (int)(strlen(s) - 1);\n if (s[v11] == 44) s[v11] = 0;\n return s;\n}", + "ida_pseudo_norm": "char *func0(const char *a1) {\n long long v2;\n int v3;\n const unsigned short *v4;\n const char *v5;\n long long v6;\n int v7;\n int v8;\n int v9;\n unsigned short v10;\n long long v11;\n v3 = strlen(a1);\n if (v3 <= 0) {\n result_1[0] = 0;\n v7 = 0;\n v8 = 0;\n LABEL_25:\n __strcat_chk(result_1, \"String must have 1 upper case character,\", 200LL,\n v2);\n v9 = 0;\n goto LABEL_11;\n }\n v4 = *__ctype_b_loc();\n v5 = a1;\n v6 = (long long)&a1[v3 - 1 + 1];\n v7 = 0;\n v8 = 0;\n v9 = 0;\n v2 = 1LL;\n do {\n v10 = v4[*v5];\n if ((v10 & 256) != 0) v9 = 1;\n if ((v10 & 512) != 0) v8 = 1;\n if ((v10 & 2048) != 0) v7 = 1;\n ++v5;\n } while (v5 != (const char *)v6);\n result_1[0] = 0;\n if (!v9) goto LABEL_25;\nLABEL_11:\n if (!v8)\n __strcat_chk(result_1, \"String must have 1 lower case character,\", 200LL,\n v2);\n if (!v7) __strcat_chk(result_1, \"String must have 1 number,\", 200LL, v2);\n if (v3 <= 7) {\n __strcat_chk(result_1, \"String length should be atleast 8,\", 200LL, v2);\n } else if (v9 && v8 && v7) {\n strcpy(result_1, \"Valid string.\");\n return result_1;\n }\n v11 = (int)(strlen(result_1) - 1);\n if (result_1[v11] == 44) result_1[v11] = 0;\n return result_1;\n}" + }, + { + "index": 523, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char *func0(const char *str1) {\n static char result[200];\n int has_upper = 0, has_lower = 0, has_digit = 0, is_valid = 1;\n int length = strlen(str1);\n for (int i = 0; i < length; i++) {\n if (isupper(str1[i])) {\n has_upper = 1;\n }\n if (islower(str1[i])) {\n has_lower = 1;\n }\n if (isdigit(str1[i])) {\n has_digit = 1;\n }\n }\n result[0] = '\\0';\n if (!has_upper) {\n strcat(result, \"String must have 1 upper case character,\");\n }\n if (!has_lower) {\n strcat(result, \"String must have 1 lower case character,\");\n }\n if (!has_digit) {\n strcat(result, \"String must have 1 number,\");\n }\n if (length < 8) {\n strcat(result, \"String length should be atleast 8,\");\n }\n if (has_upper && has_lower && has_digit && length >= 8) {\n strcpy(result, \"Valid string.\");\n } else {\n int lastIdx = strlen(result) - 1;\n if (result[lastIdx] == ',') {\n result[lastIdx] = '\\0';\n }\n }\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"python\"), \"String must have 1 upper case character,String must have 1 number,String length should be atleast 8\") == 0);\n\n assert(strcmp(func0(\"123python\"), \"String must have 1 upper case character\") == 0);\n\n assert(strcmp(func0(\"123Python\"), \"Valid string.\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nsub $0x8,%rsp\ncallq 1090 \nmov %rax,%r13\ntest %eax,%eax\njle 13b8 \ncallq 10b0 <__ctype_b_loc@plt>\nxor %r12d,%r12d\nmov %rbx,%rdi\nxor %ebp,%ebp\nmov (%rax),%rsi\nlea -0x1(%r13),%eax\nmov $0x1,%edx\nlea 0x1(%rbx,%rax,1),%rcx\nxor %ebx,%ebx\nnopl 0x0(%rax)\nmovsbq (%rdi),%rax\nmovzwl (%rsi,%rax,2),%eax\ntest $0x1,%ah\ncmovne %edx,%ebx\ntest $0x2,%ah\ncmovne %edx,%ebp\ntest $0x8,%ah\ncmovne %edx,%r12d\nadd $0x1,%rdi\ncmp %rdi,%rcx\njne 12d8 \nmovb $0x0,0x2d3d(%rip)\ntest %ebx,%ebx\nje 1460 \ntest %ebp,%ebp\nje 1440 \ntest %r12d,%r12d\nje 140a \ncmp $0x7,%r13d\njle 1398 \ntest %ebx,%ebp\nje 132f \ntest %r12d,%r12d\njne 1480 \nlea 0x2d0a(%rip),%rsi\nmov %rsi,%rdi\nmov %rsi,%rdx\nmov (%rdx),%ecx\nadd $0x4,%rdx\nlea -0x1010101(%rcx),%eax\nnot %ecx\nand %ecx,%eax\nand $0x80808080,%eax\nje 133c \nmov %eax,%ecx\nshr $0x10,%ecx\ntest $0x8080,%eax\ncmove %ecx,%eax\nlea 0x2(%rdx),%rcx\ncmove %rcx,%rdx\nmov %eax,%ebx\nadd %al,%bl\nsbb $0x3,%rdx\nsub %rsi,%rdx\nsub $0x1,%edx\nmovslq %edx,%rdx\ncmpb $0x2c,(%rdi,%rdx,1)\nje 1430 \nadd $0x8,%rsp\nlea 0x2cb2(%rip),%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopl (%rax)\nmov $0xc8,%edx\nlea 0xcc4(%rip),%rsi\nlea 0x2c95(%rip),%rdi\ncallq 1080 <__strcat_chk@plt>\njmpq 132f \nnopl (%rax)\nmov $0xc8,%edx\nlea 0xc44(%rip),%rsi\nxor %ebx,%ebx\nxor %ebp,%ebp\nmovdqa 0xee0(%rip),%xmm0\nlea 0x2c69(%rip),%rdi\nmovabs $0x2c72657463617261,%rax\nmovb $0x0,0x2c80(%rip)\nmov %rax,0x2c71(%rip)\nmovaps %xmm0,0x2c4a(%rip)\nmovdqa 0xec2(%rip),%xmm0\nmovaps %xmm0,0x2c4b(%rip)\ncallq 1080 <__strcat_chk@plt>\nmov $0xc8,%edx\nlea 0xe53(%rip),%rsi\nlea 0x2c23(%rip),%rdi\nxor %r12d,%r12d\ncallq 1080 <__strcat_chk@plt>\njmpq 131c \nnopw 0x0(%rax,%rax,1)\nmovb $0x0,(%rdi,%rdx,1)\njmpq 1383 \nnopl 0x0(%rax)\nmov $0xc8,%edx\nlea 0xbbc(%rip),%rsi\nlea 0x2bed(%rip),%rdi\ncallq 1080 <__strcat_chk@plt>\njmpq 1313 \nnopl (%rax)\nmov $0xc8,%edx\nlea 0xbcc(%rip),%rsi\nlea 0x2bcd(%rip),%rdi\ncallq 1080 <__strcat_chk@plt>\njmpq 130b \nnopl (%rax)\nmovabs $0x74732064696c6156,%rax\nmovl $0x676e6972,0x2bb4(%rip)\nmov %rax,0x2ba5(%rip)\nmov $0x2e,%eax\nmov %ax,0x2ba5(%rip)\njmpq 1383 \nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\ncall _strlen\ntest eax, eax\njle loc_13D8\nmov r13, rax\nxor r12d, r12d\nxor ebp, ebp\ncall ___ctype_b_loc\nmov rdi, rbx\nmov edx, 1\nmov rsi, [rax]\nlea eax, [r13-1]\nlea rcx, [rbx+rax+1]\nxor ebx, ebx\nnop\nloc_12E0:\nmovsx rax, byte ptr [rdi]\nmovzx eax, word ptr [rsi+rax*2]\ntest ah, 1\ncmovnz ebp, edx\ntest ah, 2\ncmovnz ebx, edx\ntest ah, 8\ncmovnz r12d, edx\nadd rdi, 1\ncmp rcx, rdi\njnz short loc_12E0\nmov byte ptr cs:result_1, 0\nlea r14, result_1\ntest ebp, ebp\njz short loc_1360\ntest ebx, ebx\njz short loc_1380\ntest r12d, r12d\njz loc_1460\ncmp r13d, 7\njle loc_1441\nloc_132D:\nmov rax, 74732064696C6156h\nmov qword ptr cs:result_1, rax\nmov rax, 2E676E69727473h\nmov qword ptr cs:result_1+6, rax\nloc_134F:\npop rbx\nmov rax, r14\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1360:\nmov edx, 0C8h\nlea rsi, aStringMustHave_1; \"String must have 1 upper case character\"...\nmov rdi, r14\ncall ___strcat_chk\ntest ebx, ebx\njnz short loc_1396\nnop dword ptr [rax+rax+00000000h]\nloc_1380:\nmov edx, 0C8h\nlea rsi, aStringMustHave_2; \"String must have 1 lower case character\"...\nmov rdi, r14\nxor ebx, ebx\ncall ___strcat_chk\nloc_1396:\ntest r12d, r12d\njz loc_1460\ncmp r13d, 7\njle loc_1441\ntest ebx, ebp\njnz short loc_132D\nloc_13AD:\nmov rdi, r14; s\ncall _strlen\nsub eax, 1\ncdqe\ncmp byte ptr [r14+rax], 2Ch ; ','\njnz short loc_134F\nmov byte ptr [r14+rax], 0\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_13D8:\nmovdqa xmm0, cs:xmmword_2290\nmovdqa xmm1, cs:xmmword_22A0\nmov rax, 2C72657463617261h\nlea r14, result_1\nmov cs:qword_4060, rax\nmovaps cs:xmmword_4090, xmm0\nmovaps cs:result_1, xmm0\nmovaps cs:xmmword_4050, xmm1\nmovdqa xmm1, cs:xmmword_22B0\nmovups cs:xmmword_4068, xmm0\nmovdqa xmm0, cs:xmmword_22C0\nmov cs:qword_4088, rax\nmovups cs:xmmword_4078, xmm1\nmovups cs:xmmword_4090+0Bh, xmm0\nloc_1441:\nmov edx, 0C8h\nlea rsi, aStringLengthSh; \"String length should be atleast 8,\"\nmov rdi, r14\ncall ___strcat_chk\njmp loc_13AD\nloc_1460:\nmov edx, 0C8h\nlea rsi, aStringMustHave_3; \"String must have 1 number,\"\nmov rdi, r14\ncall ___strcat_chk\ncmp r13d, 7\njg loc_13AD\njmp short loc_1441", + "ida_pseudo": "char *__fastcall func0(const char *a1)\n{\n int v1; // eax\n int v2; // r13d\n int v3; // r12d\n int v4; // ebp\n const unsigned __int16 *v5; // rsi\n __int64 v6; // rcx\n int v7; // ebx\n unsigned __int16 v8; // ax\n __int64 v10; // rax\n\n v1 = strlen(a1);\n if ( v1 <= 0 )\n {\n qword_4060 = 0x2C72657463617261LL;\n xmmword_4090 = (__int128)_mm_load_si128((const __m128i *)&xmmword_2290);\n *(_OWORD *)result_1 = xmmword_4090;\n xmmword_4050 = (__int128)_mm_load_si128((const __m128i *)&xmmword_22A0);\n xmmword_4068 = xmmword_4090;\n qword_4088 = 0x2C72657463617261LL;\n xmmword_4078 = (__int128)_mm_load_si128((const __m128i *)&xmmword_22B0);\n *(__int128 *)((char *)&xmmword_4090 + 11) = (__int128)_mm_load_si128((const __m128i *)&xmmword_22C0);\n goto LABEL_24;\n }\n v2 = v1;\n v3 = 0;\n v4 = 0;\n v5 = *__ctype_b_loc();\n v6 = (__int64)&a1[v2 - 1 + 1];\n v7 = 0;\n do\n {\n v8 = v5[*a1];\n if ( (v8 & 0x100) != 0 )\n v4 = 1;\n if ( (v8 & 0x200) != 0 )\n v7 = 1;\n if ( (v8 & 0x800) != 0 )\n v3 = 1;\n ++a1;\n }\n while ( (const char *)v6 != a1 );\n result_1[0] = 0;\n if ( !v4 )\n {\n __strcat_chk(result_1, \"String must have 1 upper case character,\", 200LL);\n if ( v7 )\n {\nLABEL_18:\n if ( !v3 )\n goto LABEL_25;\n if ( v2 > 7 )\n {\n if ( (v4 & v7) != 0 )\n goto LABEL_14;\n goto LABEL_21;\n }\nLABEL_24:\n __strcat_chk(result_1, \"String length should be atleast 8,\", 200LL);\n goto LABEL_21;\n }\nLABEL_17:\n v7 = 0;\n __strcat_chk(result_1, \"String must have 1 lower case character,\", 200LL);\n goto LABEL_18;\n }\n if ( !v7 )\n goto LABEL_17;\n if ( v3 )\n {\n if ( v2 > 7 )\n {\nLABEL_14:\n strcpy(result_1, \"Valid string.\");\n return result_1;\n }\n goto LABEL_24;\n }\nLABEL_25:\n __strcat_chk(result_1, \"String must have 1 number,\", 200LL);\n if ( v2 <= 7 )\n goto LABEL_24;\nLABEL_21:\n v10 = (int)(strlen(result_1) - 1);\n if ( result_1[v10] != 44 )\n return result_1;\n result_1[v10] = 0;\n return result_1;\n}", + "ida_strip_asm": "sub_12A0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\ncall _strlen\ntest eax, eax\njle loc_13D8\nmov r13, rax\nxor r12d, r12d\nxor ebp, ebp\ncall ___ctype_b_loc\nmov rdi, rbx\nmov edx, 1\nmov rsi, [rax]\nlea eax, [r13-1]\nlea rcx, [rbx+rax+1]\nxor ebx, ebx\nnop\nloc_12E0:\nmovsx rax, byte ptr [rdi]\nmovzx eax, word ptr [rsi+rax*2]\ntest ah, 1\ncmovnz ebp, edx\ntest ah, 2\ncmovnz ebx, edx\ntest ah, 8\ncmovnz r12d, edx\nadd rdi, 1\ncmp rcx, rdi\njnz short loc_12E0\nmov byte ptr cs:s, 0\nlea r14, s\ntest ebp, ebp\njz short loc_1360\ntest ebx, ebx\njz short loc_1380\ntest r12d, r12d\njz loc_1460\ncmp r13d, 7\njle loc_1441\nloc_132D:\nmov rax, 74732064696C6156h\nmov qword ptr cs:s, rax\nmov rax, 2E676E69727473h\nmov qword ptr cs:s+6, rax\nloc_134F:\npop rbx\nmov rax, r14\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1360:\nmov edx, 0C8h\nlea rsi, aStringMustHave_1; \"String must have 1 upper case character\"...\nmov rdi, r14\ncall ___strcat_chk\ntest ebx, ebx\njnz short loc_1396\nnop dword ptr [rax+rax+00000000h]\nloc_1380:\nmov edx, 0C8h\nlea rsi, aStringMustHave_2; \"String must have 1 lower case character\"...\nmov rdi, r14\nxor ebx, ebx\ncall ___strcat_chk\nloc_1396:\ntest r12d, r12d\njz loc_1460\ncmp r13d, 7\njle loc_1441\ntest ebx, ebp\njnz short loc_132D\nloc_13AD:\nmov rdi, r14; s\ncall _strlen\nsub eax, 1\ncdqe\ncmp byte ptr [r14+rax], 2Ch ; ','\njnz short loc_134F\nmov byte ptr [r14+rax], 0\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_13D8:\nmovdqa xmm0, cs:xmmword_2290\nmovdqa xmm1, cs:xmmword_22A0\nmov rax, 2C72657463617261h\nlea r14, s\nmov cs:qword_4060, rax\nmovaps cs:xmmword_4090, xmm0\nmovaps cs:s, xmm0\nmovaps cs:xmmword_4050, xmm1\nmovdqa xmm1, cs:xmmword_22B0\nmovups cs:xmmword_4068, xmm0\nmovdqa xmm0, cs:xmmword_22C0\nmov cs:qword_4088, rax\nmovups cs:xmmword_4078, xmm1\nmovups cs:xmmword_4090+0Bh, xmm0\nloc_1441:\nmov edx, 0C8h\nlea rsi, aStringLengthSh; \"String length should be atleast 8,\"\nmov rdi, r14\ncall ___strcat_chk\njmp loc_13AD\nloc_1460:\nmov edx, 0C8h\nlea rsi, aStringMustHave_3; \"String must have 1 number,\"\nmov rdi, r14\ncall ___strcat_chk\ncmp r13d, 7\njg loc_13AD\njmp short loc_1441", + "ida_strip_pseudo": "char *__fastcall sub_12A0(const char *a1)\n{\n int v1; // eax\n int v2; // r13d\n int v3; // r12d\n int v4; // ebp\n const unsigned __int16 *v5; // rsi\n __int64 v6; // rcx\n int v7; // ebx\n unsigned __int16 v8; // ax\n __int64 v10; // rax\n\n v1 = strlen(a1);\n if ( v1 <= 0 )\n {\n qword_4060 = 0x2C72657463617261LL;\n xmmword_4090 = (__int128)_mm_load_si128((const __m128i *)&xmmword_2290);\n *(_OWORD *)s = xmmword_4090;\n xmmword_4050 = (__int128)_mm_load_si128((const __m128i *)&xmmword_22A0);\n xmmword_4068 = xmmword_4090;\n qword_4088 = 0x2C72657463617261LL;\n xmmword_4078 = (__int128)_mm_load_si128((const __m128i *)&xmmword_22B0);\n *(__int128 *)((char *)&xmmword_4090 + 11) = (__int128)_mm_load_si128((const __m128i *)&xmmword_22C0);\n goto LABEL_24;\n }\n v2 = v1;\n v3 = 0;\n v4 = 0;\n v5 = *__ctype_b_loc();\n v6 = (__int64)&a1[v2 - 1 + 1];\n v7 = 0;\n do\n {\n v8 = v5[*a1];\n if ( (v8 & 0x100) != 0 )\n v4 = 1;\n if ( (v8 & 0x200) != 0 )\n v7 = 1;\n if ( (v8 & 0x800) != 0 )\n v3 = 1;\n ++a1;\n }\n while ( (const char *)v6 != a1 );\n s[0] = 0;\n if ( !v4 )\n {\n __strcat_chk(s, \"String must have 1 upper case character,\", 200LL);\n if ( v7 )\n {\nLABEL_18:\n if ( !v3 )\n goto LABEL_25;\n if ( v2 > 7 )\n {\n if ( (v4 & v7) != 0 )\n goto LABEL_14;\n goto LABEL_21;\n }\nLABEL_24:\n __strcat_chk(s, \"String length should be atleast 8,\", 200LL);\n goto LABEL_21;\n }\nLABEL_17:\n v7 = 0;\n __strcat_chk(s, \"String must have 1 lower case character,\", 200LL);\n goto LABEL_18;\n }\n if ( !v7 )\n goto LABEL_17;\n if ( v3 )\n {\n if ( v2 > 7 )\n {\nLABEL_14:\n strcpy(s, \"Valid string.\");\n return s;\n }\n goto LABEL_24;\n }\nLABEL_25:\n __strcat_chk(s, \"String must have 1 number,\", 200LL);\n if ( v2 <= 7 )\n goto LABEL_24;\nLABEL_21:\n v10 = (int)(strlen(s) - 1);\n if ( s[v10] != 44 )\n return s;\n s[v10] = 0;\n return s;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_12A0(const char *a1) {\n int v1;\n int v2;\n int v3;\n int v4;\n const unsigned short *v5;\n long long v6;\n int v7;\n unsigned short v8;\n long long v10;\n v1 = strlen(a1);\n if (v1 <= 0) {\n qword_4060 = 3202733835571786337LL;\n xmmword_4090 = (__int128)_mm_load_si128((const __m128i *)&xmmword_2290);\n *(long double *)s = xmmword_4090;\n xmmword_4050 = (__int128)_mm_load_si128((const __m128i *)&xmmword_22A0);\n xmmword_4068 = xmmword_4090;\n qword_4088 = 3202733835571786337LL;\n xmmword_4078 = (__int128)_mm_load_si128((const __m128i *)&xmmword_22B0);\n *(__int128 *)((char *)&xmmword_4090 + 11) =\n (__int128)_mm_load_si128((const __m128i *)&xmmword_22C0);\n goto LABEL_24;\n }\n v2 = v1;\n v3 = 0;\n v4 = 0;\n v5 = *__ctype_b_loc();\n v6 = (long long)&a1[v2 - 1 + 1];\n v7 = 0;\n do {\n v8 = v5[*a1];\n if ((v8 & 256) != 0) v4 = 1;\n if ((v8 & 512) != 0) v7 = 1;\n if ((v8 & 2048) != 0) v3 = 1;\n ++a1;\n } while ((const char *)v6 != a1);\n s[0] = 0;\n if (!v4) {\n __strcat_chk(s, \"String must have 1 upper case character,\", 200LL);\n if (v7) {\n LABEL_18:\n if (!v3) goto LABEL_25;\n if (v2 > 7) {\n if ((v4 & v7) != 0) goto LABEL_14;\n goto LABEL_21;\n }\n LABEL_24:\n __strcat_chk(s, \"String length should be atleast 8,\", 200LL);\n goto LABEL_21;\n }\n LABEL_17:\n v7 = 0;\n __strcat_chk(s, \"String must have 1 lower case character,\", 200LL);\n goto LABEL_18;\n }\n if (!v7) goto LABEL_17;\n if (v3) {\n if (v2 > 7) {\n LABEL_14:\n strcpy(s, \"Valid string.\");\n return s;\n }\n goto LABEL_24;\n }\nLABEL_25:\n __strcat_chk(s, \"String must have 1 number,\", 200LL);\n if (v2 <= 7) goto LABEL_24;\nLABEL_21:\n v10 = (int)(strlen(s) - 1);\n if (s[v10] != 44) return s;\n s[v10] = 0;\n return s;\n}", + "ida_pseudo_norm": "char *func0(const char *a1) {\n int v1;\n int v2;\n int v3;\n int v4;\n const unsigned short *v5;\n long long v6;\n int v7;\n unsigned short v8;\n long long v10;\n v1 = strlen(a1);\n if (v1 <= 0) {\n qword_4060 = 3202733835571786337LL;\n xmmword_4090 = (__int128)_mm_load_si128((const __m128i *)&xmmword_2290);\n *(long double *)result_1 = xmmword_4090;\n xmmword_4050 = (__int128)_mm_load_si128((const __m128i *)&xmmword_22A0);\n xmmword_4068 = xmmword_4090;\n qword_4088 = 3202733835571786337LL;\n xmmword_4078 = (__int128)_mm_load_si128((const __m128i *)&xmmword_22B0);\n *(__int128 *)((char *)&xmmword_4090 + 11) =\n (__int128)_mm_load_si128((const __m128i *)&xmmword_22C0);\n goto LABEL_24;\n }\n v2 = v1;\n v3 = 0;\n v4 = 0;\n v5 = *__ctype_b_loc();\n v6 = (long long)&a1[v2 - 1 + 1];\n v7 = 0;\n do {\n v8 = v5[*a1];\n if ((v8 & 256) != 0) v4 = 1;\n if ((v8 & 512) != 0) v7 = 1;\n if ((v8 & 2048) != 0) v3 = 1;\n ++a1;\n } while ((const char *)v6 != a1);\n result_1[0] = 0;\n if (!v4) {\n __strcat_chk(result_1, \"String must have 1 upper case character,\", 200LL);\n if (v7) {\n LABEL_18:\n if (!v3) goto LABEL_25;\n if (v2 > 7) {\n if ((v4 & v7) != 0) goto LABEL_14;\n goto LABEL_21;\n }\n LABEL_24:\n __strcat_chk(result_1, \"String length should be atleast 8,\", 200LL);\n goto LABEL_21;\n }\n LABEL_17:\n v7 = 0;\n __strcat_chk(result_1, \"String must have 1 lower case character,\", 200LL);\n goto LABEL_18;\n }\n if (!v7) goto LABEL_17;\n if (v3) {\n if (v2 > 7) {\n LABEL_14:\n strcpy(result_1, \"Valid string.\");\n return result_1;\n }\n goto LABEL_24;\n }\nLABEL_25:\n __strcat_chk(result_1, \"String must have 1 number,\", 200LL);\n if (v2 <= 7) goto LABEL_24;\nLABEL_21:\n v10 = (int)(strlen(result_1) - 1);\n if (result_1[v10] != 44) return result_1;\n result_1[v10] = 0;\n return result_1;\n}" + }, + { + "index": 523, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char *func0(const char *str1) {\n static char result[200];\n int has_upper = 0, has_lower = 0, has_digit = 0, is_valid = 1;\n int length = strlen(str1);\n for (int i = 0; i < length; i++) {\n if (isupper(str1[i])) {\n has_upper = 1;\n }\n if (islower(str1[i])) {\n has_lower = 1;\n }\n if (isdigit(str1[i])) {\n has_digit = 1;\n }\n }\n result[0] = '\\0';\n if (!has_upper) {\n strcat(result, \"String must have 1 upper case character,\");\n }\n if (!has_lower) {\n strcat(result, \"String must have 1 lower case character,\");\n }\n if (!has_digit) {\n strcat(result, \"String must have 1 number,\");\n }\n if (length < 8) {\n strcat(result, \"String length should be atleast 8,\");\n }\n if (has_upper && has_lower && has_digit && length >= 8) {\n strcpy(result, \"Valid string.\");\n } else {\n int lastIdx = strlen(result) - 1;\n if (result[lastIdx] == ',') {\n result[lastIdx] = '\\0';\n }\n }\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"python\"), \"String must have 1 upper case character,String must have 1 number,String length should be atleast 8\") == 0);\n\n assert(strcmp(func0(\"123python\"), \"String must have 1 upper case character\") == 0);\n\n assert(strcmp(func0(\"123Python\"), \"Valid string.\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nsub $0x8,%rsp\ncallq 1090 \nmov %rax,%r13\ntest %eax,%eax\njle 13b8 \ncallq 10b0 <__ctype_b_loc@plt>\nxor %r12d,%r12d\nmov %rbx,%rdi\nxor %ebp,%ebp\nmov (%rax),%rsi\nlea -0x1(%r13),%eax\nmov $0x1,%edx\nlea 0x1(%rbx,%rax,1),%rcx\nxor %ebx,%ebx\nnopl 0x0(%rax)\nmovsbq (%rdi),%rax\nmovzwl (%rsi,%rax,2),%eax\ntest $0x1,%ah\ncmovne %edx,%ebx\ntest $0x2,%ah\ncmovne %edx,%ebp\ntest $0x8,%ah\ncmovne %edx,%r12d\nadd $0x1,%rdi\ncmp %rdi,%rcx\njne 12d8 \nmovb $0x0,0x2d3d(%rip)\ntest %ebx,%ebx\nje 1460 \ntest %ebp,%ebp\nje 1440 \ntest %r12d,%r12d\nje 140a \ncmp $0x7,%r13d\njle 1398 \ntest %ebx,%ebp\nje 132f \ntest %r12d,%r12d\njne 1480 \nlea 0x2d0a(%rip),%rsi\nmov %rsi,%rdi\nmov %rsi,%rdx\nmov (%rdx),%ecx\nadd $0x4,%rdx\nlea -0x1010101(%rcx),%eax\nnot %ecx\nand %ecx,%eax\nand $0x80808080,%eax\nje 133c \nmov %eax,%ecx\nshr $0x10,%ecx\ntest $0x8080,%eax\ncmove %ecx,%eax\nlea 0x2(%rdx),%rcx\ncmove %rcx,%rdx\nmov %eax,%ebx\nadd %al,%bl\nsbb $0x3,%rdx\nsub %rsi,%rdx\nsub $0x1,%edx\nmovslq %edx,%rdx\ncmpb $0x2c,(%rdi,%rdx,1)\nje 1430 \nadd $0x8,%rsp\nlea 0x2cb2(%rip),%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopl (%rax)\nmov $0xc8,%edx\nlea 0xcc4(%rip),%rsi\nlea 0x2c95(%rip),%rdi\ncallq 1080 <__strcat_chk@plt>\njmpq 132f \nnopl (%rax)\nmov $0xc8,%edx\nlea 0xc44(%rip),%rsi\nxor %ebp,%ebp\nxor %ebx,%ebx\nmovdqa 0xee0(%rip),%xmm0\nlea 0x2c69(%rip),%rdi\nmovabs $0x2c72657463617261,%rax\nmovb $0x0,0x2c80(%rip)\nmov %rax,0x2c71(%rip)\nmovaps %xmm0,0x2c4a(%rip)\nmovdqa 0xec2(%rip),%xmm0\nmovaps %xmm0,0x2c4b(%rip)\ncallq 1080 <__strcat_chk@plt>\nmov $0xc8,%edx\nlea 0xe53(%rip),%rsi\nlea 0x2c23(%rip),%rdi\nxor %r12d,%r12d\ncallq 1080 <__strcat_chk@plt>\njmpq 131c \nnopw 0x0(%rax,%rax,1)\nmovb $0x0,(%rdi,%rdx,1)\njmpq 1383 \nnopl 0x0(%rax)\nmov $0xc8,%edx\nlea 0xbbc(%rip),%rsi\nlea 0x2bed(%rip),%rdi\ncallq 1080 <__strcat_chk@plt>\njmpq 1313 \nnopl (%rax)\nmov $0xc8,%edx\nlea 0xbcc(%rip),%rsi\nlea 0x2bcd(%rip),%rdi\ncallq 1080 <__strcat_chk@plt>\njmpq 130b \nnopl (%rax)\nmovabs $0x74732064696c6156,%rax\nmovl $0x676e6972,0x2bb4(%rip)\nmov %rax,0x2ba5(%rip)\nmov $0x2e,%eax\nmov %ax,0x2ba5(%rip)\njmpq 1383 \nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\ntest eax, eax\njle loc_13D0\nmov r12, rax\nxor ebp, ebp\ncall ___ctype_b_loc\nmov rdi, rbx\nxor ecx, ecx\nmov edx, 1\nmov r8, [rax]\nlea eax, [r12-1]\nlea rsi, [rbx+rax+1]\nxor ebx, ebx\nnop dword ptr [rax+00000000h]\nloc_12E8:\nmovsx rax, byte ptr [rdi]\nmovzx eax, word ptr [r8+rax*2]\ntest ah, 1\ncmovnz ecx, edx\ntest ah, 2\ncmovnz ebp, edx\ntest ah, 8\ncmovnz ebx, edx\nadd rdi, 1\ncmp rsi, rdi\njnz short loc_12E8\nmov byte ptr cs:result_1, 0\nlea r13, result_1\ntest ecx, ecx\njz short loc_1368\ntest ebp, ebp\njz short loc_1380\ntest ebx, ebx\njz loc_1458\ncmp r12d, 7\njle loc_1439\nmov rax, 74732064696C6156h\nmov qword ptr cs:result_1, rax\nmov rax, 2E676E69727473h\nmov qword ptr cs:result_1+6, rax\nloc_1356:\nadd rsp, 8\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1368:\nmov edx, 0C8h\nlea rsi, aStringMustHave_1; \"String must have 1 upper case character\"...\nmov rdi, r13\ncall ___strcat_chk\ntest ebp, ebp\njnz short loc_1394\nloc_1380:\nmov edx, 0C8h\nlea rsi, aStringMustHave_2; \"String must have 1 lower case character\"...\nmov rdi, r13\ncall ___strcat_chk\nloc_1394:\ntest ebx, ebx\njz loc_1458\ncmp r12d, 7\njle loc_1439\nloc_13A6:\nmov rdi, r13; s\ncall _strlen\nsub eax, 1\ncdqe\ncmp byte ptr [r13+rax+0], 2Ch ; ','\njnz short loc_1356\nmov byte ptr [r13+rax+0], 0\nadd rsp, 8\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_13D0:\nmovdqa xmm0, cs:xmmword_2290\nmovdqa xmm1, cs:xmmword_22A0\nmov rax, 2C72657463617261h\nlea r13, result_1\nmov cs:qword_4060, rax\nmovaps cs:xmmword_4090, xmm0\nmovaps cs:result_1, xmm0\nmovaps cs:xmmword_4050, xmm1\nmovdqa xmm1, cs:xmmword_22B0\nmovups cs:xmmword_4068, xmm0\nmovdqa xmm0, cs:xmmword_22C0\nmov cs:qword_4088, rax\nmovups cs:xmmword_4078, xmm1\nmovups cs:xmmword_4090+0Bh, xmm0\nloc_1439:\nmov edx, 0C8h\nlea rsi, aStringLengthSh; \"String length should be atleast 8,\"\nmov rdi, r13\ncall ___strcat_chk\njmp loc_13A6\nloc_1458:\nmov edx, 0C8h\nlea rsi, aStringMustHave_3; \"String must have 1 number,\"\nmov rdi, r13\ncall ___strcat_chk\ncmp r12d, 7\njg loc_13A6\njmp short loc_1439", + "ida_pseudo": "char *__fastcall func0(const char *a1)\n{\n int v1; // eax\n int v2; // r12d\n int v3; // ebp\n const unsigned __int16 **v4; // rax\n int v5; // ecx\n const unsigned __int16 *v6; // r8\n __int64 v7; // rsi\n int v8; // ebx\n unsigned __int16 v9; // ax\n __int64 v11; // rax\n\n v1 = strlen(a1);\n if ( v1 <= 0 )\n {\n qword_4060 = 0x2C72657463617261LL;\n xmmword_4090 = (__int128)_mm_load_si128((const __m128i *)&xmmword_2290);\n *(_OWORD *)result_1 = xmmword_4090;\n xmmword_4050 = (__int128)_mm_load_si128((const __m128i *)&xmmword_22A0);\n xmmword_4068 = xmmword_4090;\n qword_4088 = 0x2C72657463617261LL;\n xmmword_4078 = (__int128)_mm_load_si128((const __m128i *)&xmmword_22B0);\n *(__int128 *)((char *)&xmmword_4090 + 11) = (__int128)_mm_load_si128((const __m128i *)&xmmword_22C0);\nLABEL_23:\n __strcat_chk(result_1, \"String length should be atleast 8,\", 200LL);\n goto LABEL_20;\n }\n v2 = v1;\n v3 = 0;\n v4 = __ctype_b_loc();\n v5 = 0;\n v6 = *v4;\n v7 = (__int64)&a1[v2 - 1 + 1];\n v8 = 0;\n do\n {\n v9 = v6[*a1];\n if ( (v9 & 0x100) != 0 )\n v5 = 1;\n if ( (v9 & 0x200) != 0 )\n v3 = 1;\n if ( (v9 & 0x800) != 0 )\n v8 = 1;\n ++a1;\n }\n while ( (const char *)v7 != a1 );\n result_1[0] = 0;\n if ( !v5 )\n {\n __strcat_chk(result_1, \"String must have 1 upper case character,\", 200LL);\n if ( v3 )\n goto LABEL_18;\n goto LABEL_17;\n }\n if ( !v3 )\n {\nLABEL_17:\n __strcat_chk(result_1, \"String must have 1 lower case character,\", 200LL);\nLABEL_18:\n if ( v8 )\n {\n if ( v2 > 7 )\n goto LABEL_20;\n goto LABEL_23;\n }\n goto LABEL_24;\n }\n if ( v8 )\n {\n if ( v2 > 7 )\n {\n strcpy(result_1, \"Valid string.\");\n return result_1;\n }\n goto LABEL_23;\n }\nLABEL_24:\n __strcat_chk(result_1, \"String must have 1 number,\", 200LL);\n if ( v2 <= 7 )\n goto LABEL_23;\nLABEL_20:\n v11 = (int)(strlen(result_1) - 1);\n if ( result_1[v11] != 44 )\n return result_1;\n result_1[v11] = 0;\n return result_1;\n}", + "ida_strip_asm": "sub_12A0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\ntest eax, eax\njle loc_13D0\nmov r12, rax\nxor ebp, ebp\ncall ___ctype_b_loc\nmov rdi, rbx\nxor ecx, ecx\nmov edx, 1\nmov r8, [rax]\nlea eax, [r12-1]\nlea rsi, [rbx+rax+1]\nxor ebx, ebx\nnop dword ptr [rax+00000000h]\nloc_12E8:\nmovsx rax, byte ptr [rdi]\nmovzx eax, word ptr [r8+rax*2]\ntest ah, 1\ncmovnz ecx, edx\ntest ah, 2\ncmovnz ebp, edx\ntest ah, 8\ncmovnz ebx, edx\nadd rdi, 1\ncmp rsi, rdi\njnz short loc_12E8\nmov byte ptr cs:s, 0\nlea r13, s\ntest ecx, ecx\njz short loc_1368\ntest ebp, ebp\njz short loc_1380\ntest ebx, ebx\njz loc_1458\ncmp r12d, 7\njle loc_1439\nmov rax, 74732064696C6156h\nmov qword ptr cs:s, rax\nmov rax, 2E676E69727473h\nmov qword ptr cs:s+6, rax\nloc_1356:\nadd rsp, 8\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1368:\nmov edx, 0C8h\nlea rsi, aStringMustHave_1; \"String must have 1 upper case character\"...\nmov rdi, r13\ncall ___strcat_chk\ntest ebp, ebp\njnz short loc_1394\nloc_1380:\nmov edx, 0C8h\nlea rsi, aStringMustHave_2; \"String must have 1 lower case character\"...\nmov rdi, r13\ncall ___strcat_chk\nloc_1394:\ntest ebx, ebx\njz loc_1458\ncmp r12d, 7\njle loc_1439\nloc_13A6:\nmov rdi, r13; s\ncall _strlen\nsub eax, 1\ncdqe\ncmp byte ptr [r13+rax+0], 2Ch ; ','\njnz short loc_1356\nmov byte ptr [r13+rax+0], 0\nadd rsp, 8\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_13D0:\nmovdqa xmm0, cs:xmmword_2290\nmovdqa xmm1, cs:xmmword_22A0\nmov rax, 2C72657463617261h\nlea r13, s\nmov cs:qword_4060, rax\nmovaps cs:xmmword_4090, xmm0\nmovaps cs:s, xmm0\nmovaps cs:xmmword_4050, xmm1\nmovdqa xmm1, cs:xmmword_22B0\nmovups cs:xmmword_4068, xmm0\nmovdqa xmm0, cs:xmmword_22C0\nmov cs:qword_4088, rax\nmovups cs:xmmword_4078, xmm1\nmovups cs:xmmword_4090+0Bh, xmm0\nloc_1439:\nmov edx, 0C8h\nlea rsi, aStringLengthSh; \"String length should be atleast 8,\"\nmov rdi, r13\ncall ___strcat_chk\njmp loc_13A6\nloc_1458:\nmov edx, 0C8h\nlea rsi, aStringMustHave_3; \"String must have 1 number,\"\nmov rdi, r13\ncall ___strcat_chk\ncmp r12d, 7\njg loc_13A6\njmp short loc_1439", + "ida_strip_pseudo": "char *__fastcall sub_12A0(const char *a1)\n{\n int v1; // eax\n int v2; // r12d\n int v3; // ebp\n const unsigned __int16 **v4; // rax\n int v5; // ecx\n const unsigned __int16 *v6; // r8\n __int64 v7; // rsi\n int v8; // ebx\n unsigned __int16 v9; // ax\n __int64 v11; // rax\n\n v1 = strlen(a1);\n if ( v1 <= 0 )\n {\n qword_4060 = 0x2C72657463617261LL;\n xmmword_4090 = (__int128)_mm_load_si128((const __m128i *)&xmmword_2290);\n *(_OWORD *)s = xmmword_4090;\n xmmword_4050 = (__int128)_mm_load_si128((const __m128i *)&xmmword_22A0);\n xmmword_4068 = xmmword_4090;\n qword_4088 = 0x2C72657463617261LL;\n xmmword_4078 = (__int128)_mm_load_si128((const __m128i *)&xmmword_22B0);\n *(__int128 *)((char *)&xmmword_4090 + 11) = (__int128)_mm_load_si128((const __m128i *)&xmmword_22C0);\nLABEL_23:\n __strcat_chk(s, \"String length should be atleast 8,\", 200LL);\n goto LABEL_20;\n }\n v2 = v1;\n v3 = 0;\n v4 = __ctype_b_loc();\n v5 = 0;\n v6 = *v4;\n v7 = (__int64)&a1[v2 - 1 + 1];\n v8 = 0;\n do\n {\n v9 = v6[*a1];\n if ( (v9 & 0x100) != 0 )\n v5 = 1;\n if ( (v9 & 0x200) != 0 )\n v3 = 1;\n if ( (v9 & 0x800) != 0 )\n v8 = 1;\n ++a1;\n }\n while ( (const char *)v7 != a1 );\n s[0] = 0;\n if ( !v5 )\n {\n __strcat_chk(s, \"String must have 1 upper case character,\", 200LL);\n if ( v3 )\n goto LABEL_18;\n goto LABEL_17;\n }\n if ( !v3 )\n {\nLABEL_17:\n __strcat_chk(s, \"String must have 1 lower case character,\", 200LL);\nLABEL_18:\n if ( v8 )\n {\n if ( v2 > 7 )\n goto LABEL_20;\n goto LABEL_23;\n }\n goto LABEL_24;\n }\n if ( v8 )\n {\n if ( v2 > 7 )\n {\n strcpy(s, \"Valid string.\");\n return s;\n }\n goto LABEL_23;\n }\nLABEL_24:\n __strcat_chk(s, \"String must have 1 number,\", 200LL);\n if ( v2 <= 7 )\n goto LABEL_23;\nLABEL_20:\n v11 = (int)(strlen(s) - 1);\n if ( s[v11] != 44 )\n return s;\n s[v11] = 0;\n return s;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_12A0(const char *a1) {\n int v1;\n int v2;\n int v3;\n const unsigned short **v4;\n int v5;\n const unsigned short *v6;\n long long v7;\n int v8;\n unsigned short v9;\n long long v11;\n v1 = strlen(a1);\n if (v1 <= 0) {\n qword_4060 = 3202733835571786337LL;\n xmmword_4090 = (__int128)_mm_load_si128((const __m128i *)&xmmword_2290);\n *(long double *)s = xmmword_4090;\n xmmword_4050 = (__int128)_mm_load_si128((const __m128i *)&xmmword_22A0);\n xmmword_4068 = xmmword_4090;\n qword_4088 = 3202733835571786337LL;\n xmmword_4078 = (__int128)_mm_load_si128((const __m128i *)&xmmword_22B0);\n *(__int128 *)((char *)&xmmword_4090 + 11) =\n (__int128)_mm_load_si128((const __m128i *)&xmmword_22C0);\n LABEL_23:\n __strcat_chk(s, \"String length should be atleast 8,\", 200LL);\n goto LABEL_20;\n }\n v2 = v1;\n v3 = 0;\n v4 = __ctype_b_loc();\n v5 = 0;\n v6 = *v4;\n v7 = (long long)&a1[v2 - 1 + 1];\n v8 = 0;\n do {\n v9 = v6[*a1];\n if ((v9 & 256) != 0) v5 = 1;\n if ((v9 & 512) != 0) v3 = 1;\n if ((v9 & 2048) != 0) v8 = 1;\n ++a1;\n } while ((const char *)v7 != a1);\n s[0] = 0;\n if (!v5) {\n __strcat_chk(s, \"String must have 1 upper case character,\", 200LL);\n if (v3) goto LABEL_18;\n goto LABEL_17;\n }\n if (!v3) {\n LABEL_17:\n __strcat_chk(s, \"String must have 1 lower case character,\", 200LL);\n LABEL_18:\n if (v8) {\n if (v2 > 7) goto LABEL_20;\n goto LABEL_23;\n }\n goto LABEL_24;\n }\n if (v8) {\n if (v2 > 7) {\n strcpy(s, \"Valid string.\");\n return s;\n }\n goto LABEL_23;\n }\nLABEL_24:\n __strcat_chk(s, \"String must have 1 number,\", 200LL);\n if (v2 <= 7) goto LABEL_23;\nLABEL_20:\n v11 = (int)(strlen(s) - 1);\n if (s[v11] != 44) return s;\n s[v11] = 0;\n return s;\n}", + "ida_pseudo_norm": "char *func0(const char *a1) {\n int v1;\n int v2;\n int v3;\n const unsigned short **v4;\n int v5;\n const unsigned short *v6;\n long long v7;\n int v8;\n unsigned short v9;\n long long v11;\n v1 = strlen(a1);\n if (v1 <= 0) {\n qword_4060 = 3202733835571786337LL;\n xmmword_4090 = (__int128)_mm_load_si128((const __m128i *)&xmmword_2290);\n *(long double *)result_1 = xmmword_4090;\n xmmword_4050 = (__int128)_mm_load_si128((const __m128i *)&xmmword_22A0);\n xmmword_4068 = xmmword_4090;\n qword_4088 = 3202733835571786337LL;\n xmmword_4078 = (__int128)_mm_load_si128((const __m128i *)&xmmword_22B0);\n *(__int128 *)((char *)&xmmword_4090 + 11) =\n (__int128)_mm_load_si128((const __m128i *)&xmmword_22C0);\n LABEL_23:\n __strcat_chk(result_1, \"String length should be atleast 8,\", 200LL);\n goto LABEL_20;\n }\n v2 = v1;\n v3 = 0;\n v4 = __ctype_b_loc();\n v5 = 0;\n v6 = *v4;\n v7 = (long long)&a1[v2 - 1 + 1];\n v8 = 0;\n do {\n v9 = v6[*a1];\n if ((v9 & 256) != 0) v5 = 1;\n if ((v9 & 512) != 0) v3 = 1;\n if ((v9 & 2048) != 0) v8 = 1;\n ++a1;\n } while ((const char *)v7 != a1);\n result_1[0] = 0;\n if (!v5) {\n __strcat_chk(result_1, \"String must have 1 upper case character,\", 200LL);\n if (v3) goto LABEL_18;\n goto LABEL_17;\n }\n if (!v3) {\n LABEL_17:\n __strcat_chk(result_1, \"String must have 1 lower case character,\", 200LL);\n LABEL_18:\n if (v8) {\n if (v2 > 7) goto LABEL_20;\n goto LABEL_23;\n }\n goto LABEL_24;\n }\n if (v8) {\n if (v2 > 7) {\n strcpy(result_1, \"Valid string.\");\n return result_1;\n }\n goto LABEL_23;\n }\nLABEL_24:\n __strcat_chk(result_1, \"String must have 1 number,\", 200LL);\n if (v2 <= 7) goto LABEL_23;\nLABEL_20:\n v11 = (int)(strlen(result_1) - 1);\n if (result_1[v11] != 44) return result_1;\n result_1[v11] = 0;\n return result_1;\n}" + }, + { + "index": 524, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int max = 0;\n int msis[n];\n for (int i = 0; i < n; i++) {\n msis[i] = arr[i];\n }\n for (int i = 1; i < n; i++) {\n for (int j = 0; j < i; j++) {\n if (arr[i] > arr[j] && msis[i] < msis[j] + arr[i]) {\n msis[i] = msis[j] + arr[i];\n }\n }\n }\n for (int i = 0; i < n; i++) {\n if (max < msis[i]) {\n max = msis[i];\n }\n }\n return max;\n}", + "test": "int main() {\n\n int arr1[] = {1, 101, 2, 3, 100, 4, 5};\n\n int arr2[] = {3, 4, 5, 10};\n\n int arr3[] = {10, 5, 4, 3};\n\n\n\n assert(func0(arr1, 7) == 106);\n\n assert(func0(arr2, 4) == 22);\n\n assert(func0(arr3, 4) == 10);\n\n \n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x48,%rsp\nmov %rdi,-0x48(%rbp)\nmov %esi,-0x4c(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmov %rsp,%rax\nmov %rax,%rdi\nmovl $0x0,-0x30(%rbp)\nmov -0x4c(%rbp),%eax\nmovslq %eax,%rdx\nsub $0x1,%rdx\nmov %rdx,-0x28(%rbp)\nmovslq %eax,%rdx\nmov %rdx,%r8\nmov $0x0,%r9d\nmovslq %eax,%rdx\nmov %rdx,%rcx\nmov $0x0,%ebx\ncltq\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%ebx\nmov $0x0,%edx\ndiv %rbx\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rbx\nsub %rdx,%rbx\nmov %rbx,%rdx\ncmp %rdx,%rsp\nje 122f \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 1218 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 1259 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x20(%rbp)\nmovl $0x0,-0x34(%rbp)\njmp 129c \nmov -0x34(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%ecx\nmov -0x20(%rbp),%rax\nmov -0x34(%rbp),%edx\nmovslq %edx,%rdx\nmov %ecx,(%rax,%rdx,4)\naddl $0x1,-0x34(%rbp)\nmov -0x34(%rbp),%eax\ncmp -0x4c(%rbp),%eax\njl 1275 \nmovl $0x1,-0x38(%rbp)\njmpq 1369 \nmovl $0x0,-0x3c(%rbp)\njmpq 1359 \nmov -0x38(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x3c(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x48(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njle 1355 \nmov -0x20(%rbp),%rax\nmov -0x38(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%ecx\nmov -0x20(%rbp),%rax\nmov -0x3c(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%edx\nmov -0x38(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rsi\nmov -0x48(%rbp),%rax\nadd %rsi,%rax\nmov (%rax),%eax\nadd %edx,%eax\ncmp %eax,%ecx\njge 1355 \nmov -0x20(%rbp),%rax\nmov -0x3c(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%edx\nmov -0x38(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x48(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\nlea (%rdx,%rax,1),%ecx\nmov -0x20(%rbp),%rax\nmov -0x38(%rbp),%edx\nmovslq %edx,%rdx\nmov %ecx,(%rax,%rdx,4)\naddl $0x1,-0x3c(%rbp)\nmov -0x3c(%rbp),%eax\ncmp -0x38(%rbp),%eax\njl 12bc \naddl $0x1,-0x38(%rbp)\nmov -0x38(%rbp),%eax\ncmp -0x4c(%rbp),%eax\njl 12b0 \nmovl $0x0,-0x2c(%rbp)\njmp 13a4 \nmov -0x20(%rbp),%rax\nmov -0x2c(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\ncmp %eax,-0x30(%rbp)\njge 13a0 \nmov -0x20(%rbp),%rax\nmov -0x2c(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nmov %eax,-0x30(%rbp)\naddl $0x1,-0x2c(%rbp)\nmov -0x2c(%rbp),%eax\ncmp -0x4c(%rbp),%eax\njl 137e \nmov -0x30(%rbp),%eax\nmov %rdi,%rsp\nmov -0x18(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 13c6 \ncallq 1080 <__stack_chk_fail@plt>\nmov -0x8(%rbp),%rbx\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rdi, rax\nmov [rbp+var_2C], 0\nmov eax, [rbp+var_3C]\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov esi, 10h\nmov edx, 0\ndiv rsi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11FD:\ncmp rsp, rdx\njz short loc_1214\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_11FD\nloc_1214:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_123E\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_123E:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov [rbp+var_28], 0\njmp short loc_1281\nloc_125A:\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov ecx, [rax]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nadd [rbp+var_28], 1\nloc_1281:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_3C]\njl short loc_125A\nmov [rbp+var_24], 1\njmp loc_134E\nloc_1295:\nmov [rbp+var_20], 0\njmp loc_133E\nloc_12A1:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_20]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_133A\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nmov edx, [rax+rdx*4]\nmov eax, [rbp+var_24]\ncdqe\nlea rsi, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rsi\nmov eax, [rax]\nadd eax, edx\ncmp ecx, eax\njge short loc_133A\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nmov edx, [rax+rdx*4]\nmov eax, [rbp+var_24]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov eax, [rax]\nlea ecx, [rdx+rax]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nloc_133A:\nadd [rbp+var_20], 1\nloc_133E:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_24]\njl loc_12A1\nadd [rbp+var_24], 1\nloc_134E:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_3C]\njl loc_1295\nmov [rbp+var_1C], 0\njmp short loc_1389\nloc_1363:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ncmp [rbp+var_2C], eax\njge short loc_1385\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov [rbp+var_2C], eax\nloc_1385:\nadd [rbp+var_1C], 1\nloc_1389:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_3C]\njl short loc_1363\nmov eax, [rbp+var_2C]\nmov rsp, rdi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_13AB\ncall ___stack_chk_fail\nlocret_13AB:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned __int64 v2; // rax\n void *v3; // rsp\n _BYTE v5[4]; // [rsp+8h] [rbp-40h] BYREF\n int v6; // [rsp+Ch] [rbp-3Ch]\n __int64 v7; // [rsp+10h] [rbp-38h]\n unsigned int v8; // [rsp+1Ch] [rbp-2Ch]\n int i; // [rsp+20h] [rbp-28h]\n int j; // [rsp+24h] [rbp-24h]\n int k; // [rsp+28h] [rbp-20h]\n int m; // [rsp+2Ch] [rbp-1Ch]\n __int64 v13; // [rsp+30h] [rbp-18h]\n _BYTE *v14; // [rsp+38h] [rbp-10h]\n unsigned __int64 v15; // [rsp+40h] [rbp-8h]\n\n v7 = a1;\n v6 = a2;\n v15 = __readfsqword(0x28u);\n v8 = 0;\n v13 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 0x10uLL);\n while ( v5 != &v5[-(v2 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = alloca(v2 & 0xFFF);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)&v5[(v2 & 0xFFF) - 8] = *(_QWORD *)&v5[(v2 & 0xFFF) - 8];\n v14 = v5;\n for ( i = 0; i < v6; ++i )\n *(_DWORD *)&v14[4 * i] = *(_DWORD *)(4LL * i + v7);\n for ( j = 1; j < v6; ++j )\n {\n for ( k = 0; k < j; ++k )\n {\n if ( *(_DWORD *)(4LL * j + v7) > *(_DWORD *)(4LL * k + v7)\n && *(_DWORD *)&v14[4 * j] < *(_DWORD *)&v14[4 * k] + *(_DWORD *)(4LL * j + v7) )\n {\n *(_DWORD *)&v14[4 * j] = *(_DWORD *)&v14[4 * k] + *(_DWORD *)(4LL * j + v7);\n }\n }\n }\n for ( m = 0; m < v6; ++m )\n {\n if ( (signed int)v8 < *(_DWORD *)&v14[4 * m] )\n v8 = *(_DWORD *)&v14[4 * m];\n }\n return v8;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rdi, rax\nmov [rbp+var_2C], 0\nmov eax, [rbp+var_3C]\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov esi, 10h\nmov edx, 0\ndiv rsi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11FD:\ncmp rsp, rdx\njz short loc_1214\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_11FD\nloc_1214:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_123E\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_123E:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov [rbp+var_28], 0\njmp short loc_1281\nloc_125A:\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov ecx, [rax]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nadd [rbp+var_28], 1\nloc_1281:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_3C]\njl short loc_125A\nmov [rbp+var_24], 1\njmp loc_134E\nloc_1295:\nmov [rbp+var_20], 0\njmp loc_133E\nloc_12A1:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_20]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_133A\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nmov edx, [rax+rdx*4]\nmov eax, [rbp+var_24]\ncdqe\nlea rsi, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rsi\nmov eax, [rax]\nadd eax, edx\ncmp ecx, eax\njge short loc_133A\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nmov edx, [rax+rdx*4]\nmov eax, [rbp+var_24]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov eax, [rax]\nlea ecx, [rdx+rax]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nloc_133A:\nadd [rbp+var_20], 1\nloc_133E:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_24]\njl loc_12A1\nadd [rbp+var_24], 1\nloc_134E:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_3C]\njl loc_1295\nmov [rbp+var_1C], 0\njmp short loc_1389\nloc_1363:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ncmp [rbp+var_2C], eax\njge short loc_1385\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov [rbp+var_2C], eax\nloc_1385:\nadd [rbp+var_1C], 1\nloc_1389:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_3C]\njl short loc_1363\nmov eax, [rbp+var_2C]\nmov rsp, rdi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_13AB\ncall ___stack_chk_fail\nlocret_13AB:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2)\n{\n unsigned __int64 v2; // rax\n void *v3; // rsp\n _BYTE v5[4]; // [rsp+8h] [rbp-40h] BYREF\n int v6; // [rsp+Ch] [rbp-3Ch]\n __int64 v7; // [rsp+10h] [rbp-38h]\n unsigned int v8; // [rsp+1Ch] [rbp-2Ch]\n int i; // [rsp+20h] [rbp-28h]\n int j; // [rsp+24h] [rbp-24h]\n int k; // [rsp+28h] [rbp-20h]\n int m; // [rsp+2Ch] [rbp-1Ch]\n __int64 v13; // [rsp+30h] [rbp-18h]\n _BYTE *v14; // [rsp+38h] [rbp-10h]\n unsigned __int64 v15; // [rsp+40h] [rbp-8h]\n\n v7 = a1;\n v6 = a2;\n v15 = __readfsqword(0x28u);\n v8 = 0;\n v13 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 0x10uLL);\n while ( v5 != &v5[-(v2 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = alloca(v2 & 0xFFF);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)&v5[(v2 & 0xFFF) - 8] = *(_QWORD *)&v5[(v2 & 0xFFF) - 8];\n v14 = v5;\n for ( i = 0; i < v6; ++i )\n *(_DWORD *)&v14[4 * i] = *(_DWORD *)(4LL * i + v7);\n for ( j = 1; j < v6; ++j )\n {\n for ( k = 0; k < j; ++k )\n {\n if ( *(_DWORD *)(4LL * j + v7) > *(_DWORD *)(4LL * k + v7)\n && *(_DWORD *)&v14[4 * j] < *(_DWORD *)&v14[4 * k] + *(_DWORD *)(4LL * j + v7) )\n {\n *(_DWORD *)&v14[4 * j] = *(_DWORD *)&v14[4 * k] + *(_DWORD *)(4LL * j + v7);\n }\n }\n }\n for ( m = 0; m < v6; ++m )\n {\n if ( (signed int)v8 < *(_DWORD *)&v14[4 * m] )\n v8 = *(_DWORD *)&v14[4 * m];\n }\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2) {\n unsigned long long v2;\n void *v3;\n uint8_t v5[4];\n int v6;\n long long v7;\n unsigned int v8;\n int i;\n int j;\n int k;\n int m;\n long long v13;\n uint8_t *v14;\n unsigned long long v15;\n v7 = a1;\n v6 = a2;\n v15 = __readfsqword(40u);\n v8 = 0;\n v13 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 16uLL);\n while (v5 != &v5[-(v2 & 18446744073709547520LL)])\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)&v5[(v2 & 4095) - 8] = *(uint64_t *)&v5[(v2 & 4095) - 8];\n v14 = v5;\n for (i = 0; i < v6; ++i)\n *(uint32_t *)&v14[4 * i] = *(uint32_t *)(4LL * i + v7);\n for (j = 1; j < v6; ++j) {\n for (k = 0; k < j; ++k) {\n if (*(uint32_t *)(4LL * j + v7) > *(uint32_t *)(4LL * k + v7) &&\n *(uint32_t *)&v14[4 * j] <\n *(uint32_t *)&v14[4 * k] + *(uint32_t *)(4LL * j + v7)) {\n *(uint32_t *)&v14[4 * j] =\n *(uint32_t *)&v14[4 * k] + *(uint32_t *)(4LL * j + v7);\n }\n }\n }\n for (m = 0; m < v6; ++m) {\n if ((signed int)v8 < *(uint32_t *)&v14[4 * m])\n v8 = *(uint32_t *)&v14[4 * m];\n }\n return v8;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned long long v2;\n void *v3;\n uint8_t v5[4];\n int v6;\n long long v7;\n unsigned int v8;\n int i;\n int j;\n int k;\n int m;\n long long v13;\n uint8_t *v14;\n unsigned long long v15;\n v7 = a1;\n v6 = a2;\n v15 = __readfsqword(40u);\n v8 = 0;\n v13 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 16uLL);\n while (v5 != &v5[-(v2 & 18446744073709547520LL)])\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)&v5[(v2 & 4095) - 8] = *(uint64_t *)&v5[(v2 & 4095) - 8];\n v14 = v5;\n for (i = 0; i < v6; ++i)\n *(uint32_t *)&v14[4 * i] = *(uint32_t *)(4LL * i + v7);\n for (j = 1; j < v6; ++j) {\n for (k = 0; k < j; ++k) {\n if (*(uint32_t *)(4LL * j + v7) > *(uint32_t *)(4LL * k + v7) &&\n *(uint32_t *)&v14[4 * j] <\n *(uint32_t *)&v14[4 * k] + *(uint32_t *)(4LL * j + v7)) {\n *(uint32_t *)&v14[4 * j] =\n *(uint32_t *)&v14[4 * k] + *(uint32_t *)(4LL * j + v7);\n }\n }\n }\n for (m = 0; m < v6; ++m) {\n if ((signed int)v8 < *(uint32_t *)&v14[4 * m])\n v8 = *(uint32_t *)&v14[4 * m];\n }\n return v8;\n}" + }, + { + "index": 524, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int max = 0;\n int msis[n];\n for (int i = 0; i < n; i++) {\n msis[i] = arr[i];\n }\n for (int i = 1; i < n; i++) {\n for (int j = 0; j < i; j++) {\n if (arr[i] > arr[j] && msis[i] < msis[j] + arr[i]) {\n msis[i] = msis[j] + arr[i];\n }\n }\n }\n for (int i = 0; i < n; i++) {\n if (max < msis[i]) {\n max = msis[i];\n }\n }\n return max;\n}", + "test": "int main() {\n\n int arr1[] = {1, 101, 2, 3, 100, 4, 5};\n\n int arr2[] = {3, 4, 5, 10};\n\n int arr3[] = {10, 5, 4, 3};\n\n\n\n assert(func0(arr1, 7) == 106);\n\n assert(func0(arr2, 4) == 22);\n\n assert(func0(arr3, 4) == 10);\n\n \n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovslq %esi,%rax\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffffff0,%rdx\nand $0xfffffffffffff000,%rax\nmov %rsp,%rcx\nsub %rax,%rcx\nmov %rcx,%rax\ncmp %rax,%rsp\nje 11dc \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11c5 \nmov %rdx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 11f2 \norq $0x0,-0x8(%rsp,%rax,1)\nlea 0x3(%rsp),%r8\nmov %r8,%r9\nshr $0x2,%r9\nand $0xfffffffffffffffc,%r8\ntest %esi,%esi\njle 1221 \nlea -0x1(%rsi),%ecx\nmov $0x0,%eax\nmov (%rdi,%rax,4),%edx\nmov %edx,(%r8,%rax,4)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rcx,%rdx\njne 120e \ncmp $0x1,%esi\njle 126d \nlea -0x2(%rsi),%r10d\nadd $0x2,%r10\nmov $0x1,%edx\njmp 125f \nadd $0x1,%rax\ncmp %rdx,%rax\nje 1256 \ncmp (%rdi,%rax,4),%ecx\njle 1235 \nmov %ecx,%r9d\nadd (%r8,%rax,4),%r9d\ncmp %r9d,(%r8,%rdx,4)\njge 1235 \nmov %r9d,(%r8,%rdx,4)\njmp 1235 \nadd $0x1,%rdx\ncmp %r10,%rdx\nje 1276 \ntest %edx,%edx\njle 1256 \nmov (%rdi,%rdx,4),%ecx\nmov $0x0,%eax\njmp 123e \nje 12a4 \nmov $0x0,%edx\njmp 1291 \nmov $0x0,%eax\nmov $0x0,%edx\nmov (%r8,%rax,4),%ecx\ncmp %ecx,%edx\ncmovl %ecx,%edx\nadd $0x1,%rax\ncmp %eax,%esi\njg 1280 \nmov -0x8(%rbp),%rax\nxor %fs:0x28,%rax\njne 12bd \nmov %edx,%eax\nleaveq\nretq\ncmpl $0x0,0x0(,%r9,4)\nmov $0x0,%edx\ncmovns 0x0(,%r9,4),%edx\njmp 1291 \ncallq 1080 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov r11d, esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmovsxd r10, esi\nshl r10, 2\nlea rax, [r10+0Fh]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11C5:\ncmp rsp, rdx\njz short loc_11DC\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11C5\nloc_11DC:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11F2\nor [rsp+rax+10h+var_18], 0\nloc_11F2:\nmov rsi, rsp\ntest r11d, r11d\njle short loc_125E\nmov eax, 0\nloc_11FF:\nmov edx, [rdi+rax]\nmov [rsi+rax], edx\nadd rax, 4\ncmp r10, rax\njnz short loc_11FF\ncmp r11d, 1\njle short loc_1265\nmov edx, 4\nmov r9d, 1\njmp short loc_124F\nloc_1221:\nadd rax, 4\ncmp rdx, rax\njz short loc_1242\nloc_122A:\ncmp ecx, [rdi+rax]\njle short loc_1221\nmov r8d, ecx\nadd r8d, [rsi+rax]\ncmp [rsi+rdx], r8d\njge short loc_1221\nmov [rsi+rdx], r8d\njmp short loc_1221\nloc_1242:\nadd r9d, 1\nadd rdx, 4\ncmp r11d, r9d\njz short loc_1265\nloc_124F:\ntest r9d, r9d\njle short loc_1293\nmov ecx, [rdi+rdx]\nmov eax, 0\njmp short loc_122A\nloc_125E:\nmov edx, 0\njmp short loc_1280\nloc_1265:\nmov rax, rsi\nadd rsi, r10\nmov edx, 0\nloc_1270:\nmov ecx, [rax]\ncmp edx, ecx\ncmovl edx, ecx\nadd rax, 4\ncmp rax, rsi\njnz short loc_1270\nloc_1280:\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njnz short loc_129D\nmov eax, edx\nleave\nretn\nloc_1293:\nadd r9d, 1\nadd rdx, 4\njmp short loc_124F\nloc_129D:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // r10\n signed __int64 v3; // rax\n void *v4; // rsp\n __int64 v5; // rax\n __int64 v6; // rdx\n int i; // r9d\n __int64 v8; // rax\n int v9; // r8d\n int v10; // ecx\n unsigned int v11; // edx\n _BYTE *v12; // rax\n _BYTE v15[8]; // [rsp+8h] [rbp-10h] BYREF\n unsigned __int64 v16; // [rsp+10h] [rbp-8h]\n\n v16 = __readfsqword(0x28u);\n v2 = 4LL * a2;\n while ( v15 != &v15[-((v2 + 15) & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = ((_WORD)v2 + 15) & 0xFF0;\n v4 = alloca(v3);\n if ( (((_WORD)v2 + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v15[v3 - 8] = *(_QWORD *)&v15[v3 - 8];\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v5 = 0LL;\n do\n {\n *(_DWORD *)&v15[v5] = *(_DWORD *)(a1 + v5);\n v5 += 4LL;\n }\n while ( v2 != v5 );\n if ( a2 > 1 )\n {\n v6 = 4LL;\n for ( i = 1; i != a2; ++i )\n {\n while ( i <= 0 )\n {\n ++i;\n v6 += 4LL;\n }\n v10 = *(_DWORD *)(a1 + v6);\n v8 = 0LL;\n do\n {\n if ( v10 > *(_DWORD *)(a1 + v8) )\n {\n v9 = *(_DWORD *)&v15[v8] + v10;\n if ( *(_DWORD *)&v15[v6] < v9 )\n *(_DWORD *)&v15[v6] = v9;\n }\n v8 += 4LL;\n }\n while ( v6 != v8 );\n v6 += 4LL;\n }\n }\n v12 = v15;\n v11 = 0;\n do\n {\n if ( (signed int)v11 < *(_DWORD *)v12 )\n v11 = *(_DWORD *)v12;\n v12 += 4;\n }\n while ( v12 != &v15[v2] );\n }\n return v11;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov r11d, esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmovsxd r10, esi\nshl r10, 2\nlea rax, [r10+0Fh]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11C5:\ncmp rsp, rdx\njz short loc_11DC\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11C5\nloc_11DC:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11F2\nor [rsp+rax+10h+var_18], 0\nloc_11F2:\nmov rsi, rsp\ntest r11d, r11d\njle short loc_125E\nmov eax, 0\nloc_11FF:\nmov edx, [rdi+rax]\nmov [rsi+rax], edx\nadd rax, 4\ncmp r10, rax\njnz short loc_11FF\ncmp r11d, 1\njle short loc_1265\nmov edx, 4\nmov r9d, 1\njmp short loc_124F\nloc_1221:\nadd rax, 4\ncmp rdx, rax\njz short loc_1242\nloc_122A:\ncmp ecx, [rdi+rax]\njle short loc_1221\nmov r8d, ecx\nadd r8d, [rsi+rax]\ncmp [rsi+rdx], r8d\njge short loc_1221\nmov [rsi+rdx], r8d\njmp short loc_1221\nloc_1242:\nadd r9d, 1\nadd rdx, 4\ncmp r11d, r9d\njz short loc_1265\nloc_124F:\ntest r9d, r9d\njle short loc_1293\nmov ecx, [rdi+rdx]\nmov eax, 0\njmp short loc_122A\nloc_125E:\nmov edx, 0\njmp short loc_1280\nloc_1265:\nmov rax, rsi\nadd rsi, r10\nmov edx, 0\nloc_1270:\nmov ecx, [rax]\ncmp edx, ecx\ncmovl edx, ecx\nadd rax, 4\ncmp rax, rsi\njnz short loc_1270\nloc_1280:\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njnz short loc_129D\nmov eax, edx\nleave\nretn\nloc_1293:\nadd r9d, 1\nadd rdx, 4\njmp short loc_124F\nloc_129D:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2)\n{\n __int64 v2; // r10\n signed __int64 v3; // rax\n void *v4; // rsp\n __int64 v5; // rax\n __int64 v6; // rdx\n int i; // r9d\n __int64 v8; // rax\n int v9; // r8d\n int v10; // ecx\n unsigned int v11; // edx\n _BYTE *v12; // rax\n _BYTE v15[8]; // [rsp+8h] [rbp-10h] BYREF\n unsigned __int64 v16; // [rsp+10h] [rbp-8h]\n\n v16 = __readfsqword(0x28u);\n v2 = 4LL * a2;\n while ( v15 != &v15[-((v2 + 15) & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = ((_WORD)v2 + 15) & 0xFF0;\n v4 = alloca(v3);\n if ( (((_WORD)v2 + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v15[v3 - 8] = *(_QWORD *)&v15[v3 - 8];\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v5 = 0LL;\n do\n {\n *(_DWORD *)&v15[v5] = *(_DWORD *)(a1 + v5);\n v5 += 4LL;\n }\n while ( v2 != v5 );\n if ( a2 > 1 )\n {\n v6 = 4LL;\n for ( i = 1; i != a2; ++i )\n {\n while ( i <= 0 )\n {\n ++i;\n v6 += 4LL;\n }\n v10 = *(_DWORD *)(a1 + v6);\n v8 = 0LL;\n do\n {\n if ( v10 > *(_DWORD *)(a1 + v8) )\n {\n v9 = *(_DWORD *)&v15[v8] + v10;\n if ( *(_DWORD *)&v15[v6] < v9 )\n *(_DWORD *)&v15[v6] = v9;\n }\n v8 += 4LL;\n }\n while ( v6 != v8 );\n v6 += 4LL;\n }\n }\n v12 = v15;\n v11 = 0;\n do\n {\n if ( (signed int)v11 < *(_DWORD *)v12 )\n v11 = *(_DWORD *)v12;\n v12 += 4;\n }\n while ( v12 != &v15[v2] );\n }\n return v11;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2) {\n long long v2;\n signed long long v3;\n void *v4;\n long long v5;\n long long v6;\n int i;\n long long v8;\n int v9;\n int v10;\n unsigned int v11;\n uint8_t *v12;\n uint8_t v15[8];\n unsigned long long v16;\n v16 = __readfsqword(40u);\n v2 = 4LL * a2;\n while (v15 != &v15[-((v2 + 15) & 18446744073709547520LL)])\n ;\n v3 = ((unsigned short)v2 + 15) & 4080;\n v4 = alloca(v3);\n if ((((unsigned short)v2 + 15) & 4080) != 0)\n *(uint64_t *)&v15[v3 - 8] = *(uint64_t *)&v15[v3 - 8];\n if (a2 <= 0) {\n return 0;\n } else {\n v5 = 0LL;\n do {\n *(uint32_t *)&v15[v5] = *(uint32_t *)(a1 + v5);\n v5 += 4LL;\n } while (v2 != v5);\n if (a2 > 1) {\n v6 = 4LL;\n for (i = 1; i != a2; ++i) {\n while (i <= 0) {\n ++i;\n v6 += 4LL;\n }\n v10 = *(uint32_t *)(a1 + v6);\n v8 = 0LL;\n do {\n if (v10 > *(uint32_t *)(a1 + v8)) {\n v9 = *(uint32_t *)&v15[v8] + v10;\n if (*(uint32_t *)&v15[v6] < v9) *(uint32_t *)&v15[v6] = v9;\n }\n v8 += 4LL;\n } while (v6 != v8);\n v6 += 4LL;\n }\n }\n v12 = v15;\n v11 = 0;\n do {\n if ((signed int)v11 < *(uint32_t *)v12) v11 = *(uint32_t *)v12;\n v12 += 4;\n } while (v12 != &v15[v2]);\n }\n return v11;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n signed long long v3;\n void *v4;\n long long v5;\n long long v6;\n int i;\n long long v8;\n int v9;\n int v10;\n unsigned int v11;\n uint8_t *v12;\n uint8_t v15[8];\n unsigned long long v16;\n v16 = __readfsqword(40u);\n v2 = 4LL * a2;\n while (v15 != &v15[-((v2 + 15) & 18446744073709547520LL)])\n ;\n v3 = ((unsigned short)v2 + 15) & 4080;\n v4 = alloca(v3);\n if ((((unsigned short)v2 + 15) & 4080) != 0)\n *(uint64_t *)&v15[v3 - 8] = *(uint64_t *)&v15[v3 - 8];\n if (a2 <= 0) {\n return 0;\n } else {\n v5 = 0LL;\n do {\n *(uint32_t *)&v15[v5] = *(uint32_t *)(a1 + v5);\n v5 += 4LL;\n } while (v2 != v5);\n if (a2 > 1) {\n v6 = 4LL;\n for (i = 1; i != a2; ++i) {\n while (i <= 0) {\n ++i;\n v6 += 4LL;\n }\n v10 = *(uint32_t *)(a1 + v6);\n v8 = 0LL;\n do {\n if (v10 > *(uint32_t *)(a1 + v8)) {\n v9 = *(uint32_t *)&v15[v8] + v10;\n if (*(uint32_t *)&v15[v6] < v9) *(uint32_t *)&v15[v6] = v9;\n }\n v8 += 4LL;\n } while (v6 != v8);\n v6 += 4LL;\n }\n }\n v12 = v15;\n v11 = 0;\n do {\n if ((signed int)v11 < *(uint32_t *)v12) v11 = *(uint32_t *)v12;\n v12 += 4;\n } while (v12 != &v15[v2]);\n }\n return v11;\n}" + }, + { + "index": 524, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int max = 0;\n int msis[n];\n for (int i = 0; i < n; i++) {\n msis[i] = arr[i];\n }\n for (int i = 1; i < n; i++) {\n for (int j = 0; j < i; j++) {\n if (arr[i] > arr[j] && msis[i] < msis[j] + arr[i]) {\n msis[i] = msis[j] + arr[i];\n }\n }\n }\n for (int i = 0; i < n; i++) {\n if (max < msis[i]) {\n max = msis[i];\n }\n }\n return max;\n}", + "test": "int main() {\n\n int arr1[] = {1, 101, 2, 3, 100, 4, 5};\n\n int arr2[] = {3, 4, 5, 10};\n\n int arr3[] = {10, 5, 4, 3};\n\n\n\n assert(func0(arr1, 7) == 106);\n\n assert(func0(arr2, 4) == 22);\n\n assert(func0(arr3, 4) == 10);\n\n \n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovslq %esi,%rax\nmov %rsp,%rcx\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rcx\nand $0xfffffffffffffff0,%rdx\nmov %rcx,%rax\ncmp %rax,%rsp\nje 1336 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 1321 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 13ef \nlea 0x3(%rsp),%r8\nmov %r8,%r10\nand $0xfffffffffffffffc,%r8\nshr $0x2,%r10\ntest %esi,%esi\njle 13fa \nlea -0x1(%rsi),%ecx\nxor %eax,%eax\nnopl (%rax)\nmov (%rdi,%rax,4),%edx\nmov %edx,(%r8,%rax,4)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rdx,%rcx\njne 1368 \ncmp $0x1,%esi\njle 13fa \nlea -0x2(%rsi),%r10d\nmov $0x1,%edx\nadd $0x2,%r10\nnopl (%rax)\nmov (%rdi,%rdx,4),%ecx\nxor %eax,%eax\nnopl (%rax)\ncmp (%rdi,%rax,4),%ecx\njle 13ae \nmov (%r8,%rax,4),%r9d\nadd %ecx,%r9d\ncmp %r9d,(%r8,%rdx,4)\njge 13ae \nmov %r9d,(%r8,%rdx,4)\nadd $0x1,%rax\ncmp %rax,%rdx\njne 1398 \nadd $0x1,%rdx\ncmp %r10,%rdx\njne 1390 \nxor %eax,%eax\nxor %r9d,%r9d\nnopl (%rax)\nmov (%r8,%rax,4),%edx\ncmp %edx,%r9d\ncmovl %edx,%r9d\nadd $0x1,%rax\ncmp %eax,%esi\njg 13c8 \nmov -0x8(%rbp),%rax\nxor %fs:0x28,%rax\njne 141e \nleaveq\nmov %r9d,%eax\nretq\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 1348 \ncmp $0x1,%esi\nje 1404 \nxor %r9d,%r9d\njmp 13db \ncmpl $0x0,0x0(,%r10,4)\nmov $0x0,%r9d\ncmovns 0x0(,%r10,4),%r9d\njmp 13db \ncallq 1080 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r14\npush r13\nmovsxd r13, esi\npush r12\nmov r14, r13\nshl r13, 2\npush rbx\nmov rbx, rdi\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nlea rax, [r13+0Fh]\nmov rcx, rsp\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_1330\nloc_131B:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rcx\njnz short loc_131B\nloc_1330:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_13F4\nloc_1342:\nmov rdi, rsp; dest\ntest r14d, r14d\njle loc_13FF\nmov r12d, r14d\nmov rsi, rbx; src\nshl r12, 2\nmov rdx, r12; n\ncall _memcpy\nmov rdi, rax\ncmp r14d, 1\njz short loc_139C\nmov edx, 4\nxchg ax, ax\nloc_1370:\nmov ecx, [rbx+rdx]\nxor eax, eax\nnop dword ptr [rax]\nloc_1378:\ncmp ecx, [rbx+rax]\njle short loc_138A\nmov esi, [rdi+rax]\nadd esi, ecx\ncmp [rdi+rdx], esi\njge short loc_138A\nmov [rdi+rdx], esi\nloc_138A:\nadd rax, 4\ncmp rax, rdx\njnz short loc_1378\nadd rdx, 4\ncmp rdx, r12\njnz short loc_1370\nloc_139C:\nlea rcx, [rdi+r13]\nxor eax, eax\nand r13d, 4\njz short loc_13C0\nmov edx, [rdi]\ncmp eax, edx\ncmovl eax, edx\nadd rdi, 4\ncmp rdi, rcx\njz short loc_13D8\nnop dword ptr [rax+rax+00000000h]\nloc_13C0:\nmov edx, [rdi]\ncmp eax, edx\ncmovl eax, edx\nmov edx, [rdi+4]\ncmp eax, edx\ncmovl eax, edx\nadd rdi, 8\ncmp rdi, rcx\njnz short loc_13C0\nloc_13D8:\nmov rdx, [rbp+var_28]\nsub rdx, fs:28h\njnz short loc_1403\nlea rsp, [rbp-20h]\npop rbx\npop r12\npop r13\npop r14\npop rbp\nretn\nloc_13F4:\nor [rsp+rdx+1030h+var_1038], 0\njmp loc_1342\nloc_13FF:\nxor eax, eax\njmp short loc_13D8\nloc_1403:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(char *src, int a2)\n{\n __int64 v2; // r13\n _BYTE *v4; // rcx\n signed __int64 v5; // rdx\n void *v6; // rsp\n size_t v7; // r12\n int *v8; // rdi\n __int64 v9; // rdx\n int v10; // ecx\n unsigned __int64 v11; // rax\n int v12; // esi\n int *v13; // rcx\n __int64 result; // rax\n int v15; // edx\n _BYTE v17[4088]; // [rsp+8h] [rbp-1030h] BYREF\n _QWORD v18[6]; // [rsp+1008h] [rbp-30h] BYREF\n\n v2 = 4LL * a2;\n v18[1] = __readfsqword(0x28u);\n v4 = (char *)v18 - ((v2 + 15) & 0xFFFFFFFFFFFFF000LL);\n if ( v18 != (_QWORD *)v4 )\n {\n while ( v17 != v4 )\n ;\n }\n v5 = ((_WORD)v2 + 15) & 0xFF0;\n v6 = alloca(v5);\n if ( (((_WORD)v2 + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v17[v5 - 8] = *(_QWORD *)&v17[v5 - 8];\n if ( a2 <= 0 )\n return 0LL;\n v7 = 4LL * (unsigned int)a2;\n v8 = (int *)memcpy(v17, src, v7);\n if ( a2 != 1 )\n {\n v9 = 4LL;\n do\n {\n v10 = *(_DWORD *)&src[v9];\n v11 = 0LL;\n do\n {\n if ( v10 > *(_DWORD *)&src[v11] )\n {\n v12 = v10 + v8[v11 / 4];\n if ( v8[(unsigned __int64)v9 / 4] < v12 )\n v8[(unsigned __int64)v9 / 4] = v12;\n }\n v11 += 4LL;\n }\n while ( v11 != v9 );\n v9 += 4LL;\n }\n while ( v9 != v7 );\n }\n v13 = &v8[(unsigned __int64)v2 / 4];\n result = 0LL;\n if ( (v2 & 4) == 0 )\n goto LABEL_27;\n if ( *v8 > 0 )\n result = (unsigned int)*v8;\n if ( ++v8 != v13 )\n {\nLABEL_27:\n do\n {\n if ( (int)result < *v8 )\n result = (unsigned int)*v8;\n v15 = v8[1];\n if ( (int)result < v15 )\n result = (unsigned int)v15;\n v8 += 2;\n }\n while ( v8 != v13 );\n }\n return result;\n}", + "ida_strip_asm": "sub_12D0:\nendbr64\npush rbp\nmov rbp, rsp\npush r14\npush r13\nmovsxd r13, esi\npush r12\nmov r14, r13\nshl r13, 2\npush rbx\nmov rbx, rdi\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nlea rax, [r13+0Fh]\nmov rcx, rsp\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_1330\nloc_131B:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rcx\njnz short loc_131B\nloc_1330:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_13F4\nloc_1342:\nmov rdi, rsp; dest\ntest r14d, r14d\njle loc_13FF\nmov r12d, r14d\nmov rsi, rbx; src\nshl r12, 2\nmov rdx, r12; n\ncall _memcpy\nmov rdi, rax\ncmp r14d, 1\njz short loc_139C\nmov edx, 4\nxchg ax, ax\nloc_1370:\nmov ecx, [rbx+rdx]\nxor eax, eax\nnop dword ptr [rax]\nloc_1378:\ncmp ecx, [rbx+rax]\njle short loc_138A\nmov esi, [rdi+rax]\nadd esi, ecx\ncmp [rdi+rdx], esi\njge short loc_138A\nmov [rdi+rdx], esi\nloc_138A:\nadd rax, 4\ncmp rax, rdx\njnz short loc_1378\nadd rdx, 4\ncmp rdx, r12\njnz short loc_1370\nloc_139C:\nlea rcx, [rdi+r13]\nxor eax, eax\nand r13d, 4\njz short loc_13C0\nmov edx, [rdi]\ncmp eax, edx\ncmovl eax, edx\nadd rdi, 4\ncmp rdi, rcx\njz short loc_13D8\nnop dword ptr [rax+rax+00000000h]\nloc_13C0:\nmov edx, [rdi]\ncmp eax, edx\ncmovl eax, edx\nmov edx, [rdi+4]\ncmp eax, edx\ncmovl eax, edx\nadd rdi, 8\ncmp rdi, rcx\njnz short loc_13C0\nloc_13D8:\nmov rdx, [rbp+var_28]\nsub rdx, fs:28h\njnz short loc_1403\nlea rsp, [rbp-20h]\npop rbx\npop r12\npop r13\npop r14\npop rbp\nretn\nloc_13F4:\nor [rsp+rdx+1030h+var_1038], 0\njmp loc_1342\nloc_13FF:\nxor eax, eax\njmp short loc_13D8\nloc_1403:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12D0(char *src, int a2)\n{\n __int64 v2; // r13\n _BYTE *v4; // rcx\n signed __int64 v5; // rdx\n void *v6; // rsp\n size_t v7; // r12\n int *v8; // rdi\n __int64 v9; // rdx\n int v10; // ecx\n unsigned __int64 v11; // rax\n int v12; // esi\n int *v13; // rcx\n __int64 result; // rax\n int v15; // edx\n _BYTE v17[4088]; // [rsp+8h] [rbp-1030h] BYREF\n _QWORD v18[6]; // [rsp+1008h] [rbp-30h] BYREF\n\n v2 = 4LL * a2;\n v18[1] = __readfsqword(0x28u);\n v4 = (char *)v18 - ((v2 + 15) & 0xFFFFFFFFFFFFF000LL);\n if ( v18 != (_QWORD *)v4 )\n {\n while ( v17 != v4 )\n ;\n }\n v5 = ((_WORD)v2 + 15) & 0xFF0;\n v6 = alloca(v5);\n if ( (((_WORD)v2 + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v17[v5 - 8] = *(_QWORD *)&v17[v5 - 8];\n if ( a2 <= 0 )\n return 0LL;\n v7 = 4LL * (unsigned int)a2;\n v8 = (int *)memcpy(v17, src, v7);\n if ( a2 != 1 )\n {\n v9 = 4LL;\n do\n {\n v10 = *(_DWORD *)&src[v9];\n v11 = 0LL;\n do\n {\n if ( v10 > *(_DWORD *)&src[v11] )\n {\n v12 = v10 + v8[v11 / 4];\n if ( v8[(unsigned __int64)v9 / 4] < v12 )\n v8[(unsigned __int64)v9 / 4] = v12;\n }\n v11 += 4LL;\n }\n while ( v11 != v9 );\n v9 += 4LL;\n }\n while ( v9 != v7 );\n }\n v13 = &v8[(unsigned __int64)v2 / 4];\n result = 0LL;\n if ( (v2 & 4) == 0 )\n goto LABEL_27;\n if ( *v8 > 0 )\n result = (unsigned int)*v8;\n if ( ++v8 != v13 )\n {\nLABEL_27:\n do\n {\n if ( (int)result < *v8 )\n result = (unsigned int)*v8;\n v15 = v8[1];\n if ( (int)result < v15 )\n result = (unsigned int)v15;\n v8 += 2;\n }\n while ( v8 != v13 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12D0(char *src, int a2) {\n long long v2;\n uint8_t *v4;\n signed long long v5;\n void *v6;\n unsigned int v7;\n int *v8;\n long long v9;\n int v10;\n unsigned long long v11;\n int v12;\n int *v13;\n long long result;\n int v15;\n uint8_t v17[4088];\n uint64_t v18[6];\n v2 = 4LL * a2;\n v18[1] = __readfsqword(40u);\n v4 = (char *)v18 - ((v2 + 15) & 18446744073709547520LL);\n if (v18 != (uint64_t *)v4) {\n while (v17 != v4)\n ;\n }\n v5 = ((unsigned short)v2 + 15) & 4080;\n v6 = alloca(v5);\n if ((((unsigned short)v2 + 15) & 4080) != 0)\n *(uint64_t *)&v17[v5 - 8] = *(uint64_t *)&v17[v5 - 8];\n if (a2 <= 0) return 0LL;\n v7 = 4LL * (unsigned int)a2;\n v8 = (int *)memcpy(v17, src, v7);\n if (a2 != 1) {\n v9 = 4LL;\n do {\n v10 = *(uint32_t *)&src[v9];\n v11 = 0LL;\n do {\n if (v10 > *(uint32_t *)&src[v11]) {\n v12 = v10 + v8[v11 / 4];\n if (v8[(unsigned long long)v9 / 4] < v12)\n v8[(unsigned long long)v9 / 4] = v12;\n }\n v11 += 4LL;\n } while (v11 != v9);\n v9 += 4LL;\n } while (v9 != v7);\n }\n v13 = &v8[(unsigned long long)v2 / 4];\n result = 0LL;\n if ((v2 & 4) == 0) goto LABEL_27;\n if (*v8 > 0) result = (unsigned int)*v8;\n if (++v8 != v13) {\n LABEL_27:\n do {\n if ((int)result < *v8) result = (unsigned int)*v8;\n v15 = v8[1];\n if ((int)result < v15) result = (unsigned int)v15;\n v8 += 2;\n } while (v8 != v13);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(char *src, int a2) {\n long long v2;\n uint8_t *v4;\n signed long long v5;\n void *v6;\n unsigned int v7;\n int *v8;\n long long v9;\n int v10;\n unsigned long long v11;\n int v12;\n int *v13;\n long long result;\n int v15;\n uint8_t v17[4088];\n uint64_t v18[6];\n v2 = 4LL * a2;\n v18[1] = __readfsqword(40u);\n v4 = (char *)v18 - ((v2 + 15) & 18446744073709547520LL);\n if (v18 != (uint64_t *)v4) {\n while (v17 != v4)\n ;\n }\n v5 = ((unsigned short)v2 + 15) & 4080;\n v6 = alloca(v5);\n if ((((unsigned short)v2 + 15) & 4080) != 0)\n *(uint64_t *)&v17[v5 - 8] = *(uint64_t *)&v17[v5 - 8];\n if (a2 <= 0) return 0LL;\n v7 = 4LL * (unsigned int)a2;\n v8 = (int *)memcpy(v17, src, v7);\n if (a2 != 1) {\n v9 = 4LL;\n do {\n v10 = *(uint32_t *)&src[v9];\n v11 = 0LL;\n do {\n if (v10 > *(uint32_t *)&src[v11]) {\n v12 = v10 + v8[v11 / 4];\n if (v8[(unsigned long long)v9 / 4] < v12)\n v8[(unsigned long long)v9 / 4] = v12;\n }\n v11 += 4LL;\n } while (v11 != v9);\n v9 += 4LL;\n } while (v9 != v7);\n }\n v13 = &v8[(unsigned long long)v2 / 4];\n result = 0LL;\n if ((v2 & 4) == 0) goto LABEL_27;\n if (*v8 > 0) result = (unsigned int)*v8;\n if (++v8 != v13) {\n LABEL_27:\n do {\n if ((int)result < *v8) result = (unsigned int)*v8;\n v15 = v8[1];\n if ((int)result < v15) result = (unsigned int)v15;\n v8 += 2;\n } while (v8 != v13);\n }\n return result;\n}" + }, + { + "index": 524, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int max = 0;\n int msis[n];\n for (int i = 0; i < n; i++) {\n msis[i] = arr[i];\n }\n for (int i = 1; i < n; i++) {\n for (int j = 0; j < i; j++) {\n if (arr[i] > arr[j] && msis[i] < msis[j] + arr[i]) {\n msis[i] = msis[j] + arr[i];\n }\n }\n }\n for (int i = 0; i < n; i++) {\n if (max < msis[i]) {\n max = msis[i];\n }\n }\n return max;\n}", + "test": "int main() {\n\n int arr1[] = {1, 101, 2, 3, 100, 4, 5};\n\n int arr2[] = {3, 4, 5, 10};\n\n int arr3[] = {10, 5, 4, 3};\n\n\n\n assert(func0(arr1, 7) == 106);\n\n assert(func0(arr2, 4) == 22);\n\n assert(func0(arr3, 4) == 10);\n\n \n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r13\nmov %esi,%r13d\npush %r12\nmov %rdi,%r12\npush %rbx\nsub $0x18,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x28(%rbp)\nxor %eax,%eax\nmovslq %esi,%rax\nmov %rsp,%rbx\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rbx\nand $0xfffffffffffffff0,%rdx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 1331 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 131c \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 14a8 \nlea 0x3(%rsp),%rdi\nmov %rdi,%rbx\nand $0xfffffffffffffffc,%rdi\nshr $0x2,%rbx\ntest %r13d,%r13d\njle 14b3 \nlea -0x1(%r13),%eax\nmov %r12,%rsi\nlea 0x4(,%rax,4),%rdx\ncallq 10b0 \nmov %rax,%rdi\ncmp $0x1,%r13d\njle 14b3 \nlea -0x2(%r13),%r8d\nmov $0x1,%edx\nadd $0x2,%r8\nnopw 0x0(%rax,%rax,1)\nmov (%r12,%rdx,4),%ecx\nxor %eax,%eax\nnopw %cs:0x0(%rax,%rax,1)\ncmp (%r12,%rax,4),%ecx\njle 13b3 \nmov (%rdi,%rax,4),%esi\nadd %ecx,%esi\ncmp %esi,(%rdi,%rdx,4)\njge 13b3 \nmov %esi,(%rdi,%rdx,4)\nadd $0x1,%rax\ncmp %rdx,%rax\njne 13a0 \nlea 0x1(%rax),%rdx\ncmp %r8,%rdx\njne 1390 \ntest %r13d,%r13d\nmov $0x1,%ecx\ncmovg %r13d,%ecx\ncmp $0x3,%r13d\njle 14bd \nmov %ecx,%edx\npxor %xmm2,%xmm2\nmov %rdi,%rax\nshr $0x2,%edx\nshl $0x4,%rdx\nadd %rdi,%rdx\nxchg %ax,%ax\nmovdqu (%rax),%xmm0\nadd $0x10,%rax\nmovdqa %xmm0,%xmm1\npcmpgtd %xmm2,%xmm1\npand %xmm1,%xmm0\npandn %xmm2,%xmm1\nmovdqa %xmm1,%xmm2\npor %xmm0,%xmm2\ncmp %rdx,%rax\njne 13f0 \nmovdqa %xmm2,%xmm1\nmov %ecx,%edx\npsrldq $0x8,%xmm1\nand $0xfffffffc,%edx\nand $0x3,%ecx\nmovdqa %xmm1,%xmm0\npcmpgtd %xmm2,%xmm0\npand %xmm0,%xmm1\npandn %xmm2,%xmm0\npor %xmm0,%xmm1\nmovdqa %xmm1,%xmm2\npsrldq $0x4,%xmm2\nmovdqa %xmm2,%xmm0\npcmpgtd %xmm1,%xmm0\npand %xmm0,%xmm2\npandn %xmm1,%xmm0\npor %xmm2,%xmm0\nmovd %xmm0,%eax\nje 148e \nmovslq %edx,%rcx\nmov (%rdi,%rcx,4),%ecx\ncmp %ecx,%eax\ncmovl %ecx,%eax\nadd $0x1,%edx\ncmp %edx,%r13d\njle 148e \nmovslq %edx,%rcx\nmov (%rdi,%rcx,4),%ecx\ncmp %ecx,%eax\ncmovl %ecx,%eax\nadd $0x1,%edx\ncmp %edx,%r13d\njle 148e \nmovslq %edx,%rdx\nmov (%rdi,%rdx,4),%edx\ncmp %edx,%eax\ncmovl %edx,%eax\nmov -0x28(%rbp),%rbx\nxor %fs:0x28,%rbx\njne 14f1 \nlea -0x18(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %rbp\nretq\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 1343 \ncmp $0x1,%r13d\nje 14da \nxor %eax,%eax\njmp 148e \nmov 0x0(,%rbx,4),%eax\nmov $0x1,%edx\ntest %eax,%eax\nmov $0x0,%eax\ncmovns 0x0(,%rbx,4),%eax\njmp 1470 \ncmpl $0x0,0x0(,%rbx,4)\nmov $0x0,%eax\ncmovns 0x0(,%rbx,4),%eax\njmp 148e \ncallq 1090 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\nmov r14d, esi\npush r13\nmov r13, rdi\npush r12\npush rbx\nsub rsp, 28h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nmovsxd rax, esi\nmov rcx, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_1332\nloc_131D:\nsub rsp, 1000h\nor [rsp+1050h+var_58], 0\ncmp rsp, rcx\njnz short loc_131D\nloc_1332:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_14A6\nloc_1344:\nlea rdi, [rsp+1050h+var_104D]\nmov rax, rdi\nand rdi, 0FFFFFFFFFFFFFFFCh; dest\nshr rax, 2\nmov r15, rdi\nmov [rbp+var_48], rax\ntest r14d, r14d\njle loc_14B1\nmov r8d, r14d\nmov rsi, r13; src\nlea ebx, [r14-1]\nlea r12, ds:0[r8*4]\nmov rdx, r12; n\ncall _memcpy\nmov rdi, r15\ncmp r14d, 1\njz loc_14C9\nmov edx, 4\nloc_1390:\nmov ecx, [r13+rdx+0]\nxor eax, eax\nnop word ptr [rax+rax+00000000h]\nloc_13A0:\ncmp ecx, [r13+rax+0]\njle short loc_13B4\nmov esi, [rdi+rax]\nadd esi, ecx\ncmp [rdi+rdx], esi\njge short loc_13B4\nmov [rdi+rdx], esi\nloc_13B4:\nadd rax, 4\ncmp rax, rdx\njnz short loc_13A0\nlea rdx, [rax+4]\ncmp rdx, r12\njnz short loc_1390\ncmp ebx, 2\njbe loc_14B5\nmov edx, r14d\nmov rax, rdi\npxor xmm2, xmm2\nshr edx, 2\nshl rdx, 4\nadd rdx, rdi\nnop dword ptr [rax+rax+00h]\nloc_13E8:\nmovdqu xmm0, xmmword ptr [rax]\nadd rax, 10h\nmovdqa xmm1, xmm0\npcmpgtd xmm1, xmm2\npand xmm0, xmm1\npandn xmm1, xmm2\nmovdqa xmm2, xmm1\npor xmm2, xmm0\ncmp rdx, rax\njnz short loc_13E8\nmovdqa xmm0, xmm2\nmov edx, r14d\npsrldq xmm0, 8\nand edx, 0FFFFFFFCh\nmovdqa xmm1, xmm0\npcmpgtd xmm1, xmm2\npand xmm0, xmm1\npandn xmm1, xmm2\npor xmm1, xmm0\nmovdqa xmm2, xmm1\npsrldq xmm2, 4\nmovdqa xmm0, xmm2\npcmpgtd xmm0, xmm1\npand xmm2, xmm0\npandn xmm0, xmm1\npor xmm0, xmm2\nmovd eax, xmm0\ntest r14b, 3\njz short loc_1488\nmovsxd rcx, edx\nlea r15, [rdi+rcx*4]\nmov ecx, [r15]\ncmp eax, ecx\ncmovl eax, ecx\nlea ecx, [rdx+1]\ncmp r14d, ecx\njle short loc_1488\nloc_146E:\nmov ecx, [r15+4]\ncmp eax, ecx\ncmovl eax, ecx\nadd edx, 2\ncmp r14d, edx\njle short loc_1488\nmov edx, [r15+8]\ncmp eax, edx\ncmovl eax, edx\nloc_1488:\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_14DD\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_14A6:\nor [rsp+rdx+1050h+var_1058], 0\njmp loc_1344\nloc_14B1:\nxor eax, eax\njmp short loc_1488\nloc_14B5:\nmov rax, [rbp+var_48]\nxor edx, edx\nmov eax, ds:dword_0[rax*4]\ntest eax, eax\ncmovs eax, edx\njmp short loc_146E\nloc_14C9:\nmov rax, [rbp+var_48]\nxor edx, edx\nmov eax, ds:dword_0[rax*4]\ntest eax, eax\ncmovs eax, edx\njmp short loc_1488\nloc_14DD:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(char *src, int a2)\n{\n __int64 v3; // rdx\n __int64 *v4; // rcx\n __int16 v5; // dx\n signed __int64 v6; // rdx\n void *v7; // rsp\n int *v8; // r15\n unsigned int v9; // ebx\n size_t v10; // r12\n __int64 v11; // rdx\n int v12; // ecx\n __int64 v13; // rax\n int v14; // esi\n const __m128i *v15; // rax\n __m128i v16; // xmm2\n __m128i v17; // xmm0\n __m128i v18; // xmm1\n __m128i v19; // xmm0\n unsigned int v20; // edx\n __m128i v21; // xmm1\n __m128i v22; // xmm1\n __m128i v23; // xmm2\n __m128i v24; // xmm0\n __int64 result; // rax\n int v26; // ecx\n int v27; // edx\n _BYTE v29[3]; // [rsp+8h] [rbp-1050h] BYREF\n char v30; // [rsp+Bh] [rbp-104Dh] BYREF\n __int64 v31; // [rsp+1008h] [rbp-50h] BYREF\n unsigned __int64 v32; // [rsp+1010h] [rbp-48h]\n unsigned __int64 v33; // [rsp+1020h] [rbp-38h]\n\n v33 = __readfsqword(0x28u);\n v3 = 4LL * a2 + 15;\n v4 = (__int64 *)((char *)&v31 - (v3 & 0xFFFFFFFFFFFFF000LL));\n v5 = v3 & 0xFFF0;\n if ( &v31 != v4 )\n {\n while ( v29 != (_BYTE *)v4 )\n ;\n }\n v6 = v5 & 0xFFF;\n v7 = alloca(v6);\n if ( v6 )\n *(_QWORD *)&v29[v6 - 8] = *(_QWORD *)&v29[v6 - 8];\n v8 = (int *)v29;\n v32 = (unsigned __int64)&v30 >> 2;\n if ( a2 <= 0 )\n return 0LL;\n v9 = a2 - 1;\n v10 = 4LL * (unsigned int)a2;\n memcpy(v29, src, v10);\n if ( a2 == 1 )\n {\n result = *(unsigned int *)(4 * v32);\n if ( (int)result < 0 )\n return 0LL;\n }\n else\n {\n v11 = 4LL;\n do\n {\n v12 = *(_DWORD *)&src[v11];\n v13 = 0LL;\n do\n {\n if ( v12 > *(_DWORD *)&src[v13] )\n {\n v14 = v12 + *(_DWORD *)&v29[v13];\n if ( *(_DWORD *)&v29[v11] < v14 )\n *(_DWORD *)&v29[v11] = v14;\n }\n v13 += 4LL;\n }\n while ( v13 != v11 );\n v11 = v13 + 4;\n }\n while ( v13 + 4 != v10 );\n if ( v9 <= 2 )\n {\n v20 = 0;\n result = *(unsigned int *)(4 * v32);\n if ( (int)result < 0 )\n result = 0LL;\n goto LABEL_21;\n }\n v15 = (const __m128i *)v29;\n v16 = 0LL;\n do\n {\n v17 = _mm_loadu_si128(v15++);\n v18 = _mm_cmpgt_epi32(v17, v16);\n v16 = _mm_or_si128(_mm_andnot_si128(v18, v16), _mm_and_si128(v17, v18));\n }\n while ( &v29[16 * ((unsigned int)a2 >> 2)] != (_BYTE *)v15 );\n v19 = _mm_srli_si128(v16, 8);\n v20 = a2 & 0xFFFFFFFC;\n v21 = _mm_cmpgt_epi32(v19, v16);\n v22 = _mm_or_si128(_mm_andnot_si128(v21, v16), _mm_and_si128(v19, v21));\n v23 = _mm_srli_si128(v22, 4);\n v24 = _mm_cmpgt_epi32(v23, v22);\n result = (unsigned int)_mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v24, v22), _mm_and_si128(v23, v24)));\n if ( (a2 & 3) != 0 )\n {\n v8 = (int *)&v29[4 * v20];\n if ( (int)result < *v8 )\n result = (unsigned int)*v8;\n if ( a2 > (int)(v20 + 1) )\n {\nLABEL_21:\n v26 = v8[1];\n if ( (int)result < v26 )\n result = (unsigned int)v26;\n if ( a2 > (int)(v20 + 2) )\n {\n v27 = v8[2];\n if ( (int)result < v27 )\n return (unsigned int)v27;\n }\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_12D0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\nmov r14d, esi\npush r13\nmov r13, rdi\npush r12\npush rbx\nsub rsp, 28h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nmovsxd rax, esi\nmov rcx, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_1332\nloc_131D:\nsub rsp, 1000h\nor [rsp+1050h+var_58], 0\ncmp rsp, rcx\njnz short loc_131D\nloc_1332:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_14A6\nloc_1344:\nlea rdi, [rsp+1050h+var_104D]\nmov rax, rdi\nand rdi, 0FFFFFFFFFFFFFFFCh; dest\nshr rax, 2\nmov r15, rdi\nmov [rbp+var_48], rax\ntest r14d, r14d\njle loc_14B1\nmov r8d, r14d\nmov rsi, r13; src\nlea ebx, [r14-1]\nlea r12, ds:0[r8*4]\nmov rdx, r12; n\ncall _memcpy\nmov rdi, r15\ncmp r14d, 1\njz loc_14C9\nmov edx, 4\nloc_1390:\nmov ecx, [r13+rdx+0]\nxor eax, eax\nnop word ptr [rax+rax+00000000h]\nloc_13A0:\ncmp ecx, [r13+rax+0]\njle short loc_13B4\nmov esi, [rdi+rax]\nadd esi, ecx\ncmp [rdi+rdx], esi\njge short loc_13B4\nmov [rdi+rdx], esi\nloc_13B4:\nadd rax, 4\ncmp rax, rdx\njnz short loc_13A0\nlea rdx, [rax+4]\ncmp rdx, r12\njnz short loc_1390\ncmp ebx, 2\njbe loc_14B5\nmov edx, r14d\nmov rax, rdi\npxor xmm2, xmm2\nshr edx, 2\nshl rdx, 4\nadd rdx, rdi\nnop dword ptr [rax+rax+00h]\nloc_13E8:\nmovdqu xmm0, xmmword ptr [rax]\nadd rax, 10h\nmovdqa xmm1, xmm0\npcmpgtd xmm1, xmm2\npand xmm0, xmm1\npandn xmm1, xmm2\nmovdqa xmm2, xmm1\npor xmm2, xmm0\ncmp rdx, rax\njnz short loc_13E8\nmovdqa xmm0, xmm2\nmov edx, r14d\npsrldq xmm0, 8\nand edx, 0FFFFFFFCh\nmovdqa xmm1, xmm0\npcmpgtd xmm1, xmm2\npand xmm0, xmm1\npandn xmm1, xmm2\npor xmm1, xmm0\nmovdqa xmm2, xmm1\npsrldq xmm2, 4\nmovdqa xmm0, xmm2\npcmpgtd xmm0, xmm1\npand xmm2, xmm0\npandn xmm0, xmm1\npor xmm0, xmm2\nmovd eax, xmm0\ntest r14b, 3\njz short loc_1488\nmovsxd rcx, edx\nlea r15, [rdi+rcx*4]\nmov ecx, [r15]\ncmp eax, ecx\ncmovl eax, ecx\nlea ecx, [rdx+1]\ncmp r14d, ecx\njle short loc_1488\nloc_146E:\nmov ecx, [r15+4]\ncmp eax, ecx\ncmovl eax, ecx\nadd edx, 2\ncmp r14d, edx\njle short loc_1488\nmov edx, [r15+8]\ncmp eax, edx\ncmovl eax, edx\nloc_1488:\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_14DD\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_14A6:\nor [rsp+rdx+1050h+var_1058], 0\njmp loc_1344\nloc_14B1:\nxor eax, eax\njmp short loc_1488\nloc_14B5:\nmov rax, [rbp+var_48]\nxor edx, edx\nmov eax, ds:dword_0[rax*4]\ntest eax, eax\ncmovs eax, edx\njmp short loc_146E\nloc_14C9:\nmov rax, [rbp+var_48]\nxor edx, edx\nmov eax, ds:dword_0[rax*4]\ntest eax, eax\ncmovs eax, edx\njmp short loc_1488\nloc_14DD:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12D0(char *src, int a2)\n{\n __int64 v3; // rdx\n __int64 *v4; // rcx\n __int16 v5; // dx\n signed __int64 v6; // rdx\n void *v7; // rsp\n int *v8; // r15\n unsigned int v9; // ebx\n size_t v10; // r12\n __int64 v11; // rdx\n int v12; // ecx\n __int64 v13; // rax\n int v14; // esi\n const __m128i *v15; // rax\n __m128i v16; // xmm2\n __m128i v17; // xmm0\n __m128i v18; // xmm1\n __m128i v19; // xmm0\n unsigned int v20; // edx\n __m128i v21; // xmm1\n __m128i v22; // xmm1\n __m128i v23; // xmm2\n __m128i v24; // xmm0\n __int64 result; // rax\n int v26; // ecx\n int v27; // edx\n _BYTE v29[3]; // [rsp+8h] [rbp-1050h] BYREF\n char v30; // [rsp+Bh] [rbp-104Dh] BYREF\n __int64 v31; // [rsp+1008h] [rbp-50h] BYREF\n unsigned __int64 v32; // [rsp+1010h] [rbp-48h]\n unsigned __int64 v33; // [rsp+1020h] [rbp-38h]\n\n v33 = __readfsqword(0x28u);\n v3 = 4LL * a2 + 15;\n v4 = (__int64 *)((char *)&v31 - (v3 & 0xFFFFFFFFFFFFF000LL));\n v5 = v3 & 0xFFF0;\n if ( &v31 != v4 )\n {\n while ( v29 != (_BYTE *)v4 )\n ;\n }\n v6 = v5 & 0xFFF;\n v7 = alloca(v6);\n if ( v6 )\n *(_QWORD *)&v29[v6 - 8] = *(_QWORD *)&v29[v6 - 8];\n v8 = (int *)v29;\n v32 = (unsigned __int64)&v30 >> 2;\n if ( a2 <= 0 )\n return 0LL;\n v9 = a2 - 1;\n v10 = 4LL * (unsigned int)a2;\n memcpy(v29, src, v10);\n if ( a2 == 1 )\n {\n result = *(unsigned int *)(4 * v32);\n if ( (int)result < 0 )\n return 0LL;\n }\n else\n {\n v11 = 4LL;\n do\n {\n v12 = *(_DWORD *)&src[v11];\n v13 = 0LL;\n do\n {\n if ( v12 > *(_DWORD *)&src[v13] )\n {\n v14 = v12 + *(_DWORD *)&v29[v13];\n if ( *(_DWORD *)&v29[v11] < v14 )\n *(_DWORD *)&v29[v11] = v14;\n }\n v13 += 4LL;\n }\n while ( v13 != v11 );\n v11 = v13 + 4;\n }\n while ( v13 + 4 != v10 );\n if ( v9 <= 2 )\n {\n v20 = 0;\n result = *(unsigned int *)(4 * v32);\n if ( (int)result < 0 )\n result = 0LL;\n goto LABEL_21;\n }\n v15 = (const __m128i *)v29;\n v16 = 0LL;\n do\n {\n v17 = _mm_loadu_si128(v15++);\n v18 = _mm_cmpgt_epi32(v17, v16);\n v16 = _mm_or_si128(_mm_andnot_si128(v18, v16), _mm_and_si128(v17, v18));\n }\n while ( &v29[16 * ((unsigned int)a2 >> 2)] != (_BYTE *)v15 );\n v19 = _mm_srli_si128(v16, 8);\n v20 = a2 & 0xFFFFFFFC;\n v21 = _mm_cmpgt_epi32(v19, v16);\n v22 = _mm_or_si128(_mm_andnot_si128(v21, v16), _mm_and_si128(v19, v21));\n v23 = _mm_srli_si128(v22, 4);\n v24 = _mm_cmpgt_epi32(v23, v22);\n result = (unsigned int)_mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v24, v22), _mm_and_si128(v23, v24)));\n if ( (a2 & 3) != 0 )\n {\n v8 = (int *)&v29[4 * v20];\n if ( (int)result < *v8 )\n result = (unsigned int)*v8;\n if ( a2 > (int)(v20 + 1) )\n {\nLABEL_21:\n v26 = v8[1];\n if ( (int)result < v26 )\n result = (unsigned int)v26;\n if ( a2 > (int)(v20 + 2) )\n {\n v27 = v8[2];\n if ( (int)result < v27 )\n return (unsigned int)v27;\n }\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12D0(char *src, int a2) {\n long long v3;\n long long *v4;\n short v5;\n signed long long v6;\n void *v7;\n int *v8;\n unsigned int v9;\n unsigned int v10;\n long long v11;\n int v12;\n long long v13;\n int v14;\n const __m128i *v15;\n __m128i v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n unsigned int v20;\n __m128i v21;\n __m128i v22;\n __m128i v23;\n __m128i v24;\n long long result;\n int v26;\n int v27;\n uint8_t v29[3];\n char v30;\n long long v31;\n unsigned long long v32;\n unsigned long long v33;\n v33 = __readfsqword(40u);\n v3 = 4LL * a2 + 15;\n v4 = (long long *)((char *)&v31 - (v3 & 18446744073709547520LL));\n v5 = v3 & 65520;\n if (&v31 != v4) {\n while (v29 != (uint8_t *)v4)\n ;\n }\n v6 = v5 & 4095;\n v7 = alloca(v6);\n if (v6) *(uint64_t *)&v29[v6 - 8] = *(uint64_t *)&v29[v6 - 8];\n v8 = (int *)v29;\n v32 = (unsigned long long)&v30 >> 2;\n if (a2 <= 0) return 0LL;\n v9 = a2 - 1;\n v10 = 4LL * (unsigned int)a2;\n memcpy(v29, src, v10);\n if (a2 == 1) {\n result = *(unsigned int *)(4 * v32);\n if ((int)result < 0) return 0LL;\n } else {\n v11 = 4LL;\n do {\n v12 = *(uint32_t *)&src[v11];\n v13 = 0LL;\n do {\n if (v12 > *(uint32_t *)&src[v13]) {\n v14 = v12 + *(uint32_t *)&v29[v13];\n if (*(uint32_t *)&v29[v11] < v14) *(uint32_t *)&v29[v11] = v14;\n }\n v13 += 4LL;\n } while (v13 != v11);\n v11 = v13 + 4;\n } while (v13 + 4 != v10);\n if (v9 <= 2) {\n v20 = 0;\n result = *(unsigned int *)(4 * v32);\n if ((int)result < 0) result = 0LL;\n goto LABEL_21;\n }\n v15 = (const __m128i *)v29;\n v16 = 0LL;\n do {\n v17 = _mm_loadu_si128(v15++);\n v18 = _mm_cmpgt_epi32(v17, v16);\n v16 = _mm_or_si128(_mm_andnot_si128(v18, v16), _mm_and_si128(v17, v18));\n } while (&v29[16 * ((unsigned int)a2 >> 2)] != (uint8_t *)v15);\n v19 = _mm_srli_si128(v16, 8);\n v20 = a2 & 4294967292;\n v21 = _mm_cmpgt_epi32(v19, v16);\n v22 = _mm_or_si128(_mm_andnot_si128(v21, v16), _mm_and_si128(v19, v21));\n v23 = _mm_srli_si128(v22, 4);\n v24 = _mm_cmpgt_epi32(v23, v22);\n result = (unsigned int)_mm_cvtsi128_si32(\n _mm_or_si128(_mm_andnot_si128(v24, v22), _mm_and_si128(v23, v24)));\n if ((a2 & 3) != 0) {\n v8 = (int *)&v29[4 * v20];\n if ((int)result < *v8) result = (unsigned int)*v8;\n if (a2 > (int)(v20 + 1)) {\n LABEL_21:\n v26 = v8[1];\n if ((int)result < v26) result = (unsigned int)v26;\n if (a2 > (int)(v20 + 2)) {\n v27 = v8[2];\n if ((int)result < v27) return (unsigned int)v27;\n }\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(char *src, int a2) {\n long long v3;\n long long *v4;\n short v5;\n signed long long v6;\n void *v7;\n int *v8;\n unsigned int v9;\n unsigned int v10;\n long long v11;\n int v12;\n long long v13;\n int v14;\n const __m128i *v15;\n __m128i v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n unsigned int v20;\n __m128i v21;\n __m128i v22;\n __m128i v23;\n __m128i v24;\n long long result;\n int v26;\n int v27;\n uint8_t v29[3];\n char v30;\n long long v31;\n unsigned long long v32;\n unsigned long long v33;\n v33 = __readfsqword(40u);\n v3 = 4LL * a2 + 15;\n v4 = (long long *)((char *)&v31 - (v3 & 18446744073709547520LL));\n v5 = v3 & 65520;\n if (&v31 != v4) {\n while (v29 != (uint8_t *)v4)\n ;\n }\n v6 = v5 & 4095;\n v7 = alloca(v6);\n if (v6) *(uint64_t *)&v29[v6 - 8] = *(uint64_t *)&v29[v6 - 8];\n v8 = (int *)v29;\n v32 = (unsigned long long)&v30 >> 2;\n if (a2 <= 0) return 0LL;\n v9 = a2 - 1;\n v10 = 4LL * (unsigned int)a2;\n memcpy(v29, src, v10);\n if (a2 == 1) {\n result = *(unsigned int *)(4 * v32);\n if ((int)result < 0) return 0LL;\n } else {\n v11 = 4LL;\n do {\n v12 = *(uint32_t *)&src[v11];\n v13 = 0LL;\n do {\n if (v12 > *(uint32_t *)&src[v13]) {\n v14 = v12 + *(uint32_t *)&v29[v13];\n if (*(uint32_t *)&v29[v11] < v14) *(uint32_t *)&v29[v11] = v14;\n }\n v13 += 4LL;\n } while (v13 != v11);\n v11 = v13 + 4;\n } while (v13 + 4 != v10);\n if (v9 <= 2) {\n v20 = 0;\n result = *(unsigned int *)(4 * v32);\n if ((int)result < 0) result = 0LL;\n goto LABEL_21;\n }\n v15 = (const __m128i *)v29;\n v16 = 0LL;\n do {\n v17 = _mm_loadu_si128(v15++);\n v18 = _mm_cmpgt_epi32(v17, v16);\n v16 = _mm_or_si128(_mm_andnot_si128(v18, v16), _mm_and_si128(v17, v18));\n } while (&v29[16 * ((unsigned int)a2 >> 2)] != (uint8_t *)v15);\n v19 = _mm_srli_si128(v16, 8);\n v20 = a2 & 4294967292;\n v21 = _mm_cmpgt_epi32(v19, v16);\n v22 = _mm_or_si128(_mm_andnot_si128(v21, v16), _mm_and_si128(v19, v21));\n v23 = _mm_srli_si128(v22, 4);\n v24 = _mm_cmpgt_epi32(v23, v22);\n result = (unsigned int)_mm_cvtsi128_si32(\n _mm_or_si128(_mm_andnot_si128(v24, v22), _mm_and_si128(v23, v24)));\n if ((a2 & 3) != 0) {\n v8 = (int *)&v29[4 * v20];\n if ((int)result < *v8) result = (unsigned int)*v8;\n if (a2 > (int)(v20 + 1)) {\n LABEL_21:\n v26 = v8[1];\n if ((int)result < v26) result = (unsigned int)v26;\n if (a2 > (int)(v20 + 2)) {\n v27 = v8[2];\n if ((int)result < v27) return (unsigned int)v27;\n }\n }\n }\n }\n return result;\n}" + }, + { + "index": 525, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int line1[], int line2[]) {\n return line1[0] * line2[1] == line1[1] * line2[0];\n}", + "test": "int main() {\n\n int line1[] = {2, 3, 4};\n\n int line2[] = {2, 3, 8};\n\n assert(func0(line1, line2) == true);\n\n\n\n int line3[] = {2, 3, 4};\n\n int line4[] = {4, -3, 8};\n\n assert(func0(line3, line4) == false);\n\n\n\n int line5[] = {3, 3};\n\n int line6[] = {5, 5};\n\n assert(func0(line5, line6) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x8(%rbp)\nmov %rsi,-0x10(%rbp)\nmov -0x8(%rbp),%rax\nmov (%rax),%edx\nmov -0x10(%rbp),%rax\nadd $0x4,%rax\nmov (%rax),%eax\nimul %eax,%edx\nmov -0x8(%rbp),%rax\nadd $0x4,%rax\nmov (%rax),%ecx\nmov -0x10(%rbp),%rax\nmov (%rax),%eax\nimul %ecx,%eax\ncmp %eax,%edx\nsete %al\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_8], rdi\nmov [rbp+var_10], rsi\nmov rax, [rbp+var_8]\nmov edx, [rax]\nmov rax, [rbp+var_10]\nadd rax, 4\nmov eax, [rax]\nmov ecx, edx\nimul ecx, eax\nmov rax, [rbp+var_8]\nadd rax, 4\nmov edx, [rax]\nmov rax, [rbp+var_10]\nmov eax, [rax]\nimul eax, edx\ncmp ecx, eax\nsetz al\npop rbp\nretn", + "ida_pseudo": "bool __fastcall func0(_DWORD *a1, _DWORD *a2)\n{\n return a2[1] * *a1 == a1[1] * *a2;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_8], rdi\nmov [rbp+var_10], rsi\nmov rax, [rbp+var_8]\nmov edx, [rax]\nmov rax, [rbp+var_10]\nadd rax, 4\nmov eax, [rax]\nmov ecx, edx\nimul ecx, eax\nmov rax, [rbp+var_8]\nadd rax, 4\nmov edx, [rax]\nmov rax, [rbp+var_10]\nmov eax, [rax]\nimul eax, edx\ncmp ecx, eax\nsetz al\npop rbp\nretn", + "ida_strip_pseudo": "bool __fastcall sub_1169(_DWORD *a1, _DWORD *a2)\n{\n return a2[1] * *a1 == a1[1] * *a2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_1169(uint32_t *a1, uint32_t *a2) { return a2[1] * *a1 == a1[1] * *a2; }", + "ida_pseudo_norm": "bool func0(uint32_t *a1, uint32_t *a2) { return a2[1] * *a1 == a1[1] * *a2; }" + }, + { + "index": 526, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* str1) {\n size_t len = strlen(str1);\n char* result = malloc(len + 1);\n if (!result) return NULL;\n if (len > 0) {\n result[0] = toupper(str1[0]);\n for (size_t i = 1; i < len; i++) {\n result[i] = tolower(str1[i]);\n }\n result[len - 1] = toupper(result[len - 1]);\n result[len] = '\\0';\n }\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"python\"), \"PythoN\") == 0);\n\n assert(strcmp(func0(\"bigdata\"), \"BigdatA\") == 0);\n\n assert(strcmp(func0(\"Hadoop\"), \"HadooP\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x28(%rbp)\nmov -0x28(%rbp),%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x10(%rbp)\nmov -0x10(%rbp),%rax\nadd $0x1,%rax\nmov %rax,%rdi\ncallq 10f0 \nmov %rax,-0x8(%rbp)\ncmpq $0x0,-0x8(%rbp)\njne 122e \nmov $0x0,%eax\njmpq 12d7 \ncmpq $0x0,-0x10(%rbp)\nje 12d3 \nmov -0x28(%rbp),%rax\nmovzbl (%rax),%eax\nmovsbl %al,%eax\nmov %eax,%edi\ncallq 10a0 \nmov %eax,%edx\nmov -0x8(%rbp),%rax\nmov %dl,(%rax)\nmovq $0x1,-0x18(%rbp)\njmp 128a \nmov -0x28(%rbp),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmovsbl %al,%eax\nmov %eax,%edi\ncallq 10e0 \nmov %eax,%ecx\nmov -0x8(%rbp),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov %ecx,%edx\nmov %dl,(%rax)\naddq $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%rax\ncmp -0x10(%rbp),%rax\njb 125c \nmov -0x10(%rbp),%rax\nlea -0x1(%rax),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmovsbl %al,%eax\nmov %eax,%edi\ncallq 10a0 \nmov %eax,%ecx\nmov -0x10(%rbp),%rax\nlea -0x1(%rax),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov %ecx,%edx\nmov %dl,(%rax)\nmov -0x8(%rbp),%rdx\nmov -0x10(%rbp),%rax\nadd %rdx,%rax\nmovb $0x0,(%rax)\nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_10], rax\nmov rax, [rbp+var_10]\nadd rax, 1\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\ncmp [rbp+var_8], 0\njnz short loc_122E\nmov eax, 0\njmp locret_12D7\nloc_122E:\ncmp [rbp+var_10], 0\njz loc_12D3\nmov rax, [rbp+s]\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nmov edi, eax; c\ncall _toupper\nmov edx, eax\nmov rax, [rbp+var_8]\nmov [rax], dl\nmov [rbp+var_18], 1\njmp short loc_128A\nloc_125C:\nmov rdx, [rbp+s]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nmov edi, eax; c\ncall _tolower\nmov ecx, eax\nmov rdx, [rbp+var_8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, ecx\nmov [rax], dl\nadd [rbp+var_18], 1\nloc_128A:\nmov rax, [rbp+var_18]\ncmp rax, [rbp+var_10]\njb short loc_125C\nmov rax, [rbp+var_10]\nlea rdx, [rax-1]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nmov edi, eax; c\ncall _toupper\nmov ecx, eax\nmov rax, [rbp+var_10]\nlea rdx, [rax-1]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, ecx\nmov [rax], dl\nmov rdx, [rbp+var_8]\nmov rax, [rbp+var_10]\nadd rax, rdx\nmov byte ptr [rax], 0\nloc_12D3:\nmov rax, [rbp+var_8]\nlocret_12D7:\nleave\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1)\n{\n unsigned __int64 i; // [rsp+18h] [rbp-18h]\n size_t v3; // [rsp+20h] [rbp-10h]\n _BYTE *v4; // [rsp+28h] [rbp-8h]\n\n v3 = strlen(a1);\n v4 = malloc(v3 + 1);\n if ( !v4 )\n return 0LL;\n if ( v3 )\n {\n *v4 = toupper(*a1);\n for ( i = 1LL; i < v3; ++i )\n v4[i] = tolower(a1[i]);\n v4[v3 - 1] = toupper((char)v4[v3 - 1]);\n v4[v3] = 0;\n }\n return v4;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_10], rax\nmov rax, [rbp+var_10]\nadd rax, 1\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\ncmp [rbp+var_8], 0\njnz short loc_122E\nmov eax, 0\njmp locret_12D7\nloc_122E:\ncmp [rbp+var_10], 0\njz loc_12D3\nmov rax, [rbp+s]\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nmov edi, eax; c\ncall _toupper\nmov edx, eax\nmov rax, [rbp+var_8]\nmov [rax], dl\nmov [rbp+var_18], 1\njmp short loc_128A\nloc_125C:\nmov rdx, [rbp+s]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nmov edi, eax; c\ncall _tolower\nmov ecx, eax\nmov rdx, [rbp+var_8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, ecx\nmov [rax], dl\nadd [rbp+var_18], 1\nloc_128A:\nmov rax, [rbp+var_18]\ncmp rax, [rbp+var_10]\njb short loc_125C\nmov rax, [rbp+var_10]\nlea rdx, [rax-1]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nmov edi, eax; c\ncall _toupper\nmov ecx, eax\nmov rax, [rbp+var_10]\nlea rdx, [rax-1]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, ecx\nmov [rax], dl\nmov rdx, [rbp+var_8]\nmov rax, [rbp+var_10]\nadd rax, rdx\nmov byte ptr [rax], 0\nloc_12D3:\nmov rax, [rbp+var_8]\nlocret_12D7:\nleave\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_11E9(const char *a1)\n{\n unsigned __int64 i; // [rsp+18h] [rbp-18h]\n size_t v3; // [rsp+20h] [rbp-10h]\n _BYTE *v4; // [rsp+28h] [rbp-8h]\n\n v3 = strlen(a1);\n v4 = malloc(v3 + 1);\n if ( !v4 )\n return 0LL;\n if ( v3 )\n {\n *v4 = toupper(*a1);\n for ( i = 1LL; i < v3; ++i )\n v4[i] = tolower(a1[i]);\n v4[v3 - 1] = toupper((char)v4[v3 - 1]);\n v4[v3] = 0;\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_11E9(const char *a1) {\n unsigned long long i;\n unsigned int v3;\n uint8_t *v4;\n v3 = strlen(a1);\n v4 = malloc(v3 + 1);\n if (!v4) return 0LL;\n if (v3) {\n *v4 = toupper(*a1);\n for (i = 1LL; i < v3; ++i) v4[i] = tolower(a1[i]);\n v4[v3 - 1] = toupper((char)v4[v3 - 1]);\n v4[v3] = 0;\n }\n return v4;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1) {\n unsigned long long i;\n unsigned int v3;\n uint8_t *v4;\n v3 = strlen(a1);\n v4 = malloc(v3 + 1);\n if (!v4) return 0LL;\n if (v3) {\n *v4 = toupper(*a1);\n for (i = 1LL; i < v3; ++i) v4[i] = tolower(a1[i]);\n v4[v3 - 1] = toupper((char)v4[v3 - 1]);\n v4[v3] = 0;\n }\n return v4;\n}" + }, + { + "index": 526, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* str1) {\n size_t len = strlen(str1);\n char* result = malloc(len + 1);\n if (!result) return NULL;\n if (len > 0) {\n result[0] = toupper(str1[0]);\n for (size_t i = 1; i < len; i++) {\n result[i] = tolower(str1[i]);\n }\n result[len - 1] = toupper(result[len - 1]);\n result[len] = '\\0';\n }\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"python\"), \"PythoN\") == 0);\n\n assert(strcmp(func0(\"bigdata\"), \"BigdatA\") == 0);\n\n assert(strcmp(func0(\"Hadoop\"), \"HadooP\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbp\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nmov %rcx,%r12\nlea -0x1(%rcx),%r13\nmov %rcx,%rdi\ncallq 10a0 \nmov %rax,%rbx\ntest %rax,%rax\nje 1235 \ntest %r13,%r13\nje 1235 \ncallq 1080 <__ctype_toupper_loc@plt>\nmov (%rax),%r14\nmovsbq 0x0(%rbp),%rax\nmov (%r14,%rax,4),%eax\nmov %al,(%rbx)\ncmp $0x1,%r13\njbe 1220 \ncallq 10b0 <__ctype_tolower_loc@plt>\nmov (%rax),%rcx\nmov $0x1,%edx\nmovsbq 0x0(%rbp,%rdx,1),%rax\nmov (%rcx,%rax,4),%eax\nmov %al,(%rbx,%rdx,1)\nadd $0x1,%rdx\ncmp %r13,%rdx\njne 120b \nlea -0x1(%rbx,%r13,1),%rax\nmovsbq (%rax),%rdx\nmov (%r14,%rdx,4),%edx\nmov %dl,(%rax)\nmovb $0x0,-0x1(%rbx,%r12,1)\nmov %rbx,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12, rdi\ncall _strlen\nmov rbx, rax\nlea rdi, [rax+1]; size\ncall _malloc\nmov rbp, rax\ntest rbx, rbx\njz short loc_126A\ntest rax, rax\njz short loc_126A\ncall ___ctype_toupper_loc\nmov r13, [rax]\nmovsx rax, byte ptr [r12]\nmov eax, [r13+rax*4+0]\nmov [rbp+0], al\ncmp rbx, 1\njbe short loc_1255\ncall ___ctype_tolower_loc\nmov rcx, [rax]\nmov eax, 1\nloc_1240:\nmovsx rdx, byte ptr [r12+rax]\nmov edx, [rcx+rdx*4]\nmov [rbp+rax+0], dl\nadd rax, 1\ncmp rax, rbx\njnz short loc_1240\nloc_1255:\nlea rax, [rbp+rbx-1]\nmovsx rdx, byte ptr [rax]\nmov edx, [r13+rdx*4+0]\nmov [rax], dl\nmov byte ptr [rbp+rbx+0], 0\nloc_126A:\nmov rax, rbp\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1)\n{\n size_t v1; // rbx\n _BYTE *v2; // rax\n _BYTE *v3; // rbp\n const __int32_t **v4; // rax\n const __int32_t *v5; // r13\n const __int32_t *v6; // rcx\n __int64 i; // rax\n\n v1 = strlen(a1);\n v2 = malloc(v1 + 1);\n v3 = v2;\n if ( v1 && v2 )\n {\n v4 = __ctype_toupper_loc();\n v5 = *v4;\n *v3 = (*v4)[*a1];\n if ( v1 > 1 )\n {\n v6 = *__ctype_tolower_loc();\n for ( i = 1LL; i != v1; ++i )\n v3[i] = v6[a1[i]];\n }\n *(_WORD *)&v3[v1 - 1] = (unsigned __int8)v5[(char)v3[v1 - 1]];\n }\n return v3;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12, rdi\ncall _strlen\nmov rbx, rax\nlea rdi, [rax+1]; size\ncall _malloc\nmov rbp, rax\ntest rbx, rbx\njz short loc_126A\ntest rax, rax\njz short loc_126A\ncall ___ctype_toupper_loc\nmov r13, [rax]\nmovsx rax, byte ptr [r12]\nmov eax, [r13+rax*4+0]\nmov [rbp+0], al\ncmp rbx, 1\njbe short loc_1255\ncall ___ctype_tolower_loc\nmov rcx, [rax]\nmov eax, 1\nloc_1240:\nmovsx rdx, byte ptr [r12+rax]\nmov edx, [rcx+rdx*4]\nmov [rbp+rax+0], dl\nadd rax, 1\ncmp rax, rbx\njnz short loc_1240\nloc_1255:\nlea rax, [rbp+rbx-1]\nmovsx rdx, byte ptr [rax]\nmov edx, [r13+rdx*4+0]\nmov [rax], dl\nmov byte ptr [rbp+rbx+0], 0\nloc_126A:\nmov rax, rbp\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_11E9(const char *a1)\n{\n size_t v1; // rbx\n _BYTE *v2; // rax\n _BYTE *v3; // rbp\n const __int32_t **v4; // rax\n const __int32_t *v5; // r13\n const __int32_t *v6; // rcx\n __int64 i; // rax\n\n v1 = strlen(a1);\n v2 = malloc(v1 + 1);\n v3 = v2;\n if ( v1 && v2 )\n {\n v4 = __ctype_toupper_loc();\n v5 = *v4;\n *v3 = (*v4)[*a1];\n if ( v1 > 1 )\n {\n v6 = *__ctype_tolower_loc();\n for ( i = 1LL; i != v1; ++i )\n v3[i] = v6[a1[i]];\n }\n *(_WORD *)&v3[v1 - 1] = (unsigned __int8)v5[(char)v3[v1 - 1]];\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_11E9(const char *a1) {\n unsigned int v1;\n uint8_t *v2;\n uint8_t *v3;\n const __int32_t **v4;\n const __int32_t *v5;\n const __int32_t *v6;\n long long i;\n v1 = strlen(a1);\n v2 = malloc(v1 + 1);\n v3 = v2;\n if (v1 && v2) {\n v4 = __ctype_toupper_loc();\n v5 = *v4;\n *v3 = (*v4)[*a1];\n if (v1 > 1) {\n v6 = *__ctype_tolower_loc();\n for (i = 1LL; i != v1; ++i) v3[i] = v6[a1[i]];\n }\n *(unsigned short *)&v3[v1 - 1] = (unsigned char)v5[(char)v3[v1 - 1]];\n }\n return v3;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1) {\n unsigned int v1;\n uint8_t *v2;\n uint8_t *v3;\n const __int32_t **v4;\n const __int32_t *v5;\n const __int32_t *v6;\n long long i;\n v1 = strlen(a1);\n v2 = malloc(v1 + 1);\n v3 = v2;\n if (v1 && v2) {\n v4 = __ctype_toupper_loc();\n v5 = *v4;\n *v3 = (*v4)[*a1];\n if (v1 > 1) {\n v6 = *__ctype_tolower_loc();\n for (i = 1LL; i != v1; ++i) v3[i] = v6[a1[i]];\n }\n *(unsigned short *)&v3[v1 - 1] = (unsigned char)v5[(char)v3[v1 - 1]];\n }\n return v3;\n}" + }, + { + "index": 526, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* str1) {\n size_t len = strlen(str1);\n char* result = malloc(len + 1);\n if (!result) return NULL;\n if (len > 0) {\n result[0] = toupper(str1[0]);\n for (size_t i = 1; i < len; i++) {\n result[i] = tolower(str1[i]);\n }\n result[len - 1] = toupper(result[len - 1]);\n result[len] = '\\0';\n }\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"python\"), \"PythoN\") == 0);\n\n assert(strcmp(func0(\"bigdata\"), \"BigdatA\") == 0);\n\n assert(strcmp(func0(\"Hadoop\"), \"HadooP\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\nmov %rdi,%rbp\npush %rbx\nsub $0x8,%rsp\ncallq 10a0 \nlea 0x1(%rax),%rdi\nmov %rax,%rbx\ncallq 10c0 \nmov %rax,%r12\ntest %rax,%rax\nje 133b \ntest %rbx,%rbx\nje 133b \ncallq 1090 <__ctype_toupper_loc@plt>\nmov (%rax),%r13\nmovsbq 0x0(%rbp),%rax\nmov 0x0(%r13,%rax,4),%eax\nmov %al,(%r12)\ncmp $0x1,%rbx\nje 1326 \ncallq 10d0 <__ctype_tolower_loc@plt>\nmov (%rax),%rcx\nmov $0x1,%eax\nnopl 0x0(%rax,%rax,1)\nmovsbq 0x0(%rbp,%rax,1),%rdx\nmov (%rcx,%rdx,4),%edx\nmov %dl,(%r12,%rax,1)\nadd $0x1,%rax\ncmp %rbx,%rax\njne 1310 \nlea -0x1(%r12,%rbx,1),%rax\nmovsbq (%rax),%rdx\nmov 0x0(%r13,%rdx,4),%edx\nmov %dl,(%rax)\nmovb $0x0,(%r12,%rbx,1)\nadd $0x8,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 8\ncall _strlen\nlea rdi, [rax+1]; size\nmov rbx, rax\ncall _malloc\nmov rbp, rax\ntest rbx, rbx\njz short loc_134A\ntest rax, rax\njz short loc_134A\ncall ___ctype_toupper_loc\nmov r13, [rax]\nmovsx rax, byte ptr [r12]\nmov eax, [r13+rax*4+0]\nmov [rbp+0], al\ncmp rbx, 1\njz short loc_1335\ncall ___ctype_tolower_loc\nmov rcx, [rax]\nmov eax, 1\nnop word ptr [rax+rax+00000000h]\nloc_1320:\nmovsx rdx, byte ptr [r12+rax]\nmov edx, [rcx+rdx*4]\nmov [rbp+rax+0], dl\nadd rax, 1\ncmp rax, rbx\njnz short loc_1320\nloc_1335:\nlea rax, [rbp+rbx-1]\nmovsx rdx, byte ptr [rax]\nmov edx, [r13+rdx*4+0]\nmov [rax], dl\nmov byte ptr [rbp+rbx+0], 0\nloc_134A:\nadd rsp, 8\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1)\n{\n size_t v1; // rbx\n _BYTE *v2; // rax\n _BYTE *v3; // rbp\n const __int32_t **v4; // rax\n const __int32_t *v5; // r13\n const __int32_t *v6; // rcx\n __int64 i; // rax\n\n v1 = strlen(a1);\n v2 = malloc(v1 + 1);\n v3 = v2;\n if ( v1 && v2 )\n {\n v4 = __ctype_toupper_loc();\n v5 = *v4;\n *v3 = (*v4)[*a1];\n if ( v1 != 1 )\n {\n v6 = *__ctype_tolower_loc();\n for ( i = 1LL; i != v1; ++i )\n v3[i] = v6[a1[i]];\n }\n *(_WORD *)&v3[v1 - 1] = (unsigned __int8)v5[(char)v3[v1 - 1]];\n }\n return v3;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 8\ncall _strlen\nlea rdi, [rax+1]; size\nmov rbx, rax\ncall _malloc\nmov rbp, rax\ntest rbx, rbx\njz short loc_134A\ntest rax, rax\njz short loc_134A\ncall ___ctype_toupper_loc\nmov r13, [rax]\nmovsx rax, byte ptr [r12]\nmov eax, [r13+rax*4+0]\nmov [rbp+0], al\ncmp rbx, 1\njz short loc_1335\ncall ___ctype_tolower_loc\nmov rcx, [rax]\nmov eax, 1\nnop word ptr [rax+rax+00000000h]\nloc_1320:\nmovsx rdx, byte ptr [r12+rax]\nmov edx, [rcx+rdx*4]\nmov [rbp+rax+0], dl\nadd rax, 1\ncmp rax, rbx\njnz short loc_1320\nloc_1335:\nlea rax, [rbp+rbx-1]\nmovsx rdx, byte ptr [rax]\nmov edx, [r13+rdx*4+0]\nmov [rax], dl\nmov byte ptr [rbp+rbx+0], 0\nloc_134A:\nadd rsp, 8\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_12C0(const char *a1)\n{\n size_t v1; // rbx\n _BYTE *v2; // rax\n _BYTE *v3; // rbp\n const __int32_t **v4; // rax\n const __int32_t *v5; // r13\n const __int32_t *v6; // rcx\n __int64 i; // rax\n\n v1 = strlen(a1);\n v2 = malloc(v1 + 1);\n v3 = v2;\n if ( v1 && v2 )\n {\n v4 = __ctype_toupper_loc();\n v5 = *v4;\n *v3 = (*v4)[*a1];\n if ( v1 != 1 )\n {\n v6 = *__ctype_tolower_loc();\n for ( i = 1LL; i != v1; ++i )\n v3[i] = v6[a1[i]];\n }\n *(_WORD *)&v3[v1 - 1] = (unsigned __int8)v5[(char)v3[v1 - 1]];\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_12C0(const char *a1) {\n unsigned int v1;\n uint8_t *v2;\n uint8_t *v3;\n const __int32_t **v4;\n const __int32_t *v5;\n const __int32_t *v6;\n long long i;\n v1 = strlen(a1);\n v2 = malloc(v1 + 1);\n v3 = v2;\n if (v1 && v2) {\n v4 = __ctype_toupper_loc();\n v5 = *v4;\n *v3 = (*v4)[*a1];\n if (v1 != 1) {\n v6 = *__ctype_tolower_loc();\n for (i = 1LL; i != v1; ++i) v3[i] = v6[a1[i]];\n }\n *(unsigned short *)&v3[v1 - 1] = (unsigned char)v5[(char)v3[v1 - 1]];\n }\n return v3;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1) {\n unsigned int v1;\n uint8_t *v2;\n uint8_t *v3;\n const __int32_t **v4;\n const __int32_t *v5;\n const __int32_t *v6;\n long long i;\n v1 = strlen(a1);\n v2 = malloc(v1 + 1);\n v3 = v2;\n if (v1 && v2) {\n v4 = __ctype_toupper_loc();\n v5 = *v4;\n *v3 = (*v4)[*a1];\n if (v1 != 1) {\n v6 = *__ctype_tolower_loc();\n for (i = 1LL; i != v1; ++i) v3[i] = v6[a1[i]];\n }\n *(unsigned short *)&v3[v1 - 1] = (unsigned char)v5[(char)v3[v1 - 1]];\n }\n return v3;\n}" + }, + { + "index": 526, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* str1) {\n size_t len = strlen(str1);\n char* result = malloc(len + 1);\n if (!result) return NULL;\n if (len > 0) {\n result[0] = toupper(str1[0]);\n for (size_t i = 1; i < len; i++) {\n result[i] = tolower(str1[i]);\n }\n result[len - 1] = toupper(result[len - 1]);\n result[len] = '\\0';\n }\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"python\"), \"PythoN\") == 0);\n\n assert(strcmp(func0(\"bigdata\"), \"BigdatA\") == 0);\n\n assert(strcmp(func0(\"Hadoop\"), \"HadooP\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\nmov %rdi,%rbp\npush %rbx\nsub $0x8,%rsp\ncallq 10a0 \nlea 0x1(%rax),%rdi\nmov %rax,%rbx\ncallq 10c0 \nmov %rax,%r12\ntest %rax,%rax\nje 133b \ntest %rbx,%rbx\nje 133b \ncallq 1090 <__ctype_toupper_loc@plt>\nmov (%rax),%r13\nmovsbq 0x0(%rbp),%rax\nmov 0x0(%r13,%rax,4),%eax\nmov %al,(%r12)\ncmp $0x1,%rbx\nje 1326 \ncallq 10d0 <__ctype_tolower_loc@plt>\nmov (%rax),%rcx\nmov $0x1,%eax\nnopl 0x0(%rax,%rax,1)\nmovsbq 0x0(%rbp,%rax,1),%rdx\nmov (%rcx,%rdx,4),%edx\nmov %dl,(%r12,%rax,1)\nadd $0x1,%rax\ncmp %rbx,%rax\njne 1310 \nlea -0x1(%r12,%rbx,1),%rax\nmovsbq (%rax),%rdx\nmov 0x0(%r13,%rdx,4),%edx\nmov %dl,(%rax)\nmovb $0x0,(%r12,%rbx,1)\nadd $0x8,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 8\ncall _strlen\nlea rdi, [rax+1]; size\nmov rbx, rax\ncall _malloc\nmov rbp, rax\ntest rbx, rbx\njz short loc_134A\ntest rax, rax\njz short loc_134A\ncall ___ctype_toupper_loc\nmov r13, [rax]\nmovsx rax, byte ptr [r12]\nmov eax, [r13+rax*4+0]\nmov [rbp+0], al\ncmp rbx, 1\njz short loc_1335\ncall ___ctype_tolower_loc\nmov rcx, [rax]\nmov eax, 1\nnop word ptr [rax+rax+00000000h]\nloc_1320:\nmovsx rdx, byte ptr [r12+rax]\nmov edx, [rcx+rdx*4]\nmov [rbp+rax+0], dl\nadd rax, 1\ncmp rax, rbx\njnz short loc_1320\nloc_1335:\nlea rax, [rbp+rbx-1]\nmovsx rdx, byte ptr [rax]\nmov edx, [r13+rdx*4+0]\nmov [rax], dl\nmov byte ptr [rbp+rbx+0], 0\nloc_134A:\nadd rsp, 8\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1)\n{\n size_t v1; // rbx\n _BYTE *v2; // rax\n _BYTE *v3; // rbp\n const __int32_t **v4; // rax\n const __int32_t *v5; // r13\n const __int32_t *v6; // rcx\n __int64 i; // rax\n\n v1 = strlen(a1);\n v2 = malloc(v1 + 1);\n v3 = v2;\n if ( v1 && v2 )\n {\n v4 = __ctype_toupper_loc();\n v5 = *v4;\n *v3 = (*v4)[*a1];\n if ( v1 != 1 )\n {\n v6 = *__ctype_tolower_loc();\n for ( i = 1LL; i != v1; ++i )\n v3[i] = v6[a1[i]];\n }\n *(_WORD *)&v3[v1 - 1] = (unsigned __int8)v5[(char)v3[v1 - 1]];\n }\n return v3;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 8\ncall _strlen\nlea rdi, [rax+1]; size\nmov rbx, rax\ncall _malloc\nmov rbp, rax\ntest rbx, rbx\njz short loc_134A\ntest rax, rax\njz short loc_134A\ncall ___ctype_toupper_loc\nmov r13, [rax]\nmovsx rax, byte ptr [r12]\nmov eax, [r13+rax*4+0]\nmov [rbp+0], al\ncmp rbx, 1\njz short loc_1335\ncall ___ctype_tolower_loc\nmov rcx, [rax]\nmov eax, 1\nnop word ptr [rax+rax+00000000h]\nloc_1320:\nmovsx rdx, byte ptr [r12+rax]\nmov edx, [rcx+rdx*4]\nmov [rbp+rax+0], dl\nadd rax, 1\ncmp rax, rbx\njnz short loc_1320\nloc_1335:\nlea rax, [rbp+rbx-1]\nmovsx rdx, byte ptr [rax]\nmov edx, [r13+rdx*4+0]\nmov [rax], dl\nmov byte ptr [rbp+rbx+0], 0\nloc_134A:\nadd rsp, 8\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_12C0(const char *a1)\n{\n size_t v1; // rbx\n _BYTE *v2; // rax\n _BYTE *v3; // rbp\n const __int32_t **v4; // rax\n const __int32_t *v5; // r13\n const __int32_t *v6; // rcx\n __int64 i; // rax\n\n v1 = strlen(a1);\n v2 = malloc(v1 + 1);\n v3 = v2;\n if ( v1 && v2 )\n {\n v4 = __ctype_toupper_loc();\n v5 = *v4;\n *v3 = (*v4)[*a1];\n if ( v1 != 1 )\n {\n v6 = *__ctype_tolower_loc();\n for ( i = 1LL; i != v1; ++i )\n v3[i] = v6[a1[i]];\n }\n *(_WORD *)&v3[v1 - 1] = (unsigned __int8)v5[(char)v3[v1 - 1]];\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_12C0(const char *a1) {\n unsigned int v1;\n uint8_t *v2;\n uint8_t *v3;\n const __int32_t **v4;\n const __int32_t *v5;\n const __int32_t *v6;\n long long i;\n v1 = strlen(a1);\n v2 = malloc(v1 + 1);\n v3 = v2;\n if (v1 && v2) {\n v4 = __ctype_toupper_loc();\n v5 = *v4;\n *v3 = (*v4)[*a1];\n if (v1 != 1) {\n v6 = *__ctype_tolower_loc();\n for (i = 1LL; i != v1; ++i) v3[i] = v6[a1[i]];\n }\n *(unsigned short *)&v3[v1 - 1] = (unsigned char)v5[(char)v3[v1 - 1]];\n }\n return v3;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1) {\n unsigned int v1;\n uint8_t *v2;\n uint8_t *v3;\n const __int32_t **v4;\n const __int32_t *v5;\n const __int32_t *v6;\n long long i;\n v1 = strlen(a1);\n v2 = malloc(v1 + 1);\n v3 = v2;\n if (v1 && v2) {\n v4 = __ctype_toupper_loc();\n v5 = *v4;\n *v3 = (*v4)[*a1];\n if (v1 != 1) {\n v6 = *__ctype_tolower_loc();\n for (i = 1LL; i != v1; ++i) v3[i] = v6[a1[i]];\n }\n *(unsigned short *)&v3[v1 - 1] = (unsigned char)v5[(char)v3[v1 - 1]];\n }\n return v3;\n}" + }, + { + "index": 527, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n, int sum) {\n int count = 0;\n for (int i = 0; i < n; i++) {\n for (int j = i + 1; j < n; j++) {\n if (arr[i] + arr[j] == sum) {\n count++;\n }\n }\n }\n return count;\n}", + "test": "int main() {\n\n int arr1[] = {1, 5, 7, -1, 5};\n\n int arr2[] = {1, 5, 7, -1};\n\n int arr3[] = {1, 1, 1, 1};\n\n\n\n assert(func0(arr1, 5, 6) == 3);\n\n assert(func0(arr2, 4, 6) == 2);\n\n assert(func0(arr3, 4, 2) == 6);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11dd \nmov -0x8(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x4(%rbp)\njmp 11d1 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\nadd %edx,%eax\ncmp %eax,-0x20(%rbp)\njne 11cd \naddl $0x1,-0xc(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1196 \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 118b \nmov -0xc(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_11DD\nloc_118B:\nmov eax, [rbp+var_8]\nadd eax, 1\nmov [rbp+var_4], eax\njmp short loc_11D1\nloc_1196:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nadd eax, edx\ncmp [rbp+var_20], eax\njnz short loc_11CD\nadd [rbp+var_C], 1\nloc_11CD:\nadd [rbp+var_4], 1\nloc_11D1:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1196\nadd [rbp+var_8], 1\nloc_11DD:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_118B\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n unsigned int v4; // [rsp+14h] [rbp-Ch]\n int i; // [rsp+18h] [rbp-8h]\n int j; // [rsp+1Ch] [rbp-4h]\n\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( a3 == *(_DWORD *)(4LL * i + a1) + *(_DWORD *)(4LL * j + a1) )\n ++v4;\n }\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_11DD\nloc_118B:\nmov eax, [rbp+var_8]\nadd eax, 1\nmov [rbp+var_4], eax\njmp short loc_11D1\nloc_1196:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nadd eax, edx\ncmp [rbp+var_20], eax\njnz short loc_11CD\nadd [rbp+var_C], 1\nloc_11CD:\nadd [rbp+var_4], 1\nloc_11D1:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1196\nadd [rbp+var_8], 1\nloc_11DD:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_118B\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n unsigned int v4; // [rsp+14h] [rbp-Ch]\n int i; // [rsp+18h] [rbp-8h]\n int j; // [rsp+1Ch] [rbp-4h]\n\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( a3 == *(_DWORD *)(4LL * i + a1) + *(_DWORD *)(4LL * j + a1) )\n ++v4;\n }\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n unsigned int v4;\n int i;\n int j;\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if (a3 == *(uint32_t *)(4LL * i + a1) + *(uint32_t *)(4LL * j + a1)) ++v4;\n }\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n unsigned int v4;\n int i;\n int j;\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if (a3 == *(uint32_t *)(4LL * i + a1) + *(uint32_t *)(4LL * j + a1)) ++v4;\n }\n }\n return v4;\n}" + }, + { + "index": 527, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n, int sum) {\n int count = 0;\n for (int i = 0; i < n; i++) {\n for (int j = i + 1; j < n; j++) {\n if (arr[i] + arr[j] == sum) {\n count++;\n }\n }\n }\n return count;\n}", + "test": "int main() {\n\n int arr1[] = {1, 5, 7, -1, 5};\n\n int arr2[] = {1, 5, 7, -1};\n\n int arr3[] = {1, 1, 1, 1};\n\n\n\n assert(func0(arr1, 5, 6) == 3);\n\n assert(func0(arr2, 4, 6) == 2);\n\n assert(func0(arr3, 4, 2) == 6);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11b4 \nlea -0x1(%rsi),%r11d\nadd $0x1,%r11\nmov $0x1,%r10d\nmov $0x0,%ecx\ncmp %r11,%r10\nje 11b9 \nmov -0x4(%rdi,%r10,4),%r9d\nmov %r10,%rax\nmov %r9d,%r8d\nadd (%rdi,%rax,4),%r8d\ncmp %edx,%r8d\nsete %r8b\nmovzbl %r8b,%r8d\nadd %r8d,%ecx\nadd $0x1,%rax\ncmp %eax,%esi\njg 1191 \nadd $0x1,%r10\njmp 1184 \nmov $0x0,%ecx\nmov %ecx,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11C0\npush rbx\nmov r8, rdi\nmov r11d, esi\nmovsxd rbx, esi\nmov r10d, 1\nmov ecx, 0\njmp short loc_118B\nloc_1188:\nmov r10, rax\nloc_118B:\ncmp r10, r11\njz short loc_11BC\nmov r9d, [r8+r10*4-4]\nmov rax, r10\nloc_1198:\nmov edi, r9d\nadd edi, [r8+rax*4]\ncmp edi, edx\nsetz dil\nmovzx edi, dil\nadd ecx, edi\nadd rax, 1\ncmp esi, eax\njg short loc_1198\nlea rax, [r10+1]\ncmp r10, rbx\njnz short loc_1188\nloc_11BC:\nmov eax, ecx\npop rbx\nretn\nloc_11C0:\nmov ecx, 0\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n __int64 v3; // r10\n unsigned int v4; // ecx\n __int64 v5; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v3 = 1LL;\n v4 = 0;\n while ( v3 != a2 )\n {\n v5 = v3;\n do\n v4 += *(_DWORD *)(a1 + 4 * v5++) + *(_DWORD *)(a1 + 4 * v3 - 4) == a3;\n while ( a2 > (int)v5 );\n if ( v3 == a2 )\n break;\n ++v3;\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11C0\npush rbx\nmov r8, rdi\nmov r11d, esi\nmovsxd rbx, esi\nmov r10d, 1\nmov ecx, 0\njmp short loc_118B\nloc_1188:\nmov r10, rax\nloc_118B:\ncmp r10, r11\njz short loc_11BC\nmov r9d, [r8+r10*4-4]\nmov rax, r10\nloc_1198:\nmov edi, r9d\nadd edi, [r8+rax*4]\ncmp edi, edx\nsetz dil\nmovzx edi, dil\nadd ecx, edi\nadd rax, 1\ncmp esi, eax\njg short loc_1198\nlea rax, [r10+1]\ncmp r10, rbx\njnz short loc_1188\nloc_11BC:\nmov eax, ecx\npop rbx\nretn\nloc_11C0:\nmov ecx, 0\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n __int64 v3; // r10\n unsigned int v4; // ecx\n __int64 v5; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v3 = 1LL;\n v4 = 0;\n while ( v3 != a2 )\n {\n v5 = v3;\n do\n v4 += *(_DWORD *)(a1 + 4 * v5++) + *(_DWORD *)(a1 + 4 * v3 - 4) == a3;\n while ( a2 > (int)v5 );\n if ( v3 == a2 )\n break;\n ++v3;\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n long long v3;\n unsigned int v4;\n long long v5;\n if (a2 <= 0) return 0LL;\n v3 = 1LL;\n v4 = 0;\n while (v3 != a2) {\n v5 = v3;\n do\n v4 += *(uint32_t *)(a1 + 4 * v5++) + *(uint32_t *)(a1 + 4 * v3 - 4) == a3;\n while (a2 > (int)v5);\n if (v3 == a2) break;\n ++v3;\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n long long v3;\n unsigned int v4;\n long long v5;\n if (a2 <= 0) return 0LL;\n v3 = 1LL;\n v4 = 0;\n while (v3 != a2) {\n v5 = v3;\n do\n v4 += *(uint32_t *)(a1 + 4 * v5++) + *(uint32_t *)(a1 + 4 * v3 - 4) == a3;\n while (a2 > (int)v5);\n if (v3 == a2) break;\n ++v3;\n }\n return v4;\n}" + }, + { + "index": 527, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n, int sum) {\n int count = 0;\n for (int i = 0; i < n; i++) {\n for (int j = i + 1; j < n; j++) {\n if (arr[i] + arr[j] == sum) {\n count++;\n }\n }\n }\n return count;\n}", + "test": "int main() {\n\n int arr1[] = {1, 5, 7, -1, 5};\n\n int arr2[] = {1, 5, 7, -1};\n\n int arr3[] = {1, 1, 1, 1};\n\n\n\n assert(func0(arr1, 5, 6) == 3);\n\n assert(func0(arr2, 4, 6) == 2);\n\n assert(func0(arr3, 4, 2) == 6);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1386 \nlea -0x1(%rsi),%r11d\nmov $0x1,%r10d\nxor %r8d,%r8d\nadd $0x1,%r11\ncmp %r11,%r10\nje 1382 \nxchg %ax,%ax\nmov -0x4(%rdi,%r10,4),%r9d\nmov %r10,%rax\nnopl 0x0(%rax,%rax,1)\nmov (%rdi,%rax,4),%ecx\nadd %r9d,%ecx\ncmp %edx,%ecx\nsete %cl\nadd $0x1,%rax\nmovzbl %cl,%ecx\nadd %ecx,%r8d\ncmp %eax,%esi\njg 1360 \nadd $0x1,%r10\ncmp %r11,%r10\njne 1350 \nmov %r8d,%eax\nretq\nxor %r8d,%r8d\nmov %r8d,%eax\nretq\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_12C9\nmov r11d, esi\nmov r10d, 1\nxor ecx, ecx\ncmp esi, 1\njz short loc_12C6\nnop dword ptr [rax+rax+00000000h]\nloc_1290:\nmov r9d, [rdi+r10*4-4]\nmov rax, r10\nnop dword ptr [rax+rax+00000000h]\nloc_12A0:\nmov r8d, [rdi+rax*4]\nadd r8d, r9d\ncmp edx, r8d\nsetz r8b\nadd rax, 1\nmovzx r8d, r8b\nadd ecx, r8d\ncmp esi, eax\njg short loc_12A0\nadd r10, 1\ncmp r10, r11\njnz short loc_1290\nloc_12C6:\nmov eax, ecx\nretn\nloc_12C9:\nxor ecx, ecx\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n __int64 v3; // r10\n unsigned int v4; // ecx\n __int64 v5; // rax\n bool v6; // r8\n\n if ( a2 <= 0 )\n return 0LL;\n v3 = 1LL;\n v4 = 0;\n if ( a2 != 1 )\n {\n do\n {\n v5 = v3;\n do\n {\n v6 = a3 == *(_DWORD *)(a1 + 4 * v3 - 4) + *(_DWORD *)(a1 + 4 * v5++);\n v4 += v6;\n }\n while ( a2 > (int)v5 );\n ++v3;\n }\n while ( v3 != a2 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_1270:\nendbr64\ntest esi, esi\njle short loc_12C9\nmov r11d, esi\nmov r10d, 1\nxor ecx, ecx\ncmp esi, 1\njz short loc_12C6\nnop dword ptr [rax+rax+00000000h]\nloc_1290:\nmov r9d, [rdi+r10*4-4]\nmov rax, r10\nnop dword ptr [rax+rax+00000000h]\nloc_12A0:\nmov r8d, [rdi+rax*4]\nadd r8d, r9d\ncmp edx, r8d\nsetz r8b\nadd rax, 1\nmovzx r8d, r8b\nadd ecx, r8d\ncmp esi, eax\njg short loc_12A0\nadd r10, 1\ncmp r10, r11\njnz short loc_1290\nloc_12C6:\nmov eax, ecx\nretn\nloc_12C9:\nxor ecx, ecx\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1270(__int64 a1, int a2, int a3)\n{\n __int64 v3; // r10\n unsigned int v4; // ecx\n __int64 v5; // rax\n bool v6; // r8\n\n if ( a2 <= 0 )\n return 0LL;\n v3 = 1LL;\n v4 = 0;\n if ( a2 != 1 )\n {\n do\n {\n v5 = v3;\n do\n {\n v6 = a3 == *(_DWORD *)(a1 + 4 * v3 - 4) + *(_DWORD *)(a1 + 4 * v5++);\n v4 += v6;\n }\n while ( a2 > (int)v5 );\n ++v3;\n }\n while ( v3 != a2 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1270(long long a1, int a2, int a3) {\n long long v3;\n unsigned int v4;\n long long v5;\n bool v6;\n if (a2 <= 0) return 0LL;\n v3 = 1LL;\n v4 = 0;\n if (a2 != 1) {\n do {\n v5 = v3;\n do {\n v6 =\n a3 == *(uint32_t *)(a1 + 4 * v3 - 4) + *(uint32_t *)(a1 + 4 * v5++);\n v4 += v6;\n } while (a2 > (int)v5);\n ++v3;\n } while (v3 != a2);\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n long long v3;\n unsigned int v4;\n long long v5;\n bool v6;\n if (a2 <= 0) return 0LL;\n v3 = 1LL;\n v4 = 0;\n if (a2 != 1) {\n do {\n v5 = v3;\n do {\n v6 =\n a3 == *(uint32_t *)(a1 + 4 * v3 - 4) + *(uint32_t *)(a1 + 4 * v5++);\n v4 += v6;\n } while (a2 > (int)v5);\n ++v3;\n } while (v3 != a2);\n }\n return v4;\n}" + }, + { + "index": 528, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\ntypedef struct {\n\n int length;\n\n int *list;\n\n} MinResult;\n\n\n\n", + "func": "MinResult func0(int **list1, int size) {\n int min_length = 1000000;\n int *min_list = NULL;\n for (int i = 0; i < size; i++) {\n int list_length = 0;\n while (list1[i][list_length] != -1) {\n list_length++;\n }\n if (list_length < min_length) {\n min_length = list_length;\n min_list = list1[i];\n }\n }\n MinResult result;\n result.length = min_length;\n result.list = min_list;\n return result;\n}", + "test": "int main() {\n\n int list1[5][4] = {{0, -1}, {1, 3, -1}, {5, 7, -1}, {9, 11, -1}, {13, 15, 17, -1}};\n\n int *plist1[5] = {list1[0], list1[1], list1[2], list1[3], list1[4]};\n\n MinResult res1 = func0(plist1, 5);\n\n assert(res1.length == 1 && res1.list[0] == 0);\n\n\n\n int list2[3][5] = {{1, -1}, {5, 7, -1}, {10, 12, 14, 15, -1}};\n\n int *plist2[3] = {list2[0], list2[1], list2[2]};\n\n MinResult res2 = func0(plist2, 3);\n\n assert(res2.length == 1 && res2.list[0] == 1);\n\n\n\n int list3[2][4] = {{5, -1}, {15, 20, 25, -1}};\n\n int *plist3[2] = {list3[0], list3[1]};\n\n MinResult res3 = func0(plist3, 2);\n\n assert(res3.length == 1 && res3.list[0] == 5);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nmov %rdi,-0x40(%rbp)\nmov %esi,-0x44(%rbp)\nmovl $0xf4240,-0x2c(%rbp)\nmovq $0x0,-0x20(%rbp)\nmovl $0x0,-0x28(%rbp)\njmp 11f6 \nmovl $0x0,-0x24(%rbp)\njmp 119e \naddl $0x1,-0x24(%rbp)\nmov -0x28(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x40(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0x24(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x2,%rdx\nadd %rdx,%rax\nmov (%rax),%eax\ncmp $0xffffffff,%eax\njne 119a \nmov -0x24(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njge 11f2 \nmov -0x24(%rbp),%eax\nmov %eax,-0x2c(%rbp)\nmov -0x28(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x40(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov %rax,-0x20(%rbp)\naddl $0x1,-0x28(%rbp)\nmov -0x28(%rbp),%eax\ncmp -0x44(%rbp),%eax\njl 1191 \nmov -0x2c(%rbp),%eax\nmov %eax,-0x18(%rbp)\nmov -0x20(%rbp),%rax\nmov %rax,-0x10(%rbp)\nmov -0x18(%rbp),%rax\nmov -0x10(%rbp),%rdx\nmov %rax,%rcx\nmov %rdx,%rbx\nmov %ecx,%eax\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nmov [rbp+var_48], rdi\nmov [rbp+var_4C], esi\nmov [rbp+var_34], 0F4240h\nmov [rbp+var_28], 0\nmov [rbp+var_30], 0\njmp short loc_11F6\nloc_1191:\nmov [rbp+var_2C], 0\njmp short loc_119E\nloc_119A:\nadd [rbp+var_2C], 1\nloc_119E:\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_2C]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\ncmp eax, 0FFFFFFFFh\njnz short loc_119A\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_34]\njge short loc_11F2\nmov eax, [rbp+var_2C]\nmov [rbp+var_34], eax\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov rax, [rax]\nmov [rbp+var_28], rax\nloc_11F2:\nadd [rbp+var_30], 1\nloc_11F6:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_4C]\njl short loc_1191\nmov eax, [rbp+var_34]\nmov dword ptr [rbp+var_20], eax\nmov rax, [rbp+var_28]\nmov [rbp+var_18], rax\nmov rax, [rbp+var_20]\nmov rdx, [rbp+var_18]\nmov rsi, rax\nmov rdi, rdx\nmov rcx, rax\nmov rbx, rdx\nmov eax, esi\nmov rdx, rbx\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int v3; // [rsp+18h] [rbp-34h]\n int i; // [rsp+1Ch] [rbp-30h]\n int j; // [rsp+20h] [rbp-2Ch]\n\n v3 = 1000000;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = 0; *(_DWORD *)(4LL * j + *(_QWORD *)(8LL * i + a1)) != -1; ++j )\n ;\n if ( j < v3 )\n v3 = j;\n }\n return (unsigned int)v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nmov [rbp+var_48], rdi\nmov [rbp+var_4C], esi\nmov [rbp+var_34], 0F4240h\nmov [rbp+var_28], 0\nmov [rbp+var_30], 0\njmp short loc_11F6\nloc_1191:\nmov [rbp+var_2C], 0\njmp short loc_119E\nloc_119A:\nadd [rbp+var_2C], 1\nloc_119E:\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_2C]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\ncmp eax, 0FFFFFFFFh\njnz short loc_119A\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_34]\njge short loc_11F2\nmov eax, [rbp+var_2C]\nmov [rbp+var_34], eax\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov rax, [rax]\nmov [rbp+var_28], rax\nloc_11F2:\nadd [rbp+var_30], 1\nloc_11F6:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_4C]\njl short loc_1191\nmov eax, [rbp+var_34]\nmov dword ptr [rbp+var_20], eax\nmov rax, [rbp+var_28]\nmov [rbp+var_18], rax\nmov rax, [rbp+var_20]\nmov rdx, [rbp+var_18]\nmov rsi, rax\nmov rdi, rdx\nmov rcx, rax\nmov rbx, rdx\nmov eax, esi\nmov rdx, rbx\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int v3; // [rsp+18h] [rbp-34h]\n int i; // [rsp+1Ch] [rbp-30h]\n int j; // [rsp+20h] [rbp-2Ch]\n\n v3 = 1000000;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = 0; *(_DWORD *)(4LL * j + *(_QWORD *)(8LL * i + a1)) != -1; ++j )\n ;\n if ( j < v3 )\n v3 = j;\n }\n return (unsigned int)v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int v3;\n int i;\n int j;\n v3 = 1000000;\n for (i = 0; i < a2; ++i) {\n for (j = 0; *(uint32_t *)(4LL * j + *(uint64_t *)(8LL * i + a1)) != -1; ++j)\n ;\n if (j < v3) v3 = j;\n }\n return (unsigned int)v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int v3;\n int i;\n int j;\n v3 = 1000000;\n for (i = 0; i < a2; ++i) {\n for (j = 0; *(uint32_t *)(4LL * j + *(uint64_t *)(8LL * i + a1)) != -1; ++j)\n ;\n if (j < v3) v3 = j;\n }\n return (unsigned int)v3;\n}" + }, + { + "index": 528, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\ntypedef struct {\n\n int length;\n\n int *list;\n\n} MinResult;\n\n\n\n", + "func": "MinResult func0(int **list1, int size) {\n int min_length = 1000000;\n int *min_list = NULL;\n for (int i = 0; i < size; i++) {\n int list_length = 0;\n while (list1[i][list_length] != -1) {\n list_length++;\n }\n if (list_length < min_length) {\n min_length = list_length;\n min_list = list1[i];\n }\n }\n MinResult result;\n result.length = min_length;\n result.list = min_list;\n return result;\n}", + "test": "int main() {\n\n int list1[5][4] = {{0, -1}, {1, 3, -1}, {5, 7, -1}, {9, 11, -1}, {13, 15, 17, -1}};\n\n int *plist1[5] = {list1[0], list1[1], list1[2], list1[3], list1[4]};\n\n MinResult res1 = func0(plist1, 5);\n\n assert(res1.length == 1 && res1.list[0] == 0);\n\n\n\n int list2[3][5] = {{1, -1}, {5, 7, -1}, {10, 12, 14, 15, -1}};\n\n int *plist2[3] = {list2[0], list2[1], list2[2]};\n\n MinResult res2 = func0(plist2, 3);\n\n assert(res2.length == 1 && res2.list[0] == 1);\n\n\n\n int list3[2][4] = {{5, -1}, {15, 20, 25, -1}};\n\n int *plist3[2] = {list3[0], list3[1]};\n\n MinResult res3 = func0(plist3, 2);\n\n assert(res3.length == 1 && res3.list[0] == 5);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11c0 \nmov %rdi,%r8\nlea -0x1(%rsi),%eax\nlea 0x8(%rdi,%rax,8),%rdi\nmov $0x0,%r9d\nmov $0xf4240,%esi\nmov $0x0,%r10d\njmp 1198 \nadd $0x8,%r8\ncmp %rdi,%r8\nje 11cb \nmov (%r8),%rdx\nmov $0x1,%eax\nmov %r10d,%ecx\ncmpl $0xffffffff,(%rdx)\nje 11b5 \nmov %eax,%ecx\nadd $0x1,%rax\ncmpl $0xffffffff,-0x4(%rdx,%rax,4)\njne 11a8 \ncmp %ecx,%esi\njle 118f \nmov %rdx,%r9\nmov %ecx,%esi\njmp 118f \nmov $0x0,%r9d\nmov $0xf4240,%esi\nmov %esi,%eax\nmov %r9,%rdx\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11C0\nmov r8, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*8]\nmov r9d, 0\nmov eax, 0F4240h\nmov r10d, 0\njmp short loc_1197\nloc_118E:\nadd r8, 8\ncmp r8, rdi\njz short loc_11CB\nloc_1197:\nmov rsi, [r8]\nmov edx, 1\nmov ecx, r10d\ncmp dword ptr [rsi], 0FFFFFFFFh\njz short loc_11B5\nloc_11A7:\nmov rcx, rdx\nadd rdx, 1\ncmp dword ptr [rsi+rdx*4-4], 0FFFFFFFFh\njnz short loc_11A7\nloc_11B5:\ncmp eax, ecx\njle short loc_118E\nmov r9, rsi\nmov eax, ecx\njmp short loc_118E\nloc_11C0:\nmov r9d, 0\nmov eax, 0F4240h\nloc_11CB:\nmov rdx, r9\nretn", + "ida_pseudo": "__int64 __fastcall func0(_QWORD *a1, int a2)\n{\n _QWORD *v2; // r8\n _QWORD *v3; // rdi\n __int64 result; // rax\n __int64 v5; // rdx\n int v6; // ecx\n\n if ( a2 <= 0 )\n return 1000000LL;\n v2 = a1;\n v3 = &a1[a2];\n result = 1000000LL;\n do\n {\n v5 = 1LL;\n v6 = 0;\n if ( *(_DWORD *)*v2 != -1 )\n {\n do\n v6 = v5++;\n while ( *(_DWORD *)(*v2 + 4 * v5 - 4) != -1 );\n }\n if ( (int)result > v6 )\n result = (unsigned int)v6;\n ++v2;\n }\n while ( v2 != v3 );\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11C0\nmov r8, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*8]\nmov r9d, 0\nmov eax, 0F4240h\nmov r10d, 0\njmp short loc_1197\nloc_118E:\nadd r8, 8\ncmp r8, rdi\njz short loc_11CB\nloc_1197:\nmov rsi, [r8]\nmov edx, 1\nmov ecx, r10d\ncmp dword ptr [rsi], 0FFFFFFFFh\njz short loc_11B5\nloc_11A7:\nmov rcx, rdx\nadd rdx, 1\ncmp dword ptr [rsi+rdx*4-4], 0FFFFFFFFh\njnz short loc_11A7\nloc_11B5:\ncmp eax, ecx\njle short loc_118E\nmov r9, rsi\nmov eax, ecx\njmp short loc_118E\nloc_11C0:\nmov r9d, 0\nmov eax, 0F4240h\nloc_11CB:\nmov rdx, r9\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_QWORD *a1, int a2)\n{\n _QWORD *v2; // r8\n _QWORD *v3; // rdi\n __int64 result; // rax\n __int64 v5; // rdx\n int v6; // ecx\n\n if ( a2 <= 0 )\n return 1000000LL;\n v2 = a1;\n v3 = &a1[a2];\n result = 1000000LL;\n do\n {\n v5 = 1LL;\n v6 = 0;\n if ( *(_DWORD *)*v2 != -1 )\n {\n do\n v6 = v5++;\n while ( *(_DWORD *)(*v2 + 4 * v5 - 4) != -1 );\n }\n if ( (int)result > v6 )\n result = (unsigned int)v6;\n ++v2;\n }\n while ( v2 != v3 );\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint64_t *a1, int a2) {\n uint64_t *v2;\n uint64_t *v3;\n long long result;\n long long v5;\n int v6;\n if (a2 <= 0) return 1000000LL;\n v2 = a1;\n v3 = &a1[a2];\n result = 1000000LL;\n do {\n v5 = 1LL;\n v6 = 0;\n if (*(uint32_t *)*v2 != -1) {\n do\n v6 = v5++;\n while (*(uint32_t *)(*v2 + 4 * v5 - 4) != -1);\n }\n if ((int)result > v6) result = (unsigned int)v6;\n ++v2;\n } while (v2 != v3);\n return result;\n}", + "ida_pseudo_norm": "long long func0(uint64_t *a1, int a2) {\n uint64_t *v2;\n uint64_t *v3;\n long long result;\n long long v5;\n int v6;\n if (a2 <= 0) return 1000000LL;\n v2 = a1;\n v3 = &a1[a2];\n result = 1000000LL;\n do {\n v5 = 1LL;\n v6 = 0;\n if (*(uint32_t *)*v2 != -1) {\n do\n v6 = v5++;\n while (*(uint32_t *)(*v2 + 4 * v5 - 4) != -1);\n }\n if ((int)result > v6) result = (unsigned int)v6;\n ++v2;\n } while (v2 != v3);\n return result;\n}" + }, + { + "index": 528, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\ntypedef struct {\n\n int length;\n\n int *list;\n\n} MinResult;\n\n\n\n", + "func": "MinResult func0(int **list1, int size) {\n int min_length = 1000000;\n int *min_list = NULL;\n for (int i = 0; i < size; i++) {\n int list_length = 0;\n while (list1[i][list_length] != -1) {\n list_length++;\n }\n if (list_length < min_length) {\n min_length = list_length;\n min_list = list1[i];\n }\n }\n MinResult result;\n result.length = min_length;\n result.list = min_list;\n return result;\n}", + "test": "int main() {\n\n int list1[5][4] = {{0, -1}, {1, 3, -1}, {5, 7, -1}, {9, 11, -1}, {13, 15, 17, -1}};\n\n int *plist1[5] = {list1[0], list1[1], list1[2], list1[3], list1[4]};\n\n MinResult res1 = func0(plist1, 5);\n\n assert(res1.length == 1 && res1.list[0] == 0);\n\n\n\n int list2[3][5] = {{1, -1}, {5, 7, -1}, {10, 12, 14, 15, -1}};\n\n int *plist2[3] = {list2[0], list2[1], list2[2]};\n\n MinResult res2 = func0(plist2, 3);\n\n assert(res2.length == 1 && res2.list[0] == 1);\n\n\n\n int list3[2][4] = {{5, -1}, {15, 20, 25, -1}};\n\n int *plist3[2] = {list3[0], list3[1]};\n\n MinResult res3 = func0(plist3, 2);\n\n assert(res3.length == 1 && res3.list[0] == 5);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1475 \nlea -0x1(%rsi),%eax\nxor %r9d,%r9d\nmov $0xf4240,%esi\nlea 0x8(%rdi,%rax,8),%r8\nnopl 0x0(%rax,%rax,1)\nmov (%rdi),%rdx\nxor %ecx,%ecx\nmov $0x1,%eax\ncmpl $0xffffffff,(%rdx)\nje 145d \nmov %eax,%ecx\nadd $0x1,%rax\ncmpl $0xffffffff,-0x4(%rdx,%rax,4)\njne 1450 \ncmp %ecx,%esi\njle 1466 \nmov %rdx,%r9\nmov %ecx,%esi\nadd $0x8,%rdi\ncmp %r8,%rdi\njne 1440 \nmov %r9,%rdx\nmov %esi,%eax\nretq\nxor %r9d,%r9d\nmov $0xf4240,%esi\nmov %r9,%rdx\nmov %esi,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1464\nmovsxd rsi, esi\nxor r9d, r9d\nmov eax, 0F4240h\nlea r8, [rdi+rsi*8]\nnop word ptr [rax+rax+00000000h]\nloc_1430:\nmov rsi, [rdi]\nxor ecx, ecx\nmov edx, 1\ncmp dword ptr [rsi], 0FFFFFFFFh\njz short loc_144E\nnop\nloc_1440:\nmov rcx, rdx\nadd rdx, 1\ncmp dword ptr [rsi+rdx*4-4], 0FFFFFFFFh\njnz short loc_1440\nloc_144E:\ncmp eax, ecx\njle short loc_1457\nmov r9, rsi\nmov eax, ecx\nloc_1457:\nadd rdi, 8\ncmp rdi, r8\njnz short loc_1430\nmov rdx, r9\nretn\nloc_1464:\nxor r9d, r9d\nmov eax, 0F4240h\nmov rdx, r9\nretn", + "ida_pseudo": "__int64 __fastcall func0(_QWORD *a1, int a2)\n{\n __int64 result; // rax\n _QWORD *v3; // r8\n int v4; // ecx\n __int64 v5; // rdx\n\n if ( a2 <= 0 )\n return 1000000LL;\n result = 1000000LL;\n v3 = &a1[a2];\n do\n {\n v4 = 0;\n v5 = 1LL;\n if ( *(_DWORD *)*a1 != -1 )\n {\n do\n v4 = v5++;\n while ( *(_DWORD *)(*a1 + 4 * v5 - 4) != -1 );\n }\n if ( (int)result > v4 )\n result = (unsigned int)v4;\n ++a1;\n }\n while ( a1 != v3 );\n return result;\n}", + "ida_strip_asm": "sub_1410:\nendbr64\ntest esi, esi\njle short loc_1464\nmovsxd rsi, esi\nxor r9d, r9d\nmov eax, 0F4240h\nlea r8, [rdi+rsi*8]\nnop word ptr [rax+rax+00000000h]\nloc_1430:\nmov rsi, [rdi]\nxor ecx, ecx\nmov edx, 1\ncmp dword ptr [rsi], 0FFFFFFFFh\njz short loc_144E\nnop\nloc_1440:\nmov rcx, rdx\nadd rdx, 1\ncmp dword ptr [rsi+rdx*4-4], 0FFFFFFFFh\njnz short loc_1440\nloc_144E:\ncmp eax, ecx\njle short loc_1457\nmov r9, rsi\nmov eax, ecx\nloc_1457:\nadd rdi, 8\ncmp rdi, r8\njnz short loc_1430\nmov rdx, r9\nretn\nloc_1464:\nxor r9d, r9d\nmov eax, 0F4240h\nmov rdx, r9\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1410(_QWORD *a1, int a2)\n{\n __int64 result; // rax\n _QWORD *v3; // r8\n int v4; // ecx\n __int64 v5; // rdx\n\n if ( a2 <= 0 )\n return 1000000LL;\n result = 1000000LL;\n v3 = &a1[a2];\n do\n {\n v4 = 0;\n v5 = 1LL;\n if ( *(_DWORD *)*a1 != -1 )\n {\n do\n v4 = v5++;\n while ( *(_DWORD *)(*a1 + 4 * v5 - 4) != -1 );\n }\n if ( (int)result > v4 )\n result = (unsigned int)v4;\n ++a1;\n }\n while ( a1 != v3 );\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1410(uint64_t *a1, int a2) {\n long long result;\n uint64_t *v3;\n int v4;\n long long v5;\n if (a2 <= 0) return 1000000LL;\n result = 1000000LL;\n v3 = &a1[a2];\n do {\n v4 = 0;\n v5 = 1LL;\n if (*(uint32_t *)*a1 != -1) {\n do\n v4 = v5++;\n while (*(uint32_t *)(*a1 + 4 * v5 - 4) != -1);\n }\n if ((int)result > v4) result = (unsigned int)v4;\n ++a1;\n } while (a1 != v3);\n return result;\n}", + "ida_pseudo_norm": "long long func0(uint64_t *a1, int a2) {\n long long result;\n uint64_t *v3;\n int v4;\n long long v5;\n if (a2 <= 0) return 1000000LL;\n result = 1000000LL;\n v3 = &a1[a2];\n do {\n v4 = 0;\n v5 = 1LL;\n if (*(uint32_t *)*a1 != -1) {\n do\n v4 = v5++;\n while (*(uint32_t *)(*a1 + 4 * v5 - 4) != -1);\n }\n if ((int)result > v4) result = (unsigned int)v4;\n ++a1;\n } while (a1 != v3);\n return result;\n}" + }, + { + "index": 529, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int dp[n + 1];\n dp[0] = 2;\n dp[1] = 1;\n for (int i = 2; i <= n; i++) {\n dp[i] = dp[i - 1] + 2 * dp[i - 2];\n }\n return dp[n];\n}", + "test": "int main() {\n\n assert(func0(5) == 31);\n\n assert(func0(2) == 5);\n\n assert(func0(4) == 17);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x38,%rsp\nmov %edi,-0x34(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmov %rsp,%rax\nmov %rax,%rsi\nmov -0x34(%rbp),%eax\nadd $0x1,%eax\nmovslq %eax,%rdx\nsub $0x1,%rdx\nmov %rdx,-0x28(%rbp)\nmovslq %eax,%rdx\nmov %rdx,%r8\nmov $0x0,%r9d\nmovslq %eax,%rdx\nmov %rdx,%rcx\nmov $0x0,%ebx\ncltq\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%edi\nmov $0x0,%edx\ndiv %rdi\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rbx\nsub %rdx,%rbx\nmov %rbx,%rdx\ncmp %rdx,%rsp\nje 1207 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11f0 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 1231 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x20(%rbp)\nmov -0x20(%rbp),%rax\nmovl $0x2,(%rax)\nmov -0x20(%rbp),%rax\nmovl $0x1,0x4(%rax)\nmovl $0x2,-0x2c(%rbp)\njmp 1297 \nmov -0x2c(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x20(%rbp),%rax\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%ecx\nmov -0x2c(%rbp),%eax\nlea -0x2(%rax),%edx\nmov -0x20(%rbp),%rax\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nadd %eax,%eax\nadd %eax,%ecx\nmov -0x20(%rbp),%rax\nmov -0x2c(%rbp),%edx\nmovslq %edx,%rdx\nmov %ecx,(%rax,%rdx,4)\naddl $0x1,-0x2c(%rbp)\nmov -0x2c(%rbp),%eax\ncmp -0x34(%rbp),%eax\njle 1262 \nmov -0x20(%rbp),%rax\nmov -0x34(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nmov %rsi,%rsp\nmov -0x18(%rbp),%rdi\nxor %fs:0x28,%rdi\nje 12c3 \ncallq 1060 <__stack_chk_fail@plt>\nmov -0x8(%rbp),%rbx\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_24], edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov eax, [rbp+var_24]\nadd eax, 1\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11D5:\ncmp rsp, rdx\njz short loc_11EC\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\njmp short loc_11D5\nloc_11EC:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1216\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1216:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov rax, [rbp+var_10]\nmov dword ptr [rax], 2\nmov rax, [rbp+var_10]\nmov dword ptr [rax+4], 1\nmov [rbp+var_1C], 2\njmp short loc_127C\nloc_1247:\nmov eax, [rbp+var_1C]\nlea edx, [rax-1]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov eax, [rbp+var_1C]\nlea edx, [rax-2]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nadd eax, eax\nadd ecx, eax\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nadd [rbp+var_1C], 1\nloc_127C:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_24]\njle short loc_1247\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12A8\ncall ___stack_chk_fail\nlocret_12A8:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned __int64 v1; // rax\n void *v2; // rsp\n _DWORD v4[3]; // [rsp+8h] [rbp-30h] BYREF\n int v5; // [rsp+14h] [rbp-24h]\n int i; // [rsp+1Ch] [rbp-1Ch]\n __int64 v7; // [rsp+20h] [rbp-18h]\n _DWORD *v8; // [rsp+28h] [rbp-10h]\n unsigned __int64 v9; // [rsp+30h] [rbp-8h]\n\n v5 = a1;\n v9 = __readfsqword(0x28u);\n v7 = a1 + 1 - 1LL;\n v1 = 16 * ((4LL * (a1 + 1) + 15) / 0x10uLL);\n while ( v4 != (_DWORD *)((char *)v4 - (v1 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v2 = alloca(v1 & 0xFFF);\n if ( (v1 & 0xFFF) != 0 )\n *(_QWORD *)((char *)&v4[-2] + (v1 & 0xFFF)) = *(_QWORD *)((char *)&v4[-2] + (v1 & 0xFFF));\n v8 = v4;\n v4[0] = 2;\n v4[1] = 1;\n for ( i = 2; i <= v5; ++i )\n v8[i] = 2 * v8[i - 2] + v8[i - 1];\n return (unsigned int)v8[v5];\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_24], edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov eax, [rbp+var_24]\nadd eax, 1\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11D5:\ncmp rsp, rdx\njz short loc_11EC\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\njmp short loc_11D5\nloc_11EC:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1216\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1216:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov rax, [rbp+var_10]\nmov dword ptr [rax], 2\nmov rax, [rbp+var_10]\nmov dword ptr [rax+4], 1\nmov [rbp+var_1C], 2\njmp short loc_127C\nloc_1247:\nmov eax, [rbp+var_1C]\nlea edx, [rax-1]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov eax, [rbp+var_1C]\nlea edx, [rax-2]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nadd eax, eax\nadd ecx, eax\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nadd [rbp+var_1C], 1\nloc_127C:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_24]\njle short loc_1247\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12A8\ncall ___stack_chk_fail\nlocret_12A8:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n unsigned __int64 v1; // rax\n void *v2; // rsp\n _DWORD v4[3]; // [rsp+8h] [rbp-30h] BYREF\n int v5; // [rsp+14h] [rbp-24h]\n int i; // [rsp+1Ch] [rbp-1Ch]\n __int64 v7; // [rsp+20h] [rbp-18h]\n _DWORD *v8; // [rsp+28h] [rbp-10h]\n unsigned __int64 v9; // [rsp+30h] [rbp-8h]\n\n v5 = a1;\n v9 = __readfsqword(0x28u);\n v7 = a1 + 1 - 1LL;\n v1 = 16 * ((4LL * (a1 + 1) + 15) / 0x10uLL);\n while ( v4 != (_DWORD *)((char *)v4 - (v1 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v2 = alloca(v1 & 0xFFF);\n if ( (v1 & 0xFFF) != 0 )\n *(_QWORD *)((char *)&v4[-2] + (v1 & 0xFFF)) = *(_QWORD *)((char *)&v4[-2] + (v1 & 0xFFF));\n v8 = v4;\n v4[0] = 2;\n v4[1] = 1;\n for ( i = 2; i <= v5; ++i )\n v8[i] = 2 * v8[i - 2] + v8[i - 1];\n return (unsigned int)v8[v5];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n unsigned long long v1;\n void *v2;\n uint32_t v4[3];\n int v5;\n int i;\n long long v7;\n uint32_t *v8;\n unsigned long long v9;\n v5 = a1;\n v9 = __readfsqword(40u);\n v7 = a1 + 1 - 1LL;\n v1 = 16 * ((4LL * (a1 + 1) + 15) / 16uLL);\n while (v4 != (uint32_t *)((char *)v4 - (v1 & 18446744073709547520LL)))\n ;\n v2 = alloca(v1 & 4095);\n if ((v1 & 4095) != 0)\n *(uint64_t *)((char *)&v4[-2] + (v1 & 4095)) =\n *(uint64_t *)((char *)&v4[-2] + (v1 & 4095));\n v8 = v4;\n v4[0] = 2;\n v4[1] = 1;\n for (i = 2; i <= v5; ++i) v8[i] = 2 * v8[i - 2] + v8[i - 1];\n return (unsigned int)v8[v5];\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned long long v1;\n void *v2;\n uint32_t v4[3];\n int v5;\n int i;\n long long v7;\n uint32_t *v8;\n unsigned long long v9;\n v5 = a1;\n v9 = __readfsqword(40u);\n v7 = a1 + 1 - 1LL;\n v1 = 16 * ((4LL * (a1 + 1) + 15) / 16uLL);\n while (v4 != (uint32_t *)((char *)v4 - (v1 & 18446744073709547520LL)))\n ;\n v2 = alloca(v1 & 4095);\n if ((v1 & 4095) != 0)\n *(uint64_t *)((char *)&v4[-2] + (v1 & 4095)) =\n *(uint64_t *)((char *)&v4[-2] + (v1 & 4095));\n v8 = v4;\n v4[0] = 2;\n v4[1] = 1;\n for (i = 2; i <= v5; ++i) v8[i] = 2 * v8[i - 2] + v8[i - 1];\n return (unsigned int)v8[v5];\n}" + }, + { + "index": 529, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int dp[n + 1];\n dp[0] = 2;\n dp[1] = 1;\n for (int i = 2; i <= n; i++) {\n dp[i] = dp[i - 1] + 2 * dp[i - 2];\n }\n return dp[n];\n}", + "test": "int main() {\n\n assert(func0(5) == 31);\n\n assert(func0(2) == 5);\n\n assert(func0(4) == 17);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0x1(%rdi),%eax\ncltq\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffffff0,%rdx\nand $0xfffffffffffff000,%rax\nmov %rsp,%rsi\nsub %rax,%rsi\nmov %rsi,%rax\ncmp %rax,%rsp\nje 11be \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11a7 \nmov %rdx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 11d4 \norq $0x0,-0x8(%rsp,%rax,1)\nlea 0x3(%rsp),%r8\nmov %r8,%rax\nshr $0x2,%rax\nand $0xfffffffffffffffc,%r8\nmovl $0x2,0x0(,%rax,4)\nmovl $0x1,0x4(,%rax,4)\ncmp $0x1,%edi\njle 121e \nmov %r8,%rax\nlea -0x2(%rdi),%edx\nlea 0x4(%r8,%rdx,4),%rsi\nmov (%rax),%ecx\nmov 0x4(%rax),%edx\nlea (%rdx,%rcx,2),%edx\nmov %edx,0x8(%rax)\nadd $0x4,%rax\ncmp %rsi,%rax\njne 120a \nmovslq %edi,%rdi\nmov (%r8,%rdi,4),%eax\nmov -0x8(%rbp),%rdi\nxor %fs:0x28,%rdi\njne 1236 \nleaveq\nretq\ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea eax, [rdi+1]\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11A4:\ncmp rsp, rdx\njz short loc_11BB\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11A4\nloc_11BB:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11D1\nor [rsp+rax+10h+var_18], 0\nloc_11D1:\nlea r8, [rsp+10h+var_D]\nmov rax, r8\nshr rax, 2\nand r8, 0FFFFFFFFFFFFFFFCh\nmov ds:dword_0[rax*4], 2\nmov dword ptr ds:byte_4[rax*4], 1\ncmp edi, 1\njle short loc_121A\nmov rax, r8\nlea edx, [rdi-1]\nlea rsi, [r8+rdx*4]\nloc_1206:\nmov ecx, [rax]\nmov edx, [rax+4]\nlea edx, [rdx+rcx*2]\nmov [rax+8], edx\nadd rax, 4\ncmp rax, rsi\njnz short loc_1206\nloc_121A:\nmovsxd rdi, edi\nmov eax, [r8+rdi*4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_1232\nleave\nretn\nloc_1232:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n signed __int64 v1; // rax\n void *v2; // rsp\n unsigned __int64 v3; // rax\n _BYTE *v4; // rax\n _BYTE v7[3]; // [rsp+8h] [rbp-10h] BYREF\n char v8; // [rsp+Bh] [rbp-Dh] BYREF\n unsigned __int64 v9; // [rsp+10h] [rbp-8h]\n\n v9 = __readfsqword(0x28u);\n while ( v7 != &v7[-((4LL * (a1 + 1) + 15) & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v1 = (4 * ((_WORD)a1 + 1) + 15) & 0xFF0;\n v2 = alloca(v1);\n if ( ((4 * ((_WORD)a1 + 1) + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v7[v1 - 8] = *(_QWORD *)&v7[v1 - 8];\n v3 = (unsigned __int64)&v8 >> 2;\n *(_DWORD *)(4 * v3) = 2;\n *(_DWORD *)&byte_4[4 * v3] = 1;\n if ( a1 > 1 )\n {\n v4 = v7;\n do\n {\n *((_DWORD *)v4 + 2) = *((_DWORD *)v4 + 1) + 2 * *(_DWORD *)v4;\n v4 += 4;\n }\n while ( v4 != &v7[4 * (a1 - 1)] );\n }\n return *(unsigned int *)&v7[4 * a1];\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea eax, [rdi+1]\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11A4:\ncmp rsp, rdx\njz short loc_11BB\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11A4\nloc_11BB:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11D1\nor [rsp+rax+10h+var_18], 0\nloc_11D1:\nlea r8, [rsp+10h+var_D]\nmov rax, r8\nshr rax, 2\nand r8, 0FFFFFFFFFFFFFFFCh\nmov ds:dword_0[rax*4], 2\nmov dword ptr ds:byte_4[rax*4], 1\ncmp edi, 1\njle short loc_121A\nmov rax, r8\nlea edx, [rdi-1]\nlea rsi, [r8+rdx*4]\nloc_1206:\nmov ecx, [rax]\nmov edx, [rax+4]\nlea edx, [rdx+rcx*2]\nmov [rax+8], edx\nadd rax, 4\ncmp rax, rsi\njnz short loc_1206\nloc_121A:\nmovsxd rdi, edi\nmov eax, [r8+rdi*4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_1232\nleave\nretn\nloc_1232:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n signed __int64 v1; // rax\n void *v2; // rsp\n unsigned __int64 v3; // rax\n _BYTE *v4; // rax\n _BYTE v7[3]; // [rsp+8h] [rbp-10h] BYREF\n char v8; // [rsp+Bh] [rbp-Dh] BYREF\n unsigned __int64 v9; // [rsp+10h] [rbp-8h]\n\n v9 = __readfsqword(0x28u);\n while ( v7 != &v7[-((4LL * (a1 + 1) + 15) & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v1 = (4 * ((_WORD)a1 + 1) + 15) & 0xFF0;\n v2 = alloca(v1);\n if ( ((4 * ((_WORD)a1 + 1) + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v7[v1 - 8] = *(_QWORD *)&v7[v1 - 8];\n v3 = (unsigned __int64)&v8 >> 2;\n *(_DWORD *)(4 * v3) = 2;\n *(_DWORD *)&byte_4[4 * v3] = 1;\n if ( a1 > 1 )\n {\n v4 = v7;\n do\n {\n *((_DWORD *)v4 + 2) = *((_DWORD *)v4 + 1) + 2 * *(_DWORD *)v4;\n v4 += 4;\n }\n while ( v4 != &v7[4 * (a1 - 1)] );\n }\n return *(unsigned int *)&v7[4 * a1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n signed long long v1;\n void *v2;\n unsigned long long v3;\n uint8_t *v4;\n uint8_t v7[3];\n char v8;\n unsigned long long v9;\n v9 = __readfsqword(40u);\n while (v7 != &v7[-((4LL * (a1 + 1) + 15) & 18446744073709547520LL)])\n ;\n v1 = (4 * ((unsigned short)a1 + 1) + 15) & 4080;\n v2 = alloca(v1);\n if (((4 * ((unsigned short)a1 + 1) + 15) & 4080) != 0)\n *(uint64_t *)&v7[v1 - 8] = *(uint64_t *)&v7[v1 - 8];\n v3 = (unsigned long long)&v8 >> 2;\n *(uint32_t *)(4 * v3) = 2;\n *(uint32_t *)&byte_4[4 * v3] = 1;\n if (a1 > 1) {\n v4 = v7;\n do {\n *((uint32_t *)v4 + 2) = *((uint32_t *)v4 + 1) + 2 * *(uint32_t *)v4;\n v4 += 4;\n } while (v4 != &v7[4 * (a1 - 1)]);\n }\n return *(unsigned int *)&v7[4 * a1];\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n signed long long v1;\n void *v2;\n unsigned long long v3;\n uint8_t *v4;\n uint8_t v7[3];\n char v8;\n unsigned long long v9;\n v9 = __readfsqword(40u);\n while (v7 != &v7[-((4LL * (a1 + 1) + 15) & 18446744073709547520LL)])\n ;\n v1 = (4 * ((unsigned short)a1 + 1) + 15) & 4080;\n v2 = alloca(v1);\n if (((4 * ((unsigned short)a1 + 1) + 15) & 4080) != 0)\n *(uint64_t *)&v7[v1 - 8] = *(uint64_t *)&v7[v1 - 8];\n v3 = (unsigned long long)&v8 >> 2;\n *(uint32_t *)(4 * v3) = 2;\n *(uint32_t *)&byte_4[4 * v3] = 1;\n if (a1 > 1) {\n v4 = v7;\n do {\n *((uint32_t *)v4 + 2) = *((uint32_t *)v4 + 1) + 2 * *(uint32_t *)v4;\n v4 += 4;\n } while (v4 != &v7[4 * (a1 - 1)]);\n }\n return *(unsigned int *)&v7[4 * a1];\n}" + }, + { + "index": 529, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int dp[n + 1];\n dp[0] = 2;\n dp[1] = 1;\n for (int i = 2; i <= n; i++) {\n dp[i] = dp[i - 1] + 2 * dp[i - 2];\n }\n return dp[n];\n}", + "test": "int main() {\n\n assert(func0(5) == 31);\n\n assert(func0(2) == 5);\n\n assert(func0(4) == 17);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0x1(%rdi),%eax\nmov %rsp,%rsi\ncltq\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rsi\nand $0xfffffffffffffff0,%rdx\nmov %rsi,%rax\ncmp %rax,%rsp\nje 1268 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 1253 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 12e8 \nmovabs $0x100000002,%rsi\nlea 0x3(%rsp),%r8\nmov %r8,%rax\nand $0xfffffffffffffffc,%r8\nshr $0x2,%rax\nmov %rsi,0x0(,%rax,4)\ncmp $0x1,%edi\njle 12c9 \nlea -0x2(%rdi),%edx\nlea 0x8(%r8),%rax\nmov $0x2,%ecx\nlea 0x8(%r8,%rdx,4),%rsi\nmov $0x1,%edx\njmp 12bf \nnopl (%rax)\nmov -0x4(%rax),%ecx\nadd $0x4,%rax\nlea (%rdx,%rcx,2),%edx\nmov %edx,(%rax)\ncmp %rsi,%rax\njne 12b8 \nmovslq %edi,%rdi\nmov (%r8,%rdi,4),%eax\nmov -0x8(%rbp),%rdi\nxor %fs:0x28,%rdi\njne 12f0 \nleaveq\nretq\nnopl 0x0(%rax)\norq $0x0,-0x8(%rsp,%rdx,1)\njmp 1276 \ncallq 1060 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmovsxd r8, edi\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea eax, [r8+1]\nmov rcx, rsp\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_1269\nloc_1254:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rcx\njnz short loc_1254\nloc_1269:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz short loc_12E0\nloc_1277:\nlea r9, [rsp+1010h+var_100D]\nmov rdx, cs:qword_2058\nmov rax, r9\nand r9, 0FFFFFFFFFFFFFFFCh\nshr rax, 2\nmov qword ptr ds:dword_0[rax*4], rdx\ncmp r8d, 1\njle short loc_12CB\nlea eax, [r8-2]\nlea rdx, [r9+8]\nmov ecx, 2\nlea rdi, [r9+rax*4+0Ch]\nmov eax, 1\nnop dword ptr [rax+rax+00h]\nloc_12B8:\nlea esi, [rcx+rcx]\nmov ecx, eax\nadd rdx, 4\nadd eax, esi\nmov [rdx-4], eax\ncmp rdi, rdx\njnz short loc_12B8\nloc_12CB:\nmov eax, [r9+r8*4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_12E8\nleave\nretn\nloc_12E0:\nor [rsp+rdx+1010h+var_1018], 0\njmp short loc_1277\nloc_12E8:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n __int64 v1; // rdx\n __int64 *v2; // rcx\n __int16 v3; // dx\n signed __int64 v4; // rdx\n void *v5; // rsp\n _BYTE *v6; // rdx\n int v7; // ecx\n int v8; // eax\n int v9; // esi\n __int64 v11; // [rsp+0h] [rbp-1018h]\n __int64 v12; // [rsp+8h] [rbp-1010h] BYREF\n _BYTE v13[4080]; // [rsp+10h] [rbp-1008h] BYREF\n _QWORD v14[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v14[1] = __readfsqword(0x28u);\n v1 = 4LL * (a1 + 1) + 15;\n v2 = (_QWORD *)((char *)v14 - (v1 & 0xFFFFFFFFFFFFF000LL));\n v3 = v1 & 0xFFF0;\n if ( v14 != v2 )\n {\n while ( &v12 != v2 )\n ;\n }\n v4 = v3 & 0xFFF;\n v5 = alloca(v4);\n if ( v4 )\n *(__int64 *)((char *)&v11 + v4) = *(__int64 *)((char *)&v11 + v4);\n v12 = 0x100000002LL;\n if ( a1 > 1 )\n {\n v6 = v13;\n v7 = 2;\n v8 = 1;\n do\n {\n v9 = 2 * v7;\n v7 = v8;\n v6 += 4;\n v8 += v9;\n *((_DWORD *)v6 - 1) = v8;\n }\n while ( &v13[4 * (a1 - 2) + 4] != v6 );\n }\n return *(unsigned int *)&v13[4 * a1 - 8];\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbp\nmovsxd r8, edi\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea eax, [r8+1]\nmov rcx, rsp\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_1269\nloc_1254:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rcx\njnz short loc_1254\nloc_1269:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz short loc_12E0\nloc_1277:\nlea r9, [rsp+1010h+var_100D]\nmov rdx, cs:qword_2058\nmov rax, r9\nand r9, 0FFFFFFFFFFFFFFFCh\nshr rax, 2\nmov qword ptr ds:dword_0[rax*4], rdx\ncmp r8d, 1\njle short loc_12CB\nlea eax, [r8-2]\nlea rdx, [r9+8]\nmov ecx, 2\nlea rdi, [r9+rax*4+0Ch]\nmov eax, 1\nnop dword ptr [rax+rax+00h]\nloc_12B8:\nlea esi, [rcx+rcx]\nmov ecx, eax\nadd rdx, 4\nadd eax, esi\nmov [rdx-4], eax\ncmp rdi, rdx\njnz short loc_12B8\nloc_12CB:\nmov eax, [r9+r8*4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_12E8\nleave\nretn\nloc_12E0:\nor [rsp+rdx+1010h+var_1018], 0\njmp short loc_1277\nloc_12E8:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(int a1)\n{\n __int64 v1; // rdx\n __int64 *v2; // rcx\n __int16 v3; // dx\n signed __int64 v4; // rdx\n void *v5; // rsp\n _BYTE *v6; // rdx\n int v7; // ecx\n int v8; // eax\n int v9; // esi\n __int64 v11; // [rsp+0h] [rbp-1018h]\n __int64 v12; // [rsp+8h] [rbp-1010h] BYREF\n _BYTE v13[4080]; // [rsp+10h] [rbp-1008h] BYREF\n _QWORD v14[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v14[1] = __readfsqword(0x28u);\n v1 = 4LL * (a1 + 1) + 15;\n v2 = (_QWORD *)((char *)v14 - (v1 & 0xFFFFFFFFFFFFF000LL));\n v3 = v1 & 0xFFF0;\n if ( v14 != v2 )\n {\n while ( &v12 != v2 )\n ;\n }\n v4 = v3 & 0xFFF;\n v5 = alloca(v4);\n if ( v4 )\n *(__int64 *)((char *)&v11 + v4) = *(__int64 *)((char *)&v11 + v4);\n v12 = 0x100000002LL;\n if ( a1 > 1 )\n {\n v6 = v13;\n v7 = 2;\n v8 = 1;\n do\n {\n v9 = 2 * v7;\n v7 = v8;\n v6 += 4;\n v8 += v9;\n *((_DWORD *)v6 - 1) = v8;\n }\n while ( &v13[4 * (a1 - 2) + 4] != v6 );\n }\n return *(unsigned int *)&v13[4 * a1 - 8];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(int a1) {\n long long v1;\n long long *v2;\n short v3;\n signed long long v4;\n void *v5;\n uint8_t *v6;\n int v7;\n int v8;\n int v9;\n long long v11;\n long long v12;\n uint8_t v13[4080];\n uint64_t v14[2];\n v14[1] = __readfsqword(40u);\n v1 = 4LL * (a1 + 1) + 15;\n v2 = (uint64_t *)((char *)v14 - (v1 & 18446744073709547520LL));\n v3 = v1 & 65520;\n if (v14 != v2) {\n while (&v12 != v2)\n ;\n }\n v4 = v3 & 4095;\n v5 = alloca(v4);\n if (v4) *(long long *)((char *)&v11 + v4) = *(long long *)((char *)&v11 + v4);\n v12 = 4294967298LL;\n if (a1 > 1) {\n v6 = v13;\n v7 = 2;\n v8 = 1;\n do {\n v9 = 2 * v7;\n v7 = v8;\n v6 += 4;\n v8 += v9;\n *((uint32_t *)v6 - 1) = v8;\n } while (&v13[4 * (a1 - 2) + 4] != v6);\n }\n return *(unsigned int *)&v13[4 * a1 - 8];\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n long long v1;\n long long *v2;\n short v3;\n signed long long v4;\n void *v5;\n uint8_t *v6;\n int v7;\n int v8;\n int v9;\n long long v11;\n long long v12;\n uint8_t v13[4080];\n uint64_t v14[2];\n v14[1] = __readfsqword(40u);\n v1 = 4LL * (a1 + 1) + 15;\n v2 = (uint64_t *)((char *)v14 - (v1 & 18446744073709547520LL));\n v3 = v1 & 65520;\n if (v14 != v2) {\n while (&v12 != v2)\n ;\n }\n v4 = v3 & 4095;\n v5 = alloca(v4);\n if (v4) *(long long *)((char *)&v11 + v4) = *(long long *)((char *)&v11 + v4);\n v12 = 4294967298LL;\n if (a1 > 1) {\n v6 = v13;\n v7 = 2;\n v8 = 1;\n do {\n v9 = 2 * v7;\n v7 = v8;\n v6 += 4;\n v8 += v9;\n *((uint32_t *)v6 - 1) = v8;\n } while (&v13[4 * (a1 - 2) + 4] != v6);\n }\n return *(unsigned int *)&v13[4 * a1 - 8];\n}" + }, + { + "index": 529, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int dp[n + 1];\n dp[0] = 2;\n dp[1] = 1;\n for (int i = 2; i <= n; i++) {\n dp[i] = dp[i - 1] + 2 * dp[i - 2];\n }\n return dp[n];\n}", + "test": "int main() {\n\n assert(func0(5) == 31);\n\n assert(func0(2) == 5);\n\n assert(func0(4) == 17);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0x1(%rdi),%eax\nmov %rsp,%rsi\ncltq\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rsi\nand $0xfffffffffffffff0,%rdx\nmov %rsi,%rax\ncmp %rax,%rsp\nje 11e8 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 11d3 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 1298 \nmovabs $0x100000002,%rsi\nlea 0x3(%rsp),%rdx\nmov %rdx,%rax\nand $0xfffffffffffffffc,%rdx\nshr $0x2,%rax\nmov %rsi,0x0(,%rax,4)\ncmp $0x1,%edi\njle 127e \ncmp $0x3,%edi\njle 12a3 \nmov 0x0(,%rax,4),%r8d\nmov 0x4(,%rax,4),%esi\nlea -0x4(%rdi),%eax\nmov $0x4,%ecx\nshr %eax\nlea 0x6(%rax,%rax,1),%r9\nlea (%rsi,%r8,2),%r8d\nmovslq %ecx,%rax\nlea (%r8,%rsi,2),%esi\nmov %r8d,-0x8(%rdx,%rcx,4)\nmov %esi,-0x4(%rdx,%rcx,4)\nadd $0x2,%rcx\ncmp %rcx,%r9\njne 1244 \nnopl 0x0(%rax)\nmov -0x8(%rdx,%rax,4),%esi\nmov -0x4(%rdx,%rax,4),%ecx\nlea (%rcx,%rsi,2),%ecx\nmov %ecx,(%rdx,%rax,4)\nadd $0x1,%rax\ncmp %eax,%edi\njge 1268 \nmovslq %edi,%rdi\nmov (%rdx,%rdi,4),%eax\nmov -0x8(%rbp),%rdi\nxor %fs:0x28,%rdi\njne 12aa \nleaveq\nretq\nnopl (%rax)\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 11fa \nmov $0x2,%eax\njmp 1268 \ncallq 1050 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmovsxd rcx, edi\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea eax, [rcx+1]\nmov rsi, rsp\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rsi, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rsi\njz short loc_11B8\nloc_11A3:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rsi\njnz short loc_11A3\nloc_11B8:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1260\nloc_11CA:\nlea rdx, [rsp+1010h+var_100D]\nmov rsi, cs:qword_2008\nmov rax, rdx\nand rdx, 0FFFFFFFFFFFFFFFCh\nshr rax, 2\nmov qword ptr ds:dword_0[rax*4], rsi\ncmp ecx, 1\njle short loc_1246\ncmp ecx, 3\njle short loc_126B\nlea eax, [rcx-4]\nmov esi, 4\nmov r8d, 1\nmov edi, 2\nshr eax, 1\nlea r9d, [rax+3]\nadd r9, r9\nloc_120F:\nlea edi, [r8+rdi*2]\nmov rax, rsi\nlea r8d, [rdi+r8*2]\nmov [rdx+rsi*4-8], edi\nmov [rdx+rsi*4-4], r8d\nadd rsi, 2\ncmp r9, rsi\njnz short loc_120F\nloc_122C:\ncdqe\nxchg ax, ax\nloc_1230:\nmov edi, [rdx+rax*4-8]\nmov esi, [rdx+rax*4-4]\nlea esi, [rsi+rdi*2]\nmov [rdx+rax*4], esi\nadd rax, 1\ncmp ecx, eax\njge short loc_1230\nloc_1246:\nmov eax, [rdx+rcx*4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_1272\nleave\nretn\nloc_1260:\nor [rsp+rdx+1010h+var_1018], 0\njmp loc_11CA\nloc_126B:\nmov eax, 2\njmp short loc_122C\nloc_1272:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n __int64 v1; // rcx\n __int64 v2; // rdx\n _QWORD *v3; // rsi\n __int16 v4; // dx\n signed __int64 v5; // rdx\n void *v6; // rsp\n __int64 v7; // rsi\n int v8; // r8d\n int v9; // edi\n __int64 v10; // rax\n _QWORD v13[511]; // [rsp+8h] [rbp-1010h] BYREF\n _QWORD v14[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v1 = a1;\n v14[1] = __readfsqword(0x28u);\n v2 = 4LL * (a1 + 1) + 15;\n v3 = (_QWORD *)((char *)v14 - (v2 & 0xFFFFFFFFFFFFF000LL));\n v4 = v2 & 0xFFF0;\n if ( v14 != v3 )\n {\n while ( v13 != v3 )\n ;\n }\n v5 = v4 & 0xFFF;\n v6 = alloca(v5);\n if ( v5 )\n *(_QWORD *)((char *)&v13[-1] + v5) = *(_QWORD *)((char *)&v13[-1] + v5);\n v13[0] = 0x100000002LL;\n if ( a1 > 1 )\n {\n if ( a1 <= 3 )\n {\n LODWORD(v10) = 2;\n }\n else\n {\n v7 = 2LL;\n v8 = 1;\n v9 = 2;\n do\n {\n v9 = v8 + 2 * v9;\n LODWORD(v10) = v7 * 2;\n v8 = v9 + 2 * v8;\n LODWORD(v13[v7 - 1]) = v9;\n HIDWORD(v13[v7++ - 1]) = v8;\n }\n while ( ((unsigned int)(v1 - 4) >> 1) + 3 != v7 );\n }\n v10 = (int)v10;\n do\n {\n *((_DWORD *)v13 + v10) = *((_DWORD *)v13 + v10 - 1) + 2 * *((_DWORD *)&v13[-1] + v10);\n ++v10;\n }\n while ( (int)v1 >= (int)v10 );\n }\n return *((unsigned int *)v13 + v1);\n}", + "ida_strip_asm": "sub_1160:\nendbr64\npush rbp\nmovsxd rcx, edi\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea eax, [rcx+1]\nmov rsi, rsp\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rsi, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rsi\njz short loc_11B8\nloc_11A3:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rsi\njnz short loc_11A3\nloc_11B8:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1260\nloc_11CA:\nlea rdx, [rsp+1010h+var_100D]\nmov rsi, cs:qword_2008\nmov rax, rdx\nand rdx, 0FFFFFFFFFFFFFFFCh\nshr rax, 2\nmov qword ptr ds:dword_0[rax*4], rsi\ncmp ecx, 1\njle short loc_1246\ncmp ecx, 3\njle short loc_126B\nlea eax, [rcx-4]\nmov esi, 4\nmov r8d, 1\nmov edi, 2\nshr eax, 1\nlea r9d, [rax+3]\nadd r9, r9\nloc_120F:\nlea edi, [r8+rdi*2]\nmov rax, rsi\nlea r8d, [rdi+r8*2]\nmov [rdx+rsi*4-8], edi\nmov [rdx+rsi*4-4], r8d\nadd rsi, 2\ncmp r9, rsi\njnz short loc_120F\nloc_122C:\ncdqe\nxchg ax, ax\nloc_1230:\nmov edi, [rdx+rax*4-8]\nmov esi, [rdx+rax*4-4]\nlea esi, [rsi+rdi*2]\nmov [rdx+rax*4], esi\nadd rax, 1\ncmp ecx, eax\njge short loc_1230\nloc_1246:\nmov eax, [rdx+rcx*4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_1272\nleave\nretn\nloc_1260:\nor [rsp+rdx+1010h+var_1018], 0\njmp loc_11CA\nloc_126B:\nmov eax, 2\njmp short loc_122C\nloc_1272:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1160(int a1)\n{\n __int64 v1; // rcx\n __int64 v2; // rdx\n _QWORD *v3; // rsi\n __int16 v4; // dx\n signed __int64 v5; // rdx\n void *v6; // rsp\n __int64 v7; // rsi\n int v8; // r8d\n int v9; // edi\n __int64 v10; // rax\n _QWORD v13[511]; // [rsp+8h] [rbp-1010h] BYREF\n _QWORD v14[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v1 = a1;\n v14[1] = __readfsqword(0x28u);\n v2 = 4LL * (a1 + 1) + 15;\n v3 = (_QWORD *)((char *)v14 - (v2 & 0xFFFFFFFFFFFFF000LL));\n v4 = v2 & 0xFFF0;\n if ( v14 != v3 )\n {\n while ( v13 != v3 )\n ;\n }\n v5 = v4 & 0xFFF;\n v6 = alloca(v5);\n if ( v5 )\n *(_QWORD *)((char *)&v13[-1] + v5) = *(_QWORD *)((char *)&v13[-1] + v5);\n v13[0] = 0x100000002LL;\n if ( a1 > 1 )\n {\n if ( a1 <= 3 )\n {\n LODWORD(v10) = 2;\n }\n else\n {\n v7 = 2LL;\n v8 = 1;\n v9 = 2;\n do\n {\n v9 = v8 + 2 * v9;\n LODWORD(v10) = v7 * 2;\n v8 = v9 + 2 * v8;\n LODWORD(v13[v7 - 1]) = v9;\n HIDWORD(v13[v7++ - 1]) = v8;\n }\n while ( ((unsigned int)(v1 - 4) >> 1) + 3 != v7 );\n }\n v10 = (int)v10;\n do\n {\n *((_DWORD *)v13 + v10) = *((_DWORD *)v13 + v10 - 1) + 2 * *((_DWORD *)&v13[-1] + v10);\n ++v10;\n }\n while ( (int)v1 >= (int)v10 );\n }\n return *((unsigned int *)v13 + v1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1160(int a1) {\n long long v1;\n long long v2;\n uint64_t *v3;\n short v4;\n signed long long v5;\n void *v6;\n long long v7;\n int v8;\n int v9;\n long long v10;\n uint64_t v13[511];\n uint64_t v14[2];\n v1 = a1;\n v14[1] = __readfsqword(40u);\n v2 = 4LL * (a1 + 1) + 15;\n v3 = (uint64_t *)((char *)v14 - (v2 & 18446744073709547520LL));\n v4 = v2 & 65520;\n if (v14 != v3) {\n while (v13 != v3)\n ;\n }\n v5 = v4 & 4095;\n v6 = alloca(v5);\n if (v5)\n *(uint64_t *)((char *)&v13[-1] + v5) = *(uint64_t *)((char *)&v13[-1] + v5);\n v13[0] = 4294967298LL;\n if (a1 > 1) {\n if (a1 <= 3) {\n LODWORD(v10) = 2;\n } else {\n v7 = 2LL;\n v8 = 1;\n v9 = 2;\n do {\n v9 = v8 + 2 * v9;\n LODWORD(v10) = v7 * 2;\n v8 = v9 + 2 * v8;\n LODWORD(v13[v7 - 1]) = v9;\n HIDWORD(v13[v7++ - 1]) = v8;\n } while (((unsigned int)(v1 - 4) >> 1) + 3 != v7);\n }\n v10 = (int)v10;\n do {\n *((uint32_t *)v13 + v10) =\n *((uint32_t *)v13 + v10 - 1) + 2 * *((uint32_t *)&v13[-1] + v10);\n ++v10;\n } while ((int)v1 >= (int)v10);\n }\n return *((unsigned int *)v13 + v1);\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n long long v1;\n long long v2;\n uint64_t *v3;\n short v4;\n signed long long v5;\n void *v6;\n long long v7;\n int v8;\n int v9;\n long long v10;\n uint64_t v13[511];\n uint64_t v14[2];\n v1 = a1;\n v14[1] = __readfsqword(40u);\n v2 = 4LL * (a1 + 1) + 15;\n v3 = (uint64_t *)((char *)v14 - (v2 & 18446744073709547520LL));\n v4 = v2 & 65520;\n if (v14 != v3) {\n while (v13 != v3)\n ;\n }\n v5 = v4 & 4095;\n v6 = alloca(v5);\n if (v5)\n *(uint64_t *)((char *)&v13[-1] + v5) = *(uint64_t *)((char *)&v13[-1] + v5);\n v13[0] = 4294967298LL;\n if (a1 > 1) {\n if (a1 <= 3) {\n LODWORD(v10) = 2;\n } else {\n v7 = 2LL;\n v8 = 1;\n v9 = 2;\n do {\n v9 = v8 + 2 * v9;\n LODWORD(v10) = v7 * 2;\n v8 = v9 + 2 * v8;\n LODWORD(v13[v7 - 1]) = v9;\n HIDWORD(v13[v7++ - 1]) = v8;\n } while (((unsigned int)(v1 - 4) >> 1) + 3 != v7);\n }\n v10 = (int)v10;\n do {\n *((uint32_t *)v13 + v10) =\n *((uint32_t *)v13 + v10 - 1) + 2 * *((uint32_t *)&v13[-1] + v10);\n ++v10;\n } while ((int)v1 >= (int)v10);\n }\n return *((unsigned int *)v13 + v1);\n}" + }, + { + "index": 530, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int nums[], int n) {\n int n1 = 0;\n for (int i = 0; i < n; i++) {\n if (nums[i] < 0) n1++;\n }\n double result = ((double)n1) / n;\n return round(result * 100) / 100;\n}", + "test": "int main() {\n\n int arr1[] = {0, 1, 2, -1, -5, 6, 0, -3, -2, 3, 4, 6, 8};\n\n assert(func0(arr1, 13) == 0.31);\n\n \n\n int arr2[] = {2, 1, 2, -1, -5, 6, 4, -3, -2, 3, 4, 6, 8};\n\n assert(func0(arr2, 13) == 0.31);\n\n \n\n int arr3[] = {2, 4, -6, -9, 11, -12, 14, -5, 17};\n\n assert(func0(arr3, 9) == 0.44);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 11ce \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ntest %eax,%eax\njns 11ca \naddl $0x1,-0x10(%rbp)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11ac \ncvtsi2sdl -0x10(%rbp),%xmm0\ncvtsi2sdl -0x1c(%rbp),%xmm1\ndivsd %xmm1,%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmovsd -0x8(%rbp),%xmm1\nmovsd 0xe9a(%rip),%xmm0\nmulsd %xmm1,%xmm0\ncallq 1070 \nmovsd 0xe89(%rip),%xmm1\ndivsd %xmm1,%xmm0\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp short loc_11CE\nloc_11AC:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njns short loc_11CA\nadd [rbp+var_10], 1\nloc_11CA:\nadd [rbp+var_C], 1\nloc_11CE:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_11AC\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_10]\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_1C]\ndivsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm1, [rbp+var_8]\nmovsd xmm0, cs:qword_2078\nmulsd xmm1, xmm0\nmovq rax, xmm1\nmovq xmm0, rax; x\ncall _round\nmovq rax, xmm0\nmovsd xmm0, cs:qword_2078\nmovq xmm1, rax\ndivsd xmm1, xmm0\nmovapd xmm0, xmm1\nleave\nretn", + "ida_pseudo": "__int128 __usercall func0@(__int64 a1@, int a2@)\n{\n double v2; // rax\n __int128 v3; // xmm1\n int v5; // [rsp+10h] [rbp-10h]\n int i; // [rsp+14h] [rbp-Ch]\n\n v5 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(int *)(4LL * i + a1) < 0 )\n ++v5;\n }\n v2 = round((double)v5 / (double)a2 * 100.0);\n v3 = *(unsigned __int64 *)&v2;\n *(double *)&v3 = v2 / 100.0;\n return v3;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp short loc_11CE\nloc_11AC:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njns short loc_11CA\nadd [rbp+var_10], 1\nloc_11CA:\nadd [rbp+var_C], 1\nloc_11CE:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_11AC\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_10]\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_1C]\ndivsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm1, [rbp+var_8]\nmovsd xmm0, cs:qword_2078\nmulsd xmm1, xmm0\nmovq rax, xmm1\nmovq xmm0, rax; x\ncall _round\nmovq rax, xmm0\nmovsd xmm0, cs:qword_2078\nmovq xmm1, rax\ndivsd xmm1, xmm0\nmovapd xmm0, xmm1\nleave\nretn", + "ida_strip_pseudo": "__int128 __usercall sub_1189@(__int64 a1@, int a2@)\n{\n double v2; // rax\n __int128 v3; // xmm1\n int v5; // [rsp+10h] [rbp-10h]\n int i; // [rsp+14h] [rbp-Ch]\n\n v5 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(int *)(4LL * i + a1) < 0 )\n ++v5;\n }\n v2 = round((double)v5 / (double)a2 * 100.0);\n v3 = *(unsigned __int64 *)&v2;\n *(double *)&v3 = v2 / 100.0;\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__int128 __usercall sub_1189 @(long long a1 @, int a2 @) {\n double v2;\n __int128 v3;\n int v5;\n int i;\n v5 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(int *)(4LL * i + a1) < 0) ++v5;\n }\n v2 = round((double)v5 / (double)a2 * 100.0);\n v3 = *(unsigned long long *)&v2;\n *(double *)&v3 = v2 / 100.0;\n return v3;\n}", + "ida_pseudo_norm": "__int128 __usercall func0 @(long long a1 @, int a2 @) {\n double v2;\n __int128 v3;\n int v5;\n int i;\n v5 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(int *)(4LL * i + a1) < 0) ++v5;\n }\n v2 = round((double)v5 / (double)a2 * 100.0);\n v3 = *(unsigned long long *)&v2;\n *(double *)&v3 = v2 / 100.0;\n return v3;\n}" + }, + { + "index": 530, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int nums[], int n) {\n int n1 = 0;\n for (int i = 0; i < n; i++) {\n if (nums[i] < 0) n1++;\n }\n double result = ((double)n1) / n;\n return round(result * 100) / 100;\n}", + "test": "int main() {\n\n int arr1[] = {0, 1, 2, -1, -5, 6, 0, -3, -2, 3, 4, 6, 8};\n\n assert(func0(arr1, 13) == 0.31);\n\n \n\n int arr2[] = {2, 1, 2, -1, -5, 6, 4, -3, -2, 3, 4, 6, 8};\n\n assert(func0(arr2, 13) == 0.31);\n\n \n\n int arr3[] = {2, 4, -6, -9, 11, -12, 14, -5, 17};\n\n assert(func0(arr3, 9) == 0.44);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x8,%rsp\ntest %esi,%esi\njle 11e5 \nmov %rdi,%rax\nlea -0x1(%rsi),%edx\nlea 0x4(%rdi,%rdx,4),%rcx\nmov $0x0,%edx\ncmpl $0x80000000,(%rax)\nsbb $0xffffffff,%edx\nadd $0x4,%rax\ncmp %rcx,%rax\njne 11a5 \npxor %xmm0,%xmm0\ncvtsi2sd %edx,%xmm0\npxor %xmm1,%xmm1\ncvtsi2sd %esi,%xmm1\ndivsd %xmm1,%xmm0\nmulsd 0xebd(%rip),%xmm0\ncallq 1070 \ndivsd 0xeb0(%rip),%xmm0\nadd $0x8,%rsp\nretq\nmov $0x0,%edx\njmp 11b7 \n", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\ntest esi, esi\njle short loc_11E4\nmov rax, rdi\nmovsxd rdx, esi\nlea rcx, [rdi+rdx*4]\nmov edx, 0\nloc_11A4:\ncmp dword ptr [rax], 80000000h\nsbb edx, 0FFFFFFFFh\nadd rax, 4\ncmp rax, rcx\njnz short loc_11A4\nloc_11B6:\npxor xmm0, xmm0\ncvtsi2sd xmm0, edx\npxor xmm1, xmm1\ncvtsi2sd xmm1, esi\ndivsd xmm0, xmm1\nmulsd xmm0, cs:qword_2078; x\ncall _round\ndivsd xmm0, cs:qword_2078\nadd rsp, 8\nretn\nloc_11E4:\nmov edx, 0\njmp short loc_11B6", + "ida_pseudo": "double __fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n int v3; // edx\n\n if ( a2 <= 0 )\n {\n v3 = 0;\n }\n else\n {\n v2 = a1;\n v3 = 0;\n do\n v3 -= (*v2++ < 0x80000000) - 1;\n while ( v2 != &a1[a2] );\n }\n return round((double)v3 / (double)a2 * 100.0) / 100.0;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\nsub rsp, 8\ntest esi, esi\njle short loc_11E4\nmov rax, rdi\nmovsxd rdx, esi\nlea rcx, [rdi+rdx*4]\nmov edx, 0\nloc_11A4:\ncmp dword ptr [rax], 80000000h\nsbb edx, 0FFFFFFFFh\nadd rax, 4\ncmp rax, rcx\njnz short loc_11A4\nloc_11B6:\npxor xmm0, xmm0\ncvtsi2sd xmm0, edx\npxor xmm1, xmm1\ncvtsi2sd xmm1, esi\ndivsd xmm0, xmm1\nmulsd xmm0, cs:qword_2078; x\ncall _round\ndivsd xmm0, cs:qword_2078\nadd rsp, 8\nretn\nloc_11E4:\nmov edx, 0\njmp short loc_11B6", + "ida_strip_pseudo": "double __fastcall sub_1189(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n int v3; // edx\n\n if ( a2 <= 0 )\n {\n v3 = 0;\n }\n else\n {\n v2 = a1;\n v3 = 0;\n do\n v3 -= (*v2++ < 0x80000000) - 1;\n while ( v2 != &a1[a2] );\n }\n return round((double)v3 / (double)a2 * 100.0) / 100.0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1189(uint32_t *a1, int a2) {\n uint32_t *v2;\n int v3;\n if (a2 <= 0) {\n v3 = 0;\n } else {\n v2 = a1;\n v3 = 0;\n do\n v3 -= (*v2++ < 2147483648) - 1;\n while (v2 != &a1[a2]);\n }\n return round((double)v3 / (double)a2 * 100.0) / 100.0;\n}", + "ida_pseudo_norm": "double func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n int v3;\n if (a2 <= 0) {\n v3 = 0;\n } else {\n v2 = a1;\n v3 = 0;\n do\n v3 -= (*v2++ < 2147483648) - 1;\n while (v2 != &a1[a2]);\n }\n return round((double)v3 / (double)a2 * 100.0) / 100.0;\n}" + }, + { + "index": 530, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int nums[], int n) {\n int n1 = 0;\n for (int i = 0; i < n; i++) {\n if (nums[i] < 0) n1++;\n }\n double result = ((double)n1) / n;\n return round(result * 100) / 100;\n}", + "test": "int main() {\n\n int arr1[] = {0, 1, 2, -1, -5, 6, 0, -3, -2, 3, 4, 6, 8};\n\n assert(func0(arr1, 13) == 0.31);\n\n \n\n int arr2[] = {2, 1, 2, -1, -5, 6, 4, -3, -2, 3, 4, 6, 8};\n\n assert(func0(arr2, 13) == 0.31);\n\n \n\n int arr3[] = {2, 4, -6, -9, 11, -12, 14, -5, 17};\n\n assert(func0(arr3, 9) == 0.44);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x8,%rsp\ntest %esi,%esi\njle 13f0 \nlea -0x1(%rsi),%eax\nlea 0x4(%rdi,%rax,4),%rdx\nxor %eax,%eax\nnopw %cs:0x0(%rax,%rax,1)\ncmpl $0x80000000,(%rdi)\nsbb $0xffffffff,%eax\nadd $0x4,%rdi\ncmp %rdi,%rdx\njne 13b0 \npxor %xmm0,%xmm0\ncvtsi2sd %eax,%xmm0\npxor %xmm1,%xmm1\ncvtsi2sd %esi,%xmm1\ndivsd %xmm1,%xmm0\nmulsd 0xcb2(%rip),%xmm0\ncallq 1070 \ndivsd 0xca5(%rip),%xmm0\nadd $0x8,%rsp\nretq\npxor %xmm0,%xmm0\njmp 13ca \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\ntest esi, esi\njle short loc_1380\nmovsxd rax, esi\nlea rdx, [rdi+rax*4]\nxor eax, eax\nnop dword ptr [rax]\nloc_1338:\ncmp dword ptr [rdi], 80000000h\nsbb eax, 0FFFFFFFFh\nadd rdi, 4\ncmp rdi, rdx\njnz short loc_1338\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nloc_1352:\npxor xmm1, xmm1\ncvtsi2sd xmm1, esi\ndivsd xmm0, xmm1\nmulsd xmm0, cs:qword_2078; x\ncall _round\ndivsd xmm0, cs:qword_2078\nadd rsp, 8\nretn\nloc_1380:\npxor xmm0, xmm0\njmp short loc_1352", + "ida_pseudo": "double __fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rdx\n int v3; // eax\n double v4; // xmm0_8\n\n if ( a2 <= 0 )\n {\n v4 = 0.0;\n }\n else\n {\n v2 = &a1[a2];\n v3 = 0;\n do\n v3 -= (*a1++ < 0x80000000) - 1;\n while ( a1 != v2 );\n v4 = (double)v3;\n }\n return round(v4 / (double)a2 * 100.0) / 100.0;\n}", + "ida_strip_asm": "sub_1320:\nendbr64\nsub rsp, 8\ntest esi, esi\njle short loc_1380\nmovsxd rax, esi\nlea rdx, [rdi+rax*4]\nxor eax, eax\nnop dword ptr [rax]\nloc_1338:\ncmp dword ptr [rdi], 80000000h\nsbb eax, 0FFFFFFFFh\nadd rdi, 4\ncmp rdi, rdx\njnz short loc_1338\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nloc_1352:\npxor xmm1, xmm1\ncvtsi2sd xmm1, esi\ndivsd xmm0, xmm1\nmulsd xmm0, cs:qword_2078; x\ncall _round\ndivsd xmm0, cs:qword_2078\nadd rsp, 8\nretn\nloc_1380:\npxor xmm0, xmm0\njmp short loc_1352", + "ida_strip_pseudo": "double __fastcall sub_1320(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rdx\n int v3; // eax\n double v4; // xmm0_8\n\n if ( a2 <= 0 )\n {\n v4 = 0.0;\n }\n else\n {\n v2 = &a1[a2];\n v3 = 0;\n do\n v3 -= (*a1++ < 0x80000000) - 1;\n while ( a1 != v2 );\n v4 = (double)v3;\n }\n return round(v4 / (double)a2 * 100.0) / 100.0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1320(uint32_t *a1, int a2) {\n uint32_t *v2;\n int v3;\n double v4;\n if (a2 <= 0) {\n v4 = 0.0;\n } else {\n v2 = &a1[a2];\n v3 = 0;\n do\n v3 -= (*a1++ < 2147483648) - 1;\n while (a1 != v2);\n v4 = (double)v3;\n }\n return round(v4 / (double)a2 * 100.0) / 100.0;\n}", + "ida_pseudo_norm": "double func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n int v3;\n double v4;\n if (a2 <= 0) {\n v4 = 0.0;\n } else {\n v2 = &a1[a2];\n v3 = 0;\n do\n v3 -= (*a1++ < 2147483648) - 1;\n while (a1 != v2);\n v4 = (double)v3;\n }\n return round(v4 / (double)a2 * 100.0) / 100.0;\n}" + }, + { + "index": 530, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int nums[], int n) {\n int n1 = 0;\n for (int i = 0; i < n; i++) {\n if (nums[i] < 0) n1++;\n }\n double result = ((double)n1) / n;\n return round(result * 100) / 100;\n}", + "test": "int main() {\n\n int arr1[] = {0, 1, 2, -1, -5, 6, 0, -3, -2, 3, 4, 6, 8};\n\n assert(func0(arr1, 13) == 0.31);\n\n \n\n int arr2[] = {2, 1, 2, -1, -5, 6, 4, -3, -2, 3, 4, 6, 8};\n\n assert(func0(arr2, 13) == 0.31);\n\n \n\n int arr3[] = {2, 4, -6, -9, 11, -12, 14, -5, 17};\n\n assert(func0(arr3, 9) == 0.44);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x8,%rsp\ntest %esi,%esi\njle 1410 \nlea -0x1(%rsi),%eax\ncmp $0x3,%eax\njbe 1416 \nmov %esi,%edx\nmov %rdi,%rax\npxor %xmm0,%xmm0\nshr $0x2,%edx\nshl $0x4,%rdx\nadd %rdi,%rdx\nmovdqu (%rax),%xmm1\nadd $0x10,%rax\npsrad $0x1f,%xmm1\npsubd %xmm1,%xmm0\ncmp %rdx,%rax\njne 1350 \nmovdqa %xmm0,%xmm1\nmov %esi,%edx\npsrldq $0x8,%xmm1\nand $0xfffffffc,%edx\npaddd %xmm1,%xmm0\nmovdqa %xmm0,%xmm1\npsrldq $0x4,%xmm1\npaddd %xmm1,%xmm0\nmovd %xmm0,%eax\ntest $0x3,%sil\nje 13d8 \nmovslq %edx,%rcx\ncmpl $0x80000000,(%rdi,%rcx,4)\nlea 0x1(%rdx),%ecx\nsbb $0xffffffff,%eax\ncmp %esi,%ecx\njge 13d8 \nmovslq %ecx,%rcx\ncmpl $0x80000000,(%rdi,%rcx,4)\nlea 0x2(%rdx),%ecx\nsbb $0xffffffff,%eax\ncmp %ecx,%esi\njle 13d8 \nmovslq %ecx,%rcx\ncmpl $0x80000000,(%rdi,%rcx,4)\nsbb $0xffffffff,%eax\nadd $0x3,%edx\ncmp %edx,%esi\njle 13d8 \nmovslq %edx,%rdx\ncmpl $0x80000000,(%rdi,%rdx,4)\nsbb $0xffffffff,%eax\npxor %xmm0,%xmm0\ncvtsi2sd %eax,%xmm0\npxor %xmm1,%xmm1\ncvtsi2sd %esi,%xmm1\ndivsd %xmm1,%xmm0\nmulsd 0xc9c(%rip),%xmm0\ncallq 1070 \ndivsd 0xc8f(%rip),%xmm0\nadd $0x8,%rsp\nretq\nnopw %cs:0x0(%rax,%rax,1)\npxor %xmm0,%xmm0\njmp 13e0 \nxor %edx,%edx\nxor %eax,%eax\njmpq 138f \n", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\ntest esi, esi\njle loc_1410\nlea eax, [rsi-1]\nmov rcx, rdi\ncmp eax, 2\njbe loc_1416\nmov edx, esi\npxor xmm0, xmm0\nmov rax, rdi\nshr edx, 2\nmovdqa xmm2, xmm0\nshl rdx, 4\nadd rdx, rdi\nnop word ptr [rax+rax+00000000h]\nloc_1360:\nmovdqu xmm3, xmmword ptr [rax]\nmovdqa xmm1, xmm2\nadd rax, 10h\npcmpgtd xmm1, xmm3\npsubd xmm0, xmm1\ncmp rax, rdx\njnz short loc_1360\nmovdqa xmm1, xmm0\nmov edx, esi\npsrldq xmm1, 8\nand edx, 0FFFFFFFCh\npaddd xmm0, xmm1\nmovdqa xmm1, xmm0\npsrldq xmm1, 4\npaddd xmm0, xmm1\nmovd eax, xmm0\ntest sil, 3\njz short loc_13DD\nloc_13A2:\nmovsxd rdi, edx\ncmp dword ptr [rcx+rdi*4], 80000000h\nlea r8, ds:0[rdi*4]\nlea edi, [rdx+1]\nsbb eax, 0FFFFFFFFh\ncmp esi, edi\njle short loc_13DD\ncmp dword ptr [rcx+r8+4], 80000000h\nsbb eax, 0FFFFFFFFh\nadd edx, 2\ncmp esi, edx\njle short loc_13DD\ncmp dword ptr [rcx+r8+8], 80000000h\nsbb eax, 0FFFFFFFFh\nloc_13DD:\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nloc_13E5:\npxor xmm1, xmm1\ncvtsi2sd xmm1, esi\ndivsd xmm0, xmm1\nmulsd xmm0, cs:qword_2078; x\ncall _round\ndivsd xmm0, cs:qword_2078\nadd rsp, 8\nretn\nloc_1410:\npxor xmm0, xmm0\njmp short loc_13E5\nloc_1416:\nxor edx, edx\nxor eax, eax\njmp short loc_13A2", + "ida_pseudo": "double __fastcall func0(const __m128i *a1, int a2)\n{\n __m128i v2; // xmm0\n const __m128i *v3; // rax\n __m128i v4; // xmm3\n int v5; // edx\n __m128i v6; // xmm0\n int v7; // eax\n __int64 v8; // r8\n double v9; // xmm0_8\n\n if ( a2 <= 0 )\n {\n v9 = 0.0;\n return round(v9 / (double)a2 * 100.0) / 100.0;\n }\n if ( (unsigned int)(a2 - 1) <= 2 )\n {\n v5 = 0;\n v7 = 0;\n goto LABEL_6;\n }\n v2 = 0LL;\n v3 = a1;\n do\n {\n v4 = _mm_loadu_si128(v3++);\n v2 = _mm_sub_epi32(v2, _mm_cmpgt_epi32((__m128i)0LL, v4));\n }\n while ( v3 != &a1[(unsigned int)a2 >> 2] );\n v5 = a2 & 0x7FFFFFFC;\n v6 = _mm_add_epi32(v2, _mm_srli_si128(v2, 8));\n v7 = _mm_cvtsi128_si32(_mm_add_epi32(v6, _mm_srli_si128(v6, 4)));\n if ( (a2 & 3) != 0 )\n {\nLABEL_6:\n v8 = v5;\n v7 -= (a1->m128i_i32[v8] < 0x80000000) - 1;\n if ( a2 > v5 + 1 )\n {\n v7 -= (a1->m128i_i32[v8 + 1] < 0x80000000) - 1;\n if ( a2 > v5 + 2 )\n v7 -= (a1->m128i_i32[v8 + 2] < 0x80000000) - 1;\n }\n }\n v9 = (double)v7;\n return round(v9 / (double)a2 * 100.0) / 100.0;\n}", + "ida_strip_asm": "sub_1320:\nendbr64\nsub rsp, 8\ntest esi, esi\njle loc_1410\nlea eax, [rsi-1]\nmov rcx, rdi\ncmp eax, 2\njbe loc_1416\nmov edx, esi\npxor xmm0, xmm0\nmov rax, rdi\nshr edx, 2\nmovdqa xmm2, xmm0\nshl rdx, 4\nadd rdx, rdi\nnop word ptr [rax+rax+00000000h]\nloc_1360:\nmovdqu xmm3, xmmword ptr [rax]\nmovdqa xmm1, xmm2\nadd rax, 10h\npcmpgtd xmm1, xmm3\npsubd xmm0, xmm1\ncmp rax, rdx\njnz short loc_1360\nmovdqa xmm1, xmm0\nmov edx, esi\npsrldq xmm1, 8\nand edx, 0FFFFFFFCh\npaddd xmm0, xmm1\nmovdqa xmm1, xmm0\npsrldq xmm1, 4\npaddd xmm0, xmm1\nmovd eax, xmm0\ntest sil, 3\njz short loc_13DD\nloc_13A2:\nmovsxd rdi, edx\ncmp dword ptr [rcx+rdi*4], 80000000h\nlea r8, ds:0[rdi*4]\nlea edi, [rdx+1]\nsbb eax, 0FFFFFFFFh\ncmp esi, edi\njle short loc_13DD\ncmp dword ptr [rcx+r8+4], 80000000h\nsbb eax, 0FFFFFFFFh\nadd edx, 2\ncmp esi, edx\njle short loc_13DD\ncmp dword ptr [rcx+r8+8], 80000000h\nsbb eax, 0FFFFFFFFh\nloc_13DD:\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nloc_13E5:\npxor xmm1, xmm1\ncvtsi2sd xmm1, esi\ndivsd xmm0, xmm1\nmulsd xmm0, cs:qword_2078; x\ncall _round\ndivsd xmm0, cs:qword_2078\nadd rsp, 8\nretn\nloc_1410:\npxor xmm0, xmm0\njmp short loc_13E5\nloc_1416:\nxor edx, edx\nxor eax, eax\njmp short loc_13A2", + "ida_strip_pseudo": "double __fastcall sub_1320(const __m128i *a1, int a2)\n{\n __m128i v2; // xmm0\n const __m128i *v3; // rax\n __m128i v4; // xmm3\n int v5; // edx\n __m128i v6; // xmm0\n int v7; // eax\n __int64 v8; // r8\n double v9; // xmm0_8\n\n if ( a2 <= 0 )\n {\n v9 = 0.0;\n return round(v9 / (double)a2 * 100.0) / 100.0;\n }\n if ( (unsigned int)(a2 - 1) <= 2 )\n {\n v5 = 0;\n v7 = 0;\n goto LABEL_6;\n }\n v2 = 0LL;\n v3 = a1;\n do\n {\n v4 = _mm_loadu_si128(v3++);\n v2 = _mm_sub_epi32(v2, _mm_cmpgt_epi32((__m128i)0LL, v4));\n }\n while ( v3 != &a1[(unsigned int)a2 >> 2] );\n v5 = a2 & 0x7FFFFFFC;\n v6 = _mm_add_epi32(v2, _mm_srli_si128(v2, 8));\n v7 = _mm_cvtsi128_si32(_mm_add_epi32(v6, _mm_srli_si128(v6, 4)));\n if ( (a2 & 3) != 0 )\n {\nLABEL_6:\n v8 = v5;\n v7 -= (a1->m128i_i32[v8] < 0x80000000) - 1;\n if ( a2 > v5 + 1 )\n {\n v7 -= (a1->m128i_i32[v8 + 1] < 0x80000000) - 1;\n if ( a2 > v5 + 2 )\n v7 -= (a1->m128i_i32[v8 + 2] < 0x80000000) - 1;\n }\n }\n v9 = (double)v7;\n return round(v9 / (double)a2 * 100.0) / 100.0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1320(const __m128i *a1, int a2) {\n __m128i v2;\n const __m128i *v3;\n __m128i v4;\n int v5;\n __m128i v6;\n int v7;\n long long v8;\n double v9;\n if (a2 <= 0) {\n v9 = 0.0;\n return round(v9 / (double)a2 * 100.0) / 100.0;\n }\n if ((unsigned int)(a2 - 1) <= 2) {\n v5 = 0;\n v7 = 0;\n goto LABEL_6;\n }\n v2 = 0LL;\n v3 = a1;\n do {\n v4 = _mm_loadu_si128(v3++);\n v2 = _mm_sub_epi32(v2, _mm_cmpgt_epi32((__m128i)0LL, v4));\n } while (v3 != &a1[(unsigned int)a2 >> 2]);\n v5 = a2 & 2147483644;\n v6 = _mm_add_epi32(v2, _mm_srli_si128(v2, 8));\n v7 = _mm_cvtsi128_si32(_mm_add_epi32(v6, _mm_srli_si128(v6, 4)));\n if ((a2 & 3) != 0) {\n LABEL_6:\n v8 = v5;\n v7 -= (a1->m128i_i32[v8] < 2147483648) - 1;\n if (a2 > v5 + 1) {\n v7 -= (a1->m128i_i32[v8 + 1] < 2147483648) - 1;\n if (a2 > v5 + 2) v7 -= (a1->m128i_i32[v8 + 2] < 2147483648) - 1;\n }\n }\n v9 = (double)v7;\n return round(v9 / (double)a2 * 100.0) / 100.0;\n}", + "ida_pseudo_norm": "double func0(const __m128i *a1, int a2) {\n __m128i v2;\n const __m128i *v3;\n __m128i v4;\n int v5;\n __m128i v6;\n int v7;\n long long v8;\n double v9;\n if (a2 <= 0) {\n v9 = 0.0;\n return round(v9 / (double)a2 * 100.0) / 100.0;\n }\n if ((unsigned int)(a2 - 1) <= 2) {\n v5 = 0;\n v7 = 0;\n goto LABEL_6;\n }\n v2 = 0LL;\n v3 = a1;\n do {\n v4 = _mm_loadu_si128(v3++);\n v2 = _mm_sub_epi32(v2, _mm_cmpgt_epi32((__m128i)0LL, v4));\n } while (v3 != &a1[(unsigned int)a2 >> 2]);\n v5 = a2 & 2147483644;\n v6 = _mm_add_epi32(v2, _mm_srli_si128(v2, 8));\n v7 = _mm_cvtsi128_si32(_mm_add_epi32(v6, _mm_srli_si128(v6, 4)));\n if ((a2 & 3) != 0) {\n LABEL_6:\n v8 = v5;\n v7 -= (a1->m128i_i32[v8] < 2147483648) - 1;\n if (a2 > v5 + 1) {\n v7 -= (a1->m128i_i32[v8 + 1] < 2147483648) - 1;\n if (a2 > v5 + 2) v7 -= (a1->m128i_i32[v8 + 2] < 2147483648) - 1;\n }\n }\n v9 = (double)v7;\n return round(v9 / (double)a2 * 100.0) / 100.0;\n}" + }, + { + "index": 531, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(int coins[], int m, int V) {\n if (V == 0) {\n return 0;\n }\n int res = INT_MAX;\n for (int i = 0; i < m; i++) {\n if (coins[i] <= V) {\n int sub_res = func0(coins, m, V - coins[i]);\n if (sub_res != INT_MAX && sub_res + 1 < res) {\n res = sub_res + 1;\n }\n }\n }\n return res;\n}", + "test": "int main() {\n\n assert(func0((int[]){9, 6, 5, 1}, 4, 11) == 2);\n\n assert(func0((int[]){4, 5, 6, 7, 8, 9}, 6, 9) == 1);\n\n assert(func0((int[]){1, 2, 3}, 3, 4) == 2);\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\ncmpl $0x0,-0x20(%rbp)\njne 118f \nmov $0x0,%eax\njmpq 1215 \nmovl $0x7fffffff,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 120a \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x20(%rbp)\njl 1206 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov -0x20(%rbp),%edx\nsub %eax,%edx\nmov -0x1c(%rbp),%ecx\nmov -0x18(%rbp),%rax\nmov %ecx,%esi\nmov %rax,%rdi\ncallq 1169 \nmov %eax,-0x4(%rbp)\ncmpl $0x7fffffff,-0x4(%rbp)\nje 1206 \nmov -0x4(%rbp),%eax\nadd $0x1,%eax\ncmp %eax,-0xc(%rbp)\njle 1206 \nmov -0x4(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0xc(%rbp)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 119f \nmov -0xc(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\ncmp [rbp+var_20], 0\njnz short loc_118F\nmov eax, 0\njmp locret_1215\nloc_118F:\nmov [rbp+var_C], 7FFFFFFFh\nmov [rbp+var_8], 0\njmp short loc_120A\nloc_119F:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njl short loc_1206\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_20]\nsub edx, eax\nmov ecx, [rbp+var_1C]\nmov rax, [rbp+var_18]\nmov esi, ecx\nmov rdi, rax\ncall func0\nmov [rbp+var_4], eax\ncmp [rbp+var_4], 7FFFFFFFh\njz short loc_1206\nmov eax, [rbp+var_4]\nadd eax, 1\ncmp [rbp+var_C], eax\njle short loc_1206\nmov eax, [rbp+var_4]\nadd eax, 1\nmov [rbp+var_C], eax\nloc_1206:\nadd [rbp+var_8], 1\nloc_120A:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_119F\nmov eax, [rbp+var_C]\nlocret_1215:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, unsigned int a2, int a3)\n{\n int v5; // [rsp+14h] [rbp-Ch]\n int i; // [rsp+18h] [rbp-8h]\n int v7; // [rsp+1Ch] [rbp-4h]\n\n if ( !a3 )\n return 0LL;\n v5 = 0x7FFFFFFF;\n for ( i = 0; i < (int)a2; ++i )\n {\n if ( a3 >= *(_DWORD *)(4LL * i + a1) )\n {\n v7 = func0(a1, a2, (unsigned int)(a3 - *(_DWORD *)(4LL * i + a1)));\n if ( v7 != 0x7FFFFFFF && v5 > v7 + 1 )\n v5 = v7 + 1;\n }\n }\n return (unsigned int)v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\ncmp [rbp+var_20], 0\njnz short loc_118F\nmov eax, 0\njmp locret_1215\nloc_118F:\nmov [rbp+var_C], 7FFFFFFFh\nmov [rbp+var_8], 0\njmp short loc_120A\nloc_119F:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njl short loc_1206\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_20]\nsub edx, eax\nmov ecx, [rbp+var_1C]\nmov rax, [rbp+var_18]\nmov esi, ecx\nmov rdi, rax\ncall sub_1169\nmov [rbp+var_4], eax\ncmp [rbp+var_4], 7FFFFFFFh\njz short loc_1206\nmov eax, [rbp+var_4]\nadd eax, 1\ncmp [rbp+var_C], eax\njle short loc_1206\nmov eax, [rbp+var_4]\nadd eax, 1\nmov [rbp+var_C], eax\nloc_1206:\nadd [rbp+var_8], 1\nloc_120A:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_119F\nmov eax, [rbp+var_C]\nlocret_1215:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, unsigned int a2, int a3)\n{\n int v5; // [rsp+14h] [rbp-Ch]\n int i; // [rsp+18h] [rbp-8h]\n int v7; // [rsp+1Ch] [rbp-4h]\n\n if ( !a3 )\n return 0LL;\n v5 = 0x7FFFFFFF;\n for ( i = 0; i < (int)a2; ++i )\n {\n if ( a3 >= *(_DWORD *)(4LL * i + a1) )\n {\n v7 = sub_1169(a1, a2, (unsigned int)(a3 - *(_DWORD *)(4LL * i + a1)));\n if ( v7 != 0x7FFFFFFF && v5 > v7 + 1 )\n v5 = v7 + 1;\n }\n }\n return (unsigned int)v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, unsigned int a2, int a3) {\n int v5;\n int i;\n int v7;\n if (!a3) return 0LL;\n v5 = 2147483647;\n for (i = 0; i < (int)a2; ++i) {\n if (a3 >= *(uint32_t *)(4LL * i + a1)) {\n v7 = sub_1169(a1, a2, (unsigned int)(a3 - *(uint32_t *)(4LL * i + a1)));\n if (v7 != 2147483647 && v5 > v7 + 1) v5 = v7 + 1;\n }\n }\n return (unsigned int)v5;\n}", + "ida_pseudo_norm": "long long func0(long long a1, unsigned int a2, int a3) {\n int v5;\n int i;\n int v7;\n if (!a3) return 0LL;\n v5 = 2147483647;\n for (i = 0; i < (int)a2; ++i) {\n if (a3 >= *(uint32_t *)(4LL * i + a1)) {\n v7 = func0(a1, a2, (unsigned int)(a3 - *(uint32_t *)(4LL * i + a1)));\n if (v7 != 2147483647 && v5 > v7 + 1) v5 = v7 + 1;\n }\n }\n return (unsigned int)v5;\n}" + }, + { + "index": 531, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(int coins[], int m, int V) {\n if (V == 0) {\n return 0;\n }\n int res = INT_MAX;\n for (int i = 0; i < m; i++) {\n if (coins[i] <= V) {\n int sub_res = func0(coins, m, V - coins[i]);\n if (sub_res != INT_MAX && sub_res + 1 < res) {\n res = sub_res + 1;\n }\n }\n }\n return res;\n}", + "test": "int main() {\n\n assert(func0((int[]){9, 6, 5, 1}, 4, 11) == 2);\n\n assert(func0((int[]){4, 5, 6, 7, 8, 9}, 6, 9) == 1);\n\n assert(func0((int[]){1, 2, 3}, 3, 4) == 2);\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %edx,%r14d\ntest %edx,%edx\nje 11d2 \nmov %rdi,%r13\nmov %esi,%r12d\nmov %edx,%ebp\nmov $0x7fffffff,%r14d\ntest %esi,%esi\njle 11d2 \nmov %rdi,%rbx\nlea -0x1(%rsi),%eax\nlea 0x4(%rdi,%rax,4),%r15\njmp 11b4 \nadd $0x1,%eax\ncmp %eax,%r14d\ncmovg %eax,%r14d\nadd $0x4,%rbx\ncmp %r15,%rbx\nje 11d2 \nmov (%rbx),%eax\ncmp %ebp,%eax\njg 11ab \nmov %ebp,%edx\nsub %eax,%edx\nmov %r12d,%esi\nmov %r13,%rdi\ncallq 1169 \ncmp $0x7fffffff,%eax\njne 11a1 \njmp 11ab \nmov %r14d,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12d, edx\ntest edx, edx\njz short loc_11D3\nmov r14, rdi\nmov r13d, esi\nmov ebp, edx\nmov r12d, 7FFFFFFFh\ntest esi, esi\njle short loc_11D3\nmov rbx, rdi\nmovsxd rax, esi\nlea r15, [rdi+rax*4]\njmp short loc_11A9\nloc_11A0:\nadd rbx, 4\ncmp rbx, r15\njz short loc_11D3\nloc_11A9:\nmov eax, [rbx]\ncmp eax, ebp\njg short loc_11A0\nmov edx, ebp\nsub edx, eax\nmov esi, r13d\nmov rdi, r14\ncall func0\nlea edx, [rax+1]\ncmp r12d, edx\ncmovle edx, r12d\ncmp eax, 7FFFFFFFh\ncmovnz r12d, edx\njmp short loc_11A0\nloc_11D3:\nmov eax, r12d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2, int a3)\n{\n int v3; // r12d\n int *v5; // rbx\n int v6; // eax\n int v7; // edx\n\n v3 = a3;\n if ( a3 )\n {\n v3 = 0x7FFFFFFF;\n if ( a2 > 0 )\n {\n v5 = a1;\n do\n {\n if ( *v5 <= a3 )\n {\n v6 = func0(a1, (unsigned int)a2, (unsigned int)(a3 - *v5));\n v7 = v6 + 1;\n if ( v3 <= v6 + 1 )\n v7 = v3;\n if ( v6 != 0x7FFFFFFF )\n v3 = v7;\n }\n ++v5;\n }\n while ( v5 != &a1[a2] );\n }\n }\n return (unsigned int)v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12d, edx\ntest edx, edx\njz short loc_11D3\nmov r14, rdi\nmov r13d, esi\nmov ebp, edx\nmov r12d, 7FFFFFFFh\ntest esi, esi\njle short loc_11D3\nmov rbx, rdi\nmovsxd rax, esi\nlea r15, [rdi+rax*4]\njmp short loc_11A9\nloc_11A0:\nadd rbx, 4\ncmp rbx, r15\njz short loc_11D3\nloc_11A9:\nmov eax, [rbx]\ncmp eax, ebp\njg short loc_11A0\nmov edx, ebp\nsub edx, eax\nmov esi, r13d\nmov rdi, r14\ncall sub_1169\nlea edx, [rax+1]\ncmp r12d, edx\ncmovle edx, r12d\ncmp eax, 7FFFFFFFh\ncmovnz r12d, edx\njmp short loc_11A0\nloc_11D3:\nmov eax, r12d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int *a1, int a2, int a3)\n{\n int v3; // r12d\n int *v5; // rbx\n int v6; // eax\n int v7; // edx\n\n v3 = a3;\n if ( a3 )\n {\n v3 = 0x7FFFFFFF;\n if ( a2 > 0 )\n {\n v5 = a1;\n do\n {\n if ( *v5 <= a3 )\n {\n v6 = sub_1169(a1, (unsigned int)a2, (unsigned int)(a3 - *v5));\n v7 = v6 + 1;\n if ( v3 <= v6 + 1 )\n v7 = v3;\n if ( v6 != 0x7FFFFFFF )\n v3 = v7;\n }\n ++v5;\n }\n while ( v5 != &a1[a2] );\n }\n }\n return (unsigned int)v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int *a1, int a2, int a3) {\n int v3;\n int *v5;\n int v6;\n int v7;\n v3 = a3;\n if (a3) {\n v3 = 2147483647;\n if (a2 > 0) {\n v5 = a1;\n do {\n if (*v5 <= a3) {\n v6 = sub_1169(a1, (unsigned int)a2, (unsigned int)(a3 - *v5));\n v7 = v6 + 1;\n if (v3 <= v6 + 1) v7 = v3;\n if (v6 != 2147483647) v3 = v7;\n }\n ++v5;\n } while (v5 != &a1[a2]);\n }\n }\n return (unsigned int)v3;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2, int a3) {\n int v3;\n int *v5;\n int v6;\n int v7;\n v3 = a3;\n if (a3) {\n v3 = 2147483647;\n if (a2 > 0) {\n v5 = a1;\n do {\n if (*v5 <= a3) {\n v6 = func0(a1, (unsigned int)a2, (unsigned int)(a3 - *v5));\n v7 = v6 + 1;\n if (v3 <= v6 + 1) v7 = v3;\n if (v6 != 2147483647) v3 = v7;\n }\n ++v5;\n } while (v5 != &a1[a2]);\n }\n }\n return (unsigned int)v3;\n}" + }, + { + "index": 531, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(int coins[], int m, int V) {\n if (V == 0) {\n return 0;\n }\n int res = INT_MAX;\n for (int i = 0; i < m; i++) {\n if (coins[i] <= V) {\n int sub_res = func0(coins, m, V - coins[i]);\n if (sub_res != INT_MAX && sub_res + 1 < res) {\n res = sub_res + 1;\n }\n }\n }\n return res;\n}", + "test": "int main() {\n\n assert(func0((int[]){9, 6, 5, 1}, 4, 11) == 2);\n\n assert(func0((int[]){4, 5, 6, 7, 8, 9}, 6, 9) == 1);\n\n assert(func0((int[]){1, 2, 3}, 3, 4) == 2);\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %edx,%edx\nje 12d0 \njmp 12e0 \nnopw 0x0(%rax,%rax,1)\nxor %eax,%eax\nretq\ndata16 nopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0_part_0:\npush r15\npush r14\nmov r14d, 7FFFFFFFh\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\ntest esi, esi\njle short loc_12C9\nmovsxd rax, esi\nmov r15, rdi\nmov r12d, esi\nmov ebp, edx\nmov rbx, rdi\nlea r13, [rdi+rax*4]\nloc_12BA:\nmov eax, [rbx]\ncmp eax, ebp\njle short loc_12E0\nloc_12C0:\nadd rbx, 4\ncmp rbx, r13\njnz short loc_12BA\nloc_12C9:\nadd rsp, 8\nmov eax, r14d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_12E0:\nmov edx, ebp\nsub edx, eax\njz short loc_1308\nmov esi, r12d\nmov rdi, r15\ncall func0_part_0\ncmp eax, 7FFFFFFFh\njz short loc_12C0\nadd eax, 1\nloc_12FB:\ncmp r14d, eax\ncmovg r14d, eax\njmp short loc_12C0\nloc_1308:\nmov eax, 1\njmp short loc_12FB", + "ida_pseudo": "__int64 __fastcall func0_part_0(int *a1, int a2, int a3)\n{\n int v3; // r14d\n int *i; // rbx\n int v6; // eax\n int v8; // eax\n int v9; // eax\n\n v3 = 0x7FFFFFFF;\n if ( a2 > 0 )\n {\n for ( i = a1; i != &a1[a2]; ++i )\n {\n v6 = *i;\n if ( *i <= a3 )\n {\n if ( a3 == v6 )\n {\n v9 = 1;\nLABEL_9:\n if ( v3 > v9 )\n v3 = v9;\n continue;\n }\n v8 = func0_part_0(a1, (unsigned int)a2, (unsigned int)(a3 - v6));\n if ( v8 != 0x7FFFFFFF )\n {\n v9 = v8 + 1;\n goto LABEL_9;\n }\n }\n }\n }\n return (unsigned int)v3;\n}", + "ida_strip_asm": "sub_1290:\npush r15\npush r14\nmov r14d, 7FFFFFFFh\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\ntest esi, esi\njle short loc_12C9\nmovsxd rax, esi\nmov r15, rdi\nmov r12d, esi\nmov ebp, edx\nmov rbx, rdi\nlea r13, [rdi+rax*4]\nloc_12BA:\nmov eax, [rbx]\ncmp eax, ebp\njle short loc_12E0\nloc_12C0:\nadd rbx, 4\ncmp rbx, r13\njnz short loc_12BA\nloc_12C9:\nadd rsp, 8\nmov eax, r14d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_12E0:\nmov edx, ebp\nsub edx, eax\njz short loc_1308\nmov esi, r12d\nmov rdi, r15\ncall sub_1290\ncmp eax, 7FFFFFFFh\njz short loc_12C0\nadd eax, 1\nloc_12FB:\ncmp r14d, eax\ncmovg r14d, eax\njmp short loc_12C0\nloc_1308:\nmov eax, 1\njmp short loc_12FB", + "ida_strip_pseudo": "__int64 __fastcall sub_1290(int *a1, int a2, int a3)\n{\n int v3; // r14d\n int *i; // rbx\n int v6; // eax\n int v8; // eax\n int v9; // eax\n\n v3 = 0x7FFFFFFF;\n if ( a2 > 0 )\n {\n for ( i = a1; i != &a1[a2]; ++i )\n {\n v6 = *i;\n if ( *i <= a3 )\n {\n if ( a3 == v6 )\n {\n v9 = 1;\nLABEL_9:\n if ( v3 > v9 )\n v3 = v9;\n continue;\n }\n v8 = sub_1290(a1, (unsigned int)a2, (unsigned int)(a3 - v6));\n if ( v8 != 0x7FFFFFFF )\n {\n v9 = v8 + 1;\n goto LABEL_9;\n }\n }\n }\n }\n return (unsigned int)v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1290(int *a1, int a2, int a3) {\n int v3;\n int *i;\n int v6;\n int v8;\n int v9;\n v3 = 2147483647;\n if (a2 > 0) {\n for (i = a1; i != &a1[a2]; ++i) {\n v6 = *i;\n if (*i <= a3) {\n if (a3 == v6) {\n v9 = 1;\n LABEL_9:\n if (v3 > v9) v3 = v9;\n continue;\n }\n v8 = sub_1290(a1, (unsigned int)a2, (unsigned int)(a3 - v6));\n if (v8 != 2147483647) {\n v9 = v8 + 1;\n goto LABEL_9;\n }\n }\n }\n }\n return (unsigned int)v3;\n}", + "ida_pseudo_norm": "long long func0_part_0(int *a1, int a2, int a3) {\n int v3;\n int *i;\n int v6;\n int v8;\n int v9;\n v3 = 2147483647;\n if (a2 > 0) {\n for (i = a1; i != &a1[a2]; ++i) {\n v6 = *i;\n if (*i <= a3) {\n if (a3 == v6) {\n v9 = 1;\n LABEL_9:\n if (v3 > v9) v3 = v9;\n continue;\n }\n v8 = func0_part_0(a1, (unsigned int)a2, (unsigned int)(a3 - v6));\n if (v8 != 2147483647) {\n v9 = v8 + 1;\n goto LABEL_9;\n }\n }\n }\n }\n return (unsigned int)v3;\n}" + }, + { + "index": 531, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(int coins[], int m, int V) {\n if (V == 0) {\n return 0;\n }\n int res = INT_MAX;\n for (int i = 0; i < m; i++) {\n if (coins[i] <= V) {\n int sub_res = func0(coins, m, V - coins[i]);\n if (sub_res != INT_MAX && sub_res + 1 < res) {\n res = sub_res + 1;\n }\n }\n }\n return res;\n}", + "test": "int main() {\n\n assert(func0((int[]){9, 6, 5, 1}, 4, 11) == 2);\n\n assert(func0((int[]){4, 5, 6, 7, 8, 9}, 6, 9) == 1);\n\n assert(func0((int[]){1, 2, 3}, 3, 4) == 2);\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nxor %r15d,%r15d\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x28,%rsp\ntest %edx,%edx\nje 1351 \nmov $0x7fffffff,%r15d\ntest %esi,%esi\njle 1351 \nlea -0x1(%rsi),%eax\nmov %edx,%r14d\nmov %rdi,%rcx\nlea 0x4(%rdi,%rax,4),%r9\nmov (%rcx),%eax\ncmp %eax,%r14d\njge 1368 \nadd $0x4,%rcx\ncmp %r9,%rcx\njne 1341 \nadd $0x28,%rsp\nmov %r15d,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax,%rax,1)\nmov %r14d,%r12d\nsub %eax,%r12d\nje 1470 \nmov %rcx,0x8(%rsp)\nmov %rdi,%r8\nmov $0x7fffffff,%r13d\nmov %r14d,0x18(%rsp)\nmov (%r8),%eax\ncmp %eax,%r12d\njge 13c0 \nadd $0x4,%r8\ncmp %r9,%r8\njne 1387 \nmov 0x8(%rsp),%rcx\nmov 0x18(%rsp),%r14d\nlea 0x1(%r13),%eax\ncmp $0x7fffffff,%r13d\nje 1348 \ncmp %eax,%r15d\ncmovg %eax,%r15d\njmp 1348 \nnopl 0x0(%rax,%rax,1)\nmov %r12d,%r11d\nsub %eax,%r11d\nje 13f0 \nmov %rdi,%rcx\nmov $0x7fffffff,%r14d\nmov (%rcx),%eax\ncmp %eax,%r11d\njge 1400 \nadd $0x4,%rcx\ncmp %r9,%rcx\njne 13d1 \nlea 0x1(%r14),%eax\ncmp $0x7fffffff,%r14d\nje 138f \njmp 13f5 \nmov $0x1,%eax\ncmp %eax,%r13d\ncmovg %eax,%r13d\njmp 138f \nxchg %ax,%ax\nmov %r11d,%ebp\nsub %eax,%ebp\nje 1488 \nmov %rdi,%r10\nmov $0x7fffffff,%ebx\nmov (%r10),%eax\ncmp %eax,%ebp\njge 1440 \nadd $0x4,%r10\ncmp %r9,%r10\njne 1413 \ncmp $0x7fffffff,%ebx\nje 13d8 \nadd $0x1,%ebx\ncmp %ebx,%r14d\ncmovg %ebx,%r14d\njmp 13d8 \nnopw 0x0(%rax,%rax,1)\nmov %ebp,%edx\nsub %eax,%edx\nje 1490 \nmov %esi,0x1c(%rsp)\nmov %rdi,0x10(%rsp)\ncallq 1290 \nmov 0x10(%rsp),%rdi\nmov 0x1c(%rsp),%esi\ncmp $0x7fffffff,%eax\nje 141a \nadd $0x1,%eax\ncmp %eax,%ebx\ncmovg %eax,%ebx\njmp 141a \nxchg %ax,%ax\nmov $0x1,%eax\ncmp %eax,%r15d\ncmovg %eax,%r15d\njmpq 1348 \nnopl 0x0(%rax)\nmov $0x1,%ebx\njmp 142e \nmov $0x1,%eax\njmp 1467 \nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0_part_0:\npush r15\npush r14\npush r13\nmov r13d, 7FFFFFFFh\npush r12\npush rbp\npush rbx\nsub rsp, 58h\ntest esi, esi\njle short loc_12CE\nmovsxd rax, esi\nmov r12d, edx\nmov r14d, r13d\nmov rbx, rdi\nlea rdx, [rdi+rax*4]\nmov r13, rdx\nloc_12BB:\nmov eax, [rbx]\ncmp eax, r12d\njle short loc_12E0\nloc_12C2:\nadd rbx, 4\ncmp rbx, r13\njnz short loc_12BB\nmov r13d, r14d\nloc_12CE:\nadd rsp, 58h\nmov eax, r13d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_12E0:\nmov r15d, r12d\nsub r15d, eax\njz loc_14D8\nmov [rsp+88h+var_80], rbx\nmov ecx, 7FFFFFFFh\nmov rbp, rdi\nmov r8d, r14d\nmov [rsp+88h+var_74], r12d\nmov r12d, ecx\nloc_1304:\nmov eax, [rbp+0]\ncmp r15d, eax\njge short loc_1340\nloc_130C:\nadd rbp, 4\ncmp rbp, r13\njnz short loc_1304\nmov ecx, r12d\nmov rbx, [rsp+88h+var_80]\nmov r12d, [rsp+88h+var_74]\nmov r14d, r8d\ncmp ecx, 7FFFFFFFh\njz short loc_12C2\nadd ecx, 1\nloc_1330:\ncmp r14d, ecx\ncmovg r14d, ecx\njmp short loc_12C2\nloc_1340:\nmov r14d, r15d\nsub r14d, eax\njz loc_14E8\nmov [rsp+88h+var_70], r15d\nmov rcx, rbp\nmov eax, 7FFFFFFFh\nmov ebp, r14d\nmov [rsp+88h+var_6C], r12d\nmov rbx, rdi\nmov r9d, eax\nmov r14, rcx\nloc_136A:\nmov eax, [rbx]\ncmp ebp, eax\njge short loc_13A0\nloc_1370:\nadd rbx, 4\ncmp rbx, r13\njnz short loc_136A\nmov r15d, [rsp+88h+var_70]\nmov r12d, [rsp+88h+var_6C]\nmov rbp, r14\nmov eax, r9d\ncmp r9d, 7FFFFFFFh\njz loc_130C\nadd eax, 1\njmp loc_14ED\nloc_13A0:\nmov r12d, ebp\nsub r12d, eax\njz short loc_13F8\nmov [rsp+88h+var_58], r9d\nmov rcx, r14\nmov r9, rbx\nmov r15, rdi\nmov r11d, 7FFFFFFFh\nmov r14d, ebp\nmov ebx, r12d\nmov r10, r13\nloc_13C5:\nmov eax, [r15]\ncmp ebx, eax\njge short loc_1410\nloc_13CC:\nadd r15, 4\ncmp r15, r10\njnz short loc_13C5\nmov ebp, r14d\nmov rbx, r9\nmov r14, rcx\nmov r9d, [rsp+88h+var_58]\nmov r13, r10\ncmp r11d, 7FFFFFFFh\njz short loc_1370\nadd r11d, 1\njmp short loc_13FE\nloc_13F8:\nmov r11d, 1\nloc_13FE:\ncmp r9d, r11d\ncmovg r9d, r11d\njmp loc_1370\nloc_1410:\nmov ebp, ebx\nsub ebp, eax\njz loc_1500\nmov [rsp+88h+var_68], r15\nxor r12d, r12d\nmov r15d, ebx\nmov r13d, 7FFFFFFFh\nmov rbx, rcx\nloc_142E:\nmov eax, [rdi+r12*4]\ncmp ebp, eax\njge short loc_1470\nloc_1436:\nadd r12, 1\ncmp esi, r12d\njg short loc_142E\nmov rcx, rbx\nmov ebx, r15d\nmov r15, [rsp+88h+var_68]\ncmp r13d, 7FFFFFFFh\njz loc_13CC\nadd r13d, 1\nloc_145B:\ncmp r11d, r13d\ncmovg r11d, r13d\njmp loc_13CC\nloc_1470:\nmov edx, ebp\nsub edx, eax\njz loc_1510\nmov [rsp+88h+var_3C], r8d\nmov [rsp+88h+var_48], r10\nmov [rsp+88h+var_40], r11d\nmov [rsp+88h+var_50], r9\nmov [rsp+88h+var_54], esi\nmov [rsp+88h+var_60], rdi\ncall func0_part_0\nmov rdi, [rsp+88h+var_60]\nmov esi, [rsp+88h+var_54]\ncmp eax, 7FFFFFFFh\nmov r9, [rsp+88h+var_50]\nmov r11d, [rsp+88h+var_40]\nmov r10, [rsp+88h+var_48]\nmov r8d, [rsp+88h+var_3C]\njz loc_1436\nadd eax, 1\nloc_14C7:\ncmp r13d, eax\ncmovg r13d, eax\njmp loc_1436\nloc_14D8:\nmov ecx, 1\njmp loc_1330\nloc_14E8:\nmov eax, 1\nloc_14ED:\ncmp r12d, eax\ncmovg r12d, eax\njmp loc_130C\nloc_1500:\nmov r13d, 1\njmp loc_145B\nloc_1510:\nmov eax, 1\njmp short loc_14C7", + "ida_pseudo": "__int64 __fastcall func0_part_0(_DWORD *a1, __int64 a2, int a3)\n{\n unsigned int v3; // r13d\n int v5; // r14d\n _DWORD *v6; // rbx\n _DWORD *v7; // r13\n int v8; // eax\n int v10; // r15d\n _DWORD *v11; // rbp\n int v12; // r8d\n int v13; // r12d\n int v14; // eax\n int v15; // ecx\n int v16; // ecx\n _DWORD *v17; // rcx\n int v18; // ebp\n _DWORD *v19; // rbx\n int v20; // r9d\n _DWORD *v21; // r14\n int v22; // eax\n int v23; // eax\n _DWORD *v24; // rcx\n _DWORD *v25; // r9\n _DWORD *v26; // r15\n int v27; // r11d\n int v28; // r14d\n int v29; // ebx\n _DWORD *v30; // r10\n int v31; // eax\n int v32; // r11d\n int v33; // ebp\n __int64 v34; // r12\n int v35; // r15d\n int v36; // r13d\n _DWORD *v37; // rbx\n int v38; // eax\n int v39; // r13d\n int v40; // eax\n int v41; // eax\n _DWORD *v42; // [rsp+8h] [rbp-80h]\n int v43; // [rsp+14h] [rbp-74h]\n int v44; // [rsp+18h] [rbp-70h]\n int v45; // [rsp+1Ch] [rbp-6Ch]\n _DWORD *v46; // [rsp+20h] [rbp-68h]\n int v47; // [rsp+30h] [rbp-58h]\n _DWORD *v48; // [rsp+38h] [rbp-50h]\n _DWORD *v49; // [rsp+40h] [rbp-48h]\n int v50; // [rsp+48h] [rbp-40h]\n int v51; // [rsp+4Ch] [rbp-3Ch]\n\n v3 = 0x7FFFFFFF;\n if ( (int)a2 > 0 )\n {\n v5 = 0x7FFFFFFF;\n v6 = a1;\n v7 = &a1[(int)a2];\n while ( 1 )\n {\n v8 = *v6;\n if ( *v6 > a3 )\n goto LABEL_4;\n v10 = a3 - v8;\n if ( a3 == v8 )\n {\n v16 = 1;\n goto LABEL_13;\n }\n v42 = v6;\n v11 = a1;\n v12 = v5;\n v43 = a3;\n v13 = 0x7FFFFFFF;\n do\n {\n v14 = *v11;\n if ( v10 < *v11 )\n goto LABEL_10;\n if ( v10 == v14 )\n {\n v23 = 1;\n goto LABEL_49;\n }\n v44 = v10;\n v17 = v11;\n v18 = v10 - v14;\n v45 = v13;\n v19 = a1;\n v20 = 0x7FFFFFFF;\n v21 = v17;\n do\n {\n v22 = *v19;\n if ( v18 < *v19 )\n goto LABEL_19;\n if ( v18 == v22 )\n {\n v32 = 1;\n goto LABEL_29;\n }\n v47 = v20;\n v24 = v21;\n v25 = v19;\n v26 = a1;\n v27 = 0x7FFFFFFF;\n v28 = v18;\n v29 = v18 - v22;\n v30 = v7;\n do\n {\n v31 = *v26;\n if ( v29 < *v26 )\n goto LABEL_25;\n v33 = v29 - v31;\n if ( v29 == v31 )\n {\n v39 = 1;\n goto LABEL_38;\n }\n v46 = v26;\n v34 = 0LL;\n v35 = v29;\n v36 = 0x7FFFFFFF;\n v37 = v24;\n do\n {\n v38 = a1[v34];\n if ( v33 < v38 )\n goto LABEL_35;\n if ( v33 == v38 )\n {\n v41 = 1;\n }\n else\n {\n v51 = v12;\n v49 = v30;\n v50 = v27;\n v48 = v25;\n v40 = func0_part_0(a1, a2, (unsigned int)(v33 - v38));\n a2 = (unsigned int)a2;\n v25 = v48;\n v27 = v50;\n v30 = v49;\n v12 = v51;\n if ( v40 == 0x7FFFFFFF )\n goto LABEL_35;\n v41 = v40 + 1;\n }\n if ( v36 > v41 )\n v36 = v41;\nLABEL_35:\n ++v34;\n }\n while ( (int)a2 > (int)v34 );\n v24 = v37;\n v29 = v35;\n v26 = v46;\n if ( v36 != 0x7FFFFFFF )\n {\n v39 = v36 + 1;\nLABEL_38:\n if ( v27 > v39 )\n v27 = v39;\n }\nLABEL_25:\n ++v26;\n }\n while ( v26 != v30 );\n v18 = v28;\n v19 = v25;\n v21 = v24;\n v20 = v47;\n v7 = v30;\n if ( v27 != 0x7FFFFFFF )\n {\n v32 = v27 + 1;\nLABEL_29:\n if ( v20 > v32 )\n v20 = v32;\n }\nLABEL_19:\n ++v19;\n }\n while ( v19 != v7 );\n v10 = v44;\n v13 = v45;\n v11 = v21;\n if ( v20 != 0x7FFFFFFF )\n {\n v23 = v20 + 1;\nLABEL_49:\n if ( v13 > v23 )\n v13 = v23;\n }\nLABEL_10:\n ++v11;\n }\n while ( v11 != v7 );\n v15 = v13;\n v6 = v42;\n a3 = v43;\n v5 = v12;\n if ( v15 != 0x7FFFFFFF )\n {\n v16 = v15 + 1;\nLABEL_13:\n if ( v5 > v16 )\n v5 = v16;\n }\nLABEL_4:\n if ( ++v6 == v7 )\n return (unsigned int)v5;\n }\n }\n return v3;\n}", + "ida_strip_asm": "sub_1290:\npush r15\npush r14\npush r13\nmov r13d, 7FFFFFFFh\npush r12\npush rbp\npush rbx\nsub rsp, 58h\ntest esi, esi\njle short loc_12CE\nmovsxd rax, esi\nmov r12d, edx\nmov r14d, r13d\nmov rbx, rdi\nlea rdx, [rdi+rax*4]\nmov r13, rdx\nloc_12BB:\nmov eax, [rbx]\ncmp eax, r12d\njle short loc_12E0\nloc_12C2:\nadd rbx, 4\ncmp rbx, r13\njnz short loc_12BB\nmov r13d, r14d\nloc_12CE:\nadd rsp, 58h\nmov eax, r13d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_12E0:\nmov r15d, r12d\nsub r15d, eax\njz loc_14D8\nmov [rsp+88h+var_80], rbx\nmov ecx, 7FFFFFFFh\nmov rbp, rdi\nmov r8d, r14d\nmov [rsp+88h+var_74], r12d\nmov r12d, ecx\nloc_1304:\nmov eax, [rbp+0]\ncmp r15d, eax\njge short loc_1340\nloc_130C:\nadd rbp, 4\ncmp rbp, r13\njnz short loc_1304\nmov ecx, r12d\nmov rbx, [rsp+88h+var_80]\nmov r12d, [rsp+88h+var_74]\nmov r14d, r8d\ncmp ecx, 7FFFFFFFh\njz short loc_12C2\nadd ecx, 1\nloc_1330:\ncmp r14d, ecx\ncmovg r14d, ecx\njmp short loc_12C2\nloc_1340:\nmov r14d, r15d\nsub r14d, eax\njz loc_14E8\nmov [rsp+88h+var_70], r15d\nmov rcx, rbp\nmov eax, 7FFFFFFFh\nmov ebp, r14d\nmov [rsp+88h+var_6C], r12d\nmov rbx, rdi\nmov r9d, eax\nmov r14, rcx\nloc_136A:\nmov eax, [rbx]\ncmp ebp, eax\njge short loc_13A0\nloc_1370:\nadd rbx, 4\ncmp rbx, r13\njnz short loc_136A\nmov r15d, [rsp+88h+var_70]\nmov r12d, [rsp+88h+var_6C]\nmov rbp, r14\nmov eax, r9d\ncmp r9d, 7FFFFFFFh\njz loc_130C\nadd eax, 1\njmp loc_14ED\nloc_13A0:\nmov r12d, ebp\nsub r12d, eax\njz short loc_13F8\nmov [rsp+88h+var_58], r9d\nmov rcx, r14\nmov r9, rbx\nmov r15, rdi\nmov r11d, 7FFFFFFFh\nmov r14d, ebp\nmov ebx, r12d\nmov r10, r13\nloc_13C5:\nmov eax, [r15]\ncmp ebx, eax\njge short loc_1410\nloc_13CC:\nadd r15, 4\ncmp r15, r10\njnz short loc_13C5\nmov ebp, r14d\nmov rbx, r9\nmov r14, rcx\nmov r9d, [rsp+88h+var_58]\nmov r13, r10\ncmp r11d, 7FFFFFFFh\njz short loc_1370\nadd r11d, 1\njmp short loc_13FE\nloc_13F8:\nmov r11d, 1\nloc_13FE:\ncmp r9d, r11d\ncmovg r9d, r11d\njmp loc_1370\nloc_1410:\nmov ebp, ebx\nsub ebp, eax\njz loc_1500\nmov [rsp+88h+var_68], r15\nxor r12d, r12d\nmov r15d, ebx\nmov r13d, 7FFFFFFFh\nmov rbx, rcx\nloc_142E:\nmov eax, [rdi+r12*4]\ncmp ebp, eax\njge short loc_1470\nloc_1436:\nadd r12, 1\ncmp esi, r12d\njg short loc_142E\nmov rcx, rbx\nmov ebx, r15d\nmov r15, [rsp+88h+var_68]\ncmp r13d, 7FFFFFFFh\njz loc_13CC\nadd r13d, 1\nloc_145B:\ncmp r11d, r13d\ncmovg r11d, r13d\njmp loc_13CC\nloc_1470:\nmov edx, ebp\nsub edx, eax\njz loc_1510\nmov [rsp+88h+var_3C], r8d\nmov [rsp+88h+var_48], r10\nmov [rsp+88h+var_40], r11d\nmov [rsp+88h+var_50], r9\nmov [rsp+88h+var_54], esi\nmov [rsp+88h+var_60], rdi\ncall sub_1290\nmov rdi, [rsp+88h+var_60]\nmov esi, [rsp+88h+var_54]\ncmp eax, 7FFFFFFFh\nmov r9, [rsp+88h+var_50]\nmov r11d, [rsp+88h+var_40]\nmov r10, [rsp+88h+var_48]\nmov r8d, [rsp+88h+var_3C]\njz loc_1436\nadd eax, 1\nloc_14C7:\ncmp r13d, eax\ncmovg r13d, eax\njmp loc_1436\nloc_14D8:\nmov ecx, 1\njmp loc_1330\nloc_14E8:\nmov eax, 1\nloc_14ED:\ncmp r12d, eax\ncmovg r12d, eax\njmp loc_130C\nloc_1500:\nmov r13d, 1\njmp loc_145B\nloc_1510:\nmov eax, 1\njmp short loc_14C7", + "ida_strip_pseudo": "__int64 __fastcall sub_1290(_DWORD *a1, __int64 a2, int a3)\n{\n unsigned int v3; // r13d\n int v5; // r14d\n _DWORD *v6; // rbx\n _DWORD *v7; // r13\n int v8; // eax\n int v10; // r15d\n _DWORD *v11; // rbp\n int v12; // r8d\n int v13; // r12d\n int v14; // eax\n int v15; // ecx\n int v16; // ecx\n _DWORD *v17; // rcx\n int v18; // ebp\n _DWORD *v19; // rbx\n int v20; // r9d\n _DWORD *v21; // r14\n int v22; // eax\n int v23; // eax\n _DWORD *v24; // rcx\n _DWORD *v25; // r9\n _DWORD *v26; // r15\n int v27; // r11d\n int v28; // r14d\n int v29; // ebx\n _DWORD *v30; // r10\n int v31; // eax\n int v32; // r11d\n int v33; // ebp\n __int64 v34; // r12\n int v35; // r15d\n int v36; // r13d\n _DWORD *v37; // rbx\n int v38; // eax\n int v39; // r13d\n int v40; // eax\n int v41; // eax\n _DWORD *v42; // [rsp+8h] [rbp-80h]\n int v43; // [rsp+14h] [rbp-74h]\n int v44; // [rsp+18h] [rbp-70h]\n int v45; // [rsp+1Ch] [rbp-6Ch]\n _DWORD *v46; // [rsp+20h] [rbp-68h]\n int v47; // [rsp+30h] [rbp-58h]\n _DWORD *v48; // [rsp+38h] [rbp-50h]\n _DWORD *v49; // [rsp+40h] [rbp-48h]\n int v50; // [rsp+48h] [rbp-40h]\n int v51; // [rsp+4Ch] [rbp-3Ch]\n\n v3 = 0x7FFFFFFF;\n if ( (int)a2 > 0 )\n {\n v5 = 0x7FFFFFFF;\n v6 = a1;\n v7 = &a1[(int)a2];\n while ( 1 )\n {\n v8 = *v6;\n if ( *v6 > a3 )\n goto LABEL_4;\n v10 = a3 - v8;\n if ( a3 == v8 )\n {\n v16 = 1;\n goto LABEL_13;\n }\n v42 = v6;\n v11 = a1;\n v12 = v5;\n v43 = a3;\n v13 = 0x7FFFFFFF;\n do\n {\n v14 = *v11;\n if ( v10 < *v11 )\n goto LABEL_10;\n if ( v10 == v14 )\n {\n v23 = 1;\n goto LABEL_49;\n }\n v44 = v10;\n v17 = v11;\n v18 = v10 - v14;\n v45 = v13;\n v19 = a1;\n v20 = 0x7FFFFFFF;\n v21 = v17;\n do\n {\n v22 = *v19;\n if ( v18 < *v19 )\n goto LABEL_19;\n if ( v18 == v22 )\n {\n v32 = 1;\n goto LABEL_29;\n }\n v47 = v20;\n v24 = v21;\n v25 = v19;\n v26 = a1;\n v27 = 0x7FFFFFFF;\n v28 = v18;\n v29 = v18 - v22;\n v30 = v7;\n do\n {\n v31 = *v26;\n if ( v29 < *v26 )\n goto LABEL_25;\n v33 = v29 - v31;\n if ( v29 == v31 )\n {\n v39 = 1;\n goto LABEL_38;\n }\n v46 = v26;\n v34 = 0LL;\n v35 = v29;\n v36 = 0x7FFFFFFF;\n v37 = v24;\n do\n {\n v38 = a1[v34];\n if ( v33 < v38 )\n goto LABEL_35;\n if ( v33 == v38 )\n {\n v41 = 1;\n }\n else\n {\n v51 = v12;\n v49 = v30;\n v50 = v27;\n v48 = v25;\n v40 = sub_1290(a1, a2, (unsigned int)(v33 - v38));\n a2 = (unsigned int)a2;\n v25 = v48;\n v27 = v50;\n v30 = v49;\n v12 = v51;\n if ( v40 == 0x7FFFFFFF )\n goto LABEL_35;\n v41 = v40 + 1;\n }\n if ( v36 > v41 )\n v36 = v41;\nLABEL_35:\n ++v34;\n }\n while ( (int)a2 > (int)v34 );\n v24 = v37;\n v29 = v35;\n v26 = v46;\n if ( v36 != 0x7FFFFFFF )\n {\n v39 = v36 + 1;\nLABEL_38:\n if ( v27 > v39 )\n v27 = v39;\n }\nLABEL_25:\n ++v26;\n }\n while ( v26 != v30 );\n v18 = v28;\n v19 = v25;\n v21 = v24;\n v20 = v47;\n v7 = v30;\n if ( v27 != 0x7FFFFFFF )\n {\n v32 = v27 + 1;\nLABEL_29:\n if ( v20 > v32 )\n v20 = v32;\n }\nLABEL_19:\n ++v19;\n }\n while ( v19 != v7 );\n v10 = v44;\n v13 = v45;\n v11 = v21;\n if ( v20 != 0x7FFFFFFF )\n {\n v23 = v20 + 1;\nLABEL_49:\n if ( v13 > v23 )\n v13 = v23;\n }\nLABEL_10:\n ++v11;\n }\n while ( v11 != v7 );\n v15 = v13;\n v6 = v42;\n a3 = v43;\n v5 = v12;\n if ( v15 != 0x7FFFFFFF )\n {\n v16 = v15 + 1;\nLABEL_13:\n if ( v5 > v16 )\n v5 = v16;\n }\nLABEL_4:\n if ( ++v6 == v7 )\n return (unsigned int)v5;\n }\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1290(uint32_t *a1, long long a2, int a3) {\n unsigned int v3;\n int v5;\n uint32_t *v6;\n uint32_t *v7;\n int v8;\n int v10;\n uint32_t *v11;\n int v12;\n int v13;\n int v14;\n int v15;\n int v16;\n uint32_t *v17;\n int v18;\n uint32_t *v19;\n int v20;\n uint32_t *v21;\n int v22;\n int v23;\n uint32_t *v24;\n uint32_t *v25;\n uint32_t *v26;\n int v27;\n int v28;\n int v29;\n uint32_t *v30;\n int v31;\n int v32;\n int v33;\n long long v34;\n int v35;\n int v36;\n uint32_t *v37;\n int v38;\n int v39;\n int v40;\n int v41;\n uint32_t *v42;\n int v43;\n int v44;\n int v45;\n uint32_t *v46;\n int v47;\n uint32_t *v48;\n uint32_t *v49;\n int v50;\n int v51;\n v3 = 2147483647;\n if ((int)a2 > 0) {\n v5 = 2147483647;\n v6 = a1;\n v7 = &a1[(int)a2];\n while (1) {\n v8 = *v6;\n if (*v6 > a3) goto LABEL_4;\n v10 = a3 - v8;\n if (a3 == v8) {\n v16 = 1;\n goto LABEL_13;\n }\n v42 = v6;\n v11 = a1;\n v12 = v5;\n v43 = a3;\n v13 = 2147483647;\n do {\n v14 = *v11;\n if (v10 < *v11) goto LABEL_10;\n if (v10 == v14) {\n v23 = 1;\n goto LABEL_49;\n }\n v44 = v10;\n v17 = v11;\n v18 = v10 - v14;\n v45 = v13;\n v19 = a1;\n v20 = 2147483647;\n v21 = v17;\n do {\n v22 = *v19;\n if (v18 < *v19) goto LABEL_19;\n if (v18 == v22) {\n v32 = 1;\n goto LABEL_29;\n }\n v47 = v20;\n v24 = v21;\n v25 = v19;\n v26 = a1;\n v27 = 2147483647;\n v28 = v18;\n v29 = v18 - v22;\n v30 = v7;\n do {\n v31 = *v26;\n if (v29 < *v26) goto LABEL_25;\n v33 = v29 - v31;\n if (v29 == v31) {\n v39 = 1;\n goto LABEL_38;\n }\n v46 = v26;\n v34 = 0LL;\n v35 = v29;\n v36 = 2147483647;\n v37 = v24;\n do {\n v38 = a1[v34];\n if (v33 < v38) goto LABEL_35;\n if (v33 == v38) {\n v41 = 1;\n } else {\n v51 = v12;\n v49 = v30;\n v50 = v27;\n v48 = v25;\n v40 = sub_1290(a1, a2, (unsigned int)(v33 - v38));\n a2 = (unsigned int)a2;\n v25 = v48;\n v27 = v50;\n v30 = v49;\n v12 = v51;\n if (v40 == 2147483647) goto LABEL_35;\n v41 = v40 + 1;\n }\n if (v36 > v41) v36 = v41;\n LABEL_35:\n ++v34;\n } while ((int)a2 > (int)v34);\n v24 = v37;\n v29 = v35;\n v26 = v46;\n if (v36 != 2147483647) {\n v39 = v36 + 1;\n LABEL_38:\n if (v27 > v39) v27 = v39;\n }\n LABEL_25:\n ++v26;\n } while (v26 != v30);\n v18 = v28;\n v19 = v25;\n v21 = v24;\n v20 = v47;\n v7 = v30;\n if (v27 != 2147483647) {\n v32 = v27 + 1;\n LABEL_29:\n if (v20 > v32) v20 = v32;\n }\n LABEL_19:\n ++v19;\n } while (v19 != v7);\n v10 = v44;\n v13 = v45;\n v11 = v21;\n if (v20 != 2147483647) {\n v23 = v20 + 1;\n LABEL_49:\n if (v13 > v23) v13 = v23;\n }\n LABEL_10:\n ++v11;\n } while (v11 != v7);\n v15 = v13;\n v6 = v42;\n a3 = v43;\n v5 = v12;\n if (v15 != 2147483647) {\n v16 = v15 + 1;\n LABEL_13:\n if (v5 > v16) v5 = v16;\n }\n LABEL_4:\n if (++v6 == v7) return (unsigned int)v5;\n }\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0_part_0(uint32_t *a1, long long a2, int a3) {\n unsigned int v3;\n int v5;\n uint32_t *v6;\n uint32_t *v7;\n int v8;\n int v10;\n uint32_t *v11;\n int v12;\n int v13;\n int v14;\n int v15;\n int v16;\n uint32_t *v17;\n int v18;\n uint32_t *v19;\n int v20;\n uint32_t *v21;\n int v22;\n int v23;\n uint32_t *v24;\n uint32_t *v25;\n uint32_t *v26;\n int v27;\n int v28;\n int v29;\n uint32_t *v30;\n int v31;\n int v32;\n int v33;\n long long v34;\n int v35;\n int v36;\n uint32_t *v37;\n int v38;\n int v39;\n int v40;\n int v41;\n uint32_t *v42;\n int v43;\n int v44;\n int v45;\n uint32_t *v46;\n int v47;\n uint32_t *v48;\n uint32_t *v49;\n int v50;\n int v51;\n v3 = 2147483647;\n if ((int)a2 > 0) {\n v5 = 2147483647;\n v6 = a1;\n v7 = &a1[(int)a2];\n while (1) {\n v8 = *v6;\n if (*v6 > a3) goto LABEL_4;\n v10 = a3 - v8;\n if (a3 == v8) {\n v16 = 1;\n goto LABEL_13;\n }\n v42 = v6;\n v11 = a1;\n v12 = v5;\n v43 = a3;\n v13 = 2147483647;\n do {\n v14 = *v11;\n if (v10 < *v11) goto LABEL_10;\n if (v10 == v14) {\n v23 = 1;\n goto LABEL_49;\n }\n v44 = v10;\n v17 = v11;\n v18 = v10 - v14;\n v45 = v13;\n v19 = a1;\n v20 = 2147483647;\n v21 = v17;\n do {\n v22 = *v19;\n if (v18 < *v19) goto LABEL_19;\n if (v18 == v22) {\n v32 = 1;\n goto LABEL_29;\n }\n v47 = v20;\n v24 = v21;\n v25 = v19;\n v26 = a1;\n v27 = 2147483647;\n v28 = v18;\n v29 = v18 - v22;\n v30 = v7;\n do {\n v31 = *v26;\n if (v29 < *v26) goto LABEL_25;\n v33 = v29 - v31;\n if (v29 == v31) {\n v39 = 1;\n goto LABEL_38;\n }\n v46 = v26;\n v34 = 0LL;\n v35 = v29;\n v36 = 2147483647;\n v37 = v24;\n do {\n v38 = a1[v34];\n if (v33 < v38) goto LABEL_35;\n if (v33 == v38) {\n v41 = 1;\n } else {\n v51 = v12;\n v49 = v30;\n v50 = v27;\n v48 = v25;\n v40 = func0_part_0(a1, a2, (unsigned int)(v33 - v38));\n a2 = (unsigned int)a2;\n v25 = v48;\n v27 = v50;\n v30 = v49;\n v12 = v51;\n if (v40 == 2147483647) goto LABEL_35;\n v41 = v40 + 1;\n }\n if (v36 > v41) v36 = v41;\n LABEL_35:\n ++v34;\n } while ((int)a2 > (int)v34);\n v24 = v37;\n v29 = v35;\n v26 = v46;\n if (v36 != 2147483647) {\n v39 = v36 + 1;\n LABEL_38:\n if (v27 > v39) v27 = v39;\n }\n LABEL_25:\n ++v26;\n } while (v26 != v30);\n v18 = v28;\n v19 = v25;\n v21 = v24;\n v20 = v47;\n v7 = v30;\n if (v27 != 2147483647) {\n v32 = v27 + 1;\n LABEL_29:\n if (v20 > v32) v20 = v32;\n }\n LABEL_19:\n ++v19;\n } while (v19 != v7);\n v10 = v44;\n v13 = v45;\n v11 = v21;\n if (v20 != 2147483647) {\n v23 = v20 + 1;\n LABEL_49:\n if (v13 > v23) v13 = v23;\n }\n LABEL_10:\n ++v11;\n } while (v11 != v7);\n v15 = v13;\n v6 = v42;\n a3 = v43;\n v5 = v12;\n if (v15 != 2147483647) {\n v16 = v15 + 1;\n LABEL_13:\n if (v5 > v16) v5 = v16;\n }\n LABEL_4:\n if (++v6 == v7) return (unsigned int)v5;\n }\n }\n return v3;\n}" + }, + { + "index": 532, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\nint compare_chars(const void* a, const void* b) {\n\n char arg1 = *(const char*)a;\n\n char arg2 = *(const char*)b;\n\n if (arg1 < arg2) return -1;\n\n if (arg1 > arg2) return 1;\n\n return 0;\n\n}\n\n\n\n", + "func": "int func0(char *str1, char *str2) {\n int n1 = strlen(str1);\n int n2 = strlen(str2);\n if (n1 != n2) {\n return 0;\n }\n qsort(str1, n1, sizeof(char), compare_chars);\n qsort(str2, n2, sizeof(char), compare_chars);\n for (int i = 0; i < n1; i++) {\n if (str1[i] != str2[i]) {\n return 0;\n }\n }\n return 1;\n}", + "test": "int main() {\n\n char str1[] = \"abc\";\n\n char str2[] = \"cba\";\n\n char str3[] = \"test\";\n\n char str4[] = \"ttew\";\n\n char str5[] = \"xxyz\";\n\n char str6[] = \"yxzx\";\n\n \n\n assert(func0(str1, str2) == 1);\n\n assert(func0(str3, str4) == 0);\n\n assert(func0(str5, str6) == 1);\n\n\n\n printf(\"All tests passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov -0x18(%rbp),%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %eax,-0x8(%rbp)\nmov -0x20(%rbp),%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %eax,-0x4(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x4(%rbp),%eax\nje 1258 \nmov $0x0,%eax\njmpq 12d9 \nmov -0x8(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x18(%rbp),%rax\nlea -0xa0(%rip),%rcx\nmov $0x1,%edx\nmov %rax,%rdi\ncallq 10a0 \nmov -0x4(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x20(%rbp),%rax\nlea -0xbe(%rip),%rcx\nmov $0x1,%edx\nmov %rax,%rdi\ncallq 10a0 \nmovl $0x0,-0xc(%rbp)\njmp 12cc \nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%edx\nmov -0xc(%rbp),%eax\nmovslq %eax,%rcx\nmov -0x20(%rbp),%rax\nadd %rcx,%rax\nmovzbl (%rax),%eax\ncmp %al,%dl\nje 12c8 \nmov $0x0,%eax\njmp 12d9 \naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x8(%rbp),%eax\njl 129d \nmov $0x1,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov [rbp+var_20], rsi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_8], eax\nmov rax, [rbp+var_20]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njz short loc_1258\nmov eax, 0\njmp locret_12DF\nloc_1258:\nmov eax, [rbp+var_8]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+s]\nlea rdx, compare_chars\nmov rcx, rdx; compar\nmov edx, 1; size\nmov rdi, rax; base\ncall _qsort\nmov eax, [rbp+var_4]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+var_20]\nlea rdx, compare_chars\nmov rcx, rdx; compar\nmov edx, 1; size\nmov rdi, rax; base\ncall _qsort\nmov [rbp+var_C], 0\njmp short loc_12D2\nloc_12A3:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_C]\nmovsxd rcx, eax\nmov rax, [rbp+var_20]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njz short loc_12CE\nmov eax, 0\njmp short locret_12DF\nloc_12CE:\nadd [rbp+var_C], 1\nloc_12D2:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_8]\njl short loc_12A3\nmov eax, 1\nlocret_12DF:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(char *a1, char *a2)\n{\n int i; // [rsp+14h] [rbp-Ch]\n int v4; // [rsp+18h] [rbp-8h]\n int v5; // [rsp+1Ch] [rbp-4h]\n\n v4 = strlen(a1);\n v5 = strlen(a2);\n if ( v4 != v5 )\n return 0LL;\n qsort(a1, v4, 1uLL, compare_chars);\n qsort(a2, v5, 1uLL, compare_chars);\n for ( i = 0; i < v4; ++i )\n {\n if ( a1[i] != a2[i] )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1214:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov [rbp+var_20], rsi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_8], eax\nmov rax, [rbp+var_20]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njz short loc_1258\nmov eax, 0\njmp locret_12DF\nloc_1258:\nmov eax, [rbp+var_8]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+s]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 1; size\nmov rdi, rax; base\ncall _qsort\nmov eax, [rbp+var_4]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+var_20]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 1; size\nmov rdi, rax; base\ncall _qsort\nmov [rbp+var_C], 0\njmp short loc_12D2\nloc_12A3:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_C]\nmovsxd rcx, eax\nmov rax, [rbp+var_20]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njz short loc_12CE\nmov eax, 0\njmp short locret_12DF\nloc_12CE:\nadd [rbp+var_C], 1\nloc_12D2:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_8]\njl short loc_12A3\nmov eax, 1\nlocret_12DF:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1214(char *a1, char *a2)\n{\n int i; // [rsp+14h] [rbp-Ch]\n int v4; // [rsp+18h] [rbp-8h]\n int v5; // [rsp+1Ch] [rbp-4h]\n\n v4 = strlen(a1);\n v5 = strlen(a2);\n if ( v4 != v5 )\n return 0LL;\n qsort(a1, v4, 1uLL, compar);\n qsort(a2, v5, 1uLL, compar);\n for ( i = 0; i < v4; ++i )\n {\n if ( a1[i] != a2[i] )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1214(char *a1, char *a2) {\n int i;\n int v4;\n int v5;\n v4 = strlen(a1);\n v5 = strlen(a2);\n if (v4 != v5) return 0LL;\n qsort(a1, v4, 1uLL, compar);\n qsort(a2, v5, 1uLL, compar);\n for (i = 0; i < v4; ++i) {\n if (a1[i] != a2[i]) return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(char *a1, char *a2) {\n int i;\n int v4;\n int v5;\n v4 = strlen(a1);\n v5 = strlen(a2);\n if (v4 != v5) return 0LL;\n qsort(a1, v4, 1uLL, compare_chars);\n qsort(a2, v5, 1uLL, compare_chars);\n for (i = 0; i < v4; ++i) {\n if (a1[i] != a2[i]) return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": 532, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\nint compare_chars(const void* a, const void* b) {\n\n char arg1 = *(const char*)a;\n\n char arg2 = *(const char*)b;\n\n if (arg1 < arg2) return -1;\n\n if (arg1 > arg2) return 1;\n\n return 0;\n\n}\n\n\n\n", + "func": "int func0(char *str1, char *str2) {\n int n1 = strlen(str1);\n int n2 = strlen(str2);\n if (n1 != n2) {\n return 0;\n }\n qsort(str1, n1, sizeof(char), compare_chars);\n qsort(str2, n2, sizeof(char), compare_chars);\n for (int i = 0; i < n1; i++) {\n if (str1[i] != str2[i]) {\n return 0;\n }\n }\n return 1;\n}", + "test": "int main() {\n\n char str1[] = \"abc\";\n\n char str2[] = \"cba\";\n\n char str3[] = \"test\";\n\n char str4[] = \"ttew\";\n\n char str5[] = \"xxyz\";\n\n char str6[] = \"yxzx\";\n\n \n\n assert(func0(str1, str2) == 1);\n\n assert(func0(str3, str4) == 0);\n\n assert(func0(str5, str6) == 1);\n\n\n\n printf(\"All tests passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbp\nmov $0xffffffffffffffff,%rbx\nmov $0x0,%eax\nmov %rbx,%rcx\nrepnz scas %es:(%rdi),%al\nnot %rcx\nlea -0x1(%rcx),%r13\nmov %rbx,%rcx\nmov %rsi,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rbx\nmov $0x0,%eax\ncmp %ebx,%r13d\nje 1213 \nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nmov %rsi,%r12\nmovslq %r13d,%rsi\nlea -0x77(%rip),%rcx\nmov $0x1,%edx\nmov %rbp,%rdi\ncallq 1090 \nmovslq %ebx,%rsi\nlea -0x8e(%rip),%rcx\nmov $0x1,%edx\nmov %r12,%rdi\ncallq 1090 \ntest %r13d,%r13d\njle 1272 \nlea -0x1(%r13),%ecx\nmov $0x0,%eax\njmp 1257 \nmov %rdx,%rax\nmovzbl (%r12,%rax,1),%ebx\ncmp %bl,0x0(%rbp,%rax,1)\njne 1279 \nlea 0x1(%rax),%rdx\ncmp %rcx,%rax\njne 1254 \nmov $0x1,%eax\njmp 1208 \nmov $0x1,%eax\njmp 1208 \nmov $0x0,%eax\njmp 1208 \n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nmov rbp, rsi\ncall _strlen\nmov r13, rax\nmov rdi, rbp; s\ncall _strlen\nmov r12, rax\nmov eax, 0\ncmp r13d, r12d\njz short loc_121B\nloc_1212:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_121B:\nmovsxd rsi, r13d; nmemb\nlea r14, compare_chars\nmov rcx, r14; compar\nmov edx, 1; size\nmov rdi, rbx; base\ncall _qsort\nmovsxd rsi, r12d; nmemb\nmov rcx, r14; compar\nmov edx, 1; size\nmov rdi, rbp; base\ncall _qsort\ntest r13d, r13d\njle short loc_1276\nlea ecx, [r13-1]\nmov eax, 0\njmp short loc_125B\nloc_1258:\nmov rax, rdx\nloc_125B:\nmovzx esi, byte ptr [rbp+rax+0]\ncmp [rbx+rax], sil\njnz short loc_127D\nlea rdx, [rax+1]\ncmp rax, rcx\njnz short loc_1258\nmov eax, 1\njmp short loc_1212\nloc_1276:\nmov eax, 1\njmp short loc_1212\nloc_127D:\nmov eax, 0\njmp short loc_1212", + "ida_pseudo": "__int64 __fastcall func0(char *base, char *a2)\n{\n int v2; // r13d\n int v3; // r12d\n __int64 result; // rax\n __int64 i; // rax\n\n v2 = strlen(base);\n v3 = strlen(a2);\n result = 0LL;\n if ( v2 == v3 )\n {\n qsort(base, v2, 1uLL, compare_chars);\n qsort(a2, v3, 1uLL, compare_chars);\n if ( v2 <= 0 )\n {\n return 1LL;\n }\n else\n {\n for ( i = 0LL; base[i] == a2[i]; ++i )\n {\n if ( i == v2 - 1 )\n return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_11E3:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nmov rbp, rsi\ncall _strlen\nmov r13, rax\nmov rdi, rbp; s\ncall _strlen\nmov r12, rax\nmov eax, 0\ncmp r13d, r12d\njz short loc_121B\nloc_1212:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_121B:\nmovsxd rsi, r13d; nmemb\nlea r14, compar\nmov rcx, r14; compar\nmov edx, 1; size\nmov rdi, rbx; base\ncall _qsort\nmovsxd rsi, r12d; nmemb\nmov rcx, r14; compar\nmov edx, 1; size\nmov rdi, rbp; base\ncall _qsort\ntest r13d, r13d\njle short loc_1276\nlea ecx, [r13-1]\nmov eax, 0\njmp short loc_125B\nloc_1258:\nmov rax, rdx\nloc_125B:\nmovzx esi, byte ptr [rbp+rax+0]\ncmp [rbx+rax], sil\njnz short loc_127D\nlea rdx, [rax+1]\ncmp rax, rcx\njnz short loc_1258\nmov eax, 1\njmp short loc_1212\nloc_1276:\nmov eax, 1\njmp short loc_1212\nloc_127D:\nmov eax, 0\njmp short loc_1212", + "ida_strip_pseudo": "__int64 __fastcall sub_11E3(char *base, char *a2)\n{\n int v2; // r13d\n int v3; // r12d\n __int64 result; // rax\n __int64 i; // rax\n\n v2 = strlen(base);\n v3 = strlen(a2);\n result = 0LL;\n if ( v2 == v3 )\n {\n qsort(base, v2, 1uLL, compar);\n qsort(a2, v3, 1uLL, compar);\n if ( v2 <= 0 )\n {\n return 1LL;\n }\n else\n {\n for ( i = 0LL; base[i] == a2[i]; ++i )\n {\n if ( i == v2 - 1 )\n return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11E3(char *base, char *a2) {\n int v2;\n int v3;\n long long result;\n long long i;\n v2 = strlen(base);\n v3 = strlen(a2);\n result = 0LL;\n if (v2 == v3) {\n qsort(base, v2, 1uLL, compar);\n qsort(a2, v3, 1uLL, compar);\n if (v2 <= 0) {\n return 1LL;\n } else {\n for (i = 0LL; base[i] == a2[i]; ++i) {\n if (i == v2 - 1) return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(char *base, char *a2) {\n int v2;\n int v3;\n long long result;\n long long i;\n v2 = strlen(base);\n v3 = strlen(a2);\n result = 0LL;\n if (v2 == v3) {\n qsort(base, v2, 1uLL, compare_chars);\n qsort(a2, v3, 1uLL, compare_chars);\n if (v2 <= 0) {\n return 1LL;\n } else {\n for (i = 0LL; base[i] == a2[i]; ++i) {\n if (i == v2 - 1) return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}" + }, + { + "index": 532, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\nint compare_chars(const void* a, const void* b) {\n\n char arg1 = *(const char*)a;\n\n char arg2 = *(const char*)b;\n\n if (arg1 < arg2) return -1;\n\n if (arg1 > arg2) return 1;\n\n return 0;\n\n}\n\n\n\n", + "func": "int func0(char *str1, char *str2) {\n int n1 = strlen(str1);\n int n2 = strlen(str2);\n if (n1 != n2) {\n return 0;\n }\n qsort(str1, n1, sizeof(char), compare_chars);\n qsort(str2, n2, sizeof(char), compare_chars);\n for (int i = 0; i < n1; i++) {\n if (str1[i] != str2[i]) {\n return 0;\n }\n }\n return 1;\n}", + "test": "int main() {\n\n char str1[] = \"abc\";\n\n char str2[] = \"cba\";\n\n char str3[] = \"test\";\n\n char str4[] = \"ttew\";\n\n char str5[] = \"xxyz\";\n\n char str6[] = \"yxzx\";\n\n \n\n assert(func0(str1, str2) == 1);\n\n assert(func0(str3, str4) == 0);\n\n assert(func0(str5, str6) == 1);\n\n\n\n printf(\"All tests passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\nmov %rsi,%rbp\npush %rbx\nmov %rdi,%rbx\nsub $0x8,%rsp\ncallq 10b0 \nmov %rbp,%rdi\nmov %rax,%r12\ncallq 10b0 \ncmp %eax,%r12d\nje 1350 \nadd $0x8,%rsp\nxor %eax,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopw %cs:0x0(%rax,%rax,1)\nmovslq %r12d,%r13\nlea -0x6a(%rip),%rcx\nmov $0x1,%edx\nmov %rbx,%rdi\nmov %r13,%rsi\ncallq 10a0 \nmov $0x1,%edx\nmov %r13,%rsi\nmov %rbp,%rdi\nlea -0x8c(%rip),%rcx\ncallq 10a0 \ntest %r12d,%r12d\njle 13b0 \nlea -0x1(%r12),%ecx\nxor %eax,%eax\njmp 139c \nlea 0x1(%rax),%rdx\ncmp %rcx,%rax\nje 13b0 \nmov %rdx,%rax\nmovzbl 0x0(%rbp,%rax,1),%esi\ncmp %sil,(%rbx,%rax,1)\nje 1390 \njmp 1339 \nnopl 0x0(%rax)\nadd $0x8,%rsp\nmov $0x1,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\nmov rbp, rsi\npush rbx\nmov rbx, rdi\ncall _strlen\nmov rdi, rbp; s\nmov r12, rax\ncall _strlen\ncmp r12d, eax\njz short loc_1348\nloc_1337:\npop rbx\nxor eax, eax\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1348:\nmovsxd r13, r12d\nlea r14, compare_chars\nmov edx, 1; size\nmov rdi, rbx; base\nmov rcx, r14; compar\nmov rsi, r13; nmemb\ncall _qsort\nmov rcx, r14; compar\nmov edx, 1; size\nmov rsi, r13; nmemb\nmov rdi, rbp; base\ncall _qsort\ntest r12d, r12d\njle short loc_13B0\nlea ecx, [r12-1]\nxor eax, eax\njmp short loc_139C\nloc_1390:\nlea rdx, [rax+1]\ncmp rax, rcx\njz short loc_13B0\nmov rax, rdx\nloc_139C:\nmovzx esi, byte ptr [rbp+rax+0]\ncmp [rbx+rax], sil\njz short loc_1390\njmp short loc_1337\nloc_13B0:\npop rbx\nmov eax, 1\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "__int64 __fastcall func0(char *base, char *a2)\n{\n int v2; // r12d\n __int64 i; // rax\n\n v2 = strlen(base);\n if ( v2 != (unsigned int)strlen(a2) )\n return 0LL;\n qsort(base, v2, 1uLL, compare_chars);\n qsort(a2, v2, 1uLL, compare_chars);\n if ( v2 > 0 )\n {\n for ( i = 0LL; base[i] == a2[i]; ++i )\n {\n if ( i == v2 - 1 )\n return 1LL;\n }\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1310:\nendbr64\npush r14\npush r13\npush r12\npush rbp\nmov rbp, rsi\npush rbx\nmov rbx, rdi\ncall _strlen\nmov rdi, rbp; s\nmov r12, rax\ncall _strlen\ncmp r12d, eax\njz short loc_1348\nloc_1337:\npop rbx\nxor eax, eax\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1348:\nmovsxd r13, r12d\nlea r14, compar\nmov edx, 1; size\nmov rdi, rbx; base\nmov rcx, r14; compar\nmov rsi, r13; nmemb\ncall _qsort\nmov rcx, r14; compar\nmov edx, 1; size\nmov rsi, r13; nmemb\nmov rdi, rbp; base\ncall _qsort\ntest r12d, r12d\njle short loc_13B0\nlea ecx, [r12-1]\nxor eax, eax\njmp short loc_139C\nloc_1390:\nlea rdx, [rax+1]\ncmp rax, rcx\njz short loc_13B0\nmov rax, rdx\nloc_139C:\nmovzx esi, byte ptr [rbp+rax+0]\ncmp [rbx+rax], sil\njz short loc_1390\njmp short loc_1337\nloc_13B0:\npop rbx\nmov eax, 1\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1310(char *base, char *a2)\n{\n int v2; // r12d\n __int64 i; // rax\n\n v2 = strlen(base);\n if ( v2 != (unsigned int)strlen(a2) )\n return 0LL;\n qsort(base, v2, 1uLL, compar);\n qsort(a2, v2, 1uLL, compar);\n if ( v2 > 0 )\n {\n for ( i = 0LL; base[i] == a2[i]; ++i )\n {\n if ( i == v2 - 1 )\n return 1LL;\n }\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1310(char *base, char *a2) {\n int v2;\n long long i;\n v2 = strlen(base);\n if (v2 != (unsigned int)strlen(a2)) return 0LL;\n qsort(base, v2, 1uLL, compar);\n qsort(a2, v2, 1uLL, compar);\n if (v2 > 0) {\n for (i = 0LL; base[i] == a2[i]; ++i) {\n if (i == v2 - 1) return 1LL;\n }\n return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(char *base, char *a2) {\n int v2;\n long long i;\n v2 = strlen(base);\n if (v2 != (unsigned int)strlen(a2)) return 0LL;\n qsort(base, v2, 1uLL, compare_chars);\n qsort(a2, v2, 1uLL, compare_chars);\n if (v2 > 0) {\n for (i = 0LL; base[i] == a2[i]; ++i) {\n if (i == v2 - 1) return 1LL;\n }\n return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": 532, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\nint compare_chars(const void* a, const void* b) {\n\n char arg1 = *(const char*)a;\n\n char arg2 = *(const char*)b;\n\n if (arg1 < arg2) return -1;\n\n if (arg1 > arg2) return 1;\n\n return 0;\n\n}\n\n\n\n", + "func": "int func0(char *str1, char *str2) {\n int n1 = strlen(str1);\n int n2 = strlen(str2);\n if (n1 != n2) {\n return 0;\n }\n qsort(str1, n1, sizeof(char), compare_chars);\n qsort(str2, n2, sizeof(char), compare_chars);\n for (int i = 0; i < n1; i++) {\n if (str1[i] != str2[i]) {\n return 0;\n }\n }\n return 1;\n}", + "test": "int main() {\n\n char str1[] = \"abc\";\n\n char str2[] = \"cba\";\n\n char str3[] = \"test\";\n\n char str4[] = \"ttew\";\n\n char str5[] = \"xxyz\";\n\n char str6[] = \"yxzx\";\n\n \n\n assert(func0(str1, str2) == 1);\n\n assert(func0(str3, str4) == 0);\n\n assert(func0(str5, str6) == 1);\n\n\n\n printf(\"All tests passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\nmov %rsi,%rbp\npush %rbx\nmov %rdi,%rbx\nsub $0x8,%rsp\ncallq 10b0 \nmov %rbp,%rdi\nmov %rax,%r12\ncallq 10b0 \ncmp %eax,%r12d\nje 1350 \nadd $0x8,%rsp\nxor %eax,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopw %cs:0x0(%rax,%rax,1)\nmovslq %r12d,%r13\nlea -0x6a(%rip),%rcx\nmov $0x1,%edx\nmov %rbx,%rdi\nmov %r13,%rsi\ncallq 10a0 \nmov $0x1,%edx\nmov %r13,%rsi\nmov %rbp,%rdi\nlea -0x8c(%rip),%rcx\ncallq 10a0 \ntest %r12d,%r12d\njle 13b0 \nlea -0x1(%r12),%ecx\nxor %eax,%eax\njmp 139c \nlea 0x1(%rax),%rdx\ncmp %rcx,%rax\nje 13b0 \nmov %rdx,%rax\nmovzbl 0x0(%rbp,%rax,1),%esi\ncmp %sil,(%rbx,%rax,1)\nje 1390 \njmp 1339 \nnopl 0x0(%rax)\nadd $0x8,%rsp\nmov $0x1,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\nmov rbp, rsi\npush rbx\nmov rbx, rdi\ncall _strlen\nmov rdi, rbp; s\nmov r12, rax\ncall _strlen\ncmp r12d, eax\njz short loc_1348\nloc_1337:\npop rbx\nxor eax, eax\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1348:\nmovsxd r13, r12d\nlea r14, compare_chars\nmov edx, 1; size\nmov rdi, rbx; base\nmov rcx, r14; compar\nmov rsi, r13; nmemb\ncall _qsort\nmov rcx, r14; compar\nmov edx, 1; size\nmov rsi, r13; nmemb\nmov rdi, rbp; base\ncall _qsort\ntest r12d, r12d\njle short loc_13B0\nlea ecx, [r12-1]\nxor eax, eax\njmp short loc_139C\nloc_1390:\nlea rdx, [rax+1]\ncmp rax, rcx\njz short loc_13B0\nmov rax, rdx\nloc_139C:\nmovzx esi, byte ptr [rbp+rax+0]\ncmp [rbx+rax], sil\njz short loc_1390\njmp short loc_1337\nloc_13B0:\npop rbx\nmov eax, 1\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "__int64 __fastcall func0(char *base, char *a2)\n{\n int v2; // r12d\n __int64 i; // rax\n\n v2 = strlen(base);\n if ( v2 != (unsigned int)strlen(a2) )\n return 0LL;\n qsort(base, v2, 1uLL, compare_chars);\n qsort(a2, v2, 1uLL, compare_chars);\n if ( v2 > 0 )\n {\n for ( i = 0LL; base[i] == a2[i]; ++i )\n {\n if ( i == v2 - 1 )\n return 1LL;\n }\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1310:\nendbr64\npush r14\npush r13\npush r12\npush rbp\nmov rbp, rsi\npush rbx\nmov rbx, rdi\ncall _strlen\nmov rdi, rbp; s\nmov r12, rax\ncall _strlen\ncmp r12d, eax\njz short loc_1348\nloc_1337:\npop rbx\nxor eax, eax\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1348:\nmovsxd r13, r12d\nlea r14, compar\nmov edx, 1; size\nmov rdi, rbx; base\nmov rcx, r14; compar\nmov rsi, r13; nmemb\ncall _qsort\nmov rcx, r14; compar\nmov edx, 1; size\nmov rsi, r13; nmemb\nmov rdi, rbp; base\ncall _qsort\ntest r12d, r12d\njle short loc_13B0\nlea ecx, [r12-1]\nxor eax, eax\njmp short loc_139C\nloc_1390:\nlea rdx, [rax+1]\ncmp rax, rcx\njz short loc_13B0\nmov rax, rdx\nloc_139C:\nmovzx esi, byte ptr [rbp+rax+0]\ncmp [rbx+rax], sil\njz short loc_1390\njmp short loc_1337\nloc_13B0:\npop rbx\nmov eax, 1\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1310(char *base, char *a2)\n{\n int v2; // r12d\n __int64 i; // rax\n\n v2 = strlen(base);\n if ( v2 != (unsigned int)strlen(a2) )\n return 0LL;\n qsort(base, v2, 1uLL, compar);\n qsort(a2, v2, 1uLL, compar);\n if ( v2 > 0 )\n {\n for ( i = 0LL; base[i] == a2[i]; ++i )\n {\n if ( i == v2 - 1 )\n return 1LL;\n }\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1310(char *base, char *a2) {\n int v2;\n long long i;\n v2 = strlen(base);\n if (v2 != (unsigned int)strlen(a2)) return 0LL;\n qsort(base, v2, 1uLL, compar);\n qsort(a2, v2, 1uLL, compar);\n if (v2 > 0) {\n for (i = 0LL; base[i] == a2[i]; ++i) {\n if (i == v2 - 1) return 1LL;\n }\n return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(char *base, char *a2) {\n int v2;\n long long i;\n v2 = strlen(base);\n if (v2 != (unsigned int)strlen(a2)) return 0LL;\n qsort(base, v2, 1uLL, compare_chars);\n qsort(a2, v2, 1uLL, compare_chars);\n if (v2 > 0) {\n for (i = 0LL; base[i] == a2[i]; ++i) {\n if (i == v2 - 1) return 1LL;\n }\n return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": 533, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef enum {\n\n INT_TYPE,\n\n FLOAT_TYPE,\n\n STRING_TYPE\n\n} DataType;\n\n\n\ntypedef struct {\n\n DataType type;\n\n union {\n\n int i;\n\n float f;\n\n char* s;\n\n } data;\n\n} Element;\n\n\n\ntypedef struct {\n\n Element* elements;\n\n int size;\n\n} ElementArray;\n\n\n\nElementArray remove_datatype(Element* test_tuple, int size, DataType data_type) {\n\n Element* res = malloc(size * sizeof(Element));\n\n int count = 0;\n\n for(int i = 0; i < size; i++) {\n\n if(test_tuple[i].type != data_type){\n\n res[count++] = test_tuple[i];\n\n }\n\n }\n\n ElementArray result;\n\n result.elements = res;\n\n result.size = count;\n\n return result;\n\n}\n\n\n\n", + "func": "int func0(ElementArray a, ElementArray b) {\n if (a.size != b.size) return 0;\n for (int i = 0; i < a.size; i++) {\n if (a.elements[i].type != b.elements[i].type) return 0;\n switch (a.elements[i].type) {\n case INT_TYPE:\n if (a.elements[i].data.i != b.elements[i].data.i) return 0;\n break;\n case FLOAT_TYPE:\n if (a.elements[i].data.f != b.elements[i].data.f) return 0;\n break;\n case STRING_TYPE:\n if (strcmp(a.elements[i].data.s, b.elements[i].data.s) != 0) return 0;\n break;\n }\n }\n return 1;\n}", + "test": "int main() {\n\n // Test case 1\n\n Element test1[] = {\n\n {INT_TYPE, .data.i = 4},\n\n {INT_TYPE, .data.i = 5},\n\n {INT_TYPE, .data.i = 4},\n\n {FLOAT_TYPE, .data.f = 7.7},\n\n {FLOAT_TYPE, .data.f = 1.2}\n\n };\n\n Element expected1[] = {\n\n {FLOAT_TYPE, .data.f = 7.7},\n\n {FLOAT_TYPE, .data.f = 1.2}\n\n };\n\n ElementArray result1 = remove_datatype(test1, 5, INT_TYPE);\n\n ElementArray expectedArray1;\n\n expectedArray1.elements = expected1;\n\n expectedArray1.size = 2;\n\n assert(func0(result1, expectedArray1));\n\n\n\n // Test case 2\n\n Element test2[] = {\n\n {INT_TYPE, .data.i = 7},\n\n {INT_TYPE, .data.i = 8},\n\n {INT_TYPE, .data.i = 9},\n\n {STRING_TYPE, .data.s = \"SR\"}\n\n };\n\n Element expected2[] = {\n\n {INT_TYPE, .data.i = 7},\n\n {INT_TYPE, .data.i = 8},\n\n {INT_TYPE, .data.i = 9}\n\n };\n\n ElementArray result2 = remove_datatype(test2, 4, STRING_TYPE);\n\n ElementArray expectedArray2;\n\n expectedArray2.elements = expected2;\n\n expectedArray2.size = 3;\n\n assert(func0(result2, expectedArray2));\n\n\n\n // Test case 3\n\n Element test3[] = {\n\n {INT_TYPE, .data.i = 7},\n\n {FLOAT_TYPE, .data.f = 1.1},\n\n {INT_TYPE, .data.i = 2},\n\n {FLOAT_TYPE, .data.f = 2.2}\n\n };\n\n Element expected3[] = {\n\n {INT_TYPE, .data.i = 7},\n\n {INT_TYPE, .data.i = 2}\n\n };\n\n ElementArray result3 = remove_datatype(test3, 4, FLOAT_TYPE);\n\n ElementArray expectedArray3;\n\n expectedArray3.elements = expected3;\n\n expectedArray3.size = 2;\n\n assert(func0(result3, expectedArray3));\n\n\n\n // Free allocated memory\n\n free(result1.elements);\n\n free(result2.elements);\n\n free(result3.elements);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rsi,%rax\nmov %rdi,%r8\nmov %r8,%rsi\nmov %r9,%rdi\nmov %rax,%rdi\nmov %rsi,-0x20(%rbp)\nmov %rdi,-0x18(%rbp)\nmov %rdx,-0x30(%rbp)\nmov %rcx,-0x28(%rbp)\nmov -0x18(%rbp),%edx\nmov -0x28(%rbp),%eax\ncmp %eax,%edx\nje 12bd \nmov $0x0,%eax\njmpq 1402 \nmovl $0x0,-0x4(%rbp)\njmpq 13f1 \nmov -0x20(%rbp),%rax\nmov -0x4(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x4,%rdx\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x30(%rbp),%rax\nmov -0x4(%rbp),%ecx\nmovslq %ecx,%rcx\nshl $0x4,%rcx\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\nje 12fd \nmov $0x0,%eax\njmpq 1402 \nmov -0x20(%rbp),%rax\nmov -0x4(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x4,%rdx\nadd %rdx,%rax\nmov (%rax),%eax\ncmp $0x2,%eax\nje 13a9 \ncmp $0x2,%eax\nja 13ed \ntest %eax,%eax\nje 1330 \ncmp $0x1,%eax\nje 136a \njmpq 13ed \nmov -0x20(%rbp),%rax\nmov -0x4(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x4,%rdx\nadd %rdx,%rax\nmov 0x8(%rax),%edx\nmov -0x30(%rbp),%rax\nmov -0x4(%rbp),%ecx\nmovslq %ecx,%rcx\nshl $0x4,%rcx\nadd %rcx,%rax\nmov 0x8(%rax),%eax\ncmp %eax,%edx\nje 13e9 \nmov $0x0,%eax\njmpq 1402 \nmov -0x20(%rbp),%rax\nmov -0x4(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x4,%rdx\nadd %rdx,%rax\nmovss 0x8(%rax),%xmm0\nmov -0x30(%rbp),%rax\nmov -0x4(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x4,%rdx\nadd %rdx,%rax\nmovss 0x8(%rax),%xmm1\nucomiss %xmm1,%xmm0\njp 13a2 \nucomiss %xmm1,%xmm0\njne 13a2 \njmp 13ed \nmov $0x0,%eax\njmp 1402 \nmov -0x30(%rbp),%rax\nmov -0x4(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x4,%rdx\nadd %rdx,%rax\nmov 0x8(%rax),%rdx\nmov -0x20(%rbp),%rax\nmov -0x4(%rbp),%ecx\nmovslq %ecx,%rcx\nshl $0x4,%rcx\nadd %rcx,%rax\nmov 0x8(%rax),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10c0 \ntest %eax,%eax\nje 13ec \nmov $0x0,%eax\njmp 1402 \njmp 13ed \naddl $0x1,-0x4(%rbp)\nmov -0x18(%rbp),%eax\ncmp %eax,-0x4(%rbp)\njl 12c9 \nmov $0x1,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov rax, rdi\nmov r8, rsi\nmov rsi, rax\nmov rdi, rdx\nmov rdi, r8\nmov [rbp+var_20], rsi\nmov [rbp+var_18], rdi\nmov [rbp+var_30], rdx\nmov [rbp+var_28], rcx\nmov edx, dword ptr [rbp+var_18]\nmov eax, dword ptr [rbp+var_28]\ncmp edx, eax\njz short loc_12BD\nmov eax, 0\njmp locret_1403\nloc_12BD:\nmov [rbp+var_4], 0\njmp loc_13F2\nloc_12C9:\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nshl rdx, 4\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_30]\nmov ecx, [rbp+var_4]\nmovsxd rcx, ecx\nshl rcx, 4\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_12FD\nmov eax, 0\njmp locret_1403\nloc_12FD:\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nshl rdx, 4\nadd rax, rdx\nmov eax, [rax]\ncmp eax, 2\njz loc_13A7\ncmp eax, 2\nja loc_13EE\ntest eax, eax\njz short loc_1330\ncmp eax, 1\njz short loc_136A\njmp loc_13EE\nloc_1330:\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nshl rdx, 4\nadd rax, rdx\nmov edx, [rax+8]\nmov rax, [rbp+var_30]\nmov ecx, [rbp+var_4]\nmovsxd rcx, ecx\nshl rcx, 4\nadd rax, rcx\nmov eax, [rax+8]\ncmp edx, eax\njz loc_13E7\nmov eax, 0\njmp locret_1403\nloc_136A:\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nshl rdx, 4\nadd rax, rdx\nmovss xmm0, dword ptr [rax+8]\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nshl rdx, 4\nadd rax, rdx\nmovss xmm1, dword ptr [rax+8]\nucomiss xmm0, xmm1\njp short loc_13A0\nucomiss xmm0, xmm1\njz short loc_13EA\nloc_13A0:\nmov eax, 0\njmp short locret_1403\nloc_13A7:\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nshl rdx, 4\nadd rax, rdx\nmov rdx, [rax+8]\nmov rax, [rbp+var_20]\nmov ecx, [rbp+var_4]\nmovsxd rcx, ecx\nshl rcx, 4\nadd rax, rcx\nmov rax, [rax+8]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_13ED\nmov eax, 0\njmp short locret_1403\nloc_13E7:\nnop\njmp short loc_13EE\nloc_13EA:\nnop\njmp short loc_13EE\nloc_13ED:\nnop\nloc_13EE:\nadd [rbp+var_4], 1\nloc_13F2:\nmov eax, dword ptr [rbp+var_18]\ncmp [rbp+var_4], eax\njl loc_12C9\nmov eax, 1\nlocret_1403:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3, int a4)\n{\n unsigned int v5; // eax\n int i; // [rsp+2Ch] [rbp-4h]\n\n if ( a2 != a4 )\n return 0LL;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(_DWORD *)(16LL * i + a1) != *(_DWORD *)(16LL * i + a3) )\n return 0LL;\n v5 = *(_DWORD *)(16LL * i + a1);\n if ( v5 == 2 )\n {\n if ( strcmp(*(const char **)(16LL * i + a1 + 8), *(const char **)(16LL * i + a3 + 8)) )\n return 0LL;\n }\n else if ( v5 <= 2 )\n {\n if ( v5 )\n {\n if ( *(float *)(16LL * i + a1 + 8) != *(float *)(16LL * i + a3 + 8) )\n return 0LL;\n }\n else if ( *(_DWORD *)(16LL * i + a1 + 8) != *(_DWORD *)(16LL * i + a3 + 8) )\n {\n return 0LL;\n }\n }\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_127E:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov rax, rdi\nmov r8, rsi\nmov rsi, rax\nmov rdi, rdx\nmov rdi, r8\nmov [rbp+var_20], rsi\nmov [rbp+var_18], rdi\nmov [rbp+var_30], rdx\nmov [rbp+var_28], rcx\nmov edx, dword ptr [rbp+var_18]\nmov eax, dword ptr [rbp+var_28]\ncmp edx, eax\njz short loc_12BD\nmov eax, 0\njmp locret_1403\nloc_12BD:\nmov [rbp+var_4], 0\njmp loc_13F2\nloc_12C9:\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nshl rdx, 4\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_30]\nmov ecx, [rbp+var_4]\nmovsxd rcx, ecx\nshl rcx, 4\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_12FD\nmov eax, 0\njmp locret_1403\nloc_12FD:\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nshl rdx, 4\nadd rax, rdx\nmov eax, [rax]\ncmp eax, 2\njz loc_13A7\ncmp eax, 2\nja loc_13EE\ntest eax, eax\njz short loc_1330\ncmp eax, 1\njz short loc_136A\njmp loc_13EE\nloc_1330:\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nshl rdx, 4\nadd rax, rdx\nmov edx, [rax+8]\nmov rax, [rbp+var_30]\nmov ecx, [rbp+var_4]\nmovsxd rcx, ecx\nshl rcx, 4\nadd rax, rcx\nmov eax, [rax+8]\ncmp edx, eax\njz loc_13E7\nmov eax, 0\njmp locret_1403\nloc_136A:\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nshl rdx, 4\nadd rax, rdx\nmovss xmm0, dword ptr [rax+8]\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nshl rdx, 4\nadd rax, rdx\nmovss xmm1, dword ptr [rax+8]\nucomiss xmm0, xmm1\njp short loc_13A0\nucomiss xmm0, xmm1\njz short loc_13EA\nloc_13A0:\nmov eax, 0\njmp short locret_1403\nloc_13A7:\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nshl rdx, 4\nadd rax, rdx\nmov rdx, [rax+8]\nmov rax, [rbp+var_20]\nmov ecx, [rbp+var_4]\nmovsxd rcx, ecx\nshl rcx, 4\nadd rax, rcx\nmov rax, [rax+8]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_13ED\nmov eax, 0\njmp short locret_1403\nloc_13E7:\nnop\njmp short loc_13EE\nloc_13EA:\nnop\njmp short loc_13EE\nloc_13ED:\nnop\nloc_13EE:\nadd [rbp+var_4], 1\nloc_13F2:\nmov eax, dword ptr [rbp+var_18]\ncmp [rbp+var_4], eax\njl loc_12C9\nmov eax, 1\nlocret_1403:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_127E(__int64 a1, int a2, __int64 a3, int a4)\n{\n unsigned int v5; // eax\n int i; // [rsp+2Ch] [rbp-4h]\n\n if ( a2 != a4 )\n return 0LL;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(_DWORD *)(16LL * i + a1) != *(_DWORD *)(16LL * i + a3) )\n return 0LL;\n v5 = *(_DWORD *)(16LL * i + a1);\n if ( v5 == 2 )\n {\n if ( strcmp(*(const char **)(16LL * i + a1 + 8), *(const char **)(16LL * i + a3 + 8)) )\n return 0LL;\n }\n else if ( v5 <= 2 )\n {\n if ( v5 )\n {\n if ( *(float *)(16LL * i + a1 + 8) != *(float *)(16LL * i + a3 + 8) )\n return 0LL;\n }\n else if ( *(_DWORD *)(16LL * i + a1 + 8) != *(_DWORD *)(16LL * i + a3 + 8) )\n {\n return 0LL;\n }\n }\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_127E(long long a1, int a2, long long a3, int a4) {\n unsigned int v5;\n int i;\n if (a2 != a4) return 0LL;\n for (i = 0; i < a2; ++i) {\n if (*(uint32_t *)(16LL * i + a1) != *(uint32_t *)(16LL * i + a3))\n return 0LL;\n v5 = *(uint32_t *)(16LL * i + a1);\n if (v5 == 2) {\n if (strcmp(*(const char **)(16LL * i + a1 + 8),\n *(const char **)(16LL * i + a3 + 8)))\n return 0LL;\n } else if (v5 <= 2) {\n if (v5) {\n if (*(float *)(16LL * i + a1 + 8) != *(float *)(16LL * i + a3 + 8))\n return 0LL;\n } else if (*(uint32_t *)(16LL * i + a1 + 8) !=\n *(uint32_t *)(16LL * i + a3 + 8)) {\n return 0LL;\n }\n }\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3, int a4) {\n unsigned int v5;\n int i;\n if (a2 != a4) return 0LL;\n for (i = 0; i < a2; ++i) {\n if (*(uint32_t *)(16LL * i + a1) != *(uint32_t *)(16LL * i + a3))\n return 0LL;\n v5 = *(uint32_t *)(16LL * i + a1);\n if (v5 == 2) {\n if (strcmp(*(const char **)(16LL * i + a1 + 8),\n *(const char **)(16LL * i + a3 + 8)))\n return 0LL;\n } else if (v5 <= 2) {\n if (v5) {\n if (*(float *)(16LL * i + a1 + 8) != *(float *)(16LL * i + a3 + 8))\n return 0LL;\n } else if (*(uint32_t *)(16LL * i + a1 + 8) !=\n *(uint32_t *)(16LL * i + a3 + 8)) {\n return 0LL;\n }\n }\n }\n return 1LL;\n}" + }, + { + "index": 533, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef enum {\n\n INT_TYPE,\n\n FLOAT_TYPE,\n\n STRING_TYPE\n\n} DataType;\n\n\n\ntypedef struct {\n\n DataType type;\n\n union {\n\n int i;\n\n float f;\n\n char* s;\n\n } data;\n\n} Element;\n\n\n\ntypedef struct {\n\n Element* elements;\n\n int size;\n\n} ElementArray;\n\n\n\nElementArray remove_datatype(Element* test_tuple, int size, DataType data_type) {\n\n Element* res = malloc(size * sizeof(Element));\n\n int count = 0;\n\n for(int i = 0; i < size; i++) {\n\n if(test_tuple[i].type != data_type){\n\n res[count++] = test_tuple[i];\n\n }\n\n }\n\n ElementArray result;\n\n result.elements = res;\n\n result.size = count;\n\n return result;\n\n}\n\n\n\n", + "func": "int func0(ElementArray a, ElementArray b) {\n if (a.size != b.size) return 0;\n for (int i = 0; i < a.size; i++) {\n if (a.elements[i].type != b.elements[i].type) return 0;\n switch (a.elements[i].type) {\n case INT_TYPE:\n if (a.elements[i].data.i != b.elements[i].data.i) return 0;\n break;\n case FLOAT_TYPE:\n if (a.elements[i].data.f != b.elements[i].data.f) return 0;\n break;\n case STRING_TYPE:\n if (strcmp(a.elements[i].data.s, b.elements[i].data.s) != 0) return 0;\n break;\n }\n }\n return 1;\n}", + "test": "int main() {\n\n // Test case 1\n\n Element test1[] = {\n\n {INT_TYPE, .data.i = 4},\n\n {INT_TYPE, .data.i = 5},\n\n {INT_TYPE, .data.i = 4},\n\n {FLOAT_TYPE, .data.f = 7.7},\n\n {FLOAT_TYPE, .data.f = 1.2}\n\n };\n\n Element expected1[] = {\n\n {FLOAT_TYPE, .data.f = 7.7},\n\n {FLOAT_TYPE, .data.f = 1.2}\n\n };\n\n ElementArray result1 = remove_datatype(test1, 5, INT_TYPE);\n\n ElementArray expectedArray1;\n\n expectedArray1.elements = expected1;\n\n expectedArray1.size = 2;\n\n assert(func0(result1, expectedArray1));\n\n\n\n // Test case 2\n\n Element test2[] = {\n\n {INT_TYPE, .data.i = 7},\n\n {INT_TYPE, .data.i = 8},\n\n {INT_TYPE, .data.i = 9},\n\n {STRING_TYPE, .data.s = \"SR\"}\n\n };\n\n Element expected2[] = {\n\n {INT_TYPE, .data.i = 7},\n\n {INT_TYPE, .data.i = 8},\n\n {INT_TYPE, .data.i = 9}\n\n };\n\n ElementArray result2 = remove_datatype(test2, 4, STRING_TYPE);\n\n ElementArray expectedArray2;\n\n expectedArray2.elements = expected2;\n\n expectedArray2.size = 3;\n\n assert(func0(result2, expectedArray2));\n\n\n\n // Test case 3\n\n Element test3[] = {\n\n {INT_TYPE, .data.i = 7},\n\n {FLOAT_TYPE, .data.f = 1.1},\n\n {INT_TYPE, .data.i = 2},\n\n {FLOAT_TYPE, .data.f = 2.2}\n\n };\n\n Element expected3[] = {\n\n {INT_TYPE, .data.i = 7},\n\n {INT_TYPE, .data.i = 2}\n\n };\n\n ElementArray result3 = remove_datatype(test3, 4, FLOAT_TYPE);\n\n ElementArray expectedArray3;\n\n expectedArray3.elements = expected3;\n\n expectedArray3.size = 2;\n\n assert(func0(result3, expectedArray3));\n\n\n\n // Free allocated memory\n\n free(result1.elements);\n\n free(result2.elements);\n\n free(result3.elements);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x0,%eax\ncmp %ecx,%esi\njne 12cc \ntest %esi,%esi\njle 12b5 \npush %r12\npush %rbp\npush %rbx\nlea 0x8(%rdi),%rbx\nlea 0x8(%rdx),%rbp\nlea -0x1(%rsi),%eax\nshl $0x4,%rax\nlea 0x18(%rdi,%rax,1),%r12\njmp 1273 \nmovss (%rbx),%xmm0\nucomiss 0x0(%rbp),%xmm0\njp 12c5 \njne 12c5 \nadd $0x10,%rbx\nadd $0x10,%rbp\ncmp %r12,%rbx\nje 12ae \nmov -0x8(%rbx),%eax\ncmp -0x8(%rbp),%eax\njne 12bb \ncmp $0x1,%eax\nje 125a \ncmp $0x2,%eax\nje 1297 \ntest %eax,%eax\njne 1266 \nmov 0x0(%rbp),%eax\ncmp %eax,(%rbx)\nje 1266 \nmov $0x0,%eax\njmp 12c0 \nmov 0x0(%rbp),%rsi\nmov (%rbx),%rdi\ncallq 10c0 \ntest %eax,%eax\nje 1266 \nmov $0x0,%eax\njmp 12c0 \nmov $0x1,%eax\njmp 12c0 \nmov $0x1,%eax\nretq\nmov $0x0,%eax\npop %rbx\npop %rbp\npop %r12\nretq\nmov $0x0,%eax\njmp 12c0 \nretq\n", + "ida_asm": "func0:\nendbr64\nmov eax, 0\ncmp esi, ecx\njnz locret_12D6\ntest esi, esi\njle short loc_12BF\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nlea rbp, [rdx+8]\nmovsxd rsi, esi\nshl rsi, 4\nlea r12, [rsi+rdi]\njmp short loc_127C\nloc_1262:\nmovss xmm0, dword ptr [rbx+8]\nucomiss xmm0, dword ptr [rbp+0]\njp short loc_12CF\njnz short loc_12CF\nloc_126F:\nadd rbx, 10h\nadd rbp, 10h\ncmp rbx, r12\njz short loc_12B8\nloc_127C:\nmov eax, [rbx]\ncmp eax, [rbp-8]\njnz short loc_12C5\ncmp eax, 1\njz short loc_1262\ncmp eax, 2\njz short loc_12A0\ntest eax, eax\njnz short loc_126F\nmov eax, [rbp+0]\ncmp [rbx+8], eax\njz short loc_126F\nmov eax, 0\njmp short loc_12CA\nloc_12A0:\nmov rsi, [rbp+0]; s2\nmov rdi, [rbx+8]; s1\ncall _strcmp\ntest eax, eax\njz short loc_126F\nmov eax, 0\njmp short loc_12CA\nloc_12B8:\nmov eax, 1\njmp short loc_12CA\nloc_12BF:\nmov eax, 1\nretn\nloc_12C5:\nmov eax, 0\nloc_12CA:\npop rbx\npop rbp\npop r12\nretn\nloc_12CF:\nmov eax, 0\njmp short loc_12CA\nlocret_12D6:\nretn", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2, __int64 a3, int a4)\n{\n __int64 result; // rax\n int *v5; // rbx\n const char **i; // rbp\n float v7; // eax\n\n result = 0LL;\n if ( a2 == a4 )\n {\n if ( a2 <= 0 )\n return 1LL;\n v5 = a1;\n for ( i = (const char **)(a3 + 8); ; i += 2 )\n {\n v7 = *(float *)v5;\n if ( *v5 != *((_DWORD *)i - 2) )\n return 0LL;\n if ( LODWORD(v7) == 1 )\n {\n if ( *((float *)v5 + 2) != *(float *)i )\n return 0LL;\n }\n else if ( LODWORD(v7) == 2 )\n {\n if ( strcmp(*((const char **)v5 + 1), *i) )\n return 0LL;\n }\n else if ( v7 == 0.0 && v5[2] != *(_DWORD *)i )\n {\n return 0LL;\n }\n v5 += 4;\n if ( v5 == &a1[4 * a2] )\n return 1LL;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1235:\nendbr64\nmov eax, 0\ncmp esi, ecx\njnz locret_12D6\ntest esi, esi\njle short loc_12BF\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nlea rbp, [rdx+8]\nmovsxd rsi, esi\nshl rsi, 4\nlea r12, [rsi+rdi]\njmp short loc_127C\nloc_1262:\nmovss xmm0, dword ptr [rbx+8]\nucomiss xmm0, dword ptr [rbp+0]\njp short loc_12CF\njnz short loc_12CF\nloc_126F:\nadd rbx, 10h\nadd rbp, 10h\ncmp rbx, r12\njz short loc_12B8\nloc_127C:\nmov eax, [rbx]\ncmp eax, [rbp-8]\njnz short loc_12C5\ncmp eax, 1\njz short loc_1262\ncmp eax, 2\njz short loc_12A0\ntest eax, eax\njnz short loc_126F\nmov eax, [rbp+0]\ncmp [rbx+8], eax\njz short loc_126F\nmov eax, 0\njmp short loc_12CA\nloc_12A0:\nmov rsi, [rbp+0]; s2\nmov rdi, [rbx+8]; s1\ncall _strcmp\ntest eax, eax\njz short loc_126F\nmov eax, 0\njmp short loc_12CA\nloc_12B8:\nmov eax, 1\njmp short loc_12CA\nloc_12BF:\nmov eax, 1\nretn\nloc_12C5:\nmov eax, 0\nloc_12CA:\npop rbx\npop rbp\npop r12\nretn\nloc_12CF:\nmov eax, 0\njmp short loc_12CA\nlocret_12D6:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1235(int *a1, int a2, __int64 a3, int a4)\n{\n __int64 result; // rax\n int *v5; // rbx\n const char **i; // rbp\n float v7; // eax\n\n result = 0LL;\n if ( a2 == a4 )\n {\n if ( a2 <= 0 )\n return 1LL;\n v5 = a1;\n for ( i = (const char **)(a3 + 8); ; i += 2 )\n {\n v7 = *(float *)v5;\n if ( *v5 != *((_DWORD *)i - 2) )\n return 0LL;\n if ( LODWORD(v7) == 1 )\n {\n if ( *((float *)v5 + 2) != *(float *)i )\n return 0LL;\n }\n else if ( LODWORD(v7) == 2 )\n {\n if ( strcmp(*((const char **)v5 + 1), *i) )\n return 0LL;\n }\n else if ( v7 == 0.0 && v5[2] != *(_DWORD *)i )\n {\n return 0LL;\n }\n v5 += 4;\n if ( v5 == &a1[4 * a2] )\n return 1LL;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1235(int *a1, int a2, long long a3, int a4) {\n long long result;\n int *v5;\n const char **i;\n float v7;\n result = 0LL;\n if (a2 == a4) {\n if (a2 <= 0) return 1LL;\n v5 = a1;\n for (i = (const char **)(a3 + 8);; i += 2) {\n v7 = *(float *)v5;\n if (*v5 != *((uint32_t *)i - 2)) return 0LL;\n if (LODWORD(v7) == 1) {\n if (*((float *)v5 + 2) != *(float *)i) return 0LL;\n } else if (LODWORD(v7) == 2) {\n if (strcmp(*((const char **)v5 + 1), *i)) return 0LL;\n } else if (v7 == 0.0 && v5[2] != *(uint32_t *)i) {\n return 0LL;\n }\n v5 += 4;\n if (v5 == &a1[4 * a2]) return 1LL;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2, long long a3, int a4) {\n long long result;\n int *v5;\n const char **i;\n float v7;\n result = 0LL;\n if (a2 == a4) {\n if (a2 <= 0) return 1LL;\n v5 = a1;\n for (i = (const char **)(a3 + 8);; i += 2) {\n v7 = *(float *)v5;\n if (*v5 != *((uint32_t *)i - 2)) return 0LL;\n if (LODWORD(v7) == 1) {\n if (*((float *)v5 + 2) != *(float *)i) return 0LL;\n } else if (LODWORD(v7) == 2) {\n if (strcmp(*((const char **)v5 + 1), *i)) return 0LL;\n } else if (v7 == 0.0 && v5[2] != *(uint32_t *)i) {\n return 0LL;\n }\n v5 += 4;\n if (v5 == &a1[4 * a2]) return 1LL;\n }\n }\n return result;\n}" + }, + { + "index": 533, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef enum {\n\n INT_TYPE,\n\n FLOAT_TYPE,\n\n STRING_TYPE\n\n} DataType;\n\n\n\ntypedef struct {\n\n DataType type;\n\n union {\n\n int i;\n\n float f;\n\n char* s;\n\n } data;\n\n} Element;\n\n\n\ntypedef struct {\n\n Element* elements;\n\n int size;\n\n} ElementArray;\n\n\n\nElementArray remove_datatype(Element* test_tuple, int size, DataType data_type) {\n\n Element* res = malloc(size * sizeof(Element));\n\n int count = 0;\n\n for(int i = 0; i < size; i++) {\n\n if(test_tuple[i].type != data_type){\n\n res[count++] = test_tuple[i];\n\n }\n\n }\n\n ElementArray result;\n\n result.elements = res;\n\n result.size = count;\n\n return result;\n\n}\n\n\n\n", + "func": "int func0(ElementArray a, ElementArray b) {\n if (a.size != b.size) return 0;\n for (int i = 0; i < a.size; i++) {\n if (a.elements[i].type != b.elements[i].type) return 0;\n switch (a.elements[i].type) {\n case INT_TYPE:\n if (a.elements[i].data.i != b.elements[i].data.i) return 0;\n break;\n case FLOAT_TYPE:\n if (a.elements[i].data.f != b.elements[i].data.f) return 0;\n break;\n case STRING_TYPE:\n if (strcmp(a.elements[i].data.s, b.elements[i].data.s) != 0) return 0;\n break;\n }\n }\n return 1;\n}", + "test": "int main() {\n\n // Test case 1\n\n Element test1[] = {\n\n {INT_TYPE, .data.i = 4},\n\n {INT_TYPE, .data.i = 5},\n\n {INT_TYPE, .data.i = 4},\n\n {FLOAT_TYPE, .data.f = 7.7},\n\n {FLOAT_TYPE, .data.f = 1.2}\n\n };\n\n Element expected1[] = {\n\n {FLOAT_TYPE, .data.f = 7.7},\n\n {FLOAT_TYPE, .data.f = 1.2}\n\n };\n\n ElementArray result1 = remove_datatype(test1, 5, INT_TYPE);\n\n ElementArray expectedArray1;\n\n expectedArray1.elements = expected1;\n\n expectedArray1.size = 2;\n\n assert(func0(result1, expectedArray1));\n\n\n\n // Test case 2\n\n Element test2[] = {\n\n {INT_TYPE, .data.i = 7},\n\n {INT_TYPE, .data.i = 8},\n\n {INT_TYPE, .data.i = 9},\n\n {STRING_TYPE, .data.s = \"SR\"}\n\n };\n\n Element expected2[] = {\n\n {INT_TYPE, .data.i = 7},\n\n {INT_TYPE, .data.i = 8},\n\n {INT_TYPE, .data.i = 9}\n\n };\n\n ElementArray result2 = remove_datatype(test2, 4, STRING_TYPE);\n\n ElementArray expectedArray2;\n\n expectedArray2.elements = expected2;\n\n expectedArray2.size = 3;\n\n assert(func0(result2, expectedArray2));\n\n\n\n // Test case 3\n\n Element test3[] = {\n\n {INT_TYPE, .data.i = 7},\n\n {FLOAT_TYPE, .data.f = 1.1},\n\n {INT_TYPE, .data.i = 2},\n\n {FLOAT_TYPE, .data.f = 2.2}\n\n };\n\n Element expected3[] = {\n\n {INT_TYPE, .data.i = 7},\n\n {INT_TYPE, .data.i = 2}\n\n };\n\n ElementArray result3 = remove_datatype(test3, 4, FLOAT_TYPE);\n\n ElementArray expectedArray3;\n\n expectedArray3.elements = expected3;\n\n expectedArray3.size = 2;\n\n assert(func0(result3, expectedArray3));\n\n\n\n // Free allocated memory\n\n free(result1.elements);\n\n free(result2.elements);\n\n free(result3.elements);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nxor %eax,%eax\ncmp %ecx,%esi\nje 1560 \nretq\nnopl 0x0(%rax,%rax,1)\ntest %esi,%esi\njle 15f9 \nlea -0x1(%rsi),%eax\npush %r12\nshl $0x4,%rax\npush %rbp\nlea 0x8(%rdx),%rbp\npush %rbx\nlea 0x18(%rdi,%rax,1),%r12\nlea 0x8(%rdi),%rbx\njmp 1599 \nnopw 0x0(%rax,%rax,1)\ntest %eax,%eax\nje 15f0 \nadd $0x10,%rbx\nadd $0x10,%rbp\ncmp %r12,%rbx\nje 15e1 \nmov -0x8(%rbx),%eax\ncmp -0x8(%rbp),%eax\njne 15bb \ncmp $0x1,%eax\nje 15c8 \ncmp $0x2,%eax\njne 1588 \nmov 0x0(%rbp),%rsi\nmov (%rbx),%rdi\ncallq 10c0 \ntest %eax,%eax\nje 158c \npop %rbx\nxor %eax,%eax\npop %rbp\npop %r12\nretq\nnopw 0x0(%rax,%rax,1)\nmovss (%rbx),%xmm0\nucomiss 0x0(%rbp),%xmm0\njp 15bb \njne 15bb \nadd $0x10,%rbx\nadd $0x10,%rbp\ncmp %r12,%rbx\njne 1599 \npop %rbx\nmov $0x1,%eax\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax,%rax,1)\nmov 0x0(%rbp),%eax\ncmp %eax,(%rbx)\nje 158c \njmp 15bb \nmov $0x1,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nxor eax, eax\ncmp esi, ecx\njz short loc_1560\nretn\nloc_1560:\ntest esi, esi\njle loc_15EC\nmovsxd rsi, esi\npush r12\nshl rsi, 4\npush rbp\nlea rbp, [rdx+8]\npush rbx\nlea r12, [rsi+rdi]\nmov rbx, rdi\njmp short loc_1599\nloc_1580:\ntest eax, eax\njnz short loc_158C\nmov eax, [rbp+0]\ncmp [rbx+8], eax\njnz short loc_15BB\nloc_158C:\nadd rbx, 10h\nadd rbp, 10h\ncmp rbx, r12\njz short loc_15E2\nloc_1599:\nmov eax, [rbx]\ncmp eax, [rbp-8]\njnz short loc_15BB\ncmp eax, 1\njz short loc_15C8\ncmp eax, 2\njnz short loc_1580\nmov rsi, [rbp+0]; s2\nmov rdi, [rbx+8]; s1\ncall _strcmp\ntest eax, eax\njz short loc_158C\nloc_15BB:\npop rbx\nxor eax, eax\npop rbp\npop r12\nretn\nloc_15C8:\nmovss xmm0, dword ptr [rbx+8]\nucomiss xmm0, dword ptr [rbp+0]\njp short loc_15BB\njnz short loc_15BB\nadd rbx, 10h\nadd rbp, 10h\ncmp rbx, r12\njnz short loc_1599\nloc_15E2:\npop rbx\nmov eax, 1\npop rbp\npop r12\nretn\nloc_15EC:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char **a1, int a2, __int64 a3, int a4)\n{\n __int64 result; // rax\n const char **v5; // rbp\n int *v6; // r12\n const char **v7; // rbx\n int v8; // eax\n\n result = 0LL;\n if ( a2 == a4 )\n {\n if ( a2 <= 0 )\n {\n return 1LL;\n }\n else\n {\n v5 = (const char **)(a3 + 8);\n v6 = (int *)&a1[2 * a2];\n v7 = a1;\n do\n {\n while ( 1 )\n {\n v8 = *(_DWORD *)v7;\n if ( *(_DWORD *)v7 != *((_DWORD *)v5 - 2) )\n return 0LL;\n if ( v8 == 1 )\n break;\n if ( v8 == 2 )\n {\n if ( strcmp(v7[1], *v5) )\n return 0LL;\n }\n else if ( !v8 && *((_DWORD *)v7 + 2) != *(_DWORD *)v5 )\n {\n return 0LL;\n }\n v7 += 2;\n v5 += 2;\n if ( v7 == (const char **)v6 )\n return 1LL;\n }\n if ( *((float *)v7 + 2) != *(float *)v5 )\n return 0LL;\n v7 += 2;\n v5 += 2;\n }\n while ( v7 != (const char **)v6 );\n return 1LL;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1550:\nendbr64\nxor eax, eax\ncmp esi, ecx\njz short loc_1560\nretn\nloc_1560:\ntest esi, esi\njle loc_15EC\nmovsxd rsi, esi\npush r12\nshl rsi, 4\npush rbp\nlea rbp, [rdx+8]\npush rbx\nlea r12, [rsi+rdi]\nmov rbx, rdi\njmp short loc_1599\nloc_1580:\ntest eax, eax\njnz short loc_158C\nmov eax, [rbp+0]\ncmp [rbx+8], eax\njnz short loc_15BB\nloc_158C:\nadd rbx, 10h\nadd rbp, 10h\ncmp rbx, r12\njz short loc_15E2\nloc_1599:\nmov eax, [rbx]\ncmp eax, [rbp-8]\njnz short loc_15BB\ncmp eax, 1\njz short loc_15C8\ncmp eax, 2\njnz short loc_1580\nmov rsi, [rbp+0]; s2\nmov rdi, [rbx+8]; s1\ncall _strcmp\ntest eax, eax\njz short loc_158C\nloc_15BB:\npop rbx\nxor eax, eax\npop rbp\npop r12\nretn\nloc_15C8:\nmovss xmm0, dword ptr [rbx+8]\nucomiss xmm0, dword ptr [rbp+0]\njp short loc_15BB\njnz short loc_15BB\nadd rbx, 10h\nadd rbp, 10h\ncmp rbx, r12\njnz short loc_1599\nloc_15E2:\npop rbx\nmov eax, 1\npop rbp\npop r12\nretn\nloc_15EC:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1550(const char **a1, int a2, __int64 a3, int a4)\n{\n __int64 result; // rax\n const char **v5; // rbp\n int *v6; // r12\n const char **v7; // rbx\n int v8; // eax\n\n result = 0LL;\n if ( a2 == a4 )\n {\n if ( a2 <= 0 )\n {\n return 1LL;\n }\n else\n {\n v5 = (const char **)(a3 + 8);\n v6 = (int *)&a1[2 * a2];\n v7 = a1;\n do\n {\n while ( 1 )\n {\n v8 = *(_DWORD *)v7;\n if ( *(_DWORD *)v7 != *((_DWORD *)v5 - 2) )\n return 0LL;\n if ( v8 == 1 )\n break;\n if ( v8 == 2 )\n {\n if ( strcmp(v7[1], *v5) )\n return 0LL;\n }\n else if ( !v8 && *((_DWORD *)v7 + 2) != *(_DWORD *)v5 )\n {\n return 0LL;\n }\n v7 += 2;\n v5 += 2;\n if ( v7 == (const char **)v6 )\n return 1LL;\n }\n if ( *((float *)v7 + 2) != *(float *)v5 )\n return 0LL;\n v7 += 2;\n v5 += 2;\n }\n while ( v7 != (const char **)v6 );\n return 1LL;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1550(const char **a1, int a2, long long a3, int a4) {\n long long result;\n const char **v5;\n int *v6;\n const char **v7;\n int v8;\n result = 0LL;\n if (a2 == a4) {\n if (a2 <= 0) {\n return 1LL;\n } else {\n v5 = (const char **)(a3 + 8);\n v6 = (int *)&a1[2 * a2];\n v7 = a1;\n do {\n while (1) {\n v8 = *(uint32_t *)v7;\n if (*(uint32_t *)v7 != *((uint32_t *)v5 - 2)) return 0LL;\n if (v8 == 1) break;\n if (v8 == 2) {\n if (strcmp(v7[1], *v5)) return 0LL;\n } else if (!v8 && *((uint32_t *)v7 + 2) != *(uint32_t *)v5) {\n return 0LL;\n }\n v7 += 2;\n v5 += 2;\n if (v7 == (const char **)v6) return 1LL;\n }\n if (*((float *)v7 + 2) != *(float *)v5) return 0LL;\n v7 += 2;\n v5 += 2;\n } while (v7 != (const char **)v6);\n return 1LL;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(const char **a1, int a2, long long a3, int a4) {\n long long result;\n const char **v5;\n int *v6;\n const char **v7;\n int v8;\n result = 0LL;\n if (a2 == a4) {\n if (a2 <= 0) {\n return 1LL;\n } else {\n v5 = (const char **)(a3 + 8);\n v6 = (int *)&a1[2 * a2];\n v7 = a1;\n do {\n while (1) {\n v8 = *(uint32_t *)v7;\n if (*(uint32_t *)v7 != *((uint32_t *)v5 - 2)) return 0LL;\n if (v8 == 1) break;\n if (v8 == 2) {\n if (strcmp(v7[1], *v5)) return 0LL;\n } else if (!v8 && *((uint32_t *)v7 + 2) != *(uint32_t *)v5) {\n return 0LL;\n }\n v7 += 2;\n v5 += 2;\n if (v7 == (const char **)v6) return 1LL;\n }\n if (*((float *)v7 + 2) != *(float *)v5) return 0LL;\n v7 += 2;\n v5 += 2;\n } while (v7 != (const char **)v6);\n return 1LL;\n }\n }\n return result;\n}" + }, + { + "index": 533, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef enum {\n\n INT_TYPE,\n\n FLOAT_TYPE,\n\n STRING_TYPE\n\n} DataType;\n\n\n\ntypedef struct {\n\n DataType type;\n\n union {\n\n int i;\n\n float f;\n\n char* s;\n\n } data;\n\n} Element;\n\n\n\ntypedef struct {\n\n Element* elements;\n\n int size;\n\n} ElementArray;\n\n\n\nElementArray remove_datatype(Element* test_tuple, int size, DataType data_type) {\n\n Element* res = malloc(size * sizeof(Element));\n\n int count = 0;\n\n for(int i = 0; i < size; i++) {\n\n if(test_tuple[i].type != data_type){\n\n res[count++] = test_tuple[i];\n\n }\n\n }\n\n ElementArray result;\n\n result.elements = res;\n\n result.size = count;\n\n return result;\n\n}\n\n\n\n", + "func": "int func0(ElementArray a, ElementArray b) {\n if (a.size != b.size) return 0;\n for (int i = 0; i < a.size; i++) {\n if (a.elements[i].type != b.elements[i].type) return 0;\n switch (a.elements[i].type) {\n case INT_TYPE:\n if (a.elements[i].data.i != b.elements[i].data.i) return 0;\n break;\n case FLOAT_TYPE:\n if (a.elements[i].data.f != b.elements[i].data.f) return 0;\n break;\n case STRING_TYPE:\n if (strcmp(a.elements[i].data.s, b.elements[i].data.s) != 0) return 0;\n break;\n }\n }\n return 1;\n}", + "test": "int main() {\n\n // Test case 1\n\n Element test1[] = {\n\n {INT_TYPE, .data.i = 4},\n\n {INT_TYPE, .data.i = 5},\n\n {INT_TYPE, .data.i = 4},\n\n {FLOAT_TYPE, .data.f = 7.7},\n\n {FLOAT_TYPE, .data.f = 1.2}\n\n };\n\n Element expected1[] = {\n\n {FLOAT_TYPE, .data.f = 7.7},\n\n {FLOAT_TYPE, .data.f = 1.2}\n\n };\n\n ElementArray result1 = remove_datatype(test1, 5, INT_TYPE);\n\n ElementArray expectedArray1;\n\n expectedArray1.elements = expected1;\n\n expectedArray1.size = 2;\n\n assert(func0(result1, expectedArray1));\n\n\n\n // Test case 2\n\n Element test2[] = {\n\n {INT_TYPE, .data.i = 7},\n\n {INT_TYPE, .data.i = 8},\n\n {INT_TYPE, .data.i = 9},\n\n {STRING_TYPE, .data.s = \"SR\"}\n\n };\n\n Element expected2[] = {\n\n {INT_TYPE, .data.i = 7},\n\n {INT_TYPE, .data.i = 8},\n\n {INT_TYPE, .data.i = 9}\n\n };\n\n ElementArray result2 = remove_datatype(test2, 4, STRING_TYPE);\n\n ElementArray expectedArray2;\n\n expectedArray2.elements = expected2;\n\n expectedArray2.size = 3;\n\n assert(func0(result2, expectedArray2));\n\n\n\n // Test case 3\n\n Element test3[] = {\n\n {INT_TYPE, .data.i = 7},\n\n {FLOAT_TYPE, .data.f = 1.1},\n\n {INT_TYPE, .data.i = 2},\n\n {FLOAT_TYPE, .data.f = 2.2}\n\n };\n\n Element expected3[] = {\n\n {INT_TYPE, .data.i = 7},\n\n {INT_TYPE, .data.i = 2}\n\n };\n\n ElementArray result3 = remove_datatype(test3, 4, FLOAT_TYPE);\n\n ElementArray expectedArray3;\n\n expectedArray3.elements = expected3;\n\n expectedArray3.size = 2;\n\n assert(func0(result3, expectedArray3));\n\n\n\n // Free allocated memory\n\n free(result1.elements);\n\n free(result2.elements);\n\n free(result3.elements);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nxor %eax,%eax\ncmp %ecx,%esi\nje 1560 \nretq\nnopl 0x0(%rax,%rax,1)\ntest %esi,%esi\njle 15f9 \nlea -0x1(%rsi),%eax\npush %r12\nshl $0x4,%rax\npush %rbp\nlea 0x8(%rdx),%rbp\npush %rbx\nlea 0x18(%rdi,%rax,1),%r12\nlea 0x8(%rdi),%rbx\njmp 1599 \nnopw 0x0(%rax,%rax,1)\ntest %eax,%eax\nje 15f0 \nadd $0x10,%rbx\nadd $0x10,%rbp\ncmp %r12,%rbx\nje 15e1 \nmov -0x8(%rbx),%eax\ncmp -0x8(%rbp),%eax\njne 15bb \ncmp $0x1,%eax\nje 15c8 \ncmp $0x2,%eax\njne 1588 \nmov 0x0(%rbp),%rsi\nmov (%rbx),%rdi\ncallq 10c0 \ntest %eax,%eax\nje 158c \npop %rbx\nxor %eax,%eax\npop %rbp\npop %r12\nretq\nnopw 0x0(%rax,%rax,1)\nmovss (%rbx),%xmm0\nucomiss 0x0(%rbp),%xmm0\njp 15bb \njne 15bb \nadd $0x10,%rbx\nadd $0x10,%rbp\ncmp %r12,%rbx\njne 1599 \npop %rbx\nmov $0x1,%eax\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax,%rax,1)\nmov 0x0(%rbp),%eax\ncmp %eax,(%rbx)\nje 158c \njmp 15bb \nmov $0x1,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nxor eax, eax\ncmp esi, ecx\njz short loc_1560\nretn\nloc_1560:\ntest esi, esi\njle loc_15EC\nmovsxd rsi, esi\npush r12\nshl rsi, 4\npush rbp\nlea rbp, [rdx+8]\npush rbx\nlea r12, [rsi+rdi]\nmov rbx, rdi\njmp short loc_1599\nloc_1580:\ntest eax, eax\njnz short loc_158C\nmov eax, [rbp+0]\ncmp [rbx+8], eax\njnz short loc_15BB\nloc_158C:\nadd rbx, 10h\nadd rbp, 10h\ncmp rbx, r12\njz short loc_15E2\nloc_1599:\nmov eax, [rbx]\ncmp eax, [rbp-8]\njnz short loc_15BB\ncmp eax, 1\njz short loc_15C8\ncmp eax, 2\njnz short loc_1580\nmov rsi, [rbp+0]; s2\nmov rdi, [rbx+8]; s1\ncall _strcmp\ntest eax, eax\njz short loc_158C\nloc_15BB:\npop rbx\nxor eax, eax\npop rbp\npop r12\nretn\nloc_15C8:\nmovss xmm0, dword ptr [rbx+8]\nucomiss xmm0, dword ptr [rbp+0]\njp short loc_15BB\njnz short loc_15BB\nadd rbx, 10h\nadd rbp, 10h\ncmp rbx, r12\njnz short loc_1599\nloc_15E2:\npop rbx\nmov eax, 1\npop rbp\npop r12\nretn\nloc_15EC:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char **a1, int a2, __int64 a3, int a4)\n{\n __int64 result; // rax\n const char **v5; // rbp\n int *v6; // r12\n const char **v7; // rbx\n int v8; // eax\n\n result = 0LL;\n if ( a2 == a4 )\n {\n if ( a2 <= 0 )\n {\n return 1LL;\n }\n else\n {\n v5 = (const char **)(a3 + 8);\n v6 = (int *)&a1[2 * a2];\n v7 = a1;\n do\n {\n while ( 1 )\n {\n v8 = *(_DWORD *)v7;\n if ( *(_DWORD *)v7 != *((_DWORD *)v5 - 2) )\n return 0LL;\n if ( v8 == 1 )\n break;\n if ( v8 == 2 )\n {\n if ( strcmp(v7[1], *v5) )\n return 0LL;\n }\n else if ( !v8 && *((_DWORD *)v7 + 2) != *(_DWORD *)v5 )\n {\n return 0LL;\n }\n v7 += 2;\n v5 += 2;\n if ( v7 == (const char **)v6 )\n return 1LL;\n }\n if ( *((float *)v7 + 2) != *(float *)v5 )\n return 0LL;\n v7 += 2;\n v5 += 2;\n }\n while ( v7 != (const char **)v6 );\n return 1LL;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1550:\nendbr64\nxor eax, eax\ncmp esi, ecx\njz short loc_1560\nretn\nloc_1560:\ntest esi, esi\njle loc_15EC\nmovsxd rsi, esi\npush r12\nshl rsi, 4\npush rbp\nlea rbp, [rdx+8]\npush rbx\nlea r12, [rsi+rdi]\nmov rbx, rdi\njmp short loc_1599\nloc_1580:\ntest eax, eax\njnz short loc_158C\nmov eax, [rbp+0]\ncmp [rbx+8], eax\njnz short loc_15BB\nloc_158C:\nadd rbx, 10h\nadd rbp, 10h\ncmp rbx, r12\njz short loc_15E2\nloc_1599:\nmov eax, [rbx]\ncmp eax, [rbp-8]\njnz short loc_15BB\ncmp eax, 1\njz short loc_15C8\ncmp eax, 2\njnz short loc_1580\nmov rsi, [rbp+0]; s2\nmov rdi, [rbx+8]; s1\ncall _strcmp\ntest eax, eax\njz short loc_158C\nloc_15BB:\npop rbx\nxor eax, eax\npop rbp\npop r12\nretn\nloc_15C8:\nmovss xmm0, dword ptr [rbx+8]\nucomiss xmm0, dword ptr [rbp+0]\njp short loc_15BB\njnz short loc_15BB\nadd rbx, 10h\nadd rbp, 10h\ncmp rbx, r12\njnz short loc_1599\nloc_15E2:\npop rbx\nmov eax, 1\npop rbp\npop r12\nretn\nloc_15EC:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1550(const char **a1, int a2, __int64 a3, int a4)\n{\n __int64 result; // rax\n const char **v5; // rbp\n int *v6; // r12\n const char **v7; // rbx\n int v8; // eax\n\n result = 0LL;\n if ( a2 == a4 )\n {\n if ( a2 <= 0 )\n {\n return 1LL;\n }\n else\n {\n v5 = (const char **)(a3 + 8);\n v6 = (int *)&a1[2 * a2];\n v7 = a1;\n do\n {\n while ( 1 )\n {\n v8 = *(_DWORD *)v7;\n if ( *(_DWORD *)v7 != *((_DWORD *)v5 - 2) )\n return 0LL;\n if ( v8 == 1 )\n break;\n if ( v8 == 2 )\n {\n if ( strcmp(v7[1], *v5) )\n return 0LL;\n }\n else if ( !v8 && *((_DWORD *)v7 + 2) != *(_DWORD *)v5 )\n {\n return 0LL;\n }\n v7 += 2;\n v5 += 2;\n if ( v7 == (const char **)v6 )\n return 1LL;\n }\n if ( *((float *)v7 + 2) != *(float *)v5 )\n return 0LL;\n v7 += 2;\n v5 += 2;\n }\n while ( v7 != (const char **)v6 );\n return 1LL;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1550(const char **a1, int a2, long long a3, int a4) {\n long long result;\n const char **v5;\n int *v6;\n const char **v7;\n int v8;\n result = 0LL;\n if (a2 == a4) {\n if (a2 <= 0) {\n return 1LL;\n } else {\n v5 = (const char **)(a3 + 8);\n v6 = (int *)&a1[2 * a2];\n v7 = a1;\n do {\n while (1) {\n v8 = *(uint32_t *)v7;\n if (*(uint32_t *)v7 != *((uint32_t *)v5 - 2)) return 0LL;\n if (v8 == 1) break;\n if (v8 == 2) {\n if (strcmp(v7[1], *v5)) return 0LL;\n } else if (!v8 && *((uint32_t *)v7 + 2) != *(uint32_t *)v5) {\n return 0LL;\n }\n v7 += 2;\n v5 += 2;\n if (v7 == (const char **)v6) return 1LL;\n }\n if (*((float *)v7 + 2) != *(float *)v5) return 0LL;\n v7 += 2;\n v5 += 2;\n } while (v7 != (const char **)v6);\n return 1LL;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(const char **a1, int a2, long long a3, int a4) {\n long long result;\n const char **v5;\n int *v6;\n const char **v7;\n int v8;\n result = 0LL;\n if (a2 == a4) {\n if (a2 <= 0) {\n return 1LL;\n } else {\n v5 = (const char **)(a3 + 8);\n v6 = (int *)&a1[2 * a2];\n v7 = a1;\n do {\n while (1) {\n v8 = *(uint32_t *)v7;\n if (*(uint32_t *)v7 != *((uint32_t *)v5 - 2)) return 0LL;\n if (v8 == 1) break;\n if (v8 == 2) {\n if (strcmp(v7[1], *v5)) return 0LL;\n } else if (!v8 && *((uint32_t *)v7 + 2) != *(uint32_t *)v5) {\n return 0LL;\n }\n v7 += 2;\n v5 += 2;\n if (v7 == (const char **)v6) return 1LL;\n }\n if (*((float *)v7 + 2) != *(float *)v5) return 0LL;\n v7 += 2;\n v5 += 2;\n } while (v7 != (const char **)v6);\n return 1LL;\n }\n }\n return result;\n}" + }, + { + "index": 534, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *pattern, const char *text, int *start, int *end) {\n regex_t regex;\n regmatch_t match;\n int status;\n if (regcomp(®ex, pattern, REG_EXTENDED) != 0) {\n return -1;\n }\n status = regexec(®ex, text, 1, &match, 0);\n regfree(®ex);\n if (status != 0) {\n return -1;\n }\n *start = match.rm_so;\n *end = match.rm_eo;\n return 0;\n}", + "test": "int main() {\n\n int start, end;\n\n\n\n assert(func0(\"python\", \"python programming language\", &start, &end) == 0 && start == 0 && end == 6);\n\n assert(func0(\"programming\", \"python programming language\", &start, &end) == 0 && start == 7 && end == 18);\n\n assert(func0(\"language\", \"python programming language\", &start, &end) == 0 && start == 19 && end == 27);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nadd $0xffffffffffffff80,%rsp\nmov %rdi,-0x68(%rbp)\nmov %rsi,-0x70(%rbp)\nmov %rdx,-0x78(%rbp)\nmov %rcx,-0x80(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmov -0x68(%rbp),%rcx\nlea -0x50(%rbp),%rax\nmov $0x1,%edx\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 10c0 \ntest %eax,%eax\nje 1217 \nmov $0xffffffff,%eax\njmp 126c \nlea -0x58(%rbp),%rdx\nmov -0x70(%rbp),%rsi\nlea -0x50(%rbp),%rax\nmov $0x0,%r8d\nmov %rdx,%rcx\nmov $0x1,%edx\nmov %rax,%rdi\ncallq 10d0 \nmov %eax,-0x5c(%rbp)\nlea -0x50(%rbp),%rax\nmov %rax,%rdi\ncallq 1090 \ncmpl $0x0,-0x5c(%rbp)\nje 1255 \nmov $0xffffffff,%eax\njmp 126c \nmov -0x58(%rbp),%edx\nmov -0x78(%rbp),%rax\nmov %edx,(%rax)\nmov -0x54(%rbp),%edx\nmov -0x80(%rbp),%rax\nmov %edx,(%rax)\nmov $0x0,%eax\nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 1280 \ncallq 10a0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nadd rsp, 0FFFFFFFFFFFFFF80h\nmov [rbp+pattern], rdi\nmov [rbp+string], rsi\nmov [rbp+var_78], rdx\nmov [rbp+var_80], rcx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\ntest eax, eax\njz short loc_1217\nmov eax, 0FFFFFFFFh\njmp short loc_126C\nloc_1217:\nlea rdx, [rbp+pmatch]\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov rcx, rdx; pmatch\nmov edx, 1; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_5C], eax\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\ncmp [rbp+var_5C], 0\njz short loc_1255\nmov eax, 0FFFFFFFFh\njmp short loc_126C\nloc_1255:\nmov edx, [rbp+pmatch.rm_so]\nmov rax, [rbp+var_78]\nmov [rax], edx\nmov edx, [rbp+pmatch.rm_eo]\nmov rax, [rbp+var_80]\nmov [rax], edx\nmov eax, 0\nloc_126C:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1280\ncall ___stack_chk_fail\nlocret_1280:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, const char *a2, regoff_t *a3, regoff_t *a4)\n{\n int v7; // [rsp+24h] [rbp-5Ch]\n regmatch_t pmatch; // [rsp+28h] [rbp-58h] BYREF\n regex_t preg; // [rsp+30h] [rbp-50h] BYREF\n unsigned __int64 v10; // [rsp+78h] [rbp-8h]\n\n v10 = __readfsqword(0x28u);\n if ( regcomp(&preg, a1, 1) )\n return 0xFFFFFFFFLL;\n v7 = regexec(&preg, a2, 1uLL, &pmatch, 0);\n regfree(&preg);\n if ( v7 )\n return 0xFFFFFFFFLL;\n *a3 = pmatch.rm_so;\n *a4 = pmatch.rm_eo;\n return 0LL;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nadd rsp, 0FFFFFFFFFFFFFF80h\nmov [rbp+pattern], rdi\nmov [rbp+string], rsi\nmov [rbp+var_78], rdx\nmov [rbp+var_80], rcx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\ntest eax, eax\njz short loc_1217\nmov eax, 0FFFFFFFFh\njmp short loc_126C\nloc_1217:\nlea rdx, [rbp+pmatch]\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov rcx, rdx; pmatch\nmov edx, 1; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_5C], eax\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\ncmp [rbp+var_5C], 0\njz short loc_1255\nmov eax, 0FFFFFFFFh\njmp short loc_126C\nloc_1255:\nmov edx, [rbp+pmatch.rm_so]\nmov rax, [rbp+var_78]\nmov [rax], edx\nmov edx, [rbp+pmatch.rm_eo]\nmov rax, [rbp+var_80]\nmov [rax], edx\nmov eax, 0\nloc_126C:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1280\ncall ___stack_chk_fail\nlocret_1280:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11C9(const char *a1, const char *a2, regoff_t *a3, regoff_t *a4)\n{\n int v7; // [rsp+24h] [rbp-5Ch]\n regmatch_t pmatch; // [rsp+28h] [rbp-58h] BYREF\n regex_t preg; // [rsp+30h] [rbp-50h] BYREF\n unsigned __int64 v10; // [rsp+78h] [rbp-8h]\n\n v10 = __readfsqword(0x28u);\n if ( regcomp(&preg, a1, 1) )\n return 0xFFFFFFFFLL;\n v7 = regexec(&preg, a2, 1uLL, &pmatch, 0);\n regfree(&preg);\n if ( v7 )\n return 0xFFFFFFFFLL;\n *a3 = pmatch.rm_so;\n *a4 = pmatch.rm_eo;\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11C9(const char *a1, const char *a2, regoff_t *a3, regoff_t *a4) {\n int v7;\n regmatch_t pmatch;\n regex_t preg;\n unsigned long long v10;\n v10 = __readfsqword(40u);\n if (regcomp(&preg, a1, 1)) return 4294967295LL;\n v7 = regexec(&preg, a2, 1uLL, &pmatch, 0);\n regfree(&preg);\n if (v7) return 4294967295LL;\n *a3 = pmatch.rm_so;\n *a4 = pmatch.rm_eo;\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, const char *a2, regoff_t *a3, regoff_t *a4) {\n int v7;\n regmatch_t pmatch;\n regex_t preg;\n unsigned long long v10;\n v10 = __readfsqword(40u);\n if (regcomp(&preg, a1, 1)) return 4294967295LL;\n v7 = regexec(&preg, a2, 1uLL, &pmatch, 0);\n regfree(&preg);\n if (v7) return 4294967295LL;\n *a3 = pmatch.rm_so;\n *a4 = pmatch.rm_eo;\n return 0LL;\n}" + }, + { + "index": 534, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *pattern, const char *text, int *start, int *end) {\n regex_t regex;\n regmatch_t match;\n int status;\n if (regcomp(®ex, pattern, REG_EXTENDED) != 0) {\n return -1;\n }\n status = regexec(®ex, text, 1, &match, 0);\n regfree(®ex);\n if (status != 0) {\n return -1;\n }\n *start = match.rm_so;\n *end = match.rm_eo;\n return 0;\n}", + "test": "int main() {\n\n int start, end;\n\n\n\n assert(func0(\"python\", \"python programming language\", &start, &end) == 0 && start == 0 && end == 6);\n\n assert(func0(\"programming\", \"python programming language\", &start, &end) == 0 && start == 7 && end == 18);\n\n assert(func0(\"language\", \"python programming language\", &start, &end) == 0 && start == 19 && end == 27);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x68,%rsp\nmov %rsi,%rbx\nmov %rdx,%r12\nmov %rcx,%rbp\nmov %fs:0x28,%rax\nmov %rax,0x58(%rsp)\nxor %eax,%eax\nlea 0x10(%rsp),%rax\nmov $0x1,%edx\nmov %rdi,%rsi\nmov %rax,%rdi\ncallq 10c0 \ntest %eax,%eax\njne 1263 \nlea 0x8(%rsp),%rcx\nlea 0x10(%rsp),%r13\nmov $0x0,%r8d\nmov $0x1,%edx\nmov %rbx,%rsi\nmov %r13,%rdi\ncallq 10d0 \nmov %eax,%ebx\nmov %r13,%rdi\ncallq 1090 \ntest %ebx,%ebx\njne 126a \nmov 0x8(%rsp),%eax\nmov %eax,(%r12)\nmov 0xc(%rsp),%eax\nmov %eax,0x0(%rbp)\nmov 0x58(%rsp),%rax\nxor %fs:0x28,%rax\njne 1271 \nmov %ebx,%eax\nadd $0x68,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nmov $0xffffffff,%ebx\njmp 1246 \nmov $0xffffffff,%ebx\njmp 1246 \ncallq 10a0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 68h\nmov rbx, rsi\nmov r12, rdx\nmov rbp, rcx\nmov rax, fs:28h\nmov [rsp+88h+var_30], rax\nxor eax, eax\nlea rax, [rsp+88h+preg]\nmov edx, 1; cflags\nmov rsi, rdi; pattern\nmov rdi, rax; preg\ncall _regcomp\ntest eax, eax\njnz short loc_1263\nlea rcx, [rsp+88h+pmatch]; pmatch\nlea r13, [rsp+88h+preg]\nmov r8d, 0; eflags\nmov edx, 1; nmatch\nmov rsi, rbx; string\nmov rdi, r13; preg\ncall _regexec\nmov ebx, eax\nmov rdi, r13; preg\ncall _regfree\ntest ebx, ebx\njnz short loc_126A\nmov eax, [rsp+88h+pmatch.rm_so]\nmov [r12], eax\nmov eax, [rsp+88h+pmatch.rm_eo]\nmov [rbp+0], eax\nloc_1246:\nmov rax, [rsp+88h+var_30]\nsub rax, fs:28h\njnz short loc_1271\nmov eax, ebx\nadd rsp, 68h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1263:\nmov ebx, 0FFFFFFFFh\njmp short loc_1246\nloc_126A:\nmov ebx, 0FFFFFFFFh\njmp short loc_1246\nloc_1271:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(char *pattern, char *string, regoff_t *a3, regoff_t *a4)\n{\n unsigned int v6; // ebx\n regmatch_t pmatch; // [rsp+8h] [rbp-80h] BYREF\n regex_t preg; // [rsp+10h] [rbp-78h] BYREF\n unsigned __int64 v10; // [rsp+58h] [rbp-30h]\n\n v10 = __readfsqword(0x28u);\n if ( regcomp(&preg, pattern, 1) )\n {\n return (unsigned int)-1;\n }\n else\n {\n v6 = regexec(&preg, string, 1uLL, &pmatch, 0);\n regfree(&preg);\n if ( v6 )\n {\n return (unsigned int)-1;\n }\n else\n {\n *a3 = pmatch.rm_so;\n *a4 = pmatch.rm_eo;\n }\n }\n return v6;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 68h\nmov rbx, rsi\nmov r12, rdx\nmov rbp, rcx\nmov rax, fs:28h\nmov [rsp+88h+var_30], rax\nxor eax, eax\nlea rax, [rsp+88h+preg]\nmov edx, 1; cflags\nmov rsi, rdi; pattern\nmov rdi, rax; preg\ncall _regcomp\ntest eax, eax\njnz short loc_1263\nlea rcx, [rsp+88h+pmatch]; pmatch\nlea r13, [rsp+88h+preg]\nmov r8d, 0; eflags\nmov edx, 1; nmatch\nmov rsi, rbx; string\nmov rdi, r13; preg\ncall _regexec\nmov ebx, eax\nmov rdi, r13; preg\ncall _regfree\ntest ebx, ebx\njnz short loc_126A\nmov eax, [rsp+88h+pmatch.rm_so]\nmov [r12], eax\nmov eax, [rsp+88h+pmatch.rm_eo]\nmov [rbp+0], eax\nloc_1246:\nmov rax, [rsp+88h+var_30]\nsub rax, fs:28h\njnz short loc_1271\nmov eax, ebx\nadd rsp, 68h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1263:\nmov ebx, 0FFFFFFFFh\njmp short loc_1246\nloc_126A:\nmov ebx, 0FFFFFFFFh\njmp short loc_1246\nloc_1271:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_11C9(char *pattern, char *string, regoff_t *a3, regoff_t *a4)\n{\n unsigned int v6; // ebx\n regmatch_t pmatch; // [rsp+8h] [rbp-80h] BYREF\n regex_t preg; // [rsp+10h] [rbp-78h] BYREF\n unsigned __int64 v10; // [rsp+58h] [rbp-30h]\n\n v10 = __readfsqword(0x28u);\n if ( regcomp(&preg, pattern, 1) )\n {\n return (unsigned int)-1;\n }\n else\n {\n v6 = regexec(&preg, string, 1uLL, &pmatch, 0);\n regfree(&preg);\n if ( v6 )\n {\n return (unsigned int)-1;\n }\n else\n {\n *a3 = pmatch.rm_so;\n *a4 = pmatch.rm_eo;\n }\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11C9(char *pattern, char *string, regoff_t *a3, regoff_t *a4) {\n unsigned int v6;\n regmatch_t pmatch;\n regex_t preg;\n unsigned long long v10;\n v10 = __readfsqword(40u);\n if (regcomp(&preg, pattern, 1)) {\n return (unsigned int)-1;\n } else {\n v6 = regexec(&preg, string, 1uLL, &pmatch, 0);\n regfree(&preg);\n if (v6) {\n return (unsigned int)-1;\n } else {\n *a3 = pmatch.rm_so;\n *a4 = pmatch.rm_eo;\n }\n }\n return v6;\n}", + "ida_pseudo_norm": "long long func0(char *pattern, char *string, regoff_t *a3, regoff_t *a4) {\n unsigned int v6;\n regmatch_t pmatch;\n regex_t preg;\n unsigned long long v10;\n v10 = __readfsqword(40u);\n if (regcomp(&preg, pattern, 1)) {\n return (unsigned int)-1;\n } else {\n v6 = regexec(&preg, string, 1uLL, &pmatch, 0);\n regfree(&preg);\n if (v6) {\n return (unsigned int)-1;\n } else {\n *a3 = pmatch.rm_so;\n *a4 = pmatch.rm_eo;\n }\n }\n return v6;\n}" + }, + { + "index": 534, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *pattern, const char *text, int *start, int *end) {\n regex_t regex;\n regmatch_t match;\n int status;\n if (regcomp(®ex, pattern, REG_EXTENDED) != 0) {\n return -1;\n }\n status = regexec(®ex, text, 1, &match, 0);\n regfree(®ex);\n if (status != 0) {\n return -1;\n }\n *start = match.rm_so;\n *end = match.rm_eo;\n return 0;\n}", + "test": "int main() {\n\n int start, end;\n\n\n\n assert(func0(\"python\", \"python programming language\", &start, &end) == 0 && start == 0 && end == 6);\n\n assert(func0(\"programming\", \"python programming language\", &start, &end) == 0 && start == 7 && end == 18);\n\n assert(func0(\"language\", \"python programming language\", &start, &end) == 0 && start == 19 && end == 27);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\nmov %rsi,%r12\nmov %rdi,%rsi\npush %rbp\nmov %rdx,%rbp\nmov $0x1,%edx\npush %rbx\nmov %rcx,%rbx\nsub $0x68,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x58(%rsp)\nxor %eax,%eax\nlea 0x10(%rsp),%r13\nmov %r13,%rdi\ncallq 10c0 \ntest %eax,%eax\njne 1398 \nxor %r8d,%r8d\nmov %r12,%rsi\nmov %r13,%rdi\nmov $0x1,%edx\nlea 0x8(%rsp),%rcx\ncallq 10d0 \nmov %r13,%rdi\nmov %eax,%r12d\ncallq 1090 \ntest %r12d,%r12d\njne 1398 \nmov 0x8(%rsp),%eax\nmov %eax,0x0(%rbp)\nmov 0xc(%rsp),%eax\nmov %eax,(%rbx)\nmov 0x58(%rsp),%rax\nxor %fs:0x28,%rax\njne 13a0 \nadd $0x68,%rsp\nmov %r12d,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax,%rax,1)\nmov $0xffffffff,%r12d\njmp 1375 \ncallq 10a0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\nmov r12, rdx\nmov edx, 1; cflags\npush rbp\nmov rbp, rcx\npush rbx\nmov rbx, rsi\nmov rsi, rdi; pattern\nsub rsp, 68h\nmov rax, fs:28h\nmov [rsp+88h+var_30], rax\nxor eax, eax\nlea r13, [rsp+88h+preg]\nmov rdi, r13; preg\ncall _regcomp\ntest eax, eax\njnz short loc_1388\nxor r8d, r8d; eflags\nmov rsi, rbx; string\nmov rdi, r13; preg\nmov edx, 1; nmatch\nlea rcx, [rsp+88h+pmatch]; pmatch\ncall _regexec\nmov rdi, r13; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\njnz short loc_1388\nmov eax, [rsp+88h+pmatch.rm_so]\nmov [r12], eax\nmov eax, [rsp+88h+pmatch.rm_eo]\nmov [rbp+0], eax\nloc_1365:\nmov rax, [rsp+88h+var_30]\nsub rax, fs:28h\njnz short loc_138F\nadd rsp, 68h\nmov eax, ebx\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1388:\nmov ebx, 0FFFFFFFFh\njmp short loc_1365\nloc_138F:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(char *pattern, char *string, regoff_t *a3, regoff_t *a4)\n{\n unsigned int v6; // ebx\n regmatch_t pmatch; // [rsp+8h] [rbp-80h] BYREF\n regex_t preg; // [rsp+10h] [rbp-78h] BYREF\n unsigned __int64 v10; // [rsp+58h] [rbp-30h]\n\n v10 = __readfsqword(0x28u);\n if ( regcomp(&preg, pattern, 1) )\n return (unsigned int)-1;\n v6 = regexec(&preg, string, 1uLL, &pmatch, 0);\n regfree(&preg);\n if ( v6 )\n {\n return (unsigned int)-1;\n }\n else\n {\n *a3 = pmatch.rm_so;\n *a4 = pmatch.rm_eo;\n }\n return v6;\n}", + "ida_strip_asm": "sub_12F0:\nendbr64\npush r13\npush r12\nmov r12, rdx\nmov edx, 1; cflags\npush rbp\nmov rbp, rcx\npush rbx\nmov rbx, rsi\nmov rsi, rdi; pattern\nsub rsp, 68h\nmov rax, fs:28h\nmov [rsp+88h+var_30], rax\nxor eax, eax\nlea r13, [rsp+88h+preg]\nmov rdi, r13; preg\ncall _regcomp\ntest eax, eax\njnz short loc_1388\nxor r8d, r8d; eflags\nmov rsi, rbx; string\nmov rdi, r13; preg\nmov edx, 1; nmatch\nlea rcx, [rsp+88h+pmatch]; pmatch\ncall _regexec\nmov rdi, r13; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\njnz short loc_1388\nmov eax, [rsp+88h+pmatch.rm_so]\nmov [r12], eax\nmov eax, [rsp+88h+pmatch.rm_eo]\nmov [rbp+0], eax\nloc_1365:\nmov rax, [rsp+88h+var_30]\nsub rax, fs:28h\njnz short loc_138F\nadd rsp, 68h\nmov eax, ebx\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1388:\nmov ebx, 0FFFFFFFFh\njmp short loc_1365\nloc_138F:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12F0(char *pattern, char *string, regoff_t *a3, regoff_t *a4)\n{\n unsigned int v6; // ebx\n regmatch_t pmatch; // [rsp+8h] [rbp-80h] BYREF\n regex_t preg; // [rsp+10h] [rbp-78h] BYREF\n unsigned __int64 v10; // [rsp+58h] [rbp-30h]\n\n v10 = __readfsqword(0x28u);\n if ( regcomp(&preg, pattern, 1) )\n return (unsigned int)-1;\n v6 = regexec(&preg, string, 1uLL, &pmatch, 0);\n regfree(&preg);\n if ( v6 )\n {\n return (unsigned int)-1;\n }\n else\n {\n *a3 = pmatch.rm_so;\n *a4 = pmatch.rm_eo;\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12F0(char *pattern, char *string, regoff_t *a3, regoff_t *a4) {\n unsigned int v6;\n regmatch_t pmatch;\n regex_t preg;\n unsigned long long v10;\n v10 = __readfsqword(40u);\n if (regcomp(&preg, pattern, 1)) return (unsigned int)-1;\n v6 = regexec(&preg, string, 1uLL, &pmatch, 0);\n regfree(&preg);\n if (v6) {\n return (unsigned int)-1;\n } else {\n *a3 = pmatch.rm_so;\n *a4 = pmatch.rm_eo;\n }\n return v6;\n}", + "ida_pseudo_norm": "long long func0(char *pattern, char *string, regoff_t *a3, regoff_t *a4) {\n unsigned int v6;\n regmatch_t pmatch;\n regex_t preg;\n unsigned long long v10;\n v10 = __readfsqword(40u);\n if (regcomp(&preg, pattern, 1)) return (unsigned int)-1;\n v6 = regexec(&preg, string, 1uLL, &pmatch, 0);\n regfree(&preg);\n if (v6) {\n return (unsigned int)-1;\n } else {\n *a3 = pmatch.rm_so;\n *a4 = pmatch.rm_eo;\n }\n return v6;\n}" + }, + { + "index": 534, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *pattern, const char *text, int *start, int *end) {\n regex_t regex;\n regmatch_t match;\n int status;\n if (regcomp(®ex, pattern, REG_EXTENDED) != 0) {\n return -1;\n }\n status = regexec(®ex, text, 1, &match, 0);\n regfree(®ex);\n if (status != 0) {\n return -1;\n }\n *start = match.rm_so;\n *end = match.rm_eo;\n return 0;\n}", + "test": "int main() {\n\n int start, end;\n\n\n\n assert(func0(\"python\", \"python programming language\", &start, &end) == 0 && start == 0 && end == 6);\n\n assert(func0(\"programming\", \"python programming language\", &start, &end) == 0 && start == 7 && end == 18);\n\n assert(func0(\"language\", \"python programming language\", &start, &end) == 0 && start == 19 && end == 27);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\nmov %rsi,%r12\nmov %rdi,%rsi\npush %rbp\nmov %rdx,%rbp\nmov $0x1,%edx\npush %rbx\nmov %rcx,%rbx\nsub $0x68,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x58(%rsp)\nxor %eax,%eax\nlea 0x10(%rsp),%r13\nmov %r13,%rdi\ncallq 10c0 \ntest %eax,%eax\njne 1398 \nxor %r8d,%r8d\nmov %r12,%rsi\nmov %r13,%rdi\nmov $0x1,%edx\nlea 0x8(%rsp),%rcx\ncallq 10d0 \nmov %r13,%rdi\nmov %eax,%r12d\ncallq 1090 \ntest %r12d,%r12d\njne 1398 \nmov 0x8(%rsp),%eax\nmov %eax,0x0(%rbp)\nmov 0xc(%rsp),%eax\nmov %eax,(%rbx)\nmov 0x58(%rsp),%rax\nxor %fs:0x28,%rax\njne 13a0 \nadd $0x68,%rsp\nmov %r12d,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax,%rax,1)\nmov $0xffffffff,%r12d\njmp 1375 \ncallq 10a0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\nmov r12, rdx\nmov edx, 1; cflags\npush rbp\nmov rbp, rcx\npush rbx\nmov rbx, rsi\nmov rsi, rdi; pattern\nsub rsp, 68h\nmov rax, fs:28h\nmov [rsp+88h+var_30], rax\nxor eax, eax\nlea r13, [rsp+88h+preg]\nmov rdi, r13; preg\ncall _regcomp\ntest eax, eax\njnz short loc_1388\nxor r8d, r8d; eflags\nmov rsi, rbx; string\nmov rdi, r13; preg\nmov edx, 1; nmatch\nlea rcx, [rsp+88h+pmatch]; pmatch\ncall _regexec\nmov rdi, r13; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\njnz short loc_1388\nmov eax, [rsp+88h+pmatch.rm_so]\nmov [r12], eax\nmov eax, [rsp+88h+pmatch.rm_eo]\nmov [rbp+0], eax\nloc_1365:\nmov rax, [rsp+88h+var_30]\nsub rax, fs:28h\njnz short loc_138F\nadd rsp, 68h\nmov eax, ebx\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1388:\nmov ebx, 0FFFFFFFFh\njmp short loc_1365\nloc_138F:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(char *pattern, char *string, regoff_t *a3, regoff_t *a4)\n{\n unsigned int v6; // ebx\n regmatch_t pmatch; // [rsp+8h] [rbp-80h] BYREF\n regex_t preg; // [rsp+10h] [rbp-78h] BYREF\n unsigned __int64 v10; // [rsp+58h] [rbp-30h]\n\n v10 = __readfsqword(0x28u);\n if ( regcomp(&preg, pattern, 1) )\n return (unsigned int)-1;\n v6 = regexec(&preg, string, 1uLL, &pmatch, 0);\n regfree(&preg);\n if ( v6 )\n {\n return (unsigned int)-1;\n }\n else\n {\n *a3 = pmatch.rm_so;\n *a4 = pmatch.rm_eo;\n }\n return v6;\n}", + "ida_strip_asm": "sub_12F0:\nendbr64\npush r13\npush r12\nmov r12, rdx\nmov edx, 1; cflags\npush rbp\nmov rbp, rcx\npush rbx\nmov rbx, rsi\nmov rsi, rdi; pattern\nsub rsp, 68h\nmov rax, fs:28h\nmov [rsp+88h+var_30], rax\nxor eax, eax\nlea r13, [rsp+88h+preg]\nmov rdi, r13; preg\ncall _regcomp\ntest eax, eax\njnz short loc_1388\nxor r8d, r8d; eflags\nmov rsi, rbx; string\nmov rdi, r13; preg\nmov edx, 1; nmatch\nlea rcx, [rsp+88h+pmatch]; pmatch\ncall _regexec\nmov rdi, r13; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\njnz short loc_1388\nmov eax, [rsp+88h+pmatch.rm_so]\nmov [r12], eax\nmov eax, [rsp+88h+pmatch.rm_eo]\nmov [rbp+0], eax\nloc_1365:\nmov rax, [rsp+88h+var_30]\nsub rax, fs:28h\njnz short loc_138F\nadd rsp, 68h\nmov eax, ebx\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1388:\nmov ebx, 0FFFFFFFFh\njmp short loc_1365\nloc_138F:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12F0(char *pattern, char *string, regoff_t *a3, regoff_t *a4)\n{\n unsigned int v6; // ebx\n regmatch_t pmatch; // [rsp+8h] [rbp-80h] BYREF\n regex_t preg; // [rsp+10h] [rbp-78h] BYREF\n unsigned __int64 v10; // [rsp+58h] [rbp-30h]\n\n v10 = __readfsqword(0x28u);\n if ( regcomp(&preg, pattern, 1) )\n return (unsigned int)-1;\n v6 = regexec(&preg, string, 1uLL, &pmatch, 0);\n regfree(&preg);\n if ( v6 )\n {\n return (unsigned int)-1;\n }\n else\n {\n *a3 = pmatch.rm_so;\n *a4 = pmatch.rm_eo;\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12F0(char *pattern, char *string, regoff_t *a3, regoff_t *a4) {\n unsigned int v6;\n regmatch_t pmatch;\n regex_t preg;\n unsigned long long v10;\n v10 = __readfsqword(40u);\n if (regcomp(&preg, pattern, 1)) return (unsigned int)-1;\n v6 = regexec(&preg, string, 1uLL, &pmatch, 0);\n regfree(&preg);\n if (v6) {\n return (unsigned int)-1;\n } else {\n *a3 = pmatch.rm_so;\n *a4 = pmatch.rm_eo;\n }\n return v6;\n}", + "ida_pseudo_norm": "long long func0(char *pattern, char *string, regoff_t *a3, regoff_t *a4) {\n unsigned int v6;\n regmatch_t pmatch;\n regex_t preg;\n unsigned long long v10;\n v10 = __readfsqword(40u);\n if (regcomp(&preg, pattern, 1)) return (unsigned int)-1;\n v6 = regexec(&preg, string, 1uLL, &pmatch, 0);\n regfree(&preg);\n if (v6) {\n return (unsigned int)-1;\n } else {\n *a3 = pmatch.rm_so;\n *a4 = pmatch.rm_eo;\n }\n return v6;\n}" + }, + { + "index": 535, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "double func0(double r) { return 3.1415 * r * r; }", + "test": "int main() {\n\n assert(func0(10) == 314.15000000000003);\n\n assert(func0(5) == 78.53750000000001);\n\n assert(func0(4) == 50.264);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmovsd %xmm0,-0x8(%rbp)\nmovsd -0x8(%rbp),%xmm1\nmovsd 0xf3d(%rip),%xmm0\nmulsd %xmm1,%xmm0\nmulsd -0x8(%rbp),%xmm0\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmovsd [rbp+var_8], xmm0\nmovsd xmm1, [rbp+var_8]\nmovsd xmm0, cs:qword_2080\nmulsd xmm0, xmm1\nmulsd xmm0, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "double __fastcall func0(double a1)\n{\n return 3.1415 * a1 * a1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmovsd [rbp+var_8], xmm0\nmovsd xmm1, [rbp+var_8]\nmovsd xmm0, cs:qword_2080\nmulsd xmm0, xmm1\nmulsd xmm0, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "double __fastcall sub_1149(double a1)\n{\n return 3.1415 * a1 * a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1149(double a1) { return 3.1415 * a1 * a1; }", + "ida_pseudo_norm": "double func0(double a1) { return 3.1415 * a1 * a1; }" + }, + { + "index": 536, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "void func0(int* input_list, int list_size, int n, int* output_list,\n int* output_size) {\n int j = 0;\n for (int i = 0; i < list_size; i += n) {\n output_list[j++] = input_list[i];\n }\n *output_size = j;\n}", + "test": "int main() {\n\n int output_list[5];\n\n int output_size;\n\n\n\n int list1[] = {1, 2, 3, 4, 5, 6, 7, 8, 9};\n\n int expected1[] = {1, 3, 5, 7, 9};\n\n func0(list1, 9, 2, output_list, &output_size);\n\n assert(output_size == 5);\n\n for (int i = 0; i < output_size; i++) {\n\n assert(output_list[i] == expected1[i]);\n\n }\n\n\n\n int list2[] = {10, 15, 19, 17, 16, 18};\n\n int expected2[] = {10, 17};\n\n func0(list2, 6, 3, output_list, &output_size);\n\n assert(output_size == 2);\n\n for (int i = 0; i < output_size; i++) {\n\n assert(output_list[i] == expected2[i]);\n\n }\n\n\n\n int list3[] = {14, 16, 19, 15, 17};\n\n int expected3[] = {14, 17};\n\n func0(list3, 5, 4, output_list, &output_size);\n\n assert(output_size == 2);\n\n for (int i = 0; i < output_size; i++) {\n\n assert(output_list[i] == expected3[i]);\n\n }\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmov %rcx,-0x28(%rbp)\nmov %r8,-0x30(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11ec \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x8(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x8(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\nmov -0x20(%rbp),%eax\nadd %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11b3 \nmov -0x30(%rbp),%rax\nmov -0x8(%rbp),%edx\nmov %edx,(%rax)\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_28], rcx\nmov [rbp+var_30], r8\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11EC\nloc_11B3:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_8]\nlea edx, [rax+1]\nmov [rbp+var_8], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nmov eax, [rbp+var_20]\nadd [rbp+var_4], eax\nloc_11EC:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11B3\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_8]\nmov [rax], edx\nnop\npop rbp\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, int a3, __int64 a4, _DWORD *a5)\n{\n int v5; // eax\n _DWORD *result; // rax\n int v7; // [rsp+28h] [rbp-8h]\n int i; // [rsp+2Ch] [rbp-4h]\n\n v7 = 0;\n for ( i = 0; i < a2; i += a3 )\n {\n v5 = v7++;\n *(_DWORD *)(a4 + 4LL * v5) = *(_DWORD *)(4LL * i + a1);\n }\n result = a5;\n *a5 = v7;\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_28], rcx\nmov [rbp+var_30], r8\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11EC\nloc_11B3:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_8]\nlea edx, [rax+1]\nmov [rbp+var_8], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nmov eax, [rbp+var_20]\nadd [rbp+var_4], eax\nloc_11EC:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11B3\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_8]\nmov [rax], edx\nnop\npop rbp\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1189(__int64 a1, int a2, int a3, __int64 a4, _DWORD *a5)\n{\n int v5; // eax\n _DWORD *result; // rax\n int v7; // [rsp+28h] [rbp-8h]\n int i; // [rsp+2Ch] [rbp-4h]\n\n v7 = 0;\n for ( i = 0; i < a2; i += a3 )\n {\n v5 = v7++;\n *(_DWORD *)(a4 + 4LL * v5) = *(_DWORD *)(4LL * i + a1);\n }\n result = a5;\n *a5 = v7;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1189(long long a1, int a2, int a3, long long a4, uint32_t *a5) {\n int v5;\n uint32_t *result;\n int v7;\n int i;\n v7 = 0;\n for (i = 0; i < a2; i += a3) {\n v5 = v7++;\n *(uint32_t *)(a4 + 4LL * v5) = *(uint32_t *)(4LL * i + a1);\n }\n result = a5;\n *a5 = v7;\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, int a3, long long a4, uint32_t *a5) {\n int v5;\n uint32_t *result;\n int v7;\n int i;\n v7 = 0;\n for (i = 0; i < a2; i += a3) {\n v5 = v7++;\n *(uint32_t *)(a4 + 4LL * v5) = *(uint32_t *)(4LL * i + a1);\n }\n result = a5;\n *a5 = v7;\n return result;\n}" + }, + { + "index": 536, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "void func0(int* input_list, int list_size, int n, int* output_list,\n int* output_size) {\n int j = 0;\n for (int i = 0; i < list_size; i += n) {\n output_list[j++] = input_list[i];\n }\n *output_size = j;\n}", + "test": "int main() {\n\n int output_list[5];\n\n int output_size;\n\n\n\n int list1[] = {1, 2, 3, 4, 5, 6, 7, 8, 9};\n\n int expected1[] = {1, 3, 5, 7, 9};\n\n func0(list1, 9, 2, output_list, &output_size);\n\n assert(output_size == 5);\n\n for (int i = 0; i < output_size; i++) {\n\n assert(output_list[i] == expected1[i]);\n\n }\n\n\n\n int list2[] = {10, 15, 19, 17, 16, 18};\n\n int expected2[] = {10, 17};\n\n func0(list2, 6, 3, output_list, &output_size);\n\n assert(output_size == 2);\n\n for (int i = 0; i < output_size; i++) {\n\n assert(output_list[i] == expected2[i]);\n\n }\n\n\n\n int list3[] = {14, 16, 19, 15, 17};\n\n int expected3[] = {14, 17};\n\n func0(list3, 5, 4, output_list, &output_size);\n\n assert(output_size == 2);\n\n for (int i = 0; i < output_size; i++) {\n\n assert(output_list[i] == expected3[i]);\n\n }\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\ntest %esi,%esi\njle 11c2 \nmovslq %edx,%r11\nshl $0x2,%r11\nmov $0x1,%eax\nmov $0x0,%r9d\nmov %eax,%ebx\nmov (%rdi),%r10d\nmov %r10d,-0x4(%rcx,%rax,4)\nadd %edx,%r9d\nadd $0x1,%rax\nadd %r11,%rdi\ncmp %r9d,%esi\njg 11a4 \nmov %ebx,(%r8)\npop %rbx\nretq\nmov $0x0,%ebx\njmp 11bd \n", + "ida_asm": "func0:\nendbr64\nmov r9d, esi\nmov r10d, edx\ntest esi, esi\njle short loc_11C4\nmovsxd r11, edx\nshl r11, 2\nmov eax, 1\nmov edx, 0\nloc_11A8:\nmov esi, [rdi]\nmov [rcx+rax*4-4], esi\nadd edx, r10d\nmov rsi, rax\nadd rax, 1\nadd rdi, r11\ncmp r9d, edx\njg short loc_11A8\nloc_11C0:\nmov [r8], esi\nretn\nloc_11C4:\nmov esi, 0\njmp short loc_11C0", + "ida_pseudo": "void __fastcall func0(_DWORD *a1, int a2, int a3, __int64 a4, _DWORD *a5)\n{\n __int64 v7; // r11\n __int64 v8; // rax\n int v9; // edx\n int v10; // esi\n\n if ( a2 <= 0 )\n {\n v10 = 0;\n }\n else\n {\n v7 = 4LL * a3;\n v8 = 1LL;\n v9 = 0;\n do\n {\n *(_DWORD *)(a4 + 4 * v8 - 4) = *a1;\n v9 += a3;\n v10 = v8++;\n a1 = (_DWORD *)((char *)a1 + v7);\n }\n while ( a2 > v9 );\n }\n *a5 = v10;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\nmov r9d, esi\nmov r10d, edx\ntest esi, esi\njle short loc_11C4\nmovsxd r11, edx\nshl r11, 2\nmov eax, 1\nmov edx, 0\nloc_11A8:\nmov esi, [rdi]\nmov [rcx+rax*4-4], esi\nadd edx, r10d\nmov rsi, rax\nadd rax, 1\nadd rdi, r11\ncmp r9d, edx\njg short loc_11A8\nloc_11C0:\nmov [r8], esi\nretn\nloc_11C4:\nmov esi, 0\njmp short loc_11C0", + "ida_strip_pseudo": "void __fastcall sub_1189(_DWORD *a1, int a2, int a3, __int64 a4, _DWORD *a5)\n{\n __int64 v7; // r11\n __int64 v8; // rax\n int v9; // edx\n int v10; // esi\n\n if ( a2 <= 0 )\n {\n v10 = 0;\n }\n else\n {\n v7 = 4LL * a3;\n v8 = 1LL;\n v9 = 0;\n do\n {\n *(_DWORD *)(a4 + 4 * v8 - 4) = *a1;\n v9 += a3;\n v10 = v8++;\n a1 = (_DWORD *)((char *)a1 + v7);\n }\n while ( a2 > v9 );\n }\n *a5 = v10;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1189(uint32_t *a1, int a2, int a3, long long a4, uint32_t *a5) {\n long long v7;\n long long v8;\n int v9;\n int v10;\n if (a2 <= 0) {\n v10 = 0;\n } else {\n v7 = 4LL * a3;\n v8 = 1LL;\n v9 = 0;\n do {\n *(uint32_t *)(a4 + 4 * v8 - 4) = *a1;\n v9 += a3;\n v10 = v8++;\n a1 = (uint32_t *)((char *)a1 + v7);\n } while (a2 > v9);\n }\n *a5 = v10;\n}", + "ida_pseudo_norm": "void func0(uint32_t *a1, int a2, int a3, long long a4, uint32_t *a5) {\n long long v7;\n long long v8;\n int v9;\n int v10;\n if (a2 <= 0) {\n v10 = 0;\n } else {\n v7 = 4LL * a3;\n v8 = 1LL;\n v9 = 0;\n do {\n *(uint32_t *)(a4 + 4 * v8 - 4) = *a1;\n v9 += a3;\n v10 = v8++;\n a1 = (uint32_t *)((char *)a1 + v7);\n } while (a2 > v9);\n }\n *a5 = v10;\n}" + }, + { + "index": 537, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char *func0(char *str1) {\n char *words[100];\n int word_count = 0;\n char *word = strtok(str1, \" \");\n while (word != NULL) {\n for (int i = 0; i < word_count; i++) {\n if (strcmp(words[i], word) == 0) {\n return word;\n }\n }\n words[word_count++] = word;\n word = strtok(NULL, \" \");\n }\n return \"None\";\n}", + "test": "int main() {\n\n char str1[] = \"ab ca bc ab\";\n\n char str2[] = \"ab ca bc\";\n\n char str3[] = \"ab ca bc ca ab bc\";\n\n \n\n assert(strcmp(func0(str1), \"ab\") == 0);\n\n assert(strcmp(func0(str2), \"None\") == 0);\n\n assert(strcmp(func0(str3), \"ca\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x350,%rsp\nmov %rdi,-0x348(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovl $0x0,-0x340(%rbp)\nmov -0x348(%rbp),%rax\nlea 0xe22(%rip),%rsi\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x338(%rbp)\njmpq 1282 \nmovl $0x0,-0x33c(%rbp)\njmp 123c \nmov -0x33c(%rbp),%eax\ncltq\nmov -0x330(%rbp,%rax,8),%rax\nmov -0x338(%rbp),%rdx\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10a0 \ntest %eax,%eax\njne 1235 \nmov -0x338(%rbp),%rax\njmp 1297 \naddl $0x1,-0x33c(%rbp)\nmov -0x33c(%rbp),%eax\ncmp -0x340(%rbp),%eax\njl 1206 \nmov -0x340(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x340(%rbp)\ncltq\nmov -0x338(%rbp),%rdx\nmov %rdx,-0x330(%rbp,%rax,8)\nlea 0xd97(%rip),%rsi\nmov $0x0,%edi\ncallq 10b0 \nmov %rax,-0x338(%rbp)\ncmpq $0x0,-0x338(%rbp)\njne 11fa \nlea 0xd73(%rip),%rax\nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 12ab \ncallq 1080 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 350h\nmov [rbp+s], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_340], 0\nmov rax, [rbp+s]\nlea rdx, delim; \" \"\nmov rsi, rdx; delim\nmov rdi, rax; s\ncall _strtok\nmov [rbp+s2], rax\njmp loc_1288\nloc_11FD:\nmov [rbp+var_33C], 0\njmp short loc_123F\nloc_1209:\nmov eax, [rbp+var_33C]\ncdqe\nmov rax, [rbp+rax*8+s1]\nmov rdx, [rbp+s2]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1238\nmov rax, [rbp+s2]\njmp short loc_129D\nloc_1238:\nadd [rbp+var_33C], 1\nloc_123F:\nmov eax, [rbp+var_33C]\ncmp eax, [rbp+var_340]\njl short loc_1209\nmov eax, [rbp+var_340]\nlea edx, [rax+1]\nmov [rbp+var_340], edx\ncdqe\nmov rdx, [rbp+s2]\nmov [rbp+rax*8+s1], rdx\nlea rax, delim; \" \"\nmov rsi, rax; delim\nmov edi, 0; s\ncall _strtok\nmov [rbp+s2], rax\nloc_1288:\ncmp [rbp+s2], 0\njnz loc_11FD\nlea rax, aNone; \"None\"\nloc_129D:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12B1\ncall ___stack_chk_fail\nlocret_12B1:\nleave\nretn", + "ida_pseudo": "const char *__fastcall func0(char *a1)\n{\n int v2; // eax\n int v3; // [rsp+10h] [rbp-340h]\n int i; // [rsp+14h] [rbp-33Ch]\n const char *s2; // [rsp+18h] [rbp-338h]\n char *s1[102]; // [rsp+20h] [rbp-330h]\n\n s1[101] = (char *)__readfsqword(0x28u);\n v3 = 0;\n for ( s2 = strtok(a1, \" \"); s2; s2 = strtok(0LL, \" \") )\n {\n for ( i = 0; i < v3; ++i )\n {\n if ( !strcmp(s1[i], s2) )\n return s2;\n }\n v2 = v3++;\n s1[v2] = (char *)s2;\n }\n return \"None\";\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 350h\nmov [rbp+s], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_340], 0\nmov rax, [rbp+s]\nlea rdx, delim; \" \"\nmov rsi, rdx; delim\nmov rdi, rax; s\ncall _strtok\nmov [rbp+s2], rax\njmp loc_1288\nloc_11FD:\nmov [rbp+var_33C], 0\njmp short loc_123F\nloc_1209:\nmov eax, [rbp+var_33C]\ncdqe\nmov rax, [rbp+rax*8+s1]\nmov rdx, [rbp+s2]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1238\nmov rax, [rbp+s2]\njmp short loc_129D\nloc_1238:\nadd [rbp+var_33C], 1\nloc_123F:\nmov eax, [rbp+var_33C]\ncmp eax, [rbp+var_340]\njl short loc_1209\nmov eax, [rbp+var_340]\nlea edx, [rax+1]\nmov [rbp+var_340], edx\ncdqe\nmov rdx, [rbp+s2]\nmov [rbp+rax*8+s1], rdx\nlea rax, delim; \" \"\nmov rsi, rax; delim\nmov edi, 0; s\ncall _strtok\nmov [rbp+s2], rax\nloc_1288:\ncmp [rbp+s2], 0\njnz loc_11FD\nlea rax, aNone; \"None\"\nloc_129D:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12B1\ncall ___stack_chk_fail\nlocret_12B1:\nleave\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_11A9(char *a1)\n{\n int v2; // eax\n int v3; // [rsp+10h] [rbp-340h]\n int i; // [rsp+14h] [rbp-33Ch]\n const char *s2; // [rsp+18h] [rbp-338h]\n char *s1[102]; // [rsp+20h] [rbp-330h]\n\n s1[101] = (char *)__readfsqword(0x28u);\n v3 = 0;\n for ( s2 = strtok(a1, \" \"); s2; s2 = strtok(0LL, \" \") )\n {\n for ( i = 0; i < v3; ++i )\n {\n if ( !strcmp(s1[i], s2) )\n return s2;\n }\n v2 = v3++;\n s1[v2] = (char *)s2;\n }\n return \"None\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_11A9(char *a1) {\n int v2;\n int v3;\n int i;\n const char *s2;\n char *s1[102];\n s1[101] = (char *)__readfsqword(40u);\n v3 = 0;\n for (s2 = strtok(a1, \" \"); s2; s2 = strtok(0LL, \" \")) {\n for (i = 0; i < v3; ++i) {\n if (!strcmp(s1[i], s2)) return s2;\n }\n v2 = v3++;\n s1[v2] = (char *)s2;\n }\n return \"None\";\n}", + "ida_pseudo_norm": "const char *func0(char *a1) {\n int v2;\n int v3;\n int i;\n const char *s2;\n char *s1[102];\n s1[101] = (char *)__readfsqword(40u);\n v3 = 0;\n for (s2 = strtok(a1, \" \"); s2; s2 = strtok(0LL, \" \")) {\n for (i = 0; i < v3; ++i) {\n if (!strcmp(s1[i], s2)) return s2;\n }\n v2 = v3++;\n s1[v2] = (char *)s2;\n }\n return \"None\";\n}" + }, + { + "index": 537, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char *func0(char *str1) {\n char *words[100];\n int word_count = 0;\n char *word = strtok(str1, \" \");\n while (word != NULL) {\n for (int i = 0; i < word_count; i++) {\n if (strcmp(words[i], word) == 0) {\n return word;\n }\n }\n words[word_count++] = word;\n word = strtok(NULL, \" \");\n }\n return \"None\";\n}", + "test": "int main() {\n\n char str1[] = \"ab ca bc ab\";\n\n char str2[] = \"ab ca bc\";\n\n char str3[] = \"ab ca bc ca ab bc\";\n\n \n\n assert(strcmp(func0(str1), \"ab\") == 0);\n\n assert(strcmp(func0(str2), \"None\") == 0);\n\n assert(strcmp(func0(str3), \"ca\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x338,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x328(%rsp)\nxor %eax,%eax\nlea 0xe31(%rip),%rsi\ncallq 10b0 \nlea 0xe20(%rip),%rbp\ntest %rax,%rax\nje 124c \nmov %rax,%rbp\nmov %rsp,%r14\nlea 0x8(%rsp),%r12\nmov $0x1,%r13d\nlea 0xe08(%rip),%r15\nmov %rbp,-0x8(%r12)\nmov %r15,%rsi\nmov $0x0,%edi\ncallq 10b0 \nmov %rax,%rbp\ntest %rax,%rax\nje 1245 \ntest %r13d,%r13d\njle 123b \nmov %r14,%rbx\nmov %rbp,%rsi\nmov (%rbx),%rdi\ncallq 10a0 \ntest %eax,%eax\nje 124c \nadd $0x8,%rbx\ncmp %r12,%rbx\njne 1223 \nadd $0x1,%r13d\nadd $0x8,%r12\njmp 1201 \nlea 0xdb8(%rip),%rbp\nmov 0x328(%rsp),%rax\nxor %fs:0x28,%rax\njne 1274 \nmov %rbp,%rax\nadd $0x338,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\ncallq 1080 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 338h\nmov rax, fs:28h\nmov [rsp+368h+var_40], rax\nxor eax, eax\nlea rsi, delim; \" \"\ncall _strtok\nlea rbp, aNone; \"None\"\ntest rax, rax\njz short loc_124E\nmov rbp, rax\nmov r15, rsp\nmov r13, r15\nmov r14d, 0\nloc_11F8:\nadd r14d, 1\nmov [r13+0], rbp\nlea rsi, delim; \" \"\nmov edi, 0; s\ncall _strtok\nmov rbp, rax\nmov r12, r13\nadd r13, 8\ntest rax, rax\njz short loc_1247\ntest r14d, r14d\njle short loc_11F8\nmov rbx, r15\njmp short loc_122D\nloc_122A:\nmov rbx, rax\nloc_122D:\nmov rdi, [rbx]; s1\nmov rsi, rbp; s2\ncall _strcmp\ntest eax, eax\njz short loc_124E\nlea rax, [rbx+8]\ncmp rbx, r12\njnz short loc_122A\njmp short loc_11F8\nloc_1247:\nlea rbp, aNone; \"None\"\nloc_124E:\nmov rax, [rsp+368h+var_40]\nsub rax, fs:28h\njnz short loc_1276\nmov rax, rbp\nadd rsp, 338h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1276:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *a1)\n{\n char *v1; // rax\n char *v2; // rbp\n char **v3; // r13\n int v4; // r14d\n const char **v5; // r12\n const char **i; // rbx\n _QWORD v8[109]; // [rsp+0h] [rbp-368h] BYREF\n\n v8[101] = __readfsqword(0x28u);\n v1 = strtok(a1, \" \");\n v2 = \"None\";\n if ( v1 )\n {\n v2 = v1;\n v3 = (char **)v8;\n v4 = 0;\n do\n {\nLABEL_3:\n ++v4;\n *v3 = v2;\n v2 = strtok(0LL, \" \");\n v5 = (const char **)v3++;\n if ( !v2 )\n return \"None\";\n }\n while ( v4 <= 0 );\n for ( i = (const char **)v8; strcmp(*i, v2); ++i )\n {\n if ( i == v5 )\n goto LABEL_3;\n }\n }\n return v2;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 338h\nmov rax, fs:28h\nmov [rsp+368h+var_40], rax\nxor eax, eax\nlea rsi, delim; \" \"\ncall _strtok\nlea rbp, aNone; \"None\"\ntest rax, rax\njz short loc_124E\nmov rbp, rax\nmov r15, rsp\nmov r13, r15\nmov r14d, 0\nloc_11F8:\nadd r14d, 1\nmov [r13+0], rbp\nlea rsi, delim; \" \"\nmov edi, 0; s\ncall _strtok\nmov rbp, rax\nmov r12, r13\nadd r13, 8\ntest rax, rax\njz short loc_1247\ntest r14d, r14d\njle short loc_11F8\nmov rbx, r15\njmp short loc_122D\nloc_122A:\nmov rbx, rax\nloc_122D:\nmov rdi, [rbx]; s1\nmov rsi, rbp; s2\ncall _strcmp\ntest eax, eax\njz short loc_124E\nlea rax, [rbx+8]\ncmp rbx, r12\njnz short loc_122A\njmp short loc_11F8\nloc_1247:\nlea rbp, aNone; \"None\"\nloc_124E:\nmov rax, [rsp+368h+var_40]\nsub rax, fs:28h\njnz short loc_1276\nmov rax, rbp\nadd rsp, 338h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1276:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_11A9(char *a1)\n{\n char *v1; // rax\n char *v2; // rbp\n char **v3; // r13\n int v4; // r14d\n const char **v5; // r12\n const char **i; // rbx\n _QWORD v8[109]; // [rsp+0h] [rbp-368h] BYREF\n\n v8[101] = __readfsqword(0x28u);\n v1 = strtok(a1, \" \");\n v2 = \"None\";\n if ( v1 )\n {\n v2 = v1;\n v3 = (char **)v8;\n v4 = 0;\n do\n {\nLABEL_3:\n ++v4;\n *v3 = v2;\n v2 = strtok(0LL, \" \");\n v5 = (const char **)v3++;\n if ( !v2 )\n return \"None\";\n }\n while ( v4 <= 0 );\n for ( i = (const char **)v8; strcmp(*i, v2); ++i )\n {\n if ( i == v5 )\n goto LABEL_3;\n }\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_11A9(char *a1) {\n char *v1;\n char *v2;\n char **v3;\n int v4;\n const char **v5;\n const char **i;\n uint64_t v8[109];\n v8[101] = __readfsqword(40u);\n v1 = strtok(a1, \" \");\n v2 = \"None\";\n if (v1) {\n v2 = v1;\n v3 = (char **)v8;\n v4 = 0;\n do {\n LABEL_3:\n ++v4;\n *v3 = v2;\n v2 = strtok(0LL, \" \");\n v5 = (const char **)v3++;\n if (!v2) return \"None\";\n } while (v4 <= 0);\n for (i = (const char **)v8; strcmp(*i, v2); ++i) {\n if (i == v5) goto LABEL_3;\n }\n }\n return v2;\n}", + "ida_pseudo_norm": "const char *func0(char *a1) {\n char *v1;\n char *v2;\n char **v3;\n int v4;\n const char **v5;\n const char **i;\n uint64_t v8[109];\n v8[101] = __readfsqword(40u);\n v1 = strtok(a1, \" \");\n v2 = \"None\";\n if (v1) {\n v2 = v1;\n v3 = (char **)v8;\n v4 = 0;\n do {\n LABEL_3:\n ++v4;\n *v3 = v2;\n v2 = strtok(0LL, \" \");\n v5 = (const char **)v3++;\n if (!v2) return \"None\";\n } while (v4 <= 0);\n for (i = (const char **)v8; strcmp(*i, v2); ++i) {\n if (i == v5) goto LABEL_3;\n }\n }\n return v2;\n}" + }, + { + "index": 537, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char *func0(char *str1) {\n char *words[100];\n int word_count = 0;\n char *word = strtok(str1, \" \");\n while (word != NULL) {\n for (int i = 0; i < word_count; i++) {\n if (strcmp(words[i], word) == 0) {\n return word;\n }\n }\n words[word_count++] = word;\n word = strtok(NULL, \" \");\n }\n return \"None\";\n}", + "test": "int main() {\n\n char str1[] = \"ab ca bc ab\";\n\n char str2[] = \"ab ca bc\";\n\n char str3[] = \"ab ca bc ca ab bc\";\n\n \n\n assert(strcmp(func0(str1), \"ab\") == 0);\n\n assert(strcmp(func0(str2), \"None\") == 0);\n\n assert(strcmp(func0(str3), \"ca\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\nlea 0xd1c(%rip),%rsi\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x330,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x328(%rsp)\nxor %eax,%eax\ncallq 10b0 \ntest %rax,%rax\nje 1396 \nmov %rax,%r12\nmov %rsp,%r14\nlea 0x8(%rsp),%rbp\nlea 0xce0(%rip),%r13\nmov %r13,%rsi\nxor %edi,%edi\nmov %r12,-0x8(%rbp)\ncallq 10b0 \nmov %rax,%r12\ntest %rax,%rax\nje 1396 \nmov %r14,%rbx\njmp 1351 \nnopl 0x0(%rax)\nadd $0x8,%rbx\ncmp %rbp,%rbx\nje 1390 \nmov (%rbx),%rdi\nmov %r12,%rsi\ncallq 10a0 \ntest %eax,%eax\njne 1348 \nmov 0x328(%rsp),%rax\nxor %fs:0x28,%rax\njne 139f \nadd $0x330,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopw %cs:0x0(%rax,%rax,1)\nadd $0x8,%rbp\njmp 1329 \nlea 0xc67(%rip),%r12\njmp 1360 \ncallq 1080 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nlea r14, delim; \" \"\npush r13\nmov rsi, r14; delim\npush r12\npush rbp\npush rbx\nsub rsp, 338h\nmov rax, fs:28h\nmov [rsp+368h+var_40], rax\nxor eax, eax\ncall _strtok\ntest rax, rax\njz short loc_1383\nmov r15, rsp\nmov rbp, rax\nmov r13, r15\nloc_1315:\nmov [r13+0], rbp\nmov rsi, r14; delim\nxor edi, edi; s\nmov r12, r13\nadd r13, 8\ncall _strtok\nmov rbp, rax\ntest rax, rax\njz short loc_1383\nmov rbx, r15\njmp short loc_134C\nloc_1340:\nlea rax, [rbx+8]\ncmp rbx, r12\njz short loc_1315\nmov rbx, rax\nloc_134C:\nmov rdi, [rbx]; s1\nmov rsi, rbp; s2\ncall _strcmp\ntest eax, eax\njnz short loc_1340\nloc_135B:\nmov rax, [rsp+368h+var_40]\nsub rax, fs:28h\njnz short loc_138C\nadd rsp, 338h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1383:\nlea rbp, s2; \"None\"\njmp short loc_135B\nloc_138C:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *a1)\n{\n char *v1; // rax\n char *v2; // rbp\n char **v3; // r13\n const char **v4; // r12\n const char **i; // rbx\n _QWORD v7[109]; // [rsp+0h] [rbp-368h] BYREF\n\n v7[101] = __readfsqword(0x28u);\n v1 = strtok(a1, \" \");\n if ( !v1 )\n return \"None\";\n v2 = v1;\n v3 = (char **)v7;\nLABEL_3:\n *v3 = v2;\n v4 = (const char **)v3++;\n v2 = strtok(0LL, \" \");\n if ( !v2 )\n return \"None\";\n for ( i = (const char **)v7; strcmp(*i, v2); ++i )\n {\n if ( i == v4 )\n goto LABEL_3;\n }\n return v2;\n}", + "ida_strip_asm": "sub_12D0:\nendbr64\npush r15\npush r14\nlea r14, delim; \" \"\npush r13\nmov rsi, r14; delim\npush r12\npush rbp\npush rbx\nsub rsp, 338h\nmov rax, fs:28h\nmov [rsp+368h+var_40], rax\nxor eax, eax\ncall _strtok\ntest rax, rax\njz short loc_1383\nmov r15, rsp\nmov rbp, rax\nmov r13, r15\nloc_1315:\nmov [r13+0], rbp\nmov rsi, r14; delim\nxor edi, edi; s\nmov r12, r13\nadd r13, 8\ncall _strtok\nmov rbp, rax\ntest rax, rax\njz short loc_1383\nmov rbx, r15\njmp short loc_134C\nloc_1340:\nlea rax, [rbx+8]\ncmp rbx, r12\njz short loc_1315\nmov rbx, rax\nloc_134C:\nmov rdi, [rbx]; s1\nmov rsi, rbp; s2\ncall _strcmp\ntest eax, eax\njnz short loc_1340\nloc_135B:\nmov rax, [rsp+368h+var_40]\nsub rax, fs:28h\njnz short loc_138C\nadd rsp, 338h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1383:\nlea rbp, s2; \"None\"\njmp short loc_135B\nloc_138C:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_12D0(char *a1)\n{\n char *v1; // rax\n char *v2; // rbp\n char **v3; // r13\n const char **v4; // r12\n const char **i; // rbx\n _QWORD v7[109]; // [rsp+0h] [rbp-368h] BYREF\n\n v7[101] = __readfsqword(0x28u);\n v1 = strtok(a1, \" \");\n if ( !v1 )\n return \"None\";\n v2 = v1;\n v3 = (char **)v7;\nLABEL_3:\n *v3 = v2;\n v4 = (const char **)v3++;\n v2 = strtok(0LL, \" \");\n if ( !v2 )\n return \"None\";\n for ( i = (const char **)v7; strcmp(*i, v2); ++i )\n {\n if ( i == v4 )\n goto LABEL_3;\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_12D0(char *a1) {\n char *v1;\n char *v2;\n char **v3;\n const char **v4;\n const char **i;\n uint64_t v7[109];\n v7[101] = __readfsqword(40u);\n v1 = strtok(a1, \" \");\n if (!v1) return \"None\";\n v2 = v1;\n v3 = (char **)v7;\nLABEL_3:\n *v3 = v2;\n v4 = (const char **)v3++;\n v2 = strtok(0LL, \" \");\n if (!v2) return \"None\";\n for (i = (const char **)v7; strcmp(*i, v2); ++i) {\n if (i == v4) goto LABEL_3;\n }\n return v2;\n}", + "ida_pseudo_norm": "const char *func0(char *a1) {\n char *v1;\n char *v2;\n char **v3;\n const char **v4;\n const char **i;\n uint64_t v7[109];\n v7[101] = __readfsqword(40u);\n v1 = strtok(a1, \" \");\n if (!v1) return \"None\";\n v2 = v1;\n v3 = (char **)v7;\nLABEL_3:\n *v3 = v2;\n v4 = (const char **)v3++;\n v2 = strtok(0LL, \" \");\n if (!v2) return \"None\";\n for (i = (const char **)v7; strcmp(*i, v2); ++i) {\n if (i == v4) goto LABEL_3;\n }\n return v2;\n}" + }, + { + "index": 537, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char *func0(char *str1) {\n char *words[100];\n int word_count = 0;\n char *word = strtok(str1, \" \");\n while (word != NULL) {\n for (int i = 0; i < word_count; i++) {\n if (strcmp(words[i], word) == 0) {\n return word;\n }\n }\n words[word_count++] = word;\n word = strtok(NULL, \" \");\n }\n return \"None\";\n}", + "test": "int main() {\n\n char str1[] = \"ab ca bc ab\";\n\n char str2[] = \"ab ca bc\";\n\n char str3[] = \"ab ca bc ca ab bc\";\n\n \n\n assert(strcmp(func0(str1), \"ab\") == 0);\n\n assert(strcmp(func0(str2), \"None\") == 0);\n\n assert(strcmp(func0(str3), \"ca\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\nlea 0xd1c(%rip),%rsi\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x330,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x328(%rsp)\nxor %eax,%eax\ncallq 10b0 \ntest %rax,%rax\nje 1396 \nmov %rax,%r12\nmov %rsp,%r14\nlea 0x8(%rsp),%rbp\nlea 0xce0(%rip),%r13\nmov %r13,%rsi\nxor %edi,%edi\nmov %r12,-0x8(%rbp)\ncallq 10b0 \nmov %rax,%r12\ntest %rax,%rax\nje 1396 \nmov %r14,%rbx\njmp 1351 \nnopl 0x0(%rax)\nadd $0x8,%rbx\ncmp %rbp,%rbx\nje 1390 \nmov (%rbx),%rdi\nmov %r12,%rsi\ncallq 10a0 \ntest %eax,%eax\njne 1348 \nmov 0x328(%rsp),%rax\nxor %fs:0x28,%rax\njne 139f \nadd $0x330,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopw %cs:0x0(%rax,%rax,1)\nadd $0x8,%rbp\njmp 1329 \nlea 0xc67(%rip),%r12\njmp 1360 \ncallq 1080 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nlea r14, delim; \" \"\npush r13\nmov rsi, r14; delim\npush r12\npush rbp\npush rbx\nsub rsp, 338h\nmov rax, fs:28h\nmov [rsp+368h+var_40], rax\nxor eax, eax\ncall _strtok\ntest rax, rax\njz short loc_1383\nmov r15, rsp\nmov rbp, rax\nmov r13, r15\nloc_1315:\nmov [r13+0], rbp\nmov rsi, r14; delim\nxor edi, edi; s\nmov r12, r13\nadd r13, 8\ncall _strtok\nmov rbp, rax\ntest rax, rax\njz short loc_1383\nmov rbx, r15\njmp short loc_134C\nloc_1340:\nlea rax, [rbx+8]\ncmp rbx, r12\njz short loc_1315\nmov rbx, rax\nloc_134C:\nmov rdi, [rbx]; s1\nmov rsi, rbp; s2\ncall _strcmp\ntest eax, eax\njnz short loc_1340\nloc_135B:\nmov rax, [rsp+368h+var_40]\nsub rax, fs:28h\njnz short loc_138C\nadd rsp, 338h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1383:\nlea rbp, s2; \"None\"\njmp short loc_135B\nloc_138C:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *a1)\n{\n char *v1; // rax\n char *v2; // rbp\n char **v3; // r13\n const char **v4; // r12\n const char **i; // rbx\n _QWORD v7[109]; // [rsp+0h] [rbp-368h] BYREF\n\n v7[101] = __readfsqword(0x28u);\n v1 = strtok(a1, \" \");\n if ( !v1 )\n return \"None\";\n v2 = v1;\n v3 = (char **)v7;\nLABEL_3:\n *v3 = v2;\n v4 = (const char **)v3++;\n v2 = strtok(0LL, \" \");\n if ( !v2 )\n return \"None\";\n for ( i = (const char **)v7; strcmp(*i, v2); ++i )\n {\n if ( i == v4 )\n goto LABEL_3;\n }\n return v2;\n}", + "ida_strip_asm": "sub_12D0:\nendbr64\npush r15\npush r14\nlea r14, delim; \" \"\npush r13\nmov rsi, r14; delim\npush r12\npush rbp\npush rbx\nsub rsp, 338h\nmov rax, fs:28h\nmov [rsp+368h+var_40], rax\nxor eax, eax\ncall _strtok\ntest rax, rax\njz short loc_1383\nmov r15, rsp\nmov rbp, rax\nmov r13, r15\nloc_1315:\nmov [r13+0], rbp\nmov rsi, r14; delim\nxor edi, edi; s\nmov r12, r13\nadd r13, 8\ncall _strtok\nmov rbp, rax\ntest rax, rax\njz short loc_1383\nmov rbx, r15\njmp short loc_134C\nloc_1340:\nlea rax, [rbx+8]\ncmp rbx, r12\njz short loc_1315\nmov rbx, rax\nloc_134C:\nmov rdi, [rbx]; s1\nmov rsi, rbp; s2\ncall _strcmp\ntest eax, eax\njnz short loc_1340\nloc_135B:\nmov rax, [rsp+368h+var_40]\nsub rax, fs:28h\njnz short loc_138C\nadd rsp, 338h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1383:\nlea rbp, s2; \"None\"\njmp short loc_135B\nloc_138C:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_12D0(char *a1)\n{\n char *v1; // rax\n char *v2; // rbp\n char **v3; // r13\n const char **v4; // r12\n const char **i; // rbx\n _QWORD v7[109]; // [rsp+0h] [rbp-368h] BYREF\n\n v7[101] = __readfsqword(0x28u);\n v1 = strtok(a1, \" \");\n if ( !v1 )\n return \"None\";\n v2 = v1;\n v3 = (char **)v7;\nLABEL_3:\n *v3 = v2;\n v4 = (const char **)v3++;\n v2 = strtok(0LL, \" \");\n if ( !v2 )\n return \"None\";\n for ( i = (const char **)v7; strcmp(*i, v2); ++i )\n {\n if ( i == v4 )\n goto LABEL_3;\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_12D0(char *a1) {\n char *v1;\n char *v2;\n char **v3;\n const char **v4;\n const char **i;\n uint64_t v7[109];\n v7[101] = __readfsqword(40u);\n v1 = strtok(a1, \" \");\n if (!v1) return \"None\";\n v2 = v1;\n v3 = (char **)v7;\nLABEL_3:\n *v3 = v2;\n v4 = (const char **)v3++;\n v2 = strtok(0LL, \" \");\n if (!v2) return \"None\";\n for (i = (const char **)v7; strcmp(*i, v2); ++i) {\n if (i == v4) goto LABEL_3;\n }\n return v2;\n}", + "ida_pseudo_norm": "const char *func0(char *a1) {\n char *v1;\n char *v2;\n char **v3;\n const char **v4;\n const char **i;\n uint64_t v7[109];\n v7[101] = __readfsqword(40u);\n v1 = strtok(a1, \" \");\n if (!v1) return \"None\";\n v2 = v1;\n v3 = (char **)v7;\nLABEL_3:\n *v3 = v2;\n v4 = (const char **)v3++;\n v2 = strtok(0LL, \" \");\n if (!v2) return \"None\";\n for (i = (const char **)v7; strcmp(*i, v2); ++i) {\n if (i == v4) goto LABEL_3;\n }\n return v2;\n}" + }, + { + "index": 538, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include\n\ntypedef struct {\n\n char values[100];\n\n int length;\n\n} tuple;\n\n\n\n", + "func": "tuple func0(const char *str1) {\n tuple result;\n int j = 0;\n for (int i = 0; str1[i] != '\\0'; i++) {\n if (!isspace(str1[i])) {\n result.values[j++] = str1[i];\n }\n }\n result.length = j;\n return result;\n}", + "test": "int main() {\n\n tuple result;\n\n \n\n result = func0(\"python 3.0\");\n\n char expected1[] = {'p', 'y', 't', 'h', 'o', 'n', '3', '.', '0'};\n\n int length1 = sizeof(expected1);\n\n assert(result.length == length1);\n\n for (int i = 0; i < length1; i++) {\n\n assert(result.values[i] == expected1[i]);\n\n }\n\n \n\n result = func0(\"bigdata\");\n\n char expected2[] = {'b', 'i', 'g', 'd', 'a', 't', 'a'};\n\n int length2 = sizeof(expected2);\n\n assert(result.length == length2);\n\n for (int i = 0; i < length2; i++) {\n\n assert(result.values[i] == expected2[i]);\n\n }\n\n\n\n result = func0(\"language\");\n\n char expected3[] = {'l', 'a', 'n', 'g', 'u', 'a', 'g','e'};\n\n int length3 = sizeof(expected3);\n\n assert(result.length == length3);\n\n for (int i = 0; i < length3; i++) {\n\n assert(result.values[i] == expected3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x98,%rsp\nmov %rdi,-0x98(%rbp)\nmov %rsi,-0xa0(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmovl $0x0,-0x88(%rbp)\nmovl $0x0,-0x84(%rbp)\njmp 1236 \ncallq 1090 <__ctype_b_loc@plt>\nmov (%rax),%rax\nmov -0x84(%rbp),%edx\nmovslq %edx,%rcx\nmov -0xa0(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rdx),%edx\nmovsbq %dl,%rdx\nadd %rdx,%rdx\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x2000,%eax\ntest %eax,%eax\njne 122f \nmov -0x84(%rbp),%eax\nmovslq %eax,%rdx\nmov -0xa0(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x88(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x88(%rbp)\nmovzbl (%rcx),%edx\ncltq\nmov %dl,-0x80(%rbp,%rax,1)\naddl $0x1,-0x84(%rbp)\nmov -0x84(%rbp),%eax\nmovslq %eax,%rdx\nmov -0xa0(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 11cc \nmov -0x88(%rbp),%eax\nmov %eax,-0x1c(%rbp)\nmov -0x98(%rbp),%rax\nmov -0x80(%rbp),%rcx\nmov -0x78(%rbp),%rbx\nmov %rcx,(%rax)\nmov %rbx,0x8(%rax)\nmov -0x70(%rbp),%rcx\nmov -0x68(%rbp),%rbx\nmov %rcx,0x10(%rax)\nmov %rbx,0x18(%rax)\nmov -0x60(%rbp),%rcx\nmov -0x58(%rbp),%rbx\nmov %rcx,0x20(%rax)\nmov %rbx,0x28(%rax)\nmov -0x50(%rbp),%rcx\nmov -0x48(%rbp),%rbx\nmov %rcx,0x30(%rax)\nmov %rbx,0x38(%rax)\nmov -0x40(%rbp),%rcx\nmov -0x38(%rbp),%rbx\nmov %rcx,0x40(%rax)\nmov %rbx,0x48(%rax)\nmov -0x30(%rbp),%rcx\nmov -0x28(%rbp),%rbx\nmov %rcx,0x50(%rax)\nmov %rbx,0x58(%rax)\nmov -0x20(%rbp),%rdx\nmov %rdx,0x60(%rax)\nmov -0x18(%rbp),%rax\nxor %fs:0x28,%rax\nje 12df \ncallq 1070 <__stack_chk_fail@plt>\nmov -0x98(%rbp),%rax\nadd $0x98,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 98h\nmov [rbp+var_98], rdi\nmov [rbp+var_A0], rsi\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov [rbp+var_88], 0\nmov [rbp+var_84], 0\njmp short loc_1236\nloc_11CC:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_84]\nmovsxd rcx, edx\nmov rdx, [rbp+var_A0]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 2000h\ntest eax, eax\njnz short loc_122F\nmov eax, [rbp+var_84]\nmovsxd rdx, eax\nmov rax, [rbp+var_A0]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_88]\nlea edx, [rax+1]\nmov [rbp+var_88], edx\nmovzx edx, byte ptr [rcx]\ncdqe\nmov byte ptr [rbp+rax+var_80], dl\nloc_122F:\nadd [rbp+var_84], 1\nloc_1236:\nmov eax, [rbp+var_84]\nmovsxd rdx, eax\nmov rax, [rbp+var_A0]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_11CC\nmov eax, [rbp+var_88]\nmov [rbp+var_1C], eax\nmov rax, [rbp+var_98]\nmov rcx, [rbp+var_80]\nmov rbx, [rbp+var_78]\nmov [rax], rcx\nmov [rax+8], rbx\nmov rcx, [rbp+var_70]\nmov rbx, [rbp+var_68]\nmov [rax+10h], rcx\nmov [rax+18h], rbx\nmov rcx, [rbp+var_60]\nmov rbx, [rbp+var_58]\nmov [rax+20h], rcx\nmov [rax+28h], rbx\nmov rcx, [rbp+var_50]\nmov rbx, [rbp+var_48]\nmov [rax+30h], rcx\nmov [rax+38h], rbx\nmov rcx, [rbp+var_40]\nmov rbx, [rbp+var_38]\nmov [rax+40h], rcx\nmov [rax+48h], rbx\nmov rcx, [rbp+var_30]\nmov rbx, [rbp+var_28]\nmov [rax+50h], rcx\nmov [rax+58h], rbx\nmov rdx, [rbp-20h]\nmov [rax+60h], rdx\nmov rax, [rbp+var_18]\nsub rax, fs:28h\njz short loc_12DF\ncall ___stack_chk_fail\nloc_12DF:\nmov rax, [rbp+var_98]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(_QWORD *a1, __int64 a2)\n{\n int v2; // eax\n __int64 v3; // rbx\n __int64 v4; // rbx\n __int64 v5; // rbx\n __int64 v6; // rbx\n __int64 v7; // rbx\n __int64 v8; // rbx\n int v10; // [rsp+18h] [rbp-88h]\n int i; // [rsp+1Ch] [rbp-84h]\n _QWORD v12[12]; // [rsp+20h] [rbp-80h]\n __int64 v13; // [rsp+80h] [rbp-20h]\n unsigned __int64 v14; // [rsp+88h] [rbp-18h]\n\n v14 = __readfsqword(0x28u);\n v10 = 0;\n for ( i = 0; *(_BYTE *)(i + a2); ++i )\n {\n if ( ((*__ctype_b_loc())[*(char *)(i + a2)] & 0x2000) == 0 )\n {\n v2 = v10++;\n *((_BYTE *)v12 + v2) = *(_BYTE *)(i + a2);\n }\n }\n HIDWORD(v13) = v10;\n v3 = v12[1];\n *a1 = v12[0];\n a1[1] = v3;\n v4 = v12[3];\n a1[2] = v12[2];\n a1[3] = v4;\n v5 = v12[5];\n a1[4] = v12[4];\n a1[5] = v5;\n v6 = v12[7];\n a1[6] = v12[6];\n a1[7] = v6;\n v7 = v12[9];\n a1[8] = v12[8];\n a1[9] = v7;\n v8 = v12[11];\n a1[10] = v12[10];\n a1[11] = v8;\n a1[12] = v13;\n return a1;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 98h\nmov [rbp+var_98], rdi\nmov [rbp+var_A0], rsi\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov [rbp+var_88], 0\nmov [rbp+var_84], 0\njmp short loc_1236\nloc_11CC:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_84]\nmovsxd rcx, edx\nmov rdx, [rbp+var_A0]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 2000h\ntest eax, eax\njnz short loc_122F\nmov eax, [rbp+var_84]\nmovsxd rdx, eax\nmov rax, [rbp+var_A0]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_88]\nlea edx, [rax+1]\nmov [rbp+var_88], edx\nmovzx edx, byte ptr [rcx]\ncdqe\nmov byte ptr [rbp+rax+var_80], dl\nloc_122F:\nadd [rbp+var_84], 1\nloc_1236:\nmov eax, [rbp+var_84]\nmovsxd rdx, eax\nmov rax, [rbp+var_A0]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_11CC\nmov eax, [rbp+var_88]\nmov [rbp+var_1C], eax\nmov rax, [rbp+var_98]\nmov rcx, [rbp+var_80]\nmov rbx, [rbp+var_78]\nmov [rax], rcx\nmov [rax+8], rbx\nmov rcx, [rbp+var_70]\nmov rbx, [rbp+var_68]\nmov [rax+10h], rcx\nmov [rax+18h], rbx\nmov rcx, [rbp+var_60]\nmov rbx, [rbp+var_58]\nmov [rax+20h], rcx\nmov [rax+28h], rbx\nmov rcx, [rbp+var_50]\nmov rbx, [rbp+var_48]\nmov [rax+30h], rcx\nmov [rax+38h], rbx\nmov rcx, [rbp+var_40]\nmov rbx, [rbp+var_38]\nmov [rax+40h], rcx\nmov [rax+48h], rbx\nmov rcx, [rbp+var_30]\nmov rbx, [rbp+var_28]\nmov [rax+50h], rcx\nmov [rax+58h], rbx\nmov rdx, [rbp-20h]\nmov [rax+60h], rdx\nmov rax, [rbp+var_18]\nsub rax, fs:28h\njz short loc_12DF\ncall ___stack_chk_fail\nloc_12DF:\nmov rax, [rbp+var_98]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1189(_QWORD *a1, __int64 a2)\n{\n int v2; // eax\n __int64 v3; // rbx\n __int64 v4; // rbx\n __int64 v5; // rbx\n __int64 v6; // rbx\n __int64 v7; // rbx\n __int64 v8; // rbx\n int v10; // [rsp+18h] [rbp-88h]\n int i; // [rsp+1Ch] [rbp-84h]\n _QWORD v12[12]; // [rsp+20h] [rbp-80h]\n __int64 v13; // [rsp+80h] [rbp-20h]\n unsigned __int64 v14; // [rsp+88h] [rbp-18h]\n\n v14 = __readfsqword(0x28u);\n v10 = 0;\n for ( i = 0; *(_BYTE *)(i + a2); ++i )\n {\n if ( ((*__ctype_b_loc())[*(char *)(i + a2)] & 0x2000) == 0 )\n {\n v2 = v10++;\n *((_BYTE *)v12 + v2) = *(_BYTE *)(i + a2);\n }\n }\n HIDWORD(v13) = v10;\n v3 = v12[1];\n *a1 = v12[0];\n a1[1] = v3;\n v4 = v12[3];\n a1[2] = v12[2];\n a1[3] = v4;\n v5 = v12[5];\n a1[4] = v12[4];\n a1[5] = v5;\n v6 = v12[7];\n a1[6] = v12[6];\n a1[7] = v6;\n v7 = v12[9];\n a1[8] = v12[8];\n a1[9] = v7;\n v8 = v12[11];\n a1[10] = v12[10];\n a1[11] = v8;\n a1[12] = v13;\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1189(uint64_t *a1, long long a2) {\n int v2;\n long long v3;\n long long v4;\n long long v5;\n long long v6;\n long long v7;\n long long v8;\n int v10;\n int i;\n uint64_t v12[12];\n long long v13;\n unsigned long long v14;\n v14 = __readfsqword(40u);\n v10 = 0;\n for (i = 0; *(uint8_t *)(i + a2); ++i) {\n if (((*__ctype_b_loc())[*(char *)(i + a2)] & 8192) == 0) {\n v2 = v10++;\n *((uint8_t *)v12 + v2) = *(uint8_t *)(i + a2);\n }\n }\n HIDWORD(v13) = v10;\n v3 = v12[1];\n *a1 = v12[0];\n a1[1] = v3;\n v4 = v12[3];\n a1[2] = v12[2];\n a1[3] = v4;\n v5 = v12[5];\n a1[4] = v12[4];\n a1[5] = v5;\n v6 = v12[7];\n a1[6] = v12[6];\n a1[7] = v6;\n v7 = v12[9];\n a1[8] = v12[8];\n a1[9] = v7;\n v8 = v12[11];\n a1[10] = v12[10];\n a1[11] = v8;\n a1[12] = v13;\n return a1;\n}", + "ida_pseudo_norm": "uint64_t *func0(uint64_t *a1, long long a2) {\n int v2;\n long long v3;\n long long v4;\n long long v5;\n long long v6;\n long long v7;\n long long v8;\n int v10;\n int i;\n uint64_t v12[12];\n long long v13;\n unsigned long long v14;\n v14 = __readfsqword(40u);\n v10 = 0;\n for (i = 0; *(uint8_t *)(i + a2); ++i) {\n if (((*__ctype_b_loc())[*(char *)(i + a2)] & 8192) == 0) {\n v2 = v10++;\n *((uint8_t *)v12 + v2) = *(uint8_t *)(i + a2);\n }\n }\n HIDWORD(v13) = v10;\n v3 = v12[1];\n *a1 = v12[0];\n a1[1] = v3;\n v4 = v12[3];\n a1[2] = v12[2];\n a1[3] = v4;\n v5 = v12[5];\n a1[4] = v12[4];\n a1[5] = v5;\n v6 = v12[7];\n a1[6] = v12[6];\n a1[7] = v6;\n v7 = v12[9];\n a1[8] = v12[8];\n a1[9] = v7;\n v8 = v12[11];\n a1[10] = v12[10];\n a1[11] = v8;\n a1[12] = v13;\n return a1;\n}" + }, + { + "index": 538, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include\n\ntypedef struct {\n\n char values[100];\n\n int length;\n\n} tuple;\n\n\n\n", + "func": "tuple func0(const char *str1) {\n tuple result;\n int j = 0;\n for (int i = 0; str1[i] != '\\0'; i++) {\n if (!isspace(str1[i])) {\n result.values[j++] = str1[i];\n }\n }\n result.length = j;\n return result;\n}", + "test": "int main() {\n\n tuple result;\n\n \n\n result = func0(\"python 3.0\");\n\n char expected1[] = {'p', 'y', 't', 'h', 'o', 'n', '3', '.', '0'};\n\n int length1 = sizeof(expected1);\n\n assert(result.length == length1);\n\n for (int i = 0; i < length1; i++) {\n\n assert(result.values[i] == expected1[i]);\n\n }\n\n \n\n result = func0(\"bigdata\");\n\n char expected2[] = {'b', 'i', 'g', 'd', 'a', 't', 'a'};\n\n int length2 = sizeof(expected2);\n\n assert(result.length == length2);\n\n for (int i = 0; i < length2; i++) {\n\n assert(result.values[i] == expected2[i]);\n\n }\n\n\n\n result = func0(\"language\");\n\n char expected3[] = {'l', 'a', 'n', 'g', 'u', 'a', 'g','e'};\n\n int length3 = sizeof(expected3);\n\n assert(result.length == length3);\n\n for (int i = 0; i < length3; i++) {\n\n assert(result.values[i] == expected3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nsub $0x70,%rsp\nmov %rdi,%r12\nmov %fs:0x28,%rax\nmov %rax,0x68(%rsp)\nxor %eax,%eax\nmovzbl (%rsi),%ebx\ntest %bl,%bl\nje 11e7 \nmov %rsi,%rbp\ncallq 1090 <__ctype_b_loc@plt>\nmov (%rax),%rcx\nlea 0x1(%rbp),%rsi\nmov $0x0,%edx\njmp 11d1 \nadd $0x1,%rsi\nmovzbl -0x1(%rsi),%ebx\ntest %bl,%bl\nje 11ec \nmovsbq %bl,%rax\ntestb $0x20,0x1(%rcx,%rax,2)\njne 11c5 \nmovslq %edx,%rax\nmov %bl,(%rsp,%rax,1)\nlea 0x1(%rdx),%edx\njmp 11c5 \nmov $0x0,%edx\nmov %edx,0x64(%rsp)\nmovdqa (%rsp),%xmm0\nmovups %xmm0,(%r12)\nmovdqa 0x10(%rsp),%xmm1\nmovups %xmm1,0x10(%r12)\nmovdqa 0x20(%rsp),%xmm2\nmovups %xmm2,0x20(%r12)\nmovdqa 0x30(%rsp),%xmm3\nmovups %xmm3,0x30(%r12)\nmovdqa 0x40(%rsp),%xmm4\nmovups %xmm4,0x40(%r12)\nmovdqa 0x50(%rsp),%xmm5\nmovups %xmm5,0x50(%r12)\nmov 0x60(%rsp),%rax\nmov %rax,0x60(%r12)\nmov 0x68(%rsp),%rax\nxor %fs:0x28,%rax\njne 125c \nmov %r12,%rax\nadd $0x70,%rsp\npop %rbx\npop %rbp\npop %r12\nretq\ncallq 1070 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 70h\nmov r12, rdi\nmov rax, fs:28h\nmov [rsp+88h+var_20], rax\nxor eax, eax\nmovzx ebx, byte ptr [rsi]\ntest bl, bl\njz short loc_11E7\nmov rbp, rsi\ncall ___ctype_b_loc\nmov rcx, [rax]\nlea rsi, [rbp+1]\nmov edx, 0\njmp short loc_11D1\nloc_11C5:\nadd rsi, 1\nmovzx ebx, byte ptr [rsi-1]\ntest bl, bl\njz short loc_11EC\nloc_11D1:\nmovsx rax, bl\ntest byte ptr [rcx+rax*2+1], 20h\njnz short loc_11C5\nmovsxd rax, edx\nmov byte ptr [rsp+rax+88h+var_88], bl\nlea edx, [rdx+1]\njmp short loc_11C5\nloc_11E7:\nmov edx, 0\nloc_11EC:\nmov [rsp+88h+var_24], edx\nmovdqa xmm0, [rsp+88h+var_88]\nmovups xmmword ptr [r12], xmm0\nmovdqa xmm1, [rsp+88h+var_78]\nmovups xmmword ptr [r12+10h], xmm1\nmovdqa xmm2, [rsp+88h+var_68]\nmovups xmmword ptr [r12+20h], xmm2\nmovdqa xmm3, [rsp+88h+var_58]\nmovups xmmword ptr [r12+30h], xmm3\nmovdqa xmm4, [rsp+88h+var_48]\nmovups xmmword ptr [r12+40h], xmm4\nmovdqa xmm5, [rsp+88h+var_38]\nmovups xmmword ptr [r12+50h], xmm5\nmov rax, [rsp+60h]\nmov [r12+60h], rax\nmov rax, [rsp+88h+var_20]\nsub rax, fs:28h\njnz short loc_125C\nmov rax, r12\nadd rsp, 70h\npop rbx\npop rbp\npop r12\nretn\nloc_125C:\ncall ___stack_chk_fail", + "ida_pseudo": "__m128i *__fastcall func0(__m128i *a1, __int8 *a2)\n{\n __int8 v2; // bl\n const unsigned __int16 *v3; // rcx\n __int8 *v4; // rsi\n int v5; // edx\n __m128i v7; // [rsp+0h] [rbp-88h] BYREF\n __m128i v8; // [rsp+10h] [rbp-78h] BYREF\n __m128i v9; // [rsp+20h] [rbp-68h] BYREF\n __m128i v10; // [rsp+30h] [rbp-58h] BYREF\n __m128i v11; // [rsp+40h] [rbp-48h] BYREF\n __m128i v12; // [rsp+50h] [rbp-38h] BYREF\n __int64 v13; // [rsp+60h] [rbp-28h]\n unsigned __int64 v14; // [rsp+68h] [rbp-20h]\n\n v14 = __readfsqword(0x28u);\n v2 = *a2;\n if ( *a2 )\n {\n v3 = *__ctype_b_loc();\n v4 = a2 + 1;\n v5 = 0;\n do\n {\n if ( (v3[v2] & 0x2000) == 0 )\n v7.m128i_i8[v5++] = v2;\n v2 = *v4++;\n }\n while ( v2 );\n }\n else\n {\n v5 = 0;\n }\n HIDWORD(v13) = v5;\n *a1 = _mm_load_si128(&v7);\n a1[1] = _mm_load_si128(&v8);\n a1[2] = _mm_load_si128(&v9);\n a1[3] = _mm_load_si128(&v10);\n a1[4] = _mm_load_si128(&v11);\n a1[5] = _mm_load_si128(&v12);\n a1[6].m128i_i64[0] = v13;\n return a1;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 70h\nmov r12, rdi\nmov rax, fs:28h\nmov [rsp+88h+var_20], rax\nxor eax, eax\nmovzx ebx, byte ptr [rsi]\ntest bl, bl\njz short loc_11E7\nmov rbp, rsi\ncall ___ctype_b_loc\nmov rcx, [rax]\nlea rsi, [rbp+1]\nmov edx, 0\njmp short loc_11D1\nloc_11C5:\nadd rsi, 1\nmovzx ebx, byte ptr [rsi-1]\ntest bl, bl\njz short loc_11EC\nloc_11D1:\nmovsx rax, bl\ntest byte ptr [rcx+rax*2+1], 20h\njnz short loc_11C5\nmovsxd rax, edx\nmov byte ptr [rsp+rax+88h+var_88], bl\nlea edx, [rdx+1]\njmp short loc_11C5\nloc_11E7:\nmov edx, 0\nloc_11EC:\nmov [rsp+88h+var_24], edx\nmovdqa xmm0, [rsp+88h+var_88]\nmovups xmmword ptr [r12], xmm0\nmovdqa xmm1, [rsp+88h+var_78]\nmovups xmmword ptr [r12+10h], xmm1\nmovdqa xmm2, [rsp+88h+var_68]\nmovups xmmword ptr [r12+20h], xmm2\nmovdqa xmm3, [rsp+88h+var_58]\nmovups xmmword ptr [r12+30h], xmm3\nmovdqa xmm4, [rsp+88h+var_48]\nmovups xmmword ptr [r12+40h], xmm4\nmovdqa xmm5, [rsp+88h+var_38]\nmovups xmmword ptr [r12+50h], xmm5\nmov rax, [rsp+60h]\nmov [r12+60h], rax\nmov rax, [rsp+88h+var_20]\nsub rax, fs:28h\njnz short loc_125C\nmov rax, r12\nadd rsp, 70h\npop rbx\npop rbp\npop r12\nretn\nloc_125C:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__m128i *__fastcall sub_1189(__m128i *a1, __int8 *a2)\n{\n __int8 v2; // bl\n const unsigned __int16 *v3; // rcx\n __int8 *v4; // rsi\n int v5; // edx\n __m128i v7; // [rsp+0h] [rbp-88h] BYREF\n __m128i v8; // [rsp+10h] [rbp-78h] BYREF\n __m128i v9; // [rsp+20h] [rbp-68h] BYREF\n __m128i v10; // [rsp+30h] [rbp-58h] BYREF\n __m128i v11; // [rsp+40h] [rbp-48h] BYREF\n __m128i v12; // [rsp+50h] [rbp-38h] BYREF\n __int64 v13; // [rsp+60h] [rbp-28h]\n unsigned __int64 v14; // [rsp+68h] [rbp-20h]\n\n v14 = __readfsqword(0x28u);\n v2 = *a2;\n if ( *a2 )\n {\n v3 = *__ctype_b_loc();\n v4 = a2 + 1;\n v5 = 0;\n do\n {\n if ( (v3[v2] & 0x2000) == 0 )\n v7.m128i_i8[v5++] = v2;\n v2 = *v4++;\n }\n while ( v2 );\n }\n else\n {\n v5 = 0;\n }\n HIDWORD(v13) = v5;\n *a1 = _mm_load_si128(&v7);\n a1[1] = _mm_load_si128(&v8);\n a1[2] = _mm_load_si128(&v9);\n a1[3] = _mm_load_si128(&v10);\n a1[4] = _mm_load_si128(&v11);\n a1[5] = _mm_load_si128(&v12);\n a1[6].m128i_i64[0] = v13;\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__m128i *sub_1189(__m128i *a1, char *a2) {\n char v2;\n const unsigned short *v3;\n char *v4;\n int v5;\n __m128i v7;\n __m128i v8;\n __m128i v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n long long v13;\n unsigned long long v14;\n v14 = __readfsqword(40u);\n v2 = *a2;\n if (*a2) {\n v3 = *__ctype_b_loc();\n v4 = a2 + 1;\n v5 = 0;\n do {\n if ((v3[v2] & 8192) == 0) v7.m128i_i8[v5++] = v2;\n v2 = *v4++;\n } while (v2);\n } else {\n v5 = 0;\n }\n HIDWORD(v13) = v5;\n *a1 = _mm_load_si128(&v7);\n a1[1] = _mm_load_si128(&v8);\n a1[2] = _mm_load_si128(&v9);\n a1[3] = _mm_load_si128(&v10);\n a1[4] = _mm_load_si128(&v11);\n a1[5] = _mm_load_si128(&v12);\n a1[6].m128i_i64[0] = v13;\n return a1;\n}", + "ida_pseudo_norm": "__m128i *func0(__m128i *a1, char *a2) {\n char v2;\n const unsigned short *v3;\n char *v4;\n int v5;\n __m128i v7;\n __m128i v8;\n __m128i v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n long long v13;\n unsigned long long v14;\n v14 = __readfsqword(40u);\n v2 = *a2;\n if (*a2) {\n v3 = *__ctype_b_loc();\n v4 = a2 + 1;\n v5 = 0;\n do {\n if ((v3[v2] & 8192) == 0) v7.m128i_i8[v5++] = v2;\n v2 = *v4++;\n } while (v2);\n } else {\n v5 = 0;\n }\n HIDWORD(v13) = v5;\n *a1 = _mm_load_si128(&v7);\n a1[1] = _mm_load_si128(&v8);\n a1[2] = _mm_load_si128(&v9);\n a1[3] = _mm_load_si128(&v10);\n a1[4] = _mm_load_si128(&v11);\n a1[5] = _mm_load_si128(&v12);\n a1[6].m128i_i64[0] = v13;\n return a1;\n}" + }, + { + "index": 538, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include\n\ntypedef struct {\n\n char values[100];\n\n int length;\n\n} tuple;\n\n\n\n", + "func": "tuple func0(const char *str1) {\n tuple result;\n int j = 0;\n for (int i = 0; str1[i] != '\\0'; i++) {\n if (!isspace(str1[i])) {\n result.values[j++] = str1[i];\n }\n }\n result.length = j;\n return result;\n}", + "test": "int main() {\n\n tuple result;\n\n \n\n result = func0(\"python 3.0\");\n\n char expected1[] = {'p', 'y', 't', 'h', 'o', 'n', '3', '.', '0'};\n\n int length1 = sizeof(expected1);\n\n assert(result.length == length1);\n\n for (int i = 0; i < length1; i++) {\n\n assert(result.values[i] == expected1[i]);\n\n }\n\n \n\n result = func0(\"bigdata\");\n\n char expected2[] = {'b', 'i', 'g', 'd', 'a', 't', 'a'};\n\n int length2 = sizeof(expected2);\n\n assert(result.length == length2);\n\n for (int i = 0; i < length2; i++) {\n\n assert(result.values[i] == expected2[i]);\n\n }\n\n\n\n result = func0(\"language\");\n\n char expected3[] = {'l', 'a', 'n', 'g', 'u', 'a', 'g','e'};\n\n int length3 = sizeof(expected3);\n\n assert(result.length == length3);\n\n for (int i = 0; i < length3; i++) {\n\n assert(result.values[i] == expected3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %rdi,%r12\npush %rbp\npush %rbx\nsub $0x70,%rsp\nmovzbl (%rsi),%ebx\nmov %fs:0x28,%rax\nmov %rax,0x68(%rsp)\nxor %eax,%eax\ntest %bl,%bl\nje 1460 \nmov %rsi,%rbp\ncallq 1090 <__ctype_b_loc@plt>\nlea 0x1(%rbp),%rsi\nxor %edx,%edx\nmov (%rax),%rcx\nnopl 0x0(%rax,%rax,1)\nmovsbq %bl,%rax\ntestb $0x20,0x1(%rcx,%rax,2)\njne 13e4 \nmovslq %edx,%rax\nadd $0x1,%edx\nmov %bl,(%rsp,%rax,1)\nmovzbl (%rsi),%ebx\nadd $0x1,%rsi\ntest %bl,%bl\njne 13d0 \nmovdqa (%rsp),%xmm0\nmovdqa 0x10(%rsp),%xmm1\nmov %edx,0x64(%rsp)\nmov 0x60(%rsp),%rax\nmovdqa 0x20(%rsp),%xmm2\nmovdqa 0x30(%rsp),%xmm3\nmovdqa 0x40(%rsp),%xmm4\nmovups %xmm0,(%r12)\nmov %rax,0x60(%r12)\nmovdqa 0x50(%rsp),%xmm5\nmovups %xmm1,0x10(%r12)\nmovups %xmm2,0x20(%r12)\nmovups %xmm3,0x30(%r12)\nmovups %xmm4,0x40(%r12)\nmovups %xmm5,0x50(%r12)\nmov 0x68(%rsp),%rax\nxor %fs:0x28,%rax\njne 1464 \nadd $0x70,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\nretq\nxor %edx,%edx\njmp 13ef \ncallq 1070 <__stack_chk_fail@plt>\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 70h\nmovzx ebx, byte ptr [rsi]\nmov rax, fs:28h\nmov [rsp+88h+var_20], rax\nxor eax, eax\ntest bl, bl\njz loc_1460\nmov rbp, rsi\ncall ___ctype_b_loc\nlea rsi, [rbp+1]\nxor edx, edx\nmov rcx, [rax]\nnop dword ptr [rax+rax+00h]\nloc_13D0:\nmovsx rax, bl\ntest byte ptr [rcx+rax*2+1], 20h\njnz short loc_13E4\nmovsxd rax, edx\nadd edx, 1\nmov byte ptr [rsp+rax+88h+var_88], bl\nloc_13E4:\nmovzx ebx, byte ptr [rsi]\nadd rsi, 1\ntest bl, bl\njnz short loc_13D0\nloc_13EF:\nmovdqa xmm0, [rsp+88h+var_88]\nmovdqa xmm1, [rsp+88h+var_78]\nmov [rsp+88h+var_24], edx\nmov rax, [rsp+60h]\nmovdqa xmm2, [rsp+88h+var_68]\nmovdqa xmm3, [rsp+88h+var_58]\nmovdqa xmm4, [rsp+88h+var_48]\nmovups xmmword ptr [r12], xmm0\nmovdqa xmm5, [rsp+88h+var_38]\nmov [r12+60h], rax\nmovups xmmword ptr [r12+10h], xmm1\nmovups xmmword ptr [r12+20h], xmm2\nmovups xmmword ptr [r12+30h], xmm3\nmovups xmmword ptr [r12+40h], xmm4\nmovups xmmword ptr [r12+50h], xmm5\nmov rax, [rsp+88h+var_20]\nsub rax, fs:28h\njnz short loc_1464\nadd rsp, 70h\nmov rax, r12\npop rbx\npop rbp\npop r12\nretn\nloc_1460:\nxor edx, edx\njmp short loc_13EF\nloc_1464:\ncall ___stack_chk_fail", + "ida_pseudo": "__m128i *__fastcall func0(__m128i *a1, __int8 *a2)\n{\n __int8 v2; // bl\n const unsigned __int16 **v3; // rax\n __int8 *v4; // rsi\n int v5; // edx\n const unsigned __int16 *v6; // rcx\n __int64 v7; // rax\n __m128i v8; // xmm0\n __m128i v9; // xmm1\n __int64 v10; // rax\n __m128i v11; // xmm2\n __m128i v12; // xmm3\n __m128i v13; // xmm4\n __m128i v14; // xmm5\n __m128i v16; // [rsp+0h] [rbp-88h] BYREF\n __m128i v17; // [rsp+10h] [rbp-78h] BYREF\n __m128i v18; // [rsp+20h] [rbp-68h] BYREF\n __m128i v19; // [rsp+30h] [rbp-58h] BYREF\n __m128i v20; // [rsp+40h] [rbp-48h] BYREF\n __m128i v21; // [rsp+50h] [rbp-38h] BYREF\n __int64 v22; // [rsp+60h] [rbp-28h]\n unsigned __int64 v23; // [rsp+68h] [rbp-20h]\n\n v2 = *a2;\n v23 = __readfsqword(0x28u);\n if ( v2 )\n {\n v3 = __ctype_b_loc();\n v4 = a2 + 1;\n v5 = 0;\n v6 = *v3;\n do\n {\n if ( (v6[v2] & 0x2000) == 0 )\n {\n v7 = v5++;\n v16.m128i_i8[v7] = v2;\n }\n v2 = *v4++;\n }\n while ( v2 );\n }\n else\n {\n v5 = 0;\n }\n v8 = _mm_load_si128(&v16);\n v9 = _mm_load_si128(&v17);\n HIDWORD(v22) = v5;\n v10 = v22;\n v11 = _mm_load_si128(&v18);\n v12 = _mm_load_si128(&v19);\n v13 = _mm_load_si128(&v20);\n *a1 = v8;\n v14 = _mm_load_si128(&v21);\n a1[6].m128i_i64[0] = v10;\n a1[1] = v9;\n a1[2] = v11;\n a1[3] = v12;\n a1[4] = v13;\n a1[5] = v14;\n return a1;\n}", + "ida_strip_asm": "sub_1390:\nendbr64\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 70h\nmovzx ebx, byte ptr [rsi]\nmov rax, fs:28h\nmov [rsp+88h+var_20], rax\nxor eax, eax\ntest bl, bl\njz loc_1460\nmov rbp, rsi\ncall ___ctype_b_loc\nlea rsi, [rbp+1]\nxor edx, edx\nmov rcx, [rax]\nnop dword ptr [rax+rax+00h]\nloc_13D0:\nmovsx rax, bl\ntest byte ptr [rcx+rax*2+1], 20h\njnz short loc_13E4\nmovsxd rax, edx\nadd edx, 1\nmov byte ptr [rsp+rax+88h+var_88], bl\nloc_13E4:\nmovzx ebx, byte ptr [rsi]\nadd rsi, 1\ntest bl, bl\njnz short loc_13D0\nloc_13EF:\nmovdqa xmm0, [rsp+88h+var_88]\nmovdqa xmm1, [rsp+88h+var_78]\nmov [rsp+88h+var_24], edx\nmov rax, [rsp+60h]\nmovdqa xmm2, [rsp+88h+var_68]\nmovdqa xmm3, [rsp+88h+var_58]\nmovdqa xmm4, [rsp+88h+var_48]\nmovups xmmword ptr [r12], xmm0\nmovdqa xmm5, [rsp+88h+var_38]\nmov [r12+60h], rax\nmovups xmmword ptr [r12+10h], xmm1\nmovups xmmword ptr [r12+20h], xmm2\nmovups xmmword ptr [r12+30h], xmm3\nmovups xmmword ptr [r12+40h], xmm4\nmovups xmmword ptr [r12+50h], xmm5\nmov rax, [rsp+88h+var_20]\nsub rax, fs:28h\njnz short loc_1464\nadd rsp, 70h\nmov rax, r12\npop rbx\npop rbp\npop r12\nretn\nloc_1460:\nxor edx, edx\njmp short loc_13EF\nloc_1464:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__m128i *__fastcall sub_1390(__m128i *a1, __int8 *a2)\n{\n __int8 v2; // bl\n const unsigned __int16 **v3; // rax\n __int8 *v4; // rsi\n int v5; // edx\n const unsigned __int16 *v6; // rcx\n __int64 v7; // rax\n __m128i v8; // xmm0\n __m128i v9; // xmm1\n __int64 v10; // rax\n __m128i v11; // xmm2\n __m128i v12; // xmm3\n __m128i v13; // xmm4\n __m128i v14; // xmm5\n __m128i v16; // [rsp+0h] [rbp-88h] BYREF\n __m128i v17; // [rsp+10h] [rbp-78h] BYREF\n __m128i v18; // [rsp+20h] [rbp-68h] BYREF\n __m128i v19; // [rsp+30h] [rbp-58h] BYREF\n __m128i v20; // [rsp+40h] [rbp-48h] BYREF\n __m128i v21; // [rsp+50h] [rbp-38h] BYREF\n __int64 v22; // [rsp+60h] [rbp-28h]\n unsigned __int64 v23; // [rsp+68h] [rbp-20h]\n\n v2 = *a2;\n v23 = __readfsqword(0x28u);\n if ( v2 )\n {\n v3 = __ctype_b_loc();\n v4 = a2 + 1;\n v5 = 0;\n v6 = *v3;\n do\n {\n if ( (v6[v2] & 0x2000) == 0 )\n {\n v7 = v5++;\n v16.m128i_i8[v7] = v2;\n }\n v2 = *v4++;\n }\n while ( v2 );\n }\n else\n {\n v5 = 0;\n }\n v8 = _mm_load_si128(&v16);\n v9 = _mm_load_si128(&v17);\n HIDWORD(v22) = v5;\n v10 = v22;\n v11 = _mm_load_si128(&v18);\n v12 = _mm_load_si128(&v19);\n v13 = _mm_load_si128(&v20);\n *a1 = v8;\n v14 = _mm_load_si128(&v21);\n a1[6].m128i_i64[0] = v10;\n a1[1] = v9;\n a1[2] = v11;\n a1[3] = v12;\n a1[4] = v13;\n a1[5] = v14;\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__m128i *sub_1390(__m128i *a1, char *a2) {\n char v2;\n const unsigned short **v3;\n char *v4;\n int v5;\n const unsigned short *v6;\n long long v7;\n __m128i v8;\n __m128i v9;\n long long v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n __m128i v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n __m128i v20;\n __m128i v21;\n long long v22;\n unsigned long long v23;\n v2 = *a2;\n v23 = __readfsqword(40u);\n if (v2) {\n v3 = __ctype_b_loc();\n v4 = a2 + 1;\n v5 = 0;\n v6 = *v3;\n do {\n if ((v6[v2] & 8192) == 0) {\n v7 = v5++;\n v16.m128i_i8[v7] = v2;\n }\n v2 = *v4++;\n } while (v2);\n } else {\n v5 = 0;\n }\n v8 = _mm_load_si128(&v16);\n v9 = _mm_load_si128(&v17);\n HIDWORD(v22) = v5;\n v10 = v22;\n v11 = _mm_load_si128(&v18);\n v12 = _mm_load_si128(&v19);\n v13 = _mm_load_si128(&v20);\n *a1 = v8;\n v14 = _mm_load_si128(&v21);\n a1[6].m128i_i64[0] = v10;\n a1[1] = v9;\n a1[2] = v11;\n a1[3] = v12;\n a1[4] = v13;\n a1[5] = v14;\n return a1;\n}", + "ida_pseudo_norm": "__m128i *func0(__m128i *a1, char *a2) {\n char v2;\n const unsigned short **v3;\n char *v4;\n int v5;\n const unsigned short *v6;\n long long v7;\n __m128i v8;\n __m128i v9;\n long long v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n __m128i v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n __m128i v20;\n __m128i v21;\n long long v22;\n unsigned long long v23;\n v2 = *a2;\n v23 = __readfsqword(40u);\n if (v2) {\n v3 = __ctype_b_loc();\n v4 = a2 + 1;\n v5 = 0;\n v6 = *v3;\n do {\n if ((v6[v2] & 8192) == 0) {\n v7 = v5++;\n v16.m128i_i8[v7] = v2;\n }\n v2 = *v4++;\n } while (v2);\n } else {\n v5 = 0;\n }\n v8 = _mm_load_si128(&v16);\n v9 = _mm_load_si128(&v17);\n HIDWORD(v22) = v5;\n v10 = v22;\n v11 = _mm_load_si128(&v18);\n v12 = _mm_load_si128(&v19);\n v13 = _mm_load_si128(&v20);\n *a1 = v8;\n v14 = _mm_load_si128(&v21);\n a1[6].m128i_i64[0] = v10;\n a1[1] = v9;\n a1[2] = v11;\n a1[3] = v12;\n a1[4] = v13;\n a1[5] = v14;\n return a1;\n}" + }, + { + "index": 538, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include\n\ntypedef struct {\n\n char values[100];\n\n int length;\n\n} tuple;\n\n\n\n", + "func": "tuple func0(const char *str1) {\n tuple result;\n int j = 0;\n for (int i = 0; str1[i] != '\\0'; i++) {\n if (!isspace(str1[i])) {\n result.values[j++] = str1[i];\n }\n }\n result.length = j;\n return result;\n}", + "test": "int main() {\n\n tuple result;\n\n \n\n result = func0(\"python 3.0\");\n\n char expected1[] = {'p', 'y', 't', 'h', 'o', 'n', '3', '.', '0'};\n\n int length1 = sizeof(expected1);\n\n assert(result.length == length1);\n\n for (int i = 0; i < length1; i++) {\n\n assert(result.values[i] == expected1[i]);\n\n }\n\n \n\n result = func0(\"bigdata\");\n\n char expected2[] = {'b', 'i', 'g', 'd', 'a', 't', 'a'};\n\n int length2 = sizeof(expected2);\n\n assert(result.length == length2);\n\n for (int i = 0; i < length2; i++) {\n\n assert(result.values[i] == expected2[i]);\n\n }\n\n\n\n result = func0(\"language\");\n\n char expected3[] = {'l', 'a', 'n', 'g', 'u', 'a', 'g','e'};\n\n int length3 = sizeof(expected3);\n\n assert(result.length == length3);\n\n for (int i = 0; i < length3; i++) {\n\n assert(result.values[i] == expected3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %rdi,%r12\npush %rbp\npush %rbx\nsub $0x70,%rsp\nmovzbl (%rsi),%ebx\nmov %fs:0x28,%rax\nmov %rax,0x68(%rsp)\nxor %eax,%eax\ntest %bl,%bl\nje 1550 \nmov %rsi,%rbp\ncallq 1090 <__ctype_b_loc@plt>\nlea 0x1(%rbp),%rsi\nmov (%rax),%rcx\nxor %eax,%eax\nnopl 0x0(%rax,%rax,1)\nmovsbq %bl,%rdx\ntestb $0x20,0x1(%rcx,%rdx,2)\njne 14cb \nadd $0x1,%rsi\nmov %bl,(%rsp,%rax,1)\nlea 0x1(%rax),%edx\nmovzbl -0x1(%rsi),%ebx\ntest %bl,%bl\nje 14d8 \nmovslq %edx,%rax\nmovsbq %bl,%rdx\ntestb $0x20,0x1(%rcx,%rdx,2)\nje 14ab \nmovzbl (%rsi),%ebx\nadd $0x1,%rsi\ntest %bl,%bl\njne 14a0 \nmov %eax,%edx\nmovdqa (%rsp),%xmm0\nmovdqa 0x10(%rsp),%xmm1\nmov %edx,0x64(%rsp)\nmov 0x60(%rsp),%rax\nmovdqa 0x20(%rsp),%xmm2\nmovdqa 0x30(%rsp),%xmm3\nmovdqa 0x40(%rsp),%xmm4\nmovups %xmm0,(%r12)\nmov %rax,0x60(%r12)\nmovdqa 0x50(%rsp),%xmm5\nmovups %xmm1,0x10(%r12)\nmovups %xmm2,0x20(%r12)\nmovups %xmm3,0x30(%r12)\nmovups %xmm4,0x40(%r12)\nmovups %xmm5,0x50(%r12)\nmov 0x68(%rsp),%rax\nxor %fs:0x28,%rax\njne 1554 \nadd $0x70,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax,%rax,1)\nxor %edx,%edx\njmp 14d8 \ncallq 1070 <__stack_chk_fail@plt>\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 70h\nmovzx ebx, byte ptr [rsi]\nmov rax, fs:28h\nmov [rsp+88h+var_20], rax\nxor eax, eax\ntest bl, bl\njz loc_14B8\nmov rbp, rsi\ncall ___ctype_b_loc\nlea rsi, [rbp+1]\nmov rcx, [rax]\nxor eax, eax\nnop dword ptr [rax+rax+00h]\nloc_1400:\nmovsx rdx, bl\ntest byte ptr [rcx+rdx*2+1], 20h\njnz short loc_142F\nloc_140B:\nadd rsi, 1\nmov byte ptr [rsp+rax+88h+var_88], bl\nlea edx, [rax+1]\nmovzx ebx, byte ptr [rsi-1]\ntest bl, bl\njz loc_14B0\nmovsxd rax, edx\nmovsx rdx, bl\ntest byte ptr [rcx+rdx*2+1], 20h\njz short loc_140B\nloc_142F:\nmovzx ebx, byte ptr [rsi]\nadd rsi, 1\ntest bl, bl\njnz short loc_1400\nloc_143A:\nmovdqa xmm0, [rsp+88h+var_88]\nmovdqa xmm1, [rsp+88h+var_78]\nmov [rsp+88h+var_24], eax\nmov rax, [rsp+60h]\nmovdqa xmm2, [rsp+88h+var_68]\nmovdqa xmm3, [rsp+88h+var_58]\nmovdqa xmm4, [rsp+88h+var_48]\nmovups xmmword ptr [r12], xmm0\nmovdqa xmm5, [rsp+88h+var_38]\nmov [r12+60h], rax\nmovups xmmword ptr [r12+10h], xmm1\nmovups xmmword ptr [r12+20h], xmm2\nmovups xmmword ptr [r12+30h], xmm3\nmovups xmmword ptr [r12+40h], xmm4\nmovups xmmword ptr [r12+50h], xmm5\nmov rax, [rsp+88h+var_20]\nsub rax, fs:28h\njnz short loc_14BF\nadd rsp, 70h\nmov rax, r12\npop rbx\npop rbp\npop r12\nretn\nloc_14B0:\nmov eax, edx\njmp short loc_143A\nloc_14B8:\nxor eax, eax\njmp loc_143A\nloc_14BF:\ncall ___stack_chk_fail", + "ida_pseudo": "__m128i *__fastcall func0(__m128i *a1, __int8 *a2)\n{\n __int8 v2; // bl\n __int8 *v3; // rsi\n const unsigned __int16 *v4; // rcx\n __int64 v5; // rax\n __m128i v6; // xmm0\n __m128i v7; // xmm1\n __int64 v8; // rax\n __m128i v9; // xmm2\n __m128i v10; // xmm3\n __m128i v11; // xmm4\n __m128i v12; // xmm5\n __m128i v14; // [rsp+0h] [rbp-88h] BYREF\n __m128i v15; // [rsp+10h] [rbp-78h] BYREF\n __m128i v16; // [rsp+20h] [rbp-68h] BYREF\n __m128i v17; // [rsp+30h] [rbp-58h] BYREF\n __m128i v18; // [rsp+40h] [rbp-48h] BYREF\n __m128i v19; // [rsp+50h] [rbp-38h] BYREF\n __int64 v20; // [rsp+60h] [rbp-28h]\n unsigned __int64 v21; // [rsp+68h] [rbp-20h]\n\n v2 = *a2;\n v21 = __readfsqword(0x28u);\n if ( v2 )\n {\n v3 = a2 + 1;\n v4 = *__ctype_b_loc();\n v5 = 0LL;\n while ( (v4[v2] & 0x2000) != 0 )\n {\nLABEL_6:\n v2 = *v3++;\n if ( !v2 )\n goto LABEL_7;\n }\n while ( 1 )\n {\n ++v3;\n v14.m128i_i8[v5] = v2;\n v2 = *(v3 - 1);\n if ( !v2 )\n break;\n v5 = (int)v5 + 1;\n if ( (v4[v2] & 0x2000) != 0 )\n goto LABEL_6;\n }\n LODWORD(v5) = v5 + 1;\n }\n else\n {\n LODWORD(v5) = 0;\n }\nLABEL_7:\n v6 = _mm_load_si128(&v14);\n v7 = _mm_load_si128(&v15);\n HIDWORD(v20) = v5;\n v8 = v20;\n v9 = _mm_load_si128(&v16);\n v10 = _mm_load_si128(&v17);\n v11 = _mm_load_si128(&v18);\n *a1 = v6;\n v12 = _mm_load_si128(&v19);\n a1[6].m128i_i64[0] = v8;\n a1[1] = v7;\n a1[2] = v9;\n a1[3] = v10;\n a1[4] = v11;\n a1[5] = v12;\n return a1;\n}", + "ida_strip_asm": "sub_13C0:\nendbr64\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 70h\nmovzx ebx, byte ptr [rsi]\nmov rax, fs:28h\nmov [rsp+88h+var_20], rax\nxor eax, eax\ntest bl, bl\njz loc_14B8\nmov rbp, rsi\ncall ___ctype_b_loc\nlea rsi, [rbp+1]\nmov rcx, [rax]\nxor eax, eax\nnop dword ptr [rax+rax+00h]\nloc_1400:\nmovsx rdx, bl\ntest byte ptr [rcx+rdx*2+1], 20h\njnz short loc_142F\nloc_140B:\nadd rsi, 1\nmov byte ptr [rsp+rax+88h+var_88], bl\nlea edx, [rax+1]\nmovzx ebx, byte ptr [rsi-1]\ntest bl, bl\njz loc_14B0\nmovsxd rax, edx\nmovsx rdx, bl\ntest byte ptr [rcx+rdx*2+1], 20h\njz short loc_140B\nloc_142F:\nmovzx ebx, byte ptr [rsi]\nadd rsi, 1\ntest bl, bl\njnz short loc_1400\nloc_143A:\nmovdqa xmm0, [rsp+88h+var_88]\nmovdqa xmm1, [rsp+88h+var_78]\nmov [rsp+88h+var_24], eax\nmov rax, [rsp+60h]\nmovdqa xmm2, [rsp+88h+var_68]\nmovdqa xmm3, [rsp+88h+var_58]\nmovdqa xmm4, [rsp+88h+var_48]\nmovups xmmword ptr [r12], xmm0\nmovdqa xmm5, [rsp+88h+var_38]\nmov [r12+60h], rax\nmovups xmmword ptr [r12+10h], xmm1\nmovups xmmword ptr [r12+20h], xmm2\nmovups xmmword ptr [r12+30h], xmm3\nmovups xmmword ptr [r12+40h], xmm4\nmovups xmmword ptr [r12+50h], xmm5\nmov rax, [rsp+88h+var_20]\nsub rax, fs:28h\njnz short loc_14BF\nadd rsp, 70h\nmov rax, r12\npop rbx\npop rbp\npop r12\nretn\nloc_14B0:\nmov eax, edx\njmp short loc_143A\nloc_14B8:\nxor eax, eax\njmp loc_143A\nloc_14BF:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__m128i *__fastcall sub_13C0(__m128i *a1, __int8 *a2)\n{\n __int8 v2; // bl\n __int8 *v3; // rsi\n const unsigned __int16 *v4; // rcx\n __int64 v5; // rax\n __m128i v6; // xmm0\n __m128i v7; // xmm1\n __int64 v8; // rax\n __m128i v9; // xmm2\n __m128i v10; // xmm3\n __m128i v11; // xmm4\n __m128i v12; // xmm5\n __m128i v14; // [rsp+0h] [rbp-88h] BYREF\n __m128i v15; // [rsp+10h] [rbp-78h] BYREF\n __m128i v16; // [rsp+20h] [rbp-68h] BYREF\n __m128i v17; // [rsp+30h] [rbp-58h] BYREF\n __m128i v18; // [rsp+40h] [rbp-48h] BYREF\n __m128i v19; // [rsp+50h] [rbp-38h] BYREF\n __int64 v20; // [rsp+60h] [rbp-28h]\n unsigned __int64 v21; // [rsp+68h] [rbp-20h]\n\n v2 = *a2;\n v21 = __readfsqword(0x28u);\n if ( v2 )\n {\n v3 = a2 + 1;\n v4 = *__ctype_b_loc();\n v5 = 0LL;\n while ( (v4[v2] & 0x2000) != 0 )\n {\nLABEL_6:\n v2 = *v3++;\n if ( !v2 )\n goto LABEL_7;\n }\n while ( 1 )\n {\n ++v3;\n v14.m128i_i8[v5] = v2;\n v2 = *(v3 - 1);\n if ( !v2 )\n break;\n v5 = (int)v5 + 1;\n if ( (v4[v2] & 0x2000) != 0 )\n goto LABEL_6;\n }\n LODWORD(v5) = v5 + 1;\n }\n else\n {\n LODWORD(v5) = 0;\n }\nLABEL_7:\n v6 = _mm_load_si128(&v14);\n v7 = _mm_load_si128(&v15);\n HIDWORD(v20) = v5;\n v8 = v20;\n v9 = _mm_load_si128(&v16);\n v10 = _mm_load_si128(&v17);\n v11 = _mm_load_si128(&v18);\n *a1 = v6;\n v12 = _mm_load_si128(&v19);\n a1[6].m128i_i64[0] = v8;\n a1[1] = v7;\n a1[2] = v9;\n a1[3] = v10;\n a1[4] = v11;\n a1[5] = v12;\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__m128i *sub_13C0(__m128i *a1, char *a2) {\n char v2;\n char *v3;\n const unsigned short *v4;\n long long v5;\n __m128i v6;\n __m128i v7;\n long long v8;\n __m128i v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n __m128i v14;\n __m128i v15;\n __m128i v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n long long v20;\n unsigned long long v21;\n v2 = *a2;\n v21 = __readfsqword(40u);\n if (v2) {\n v3 = a2 + 1;\n v4 = *__ctype_b_loc();\n v5 = 0LL;\n while ((v4[v2] & 8192) != 0) {\n LABEL_6:\n v2 = *v3++;\n if (!v2) goto LABEL_7;\n }\n while (1) {\n ++v3;\n v14.m128i_i8[v5] = v2;\n v2 = *(v3 - 1);\n if (!v2) break;\n v5 = (int)v5 + 1;\n if ((v4[v2] & 8192) != 0) goto LABEL_6;\n }\n LODWORD(v5) = v5 + 1;\n } else {\n LODWORD(v5) = 0;\n }\nLABEL_7:\n v6 = _mm_load_si128(&v14);\n v7 = _mm_load_si128(&v15);\n HIDWORD(v20) = v5;\n v8 = v20;\n v9 = _mm_load_si128(&v16);\n v10 = _mm_load_si128(&v17);\n v11 = _mm_load_si128(&v18);\n *a1 = v6;\n v12 = _mm_load_si128(&v19);\n a1[6].m128i_i64[0] = v8;\n a1[1] = v7;\n a1[2] = v9;\n a1[3] = v10;\n a1[4] = v11;\n a1[5] = v12;\n return a1;\n}", + "ida_pseudo_norm": "__m128i *func0(__m128i *a1, char *a2) {\n char v2;\n char *v3;\n const unsigned short *v4;\n long long v5;\n __m128i v6;\n __m128i v7;\n long long v8;\n __m128i v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n __m128i v14;\n __m128i v15;\n __m128i v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n long long v20;\n unsigned long long v21;\n v2 = *a2;\n v21 = __readfsqword(40u);\n if (v2) {\n v3 = a2 + 1;\n v4 = *__ctype_b_loc();\n v5 = 0LL;\n while ((v4[v2] & 8192) != 0) {\n LABEL_6:\n v2 = *v3++;\n if (!v2) goto LABEL_7;\n }\n while (1) {\n ++v3;\n v14.m128i_i8[v5] = v2;\n v2 = *(v3 - 1);\n if (!v2) break;\n v5 = (int)v5 + 1;\n if ((v4[v2] & 8192) != 0) goto LABEL_6;\n }\n LODWORD(v5) = v5 + 1;\n } else {\n LODWORD(v5) = 0;\n }\nLABEL_7:\n v6 = _mm_load_si128(&v14);\n v7 = _mm_load_si128(&v15);\n HIDWORD(v20) = v5;\n v8 = v20;\n v9 = _mm_load_si128(&v16);\n v10 = _mm_load_si128(&v17);\n v11 = _mm_load_si128(&v18);\n *a1 = v6;\n v12 = _mm_load_si128(&v19);\n a1[6].m128i_i64[0] = v8;\n a1[1] = v7;\n a1[2] = v9;\n a1[3] = v10;\n a1[4] = v11;\n a1[5] = v12;\n return a1;\n}" + }, + { + "index": 539, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "double* func0(int bases_num[], int index[], int length, double result[]) {\n for (int i = 0; i < length; i++) {\n result[i] = pow(bases_num[i], index[i]);\n }\n return result;\n}", + "test": "int main() {\n\n int bases_num1[] = {10, 20, 30, 40, 50, 60, 70, 80, 90, 100};\n\n int index1[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n double expected1[] = {10, 400, 27000, 2560000, 312500000, 46656000000, 8235430000000, 1677721600000000, 387420489000000000, 100000000000000000000.0};\n\n double result1[10];\n\n func0(bases_num1, index1, 10, result1);\n\n for (int i = 0; i < 10; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n\n\n int bases_num2[] = {1, 2, 3, 4, 5, 6, 7};\n\n int index2[] = {10, 20, 30, 40, 50, 60, 70};\n\n double expected2[] = {1, 1048576, 205891132094649.0, 1208925819614629174706176.0, 88817841970012523233890533447265625.0, 48873677980689257489322752273774603865660850176.0, 143503601609868434285603076356671071740077383739246066639249.0};\n\n double result2[7];\n\n func0(bases_num2, index2, 7, result2);\n\n for (int i = 0; i < 7; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n\n\n int bases_num3[] = {4, 8, 12, 16, 20, 24, 28};\n\n int index3[] = {3, 6, 9, 12, 15, 18, 21};\n\n double expected3[] = {64, 262144, 5159780352.0, 281474976710656.0, 32768000000000000000.0, 6979147079584381377970176.0, 2456510688823056210273111113728.0};\n\n double result3[7];\n\n func0(bases_num3, index3, 7, result3);\n\n for (int i = 0; i < 7; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x38,%rsp\nmov %rdi,-0x28(%rbp)\nmov %rsi,-0x30(%rbp)\nmov %edx,-0x34(%rbp)\nmov %rcx,-0x40(%rbp)\nmovl $0x0,-0x14(%rbp)\njmp 1208 \nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x30(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncvtsi2sd %eax,%xmm1\nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncvtsi2sd %eax,%xmm0\nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x40(%rbp),%rax\nlea (%rdx,%rax,1),%rbx\ncallq 1070 \nmovq %xmm0,%rax\nmov %rax,(%rbx)\naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\ncmp -0x34(%rbp),%eax\njl 11ae \nmov -0x40(%rbp),%rax\nadd $0x38,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+var_28], rdi\nmov [rbp+var_30], rsi\nmov [rbp+var_34], edx\nmov [rbp+var_40], rcx\nmov [rbp+var_14], 0\njmp short loc_121F\nloc_11AE:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov eax, [rax]\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\npxor xmm2, xmm2\ncvtsi2sd xmm2, eax\nmovq rax, xmm2\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_40]\nlea rbx, [rcx+rdx]\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\nmovq rax, xmm0\nmov [rbx], rax\nadd [rbp+var_14], 1\nloc_121F:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_34]\njl short loc_11AE\nmov rax, [rbp+var_40]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3, __int64 a4)\n{\n int i; // [rsp+2Ch] [rbp-14h]\n\n for ( i = 0; i < a3; ++i )\n *(double *)(8LL * i + a4) = pow((double)*(int *)(4LL * i + a1), (double)*(int *)(4LL * i + a2));\n return a4;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+var_28], rdi\nmov [rbp+var_30], rsi\nmov [rbp+var_34], edx\nmov [rbp+var_40], rcx\nmov [rbp+var_14], 0\njmp short loc_121F\nloc_11AE:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov eax, [rax]\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\npxor xmm2, xmm2\ncvtsi2sd xmm2, eax\nmovq rax, xmm2\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_40]\nlea rbx, [rcx+rdx]\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\nmovq rax, xmm0\nmov [rbx], rax\nadd [rbp+var_14], 1\nloc_121F:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_34]\njl short loc_11AE\nmov rax, [rbp+var_40]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, __int64 a2, int a3, __int64 a4)\n{\n int i; // [rsp+2Ch] [rbp-14h]\n\n for ( i = 0; i < a3; ++i )\n *(double *)(8LL * i + a4) = pow((double)*(int *)(4LL * i + a1), (double)*(int *)(4LL * i + a2));\n return a4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, long long a2, int a3, long long a4) {\n int i;\n for (i = 0; i < a3; ++i)\n *(double *)(8LL * i + a4) =\n pow((double)*(int *)(4LL * i + a1), (double)*(int *)(4LL * i + a2));\n return a4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3, long long a4) {\n int i;\n for (i = 0; i < a3; ++i)\n *(double *)(8LL * i + a4) =\n pow((double)*(int *)(4LL * i + a1), (double)*(int *)(4LL * i + a2));\n return a4;\n}" + }, + { + "index": 539, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "double* func0(int bases_num[], int index[], int length, double result[]) {\n for (int i = 0; i < length; i++) {\n result[i] = pow(bases_num[i], index[i]);\n }\n return result;\n}", + "test": "int main() {\n\n int bases_num1[] = {10, 20, 30, 40, 50, 60, 70, 80, 90, 100};\n\n int index1[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n double expected1[] = {10, 400, 27000, 2560000, 312500000, 46656000000, 8235430000000, 1677721600000000, 387420489000000000, 100000000000000000000.0};\n\n double result1[10];\n\n func0(bases_num1, index1, 10, result1);\n\n for (int i = 0; i < 10; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n\n\n int bases_num2[] = {1, 2, 3, 4, 5, 6, 7};\n\n int index2[] = {10, 20, 30, 40, 50, 60, 70};\n\n double expected2[] = {1, 1048576, 205891132094649.0, 1208925819614629174706176.0, 88817841970012523233890533447265625.0, 48873677980689257489322752273774603865660850176.0, 143503601609868434285603076356671071740077383739246066639249.0};\n\n double result2[7];\n\n func0(bases_num2, index2, 7, result2);\n\n for (int i = 0; i < 7; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n\n\n int bases_num3[] = {4, 8, 12, 16, 20, 24, 28};\n\n int index3[] = {3, 6, 9, 12, 15, 18, 21};\n\n double expected3[] = {64, 262144, 5159780352.0, 281474976710656.0, 32768000000000000000.0, 6979147079584381377970176.0, 2456510688823056210273111113728.0};\n\n double result3[7];\n\n func0(bases_num3, index3, 7, result3);\n\n for (int i = 0; i < 7; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %rcx,%rbp\ntest %edx,%edx\njle 11d7 \nmov %rdi,%r12\nmov %rsi,%r13\nlea -0x1(%rdx),%r14d\nmov $0x0,%ebx\npxor %xmm0,%xmm0\ncvtsi2sdl (%r12,%rbx,4),%xmm0\npxor %xmm1,%xmm1\ncvtsi2sdl 0x0(%r13,%rbx,4),%xmm1\ncallq 1070 \nmovsd %xmm0,0x0(%rbp,%rbx,8)\nmov %rbx,%rax\nadd $0x1,%rbx\ncmp %r14,%rax\njne 11ab \nmov %rbp,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r12, rcx\ntest edx, edx\njle short loc_11DB\nmov r13, rdi\nmov r14, rsi\nmovsxd rdx, edx\nlea rbp, ds:0[rdx*4]\nmov ebx, 0\nloc_11B2:\npxor xmm0, xmm0\ncvtsi2sd xmm0, dword ptr [r13+rbx+0]; x\npxor xmm1, xmm1\ncvtsi2sd xmm1, dword ptr [r14+rbx]; y\ncall _pow\nmovsd qword ptr [r12+rbx*2], xmm0\nadd rbx, 4\ncmp rbx, rbp\njnz short loc_11B2\nloc_11DB:\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3, __int64 a4)\n{\n __int64 v5; // rbp\n __int64 v6; // rbx\n\n if ( a3 > 0 )\n {\n v5 = 4LL * a3;\n v6 = 0LL;\n do\n {\n *(double *)(a4 + 2 * v6) = pow((double)*(int *)(a1 + v6), (double)*(int *)(a2 + v6));\n v6 += 4LL;\n }\n while ( v6 != v5 );\n }\n return a4;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r12, rcx\ntest edx, edx\njle short loc_11DB\nmov r13, rdi\nmov r14, rsi\nmovsxd rdx, edx\nlea rbp, ds:0[rdx*4]\nmov ebx, 0\nloc_11B2:\npxor xmm0, xmm0\ncvtsi2sd xmm0, dword ptr [r13+rbx+0]; x\npxor xmm1, xmm1\ncvtsi2sd xmm1, dword ptr [r14+rbx]; y\ncall _pow\nmovsd qword ptr [r12+rbx*2], xmm0\nadd rbx, 4\ncmp rbx, rbp\njnz short loc_11B2\nloc_11DB:\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, __int64 a2, int a3, __int64 a4)\n{\n __int64 v5; // rbp\n __int64 v6; // rbx\n\n if ( a3 > 0 )\n {\n v5 = 4LL * a3;\n v6 = 0LL;\n do\n {\n *(double *)(a4 + 2 * v6) = pow((double)*(int *)(a1 + v6), (double)*(int *)(a2 + v6));\n v6 += 4LL;\n }\n while ( v6 != v5 );\n }\n return a4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, long long a2, int a3, long long a4) {\n long long v5;\n long long v6;\n if (a3 > 0) {\n v5 = 4LL * a3;\n v6 = 0LL;\n do {\n *(double *)(a4 + 2 * v6) =\n pow((double)*(int *)(a1 + v6), (double)*(int *)(a2 + v6));\n v6 += 4LL;\n } while (v6 != v5);\n }\n return a4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3, long long a4) {\n long long v5;\n long long v6;\n if (a3 > 0) {\n v5 = 4LL * a3;\n v6 = 0LL;\n do {\n *(double *)(a4 + 2 * v6) =\n pow((double)*(int *)(a1 + v6), (double)*(int *)(a2 + v6));\n v6 += 4LL;\n } while (v6 != v5);\n }\n return a4;\n}" + }, + { + "index": 539, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "double* func0(int bases_num[], int index[], int length, double result[]) {\n for (int i = 0; i < length; i++) {\n result[i] = pow(bases_num[i], index[i]);\n }\n return result;\n}", + "test": "int main() {\n\n int bases_num1[] = {10, 20, 30, 40, 50, 60, 70, 80, 90, 100};\n\n int index1[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n double expected1[] = {10, 400, 27000, 2560000, 312500000, 46656000000, 8235430000000, 1677721600000000, 387420489000000000, 100000000000000000000.0};\n\n double result1[10];\n\n func0(bases_num1, index1, 10, result1);\n\n for (int i = 0; i < 10; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n\n\n int bases_num2[] = {1, 2, 3, 4, 5, 6, 7};\n\n int index2[] = {10, 20, 30, 40, 50, 60, 70};\n\n double expected2[] = {1, 1048576, 205891132094649.0, 1208925819614629174706176.0, 88817841970012523233890533447265625.0, 48873677980689257489322752273774603865660850176.0, 143503601609868434285603076356671071740077383739246066639249.0};\n\n double result2[7];\n\n func0(bases_num2, index2, 7, result2);\n\n for (int i = 0; i < 7; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n\n\n int bases_num3[] = {4, 8, 12, 16, 20, 24, 28};\n\n int index3[] = {3, 6, 9, 12, 15, 18, 21};\n\n double expected3[] = {64, 262144, 5159780352.0, 281474976710656.0, 32768000000000000000.0, 6979147079584381377970176.0, 2456510688823056210273111113728.0};\n\n double result3[7];\n\n func0(bases_num3, index3, 7, result3);\n\n for (int i = 0; i < 7; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\nmov %rcx,%r12\npush %rbp\npush %rbx\ntest %edx,%edx\njle 163c \nmov %rdi,%rbp\nmov %rsi,%r13\nlea -0x1(%rdx),%r14d\nxor %ebx,%ebx\npxor %xmm0,%xmm0\npxor %xmm1,%xmm1\ncvtsi2sdl 0x0(%rbp,%rbx,4),%xmm0\ncvtsi2sdl 0x0(%r13,%rbx,4),%xmm1\ncallq 1070 \nmov %rbx,%rax\nmovsd %xmm0,(%r12,%rbx,8)\nadd $0x1,%rbx\ncmp %r14,%rax\njne 1610 \npop %rbx\nmov %r12,%rax\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\nmov r12, rcx\npush rbp\npush rbx\ntest edx, edx\njle short loc_1529\nmovsxd rdx, edx\nmov r13, rdi\nmov r14, rsi\nxor ebx, ebx\nlea rbp, ds:0[rdx*4]\nnop word ptr [rax+rax+00000000h]\nloc_1500:\npxor xmm0, xmm0\npxor xmm1, xmm1\ncvtsi2sd xmm0, dword ptr [r13+rbx+0]; x\ncvtsi2sd xmm1, dword ptr [r14+rbx]; y\ncall _pow\nmovsd qword ptr [r12+rbx*2], xmm0\nadd rbx, 4\ncmp rbp, rbx\njnz short loc_1500\nloc_1529:\npop rbx\nmov rax, r12\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3, __int64 a4)\n{\n __int64 v5; // rbx\n __int64 v6; // rbp\n\n if ( a3 > 0 )\n {\n v5 = 0LL;\n v6 = 4LL * a3;\n do\n {\n *(double *)(a4 + 2 * v5) = pow((double)*(int *)(a1 + v5), (double)*(int *)(a2 + v5));\n v5 += 4LL;\n }\n while ( v6 != v5 );\n }\n return a4;\n}", + "ida_strip_asm": "sub_14D0:\nendbr64\npush r14\npush r13\npush r12\nmov r12, rcx\npush rbp\npush rbx\ntest edx, edx\njle short loc_1529\nmovsxd rdx, edx\nmov r13, rdi\nmov r14, rsi\nxor ebx, ebx\nlea rbp, ds:0[rdx*4]\nnop word ptr [rax+rax+00000000h]\nloc_1500:\npxor xmm0, xmm0\npxor xmm1, xmm1\ncvtsi2sd xmm0, dword ptr [r13+rbx+0]; x\ncvtsi2sd xmm1, dword ptr [r14+rbx]; y\ncall _pow\nmovsd qword ptr [r12+rbx*2], xmm0\nadd rbx, 4\ncmp rbp, rbx\njnz short loc_1500\nloc_1529:\npop rbx\nmov rax, r12\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_14D0(__int64 a1, __int64 a2, int a3, __int64 a4)\n{\n __int64 v5; // rbx\n __int64 v6; // rbp\n\n if ( a3 > 0 )\n {\n v5 = 0LL;\n v6 = 4LL * a3;\n do\n {\n *(double *)(a4 + 2 * v5) = pow((double)*(int *)(a1 + v5), (double)*(int *)(a2 + v5));\n v5 += 4LL;\n }\n while ( v6 != v5 );\n }\n return a4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_14D0(long long a1, long long a2, int a3, long long a4) {\n long long v5;\n long long v6;\n if (a3 > 0) {\n v5 = 0LL;\n v6 = 4LL * a3;\n do {\n *(double *)(a4 + 2 * v5) =\n pow((double)*(int *)(a1 + v5), (double)*(int *)(a2 + v5));\n v5 += 4LL;\n } while (v6 != v5);\n }\n return a4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3, long long a4) {\n long long v5;\n long long v6;\n if (a3 > 0) {\n v5 = 0LL;\n v6 = 4LL * a3;\n do {\n *(double *)(a4 + 2 * v5) =\n pow((double)*(int *)(a1 + v5), (double)*(int *)(a2 + v5));\n v5 += 4LL;\n } while (v6 != v5);\n }\n return a4;\n}" + }, + { + "index": 539, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "double* func0(int bases_num[], int index[], int length, double result[]) {\n for (int i = 0; i < length; i++) {\n result[i] = pow(bases_num[i], index[i]);\n }\n return result;\n}", + "test": "int main() {\n\n int bases_num1[] = {10, 20, 30, 40, 50, 60, 70, 80, 90, 100};\n\n int index1[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n double expected1[] = {10, 400, 27000, 2560000, 312500000, 46656000000, 8235430000000, 1677721600000000, 387420489000000000, 100000000000000000000.0};\n\n double result1[10];\n\n func0(bases_num1, index1, 10, result1);\n\n for (int i = 0; i < 10; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n\n\n int bases_num2[] = {1, 2, 3, 4, 5, 6, 7};\n\n int index2[] = {10, 20, 30, 40, 50, 60, 70};\n\n double expected2[] = {1, 1048576, 205891132094649.0, 1208925819614629174706176.0, 88817841970012523233890533447265625.0, 48873677980689257489322752273774603865660850176.0, 143503601609868434285603076356671071740077383739246066639249.0};\n\n double result2[7];\n\n func0(bases_num2, index2, 7, result2);\n\n for (int i = 0; i < 7; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n\n\n int bases_num3[] = {4, 8, 12, 16, 20, 24, 28};\n\n int index3[] = {3, 6, 9, 12, 15, 18, 21};\n\n double expected3[] = {64, 262144, 5159780352.0, 281474976710656.0, 32768000000000000000.0, 6979147079584381377970176.0, 2456510688823056210273111113728.0};\n\n double result3[7];\n\n func0(bases_num3, index3, 7, result3);\n\n for (int i = 0; i < 7; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\nmov %rcx,%r12\npush %rbp\npush %rbx\ntest %edx,%edx\njle 174c \nmov %rdi,%rbp\nmov %rsi,%r13\nlea -0x1(%rdx),%r14d\nxor %ebx,%ebx\npxor %xmm0,%xmm0\npxor %xmm1,%xmm1\ncvtsi2sdl 0x0(%rbp,%rbx,4),%xmm0\ncvtsi2sdl 0x0(%r13,%rbx,4),%xmm1\ncallq 1070 \nmov %rbx,%rax\nmovsd %xmm0,(%r12,%rbx,8)\nadd $0x1,%rbx\ncmp %r14,%rax\njne 1720 \npop %rbx\nmov %r12,%rax\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\nmov r12, rcx\npush rbp\npush rbx\ntest edx, edx\njle short loc_1659\nmovsxd rdx, edx\nmov r13, rdi\nmov r14, rsi\nxor ebx, ebx\nlea rbp, ds:0[rdx*4]\nnop word ptr [rax+rax+00000000h]\nloc_1630:\npxor xmm0, xmm0\npxor xmm1, xmm1\ncvtsi2sd xmm0, dword ptr [r13+rbx+0]; x\ncvtsi2sd xmm1, dword ptr [r14+rbx]; y\ncall _pow\nmovsd qword ptr [r12+rbx*2], xmm0\nadd rbx, 4\ncmp rbp, rbx\njnz short loc_1630\nloc_1659:\npop rbx\nmov rax, r12\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3, __int64 a4)\n{\n __int64 v5; // rbx\n __int64 v6; // rbp\n\n if ( a3 > 0 )\n {\n v5 = 0LL;\n v6 = 4LL * a3;\n do\n {\n *(double *)(a4 + 2 * v5) = pow((double)*(int *)(a1 + v5), (double)*(int *)(a2 + v5));\n v5 += 4LL;\n }\n while ( v6 != v5 );\n }\n return a4;\n}", + "ida_strip_asm": "sub_1600:\nendbr64\npush r14\npush r13\npush r12\nmov r12, rcx\npush rbp\npush rbx\ntest edx, edx\njle short loc_1659\nmovsxd rdx, edx\nmov r13, rdi\nmov r14, rsi\nxor ebx, ebx\nlea rbp, ds:0[rdx*4]\nnop word ptr [rax+rax+00000000h]\nloc_1630:\npxor xmm0, xmm0\npxor xmm1, xmm1\ncvtsi2sd xmm0, dword ptr [r13+rbx+0]; x\ncvtsi2sd xmm1, dword ptr [r14+rbx]; y\ncall _pow\nmovsd qword ptr [r12+rbx*2], xmm0\nadd rbx, 4\ncmp rbp, rbx\njnz short loc_1630\nloc_1659:\npop rbx\nmov rax, r12\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1600(__int64 a1, __int64 a2, int a3, __int64 a4)\n{\n __int64 v5; // rbx\n __int64 v6; // rbp\n\n if ( a3 > 0 )\n {\n v5 = 0LL;\n v6 = 4LL * a3;\n do\n {\n *(double *)(a4 + 2 * v5) = pow((double)*(int *)(a1 + v5), (double)*(int *)(a2 + v5));\n v5 += 4LL;\n }\n while ( v6 != v5 );\n }\n return a4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1600(long long a1, long long a2, int a3, long long a4) {\n long long v5;\n long long v6;\n if (a3 > 0) {\n v5 = 0LL;\n v6 = 4LL * a3;\n do {\n *(double *)(a4 + 2 * v5) =\n pow((double)*(int *)(a1 + v5), (double)*(int *)(a2 + v5));\n v5 += 4LL;\n } while (v6 != v5);\n }\n return a4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3, long long a4) {\n long long v5;\n long long v6;\n if (a3 > 0) {\n v5 = 0LL;\n v6 = 4LL * a3;\n do {\n *(double *)(a4 + 2 * v5) =\n pow((double)*(int *)(a1 + v5), (double)*(int *)(a2 + v5));\n v5 += 4LL;\n } while (v6 != v5);\n }\n return a4;\n}" + }, + { + "index": 540, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nvoid sortArray(int *arr, int n) {\n\n for (int i = 0; i < n - 1; i++) {\n\n for (int j = 0; j < n - 1 - i; j++) {\n\n if (arr[j] > arr[j + 1]) {\n\n int temp = arr[j];\n\n arr[j] = arr[j + 1];\n\n arr[j + 1] = temp;\n\n }\n\n }\n\n }\n\n}\n\n\n\n", + "func": "int func0(int *arr, int n) {\n sortArray(arr, n);\n int count = 0, max_count = 0, min_count = n;\n for (int i = 0; i < n - 1; i++) {\n if (arr[i] == arr[i + 1]) {\n count++;\n continue;\n } else {\n max_count = (max_count > count) ? max_count : count;\n min_count = (min_count < count) ? min_count : count;\n count = 0;\n }\n }\n return max_count - min_count;\n}", + "test": "int main() {\n\n int arr1[10] = {1, 1, 2, 2, 7, 8, 4, 5, 1, 4};\n\n int arr2[9] = {1, 7, 9, 2, 3, 3, 1, 3, 3};\n\n int arr3[4] = {1, 2, 1, 2};\n\n\n\n assert(func0(arr1, 10) == 2);\n\n assert(func0(arr2, 9) == 3);\n\n assert(func0(arr3, 4) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov -0x1c(%rbp),%edx\nmov -0x18(%rbp),%rax\nmov %edx,%esi\nmov %rax,%rdi\ncallq 1169 \nmovl $0x0,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\nmov -0x1c(%rbp),%eax\nmov %eax,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 12f8 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 12d3 \naddl $0x1,-0x10(%rbp)\njmp 12f4 \nmov -0xc(%rbp),%eax\ncmp %eax,-0x10(%rbp)\ncmovge -0x10(%rbp),%eax\nmov %eax,-0xc(%rbp)\nmov -0x8(%rbp),%eax\ncmp %eax,-0x10(%rbp)\ncmovle -0x10(%rbp),%eax\nmov %eax,-0x8(%rbp)\nmovl $0x0,-0x10(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x1c(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x4(%rbp)\njl 1299 \nmov -0xc(%rbp),%eax\nsub -0x8(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov edx, [rbp+var_1C]\nmov rax, [rbp+var_18]\nmov esi, edx\nmov rdi, rax\ncall sortArray\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\nmov eax, [rbp+var_1C]\nmov [rbp+var_8], eax\nmov [rbp+var_4], 0\njmp short loc_12FA\nloc_1299:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_12D3\nadd [rbp+var_10], 1\njmp short loc_12F6\nloc_12D3:\nmov edx, [rbp+var_C]\nmov eax, [rbp+var_10]\ncmp edx, eax\ncmovge eax, edx\nmov [rbp+var_C], eax\nmov edx, [rbp+var_8]\nmov eax, [rbp+var_10]\ncmp edx, eax\ncmovle eax, edx\nmov [rbp+var_8], eax\nmov [rbp+var_10], 0\nloc_12F6:\nadd [rbp+var_4], 1\nloc_12FA:\nmov eax, [rbp+var_1C]\nsub eax, 1\ncmp [rbp+var_4], eax\njl short loc_1299\nmov eax, [rbp+var_C]\nsub eax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, unsigned int a2)\n{\n int v2; // eax\n int v3; // eax\n int v5; // [rsp+10h] [rbp-10h]\n int v6; // [rsp+14h] [rbp-Ch]\n signed int v7; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n sortArray(a1, a2);\n v5 = 0;\n v6 = 0;\n v7 = a2;\n for ( i = 0; i < (int)(a2 - 1); ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4 * (i + 1LL) + a1) )\n {\n ++v5;\n }\n else\n {\n v2 = v5;\n if ( v6 >= v5 )\n v2 = v6;\n v6 = v2;\n v3 = v5;\n if ( v7 <= v5 )\n v3 = v7;\n v7 = v3;\n v5 = 0;\n }\n }\n return (unsigned int)(v6 - v7);\n}", + "ida_strip_asm": "sub_1258:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov edx, [rbp+var_1C]\nmov rax, [rbp+var_18]\nmov esi, edx\nmov rdi, rax\ncall sub_1169\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\nmov eax, [rbp+var_1C]\nmov [rbp+var_8], eax\nmov [rbp+var_4], 0\njmp short loc_12FA\nloc_1299:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_12D3\nadd [rbp+var_10], 1\njmp short loc_12F6\nloc_12D3:\nmov edx, [rbp+var_C]\nmov eax, [rbp+var_10]\ncmp edx, eax\ncmovge eax, edx\nmov [rbp+var_C], eax\nmov edx, [rbp+var_8]\nmov eax, [rbp+var_10]\ncmp edx, eax\ncmovle eax, edx\nmov [rbp+var_8], eax\nmov [rbp+var_10], 0\nloc_12F6:\nadd [rbp+var_4], 1\nloc_12FA:\nmov eax, [rbp+var_1C]\nsub eax, 1\ncmp [rbp+var_4], eax\njl short loc_1299\nmov eax, [rbp+var_C]\nsub eax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1258(__int64 a1, unsigned int a2)\n{\n int v2; // eax\n int v3; // eax\n int v5; // [rsp+10h] [rbp-10h]\n int v6; // [rsp+14h] [rbp-Ch]\n signed int v7; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n sub_1169(a1, a2);\n v5 = 0;\n v6 = 0;\n v7 = a2;\n for ( i = 0; i < (int)(a2 - 1); ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4 * (i + 1LL) + a1) )\n {\n ++v5;\n }\n else\n {\n v2 = v5;\n if ( v6 >= v5 )\n v2 = v6;\n v6 = v2;\n v3 = v5;\n if ( v7 <= v5 )\n v3 = v7;\n v7 = v3;\n v5 = 0;\n }\n }\n return (unsigned int)(v6 - v7);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1258(long long a1, unsigned int a2) {\n int v2;\n int v3;\n int v5;\n int v6;\n signed int v7;\n int i;\n sub_1169(a1, a2);\n v5 = 0;\n v6 = 0;\n v7 = a2;\n for (i = 0; i < (int)(a2 - 1); ++i) {\n if (*(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4 * (i + 1LL) + a1)) {\n ++v5;\n } else {\n v2 = v5;\n if (v6 >= v5) v2 = v6;\n v6 = v2;\n v3 = v5;\n if (v7 <= v5) v3 = v7;\n v7 = v3;\n v5 = 0;\n }\n }\n return (unsigned int)(v6 - v7);\n}", + "ida_pseudo_norm": "long long func0(long long a1, unsigned int a2) {\n int v2;\n int v3;\n int v5;\n int v6;\n signed int v7;\n int i;\n sortArray(a1, a2);\n v5 = 0;\n v6 = 0;\n v7 = a2;\n for (i = 0; i < (int)(a2 - 1); ++i) {\n if (*(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4 * (i + 1LL) + a1)) {\n ++v5;\n } else {\n v2 = v5;\n if (v6 >= v5) v2 = v6;\n v6 = v2;\n v3 = v5;\n if (v7 <= v5) v3 = v7;\n v7 = v3;\n v5 = 0;\n }\n }\n return (unsigned int)(v6 - v7);\n}" + }, + { + "index": 540, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nvoid sortArray(int *arr, int n) {\n\n for (int i = 0; i < n - 1; i++) {\n\n for (int j = 0; j < n - 1 - i; j++) {\n\n if (arr[j] > arr[j + 1]) {\n\n int temp = arr[j];\n\n arr[j] = arr[j + 1];\n\n arr[j + 1] = temp;\n\n }\n\n }\n\n }\n\n}\n\n\n\n", + "func": "int func0(int *arr, int n) {\n sortArray(arr, n);\n int count = 0, max_count = 0, min_count = n;\n for (int i = 0; i < n - 1; i++) {\n if (arr[i] == arr[i + 1]) {\n count++;\n continue;\n } else {\n max_count = (max_count > count) ? max_count : count;\n min_count = (min_count < count) ? min_count : count;\n count = 0;\n }\n }\n return max_count - min_count;\n}", + "test": "int main() {\n\n int arr1[10] = {1, 1, 2, 2, 7, 8, 4, 5, 1, 4};\n\n int arr2[9] = {1, 7, 9, 2, 3, 3, 1, 3, 3};\n\n int arr3[4] = {1, 2, 1, 2};\n\n\n\n assert(func0(arr1, 10) == 2);\n\n assert(func0(arr2, 9) == 3);\n\n assert(func0(arr3, 4) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nmov %rdi,%rbp\nmov %esi,%ebx\ncallq 1169 \ncmp $0x1,%ebx\njle 11fe \nmov %rbp,%rdx\nlea -0x2(%rbx),%eax\nlea 0x4(%rbp,%rax,4),%rsi\nmov $0x0,%eax\nmov $0x0,%ecx\njmp 11e6 \nadd $0x1,%ecx\nadd $0x4,%rdx\ncmp %rsi,%rdx\nje 1203 \nmov 0x4(%rdx),%edi\ncmp %edi,(%rdx)\nje 11da \ncmp %ecx,%eax\ncmovl %ecx,%eax\ncmp %ecx,%ebx\ncmovg %ecx,%ebx\nmov $0x0,%ecx\njmp 11dd \nmov $0x0,%eax\nsub %ebx,%eax\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nmov rbp, rdi\nmov ebx, esi\ncall sortArray\ncmp ebx, 1\njle short loc_1205\nmov rdx, rbp\nlea eax, [rbx-2]\nlea rsi, [rbp+rax*4+4]\nmov eax, 0\nmov ecx, 0\njmp short loc_11ED\nloc_11E1:\nadd ecx, 1\nloc_11E4:\nadd rdx, 4\ncmp rdx, rsi\njz short loc_120A\nloc_11ED:\nmov edi, [rdx+4]\ncmp [rdx], edi\njz short loc_11E1\ncmp eax, ecx\ncmovl eax, ecx\ncmp ebx, ecx\ncmovg ebx, ecx\nmov ecx, 0\njmp short loc_11E4\nloc_1205:\nmov eax, 0\nloc_120A:\nsub eax, ebx\npop rbx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n int v2; // ebx\n _DWORD *v3; // rdx\n __int64 v4; // rsi\n int v5; // eax\n int v6; // ecx\n\n v2 = a2;\n sortArray();\n if ( a2 <= 1 )\n {\n v5 = 0;\n }\n else\n {\n v3 = a1;\n v4 = (__int64)&a1[a2 - 2 + 1];\n v5 = 0;\n v6 = 0;\n do\n {\n if ( *v3 == v3[1] )\n {\n ++v6;\n }\n else\n {\n if ( v5 < v6 )\n v5 = v6;\n if ( v2 > v6 )\n v2 = v6;\n v6 = 0;\n }\n ++v3;\n }\n while ( v3 != (_DWORD *)v4 );\n }\n return (unsigned int)(v5 - v2);\n}", + "ida_strip_asm": "sub_11B5:\nendbr64\npush rbp\npush rbx\nmov rbp, rdi\nmov ebx, esi\ncall sub_1169\ncmp ebx, 1\njle short loc_1205\nmov rdx, rbp\nlea eax, [rbx-2]\nlea rsi, [rbp+rax*4+4]\nmov eax, 0\nmov ecx, 0\njmp short loc_11ED\nloc_11E1:\nadd ecx, 1\nloc_11E4:\nadd rdx, 4\ncmp rdx, rsi\njz short loc_120A\nloc_11ED:\nmov edi, [rdx+4]\ncmp [rdx], edi\njz short loc_11E1\ncmp eax, ecx\ncmovl eax, ecx\ncmp ebx, ecx\ncmovg ebx, ecx\nmov ecx, 0\njmp short loc_11E4\nloc_1205:\nmov eax, 0\nloc_120A:\nsub eax, ebx\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11B5(_DWORD *a1, int a2)\n{\n int v2; // ebx\n _DWORD *v3; // rdx\n __int64 v4; // rsi\n int v5; // eax\n int v6; // ecx\n\n v2 = a2;\n sub_1169();\n if ( a2 <= 1 )\n {\n v5 = 0;\n }\n else\n {\n v3 = a1;\n v4 = (__int64)&a1[a2 - 2 + 1];\n v5 = 0;\n v6 = 0;\n do\n {\n if ( *v3 == v3[1] )\n {\n ++v6;\n }\n else\n {\n if ( v5 < v6 )\n v5 = v6;\n if ( v2 > v6 )\n v2 = v6;\n v6 = 0;\n }\n ++v3;\n }\n while ( v3 != (_DWORD *)v4 );\n }\n return (unsigned int)(v5 - v2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11B5(uint32_t *a1, int a2) {\n int v2;\n uint32_t *v3;\n long long v4;\n int v5;\n int v6;\n v2 = a2;\n sub_1169();\n if (a2 <= 1) {\n v5 = 0;\n } else {\n v3 = a1;\n v4 = (long long)&a1[a2 - 2 + 1];\n v5 = 0;\n v6 = 0;\n do {\n if (*v3 == v3[1]) {\n ++v6;\n } else {\n if (v5 < v6) v5 = v6;\n if (v2 > v6) v2 = v6;\n v6 = 0;\n }\n ++v3;\n } while (v3 != (uint32_t *)v4);\n }\n return (unsigned int)(v5 - v2);\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n int v2;\n uint32_t *v3;\n long long v4;\n int v5;\n int v6;\n v2 = a2;\n sortArray();\n if (a2 <= 1) {\n v5 = 0;\n } else {\n v3 = a1;\n v4 = (long long)&a1[a2 - 2 + 1];\n v5 = 0;\n v6 = 0;\n do {\n if (*v3 == v3[1]) {\n ++v6;\n } else {\n if (v5 < v6) v5 = v6;\n if (v2 > v6) v2 = v6;\n v6 = 0;\n }\n ++v3;\n } while (v3 != (uint32_t *)v4);\n }\n return (unsigned int)(v5 - v2);\n}" + }, + { + "index": 540, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nvoid sortArray(int *arr, int n) {\n\n for (int i = 0; i < n - 1; i++) {\n\n for (int j = 0; j < n - 1 - i; j++) {\n\n if (arr[j] > arr[j + 1]) {\n\n int temp = arr[j];\n\n arr[j] = arr[j + 1];\n\n arr[j + 1] = temp;\n\n }\n\n }\n\n }\n\n}\n\n\n\n", + "func": "int func0(int *arr, int n) {\n sortArray(arr, n);\n int count = 0, max_count = 0, min_count = n;\n for (int i = 0; i < n - 1; i++) {\n if (arr[i] == arr[i + 1]) {\n count++;\n continue;\n } else {\n max_count = (max_count > count) ? max_count : count;\n min_count = (min_count < count) ? min_count : count;\n count = 0;\n }\n }\n return max_count - min_count;\n}", + "test": "int main() {\n\n int arr1[10] = {1, 1, 2, 2, 7, 8, 4, 5, 1, 4};\n\n int arr2[9] = {1, 7, 9, 2, 3, 3, 1, 3, 3};\n\n int arr3[4] = {1, 2, 1, 2};\n\n\n\n assert(func0(arr1, 10) == 2);\n\n assert(func0(arr2, 9) == 3);\n\n assert(func0(arr3, 4) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov %esi,%r10d\ncallq 12e0 \ncmp $0x1,%r10d\njle 1380 \nlea -0x2(%r10),%eax\nxor %edx,%edx\nlea 0x4(%rdi,%rax,4),%rcx\nxor %eax,%eax\njmp 135f \nnopl 0x0(%rax)\ncmp %edx,%eax\ncmovl %edx,%eax\ncmp %edx,%r10d\ncmovg %edx,%r10d\nadd $0x4,%rdi\nxor %edx,%edx\ncmp %rcx,%rdi\nje 1372 \nmov 0x4(%rdi),%esi\ncmp %esi,(%rdi)\njne 1348 \nadd $0x4,%rdi\nadd $0x1,%edx\ncmp %rcx,%rdi\njne 135f \nsub %r10d,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxor %eax,%eax\nsub %r10d,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmov r9d, esi\nmov r10, rdi\ncall sortArray\ncmp r9d, 1\njle short loc_1360\nlea eax, [r9-2]\nmov esi, [r10]\nlea rcx, [r10+4]\nxor edx, edx\nlea r8, [r10+rax*4+8]\nxor eax, eax\njmp short loc_1347\nloc_1330:\ncmp eax, edx\ncmovl eax, edx\ncmp r9d, edx\ncmovg r9d, edx\nadd rcx, 4\nxor edx, edx\ncmp rcx, r8\njz short loc_135B\nloc_1347:\nmov edi, esi\nmov esi, [rcx]\ncmp edi, esi\njnz short loc_1330\nadd rcx, 4\nadd edx, 1\ncmp rcx, r8\njnz short loc_1347\nloc_135B:\nsub eax, r9d\nretn\nloc_1360:\nxor eax, eax\nsub eax, r9d\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, __int64 a3, __int64 a4, __int64 a5)\n{\n int v5; // r9d\n int *v6; // r10\n int v7; // esi\n int *v8; // rcx\n int v9; // edx\n __int64 v10; // r8\n int v11; // eax\n int v12; // edi\n\n sortArray(a1, a2, a3, a4, a5, (unsigned int)a2);\n if ( v5 <= 1 )\n return (unsigned int)-v5;\n v7 = *v6;\n v8 = v6 + 1;\n v9 = 0;\n v10 = (__int64)&v6[v5 - 2 + 2];\n v11 = 0;\n do\n {\n while ( 1 )\n {\n v12 = v7;\n v7 = *v8;\n if ( v12 != *v8 )\n break;\n ++v8;\n ++v9;\n if ( v8 == (int *)v10 )\n return (unsigned int)(v11 - v5);\n }\n if ( v11 < v9 )\n v11 = v9;\n if ( v5 > v9 )\n v5 = v9;\n ++v8;\n v9 = 0;\n }\n while ( v8 != (int *)v10 );\n return (unsigned int)(v11 - v5);\n}", + "ida_strip_asm": "sub_1300:\nendbr64\nmov r9d, esi\nmov r10, rdi\ncall sub_1290\ncmp r9d, 1\njle short loc_1360\nlea eax, [r9-2]\nmov esi, [r10]\nlea rcx, [r10+4]\nxor edx, edx\nlea r8, [r10+rax*4+8]\nxor eax, eax\njmp short loc_1347\nloc_1330:\ncmp eax, edx\ncmovl eax, edx\ncmp r9d, edx\ncmovg r9d, edx\nadd rcx, 4\nxor edx, edx\ncmp rcx, r8\njz short loc_135B\nloc_1347:\nmov edi, esi\nmov esi, [rcx]\ncmp edi, esi\njnz short loc_1330\nadd rcx, 4\nadd edx, 1\ncmp rcx, r8\njnz short loc_1347\nloc_135B:\nsub eax, r9d\nretn\nloc_1360:\nxor eax, eax\nsub eax, r9d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1300(__int64 a1, __int64 a2, __int64 a3, __int64 a4, __int64 a5)\n{\n int v5; // r9d\n int *v6; // r10\n int v7; // esi\n int *v8; // rcx\n int v9; // edx\n __int64 v10; // r8\n int v11; // eax\n int v12; // edi\n\n sub_1290(a1, a2, a3, a4, a5, (unsigned int)a2);\n if ( v5 <= 1 )\n return (unsigned int)-v5;\n v7 = *v6;\n v8 = v6 + 1;\n v9 = 0;\n v10 = (__int64)&v6[v5 - 2 + 2];\n v11 = 0;\n do\n {\n while ( 1 )\n {\n v12 = v7;\n v7 = *v8;\n if ( v12 != *v8 )\n break;\n ++v8;\n ++v9;\n if ( v8 == (int *)v10 )\n return (unsigned int)(v11 - v5);\n }\n if ( v11 < v9 )\n v11 = v9;\n if ( v5 > v9 )\n v5 = v9;\n ++v8;\n v9 = 0;\n }\n while ( v8 != (int *)v10 );\n return (unsigned int)(v11 - v5);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1300(long long a1, long long a2, long long a3, long long a4,\n long long a5) {\n int v5;\n int *v6;\n int v7;\n int *v8;\n int v9;\n long long v10;\n int v11;\n int v12;\n sub_1290(a1, a2, a3, a4, a5, (unsigned int)a2);\n if (v5 <= 1) return (unsigned int)-v5;\n v7 = *v6;\n v8 = v6 + 1;\n v9 = 0;\n v10 = (long long)&v6[v5 - 2 + 2];\n v11 = 0;\n do {\n while (1) {\n v12 = v7;\n v7 = *v8;\n if (v12 != *v8) break;\n ++v8;\n ++v9;\n if (v8 == (int *)v10) return (unsigned int)(v11 - v5);\n }\n if (v11 < v9) v11 = v9;\n if (v5 > v9) v5 = v9;\n ++v8;\n v9 = 0;\n } while (v8 != (int *)v10);\n return (unsigned int)(v11 - v5);\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, long long a3, long long a4,\n long long a5) {\n int v5;\n int *v6;\n int v7;\n int *v8;\n int v9;\n long long v10;\n int v11;\n int v12;\n sortArray(a1, a2, a3, a4, a5, (unsigned int)a2);\n if (v5 <= 1) return (unsigned int)-v5;\n v7 = *v6;\n v8 = v6 + 1;\n v9 = 0;\n v10 = (long long)&v6[v5 - 2 + 2];\n v11 = 0;\n do {\n while (1) {\n v12 = v7;\n v7 = *v8;\n if (v12 != *v8) break;\n ++v8;\n ++v9;\n if (v8 == (int *)v10) return (unsigned int)(v11 - v5);\n }\n if (v11 < v9) v11 = v9;\n if (v5 > v9) v5 = v9;\n ++v8;\n v9 = 0;\n } while (v8 != (int *)v10);\n return (unsigned int)(v11 - v5);\n}" + }, + { + "index": 540, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nvoid sortArray(int *arr, int n) {\n\n for (int i = 0; i < n - 1; i++) {\n\n for (int j = 0; j < n - 1 - i; j++) {\n\n if (arr[j] > arr[j + 1]) {\n\n int temp = arr[j];\n\n arr[j] = arr[j + 1];\n\n arr[j + 1] = temp;\n\n }\n\n }\n\n }\n\n}\n\n\n\n", + "func": "int func0(int *arr, int n) {\n sortArray(arr, n);\n int count = 0, max_count = 0, min_count = n;\n for (int i = 0; i < n - 1; i++) {\n if (arr[i] == arr[i + 1]) {\n count++;\n continue;\n } else {\n max_count = (max_count > count) ? max_count : count;\n min_count = (min_count < count) ? min_count : count;\n count = 0;\n }\n }\n return max_count - min_count;\n}", + "test": "int main() {\n\n int arr1[10] = {1, 1, 2, 2, 7, 8, 4, 5, 1, 4};\n\n int arr2[9] = {1, 7, 9, 2, 3, 3, 1, 3, 3};\n\n int arr3[4] = {1, 2, 1, 2};\n\n\n\n assert(func0(arr1, 10) == 2);\n\n assert(func0(arr2, 9) == 3);\n\n assert(func0(arr3, 4) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nlea -0x1(%rsi),%edx\ntest %edx,%edx\njle 1380 \nlea 0x4(%rdi),%rcx\nnopl 0x0(%rax,%rax,1)\nlea -0x1(%rdx),%r8d\nmov %rdi,%rax\nmov %r8,%rdx\nlea (%rcx,%r8,4),%r10\nnopw %cs:0x0(%rax,%rax,1)\nmov (%rax),%r8d\nmov 0x4(%rax),%r9d\ncmp %r9d,%r8d\njle 1323 \nmov %r9d,(%rax)\nmov %r8d,0x4(%rax)\nadd $0x4,%rax\ncmp %rax,%r10\njne 1310 \ntest %edx,%edx\njne 12f8 \nlea -0x2(%rsi),%eax\nmov %rcx,%rdx\nmov (%rdi),%r8d\nxor %ecx,%ecx\nlea 0x8(%rdi,%rax,4),%r9\nxor %eax,%eax\njmp 135d \nnopl 0x0(%rax)\ncmp %ecx,%eax\ncmovl %ecx,%eax\ncmp %ecx,%esi\ncmovg %ecx,%esi\nadd $0x4,%rdx\nxor %ecx,%ecx\ncmp %rdx,%r9\nje 1374 \nmov %r8d,%edi\nmov (%rdx),%r8d\ncmp %edi,%r8d\njne 1348 \nadd $0x4,%rdx\nadd $0x1,%ecx\ncmp %rdx,%r9\njne 135d \nsub %esi,%eax\nretq\nnopw 0x0(%rax,%rax,1)\nxor %eax,%eax\nsub %esi,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nlea eax, [rsi-1]\nmov r8, rdi\nmov edi, esi\ntest eax, eax\njle loc_13AE\ncdqe\nlea r10d, [rdi-2]\nshl rax, 2\nshl r10, 2\nlea r9, [r8+rax-4]\nlea rsi, [rax+r8]\nsub r9, r10\nxchg ax, ax\nloc_1330:\nmov rax, r8\nnop dword ptr [rax+rax+00h]\nloc_1338:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd ecx, xmm0\nmovd edx, xmm1\ncmp ecx, edx\njle short loc_1356\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_1356:\nadd rax, 4\ncmp rax, rsi\njnz short loc_1338\nlea rsi, [rax-4]\ncmp rsi, r9\njnz short loc_1330\nmov esi, [r8]\nlea rcx, [r8+4]\nlea r9, [r8+r10+8]\nxor eax, eax\nxor edx, edx\njmp short loc_1395\nloc_1380:\ncmp eax, edx\ncmovl eax, edx\ncmp edi, edx\ncmovg edi, edx\nadd rcx, 4\nxor edx, edx\ncmp rcx, r9\njz short loc_13AB\nloc_1395:\nmov r8d, esi\nmov esi, [rcx]\ncmp esi, r8d\njnz short loc_1380\nadd rcx, 4\nadd edx, 1\ncmp rcx, r9\njnz short loc_1395\nloc_13AB:\nsub eax, edi\nretn\nloc_13AE:\nxor eax, eax\nsub eax, edi\nretn", + "ida_pseudo": "__int64 __fastcall func0(__m128i *a1, int a2)\n{\n int v3; // edi\n __int64 v4; // r10\n __m128i *v5; // rsi\n __m128i *v6; // r9\n __m128i *v7; // rax\n __m128i v8; // xmm0\n __int32 v9; // esi\n __int32 *v10; // rcx\n __int64 v11; // r9\n int v12; // eax\n int v13; // edx\n __int32 v14; // r8d\n\n v3 = a2;\n if ( a2 - 1 <= 0 )\n return (unsigned int)-a2;\n v4 = 4LL * (unsigned int)(a2 - 2);\n v5 = (__m128i *)((char *)a1 + 4 * a2 - 4);\n v6 = (__m128i *)((char *)v5->m128i_u64 - v4 - 4);\n do\n {\n v7 = a1;\n do\n {\n v8 = _mm_loadl_epi64(v7);\n if ( _mm_cvtsi128_si32(v8) > _mm_cvtsi128_si32(_mm_shuffle_epi32(v8, 229)) )\n v7->m128i_i64[0] = _mm_shuffle_epi32(v8, 225).m128i_u64[0];\n v7 = (__m128i *)((char *)v7 + 4);\n }\n while ( v7 != v5 );\n v5 = (__m128i *)((char *)v7 - 4);\n }\n while ( (__m128i *)((char *)&v7[-1].m128i_u64[1] + 4) != v6 );\n v9 = a1->m128i_i32[0];\n v10 = &a1->m128i_i32[1];\n v11 = (__int64)&a1->m128i_i64[1] + v4;\n v12 = 0;\n v13 = 0;\n do\n {\n while ( 1 )\n {\n v14 = v9;\n v9 = *v10;\n if ( *v10 != v14 )\n break;\n ++v10;\n ++v13;\n if ( v10 == (__int32 *)v11 )\n return (unsigned int)(v12 - v3);\n }\n if ( v12 < v13 )\n v12 = v13;\n if ( v3 > v13 )\n v3 = v13;\n ++v10;\n v13 = 0;\n }\n while ( v10 != (__int32 *)v11 );\n return (unsigned int)(v12 - v3);\n}", + "ida_strip_asm": "sub_1300:\nendbr64\nlea eax, [rsi-1]\nmov r8, rdi\nmov edi, esi\ntest eax, eax\njle loc_13AE\ncdqe\nlea r10d, [rdi-2]\nshl rax, 2\nshl r10, 2\nlea r9, [r8+rax-4]\nlea rsi, [rax+r8]\nsub r9, r10\nxchg ax, ax\nloc_1330:\nmov rax, r8\nnop dword ptr [rax+rax+00h]\nloc_1338:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd ecx, xmm0\nmovd edx, xmm1\ncmp ecx, edx\njle short loc_1356\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_1356:\nadd rax, 4\ncmp rax, rsi\njnz short loc_1338\nlea rsi, [rax-4]\ncmp rsi, r9\njnz short loc_1330\nmov esi, [r8]\nlea rcx, [r8+4]\nlea r9, [r8+r10+8]\nxor eax, eax\nxor edx, edx\njmp short loc_1395\nloc_1380:\ncmp eax, edx\ncmovl eax, edx\ncmp edi, edx\ncmovg edi, edx\nadd rcx, 4\nxor edx, edx\ncmp rcx, r9\njz short loc_13AB\nloc_1395:\nmov r8d, esi\nmov esi, [rcx]\ncmp esi, r8d\njnz short loc_1380\nadd rcx, 4\nadd edx, 1\ncmp rcx, r9\njnz short loc_1395\nloc_13AB:\nsub eax, edi\nretn\nloc_13AE:\nxor eax, eax\nsub eax, edi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1300(__m128i *a1, int a2)\n{\n int v3; // edi\n __int64 v4; // r10\n __m128i *v5; // rsi\n __m128i *v6; // r9\n __m128i *v7; // rax\n __m128i v8; // xmm0\n __int32 v9; // esi\n __int32 *v10; // rcx\n __int64 v11; // r9\n int v12; // eax\n int v13; // edx\n __int32 v14; // r8d\n\n v3 = a2;\n if ( a2 - 1 <= 0 )\n return (unsigned int)-a2;\n v4 = 4LL * (unsigned int)(a2 - 2);\n v5 = (__m128i *)((char *)a1 + 4 * a2 - 4);\n v6 = (__m128i *)((char *)v5->m128i_u64 - v4 - 4);\n do\n {\n v7 = a1;\n do\n {\n v8 = _mm_loadl_epi64(v7);\n if ( _mm_cvtsi128_si32(v8) > _mm_cvtsi128_si32(_mm_shuffle_epi32(v8, 229)) )\n v7->m128i_i64[0] = _mm_shuffle_epi32(v8, 225).m128i_u64[0];\n v7 = (__m128i *)((char *)v7 + 4);\n }\n while ( v7 != v5 );\n v5 = (__m128i *)((char *)v7 - 4);\n }\n while ( (__m128i *)((char *)&v7[-1].m128i_u64[1] + 4) != v6 );\n v9 = a1->m128i_i32[0];\n v10 = &a1->m128i_i32[1];\n v11 = (__int64)&a1->m128i_i64[1] + v4;\n v12 = 0;\n v13 = 0;\n do\n {\n while ( 1 )\n {\n v14 = v9;\n v9 = *v10;\n if ( *v10 != v14 )\n break;\n ++v10;\n ++v13;\n if ( v10 == (__int32 *)v11 )\n return (unsigned int)(v12 - v3);\n }\n if ( v12 < v13 )\n v12 = v13;\n if ( v3 > v13 )\n v3 = v13;\n ++v10;\n v13 = 0;\n }\n while ( v10 != (__int32 *)v11 );\n return (unsigned int)(v12 - v3);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1300(__m128i *a1, int a2) {\n int v3;\n long long v4;\n __m128i *v5;\n __m128i *v6;\n __m128i *v7;\n __m128i v8;\n int v9;\n int *v10;\n long long v11;\n int v12;\n int v13;\n int v14;\n v3 = a2;\n if (a2 - 1 <= 0) return (unsigned int)-a2;\n v4 = 4LL * (unsigned int)(a2 - 2);\n v5 = (__m128i *)((char *)a1 + 4 * a2 - 4);\n v6 = (__m128i *)((char *)v5->m128i_u64 - v4 - 4);\n do {\n v7 = a1;\n do {\n v8 = _mm_loadl_epi64(v7);\n if (_mm_cvtsi128_si32(v8) > _mm_cvtsi128_si32(_mm_shuffle_epi32(v8, 229)))\n v7->m128i_i64[0] = _mm_shuffle_epi32(v8, 225).m128i_u64[0];\n v7 = (__m128i *)((char *)v7 + 4);\n } while (v7 != v5);\n v5 = (__m128i *)((char *)v7 - 4);\n } while ((__m128i *)((char *)&v7[-1].m128i_u64[1] + 4) != v6);\n v9 = a1->m128i_i32[0];\n v10 = &a1->m128i_i32[1];\n v11 = (long long)&a1->m128i_i64[1] + v4;\n v12 = 0;\n v13 = 0;\n do {\n while (1) {\n v14 = v9;\n v9 = *v10;\n if (*v10 != v14) break;\n ++v10;\n ++v13;\n if (v10 == (int *)v11) return (unsigned int)(v12 - v3);\n }\n if (v12 < v13) v12 = v13;\n if (v3 > v13) v3 = v13;\n ++v10;\n v13 = 0;\n } while (v10 != (int *)v11);\n return (unsigned int)(v12 - v3);\n}", + "ida_pseudo_norm": "long long func0(__m128i *a1, int a2) {\n int v3;\n long long v4;\n __m128i *v5;\n __m128i *v6;\n __m128i *v7;\n __m128i v8;\n int v9;\n int *v10;\n long long v11;\n int v12;\n int v13;\n int v14;\n v3 = a2;\n if (a2 - 1 <= 0) return (unsigned int)-a2;\n v4 = 4LL * (unsigned int)(a2 - 2);\n v5 = (__m128i *)((char *)a1 + 4 * a2 - 4);\n v6 = (__m128i *)((char *)v5->m128i_u64 - v4 - 4);\n do {\n v7 = a1;\n do {\n v8 = _mm_loadl_epi64(v7);\n if (_mm_cvtsi128_si32(v8) > _mm_cvtsi128_si32(_mm_shuffle_epi32(v8, 229)))\n v7->m128i_i64[0] = _mm_shuffle_epi32(v8, 225).m128i_u64[0];\n v7 = (__m128i *)((char *)v7 + 4);\n } while (v7 != v5);\n v5 = (__m128i *)((char *)v7 - 4);\n } while ((__m128i *)((char *)&v7[-1].m128i_u64[1] + 4) != v6);\n v9 = a1->m128i_i32[0];\n v10 = &a1->m128i_i32[1];\n v11 = (long long)&a1->m128i_i64[1] + v4;\n v12 = 0;\n v13 = 0;\n do {\n while (1) {\n v14 = v9;\n v9 = *v10;\n if (*v10 != v14) break;\n ++v10;\n ++v13;\n if (v10 == (int *)v11) return (unsigned int)(v12 - v3);\n }\n if (v12 < v13) v12 = v13;\n if (v3 > v13) v3 = v13;\n ++v10;\n v13 = 0;\n } while (v10 != (int *)v11);\n return (unsigned int)(v12 - v3);\n}" + }, + { + "index": 541, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\ndouble get_sum(int n) {\n\n double sum = 0;\n\n int i = 1;\n\n while (i <= (int)(sqrt(n))) {\n\n if (n % i == 0) {\n\n if (n / i == i) {\n\n sum = sum + i;\n\n } else {\n\n sum = sum + i;\n\n sum = sum + (n / i);\n\n }\n\n }\n\n i = i + 1;\n\n }\n\n sum = sum - n;\n\n return sum;\n\n}\n\n\n\n", + "func": "int func0(int n) {\n if (get_sum(n) > n) {\n return 1;\n } else {\n return 0;\n }\n}", + "test": "int main() {\n\n assert(func0(12) == 1);\n\n assert(func0(15) == 0);\n\n assert(func0(18) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %edi,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nmov %eax,%edi\ncallq 1169 \ncvtsi2sdl -0x4(%rbp),%xmm1\ncomisd %xmm1,%xmm0\njbe 1240 \nmov $0x1,%eax\njmp 1245 \nmov $0x0,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+var_4], edi\nmov eax, [rbp+var_4]\nmov edi, eax\ncall get_sum\nmovq rax, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_4]\nmovq xmm1, rax\ncomisd xmm1, xmm0\njbe short loc_1270\nmov eax, 1\njmp short locret_1275\nloc_1270:\nmov eax, 0\nlocret_1275:\nleave\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(int a1)\n{\n return get_sum((unsigned int)a1) > (double)a1;\n}", + "ida_strip_asm": "sub_1237:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+var_4], edi\nmov eax, [rbp+var_4]\nmov edi, eax\ncall sub_1169\nmovq rax, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_4]\nmovq xmm1, rax\ncomisd xmm1, xmm0\njbe short loc_1270\nmov eax, 1\njmp short locret_1275\nloc_1270:\nmov eax, 0\nlocret_1275:\nleave\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1237(int a1)\n{\n return sub_1169((unsigned int)a1) > (double)a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1237(int a1) { return sub_1169((unsigned int)a1) > (double)a1; }", + "ida_pseudo_norm": "uint8_t func0(int a1) { return get_sum((unsigned int)a1) > (double)a1; }" + }, + { + "index": 541, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\ndouble get_sum(int n) {\n\n double sum = 0;\n\n int i = 1;\n\n while (i <= (int)(sqrt(n))) {\n\n if (n % i == 0) {\n\n if (n / i == i) {\n\n sum = sum + i;\n\n } else {\n\n sum = sum + i;\n\n sum = sum + (n / i);\n\n }\n\n }\n\n i = i + 1;\n\n }\n\n sum = sum - n;\n\n return sum;\n\n}\n\n\n\n", + "func": "int func0(int n) {\n if (get_sum(n) > n) {\n return 1;\n } else {\n return 0;\n }\n}", + "test": "int main() {\n\n assert(func0(12) == 1);\n\n assert(func0(15) == 0);\n\n assert(func0(18) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %edi,%ebx\ncallq 1169 \nmovapd %xmm0,%xmm1\npxor %xmm0,%xmm0\ncvtsi2sd %ebx,%xmm0\ncomisd %xmm0,%xmm1\nseta %al\nmovzbl %al,%eax\npop %rbx\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov ebx, edi\ncall get_sum\nmovapd xmm1, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, ebx\ncomisd xmm1, xmm0\nsetnbe al\nmovzx eax, al\npop rbx\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(int a1)\n{\n return get_sum() > (double)a1;\n}", + "ida_strip_asm": "sub_121A:\nendbr64\npush rbx\nmov ebx, edi\ncall sub_1169\nmovapd xmm1, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, ebx\ncomisd xmm1, xmm0\nsetnbe al\nmovzx eax, al\npop rbx\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_121A(int a1)\n{\n return sub_1169() > (double)a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_121A(int a1) { return sub_1169() > (double)a1; }", + "ida_pseudo_norm": "uint8_t func0(int a1) { return get_sum() > (double)a1; }" + }, + { + "index": 542, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n static char result[100];\n strcpy(result, text);\n for (int i = 0; result[i] != '\\0'; i++) {\n if (result[i] == ' ' || result[i] == ',' || result[i] == '.')\n result[i] = ':';\n }\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"Boult Curve Wireless Neckband\"), \"Boult:Curve:Wireless:Neckband\") == 0);\n\n assert(strcmp(func0(\"Stereo Sound Sweatproof\"), \"Stereo:Sound:Sweatproof\") == 0);\n\n assert(strcmp(func0(\"Probass Curve Audio\"), \"Probass:Curve:Audio\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov -0x18(%rbp),%rax\nmov %rax,%rsi\nlea 0x2e99(%rip),%rdi\ncallq 1070 \nmovl $0x0,-0x4(%rbp)\njmp 1205 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x2e7f(%rip),%rdx\nmovzbl (%rax,%rdx,1),%eax\ncmp $0x20,%al\nje 11f1 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x2e6b(%rip),%rdx\nmovzbl (%rax,%rdx,1),%eax\ncmp $0x2c,%al\nje 11f1 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x2e57(%rip),%rdx\nmovzbl (%rax,%rdx,1),%eax\ncmp $0x2e,%al\njne 1201 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x2e43(%rip),%rdx\nmovb $0x3a,(%rax,%rdx,1)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncltq\nlea 0x2e2f(%rip),%rdx\nmovzbl (%rax,%rdx,1),%eax\ntest %al,%al\njne 11b5 \nlea 0x2e20(%rip),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+src], rdi\nmov rax, [rbp+src]\nmov rsi, rax; src\nlea rax, result_1\nmov rdi, rax; dest\ncall _strcpy\nmov [rbp+var_4], 0\njmp short loc_1208\nloc_11B8:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, result_1\nmovzx eax, byte ptr [rax+rdx]\ncmp al, 20h ; ' '\njz short loc_11F4\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, result_1\nmovzx eax, byte ptr [rax+rdx]\ncmp al, 2Ch ; ','\njz short loc_11F4\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, result_1\nmovzx eax, byte ptr [rax+rdx]\ncmp al, 2Eh ; '.'\njnz short loc_1204\nloc_11F4:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, result_1\nmov byte ptr [rax+rdx], 3Ah ; ':'\nloc_1204:\nadd [rbp+var_4], 1\nloc_1208:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, result_1\nmovzx eax, byte ptr [rax+rdx]\ntest al, al\njnz short loc_11B8\nlea rax, result_1\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(const char *a1)\n{\n int i; // [rsp+1Ch] [rbp-4h]\n\n strcpy(result_1, a1);\n for ( i = 0; result_1[i]; ++i )\n {\n if ( result_1[i] == 32 || result_1[i] == 44 || result_1[i] == 46 )\n result_1[i] = 58;\n }\n return result_1;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+src], rdi\nmov rax, [rbp+src]\nmov rsi, rax; src\nlea rax, dest\nmov rdi, rax; dest\ncall _strcpy\nmov [rbp+var_4], 0\njmp short loc_1208\nloc_11B8:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, dest\nmovzx eax, byte ptr [rax+rdx]\ncmp al, 20h ; ' '\njz short loc_11F4\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, dest\nmovzx eax, byte ptr [rax+rdx]\ncmp al, 2Ch ; ','\njz short loc_11F4\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, dest\nmovzx eax, byte ptr [rax+rdx]\ncmp al, 2Eh ; '.'\njnz short loc_1204\nloc_11F4:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, dest\nmov byte ptr [rax+rdx], 3Ah ; ':'\nloc_1204:\nadd [rbp+var_4], 1\nloc_1208:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, dest\nmovzx eax, byte ptr [rax+rdx]\ntest al, al\njnz short loc_11B8\nlea rax, dest\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1189(const char *a1)\n{\n int i; // [rsp+1Ch] [rbp-4h]\n\n strcpy(dest, a1);\n for ( i = 0; dest[i]; ++i )\n {\n if ( dest[i] == 32 || dest[i] == 44 || dest[i] == 46 )\n dest[i] = 58;\n }\n return dest;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1189(const char *a1) {\n int i;\n strcpy(dest, a1);\n for (i = 0; dest[i]; ++i) {\n if (dest[i] == 32 || dest[i] == 44 || dest[i] == 46) dest[i] = 58;\n }\n return dest;\n}", + "ida_pseudo_norm": "char *func0(const char *a1) {\n int i;\n strcpy(result_1, a1);\n for (i = 0; result_1[i]; ++i) {\n if (result_1[i] == 32 || result_1[i] == 44 || result_1[i] == 46)\n result_1[i] = 58;\n }\n return result_1;\n}" + }, + { + "index": 542, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n static char result[100];\n strcpy(result, text);\n for (int i = 0; result[i] != '\\0'; i++) {\n if (result[i] == ' ' || result[i] == ',' || result[i] == '.')\n result[i] = ':';\n }\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"Boult Curve Wireless Neckband\"), \"Boult:Curve:Wireless:Neckband\") == 0);\n\n assert(strcmp(func0(\"Stereo Sound Sweatproof\"), \"Stereo:Sound:Sweatproof\") == 0);\n\n assert(strcmp(func0(\"Probass Curve Audio\"), \"Probass:Curve:Audio\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x8,%rsp\nmov %rdi,%rsi\nmov $0x64,%edx\nlea 0x2ec0(%rip),%rdi\ncallq 1070 <__strcpy_chk@plt>\nmovzbl 0x2eb4(%rip),%eax\ntest %al,%al\nje 11b7 \nlea 0x2ea9(%rip),%rdx\njmp 11a7 \nmovb $0x3a,(%rdx)\nadd $0x1,%rdx\nmovzbl (%rdx),%eax\ntest %al,%al\nje 11b7 \nmov %eax,%ecx\nand $0xfffffffd,%ecx\ncmp $0x2c,%cl\nje 1199 \ncmp $0x20,%al\nje 1199 \njmp 119c \nlea 0x2e82(%rip),%rax\nadd $0x8,%rsp\nretq\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\nmov rsi, rdi\nmov edx, 64h ; 'd'\nlea rdi, result_1\ncall ___strcpy_chk\nmovzx eax, cs:result_1\ntest al, al\njz short loc_11DD\nlea rdx, result_1\nmov rcx, 500100000000h\njmp short loc_11D1\nloc_11C3:\nmov byte ptr [rdx], 3Ah ; ':'\nloc_11C6:\nadd rdx, 1\nmovzx eax, byte ptr [rdx]\ntest al, al\njz short loc_11DD\nloc_11D1:\ncmp al, 2Eh ; '.'\nja short loc_11C6\nbt rcx, rax\njb short loc_11C3\njmp short loc_11C6\nloc_11DD:\nlea rax, result_1\nadd rsp, 8\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1)\n{\n unsigned __int64 v1; // rax\n char *v2; // rdx\n __int64 v3; // rcx\n\n __strcpy_chk(&result_1, a1, 100LL);\n v1 = (unsigned __int8)result_1;\n if ( result_1 )\n {\n v2 = &result_1;\n v3 = 0x500100000000LL;\n do\n {\n if ( (unsigned __int8)v1 <= 0x2Eu && _bittest64(&v3, v1) )\n *v2 = 58;\n v1 = (unsigned __int8)*++v2;\n }\n while ( (_BYTE)v1 );\n }\n return &result_1;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\nsub rsp, 8\nmov rsi, rdi\nmov edx, 64h ; 'd'\nlea rdi, byte_4040\ncall ___strcpy_chk\nmovzx eax, cs:byte_4040\ntest al, al\njz short loc_11DD\nlea rdx, byte_4040\nmov rcx, 500100000000h\njmp short loc_11D1\nloc_11C3:\nmov byte ptr [rdx], 3Ah ; ':'\nloc_11C6:\nadd rdx, 1\nmovzx eax, byte ptr [rdx]\ntest al, al\njz short loc_11DD\nloc_11D1:\ncmp al, 2Eh ; '.'\nja short loc_11C6\nbt rcx, rax\njb short loc_11C3\njmp short loc_11C6\nloc_11DD:\nlea rax, byte_4040\nadd rsp, 8\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1189(__int64 a1)\n{\n unsigned __int64 v1; // rax\n char *v2; // rdx\n __int64 v3; // rcx\n\n __strcpy_chk(&byte_4040, a1, 100LL);\n v1 = (unsigned __int8)byte_4040;\n if ( byte_4040 )\n {\n v2 = &byte_4040;\n v3 = 0x500100000000LL;\n do\n {\n if ( (unsigned __int8)v1 <= 0x2Eu && _bittest64(&v3, v1) )\n *v2 = 58;\n v1 = (unsigned __int8)*++v2;\n }\n while ( (_BYTE)v1 );\n }\n return &byte_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1189(long long a1) {\n unsigned long long v1;\n char *v2;\n long long v3;\n __strcpy_chk(&byte_4040, a1, 100LL);\n v1 = (unsigned char)byte_4040;\n if (byte_4040) {\n v2 = &byte_4040;\n v3 = 87965225189376LL;\n do {\n if ((unsigned char)v1 <= 46u && _bittest64(&v3, v1)) *v2 = 58;\n v1 = (unsigned char)*++v2;\n } while ((uint8_t)v1);\n }\n return &byte_4040;\n}", + "ida_pseudo_norm": "char *func0(long long a1) {\n unsigned long long v1;\n char *v2;\n long long v3;\n __strcpy_chk(&result_1, a1, 100LL);\n v1 = (unsigned char)result_1;\n if (result_1) {\n v2 = &result_1;\n v3 = 87965225189376LL;\n do {\n if ((unsigned char)v1 <= 46u && _bittest64(&v3, v1)) *v2 = 58;\n v1 = (unsigned char)*++v2;\n } while ((uint8_t)v1);\n }\n return &result_1;\n}" + }, + { + "index": 542, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n static char result[100];\n strcpy(result, text);\n for (int i = 0; result[i] != '\\0'; i++) {\n if (result[i] == ' ' || result[i] == ',' || result[i] == '.')\n result[i] = ':';\n }\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"Boult Curve Wireless Neckband\"), \"Boult:Curve:Wireless:Neckband\") == 0);\n\n assert(strcmp(func0(\"Stereo Sound Sweatproof\"), \"Stereo:Sound:Sweatproof\") == 0);\n\n assert(strcmp(func0(\"Probass Curve Audio\"), \"Probass:Curve:Audio\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%rsi\nsub $0x8,%rsp\nmov $0x64,%edx\nlea 0x2dd9(%rip),%rdi\ncallq 1070 <__strcpy_chk@plt>\nmovzbl 0x2dcd(%rip),%eax\ntest %al,%al\nje 129d \nlea 0x2dc2(%rip),%rdx\nxchg %ax,%ax\nmov %eax,%ecx\nand $0xfffffffd,%ecx\ncmp $0x2c,%cl\nje 128e \ncmp $0x20,%al\njne 1291 \nmovb $0x3a,(%rdx)\nmovzbl 0x1(%rdx),%eax\nadd $0x1,%rdx\ntest %al,%al\njne 1280 \nlea 0x2d9c(%rip),%rax\nadd $0x8,%rsp\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\nmov rsi, rdi\nsub rsp, 8\nmov edx, 64h ; 'd'\nlea rdi, result_1\ncall ___strcpy_chk\nmov rdi, rax\nmovzx eax, cs:result_1\ntest al, al\njz short loc_12B9\nmov rcx, 500100000000h\nmov rdx, rdi\nnop word ptr [rax+rax+00000000h]\nloc_12A0:\ncmp al, 2Eh ; '.'\nja short loc_12AD\nbt rcx, rax\njnb short loc_12AD\nmov byte ptr [rdx], 3Ah ; ':'\nloc_12AD:\nmovzx eax, byte ptr [rdx+1]\nadd rdx, 1\ntest al, al\njnz short loc_12A0\nloc_12B9:\nmov rax, rdi\nadd rsp, 8\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1)\n{\n __int64 v1; // rdi\n unsigned __int64 v2; // rax\n __int64 v3; // rcx\n _BYTE *v4; // rdx\n\n v1 = __strcpy_chk(&result_1, a1, 100LL);\n v2 = (unsigned __int8)result_1;\n if ( result_1 )\n {\n v3 = 0x500100000000LL;\n v4 = (_BYTE *)v1;\n do\n {\n if ( (unsigned __int8)v2 <= 0x2Eu && _bittest64(&v3, v2) )\n *v4 = 58;\n v2 = (unsigned __int8)*++v4;\n }\n while ( (_BYTE)v2 );\n }\n return v1;\n}", + "ida_strip_asm": "sub_1260:\nendbr64\nmov rsi, rdi\nsub rsp, 8\nmov edx, 64h ; 'd'\nlea rdi, byte_4040\ncall ___strcpy_chk\nmov rdi, rax\nmovzx eax, cs:byte_4040\ntest al, al\njz short loc_12B9\nmov rcx, 500100000000h\nmov rdx, rdi\nnop word ptr [rax+rax+00000000h]\nloc_12A0:\ncmp al, 2Eh ; '.'\nja short loc_12AD\nbt rcx, rax\njnb short loc_12AD\nmov byte ptr [rdx], 3Ah ; ':'\nloc_12AD:\nmovzx eax, byte ptr [rdx+1]\nadd rdx, 1\ntest al, al\njnz short loc_12A0\nloc_12B9:\nmov rax, rdi\nadd rsp, 8\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1260(__int64 a1)\n{\n __int64 v1; // rdi\n unsigned __int64 v2; // rax\n __int64 v3; // rcx\n _BYTE *v4; // rdx\n\n v1 = __strcpy_chk(&byte_4040, a1, 100LL);\n v2 = (unsigned __int8)byte_4040;\n if ( byte_4040 )\n {\n v3 = 0x500100000000LL;\n v4 = (_BYTE *)v1;\n do\n {\n if ( (unsigned __int8)v2 <= 0x2Eu && _bittest64(&v3, v2) )\n *v4 = 58;\n v2 = (unsigned __int8)*++v4;\n }\n while ( (_BYTE)v2 );\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1260(long long a1) {\n long long v1;\n unsigned long long v2;\n long long v3;\n uint8_t *v4;\n v1 = __strcpy_chk(&byte_4040, a1, 100LL);\n v2 = (unsigned char)byte_4040;\n if (byte_4040) {\n v3 = 87965225189376LL;\n v4 = (uint8_t *)v1;\n do {\n if ((unsigned char)v2 <= 46u && _bittest64(&v3, v2)) *v4 = 58;\n v2 = (unsigned char)*++v4;\n } while ((uint8_t)v2);\n }\n return v1;\n}", + "ida_pseudo_norm": "long long func0(long long a1) {\n long long v1;\n unsigned long long v2;\n long long v3;\n uint8_t *v4;\n v1 = __strcpy_chk(&result_1, a1, 100LL);\n v2 = (unsigned char)result_1;\n if (result_1) {\n v3 = 87965225189376LL;\n v4 = (uint8_t *)v1;\n do {\n if ((unsigned char)v2 <= 46u && _bittest64(&v3, v2)) *v4 = 58;\n v2 = (unsigned char)*++v4;\n } while ((uint8_t)v2);\n }\n return v1;\n}" + }, + { + "index": 542, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n static char result[100];\n strcpy(result, text);\n for (int i = 0; result[i] != '\\0'; i++) {\n if (result[i] == ' ' || result[i] == ',' || result[i] == '.')\n result[i] = ':';\n }\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"Boult Curve Wireless Neckband\"), \"Boult:Curve:Wireless:Neckband\") == 0);\n\n assert(strcmp(func0(\"Stereo Sound Sweatproof\"), \"Stereo:Sound:Sweatproof\") == 0);\n\n assert(strcmp(func0(\"Probass Curve Audio\"), \"Probass:Curve:Audio\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%rsi\nsub $0x8,%rsp\nmov $0x64,%edx\nlea 0x2dd9(%rip),%rdi\ncallq 1070 <__strcpy_chk@plt>\nmovzbl 0x2dcd(%rip),%eax\ntest %al,%al\nje 129a \nlea 0x2dc2(%rip),%rdx\nxchg %ax,%ax\nmov %eax,%ecx\nand $0xfffffffd,%ecx\ncmp $0x2c,%cl\nje 12b0 \ncmp $0x20,%al\nje 12b0 \nmovzbl 0x1(%rdx),%eax\nadd $0x1,%rdx\ntest %al,%al\njne 1280 \nlea 0x2d9f(%rip),%rax\nadd $0x8,%rsp\nretq\nnopw %cs:0x0(%rax,%rax,1)\nmovb $0x3a,(%rdx)\nmovzbl 0x1(%rdx),%eax\nadd $0x1,%rdx\ntest %al,%al\njne 1280 \nlea 0x2d7a(%rip),%rax\nadd $0x8,%rsp\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmov rsi, rdi\nsub rsp, 8\nmov edx, 64h ; 'd'\nlea rdi, result_1\ncall ___strcpy_chk\nmov rdi, rax\nmovzx eax, cs:result_1\ntest al, al\njz short loc_12B9\nmov rcx, 500100000000h\nmov rdx, rdi\nnop word ptr [rax+rax+00000000h]\nloc_12A0:\ncmp al, 2Eh ; '.'\nja short loc_12AD\nbt rcx, rax\njnb short loc_12AD\nmov byte ptr [rdx], 3Ah ; ':'\nloc_12AD:\nmovzx eax, byte ptr [rdx+1]\nadd rdx, 1\ntest al, al\njnz short loc_12A0\nloc_12B9:\nmov rax, rdi\nadd rsp, 8\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1)\n{\n __int64 v1; // rdi\n unsigned __int64 v2; // rax\n __int64 v3; // rcx\n _BYTE *v4; // rdx\n\n v1 = __strcpy_chk(&result_1, a1, 100LL);\n v2 = (unsigned __int8)result_1;\n if ( result_1 )\n {\n v3 = 0x500100000000LL;\n v4 = (_BYTE *)v1;\n do\n {\n if ( (unsigned __int8)v2 <= 0x2Eu && _bittest64(&v3, v2) )\n *v4 = 58;\n v2 = (unsigned __int8)*++v4;\n }\n while ( (_BYTE)v2 );\n }\n return v1;\n}", + "ida_strip_asm": "sub_1260:\nendbr64\nmov rsi, rdi\nsub rsp, 8\nmov edx, 64h ; 'd'\nlea rdi, byte_4040\ncall ___strcpy_chk\nmov rdi, rax\nmovzx eax, cs:byte_4040\ntest al, al\njz short loc_12B9\nmov rcx, 500100000000h\nmov rdx, rdi\nnop word ptr [rax+rax+00000000h]\nloc_12A0:\ncmp al, 2Eh ; '.'\nja short loc_12AD\nbt rcx, rax\njnb short loc_12AD\nmov byte ptr [rdx], 3Ah ; ':'\nloc_12AD:\nmovzx eax, byte ptr [rdx+1]\nadd rdx, 1\ntest al, al\njnz short loc_12A0\nloc_12B9:\nmov rax, rdi\nadd rsp, 8\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1260(__int64 a1)\n{\n __int64 v1; // rdi\n unsigned __int64 v2; // rax\n __int64 v3; // rcx\n _BYTE *v4; // rdx\n\n v1 = __strcpy_chk(&byte_4040, a1, 100LL);\n v2 = (unsigned __int8)byte_4040;\n if ( byte_4040 )\n {\n v3 = 0x500100000000LL;\n v4 = (_BYTE *)v1;\n do\n {\n if ( (unsigned __int8)v2 <= 0x2Eu && _bittest64(&v3, v2) )\n *v4 = 58;\n v2 = (unsigned __int8)*++v4;\n }\n while ( (_BYTE)v2 );\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1260(long long a1) {\n long long v1;\n unsigned long long v2;\n long long v3;\n uint8_t *v4;\n v1 = __strcpy_chk(&byte_4040, a1, 100LL);\n v2 = (unsigned char)byte_4040;\n if (byte_4040) {\n v3 = 87965225189376LL;\n v4 = (uint8_t *)v1;\n do {\n if ((unsigned char)v2 <= 46u && _bittest64(&v3, v2)) *v4 = 58;\n v2 = (unsigned char)*++v4;\n } while ((uint8_t)v2);\n }\n return v1;\n}", + "ida_pseudo_norm": "long long func0(long long a1) {\n long long v1;\n unsigned long long v2;\n long long v3;\n uint8_t *v4;\n v1 = __strcpy_chk(&result_1, a1, 100LL);\n v2 = (unsigned char)result_1;\n if (result_1) {\n v3 = 87965225189376LL;\n v4 = (uint8_t *)v1;\n do {\n if ((unsigned char)v2 <= 46u && _bittest64(&v3, v2)) *v4 = 58;\n v2 = (unsigned char)*++v4;\n } while ((uint8_t)v2);\n }\n return v1;\n}" + }, + { + "index": 543, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(long long num1, long long num2) {\n long long number = num1 + num2;\n int count = 0;\n while (number > 0) {\n number = number / 10;\n count = count + 1;\n }\n return count;\n}", + "test": "int main() {\n\n assert(func0(9875, 10) == 4);\n\n assert(func0(98759853034, 100) == 11);\n\n assert(func0(1234567, 500) == 7);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov -0x18(%rbp),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov %rax,-0x8(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 119e \nmov -0x8(%rbp),%rcx\nmovabs $0x6666666666666667,%rdx\nmov %rcx,%rax\nimul %rdx\nsar $0x2,%rdx\nmov %rcx,%rax\nsar $0x3f,%rax\nsub %rax,%rdx\nmov %rdx,%rax\nmov %rax,-0x8(%rbp)\naddl $0x1,-0xc(%rbp)\ncmpq $0x0,-0x8(%rbp)\njg 1171 \nmov -0xc(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov rdx, [rbp+var_18]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp short loc_119E\nloc_1171:\nmov rcx, [rbp+var_8]\nmov rdx, 6666666666666667h\nmov rax, rcx\nimul rdx\nmov rax, rdx\nsar rax, 2\nsar rcx, 3Fh\nmov rdx, rcx\nsub rax, rdx\nmov [rbp+var_8], rax\nadd [rbp+var_C], 1\nloc_119E:\ncmp [rbp+var_8], 0\njg short loc_1171\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-Ch]\n __int64 v4; // [rsp+18h] [rbp-8h]\n\n v4 = a1 + a2;\n v3 = 0;\n while ( v4 > 0 )\n {\n v4 /= 10LL;\n ++v3;\n }\n return v3;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov rdx, [rbp+var_18]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp short loc_119E\nloc_1171:\nmov rcx, [rbp+var_8]\nmov rdx, 6666666666666667h\nmov rax, rcx\nimul rdx\nmov rax, rdx\nsar rax, 2\nsar rcx, 3Fh\nmov rdx, rcx\nsub rax, rdx\nmov [rbp+var_8], rax\nadd [rbp+var_C], 1\nloc_119E:\ncmp [rbp+var_8], 0\njg short loc_1171\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(__int64 a1, __int64 a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-Ch]\n __int64 v4; // [rsp+18h] [rbp-8h]\n\n v4 = a1 + a2;\n v3 = 0;\n while ( v4 > 0 )\n {\n v4 /= 10LL;\n ++v3;\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(long long a1, long long a2) {\n unsigned int v3;\n long long v4;\n v4 = a1 + a2;\n v3 = 0;\n while (v4 > 0) {\n v4 /= 10LL;\n ++v3;\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2) {\n unsigned int v3;\n long long v4;\n v4 = a1 + a2;\n v3 = 0;\n while (v4 > 0) {\n v4 /= 10LL;\n ++v3;\n }\n return v3;\n}" + }, + { + "index": 544, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* test_list[], int size) {\n static char res[1000];\n strcpy(res, \"\");\n for (int i = 0; i < size; i++) {\n strcat(res, test_list[i]);\n strcat(res, \" \");\n }\n res[strlen(res) - 1] = '\\0';\n return res;\n}", + "test": "int main() {\n\n char* list1[] = {\"1\", \"4\", \"6\", \"5\", \"8\", \"2\", \"9\", \"1\", \"10\"};\n\n assert(strcmp(func0(list1, 9), \"1 4 6 5 8 2 9 1 10\") == 0);\n\n\n\n char* list2[] = {\"2\", \"3\", \"4\", \"6\", \"9\", \"3\", \"2\", \"2\", \"11\"};\n\n assert(strcmp(func0(list2, 9), \"2 3 4 6 9 3 2 2 11\") == 0);\n\n\n\n char* list3[] = {\"14\", \"21\", \"9\", \"24\", \"19\", \"12\", \"29\", \"23\", \"17\"};\n\n assert(strcmp(func0(list3, 9), \"14 21 9 24 19 12 29 23 17\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovb $0x0,0x2e5d(%rip)\nmovl $0x0,-0x4(%rbp)\njmp 124a \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov %rax,%rsi\nlea 0x2e33(%rip),%rdi\ncallq 10d0 \nlea 0x2e27(%rip),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nlea 0x2e02(%rip),%rax\nadd %rdx,%rax\nmovw $0x20,(%rax)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11ec \nlea 0x2de7(%rip),%rdi\ncallq 1090 \nlea -0x1(%rax),%rdx\nlea 0x2dd7(%rip),%rax\nmovb $0x0,(%rdx,%rax,1)\nlea 0x2dcc(%rip),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov cs:res_1, 0\nmov [rbp+var_4], 0\njmp short loc_123A\nloc_11EC:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov rsi, rax; src\nlea rax, res_1\nmov rdi, rax; dest\ncall _strcat\nlea rax, res_1\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nlea rax, res_1\nadd rax, rdx\nmov word ptr [rax], 20h ; ' '\nadd [rbp+var_4], 1\nloc_123A:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11EC\nlea rax, res_1\nmov rdi, rax; s\ncall _strlen\nlea rdx, [rax-1]\nlea rax, res_1\nmov byte ptr [rdx+rax], 0\nlea rax, res_1\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+1Ch] [rbp-4h]\n\n res_1[0] = 0;\n for ( i = 0; i < a2; ++i )\n {\n strcat(res_1, *(const char **)(8LL * i + a1));\n *(_WORD *)&res_1[strlen(res_1)] = 32;\n }\n res_1[strlen(res_1) - 1] = 0;\n return res_1;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov cs:s, 0\nmov [rbp+var_4], 0\njmp short loc_123A\nloc_11EC:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov rsi, rax; src\nlea rax, s\nmov rdi, rax; dest\ncall _strcat\nlea rax, s\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nlea rax, s\nadd rax, rdx\nmov word ptr [rax], 20h ; ' '\nadd [rbp+var_4], 1\nloc_123A:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11EC\nlea rax, s\nmov rdi, rax; s\ncall _strlen\nlea rdx, [rax-1]\nlea rax, s\nmov byte ptr [rdx+rax], 0\nlea rax, s\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11C9(__int64 a1, int a2)\n{\n int i; // [rsp+1Ch] [rbp-4h]\n\n s[0] = 0;\n for ( i = 0; i < a2; ++i )\n {\n strcat(s, *(const char **)(8LL * i + a1));\n *(_WORD *)&s[strlen(s)] = 32;\n }\n s[strlen(s) - 1] = 0;\n return s;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11C9(long long a1, int a2) {\n int i;\n s[0] = 0;\n for (i = 0; i < a2; ++i) {\n strcat(s, *(const char **)(8LL * i + a1));\n *(unsigned short *)&s[strlen(s)] = 32;\n }\n s[strlen(s) - 1] = 0;\n return s;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2) {\n int i;\n res_1[0] = 0;\n for (i = 0; i < a2; ++i) {\n strcat(res_1, *(const char **)(8LL * i + a1));\n *(unsigned short *)&res_1[strlen(res_1)] = 32;\n }\n res_1[strlen(res_1) - 1] = 0;\n return res_1;\n}" + }, + { + "index": 544, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* test_list[], int size) {\n static char res[1000];\n strcpy(res, \"\");\n for (int i = 0; i < size; i++) {\n strcat(res, test_list[i]);\n strcat(res, \" \");\n }\n res[strlen(res) - 1] = '\\0';\n return res;\n}", + "test": "int main() {\n\n char* list1[] = {\"1\", \"4\", \"6\", \"5\", \"8\", \"2\", \"9\", \"1\", \"10\"};\n\n assert(strcmp(func0(list1, 9), \"1 4 6 5 8 2 9 1 10\") == 0);\n\n\n\n char* list2[] = {\"2\", \"3\", \"4\", \"6\", \"9\", \"3\", \"2\", \"2\", \"11\"};\n\n assert(strcmp(func0(list2, 9), \"2 3 4 6 9 3 2 2 11\") == 0);\n\n\n\n char* list3[] = {\"14\", \"21\", \"9\", \"24\", \"19\", \"12\", \"29\", \"23\", \"17\"};\n\n assert(strcmp(func0(list3, 9), \"14 21 9 24 19 12 29 23 17\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmovb $0x0,0x2ea8(%rip)\ntest %esi,%esi\njle 11db \nmov %rdi,%rbx\nlea -0x1(%rsi),%eax\nlea 0x8(%rdi,%rax,8),%r12\nlea 0x2e92(%rip),%rbp\nmov $0x3e8,%edx\nmov (%rbx),%rsi\nmov %rbp,%rdi\ncallq 1070 <__strcat_chk@plt>\nmov $0x3e8,%edx\nlea 0xe3a(%rip),%rsi\nmov %rbp,%rdi\ncallq 1070 <__strcat_chk@plt>\nadd $0x8,%rbx\ncmp %r12,%rbx\njne 11ae \nlea 0x2e5e(%rip),%rdx\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nnot %rcx\nmovb $0x0,-0x2(%rdx,%rcx,1)\nmov %rdx,%rax\npop %rbx\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov cs:res_1, 0\ntest esi, esi\njle short loc_1223\nmov rbx, rdi\nmovsxd rsi, esi\nlea r13, [rdi+rsi*8]\nlea rbp, res_1\nlea r12, a658; \" 658\"\nloc_11FA:\nmov rsi, [rbx]\nmov edx, 3E8h\nmov rdi, rbp\ncall ___strcat_chk\nmov edx, 3E8h\nmov rsi, r12\nmov rdi, rbp\ncall ___strcat_chk\nadd rbx, 8\ncmp rbx, r13\njnz short loc_11FA\nloc_1223:\nlea rbx, res_1\nmov rdi, rbx; s\ncall _strlen\nmov byte ptr [rbx+rax-1], 0\nmov rax, rbx\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "char *__fastcall func0(_QWORD *a1, int a2)\n{\n _QWORD *v2; // rbx\n\n res_1[0] = 0;\n if ( a2 > 0 )\n {\n v2 = a1;\n do\n {\n __strcat_chk(res_1, *v2, 1000LL);\n __strcat_chk(res_1, a658, 1000LL);\n ++v2;\n }\n while ( v2 != &a1[a2] );\n }\n res_1[strlen(res_1) - 1] = 0;\n return res_1;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov cs:s, 0\ntest esi, esi\njle short loc_1223\nmov rbx, rdi\nmovsxd rsi, esi\nlea r13, [rdi+rsi*8]\nlea rbp, s\nlea r12, a658; \" 658\"\nloc_11FA:\nmov rsi, [rbx]\nmov edx, 3E8h\nmov rdi, rbp\ncall ___strcat_chk\nmov edx, 3E8h\nmov rsi, r12\nmov rdi, rbp\ncall ___strcat_chk\nadd rbx, 8\ncmp rbx, r13\njnz short loc_11FA\nloc_1223:\nlea rbx, s\nmov rdi, rbx; s\ncall _strlen\nmov byte ptr [rbx+rax-1], 0\nmov rax, rbx\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11C9(_QWORD *a1, int a2)\n{\n _QWORD *v2; // rbx\n\n s[0] = 0;\n if ( a2 > 0 )\n {\n v2 = a1;\n do\n {\n __strcat_chk(s, *v2, 1000LL);\n __strcat_chk(s, a658, 1000LL);\n ++v2;\n }\n while ( v2 != &a1[a2] );\n }\n s[strlen(s) - 1] = 0;\n return s;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11C9(uint64_t *a1, int a2) {\n uint64_t *v2;\n s[0] = 0;\n if (a2 > 0) {\n v2 = a1;\n do {\n __strcat_chk(s, *v2, 1000LL);\n __strcat_chk(s, a658, 1000LL);\n ++v2;\n } while (v2 != &a1[a2]);\n }\n s[strlen(s) - 1] = 0;\n return s;\n}", + "ida_pseudo_norm": "char *func0(uint64_t *a1, int a2) {\n uint64_t *v2;\n res_1[0] = 0;\n if (a2 > 0) {\n v2 = a1;\n do {\n __strcat_chk(res_1, *v2, 1000LL);\n __strcat_chk(res_1, a658, 1000LL);\n ++v2;\n } while (v2 != &a1[a2]);\n }\n res_1[strlen(res_1) - 1] = 0;\n return res_1;\n}" + }, + { + "index": 544, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* test_list[], int size) {\n static char res[1000];\n strcpy(res, \"\");\n for (int i = 0; i < size; i++) {\n strcat(res, test_list[i]);\n strcat(res, \" \");\n }\n res[strlen(res) - 1] = '\\0';\n return res;\n}", + "test": "int main() {\n\n char* list1[] = {\"1\", \"4\", \"6\", \"5\", \"8\", \"2\", \"9\", \"1\", \"10\"};\n\n assert(strcmp(func0(list1, 9), \"1 4 6 5 8 2 9 1 10\") == 0);\n\n\n\n char* list2[] = {\"2\", \"3\", \"4\", \"6\", \"9\", \"3\", \"2\", \"2\", \"11\"};\n\n assert(strcmp(func0(list2, 9), \"2 3 4 6 9 3 2 2 11\") == 0);\n\n\n\n char* list3[] = {\"14\", \"21\", \"9\", \"24\", \"19\", \"12\", \"29\", \"23\", \"17\"};\n\n assert(strcmp(func0(list3, 9), \"14 21 9 24 19 12 29 23 17\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmovb $0x0,0x2c23(%rip)\npush %rbp\npush %rbx\ntest %esi,%esi\njle 14ad \nlea -0x1(%rsi),%eax\nmov %rdi,%r12\nlea 0x2ff4(%rip),%rbx\nlea 0x8(%rdi,%rax,8),%rbp\nnopl 0x0(%rax)\nlea 0x2bf9(%rip),%rdi\nmov (%rdi),%edx\nadd $0x4,%rdi\nlea -0x1010101(%rdx),%eax\nnot %edx\nand %edx,%eax\nand $0x80808080,%eax\nje 1447 \nmov %eax,%edx\nshr $0x10,%edx\ntest $0x8080,%eax\ncmove %edx,%eax\nlea 0x2(%rdi),%rdx\ncmove %rdx,%rdi\nmov $0x3e8,%edx\nmov %eax,%esi\nadd %al,%sil\nmov (%r12),%rsi\nsbb $0x3,%rdi\nadd $0x8,%r12\ncallq 10b0 <__stpcpy_chk@plt>\nmov %rbx,%rcx\nmov $0x2,%edx\nlea 0xb67(%rip),%rsi\nmov %rax,%rdi\nsub %rax,%rcx\ncallq 10a0 <__memcpy_chk@plt>\ncmp %rbp,%r12\njne 1440 \nlea 0x2b8c(%rip),%rsi\nmov %rsi,%rdi\nmov %rsi,%rdx\nmov (%rdx),%ecx\nadd $0x4,%rdx\nlea -0x1010101(%rcx),%eax\nnot %ecx\nand %ecx,%eax\nand $0x80808080,%eax\nje 14ba \nmov %eax,%ecx\nshr $0x10,%ecx\ntest $0x8080,%eax\ncmove %ecx,%eax\nlea 0x2(%rdx),%rcx\ncmove %rcx,%rdx\nmov %eax,%ebx\nadd %al,%bl\nlea 0x2b4f(%rip),%rax\nsbb $0x3,%rdx\nsub %rsi,%rdx\nmovb $0x0,-0x1(%rdi,%rdx,1)\npop %rbx\npop %rbp\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nlea rbx, res_1\nmov cs:res_1, 0\ntest esi, esi\njle short loc_1539\nmovsxd rsi, esi\nmov r14, rdi\nlea r12, [rbx+3E8h]\nlea r13, [rdi+rsi*8]\nlea rbp, unk_2004\nnop word ptr [rax+rax+00000000h]\nloc_1500:\nmov rdi, rbx; s\nadd r14, 8\ncall _strlen\nmov rsi, [r14-8]\nmov edx, 3E8h\nlea rdi, [rbx+rax]\ncall ___stpcpy_chk\nmov rcx, r12\nmov edx, 2\nmov rsi, rbp\nmov rdi, rax\nsub rcx, rax\ncall ___memcpy_chk\ncmp r14, r13\njnz short loc_1500\nloc_1539:\nmov rdi, rbx; s\ncall _strlen\nmov byte ptr [rbx+rax-1], 0\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // r14\n size_t v3; // rax\n __int64 v4; // rax\n\n res_1[0] = 0;\n if ( a2 > 0 )\n {\n v2 = a1;\n do\n {\n v2 += 8LL;\n v3 = strlen(res_1);\n v4 = __stpcpy_chk(&res_1[v3], *(_QWORD *)(v2 - 8), 1000LL);\n __memcpy_chk(v4, &unk_2004, 2LL, &res_1[-v4 + 1000]);\n }\n while ( v2 != a1 + 8LL * a2 );\n }\n res_1[strlen(res_1) - 1] = 0;\n return res_1;\n}", + "ida_strip_asm": "sub_14C0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nlea rbx, s\nmov cs:s, 0\ntest esi, esi\njle short loc_1539\nmovsxd rsi, esi\nmov r14, rdi\nlea r12, [rbx+3E8h]\nlea r13, [rdi+rsi*8]\nlea rbp, unk_2004\nnop word ptr [rax+rax+00000000h]\nloc_1500:\nmov rdi, rbx; s\nadd r14, 8\ncall _strlen\nmov rsi, [r14-8]\nmov edx, 3E8h\nlea rdi, [rbx+rax]\ncall ___stpcpy_chk\nmov rcx, r12\nmov edx, 2\nmov rsi, rbp\nmov rdi, rax\nsub rcx, rax\ncall ___memcpy_chk\ncmp r14, r13\njnz short loc_1500\nloc_1539:\nmov rdi, rbx; s\ncall _strlen\nmov byte ptr [rbx+rax-1], 0\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "char *__fastcall sub_14C0(__int64 a1, int a2)\n{\n __int64 v2; // r14\n size_t v3; // rax\n __int64 v4; // rax\n\n s[0] = 0;\n if ( a2 > 0 )\n {\n v2 = a1;\n do\n {\n v2 += 8LL;\n v3 = strlen(s);\n v4 = __stpcpy_chk(&s[v3], *(_QWORD *)(v2 - 8), 1000LL);\n __memcpy_chk(v4, &unk_2004, 2LL, &s[-v4 + 1000]);\n }\n while ( v2 != a1 + 8LL * a2 );\n }\n s[strlen(s) - 1] = 0;\n return s;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_14C0(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n long long v4;\n s[0] = 0;\n if (a2 > 0) {\n v2 = a1;\n do {\n v2 += 8LL;\n v3 = strlen(s);\n v4 = __stpcpy_chk(&s[v3], *(uint64_t *)(v2 - 8), 1000LL);\n __memcpy_chk(v4, &unk_2004, 2LL, &s[-v4 + 1000]);\n } while (v2 != a1 + 8LL * a2);\n }\n s[strlen(s) - 1] = 0;\n return s;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n long long v4;\n res_1[0] = 0;\n if (a2 > 0) {\n v2 = a1;\n do {\n v2 += 8LL;\n v3 = strlen(res_1);\n v4 = __stpcpy_chk(&res_1[v3], *(uint64_t *)(v2 - 8), 1000LL);\n __memcpy_chk(v4, &unk_2004, 2LL, &res_1[-v4 + 1000]);\n } while (v2 != a1 + 8LL * a2);\n }\n res_1[strlen(res_1) - 1] = 0;\n return res_1;\n}" + }, + { + "index": 544, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* test_list[], int size) {\n static char res[1000];\n strcpy(res, \"\");\n for (int i = 0; i < size; i++) {\n strcat(res, test_list[i]);\n strcat(res, \" \");\n }\n res[strlen(res) - 1] = '\\0';\n return res;\n}", + "test": "int main() {\n\n char* list1[] = {\"1\", \"4\", \"6\", \"5\", \"8\", \"2\", \"9\", \"1\", \"10\"};\n\n assert(strcmp(func0(list1, 9), \"1 4 6 5 8 2 9 1 10\") == 0);\n\n\n\n char* list2[] = {\"2\", \"3\", \"4\", \"6\", \"9\", \"3\", \"2\", \"2\", \"11\"};\n\n assert(strcmp(func0(list2, 9), \"2 3 4 6 9 3 2 2 11\") == 0);\n\n\n\n char* list3[] = {\"14\", \"21\", \"9\", \"24\", \"19\", \"12\", \"29\", \"23\", \"17\"};\n\n assert(strcmp(func0(list3, 9), \"14 21 9 24 19 12 29 23 17\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmovb $0x0,0x2be3(%rip)\npush %rbp\npush %rbx\ntest %esi,%esi\njle 14ed \nlea -0x1(%rsi),%eax\nmov %rdi,%r12\nlea 0x2fb4(%rip),%rbx\nlea 0x8(%rdi,%rax,8),%rbp\nnopl 0x0(%rax)\nlea 0x2bb9(%rip),%rdi\nmov (%rdi),%edx\nadd $0x4,%rdi\nlea -0x1010101(%rdx),%eax\nnot %edx\nand %edx,%eax\nand $0x80808080,%eax\nje 1487 \nmov %eax,%edx\nshr $0x10,%edx\ntest $0x8080,%eax\ncmove %edx,%eax\nlea 0x2(%rdi),%rdx\ncmove %rdx,%rdi\nmov $0x3e8,%edx\nmov %eax,%esi\nadd %al,%sil\nmov (%r12),%rsi\nsbb $0x3,%rdi\nadd $0x8,%r12\ncallq 10b0 <__stpcpy_chk@plt>\nmov %rbx,%rcx\nmov $0x2,%edx\nlea 0xb27(%rip),%rsi\nmov %rax,%rdi\nsub %rax,%rcx\ncallq 10a0 <__memcpy_chk@plt>\ncmp %r12,%rbp\njne 1480 \nlea 0x2b4c(%rip),%rsi\nmov %rsi,%rdi\nmov %rsi,%rdx\nmov (%rdx),%ecx\nadd $0x4,%rdx\nlea -0x1010101(%rcx),%eax\nnot %ecx\nand %ecx,%eax\nand $0x80808080,%eax\nje 14fa \nmov %eax,%ecx\nshr $0x10,%ecx\ntest $0x8080,%eax\ncmove %ecx,%eax\nlea 0x2(%rdx),%rcx\ncmove %rcx,%rdx\nmov %eax,%ebx\nadd %al,%bl\nlea 0x2b0f(%rip),%rax\nsbb $0x3,%rdx\nsub %rsi,%rdx\nmovb $0x0,-0x1(%rdi,%rdx,1)\npop %rbx\npop %rbp\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nlea rbx, res_1\nmov cs:res_1, 0\ntest esi, esi\njle short loc_1539\nmovsxd rsi, esi\nmov r14, rdi\nlea r12, [rbx+3E8h]\nlea r13, [rdi+rsi*8]\nlea rbp, unk_2004\nnop word ptr [rax+rax+00000000h]\nloc_1500:\nmov rdi, rbx; s\nadd r14, 8\ncall _strlen\nmov rsi, [r14-8]\nmov edx, 3E8h\nlea rdi, [rbx+rax]\ncall ___stpcpy_chk\nmov rcx, r12\nmov edx, 2\nmov rsi, rbp\nmov rdi, rax\nsub rcx, rax\ncall ___memcpy_chk\ncmp r13, r14\njnz short loc_1500\nloc_1539:\nmov rdi, rbx; s\ncall _strlen\nmov byte ptr [rbx+rax-1], 0\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // r14\n size_t v3; // rax\n __int64 v4; // rax\n\n res_1[0] = 0;\n if ( a2 > 0 )\n {\n v2 = a1;\n do\n {\n v2 += 8LL;\n v3 = strlen(res_1);\n v4 = __stpcpy_chk(&res_1[v3], *(_QWORD *)(v2 - 8), 1000LL);\n __memcpy_chk(v4, &unk_2004, 2LL, &res_1[-v4 + 1000]);\n }\n while ( a1 + 8LL * a2 != v2 );\n }\n res_1[strlen(res_1) - 1] = 0;\n return res_1;\n}", + "ida_strip_asm": "sub_14C0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nlea rbx, s\nmov cs:s, 0\ntest esi, esi\njle short loc_1539\nmovsxd rsi, esi\nmov r14, rdi\nlea r12, [rbx+3E8h]\nlea r13, [rdi+rsi*8]\nlea rbp, unk_2004\nnop word ptr [rax+rax+00000000h]\nloc_1500:\nmov rdi, rbx; s\nadd r14, 8\ncall _strlen\nmov rsi, [r14-8]\nmov edx, 3E8h\nlea rdi, [rbx+rax]\ncall ___stpcpy_chk\nmov rcx, r12\nmov edx, 2\nmov rsi, rbp\nmov rdi, rax\nsub rcx, rax\ncall ___memcpy_chk\ncmp r13, r14\njnz short loc_1500\nloc_1539:\nmov rdi, rbx; s\ncall _strlen\nmov byte ptr [rbx+rax-1], 0\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "char *__fastcall sub_14C0(__int64 a1, int a2)\n{\n __int64 v2; // r14\n size_t v3; // rax\n __int64 v4; // rax\n\n s[0] = 0;\n if ( a2 > 0 )\n {\n v2 = a1;\n do\n {\n v2 += 8LL;\n v3 = strlen(s);\n v4 = __stpcpy_chk(&s[v3], *(_QWORD *)(v2 - 8), 1000LL);\n __memcpy_chk(v4, &unk_2004, 2LL, &s[-v4 + 1000]);\n }\n while ( a1 + 8LL * a2 != v2 );\n }\n s[strlen(s) - 1] = 0;\n return s;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_14C0(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n long long v4;\n s[0] = 0;\n if (a2 > 0) {\n v2 = a1;\n do {\n v2 += 8LL;\n v3 = strlen(s);\n v4 = __stpcpy_chk(&s[v3], *(uint64_t *)(v2 - 8), 1000LL);\n __memcpy_chk(v4, &unk_2004, 2LL, &s[-v4 + 1000]);\n } while (a1 + 8LL * a2 != v2);\n }\n s[strlen(s) - 1] = 0;\n return s;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n long long v4;\n res_1[0] = 0;\n if (a2 > 0) {\n v2 = a1;\n do {\n v2 += 8LL;\n v3 = strlen(res_1);\n v4 = __stpcpy_chk(&res_1[v3], *(uint64_t *)(v2 - 8), 1000LL);\n __memcpy_chk(v4, &unk_2004, 2LL, &res_1[-v4 + 1000]);\n } while (a1 + 8LL * a2 != v2);\n }\n res_1[strlen(res_1) - 1] = 0;\n return res_1;\n}" + }, + { + "index": 545, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\nint take_L_and_F_set_bits(int n) {\n\n n = n | n >> 1;\n\n n = n | n >> 2;\n\n n = n | n >> 4;\n\n n = n | n >> 8;\n\n n = n | n >> 16;\n\n return ((n + 1) >> 1) + 1;\n\n}\n\n\n\n", + "func": "int func0(int n) {\n if (n == 1) {\n return 0;\n }\n return n ^ take_L_and_F_set_bits(n);\n}", + "test": "int main() {\n\n assert(func0(10) == 3);\n\n assert(func0(15) == 6);\n\n assert(func0(20) == 5);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x8,%rsp\nmov %edi,-0x4(%rbp)\ncmpl $0x1,-0x4(%rbp)\njne 11a9 \nmov $0x0,%eax\njmp 11b6 \nmov -0x4(%rbp),%eax\nmov %eax,%edi\ncallq 1149 \nxor -0x4(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 8\nmov [rbp+var_4], edi\ncmp [rbp+var_4], 1\njnz short loc_11A9\nmov eax, 0\njmp short locret_11B6\nloc_11A9:\nmov eax, [rbp+var_4]\nmov edi, eax\ncall take_L_and_F_set_bits\nxor eax, [rbp+var_4]\nlocret_11B6:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1)\n{\n if ( a1 == 1 )\n return 0LL;\n else\n return a1 ^ (unsigned int)take_L_and_F_set_bits(a1);\n}", + "ida_strip_asm": "sub_118D:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 8\nmov [rbp+var_4], edi\ncmp [rbp+var_4], 1\njnz short loc_11A9\nmov eax, 0\njmp short locret_11B6\nloc_11A9:\nmov eax, [rbp+var_4]\nmov edi, eax\ncall sub_1149\nxor eax, [rbp+var_4]\nlocret_11B6:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_118D(unsigned int a1)\n{\n if ( a1 == 1 )\n return 0LL;\n else\n return a1 ^ (unsigned int)sub_1149(a1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_118D(unsigned int a1) {\n if (a1 == 1)\n return 0LL;\n else\n return a1 ^ (unsigned int)sub_1149(a1);\n}", + "ida_pseudo_norm": "long long func0(unsigned int a1) {\n if (a1 == 1)\n return 0LL;\n else\n return a1 ^ (unsigned int)take_L_and_F_set_bits(a1);\n}" + }, + { + "index": 546, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *string, char c) {\n int flag = -1;\n int length = strlen(string);\n for (int i = 0; i < length; i++) {\n if (string[i] == c) {\n flag = i;\n }\n }\n if (flag == -1) {\n return -1;\n } else {\n return flag + 1;\n }\n}", + "test": "int main() {\n\n assert(func0(\"hello world\", 'l') == 10);\n\n assert(func0(\"language\", 'g') == 7);\n\n assert(func0(\"little\", 'y') == -1); // -1 indicates None in Python\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,%eax\nmov %al,-0x1c(%rbp)\nmovl $0xffffffff,-0xc(%rbp)\nmov -0x18(%rbp),%rax\nmov %rax,%rdi\ncallq 1060 \nmov %eax,-0x4(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11bc \nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp %al,-0x1c(%rbp)\njne 11b8 \nmov -0x8(%rbp),%eax\nmov %eax,-0xc(%rbp)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x4(%rbp),%eax\njl 119d \ncmpl $0xffffffff,-0xc(%rbp)\njne 11d1 \nmov $0xffffffff,%eax\njmp 11d7 \nmov -0xc(%rbp),%eax\nadd $0x1,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov eax, esi\nmov [rbp+var_1C], al\nmov [rbp+var_C], 0FFFFFFFFh\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_8], 0\njmp short loc_11BC\nloc_119D:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp [rbp+var_1C], al\njnz short loc_11B8\nmov eax, [rbp+var_8]\nmov [rbp+var_C], eax\nloc_11B8:\nadd [rbp+var_8], 1\nloc_11BC:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njl short loc_119D\ncmp [rbp+var_C], 0FFFFFFFFh\njnz short loc_11D1\nmov eax, 0FFFFFFFFh\njmp short locret_11D7\nloc_11D1:\nmov eax, [rbp+var_C]\nadd eax, 1\nlocret_11D7:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, char a2)\n{\n int v3; // [rsp+14h] [rbp-Ch]\n int i; // [rsp+18h] [rbp-8h]\n int v5; // [rsp+1Ch] [rbp-4h]\n\n v3 = -1;\n v5 = strlen(a1);\n for ( i = 0; i < v5; ++i )\n {\n if ( a2 == a1[i] )\n v3 = i;\n }\n if ( v3 == -1 )\n return 0xFFFFFFFFLL;\n else\n return (unsigned int)(v3 + 1);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov eax, esi\nmov [rbp+var_1C], al\nmov [rbp+var_C], 0FFFFFFFFh\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_8], 0\njmp short loc_11BC\nloc_119D:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp [rbp+var_1C], al\njnz short loc_11B8\nmov eax, [rbp+var_8]\nmov [rbp+var_C], eax\nloc_11B8:\nadd [rbp+var_8], 1\nloc_11BC:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njl short loc_119D\ncmp [rbp+var_C], 0FFFFFFFFh\njnz short loc_11D1\nmov eax, 0FFFFFFFFh\njmp short locret_11D7\nloc_11D1:\nmov eax, [rbp+var_C]\nadd eax, 1\nlocret_11D7:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1, char a2)\n{\n int v3; // [rsp+14h] [rbp-Ch]\n int i; // [rsp+18h] [rbp-8h]\n int v5; // [rsp+1Ch] [rbp-4h]\n\n v3 = -1;\n v5 = strlen(a1);\n for ( i = 0; i < v5; ++i )\n {\n if ( a2 == a1[i] )\n v3 = i;\n }\n if ( v3 == -1 )\n return 0xFFFFFFFFLL;\n else\n return (unsigned int)(v3 + 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1, char a2) {\n int v3;\n int i;\n int v5;\n v3 = -1;\n v5 = strlen(a1);\n for (i = 0; i < v5; ++i) {\n if (a2 == a1[i]) v3 = i;\n }\n if (v3 == -1)\n return 4294967295LL;\n else\n return (unsigned int)(v3 + 1);\n}", + "ida_pseudo_norm": "long long func0(const char *a1, char a2) {\n int v3;\n int i;\n int v5;\n v3 = -1;\n v5 = strlen(a1);\n for (i = 0; i < v5; ++i) {\n if (a2 == a1[i]) v3 = i;\n }\n if (v3 == -1)\n return 4294967295LL;\n else\n return (unsigned int)(v3 + 1);\n}" + }, + { + "index": 546, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *string, char c) {\n int flag = -1;\n int length = strlen(string);\n for (int i = 0; i < length; i++) {\n if (string[i] == c) {\n flag = i;\n }\n }\n if (flag == -1) {\n return -1;\n } else {\n return flag + 1;\n }\n}", + "test": "int main() {\n\n assert(func0(\"hello world\", 'l') == 10);\n\n assert(func0(\"language\", 'g') == 7);\n\n assert(func0(\"little\", 'y') == -1); // -1 indicates None in Python\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%r8\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nsub $0x1,%rcx\ntest %ecx,%ecx\njle 1196 \nlea -0x1(%rcx),%edi\nmov $0x0,%eax\nmov $0xffffffff,%edx\njmp 117b \nmov %rcx,%rax\ncmp %sil,(%r8,%rax,1)\ncmove %eax,%edx\nlea 0x1(%rax),%rcx\ncmp %rdi,%rax\njne 1178 \ncmp $0xffffffff,%edx\nje 1193 \nadd $0x1,%edx\nmov %edx,%eax\nretq\nmov $0xffffffff,%edx\njmp 1193 \n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov ebp, esi\ncall _strlen\ntest eax, eax\njle short loc_11B4\nlea esi, [rax-1]\nmov eax, 0\nmov edx, 0FFFFFFFFh\njmp short loc_1193\nloc_1190:\nmov rax, rcx\nloc_1193:\ncmp [rbx+rax], bpl\ncmovz edx, eax\nlea rcx, [rax+1]\ncmp rax, rsi\njnz short loc_1190\ncmp edx, 0FFFFFFFFh\njz short loc_11AB\nadd edx, 1\nloc_11AB:\nmov eax, edx\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_11B4:\nmov edx, 0FFFFFFFFh\njmp short loc_11AB", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, char a2)\n{\n int v3; // eax\n __int64 v4; // rsi\n __int64 v5; // rax\n unsigned int v6; // edx\n\n v3 = strlen(a1);\n if ( v3 <= 0 )\n {\n return (unsigned int)-1;\n }\n else\n {\n v4 = (unsigned int)(v3 - 1);\n v5 = 0LL;\n v6 = -1;\n while ( 1 )\n {\n if ( a1[v5] == a2 )\n v6 = v5;\n if ( v5 == v4 )\n break;\n ++v5;\n }\n if ( v6 != -1 )\n ++v6;\n }\n return v6;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov ebp, esi\ncall _strlen\ntest eax, eax\njle short loc_11B4\nlea esi, [rax-1]\nmov eax, 0\nmov edx, 0FFFFFFFFh\njmp short loc_1193\nloc_1190:\nmov rax, rcx\nloc_1193:\ncmp [rbx+rax], bpl\ncmovz edx, eax\nlea rcx, [rax+1]\ncmp rax, rsi\njnz short loc_1190\ncmp edx, 0FFFFFFFFh\njz short loc_11AB\nadd edx, 1\nloc_11AB:\nmov eax, edx\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_11B4:\nmov edx, 0FFFFFFFFh\njmp short loc_11AB", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1, char a2)\n{\n int v3; // eax\n __int64 v4; // rsi\n __int64 v5; // rax\n unsigned int v6; // edx\n\n v3 = strlen(a1);\n if ( v3 <= 0 )\n {\n return (unsigned int)-1;\n }\n else\n {\n v4 = (unsigned int)(v3 - 1);\n v5 = 0LL;\n v6 = -1;\n while ( 1 )\n {\n if ( a1[v5] == a2 )\n v6 = v5;\n if ( v5 == v4 )\n break;\n ++v5;\n }\n if ( v6 != -1 )\n ++v6;\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1, char a2) {\n int v3;\n long long v4;\n long long v5;\n unsigned int v6;\n v3 = strlen(a1);\n if (v3 <= 0) {\n return (unsigned int)-1;\n } else {\n v4 = (unsigned int)(v3 - 1);\n v5 = 0LL;\n v6 = -1;\n while (1) {\n if (a1[v5] == a2) v6 = v5;\n if (v5 == v4) break;\n ++v5;\n }\n if (v6 != -1) ++v6;\n }\n return v6;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, char a2) {\n int v3;\n long long v4;\n long long v5;\n unsigned int v6;\n v3 = strlen(a1);\n if (v3 <= 0) {\n return (unsigned int)-1;\n } else {\n v4 = (unsigned int)(v3 - 1);\n v5 = 0LL;\n v6 = -1;\n while (1) {\n if (a1[v5] == a2) v6 = v5;\n if (v5 == v4) break;\n ++v5;\n }\n if (v6 != -1) ++v6;\n }\n return v6;\n}" + }, + { + "index": 546, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *string, char c) {\n int flag = -1;\n int length = strlen(string);\n for (int i = 0; i < length; i++) {\n if (string[i] == c) {\n flag = i;\n }\n }\n if (flag == -1) {\n return -1;\n } else {\n return flag + 1;\n }\n}", + "test": "int main() {\n\n assert(func0(\"hello world\", 'l') == 10);\n\n assert(func0(\"language\", 'g') == 7);\n\n assert(func0(\"little\", 'y') == -1); // -1 indicates None in Python\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %esi,%ebp\npush %rbx\nmov %rdi,%rbx\nsub $0x8,%rsp\ncallq 1060 \ntest %eax,%eax\njle 1270 \nlea -0x1(%rax),%ecx\nmov $0xffffffff,%r8d\nxor %eax,%eax\njmp 124b \nnopl (%rax)\nmov %rdx,%rax\ncmp %bpl,(%rbx,%rax,1)\nlea 0x1(%rax),%rdx\ncmove %eax,%r8d\ncmp %rcx,%rax\njne 1248 \ncmp $0xffffffff,%r8d\nje 1266 \nadd $0x1,%r8d\nadd $0x8,%rsp\nmov %r8d,%eax\npop %rbx\npop %rbp\nretq\nadd $0x8,%rsp\nmov $0xffffffff,%r8d\nmov %r8d,%eax\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov ebp, esi\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\ntest eax, eax\njle short loc_1270\nlea esi, [rax-1]\nmov edx, 0FFFFFFFFh\nxor eax, eax\njmp short loc_124B\nloc_1248:\nmov rax, rcx\nloc_124B:\ncmp bpl, [rbx+rax]\nlea rcx, [rax+1]\ncmovz edx, eax\ncmp rsi, rax\njnz short loc_1248\ncmp edx, 0FFFFFFFFh\njz short loc_1263\nadd edx, 1\nloc_1263:\nadd rsp, 8\nmov eax, edx\npop rbx\npop rbp\nretn\nloc_1270:\nadd rsp, 8\nmov edx, 0FFFFFFFFh\nmov eax, edx\npop rbx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, char a2)\n{\n int v3; // eax\n __int64 v4; // rsi\n unsigned int v5; // edx\n __int64 i; // rax\n\n v3 = strlen(a1);\n if ( v3 <= 0 )\n return 0xFFFFFFFFLL;\n v4 = (unsigned int)(v3 - 1);\n v5 = -1;\n for ( i = 0LL; ; ++i )\n {\n if ( a2 == a1[i] )\n v5 = i;\n if ( v4 == i )\n break;\n }\n if ( v5 != -1 )\n ++v5;\n return v5;\n}", + "ida_strip_asm": "sub_1220:\nendbr64\npush rbp\nmov ebp, esi\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\ntest eax, eax\njle short loc_1270\nlea esi, [rax-1]\nmov edx, 0FFFFFFFFh\nxor eax, eax\njmp short loc_124B\nloc_1248:\nmov rax, rcx\nloc_124B:\ncmp bpl, [rbx+rax]\nlea rcx, [rax+1]\ncmovz edx, eax\ncmp rsi, rax\njnz short loc_1248\ncmp edx, 0FFFFFFFFh\njz short loc_1263\nadd edx, 1\nloc_1263:\nadd rsp, 8\nmov eax, edx\npop rbx\npop rbp\nretn\nloc_1270:\nadd rsp, 8\nmov edx, 0FFFFFFFFh\nmov eax, edx\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1220(const char *a1, char a2)\n{\n int v3; // eax\n __int64 v4; // rsi\n unsigned int v5; // edx\n __int64 i; // rax\n\n v3 = strlen(a1);\n if ( v3 <= 0 )\n return 0xFFFFFFFFLL;\n v4 = (unsigned int)(v3 - 1);\n v5 = -1;\n for ( i = 0LL; ; ++i )\n {\n if ( a2 == a1[i] )\n v5 = i;\n if ( v4 == i )\n break;\n }\n if ( v5 != -1 )\n ++v5;\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1220(const char *a1, char a2) {\n int v3;\n long long v4;\n unsigned int v5;\n long long i;\n v3 = strlen(a1);\n if (v3 <= 0) return 4294967295LL;\n v4 = (unsigned int)(v3 - 1);\n v5 = -1;\n for (i = 0LL;; ++i) {\n if (a2 == a1[i]) v5 = i;\n if (v4 == i) break;\n }\n if (v5 != -1) ++v5;\n return v5;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, char a2) {\n int v3;\n long long v4;\n unsigned int v5;\n long long i;\n v3 = strlen(a1);\n if (v3 <= 0) return 4294967295LL;\n v4 = (unsigned int)(v3 - 1);\n v5 = -1;\n for (i = 0LL;; ++i) {\n if (a2 == a1[i]) v5 = i;\n if (v4 == i) break;\n }\n if (v5 != -1) ++v5;\n return v5;\n}" + }, + { + "index": 546, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *string, char c) {\n int flag = -1;\n int length = strlen(string);\n for (int i = 0; i < length; i++) {\n if (string[i] == c) {\n flag = i;\n }\n }\n if (flag == -1) {\n return -1;\n } else {\n return flag + 1;\n }\n}", + "test": "int main() {\n\n assert(func0(\"hello world\", 'l') == 10);\n\n assert(func0(\"language\", 'g') == 7);\n\n assert(func0(\"little\", 'y') == -1); // -1 indicates None in Python\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %esi,%ebp\npush %rbx\nmov %rdi,%rbx\nsub $0x8,%rsp\ncallq 1060 \ntest %eax,%eax\njle 1270 \nlea -0x1(%rax),%ecx\nmov $0xffffffff,%r8d\nxor %eax,%eax\njmp 124b \nnopl (%rax)\nmov %rdx,%rax\ncmp (%rbx,%rax,1),%bpl\nlea 0x1(%rax),%rdx\ncmove %eax,%r8d\ncmp %rax,%rcx\njne 1248 \ncmp $0xffffffff,%r8d\nje 1266 \nadd $0x1,%r8d\nadd $0x8,%rsp\nmov %r8d,%eax\npop %rbx\npop %rbp\nretq\nadd $0x8,%rsp\nmov $0xffffffff,%r8d\nmov %r8d,%eax\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov ebp, esi\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\ntest eax, eax\njle short loc_1270\nlea esi, [rax-1]\nmov edx, 0FFFFFFFFh\nxor eax, eax\njmp short loc_124B\nloc_1248:\nmov rax, rcx\nloc_124B:\ncmp bpl, [rbx+rax]\nlea rcx, [rax+1]\ncmovz edx, eax\ncmp rsi, rax\njnz short loc_1248\ncmp edx, 0FFFFFFFFh\njz short loc_1263\nadd edx, 1\nloc_1263:\nadd rsp, 8\nmov eax, edx\npop rbx\npop rbp\nretn\nloc_1270:\nadd rsp, 8\nmov edx, 0FFFFFFFFh\nmov eax, edx\npop rbx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, char a2)\n{\n int v3; // eax\n __int64 v4; // rsi\n unsigned int v5; // edx\n __int64 i; // rax\n\n v3 = strlen(a1);\n if ( v3 <= 0 )\n return 0xFFFFFFFFLL;\n v4 = (unsigned int)(v3 - 1);\n v5 = -1;\n for ( i = 0LL; ; ++i )\n {\n if ( a2 == a1[i] )\n v5 = i;\n if ( v4 == i )\n break;\n }\n if ( v5 != -1 )\n ++v5;\n return v5;\n}", + "ida_strip_asm": "sub_1220:\nendbr64\npush rbp\nmov ebp, esi\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\ntest eax, eax\njle short loc_1270\nlea esi, [rax-1]\nmov edx, 0FFFFFFFFh\nxor eax, eax\njmp short loc_124B\nloc_1248:\nmov rax, rcx\nloc_124B:\ncmp bpl, [rbx+rax]\nlea rcx, [rax+1]\ncmovz edx, eax\ncmp rsi, rax\njnz short loc_1248\ncmp edx, 0FFFFFFFFh\njz short loc_1263\nadd edx, 1\nloc_1263:\nadd rsp, 8\nmov eax, edx\npop rbx\npop rbp\nretn\nloc_1270:\nadd rsp, 8\nmov edx, 0FFFFFFFFh\nmov eax, edx\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1220(const char *a1, char a2)\n{\n int v3; // eax\n __int64 v4; // rsi\n unsigned int v5; // edx\n __int64 i; // rax\n\n v3 = strlen(a1);\n if ( v3 <= 0 )\n return 0xFFFFFFFFLL;\n v4 = (unsigned int)(v3 - 1);\n v5 = -1;\n for ( i = 0LL; ; ++i )\n {\n if ( a2 == a1[i] )\n v5 = i;\n if ( v4 == i )\n break;\n }\n if ( v5 != -1 )\n ++v5;\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1220(const char *a1, char a2) {\n int v3;\n long long v4;\n unsigned int v5;\n long long i;\n v3 = strlen(a1);\n if (v3 <= 0) return 4294967295LL;\n v4 = (unsigned int)(v3 - 1);\n v5 = -1;\n for (i = 0LL;; ++i) {\n if (a2 == a1[i]) v5 = i;\n if (v4 == i) break;\n }\n if (v5 != -1) ++v5;\n return v5;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, char a2) {\n int v3;\n long long v4;\n unsigned int v5;\n long long i;\n v3 = strlen(a1);\n if (v3 <= 0) return 4294967295LL;\n v4 = (unsigned int)(v3 - 1);\n v5 = -1;\n for (i = 0LL;; ++i) {\n if (a2 == a1[i]) v5 = i;\n if (v4 == i) break;\n }\n if (v5 != -1) ++v5;\n return v5;\n}" + }, + { + "index": 547, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int n) {\n int i = 1;\n int sum = 0;\n while (n / i > 0) {\n sum = sum + n / i;\n i = i * 2;\n }\n return sum;\n}", + "test": "int main() {\n\n assert(func0(4) == 7);\n\n assert(func0(2) == 3);\n\n assert(func0(5) == 8);\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmovl $0x1,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 1171 \nmov -0x14(%rbp),%eax\ncltd\nidivl -0x8(%rbp)\nadd %eax,-0x4(%rbp)\nshll -0x8(%rbp)\nmov -0x14(%rbp),%eax\ncltd\nidivl -0x8(%rbp)\ntest %eax,%eax\njg 1164 \nmov -0x4(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_8], 1\nmov [rbp+var_4], 0\njmp short loc_1171\nloc_1164:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_8]\nadd [rbp+var_4], eax\nshl [rbp+var_8], 1\nloc_1171:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_8]\ntest eax, eax\njg short loc_1164\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v2; // [rsp+Ch] [rbp-8h]\n unsigned int v3; // [rsp+10h] [rbp-4h]\n\n v2 = 1;\n v3 = 0;\n while ( a1 / v2 > 0 )\n {\n v3 += a1 / v2;\n v2 *= 2;\n }\n return v3;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_8], 1\nmov [rbp+var_4], 0\njmp short loc_1171\nloc_1164:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_8]\nadd [rbp+var_4], eax\nshl [rbp+var_8], 1\nloc_1171:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_8]\ntest eax, eax\njg short loc_1164\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v2; // [rsp+Ch] [rbp-8h]\n unsigned int v3; // [rsp+10h] [rbp-4h]\n\n v2 = 1;\n v3 = 0;\n while ( a1 / v2 > 0 )\n {\n v3 += a1 / v2;\n v2 *= 2;\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v2;\n unsigned int v3;\n v2 = 1;\n v3 = 0;\n while (a1 / v2 > 0) {\n v3 += a1 / v2;\n v2 *= 2;\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v2;\n unsigned int v3;\n v2 = 1;\n v3 = 0;\n while (a1 / v2 > 0) {\n v3 += a1 / v2;\n v2 *= 2;\n }\n return v3;\n}" + }, + { + "index": 547, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int n) {\n int i = 1;\n int sum = 0;\n while (n / i > 0) {\n sum = sum + n / i;\n i = i * 2;\n }\n return sum;\n}", + "test": "int main() {\n\n assert(func0(4) == 7);\n\n assert(func0(2) == 3);\n\n assert(func0(5) == 8);\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\njle 116f \nmov %edi,%edx\nmov $0x0,%esi\nmov $0x1,%ecx\nadd %edx,%esi\nadd %ecx,%ecx\nmov %edi,%eax\ncltd\nidiv %ecx\nmov %eax,%edx\ntest %eax,%eax\njg 115d \nmov %esi,%eax\nretq\nmov $0x0,%esi\njmp 116c \n", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njle short loc_116F\nmov edx, edi\nmov esi, 0\nmov ecx, 1\nloc_115D:\nadd esi, edx\nadd ecx, ecx\nmov eax, edi\ncdq\nidiv ecx\nmov edx, eax\ntest eax, eax\njg short loc_115D\nloc_116C:\nmov eax, esi\nretn\nloc_116F:\nmov esi, 0\njmp short loc_116C", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // edx\n unsigned int v2; // esi\n int v3; // ecx\n\n if ( a1 <= 0 )\n {\n return 0;\n }\n else\n {\n v1 = a1;\n v2 = 0;\n v3 = 1;\n do\n {\n v2 += v1;\n v3 *= 2;\n v1 = a1 / v3;\n }\n while ( a1 / v3 > 0 );\n }\n return v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ntest edi, edi\njle short loc_116F\nmov edx, edi\nmov esi, 0\nmov ecx, 1\nloc_115D:\nadd esi, edx\nadd ecx, ecx\nmov eax, edi\ncdq\nidiv ecx\nmov edx, eax\ntest eax, eax\njg short loc_115D\nloc_116C:\nmov eax, esi\nretn\nloc_116F:\nmov esi, 0\njmp short loc_116C", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v1; // edx\n unsigned int v2; // esi\n int v3; // ecx\n\n if ( a1 <= 0 )\n {\n return 0;\n }\n else\n {\n v1 = a1;\n v2 = 0;\n v3 = 1;\n do\n {\n v2 += v1;\n v3 *= 2;\n v1 = a1 / v3;\n }\n while ( a1 / v3 > 0 );\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v1;\n unsigned int v2;\n int v3;\n if (a1 <= 0) {\n return 0;\n } else {\n v1 = a1;\n v2 = 0;\n v3 = 1;\n do {\n v2 += v1;\n v3 *= 2;\n v1 = a1 / v3;\n } while (a1 / v3 > 0);\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n unsigned int v2;\n int v3;\n if (a1 <= 0) {\n return 0;\n } else {\n v1 = a1;\n v2 = 0;\n v3 = 1;\n do {\n v2 += v1;\n v3 *= 2;\n v1 = a1 / v3;\n } while (a1 / v3 > 0);\n }\n return v2;\n}" + }, + { + "index": 548, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int longest_increasing_subsequence[n];\n for (int i = 0; i < n; i++) {\n longest_increasing_subsequence[i] = 1;\n }\n for (int i = 1; i < n; i++) {\n for (int j = 0; j < i; j++) {\n if (arr[i] > arr[j] && longest_increasing_subsequence[i] <\n longest_increasing_subsequence[j] + 1) {\n longest_increasing_subsequence[i] =\n longest_increasing_subsequence[j] + 1;\n }\n }\n }\n int maximum = 0;\n for (int i = 0; i < n; i++) {\n if (longest_increasing_subsequence[i] > maximum) {\n maximum = longest_increasing_subsequence[i];\n }\n }\n return maximum;\n}", + "test": "int main() {\n\n int arr1[] = {10, 22, 9, 33, 21, 50, 41, 60};\n\n int n1 = sizeof(arr1)/sizeof(arr1[0]);\n\n assert(func0(arr1, n1) == 5);\n\n\n\n int arr2[] = {3, 10, 2, 1, 20};\n\n int n2 = sizeof(arr2)/sizeof(arr2[0]);\n\n assert(func0(arr2, n2) == 3);\n\n\n\n int arr3[] = {50, 3, 10, 7, 40, 80};\n\n int n3 = sizeof(arr3)/sizeof(arr3[0]);\n\n assert(func0(arr3, n3) == 4);\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x48,%rsp\nmov %rdi,-0x48(%rbp)\nmov %esi,-0x4c(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmov %rsp,%rax\nmov %rax,%rsi\nmov -0x4c(%rbp),%eax\nmovslq %eax,%rdx\nsub $0x1,%rdx\nmov %rdx,-0x28(%rbp)\nmovslq %eax,%rdx\nmov %rdx,%r8\nmov $0x0,%r9d\nmovslq %eax,%rdx\nmov %rdx,%rcx\nmov $0x0,%ebx\ncltq\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%edi\nmov $0x0,%edx\ndiv %rdi\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rbx\nsub %rdx,%rbx\nmov %rbx,%rdx\ncmp %rdx,%rsp\nje 1228 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 1211 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 1252 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x20(%rbp)\nmovl $0x0,-0x30(%rbp)\njmp 1283 \nmov -0x20(%rbp),%rax\nmov -0x30(%rbp),%edx\nmovslq %edx,%rdx\nmovl $0x1,(%rax,%rdx,4)\naddl $0x1,-0x30(%rbp)\nmov -0x30(%rbp),%eax\ncmp -0x4c(%rbp),%eax\njl 126e \nmovl $0x1,-0x34(%rbp)\njmpq 131b \nmovl $0x0,-0x38(%rbp)\njmp 130f \nmov -0x34(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x38(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x48(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njle 130b \nmov -0x20(%rbp),%rax\nmov -0x38(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%ecx\nmov -0x20(%rbp),%rax\nmov -0x34(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\ncmp %eax,%ecx\njl 130b \nmov -0x20(%rbp),%rax\nmov -0x38(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nlea 0x1(%rax),%ecx\nmov -0x20(%rbp),%rax\nmov -0x34(%rbp),%edx\nmovslq %edx,%rdx\nmov %ecx,(%rax,%rdx,4)\naddl $0x1,-0x38(%rbp)\nmov -0x38(%rbp),%eax\ncmp -0x34(%rbp),%eax\njl 12a0 \naddl $0x1,-0x34(%rbp)\nmov -0x34(%rbp),%eax\ncmp -0x4c(%rbp),%eax\njl 1297 \nmovl $0x0,-0x3c(%rbp)\nmovl $0x0,-0x2c(%rbp)\njmp 135d \nmov -0x20(%rbp),%rax\nmov -0x2c(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\ncmp %eax,-0x3c(%rbp)\njge 1359 \nmov -0x20(%rbp),%rax\nmov -0x2c(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nmov %eax,-0x3c(%rbp)\naddl $0x1,-0x2c(%rbp)\nmov -0x2c(%rbp),%eax\ncmp -0x4c(%rbp),%eax\njl 1337 \nmov -0x3c(%rbp),%eax\nmov %rsi,%rsp\nmov -0x18(%rbp),%rdi\nxor %fs:0x28,%rdi\nje 137f \ncallq 1080 <__stack_chk_fail@plt>\nmov -0x8(%rbp),%rbx\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov eax, [rbp+var_3C]\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11F6:\ncmp rsp, rdx\njz short loc_120D\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_11F6\nloc_120D:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1237\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1237:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov [rbp+var_2C], 0\njmp short loc_1268\nloc_1253:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_2C]\nmovsxd rdx, edx\nmov dword ptr [rax+rdx*4], 1\nadd [rbp+var_2C], 1\nloc_1268:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_3C]\njl short loc_1253\nmov [rbp+var_28], 1\njmp loc_1300\nloc_127C:\nmov [rbp+var_24], 0\njmp short loc_12F4\nloc_1285:\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_24]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_12F0\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ncmp ecx, eax\njl short loc_12F0\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nlea ecx, [rax+1]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nloc_12F0:\nadd [rbp+var_24], 1\nloc_12F4:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_28]\njl short loc_1285\nadd [rbp+var_28], 1\nloc_1300:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_3C]\njl loc_127C\nmov [rbp+var_20], 0\nmov [rbp+var_1C], 0\njmp short loc_1342\nloc_131C:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ncmp [rbp+var_20], eax\njge short loc_133E\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov [rbp+var_20], eax\nloc_133E:\nadd [rbp+var_1C], 1\nloc_1342:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_3C]\njl short loc_131C\nmov eax, [rbp+var_20]\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1364\ncall ___stack_chk_fail\nlocret_1364:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned __int64 v2; // rax\n void *v3; // rsp\n _BYTE v5[4]; // [rsp+8h] [rbp-40h] BYREF\n int v6; // [rsp+Ch] [rbp-3Ch]\n __int64 v7; // [rsp+10h] [rbp-38h]\n int i; // [rsp+1Ch] [rbp-2Ch]\n int j; // [rsp+20h] [rbp-28h]\n int k; // [rsp+24h] [rbp-24h]\n unsigned int v11; // [rsp+28h] [rbp-20h]\n int m; // [rsp+2Ch] [rbp-1Ch]\n __int64 v13; // [rsp+30h] [rbp-18h]\n _BYTE *v14; // [rsp+38h] [rbp-10h]\n unsigned __int64 v15; // [rsp+40h] [rbp-8h]\n\n v7 = a1;\n v6 = a2;\n v15 = __readfsqword(0x28u);\n v13 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 0x10uLL);\n while ( v5 != &v5[-(v2 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = alloca(v2 & 0xFFF);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)&v5[(v2 & 0xFFF) - 8] = *(_QWORD *)&v5[(v2 & 0xFFF) - 8];\n v14 = v5;\n for ( i = 0; i < v6; ++i )\n *(_DWORD *)&v14[4 * i] = 1;\n for ( j = 1; j < v6; ++j )\n {\n for ( k = 0; k < j; ++k )\n {\n if ( *(_DWORD *)(4LL * j + v7) > *(_DWORD *)(4LL * k + v7) && *(_DWORD *)&v14[4 * k] >= *(_DWORD *)&v14[4 * j] )\n *(_DWORD *)&v14[4 * j] = *(_DWORD *)&v14[4 * k] + 1;\n }\n }\n v11 = 0;\n for ( m = 0; m < v6; ++m )\n {\n if ( (signed int)v11 < *(_DWORD *)&v14[4 * m] )\n v11 = *(_DWORD *)&v14[4 * m];\n }\n return v11;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov eax, [rbp+var_3C]\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11F6:\ncmp rsp, rdx\njz short loc_120D\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_11F6\nloc_120D:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1237\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1237:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov [rbp+var_2C], 0\njmp short loc_1268\nloc_1253:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_2C]\nmovsxd rdx, edx\nmov dword ptr [rax+rdx*4], 1\nadd [rbp+var_2C], 1\nloc_1268:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_3C]\njl short loc_1253\nmov [rbp+var_28], 1\njmp loc_1300\nloc_127C:\nmov [rbp+var_24], 0\njmp short loc_12F4\nloc_1285:\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_24]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_12F0\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ncmp ecx, eax\njl short loc_12F0\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nlea ecx, [rax+1]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nloc_12F0:\nadd [rbp+var_24], 1\nloc_12F4:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_28]\njl short loc_1285\nadd [rbp+var_28], 1\nloc_1300:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_3C]\njl loc_127C\nmov [rbp+var_20], 0\nmov [rbp+var_1C], 0\njmp short loc_1342\nloc_131C:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ncmp [rbp+var_20], eax\njge short loc_133E\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov [rbp+var_20], eax\nloc_133E:\nadd [rbp+var_1C], 1\nloc_1342:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_3C]\njl short loc_131C\nmov eax, [rbp+var_20]\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1364\ncall ___stack_chk_fail\nlocret_1364:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2)\n{\n unsigned __int64 v2; // rax\n void *v3; // rsp\n _BYTE v5[4]; // [rsp+8h] [rbp-40h] BYREF\n int v6; // [rsp+Ch] [rbp-3Ch]\n __int64 v7; // [rsp+10h] [rbp-38h]\n int i; // [rsp+1Ch] [rbp-2Ch]\n int j; // [rsp+20h] [rbp-28h]\n int k; // [rsp+24h] [rbp-24h]\n unsigned int v11; // [rsp+28h] [rbp-20h]\n int m; // [rsp+2Ch] [rbp-1Ch]\n __int64 v13; // [rsp+30h] [rbp-18h]\n _BYTE *v14; // [rsp+38h] [rbp-10h]\n unsigned __int64 v15; // [rsp+40h] [rbp-8h]\n\n v7 = a1;\n v6 = a2;\n v15 = __readfsqword(0x28u);\n v13 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 0x10uLL);\n while ( v5 != &v5[-(v2 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = alloca(v2 & 0xFFF);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)&v5[(v2 & 0xFFF) - 8] = *(_QWORD *)&v5[(v2 & 0xFFF) - 8];\n v14 = v5;\n for ( i = 0; i < v6; ++i )\n *(_DWORD *)&v14[4 * i] = 1;\n for ( j = 1; j < v6; ++j )\n {\n for ( k = 0; k < j; ++k )\n {\n if ( *(_DWORD *)(4LL * j + v7) > *(_DWORD *)(4LL * k + v7) && *(_DWORD *)&v14[4 * k] >= *(_DWORD *)&v14[4 * j] )\n *(_DWORD *)&v14[4 * j] = *(_DWORD *)&v14[4 * k] + 1;\n }\n }\n v11 = 0;\n for ( m = 0; m < v6; ++m )\n {\n if ( (signed int)v11 < *(_DWORD *)&v14[4 * m] )\n v11 = *(_DWORD *)&v14[4 * m];\n }\n return v11;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2) {\n unsigned long long v2;\n void *v3;\n uint8_t v5[4];\n int v6;\n long long v7;\n int i;\n int j;\n int k;\n unsigned int v11;\n int m;\n long long v13;\n uint8_t *v14;\n unsigned long long v15;\n v7 = a1;\n v6 = a2;\n v15 = __readfsqword(40u);\n v13 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 16uLL);\n while (v5 != &v5[-(v2 & 18446744073709547520LL)])\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)&v5[(v2 & 4095) - 8] = *(uint64_t *)&v5[(v2 & 4095) - 8];\n v14 = v5;\n for (i = 0; i < v6; ++i) *(uint32_t *)&v14[4 * i] = 1;\n for (j = 1; j < v6; ++j) {\n for (k = 0; k < j; ++k) {\n if (*(uint32_t *)(4LL * j + v7) > *(uint32_t *)(4LL * k + v7) &&\n *(uint32_t *)&v14[4 * k] >= *(uint32_t *)&v14[4 * j])\n *(uint32_t *)&v14[4 * j] = *(uint32_t *)&v14[4 * k] + 1;\n }\n }\n v11 = 0;\n for (m = 0; m < v6; ++m) {\n if ((signed int)v11 < *(uint32_t *)&v14[4 * m])\n v11 = *(uint32_t *)&v14[4 * m];\n }\n return v11;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned long long v2;\n void *v3;\n uint8_t v5[4];\n int v6;\n long long v7;\n int i;\n int j;\n int k;\n unsigned int v11;\n int m;\n long long v13;\n uint8_t *v14;\n unsigned long long v15;\n v7 = a1;\n v6 = a2;\n v15 = __readfsqword(40u);\n v13 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 16uLL);\n while (v5 != &v5[-(v2 & 18446744073709547520LL)])\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)&v5[(v2 & 4095) - 8] = *(uint64_t *)&v5[(v2 & 4095) - 8];\n v14 = v5;\n for (i = 0; i < v6; ++i) *(uint32_t *)&v14[4 * i] = 1;\n for (j = 1; j < v6; ++j) {\n for (k = 0; k < j; ++k) {\n if (*(uint32_t *)(4LL * j + v7) > *(uint32_t *)(4LL * k + v7) &&\n *(uint32_t *)&v14[4 * k] >= *(uint32_t *)&v14[4 * j])\n *(uint32_t *)&v14[4 * j] = *(uint32_t *)&v14[4 * k] + 1;\n }\n }\n v11 = 0;\n for (m = 0; m < v6; ++m) {\n if ((signed int)v11 < *(uint32_t *)&v14[4 * m])\n v11 = *(uint32_t *)&v14[4 * m];\n }\n return v11;\n}" + }, + { + "index": 548, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int longest_increasing_subsequence[n];\n for (int i = 0; i < n; i++) {\n longest_increasing_subsequence[i] = 1;\n }\n for (int i = 1; i < n; i++) {\n for (int j = 0; j < i; j++) {\n if (arr[i] > arr[j] && longest_increasing_subsequence[i] <\n longest_increasing_subsequence[j] + 1) {\n longest_increasing_subsequence[i] =\n longest_increasing_subsequence[j] + 1;\n }\n }\n }\n int maximum = 0;\n for (int i = 0; i < n; i++) {\n if (longest_increasing_subsequence[i] > maximum) {\n maximum = longest_increasing_subsequence[i];\n }\n }\n return maximum;\n}", + "test": "int main() {\n\n int arr1[] = {10, 22, 9, 33, 21, 50, 41, 60};\n\n int n1 = sizeof(arr1)/sizeof(arr1[0]);\n\n assert(func0(arr1, n1) == 5);\n\n\n\n int arr2[] = {3, 10, 2, 1, 20};\n\n int n2 = sizeof(arr2)/sizeof(arr2[0]);\n\n assert(func0(arr2, n2) == 3);\n\n\n\n int arr3[] = {50, 3, 10, 7, 40, 80};\n\n int n3 = sizeof(arr3)/sizeof(arr3[0]);\n\n assert(func0(arr3, n3) == 4);\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovslq %esi,%rax\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffffff0,%rdx\nand $0xfffffffffffff000,%rax\nmov %rsp,%rcx\nsub %rax,%rcx\nmov %rcx,%rax\ncmp %rax,%rsp\nje 11dc \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11c5 \nmov %rdx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 11f2 \norq $0x0,-0x8(%rsp,%rax,1)\nlea 0x3(%rsp),%rdx\nmov %rdx,%r9\nshr $0x2,%r9\nand $0xfffffffffffffffc,%rdx\nmov %rdx,%r8\ntest %esi,%esi\njle 1223 \nmov %rdx,%rax\nlea -0x1(%rsi),%ecx\nlea 0x4(%rdx,%rcx,4),%rdx\nmovl $0x1,(%rax)\nadd $0x4,%rax\ncmp %rdx,%rax\njne 1214 \ncmp $0x1,%esi\njle 1271 \nlea -0x2(%rsi),%r10d\nadd $0x2,%r10\nmov $0x1,%edx\njmp 1262 \nadd $0x1,%rax\ncmp %rdx,%rax\nje 1259 \ncmp (%rdi,%rax,4),%r9d\njle 1237 \nmov (%r8,%rax,4),%ecx\ncmp (%r8,%rdx,4),%ecx\njl 1237 \nadd $0x1,%ecx\nmov %ecx,(%r8,%rdx,4)\njmp 1237 \nadd $0x1,%rdx\ncmp %r10,%rdx\nje 127a \ntest %edx,%edx\njle 1259 \nmov (%rdi,%rdx,4),%r9d\nmov $0x0,%eax\njmp 1240 \nje 12a8 \nmov $0x0,%edx\njmp 1295 \nmov $0x0,%eax\nmov $0x0,%edx\nmov (%r8,%rax,4),%ecx\ncmp %ecx,%edx\ncmovl %ecx,%edx\nadd $0x1,%rax\ncmp %eax,%esi\njg 1284 \nmov -0x8(%rbp),%rax\nxor %fs:0x28,%rax\njne 12c1 \nmov %edx,%eax\nleaveq\nretq\ncmpl $0x0,0x0(,%r9,4)\nmov $0x0,%edx\ncmovns 0x0(,%r9,4),%edx\njmp 1295 \ncallq 1080 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov r10d, esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmovsxd r11, esi\nshl r11, 2\nlea rax, [r11+0Fh]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11C5:\ncmp rsp, rdx\njz short loc_11DC\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11C5\nloc_11DC:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11F2\nor [rsp+rax+10h+var_18], 0\nloc_11F2:\nmov rsi, rsp\ntest r10d, r10d\njle short loc_125F\nmov rax, rsi\nlea rdx, [rsi+r11]\nloc_1201:\nmov dword ptr [rax], 1\nadd rax, 4\ncmp rax, rdx\njnz short loc_1201\ncmp r10d, 1\njle short loc_1266\nmov edx, 4\nmov r9d, 1\njmp short loc_124F\nloc_1223:\nadd rax, 4\ncmp rdx, rax\njz short loc_1242\nloc_122C:\ncmp r8d, [rdi+rax]\njle short loc_1223\nmov ecx, [rsi+rax]\ncmp ecx, [rsi+rdx]\njl short loc_1223\nadd ecx, 1\nmov [rsi+rdx], ecx\njmp short loc_1223\nloc_1242:\nadd r9d, 1\nadd rdx, 4\ncmp r10d, r9d\njz short loc_1266\nloc_124F:\ntest r9d, r9d\njle short loc_1294\nmov r8d, [rdi+rdx]\nmov eax, 0\njmp short loc_122C\nloc_125F:\nmov edx, 0\njmp short loc_1281\nloc_1266:\nmov rax, rsi\nadd rsi, r11\nmov edx, 0\nloc_1271:\nmov ecx, [rax]\ncmp edx, ecx\ncmovl edx, ecx\nadd rax, 4\ncmp rax, rsi\njnz short loc_1271\nloc_1281:\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njnz short loc_129E\nmov eax, edx\nleave\nretn\nloc_1294:\nadd r9d, 1\nadd rdx, 4\njmp short loc_124F\nloc_129E:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // r11\n signed __int64 v3; // rax\n void *v4; // rsp\n _BYTE *v5; // rax\n __int64 v6; // rdx\n int i; // r9d\n __int64 v8; // rax\n int v9; // ecx\n int v10; // r8d\n unsigned int v11; // edx\n _BYTE *v12; // rax\n _BYTE v15[8]; // [rsp+8h] [rbp-10h] BYREF\n unsigned __int64 v16; // [rsp+10h] [rbp-8h]\n\n v16 = __readfsqword(0x28u);\n v2 = 4LL * a2;\n while ( v15 != &v15[-((v2 + 15) & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = ((_WORD)v2 + 15) & 0xFF0;\n v4 = alloca(v3);\n if ( (((_WORD)v2 + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v15[v3 - 8] = *(_QWORD *)&v15[v3 - 8];\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v5 = v15;\n do\n {\n *(_DWORD *)v5 = 1;\n v5 += 4;\n }\n while ( v5 != &v15[v2] );\n if ( a2 > 1 )\n {\n v6 = 4LL;\n for ( i = 1; i != a2; ++i )\n {\n while ( i <= 0 )\n {\n ++i;\n v6 += 4LL;\n }\n v10 = *(_DWORD *)(a1 + v6);\n v8 = 0LL;\n do\n {\n if ( v10 > *(_DWORD *)(a1 + v8) )\n {\n v9 = *(_DWORD *)&v15[v8];\n if ( v9 >= *(_DWORD *)&v15[v6] )\n *(_DWORD *)&v15[v6] = v9 + 1;\n }\n v8 += 4LL;\n }\n while ( v6 != v8 );\n v6 += 4LL;\n }\n }\n v12 = v15;\n v11 = 0;\n do\n {\n if ( (signed int)v11 < *(_DWORD *)v12 )\n v11 = *(_DWORD *)v12;\n v12 += 4;\n }\n while ( v12 != &v15[v2] );\n }\n return v11;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov r10d, esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmovsxd r11, esi\nshl r11, 2\nlea rax, [r11+0Fh]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11C5:\ncmp rsp, rdx\njz short loc_11DC\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11C5\nloc_11DC:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11F2\nor [rsp+rax+10h+var_18], 0\nloc_11F2:\nmov rsi, rsp\ntest r10d, r10d\njle short loc_125F\nmov rax, rsi\nlea rdx, [rsi+r11]\nloc_1201:\nmov dword ptr [rax], 1\nadd rax, 4\ncmp rax, rdx\njnz short loc_1201\ncmp r10d, 1\njle short loc_1266\nmov edx, 4\nmov r9d, 1\njmp short loc_124F\nloc_1223:\nadd rax, 4\ncmp rdx, rax\njz short loc_1242\nloc_122C:\ncmp r8d, [rdi+rax]\njle short loc_1223\nmov ecx, [rsi+rax]\ncmp ecx, [rsi+rdx]\njl short loc_1223\nadd ecx, 1\nmov [rsi+rdx], ecx\njmp short loc_1223\nloc_1242:\nadd r9d, 1\nadd rdx, 4\ncmp r10d, r9d\njz short loc_1266\nloc_124F:\ntest r9d, r9d\njle short loc_1294\nmov r8d, [rdi+rdx]\nmov eax, 0\njmp short loc_122C\nloc_125F:\nmov edx, 0\njmp short loc_1281\nloc_1266:\nmov rax, rsi\nadd rsi, r11\nmov edx, 0\nloc_1271:\nmov ecx, [rax]\ncmp edx, ecx\ncmovl edx, ecx\nadd rax, 4\ncmp rax, rsi\njnz short loc_1271\nloc_1281:\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njnz short loc_129E\nmov eax, edx\nleave\nretn\nloc_1294:\nadd r9d, 1\nadd rdx, 4\njmp short loc_124F\nloc_129E:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2)\n{\n __int64 v2; // r11\n signed __int64 v3; // rax\n void *v4; // rsp\n _BYTE *v5; // rax\n __int64 v6; // rdx\n int i; // r9d\n __int64 v8; // rax\n int v9; // ecx\n int v10; // r8d\n unsigned int v11; // edx\n _BYTE *v12; // rax\n _BYTE v15[8]; // [rsp+8h] [rbp-10h] BYREF\n unsigned __int64 v16; // [rsp+10h] [rbp-8h]\n\n v16 = __readfsqword(0x28u);\n v2 = 4LL * a2;\n while ( v15 != &v15[-((v2 + 15) & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = ((_WORD)v2 + 15) & 0xFF0;\n v4 = alloca(v3);\n if ( (((_WORD)v2 + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v15[v3 - 8] = *(_QWORD *)&v15[v3 - 8];\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v5 = v15;\n do\n {\n *(_DWORD *)v5 = 1;\n v5 += 4;\n }\n while ( v5 != &v15[v2] );\n if ( a2 > 1 )\n {\n v6 = 4LL;\n for ( i = 1; i != a2; ++i )\n {\n while ( i <= 0 )\n {\n ++i;\n v6 += 4LL;\n }\n v10 = *(_DWORD *)(a1 + v6);\n v8 = 0LL;\n do\n {\n if ( v10 > *(_DWORD *)(a1 + v8) )\n {\n v9 = *(_DWORD *)&v15[v8];\n if ( v9 >= *(_DWORD *)&v15[v6] )\n *(_DWORD *)&v15[v6] = v9 + 1;\n }\n v8 += 4LL;\n }\n while ( v6 != v8 );\n v6 += 4LL;\n }\n }\n v12 = v15;\n v11 = 0;\n do\n {\n if ( (signed int)v11 < *(_DWORD *)v12 )\n v11 = *(_DWORD *)v12;\n v12 += 4;\n }\n while ( v12 != &v15[v2] );\n }\n return v11;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2) {\n long long v2;\n signed long long v3;\n void *v4;\n uint8_t *v5;\n long long v6;\n int i;\n long long v8;\n int v9;\n int v10;\n unsigned int v11;\n uint8_t *v12;\n uint8_t v15[8];\n unsigned long long v16;\n v16 = __readfsqword(40u);\n v2 = 4LL * a2;\n while (v15 != &v15[-((v2 + 15) & 18446744073709547520LL)])\n ;\n v3 = ((unsigned short)v2 + 15) & 4080;\n v4 = alloca(v3);\n if ((((unsigned short)v2 + 15) & 4080) != 0)\n *(uint64_t *)&v15[v3 - 8] = *(uint64_t *)&v15[v3 - 8];\n if (a2 <= 0) {\n return 0;\n } else {\n v5 = v15;\n do {\n *(uint32_t *)v5 = 1;\n v5 += 4;\n } while (v5 != &v15[v2]);\n if (a2 > 1) {\n v6 = 4LL;\n for (i = 1; i != a2; ++i) {\n while (i <= 0) {\n ++i;\n v6 += 4LL;\n }\n v10 = *(uint32_t *)(a1 + v6);\n v8 = 0LL;\n do {\n if (v10 > *(uint32_t *)(a1 + v8)) {\n v9 = *(uint32_t *)&v15[v8];\n if (v9 >= *(uint32_t *)&v15[v6]) *(uint32_t *)&v15[v6] = v9 + 1;\n }\n v8 += 4LL;\n } while (v6 != v8);\n v6 += 4LL;\n }\n }\n v12 = v15;\n v11 = 0;\n do {\n if ((signed int)v11 < *(uint32_t *)v12) v11 = *(uint32_t *)v12;\n v12 += 4;\n } while (v12 != &v15[v2]);\n }\n return v11;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n signed long long v3;\n void *v4;\n uint8_t *v5;\n long long v6;\n int i;\n long long v8;\n int v9;\n int v10;\n unsigned int v11;\n uint8_t *v12;\n uint8_t v15[8];\n unsigned long long v16;\n v16 = __readfsqword(40u);\n v2 = 4LL * a2;\n while (v15 != &v15[-((v2 + 15) & 18446744073709547520LL)])\n ;\n v3 = ((unsigned short)v2 + 15) & 4080;\n v4 = alloca(v3);\n if ((((unsigned short)v2 + 15) & 4080) != 0)\n *(uint64_t *)&v15[v3 - 8] = *(uint64_t *)&v15[v3 - 8];\n if (a2 <= 0) {\n return 0;\n } else {\n v5 = v15;\n do {\n *(uint32_t *)v5 = 1;\n v5 += 4;\n } while (v5 != &v15[v2]);\n if (a2 > 1) {\n v6 = 4LL;\n for (i = 1; i != a2; ++i) {\n while (i <= 0) {\n ++i;\n v6 += 4LL;\n }\n v10 = *(uint32_t *)(a1 + v6);\n v8 = 0LL;\n do {\n if (v10 > *(uint32_t *)(a1 + v8)) {\n v9 = *(uint32_t *)&v15[v8];\n if (v9 >= *(uint32_t *)&v15[v6]) *(uint32_t *)&v15[v6] = v9 + 1;\n }\n v8 += 4LL;\n } while (v6 != v8);\n v6 += 4LL;\n }\n }\n v12 = v15;\n v11 = 0;\n do {\n if ((signed int)v11 < *(uint32_t *)v12) v11 = *(uint32_t *)v12;\n v12 += 4;\n } while (v12 != &v15[v2]);\n }\n return v11;\n}" + }, + { + "index": 548, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int longest_increasing_subsequence[n];\n for (int i = 0; i < n; i++) {\n longest_increasing_subsequence[i] = 1;\n }\n for (int i = 1; i < n; i++) {\n for (int j = 0; j < i; j++) {\n if (arr[i] > arr[j] && longest_increasing_subsequence[i] <\n longest_increasing_subsequence[j] + 1) {\n longest_increasing_subsequence[i] =\n longest_increasing_subsequence[j] + 1;\n }\n }\n }\n int maximum = 0;\n for (int i = 0; i < n; i++) {\n if (longest_increasing_subsequence[i] > maximum) {\n maximum = longest_increasing_subsequence[i];\n }\n }\n return maximum;\n}", + "test": "int main() {\n\n int arr1[] = {10, 22, 9, 33, 21, 50, 41, 60};\n\n int n1 = sizeof(arr1)/sizeof(arr1[0]);\n\n assert(func0(arr1, n1) == 5);\n\n\n\n int arr2[] = {3, 10, 2, 1, 20};\n\n int n2 = sizeof(arr2)/sizeof(arr2[0]);\n\n assert(func0(arr2, n2) == 3);\n\n\n\n int arr3[] = {50, 3, 10, 7, 40, 80};\n\n int n3 = sizeof(arr3)/sizeof(arr3[0]);\n\n assert(func0(arr3, n3) == 4);\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovslq %esi,%rax\nmov %rsp,%rcx\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rcx\nand $0xfffffffffffffff0,%rdx\nmov %rcx,%rax\ncmp %rax,%rsp\nje 1356 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 1341 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 1417 \nlea 0x3(%rsp),%r8\nmov %r8,%rcx\nand $0xfffffffffffffffc,%r8\nshr $0x2,%rcx\ntest %esi,%esi\njle 1422 \nlea -0x1(%rsi),%edx\nmov %r8,%rax\nlea 0x4(%r8,%rdx,4),%rdx\nnopl 0x0(%rax,%rax,1)\nmovl $0x1,(%rax)\nadd $0x4,%rax\ncmp %rdx,%rax\njne 1390 \ncmp $0x1,%esi\njle 1422 \nlea -0x2(%rsi),%r10d\nmov $0x1,%edx\nadd $0x2,%r10\nnopl 0x0(%rax)\nmov (%rdi,%rdx,4),%r9d\nxor %eax,%eax\nxchg %ax,%ax\ncmp (%rdi,%rax,4),%r9d\njle 13d7 \nmov (%r8,%rax,4),%ecx\ncmp (%r8,%rdx,4),%ecx\njl 13d7 \nadd $0x1,%ecx\nmov %ecx,(%r8,%rdx,4)\nadd $0x1,%rax\ncmp %rax,%rdx\njne 13c0 \nadd $0x1,%rdx\ncmp %rdx,%r10\njne 13b8 \nxor %eax,%eax\nxor %r9d,%r9d\nxchg %ax,%ax\nmov (%r8,%rax,4),%edx\ncmp %edx,%r9d\ncmovl %edx,%r9d\nadd $0x1,%rax\ncmp %eax,%esi\njg 13f0 \nmov -0x8(%rbp),%rax\nxor %fs:0x28,%rax\njne 1445 \nleaveq\nmov %r9d,%eax\nretq\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 1368 \ncmp $0x1,%esi\nje 142c \nxor %r9d,%r9d\njmp 1403 \ncmpl $0x0,0x0(,%rcx,4)\nmov $0x0,%r9d\ncmovns 0x0(,%rcx,4),%r9d\njmp 1403 \ncallq 1080 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmovsxd rdx, esi\nmov r8, rdi\nshl rdx, 2\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [rdx+0Fh]\nmov rdi, rsp\nmov rcx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rdi, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rdi\njz short loc_1316\nloc_1301:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rdi\njnz short loc_1301\nloc_1316:\nand ecx, 0FFFh\nsub rsp, rcx\ntest rcx, rcx\njnz loc_1403\nloc_1328:\nmov rdi, rsp\ntest esi, esi\njle loc_140E\nlea r11, [rdi+rdx]\nand edx, 4\nmov r9, rdi\nmov rax, rdi\njz short loc_1358\nlea rax, [rdi+4]\nmov dword ptr [rdi], 1\ncmp rax, r11\njz short loc_136E\nnop dword ptr [rax+00000000h]\nloc_1358:\nmov dword ptr [rax], 1\nadd rax, 8\nmov dword ptr [rax-4], 1\ncmp rax, r11\njnz short loc_1358\nloc_136E:\ncmp esi, 1\njz short loc_13B6\nmov esi, esi\nmov edx, 4\nlea r10, ds:0[rsi*4]\nnop word ptr [rax+rax+00h]\nloc_1388:\nmov esi, [r8+rdx]\nxor eax, eax\nxchg ax, ax\nloc_1390:\ncmp esi, [r8+rax]\njle short loc_13A4\nmov ecx, [rdi+rax]\ncmp ecx, [rdi+rdx]\njl short loc_13A4\nadd ecx, 1\nmov [rdi+rdx], ecx\nloc_13A4:\nadd rax, 4\ncmp rdx, rax\njnz short loc_1390\nadd rdx, 4\ncmp rdx, r10\njnz short loc_1388\nloc_13B6:\nmov rdx, r11\nxor eax, eax\nsub rdx, rdi\nand edx, 4\njz short loc_13D8\nmov edx, [rdi]\nlea r9, [rdi+4]\ncmp eax, edx\ncmovl eax, edx\ncmp r9, r11\njz short loc_13F2\nnop dword ptr [rax+rax+00h]\nloc_13D8:\nmov edx, [r9]\ncmp eax, edx\ncmovl eax, edx\nmov edx, [r9+4]\ncmp eax, edx\ncmovl eax, edx\nadd r9, 8\ncmp r9, r11\njnz short loc_13D8\nloc_13F2:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_1412\nleave\nretn\nloc_1403:\nor [rsp+rcx+1010h+var_1018], 0\njmp loc_1328\nloc_140E:\nxor eax, eax\njmp short loc_13F2\nloc_1412:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v3; // rdx\n int *v4; // rdi\n signed __int64 v5; // rcx\n void *v6; // rsp\n int *v7; // r11\n int *v8; // r9\n int *v9; // rax\n __int64 v10; // rdx\n __int64 v11; // r10\n int v12; // esi\n __int64 v13; // rax\n int v14; // ecx\n __int64 result; // rax\n int v16; // edx\n __int64 v17; // [rsp+0h] [rbp-1018h]\n int v18; // [rsp+8h] [rbp-1010h] BYREF\n _BYTE v19[4084]; // [rsp+Ch] [rbp-100Ch] BYREF\n _QWORD v20[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v3 = 4LL * a2;\n v20[1] = __readfsqword(0x28u);\n v4 = (int *)((char *)v20 - ((v3 + 15) & 0xFFFFFFFFFFFFF000LL));\n if ( v20 != (_QWORD *)v4 )\n {\n while ( &v18 != v4 )\n ;\n }\n v5 = ((_WORD)v3 + 15) & 0xFF0;\n v6 = alloca(v5);\n if ( (((_WORD)v3 + 15) & 0xFF0) != 0 )\n *(__int64 *)((char *)&v17 + v5) = *(__int64 *)((char *)&v17 + v5);\n if ( a2 <= 0 )\n return 0LL;\n v7 = (int *)&v19[v3 - 4];\n v8 = &v18;\n v9 = &v18;\n if ( (v3 & 4) == 0 || (v9 = (int *)v19, v18 = 1, v19 != (_BYTE *)v7) )\n {\n do\n {\n *v9 = 1;\n v9 += 2;\n *(v9 - 1) = 1;\n }\n while ( v9 != v7 );\n }\n if ( a2 != 1 )\n {\n v10 = 4LL;\n v11 = 4LL * (unsigned int)a2;\n do\n {\n v12 = *(_DWORD *)(a1 + v10);\n v13 = 0LL;\n do\n {\n if ( v12 > *(_DWORD *)(a1 + v13) )\n {\n v14 = *(_DWORD *)&v19[v13 - 4];\n if ( v14 >= *(_DWORD *)&v19[v10 - 4] )\n *(_DWORD *)&v19[v10 - 4] = v14 + 1;\n }\n v13 += 4LL;\n }\n while ( v10 != v13 );\n v10 += 4LL;\n }\n while ( v10 != v11 );\n }\n result = 0LL;\n if ( (((_BYTE)v7 - (unsigned __int8)&v18) & 4) == 0 )\n goto LABEL_30;\n v8 = (int *)v19;\n if ( v18 > 0 )\n result = (unsigned int)v18;\n if ( v19 != (_BYTE *)v7 )\n {\nLABEL_30:\n do\n {\n if ( (int)result < *v8 )\n result = (unsigned int)*v8;\n v16 = v8[1];\n if ( (int)result < v16 )\n result = (unsigned int)v16;\n v8 += 2;\n }\n while ( v8 != v7 );\n }\n return result;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\npush rbp\nmovsxd rdx, esi\nmov r8, rdi\nshl rdx, 2\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [rdx+0Fh]\nmov rdi, rsp\nmov rcx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rdi, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rdi\njz short loc_1316\nloc_1301:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rdi\njnz short loc_1301\nloc_1316:\nand ecx, 0FFFh\nsub rsp, rcx\ntest rcx, rcx\njnz loc_1403\nloc_1328:\nmov rdi, rsp\ntest esi, esi\njle loc_140E\nlea r11, [rdi+rdx]\nand edx, 4\nmov r9, rdi\nmov rax, rdi\njz short loc_1358\nlea rax, [rdi+4]\nmov dword ptr [rdi], 1\ncmp rax, r11\njz short loc_136E\nnop dword ptr [rax+00000000h]\nloc_1358:\nmov dword ptr [rax], 1\nadd rax, 8\nmov dword ptr [rax-4], 1\ncmp rax, r11\njnz short loc_1358\nloc_136E:\ncmp esi, 1\njz short loc_13B6\nmov esi, esi\nmov edx, 4\nlea r10, ds:0[rsi*4]\nnop word ptr [rax+rax+00h]\nloc_1388:\nmov esi, [r8+rdx]\nxor eax, eax\nxchg ax, ax\nloc_1390:\ncmp esi, [r8+rax]\njle short loc_13A4\nmov ecx, [rdi+rax]\ncmp ecx, [rdi+rdx]\njl short loc_13A4\nadd ecx, 1\nmov [rdi+rdx], ecx\nloc_13A4:\nadd rax, 4\ncmp rdx, rax\njnz short loc_1390\nadd rdx, 4\ncmp rdx, r10\njnz short loc_1388\nloc_13B6:\nmov rdx, r11\nxor eax, eax\nsub rdx, rdi\nand edx, 4\njz short loc_13D8\nmov edx, [rdi]\nlea r9, [rdi+4]\ncmp eax, edx\ncmovl eax, edx\ncmp r9, r11\njz short loc_13F2\nnop dword ptr [rax+rax+00h]\nloc_13D8:\nmov edx, [r9]\ncmp eax, edx\ncmovl eax, edx\nmov edx, [r9+4]\ncmp eax, edx\ncmovl eax, edx\nadd r9, 8\ncmp r9, r11\njnz short loc_13D8\nloc_13F2:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_1412\nleave\nretn\nloc_1403:\nor [rsp+rcx+1010h+var_1018], 0\njmp loc_1328\nloc_140E:\nxor eax, eax\njmp short loc_13F2\nloc_1412:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12C0(__int64 a1, int a2)\n{\n __int64 v3; // rdx\n int *v4; // rdi\n signed __int64 v5; // rcx\n void *v6; // rsp\n int *v7; // r11\n int *v8; // r9\n int *v9; // rax\n __int64 v10; // rdx\n __int64 v11; // r10\n int v12; // esi\n __int64 v13; // rax\n int v14; // ecx\n __int64 result; // rax\n int v16; // edx\n __int64 v17; // [rsp+0h] [rbp-1018h]\n int v18; // [rsp+8h] [rbp-1010h] BYREF\n _BYTE v19[4084]; // [rsp+Ch] [rbp-100Ch] BYREF\n _QWORD v20[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v3 = 4LL * a2;\n v20[1] = __readfsqword(0x28u);\n v4 = (int *)((char *)v20 - ((v3 + 15) & 0xFFFFFFFFFFFFF000LL));\n if ( v20 != (_QWORD *)v4 )\n {\n while ( &v18 != v4 )\n ;\n }\n v5 = ((_WORD)v3 + 15) & 0xFF0;\n v6 = alloca(v5);\n if ( (((_WORD)v3 + 15) & 0xFF0) != 0 )\n *(__int64 *)((char *)&v17 + v5) = *(__int64 *)((char *)&v17 + v5);\n if ( a2 <= 0 )\n return 0LL;\n v7 = (int *)&v19[v3 - 4];\n v8 = &v18;\n v9 = &v18;\n if ( (v3 & 4) == 0 || (v9 = (int *)v19, v18 = 1, v19 != (_BYTE *)v7) )\n {\n do\n {\n *v9 = 1;\n v9 += 2;\n *(v9 - 1) = 1;\n }\n while ( v9 != v7 );\n }\n if ( a2 != 1 )\n {\n v10 = 4LL;\n v11 = 4LL * (unsigned int)a2;\n do\n {\n v12 = *(_DWORD *)(a1 + v10);\n v13 = 0LL;\n do\n {\n if ( v12 > *(_DWORD *)(a1 + v13) )\n {\n v14 = *(_DWORD *)&v19[v13 - 4];\n if ( v14 >= *(_DWORD *)&v19[v10 - 4] )\n *(_DWORD *)&v19[v10 - 4] = v14 + 1;\n }\n v13 += 4LL;\n }\n while ( v10 != v13 );\n v10 += 4LL;\n }\n while ( v10 != v11 );\n }\n result = 0LL;\n if ( (((_BYTE)v7 - (unsigned __int8)&v18) & 4) == 0 )\n goto LABEL_30;\n v8 = (int *)v19;\n if ( v18 > 0 )\n result = (unsigned int)v18;\n if ( v19 != (_BYTE *)v7 )\n {\nLABEL_30:\n do\n {\n if ( (int)result < *v8 )\n result = (unsigned int)*v8;\n v16 = v8[1];\n if ( (int)result < v16 )\n result = (unsigned int)v16;\n v8 += 2;\n }\n while ( v8 != v7 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12C0(long long a1, int a2) {\n long long v3;\n int *v4;\n signed long long v5;\n void *v6;\n int *v7;\n int *v8;\n int *v9;\n long long v10;\n long long v11;\n int v12;\n long long v13;\n int v14;\n long long result;\n int v16;\n long long v17;\n int v18;\n uint8_t v19[4084];\n uint64_t v20[2];\n v3 = 4LL * a2;\n v20[1] = __readfsqword(40u);\n v4 = (int *)((char *)v20 - ((v3 + 15) & 18446744073709547520LL));\n if (v20 != (uint64_t *)v4) {\n while (&v18 != v4)\n ;\n }\n v5 = ((unsigned short)v3 + 15) & 4080;\n v6 = alloca(v5);\n if ((((unsigned short)v3 + 15) & 4080) != 0)\n *(long long *)((char *)&v17 + v5) = *(long long *)((char *)&v17 + v5);\n if (a2 <= 0) return 0LL;\n v7 = (int *)&v19[v3 - 4];\n v8 = &v18;\n v9 = &v18;\n if ((v3 & 4) == 0 || (v9 = (int *)v19, v18 = 1, v19 != (uint8_t *)v7)) {\n do {\n *v9 = 1;\n v9 += 2;\n *(v9 - 1) = 1;\n } while (v9 != v7);\n }\n if (a2 != 1) {\n v10 = 4LL;\n v11 = 4LL * (unsigned int)a2;\n do {\n v12 = *(uint32_t *)(a1 + v10);\n v13 = 0LL;\n do {\n if (v12 > *(uint32_t *)(a1 + v13)) {\n v14 = *(uint32_t *)&v19[v13 - 4];\n if (v14 >= *(uint32_t *)&v19[v10 - 4])\n *(uint32_t *)&v19[v10 - 4] = v14 + 1;\n }\n v13 += 4LL;\n } while (v10 != v13);\n v10 += 4LL;\n } while (v10 != v11);\n }\n result = 0LL;\n if ((((uint8_t)v7 - (unsigned char)&v18) & 4) == 0) goto LABEL_30;\n v8 = (int *)v19;\n if (v18 > 0) result = (unsigned int)v18;\n if (v19 != (uint8_t *)v7) {\n LABEL_30:\n do {\n if ((int)result < *v8) result = (unsigned int)*v8;\n v16 = v8[1];\n if ((int)result < v16) result = (unsigned int)v16;\n v8 += 2;\n } while (v8 != v7);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v3;\n int *v4;\n signed long long v5;\n void *v6;\n int *v7;\n int *v8;\n int *v9;\n long long v10;\n long long v11;\n int v12;\n long long v13;\n int v14;\n long long result;\n int v16;\n long long v17;\n int v18;\n uint8_t v19[4084];\n uint64_t v20[2];\n v3 = 4LL * a2;\n v20[1] = __readfsqword(40u);\n v4 = (int *)((char *)v20 - ((v3 + 15) & 18446744073709547520LL));\n if (v20 != (uint64_t *)v4) {\n while (&v18 != v4)\n ;\n }\n v5 = ((unsigned short)v3 + 15) & 4080;\n v6 = alloca(v5);\n if ((((unsigned short)v3 + 15) & 4080) != 0)\n *(long long *)((char *)&v17 + v5) = *(long long *)((char *)&v17 + v5);\n if (a2 <= 0) return 0LL;\n v7 = (int *)&v19[v3 - 4];\n v8 = &v18;\n v9 = &v18;\n if ((v3 & 4) == 0 || (v9 = (int *)v19, v18 = 1, v19 != (uint8_t *)v7)) {\n do {\n *v9 = 1;\n v9 += 2;\n *(v9 - 1) = 1;\n } while (v9 != v7);\n }\n if (a2 != 1) {\n v10 = 4LL;\n v11 = 4LL * (unsigned int)a2;\n do {\n v12 = *(uint32_t *)(a1 + v10);\n v13 = 0LL;\n do {\n if (v12 > *(uint32_t *)(a1 + v13)) {\n v14 = *(uint32_t *)&v19[v13 - 4];\n if (v14 >= *(uint32_t *)&v19[v10 - 4])\n *(uint32_t *)&v19[v10 - 4] = v14 + 1;\n }\n v13 += 4LL;\n } while (v10 != v13);\n v10 += 4LL;\n } while (v10 != v11);\n }\n result = 0LL;\n if ((((uint8_t)v7 - (unsigned char)&v18) & 4) == 0) goto LABEL_30;\n v8 = (int *)v19;\n if (v18 > 0) result = (unsigned int)v18;\n if (v19 != (uint8_t *)v7) {\n LABEL_30:\n do {\n if ((int)result < *v8) result = (unsigned int)*v8;\n v16 = v8[1];\n if ((int)result < v16) result = (unsigned int)v16;\n v8 += 2;\n } while (v8 != v7);\n }\n return result;\n}" + }, + { + "index": 548, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int longest_increasing_subsequence[n];\n for (int i = 0; i < n; i++) {\n longest_increasing_subsequence[i] = 1;\n }\n for (int i = 1; i < n; i++) {\n for (int j = 0; j < i; j++) {\n if (arr[i] > arr[j] && longest_increasing_subsequence[i] <\n longest_increasing_subsequence[j] + 1) {\n longest_increasing_subsequence[i] =\n longest_increasing_subsequence[j] + 1;\n }\n }\n }\n int maximum = 0;\n for (int i = 0; i < n; i++) {\n if (longest_increasing_subsequence[i] > maximum) {\n maximum = longest_increasing_subsequence[i];\n }\n }\n return maximum;\n}", + "test": "int main() {\n\n int arr1[] = {10, 22, 9, 33, 21, 50, 41, 60};\n\n int n1 = sizeof(arr1)/sizeof(arr1[0]);\n\n assert(func0(arr1, n1) == 5);\n\n\n\n int arr2[] = {3, 10, 2, 1, 20};\n\n int n2 = sizeof(arr2)/sizeof(arr2[0]);\n\n assert(func0(arr2, n2) == 3);\n\n\n\n int arr3[] = {50, 3, 10, 7, 40, 80};\n\n int n3 = sizeof(arr3)/sizeof(arr3[0]);\n\n assert(func0(arr3, n3) == 4);\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovslq %esi,%rax\nmov %rsp,%rcx\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rcx\nand $0xfffffffffffffff0,%rdx\nmov %rcx,%rax\ncmp %rax,%rsp\nje 1316 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 1301 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 14d0 \nlea 0x3(%rsp),%r8\nmov %r8,%r11\nand $0xfffffffffffffffc,%r8\nshr $0x2,%r11\ntest %esi,%esi\njle 14db \nlea -0x1(%rsi),%eax\ncmp $0x2,%eax\njbe 14e4 \nmov %esi,%edx\nmovdqa 0xd4a(%rip),%xmm0\nmov %r8,%rax\nshr $0x2,%edx\nshl $0x4,%rdx\nadd %r8,%rdx\nnopl 0x0(%rax,%rax,1)\nmovups %xmm0,(%rax)\nadd $0x10,%rax\ncmp %rdx,%rax\njne 1368 \nmov %esi,%eax\nand $0xfffffffc,%eax\ntest $0x3,%sil\nje 13ad \nmovslq %eax,%rdx\nmovl $0x1,(%r8,%rdx,4)\nlea 0x1(%rax),%edx\ncmp %edx,%esi\njle 13ad \nmovslq %edx,%rdx\nadd $0x2,%eax\nmovl $0x1,(%r8,%rdx,4)\ncmp %eax,%esi\njle 13ad \ncltq\nmovl $0x1,(%r8,%rax,4)\ncmp $0x1,%esi\njle 14db \nlea -0x2(%rsi),%r10d\nmov $0x1,%edx\nadd $0x2,%r10\nnopl 0x0(%rax,%rax,1)\nmov (%rdi,%rdx,4),%r9d\nxor %eax,%eax\nxchg %ax,%ax\ncmp (%rdi,%rax,4),%r9d\njle 13e7 \nmov (%r8,%rax,4),%ecx\ncmp (%r8,%rdx,4),%ecx\njl 13e7 \nadd $0x1,%ecx\nmov %ecx,(%r8,%rdx,4)\nadd $0x1,%rax\ncmp %rdx,%rax\njne 13d0 \nlea 0x1(%rax),%rdx\ncmp %r10,%rdx\njne 13c8 \ntest %esi,%esi\nmov $0x1,%ecx\ncmovg %esi,%ecx\ncmp $0x3,%esi\njle 14eb \nmov %ecx,%edx\npxor %xmm2,%xmm2\nmov %r8,%rax\nshr $0x2,%edx\nshl $0x4,%rdx\nadd %r8,%rdx\nmovdqu (%rax),%xmm0\nadd $0x10,%rax\nmovdqa %xmm0,%xmm1\npcmpgtd %xmm2,%xmm1\npand %xmm1,%xmm0\npandn %xmm2,%xmm1\nmovdqa %xmm1,%xmm2\npor %xmm0,%xmm2\ncmp %rdx,%rax\njne 1420 \nmovdqa %xmm2,%xmm1\nmov %ecx,%edx\npsrldq $0x8,%xmm1\nand $0xfffffffc,%edx\nand $0x3,%ecx\nmovdqa %xmm1,%xmm0\npcmpgtd %xmm2,%xmm0\npand %xmm0,%xmm1\npandn %xmm2,%xmm0\npor %xmm0,%xmm1\nmovdqa %xmm1,%xmm2\npsrldq $0x4,%xmm2\nmovdqa %xmm2,%xmm0\npcmpgtd %xmm1,%xmm0\npand %xmm0,%xmm2\npandn %xmm1,%xmm0\npor %xmm2,%xmm0\nmovd %xmm0,%eax\nje 14bf \nmovslq %edx,%rcx\nmov (%r8,%rcx,4),%ecx\ncmp %ecx,%eax\ncmovl %ecx,%eax\nadd $0x1,%edx\ncmp %edx,%esi\njle 14bf \nmovslq %edx,%rcx\nmov (%r8,%rcx,4),%ecx\ncmp %ecx,%eax\ncmovl %ecx,%eax\nadd $0x1,%edx\ncmp %edx,%esi\njle 14bf \nmovslq %edx,%rdx\nmov (%r8,%rdx,4),%edx\ncmp %edx,%eax\ncmovl %edx,%eax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\njne 1523 \nleaveq\nretq\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 1328 \ncmp $0x1,%esi\nje 150a \nxor %eax,%eax\njmp 14bf \nxor %eax,%eax\njmpq 137f \nmov 0x0(,%r11,4),%eax\nmov $0x1,%edx\ntest %eax,%eax\nmov $0x0,%eax\ncmovns 0x0(,%r11,4),%eax\njmp 14a0 \ncmpl $0x0,0x0(,%r11,4)\nmov $0x0,%eax\ncmovns 0x0(,%r11,4),%eax\njmp 14bf \ncallq 1080 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov r9d, esi\nmov rbp, rsp\npush r12\npush rbx\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmovsxd rax, esi\nmov rcx, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_1319\nloc_1304:\nsub rsp, 1000h\nor [rsp+1020h+var_28], 0\ncmp rsp, rcx\njnz short loc_1304\nloc_1319:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_14E0\nloc_132B:\nlea rsi, [rsp+1020h+var_101D]\nmov r12, rsi\nand rsi, 0FFFFFFFFFFFFFFFCh\nshr r12, 2\nmov r11, rsi\ntest r9d, r9d\njle loc_14EB\nlea ebx, [r9-1]\ncmp ebx, 2\njbe loc_14EF\nmov edx, r9d\nmovdqa xmm0, cs:xmmword_2090\nmov rax, rsi\nshr edx, 2\nshl rdx, 4\nlea rcx, [rsi+rdx]\nand edx, 10h\njz short loc_1380\nlea rax, [rsi+10h]\nmovups xmmword ptr [rsi], xmm0\ncmp rax, rcx\njz short loc_1390\nxchg ax, ax\nloc_1380:\nmovups xmmword ptr [rax], xmm0\nadd rax, 20h ; ' '\nmovups xmmword ptr [rax-10h], xmm0\ncmp rax, rcx\njnz short loc_1380\nloc_1390:\nmov eax, r9d\nand eax, 0FFFFFFFCh\ntest r9b, 3\njz short loc_13C6\nmov edx, eax\nlea ecx, [rax+1]\nlea rdx, [rsi+rdx*4]\nmov dword ptr [rdx], 1\ncmp r9d, ecx\njle short loc_13C6\nloc_13B0:\nadd eax, 2\nmov dword ptr [rdx+4], 1\ncmp r9d, eax\njle short loc_13C6\nmov dword ptr [rdx+8], 1\nloc_13C6:\nmov r10d, r9d\nmov edx, 4\nshl r10, 2\nnop word ptr [rax+rax+00h]\nloc_13D8:\nmov r8d, [rdi+rdx]\nxor eax, eax\nxchg ax, ax\nloc_13E0:\ncmp r8d, [rdi+rax]\njle short loc_13F4\nmov ecx, [rsi+rax]\ncmp ecx, [rsi+rdx]\njl short loc_13F4\nadd ecx, 1\nmov [rsi+rdx], ecx\nloc_13F4:\nadd rax, 4\ncmp rax, rdx\njnz short loc_13E0\nlea rdx, [rax+4]\ncmp rdx, r10\njnz short loc_13D8\ncmp ebx, 2\njbe loc_1511\nmov edx, r9d\nmov rax, rsi\npxor xmm2, xmm2\nshr edx, 2\nshl rdx, 4\nadd rdx, rsi\nnop dword ptr [rax+rax+00h]\nloc_1428:\nmovdqu xmm0, xmmword ptr [rax]\nadd rax, 10h\nmovdqa xmm1, xmm0\npcmpgtd xmm1, xmm2\npand xmm0, xmm1\npandn xmm1, xmm2\nmovdqa xmm2, xmm1\npor xmm2, xmm0\ncmp rdx, rax\njnz short loc_1428\nmovdqa xmm0, xmm2\nmov edx, r9d\npsrldq xmm0, 8\nand edx, 0FFFFFFFCh\nmovdqa xmm1, xmm0\npcmpgtd xmm1, xmm2\npand xmm0, xmm1\npandn xmm1, xmm2\npor xmm1, xmm0\nmovdqa xmm2, xmm1\npsrldq xmm2, 4\nmovdqa xmm0, xmm2\npcmpgtd xmm0, xmm1\npand xmm2, xmm0\npandn xmm0, xmm1\npor xmm0, xmm2\nmovd eax, xmm0\ntest r9b, 3\njz short loc_14C8\nmovsxd rcx, edx\nlea r11, [rsi+rcx*4]\nmov ecx, [r11]\ncmp eax, ecx\ncmovl eax, ecx\nlea ecx, [rdx+1]\ncmp ecx, r9d\njge short loc_14C8\nloc_14AE:\nmov ecx, [r11+4]\ncmp eax, ecx\ncmovl eax, ecx\nadd edx, 2\ncmp r9d, edx\njle short loc_14C8\nmov edx, [r11+8]\ncmp eax, edx\ncmovl eax, edx\nloc_14C8:\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njnz short loc_1522\nlea rsp, [rbp-10h]\npop rbx\npop r12\npop rbp\nretn\nloc_14E0:\nor [rsp+rdx+1020h+var_1028], 0\njmp loc_132B\nloc_14EB:\nxor eax, eax\njmp short loc_14C8\nloc_14EF:\nmov ds:dword_0[r12*4], 1\nmov rdx, rsi\nxor eax, eax\ncmp r9d, 1\njnz loc_13B0\nmov eax, 1\njmp short loc_14C8\nloc_1511:\nmov eax, ds:dword_0[r12*4]\nxor edx, edx\ntest eax, eax\ncmovs eax, edx\njmp short loc_14AE\nloc_1522:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // rdx\n __m128i *v3; // rcx\n __int16 v4; // dx\n signed __int64 v5; // rdx\n void *v6; // rsp\n int *v7; // r11\n __m128i si128; // xmm0\n __m128i *v9; // rax\n __int64 v10; // rdx\n __m128i *v11; // rcx\n int v12; // eax\n __m128i *v13; // rdx\n __int64 v14; // rdx\n int v15; // r8d\n unsigned __int64 v16; // rax\n __int32 v17; // ecx\n const __m128i *v18; // rax\n __m128i v19; // xmm2\n __m128i v20; // xmm0\n __m128i v21; // xmm1\n __m128i v22; // xmm0\n unsigned int v23; // edx\n __m128i v24; // xmm1\n __m128i v25; // xmm1\n __m128i v26; // xmm2\n __m128i v27; // xmm0\n __int64 result; // rax\n int v29; // ecx\n int v30; // edx\n __int64 v31; // [rsp+0h] [rbp-1028h]\n __m128i v32; // [rsp+8h] [rbp-1020h] BYREF\n _BYTE v33[4072]; // [rsp+18h] [rbp-1010h] BYREF\n _QWORD v34[4]; // [rsp+1008h] [rbp-20h] BYREF\n\n v34[1] = __readfsqword(0x28u);\n v2 = 4LL * a2 + 15;\n v3 = (__m128i *)((char *)v34 - (v2 & 0xFFFFFFFFFFFFF000LL));\n v4 = v2 & 0xFFF0;\n if ( v34 != (_QWORD *)v3 )\n {\n while ( &v32 != v3 )\n ;\n }\n v5 = v4 & 0xFFF;\n v6 = alloca(v5);\n if ( v5 )\n *(__int64 *)((char *)&v31 + v5) = *(__int64 *)((char *)&v31 + v5);\n v7 = (int *)&v32;\n if ( a2 <= 0 )\n return 0LL;\n if ( (unsigned int)(a2 - 1) <= 2 )\n {\n v32.m128i_i32[0] = 1;\n v13 = &v32;\n v12 = 0;\n if ( a2 == 1 )\n return 1LL;\n goto LABEL_12;\n }\n si128 = _mm_load_si128((const __m128i *)&xmmword_2090);\n v9 = &v32;\n v10 = 16LL * ((unsigned int)a2 >> 2);\n v11 = (__m128i *)((char *)&v32 + v10);\n if ( (v10 & 0x10) == 0 || (v9 = (__m128i *)v33, v32 = si128, v33 != (_BYTE *)v11) )\n {\n do\n {\n *v9 = si128;\n v9 += 2;\n v9[-1] = si128;\n }\n while ( v9 != v11 );\n }\n v12 = a2 & 0x7FFFFFFC;\n if ( (a2 & 3) != 0 )\n {\n v13 = (__m128i *)((char *)&v32 + 4 * (unsigned int)v12);\n v13->m128i_i32[0] = 1;\n if ( a2 > v12 + 1 )\n {\nLABEL_12:\n v13->m128i_i32[1] = 1;\n if ( a2 > v12 + 2 )\n v13->m128i_i32[2] = 1;\n }\n }\n v14 = 4LL;\n do\n {\n v15 = *(_DWORD *)(a1 + v14);\n v16 = 0LL;\n do\n {\n if ( v15 > *(_DWORD *)(a1 + v16) )\n {\n v17 = v32.m128i_i32[v16 / 4];\n if ( v17 >= *(__int32 *)((char *)v32.m128i_i32 + v14) )\n *(__int32 *)((char *)v32.m128i_i32 + v14) = v17 + 1;\n }\n v16 += 4LL;\n }\n while ( v16 != v14 );\n v14 = v16 + 4;\n }\n while ( v16 + 4 != 4LL * (unsigned int)a2 );\n if ( (unsigned int)(a2 - 1) <= 2 )\n {\n result = v32.m128i_u32[0];\n v23 = 0;\n if ( v32.m128i_i32[0] < 0 )\n result = 0LL;\n goto LABEL_28;\n }\n v18 = &v32;\n v19 = 0LL;\n do\n {\n v20 = _mm_loadu_si128(v18++);\n v21 = _mm_cmpgt_epi32(v20, v19);\n v19 = _mm_or_si128(_mm_andnot_si128(v21, v19), _mm_and_si128(v20, v21));\n }\n while ( &v32 + ((unsigned int)a2 >> 2) != v18 );\n v22 = _mm_srli_si128(v19, 8);\n v23 = a2 & 0xFFFFFFFC;\n v24 = _mm_cmpgt_epi32(v22, v19);\n v25 = _mm_or_si128(_mm_andnot_si128(v24, v19), _mm_and_si128(v22, v24));\n v26 = _mm_srli_si128(v25, 4);\n v27 = _mm_cmpgt_epi32(v26, v25);\n result = (unsigned int)_mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v27, v25), _mm_and_si128(v26, v27)));\n if ( (a2 & 3) != 0 )\n {\n v7 = &v32.m128i_i32[v23];\n if ( (int)result < *v7 )\n result = (unsigned int)*v7;\n if ( (int)(v23 + 1) < a2 )\n {\nLABEL_28:\n v29 = v7[1];\n if ( (int)result < v29 )\n result = (unsigned int)v29;\n if ( a2 > (int)(v23 + 2) )\n {\n v30 = v7[2];\n if ( (int)result < v30 )\n return (unsigned int)v30;\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\npush rbp\nmov r9d, esi\nmov rbp, rsp\npush r12\npush rbx\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmovsxd rax, esi\nmov rcx, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_1319\nloc_1304:\nsub rsp, 1000h\nor [rsp+1020h+var_28], 0\ncmp rsp, rcx\njnz short loc_1304\nloc_1319:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_14E0\nloc_132B:\nlea rsi, [rsp+1020h+var_101D]\nmov r12, rsi\nand rsi, 0FFFFFFFFFFFFFFFCh\nshr r12, 2\nmov r11, rsi\ntest r9d, r9d\njle loc_14EB\nlea ebx, [r9-1]\ncmp ebx, 2\njbe loc_14EF\nmov edx, r9d\nmovdqa xmm0, cs:xmmword_2090\nmov rax, rsi\nshr edx, 2\nshl rdx, 4\nlea rcx, [rsi+rdx]\nand edx, 10h\njz short loc_1380\nlea rax, [rsi+10h]\nmovups xmmword ptr [rsi], xmm0\ncmp rax, rcx\njz short loc_1390\nxchg ax, ax\nloc_1380:\nmovups xmmword ptr [rax], xmm0\nadd rax, 20h ; ' '\nmovups xmmword ptr [rax-10h], xmm0\ncmp rax, rcx\njnz short loc_1380\nloc_1390:\nmov eax, r9d\nand eax, 0FFFFFFFCh\ntest r9b, 3\njz short loc_13C6\nmov edx, eax\nlea ecx, [rax+1]\nlea rdx, [rsi+rdx*4]\nmov dword ptr [rdx], 1\ncmp r9d, ecx\njle short loc_13C6\nloc_13B0:\nadd eax, 2\nmov dword ptr [rdx+4], 1\ncmp r9d, eax\njle short loc_13C6\nmov dword ptr [rdx+8], 1\nloc_13C6:\nmov r10d, r9d\nmov edx, 4\nshl r10, 2\nnop word ptr [rax+rax+00h]\nloc_13D8:\nmov r8d, [rdi+rdx]\nxor eax, eax\nxchg ax, ax\nloc_13E0:\ncmp r8d, [rdi+rax]\njle short loc_13F4\nmov ecx, [rsi+rax]\ncmp ecx, [rsi+rdx]\njl short loc_13F4\nadd ecx, 1\nmov [rsi+rdx], ecx\nloc_13F4:\nadd rax, 4\ncmp rax, rdx\njnz short loc_13E0\nlea rdx, [rax+4]\ncmp rdx, r10\njnz short loc_13D8\ncmp ebx, 2\njbe loc_1511\nmov edx, r9d\nmov rax, rsi\npxor xmm2, xmm2\nshr edx, 2\nshl rdx, 4\nadd rdx, rsi\nnop dword ptr [rax+rax+00h]\nloc_1428:\nmovdqu xmm0, xmmword ptr [rax]\nadd rax, 10h\nmovdqa xmm1, xmm0\npcmpgtd xmm1, xmm2\npand xmm0, xmm1\npandn xmm1, xmm2\nmovdqa xmm2, xmm1\npor xmm2, xmm0\ncmp rdx, rax\njnz short loc_1428\nmovdqa xmm0, xmm2\nmov edx, r9d\npsrldq xmm0, 8\nand edx, 0FFFFFFFCh\nmovdqa xmm1, xmm0\npcmpgtd xmm1, xmm2\npand xmm0, xmm1\npandn xmm1, xmm2\npor xmm1, xmm0\nmovdqa xmm2, xmm1\npsrldq xmm2, 4\nmovdqa xmm0, xmm2\npcmpgtd xmm0, xmm1\npand xmm2, xmm0\npandn xmm0, xmm1\npor xmm0, xmm2\nmovd eax, xmm0\ntest r9b, 3\njz short loc_14C8\nmovsxd rcx, edx\nlea r11, [rsi+rcx*4]\nmov ecx, [r11]\ncmp eax, ecx\ncmovl eax, ecx\nlea ecx, [rdx+1]\ncmp ecx, r9d\njge short loc_14C8\nloc_14AE:\nmov ecx, [r11+4]\ncmp eax, ecx\ncmovl eax, ecx\nadd edx, 2\ncmp r9d, edx\njle short loc_14C8\nmov edx, [r11+8]\ncmp eax, edx\ncmovl eax, edx\nloc_14C8:\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njnz short loc_1522\nlea rsp, [rbp-10h]\npop rbx\npop r12\npop rbp\nretn\nloc_14E0:\nor [rsp+rdx+1020h+var_1028], 0\njmp loc_132B\nloc_14EB:\nxor eax, eax\njmp short loc_14C8\nloc_14EF:\nmov ds:dword_0[r12*4], 1\nmov rdx, rsi\nxor eax, eax\ncmp r9d, 1\njnz loc_13B0\nmov eax, 1\njmp short loc_14C8\nloc_1511:\nmov eax, ds:dword_0[r12*4]\nxor edx, edx\ntest eax, eax\ncmovs eax, edx\njmp short loc_14AE\nloc_1522:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12C0(__int64 a1, int a2)\n{\n __int64 v2; // rdx\n __m128i *v3; // rcx\n __int16 v4; // dx\n signed __int64 v5; // rdx\n void *v6; // rsp\n int *v7; // r11\n __m128i si128; // xmm0\n __m128i *v9; // rax\n __int64 v10; // rdx\n __m128i *v11; // rcx\n int v12; // eax\n __m128i *v13; // rdx\n __int64 v14; // rdx\n int v15; // r8d\n unsigned __int64 v16; // rax\n __int32 v17; // ecx\n const __m128i *v18; // rax\n __m128i v19; // xmm2\n __m128i v20; // xmm0\n __m128i v21; // xmm1\n __m128i v22; // xmm0\n unsigned int v23; // edx\n __m128i v24; // xmm1\n __m128i v25; // xmm1\n __m128i v26; // xmm2\n __m128i v27; // xmm0\n __int64 result; // rax\n int v29; // ecx\n int v30; // edx\n __int64 v31; // [rsp+0h] [rbp-1028h]\n __m128i v32; // [rsp+8h] [rbp-1020h] BYREF\n _BYTE v33[4072]; // [rsp+18h] [rbp-1010h] BYREF\n _QWORD v34[4]; // [rsp+1008h] [rbp-20h] BYREF\n\n v34[1] = __readfsqword(0x28u);\n v2 = 4LL * a2 + 15;\n v3 = (__m128i *)((char *)v34 - (v2 & 0xFFFFFFFFFFFFF000LL));\n v4 = v2 & 0xFFF0;\n if ( v34 != (_QWORD *)v3 )\n {\n while ( &v32 != v3 )\n ;\n }\n v5 = v4 & 0xFFF;\n v6 = alloca(v5);\n if ( v5 )\n *(__int64 *)((char *)&v31 + v5) = *(__int64 *)((char *)&v31 + v5);\n v7 = (int *)&v32;\n if ( a2 <= 0 )\n return 0LL;\n if ( (unsigned int)(a2 - 1) <= 2 )\n {\n v32.m128i_i32[0] = 1;\n v13 = &v32;\n v12 = 0;\n if ( a2 == 1 )\n return 1LL;\n goto LABEL_12;\n }\n si128 = _mm_load_si128((const __m128i *)&xmmword_2090);\n v9 = &v32;\n v10 = 16LL * ((unsigned int)a2 >> 2);\n v11 = (__m128i *)((char *)&v32 + v10);\n if ( (v10 & 0x10) == 0 || (v9 = (__m128i *)v33, v32 = si128, v33 != (_BYTE *)v11) )\n {\n do\n {\n *v9 = si128;\n v9 += 2;\n v9[-1] = si128;\n }\n while ( v9 != v11 );\n }\n v12 = a2 & 0x7FFFFFFC;\n if ( (a2 & 3) != 0 )\n {\n v13 = (__m128i *)((char *)&v32 + 4 * (unsigned int)v12);\n v13->m128i_i32[0] = 1;\n if ( a2 > v12 + 1 )\n {\nLABEL_12:\n v13->m128i_i32[1] = 1;\n if ( a2 > v12 + 2 )\n v13->m128i_i32[2] = 1;\n }\n }\n v14 = 4LL;\n do\n {\n v15 = *(_DWORD *)(a1 + v14);\n v16 = 0LL;\n do\n {\n if ( v15 > *(_DWORD *)(a1 + v16) )\n {\n v17 = v32.m128i_i32[v16 / 4];\n if ( v17 >= *(__int32 *)((char *)v32.m128i_i32 + v14) )\n *(__int32 *)((char *)v32.m128i_i32 + v14) = v17 + 1;\n }\n v16 += 4LL;\n }\n while ( v16 != v14 );\n v14 = v16 + 4;\n }\n while ( v16 + 4 != 4LL * (unsigned int)a2 );\n if ( (unsigned int)(a2 - 1) <= 2 )\n {\n result = v32.m128i_u32[0];\n v23 = 0;\n if ( v32.m128i_i32[0] < 0 )\n result = 0LL;\n goto LABEL_28;\n }\n v18 = &v32;\n v19 = 0LL;\n do\n {\n v20 = _mm_loadu_si128(v18++);\n v21 = _mm_cmpgt_epi32(v20, v19);\n v19 = _mm_or_si128(_mm_andnot_si128(v21, v19), _mm_and_si128(v20, v21));\n }\n while ( &v32 + ((unsigned int)a2 >> 2) != v18 );\n v22 = _mm_srli_si128(v19, 8);\n v23 = a2 & 0xFFFFFFFC;\n v24 = _mm_cmpgt_epi32(v22, v19);\n v25 = _mm_or_si128(_mm_andnot_si128(v24, v19), _mm_and_si128(v22, v24));\n v26 = _mm_srli_si128(v25, 4);\n v27 = _mm_cmpgt_epi32(v26, v25);\n result = (unsigned int)_mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v27, v25), _mm_and_si128(v26, v27)));\n if ( (a2 & 3) != 0 )\n {\n v7 = &v32.m128i_i32[v23];\n if ( (int)result < *v7 )\n result = (unsigned int)*v7;\n if ( (int)(v23 + 1) < a2 )\n {\nLABEL_28:\n v29 = v7[1];\n if ( (int)result < v29 )\n result = (unsigned int)v29;\n if ( a2 > (int)(v23 + 2) )\n {\n v30 = v7[2];\n if ( (int)result < v30 )\n return (unsigned int)v30;\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12C0(long long a1, int a2) {\n long long v2;\n __m128i *v3;\n short v4;\n signed long long v5;\n void *v6;\n int *v7;\n __m128i si128;\n __m128i *v9;\n long long v10;\n __m128i *v11;\n int v12;\n __m128i *v13;\n long long v14;\n int v15;\n unsigned long long v16;\n int v17;\n const __m128i *v18;\n __m128i v19;\n __m128i v20;\n __m128i v21;\n __m128i v22;\n unsigned int v23;\n __m128i v24;\n __m128i v25;\n __m128i v26;\n __m128i v27;\n long long result;\n int v29;\n int v30;\n long long v31;\n __m128i v32;\n uint8_t v33[4072];\n uint64_t v34[4];\n v34[1] = __readfsqword(40u);\n v2 = 4LL * a2 + 15;\n v3 = (__m128i *)((char *)v34 - (v2 & 18446744073709547520LL));\n v4 = v2 & 65520;\n if (v34 != (uint64_t *)v3) {\n while (&v32 != v3)\n ;\n }\n v5 = v4 & 4095;\n v6 = alloca(v5);\n if (v5) *(long long *)((char *)&v31 + v5) = *(long long *)((char *)&v31 + v5);\n v7 = (int *)&v32;\n if (a2 <= 0) return 0LL;\n if ((unsigned int)(a2 - 1) <= 2) {\n v32.m128i_i32[0] = 1;\n v13 = &v32;\n v12 = 0;\n if (a2 == 1) return 1LL;\n goto LABEL_12;\n }\n si128 = _mm_load_si128((const __m128i *)&xmmword_2090);\n v9 = &v32;\n v10 = 16LL * ((unsigned int)a2 >> 2);\n v11 = (__m128i *)((char *)&v32 + v10);\n if ((v10 & 16) == 0 ||\n (v9 = (__m128i *)v33, v32 = si128, v33 != (uint8_t *)v11)) {\n do {\n *v9 = si128;\n v9 += 2;\n v9[-1] = si128;\n } while (v9 != v11);\n }\n v12 = a2 & 2147483644;\n if ((a2 & 3) != 0) {\n v13 = (__m128i *)((char *)&v32 + 4 * (unsigned int)v12);\n v13->m128i_i32[0] = 1;\n if (a2 > v12 + 1) {\n LABEL_12:\n v13->m128i_i32[1] = 1;\n if (a2 > v12 + 2) v13->m128i_i32[2] = 1;\n }\n }\n v14 = 4LL;\n do {\n v15 = *(uint32_t *)(a1 + v14);\n v16 = 0LL;\n do {\n if (v15 > *(uint32_t *)(a1 + v16)) {\n v17 = v32.m128i_i32[v16 / 4];\n if (v17 >= *(int *)((char *)v32.m128i_i32 + v14))\n *(int *)((char *)v32.m128i_i32 + v14) = v17 + 1;\n }\n v16 += 4LL;\n } while (v16 != v14);\n v14 = v16 + 4;\n } while (v16 + 4 != 4LL * (unsigned int)a2);\n if ((unsigned int)(a2 - 1) <= 2) {\n result = v32.m128i_u32[0];\n v23 = 0;\n if (v32.m128i_i32[0] < 0) result = 0LL;\n goto LABEL_28;\n }\n v18 = &v32;\n v19 = 0LL;\n do {\n v20 = _mm_loadu_si128(v18++);\n v21 = _mm_cmpgt_epi32(v20, v19);\n v19 = _mm_or_si128(_mm_andnot_si128(v21, v19), _mm_and_si128(v20, v21));\n } while (&v32 + ((unsigned int)a2 >> 2) != v18);\n v22 = _mm_srli_si128(v19, 8);\n v23 = a2 & 4294967292;\n v24 = _mm_cmpgt_epi32(v22, v19);\n v25 = _mm_or_si128(_mm_andnot_si128(v24, v19), _mm_and_si128(v22, v24));\n v26 = _mm_srli_si128(v25, 4);\n v27 = _mm_cmpgt_epi32(v26, v25);\n result = (unsigned int)_mm_cvtsi128_si32(\n _mm_or_si128(_mm_andnot_si128(v27, v25), _mm_and_si128(v26, v27)));\n if ((a2 & 3) != 0) {\n v7 = &v32.m128i_i32[v23];\n if ((int)result < *v7) result = (unsigned int)*v7;\n if ((int)(v23 + 1) < a2) {\n LABEL_28:\n v29 = v7[1];\n if ((int)result < v29) result = (unsigned int)v29;\n if (a2 > (int)(v23 + 2)) {\n v30 = v7[2];\n if ((int)result < v30) return (unsigned int)v30;\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n __m128i *v3;\n short v4;\n signed long long v5;\n void *v6;\n int *v7;\n __m128i si128;\n __m128i *v9;\n long long v10;\n __m128i *v11;\n int v12;\n __m128i *v13;\n long long v14;\n int v15;\n unsigned long long v16;\n int v17;\n const __m128i *v18;\n __m128i v19;\n __m128i v20;\n __m128i v21;\n __m128i v22;\n unsigned int v23;\n __m128i v24;\n __m128i v25;\n __m128i v26;\n __m128i v27;\n long long result;\n int v29;\n int v30;\n long long v31;\n __m128i v32;\n uint8_t v33[4072];\n uint64_t v34[4];\n v34[1] = __readfsqword(40u);\n v2 = 4LL * a2 + 15;\n v3 = (__m128i *)((char *)v34 - (v2 & 18446744073709547520LL));\n v4 = v2 & 65520;\n if (v34 != (uint64_t *)v3) {\n while (&v32 != v3)\n ;\n }\n v5 = v4 & 4095;\n v6 = alloca(v5);\n if (v5) *(long long *)((char *)&v31 + v5) = *(long long *)((char *)&v31 + v5);\n v7 = (int *)&v32;\n if (a2 <= 0) return 0LL;\n if ((unsigned int)(a2 - 1) <= 2) {\n v32.m128i_i32[0] = 1;\n v13 = &v32;\n v12 = 0;\n if (a2 == 1) return 1LL;\n goto LABEL_12;\n }\n si128 = _mm_load_si128((const __m128i *)&xmmword_2090);\n v9 = &v32;\n v10 = 16LL * ((unsigned int)a2 >> 2);\n v11 = (__m128i *)((char *)&v32 + v10);\n if ((v10 & 16) == 0 ||\n (v9 = (__m128i *)v33, v32 = si128, v33 != (uint8_t *)v11)) {\n do {\n *v9 = si128;\n v9 += 2;\n v9[-1] = si128;\n } while (v9 != v11);\n }\n v12 = a2 & 2147483644;\n if ((a2 & 3) != 0) {\n v13 = (__m128i *)((char *)&v32 + 4 * (unsigned int)v12);\n v13->m128i_i32[0] = 1;\n if (a2 > v12 + 1) {\n LABEL_12:\n v13->m128i_i32[1] = 1;\n if (a2 > v12 + 2) v13->m128i_i32[2] = 1;\n }\n }\n v14 = 4LL;\n do {\n v15 = *(uint32_t *)(a1 + v14);\n v16 = 0LL;\n do {\n if (v15 > *(uint32_t *)(a1 + v16)) {\n v17 = v32.m128i_i32[v16 / 4];\n if (v17 >= *(int *)((char *)v32.m128i_i32 + v14))\n *(int *)((char *)v32.m128i_i32 + v14) = v17 + 1;\n }\n v16 += 4LL;\n } while (v16 != v14);\n v14 = v16 + 4;\n } while (v16 + 4 != 4LL * (unsigned int)a2);\n if ((unsigned int)(a2 - 1) <= 2) {\n result = v32.m128i_u32[0];\n v23 = 0;\n if (v32.m128i_i32[0] < 0) result = 0LL;\n goto LABEL_28;\n }\n v18 = &v32;\n v19 = 0LL;\n do {\n v20 = _mm_loadu_si128(v18++);\n v21 = _mm_cmpgt_epi32(v20, v19);\n v19 = _mm_or_si128(_mm_andnot_si128(v21, v19), _mm_and_si128(v20, v21));\n } while (&v32 + ((unsigned int)a2 >> 2) != v18);\n v22 = _mm_srli_si128(v19, 8);\n v23 = a2 & 4294967292;\n v24 = _mm_cmpgt_epi32(v22, v19);\n v25 = _mm_or_si128(_mm_andnot_si128(v24, v19), _mm_and_si128(v22, v24));\n v26 = _mm_srli_si128(v25, 4);\n v27 = _mm_cmpgt_epi32(v26, v25);\n result = (unsigned int)_mm_cvtsi128_si32(\n _mm_or_si128(_mm_andnot_si128(v27, v25), _mm_and_si128(v26, v27)));\n if ((a2 & 3) != 0) {\n v7 = &v32.m128i_i32[v23];\n if ((int)result < *v7) result = (unsigned int)*v7;\n if ((int)(v23 + 1) < a2) {\n LABEL_28:\n v29 = v7[1];\n if ((int)result < v29) result = (unsigned int)v29;\n if (a2 > (int)(v23 + 2)) {\n v30 = v7[2];\n if ((int)result < v30) return (unsigned int)v30;\n }\n }\n }\n return result;\n}" + }, + { + "index": 549, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int j = 0;\n int sm = 0;\n for (int i = 1; i <= n; i++) {\n j = (2 * i - 1);\n sm += (j * j * j * j * j);\n }\n return sm;\n}", + "test": "int main() {\n\n assert(func0(1) == 1);\n\n assert(func0(2) == 244);\n\n assert(func0(3) == 3369);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmovl $0x0,-0x4(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x1,-0x8(%rbp)\njmp 118f \nmov -0x8(%rbp),%eax\nadd %eax,%eax\nsub $0x1,%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nimul %eax,%eax\nimul -0x4(%rbp),%eax\nimul -0x4(%rbp),%eax\nimul -0x4(%rbp),%eax\nadd %eax,-0xc(%rbp)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x14(%rbp),%eax\njle 116b \nmov -0xc(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_4], 0\nmov [rbp+var_C], 0\nmov [rbp+var_8], 1\njmp short loc_118F\nloc_116B:\nmov eax, [rbp+var_8]\nadd eax, eax\nsub eax, 1\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\nimul eax, eax\nimul eax, [rbp+var_4]\nimul eax, [rbp+var_4]\nimul eax, [rbp+var_4]\nadd [rbp+var_C], eax\nadd [rbp+var_8], 1\nloc_118F:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_14]\njle short loc_116B\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v2; // [rsp+8h] [rbp-Ch]\n int i; // [rsp+Ch] [rbp-8h]\n\n v2 = 0;\n for ( i = 1; i <= a1; ++i )\n v2 += (2 * i - 1) * (2 * i - 1) * (2 * i - 1) * (2 * i - 1) * (2 * i - 1);\n return v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_4], 0\nmov [rbp+var_C], 0\nmov [rbp+var_8], 1\njmp short loc_118F\nloc_116B:\nmov eax, [rbp+var_8]\nadd eax, eax\nsub eax, 1\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\nimul eax, eax\nimul eax, [rbp+var_4]\nimul eax, [rbp+var_4]\nimul eax, [rbp+var_4]\nadd [rbp+var_C], eax\nadd [rbp+var_8], 1\nloc_118F:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_14]\njle short loc_116B\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n unsigned int v2; // [rsp+8h] [rbp-Ch]\n int i; // [rsp+Ch] [rbp-8h]\n\n v2 = 0;\n for ( i = 1; i <= a1; ++i )\n v2 += (2 * i - 1) * (2 * i - 1) * (2 * i - 1) * (2 * i - 1) * (2 * i - 1);\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n unsigned int v2;\n int i;\n v2 = 0;\n for (i = 1; i <= a1; ++i)\n v2 += (2 * i - 1) * (2 * i - 1) * (2 * i - 1) * (2 * i - 1) * (2 * i - 1);\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v2;\n int i;\n v2 = 0;\n for (i = 1; i <= a1; ++i)\n v2 += (2 * i - 1) * (2 * i - 1) * (2 * i - 1) * (2 * i - 1) * (2 * i - 1);\n return v2;\n}" + }, + { + "index": 549, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int j = 0;\n int sm = 0;\n for (int i = 1; i <= n; i++) {\n j = (2 * i - 1);\n sm += (j * j * j * j * j);\n }\n return sm;\n}", + "test": "int main() {\n\n assert(func0(1) == 1);\n\n assert(func0(2) == 244);\n\n assert(func0(3) == 3369);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\njle 1176 \nlea 0x1(%rdi,%rdi,1),%esi\nmov $0x1,%edx\nmov $0x0,%ecx\nmov %edx,%eax\nimul %edx,%eax\nimul %eax,%eax\nimul %edx,%eax\nadd %eax,%ecx\nadd $0x2,%edx\ncmp %esi,%edx\njne 115f \nmov %ecx,%eax\nretq\nmov $0x0,%ecx\njmp 1173 \n", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njle short loc_1176\nlea esi, [rdi+rdi+1]\nmov edx, 1\nmov ecx, 0\nloc_115F:\nmov eax, edx\nimul eax, edx\nimul eax, eax\nimul eax, edx\nadd ecx, eax\nadd edx, 2\ncmp edx, esi\njnz short loc_115F\nloc_1173:\nmov eax, ecx\nretn\nloc_1176:\nmov ecx, 0\njmp short loc_1173", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // edx\n unsigned int v2; // ecx\n\n if ( a1 <= 0 )\n {\n return 0;\n }\n else\n {\n v1 = 1;\n v2 = 0;\n do\n {\n v2 += v1 * v1 * v1 * v1 * v1;\n v1 += 2;\n }\n while ( v1 != 2 * a1 + 1 );\n }\n return v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ntest edi, edi\njle short loc_1176\nlea esi, [rdi+rdi+1]\nmov edx, 1\nmov ecx, 0\nloc_115F:\nmov eax, edx\nimul eax, edx\nimul eax, eax\nimul eax, edx\nadd ecx, eax\nadd edx, 2\ncmp edx, esi\njnz short loc_115F\nloc_1173:\nmov eax, ecx\nretn\nloc_1176:\nmov ecx, 0\njmp short loc_1173", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v1; // edx\n unsigned int v2; // ecx\n\n if ( a1 <= 0 )\n {\n return 0;\n }\n else\n {\n v1 = 1;\n v2 = 0;\n do\n {\n v2 += v1 * v1 * v1 * v1 * v1;\n v1 += 2;\n }\n while ( v1 != 2 * a1 + 1 );\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v1;\n unsigned int v2;\n if (a1 <= 0) {\n return 0;\n } else {\n v1 = 1;\n v2 = 0;\n do {\n v2 += v1 * v1 * v1 * v1 * v1;\n v1 += 2;\n } while (v1 != 2 * a1 + 1);\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n unsigned int v2;\n if (a1 <= 0) {\n return 0;\n } else {\n v1 = 1;\n v2 = 0;\n do {\n v2 += v1 * v1 * v1 * v1 * v1;\n v1 += 2;\n } while (v1 != 2 * a1 + 1);\n }\n return v2;\n}" + }, + { + "index": 549, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int j = 0;\n int sm = 0;\n for (int i = 1; i <= n; i++) {\n j = (2 * i - 1);\n sm += (j * j * j * j * j);\n }\n return sm;\n}", + "test": "int main() {\n\n assert(func0(1) == 1);\n\n assert(func0(2) == 244);\n\n assert(func0(3) == 3369);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\njle 1178 \nlea 0x1(%rdi,%rdi,1),%ecx\nmov $0x1,%edx\nxor %r8d,%r8d\nnopl 0x0(%rax)\nmov %edx,%eax\nimul %edx,%eax\nimul %eax,%eax\nimul %edx,%eax\nadd $0x2,%edx\nadd %eax,%r8d\ncmp %edx,%ecx\njne 1158 \nmov %r8d,%eax\nretq\nnopl 0x0(%rax)\nxor %r8d,%r8d\nmov %r8d,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njle short loc_1220\nlea esi, [rdi+rdi+1]\nmov edx, 1\nxor ecx, ecx\nnop dword ptr [rax+rax+00h]\nloc_1208:\nmov eax, edx\nimul eax, edx\nimul eax, eax\nimul eax, edx\nadd edx, 2\nadd ecx, eax\ncmp esi, edx\njnz short loc_1208\nmov eax, ecx\nretn\nloc_1220:\nxor ecx, ecx\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // edx\n unsigned int v2; // ecx\n int v3; // eax\n\n if ( a1 <= 0 )\n return 0LL;\n v1 = 1;\n v2 = 0;\n do\n {\n v3 = v1 * v1 * v1 * v1 * v1;\n v1 += 2;\n v2 += v3;\n }\n while ( 2 * a1 + 1 != v1 );\n return v2;\n}", + "ida_strip_asm": "sub_11F0:\nendbr64\ntest edi, edi\njle short loc_1220\nlea esi, [rdi+rdi+1]\nmov edx, 1\nxor ecx, ecx\nnop dword ptr [rax+rax+00h]\nloc_1208:\nmov eax, edx\nimul eax, edx\nimul eax, eax\nimul eax, edx\nadd edx, 2\nadd ecx, eax\ncmp esi, edx\njnz short loc_1208\nmov eax, ecx\nretn\nloc_1220:\nxor ecx, ecx\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11F0(int a1)\n{\n int v1; // edx\n unsigned int v2; // ecx\n int v3; // eax\n\n if ( a1 <= 0 )\n return 0LL;\n v1 = 1;\n v2 = 0;\n do\n {\n v3 = v1 * v1 * v1 * v1 * v1;\n v1 += 2;\n v2 += v3;\n }\n while ( 2 * a1 + 1 != v1 );\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11F0(int a1) {\n int v1;\n unsigned int v2;\n int v3;\n if (a1 <= 0) return 0LL;\n v1 = 1;\n v2 = 0;\n do {\n v3 = v1 * v1 * v1 * v1 * v1;\n v1 += 2;\n v2 += v3;\n } while (2 * a1 + 1 != v1);\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n unsigned int v2;\n int v3;\n if (a1 <= 0) return 0LL;\n v1 = 1;\n v2 = 0;\n do {\n v3 = v1 * v1 * v1 * v1 * v1;\n v1 += 2;\n v2 += v3;\n } while (2 * a1 + 1 != v1);\n return v2;\n}" + }, + { + "index": 550, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int low, int high) {\n if (high < low) return arr[0];\n if (high == low) return arr[low];\n int mid = low + (high - low) / 2;\n if (mid < high && arr[mid + 1] < arr[mid]) return arr[mid];\n if (mid > low && arr[mid] < arr[mid - 1]) return arr[mid - 1];\n if (arr[low] > arr[mid])\n return func0(arr, low, mid - 1);\n else\n return func0(arr, mid + 1, high);\n}", + "test": "int main() {\n\n int arr1[] = {2, 3, 5, 6, 9};\n\n int arr2[] = {3, 4, 5, 2, 1};\n\n int arr3[] = {1, 2, 3};\n\n \n\n assert(func0(arr1, 0, 4) == 9);\n\n assert(func0(arr2, 0, 4) == 5);\n\n assert(func0(arr3, 0, 2) == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmov -0x20(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njge 1192 \nmov -0x18(%rbp),%rax\nmov (%rax),%eax\njmpq 12d5 \nmov -0x20(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njne 11b5 \nmov -0x1c(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\njmpq 12d5 \nmov -0x20(%rbp),%eax\nsub -0x1c(%rbp),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nmov %eax,%edx\nmov -0x1c(%rbp),%eax\nadd %edx,%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x20(%rbp),%eax\njge 1225 \nmov -0x4(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njge 1225 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\njmpq 12d5 \nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njle 1275 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njge 1275 \nmov -0x4(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\njmp 12d5 \nmov -0x1c(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njle 12be \nmov -0x4(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x1c(%rbp),%ecx\nmov -0x18(%rbp),%rax\nmov %ecx,%esi\nmov %rax,%rdi\ncallq 1169 \njmp 12d5 \nmov -0x4(%rbp),%eax\nlea 0x1(%rax),%ecx\nmov -0x20(%rbp),%edx\nmov -0x18(%rbp),%rax\nmov %ecx,%esi\nmov %rax,%rdi\ncallq 1169 \nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_1C]\njge short loc_1192\nmov rax, [rbp+var_18]\nmov eax, [rax]\njmp locret_12D5\nloc_1192:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_1C]\njnz short loc_11B5\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\njmp locret_12D5\nloc_11B5:\nmov eax, [rbp+var_20]\nsub eax, [rbp+var_1C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov edx, eax\nmov eax, [rbp+var_1C]\nadd eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_20]\njge short loc_1225\nmov eax, [rbp+var_4]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njge short loc_1225\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\njmp locret_12D5\nloc_1225:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njle short loc_1275\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nshl rax, 2\nlea rcx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njge short loc_1275\nmov eax, [rbp+var_4]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\njmp short locret_12D5\nloc_1275:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_12BE\nmov eax, [rbp+var_4]\nlea edx, [rax-1]\nmov ecx, [rbp+var_1C]\nmov rax, [rbp+var_18]\nmov esi, ecx\nmov rdi, rax\ncall func0\njmp short locret_12D5\nloc_12BE:\nmov eax, [rbp+var_4]\nlea ecx, [rax+1]\nmov edx, [rbp+var_20]\nmov rax, [rbp+var_18]\nmov esi, ecx\nmov rdi, rax\ncall func0\nlocret_12D5:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, signed int a2, signed int a3)\n{\n int v4; // [rsp+1Ch] [rbp-4h]\n\n if ( a3 < a2 )\n return *a1;\n if ( a3 == a2 )\n return a1[a2];\n v4 = (a3 - a2) / 2 + a2;\n if ( v4 < a3 && (int)a1[v4 + 1] < (int)a1[v4] )\n return a1[v4];\n if ( v4 > a2 && (int)a1[v4] < (int)a1[v4 - 1] )\n return a1[v4 - 1];\n if ( (int)a1[a2] <= (int)a1[v4] )\n return func0(a1, (unsigned int)(v4 + 1), (unsigned int)a3);\n return func0(a1, (unsigned int)a2, (unsigned int)(v4 - 1));\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_1C]\njge short loc_1192\nmov rax, [rbp+var_18]\nmov eax, [rax]\njmp locret_12D5\nloc_1192:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_1C]\njnz short loc_11B5\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\njmp locret_12D5\nloc_11B5:\nmov eax, [rbp+var_20]\nsub eax, [rbp+var_1C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov edx, eax\nmov eax, [rbp+var_1C]\nadd eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_20]\njge short loc_1225\nmov eax, [rbp+var_4]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njge short loc_1225\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\njmp locret_12D5\nloc_1225:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njle short loc_1275\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nshl rax, 2\nlea rcx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njge short loc_1275\nmov eax, [rbp+var_4]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\njmp short locret_12D5\nloc_1275:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_12BE\nmov eax, [rbp+var_4]\nlea edx, [rax-1]\nmov ecx, [rbp+var_1C]\nmov rax, [rbp+var_18]\nmov esi, ecx\nmov rdi, rax\ncall sub_1169\njmp short locret_12D5\nloc_12BE:\nmov eax, [rbp+var_4]\nlea ecx, [rax+1]\nmov edx, [rbp+var_20]\nmov rax, [rbp+var_18]\nmov esi, ecx\nmov rdi, rax\ncall sub_1169\nlocret_12D5:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(unsigned int *a1, signed int a2, signed int a3)\n{\n int v4; // [rsp+1Ch] [rbp-4h]\n\n if ( a3 < a2 )\n return *a1;\n if ( a3 == a2 )\n return a1[a2];\n v4 = (a3 - a2) / 2 + a2;\n if ( v4 < a3 && (int)a1[v4 + 1] < (int)a1[v4] )\n return a1[v4];\n if ( v4 > a2 && (int)a1[v4] < (int)a1[v4 - 1] )\n return a1[v4 - 1];\n if ( (int)a1[a2] <= (int)a1[v4] )\n return sub_1169(a1, (unsigned int)(v4 + 1), (unsigned int)a3);\n return sub_1169(a1, (unsigned int)a2, (unsigned int)(v4 - 1));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(unsigned int *a1, signed int a2, signed int a3) {\n int v4;\n if (a3 < a2) return *a1;\n if (a3 == a2) return a1[a2];\n v4 = (a3 - a2) / 2 + a2;\n if (v4 < a3 && (int)a1[v4 + 1] < (int)a1[v4]) return a1[v4];\n if (v4 > a2 && (int)a1[v4] < (int)a1[v4 - 1]) return a1[v4 - 1];\n if ((int)a1[a2] <= (int)a1[v4])\n return sub_1169(a1, (unsigned int)(v4 + 1), (unsigned int)a3);\n return sub_1169(a1, (unsigned int)a2, (unsigned int)(v4 - 1));\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, signed int a2, signed int a3) {\n int v4;\n if (a3 < a2) return *a1;\n if (a3 == a2) return a1[a2];\n v4 = (a3 - a2) / 2 + a2;\n if (v4 < a3 && (int)a1[v4 + 1] < (int)a1[v4]) return a1[v4];\n if (v4 > a2 && (int)a1[v4] < (int)a1[v4 - 1]) return a1[v4 - 1];\n if ((int)a1[a2] <= (int)a1[v4])\n return func0(a1, (unsigned int)(v4 + 1), (unsigned int)a3);\n return func0(a1, (unsigned int)a2, (unsigned int)(v4 - 1));\n}" + }, + { + "index": 550, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int low, int high) {\n if (high < low) return arr[0];\n if (high == low) return arr[low];\n int mid = low + (high - low) / 2;\n if (mid < high && arr[mid + 1] < arr[mid]) return arr[mid];\n if (mid > low && arr[mid] < arr[mid - 1]) return arr[mid - 1];\n if (arr[low] > arr[mid])\n return func0(arr, low, mid - 1);\n else\n return func0(arr, mid + 1, high);\n}", + "test": "int main() {\n\n int arr1[] = {2, 3, 5, 6, 9};\n\n int arr2[] = {3, 4, 5, 2, 1};\n\n int arr3[] = {1, 2, 3};\n\n \n\n assert(func0(arr1, 0, 4) == 9);\n\n assert(func0(arr2, 0, 4) == 5);\n\n assert(func0(arr3, 0, 2) == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ncmp %esi,%edx\njl 11cb \nje 11ce \nmov %edx,%eax\nsub %esi,%eax\nmov %eax,%ecx\nshr $0x1f,%ecx\nadd %eax,%ecx\nsar %ecx\nadd %esi,%ecx\ncmp %ecx,%edx\njle 1198 \nmovslq %ecx,%r8\nadd $0x1,%r8\nmov -0x4(%rdi,%r8,4),%eax\ncmp %eax,(%rdi,%r8,4)\njl 11df \ncmp %ecx,%esi\njge 11aa \nmovslq %ecx,%r8\nmov -0x4(%rdi,%r8,4),%eax\ncmp %eax,(%rdi,%r8,4)\njl 11df \nsub $0x8,%rsp\nmovslq %esi,%rax\nmovslq %ecx,%r8\nmov (%rdi,%r8,4),%r9d\ncmp %r9d,(%rdi,%rax,4)\njle 11d5 \nlea -0x1(%rcx),%edx\ncallq 1169 \nadd $0x8,%rsp\nretq\nmov (%rdi),%eax\nretq\nmovslq %esi,%rsi\nmov (%rdi,%rsi,4),%eax\nretq\nlea 0x1(%rcx),%esi\ncallq 1169 \njmp 11c6 \nretq\n", + "ida_asm": "func0:\nendbr64\ncmp edx, esi\njl short loc_11CD\nmov ecx, edx\njz short loc_11D0\nmov eax, edx\nsub eax, esi\nmov edx, eax\nshr edx, 1Fh\nadd edx, eax\nsar edx, 1\nadd edx, esi\ncmp ecx, edx\njle short loc_119A\nmovsxd r8, edx\nadd r8, 1\nmov eax, [rdi+r8*4-4]\ncmp [rdi+r8*4], eax\njl short locret_11E3\nloc_119A:\ncmp esi, edx\njge short loc_11AC\nmovsxd r8, edx\nmov eax, [rdi+r8*4-4]\ncmp [rdi+r8*4], eax\njl short locret_11E3\nloc_11AC:\nsub rsp, 8\nmovsxd rax, esi\nmovsxd r8, edx\nmov r9d, [rdi+r8*4]\ncmp [rdi+rax*4], r9d\njle short loc_11D7\nsub edx, 1\ncall func0\nloc_11C8:\nadd rsp, 8\nretn\nloc_11CD:\nmov eax, [rdi]\nretn\nloc_11D0:\nmovsxd rsi, esi\nmov eax, [rdi+rsi*4]\nretn\nloc_11D7:\nlea esi, [rdx+1]\nmov edx, ecx\ncall func0\njmp short loc_11C8\nlocret_11E3:\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, __int64 a2, int a3)\n{\n int v4; // edx\n __int64 v5; // r8\n __int64 result; // rax\n\n if ( a3 < (int)a2 )\n return *a1;\n if ( a3 == (_DWORD)a2 )\n return a1[(int)a2];\n v4 = a2 + (a3 - (int)a2) / 2;\n if ( a3 <= v4 || (v5 = v4 + 1LL, result = a1[v5 - 1], (int)a1[v5] >= (int)result) )\n {\n if ( (int)a2 >= v4 || (result = a1[v4 - 1], (int)a1[v4] >= (int)result) )\n {\n if ( (int)a1[(int)a2] <= (int)a1[v4] )\n return func0(a1, (unsigned int)(v4 + 1), (unsigned int)a3);\n else\n return func0(a1, a2, (unsigned int)(v4 - 1));\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ncmp edx, esi\njl short loc_11CD\nmov ecx, edx\njz short loc_11D0\nmov eax, edx\nsub eax, esi\nmov edx, eax\nshr edx, 1Fh\nadd edx, eax\nsar edx, 1\nadd edx, esi\ncmp ecx, edx\njle short loc_119A\nmovsxd r8, edx\nadd r8, 1\nmov eax, [rdi+r8*4-4]\ncmp [rdi+r8*4], eax\njl short locret_11E3\nloc_119A:\ncmp esi, edx\njge short loc_11AC\nmovsxd r8, edx\nmov eax, [rdi+r8*4-4]\ncmp [rdi+r8*4], eax\njl short locret_11E3\nloc_11AC:\nsub rsp, 8\nmovsxd rax, esi\nmovsxd r8, edx\nmov r9d, [rdi+r8*4]\ncmp [rdi+rax*4], r9d\njle short loc_11D7\nsub edx, 1\ncall sub_1169\nloc_11C8:\nadd rsp, 8\nretn\nloc_11CD:\nmov eax, [rdi]\nretn\nloc_11D0:\nmovsxd rsi, esi\nmov eax, [rdi+rsi*4]\nretn\nloc_11D7:\nlea esi, [rdx+1]\nmov edx, ecx\ncall sub_1169\njmp short loc_11C8\nlocret_11E3:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(unsigned int *a1, __int64 a2, int a3)\n{\n int v4; // edx\n __int64 v5; // r8\n __int64 result; // rax\n\n if ( a3 < (int)a2 )\n return *a1;\n if ( a3 == (_DWORD)a2 )\n return a1[(int)a2];\n v4 = a2 + (a3 - (int)a2) / 2;\n if ( a3 <= v4 || (v5 = v4 + 1LL, result = a1[v5 - 1], (int)a1[v5] >= (int)result) )\n {\n if ( (int)a2 >= v4 || (result = a1[v4 - 1], (int)a1[v4] >= (int)result) )\n {\n if ( (int)a1[(int)a2] <= (int)a1[v4] )\n return sub_1169(a1, (unsigned int)(v4 + 1), (unsigned int)a3);\n else\n return sub_1169(a1, a2, (unsigned int)(v4 - 1));\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(unsigned int *a1, long long a2, int a3) {\n int v4;\n long long v5;\n long long result;\n if (a3 < (int)a2) return *a1;\n if (a3 == (uint32_t)a2) return a1[(int)a2];\n v4 = a2 + (a3 - (int)a2) / 2;\n if (a3 <= v4 ||\n (v5 = v4 + 1LL, result = a1[v5 - 1], (int)a1[v5] >= (int)result)) {\n if ((int)a2 >= v4 || (result = a1[v4 - 1], (int)a1[v4] >= (int)result)) {\n if ((int)a1[(int)a2] <= (int)a1[v4])\n return sub_1169(a1, (unsigned int)(v4 + 1), (unsigned int)a3);\n else\n return sub_1169(a1, a2, (unsigned int)(v4 - 1));\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, long long a2, int a3) {\n int v4;\n long long v5;\n long long result;\n if (a3 < (int)a2) return *a1;\n if (a3 == (uint32_t)a2) return a1[(int)a2];\n v4 = a2 + (a3 - (int)a2) / 2;\n if (a3 <= v4 ||\n (v5 = v4 + 1LL, result = a1[v5 - 1], (int)a1[v5] >= (int)result)) {\n if ((int)a2 >= v4 || (result = a1[v4 - 1], (int)a1[v4] >= (int)result)) {\n if ((int)a1[(int)a2] <= (int)a1[v4])\n return func0(a1, (unsigned int)(v4 + 1), (unsigned int)a3);\n else\n return func0(a1, a2, (unsigned int)(v4 - 1));\n }\n }\n return result;\n}" + }, + { + "index": 550, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int low, int high) {\n if (high < low) return arr[0];\n if (high == low) return arr[low];\n int mid = low + (high - low) / 2;\n if (mid < high && arr[mid + 1] < arr[mid]) return arr[mid];\n if (mid > low && arr[mid] < arr[mid - 1]) return arr[mid - 1];\n if (arr[low] > arr[mid])\n return func0(arr, low, mid - 1);\n else\n return func0(arr, mid + 1, high);\n}", + "test": "int main() {\n\n int arr1[] = {2, 3, 5, 6, 9};\n\n int arr2[] = {3, 4, 5, 2, 1};\n\n int arr3[] = {1, 2, 3};\n\n \n\n assert(func0(arr1, 0, 4) == 9);\n\n assert(func0(arr2, 0, 4) == 5);\n\n assert(func0(arr3, 0, 2) == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ncmp %edx,%esi\njg 12f2 \nnopl 0x0(%rax,%rax,1)\nje 1308 \nmov %edx,%eax\nsub %esi,%eax\nsar %eax\nadd %esi,%eax\nmovslq %eax,%rcx\nmov (%rdi,%rcx,4),%r8d\nlea 0x0(,%rcx,4),%r9\ncmp %edx,%eax\njge 12d4 \ncmp %r8d,0x4(%rdi,%r9,1)\njl 12f5 \ncmp %esi,%eax\njle 12e2 \nmov -0x4(%rdi,%r9,1),%ecx\ncmp %r8d,%ecx\njg 1318 \nmovslq %esi,%rcx\ncmp %r8d,(%rdi,%rcx,4)\njle 1300 \nlea -0x1(%rax),%edx\ncmp %esi,%edx\njge 12b0 \nmov (%rdi),%r8d\nmov %r8d,%eax\nretq\nnopl 0x0(%rax)\nlea 0x1(%rax),%esi\njmp 12ee \nnopl (%rax)\nmovslq %esi,%rsi\nmov (%rdi,%rsi,4),%r8d\nmov %r8d,%eax\nretq\nnopl 0x0(%rax,%rax,1)\nmov %ecx,%r8d\nmov %r8d,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov rcx, rdi\ncmp esi, edx\njg short loc_12D0\nnop dword ptr [rax+rax+00h]\nloc_1290:\njz short loc_12F0\nmov eax, edx\nsub eax, esi\nsar eax, 1\nadd eax, esi\nmovsxd rdi, eax\nlea r8, ds:0[rdi*4]\nmov edi, [rcx+rdi*4]\ncmp eax, edx\njge short loc_12B3\ncmp [rcx+r8+4], edi\njl short loc_12D2\nloc_12B3:\ncmp eax, esi\njg short loc_12D8\nmovsxd rsi, esi\ncmp [rcx+rsi*4], edi\njg short loc_12D0\nloc_12BF:\nlea esi, [rax+1]\nloc_12C2:\ncmp edx, esi\njge short loc_1290\nnop word ptr [rax+rax+00000000h]\nloc_12D0:\nmov edi, [rcx]\nloc_12D2:\nmov eax, edi\nretn\nloc_12D8:\nmov r8d, [rcx+r8-4]\ncmp r8d, edi\njg short loc_1300\nmovsxd r8, esi\ncmp [rcx+r8*4], edi\njle short loc_12BF\nlea edx, [rax-1]\njmp short loc_12C2\nloc_12F0:\nmovsxd rsi, esi\nmov edi, [rcx+rsi*4]\nmov eax, edi\nretn\nloc_1300:\nmov edi, r8d\nmov eax, edi\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2, int a3)\n{\n bool i; // zf\n int v5; // eax\n __int64 v6; // r8\n signed int v7; // edi\n unsigned int v9; // r8d\n\n for ( i = a2 == a3; a3 >= a2; i = a3 == a2 )\n {\n if ( i )\n return a1[a2];\n v5 = a2 + ((a3 - a2) >> 1);\n v6 = v5;\n v7 = a1[v6];\n if ( v5 < a3 && (int)a1[v6 + 1] < v7 )\n return (unsigned int)v7;\n if ( v5 > a2 )\n {\n v9 = a1[v6 - 1];\n if ( (int)v9 > v7 )\n return v9;\n if ( (int)a1[a2] > v7 )\n {\n a3 = v5 - 1;\n continue;\n }\n }\n else if ( (int)a1[a2] > v7 )\n {\n break;\n }\n a2 = v5 + 1;\n }\n return *a1;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\nmov rcx, rdi\ncmp esi, edx\njg short loc_12D0\nnop dword ptr [rax+rax+00h]\nloc_1290:\njz short loc_12F0\nmov eax, edx\nsub eax, esi\nsar eax, 1\nadd eax, esi\nmovsxd rdi, eax\nlea r8, ds:0[rdi*4]\nmov edi, [rcx+rdi*4]\ncmp eax, edx\njge short loc_12B3\ncmp [rcx+r8+4], edi\njl short loc_12D2\nloc_12B3:\ncmp eax, esi\njg short loc_12D8\nmovsxd rsi, esi\ncmp [rcx+rsi*4], edi\njg short loc_12D0\nloc_12BF:\nlea esi, [rax+1]\nloc_12C2:\ncmp edx, esi\njge short loc_1290\nnop word ptr [rax+rax+00000000h]\nloc_12D0:\nmov edi, [rcx]\nloc_12D2:\nmov eax, edi\nretn\nloc_12D8:\nmov r8d, [rcx+r8-4]\ncmp r8d, edi\njg short loc_1300\nmovsxd r8, esi\ncmp [rcx+r8*4], edi\njle short loc_12BF\nlea edx, [rax-1]\njmp short loc_12C2\nloc_12F0:\nmovsxd rsi, esi\nmov edi, [rcx+rsi*4]\nmov eax, edi\nretn\nloc_1300:\nmov edi, r8d\nmov eax, edi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1280(unsigned int *a1, int a2, int a3)\n{\n bool i; // zf\n int v5; // eax\n __int64 v6; // r8\n signed int v7; // edi\n unsigned int v9; // r8d\n\n for ( i = a2 == a3; a3 >= a2; i = a3 == a2 )\n {\n if ( i )\n return a1[a2];\n v5 = a2 + ((a3 - a2) >> 1);\n v6 = v5;\n v7 = a1[v6];\n if ( v5 < a3 && (int)a1[v6 + 1] < v7 )\n return (unsigned int)v7;\n if ( v5 > a2 )\n {\n v9 = a1[v6 - 1];\n if ( (int)v9 > v7 )\n return v9;\n if ( (int)a1[a2] > v7 )\n {\n a3 = v5 - 1;\n continue;\n }\n }\n else if ( (int)a1[a2] > v7 )\n {\n break;\n }\n a2 = v5 + 1;\n }\n return *a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1280(unsigned int *a1, int a2, int a3) {\n bool i;\n int v5;\n long long v6;\n signed int v7;\n unsigned int v9;\n for (i = a2 == a3; a3 >= a2; i = a3 == a2) {\n if (i) return a1[a2];\n v5 = a2 + ((a3 - a2) >> 1);\n v6 = v5;\n v7 = a1[v6];\n if (v5 < a3 && (int)a1[v6 + 1] < v7) return (unsigned int)v7;\n if (v5 > a2) {\n v9 = a1[v6 - 1];\n if ((int)v9 > v7) return v9;\n if ((int)a1[a2] > v7) {\n a3 = v5 - 1;\n continue;\n }\n } else if ((int)a1[a2] > v7) {\n break;\n }\n a2 = v5 + 1;\n }\n return *a1;\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2, int a3) {\n bool i;\n int v5;\n long long v6;\n signed int v7;\n unsigned int v9;\n for (i = a2 == a3; a3 >= a2; i = a3 == a2) {\n if (i) return a1[a2];\n v5 = a2 + ((a3 - a2) >> 1);\n v6 = v5;\n v7 = a1[v6];\n if (v5 < a3 && (int)a1[v6 + 1] < v7) return (unsigned int)v7;\n if (v5 > a2) {\n v9 = a1[v6 - 1];\n if ((int)v9 > v7) return v9;\n if ((int)a1[a2] > v7) {\n a3 = v5 - 1;\n continue;\n }\n } else if ((int)a1[a2] > v7) {\n break;\n }\n a2 = v5 + 1;\n }\n return *a1;\n}" + }, + { + "index": 550, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int low, int high) {\n if (high < low) return arr[0];\n if (high == low) return arr[low];\n int mid = low + (high - low) / 2;\n if (mid < high && arr[mid + 1] < arr[mid]) return arr[mid];\n if (mid > low && arr[mid] < arr[mid - 1]) return arr[mid - 1];\n if (arr[low] > arr[mid])\n return func0(arr, low, mid - 1);\n else\n return func0(arr, mid + 1, high);\n}", + "test": "int main() {\n\n int arr1[] = {2, 3, 5, 6, 9};\n\n int arr2[] = {3, 4, 5, 2, 1};\n\n int arr3[] = {1, 2, 3};\n\n \n\n assert(func0(arr1, 0, 4) == 9);\n\n assert(func0(arr2, 0, 4) == 5);\n\n assert(func0(arr3, 0, 2) == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ncmp %edx,%esi\njg 12e2 \nnopl 0x0(%rax,%rax,1)\nje 12f8 \nmov %edx,%eax\nsub %esi,%eax\nsar %eax\nadd %esi,%eax\nmovslq %eax,%rcx\nmov (%rdi,%rcx,4),%r8d\nlea 0x0(,%rcx,4),%r9\ncmp %edx,%eax\njge 12c4 \ncmp %r8d,0x4(%rdi,%r9,1)\njl 12e5 \ncmp %esi,%eax\njle 12d2 \nmov -0x4(%rdi,%r9,1),%ecx\ncmp %r8d,%ecx\njg 1308 \nmovslq %esi,%rcx\ncmp %r8d,(%rdi,%rcx,4)\njle 12f0 \nlea -0x1(%rax),%edx\ncmp %esi,%edx\njge 12a0 \nmov (%rdi),%r8d\nmov %r8d,%eax\nretq\nnopl 0x0(%rax)\nlea 0x1(%rax),%esi\njmp 12de \nnopl (%rax)\nmovslq %esi,%rsi\nmov (%rdi,%rsi,4),%r8d\nmov %r8d,%eax\nretq\nnopl 0x0(%rax,%rax,1)\nmov %ecx,%r8d\nmov %r8d,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov rcx, rdi\ncmp esi, edx\njg short loc_12D0\nnop dword ptr [rax+rax+00h]\nloc_1290:\njz short loc_12F0\nmov eax, edx\nsub eax, esi\nsar eax, 1\nadd eax, esi\nmovsxd rdi, eax\nlea r8, ds:0[rdi*4]\nmov edi, [rcx+rdi*4]\ncmp eax, edx\njge short loc_12B3\ncmp [rcx+r8+4], edi\njl short loc_12D2\nloc_12B3:\ncmp eax, esi\njg short loc_12D8\nmovsxd rsi, esi\ncmp [rcx+rsi*4], edi\njg short loc_12D0\nloc_12BF:\nlea esi, [rax+1]\nloc_12C2:\ncmp edx, esi\njge short loc_1290\nnop word ptr [rax+rax+00000000h]\nloc_12D0:\nmov edi, [rcx]\nloc_12D2:\nmov eax, edi\nretn\nloc_12D8:\nmov r8d, [rcx+r8-4]\ncmp r8d, edi\njg short loc_1300\nmovsxd r8, esi\ncmp [rcx+r8*4], edi\njle short loc_12BF\nlea edx, [rax-1]\njmp short loc_12C2\nloc_12F0:\nmovsxd rsi, esi\nmov edi, [rcx+rsi*4]\nmov eax, edi\nretn\nloc_1300:\nmov edi, r8d\nmov eax, edi\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2, int a3)\n{\n bool i; // zf\n int v5; // eax\n __int64 v6; // r8\n signed int v7; // edi\n unsigned int v9; // r8d\n\n for ( i = a2 == a3; a3 >= a2; i = a3 == a2 )\n {\n if ( i )\n return a1[a2];\n v5 = a2 + ((a3 - a2) >> 1);\n v6 = v5;\n v7 = a1[v6];\n if ( v5 < a3 && (int)a1[v6 + 1] < v7 )\n return (unsigned int)v7;\n if ( v5 > a2 )\n {\n v9 = a1[v6 - 1];\n if ( (int)v9 > v7 )\n return v9;\n if ( (int)a1[a2] > v7 )\n {\n a3 = v5 - 1;\n continue;\n }\n }\n else if ( (int)a1[a2] > v7 )\n {\n break;\n }\n a2 = v5 + 1;\n }\n return *a1;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\nmov rcx, rdi\ncmp esi, edx\njg short loc_12D0\nnop dword ptr [rax+rax+00h]\nloc_1290:\njz short loc_12F0\nmov eax, edx\nsub eax, esi\nsar eax, 1\nadd eax, esi\nmovsxd rdi, eax\nlea r8, ds:0[rdi*4]\nmov edi, [rcx+rdi*4]\ncmp eax, edx\njge short loc_12B3\ncmp [rcx+r8+4], edi\njl short loc_12D2\nloc_12B3:\ncmp eax, esi\njg short loc_12D8\nmovsxd rsi, esi\ncmp [rcx+rsi*4], edi\njg short loc_12D0\nloc_12BF:\nlea esi, [rax+1]\nloc_12C2:\ncmp edx, esi\njge short loc_1290\nnop word ptr [rax+rax+00000000h]\nloc_12D0:\nmov edi, [rcx]\nloc_12D2:\nmov eax, edi\nretn\nloc_12D8:\nmov r8d, [rcx+r8-4]\ncmp r8d, edi\njg short loc_1300\nmovsxd r8, esi\ncmp [rcx+r8*4], edi\njle short loc_12BF\nlea edx, [rax-1]\njmp short loc_12C2\nloc_12F0:\nmovsxd rsi, esi\nmov edi, [rcx+rsi*4]\nmov eax, edi\nretn\nloc_1300:\nmov edi, r8d\nmov eax, edi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1280(unsigned int *a1, int a2, int a3)\n{\n bool i; // zf\n int v5; // eax\n __int64 v6; // r8\n signed int v7; // edi\n unsigned int v9; // r8d\n\n for ( i = a2 == a3; a3 >= a2; i = a3 == a2 )\n {\n if ( i )\n return a1[a2];\n v5 = a2 + ((a3 - a2) >> 1);\n v6 = v5;\n v7 = a1[v6];\n if ( v5 < a3 && (int)a1[v6 + 1] < v7 )\n return (unsigned int)v7;\n if ( v5 > a2 )\n {\n v9 = a1[v6 - 1];\n if ( (int)v9 > v7 )\n return v9;\n if ( (int)a1[a2] > v7 )\n {\n a3 = v5 - 1;\n continue;\n }\n }\n else if ( (int)a1[a2] > v7 )\n {\n break;\n }\n a2 = v5 + 1;\n }\n return *a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1280(unsigned int *a1, int a2, int a3) {\n bool i;\n int v5;\n long long v6;\n signed int v7;\n unsigned int v9;\n for (i = a2 == a3; a3 >= a2; i = a3 == a2) {\n if (i) return a1[a2];\n v5 = a2 + ((a3 - a2) >> 1);\n v6 = v5;\n v7 = a1[v6];\n if (v5 < a3 && (int)a1[v6 + 1] < v7) return (unsigned int)v7;\n if (v5 > a2) {\n v9 = a1[v6 - 1];\n if ((int)v9 > v7) return v9;\n if ((int)a1[a2] > v7) {\n a3 = v5 - 1;\n continue;\n }\n } else if ((int)a1[a2] > v7) {\n break;\n }\n a2 = v5 + 1;\n }\n return *a1;\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2, int a3) {\n bool i;\n int v5;\n long long v6;\n signed int v7;\n unsigned int v9;\n for (i = a2 == a3; a3 >= a2; i = a3 == a2) {\n if (i) return a1[a2];\n v5 = a2 + ((a3 - a2) >> 1);\n v6 = v5;\n v7 = a1[v6];\n if (v5 < a3 && (int)a1[v6 + 1] < v7) return (unsigned int)v7;\n if (v5 > a2) {\n v9 = a1[v6 - 1];\n if ((int)v9 > v7) return v9;\n if ((int)a1[a2] > v7) {\n a3 = v5 - 1;\n continue;\n }\n } else if ((int)a1[a2] > v7) {\n break;\n }\n a2 = v5 + 1;\n }\n return *a1;\n}" + }, + { + "index": 551, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int** list1, int rows, int n) {\n int* result = malloc(rows * sizeof(int));\n for (int i = 0; i < rows; i++) {\n result[i] = list1[i][n];\n }\n return result;\n}", + "test": "int main() {\n\n // First test case\n\n int row1_1[] = {1, 2, 3};\n\n int row1_2[] = {2, 4, 5};\n\n int row1_3[] = {1, 1, 1};\n\n int* list1[] = {row1_1, row1_2, row1_3};\n\n int expected1[] = {1, 2, 1};\n\n int* result1 = func0(list1, 3, 0);\n\n for(int i = 0; i < 3; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n free(result1);\n\n\n\n // Second test case\n\n int row2_1[] = {1, 2, 3};\n\n int row2_2[] = {-2, 4, -5};\n\n int row2_3[] = {1, -1, 1};\n\n int* list2[] = {row2_1, row2_2, row2_3};\n\n int expected2[] = {3, -5, 1};\n\n int* result2 = func0(list2, 3, 2);\n\n for(int i = 0; i < 3; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n free(result2);\n\n\n\n // Third test case\n\n int row3_1[] = {1, 3, 0};\n\n int row3_2[] = {5, 7, 0};\n\n int row3_3[] = {1, 3, 0};\n\n int row3_4[] = {13, 15, 17};\n\n int row3_5[] = {5, 7, 0};\n\n int row3_6[] = {9, 11, 0};\n\n int* list3[] = {row3_1, row3_2, row3_3, row3_4, row3_5, row3_6};\n\n int expected3[] = {1, 5, 1, 13, 5, 9};\n\n int* result3 = func0(list3, 6, 0);\n\n for(int i = 0; i < 6; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmov -0x1c(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 121e \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0x20(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x2,%rdx\nadd %rdx,%rax\nmov -0xc(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11dd \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp short loc_121E\nloc_11DD:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_C], 1\nloc_121E:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_11DD\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, int a3)\n{\n int i; // [rsp+14h] [rbp-Ch]\n _DWORD *v6; // [rsp+18h] [rbp-8h]\n\n v6 = malloc(4LL * a2);\n for ( i = 0; i < a2; ++i )\n v6[i] = *(_DWORD *)(4LL * a3 + *(_QWORD *)(8LL * i + a1));\n return v6;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp short loc_121E\nloc_11DD:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_C], 1\nloc_121E:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_11DD\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(__int64 a1, int a2, int a3)\n{\n int i; // [rsp+14h] [rbp-Ch]\n _DWORD *v6; // [rsp+18h] [rbp-8h]\n\n v6 = malloc(4LL * a2);\n for ( i = 0; i < a2; ++i )\n v6[i] = *(_DWORD *)(4LL * a3 + *(_QWORD *)(8LL * i + a1));\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(long long a1, int a2, int a3) {\n int i;\n uint32_t *v6;\n v6 = malloc(4LL * a2);\n for (i = 0; i < a2; ++i)\n v6[i] = *(uint32_t *)(4LL * a3 + *(uint64_t *)(8LL * i + a1));\n return v6;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, int a3) {\n int i;\n uint32_t *v6;\n v6 = malloc(4LL * a2);\n for (i = 0; i < a2; ++i)\n v6[i] = *(uint32_t *)(4LL * a3 + *(uint64_t *)(8LL * i + a1));\n return v6;\n}" + }, + { + "index": 551, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int** list1, int rows, int n) {\n int* result = malloc(rows * sizeof(int));\n for (int i = 0; i < rows; i++) {\n result[i] = list1[i][n];\n }\n return result;\n}", + "test": "int main() {\n\n // First test case\n\n int row1_1[] = {1, 2, 3};\n\n int row1_2[] = {2, 4, 5};\n\n int row1_3[] = {1, 1, 1};\n\n int* list1[] = {row1_1, row1_2, row1_3};\n\n int expected1[] = {1, 2, 1};\n\n int* result1 = func0(list1, 3, 0);\n\n for(int i = 0; i < 3; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n free(result1);\n\n\n\n // Second test case\n\n int row2_1[] = {1, 2, 3};\n\n int row2_2[] = {-2, 4, -5};\n\n int row2_3[] = {1, -1, 1};\n\n int* list2[] = {row2_1, row2_2, row2_3};\n\n int expected2[] = {3, -5, 1};\n\n int* result2 = func0(list2, 3, 2);\n\n for(int i = 0; i < 3; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n free(result2);\n\n\n\n // Third test case\n\n int row3_1[] = {1, 3, 0};\n\n int row3_2[] = {5, 7, 0};\n\n int row3_3[] = {1, 3, 0};\n\n int row3_4[] = {13, 15, 17};\n\n int row3_5[] = {5, 7, 0};\n\n int row3_6[] = {9, 11, 0};\n\n int* list3[] = {row3_1, row3_2, row3_3, row3_4, row3_5, row3_6};\n\n int expected3[] = {1, 5, 1, 13, 5, 9};\n\n int* result3 = func0(list3, 6, 0);\n\n for(int i = 0; i < 6; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nmov %esi,%r12d\nmov %edx,%ebp\nmovslq %esi,%rdi\nshl $0x2,%rdi\ncallq 10b0 \ntest %r12d,%r12d\njle 11f1 \nmovslq %ebp,%rsi\nshl $0x2,%rsi\nlea -0x1(%r12),%edi\nmov $0x0,%edx\nmov (%rbx,%rdx,8),%rcx\nmov (%rcx,%rsi,1),%ecx\nmov %ecx,(%rax,%rdx,4)\nmov %rdx,%rcx\nadd $0x1,%rdx\ncmp %rdi,%rcx\njne 11db \npop %rbx\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov r13d, esi\nmov r12d, edx\nmovsxd rbp, esi\nlea rdi, ds:0[rbp*4]; size\ncall _malloc\ntest r13d, r13d\njle short loc_11F4\nmovsxd rsi, r12d\nshl rsi, 2\nmov edx, 0\nloc_11E1:\nmov rcx, [rbx+rdx*8]\nmov ecx, [rcx+rsi]\nmov [rax+rdx*4], ecx\nadd rdx, 1\ncmp rbp, rdx\njnz short loc_11E1\nloc_11F4:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, int a3)\n{\n _DWORD *result; // rax\n __int64 i; // rdx\n\n result = malloc(4LL * a2);\n if ( a2 > 0 )\n {\n for ( i = 0LL; i != a2; ++i )\n result[i] = *(_DWORD *)(*(_QWORD *)(a1 + 8 * i) + 4LL * a3);\n }\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov r13d, esi\nmov r12d, edx\nmovsxd rbp, esi\nlea rdi, ds:0[rbp*4]; size\ncall _malloc\ntest r13d, r13d\njle short loc_11F4\nmovsxd rsi, r12d\nshl rsi, 2\nmov edx, 0\nloc_11E1:\nmov rcx, [rbx+rdx*8]\nmov ecx, [rcx+rsi]\nmov [rax+rdx*4], ecx\nadd rdx, 1\ncmp rbp, rdx\njnz short loc_11E1\nloc_11F4:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(__int64 a1, int a2, int a3)\n{\n _DWORD *result; // rax\n __int64 i; // rdx\n\n result = malloc(4LL * a2);\n if ( a2 > 0 )\n {\n for ( i = 0LL; i != a2; ++i )\n result[i] = *(_DWORD *)(*(_QWORD *)(a1 + 8 * i) + 4LL * a3);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(long long a1, int a2, int a3) {\n uint32_t *result;\n long long i;\n result = malloc(4LL * a2);\n if (a2 > 0) {\n for (i = 0LL; i != a2; ++i)\n result[i] = *(uint32_t *)(*(uint64_t *)(a1 + 8 * i) + 4LL * a3);\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, int a3) {\n uint32_t *result;\n long long i;\n result = malloc(4LL * a2);\n if (a2 > 0) {\n for (i = 0LL; i != a2; ++i)\n result[i] = *(uint32_t *)(*(uint64_t *)(a1 + 8 * i) + 4LL * a3);\n }\n return result;\n}" + }, + { + "index": 551, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int** list1, int rows, int n) {\n int* result = malloc(rows * sizeof(int));\n for (int i = 0; i < rows; i++) {\n result[i] = list1[i][n];\n }\n return result;\n}", + "test": "int main() {\n\n // First test case\n\n int row1_1[] = {1, 2, 3};\n\n int row1_2[] = {2, 4, 5};\n\n int row1_3[] = {1, 1, 1};\n\n int* list1[] = {row1_1, row1_2, row1_3};\n\n int expected1[] = {1, 2, 1};\n\n int* result1 = func0(list1, 3, 0);\n\n for(int i = 0; i < 3; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n free(result1);\n\n\n\n // Second test case\n\n int row2_1[] = {1, 2, 3};\n\n int row2_2[] = {-2, 4, -5};\n\n int row2_3[] = {1, -1, 1};\n\n int* list2[] = {row2_1, row2_2, row2_3};\n\n int expected2[] = {3, -5, 1};\n\n int* result2 = func0(list2, 3, 2);\n\n for(int i = 0; i < 3; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n free(result2);\n\n\n\n // Third test case\n\n int row3_1[] = {1, 3, 0};\n\n int row3_2[] = {5, 7, 0};\n\n int row3_3[] = {1, 3, 0};\n\n int row3_4[] = {13, 15, 17};\n\n int row3_5[] = {5, 7, 0};\n\n int row3_6[] = {9, 11, 0};\n\n int* list3[] = {row3_1, row3_2, row3_3, row3_4, row3_5, row3_6};\n\n int expected3[] = {1, 5, 1, 13, 5, 9};\n\n int* result3 = func0(list3, 6, 0);\n\n for(int i = 0; i < 6; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\nmov %rdi,%rbp\nmovslq %esi,%rdi\npush %rbx\nmov %rdi,%r12\nshl $0x2,%rdi\nmov %edx,%ebx\ncallq 10b0 \ntest %r12d,%r12d\njle 1517 \nmovslq %ebx,%rdi\nlea -0x1(%r12),%esi\nxor %edx,%edx\nshl $0x2,%rdi\nmov 0x0(%rbp,%rdx,8),%rcx\nmov (%rcx,%rdi,1),%ecx\nmov %ecx,(%rax,%rdx,4)\nmov %rdx,%rcx\nadd $0x1,%rdx\ncmp %rsi,%rcx\njne 1500 \npop %rbx\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\nmovsxd r12, esi\npush rbp\nmov rbp, rdi\nlea rdi, ds:0[r12*4]; size\npush rbx\nmov ebx, edx\nsub rsp, 8\ncall _malloc\ntest r12d, r12d\njle short loc_157C\nmovsxd rsi, ebx\nxor edx, edx\nshl rsi, 2\nnop dword ptr [rax+00000000h]\nloc_1568:\nmov rcx, [rbp+rdx*8+0]\nmov ecx, [rcx+rsi]\nmov [rax+rdx*4], ecx\nadd rdx, 1\ncmp r12, rdx\njnz short loc_1568\nloc_157C:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, int a3)\n{\n _DWORD *result; // rax\n __int64 i; // rdx\n\n result = malloc(4LL * a2);\n if ( a2 > 0 )\n {\n for ( i = 0LL; i != a2; ++i )\n result[i] = *(_DWORD *)(*(_QWORD *)(a1 + 8 * i) + 4LL * a3);\n }\n return result;\n}", + "ida_strip_asm": "sub_1530:\nendbr64\npush r13\npush r12\nmovsxd r12, esi\npush rbp\nmov rbp, rdi\nlea rdi, ds:0[r12*4]; size\npush rbx\nmov ebx, edx\nsub rsp, 8\ncall _malloc\ntest r12d, r12d\njle short loc_157C\nmovsxd rsi, ebx\nxor edx, edx\nshl rsi, 2\nnop dword ptr [rax+00000000h]\nloc_1568:\nmov rcx, [rbp+rdx*8+0]\nmov ecx, [rcx+rsi]\nmov [rax+rdx*4], ecx\nadd rdx, 1\ncmp r12, rdx\njnz short loc_1568\nloc_157C:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1530(__int64 a1, int a2, int a3)\n{\n _DWORD *result; // rax\n __int64 i; // rdx\n\n result = malloc(4LL * a2);\n if ( a2 > 0 )\n {\n for ( i = 0LL; i != a2; ++i )\n result[i] = *(_DWORD *)(*(_QWORD *)(a1 + 8 * i) + 4LL * a3);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1530(long long a1, int a2, int a3) {\n uint32_t *result;\n long long i;\n result = malloc(4LL * a2);\n if (a2 > 0) {\n for (i = 0LL; i != a2; ++i)\n result[i] = *(uint32_t *)(*(uint64_t *)(a1 + 8 * i) + 4LL * a3);\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, int a3) {\n uint32_t *result;\n long long i;\n result = malloc(4LL * a2);\n if (a2 > 0) {\n for (i = 0LL; i != a2; ++i)\n result[i] = *(uint32_t *)(*(uint64_t *)(a1 + 8 * i) + 4LL * a3);\n }\n return result;\n}" + }, + { + "index": 551, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int** list1, int rows, int n) {\n int* result = malloc(rows * sizeof(int));\n for (int i = 0; i < rows; i++) {\n result[i] = list1[i][n];\n }\n return result;\n}", + "test": "int main() {\n\n // First test case\n\n int row1_1[] = {1, 2, 3};\n\n int row1_2[] = {2, 4, 5};\n\n int row1_3[] = {1, 1, 1};\n\n int* list1[] = {row1_1, row1_2, row1_3};\n\n int expected1[] = {1, 2, 1};\n\n int* result1 = func0(list1, 3, 0);\n\n for(int i = 0; i < 3; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n free(result1);\n\n\n\n // Second test case\n\n int row2_1[] = {1, 2, 3};\n\n int row2_2[] = {-2, 4, -5};\n\n int row2_3[] = {1, -1, 1};\n\n int* list2[] = {row2_1, row2_2, row2_3};\n\n int expected2[] = {3, -5, 1};\n\n int* result2 = func0(list2, 3, 2);\n\n for(int i = 0; i < 3; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n free(result2);\n\n\n\n // Third test case\n\n int row3_1[] = {1, 3, 0};\n\n int row3_2[] = {5, 7, 0};\n\n int row3_3[] = {1, 3, 0};\n\n int row3_4[] = {13, 15, 17};\n\n int row3_5[] = {5, 7, 0};\n\n int row3_6[] = {9, 11, 0};\n\n int* list3[] = {row3_1, row3_2, row3_3, row3_4, row3_5, row3_6};\n\n int expected3[] = {1, 5, 1, 13, 5, 9};\n\n int* result3 = func0(list3, 6, 0);\n\n for(int i = 0; i < 6; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\nmov %rdi,%rbp\nmovslq %esi,%rdi\npush %rbx\nmov %rdi,%r12\nshl $0x2,%rdi\nmov %edx,%ebx\ncallq 10b0 \ntest %r12d,%r12d\njle 1537 \nmovslq %ebx,%rdi\nlea -0x1(%r12),%esi\nxor %edx,%edx\nshl $0x2,%rdi\nmov 0x0(%rbp,%rdx,8),%rcx\nmov (%rcx,%rdi,1),%ecx\nmov %ecx,(%rax,%rdx,4)\nmov %rdx,%rcx\nadd $0x1,%rdx\ncmp %rsi,%rcx\njne 1520 \npop %rbx\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\nmovsxd r12, esi\npush rbp\nmov rbp, rdi\nlea rdi, ds:0[r12*4]; size\npush rbx\nmov ebx, edx\nsub rsp, 8\ncall _malloc\ntest r12d, r12d\njle short loc_155C\nmovsxd rsi, ebx\nxor edx, edx\nshl rsi, 2\nnop dword ptr [rax+00000000h]\nloc_1548:\nmov rcx, [rbp+rdx*8+0]\nmov ecx, [rcx+rsi]\nmov [rax+rdx*4], ecx\nadd rdx, 1\ncmp r12, rdx\njnz short loc_1548\nloc_155C:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, int a3)\n{\n _DWORD *result; // rax\n __int64 i; // rdx\n\n result = malloc(4LL * a2);\n if ( a2 > 0 )\n {\n for ( i = 0LL; i != a2; ++i )\n result[i] = *(_DWORD *)(*(_QWORD *)(a1 + 8 * i) + 4LL * a3);\n }\n return result;\n}", + "ida_strip_asm": "sub_1510:\nendbr64\npush r13\npush r12\nmovsxd r12, esi\npush rbp\nmov rbp, rdi\nlea rdi, ds:0[r12*4]; size\npush rbx\nmov ebx, edx\nsub rsp, 8\ncall _malloc\ntest r12d, r12d\njle short loc_155C\nmovsxd rsi, ebx\nxor edx, edx\nshl rsi, 2\nnop dword ptr [rax+00000000h]\nloc_1548:\nmov rcx, [rbp+rdx*8+0]\nmov ecx, [rcx+rsi]\nmov [rax+rdx*4], ecx\nadd rdx, 1\ncmp r12, rdx\njnz short loc_1548\nloc_155C:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1510(__int64 a1, int a2, int a3)\n{\n _DWORD *result; // rax\n __int64 i; // rdx\n\n result = malloc(4LL * a2);\n if ( a2 > 0 )\n {\n for ( i = 0LL; i != a2; ++i )\n result[i] = *(_DWORD *)(*(_QWORD *)(a1 + 8 * i) + 4LL * a3);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1510(long long a1, int a2, int a3) {\n uint32_t *result;\n long long i;\n result = malloc(4LL * a2);\n if (a2 > 0) {\n for (i = 0LL; i != a2; ++i)\n result[i] = *(uint32_t *)(*(uint64_t *)(a1 + 8 * i) + 4LL * a3);\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, int a3) {\n uint32_t *result;\n long long i;\n result = malloc(4LL * a2);\n if (a2 > 0) {\n for (i = 0LL; i != a2; ++i)\n result[i] = *(uint32_t *)(*(uint64_t *)(a1 + 8 * i) + 4LL * a3);\n }\n return result;\n}" + }, + { + "index": 552, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "char* func0(int seq_nums[], int n) {\n int diff[n - 1];\n for (int x = 1; x < n; x++) {\n diff[x - 1] = seq_nums[x] - seq_nums[x - 1];\n }\n for (int i = 1; i < n - 1; i++) {\n if (diff[i] != diff[0]) {\n return \"Non Linear Sequence\";\n }\n }\n return \"Linear Sequence\";\n}", + "test": "int main() {\n\n int arr1[] = {0, 2, 4, 6, 8, 10};\n\n int arr2[] = {1, 2, 3};\n\n int arr3[] = {1, 5, 2};\n\n\n\n assert(func0(arr1, 6) == \"Linear Sequence\");\n\n assert(func0(arr2, 3) == \"Linear Sequence\");\n\n assert(func0(arr3, 3) == \"Non Linear Sequence\");\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x38,%rsp\nmov %rdi,-0x38(%rbp)\nmov %esi,-0x3c(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmov %rsp,%rax\nmov %rax,%rdi\nmov -0x3c(%rbp),%eax\nsub $0x1,%eax\nmovslq %eax,%rdx\nsub $0x1,%rdx\nmov %rdx,-0x28(%rbp)\nmovslq %eax,%rdx\nmov %rdx,%r8\nmov $0x0,%r9d\nmovslq %eax,%rdx\nmov %rdx,%rcx\nmov $0x0,%ebx\ncltq\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%ebx\nmov $0x0,%edx\ndiv %rbx\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rbx\nsub %rdx,%rbx\nmov %rbx,%rdx\ncmp %rdx,%rsp\nje 120b \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11f4 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 1235 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x20(%rbp)\nmovl $0x1,-0x2c(%rbp)\njmp 1295 \nmov -0x2c(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x2c(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rcx\nmov -0x38(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\nmov -0x2c(%rbp),%ecx\nlea -0x1(%rcx),%esi\nmov %edx,%ecx\nsub %eax,%ecx\nmov -0x20(%rbp),%rax\nmovslq %esi,%rdx\nmov %ecx,(%rax,%rdx,4)\naddl $0x1,-0x2c(%rbp)\nmov -0x2c(%rbp),%eax\ncmp -0x3c(%rbp),%eax\njl 1251 \nmovl $0x1,-0x30(%rbp)\njmp 12ca \nmov -0x20(%rbp),%rax\nmov -0x30(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%edx\nmov -0x20(%rbp),%rax\nmov (%rax),%eax\ncmp %eax,%edx\nje 12c6 \nlea 0xd44(%rip),%rax\njmp 12dc \naddl $0x1,-0x30(%rbp)\nmov -0x3c(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x30(%rbp)\njl 12a6 \nlea 0xd40(%rip),%rax\nmov %rdi,%rsp\nmov -0x18(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 12f3 \ncallq 1060 <__stack_chk_fail@plt>\nmov -0x8(%rbp),%rbx\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rdi, rax\nmov eax, [rbp+var_2C]\nsub eax, 1\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov esi, 10h\nmov edx, 0\ndiv rsi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11D9:\ncmp rsp, rdx\njz short loc_11F0\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\njmp short loc_11D9\nloc_11F0:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_121A\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_121A:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov [rbp+var_20], 1\njmp short loc_127A\nloc_1236:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_20]\ncdqe\nshl rax, 2\nlea rcx, [rax-4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\nmov ecx, [rbp+var_20]\nlea esi, [rcx-1]\nmov ecx, edx\nsub ecx, eax\nmov rax, [rbp+var_10]\nmovsxd rdx, esi\nmov [rax+rdx*4], ecx\nadd [rbp+var_20], 1\nloc_127A:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_2C]\njl short loc_1236\nmov [rbp+var_1C], 1\njmp short loc_12AF\nloc_128B:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov edx, [rax+rdx*4]\nmov rax, [rbp+var_10]\nmov eax, [rax]\ncmp edx, eax\njz short loc_12AB\nlea rax, aNonLinearSeque; \"Non Linear Sequence\"\njmp short loc_12C1\nloc_12AB:\nadd [rbp+var_1C], 1\nloc_12AF:\nmov eax, [rbp+var_2C]\nsub eax, 1\ncmp [rbp+var_1C], eax\njl short loc_128B\nlea rax, aLinearSequence; \"Linear Sequence\"\nloc_12C1:\nmov rsp, rdi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12D8\ncall ___stack_chk_fail\nlocret_12D8:\nleave\nretn", + "ida_pseudo": "const char *__fastcall func0(__int64 a1, int a2)\n{\n unsigned __int64 v2; // rax\n void *v3; // rsp\n _BYTE v5[4]; // [rsp+8h] [rbp-30h] BYREF\n int v6; // [rsp+Ch] [rbp-2Ch]\n __int64 v7; // [rsp+10h] [rbp-28h]\n int i; // [rsp+18h] [rbp-20h]\n int j; // [rsp+1Ch] [rbp-1Ch]\n __int64 v10; // [rsp+20h] [rbp-18h]\n _DWORD *v11; // [rsp+28h] [rbp-10h]\n unsigned __int64 v12; // [rsp+30h] [rbp-8h]\n\n v7 = a1;\n v6 = a2;\n v12 = __readfsqword(0x28u);\n v10 = a2 - 1 - 1LL;\n v2 = 16 * ((4LL * (a2 - 1) + 15) / 0x10uLL);\n while ( v5 != &v5[-(v2 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = alloca(v2 & 0xFFF);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)&v5[(v2 & 0xFFF) - 8] = *(_QWORD *)&v5[(v2 & 0xFFF) - 8];\n v11 = v5;\n for ( i = 1; i < v6; ++i )\n v11[i - 1] = *(_DWORD *)(4LL * i + v7) - *(_DWORD *)(4LL * i - 4 + v7);\n for ( j = 1; j < v6 - 1; ++j )\n {\n if ( v11[j] != *v11 )\n return \"Non Linear Sequence\";\n }\n return \"Linear Sequence\";\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rdi, rax\nmov eax, [rbp+var_2C]\nsub eax, 1\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov esi, 10h\nmov edx, 0\ndiv rsi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11D9:\ncmp rsp, rdx\njz short loc_11F0\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\njmp short loc_11D9\nloc_11F0:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_121A\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_121A:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov [rbp+var_20], 1\njmp short loc_127A\nloc_1236:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_20]\ncdqe\nshl rax, 2\nlea rcx, [rax-4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\nmov ecx, [rbp+var_20]\nlea esi, [rcx-1]\nmov ecx, edx\nsub ecx, eax\nmov rax, [rbp+var_10]\nmovsxd rdx, esi\nmov [rax+rdx*4], ecx\nadd [rbp+var_20], 1\nloc_127A:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_2C]\njl short loc_1236\nmov [rbp+var_1C], 1\njmp short loc_12AF\nloc_128B:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov edx, [rax+rdx*4]\nmov rax, [rbp+var_10]\nmov eax, [rax]\ncmp edx, eax\njz short loc_12AB\nlea rax, aNonLinearSeque; \"Non Linear Sequence\"\njmp short loc_12C1\nloc_12AB:\nadd [rbp+var_1C], 1\nloc_12AF:\nmov eax, [rbp+var_2C]\nsub eax, 1\ncmp [rbp+var_1C], eax\njl short loc_128B\nlea rax, aLinearSequence; \"Linear Sequence\"\nloc_12C1:\nmov rsp, rdi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12D8\ncall ___stack_chk_fail\nlocret_12D8:\nleave\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned __int64 v2; // rax\n void *v3; // rsp\n _BYTE v5[4]; // [rsp+8h] [rbp-30h] BYREF\n int v6; // [rsp+Ch] [rbp-2Ch]\n __int64 v7; // [rsp+10h] [rbp-28h]\n int i; // [rsp+18h] [rbp-20h]\n int j; // [rsp+1Ch] [rbp-1Ch]\n __int64 v10; // [rsp+20h] [rbp-18h]\n _DWORD *v11; // [rsp+28h] [rbp-10h]\n unsigned __int64 v12; // [rsp+30h] [rbp-8h]\n\n v7 = a1;\n v6 = a2;\n v12 = __readfsqword(0x28u);\n v10 = a2 - 1 - 1LL;\n v2 = 16 * ((4LL * (a2 - 1) + 15) / 0x10uLL);\n while ( v5 != &v5[-(v2 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = alloca(v2 & 0xFFF);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)&v5[(v2 & 0xFFF) - 8] = *(_QWORD *)&v5[(v2 & 0xFFF) - 8];\n v11 = v5;\n for ( i = 1; i < v6; ++i )\n v11[i - 1] = *(_DWORD *)(4LL * i + v7) - *(_DWORD *)(4LL * i - 4 + v7);\n for ( j = 1; j < v6 - 1; ++j )\n {\n if ( v11[j] != *v11 )\n return \"Non Linear Sequence\";\n }\n return \"Linear Sequence\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1169(long long a1, int a2) {\n unsigned long long v2;\n void *v3;\n uint8_t v5[4];\n int v6;\n long long v7;\n int i;\n int j;\n long long v10;\n uint32_t *v11;\n unsigned long long v12;\n v7 = a1;\n v6 = a2;\n v12 = __readfsqword(40u);\n v10 = a2 - 1 - 1LL;\n v2 = 16 * ((4LL * (a2 - 1) + 15) / 16uLL);\n while (v5 != &v5[-(v2 & 18446744073709547520LL)])\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)&v5[(v2 & 4095) - 8] = *(uint64_t *)&v5[(v2 & 4095) - 8];\n v11 = v5;\n for (i = 1; i < v6; ++i)\n v11[i - 1] = *(uint32_t *)(4LL * i + v7) - *(uint32_t *)(4LL * i - 4 + v7);\n for (j = 1; j < v6 - 1; ++j) {\n if (v11[j] != *v11) return \"Non Linear Sequence\";\n }\n return \"Linear Sequence\";\n}", + "ida_pseudo_norm": "const char *func0(long long a1, int a2) {\n unsigned long long v2;\n void *v3;\n uint8_t v5[4];\n int v6;\n long long v7;\n int i;\n int j;\n long long v10;\n uint32_t *v11;\n unsigned long long v12;\n v7 = a1;\n v6 = a2;\n v12 = __readfsqword(40u);\n v10 = a2 - 1 - 1LL;\n v2 = 16 * ((4LL * (a2 - 1) + 15) / 16uLL);\n while (v5 != &v5[-(v2 & 18446744073709547520LL)])\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)&v5[(v2 & 4095) - 8] = *(uint64_t *)&v5[(v2 & 4095) - 8];\n v11 = v5;\n for (i = 1; i < v6; ++i)\n v11[i - 1] = *(uint32_t *)(4LL * i + v7) - *(uint32_t *)(4LL * i - 4 + v7);\n for (j = 1; j < v6 - 1; ++j) {\n if (v11[j] != *v11) return \"Non Linear Sequence\";\n }\n return \"Linear Sequence\";\n}" + }, + { + "index": 552, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "char* func0(int seq_nums[], int n) {\n int diff[n - 1];\n for (int x = 1; x < n; x++) {\n diff[x - 1] = seq_nums[x] - seq_nums[x - 1];\n }\n for (int i = 1; i < n - 1; i++) {\n if (diff[i] != diff[0]) {\n return \"Non Linear Sequence\";\n }\n }\n return \"Linear Sequence\";\n}", + "test": "int main() {\n\n int arr1[] = {0, 2, 4, 6, 8, 10};\n\n int arr2[] = {1, 2, 3};\n\n int arr3[] = {1, 5, 2};\n\n\n\n assert(func0(arr1, 6) == \"Linear Sequence\");\n\n assert(func0(arr2, 3) == \"Linear Sequence\");\n\n assert(func0(arr3, 3) == \"Non Linear Sequence\");\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea -0x1(%rsi),%r10d\nmovslq %r10d,%rax\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffffff0,%rdx\nand $0xfffffffffffff000,%rax\nmov %rsp,%rcx\nsub %rax,%rcx\nmov %rcx,%rax\ncmp %rax,%rsp\nje 11c0 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11a9 \nmov %rdx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 11d6 \norq $0x0,-0x8(%rsp,%rax,1)\nlea 0x3(%rsp),%r9\nmov %r9,%r11\nshr $0x2,%r11\nand $0xfffffffffffffffc,%r9\nmov %r9,%r8\ncmp $0x1,%esi\njle 120d \nlea -0x2(%rsi),%ecx\nmov $0x0,%eax\nmov 0x4(%rdi,%rax,4),%edx\nsub (%rdi,%rax,4),%edx\nmov %edx,(%r8,%rax,4)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rcx,%rdx\njne 11f6 \nlea 0xdf4(%rip),%rax\ncmp $0x1,%r10d\njle 124b \nmov 0x0(,%r11,4),%edx\nlea 0x4(%r9),%rax\nlea -0x3(%rsi),%ecx\nlea 0x8(%r9,%rcx,4),%rcx\ncmp %edx,(%rax)\njne 1244 \nadd $0x4,%rax\ncmp %rcx,%rax\njne 122e \nlea 0xdc6(%rip),%rax\njmp 124b \nlea 0xdb9(%rip),%rax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\njne 125c \nleaveq\nretq\ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov rcx, rdi\nmov r8d, esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea r9d, [rsi-1]\nmovsxd rax, r9d\nlea rax, ds:0Fh[rax*4]\nmov rsi, rax\nand rsi, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11AC:\ncmp rsp, rdx\njz short loc_11C3\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11AC\nloc_11C3:\nmov rax, rsi\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11D9\nor [rsp+rax+10h+var_18], 0\nloc_11D9:\nlea rsi, [rsp+10h+var_D]\nmov r10, rsi\nshr r10, 2\nand rsi, 0FFFFFFFFFFFFFFFCh\ncmp r8d, 1\njle short loc_120B\nlea edi, [r8-1]\nmov eax, 0\nloc_11F8:\nmov edx, [rcx+rax*4+4]\nsub edx, [rcx+rax*4]\nmov [rsi+rax*4], edx\nadd rax, 1\ncmp rax, rdi\njnz short loc_11F8\nloc_120B:\nlea rax, aNonLinearSeque+4; \"Linear Sequence\"\ncmp r9d, 1\njle short loc_124A\nmov edx, ds:dword_0[r10*4]\nlea rax, [rsi+4]\nlea ecx, [r8-3]\nlea rcx, [rsi+rcx*4+8]\nloc_122D:\ncmp [rax], edx\njnz short loc_1243\nadd rax, 4\ncmp rax, rcx\njnz short loc_122D\nlea rax, aNonLinearSeque+4; \"Linear Sequence\"\njmp short loc_124A\nloc_1243:\nlea rax, aNonLinearSeque; \"Non Linear Sequence\"\nloc_124A:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_125B\nleave\nretn\nloc_125B:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(__int64 a1, int a2)\n{\n int v3; // r9d\n __int16 v4; // si\n signed __int64 v5; // rax\n void *v6; // rsp\n __int64 v7; // rax\n const char *result; // rax\n int *v9; // rax\n __int64 v10; // [rsp+0h] [rbp-18h]\n int v11; // [rsp+8h] [rbp-10h] BYREF\n int v12; // [rsp+Ch] [rbp-Ch] BYREF\n unsigned __int64 v13; // [rsp+10h] [rbp-8h] BYREF\n\n v13 = __readfsqword(0x28u);\n v3 = a2 - 1;\n v4 = (4 * (a2 - 1) + 15) & 0xFFF0;\n while ( &v11 != (int *)((char *)&v11 - ((4LL * v3 + 15) & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v5 = v4 & 0xFFF;\n v6 = alloca(v5);\n if ( (v4 & 0xFFF) != 0 )\n *(__int64 *)((char *)&v10 + v5) = *(__int64 *)((char *)&v10 + v5);\n if ( a2 > 1 )\n {\n v7 = 0LL;\n do\n {\n *(&v11 + v7) = *(_DWORD *)(a1 + 4 * v7 + 4) - *(_DWORD *)(a1 + 4 * v7);\n ++v7;\n }\n while ( v7 != a2 - 1 );\n }\n result = \"Linear Sequence\";\n if ( v3 > 1 )\n {\n v9 = &v12;\n while ( *v9 == v11 )\n {\n if ( ++v9 == (int *)((char *)&v13 + 4 * (unsigned int)(a2 - 3)) )\n return \"Linear Sequence\";\n }\n return \"Non Linear Sequence\";\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov rcx, rdi\nmov r8d, esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea r9d, [rsi-1]\nmovsxd rax, r9d\nlea rax, ds:0Fh[rax*4]\nmov rsi, rax\nand rsi, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11AC:\ncmp rsp, rdx\njz short loc_11C3\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11AC\nloc_11C3:\nmov rax, rsi\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11D9\nor [rsp+rax+10h+var_18], 0\nloc_11D9:\nlea rsi, [rsp+10h+var_D]\nmov r10, rsi\nshr r10, 2\nand rsi, 0FFFFFFFFFFFFFFFCh\ncmp r8d, 1\njle short loc_120B\nlea edi, [r8-1]\nmov eax, 0\nloc_11F8:\nmov edx, [rcx+rax*4+4]\nsub edx, [rcx+rax*4]\nmov [rsi+rax*4], edx\nadd rax, 1\ncmp rax, rdi\njnz short loc_11F8\nloc_120B:\nlea rax, aNonLinearSeque+4; \"Linear Sequence\"\ncmp r9d, 1\njle short loc_124A\nmov edx, ds:dword_0[r10*4]\nlea rax, [rsi+4]\nlea ecx, [r8-3]\nlea rcx, [rsi+rcx*4+8]\nloc_122D:\ncmp [rax], edx\njnz short loc_1243\nadd rax, 4\ncmp rax, rcx\njnz short loc_122D\nlea rax, aNonLinearSeque+4; \"Linear Sequence\"\njmp short loc_124A\nloc_1243:\nlea rax, aNonLinearSeque; \"Non Linear Sequence\"\nloc_124A:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_125B\nleave\nretn\nloc_125B:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_1169(__int64 a1, int a2)\n{\n int v3; // r9d\n __int16 v4; // si\n signed __int64 v5; // rax\n void *v6; // rsp\n __int64 v7; // rax\n const char *result; // rax\n int *v9; // rax\n __int64 v10; // [rsp+0h] [rbp-18h]\n int v11; // [rsp+8h] [rbp-10h] BYREF\n int v12; // [rsp+Ch] [rbp-Ch] BYREF\n unsigned __int64 v13; // [rsp+10h] [rbp-8h] BYREF\n\n v13 = __readfsqword(0x28u);\n v3 = a2 - 1;\n v4 = (4 * (a2 - 1) + 15) & 0xFFF0;\n while ( &v11 != (int *)((char *)&v11 - ((4LL * v3 + 15) & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v5 = v4 & 0xFFF;\n v6 = alloca(v5);\n if ( (v4 & 0xFFF) != 0 )\n *(__int64 *)((char *)&v10 + v5) = *(__int64 *)((char *)&v10 + v5);\n if ( a2 > 1 )\n {\n v7 = 0LL;\n do\n {\n *(&v11 + v7) = *(_DWORD *)(a1 + 4 * v7 + 4) - *(_DWORD *)(a1 + 4 * v7);\n ++v7;\n }\n while ( v7 != a2 - 1 );\n }\n result = \"Linear Sequence\";\n if ( v3 > 1 )\n {\n v9 = &v12;\n while ( *v9 == v11 )\n {\n if ( ++v9 == (int *)((char *)&v13 + 4 * (unsigned int)(a2 - 3)) )\n return \"Linear Sequence\";\n }\n return \"Non Linear Sequence\";\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1169(long long a1, int a2) {\n int v3;\n short v4;\n signed long long v5;\n void *v6;\n long long v7;\n const char *result;\n int *v9;\n long long v10;\n int v11;\n int v12;\n unsigned long long v13;\n v13 = __readfsqword(40u);\n v3 = a2 - 1;\n v4 = (4 * (a2 - 1) + 15) & 65520;\n while (&v11 !=\n (int *)((char *)&v11 - ((4LL * v3 + 15) & 18446744073709547520LL)))\n ;\n v5 = v4 & 4095;\n v6 = alloca(v5);\n if ((v4 & 4095) != 0)\n *(long long *)((char *)&v10 + v5) = *(long long *)((char *)&v10 + v5);\n if (a2 > 1) {\n v7 = 0LL;\n do {\n *(&v11 + v7) =\n *(uint32_t *)(a1 + 4 * v7 + 4) - *(uint32_t *)(a1 + 4 * v7);\n ++v7;\n } while (v7 != a2 - 1);\n }\n result = \"Linear Sequence\";\n if (v3 > 1) {\n v9 = &v12;\n while (*v9 == v11) {\n if (++v9 == (int *)((char *)&v13 + 4 * (unsigned int)(a2 - 3)))\n return \"Linear Sequence\";\n }\n return \"Non Linear Sequence\";\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(long long a1, int a2) {\n int v3;\n short v4;\n signed long long v5;\n void *v6;\n long long v7;\n const char *result;\n int *v9;\n long long v10;\n int v11;\n int v12;\n unsigned long long v13;\n v13 = __readfsqword(40u);\n v3 = a2 - 1;\n v4 = (4 * (a2 - 1) + 15) & 65520;\n while (&v11 !=\n (int *)((char *)&v11 - ((4LL * v3 + 15) & 18446744073709547520LL)))\n ;\n v5 = v4 & 4095;\n v6 = alloca(v5);\n if ((v4 & 4095) != 0)\n *(long long *)((char *)&v10 + v5) = *(long long *)((char *)&v10 + v5);\n if (a2 > 1) {\n v7 = 0LL;\n do {\n *(&v11 + v7) =\n *(uint32_t *)(a1 + 4 * v7 + 4) - *(uint32_t *)(a1 + 4 * v7);\n ++v7;\n } while (v7 != a2 - 1);\n }\n result = \"Linear Sequence\";\n if (v3 > 1) {\n v9 = &v12;\n while (*v9 == v11) {\n if (++v9 == (int *)((char *)&v13 + 4 * (unsigned int)(a2 - 3)))\n return \"Linear Sequence\";\n }\n return \"Non Linear Sequence\";\n }\n return result;\n}" + }, + { + "index": 552, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "char* func0(int seq_nums[], int n) {\n int diff[n - 1];\n for (int x = 1; x < n; x++) {\n diff[x - 1] = seq_nums[x] - seq_nums[x - 1];\n }\n for (int i = 1; i < n - 1; i++) {\n if (diff[i] != diff[0]) {\n return \"Non Linear Sequence\";\n }\n }\n return \"Linear Sequence\";\n}", + "test": "int main() {\n\n int arr1[] = {0, 2, 4, 6, 8, 10};\n\n int arr2[] = {1, 2, 3};\n\n int arr3[] = {1, 5, 2};\n\n\n\n assert(func0(arr1, 6) == \"Linear Sequence\");\n\n assert(func0(arr2, 3) == \"Linear Sequence\");\n\n assert(func0(arr3, 3) == \"Non Linear Sequence\");\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nlea -0x1(%rsi),%r9d\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovslq %r9d,%rax\nmov %rsp,%rcx\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rcx\nand $0xfffffffffffffff0,%rdx\nmov %rcx,%rax\ncmp %rax,%rsp\nje 130a \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 12f5 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 13b8 \nlea 0x3(%rsp),%rcx\nmov %rcx,%r10\nand $0xfffffffffffffffc,%rcx\nshr $0x2,%r10\ncmp $0x1,%esi\njle 1356 \nlea -0x2(%rsi),%r8d\nxor %eax,%eax\nnopw 0x0(%rax,%rax,1)\nmov 0x4(%rdi,%rax,4),%edx\nsub (%rdi,%rax,4),%edx\nmov %edx,(%rcx,%rax,4)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rdx,%r8\njne 1340 \nlea 0xcab(%rip),%rax\ncmp $0x1,%r9d\njle 1394 \nsub $0x3,%esi\nlea 0x4(%rcx),%rax\nmov 0x0(,%r10,4),%edx\nlea 0x8(%rcx,%rsi,4),%rcx\njmp 1389 \nnopl 0x0(%rax)\nadd $0x4,%rax\ncmp %rcx,%rax\nje 13a8 \ncmp %edx,(%rax)\nje 1380 \nlea 0xc70(%rip),%rax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\njne 13c3 \nleaveq\nretq\nnopl (%rax)\nlea 0xc59(%rip),%rax\njmp 1394 \nnopl 0x0(%rax)\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 131c \ncallq 1060 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nlea r11d, [rsi-1]\nmov r10d, esi\nmov rbp, rsp\npush rbx\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmovsxd rax, r11d\nmov rcx, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_12EB\nloc_12D6:\nsub rsp, 1000h\nor [rsp+1020h+var_28], 0\ncmp rsp, rcx\njnz short loc_12D6\nloc_12EB:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_13A0\nloc_12FD:\nlea r8, [rsp+1020h+var_101D]\nmov rbx, r8\nand r8, 0FFFFFFFFFFFFFFFCh\nshr rbx, 2\ncmp r10d, 1\njle short loc_1337\nmov edx, [rdi]\nmov r9d, r10d\nmov eax, 1\nnop dword ptr [rax]\nloc_1320:\nmov esi, edx\nmov edx, [rdi+rax*4]\nmov ecx, edx\nsub ecx, esi\nmov [r8+rax*4-4], ecx\nadd rax, 1\ncmp rax, r9\njnz short loc_1320\nloc_1337:\nlea rax, aNonLinearSeque+4; \"Linear Sequence\"\ncmp r11d, 1\njle short loc_1374\nlea ecx, [r10-3]\nmov edx, ds:dword_0[rbx*4]\nlea rax, [r8+4]\nlea rcx, [r8+rcx*4+8]\njmp short loc_1369\nloc_1360:\nadd rax, 4\ncmp rax, rcx\njz short loc_1390\nloc_1369:\ncmp [rax], edx\njz short loc_1360\nlea rax, aNonLinearSeque; \"Non Linear Sequence\"\nloc_1374:\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njnz short loc_13AB\nmov rbx, [rbp+var_8]\nleave\nretn\nloc_1390:\nlea rax, aNonLinearSeque+4; \"Linear Sequence\"\njmp short loc_1374\nloc_13A0:\nor [rsp+rdx+1020h+var_1028], 0\njmp loc_12FD\nloc_13AB:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(int *a1, int a2)\n{\n int v2; // r11d\n __int64 v4; // rdx\n int *v5; // rcx\n __int16 v6; // dx\n signed __int64 v7; // rdx\n void *v8; // rsp\n int v9; // edx\n __int64 i; // rax\n int v11; // esi\n const char *result; // rax\n _BYTE *v13; // rax\n __int64 v14; // [rsp+0h] [rbp-1028h]\n int v15; // [rsp+8h] [rbp-1020h] BYREF\n _BYTE v16[4084]; // [rsp+Ch] [rbp-101Ch] BYREF\n _QWORD v17[3]; // [rsp+1008h] [rbp-20h] BYREF\n\n v2 = a2 - 1;\n v17[1] = __readfsqword(0x28u);\n v4 = 4LL * (a2 - 1) + 15;\n v5 = (int *)((char *)v17 - (v4 & 0xFFFFFFFFFFFFF000LL));\n v6 = v4 & 0xFFF0;\n if ( v17 != (_QWORD *)v5 )\n {\n while ( &v15 != v5 )\n ;\n }\n v7 = v6 & 0xFFF;\n v8 = alloca(v7);\n if ( v7 )\n *(__int64 *)((char *)&v14 + v7) = *(__int64 *)((char *)&v14 + v7);\n if ( a2 > 1 )\n {\n v9 = *a1;\n for ( i = 1LL; i != a2; *(_DWORD *)&v16[4 * i++ - 8] = v9 - v11 )\n {\n v11 = v9;\n v9 = a1[i];\n }\n }\n result = \"Linear Sequence\";\n if ( v2 > 1 )\n {\n v13 = v16;\n do\n {\n if ( *(_DWORD *)v13 != v15 )\n return \"Non Linear Sequence\";\n v13 += 4;\n }\n while ( v13 != &v16[4 * (a2 - 3) + 4] );\n return \"Linear Sequence\";\n }\n return result;\n}", + "ida_strip_asm": "sub_1290:\nendbr64\npush rbp\nlea r11d, [rsi-1]\nmov r10d, esi\nmov rbp, rsp\npush rbx\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmovsxd rax, r11d\nmov rcx, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_12EB\nloc_12D6:\nsub rsp, 1000h\nor [rsp+1020h+var_28], 0\ncmp rsp, rcx\njnz short loc_12D6\nloc_12EB:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_13A0\nloc_12FD:\nlea r8, [rsp+1020h+var_101D]\nmov rbx, r8\nand r8, 0FFFFFFFFFFFFFFFCh\nshr rbx, 2\ncmp r10d, 1\njle short loc_1337\nmov edx, [rdi]\nmov r9d, r10d\nmov eax, 1\nnop dword ptr [rax]\nloc_1320:\nmov esi, edx\nmov edx, [rdi+rax*4]\nmov ecx, edx\nsub ecx, esi\nmov [r8+rax*4-4], ecx\nadd rax, 1\ncmp rax, r9\njnz short loc_1320\nloc_1337:\nlea rax, aNonLinearSeque+4; \"Linear Sequence\"\ncmp r11d, 1\njle short loc_1374\nlea ecx, [r10-3]\nmov edx, ds:dword_0[rbx*4]\nlea rax, [r8+4]\nlea rcx, [r8+rcx*4+8]\njmp short loc_1369\nloc_1360:\nadd rax, 4\ncmp rax, rcx\njz short loc_1390\nloc_1369:\ncmp [rax], edx\njz short loc_1360\nlea rax, aNonLinearSeque; \"Non Linear Sequence\"\nloc_1374:\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njnz short loc_13AB\nmov rbx, [rbp+var_8]\nleave\nretn\nloc_1390:\nlea rax, aNonLinearSeque+4; \"Linear Sequence\"\njmp short loc_1374\nloc_13A0:\nor [rsp+rdx+1020h+var_1028], 0\njmp loc_12FD\nloc_13AB:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_1290(int *a1, int a2)\n{\n int v2; // r11d\n __int64 v4; // rdx\n int *v5; // rcx\n __int16 v6; // dx\n signed __int64 v7; // rdx\n void *v8; // rsp\n int v9; // edx\n __int64 i; // rax\n int v11; // esi\n const char *result; // rax\n _BYTE *v13; // rax\n __int64 v14; // [rsp+0h] [rbp-1028h]\n int v15; // [rsp+8h] [rbp-1020h] BYREF\n _BYTE v16[4084]; // [rsp+Ch] [rbp-101Ch] BYREF\n _QWORD v17[3]; // [rsp+1008h] [rbp-20h] BYREF\n\n v2 = a2 - 1;\n v17[1] = __readfsqword(0x28u);\n v4 = 4LL * (a2 - 1) + 15;\n v5 = (int *)((char *)v17 - (v4 & 0xFFFFFFFFFFFFF000LL));\n v6 = v4 & 0xFFF0;\n if ( v17 != (_QWORD *)v5 )\n {\n while ( &v15 != v5 )\n ;\n }\n v7 = v6 & 0xFFF;\n v8 = alloca(v7);\n if ( v7 )\n *(__int64 *)((char *)&v14 + v7) = *(__int64 *)((char *)&v14 + v7);\n if ( a2 > 1 )\n {\n v9 = *a1;\n for ( i = 1LL; i != a2; *(_DWORD *)&v16[4 * i++ - 8] = v9 - v11 )\n {\n v11 = v9;\n v9 = a1[i];\n }\n }\n result = \"Linear Sequence\";\n if ( v2 > 1 )\n {\n v13 = v16;\n do\n {\n if ( *(_DWORD *)v13 != v15 )\n return \"Non Linear Sequence\";\n v13 += 4;\n }\n while ( v13 != &v16[4 * (a2 - 3) + 4] );\n return \"Linear Sequence\";\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1290(int *a1, int a2) {\n int v2;\n long long v4;\n int *v5;\n short v6;\n signed long long v7;\n void *v8;\n int v9;\n long long i;\n int v11;\n const char *result;\n uint8_t *v13;\n long long v14;\n int v15;\n uint8_t v16[4084];\n uint64_t v17[3];\n v2 = a2 - 1;\n v17[1] = __readfsqword(40u);\n v4 = 4LL * (a2 - 1) + 15;\n v5 = (int *)((char *)v17 - (v4 & 18446744073709547520LL));\n v6 = v4 & 65520;\n if (v17 != (uint64_t *)v5) {\n while (&v15 != v5)\n ;\n }\n v7 = v6 & 4095;\n v8 = alloca(v7);\n if (v7) *(long long *)((char *)&v14 + v7) = *(long long *)((char *)&v14 + v7);\n if (a2 > 1) {\n v9 = *a1;\n for (i = 1LL; i != a2; *(uint32_t *)&v16[4 * i++ - 8] = v9 - v11) {\n v11 = v9;\n v9 = a1[i];\n }\n }\n result = \"Linear Sequence\";\n if (v2 > 1) {\n v13 = v16;\n do {\n if (*(uint32_t *)v13 != v15) return \"Non Linear Sequence\";\n v13 += 4;\n } while (v13 != &v16[4 * (a2 - 3) + 4]);\n return \"Linear Sequence\";\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(int *a1, int a2) {\n int v2;\n long long v4;\n int *v5;\n short v6;\n signed long long v7;\n void *v8;\n int v9;\n long long i;\n int v11;\n const char *result;\n uint8_t *v13;\n long long v14;\n int v15;\n uint8_t v16[4084];\n uint64_t v17[3];\n v2 = a2 - 1;\n v17[1] = __readfsqword(40u);\n v4 = 4LL * (a2 - 1) + 15;\n v5 = (int *)((char *)v17 - (v4 & 18446744073709547520LL));\n v6 = v4 & 65520;\n if (v17 != (uint64_t *)v5) {\n while (&v15 != v5)\n ;\n }\n v7 = v6 & 4095;\n v8 = alloca(v7);\n if (v7) *(long long *)((char *)&v14 + v7) = *(long long *)((char *)&v14 + v7);\n if (a2 > 1) {\n v9 = *a1;\n for (i = 1LL; i != a2; *(uint32_t *)&v16[4 * i++ - 8] = v9 - v11) {\n v11 = v9;\n v9 = a1[i];\n }\n }\n result = \"Linear Sequence\";\n if (v2 > 1) {\n v13 = v16;\n do {\n if (*(uint32_t *)v13 != v15) return \"Non Linear Sequence\";\n v13 += 4;\n } while (v13 != &v16[4 * (a2 - 3) + 4]);\n return \"Linear Sequence\";\n }\n return result;\n}" + }, + { + "index": 552, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "char* func0(int seq_nums[], int n) {\n int diff[n - 1];\n for (int x = 1; x < n; x++) {\n diff[x - 1] = seq_nums[x] - seq_nums[x - 1];\n }\n for (int i = 1; i < n - 1; i++) {\n if (diff[i] != diff[0]) {\n return \"Non Linear Sequence\";\n }\n }\n return \"Linear Sequence\";\n}", + "test": "int main() {\n\n int arr1[] = {0, 2, 4, 6, 8, 10};\n\n int arr2[] = {1, 2, 3};\n\n int arr3[] = {1, 5, 2};\n\n\n\n assert(func0(arr1, 6) == \"Linear Sequence\");\n\n assert(func0(arr2, 3) == \"Linear Sequence\");\n\n assert(func0(arr3, 3) == \"Non Linear Sequence\");\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nlea -0x1(%rsi),%r8d\nmov %rsp,%rbp\npush %r14\npush %rbx\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmovslq %r8d,%rax\nmov %rsp,%rbx\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rbx\nand $0xfffffffffffffff0,%rdx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 12fd \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 12e8 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 14d0 \nlea 0x3(%rsp),%rdx\nmov %rdx,%r9\nand $0xfffffffffffffffc,%rdx\nshr $0x2,%r9\ncmp $0x1,%esi\njle 1435 \nlea -0x2(%rsi),%eax\ncmp $0x2,%eax\njbe 14db \nmov %r8d,%ecx\nxor %eax,%eax\nshr $0x2,%ecx\nshl $0x4,%rcx\nmovdqu 0x4(%rdi,%rax,1),%xmm0\nmovdqu (%rdi,%rax,1),%xmm1\npsubd %xmm1,%xmm0\nmovups %xmm0,(%rdx,%rax,1)\nadd $0x10,%rax\ncmp %rax,%rcx\njne 1340 \nmov %r8d,%eax\nand $0xfffffffc,%eax\nlea 0x1(%rax),%ecx\ncmp %eax,%r8d\nje 1435 \nmovslq %ecx,%rax\nlea 0x1(%rcx),%r11d\nshl $0x2,%rax\nlea (%rdi,%rax,1),%r10\ncmp %r8d,%r11d\njge 14e5 \ncmp %ecx,%esi\njle 14e5 \nmov (%r10),%ebx\nlea (%rdx,%rax,1),%r11\nmov %ebx,%r14d\nsub -0x4(%r10),%r14d\nmov 0x4(%rdi,%rax,1),%r10d\nmov %r14d,-0x4(%r11)\nmov %r10d,%eax\nsub %ebx,%eax\nmov %eax,(%r11)\nlea 0x3(%rcx),%r11d\nlea 0x2(%rcx),%eax\ncmp %r11d,%r8d\njle 13f2 \ncltq\nmov (%rdi,%rax,4),%r11d\nlea 0x0(,%rax,4),%rbx\nlea (%rdx,%rbx,1),%rax\nmov %r11d,%r14d\nsub %r10d,%r14d\nmov 0x4(%rdi,%rbx,1),%r10d\nmov %r14d,-0x4(%rax)\nmov %r10d,%ebx\nsub %r11d,%ebx\nlea 0x5(%rcx),%r11d\nmov %ebx,(%rax)\nlea 0x4(%rcx),%eax\ncmp %r11d,%r8d\njg 14a0 \nmovslq %eax,%r11\nlea -0x1(%rax),%ecx\nmovslq %ecx,%rcx\nmov (%rdi,%r11,4),%r10d\nsub -0x4(%rdi,%r11,4),%r10d\nmov %r10d,(%rdx,%rcx,4)\nlea 0x1(%rax),%ecx\ncmp %ecx,%esi\njle 1435 \nmovslq %ecx,%rcx\nadd $0x2,%eax\nmov (%rdi,%rcx,4),%r10d\nsub -0x4(%rdi,%rcx,4),%r10d\nmov %r10d,(%rdx,%r11,4)\ncmp %eax,%esi\njle 1435 \ncltq\nmov (%rdi,%rax,4),%r10d\nsub -0x4(%rdi,%rax,4),%r10d\nmov %r10d,(%rdx,%rcx,4)\nlea 0xbcc(%rip),%rax\ncmp $0x1,%r8d\njle 1474 \nsub $0x3,%esi\nlea 0x4(%rdx),%rax\nmov 0x0(,%r9,4),%ecx\nlea 0x8(%rdx,%rsi,4),%rdx\njmp 1469 \nnopl 0x0(%rax,%rax,1)\nadd $0x4,%rax\ncmp %rax,%rdx\nje 1490 \ncmp %ecx,(%rax)\nje 1460 \nlea 0xb90(%rip),%rax\nmov -0x18(%rbp),%rbx\nxor %fs:0x28,%rbx\njne 14ec \nlea -0x10(%rbp),%rsp\npop %rbx\npop %r14\npop %rbp\nretq\nnopl 0x0(%rax)\nlea 0xb71(%rip),%rax\njmp 1474 \nnopl 0x0(%rax)\nmovslq %eax,%r11\nmov (%rdi,%r11,4),%ebx\nlea 0x0(,%r11,4),%rax\nlea (%rdx,%rax,1),%r11\nmov 0x4(%rdi,%rax,1),%eax\nmov %ebx,%r14d\nsub %ebx,%eax\nsub %r10d,%r14d\nmov %eax,(%r11)\nlea 0x6(%rcx),%eax\nmov %r14d,-0x4(%r11)\njmpq 13f2 \nxchg %ax,%ax\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 130f \nmov $0x1,%ecx\njmpq 136e \nmov %ecx,%eax\njmpq 13f2 \ncallq 1060 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nlea r9d, [rsi-1]\nmov r8d, esi\nmov rdx, rdi\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmovsxd rax, r9d\nmov rsi, rsp\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rsi, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rsi\njz short loc_12ED\nloc_12D8:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rsi\njnz short loc_12D8\nloc_12ED:\nand ecx, 0FFFh\nsub rsp, rcx\ntest rcx, rcx\njnz loc_1408\nloc_12FF:\nlea rsi, [rsp+1010h+var_100D]\nmov r10, rsi\nand rsi, 0FFFFFFFFFFFFFFFCh\nshr r10, 2\ncmp r8d, 1\njle loc_13B1\nlea eax, [r8-2]\ncmp eax, 2\njbe loc_1413\nmov ecx, r9d\nxor eax, eax\nshr ecx, 2\nshl rcx, 4\nnop word ptr [rax+rax+00h]\nloc_1338:\nmovdqu xmm0, xmmword ptr [rdx+rax+4]\nmovdqu xmm2, xmmword ptr [rdx+rax]\npsubd xmm0, xmm2\nmovups xmmword ptr [rsi+rax], xmm0\nadd rax, 10h\ncmp rcx, rax\njnz short loc_1338\nmov edi, r9d\nand edi, 0FFFFFFFCh\nlea eax, [rdi+1]\ntest r9b, 3\njz short loc_13B7\nloc_1363:\nmov r11d, r8d\nsub r11d, edi\nlea ecx, [r11-1]\ncmp r11d, 2\njz short loc_139F\nlea r11d, [rdi+1]\nlea rdi, ds:0[r11*4]\nmovq xmm0, qword ptr [rdx+r11*4]\nmovq xmm1, qword ptr [rdx+rdi-4]\npsubd xmm0, xmm1\nmovq qword ptr [rsi+rdi-4], xmm0\ntest cl, 1\njz short loc_13B1\nand ecx, 0FFFFFFFEh\nadd eax, ecx\nloc_139F:\nmovsxd rdi, eax\nsub eax, 1\nmov ecx, [rdx+rdi*4]\ncdqe\nsub ecx, [rdx+rdi*4-4]\nmov [rsi+rax*4], ecx\nloc_13B1:\ncmp r9d, 1\njle short loc_13F8\nloc_13B7:\nlea ecx, [r8-3]\nmov edx, ds:dword_0[r10*4]\nlea rax, [rsi+4]\nlea rcx, [rsi+rcx*4+8]\njmp short loc_13D9\nloc_13D0:\nadd rax, 4\ncmp rax, rcx\njz short loc_13F8\nloc_13D9:\ncmp [rax], edx\njz short loc_13D0\nlea rax, aNonLinearSeque; \"Non Linear Sequence\"\nloc_13E4:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_141F\nleave\nretn\nloc_13F8:\nlea rax, aNonLinearSeque+4; \"Linear Sequence\"\njmp short loc_13E4\nloc_1408:\nor [rsp+rcx+1010h+var_1018], 0\njmp loc_12FF\nloc_1413:\nxor edi, edi\nmov eax, 1\njmp loc_1363\nloc_141F:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(__int64 a1, int a2)\n{\n int v2; // r9d\n __int64 v5; // rcx\n int *v6; // rsi\n __int16 v7; // cx\n signed __int64 v8; // rcx\n void *v9; // rsp\n __int64 v10; // rax\n unsigned int v11; // edi\n signed int v12; // eax\n int v13; // ecx\n _BYTE *v14; // rax\n __int64 v16; // [rsp+0h] [rbp-1018h]\n int v17; // [rsp+8h] [rbp-1010h] BYREF\n _BYTE v18[4084]; // [rsp+Ch] [rbp-100Ch] BYREF\n _QWORD v19[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v2 = a2 - 1;\n v19[1] = __readfsqword(0x28u);\n v5 = 4LL * (a2 - 1) + 15;\n v6 = (int *)((char *)v19 - (v5 & 0xFFFFFFFFFFFFF000LL));\n v7 = v5 & 0xFFF0;\n if ( v19 != (_QWORD *)v6 )\n {\n while ( &v17 != v6 )\n ;\n }\n v8 = v7 & 0xFFF;\n v9 = alloca(v8);\n if ( v8 )\n *(__int64 *)((char *)&v16 + v8) = *(__int64 *)((char *)&v16 + v8);\n if ( a2 > 1 )\n {\n if ( (unsigned int)(a2 - 2) <= 2 )\n {\n v11 = 0;\n v12 = 1;\n }\n else\n {\n v10 = 0LL;\n do\n {\n *(__m128i *)&v18[v10 - 4] = _mm_sub_epi32(\n _mm_loadu_si128((const __m128i *)(a1 + v10 + 4)),\n _mm_loadu_si128((const __m128i *)(a1 + v10)));\n v10 += 16LL;\n }\n while ( 16LL * ((unsigned int)v2 >> 2) != v10 );\n v11 = v2 & 0xFFFFFFFC;\n v12 = (v2 & 0xFFFFFFFC) + 1;\n if ( (v2 & 3) == 0 )\n goto LABEL_15;\n }\n v13 = a2 - v11 - 1;\n if ( a2 - v11 != 2 )\n {\n *(_QWORD *)&v18[4 * v11 - 4] = _mm_sub_epi32(\n _mm_loadl_epi64((const __m128i *)(a1 + 4LL * (v11 + 1))),\n _mm_loadl_epi64((const __m128i *)(a1 + 4LL * (v11 + 1) - 4))).m128i_u64[0];\n if ( (v13 & 1) == 0 )\n goto LABEL_14;\n v12 += v13 & 0xFFFFFFFE;\n }\n *(&v17 + v12 - 1) = *(_DWORD *)(a1 + 4LL * v12) - *(_DWORD *)(a1 + 4LL * v12 - 4);\n }\nLABEL_14:\n if ( v2 <= 1 )\n return \"Linear Sequence\";\nLABEL_15:\n v14 = v18;\n while ( *(_DWORD *)v14 == v17 )\n {\n v14 += 4;\n if ( v14 == &v18[4 * (a2 - 3) + 4] )\n return \"Linear Sequence\";\n }\n return \"Non Linear Sequence\";\n}", + "ida_strip_asm": "sub_1290:\nendbr64\npush rbp\nlea r9d, [rsi-1]\nmov r8d, esi\nmov rdx, rdi\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmovsxd rax, r9d\nmov rsi, rsp\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rsi, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rsi\njz short loc_12ED\nloc_12D8:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rsi\njnz short loc_12D8\nloc_12ED:\nand ecx, 0FFFh\nsub rsp, rcx\ntest rcx, rcx\njnz loc_1408\nloc_12FF:\nlea rsi, [rsp+1010h+var_100D]\nmov r10, rsi\nand rsi, 0FFFFFFFFFFFFFFFCh\nshr r10, 2\ncmp r8d, 1\njle loc_13B1\nlea eax, [r8-2]\ncmp eax, 2\njbe loc_1413\nmov ecx, r9d\nxor eax, eax\nshr ecx, 2\nshl rcx, 4\nnop word ptr [rax+rax+00h]\nloc_1338:\nmovdqu xmm0, xmmword ptr [rdx+rax+4]\nmovdqu xmm2, xmmword ptr [rdx+rax]\npsubd xmm0, xmm2\nmovups xmmword ptr [rsi+rax], xmm0\nadd rax, 10h\ncmp rcx, rax\njnz short loc_1338\nmov edi, r9d\nand edi, 0FFFFFFFCh\nlea eax, [rdi+1]\ntest r9b, 3\njz short loc_13B7\nloc_1363:\nmov r11d, r8d\nsub r11d, edi\nlea ecx, [r11-1]\ncmp r11d, 2\njz short loc_139F\nlea r11d, [rdi+1]\nlea rdi, ds:0[r11*4]\nmovq xmm0, qword ptr [rdx+r11*4]\nmovq xmm1, qword ptr [rdx+rdi-4]\npsubd xmm0, xmm1\nmovq qword ptr [rsi+rdi-4], xmm0\ntest cl, 1\njz short loc_13B1\nand ecx, 0FFFFFFFEh\nadd eax, ecx\nloc_139F:\nmovsxd rdi, eax\nsub eax, 1\nmov ecx, [rdx+rdi*4]\ncdqe\nsub ecx, [rdx+rdi*4-4]\nmov [rsi+rax*4], ecx\nloc_13B1:\ncmp r9d, 1\njle short loc_13F8\nloc_13B7:\nlea ecx, [r8-3]\nmov edx, ds:dword_0[r10*4]\nlea rax, [rsi+4]\nlea rcx, [rsi+rcx*4+8]\njmp short loc_13D9\nloc_13D0:\nadd rax, 4\ncmp rax, rcx\njz short loc_13F8\nloc_13D9:\ncmp [rax], edx\njz short loc_13D0\nlea rax, aNonLinearSeque; \"Non Linear Sequence\"\nloc_13E4:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_141F\nleave\nretn\nloc_13F8:\nlea rax, aNonLinearSeque+4; \"Linear Sequence\"\njmp short loc_13E4\nloc_1408:\nor [rsp+rcx+1010h+var_1018], 0\njmp loc_12FF\nloc_1413:\nxor edi, edi\nmov eax, 1\njmp loc_1363\nloc_141F:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_1290(__int64 a1, int a2)\n{\n int v2; // r9d\n __int64 v5; // rcx\n int *v6; // rsi\n __int16 v7; // cx\n signed __int64 v8; // rcx\n void *v9; // rsp\n __int64 v10; // rax\n unsigned int v11; // edi\n signed int v12; // eax\n int v13; // ecx\n _BYTE *v14; // rax\n __int64 v16; // [rsp+0h] [rbp-1018h]\n int v17; // [rsp+8h] [rbp-1010h] BYREF\n _BYTE v18[4084]; // [rsp+Ch] [rbp-100Ch] BYREF\n _QWORD v19[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v2 = a2 - 1;\n v19[1] = __readfsqword(0x28u);\n v5 = 4LL * (a2 - 1) + 15;\n v6 = (int *)((char *)v19 - (v5 & 0xFFFFFFFFFFFFF000LL));\n v7 = v5 & 0xFFF0;\n if ( v19 != (_QWORD *)v6 )\n {\n while ( &v17 != v6 )\n ;\n }\n v8 = v7 & 0xFFF;\n v9 = alloca(v8);\n if ( v8 )\n *(__int64 *)((char *)&v16 + v8) = *(__int64 *)((char *)&v16 + v8);\n if ( a2 > 1 )\n {\n if ( (unsigned int)(a2 - 2) <= 2 )\n {\n v11 = 0;\n v12 = 1;\n }\n else\n {\n v10 = 0LL;\n do\n {\n *(__m128i *)&v18[v10 - 4] = _mm_sub_epi32(\n _mm_loadu_si128((const __m128i *)(a1 + v10 + 4)),\n _mm_loadu_si128((const __m128i *)(a1 + v10)));\n v10 += 16LL;\n }\n while ( 16LL * ((unsigned int)v2 >> 2) != v10 );\n v11 = v2 & 0xFFFFFFFC;\n v12 = (v2 & 0xFFFFFFFC) + 1;\n if ( (v2 & 3) == 0 )\n goto LABEL_15;\n }\n v13 = a2 - v11 - 1;\n if ( a2 - v11 != 2 )\n {\n *(_QWORD *)&v18[4 * v11 - 4] = _mm_sub_epi32(\n _mm_loadl_epi64((const __m128i *)(a1 + 4LL * (v11 + 1))),\n _mm_loadl_epi64((const __m128i *)(a1 + 4LL * (v11 + 1) - 4))).m128i_u64[0];\n if ( (v13 & 1) == 0 )\n goto LABEL_14;\n v12 += v13 & 0xFFFFFFFE;\n }\n *(&v17 + v12 - 1) = *(_DWORD *)(a1 + 4LL * v12) - *(_DWORD *)(a1 + 4LL * v12 - 4);\n }\nLABEL_14:\n if ( v2 <= 1 )\n return \"Linear Sequence\";\nLABEL_15:\n v14 = v18;\n while ( *(_DWORD *)v14 == v17 )\n {\n v14 += 4;\n if ( v14 == &v18[4 * (a2 - 3) + 4] )\n return \"Linear Sequence\";\n }\n return \"Non Linear Sequence\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1290(long long a1, int a2) {\n int v2;\n long long v5;\n int *v6;\n short v7;\n signed long long v8;\n void *v9;\n long long v10;\n unsigned int v11;\n signed int v12;\n int v13;\n uint8_t *v14;\n long long v16;\n int v17;\n uint8_t v18[4084];\n uint64_t v19[2];\n v2 = a2 - 1;\n v19[1] = __readfsqword(40u);\n v5 = 4LL * (a2 - 1) + 15;\n v6 = (int *)((char *)v19 - (v5 & 18446744073709547520LL));\n v7 = v5 & 65520;\n if (v19 != (uint64_t *)v6) {\n while (&v17 != v6)\n ;\n }\n v8 = v7 & 4095;\n v9 = alloca(v8);\n if (v8) *(long long *)((char *)&v16 + v8) = *(long long *)((char *)&v16 + v8);\n if (a2 > 1) {\n if ((unsigned int)(a2 - 2) <= 2) {\n v11 = 0;\n v12 = 1;\n } else {\n v10 = 0LL;\n do {\n *(__m128i *)&v18[v10 - 4] =\n _mm_sub_epi32(_mm_loadu_si128((const __m128i *)(a1 + v10 + 4)),\n _mm_loadu_si128((const __m128i *)(a1 + v10)));\n v10 += 16LL;\n } while (16LL * ((unsigned int)v2 >> 2) != v10);\n v11 = v2 & 4294967292;\n v12 = (v2 & 4294967292) + 1;\n if ((v2 & 3) == 0) goto LABEL_15;\n }\n v13 = a2 - v11 - 1;\n if (a2 - v11 != 2) {\n *(uint64_t *)&v18[4 * v11 - 4] =\n _mm_sub_epi32(\n _mm_loadl_epi64((const __m128i *)(a1 + 4LL * (v11 + 1))),\n _mm_loadl_epi64((const __m128i *)(a1 + 4LL * (v11 + 1) - 4)))\n .m128i_u64[0];\n if ((v13 & 1) == 0) goto LABEL_14;\n v12 += v13 & 4294967294;\n }\n *(&v17 + v12 - 1) =\n *(uint32_t *)(a1 + 4LL * v12) - *(uint32_t *)(a1 + 4LL * v12 - 4);\n }\nLABEL_14:\n if (v2 <= 1) return \"Linear Sequence\";\nLABEL_15:\n v14 = v18;\n while (*(uint32_t *)v14 == v17) {\n v14 += 4;\n if (v14 == &v18[4 * (a2 - 3) + 4]) return \"Linear Sequence\";\n }\n return \"Non Linear Sequence\";\n}", + "ida_pseudo_norm": "const char *func0(long long a1, int a2) {\n int v2;\n long long v5;\n int *v6;\n short v7;\n signed long long v8;\n void *v9;\n long long v10;\n unsigned int v11;\n signed int v12;\n int v13;\n uint8_t *v14;\n long long v16;\n int v17;\n uint8_t v18[4084];\n uint64_t v19[2];\n v2 = a2 - 1;\n v19[1] = __readfsqword(40u);\n v5 = 4LL * (a2 - 1) + 15;\n v6 = (int *)((char *)v19 - (v5 & 18446744073709547520LL));\n v7 = v5 & 65520;\n if (v19 != (uint64_t *)v6) {\n while (&v17 != v6)\n ;\n }\n v8 = v7 & 4095;\n v9 = alloca(v8);\n if (v8) *(long long *)((char *)&v16 + v8) = *(long long *)((char *)&v16 + v8);\n if (a2 > 1) {\n if ((unsigned int)(a2 - 2) <= 2) {\n v11 = 0;\n v12 = 1;\n } else {\n v10 = 0LL;\n do {\n *(__m128i *)&v18[v10 - 4] =\n _mm_sub_epi32(_mm_loadu_si128((const __m128i *)(a1 + v10 + 4)),\n _mm_loadu_si128((const __m128i *)(a1 + v10)));\n v10 += 16LL;\n } while (16LL * ((unsigned int)v2 >> 2) != v10);\n v11 = v2 & 4294967292;\n v12 = (v2 & 4294967292) + 1;\n if ((v2 & 3) == 0) goto LABEL_15;\n }\n v13 = a2 - v11 - 1;\n if (a2 - v11 != 2) {\n *(uint64_t *)&v18[4 * v11 - 4] =\n _mm_sub_epi32(\n _mm_loadl_epi64((const __m128i *)(a1 + 4LL * (v11 + 1))),\n _mm_loadl_epi64((const __m128i *)(a1 + 4LL * (v11 + 1) - 4)))\n .m128i_u64[0];\n if ((v13 & 1) == 0) goto LABEL_14;\n v12 += v13 & 4294967294;\n }\n *(&v17 + v12 - 1) =\n *(uint32_t *)(a1 + 4LL * v12) - *(uint32_t *)(a1 + 4LL * v12 - 4);\n }\nLABEL_14:\n if (v2 <= 1) return \"Linear Sequence\";\nLABEL_15:\n v14 = v18;\n while (*(uint32_t *)v14 == v17) {\n v14 += 4;\n if (v14 == &v18[4 * (a2 - 3) + 4]) return \"Linear Sequence\";\n }\n return \"Non Linear Sequence\";\n}" + }, + { + "index": 553, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "float func0(int a, int b) {\n int digits = 0;\n int temp = b;\n if (temp == 0) {\n digits = 1;\n } else {\n while (temp != 0) {\n digits++;\n temp /= 10;\n }\n }\n return a + b / pow(10, digits);\n}", + "test": "int main() {\n\n assert(func0(4, 56) == 4.56f);\n\n assert(func0(7, 256) == 7.256f);\n\n assert(func0(8, 123) == 8.123f);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmovl $0x0,-0x8(%rbp)\nmov -0x18(%rbp),%eax\nmov %eax,-0x4(%rbp)\ncmpl $0x0,-0x4(%rbp)\njne 11b9 \nmovl $0x1,-0x8(%rbp)\njmp 11bf \naddl $0x1,-0x8(%rbp)\nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nimul $0x66666667,%rdx,%rdx\nshr $0x20,%rdx\nsar $0x2,%edx\nsar $0x1f,%eax\nsub %eax,%edx\nmov %edx,%eax\nmov %eax,-0x4(%rbp)\ncmpl $0x0,-0x4(%rbp)\njne 1197 \ncvtsi2sdl -0x14(%rbp),%xmm3\nmovsd %xmm3,-0x20(%rbp)\ncvtsi2sdl -0x18(%rbp),%xmm2\nmovsd %xmm2,-0x28(%rbp)\ncvtsi2sdl -0x8(%rbp),%xmm0\nmov 0xeb1(%rip),%rax\nmovapd %xmm0,%xmm1\nmovq %rax,%xmm0\ncallq 1060 \nmovsd -0x28(%rbp),%xmm2\ndivsd %xmm0,%xmm2\nmovapd %xmm2,%xmm0\naddsd -0x20(%rbp),%xmm0\ncvtsd2ss %xmm0,%xmm0\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_8], 0\nmov eax, [rbp+var_18]\nmov [rbp+var_4], eax\ncmp [rbp+var_4], 0\njnz short loc_11B9\nmov [rbp+var_8], 1\njmp short loc_11BF\nloc_1197:\nadd [rbp+var_8], 1\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_4], eax\nloc_11B9:\ncmp [rbp+var_4], 0\njnz short loc_1197\nloc_11BF:\npxor xmm2, xmm2\ncvtsi2sd xmm2, [rbp+var_14]\nmovsd [rbp+var_20], xmm2\npxor xmm3, xmm3\ncvtsi2sd xmm3, [rbp+var_18]\nmovsd [rbp+var_28], xmm3\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_8]\nmov rax, cs:x\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\nmovsd xmm1, [rbp+var_28]\ndivsd xmm1, xmm0\nmovsd xmm0, [rbp+var_20]\naddsd xmm0, xmm1\ncvtsd2ss xmm0, xmm0\nleave\nretn", + "ida_pseudo": "float __fastcall func0(int a1, int a2)\n{\n int v3; // [rsp+28h] [rbp-8h]\n int v4; // [rsp+2Ch] [rbp-4h]\n\n v3 = 0;\n v4 = a2;\n if ( a2 )\n {\n while ( v4 )\n {\n ++v3;\n v4 /= 10;\n }\n }\n else\n {\n v3 = 1;\n }\n return (double)a1 + (double)a2 / pow(10.0, (double)v3);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_8], 0\nmov eax, [rbp+var_18]\nmov [rbp+var_4], eax\ncmp [rbp+var_4], 0\njnz short loc_11B9\nmov [rbp+var_8], 1\njmp short loc_11BF\nloc_1197:\nadd [rbp+var_8], 1\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_4], eax\nloc_11B9:\ncmp [rbp+var_4], 0\njnz short loc_1197\nloc_11BF:\npxor xmm2, xmm2\ncvtsi2sd xmm2, [rbp+var_14]\nmovsd [rbp+var_20], xmm2\npxor xmm3, xmm3\ncvtsi2sd xmm3, [rbp+var_18]\nmovsd [rbp+var_28], xmm3\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_8]\nmov rax, cs:x\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\nmovsd xmm1, [rbp+var_28]\ndivsd xmm1, xmm0\nmovsd xmm0, [rbp+var_20]\naddsd xmm0, xmm1\ncvtsd2ss xmm0, xmm0\nleave\nretn", + "ida_strip_pseudo": "float __fastcall sub_1169(int a1, int a2)\n{\n int v3; // [rsp+28h] [rbp-8h]\n int v4; // [rsp+2Ch] [rbp-4h]\n\n v3 = 0;\n v4 = a2;\n if ( a2 )\n {\n while ( v4 )\n {\n ++v3;\n v4 /= 10;\n }\n }\n else\n {\n v3 = 1;\n }\n return (double)a1 + (double)a2 / pow(10.0, (double)v3);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "float sub_1169(int a1, int a2) {\n int v3;\n int v4;\n v3 = 0;\n v4 = a2;\n if (a2) {\n while (v4) {\n ++v3;\n v4 /= 10;\n }\n } else {\n v3 = 1;\n }\n return (double)a1 + (double)a2 / pow(10.0, (double)v3);\n}", + "ida_pseudo_norm": "float func0(int a1, int a2) {\n int v3;\n int v4;\n v3 = 0;\n v4 = a2;\n if (a2) {\n while (v4) {\n ++v3;\n v4 /= 10;\n }\n } else {\n v3 = 1;\n }\n return (double)a1 + (double)a2 / pow(10.0, (double)v3);\n}" + }, + { + "index": 553, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "float func0(int a, int b) {\n int digits = 0;\n int temp = b;\n if (temp == 0) {\n digits = 1;\n } else {\n while (temp != 0) {\n digits++;\n temp /= 10;\n }\n }\n return a + b / pow(10, digits);\n}", + "test": "int main() {\n\n assert(func0(4, 56) == 4.56f);\n\n assert(func0(7, 256) == 7.256f);\n\n assert(func0(8, 123) == 8.123f);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %edi,%ebp\nmov %esi,%ebx\nmov $0x1,%ecx\ntest %esi,%esi\nje 11a1 \nmov %esi,%edx\nmov $0x0,%ecx\nadd $0x1,%ecx\nmovslq %edx,%rax\nimul $0x66666667,%rax,%rax\nsar $0x22,%rax\nsar $0x1f,%edx\nsub %edx,%eax\nmov %eax,%edx\njne 1187 \npxor %xmm1,%xmm1\ncvtsi2sd %ecx,%xmm1\nmovsd 0xedf(%rip),%xmm0\ncallq 1060 \nmovapd %xmm0,%xmm1\npxor %xmm0,%xmm0\ncvtsi2sd %ebx,%xmm0\ndivsd %xmm1,%xmm0\npxor %xmm1,%xmm1\ncvtsi2sd %ebp,%xmm1\naddsd %xmm1,%xmm0\ncvtsd2ss %xmm0,%xmm0\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov ebp, edi\nmov ebx, esi\nmov ecx, 1\ntest esi, esi\njz short loc_11A1\nmov edx, esi\nmov ecx, 0\nloc_1187:\nadd ecx, 1\nmovsxd rax, edx\nimul rax, 66666667h\nsar rax, 22h\nsar edx, 1Fh\nsub eax, edx\nmov edx, eax\njnz short loc_1187\nloc_11A1:\npxor xmm1, xmm1\ncvtsi2sd xmm1, ecx; y\nmovsd xmm0, cs:x; x\ncall _pow\nmovapd xmm1, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, ebx\ndivsd xmm0, xmm1\npxor xmm1, xmm1\ncvtsi2sd xmm1, ebp\naddsd xmm0, xmm1\ncvtsd2ss xmm0, xmm0\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_pseudo": "float __fastcall func0(int a1, int a2)\n{\n int v2; // ecx\n int v3; // edx\n\n v2 = 1;\n if ( a2 )\n {\n v3 = a2;\n v2 = 0;\n do\n {\n ++v2;\n v3 /= 10;\n }\n while ( v3 );\n }\n return (double)a2 / pow(10.0, (double)v2) + (double)a1;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov ebp, edi\nmov ebx, esi\nmov ecx, 1\ntest esi, esi\njz short loc_11A1\nmov edx, esi\nmov ecx, 0\nloc_1187:\nadd ecx, 1\nmovsxd rax, edx\nimul rax, 66666667h\nsar rax, 22h\nsar edx, 1Fh\nsub eax, edx\nmov edx, eax\njnz short loc_1187\nloc_11A1:\npxor xmm1, xmm1\ncvtsi2sd xmm1, ecx; y\nmovsd xmm0, cs:x; x\ncall _pow\nmovapd xmm1, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, ebx\ndivsd xmm0, xmm1\npxor xmm1, xmm1\ncvtsi2sd xmm1, ebp\naddsd xmm0, xmm1\ncvtsd2ss xmm0, xmm0\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "float __fastcall sub_1169(int a1, int a2)\n{\n int v2; // ecx\n int v3; // edx\n\n v2 = 1;\n if ( a2 )\n {\n v3 = a2;\n v2 = 0;\n do\n {\n ++v2;\n v3 /= 10;\n }\n while ( v3 );\n }\n return (double)a2 / pow(10.0, (double)v2) + (double)a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "float sub_1169(int a1, int a2) {\n int v2;\n int v3;\n v2 = 1;\n if (a2) {\n v3 = a2;\n v2 = 0;\n do {\n ++v2;\n v3 /= 10;\n } while (v3);\n }\n return (double)a2 / pow(10.0, (double)v2) + (double)a1;\n}", + "ida_pseudo_norm": "float func0(int a1, int a2) {\n int v2;\n int v3;\n v2 = 1;\n if (a2) {\n v3 = a2;\n v2 = 0;\n do {\n ++v2;\n v3 /= 10;\n } while (v3);\n }\n return (double)a2 / pow(10.0, (double)v2) + (double)a1;\n}" + }, + { + "index": 553, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "float func0(int a, int b) {\n int digits = 0;\n int temp = b;\n if (temp == 0) {\n digits = 1;\n } else {\n while (temp != 0) {\n digits++;\n temp /= 10;\n }\n }\n return a + b / pow(10, digits);\n}", + "test": "int main() {\n\n assert(func0(4, 56) == 4.56f);\n\n assert(func0(7, 256) == 7.256f);\n\n assert(func0(8, 123) == 8.123f);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %edi,%ebp\npush %rbx\nmov %esi,%ebx\nsub $0x8,%rsp\nmovsd 0xe92(%rip),%xmm1\ntest %esi,%esi\nje 11a2 \nmov %esi,%edx\nxor %ecx,%ecx\nxchg %ax,%ax\nmovslq %edx,%rax\nsar $0x1f,%edx\nadd $0x1,%ecx\nimul $0x66666667,%rax,%rax\nsar $0x22,%rax\nsub %edx,%eax\nmov %eax,%edx\njne 1180 \npxor %xmm1,%xmm1\ncvtsi2sd %ecx,%xmm1\nmovsd 0xe66(%rip),%xmm0\ncallq 1050 \nadd $0x8,%rsp\nmovapd %xmm0,%xmm1\npxor %xmm0,%xmm0\ncvtsi2sd %ebx,%xmm0\npop %rbx\ndivsd %xmm1,%xmm0\npxor %xmm1,%xmm1\ncvtsi2sd %ebp,%xmm1\npop %rbp\naddsd %xmm1,%xmm0\ncvtsd2ss %xmm0,%xmm0\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov ebp, edi\npush rbx\nmov ebx, esi\nsub rsp, 8\nmovsd xmm1, cs:qword_2080\ntest esi, esi\njz short loc_1276\nmov edx, esi\nxor r8d, r8d\nnop\nloc_1250:\nmovsxd rax, edx\nmov ecx, edx\nadd r8d, 1\nimul rax, 66666667h\nsar ecx, 1Fh\nsar rax, 22h\nsub eax, ecx\nmov edx, eax\njnz short loc_1250\npxor xmm1, xmm1\ncvtsi2sd xmm1, r8d; y\nloc_1276:\nmovsd xmm0, cs:x; x\ncall _pow\nadd rsp, 8\nmovapd xmm1, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, ebx\npop rbx\ndivsd xmm0, xmm1\npxor xmm1, xmm1\ncvtsi2sd xmm1, ebp\npop rbp\naddsd xmm0, xmm1\ncvtsd2ss xmm0, xmm0\nretn", + "ida_pseudo": "float __fastcall func0(int a1, int a2)\n{\n double v2; // xmm1_8\n int v3; // edx\n int v4; // r8d\n\n v2 = 1.0;\n if ( a2 )\n {\n v3 = a2;\n v4 = 0;\n do\n {\n ++v4;\n v3 /= 10;\n }\n while ( v3 );\n v2 = (double)v4;\n }\n return (double)a2 / pow(10.0, v2) + (double)a1;\n}", + "ida_strip_asm": "sub_1230:\nendbr64\npush rbp\nmov ebp, edi\npush rbx\nmov ebx, esi\nsub rsp, 8\nmovsd xmm1, cs:qword_2080\ntest esi, esi\njz short loc_1276\nmov edx, esi\nxor r8d, r8d\nnop\nloc_1250:\nmovsxd rax, edx\nmov ecx, edx\nadd r8d, 1\nimul rax, 66666667h\nsar ecx, 1Fh\nsar rax, 22h\nsub eax, ecx\nmov edx, eax\njnz short loc_1250\npxor xmm1, xmm1\ncvtsi2sd xmm1, r8d; y\nloc_1276:\nmovsd xmm0, cs:x; x\ncall _pow\nadd rsp, 8\nmovapd xmm1, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, ebx\npop rbx\ndivsd xmm0, xmm1\npxor xmm1, xmm1\ncvtsi2sd xmm1, ebp\npop rbp\naddsd xmm0, xmm1\ncvtsd2ss xmm0, xmm0\nretn", + "ida_strip_pseudo": "float __fastcall sub_1230(int a1, int a2)\n{\n double v2; // xmm1_8\n int v3; // edx\n int v4; // r8d\n\n v2 = 1.0;\n if ( a2 )\n {\n v3 = a2;\n v4 = 0;\n do\n {\n ++v4;\n v3 /= 10;\n }\n while ( v3 );\n v2 = (double)v4;\n }\n return (double)a2 / pow(10.0, v2) + (double)a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "float sub_1230(int a1, int a2) {\n double v2;\n int v3;\n int v4;\n v2 = 1.0;\n if (a2) {\n v3 = a2;\n v4 = 0;\n do {\n ++v4;\n v3 /= 10;\n } while (v3);\n v2 = (double)v4;\n }\n return (double)a2 / pow(10.0, v2) + (double)a1;\n}", + "ida_pseudo_norm": "float func0(int a1, int a2) {\n double v2;\n int v3;\n int v4;\n v2 = 1.0;\n if (a2) {\n v3 = a2;\n v4 = 0;\n do {\n ++v4;\n v3 /= 10;\n } while (v3);\n v2 = (double)v4;\n }\n return (double)a2 / pow(10.0, v2) + (double)a1;\n}" + }, + { + "index": 553, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "float func0(int a, int b) {\n int digits = 0;\n int temp = b;\n if (temp == 0) {\n digits = 1;\n } else {\n while (temp != 0) {\n digits++;\n temp /= 10;\n }\n }\n return a + b / pow(10, digits);\n}", + "test": "int main() {\n\n assert(func0(4, 56) == 4.56f);\n\n assert(func0(7, 256) == 7.256f);\n\n assert(func0(8, 123) == 8.123f);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %edi,%ebp\npush %rbx\nmov %esi,%ebx\nsub $0x8,%rsp\nmovsd 0xe92(%rip),%xmm1\ntest %esi,%esi\nje 11a2 \nmov %esi,%edx\nxor %ecx,%ecx\nxchg %ax,%ax\nmovslq %edx,%rax\nsar $0x1f,%edx\nadd $0x1,%ecx\nimul $0x66666667,%rax,%rax\nsar $0x22,%rax\nsub %edx,%eax\nmov %eax,%edx\njne 1180 \npxor %xmm1,%xmm1\ncvtsi2sd %ecx,%xmm1\nmovsd 0xe66(%rip),%xmm0\ncallq 1050 \nadd $0x8,%rsp\nmovapd %xmm0,%xmm1\npxor %xmm0,%xmm0\ncvtsi2sd %ebx,%xmm0\npop %rbx\ndivsd %xmm1,%xmm0\npxor %xmm1,%xmm1\ncvtsi2sd %ebp,%xmm1\npop %rbp\naddsd %xmm1,%xmm0\ncvtsd2ss %xmm0,%xmm0\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov ebp, edi\npush rbx\nmov ebx, esi\nsub rsp, 8\nmovsd xmm1, cs:qword_2008\ntest esi, esi\njz short loc_11A6\nmov edx, esi\nxor r8d, r8d\nnop\nloc_1180:\nmovsxd rax, edx\nmov ecx, edx\nadd r8d, 1\nimul rax, 66666667h\nsar ecx, 1Fh\nsar rax, 22h\nsub eax, ecx\nmov edx, eax\njnz short loc_1180\npxor xmm1, xmm1\ncvtsi2sd xmm1, r8d; y\nloc_11A6:\nmovsd xmm0, cs:x; x\ncall _pow\nadd rsp, 8\nmovapd xmm1, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, ebx\npop rbx\ndivsd xmm0, xmm1\npxor xmm1, xmm1\ncvtsi2sd xmm1, ebp\npop rbp\naddsd xmm0, xmm1\ncvtsd2ss xmm0, xmm0\nretn", + "ida_pseudo": "float __fastcall func0(int a1, int a2)\n{\n double v2; // xmm1_8\n int v3; // edx\n int v4; // r8d\n\n v2 = 1.0;\n if ( a2 )\n {\n v3 = a2;\n v4 = 0;\n do\n {\n ++v4;\n v3 /= 10;\n }\n while ( v3 );\n v2 = (double)v4;\n }\n return (double)a2 / pow(10.0, v2) + (double)a1;\n}", + "ida_strip_asm": "sub_1160:\nendbr64\npush rbp\nmov ebp, edi\npush rbx\nmov ebx, esi\nsub rsp, 8\nmovsd xmm1, cs:qword_2008\ntest esi, esi\njz short loc_11A6\nmov edx, esi\nxor r8d, r8d\nnop\nloc_1180:\nmovsxd rax, edx\nmov ecx, edx\nadd r8d, 1\nimul rax, 66666667h\nsar ecx, 1Fh\nsar rax, 22h\nsub eax, ecx\nmov edx, eax\njnz short loc_1180\npxor xmm1, xmm1\ncvtsi2sd xmm1, r8d; y\nloc_11A6:\nmovsd xmm0, cs:x; x\ncall _pow\nadd rsp, 8\nmovapd xmm1, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, ebx\npop rbx\ndivsd xmm0, xmm1\npxor xmm1, xmm1\ncvtsi2sd xmm1, ebp\npop rbp\naddsd xmm0, xmm1\ncvtsd2ss xmm0, xmm0\nretn", + "ida_strip_pseudo": "float __fastcall sub_1160(int a1, int a2)\n{\n double v2; // xmm1_8\n int v3; // edx\n int v4; // r8d\n\n v2 = 1.0;\n if ( a2 )\n {\n v3 = a2;\n v4 = 0;\n do\n {\n ++v4;\n v3 /= 10;\n }\n while ( v3 );\n v2 = (double)v4;\n }\n return (double)a2 / pow(10.0, v2) + (double)a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "float sub_1160(int a1, int a2) {\n double v2;\n int v3;\n int v4;\n v2 = 1.0;\n if (a2) {\n v3 = a2;\n v4 = 0;\n do {\n ++v4;\n v3 /= 10;\n } while (v3);\n v2 = (double)v4;\n }\n return (double)a2 / pow(10.0, v2) + (double)a1;\n}", + "ida_pseudo_norm": "float func0(int a1, int a2) {\n double v2;\n int v3;\n int v4;\n v2 = 1.0;\n if (a2) {\n v3 = a2;\n v4 = 0;\n do {\n ++v4;\n v3 /= 10;\n } while (v3);\n v2 = (double)v4;\n }\n return (double)a2 / pow(10.0, v2) + (double)a1;\n}" + }, + { + "index": 554, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int list[], int length, int* odd_length) {\n static int od_li[100];\n int j = 0;\n for (int i = 0; i < length; i++) {\n if (list[i] % 2 != 0) {\n od_li[j++] = list[i];\n }\n }\n *odd_length = j;\n return od_li;\n}", + "test": "int main() {\n\n int list1[] = {1, 2, 3, 4, 5, 6};\n\n int list2[] = {10, 11, 12, 13};\n\n int list3[] = {7, 8, 9, 1};\n\n int length1, length2, length3;\n\n int* res;\n\n\n\n res = func0(list1, 6, &length1);\n\n assert(length1 == 3 && res[0] == 1 && res[1] == 3 && res[2] == 5);\n\n\n\n res = func0(list2, 4, &length2);\n\n assert(length2 == 2 && res[0] == 11 && res[1] == 13);\n\n\n\n res = func0(list3, 4, &length3);\n\n assert(length3 == 3 && res[0] == 7 && res[1] == 9 && res[2] == 1);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 1201 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nand $0x1,%eax\ntest %eax,%eax\nje 11fd \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x8(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x8(%rbp)\nmov (%rcx),%edx\ncltq\nlea 0x0(,%rax,4),%rcx\nlea 0x2e46(%rip),%rax\nmov %edx,(%rcx,%rax,1)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11ac \nmov -0x28(%rbp),%rax\nmov -0x8(%rbp),%edx\nmov %edx,(%rax)\nlea 0x2e27(%rip),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_1201\nloc_11AC:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njz short loc_11FD\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_8]\nlea edx, [rax+1]\nmov [rbp+var_8], edx\nmov edx, [rcx]\ncdqe\nlea rcx, ds:0[rax*4]\nlea rax, od_li_1\nmov [rcx+rax], edx\nloc_11FD:\nadd [rbp+var_4], 1\nloc_1201:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11AC\nmov rax, [rbp+var_28]\nmov edx, [rbp+var_8]\nmov [rax], edx\nlea rax, od_li_1\npop rbp\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, _DWORD *a3)\n{\n int v3; // eax\n int v5; // [rsp+20h] [rbp-8h]\n int i; // [rsp+24h] [rbp-4h]\n\n v5 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( (*(_DWORD *)(4LL * i + a1) & 1) != 0 )\n {\n v3 = v5++;\n od_li_1[v3] = *(_DWORD *)(4LL * i + a1);\n }\n }\n *a3 = v5;\n return od_li_1;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_1201\nloc_11AC:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njz short loc_11FD\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_8]\nlea edx, [rax+1]\nmov [rbp+var_8], edx\nmov edx, [rcx]\ncdqe\nlea rcx, ds:0[rax*4]\nlea rax, unk_4040\nmov [rcx+rax], edx\nloc_11FD:\nadd [rbp+var_4], 1\nloc_1201:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11AC\nmov rax, [rbp+var_28]\nmov edx, [rbp+var_8]\nmov [rax], edx\nlea rax, unk_4040\npop rbp\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1189(__int64 a1, int a2, _DWORD *a3)\n{\n int v3; // eax\n int v5; // [rsp+20h] [rbp-8h]\n int i; // [rsp+24h] [rbp-4h]\n\n v5 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( (*(_DWORD *)(4LL * i + a1) & 1) != 0 )\n {\n v3 = v5++;\n dword_4040[v3] = *(_DWORD *)(4LL * i + a1);\n }\n }\n *a3 = v5;\n return dword_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1189(long long a1, int a2, uint32_t *a3) {\n int v3;\n int v5;\n int i;\n v5 = 0;\n for (i = 0; i < a2; ++i) {\n if ((*(uint32_t *)(4LL * i + a1) & 1) != 0) {\n v3 = v5++;\n dword_4040[v3] = *(uint32_t *)(4LL * i + a1);\n }\n }\n *a3 = v5;\n return dword_4040;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, uint32_t *a3) {\n int v3;\n int v5;\n int i;\n v5 = 0;\n for (i = 0; i < a2; ++i) {\n if ((*(uint32_t *)(4LL * i + a1) & 1) != 0) {\n v3 = v5++;\n od_li_1[v3] = *(uint32_t *)(4LL * i + a1);\n }\n }\n *a3 = v5;\n return od_li_1;\n}" + }, + { + "index": 554, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int list[], int length, int* odd_length) {\n static int od_li[100];\n int j = 0;\n for (int i = 0; i < length; i++) {\n if (list[i] % 2 != 0) {\n od_li[j++] = list[i];\n }\n }\n *odd_length = j;\n return od_li;\n}", + "test": "int main() {\n\n int list1[] = {1, 2, 3, 4, 5, 6};\n\n int list2[] = {10, 11, 12, 13};\n\n int list3[] = {7, 8, 9, 1};\n\n int length1, length2, length3;\n\n int* res;\n\n\n\n res = func0(list1, 6, &length1);\n\n assert(length1 == 3 && res[0] == 1 && res[1] == 3 && res[2] == 5);\n\n\n\n res = func0(list2, 4, &length2);\n\n assert(length2 == 2 && res[0] == 11 && res[1] == 13);\n\n\n\n res = func0(list3, 4, &length3);\n\n assert(length3 == 3 && res[0] == 7 && res[1] == 9 && res[2] == 1);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11c6 \nmov %rdi,%rax\nlea -0x1(%rsi),%ecx\nlea 0x4(%rdi,%rcx,4),%rdi\nmov $0x0,%esi\nlea 0x2e98(%rip),%r9\njmp 11b3 \nadd $0x4,%rax\ncmp %rdi,%rax\nje 11cb \nmov (%rax),%ecx\ntest $0x1,%cl\nje 11aa \nmovslq %esi,%r8\nmov %ecx,(%r9,%r8,4)\nlea 0x1(%rsi),%esi\njmp 11aa \nmov $0x0,%esi\nmov %esi,(%rdx)\nlea 0x2e6c(%rip),%rax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11C5\nmov rax, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*4]\nmov esi, 0\nlea r9, od_li_1\njmp short loc_11B2\nloc_11A9:\nadd rax, 4\ncmp rax, rdi\njz short loc_11CA\nloc_11B2:\nmov ecx, [rax]\ntest cl, 1\njz short loc_11A9\nmovsxd r8, esi\nmov [r9+r8*4], ecx\nlea esi, [rsi+1]\njmp short loc_11A9\nloc_11C5:\nmov esi, 0\nloc_11CA:\nmov [rdx], esi\nlea rax, od_li_1\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(_DWORD *a1, int a2, _DWORD *a3)\n{\n _DWORD *v3; // rax\n _DWORD *v4; // rdi\n int v5; // esi\n\n if ( a2 <= 0 )\n {\n v5 = 0;\n }\n else\n {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n do\n {\n if ( (*v3 & 1) != 0 )\n od_li_1[v5++] = *v3;\n ++v3;\n }\n while ( v3 != v4 );\n }\n *a3 = v5;\n return od_li_1;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\ntest esi, esi\njle short loc_11C5\nmov rax, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*4]\nmov esi, 0\nlea r9, unk_4040\njmp short loc_11B2\nloc_11A9:\nadd rax, 4\ncmp rax, rdi\njz short loc_11CA\nloc_11B2:\nmov ecx, [rax]\ntest cl, 1\njz short loc_11A9\nmovsxd r8, esi\nmov [r9+r8*4], ecx\nlea esi, [rsi+1]\njmp short loc_11A9\nloc_11C5:\nmov esi, 0\nloc_11CA:\nmov [rdx], esi\nlea rax, unk_4040\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1189(_DWORD *a1, int a2, _DWORD *a3)\n{\n _DWORD *v3; // rax\n _DWORD *v4; // rdi\n int v5; // esi\n\n if ( a2 <= 0 )\n {\n v5 = 0;\n }\n else\n {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n do\n {\n if ( (*v3 & 1) != 0 )\n dword_4040[v5++] = *v3;\n ++v3;\n }\n while ( v3 != v4 );\n }\n *a3 = v5;\n return dword_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1189(uint32_t *a1, int a2, uint32_t *a3) {\n uint32_t *v3;\n uint32_t *v4;\n int v5;\n if (a2 <= 0) {\n v5 = 0;\n } else {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n do {\n if ((*v3 & 1) != 0) dword_4040[v5++] = *v3;\n ++v3;\n } while (v3 != v4);\n }\n *a3 = v5;\n return dword_4040;\n}", + "ida_pseudo_norm": "uint32_t *func0(uint32_t *a1, int a2, uint32_t *a3) {\n uint32_t *v3;\n uint32_t *v4;\n int v5;\n if (a2 <= 0) {\n v5 = 0;\n } else {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n do {\n if ((*v3 & 1) != 0) od_li_1[v5++] = *v3;\n ++v3;\n } while (v3 != v4);\n }\n *a3 = v5;\n return od_li_1;\n}" + }, + { + "index": 554, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int list[], int length, int* odd_length) {\n static int od_li[100];\n int j = 0;\n for (int i = 0; i < length; i++) {\n if (list[i] % 2 != 0) {\n od_li[j++] = list[i];\n }\n }\n *odd_length = j;\n return od_li;\n}", + "test": "int main() {\n\n int list1[] = {1, 2, 3, 4, 5, 6};\n\n int list2[] = {10, 11, 12, 13};\n\n int list3[] = {7, 8, 9, 1};\n\n int length1, length2, length3;\n\n int* res;\n\n\n\n res = func0(list1, 6, &length1);\n\n assert(length1 == 3 && res[0] == 1 && res[1] == 3 && res[2] == 5);\n\n\n\n res = func0(list2, 4, &length2);\n\n assert(length2 == 2 && res[0] == 11 && res[1] == 13);\n\n\n\n res = func0(list3, 4, &length3);\n\n assert(length3 == 3 && res[0] == 7 && res[1] == 9 && res[2] == 1);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 13c8 \nlea -0x1(%rsi),%eax\nxor %ecx,%ecx\nlea 0x2cac(%rip),%r9\nlea 0x4(%rdi,%rax,4),%rsi\nnopl 0x0(%rax)\nmov (%rdi),%eax\ntest $0x1,%al\nje 13b0 \nmovslq %ecx,%r8\nadd $0x1,%ecx\nmov %eax,(%r9,%r8,4)\nadd $0x4,%rdi\ncmp %rsi,%rdi\njne 13a0 \nmov %ecx,(%rdx)\nlea 0x2c7e(%rip),%rax\nretq\nnopl 0x0(%rax,%rax,1)\nxor %ecx,%ecx\nlea 0x2c6f(%rip),%rax\nmov %ecx,(%rdx)\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1340\nmovsxd rsi, esi\nxor ecx, ecx\nlea r9, od_li_1\nlea rsi, [rdi+rsi*4]\nnop dword ptr [rax+rax+00000000h]\nloc_1320:\nmov eax, [rdi]\ntest al, 1\njz short loc_1330\nmovsxd r8, ecx\nadd ecx, 1\nmov [r9+r8*4], eax\nloc_1330:\nadd rdi, 4\ncmp rdi, rsi\njnz short loc_1320\nmov [rdx], ecx\nmov rax, r9\nretn\nloc_1340:\nxor ecx, ecx\nlea r9, od_li_1\nmov [rdx], ecx\nmov rax, r9\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(_DWORD *a1, int a2, _DWORD *a3)\n{\n int v3; // ecx\n _DWORD *v4; // rsi\n __int64 v5; // r8\n\n if ( a2 <= 0 )\n {\n *a3 = 0;\n return od_li_1;\n }\n else\n {\n v3 = 0;\n v4 = &a1[a2];\n do\n {\n if ( (*a1 & 1) != 0 )\n {\n v5 = v3++;\n od_li_1[v5] = *a1;\n }\n ++a1;\n }\n while ( a1 != v4 );\n *a3 = v3;\n return od_li_1;\n }\n}", + "ida_strip_asm": "sub_1300:\nendbr64\ntest esi, esi\njle short loc_1340\nmovsxd rsi, esi\nxor ecx, ecx\nlea r9, unk_4040\nlea rsi, [rdi+rsi*4]\nnop dword ptr [rax+rax+00000000h]\nloc_1320:\nmov eax, [rdi]\ntest al, 1\njz short loc_1330\nmovsxd r8, ecx\nadd ecx, 1\nmov [r9+r8*4], eax\nloc_1330:\nadd rdi, 4\ncmp rdi, rsi\njnz short loc_1320\nmov [rdx], ecx\nmov rax, r9\nretn\nloc_1340:\nxor ecx, ecx\nlea r9, unk_4040\nmov [rdx], ecx\nmov rax, r9\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1300(_DWORD *a1, int a2, _DWORD *a3)\n{\n int v3; // ecx\n _DWORD *v4; // rsi\n __int64 v5; // r8\n\n if ( a2 <= 0 )\n {\n *a3 = 0;\n return dword_4040;\n }\n else\n {\n v3 = 0;\n v4 = &a1[a2];\n do\n {\n if ( (*a1 & 1) != 0 )\n {\n v5 = v3++;\n dword_4040[v5] = *a1;\n }\n ++a1;\n }\n while ( a1 != v4 );\n *a3 = v3;\n return dword_4040;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1300(uint32_t *a1, int a2, uint32_t *a3) {\n int v3;\n uint32_t *v4;\n long long v5;\n if (a2 <= 0) {\n *a3 = 0;\n return dword_4040;\n } else {\n v3 = 0;\n v4 = &a1[a2];\n do {\n if ((*a1 & 1) != 0) {\n v5 = v3++;\n dword_4040[v5] = *a1;\n }\n ++a1;\n } while (a1 != v4);\n *a3 = v3;\n return dword_4040;\n }\n}", + "ida_pseudo_norm": "uint32_t *func0(uint32_t *a1, int a2, uint32_t *a3) {\n int v3;\n uint32_t *v4;\n long long v5;\n if (a2 <= 0) {\n *a3 = 0;\n return od_li_1;\n } else {\n v3 = 0;\n v4 = &a1[a2];\n do {\n if ((*a1 & 1) != 0) {\n v5 = v3++;\n od_li_1[v5] = *a1;\n }\n ++a1;\n } while (a1 != v4);\n *a3 = v3;\n return od_li_1;\n }\n}" + }, + { + "index": 555, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int S = (n * (n + 1)) / 2;\n int res = S * (S - 1);\n return res;\n}", + "test": "int main() {\n\n assert(func0(3) == 30);\n\n assert(func0(5) == 210);\n\n assert(func0(2) == 6);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov -0x14(%rbp),%eax\nadd $0x1,%eax\nimul -0x14(%rbp),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nmov %eax,-0x8(%rbp)\nmov -0x8(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x8(%rbp),%eax\nimul %edx,%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov eax, [rbp+var_14]\nadd eax, 1\nimul eax, [rbp+var_14]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_8], eax\nmov eax, [rbp+var_8]\nlea edx, [rax-1]\nmov eax, [rbp+var_8]\nimul eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n return (unsigned int)((a1 * (a1 + 1) / 2 - 1) * (a1 * (a1 + 1) / 2));\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov eax, [rbp+var_14]\nadd eax, 1\nimul eax, [rbp+var_14]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_8], eax\nmov eax, [rbp+var_8]\nlea edx, [rax-1]\nmov eax, [rbp+var_8]\nimul eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n return (unsigned int)((a1 * (a1 + 1) / 2 - 1) * (a1 * (a1 + 1) / 2));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n return (unsigned int)((a1 * (a1 + 1) / 2 - 1) * (a1 * (a1 + 1) / 2));\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n return (unsigned int)((a1 * (a1 + 1) / 2 - 1) * (a1 * (a1 + 1) / 2));\n}" + }, + { + "index": 556, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int A[], int N) {\n int oddPair = 0;\n for (int i = 0; i < N; i++) {\n for (int j = i + 1; j < N; j++) {\n if ((A[i] ^ A[j]) % 2 != 0) {\n oddPair++;\n }\n }\n }\n return oddPair;\n}", + "test": "int main() {\n\n int array1[] = {5, 4, 7, 2, 1};\n\n int array2[] = {7, 2, 8, 1, 0, 5, 11};\n\n int array3[] = {1, 2, 3};\n\n\n\n assert(func0(array1, 5) == 6);\n\n assert(func0(array2, 7) == 12);\n\n assert(func0(array3, 3) == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11dc \nmov -0x8(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x4(%rbp)\njmp 11d0 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\nxor %edx,%eax\nand $0x1,%eax\ntest %eax,%eax\nje 11cc \naddl $0x1,-0xc(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1193 \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1188 \nmov -0xc(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_11DC\nloc_1188:\nmov eax, [rbp+var_8]\nadd eax, 1\nmov [rbp+var_4], eax\njmp short loc_11D0\nloc_1193:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nxor eax, edx\nand eax, 1\ntest eax, eax\njz short loc_11CC\nadd [rbp+var_C], 1\nloc_11CC:\nadd [rbp+var_4], 1\nloc_11D0:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1193\nadd [rbp+var_8], 1\nloc_11DC:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+10h] [rbp-Ch]\n int i; // [rsp+14h] [rbp-8h]\n int j; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( (((unsigned __int8)*(_DWORD *)(4LL * i + a1) ^ (unsigned __int8)*(_DWORD *)(4LL * j + a1)) & 1) != 0 )\n ++v3;\n }\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_11DC\nloc_1188:\nmov eax, [rbp+var_8]\nadd eax, 1\nmov [rbp+var_4], eax\njmp short loc_11D0\nloc_1193:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nxor eax, edx\nand eax, 1\ntest eax, eax\njz short loc_11CC\nadd [rbp+var_C], 1\nloc_11CC:\nadd [rbp+var_4], 1\nloc_11D0:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1193\nadd [rbp+var_8], 1\nloc_11DC:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+10h] [rbp-Ch]\n int i; // [rsp+14h] [rbp-8h]\n int j; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( (((unsigned __int8)*(_DWORD *)(4LL * i + a1) ^ (unsigned __int8)*(_DWORD *)(4LL * j + a1)) & 1) != 0 )\n ++v3;\n }\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n unsigned int v3;\n int i;\n int j;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if ((((unsigned char)*(uint32_t *)(4LL * i + a1) ^\n (unsigned char)*(uint32_t *)(4LL * j + a1)) &\n 1) != 0)\n ++v3;\n }\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n int j;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if ((((unsigned char)*(uint32_t *)(4LL * i + a1) ^\n (unsigned char)*(uint32_t *)(4LL * j + a1)) &\n 1) != 0)\n ++v3;\n }\n }\n return v3;\n}" + }, + { + "index": 556, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int A[], int N) {\n int oddPair = 0;\n for (int i = 0; i < N; i++) {\n for (int j = i + 1; j < N; j++) {\n if ((A[i] ^ A[j]) % 2 != 0) {\n oddPair++;\n }\n }\n }\n return oddPair;\n}", + "test": "int main() {\n\n int array1[] = {5, 4, 7, 2, 1};\n\n int array2[] = {7, 2, 8, 1, 0, 5, 11};\n\n int array3[] = {1, 2, 3};\n\n\n\n assert(func0(array1, 5) == 6);\n\n assert(func0(array2, 7) == 12);\n\n assert(func0(array3, 3) == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11ae \nlea -0x1(%rsi),%r10d\nadd $0x1,%r10\nmov $0x1,%r9d\nmov $0x0,%ecx\ncmp %r10,%r9\nje 11b3 \nmov -0x4(%rdi,%r9,4),%r8d\nmov %r9,%rax\nmov %r8d,%edx\nxor (%rdi,%rax,4),%edx\nand $0x1,%edx\ncmp $0x1,%edx\nsbb $0xffffffff,%ecx\nadd $0x1,%rax\ncmp %eax,%esi\njg 1191 \nadd $0x1,%r9\njmp 1184 \nmov $0x0,%ecx\nmov %ecx,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11B6\nmov r10d, esi\nmovsxd r11, esi\nmov r9d, 1\nmov ecx, 0\njmp short loc_1187\nloc_1184:\nmov r9, rax\nloc_1187:\ncmp r9, r10\njz short loc_11BB\nmov r8d, [rdi+r9*4-4]\nmov rax, r9\nloc_1194:\nmov edx, r8d\nxor edx, [rdi+rax*4]\nand edx, 1\ncmp edx, 1\nsbb ecx, 0FFFFFFFFh\nadd rax, 1\ncmp esi, eax\njg short loc_1194\nlea rax, [r9+1]\ncmp r9, r11\njnz short loc_1184\njmp short loc_11BB\nloc_11B6:\nmov ecx, 0\nloc_11BB:\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // r9\n unsigned int v3; // ecx\n __int64 v4; // rax\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = 1LL;\n v3 = 0;\n while ( v2 != a2 )\n {\n v4 = v2;\n do\n v3 -= (((*(_DWORD *)(a1 + 4 * v4++) ^ *(_DWORD *)(a1 + 4 * v2 - 4)) & 1) == 0) - 1;\n while ( a2 > (int)v4 );\n if ( v2 == a2 )\n break;\n ++v2;\n }\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11B6\nmov r10d, esi\nmovsxd r11, esi\nmov r9d, 1\nmov ecx, 0\njmp short loc_1187\nloc_1184:\nmov r9, rax\nloc_1187:\ncmp r9, r10\njz short loc_11BB\nmov r8d, [rdi+r9*4-4]\nmov rax, r9\nloc_1194:\nmov edx, r8d\nxor edx, [rdi+rax*4]\nand edx, 1\ncmp edx, 1\nsbb ecx, 0FFFFFFFFh\nadd rax, 1\ncmp esi, eax\njg short loc_1194\nlea rax, [r9+1]\ncmp r9, r11\njnz short loc_1184\njmp short loc_11BB\nloc_11B6:\nmov ecx, 0\nloc_11BB:\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n __int64 v2; // r9\n unsigned int v3; // ecx\n __int64 v4; // rax\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = 1LL;\n v3 = 0;\n while ( v2 != a2 )\n {\n v4 = v2;\n do\n v3 -= (((*(_DWORD *)(a1 + 4 * v4++) ^ *(_DWORD *)(a1 + 4 * v2 - 4)) & 1) == 0) - 1;\n while ( a2 > (int)v4 );\n if ( v2 == a2 )\n break;\n ++v2;\n }\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n long long v4;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = 1LL;\n v3 = 0;\n while (v2 != a2) {\n v4 = v2;\n do\n v3 -=\n (((*(uint32_t *)(a1 + 4 * v4++) ^ *(uint32_t *)(a1 + 4 * v2 - 4)) &\n 1) == 0) -\n 1;\n while (a2 > (int)v4);\n if (v2 == a2) break;\n ++v2;\n }\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n long long v4;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = 1LL;\n v3 = 0;\n while (v2 != a2) {\n v4 = v2;\n do\n v3 -=\n (((*(uint32_t *)(a1 + 4 * v4++) ^ *(uint32_t *)(a1 + 4 * v2 - 4)) &\n 1) == 0) -\n 1;\n while (a2 > (int)v4);\n if (v2 == a2) break;\n ++v2;\n }\n }\n return v3;\n}" + }, + { + "index": 556, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int A[], int N) {\n int oddPair = 0;\n for (int i = 0; i < N; i++) {\n for (int j = i + 1; j < N; j++) {\n if ((A[i] ^ A[j]) % 2 != 0) {\n oddPair++;\n }\n }\n }\n return oddPair;\n}", + "test": "int main() {\n\n int array1[] = {5, 4, 7, 2, 1};\n\n int array2[] = {7, 2, 8, 1, 0, 5, 11};\n\n int array3[] = {1, 2, 3};\n\n\n\n assert(func0(array1, 5) == 6);\n\n assert(func0(array2, 7) == 12);\n\n assert(func0(array3, 3) == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 13c4 \nlea -0x1(%rsi),%r10d\nmov $0x1,%r9d\nxor %r8d,%r8d\nadd $0x1,%r10\ncmp %r10,%r9\nje 13c0 \nxchg %ax,%ax\nmov -0x4(%rdi,%r9,4),%ecx\nmov %r9,%rax\nnopl 0x0(%rax,%rax,1)\nmov (%rdi,%rax,4),%edx\nxor %ecx,%edx\nand $0x1,%edx\ncmp $0x1,%edx\nsbb $0xffffffff,%r8d\nadd $0x1,%rax\ncmp %eax,%esi\njg 13a0 \nadd $0x1,%r9\ncmp %r10,%r9\njne 1390 \nmov %r8d,%eax\nretq\nxor %r8d,%r8d\nmov %r8d,%eax\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_12E3\nmov r10d, esi\nmov r9d, 1\nxor ecx, ecx\ncmp esi, 1\njz short loc_12E0\nnop dword ptr [rax+rax+00000000h]\nloc_12B0:\nmov r8d, [rdi+r9*4-4]\nmov rax, r9\nnop dword ptr [rax+rax+00000000h]\nloc_12C0:\nmov edx, [rdi+rax*4]\nxor edx, r8d\nand edx, 1\ncmp edx, 1\nsbb ecx, 0FFFFFFFFh\nadd rax, 1\ncmp esi, eax\njg short loc_12C0\nadd r9, 1\ncmp r9, r10\njnz short loc_12B0\nloc_12E0:\nmov eax, ecx\nretn\nloc_12E3:\nxor ecx, ecx\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // r9\n unsigned int v3; // ecx\n __int64 v4; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 1LL;\n v3 = 0;\n if ( a2 != 1 )\n {\n do\n {\n v4 = v2;\n do\n v3 -= ((((unsigned __int8)*(_DWORD *)(a1 + 4 * v2 - 4) ^ (unsigned __int8)*(_DWORD *)(a1 + 4 * v4++)) & 1) == 0)\n - 1;\n while ( a2 > (int)v4 );\n ++v2;\n }\n while ( v2 != a2 );\n }\n return v3;\n}", + "ida_strip_asm": "sub_1290:\nendbr64\ntest esi, esi\njle short loc_12E3\nmov r10d, esi\nmov r9d, 1\nxor ecx, ecx\ncmp esi, 1\njz short loc_12E0\nnop dword ptr [rax+rax+00000000h]\nloc_12B0:\nmov r8d, [rdi+r9*4-4]\nmov rax, r9\nnop dword ptr [rax+rax+00000000h]\nloc_12C0:\nmov edx, [rdi+rax*4]\nxor edx, r8d\nand edx, 1\ncmp edx, 1\nsbb ecx, 0FFFFFFFFh\nadd rax, 1\ncmp esi, eax\njg short loc_12C0\nadd r9, 1\ncmp r9, r10\njnz short loc_12B0\nloc_12E0:\nmov eax, ecx\nretn\nloc_12E3:\nxor ecx, ecx\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1290(__int64 a1, int a2)\n{\n __int64 v2; // r9\n unsigned int v3; // ecx\n __int64 v4; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 1LL;\n v3 = 0;\n if ( a2 != 1 )\n {\n do\n {\n v4 = v2;\n do\n v3 -= ((((unsigned __int8)*(_DWORD *)(a1 + 4 * v2 - 4) ^ (unsigned __int8)*(_DWORD *)(a1 + 4 * v4++)) & 1) == 0)\n - 1;\n while ( a2 > (int)v4 );\n ++v2;\n }\n while ( v2 != a2 );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1290(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n long long v4;\n if (a2 <= 0) return 0LL;\n v2 = 1LL;\n v3 = 0;\n if (a2 != 1) {\n do {\n v4 = v2;\n do\n v3 -= ((((unsigned char)*(uint32_t *)(a1 + 4 * v2 - 4) ^\n (unsigned char)*(uint32_t *)(a1 + 4 * v4++)) &\n 1) == 0) -\n 1;\n while (a2 > (int)v4);\n ++v2;\n } while (v2 != a2);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n long long v4;\n if (a2 <= 0) return 0LL;\n v2 = 1LL;\n v3 = 0;\n if (a2 != 1) {\n do {\n v4 = v2;\n do\n v3 -= ((((unsigned char)*(uint32_t *)(a1 + 4 * v2 - 4) ^\n (unsigned char)*(uint32_t *)(a1 + 4 * v4++)) &\n 1) == 0) -\n 1;\n while (a2 > (int)v4);\n ++v2;\n } while (v2 != a2);\n }\n return v3;\n}" + }, + { + "index": 557, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* string) {\n static char toggled_string[100];\n strcpy(toggled_string, string);\n for (int i = 0; toggled_string[i] != '\\0'; i++) {\n if (isupper(toggled_string[i])) {\n toggled_string[i] = tolower(toggled_string[i]);\n } else if (islower(toggled_string[i])) {\n toggled_string[i] = toupper(toggled_string[i]);\n }\n }\n return toggled_string;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"Python\"), \"pYTHON\") == 0);\n\n assert(strcmp(func0(\"Pangram\"), \"pANGRAM\") == 0);\n\n assert(strcmp(func0(\"LIttLE\"), \"liTTle\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov -0x18(%rbp),%rax\nmov %rax,%rsi\nlea 0x2e39(%rip),%rdi\ncallq 10a0 \nmovl $0x0,-0x4(%rbp)\njmpq 12d6 \ncallq 10f0 <__ctype_b_loc@plt>\nmov (%rax),%rdx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x2e14(%rip),%rcx\nmovzbl (%rax,%rcx,1),%eax\nmovsbq %al,%rax\nadd %rax,%rax\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x100,%eax\ntest %eax,%eax\nje 1276 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x2deb(%rip),%rdx\nmovzbl (%rax,%rdx,1),%eax\nmovsbl %al,%eax\nmov %eax,%edi\ncallq 10e0 \nmov %eax,%ecx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x2dcf(%rip),%rdx\nmov %cl,(%rax,%rdx,1)\njmp 12d2 \ncallq 10f0 <__ctype_b_loc@plt>\nmov (%rax),%rdx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x2db6(%rip),%rcx\nmovzbl (%rax,%rcx,1),%eax\nmovsbq %al,%rax\nadd %rax,%rax\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x200,%eax\ntest %eax,%eax\nje 12d2 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x2d8d(%rip),%rdx\nmovzbl (%rax,%rdx,1),%eax\nmovsbl %al,%eax\nmov %eax,%edi\ncallq 10b0 \nmov %eax,%ecx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x2d71(%rip),%rdx\nmov %cl,(%rax,%rdx,1)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncltq\nlea 0x2d5e(%rip),%rdx\nmovzbl (%rax,%rdx,1),%eax\ntest %al,%al\njne 1218 \nlea 0x2d4b(%rip),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+src], rdi\nmov rax, [rbp+src]\nmov rsi, rax; src\nlea rax, toggled_string_1\nmov rdi, rax; dest\ncall _strcpy\nmov [rbp+var_4], 0\njmp loc_12D9\nloc_121B:\ncall ___ctype_b_loc\nmov rdx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, toggled_string_1\nmovzx eax, byte ptr [rax+rcx]\nmovsx rax, al\nadd rax, rax\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 100h\ntest eax, eax\njz short loc_1279\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, toggled_string_1\nmovzx eax, byte ptr [rax+rdx]\nmovsx eax, al\nmov edi, eax; c\ncall _tolower\nmov ecx, eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, toggled_string_1\nmov [rax+rdx], cl\njmp short loc_12D5\nloc_1279:\ncall ___ctype_b_loc\nmov rdx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, toggled_string_1\nmovzx eax, byte ptr [rax+rcx]\nmovsx rax, al\nadd rax, rax\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 200h\ntest eax, eax\njz short loc_12D5\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, toggled_string_1\nmovzx eax, byte ptr [rax+rdx]\nmovsx eax, al\nmov edi, eax; c\ncall _toupper\nmov ecx, eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, toggled_string_1\nmov [rax+rdx], cl\nloc_12D5:\nadd [rbp+var_4], 1\nloc_12D9:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, toggled_string_1\nmovzx eax, byte ptr [rax+rdx]\ntest al, al\njnz loc_121B\nlea rax, toggled_string_1\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(const char *a1)\n{\n int i; // [rsp+1Ch] [rbp-4h]\n\n strcpy(toggled_string_1, a1);\n for ( i = 0; toggled_string_1[i]; ++i )\n {\n if ( ((*__ctype_b_loc())[toggled_string_1[i]] & 0x100) != 0 )\n {\n toggled_string_1[i] = tolower(toggled_string_1[i]);\n }\n else if ( ((*__ctype_b_loc())[toggled_string_1[i]] & 0x200) != 0 )\n {\n toggled_string_1[i] = toupper(toggled_string_1[i]);\n }\n }\n return toggled_string_1;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+src], rdi\nmov rax, [rbp+src]\nmov rsi, rax; src\nlea rax, dest\nmov rdi, rax; dest\ncall _strcpy\nmov [rbp+var_4], 0\njmp loc_12D9\nloc_121B:\ncall ___ctype_b_loc\nmov rdx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, dest\nmovzx eax, byte ptr [rax+rcx]\nmovsx rax, al\nadd rax, rax\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 100h\ntest eax, eax\njz short loc_1279\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, dest\nmovzx eax, byte ptr [rax+rdx]\nmovsx eax, al\nmov edi, eax; c\ncall _tolower\nmov ecx, eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, dest\nmov [rax+rdx], cl\njmp short loc_12D5\nloc_1279:\ncall ___ctype_b_loc\nmov rdx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, dest\nmovzx eax, byte ptr [rax+rcx]\nmovsx rax, al\nadd rax, rax\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 200h\ntest eax, eax\njz short loc_12D5\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, dest\nmovzx eax, byte ptr [rax+rdx]\nmovsx eax, al\nmov edi, eax; c\ncall _toupper\nmov ecx, eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, dest\nmov [rax+rdx], cl\nloc_12D5:\nadd [rbp+var_4], 1\nloc_12D9:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, dest\nmovzx eax, byte ptr [rax+rdx]\ntest al, al\njnz loc_121B\nlea rax, dest\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11E9(const char *a1)\n{\n int i; // [rsp+1Ch] [rbp-4h]\n\n strcpy(dest, a1);\n for ( i = 0; dest[i]; ++i )\n {\n if ( ((*__ctype_b_loc())[dest[i]] & 0x100) != 0 )\n {\n dest[i] = tolower(dest[i]);\n }\n else if ( ((*__ctype_b_loc())[dest[i]] & 0x200) != 0 )\n {\n dest[i] = toupper(dest[i]);\n }\n }\n return dest;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11E9(const char *a1) {\n int i;\n strcpy(dest, a1);\n for (i = 0; dest[i]; ++i) {\n if (((*__ctype_b_loc())[dest[i]] & 256) != 0) {\n dest[i] = tolower(dest[i]);\n } else if (((*__ctype_b_loc())[dest[i]] & 512) != 0) {\n dest[i] = toupper(dest[i]);\n }\n }\n return dest;\n}", + "ida_pseudo_norm": "char *func0(const char *a1) {\n int i;\n strcpy(toggled_string_1, a1);\n for (i = 0; toggled_string_1[i]; ++i) {\n if (((*__ctype_b_loc())[toggled_string_1[i]] & 256) != 0) {\n toggled_string_1[i] = tolower(toggled_string_1[i]);\n } else if (((*__ctype_b_loc())[toggled_string_1[i]] & 512) != 0) {\n toggled_string_1[i] = toupper(toggled_string_1[i]);\n }\n }\n return toggled_string_1;\n}" + }, + { + "index": 557, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* string) {\n static char toggled_string[100];\n strcpy(toggled_string, string);\n for (int i = 0; toggled_string[i] != '\\0'; i++) {\n if (isupper(toggled_string[i])) {\n toggled_string[i] = tolower(toggled_string[i]);\n } else if (islower(toggled_string[i])) {\n toggled_string[i] = toupper(toggled_string[i]);\n }\n }\n return toggled_string;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"Python\"), \"pYTHON\") == 0);\n\n assert(strcmp(func0(\"Pangram\"), \"pANGRAM\") == 0);\n\n assert(strcmp(func0(\"LIttLE\"), \"liTTle\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rsi\nmov $0x64,%edx\nlea 0x2e60(%rip),%rdi\ncallq 10b0 <__strcpy_chk@plt>\nmovzbl 0x2e54(%rip),%ebx\ntest %bl,%bl\nje 1241 \ncallq 10d0 <__ctype_b_loc@plt>\nmov %rax,%r12\nlea 0x2e41(%rip),%rbp\njmp 1220 \ntest $0x2,%ah\nje 1214 \ncallq 1090 <__ctype_toupper_loc@plt>\nmov (%rax),%rax\nmov (%rax,%rbx,4),%eax\nmov %al,0x0(%rbp)\nadd $0x1,%rbp\nmovzbl 0x0(%rbp),%ebx\ntest %bl,%bl\nje 1241 \nmovsbq %bl,%rbx\nmov (%r12),%rax\nmovzwl (%rax,%rbx,2),%eax\ntest $0x1,%ah\nje 1201 \ncallq 10c0 <__ctype_tolower_loc@plt>\nmov (%rax),%rax\nmov (%rax,%rbx,4),%eax\nmov %al,0x0(%rbp)\njmp 1214 \nlea 0x2df8(%rip),%rax\npop %rbx\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov rsi, rdi\nmov edx, 64h ; 'd'\nlea rdi, toggled_string_1\ncall ___strcpy_chk\nmovzx ebx, cs:toggled_string_1\ntest bl, bl\njz short loc_1261\ncall ___ctype_b_loc\nmov r12, rax\nlea rbp, toggled_string_1\njmp short loc_1240\nloc_1221:\ntest ah, 2\njz short loc_1234\ncall ___ctype_toupper_loc\nmov rax, [rax]\nmov eax, [rax+rbx*4]\nmov [rbp+0], al\nloc_1234:\nadd rbp, 1\nmovzx ebx, byte ptr [rbp+0]\ntest bl, bl\njz short loc_1261\nloc_1240:\nmovsx rbx, bl\nmov rax, [r12]\nmovzx eax, word ptr [rax+rbx*2]\ntest ah, 1\njz short loc_1221\ncall ___ctype_tolower_loc\nmov rax, [rax]\nmov eax, [rax+rbx*4]\nmov [rbp+0], al\njmp short loc_1234\nloc_1261:\nlea rax, toggled_string_1\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1)\n{\n char v1; // bl\n const unsigned __int16 **v2; // r12\n char *v3; // rbp\n unsigned __int16 v4; // ax\n\n __strcpy_chk(&toggled_string_1, a1, 100LL);\n v1 = toggled_string_1;\n if ( toggled_string_1 )\n {\n v2 = __ctype_b_loc();\n v3 = &toggled_string_1;\n do\n {\n v4 = (*v2)[v1];\n if ( (v4 & 0x100) != 0 )\n {\n *v3 = (*__ctype_tolower_loc())[v1];\n }\n else if ( (v4 & 0x200) != 0 )\n {\n *v3 = (*__ctype_toupper_loc())[v1];\n }\n v1 = *++v3;\n }\n while ( *v3 );\n }\n return &toggled_string_1;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush r12\npush rbp\npush rbx\nmov rsi, rdi\nmov edx, 64h ; 'd'\nlea rdi, byte_4040\ncall ___strcpy_chk\nmovzx ebx, cs:byte_4040\ntest bl, bl\njz short loc_1261\ncall ___ctype_b_loc\nmov r12, rax\nlea rbp, byte_4040\njmp short loc_1240\nloc_1221:\ntest ah, 2\njz short loc_1234\ncall ___ctype_toupper_loc\nmov rax, [rax]\nmov eax, [rax+rbx*4]\nmov [rbp+0], al\nloc_1234:\nadd rbp, 1\nmovzx ebx, byte ptr [rbp+0]\ntest bl, bl\njz short loc_1261\nloc_1240:\nmovsx rbx, bl\nmov rax, [r12]\nmovzx eax, word ptr [rax+rbx*2]\ntest ah, 1\njz short loc_1221\ncall ___ctype_tolower_loc\nmov rax, [rax]\nmov eax, [rax+rbx*4]\nmov [rbp+0], al\njmp short loc_1234\nloc_1261:\nlea rax, byte_4040\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11E9(__int64 a1)\n{\n char v1; // bl\n const unsigned __int16 **v2; // r12\n char *v3; // rbp\n unsigned __int16 v4; // ax\n\n __strcpy_chk(&byte_4040, a1, 100LL);\n v1 = byte_4040;\n if ( byte_4040 )\n {\n v2 = __ctype_b_loc();\n v3 = &byte_4040;\n do\n {\n v4 = (*v2)[v1];\n if ( (v4 & 0x100) != 0 )\n {\n *v3 = (*__ctype_tolower_loc())[v1];\n }\n else if ( (v4 & 0x200) != 0 )\n {\n *v3 = (*__ctype_toupper_loc())[v1];\n }\n v1 = *++v3;\n }\n while ( *v3 );\n }\n return &byte_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11E9(long long a1) {\n char v1;\n const unsigned short **v2;\n char *v3;\n unsigned short v4;\n __strcpy_chk(&byte_4040, a1, 100LL);\n v1 = byte_4040;\n if (byte_4040) {\n v2 = __ctype_b_loc();\n v3 = &byte_4040;\n do {\n v4 = (*v2)[v1];\n if ((v4 & 256) != 0) {\n *v3 = (*__ctype_tolower_loc())[v1];\n } else if ((v4 & 512) != 0) {\n *v3 = (*__ctype_toupper_loc())[v1];\n }\n v1 = *++v3;\n } while (*v3);\n }\n return &byte_4040;\n}", + "ida_pseudo_norm": "char *func0(long long a1) {\n char v1;\n const unsigned short **v2;\n char *v3;\n unsigned short v4;\n __strcpy_chk(&toggled_string_1, a1, 100LL);\n v1 = toggled_string_1;\n if (toggled_string_1) {\n v2 = __ctype_b_loc();\n v3 = &toggled_string_1;\n do {\n v4 = (*v2)[v1];\n if ((v4 & 256) != 0) {\n *v3 = (*__ctype_tolower_loc())[v1];\n } else if ((v4 & 512) != 0) {\n *v3 = (*__ctype_toupper_loc())[v1];\n }\n v1 = *++v3;\n } while (*v3);\n }\n return &toggled_string_1;\n}" + }, + { + "index": 557, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* string) {\n static char toggled_string[100];\n strcpy(toggled_string, string);\n for (int i = 0; toggled_string[i] != '\\0'; i++) {\n if (isupper(toggled_string[i])) {\n toggled_string[i] = tolower(toggled_string[i]);\n } else if (islower(toggled_string[i])) {\n toggled_string[i] = toupper(toggled_string[i]);\n }\n }\n return toggled_string;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"Python\"), \"pYTHON\") == 0);\n\n assert(strcmp(func0(\"Pangram\"), \"pANGRAM\") == 0);\n\n assert(strcmp(func0(\"LIttLE\"), \"liTTle\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %rdi,%rsi\nmov $0x64,%edx\nlea 0x2d7b(%rip),%rdi\npush %rbp\npush %rbx\ncallq 10b0 <__strcpy_chk@plt>\nmovsbq 0x2d6c(%rip),%rbx\ntest %bl,%bl\nje 1338 \ncallq 10d0 <__ctype_b_loc@plt>\nlea 0x2d5c(%rip),%rbp\nmov %rax,%r12\njmp 130b \nnopl 0x0(%rax)\ncallq 10c0 <__ctype_tolower_loc@plt>\nmov (%rax),%rax\nmov (%rax,%rbx,4),%eax\nmov %al,0x0(%rbp)\nmovsbq 0x1(%rbp),%rbx\nadd $0x1,%rbp\ntest %bl,%bl\nje 1338 \nmov (%r12),%rax\nmovzwl (%rax,%rbx,2),%eax\ntest $0x1,%ah\njne 12f0 \ntest $0x2,%ah\nje 12fe \ncallq 1090 <__ctype_toupper_loc@plt>\nadd $0x1,%rbp\nmov (%rax),%rax\nmov (%rax,%rbx,4),%eax\nmov %al,-0x1(%rbp)\nmovsbq 0x0(%rbp),%rbx\ntest %bl,%bl\njne 130b \npop %rbx\nlea 0x2d00(%rip),%rax\npop %rbp\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r13\nmov rsi, rdi\nmov edx, 64h ; 'd'\npush r12\nlea r12, toggled_string_1\npush rbp\nmov rdi, r12\npush rbx\nsub rsp, 8\ncall ___strcpy_chk\nmovsx rbx, cs:toggled_string_1\ntest bl, bl\njz short loc_1348\ncall ___ctype_b_loc\nmov rbp, r12\nmov r13, rax\njmp short loc_131B\nloc_1300:\ncall ___ctype_tolower_loc\nmov rax, [rax]\nmov eax, [rax+rbx*4]\nmov [rbp+0], al\nloc_130E:\nmovsx rbx, byte ptr [rbp+1]\nadd rbp, 1\ntest bl, bl\njz short loc_1348\nloc_131B:\nmov rax, [r13+0]\nmovzx eax, word ptr [rax+rbx*2]\ntest ah, 1\njnz short loc_1300\ntest ah, 2\njz short loc_130E\ncall ___ctype_toupper_loc\nadd rbp, 1\nmov rax, [rax]\nmov eax, [rax+rbx*4]\nmov [rbp-1], al\nmovsx rbx, byte ptr [rbp+0]\ntest bl, bl\njnz short loc_131B\nloc_1348:\nadd rsp, 8\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1)\n{\n __int64 v1; // rbx\n char *v2; // rbp\n const unsigned __int16 **v3; // r13\n unsigned __int16 v4; // ax\n\n __strcpy_chk(&toggled_string_1, a1, 100LL);\n v1 = toggled_string_1;\n if ( toggled_string_1 )\n {\n v2 = &toggled_string_1;\n v3 = __ctype_b_loc();\n do\n {\n while ( 1 )\n {\n v4 = (*v3)[v1];\n if ( (v4 & 0x100) == 0 )\n break;\n *v2 = (*__ctype_tolower_loc())[v1];\nLABEL_4:\n v1 = *++v2;\n if ( !(_BYTE)v1 )\n return &toggled_string_1;\n }\n if ( (v4 & 0x200) == 0 )\n goto LABEL_4;\n *v2++ = (*__ctype_toupper_loc())[v1];\n v1 = *v2;\n }\n while ( (_BYTE)v1 );\n }\n return &toggled_string_1;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\npush r13\nmov rsi, rdi\nmov edx, 64h ; 'd'\npush r12\nlea r12, byte_4040\npush rbp\nmov rdi, r12\npush rbx\nsub rsp, 8\ncall ___strcpy_chk\nmovsx rbx, cs:byte_4040\ntest bl, bl\njz short loc_1348\ncall ___ctype_b_loc\nmov rbp, r12\nmov r13, rax\njmp short loc_131B\nloc_1300:\ncall ___ctype_tolower_loc\nmov rax, [rax]\nmov eax, [rax+rbx*4]\nmov [rbp+0], al\nloc_130E:\nmovsx rbx, byte ptr [rbp+1]\nadd rbp, 1\ntest bl, bl\njz short loc_1348\nloc_131B:\nmov rax, [r13+0]\nmovzx eax, word ptr [rax+rbx*2]\ntest ah, 1\njnz short loc_1300\ntest ah, 2\njz short loc_130E\ncall ___ctype_toupper_loc\nadd rbp, 1\nmov rax, [rax]\nmov eax, [rax+rbx*4]\nmov [rbp-1], al\nmovsx rbx, byte ptr [rbp+0]\ntest bl, bl\njnz short loc_131B\nloc_1348:\nadd rsp, 8\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "char *__fastcall sub_12C0(__int64 a1)\n{\n __int64 v1; // rbx\n char *v2; // rbp\n const unsigned __int16 **v3; // r13\n unsigned __int16 v4; // ax\n\n __strcpy_chk(&byte_4040, a1, 100LL);\n v1 = byte_4040;\n if ( byte_4040 )\n {\n v2 = &byte_4040;\n v3 = __ctype_b_loc();\n do\n {\n while ( 1 )\n {\n v4 = (*v3)[v1];\n if ( (v4 & 0x100) == 0 )\n break;\n *v2 = (*__ctype_tolower_loc())[v1];\nLABEL_4:\n v1 = *++v2;\n if ( !(_BYTE)v1 )\n return &byte_4040;\n }\n if ( (v4 & 0x200) == 0 )\n goto LABEL_4;\n *v2++ = (*__ctype_toupper_loc())[v1];\n v1 = *v2;\n }\n while ( (_BYTE)v1 );\n }\n return &byte_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_12C0(long long a1) {\n long long v1;\n char *v2;\n const unsigned short **v3;\n unsigned short v4;\n __strcpy_chk(&byte_4040, a1, 100LL);\n v1 = byte_4040;\n if (byte_4040) {\n v2 = &byte_4040;\n v3 = __ctype_b_loc();\n do {\n while (1) {\n v4 = (*v3)[v1];\n if ((v4 & 256) == 0) break;\n *v2 = (*__ctype_tolower_loc())[v1];\n LABEL_4:\n v1 = *++v2;\n if (!(uint8_t)v1) return &byte_4040;\n }\n if ((v4 & 512) == 0) goto LABEL_4;\n *v2++ = (*__ctype_toupper_loc())[v1];\n v1 = *v2;\n } while ((uint8_t)v1);\n }\n return &byte_4040;\n}", + "ida_pseudo_norm": "char *func0(long long a1) {\n long long v1;\n char *v2;\n const unsigned short **v3;\n unsigned short v4;\n __strcpy_chk(&toggled_string_1, a1, 100LL);\n v1 = toggled_string_1;\n if (toggled_string_1) {\n v2 = &toggled_string_1;\n v3 = __ctype_b_loc();\n do {\n while (1) {\n v4 = (*v3)[v1];\n if ((v4 & 256) == 0) break;\n *v2 = (*__ctype_tolower_loc())[v1];\n LABEL_4:\n v1 = *++v2;\n if (!(uint8_t)v1) return &toggled_string_1;\n }\n if ((v4 & 512) == 0) goto LABEL_4;\n *v2++ = (*__ctype_toupper_loc())[v1];\n v1 = *v2;\n } while ((uint8_t)v1);\n }\n return &toggled_string_1;\n}" + }, + { + "index": 557, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* string) {\n static char toggled_string[100];\n strcpy(toggled_string, string);\n for (int i = 0; toggled_string[i] != '\\0'; i++) {\n if (isupper(toggled_string[i])) {\n toggled_string[i] = tolower(toggled_string[i]);\n } else if (islower(toggled_string[i])) {\n toggled_string[i] = toupper(toggled_string[i]);\n }\n }\n return toggled_string;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"Python\"), \"pYTHON\") == 0);\n\n assert(strcmp(func0(\"Pangram\"), \"pANGRAM\") == 0);\n\n assert(strcmp(func0(\"LIttLE\"), \"liTTle\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %rdi,%rsi\nmov $0x64,%edx\nlea 0x2d7b(%rip),%rdi\npush %rbp\npush %rbx\ncallq 10b0 <__strcpy_chk@plt>\nmovsbq 0x2d6c(%rip),%rbx\ntest %bl,%bl\nje 1338 \ncallq 10d0 <__ctype_b_loc@plt>\nlea 0x2d5c(%rip),%rbp\nmov %rax,%r12\njmp 130b \nnopl 0x0(%rax)\ncallq 10c0 <__ctype_tolower_loc@plt>\nmov (%rax),%rax\nmov (%rax,%rbx,4),%eax\nmov %al,0x0(%rbp)\nmovsbq 0x1(%rbp),%rbx\nadd $0x1,%rbp\ntest %bl,%bl\nje 1338 \nmov (%r12),%rax\nmovzwl (%rax,%rbx,2),%eax\ntest $0x1,%ah\njne 12f0 \ntest $0x2,%ah\nje 12fe \ncallq 1090 <__ctype_toupper_loc@plt>\nadd $0x1,%rbp\nmov (%rax),%rax\nmov (%rax,%rbx,4),%eax\nmov %al,-0x1(%rbp)\nmovsbq 0x0(%rbp),%rbx\ntest %bl,%bl\njne 130b \npop %rbx\nlea 0x2d00(%rip),%rax\npop %rbp\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r13\nmov rsi, rdi\nmov edx, 64h ; 'd'\npush r12\nlea r12, toggled_string_1\npush rbp\nmov rdi, r12\npush rbx\nsub rsp, 8\ncall ___strcpy_chk\nmovsx rbx, cs:toggled_string_1\ntest bl, bl\njz short loc_1348\ncall ___ctype_b_loc\nmov rbp, r12\nmov r13, rax\njmp short loc_131B\nloc_1300:\ncall ___ctype_tolower_loc\nmov rax, [rax]\nmov eax, [rax+rbx*4]\nmov [rbp+0], al\nloc_130E:\nmovsx rbx, byte ptr [rbp+1]\nadd rbp, 1\ntest bl, bl\njz short loc_1348\nloc_131B:\nmov rax, [r13+0]\nmovzx eax, word ptr [rax+rbx*2]\ntest ah, 1\njnz short loc_1300\ntest ah, 2\njz short loc_130E\ncall ___ctype_toupper_loc\nadd rbp, 1\nmov rax, [rax]\nmov eax, [rax+rbx*4]\nmov [rbp-1], al\nmovsx rbx, byte ptr [rbp+0]\ntest bl, bl\njnz short loc_131B\nloc_1348:\nadd rsp, 8\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1)\n{\n __int64 v1; // rbx\n char *v2; // rbp\n const unsigned __int16 **v3; // r13\n unsigned __int16 v4; // ax\n\n __strcpy_chk(&toggled_string_1, a1, 100LL);\n v1 = toggled_string_1;\n if ( toggled_string_1 )\n {\n v2 = &toggled_string_1;\n v3 = __ctype_b_loc();\n do\n {\n while ( 1 )\n {\n v4 = (*v3)[v1];\n if ( (v4 & 0x100) == 0 )\n break;\n *v2 = (*__ctype_tolower_loc())[v1];\nLABEL_4:\n v1 = *++v2;\n if ( !(_BYTE)v1 )\n return &toggled_string_1;\n }\n if ( (v4 & 0x200) == 0 )\n goto LABEL_4;\n *v2++ = (*__ctype_toupper_loc())[v1];\n v1 = *v2;\n }\n while ( (_BYTE)v1 );\n }\n return &toggled_string_1;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\npush r13\nmov rsi, rdi\nmov edx, 64h ; 'd'\npush r12\nlea r12, byte_4040\npush rbp\nmov rdi, r12\npush rbx\nsub rsp, 8\ncall ___strcpy_chk\nmovsx rbx, cs:byte_4040\ntest bl, bl\njz short loc_1348\ncall ___ctype_b_loc\nmov rbp, r12\nmov r13, rax\njmp short loc_131B\nloc_1300:\ncall ___ctype_tolower_loc\nmov rax, [rax]\nmov eax, [rax+rbx*4]\nmov [rbp+0], al\nloc_130E:\nmovsx rbx, byte ptr [rbp+1]\nadd rbp, 1\ntest bl, bl\njz short loc_1348\nloc_131B:\nmov rax, [r13+0]\nmovzx eax, word ptr [rax+rbx*2]\ntest ah, 1\njnz short loc_1300\ntest ah, 2\njz short loc_130E\ncall ___ctype_toupper_loc\nadd rbp, 1\nmov rax, [rax]\nmov eax, [rax+rbx*4]\nmov [rbp-1], al\nmovsx rbx, byte ptr [rbp+0]\ntest bl, bl\njnz short loc_131B\nloc_1348:\nadd rsp, 8\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "char *__fastcall sub_12C0(__int64 a1)\n{\n __int64 v1; // rbx\n char *v2; // rbp\n const unsigned __int16 **v3; // r13\n unsigned __int16 v4; // ax\n\n __strcpy_chk(&byte_4040, a1, 100LL);\n v1 = byte_4040;\n if ( byte_4040 )\n {\n v2 = &byte_4040;\n v3 = __ctype_b_loc();\n do\n {\n while ( 1 )\n {\n v4 = (*v3)[v1];\n if ( (v4 & 0x100) == 0 )\n break;\n *v2 = (*__ctype_tolower_loc())[v1];\nLABEL_4:\n v1 = *++v2;\n if ( !(_BYTE)v1 )\n return &byte_4040;\n }\n if ( (v4 & 0x200) == 0 )\n goto LABEL_4;\n *v2++ = (*__ctype_toupper_loc())[v1];\n v1 = *v2;\n }\n while ( (_BYTE)v1 );\n }\n return &byte_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_12C0(long long a1) {\n long long v1;\n char *v2;\n const unsigned short **v3;\n unsigned short v4;\n __strcpy_chk(&byte_4040, a1, 100LL);\n v1 = byte_4040;\n if (byte_4040) {\n v2 = &byte_4040;\n v3 = __ctype_b_loc();\n do {\n while (1) {\n v4 = (*v3)[v1];\n if ((v4 & 256) == 0) break;\n *v2 = (*__ctype_tolower_loc())[v1];\n LABEL_4:\n v1 = *++v2;\n if (!(uint8_t)v1) return &byte_4040;\n }\n if ((v4 & 512) == 0) goto LABEL_4;\n *v2++ = (*__ctype_toupper_loc())[v1];\n v1 = *v2;\n } while ((uint8_t)v1);\n }\n return &byte_4040;\n}", + "ida_pseudo_norm": "char *func0(long long a1) {\n long long v1;\n char *v2;\n const unsigned short **v3;\n unsigned short v4;\n __strcpy_chk(&toggled_string_1, a1, 100LL);\n v1 = toggled_string_1;\n if (toggled_string_1) {\n v2 = &toggled_string_1;\n v3 = __ctype_b_loc();\n do {\n while (1) {\n v4 = (*v3)[v1];\n if ((v4 & 256) == 0) break;\n *v2 = (*__ctype_tolower_loc())[v1];\n LABEL_4:\n v1 = *++v2;\n if (!(uint8_t)v1) return &toggled_string_1;\n }\n if ((v4 & 512) == 0) goto LABEL_4;\n *v2++ = (*__ctype_toupper_loc())[v1];\n v1 = *v2;\n } while ((uint8_t)v1);\n }\n return &toggled_string_1;\n}" + }, + { + "index": 558, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n1, int n2) {\n int distance = abs(n1 - n2);\n int sum = 0;\n while (distance > 0) {\n sum += distance % 10;\n distance /= 10;\n }\n return sum;\n}", + "test": "int main() {\n\n assert(func0(1, 2) == 1);\n\n assert(func0(23, 56) == 6);\n\n assert(func0(123, 256) == 7);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov -0x14(%rbp),%eax\nsub -0x18(%rbp),%eax\nmov %eax,%edx\nmov %edx,%eax\nsar $0x1f,%eax\nxor %eax,%edx\nmov %edx,-0x8(%rbp)\nsub %eax,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11c0 \nmov -0x8(%rbp),%ecx\nmovslq %ecx,%rax\nimul $0x66666667,%rax,%rax\nshr $0x20,%rax\nmov %eax,%edx\nsar $0x2,%edx\nmov %ecx,%eax\nsar $0x1f,%eax\nsub %eax,%edx\nmov %edx,%eax\nshl $0x2,%eax\nadd %edx,%eax\nadd %eax,%eax\nsub %eax,%ecx\nmov %ecx,%edx\nadd %edx,-0x4(%rbp)\nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nimul $0x66666667,%rdx,%rdx\nshr $0x20,%rdx\nsar $0x2,%edx\nsar $0x1f,%eax\nsub %eax,%edx\nmov %edx,%eax\nmov %eax,-0x8(%rbp)\ncmpl $0x0,-0x8(%rbp)\njg 1175 \nmov -0x4(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov eax, [rbp+var_14]\nsub eax, [rbp+var_18]\nmov edx, eax\nneg edx\ncmovns eax, edx\nmov [rbp+var_8], eax\nmov [rbp+var_4], 0\njmp short loc_11BB\nloc_1170:\nmov ecx, [rbp+var_8]\nmovsxd rax, ecx\nimul rax, 66666667h\nshr rax, 20h\nmov edx, eax\nsar edx, 2\nmov eax, ecx\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nsub ecx, eax\nmov edx, ecx\nadd [rbp+var_4], edx\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_8], eax\nloc_11BB:\ncmp [rbp+var_8], 0\njg short loc_1170\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n int v2; // eax\n int v4; // [rsp+10h] [rbp-8h]\n unsigned int v5; // [rsp+14h] [rbp-4h]\n\n v2 = a1 - a2;\n if ( a2 - a1 >= 0 )\n v2 = a2 - a1;\n v4 = v2;\n v5 = 0;\n while ( v4 > 0 )\n {\n v5 += v4 % 10;\n v4 /= 10;\n }\n return v5;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov eax, [rbp+var_14]\nsub eax, [rbp+var_18]\nmov edx, eax\nneg edx\ncmovns eax, edx\nmov [rbp+var_8], eax\nmov [rbp+var_4], 0\njmp short loc_11BB\nloc_1170:\nmov ecx, [rbp+var_8]\nmovsxd rax, ecx\nimul rax, 66666667h\nshr rax, 20h\nmov edx, eax\nsar edx, 2\nmov eax, ecx\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nsub ecx, eax\nmov edx, ecx\nadd [rbp+var_4], edx\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_8], eax\nloc_11BB:\ncmp [rbp+var_8], 0\njg short loc_1170\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2)\n{\n int v2; // eax\n int v4; // [rsp+10h] [rbp-8h]\n unsigned int v5; // [rsp+14h] [rbp-4h]\n\n v2 = a1 - a2;\n if ( a2 - a1 >= 0 )\n v2 = a2 - a1;\n v4 = v2;\n v5 = 0;\n while ( v4 > 0 )\n {\n v5 += v4 % 10;\n v4 /= 10;\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2) {\n int v2;\n int v4;\n unsigned int v5;\n v2 = a1 - a2;\n if (a2 - a1 >= 0) v2 = a2 - a1;\n v4 = v2;\n v5 = 0;\n while (v4 > 0) {\n v5 += v4 % 10;\n v4 /= 10;\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n int v2;\n int v4;\n unsigned int v5;\n v2 = a1 - a2;\n if (a2 - a1 >= 0) v2 = a2 - a1;\n v4 = v2;\n v5 = 0;\n while (v4 > 0) {\n v5 += v4 % 10;\n v4 /= 10;\n }\n return v5;\n}" + }, + { + "index": 558, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n1, int n2) {\n int distance = abs(n1 - n2);\n int sum = 0;\n while (distance > 0) {\n sum += distance % 10;\n distance /= 10;\n }\n return sum;\n}", + "test": "int main() {\n\n assert(func0(1, 2) == 1);\n\n assert(func0(23, 56) == 6);\n\n assert(func0(123, 256) == 7);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub %esi,%edi\nmov %edi,%eax\nsar $0x1f,%eax\nxor %eax,%edi\nsub %eax,%edi\ntest %edi,%edi\njle 118d \nmov $0x0,%ecx\nmovslq %edi,%rax\nimul $0x66666667,%rax,%rax\nsar $0x22,%rax\nmov %edi,%edx\nsar $0x1f,%edx\nsub %edx,%eax\nlea (%rax,%rax,4),%edx\nadd %edx,%edx\nmov %edi,%esi\nsub %edx,%esi\nadd %esi,%ecx\nmov %edi,%edx\nmov %eax,%edi\ncmp $0x9,%edx\njg 1161 \nmov %ecx,%eax\nretq\nmov $0x0,%ecx\njmp 118a \n", + "ida_asm": "func0:\nendbr64\nsub edi, esi\nmov edx, edi\nneg edx\ncmovs edx, edi\ntest edx, edx\njle short loc_118B\nmov esi, 0\nloc_115F:\nmovsxd rax, edx\nimul rax, 66666667h\nsar rax, 22h\nmov ecx, edx\nsar ecx, 1Fh\nsub eax, ecx\nlea ecx, [rax+rax*4]\nadd ecx, ecx\nmov edi, edx\nsub edi, ecx\nadd esi, edi\nmov ecx, edx\nmov edx, eax\ncmp ecx, 9\njg short loc_115F\nloc_1188:\nmov eax, esi\nretn\nloc_118B:\nmov esi, 0\njmp short loc_1188", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n int v2; // edi\n int v3; // edx\n unsigned int v4; // esi\n int v5; // ecx\n\n v2 = a1 - a2;\n v3 = -v2;\n if ( v2 > 0 )\n v3 = v2;\n if ( v3 <= 0 )\n {\n return 0;\n }\n else\n {\n v4 = 0;\n do\n {\n v4 += v3 % 10;\n v5 = v3;\n v3 /= 10;\n }\n while ( v5 > 9 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nsub edi, esi\nmov edx, edi\nneg edx\ncmovs edx, edi\ntest edx, edx\njle short loc_118B\nmov esi, 0\nloc_115F:\nmovsxd rax, edx\nimul rax, 66666667h\nsar rax, 22h\nmov ecx, edx\nsar ecx, 1Fh\nsub eax, ecx\nlea ecx, [rax+rax*4]\nadd ecx, ecx\nmov edi, edx\nsub edi, ecx\nadd esi, edi\nmov ecx, edx\nmov edx, eax\ncmp ecx, 9\njg short loc_115F\nloc_1188:\nmov eax, esi\nretn\nloc_118B:\nmov esi, 0\njmp short loc_1188", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2)\n{\n int v2; // edi\n int v3; // edx\n unsigned int v4; // esi\n int v5; // ecx\n\n v2 = a1 - a2;\n v3 = -v2;\n if ( v2 > 0 )\n v3 = v2;\n if ( v3 <= 0 )\n {\n return 0;\n }\n else\n {\n v4 = 0;\n do\n {\n v4 += v3 % 10;\n v5 = v3;\n v3 /= 10;\n }\n while ( v5 > 9 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2) {\n int v2;\n int v3;\n unsigned int v4;\n int v5;\n v2 = a1 - a2;\n v3 = -v2;\n if (v2 > 0) v3 = v2;\n if (v3 <= 0) {\n return 0;\n } else {\n v4 = 0;\n do {\n v4 += v3 % 10;\n v5 = v3;\n v3 /= 10;\n } while (v5 > 9);\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n int v2;\n int v3;\n unsigned int v4;\n int v5;\n v2 = a1 - a2;\n v3 = -v2;\n if (v2 > 0) v3 = v2;\n if (v3 <= 0) {\n return 0;\n } else {\n v4 = 0;\n do {\n v4 += v3 % 10;\n v5 = v3;\n v3 /= 10;\n } while (v5 > 9);\n }\n return v4;\n}" + }, + { + "index": 559, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int a[], int size) {\n int max_so_far = 0;\n int max_ending_here = 0;\n for (int i = 0; i < size; i++) {\n max_ending_here = max_ending_here + a[i];\n if (max_ending_here < 0) {\n max_ending_here = 0;\n } else if (max_so_far < max_ending_here) {\n max_so_far = max_ending_here;\n }\n }\n return max_so_far;\n}", + "test": "int main() {\n\n int arr1[] = {-2, -3, 4, -1, -2, 1, 5, -3};\n\n int arr2[] = {-3, -4, 5, -2, -3, 2, 6, -4};\n\n int arr3[] = {-4, -5, 6, -3, -4, 3, 7, -5};\n\n \n\n assert(func0(arr1, 8) == 7);\n\n assert(func0(arr2, 8) == 8);\n\n assert(func0(arr3, 8) == 10);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11c9 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nadd %eax,-0x8(%rbp)\ncmpl $0x0,-0x8(%rbp)\njns 11b7 \nmovl $0x0,-0x8(%rbp)\njmp 11c5 \nmov -0xc(%rbp),%eax\ncmp -0x8(%rbp),%eax\njge 11c5 \nmov -0x8(%rbp),%eax\nmov %eax,-0xc(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 118f \nmov -0xc(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11C9\nloc_118F:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\ncmp [rbp+var_8], 0\njns short loc_11B7\nmov [rbp+var_8], 0\njmp short loc_11C5\nloc_11B7:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_8]\njge short loc_11C5\nmov eax, [rbp+var_8]\nmov [rbp+var_C], eax\nloc_11C5:\nadd [rbp+var_4], 1\nloc_11C9:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_118F\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int v3; // [rsp+10h] [rbp-Ch]\n int v4; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v4 += *(_DWORD *)(4LL * i + a1);\n if ( v4 >= 0 )\n {\n if ( v3 < v4 )\n v3 = v4;\n }\n else\n {\n v4 = 0;\n }\n }\n return (unsigned int)v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11C9\nloc_118F:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\ncmp [rbp+var_8], 0\njns short loc_11B7\nmov [rbp+var_8], 0\njmp short loc_11C5\nloc_11B7:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_8]\njge short loc_11C5\nmov eax, [rbp+var_8]\nmov [rbp+var_C], eax\nloc_11C5:\nadd [rbp+var_4], 1\nloc_11C9:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_118F\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int v3; // [rsp+10h] [rbp-Ch]\n int v4; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v4 += *(_DWORD *)(4LL * i + a1);\n if ( v4 >= 0 )\n {\n if ( v3 < v4 )\n v3 = v4;\n }\n else\n {\n v4 = 0;\n }\n }\n return (unsigned int)v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int v3;\n int v4;\n int i;\n v3 = 0;\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n v4 += *(uint32_t *)(4LL * i + a1);\n if (v4 >= 0) {\n if (v3 < v4) v3 = v4;\n } else {\n v4 = 0;\n }\n }\n return (unsigned int)v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int v3;\n int v4;\n int i;\n v3 = 0;\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n v4 += *(uint32_t *)(4LL * i + a1);\n if (v4 >= 0) {\n if (v3 < v4) v3 = v4;\n } else {\n v4 = 0;\n }\n }\n return (unsigned int)v3;\n}" + }, + { + "index": 559, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int a[], int size) {\n int max_so_far = 0;\n int max_ending_here = 0;\n for (int i = 0; i < size; i++) {\n max_ending_here = max_ending_here + a[i];\n if (max_ending_here < 0) {\n max_ending_here = 0;\n } else if (max_so_far < max_ending_here) {\n max_so_far = max_ending_here;\n }\n }\n return max_so_far;\n}", + "test": "int main() {\n\n int arr1[] = {-2, -3, 4, -1, -2, 1, 5, -3};\n\n int arr2[] = {-3, -4, 5, -2, -3, 2, 6, -4};\n\n int arr3[] = {-4, -5, 6, -3, -4, 3, 7, -5};\n\n \n\n assert(func0(arr1, 8) == 7);\n\n assert(func0(arr2, 8) == 8);\n\n assert(func0(arr3, 8) == 10);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11a9 \nmov %rdi,%rdx\nlea -0x1(%rsi),%eax\nlea 0x4(%rdi,%rax,4),%rdi\nmov $0x0,%ecx\nmov $0x0,%esi\nmov $0x0,%r8d\njmp 119a \nmov %r8d,%ecx\nadd $0x4,%rdx\ncmp %rdi,%rdx\nje 11ae \nmov %ecx,%eax\nadd (%rdx),%eax\nmov %eax,%ecx\njs 118e \ncmp %eax,%esi\ncmovl %eax,%esi\njmp 1191 \nmov $0x0,%esi\nmov %esi,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11A8\nmov rdx, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*4]\nmov ecx, 0\nmov esi, 0\nmov r8d, 0\njmp short loc_119B\nloc_118D:\ncmp esi, eax\ncmovl esi, eax\nloc_1192:\nadd rdx, 4\ncmp rdx, rdi\njz short loc_11AD\nloc_119B:\nmov eax, ecx\nadd eax, [rdx]\nmov ecx, eax\njns short loc_118D\nmov ecx, r8d\njmp short loc_1192\nloc_11A8:\nmov esi, 0\nloc_11AD:\nmov eax, esi\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rdx\n _DWORD *v3; // rdi\n int v4; // ecx\n unsigned int v5; // esi\n bool v6; // sf\n int v7; // eax\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n v5 = 0;\n do\n {\n v6 = *v2 + v4 < 0;\n v7 = *v2 + v4;\n v4 = v7;\n if ( v6 )\n {\n v4 = 0;\n }\n else if ( (int)v5 < v7 )\n {\n v5 = v7;\n }\n ++v2;\n }\n while ( v2 != v3 );\n }\n return v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11A8\nmov rdx, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*4]\nmov ecx, 0\nmov esi, 0\nmov r8d, 0\njmp short loc_119B\nloc_118D:\ncmp esi, eax\ncmovl esi, eax\nloc_1192:\nadd rdx, 4\ncmp rdx, rdi\njz short loc_11AD\nloc_119B:\nmov eax, ecx\nadd eax, [rdx]\nmov ecx, eax\njns short loc_118D\nmov ecx, r8d\njmp short loc_1192\nloc_11A8:\nmov esi, 0\nloc_11AD:\nmov eax, esi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rdx\n _DWORD *v3; // rdi\n int v4; // ecx\n unsigned int v5; // esi\n bool v6; // sf\n int v7; // eax\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n v5 = 0;\n do\n {\n v6 = *v2 + v4 < 0;\n v7 = *v2 + v4;\n v4 = v7;\n if ( v6 )\n {\n v4 = 0;\n }\n else if ( (int)v5 < v7 )\n {\n v5 = v7;\n }\n ++v2;\n }\n while ( v2 != v3 );\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2) {\n uint32_t *v2;\n uint32_t *v3;\n int v4;\n unsigned int v5;\n bool v6;\n int v7;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n v5 = 0;\n do {\n v6 = *v2 + v4 < 0;\n v7 = *v2 + v4;\n v4 = v7;\n if (v6) {\n v4 = 0;\n } else if ((int)v5 < v7) {\n v5 = v7;\n }\n ++v2;\n } while (v2 != v3);\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n uint32_t *v3;\n int v4;\n unsigned int v5;\n bool v6;\n int v7;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n v5 = 0;\n do {\n v6 = *v2 + v4 < 0;\n v7 = *v2 + v4;\n v4 = v7;\n if (v6) {\n v4 = 0;\n } else if ((int)v5 < v7) {\n v5 = v7;\n }\n ++v2;\n } while (v2 != v3);\n }\n return v5;\n}" + }, + { + "index": 560, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int *elements;\n\n int size;\n\n} UniqueTuple;\n\n\n\n", + "func": "UniqueTuple func0(int *test_tup1, int size1, int *test_tup2, int size2) {\n UniqueTuple result;\n result.elements = (int *)malloc((size1 + size2) * sizeof(int));\n int k = 0;\n for (int i = 0; i < size1; i++) {\n int j;\n for (j = 0; j < k; j++) {\n if (result.elements[j] == test_tup1[i]) break;\n }\n if (j == k) {\n result.elements[k++] = test_tup1[i];\n }\n }\n for (int i = 0; i < size2; i++) {\n int j;\n for (j = 0; j < k; j++) {\n if (result.elements[j] == test_tup2[i]) break;\n }\n if (j == k) {\n result.elements[k++] = test_tup2[i];\n }\n }\n result.size = k;\n return result;\n}", + "test": "int main() {\n\n int tuple1[] = {3, 4, 5, 6};\n\n int tuple2[] = {5, 7, 4, 10};\n\n UniqueTuple res1 = func0(tuple1, 4, tuple2, 4);\n\n int expected1[] = {3, 4, 5, 6, 7, 10};\n\n assert(res1.size == sizeof(expected1) / sizeof(int));\n\n for (int i = 0; i < res1.size; i++) {\n\n assert(res1.elements[i] == expected1[i]);\n\n }\n\n\n\n int tuple3[] = {1, 2, 3, 4};\n\n int tuple4[] = {3, 4, 5, 6};\n\n UniqueTuple res2 = func0(tuple3, 4, tuple4, 4);\n\n int expected2[] = {1, 2, 3, 4, 5, 6};\n\n assert(res2.size == sizeof(expected2) / sizeof(int));\n\n for (int i = 0; i < res2.size; i++) {\n\n assert(res2.elements[i] == expected2[i]);\n\n }\n\n\n\n int tuple5[] = {11, 12, 13, 14};\n\n int tuple6[] = {13, 15, 16, 17};\n\n UniqueTuple res3 = func0(tuple5, 4, tuple6, 4);\n\n int expected3[] = {11, 12, 13, 14, 15, 16, 17};\n\n assert(res3.size == sizeof(expected3) / sizeof(int));\n\n for (int i = 0; i < res3.size; i++) {\n\n assert(res3.elements[i] == expected3[i]);\n\n }\n\n\n\n free(res1.elements);\n\n free(res2.elements);\n\n free(res3.elements);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x50,%rsp\nmov %rdi,-0x38(%rbp)\nmov %esi,-0x3c(%rbp)\nmov %rdx,-0x48(%rbp)\nmov %ecx,-0x40(%rbp)\nmov -0x3c(%rbp),%edx\nmov -0x40(%rbp),%eax\nadd %edx,%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,-0x10(%rbp)\nmovl $0x0,-0x24(%rbp)\nmovl $0x0,-0x20(%rbp)\njmpq 1291 \nmovl $0x0,-0x1c(%rbp)\njmp 124a \nmov -0x10(%rbp),%rax\nmov -0x1c(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x2,%rdx\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x20(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x38(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\nje 1254 \naddl $0x1,-0x1c(%rbp)\nmov -0x1c(%rbp),%eax\ncmp -0x24(%rbp),%eax\njl 1219 \njmp 1255 \nmov -0x1c(%rbp),%eax\ncmp -0x24(%rbp),%eax\njne 128d \nmov -0x20(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x38(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x10(%rbp),%rsi\nmov -0x24(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x24(%rbp)\ncltq\nshl $0x2,%rax\nlea (%rsi,%rax,1),%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x20(%rbp)\nmov -0x20(%rbp),%eax\ncmp -0x3c(%rbp),%eax\njl 1210 \nmovl $0x0,-0x18(%rbp)\njmpq 132a \nmovl $0x0,-0x14(%rbp)\njmp 12e3 \nmov -0x10(%rbp),%rax\nmov -0x14(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x2,%rdx\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x48(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\nje 12ed \naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\ncmp -0x24(%rbp),%eax\njl 12b2 \njmp 12ee \nmov -0x14(%rbp),%eax\ncmp -0x24(%rbp),%eax\njne 1326 \nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x48(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x10(%rbp),%rsi\nmov -0x24(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x24(%rbp)\ncltq\nshl $0x2,%rax\nlea (%rsi,%rax,1),%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%eax\ncmp -0x40(%rbp),%eax\njl 12a9 \nmov -0x24(%rbp),%eax\nmov %eax,-0x8(%rbp)\nmov -0x10(%rbp),%rax\nmov -0x8(%rbp),%rdx\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov [rbp+var_48], rdx\nmov [rbp+var_40], ecx\nmov edx, [rbp+var_3C]\nmov eax, [rbp+var_40]\nadd eax, edx\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_10], rax\nmov [rbp+var_24], 0\nmov [rbp+var_20], 0\njmp loc_1291\nloc_1210:\nmov [rbp+var_1C], 0\njmp short loc_124A\nloc_1219:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_20]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_1254\nadd [rbp+var_1C], 1\nloc_124A:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_24]\njl short loc_1219\njmp short loc_1255\nloc_1254:\nnop\nloc_1255:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_24]\njnz short loc_128D\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nlea rcx, [rdx+rax]\nmov rsi, [rbp+var_10]\nmov eax, [rbp+var_24]\nlea edx, [rax+1]\nmov [rbp+var_24], edx\ncdqe\nshl rax, 2\nlea rdx, [rsi+rax]\nmov eax, [rcx]\nmov [rdx], eax\nloc_128D:\nadd [rbp+var_20], 1\nloc_1291:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_3C]\njl loc_1210\nmov [rbp+var_18], 0\njmp loc_132A\nloc_12A9:\nmov [rbp+var_14], 0\njmp short loc_12E3\nloc_12B2:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_18]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_12ED\nadd [rbp+var_14], 1\nloc_12E3:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_24]\njl short loc_12B2\njmp short loc_12EE\nloc_12ED:\nnop\nloc_12EE:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_24]\njnz short loc_1326\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nlea rcx, [rdx+rax]\nmov rsi, [rbp+var_10]\nmov eax, [rbp+var_24]\nlea edx, [rax+1]\nmov [rbp+var_24], edx\ncdqe\nshl rax, 2\nlea rdx, [rsi+rax]\nmov eax, [rcx]\nmov [rdx], eax\nloc_1326:\nadd [rbp+var_18], 1\nloc_132A:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_40]\njl loc_12A9\nmov eax, [rbp+var_24]\nmov dword ptr [rbp+var_8], eax\nmov rax, [rbp+var_10]\nmov rdx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, __int64 a3, int a4)\n{\n int v4; // eax\n int v5; // eax\n int v9; // [rsp+2Ch] [rbp-24h]\n int i; // [rsp+30h] [rbp-20h]\n int j; // [rsp+34h] [rbp-1Ch]\n int k; // [rsp+38h] [rbp-18h]\n int m; // [rsp+3Ch] [rbp-14h]\n _DWORD *v14; // [rsp+40h] [rbp-10h]\n\n v14 = malloc(4LL * (a2 + a4));\n v9 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = 0; j < v9 && v14[j] != *(_DWORD *)(4LL * i + a1); ++j )\n ;\n if ( j == v9 )\n {\n v4 = v9++;\n v14[v4] = *(_DWORD *)(4LL * i + a1);\n }\n }\n for ( k = 0; k < a4; ++k )\n {\n for ( m = 0; m < v9 && v14[m] != *(_DWORD *)(4LL * k + a3); ++m )\n ;\n if ( m == v9 )\n {\n v5 = v9++;\n v14[v5] = *(_DWORD *)(4LL * k + a3);\n }\n }\n return v14;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov [rbp+var_48], rdx\nmov [rbp+var_40], ecx\nmov edx, [rbp+var_3C]\nmov eax, [rbp+var_40]\nadd eax, edx\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_10], rax\nmov [rbp+var_24], 0\nmov [rbp+var_20], 0\njmp loc_1291\nloc_1210:\nmov [rbp+var_1C], 0\njmp short loc_124A\nloc_1219:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_20]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_1254\nadd [rbp+var_1C], 1\nloc_124A:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_24]\njl short loc_1219\njmp short loc_1255\nloc_1254:\nnop\nloc_1255:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_24]\njnz short loc_128D\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nlea rcx, [rdx+rax]\nmov rsi, [rbp+var_10]\nmov eax, [rbp+var_24]\nlea edx, [rax+1]\nmov [rbp+var_24], edx\ncdqe\nshl rax, 2\nlea rdx, [rsi+rax]\nmov eax, [rcx]\nmov [rdx], eax\nloc_128D:\nadd [rbp+var_20], 1\nloc_1291:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_3C]\njl loc_1210\nmov [rbp+var_18], 0\njmp loc_132A\nloc_12A9:\nmov [rbp+var_14], 0\njmp short loc_12E3\nloc_12B2:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_18]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_12ED\nadd [rbp+var_14], 1\nloc_12E3:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_24]\njl short loc_12B2\njmp short loc_12EE\nloc_12ED:\nnop\nloc_12EE:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_24]\njnz short loc_1326\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nlea rcx, [rdx+rax]\nmov rsi, [rbp+var_10]\nmov eax, [rbp+var_24]\nlea edx, [rax+1]\nmov [rbp+var_24], edx\ncdqe\nshl rax, 2\nlea rdx, [rsi+rax]\nmov eax, [rcx]\nmov [rdx], eax\nloc_1326:\nadd [rbp+var_18], 1\nloc_132A:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_40]\njl loc_12A9\nmov eax, [rbp+var_24]\nmov dword ptr [rbp+var_8], eax\nmov rax, [rbp+var_10]\nmov rdx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11C9(__int64 a1, int a2, __int64 a3, int a4)\n{\n int v4; // eax\n int v5; // eax\n int v9; // [rsp+2Ch] [rbp-24h]\n int i; // [rsp+30h] [rbp-20h]\n int j; // [rsp+34h] [rbp-1Ch]\n int k; // [rsp+38h] [rbp-18h]\n int m; // [rsp+3Ch] [rbp-14h]\n _DWORD *v14; // [rsp+40h] [rbp-10h]\n\n v14 = malloc(4LL * (a2 + a4));\n v9 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = 0; j < v9 && v14[j] != *(_DWORD *)(4LL * i + a1); ++j )\n ;\n if ( j == v9 )\n {\n v4 = v9++;\n v14[v4] = *(_DWORD *)(4LL * i + a1);\n }\n }\n for ( k = 0; k < a4; ++k )\n {\n for ( m = 0; m < v9 && v14[m] != *(_DWORD *)(4LL * k + a3); ++m )\n ;\n if ( m == v9 )\n {\n v5 = v9++;\n v14[v5] = *(_DWORD *)(4LL * k + a3);\n }\n }\n return v14;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11C9(long long a1, int a2, long long a3, int a4) {\n int v4;\n int v5;\n int v9;\n int i;\n int j;\n int k;\n int m;\n uint32_t *v14;\n v14 = malloc(4LL * (a2 + a4));\n v9 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = 0; j < v9 && v14[j] != *(uint32_t *)(4LL * i + a1); ++j)\n ;\n if (j == v9) {\n v4 = v9++;\n v14[v4] = *(uint32_t *)(4LL * i + a1);\n }\n }\n for (k = 0; k < a4; ++k) {\n for (m = 0; m < v9 && v14[m] != *(uint32_t *)(4LL * k + a3); ++m)\n ;\n if (m == v9) {\n v5 = v9++;\n v14[v5] = *(uint32_t *)(4LL * k + a3);\n }\n }\n return v14;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, long long a3, int a4) {\n int v4;\n int v5;\n int v9;\n int i;\n int j;\n int k;\n int m;\n uint32_t *v14;\n v14 = malloc(4LL * (a2 + a4));\n v9 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = 0; j < v9 && v14[j] != *(uint32_t *)(4LL * i + a1); ++j)\n ;\n if (j == v9) {\n v4 = v9++;\n v14[v4] = *(uint32_t *)(4LL * i + a1);\n }\n }\n for (k = 0; k < a4; ++k) {\n for (m = 0; m < v9 && v14[m] != *(uint32_t *)(4LL * k + a3); ++m)\n ;\n if (m == v9) {\n v5 = v9++;\n v14[v5] = *(uint32_t *)(4LL * k + a3);\n }\n }\n return v14;\n}" + }, + { + "index": 560, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int *elements;\n\n int size;\n\n} UniqueTuple;\n\n\n\n", + "func": "UniqueTuple func0(int *test_tup1, int size1, int *test_tup2, int size2) {\n UniqueTuple result;\n result.elements = (int *)malloc((size1 + size2) * sizeof(int));\n int k = 0;\n for (int i = 0; i < size1; i++) {\n int j;\n for (j = 0; j < k; j++) {\n if (result.elements[j] == test_tup1[i]) break;\n }\n if (j == k) {\n result.elements[k++] = test_tup1[i];\n }\n }\n for (int i = 0; i < size2; i++) {\n int j;\n for (j = 0; j < k; j++) {\n if (result.elements[j] == test_tup2[i]) break;\n }\n if (j == k) {\n result.elements[k++] = test_tup2[i];\n }\n }\n result.size = k;\n return result;\n}", + "test": "int main() {\n\n int tuple1[] = {3, 4, 5, 6};\n\n int tuple2[] = {5, 7, 4, 10};\n\n UniqueTuple res1 = func0(tuple1, 4, tuple2, 4);\n\n int expected1[] = {3, 4, 5, 6, 7, 10};\n\n assert(res1.size == sizeof(expected1) / sizeof(int));\n\n for (int i = 0; i < res1.size; i++) {\n\n assert(res1.elements[i] == expected1[i]);\n\n }\n\n\n\n int tuple3[] = {1, 2, 3, 4};\n\n int tuple4[] = {3, 4, 5, 6};\n\n UniqueTuple res2 = func0(tuple3, 4, tuple4, 4);\n\n int expected2[] = {1, 2, 3, 4, 5, 6};\n\n assert(res2.size == sizeof(expected2) / sizeof(int));\n\n for (int i = 0; i < res2.size; i++) {\n\n assert(res2.elements[i] == expected2[i]);\n\n }\n\n\n\n int tuple5[] = {11, 12, 13, 14};\n\n int tuple6[] = {13, 15, 16, 17};\n\n UniqueTuple res3 = func0(tuple5, 4, tuple6, 4);\n\n int expected3[] = {11, 12, 13, 14, 15, 16, 17};\n\n assert(res3.size == sizeof(expected3) / sizeof(int));\n\n for (int i = 0; i < res3.size; i++) {\n\n assert(res3.elements[i] == expected3[i]);\n\n }\n\n\n\n free(res1.elements);\n\n free(res2.elements);\n\n free(res3.elements);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%r13\nmov %esi,%r12d\nmov %rdx,%rbp\nmov %ecx,%ebx\nlea (%rsi,%rcx,1),%edi\nmovslq %edi,%rdi\nshl $0x2,%rdi\ncallq 10d0 \ntest %r12d,%r12d\njle 1266 \nmov %r13,%r10\nlea -0x1(%r12),%edx\nlea 0x0(%r13,%rdx,4),%r11\nmov $0x0,%r9d\nmov $0x0,%ecx\nmov $0x0,%r13d\nmov $0x0,%r12d\njmp 1236 \nmov %rsi,%rdx\nmov %edx,%ecx\ncmp %edi,(%rax,%rdx,4)\nje 1232 \nlea 0x1(%rdx),%ecx\nlea 0x1(%rdx),%rsi\ncmp %r8,%rdx\njne 121c \nadd $0x4,%r10\ncmp %ecx,%r9d\nje 1252 \ncmp %r11,%r10\nje 126c \ntest %r9d,%r9d\njle 1261 \nmov 0x4(%r10),%edi\nlea -0x1(%r9),%r8d\nmov %r12,%rdx\njmp 121f \nmovslq %r9d,%rdx\nmov (%r10),%ecx\nmov %ecx,(%rax,%rdx,4)\nlea 0x1(%r9),%r9d\njmp 123b \nmov %r13d,%ecx\njmp 1232 \nmov $0x0,%r9d\ntest %ebx,%ebx\njle 12cd \nmov %rbp,%r10\nlea -0x1(%rbx),%edx\nlea 0x4(%rbp,%rdx,4),%r11\nmov $0x0,%ebp\nmov $0x0,%ebx\njmp 12ab \nmov %rsi,%rdx\nmov %edx,%ecx\ncmp %edi,(%rax,%rdx,4)\nje 129d \nlea 0x1(%rdx),%ecx\nlea 0x1(%rdx),%rsi\ncmp %r8,%rdx\njne 1287 \ncmp %ecx,%r9d\nje 12be \nadd $0x4,%r10\ncmp %r11,%r10\nje 12cd \nmov %ebp,%ecx\ntest %r9d,%r9d\njle 129d \nmov (%r10),%edi\nlea -0x1(%r9),%r8d\nmov %rbx,%rdx\njmp 128a \nmovslq %r9d,%rdx\nmov (%r10),%ecx\nmov %ecx,(%rax,%rdx,4)\nlea 0x1(%r9),%r9d\njmp 12a2 \nmov %r9d,%edx\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r13, rdi\nmov r12d, esi\nmov rbp, rdx\nmov ebx, ecx\nlea edi, [rsi+rcx]\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov r8, rax\ntest r12d, r12d\njle short loc_1248\nmov rdi, r13\nmovsxd r12, r12d\nlea r9, [r13+r12*4+0]\nmov ecx, 0\njmp short loc_1218\nloc_120B:\ncmp ecx, eax\njz short loc_123A\nloc_120F:\nadd rdi, 4\ncmp rdi, r9\njz short loc_124D\nloc_1218:\nmov eax, 0\ntest ecx, ecx\njle short loc_120B\nmov esi, [rdi]\nmov rdx, r8\nmov eax, 0\nloc_122B:\ncmp [rdx], esi\njz short loc_120B\nadd eax, 1\nadd rdx, 4\ncmp eax, ecx\njnz short loc_122B\nloc_123A:\nmovsxd rax, ecx\nmov edx, [rdi]\nmov [r8+rax*4], edx\nlea ecx, [rcx+1]\njmp short loc_120F\nloc_1248:\nmov ecx, 0\nloc_124D:\ntest ebx, ebx\njle short loc_129B\nmov rdi, rbp\nmovsxd rbx, ebx\nlea r9, [rbp+rbx*4+0]\njmp short loc_126B\nloc_125E:\ncmp ecx, eax\njz short loc_128D\nloc_1262:\nadd rdi, 4\ncmp rdi, r9\njz short loc_129B\nloc_126B:\nmov eax, 0\ntest ecx, ecx\njle short loc_125E\nmov esi, [rdi]\nmov rdx, r8\nmov eax, 0\nloc_127E:\ncmp [rdx], esi\njz short loc_125E\nadd eax, 1\nadd rdx, 4\ncmp eax, ecx\njnz short loc_127E\nloc_128D:\nmovsxd rax, ecx\nmov edx, [rdi]\nmov [r8+rax*4], edx\nlea ecx, [rcx+1]\njmp short loc_1262\nloc_129B:\nmov edx, ecx\nmov rax, r8\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(_DWORD *a1, int a2, _DWORD *a3, int a4)\n{\n _DWORD *v4; // r13\n _DWORD *v7; // r8\n int v8; // ecx\n int v9; // eax\n _DWORD *v10; // rdx\n _DWORD *v11; // rdi\n int v12; // eax\n _DWORD *v13; // rdx\n\n v4 = a1;\n v7 = malloc(4LL * (a2 + a4));\n if ( a2 <= 0 )\n {\n v8 = 0;\n }\n else\n {\n v8 = 0;\n do\n {\n v9 = 0;\n if ( v8 > 0 )\n {\n v10 = v7;\n v9 = 0;\n while ( *v10 != *a1 )\n {\n ++v9;\n ++v10;\n if ( v9 == v8 )\n goto LABEL_9;\n }\n }\n if ( v8 == v9 )\nLABEL_9:\n v7[v8++] = *a1;\n ++a1;\n }\n while ( a1 != &v4[a2] );\n }\n if ( a4 > 0 )\n {\n v11 = a3;\n do\n {\n v12 = 0;\n if ( v8 > 0 )\n {\n v13 = v7;\n v12 = 0;\n while ( *v13 != *v11 )\n {\n ++v12;\n ++v13;\n if ( v12 == v8 )\n goto LABEL_19;\n }\n }\n if ( v8 == v12 )\nLABEL_19:\n v7[v8++] = *v11;\n ++v11;\n }\n while ( v11 != &a3[a4] );\n }\n return v7;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r13, rdi\nmov r12d, esi\nmov rbp, rdx\nmov ebx, ecx\nlea edi, [rsi+rcx]\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov r8, rax\ntest r12d, r12d\njle short loc_1248\nmov rdi, r13\nmovsxd r12, r12d\nlea r9, [r13+r12*4+0]\nmov ecx, 0\njmp short loc_1218\nloc_120B:\ncmp ecx, eax\njz short loc_123A\nloc_120F:\nadd rdi, 4\ncmp rdi, r9\njz short loc_124D\nloc_1218:\nmov eax, 0\ntest ecx, ecx\njle short loc_120B\nmov esi, [rdi]\nmov rdx, r8\nmov eax, 0\nloc_122B:\ncmp [rdx], esi\njz short loc_120B\nadd eax, 1\nadd rdx, 4\ncmp eax, ecx\njnz short loc_122B\nloc_123A:\nmovsxd rax, ecx\nmov edx, [rdi]\nmov [r8+rax*4], edx\nlea ecx, [rcx+1]\njmp short loc_120F\nloc_1248:\nmov ecx, 0\nloc_124D:\ntest ebx, ebx\njle short loc_129B\nmov rdi, rbp\nmovsxd rbx, ebx\nlea r9, [rbp+rbx*4+0]\njmp short loc_126B\nloc_125E:\ncmp ecx, eax\njz short loc_128D\nloc_1262:\nadd rdi, 4\ncmp rdi, r9\njz short loc_129B\nloc_126B:\nmov eax, 0\ntest ecx, ecx\njle short loc_125E\nmov esi, [rdi]\nmov rdx, r8\nmov eax, 0\nloc_127E:\ncmp [rdx], esi\njz short loc_125E\nadd eax, 1\nadd rdx, 4\ncmp eax, ecx\njnz short loc_127E\nloc_128D:\nmovsxd rax, ecx\nmov edx, [rdi]\nmov [r8+rax*4], edx\nlea ecx, [rcx+1]\njmp short loc_1262\nloc_129B:\nmov edx, ecx\nmov rax, r8\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11C9(_DWORD *a1, int a2, _DWORD *a3, int a4)\n{\n _DWORD *v4; // r13\n _DWORD *v7; // r8\n int v8; // ecx\n int v9; // eax\n _DWORD *v10; // rdx\n _DWORD *v11; // rdi\n int v12; // eax\n _DWORD *v13; // rdx\n\n v4 = a1;\n v7 = malloc(4LL * (a2 + a4));\n if ( a2 <= 0 )\n {\n v8 = 0;\n }\n else\n {\n v8 = 0;\n do\n {\n v9 = 0;\n if ( v8 > 0 )\n {\n v10 = v7;\n v9 = 0;\n while ( *v10 != *a1 )\n {\n ++v9;\n ++v10;\n if ( v9 == v8 )\n goto LABEL_9;\n }\n }\n if ( v8 == v9 )\nLABEL_9:\n v7[v8++] = *a1;\n ++a1;\n }\n while ( a1 != &v4[a2] );\n }\n if ( a4 > 0 )\n {\n v11 = a3;\n do\n {\n v12 = 0;\n if ( v8 > 0 )\n {\n v13 = v7;\n v12 = 0;\n while ( *v13 != *v11 )\n {\n ++v12;\n ++v13;\n if ( v12 == v8 )\n goto LABEL_19;\n }\n }\n if ( v8 == v12 )\nLABEL_19:\n v7[v8++] = *v11;\n ++v11;\n }\n while ( v11 != &a3[a4] );\n }\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11C9(uint32_t *a1, int a2, uint32_t *a3, int a4) {\n uint32_t *v4;\n uint32_t *v7;\n int v8;\n int v9;\n uint32_t *v10;\n uint32_t *v11;\n int v12;\n uint32_t *v13;\n v4 = a1;\n v7 = malloc(4LL * (a2 + a4));\n if (a2 <= 0) {\n v8 = 0;\n } else {\n v8 = 0;\n do {\n v9 = 0;\n if (v8 > 0) {\n v10 = v7;\n v9 = 0;\n while (*v10 != *a1) {\n ++v9;\n ++v10;\n if (v9 == v8) goto LABEL_9;\n }\n }\n if (v8 == v9)\n LABEL_9:\n v7[v8++] = *a1;\n ++a1;\n } while (a1 != &v4[a2]);\n }\n if (a4 > 0) {\n v11 = a3;\n do {\n v12 = 0;\n if (v8 > 0) {\n v13 = v7;\n v12 = 0;\n while (*v13 != *v11) {\n ++v12;\n ++v13;\n if (v12 == v8) goto LABEL_19;\n }\n }\n if (v8 == v12)\n LABEL_19:\n v7[v8++] = *v11;\n ++v11;\n } while (v11 != &a3[a4]);\n }\n return v7;\n}", + "ida_pseudo_norm": "uint32_t *func0(uint32_t *a1, int a2, uint32_t *a3, int a4) {\n uint32_t *v4;\n uint32_t *v7;\n int v8;\n int v9;\n uint32_t *v10;\n uint32_t *v11;\n int v12;\n uint32_t *v13;\n v4 = a1;\n v7 = malloc(4LL * (a2 + a4));\n if (a2 <= 0) {\n v8 = 0;\n } else {\n v8 = 0;\n do {\n v9 = 0;\n if (v8 > 0) {\n v10 = v7;\n v9 = 0;\n while (*v10 != *a1) {\n ++v9;\n ++v10;\n if (v9 == v8) goto LABEL_9;\n }\n }\n if (v8 == v9)\n LABEL_9:\n v7[v8++] = *a1;\n ++a1;\n } while (a1 != &v4[a2]);\n }\n if (a4 > 0) {\n v11 = a3;\n do {\n v12 = 0;\n if (v8 > 0) {\n v13 = v7;\n v12 = 0;\n while (*v13 != *v11) {\n ++v12;\n ++v13;\n if (v12 == v8) goto LABEL_19;\n }\n }\n if (v8 == v12)\n LABEL_19:\n v7[v8++] = *v11;\n ++v11;\n } while (v11 != &a3[a4]);\n }\n return v7;\n}" + }, + { + "index": 560, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int *elements;\n\n int size;\n\n} UniqueTuple;\n\n\n\n", + "func": "UniqueTuple func0(int *test_tup1, int size1, int *test_tup2, int size2) {\n UniqueTuple result;\n result.elements = (int *)malloc((size1 + size2) * sizeof(int));\n int k = 0;\n for (int i = 0; i < size1; i++) {\n int j;\n for (j = 0; j < k; j++) {\n if (result.elements[j] == test_tup1[i]) break;\n }\n if (j == k) {\n result.elements[k++] = test_tup1[i];\n }\n }\n for (int i = 0; i < size2; i++) {\n int j;\n for (j = 0; j < k; j++) {\n if (result.elements[j] == test_tup2[i]) break;\n }\n if (j == k) {\n result.elements[k++] = test_tup2[i];\n }\n }\n result.size = k;\n return result;\n}", + "test": "int main() {\n\n int tuple1[] = {3, 4, 5, 6};\n\n int tuple2[] = {5, 7, 4, 10};\n\n UniqueTuple res1 = func0(tuple1, 4, tuple2, 4);\n\n int expected1[] = {3, 4, 5, 6, 7, 10};\n\n assert(res1.size == sizeof(expected1) / sizeof(int));\n\n for (int i = 0; i < res1.size; i++) {\n\n assert(res1.elements[i] == expected1[i]);\n\n }\n\n\n\n int tuple3[] = {1, 2, 3, 4};\n\n int tuple4[] = {3, 4, 5, 6};\n\n UniqueTuple res2 = func0(tuple3, 4, tuple4, 4);\n\n int expected2[] = {1, 2, 3, 4, 5, 6};\n\n assert(res2.size == sizeof(expected2) / sizeof(int));\n\n for (int i = 0; i < res2.size; i++) {\n\n assert(res2.elements[i] == expected2[i]);\n\n }\n\n\n\n int tuple5[] = {11, 12, 13, 14};\n\n int tuple6[] = {13, 15, 16, 17};\n\n UniqueTuple res3 = func0(tuple5, 4, tuple6, 4);\n\n int expected3[] = {11, 12, 13, 14, 15, 16, 17};\n\n assert(res3.size == sizeof(expected3) / sizeof(int));\n\n for (int i = 0; i < res3.size; i++) {\n\n assert(res3.elements[i] == expected3[i]);\n\n }\n\n\n\n free(res1.elements);\n\n free(res2.elements);\n\n free(res3.elements);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov %esi,%r13d\npush %r12\nmov %ecx,%r12d\npush %rbp\nmov %rdi,%rbp\nlea (%rsi,%rcx,1),%edi\npush %rbx\nmovslq %edi,%rdi\nmov %rdx,%rbx\nshl $0x2,%rdi\nsub $0x8,%rsp\ncallq 10d0 \ntest %r13d,%r13d\njle 1638 \nlea -0x1(%r13),%edx\nmov %rbp,%r10\nxor %r9d,%r9d\nlea 0x4(%rbp,%rdx,4),%r11\nnopl 0x0(%rax)\nxor %r8d,%r8d\ntest %r9d,%r9d\njle 15f0 \nlea -0x1(%r9),%esi\nmov (%r10),%edi\nmov $0x1,%edx\nadd $0x2,%rsi\njmp 157c \nnopw %cs:0x0(%rax,%rax,1)\nmov %edx,%r8d\nadd $0x1,%rdx\ncmp %rsi,%rdx\nje 15f0 \ncmp %edi,-0x4(%rax,%rdx,4)\njne 1570 \nadd $0x4,%r10\ncmp %r11,%r10\njne 1548 \ntest %r12d,%r12d\njle 15da \nlea -0x1(%r12),%edx\nlea 0x4(%rbx,%rdx,4),%r8\nnopw 0x0(%rax,%rax,1)\nxor %edi,%edi\ntest %r9d,%r9d\njle 1618 \nlea -0x1(%r9),%ecx\nmov (%rbx),%esi\nmov $0x1,%edx\nadd $0x2,%rcx\njmp 15cb \nnopl 0x0(%rax,%rax,1)\nmov %edx,%edi\nadd $0x1,%rdx\ncmp %rcx,%rdx\nje 1618 \ncmp %esi,-0x4(%rax,%rdx,4)\njne 15c0 \nadd $0x4,%rbx\ncmp %r8,%rbx\njne 15a0 \nadd $0x8,%rsp\nmov %r9d,%edx\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax,%rax,1)\ncmp %r9d,%r8d\njne 1582 \nmov (%r10),%ecx\nmovslq %r9d,%rdx\nadd $0x4,%r10\nadd $0x1,%r9d\nmov %ecx,(%rax,%rdx,4)\ncmp %r11,%r10\njne 1548 \njmpq 158b \nnopl 0x0(%rax)\ncmp %r9d,%edi\njne 15d1 \nmov (%rbx),%ecx\nmovslq %r9d,%rdx\nadd $0x4,%rbx\nadd $0x1,%r9d\nmov %ecx,(%rax,%rdx,4)\ncmp %r8,%rbx\njne 15a0 \njmp 15da \nxor %r9d,%r9d\njmpq 158b \n", + "ida_asm": "func0:\nendbr64\npush r13\nmovsxd r13, esi\npush r12\nmovsxd r12, ecx\npush rbp\nmov rbp, rdi\nlea edi, [r13+r12+0]\npush rbx\nmovsxd rdi, edi\nmov rbx, rdx\nshl rdi, 2; size\nsub rsp, 8\ncall _malloc\nmov r8, rax\ntest r13d, r13d\njle loc_1584\nmov rdi, rbp\nlea r9, [rbp+r13*4+0]\nxor ecx, ecx\nloc_14C1:\nxor eax, eax\ntest ecx, ecx\njle short loc_14DF\nloc_14C7:\nmov esi, [rdi]\nmov rdx, r8\nxor eax, eax\njmp short loc_14DB\nloc_14D0:\nadd eax, 1\nadd rdx, 4\ncmp ecx, eax\njz short loc_1540\nloc_14DB:\ncmp [rdx], esi\njnz short loc_14D0\nloc_14DF:\ncmp ecx, eax\njz short loc_1540\nadd rdi, 4\ncmp rdi, r9\njnz short loc_14C1\nloc_14EC:\ntest r12d, r12d\njle short loc_152C\nmov rdi, rbx\nlea r9, [rbx+r12*4]\nloc_14F8:\nxor eax, eax\ntest ecx, ecx\njle short loc_151F\nloc_14FE:\nmov esi, [rdi]\nmov rdx, r8\nxor eax, eax\njmp short loc_151B\nloc_1510:\nadd eax, 1\nadd rdx, 4\ncmp ecx, eax\njz short loc_1560\nloc_151B:\ncmp [rdx], esi\njnz short loc_1510\nloc_151F:\ncmp ecx, eax\njz short loc_1560\nadd rdi, 4\ncmp rdi, r9\njnz short loc_14F8\nloc_152C:\nadd rsp, 8\nmov edx, ecx\nmov rax, r8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1540:\nmov edx, [rdi]\nlea ecx, [rax+1]\nadd rdi, 4\ncdqe\nmov [r8+rax*4], edx\ncmp rdi, r9\njnz loc_14C7\njmp short loc_14EC\nloc_1560:\nmov edx, [rdi]\nlea ecx, [rax+1]\nadd rdi, 4\ncdqe\nmov [r8+rax*4], edx\ncmp rdi, r9\njnz short loc_14FE\nadd rsp, 8\nmov edx, ecx\nmov rax, r8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1584:\nxor ecx, ecx\njmp loc_14EC", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2, int *a3, int a4)\n{\n __int64 v4; // r12\n _DWORD *v6; // r8\n int *v7; // r9\n int v8; // ecx\n int v9; // eax\n _DWORD *v10; // rdx\n int *v11; // rdi\n int *v12; // r9\n int v13; // eax\n _DWORD *v14; // rdx\n int v16; // edx\n int v17; // edx\n\n v4 = a4;\n v6 = malloc(4LL * (a2 + a4));\n if ( a2 > 0 )\n {\n v7 = &a1[a2];\n v8 = 0;\n while ( 1 )\n {\n v9 = 0;\n if ( v8 <= 0 )\n goto LABEL_7;\n while ( 1 )\n {\n v10 = v6;\n v9 = 0;\n while ( *v10 != *a1 )\n {\n ++v9;\n ++v10;\n if ( v8 == v9 )\n goto LABEL_18;\n }\nLABEL_7:\n if ( v8 != v9 )\n break;\nLABEL_18:\n v16 = *a1;\n v8 = v9 + 1;\n ++a1;\n v6[v9] = v16;\n if ( a1 == v7 )\n goto LABEL_9;\n }\n if ( ++a1 == v7 )\n goto LABEL_9;\n }\n }\n v8 = 0;\nLABEL_9:\n if ( (int)v4 <= 0 )\n return v6;\n v11 = a3;\n v12 = &a3[v4];\nLABEL_11:\n v13 = 0;\n if ( v8 <= 0 )\n goto LABEL_15;\n do\n {\n v14 = v6;\n v13 = 0;\n while ( *v14 != *v11 )\n {\n ++v13;\n ++v14;\n if ( v8 == v13 )\n goto LABEL_20;\n }\nLABEL_15:\n if ( v8 != v13 )\n {\n if ( ++v11 == v12 )\n return v6;\n goto LABEL_11;\n }\nLABEL_20:\n v17 = *v11;\n v8 = v13 + 1;\n ++v11;\n v6[v13] = v17;\n }\n while ( v11 != v12 );\n return v6;\n}", + "ida_strip_asm": "sub_1480:\nendbr64\npush r13\nmovsxd r13, esi\npush r12\nmovsxd r12, ecx\npush rbp\nmov rbp, rdi\nlea edi, [r13+r12+0]\npush rbx\nmovsxd rdi, edi\nmov rbx, rdx\nshl rdi, 2; size\nsub rsp, 8\ncall _malloc\nmov r8, rax\ntest r13d, r13d\njle loc_1584\nmov rdi, rbp\nlea r9, [rbp+r13*4+0]\nxor ecx, ecx\nloc_14C1:\nxor eax, eax\ntest ecx, ecx\njle short loc_14DF\nloc_14C7:\nmov esi, [rdi]\nmov rdx, r8\nxor eax, eax\njmp short loc_14DB\nloc_14D0:\nadd eax, 1\nadd rdx, 4\ncmp ecx, eax\njz short loc_1540\nloc_14DB:\ncmp [rdx], esi\njnz short loc_14D0\nloc_14DF:\ncmp ecx, eax\njz short loc_1540\nadd rdi, 4\ncmp rdi, r9\njnz short loc_14C1\nloc_14EC:\ntest r12d, r12d\njle short loc_152C\nmov rdi, rbx\nlea r9, [rbx+r12*4]\nloc_14F8:\nxor eax, eax\ntest ecx, ecx\njle short loc_151F\nloc_14FE:\nmov esi, [rdi]\nmov rdx, r8\nxor eax, eax\njmp short loc_151B\nloc_1510:\nadd eax, 1\nadd rdx, 4\ncmp ecx, eax\njz short loc_1560\nloc_151B:\ncmp [rdx], esi\njnz short loc_1510\nloc_151F:\ncmp ecx, eax\njz short loc_1560\nadd rdi, 4\ncmp rdi, r9\njnz short loc_14F8\nloc_152C:\nadd rsp, 8\nmov edx, ecx\nmov rax, r8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1540:\nmov edx, [rdi]\nlea ecx, [rax+1]\nadd rdi, 4\ncdqe\nmov [r8+rax*4], edx\ncmp rdi, r9\njnz loc_14C7\njmp short loc_14EC\nloc_1560:\nmov edx, [rdi]\nlea ecx, [rax+1]\nadd rdi, 4\ncdqe\nmov [r8+rax*4], edx\ncmp rdi, r9\njnz short loc_14FE\nadd rsp, 8\nmov edx, ecx\nmov rax, r8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1584:\nxor ecx, ecx\njmp loc_14EC", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1480(int *a1, int a2, int *a3, int a4)\n{\n __int64 v4; // r12\n _DWORD *v6; // r8\n int *v7; // r9\n int v8; // ecx\n int v9; // eax\n _DWORD *v10; // rdx\n int *v11; // rdi\n int *v12; // r9\n int v13; // eax\n _DWORD *v14; // rdx\n int v16; // edx\n int v17; // edx\n\n v4 = a4;\n v6 = malloc(4LL * (a2 + a4));\n if ( a2 > 0 )\n {\n v7 = &a1[a2];\n v8 = 0;\n while ( 1 )\n {\n v9 = 0;\n if ( v8 <= 0 )\n goto LABEL_7;\n while ( 1 )\n {\n v10 = v6;\n v9 = 0;\n while ( *v10 != *a1 )\n {\n ++v9;\n ++v10;\n if ( v8 == v9 )\n goto LABEL_18;\n }\nLABEL_7:\n if ( v8 != v9 )\n break;\nLABEL_18:\n v16 = *a1;\n v8 = v9 + 1;\n ++a1;\n v6[v9] = v16;\n if ( a1 == v7 )\n goto LABEL_9;\n }\n if ( ++a1 == v7 )\n goto LABEL_9;\n }\n }\n v8 = 0;\nLABEL_9:\n if ( (int)v4 <= 0 )\n return v6;\n v11 = a3;\n v12 = &a3[v4];\nLABEL_11:\n v13 = 0;\n if ( v8 <= 0 )\n goto LABEL_15;\n do\n {\n v14 = v6;\n v13 = 0;\n while ( *v14 != *v11 )\n {\n ++v13;\n ++v14;\n if ( v8 == v13 )\n goto LABEL_20;\n }\nLABEL_15:\n if ( v8 != v13 )\n {\n if ( ++v11 == v12 )\n return v6;\n goto LABEL_11;\n }\nLABEL_20:\n v17 = *v11;\n v8 = v13 + 1;\n ++v11;\n v6[v13] = v17;\n }\n while ( v11 != v12 );\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1480(int *a1, int a2, int *a3, int a4) {\n long long v4;\n uint32_t *v6;\n int *v7;\n int v8;\n int v9;\n uint32_t *v10;\n int *v11;\n int *v12;\n int v13;\n uint32_t *v14;\n int v16;\n int v17;\n v4 = a4;\n v6 = malloc(4LL * (a2 + a4));\n if (a2 > 0) {\n v7 = &a1[a2];\n v8 = 0;\n while (1) {\n v9 = 0;\n if (v8 <= 0) goto LABEL_7;\n while (1) {\n v10 = v6;\n v9 = 0;\n while (*v10 != *a1) {\n ++v9;\n ++v10;\n if (v8 == v9) goto LABEL_18;\n }\n LABEL_7:\n if (v8 != v9) break;\n LABEL_18:\n v16 = *a1;\n v8 = v9 + 1;\n ++a1;\n v6[v9] = v16;\n if (a1 == v7) goto LABEL_9;\n }\n if (++a1 == v7) goto LABEL_9;\n }\n }\n v8 = 0;\nLABEL_9:\n if ((int)v4 <= 0) return v6;\n v11 = a3;\n v12 = &a3[v4];\nLABEL_11:\n v13 = 0;\n if (v8 <= 0) goto LABEL_15;\n do {\n v14 = v6;\n v13 = 0;\n while (*v14 != *v11) {\n ++v13;\n ++v14;\n if (v8 == v13) goto LABEL_20;\n }\n LABEL_15:\n if (v8 != v13) {\n if (++v11 == v12) return v6;\n goto LABEL_11;\n }\n LABEL_20:\n v17 = *v11;\n v8 = v13 + 1;\n ++v11;\n v6[v13] = v17;\n } while (v11 != v12);\n return v6;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2, int *a3, int a4) {\n long long v4;\n uint32_t *v6;\n int *v7;\n int v8;\n int v9;\n uint32_t *v10;\n int *v11;\n int *v12;\n int v13;\n uint32_t *v14;\n int v16;\n int v17;\n v4 = a4;\n v6 = malloc(4LL * (a2 + a4));\n if (a2 > 0) {\n v7 = &a1[a2];\n v8 = 0;\n while (1) {\n v9 = 0;\n if (v8 <= 0) goto LABEL_7;\n while (1) {\n v10 = v6;\n v9 = 0;\n while (*v10 != *a1) {\n ++v9;\n ++v10;\n if (v8 == v9) goto LABEL_18;\n }\n LABEL_7:\n if (v8 != v9) break;\n LABEL_18:\n v16 = *a1;\n v8 = v9 + 1;\n ++a1;\n v6[v9] = v16;\n if (a1 == v7) goto LABEL_9;\n }\n if (++a1 == v7) goto LABEL_9;\n }\n }\n v8 = 0;\nLABEL_9:\n if ((int)v4 <= 0) return v6;\n v11 = a3;\n v12 = &a3[v4];\nLABEL_11:\n v13 = 0;\n if (v8 <= 0) goto LABEL_15;\n do {\n v14 = v6;\n v13 = 0;\n while (*v14 != *v11) {\n ++v13;\n ++v14;\n if (v8 == v13) goto LABEL_20;\n }\n LABEL_15:\n if (v8 != v13) {\n if (++v11 == v12) return v6;\n goto LABEL_11;\n }\n LABEL_20:\n v17 = *v11;\n v8 = v13 + 1;\n ++v11;\n v6[v13] = v17;\n } while (v11 != v12);\n return v6;\n}" + }, + { + "index": 560, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int *elements;\n\n int size;\n\n} UniqueTuple;\n\n\n\n", + "func": "UniqueTuple func0(int *test_tup1, int size1, int *test_tup2, int size2) {\n UniqueTuple result;\n result.elements = (int *)malloc((size1 + size2) * sizeof(int));\n int k = 0;\n for (int i = 0; i < size1; i++) {\n int j;\n for (j = 0; j < k; j++) {\n if (result.elements[j] == test_tup1[i]) break;\n }\n if (j == k) {\n result.elements[k++] = test_tup1[i];\n }\n }\n for (int i = 0; i < size2; i++) {\n int j;\n for (j = 0; j < k; j++) {\n if (result.elements[j] == test_tup2[i]) break;\n }\n if (j == k) {\n result.elements[k++] = test_tup2[i];\n }\n }\n result.size = k;\n return result;\n}", + "test": "int main() {\n\n int tuple1[] = {3, 4, 5, 6};\n\n int tuple2[] = {5, 7, 4, 10};\n\n UniqueTuple res1 = func0(tuple1, 4, tuple2, 4);\n\n int expected1[] = {3, 4, 5, 6, 7, 10};\n\n assert(res1.size == sizeof(expected1) / sizeof(int));\n\n for (int i = 0; i < res1.size; i++) {\n\n assert(res1.elements[i] == expected1[i]);\n\n }\n\n\n\n int tuple3[] = {1, 2, 3, 4};\n\n int tuple4[] = {3, 4, 5, 6};\n\n UniqueTuple res2 = func0(tuple3, 4, tuple4, 4);\n\n int expected2[] = {1, 2, 3, 4, 5, 6};\n\n assert(res2.size == sizeof(expected2) / sizeof(int));\n\n for (int i = 0; i < res2.size; i++) {\n\n assert(res2.elements[i] == expected2[i]);\n\n }\n\n\n\n int tuple5[] = {11, 12, 13, 14};\n\n int tuple6[] = {13, 15, 16, 17};\n\n UniqueTuple res3 = func0(tuple5, 4, tuple6, 4);\n\n int expected3[] = {11, 12, 13, 14, 15, 16, 17};\n\n assert(res3.size == sizeof(expected3) / sizeof(int));\n\n for (int i = 0; i < res3.size; i++) {\n\n assert(res3.elements[i] == expected3[i]);\n\n }\n\n\n\n free(res1.elements);\n\n free(res2.elements);\n\n free(res3.elements);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov %esi,%r13d\npush %r12\nmov %ecx,%r12d\npush %rbp\nmov %rdi,%rbp\nlea (%rsi,%rcx,1),%edi\npush %rbx\nmovslq %edi,%rdi\nmov %rdx,%rbx\nshl $0x2,%rdi\nsub $0x8,%rsp\ncallq 10d0 \ntest %r13d,%r13d\njle 1618 \nlea -0x1(%r13),%edx\nmov %rbp,%r10\nxor %r9d,%r9d\nlea 0x4(%rbp,%rdx,4),%r11\nnopl 0x0(%rax)\nxor %r8d,%r8d\ntest %r9d,%r9d\njle 15d0 \nlea -0x1(%r9),%esi\nmov (%r10),%edi\nmov $0x1,%edx\nadd $0x2,%rsi\njmp 155c \nnopw %cs:0x0(%rax,%rax,1)\nmov %edx,%r8d\nadd $0x1,%rdx\ncmp %rsi,%rdx\nje 15d0 \ncmp %edi,-0x4(%rax,%rdx,4)\njne 1550 \nadd $0x4,%r10\ncmp %r11,%r10\njne 1528 \ntest %r12d,%r12d\njle 15ba \nlea -0x1(%r12),%edx\nlea 0x4(%rbx,%rdx,4),%r8\nnopw 0x0(%rax,%rax,1)\nxor %edi,%edi\ntest %r9d,%r9d\njle 15f8 \nlea -0x1(%r9),%ecx\nmov (%rbx),%esi\nmov $0x1,%edx\nadd $0x2,%rcx\njmp 15ab \nnopl 0x0(%rax,%rax,1)\nmov %edx,%edi\nadd $0x1,%rdx\ncmp %rdx,%rcx\nje 15f8 \ncmp %esi,-0x4(%rax,%rdx,4)\njne 15a0 \nadd $0x4,%rbx\ncmp %r8,%rbx\njne 1580 \nadd $0x8,%rsp\nmov %r9d,%edx\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax,%rax,1)\ncmp %r9d,%r8d\njne 1562 \nmov (%r10),%ecx\nmovslq %r9d,%rdx\nadd $0x4,%r10\nadd $0x1,%r9d\nmov %ecx,(%rax,%rdx,4)\ncmp %r11,%r10\njne 1528 \njmpq 156b \nnopl 0x0(%rax)\ncmp %r9d,%edi\njne 15b1 \nmov (%rbx),%ecx\nmovslq %r9d,%rdx\nadd $0x4,%rbx\nadd $0x1,%r9d\nmov %ecx,(%rax,%rdx,4)\ncmp %r8,%rbx\njne 1580 \njmp 15ba \nxor %r9d,%r9d\njmpq 156b \n", + "ida_asm": "func0:\nendbr64\npush r13\nmovsxd r13, esi\npush r12\nmovsxd r12, ecx\npush rbp\nmov rbp, rdi\nlea edi, [r13+r12+0]\npush rbx\nmovsxd rdi, edi\nmov rbx, rdx\nshl rdi, 2; size\nsub rsp, 8\ncall _malloc\nmov r8, rax\ntest r13d, r13d\njle loc_1557\nmov rdi, rbp\nlea r9, [rbp+r13*4+0]\nxor ecx, ecx\nloc_1491:\nxor eax, eax\ntest ecx, ecx\njle short loc_14AF\nloc_1497:\nmov esi, [rdi]\nmov rdx, r8\nxor eax, eax\njmp short loc_14AB\nloc_14A0:\nadd eax, 1\nadd rdx, 4\ncmp ecx, eax\njz short loc_1510\nloc_14AB:\ncmp [rdx], esi\njnz short loc_14A0\nloc_14AF:\ncmp ecx, eax\njz short loc_1510\nadd rdi, 4\ncmp rdi, r9\njnz short loc_1491\nloc_14BC:\ntest r12d, r12d\njle short loc_14FC\nmov rdi, rbx\nlea r9, [rbx+r12*4]\nloc_14C8:\nxor eax, eax\ntest ecx, ecx\njle short loc_14EF\nloc_14CE:\nmov esi, [rdi]\nmov rdx, r8\nxor eax, eax\njmp short loc_14EB\nloc_14E0:\nadd eax, 1\nadd rdx, 4\ncmp eax, ecx\njz short loc_1530\nloc_14EB:\ncmp [rdx], esi\njnz short loc_14E0\nloc_14EF:\ncmp ecx, eax\njz short loc_1530\nadd rdi, 4\ncmp rdi, r9\njnz short loc_14C8\nloc_14FC:\nadd rsp, 8\nmov edx, ecx\nmov rax, r8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1510:\nmov edx, [rdi]\nlea ecx, [rax+1]\nadd rdi, 4\ncdqe\nmov [r8+rax*4], edx\ncmp rdi, r9\njnz loc_1497\njmp short loc_14BC\nloc_1530:\nmov edx, [rdi]\nlea eax, [rcx+1]\nadd rdi, 4\nmovsxd rcx, ecx\nmov [r8+rcx*4], edx\nmov ecx, eax\ncmp rdi, r9\njnz short loc_14CE\nadd rsp, 8\nmov edx, ecx\nmov rax, r8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1557:\nxor ecx, ecx\njmp loc_14BC", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2, int *a3, int a4)\n{\n __int64 v4; // r12\n _DWORD *v6; // r8\n int *v7; // r9\n int v8; // ecx\n int v9; // eax\n _DWORD *v10; // rdx\n int *v11; // rdi\n int *v12; // r9\n int v13; // eax\n _DWORD *v14; // rdx\n int v16; // edx\n int v17; // edx\n\n v4 = a4;\n v6 = malloc(4LL * (a2 + a4));\n if ( a2 > 0 )\n {\n v7 = &a1[a2];\n v8 = 0;\n while ( 1 )\n {\n v9 = 0;\n if ( v8 <= 0 )\n goto LABEL_7;\n while ( 1 )\n {\n v10 = v6;\n v9 = 0;\n while ( *v10 != *a1 )\n {\n ++v9;\n ++v10;\n if ( v8 == v9 )\n goto LABEL_18;\n }\nLABEL_7:\n if ( v8 != v9 )\n break;\nLABEL_18:\n v16 = *a1;\n v8 = v9 + 1;\n ++a1;\n v6[v9] = v16;\n if ( a1 == v7 )\n goto LABEL_9;\n }\n if ( ++a1 == v7 )\n goto LABEL_9;\n }\n }\n v8 = 0;\nLABEL_9:\n if ( (int)v4 <= 0 )\n return v6;\n v11 = a3;\n v12 = &a3[v4];\nLABEL_11:\n v13 = 0;\n if ( v8 <= 0 )\n goto LABEL_15;\n do\n {\n v14 = v6;\n v13 = 0;\n while ( *v14 != *v11 )\n {\n ++v13;\n ++v14;\n if ( v13 == v8 )\n goto LABEL_20;\n }\nLABEL_15:\n if ( v8 != v13 )\n {\n if ( ++v11 == v12 )\n return v6;\n goto LABEL_11;\n }\nLABEL_20:\n v17 = *v11++;\n v6[v8++] = v17;\n }\n while ( v11 != v12 );\n return v6;\n}", + "ida_strip_asm": "sub_1450:\nendbr64\npush r13\nmovsxd r13, esi\npush r12\nmovsxd r12, ecx\npush rbp\nmov rbp, rdi\nlea edi, [r13+r12+0]\npush rbx\nmovsxd rdi, edi\nmov rbx, rdx\nshl rdi, 2; size\nsub rsp, 8\ncall _malloc\nmov r8, rax\ntest r13d, r13d\njle loc_1557\nmov rdi, rbp\nlea r9, [rbp+r13*4+0]\nxor ecx, ecx\nloc_1491:\nxor eax, eax\ntest ecx, ecx\njle short loc_14AF\nloc_1497:\nmov esi, [rdi]\nmov rdx, r8\nxor eax, eax\njmp short loc_14AB\nloc_14A0:\nadd eax, 1\nadd rdx, 4\ncmp ecx, eax\njz short loc_1510\nloc_14AB:\ncmp [rdx], esi\njnz short loc_14A0\nloc_14AF:\ncmp ecx, eax\njz short loc_1510\nadd rdi, 4\ncmp rdi, r9\njnz short loc_1491\nloc_14BC:\ntest r12d, r12d\njle short loc_14FC\nmov rdi, rbx\nlea r9, [rbx+r12*4]\nloc_14C8:\nxor eax, eax\ntest ecx, ecx\njle short loc_14EF\nloc_14CE:\nmov esi, [rdi]\nmov rdx, r8\nxor eax, eax\njmp short loc_14EB\nloc_14E0:\nadd eax, 1\nadd rdx, 4\ncmp eax, ecx\njz short loc_1530\nloc_14EB:\ncmp [rdx], esi\njnz short loc_14E0\nloc_14EF:\ncmp ecx, eax\njz short loc_1530\nadd rdi, 4\ncmp rdi, r9\njnz short loc_14C8\nloc_14FC:\nadd rsp, 8\nmov edx, ecx\nmov rax, r8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1510:\nmov edx, [rdi]\nlea ecx, [rax+1]\nadd rdi, 4\ncdqe\nmov [r8+rax*4], edx\ncmp rdi, r9\njnz loc_1497\njmp short loc_14BC\nloc_1530:\nmov edx, [rdi]\nlea eax, [rcx+1]\nadd rdi, 4\nmovsxd rcx, ecx\nmov [r8+rcx*4], edx\nmov ecx, eax\ncmp rdi, r9\njnz short loc_14CE\nadd rsp, 8\nmov edx, ecx\nmov rax, r8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1557:\nxor ecx, ecx\njmp loc_14BC", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1450(int *a1, int a2, int *a3, int a4)\n{\n __int64 v4; // r12\n _DWORD *v6; // r8\n int *v7; // r9\n int v8; // ecx\n int v9; // eax\n _DWORD *v10; // rdx\n int *v11; // rdi\n int *v12; // r9\n int v13; // eax\n _DWORD *v14; // rdx\n int v16; // edx\n int v17; // edx\n\n v4 = a4;\n v6 = malloc(4LL * (a2 + a4));\n if ( a2 > 0 )\n {\n v7 = &a1[a2];\n v8 = 0;\n while ( 1 )\n {\n v9 = 0;\n if ( v8 <= 0 )\n goto LABEL_7;\n while ( 1 )\n {\n v10 = v6;\n v9 = 0;\n while ( *v10 != *a1 )\n {\n ++v9;\n ++v10;\n if ( v8 == v9 )\n goto LABEL_18;\n }\nLABEL_7:\n if ( v8 != v9 )\n break;\nLABEL_18:\n v16 = *a1;\n v8 = v9 + 1;\n ++a1;\n v6[v9] = v16;\n if ( a1 == v7 )\n goto LABEL_9;\n }\n if ( ++a1 == v7 )\n goto LABEL_9;\n }\n }\n v8 = 0;\nLABEL_9:\n if ( (int)v4 <= 0 )\n return v6;\n v11 = a3;\n v12 = &a3[v4];\nLABEL_11:\n v13 = 0;\n if ( v8 <= 0 )\n goto LABEL_15;\n do\n {\n v14 = v6;\n v13 = 0;\n while ( *v14 != *v11 )\n {\n ++v13;\n ++v14;\n if ( v13 == v8 )\n goto LABEL_20;\n }\nLABEL_15:\n if ( v8 != v13 )\n {\n if ( ++v11 == v12 )\n return v6;\n goto LABEL_11;\n }\nLABEL_20:\n v17 = *v11++;\n v6[v8++] = v17;\n }\n while ( v11 != v12 );\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1450(int *a1, int a2, int *a3, int a4) {\n long long v4;\n uint32_t *v6;\n int *v7;\n int v8;\n int v9;\n uint32_t *v10;\n int *v11;\n int *v12;\n int v13;\n uint32_t *v14;\n int v16;\n int v17;\n v4 = a4;\n v6 = malloc(4LL * (a2 + a4));\n if (a2 > 0) {\n v7 = &a1[a2];\n v8 = 0;\n while (1) {\n v9 = 0;\n if (v8 <= 0) goto LABEL_7;\n while (1) {\n v10 = v6;\n v9 = 0;\n while (*v10 != *a1) {\n ++v9;\n ++v10;\n if (v8 == v9) goto LABEL_18;\n }\n LABEL_7:\n if (v8 != v9) break;\n LABEL_18:\n v16 = *a1;\n v8 = v9 + 1;\n ++a1;\n v6[v9] = v16;\n if (a1 == v7) goto LABEL_9;\n }\n if (++a1 == v7) goto LABEL_9;\n }\n }\n v8 = 0;\nLABEL_9:\n if ((int)v4 <= 0) return v6;\n v11 = a3;\n v12 = &a3[v4];\nLABEL_11:\n v13 = 0;\n if (v8 <= 0) goto LABEL_15;\n do {\n v14 = v6;\n v13 = 0;\n while (*v14 != *v11) {\n ++v13;\n ++v14;\n if (v13 == v8) goto LABEL_20;\n }\n LABEL_15:\n if (v8 != v13) {\n if (++v11 == v12) return v6;\n goto LABEL_11;\n }\n LABEL_20:\n v17 = *v11++;\n v6[v8++] = v17;\n } while (v11 != v12);\n return v6;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2, int *a3, int a4) {\n long long v4;\n uint32_t *v6;\n int *v7;\n int v8;\n int v9;\n uint32_t *v10;\n int *v11;\n int *v12;\n int v13;\n uint32_t *v14;\n int v16;\n int v17;\n v4 = a4;\n v6 = malloc(4LL * (a2 + a4));\n if (a2 > 0) {\n v7 = &a1[a2];\n v8 = 0;\n while (1) {\n v9 = 0;\n if (v8 <= 0) goto LABEL_7;\n while (1) {\n v10 = v6;\n v9 = 0;\n while (*v10 != *a1) {\n ++v9;\n ++v10;\n if (v8 == v9) goto LABEL_18;\n }\n LABEL_7:\n if (v8 != v9) break;\n LABEL_18:\n v16 = *a1;\n v8 = v9 + 1;\n ++a1;\n v6[v9] = v16;\n if (a1 == v7) goto LABEL_9;\n }\n if (++a1 == v7) goto LABEL_9;\n }\n }\n v8 = 0;\nLABEL_9:\n if ((int)v4 <= 0) return v6;\n v11 = a3;\n v12 = &a3[v4];\nLABEL_11:\n v13 = 0;\n if (v8 <= 0) goto LABEL_15;\n do {\n v14 = v6;\n v13 = 0;\n while (*v14 != *v11) {\n ++v13;\n ++v14;\n if (v13 == v8) goto LABEL_20;\n }\n LABEL_15:\n if (v8 != v13) {\n if (++v11 == v12) return v6;\n goto LABEL_11;\n }\n LABEL_20:\n v17 = *v11++;\n v6[v8++] = v17;\n } while (v11 != v12);\n return v6;\n}" + }, + { + "index": 561, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n#define MAX_ENTRIES 100\n\n#define MAX_VALUES 10\n\n\n\ntypedef struct {\n\n int key;\n\n int values[MAX_VALUES];\n\n int count;\n\n} map_entry;\n\n\n\ntypedef struct {\n\n map_entry entries[MAX_ENTRIES];\n\n int size;\n\n} map;\n\n\n\nint find_key(map* m, int key) {\n\n for(int i = 0; i < m->size; i++) {\n\n if(m->entries[i].key == key)\n\n return i;\n\n }\n\n return -1;\n\n}\n\n\n\n", + "func": "map func0(int test_keys[], int test_vals[], int n) {\n map res;\n res.size = 0;\n for (int i = 0; i < n; i++) {\n int key = test_keys[i];\n int val = test_vals[i];\n if (find_key(&res, val) == -1) {\n res.entries[res.size].key = val;\n res.entries[res.size].count = 0;\n res.size++;\n }\n int idx = find_key(&res, key);\n if (idx == -1) {\n res.entries[res.size].key = key;\n res.entries[res.size].count = 0;\n idx = res.size;\n res.size++;\n }\n if (res.entries[idx].count < MAX_VALUES) {\n res.entries[idx].values[res.entries[idx].count++] = val;\n }\n }\n return res;\n}", + "test": "int main(){\n\n // First test case\n\n int test1_keys[] = {5, 7, 2, 3, 8};\n\n int test1_vals[] = {3, 5, 7, 8, 4};\n\n int n1 = 5;\n\n map result1 = func0(test1_keys, test1_vals, n1);\n\n map expected1;\n\n expected1.size = 6;\n\n expected1.entries[0].key = 3; expected1.entries[0].count = 1; expected1.entries[0].values[0] = 8;\n\n expected1.entries[1].key = 5; expected1.entries[1].count = 1; expected1.entries[1].values[0] = 3;\n\n expected1.entries[2].key = 7; expected1.entries[2].count = 1; expected1.entries[2].values[0] = 5;\n\n expected1.entries[3].key = 2; expected1.entries[3].count = 1; expected1.entries[3].values[0] = 7;\n\n expected1.entries[4].key = 8; expected1.entries[4].count = 1; expected1.entries[4].values[0] = 4;\n\n expected1.entries[5].key = 4; expected1.entries[5].count = 0;\n\n \n\n assert(result1.size == expected1.size);\n\n for(int i = 0; i < result1.size; i++){\n\n int found = 0;\n\n for(int j = 0; j < expected1.size; j++){\n\n if(result1.entries[i].key == expected1.entries[j].key){\n\n assert(result1.entries[i].count == expected1.entries[j].count);\n\n for(int k = 0; k < result1.entries[i].count; k++){\n\n assert(result1.entries[i].values[k] == expected1.entries[j].values[k]);\n\n }\n\n found = 1;\n\n break;\n\n }\n\n }\n\n assert(found);\n\n }\n\n\n\n // Second test case\n\n int test2_keys[] = {6, 9, 3, 4, 9};\n\n int test2_vals[] = {4, 4, 8, 9, 5};\n\n int n2 = 5;\n\n map result2 = func0(test2_keys, test2_vals, n2);\n\n map expected2;\n\n expected2.size = 6;\n\n expected2.entries[0].key = 4; expected2.entries[0].count = 1; expected2.entries[0].values[0] = 9;\n\n expected2.entries[1].key = 6; expected2.entries[1].count = 1; expected2.entries[1].values[0] = 4;\n\n expected2.entries[2].key = 9; expected2.entries[2].count = 2; expected2.entries[2].values[0] = 4; expected2.entries[2].values[1] = 5;\n\n expected2.entries[3].key = 8; expected2.entries[3].count = 0;\n\n expected2.entries[4].key = 3; expected2.entries[4].count = 1; expected2.entries[4].values[0] = 8;\n\n expected2.entries[5].key = 5; expected2.entries[5].count = 0;\n\n \n\n assert(result2.size == expected2.size);\n\n for(int i = 0; i < result2.size; i++){\n\n int found = 0;\n\n for(int j = 0; j < expected2.size; j++){\n\n if(result2.entries[i].key == expected2.entries[j].key){\n\n assert(result2.entries[i].count == expected2.entries[j].count);\n\n for(int k = 0; k < result2.entries[i].count; k++){\n\n assert(result2.entries[i].values[k] == expected2.entries[j].values[k]);\n\n }\n\n found = 1;\n\n break;\n\n }\n\n }\n\n assert(found);\n\n }\n\n\n\n // Third test case\n\n int test3_keys[] = {6, 6, 4, 4, 3};\n\n int test3_vals[] = {2, 8, 9, 9, 7};\n\n int n3 = 5;\n\n map result3 = func0(test3_keys, test3_vals, n3);\n\n map expected3;\n\n expected3.size = 7;\n\n expected3.entries[0].key = 2; expected3.entries[0].count = 0;\n\n expected3.entries[1].key = 6; expected3.entries[1].count = 2; expected3.entries[1].values[0] = 2; expected3.entries[1].values[1] = 8;\n\n expected3.entries[2].key = 8; expected3.entries[2].count = 0;\n\n expected3.entries[3].key = 9; expected3.entries[3].count = 0;\n\n expected3.entries[4].key = 4; expected3.entries[4].count = 2; expected3.entries[4].values[0] = 9; expected3.entries[4].values[1] = 9;\n\n expected3.entries[5].key = 7; expected3.entries[5].count = 0;\n\n expected3.entries[6].key = 3; expected3.entries[6].count = 1; expected3.entries[6].values[0] = 7;\n\n \n\n assert(result3.size == expected3.size);\n\n for(int i = 0; i < result3.size; i++){\n\n int found = 0;\n\n for(int j = 0; j < expected3.size; j++){\n\n if(result3.entries[i].key == expected3.entries[j].key){\n\n assert(result3.entries[i].count == expected3.entries[j].count);\n\n for(int k = 0; k < result3.entries[i].count; k++){\n\n assert(result3.entries[i].values[k] == expected3.entries[j].values[k]);\n\n }\n\n found = 1;\n\n break;\n\n }\n\n }\n\n assert(found);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x1000,%rsp\norq $0x0,(%rsp)\nsub $0x300,%rsp\nmov %rdi,-0x12e8(%rbp)\nmov %rsi,-0x12f0(%rbp)\nmov %rdx,-0x12f8(%rbp)\nmov %ecx,-0x12fc(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovl $0x0,-0x10(%rbp)\nmovl $0x0,-0x12e0(%rbp)\njmpq 13e7 \nmov -0x12e0(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x12f0(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x12d8(%rbp)\nmov -0x12e0(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x12f8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x12d4(%rbp)\nmov -0x12d4(%rbp),%edx\nlea -0x12d0(%rbp),%rax\nmov %edx,%esi\nmov %rax,%rdi\ncallq 1169 \ncmp $0xffffffff,%eax\njne 12cc \nmov -0x10(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x4,%rax\nadd %rbp,%rax\nlea -0x12d0(%rax),%rdx\nmov -0x12d4(%rbp),%eax\nmov %eax,(%rdx)\nmov -0x10(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x4,%rax\nadd %rbp,%rax\nsub $0x12a4,%rax\nmovl $0x0,(%rax)\nmov -0x10(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x10(%rbp)\nmov -0x12d8(%rbp),%edx\nlea -0x12d0(%rbp),%rax\nmov %edx,%esi\nmov %rax,%rdi\ncallq 1169 \nmov %eax,-0x12dc(%rbp)\ncmpl $0xffffffff,-0x12dc(%rbp)\njne 134b \nmov -0x10(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x4,%rax\nadd %rbp,%rax\nlea -0x12d0(%rax),%rdx\nmov -0x12d8(%rbp),%eax\nmov %eax,(%rdx)\nmov -0x10(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x4,%rax\nadd %rbp,%rax\nsub $0x12a4,%rax\nmovl $0x0,(%rax)\nmov -0x10(%rbp),%eax\nmov %eax,-0x12dc(%rbp)\nmov -0x10(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x10(%rbp)\nmov -0x12dc(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x4,%rax\nadd %rbp,%rax\nsub $0x12a4,%rax\nmov (%rax),%eax\ncmp $0x9,%eax\njg 13e0 \nmov -0x12dc(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x4,%rax\nadd %rbp,%rax\nsub $0x12a4,%rax\nmov (%rax),%edx\nlea 0x1(%rdx),%esi\nmov -0x12dc(%rbp),%eax\nmovslq %eax,%rcx\nmov %rcx,%rax\nadd %rax,%rax\nadd %rcx,%rax\nshl $0x4,%rax\nadd %rbp,%rax\nsub $0x12a4,%rax\nmov %esi,(%rax)\nmovslq %edx,%rcx\nmov -0x12dc(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nlea (%rax,%rcx,1),%rdx\nmov -0x12d4(%rbp),%eax\nmov %eax,-0x12cc(%rbp,%rdx,4)\naddl $0x1,-0x12e0(%rbp)\nmov -0x12e0(%rbp),%eax\ncmp -0x12fc(%rbp),%eax\njl 121c \nmov -0x12e8(%rbp),%rax\nmov %rax,%rdx\nlea -0x12d0(%rbp),%rax\nmov $0x12c4,%ecx\nmov (%rax),%rsi\nmov %rsi,(%rdx)\nmov %ecx,%esi\nadd %rdx,%rsi\nlea 0x8(%rsi),%rdi\nmov %ecx,%esi\nadd %rax,%rsi\nadd $0x8,%rsi\nmov -0x10(%rsi),%rsi\nmov %rsi,-0x10(%rdi)\nlea 0x8(%rdx),%rdi\nand $0xfffffffffffffff8,%rdi\nsub %rdi,%rdx\nsub %rdx,%rax\nadd %edx,%ecx\nand $0xfffffff8,%ecx\nshr $0x3,%ecx\nmov %ecx,%edx\nmov %edx,%edx\nmov %rax,%rsi\nmov %rdx,%rcx\nrep movsq %ds:(%rsi),%es:(%rdi)\nmov -0x8(%rbp),%rax\nxor %fs:0x28,%rax\nje 1466 \ncallq 1060 <__stack_chk_fail@plt>\nmov -0x12e8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 1000h\nor [rsp+1000h+var_1000], 0\nsub rsp, 300h\nmov [rbp+var_12E8], rdi\nmov [rbp+var_12F0], rsi\nmov [rbp+var_12F8], rdx\nmov [rbp+var_12FC], ecx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_10], 0\nmov [rbp+var_12E0], 0\njmp loc_13E7\nloc_121C:\nmov eax, [rbp+var_12E0]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_12F0]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_12D8], eax\nmov eax, [rbp+var_12E0]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_12F8]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_12D4], eax\nmov edx, [rbp+var_12D4]\nlea rax, [rbp+var_12D0]\nmov esi, edx\nmov rdi, rax\ncall find_key\ncmp eax, 0FFFFFFFFh\njnz short loc_12CC\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 4\nadd rax, rbp\nlea rdx, [rax-12D0h]\nmov eax, [rbp+var_12D4]\nmov [rdx], eax\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 4\nadd rax, rbp\nsub rax, 12A4h\nmov dword ptr [rax], 0\nmov eax, [rbp+var_10]\nadd eax, 1\nmov [rbp+var_10], eax\nloc_12CC:\nmov edx, [rbp+var_12D8]\nlea rax, [rbp+var_12D0]\nmov esi, edx\nmov rdi, rax\ncall find_key\nmov [rbp+var_12DC], eax\ncmp [rbp+var_12DC], 0FFFFFFFFh\njnz short loc_134B\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 4\nadd rax, rbp\nlea rdx, [rax-12D0h]\nmov eax, [rbp+var_12D8]\nmov [rdx], eax\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 4\nadd rax, rbp\nsub rax, 12A4h\nmov dword ptr [rax], 0\nmov eax, [rbp+var_10]\nmov [rbp+var_12DC], eax\nmov eax, [rbp+var_10]\nadd eax, 1\nmov [rbp+var_10], eax\nloc_134B:\nmov eax, [rbp+var_12DC]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 4\nadd rax, rbp\nsub rax, 12A4h\nmov eax, [rax]\ncmp eax, 9\njg short loc_13E0\nmov eax, [rbp+var_12DC]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 4\nadd rax, rbp\nsub rax, 12A4h\nmov edx, [rax]\nlea esi, [rdx+1]\nmov eax, [rbp+var_12DC]\nmovsxd rcx, eax\nmov rax, rcx\nadd rax, rax\nadd rax, rcx\nshl rax, 4\nadd rax, rbp\nsub rax, 12A4h\nmov [rax], esi\nmovsxd rcx, edx\nmov eax, [rbp+var_12DC]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nlea rdx, [rax+rcx]\nmov eax, [rbp+var_12D4]\nmov [rbp+rdx*4+var_12CC], eax\nloc_13E0:\nadd [rbp+var_12E0], 1\nloc_13E7:\nmov eax, [rbp+var_12E0]\ncmp eax, [rbp+var_12FC]\njl loc_121C\nmov rax, [rbp+var_12E8]\nmov rdx, rax\nlea rax, [rbp+var_12D0]\nmov ecx, 12C4h\nmov rsi, [rax]\nmov [rdx], rsi\nmov esi, ecx\nadd rsi, rdx\nlea rdi, [rsi+8]\nmov esi, ecx\nadd rsi, rax\nadd rsi, 8\nmov rsi, [rsi-10h]\nmov [rdi-10h], rsi\nlea rdi, [rdx+8]\nand rdi, 0FFFFFFFFFFFFFFF8h\nsub rdx, rdi\nsub rax, rdx\nadd ecx, edx\nand ecx, 0FFFFFFF8h\nshr ecx, 3\nmov edx, ecx\nmov edx, edx\nmov rsi, rax\nmov rcx, rdx\nrep movsq\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njz short loc_1466\ncall ___stack_chk_fail\nloc_1466:\nmov rax, [rbp+var_12E8]\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(_QWORD *a1, __int64 a2, __int64 a3, int a4)\n{\n int v4; // edx\n int i; // [rsp+20h] [rbp-12E0h]\n int key; // [rsp+24h] [rbp-12DCh]\n unsigned int v10; // [rsp+28h] [rbp-12D8h]\n unsigned int v11; // [rsp+2Ch] [rbp-12D4h]\n _QWORD v12[90]; // [rsp+30h] [rbp-12D0h] BYREF\n __int64 v13; // [rsp+12ECh] [rbp-14h]\n unsigned __int64 v14; // [rsp+12F8h] [rbp-8h]\n\n v14 = __readfsqword(0x28u);\n HIDWORD(v13) = 0;\n for ( i = 0; i < a4; ++i )\n {\n v10 = *(_DWORD *)(4LL * i + a2);\n v11 = *(_DWORD *)(4LL * i + a3);\n if ( (unsigned int)find_key(v12, v11) == -1 )\n {\n LODWORD(v12[6 * SHIDWORD(v13)]) = v11;\n HIDWORD(v12[6 * SHIDWORD(v13) + 5]) = 0;\n ++HIDWORD(v13);\n }\n key = find_key(v12, v10);\n if ( key == -1 )\n {\n LODWORD(v12[6 * SHIDWORD(v13)]) = v10;\n HIDWORD(v12[6 * SHIDWORD(v13) + 5]) = 0;\n key = HIDWORD(v13)++;\n }\n if ( SHIDWORD(v12[6 * key + 5]) <= 9 )\n {\n v4 = HIDWORD(v12[6 * key + 5]);\n HIDWORD(v12[6 * key + 5]) = v4 + 1;\n *((_DWORD *)&v12[6 * key] + v4 + 1) = v11;\n }\n }\n *a1 = v12[0];\n *(_QWORD *)((char *)a1 + 4796) = v13;\n qmemcpy(\n (void *)((unsigned __int64)(a1 + 1) & 0xFFFFFFFFFFFFFFF8LL),\n (const void *)((char *)v12 - ((char *)a1 - ((unsigned __int64)(a1 + 1) & 0xFFFFFFFFFFFFFFF8LL))),\n 8LL * ((((_DWORD)a1 - (((_DWORD)a1 + 8) & 0xFFFFFFF8) + 4804) & 0xFFFFFFF8) >> 3));\n return a1;\n}", + "ida_strip_asm": "sub_11C1:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 1000h\nor [rsp+1000h+var_1000], 0\nsub rsp, 300h\nmov [rbp+var_12E8], rdi\nmov [rbp+var_12F0], rsi\nmov [rbp+var_12F8], rdx\nmov [rbp+var_12FC], ecx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_10], 0\nmov [rbp+var_12E0], 0\njmp loc_13E7\nloc_121C:\nmov eax, [rbp+var_12E0]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_12F0]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_12D8], eax\nmov eax, [rbp+var_12E0]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_12F8]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_12D4], eax\nmov edx, [rbp+var_12D4]\nlea rax, [rbp+var_12D0]\nmov esi, edx\nmov rdi, rax\ncall sub_1169\ncmp eax, 0FFFFFFFFh\njnz short loc_12CC\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 4\nadd rax, rbp\nlea rdx, [rax-12D0h]\nmov eax, [rbp+var_12D4]\nmov [rdx], eax\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 4\nadd rax, rbp\nsub rax, 12A4h\nmov dword ptr [rax], 0\nmov eax, [rbp+var_10]\nadd eax, 1\nmov [rbp+var_10], eax\nloc_12CC:\nmov edx, [rbp+var_12D8]\nlea rax, [rbp+var_12D0]\nmov esi, edx\nmov rdi, rax\ncall sub_1169\nmov [rbp+var_12DC], eax\ncmp [rbp+var_12DC], 0FFFFFFFFh\njnz short loc_134B\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 4\nadd rax, rbp\nlea rdx, [rax-12D0h]\nmov eax, [rbp+var_12D8]\nmov [rdx], eax\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 4\nadd rax, rbp\nsub rax, 12A4h\nmov dword ptr [rax], 0\nmov eax, [rbp+var_10]\nmov [rbp+var_12DC], eax\nmov eax, [rbp+var_10]\nadd eax, 1\nmov [rbp+var_10], eax\nloc_134B:\nmov eax, [rbp+var_12DC]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 4\nadd rax, rbp\nsub rax, 12A4h\nmov eax, [rax]\ncmp eax, 9\njg short loc_13E0\nmov eax, [rbp+var_12DC]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 4\nadd rax, rbp\nsub rax, 12A4h\nmov edx, [rax]\nlea esi, [rdx+1]\nmov eax, [rbp+var_12DC]\nmovsxd rcx, eax\nmov rax, rcx\nadd rax, rax\nadd rax, rcx\nshl rax, 4\nadd rax, rbp\nsub rax, 12A4h\nmov [rax], esi\nmovsxd rcx, edx\nmov eax, [rbp+var_12DC]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nlea rdx, [rax+rcx]\nmov eax, [rbp+var_12D4]\nmov [rbp+rdx*4+var_12CC], eax\nloc_13E0:\nadd [rbp+var_12E0], 1\nloc_13E7:\nmov eax, [rbp+var_12E0]\ncmp eax, [rbp+var_12FC]\njl loc_121C\nmov rax, [rbp+var_12E8]\nmov rdx, rax\nlea rax, [rbp+var_12D0]\nmov ecx, 12C4h\nmov rsi, [rax]\nmov [rdx], rsi\nmov esi, ecx\nadd rsi, rdx\nlea rdi, [rsi+8]\nmov esi, ecx\nadd rsi, rax\nadd rsi, 8\nmov rsi, [rsi-10h]\nmov [rdi-10h], rsi\nlea rdi, [rdx+8]\nand rdi, 0FFFFFFFFFFFFFFF8h\nsub rdx, rdi\nsub rax, rdx\nadd ecx, edx\nand ecx, 0FFFFFFF8h\nshr ecx, 3\nmov edx, ecx\nmov edx, edx\nmov rsi, rax\nmov rcx, rdx\nrep movsq\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njz short loc_1466\ncall ___stack_chk_fail\nloc_1466:\nmov rax, [rbp+var_12E8]\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11C1(_QWORD *a1, __int64 a2, __int64 a3, int a4)\n{\n int v4; // edx\n int i; // [rsp+20h] [rbp-12E0h]\n int v9; // [rsp+24h] [rbp-12DCh]\n unsigned int v10; // [rsp+28h] [rbp-12D8h]\n unsigned int v11; // [rsp+2Ch] [rbp-12D4h]\n _QWORD v12[90]; // [rsp+30h] [rbp-12D0h] BYREF\n __int64 v13; // [rsp+12ECh] [rbp-14h]\n unsigned __int64 v14; // [rsp+12F8h] [rbp-8h]\n\n v14 = __readfsqword(0x28u);\n HIDWORD(v13) = 0;\n for ( i = 0; i < a4; ++i )\n {\n v10 = *(_DWORD *)(4LL * i + a2);\n v11 = *(_DWORD *)(4LL * i + a3);\n if ( (unsigned int)sub_1169(v12, v11) == -1 )\n {\n LODWORD(v12[6 * SHIDWORD(v13)]) = v11;\n HIDWORD(v12[6 * SHIDWORD(v13) + 5]) = 0;\n ++HIDWORD(v13);\n }\n v9 = sub_1169(v12, v10);\n if ( v9 == -1 )\n {\n LODWORD(v12[6 * SHIDWORD(v13)]) = v10;\n HIDWORD(v12[6 * SHIDWORD(v13) + 5]) = 0;\n v9 = HIDWORD(v13)++;\n }\n if ( SHIDWORD(v12[6 * v9 + 5]) <= 9 )\n {\n v4 = HIDWORD(v12[6 * v9 + 5]);\n HIDWORD(v12[6 * v9 + 5]) = v4 + 1;\n *((_DWORD *)&v12[6 * v9] + v4 + 1) = v11;\n }\n }\n *a1 = v12[0];\n *(_QWORD *)((char *)a1 + 4796) = v13;\n qmemcpy(\n (void *)((unsigned __int64)(a1 + 1) & 0xFFFFFFFFFFFFFFF8LL),\n (const void *)((char *)v12 - ((char *)a1 - ((unsigned __int64)(a1 + 1) & 0xFFFFFFFFFFFFFFF8LL))),\n 8LL * ((((_DWORD)a1 - (((_DWORD)a1 + 8) & 0xFFFFFFF8) + 4804) & 0xFFFFFFF8) >> 3));\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11C1(uint64_t *a1, long long a2, long long a3, int a4) {\n int v4;\n int i;\n int v9;\n unsigned int v10;\n unsigned int v11;\n uint64_t v12[90];\n long long v13;\n unsigned long long v14;\n v14 = __readfsqword(40u);\n HIDWORD(v13) = 0;\n for (i = 0; i < a4; ++i) {\n v10 = *(uint32_t *)(4LL * i + a2);\n v11 = *(uint32_t *)(4LL * i + a3);\n if ((unsigned int)sub_1169(v12, v11) == -1) {\n LODWORD(v12[6 * SHIDWORD(v13)]) = v11;\n HIDWORD(v12[6 * SHIDWORD(v13) + 5]) = 0;\n ++HIDWORD(v13);\n }\n v9 = sub_1169(v12, v10);\n if (v9 == -1) {\n LODWORD(v12[6 * SHIDWORD(v13)]) = v10;\n HIDWORD(v12[6 * SHIDWORD(v13) + 5]) = 0;\n v9 = HIDWORD(v13)++;\n }\n if (SHIDWORD(v12[6 * v9 + 5]) <= 9) {\n v4 = HIDWORD(v12[6 * v9 + 5]);\n HIDWORD(v12[6 * v9 + 5]) = v4 + 1;\n *((uint32_t *)&v12[6 * v9] + v4 + 1) = v11;\n }\n }\n *a1 = v12[0];\n *(uint64_t *)((char *)a1 + 4796) = v13;\n qmemcpy(\n (void *)((unsigned long long)(a1 + 1) & 18446744073709551608LL),\n (const void *)((char *)v12 - ((char *)a1 - ((unsigned long long)(a1 + 1) &\n 18446744073709551608LL))),\n 8LL * ((((uint32_t)a1 - (((uint32_t)a1 + 8) & 4294967288) + 4804) &\n 4294967288) >>\n 3));\n return a1;\n}", + "ida_pseudo_norm": "uint64_t *func0(uint64_t *a1, long long a2, long long a3, int a4) {\n int v4;\n int i;\n int key;\n unsigned int v10;\n unsigned int v11;\n uint64_t v12[90];\n long long v13;\n unsigned long long v14;\n v14 = __readfsqword(40u);\n HIDWORD(v13) = 0;\n for (i = 0; i < a4; ++i) {\n v10 = *(uint32_t *)(4LL * i + a2);\n v11 = *(uint32_t *)(4LL * i + a3);\n if ((unsigned int)find_key(v12, v11) == -1) {\n LODWORD(v12[6 * SHIDWORD(v13)]) = v11;\n HIDWORD(v12[6 * SHIDWORD(v13) + 5]) = 0;\n ++HIDWORD(v13);\n }\n key = find_key(v12, v10);\n if (key == -1) {\n LODWORD(v12[6 * SHIDWORD(v13)]) = v10;\n HIDWORD(v12[6 * SHIDWORD(v13) + 5]) = 0;\n key = HIDWORD(v13)++;\n }\n if (SHIDWORD(v12[6 * key + 5]) <= 9) {\n v4 = HIDWORD(v12[6 * key + 5]);\n HIDWORD(v12[6 * key + 5]) = v4 + 1;\n *((uint32_t *)&v12[6 * key] + v4 + 1) = v11;\n }\n }\n *a1 = v12[0];\n *(uint64_t *)((char *)a1 + 4796) = v13;\n qmemcpy(\n (void *)((unsigned long long)(a1 + 1) & 18446744073709551608LL),\n (const void *)((char *)v12 - ((char *)a1 - ((unsigned long long)(a1 + 1) &\n 18446744073709551608LL))),\n 8LL * ((((uint32_t)a1 - (((uint32_t)a1 + 8) & 4294967288) + 4804) &\n 4294967288) >>\n 3));\n return a1;\n}" + }, + { + "index": 561, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n#define MAX_ENTRIES 100\n\n#define MAX_VALUES 10\n\n\n\ntypedef struct {\n\n int key;\n\n int values[MAX_VALUES];\n\n int count;\n\n} map_entry;\n\n\n\ntypedef struct {\n\n map_entry entries[MAX_ENTRIES];\n\n int size;\n\n} map;\n\n\n\nint find_key(map* m, int key) {\n\n for(int i = 0; i < m->size; i++) {\n\n if(m->entries[i].key == key)\n\n return i;\n\n }\n\n return -1;\n\n}\n\n\n\n", + "func": "map func0(int test_keys[], int test_vals[], int n) {\n map res;\n res.size = 0;\n for (int i = 0; i < n; i++) {\n int key = test_keys[i];\n int val = test_vals[i];\n if (find_key(&res, val) == -1) {\n res.entries[res.size].key = val;\n res.entries[res.size].count = 0;\n res.size++;\n }\n int idx = find_key(&res, key);\n if (idx == -1) {\n res.entries[res.size].key = key;\n res.entries[res.size].count = 0;\n idx = res.size;\n res.size++;\n }\n if (res.entries[idx].count < MAX_VALUES) {\n res.entries[idx].values[res.entries[idx].count++] = val;\n }\n }\n return res;\n}", + "test": "int main(){\n\n // First test case\n\n int test1_keys[] = {5, 7, 2, 3, 8};\n\n int test1_vals[] = {3, 5, 7, 8, 4};\n\n int n1 = 5;\n\n map result1 = func0(test1_keys, test1_vals, n1);\n\n map expected1;\n\n expected1.size = 6;\n\n expected1.entries[0].key = 3; expected1.entries[0].count = 1; expected1.entries[0].values[0] = 8;\n\n expected1.entries[1].key = 5; expected1.entries[1].count = 1; expected1.entries[1].values[0] = 3;\n\n expected1.entries[2].key = 7; expected1.entries[2].count = 1; expected1.entries[2].values[0] = 5;\n\n expected1.entries[3].key = 2; expected1.entries[3].count = 1; expected1.entries[3].values[0] = 7;\n\n expected1.entries[4].key = 8; expected1.entries[4].count = 1; expected1.entries[4].values[0] = 4;\n\n expected1.entries[5].key = 4; expected1.entries[5].count = 0;\n\n \n\n assert(result1.size == expected1.size);\n\n for(int i = 0; i < result1.size; i++){\n\n int found = 0;\n\n for(int j = 0; j < expected1.size; j++){\n\n if(result1.entries[i].key == expected1.entries[j].key){\n\n assert(result1.entries[i].count == expected1.entries[j].count);\n\n for(int k = 0; k < result1.entries[i].count; k++){\n\n assert(result1.entries[i].values[k] == expected1.entries[j].values[k]);\n\n }\n\n found = 1;\n\n break;\n\n }\n\n }\n\n assert(found);\n\n }\n\n\n\n // Second test case\n\n int test2_keys[] = {6, 9, 3, 4, 9};\n\n int test2_vals[] = {4, 4, 8, 9, 5};\n\n int n2 = 5;\n\n map result2 = func0(test2_keys, test2_vals, n2);\n\n map expected2;\n\n expected2.size = 6;\n\n expected2.entries[0].key = 4; expected2.entries[0].count = 1; expected2.entries[0].values[0] = 9;\n\n expected2.entries[1].key = 6; expected2.entries[1].count = 1; expected2.entries[1].values[0] = 4;\n\n expected2.entries[2].key = 9; expected2.entries[2].count = 2; expected2.entries[2].values[0] = 4; expected2.entries[2].values[1] = 5;\n\n expected2.entries[3].key = 8; expected2.entries[3].count = 0;\n\n expected2.entries[4].key = 3; expected2.entries[4].count = 1; expected2.entries[4].values[0] = 8;\n\n expected2.entries[5].key = 5; expected2.entries[5].count = 0;\n\n \n\n assert(result2.size == expected2.size);\n\n for(int i = 0; i < result2.size; i++){\n\n int found = 0;\n\n for(int j = 0; j < expected2.size; j++){\n\n if(result2.entries[i].key == expected2.entries[j].key){\n\n assert(result2.entries[i].count == expected2.entries[j].count);\n\n for(int k = 0; k < result2.entries[i].count; k++){\n\n assert(result2.entries[i].values[k] == expected2.entries[j].values[k]);\n\n }\n\n found = 1;\n\n break;\n\n }\n\n }\n\n assert(found);\n\n }\n\n\n\n // Third test case\n\n int test3_keys[] = {6, 6, 4, 4, 3};\n\n int test3_vals[] = {2, 8, 9, 9, 7};\n\n int n3 = 5;\n\n map result3 = func0(test3_keys, test3_vals, n3);\n\n map expected3;\n\n expected3.size = 7;\n\n expected3.entries[0].key = 2; expected3.entries[0].count = 0;\n\n expected3.entries[1].key = 6; expected3.entries[1].count = 2; expected3.entries[1].values[0] = 2; expected3.entries[1].values[1] = 8;\n\n expected3.entries[2].key = 8; expected3.entries[2].count = 0;\n\n expected3.entries[3].key = 9; expected3.entries[3].count = 0;\n\n expected3.entries[4].key = 4; expected3.entries[4].count = 2; expected3.entries[4].values[0] = 9; expected3.entries[4].values[1] = 9;\n\n expected3.entries[5].key = 7; expected3.entries[5].count = 0;\n\n expected3.entries[6].key = 3; expected3.entries[6].count = 1; expected3.entries[6].values[0] = 7;\n\n \n\n assert(result3.size == expected3.size);\n\n for(int i = 0; i < result3.size; i++){\n\n int found = 0;\n\n for(int j = 0; j < expected3.size; j++){\n\n if(result3.entries[i].key == expected3.entries[j].key){\n\n assert(result3.entries[i].count == expected3.entries[j].count);\n\n for(int k = 0; k < result3.entries[i].count; k++){\n\n assert(result3.entries[i].values[k] == expected3.entries[j].values[k]);\n\n }\n\n found = 1;\n\n break;\n\n }\n\n }\n\n assert(found);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x1000,%rsp\norq $0x0,(%rsp)\nsub $0x2e8,%rsp\nmov %rdi,0x8(%rsp)\nmov %fs:0x28,%rax\nmov %rax,0x12d8(%rsp)\nxor %eax,%eax\nmovl $0x0,0x12d0(%rsp)\ntest %ecx,%ecx\njle 12d4 \nmov %rsi,%r14\nmov %rdx,%r15\nlea -0x1(%rcx),%eax\nmov %rax,(%rsp)\nmov $0x0,%ebx\nlea 0x10(%rsp),%r13\njmpq 128f \nmov 0x12d0(%rsp),%edx\nmovslq %edx,%rcx\nlea (%rcx,%rcx,1),%rax\nlea (%rax,%rcx,1),%rsi\nshl $0x4,%rsi\nmov %ebp,0x10(%rsp,%rsi,1)\nmovl $0x0,0x3c(%rsp,%rsi,1)\nadd $0x1,%edx\nmov %edx,0x12d0(%rsp)\njmp 12aa \nmov 0x12d0(%rsp),%eax\nmovslq %eax,%rcx\nlea (%rcx,%rcx,1),%rdx\nlea (%rdx,%rcx,1),%rsi\nshl $0x4,%rsi\nmov %r12d,0x10(%rsp,%rsi,1)\nmovl $0x0,0x3c(%rsp,%rsi,1)\nlea 0x1(%rax),%edx\nmov %edx,0x12d0(%rsp)\nmov $0x0,%edx\ncltq\nlea (%rax,%rax,1),%rcx\nlea (%rcx,%rax,1),%rsi\nshl $0x4,%rsi\nlea 0x1(%rdx),%edi\nmov %edi,0x3c(%rsp,%rsi,1)\nmovslq %edx,%rdx\nadd %rcx,%rax\nlea (%rdx,%rax,4),%rax\nmov %ebp,0x14(%rsp,%rax,4)\nlea 0x1(%rbx),%rax\ncmp (%rsp),%rbx\nje 12d4 \nmov %rax,%rbx\nmov (%r14,%rbx,4),%r12d\nmov (%r15,%rbx,4),%ebp\nmov %ebp,%esi\nmov %r13,%rdi\ncallq 1169 \ncmp $0xffffffff,%eax\nje 11ff \nmov %r12d,%esi\nmov %r13,%rdi\ncallq 1169 \ncmp $0xffffffff,%eax\nje 122d \nmovslq %eax,%rdx\nlea (%rdx,%rdx,2),%rdx\nshl $0x4,%rdx\nmov 0x3c(%rsp,%rdx,1),%edx\ncmp $0x9,%edx\njg 1282 \njmp 125f \nlea 0x10(%rsp),%rsi\nmov 0x10(%rsp),%rax\nmov 0x8(%rsp),%rbx\nmov %rax,(%rbx)\nmov 0x12cc(%rsp),%rax\nmov %rax,0x12bc(%rbx)\nmov %rbx,%rax\nlea 0x8(%rbx),%rdi\nand $0xfffffffffffffff8,%rdi\nsub %rdi,%rax\nmov %rax,%rcx\nsub %rax,%rsi\nadd $0x12c4,%ecx\nshr $0x3,%ecx\nmov %ecx,%ecx\nrep movsq %ds:(%rsi),%es:(%rdi)\nmov 0x12d8(%rsp),%rax\nxor %fs:0x28,%rax\njne 1341 \nmov 0x8(%rsp),%rax\nadd $0x12e8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 1000h\nor [rsp+1030h+var_1030], 0\nsub rsp, 2E8h\nmov [rsp+1318h+var_1310], rdi\nmov rax, fs:28h\nmov [rsp+1318h+var_40], rax\nxor eax, eax\nmov [rsp+1318h+var_48], 0\ntest ecx, ecx\njle loc_12D1\nmov rbx, rsi\nmov rbp, rdx\nmovsxd rcx, ecx\nlea r15, [rsi+rcx*4]\nlea r14, [rsp+1318h+var_1308]\njmp loc_128C\nloc_11FA:\nmov edx, [rsp+1318h+var_48]\nmovsxd rcx, edx\nlea rax, [rcx+rcx]\nlea rsi, [rax+rcx]\nshl rsi, 4\nmov dword ptr [rsp+rsi+1318h+var_1308], r12d\nmov [rsp+rsi+1318h+var_12DC], 0\nadd edx, 1\nmov [rsp+1318h+var_48], edx\njmp short loc_12A7\nloc_1229:\nmov eax, [rsp+1318h+var_48]\nmovsxd rcx, eax\nlea rdx, [rcx+rcx]\nlea rsi, [rdx+rcx]\nshl rsi, 4\nmov dword ptr [rsp+rsi+1318h+var_1308], r13d\nmov [rsp+rsi+1318h+var_12DC], 0\nlea edx, [rax+1]\nmov [rsp+1318h+var_48], edx\nmov edx, 0\nloc_125B:\ncdqe\nlea rcx, [rax+rax]\nlea rsi, [rcx+rax]\nshl rsi, 4\nlea edi, [rdx+1]\nmov [rsp+rsi+1318h+var_12DC], edi\nmovsxd rdx, edx\nadd rcx, rax\nlea rax, [rdx+rcx*4]\nmov dword ptr [rsp+rax*4+1318h+var_1308+4], r12d\nloc_127F:\nadd rbx, 4\nadd rbp, 4\ncmp rbx, r15\njz short loc_12D1\nloc_128C:\nmov r13d, [rbx]\nmov r12d, [rbp+0]\nmov esi, r12d\nmov rdi, r14\ncall find_key\ncmp eax, 0FFFFFFFFh\njz loc_11FA\nloc_12A7:\nmov esi, r13d\nmov rdi, r14\ncall find_key\ncmp eax, 0FFFFFFFFh\njz loc_1229\nmovsxd rdx, eax\nlea rdx, [rdx+rdx*2]\nshl rdx, 4\nmov edx, [rsp+rdx+1318h+var_12DC]\ncmp edx, 9\njg short loc_127F\njmp short loc_125B\nloc_12D1:\nlea rsi, [rsp+1318h+var_1308]\nmov rax, [rsp+1318h+var_1308]\nmov rbx, [rsp+1318h+var_1310]\nmov [rbx], rax\nmov rax, [rsp+12CCh]\nmov [rbx+12BCh], rax\nmov rax, rbx\nlea rdi, [rbx+8]\nand rdi, 0FFFFFFFFFFFFFFF8h\nsub rax, rdi\nmov rcx, rax\nsub rsi, rax\nadd ecx, 12C4h\nshr ecx, 3\nmov ecx, ecx\nrep movsq\nmov rax, [rsp+1318h+var_40]\nsub rax, fs:28h\njnz short loc_133E\nmov rax, [rsp+1318h+var_1310]\nadd rsp, 12E8h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_133E:\ncall ___stack_chk_fail", + "ida_pseudo": "_QWORD *__fastcall func0(_QWORD *a1, unsigned int *a2, unsigned int *a3, int a4)\n{\n unsigned int *v4; // rbx\n unsigned int *v6; // r15\n int v7; // edx\n __int64 v8; // rsi\n int key; // eax\n __int64 v10; // rsi\n int v11; // edx\n unsigned int v12; // r13d\n int v13; // r12d\n _QWORD v15[91]; // [rsp+10h] [rbp-1308h] BYREF\n __int64 v16; // [rsp+12CCh] [rbp-4Ch]\n unsigned __int64 v17; // [rsp+12D8h] [rbp-40h]\n\n v17 = __readfsqword(0x28u);\n HIDWORD(v16) = 0;\n if ( a4 > 0 )\n {\n v4 = a2;\n v6 = &a2[a4];\n do\n {\n v12 = *v4;\n v13 = *a3;\n if ( (unsigned int)find_key(v15, *a3) == -1 )\n {\n v7 = HIDWORD(v16);\n v8 = 6LL * SHIDWORD(v16);\n LODWORD(v15[v8]) = v13;\n HIDWORD(v15[v8 + 5]) = 0;\n HIDWORD(v16) = v7 + 1;\n }\n key = find_key(v15, v12);\n if ( key == -1 )\n {\n key = HIDWORD(v16);\n v10 = 6LL * SHIDWORD(v16);\n LODWORD(v15[v10]) = v12;\n HIDWORD(v15[v10 + 5]) = 0;\n HIDWORD(v16) = key + 1;\n v11 = 0;\n }\n else\n {\n v11 = HIDWORD(v15[6 * key + 5]);\n if ( v11 > 9 )\n goto LABEL_5;\n }\n HIDWORD(v15[6 * key + 5]) = v11 + 1;\n *((_DWORD *)&v15[6 * key] + v11 + 1) = v13;\nLABEL_5:\n ++v4;\n ++a3;\n }\n while ( v4 != v6 );\n }\n *a1 = v15[0];\n *(_QWORD *)((char *)a1 + 4796) = v16;\n qmemcpy(\n (void *)((unsigned __int64)(a1 + 1) & 0xFFFFFFFFFFFFFFF8LL),\n (const void *)((char *)v15 - ((char *)a1 - ((unsigned __int64)(a1 + 1) & 0xFFFFFFFFFFFFFFF8LL))),\n 8LL * (((unsigned int)a1 - (((_DWORD)a1 + 8) & 0xFFFFFFF8) + 4804) >> 3));\n return a1;\n}", + "ida_strip_asm": "sub_1197:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 1000h\nor [rsp+1030h+var_1030], 0\nsub rsp, 2E8h\nmov [rsp+1318h+var_1310], rdi\nmov rax, fs:28h\nmov [rsp+1318h+var_40], rax\nxor eax, eax\nmov [rsp+1318h+var_48], 0\ntest ecx, ecx\njle loc_12D1\nmov rbx, rsi\nmov rbp, rdx\nmovsxd rcx, ecx\nlea r15, [rsi+rcx*4]\nlea r14, [rsp+1318h+var_1308]\njmp loc_128C\nloc_11FA:\nmov edx, [rsp+1318h+var_48]\nmovsxd rcx, edx\nlea rax, [rcx+rcx]\nlea rsi, [rax+rcx]\nshl rsi, 4\nmov dword ptr [rsp+rsi+1318h+var_1308], r12d\nmov [rsp+rsi+1318h+var_12DC], 0\nadd edx, 1\nmov [rsp+1318h+var_48], edx\njmp short loc_12A7\nloc_1229:\nmov eax, [rsp+1318h+var_48]\nmovsxd rcx, eax\nlea rdx, [rcx+rcx]\nlea rsi, [rdx+rcx]\nshl rsi, 4\nmov dword ptr [rsp+rsi+1318h+var_1308], r13d\nmov [rsp+rsi+1318h+var_12DC], 0\nlea edx, [rax+1]\nmov [rsp+1318h+var_48], edx\nmov edx, 0\nloc_125B:\ncdqe\nlea rcx, [rax+rax]\nlea rsi, [rcx+rax]\nshl rsi, 4\nlea edi, [rdx+1]\nmov [rsp+rsi+1318h+var_12DC], edi\nmovsxd rdx, edx\nadd rcx, rax\nlea rax, [rdx+rcx*4]\nmov dword ptr [rsp+rax*4+1318h+var_1308+4], r12d\nloc_127F:\nadd rbx, 4\nadd rbp, 4\ncmp rbx, r15\njz short loc_12D1\nloc_128C:\nmov r13d, [rbx]\nmov r12d, [rbp+0]\nmov esi, r12d\nmov rdi, r14\ncall sub_1169\ncmp eax, 0FFFFFFFFh\njz loc_11FA\nloc_12A7:\nmov esi, r13d\nmov rdi, r14\ncall sub_1169\ncmp eax, 0FFFFFFFFh\njz loc_1229\nmovsxd rdx, eax\nlea rdx, [rdx+rdx*2]\nshl rdx, 4\nmov edx, [rsp+rdx+1318h+var_12DC]\ncmp edx, 9\njg short loc_127F\njmp short loc_125B\nloc_12D1:\nlea rsi, [rsp+1318h+var_1308]\nmov rax, [rsp+1318h+var_1308]\nmov rbx, [rsp+1318h+var_1310]\nmov [rbx], rax\nmov rax, [rsp+12CCh]\nmov [rbx+12BCh], rax\nmov rax, rbx\nlea rdi, [rbx+8]\nand rdi, 0FFFFFFFFFFFFFFF8h\nsub rax, rdi\nmov rcx, rax\nsub rsi, rax\nadd ecx, 12C4h\nshr ecx, 3\nmov ecx, ecx\nrep movsq\nmov rax, [rsp+1318h+var_40]\nsub rax, fs:28h\njnz short loc_133E\nmov rax, [rsp+1318h+var_1310]\nadd rsp, 12E8h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_133E:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1197(_QWORD *a1, unsigned int *a2, unsigned int *a3, int a4)\n{\n unsigned int *v4; // rbx\n unsigned int *v6; // r15\n int v7; // edx\n __int64 v8; // rsi\n int v9; // eax\n __int64 v10; // rsi\n int v11; // edx\n unsigned int v12; // r13d\n int v13; // r12d\n _QWORD v15[91]; // [rsp+10h] [rbp-1308h] BYREF\n __int64 v16; // [rsp+12CCh] [rbp-4Ch]\n unsigned __int64 v17; // [rsp+12D8h] [rbp-40h]\n\n v17 = __readfsqword(0x28u);\n HIDWORD(v16) = 0;\n if ( a4 > 0 )\n {\n v4 = a2;\n v6 = &a2[a4];\n do\n {\n v12 = *v4;\n v13 = *a3;\n if ( (unsigned int)sub_1169(v15, *a3) == -1 )\n {\n v7 = HIDWORD(v16);\n v8 = 6LL * SHIDWORD(v16);\n LODWORD(v15[v8]) = v13;\n HIDWORD(v15[v8 + 5]) = 0;\n HIDWORD(v16) = v7 + 1;\n }\n v9 = sub_1169(v15, v12);\n if ( v9 == -1 )\n {\n v9 = HIDWORD(v16);\n v10 = 6LL * SHIDWORD(v16);\n LODWORD(v15[v10]) = v12;\n HIDWORD(v15[v10 + 5]) = 0;\n HIDWORD(v16) = v9 + 1;\n v11 = 0;\n }\n else\n {\n v11 = HIDWORD(v15[6 * v9 + 5]);\n if ( v11 > 9 )\n goto LABEL_5;\n }\n HIDWORD(v15[6 * v9 + 5]) = v11 + 1;\n *((_DWORD *)&v15[6 * v9] + v11 + 1) = v13;\nLABEL_5:\n ++v4;\n ++a3;\n }\n while ( v4 != v6 );\n }\n *a1 = v15[0];\n *(_QWORD *)((char *)a1 + 4796) = v16;\n qmemcpy(\n (void *)((unsigned __int64)(a1 + 1) & 0xFFFFFFFFFFFFFFF8LL),\n (const void *)((char *)v15 - ((char *)a1 - ((unsigned __int64)(a1 + 1) & 0xFFFFFFFFFFFFFFF8LL))),\n 8LL * (((unsigned int)a1 - (((_DWORD)a1 + 8) & 0xFFFFFFF8) + 4804) >> 3));\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1197(uint64_t *a1, unsigned int *a2, unsigned int *a3, int a4) {\n unsigned int *v4;\n unsigned int *v6;\n int v7;\n long long v8;\n int v9;\n long long v10;\n int v11;\n unsigned int v12;\n int v13;\n uint64_t v15[91];\n long long v16;\n unsigned long long v17;\n v17 = __readfsqword(40u);\n HIDWORD(v16) = 0;\n if (a4 > 0) {\n v4 = a2;\n v6 = &a2[a4];\n do {\n v12 = *v4;\n v13 = *a3;\n if ((unsigned int)sub_1169(v15, *a3) == -1) {\n v7 = HIDWORD(v16);\n v8 = 6LL * SHIDWORD(v16);\n LODWORD(v15[v8]) = v13;\n HIDWORD(v15[v8 + 5]) = 0;\n HIDWORD(v16) = v7 + 1;\n }\n v9 = sub_1169(v15, v12);\n if (v9 == -1) {\n v9 = HIDWORD(v16);\n v10 = 6LL * SHIDWORD(v16);\n LODWORD(v15[v10]) = v12;\n HIDWORD(v15[v10 + 5]) = 0;\n HIDWORD(v16) = v9 + 1;\n v11 = 0;\n } else {\n v11 = HIDWORD(v15[6 * v9 + 5]);\n if (v11 > 9) goto LABEL_5;\n }\n HIDWORD(v15[6 * v9 + 5]) = v11 + 1;\n *((uint32_t *)&v15[6 * v9] + v11 + 1) = v13;\n LABEL_5:\n ++v4;\n ++a3;\n } while (v4 != v6);\n }\n *a1 = v15[0];\n *(uint64_t *)((char *)a1 + 4796) = v16;\n qmemcpy(\n (void *)((unsigned long long)(a1 + 1) & 18446744073709551608LL),\n (const void *)((char *)v15 - ((char *)a1 - ((unsigned long long)(a1 + 1) &\n 18446744073709551608LL))),\n 8LL *\n (((unsigned int)a1 - (((uint32_t)a1 + 8) & 4294967288) + 4804) >> 3));\n return a1;\n}", + "ida_pseudo_norm": "uint64_t *func0(uint64_t *a1, unsigned int *a2, unsigned int *a3, int a4) {\n unsigned int *v4;\n unsigned int *v6;\n int v7;\n long long v8;\n int key;\n long long v10;\n int v11;\n unsigned int v12;\n int v13;\n uint64_t v15[91];\n long long v16;\n unsigned long long v17;\n v17 = __readfsqword(40u);\n HIDWORD(v16) = 0;\n if (a4 > 0) {\n v4 = a2;\n v6 = &a2[a4];\n do {\n v12 = *v4;\n v13 = *a3;\n if ((unsigned int)find_key(v15, *a3) == -1) {\n v7 = HIDWORD(v16);\n v8 = 6LL * SHIDWORD(v16);\n LODWORD(v15[v8]) = v13;\n HIDWORD(v15[v8 + 5]) = 0;\n HIDWORD(v16) = v7 + 1;\n }\n key = find_key(v15, v12);\n if (key == -1) {\n key = HIDWORD(v16);\n v10 = 6LL * SHIDWORD(v16);\n LODWORD(v15[v10]) = v12;\n HIDWORD(v15[v10 + 5]) = 0;\n HIDWORD(v16) = key + 1;\n v11 = 0;\n } else {\n v11 = HIDWORD(v15[6 * key + 5]);\n if (v11 > 9) goto LABEL_5;\n }\n HIDWORD(v15[6 * key + 5]) = v11 + 1;\n *((uint32_t *)&v15[6 * key] + v11 + 1) = v13;\n LABEL_5:\n ++v4;\n ++a3;\n } while (v4 != v6);\n }\n *a1 = v15[0];\n *(uint64_t *)((char *)a1 + 4796) = v16;\n qmemcpy(\n (void *)((unsigned long long)(a1 + 1) & 18446744073709551608LL),\n (const void *)((char *)v15 - ((char *)a1 - ((unsigned long long)(a1 + 1) &\n 18446744073709551608LL))),\n 8LL *\n (((unsigned int)a1 - (((uint32_t)a1 + 8) & 4294967288) + 4804) >> 3));\n return a1;\n}" + }, + { + "index": 561, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n#define MAX_ENTRIES 100\n\n#define MAX_VALUES 10\n\n\n\ntypedef struct {\n\n int key;\n\n int values[MAX_VALUES];\n\n int count;\n\n} map_entry;\n\n\n\ntypedef struct {\n\n map_entry entries[MAX_ENTRIES];\n\n int size;\n\n} map;\n\n\n\nint find_key(map* m, int key) {\n\n for(int i = 0; i < m->size; i++) {\n\n if(m->entries[i].key == key)\n\n return i;\n\n }\n\n return -1;\n\n}\n\n\n\n", + "func": "map func0(int test_keys[], int test_vals[], int n) {\n map res;\n res.size = 0;\n for (int i = 0; i < n; i++) {\n int key = test_keys[i];\n int val = test_vals[i];\n if (find_key(&res, val) == -1) {\n res.entries[res.size].key = val;\n res.entries[res.size].count = 0;\n res.size++;\n }\n int idx = find_key(&res, key);\n if (idx == -1) {\n res.entries[res.size].key = key;\n res.entries[res.size].count = 0;\n idx = res.size;\n res.size++;\n }\n if (res.entries[idx].count < MAX_VALUES) {\n res.entries[idx].values[res.entries[idx].count++] = val;\n }\n }\n return res;\n}", + "test": "int main(){\n\n // First test case\n\n int test1_keys[] = {5, 7, 2, 3, 8};\n\n int test1_vals[] = {3, 5, 7, 8, 4};\n\n int n1 = 5;\n\n map result1 = func0(test1_keys, test1_vals, n1);\n\n map expected1;\n\n expected1.size = 6;\n\n expected1.entries[0].key = 3; expected1.entries[0].count = 1; expected1.entries[0].values[0] = 8;\n\n expected1.entries[1].key = 5; expected1.entries[1].count = 1; expected1.entries[1].values[0] = 3;\n\n expected1.entries[2].key = 7; expected1.entries[2].count = 1; expected1.entries[2].values[0] = 5;\n\n expected1.entries[3].key = 2; expected1.entries[3].count = 1; expected1.entries[3].values[0] = 7;\n\n expected1.entries[4].key = 8; expected1.entries[4].count = 1; expected1.entries[4].values[0] = 4;\n\n expected1.entries[5].key = 4; expected1.entries[5].count = 0;\n\n \n\n assert(result1.size == expected1.size);\n\n for(int i = 0; i < result1.size; i++){\n\n int found = 0;\n\n for(int j = 0; j < expected1.size; j++){\n\n if(result1.entries[i].key == expected1.entries[j].key){\n\n assert(result1.entries[i].count == expected1.entries[j].count);\n\n for(int k = 0; k < result1.entries[i].count; k++){\n\n assert(result1.entries[i].values[k] == expected1.entries[j].values[k]);\n\n }\n\n found = 1;\n\n break;\n\n }\n\n }\n\n assert(found);\n\n }\n\n\n\n // Second test case\n\n int test2_keys[] = {6, 9, 3, 4, 9};\n\n int test2_vals[] = {4, 4, 8, 9, 5};\n\n int n2 = 5;\n\n map result2 = func0(test2_keys, test2_vals, n2);\n\n map expected2;\n\n expected2.size = 6;\n\n expected2.entries[0].key = 4; expected2.entries[0].count = 1; expected2.entries[0].values[0] = 9;\n\n expected2.entries[1].key = 6; expected2.entries[1].count = 1; expected2.entries[1].values[0] = 4;\n\n expected2.entries[2].key = 9; expected2.entries[2].count = 2; expected2.entries[2].values[0] = 4; expected2.entries[2].values[1] = 5;\n\n expected2.entries[3].key = 8; expected2.entries[3].count = 0;\n\n expected2.entries[4].key = 3; expected2.entries[4].count = 1; expected2.entries[4].values[0] = 8;\n\n expected2.entries[5].key = 5; expected2.entries[5].count = 0;\n\n \n\n assert(result2.size == expected2.size);\n\n for(int i = 0; i < result2.size; i++){\n\n int found = 0;\n\n for(int j = 0; j < expected2.size; j++){\n\n if(result2.entries[i].key == expected2.entries[j].key){\n\n assert(result2.entries[i].count == expected2.entries[j].count);\n\n for(int k = 0; k < result2.entries[i].count; k++){\n\n assert(result2.entries[i].values[k] == expected2.entries[j].values[k]);\n\n }\n\n found = 1;\n\n break;\n\n }\n\n }\n\n assert(found);\n\n }\n\n\n\n // Third test case\n\n int test3_keys[] = {6, 6, 4, 4, 3};\n\n int test3_vals[] = {2, 8, 9, 9, 7};\n\n int n3 = 5;\n\n map result3 = func0(test3_keys, test3_vals, n3);\n\n map expected3;\n\n expected3.size = 7;\n\n expected3.entries[0].key = 2; expected3.entries[0].count = 0;\n\n expected3.entries[1].key = 6; expected3.entries[1].count = 2; expected3.entries[1].values[0] = 2; expected3.entries[1].values[1] = 8;\n\n expected3.entries[2].key = 8; expected3.entries[2].count = 0;\n\n expected3.entries[3].key = 9; expected3.entries[3].count = 0;\n\n expected3.entries[4].key = 4; expected3.entries[4].count = 2; expected3.entries[4].values[0] = 9; expected3.entries[4].values[1] = 9;\n\n expected3.entries[5].key = 7; expected3.entries[5].count = 0;\n\n expected3.entries[6].key = 3; expected3.entries[6].count = 1; expected3.entries[6].values[0] = 7;\n\n \n\n assert(result3.size == expected3.size);\n\n for(int i = 0; i < result3.size; i++){\n\n int found = 0;\n\n for(int j = 0; j < expected3.size; j++){\n\n if(result3.entries[i].key == expected3.entries[j].key){\n\n assert(result3.entries[i].count == expected3.entries[j].count);\n\n for(int k = 0; k < result3.entries[i].count; k++){\n\n assert(result3.entries[i].values[k] == expected3.entries[j].values[k]);\n\n }\n\n found = 1;\n\n break;\n\n }\n\n }\n\n assert(found);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x1000,%rsp\norq $0x0,(%rsp)\nsub $0x2d8,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x12c8(%rsp)\nxor %eax,%eax\nmov %rdi,%r10\ntest %ecx,%ecx\njle 19e4 \nmov %rsi,%r11\nxor %r9d,%r9d\nxor %edi,%edi\nmov %rsp,%rsi\nmov (%r11,%r9,4),%r12d\nmov (%rdx,%r9,4),%r8d\nlea -0x1(%rcx),%ebx\nlea 0x30(%rsp),%rbp\ntest %edi,%edi\nje 1920 \nnopw 0x0(%rax,%rax,1)\nlea -0x1(%rdi),%ecx\nmov %rsi,%rax\nlea (%rcx,%rcx,2),%rcx\nshl $0x4,%rcx\nadd %rbp,%rcx\njmp 18d1 \nnopl 0x0(%rax,%rax,1)\nadd $0x30,%rax\ncmp %rcx,%rax\nje 1920 \ncmp (%rax),%r8d\njne 18c8 \nmov %rsi,%rcx\nxor %eax,%eax\njmp 18eb \nnopl (%rax)\nadd $0x1,%eax\nadd $0x30,%rcx\ncmp %edi,%eax\njge 1940 \ncmp (%rcx),%r12d\njne 18e0 \ncltq\nlea (%rax,%rax,2),%rcx\nshl $0x4,%rcx\nmovslq 0x2c(%rsp,%rcx,1),%rcx\ncmp $0x9,%ecx\njle 195f \nlea 0x1(%r9),%rax\ncmp %rbx,%r9\nje 1985 \nmov %rax,%r9\nmov (%r11,%r9,4),%r12d\nmov (%rdx,%r9,4),%r8d\ntest %edi,%edi\njne 18b0 \nnopl 0x0(%rax)\nmovslq %edi,%rax\nadd $0x1,%edi\nlea (%rax,%rax,2),%rax\nshl $0x4,%rax\nmov %r8d,(%rsp,%rax,1)\nmovl $0x0,0x2c(%rsp,%rax,1)\njmp 18d6 \nnopl 0x0(%rax)\nmovslq %edi,%rax\nxor %ecx,%ecx\nlea (%rax,%rax,2),%rax\nshl $0x4,%rax\nmov %r12d,(%rsp,%rax,1)\nmovl $0x0,0x2c(%rsp,%rax,1)\nmovslq %edi,%rax\nadd $0x1,%edi\nlea (%rax,%rax,2),%rax\nlea 0x1(%rcx),%r13d\nmov %rax,%r12\nlea (%rcx,%rax,4),%rax\nshl $0x4,%r12\nmov %r8d,0x4(%rsp,%rax,4)\nlea 0x1(%r9),%rax\nmov %r13d,0x2c(%rsp,%r12,1)\ncmp %rbx,%r9\njne 190d \nmov (%rsp),%rax\nmov %edi,0x12c0(%rsp)\nlea 0x8(%r10),%rdi\nand $0xfffffffffffffff8,%rdi\nmov %rax,(%r10)\nmov 0x12bc(%rsp),%rax\nmov %rax,0x12bc(%r10)\nmov %r10,%rax\nsub %rdi,%rax\nsub %rax,%rsi\nadd $0x12c4,%eax\nshr $0x3,%eax\nmov %eax,%ecx\nrep movsq %ds:(%rsi),%es:(%rdi)\nmov 0x12c8(%rsp),%rax\nxor %fs:0x28,%rax\njne 19eb \nadd $0x12d8,%rsp\nmov %r10,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nxor %edi,%edi\nmov %rsp,%rsi\njmp 1985 \ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 1000h\nor [rsp+1018h+var_1018], 0\nsub rsp, 2D0h\nmov rax, fs:28h\nmov [rsp+12E8h+var_20], rax\nxor eax, eax\nmov r10, rdi\ntest ecx, ecx\njle loc_1979\nmovsxd rcx, ecx\nmov r11, rsi\nmov rbx, rdx\nxor r9d, r9d\nlea rbp, ds:0[rcx*4]\nmov rsi, rsp\nxor ecx, ecx\nnop word ptr [rax+rax+00h]\nloc_1808:\nmov r8d, [r11+r9]\nmov edi, [rbx+r9]\ntest ecx, ecx\njle loc_18A0\nloc_1818:\nmov rax, rsi\nxor edx, edx\njmp short loc_182B\nloc_1820:\nadd edx, 1\nadd rax, 30h ; '0'\ncmp edx, ecx\njz short loc_1880\nloc_182B:\ncmp [rax], edi\njnz short loc_1820\nloc_182F:\nmov rdx, rsi\nxor eax, eax\njmp short loc_184B\nloc_1840:\nadd eax, 1\nadd rdx, 30h ; '0'\ncmp eax, ecx\njz short loc_18C8\nloc_184B:\ncmp [rdx], r8d\njnz short loc_1840\ncdqe\nlea rdx, [rax+rax*2]\nshl rdx, 4\nmovsxd rdx, [rsp+rdx+12E8h+var_12BC]\ncmp edx, 9\njle loc_1970\nadd r9, 4\ncmp r9, rbp\njz loc_1912\nmov r8d, [r11+r9]\nmov edi, [rbx+r9]\njmp short loc_1818\nloc_1880:\nmovsxd rax, ecx\nadd ecx, 1\nlea rax, [rax+rax*2]\nshl rax, 4\nmov dword ptr [rsp+rax+12E8h+var_12E8], edi\nmov [rsp+rax+12E8h+var_12BC], 0\njmp short loc_182F\nloc_18A0:\nmovsxd rax, ecx\nadd ecx, 1\nlea rax, [rax+rax*2]\nshl rax, 4\nmov dword ptr [rsp+rax+12E8h+var_12E8], edi\nmov [rsp+rax+12E8h+var_12BC], 0\ncmp ecx, 1\njz loc_182F\nnop word ptr [rax+rax+00h]\nloc_18C8:\nmovsxd rax, ecx\nmov r12d, 1\nxor edx, edx\nlea rax, [rax+rax*2]\nshl rax, 4\nmov dword ptr [rsp+rax+12E8h+var_12E8], r8d\nmov [rsp+rax+12E8h+var_12BC], 0\nmovsxd rax, ecx\nadd ecx, 1\nloc_18ED:\nlea rax, [rax+rax*2]\nadd r9, 4\nmov r8, rax\nlea rax, [rdx+rax*4]\nshl r8, 4\nmov dword ptr [rsp+rax*4+12E8h+var_12E8+4], edi\nmov [rsp+r8+12E8h+var_12BC], r12d\ncmp r9, rbp\njnz loc_1808\nloc_1912:\nmov rax, [rsp+12E8h+var_12E8]\nmov [rsp+12E8h+var_28], ecx\nlea rdi, [r10+8]\nand rdi, 0FFFFFFFFFFFFFFF8h\nmov [r10], rax\nmov rax, [rsp+12BCh]\nmov [r10+12BCh], rax\nmov rax, r10\nsub rax, rdi\nsub rsi, rax\nadd eax, 12C4h\nshr eax, 3\nmov ecx, eax\nrep movsq\nmov rax, [rsp+12E8h+var_20]\nsub rax, fs:28h\njnz short loc_1980\nadd rsp, 12D0h\nmov rax, r10\npop rbx\npop rbp\npop r12\nretn\nloc_1970:\nlea r12d, [rdx+1]\njmp loc_18ED\nloc_1979:\nxor ecx, ecx\nmov rsi, rsp\njmp short loc_1912\nloc_1980:\ncall ___stack_chk_fail", + "ida_pseudo": "_QWORD *__fastcall func0(_QWORD *a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 v6; // r9\n __int64 v7; // rbp\n int v8; // ecx\n int v9; // r8d\n int v10; // edi\n _DWORD *v11; // rax\n int v12; // edx\n _DWORD *v13; // rdx\n __int64 v14; // rax\n __int64 v15; // rdx\n __int64 v16; // rax\n __int64 v17; // rax\n int v18; // r12d\n __int64 v19; // rax\n _QWORD v21[90]; // [rsp+0h] [rbp-12E8h] BYREF\n __int64 v22; // [rsp+12BCh] [rbp-2Ch]\n unsigned __int64 v23; // [rsp+12C8h] [rbp-20h]\n\n v23 = __readfsqword(0x28u);\n if ( a4 > 0 )\n {\n v6 = 0LL;\n v7 = 4LL * a4;\n v8 = 0;\n while ( 1 )\n {\n v9 = *(_DWORD *)(a2 + v6);\n v10 = *(_DWORD *)(a3 + v6);\n if ( v8 > 0 )\n break;\n v17 = v8++;\n v17 *= 48LL;\n *(_DWORD *)((char *)v21 + v17) = v10;\n *(_DWORD *)((char *)&v21[5] + v17 + 4) = 0;\n if ( v8 == 1 )\n goto LABEL_7;\nLABEL_15:\n v18 = 1;\n v15 = 0LL;\n v19 = 6LL * v8;\n LODWORD(v21[v19]) = v9;\n HIDWORD(v21[v19 + 5]) = 0;\n v14 = v8++;\nLABEL_16:\n v6 += 4LL;\n *((_DWORD *)&v21[6 * v14] + v15 + 1) = v10;\n HIDWORD(v21[6 * v14 + 5]) = v18;\n if ( v6 == v7 )\n goto LABEL_17;\n }\n while ( 1 )\n {\n v11 = v21;\n v12 = 0;\n while ( *v11 != v10 )\n {\n ++v12;\n v11 += 12;\n if ( v12 == v8 )\n {\n v16 = v8++;\n v16 *= 48LL;\n *(_DWORD *)((char *)v21 + v16) = v10;\n *(_DWORD *)((char *)&v21[5] + v16 + 4) = 0;\n break;\n }\n }\nLABEL_7:\n v13 = v21;\n LODWORD(v14) = 0;\n while ( *v13 != v9 )\n {\n LODWORD(v14) = v14 + 1;\n v13 += 12;\n if ( (_DWORD)v14 == v8 )\n goto LABEL_15;\n }\n v14 = (int)v14;\n v15 = SHIDWORD(v21[6 * (int)v14 + 5]);\n if ( (int)v15 <= 9 )\n {\n v18 = v15 + 1;\n goto LABEL_16;\n }\n v6 += 4LL;\n if ( v6 == v7 )\n goto LABEL_17;\n v9 = *(_DWORD *)(a2 + v6);\n v10 = *(_DWORD *)(a3 + v6);\n }\n }\n v8 = 0;\nLABEL_17:\n HIDWORD(v22) = v8;\n *a1 = v21[0];\n *(_QWORD *)((char *)a1 + 4796) = v22;\n qmemcpy(\n (void *)((unsigned __int64)(a1 + 1) & 0xFFFFFFFFFFFFFFF8LL),\n (const void *)((char *)v21 - ((char *)a1 - ((unsigned __int64)(a1 + 1) & 0xFFFFFFFFFFFFFFF8LL))),\n 8LL * (((unsigned int)a1 - (((_DWORD)a1 + 8) & 0xFFFFFFF8) + 4804) >> 3));\n return a1;\n}", + "ida_strip_asm": "sub_17B0:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 1000h\nor [rsp+1018h+var_1018], 0\nsub rsp, 2D0h\nmov rax, fs:28h\nmov [rsp+12E8h+var_20], rax\nxor eax, eax\nmov r10, rdi\ntest ecx, ecx\njle loc_1979\nmovsxd rcx, ecx\nmov r11, rsi\nmov rbx, rdx\nxor r9d, r9d\nlea rbp, ds:0[rcx*4]\nmov rsi, rsp\nxor ecx, ecx\nnop word ptr [rax+rax+00h]\nloc_1808:\nmov r8d, [r11+r9]\nmov edi, [rbx+r9]\ntest ecx, ecx\njle loc_18A0\nloc_1818:\nmov rax, rsi\nxor edx, edx\njmp short loc_182B\nloc_1820:\nadd edx, 1\nadd rax, 30h ; '0'\ncmp edx, ecx\njz short loc_1880\nloc_182B:\ncmp [rax], edi\njnz short loc_1820\nloc_182F:\nmov rdx, rsi\nxor eax, eax\njmp short loc_184B\nloc_1840:\nadd eax, 1\nadd rdx, 30h ; '0'\ncmp eax, ecx\njz short loc_18C8\nloc_184B:\ncmp [rdx], r8d\njnz short loc_1840\ncdqe\nlea rdx, [rax+rax*2]\nshl rdx, 4\nmovsxd rdx, [rsp+rdx+12E8h+var_12BC]\ncmp edx, 9\njle loc_1970\nadd r9, 4\ncmp r9, rbp\njz loc_1912\nmov r8d, [r11+r9]\nmov edi, [rbx+r9]\njmp short loc_1818\nloc_1880:\nmovsxd rax, ecx\nadd ecx, 1\nlea rax, [rax+rax*2]\nshl rax, 4\nmov dword ptr [rsp+rax+12E8h+var_12E8], edi\nmov [rsp+rax+12E8h+var_12BC], 0\njmp short loc_182F\nloc_18A0:\nmovsxd rax, ecx\nadd ecx, 1\nlea rax, [rax+rax*2]\nshl rax, 4\nmov dword ptr [rsp+rax+12E8h+var_12E8], edi\nmov [rsp+rax+12E8h+var_12BC], 0\ncmp ecx, 1\njz loc_182F\nnop word ptr [rax+rax+00h]\nloc_18C8:\nmovsxd rax, ecx\nmov r12d, 1\nxor edx, edx\nlea rax, [rax+rax*2]\nshl rax, 4\nmov dword ptr [rsp+rax+12E8h+var_12E8], r8d\nmov [rsp+rax+12E8h+var_12BC], 0\nmovsxd rax, ecx\nadd ecx, 1\nloc_18ED:\nlea rax, [rax+rax*2]\nadd r9, 4\nmov r8, rax\nlea rax, [rdx+rax*4]\nshl r8, 4\nmov dword ptr [rsp+rax*4+12E8h+var_12E8+4], edi\nmov [rsp+r8+12E8h+var_12BC], r12d\ncmp r9, rbp\njnz loc_1808\nloc_1912:\nmov rax, [rsp+12E8h+var_12E8]\nmov [rsp+12E8h+var_28], ecx\nlea rdi, [r10+8]\nand rdi, 0FFFFFFFFFFFFFFF8h\nmov [r10], rax\nmov rax, [rsp+12BCh]\nmov [r10+12BCh], rax\nmov rax, r10\nsub rax, rdi\nsub rsi, rax\nadd eax, 12C4h\nshr eax, 3\nmov ecx, eax\nrep movsq\nmov rax, [rsp+12E8h+var_20]\nsub rax, fs:28h\njnz short loc_1980\nadd rsp, 12D0h\nmov rax, r10\npop rbx\npop rbp\npop r12\nretn\nloc_1970:\nlea r12d, [rdx+1]\njmp loc_18ED\nloc_1979:\nxor ecx, ecx\nmov rsi, rsp\njmp short loc_1912\nloc_1980:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_QWORD *__fastcall sub_17B0(_QWORD *a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 v6; // r9\n __int64 v7; // rbp\n int v8; // ecx\n int v9; // r8d\n int v10; // edi\n _DWORD *v11; // rax\n int v12; // edx\n _DWORD *v13; // rdx\n __int64 v14; // rax\n __int64 v15; // rdx\n __int64 v16; // rax\n __int64 v17; // rax\n int v18; // r12d\n __int64 v19; // rax\n _QWORD v21[90]; // [rsp+0h] [rbp-12E8h] BYREF\n __int64 v22; // [rsp+12BCh] [rbp-2Ch]\n unsigned __int64 v23; // [rsp+12C8h] [rbp-20h]\n\n v23 = __readfsqword(0x28u);\n if ( a4 > 0 )\n {\n v6 = 0LL;\n v7 = 4LL * a4;\n v8 = 0;\n while ( 1 )\n {\n v9 = *(_DWORD *)(a2 + v6);\n v10 = *(_DWORD *)(a3 + v6);\n if ( v8 > 0 )\n break;\n v17 = v8++;\n v17 *= 48LL;\n *(_DWORD *)((char *)v21 + v17) = v10;\n *(_DWORD *)((char *)&v21[5] + v17 + 4) = 0;\n if ( v8 == 1 )\n goto LABEL_7;\nLABEL_15:\n v18 = 1;\n v15 = 0LL;\n v19 = 6LL * v8;\n LODWORD(v21[v19]) = v9;\n HIDWORD(v21[v19 + 5]) = 0;\n v14 = v8++;\nLABEL_16:\n v6 += 4LL;\n *((_DWORD *)&v21[6 * v14] + v15 + 1) = v10;\n HIDWORD(v21[6 * v14 + 5]) = v18;\n if ( v6 == v7 )\n goto LABEL_17;\n }\n while ( 1 )\n {\n v11 = v21;\n v12 = 0;\n while ( *v11 != v10 )\n {\n ++v12;\n v11 += 12;\n if ( v12 == v8 )\n {\n v16 = v8++;\n v16 *= 48LL;\n *(_DWORD *)((char *)v21 + v16) = v10;\n *(_DWORD *)((char *)&v21[5] + v16 + 4) = 0;\n break;\n }\n }\nLABEL_7:\n v13 = v21;\n LODWORD(v14) = 0;\n while ( *v13 != v9 )\n {\n LODWORD(v14) = v14 + 1;\n v13 += 12;\n if ( (_DWORD)v14 == v8 )\n goto LABEL_15;\n }\n v14 = (int)v14;\n v15 = SHIDWORD(v21[6 * (int)v14 + 5]);\n if ( (int)v15 <= 9 )\n {\n v18 = v15 + 1;\n goto LABEL_16;\n }\n v6 += 4LL;\n if ( v6 == v7 )\n goto LABEL_17;\n v9 = *(_DWORD *)(a2 + v6);\n v10 = *(_DWORD *)(a3 + v6);\n }\n }\n v8 = 0;\nLABEL_17:\n HIDWORD(v22) = v8;\n *a1 = v21[0];\n *(_QWORD *)((char *)a1 + 4796) = v22;\n qmemcpy(\n (void *)((unsigned __int64)(a1 + 1) & 0xFFFFFFFFFFFFFFF8LL),\n (const void *)((char *)v21 - ((char *)a1 - ((unsigned __int64)(a1 + 1) & 0xFFFFFFFFFFFFFFF8LL))),\n 8LL * (((unsigned int)a1 - (((_DWORD)a1 + 8) & 0xFFFFFFF8) + 4804) >> 3));\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_17B0(uint64_t *a1, long long a2, long long a3, int a4) {\n long long v6;\n long long v7;\n int v8;\n int v9;\n int v10;\n uint32_t *v11;\n int v12;\n uint32_t *v13;\n long long v14;\n long long v15;\n long long v16;\n long long v17;\n int v18;\n long long v19;\n uint64_t v21[90];\n long long v22;\n unsigned long long v23;\n v23 = __readfsqword(40u);\n if (a4 > 0) {\n v6 = 0LL;\n v7 = 4LL * a4;\n v8 = 0;\n while (1) {\n v9 = *(uint32_t *)(a2 + v6);\n v10 = *(uint32_t *)(a3 + v6);\n if (v8 > 0) break;\n v17 = v8++;\n v17 *= 48LL;\n *(uint32_t *)((char *)v21 + v17) = v10;\n *(uint32_t *)((char *)&v21[5] + v17 + 4) = 0;\n if (v8 == 1) goto LABEL_7;\n LABEL_15:\n v18 = 1;\n v15 = 0LL;\n v19 = 6LL * v8;\n LODWORD(v21[v19]) = v9;\n HIDWORD(v21[v19 + 5]) = 0;\n v14 = v8++;\n LABEL_16:\n v6 += 4LL;\n *((uint32_t *)&v21[6 * v14] + v15 + 1) = v10;\n HIDWORD(v21[6 * v14 + 5]) = v18;\n if (v6 == v7) goto LABEL_17;\n }\n while (1) {\n v11 = v21;\n v12 = 0;\n while (*v11 != v10) {\n ++v12;\n v11 += 12;\n if (v12 == v8) {\n v16 = v8++;\n v16 *= 48LL;\n *(uint32_t *)((char *)v21 + v16) = v10;\n *(uint32_t *)((char *)&v21[5] + v16 + 4) = 0;\n break;\n }\n }\n LABEL_7:\n v13 = v21;\n LODWORD(v14) = 0;\n while (*v13 != v9) {\n LODWORD(v14) = v14 + 1;\n v13 += 12;\n if ((uint32_t)v14 == v8) goto LABEL_15;\n }\n v14 = (int)v14;\n v15 = SHIDWORD(v21[6 * (int)v14 + 5]);\n if ((int)v15 <= 9) {\n v18 = v15 + 1;\n goto LABEL_16;\n }\n v6 += 4LL;\n if (v6 == v7) goto LABEL_17;\n v9 = *(uint32_t *)(a2 + v6);\n v10 = *(uint32_t *)(a3 + v6);\n }\n }\n v8 = 0;\nLABEL_17:\n HIDWORD(v22) = v8;\n *a1 = v21[0];\n *(uint64_t *)((char *)a1 + 4796) = v22;\n qmemcpy(\n (void *)((unsigned long long)(a1 + 1) & 18446744073709551608LL),\n (const void *)((char *)v21 - ((char *)a1 - ((unsigned long long)(a1 + 1) &\n 18446744073709551608LL))),\n 8LL *\n (((unsigned int)a1 - (((uint32_t)a1 + 8) & 4294967288) + 4804) >> 3));\n return a1;\n}", + "ida_pseudo_norm": "uint64_t *func0(uint64_t *a1, long long a2, long long a3, int a4) {\n long long v6;\n long long v7;\n int v8;\n int v9;\n int v10;\n uint32_t *v11;\n int v12;\n uint32_t *v13;\n long long v14;\n long long v15;\n long long v16;\n long long v17;\n int v18;\n long long v19;\n uint64_t v21[90];\n long long v22;\n unsigned long long v23;\n v23 = __readfsqword(40u);\n if (a4 > 0) {\n v6 = 0LL;\n v7 = 4LL * a4;\n v8 = 0;\n while (1) {\n v9 = *(uint32_t *)(a2 + v6);\n v10 = *(uint32_t *)(a3 + v6);\n if (v8 > 0) break;\n v17 = v8++;\n v17 *= 48LL;\n *(uint32_t *)((char *)v21 + v17) = v10;\n *(uint32_t *)((char *)&v21[5] + v17 + 4) = 0;\n if (v8 == 1) goto LABEL_7;\n LABEL_15:\n v18 = 1;\n v15 = 0LL;\n v19 = 6LL * v8;\n LODWORD(v21[v19]) = v9;\n HIDWORD(v21[v19 + 5]) = 0;\n v14 = v8++;\n LABEL_16:\n v6 += 4LL;\n *((uint32_t *)&v21[6 * v14] + v15 + 1) = v10;\n HIDWORD(v21[6 * v14 + 5]) = v18;\n if (v6 == v7) goto LABEL_17;\n }\n while (1) {\n v11 = v21;\n v12 = 0;\n while (*v11 != v10) {\n ++v12;\n v11 += 12;\n if (v12 == v8) {\n v16 = v8++;\n v16 *= 48LL;\n *(uint32_t *)((char *)v21 + v16) = v10;\n *(uint32_t *)((char *)&v21[5] + v16 + 4) = 0;\n break;\n }\n }\n LABEL_7:\n v13 = v21;\n LODWORD(v14) = 0;\n while (*v13 != v9) {\n LODWORD(v14) = v14 + 1;\n v13 += 12;\n if ((uint32_t)v14 == v8) goto LABEL_15;\n }\n v14 = (int)v14;\n v15 = SHIDWORD(v21[6 * (int)v14 + 5]);\n if ((int)v15 <= 9) {\n v18 = v15 + 1;\n goto LABEL_16;\n }\n v6 += 4LL;\n if (v6 == v7) goto LABEL_17;\n v9 = *(uint32_t *)(a2 + v6);\n v10 = *(uint32_t *)(a3 + v6);\n }\n }\n v8 = 0;\nLABEL_17:\n HIDWORD(v22) = v8;\n *a1 = v21[0];\n *(uint64_t *)((char *)a1 + 4796) = v22;\n qmemcpy(\n (void *)((unsigned long long)(a1 + 1) & 18446744073709551608LL),\n (const void *)((char *)v21 - ((char *)a1 - ((unsigned long long)(a1 + 1) &\n 18446744073709551608LL))),\n 8LL *\n (((unsigned int)a1 - (((uint32_t)a1 + 8) & 4294967288) + 4804) >> 3));\n return a1;\n}" + }, + { + "index": 561, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n#define MAX_ENTRIES 100\n\n#define MAX_VALUES 10\n\n\n\ntypedef struct {\n\n int key;\n\n int values[MAX_VALUES];\n\n int count;\n\n} map_entry;\n\n\n\ntypedef struct {\n\n map_entry entries[MAX_ENTRIES];\n\n int size;\n\n} map;\n\n\n\nint find_key(map* m, int key) {\n\n for(int i = 0; i < m->size; i++) {\n\n if(m->entries[i].key == key)\n\n return i;\n\n }\n\n return -1;\n\n}\n\n\n\n", + "func": "map func0(int test_keys[], int test_vals[], int n) {\n map res;\n res.size = 0;\n for (int i = 0; i < n; i++) {\n int key = test_keys[i];\n int val = test_vals[i];\n if (find_key(&res, val) == -1) {\n res.entries[res.size].key = val;\n res.entries[res.size].count = 0;\n res.size++;\n }\n int idx = find_key(&res, key);\n if (idx == -1) {\n res.entries[res.size].key = key;\n res.entries[res.size].count = 0;\n idx = res.size;\n res.size++;\n }\n if (res.entries[idx].count < MAX_VALUES) {\n res.entries[idx].values[res.entries[idx].count++] = val;\n }\n }\n return res;\n}", + "test": "int main(){\n\n // First test case\n\n int test1_keys[] = {5, 7, 2, 3, 8};\n\n int test1_vals[] = {3, 5, 7, 8, 4};\n\n int n1 = 5;\n\n map result1 = func0(test1_keys, test1_vals, n1);\n\n map expected1;\n\n expected1.size = 6;\n\n expected1.entries[0].key = 3; expected1.entries[0].count = 1; expected1.entries[0].values[0] = 8;\n\n expected1.entries[1].key = 5; expected1.entries[1].count = 1; expected1.entries[1].values[0] = 3;\n\n expected1.entries[2].key = 7; expected1.entries[2].count = 1; expected1.entries[2].values[0] = 5;\n\n expected1.entries[3].key = 2; expected1.entries[3].count = 1; expected1.entries[3].values[0] = 7;\n\n expected1.entries[4].key = 8; expected1.entries[4].count = 1; expected1.entries[4].values[0] = 4;\n\n expected1.entries[5].key = 4; expected1.entries[5].count = 0;\n\n \n\n assert(result1.size == expected1.size);\n\n for(int i = 0; i < result1.size; i++){\n\n int found = 0;\n\n for(int j = 0; j < expected1.size; j++){\n\n if(result1.entries[i].key == expected1.entries[j].key){\n\n assert(result1.entries[i].count == expected1.entries[j].count);\n\n for(int k = 0; k < result1.entries[i].count; k++){\n\n assert(result1.entries[i].values[k] == expected1.entries[j].values[k]);\n\n }\n\n found = 1;\n\n break;\n\n }\n\n }\n\n assert(found);\n\n }\n\n\n\n // Second test case\n\n int test2_keys[] = {6, 9, 3, 4, 9};\n\n int test2_vals[] = {4, 4, 8, 9, 5};\n\n int n2 = 5;\n\n map result2 = func0(test2_keys, test2_vals, n2);\n\n map expected2;\n\n expected2.size = 6;\n\n expected2.entries[0].key = 4; expected2.entries[0].count = 1; expected2.entries[0].values[0] = 9;\n\n expected2.entries[1].key = 6; expected2.entries[1].count = 1; expected2.entries[1].values[0] = 4;\n\n expected2.entries[2].key = 9; expected2.entries[2].count = 2; expected2.entries[2].values[0] = 4; expected2.entries[2].values[1] = 5;\n\n expected2.entries[3].key = 8; expected2.entries[3].count = 0;\n\n expected2.entries[4].key = 3; expected2.entries[4].count = 1; expected2.entries[4].values[0] = 8;\n\n expected2.entries[5].key = 5; expected2.entries[5].count = 0;\n\n \n\n assert(result2.size == expected2.size);\n\n for(int i = 0; i < result2.size; i++){\n\n int found = 0;\n\n for(int j = 0; j < expected2.size; j++){\n\n if(result2.entries[i].key == expected2.entries[j].key){\n\n assert(result2.entries[i].count == expected2.entries[j].count);\n\n for(int k = 0; k < result2.entries[i].count; k++){\n\n assert(result2.entries[i].values[k] == expected2.entries[j].values[k]);\n\n }\n\n found = 1;\n\n break;\n\n }\n\n }\n\n assert(found);\n\n }\n\n\n\n // Third test case\n\n int test3_keys[] = {6, 6, 4, 4, 3};\n\n int test3_vals[] = {2, 8, 9, 9, 7};\n\n int n3 = 5;\n\n map result3 = func0(test3_keys, test3_vals, n3);\n\n map expected3;\n\n expected3.size = 7;\n\n expected3.entries[0].key = 2; expected3.entries[0].count = 0;\n\n expected3.entries[1].key = 6; expected3.entries[1].count = 2; expected3.entries[1].values[0] = 2; expected3.entries[1].values[1] = 8;\n\n expected3.entries[2].key = 8; expected3.entries[2].count = 0;\n\n expected3.entries[3].key = 9; expected3.entries[3].count = 0;\n\n expected3.entries[4].key = 4; expected3.entries[4].count = 2; expected3.entries[4].values[0] = 9; expected3.entries[4].values[1] = 9;\n\n expected3.entries[5].key = 7; expected3.entries[5].count = 0;\n\n expected3.entries[6].key = 3; expected3.entries[6].count = 1; expected3.entries[6].values[0] = 7;\n\n \n\n assert(result3.size == expected3.size);\n\n for(int i = 0; i < result3.size; i++){\n\n int found = 0;\n\n for(int j = 0; j < expected3.size; j++){\n\n if(result3.entries[i].key == expected3.entries[j].key){\n\n assert(result3.entries[i].count == expected3.entries[j].count);\n\n for(int k = 0; k < result3.entries[i].count; k++){\n\n assert(result3.entries[i].values[k] == expected3.entries[j].values[k]);\n\n }\n\n found = 1;\n\n break;\n\n }\n\n }\n\n assert(found);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x1000,%rsp\norq $0x0,(%rsp)\nsub $0x2d8,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x12c8(%rsp)\nxor %eax,%eax\nmov %rdi,%r10\ntest %ecx,%ecx\njle 1c94 \nmov %rsi,%r11\nxor %r9d,%r9d\nxor %edi,%edi\nmov %rsp,%rsi\nmov (%r11,%r9,4),%r12d\nmov (%rdx,%r9,4),%r8d\nlea -0x1(%rcx),%ebx\nlea 0x30(%rsp),%rbp\ntest %edi,%edi\nje 1bd0 \nnopw 0x0(%rax,%rax,1)\nlea -0x1(%rdi),%ecx\nmov %rsi,%rax\nlea (%rcx,%rcx,2),%rcx\nshl $0x4,%rcx\nadd %rbp,%rcx\njmp 1b81 \nnopl 0x0(%rax,%rax,1)\nadd $0x30,%rax\ncmp %rcx,%rax\nje 1bd0 \ncmp (%rax),%r8d\njne 1b78 \nmov %rsi,%rcx\nxor %eax,%eax\njmp 1b9b \nnopl (%rax)\nadd $0x1,%eax\nadd $0x30,%rcx\ncmp %edi,%eax\njge 1bf0 \ncmp (%rcx),%r12d\njne 1b90 \ncltq\nlea (%rax,%rax,2),%rcx\nshl $0x4,%rcx\nmovslq 0x2c(%rsp,%rcx,1),%rcx\ncmp $0x9,%ecx\njle 1c0f \nlea 0x1(%r9),%rax\ncmp %rbx,%r9\nje 1c35 \nmov %rax,%r9\nmov (%r11,%r9,4),%r12d\nmov (%rdx,%r9,4),%r8d\ntest %edi,%edi\njne 1b60 \nnopl 0x0(%rax)\nmovslq %edi,%rax\nadd $0x1,%edi\nlea (%rax,%rax,2),%rax\nshl $0x4,%rax\nmov %r8d,(%rsp,%rax,1)\nmovl $0x0,0x2c(%rsp,%rax,1)\njmp 1b86 \nnopl 0x0(%rax)\nmovslq %edi,%rax\nxor %ecx,%ecx\nlea (%rax,%rax,2),%rax\nshl $0x4,%rax\nmov %r12d,(%rsp,%rax,1)\nmovl $0x0,0x2c(%rsp,%rax,1)\nmovslq %edi,%rax\nadd $0x1,%edi\nlea (%rax,%rax,2),%rax\nlea 0x1(%rcx),%r13d\nmov %rax,%r12\nlea (%rcx,%rax,4),%rax\nshl $0x4,%r12\nmov %r8d,0x4(%rsp,%rax,4)\nlea 0x1(%r9),%rax\nmov %r13d,0x2c(%rsp,%r12,1)\ncmp %rbx,%r9\njne 1bbd \nmov (%rsp),%rax\nmov %edi,0x12c0(%rsp)\nlea 0x8(%r10),%rdi\nand $0xfffffffffffffff8,%rdi\nmov %rax,(%r10)\nmov 0x12bc(%rsp),%rax\nmov %rax,0x12bc(%r10)\nmov %r10,%rax\nsub %rdi,%rax\nsub %rax,%rsi\nadd $0x12c4,%eax\nshr $0x3,%eax\nmov %eax,%ecx\nrep movsq %ds:(%rsi),%es:(%rdi)\nmov 0x12c8(%rsp),%rax\nxor %fs:0x28,%rax\njne 1c9b \nadd $0x12d8,%rsp\nmov %r10,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nxor %edi,%edi\nmov %rsp,%rsi\njmp 1c35 \ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 1000h\nor [rsp+1018h+var_1018], 0\nsub rsp, 2D0h\nmov rax, fs:28h\nmov [rsp+12E8h+var_20], rax\nxor eax, eax\nmov r10, rdi\ntest ecx, ecx\njle loc_1C69\nmovsxd rcx, ecx\nmov r11, rsi\nmov rbx, rdx\nxor r9d, r9d\nlea rbp, ds:0[rcx*4]\nmov rsi, rsp\nxor ecx, ecx\nnop word ptr [rax+rax+00h]\nloc_1AF8:\nmov r8d, [r11+r9]\nmov edi, [rbx+r9]\ntest ecx, ecx\njle loc_1B90\nloc_1B08:\nmov rax, rsi\nxor edx, edx\njmp short loc_1B1B\nloc_1B10:\nadd edx, 1\nadd rax, 30h ; '0'\ncmp edx, ecx\njz short loc_1B70\nloc_1B1B:\ncmp [rax], edi\njnz short loc_1B10\nloc_1B1F:\nmov rdx, rsi\nxor eax, eax\njmp short loc_1B3B\nloc_1B30:\nadd eax, 1\nadd rdx, 30h ; '0'\ncmp eax, ecx\njz short loc_1BB8\nloc_1B3B:\ncmp [rdx], r8d\njnz short loc_1B30\ncdqe\nlea rdx, [rax+rax*2]\nshl rdx, 4\nmovsxd rdx, [rsp+rdx+12E8h+var_12BC]\ncmp edx, 9\njle loc_1C60\nadd r9, 4\ncmp r9, rbp\njz loc_1C02\nmov r8d, [r11+r9]\nmov edi, [rbx+r9]\njmp short loc_1B08\nloc_1B70:\nmovsxd rax, ecx\nadd ecx, 1\nlea rax, [rax+rax*2]\nshl rax, 4\nmov dword ptr [rsp+rax+12E8h+var_12E8], edi\nmov [rsp+rax+12E8h+var_12BC], 0\njmp short loc_1B1F\nloc_1B90:\nmovsxd rax, ecx\nadd ecx, 1\nlea rax, [rax+rax*2]\nshl rax, 4\nmov dword ptr [rsp+rax+12E8h+var_12E8], edi\nmov [rsp+rax+12E8h+var_12BC], 0\ncmp ecx, 1\njz loc_1B1F\nnop word ptr [rax+rax+00h]\nloc_1BB8:\nmovsxd rax, ecx\nmov r12d, 1\nxor edx, edx\nlea rax, [rax+rax*2]\nshl rax, 4\nmov dword ptr [rsp+rax+12E8h+var_12E8], r8d\nmov [rsp+rax+12E8h+var_12BC], 0\nmovsxd rax, ecx\nadd ecx, 1\nloc_1BDD:\nlea rax, [rax+rax*2]\nadd r9, 4\nmov r8, rax\nlea rax, [rdx+rax*4]\nshl r8, 4\nmov dword ptr [rsp+rax*4+12E8h+var_12E8+4], edi\nmov [rsp+r8+12E8h+var_12BC], r12d\ncmp r9, rbp\njnz loc_1AF8\nloc_1C02:\nmov rax, [rsp+12E8h+var_12E8]\nmov [rsp+12E8h+var_28], ecx\nlea rdi, [r10+8]\nand rdi, 0FFFFFFFFFFFFFFF8h\nmov [r10], rax\nmov rax, [rsp+12BCh]\nmov [r10+12BCh], rax\nmov rax, r10\nsub rax, rdi\nsub rsi, rax\nadd eax, 12C4h\nshr eax, 3\nmov ecx, eax\nrep movsq\nmov rax, [rsp+12E8h+var_20]\nsub rax, fs:28h\njnz short loc_1C70\nadd rsp, 12D0h\nmov rax, r10\npop rbx\npop rbp\npop r12\nretn\nloc_1C60:\nlea r12d, [rdx+1]\njmp loc_1BDD\nloc_1C69:\nxor ecx, ecx\nmov rsi, rsp\njmp short loc_1C02\nloc_1C70:\ncall ___stack_chk_fail", + "ida_pseudo": "_QWORD *__fastcall func0(_QWORD *a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 v6; // r9\n __int64 v7; // rbp\n int v8; // ecx\n int v9; // r8d\n int v10; // edi\n _DWORD *v11; // rax\n int v12; // edx\n _DWORD *v13; // rdx\n __int64 v14; // rax\n __int64 v15; // rdx\n __int64 v16; // rax\n __int64 v17; // rax\n int v18; // r12d\n __int64 v19; // rax\n _QWORD v21[90]; // [rsp+0h] [rbp-12E8h] BYREF\n __int64 v22; // [rsp+12BCh] [rbp-2Ch]\n unsigned __int64 v23; // [rsp+12C8h] [rbp-20h]\n\n v23 = __readfsqword(0x28u);\n if ( a4 > 0 )\n {\n v6 = 0LL;\n v7 = 4LL * a4;\n v8 = 0;\n while ( 1 )\n {\n v9 = *(_DWORD *)(a2 + v6);\n v10 = *(_DWORD *)(a3 + v6);\n if ( v8 > 0 )\n break;\n v17 = v8++;\n v17 *= 48LL;\n *(_DWORD *)((char *)v21 + v17) = v10;\n *(_DWORD *)((char *)&v21[5] + v17 + 4) = 0;\n if ( v8 == 1 )\n goto LABEL_7;\nLABEL_15:\n v18 = 1;\n v15 = 0LL;\n v19 = 6LL * v8;\n LODWORD(v21[v19]) = v9;\n HIDWORD(v21[v19 + 5]) = 0;\n v14 = v8++;\nLABEL_16:\n v6 += 4LL;\n *((_DWORD *)&v21[6 * v14] + v15 + 1) = v10;\n HIDWORD(v21[6 * v14 + 5]) = v18;\n if ( v6 == v7 )\n goto LABEL_17;\n }\n while ( 1 )\n {\n v11 = v21;\n v12 = 0;\n while ( *v11 != v10 )\n {\n ++v12;\n v11 += 12;\n if ( v12 == v8 )\n {\n v16 = v8++;\n v16 *= 48LL;\n *(_DWORD *)((char *)v21 + v16) = v10;\n *(_DWORD *)((char *)&v21[5] + v16 + 4) = 0;\n break;\n }\n }\nLABEL_7:\n v13 = v21;\n LODWORD(v14) = 0;\n while ( *v13 != v9 )\n {\n LODWORD(v14) = v14 + 1;\n v13 += 12;\n if ( (_DWORD)v14 == v8 )\n goto LABEL_15;\n }\n v14 = (int)v14;\n v15 = SHIDWORD(v21[6 * (int)v14 + 5]);\n if ( (int)v15 <= 9 )\n {\n v18 = v15 + 1;\n goto LABEL_16;\n }\n v6 += 4LL;\n if ( v6 == v7 )\n goto LABEL_17;\n v9 = *(_DWORD *)(a2 + v6);\n v10 = *(_DWORD *)(a3 + v6);\n }\n }\n v8 = 0;\nLABEL_17:\n HIDWORD(v22) = v8;\n *a1 = v21[0];\n *(_QWORD *)((char *)a1 + 4796) = v22;\n qmemcpy(\n (void *)((unsigned __int64)(a1 + 1) & 0xFFFFFFFFFFFFFFF8LL),\n (const void *)((char *)v21 - ((char *)a1 - ((unsigned __int64)(a1 + 1) & 0xFFFFFFFFFFFFFFF8LL))),\n 8LL * (((unsigned int)a1 - (((_DWORD)a1 + 8) & 0xFFFFFFF8) + 4804) >> 3));\n return a1;\n}", + "ida_strip_asm": "sub_1AA0:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 1000h\nor [rsp+1018h+var_1018], 0\nsub rsp, 2D0h\nmov rax, fs:28h\nmov [rsp+12E8h+var_20], rax\nxor eax, eax\nmov r10, rdi\ntest ecx, ecx\njle loc_1C69\nmovsxd rcx, ecx\nmov r11, rsi\nmov rbx, rdx\nxor r9d, r9d\nlea rbp, ds:0[rcx*4]\nmov rsi, rsp\nxor ecx, ecx\nnop word ptr [rax+rax+00h]\nloc_1AF8:\nmov r8d, [r11+r9]\nmov edi, [rbx+r9]\ntest ecx, ecx\njle loc_1B90\nloc_1B08:\nmov rax, rsi\nxor edx, edx\njmp short loc_1B1B\nloc_1B10:\nadd edx, 1\nadd rax, 30h ; '0'\ncmp edx, ecx\njz short loc_1B70\nloc_1B1B:\ncmp [rax], edi\njnz short loc_1B10\nloc_1B1F:\nmov rdx, rsi\nxor eax, eax\njmp short loc_1B3B\nloc_1B30:\nadd eax, 1\nadd rdx, 30h ; '0'\ncmp eax, ecx\njz short loc_1BB8\nloc_1B3B:\ncmp [rdx], r8d\njnz short loc_1B30\ncdqe\nlea rdx, [rax+rax*2]\nshl rdx, 4\nmovsxd rdx, [rsp+rdx+12E8h+var_12BC]\ncmp edx, 9\njle loc_1C60\nadd r9, 4\ncmp r9, rbp\njz loc_1C02\nmov r8d, [r11+r9]\nmov edi, [rbx+r9]\njmp short loc_1B08\nloc_1B70:\nmovsxd rax, ecx\nadd ecx, 1\nlea rax, [rax+rax*2]\nshl rax, 4\nmov dword ptr [rsp+rax+12E8h+var_12E8], edi\nmov [rsp+rax+12E8h+var_12BC], 0\njmp short loc_1B1F\nloc_1B90:\nmovsxd rax, ecx\nadd ecx, 1\nlea rax, [rax+rax*2]\nshl rax, 4\nmov dword ptr [rsp+rax+12E8h+var_12E8], edi\nmov [rsp+rax+12E8h+var_12BC], 0\ncmp ecx, 1\njz loc_1B1F\nnop word ptr [rax+rax+00h]\nloc_1BB8:\nmovsxd rax, ecx\nmov r12d, 1\nxor edx, edx\nlea rax, [rax+rax*2]\nshl rax, 4\nmov dword ptr [rsp+rax+12E8h+var_12E8], r8d\nmov [rsp+rax+12E8h+var_12BC], 0\nmovsxd rax, ecx\nadd ecx, 1\nloc_1BDD:\nlea rax, [rax+rax*2]\nadd r9, 4\nmov r8, rax\nlea rax, [rdx+rax*4]\nshl r8, 4\nmov dword ptr [rsp+rax*4+12E8h+var_12E8+4], edi\nmov [rsp+r8+12E8h+var_12BC], r12d\ncmp r9, rbp\njnz loc_1AF8\nloc_1C02:\nmov rax, [rsp+12E8h+var_12E8]\nmov [rsp+12E8h+var_28], ecx\nlea rdi, [r10+8]\nand rdi, 0FFFFFFFFFFFFFFF8h\nmov [r10], rax\nmov rax, [rsp+12BCh]\nmov [r10+12BCh], rax\nmov rax, r10\nsub rax, rdi\nsub rsi, rax\nadd eax, 12C4h\nshr eax, 3\nmov ecx, eax\nrep movsq\nmov rax, [rsp+12E8h+var_20]\nsub rax, fs:28h\njnz short loc_1C70\nadd rsp, 12D0h\nmov rax, r10\npop rbx\npop rbp\npop r12\nretn\nloc_1C60:\nlea r12d, [rdx+1]\njmp loc_1BDD\nloc_1C69:\nxor ecx, ecx\nmov rsi, rsp\njmp short loc_1C02\nloc_1C70:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1AA0(_QWORD *a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 v6; // r9\n __int64 v7; // rbp\n int v8; // ecx\n int v9; // r8d\n int v10; // edi\n _DWORD *v11; // rax\n int v12; // edx\n _DWORD *v13; // rdx\n __int64 v14; // rax\n __int64 v15; // rdx\n __int64 v16; // rax\n __int64 v17; // rax\n int v18; // r12d\n __int64 v19; // rax\n _QWORD v21[90]; // [rsp+0h] [rbp-12E8h] BYREF\n __int64 v22; // [rsp+12BCh] [rbp-2Ch]\n unsigned __int64 v23; // [rsp+12C8h] [rbp-20h]\n\n v23 = __readfsqword(0x28u);\n if ( a4 > 0 )\n {\n v6 = 0LL;\n v7 = 4LL * a4;\n v8 = 0;\n while ( 1 )\n {\n v9 = *(_DWORD *)(a2 + v6);\n v10 = *(_DWORD *)(a3 + v6);\n if ( v8 > 0 )\n break;\n v17 = v8++;\n v17 *= 48LL;\n *(_DWORD *)((char *)v21 + v17) = v10;\n *(_DWORD *)((char *)&v21[5] + v17 + 4) = 0;\n if ( v8 == 1 )\n goto LABEL_7;\nLABEL_15:\n v18 = 1;\n v15 = 0LL;\n v19 = 6LL * v8;\n LODWORD(v21[v19]) = v9;\n HIDWORD(v21[v19 + 5]) = 0;\n v14 = v8++;\nLABEL_16:\n v6 += 4LL;\n *((_DWORD *)&v21[6 * v14] + v15 + 1) = v10;\n HIDWORD(v21[6 * v14 + 5]) = v18;\n if ( v6 == v7 )\n goto LABEL_17;\n }\n while ( 1 )\n {\n v11 = v21;\n v12 = 0;\n while ( *v11 != v10 )\n {\n ++v12;\n v11 += 12;\n if ( v12 == v8 )\n {\n v16 = v8++;\n v16 *= 48LL;\n *(_DWORD *)((char *)v21 + v16) = v10;\n *(_DWORD *)((char *)&v21[5] + v16 + 4) = 0;\n break;\n }\n }\nLABEL_7:\n v13 = v21;\n LODWORD(v14) = 0;\n while ( *v13 != v9 )\n {\n LODWORD(v14) = v14 + 1;\n v13 += 12;\n if ( (_DWORD)v14 == v8 )\n goto LABEL_15;\n }\n v14 = (int)v14;\n v15 = SHIDWORD(v21[6 * (int)v14 + 5]);\n if ( (int)v15 <= 9 )\n {\n v18 = v15 + 1;\n goto LABEL_16;\n }\n v6 += 4LL;\n if ( v6 == v7 )\n goto LABEL_17;\n v9 = *(_DWORD *)(a2 + v6);\n v10 = *(_DWORD *)(a3 + v6);\n }\n }\n v8 = 0;\nLABEL_17:\n HIDWORD(v22) = v8;\n *a1 = v21[0];\n *(_QWORD *)((char *)a1 + 4796) = v22;\n qmemcpy(\n (void *)((unsigned __int64)(a1 + 1) & 0xFFFFFFFFFFFFFFF8LL),\n (const void *)((char *)v21 - ((char *)a1 - ((unsigned __int64)(a1 + 1) & 0xFFFFFFFFFFFFFFF8LL))),\n 8LL * (((unsigned int)a1 - (((_DWORD)a1 + 8) & 0xFFFFFFF8) + 4804) >> 3));\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1AA0(uint64_t *a1, long long a2, long long a3, int a4) {\n long long v6;\n long long v7;\n int v8;\n int v9;\n int v10;\n uint32_t *v11;\n int v12;\n uint32_t *v13;\n long long v14;\n long long v15;\n long long v16;\n long long v17;\n int v18;\n long long v19;\n uint64_t v21[90];\n long long v22;\n unsigned long long v23;\n v23 = __readfsqword(40u);\n if (a4 > 0) {\n v6 = 0LL;\n v7 = 4LL * a4;\n v8 = 0;\n while (1) {\n v9 = *(uint32_t *)(a2 + v6);\n v10 = *(uint32_t *)(a3 + v6);\n if (v8 > 0) break;\n v17 = v8++;\n v17 *= 48LL;\n *(uint32_t *)((char *)v21 + v17) = v10;\n *(uint32_t *)((char *)&v21[5] + v17 + 4) = 0;\n if (v8 == 1) goto LABEL_7;\n LABEL_15:\n v18 = 1;\n v15 = 0LL;\n v19 = 6LL * v8;\n LODWORD(v21[v19]) = v9;\n HIDWORD(v21[v19 + 5]) = 0;\n v14 = v8++;\n LABEL_16:\n v6 += 4LL;\n *((uint32_t *)&v21[6 * v14] + v15 + 1) = v10;\n HIDWORD(v21[6 * v14 + 5]) = v18;\n if (v6 == v7) goto LABEL_17;\n }\n while (1) {\n v11 = v21;\n v12 = 0;\n while (*v11 != v10) {\n ++v12;\n v11 += 12;\n if (v12 == v8) {\n v16 = v8++;\n v16 *= 48LL;\n *(uint32_t *)((char *)v21 + v16) = v10;\n *(uint32_t *)((char *)&v21[5] + v16 + 4) = 0;\n break;\n }\n }\n LABEL_7:\n v13 = v21;\n LODWORD(v14) = 0;\n while (*v13 != v9) {\n LODWORD(v14) = v14 + 1;\n v13 += 12;\n if ((uint32_t)v14 == v8) goto LABEL_15;\n }\n v14 = (int)v14;\n v15 = SHIDWORD(v21[6 * (int)v14 + 5]);\n if ((int)v15 <= 9) {\n v18 = v15 + 1;\n goto LABEL_16;\n }\n v6 += 4LL;\n if (v6 == v7) goto LABEL_17;\n v9 = *(uint32_t *)(a2 + v6);\n v10 = *(uint32_t *)(a3 + v6);\n }\n }\n v8 = 0;\nLABEL_17:\n HIDWORD(v22) = v8;\n *a1 = v21[0];\n *(uint64_t *)((char *)a1 + 4796) = v22;\n qmemcpy(\n (void *)((unsigned long long)(a1 + 1) & 18446744073709551608LL),\n (const void *)((char *)v21 - ((char *)a1 - ((unsigned long long)(a1 + 1) &\n 18446744073709551608LL))),\n 8LL *\n (((unsigned int)a1 - (((uint32_t)a1 + 8) & 4294967288) + 4804) >> 3));\n return a1;\n}", + "ida_pseudo_norm": "uint64_t *func0(uint64_t *a1, long long a2, long long a3, int a4) {\n long long v6;\n long long v7;\n int v8;\n int v9;\n int v10;\n uint32_t *v11;\n int v12;\n uint32_t *v13;\n long long v14;\n long long v15;\n long long v16;\n long long v17;\n int v18;\n long long v19;\n uint64_t v21[90];\n long long v22;\n unsigned long long v23;\n v23 = __readfsqword(40u);\n if (a4 > 0) {\n v6 = 0LL;\n v7 = 4LL * a4;\n v8 = 0;\n while (1) {\n v9 = *(uint32_t *)(a2 + v6);\n v10 = *(uint32_t *)(a3 + v6);\n if (v8 > 0) break;\n v17 = v8++;\n v17 *= 48LL;\n *(uint32_t *)((char *)v21 + v17) = v10;\n *(uint32_t *)((char *)&v21[5] + v17 + 4) = 0;\n if (v8 == 1) goto LABEL_7;\n LABEL_15:\n v18 = 1;\n v15 = 0LL;\n v19 = 6LL * v8;\n LODWORD(v21[v19]) = v9;\n HIDWORD(v21[v19 + 5]) = 0;\n v14 = v8++;\n LABEL_16:\n v6 += 4LL;\n *((uint32_t *)&v21[6 * v14] + v15 + 1) = v10;\n HIDWORD(v21[6 * v14 + 5]) = v18;\n if (v6 == v7) goto LABEL_17;\n }\n while (1) {\n v11 = v21;\n v12 = 0;\n while (*v11 != v10) {\n ++v12;\n v11 += 12;\n if (v12 == v8) {\n v16 = v8++;\n v16 *= 48LL;\n *(uint32_t *)((char *)v21 + v16) = v10;\n *(uint32_t *)((char *)&v21[5] + v16 + 4) = 0;\n break;\n }\n }\n LABEL_7:\n v13 = v21;\n LODWORD(v14) = 0;\n while (*v13 != v9) {\n LODWORD(v14) = v14 + 1;\n v13 += 12;\n if ((uint32_t)v14 == v8) goto LABEL_15;\n }\n v14 = (int)v14;\n v15 = SHIDWORD(v21[6 * (int)v14 + 5]);\n if ((int)v15 <= 9) {\n v18 = v15 + 1;\n goto LABEL_16;\n }\n v6 += 4LL;\n if (v6 == v7) goto LABEL_17;\n v9 = *(uint32_t *)(a2 + v6);\n v10 = *(uint32_t *)(a3 + v6);\n }\n }\n v8 = 0;\nLABEL_17:\n HIDWORD(v22) = v8;\n *a1 = v21[0];\n *(uint64_t *)((char *)a1 + 4796) = v22;\n qmemcpy(\n (void *)((unsigned long long)(a1 + 1) & 18446744073709551608LL),\n (const void *)((char *)v21 - ((char *)a1 - ((unsigned long long)(a1 + 1) &\n 18446744073709551608LL))),\n 8LL *\n (((unsigned int)a1 - (((uint32_t)a1 + 8) & 4294967288) + 4804) >> 3));\n return a1;\n}" + }, + { + "index": 562, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(int** lst, int* sizes, int lst_size) {\n int maxLength = 0;\n for (int i = 0; i < lst_size; i++) {\n if (sizes[i] > maxLength) {\n maxLength = sizes[i];\n }\n }\n return maxLength;\n}", + "test": "int main() {\n\n int lst1_sizes[] = {1, 2, 4};\n\n int* lst1[] = {(int[]){1}, (int[]){1, 4}, (int[]){5, 6, 7, 8}};\n\n assert(func0(lst1, lst1_sizes, 3) == 4);\n\n\n\n int lst2_sizes[] = {2, 2, 3};\n\n int* lst2[] = {(int[]){0, 1}, (int[]){2, 2}, (int[]){3, 2, 1}};\n\n assert(func0(lst2, lst2_sizes, 3) == 3);\n\n\n\n int lst3_sizes[] = {1, 2, 3, 5};\n\n int* lst3[] = {(int[]){7}, (int[]){22, 23}, (int[]){13, 14, 15}, (int[]){10, 20, 30, 40, 50}};\n\n assert(func0(lst3, lst3_sizes, 4) == 5);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %edx,-0x24(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11c4 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x8(%rbp)\njge 11c0 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x24(%rbp),%eax\njl 118c \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11C4\nloc_118C:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_8], eax\njge short loc_11C0\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_8], eax\nloc_11C0:\nadd [rbp+var_4], 1\nloc_11C4:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_24]\njl short loc_118C\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n unsigned int v4; // [rsp+1Ch] [rbp-8h]\n int i; // [rsp+20h] [rbp-4h]\n\n v4 = 0;\n for ( i = 0; i < a3; ++i )\n {\n if ( (signed int)v4 < *(_DWORD *)(4LL * i + a2) )\n v4 = *(_DWORD *)(4LL * i + a2);\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11C4\nloc_118C:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_8], eax\njge short loc_11C0\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_8], eax\nloc_11C0:\nadd [rbp+var_4], 1\nloc_11C4:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_24]\njl short loc_118C\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, int a3)\n{\n unsigned int v4; // [rsp+1Ch] [rbp-8h]\n int i; // [rsp+20h] [rbp-4h]\n\n v4 = 0;\n for ( i = 0; i < a3; ++i )\n {\n if ( (signed int)v4 < *(_DWORD *)(4LL * i + a2) )\n v4 = *(_DWORD *)(4LL * i + a2);\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, int a3) {\n unsigned int v4;\n int i;\n v4 = 0;\n for (i = 0; i < a3; ++i) {\n if ((signed int)v4 < *(uint32_t *)(4LL * i + a2))\n v4 = *(uint32_t *)(4LL * i + a2);\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3) {\n unsigned int v4;\n int i;\n v4 = 0;\n for (i = 0; i < a3; ++i) {\n if ((signed int)v4 < *(uint32_t *)(4LL * i + a2))\n v4 = *(uint32_t *)(4LL * i + a2);\n }\n return v4;\n}" + }, + { + "index": 562, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(int** lst, int* sizes, int lst_size) {\n int maxLength = 0;\n for (int i = 0; i < lst_size; i++) {\n if (sizes[i] > maxLength) {\n maxLength = sizes[i];\n }\n }\n return maxLength;\n}", + "test": "int main() {\n\n int lst1_sizes[] = {1, 2, 4};\n\n int* lst1[] = {(int[]){1}, (int[]){1, 4}, (int[]){5, 6, 7, 8}};\n\n assert(func0(lst1, lst1_sizes, 3) == 4);\n\n\n\n int lst2_sizes[] = {2, 2, 3};\n\n int* lst2[] = {(int[]){0, 1}, (int[]){2, 2}, (int[]){3, 2, 1}};\n\n assert(func0(lst2, lst2_sizes, 3) == 3);\n\n\n\n int lst3_sizes[] = {1, 2, 3, 5};\n\n int* lst3[] = {(int[]){7}, (int[]){22, 23}, (int[]){13, 14, 15}, (int[]){10, 20, 30, 40, 50}};\n\n assert(func0(lst3, lst3_sizes, 4) == 5);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edx,%edx\njle 1194 \nmov %rsi,%rax\nlea -0x1(%rdx),%edx\nlea 0x4(%rsi,%rdx,4),%rsi\nmov $0x0,%edx\nmov (%rax),%ecx\ncmp %ecx,%edx\ncmovl %ecx,%edx\nadd $0x4,%rax\ncmp %rsi,%rax\njne 1181 \nmov %edx,%eax\nretq\nmov $0x0,%edx\njmp 1191 \n", + "ida_asm": "func0:\nendbr64\ntest edx, edx\njle short loc_1193\nmov rax, rsi\nmovsxd rdx, edx\nlea rsi, [rsi+rdx*4]\nmov edx, 0\nloc_1180:\nmov ecx, [rax]\ncmp edx, ecx\ncmovl edx, ecx\nadd rax, 4\ncmp rax, rsi\njnz short loc_1180\nloc_1190:\nmov eax, edx\nretn\nloc_1193:\nmov edx, 0\njmp short loc_1190", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, unsigned int *a2, int a3)\n{\n unsigned int *v3; // rax\n unsigned int *v4; // rsi\n unsigned int v5; // edx\n\n if ( a3 <= 0 )\n {\n return 0;\n }\n else\n {\n v3 = a2;\n v4 = &a2[a3];\n v5 = 0;\n do\n {\n if ( (int)v5 < (int)*v3 )\n v5 = *v3;\n ++v3;\n }\n while ( v3 != v4 );\n }\n return v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest edx, edx\njle short loc_1193\nmov rax, rsi\nmovsxd rdx, edx\nlea rsi, [rsi+rdx*4]\nmov edx, 0\nloc_1180:\nmov ecx, [rax]\ncmp edx, ecx\ncmovl edx, ecx\nadd rax, 4\ncmp rax, rsi\njnz short loc_1180\nloc_1190:\nmov eax, edx\nretn\nloc_1193:\nmov edx, 0\njmp short loc_1190", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, unsigned int *a2, int a3)\n{\n unsigned int *v3; // rax\n unsigned int *v4; // rsi\n unsigned int v5; // edx\n\n if ( a3 <= 0 )\n {\n return 0;\n }\n else\n {\n v3 = a2;\n v4 = &a2[a3];\n v5 = 0;\n do\n {\n if ( (int)v5 < (int)*v3 )\n v5 = *v3;\n ++v3;\n }\n while ( v3 != v4 );\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, unsigned int *a2, int a3) {\n unsigned int *v3;\n unsigned int *v4;\n unsigned int v5;\n if (a3 <= 0) {\n return 0;\n } else {\n v3 = a2;\n v4 = &a2[a3];\n v5 = 0;\n do {\n if ((int)v5 < (int)*v3) v5 = *v3;\n ++v3;\n } while (v3 != v4);\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(long long a1, unsigned int *a2, int a3) {\n unsigned int *v3;\n unsigned int *v4;\n unsigned int v5;\n if (a3 <= 0) {\n return 0;\n } else {\n v3 = a2;\n v4 = &a2[a3];\n v5 = 0;\n do {\n if ((int)v5 < (int)*v3) v5 = *v3;\n ++v3;\n } while (v3 != v4);\n }\n return v5;\n}" + }, + { + "index": 563, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(const char *text, char values[][50], int *count) {\n int index = 0;\n *count = 0;\n const char *start = NULL;\n const char *end = NULL;\n while ((start = strchr(text, '\"')) != NULL) {\n end = strchr(start + 1, '\"');\n if (end == NULL) break;\n int len = end - (start + 1);\n strncpy(values[index], start + 1, len);\n values[index][len] = '\\0';\n index++;\n text = end + 1;\n }\n *count = index;\n}", + "test": "int main() {\n\n char values[10][50];\n\n int count, i;\n\n\n\n func0(\"\\\"Python\\\", \\\"PHP\\\", \\\"Java\\\"\", values, &count);\n\n assert(count == 3);\n\n assert(strcmp(values[0], \"Python\") == 0);\n\n assert(strcmp(values[1], \"PHP\") == 0);\n\n assert(strcmp(values[2], \"Java\") == 0);\n\n\n\n func0(\"\\\"python\\\",\\\"program\\\",\\\"language\\\"\", values, &count);\n\n assert(count == 3);\n\n assert(strcmp(values[0], \"python\") == 0);\n\n assert(strcmp(values[1], \"program\") == 0);\n\n assert(strcmp(values[2], \"language\") == 0);\n\n\n\n func0(\"\\\"red\\\",\\\"blue\\\",\\\"green\\\",\\\"yellow\\\"\", values, &count);\n\n assert(count == 4);\n\n assert(strcmp(values[0], \"red\") == 0);\n\n assert(strcmp(values[1], \"blue\") == 0);\n\n assert(strcmp(values[2], \"green\") == 0);\n\n assert(strcmp(values[3], \"yellow\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x40,%rsp\nmov %rdi,-0x28(%rbp)\nmov %rsi,-0x30(%rbp)\nmov %rdx,-0x38(%rbp)\nmovl $0x0,-0x18(%rbp)\nmov -0x38(%rbp),%rax\nmovl $0x0,(%rax)\nmovq $0x0,-0x10(%rbp)\nmovq $0x0,-0x8(%rbp)\njmpq 12bf \nmov -0x10(%rbp),%rax\nadd $0x1,%rax\nmov $0x22,%esi\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\ncmpq $0x0,-0x8(%rbp)\nje 12e1 \nmov -0x10(%rbp),%rax\nlea 0x1(%rax),%rdx\nmov -0x8(%rbp),%rax\nsub %rdx,%rax\nmov %eax,-0x14(%rbp)\nmov -0x14(%rbp),%eax\nmovslq %eax,%rcx\nmov -0x10(%rbp),%rax\nlea 0x1(%rax),%rsi\nmov -0x18(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nadd %rax,%rax\nmov %rax,%rdx\nmov -0x30(%rbp),%rax\nadd %rdx,%rax\nmov %rcx,%rdx\nmov %rax,%rdi\ncallq 1090 \nmov -0x18(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nadd %rax,%rax\nmov %rax,%rdx\nmov -0x30(%rbp),%rax\nadd %rax,%rdx\nmov -0x14(%rbp),%eax\ncltq\nmovb $0x0,(%rdx,%rax,1)\naddl $0x1,-0x18(%rbp)\nmov -0x8(%rbp),%rax\nadd $0x1,%rax\nmov %rax,-0x28(%rbp)\nmov -0x28(%rbp),%rax\nmov $0x22,%esi\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x10(%rbp)\ncmpq $0x0,-0x10(%rbp)\njne 1207 \njmp 12e2 \nmov -0x38(%rbp),%rax\nmov -0x18(%rbp),%edx\nmov %edx,(%rax)\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+s], rdi\nmov [rbp+var_30], rsi\nmov [rbp+var_38], rdx\nmov [rbp+var_18], 0\nmov rax, [rbp+var_38]\nmov dword ptr [rax], 0\nmov [rbp+var_10], 0\nmov [rbp+var_8], 0\njmp loc_12BF\nloc_1207:\nmov rax, [rbp+var_10]\nadd rax, 1\nmov esi, 22h ; '\"'; c\nmov rdi, rax; s\ncall _strchr\nmov [rbp+var_8], rax\ncmp [rbp+var_8], 0\njz loc_12E1\nmov rax, [rbp+var_10]\nlea rdx, [rax+1]\nmov rax, [rbp+var_8]\nsub rax, rdx\nmov [rbp+var_14], eax\nmov eax, [rbp+var_14]\nmovsxd rcx, eax\nmov rax, [rbp+var_10]\nlea rsi, [rax+1]; src\nmov eax, [rbp+var_18]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nadd rax, rax\nmov rdx, rax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov rdx, rcx; n\nmov rdi, rax; dest\ncall _strncpy\nmov eax, [rbp+var_18]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nadd rax, rax\nmov rdx, rax\nmov rax, [rbp+var_30]\nadd rdx, rax\nmov eax, [rbp+var_14]\ncdqe\nmov byte ptr [rdx+rax], 0\nadd [rbp+var_18], 1\nmov rax, [rbp+var_8]\nadd rax, 1\nmov [rbp+s], rax\nloc_12BF:\nmov rax, [rbp+s]\nmov esi, 22h ; '\"'; c\nmov rdi, rax; s\ncall _strchr\nmov [rbp+var_10], rax\ncmp [rbp+var_10], 0\njnz loc_1207\njmp short loc_12E2\nloc_12E1:\nnop\nloc_12E2:\nmov rax, [rbp+var_38]\nmov edx, [rbp+var_18]\nmov [rax], edx\nnop\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(const char *a1, __int64 a2, _DWORD *a3)\n{\n char *i; // rax\n _DWORD *result; // rax\n int v6; // [rsp+28h] [rbp-18h]\n char *v7; // [rsp+30h] [rbp-10h]\n char *v8; // [rsp+38h] [rbp-8h]\n\n v6 = 0;\n *a3 = 0;\n for ( i = strchr(a1, 34); ; i = strchr(v8 + 1, 34) )\n {\n v7 = i;\n if ( !i )\n break;\n v8 = strchr(i + 1, 34);\n if ( !v8 )\n break;\n strncpy((char *)(50LL * v6 + a2), v7 + 1, (int)v8 - ((int)v7 + 1));\n *(_BYTE *)(a2 + 50LL * v6++ + (int)v8 - ((int)v7 + 1)) = 0;\n }\n result = a3;\n *a3 = v6;\n return result;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+s], rdi\nmov [rbp+var_30], rsi\nmov [rbp+var_38], rdx\nmov [rbp+var_18], 0\nmov rax, [rbp+var_38]\nmov dword ptr [rax], 0\nmov [rbp+var_10], 0\nmov [rbp+var_8], 0\njmp loc_12BF\nloc_1207:\nmov rax, [rbp+var_10]\nadd rax, 1\nmov esi, 22h ; '\"'; c\nmov rdi, rax; s\ncall _strchr\nmov [rbp+var_8], rax\ncmp [rbp+var_8], 0\njz loc_12E1\nmov rax, [rbp+var_10]\nlea rdx, [rax+1]\nmov rax, [rbp+var_8]\nsub rax, rdx\nmov [rbp+var_14], eax\nmov eax, [rbp+var_14]\nmovsxd rcx, eax\nmov rax, [rbp+var_10]\nlea rsi, [rax+1]; src\nmov eax, [rbp+var_18]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nadd rax, rax\nmov rdx, rax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov rdx, rcx; n\nmov rdi, rax; dest\ncall _strncpy\nmov eax, [rbp+var_18]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nadd rax, rax\nmov rdx, rax\nmov rax, [rbp+var_30]\nadd rdx, rax\nmov eax, [rbp+var_14]\ncdqe\nmov byte ptr [rdx+rax], 0\nadd [rbp+var_18], 1\nmov rax, [rbp+var_8]\nadd rax, 1\nmov [rbp+s], rax\nloc_12BF:\nmov rax, [rbp+s]\nmov esi, 22h ; '\"'; c\nmov rdi, rax; s\ncall _strchr\nmov [rbp+var_10], rax\ncmp [rbp+var_10], 0\njnz loc_1207\njmp short loc_12E2\nloc_12E1:\nnop\nloc_12E2:\nmov rax, [rbp+var_38]\nmov edx, [rbp+var_18]\nmov [rax], edx\nnop\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11C9(const char *a1, __int64 a2, _DWORD *a3)\n{\n char *i; // rax\n _DWORD *result; // rax\n int v6; // [rsp+28h] [rbp-18h]\n char *v7; // [rsp+30h] [rbp-10h]\n char *v8; // [rsp+38h] [rbp-8h]\n\n v6 = 0;\n *a3 = 0;\n for ( i = strchr(a1, 34); ; i = strchr(v8 + 1, 34) )\n {\n v7 = i;\n if ( !i )\n break;\n v8 = strchr(i + 1, 34);\n if ( !v8 )\n break;\n strncpy((char *)(50LL * v6 + a2), v7 + 1, (int)v8 - ((int)v7 + 1));\n *(_BYTE *)(a2 + 50LL * v6++ + (int)v8 - ((int)v7 + 1)) = 0;\n }\n result = a3;\n *a3 = v6;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11C9(const char *a1, long long a2, uint32_t *a3) {\n char *i;\n uint32_t *result;\n int v6;\n char *v7;\n char *v8;\n v6 = 0;\n *a3 = 0;\n for (i = strchr(a1, 34);; i = strchr(v8 + 1, 34)) {\n v7 = i;\n if (!i) break;\n v8 = strchr(i + 1, 34);\n if (!v8) break;\n strncpy((char *)(50LL * v6 + a2), v7 + 1, (int)v8 - ((int)v7 + 1));\n *(uint8_t *)(a2 + 50LL * v6++ + (int)v8 - ((int)v7 + 1)) = 0;\n }\n result = a3;\n *a3 = v6;\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(const char *a1, long long a2, uint32_t *a3) {\n char *i;\n uint32_t *result;\n int v6;\n char *v7;\n char *v8;\n v6 = 0;\n *a3 = 0;\n for (i = strchr(a1, 34);; i = strchr(v8 + 1, 34)) {\n v7 = i;\n if (!i) break;\n v8 = strchr(i + 1, 34);\n if (!v8) break;\n strncpy((char *)(50LL * v6 + a2), v7 + 1, (int)v8 - ((int)v7 + 1));\n *(uint8_t *)(a2 + 50LL * v6++ + (int)v8 - ((int)v7 + 1)) = 0;\n }\n result = a3;\n *a3 = v6;\n return result;\n}" + }, + { + "index": 563, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(const char *text, char values[][50], int *count) {\n int index = 0;\n *count = 0;\n const char *start = NULL;\n const char *end = NULL;\n while ((start = strchr(text, '\"')) != NULL) {\n end = strchr(start + 1, '\"');\n if (end == NULL) break;\n int len = end - (start + 1);\n strncpy(values[index], start + 1, len);\n values[index][len] = '\\0';\n index++;\n text = end + 1;\n }\n *count = index;\n}", + "test": "int main() {\n\n char values[10][50];\n\n int count, i;\n\n\n\n func0(\"\\\"Python\\\", \\\"PHP\\\", \\\"Java\\\"\", values, &count);\n\n assert(count == 3);\n\n assert(strcmp(values[0], \"Python\") == 0);\n\n assert(strcmp(values[1], \"PHP\") == 0);\n\n assert(strcmp(values[2], \"Java\") == 0);\n\n\n\n func0(\"\\\"python\\\",\\\"program\\\",\\\"language\\\"\", values, &count);\n\n assert(count == 3);\n\n assert(strcmp(values[0], \"python\") == 0);\n\n assert(strcmp(values[1], \"program\") == 0);\n\n assert(strcmp(values[2], \"language\") == 0);\n\n\n\n func0(\"\\\"red\\\",\\\"blue\\\",\\\"green\\\",\\\"yellow\\\"\", values, &count);\n\n assert(count == 4);\n\n assert(strcmp(values[0], \"red\") == 0);\n\n assert(strcmp(values[1], \"blue\") == 0);\n\n assert(strcmp(values[2], \"green\") == 0);\n\n assert(strcmp(values[3], \"yellow\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdx,%r13\nmovl $0x0,(%rdx)\nmov %rsi,%rbp\nmov $0x0,%r12d\nmov $0x22,%esi\ncallq 10a0 \ntest %rax,%rax\nje 1220 \nlea 0x1(%rax),%rbx\nmov $0x22,%esi\nmov %rbx,%rdi\ncallq 10a0 \nmov %rax,%r14\ntest %rax,%rax\nje 1220 \nmov %rax,%r15\nsub %rbx,%r15\nmovslq %r15d,%r15\nmov %r15,%rdx\nmov %rbx,%rsi\nmov %rbp,%rdi\ncallq 1080 \nmovb $0x0,0x0(%rbp,%r15,1)\nadd $0x1,%r12d\nlea 0x1(%r14),%rdi\nadd $0x32,%rbp\njmp 11cd \nmov %r12d,0x0(%r13)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r13, rdx\nmov dword ptr [rdx], 0\nmov rbp, rsi\nmov r12d, 0\njmp short loc_1218\nloc_11EF:\nmov r15, rax\nsub r15, rbx\nmovsxd r15, r15d\nmov rdx, r15; n\nmov rsi, rbx; src\nmov rdi, rbp; dest\ncall _strncpy\nmov byte ptr [rbp+r15+0], 0\nadd r12d, 1\nlea rdi, [r14+1]; s\nadd rbp, 32h ; '2'\nloc_1218:\nmov esi, 22h ; '\"'; c\ncall _strchr\ntest rax, rax\njz short loc_1240\nlea rbx, [rax+1]\nmov esi, 22h ; '\"'; c\nmov rdi, rbx; s\ncall _strchr\nmov r14, rax\ntest rax, rax\njnz short loc_11EF\nloc_1240:\nmov [r13+0], r12d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "char *__fastcall func0(const char *a1, char *a2, _DWORD *a3)\n{\n int i; // r12d\n size_t v6; // r15\n char *result; // rax\n const char *v8; // rbx\n char *v9; // r14\n\n *a3 = 0;\n for ( i = 0; ; ++i )\n {\n result = strchr(a1, 34);\n if ( !result )\n break;\n v8 = result + 1;\n result = strchr(result + 1, 34);\n v9 = result;\n if ( !result )\n break;\n v6 = (int)result - (int)v8;\n strncpy(a2, v8, v6);\n a2[v6] = 0;\n a1 = v9 + 1;\n a2 += 50;\n }\n *a3 = i;\n return result;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r13, rdx\nmov dword ptr [rdx], 0\nmov rbp, rsi\nmov r12d, 0\njmp short loc_1218\nloc_11EF:\nmov r15, rax\nsub r15, rbx\nmovsxd r15, r15d\nmov rdx, r15; n\nmov rsi, rbx; src\nmov rdi, rbp; dest\ncall _strncpy\nmov byte ptr [rbp+r15+0], 0\nadd r12d, 1\nlea rdi, [r14+1]; s\nadd rbp, 32h ; '2'\nloc_1218:\nmov esi, 22h ; '\"'; c\ncall _strchr\ntest rax, rax\njz short loc_1240\nlea rbx, [rax+1]\nmov esi, 22h ; '\"'; c\nmov rdi, rbx; s\ncall _strchr\nmov r14, rax\ntest rax, rax\njnz short loc_11EF\nloc_1240:\nmov [r13+0], r12d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11C9(const char *a1, char *a2, _DWORD *a3)\n{\n int i; // r12d\n size_t v6; // r15\n char *result; // rax\n const char *v8; // rbx\n char *v9; // r14\n\n *a3 = 0;\n for ( i = 0; ; ++i )\n {\n result = strchr(a1, 34);\n if ( !result )\n break;\n v8 = result + 1;\n result = strchr(result + 1, 34);\n v9 = result;\n if ( !result )\n break;\n v6 = (int)result - (int)v8;\n strncpy(a2, v8, v6);\n a2[v6] = 0;\n a1 = v9 + 1;\n a2 += 50;\n }\n *a3 = i;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11C9(const char *a1, char *a2, uint32_t *a3) {\n int i;\n unsigned int v6;\n char *result;\n const char *v8;\n char *v9;\n *a3 = 0;\n for (i = 0;; ++i) {\n result = strchr(a1, 34);\n if (!result) break;\n v8 = result + 1;\n result = strchr(result + 1, 34);\n v9 = result;\n if (!result) break;\n v6 = (int)result - (int)v8;\n strncpy(a2, v8, v6);\n a2[v6] = 0;\n a1 = v9 + 1;\n a2 += 50;\n }\n *a3 = i;\n return result;\n}", + "ida_pseudo_norm": "char *func0(const char *a1, char *a2, uint32_t *a3) {\n int i;\n unsigned int v6;\n char *result;\n const char *v8;\n char *v9;\n *a3 = 0;\n for (i = 0;; ++i) {\n result = strchr(a1, 34);\n if (!result) break;\n v8 = result + 1;\n result = strchr(result + 1, 34);\n v9 = result;\n if (!result) break;\n v6 = (int)result - (int)v8;\n strncpy(a2, v8, v6);\n a2[v6] = 0;\n a1 = v9 + 1;\n a2 += 50;\n }\n *a3 = i;\n return result;\n}" + }, + { + "index": 563, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(const char *text, char values[][50], int *count) {\n int index = 0;\n *count = 0;\n const char *start = NULL;\n const char *end = NULL;\n while ((start = strchr(text, '\"')) != NULL) {\n end = strchr(start + 1, '\"');\n if (end == NULL) break;\n int len = end - (start + 1);\n strncpy(values[index], start + 1, len);\n values[index][len] = '\\0';\n index++;\n text = end + 1;\n }\n *count = index;\n}", + "test": "int main() {\n\n char values[10][50];\n\n int count, i;\n\n\n\n func0(\"\\\"Python\\\", \\\"PHP\\\", \\\"Java\\\"\", values, &count);\n\n assert(count == 3);\n\n assert(strcmp(values[0], \"Python\") == 0);\n\n assert(strcmp(values[1], \"PHP\") == 0);\n\n assert(strcmp(values[2], \"Java\") == 0);\n\n\n\n func0(\"\\\"python\\\",\\\"program\\\",\\\"language\\\"\", values, &count);\n\n assert(count == 3);\n\n assert(strcmp(values[0], \"python\") == 0);\n\n assert(strcmp(values[1], \"program\") == 0);\n\n assert(strcmp(values[2], \"language\") == 0);\n\n\n\n func0(\"\\\"red\\\",\\\"blue\\\",\\\"green\\\",\\\"yellow\\\"\", values, &count);\n\n assert(count == 4);\n\n assert(strcmp(values[0], \"red\") == 0);\n\n assert(strcmp(values[1], \"blue\") == 0);\n\n assert(strcmp(values[2], \"green\") == 0);\n\n assert(strcmp(values[3], \"yellow\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\nmov %rdx,%r13\npush %r12\nxor %r12d,%r12d\npush %rbp\npush %rbx\nmov %rsi,%rbx\nsub $0x8,%rsp\nmovl $0x0,(%rdx)\njmp 152a \nnopl 0x0(%rax,%rax,1)\nlea 0x1(%rax),%rbp\nmov $0x22,%esi\nmov %rbp,%rdi\ncallq 10a0 \nmov %rax,%r14\ntest %rax,%rax\nje 1539 \nmov %rax,%r15\nmov %rbx,%rdi\nmov %rbp,%rsi\nadd $0x1,%r12d\nsub %rbp,%r15\nadd $0x32,%rbx\nmovslq %r15d,%r15\nmov %r15,%rdx\ncallq 1080 \nmovb $0x0,-0x32(%rbx,%r15,1)\nlea 0x1(%r14),%rdi\nmov $0x22,%esi\ncallq 10a0 \ntest %rax,%rax\njne 14e8 \nmov %r12d,0x0(%r13)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\nmov r13, rdx\npush r12\nxor r12d, r12d\npush rbp\nmov rbp, rsi\npush rbx\nsub rsp, 8\nmov dword ptr [rdx], 0\njmp short loc_150A\nloc_14C8:\nlea rbx, [rax+1]\nmov esi, 22h ; '\"'; c\nmov rdi, rbx; s\ncall _strchr\nmov r14, rax\ntest rax, rax\njz short loc_1519\nmov r15, rax\nmov rdi, rbp; dest\nmov rsi, rbx; src\nadd r12d, 1\nsub r15, rbx\nadd rbp, 32h ; '2'\nmovsxd r15, r15d\nmov rdx, r15; n\ncall _strncpy\nmov byte ptr [rbp+r15-32h], 0\nlea rdi, [r14+1]; s\nloc_150A:\nmov esi, 22h ; '\"'; c\ncall _strchr\ntest rax, rax\njnz short loc_14C8\nloc_1519:\nmov [r13+0], r12d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "char *__fastcall func0(const char *a1, char *a2, _DWORD *a3)\n{\n int v4; // r12d\n const char *v6; // rbx\n char *result; // rax\n char *v8; // r14\n char *v9; // rdi\n size_t v10; // r15\n\n v4 = 0;\n *a3 = 0;\n while ( 1 )\n {\n result = strchr(a1, 34);\n if ( !result )\n break;\n v6 = result + 1;\n result = strchr(result + 1, 34);\n v8 = result;\n if ( !result )\n break;\n v9 = a2;\n ++v4;\n a2 += 50;\n v10 = (int)result - (int)v6;\n strncpy(v9, v6, v10);\n a2[v10 - 50] = 0;\n a1 = v8 + 1;\n }\n *a3 = v4;\n return result;\n}", + "ida_strip_asm": "sub_14A0:\nendbr64\npush r15\npush r14\npush r13\nmov r13, rdx\npush r12\nxor r12d, r12d\npush rbp\nmov rbp, rsi\npush rbx\nsub rsp, 8\nmov dword ptr [rdx], 0\njmp short loc_150A\nloc_14C8:\nlea rbx, [rax+1]\nmov esi, 22h ; '\"'; c\nmov rdi, rbx; s\ncall _strchr\nmov r14, rax\ntest rax, rax\njz short loc_1519\nmov r15, rax\nmov rdi, rbp; dest\nmov rsi, rbx; src\nadd r12d, 1\nsub r15, rbx\nadd rbp, 32h ; '2'\nmovsxd r15, r15d\nmov rdx, r15; n\ncall _strncpy\nmov byte ptr [rbp+r15-32h], 0\nlea rdi, [r14+1]; s\nloc_150A:\nmov esi, 22h ; '\"'; c\ncall _strchr\ntest rax, rax\njnz short loc_14C8\nloc_1519:\nmov [r13+0], r12d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "char *__fastcall sub_14A0(const char *a1, char *a2, _DWORD *a3)\n{\n int v4; // r12d\n const char *v6; // rbx\n char *result; // rax\n char *v8; // r14\n char *v9; // rdi\n size_t v10; // r15\n\n v4 = 0;\n *a3 = 0;\n while ( 1 )\n {\n result = strchr(a1, 34);\n if ( !result )\n break;\n v6 = result + 1;\n result = strchr(result + 1, 34);\n v8 = result;\n if ( !result )\n break;\n v9 = a2;\n ++v4;\n a2 += 50;\n v10 = (int)result - (int)v6;\n strncpy(v9, v6, v10);\n a2[v10 - 50] = 0;\n a1 = v8 + 1;\n }\n *a3 = v4;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_14A0(const char *a1, char *a2, uint32_t *a3) {\n int v4;\n const char *v6;\n char *result;\n char *v8;\n char *v9;\n unsigned int v10;\n v4 = 0;\n *a3 = 0;\n while (1) {\n result = strchr(a1, 34);\n if (!result) break;\n v6 = result + 1;\n result = strchr(result + 1, 34);\n v8 = result;\n if (!result) break;\n v9 = a2;\n ++v4;\n a2 += 50;\n v10 = (int)result - (int)v6;\n strncpy(v9, v6, v10);\n a2[v10 - 50] = 0;\n a1 = v8 + 1;\n }\n *a3 = v4;\n return result;\n}", + "ida_pseudo_norm": "char *func0(const char *a1, char *a2, uint32_t *a3) {\n int v4;\n const char *v6;\n char *result;\n char *v8;\n char *v9;\n unsigned int v10;\n v4 = 0;\n *a3 = 0;\n while (1) {\n result = strchr(a1, 34);\n if (!result) break;\n v6 = result + 1;\n result = strchr(result + 1, 34);\n v8 = result;\n if (!result) break;\n v9 = a2;\n ++v4;\n a2 += 50;\n v10 = (int)result - (int)v6;\n strncpy(v9, v6, v10);\n a2[v10 - 50] = 0;\n a1 = v8 + 1;\n }\n *a3 = v4;\n return result;\n}" + }, + { + "index": 563, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(const char *text, char values[][50], int *count) {\n int index = 0;\n *count = 0;\n const char *start = NULL;\n const char *end = NULL;\n while ((start = strchr(text, '\"')) != NULL) {\n end = strchr(start + 1, '\"');\n if (end == NULL) break;\n int len = end - (start + 1);\n strncpy(values[index], start + 1, len);\n values[index][len] = '\\0';\n index++;\n text = end + 1;\n }\n *count = index;\n}", + "test": "int main() {\n\n char values[10][50];\n\n int count, i;\n\n\n\n func0(\"\\\"Python\\\", \\\"PHP\\\", \\\"Java\\\"\", values, &count);\n\n assert(count == 3);\n\n assert(strcmp(values[0], \"Python\") == 0);\n\n assert(strcmp(values[1], \"PHP\") == 0);\n\n assert(strcmp(values[2], \"Java\") == 0);\n\n\n\n func0(\"\\\"python\\\",\\\"program\\\",\\\"language\\\"\", values, &count);\n\n assert(count == 3);\n\n assert(strcmp(values[0], \"python\") == 0);\n\n assert(strcmp(values[1], \"program\") == 0);\n\n assert(strcmp(values[2], \"language\") == 0);\n\n\n\n func0(\"\\\"red\\\",\\\"blue\\\",\\\"green\\\",\\\"yellow\\\"\", values, &count);\n\n assert(count == 4);\n\n assert(strcmp(values[0], \"red\") == 0);\n\n assert(strcmp(values[1], \"blue\") == 0);\n\n assert(strcmp(values[2], \"green\") == 0);\n\n assert(strcmp(values[3], \"yellow\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\nmov %rdx,%r13\npush %r12\nxor %r12d,%r12d\npush %rbp\npush %rbx\nmov %rsi,%rbx\nsub $0x8,%rsp\nmovl $0x0,(%rdx)\njmp 152a \nnopl 0x0(%rax,%rax,1)\nlea 0x1(%rax),%rbp\nmov $0x22,%esi\nmov %rbp,%rdi\ncallq 10a0 \nmov %rax,%r14\ntest %rax,%rax\nje 1539 \nmov %rax,%r15\nmov %rbx,%rdi\nmov %rbp,%rsi\nadd $0x1,%r12d\nsub %rbp,%r15\nadd $0x32,%rbx\nmovslq %r15d,%r15\nmov %r15,%rdx\ncallq 1080 \nmovb $0x0,-0x32(%rbx,%r15,1)\nlea 0x1(%r14),%rdi\nmov $0x22,%esi\ncallq 10a0 \ntest %rax,%rax\njne 14e8 \nmov %r12d,0x0(%r13)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\nmov r13, rdx\npush r12\nxor r12d, r12d\npush rbp\nmov rbp, rsi\npush rbx\nsub rsp, 8\nmov dword ptr [rdx], 0\njmp short loc_150A\nloc_14C8:\nlea rbx, [rax+1]\nmov esi, 22h ; '\"'; c\nmov rdi, rbx; s\ncall _strchr\nmov r14, rax\ntest rax, rax\njz short loc_1519\nmov r15, rax\nmov rdi, rbp; dest\nmov rsi, rbx; src\nadd r12d, 1\nsub r15, rbx\nadd rbp, 32h ; '2'\nmovsxd r15, r15d\nmov rdx, r15; n\ncall _strncpy\nmov byte ptr [rbp+r15-32h], 0\nlea rdi, [r14+1]; s\nloc_150A:\nmov esi, 22h ; '\"'; c\ncall _strchr\ntest rax, rax\njnz short loc_14C8\nloc_1519:\nmov [r13+0], r12d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "char *__fastcall func0(const char *a1, char *a2, _DWORD *a3)\n{\n int v4; // r12d\n const char *v6; // rbx\n char *result; // rax\n char *v8; // r14\n char *v9; // rdi\n size_t v10; // r15\n\n v4 = 0;\n *a3 = 0;\n while ( 1 )\n {\n result = strchr(a1, 34);\n if ( !result )\n break;\n v6 = result + 1;\n result = strchr(result + 1, 34);\n v8 = result;\n if ( !result )\n break;\n v9 = a2;\n ++v4;\n a2 += 50;\n v10 = (int)result - (int)v6;\n strncpy(v9, v6, v10);\n a2[v10 - 50] = 0;\n a1 = v8 + 1;\n }\n *a3 = v4;\n return result;\n}", + "ida_strip_asm": "sub_14A0:\nendbr64\npush r15\npush r14\npush r13\nmov r13, rdx\npush r12\nxor r12d, r12d\npush rbp\nmov rbp, rsi\npush rbx\nsub rsp, 8\nmov dword ptr [rdx], 0\njmp short loc_150A\nloc_14C8:\nlea rbx, [rax+1]\nmov esi, 22h ; '\"'; c\nmov rdi, rbx; s\ncall _strchr\nmov r14, rax\ntest rax, rax\njz short loc_1519\nmov r15, rax\nmov rdi, rbp; dest\nmov rsi, rbx; src\nadd r12d, 1\nsub r15, rbx\nadd rbp, 32h ; '2'\nmovsxd r15, r15d\nmov rdx, r15; n\ncall _strncpy\nmov byte ptr [rbp+r15-32h], 0\nlea rdi, [r14+1]; s\nloc_150A:\nmov esi, 22h ; '\"'; c\ncall _strchr\ntest rax, rax\njnz short loc_14C8\nloc_1519:\nmov [r13+0], r12d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "char *__fastcall sub_14A0(const char *a1, char *a2, _DWORD *a3)\n{\n int v4; // r12d\n const char *v6; // rbx\n char *result; // rax\n char *v8; // r14\n char *v9; // rdi\n size_t v10; // r15\n\n v4 = 0;\n *a3 = 0;\n while ( 1 )\n {\n result = strchr(a1, 34);\n if ( !result )\n break;\n v6 = result + 1;\n result = strchr(result + 1, 34);\n v8 = result;\n if ( !result )\n break;\n v9 = a2;\n ++v4;\n a2 += 50;\n v10 = (int)result - (int)v6;\n strncpy(v9, v6, v10);\n a2[v10 - 50] = 0;\n a1 = v8 + 1;\n }\n *a3 = v4;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_14A0(const char *a1, char *a2, uint32_t *a3) {\n int v4;\n const char *v6;\n char *result;\n char *v8;\n char *v9;\n unsigned int v10;\n v4 = 0;\n *a3 = 0;\n while (1) {\n result = strchr(a1, 34);\n if (!result) break;\n v6 = result + 1;\n result = strchr(result + 1, 34);\n v8 = result;\n if (!result) break;\n v9 = a2;\n ++v4;\n a2 += 50;\n v10 = (int)result - (int)v6;\n strncpy(v9, v6, v10);\n a2[v10 - 50] = 0;\n a1 = v8 + 1;\n }\n *a3 = v4;\n return result;\n}", + "ida_pseudo_norm": "char *func0(const char *a1, char *a2, uint32_t *a3) {\n int v4;\n const char *v6;\n char *result;\n char *v8;\n char *v9;\n unsigned int v10;\n v4 = 0;\n *a3 = 0;\n while (1) {\n result = strchr(a1, 34);\n if (!result) break;\n v6 = result + 1;\n result = strchr(result + 1, 34);\n v8 = result;\n if (!result) break;\n v9 = a2;\n ++v4;\n a2 += 50;\n v10 = (int)result - (int)v6;\n strncpy(v9, v6, v10);\n a2[v10 - 50] = 0;\n a1 = v8 + 1;\n }\n *a3 = v4;\n return result;\n}" + }, + { + "index": 564, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int cnt = 0;\n for (int i = 0; i < n; i++) {\n for (int j = i + 1; j < n; j++) {\n if (arr[i] != arr[j]) {\n cnt++;\n }\n }\n }\n return cnt;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 1};\n\n int arr2[] = {1, 1, 1, 1};\n\n int arr3[] = {1, 2, 3, 4, 5};\n\n \n\n assert(func0(arr1, 3) == 2);\n\n assert(func0(arr2, 4) == 0);\n\n assert(func0(arr3, 5) == 10);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11d7 \nmov -0x8(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x4(%rbp)\njmp 11cb \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\nje 11c7 \naddl $0x1,-0xc(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1193 \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1188 \nmov -0xc(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_11D7\nloc_1188:\nmov eax, [rbp+var_8]\nadd eax, 1\nmov [rbp+var_4], eax\njmp short loc_11CB\nloc_1193:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_11C7\nadd [rbp+var_C], 1\nloc_11C7:\nadd [rbp+var_4], 1\nloc_11CB:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1193\nadd [rbp+var_8], 1\nloc_11D7:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+10h] [rbp-Ch]\n int i; // [rsp+14h] [rbp-8h]\n int j; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a1) != *(_DWORD *)(4LL * j + a1) )\n ++v3;\n }\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_11D7\nloc_1188:\nmov eax, [rbp+var_8]\nadd eax, 1\nmov [rbp+var_4], eax\njmp short loc_11CB\nloc_1193:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_11C7\nadd [rbp+var_C], 1\nloc_11C7:\nadd [rbp+var_4], 1\nloc_11CB:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1193\nadd [rbp+var_8], 1\nloc_11D7:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+10h] [rbp-Ch]\n int i; // [rsp+14h] [rbp-8h]\n int j; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a1) != *(_DWORD *)(4LL * j + a1) )\n ++v3;\n }\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n unsigned int v3;\n int i;\n int j;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if (*(uint32_t *)(4LL * i + a1) != *(uint32_t *)(4LL * j + a1)) ++v3;\n }\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n int j;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if (*(uint32_t *)(4LL * i + a1) != *(uint32_t *)(4LL * j + a1)) ++v3;\n }\n }\n return v3;\n}" + }, + { + "index": 564, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int cnt = 0;\n for (int i = 0; i < n; i++) {\n for (int j = i + 1; j < n; j++) {\n if (arr[i] != arr[j]) {\n cnt++;\n }\n }\n }\n return cnt;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 1};\n\n int arr2[] = {1, 1, 1, 1};\n\n int arr3[] = {1, 2, 3, 4, 5};\n\n \n\n assert(func0(arr1, 3) == 2);\n\n assert(func0(arr2, 4) == 0);\n\n assert(func0(arr3, 5) == 10);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11ab \nlea -0x1(%rsi),%r9d\nadd $0x1,%r9\nmov $0x1,%r8d\nmov $0x0,%edx\njmp 119c \nadd $0x1,%edx\nadd $0x1,%rax\ncmp %eax,%esi\njle 1198 \ncmp (%rdi,%rax,4),%ecx\njne 1186 \njmp 1189 \nadd $0x1,%r8\ncmp %r9,%r8\nje 11b0 \nmov -0x4(%rdi,%r8,4),%ecx\nmov %r8,%rax\njmp 1191 \nmov $0x0,%edx\nmov %edx,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11B1\nmov r9d, esi\nmovsxd r10, esi\nmov r8d, 1\nmov edx, 0\njmp short loc_11A2\nloc_1184:\nadd edx, 1\nloc_1187:\nadd rax, 1\ncmp esi, eax\njle short loc_1196\nloc_118F:\ncmp ecx, [rdi+rax*4]\njnz short loc_1184\njmp short loc_1187\nloc_1196:\nlea rax, [r8+1]\ncmp r8, r10\njz short loc_11B6\nmov r8, rax\nloc_11A2:\ncmp r8, r9\njz short loc_11B6\nmov ecx, [rdi+r8*4-4]\nmov rax, r8\njmp short loc_118F\nloc_11B1:\nmov edx, 0\nloc_11B6:\nmov eax, edx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // r8\n unsigned int v3; // edx\n __int64 v4; // rax\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = 1LL;\n v3 = 0;\n while ( v2 != a2 )\n {\n v4 = v2;\n do\n {\n if ( *(_DWORD *)(a1 + 4 * v2 - 4) != *(_DWORD *)(a1 + 4 * v4) )\n ++v3;\n ++v4;\n }\n while ( a2 > (int)v4 );\n if ( v2 == a2 )\n break;\n ++v2;\n }\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11B1\nmov r9d, esi\nmovsxd r10, esi\nmov r8d, 1\nmov edx, 0\njmp short loc_11A2\nloc_1184:\nadd edx, 1\nloc_1187:\nadd rax, 1\ncmp esi, eax\njle short loc_1196\nloc_118F:\ncmp ecx, [rdi+rax*4]\njnz short loc_1184\njmp short loc_1187\nloc_1196:\nlea rax, [r8+1]\ncmp r8, r10\njz short loc_11B6\nmov r8, rax\nloc_11A2:\ncmp r8, r9\njz short loc_11B6\nmov ecx, [rdi+r8*4-4]\nmov rax, r8\njmp short loc_118F\nloc_11B1:\nmov edx, 0\nloc_11B6:\nmov eax, edx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n __int64 v2; // r8\n unsigned int v3; // edx\n __int64 v4; // rax\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = 1LL;\n v3 = 0;\n while ( v2 != a2 )\n {\n v4 = v2;\n do\n {\n if ( *(_DWORD *)(a1 + 4 * v2 - 4) != *(_DWORD *)(a1 + 4 * v4) )\n ++v3;\n ++v4;\n }\n while ( a2 > (int)v4 );\n if ( v2 == a2 )\n break;\n ++v2;\n }\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n long long v4;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = 1LL;\n v3 = 0;\n while (v2 != a2) {\n v4 = v2;\n do {\n if (*(uint32_t *)(a1 + 4 * v2 - 4) != *(uint32_t *)(a1 + 4 * v4)) ++v3;\n ++v4;\n } while (a2 > (int)v4);\n if (v2 == a2) break;\n ++v2;\n }\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n long long v4;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = 1LL;\n v3 = 0;\n while (v2 != a2) {\n v4 = v2;\n do {\n if (*(uint32_t *)(a1 + 4 * v2 - 4) != *(uint32_t *)(a1 + 4 * v4)) ++v3;\n ++v4;\n } while (a2 > (int)v4);\n if (v2 == a2) break;\n ++v2;\n }\n }\n return v3;\n}" + }, + { + "index": 564, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int cnt = 0;\n for (int i = 0; i < n; i++) {\n for (int j = i + 1; j < n; j++) {\n if (arr[i] != arr[j]) {\n cnt++;\n }\n }\n }\n return cnt;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 1};\n\n int arr2[] = {1, 1, 1, 1};\n\n int arr3[] = {1, 2, 3, 4, 5};\n\n \n\n assert(func0(arr1, 3) == 2);\n\n assert(func0(arr2, 4) == 0);\n\n assert(func0(arr3, 5) == 10);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 136e \nlea -0x1(%rsi),%r9d\nmov $0x1,%ecx\nxor %r8d,%r8d\nadd $0x1,%r9\ncmp %r9,%rcx\nje 136a \nnopl (%rax)\nmov -0x4(%rdi,%rcx,4),%edx\nmov %rcx,%rax\nnopw 0x0(%rax,%rax,1)\ncmp (%rdi,%rax,4),%edx\nje 1359 \nadd $0x1,%r8d\nadd $0x1,%rax\ncmp %eax,%esi\njg 1350 \nadd $0x1,%rcx\ncmp %r9,%rcx\njne 1340 \nmov %r8d,%eax\nretq\nxor %r8d,%r8d\nmov %r8d,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_12BC\nmov r9d, esi\nmov r8d, 1\nxor edx, edx\ncmp esi, 1\njz short loc_12B9\nnop dword ptr [rax+rax+00000000h]\nloc_1290:\nmov ecx, [rdi+r8*4-4]\nmov rax, r8\nnop dword ptr [rax+rax+00000000h]\nloc_12A0:\ncmp ecx, [rdi+rax*4]\njz short loc_12A8\nadd edx, 1\nloc_12A8:\nadd rax, 1\ncmp esi, eax\njg short loc_12A0\nadd r8, 1\ncmp r8, r9\njnz short loc_1290\nloc_12B9:\nmov eax, edx\nretn\nloc_12BC:\nxor edx, edx\nmov eax, edx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // r8\n unsigned int v3; // edx\n __int64 v4; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 1LL;\n v3 = 0;\n if ( a2 != 1 )\n {\n do\n {\n v4 = v2;\n do\n {\n if ( *(_DWORD *)(a1 + 4 * v2 - 4) != *(_DWORD *)(a1 + 4 * v4) )\n ++v3;\n ++v4;\n }\n while ( a2 > (int)v4 );\n ++v2;\n }\n while ( v2 != a2 );\n }\n return v3;\n}", + "ida_strip_asm": "sub_1270:\nendbr64\ntest esi, esi\njle short loc_12BC\nmov r9d, esi\nmov r8d, 1\nxor edx, edx\ncmp esi, 1\njz short loc_12B9\nnop dword ptr [rax+rax+00000000h]\nloc_1290:\nmov ecx, [rdi+r8*4-4]\nmov rax, r8\nnop dword ptr [rax+rax+00000000h]\nloc_12A0:\ncmp ecx, [rdi+rax*4]\njz short loc_12A8\nadd edx, 1\nloc_12A8:\nadd rax, 1\ncmp esi, eax\njg short loc_12A0\nadd r8, 1\ncmp r8, r9\njnz short loc_1290\nloc_12B9:\nmov eax, edx\nretn\nloc_12BC:\nxor edx, edx\nmov eax, edx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1270(__int64 a1, int a2)\n{\n __int64 v2; // r8\n unsigned int v3; // edx\n __int64 v4; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 1LL;\n v3 = 0;\n if ( a2 != 1 )\n {\n do\n {\n v4 = v2;\n do\n {\n if ( *(_DWORD *)(a1 + 4 * v2 - 4) != *(_DWORD *)(a1 + 4 * v4) )\n ++v3;\n ++v4;\n }\n while ( a2 > (int)v4 );\n ++v2;\n }\n while ( v2 != a2 );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1270(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n long long v4;\n if (a2 <= 0) return 0LL;\n v2 = 1LL;\n v3 = 0;\n if (a2 != 1) {\n do {\n v4 = v2;\n do {\n if (*(uint32_t *)(a1 + 4 * v2 - 4) != *(uint32_t *)(a1 + 4 * v4)) ++v3;\n ++v4;\n } while (a2 > (int)v4);\n ++v2;\n } while (v2 != a2);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n long long v4;\n if (a2 <= 0) return 0LL;\n v2 = 1LL;\n v3 = 0;\n if (a2 != 1) {\n do {\n v4 = v2;\n do {\n if (*(uint32_t *)(a1 + 4 * v2 - 4) != *(uint32_t *)(a1 + 4 * v4)) ++v3;\n ++v4;\n } while (a2 > (int)v4);\n ++v2;\n } while (v2 != a2);\n }\n return v3;\n}" + }, + { + "index": 565, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* word, char* result) {\n int length = strlen(word);\n for (int i = 0; i < length; i++) {\n result[i] = word[i];\n }\n result[length] = '\\0';\n return result;\n}", + "test": "int main() {\n\n char result[100];\n\n assert(strcmp(func0(\"python\", result), \"python\") == 0);\n\n assert(strcmp(func0(\"Name\", result), \"Name\") == 0);\n\n assert(strcmp(func0(\"program\", result), \"program\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov -0x18(%rbp),%rax\nmov %rax,%rdi\ncallq 1080 \nmov %eax,-0x4(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11f8 \nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0x8(%rbp),%edx\nmovslq %edx,%rcx\nmov -0x20(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rax),%eax\nmov %al,(%rdx)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x4(%rbp),%eax\njl 11d5 \nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmovb $0x0,(%rax)\nmov -0x20(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov [rbp+var_20], rsi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_8], 0\njmp short loc_11F8\nloc_11D5:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmov edx, [rbp+var_8]\nmovsxd rcx, edx\nmov rdx, [rbp+var_20]\nadd rdx, rcx\nmovzx eax, byte ptr [rax]\nmov [rdx], al\nadd [rbp+var_8], 1\nloc_11F8:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njl short loc_11D5\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+var_20]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, __int64 a2)\n{\n int i; // [rsp+18h] [rbp-8h]\n int v4; // [rsp+1Ch] [rbp-4h]\n\n v4 = strlen(a1);\n for ( i = 0; i < v4; ++i )\n *(_BYTE *)(i + a2) = a1[i];\n *(_BYTE *)(v4 + a2) = 0;\n return a2;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov [rbp+var_20], rsi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_8], 0\njmp short loc_11F8\nloc_11D5:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmov edx, [rbp+var_8]\nmovsxd rcx, edx\nmov rdx, [rbp+var_20]\nadd rdx, rcx\nmovzx eax, byte ptr [rax]\nmov [rdx], al\nadd [rbp+var_8], 1\nloc_11F8:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njl short loc_11D5\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+var_20]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(const char *a1, __int64 a2)\n{\n int i; // [rsp+18h] [rbp-8h]\n int v4; // [rsp+1Ch] [rbp-4h]\n\n v4 = strlen(a1);\n for ( i = 0; i < v4; ++i )\n *(_BYTE *)(i + a2) = a1[i];\n *(_BYTE *)(v4 + a2) = 0;\n return a2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(const char *a1, long long a2) {\n int i;\n int v4;\n v4 = strlen(a1);\n for (i = 0; i < v4; ++i) *(uint8_t *)(i + a2) = a1[i];\n *(uint8_t *)(v4 + a2) = 0;\n return a2;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, long long a2) {\n int i;\n int v4;\n v4 = strlen(a1);\n for (i = 0; i < v4; ++i) *(uint8_t *)(i + a2) = a1[i];\n *(uint8_t *)(v4 + a2) = 0;\n return a2;\n}" + }, + { + "index": 565, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* word, char* result) {\n int length = strlen(word);\n for (int i = 0; i < length; i++) {\n result[i] = word[i];\n }\n result[length] = '\\0';\n return result;\n}", + "test": "int main() {\n\n char result[100];\n\n assert(strcmp(func0(\"python\", result), \"python\") == 0);\n\n assert(strcmp(func0(\"Name\", result), \"Name\") == 0);\n\n assert(strcmp(func0(\"program\", result), \"program\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%r8\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nsub $0x1,%rcx\ntest %ecx,%ecx\njle 11a5 \nlea -0x1(%rcx),%edi\nmov $0x0,%eax\nmovzbl (%r8,%rax,1),%edx\nmov %dl,(%rsi,%rax,1)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rdi,%rdx\njne 1191 \nmovslq %ecx,%rcx\nmovb $0x0,(%rsi,%rcx,1)\nmov %rsi,%rax\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov rbx, rsi\ncall _strlen\ntest eax, eax\njle short loc_11DE\nlea esi, [rax-1]\nmov edx, 0\nloc_11CA:\nmovzx ecx, byte ptr [rbp+rdx+0]\nmov [rbx+rdx], cl\nmov rcx, rdx\nadd rdx, 1\ncmp rcx, rsi\njnz short loc_11CA\nloc_11DE:\ncdqe\nmov byte ptr [rbx+rax], 0\nmov rax, rbx\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, __int64 a2)\n{\n int v2; // eax\n __int64 v3; // rdx\n __int64 v4; // rcx\n\n v2 = strlen(a1);\n if ( v2 > 0 )\n {\n v3 = 0LL;\n do\n {\n *(_BYTE *)(a2 + v3) = a1[v3];\n v4 = v3++;\n }\n while ( v4 != v2 - 1 );\n }\n *(_BYTE *)(a2 + v2) = 0;\n return a2;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov rbx, rsi\ncall _strlen\ntest eax, eax\njle short loc_11DE\nlea esi, [rax-1]\nmov edx, 0\nloc_11CA:\nmovzx ecx, byte ptr [rbp+rdx+0]\nmov [rbx+rdx], cl\nmov rcx, rdx\nadd rdx, 1\ncmp rcx, rsi\njnz short loc_11CA\nloc_11DE:\ncdqe\nmov byte ptr [rbx+rax], 0\nmov rax, rbx\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(const char *a1, __int64 a2)\n{\n int v2; // eax\n __int64 v3; // rdx\n __int64 v4; // rcx\n\n v2 = strlen(a1);\n if ( v2 > 0 )\n {\n v3 = 0LL;\n do\n {\n *(_BYTE *)(a2 + v3) = a1[v3];\n v4 = v3++;\n }\n while ( v4 != v2 - 1 );\n }\n *(_BYTE *)(a2 + v2) = 0;\n return a2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(const char *a1, long long a2) {\n int v2;\n long long v3;\n long long v4;\n v2 = strlen(a1);\n if (v2 > 0) {\n v3 = 0LL;\n do {\n *(uint8_t *)(a2 + v3) = a1[v3];\n v4 = v3++;\n } while (v4 != v2 - 1);\n }\n *(uint8_t *)(a2 + v2) = 0;\n return a2;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, long long a2) {\n int v2;\n long long v3;\n long long v4;\n v2 = strlen(a1);\n if (v2 > 0) {\n v3 = 0LL;\n do {\n *(uint8_t *)(a2 + v3) = a1[v3];\n v4 = v3++;\n } while (v4 != v2 - 1);\n }\n *(uint8_t *)(a2 + v2) = 0;\n return a2;\n}" + }, + { + "index": 565, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* word, char* result) {\n int length = strlen(word);\n for (int i = 0; i < length; i++) {\n result[i] = word[i];\n }\n result[length] = '\\0';\n return result;\n}", + "test": "int main() {\n\n char result[100];\n\n assert(strcmp(func0(\"python\", result), \"python\") == 0);\n\n assert(strcmp(func0(\"Name\", result), \"Name\") == 0);\n\n assert(strcmp(func0(\"program\", result), \"program\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %rsi,%r12\npush %rbx\nmov %rdi,%rbx\nsub $0x8,%rsp\ncallq 1070 \ntest %eax,%eax\njle 12e4 \nlea -0x1(%rax),%esi\nxor %edx,%edx\nmovzbl (%rbx,%rdx,1),%ecx\nmov %cl,(%r12,%rdx,1)\nmov %rdx,%rcx\nadd $0x1,%rdx\ncmp %rcx,%rsi\njne 12d0 \ncltq\nmovb $0x0,(%r12,%rax,1)\nadd $0x8,%rsp\nmov %r12,%rax\npop %rbx\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rdi\npush rbx\nmov rbx, rsi\nsub rsp, 8\ncall _strlen\ntest eax, eax\njle short loc_12E4\nlea esi, [rax-1]\nxor edx, edx\nxchg ax, ax\nloc_12D0:\nmovzx ecx, byte ptr [rbp+rdx+0]\nmov [rbx+rdx], cl\nmov rcx, rdx\nadd rdx, 1\ncmp rcx, rsi\njnz short loc_12D0\nloc_12E4:\ncdqe\nmov byte ptr [rbx+rax], 0\nadd rsp, 8\nmov rax, rbx\npop rbx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, __int64 a2)\n{\n int v2; // eax\n __int64 v3; // rdx\n __int64 v4; // rcx\n\n v2 = strlen(a1);\n if ( v2 > 0 )\n {\n v3 = 0LL;\n do\n {\n *(_BYTE *)(a2 + v3) = a1[v3];\n v4 = v3++;\n }\n while ( v4 != v2 - 1 );\n }\n *(_BYTE *)(a2 + v2) = 0;\n return a2;\n}", + "ida_strip_asm": "sub_12B0:\nendbr64\npush rbp\nmov rbp, rdi\npush rbx\nmov rbx, rsi\nsub rsp, 8\ncall _strlen\ntest eax, eax\njle short loc_12E4\nlea esi, [rax-1]\nxor edx, edx\nxchg ax, ax\nloc_12D0:\nmovzx ecx, byte ptr [rbp+rdx+0]\nmov [rbx+rdx], cl\nmov rcx, rdx\nadd rdx, 1\ncmp rcx, rsi\njnz short loc_12D0\nloc_12E4:\ncdqe\nmov byte ptr [rbx+rax], 0\nadd rsp, 8\nmov rax, rbx\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12B0(const char *a1, __int64 a2)\n{\n int v2; // eax\n __int64 v3; // rdx\n __int64 v4; // rcx\n\n v2 = strlen(a1);\n if ( v2 > 0 )\n {\n v3 = 0LL;\n do\n {\n *(_BYTE *)(a2 + v3) = a1[v3];\n v4 = v3++;\n }\n while ( v4 != v2 - 1 );\n }\n *(_BYTE *)(a2 + v2) = 0;\n return a2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12B0(const char *a1, long long a2) {\n int v2;\n long long v3;\n long long v4;\n v2 = strlen(a1);\n if (v2 > 0) {\n v3 = 0LL;\n do {\n *(uint8_t *)(a2 + v3) = a1[v3];\n v4 = v3++;\n } while (v4 != v2 - 1);\n }\n *(uint8_t *)(a2 + v2) = 0;\n return a2;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, long long a2) {\n int v2;\n long long v3;\n long long v4;\n v2 = strlen(a1);\n if (v2 > 0) {\n v3 = 0LL;\n do {\n *(uint8_t *)(a2 + v3) = a1[v3];\n v4 = v3++;\n } while (v4 != v2 - 1);\n }\n *(uint8_t *)(a2 + v2) = 0;\n return a2;\n}" + }, + { + "index": 565, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* word, char* result) {\n int length = strlen(word);\n for (int i = 0; i < length; i++) {\n result[i] = word[i];\n }\n result[length] = '\\0';\n return result;\n}", + "test": "int main() {\n\n char result[100];\n\n assert(strcmp(func0(\"python\", result), \"python\") == 0);\n\n assert(strcmp(func0(\"Name\", result), \"Name\") == 0);\n\n assert(strcmp(func0(\"program\", result), \"program\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %rsi,%r12\npush %rbx\nmov %rdi,%rbx\nsub $0x8,%rsp\ncallq 1070 \ntest %eax,%eax\njle 1443 \nlea 0xf(%rbx),%rcx\nlea -0x1(%rax),%edx\nsub %r12,%rcx\ncmp $0x1e,%rcx\njbe 1458 \ncmp $0xe,%edx\njbe 1458 \nmov %eax,%ecx\nxor %edx,%edx\nshr $0x4,%ecx\nshl $0x4,%rcx\nnopw %cs:0x0(%rax,%rax,1)\nmovdqu (%rbx,%rdx,1),%xmm0\nmovups %xmm0,(%r12,%rdx,1)\nadd $0x10,%rdx\ncmp %rcx,%rdx\njne 1300 \nmov %eax,%edx\nand $0xfffffff0,%edx\ntest $0xf,%al\nje 1443 \nmovslq %edx,%rcx\nmovzbl (%rbx,%rcx,1),%esi\nmov %sil,(%r12,%rcx,1)\nlea 0x1(%rdx),%ecx\ncmp %ecx,%eax\njle 1443 \nmovslq %ecx,%rcx\nmovzbl (%rbx,%rcx,1),%esi\nmov %sil,(%r12,%rcx,1)\nlea 0x2(%rdx),%ecx\ncmp %ecx,%eax\njle 1443 \nmovslq %ecx,%rcx\nmovzbl (%rbx,%rcx,1),%esi\nmov %sil,(%r12,%rcx,1)\nlea 0x3(%rdx),%ecx\ncmp %ecx,%eax\njle 1443 \nmovslq %ecx,%rcx\nmovzbl (%rbx,%rcx,1),%esi\nmov %sil,(%r12,%rcx,1)\nlea 0x4(%rdx),%ecx\ncmp %ecx,%eax\njle 1443 \nmovslq %ecx,%rcx\nmovzbl (%rbx,%rcx,1),%esi\nmov %sil,(%r12,%rcx,1)\nlea 0x5(%rdx),%ecx\ncmp %ecx,%eax\njle 1443 \nmovslq %ecx,%rcx\nmovzbl (%rbx,%rcx,1),%esi\nmov %sil,(%r12,%rcx,1)\nlea 0x6(%rdx),%ecx\ncmp %ecx,%eax\njle 1443 \nmovslq %ecx,%rcx\nmovzbl (%rbx,%rcx,1),%esi\nmov %sil,(%r12,%rcx,1)\nlea 0x7(%rdx),%ecx\ncmp %ecx,%eax\njle 1443 \nmovslq %ecx,%rcx\nmovzbl (%rbx,%rcx,1),%esi\nmov %sil,(%r12,%rcx,1)\nlea 0x8(%rdx),%ecx\ncmp %ecx,%eax\njle 1443 \nmovslq %ecx,%rcx\nmovzbl (%rbx,%rcx,1),%esi\nmov %sil,(%r12,%rcx,1)\nlea 0x9(%rdx),%ecx\ncmp %ecx,%eax\njle 1443 \nmovslq %ecx,%rcx\nmovzbl (%rbx,%rcx,1),%esi\nmov %sil,(%r12,%rcx,1)\nlea 0xa(%rdx),%ecx\ncmp %ecx,%eax\njle 1443 \nmovslq %ecx,%rcx\nmovzbl (%rbx,%rcx,1),%esi\nmov %sil,(%r12,%rcx,1)\nlea 0xb(%rdx),%ecx\ncmp %ecx,%eax\njle 1443 \nmovslq %ecx,%rcx\nmovzbl (%rbx,%rcx,1),%esi\nmov %sil,(%r12,%rcx,1)\nlea 0xc(%rdx),%ecx\ncmp %ecx,%eax\njle 1443 \nmovslq %ecx,%rcx\nmovzbl (%rbx,%rcx,1),%esi\nmov %sil,(%r12,%rcx,1)\nlea 0xd(%rdx),%ecx\ncmp %ecx,%eax\njle 1443 \nmovslq %ecx,%rcx\nadd $0xe,%edx\nmovzbl (%rbx,%rcx,1),%esi\nmov %sil,(%r12,%rcx,1)\ncmp %edx,%eax\njle 1443 \nmovslq %edx,%rdx\nmovzbl (%rbx,%rdx,1),%ecx\nmov %cl,(%r12,%rdx,1)\ncltq\nmovb $0x0,(%r12,%rax,1)\nadd $0x8,%rsp\nmov %r12,%rax\npop %rbx\npop %r12\nretq\nnopl (%rax)\nmov %edx,%ecx\nxor %edx,%edx\nnopl 0x0(%rax)\nmovzbl (%rbx,%rdx,1),%esi\nmov %sil,(%r12,%rdx,1)\nmov %rdx,%rsi\nadd $0x1,%rdx\ncmp %rcx,%rsi\njne 1460 \njmp 1443 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rdi\npush rbx\nmov rbx, rsi\nsub rsp, 8\ncall _strlen\nmov rdx, rax\ntest eax, eax\njle short loc_1304\nlea esi, [rax-1]\nmov edi, eax\ncmp esi, 6\njbe short loc_12E6\nlea rcx, [rbp+1]\nmov rax, rbx\nsub rax, rcx\ncmp rax, 0Eh\nja short loc_1318\nloc_12E6:\nxor eax, eax\nnop dword ptr [rax+rax+00000000h]\nloc_12F0:\nmovzx ecx, byte ptr [rbp+rax+0]\nmov [rbx+rax], cl\nmov rcx, rax\nadd rax, 1\ncmp rcx, rsi\njnz short loc_12F0\nloc_1304:\nmovsxd rdx, edx\nmov rax, rbx\nmov byte ptr [rbx+rdx], 0\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1318:\ncmp esi, 0Eh\njbe loc_1405\nmov ecx, edx\nxor eax, eax\nshr ecx, 4\nshl rcx, 4\nnop dword ptr [rax+00h]\nloc_1330:\nmovdqu xmm0, xmmword ptr [rbp+rax+0]\nmovups xmmword ptr [rbx+rax], xmm0\nadd rax, 10h\ncmp rax, rcx\njnz short loc_1330\nmov ecx, edx\nand ecx, 0FFFFFFF0h\nmov eax, ecx\ntest dl, 0Fh\njz short loc_1304\nmov edi, edx\nsub edi, ecx\nlea esi, [rdi-1]\ncmp esi, 6\njbe short loc_1370\nloc_135B:\nmov rsi, [rbp+rcx+0]\nmov [rbx+rcx], rsi\nmov ecx, edi\nand ecx, 0FFFFFFF8h\nadd eax, ecx\nand edi, 7\njz short loc_1304\nloc_1370:\nmovsxd rcx, eax\nmovzx esi, byte ptr [rbp+rcx+0]\nmov [rbx+rcx], sil\nlea ecx, [rax+1]\ncmp edx, ecx\njle short loc_1304\nmovsxd rcx, ecx\nmovzx esi, byte ptr [rbp+rcx+0]\nmov [rbx+rcx], sil\nlea ecx, [rax+2]\ncmp edx, ecx\njle loc_1304\nmovsxd rcx, ecx\nmovzx esi, byte ptr [rbp+rcx+0]\nmov [rbx+rcx], sil\nlea ecx, [rax+3]\ncmp edx, ecx\njle loc_1304\nmovsxd rcx, ecx\nmovzx esi, byte ptr [rbp+rcx+0]\nmov [rbx+rcx], sil\nlea ecx, [rax+4]\ncmp edx, ecx\njle loc_1304\nmovsxd rcx, ecx\nmovzx esi, byte ptr [rbp+rcx+0]\nmov [rbx+rcx], sil\nlea ecx, [rax+5]\ncmp edx, ecx\njle loc_1304\nmovsxd rcx, ecx\nadd eax, 6\nmovzx esi, byte ptr [rbp+rcx+0]\nmov [rbx+rcx], sil\ncmp edx, eax\njle loc_1304\ncdqe\nmovzx ecx, byte ptr [rbp+rax+0]\nmov [rbx+rax], cl\njmp loc_1304\nloc_1405:\nxor ecx, ecx\nxor eax, eax\njmp loc_135B", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, __int64 a2)\n{\n int v4; // eax\n int v5; // edx\n __int64 v6; // rsi\n int v7; // edi\n __int64 v8; // rax\n __int64 v9; // rcx\n __int64 result; // rax\n __int64 v11; // rax\n __int64 v12; // rcx\n signed int v13; // eax\n int v14; // ecx\n int v15; // eax\n\n v4 = strlen(a1);\n v5 = v4;\n if ( v4 <= 0 )\n goto LABEL_6;\n v6 = (unsigned int)(v4 - 1);\n v7 = v4;\n if ( (unsigned int)v6 <= 6 || (unsigned __int64)(a2 - (_QWORD)(a1 + 1)) <= 0xE )\n {\n v8 = 0LL;\n do\n {\n *(_BYTE *)(a2 + v8) = a1[v8];\n v9 = v8++;\n }\n while ( v9 != v6 );\n goto LABEL_6;\n }\n if ( (unsigned int)v6 <= 0xE )\n {\n v12 = 0LL;\n v13 = 0;\n }\n else\n {\n v11 = 0LL;\n do\n {\n *(__m128i *)(a2 + v11) = _mm_loadu_si128((const __m128i *)&a1[v11]);\n v11 += 16LL;\n }\n while ( v11 != 16LL * ((unsigned int)v5 >> 4) );\n v12 = v5 & 0xFFFFFFF0;\n v13 = v5 & 0xFFFFFFF0;\n if ( (v5 & 0xF) == 0 )\n goto LABEL_6;\n v7 = v5 - v12;\n if ( (unsigned int)(v5 - v12 - 1) <= 6 )\n goto LABEL_13;\n }\n *(_QWORD *)(a2 + v12) = *(_QWORD *)&a1[v12];\n v13 += v7 & 0xFFFFFFF8;\n if ( (v7 & 7) == 0 )\n goto LABEL_6;\nLABEL_13:\n *(_BYTE *)(a2 + v13) = a1[v13];\n if ( v5 > v13 + 1 )\n {\n *(_BYTE *)(a2 + v13 + 1) = a1[v13 + 1];\n if ( v5 > v13 + 2 )\n {\n *(_BYTE *)(a2 + v13 + 2) = a1[v13 + 2];\n if ( v5 > v13 + 3 )\n {\n *(_BYTE *)(a2 + v13 + 3) = a1[v13 + 3];\n if ( v5 > v13 + 4 )\n {\n *(_BYTE *)(a2 + v13 + 4) = a1[v13 + 4];\n v14 = v13 + 5;\n if ( v5 > v13 + 5 )\n {\n v15 = v13 + 6;\n *(_BYTE *)(a2 + v14) = a1[v14];\n if ( v5 > v15 )\n *(_BYTE *)(a2 + v15) = a1[v15];\n }\n }\n }\n }\n }\nLABEL_6:\n result = a2;\n *(_BYTE *)(a2 + v5) = 0;\n return result;\n}", + "ida_strip_asm": "sub_12B0:\nendbr64\npush rbp\nmov rbp, rdi\npush rbx\nmov rbx, rsi\nsub rsp, 8\ncall _strlen\nmov rdx, rax\ntest eax, eax\njle short loc_1304\nlea esi, [rax-1]\nmov edi, eax\ncmp esi, 6\njbe short loc_12E6\nlea rcx, [rbp+1]\nmov rax, rbx\nsub rax, rcx\ncmp rax, 0Eh\nja short loc_1318\nloc_12E6:\nxor eax, eax\nnop dword ptr [rax+rax+00000000h]\nloc_12F0:\nmovzx ecx, byte ptr [rbp+rax+0]\nmov [rbx+rax], cl\nmov rcx, rax\nadd rax, 1\ncmp rcx, rsi\njnz short loc_12F0\nloc_1304:\nmovsxd rdx, edx\nmov rax, rbx\nmov byte ptr [rbx+rdx], 0\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1318:\ncmp esi, 0Eh\njbe loc_1405\nmov ecx, edx\nxor eax, eax\nshr ecx, 4\nshl rcx, 4\nnop dword ptr [rax+00h]\nloc_1330:\nmovdqu xmm0, xmmword ptr [rbp+rax+0]\nmovups xmmword ptr [rbx+rax], xmm0\nadd rax, 10h\ncmp rax, rcx\njnz short loc_1330\nmov ecx, edx\nand ecx, 0FFFFFFF0h\nmov eax, ecx\ntest dl, 0Fh\njz short loc_1304\nmov edi, edx\nsub edi, ecx\nlea esi, [rdi-1]\ncmp esi, 6\njbe short loc_1370\nloc_135B:\nmov rsi, [rbp+rcx+0]\nmov [rbx+rcx], rsi\nmov ecx, edi\nand ecx, 0FFFFFFF8h\nadd eax, ecx\nand edi, 7\njz short loc_1304\nloc_1370:\nmovsxd rcx, eax\nmovzx esi, byte ptr [rbp+rcx+0]\nmov [rbx+rcx], sil\nlea ecx, [rax+1]\ncmp edx, ecx\njle short loc_1304\nmovsxd rcx, ecx\nmovzx esi, byte ptr [rbp+rcx+0]\nmov [rbx+rcx], sil\nlea ecx, [rax+2]\ncmp edx, ecx\njle loc_1304\nmovsxd rcx, ecx\nmovzx esi, byte ptr [rbp+rcx+0]\nmov [rbx+rcx], sil\nlea ecx, [rax+3]\ncmp edx, ecx\njle loc_1304\nmovsxd rcx, ecx\nmovzx esi, byte ptr [rbp+rcx+0]\nmov [rbx+rcx], sil\nlea ecx, [rax+4]\ncmp edx, ecx\njle loc_1304\nmovsxd rcx, ecx\nmovzx esi, byte ptr [rbp+rcx+0]\nmov [rbx+rcx], sil\nlea ecx, [rax+5]\ncmp edx, ecx\njle loc_1304\nmovsxd rcx, ecx\nadd eax, 6\nmovzx esi, byte ptr [rbp+rcx+0]\nmov [rbx+rcx], sil\ncmp edx, eax\njle loc_1304\ncdqe\nmovzx ecx, byte ptr [rbp+rax+0]\nmov [rbx+rax], cl\njmp loc_1304\nloc_1405:\nxor ecx, ecx\nxor eax, eax\njmp loc_135B", + "ida_strip_pseudo": "__int64 __fastcall sub_12B0(const char *a1, __int64 a2)\n{\n int v4; // eax\n int v5; // edx\n __int64 v6; // rsi\n int v7; // edi\n __int64 v8; // rax\n __int64 v9; // rcx\n __int64 result; // rax\n __int64 v11; // rax\n __int64 v12; // rcx\n signed int v13; // eax\n int v14; // ecx\n int v15; // eax\n\n v4 = strlen(a1);\n v5 = v4;\n if ( v4 <= 0 )\n goto LABEL_6;\n v6 = (unsigned int)(v4 - 1);\n v7 = v4;\n if ( (unsigned int)v6 <= 6 || (unsigned __int64)(a2 - (_QWORD)(a1 + 1)) <= 0xE )\n {\n v8 = 0LL;\n do\n {\n *(_BYTE *)(a2 + v8) = a1[v8];\n v9 = v8++;\n }\n while ( v9 != v6 );\n goto LABEL_6;\n }\n if ( (unsigned int)v6 <= 0xE )\n {\n v12 = 0LL;\n v13 = 0;\n }\n else\n {\n v11 = 0LL;\n do\n {\n *(__m128i *)(a2 + v11) = _mm_loadu_si128((const __m128i *)&a1[v11]);\n v11 += 16LL;\n }\n while ( v11 != 16LL * ((unsigned int)v5 >> 4) );\n v12 = v5 & 0xFFFFFFF0;\n v13 = v5 & 0xFFFFFFF0;\n if ( (v5 & 0xF) == 0 )\n goto LABEL_6;\n v7 = v5 - v12;\n if ( (unsigned int)(v5 - v12 - 1) <= 6 )\n goto LABEL_13;\n }\n *(_QWORD *)(a2 + v12) = *(_QWORD *)&a1[v12];\n v13 += v7 & 0xFFFFFFF8;\n if ( (v7 & 7) == 0 )\n goto LABEL_6;\nLABEL_13:\n *(_BYTE *)(a2 + v13) = a1[v13];\n if ( v5 > v13 + 1 )\n {\n *(_BYTE *)(a2 + v13 + 1) = a1[v13 + 1];\n if ( v5 > v13 + 2 )\n {\n *(_BYTE *)(a2 + v13 + 2) = a1[v13 + 2];\n if ( v5 > v13 + 3 )\n {\n *(_BYTE *)(a2 + v13 + 3) = a1[v13 + 3];\n if ( v5 > v13 + 4 )\n {\n *(_BYTE *)(a2 + v13 + 4) = a1[v13 + 4];\n v14 = v13 + 5;\n if ( v5 > v13 + 5 )\n {\n v15 = v13 + 6;\n *(_BYTE *)(a2 + v14) = a1[v14];\n if ( v5 > v15 )\n *(_BYTE *)(a2 + v15) = a1[v15];\n }\n }\n }\n }\n }\nLABEL_6:\n result = a2;\n *(_BYTE *)(a2 + v5) = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12B0(const char *a1, long long a2) {\n int v4;\n int v5;\n long long v6;\n int v7;\n long long v8;\n long long v9;\n long long result;\n long long v11;\n long long v12;\n signed int v13;\n int v14;\n int v15;\n v4 = strlen(a1);\n v5 = v4;\n if (v4 <= 0) goto LABEL_6;\n v6 = (unsigned int)(v4 - 1);\n v7 = v4;\n if ((unsigned int)v6 <= 6 ||\n (unsigned long long)(a2 - (uint64_t)(a1 + 1)) <= 14) {\n v8 = 0LL;\n do {\n *(uint8_t *)(a2 + v8) = a1[v8];\n v9 = v8++;\n } while (v9 != v6);\n goto LABEL_6;\n }\n if ((unsigned int)v6 <= 14) {\n v12 = 0LL;\n v13 = 0;\n } else {\n v11 = 0LL;\n do {\n *(__m128i *)(a2 + v11) = _mm_loadu_si128((const __m128i *)&a1[v11]);\n v11 += 16LL;\n } while (v11 != 16LL * ((unsigned int)v5 >> 4));\n v12 = v5 & 4294967280;\n v13 = v5 & 4294967280;\n if ((v5 & 15) == 0) goto LABEL_6;\n v7 = v5 - v12;\n if ((unsigned int)(v5 - v12 - 1) <= 6) goto LABEL_13;\n }\n *(uint64_t *)(a2 + v12) = *(uint64_t *)&a1[v12];\n v13 += v7 & 4294967288;\n if ((v7 & 7) == 0) goto LABEL_6;\nLABEL_13:\n *(uint8_t *)(a2 + v13) = a1[v13];\n if (v5 > v13 + 1) {\n *(uint8_t *)(a2 + v13 + 1) = a1[v13 + 1];\n if (v5 > v13 + 2) {\n *(uint8_t *)(a2 + v13 + 2) = a1[v13 + 2];\n if (v5 > v13 + 3) {\n *(uint8_t *)(a2 + v13 + 3) = a1[v13 + 3];\n if (v5 > v13 + 4) {\n *(uint8_t *)(a2 + v13 + 4) = a1[v13 + 4];\n v14 = v13 + 5;\n if (v5 > v13 + 5) {\n v15 = v13 + 6;\n *(uint8_t *)(a2 + v14) = a1[v14];\n if (v5 > v15) *(uint8_t *)(a2 + v15) = a1[v15];\n }\n }\n }\n }\n }\nLABEL_6:\n result = a2;\n *(uint8_t *)(a2 + v5) = 0;\n return result;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, long long a2) {\n int v4;\n int v5;\n long long v6;\n int v7;\n long long v8;\n long long v9;\n long long result;\n long long v11;\n long long v12;\n signed int v13;\n int v14;\n int v15;\n v4 = strlen(a1);\n v5 = v4;\n if (v4 <= 0) goto LABEL_6;\n v6 = (unsigned int)(v4 - 1);\n v7 = v4;\n if ((unsigned int)v6 <= 6 ||\n (unsigned long long)(a2 - (uint64_t)(a1 + 1)) <= 14) {\n v8 = 0LL;\n do {\n *(uint8_t *)(a2 + v8) = a1[v8];\n v9 = v8++;\n } while (v9 != v6);\n goto LABEL_6;\n }\n if ((unsigned int)v6 <= 14) {\n v12 = 0LL;\n v13 = 0;\n } else {\n v11 = 0LL;\n do {\n *(__m128i *)(a2 + v11) = _mm_loadu_si128((const __m128i *)&a1[v11]);\n v11 += 16LL;\n } while (v11 != 16LL * ((unsigned int)v5 >> 4));\n v12 = v5 & 4294967280;\n v13 = v5 & 4294967280;\n if ((v5 & 15) == 0) goto LABEL_6;\n v7 = v5 - v12;\n if ((unsigned int)(v5 - v12 - 1) <= 6) goto LABEL_13;\n }\n *(uint64_t *)(a2 + v12) = *(uint64_t *)&a1[v12];\n v13 += v7 & 4294967288;\n if ((v7 & 7) == 0) goto LABEL_6;\nLABEL_13:\n *(uint8_t *)(a2 + v13) = a1[v13];\n if (v5 > v13 + 1) {\n *(uint8_t *)(a2 + v13 + 1) = a1[v13 + 1];\n if (v5 > v13 + 2) {\n *(uint8_t *)(a2 + v13 + 2) = a1[v13 + 2];\n if (v5 > v13 + 3) {\n *(uint8_t *)(a2 + v13 + 3) = a1[v13 + 3];\n if (v5 > v13 + 4) {\n *(uint8_t *)(a2 + v13 + 4) = a1[v13 + 4];\n v14 = v13 + 5;\n if (v5 > v13 + 5) {\n v15 = v13 + 6;\n *(uint8_t *)(a2 + v14) = a1[v14];\n if (v5 > v15) *(uint8_t *)(a2 + v15) = a1[v15];\n }\n }\n }\n }\n }\nLABEL_6:\n result = a2;\n *(uint8_t *)(a2 + v5) = 0;\n return result;\n}" + }, + { + "index": 566, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n == 0)\n return 0;\n else\n return n % 10 + func0(n / 10);\n}", + "test": "int main() {\n\n assert(func0(345) == 12);\n\n assert(func0(12) == 3);\n\n assert(func0(97) == 16);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x18,%rsp\nmov %edi,-0x14(%rbp)\ncmpl $0x0,-0x14(%rbp)\njne 1166 \nmov $0x0,%eax\njmp 11b6 \nmov -0x14(%rbp),%edx\nmovslq %edx,%rax\nimul $0x66666667,%rax,%rax\nshr $0x20,%rax\nmov %eax,%ecx\nsar $0x2,%ecx\nmov %edx,%eax\nsar $0x1f,%eax\nsub %eax,%ecx\nmov %ecx,%ebx\nmov %ebx,%eax\nshl $0x2,%eax\nadd %ebx,%eax\nadd %eax,%eax\nmov %edx,%ebx\nsub %eax,%ebx\nmov -0x14(%rbp),%eax\nmovslq %eax,%rdx\nimul $0x66666667,%rdx,%rdx\nshr $0x20,%rdx\nsar $0x2,%edx\nsar $0x1f,%eax\nsub %eax,%edx\nmov %edx,%eax\nmov %eax,%edi\ncallq 1149 \nadd %ebx,%eax\nadd $0x18,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 18h\nmov [rbp+var_14], edi\ncmp [rbp+var_14], 0\njnz short loc_1166\nmov eax, 0\njmp short loc_11B6\nloc_1166:\nmov edx, [rbp+var_14]\nmovsxd rax, edx\nimul rax, 66666667h\nshr rax, 20h\nmov ecx, eax\nsar ecx, 2\nmov eax, edx\nsar eax, 1Fh\nmov ebx, ecx\nsub ebx, eax\nmov eax, ebx\nshl eax, 2\nadd eax, ebx\nadd eax, eax\nmov ebx, edx\nsub ebx, eax\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov edi, eax\ncall func0\nadd eax, ebx\nloc_11B6:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n if ( a1 )\n return a1 % 10 + (unsigned int)func0((unsigned int)(a1 / 10));\n else\n return 0LL;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 18h\nmov [rbp+var_14], edi\ncmp [rbp+var_14], 0\njnz short loc_1166\nmov eax, 0\njmp short loc_11B6\nloc_1166:\nmov edx, [rbp+var_14]\nmovsxd rax, edx\nimul rax, 66666667h\nshr rax, 20h\nmov ecx, eax\nsar ecx, 2\nmov eax, edx\nsar eax, 1Fh\nmov ebx, ecx\nsub ebx, eax\nmov eax, ebx\nshl eax, 2\nadd eax, ebx\nadd eax, eax\nmov ebx, edx\nsub ebx, eax\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov edi, eax\ncall sub_1149\nadd eax, ebx\nloc_11B6:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n if ( a1 )\n return a1 % 10 + (unsigned int)sub_1149((unsigned int)(a1 / 10));\n else\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n if (a1)\n return a1 % 10 + (unsigned int)sub_1149((unsigned int)(a1 / 10));\n else\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n if (a1)\n return a1 % 10 + (unsigned int)func0((unsigned int)(a1 / 10));\n else\n return 0LL;\n}" + }, + { + "index": 566, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n == 0)\n return 0;\n else\n return n % 10 + func0(n / 10);\n}", + "test": "int main() {\n\n assert(func0(345) == 12);\n\n assert(func0(12) == 3);\n\n assert(func0(97) == 16);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %edi,%ebx\ntest %edi,%edi\njne 1162 \nmov %ebx,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nmovslq %edi,%rbp\nimul $0x66666667,%rbp,%rbp\nsar $0x22,%rbp\nmov %edi,%eax\nsar $0x1f,%eax\nsub %eax,%ebp\nmov %ebp,%edi\ncallq 1149 \nmov %eax,%edx\nlea 0x0(%rbp,%rbp,4),%eax\nadd %eax,%eax\nsub %eax,%ebx\nadd %edx,%ebx\njmp 1159 \n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov ebx, edi\ntest edi, edi\njnz short loc_1162\nloc_1159:\nmov eax, ebx\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1162:\nmovsxd rbp, edi\nimul rbp, 66666667h\nsar rbp, 22h\nmov eax, edi\nsar eax, 1Fh\nsub ebp, eax\nmov edi, ebp\ncall func0\nmov edx, eax\nlea eax, [rbp+rbp*4+0]\nadd eax, eax\nsub ebx, eax\nadd ebx, edx\njmp short loc_1159", + "ida_pseudo": "__int64 __fastcall func0(signed int a1)\n{\n unsigned int v1; // ebx\n\n v1 = a1;\n if ( a1 )\n return (unsigned int)func0((unsigned int)(a1 / 10)) + a1 % 10;\n return v1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov ebx, edi\ntest edi, edi\njnz short loc_1162\nloc_1159:\nmov eax, ebx\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1162:\nmovsxd rbp, edi\nimul rbp, 66666667h\nsar rbp, 22h\nmov eax, edi\nsar eax, 1Fh\nsub ebp, eax\nmov edi, ebp\ncall sub_1149\nmov edx, eax\nlea eax, [rbp+rbp*4+0]\nadd eax, eax\nsub ebx, eax\nadd ebx, edx\njmp short loc_1159", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(signed int a1)\n{\n unsigned int v1; // ebx\n\n v1 = a1;\n if ( a1 )\n return (unsigned int)sub_1149((unsigned int)(a1 / 10)) + a1 % 10;\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(signed int a1) {\n unsigned int v1;\n v1 = a1;\n if (a1) return (unsigned int)sub_1149((unsigned int)(a1 / 10)) + a1 % 10;\n return v1;\n}", + "ida_pseudo_norm": "long long func0(signed int a1) {\n unsigned int v1;\n v1 = a1;\n if (a1) return (unsigned int)func0((unsigned int)(a1 / 10)) + a1 % 10;\n return v1;\n}" + }, + { + "index": 567, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int list1[], int size) {\n for (int i = 0; i < size - 1; i++) {\n if (list1[i] > list1[i + 1]) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n int list1[] = {1,2,4,6,8,10,12,14,16,17};\n\n int list2[] = {1, 2, 4, 6, 8, 10, 12, 14, 20, 17};\n\n int list3[] = {1, 2, 4, 6, 8, 10, 15, 14, 20};\n\n\n\n assert(func0(list1, 10) == true);\n\n assert(func0(list2, 10) == false);\n\n assert(func0(list3, 9) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11c0 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njle 11bc \nmov $0x0,%eax\njmp 11d0 \naddl $0x1,-0x4(%rbp)\nmov -0x1c(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x4(%rbp)\njl 1181 \nmov $0x1,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 0\njmp short loc_11C0\nloc_1181:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_11BC\nmov eax, 0\njmp short loc_11D0\nloc_11BC:\nadd [rbp+var_4], 1\nloc_11C0:\nmov eax, [rbp+var_1C]\nsub eax, 1\ncmp [rbp+var_4], eax\njl short loc_1181\nmov eax, 1\nloc_11D0:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i < a2 - 1; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) > *(_DWORD *)(4 * (i + 1LL) + a1) )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 0\njmp short loc_11C0\nloc_1181:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_11BC\nmov eax, 0\njmp short loc_11D0\nloc_11BC:\nadd [rbp+var_4], 1\nloc_11C0:\nmov eax, [rbp+var_1C]\nsub eax, 1\ncmp [rbp+var_4], eax\njl short loc_1181\nmov eax, 1\nloc_11D0:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i < a2 - 1; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) > *(_DWORD *)(4 * (i + 1LL) + a1) )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int i;\n for (i = 0; i < a2 - 1; ++i) {\n if (*(uint32_t *)(4LL * i + a1) > *(uint32_t *)(4 * (i + 1LL) + a1))\n return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int i;\n for (i = 0; i < a2 - 1; ++i) {\n if (*(uint32_t *)(4LL * i + a1) > *(uint32_t *)(4 * (i + 1LL) + a1))\n return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": 567, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int list1[], int size) {\n for (int i = 0; i < size - 1; i++) {\n if (list1[i] > list1[i + 1]) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n int list1[] = {1,2,4,6,8,10,12,14,16,17};\n\n int list2[] = {1, 2, 4, 6, 8, 10, 12, 14, 20, 17};\n\n int list3[] = {1, 2, 4, 6, 8, 10, 15, 14, 20};\n\n\n\n assert(func0(list1, 10) == true);\n\n assert(func0(list2, 10) == false);\n\n assert(func0(list3, 9) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%esi\njle 1193 \nmov %rdi,%rax\nlea -0x2(%rsi),%edx\nlea 0x4(%rdi,%rdx,4),%rdx\nmov 0x4(%rax),%ecx\ncmp %ecx,(%rax)\njg 1199 \nadd $0x4,%rax\ncmp %rdx,%rax\njne 117d \nmov $0x1,%eax\nretq\nmov $0x1,%eax\nretq\nmov $0x0,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ncmp esi, 1\njle short loc_1193\nmov rax, rdi\nlea edx, [rsi-2]\nlea rdx, [rdi+rdx*4+4]\nloc_117D:\nmov ecx, [rax+4]\ncmp [rax], ecx\njg short loc_1199\nadd rax, 4\ncmp rax, rdx\njnz short loc_117D\nmov eax, 1\nretn\nloc_1193:\nmov eax, 1\nretn\nloc_1199:\nmov eax, 0\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n\n if ( a2 <= 1 )\n return 1LL;\n v2 = a1;\n while ( *v2 <= v2[1] )\n {\n if ( ++v2 == &a1[a2 - 2 + 1] )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ncmp esi, 1\njle short loc_1193\nmov rax, rdi\nlea edx, [rsi-2]\nlea rdx, [rdi+rdx*4+4]\nloc_117D:\nmov ecx, [rax+4]\ncmp [rax], ecx\njg short loc_1199\nadd rax, 4\ncmp rax, rdx\njnz short loc_117D\nmov eax, 1\nretn\nloc_1193:\nmov eax, 1\nretn\nloc_1199:\nmov eax, 0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n\n if ( a2 <= 1 )\n return 1LL;\n v2 = a1;\n while ( *v2 <= v2[1] )\n {\n if ( ++v2 == &a1[a2 - 2 + 1] )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2) {\n uint32_t *v2;\n if (a2 <= 1) return 1LL;\n v2 = a1;\n while (*v2 <= v2[1]) {\n if (++v2 == &a1[a2 - 2 + 1]) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n if (a2 <= 1) return 1LL;\n v2 = a1;\n while (*v2 <= v2[1]) {\n if (++v2 == &a1[a2 - 2 + 1]) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 567, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int list1[], int size) {\n for (int i = 0; i < size - 1; i++) {\n if (list1[i] > list1[i + 1]) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n int list1[] = {1,2,4,6,8,10,12,14,16,17};\n\n int list2[] = {1, 2, 4, 6, 8, 10, 12, 14, 20, 17};\n\n int list3[] = {1, 2, 4, 6, 8, 10, 15, 14, 20};\n\n\n\n assert(func0(list1, 10) == true);\n\n assert(func0(list2, 10) == false);\n\n assert(func0(list3, 9) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%esi\njle 1340 \nlea -0x2(%rsi),%eax\nlea 0x4(%rdi,%rax,4),%rax\njmp 1331 \nnopl 0x0(%rax,%rax,1)\nadd $0x4,%rdi\ncmp %rax,%rdi\nje 1340 \nmov 0x4(%rdi),%edx\ncmp %edx,(%rdi)\njle 1328 \nxor %eax,%eax\nretq\nnopl 0x0(%rax,%rax,1)\nmov $0x1,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ncmp esi, 1\njle short loc_12D8\nlea ecx, [rsi-2]\nmov edx, [rdi]\nlea rax, [rdi+4]\nlea rsi, [rdi+rcx*4+8]\njmp short loc_12C9\nloc_12C0:\nadd rax, 4\ncmp rax, rsi\njz short loc_12D8\nloc_12C9:\nmov ecx, edx\nmov edx, [rax]\ncmp edx, ecx\njge short loc_12C0\nxor eax, eax\nretn\nloc_12D8:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int v2; // edx\n int *v3; // rax\n __int64 v4; // rsi\n int v5; // ecx\n\n if ( a2 <= 1 )\n return 1LL;\n v2 = *a1;\n v3 = a1 + 1;\n v4 = (__int64)&a1[a2 - 2 + 2];\n while ( 1 )\n {\n v5 = v2;\n v2 = *v3;\n if ( *v3 < v5 )\n break;\n if ( ++v3 == (int *)v4 )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_12A0:\nendbr64\ncmp esi, 1\njle short loc_12D8\nlea ecx, [rsi-2]\nmov edx, [rdi]\nlea rax, [rdi+4]\nlea rsi, [rdi+rcx*4+8]\njmp short loc_12C9\nloc_12C0:\nadd rax, 4\ncmp rax, rsi\njz short loc_12D8\nloc_12C9:\nmov ecx, edx\nmov edx, [rax]\ncmp edx, ecx\njge short loc_12C0\nxor eax, eax\nretn\nloc_12D8:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12A0(int *a1, int a2)\n{\n int v2; // edx\n int *v3; // rax\n __int64 v4; // rsi\n int v5; // ecx\n\n if ( a2 <= 1 )\n return 1LL;\n v2 = *a1;\n v3 = a1 + 1;\n v4 = (__int64)&a1[a2 - 2 + 2];\n while ( 1 )\n {\n v5 = v2;\n v2 = *v3;\n if ( *v3 < v5 )\n break;\n if ( ++v3 == (int *)v4 )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12A0(int *a1, int a2) {\n int v2;\n int *v3;\n long long v4;\n int v5;\n if (a2 <= 1) return 1LL;\n v2 = *a1;\n v3 = a1 + 1;\n v4 = (long long)&a1[a2 - 2 + 2];\n while (1) {\n v5 = v2;\n v2 = *v3;\n if (*v3 < v5) break;\n if (++v3 == (int *)v4) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int v2;\n int *v3;\n long long v4;\n int v5;\n if (a2 <= 1) return 1LL;\n v2 = *a1;\n v3 = a1 + 1;\n v4 = (long long)&a1[a2 - 2 + 2];\n while (1) {\n v5 = v2;\n v2 = *v3;\n if (*v3 < v5) break;\n if (++v3 == (int *)v4) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 568, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n// Define a function to create an array of empty dictionaries\n\nstruct EmptyDict {\n\n // We can use an empty struct to represent an empty dictionary\n\n};\n\n\n\n", + "func": "struct EmptyDict* func0(int length) {\n struct EmptyDict* array = malloc(sizeof(struct EmptyDict) * length);\n return array;\n}", + "test": "int main() {\n\n // Test the function with different lengths\n\n assert(func0(5) != NULL);\n\n assert(func0(6) != NULL);\n\n assert(func0(7) != NULL);\n\n\n\n // Free the allocated memory after using\n\n free(func0(5));\n\n free(func0(6));\n\n free(func0(7));\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %edi,-0x14(%rbp)\nmov $0x0,%edi\ncallq 1090 \nmov %rax,-0x8(%rbp)\nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov edi, 0; size\ncall _malloc\nmov [rbp+var_8], rax\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "void *func0()\n{\n return malloc(0LL);\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov edi, 0; size\ncall _malloc\nmov [rbp+var_8], rax\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "void *sub_1189()\n{\n return malloc(0LL);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1189() { return malloc(0LL); }", + "ida_pseudo_norm": "void *func0() { return malloc(0LL); }" + }, + { + "index": 568, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n// Define a function to create an array of empty dictionaries\n\nstruct EmptyDict {\n\n // We can use an empty struct to represent an empty dictionary\n\n};\n\n\n\n", + "func": "struct EmptyDict* func0(int length) {\n struct EmptyDict* array = malloc(sizeof(struct EmptyDict) * length);\n return array;\n}", + "test": "int main() {\n\n // Test the function with different lengths\n\n assert(func0(5) != NULL);\n\n assert(func0(6) != NULL);\n\n assert(func0(7) != NULL);\n\n\n\n // Free the allocated memory after using\n\n free(func0(5));\n\n free(func0(6));\n\n free(func0(7));\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x8,%rsp\nmov $0x0,%edi\ncallq 1070 \nadd $0x8,%rsp\nretq\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\nmov edi, 0; size\ncall _malloc\nadd rsp, 8\nretn", + "ida_pseudo": "void *func0()\n{\n return malloc(0LL);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nsub rsp, 8\nmov edi, 0; size\ncall _malloc\nadd rsp, 8\nretn", + "ida_strip_pseudo": "void *sub_1169()\n{\n return malloc(0LL);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1169() { return malloc(0LL); }", + "ida_pseudo_norm": "void *func0() { return malloc(0LL); }" + }, + { + "index": 569, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n// Function to compare two strings for qsort\n\nint cmpfunc(const void * a, const void * b) {\n\n const char **sa = (const char **)a;\n\n const char **sb = (const char **)b;\n\n return strcmp(*sa, *sb);\n\n}\n\n\n\n// Function to sort sublists\n\nchar*** sort_sublists(char ***list, int num_sublists, int *sizes) {\n\n for(int i=0; i\nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x30(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x38(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\nje 12c3 \nmov $0x0,%eax\njmpq 1368 \nmovl $0x0,-0x4(%rbp)\njmp 1334 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0x4(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x3,%rdx\nadd %rdx,%rax\nmov (%rax),%rdx\nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%rax\nmov -0x4(%rbp),%ecx\nmovslq %ecx,%rcx\nshl $0x3,%rcx\nadd %rcx,%rax\nmov (%rax),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10b0 \ntest %eax,%eax\nje 1330 \nmov $0x0,%eax\njmp 1368 \naddl $0x1,-0x4(%rbp)\nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x30(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x4(%rbp)\njl 12cc \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x24(%rbp),%eax\njl 1289 \nmov $0x1,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_30], rcx\nmov [rbp+var_38], r8\nmov [rbp+var_8], 0\njmp loc_135A\nloc_128C:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_12C6\nmov eax, 0\njmp locret_136B\nloc_12C6:\nmov [rbp+var_4], 0\njmp short loc_1337\nloc_12CF:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nshl rdx, 3\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov rax, [rax]\nmov ecx, [rbp+var_4]\nmovsxd rcx, ecx\nshl rcx, 3\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_1333\nmov eax, 0\njmp short locret_136B\nloc_1333:\nadd [rbp+var_4], 1\nloc_1337:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_4], eax\njl loc_12CF\nadd [rbp+var_8], 1\nloc_135A:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_24]\njl loc_128C\nmov eax, 1\nlocret_136B:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3, __int64 a4, __int64 a5)\n{\n int i; // [rsp+38h] [rbp-8h]\n int j; // [rsp+3Ch] [rbp-4h]\n\n for ( i = 0; i < a3; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a4) != *(_DWORD *)(4LL * i + a5) )\n return 0LL;\n for ( j = 0; j < *(_DWORD *)(4LL * i + a4); ++j )\n {\n if ( strcmp(\n *(const char **)(8LL * j + *(_QWORD *)(8LL * i + a1)),\n *(const char **)(8LL * j + *(_QWORD *)(8LL * i + a2))) )\n {\n return 0LL;\n }\n }\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1261:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_30], rcx\nmov [rbp+var_38], r8\nmov [rbp+var_8], 0\njmp loc_135A\nloc_128C:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_12C6\nmov eax, 0\njmp locret_136B\nloc_12C6:\nmov [rbp+var_4], 0\njmp short loc_1337\nloc_12CF:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nshl rdx, 3\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov rax, [rax]\nmov ecx, [rbp+var_4]\nmovsxd rcx, ecx\nshl rcx, 3\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_1333\nmov eax, 0\njmp short locret_136B\nloc_1333:\nadd [rbp+var_4], 1\nloc_1337:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_4], eax\njl loc_12CF\nadd [rbp+var_8], 1\nloc_135A:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_24]\njl loc_128C\nmov eax, 1\nlocret_136B:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1261(__int64 a1, __int64 a2, int a3, __int64 a4, __int64 a5)\n{\n int i; // [rsp+38h] [rbp-8h]\n int j; // [rsp+3Ch] [rbp-4h]\n\n for ( i = 0; i < a3; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a4) != *(_DWORD *)(4LL * i + a5) )\n return 0LL;\n for ( j = 0; j < *(_DWORD *)(4LL * i + a4); ++j )\n {\n if ( strcmp(\n *(const char **)(8LL * j + *(_QWORD *)(8LL * i + a1)),\n *(const char **)(8LL * j + *(_QWORD *)(8LL * i + a2))) )\n {\n return 0LL;\n }\n }\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1261(long long a1, long long a2, int a3, long long a4,\n long long a5) {\n int i;\n int j;\n for (i = 0; i < a3; ++i) {\n if (*(uint32_t *)(4LL * i + a4) != *(uint32_t *)(4LL * i + a5)) return 0LL;\n for (j = 0; j < *(uint32_t *)(4LL * i + a4); ++j) {\n if (strcmp(*(const char **)(8LL * j + *(uint64_t *)(8LL * i + a1)),\n *(const char **)(8LL * j + *(uint64_t *)(8LL * i + a2)))) {\n return 0LL;\n }\n }\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3, long long a4,\n long long a5) {\n int i;\n int j;\n for (i = 0; i < a3; ++i) {\n if (*(uint32_t *)(4LL * i + a4) != *(uint32_t *)(4LL * i + a5)) return 0LL;\n for (j = 0; j < *(uint32_t *)(4LL * i + a4); ++j) {\n if (strcmp(*(const char **)(8LL * j + *(uint64_t *)(8LL * i + a1)),\n *(const char **)(8LL * j + *(uint64_t *)(8LL * i + a2)))) {\n return 0LL;\n }\n }\n }\n return 1LL;\n}" + }, + { + "index": 569, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n// Function to compare two strings for qsort\n\nint cmpfunc(const void * a, const void * b) {\n\n const char **sa = (const char **)a;\n\n const char **sb = (const char **)b;\n\n return strcmp(*sa, *sb);\n\n}\n\n\n\n// Function to sort sublists\n\nchar*** sort_sublists(char ***list, int num_sublists, int *sizes) {\n\n for(int i=0; i\nmov %r8,%r15\nlea -0x1(%rdx),%eax\nmov %rax,0x18(%rsp)\nmov $0x0,%r14d\nmov (%rsp),%rax\nmov (%rax,%r14,4),%eax\ncmp (%r15,%r14,4),%eax\njne 12b5 \ntest %eax,%eax\njle 1297 \nmov 0x10(%rsp),%rcx\nmov (%rcx,%r14,8),%r12\nmov 0x8(%rsp),%rdx\nmov (%rdx,%r14,8),%rbp\nlea -0x1(%rax),%r13d\nmov $0x0,%ebx\njmp 127c \nmov %rax,%rbx\nmov (%r12,%rbx,8),%rsi\nmov 0x0(%rbp,%rbx,8),%rdi\ncallq 10b0 \ntest %eax,%eax\njne 12bc \nlea 0x1(%rbx),%rax\ncmp %r13,%rbx\njne 1279 \nlea 0x1(%r14),%rax\ncmp 0x18(%rsp),%r14\nje 12a7 \nmov %rax,%r14\njmp 124a \nmov $0x1,%eax\njmp 12c1 \nmov $0x1,%eax\njmp 12c1 \nmov $0x0,%eax\njmp 12c1 \nmov $0x0,%eax\nadd $0x28,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov [rsp+58h+var_50], rdi\nmov [rsp+58h+var_48], rsi\ntest edx, edx\njle short loc_12A9\nmov r14, rcx\nmov r15, r8\nmovsxd rdx, edx\nlea rax, ds:0[rdx*4]\nmov [rsp+58h+var_40], rax\nmov r13d, 0\nloc_1251:\nmov eax, [r14+r13]\ncmp eax, [r15+r13]\njnz short loc_12B0\ntest eax, eax\njle short loc_1294\nmov rcx, [rsp+58h+var_48]\nmov rbx, [rcx+r13*2]\nmov rcx, [rsp+58h+var_50]\nmov rbp, [rcx+r13*2]\ncdqe\nlea r12, [rbx+rax*8]\nloc_1277:\nmov rsi, [rbx]; s2\nmov rdi, [rbp+0]; s1\ncall _strcmp\ntest eax, eax\njnz short loc_12B7\nadd rbx, 8\nadd rbp, 8\ncmp rbx, r12\njnz short loc_1277\nloc_1294:\nadd r13, 4\nmov rax, [rsp+58h+var_40]\ncmp r13, rax\njnz short loc_1251\nmov eax, 1\njmp short loc_12BC\nloc_12A9:\nmov eax, 1\njmp short loc_12BC\nloc_12B0:\nmov eax, 0\njmp short loc_12BC\nloc_12B7:\nmov eax, 0\nloc_12BC:\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3, __int64 a4, __int64 a5)\n{\n __int64 v7; // r13\n int v8; // eax\n const char **v9; // rbx\n const char **v10; // rbp\n const char **v11; // r12\n __int64 v13; // [rsp+18h] [rbp-40h]\n\n if ( a3 <= 0 )\n return 1LL;\n v13 = 4LL * a3;\n v7 = 0LL;\n while ( 1 )\n {\n v8 = *(_DWORD *)(a4 + v7);\n if ( v8 != *(_DWORD *)(a5 + v7) )\n return 0LL;\n if ( v8 > 0 )\n break;\nLABEL_8:\n v7 += 4LL;\n if ( v7 == v13 )\n return 1LL;\n }\n v9 = *(const char ***)(a2 + 2 * v7);\n v10 = *(const char ***)(a1 + 2 * v7);\n v11 = &v9[v8];\n while ( !strcmp(*v10, *v9) )\n {\n ++v9;\n ++v10;\n if ( v9 == v11 )\n goto LABEL_8;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1215:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov [rsp+58h+var_50], rdi\nmov [rsp+58h+var_48], rsi\ntest edx, edx\njle short loc_12A9\nmov r14, rcx\nmov r15, r8\nmovsxd rdx, edx\nlea rax, ds:0[rdx*4]\nmov [rsp+58h+var_40], rax\nmov r13d, 0\nloc_1251:\nmov eax, [r14+r13]\ncmp eax, [r15+r13]\njnz short loc_12B0\ntest eax, eax\njle short loc_1294\nmov rcx, [rsp+58h+var_48]\nmov rbx, [rcx+r13*2]\nmov rcx, [rsp+58h+var_50]\nmov rbp, [rcx+r13*2]\ncdqe\nlea r12, [rbx+rax*8]\nloc_1277:\nmov rsi, [rbx]; s2\nmov rdi, [rbp+0]; s1\ncall _strcmp\ntest eax, eax\njnz short loc_12B7\nadd rbx, 8\nadd rbp, 8\ncmp rbx, r12\njnz short loc_1277\nloc_1294:\nadd r13, 4\nmov rax, [rsp+58h+var_40]\ncmp r13, rax\njnz short loc_1251\nmov eax, 1\njmp short loc_12BC\nloc_12A9:\nmov eax, 1\njmp short loc_12BC\nloc_12B0:\nmov eax, 0\njmp short loc_12BC\nloc_12B7:\nmov eax, 0\nloc_12BC:\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1215(__int64 a1, __int64 a2, int a3, __int64 a4, __int64 a5)\n{\n __int64 v7; // r13\n int v8; // eax\n const char **v9; // rbx\n const char **v10; // rbp\n const char **v11; // r12\n __int64 v13; // [rsp+18h] [rbp-40h]\n\n if ( a3 <= 0 )\n return 1LL;\n v13 = 4LL * a3;\n v7 = 0LL;\n while ( 1 )\n {\n v8 = *(_DWORD *)(a4 + v7);\n if ( v8 != *(_DWORD *)(a5 + v7) )\n return 0LL;\n if ( v8 > 0 )\n break;\nLABEL_8:\n v7 += 4LL;\n if ( v7 == v13 )\n return 1LL;\n }\n v9 = *(const char ***)(a2 + 2 * v7);\n v10 = *(const char ***)(a1 + 2 * v7);\n v11 = &v9[v8];\n while ( !strcmp(*v10, *v9) )\n {\n ++v9;\n ++v10;\n if ( v9 == v11 )\n goto LABEL_8;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1215(long long a1, long long a2, int a3, long long a4,\n long long a5) {\n long long v7;\n int v8;\n const char **v9;\n const char **v10;\n const char **v11;\n long long v13;\n if (a3 <= 0) return 1LL;\n v13 = 4LL * a3;\n v7 = 0LL;\n while (1) {\n v8 = *(uint32_t *)(a4 + v7);\n if (v8 != *(uint32_t *)(a5 + v7)) return 0LL;\n if (v8 > 0) break;\n LABEL_8:\n v7 += 4LL;\n if (v7 == v13) return 1LL;\n }\n v9 = *(const char ***)(a2 + 2 * v7);\n v10 = *(const char ***)(a1 + 2 * v7);\n v11 = &v9[v8];\n while (!strcmp(*v10, *v9)) {\n ++v9;\n ++v10;\n if (v9 == v11) goto LABEL_8;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3, long long a4,\n long long a5) {\n long long v7;\n int v8;\n const char **v9;\n const char **v10;\n const char **v11;\n long long v13;\n if (a3 <= 0) return 1LL;\n v13 = 4LL * a3;\n v7 = 0LL;\n while (1) {\n v8 = *(uint32_t *)(a4 + v7);\n if (v8 != *(uint32_t *)(a5 + v7)) return 0LL;\n if (v8 > 0) break;\n LABEL_8:\n v7 += 4LL;\n if (v7 == v13) return 1LL;\n }\n v9 = *(const char ***)(a2 + 2 * v7);\n v10 = *(const char ***)(a1 + 2 * v7);\n v11 = &v9[v8];\n while (!strcmp(*v10, *v9)) {\n ++v9;\n ++v10;\n if (v9 == v11) goto LABEL_8;\n }\n return 0LL;\n}" + }, + { + "index": 569, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n// Function to compare two strings for qsort\n\nint cmpfunc(const void * a, const void * b) {\n\n const char **sa = (const char **)a;\n\n const char **sb = (const char **)b;\n\n return strcmp(*sa, *sb);\n\n}\n\n\n\n// Function to sort sublists\n\nchar*** sort_sublists(char ***list, int num_sublists, int *sizes) {\n\n for(int i=0; i\nlea -0x1(%rdx),%eax\nmov %r8,%r13\nxor %ebp,%ebp\nmov %rax,0x18(%rsp)\nmov (%rsp),%rax\nmov (%rax,%rbp,4),%eax\ncmp 0x0(%r13,%rbp,4),%eax\njne 179d \ntest %eax,%eax\njle 17b0 \nmov 0x10(%rsp),%rcx\nmov 0x8(%rsp),%rdx\nlea -0x1(%rax),%ebx\nxor %r14d,%r14d\nmov (%rcx,%rbp,8),%r12\nmov (%rdx,%rbp,8),%r15\njmp 178c \nnopl (%rax)\nlea 0x1(%r14),%rax\ncmp %r14,%rbx\nje 17b0 \nmov %rax,%r14\nmov (%r12,%r14,8),%rsi\nmov (%r15,%r14,8),%rdi\ncallq 10b0 \ntest %eax,%eax\nje 1780 \nxor %eax,%eax\nadd $0x28,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nxchg %ax,%ax\nlea 0x1(%rbp),%rax\ncmp %rbp,0x18(%rsp)\nje 17c0 \nmov %rax,%rbp\njmp 1751 \nmov $0x1,%eax\njmp 179f \nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov [rsp+58h+var_50], rdi\nmov [rsp+58h+var_48], rsi\ntest edx, edx\njle short loc_18DE\nmovsxd rdx, edx\nmov r12, rcx\nmov r13, r8\nxor ebp, ebp\nlea rax, ds:0[rdx*4]\nmov [rsp+58h+var_40], rax\nloc_1878:\nmovsxd rax, dword ptr [r12+rbp]\ncmp eax, [r13+rbp+0]\njnz short loc_18BC\ntest eax, eax\njle short loc_18D0\nmov rcx, [rsp+58h+var_48]\nmov r14, [rcx+rbp*2]\nmov rcx, [rsp+58h+var_50]\nlea rbx, [r14+rax*8]\nmov r15, [rcx+rbp*2]\njmp short loc_18AD\nloc_18A0:\nadd r14, 8\nadd r15, 8\ncmp rbx, r14\njz short loc_18D0\nloc_18AD:\nmov rsi, [r14]; s2\nmov rdi, [r15]; s1\ncall _strcmp\ntest eax, eax\njz short loc_18A0\nloc_18BC:\nxor eax, eax\nloc_18BE:\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_18D0:\nmov rax, [rsp+58h+var_40]\nadd rbp, 4\ncmp rbp, rax\njnz short loc_1878\nloc_18DE:\nmov eax, 1\njmp short loc_18BE", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3, __int64 a4, __int64 a5)\n{\n __int64 v7; // rbp\n __int64 v8; // rax\n const char **v9; // r14\n const char **v10; // rbx\n const char **v11; // r15\n __int64 v13; // [rsp+18h] [rbp-40h]\n\n if ( a3 <= 0 )\n return 1LL;\n v7 = 0LL;\n v13 = 4LL * a3;\n while ( 1 )\n {\n v8 = *(int *)(a4 + v7);\n if ( (_DWORD)v8 != *(_DWORD *)(a5 + v7) )\n return 0LL;\n if ( (int)v8 > 0 )\n {\n v9 = *(const char ***)(a2 + 2 * v7);\n v10 = &v9[v8];\n v11 = *(const char ***)(a1 + 2 * v7);\n while ( !strcmp(*v11, *v9) )\n {\n ++v9;\n ++v11;\n if ( v10 == v9 )\n goto LABEL_9;\n }\n return 0LL;\n }\nLABEL_9:\n v7 += 4LL;\n if ( v7 == v13 )\n return 1LL;\n }\n}", + "ida_strip_asm": "sub_1840:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov [rsp+58h+var_50], rdi\nmov [rsp+58h+var_48], rsi\ntest edx, edx\njle short loc_18DE\nmovsxd rdx, edx\nmov r12, rcx\nmov r13, r8\nxor ebp, ebp\nlea rax, ds:0[rdx*4]\nmov [rsp+58h+var_40], rax\nloc_1878:\nmovsxd rax, dword ptr [r12+rbp]\ncmp eax, [r13+rbp+0]\njnz short loc_18BC\ntest eax, eax\njle short loc_18D0\nmov rcx, [rsp+58h+var_48]\nmov r14, [rcx+rbp*2]\nmov rcx, [rsp+58h+var_50]\nlea rbx, [r14+rax*8]\nmov r15, [rcx+rbp*2]\njmp short loc_18AD\nloc_18A0:\nadd r14, 8\nadd r15, 8\ncmp rbx, r14\njz short loc_18D0\nloc_18AD:\nmov rsi, [r14]; s2\nmov rdi, [r15]; s1\ncall _strcmp\ntest eax, eax\njz short loc_18A0\nloc_18BC:\nxor eax, eax\nloc_18BE:\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_18D0:\nmov rax, [rsp+58h+var_40]\nadd rbp, 4\ncmp rbp, rax\njnz short loc_1878\nloc_18DE:\nmov eax, 1\njmp short loc_18BE", + "ida_strip_pseudo": "__int64 __fastcall sub_1840(__int64 a1, __int64 a2, int a3, __int64 a4, __int64 a5)\n{\n __int64 v7; // rbp\n __int64 v8; // rax\n const char **v9; // r14\n const char **v10; // rbx\n const char **v11; // r15\n __int64 v13; // [rsp+18h] [rbp-40h]\n\n if ( a3 <= 0 )\n return 1LL;\n v7 = 0LL;\n v13 = 4LL * a3;\n while ( 1 )\n {\n v8 = *(int *)(a4 + v7);\n if ( (_DWORD)v8 != *(_DWORD *)(a5 + v7) )\n return 0LL;\n if ( (int)v8 > 0 )\n {\n v9 = *(const char ***)(a2 + 2 * v7);\n v10 = &v9[v8];\n v11 = *(const char ***)(a1 + 2 * v7);\n while ( !strcmp(*v11, *v9) )\n {\n ++v9;\n ++v11;\n if ( v10 == v9 )\n goto LABEL_9;\n }\n return 0LL;\n }\nLABEL_9:\n v7 += 4LL;\n if ( v7 == v13 )\n return 1LL;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1840(long long a1, long long a2, int a3, long long a4,\n long long a5) {\n long long v7;\n long long v8;\n const char **v9;\n const char **v10;\n const char **v11;\n long long v13;\n if (a3 <= 0) return 1LL;\n v7 = 0LL;\n v13 = 4LL * a3;\n while (1) {\n v8 = *(int *)(a4 + v7);\n if ((uint32_t)v8 != *(uint32_t *)(a5 + v7)) return 0LL;\n if ((int)v8 > 0) {\n v9 = *(const char ***)(a2 + 2 * v7);\n v10 = &v9[v8];\n v11 = *(const char ***)(a1 + 2 * v7);\n while (!strcmp(*v11, *v9)) {\n ++v9;\n ++v11;\n if (v10 == v9) goto LABEL_9;\n }\n return 0LL;\n }\n LABEL_9:\n v7 += 4LL;\n if (v7 == v13) return 1LL;\n }\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3, long long a4,\n long long a5) {\n long long v7;\n long long v8;\n const char **v9;\n const char **v10;\n const char **v11;\n long long v13;\n if (a3 <= 0) return 1LL;\n v7 = 0LL;\n v13 = 4LL * a3;\n while (1) {\n v8 = *(int *)(a4 + v7);\n if ((uint32_t)v8 != *(uint32_t *)(a5 + v7)) return 0LL;\n if ((int)v8 > 0) {\n v9 = *(const char ***)(a2 + 2 * v7);\n v10 = &v9[v8];\n v11 = *(const char ***)(a1 + 2 * v7);\n while (!strcmp(*v11, *v9)) {\n ++v9;\n ++v11;\n if (v10 == v9) goto LABEL_9;\n }\n return 0LL;\n }\n LABEL_9:\n v7 += 4LL;\n if (v7 == v13) return 1LL;\n }\n}" + }, + { + "index": 569, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n// Function to compare two strings for qsort\n\nint cmpfunc(const void * a, const void * b) {\n\n const char **sa = (const char **)a;\n\n const char **sb = (const char **)b;\n\n return strcmp(*sa, *sb);\n\n}\n\n\n\n// Function to sort sublists\n\nchar*** sort_sublists(char ***list, int num_sublists, int *sizes) {\n\n for(int i=0; i\nlea -0x1(%rdx),%eax\nmov %r8,%r13\nxor %ebp,%ebp\nmov %rax,0x18(%rsp)\nmov (%rsp),%rax\nmov (%rax,%rbp,4),%eax\ncmp 0x0(%r13,%rbp,4),%eax\njne 17bd \ntest %eax,%eax\njle 17d0 \nmov 0x10(%rsp),%rcx\nmov 0x8(%rsp),%rdx\nlea -0x1(%rax),%ebx\nxor %r14d,%r14d\nmov (%rcx,%rbp,8),%r12\nmov (%rdx,%rbp,8),%r15\njmp 17ac \nnopl (%rax)\nlea 0x1(%r14),%rax\ncmp %r14,%rbx\nje 17d0 \nmov %rax,%r14\nmov (%r12,%r14,8),%rsi\nmov (%r15,%r14,8),%rdi\ncallq 10b0 \ntest %eax,%eax\nje 17a0 \nxor %eax,%eax\nadd $0x28,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nxchg %ax,%ax\nlea 0x1(%rbp),%rax\ncmp %rbp,0x18(%rsp)\nje 17e0 \nmov %rax,%rbp\njmp 1771 \nmov $0x1,%eax\njmp 17bf \nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov [rsp+58h+var_50], rdi\nmov [rsp+58h+var_48], rsi\ntest edx, edx\njle short loc_18DB\nmovsxd rdx, edx\nmov r12, rcx\nmov r13, r8\nxor ebp, ebp\nlea rax, ds:0[rdx*4]\nmov [rsp+58h+var_40], rax\nloc_1878:\nmovsxd rax, dword ptr [r12+rbp]\ncmp eax, [r13+rbp+0]\njnz short loc_18BC\ntest eax, eax\njle short loc_18D0\nmov rcx, [rsp+58h+var_48]\nmov r14, [rcx+rbp*2]\nmov rcx, [rsp+58h+var_50]\nlea rbx, [r14+rax*8]\nmov r15, [rcx+rbp*2]\njmp short loc_18AD\nloc_18A0:\nadd r14, 8\nadd r15, 8\ncmp rbx, r14\njz short loc_18D0\nloc_18AD:\nmov rsi, [r14]; s2\nmov rdi, [r15]; s1\ncall _strcmp\ntest eax, eax\njz short loc_18A0\nloc_18BC:\nxor eax, eax\nloc_18BE:\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_18D0:\nadd rbp, 4\ncmp [rsp+58h+var_40], rbp\njnz short loc_1878\nloc_18DB:\nmov eax, 1\njmp short loc_18BE", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3, __int64 a4, __int64 a5)\n{\n __int64 v7; // rbp\n __int64 v8; // rax\n const char **v9; // r14\n const char **v10; // rbx\n const char **v11; // r15\n __int64 v13; // [rsp+18h] [rbp-40h]\n\n if ( a3 <= 0 )\n return 1LL;\n v7 = 0LL;\n v13 = 4LL * a3;\n while ( 1 )\n {\n v8 = *(int *)(a4 + v7);\n if ( (_DWORD)v8 != *(_DWORD *)(a5 + v7) )\n return 0LL;\n if ( (int)v8 > 0 )\n {\n v9 = *(const char ***)(a2 + 2 * v7);\n v10 = &v9[v8];\n v11 = *(const char ***)(a1 + 2 * v7);\n while ( !strcmp(*v11, *v9) )\n {\n ++v9;\n ++v11;\n if ( v10 == v9 )\n goto LABEL_9;\n }\n return 0LL;\n }\nLABEL_9:\n v7 += 4LL;\n if ( v13 == v7 )\n return 1LL;\n }\n}", + "ida_strip_asm": "sub_1840:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov [rsp+58h+var_50], rdi\nmov [rsp+58h+var_48], rsi\ntest edx, edx\njle short loc_18DB\nmovsxd rdx, edx\nmov r12, rcx\nmov r13, r8\nxor ebp, ebp\nlea rax, ds:0[rdx*4]\nmov [rsp+58h+var_40], rax\nloc_1878:\nmovsxd rax, dword ptr [r12+rbp]\ncmp eax, [r13+rbp+0]\njnz short loc_18BC\ntest eax, eax\njle short loc_18D0\nmov rcx, [rsp+58h+var_48]\nmov r14, [rcx+rbp*2]\nmov rcx, [rsp+58h+var_50]\nlea rbx, [r14+rax*8]\nmov r15, [rcx+rbp*2]\njmp short loc_18AD\nloc_18A0:\nadd r14, 8\nadd r15, 8\ncmp rbx, r14\njz short loc_18D0\nloc_18AD:\nmov rsi, [r14]; s2\nmov rdi, [r15]; s1\ncall _strcmp\ntest eax, eax\njz short loc_18A0\nloc_18BC:\nxor eax, eax\nloc_18BE:\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_18D0:\nadd rbp, 4\ncmp [rsp+58h+var_40], rbp\njnz short loc_1878\nloc_18DB:\nmov eax, 1\njmp short loc_18BE", + "ida_strip_pseudo": "__int64 __fastcall sub_1840(__int64 a1, __int64 a2, int a3, __int64 a4, __int64 a5)\n{\n __int64 v7; // rbp\n __int64 v8; // rax\n const char **v9; // r14\n const char **v10; // rbx\n const char **v11; // r15\n __int64 v13; // [rsp+18h] [rbp-40h]\n\n if ( a3 <= 0 )\n return 1LL;\n v7 = 0LL;\n v13 = 4LL * a3;\n while ( 1 )\n {\n v8 = *(int *)(a4 + v7);\n if ( (_DWORD)v8 != *(_DWORD *)(a5 + v7) )\n return 0LL;\n if ( (int)v8 > 0 )\n {\n v9 = *(const char ***)(a2 + 2 * v7);\n v10 = &v9[v8];\n v11 = *(const char ***)(a1 + 2 * v7);\n while ( !strcmp(*v11, *v9) )\n {\n ++v9;\n ++v11;\n if ( v10 == v9 )\n goto LABEL_9;\n }\n return 0LL;\n }\nLABEL_9:\n v7 += 4LL;\n if ( v13 == v7 )\n return 1LL;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1840(long long a1, long long a2, int a3, long long a4,\n long long a5) {\n long long v7;\n long long v8;\n const char **v9;\n const char **v10;\n const char **v11;\n long long v13;\n if (a3 <= 0) return 1LL;\n v7 = 0LL;\n v13 = 4LL * a3;\n while (1) {\n v8 = *(int *)(a4 + v7);\n if ((uint32_t)v8 != *(uint32_t *)(a5 + v7)) return 0LL;\n if ((int)v8 > 0) {\n v9 = *(const char ***)(a2 + 2 * v7);\n v10 = &v9[v8];\n v11 = *(const char ***)(a1 + 2 * v7);\n while (!strcmp(*v11, *v9)) {\n ++v9;\n ++v11;\n if (v10 == v9) goto LABEL_9;\n }\n return 0LL;\n }\n LABEL_9:\n v7 += 4LL;\n if (v13 == v7) return 1LL;\n }\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3, long long a4,\n long long a5) {\n long long v7;\n long long v8;\n const char **v9;\n const char **v10;\n const char **v11;\n long long v13;\n if (a3 <= 0) return 1LL;\n v7 = 0LL;\n v13 = 4LL * a3;\n while (1) {\n v8 = *(int *)(a4 + v7);\n if ((uint32_t)v8 != *(uint32_t *)(a5 + v7)) return 0LL;\n if ((int)v8 > 0) {\n v9 = *(const char ***)(a2 + 2 * v7);\n v10 = &v9[v8];\n v11 = *(const char ***)(a1 + 2 * v7);\n while (!strcmp(*v11, *v9)) {\n ++v9;\n ++v11;\n if (v10 == v9) goto LABEL_9;\n }\n return 0LL;\n }\n LABEL_9:\n v7 += 4LL;\n if (v13 == v7) return 1LL;\n }\n}" + }, + { + "index": 570, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(char* list1[], int n1, char* charlist[], int n_char) {\n char** new_list = malloc(n1 * sizeof(char*));\n for (int i = 0; i < n1; i++) {\n char* line = strdup(list1[i]);\n char* token;\n char buffer[1024] = \"\";\n token = strtok(line, \" \");\n while (token != NULL) {\n int skip = 0;\n for (int j = 0; j < n_char; j++) {\n if (strstr(token, charlist[j]) != NULL) {\n skip = 1;\n break;\n }\n }\n if (!skip) {\n if (strlen(buffer) > 0) strcat(buffer, \" \");\n strcat(buffer, token);\n }\n token = strtok(NULL, \" \");\n }\n new_list[i] = strdup(buffer);\n free(line);\n }\n return new_list;\n}", + "test": "int main() {\n\n // Test case 1\n\n char* list1_a[] = {\"Red color\", \"Orange#\", \"Green\", \"Orange @\", \"White\"};\n\n char* charlist_a[] = {\"#\", \"color\", \"@\"};\n\n char* expected_a[] = {\"Red\", \"\", \"Green\", \"Orange\", \"White\"};\n\n char** result_a = func0(list1_a, 5, charlist_a, 3);\n\n for(int i = 0; i < 5; i++) {\n\n assert(strcmp(result_a[i], expected_a[i]) == 0);\n\n free(result_a[i]);\n\n }\n\n free(result_a);\n\n\n\n // Test case 2\n\n char* list1_b[] = {\"Red &\", \"Orange+\", \"Green\", \"Orange @\", \"White\"};\n\n char* charlist_b[] = {\"&\", \"+\", \"@\"};\n\n char* expected_b[] = {\"Red\", \"\", \"Green\", \"Orange\", \"White\"};\n\n char** result_b = func0(list1_b, 5, charlist_b, 3);\n\n for(int i = 0; i < 5; i++) {\n\n assert(strcmp(result_b[i], expected_b[i]) == 0);\n\n free(result_b[i]);\n\n }\n\n free(result_b);\n\n\n\n // Test case 3\n\n char* list1_c[] = {\"Red &\", \"Orange+\", \"Green\", \"Orange @\", \"White\"};\n\n char* charlist_c[] = {\"@\"};\n\n char* expected_c[] = {\"Red &\", \"Orange+\", \"Green\", \"Orange\", \"White\"};\n\n char** result_c = func0(list1_c, 5, charlist_c, 1);\n\n for(int i = 0; i < 5; i++) {\n\n assert(strcmp(result_c[i], expected_c[i]) == 0);\n\n free(result_c[i]);\n\n }\n\n free(result_c);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x468,%rsp\nmov %rdi,-0x458(%rbp)\nmov %esi,-0x45c(%rbp)\nmov %rdx,-0x468(%rbp)\nmov %ecx,-0x460(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmov -0x45c(%rbp),%eax\ncltq\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 1110 \nmov %rax,-0x430(%rbp)\nmovl $0x0,-0x444(%rbp)\njmpq 145f \nmov -0x444(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x458(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov %rax,%rdi\ncallq 1140 \nmov %rax,-0x428(%rbp)\nmovq $0x0,-0x420(%rbp)\nmovq $0x0,-0x418(%rbp)\nlea -0x410(%rbp),%rdx\nmov $0x0,%eax\nmov $0x7e,%ecx\nmov %rdx,%rdi\nrep stos %rax,%es:(%rdi)\nmov -0x428(%rbp),%rax\nlea 0xcf5(%rip),%rsi\nmov %rax,%rdi\ncallq 1120 \nmov %rax,-0x438(%rbp)\njmpq 140e \nmovl $0x0,-0x440(%rbp)\nmovl $0x0,-0x43c(%rbp)\njmp 1384 \nmov -0x43c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x468(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rdx\nmov -0x438(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1150 \ntest %rax,%rax\nje 137d \nmovl $0x1,-0x440(%rbp)\njmp 1392 \naddl $0x1,-0x43c(%rbp)\nmov -0x43c(%rbp),%eax\ncmp -0x460(%rbp),%eax\njl 133d \ncmpl $0x0,-0x440(%rbp)\njne 13f6 \nlea -0x420(%rbp),%rax\nmovzbl (%rax),%eax\ntest %al,%al\nje 13dd \nlea -0x420(%rbp),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nlea -0x420(%rbp),%rax\nadd %rdx,%rax\nmovw $0x20,(%rax)\nmov -0x438(%rbp),%rdx\nlea -0x420(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1130 \nlea 0xc0b(%rip),%rsi\nmov $0x0,%edi\ncallq 1120 \nmov %rax,-0x438(%rbp)\ncmpq $0x0,-0x438(%rbp)\njne 1327 \nmov -0x444(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x430(%rbp),%rax\nlea (%rdx,%rax,1),%rbx\nlea -0x420(%rbp),%rax\nmov %rax,%rdi\ncallq 1140 \nmov %rax,(%rbx)\nmov -0x428(%rbp),%rax\nmov %rax,%rdi\ncallq 10d0 \naddl $0x1,-0x444(%rbp)\nmov -0x444(%rbp),%eax\ncmp -0x45c(%rbp),%eax\njl 12ac \nmov -0x430(%rbp),%rax\nmov -0x18(%rbp),%rbx\nxor %fs:0x28,%rbx\nje 148c \ncallq 10e0 <__stack_chk_fail@plt>\nadd $0x468,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 468h\nmov [rbp+var_458], rdi\nmov [rbp+var_45C], esi\nmov [rbp+var_468], rdx\nmov [rbp+var_460], ecx\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov eax, [rbp+var_45C]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_430], rax\nmov [rbp+var_444], 0\njmp loc_145C\nloc_12CC:\nmov eax, [rbp+var_444]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_458]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; s\ncall _strdup\nmov [rbp+s], rax\nlea rdx, [rbp+dest]\nmov eax, 0\nmov ecx, 80h\nmov rdi, rdx\nrep stosq\nmov rax, [rbp+s]\nlea rdx, delim; \" \"\nmov rsi, rdx; delim\nmov rdi, rax; s\ncall _strtok\nmov [rbp+haystack], rax\njmp loc_140B\nloc_1334:\nmov [rbp+var_440], 0\nmov [rbp+var_43C], 0\njmp short loc_1391\nloc_134A:\nmov eax, [rbp+var_43C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_468]\nadd rax, rdx\nmov rdx, [rax]\nmov rax, [rbp+haystack]\nmov rsi, rdx; needle\nmov rdi, rax; haystack\ncall _strstr\ntest rax, rax\njz short loc_138A\nmov [rbp+var_440], 1\njmp short loc_139F\nloc_138A:\nadd [rbp+var_43C], 1\nloc_1391:\nmov eax, [rbp+var_43C]\ncmp eax, [rbp+var_460]\njl short loc_134A\nloc_139F:\ncmp [rbp+var_440], 0\njnz short loc_13F0\nlea rax, [rbp+dest]\nmovzx eax, byte ptr [rax]\ntest al, al\njz short loc_13D7\nlea rax, [rbp+dest]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nlea rax, [rbp+dest]\nadd rax, rdx\nmov word ptr [rax], 20h ; ' '\nloc_13D7:\nmov rdx, [rbp+haystack]\nlea rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\nloc_13F0:\nlea rax, delim; \" \"\nmov rsi, rax; delim\nmov edi, 0; s\ncall _strtok\nmov [rbp+haystack], rax\nloc_140B:\ncmp [rbp+haystack], 0\njnz loc_1334\nmov eax, [rbp+var_444]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_430]\nlea rbx, [rdx+rax]\nlea rax, [rbp+dest]\nmov rdi, rax; s\ncall _strdup\nmov [rbx], rax\nmov rax, [rbp+s]\nmov rdi, rax; ptr\ncall _free\nadd [rbp+var_444], 1\nloc_145C:\nmov eax, [rbp+var_444]\ncmp eax, [rbp+var_45C]\njl loc_12CC\nmov rax, [rbp+var_430]\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njz short loc_1489\ncall ___stack_chk_fail\nloc_1489:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, int a2, __int64 a3, int a4)\n{\n int i; // [rsp+2Ch] [rbp-444h]\n int v8; // [rsp+30h] [rbp-440h]\n int j; // [rsp+34h] [rbp-43Ch]\n const char *haystack; // [rsp+38h] [rbp-438h]\n _QWORD *v11; // [rsp+40h] [rbp-430h]\n char *s; // [rsp+48h] [rbp-428h]\n char dest[1032]; // [rsp+50h] [rbp-420h] BYREF\n unsigned __int64 v14; // [rsp+458h] [rbp-18h]\n\n v14 = __readfsqword(0x28u);\n v11 = malloc(8LL * a2);\n for ( i = 0; i < a2; ++i )\n {\n s = strdup(*(const char **)(8LL * i + a1));\n memset(dest, 0, 0x400uLL);\n for ( haystack = strtok(s, \" \"); haystack; haystack = strtok(0LL, \" \") )\n {\n v8 = 0;\n for ( j = 0; j < a4; ++j )\n {\n if ( strstr(haystack, *(const char **)(8LL * j + a3)) )\n {\n v8 = 1;\n break;\n }\n }\n if ( !v8 )\n {\n if ( dest[0] )\n *(_WORD *)&dest[strlen(dest)] = 32;\n strcat(dest, haystack);\n }\n }\n v11[i] = strdup(dest);\n free(s);\n }\n return v11;\n}", + "ida_strip_asm": "sub_1269:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 468h\nmov [rbp+var_458], rdi\nmov [rbp+var_45C], esi\nmov [rbp+var_468], rdx\nmov [rbp+var_460], ecx\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov eax, [rbp+var_45C]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_430], rax\nmov [rbp+var_444], 0\njmp loc_145C\nloc_12CC:\nmov eax, [rbp+var_444]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_458]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; s\ncall _strdup\nmov [rbp+s], rax\nlea rdx, [rbp+dest]\nmov eax, 0\nmov ecx, 80h\nmov rdi, rdx\nrep stosq\nmov rax, [rbp+s]\nlea rdx, delim; \" \"\nmov rsi, rdx; delim\nmov rdi, rax; s\ncall _strtok\nmov [rbp+haystack], rax\njmp loc_140B\nloc_1334:\nmov [rbp+var_440], 0\nmov [rbp+var_43C], 0\njmp short loc_1391\nloc_134A:\nmov eax, [rbp+var_43C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_468]\nadd rax, rdx\nmov rdx, [rax]\nmov rax, [rbp+haystack]\nmov rsi, rdx; needle\nmov rdi, rax; haystack\ncall _strstr\ntest rax, rax\njz short loc_138A\nmov [rbp+var_440], 1\njmp short loc_139F\nloc_138A:\nadd [rbp+var_43C], 1\nloc_1391:\nmov eax, [rbp+var_43C]\ncmp eax, [rbp+var_460]\njl short loc_134A\nloc_139F:\ncmp [rbp+var_440], 0\njnz short loc_13F0\nlea rax, [rbp+dest]\nmovzx eax, byte ptr [rax]\ntest al, al\njz short loc_13D7\nlea rax, [rbp+dest]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nlea rax, [rbp+dest]\nadd rax, rdx\nmov word ptr [rax], 20h ; ' '\nloc_13D7:\nmov rdx, [rbp+haystack]\nlea rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\nloc_13F0:\nlea rax, delim; \" \"\nmov rsi, rax; delim\nmov edi, 0; s\ncall _strtok\nmov [rbp+haystack], rax\nloc_140B:\ncmp [rbp+haystack], 0\njnz loc_1334\nmov eax, [rbp+var_444]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_430]\nlea rbx, [rdx+rax]\nlea rax, [rbp+dest]\nmov rdi, rax; s\ncall _strdup\nmov [rbx], rax\nmov rax, [rbp+s]\nmov rdi, rax; ptr\ncall _free\nadd [rbp+var_444], 1\nloc_145C:\nmov eax, [rbp+var_444]\ncmp eax, [rbp+var_45C]\njl loc_12CC\nmov rax, [rbp+var_430]\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njz short loc_1489\ncall ___stack_chk_fail\nloc_1489:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1269(__int64 a1, int a2, __int64 a3, int a4)\n{\n int i; // [rsp+2Ch] [rbp-444h]\n int v8; // [rsp+30h] [rbp-440h]\n int j; // [rsp+34h] [rbp-43Ch]\n const char *haystack; // [rsp+38h] [rbp-438h]\n _QWORD *v11; // [rsp+40h] [rbp-430h]\n char *s; // [rsp+48h] [rbp-428h]\n char dest[1032]; // [rsp+50h] [rbp-420h] BYREF\n unsigned __int64 v14; // [rsp+458h] [rbp-18h]\n\n v14 = __readfsqword(0x28u);\n v11 = malloc(8LL * a2);\n for ( i = 0; i < a2; ++i )\n {\n s = strdup(*(const char **)(8LL * i + a1));\n memset(dest, 0, 0x400uLL);\n for ( haystack = strtok(s, \" \"); haystack; haystack = strtok(0LL, \" \") )\n {\n v8 = 0;\n for ( j = 0; j < a4; ++j )\n {\n if ( strstr(haystack, *(const char **)(8LL * j + a3)) )\n {\n v8 = 1;\n break;\n }\n }\n if ( !v8 )\n {\n if ( dest[0] )\n *(_WORD *)&dest[strlen(dest)] = 32;\n strcat(dest, haystack);\n }\n }\n v11[i] = strdup(dest);\n free(s);\n }\n return v11;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1269(long long a1, int a2, long long a3, int a4) {\n int i;\n int v8;\n int j;\n const char *haystack;\n uint64_t *v11;\n char *s;\n char dest[1032];\n unsigned long long v14;\n v14 = __readfsqword(40u);\n v11 = malloc(8LL * a2);\n for (i = 0; i < a2; ++i) {\n s = strdup(*(const char **)(8LL * i + a1));\n memset(dest, 0, 1024uLL);\n for (haystack = strtok(s, \" \"); haystack; haystack = strtok(0LL, \" \")) {\n v8 = 0;\n for (j = 0; j < a4; ++j) {\n if (strstr(haystack, *(const char **)(8LL * j + a3))) {\n v8 = 1;\n break;\n }\n }\n if (!v8) {\n if (dest[0]) *(unsigned short *)&dest[strlen(dest)] = 32;\n strcat(dest, haystack);\n }\n }\n v11[i] = strdup(dest);\n free(s);\n }\n return v11;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, int a2, long long a3, int a4) {\n int i;\n int v8;\n int j;\n const char *haystack;\n uint64_t *v11;\n char *s;\n char dest[1032];\n unsigned long long v14;\n v14 = __readfsqword(40u);\n v11 = malloc(8LL * a2);\n for (i = 0; i < a2; ++i) {\n s = strdup(*(const char **)(8LL * i + a1));\n memset(dest, 0, 1024uLL);\n for (haystack = strtok(s, \" \"); haystack; haystack = strtok(0LL, \" \")) {\n v8 = 0;\n for (j = 0; j < a4; ++j) {\n if (strstr(haystack, *(const char **)(8LL * j + a3))) {\n v8 = 1;\n break;\n }\n }\n if (!v8) {\n if (dest[0]) *(unsigned short *)&dest[strlen(dest)] = 32;\n strcat(dest, haystack);\n }\n }\n v11[i] = strdup(dest);\n free(s);\n }\n return v11;\n}" + }, + { + "index": 570, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(char* list1[], int n1, char* charlist[], int n_char) {\n char** new_list = malloc(n1 * sizeof(char*));\n for (int i = 0; i < n1; i++) {\n char* line = strdup(list1[i]);\n char* token;\n char buffer[1024] = \"\";\n token = strtok(line, \" \");\n while (token != NULL) {\n int skip = 0;\n for (int j = 0; j < n_char; j++) {\n if (strstr(token, charlist[j]) != NULL) {\n skip = 1;\n break;\n }\n }\n if (!skip) {\n if (strlen(buffer) > 0) strcat(buffer, \" \");\n strcat(buffer, token);\n }\n token = strtok(NULL, \" \");\n }\n new_list[i] = strdup(buffer);\n free(line);\n }\n return new_list;\n}", + "test": "int main() {\n\n // Test case 1\n\n char* list1_a[] = {\"Red color\", \"Orange#\", \"Green\", \"Orange @\", \"White\"};\n\n char* charlist_a[] = {\"#\", \"color\", \"@\"};\n\n char* expected_a[] = {\"Red\", \"\", \"Green\", \"Orange\", \"White\"};\n\n char** result_a = func0(list1_a, 5, charlist_a, 3);\n\n for(int i = 0; i < 5; i++) {\n\n assert(strcmp(result_a[i], expected_a[i]) == 0);\n\n free(result_a[i]);\n\n }\n\n free(result_a);\n\n\n\n // Test case 2\n\n char* list1_b[] = {\"Red &\", \"Orange+\", \"Green\", \"Orange @\", \"White\"};\n\n char* charlist_b[] = {\"&\", \"+\", \"@\"};\n\n char* expected_b[] = {\"Red\", \"\", \"Green\", \"Orange\", \"White\"};\n\n char** result_b = func0(list1_b, 5, charlist_b, 3);\n\n for(int i = 0; i < 5; i++) {\n\n assert(strcmp(result_b[i], expected_b[i]) == 0);\n\n free(result_b[i]);\n\n }\n\n free(result_b);\n\n\n\n // Test case 3\n\n char* list1_c[] = {\"Red &\", \"Orange+\", \"Green\", \"Orange @\", \"White\"};\n\n char* charlist_c[] = {\"@\"};\n\n char* expected_c[] = {\"Red &\", \"Orange+\", \"Green\", \"Orange\", \"White\"};\n\n char** result_c = func0(list1_c, 5, charlist_c, 1);\n\n for(int i = 0; i < 5; i++) {\n\n assert(strcmp(result_c[i], expected_c[i]) == 0);\n\n free(result_c[i]);\n\n }\n\n free(result_c);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x448,%rsp\nmov %rdi,0x28(%rsp)\nmov %esi,%ebp\nmov %rdx,%rbx\nmov %ecx,%r14d\nmov %fs:0x28,%rax\nmov %rax,0x438(%rsp)\nxor %eax,%eax\nmovslq %esi,%rdi\nshl $0x3,%rdi\ncallq 1120 \nmov %rax,0x18(%rsp)\ntest %ebp,%ebp\njle 13bd \nlea -0x1(%rbp),%eax\nmov %rax,0x20(%rsp)\nmov %rbx,%r15\nlea -0x1(%r14),%eax\nlea 0x8(%rbx,%rax,8),%r12\nmovq $0x0,0x8(%rsp)\nmov $0x0,%r13d\nlea 0x30(%rsp),%rax\nmov %rax,(%rsp)\njmpq 1360 \nmov $0x400,%edx\nlea 0xd30(%rip),%rsi\nmov (%rsp),%rdi\ncallq 10d0 <__strcat_chk@plt>\nmov $0x400,%edx\nmov %rbp,%rsi\nmov (%rsp),%rdi\ncallq 10d0 <__strcat_chk@plt>\nlea 0xd0f(%rip),%rsi\nmov %r13,%rdi\ncallq 1130 \nmov %rax,%rbp\ntest %rax,%rax\nje 132f \nmov %r15,%rbx\ntest %r14d,%r14d\njle 1326 \nmov (%rbx),%rsi\nmov %rbp,%rdi\ncallq 1150 \ntest %rax,%rax\njne 12ee \nadd $0x8,%rbx\ncmp %r12,%rbx\njne 130d \ncmpb $0x0,0x30(%rsp)\nje 12dd \njmp 12c8 \nmov (%rsp),%rdi\ncallq 1140 \nmov 0x18(%rsp),%rdx\nmov 0x8(%rsp),%rbx\nmov %rax,(%rdx,%rbx,8)\nmov 0x10(%rsp),%rdi\ncallq 10e0 \nlea 0x1(%rbx),%rax\ncmp 0x20(%rsp),%rbx\nje 13bd \nmov %rax,0x8(%rsp)\nmov 0x28(%rsp),%rax\nmov 0x8(%rsp),%rdx\nmov (%rax,%rdx,8),%rdi\ncallq 1140 \nmov %rax,%rdx\nmov %rax,0x10(%rsp)\nmovq $0x0,0x30(%rsp)\nmovq $0x0,0x38(%rsp)\nlea 0x40(%rsp),%rdi\nmov $0x7e,%ecx\nmov %r13,%rax\nrep stos %rax,%es:(%rdi)\nlea 0xc60(%rip),%rsi\nmov %rdx,%rdi\ncallq 1130 \nmov %rax,%rbp\ntest %rax,%rax\njne 1305 \njmpq 132f \nmov 0x438(%rsp),%rax\nxor %fs:0x28,%rax\njne 13e7 \nmov 0x18(%rsp),%rax\nadd $0x448,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\ncallq 10f0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 448h\nmov rbp, rdi\nmov r12d, esi\nmov r13, rdx\nmov [rsp+478h+var_470], rdx\nmov r14d, ecx\nmov rax, fs:28h\nmov [rsp+478h+var_40], rax\nxor eax, eax\nmovsxd rbx, esi\nshl rbx, 3\nmov rdi, rbx; size\ncall _malloc\nmov [rsp+478h+var_450], rax\ntest r12d, r12d\njle loc_139B\nmov r15, rbp\nmov [rsp+478h+var_468], rax\nlea rax, [rbp+rbx+0]\nmov [rsp+478h+var_458], rax\nmovsxd rax, r14d\nlea r12, [r13+rax*8+0]\nlea r13, delim; \" \"\njmp loc_1360\nloc_12C5:\nlea rdi, [rsp+478h+s]\nmov edx, 400h\nmov rsi, rbp\ncall ___strcat_chk\nloc_12D7:\nmov rsi, r13; delim\nmov edi, 0; s\ncall _strtok\nmov rbp, rax\ntest rax, rax\njz short loc_132A\nloc_12EC:\nmov rbx, [rsp+478h+var_470]\ntest r14d, r14d\njle short loc_130F\nloc_12F6:\nmov rsi, [rbx]; needle\nmov rdi, rbp; haystack\ncall _strstr\ntest rax, rax\njnz short loc_12D7\nadd rbx, 8\ncmp rbx, r12\njnz short loc_12F6\nloc_130F:\ncmp [rsp+478h+s], 0\njz short loc_12C5\nlea rdi, [rsp+478h+s]\nmov edx, 400h\nmov rsi, r13\ncall ___strcat_chk\njmp short loc_12C5\nloc_132A:\nlea rdi, [rsp+478h+s]; s\ncall _strdup\nmov rbx, [rsp+478h+var_468]\nmov [rbx], rax\nmov rdi, [rsp+478h+ptr]; ptr\ncall _free\nadd r15, 8\nmov rcx, rbx\nadd rcx, 8\nmov [rsp+478h+var_468], rcx\nmov rax, [rsp+478h+var_458]\ncmp r15, rax\njz short loc_139B\nloc_1360:\nmov rdi, [r15]; s\ncall _strdup\nmov rdx, rax\nmov [rsp+478h+ptr], rax\nlea rdi, [rsp+478h+s]\nmov ecx, 80h\nmov eax, 0\nrep stosq\nmov rsi, r13; delim\nmov rdi, rdx; s\ncall _strtok\nmov rbp, rax\ntest rax, rax\njnz loc_12EC\njmp short loc_132A\nloc_139B:\nmov rax, [rsp+478h+var_40]\nsub rax, fs:28h\njnz short loc_13C5\nmov rax, [rsp+478h+var_450]\nadd rsp, 448h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_13C5:\ncall ___stack_chk_fail", + "ida_pseudo": "_QWORD *__fastcall func0(const char **a1, int a2, const char **a3, int a4)\n{\n _QWORD *v6; // rax\n const char **v7; // r15\n char *i; // rbp\n const char **v9; // rbx\n char **v12; // [rsp+10h] [rbp-468h]\n char *ptr; // [rsp+18h] [rbp-460h]\n _QWORD *v14; // [rsp+28h] [rbp-450h]\n char s[1032]; // [rsp+30h] [rbp-448h] BYREF\n unsigned __int64 v16; // [rsp+438h] [rbp-40h]\n\n v16 = __readfsqword(0x28u);\n v6 = malloc(8LL * a2);\n v14 = v6;\n if ( a2 > 0 )\n {\n v7 = a1;\n v12 = (char **)v6;\n do\n {\n ptr = strdup(*v7);\n memset(s, 0, 0x400uLL);\n for ( i = strtok(ptr, \" \"); i; i = strtok(0LL, \" \") )\n {\n v9 = a3;\n if ( a4 <= 0 )\n {\nLABEL_8:\n if ( s[0] )\n __strcat_chk(s, \" \", 1024LL);\n __strcat_chk(s, i, 1024LL);\n }\n else\n {\n while ( !strstr(i, *v9) )\n {\n if ( ++v9 == &a3[a4] )\n goto LABEL_8;\n }\n }\n }\n *v12 = strdup(s);\n free(ptr);\n ++v7;\n ++v12;\n }\n while ( v7 != &a1[a2] );\n }\n return v14;\n}", + "ida_strip_asm": "sub_1249:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 448h\nmov rbp, rdi\nmov r12d, esi\nmov r13, rdx\nmov [rsp+478h+var_470], rdx\nmov r14d, ecx\nmov rax, fs:28h\nmov [rsp+478h+var_40], rax\nxor eax, eax\nmovsxd rbx, esi\nshl rbx, 3\nmov rdi, rbx; size\ncall _malloc\nmov [rsp+478h+var_450], rax\ntest r12d, r12d\njle loc_139B\nmov r15, rbp\nmov [rsp+478h+var_468], rax\nlea rax, [rbp+rbx+0]\nmov [rsp+478h+var_458], rax\nmovsxd rax, r14d\nlea r12, [r13+rax*8+0]\nlea r13, delim; \" \"\njmp loc_1360\nloc_12C5:\nlea rdi, [rsp+478h+s]\nmov edx, 400h\nmov rsi, rbp\ncall ___strcat_chk\nloc_12D7:\nmov rsi, r13; delim\nmov edi, 0; s\ncall _strtok\nmov rbp, rax\ntest rax, rax\njz short loc_132A\nloc_12EC:\nmov rbx, [rsp+478h+var_470]\ntest r14d, r14d\njle short loc_130F\nloc_12F6:\nmov rsi, [rbx]; needle\nmov rdi, rbp; haystack\ncall _strstr\ntest rax, rax\njnz short loc_12D7\nadd rbx, 8\ncmp rbx, r12\njnz short loc_12F6\nloc_130F:\ncmp [rsp+478h+s], 0\njz short loc_12C5\nlea rdi, [rsp+478h+s]\nmov edx, 400h\nmov rsi, r13\ncall ___strcat_chk\njmp short loc_12C5\nloc_132A:\nlea rdi, [rsp+478h+s]; s\ncall _strdup\nmov rbx, [rsp+478h+var_468]\nmov [rbx], rax\nmov rdi, [rsp+478h+ptr]; ptr\ncall _free\nadd r15, 8\nmov rcx, rbx\nadd rcx, 8\nmov [rsp+478h+var_468], rcx\nmov rax, [rsp+478h+var_458]\ncmp r15, rax\njz short loc_139B\nloc_1360:\nmov rdi, [r15]; s\ncall _strdup\nmov rdx, rax\nmov [rsp+478h+ptr], rax\nlea rdi, [rsp+478h+s]\nmov ecx, 80h\nmov eax, 0\nrep stosq\nmov rsi, r13; delim\nmov rdi, rdx; s\ncall _strtok\nmov rbp, rax\ntest rax, rax\njnz loc_12EC\njmp short loc_132A\nloc_139B:\nmov rax, [rsp+478h+var_40]\nsub rax, fs:28h\njnz short loc_13C5\nmov rax, [rsp+478h+var_450]\nadd rsp, 448h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_13C5:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1249(const char **a1, int a2, const char **a3, int a4)\n{\n _QWORD *v6; // rax\n const char **v7; // r15\n char *i; // rbp\n const char **v9; // rbx\n char **v12; // [rsp+10h] [rbp-468h]\n char *ptr; // [rsp+18h] [rbp-460h]\n _QWORD *v14; // [rsp+28h] [rbp-450h]\n char s[1032]; // [rsp+30h] [rbp-448h] BYREF\n unsigned __int64 v16; // [rsp+438h] [rbp-40h]\n\n v16 = __readfsqword(0x28u);\n v6 = malloc(8LL * a2);\n v14 = v6;\n if ( a2 > 0 )\n {\n v7 = a1;\n v12 = (char **)v6;\n do\n {\n ptr = strdup(*v7);\n memset(s, 0, 0x400uLL);\n for ( i = strtok(ptr, \" \"); i; i = strtok(0LL, \" \") )\n {\n v9 = a3;\n if ( a4 <= 0 )\n {\nLABEL_8:\n if ( s[0] )\n __strcat_chk(s, \" \", 1024LL);\n __strcat_chk(s, i, 1024LL);\n }\n else\n {\n while ( !strstr(i, *v9) )\n {\n if ( ++v9 == &a3[a4] )\n goto LABEL_8;\n }\n }\n }\n *v12 = strdup(s);\n free(ptr);\n ++v7;\n ++v12;\n }\n while ( v7 != &a1[a2] );\n }\n return v14;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1249(const char **a1, int a2, const char **a3, int a4) {\n uint64_t *v6;\n const char **v7;\n char *i;\n const char **v9;\n char **v12;\n char *ptr;\n uint64_t *v14;\n char s[1032];\n unsigned long long v16;\n v16 = __readfsqword(40u);\n v6 = malloc(8LL * a2);\n v14 = v6;\n if (a2 > 0) {\n v7 = a1;\n v12 = (char **)v6;\n do {\n ptr = strdup(*v7);\n memset(s, 0, 1024uLL);\n for (i = strtok(ptr, \" \"); i; i = strtok(0LL, \" \")) {\n v9 = a3;\n if (a4 <= 0) {\n LABEL_8:\n if (s[0]) __strcat_chk(s, \" \", 1024LL);\n __strcat_chk(s, i, 1024LL);\n } else {\n while (!strstr(i, *v9)) {\n if (++v9 == &a3[a4]) goto LABEL_8;\n }\n }\n }\n *v12 = strdup(s);\n free(ptr);\n ++v7;\n ++v12;\n } while (v7 != &a1[a2]);\n }\n return v14;\n}", + "ida_pseudo_norm": "uint64_t *func0(const char **a1, int a2, const char **a3, int a4) {\n uint64_t *v6;\n const char **v7;\n char *i;\n const char **v9;\n char **v12;\n char *ptr;\n uint64_t *v14;\n char s[1032];\n unsigned long long v16;\n v16 = __readfsqword(40u);\n v6 = malloc(8LL * a2);\n v14 = v6;\n if (a2 > 0) {\n v7 = a1;\n v12 = (char **)v6;\n do {\n ptr = strdup(*v7);\n memset(s, 0, 1024uLL);\n for (i = strtok(ptr, \" \"); i; i = strtok(0LL, \" \")) {\n v9 = a3;\n if (a4 <= 0) {\n LABEL_8:\n if (s[0]) __strcat_chk(s, \" \", 1024LL);\n __strcat_chk(s, i, 1024LL);\n } else {\n while (!strstr(i, *v9)) {\n if (++v9 == &a3[a4]) goto LABEL_8;\n }\n }\n }\n *v12 = strdup(s);\n free(ptr);\n ++v7;\n ++v12;\n } while (v7 != &a1[a2]);\n }\n return v14;\n}" + }, + { + "index": 570, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(char* list1[], int n1, char* charlist[], int n_char) {\n char** new_list = malloc(n1 * sizeof(char*));\n for (int i = 0; i < n1; i++) {\n char* line = strdup(list1[i]);\n char* token;\n char buffer[1024] = \"\";\n token = strtok(line, \" \");\n while (token != NULL) {\n int skip = 0;\n for (int j = 0; j < n_char; j++) {\n if (strstr(token, charlist[j]) != NULL) {\n skip = 1;\n break;\n }\n }\n if (!skip) {\n if (strlen(buffer) > 0) strcat(buffer, \" \");\n strcat(buffer, token);\n }\n token = strtok(NULL, \" \");\n }\n new_list[i] = strdup(buffer);\n free(line);\n }\n return new_list;\n}", + "test": "int main() {\n\n // Test case 1\n\n char* list1_a[] = {\"Red color\", \"Orange#\", \"Green\", \"Orange @\", \"White\"};\n\n char* charlist_a[] = {\"#\", \"color\", \"@\"};\n\n char* expected_a[] = {\"Red\", \"\", \"Green\", \"Orange\", \"White\"};\n\n char** result_a = func0(list1_a, 5, charlist_a, 3);\n\n for(int i = 0; i < 5; i++) {\n\n assert(strcmp(result_a[i], expected_a[i]) == 0);\n\n free(result_a[i]);\n\n }\n\n free(result_a);\n\n\n\n // Test case 2\n\n char* list1_b[] = {\"Red &\", \"Orange+\", \"Green\", \"Orange @\", \"White\"};\n\n char* charlist_b[] = {\"&\", \"+\", \"@\"};\n\n char* expected_b[] = {\"Red\", \"\", \"Green\", \"Orange\", \"White\"};\n\n char** result_b = func0(list1_b, 5, charlist_b, 3);\n\n for(int i = 0; i < 5; i++) {\n\n assert(strcmp(result_b[i], expected_b[i]) == 0);\n\n free(result_b[i]);\n\n }\n\n free(result_b);\n\n\n\n // Test case 3\n\n char* list1_c[] = {\"Red &\", \"Orange+\", \"Green\", \"Orange @\", \"White\"};\n\n char* charlist_c[] = {\"@\"};\n\n char* expected_c[] = {\"Red &\", \"Orange+\", \"Green\", \"Orange\", \"White\"};\n\n char** result_c = func0(list1_c, 5, charlist_c, 1);\n\n for(int i = 0; i < 5; i++) {\n\n assert(strcmp(result_c[i], expected_c[i]) == 0);\n\n free(result_c[i]);\n\n }\n\n free(result_c);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\nmov %rdx,%r14\npush %r13\nmov %ecx,%r13d\npush %r12\npush %rbp\npush %rbx\nsub $0x458,%rsp\nmov %rdi,0x30(%rsp)\nmovslq %esi,%rdi\nmov %rdx,0x8(%rsp)\nmov %rdi,%rbx\nshl $0x3,%rdi\nmov %fs:0x28,%rax\nmov %rax,0x448(%rsp)\nxor %eax,%eax\ncallq 1120 \nmov %rax,0x20(%rsp)\ntest %ebx,%ebx\njle 1742 \nmovq $0x0,0x10(%rsp)\nlea -0x1(%rbx),%eax\nmov %rax,0x28(%rsp)\nlea -0x1(%r13),%eax\nlea 0x8(%r14,%rax,8),%rbx\nlea 0x50(%rsp),%rax\nmov %rax,0x38(%rsp)\nlea 0x40(%rsp),%r14\nnopl (%rax)\nmov 0x10(%rsp),%rdx\nmov 0x30(%rsp),%rax\nlea 0x9b3(%rip),%rbp\nmov (%rax,%rdx,8),%rdi\ncallq 1140 \nmov 0x38(%rsp),%rdi\npxor %xmm0,%xmm0\nmov $0x7e,%ecx\nmov %rax,%rdx\nmov %rax,0x18(%rsp)\nxor %eax,%eax\nlea 0x98b(%rip),%rsi\nrep stos %rax,%es:(%rdi)\nmov %rdx,%rdi\nmovaps %xmm0,0x40(%rsp)\ncallq 1130 \nmov %rax,%r15\ntest %rax,%rax\nje 16d4 \nnopl 0x0(%rax)\nmov 0x8(%rsp),%r12\ntest %r13d,%r13d\njg 16b1 \njmp 1710 \nnopl 0x0(%rax)\nadd $0x8,%r12\ncmp %rbx,%r12\nje 1710 \nmov (%r12),%rsi\nmov %r15,%rdi\ncallq 1150 \ntest %rax,%rax\nje 16a8 \nmov %rbp,%rsi\nxor %edi,%edi\ncallq 1130 \nmov %rax,%r15\ntest %rax,%rax\njne 1698 \nmov %r14,%rdi\ncallq 1140 \nmov 0x10(%rsp),%r15\nmov 0x20(%rsp),%rdx\nmov 0x18(%rsp),%rdi\nmov %rax,(%rdx,%r15,8)\ncallq 10e0 \nlea 0x1(%r15),%rax\ncmp %r15,0x28(%rsp)\nje 1742 \nmov %rax,0x10(%rsp)\njmpq 1640 \nnopl 0x0(%rax)\ncmpb $0x0,0x40(%rsp)\njne 1730 \nmov $0x400,%edx\nmov %r15,%rsi\nmov %r14,%rdi\ncallq 10d0 <__strcat_chk@plt>\njmp 16c2 \nnopl 0x0(%rax)\nmov $0x400,%edx\nmov %rbp,%rsi\nmov %r14,%rdi\ncallq 10d0 <__strcat_chk@plt>\njmp 1717 \nmov 0x448(%rsp),%rax\nxor %fs:0x28,%rax\njne 176c \nmov 0x20(%rsp),%rax\nadd $0x458,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\ncallq 10f0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov r15d, ecx\npush r14\nmov r14, rdx\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nmovsxd rbx, esi\nmov r12, rbx\nshl rbx, 3\nmov rdi, rbx; size\nsub rsp, 448h\nmov [rsp+478h+var_474], ecx\nmov rax, fs:28h\nmov [rsp+478h+var_40], rax\nxor eax, eax\ncall _malloc\nmov [rsp+478h+var_450], rax\ntest r12d, r12d\njle loc_170B\nmov [rsp+478h+var_468], rax\nlea rax, [rbp+rbx+0]\nlea r13, [rsp+478h+s]\nmov [rsp+478h+var_458], rax\nmovsxd rax, r15d\nlea r12, delim; \" \"\nmov [rsp+478h+var_470], rbp\nlea rbp, [r14+rax*8]\nnop dword ptr [rax+00h]\nloc_1650:\nmov rax, [rsp+478h+var_470]\nmov rdi, [rax]; s\ncall _strdup\nmov ecx, 80h\nmov rdi, r13\nmov rsi, r12; delim\nmov rdx, rax\nmov [rsp+478h+ptr], rax\nxor eax, eax\nrep stosq\nmov rdi, rdx; s\ncall _strtok\nmov rbx, rax\ntest rax, rax\njz short loc_16CF\nnop dword ptr [rax]\nloc_1688:\nmov eax, [rsp+478h+var_474]\ntest eax, eax\njle loc_1738\nloc_1694:\nmov r15, r14\njmp short loc_16AD\nloc_16A0:\nadd r15, 8\ncmp rbp, r15\njz loc_1738\nloc_16AD:\nmov rsi, [r15]; needle\nmov rdi, rbx; haystack\ncall _strstr\ntest rax, rax\njz short loc_16A0\nmov rsi, r12; delim\nxor edi, edi; s\ncall _strtok\nmov rbx, rax\ntest rax, rax\njnz short loc_1694\nloc_16CF:\nmov rdi, r13; s\ncall _strdup\nmov rbx, [rsp+478h+var_468]\nmov rdi, [rsp+478h+ptr]; ptr\nmov [rbx], rax\nadd rbx, 8\ncall _free\nadd [rsp+478h+var_470], 8\nmov rcx, [rsp+478h+var_458]\nmov rax, [rsp+478h+var_470]\nmov [rsp+478h+var_468], rbx\ncmp rax, rcx\njnz loc_1650\nloc_170B:\nmov rax, [rsp+478h+var_40]\nsub rax, fs:28h\njnz short loc_1782\nmov rax, [rsp+478h+var_450]\nadd rsp, 448h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1738:\ncmp [rsp+478h+s], 0\njnz short loc_1770\nloc_173F:\nmov rsi, rbx\nmov edx, 400h\nmov rdi, r13\ncall ___strcat_chk\nmov rsi, r12; delim\nxor edi, edi; s\ncall _strtok\nmov rbx, rax\ntest rax, rax\njnz loc_1688\njmp loc_16CF\nloc_1770:\nmov edx, 400h\nmov rsi, r12\nmov rdi, r13\ncall ___strcat_chk\njmp short loc_173F\nloc_1782:\ncall ___stack_chk_fail", + "ida_pseudo": "_QWORD *__fastcall func0(const char **a1, int a2, const char **a3, int a4)\n{\n _QWORD *v6; // rax\n const char **v7; // rbp\n char *v8; // rbx\n const char **v9; // r15\n const char **v12; // [rsp+8h] [rbp-470h]\n char **v13; // [rsp+10h] [rbp-468h]\n char *ptr; // [rsp+18h] [rbp-460h]\n _QWORD *v15; // [rsp+28h] [rbp-450h]\n char s[1032]; // [rsp+30h] [rbp-448h] BYREF\n unsigned __int64 v17; // [rsp+438h] [rbp-40h]\n\n v17 = __readfsqword(0x28u);\n v6 = malloc(8LL * a2);\n v15 = v6;\n if ( a2 > 0 )\n {\n v13 = (char **)v6;\n v12 = a1;\n v7 = &a3[a4];\n do\n {\n ptr = strdup(*v12);\n memset(s, 0, 0x400uLL);\n v8 = strtok(ptr, \" \");\n if ( v8 )\n {\n while ( a4 <= 0 )\n {\nLABEL_11:\n if ( s[0] )\n __strcat_chk(s, \" \", 1024LL);\n __strcat_chk(s, v8, 1024LL);\n v8 = strtok(0LL, \" \");\n if ( !v8 )\n goto LABEL_9;\n }\n do\n {\n v9 = a3;\n while ( !strstr(v8, *v9) )\n {\n if ( v7 == ++v9 )\n goto LABEL_11;\n }\n v8 = strtok(0LL, \" \");\n }\n while ( v8 );\n }\nLABEL_9:\n *v13 = strdup(s);\n free(ptr);\n ++v12;\n ++v13;\n }\n while ( v12 != &a1[a2] );\n }\n return v15;\n}", + "ida_strip_asm": "sub_15D0:\nendbr64\npush r15\nmov r15d, ecx\npush r14\nmov r14, rdx\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nmovsxd rbx, esi\nmov r12, rbx\nshl rbx, 3\nmov rdi, rbx; size\nsub rsp, 448h\nmov [rsp+478h+var_474], ecx\nmov rax, fs:28h\nmov [rsp+478h+var_40], rax\nxor eax, eax\ncall _malloc\nmov [rsp+478h+var_450], rax\ntest r12d, r12d\njle loc_170B\nmov [rsp+478h+var_468], rax\nlea rax, [rbp+rbx+0]\nlea r13, [rsp+478h+s]\nmov [rsp+478h+var_458], rax\nmovsxd rax, r15d\nlea r12, delim; \" \"\nmov [rsp+478h+var_470], rbp\nlea rbp, [r14+rax*8]\nnop dword ptr [rax+00h]\nloc_1650:\nmov rax, [rsp+478h+var_470]\nmov rdi, [rax]; s\ncall _strdup\nmov ecx, 80h\nmov rdi, r13\nmov rsi, r12; delim\nmov rdx, rax\nmov [rsp+478h+ptr], rax\nxor eax, eax\nrep stosq\nmov rdi, rdx; s\ncall _strtok\nmov rbx, rax\ntest rax, rax\njz short loc_16CF\nnop dword ptr [rax]\nloc_1688:\nmov eax, [rsp+478h+var_474]\ntest eax, eax\njle loc_1738\nloc_1694:\nmov r15, r14\njmp short loc_16AD\nloc_16A0:\nadd r15, 8\ncmp rbp, r15\njz loc_1738\nloc_16AD:\nmov rsi, [r15]; needle\nmov rdi, rbx; haystack\ncall _strstr\ntest rax, rax\njz short loc_16A0\nmov rsi, r12; delim\nxor edi, edi; s\ncall _strtok\nmov rbx, rax\ntest rax, rax\njnz short loc_1694\nloc_16CF:\nmov rdi, r13; s\ncall _strdup\nmov rbx, [rsp+478h+var_468]\nmov rdi, [rsp+478h+ptr]; ptr\nmov [rbx], rax\nadd rbx, 8\ncall _free\nadd [rsp+478h+var_470], 8\nmov rcx, [rsp+478h+var_458]\nmov rax, [rsp+478h+var_470]\nmov [rsp+478h+var_468], rbx\ncmp rax, rcx\njnz loc_1650\nloc_170B:\nmov rax, [rsp+478h+var_40]\nsub rax, fs:28h\njnz short loc_1782\nmov rax, [rsp+478h+var_450]\nadd rsp, 448h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1738:\ncmp [rsp+478h+s], 0\njnz short loc_1770\nloc_173F:\nmov rsi, rbx\nmov edx, 400h\nmov rdi, r13\ncall ___strcat_chk\nmov rsi, r12; delim\nxor edi, edi; s\ncall _strtok\nmov rbx, rax\ntest rax, rax\njnz loc_1688\njmp loc_16CF\nloc_1770:\nmov edx, 400h\nmov rsi, r12\nmov rdi, r13\ncall ___strcat_chk\njmp short loc_173F\nloc_1782:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_QWORD *__fastcall sub_15D0(const char **a1, int a2, const char **a3, int a4)\n{\n _QWORD *v6; // rax\n const char **v7; // rbp\n char *v8; // rbx\n const char **v9; // r15\n const char **v12; // [rsp+8h] [rbp-470h]\n char **v13; // [rsp+10h] [rbp-468h]\n char *ptr; // [rsp+18h] [rbp-460h]\n _QWORD *v15; // [rsp+28h] [rbp-450h]\n char s[1032]; // [rsp+30h] [rbp-448h] BYREF\n unsigned __int64 v17; // [rsp+438h] [rbp-40h]\n\n v17 = __readfsqword(0x28u);\n v6 = malloc(8LL * a2);\n v15 = v6;\n if ( a2 > 0 )\n {\n v13 = (char **)v6;\n v12 = a1;\n v7 = &a3[a4];\n do\n {\n ptr = strdup(*v12);\n memset(s, 0, 0x400uLL);\n v8 = strtok(ptr, \" \");\n if ( v8 )\n {\n while ( a4 <= 0 )\n {\nLABEL_11:\n if ( s[0] )\n __strcat_chk(s, \" \", 1024LL);\n __strcat_chk(s, v8, 1024LL);\n v8 = strtok(0LL, \" \");\n if ( !v8 )\n goto LABEL_9;\n }\n do\n {\n v9 = a3;\n while ( !strstr(v8, *v9) )\n {\n if ( v7 == ++v9 )\n goto LABEL_11;\n }\n v8 = strtok(0LL, \" \");\n }\n while ( v8 );\n }\nLABEL_9:\n *v13 = strdup(s);\n free(ptr);\n ++v12;\n ++v13;\n }\n while ( v12 != &a1[a2] );\n }\n return v15;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_15D0(const char **a1, int a2, const char **a3, int a4) {\n uint64_t *v6;\n const char **v7;\n char *v8;\n const char **v9;\n const char **v12;\n char **v13;\n char *ptr;\n uint64_t *v15;\n char s[1032];\n unsigned long long v17;\n v17 = __readfsqword(40u);\n v6 = malloc(8LL * a2);\n v15 = v6;\n if (a2 > 0) {\n v13 = (char **)v6;\n v12 = a1;\n v7 = &a3[a4];\n do {\n ptr = strdup(*v12);\n memset(s, 0, 1024uLL);\n v8 = strtok(ptr, \" \");\n if (v8) {\n while (a4 <= 0) {\n LABEL_11:\n if (s[0]) __strcat_chk(s, \" \", 1024LL);\n __strcat_chk(s, v8, 1024LL);\n v8 = strtok(0LL, \" \");\n if (!v8) goto LABEL_9;\n }\n do {\n v9 = a3;\n while (!strstr(v8, *v9)) {\n if (v7 == ++v9) goto LABEL_11;\n }\n v8 = strtok(0LL, \" \");\n } while (v8);\n }\n LABEL_9:\n *v13 = strdup(s);\n free(ptr);\n ++v12;\n ++v13;\n } while (v12 != &a1[a2]);\n }\n return v15;\n}", + "ida_pseudo_norm": "uint64_t *func0(const char **a1, int a2, const char **a3, int a4) {\n uint64_t *v6;\n const char **v7;\n char *v8;\n const char **v9;\n const char **v12;\n char **v13;\n char *ptr;\n uint64_t *v15;\n char s[1032];\n unsigned long long v17;\n v17 = __readfsqword(40u);\n v6 = malloc(8LL * a2);\n v15 = v6;\n if (a2 > 0) {\n v13 = (char **)v6;\n v12 = a1;\n v7 = &a3[a4];\n do {\n ptr = strdup(*v12);\n memset(s, 0, 1024uLL);\n v8 = strtok(ptr, \" \");\n if (v8) {\n while (a4 <= 0) {\n LABEL_11:\n if (s[0]) __strcat_chk(s, \" \", 1024LL);\n __strcat_chk(s, v8, 1024LL);\n v8 = strtok(0LL, \" \");\n if (!v8) goto LABEL_9;\n }\n do {\n v9 = a3;\n while (!strstr(v8, *v9)) {\n if (v7 == ++v9) goto LABEL_11;\n }\n v8 = strtok(0LL, \" \");\n } while (v8);\n }\n LABEL_9:\n *v13 = strdup(s);\n free(ptr);\n ++v12;\n ++v13;\n } while (v12 != &a1[a2]);\n }\n return v15;\n}" + }, + { + "index": 570, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(char* list1[], int n1, char* charlist[], int n_char) {\n char** new_list = malloc(n1 * sizeof(char*));\n for (int i = 0; i < n1; i++) {\n char* line = strdup(list1[i]);\n char* token;\n char buffer[1024] = \"\";\n token = strtok(line, \" \");\n while (token != NULL) {\n int skip = 0;\n for (int j = 0; j < n_char; j++) {\n if (strstr(token, charlist[j]) != NULL) {\n skip = 1;\n break;\n }\n }\n if (!skip) {\n if (strlen(buffer) > 0) strcat(buffer, \" \");\n strcat(buffer, token);\n }\n token = strtok(NULL, \" \");\n }\n new_list[i] = strdup(buffer);\n free(line);\n }\n return new_list;\n}", + "test": "int main() {\n\n // Test case 1\n\n char* list1_a[] = {\"Red color\", \"Orange#\", \"Green\", \"Orange @\", \"White\"};\n\n char* charlist_a[] = {\"#\", \"color\", \"@\"};\n\n char* expected_a[] = {\"Red\", \"\", \"Green\", \"Orange\", \"White\"};\n\n char** result_a = func0(list1_a, 5, charlist_a, 3);\n\n for(int i = 0; i < 5; i++) {\n\n assert(strcmp(result_a[i], expected_a[i]) == 0);\n\n free(result_a[i]);\n\n }\n\n free(result_a);\n\n\n\n // Test case 2\n\n char* list1_b[] = {\"Red &\", \"Orange+\", \"Green\", \"Orange @\", \"White\"};\n\n char* charlist_b[] = {\"&\", \"+\", \"@\"};\n\n char* expected_b[] = {\"Red\", \"\", \"Green\", \"Orange\", \"White\"};\n\n char** result_b = func0(list1_b, 5, charlist_b, 3);\n\n for(int i = 0; i < 5; i++) {\n\n assert(strcmp(result_b[i], expected_b[i]) == 0);\n\n free(result_b[i]);\n\n }\n\n free(result_b);\n\n\n\n // Test case 3\n\n char* list1_c[] = {\"Red &\", \"Orange+\", \"Green\", \"Orange @\", \"White\"};\n\n char* charlist_c[] = {\"@\"};\n\n char* expected_c[] = {\"Red &\", \"Orange+\", \"Green\", \"Orange\", \"White\"};\n\n char** result_c = func0(list1_c, 5, charlist_c, 1);\n\n for(int i = 0; i < 5; i++) {\n\n assert(strcmp(result_c[i], expected_c[i]) == 0);\n\n free(result_c[i]);\n\n }\n\n free(result_c);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\nmov %rdx,%r14\npush %r13\nmov %ecx,%r13d\npush %r12\npush %rbp\npush %rbx\nsub $0x458,%rsp\nmov %rdi,0x30(%rsp)\nmovslq %esi,%rdi\nmov %rdx,0x8(%rsp)\nmov %rdi,%rbx\nshl $0x3,%rdi\nmov %fs:0x28,%rax\nmov %rax,0x448(%rsp)\nxor %eax,%eax\ncallq 1120 \nmov %rax,0x20(%rsp)\ntest %ebx,%ebx\njle 1752 \nmovq $0x0,0x10(%rsp)\nlea -0x1(%rbx),%eax\nmov 0x10(%rsp),%rdx\nmov %rax,0x28(%rsp)\nlea -0x1(%r13),%eax\nlea 0x8(%r14,%rax,8),%rbx\nlea 0x50(%rsp),%rax\nmov %rax,0x38(%rsp)\nlea 0x40(%rsp),%r14\nnopw 0x0(%rax,%rax,1)\nmov 0x30(%rsp),%rax\nlea 0x9a0(%rip),%rbp\nmov (%rax,%rdx,8),%rdi\ncallq 1140 \nmov 0x38(%rsp),%rdi\npxor %xmm0,%xmm0\nmov $0x7e,%ecx\nmov %rax,%rdx\nmov %rax,0x18(%rsp)\nxor %eax,%eax\nlea 0x978(%rip),%rsi\nrep stos %rax,%es:(%rdi)\nmov %rdx,%rdi\nmovaps %xmm0,0x40(%rsp)\ncallq 1130 \nmov %rax,%r15\ntest %rax,%rax\nje 16e4 \nnopl 0x0(%rax)\nmov 0x8(%rsp),%r12\ntest %r13d,%r13d\njg 16c1 \njmp 1720 \nnopl 0x0(%rax)\nadd $0x8,%r12\ncmp %r12,%rbx\nje 1720 \nmov (%r12),%rsi\nmov %r15,%rdi\ncallq 1150 \ntest %rax,%rax\nje 16b8 \nmov %rbp,%rsi\nxor %edi,%edi\ncallq 1130 \nmov %rax,%r15\ntest %rax,%rax\njne 16a8 \nmov %r14,%rdi\ncallq 1140 \nmov 0x10(%rsp),%r15\nmov 0x20(%rsp),%rdx\nmov 0x18(%rsp),%rdi\nmov %rax,(%rdx,%r15,8)\ncallq 10e0 \nlea 0x1(%r15),%rax\ncmp 0x28(%rsp),%r15\nje 1752 \nmov %rax,0x10(%rsp)\nmov %rax,%rdx\njmpq 1658 \nnopl 0x0(%rax)\ncmpb $0x0,0x40(%rsp)\njne 1740 \nmov $0x400,%edx\nmov %r15,%rsi\nmov %r14,%rdi\ncallq 10d0 <__strcat_chk@plt>\njmp 16d2 \nnopl 0x0(%rax)\nmov $0x400,%edx\nmov %rbp,%rsi\nmov %r14,%rdi\ncallq 10d0 <__strcat_chk@plt>\njmp 1727 \nmov 0x448(%rsp),%rax\nxor %fs:0x28,%rax\njne 177c \nmov 0x20(%rsp),%rax\nadd $0x458,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\ncallq 10f0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov r15d, ecx\npush r14\nmov r14, rdx\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nmovsxd rbx, esi\nmov r12, rbx\nshl rbx, 3\nmov rdi, rbx; size\nsub rsp, 448h\nmov [rsp+478h+var_474], ecx\nmov rax, fs:28h\nmov [rsp+478h+var_40], rax\nxor eax, eax\ncall _malloc\nmov [rsp+478h+var_450], rax\ntest r12d, r12d\njle loc_170B\nmov [rsp+478h+var_468], rax\nlea rax, [rbp+rbx+0]\nlea r13, [rsp+478h+s]\nmov [rsp+478h+var_458], rax\nmovsxd rax, r15d\nlea r12, delim; \" \"\nmov [rsp+478h+var_470], rbp\nlea rbp, [r14+rax*8]\nnop dword ptr [rax+00h]\nloc_1650:\nmov rax, [rsp+478h+var_470]\nmov rdi, [rax]; s\ncall _strdup\nmov ecx, 80h\nmov rdi, r13\nmov rsi, r12; delim\nmov rdx, rax\nmov [rsp+478h+ptr], rax\nxor eax, eax\nrep stosq\nmov rdi, rdx; s\ncall _strtok\nmov rbx, rax\ntest rax, rax\njz short loc_16CF\nnop dword ptr [rax]\nloc_1688:\nmov eax, [rsp+478h+var_474]\ntest eax, eax\njle loc_1738\nloc_1694:\nmov r15, r14\njmp short loc_16AD\nloc_16A0:\nadd r15, 8\ncmp rbp, r15\njz loc_1738\nloc_16AD:\nmov rsi, [r15]; needle\nmov rdi, rbx; haystack\ncall _strstr\ntest rax, rax\njz short loc_16A0\nmov rsi, r12; delim\nxor edi, edi; s\ncall _strtok\nmov rbx, rax\ntest rax, rax\njnz short loc_1694\nloc_16CF:\nmov rdi, r13; s\ncall _strdup\nmov rbx, [rsp+478h+var_468]\nmov rdi, [rsp+478h+ptr]; ptr\nmov [rbx], rax\nadd rbx, 8\ncall _free\nadd [rsp+478h+var_470], 8\nmov rcx, [rsp+478h+var_458]\nmov rax, [rsp+478h+var_470]\nmov [rsp+478h+var_468], rbx\ncmp rax, rcx\njnz loc_1650\nloc_170B:\nmov rax, [rsp+478h+var_40]\nsub rax, fs:28h\njnz short loc_1782\nmov rax, [rsp+478h+var_450]\nadd rsp, 448h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1738:\ncmp [rsp+478h+s], 0\njnz short loc_1770\nloc_173F:\nmov rsi, rbx\nmov edx, 400h\nmov rdi, r13\ncall ___strcat_chk\nmov rsi, r12; delim\nxor edi, edi; s\ncall _strtok\nmov rbx, rax\ntest rax, rax\njnz loc_1688\njmp loc_16CF\nloc_1770:\nmov edx, 400h\nmov rsi, r12\nmov rdi, r13\ncall ___strcat_chk\njmp short loc_173F\nloc_1782:\ncall ___stack_chk_fail", + "ida_pseudo": "_QWORD *__fastcall func0(const char **a1, int a2, const char **a3, int a4)\n{\n _QWORD *v6; // rax\n const char **v7; // rbp\n char *v8; // rbx\n const char **v9; // r15\n const char **v12; // [rsp+8h] [rbp-470h]\n char **v13; // [rsp+10h] [rbp-468h]\n char *ptr; // [rsp+18h] [rbp-460h]\n _QWORD *v15; // [rsp+28h] [rbp-450h]\n char s[1032]; // [rsp+30h] [rbp-448h] BYREF\n unsigned __int64 v17; // [rsp+438h] [rbp-40h]\n\n v17 = __readfsqword(0x28u);\n v6 = malloc(8LL * a2);\n v15 = v6;\n if ( a2 > 0 )\n {\n v13 = (char **)v6;\n v12 = a1;\n v7 = &a3[a4];\n do\n {\n ptr = strdup(*v12);\n memset(s, 0, 0x400uLL);\n v8 = strtok(ptr, \" \");\n if ( v8 )\n {\n while ( a4 <= 0 )\n {\nLABEL_11:\n if ( s[0] )\n __strcat_chk(s, \" \", 1024LL);\n __strcat_chk(s, v8, 1024LL);\n v8 = strtok(0LL, \" \");\n if ( !v8 )\n goto LABEL_9;\n }\n do\n {\n v9 = a3;\n while ( !strstr(v8, *v9) )\n {\n if ( v7 == ++v9 )\n goto LABEL_11;\n }\n v8 = strtok(0LL, \" \");\n }\n while ( v8 );\n }\nLABEL_9:\n *v13 = strdup(s);\n free(ptr);\n ++v12;\n ++v13;\n }\n while ( v12 != &a1[a2] );\n }\n return v15;\n}", + "ida_strip_asm": "sub_15D0:\nendbr64\npush r15\nmov r15d, ecx\npush r14\nmov r14, rdx\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nmovsxd rbx, esi\nmov r12, rbx\nshl rbx, 3\nmov rdi, rbx; size\nsub rsp, 448h\nmov [rsp+478h+var_474], ecx\nmov rax, fs:28h\nmov [rsp+478h+var_40], rax\nxor eax, eax\ncall _malloc\nmov [rsp+478h+var_450], rax\ntest r12d, r12d\njle loc_170B\nmov [rsp+478h+var_468], rax\nlea rax, [rbp+rbx+0]\nlea r13, [rsp+478h+s]\nmov [rsp+478h+var_458], rax\nmovsxd rax, r15d\nlea r12, delim; \" \"\nmov [rsp+478h+var_470], rbp\nlea rbp, [r14+rax*8]\nnop dword ptr [rax+00h]\nloc_1650:\nmov rax, [rsp+478h+var_470]\nmov rdi, [rax]; s\ncall _strdup\nmov ecx, 80h\nmov rdi, r13\nmov rsi, r12; delim\nmov rdx, rax\nmov [rsp+478h+ptr], rax\nxor eax, eax\nrep stosq\nmov rdi, rdx; s\ncall _strtok\nmov rbx, rax\ntest rax, rax\njz short loc_16CF\nnop dword ptr [rax]\nloc_1688:\nmov eax, [rsp+478h+var_474]\ntest eax, eax\njle loc_1738\nloc_1694:\nmov r15, r14\njmp short loc_16AD\nloc_16A0:\nadd r15, 8\ncmp rbp, r15\njz loc_1738\nloc_16AD:\nmov rsi, [r15]; needle\nmov rdi, rbx; haystack\ncall _strstr\ntest rax, rax\njz short loc_16A0\nmov rsi, r12; delim\nxor edi, edi; s\ncall _strtok\nmov rbx, rax\ntest rax, rax\njnz short loc_1694\nloc_16CF:\nmov rdi, r13; s\ncall _strdup\nmov rbx, [rsp+478h+var_468]\nmov rdi, [rsp+478h+ptr]; ptr\nmov [rbx], rax\nadd rbx, 8\ncall _free\nadd [rsp+478h+var_470], 8\nmov rcx, [rsp+478h+var_458]\nmov rax, [rsp+478h+var_470]\nmov [rsp+478h+var_468], rbx\ncmp rax, rcx\njnz loc_1650\nloc_170B:\nmov rax, [rsp+478h+var_40]\nsub rax, fs:28h\njnz short loc_1782\nmov rax, [rsp+478h+var_450]\nadd rsp, 448h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1738:\ncmp [rsp+478h+s], 0\njnz short loc_1770\nloc_173F:\nmov rsi, rbx\nmov edx, 400h\nmov rdi, r13\ncall ___strcat_chk\nmov rsi, r12; delim\nxor edi, edi; s\ncall _strtok\nmov rbx, rax\ntest rax, rax\njnz loc_1688\njmp loc_16CF\nloc_1770:\nmov edx, 400h\nmov rsi, r12\nmov rdi, r13\ncall ___strcat_chk\njmp short loc_173F\nloc_1782:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_QWORD *__fastcall sub_15D0(const char **a1, int a2, const char **a3, int a4)\n{\n _QWORD *v6; // rax\n const char **v7; // rbp\n char *v8; // rbx\n const char **v9; // r15\n const char **v12; // [rsp+8h] [rbp-470h]\n char **v13; // [rsp+10h] [rbp-468h]\n char *ptr; // [rsp+18h] [rbp-460h]\n _QWORD *v15; // [rsp+28h] [rbp-450h]\n char s[1032]; // [rsp+30h] [rbp-448h] BYREF\n unsigned __int64 v17; // [rsp+438h] [rbp-40h]\n\n v17 = __readfsqword(0x28u);\n v6 = malloc(8LL * a2);\n v15 = v6;\n if ( a2 > 0 )\n {\n v13 = (char **)v6;\n v12 = a1;\n v7 = &a3[a4];\n do\n {\n ptr = strdup(*v12);\n memset(s, 0, 0x400uLL);\n v8 = strtok(ptr, \" \");\n if ( v8 )\n {\n while ( a4 <= 0 )\n {\nLABEL_11:\n if ( s[0] )\n __strcat_chk(s, \" \", 1024LL);\n __strcat_chk(s, v8, 1024LL);\n v8 = strtok(0LL, \" \");\n if ( !v8 )\n goto LABEL_9;\n }\n do\n {\n v9 = a3;\n while ( !strstr(v8, *v9) )\n {\n if ( v7 == ++v9 )\n goto LABEL_11;\n }\n v8 = strtok(0LL, \" \");\n }\n while ( v8 );\n }\nLABEL_9:\n *v13 = strdup(s);\n free(ptr);\n ++v12;\n ++v13;\n }\n while ( v12 != &a1[a2] );\n }\n return v15;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_15D0(const char **a1, int a2, const char **a3, int a4) {\n uint64_t *v6;\n const char **v7;\n char *v8;\n const char **v9;\n const char **v12;\n char **v13;\n char *ptr;\n uint64_t *v15;\n char s[1032];\n unsigned long long v17;\n v17 = __readfsqword(40u);\n v6 = malloc(8LL * a2);\n v15 = v6;\n if (a2 > 0) {\n v13 = (char **)v6;\n v12 = a1;\n v7 = &a3[a4];\n do {\n ptr = strdup(*v12);\n memset(s, 0, 1024uLL);\n v8 = strtok(ptr, \" \");\n if (v8) {\n while (a4 <= 0) {\n LABEL_11:\n if (s[0]) __strcat_chk(s, \" \", 1024LL);\n __strcat_chk(s, v8, 1024LL);\n v8 = strtok(0LL, \" \");\n if (!v8) goto LABEL_9;\n }\n do {\n v9 = a3;\n while (!strstr(v8, *v9)) {\n if (v7 == ++v9) goto LABEL_11;\n }\n v8 = strtok(0LL, \" \");\n } while (v8);\n }\n LABEL_9:\n *v13 = strdup(s);\n free(ptr);\n ++v12;\n ++v13;\n } while (v12 != &a1[a2]);\n }\n return v15;\n}", + "ida_pseudo_norm": "uint64_t *func0(const char **a1, int a2, const char **a3, int a4) {\n uint64_t *v6;\n const char **v7;\n char *v8;\n const char **v9;\n const char **v12;\n char **v13;\n char *ptr;\n uint64_t *v15;\n char s[1032];\n unsigned long long v17;\n v17 = __readfsqword(40u);\n v6 = malloc(8LL * a2);\n v15 = v6;\n if (a2 > 0) {\n v13 = (char **)v6;\n v12 = a1;\n v7 = &a3[a4];\n do {\n ptr = strdup(*v12);\n memset(s, 0, 1024uLL);\n v8 = strtok(ptr, \" \");\n if (v8) {\n while (a4 <= 0) {\n LABEL_11:\n if (s[0]) __strcat_chk(s, \" \", 1024LL);\n __strcat_chk(s, v8, 1024LL);\n v8 = strtok(0LL, \" \");\n if (!v8) goto LABEL_9;\n }\n do {\n v9 = a3;\n while (!strstr(v8, *v9)) {\n if (v7 == ++v9) goto LABEL_11;\n }\n v8 = strtok(0LL, \" \");\n } while (v8);\n }\n LABEL_9:\n *v13 = strdup(s);\n free(ptr);\n ++v12;\n ++v13;\n } while (v12 != &a1[a2]);\n }\n return v15;\n}" + }, + { + "index": 571, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint cmpfunc(const void *a, const void *b) {\n\n return (*(int*)a - *(int*)b);\n\n}\n\n\n\n", + "func": "int func0(int arr[], int N, int K) {\n qsort(arr, N, sizeof(int), cmpfunc);\n int *dp = (int *)malloc(N * sizeof(int));\n dp[0] = 0;\n for (int i = 1; i < N; i++) {\n dp[i] = dp[i - 1];\n if (arr[i] - arr[i - 1] < K) {\n if (i >= 2) {\n dp[i] = (dp[i] > (dp[i - 2] + arr[i] + arr[i - 1]))\n ? dp[i]\n : (dp[i - 2] + arr[i] + arr[i - 1]);\n } else {\n dp[i] = (dp[i] > (arr[i] + arr[i - 1])) ? dp[i] : (arr[i] + arr[i - 1]);\n }\n }\n }\n int result = dp[N - 1];\n free(dp);\n return result;\n}", + "test": "int main() {\n\n int arr1[] = {3, 5, 10, 15, 17, 12, 9};\n\n int arr2[] = {5, 15, 10, 300};\n\n int arr3[] = {1, 2, 3, 4, 5, 6};\n\n\n\n assert(func0(arr1, 7, 4) == 62);\n\n assert(func0(arr2, 4, 12) == 25);\n\n assert(func0(arr3, 6, 6) == 21);\n\n\n\n printf(\"All assertions passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmov -0x1c(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x18(%rbp),%rax\nlea -0x49(%rip),%rcx\nmov $0x4,%edx\nmov %rax,%rdi\ncallq 10c0 \nmov -0x1c(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10f0 \nmov %rax,-0x8(%rbp)\nmov -0x8(%rbp),%rax\nmovl $0x0,(%rax)\nmovl $0x1,-0x10(%rbp)\njmpq 13b4 \nmov -0x10(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov -0x10(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x10(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\nsub %eax,%edx\nmov %edx,%eax\ncmp %eax,-0x20(%rbp)\njle 13b0 \ncmpl $0x1,-0x10(%rbp)\njle 1350 \nmov -0x10(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x8(%rax),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\nadd %eax,%edx\nmov -0x10(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\nadd %eax,%edx\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x8(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\nmov -0x10(%rbp),%ecx\nmovslq %ecx,%rcx\nlea 0x0(,%rcx,4),%rsi\nmov -0x8(%rbp),%rcx\nadd %rsi,%rcx\ncmp %eax,%edx\ncmovge %edx,%eax\nmov %eax,(%rcx)\njmp 13b0 \nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x10(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\nadd %eax,%edx\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x8(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\nmov -0x10(%rbp),%ecx\nmovslq %ecx,%rcx\nlea 0x0(,%rcx,4),%rsi\nmov -0x8(%rbp),%rcx\nadd %rsi,%rcx\ncmp %eax,%edx\ncmovge %edx,%eax\nmov %eax,(%rcx)\naddl $0x1,-0x10(%rbp)\nmov -0x10(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 126a \nmov -0x1c(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0xc(%rbp)\nmov -0x8(%rbp),%rax\nmov %rax,%rdi\ncallq 10a0 \nmov -0xc(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+base], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov eax, [rbp+var_1C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, cmpfunc\nmov rcx, rdx; compar\nmov edx, 4; size\nmov rdi, rax; base\ncall _qsort\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov rax, [rbp+ptr]\nmov dword ptr [rax], 0\nmov [rbp+var_10], 1\njmp loc_13B5\nloc_126D:\nmov eax, [rbp+var_10]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+ptr]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nshl rax, 2\nlea rcx, [rax-4]\nmov rax, [rbp+base]\nadd rax, rcx\nmov eax, [rax]\nsub edx, eax\ncmp [rbp+var_20], edx\njle loc_13B1\ncmp [rbp+var_10], 1\njle short loc_1351\nmov eax, [rbp+var_10]\ncdqe\nshl rax, 2\nlea rdx, [rax-8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rcx\nmov eax, [rax]\nadd edx, eax\nmov eax, [rbp+var_10]\ncdqe\nshl rax, 2\nlea rcx, [rax-4]\nmov rax, [rbp+base]\nadd rax, rcx\nmov eax, [rax]\nadd edx, eax\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rcx\nmov eax, [rax]\nmov ecx, [rbp+var_10]\nmovsxd rcx, ecx\nlea rsi, ds:0[rcx*4]\nmov rcx, [rbp+ptr]\nadd rcx, rsi\ncmp edx, eax\ncmovge eax, edx\nmov [rcx], eax\njmp short loc_13B1\nloc_1351:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nshl rax, 2\nlea rcx, [rax-4]\nmov rax, [rbp+base]\nadd rax, rcx\nmov eax, [rax]\nadd edx, eax\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rcx\nmov eax, [rax]\nmov ecx, [rbp+var_10]\nmovsxd rcx, ecx\nlea rsi, ds:0[rcx*4]\nmov rcx, [rbp+ptr]\nadd rcx, rsi\ncmp edx, eax\ncmovge eax, edx\nmov [rcx], eax\nloc_13B1:\nadd [rbp+var_10], 1\nloc_13B5:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_1C]\njl loc_126D\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov eax, [rbp+var_C]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(void *a1, int a2, int a3)\n{\n int v3; // eax\n int v4; // eax\n int i; // [rsp+10h] [rbp-10h]\n unsigned int v8; // [rsp+14h] [rbp-Ch]\n _DWORD *ptr; // [rsp+18h] [rbp-8h]\n\n qsort(a1, a2, 4uLL, cmpfunc);\n ptr = malloc(4LL * a2);\n *ptr = 0;\n for ( i = 1; i < a2; ++i )\n {\n ptr[i] = ptr[i - 1];\n if ( a3 > *((_DWORD *)a1 + i) - *((_DWORD *)a1 + i - 1) )\n {\n if ( i <= 1 )\n {\n v4 = ptr[i];\n if ( *((_DWORD *)a1 + i - 1) + *((_DWORD *)a1 + i) >= v4 )\n v4 = *((_DWORD *)a1 + i - 1) + *((_DWORD *)a1 + i);\n ptr[i] = v4;\n }\n else\n {\n v3 = ptr[i];\n if ( *((_DWORD *)a1 + i - 1) + *((_DWORD *)a1 + i) + ptr[i - 2] >= v3 )\n v3 = *((_DWORD *)a1 + i - 1) + *((_DWORD *)a1 + i) + ptr[i - 2];\n ptr[i] = v3;\n }\n }\n }\n v8 = ptr[a2 - 1];\n free(ptr);\n return v8;\n}", + "ida_strip_asm": "sub_120B:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+base], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov eax, [rbp+var_1C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 4; size\nmov rdi, rax; base\ncall _qsort\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov rax, [rbp+ptr]\nmov dword ptr [rax], 0\nmov [rbp+var_10], 1\njmp loc_13B5\nloc_126D:\nmov eax, [rbp+var_10]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+ptr]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nshl rax, 2\nlea rcx, [rax-4]\nmov rax, [rbp+base]\nadd rax, rcx\nmov eax, [rax]\nsub edx, eax\ncmp [rbp+var_20], edx\njle loc_13B1\ncmp [rbp+var_10], 1\njle short loc_1351\nmov eax, [rbp+var_10]\ncdqe\nshl rax, 2\nlea rdx, [rax-8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rcx\nmov eax, [rax]\nadd edx, eax\nmov eax, [rbp+var_10]\ncdqe\nshl rax, 2\nlea rcx, [rax-4]\nmov rax, [rbp+base]\nadd rax, rcx\nmov eax, [rax]\nadd edx, eax\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rcx\nmov eax, [rax]\nmov ecx, [rbp+var_10]\nmovsxd rcx, ecx\nlea rsi, ds:0[rcx*4]\nmov rcx, [rbp+ptr]\nadd rcx, rsi\ncmp edx, eax\ncmovge eax, edx\nmov [rcx], eax\njmp short loc_13B1\nloc_1351:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nshl rax, 2\nlea rcx, [rax-4]\nmov rax, [rbp+base]\nadd rax, rcx\nmov eax, [rax]\nadd edx, eax\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rcx\nmov eax, [rax]\nmov ecx, [rbp+var_10]\nmovsxd rcx, ecx\nlea rsi, ds:0[rcx*4]\nmov rcx, [rbp+ptr]\nadd rcx, rsi\ncmp edx, eax\ncmovge eax, edx\nmov [rcx], eax\nloc_13B1:\nadd [rbp+var_10], 1\nloc_13B5:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_1C]\njl loc_126D\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov eax, [rbp+var_C]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_120B(void *a1, int a2, int a3)\n{\n int v3; // eax\n int v4; // eax\n int i; // [rsp+10h] [rbp-10h]\n unsigned int v8; // [rsp+14h] [rbp-Ch]\n _DWORD *ptr; // [rsp+18h] [rbp-8h]\n\n qsort(a1, a2, 4uLL, compar);\n ptr = malloc(4LL * a2);\n *ptr = 0;\n for ( i = 1; i < a2; ++i )\n {\n ptr[i] = ptr[i - 1];\n if ( a3 > *((_DWORD *)a1 + i) - *((_DWORD *)a1 + i - 1) )\n {\n if ( i <= 1 )\n {\n v4 = ptr[i];\n if ( *((_DWORD *)a1 + i - 1) + *((_DWORD *)a1 + i) >= v4 )\n v4 = *((_DWORD *)a1 + i - 1) + *((_DWORD *)a1 + i);\n ptr[i] = v4;\n }\n else\n {\n v3 = ptr[i];\n if ( *((_DWORD *)a1 + i - 1) + *((_DWORD *)a1 + i) + ptr[i - 2] >= v3 )\n v3 = *((_DWORD *)a1 + i - 1) + *((_DWORD *)a1 + i) + ptr[i - 2];\n ptr[i] = v3;\n }\n }\n }\n v8 = ptr[a2 - 1];\n free(ptr);\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_120B(void *a1, int a2, int a3) {\n int v3;\n int v4;\n int i;\n unsigned int v8;\n uint32_t *ptr;\n qsort(a1, a2, 4uLL, compar);\n ptr = malloc(4LL * a2);\n *ptr = 0;\n for (i = 1; i < a2; ++i) {\n ptr[i] = ptr[i - 1];\n if (a3 > *((uint32_t *)a1 + i) - *((uint32_t *)a1 + i - 1)) {\n if (i <= 1) {\n v4 = ptr[i];\n if (*((uint32_t *)a1 + i - 1) + *((uint32_t *)a1 + i) >= v4)\n v4 = *((uint32_t *)a1 + i - 1) + *((uint32_t *)a1 + i);\n ptr[i] = v4;\n } else {\n v3 = ptr[i];\n if (*((uint32_t *)a1 + i - 1) + *((uint32_t *)a1 + i) + ptr[i - 2] >=\n v3)\n v3 = *((uint32_t *)a1 + i - 1) + *((uint32_t *)a1 + i) + ptr[i - 2];\n ptr[i] = v3;\n }\n }\n }\n v8 = ptr[a2 - 1];\n free(ptr);\n return v8;\n}", + "ida_pseudo_norm": "long long func0(void *a1, int a2, int a3) {\n int v3;\n int v4;\n int i;\n unsigned int v8;\n uint32_t *ptr;\n qsort(a1, a2, 4uLL, cmpfunc);\n ptr = malloc(4LL * a2);\n *ptr = 0;\n for (i = 1; i < a2; ++i) {\n ptr[i] = ptr[i - 1];\n if (a3 > *((uint32_t *)a1 + i) - *((uint32_t *)a1 + i - 1)) {\n if (i <= 1) {\n v4 = ptr[i];\n if (*((uint32_t *)a1 + i - 1) + *((uint32_t *)a1 + i) >= v4)\n v4 = *((uint32_t *)a1 + i - 1) + *((uint32_t *)a1 + i);\n ptr[i] = v4;\n } else {\n v3 = ptr[i];\n if (*((uint32_t *)a1 + i - 1) + *((uint32_t *)a1 + i) + ptr[i - 2] >=\n v3)\n v3 = *((uint32_t *)a1 + i - 1) + *((uint32_t *)a1 + i) + ptr[i - 2];\n ptr[i] = v3;\n }\n }\n }\n v8 = ptr[a2 - 1];\n free(ptr);\n return v8;\n}" + }, + { + "index": 571, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint cmpfunc(const void *a, const void *b) {\n\n return (*(int*)a - *(int*)b);\n\n}\n\n\n\n", + "func": "int func0(int arr[], int N, int K) {\n qsort(arr, N, sizeof(int), cmpfunc);\n int *dp = (int *)malloc(N * sizeof(int));\n dp[0] = 0;\n for (int i = 1; i < N; i++) {\n dp[i] = dp[i - 1];\n if (arr[i] - arr[i - 1] < K) {\n if (i >= 2) {\n dp[i] = (dp[i] > (dp[i - 2] + arr[i] + arr[i - 1]))\n ? dp[i]\n : (dp[i - 2] + arr[i] + arr[i - 1]);\n } else {\n dp[i] = (dp[i] > (arr[i] + arr[i - 1])) ? dp[i] : (arr[i] + arr[i - 1]);\n }\n }\n }\n int result = dp[N - 1];\n free(dp);\n return result;\n}", + "test": "int main() {\n\n int arr1[] = {3, 5, 10, 15, 17, 12, 9};\n\n int arr2[] = {5, 15, 10, 300};\n\n int arr3[] = {1, 2, 3, 4, 5, 6};\n\n\n\n assert(func0(arr1, 7, 4) == 62);\n\n assert(func0(arr2, 4, 12) == 25);\n\n assert(func0(arr3, 6, 6) == 21);\n\n\n\n printf(\"All assertions passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbx\nmov %esi,%r13d\nmov %edx,%ebp\nmovslq %esi,%r12\nlea -0x29(%rip),%rcx\nmov $0x4,%edx\nmov %r12,%rsi\ncallq 10c0 \nshl $0x2,%r12\nmov %r12,%rdi\ncallq 10f0 \nmov %rax,%rdi\nmovl $0x0,(%rax)\ncmp $0x1,%r13d\njle 128a \nlea -0x2(%r13),%r9d\nadd $0x2,%r9\nmov $0x1,%edx\njmp 1260 \nadd -0x8(%rdi,%rdx,4),%ecx\nadd %esi,%ecx\ncmp %eax,%ecx\ncmovl %eax,%ecx\nmov %ecx,(%rdi,%rdx,4)\nadd $0x1,%rdx\ncmp %r9,%rdx\nje 128a \nmov -0x4(%rdi,%rdx,4),%eax\nmov %eax,(%rdi,%rdx,4)\nmov (%rbx,%rdx,4),%ecx\nmov -0x4(%rbx,%rdx,4),%esi\nmov %ecx,%r8d\nsub %esi,%r8d\ncmp %ebp,%r8d\njge 1257 \ncmp $0x1,%edx\njg 1249 \nadd %ecx,%esi\ncmp %eax,%esi\ncmovge %esi,%eax\nmov %eax,(%rdi,%rdx,4)\njmp 1257 \nmov -0x4(%rdi,%r12,1),%ebx\ncallq 10a0 \nmov %ebx,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov r13d, esi\nmov ebp, edx\nmovsxd r12, esi\nlea rcx, cmpfunc; compar\nmov edx, 4; size\nmov rsi, r12; nmemb\ncall _qsort\nshl r12, 2\nmov rdi, r12; size\ncall _malloc\nmov rdi, rax; ptr\nmov dword ptr [rax], 0\ncmp r13d, 1\njle short loc_1285\nmov r9d, r13d\nmov eax, 1\njmp short loc_1257\nloc_1244:\nadd edx, esi\ncmp edx, ecx\ncmovl edx, ecx\nmov [rdi+rax*4], edx\nloc_124E:\nadd rax, 1\ncmp rax, r9\njz short loc_1285\nloc_1257:\nmov ecx, [rdi+rax*4-4]\nmov [rdi+rax*4], ecx\nmov edx, [rbx+rax*4]\nmov esi, [rbx+rax*4-4]\nmov r8d, edx\nsub r8d, esi\ncmp r8d, ebp\njge short loc_124E\ncmp eax, 1\njle short loc_1244\nadd edx, [rdi+rax*4-8]\nadd edx, esi\ncmp edx, ecx\ncmovl edx, ecx\nmov [rdi+rax*4], edx\njmp short loc_124E\nloc_1285:\nmov ebx, [rdi+r12-4]\ncall _free\nmov eax, ebx\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "__int64 __fastcall func0(void *a1, int a2, int a3)\n{\n size_t v6; // r12\n _DWORD *v7; // rdi\n __int64 i; // rax\n int v9; // edx\n int v10; // ecx\n int v11; // edx\n int v12; // esi\n int v13; // edx\n unsigned int v14; // ebx\n\n qsort(a1, a2, 4uLL, cmpfunc);\n v6 = a2;\n v7 = malloc(v6 * 4);\n *v7 = 0;\n if ( a2 > 1 )\n {\n for ( i = 1LL; i != a2; ++i )\n {\n v10 = v7[i - 1];\n v7[i] = v10;\n v11 = *((_DWORD *)a1 + i);\n v12 = *((_DWORD *)a1 + i - 1);\n if ( v11 - v12 < a3 )\n {\n if ( (int)i <= 1 )\n {\n v9 = v12 + v11;\n if ( v9 < v10 )\n v9 = v10;\n v7[i] = v9;\n }\n else\n {\n v13 = v12 + v7[i - 2] + v11;\n if ( v13 < v10 )\n v13 = v10;\n v7[i] = v13;\n }\n }\n }\n }\n v14 = v7[v6 - 1];\n free(v7);\n return v14;\n}", + "ida_strip_asm": "sub_11F2:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov r13d, esi\nmov ebp, edx\nmovsxd r12, esi\nlea rcx, compar; compar\nmov edx, 4; size\nmov rsi, r12; nmemb\ncall _qsort\nshl r12, 2\nmov rdi, r12; size\ncall _malloc\nmov rdi, rax; ptr\nmov dword ptr [rax], 0\ncmp r13d, 1\njle short loc_1285\nmov r9d, r13d\nmov eax, 1\njmp short loc_1257\nloc_1244:\nadd edx, esi\ncmp edx, ecx\ncmovl edx, ecx\nmov [rdi+rax*4], edx\nloc_124E:\nadd rax, 1\ncmp rax, r9\njz short loc_1285\nloc_1257:\nmov ecx, [rdi+rax*4-4]\nmov [rdi+rax*4], ecx\nmov edx, [rbx+rax*4]\nmov esi, [rbx+rax*4-4]\nmov r8d, edx\nsub r8d, esi\ncmp r8d, ebp\njge short loc_124E\ncmp eax, 1\njle short loc_1244\nadd edx, [rdi+rax*4-8]\nadd edx, esi\ncmp edx, ecx\ncmovl edx, ecx\nmov [rdi+rax*4], edx\njmp short loc_124E\nloc_1285:\nmov ebx, [rdi+r12-4]\ncall _free\nmov eax, ebx\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11F2(void *a1, int a2, int a3)\n{\n size_t v6; // r12\n _DWORD *v7; // rdi\n __int64 i; // rax\n int v9; // edx\n int v10; // ecx\n int v11; // edx\n int v12; // esi\n int v13; // edx\n unsigned int v14; // ebx\n\n qsort(a1, a2, 4uLL, compar);\n v6 = a2;\n v7 = malloc(v6 * 4);\n *v7 = 0;\n if ( a2 > 1 )\n {\n for ( i = 1LL; i != a2; ++i )\n {\n v10 = v7[i - 1];\n v7[i] = v10;\n v11 = *((_DWORD *)a1 + i);\n v12 = *((_DWORD *)a1 + i - 1);\n if ( v11 - v12 < a3 )\n {\n if ( (int)i <= 1 )\n {\n v9 = v12 + v11;\n if ( v9 < v10 )\n v9 = v10;\n v7[i] = v9;\n }\n else\n {\n v13 = v12 + v7[i - 2] + v11;\n if ( v13 < v10 )\n v13 = v10;\n v7[i] = v13;\n }\n }\n }\n }\n v14 = v7[v6 - 1];\n free(v7);\n return v14;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11F2(void *a1, int a2, int a3) {\n unsigned int v6;\n uint32_t *v7;\n long long i;\n int v9;\n int v10;\n int v11;\n int v12;\n int v13;\n unsigned int v14;\n qsort(a1, a2, 4uLL, compar);\n v6 = a2;\n v7 = malloc(v6 * 4);\n *v7 = 0;\n if (a2 > 1) {\n for (i = 1LL; i != a2; ++i) {\n v10 = v7[i - 1];\n v7[i] = v10;\n v11 = *((uint32_t *)a1 + i);\n v12 = *((uint32_t *)a1 + i - 1);\n if (v11 - v12 < a3) {\n if ((int)i <= 1) {\n v9 = v12 + v11;\n if (v9 < v10) v9 = v10;\n v7[i] = v9;\n } else {\n v13 = v12 + v7[i - 2] + v11;\n if (v13 < v10) v13 = v10;\n v7[i] = v13;\n }\n }\n }\n }\n v14 = v7[v6 - 1];\n free(v7);\n return v14;\n}", + "ida_pseudo_norm": "long long func0(void *a1, int a2, int a3) {\n unsigned int v6;\n uint32_t *v7;\n long long i;\n int v9;\n int v10;\n int v11;\n int v12;\n int v13;\n unsigned int v14;\n qsort(a1, a2, 4uLL, cmpfunc);\n v6 = a2;\n v7 = malloc(v6 * 4);\n *v7 = 0;\n if (a2 > 1) {\n for (i = 1LL; i != a2; ++i) {\n v10 = v7[i - 1];\n v7[i] = v10;\n v11 = *((uint32_t *)a1 + i);\n v12 = *((uint32_t *)a1 + i - 1);\n if (v11 - v12 < a3) {\n if ((int)i <= 1) {\n v9 = v12 + v11;\n if (v9 < v10) v9 = v10;\n v7[i] = v9;\n } else {\n v13 = v12 + v7[i - 2] + v11;\n if (v13 < v10) v13 = v10;\n v7[i] = v13;\n }\n }\n }\n }\n v14 = v7[v6 - 1];\n free(v7);\n return v14;\n}" + }, + { + "index": 571, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint cmpfunc(const void *a, const void *b) {\n\n return (*(int*)a - *(int*)b);\n\n}\n\n\n\n", + "func": "int func0(int arr[], int N, int K) {\n qsort(arr, N, sizeof(int), cmpfunc);\n int *dp = (int *)malloc(N * sizeof(int));\n dp[0] = 0;\n for (int i = 1; i < N; i++) {\n dp[i] = dp[i - 1];\n if (arr[i] - arr[i - 1] < K) {\n if (i >= 2) {\n dp[i] = (dp[i] > (dp[i - 2] + arr[i] + arr[i - 1]))\n ? dp[i]\n : (dp[i - 2] + arr[i] + arr[i - 1]);\n } else {\n dp[i] = (dp[i] > (arr[i] + arr[i - 1])) ? dp[i] : (arr[i] + arr[i - 1]);\n }\n }\n }\n int result = dp[N - 1];\n free(dp);\n return result;\n}", + "test": "int main() {\n\n int arr1[] = {3, 5, 10, 15, 17, 12, 9};\n\n int arr2[] = {5, 15, 10, 300};\n\n int arr3[] = {1, 2, 3, 4, 5, 6};\n\n\n\n assert(func0(arr1, 7, 4) == 62);\n\n assert(func0(arr2, 4, 12) == 25);\n\n assert(func0(arr3, 6, 6) == 21);\n\n\n\n printf(\"All assertions passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nlea -0x1d(%rip),%rcx\npush %r12\nmovslq %esi,%r12\npush %rbp\nmov %r12,%rsi\nmov %r12,%r13\nmov %edx,%ebp\npush %rbx\nmov $0x4,%edx\nshl $0x2,%r12\nmov %rdi,%rbx\nsub $0x8,%rsp\ncallq 10c0 \nmov %r12,%rdi\ncallq 10f0 \nmovl $0x0,(%rax)\nmov %rax,%rdi\ncmp $0x1,%r13d\njle 1414 \nlea -0x2(%r13),%r9d\nmov $0x1,%edx\nxor %eax,%eax\nadd $0x1,%r9\njmp 13ea \nnopl 0x0(%rax)\nadd -0x8(%rdi,%rdx,4),%ecx\nadd %esi,%ecx\ncmp %eax,%ecx\ncmovl %eax,%ecx\nmov %ecx,(%rdi,%rdx,4)\ncmp %r9,%rdx\nje 1414 \nmov (%rdi,%rdx,4),%eax\nadd $0x1,%rdx\nmov (%rbx,%rdx,4),%ecx\nmov -0x4(%rbx,%rdx,4),%esi\nmov %eax,(%rdi,%rdx,4)\nmov %ecx,%r8d\nsub %esi,%r8d\ncmp %ebp,%r8d\njge 13de \ncmp $0x1,%rdx\njne 13d0 \nadd %ecx,%esi\ncmp %eax,%esi\ncmovge %esi,%eax\nmov %eax,0x4(%rdi)\ncmp %r9,%rdx\njne 13e3 \nmov -0x4(%rdi,%r12,1),%r12d\ncallq 10a0 \nadd $0x8,%rsp\npop %rbx\nmov %r12d,%eax\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r13\nlea rcx, cmpfunc; compar\npush r12\nmovsxd r12, esi\npush rbp\nmov rsi, r12; nmemb\nmov r13, r12\nmov ebp, edx\npush rbx\nmov edx, 4; size\nshl r12, 2\nmov rbx, rdi\nsub rsp, 8\ncall _qsort\nmov rdi, r12; size\ncall _malloc\nmov dword ptr [rax], 0\nmov rdi, rax; ptr\ncmp r13d, 1\njle short loc_13DA\nmov edx, [rbx]\nmov esi, r13d\nmov eax, 1\njmp short loc_13A6\nloc_1388:\nmov r9d, [rdi+rax*4-8]\nadd r9d, edx\nadd ecx, r9d\ncmp ecx, r8d\ncmovl ecx, r8d\nmov [rdi+rax*4], ecx\nloc_139D:\nadd rax, 1\ncmp rsi, rax\njz short loc_13DA\nloc_13A6:\nmov ecx, edx\nmov edx, [rbx+rax*4]\nmov r8d, [rdi+rax*4-4]\nmov r9d, edx\nmov [rdi+rax*4], r8d\nsub r9d, ecx\ncmp r9d, ebp\njge short loc_139D\ncmp rax, 1\njnz short loc_1388\nadd ecx, edx\ncmp ecx, r8d\ncmovl ecx, r8d\nadd rax, 1\nmov [rdi+4], ecx\ncmp rsi, rax\njnz short loc_13A6\nloc_13DA:\nmov ebx, [rdi+r12-4]\ncall _free\nadd rsp, 8\nmov eax, ebx\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2, int a3)\n{\n _DWORD *v5; // rax\n _DWORD *v6; // rdi\n int v7; // edx\n __int64 v8; // rax\n int v9; // ecx\n int v10; // ecx\n int v11; // r8d\n int v12; // ecx\n unsigned int v13; // ebx\n\n qsort(a1, a2, 4uLL, cmpfunc);\n v5 = malloc(4LL * a2);\n *v5 = 0;\n v6 = v5;\n if ( a2 > 1 )\n {\n v7 = *a1;\n v8 = 1LL;\n do\n {\n while ( 1 )\n {\n v10 = v7;\n v7 = a1[v8];\n v11 = v6[v8 - 1];\n v6[v8] = v11;\n if ( v7 - v10 < a3 )\n break;\nLABEL_6:\n if ( a2 == ++v8 )\n goto LABEL_12;\n }\n if ( v8 != 1 )\n {\n v9 = v7 + v6[v8 - 2] + v10;\n if ( v9 < v11 )\n v9 = v11;\n v6[v8] = v9;\n goto LABEL_6;\n }\n v12 = v7 + v10;\n if ( v12 < v11 )\n v12 = v11;\n v8 = 2LL;\n v6[1] = v12;\n }\n while ( a2 != 2LL );\n }\nLABEL_12:\n v13 = v6[a2 - 1];\n free(v6);\n return v13;\n}", + "ida_strip_asm": "sub_1330:\nendbr64\npush r13\nlea rcx, compar; compar\npush r12\nmovsxd r12, esi\npush rbp\nmov rsi, r12; nmemb\nmov r13, r12\nmov ebp, edx\npush rbx\nmov edx, 4; size\nshl r12, 2\nmov rbx, rdi\nsub rsp, 8\ncall _qsort\nmov rdi, r12; size\ncall _malloc\nmov dword ptr [rax], 0\nmov rdi, rax; ptr\ncmp r13d, 1\njle short loc_13DA\nmov edx, [rbx]\nmov esi, r13d\nmov eax, 1\njmp short loc_13A6\nloc_1388:\nmov r9d, [rdi+rax*4-8]\nadd r9d, edx\nadd ecx, r9d\ncmp ecx, r8d\ncmovl ecx, r8d\nmov [rdi+rax*4], ecx\nloc_139D:\nadd rax, 1\ncmp rsi, rax\njz short loc_13DA\nloc_13A6:\nmov ecx, edx\nmov edx, [rbx+rax*4]\nmov r8d, [rdi+rax*4-4]\nmov r9d, edx\nmov [rdi+rax*4], r8d\nsub r9d, ecx\ncmp r9d, ebp\njge short loc_139D\ncmp rax, 1\njnz short loc_1388\nadd ecx, edx\ncmp ecx, r8d\ncmovl ecx, r8d\nadd rax, 1\nmov [rdi+4], ecx\ncmp rsi, rax\njnz short loc_13A6\nloc_13DA:\nmov ebx, [rdi+r12-4]\ncall _free\nadd rsp, 8\nmov eax, ebx\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1330(int *a1, int a2, int a3)\n{\n _DWORD *v5; // rax\n _DWORD *v6; // rdi\n int v7; // edx\n __int64 v8; // rax\n int v9; // ecx\n int v10; // ecx\n int v11; // r8d\n int v12; // ecx\n unsigned int v13; // ebx\n\n qsort(a1, a2, 4uLL, compar);\n v5 = malloc(4LL * a2);\n *v5 = 0;\n v6 = v5;\n if ( a2 > 1 )\n {\n v7 = *a1;\n v8 = 1LL;\n do\n {\n while ( 1 )\n {\n v10 = v7;\n v7 = a1[v8];\n v11 = v6[v8 - 1];\n v6[v8] = v11;\n if ( v7 - v10 < a3 )\n break;\nLABEL_6:\n if ( a2 == ++v8 )\n goto LABEL_12;\n }\n if ( v8 != 1 )\n {\n v9 = v7 + v6[v8 - 2] + v10;\n if ( v9 < v11 )\n v9 = v11;\n v6[v8] = v9;\n goto LABEL_6;\n }\n v12 = v7 + v10;\n if ( v12 < v11 )\n v12 = v11;\n v8 = 2LL;\n v6[1] = v12;\n }\n while ( a2 != 2LL );\n }\nLABEL_12:\n v13 = v6[a2 - 1];\n free(v6);\n return v13;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1330(int *a1, int a2, int a3) {\n uint32_t *v5;\n uint32_t *v6;\n int v7;\n long long v8;\n int v9;\n int v10;\n int v11;\n int v12;\n unsigned int v13;\n qsort(a1, a2, 4uLL, compar);\n v5 = malloc(4LL * a2);\n *v5 = 0;\n v6 = v5;\n if (a2 > 1) {\n v7 = *a1;\n v8 = 1LL;\n do {\n while (1) {\n v10 = v7;\n v7 = a1[v8];\n v11 = v6[v8 - 1];\n v6[v8] = v11;\n if (v7 - v10 < a3) break;\n LABEL_6:\n if (a2 == ++v8) goto LABEL_12;\n }\n if (v8 != 1) {\n v9 = v7 + v6[v8 - 2] + v10;\n if (v9 < v11) v9 = v11;\n v6[v8] = v9;\n goto LABEL_6;\n }\n v12 = v7 + v10;\n if (v12 < v11) v12 = v11;\n v8 = 2LL;\n v6[1] = v12;\n } while (a2 != 2LL);\n }\nLABEL_12:\n v13 = v6[a2 - 1];\n free(v6);\n return v13;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2, int a3) {\n uint32_t *v5;\n uint32_t *v6;\n int v7;\n long long v8;\n int v9;\n int v10;\n int v11;\n int v12;\n unsigned int v13;\n qsort(a1, a2, 4uLL, cmpfunc);\n v5 = malloc(4LL * a2);\n *v5 = 0;\n v6 = v5;\n if (a2 > 1) {\n v7 = *a1;\n v8 = 1LL;\n do {\n while (1) {\n v10 = v7;\n v7 = a1[v8];\n v11 = v6[v8 - 1];\n v6[v8] = v11;\n if (v7 - v10 < a3) break;\n LABEL_6:\n if (a2 == ++v8) goto LABEL_12;\n }\n if (v8 != 1) {\n v9 = v7 + v6[v8 - 2] + v10;\n if (v9 < v11) v9 = v11;\n v6[v8] = v9;\n goto LABEL_6;\n }\n v12 = v7 + v10;\n if (v12 < v11) v12 = v11;\n v8 = 2LL;\n v6[1] = v12;\n } while (a2 != 2LL);\n }\nLABEL_12:\n v13 = v6[a2 - 1];\n free(v6);\n return v13;\n}" + }, + { + "index": 571, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint cmpfunc(const void *a, const void *b) {\n\n return (*(int*)a - *(int*)b);\n\n}\n\n\n\n", + "func": "int func0(int arr[], int N, int K) {\n qsort(arr, N, sizeof(int), cmpfunc);\n int *dp = (int *)malloc(N * sizeof(int));\n dp[0] = 0;\n for (int i = 1; i < N; i++) {\n dp[i] = dp[i - 1];\n if (arr[i] - arr[i - 1] < K) {\n if (i >= 2) {\n dp[i] = (dp[i] > (dp[i - 2] + arr[i] + arr[i - 1]))\n ? dp[i]\n : (dp[i - 2] + arr[i] + arr[i - 1]);\n } else {\n dp[i] = (dp[i] > (arr[i] + arr[i - 1])) ? dp[i] : (arr[i] + arr[i - 1]);\n }\n }\n }\n int result = dp[N - 1];\n free(dp);\n return result;\n}", + "test": "int main() {\n\n int arr1[] = {3, 5, 10, 15, 17, 12, 9};\n\n int arr2[] = {5, 15, 10, 300};\n\n int arr3[] = {1, 2, 3, 4, 5, 6};\n\n\n\n assert(func0(arr1, 7, 4) == 62);\n\n assert(func0(arr2, 4, 12) == 25);\n\n assert(func0(arr3, 6, 6) == 21);\n\n\n\n printf(\"All assertions passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmovslq %esi,%r13\nlea -0x20(%rip),%rcx\npush %r12\nmov %r13,%rsi\nmov %edx,%r12d\nmov $0x4,%edx\npush %rbp\nmov %r13,%rbp\nshl $0x2,%r13\npush %rbx\nmov %rdi,%rbx\nsub $0x8,%rsp\ncallq 10c0 \nmov %r13,%rdi\ncallq 10f0 \nmovl $0x0,(%rax)\nmov %rax,%rdi\ncmp $0x1,%ebp\njle 144e \ncmp $0x3,%ebp\njle 14b6 \nlea -0x4(%rbp),%edx\nmov (%rbx),%r8d\nmov $0x3,%ecx\nshr %edx\nlea 0x5(%rdx,%rdx,1),%r9\nmov -0x8(%rbx,%rcx,4),%r10d\nmov (%rax),%edx\nmov %r10d,%esi\nmov %edx,0x4(%rax)\nsub %r8d,%esi\ncmp %r12d,%esi\njge 13d9 \ncmp $0x3,%ecx\nje 1466 \nmov -0x4(%rax),%esi\nadd %r10d,%esi\nadd %esi,%r8d\ncmp %edx,%r8d\ncmovl %edx,%r8d\nmov %r8d,0x4(%rax)\nmov -0x4(%rbx,%rcx,4),%r8d\nmov 0x4(%rax),%esi\nmov %r8d,%r11d\nmov %esi,0x8(%rax)\nsub %r10d,%r11d\ncmp %r11d,%r12d\njg 1490 \nmovslq %ecx,%rdx\nadd $0x2,%rcx\nadd $0x8,%rax\ncmp %r9,%rcx\njne 13a7 \njmp 141e \nnopl (%rax)\nadd -0x8(%rdi,%rdx,4),%ecx\nadd %esi,%ecx\ncmp %eax,%ecx\ncmovl %eax,%ecx\nmov %ecx,(%rdi,%rdx,4)\nadd $0x1,%rdx\ncmp %edx,%ebp\njle 144e \nmov (%rbx,%rdx,4),%ecx\nmov -0x4(%rbx,%rdx,4),%esi\nmov -0x4(%rdi,%rdx,4),%eax\nmov %ecx,%r8d\nsub %esi,%r8d\nmov %eax,(%rdi,%rdx,4)\ncmp %r8d,%r12d\njle 1416 \ncmp $0x1,%edx\njne 1408 \nadd %ecx,%esi\ncmp %eax,%esi\ncmovge %esi,%eax\nmov %eax,(%rdi,%rdx,4)\nadd $0x1,%rdx\ncmp %edx,%ebp\njg 141e \nmov -0x4(%rdi,%r13,1),%r12d\ncallq 10a0 \nadd $0x8,%rsp\npop %rbx\nmov %r12d,%eax\npop %rbp\npop %r12\npop %r13\nretq\nlea (%r10,%r8,1),%esi\nmov -0x4(%rbx,%rcx,4),%r8d\ncmp %edx,%esi\ncmovl %edx,%esi\nmov %r8d,%r11d\nsub %r10d,%r11d\nmov %esi,0x4(%rax)\nmov %esi,0x8(%rax)\ncmp %r12d,%r11d\njge 13f3 \nnopl 0x0(%rax)\nadd %r8d,%edx\nadd %r10d,%edx\ncmp %esi,%edx\ncmovl %esi,%edx\nadd $0x8,%rax\nmov %edx,(%rax)\nmovslq %ecx,%rdx\nadd $0x2,%rcx\ncmp %r9,%rcx\njne 13a7 \njmpq 141e \nmov $0x1,%edx\njmpq 141e \n", + "ida_asm": "func0:\nendbr64\npush r13\nmovsxd r13, esi\nlea rcx, cmpfunc; compar\npush r12\nmov rsi, r13; nmemb\nmov r12d, edx\nmov edx, 4; size\npush rbp\nmov rbp, r13\nshl r13, 2\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _qsort\nmov rdi, r13; size\ncall _malloc\nmov dword ptr [rax], 0\nmov rdi, rax; ptr\ncmp ebp, 1\njle loc_13F8\ncmp ebp, 3\njle loc_1488\nmov rdx, rax\nlea eax, [rbp-4]\nmov esi, [rbx]\nshr eax, 1\nlea r9d, [rax+rax]\nmov eax, 1\nadd r9, 3\nloc_139C:\nmov r8d, [rbx+rax*4]\nmov ecx, [rdx]\nmov r10d, r8d\nmov [rdx+4], ecx\nsub r10d, esi\ncmp r10d, r12d\njge short loc_13CC\ncmp rax, 1\njz loc_1478\nmov r10d, [rdx-4]\nadd r10d, r8d\nadd esi, r10d\ncmp esi, ecx\ncmovl esi, ecx\nmov [rdx+4], esi\nloc_13CC:\nmov esi, [rbx+rax*4+4]\nmov r10d, [rdx+4]\nmov r11d, esi\nmov [rdx+8], r10d\nsub r11d, r8d\ncmp r12d, r11d\njg short loc_1410\nlea rcx, [rax+2]\nadd rdx, 8\ncmp rcx, r9\njz short loc_142B\nloc_13F0:\nmov rax, rcx\njmp short loc_139C\nloc_13F8:\nmov ebx, [rdi+r13-4]\ncall _free\nadd rsp, 8\nmov eax, ebx\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1410:\nadd ecx, esi\nadd ecx, r8d\ncmp ecx, r10d\ncmovl ecx, r10d\nadd rdx, 8\nmov [rdx], ecx\nlea rcx, [rax+2]\ncmp rcx, r9\njnz short loc_13F0\nloc_142B:\nadd eax, 2\nloc_142E:\ncdqe\njmp short loc_144E\nloc_1438:\nadd edx, [rdi+rax*4-8]\nadd edx, ecx\ncmp edx, esi\ncmovl edx, esi\nmov [rdi+rax*4], edx\nloc_1446:\nadd rax, 1\ncmp ebp, eax\njle short loc_13F8\nloc_144E:\nmov edx, [rbx+rax*4]\nmov ecx, [rbx+rax*4-4]\nmov esi, [rdi+rax*4-4]\nmov r8d, edx\nsub r8d, ecx\nmov [rdi+rax*4], esi\ncmp r8d, r12d\njge short loc_1446\ncmp eax, 1\njnz short loc_1438\nadd ecx, edx\ncmp ecx, esi\ncmovl ecx, esi\nmov [rdi+rax*4], ecx\njmp short loc_1446\nloc_1478:\nadd esi, r8d\ncmp esi, ecx\ncmovl esi, ecx\nmov [rdx+4], esi\njmp loc_13CC\nloc_1488:\nmov eax, 1\njmp short loc_142E", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2, int a3)\n{\n size_t v5; // r13\n _DWORD *v7; // rax\n _DWORD *v8; // rdi\n int *v9; // rdx\n int v10; // esi\n __int64 v11; // rax\n __int64 v12; // r9\n int v13; // r8d\n int v14; // ecx\n int v15; // esi\n int v16; // r10d\n __int64 v17; // rcx\n unsigned int v18; // ebx\n int v20; // ecx\n int v21; // edx\n int v22; // edx\n int v23; // ecx\n int v24; // esi\n int v25; // ecx\n int v26; // esi\n\n v5 = a2;\n qsort(a1, a2, 4uLL, cmpfunc);\n v7 = malloc(v5 * 4);\n *v7 = 0;\n v8 = v7;\n if ( a2 <= 1 )\n goto LABEL_12;\n if ( a2 <= 3 )\n {\n LODWORD(v11) = 1;\n goto LABEL_17;\n }\n v9 = v7;\n v10 = *a1;\n v11 = 1LL;\n v12 = 2 * ((unsigned int)(a2 - 4) >> 1) + 3LL;\n while ( 1 )\n {\n v13 = a1[v11];\n v14 = *v9;\n v9[1] = *v9;\n if ( v13 - v10 < a3 )\n {\n if ( v11 == 1 )\n {\n v26 = v13 + v10;\n if ( v26 < v14 )\n v26 = v14;\n v9[1] = v26;\n }\n else\n {\n v15 = v13 + *(v9 - 1) + v10;\n if ( v15 < v14 )\n v15 = v14;\n v9[1] = v15;\n }\n }\n v10 = a1[v11 + 1];\n v16 = v9[1];\n v9[2] = v16;\n if ( a3 > v10 - v13 )\n break;\n v17 = v11 + 2;\n v9 += 2;\n if ( v11 + 2 == v12 )\n goto LABEL_16;\nLABEL_11:\n v11 = v17;\n }\n v20 = v13 + v10 + v14;\n if ( v20 < v16 )\n v20 = v16;\n v9 += 2;\n *v9 = v20;\n v17 = v11 + 2;\n if ( v11 + 2 != v12 )\n goto LABEL_11;\nLABEL_16:\n LODWORD(v11) = v11 + 2;\nLABEL_17:\n v11 = (int)v11;\n do\n {\n v22 = a1[v11];\n v23 = a1[v11 - 1];\n v24 = v8[v11 - 1];\n v8[v11] = v24;\n if ( v22 - v23 < a3 )\n {\n if ( (_DWORD)v11 == 1 )\n {\n v25 = v22 + v23;\n if ( v25 < v24 )\n v25 = v24;\n v8[v11] = v25;\n }\n else\n {\n v21 = v23 + v8[v11 - 2] + v22;\n if ( v21 < v24 )\n v21 = v24;\n v8[v11] = v21;\n }\n }\n ++v11;\n }\n while ( a2 > (int)v11 );\nLABEL_12:\n v18 = v8[v5 - 1];\n free(v8);\n return v18;\n}", + "ida_strip_asm": "sub_1330:\nendbr64\npush r13\nmovsxd r13, esi\nlea rcx, compar; compar\npush r12\nmov rsi, r13; nmemb\nmov r12d, edx\nmov edx, 4; size\npush rbp\nmov rbp, r13\nshl r13, 2\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _qsort\nmov rdi, r13; size\ncall _malloc\nmov dword ptr [rax], 0\nmov rdi, rax; ptr\ncmp ebp, 1\njle loc_13F8\ncmp ebp, 3\njle loc_1488\nmov rdx, rax\nlea eax, [rbp-4]\nmov esi, [rbx]\nshr eax, 1\nlea r9d, [rax+rax]\nmov eax, 1\nadd r9, 3\nloc_139C:\nmov r8d, [rbx+rax*4]\nmov ecx, [rdx]\nmov r10d, r8d\nmov [rdx+4], ecx\nsub r10d, esi\ncmp r10d, r12d\njge short loc_13CC\ncmp rax, 1\njz loc_1478\nmov r10d, [rdx-4]\nadd r10d, r8d\nadd esi, r10d\ncmp esi, ecx\ncmovl esi, ecx\nmov [rdx+4], esi\nloc_13CC:\nmov esi, [rbx+rax*4+4]\nmov r10d, [rdx+4]\nmov r11d, esi\nmov [rdx+8], r10d\nsub r11d, r8d\ncmp r12d, r11d\njg short loc_1410\nlea rcx, [rax+2]\nadd rdx, 8\ncmp rcx, r9\njz short loc_142B\nloc_13F0:\nmov rax, rcx\njmp short loc_139C\nloc_13F8:\nmov ebx, [rdi+r13-4]\ncall _free\nadd rsp, 8\nmov eax, ebx\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1410:\nadd ecx, esi\nadd ecx, r8d\ncmp ecx, r10d\ncmovl ecx, r10d\nadd rdx, 8\nmov [rdx], ecx\nlea rcx, [rax+2]\ncmp rcx, r9\njnz short loc_13F0\nloc_142B:\nadd eax, 2\nloc_142E:\ncdqe\njmp short loc_144E\nloc_1438:\nadd edx, [rdi+rax*4-8]\nadd edx, ecx\ncmp edx, esi\ncmovl edx, esi\nmov [rdi+rax*4], edx\nloc_1446:\nadd rax, 1\ncmp ebp, eax\njle short loc_13F8\nloc_144E:\nmov edx, [rbx+rax*4]\nmov ecx, [rbx+rax*4-4]\nmov esi, [rdi+rax*4-4]\nmov r8d, edx\nsub r8d, ecx\nmov [rdi+rax*4], esi\ncmp r8d, r12d\njge short loc_1446\ncmp eax, 1\njnz short loc_1438\nadd ecx, edx\ncmp ecx, esi\ncmovl ecx, esi\nmov [rdi+rax*4], ecx\njmp short loc_1446\nloc_1478:\nadd esi, r8d\ncmp esi, ecx\ncmovl esi, ecx\nmov [rdx+4], esi\njmp loc_13CC\nloc_1488:\nmov eax, 1\njmp short loc_142E", + "ida_strip_pseudo": "__int64 __fastcall sub_1330(int *a1, int a2, int a3)\n{\n size_t v5; // r13\n _DWORD *v7; // rax\n _DWORD *v8; // rdi\n int *v9; // rdx\n int v10; // esi\n __int64 v11; // rax\n __int64 v12; // r9\n int v13; // r8d\n int v14; // ecx\n int v15; // esi\n int v16; // r10d\n __int64 v17; // rcx\n unsigned int v18; // ebx\n int v20; // ecx\n int v21; // edx\n int v22; // edx\n int v23; // ecx\n int v24; // esi\n int v25; // ecx\n int v26; // esi\n\n v5 = a2;\n qsort(a1, a2, 4uLL, compar);\n v7 = malloc(v5 * 4);\n *v7 = 0;\n v8 = v7;\n if ( a2 <= 1 )\n goto LABEL_12;\n if ( a2 <= 3 )\n {\n LODWORD(v11) = 1;\n goto LABEL_17;\n }\n v9 = v7;\n v10 = *a1;\n v11 = 1LL;\n v12 = 2 * ((unsigned int)(a2 - 4) >> 1) + 3LL;\n while ( 1 )\n {\n v13 = a1[v11];\n v14 = *v9;\n v9[1] = *v9;\n if ( v13 - v10 < a3 )\n {\n if ( v11 == 1 )\n {\n v26 = v13 + v10;\n if ( v26 < v14 )\n v26 = v14;\n v9[1] = v26;\n }\n else\n {\n v15 = v13 + *(v9 - 1) + v10;\n if ( v15 < v14 )\n v15 = v14;\n v9[1] = v15;\n }\n }\n v10 = a1[v11 + 1];\n v16 = v9[1];\n v9[2] = v16;\n if ( a3 > v10 - v13 )\n break;\n v17 = v11 + 2;\n v9 += 2;\n if ( v11 + 2 == v12 )\n goto LABEL_16;\nLABEL_11:\n v11 = v17;\n }\n v20 = v13 + v10 + v14;\n if ( v20 < v16 )\n v20 = v16;\n v9 += 2;\n *v9 = v20;\n v17 = v11 + 2;\n if ( v11 + 2 != v12 )\n goto LABEL_11;\nLABEL_16:\n LODWORD(v11) = v11 + 2;\nLABEL_17:\n v11 = (int)v11;\n do\n {\n v22 = a1[v11];\n v23 = a1[v11 - 1];\n v24 = v8[v11 - 1];\n v8[v11] = v24;\n if ( v22 - v23 < a3 )\n {\n if ( (_DWORD)v11 == 1 )\n {\n v25 = v22 + v23;\n if ( v25 < v24 )\n v25 = v24;\n v8[v11] = v25;\n }\n else\n {\n v21 = v23 + v8[v11 - 2] + v22;\n if ( v21 < v24 )\n v21 = v24;\n v8[v11] = v21;\n }\n }\n ++v11;\n }\n while ( a2 > (int)v11 );\nLABEL_12:\n v18 = v8[v5 - 1];\n free(v8);\n return v18;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1330(int *a1, int a2, int a3) {\n unsigned int v5;\n uint32_t *v7;\n uint32_t *v8;\n int *v9;\n int v10;\n long long v11;\n long long v12;\n int v13;\n int v14;\n int v15;\n int v16;\n long long v17;\n unsigned int v18;\n int v20;\n int v21;\n int v22;\n int v23;\n int v24;\n int v25;\n int v26;\n v5 = a2;\n qsort(a1, a2, 4uLL, compar);\n v7 = malloc(v5 * 4);\n *v7 = 0;\n v8 = v7;\n if (a2 <= 1) goto LABEL_12;\n if (a2 <= 3) {\n LODWORD(v11) = 1;\n goto LABEL_17;\n }\n v9 = v7;\n v10 = *a1;\n v11 = 1LL;\n v12 = 2 * ((unsigned int)(a2 - 4) >> 1) + 3LL;\n while (1) {\n v13 = a1[v11];\n v14 = *v9;\n v9[1] = *v9;\n if (v13 - v10 < a3) {\n if (v11 == 1) {\n v26 = v13 + v10;\n if (v26 < v14) v26 = v14;\n v9[1] = v26;\n } else {\n v15 = v13 + *(v9 - 1) + v10;\n if (v15 < v14) v15 = v14;\n v9[1] = v15;\n }\n }\n v10 = a1[v11 + 1];\n v16 = v9[1];\n v9[2] = v16;\n if (a3 > v10 - v13) break;\n v17 = v11 + 2;\n v9 += 2;\n if (v11 + 2 == v12) goto LABEL_16;\n LABEL_11:\n v11 = v17;\n }\n v20 = v13 + v10 + v14;\n if (v20 < v16) v20 = v16;\n v9 += 2;\n *v9 = v20;\n v17 = v11 + 2;\n if (v11 + 2 != v12) goto LABEL_11;\nLABEL_16:\n LODWORD(v11) = v11 + 2;\nLABEL_17:\n v11 = (int)v11;\n do {\n v22 = a1[v11];\n v23 = a1[v11 - 1];\n v24 = v8[v11 - 1];\n v8[v11] = v24;\n if (v22 - v23 < a3) {\n if ((uint32_t)v11 == 1) {\n v25 = v22 + v23;\n if (v25 < v24) v25 = v24;\n v8[v11] = v25;\n } else {\n v21 = v23 + v8[v11 - 2] + v22;\n if (v21 < v24) v21 = v24;\n v8[v11] = v21;\n }\n }\n ++v11;\n } while (a2 > (int)v11);\nLABEL_12:\n v18 = v8[v5 - 1];\n free(v8);\n return v18;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2, int a3) {\n unsigned int v5;\n uint32_t *v7;\n uint32_t *v8;\n int *v9;\n int v10;\n long long v11;\n long long v12;\n int v13;\n int v14;\n int v15;\n int v16;\n long long v17;\n unsigned int v18;\n int v20;\n int v21;\n int v22;\n int v23;\n int v24;\n int v25;\n int v26;\n v5 = a2;\n qsort(a1, a2, 4uLL, cmpfunc);\n v7 = malloc(v5 * 4);\n *v7 = 0;\n v8 = v7;\n if (a2 <= 1) goto LABEL_12;\n if (a2 <= 3) {\n LODWORD(v11) = 1;\n goto LABEL_17;\n }\n v9 = v7;\n v10 = *a1;\n v11 = 1LL;\n v12 = 2 * ((unsigned int)(a2 - 4) >> 1) + 3LL;\n while (1) {\n v13 = a1[v11];\n v14 = *v9;\n v9[1] = *v9;\n if (v13 - v10 < a3) {\n if (v11 == 1) {\n v26 = v13 + v10;\n if (v26 < v14) v26 = v14;\n v9[1] = v26;\n } else {\n v15 = v13 + *(v9 - 1) + v10;\n if (v15 < v14) v15 = v14;\n v9[1] = v15;\n }\n }\n v10 = a1[v11 + 1];\n v16 = v9[1];\n v9[2] = v16;\n if (a3 > v10 - v13) break;\n v17 = v11 + 2;\n v9 += 2;\n if (v11 + 2 == v12) goto LABEL_16;\n LABEL_11:\n v11 = v17;\n }\n v20 = v13 + v10 + v14;\n if (v20 < v16) v20 = v16;\n v9 += 2;\n *v9 = v20;\n v17 = v11 + 2;\n if (v11 + 2 != v12) goto LABEL_11;\nLABEL_16:\n LODWORD(v11) = v11 + 2;\nLABEL_17:\n v11 = (int)v11;\n do {\n v22 = a1[v11];\n v23 = a1[v11 - 1];\n v24 = v8[v11 - 1];\n v8[v11] = v24;\n if (v22 - v23 < a3) {\n if ((uint32_t)v11 == 1) {\n v25 = v22 + v23;\n if (v25 < v24) v25 = v24;\n v8[v11] = v25;\n } else {\n v21 = v23 + v8[v11 - 2] + v22;\n if (v21 < v24) v21 = v24;\n v8[v11] = v21;\n }\n }\n ++v11;\n } while (a2 > (int)v11);\nLABEL_12:\n v18 = v8[v5 - 1];\n free(v8);\n return v18;\n}" + }, + { + "index": 572, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\nvoid print_array(int arr[], int size) {\n\n printf(\"[\");\n\n for (int i = 0; i < size; i++) {\n\n printf(\"%d\", arr[i]);\n\n if (i < size - 1) printf(\", \");\n\n }\n\n printf(\"]\\n\");\n\n}\n\n\n\nint arrays_equal(int a[], int b[], int sizeA, int sizeB) {\n\n if (sizeA != sizeB) return 0;\n\n for (int i = 0; i < sizeA; i++) { \n\n if (a[i] != b[i]) return 0;\n\n }\n\n return 1;\n\n}\n\n\n\n", + "func": "int *func0(int nums[], int size, int *returnSize) {\n int *result = (int *)malloc(size * sizeof(int));\n int k = 0;\n for (int i = 0; i < size; i++) {\n int count = 0;\n for (int j = 0; j < size; j++) {\n if (nums[i] == nums[j]) {\n count++;\n }\n }\n if (count == 1) {\n result[k++] = nums[i];\n }\n }\n *returnSize = k;\n return result;\n}", + "test": "int main() {\n\n int sz;\n\n\n\n int testArr1[] = {1, 2, 3, 2, 3, 4, 5};\n\n int expected1[] = {1, 4, 5};\n\n int* result1 = func0(testArr1, 7, &sz);\n\n assert(arrays_equal(result1, expected1, sz, 3));\n\n \n\n int testArr2[] = {1, 2, 3, 2, 4, 5};\n\n int expected2[] = {1, 3, 4, 5};\n\n int* result2 = func0(testArr2, 6, &sz);\n\n assert(arrays_equal(result2, expected2, sz, 4));\n\n\n\n int testArr3[] = {1, 2, 3, 4, 5};\n\n int expected3[] = {1, 2, 3, 4, 5};\n\n int* result3 = func0(testArr3, 5, &sz);\n\n assert(arrays_equal(result3, expected3, sz, 5));\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x40,%rsp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmov %rdx,-0x38(%rbp)\nmov -0x2c(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 1110 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0x18(%rbp)\nmovl $0x0,-0x14(%rbp)\njmpq 13d3 \nmovl $0x0,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 138e \nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 138a \naddl $0x1,-0x10(%rbp)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 1356 \ncmpl $0x1,-0x10(%rbp)\njne 13cf \nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x18(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x18(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 1346 \nmov -0x38(%rbp),%rax\nmov -0x18(%rbp),%edx\nmov %edx,(%rax)\nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp loc_13DC\nloc_134F:\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp short loc_1397\nloc_135F:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_1393\nadd [rbp+var_10], 1\nloc_1393:\nadd [rbp+var_C], 1\nloc_1397:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_2C]\njl short loc_135F\ncmp [rbp+var_10], 1\njnz short loc_13D8\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_13D8:\nadd [rbp+var_14], 1\nloc_13DC:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl loc_134F\nmov rax, [rbp+var_38]\nmov edx, [rbp+var_18]\nmov [rax], edx\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, _DWORD *a3)\n{\n int v3; // eax\n int v6; // [rsp+28h] [rbp-18h]\n int i; // [rsp+2Ch] [rbp-14h]\n int v8; // [rsp+30h] [rbp-10h]\n int j; // [rsp+34h] [rbp-Ch]\n _DWORD *v10; // [rsp+38h] [rbp-8h]\n\n v10 = malloc(4LL * a2);\n v6 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v8 = 0;\n for ( j = 0; j < a2; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4LL * j + a1) )\n ++v8;\n }\n if ( v8 == 1 )\n {\n v3 = v6++;\n v10[v3] = *(_DWORD *)(4LL * i + a1);\n }\n }\n *a3 = v6;\n return v10;\n}", + "ida_strip_asm": "sub_1310:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp loc_13DC\nloc_134F:\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp short loc_1397\nloc_135F:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_1393\nadd [rbp+var_10], 1\nloc_1393:\nadd [rbp+var_C], 1\nloc_1397:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_2C]\njl short loc_135F\ncmp [rbp+var_10], 1\njnz short loc_13D8\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_13D8:\nadd [rbp+var_14], 1\nloc_13DC:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl loc_134F\nmov rax, [rbp+var_38]\nmov edx, [rbp+var_18]\nmov [rax], edx\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1310(__int64 a1, int a2, _DWORD *a3)\n{\n int v3; // eax\n int v6; // [rsp+28h] [rbp-18h]\n int i; // [rsp+2Ch] [rbp-14h]\n int v8; // [rsp+30h] [rbp-10h]\n int j; // [rsp+34h] [rbp-Ch]\n _DWORD *v10; // [rsp+38h] [rbp-8h]\n\n v10 = malloc(4LL * a2);\n v6 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v8 = 0;\n for ( j = 0; j < a2; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4LL * j + a1) )\n ++v8;\n }\n if ( v8 == 1 )\n {\n v3 = v6++;\n v10[v3] = *(_DWORD *)(4LL * i + a1);\n }\n }\n *a3 = v6;\n return v10;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1310(long long a1, int a2, uint32_t *a3) {\n int v3;\n int v6;\n int i;\n int v8;\n int j;\n uint32_t *v10;\n v10 = malloc(4LL * a2);\n v6 = 0;\n for (i = 0; i < a2; ++i) {\n v8 = 0;\n for (j = 0; j < a2; ++j) {\n if (*(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4LL * j + a1)) ++v8;\n }\n if (v8 == 1) {\n v3 = v6++;\n v10[v3] = *(uint32_t *)(4LL * i + a1);\n }\n }\n *a3 = v6;\n return v10;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, uint32_t *a3) {\n int v3;\n int v6;\n int i;\n int v8;\n int j;\n uint32_t *v10;\n v10 = malloc(4LL * a2);\n v6 = 0;\n for (i = 0; i < a2; ++i) {\n v8 = 0;\n for (j = 0; j < a2; ++j) {\n if (*(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4LL * j + a1)) ++v8;\n }\n if (v8 == 1) {\n v3 = v6++;\n v10[v3] = *(uint32_t *)(4LL * i + a1);\n }\n }\n *a3 = v6;\n return v10;\n}" + }, + { + "index": 572, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\nvoid print_array(int arr[], int size) {\n\n printf(\"[\");\n\n for (int i = 0; i < size; i++) {\n\n printf(\"%d\", arr[i]);\n\n if (i < size - 1) printf(\", \");\n\n }\n\n printf(\"]\\n\");\n\n}\n\n\n\nint arrays_equal(int a[], int b[], int sizeA, int sizeB) {\n\n if (sizeA != sizeB) return 0;\n\n for (int i = 0; i < sizeA; i++) { \n\n if (a[i] != b[i]) return 0;\n\n }\n\n return 1;\n\n}\n\n\n\n", + "func": "int *func0(int nums[], int size, int *returnSize) {\n int *result = (int *)malloc(size * sizeof(int));\n int k = 0;\n for (int i = 0; i < size; i++) {\n int count = 0;\n for (int j = 0; j < size; j++) {\n if (nums[i] == nums[j]) {\n count++;\n }\n }\n if (count == 1) {\n result[k++] = nums[i];\n }\n }\n *returnSize = k;\n return result;\n}", + "test": "int main() {\n\n int sz;\n\n\n\n int testArr1[] = {1, 2, 3, 2, 3, 4, 5};\n\n int expected1[] = {1, 4, 5};\n\n int* result1 = func0(testArr1, 7, &sz);\n\n assert(arrays_equal(result1, expected1, sz, 3));\n\n \n\n int testArr2[] = {1, 2, 3, 2, 4, 5};\n\n int expected2[] = {1, 3, 4, 5};\n\n int* result2 = func0(testArr2, 6, &sz);\n\n assert(arrays_equal(result2, expected2, sz, 4));\n\n\n\n int testArr3[] = {1, 2, 3, 4, 5};\n\n int expected3[] = {1, 2, 3, 4, 5};\n\n int* result3 = func0(testArr3, 5, &sz);\n\n assert(arrays_equal(result3, expected3, sz, 5));\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbp\nmov %esi,%r12d\nmov %rdx,%rbx\nmovslq %esi,%rdi\nshl $0x2,%rdi\ncallq 1100 \ntest %r12d,%r12d\njle 1346 \nmov %rbp,%r11\nlea -0x1(%r12),%edx\nlea 0x4(%rbp,%rdx,4),%r8\nmov %rbp,%r9\nmov $0x0,%r10d\njmp 1315 \nadd $0x4,%r9\ncmp %r8,%r9\nje 134c \nmov (%r9),%edi\nmov %r11,%rdx\nmov $0x0,%ecx\ncmp (%rdx),%edi\nsete %sil\nmovzbl %sil,%esi\nadd %esi,%ecx\nadd $0x4,%rdx\ncmp %r8,%rdx\njne 1320 \ncmp $0x1,%ecx\njne 130c \nmovslq %r10d,%rdx\nmov %edi,(%rax,%rdx,4)\nlea 0x1(%r10),%r10d\njmp 130c \nmov $0x0,%r10d\nmov %r10d,(%rbx)\npop %rbx\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov r13d, esi\nmov rbp, rdx\nmovsxd rdi, esi\nlea r12, ds:0[rdi*4]\nmov rdi, r12; size\ncall _malloc\ntest r13d, r13d\njle short loc_1355\nlea rdi, [rbx+r12]\nmov r9, rbx\nmov r10d, 0\njmp short loc_1322\nloc_1319:\nadd r9, 4\ncmp r9, rdi\njz short loc_135B\nloc_1322:\nmov r8d, [r9]\nmov rdx, rbx\nmov ecx, 0\nloc_132D:\ncmp r8d, [rdx]\nsetz sil\nmovzx esi, sil\nadd ecx, esi\nadd rdx, 4\ncmp rdx, rdi\njnz short loc_132D\ncmp ecx, 1\njnz short loc_1319\nmovsxd rdx, r10d\nmov [rax+rdx*4], r8d\nlea r10d, [r10+1]\njmp short loc_1319\nloc_1355:\nmov r10d, 0\nloc_135B:\nmov [rbp+0], r10d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2, _DWORD *a3)\n{\n _DWORD *result; // rax\n int *v6; // rdi\n int *v7; // r9\n int v8; // r10d\n int v9; // r8d\n int *v10; // rdx\n int v11; // ecx\n\n result = malloc(4LL * a2);\n if ( a2 <= 0 )\n {\n v8 = 0;\n }\n else\n {\n v6 = &a1[a2];\n v7 = a1;\n v8 = 0;\n do\n {\n v9 = *v7;\n v10 = a1;\n v11 = 0;\n do\n v11 += v9 == *v10++;\n while ( v10 != v6 );\n if ( v11 == 1 )\n result[v8++] = v9;\n ++v7;\n }\n while ( v7 != v6 );\n }\n *a3 = v8;\n return result;\n}", + "ida_strip_asm": "sub_12DB:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov r13d, esi\nmov rbp, rdx\nmovsxd rdi, esi\nlea r12, ds:0[rdi*4]\nmov rdi, r12; size\ncall _malloc\ntest r13d, r13d\njle short loc_1355\nlea rdi, [rbx+r12]\nmov r9, rbx\nmov r10d, 0\njmp short loc_1322\nloc_1319:\nadd r9, 4\ncmp r9, rdi\njz short loc_135B\nloc_1322:\nmov r8d, [r9]\nmov rdx, rbx\nmov ecx, 0\nloc_132D:\ncmp r8d, [rdx]\nsetz sil\nmovzx esi, sil\nadd ecx, esi\nadd rdx, 4\ncmp rdx, rdi\njnz short loc_132D\ncmp ecx, 1\njnz short loc_1319\nmovsxd rdx, r10d\nmov [rax+rdx*4], r8d\nlea r10d, [r10+1]\njmp short loc_1319\nloc_1355:\nmov r10d, 0\nloc_135B:\nmov [rbp+0], r10d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_12DB(int *a1, int a2, _DWORD *a3)\n{\n _DWORD *result; // rax\n int *v6; // rdi\n int *v7; // r9\n int v8; // r10d\n int v9; // r8d\n int *v10; // rdx\n int v11; // ecx\n\n result = malloc(4LL * a2);\n if ( a2 <= 0 )\n {\n v8 = 0;\n }\n else\n {\n v6 = &a1[a2];\n v7 = a1;\n v8 = 0;\n do\n {\n v9 = *v7;\n v10 = a1;\n v11 = 0;\n do\n v11 += v9 == *v10++;\n while ( v10 != v6 );\n if ( v11 == 1 )\n result[v8++] = v9;\n ++v7;\n }\n while ( v7 != v6 );\n }\n *a3 = v8;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_12DB(int *a1, int a2, uint32_t *a3) {\n uint32_t *result;\n int *v6;\n int *v7;\n int v8;\n int v9;\n int *v10;\n int v11;\n result = malloc(4LL * a2);\n if (a2 <= 0) {\n v8 = 0;\n } else {\n v6 = &a1[a2];\n v7 = a1;\n v8 = 0;\n do {\n v9 = *v7;\n v10 = a1;\n v11 = 0;\n do\n v11 += v9 == *v10++;\n while (v10 != v6);\n if (v11 == 1) result[v8++] = v9;\n ++v7;\n } while (v7 != v6);\n }\n *a3 = v8;\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2, uint32_t *a3) {\n uint32_t *result;\n int *v6;\n int *v7;\n int v8;\n int v9;\n int *v10;\n int v11;\n result = malloc(4LL * a2);\n if (a2 <= 0) {\n v8 = 0;\n } else {\n v6 = &a1[a2];\n v7 = a1;\n v8 = 0;\n do {\n v9 = *v7;\n v10 = a1;\n v11 = 0;\n do\n v11 += v9 == *v10++;\n while (v10 != v6);\n if (v11 == 1) result[v8++] = v9;\n ++v7;\n } while (v7 != v6);\n }\n *a3 = v8;\n return result;\n}" + }, + { + "index": 572, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\nvoid print_array(int arr[], int size) {\n\n printf(\"[\");\n\n for (int i = 0; i < size; i++) {\n\n printf(\"%d\", arr[i]);\n\n if (i < size - 1) printf(\", \");\n\n }\n\n printf(\"]\\n\");\n\n}\n\n\n\nint arrays_equal(int a[], int b[], int sizeA, int sizeB) {\n\n if (sizeA != sizeB) return 0;\n\n for (int i = 0; i < sizeA; i++) { \n\n if (a[i] != b[i]) return 0;\n\n }\n\n return 1;\n\n}\n\n\n\n", + "func": "int *func0(int nums[], int size, int *returnSize) {\n int *result = (int *)malloc(size * sizeof(int));\n int k = 0;\n for (int i = 0; i < size; i++) {\n int count = 0;\n for (int j = 0; j < size; j++) {\n if (nums[i] == nums[j]) {\n count++;\n }\n }\n if (count == 1) {\n result[k++] = nums[i];\n }\n }\n *returnSize = k;\n return result;\n}", + "test": "int main() {\n\n int sz;\n\n\n\n int testArr1[] = {1, 2, 3, 2, 3, 4, 5};\n\n int expected1[] = {1, 4, 5};\n\n int* result1 = func0(testArr1, 7, &sz);\n\n assert(arrays_equal(result1, expected1, sz, 3));\n\n \n\n int testArr2[] = {1, 2, 3, 2, 4, 5};\n\n int expected2[] = {1, 3, 4, 5};\n\n int* result2 = func0(testArr2, 6, &sz);\n\n assert(arrays_equal(result2, expected2, sz, 4));\n\n\n\n int testArr3[] = {1, 2, 3, 4, 5};\n\n int expected3[] = {1, 2, 3, 4, 5};\n\n int* result3 = func0(testArr3, 5, &sz);\n\n assert(arrays_equal(result3, expected3, sz, 5));\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %rdx,%r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nmovslq %esi,%rdi\nmov %rdi,%rbp\nshl $0x2,%rdi\ncallq 1100 \ntest %ebp,%ebp\njle 15b6 \nlea -0x1(%rbp),%edx\nmov %rbx,%r10\nxor %r11d,%r11d\nlea 0x4(%rbx,%rdx,4),%r9\nmov (%r10),%r8d\nmov %rbx,%rcx\nxor %esi,%esi\nnopl 0x0(%rax,%rax,1)\nxor %edi,%edi\ncmp (%rcx),%r8d\nsete %dil\nadd $0x4,%rcx\nadd %edi,%esi\ncmp %r9,%rcx\njne 1580 \ncmp $0x1,%esi\njne 15a4 \nmovslq %r11d,%rcx\nadd $0x1,%r11d\nmov %r8d,(%rax,%rcx,4)\nadd $0x4,%r10\ncmp %r9,%r10\njne 1570 \npop %rbx\npop %rbp\nmov %r11d,(%r12)\npop %r12\nretq\nxor %r11d,%r11d\npop %rbx\npop %rbp\nmov %r11d,(%r12)\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\nmov r12, rdx\npush rbp\nmov rbp, rdi\nmovsxd rdi, esi\npush rbx\nlea rbx, ds:0[rdi*4]\nmov r13, rdi\nmov rdi, rbx; size\nsub rsp, 8\ncall _malloc\ntest r13d, r13d\njle short loc_15AC\nlea rdi, [rbp+rbx+0]\nmov r9, rbp\nxor r10d, r10d\nnop word ptr [rax+rax+00h]\nloc_1560:\nmov r8d, [r9]\nmov rdx, rbp\nxor ecx, ecx\nnop dword ptr [rax+rax+00000000h]\nloc_1570:\nxor esi, esi\ncmp r8d, [rdx]\nsetz sil\nadd rdx, 4\nadd ecx, esi\ncmp rdx, rdi\njnz short loc_1570\ncmp ecx, 1\njnz short loc_1594\nmovsxd rdx, r10d\nadd r10d, 1\nmov [rax+rdx*4], r8d\nloc_1594:\nadd r9, 4\ncmp r9, rdi\njnz short loc_1560\nmov [r12], r10d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_15AC:\nxor r10d, r10d\nmov [r12], r10d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2, _DWORD *a3)\n{\n _DWORD *result; // rax\n int *v6; // rdi\n int *v7; // r9\n int v8; // r10d\n int v9; // r8d\n int *v10; // rdx\n int v11; // ecx\n int v12; // esi\n __int64 v13; // rdx\n\n result = malloc(4LL * a2);\n if ( a2 <= 0 )\n {\n *a3 = 0;\n }\n else\n {\n v6 = &a1[a2];\n v7 = a1;\n v8 = 0;\n do\n {\n v9 = *v7;\n v10 = a1;\n v11 = 0;\n do\n {\n v12 = v9 == *v10++;\n v11 += v12;\n }\n while ( v10 != v6 );\n if ( v11 == 1 )\n {\n v13 = v8++;\n result[v13] = v9;\n }\n ++v7;\n }\n while ( v7 != v6 );\n *a3 = v8;\n }\n return result;\n}", + "ida_strip_asm": "sub_1520:\nendbr64\npush r13\npush r12\nmov r12, rdx\npush rbp\nmov rbp, rdi\nmovsxd rdi, esi\npush rbx\nlea rbx, ds:0[rdi*4]\nmov r13, rdi\nmov rdi, rbx; size\nsub rsp, 8\ncall _malloc\ntest r13d, r13d\njle short loc_15AC\nlea rdi, [rbp+rbx+0]\nmov r9, rbp\nxor r10d, r10d\nnop word ptr [rax+rax+00h]\nloc_1560:\nmov r8d, [r9]\nmov rdx, rbp\nxor ecx, ecx\nnop dword ptr [rax+rax+00000000h]\nloc_1570:\nxor esi, esi\ncmp r8d, [rdx]\nsetz sil\nadd rdx, 4\nadd ecx, esi\ncmp rdx, rdi\njnz short loc_1570\ncmp ecx, 1\njnz short loc_1594\nmovsxd rdx, r10d\nadd r10d, 1\nmov [rax+rdx*4], r8d\nloc_1594:\nadd r9, 4\ncmp r9, rdi\njnz short loc_1560\nmov [r12], r10d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_15AC:\nxor r10d, r10d\nmov [r12], r10d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1520(int *a1, int a2, _DWORD *a3)\n{\n _DWORD *result; // rax\n int *v6; // rdi\n int *v7; // r9\n int v8; // r10d\n int v9; // r8d\n int *v10; // rdx\n int v11; // ecx\n int v12; // esi\n __int64 v13; // rdx\n\n result = malloc(4LL * a2);\n if ( a2 <= 0 )\n {\n *a3 = 0;\n }\n else\n {\n v6 = &a1[a2];\n v7 = a1;\n v8 = 0;\n do\n {\n v9 = *v7;\n v10 = a1;\n v11 = 0;\n do\n {\n v12 = v9 == *v10++;\n v11 += v12;\n }\n while ( v10 != v6 );\n if ( v11 == 1 )\n {\n v13 = v8++;\n result[v13] = v9;\n }\n ++v7;\n }\n while ( v7 != v6 );\n *a3 = v8;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1520(int *a1, int a2, uint32_t *a3) {\n uint32_t *result;\n int *v6;\n int *v7;\n int v8;\n int v9;\n int *v10;\n int v11;\n int v12;\n long long v13;\n result = malloc(4LL * a2);\n if (a2 <= 0) {\n *a3 = 0;\n } else {\n v6 = &a1[a2];\n v7 = a1;\n v8 = 0;\n do {\n v9 = *v7;\n v10 = a1;\n v11 = 0;\n do {\n v12 = v9 == *v10++;\n v11 += v12;\n } while (v10 != v6);\n if (v11 == 1) {\n v13 = v8++;\n result[v13] = v9;\n }\n ++v7;\n } while (v7 != v6);\n *a3 = v8;\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2, uint32_t *a3) {\n uint32_t *result;\n int *v6;\n int *v7;\n int v8;\n int v9;\n int *v10;\n int v11;\n int v12;\n long long v13;\n result = malloc(4LL * a2);\n if (a2 <= 0) {\n *a3 = 0;\n } else {\n v6 = &a1[a2];\n v7 = a1;\n v8 = 0;\n do {\n v9 = *v7;\n v10 = a1;\n v11 = 0;\n do {\n v12 = v9 == *v10++;\n v11 += v12;\n } while (v10 != v6);\n if (v11 == 1) {\n v13 = v8++;\n result[v13] = v9;\n }\n ++v7;\n } while (v7 != v6);\n *a3 = v8;\n }\n return result;\n}" + }, + { + "index": 572, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\nvoid print_array(int arr[], int size) {\n\n printf(\"[\");\n\n for (int i = 0; i < size; i++) {\n\n printf(\"%d\", arr[i]);\n\n if (i < size - 1) printf(\", \");\n\n }\n\n printf(\"]\\n\");\n\n}\n\n\n\nint arrays_equal(int a[], int b[], int sizeA, int sizeB) {\n\n if (sizeA != sizeB) return 0;\n\n for (int i = 0; i < sizeA; i++) { \n\n if (a[i] != b[i]) return 0;\n\n }\n\n return 1;\n\n}\n\n\n\n", + "func": "int *func0(int nums[], int size, int *returnSize) {\n int *result = (int *)malloc(size * sizeof(int));\n int k = 0;\n for (int i = 0; i < size; i++) {\n int count = 0;\n for (int j = 0; j < size; j++) {\n if (nums[i] == nums[j]) {\n count++;\n }\n }\n if (count == 1) {\n result[k++] = nums[i];\n }\n }\n *returnSize = k;\n return result;\n}", + "test": "int main() {\n\n int sz;\n\n\n\n int testArr1[] = {1, 2, 3, 2, 3, 4, 5};\n\n int expected1[] = {1, 4, 5};\n\n int* result1 = func0(testArr1, 7, &sz);\n\n assert(arrays_equal(result1, expected1, sz, 3));\n\n \n\n int testArr2[] = {1, 2, 3, 2, 4, 5};\n\n int expected2[] = {1, 3, 4, 5};\n\n int* result2 = func0(testArr2, 6, &sz);\n\n assert(arrays_equal(result2, expected2, sz, 4));\n\n\n\n int testArr3[] = {1, 2, 3, 4, 5};\n\n int expected3[] = {1, 2, 3, 4, 5};\n\n int* result3 = func0(testArr3, 5, &sz);\n\n assert(arrays_equal(result3, expected3, sz, 5));\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\nmov %rdx,%r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nmovslq %esi,%rdi\nmov %rdi,%rbp\nshl $0x2,%rdi\nsub $0x8,%rsp\ncallq 1100 \nmov %rax,%r13\ntest %ebp,%ebp\njle 16ca \nmov %ebp,%edi\nlea -0x1(%rbp),%edx\nmov %ebp,%esi\nmov %rbx,%r10\nshr $0x2,%edi\nmov %rdx,%rax\nand $0xfffffffc,%esi\nxor %r11d,%r11d\nshl $0x4,%rdi\nlea 0x4(%rbx,%rdx,4),%rdx\nadd %rbx,%rdi\nnopl 0x0(%rax)\nmov (%r10),%r9d\ncmp $0x3,%eax\njbe 16c0 \nmovd %r9d,%xmm3\nmov %rbx,%rcx\npxor %xmm1,%xmm1\npshufd $0x0,%xmm3,%xmm2\nnopl (%rax)\nmovdqu (%rcx),%xmm0\nadd $0x10,%rcx\npcmpeqd %xmm2,%xmm0\npsubd %xmm0,%xmm1\ncmp %rcx,%rdi\njne 15f8 \nmovdqa %xmm1,%xmm0\nmov %esi,%r8d\npsrldq $0x8,%xmm0\npaddd %xmm0,%xmm1\nmovdqa %xmm1,%xmm0\npsrldq $0x4,%xmm0\npaddd %xmm0,%xmm1\nmovd %xmm1,%ecx\ncmp %ebp,%esi\nje 1688 \nmovslq %r8d,%r15\ncmp (%rbx,%r15,4),%r9d\nlea 0x0(,%r15,4),%r14\nsete %r15b\nmovzbl %r15b,%r15d\nadd %r15d,%ecx\nlea 0x1(%r8),%r15d\ncmp %ebp,%r15d\njge 1688 \ncmp 0x4(%rbx,%r14,1),%r9d\njne 165f \nadd $0x1,%ecx\nlea 0x2(%r8),%r15d\ncmp %ebp,%r15d\njge 1688 \ncmp 0x8(%rbx,%r14,1),%r9d\njne 1672 \nadd $0x1,%ecx\nadd $0x3,%r8d\ncmp %r8d,%ebp\njle 1688 \ncmp 0xc(%rbx,%r14,1),%r9d\njne 1688 \nadd $0x1,%ecx\nnopl (%rax)\ncmp $0x1,%ecx\njne 1699 \nmovslq %r11d,%rcx\nadd $0x1,%r11d\nmov %r9d,0x0(%r13,%rcx,4)\nadd $0x4,%r10\ncmp %rdx,%r10\njne 15d8 \nmov %r11d,(%r12)\nadd $0x8,%rsp\nmov %r13,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\nxor %r8d,%r8d\nxor %ecx,%ecx\njmpq 1632 \nxor %r11d,%r11d\njmp 16a6 \n", + "ida_asm": "func0:\nendbr64\npush r15\nmovsxd r9, esi\npush r14\nlea r14, ds:0[r9*4]\npush r13\npush r12\nmov r12, rdx\npush rbp\nmov rbp, r9\npush rbx\nmov rbx, rdi\nmov rdi, r14; size\nsub rsp, 8\ncall _malloc\nmov r13, rax\ntest ebp, ebp\njle loc_1686\nmov edx, ebp\nmov r8d, ebp\nlea r9, [r14+rbx]\nmov rdi, rbx\nshr edx, 2\nlea r11d, [rbp-1]\nand r8d, 0FFFFFFFCh\nxor r10d, r10d\nshl rdx, 4\nadd rdx, rbx\nnop word ptr [rax+rax+00h]\nloc_15B0:\nmov esi, [rdi]\ncmp r11d, 2\njbe loc_1680\nmovd xmm3, esi\nmov rax, rbx\npxor xmm1, xmm1\npshufd xmm2, xmm3, 0\nnop dword ptr [rax+00h]\nloc_15D0:\nmovdqu xmm0, xmmword ptr [rax]\nadd rax, 10h\npcmpeqd xmm0, xmm2\npsubd xmm1, xmm0\ncmp rdx, rax\njnz short loc_15D0\nmovdqa xmm0, xmm1\nmov ecx, r8d\npsrldq xmm0, 8\npaddd xmm1, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm0, 4\npaddd xmm1, xmm0\nmovd eax, xmm1\ncmp ebp, r8d\njz short loc_1643\nloc_160B:\nmovsxd r15, ecx\nlea r14, ds:0[r15*4]\ncmp esi, [rbx+r15*4]\njnz short loc_161F\nadd eax, 1\nloc_161F:\nlea r15d, [rcx+1]\ncmp ebp, r15d\njle short loc_1643\ncmp esi, [rbx+r14+4]\njnz short loc_1632\nadd eax, 1\nloc_1632:\nadd ecx, 2\ncmp ebp, ecx\njle short loc_1643\ncmp esi, [rbx+r14+8]\njnz short loc_1643\nadd eax, 1\nloc_1643:\ncmp eax, 1\njnz short loc_1654\nmovsxd rax, r10d\nadd r10d, 1\nmov [r13+rax*4+0], esi\nloc_1654:\nadd rdi, 4\ncmp r9, rdi\njnz loc_15B0\nloc_1661:\nmov [r12], r10d\nadd rsp, 8\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1680:\nxor ecx, ecx\nxor eax, eax\njmp short loc_160B\nloc_1686:\nxor r10d, r10d\njmp short loc_1661", + "ida_pseudo": "_DWORD *__fastcall func0(unsigned int *a1, int a2, _DWORD *a3)\n{\n const __m128i *v5; // rbx\n _DWORD *v6; // r13\n unsigned int *v7; // r9\n int v8; // r10d\n unsigned int v9; // esi\n const __m128i *v10; // rax\n __m128i v11; // xmm1\n __m128i v12; // xmm2\n __m128i v13; // xmm0\n int v14; // ecx\n __m128i v15; // xmm1\n int v16; // eax\n __int64 v17; // r14\n __int64 v18; // rax\n\n v5 = (const __m128i *)a1;\n v6 = malloc(4LL * a2);\n if ( a2 > 0 )\n {\n v7 = &a1[a2];\n v8 = 0;\n while ( 1 )\n {\n v9 = *a1;\n if ( (unsigned int)(a2 - 1) <= 2 )\n break;\n v10 = v5;\n v11 = 0LL;\n v12 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v9), 0);\n do\n {\n v13 = _mm_loadu_si128(v10++);\n v11 = _mm_sub_epi32(v11, _mm_cmpeq_epi32(v13, v12));\n }\n while ( &v5[(unsigned int)a2 >> 2] != v10 );\n v14 = a2 & 0x7FFFFFFC;\n v15 = _mm_add_epi32(v11, _mm_srli_si128(v11, 8));\n v16 = _mm_cvtsi128_si32(_mm_add_epi32(v15, _mm_srli_si128(v15, 4)));\n if ( a2 != (a2 & 0xFFFFFFFC) )\n goto LABEL_7;\nLABEL_15:\n if ( v16 == 1 )\n {\n v18 = v8++;\n v6[v18] = v9;\n }\n if ( v7 == ++a1 )\n goto LABEL_18;\n }\n v14 = 0;\n v16 = 0;\nLABEL_7:\n v17 = v14;\n if ( v9 == v5->m128i_i32[v17] )\n ++v16;\n if ( a2 > v14 + 1 )\n {\n if ( v9 == v5->m128i_i32[v17 + 1] )\n ++v16;\n if ( a2 > v14 + 2 && v9 == v5->m128i_i32[v17 + 2] )\n ++v16;\n }\n goto LABEL_15;\n }\n v8 = 0;\nLABEL_18:\n *a3 = v8;\n return v6;\n}", + "ida_strip_asm": "sub_1550:\nendbr64\npush r15\nmovsxd r9, esi\npush r14\nlea r14, ds:0[r9*4]\npush r13\npush r12\nmov r12, rdx\npush rbp\nmov rbp, r9\npush rbx\nmov rbx, rdi\nmov rdi, r14; size\nsub rsp, 8\ncall _malloc\nmov r13, rax\ntest ebp, ebp\njle loc_1686\nmov edx, ebp\nmov r8d, ebp\nlea r9, [r14+rbx]\nmov rdi, rbx\nshr edx, 2\nlea r11d, [rbp-1]\nand r8d, 0FFFFFFFCh\nxor r10d, r10d\nshl rdx, 4\nadd rdx, rbx\nnop word ptr [rax+rax+00h]\nloc_15B0:\nmov esi, [rdi]\ncmp r11d, 2\njbe loc_1680\nmovd xmm3, esi\nmov rax, rbx\npxor xmm1, xmm1\npshufd xmm2, xmm3, 0\nnop dword ptr [rax+00h]\nloc_15D0:\nmovdqu xmm0, xmmword ptr [rax]\nadd rax, 10h\npcmpeqd xmm0, xmm2\npsubd xmm1, xmm0\ncmp rdx, rax\njnz short loc_15D0\nmovdqa xmm0, xmm1\nmov ecx, r8d\npsrldq xmm0, 8\npaddd xmm1, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm0, 4\npaddd xmm1, xmm0\nmovd eax, xmm1\ncmp ebp, r8d\njz short loc_1643\nloc_160B:\nmovsxd r15, ecx\nlea r14, ds:0[r15*4]\ncmp esi, [rbx+r15*4]\njnz short loc_161F\nadd eax, 1\nloc_161F:\nlea r15d, [rcx+1]\ncmp ebp, r15d\njle short loc_1643\ncmp esi, [rbx+r14+4]\njnz short loc_1632\nadd eax, 1\nloc_1632:\nadd ecx, 2\ncmp ebp, ecx\njle short loc_1643\ncmp esi, [rbx+r14+8]\njnz short loc_1643\nadd eax, 1\nloc_1643:\ncmp eax, 1\njnz short loc_1654\nmovsxd rax, r10d\nadd r10d, 1\nmov [r13+rax*4+0], esi\nloc_1654:\nadd rdi, 4\ncmp r9, rdi\njnz loc_15B0\nloc_1661:\nmov [r12], r10d\nadd rsp, 8\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1680:\nxor ecx, ecx\nxor eax, eax\njmp short loc_160B\nloc_1686:\nxor r10d, r10d\njmp short loc_1661", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1550(unsigned int *a1, int a2, _DWORD *a3)\n{\n const __m128i *v5; // rbx\n _DWORD *v6; // r13\n unsigned int *v7; // r9\n int v8; // r10d\n unsigned int v9; // esi\n const __m128i *v10; // rax\n __m128i v11; // xmm1\n __m128i v12; // xmm2\n __m128i v13; // xmm0\n int v14; // ecx\n __m128i v15; // xmm1\n int v16; // eax\n __int64 v17; // r14\n __int64 v18; // rax\n\n v5 = (const __m128i *)a1;\n v6 = malloc(4LL * a2);\n if ( a2 > 0 )\n {\n v7 = &a1[a2];\n v8 = 0;\n while ( 1 )\n {\n v9 = *a1;\n if ( (unsigned int)(a2 - 1) <= 2 )\n break;\n v10 = v5;\n v11 = 0LL;\n v12 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v9), 0);\n do\n {\n v13 = _mm_loadu_si128(v10++);\n v11 = _mm_sub_epi32(v11, _mm_cmpeq_epi32(v13, v12));\n }\n while ( &v5[(unsigned int)a2 >> 2] != v10 );\n v14 = a2 & 0x7FFFFFFC;\n v15 = _mm_add_epi32(v11, _mm_srli_si128(v11, 8));\n v16 = _mm_cvtsi128_si32(_mm_add_epi32(v15, _mm_srli_si128(v15, 4)));\n if ( a2 != (a2 & 0xFFFFFFFC) )\n goto LABEL_7;\nLABEL_15:\n if ( v16 == 1 )\n {\n v18 = v8++;\n v6[v18] = v9;\n }\n if ( v7 == ++a1 )\n goto LABEL_18;\n }\n v14 = 0;\n v16 = 0;\nLABEL_7:\n v17 = v14;\n if ( v9 == v5->m128i_i32[v17] )\n ++v16;\n if ( a2 > v14 + 1 )\n {\n if ( v9 == v5->m128i_i32[v17 + 1] )\n ++v16;\n if ( a2 > v14 + 2 && v9 == v5->m128i_i32[v17 + 2] )\n ++v16;\n }\n goto LABEL_15;\n }\n v8 = 0;\nLABEL_18:\n *a3 = v8;\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1550(unsigned int *a1, int a2, uint32_t *a3) {\n const __m128i *v5;\n uint32_t *v6;\n unsigned int *v7;\n int v8;\n unsigned int v9;\n const __m128i *v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n int v14;\n __m128i v15;\n int v16;\n long long v17;\n long long v18;\n v5 = (const __m128i *)a1;\n v6 = malloc(4LL * a2);\n if (a2 > 0) {\n v7 = &a1[a2];\n v8 = 0;\n while (1) {\n v9 = *a1;\n if ((unsigned int)(a2 - 1) <= 2) break;\n v10 = v5;\n v11 = 0LL;\n v12 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v9), 0);\n do {\n v13 = _mm_loadu_si128(v10++);\n v11 = _mm_sub_epi32(v11, _mm_cmpeq_epi32(v13, v12));\n } while (&v5[(unsigned int)a2 >> 2] != v10);\n v14 = a2 & 2147483644;\n v15 = _mm_add_epi32(v11, _mm_srli_si128(v11, 8));\n v16 = _mm_cvtsi128_si32(_mm_add_epi32(v15, _mm_srli_si128(v15, 4)));\n if (a2 != (a2 & 4294967292)) goto LABEL_7;\n LABEL_15:\n if (v16 == 1) {\n v18 = v8++;\n v6[v18] = v9;\n }\n if (v7 == ++a1) goto LABEL_18;\n }\n v14 = 0;\n v16 = 0;\n LABEL_7:\n v17 = v14;\n if (v9 == v5->m128i_i32[v17]) ++v16;\n if (a2 > v14 + 1) {\n if (v9 == v5->m128i_i32[v17 + 1]) ++v16;\n if (a2 > v14 + 2 && v9 == v5->m128i_i32[v17 + 2]) ++v16;\n }\n goto LABEL_15;\n }\n v8 = 0;\nLABEL_18:\n *a3 = v8;\n return v6;\n}", + "ida_pseudo_norm": "uint32_t *func0(unsigned int *a1, int a2, uint32_t *a3) {\n const __m128i *v5;\n uint32_t *v6;\n unsigned int *v7;\n int v8;\n unsigned int v9;\n const __m128i *v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n int v14;\n __m128i v15;\n int v16;\n long long v17;\n long long v18;\n v5 = (const __m128i *)a1;\n v6 = malloc(4LL * a2);\n if (a2 > 0) {\n v7 = &a1[a2];\n v8 = 0;\n while (1) {\n v9 = *a1;\n if ((unsigned int)(a2 - 1) <= 2) break;\n v10 = v5;\n v11 = 0LL;\n v12 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v9), 0);\n do {\n v13 = _mm_loadu_si128(v10++);\n v11 = _mm_sub_epi32(v11, _mm_cmpeq_epi32(v13, v12));\n } while (&v5[(unsigned int)a2 >> 2] != v10);\n v14 = a2 & 2147483644;\n v15 = _mm_add_epi32(v11, _mm_srli_si128(v11, 8));\n v16 = _mm_cvtsi128_si32(_mm_add_epi32(v15, _mm_srli_si128(v15, 4)));\n if (a2 != (a2 & 4294967292)) goto LABEL_7;\n LABEL_15:\n if (v16 == 1) {\n v18 = v8++;\n v6[v18] = v9;\n }\n if (v7 == ++a1) goto LABEL_18;\n }\n v14 = 0;\n v16 = 0;\n LABEL_7:\n v17 = v14;\n if (v9 == v5->m128i_i32[v17]) ++v16;\n if (a2 > v14 + 1) {\n if (v9 == v5->m128i_i32[v17 + 1]) ++v16;\n if (a2 > v14 + 2 && v9 == v5->m128i_i32[v17 + 2]) ++v16;\n }\n goto LABEL_15;\n }\n v8 = 0;\nLABEL_18:\n *a3 = v8;\n return v6;\n}" + }, + { + "index": 573, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int list_data[], int size) {\n int p = 1;\n int exists[101] = {0};\n for (int i = 0; i < size; i++) {\n if (!exists[list_data[i]]) {\n p *= list_data[i];\n exists[list_data[i]] = 1;\n }\n }\n return p;\n}", + "test": "int main() {\n\n int data1[] = {10, 20, 30, 40, 20, 50, 60, 40};\n\n assert(func0(data1, 8) == 720000000);\n\n\n\n int data2[] = {1, 2, 3, 1};\n\n assert(func0(data2, 4) == 6);\n\n\n\n int data3[] = {7, 8, 9, 0, 1, 1};\n\n assert(func0(data3, 6) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x1c0,%rsp\nmov %rdi,-0x1b8(%rbp)\nmov %esi,-0x1bc(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovl $0x1,-0x1a8(%rbp)\nlea -0x1a0(%rbp),%rdx\nmov $0x0,%eax\nmov $0x32,%ecx\nmov %rdx,%rdi\nrep stos %rax,%es:(%rdi)\nmov %rdi,%rdx\nmov %eax,(%rdx)\nadd $0x4,%rdx\nmovl $0x0,-0x1a4(%rbp)\njmpq 1251 \nmov -0x1a4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x1b8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncltq\nmov -0x1a0(%rbp,%rax,4),%eax\ntest %eax,%eax\njne 124a \nmov -0x1a4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x1b8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov -0x1a8(%rbp),%edx\nimul %edx,%eax\nmov %eax,-0x1a8(%rbp)\nmov -0x1a4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x1b8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncltq\nmovl $0x1,-0x1a0(%rbp,%rax,4)\naddl $0x1,-0x1a4(%rbp)\nmov -0x1a4(%rbp),%eax\ncmp -0x1bc(%rbp),%eax\njl 11cd \nmov -0x1a8(%rbp),%eax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 127d \ncallq 1060 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 1C0h\nmov [rbp+var_1B8], rdi\nmov [rbp+var_1BC], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_1A8], 1\nlea rdx, [rbp+var_1A0]\nmov eax, 0\nmov ecx, 32h ; '2'\nmov rdi, rdx\nrep stosq\nmov rdx, rdi\nmov [rdx], eax\nadd rdx, 4\nmov [rbp+var_1A4], 0\njmp loc_1251\nloc_11CD:\nmov eax, [rbp+var_1A4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_1B8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nmov eax, [rbp+rax*4+var_1A0]\ntest eax, eax\njnz short loc_124A\nmov eax, [rbp+var_1A4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_1B8]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_1A8]\nimul eax, edx\nmov [rbp+var_1A8], eax\nmov eax, [rbp+var_1A4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_1B8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nmov [rbp+rax*4+var_1A0], 1\nloc_124A:\nadd [rbp+var_1A4], 1\nloc_1251:\nmov eax, [rbp+var_1A4]\ncmp eax, [rbp+var_1BC]\njl loc_11CD\nmov eax, [rbp+var_1A8]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_127D\ncall ___stack_chk_fail\nlocret_127D:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+18h] [rbp-1A8h]\n int i; // [rsp+1Ch] [rbp-1A4h]\n _DWORD v5[102]; // [rsp+20h] [rbp-1A0h] BYREF\n unsigned __int64 v6; // [rsp+1B8h] [rbp-8h]\n\n v6 = __readfsqword(0x28u);\n v3 = 1;\n memset(v5, 0, 404);\n for ( i = 0; i < a2; ++i )\n {\n if ( !v5[*(int *)(4LL * i + a1)] )\n {\n v3 *= *(_DWORD *)(4LL * i + a1);\n v5[*(int *)(4LL * i + a1)] = 1;\n }\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 1C0h\nmov [rbp+var_1B8], rdi\nmov [rbp+var_1BC], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_1A8], 1\nlea rdx, [rbp+var_1A0]\nmov eax, 0\nmov ecx, 32h ; '2'\nmov rdi, rdx\nrep stosq\nmov rdx, rdi\nmov [rdx], eax\nadd rdx, 4\nmov [rbp+var_1A4], 0\njmp loc_1251\nloc_11CD:\nmov eax, [rbp+var_1A4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_1B8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nmov eax, [rbp+rax*4+var_1A0]\ntest eax, eax\njnz short loc_124A\nmov eax, [rbp+var_1A4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_1B8]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_1A8]\nimul eax, edx\nmov [rbp+var_1A8], eax\nmov eax, [rbp+var_1A4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_1B8]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nmov [rbp+rax*4+var_1A0], 1\nloc_124A:\nadd [rbp+var_1A4], 1\nloc_1251:\nmov eax, [rbp+var_1A4]\ncmp eax, [rbp+var_1BC]\njl loc_11CD\nmov eax, [rbp+var_1A8]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_127D\ncall ___stack_chk_fail\nlocret_127D:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+18h] [rbp-1A8h]\n int i; // [rsp+1Ch] [rbp-1A4h]\n _DWORD v5[102]; // [rsp+20h] [rbp-1A0h] BYREF\n unsigned __int64 v6; // [rsp+1B8h] [rbp-8h]\n\n v6 = __readfsqword(0x28u);\n v3 = 1;\n memset(v5, 0, 404);\n for ( i = 0; i < a2; ++i )\n {\n if ( !v5[*(int *)(4LL * i + a1)] )\n {\n v3 *= *(_DWORD *)(4LL * i + a1);\n v5[*(int *)(4LL * i + a1)] = 1;\n }\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n unsigned int v3;\n int i;\n uint32_t v5[102];\n unsigned long long v6;\n v6 = __readfsqword(40u);\n v3 = 1;\n memset(v5, 0, 404);\n for (i = 0; i < a2; ++i) {\n if (!v5[*(int *)(4LL * i + a1)]) {\n v3 *= *(uint32_t *)(4LL * i + a1);\n v5[*(int *)(4LL * i + a1)] = 1;\n }\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n uint32_t v5[102];\n unsigned long long v6;\n v6 = __readfsqword(40u);\n v3 = 1;\n memset(v5, 0, 404);\n for (i = 0; i < a2; ++i) {\n if (!v5[*(int *)(4LL * i + a1)]) {\n v3 *= *(uint32_t *)(4LL * i + a1);\n v5[*(int *)(4LL * i + a1)] = 1;\n }\n }\n return v3;\n}" + }, + { + "index": 573, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int list_data[], int size) {\n int p = 1;\n int exists[101] = {0};\n for (int i = 0; i < size; i++) {\n if (!exists[list_data[i]]) {\n p *= list_data[i];\n exists[list_data[i]] = 1;\n }\n }\n return p;\n}", + "test": "int main() {\n\n int data1[] = {10, 20, 30, 40, 20, 50, 60, 40};\n\n assert(func0(data1, 8) == 720000000);\n\n\n\n int data2[] = {1, 2, 3, 1};\n\n assert(func0(data2, 4) == 6);\n\n\n\n int data3[] = {7, 8, 9, 0, 1, 1};\n\n assert(func0(data3, 6) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x1a8,%rsp\nmov %rdi,%rdx\nmov %fs:0x28,%rax\nmov %rax,0x198(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nmov $0x32,%ecx\nrep stos %rax,%es:(%rdi)\nmovl $0x0,(%rdi)\ntest %esi,%esi\njle 11d1 \nmov %rdx,%rax\nlea -0x1(%rsi),%ecx\nlea 0x4(%rdx,%rcx,4),%rdi\nmov $0x1,%esi\njmp 11ba \nadd $0x4,%rax\ncmp %rdi,%rax\nje 11d6 \nmov (%rax),%edx\nmovslq %edx,%rcx\ncmpl $0x0,(%rsp,%rcx,4)\njne 11b1 \nimul %edx,%esi\nmovl $0x1,(%rsp,%rcx,4)\njmp 11b1 \nmov $0x1,%esi\nmov 0x198(%rsp),%rax\nxor %fs:0x28,%rax\njne 11f3 \nmov %esi,%eax\nadd $0x1a8,%rsp\nretq\ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 1A8h\nmov rdx, rdi\nmov rax, fs:28h\nmov [rsp+1A8h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nmov ecx, 32h ; '2'\nrep stosq\nmov dword ptr [rdi], 0\ntest esi, esi\njle short loc_11D0\nmov rax, rdx\nmovsxd rsi, esi\nlea rdi, [rdx+rsi*4]\nmov esi, 1\njmp short loc_11B9\nloc_11B0:\nadd rax, 4\ncmp rax, rdi\njz short loc_11D5\nloc_11B9:\nmov edx, [rax]\nmovsxd rcx, edx\ncmp [rsp+rcx*4+1A8h+var_1A8], 0\njnz short loc_11B0\nimul esi, edx\nmov [rsp+rcx*4+1A8h+var_1A8], 1\njmp short loc_11B0\nloc_11D0:\nmov esi, 1\nloc_11D5:\nmov rax, [rsp+1A8h+var_10]\nsub rax, fs:28h\njnz short loc_11F2\nmov eax, esi\nadd rsp, 1A8h\nretn\nloc_11F2:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int *v2; // rax\n int *v3; // rdi\n unsigned int v4; // esi\n int v5; // edx\n _DWORD v7[102]; // [rsp+0h] [rbp-1A8h] BYREF\n unsigned __int64 v8; // [rsp+198h] [rbp-10h]\n\n v8 = __readfsqword(0x28u);\n memset(v7, 0, 404);\n if ( a2 <= 0 )\n {\n return 1;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 1;\n do\n {\n v5 = *v2;\n if ( !v7[*v2] )\n {\n v4 *= v5;\n v7[v5] = 1;\n }\n ++v2;\n }\n while ( v2 != v3 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nsub rsp, 1A8h\nmov rdx, rdi\nmov rax, fs:28h\nmov [rsp+1A8h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nmov ecx, 32h ; '2'\nrep stosq\nmov dword ptr [rdi], 0\ntest esi, esi\njle short loc_11D0\nmov rax, rdx\nmovsxd rsi, esi\nlea rdi, [rdx+rsi*4]\nmov esi, 1\njmp short loc_11B9\nloc_11B0:\nadd rax, 4\ncmp rax, rdi\njz short loc_11D5\nloc_11B9:\nmov edx, [rax]\nmovsxd rcx, edx\ncmp [rsp+rcx*4+1A8h+var_1A8], 0\njnz short loc_11B0\nimul esi, edx\nmov [rsp+rcx*4+1A8h+var_1A8], 1\njmp short loc_11B0\nloc_11D0:\nmov esi, 1\nloc_11D5:\nmov rax, [rsp+1A8h+var_10]\nsub rax, fs:28h\njnz short loc_11F2\nmov eax, esi\nadd rsp, 1A8h\nretn\nloc_11F2:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int *a1, int a2)\n{\n int *v2; // rax\n int *v3; // rdi\n unsigned int v4; // esi\n int v5; // edx\n _DWORD v7[102]; // [rsp+0h] [rbp-1A8h] BYREF\n unsigned __int64 v8; // [rsp+198h] [rbp-10h]\n\n v8 = __readfsqword(0x28u);\n memset(v7, 0, 404);\n if ( a2 <= 0 )\n {\n return 1;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 1;\n do\n {\n v5 = *v2;\n if ( !v7[*v2] )\n {\n v4 *= v5;\n v7[v5] = 1;\n }\n ++v2;\n }\n while ( v2 != v3 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int *a1, int a2) {\n int *v2;\n int *v3;\n unsigned int v4;\n int v5;\n uint32_t v7[102];\n unsigned long long v8;\n v8 = __readfsqword(40u);\n memset(v7, 0, 404);\n if (a2 <= 0) {\n return 1;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 1;\n do {\n v5 = *v2;\n if (!v7[*v2]) {\n v4 *= v5;\n v7[v5] = 1;\n }\n ++v2;\n } while (v2 != v3);\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int *v2;\n int *v3;\n unsigned int v4;\n int v5;\n uint32_t v7[102];\n unsigned long long v8;\n v8 = __readfsqword(40u);\n memset(v7, 0, 404);\n if (a2 <= 0) {\n return 1;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 1;\n do {\n v5 = *v2;\n if (!v7[*v2]) {\n v4 *= v5;\n v7[v5] = 1;\n }\n ++v2;\n } while (v2 != v3);\n }\n return v4;\n}" + }, + { + "index": 573, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int list_data[], int size) {\n int p = 1;\n int exists[101] = {0};\n for (int i = 0; i < size; i++) {\n if (!exists[list_data[i]]) {\n p *= list_data[i];\n exists[list_data[i]] = 1;\n }\n }\n return p;\n}", + "test": "int main() {\n\n int data1[] = {10, 20, 30, 40, 20, 50, 60, 40};\n\n assert(func0(data1, 8) == 720000000);\n\n\n\n int data2[] = {1, 2, 3, 1};\n\n assert(func0(data2, 4) == 6);\n\n\n\n int data3[] = {7, 8, 9, 0, 1, 1};\n\n assert(func0(data3, 6) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x1a8,%rsp\nmov %rdi,%rdx\nmov $0x32,%ecx\nmov %fs:0x28,%rax\nmov %rax,0x198(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nrep stos %rax,%es:(%rdi)\nmovl $0x0,(%rdi)\ntest %esi,%esi\njle 1430 \nlea -0x1(%rsi),%eax\nmov %rdx,%rdi\nmov $0x1,%r8d\nlea 0x4(%rdx,%rax,4),%rcx\nnopw 0x0(%rax,%rax,1)\nmovslq (%rdi),%rax\nmov (%rsp,%rax,4),%esi\ntest %esi,%esi\njne 1405 \nimul %eax,%r8d\nmovl $0x1,(%rsp,%rax,4)\nadd $0x4,%rdi\ncmp %rcx,%rdi\njne 13f0 \nmov 0x198(%rsp),%rax\nxor %fs:0x28,%rax\njne 1438 \nmov %r8d,%eax\nadd $0x1a8,%rsp\nretq\nnopl 0x0(%rax)\nmov $0x1,%r8d\njmp 140e \ncallq 1060 <__stack_chk_fail@plt>\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 1A8h\nmov rdx, rdi\nmov ecx, 32h ; '2'\nmov rax, fs:28h\nmov [rsp+1A8h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\nmov dword ptr [rdi], 0\ntest esi, esi\njle short loc_1308\nmovsxd rsi, esi\nmov rdi, rdx\nmov ecx, 1\nlea rsi, [rdx+rsi*4]\nnop dword ptr [rax]\nloc_12C8:\nmovsxd rax, dword ptr [rdi]\nmov r8d, [rsp+rax*4+1A8h+var_1A8]\ntest r8d, r8d\njnz short loc_12DE\nimul ecx, eax\nmov [rsp+rax*4+1A8h+var_1A8], 1\nloc_12DE:\nadd rdi, 4\ncmp rdi, rsi\njnz short loc_12C8\nloc_12E7:\nmov rax, [rsp+1A8h+var_10]\nsub rax, fs:28h\njnz short loc_130F\nmov eax, ecx\nadd rsp, 1A8h\nretn\nloc_1308:\nmov ecx, 1\njmp short loc_12E7\nloc_130F:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n unsigned int v2; // ecx\n int *v3; // rsi\n __int64 v4; // rax\n _DWORD v6[102]; // [rsp+0h] [rbp-1A8h] BYREF\n unsigned __int64 v7; // [rsp+198h] [rbp-10h]\n\n v7 = __readfsqword(0x28u);\n memset(v6, 0, 404);\n if ( a2 <= 0 )\n {\n return 1;\n }\n else\n {\n v2 = 1;\n v3 = &a1[a2];\n do\n {\n v4 = *a1;\n if ( !v6[v4] )\n {\n v2 *= (_DWORD)v4;\n v6[v4] = 1;\n }\n ++a1;\n }\n while ( a1 != v3 );\n }\n return v2;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\nsub rsp, 1A8h\nmov rdx, rdi\nmov ecx, 32h ; '2'\nmov rax, fs:28h\nmov [rsp+1A8h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\nmov dword ptr [rdi], 0\ntest esi, esi\njle short loc_1308\nmovsxd rsi, esi\nmov rdi, rdx\nmov ecx, 1\nlea rsi, [rdx+rsi*4]\nnop dword ptr [rax]\nloc_12C8:\nmovsxd rax, dword ptr [rdi]\nmov r8d, [rsp+rax*4+1A8h+var_1A8]\ntest r8d, r8d\njnz short loc_12DE\nimul ecx, eax\nmov [rsp+rax*4+1A8h+var_1A8], 1\nloc_12DE:\nadd rdi, 4\ncmp rdi, rsi\njnz short loc_12C8\nloc_12E7:\nmov rax, [rsp+1A8h+var_10]\nsub rax, fs:28h\njnz short loc_130F\nmov eax, ecx\nadd rsp, 1A8h\nretn\nloc_1308:\nmov ecx, 1\njmp short loc_12E7\nloc_130F:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1280(int *a1, int a2)\n{\n unsigned int v2; // ecx\n int *v3; // rsi\n __int64 v4; // rax\n _DWORD v6[102]; // [rsp+0h] [rbp-1A8h] BYREF\n unsigned __int64 v7; // [rsp+198h] [rbp-10h]\n\n v7 = __readfsqword(0x28u);\n memset(v6, 0, 404);\n if ( a2 <= 0 )\n {\n return 1;\n }\n else\n {\n v2 = 1;\n v3 = &a1[a2];\n do\n {\n v4 = *a1;\n if ( !v6[v4] )\n {\n v2 *= (_DWORD)v4;\n v6[v4] = 1;\n }\n ++a1;\n }\n while ( a1 != v3 );\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1280(int *a1, int a2) {\n unsigned int v2;\n int *v3;\n long long v4;\n uint32_t v6[102];\n unsigned long long v7;\n v7 = __readfsqword(40u);\n memset(v6, 0, 404);\n if (a2 <= 0) {\n return 1;\n } else {\n v2 = 1;\n v3 = &a1[a2];\n do {\n v4 = *a1;\n if (!v6[v4]) {\n v2 *= (uint32_t)v4;\n v6[v4] = 1;\n }\n ++a1;\n } while (a1 != v3);\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n unsigned int v2;\n int *v3;\n long long v4;\n uint32_t v6[102];\n unsigned long long v7;\n v7 = __readfsqword(40u);\n memset(v6, 0, 404);\n if (a2 <= 0) {\n return 1;\n } else {\n v2 = 1;\n v3 = &a1[a2];\n do {\n v4 = *a1;\n if (!v6[v4]) {\n v2 *= (uint32_t)v4;\n v6[v4] = 1;\n }\n ++a1;\n } while (a1 != v3);\n }\n return v2;\n}" + }, + { + "index": 573, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int list_data[], int size) {\n int p = 1;\n int exists[101] = {0};\n for (int i = 0; i < size; i++) {\n if (!exists[list_data[i]]) {\n p *= list_data[i];\n exists[list_data[i]] = 1;\n }\n }\n return p;\n}", + "test": "int main() {\n\n int data1[] = {10, 20, 30, 40, 20, 50, 60, 40};\n\n assert(func0(data1, 8) == 720000000);\n\n\n\n int data2[] = {1, 2, 3, 1};\n\n assert(func0(data2, 4) == 6);\n\n\n\n int data3[] = {7, 8, 9, 0, 1, 1};\n\n assert(func0(data3, 6) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x1a8,%rsp\nmov %rdi,%rdx\nmov $0x32,%ecx\nmov %fs:0x28,%rax\nmov %rax,0x198(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nrep stos %rax,%es:(%rdi)\nmovl $0x0,(%rdi)\ntest %esi,%esi\njle 14a0 \nlea -0x1(%rsi),%eax\nmov %rdx,%rdi\nmov $0x1,%r8d\nlea 0x4(%rdx,%rax,4),%rcx\nnopw 0x0(%rax,%rax,1)\nmovslq (%rdi),%rax\nmov (%rsp,%rax,4),%esi\ntest %esi,%esi\njne 1475 \nimul %eax,%r8d\nmovl $0x1,(%rsp,%rax,4)\nadd $0x4,%rdi\ncmp %rcx,%rdi\njne 1460 \nmov 0x198(%rsp),%rax\nxor %fs:0x28,%rax\njne 14a8 \nmov %r8d,%eax\nadd $0x1a8,%rsp\nretq\nnopl 0x0(%rax)\nmov $0x1,%r8d\njmp 147e \ncallq 1060 <__stack_chk_fail@plt>\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 1A8h\nmov rdx, rdi\nmov ecx, 32h ; '2'\nmov rax, fs:28h\nmov [rsp+1A8h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\nmov dword ptr [rdi], 0\ntest esi, esi\njle short loc_11E8\nmovsxd rsi, esi\nmov rdi, rdx\nmov ecx, 1\nlea rsi, [rdx+rsi*4]\nnop dword ptr [rax]\nloc_11A8:\nmovsxd rax, dword ptr [rdi]\nmov r8d, [rsp+rax*4+1A8h+var_1A8]\ntest r8d, r8d\njnz short loc_11BE\nimul ecx, eax\nmov [rsp+rax*4+1A8h+var_1A8], 1\nloc_11BE:\nadd rdi, 4\ncmp rdi, rsi\njnz short loc_11A8\nloc_11C7:\nmov rax, [rsp+1A8h+var_10]\nsub rax, fs:28h\njnz short loc_11EF\nmov eax, ecx\nadd rsp, 1A8h\nretn\nloc_11E8:\nmov ecx, 1\njmp short loc_11C7\nloc_11EF:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n unsigned int v2; // ecx\n int *v3; // rsi\n __int64 v4; // rax\n _DWORD v6[102]; // [rsp+0h] [rbp-1A8h] BYREF\n unsigned __int64 v7; // [rsp+198h] [rbp-10h]\n\n v7 = __readfsqword(0x28u);\n memset(v6, 0, 404);\n if ( a2 <= 0 )\n {\n return 1;\n }\n else\n {\n v2 = 1;\n v3 = &a1[a2];\n do\n {\n v4 = *a1;\n if ( !v6[v4] )\n {\n v2 *= (_DWORD)v4;\n v6[v4] = 1;\n }\n ++a1;\n }\n while ( a1 != v3 );\n }\n return v2;\n}", + "ida_strip_asm": "sub_1160:\nendbr64\nsub rsp, 1A8h\nmov rdx, rdi\nmov ecx, 32h ; '2'\nmov rax, fs:28h\nmov [rsp+1A8h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\nmov dword ptr [rdi], 0\ntest esi, esi\njle short loc_11E8\nmovsxd rsi, esi\nmov rdi, rdx\nmov ecx, 1\nlea rsi, [rdx+rsi*4]\nnop dword ptr [rax]\nloc_11A8:\nmovsxd rax, dword ptr [rdi]\nmov r8d, [rsp+rax*4+1A8h+var_1A8]\ntest r8d, r8d\njnz short loc_11BE\nimul ecx, eax\nmov [rsp+rax*4+1A8h+var_1A8], 1\nloc_11BE:\nadd rdi, 4\ncmp rdi, rsi\njnz short loc_11A8\nloc_11C7:\nmov rax, [rsp+1A8h+var_10]\nsub rax, fs:28h\njnz short loc_11EF\nmov eax, ecx\nadd rsp, 1A8h\nretn\nloc_11E8:\nmov ecx, 1\njmp short loc_11C7\nloc_11EF:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1160(int *a1, int a2)\n{\n unsigned int v2; // ecx\n int *v3; // rsi\n __int64 v4; // rax\n _DWORD v6[102]; // [rsp+0h] [rbp-1A8h] BYREF\n unsigned __int64 v7; // [rsp+198h] [rbp-10h]\n\n v7 = __readfsqword(0x28u);\n memset(v6, 0, 404);\n if ( a2 <= 0 )\n {\n return 1;\n }\n else\n {\n v2 = 1;\n v3 = &a1[a2];\n do\n {\n v4 = *a1;\n if ( !v6[v4] )\n {\n v2 *= (_DWORD)v4;\n v6[v4] = 1;\n }\n ++a1;\n }\n while ( a1 != v3 );\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1160(int *a1, int a2) {\n unsigned int v2;\n int *v3;\n long long v4;\n uint32_t v6[102];\n unsigned long long v7;\n v7 = __readfsqword(40u);\n memset(v6, 0, 404);\n if (a2 <= 0) {\n return 1;\n } else {\n v2 = 1;\n v3 = &a1[a2];\n do {\n v4 = *a1;\n if (!v6[v4]) {\n v2 *= (uint32_t)v4;\n v6[v4] = 1;\n }\n ++a1;\n } while (a1 != v3);\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n unsigned int v2;\n int *v3;\n long long v4;\n uint32_t v6[102];\n unsigned long long v7;\n v7 = __readfsqword(40u);\n memset(v6, 0, 404);\n if (a2 <= 0) {\n return 1;\n } else {\n v2 = 1;\n v3 = &a1[a2];\n do {\n v4 = *a1;\n if (!v6[v4]) {\n v2 *= (uint32_t)v4;\n v6[v4] = 1;\n }\n ++a1;\n } while (a1 != v3);\n }\n return v2;\n}" + }, + { + "index": 574, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "double func0(double r, double h) {\n double surfacearea = ((2 * 3.1415 * r * r) + (2 * 3.1415 * r * h));\n return surfacearea;\n}", + "test": "int main() {\n\n assert(func0(10, 5) == 942.45);\n\n assert(func0(4, 5) == 226.18800000000002);\n\n assert(func0(4, 10) == 351.848);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmovsd %xmm0,-0x18(%rbp)\nmovsd %xmm1,-0x20(%rbp)\nmovsd -0x18(%rbp),%xmm1\nmovsd 0xf38(%rip),%xmm0\nmulsd %xmm1,%xmm0\nmovapd %xmm0,%xmm1\nmulsd -0x18(%rbp),%xmm1\nmovsd -0x18(%rbp),%xmm2\nmovsd 0xf1e(%rip),%xmm0\nmulsd %xmm2,%xmm0\nmulsd -0x20(%rbp),%xmm0\naddsd %xmm1,%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmovsd -0x8(%rbp),%xmm0\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmovsd [rbp+var_18], xmm0\nmovsd [rbp+var_20], xmm1\nmovsd xmm1, [rbp+var_18]\nmovsd xmm0, cs:qword_2080\nmulsd xmm0, xmm1\nmovapd xmm1, xmm0\nmulsd xmm1, [rbp+var_18]\nmovsd xmm2, [rbp+var_18]\nmovsd xmm0, cs:qword_2080\nmulsd xmm0, xmm2\nmulsd xmm0, [rbp+var_20]\naddsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "double __fastcall func0(double a1, double a2)\n{\n return 6.283 * a1 * a2 + 6.283 * a1 * a1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmovsd [rbp+var_18], xmm0\nmovsd [rbp+var_20], xmm1\nmovsd xmm1, [rbp+var_18]\nmovsd xmm0, cs:qword_2080\nmulsd xmm0, xmm1\nmovapd xmm1, xmm0\nmulsd xmm1, [rbp+var_18]\nmovsd xmm2, [rbp+var_18]\nmovsd xmm0, cs:qword_2080\nmulsd xmm0, xmm2\nmulsd xmm0, [rbp+var_20]\naddsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "double __fastcall sub_1149(double a1, double a2)\n{\n return 6.283 * a1 * a2 + 6.283 * a1 * a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1149(double a1, double a2) {\n return 6.283 * a1 * a2 + 6.283 * a1 * a1;\n}", + "ida_pseudo_norm": "double func0(double a1, double a2) { return 6.283 * a1 * a2 + 6.283 * a1 * a1; }" + }, + { + "index": 575, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int A, int N, int L, int R) {\n int count = 0;\n int i;\n for (i = L; i <= R; i++) {\n if (i % A != 0) {\n count += 1;\n }\n if (count == N) {\n break;\n }\n }\n return i;\n}", + "test": "int main() {\n\n assert(func0(2, 3, 1, 10) == 5);\n\n assert(func0(3, 6, 4, 20) == 11);\n\n assert(func0(5, 10, 4, 20) == 16);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov %edx,-0x1c(%rbp)\nmov %ecx,-0x20(%rbp)\nmovl $0x0,-0x8(%rbp)\nmov -0x1c(%rbp),%eax\nmov %eax,-0x4(%rbp)\njmp 1189 \nmov -0x4(%rbp),%eax\ncltd\nidivl -0x14(%rbp)\nmov %edx,%eax\ntest %eax,%eax\nje 117d \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x18(%rbp),%eax\nje 1193 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x20(%rbp),%eax\njle 116c \njmp 1194 \nmov -0x4(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov [rbp+var_20], ecx\nmov [rbp+var_8], 0\nmov eax, [rbp+var_1C]\nmov [rbp+var_4], eax\njmp short loc_1189\nloc_116C:\nmov eax, [rbp+var_4]\ncdq\nidiv [rbp+var_14]\nmov eax, edx\ntest eax, eax\njz short loc_117D\nadd [rbp+var_8], 1\nloc_117D:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_18]\njz short loc_1193\nadd [rbp+var_4], 1\nloc_1189:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_20]\njle short loc_116C\njmp short loc_1194\nloc_1193:\nnop\nloc_1194:\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, signed int a3, signed int a4)\n{\n int v5; // [rsp+18h] [rbp-8h]\n\n v5 = 0;\n while ( a3 <= a4 )\n {\n if ( a3 % a1 )\n ++v5;\n if ( v5 == a2 )\n break;\n ++a3;\n }\n return (unsigned int)a3;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov [rbp+var_20], ecx\nmov [rbp+var_8], 0\nmov eax, [rbp+var_1C]\nmov [rbp+var_4], eax\njmp short loc_1189\nloc_116C:\nmov eax, [rbp+var_4]\ncdq\nidiv [rbp+var_14]\nmov eax, edx\ntest eax, eax\njz short loc_117D\nadd [rbp+var_8], 1\nloc_117D:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_18]\njz short loc_1193\nadd [rbp+var_4], 1\nloc_1189:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_20]\njle short loc_116C\njmp short loc_1194\nloc_1193:\nnop\nloc_1194:\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2, signed int a3, signed int a4)\n{\n int v5; // [rsp+18h] [rbp-8h]\n\n v5 = 0;\n while ( a3 <= a4 )\n {\n if ( a3 % a1 )\n ++v5;\n if ( v5 == a2 )\n break;\n ++a3;\n }\n return (unsigned int)a3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2, signed int a3, signed int a4) {\n int v5;\n v5 = 0;\n while (a3 <= a4) {\n if (a3 % a1) ++v5;\n if (v5 == a2) break;\n ++a3;\n }\n return (unsigned int)a3;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, signed int a3, signed int a4) {\n int v5;\n v5 = 0;\n while (a3 <= a4) {\n if (a3 % a1) ++v5;\n if (v5 == a2) break;\n ++a3;\n }\n return (unsigned int)a3;\n}" + }, + { + "index": 575, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int A, int N, int L, int R) {\n int count = 0;\n int i;\n for (i = L; i <= R; i++) {\n if (i % A != 0) {\n count += 1;\n }\n if (count == N) {\n break;\n }\n }\n return i;\n}", + "test": "int main() {\n\n assert(func0(2, 3, 1, 10) == 5);\n\n assert(func0(3, 6, 4, 20) == 11);\n\n assert(func0(5, 10, 4, 20) == 16);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %edx,%r8d\ncmp %ecx,%edx\njg 1179 \nmov $0x0,%r9d\nmov %r8d,%eax\ncltd\nidiv %edi\ncmp $0x1,%edx\nsbb $0xffffffff,%r9d\ncmp %esi,%r9d\nje 117c \nadd $0x1,%r8d\ncmp %r8d,%ecx\njge 115a \nmov %r8d,%eax\nretq\nmov %edx,%eax\nretq\nmov %r8d,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov r8d, edx\ncmp edx, ecx\njg short loc_1179\nmov r9d, 0\nloc_115A:\nmov eax, r8d\ncdq\nidiv edi\ncmp edx, 1\nsbb r9d, 0FFFFFFFFh\ncmp r9d, esi\njz short loc_117C\nadd r8d, 1\ncmp ecx, r8d\njge short loc_115A\nmov eax, r8d\nretn\nloc_1179:\nmov eax, edx\nretn\nloc_117C:\nmov eax, r8d\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, unsigned int a3, int a4)\n{\n unsigned int v4; // r8d\n int v5; // r9d\n\n v4 = a3;\n if ( (int)a3 > a4 )\n return a3;\n v5 = 0;\n while ( 1 )\n {\n v5 -= ((int)v4 % a1 == 0) - 1;\n if ( v5 == a2 )\n break;\n if ( a4 < (int)++v4 )\n return v4;\n }\n return v4;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmov r8d, edx\ncmp edx, ecx\njg short loc_1179\nmov r9d, 0\nloc_115A:\nmov eax, r8d\ncdq\nidiv edi\ncmp edx, 1\nsbb r9d, 0FFFFFFFFh\ncmp r9d, esi\njz short loc_117C\nadd r8d, 1\ncmp ecx, r8d\njge short loc_115A\nmov eax, r8d\nretn\nloc_1179:\nmov eax, edx\nretn\nloc_117C:\nmov eax, r8d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2, unsigned int a3, int a4)\n{\n unsigned int v4; // r8d\n int v5; // r9d\n\n v4 = a3;\n if ( (int)a3 > a4 )\n return a3;\n v5 = 0;\n while ( 1 )\n {\n v5 -= ((int)v4 % a1 == 0) - 1;\n if ( v5 == a2 )\n break;\n if ( a4 < (int)++v4 )\n return v4;\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2, unsigned int a3, int a4) {\n unsigned int v4;\n int v5;\n v4 = a3;\n if ((int)a3 > a4) return a3;\n v5 = 0;\n while (1) {\n v5 -= ((int)v4 % a1 == 0) - 1;\n if (v5 == a2) break;\n if (a4 < (int)++v4) return v4;\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, unsigned int a3, int a4) {\n unsigned int v4;\n int v5;\n v4 = a3;\n if ((int)a3 > a4) return a3;\n v5 = 0;\n while (1) {\n v5 -= ((int)v4 % a1 == 0) - 1;\n if (v5 == a2) break;\n if (a4 < (int)++v4) return v4;\n }\n return v4;\n}" + }, + { + "index": 576, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int A[], int B[], int n, int m) {\n int i = 0, j = 0;\n while (i < n && j < m) {\n if (A[i] == B[j]) {\n i++;\n j++;\n if (j == m) {\n return true;\n }\n } else {\n i = i - j + 1;\n j = 0;\n }\n }\n return false;\n}", + "test": "int main() {\n\n int A1[] = {1, 4, 3, 5};\n\n int B1[] = {1, 2};\n\n assert(func0(A1, B1, 4, 2) == false);\n\n\n\n int A2[] = {1, 2, 1};\n\n int B2[] = {1, 2, 1};\n\n assert(func0(A2, B2, 3, 3) == true);\n\n\n\n int A3[] = {1, 0, 2, 2};\n\n int B3[] = {2, 2, 0};\n\n assert(func0(A3, B3, 4, 3) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %edx,-0x24(%rbp)\nmov %ecx,-0x28(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11e9 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x20(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 11d6 \naddl $0x1,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x28(%rbp),%eax\njne 11e9 \nmov $0x1,%eax\njmp 11fe \nmov -0x8(%rbp),%eax\nsub -0x4(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x24(%rbp),%eax\njge 11f9 \nmov -0x4(%rbp),%eax\ncmp -0x28(%rbp),%eax\njl 118f \nmov $0x0,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_28], ecx\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11E9\nloc_118F:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11D6\nadd [rbp+var_8], 1\nadd [rbp+var_4], 1\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_28]\njnz short loc_11E9\nmov eax, 1\njmp short loc_11FE\nloc_11D6:\nmov eax, [rbp+var_8]\nsub eax, [rbp+var_4]\nadd eax, 1\nmov [rbp+var_8], eax\nmov [rbp+var_4], 0\nloc_11E9:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_24]\njge short loc_11F9\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_28]\njl short loc_118F\nloc_11F9:\nmov eax, 0\nloc_11FE:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3, int a4)\n{\n int v5; // [rsp+20h] [rbp-8h]\n int v6; // [rsp+24h] [rbp-4h]\n\n v5 = 0;\n v6 = 0;\n while ( v5 < a3 && v6 < a4 )\n {\n if ( *(_DWORD *)(4LL * v5 + a1) == *(_DWORD *)(4LL * v6 + a2) )\n {\n ++v5;\n if ( ++v6 == a4 )\n return 1LL;\n }\n else\n {\n v5 = v5 - v6 + 1;\n v6 = 0;\n }\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_28], ecx\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11E9\nloc_118F:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11D6\nadd [rbp+var_8], 1\nadd [rbp+var_4], 1\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_28]\njnz short loc_11E9\nmov eax, 1\njmp short loc_11FE\nloc_11D6:\nmov eax, [rbp+var_8]\nsub eax, [rbp+var_4]\nadd eax, 1\nmov [rbp+var_8], eax\nmov [rbp+var_4], 0\nloc_11E9:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_24]\njge short loc_11F9\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_28]\njl short loc_118F\nloc_11F9:\nmov eax, 0\nloc_11FE:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, int a3, int a4)\n{\n int v5; // [rsp+20h] [rbp-8h]\n int v6; // [rsp+24h] [rbp-4h]\n\n v5 = 0;\n v6 = 0;\n while ( v5 < a3 && v6 < a4 )\n {\n if ( *(_DWORD *)(4LL * v5 + a1) == *(_DWORD *)(4LL * v6 + a2) )\n {\n ++v5;\n if ( ++v6 == a4 )\n return 1LL;\n }\n else\n {\n v5 = v5 - v6 + 1;\n v6 = 0;\n }\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, int a3, int a4) {\n int v5;\n int v6;\n v5 = 0;\n v6 = 0;\n while (v5 < a3 && v6 < a4) {\n if (*(uint32_t *)(4LL * v5 + a1) == *(uint32_t *)(4LL * v6 + a2)) {\n ++v5;\n if (++v6 == a4) return 1LL;\n } else {\n v5 = v5 - v6 + 1;\n v6 = 0;\n }\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3, int a4) {\n int v5;\n int v6;\n v5 = 0;\n v6 = 0;\n while (v5 < a3 && v6 < a4) {\n if (*(uint32_t *)(4LL * v5 + a1) == *(uint32_t *)(4LL * v6 + a2)) {\n ++v5;\n if (++v6 == a4) return 1LL;\n } else {\n v5 = v5 - v6 + 1;\n v6 = 0;\n }\n }\n return 0LL;\n}" + }, + { + "index": 576, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int A[], int B[], int n, int m) {\n int i = 0, j = 0;\n while (i < n && j < m) {\n if (A[i] == B[j]) {\n i++;\n j++;\n if (j == m) {\n return true;\n }\n } else {\n i = i - j + 1;\n j = 0;\n }\n }\n return false;\n}", + "test": "int main() {\n\n int A1[] = {1, 4, 3, 5};\n\n int B1[] = {1, 2};\n\n assert(func0(A1, B1, 4, 2) == false);\n\n\n\n int A2[] = {1, 2, 1};\n\n int B2[] = {1, 2, 1};\n\n assert(func0(A2, B2, 3, 3) == true);\n\n\n\n int A3[] = {1, 0, 2, 2};\n\n int B3[] = {2, 2, 0};\n\n assert(func0(A3, B3, 4, 3) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edx,%edx\nsetg %al\ntest %ecx,%ecx\nsetg %r11b\nand %al,%r11b\nje 11cc \nmov $0x0,%r9d\nmov $0x0,%r8d\njmp 11aa \nsub %r9d,%r8d\nadd $0x1,%r8d\nmov $0x0,%r9d\ncmp %edx,%r8d\nsetl %al\ncmp %ecx,%r9d\nsetl %r10b\nand %r10b,%al\nje 11cb \nmovslq %r8d,%rax\nmovslq %r9d,%r10\nmov (%rsi,%r10,4),%r10d\ncmp %r10d,(%rdi,%rax,4)\njne 118b \nadd $0x1,%r8d\nadd $0x1,%r9d\ncmp %r9d,%ecx\njne 1198 \nmov %r11d,%eax\nretq\nretq\nmov %r11d,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov r9, rdi\nmov r10, rsi\nmov r8d, edx\nmov edi, ecx\ntest edx, edx\nsetnle al\ntest ecx, ecx\nsetnle dl\nand al, dl\nmov r11d, eax\njz short locret_11CF\nmov ecx, 0\nmov edx, 0\njmp short loc_11B0\nloc_1195:\nsub edx, ecx\nadd edx, 1\nmov ecx, 0\nloc_119F:\ncmp edx, r8d\nsetl al\ncmp ecx, edi\nsetl sil\nand al, sil\njz short locret_11CE\nloc_11B0:\nmovsxd rax, edx\nmovsxd rsi, ecx\nmov esi, [r10+rsi*4]\ncmp [r9+rax*4], esi\njnz short loc_1195\nadd edx, 1\nadd ecx, 1\ncmp edi, ecx\njnz short loc_119F\nmov eax, r11d\nretn\nlocret_11CE:\nretn\nlocret_11CF:\nretn", + "ida_pseudo": "bool __fastcall func0(__int64 a1, __int64 a2, int a3, int a4)\n{\n bool result; // al\n bool v8; // r11\n int v9; // ecx\n int v10; // edx\n\n result = a4 > 0 && a3 > 0;\n v8 = result;\n if ( result )\n {\n v9 = 0;\n v10 = 0;\n do\n {\n if ( *(_DWORD *)(a1 + 4LL * v10) == *(_DWORD *)(a2 + 4LL * v9) )\n {\n ++v10;\n if ( a4 == ++v9 )\n return v8;\n }\n else\n {\n v10 = v10 - v9 + 1;\n v9 = 0;\n }\n result = v9 < a4 && v10 < a3;\n }\n while ( result );\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov r9, rdi\nmov r10, rsi\nmov r8d, edx\nmov edi, ecx\ntest edx, edx\nsetnle al\ntest ecx, ecx\nsetnle dl\nand al, dl\nmov r11d, eax\njz short locret_11CF\nmov ecx, 0\nmov edx, 0\njmp short loc_11B0\nloc_1195:\nsub edx, ecx\nadd edx, 1\nmov ecx, 0\nloc_119F:\ncmp edx, r8d\nsetl al\ncmp ecx, edi\nsetl sil\nand al, sil\njz short locret_11CE\nloc_11B0:\nmovsxd rax, edx\nmovsxd rsi, ecx\nmov esi, [r10+rsi*4]\ncmp [r9+rax*4], esi\njnz short loc_1195\nadd edx, 1\nadd ecx, 1\ncmp edi, ecx\njnz short loc_119F\nmov eax, r11d\nretn\nlocret_11CE:\nretn\nlocret_11CF:\nretn", + "ida_strip_pseudo": "bool __fastcall sub_1169(__int64 a1, __int64 a2, int a3, int a4)\n{\n bool result; // al\n bool v8; // r11\n int v9; // ecx\n int v10; // edx\n\n result = a4 > 0 && a3 > 0;\n v8 = result;\n if ( result )\n {\n v9 = 0;\n v10 = 0;\n do\n {\n if ( *(_DWORD *)(a1 + 4LL * v10) == *(_DWORD *)(a2 + 4LL * v9) )\n {\n ++v10;\n if ( a4 == ++v9 )\n return v8;\n }\n else\n {\n v10 = v10 - v9 + 1;\n v9 = 0;\n }\n result = v9 < a4 && v10 < a3;\n }\n while ( result );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_1169(long long a1, long long a2, int a3, int a4) {\n bool result;\n bool v8;\n int v9;\n int v10;\n result = a4 > 0 && a3 > 0;\n v8 = result;\n if (result) {\n v9 = 0;\n v10 = 0;\n do {\n if (*(uint32_t *)(a1 + 4LL * v10) == *(uint32_t *)(a2 + 4LL * v9)) {\n ++v10;\n if (a4 == ++v9) return v8;\n } else {\n v10 = v10 - v9 + 1;\n v9 = 0;\n }\n result = v9 < a4 && v10 < a3;\n } while (result);\n }\n return result;\n}", + "ida_pseudo_norm": "bool func0(long long a1, long long a2, int a3, int a4) {\n bool result;\n bool v8;\n int v9;\n int v10;\n result = a4 > 0 && a3 > 0;\n v8 = result;\n if (result) {\n v9 = 0;\n v10 = 0;\n do {\n if (*(uint32_t *)(a1 + 4LL * v10) == *(uint32_t *)(a2 + 4LL * v9)) {\n ++v10;\n if (a4 == ++v9) return v8;\n } else {\n v10 = v10 - v9 + 1;\n v9 = 0;\n }\n result = v9 < a4 && v10 < a3;\n } while (result);\n }\n return result;\n}" + }, + { + "index": 576, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int A[], int B[], int n, int m) {\n int i = 0, j = 0;\n while (i < n && j < m) {\n if (A[i] == B[j]) {\n i++;\n j++;\n if (j == m) {\n return true;\n }\n } else {\n i = i - j + 1;\n j = 0;\n }\n }\n return false;\n}", + "test": "int main() {\n\n int A1[] = {1, 4, 3, 5};\n\n int B1[] = {1, 2};\n\n assert(func0(A1, B1, 4, 2) == false);\n\n\n\n int A2[] = {1, 2, 1};\n\n int B2[] = {1, 2, 1};\n\n assert(func0(A2, B2, 3, 3) == true);\n\n\n\n int A3[] = {1, 0, 2, 2};\n\n int B3[] = {2, 2, 0};\n\n assert(func0(A3, B3, 4, 3) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %ecx,%ecx\nsetg %r11b\ntest %edx,%edx\nsetg %al\nand %al,%r11b\nje 13ac \nxor %r9d,%r9d\nxor %r8d,%r8d\njmp 1378 \nnopl 0x0(%rax)\nsub %r9d,%r8d\nxor %r9d,%r9d\nmov %r11d,%r10d\nadd $0x1,%r8d\ncmp %edx,%r8d\nsetl %al\nand %r10b,%al\nje 13a4 \nmovslq %r9d,%r10\nmovslq %r8d,%rax\nmov (%rsi,%r10,4),%r10d\ncmp %r10d,(%rdi,%rax,4)\njne 1360 \nadd $0x1,%r9d\nadd $0x1,%r8d\ncmp %r9d,%ecx\nje 13a8 \nsetg %r10b\ncmp %edx,%r8d\nsetl %al\nand %r10b,%al\njne 1378 \nretq\nnopl (%rax)\nmov %r11d,%eax\nretq\nxor %eax,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest edx, edx\nmov r8, rdi\nmov r9, rsi\nmov edi, edx\nsetnle r10b\ntest ecx, ecx\nmov r11d, ecx\nsetnle al\nand r10b, al\njz short loc_1334\nxor ecx, ecx\nxor edx, edx\njmp short loc_12FC\nloc_12E8:\nsub edx, ecx\nxor ecx, ecx\nmov esi, r10d\nadd edx, 1\ncmp edx, edi\nsetl al\nand al, sil\njz short locret_1325\nloc_12FC:\nmovsxd rsi, ecx\nmovsxd rax, edx\nmov esi, [r9+rsi*4]\ncmp [r8+rax*4], esi\njnz short loc_12E8\nadd ecx, 1\nadd edx, 1\ncmp r11d, ecx\njz short loc_1330\nsetnle sil\ncmp edx, edi\nsetl al\nand al, sil\njnz short loc_12FC\nlocret_1325:\nretn\nloc_1330:\nmov eax, r10d\nretn\nloc_1334:\nxor eax, eax\nretn", + "ida_pseudo": "bool __fastcall func0(__int64 a1, __int64 a2, int a3, int a4)\n{\n bool v7; // r10\n int v8; // ecx\n int v9; // edx\n int v10; // edx\n bool result; // al\n\n v7 = a4 > 0 && a3 > 0;\n if ( !v7 )\n return 0;\n v8 = 0;\n v9 = 0;\n while ( 1 )\n {\n while ( *(_DWORD *)(a1 + 4LL * v9) != *(_DWORD *)(a2 + 4LL * v8) )\n {\n v10 = v9 - v8;\n v8 = 0;\n v9 = v10 + 1;\n result = v7 && v9 < a3;\n if ( !result )\n return result;\n }\n ++v8;\n ++v9;\n if ( a4 == v8 )\n break;\n result = a4 > v8 && v9 < a3;\n if ( !result )\n return result;\n }\n return v7;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\ntest edx, edx\nmov r8, rdi\nmov r9, rsi\nmov edi, edx\nsetnle r10b\ntest ecx, ecx\nmov r11d, ecx\nsetnle al\nand r10b, al\njz short loc_1334\nxor ecx, ecx\nxor edx, edx\njmp short loc_12FC\nloc_12E8:\nsub edx, ecx\nxor ecx, ecx\nmov esi, r10d\nadd edx, 1\ncmp edx, edi\nsetl al\nand al, sil\njz short locret_1325\nloc_12FC:\nmovsxd rsi, ecx\nmovsxd rax, edx\nmov esi, [r9+rsi*4]\ncmp [r8+rax*4], esi\njnz short loc_12E8\nadd ecx, 1\nadd edx, 1\ncmp r11d, ecx\njz short loc_1330\nsetnle sil\ncmp edx, edi\nsetl al\nand al, sil\njnz short loc_12FC\nlocret_1325:\nretn\nloc_1330:\nmov eax, r10d\nretn\nloc_1334:\nxor eax, eax\nretn", + "ida_strip_pseudo": "bool __fastcall sub_12C0(__int64 a1, __int64 a2, int a3, int a4)\n{\n bool v7; // r10\n int v8; // ecx\n int v9; // edx\n int v10; // edx\n bool result; // al\n\n v7 = a4 > 0 && a3 > 0;\n if ( !v7 )\n return 0;\n v8 = 0;\n v9 = 0;\n while ( 1 )\n {\n while ( *(_DWORD *)(a1 + 4LL * v9) != *(_DWORD *)(a2 + 4LL * v8) )\n {\n v10 = v9 - v8;\n v8 = 0;\n v9 = v10 + 1;\n result = v7 && v9 < a3;\n if ( !result )\n return result;\n }\n ++v8;\n ++v9;\n if ( a4 == v8 )\n break;\n result = a4 > v8 && v9 < a3;\n if ( !result )\n return result;\n }\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_12C0(long long a1, long long a2, int a3, int a4) {\n bool v7;\n int v8;\n int v9;\n int v10;\n bool result;\n v7 = a4 > 0 && a3 > 0;\n if (!v7) return 0;\n v8 = 0;\n v9 = 0;\n while (1) {\n while (*(uint32_t *)(a1 + 4LL * v9) != *(uint32_t *)(a2 + 4LL * v8)) {\n v10 = v9 - v8;\n v8 = 0;\n v9 = v10 + 1;\n result = v7 && v9 < a3;\n if (!result) return result;\n }\n ++v8;\n ++v9;\n if (a4 == v8) break;\n result = a4 > v8 && v9 < a3;\n if (!result) return result;\n }\n return v7;\n}", + "ida_pseudo_norm": "bool func0(long long a1, long long a2, int a3, int a4) {\n bool v7;\n int v8;\n int v9;\n int v10;\n bool result;\n v7 = a4 > 0 && a3 > 0;\n if (!v7) return 0;\n v8 = 0;\n v9 = 0;\n while (1) {\n while (*(uint32_t *)(a1 + 4LL * v9) != *(uint32_t *)(a2 + 4LL * v8)) {\n v10 = v9 - v8;\n v8 = 0;\n v9 = v10 + 1;\n result = v7 && v9 < a3;\n if (!result) return result;\n }\n ++v8;\n ++v9;\n if (a4 == v8) break;\n result = a4 > v8 && v9 < a3;\n if (!result) return result;\n }\n return v7;\n}" + }, + { + "index": 577, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int n) {\n if (n == 0)\n return 1;\n else if (n <= 2)\n return n;\n else if (n == 3)\n return 6;\n else if (n == 4)\n return 4;\n else\n return 0;\n}", + "test": "int main() {\n\n assert(func0(4) == 4);\n\n assert(func0(21) == 0);\n\n assert(func0(30) == 0);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\ncmpl $0x0,-0x4(%rbp)\njne 1161 \nmov $0x1,%eax\njmp 118b \ncmpl $0x2,-0x4(%rbp)\njg 116c \nmov -0x4(%rbp),%eax\njmp 118b \ncmpl $0x3,-0x4(%rbp)\njne 1179 \nmov $0x6,%eax\njmp 118b \ncmpl $0x4,-0x4(%rbp)\njne 1186 \nmov $0x4,%eax\njmp 118b \nmov $0x0,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\ncmp [rbp+var_4], 0\njnz short loc_1161\nmov eax, 1\njmp short loc_118B\nloc_1161:\ncmp [rbp+var_4], 2\njg short loc_116C\nmov eax, [rbp+var_4]\njmp short loc_118B\nloc_116C:\ncmp [rbp+var_4], 3\njnz short loc_1179\nmov eax, 6\njmp short loc_118B\nloc_1179:\ncmp [rbp+var_4], 4\njnz short loc_1186\nmov eax, 4\njmp short loc_118B\nloc_1186:\nmov eax, 0\nloc_118B:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n if ( !a1 )\n return 1LL;\n if ( a1 <= 2 )\n return (unsigned int)a1;\n if ( a1 == 3 )\n return 6LL;\n if ( a1 == 4 )\n return 4LL;\n return 0LL;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\ncmp [rbp+var_4], 0\njnz short loc_1161\nmov eax, 1\njmp short loc_118B\nloc_1161:\ncmp [rbp+var_4], 2\njg short loc_116C\nmov eax, [rbp+var_4]\njmp short loc_118B\nloc_116C:\ncmp [rbp+var_4], 3\njnz short loc_1179\nmov eax, 6\njmp short loc_118B\nloc_1179:\ncmp [rbp+var_4], 4\njnz short loc_1186\nmov eax, 4\njmp short loc_118B\nloc_1186:\nmov eax, 0\nloc_118B:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n if ( !a1 )\n return 1LL;\n if ( a1 <= 2 )\n return (unsigned int)a1;\n if ( a1 == 3 )\n return 6LL;\n if ( a1 == 4 )\n return 4LL;\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n if (!a1) return 1LL;\n if (a1 <= 2) return (unsigned int)a1;\n if (a1 == 3) return 6LL;\n if (a1 == 4) return 4LL;\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n if (!a1) return 1LL;\n if (a1 <= 2) return (unsigned int)a1;\n if (a1 == 3) return 6LL;\n if (a1 == 4) return 4LL;\n return 0LL;\n}" + }, + { + "index": 578, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int list1[], int list2[], int list3[], int result[], int size) {\n int idx = 0;\n for (int i = 0; i < size; i++) {\n result[idx++] = list1[i];\n result[idx++] = list2[i];\n result[idx++] = list3[i];\n }\n}", + "test": "int main() {\n\n int size1 = 7;\n\n int list1[] = {1, 2, 3, 4, 5, 6, 7};\n\n int list2[] = {10, 20, 30, 40, 50, 60, 70};\n\n int list3[] = {100, 200, 300, 400, 500, 600, 700};\n\n int result1[21];\n\n func0(list1, list2, list3, result1, size1);\n\n int expected1[] = {1, 10, 100, 2, 20, 200, 3, 30, 300, 4, 40, 400, 5, 50, 500, 6, 60, 600, 7, 70, 700};\n\n for (int i = 0; i < size1 * 3; i++) assert(result1[i] == expected1[i]);\n\n\n\n int size2 = 2;\n\n int list4[] = {10, 20};\n\n int list5[] = {15, 2};\n\n int list6[] = {5, 10};\n\n int result2[6];\n\n func0(list4, list5, list6, result2, size2);\n\n int expected2[] = {10, 15, 5, 20, 2, 10};\n\n for (int i = 0; i < size2 * 3; i++) assert(result2[i] == expected2[i]);\n\n\n\n int size3 = 2;\n\n int list7[] = {11, 44};\n\n int list8[] = {10, 15};\n\n int list9[] = {20, 5};\n\n int result3[6];\n\n func0(list7, list8, list9, result3, size3);\n\n int expected3[] = {11, 10, 20, 44, 15, 5};\n\n for (int i = 0; i < size3 * 3; i++) assert(result3[i] == expected3[i]);\n\n\n\n printf(\"All tests passed successfully!\\n\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %rcx,-0x30(%rbp)\nmov %r8d,-0x34(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmpq 1255 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x8(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x8(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x30(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x20(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x8(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x8(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x30(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x8(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x8(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x30(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x34(%rbp),%eax\njl 11b8 \npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_28], rdx\nmov [rbp+var_30], rcx\nmov [rbp+var_34], r8d\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp loc_1255\nloc_11B8:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_8]\nlea edx, [rax+1]\nmov [rbp+var_8], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_30]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_8]\nlea edx, [rax+1]\nmov [rbp+var_8], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_30]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_8]\nlea edx, [rax+1]\nmov [rbp+var_8], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_30]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nadd [rbp+var_4], 1\nloc_1255:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_34]\njl loc_11B8\nnop\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, __int64 a3, __int64 a4, int a5)\n{\n int v5; // eax\n __int64 result; // rax\n int v7; // [rsp+2Ch] [rbp-8h]\n unsigned int i; // [rsp+30h] [rbp-4h]\n\n v7 = 0;\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a5 )\n break;\n *(_DWORD *)(a4 + 4LL * v7) = *(_DWORD *)(4LL * (int)i + a1);\n *(_DWORD *)(a4 + 4LL * (v7 + 1)) = *(_DWORD *)(4LL * (int)i + a2);\n v5 = v7 + 2;\n v7 += 3;\n *(_DWORD *)(a4 + 4LL * v5) = *(_DWORD *)(4LL * (int)i + a3);\n }\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_28], rdx\nmov [rbp+var_30], rcx\nmov [rbp+var_34], r8d\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp loc_1255\nloc_11B8:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_8]\nlea edx, [rax+1]\nmov [rbp+var_8], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_30]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_8]\nlea edx, [rax+1]\nmov [rbp+var_8], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_30]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_8]\nlea edx, [rax+1]\nmov [rbp+var_8], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_30]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nadd [rbp+var_4], 1\nloc_1255:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_34]\njl loc_11B8\nnop\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, __int64 a2, __int64 a3, __int64 a4, int a5)\n{\n int v5; // eax\n __int64 result; // rax\n int v7; // [rsp+2Ch] [rbp-8h]\n unsigned int i; // [rsp+30h] [rbp-4h]\n\n v7 = 0;\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a5 )\n break;\n *(_DWORD *)(a4 + 4LL * v7) = *(_DWORD *)(4LL * (int)i + a1);\n *(_DWORD *)(a4 + 4LL * (v7 + 1)) = *(_DWORD *)(4LL * (int)i + a2);\n v5 = v7 + 2;\n v7 += 3;\n *(_DWORD *)(a4 + 4LL * v5) = *(_DWORD *)(4LL * (int)i + a3);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, long long a2, long long a3, long long a4,\n int a5) {\n int v5;\n long long result;\n int v7;\n unsigned int i;\n v7 = 0;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a5) break;\n *(uint32_t *)(a4 + 4LL * v7) = *(uint32_t *)(4LL * (int)i + a1);\n *(uint32_t *)(a4 + 4LL * (v7 + 1)) = *(uint32_t *)(4LL * (int)i + a2);\n v5 = v7 + 2;\n v7 += 3;\n *(uint32_t *)(a4 + 4LL * v5) = *(uint32_t *)(4LL * (int)i + a3);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, long long a3, long long a4,\n int a5) {\n int v5;\n long long result;\n int v7;\n unsigned int i;\n v7 = 0;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a5) break;\n *(uint32_t *)(a4 + 4LL * v7) = *(uint32_t *)(4LL * (int)i + a1);\n *(uint32_t *)(a4 + 4LL * (v7 + 1)) = *(uint32_t *)(4LL * (int)i + a2);\n v5 = v7 + 2;\n v7 += 3;\n *(uint32_t *)(a4 + 4LL * v5) = *(uint32_t *)(4LL * (int)i + a3);\n }\n return result;\n}" + }, + { + "index": 578, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int list1[], int list2[], int list3[], int result[], int size) {\n int idx = 0;\n for (int i = 0; i < size; i++) {\n result[idx++] = list1[i];\n result[idx++] = list2[i];\n result[idx++] = list3[i];\n }\n}", + "test": "int main() {\n\n int size1 = 7;\n\n int list1[] = {1, 2, 3, 4, 5, 6, 7};\n\n int list2[] = {10, 20, 30, 40, 50, 60, 70};\n\n int list3[] = {100, 200, 300, 400, 500, 600, 700};\n\n int result1[21];\n\n func0(list1, list2, list3, result1, size1);\n\n int expected1[] = {1, 10, 100, 2, 20, 200, 3, 30, 300, 4, 40, 400, 5, 50, 500, 6, 60, 600, 7, 70, 700};\n\n for (int i = 0; i < size1 * 3; i++) assert(result1[i] == expected1[i]);\n\n\n\n int size2 = 2;\n\n int list4[] = {10, 20};\n\n int list5[] = {15, 2};\n\n int list6[] = {5, 10};\n\n int result2[6];\n\n func0(list4, list5, list6, result2, size2);\n\n int expected2[] = {10, 15, 5, 20, 2, 10};\n\n for (int i = 0; i < size2 * 3; i++) assert(result2[i] == expected2[i]);\n\n\n\n int size3 = 2;\n\n int list7[] = {11, 44};\n\n int list8[] = {10, 15};\n\n int list9[] = {20, 5};\n\n int result3[6];\n\n func0(list7, list8, list9, result3, size3);\n\n int expected3[] = {11, 10, 20, 44, 15, 5};\n\n for (int i = 0; i < size3 * 3; i++) assert(result3[i] == expected3[i]);\n\n\n\n printf(\"All tests passed successfully!\\n\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %r8d,%r8d\njle 11c2 \nlea -0x1(%r8),%r9d\nmov $0x0,%eax\nmov (%rdi,%rax,4),%r8d\nmov %r8d,(%rcx)\nmov (%rsi,%rax,4),%r8d\nmov %r8d,0x4(%rcx)\nmov (%rdx,%rax,4),%r8d\nmov %r8d,0x8(%rcx)\nmov %rax,%r8\nadd $0x1,%rax\nadd $0xc,%rcx\ncmp %r9,%r8\njne 119b \nretq\n", + "ida_asm": "func0:\nendbr64\nmov r9, rsi\nmov r10, rdx\ntest r8d, r8d\njle short locret_11C8\nmovsxd r8, r8d\nlea rsi, ds:0[r8*4]\nmov eax, 0\nloc_11A8:\nmov edx, [rdi+rax]\nmov [rcx], edx\nmov edx, [r9+rax]\nmov [rcx+4], edx\nmov edx, [r10+rax]\nmov [rcx+8], edx\nadd rcx, 0Ch\nadd rax, 4\ncmp rax, rsi\njnz short loc_11A8\nlocret_11C8:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, __int64 a2, __int64 a3, _DWORD *a4, int a5)\n{\n __int64 v5; // rax\n\n if ( a5 > 0 )\n {\n v5 = 0LL;\n do\n {\n *a4 = *(_DWORD *)(a1 + v5);\n a4[1] = *(_DWORD *)(a2 + v5);\n a4[2] = *(_DWORD *)(a3 + v5);\n a4 += 3;\n v5 += 4LL;\n }\n while ( v5 != 4LL * a5 );\n }\n}", + "ida_strip_asm": "sub_1189:\nendbr64\nmov r9, rsi\nmov r10, rdx\ntest r8d, r8d\njle short locret_11C8\nmovsxd r8, r8d\nlea rsi, ds:0[r8*4]\nmov eax, 0\nloc_11A8:\nmov edx, [rdi+rax]\nmov [rcx], edx\nmov edx, [r9+rax]\nmov [rcx+4], edx\nmov edx, [r10+rax]\nmov [rcx+8], edx\nadd rcx, 0Ch\nadd rax, 4\ncmp rax, rsi\njnz short loc_11A8\nlocret_11C8:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1189(__int64 a1, __int64 a2, __int64 a3, _DWORD *a4, int a5)\n{\n __int64 v5; // rax\n\n if ( a5 > 0 )\n {\n v5 = 0LL;\n do\n {\n *a4 = *(_DWORD *)(a1 + v5);\n a4[1] = *(_DWORD *)(a2 + v5);\n a4[2] = *(_DWORD *)(a3 + v5);\n a4 += 3;\n v5 += 4LL;\n }\n while ( v5 != 4LL * a5 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1189(long long a1, long long a2, long long a3, uint32_t *a4, int a5) {\n long long v5;\n if (a5 > 0) {\n v5 = 0LL;\n do {\n *a4 = *(uint32_t *)(a1 + v5);\n a4[1] = *(uint32_t *)(a2 + v5);\n a4[2] = *(uint32_t *)(a3 + v5);\n a4 += 3;\n v5 += 4LL;\n } while (v5 != 4LL * a5);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, long long a2, long long a3, uint32_t *a4, int a5) {\n long long v5;\n if (a5 > 0) {\n v5 = 0LL;\n do {\n *a4 = *(uint32_t *)(a1 + v5);\n a4[1] = *(uint32_t *)(a2 + v5);\n a4[2] = *(uint32_t *)(a3 + v5);\n a4 += 3;\n v5 += 4LL;\n } while (v5 != 4LL * a5);\n }\n}" + }, + { + "index": 578, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int list1[], int list2[], int list3[], int result[], int size) {\n int idx = 0;\n for (int i = 0; i < size; i++) {\n result[idx++] = list1[i];\n result[idx++] = list2[i];\n result[idx++] = list3[i];\n }\n}", + "test": "int main() {\n\n int size1 = 7;\n\n int list1[] = {1, 2, 3, 4, 5, 6, 7};\n\n int list2[] = {10, 20, 30, 40, 50, 60, 70};\n\n int list3[] = {100, 200, 300, 400, 500, 600, 700};\n\n int result1[21];\n\n func0(list1, list2, list3, result1, size1);\n\n int expected1[] = {1, 10, 100, 2, 20, 200, 3, 30, 300, 4, 40, 400, 5, 50, 500, 6, 60, 600, 7, 70, 700};\n\n for (int i = 0; i < size1 * 3; i++) assert(result1[i] == expected1[i]);\n\n\n\n int size2 = 2;\n\n int list4[] = {10, 20};\n\n int list5[] = {15, 2};\n\n int list6[] = {5, 10};\n\n int result2[6];\n\n func0(list4, list5, list6, result2, size2);\n\n int expected2[] = {10, 15, 5, 20, 2, 10};\n\n for (int i = 0; i < size2 * 3; i++) assert(result2[i] == expected2[i]);\n\n\n\n int size3 = 2;\n\n int list7[] = {11, 44};\n\n int list8[] = {10, 15};\n\n int list9[] = {20, 5};\n\n int result3[6];\n\n func0(list7, list8, list9, result3, size3);\n\n int expected3[] = {11, 10, 20, 44, 15, 5};\n\n for (int i = 0; i < size3 * 3; i++) assert(result3[i] == expected3[i]);\n\n\n\n printf(\"All tests passed successfully!\\n\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %r8d,%r8d\njle 1588 \nlea -0x1(%r8),%r9d\nxor %eax,%eax\nmov (%rdi,%rax,4),%r8d\nadd $0xc,%rcx\nmov %r8d,-0xc(%rcx)\nmov (%rsi,%rax,4),%r8d\nmov %r8d,-0x8(%rcx)\nmov (%rdx,%rax,4),%r8d\nmov %r8d,-0x4(%rcx)\nmov %rax,%r8\nadd $0x1,%rax\ncmp %r8,%r9\njne 1560 \nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\nmov r9, rsi\nmov r10, rdx\ntest r8d, r8d\njle short locret_14B1\nmovsxd r8, r8d\nxor eax, eax\nlea rsi, ds:0[r8*4]\nnop dword ptr [rax+00h]\nloc_1490:\nmov edx, [rdi+rax]\nadd rcx, 0Ch\nmov [rcx-0Ch], edx\nmov edx, [r9+rax]\nmov [rcx-8], edx\nmov edx, [r10+rax]\nadd rax, 4\nmov [rcx-4], edx\ncmp rsi, rax\njnz short loc_1490\nlocret_14B1:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, __int64 a2, __int64 a3, __int64 a4, int a5)\n{\n __int64 v6; // rax\n int v7; // edx\n\n if ( a5 > 0 )\n {\n v6 = 0LL;\n do\n {\n a4 += 12LL;\n *(_DWORD *)(a4 - 12) = *(_DWORD *)(a1 + v6);\n *(_DWORD *)(a4 - 8) = *(_DWORD *)(a2 + v6);\n v7 = *(_DWORD *)(a3 + v6);\n v6 += 4LL;\n *(_DWORD *)(a4 - 4) = v7;\n }\n while ( 4LL * a5 != v6 );\n }\n}", + "ida_strip_asm": "sub_1470:\nendbr64\nmov r9, rsi\nmov r10, rdx\ntest r8d, r8d\njle short locret_14B1\nmovsxd r8, r8d\nxor eax, eax\nlea rsi, ds:0[r8*4]\nnop dword ptr [rax+00h]\nloc_1490:\nmov edx, [rdi+rax]\nadd rcx, 0Ch\nmov [rcx-0Ch], edx\nmov edx, [r9+rax]\nmov [rcx-8], edx\nmov edx, [r10+rax]\nadd rax, 4\nmov [rcx-4], edx\ncmp rsi, rax\njnz short loc_1490\nlocret_14B1:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1470(__int64 a1, __int64 a2, __int64 a3, __int64 a4, int a5)\n{\n __int64 v6; // rax\n int v7; // edx\n\n if ( a5 > 0 )\n {\n v6 = 0LL;\n do\n {\n a4 += 12LL;\n *(_DWORD *)(a4 - 12) = *(_DWORD *)(a1 + v6);\n *(_DWORD *)(a4 - 8) = *(_DWORD *)(a2 + v6);\n v7 = *(_DWORD *)(a3 + v6);\n v6 += 4LL;\n *(_DWORD *)(a4 - 4) = v7;\n }\n while ( 4LL * a5 != v6 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1470(long long a1, long long a2, long long a3, long long a4, int a5) {\n long long v6;\n int v7;\n if (a5 > 0) {\n v6 = 0LL;\n do {\n a4 += 12LL;\n *(uint32_t *)(a4 - 12) = *(uint32_t *)(a1 + v6);\n *(uint32_t *)(a4 - 8) = *(uint32_t *)(a2 + v6);\n v7 = *(uint32_t *)(a3 + v6);\n v6 += 4LL;\n *(uint32_t *)(a4 - 4) = v7;\n } while (4LL * a5 != v6);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, long long a2, long long a3, long long a4, int a5) {\n long long v6;\n int v7;\n if (a5 > 0) {\n v6 = 0LL;\n do {\n a4 += 12LL;\n *(uint32_t *)(a4 - 12) = *(uint32_t *)(a1 + v6);\n *(uint32_t *)(a4 - 8) = *(uint32_t *)(a2 + v6);\n v7 = *(uint32_t *)(a3 + v6);\n v6 += 4LL;\n *(uint32_t *)(a4 - 4) = v7;\n } while (4LL * a5 != v6);\n }\n}" + }, + { + "index": 578, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int list1[], int list2[], int list3[], int result[], int size) {\n int idx = 0;\n for (int i = 0; i < size; i++) {\n result[idx++] = list1[i];\n result[idx++] = list2[i];\n result[idx++] = list3[i];\n }\n}", + "test": "int main() {\n\n int size1 = 7;\n\n int list1[] = {1, 2, 3, 4, 5, 6, 7};\n\n int list2[] = {10, 20, 30, 40, 50, 60, 70};\n\n int list3[] = {100, 200, 300, 400, 500, 600, 700};\n\n int result1[21];\n\n func0(list1, list2, list3, result1, size1);\n\n int expected1[] = {1, 10, 100, 2, 20, 200, 3, 30, 300, 4, 40, 400, 5, 50, 500, 6, 60, 600, 7, 70, 700};\n\n for (int i = 0; i < size1 * 3; i++) assert(result1[i] == expected1[i]);\n\n\n\n int size2 = 2;\n\n int list4[] = {10, 20};\n\n int list5[] = {15, 2};\n\n int list6[] = {5, 10};\n\n int result2[6];\n\n func0(list4, list5, list6, result2, size2);\n\n int expected2[] = {10, 15, 5, 20, 2, 10};\n\n for (int i = 0; i < size2 * 3; i++) assert(result2[i] == expected2[i]);\n\n\n\n int size3 = 2;\n\n int list7[] = {11, 44};\n\n int list8[] = {10, 15};\n\n int list9[] = {20, 5};\n\n int result3[6];\n\n func0(list7, list8, list9, result3, size3);\n\n int expected3[] = {11, 10, 20, 44, 15, 5};\n\n for (int i = 0; i < size3 * 3; i++) assert(result3[i] == expected3[i]);\n\n\n\n printf(\"All tests passed successfully!\\n\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ntest %r8d,%r8d\njle 14f8 \nlea -0x1(%r8),%r9d\nxor %eax,%eax\nmov (%rdi,%rax,4),%r8d\nadd $0xc,%rcx\nmov %r8d,-0xc(%rcx)\nmov (%rsi,%rax,4),%r8d\nmov %r8d,-0x8(%rcx)\nmov (%rdx,%rax,4),%r8d\nmov %r8d,-0x4(%rcx)\nmov %rax,%r8\nadd $0x1,%rax\ncmp %r9,%r8\njne 14d0 \nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\ntest r8d, r8d\njle locret_1640\nmov r9, rdx\nlea edx, [r8-1]\npush r14\nmov rax, rcx\npush rbp\nmovsxd rcx, r8d\npush rbx\ncmp edx, 2\njbe loc_1608\nlea rdx, ds:0[rcx*4]\nlea r10, [rcx+rcx*2]\nlea rbx, [rax+r10*4]\nlea r10, [rdi+rdx]\ncmp rax, r10\nsetnb r11b\ncmp rdi, rbx\nsetnb r10b\nor r11d, r10d\nlea r10, [rsi+rdx]\ncmp rax, r10\nsetnb r10b\ncmp rsi, rbx\nsetnb bpl\nor r10d, ebp\ntest r11b, r10b\njz loc_1608\nadd rdx, r9\ncmp rax, rdx\nsetnb dl\ncmp r9, rbx\nsetnb r10b\nor dl, r10b\njz loc_1608\nmov r10d, r8d\nmov rcx, rax\nxor edx, edx\nshr r10d, 2\nshl r10, 4\nnop dword ptr [rax+rax+00h]\nloc_14F8:\nmovdqu xmm1, xmmword ptr [rdi+rdx]\nmovdqu xmm3, xmmword ptr [rsi+rdx]\nadd rcx, 30h ; '0'\nmovdqu xmm0, xmmword ptr [r9+rdx]\nadd rdx, 10h\nmovdqa xmm2, xmm1\npunpckldq xmm2, xmm3\nmovdqa xmm4, xmm0\npshufd xmm2, xmm2, 84h\nshufps xmm4, xmm2, 0F0h\nshufps xmm2, xmm4, 84h\nmovups xmmword ptr [rcx-30h], xmm2\nmovdqa xmm2, xmm3\nmovdqa xmm4, xmm0\nshufps xmm2, xmm1, 89h\nshufps xmm3, xmm1, 0Fh\npshufd xmm2, xmm2, 78h ; 'x'\nshufps xmm1, xmm3, 8Ch\nshufps xmm0, xmm1, 9Eh\npshufd xmm0, xmm0, 78h ; 'x'\nshufps xmm4, xmm2, 5\nmovups xmmword ptr [rcx-10h], xmm0\nshufps xmm4, xmm2, 0E2h\nmovups xmmword ptr [rcx-20h], xmm4\ncmp rdx, r10\njnz short loc_14F8\nmov edx, r8d\nand edx, 0FFFFFFFCh\nlea ecx, [rdx+rdx*2]\ncmp r8d, edx\njz loc_15FC\nmov ebx, edx\nmovsxd r11, ecx\nadd ecx, 1\nmov r14d, [rdi+rbx*4]\nmovsxd rcx, ecx\nlea rbp, ds:0[r11*4]\nlea r10, ds:0[rbx*4]\nmov [rax+r11*4], r14d\nmov r14d, [rsi+rbx*4]\nlea r11, ds:0[rcx*4]\nmov [rax+rcx*4], r14d\nmov ecx, [r9+rbx*4]\nmov [rax+r11+4], ecx\nlea ecx, [rdx+1]\ncmp r8d, ecx\njle short loc_15FC\nmov ecx, [rdi+r10+4]\nadd edx, 2\nmov [rax+rbp+0Ch], ecx\nmov ecx, [rsi+r10+4]\nmov [rax+r11+0Ch], ecx\nmov ecx, [r9+r10+4]\nmov [rax+r11+10h], ecx\ncmp r8d, edx\njle short loc_15FC\nmov edx, [rdi+r10+8]\nmov [rax+rbp+18h], edx\nmov edx, [rsi+r10+8]\nmov [rax+r11+18h], edx\nmov edx, [r9+r10+8]\nmov [rax+r11+1Ch], edx\nloc_15FC:\npop rbx\npop rbp\npop r14\nretn\nloc_1608:\nshl rcx, 2\nxor edx, edx\nxchg ax, ax\nloc_1610:\nmov r8d, [rdi+rdx]\nadd rax, 0Ch\nmov [rax-0Ch], r8d\nmov r8d, [rsi+rdx]\nmov [rax-8], r8d\nmov r8d, [r9+rdx]\nadd rdx, 4\nmov [rax-4], r8d\ncmp rcx, rdx\njnz short loc_1610\npop rbx\npop rbp\npop r14\nretn\nlocret_1640:\nretn", + "ida_pseudo": "void __fastcall func0(unsigned __int64 a1, unsigned __int64 a2, unsigned __int64 a3, unsigned __int64 a4, int a5)\n{\n unsigned __int64 v6; // rax\n unsigned __int64 v7; // rbx\n __int64 v8; // rdx\n __m128 v9; // xmm1\n __m128 v10; // xmm3\n __m128 v11; // xmm0\n __m128 v12; // xmm2\n __m128 v13; // xmm2\n unsigned int v14; // edx\n signed int v15; // ecx\n __int64 v16; // rbp\n __int64 v17; // r10\n __int64 v18; // r11\n __int64 v19; // rcx\n __int64 v20; // rdx\n int v21; // r8d\n\n if ( a5 > 0 )\n {\n v6 = a4;\n if ( (unsigned int)(a5 - 1) > 2\n && (v7 = a4 + 12LL * a5, (a2 >= v7 || a4 >= a2 + 4LL * a5) && (a1 >= v7 || a4 >= a1 + 4LL * a5))\n && (a3 >= v7 || a4 >= a3 + 4LL * a5) )\n {\n v8 = 0LL;\n do\n {\n v9 = (__m128)_mm_loadu_si128((const __m128i *)(a1 + v8));\n v10 = (__m128)_mm_loadu_si128((const __m128i *)(a2 + v8));\n a4 += 48LL;\n v11 = (__m128)_mm_loadu_si128((const __m128i *)(a3 + v8));\n v8 += 16LL;\n v12 = (__m128)_mm_shuffle_epi32(_mm_unpacklo_epi32((__m128i)v9, (__m128i)v10), 132);\n *(__m128 *)(a4 - 48) = _mm_shuffle_ps(v12, _mm_shuffle_ps(v11, v12, 240), 132);\n v13 = (__m128)_mm_shuffle_epi32((__m128i)_mm_shuffle_ps(v10, v9, 137), 120);\n *(__m128i *)(a4 - 16) = _mm_shuffle_epi32(\n (__m128i)_mm_shuffle_ps(\n v11,\n _mm_shuffle_ps(v9, _mm_shuffle_ps(v10, v9, 15), 140),\n 158),\n 120);\n *(__m128 *)(a4 - 32) = _mm_shuffle_ps(_mm_shuffle_ps(v11, v13, 5), v13, 226);\n }\n while ( v8 != 16LL * ((unsigned int)a5 >> 2) );\n v14 = a5 & 0x7FFFFFFC;\n v15 = 3 * (a5 & 0xFFFFFFFC);\n if ( a5 != (a5 & 0xFFFFFFFC) )\n {\n v16 = 4LL * v15;\n v17 = 4LL * v14;\n *(_DWORD *)(v6 + v16) = *(_DWORD *)(a1 + v17);\n v18 = 4LL * (v15 + 1);\n *(_DWORD *)(v6 + v18) = *(_DWORD *)(a2 + v17);\n *(_DWORD *)(v6 + v18 + 4) = *(_DWORD *)(a3 + v17);\n if ( a5 > (int)(v14 + 1) )\n {\n *(_DWORD *)(v6 + v16 + 12) = *(_DWORD *)(a1 + v17 + 4);\n *(_DWORD *)(v6 + v18 + 12) = *(_DWORD *)(a2 + v17 + 4);\n *(_DWORD *)(v6 + v18 + 16) = *(_DWORD *)(a3 + v17 + 4);\n if ( a5 > (int)(v14 + 2) )\n {\n *(_DWORD *)(v6 + v16 + 24) = *(_DWORD *)(a1 + v17 + 8);\n *(_DWORD *)(v6 + v18 + 24) = *(_DWORD *)(a2 + v17 + 8);\n *(_DWORD *)(v6 + v18 + 28) = *(_DWORD *)(a3 + v17 + 8);\n }\n }\n }\n }\n else\n {\n v19 = 4LL * a5;\n v20 = 0LL;\n do\n {\n v6 += 12LL;\n *(_DWORD *)(v6 - 12) = *(_DWORD *)(a1 + v20);\n *(_DWORD *)(v6 - 8) = *(_DWORD *)(a2 + v20);\n v21 = *(_DWORD *)(a3 + v20);\n v20 += 4LL;\n *(_DWORD *)(v6 - 4) = v21;\n }\n while ( v19 != v20 );\n }\n }\n}", + "ida_strip_asm": "sub_1460:\nendbr64\ntest r8d, r8d\njle locret_1640\nmov r9, rdx\nlea edx, [r8-1]\npush r14\nmov rax, rcx\npush rbp\nmovsxd rcx, r8d\npush rbx\ncmp edx, 2\njbe loc_1608\nlea rdx, ds:0[rcx*4]\nlea r10, [rcx+rcx*2]\nlea rbx, [rax+r10*4]\nlea r10, [rdi+rdx]\ncmp rax, r10\nsetnb r11b\ncmp rdi, rbx\nsetnb r10b\nor r11d, r10d\nlea r10, [rsi+rdx]\ncmp rax, r10\nsetnb r10b\ncmp rsi, rbx\nsetnb bpl\nor r10d, ebp\ntest r11b, r10b\njz loc_1608\nadd rdx, r9\ncmp rax, rdx\nsetnb dl\ncmp r9, rbx\nsetnb r10b\nor dl, r10b\njz loc_1608\nmov r10d, r8d\nmov rcx, rax\nxor edx, edx\nshr r10d, 2\nshl r10, 4\nnop dword ptr [rax+rax+00h]\nloc_14F8:\nmovdqu xmm1, xmmword ptr [rdi+rdx]\nmovdqu xmm3, xmmword ptr [rsi+rdx]\nadd rcx, 30h ; '0'\nmovdqu xmm0, xmmword ptr [r9+rdx]\nadd rdx, 10h\nmovdqa xmm2, xmm1\npunpckldq xmm2, xmm3\nmovdqa xmm4, xmm0\npshufd xmm2, xmm2, 84h\nshufps xmm4, xmm2, 0F0h\nshufps xmm2, xmm4, 84h\nmovups xmmword ptr [rcx-30h], xmm2\nmovdqa xmm2, xmm3\nmovdqa xmm4, xmm0\nshufps xmm2, xmm1, 89h\nshufps xmm3, xmm1, 0Fh\npshufd xmm2, xmm2, 78h ; 'x'\nshufps xmm1, xmm3, 8Ch\nshufps xmm0, xmm1, 9Eh\npshufd xmm0, xmm0, 78h ; 'x'\nshufps xmm4, xmm2, 5\nmovups xmmword ptr [rcx-10h], xmm0\nshufps xmm4, xmm2, 0E2h\nmovups xmmword ptr [rcx-20h], xmm4\ncmp rdx, r10\njnz short loc_14F8\nmov edx, r8d\nand edx, 0FFFFFFFCh\nlea ecx, [rdx+rdx*2]\ncmp r8d, edx\njz loc_15FC\nmov ebx, edx\nmovsxd r11, ecx\nadd ecx, 1\nmov r14d, [rdi+rbx*4]\nmovsxd rcx, ecx\nlea rbp, ds:0[r11*4]\nlea r10, ds:0[rbx*4]\nmov [rax+r11*4], r14d\nmov r14d, [rsi+rbx*4]\nlea r11, ds:0[rcx*4]\nmov [rax+rcx*4], r14d\nmov ecx, [r9+rbx*4]\nmov [rax+r11+4], ecx\nlea ecx, [rdx+1]\ncmp r8d, ecx\njle short loc_15FC\nmov ecx, [rdi+r10+4]\nadd edx, 2\nmov [rax+rbp+0Ch], ecx\nmov ecx, [rsi+r10+4]\nmov [rax+r11+0Ch], ecx\nmov ecx, [r9+r10+4]\nmov [rax+r11+10h], ecx\ncmp r8d, edx\njle short loc_15FC\nmov edx, [rdi+r10+8]\nmov [rax+rbp+18h], edx\nmov edx, [rsi+r10+8]\nmov [rax+r11+18h], edx\nmov edx, [r9+r10+8]\nmov [rax+r11+1Ch], edx\nloc_15FC:\npop rbx\npop rbp\npop r14\nretn\nloc_1608:\nshl rcx, 2\nxor edx, edx\nxchg ax, ax\nloc_1610:\nmov r8d, [rdi+rdx]\nadd rax, 0Ch\nmov [rax-0Ch], r8d\nmov r8d, [rsi+rdx]\nmov [rax-8], r8d\nmov r8d, [r9+rdx]\nadd rdx, 4\nmov [rax-4], r8d\ncmp rcx, rdx\njnz short loc_1610\npop rbx\npop rbp\npop r14\nretn\nlocret_1640:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1460(unsigned __int64 a1, unsigned __int64 a2, unsigned __int64 a3, unsigned __int64 a4, int a5)\n{\n unsigned __int64 v6; // rax\n unsigned __int64 v7; // rbx\n __int64 v8; // rdx\n __m128 v9; // xmm1\n __m128 v10; // xmm3\n __m128 v11; // xmm0\n __m128 v12; // xmm2\n __m128 v13; // xmm2\n unsigned int v14; // edx\n signed int v15; // ecx\n __int64 v16; // rbp\n __int64 v17; // r10\n __int64 v18; // r11\n __int64 v19; // rcx\n __int64 v20; // rdx\n int v21; // r8d\n\n if ( a5 > 0 )\n {\n v6 = a4;\n if ( (unsigned int)(a5 - 1) > 2\n && (v7 = a4 + 12LL * a5, (a2 >= v7 || a4 >= a2 + 4LL * a5) && (a1 >= v7 || a4 >= a1 + 4LL * a5))\n && (a3 >= v7 || a4 >= a3 + 4LL * a5) )\n {\n v8 = 0LL;\n do\n {\n v9 = (__m128)_mm_loadu_si128((const __m128i *)(a1 + v8));\n v10 = (__m128)_mm_loadu_si128((const __m128i *)(a2 + v8));\n a4 += 48LL;\n v11 = (__m128)_mm_loadu_si128((const __m128i *)(a3 + v8));\n v8 += 16LL;\n v12 = (__m128)_mm_shuffle_epi32(_mm_unpacklo_epi32((__m128i)v9, (__m128i)v10), 132);\n *(__m128 *)(a4 - 48) = _mm_shuffle_ps(v12, _mm_shuffle_ps(v11, v12, 240), 132);\n v13 = (__m128)_mm_shuffle_epi32((__m128i)_mm_shuffle_ps(v10, v9, 137), 120);\n *(__m128i *)(a4 - 16) = _mm_shuffle_epi32(\n (__m128i)_mm_shuffle_ps(\n v11,\n _mm_shuffle_ps(v9, _mm_shuffle_ps(v10, v9, 15), 140),\n 158),\n 120);\n *(__m128 *)(a4 - 32) = _mm_shuffle_ps(_mm_shuffle_ps(v11, v13, 5), v13, 226);\n }\n while ( v8 != 16LL * ((unsigned int)a5 >> 2) );\n v14 = a5 & 0x7FFFFFFC;\n v15 = 3 * (a5 & 0xFFFFFFFC);\n if ( a5 != (a5 & 0xFFFFFFFC) )\n {\n v16 = 4LL * v15;\n v17 = 4LL * v14;\n *(_DWORD *)(v6 + v16) = *(_DWORD *)(a1 + v17);\n v18 = 4LL * (v15 + 1);\n *(_DWORD *)(v6 + v18) = *(_DWORD *)(a2 + v17);\n *(_DWORD *)(v6 + v18 + 4) = *(_DWORD *)(a3 + v17);\n if ( a5 > (int)(v14 + 1) )\n {\n *(_DWORD *)(v6 + v16 + 12) = *(_DWORD *)(a1 + v17 + 4);\n *(_DWORD *)(v6 + v18 + 12) = *(_DWORD *)(a2 + v17 + 4);\n *(_DWORD *)(v6 + v18 + 16) = *(_DWORD *)(a3 + v17 + 4);\n if ( a5 > (int)(v14 + 2) )\n {\n *(_DWORD *)(v6 + v16 + 24) = *(_DWORD *)(a1 + v17 + 8);\n *(_DWORD *)(v6 + v18 + 24) = *(_DWORD *)(a2 + v17 + 8);\n *(_DWORD *)(v6 + v18 + 28) = *(_DWORD *)(a3 + v17 + 8);\n }\n }\n }\n }\n else\n {\n v19 = 4LL * a5;\n v20 = 0LL;\n do\n {\n v6 += 12LL;\n *(_DWORD *)(v6 - 12) = *(_DWORD *)(a1 + v20);\n *(_DWORD *)(v6 - 8) = *(_DWORD *)(a2 + v20);\n v21 = *(_DWORD *)(a3 + v20);\n v20 += 4LL;\n *(_DWORD *)(v6 - 4) = v21;\n }\n while ( v19 != v20 );\n }\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1460(unsigned long long a1, unsigned long long a2,\n unsigned long long a3, unsigned long long a4, int a5) {\n unsigned long long v6;\n unsigned long long v7;\n long long v8;\n __m128 v9;\n __m128 v10;\n __m128 v11;\n __m128 v12;\n __m128 v13;\n unsigned int v14;\n signed int v15;\n long long v16;\n long long v17;\n long long v18;\n long long v19;\n long long v20;\n int v21;\n if (a5 > 0) {\n v6 = a4;\n if ((unsigned int)(a5 - 1) > 2 &&\n (v7 = a4 + 12LL * a5, (a2 >= v7 || a4 >= a2 + 4LL * a5) &&\n (a1 >= v7 || a4 >= a1 + 4LL * a5)) &&\n (a3 >= v7 || a4 >= a3 + 4LL * a5)) {\n v8 = 0LL;\n do {\n v9 = (__m128)_mm_loadu_si128((const __m128i *)(a1 + v8));\n v10 = (__m128)_mm_loadu_si128((const __m128i *)(a2 + v8));\n a4 += 48LL;\n v11 = (__m128)_mm_loadu_si128((const __m128i *)(a3 + v8));\n v8 += 16LL;\n v12 = (__m128)_mm_shuffle_epi32(\n _mm_unpacklo_epi32((__m128i)v9, (__m128i)v10), 132);\n *(__m128 *)(a4 - 48) =\n _mm_shuffle_ps(v12, _mm_shuffle_ps(v11, v12, 240), 132);\n v13 = (__m128)_mm_shuffle_epi32((__m128i)_mm_shuffle_ps(v10, v9, 137),\n 120);\n *(__m128i *)(a4 - 16) = _mm_shuffle_epi32(\n (__m128i)_mm_shuffle_ps(\n v11, _mm_shuffle_ps(v9, _mm_shuffle_ps(v10, v9, 15), 140), 158),\n 120);\n *(__m128 *)(a4 - 32) =\n _mm_shuffle_ps(_mm_shuffle_ps(v11, v13, 5), v13, 226);\n } while (v8 != 16LL * ((unsigned int)a5 >> 2));\n v14 = a5 & 2147483644;\n v15 = 3 * (a5 & 4294967292);\n if (a5 != (a5 & 4294967292)) {\n v16 = 4LL * v15;\n v17 = 4LL * v14;\n *(uint32_t *)(v6 + v16) = *(uint32_t *)(a1 + v17);\n v18 = 4LL * (v15 + 1);\n *(uint32_t *)(v6 + v18) = *(uint32_t *)(a2 + v17);\n *(uint32_t *)(v6 + v18 + 4) = *(uint32_t *)(a3 + v17);\n if (a5 > (int)(v14 + 1)) {\n *(uint32_t *)(v6 + v16 + 12) = *(uint32_t *)(a1 + v17 + 4);\n *(uint32_t *)(v6 + v18 + 12) = *(uint32_t *)(a2 + v17 + 4);\n *(uint32_t *)(v6 + v18 + 16) = *(uint32_t *)(a3 + v17 + 4);\n if (a5 > (int)(v14 + 2)) {\n *(uint32_t *)(v6 + v16 + 24) = *(uint32_t *)(a1 + v17 + 8);\n *(uint32_t *)(v6 + v18 + 24) = *(uint32_t *)(a2 + v17 + 8);\n *(uint32_t *)(v6 + v18 + 28) = *(uint32_t *)(a3 + v17 + 8);\n }\n }\n }\n } else {\n v19 = 4LL * a5;\n v20 = 0LL;\n do {\n v6 += 12LL;\n *(uint32_t *)(v6 - 12) = *(uint32_t *)(a1 + v20);\n *(uint32_t *)(v6 - 8) = *(uint32_t *)(a2 + v20);\n v21 = *(uint32_t *)(a3 + v20);\n v20 += 4LL;\n *(uint32_t *)(v6 - 4) = v21;\n } while (v19 != v20);\n }\n }\n}", + "ida_pseudo_norm": "void func0(unsigned long long a1, unsigned long long a2, unsigned long long a3,\n unsigned long long a4, int a5) {\n unsigned long long v6;\n unsigned long long v7;\n long long v8;\n __m128 v9;\n __m128 v10;\n __m128 v11;\n __m128 v12;\n __m128 v13;\n unsigned int v14;\n signed int v15;\n long long v16;\n long long v17;\n long long v18;\n long long v19;\n long long v20;\n int v21;\n if (a5 > 0) {\n v6 = a4;\n if ((unsigned int)(a5 - 1) > 2 &&\n (v7 = a4 + 12LL * a5, (a2 >= v7 || a4 >= a2 + 4LL * a5) &&\n (a1 >= v7 || a4 >= a1 + 4LL * a5)) &&\n (a3 >= v7 || a4 >= a3 + 4LL * a5)) {\n v8 = 0LL;\n do {\n v9 = (__m128)_mm_loadu_si128((const __m128i *)(a1 + v8));\n v10 = (__m128)_mm_loadu_si128((const __m128i *)(a2 + v8));\n a4 += 48LL;\n v11 = (__m128)_mm_loadu_si128((const __m128i *)(a3 + v8));\n v8 += 16LL;\n v12 = (__m128)_mm_shuffle_epi32(\n _mm_unpacklo_epi32((__m128i)v9, (__m128i)v10), 132);\n *(__m128 *)(a4 - 48) =\n _mm_shuffle_ps(v12, _mm_shuffle_ps(v11, v12, 240), 132);\n v13 = (__m128)_mm_shuffle_epi32((__m128i)_mm_shuffle_ps(v10, v9, 137),\n 120);\n *(__m128i *)(a4 - 16) = _mm_shuffle_epi32(\n (__m128i)_mm_shuffle_ps(\n v11, _mm_shuffle_ps(v9, _mm_shuffle_ps(v10, v9, 15), 140), 158),\n 120);\n *(__m128 *)(a4 - 32) =\n _mm_shuffle_ps(_mm_shuffle_ps(v11, v13, 5), v13, 226);\n } while (v8 != 16LL * ((unsigned int)a5 >> 2));\n v14 = a5 & 2147483644;\n v15 = 3 * (a5 & 4294967292);\n if (a5 != (a5 & 4294967292)) {\n v16 = 4LL * v15;\n v17 = 4LL * v14;\n *(uint32_t *)(v6 + v16) = *(uint32_t *)(a1 + v17);\n v18 = 4LL * (v15 + 1);\n *(uint32_t *)(v6 + v18) = *(uint32_t *)(a2 + v17);\n *(uint32_t *)(v6 + v18 + 4) = *(uint32_t *)(a3 + v17);\n if (a5 > (int)(v14 + 1)) {\n *(uint32_t *)(v6 + v16 + 12) = *(uint32_t *)(a1 + v17 + 4);\n *(uint32_t *)(v6 + v18 + 12) = *(uint32_t *)(a2 + v17 + 4);\n *(uint32_t *)(v6 + v18 + 16) = *(uint32_t *)(a3 + v17 + 4);\n if (a5 > (int)(v14 + 2)) {\n *(uint32_t *)(v6 + v16 + 24) = *(uint32_t *)(a1 + v17 + 8);\n *(uint32_t *)(v6 + v18 + 24) = *(uint32_t *)(a2 + v17 + 8);\n *(uint32_t *)(v6 + v18 + 28) = *(uint32_t *)(a3 + v17 + 8);\n }\n }\n }\n } else {\n v19 = 4LL * a5;\n v20 = 0LL;\n do {\n v6 += 12LL;\n *(uint32_t *)(v6 - 12) = *(uint32_t *)(a1 + v20);\n *(uint32_t *)(v6 - 8) = *(uint32_t *)(a2 + v20);\n v21 = *(uint32_t *)(a3 + v20);\n v20 += 4LL;\n *(uint32_t *)(v6 - 4) = v21;\n } while (v19 != v20);\n }\n }\n}" + }, + { + "index": 579, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n// Structure to hold the result tuple\n\ntypedef struct {\n\n int *data;\n\n size_t size;\n\n} tuple;\n\n\n\n// Function to check if a value exists in an array\n\nint contains(int *arr, size_t len, int val) {\n\n for (size_t i = 0; i < len; i++) {\n\n if (arr[i] == val)\n\n return 1;\n\n }\n\n return 0;\n\n}\n\n\n\n// Function to find symmetric difference\n\n", + "func": "tuple func0(int *a, size_t a_len, int *b, size_t b_len) {\n int *temp = malloc((a_len + b_len) * sizeof(int));\n size_t count = 0;\n for (size_t i = 0; i < a_len; i++) {\n if (!contains(b, b_len, a[i])) {\n temp[count++] = a[i];\n }\n }\n for (size_t i = 0; i < b_len; i++) {\n if (!contains(a, a_len, b[i])) {\n temp[count++] = b[i];\n }\n }\n for (size_t i = 0; i < count - 1; i++) {\n for (size_t j = i + 1; j < count; j++) {\n if (temp[i] > temp[j]) {\n int swap = temp[i];\n temp[i] = temp[j];\n temp[j] = swap;\n }\n }\n }\n tuple result;\n result.data = temp;\n result.size = count;\n return result;\n}", + "test": "int main() {\n\n // Test 1\n\n int test1_a[] = {3, 4, 5, 6};\n\n int test1_b[] = {5, 7, 4, 10};\n\n int expected1[] = {3, 6, 7, 10};\n\n tuple res1 = func0(test1_a, 4, test1_b, 4);\n\n assert(res1.size == 4);\n\n for (int i = 0; i < 4; i++) {\n\n assert(res1.data[i] == expected1[i]);\n\n }\n\n free(res1.data);\n\n\n\n // Test 2\n\n int test2_a[] = {1, 2, 3, 4};\n\n int test2_b[] = {7, 2, 3, 9};\n\n int expected2[] = {1, 4, 7, 9};\n\n tuple res2 = func0(test2_a, 4, test2_b, 4);\n\n assert(res2.size == 4);\n\n for (int i = 0; i < 4; i++) {\n\n assert(res2.data[i] == expected2[i]);\n\n }\n\n free(res2.data);\n\n\n\n // Test 3\n\n int test3_a[] = {21, 11, 25, 26};\n\n int test3_b[] = {26, 34, 21, 36};\n\n int expected3[] = {11, 25, 34, 36};\n\n tuple res3 = func0(test3_a, 4, test3_b, 4);\n\n assert(res3.size == 4);\n\n for (int i = 0; i < 4; i++) {\n\n assert(res3.data[i] == expected3[i]);\n\n }\n\n free(res3.data);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x70,%rsp\nmov %rdi,-0x58(%rbp)\nmov %rsi,-0x60(%rbp)\nmov %rdx,-0x68(%rbp)\nmov %rcx,-0x70(%rbp)\nmov -0x60(%rbp),%rdx\nmov -0x70(%rbp),%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x18(%rbp)\nmovq $0x0,-0x40(%rbp)\nmovq $0x0,-0x38(%rbp)\njmp 12aa \nmov -0x38(%rbp),%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x58(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x70(%rbp),%rcx\nmov -0x68(%rbp),%rax\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 11a9 \ntest %eax,%eax\njne 12a5 \nmov -0x38(%rbp),%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x58(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x40(%rbp),%rax\nlea 0x1(%rax),%rdx\nmov %rdx,-0x40(%rbp)\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\naddq $0x1,-0x38(%rbp)\nmov -0x38(%rbp),%rax\ncmp -0x60(%rbp),%rax\njb 1246 \nmovq $0x0,-0x30(%rbp)\njmp 1322 \nmov -0x30(%rbp),%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x68(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x60(%rbp),%rcx\nmov -0x58(%rbp),%rax\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 11a9 \ntest %eax,%eax\njne 131d \nmov -0x30(%rbp),%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x68(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x40(%rbp),%rax\nlea 0x1(%rax),%rdx\nmov %rdx,-0x40(%rbp)\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\naddq $0x1,-0x30(%rbp)\nmov -0x30(%rbp),%rax\ncmp -0x70(%rbp),%rax\njb 12be \nmovq $0x0,-0x28(%rbp)\njmpq 13ea \nmov -0x28(%rbp),%rax\nadd $0x1,%rax\nmov %rax,-0x20(%rbp)\njmpq 13d7 \nmov -0x28(%rbp),%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x20(%rbp),%rax\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njle 13d2 \nmov -0x28(%rbp),%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x44(%rbp)\nmov -0x20(%rbp),%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0x28(%rbp),%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\nmov -0x20(%rbp),%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0x44(%rbp),%eax\nmov %eax,(%rdx)\naddq $0x1,-0x20(%rbp)\nmov -0x20(%rbp),%rax\ncmp -0x40(%rbp),%rax\njb 134a \naddq $0x1,-0x28(%rbp)\nmov -0x40(%rbp),%rax\nsub $0x1,%rax\ncmp %rax,-0x28(%rbp)\njb 1339 \nmov -0x18(%rbp),%rax\nmov %rax,-0x10(%rbp)\nmov -0x40(%rbp),%rax\nmov %rax,-0x8(%rbp)\nmov -0x10(%rbp),%rax\nmov -0x8(%rbp),%rdx\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+var_58], rdi\nmov [rbp+var_60], rsi\nmov [rbp+var_68], rdx\nmov [rbp+var_70], rcx\nmov rdx, [rbp+var_60]\nmov rax, [rbp+var_70]\nadd rax, rdx\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_40], 0\nmov [rbp+var_38], 0\njmp short loc_12AA\nloc_1246:\nmov rax, [rbp+var_38]\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov edx, [rax]\nmov rcx, [rbp+var_70]\nmov rax, [rbp+var_68]\nmov rsi, rcx\nmov rdi, rax\ncall contains\ntest eax, eax\njnz short loc_12A5\nmov rax, [rbp+var_38]\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nlea rcx, [rdx+rax]\nmov rax, [rbp+var_40]\nlea rdx, [rax+1]\nmov [rbp+var_40], rdx\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_12A5:\nadd [rbp+var_38], 1\nloc_12AA:\nmov rax, [rbp+var_38]\ncmp rax, [rbp+var_60]\njb short loc_1246\nmov [rbp+var_30], 0\njmp short loc_1322\nloc_12BE:\nmov rax, [rbp+var_30]\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_68]\nadd rax, rdx\nmov edx, [rax]\nmov rcx, [rbp+var_60]\nmov rax, [rbp+var_58]\nmov rsi, rcx\nmov rdi, rax\ncall contains\ntest eax, eax\njnz short loc_131D\nmov rax, [rbp+var_30]\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_68]\nlea rcx, [rdx+rax]\nmov rax, [rbp+var_40]\nlea rdx, [rax+1]\nmov [rbp+var_40], rdx\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_131D:\nadd [rbp+var_30], 1\nloc_1322:\nmov rax, [rbp+var_30]\ncmp rax, [rbp+var_70]\njb short loc_12BE\nmov [rbp+var_28], 0\njmp loc_13EA\nloc_1339:\nmov rax, [rbp+var_28]\nadd rax, 1\nmov [rbp+var_20], rax\njmp loc_13D7\nloc_134A:\nmov rax, [rbp+var_28]\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_20]\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_13D2\nmov rax, [rbp+var_28]\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_44], eax\nmov rax, [rbp+var_20]\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rdx, [rbp+var_28]\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov rax, [rbp+var_20]\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_44]\nmov [rdx], eax\nloc_13D2:\nadd [rbp+var_20], 1\nloc_13D7:\nmov rax, [rbp+var_20]\ncmp rax, [rbp+var_40]\njb loc_134A\nadd [rbp+var_28], 1\nloc_13EA:\nmov rax, [rbp+var_40]\nsub rax, 1\ncmp [rbp+var_28], rax\njb loc_1339\nmov rax, [rbp+var_18]\nmov [rbp+var_10], rax\nmov rax, [rbp+var_40]\nmov [rbp+var_8], rax\nmov rax, [rbp+var_10]\nmov rdx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, unsigned __int64 a2, __int64 a3, unsigned __int64 a4)\n{\n unsigned __int64 v4; // rax\n unsigned __int64 v5; // rax\n int v9; // [rsp+2Ch] [rbp-44h]\n unsigned __int64 v10; // [rsp+30h] [rbp-40h]\n unsigned __int64 i; // [rsp+38h] [rbp-38h]\n unsigned __int64 j; // [rsp+40h] [rbp-30h]\n unsigned __int64 k; // [rsp+48h] [rbp-28h]\n unsigned __int64 m; // [rsp+50h] [rbp-20h]\n _DWORD *v15; // [rsp+58h] [rbp-18h]\n\n v15 = malloc(4 * (a2 + a4));\n v10 = 0LL;\n for ( i = 0LL; i < a2; ++i )\n {\n if ( !(unsigned int)contains(a3, a4, *(unsigned int *)(4 * i + a1)) )\n {\n v4 = v10++;\n v15[v4] = *(_DWORD *)(4 * i + a1);\n }\n }\n for ( j = 0LL; j < a4; ++j )\n {\n if ( !(unsigned int)contains(a1, a2, *(unsigned int *)(4 * j + a3)) )\n {\n v5 = v10++;\n v15[v5] = *(_DWORD *)(4 * j + a3);\n }\n }\n for ( k = 0LL; k < v10 - 1; ++k )\n {\n for ( m = k + 1; m < v10; ++m )\n {\n if ( v15[k] > v15[m] )\n {\n v9 = v15[k];\n v15[k] = v15[m];\n v15[m] = v9;\n }\n }\n }\n return v15;\n}", + "ida_strip_asm": "sub_11FD:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+var_58], rdi\nmov [rbp+var_60], rsi\nmov [rbp+var_68], rdx\nmov [rbp+var_70], rcx\nmov rdx, [rbp+var_60]\nmov rax, [rbp+var_70]\nadd rax, rdx\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_40], 0\nmov [rbp+var_38], 0\njmp short loc_12AA\nloc_1246:\nmov rax, [rbp+var_38]\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov edx, [rax]\nmov rcx, [rbp+var_70]\nmov rax, [rbp+var_68]\nmov rsi, rcx\nmov rdi, rax\ncall sub_11A9\ntest eax, eax\njnz short loc_12A5\nmov rax, [rbp+var_38]\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nlea rcx, [rdx+rax]\nmov rax, [rbp+var_40]\nlea rdx, [rax+1]\nmov [rbp+var_40], rdx\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_12A5:\nadd [rbp+var_38], 1\nloc_12AA:\nmov rax, [rbp+var_38]\ncmp rax, [rbp+var_60]\njb short loc_1246\nmov [rbp+var_30], 0\njmp short loc_1322\nloc_12BE:\nmov rax, [rbp+var_30]\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_68]\nadd rax, rdx\nmov edx, [rax]\nmov rcx, [rbp+var_60]\nmov rax, [rbp+var_58]\nmov rsi, rcx\nmov rdi, rax\ncall sub_11A9\ntest eax, eax\njnz short loc_131D\nmov rax, [rbp+var_30]\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_68]\nlea rcx, [rdx+rax]\nmov rax, [rbp+var_40]\nlea rdx, [rax+1]\nmov [rbp+var_40], rdx\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_131D:\nadd [rbp+var_30], 1\nloc_1322:\nmov rax, [rbp+var_30]\ncmp rax, [rbp+var_70]\njb short loc_12BE\nmov [rbp+var_28], 0\njmp loc_13EA\nloc_1339:\nmov rax, [rbp+var_28]\nadd rax, 1\nmov [rbp+var_20], rax\njmp loc_13D7\nloc_134A:\nmov rax, [rbp+var_28]\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_20]\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_13D2\nmov rax, [rbp+var_28]\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_44], eax\nmov rax, [rbp+var_20]\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rdx, [rbp+var_28]\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov rax, [rbp+var_20]\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_44]\nmov [rdx], eax\nloc_13D2:\nadd [rbp+var_20], 1\nloc_13D7:\nmov rax, [rbp+var_20]\ncmp rax, [rbp+var_40]\njb loc_134A\nadd [rbp+var_28], 1\nloc_13EA:\nmov rax, [rbp+var_40]\nsub rax, 1\ncmp [rbp+var_28], rax\njb loc_1339\nmov rax, [rbp+var_18]\nmov [rbp+var_10], rax\nmov rax, [rbp+var_40]\nmov [rbp+var_8], rax\nmov rax, [rbp+var_10]\nmov rdx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11FD(__int64 a1, unsigned __int64 a2, __int64 a3, unsigned __int64 a4)\n{\n unsigned __int64 v4; // rax\n unsigned __int64 v5; // rax\n int v9; // [rsp+2Ch] [rbp-44h]\n unsigned __int64 v10; // [rsp+30h] [rbp-40h]\n unsigned __int64 i; // [rsp+38h] [rbp-38h]\n unsigned __int64 j; // [rsp+40h] [rbp-30h]\n unsigned __int64 k; // [rsp+48h] [rbp-28h]\n unsigned __int64 m; // [rsp+50h] [rbp-20h]\n _DWORD *v15; // [rsp+58h] [rbp-18h]\n\n v15 = malloc(4 * (a2 + a4));\n v10 = 0LL;\n for ( i = 0LL; i < a2; ++i )\n {\n if ( !(unsigned int)sub_11A9(a3, a4, *(unsigned int *)(4 * i + a1)) )\n {\n v4 = v10++;\n v15[v4] = *(_DWORD *)(4 * i + a1);\n }\n }\n for ( j = 0LL; j < a4; ++j )\n {\n if ( !(unsigned int)sub_11A9(a1, a2, *(unsigned int *)(4 * j + a3)) )\n {\n v5 = v10++;\n v15[v5] = *(_DWORD *)(4 * j + a3);\n }\n }\n for ( k = 0LL; k < v10 - 1; ++k )\n {\n for ( m = k + 1; m < v10; ++m )\n {\n if ( v15[k] > v15[m] )\n {\n v9 = v15[k];\n v15[k] = v15[m];\n v15[m] = v9;\n }\n }\n }\n return v15;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11FD(long long a1, unsigned long long a2, long long a3,\n unsigned long long a4) {\n unsigned long long v4;\n unsigned long long v5;\n int v9;\n unsigned long long v10;\n unsigned long long i;\n unsigned long long j;\n unsigned long long k;\n unsigned long long m;\n uint32_t *v15;\n v15 = malloc(4 * (a2 + a4));\n v10 = 0LL;\n for (i = 0LL; i < a2; ++i) {\n if (!(unsigned int)sub_11A9(a3, a4, *(unsigned int *)(4 * i + a1))) {\n v4 = v10++;\n v15[v4] = *(uint32_t *)(4 * i + a1);\n }\n }\n for (j = 0LL; j < a4; ++j) {\n if (!(unsigned int)sub_11A9(a1, a2, *(unsigned int *)(4 * j + a3))) {\n v5 = v10++;\n v15[v5] = *(uint32_t *)(4 * j + a3);\n }\n }\n for (k = 0LL; k < v10 - 1; ++k) {\n for (m = k + 1; m < v10; ++m) {\n if (v15[k] > v15[m]) {\n v9 = v15[k];\n v15[k] = v15[m];\n v15[m] = v9;\n }\n }\n }\n return v15;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, unsigned long long a2, long long a3,\n unsigned long long a4) {\n unsigned long long v4;\n unsigned long long v5;\n int v9;\n unsigned long long v10;\n unsigned long long i;\n unsigned long long j;\n unsigned long long k;\n unsigned long long m;\n uint32_t *v15;\n v15 = malloc(4 * (a2 + a4));\n v10 = 0LL;\n for (i = 0LL; i < a2; ++i) {\n if (!(unsigned int)contains(a3, a4, *(unsigned int *)(4 * i + a1))) {\n v4 = v10++;\n v15[v4] = *(uint32_t *)(4 * i + a1);\n }\n }\n for (j = 0LL; j < a4; ++j) {\n if (!(unsigned int)contains(a1, a2, *(unsigned int *)(4 * j + a3))) {\n v5 = v10++;\n v15[v5] = *(uint32_t *)(4 * j + a3);\n }\n }\n for (k = 0LL; k < v10 - 1; ++k) {\n for (m = k + 1; m < v10; ++m) {\n if (v15[k] > v15[m]) {\n v9 = v15[k];\n v15[k] = v15[m];\n v15[m] = v9;\n }\n }\n }\n return v15;\n}" + }, + { + "index": 579, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n// Structure to hold the result tuple\n\ntypedef struct {\n\n int *data;\n\n size_t size;\n\n} tuple;\n\n\n\n// Function to check if a value exists in an array\n\nint contains(int *arr, size_t len, int val) {\n\n for (size_t i = 0; i < len; i++) {\n\n if (arr[i] == val)\n\n return 1;\n\n }\n\n return 0;\n\n}\n\n\n\n// Function to find symmetric difference\n\n", + "func": "tuple func0(int *a, size_t a_len, int *b, size_t b_len) {\n int *temp = malloc((a_len + b_len) * sizeof(int));\n size_t count = 0;\n for (size_t i = 0; i < a_len; i++) {\n if (!contains(b, b_len, a[i])) {\n temp[count++] = a[i];\n }\n }\n for (size_t i = 0; i < b_len; i++) {\n if (!contains(a, a_len, b[i])) {\n temp[count++] = b[i];\n }\n }\n for (size_t i = 0; i < count - 1; i++) {\n for (size_t j = i + 1; j < count; j++) {\n if (temp[i] > temp[j]) {\n int swap = temp[i];\n temp[i] = temp[j];\n temp[j] = swap;\n }\n }\n }\n tuple result;\n result.data = temp;\n result.size = count;\n return result;\n}", + "test": "int main() {\n\n // Test 1\n\n int test1_a[] = {3, 4, 5, 6};\n\n int test1_b[] = {5, 7, 4, 10};\n\n int expected1[] = {3, 6, 7, 10};\n\n tuple res1 = func0(test1_a, 4, test1_b, 4);\n\n assert(res1.size == 4);\n\n for (int i = 0; i < 4; i++) {\n\n assert(res1.data[i] == expected1[i]);\n\n }\n\n free(res1.data);\n\n\n\n // Test 2\n\n int test2_a[] = {1, 2, 3, 4};\n\n int test2_b[] = {7, 2, 3, 9};\n\n int expected2[] = {1, 4, 7, 9};\n\n tuple res2 = func0(test2_a, 4, test2_b, 4);\n\n assert(res2.size == 4);\n\n for (int i = 0; i < 4; i++) {\n\n assert(res2.data[i] == expected2[i]);\n\n }\n\n free(res2.data);\n\n\n\n // Test 3\n\n int test3_a[] = {21, 11, 25, 26};\n\n int test3_b[] = {26, 34, 21, 36};\n\n int expected3[] = {11, 25, 34, 36};\n\n tuple res3 = func0(test3_a, 4, test3_b, 4);\n\n assert(res3.size == 4);\n\n for (int i = 0; i < 4; i++) {\n\n assert(res3.data[i] == expected3[i]);\n\n }\n\n free(res3.data);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x28,%rsp\nmov %rdi,%r15\nmov %rdi,0x10(%rsp)\nmov %rsi,%rbx\nmov %rsi,0x8(%rsp)\nmov %rdx,%r13\nmov %rcx,%r12\nlea (%rsi,%rcx,1),%rdi\nshl $0x2,%rdi\ncallq 10b0 \nmov %rax,%r14\ntest %rbx,%rbx\nje 12f3 \nmov %r15,%rbp\nlea (%r15,%rbx,4),%rax\nmov %rax,0x18(%rsp)\nmov $0x0,%ebx\njmp 1236 \nadd $0x4,%rbp\ncmp 0x18(%rsp),%rbp\nje 1256 \nmov 0x0(%rbp),%r15d\nmov %r15d,%edx\nmov %r12,%rsi\nmov %r13,%rdi\ncallq 11a9 \ntest %eax,%eax\njne 122b \nmov %r15d,(%r14,%rbx,4)\nlea 0x1(%rbx),%rbx\njmp 122b \ntest %r12,%r12\nje 1290 \nmov $0x0,%ebp\njmp 126b \nadd $0x1,%rbp\ncmp %rbp,%r12\njbe 1290 \nmov 0x0(%r13,%rbp,4),%r15d\nmov %r15d,%edx\nmov 0x8(%rsp),%rsi\nmov 0x10(%rsp),%rdi\ncallq 11a9 \ntest %eax,%eax\njne 1262 \nmov %r15d,(%r14,%rbx,4)\nlea 0x1(%rbx),%rbx\njmp 1262 \nmov %rbx,%r9\nsub $0x1,%r9\nje 12d9 \nlea 0x4(%r14),%rsi\nlea (%r14,%rbx,4),%rdi\nmov $0x0,%r8d\njmp 12cb \nadd $0x4,%rax\ncmp %rax,%rdi\nje 12c2 \nmov -0x4(%rsi),%edx\nmov (%rax),%ecx\ncmp %ecx,%edx\njle 12a9 \nmov %ecx,-0x4(%rsi)\nmov %edx,(%rax)\njmp 12a9 \nadd $0x4,%rsi\ncmp %r9,%r8\njae 12de \nadd $0x1,%r8\ncmp %r8,%rbx\njbe 12c2 \nmov %rsi,%rax\njmp 12b2 \nmov $0x1,%ebx\nmov %r14,%rax\nmov %rbx,%rdx\nadd $0x28,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmov 0x8(%rsp),%rbx\ntest %r12,%r12\njne 125b \nmov %r12,%rbx\nmov $0xffffffffffffffff,%r9\njmp 1299 \n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov rbx, rdi\nmov [rsp+58h+var_40], rdi\nmov r13, rsi\nmov [rsp+58h+var_48], rdx\nmov [rsp+58h+var_50], rcx\nlea rdi, [rsi+rcx]\nshl rdi, 2; size\ncall _malloc\nmov r14, rax\ntest r13, r13\njz loc_12E2\nmov rbp, rbx\nlea r15, [rbx+r13*4]\nmov ebx, 0\njmp short loc_122E\nloc_1225:\nadd rbp, 4\ncmp rbp, r15\njz short loc_1252\nloc_122E:\nmov r12d, [rbp+0]\nmov edx, r12d\nmov rsi, [rsp+58h+var_50]\nmov rdi, [rsp+58h+var_48]\ncall contains\ntest eax, eax\njnz short loc_1225\nmov [r14+rbx*4], r12d\nlea rbx, [rbx+1]\njmp short loc_1225\nloc_1252:\ncmp [rsp+58h+var_50], 0\njz short loc_1298\nloc_125A:\nmov rax, [rsp+58h+var_48]\nmov rbp, rax\nmov rdi, [rsp+58h+var_50]\nlea r15, [rax+rdi*4]\njmp short loc_1276\nloc_126D:\nadd rbp, 4\ncmp rbp, r15\njz short loc_1298\nloc_1276:\nmov r12d, [rbp+0]\nmov edx, r12d\nmov rsi, r13\nmov rdi, [rsp+58h+var_40]\ncall contains\ntest eax, eax\njnz short loc_126D\nmov [r14+rbx*4], r12d\nlea rbx, [rbx+1]\njmp short loc_126D\nloc_1298:\nlea r9, [rbx-1]\ncmp rbx, 1\njz short loc_12FF\nloc_12A2:\nlea rsi, [r14+4]\nlea rdi, [r14+rbx*4]\nmov r8d, 0\njmp short loc_12D4\nloc_12B2:\nadd rax, 4\ncmp rax, rdi\njz short loc_12CB\nloc_12BB:\nmov edx, [rsi-4]\nmov ecx, [rax]\ncmp edx, ecx\njle short loc_12B2\nmov [rsi-4], ecx\nmov [rax], edx\njmp short loc_12B2\nloc_12CB:\nadd rsi, 4\ncmp r8, r9\njz short loc_12FF\nloc_12D4:\nadd r8, 1\ncmp r8, rbx\njnb short loc_12CB\nmov rax, rsi\njmp short loc_12BB\nloc_12E2:\nmov rbx, r13\ncmp [rsp+58h+var_50], 0\njnz loc_125A\nmov rbx, [rsp+58h+var_50]\nmov r9, 0FFFFFFFFFFFFFFFFh\njmp short loc_12A2\nloc_12FF:\nmov rax, r14\nmov rdx, rbx\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(unsigned int *a1, __int64 a2, unsigned int *a3, __int64 a4)\n{\n _DWORD *v4; // r14\n unsigned int *v5; // rbp\n unsigned __int64 v6; // rbx\n unsigned int v7; // r12d\n unsigned int *v8; // rbp\n unsigned int v9; // r12d\n __int64 v10; // r9\n _DWORD *v11; // rsi\n __int64 v12; // r8\n _DWORD *v13; // rax\n int v14; // edx\n\n v4 = malloc(4 * (a2 + a4));\n if ( a2 )\n {\n v5 = a1;\n v6 = 0LL;\n do\n {\n v7 = *v5;\n if ( !(unsigned int)contains(a3, a4, *v5) )\n v4[v6++] = v7;\n ++v5;\n }\n while ( v5 != &a1[a2] );\n if ( !a4 )\n {\nLABEL_11:\n v10 = v6 - 1;\n if ( v6 == 1 )\n return v4;\n goto LABEL_12;\n }\nLABEL_7:\n v8 = a3;\n do\n {\n v9 = *v8;\n if ( !(unsigned int)contains(a1, a2, *v8) )\n v4[v6++] = v9;\n ++v8;\n }\n while ( v8 != &a3[a4] );\n goto LABEL_11;\n }\n v6 = 0LL;\n if ( a4 )\n goto LABEL_7;\n v6 = 0LL;\n v10 = -1LL;\nLABEL_12:\n v11 = v4 + 1;\n v12 = 0LL;\n do\n {\n if ( ++v12 < v6 )\n {\n v13 = v11;\n do\n {\n v14 = *(v11 - 1);\n if ( v14 > *v13 )\n {\n *(v11 - 1) = *v13;\n *v13 = v14;\n }\n ++v13;\n }\n while ( v13 != &v4[v6] );\n }\n ++v11;\n }\n while ( v12 != v10 );\n return v4;\n}", + "ida_strip_asm": "sub_11D7:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov rbx, rdi\nmov [rsp+58h+var_40], rdi\nmov r13, rsi\nmov [rsp+58h+var_48], rdx\nmov [rsp+58h+var_50], rcx\nlea rdi, [rsi+rcx]\nshl rdi, 2; size\ncall _malloc\nmov r14, rax\ntest r13, r13\njz loc_12E2\nmov rbp, rbx\nlea r15, [rbx+r13*4]\nmov ebx, 0\njmp short loc_122E\nloc_1225:\nadd rbp, 4\ncmp rbp, r15\njz short loc_1252\nloc_122E:\nmov r12d, [rbp+0]\nmov edx, r12d\nmov rsi, [rsp+58h+var_50]\nmov rdi, [rsp+58h+var_48]\ncall sub_11A9\ntest eax, eax\njnz short loc_1225\nmov [r14+rbx*4], r12d\nlea rbx, [rbx+1]\njmp short loc_1225\nloc_1252:\ncmp [rsp+58h+var_50], 0\njz short loc_1298\nloc_125A:\nmov rax, [rsp+58h+var_48]\nmov rbp, rax\nmov rdi, [rsp+58h+var_50]\nlea r15, [rax+rdi*4]\njmp short loc_1276\nloc_126D:\nadd rbp, 4\ncmp rbp, r15\njz short loc_1298\nloc_1276:\nmov r12d, [rbp+0]\nmov edx, r12d\nmov rsi, r13\nmov rdi, [rsp+58h+var_40]\ncall sub_11A9\ntest eax, eax\njnz short loc_126D\nmov [r14+rbx*4], r12d\nlea rbx, [rbx+1]\njmp short loc_126D\nloc_1298:\nlea r9, [rbx-1]\ncmp rbx, 1\njz short loc_12FF\nloc_12A2:\nlea rsi, [r14+4]\nlea rdi, [r14+rbx*4]\nmov r8d, 0\njmp short loc_12D4\nloc_12B2:\nadd rax, 4\ncmp rax, rdi\njz short loc_12CB\nloc_12BB:\nmov edx, [rsi-4]\nmov ecx, [rax]\ncmp edx, ecx\njle short loc_12B2\nmov [rsi-4], ecx\nmov [rax], edx\njmp short loc_12B2\nloc_12CB:\nadd rsi, 4\ncmp r8, r9\njz short loc_12FF\nloc_12D4:\nadd r8, 1\ncmp r8, rbx\njnb short loc_12CB\nmov rax, rsi\njmp short loc_12BB\nloc_12E2:\nmov rbx, r13\ncmp [rsp+58h+var_50], 0\njnz loc_125A\nmov rbx, [rsp+58h+var_50]\nmov r9, 0FFFFFFFFFFFFFFFFh\njmp short loc_12A2\nloc_12FF:\nmov rax, r14\nmov rdx, rbx\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11D7(unsigned int *a1, __int64 a2, unsigned int *a3, __int64 a4)\n{\n _DWORD *v4; // r14\n unsigned int *v5; // rbp\n unsigned __int64 v6; // rbx\n unsigned int v7; // r12d\n unsigned int *v8; // rbp\n unsigned int v9; // r12d\n __int64 v10; // r9\n _DWORD *v11; // rsi\n __int64 v12; // r8\n _DWORD *v13; // rax\n int v14; // edx\n\n v4 = malloc(4 * (a2 + a4));\n if ( a2 )\n {\n v5 = a1;\n v6 = 0LL;\n do\n {\n v7 = *v5;\n if ( !(unsigned int)sub_11A9(a3, a4, *v5) )\n v4[v6++] = v7;\n ++v5;\n }\n while ( v5 != &a1[a2] );\n if ( !a4 )\n {\nLABEL_11:\n v10 = v6 - 1;\n if ( v6 == 1 )\n return v4;\n goto LABEL_12;\n }\nLABEL_7:\n v8 = a3;\n do\n {\n v9 = *v8;\n if ( !(unsigned int)sub_11A9(a1, a2, *v8) )\n v4[v6++] = v9;\n ++v8;\n }\n while ( v8 != &a3[a4] );\n goto LABEL_11;\n }\n v6 = 0LL;\n if ( a4 )\n goto LABEL_7;\n v6 = 0LL;\n v10 = -1LL;\nLABEL_12:\n v11 = v4 + 1;\n v12 = 0LL;\n do\n {\n if ( ++v12 < v6 )\n {\n v13 = v11;\n do\n {\n v14 = *(v11 - 1);\n if ( v14 > *v13 )\n {\n *(v11 - 1) = *v13;\n *v13 = v14;\n }\n ++v13;\n }\n while ( v13 != &v4[v6] );\n }\n ++v11;\n }\n while ( v12 != v10 );\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11D7(unsigned int *a1, long long a2, unsigned int *a3,\n long long a4) {\n uint32_t *v4;\n unsigned int *v5;\n unsigned long long v6;\n unsigned int v7;\n unsigned int *v8;\n unsigned int v9;\n long long v10;\n uint32_t *v11;\n long long v12;\n uint32_t *v13;\n int v14;\n v4 = malloc(4 * (a2 + a4));\n if (a2) {\n v5 = a1;\n v6 = 0LL;\n do {\n v7 = *v5;\n if (!(unsigned int)sub_11A9(a3, a4, *v5)) v4[v6++] = v7;\n ++v5;\n } while (v5 != &a1[a2]);\n if (!a4) {\n LABEL_11:\n v10 = v6 - 1;\n if (v6 == 1) return v4;\n goto LABEL_12;\n }\n LABEL_7:\n v8 = a3;\n do {\n v9 = *v8;\n if (!(unsigned int)sub_11A9(a1, a2, *v8)) v4[v6++] = v9;\n ++v8;\n } while (v8 != &a3[a4]);\n goto LABEL_11;\n }\n v6 = 0LL;\n if (a4) goto LABEL_7;\n v6 = 0LL;\n v10 = -1LL;\nLABEL_12:\n v11 = v4 + 1;\n v12 = 0LL;\n do {\n if (++v12 < v6) {\n v13 = v11;\n do {\n v14 = *(v11 - 1);\n if (v14 > *v13) {\n *(v11 - 1) = *v13;\n *v13 = v14;\n }\n ++v13;\n } while (v13 != &v4[v6]);\n }\n ++v11;\n } while (v12 != v10);\n return v4;\n}", + "ida_pseudo_norm": "uint32_t *func0(unsigned int *a1, long long a2, unsigned int *a3,\n long long a4) {\n uint32_t *v4;\n unsigned int *v5;\n unsigned long long v6;\n unsigned int v7;\n unsigned int *v8;\n unsigned int v9;\n long long v10;\n uint32_t *v11;\n long long v12;\n uint32_t *v13;\n int v14;\n v4 = malloc(4 * (a2 + a4));\n if (a2) {\n v5 = a1;\n v6 = 0LL;\n do {\n v7 = *v5;\n if (!(unsigned int)contains(a3, a4, *v5)) v4[v6++] = v7;\n ++v5;\n } while (v5 != &a1[a2]);\n if (!a4) {\n LABEL_11:\n v10 = v6 - 1;\n if (v6 == 1) return v4;\n goto LABEL_12;\n }\n LABEL_7:\n v8 = a3;\n do {\n v9 = *v8;\n if (!(unsigned int)contains(a1, a2, *v8)) v4[v6++] = v9;\n ++v8;\n } while (v8 != &a3[a4]);\n goto LABEL_11;\n }\n v6 = 0LL;\n if (a4) goto LABEL_7;\n v6 = 0LL;\n v10 = -1LL;\nLABEL_12:\n v11 = v4 + 1;\n v12 = 0LL;\n do {\n if (++v12 < v6) {\n v13 = v11;\n do {\n v14 = *(v11 - 1);\n if (v14 > *v13) {\n *(v11 - 1) = *v13;\n *v13 = v14;\n }\n ++v13;\n } while (v13 != &v4[v6]);\n }\n ++v11;\n } while (v12 != v10);\n return v4;\n}" + }, + { + "index": 579, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n// Structure to hold the result tuple\n\ntypedef struct {\n\n int *data;\n\n size_t size;\n\n} tuple;\n\n\n\n// Function to check if a value exists in an array\n\nint contains(int *arr, size_t len, int val) {\n\n for (size_t i = 0; i < len; i++) {\n\n if (arr[i] == val)\n\n return 1;\n\n }\n\n return 0;\n\n}\n\n\n\n// Function to find symmetric difference\n\n", + "func": "tuple func0(int *a, size_t a_len, int *b, size_t b_len) {\n int *temp = malloc((a_len + b_len) * sizeof(int));\n size_t count = 0;\n for (size_t i = 0; i < a_len; i++) {\n if (!contains(b, b_len, a[i])) {\n temp[count++] = a[i];\n }\n }\n for (size_t i = 0; i < b_len; i++) {\n if (!contains(a, a_len, b[i])) {\n temp[count++] = b[i];\n }\n }\n for (size_t i = 0; i < count - 1; i++) {\n for (size_t j = i + 1; j < count; j++) {\n if (temp[i] > temp[j]) {\n int swap = temp[i];\n temp[i] = temp[j];\n temp[j] = swap;\n }\n }\n }\n tuple result;\n result.data = temp;\n result.size = count;\n return result;\n}", + "test": "int main() {\n\n // Test 1\n\n int test1_a[] = {3, 4, 5, 6};\n\n int test1_b[] = {5, 7, 4, 10};\n\n int expected1[] = {3, 6, 7, 10};\n\n tuple res1 = func0(test1_a, 4, test1_b, 4);\n\n assert(res1.size == 4);\n\n for (int i = 0; i < 4; i++) {\n\n assert(res1.data[i] == expected1[i]);\n\n }\n\n free(res1.data);\n\n\n\n // Test 2\n\n int test2_a[] = {1, 2, 3, 4};\n\n int test2_b[] = {7, 2, 3, 9};\n\n int expected2[] = {1, 4, 7, 9};\n\n tuple res2 = func0(test2_a, 4, test2_b, 4);\n\n assert(res2.size == 4);\n\n for (int i = 0; i < 4; i++) {\n\n assert(res2.data[i] == expected2[i]);\n\n }\n\n free(res2.data);\n\n\n\n // Test 3\n\n int test3_a[] = {21, 11, 25, 26};\n\n int test3_b[] = {26, 34, 21, 36};\n\n int expected3[] = {11, 25, 34, 36};\n\n tuple res3 = func0(test3_a, 4, test3_b, 4);\n\n assert(res3.size == 4);\n\n for (int i = 0; i < 4; i++) {\n\n assert(res3.data[i] == expected3[i]);\n\n }\n\n free(res3.data);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov %rsi,%r13\npush %r12\nmov %rdi,%r12\nlea (%rsi,%rcx,1),%rdi\npush %rbp\nshl $0x2,%rdi\nmov %rcx,%rbp\npush %rbx\nmov %rdx,%rbx\nsub $0x8,%rsp\ncallq 10b0 \ntest %r13,%r13\nje 160a \nmov %r12,%rcx\nlea (%r12,%r13,4),%rsi\nxor %r9d,%r9d\nnopw 0x0(%rax,%rax,1)\nmov (%rcx),%edx\ntest %rbp,%rbp\nje 15d0 \nxor %edi,%edi\njmp 151d \nadd $0x1,%rdi\ncmp %rdi,%rbp\nje 15d0 \ncmp (%rbx,%rdi,4),%edx\njne 1510 \nadd $0x4,%rcx\ncmp %rsi,%rcx\njne 1500 \ntest %rbp,%rbp\nje 156c \nlea (%rbx,%rbp,4),%rsi\nnopl 0x0(%rax)\nmov (%rbx),%ecx\ntest %r13,%r13\nje 15f0 \nxor %edx,%edx\njmp 155d \nnopw 0x0(%rax,%rax,1)\nadd $0x1,%rdx\ncmp %rdx,%r13\nje 15f0 \ncmp (%r12,%rdx,4),%ecx\njne 1550 \nadd $0x4,%rbx\ncmp %rsi,%rbx\njne 1538 \nmov %r9,%r11\nsub $0x1,%r11\nje 1622 \nlea 0x4(%rax),%rdi\nlea (%rax,%r9,4),%r8\nxor %r10d,%r10d\nnopl 0x0(%rax)\nadd $0x1,%r10\ncmp %r10,%r9\njbe 15af \nmov %rdi,%rdx\nnopl 0x0(%rax)\nmov -0x4(%rdi),%ecx\nmov (%rdx),%esi\ncmp %esi,%ecx\njle 15a6 \nmov %esi,-0x4(%rdi)\nmov %ecx,(%rdx)\nadd $0x4,%rdx\ncmp %rdx,%r8\njne 1598 \nadd $0x4,%rdi\ncmp %r10,%r11\njne 1588 \nadd $0x8,%rsp\nmov %r9,%rdx\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopw %cs:0x0(%rax,%rax,1)\nadd $0x4,%rcx\nmov %edx,(%rax,%r9,4)\nadd $0x1,%r9\ncmp %rsi,%rcx\njne 1500 \njmpq 152b \nnopw 0x0(%rax,%rax,1)\nadd $0x4,%rbx\nmov %ecx,(%rax,%r9,4)\nadd $0x1,%r9\ncmp %rsi,%rbx\njne 1538 \njmpq 156c \nxor %r9d,%r9d\nmov $0xffffffffffffffff,%r11\ntest %rbp,%rbp\njne 1530 \njmpq 1579 \nadd $0x8,%rsp\nmov $0x1,%r9d\npop %rbx\nmov %r9,%rdx\npop %rbp\npop %r12\npop %r13\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r13\nmov r13, rdi\nlea rdi, [rsi+rcx]\npush r12\nshl rdi, 2; size\nmov r12, rsi\npush rbp\nmov rbp, rdx\npush rbx\nmov rbx, rcx\nsub rsp, 8\ncall _malloc\nmov r9, rax\ntest r12, r12\njz loc_1561\nmov rcx, r13\nlea rdi, [r13+r12*4+0]\nxor esi, esi\nnop dword ptr [rax]\nloc_1470:\nmov edx, [rcx]\ntest rbx, rbx\njz short loc_14A0\nloc_1477:\nxor eax, eax\njmp short loc_1489\nloc_1480:\nadd rax, 1\ncmp rbx, rax\njz short loc_14A0\nloc_1489:\ncmp edx, [rbp+rax*4+0]\njnz short loc_1480\nadd rcx, 4\ncmp rcx, rdi\njz short loc_14B6\nmov edx, [rcx]\njmp short loc_1477\nloc_14A0:\nadd rcx, 4\nmov [r9+rsi*4], edx\nlea r8, [rsi+1]\ncmp rcx, rdi\njz short loc_14B9\nmov rsi, r8\njmp short loc_1470\nloc_14B6:\nmov r8, rsi\nloc_14B9:\ntest rbx, rbx\njz short loc_1501\nloc_14BE:\nxor ecx, ecx\nloc_14C0:\nmov edx, [rbp+rcx*4+0]\nmov rsi, r8\ntest r12, r12\njz short loc_14F0\nloc_14CC:\nxor eax, eax\njmp short loc_14D9\nloc_14D0:\nadd rax, 1\ncmp r12, rax\njz short loc_14F0\nloc_14D9:\ncmp edx, [r13+rax*4+0]\njnz short loc_14D0\nadd rcx, 1\ncmp rcx, rbx\njnb short loc_1501\nmov edx, [rbp+rcx*4+0]\njmp short loc_14CC\nloc_14F0:\nadd rcx, 1\nmov [r9+rsi*4], edx\nadd r8, 1\ncmp rcx, rbx\njb short loc_14C0\nloc_1501:\ncmp r8, 1\njz short loc_1550\nlea r11, [r8-1]\nloc_150B:\nlea rsi, [r9+4]\nlea rdi, [r9+r8*4]\nxor r10d, r10d\nnop word ptr [rax+rax+00000000h]\nloc_1520:\nadd r10, 1\nmov rax, rsi\ncmp r10, r8\njnb short loc_1547\nnop dword ptr [rax+00h]\nloc_1530:\nmov edx, [rsi-4]\nmov ecx, [rax]\ncmp edx, ecx\njle short loc_153E\nmov [rsi-4], ecx\nmov [rax], edx\nloc_153E:\nadd rax, 4\ncmp rax, rdi\njnz short loc_1530\nloc_1547:\nadd rsi, 4\ncmp r10, r11\njb short loc_1520\nloc_1550:\nadd rsp, 8\nmov rax, r9\nmov rdx, r8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1561:\nxor r8d, r8d\nmov r11, 0FFFFFFFFFFFFFFFFh\ntest rbx, rbx\njnz loc_14BE\njmp short loc_150B", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, __int64 a2, __int64 a3, unsigned __int64 a4)\n{\n _DWORD *v8; // r9\n int *v9; // rcx\n int *v10; // rdi\n unsigned __int64 i; // rsi\n int v12; // edx\n __int64 v13; // rax\n unsigned __int64 v14; // r8\n unsigned __int64 v15; // rcx\n int v16; // edx\n __int64 v17; // rax\n unsigned __int64 v18; // r11\n _DWORD *v19; // rsi\n unsigned __int64 v20; // r10\n _DWORD *v21; // rax\n int v22; // edx\n\n v8 = malloc(4 * (a2 + a4));\n if ( a2 )\n {\n v9 = a1;\n v10 = &a1[a2];\n for ( i = 0LL; ; ++i )\n {\n v12 = *v9;\n if ( a4 )\n break;\nLABEL_9:\n ++v9;\n v8[i] = v12;\n v14 = i + 1;\n if ( v9 == v10 )\n goto LABEL_12;\n }\n while ( 1 )\n {\n v13 = 0LL;\n while ( v12 != *(_DWORD *)(a3 + 4 * v13) )\n {\n if ( a4 == ++v13 )\n goto LABEL_9;\n }\n if ( ++v9 == v10 )\n break;\n v12 = *v9;\n }\n v14 = i;\nLABEL_12:\n if ( !a4 )\n goto LABEL_21;\n }\n else\n {\n v14 = 0LL;\n v18 = -1LL;\n if ( !a4 )\n goto LABEL_23;\n }\n v15 = 0LL;\n while ( 1 )\n {\n v16 = *(_DWORD *)(a3 + 4 * v15);\n if ( a2 )\n break;\nLABEL_20:\n ++v15;\n v8[v14++] = v16;\n if ( v15 >= a4 )\n goto LABEL_21;\n }\n while ( 1 )\n {\n v17 = 0LL;\n while ( v16 != a1[v17] )\n {\n if ( a2 == ++v17 )\n goto LABEL_20;\n }\n if ( ++v15 >= a4 )\n break;\n v16 = *(_DWORD *)(a3 + 4 * v15);\n }\nLABEL_21:\n if ( v14 == 1 )\n return v8;\n v18 = v14 - 1;\nLABEL_23:\n v19 = v8 + 1;\n v20 = 0LL;\n do\n {\n ++v20;\n v21 = v19;\n if ( v20 < v14 )\n {\n do\n {\n v22 = *(v19 - 1);\n if ( v22 > *v21 )\n {\n *(v19 - 1) = *v21;\n *v21 = v22;\n }\n ++v21;\n }\n while ( v21 != &v8[v14] );\n }\n ++v19;\n }\n while ( v20 < v18 );\n return v8;\n}", + "ida_strip_asm": "sub_1430:\nendbr64\npush r13\nmov r13, rdi\nlea rdi, [rsi+rcx]\npush r12\nshl rdi, 2; size\nmov r12, rsi\npush rbp\nmov rbp, rdx\npush rbx\nmov rbx, rcx\nsub rsp, 8\ncall _malloc\nmov r9, rax\ntest r12, r12\njz loc_1561\nmov rcx, r13\nlea rdi, [r13+r12*4+0]\nxor esi, esi\nnop dword ptr [rax]\nloc_1470:\nmov edx, [rcx]\ntest rbx, rbx\njz short loc_14A0\nloc_1477:\nxor eax, eax\njmp short loc_1489\nloc_1480:\nadd rax, 1\ncmp rbx, rax\njz short loc_14A0\nloc_1489:\ncmp edx, [rbp+rax*4+0]\njnz short loc_1480\nadd rcx, 4\ncmp rcx, rdi\njz short loc_14B6\nmov edx, [rcx]\njmp short loc_1477\nloc_14A0:\nadd rcx, 4\nmov [r9+rsi*4], edx\nlea r8, [rsi+1]\ncmp rcx, rdi\njz short loc_14B9\nmov rsi, r8\njmp short loc_1470\nloc_14B6:\nmov r8, rsi\nloc_14B9:\ntest rbx, rbx\njz short loc_1501\nloc_14BE:\nxor ecx, ecx\nloc_14C0:\nmov edx, [rbp+rcx*4+0]\nmov rsi, r8\ntest r12, r12\njz short loc_14F0\nloc_14CC:\nxor eax, eax\njmp short loc_14D9\nloc_14D0:\nadd rax, 1\ncmp r12, rax\njz short loc_14F0\nloc_14D9:\ncmp edx, [r13+rax*4+0]\njnz short loc_14D0\nadd rcx, 1\ncmp rcx, rbx\njnb short loc_1501\nmov edx, [rbp+rcx*4+0]\njmp short loc_14CC\nloc_14F0:\nadd rcx, 1\nmov [r9+rsi*4], edx\nadd r8, 1\ncmp rcx, rbx\njb short loc_14C0\nloc_1501:\ncmp r8, 1\njz short loc_1550\nlea r11, [r8-1]\nloc_150B:\nlea rsi, [r9+4]\nlea rdi, [r9+r8*4]\nxor r10d, r10d\nnop word ptr [rax+rax+00000000h]\nloc_1520:\nadd r10, 1\nmov rax, rsi\ncmp r10, r8\njnb short loc_1547\nnop dword ptr [rax+00h]\nloc_1530:\nmov edx, [rsi-4]\nmov ecx, [rax]\ncmp edx, ecx\njle short loc_153E\nmov [rsi-4], ecx\nmov [rax], edx\nloc_153E:\nadd rax, 4\ncmp rax, rdi\njnz short loc_1530\nloc_1547:\nadd rsi, 4\ncmp r10, r11\njb short loc_1520\nloc_1550:\nadd rsp, 8\nmov rax, r9\nmov rdx, r8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1561:\nxor r8d, r8d\nmov r11, 0FFFFFFFFFFFFFFFFh\ntest rbx, rbx\njnz loc_14BE\njmp short loc_150B", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1430(int *a1, __int64 a2, __int64 a3, unsigned __int64 a4)\n{\n _DWORD *v8; // r9\n int *v9; // rcx\n int *v10; // rdi\n unsigned __int64 i; // rsi\n int v12; // edx\n __int64 v13; // rax\n unsigned __int64 v14; // r8\n unsigned __int64 v15; // rcx\n int v16; // edx\n __int64 v17; // rax\n unsigned __int64 v18; // r11\n _DWORD *v19; // rsi\n unsigned __int64 v20; // r10\n _DWORD *v21; // rax\n int v22; // edx\n\n v8 = malloc(4 * (a2 + a4));\n if ( a2 )\n {\n v9 = a1;\n v10 = &a1[a2];\n for ( i = 0LL; ; ++i )\n {\n v12 = *v9;\n if ( a4 )\n break;\nLABEL_9:\n ++v9;\n v8[i] = v12;\n v14 = i + 1;\n if ( v9 == v10 )\n goto LABEL_12;\n }\n while ( 1 )\n {\n v13 = 0LL;\n while ( v12 != *(_DWORD *)(a3 + 4 * v13) )\n {\n if ( a4 == ++v13 )\n goto LABEL_9;\n }\n if ( ++v9 == v10 )\n break;\n v12 = *v9;\n }\n v14 = i;\nLABEL_12:\n if ( !a4 )\n goto LABEL_21;\n }\n else\n {\n v14 = 0LL;\n v18 = -1LL;\n if ( !a4 )\n goto LABEL_23;\n }\n v15 = 0LL;\n while ( 1 )\n {\n v16 = *(_DWORD *)(a3 + 4 * v15);\n if ( a2 )\n break;\nLABEL_20:\n ++v15;\n v8[v14++] = v16;\n if ( v15 >= a4 )\n goto LABEL_21;\n }\n while ( 1 )\n {\n v17 = 0LL;\n while ( v16 != a1[v17] )\n {\n if ( a2 == ++v17 )\n goto LABEL_20;\n }\n if ( ++v15 >= a4 )\n break;\n v16 = *(_DWORD *)(a3 + 4 * v15);\n }\nLABEL_21:\n if ( v14 == 1 )\n return v8;\n v18 = v14 - 1;\nLABEL_23:\n v19 = v8 + 1;\n v20 = 0LL;\n do\n {\n ++v20;\n v21 = v19;\n if ( v20 < v14 )\n {\n do\n {\n v22 = *(v19 - 1);\n if ( v22 > *v21 )\n {\n *(v19 - 1) = *v21;\n *v21 = v22;\n }\n ++v21;\n }\n while ( v21 != &v8[v14] );\n }\n ++v19;\n }\n while ( v20 < v18 );\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1430(int *a1, long long a2, long long a3, unsigned long long a4) {\n uint32_t *v8;\n int *v9;\n int *v10;\n unsigned long long i;\n int v12;\n long long v13;\n unsigned long long v14;\n unsigned long long v15;\n int v16;\n long long v17;\n unsigned long long v18;\n uint32_t *v19;\n unsigned long long v20;\n uint32_t *v21;\n int v22;\n v8 = malloc(4 * (a2 + a4));\n if (a2) {\n v9 = a1;\n v10 = &a1[a2];\n for (i = 0LL;; ++i) {\n v12 = *v9;\n if (a4) break;\n LABEL_9:\n ++v9;\n v8[i] = v12;\n v14 = i + 1;\n if (v9 == v10) goto LABEL_12;\n }\n while (1) {\n v13 = 0LL;\n while (v12 != *(uint32_t *)(a3 + 4 * v13)) {\n if (a4 == ++v13) goto LABEL_9;\n }\n if (++v9 == v10) break;\n v12 = *v9;\n }\n v14 = i;\n LABEL_12:\n if (!a4) goto LABEL_21;\n } else {\n v14 = 0LL;\n v18 = -1LL;\n if (!a4) goto LABEL_23;\n }\n v15 = 0LL;\n while (1) {\n v16 = *(uint32_t *)(a3 + 4 * v15);\n if (a2) break;\n LABEL_20:\n ++v15;\n v8[v14++] = v16;\n if (v15 >= a4) goto LABEL_21;\n }\n while (1) {\n v17 = 0LL;\n while (v16 != a1[v17]) {\n if (a2 == ++v17) goto LABEL_20;\n }\n if (++v15 >= a4) break;\n v16 = *(uint32_t *)(a3 + 4 * v15);\n }\nLABEL_21:\n if (v14 == 1) return v8;\n v18 = v14 - 1;\nLABEL_23:\n v19 = v8 + 1;\n v20 = 0LL;\n do {\n ++v20;\n v21 = v19;\n if (v20 < v14) {\n do {\n v22 = *(v19 - 1);\n if (v22 > *v21) {\n *(v19 - 1) = *v21;\n *v21 = v22;\n }\n ++v21;\n } while (v21 != &v8[v14]);\n }\n ++v19;\n } while (v20 < v18);\n return v8;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, long long a2, long long a3, unsigned long long a4) {\n uint32_t *v8;\n int *v9;\n int *v10;\n unsigned long long i;\n int v12;\n long long v13;\n unsigned long long v14;\n unsigned long long v15;\n int v16;\n long long v17;\n unsigned long long v18;\n uint32_t *v19;\n unsigned long long v20;\n uint32_t *v21;\n int v22;\n v8 = malloc(4 * (a2 + a4));\n if (a2) {\n v9 = a1;\n v10 = &a1[a2];\n for (i = 0LL;; ++i) {\n v12 = *v9;\n if (a4) break;\n LABEL_9:\n ++v9;\n v8[i] = v12;\n v14 = i + 1;\n if (v9 == v10) goto LABEL_12;\n }\n while (1) {\n v13 = 0LL;\n while (v12 != *(uint32_t *)(a3 + 4 * v13)) {\n if (a4 == ++v13) goto LABEL_9;\n }\n if (++v9 == v10) break;\n v12 = *v9;\n }\n v14 = i;\n LABEL_12:\n if (!a4) goto LABEL_21;\n } else {\n v14 = 0LL;\n v18 = -1LL;\n if (!a4) goto LABEL_23;\n }\n v15 = 0LL;\n while (1) {\n v16 = *(uint32_t *)(a3 + 4 * v15);\n if (a2) break;\n LABEL_20:\n ++v15;\n v8[v14++] = v16;\n if (v15 >= a4) goto LABEL_21;\n }\n while (1) {\n v17 = 0LL;\n while (v16 != a1[v17]) {\n if (a2 == ++v17) goto LABEL_20;\n }\n if (++v15 >= a4) break;\n v16 = *(uint32_t *)(a3 + 4 * v15);\n }\nLABEL_21:\n if (v14 == 1) return v8;\n v18 = v14 - 1;\nLABEL_23:\n v19 = v8 + 1;\n v20 = 0LL;\n do {\n ++v20;\n v21 = v19;\n if (v20 < v14) {\n do {\n v22 = *(v19 - 1);\n if (v22 > *v21) {\n *(v19 - 1) = *v21;\n *v21 = v22;\n }\n ++v21;\n } while (v21 != &v8[v14]);\n }\n ++v19;\n } while (v20 < v18);\n return v8;\n}" + }, + { + "index": 579, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n// Structure to hold the result tuple\n\ntypedef struct {\n\n int *data;\n\n size_t size;\n\n} tuple;\n\n\n\n// Function to check if a value exists in an array\n\nint contains(int *arr, size_t len, int val) {\n\n for (size_t i = 0; i < len; i++) {\n\n if (arr[i] == val)\n\n return 1;\n\n }\n\n return 0;\n\n}\n\n\n\n// Function to find symmetric difference\n\n", + "func": "tuple func0(int *a, size_t a_len, int *b, size_t b_len) {\n int *temp = malloc((a_len + b_len) * sizeof(int));\n size_t count = 0;\n for (size_t i = 0; i < a_len; i++) {\n if (!contains(b, b_len, a[i])) {\n temp[count++] = a[i];\n }\n }\n for (size_t i = 0; i < b_len; i++) {\n if (!contains(a, a_len, b[i])) {\n temp[count++] = b[i];\n }\n }\n for (size_t i = 0; i < count - 1; i++) {\n for (size_t j = i + 1; j < count; j++) {\n if (temp[i] > temp[j]) {\n int swap = temp[i];\n temp[i] = temp[j];\n temp[j] = swap;\n }\n }\n }\n tuple result;\n result.data = temp;\n result.size = count;\n return result;\n}", + "test": "int main() {\n\n // Test 1\n\n int test1_a[] = {3, 4, 5, 6};\n\n int test1_b[] = {5, 7, 4, 10};\n\n int expected1[] = {3, 6, 7, 10};\n\n tuple res1 = func0(test1_a, 4, test1_b, 4);\n\n assert(res1.size == 4);\n\n for (int i = 0; i < 4; i++) {\n\n assert(res1.data[i] == expected1[i]);\n\n }\n\n free(res1.data);\n\n\n\n // Test 2\n\n int test2_a[] = {1, 2, 3, 4};\n\n int test2_b[] = {7, 2, 3, 9};\n\n int expected2[] = {1, 4, 7, 9};\n\n tuple res2 = func0(test2_a, 4, test2_b, 4);\n\n assert(res2.size == 4);\n\n for (int i = 0; i < 4; i++) {\n\n assert(res2.data[i] == expected2[i]);\n\n }\n\n free(res2.data);\n\n\n\n // Test 3\n\n int test3_a[] = {21, 11, 25, 26};\n\n int test3_b[] = {26, 34, 21, 36};\n\n int expected3[] = {11, 25, 34, 36};\n\n tuple res3 = func0(test3_a, 4, test3_b, 4);\n\n assert(res3.size == 4);\n\n for (int i = 0; i < 4; i++) {\n\n assert(res3.data[i] == expected3[i]);\n\n }\n\n free(res3.data);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov %rsi,%r13\npush %r12\nmov %rdi,%r12\nlea (%rsi,%rcx,1),%rdi\npush %rbp\nshl $0x2,%rdi\nmov %rcx,%rbp\npush %rbx\nmov %rdx,%rbx\nsub $0x8,%rsp\ncallq 10b0 \ntest %r13,%r13\nje 155a \nmov %r12,%rcx\nlea (%r12,%r13,4),%rsi\nxor %r9d,%r9d\nnopw 0x0(%rax,%rax,1)\nmov (%rcx),%edx\ntest %rbp,%rbp\nje 1520 \nxor %edi,%edi\njmp 146d \nadd $0x1,%rdi\ncmp %rdi,%rbp\nje 1520 \ncmp (%rbx,%rdi,4),%edx\njne 1460 \nadd $0x4,%rcx\ncmp %rsi,%rcx\njne 1450 \ntest %rbp,%rbp\nje 14bc \nlea (%rbx,%rbp,4),%rsi\nnopl 0x0(%rax)\nmov (%rbx),%ecx\ntest %r13,%r13\nje 1540 \nxor %edx,%edx\njmp 14ad \nnopw 0x0(%rax,%rax,1)\nadd $0x1,%rdx\ncmp %rdx,%r13\nje 1540 \ncmp (%r12,%rdx,4),%ecx\njne 14a0 \nadd $0x4,%rbx\ncmp %rbx,%rsi\njne 1488 \nmov %r9,%r11\nsub $0x1,%r11\nje 1572 \nlea 0x4(%rax),%rdi\nlea (%rax,%r9,4),%r8\nxor %r10d,%r10d\nnopl 0x0(%rax)\nadd $0x1,%r10\ncmp %r10,%r9\njbe 14ff \nmov %rdi,%rdx\nnopl 0x0(%rax)\nmov -0x4(%rdi),%ecx\nmov (%rdx),%esi\ncmp %esi,%ecx\njle 14f6 \nmov %esi,-0x4(%rdi)\nmov %ecx,(%rdx)\nadd $0x4,%rdx\ncmp %rdx,%r8\njne 14e8 \nadd $0x4,%rdi\ncmp %r10,%r11\njne 14d8 \nadd $0x8,%rsp\nmov %r9,%rdx\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopw %cs:0x0(%rax,%rax,1)\nadd $0x4,%rcx\nmov %edx,(%rax,%r9,4)\nadd $0x1,%r9\ncmp %rsi,%rcx\njne 1450 \njmpq 147b \nnopw 0x0(%rax,%rax,1)\nadd $0x4,%rbx\nmov %ecx,(%rax,%r9,4)\nadd $0x1,%r9\ncmp %rbx,%rsi\njne 1488 \njmpq 14bc \nxor %r9d,%r9d\nmov $0xffffffffffffffff,%r11\ntest %rbp,%rbp\njne 1480 \njmpq 14c9 \nadd $0x8,%rsp\nmov $0x1,%r9d\npop %rbx\nmov %r9,%rdx\npop %rbp\npop %r12\npop %r13\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r13\nmov r13, rdi\nlea rdi, [rsi+rcx]\npush r12\nshl rdi, 2; size\nmov r12, rsi\npush rbp\nmov rbp, rdx\npush rbx\nmov rbx, rcx\nsub rsp, 8\ncall _malloc\nmov r9, rax\ntest r12, r12\njz loc_1541\nmov rcx, r13\nlea rdi, [r13+r12*4+0]\nxor esi, esi\nnop dword ptr [rax]\nloc_1450:\nmov edx, [rcx]\ntest rbx, rbx\njz short loc_1480\nloc_1457:\nxor eax, eax\njmp short loc_1469\nloc_1460:\nadd rax, 1\ncmp rbx, rax\njz short loc_1480\nloc_1469:\ncmp edx, [rbp+rax*4+0]\njnz short loc_1460\nadd rcx, 4\ncmp rcx, rdi\njz short loc_1496\nmov edx, [rcx]\njmp short loc_1457\nloc_1480:\nadd rcx, 4\nmov [r9+rsi*4], edx\nlea r8, [rsi+1]\ncmp rcx, rdi\njz short loc_1499\nmov rsi, r8\njmp short loc_1450\nloc_1496:\nmov r8, rsi\nloc_1499:\ntest rbx, rbx\njz short loc_14E1\nloc_149E:\nxor ecx, ecx\nloc_14A0:\nmov edx, [rbp+rcx*4+0]\nmov rsi, r8\ntest r12, r12\njz short loc_14D0\nloc_14AC:\nxor eax, eax\njmp short loc_14B9\nloc_14B0:\nadd rax, 1\ncmp r12, rax\njz short loc_14D0\nloc_14B9:\ncmp edx, [r13+rax*4+0]\njnz short loc_14B0\nadd rcx, 1\ncmp rcx, rbx\njnb short loc_14E1\nmov edx, [rbp+rcx*4+0]\njmp short loc_14AC\nloc_14D0:\nadd rcx, 1\nmov [r9+rsi*4], edx\nadd r8, 1\ncmp rcx, rbx\njb short loc_14A0\nloc_14E1:\ncmp r8, 1\njz short loc_1530\nlea r11, [r8-1]\nloc_14EB:\nlea rsi, [r9+4]\nlea rdi, [r9+r8*4]\nxor r10d, r10d\nnop word ptr [rax+rax+00000000h]\nloc_1500:\nadd r10, 1\nmov rax, rsi\ncmp r10, r8\njnb short loc_1527\nnop dword ptr [rax+00h]\nloc_1510:\nmov edx, [rsi-4]\nmov ecx, [rax]\ncmp edx, ecx\njle short loc_151E\nmov [rsi-4], ecx\nmov [rax], edx\nloc_151E:\nadd rax, 4\ncmp rdi, rax\njnz short loc_1510\nloc_1527:\nadd rsi, 4\ncmp r10, r11\njb short loc_1500\nloc_1530:\nadd rsp, 8\nmov rax, r9\nmov rdx, r8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1541:\nxor r8d, r8d\nmov r11, 0FFFFFFFFFFFFFFFFh\ntest rbx, rbx\njnz loc_149E\njmp short loc_14EB", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, __int64 a2, __int64 a3, unsigned __int64 a4)\n{\n _DWORD *v8; // r9\n int *v9; // rcx\n int *v10; // rdi\n unsigned __int64 i; // rsi\n int v12; // edx\n __int64 v13; // rax\n unsigned __int64 v14; // r8\n unsigned __int64 v15; // rcx\n int v16; // edx\n __int64 v17; // rax\n unsigned __int64 v18; // r11\n _DWORD *v19; // rsi\n unsigned __int64 v20; // r10\n _DWORD *v21; // rax\n int v22; // edx\n\n v8 = malloc(4 * (a2 + a4));\n if ( a2 )\n {\n v9 = a1;\n v10 = &a1[a2];\n for ( i = 0LL; ; ++i )\n {\n v12 = *v9;\n if ( a4 )\n break;\nLABEL_9:\n ++v9;\n v8[i] = v12;\n v14 = i + 1;\n if ( v9 == v10 )\n goto LABEL_12;\n }\n while ( 1 )\n {\n v13 = 0LL;\n while ( v12 != *(_DWORD *)(a3 + 4 * v13) )\n {\n if ( a4 == ++v13 )\n goto LABEL_9;\n }\n if ( ++v9 == v10 )\n break;\n v12 = *v9;\n }\n v14 = i;\nLABEL_12:\n if ( !a4 )\n goto LABEL_21;\n }\n else\n {\n v14 = 0LL;\n v18 = -1LL;\n if ( !a4 )\n goto LABEL_23;\n }\n v15 = 0LL;\n while ( 1 )\n {\n v16 = *(_DWORD *)(a3 + 4 * v15);\n if ( a2 )\n break;\nLABEL_20:\n ++v15;\n v8[v14++] = v16;\n if ( v15 >= a4 )\n goto LABEL_21;\n }\n while ( 1 )\n {\n v17 = 0LL;\n while ( v16 != a1[v17] )\n {\n if ( a2 == ++v17 )\n goto LABEL_20;\n }\n if ( ++v15 >= a4 )\n break;\n v16 = *(_DWORD *)(a3 + 4 * v15);\n }\nLABEL_21:\n if ( v14 == 1 )\n return v8;\n v18 = v14 - 1;\nLABEL_23:\n v19 = v8 + 1;\n v20 = 0LL;\n do\n {\n ++v20;\n v21 = v19;\n if ( v20 < v14 )\n {\n do\n {\n v22 = *(v19 - 1);\n if ( v22 > *v21 )\n {\n *(v19 - 1) = *v21;\n *v21 = v22;\n }\n ++v21;\n }\n while ( &v8[v14] != v21 );\n }\n ++v19;\n }\n while ( v20 < v18 );\n return v8;\n}", + "ida_strip_asm": "sub_1410:\nendbr64\npush r13\nmov r13, rdi\nlea rdi, [rsi+rcx]\npush r12\nshl rdi, 2; size\nmov r12, rsi\npush rbp\nmov rbp, rdx\npush rbx\nmov rbx, rcx\nsub rsp, 8\ncall _malloc\nmov r9, rax\ntest r12, r12\njz loc_1541\nmov rcx, r13\nlea rdi, [r13+r12*4+0]\nxor esi, esi\nnop dword ptr [rax]\nloc_1450:\nmov edx, [rcx]\ntest rbx, rbx\njz short loc_1480\nloc_1457:\nxor eax, eax\njmp short loc_1469\nloc_1460:\nadd rax, 1\ncmp rbx, rax\njz short loc_1480\nloc_1469:\ncmp edx, [rbp+rax*4+0]\njnz short loc_1460\nadd rcx, 4\ncmp rcx, rdi\njz short loc_1496\nmov edx, [rcx]\njmp short loc_1457\nloc_1480:\nadd rcx, 4\nmov [r9+rsi*4], edx\nlea r8, [rsi+1]\ncmp rcx, rdi\njz short loc_1499\nmov rsi, r8\njmp short loc_1450\nloc_1496:\nmov r8, rsi\nloc_1499:\ntest rbx, rbx\njz short loc_14E1\nloc_149E:\nxor ecx, ecx\nloc_14A0:\nmov edx, [rbp+rcx*4+0]\nmov rsi, r8\ntest r12, r12\njz short loc_14D0\nloc_14AC:\nxor eax, eax\njmp short loc_14B9\nloc_14B0:\nadd rax, 1\ncmp r12, rax\njz short loc_14D0\nloc_14B9:\ncmp edx, [r13+rax*4+0]\njnz short loc_14B0\nadd rcx, 1\ncmp rcx, rbx\njnb short loc_14E1\nmov edx, [rbp+rcx*4+0]\njmp short loc_14AC\nloc_14D0:\nadd rcx, 1\nmov [r9+rsi*4], edx\nadd r8, 1\ncmp rcx, rbx\njb short loc_14A0\nloc_14E1:\ncmp r8, 1\njz short loc_1530\nlea r11, [r8-1]\nloc_14EB:\nlea rsi, [r9+4]\nlea rdi, [r9+r8*4]\nxor r10d, r10d\nnop word ptr [rax+rax+00000000h]\nloc_1500:\nadd r10, 1\nmov rax, rsi\ncmp r10, r8\njnb short loc_1527\nnop dword ptr [rax+00h]\nloc_1510:\nmov edx, [rsi-4]\nmov ecx, [rax]\ncmp edx, ecx\njle short loc_151E\nmov [rsi-4], ecx\nmov [rax], edx\nloc_151E:\nadd rax, 4\ncmp rdi, rax\njnz short loc_1510\nloc_1527:\nadd rsi, 4\ncmp r10, r11\njb short loc_1500\nloc_1530:\nadd rsp, 8\nmov rax, r9\nmov rdx, r8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1541:\nxor r8d, r8d\nmov r11, 0FFFFFFFFFFFFFFFFh\ntest rbx, rbx\njnz loc_149E\njmp short loc_14EB", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1410(int *a1, __int64 a2, __int64 a3, unsigned __int64 a4)\n{\n _DWORD *v8; // r9\n int *v9; // rcx\n int *v10; // rdi\n unsigned __int64 i; // rsi\n int v12; // edx\n __int64 v13; // rax\n unsigned __int64 v14; // r8\n unsigned __int64 v15; // rcx\n int v16; // edx\n __int64 v17; // rax\n unsigned __int64 v18; // r11\n _DWORD *v19; // rsi\n unsigned __int64 v20; // r10\n _DWORD *v21; // rax\n int v22; // edx\n\n v8 = malloc(4 * (a2 + a4));\n if ( a2 )\n {\n v9 = a1;\n v10 = &a1[a2];\n for ( i = 0LL; ; ++i )\n {\n v12 = *v9;\n if ( a4 )\n break;\nLABEL_9:\n ++v9;\n v8[i] = v12;\n v14 = i + 1;\n if ( v9 == v10 )\n goto LABEL_12;\n }\n while ( 1 )\n {\n v13 = 0LL;\n while ( v12 != *(_DWORD *)(a3 + 4 * v13) )\n {\n if ( a4 == ++v13 )\n goto LABEL_9;\n }\n if ( ++v9 == v10 )\n break;\n v12 = *v9;\n }\n v14 = i;\nLABEL_12:\n if ( !a4 )\n goto LABEL_21;\n }\n else\n {\n v14 = 0LL;\n v18 = -1LL;\n if ( !a4 )\n goto LABEL_23;\n }\n v15 = 0LL;\n while ( 1 )\n {\n v16 = *(_DWORD *)(a3 + 4 * v15);\n if ( a2 )\n break;\nLABEL_20:\n ++v15;\n v8[v14++] = v16;\n if ( v15 >= a4 )\n goto LABEL_21;\n }\n while ( 1 )\n {\n v17 = 0LL;\n while ( v16 != a1[v17] )\n {\n if ( a2 == ++v17 )\n goto LABEL_20;\n }\n if ( ++v15 >= a4 )\n break;\n v16 = *(_DWORD *)(a3 + 4 * v15);\n }\nLABEL_21:\n if ( v14 == 1 )\n return v8;\n v18 = v14 - 1;\nLABEL_23:\n v19 = v8 + 1;\n v20 = 0LL;\n do\n {\n ++v20;\n v21 = v19;\n if ( v20 < v14 )\n {\n do\n {\n v22 = *(v19 - 1);\n if ( v22 > *v21 )\n {\n *(v19 - 1) = *v21;\n *v21 = v22;\n }\n ++v21;\n }\n while ( &v8[v14] != v21 );\n }\n ++v19;\n }\n while ( v20 < v18 );\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1410(int *a1, long long a2, long long a3, unsigned long long a4) {\n uint32_t *v8;\n int *v9;\n int *v10;\n unsigned long long i;\n int v12;\n long long v13;\n unsigned long long v14;\n unsigned long long v15;\n int v16;\n long long v17;\n unsigned long long v18;\n uint32_t *v19;\n unsigned long long v20;\n uint32_t *v21;\n int v22;\n v8 = malloc(4 * (a2 + a4));\n if (a2) {\n v9 = a1;\n v10 = &a1[a2];\n for (i = 0LL;; ++i) {\n v12 = *v9;\n if (a4) break;\n LABEL_9:\n ++v9;\n v8[i] = v12;\n v14 = i + 1;\n if (v9 == v10) goto LABEL_12;\n }\n while (1) {\n v13 = 0LL;\n while (v12 != *(uint32_t *)(a3 + 4 * v13)) {\n if (a4 == ++v13) goto LABEL_9;\n }\n if (++v9 == v10) break;\n v12 = *v9;\n }\n v14 = i;\n LABEL_12:\n if (!a4) goto LABEL_21;\n } else {\n v14 = 0LL;\n v18 = -1LL;\n if (!a4) goto LABEL_23;\n }\n v15 = 0LL;\n while (1) {\n v16 = *(uint32_t *)(a3 + 4 * v15);\n if (a2) break;\n LABEL_20:\n ++v15;\n v8[v14++] = v16;\n if (v15 >= a4) goto LABEL_21;\n }\n while (1) {\n v17 = 0LL;\n while (v16 != a1[v17]) {\n if (a2 == ++v17) goto LABEL_20;\n }\n if (++v15 >= a4) break;\n v16 = *(uint32_t *)(a3 + 4 * v15);\n }\nLABEL_21:\n if (v14 == 1) return v8;\n v18 = v14 - 1;\nLABEL_23:\n v19 = v8 + 1;\n v20 = 0LL;\n do {\n ++v20;\n v21 = v19;\n if (v20 < v14) {\n do {\n v22 = *(v19 - 1);\n if (v22 > *v21) {\n *(v19 - 1) = *v21;\n *v21 = v22;\n }\n ++v21;\n } while (&v8[v14] != v21);\n }\n ++v19;\n } while (v20 < v18);\n return v8;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, long long a2, long long a3, unsigned long long a4) {\n uint32_t *v8;\n int *v9;\n int *v10;\n unsigned long long i;\n int v12;\n long long v13;\n unsigned long long v14;\n unsigned long long v15;\n int v16;\n long long v17;\n unsigned long long v18;\n uint32_t *v19;\n unsigned long long v20;\n uint32_t *v21;\n int v22;\n v8 = malloc(4 * (a2 + a4));\n if (a2) {\n v9 = a1;\n v10 = &a1[a2];\n for (i = 0LL;; ++i) {\n v12 = *v9;\n if (a4) break;\n LABEL_9:\n ++v9;\n v8[i] = v12;\n v14 = i + 1;\n if (v9 == v10) goto LABEL_12;\n }\n while (1) {\n v13 = 0LL;\n while (v12 != *(uint32_t *)(a3 + 4 * v13)) {\n if (a4 == ++v13) goto LABEL_9;\n }\n if (++v9 == v10) break;\n v12 = *v9;\n }\n v14 = i;\n LABEL_12:\n if (!a4) goto LABEL_21;\n } else {\n v14 = 0LL;\n v18 = -1LL;\n if (!a4) goto LABEL_23;\n }\n v15 = 0LL;\n while (1) {\n v16 = *(uint32_t *)(a3 + 4 * v15);\n if (a2) break;\n LABEL_20:\n ++v15;\n v8[v14++] = v16;\n if (v15 >= a4) goto LABEL_21;\n }\n while (1) {\n v17 = 0LL;\n while (v16 != a1[v17]) {\n if (a2 == ++v17) goto LABEL_20;\n }\n if (++v15 >= a4) break;\n v16 = *(uint32_t *)(a3 + 4 * v15);\n }\nLABEL_21:\n if (v14 == 1) return v8;\n v18 = v14 - 1;\nLABEL_23:\n v19 = v8 + 1;\n v20 = 0LL;\n do {\n ++v20;\n v21 = v19;\n if (v20 < v14) {\n do {\n v22 = *(v19 - 1);\n if (v22 > *v21) {\n *(v19 - 1) = *v21;\n *v21 = v22;\n }\n ++v21;\n } while (&v8[v14] != v21);\n }\n ++v19;\n } while (v20 < v18);\n return v8;\n}" + }, + { + "index": 580, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n// Structure Definitions\n\ntypedef struct Tuple Tuple;\n\n\n\ntypedef struct Element {\n\n int is_tuple;\n\n union {\n\n int value;\n\n Tuple* tuple;\n\n } data;\n\n} Element;\n\n\n\nstruct Tuple {\n\n Element* elements;\n\n int size;\n\n};\n\n\n\n// Function to create an integer element\n\nElement make_int(int value) {\n\n Element e;\n\n e.is_tuple = 0;\n\n e.data.value = value;\n\n return e;\n\n}\n\n\n\n// Function to create a tuple element\n\nElement make_tuple(Element* elements, int size);\n\n\n\n// Function to create a tuple\n\nTuple* create_tuple(Element* elements, int size) {\n\n Tuple* t = malloc(sizeof(Tuple));\n\n t->elements = malloc(sizeof(Element) * size);\n\n for(int i = 0; i < size; i++) {\n\n t->elements[i] = elements[i];\n\n }\n\n t->size = size;\n\n return t;\n\n}\n\n\n\n// Function to create a tuple element\n\nElement make_tuple_element(Element* elements, int size) {\n\n Element e;\n\n e.is_tuple = 1;\n\n e.data.tuple = create_tuple(elements, size);\n\n return e;\n\n}\n\n\n\n// Function to check if a number is even\n\nint is_even(int x) {\n\n return x % 2 == 0;\n\n}\n\n\n\n// Recursive function to extract even elements\n\nTuple* even_ele(Tuple* test_tuple, int (*even_fnc)(int)) {\n\n Tuple* res = create_tuple(NULL, 0);\n\n for(int i = 0; i < test_tuple->size; i++) {\n\n Element ele = test_tuple->elements[i];\n\n if(ele.is_tuple) {\n\n Tuple* filtered = even_ele(ele.data.tuple, even_fnc);\n\n if(filtered->size > 0) {\n\n res->elements = realloc(res->elements, sizeof(Element) * (res->size + 1));\n\n res->elements[res->size] = make_tuple_element(filtered->elements, filtered->size);\n\n res->size++;\n\n }\n\n }\n\n else if(even_fnc(ele.data.value)) {\n\n res->elements = realloc(res->elements, sizeof(Element) * (res->size + 1));\n\n res->elements[res->size] = make_int(ele.data.value);\n\n res->size++;\n\n }\n\n }\n\n return res;\n\n}\n\n\n\n// Function to extract even elements\n\nTuple* extract_even(Tuple* test_tuple) {\n\n return even_ele(test_tuple, is_even);\n\n}\n\n\n\n// Function to compare two tuples\n\n", + "func": "int func0(Tuple* a, Tuple* b) {\n if (a->size != b->size) return 0;\n for (int i = 0; i < a->size; i++) {\n Element ea = a->elements[i];\n Element eb = b->elements[i];\n if (ea.is_tuple != eb.is_tuple) return 0;\n if (ea.is_tuple) {\n if (!func0(ea.data.tuple, eb.data.tuple)) return 0;\n }\n else {\n if (ea.data.value != eb.data.value) return 0;\n }\n }\n return 1;\n}", + "test": "int main() {\n\n // Construct first input tuple: (4, 5, (7, 6, (2, 4)), 6, 8)\n\n Element sub_sub_elements1[] = { make_int(2), make_int(4) };\n\n Element sub_elements1[] = { make_int(7), make_int(6), make_tuple_element(sub_sub_elements1, 2) };\n\n Element input_elements1[] = { make_int(4), make_int(5), make_tuple_element(sub_elements1, 3), make_int(6), make_int(8) };\n\n Tuple* input1 = create_tuple(input_elements1, 5);\n\n\n\n // Construct expected tuple: (4, (6, (2, 4)), 6, 8)\n\n Element expected_sub_sub_elements1[] = { make_int(2), make_int(4) };\n\n Element expected_sub_elements1[] = { make_int(6), make_tuple_element(expected_sub_sub_elements1, 2) };\n\n Element expected_elements1[] = { make_int(4), make_tuple_element(expected_sub_elements1, 2), make_int(6), make_int(8) };\n\n Tuple* expected1 = create_tuple(expected_elements1, 4);\n\n\n\n // Assert first test case\n\n Tuple* result1 = extract_even(input1);\n\n assert(func0(result1, expected1));\n\n\n\n // Construct second input tuple: (5, 6, (8, 7, (4, 8)), 7, 9)\n\n Element sub_sub_elements2[] = { make_int(4), make_int(8) };\n\n Element sub_elements2[] = { make_int(8), make_int(7), make_tuple_element(sub_sub_elements2, 2) };\n\n Element input_elements2[] = { make_int(5), make_int(6), make_tuple_element(sub_elements2, 3), make_int(7), make_int(9) };\n\n Tuple* input2 = create_tuple(input_elements2, 5);\n\n\n\n // Construct expected tuple: (6, (8, (4, 8)))\n\n Element expected_sub_elements2[] = { make_int(8), make_tuple_element(sub_sub_elements2, 2) };\n\n Element expected_elements2[] = { make_int(6), make_tuple_element(expected_sub_elements2, 2) };\n\n Tuple* expected2 = create_tuple(expected_elements2, 2);\n\n\n\n // Assert second test case\n\n Tuple* result2 = extract_even(input2);\n\n assert(func0(result2, expected2));\n\n\n\n // Construct third input tuple: (5, 6, (9, 8, (4, 6)), 8, 10)\n\n Element sub_sub_elements3[] = { make_int(4), make_int(6) };\n\n Element sub_elements3[] = { make_int(9), make_int(8), make_tuple_element(sub_sub_elements3, 2) };\n\n Element input_elements3[] = { make_int(5), make_int(6), make_tuple_element(sub_elements3, 3), make_int(8), make_int(10) };\n\n Tuple* input3 = create_tuple(input_elements3, 5);\n\n\n\n // Construct expected tuple: (6, (8, (4, 6)), 8, 10)\n\n Element expected_sub_elements3[] = { make_int(8), make_tuple_element(sub_sub_elements3, 2) };\n\n Element expected_elements3[] = { make_int(6), make_tuple_element(expected_sub_elements3, 2), make_int(8), make_int(10) };\n\n Tuple* expected3 = create_tuple(expected_elements3, 4);\n\n\n\n // Assert third test case\n\n Tuple* result3 = extract_even(input3);\n\n assert(func0(result3, expected3));\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x40,%rsp\nmov %rdi,-0x38(%rbp)\nmov %rsi,-0x40(%rbp)\nmov -0x38(%rbp),%rax\nmov 0x8(%rax),%edx\nmov -0x40(%rbp),%rax\nmov 0x8(%rax),%eax\ncmp %eax,%edx\nje 14be \nmov $0x0,%eax\njmpq 1570 \nmovl $0x0,-0x24(%rbp)\njmpq 155b \nmov -0x38(%rbp),%rax\nmov (%rax),%rax\nmov -0x24(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x4,%rdx\nadd %rdx,%rax\nmov 0x8(%rax),%rdx\nmov (%rax),%rax\nmov %rax,-0x20(%rbp)\nmov %rdx,-0x18(%rbp)\nmov -0x40(%rbp),%rax\nmov (%rax),%rax\nmov -0x24(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x4,%rdx\nadd %rdx,%rax\nmov 0x8(%rax),%rdx\nmov (%rax),%rax\nmov %rax,-0x10(%rbp)\nmov %rdx,-0x8(%rbp)\nmov -0x20(%rbp),%edx\nmov -0x10(%rbp),%eax\ncmp %eax,%edx\nje 1521 \nmov $0x0,%eax\njmp 1570 \nmov -0x20(%rbp),%eax\ntest %eax,%eax\nje 1546 \nmov -0x8(%rbp),%rdx\nmov -0x18(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 148e \ntest %eax,%eax\njne 1557 \nmov $0x0,%eax\njmp 1570 \nmov -0x18(%rbp),%edx\nmov -0x8(%rbp),%eax\ncmp %eax,%edx\nje 1557 \nmov $0x0,%eax\njmp 1570 \naddl $0x1,-0x24(%rbp)\nmov -0x38(%rbp),%rax\nmov 0x8(%rax),%eax\ncmp %eax,-0x24(%rbp)\njl 14ca \nmov $0x1,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_38], rdi\nmov [rbp+var_40], rsi\nmov rax, [rbp+var_38]\nmov edx, [rax+8]\nmov rax, [rbp+var_40]\nmov eax, [rax+8]\ncmp edx, eax\njz short loc_14D4\nmov eax, 0\njmp locret_1586\nloc_14D4:\nmov [rbp+var_24], 0\njmp loc_1571\nloc_14E0:\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nshl rdx, 4\nadd rax, rdx\nmov rdx, [rax+8]\nmov rax, [rax]\nmov [rbp+var_20], rax\nmov [rbp+var_18], rdx\nmov rax, [rbp+var_40]\nmov rax, [rax]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nshl rdx, 4\nadd rax, rdx\nmov rdx, [rax+8]\nmov rax, [rax]\nmov [rbp+var_10], rax\nmov [rbp+var_8], rdx\nmov edx, dword ptr [rbp+var_20]\nmov eax, dword ptr [rbp+var_10]\ncmp edx, eax\njz short loc_1537\nmov eax, 0\njmp short locret_1586\nloc_1537:\nmov eax, dword ptr [rbp+var_20]\ntest eax, eax\njz short loc_155C\nmov rdx, [rbp+var_8]\nmov rax, [rbp+var_18]\nmov rsi, rdx\nmov rdi, rax\ncall func0\ntest eax, eax\njnz short loc_156D\nmov eax, 0\njmp short locret_1586\nloc_155C:\nmov edx, dword ptr [rbp+var_18]\nmov eax, dword ptr [rbp+var_8]\ncmp edx, eax\njz short loc_156D\nmov eax, 0\njmp short locret_1586\nloc_156D:\nadd [rbp+var_24], 1\nloc_1571:\nmov rax, [rbp+var_38]\nmov eax, [rax+8]\ncmp [rbp+var_24], eax\njl loc_14E0\nmov eax, 1\nlocret_1586:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2)\n{\n __int64 *v3; // rax\n _QWORD *v4; // rax\n int i; // [rsp+1Ch] [rbp-24h]\n __int64 v6; // [rsp+20h] [rbp-20h]\n __int64 v7; // [rsp+28h] [rbp-18h]\n __int64 v8; // [rsp+38h] [rbp-8h]\n\n if ( *(_DWORD *)(a1 + 8) != *(_DWORD *)(a2 + 8) )\n return 0LL;\n for ( i = 0; i < *(_DWORD *)(a1 + 8); ++i )\n {\n v3 = (__int64 *)(16LL * i + *(_QWORD *)a1);\n v6 = *v3;\n v7 = v3[1];\n v4 = (_QWORD *)(16LL * i + *(_QWORD *)a2);\n v8 = v4[1];\n if ( (_DWORD)v6 != (unsigned int)*v4 )\n return 0LL;\n if ( (_DWORD)v6 )\n {\n if ( !(unsigned int)func0(v7, v8) )\n return 0LL;\n }\n else if ( (_DWORD)v7 != (_DWORD)v8 )\n {\n return 0LL;\n }\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_14A4:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_38], rdi\nmov [rbp+var_40], rsi\nmov rax, [rbp+var_38]\nmov edx, [rax+8]\nmov rax, [rbp+var_40]\nmov eax, [rax+8]\ncmp edx, eax\njz short loc_14D4\nmov eax, 0\njmp locret_1586\nloc_14D4:\nmov [rbp+var_24], 0\njmp loc_1571\nloc_14E0:\nmov rax, [rbp+var_38]\nmov rax, [rax]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nshl rdx, 4\nadd rax, rdx\nmov rdx, [rax+8]\nmov rax, [rax]\nmov [rbp+var_20], rax\nmov [rbp+var_18], rdx\nmov rax, [rbp+var_40]\nmov rax, [rax]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nshl rdx, 4\nadd rax, rdx\nmov rdx, [rax+8]\nmov rax, [rax]\nmov [rbp+var_10], rax\nmov [rbp+var_8], rdx\nmov edx, dword ptr [rbp+var_20]\nmov eax, dword ptr [rbp+var_10]\ncmp edx, eax\njz short loc_1537\nmov eax, 0\njmp short locret_1586\nloc_1537:\nmov eax, dword ptr [rbp+var_20]\ntest eax, eax\njz short loc_155C\nmov rdx, [rbp+var_8]\nmov rax, [rbp+var_18]\nmov rsi, rdx\nmov rdi, rax\ncall sub_14A4\ntest eax, eax\njnz short loc_156D\nmov eax, 0\njmp short locret_1586\nloc_155C:\nmov edx, dword ptr [rbp+var_18]\nmov eax, dword ptr [rbp+var_8]\ncmp edx, eax\njz short loc_156D\nmov eax, 0\njmp short locret_1586\nloc_156D:\nadd [rbp+var_24], 1\nloc_1571:\nmov rax, [rbp+var_38]\nmov eax, [rax+8]\ncmp [rbp+var_24], eax\njl loc_14E0\nmov eax, 1\nlocret_1586:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_14A4(__int64 a1, __int64 a2)\n{\n __int64 *v3; // rax\n _QWORD *v4; // rax\n int i; // [rsp+1Ch] [rbp-24h]\n __int64 v6; // [rsp+20h] [rbp-20h]\n __int64 v7; // [rsp+28h] [rbp-18h]\n __int64 v8; // [rsp+38h] [rbp-8h]\n\n if ( *(_DWORD *)(a1 + 8) != *(_DWORD *)(a2 + 8) )\n return 0LL;\n for ( i = 0; i < *(_DWORD *)(a1 + 8); ++i )\n {\n v3 = (__int64 *)(16LL * i + *(_QWORD *)a1);\n v6 = *v3;\n v7 = v3[1];\n v4 = (_QWORD *)(16LL * i + *(_QWORD *)a2);\n v8 = v4[1];\n if ( (_DWORD)v6 != (unsigned int)*v4 )\n return 0LL;\n if ( (_DWORD)v6 )\n {\n if ( !(unsigned int)sub_14A4(v7, v8) )\n return 0LL;\n }\n else if ( (_DWORD)v7 != (_DWORD)v8 )\n {\n return 0LL;\n }\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_14A4(long long a1, long long a2) {\n long long *v3;\n uint64_t *v4;\n int i;\n long long v6;\n long long v7;\n long long v8;\n if (*(uint32_t *)(a1 + 8) != *(uint32_t *)(a2 + 8)) return 0LL;\n for (i = 0; i < *(uint32_t *)(a1 + 8); ++i) {\n v3 = (long long *)(16LL * i + *(uint64_t *)a1);\n v6 = *v3;\n v7 = v3[1];\n v4 = (uint64_t *)(16LL * i + *(uint64_t *)a2);\n v8 = v4[1];\n if ((uint32_t)v6 != (unsigned int)*v4) return 0LL;\n if ((uint32_t)v6) {\n if (!(unsigned int)sub_14A4(v7, v8)) return 0LL;\n } else if ((uint32_t)v7 != (uint32_t)v8) {\n return 0LL;\n }\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2) {\n long long *v3;\n uint64_t *v4;\n int i;\n long long v6;\n long long v7;\n long long v8;\n if (*(uint32_t *)(a1 + 8) != *(uint32_t *)(a2 + 8)) return 0LL;\n for (i = 0; i < *(uint32_t *)(a1 + 8); ++i) {\n v3 = (long long *)(16LL * i + *(uint64_t *)a1);\n v6 = *v3;\n v7 = v3[1];\n v4 = (uint64_t *)(16LL * i + *(uint64_t *)a2);\n v8 = v4[1];\n if ((uint32_t)v6 != (unsigned int)*v4) return 0LL;\n if ((uint32_t)v6) {\n if (!(unsigned int)func0(v7, v8)) return 0LL;\n } else if ((uint32_t)v7 != (uint32_t)v8) {\n return 0LL;\n }\n }\n return 1LL;\n}" + }, + { + "index": 580, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n// Structure Definitions\n\ntypedef struct Tuple Tuple;\n\n\n\ntypedef struct Element {\n\n int is_tuple;\n\n union {\n\n int value;\n\n Tuple* tuple;\n\n } data;\n\n} Element;\n\n\n\nstruct Tuple {\n\n Element* elements;\n\n int size;\n\n};\n\n\n\n// Function to create an integer element\n\nElement make_int(int value) {\n\n Element e;\n\n e.is_tuple = 0;\n\n e.data.value = value;\n\n return e;\n\n}\n\n\n\n// Function to create a tuple element\n\nElement make_tuple(Element* elements, int size);\n\n\n\n// Function to create a tuple\n\nTuple* create_tuple(Element* elements, int size) {\n\n Tuple* t = malloc(sizeof(Tuple));\n\n t->elements = malloc(sizeof(Element) * size);\n\n for(int i = 0; i < size; i++) {\n\n t->elements[i] = elements[i];\n\n }\n\n t->size = size;\n\n return t;\n\n}\n\n\n\n// Function to create a tuple element\n\nElement make_tuple_element(Element* elements, int size) {\n\n Element e;\n\n e.is_tuple = 1;\n\n e.data.tuple = create_tuple(elements, size);\n\n return e;\n\n}\n\n\n\n// Function to check if a number is even\n\nint is_even(int x) {\n\n return x % 2 == 0;\n\n}\n\n\n\n// Recursive function to extract even elements\n\nTuple* even_ele(Tuple* test_tuple, int (*even_fnc)(int)) {\n\n Tuple* res = create_tuple(NULL, 0);\n\n for(int i = 0; i < test_tuple->size; i++) {\n\n Element ele = test_tuple->elements[i];\n\n if(ele.is_tuple) {\n\n Tuple* filtered = even_ele(ele.data.tuple, even_fnc);\n\n if(filtered->size > 0) {\n\n res->elements = realloc(res->elements, sizeof(Element) * (res->size + 1));\n\n res->elements[res->size] = make_tuple_element(filtered->elements, filtered->size);\n\n res->size++;\n\n }\n\n }\n\n else if(even_fnc(ele.data.value)) {\n\n res->elements = realloc(res->elements, sizeof(Element) * (res->size + 1));\n\n res->elements[res->size] = make_int(ele.data.value);\n\n res->size++;\n\n }\n\n }\n\n return res;\n\n}\n\n\n\n// Function to extract even elements\n\nTuple* extract_even(Tuple* test_tuple) {\n\n return even_ele(test_tuple, is_even);\n\n}\n\n\n\n// Function to compare two tuples\n\n", + "func": "int func0(Tuple* a, Tuple* b) {\n if (a->size != b->size) return 0;\n for (int i = 0; i < a->size; i++) {\n Element ea = a->elements[i];\n Element eb = b->elements[i];\n if (ea.is_tuple != eb.is_tuple) return 0;\n if (ea.is_tuple) {\n if (!func0(ea.data.tuple, eb.data.tuple)) return 0;\n }\n else {\n if (ea.data.value != eb.data.value) return 0;\n }\n }\n return 1;\n}", + "test": "int main() {\n\n // Construct first input tuple: (4, 5, (7, 6, (2, 4)), 6, 8)\n\n Element sub_sub_elements1[] = { make_int(2), make_int(4) };\n\n Element sub_elements1[] = { make_int(7), make_int(6), make_tuple_element(sub_sub_elements1, 2) };\n\n Element input_elements1[] = { make_int(4), make_int(5), make_tuple_element(sub_elements1, 3), make_int(6), make_int(8) };\n\n Tuple* input1 = create_tuple(input_elements1, 5);\n\n\n\n // Construct expected tuple: (4, (6, (2, 4)), 6, 8)\n\n Element expected_sub_sub_elements1[] = { make_int(2), make_int(4) };\n\n Element expected_sub_elements1[] = { make_int(6), make_tuple_element(expected_sub_sub_elements1, 2) };\n\n Element expected_elements1[] = { make_int(4), make_tuple_element(expected_sub_elements1, 2), make_int(6), make_int(8) };\n\n Tuple* expected1 = create_tuple(expected_elements1, 4);\n\n\n\n // Assert first test case\n\n Tuple* result1 = extract_even(input1);\n\n assert(func0(result1, expected1));\n\n\n\n // Construct second input tuple: (5, 6, (8, 7, (4, 8)), 7, 9)\n\n Element sub_sub_elements2[] = { make_int(4), make_int(8) };\n\n Element sub_elements2[] = { make_int(8), make_int(7), make_tuple_element(sub_sub_elements2, 2) };\n\n Element input_elements2[] = { make_int(5), make_int(6), make_tuple_element(sub_elements2, 3), make_int(7), make_int(9) };\n\n Tuple* input2 = create_tuple(input_elements2, 5);\n\n\n\n // Construct expected tuple: (6, (8, (4, 8)))\n\n Element expected_sub_elements2[] = { make_int(8), make_tuple_element(sub_sub_elements2, 2) };\n\n Element expected_elements2[] = { make_int(6), make_tuple_element(expected_sub_elements2, 2) };\n\n Tuple* expected2 = create_tuple(expected_elements2, 2);\n\n\n\n // Assert second test case\n\n Tuple* result2 = extract_even(input2);\n\n assert(func0(result2, expected2));\n\n\n\n // Construct third input tuple: (5, 6, (9, 8, (4, 6)), 8, 10)\n\n Element sub_sub_elements3[] = { make_int(4), make_int(6) };\n\n Element sub_elements3[] = { make_int(9), make_int(8), make_tuple_element(sub_sub_elements3, 2) };\n\n Element input_elements3[] = { make_int(5), make_int(6), make_tuple_element(sub_elements3, 3), make_int(8), make_int(10) };\n\n Tuple* input3 = create_tuple(input_elements3, 5);\n\n\n\n // Construct expected tuple: (6, (8, (4, 6)), 8, 10)\n\n Element expected_sub_elements3[] = { make_int(8), make_tuple_element(sub_sub_elements3, 2) };\n\n Element expected_elements3[] = { make_int(6), make_tuple_element(expected_sub_elements3, 2), make_int(8), make_int(10) };\n\n Tuple* expected3 = create_tuple(expected_elements3, 4);\n\n\n\n // Assert third test case\n\n Tuple* result3 = extract_even(input3);\n\n assert(func0(result3, expected3));\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov 0x8(%rdi),%eax\nmov $0x0,%edx\ncmp 0x8(%rsi),%eax\njne 13f1 \npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbp\nmov %rsi,%r12\ntest %eax,%eax\njle 13ea \nlea -0x1(%rax),%r13d\nadd $0x1,%r13\nshl $0x4,%r13\nmov $0x0,%ebx\njmp 13ad \ncallq 1363 \ntest %eax,%eax\nje 13d1 \nadd $0x10,%rbx\ncmp %r13,%rbx\nje 13e3 \nmov %rbx,%rax\nadd 0x0(%rbp),%rax\nmov 0x8(%rax),%rdi\nmov (%rax),%edx\nmov %rbx,%rax\nadd (%r12),%rax\nmov 0x8(%rax),%rsi\ncmp (%rax),%edx\njne 13d1 \ntest %edx,%edx\njne 139b \ncmp %esi,%edi\nje 13a4 \nmov $0x0,%edx\nmov %edx,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nmov $0x1,%edx\njmp 13d6 \nmov $0x1,%edx\njmp 13d6 \nmov %edx,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov r12d, [rdi+8]\nmov eax, 0\ncmp r12d, [rsi+8]\njnz short loc_13C6\ntest r12d, r12d\njle short loc_13D2\nmov rbx, [rdi]\nmov rbp, [rsi]\nmovsxd r12, r12d\nshl r12, 4\nadd r12, rbx\njmp short loc_13AA\nloc_1394:\ncall func0\ntest eax, eax\njz short loc_13C1\nloc_139D:\nadd rbx, 10h\nadd rbp, 10h\ncmp rbx, r12\njz short loc_13CB\nloc_13AA:\nmov rdi, [rbx+8]\nmov eax, [rbx]\nmov rsi, [rbp+8]\ncmp eax, [rbp+0]\njnz short loc_13C1\ntest eax, eax\njnz short loc_1394\ncmp edi, esi\njz short loc_139D\nloc_13C1:\nmov eax, 0\nloc_13C6:\npop rbx\npop rbp\npop r12\nretn\nloc_13CB:\nmov eax, 1\njmp short loc_13C6\nloc_13D2:\nmov eax, 1\njmp short loc_13C6", + "ida_pseudo": "__int64 __fastcall func0(__int64 *a1, __int64 *a2)\n{\n int v2; // r12d\n __int64 result; // rax\n __int64 v4; // rbx\n __int64 v5; // rbp\n __int64 v6; // r12\n\n v2 = *((_DWORD *)a1 + 2);\n result = 0LL;\n if ( v2 == *((_DWORD *)a2 + 2) )\n {\n if ( v2 <= 0 )\n {\n return 1LL;\n }\n else\n {\n v4 = *a1;\n v5 = *a2;\n v6 = *a1 + 16LL * v2;\n do\n {\n if ( *(_DWORD *)v4 != *(_DWORD *)v5 )\n return 0LL;\n if ( *(_DWORD *)v4 )\n {\n if ( !(unsigned int)func0() )\n return 0LL;\n }\n else if ( (unsigned int)*(_QWORD *)(v4 + 8) != (unsigned int)*(_QWORD *)(v5 + 8) )\n {\n return 0LL;\n }\n v4 += 16LL;\n v5 += 16LL;\n }\n while ( v4 != v6 );\n return 1LL;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1366:\nendbr64\npush r12\npush rbp\npush rbx\nmov r12d, [rdi+8]\nmov eax, 0\ncmp r12d, [rsi+8]\njnz short loc_13C6\ntest r12d, r12d\njle short loc_13D2\nmov rbx, [rdi]\nmov rbp, [rsi]\nmovsxd r12, r12d\nshl r12, 4\nadd r12, rbx\njmp short loc_13AA\nloc_1394:\ncall sub_1366\ntest eax, eax\njz short loc_13C1\nloc_139D:\nadd rbx, 10h\nadd rbp, 10h\ncmp rbx, r12\njz short loc_13CB\nloc_13AA:\nmov rdi, [rbx+8]\nmov eax, [rbx]\nmov rsi, [rbp+8]\ncmp eax, [rbp+0]\njnz short loc_13C1\ntest eax, eax\njnz short loc_1394\ncmp edi, esi\njz short loc_139D\nloc_13C1:\nmov eax, 0\nloc_13C6:\npop rbx\npop rbp\npop r12\nretn\nloc_13CB:\nmov eax, 1\njmp short loc_13C6\nloc_13D2:\nmov eax, 1\njmp short loc_13C6", + "ida_strip_pseudo": "__int64 __fastcall sub_1366(__int64 *a1, __int64 *a2)\n{\n int v2; // r12d\n __int64 result; // rax\n __int64 v4; // rbx\n __int64 v5; // rbp\n __int64 v6; // r12\n\n v2 = *((_DWORD *)a1 + 2);\n result = 0LL;\n if ( v2 == *((_DWORD *)a2 + 2) )\n {\n if ( v2 <= 0 )\n {\n return 1LL;\n }\n else\n {\n v4 = *a1;\n v5 = *a2;\n v6 = *a1 + 16LL * v2;\n do\n {\n if ( *(_DWORD *)v4 != *(_DWORD *)v5 )\n return 0LL;\n if ( *(_DWORD *)v4 )\n {\n if ( !(unsigned int)sub_1366() )\n return 0LL;\n }\n else if ( (unsigned int)*(_QWORD *)(v4 + 8) != (unsigned int)*(_QWORD *)(v5 + 8) )\n {\n return 0LL;\n }\n v4 += 16LL;\n v5 += 16LL;\n }\n while ( v4 != v6 );\n return 1LL;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1366(long long *a1, long long *a2) {\n int v2;\n long long result;\n long long v4;\n long long v5;\n long long v6;\n v2 = *((uint32_t *)a1 + 2);\n result = 0LL;\n if (v2 == *((uint32_t *)a2 + 2)) {\n if (v2 <= 0) {\n return 1LL;\n } else {\n v4 = *a1;\n v5 = *a2;\n v6 = *a1 + 16LL * v2;\n do {\n if (*(uint32_t *)v4 != *(uint32_t *)v5) return 0LL;\n if (*(uint32_t *)v4) {\n if (!(unsigned int)sub_1366()) return 0LL;\n } else if ((unsigned int)*(uint64_t *)(v4 + 8) !=\n (unsigned int)*(uint64_t *)(v5 + 8)) {\n return 0LL;\n }\n v4 += 16LL;\n v5 += 16LL;\n } while (v4 != v6);\n return 1LL;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long *a1, long long *a2) {\n int v2;\n long long result;\n long long v4;\n long long v5;\n long long v6;\n v2 = *((uint32_t *)a1 + 2);\n result = 0LL;\n if (v2 == *((uint32_t *)a2 + 2)) {\n if (v2 <= 0) {\n return 1LL;\n } else {\n v4 = *a1;\n v5 = *a2;\n v6 = *a1 + 16LL * v2;\n do {\n if (*(uint32_t *)v4 != *(uint32_t *)v5) return 0LL;\n if (*(uint32_t *)v4) {\n if (!(unsigned int)func0()) return 0LL;\n } else if ((unsigned int)*(uint64_t *)(v4 + 8) !=\n (unsigned int)*(uint64_t *)(v5 + 8)) {\n return 0LL;\n }\n v4 += 16LL;\n v5 += 16LL;\n } while (v4 != v6);\n return 1LL;\n }\n }\n return result;\n}" + }, + { + "index": 580, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n// Structure Definitions\n\ntypedef struct Tuple Tuple;\n\n\n\ntypedef struct Element {\n\n int is_tuple;\n\n union {\n\n int value;\n\n Tuple* tuple;\n\n } data;\n\n} Element;\n\n\n\nstruct Tuple {\n\n Element* elements;\n\n int size;\n\n};\n\n\n\n// Function to create an integer element\n\nElement make_int(int value) {\n\n Element e;\n\n e.is_tuple = 0;\n\n e.data.value = value;\n\n return e;\n\n}\n\n\n\n// Function to create a tuple element\n\nElement make_tuple(Element* elements, int size);\n\n\n\n// Function to create a tuple\n\nTuple* create_tuple(Element* elements, int size) {\n\n Tuple* t = malloc(sizeof(Tuple));\n\n t->elements = malloc(sizeof(Element) * size);\n\n for(int i = 0; i < size; i++) {\n\n t->elements[i] = elements[i];\n\n }\n\n t->size = size;\n\n return t;\n\n}\n\n\n\n// Function to create a tuple element\n\nElement make_tuple_element(Element* elements, int size) {\n\n Element e;\n\n e.is_tuple = 1;\n\n e.data.tuple = create_tuple(elements, size);\n\n return e;\n\n}\n\n\n\n// Function to check if a number is even\n\nint is_even(int x) {\n\n return x % 2 == 0;\n\n}\n\n\n\n// Recursive function to extract even elements\n\nTuple* even_ele(Tuple* test_tuple, int (*even_fnc)(int)) {\n\n Tuple* res = create_tuple(NULL, 0);\n\n for(int i = 0; i < test_tuple->size; i++) {\n\n Element ele = test_tuple->elements[i];\n\n if(ele.is_tuple) {\n\n Tuple* filtered = even_ele(ele.data.tuple, even_fnc);\n\n if(filtered->size > 0) {\n\n res->elements = realloc(res->elements, sizeof(Element) * (res->size + 1));\n\n res->elements[res->size] = make_tuple_element(filtered->elements, filtered->size);\n\n res->size++;\n\n }\n\n }\n\n else if(even_fnc(ele.data.value)) {\n\n res->elements = realloc(res->elements, sizeof(Element) * (res->size + 1));\n\n res->elements[res->size] = make_int(ele.data.value);\n\n res->size++;\n\n }\n\n }\n\n return res;\n\n}\n\n\n\n// Function to extract even elements\n\nTuple* extract_even(Tuple* test_tuple) {\n\n return even_ele(test_tuple, is_even);\n\n}\n\n\n\n// Function to compare two tuples\n\n", + "func": "int func0(Tuple* a, Tuple* b) {\n if (a->size != b->size) return 0;\n for (int i = 0; i < a->size; i++) {\n Element ea = a->elements[i];\n Element eb = b->elements[i];\n if (ea.is_tuple != eb.is_tuple) return 0;\n if (ea.is_tuple) {\n if (!func0(ea.data.tuple, eb.data.tuple)) return 0;\n }\n else {\n if (ea.data.value != eb.data.value) return 0;\n }\n }\n return 1;\n}", + "test": "int main() {\n\n // Construct first input tuple: (4, 5, (7, 6, (2, 4)), 6, 8)\n\n Element sub_sub_elements1[] = { make_int(2), make_int(4) };\n\n Element sub_elements1[] = { make_int(7), make_int(6), make_tuple_element(sub_sub_elements1, 2) };\n\n Element input_elements1[] = { make_int(4), make_int(5), make_tuple_element(sub_elements1, 3), make_int(6), make_int(8) };\n\n Tuple* input1 = create_tuple(input_elements1, 5);\n\n\n\n // Construct expected tuple: (4, (6, (2, 4)), 6, 8)\n\n Element expected_sub_sub_elements1[] = { make_int(2), make_int(4) };\n\n Element expected_sub_elements1[] = { make_int(6), make_tuple_element(expected_sub_sub_elements1, 2) };\n\n Element expected_elements1[] = { make_int(4), make_tuple_element(expected_sub_elements1, 2), make_int(6), make_int(8) };\n\n Tuple* expected1 = create_tuple(expected_elements1, 4);\n\n\n\n // Assert first test case\n\n Tuple* result1 = extract_even(input1);\n\n assert(func0(result1, expected1));\n\n\n\n // Construct second input tuple: (5, 6, (8, 7, (4, 8)), 7, 9)\n\n Element sub_sub_elements2[] = { make_int(4), make_int(8) };\n\n Element sub_elements2[] = { make_int(8), make_int(7), make_tuple_element(sub_sub_elements2, 2) };\n\n Element input_elements2[] = { make_int(5), make_int(6), make_tuple_element(sub_elements2, 3), make_int(7), make_int(9) };\n\n Tuple* input2 = create_tuple(input_elements2, 5);\n\n\n\n // Construct expected tuple: (6, (8, (4, 8)))\n\n Element expected_sub_elements2[] = { make_int(8), make_tuple_element(sub_sub_elements2, 2) };\n\n Element expected_elements2[] = { make_int(6), make_tuple_element(expected_sub_elements2, 2) };\n\n Tuple* expected2 = create_tuple(expected_elements2, 2);\n\n\n\n // Assert second test case\n\n Tuple* result2 = extract_even(input2);\n\n assert(func0(result2, expected2));\n\n\n\n // Construct third input tuple: (5, 6, (9, 8, (4, 6)), 8, 10)\n\n Element sub_sub_elements3[] = { make_int(4), make_int(6) };\n\n Element sub_elements3[] = { make_int(9), make_int(8), make_tuple_element(sub_sub_elements3, 2) };\n\n Element input_elements3[] = { make_int(5), make_int(6), make_tuple_element(sub_elements3, 3), make_int(8), make_int(10) };\n\n Tuple* input3 = create_tuple(input_elements3, 5);\n\n\n\n // Construct expected tuple: (6, (8, (4, 6)), 8, 10)\n\n Element expected_sub_elements3[] = { make_int(8), make_tuple_element(sub_sub_elements3, 2) };\n\n Element expected_elements3[] = { make_int(6), make_tuple_element(expected_sub_elements3, 2), make_int(8), make_int(10) };\n\n Tuple* expected3 = create_tuple(expected_elements3, 4);\n\n\n\n // Assert third test case\n\n Tuple* result3 = extract_even(input3);\n\n assert(func0(result3, expected3));\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov 0x8(%rsi),%eax\ncmp %eax,0x8(%rdi)\njne 19d0 \njmp 19e0 \nxchg %ax,%ax\nxor %eax,%eax\nretq\ndata16 nopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmovsxd r12, dword ptr [rdi+8]\ncmp r12d, [rsi+8]\njz short loc_1A60\nloc_1A52:\npop rbx\nxor eax, eax\npop rbp\npop r12\nretn\nloc_1A60:\ntest r12d, r12d\njle short loc_1AB2\nmov rbx, [rdi]\nshl r12, 4\nmov rbp, [rsi]\nadd r12, rbx\njmp short loc_1A89\nloc_1A78:\ncmp edi, esi\njnz short loc_1A52\nadd rbx, 10h\nadd rbp, 10h\ncmp rbx, r12\njz short loc_1AB2\nloc_1A89:\nmov rdi, [rbx+8]\nmov eax, [rbx]\nmov rsi, [rbp+8]\ncmp eax, [rbp+0]\njnz short loc_1A52\ntest eax, eax\njz short loc_1A78\ncall func0\ntest eax, eax\njz short loc_1A52\nadd rbx, 10h\nadd rbp, 10h\ncmp rbx, r12\njnz short loc_1A89\nloc_1AB2:\npop rbx\nmov eax, 1\npop rbp\npop r12\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 *a1, __int64 *a2)\n{\n __int64 v2; // r12\n __int64 v4; // rbx\n __int64 v5; // rbp\n __int64 v6; // r12\n __int64 v7; // rdi\n __int64 v8; // rsi\n\n v2 = *((int *)a1 + 2);\n if ( (_DWORD)v2 != *((_DWORD *)a2 + 2) )\n return 0LL;\n if ( (int)v2 > 0 )\n {\n v4 = *a1;\n v5 = *a2;\n v6 = *a1 + 16 * v2;\n while ( 1 )\n {\n v7 = *(_QWORD *)(v4 + 8);\n v8 = *(_QWORD *)(v5 + 8);\n if ( *(_DWORD *)v4 != *(_DWORD *)v5 )\n break;\n if ( *(_DWORD *)v4 )\n {\n if ( !(unsigned int)func0(v7, v8) )\n return 0LL;\n v4 += 16LL;\n v5 += 16LL;\n if ( v4 == v6 )\n return 1LL;\n }\n else\n {\n if ( (_DWORD)v7 != (_DWORD)v8 )\n return 0LL;\n v4 += 16LL;\n v5 += 16LL;\n if ( v4 == v6 )\n return 1LL;\n }\n }\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1A40:\nendbr64\npush r12\npush rbp\npush rbx\nmovsxd r12, dword ptr [rdi+8]\ncmp r12d, [rsi+8]\njz short loc_1A60\nloc_1A52:\npop rbx\nxor eax, eax\npop rbp\npop r12\nretn\nloc_1A60:\ntest r12d, r12d\njle short loc_1AB2\nmov rbx, [rdi]\nshl r12, 4\nmov rbp, [rsi]\nadd r12, rbx\njmp short loc_1A89\nloc_1A78:\ncmp edi, esi\njnz short loc_1A52\nadd rbx, 10h\nadd rbp, 10h\ncmp rbx, r12\njz short loc_1AB2\nloc_1A89:\nmov rdi, [rbx+8]\nmov eax, [rbx]\nmov rsi, [rbp+8]\ncmp eax, [rbp+0]\njnz short loc_1A52\ntest eax, eax\njz short loc_1A78\ncall sub_1A40\ntest eax, eax\njz short loc_1A52\nadd rbx, 10h\nadd rbp, 10h\ncmp rbx, r12\njnz short loc_1A89\nloc_1AB2:\npop rbx\nmov eax, 1\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1A40(__int64 *a1, __int64 *a2)\n{\n __int64 v2; // r12\n __int64 v4; // rbx\n __int64 v5; // rbp\n __int64 v6; // r12\n __int64 v7; // rdi\n __int64 v8; // rsi\n\n v2 = *((int *)a1 + 2);\n if ( (_DWORD)v2 != *((_DWORD *)a2 + 2) )\n return 0LL;\n if ( (int)v2 > 0 )\n {\n v4 = *a1;\n v5 = *a2;\n v6 = *a1 + 16 * v2;\n while ( 1 )\n {\n v7 = *(_QWORD *)(v4 + 8);\n v8 = *(_QWORD *)(v5 + 8);\n if ( *(_DWORD *)v4 != *(_DWORD *)v5 )\n break;\n if ( *(_DWORD *)v4 )\n {\n if ( !(unsigned int)sub_1A40(v7, v8) )\n return 0LL;\n v4 += 16LL;\n v5 += 16LL;\n if ( v4 == v6 )\n return 1LL;\n }\n else\n {\n if ( (_DWORD)v7 != (_DWORD)v8 )\n return 0LL;\n v4 += 16LL;\n v5 += 16LL;\n if ( v4 == v6 )\n return 1LL;\n }\n }\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1A40(long long *a1, long long *a2) {\n long long v2;\n long long v4;\n long long v5;\n long long v6;\n long long v7;\n long long v8;\n v2 = *((int *)a1 + 2);\n if ((uint32_t)v2 != *((uint32_t *)a2 + 2)) return 0LL;\n if ((int)v2 > 0) {\n v4 = *a1;\n v5 = *a2;\n v6 = *a1 + 16 * v2;\n while (1) {\n v7 = *(uint64_t *)(v4 + 8);\n v8 = *(uint64_t *)(v5 + 8);\n if (*(uint32_t *)v4 != *(uint32_t *)v5) break;\n if (*(uint32_t *)v4) {\n if (!(unsigned int)sub_1A40(v7, v8)) return 0LL;\n v4 += 16LL;\n v5 += 16LL;\n if (v4 == v6) return 1LL;\n } else {\n if ((uint32_t)v7 != (uint32_t)v8) return 0LL;\n v4 += 16LL;\n v5 += 16LL;\n if (v4 == v6) return 1LL;\n }\n }\n return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long *a1, long long *a2) {\n long long v2;\n long long v4;\n long long v5;\n long long v6;\n long long v7;\n long long v8;\n v2 = *((int *)a1 + 2);\n if ((uint32_t)v2 != *((uint32_t *)a2 + 2)) return 0LL;\n if ((int)v2 > 0) {\n v4 = *a1;\n v5 = *a2;\n v6 = *a1 + 16 * v2;\n while (1) {\n v7 = *(uint64_t *)(v4 + 8);\n v8 = *(uint64_t *)(v5 + 8);\n if (*(uint32_t *)v4 != *(uint32_t *)v5) break;\n if (*(uint32_t *)v4) {\n if (!(unsigned int)func0(v7, v8)) return 0LL;\n v4 += 16LL;\n v5 += 16LL;\n if (v4 == v6) return 1LL;\n } else {\n if ((uint32_t)v7 != (uint32_t)v8) return 0LL;\n v4 += 16LL;\n v5 += 16LL;\n if (v4 == v6) return 1LL;\n }\n }\n return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": 580, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n// Structure Definitions\n\ntypedef struct Tuple Tuple;\n\n\n\ntypedef struct Element {\n\n int is_tuple;\n\n union {\n\n int value;\n\n Tuple* tuple;\n\n } data;\n\n} Element;\n\n\n\nstruct Tuple {\n\n Element* elements;\n\n int size;\n\n};\n\n\n\n// Function to create an integer element\n\nElement make_int(int value) {\n\n Element e;\n\n e.is_tuple = 0;\n\n e.data.value = value;\n\n return e;\n\n}\n\n\n\n// Function to create a tuple element\n\nElement make_tuple(Element* elements, int size);\n\n\n\n// Function to create a tuple\n\nTuple* create_tuple(Element* elements, int size) {\n\n Tuple* t = malloc(sizeof(Tuple));\n\n t->elements = malloc(sizeof(Element) * size);\n\n for(int i = 0; i < size; i++) {\n\n t->elements[i] = elements[i];\n\n }\n\n t->size = size;\n\n return t;\n\n}\n\n\n\n// Function to create a tuple element\n\nElement make_tuple_element(Element* elements, int size) {\n\n Element e;\n\n e.is_tuple = 1;\n\n e.data.tuple = create_tuple(elements, size);\n\n return e;\n\n}\n\n\n\n// Function to check if a number is even\n\nint is_even(int x) {\n\n return x % 2 == 0;\n\n}\n\n\n\n// Recursive function to extract even elements\n\nTuple* even_ele(Tuple* test_tuple, int (*even_fnc)(int)) {\n\n Tuple* res = create_tuple(NULL, 0);\n\n for(int i = 0; i < test_tuple->size; i++) {\n\n Element ele = test_tuple->elements[i];\n\n if(ele.is_tuple) {\n\n Tuple* filtered = even_ele(ele.data.tuple, even_fnc);\n\n if(filtered->size > 0) {\n\n res->elements = realloc(res->elements, sizeof(Element) * (res->size + 1));\n\n res->elements[res->size] = make_tuple_element(filtered->elements, filtered->size);\n\n res->size++;\n\n }\n\n }\n\n else if(even_fnc(ele.data.value)) {\n\n res->elements = realloc(res->elements, sizeof(Element) * (res->size + 1));\n\n res->elements[res->size] = make_int(ele.data.value);\n\n res->size++;\n\n }\n\n }\n\n return res;\n\n}\n\n\n\n// Function to extract even elements\n\nTuple* extract_even(Tuple* test_tuple) {\n\n return even_ele(test_tuple, is_even);\n\n}\n\n\n\n// Function to compare two tuples\n\n", + "func": "int func0(Tuple* a, Tuple* b) {\n if (a->size != b->size) return 0;\n for (int i = 0; i < a->size; i++) {\n Element ea = a->elements[i];\n Element eb = b->elements[i];\n if (ea.is_tuple != eb.is_tuple) return 0;\n if (ea.is_tuple) {\n if (!func0(ea.data.tuple, eb.data.tuple)) return 0;\n }\n else {\n if (ea.data.value != eb.data.value) return 0;\n }\n }\n return 1;\n}", + "test": "int main() {\n\n // Construct first input tuple: (4, 5, (7, 6, (2, 4)), 6, 8)\n\n Element sub_sub_elements1[] = { make_int(2), make_int(4) };\n\n Element sub_elements1[] = { make_int(7), make_int(6), make_tuple_element(sub_sub_elements1, 2) };\n\n Element input_elements1[] = { make_int(4), make_int(5), make_tuple_element(sub_elements1, 3), make_int(6), make_int(8) };\n\n Tuple* input1 = create_tuple(input_elements1, 5);\n\n\n\n // Construct expected tuple: (4, (6, (2, 4)), 6, 8)\n\n Element expected_sub_sub_elements1[] = { make_int(2), make_int(4) };\n\n Element expected_sub_elements1[] = { make_int(6), make_tuple_element(expected_sub_sub_elements1, 2) };\n\n Element expected_elements1[] = { make_int(4), make_tuple_element(expected_sub_elements1, 2), make_int(6), make_int(8) };\n\n Tuple* expected1 = create_tuple(expected_elements1, 4);\n\n\n\n // Assert first test case\n\n Tuple* result1 = extract_even(input1);\n\n assert(func0(result1, expected1));\n\n\n\n // Construct second input tuple: (5, 6, (8, 7, (4, 8)), 7, 9)\n\n Element sub_sub_elements2[] = { make_int(4), make_int(8) };\n\n Element sub_elements2[] = { make_int(8), make_int(7), make_tuple_element(sub_sub_elements2, 2) };\n\n Element input_elements2[] = { make_int(5), make_int(6), make_tuple_element(sub_elements2, 3), make_int(7), make_int(9) };\n\n Tuple* input2 = create_tuple(input_elements2, 5);\n\n\n\n // Construct expected tuple: (6, (8, (4, 8)))\n\n Element expected_sub_elements2[] = { make_int(8), make_tuple_element(sub_sub_elements2, 2) };\n\n Element expected_elements2[] = { make_int(6), make_tuple_element(expected_sub_elements2, 2) };\n\n Tuple* expected2 = create_tuple(expected_elements2, 2);\n\n\n\n // Assert second test case\n\n Tuple* result2 = extract_even(input2);\n\n assert(func0(result2, expected2));\n\n\n\n // Construct third input tuple: (5, 6, (9, 8, (4, 6)), 8, 10)\n\n Element sub_sub_elements3[] = { make_int(4), make_int(6) };\n\n Element sub_elements3[] = { make_int(9), make_int(8), make_tuple_element(sub_sub_elements3, 2) };\n\n Element input_elements3[] = { make_int(5), make_int(6), make_tuple_element(sub_elements3, 3), make_int(8), make_int(10) };\n\n Tuple* input3 = create_tuple(input_elements3, 5);\n\n\n\n // Construct expected tuple: (6, (8, (4, 6)), 8, 10)\n\n Element expected_sub_elements3[] = { make_int(8), make_tuple_element(sub_sub_elements3, 2) };\n\n Element expected_elements3[] = { make_int(6), make_tuple_element(expected_sub_elements3, 2), make_int(8), make_int(10) };\n\n Tuple* expected3 = create_tuple(expected_elements3, 4);\n\n\n\n // Assert third test case\n\n Tuple* result3 = extract_even(input3);\n\n assert(func0(result3, expected3));\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nmov 0x8(%rdi),%eax\nxor %r8d,%r8d\ncmp 0x8(%rsi),%eax\nje 1c88 \nmov %r8d,%eax\nretq\nnopl 0x0(%rax,%rax,1)\ntest %eax,%eax\njle 1d30 \nmov (%rdi),%rdx\nsub $0x1,%eax\nmov (%rsi),%rcx\nshl $0x4,%rax\nlea 0x10(%rdx,%rax,1),%r8\njmp 1cb9 \nnopl 0x0(%rax)\ncmp %esi,%edi\njne 1cd3 \nadd $0x10,%rdx\nadd $0x10,%rcx\ncmp %r8,%rdx\nje 1d30 \nmov 0x8(%rdx),%rdi\nmov (%rdx),%eax\nmov 0x8(%rcx),%rsi\ncmp (%rcx),%eax\njne 1cd3 \ntest %eax,%eax\nje 1ca8 \nmov 0x8(%rsi),%eax\ncmp %eax,0x8(%rdi)\nje 1ce0 \nxor %r8d,%r8d\nmov %r8d,%eax\nretq\nnopw 0x0(%rax,%rax,1)\nsub $0x8,%rsp\ncallq 1800 \ntest %eax,%eax\nje 1d20 \nadd $0x10,%rdx\nadd $0x10,%rcx\ncmp %r8,%rdx\nje 1d40 \nmov 0x8(%rdx),%rdi\nmov (%rdx),%eax\nmov 0x8(%rcx),%rsi\ncmp (%rcx),%eax\njne 1d20 \ntest %eax,%eax\njne 1d18 \ncmp %esi,%edi\nje 1ced \njmp 1d20 \nnopw 0x0(%rax,%rax,1)\nmov 0x8(%rsi),%eax\ncmp %eax,0x8(%rdi)\nje 1ce4 \nxor %r8d,%r8d\nmov %r8d,%eax\nadd $0x8,%rsp\nretq\nnopl 0x0(%rax,%rax,1)\nmov $0x1,%r8d\njmpq 1c7f \nnopl 0x0(%rax,%rax,1)\nmov $0x1,%r8d\njmp 1d23 \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmovsxd rax, dword ptr [rdi+8]\ncmp eax, [rsi+8]\njz short loc_1BA0\nxor eax, eax\nretn\nloc_1BA0:\ntest eax, eax\njle loc_20A0\npush r15\nshl rax, 4\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 0B8h\nmov rbp, [rdi]\nmov r12, [rsi]\nlea r14, [rax+rbp]\nmov rbx, r12\nmov r13, r14\njmp short loc_1BE9\nloc_1BD0:\ncmp ecx, edx\njnz loc_1F88\nloc_1BD8:\nadd rbp, 10h\nadd rbx, 10h\ncmp rbp, r13\njz loc_1FA0\nloc_1BE9:\nmov rcx, [rbp+8]\nmov eax, [rbp+0]\nmov rdx, [rbx+8]\ncmp eax, [rbx]\njnz loc_1F88\ntest eax, eax\njz short loc_1BD0\nmovsxd rax, dword ptr [rcx+8]\ncmp eax, [rdx+8]\njnz loc_1F88\ntest eax, eax\njle short loc_1BD8\nmov r12, [rcx]\nshl rax, 4\nmov r14, [rdx]\nmov rsi, rbp\nlea rdx, [rax+r12]\nmov rax, rbx\nmov rbx, rdx\njmp short loc_1C49\nloc_1C30:\ncmp edi, ecx\njnz loc_1F88\nloc_1C38:\nadd r12, 10h\nadd r14, 10h\ncmp r12, rbx\njz loc_1FB0\nloc_1C49:\nmov rdi, [r12+8]\nmov edx, [r12]\nmov rcx, [r14+8]\ncmp edx, [r14]\njnz loc_1F88\ntest edx, edx\njz short loc_1C30\nmovsxd r8, dword ptr [rdi+8]\ncmp r8d, [rcx+8]\njnz loc_1F88\ntest r8d, r8d\njle short loc_1C38\nmov rbp, [rdi]\nmov rdx, [rcx]\nshl r8, 4\nmov rdi, r13\nmov [rsp+0E8h+var_D8], rbx\nmov r9, rsi\nlea rcx, [r8+rbp]\nmov [rsp+0E8h+var_E0], r14\nmov r8, rax\nmov rbx, rdx\nmov r13, rcx\nmov rax, r12\nmov rcx, rdi\njmp short loc_1CC2\nloc_1CA8:\ncmp r11d, r10d\njnz loc_1F88\nloc_1CB1:\nadd rbp, 10h\nadd rbx, 10h\ncmp rbp, r13\njz loc_1FC0\nloc_1CC2:\nmov r11, [rbp+8]\nmov edx, [rbp+0]\nmov r10, [rbx+8]\ncmp edx, [rbx]\njnz loc_1F88\ntest edx, edx\njz short loc_1CA8\nmovsxd rdx, dword ptr [r11+8]\ncmp edx, [r10+8]\njnz loc_1F88\ntest edx, edx\njle short loc_1CB1\nmov r12, [r11]\nshl rdx, 4\nmov [rsp+0E8h+var_C8], rbx\nmov r15, rax\nmov [rsp+0E8h+var_D0], rbp\nmov r14, [r10]\nmov rax, rcx\nadd rdx, r12\nmov rbx, rdx\njmp short loc_1D29\nloc_1D10:\ncmp ebp, edx\njnz loc_1F88\nloc_1D18:\nadd r12, 10h\nadd r14, 10h\ncmp r12, rbx\njz loc_1FE0\nloc_1D29:\nmov rbp, [r12+8]\nmov esi, [r12]\nmov rdx, [r14+8]\ncmp esi, [r14]\njnz loc_1F88\ntest esi, esi\njz short loc_1D10\nmovsxd rsi, dword ptr [rbp+8]\ncmp esi, [rdx+8]\njnz loc_1F88\ntest esi, esi\njle short loc_1D18\nmov rbp, [rbp+0]\nmov rdx, [rdx]\nshl rsi, 4\nmov [rsp+0E8h+var_C0], r12\nmov rcx, r13\nmov r11, r9\nmov [rsp+0E8h+var_B8], r14\nmov r10, r8\nadd rsi, rbp\nmov [rsp+0E8h+var_B0], rbx\nmov r12, rdx\nmov r9, rax\nmov r13, rsi\njmp short loc_1DA1\nloc_1D88:\ncmp ebx, edx\njnz loc_1F88\nloc_1D90:\nadd rbp, 10h\nadd r12, 10h\ncmp rbp, r13\njz loc_1FF8\nloc_1DA1:\nmov rbx, [rbp+8]\nmov eax, [rbp+0]\nmov rdx, [r12+8]\ncmp eax, [r12]\njnz loc_1F88\ntest eax, eax\njz short loc_1D88\nmovsxd rax, dword ptr [rbx+8]\ncmp eax, [rdx+8]\njnz loc_1F88\ntest eax, eax\njle short loc_1D90\nmov rbx, [rbx]\nshl rax, 4\nmov [rsp+0E8h+var_A0], r12\nmov r8, rcx\nmov [rsp+0E8h+var_A8], rbp\nmov r14, [rdx]\nadd rax, rbx\nmov [rsp+0E8h+var_98], r13\nmov [rsp+0E8h+var_90], r15\nmov r12, rax\njmp short loc_1E11\nloc_1DF8:\ncmp ebp, edi\njnz loc_1F88\nloc_1E00:\nadd rbx, 10h\nadd r14, 10h\ncmp rbx, r12\njz loc_2020\nloc_1E11:\nmov rbp, [rbx+8]\nmov ecx, [rbx]\nmov rdi, [r14+8]\ncmp ecx, [r14]\njnz loc_1F88\ntest ecx, ecx\njz short loc_1DF8\nmovsxd rcx, dword ptr [rbp+8]\ncmp ecx, [rdi+8]\njnz loc_1F88\ntest ecx, ecx\njle short loc_1E00\nmov rbp, [rbp+0]\nmov r15, [rdi]\nshl rcx, 4\nmov [rsp+0E8h+var_80], rbx\nmov [rsp+0E8h+var_88], r14\nadd rcx, rbp\nmov rbx, r15\nmov [rsp+0E8h+var_78], r12\nmov r15, rcx\njmp short loc_1E7A\nloc_1E60:\ncmp r14d, r12d\njnz loc_1F88\nloc_1E69:\nadd rbp, 10h\nadd rbx, 10h\ncmp r15, rbp\njz loc_2040\nloc_1E7A:\nmov r14, [rbp+8]\nmov edx, [rbp+0]\nmov r12, [rbx+8]\ncmp edx, [rbx]\njnz loc_1F88\ntest edx, edx\njz short loc_1E60\nmovsxd rdx, dword ptr [r14+8]\ncmp edx, [r12+8]\njnz loc_1F88\ntest edx, edx\njle short loc_1E69\nmov r14, [r14]\nmov r12, [r12]\nshl rdx, 4\nmov [rsp+0E8h+var_70], r15\nmov [rsp+0E8h+var_68], rbx\nadd rdx, r14\nmov [rsp+0E8h+var_60], rbp\nmov rbx, r12\nmov [rsp+0E8h+var_58], r8\nmov r15, rdx\njmp short loc_1EF9\nloc_1EE0:\ncmp ebp, esi\njnz loc_1F88\nloc_1EE8:\nadd r14, 10h\nadd rbx, 10h\ncmp r15, r14\njz loc_2058\nloc_1EF9:\nmov rbp, [r14+8]\nmov r12d, [r14]\nmov rsi, [rbx+8]\ncmp r12d, [rbx]\njnz short loc_1F88\ntest r12d, r12d\njz short loc_1EE0\nmovsxd r13, dword ptr [rbp+8]\ncmp r13d, [rsi+8]\njnz short loc_1F88\ntest r13d, r13d\njle short loc_1EE8\nmov r12, [rbp+0]\nshl r13, 4\nmov [rsp+0E8h+var_50], rbx\nmov [rsp+0E8h+var_48], r11\nmov rbp, [rsi]\nadd r13, r12\nmov rbx, r12\nmov [rsp+0E8h+var_40], r10\nmov r12, r13\nmov r13, r9\njmp short loc_1F65\nloc_1F50:\ncmp edi, esi\njnz short loc_1F88\nloc_1F54:\nadd rbx, 10h\nadd rbp, 10h\ncmp rbx, r12\njz loc_2080\nloc_1F65:\nmov rdi, [rbx+8]\nmov eax, [rbx]\nmov rsi, [rbp+8]\ncmp eax, [rbp+0]\njnz short loc_1F88\ntest eax, eax\njz short loc_1F50\ncall func0\ntest eax, eax\njnz short loc_1F54\nnop dword ptr [rax+00000000h]\nloc_1F88:\nxor eax, eax\nloc_1F8A:\nadd rsp, 0B8h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1FA0:\nmov eax, 1\njmp short loc_1F8A\nloc_1FB0:\nmov rbp, rsi\nmov rbx, rax\njmp loc_1BD8\nloc_1FC0:\nmov r12, rax\nmov r14, [rsp+0E8h+var_E0]\nmov rbx, [rsp+0E8h+var_D8]\nmov rsi, r9\nmov rax, r8\nmov r13, rcx\njmp loc_1C38\nloc_1FE0:\nmov rcx, rax\nmov rbp, [rsp+0E8h+var_D0]\nmov rbx, [rsp+0E8h+var_C8]\nmov rax, r15\njmp loc_1CB1\nloc_1FF8:\nmov rax, r9\nmov r12, [rsp+0E8h+var_C0]\nmov r14, [rsp+0E8h+var_B8]\nmov r13, rcx\nmov rbx, [rsp+0E8h+var_B0]\nmov r8, r10\nmov r9, r11\njmp loc_1D18\nloc_2020:\nmov rbp, [rsp+0E8h+var_A8]\nmov r12, [rsp+0E8h+var_A0]\nmov rcx, r8\nmov r13, [rsp+0E8h+var_98]\nmov r15, [rsp+0E8h+var_90]\njmp loc_1D90\nloc_2040:\nmov r14, [rsp+0E8h+var_88]\nmov rbx, [rsp+0E8h+var_80]\nmov r12, [rsp+0E8h+var_78]\njmp loc_1E00\nloc_2058:\nmov r15, [rsp+0E8h+var_70]\nmov rbx, [rsp+0E8h+var_68]\nmov rbp, [rsp+0E8h+var_60]\nmov r8, [rsp+0E8h+var_58]\njmp loc_1E69\nloc_2080:\nmov rbx, [rsp+0E8h+var_50]\nmov r11, [rsp+0E8h+var_48]\nmov r9, r13\nmov r10, [rsp+0E8h+var_40]\njmp loc_1EE8\nloc_20A0:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 *a1, __int64 *a2)\n{\n __int64 v2; // rax\n __int64 v4; // rbp\n __int64 v5; // rbx\n __int64 v6; // r13\n __int64 *v7; // rcx\n __int64 *v8; // rdx\n __int64 v9; // rax\n __int64 v10; // r12\n __int64 v11; // r14\n __int64 v12; // rsi\n __int64 v13; // rdx\n __int64 v14; // rax\n __int64 v15; // rbx\n __int64 *v16; // rdi\n __int64 *v17; // rcx\n __int64 v18; // r8\n __int64 v19; // rbp\n __int64 v20; // rdx\n __int64 v21; // rdi\n __int64 v22; // r9\n __int64 v23; // rcx\n __int64 v24; // r8\n __int64 v25; // rbx\n __int64 v26; // r13\n __int64 v27; // rax\n __int64 v28; // rcx\n __int64 *v29; // r11\n __int64 *v30; // r10\n __int64 v31; // rdx\n __int64 v32; // r12\n __int64 v33; // r15\n __int64 v34; // r14\n __int64 v35; // rax\n __int64 v36; // rbx\n __int64 *v37; // rbp\n __int64 *v38; // rdx\n __int64 v39; // rsi\n __int64 v40; // rbp\n __int64 v41; // rcx\n __int64 v42; // r11\n __int64 v43; // r10\n __int64 v44; // r12\n __int64 v45; // r9\n __int64 v46; // r13\n __int64 *v47; // rbx\n __int64 *v48; // rdx\n __int64 v49; // rax\n __int64 v50; // rbx\n __int64 v51; // r8\n __int64 v52; // r14\n __int64 v53; // r12\n __int64 *v54; // rbp\n __int64 *v55; // rdi\n __int64 v56; // rcx\n __int64 v57; // rbp\n __int64 v58; // rbx\n __int64 v59; // r15\n __int64 *v60; // r14\n __int64 *v61; // r12\n __int64 v62; // rdx\n __int64 v63; // r14\n __int64 v64; // rbx\n __int64 v65; // r15\n __int64 *v66; // rbp\n __int64 *v67; // rsi\n __int64 v68; // r13\n __int64 v69; // r12\n __int64 v70; // rbp\n __int64 v71; // rbx\n __int64 v72; // r12\n __int64 v73; // r13\n __int64 v74; // rdi\n __int64 v75; // rsi\n __int64 v76; // [rsp+0h] [rbp-E0h]\n __int64 v77; // [rsp+8h] [rbp-D8h]\n __int64 v78; // [rsp+10h] [rbp-D0h]\n __int64 v79; // [rsp+18h] [rbp-C8h]\n __int64 v80; // [rsp+20h] [rbp-C0h]\n __int64 v81; // [rsp+28h] [rbp-B8h]\n __int64 v82; // [rsp+30h] [rbp-B0h]\n __int64 v83; // [rsp+38h] [rbp-A8h]\n __int64 v84; // [rsp+40h] [rbp-A0h]\n __int64 v85; // [rsp+48h] [rbp-98h]\n __int64 v86; // [rsp+50h] [rbp-90h]\n __int64 v87; // [rsp+58h] [rbp-88h]\n __int64 v88; // [rsp+60h] [rbp-80h]\n __int64 v89; // [rsp+68h] [rbp-78h]\n __int64 v90; // [rsp+70h] [rbp-70h]\n __int64 v91; // [rsp+78h] [rbp-68h]\n __int64 v92; // [rsp+80h] [rbp-60h]\n __int64 v93; // [rsp+88h] [rbp-58h]\n __int64 v94; // [rsp+90h] [rbp-50h]\n __int64 v95; // [rsp+98h] [rbp-48h]\n __int64 v96; // [rsp+A0h] [rbp-40h]\n\n v2 = *((int *)a1 + 2);\n if ( (_DWORD)v2 != *((_DWORD *)a2 + 2) )\n return 0LL;\n if ( (int)v2 <= 0 )\n return 1LL;\n v4 = *a1;\n v5 = *a2;\n v6 = 16 * v2 + *a1;\n do\n {\n v7 = *(__int64 **)(v4 + 8);\n v8 = *(__int64 **)(v5 + 8);\n if ( *(_DWORD *)v4 != *(_DWORD *)v5 )\n return 0LL;\n if ( *(_DWORD *)v4 )\n {\n v9 = *((int *)v7 + 2);\n if ( (_DWORD)v9 != *((_DWORD *)v8 + 2) )\n return 0LL;\n if ( (int)v9 > 0 )\n {\n v10 = *v7;\n v11 = *v8;\n v12 = v4;\n v13 = 16 * v9 + *v7;\n v14 = v5;\n v15 = v13;\n while ( 1 )\n {\n v16 = *(__int64 **)(v10 + 8);\n v17 = *(__int64 **)(v11 + 8);\n if ( *(_DWORD *)v10 != *(_DWORD *)v11 )\n return 0LL;\n if ( *(_DWORD *)v10 )\n {\n v18 = *((int *)v16 + 2);\n if ( (_DWORD)v18 != *((_DWORD *)v17 + 2) )\n return 0LL;\n if ( (int)v18 > 0 )\n {\n v19 = *v16;\n v20 = *v17;\n v21 = v6;\n v77 = v15;\n v22 = v12;\n v23 = 16 * v18 + v19;\n v76 = v11;\n v24 = v14;\n v25 = v20;\n v26 = v23;\n v27 = v10;\n v28 = v21;\n while ( 1 )\n {\n v29 = *(__int64 **)(v19 + 8);\n v30 = *(__int64 **)(v25 + 8);\n if ( *(_DWORD *)v19 != *(_DWORD *)v25 )\n return 0LL;\n if ( *(_DWORD *)v19 )\n {\n v31 = *((int *)v29 + 2);\n if ( (_DWORD)v31 != *((_DWORD *)v30 + 2) )\n return 0LL;\n if ( (int)v31 > 0 )\n {\n v32 = *v29;\n v79 = v25;\n v33 = v27;\n v78 = v19;\n v34 = *v30;\n v35 = v28;\n v36 = *v29 + 16 * v31;\n while ( 1 )\n {\n v37 = *(__int64 **)(v32 + 8);\n v38 = *(__int64 **)(v34 + 8);\n if ( *(_DWORD *)v32 != *(_DWORD *)v34 )\n return 0LL;\n if ( *(_DWORD *)v32 )\n {\n v39 = *((int *)v37 + 2);\n if ( (_DWORD)v39 != *((_DWORD *)v38 + 2) )\n return 0LL;\n if ( (int)v39 > 0 )\n {\n v40 = *v37;\n v80 = v32;\n v41 = v26;\n v42 = v22;\n v81 = v34;\n v43 = v24;\n v82 = v36;\n v44 = *v38;\n v45 = v35;\n v46 = v40 + 16 * v39;\n while ( 1 )\n {\n v47 = *(__int64 **)(v40 + 8);\n v48 = *(__int64 **)(v44 + 8);\n if ( *(_DWORD *)v40 != *(_DWORD *)v44 )\n return 0LL;\n if ( *(_DWORD *)v40 )\n {\n v49 = *((int *)v47 + 2);\n if ( (_DWORD)v49 != *((_DWORD *)v48 + 2) )\n return 0LL;\n if ( (int)v49 > 0 )\n {\n v50 = *v47;\n v84 = v44;\n v51 = v41;\n v83 = v40;\n v52 = *v48;\n v85 = v46;\n v86 = v33;\n v53 = v50 + 16 * v49;\n while ( 1 )\n {\n v54 = *(__int64 **)(v50 + 8);\n v55 = *(__int64 **)(v52 + 8);\n if ( *(_DWORD *)v50 != *(_DWORD *)v52 )\n return 0LL;\n if ( *(_DWORD *)v50 )\n {\n v56 = *((int *)v54 + 2);\n if ( (_DWORD)v56 != *((_DWORD *)v55 + 2) )\n return 0LL;\n if ( (int)v56 > 0 )\n {\n v57 = *v54;\n v88 = v50;\n v87 = v52;\n v58 = *v55;\n v89 = v53;\n v59 = v57 + 16 * v56;\n while ( 1 )\n {\n v60 = *(__int64 **)(v57 + 8);\n v61 = *(__int64 **)(v58 + 8);\n if ( *(_DWORD *)v57 != *(_DWORD *)v58 )\n return 0LL;\n if ( *(_DWORD *)v57 )\n {\n v62 = *((int *)v60 + 2);\n if ( (_DWORD)v62 != *((_DWORD *)v61 + 2) )\n return 0LL;\n if ( (int)v62 > 0 )\n {\n v63 = *v60;\n v90 = v59;\n v91 = v58;\n v92 = v57;\n v64 = *v61;\n v93 = v51;\n v65 = v63 + 16 * v62;\n while ( 1 )\n {\n v66 = *(__int64 **)(v63 + 8);\n v67 = *(__int64 **)(v64 + 8);\n if ( *(_DWORD *)v63 != *(_DWORD *)v64 )\n return 0LL;\n if ( *(_DWORD *)v63 )\n {\n v68 = *((int *)v66 + 2);\n if ( (_DWORD)v68 != *((_DWORD *)v67 + 2) )\n return 0LL;\n if ( (int)v68 > 0 )\n {\n v69 = *v66;\n v94 = v64;\n v95 = v42;\n v70 = *v67;\n v71 = v69;\n v96 = v43;\n v72 = v69 + 16 * v68;\n v73 = v45;\n while ( 1 )\n {\n v74 = *(_QWORD *)(v71 + 8);\n v75 = *(_QWORD *)(v70 + 8);\n if ( *(_DWORD *)v71 != *(_DWORD *)v70 )\n return 0LL;\n if ( *(_DWORD *)v71 )\n {\n if ( !(unsigned int)func0(v74, v75) )\n return 0LL;\n }\n else if ( (_DWORD)v74 != (_DWORD)v75 )\n {\n return 0LL;\n }\n v71 += 16LL;\n v70 += 16LL;\n if ( v71 == v72 )\n {\n v64 = v94;\n v42 = v95;\n v45 = v73;\n v43 = v96;\n break;\n }\n }\n }\n }\n else if ( (_DWORD)v66 != (_DWORD)v67 )\n {\n return 0LL;\n }\n v63 += 16LL;\n v64 += 16LL;\n if ( v65 == v63 )\n {\n v59 = v90;\n v58 = v91;\n v57 = v92;\n v51 = v93;\n break;\n }\n }\n }\n }\n else if ( (_DWORD)v60 != (_DWORD)v61 )\n {\n return 0LL;\n }\n v57 += 16LL;\n v58 += 16LL;\n if ( v59 == v57 )\n {\n v52 = v87;\n v50 = v88;\n v53 = v89;\n break;\n }\n }\n }\n }\n else if ( (_DWORD)v54 != (_DWORD)v55 )\n {\n return 0LL;\n }\n v50 += 16LL;\n v52 += 16LL;\n if ( v50 == v53 )\n {\n v40 = v83;\n v44 = v84;\n v41 = v51;\n v46 = v85;\n v33 = v86;\n break;\n }\n }\n }\n }\n else if ( (_DWORD)v47 != (_DWORD)v48 )\n {\n return 0LL;\n }\n v40 += 16LL;\n v44 += 16LL;\n if ( v40 == v46 )\n {\n v35 = v45;\n v32 = v80;\n v34 = v81;\n v26 = v41;\n v36 = v82;\n v24 = v43;\n v22 = v42;\n break;\n }\n }\n }\n }\n else if ( (_DWORD)v37 != (_DWORD)v38 )\n {\n return 0LL;\n }\n v32 += 16LL;\n v34 += 16LL;\n if ( v32 == v36 )\n {\n v28 = v35;\n v19 = v78;\n v25 = v79;\n v27 = v33;\n break;\n }\n }\n }\n }\n else if ( (_DWORD)v29 != (_DWORD)v30 )\n {\n return 0LL;\n }\n v19 += 16LL;\n v25 += 16LL;\n if ( v19 == v26 )\n {\n v10 = v27;\n v11 = v76;\n v15 = v77;\n v12 = v22;\n v14 = v24;\n v6 = v28;\n break;\n }\n }\n }\n }\n else if ( (_DWORD)v16 != (_DWORD)v17 )\n {\n return 0LL;\n }\n v10 += 16LL;\n v11 += 16LL;\n if ( v10 == v15 )\n {\n v4 = v12;\n v5 = v14;\n break;\n }\n }\n }\n }\n else if ( (_DWORD)v7 != (_DWORD)v8 )\n {\n return 0LL;\n }\n v4 += 16LL;\n v5 += 16LL;\n }\n while ( v4 != v6 );\n return 1LL;\n}", + "ida_strip_asm": "sub_1B90:\nendbr64\nmovsxd rax, dword ptr [rdi+8]\ncmp eax, [rsi+8]\njz short loc_1BA0\nxor eax, eax\nretn\nloc_1BA0:\ntest eax, eax\njle loc_20A0\npush r15\nshl rax, 4\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 0B8h\nmov rbp, [rdi]\nmov r12, [rsi]\nlea r14, [rax+rbp]\nmov rbx, r12\nmov r13, r14\njmp short loc_1BE9\nloc_1BD0:\ncmp ecx, edx\njnz loc_1F88\nloc_1BD8:\nadd rbp, 10h\nadd rbx, 10h\ncmp rbp, r13\njz loc_1FA0\nloc_1BE9:\nmov rcx, [rbp+8]\nmov eax, [rbp+0]\nmov rdx, [rbx+8]\ncmp eax, [rbx]\njnz loc_1F88\ntest eax, eax\njz short loc_1BD0\nmovsxd rax, dword ptr [rcx+8]\ncmp eax, [rdx+8]\njnz loc_1F88\ntest eax, eax\njle short loc_1BD8\nmov r12, [rcx]\nshl rax, 4\nmov r14, [rdx]\nmov rsi, rbp\nlea rdx, [rax+r12]\nmov rax, rbx\nmov rbx, rdx\njmp short loc_1C49\nloc_1C30:\ncmp edi, ecx\njnz loc_1F88\nloc_1C38:\nadd r12, 10h\nadd r14, 10h\ncmp r12, rbx\njz loc_1FB0\nloc_1C49:\nmov rdi, [r12+8]\nmov edx, [r12]\nmov rcx, [r14+8]\ncmp edx, [r14]\njnz loc_1F88\ntest edx, edx\njz short loc_1C30\nmovsxd r8, dword ptr [rdi+8]\ncmp r8d, [rcx+8]\njnz loc_1F88\ntest r8d, r8d\njle short loc_1C38\nmov rbp, [rdi]\nmov rdx, [rcx]\nshl r8, 4\nmov rdi, r13\nmov [rsp+0E8h+var_D8], rbx\nmov r9, rsi\nlea rcx, [r8+rbp]\nmov [rsp+0E8h+var_E0], r14\nmov r8, rax\nmov rbx, rdx\nmov r13, rcx\nmov rax, r12\nmov rcx, rdi\njmp short loc_1CC2\nloc_1CA8:\ncmp r11d, r10d\njnz loc_1F88\nloc_1CB1:\nadd rbp, 10h\nadd rbx, 10h\ncmp rbp, r13\njz loc_1FC0\nloc_1CC2:\nmov r11, [rbp+8]\nmov edx, [rbp+0]\nmov r10, [rbx+8]\ncmp edx, [rbx]\njnz loc_1F88\ntest edx, edx\njz short loc_1CA8\nmovsxd rdx, dword ptr [r11+8]\ncmp edx, [r10+8]\njnz loc_1F88\ntest edx, edx\njle short loc_1CB1\nmov r12, [r11]\nshl rdx, 4\nmov [rsp+0E8h+var_C8], rbx\nmov r15, rax\nmov [rsp+0E8h+var_D0], rbp\nmov r14, [r10]\nmov rax, rcx\nadd rdx, r12\nmov rbx, rdx\njmp short loc_1D29\nloc_1D10:\ncmp ebp, edx\njnz loc_1F88\nloc_1D18:\nadd r12, 10h\nadd r14, 10h\ncmp r12, rbx\njz loc_1FE0\nloc_1D29:\nmov rbp, [r12+8]\nmov esi, [r12]\nmov rdx, [r14+8]\ncmp esi, [r14]\njnz loc_1F88\ntest esi, esi\njz short loc_1D10\nmovsxd rsi, dword ptr [rbp+8]\ncmp esi, [rdx+8]\njnz loc_1F88\ntest esi, esi\njle short loc_1D18\nmov rbp, [rbp+0]\nmov rdx, [rdx]\nshl rsi, 4\nmov [rsp+0E8h+var_C0], r12\nmov rcx, r13\nmov r11, r9\nmov [rsp+0E8h+var_B8], r14\nmov r10, r8\nadd rsi, rbp\nmov [rsp+0E8h+var_B0], rbx\nmov r12, rdx\nmov r9, rax\nmov r13, rsi\njmp short loc_1DA1\nloc_1D88:\ncmp ebx, edx\njnz loc_1F88\nloc_1D90:\nadd rbp, 10h\nadd r12, 10h\ncmp rbp, r13\njz loc_1FF8\nloc_1DA1:\nmov rbx, [rbp+8]\nmov eax, [rbp+0]\nmov rdx, [r12+8]\ncmp eax, [r12]\njnz loc_1F88\ntest eax, eax\njz short loc_1D88\nmovsxd rax, dword ptr [rbx+8]\ncmp eax, [rdx+8]\njnz loc_1F88\ntest eax, eax\njle short loc_1D90\nmov rbx, [rbx]\nshl rax, 4\nmov [rsp+0E8h+var_A0], r12\nmov r8, rcx\nmov [rsp+0E8h+var_A8], rbp\nmov r14, [rdx]\nadd rax, rbx\nmov [rsp+0E8h+var_98], r13\nmov [rsp+0E8h+var_90], r15\nmov r12, rax\njmp short loc_1E11\nloc_1DF8:\ncmp ebp, edi\njnz loc_1F88\nloc_1E00:\nadd rbx, 10h\nadd r14, 10h\ncmp rbx, r12\njz loc_2020\nloc_1E11:\nmov rbp, [rbx+8]\nmov ecx, [rbx]\nmov rdi, [r14+8]\ncmp ecx, [r14]\njnz loc_1F88\ntest ecx, ecx\njz short loc_1DF8\nmovsxd rcx, dword ptr [rbp+8]\ncmp ecx, [rdi+8]\njnz loc_1F88\ntest ecx, ecx\njle short loc_1E00\nmov rbp, [rbp+0]\nmov r15, [rdi]\nshl rcx, 4\nmov [rsp+0E8h+var_80], rbx\nmov [rsp+0E8h+var_88], r14\nadd rcx, rbp\nmov rbx, r15\nmov [rsp+0E8h+var_78], r12\nmov r15, rcx\njmp short loc_1E7A\nloc_1E60:\ncmp r14d, r12d\njnz loc_1F88\nloc_1E69:\nadd rbp, 10h\nadd rbx, 10h\ncmp r15, rbp\njz loc_2040\nloc_1E7A:\nmov r14, [rbp+8]\nmov edx, [rbp+0]\nmov r12, [rbx+8]\ncmp edx, [rbx]\njnz loc_1F88\ntest edx, edx\njz short loc_1E60\nmovsxd rdx, dword ptr [r14+8]\ncmp edx, [r12+8]\njnz loc_1F88\ntest edx, edx\njle short loc_1E69\nmov r14, [r14]\nmov r12, [r12]\nshl rdx, 4\nmov [rsp+0E8h+var_70], r15\nmov [rsp+0E8h+var_68], rbx\nadd rdx, r14\nmov [rsp+0E8h+var_60], rbp\nmov rbx, r12\nmov [rsp+0E8h+var_58], r8\nmov r15, rdx\njmp short loc_1EF9\nloc_1EE0:\ncmp ebp, esi\njnz loc_1F88\nloc_1EE8:\nadd r14, 10h\nadd rbx, 10h\ncmp r15, r14\njz loc_2058\nloc_1EF9:\nmov rbp, [r14+8]\nmov r12d, [r14]\nmov rsi, [rbx+8]\ncmp r12d, [rbx]\njnz short loc_1F88\ntest r12d, r12d\njz short loc_1EE0\nmovsxd r13, dword ptr [rbp+8]\ncmp r13d, [rsi+8]\njnz short loc_1F88\ntest r13d, r13d\njle short loc_1EE8\nmov r12, [rbp+0]\nshl r13, 4\nmov [rsp+0E8h+var_50], rbx\nmov [rsp+0E8h+var_48], r11\nmov rbp, [rsi]\nadd r13, r12\nmov rbx, r12\nmov [rsp+0E8h+var_40], r10\nmov r12, r13\nmov r13, r9\njmp short loc_1F65\nloc_1F50:\ncmp edi, esi\njnz short loc_1F88\nloc_1F54:\nadd rbx, 10h\nadd rbp, 10h\ncmp rbx, r12\njz loc_2080\nloc_1F65:\nmov rdi, [rbx+8]\nmov eax, [rbx]\nmov rsi, [rbp+8]\ncmp eax, [rbp+0]\njnz short loc_1F88\ntest eax, eax\njz short loc_1F50\ncall sub_1B90\ntest eax, eax\njnz short loc_1F54\nnop dword ptr [rax+00000000h]\nloc_1F88:\nxor eax, eax\nloc_1F8A:\nadd rsp, 0B8h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1FA0:\nmov eax, 1\njmp short loc_1F8A\nloc_1FB0:\nmov rbp, rsi\nmov rbx, rax\njmp loc_1BD8\nloc_1FC0:\nmov r12, rax\nmov r14, [rsp+0E8h+var_E0]\nmov rbx, [rsp+0E8h+var_D8]\nmov rsi, r9\nmov rax, r8\nmov r13, rcx\njmp loc_1C38\nloc_1FE0:\nmov rcx, rax\nmov rbp, [rsp+0E8h+var_D0]\nmov rbx, [rsp+0E8h+var_C8]\nmov rax, r15\njmp loc_1CB1\nloc_1FF8:\nmov rax, r9\nmov r12, [rsp+0E8h+var_C0]\nmov r14, [rsp+0E8h+var_B8]\nmov r13, rcx\nmov rbx, [rsp+0E8h+var_B0]\nmov r8, r10\nmov r9, r11\njmp loc_1D18\nloc_2020:\nmov rbp, [rsp+0E8h+var_A8]\nmov r12, [rsp+0E8h+var_A0]\nmov rcx, r8\nmov r13, [rsp+0E8h+var_98]\nmov r15, [rsp+0E8h+var_90]\njmp loc_1D90\nloc_2040:\nmov r14, [rsp+0E8h+var_88]\nmov rbx, [rsp+0E8h+var_80]\nmov r12, [rsp+0E8h+var_78]\njmp loc_1E00\nloc_2058:\nmov r15, [rsp+0E8h+var_70]\nmov rbx, [rsp+0E8h+var_68]\nmov rbp, [rsp+0E8h+var_60]\nmov r8, [rsp+0E8h+var_58]\njmp loc_1E69\nloc_2080:\nmov rbx, [rsp+0E8h+var_50]\nmov r11, [rsp+0E8h+var_48]\nmov r9, r13\nmov r10, [rsp+0E8h+var_40]\njmp loc_1EE8\nloc_20A0:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1B90(__int64 *a1, __int64 *a2)\n{\n __int64 v2; // rax\n __int64 v4; // rbp\n __int64 v5; // rbx\n __int64 v6; // r13\n __int64 *v7; // rcx\n __int64 *v8; // rdx\n __int64 v9; // rax\n __int64 v10; // r12\n __int64 v11; // r14\n __int64 v12; // rsi\n __int64 v13; // rdx\n __int64 v14; // rax\n __int64 v15; // rbx\n __int64 *v16; // rdi\n __int64 *v17; // rcx\n __int64 v18; // r8\n __int64 v19; // rbp\n __int64 v20; // rdx\n __int64 v21; // rdi\n __int64 v22; // r9\n __int64 v23; // rcx\n __int64 v24; // r8\n __int64 v25; // rbx\n __int64 v26; // r13\n __int64 v27; // rax\n __int64 v28; // rcx\n __int64 *v29; // r11\n __int64 *v30; // r10\n __int64 v31; // rdx\n __int64 v32; // r12\n __int64 v33; // r15\n __int64 v34; // r14\n __int64 v35; // rax\n __int64 v36; // rbx\n __int64 *v37; // rbp\n __int64 *v38; // rdx\n __int64 v39; // rsi\n __int64 v40; // rbp\n __int64 v41; // rcx\n __int64 v42; // r11\n __int64 v43; // r10\n __int64 v44; // r12\n __int64 v45; // r9\n __int64 v46; // r13\n __int64 *v47; // rbx\n __int64 *v48; // rdx\n __int64 v49; // rax\n __int64 v50; // rbx\n __int64 v51; // r8\n __int64 v52; // r14\n __int64 v53; // r12\n __int64 *v54; // rbp\n __int64 *v55; // rdi\n __int64 v56; // rcx\n __int64 v57; // rbp\n __int64 v58; // rbx\n __int64 v59; // r15\n __int64 *v60; // r14\n __int64 *v61; // r12\n __int64 v62; // rdx\n __int64 v63; // r14\n __int64 v64; // rbx\n __int64 v65; // r15\n __int64 *v66; // rbp\n __int64 *v67; // rsi\n __int64 v68; // r13\n __int64 v69; // r12\n __int64 v70; // rbp\n __int64 v71; // rbx\n __int64 v72; // r12\n __int64 v73; // r13\n __int64 v74; // rdi\n __int64 v75; // rsi\n __int64 v76; // [rsp+0h] [rbp-E0h]\n __int64 v77; // [rsp+8h] [rbp-D8h]\n __int64 v78; // [rsp+10h] [rbp-D0h]\n __int64 v79; // [rsp+18h] [rbp-C8h]\n __int64 v80; // [rsp+20h] [rbp-C0h]\n __int64 v81; // [rsp+28h] [rbp-B8h]\n __int64 v82; // [rsp+30h] [rbp-B0h]\n __int64 v83; // [rsp+38h] [rbp-A8h]\n __int64 v84; // [rsp+40h] [rbp-A0h]\n __int64 v85; // [rsp+48h] [rbp-98h]\n __int64 v86; // [rsp+50h] [rbp-90h]\n __int64 v87; // [rsp+58h] [rbp-88h]\n __int64 v88; // [rsp+60h] [rbp-80h]\n __int64 v89; // [rsp+68h] [rbp-78h]\n __int64 v90; // [rsp+70h] [rbp-70h]\n __int64 v91; // [rsp+78h] [rbp-68h]\n __int64 v92; // [rsp+80h] [rbp-60h]\n __int64 v93; // [rsp+88h] [rbp-58h]\n __int64 v94; // [rsp+90h] [rbp-50h]\n __int64 v95; // [rsp+98h] [rbp-48h]\n __int64 v96; // [rsp+A0h] [rbp-40h]\n\n v2 = *((int *)a1 + 2);\n if ( (_DWORD)v2 != *((_DWORD *)a2 + 2) )\n return 0LL;\n if ( (int)v2 <= 0 )\n return 1LL;\n v4 = *a1;\n v5 = *a2;\n v6 = 16 * v2 + *a1;\n do\n {\n v7 = *(__int64 **)(v4 + 8);\n v8 = *(__int64 **)(v5 + 8);\n if ( *(_DWORD *)v4 != *(_DWORD *)v5 )\n return 0LL;\n if ( *(_DWORD *)v4 )\n {\n v9 = *((int *)v7 + 2);\n if ( (_DWORD)v9 != *((_DWORD *)v8 + 2) )\n return 0LL;\n if ( (int)v9 > 0 )\n {\n v10 = *v7;\n v11 = *v8;\n v12 = v4;\n v13 = 16 * v9 + *v7;\n v14 = v5;\n v15 = v13;\n while ( 1 )\n {\n v16 = *(__int64 **)(v10 + 8);\n v17 = *(__int64 **)(v11 + 8);\n if ( *(_DWORD *)v10 != *(_DWORD *)v11 )\n return 0LL;\n if ( *(_DWORD *)v10 )\n {\n v18 = *((int *)v16 + 2);\n if ( (_DWORD)v18 != *((_DWORD *)v17 + 2) )\n return 0LL;\n if ( (int)v18 > 0 )\n {\n v19 = *v16;\n v20 = *v17;\n v21 = v6;\n v77 = v15;\n v22 = v12;\n v23 = 16 * v18 + v19;\n v76 = v11;\n v24 = v14;\n v25 = v20;\n v26 = v23;\n v27 = v10;\n v28 = v21;\n while ( 1 )\n {\n v29 = *(__int64 **)(v19 + 8);\n v30 = *(__int64 **)(v25 + 8);\n if ( *(_DWORD *)v19 != *(_DWORD *)v25 )\n return 0LL;\n if ( *(_DWORD *)v19 )\n {\n v31 = *((int *)v29 + 2);\n if ( (_DWORD)v31 != *((_DWORD *)v30 + 2) )\n return 0LL;\n if ( (int)v31 > 0 )\n {\n v32 = *v29;\n v79 = v25;\n v33 = v27;\n v78 = v19;\n v34 = *v30;\n v35 = v28;\n v36 = *v29 + 16 * v31;\n while ( 1 )\n {\n v37 = *(__int64 **)(v32 + 8);\n v38 = *(__int64 **)(v34 + 8);\n if ( *(_DWORD *)v32 != *(_DWORD *)v34 )\n return 0LL;\n if ( *(_DWORD *)v32 )\n {\n v39 = *((int *)v37 + 2);\n if ( (_DWORD)v39 != *((_DWORD *)v38 + 2) )\n return 0LL;\n if ( (int)v39 > 0 )\n {\n v40 = *v37;\n v80 = v32;\n v41 = v26;\n v42 = v22;\n v81 = v34;\n v43 = v24;\n v82 = v36;\n v44 = *v38;\n v45 = v35;\n v46 = v40 + 16 * v39;\n while ( 1 )\n {\n v47 = *(__int64 **)(v40 + 8);\n v48 = *(__int64 **)(v44 + 8);\n if ( *(_DWORD *)v40 != *(_DWORD *)v44 )\n return 0LL;\n if ( *(_DWORD *)v40 )\n {\n v49 = *((int *)v47 + 2);\n if ( (_DWORD)v49 != *((_DWORD *)v48 + 2) )\n return 0LL;\n if ( (int)v49 > 0 )\n {\n v50 = *v47;\n v84 = v44;\n v51 = v41;\n v83 = v40;\n v52 = *v48;\n v85 = v46;\n v86 = v33;\n v53 = v50 + 16 * v49;\n while ( 1 )\n {\n v54 = *(__int64 **)(v50 + 8);\n v55 = *(__int64 **)(v52 + 8);\n if ( *(_DWORD *)v50 != *(_DWORD *)v52 )\n return 0LL;\n if ( *(_DWORD *)v50 )\n {\n v56 = *((int *)v54 + 2);\n if ( (_DWORD)v56 != *((_DWORD *)v55 + 2) )\n return 0LL;\n if ( (int)v56 > 0 )\n {\n v57 = *v54;\n v88 = v50;\n v87 = v52;\n v58 = *v55;\n v89 = v53;\n v59 = v57 + 16 * v56;\n while ( 1 )\n {\n v60 = *(__int64 **)(v57 + 8);\n v61 = *(__int64 **)(v58 + 8);\n if ( *(_DWORD *)v57 != *(_DWORD *)v58 )\n return 0LL;\n if ( *(_DWORD *)v57 )\n {\n v62 = *((int *)v60 + 2);\n if ( (_DWORD)v62 != *((_DWORD *)v61 + 2) )\n return 0LL;\n if ( (int)v62 > 0 )\n {\n v63 = *v60;\n v90 = v59;\n v91 = v58;\n v92 = v57;\n v64 = *v61;\n v93 = v51;\n v65 = v63 + 16 * v62;\n while ( 1 )\n {\n v66 = *(__int64 **)(v63 + 8);\n v67 = *(__int64 **)(v64 + 8);\n if ( *(_DWORD *)v63 != *(_DWORD *)v64 )\n return 0LL;\n if ( *(_DWORD *)v63 )\n {\n v68 = *((int *)v66 + 2);\n if ( (_DWORD)v68 != *((_DWORD *)v67 + 2) )\n return 0LL;\n if ( (int)v68 > 0 )\n {\n v69 = *v66;\n v94 = v64;\n v95 = v42;\n v70 = *v67;\n v71 = v69;\n v96 = v43;\n v72 = v69 + 16 * v68;\n v73 = v45;\n while ( 1 )\n {\n v74 = *(_QWORD *)(v71 + 8);\n v75 = *(_QWORD *)(v70 + 8);\n if ( *(_DWORD *)v71 != *(_DWORD *)v70 )\n return 0LL;\n if ( *(_DWORD *)v71 )\n {\n if ( !(unsigned int)sub_1B90(v74, v75) )\n return 0LL;\n }\n else if ( (_DWORD)v74 != (_DWORD)v75 )\n {\n return 0LL;\n }\n v71 += 16LL;\n v70 += 16LL;\n if ( v71 == v72 )\n {\n v64 = v94;\n v42 = v95;\n v45 = v73;\n v43 = v96;\n break;\n }\n }\n }\n }\n else if ( (_DWORD)v66 != (_DWORD)v67 )\n {\n return 0LL;\n }\n v63 += 16LL;\n v64 += 16LL;\n if ( v65 == v63 )\n {\n v59 = v90;\n v58 = v91;\n v57 = v92;\n v51 = v93;\n break;\n }\n }\n }\n }\n else if ( (_DWORD)v60 != (_DWORD)v61 )\n {\n return 0LL;\n }\n v57 += 16LL;\n v58 += 16LL;\n if ( v59 == v57 )\n {\n v52 = v87;\n v50 = v88;\n v53 = v89;\n break;\n }\n }\n }\n }\n else if ( (_DWORD)v54 != (_DWORD)v55 )\n {\n return 0LL;\n }\n v50 += 16LL;\n v52 += 16LL;\n if ( v50 == v53 )\n {\n v40 = v83;\n v44 = v84;\n v41 = v51;\n v46 = v85;\n v33 = v86;\n break;\n }\n }\n }\n }\n else if ( (_DWORD)v47 != (_DWORD)v48 )\n {\n return 0LL;\n }\n v40 += 16LL;\n v44 += 16LL;\n if ( v40 == v46 )\n {\n v35 = v45;\n v32 = v80;\n v34 = v81;\n v26 = v41;\n v36 = v82;\n v24 = v43;\n v22 = v42;\n break;\n }\n }\n }\n }\n else if ( (_DWORD)v37 != (_DWORD)v38 )\n {\n return 0LL;\n }\n v32 += 16LL;\n v34 += 16LL;\n if ( v32 == v36 )\n {\n v28 = v35;\n v19 = v78;\n v25 = v79;\n v27 = v33;\n break;\n }\n }\n }\n }\n else if ( (_DWORD)v29 != (_DWORD)v30 )\n {\n return 0LL;\n }\n v19 += 16LL;\n v25 += 16LL;\n if ( v19 == v26 )\n {\n v10 = v27;\n v11 = v76;\n v15 = v77;\n v12 = v22;\n v14 = v24;\n v6 = v28;\n break;\n }\n }\n }\n }\n else if ( (_DWORD)v16 != (_DWORD)v17 )\n {\n return 0LL;\n }\n v10 += 16LL;\n v11 += 16LL;\n if ( v10 == v15 )\n {\n v4 = v12;\n v5 = v14;\n break;\n }\n }\n }\n }\n else if ( (_DWORD)v7 != (_DWORD)v8 )\n {\n return 0LL;\n }\n v4 += 16LL;\n v5 += 16LL;\n }\n while ( v4 != v6 );\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1B90(long long *a1, long long *a2) {\n long long v2;\n long long v4;\n long long v5;\n long long v6;\n long long *v7;\n long long *v8;\n long long v9;\n long long v10;\n long long v11;\n long long v12;\n long long v13;\n long long v14;\n long long v15;\n long long *v16;\n long long *v17;\n long long v18;\n long long v19;\n long long v20;\n long long v21;\n long long v22;\n long long v23;\n long long v24;\n long long v25;\n long long v26;\n long long v27;\n long long v28;\n long long *v29;\n long long *v30;\n long long v31;\n long long v32;\n long long v33;\n long long v34;\n long long v35;\n long long v36;\n long long *v37;\n long long *v38;\n long long v39;\n long long v40;\n long long v41;\n long long v42;\n long long v43;\n long long v44;\n long long v45;\n long long v46;\n long long *v47;\n long long *v48;\n long long v49;\n long long v50;\n long long v51;\n long long v52;\n long long v53;\n long long *v54;\n long long *v55;\n long long v56;\n long long v57;\n long long v58;\n long long v59;\n long long *v60;\n long long *v61;\n long long v62;\n long long v63;\n long long v64;\n long long v65;\n long long *v66;\n long long *v67;\n long long v68;\n long long v69;\n long long v70;\n long long v71;\n long long v72;\n long long v73;\n long long v74;\n long long v75;\n long long v76;\n long long v77;\n long long v78;\n long long v79;\n long long v80;\n long long v81;\n long long v82;\n long long v83;\n long long v84;\n long long v85;\n long long v86;\n long long v87;\n long long v88;\n long long v89;\n long long v90;\n long long v91;\n long long v92;\n long long v93;\n long long v94;\n long long v95;\n long long v96;\n v2 = *((int *)a1 + 2);\n if ((uint32_t)v2 != *((uint32_t *)a2 + 2)) return 0LL;\n if ((int)v2 <= 0) return 1LL;\n v4 = *a1;\n v5 = *a2;\n v6 = 16 * v2 + *a1;\n do {\n v7 = *(long long **)(v4 + 8);\n v8 = *(long long **)(v5 + 8);\n if (*(uint32_t *)v4 != *(uint32_t *)v5) return 0LL;\n if (*(uint32_t *)v4) {\n v9 = *((int *)v7 + 2);\n if ((uint32_t)v9 != *((uint32_t *)v8 + 2)) return 0LL;\n if ((int)v9 > 0) {\n v10 = *v7;\n v11 = *v8;\n v12 = v4;\n v13 = 16 * v9 + *v7;\n v14 = v5;\n v15 = v13;\n while (1) {\n v16 = *(long long **)(v10 + 8);\n v17 = *(long long **)(v11 + 8);\n if (*(uint32_t *)v10 != *(uint32_t *)v11) return 0LL;\n if (*(uint32_t *)v10) {\n v18 = *((int *)v16 + 2);\n if ((uint32_t)v18 != *((uint32_t *)v17 + 2)) return 0LL;\n if ((int)v18 > 0) {\n v19 = *v16;\n v20 = *v17;\n v21 = v6;\n v77 = v15;\n v22 = v12;\n v23 = 16 * v18 + v19;\n v76 = v11;\n v24 = v14;\n v25 = v20;\n v26 = v23;\n v27 = v10;\n v28 = v21;\n while (1) {\n v29 = *(long long **)(v19 + 8);\n v30 = *(long long **)(v25 + 8);\n if (*(uint32_t *)v19 != *(uint32_t *)v25) return 0LL;\n if (*(uint32_t *)v19) {\n v31 = *((int *)v29 + 2);\n if ((uint32_t)v31 != *((uint32_t *)v30 + 2)) return 0LL;\n if ((int)v31 > 0) {\n v32 = *v29;\n v79 = v25;\n v33 = v27;\n v78 = v19;\n v34 = *v30;\n v35 = v28;\n v36 = *v29 + 16 * v31;\n while (1) {\n v37 = *(long long **)(v32 + 8);\n v38 = *(long long **)(v34 + 8);\n if (*(uint32_t *)v32 != *(uint32_t *)v34) return 0LL;\n if (*(uint32_t *)v32) {\n v39 = *((int *)v37 + 2);\n if ((uint32_t)v39 != *((uint32_t *)v38 + 2)) return 0LL;\n if ((int)v39 > 0) {\n v40 = *v37;\n v80 = v32;\n v41 = v26;\n v42 = v22;\n v81 = v34;\n v43 = v24;\n v82 = v36;\n v44 = *v38;\n v45 = v35;\n v46 = v40 + 16 * v39;\n while (1) {\n v47 = *(long long **)(v40 + 8);\n v48 = *(long long **)(v44 + 8);\n if (*(uint32_t *)v40 != *(uint32_t *)v44)\n return 0LL;\n if (*(uint32_t *)v40) {\n v49 = *((int *)v47 + 2);\n if ((uint32_t)v49 != *((uint32_t *)v48 + 2))\n return 0LL;\n if ((int)v49 > 0) {\n v50 = *v47;\n v84 = v44;\n v51 = v41;\n v83 = v40;\n v52 = *v48;\n v85 = v46;\n v86 = v33;\n v53 = v50 + 16 * v49;\n while (1) {\n v54 = *(long long **)(v50 + 8);\n v55 = *(long long **)(v52 + 8);\n if (*(uint32_t *)v50 != *(uint32_t *)v52)\n return 0LL;\n if (*(uint32_t *)v50) {\n v56 = *((int *)v54 + 2);\n if ((uint32_t)v56 != *((uint32_t *)v55 + 2))\n return 0LL;\n if ((int)v56 > 0) {\n v57 = *v54;\n v88 = v50;\n v87 = v52;\n v58 = *v55;\n v89 = v53;\n v59 = v57 + 16 * v56;\n while (1) {\n v60 = *(long long **)(v57 + 8);\n v61 = *(long long **)(v58 + 8);\n if (*(uint32_t *)v57 !=\n *(uint32_t *)v58)\n return 0LL;\n if (*(uint32_t *)v57) {\n v62 = *((int *)v60 + 2);\n if ((uint32_t)v62 !=\n *((uint32_t *)v61 + 2))\n return 0LL;\n if ((int)v62 > 0) {\n v63 = *v60;\n v90 = v59;\n v91 = v58;\n v92 = v57;\n v64 = *v61;\n v93 = v51;\n v65 = v63 + 16 * v62;\n while (1) {\n v66 = *(long long **)(v63 + 8);\n v67 = *(long long **)(v64 + 8);\n if (*(uint32_t *)v63 !=\n *(uint32_t *)v64)\n return 0LL;\n if (*(uint32_t *)v63) {\n v68 = *((int *)v66 + 2);\n if ((uint32_t)v68 !=\n *((uint32_t *)v67 + 2))\n return 0LL;\n if ((int)v68 > 0) {\n v69 = *v66;\n v94 = v64;\n v95 = v42;\n v70 = *v67;\n v71 = v69;\n v96 = v43;\n v72 = v69 + 16 * v68;\n v73 = v45;\n while (1) {\n v74 =\n *(uint64_t *)(v71 + 8);\n v75 =\n *(uint64_t *)(v70 + 8);\n if (*(uint32_t *)v71 !=\n *(uint32_t *)v70)\n return 0LL;\n if (*(uint32_t *)v71) {\n if (!(unsigned int)\n sub_1B90(v74,\n v75))\n return 0LL;\n } else if ((uint32_t)v74 !=\n (uint32_t)v75) {\n return 0LL;\n }\n v71 += 16LL;\n v70 += 16LL;\n if (v71 == v72) {\n v64 = v94;\n v42 = v95;\n v45 = v73;\n v43 = v96;\n break;\n }\n }\n }\n } else if ((uint32_t)v66 !=\n (uint32_t)v67) {\n return 0LL;\n }\n v63 += 16LL;\n v64 += 16LL;\n if (v65 == v63) {\n v59 = v90;\n v58 = v91;\n v57 = v92;\n v51 = v93;\n break;\n }\n }\n }\n } else if ((uint32_t)v60 !=\n (uint32_t)v61) {\n return 0LL;\n }\n v57 += 16LL;\n v58 += 16LL;\n if (v59 == v57) {\n v52 = v87;\n v50 = v88;\n v53 = v89;\n break;\n }\n }\n }\n } else if ((uint32_t)v54 != (uint32_t)v55) {\n return 0LL;\n }\n v50 += 16LL;\n v52 += 16LL;\n if (v50 == v53) {\n v40 = v83;\n v44 = v84;\n v41 = v51;\n v46 = v85;\n v33 = v86;\n break;\n }\n }\n }\n } else if ((uint32_t)v47 != (uint32_t)v48) {\n return 0LL;\n }\n v40 += 16LL;\n v44 += 16LL;\n if (v40 == v46) {\n v35 = v45;\n v32 = v80;\n v34 = v81;\n v26 = v41;\n v36 = v82;\n v24 = v43;\n v22 = v42;\n break;\n }\n }\n }\n } else if ((uint32_t)v37 != (uint32_t)v38) {\n return 0LL;\n }\n v32 += 16LL;\n v34 += 16LL;\n if (v32 == v36) {\n v28 = v35;\n v19 = v78;\n v25 = v79;\n v27 = v33;\n break;\n }\n }\n }\n } else if ((uint32_t)v29 != (uint32_t)v30) {\n return 0LL;\n }\n v19 += 16LL;\n v25 += 16LL;\n if (v19 == v26) {\n v10 = v27;\n v11 = v76;\n v15 = v77;\n v12 = v22;\n v14 = v24;\n v6 = v28;\n break;\n }\n }\n }\n } else if ((uint32_t)v16 != (uint32_t)v17) {\n return 0LL;\n }\n v10 += 16LL;\n v11 += 16LL;\n if (v10 == v15) {\n v4 = v12;\n v5 = v14;\n break;\n }\n }\n }\n } else if ((uint32_t)v7 != (uint32_t)v8) {\n return 0LL;\n }\n v4 += 16LL;\n v5 += 16LL;\n } while (v4 != v6);\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long *a1, long long *a2) {\n long long v2;\n long long v4;\n long long v5;\n long long v6;\n long long *v7;\n long long *v8;\n long long v9;\n long long v10;\n long long v11;\n long long v12;\n long long v13;\n long long v14;\n long long v15;\n long long *v16;\n long long *v17;\n long long v18;\n long long v19;\n long long v20;\n long long v21;\n long long v22;\n long long v23;\n long long v24;\n long long v25;\n long long v26;\n long long v27;\n long long v28;\n long long *v29;\n long long *v30;\n long long v31;\n long long v32;\n long long v33;\n long long v34;\n long long v35;\n long long v36;\n long long *v37;\n long long *v38;\n long long v39;\n long long v40;\n long long v41;\n long long v42;\n long long v43;\n long long v44;\n long long v45;\n long long v46;\n long long *v47;\n long long *v48;\n long long v49;\n long long v50;\n long long v51;\n long long v52;\n long long v53;\n long long *v54;\n long long *v55;\n long long v56;\n long long v57;\n long long v58;\n long long v59;\n long long *v60;\n long long *v61;\n long long v62;\n long long v63;\n long long v64;\n long long v65;\n long long *v66;\n long long *v67;\n long long v68;\n long long v69;\n long long v70;\n long long v71;\n long long v72;\n long long v73;\n long long v74;\n long long v75;\n long long v76;\n long long v77;\n long long v78;\n long long v79;\n long long v80;\n long long v81;\n long long v82;\n long long v83;\n long long v84;\n long long v85;\n long long v86;\n long long v87;\n long long v88;\n long long v89;\n long long v90;\n long long v91;\n long long v92;\n long long v93;\n long long v94;\n long long v95;\n long long v96;\n v2 = *((int *)a1 + 2);\n if ((uint32_t)v2 != *((uint32_t *)a2 + 2)) return 0LL;\n if ((int)v2 <= 0) return 1LL;\n v4 = *a1;\n v5 = *a2;\n v6 = 16 * v2 + *a1;\n do {\n v7 = *(long long **)(v4 + 8);\n v8 = *(long long **)(v5 + 8);\n if (*(uint32_t *)v4 != *(uint32_t *)v5) return 0LL;\n if (*(uint32_t *)v4) {\n v9 = *((int *)v7 + 2);\n if ((uint32_t)v9 != *((uint32_t *)v8 + 2)) return 0LL;\n if ((int)v9 > 0) {\n v10 = *v7;\n v11 = *v8;\n v12 = v4;\n v13 = 16 * v9 + *v7;\n v14 = v5;\n v15 = v13;\n while (1) {\n v16 = *(long long **)(v10 + 8);\n v17 = *(long long **)(v11 + 8);\n if (*(uint32_t *)v10 != *(uint32_t *)v11) return 0LL;\n if (*(uint32_t *)v10) {\n v18 = *((int *)v16 + 2);\n if ((uint32_t)v18 != *((uint32_t *)v17 + 2)) return 0LL;\n if ((int)v18 > 0) {\n v19 = *v16;\n v20 = *v17;\n v21 = v6;\n v77 = v15;\n v22 = v12;\n v23 = 16 * v18 + v19;\n v76 = v11;\n v24 = v14;\n v25 = v20;\n v26 = v23;\n v27 = v10;\n v28 = v21;\n while (1) {\n v29 = *(long long **)(v19 + 8);\n v30 = *(long long **)(v25 + 8);\n if (*(uint32_t *)v19 != *(uint32_t *)v25) return 0LL;\n if (*(uint32_t *)v19) {\n v31 = *((int *)v29 + 2);\n if ((uint32_t)v31 != *((uint32_t *)v30 + 2)) return 0LL;\n if ((int)v31 > 0) {\n v32 = *v29;\n v79 = v25;\n v33 = v27;\n v78 = v19;\n v34 = *v30;\n v35 = v28;\n v36 = *v29 + 16 * v31;\n while (1) {\n v37 = *(long long **)(v32 + 8);\n v38 = *(long long **)(v34 + 8);\n if (*(uint32_t *)v32 != *(uint32_t *)v34) return 0LL;\n if (*(uint32_t *)v32) {\n v39 = *((int *)v37 + 2);\n if ((uint32_t)v39 != *((uint32_t *)v38 + 2)) return 0LL;\n if ((int)v39 > 0) {\n v40 = *v37;\n v80 = v32;\n v41 = v26;\n v42 = v22;\n v81 = v34;\n v43 = v24;\n v82 = v36;\n v44 = *v38;\n v45 = v35;\n v46 = v40 + 16 * v39;\n while (1) {\n v47 = *(long long **)(v40 + 8);\n v48 = *(long long **)(v44 + 8);\n if (*(uint32_t *)v40 != *(uint32_t *)v44)\n return 0LL;\n if (*(uint32_t *)v40) {\n v49 = *((int *)v47 + 2);\n if ((uint32_t)v49 != *((uint32_t *)v48 + 2))\n return 0LL;\n if ((int)v49 > 0) {\n v50 = *v47;\n v84 = v44;\n v51 = v41;\n v83 = v40;\n v52 = *v48;\n v85 = v46;\n v86 = v33;\n v53 = v50 + 16 * v49;\n while (1) {\n v54 = *(long long **)(v50 + 8);\n v55 = *(long long **)(v52 + 8);\n if (*(uint32_t *)v50 != *(uint32_t *)v52)\n return 0LL;\n if (*(uint32_t *)v50) {\n v56 = *((int *)v54 + 2);\n if ((uint32_t)v56 != *((uint32_t *)v55 + 2))\n return 0LL;\n if ((int)v56 > 0) {\n v57 = *v54;\n v88 = v50;\n v87 = v52;\n v58 = *v55;\n v89 = v53;\n v59 = v57 + 16 * v56;\n while (1) {\n v60 = *(long long **)(v57 + 8);\n v61 = *(long long **)(v58 + 8);\n if (*(uint32_t *)v57 !=\n *(uint32_t *)v58)\n return 0LL;\n if (*(uint32_t *)v57) {\n v62 = *((int *)v60 + 2);\n if ((uint32_t)v62 !=\n *((uint32_t *)v61 + 2))\n return 0LL;\n if ((int)v62 > 0) {\n v63 = *v60;\n v90 = v59;\n v91 = v58;\n v92 = v57;\n v64 = *v61;\n v93 = v51;\n v65 = v63 + 16 * v62;\n while (1) {\n v66 = *(long long **)(v63 + 8);\n v67 = *(long long **)(v64 + 8);\n if (*(uint32_t *)v63 !=\n *(uint32_t *)v64)\n return 0LL;\n if (*(uint32_t *)v63) {\n v68 = *((int *)v66 + 2);\n if ((uint32_t)v68 !=\n *((uint32_t *)v67 + 2))\n return 0LL;\n if ((int)v68 > 0) {\n v69 = *v66;\n v94 = v64;\n v95 = v42;\n v70 = *v67;\n v71 = v69;\n v96 = v43;\n v72 = v69 + 16 * v68;\n v73 = v45;\n while (1) {\n v74 =\n *(uint64_t *)(v71 + 8);\n v75 =\n *(uint64_t *)(v70 + 8);\n if (*(uint32_t *)v71 !=\n *(uint32_t *)v70)\n return 0LL;\n if (*(uint32_t *)v71) {\n if (!(unsigned int)func0(\n v74, v75))\n return 0LL;\n } else if ((uint32_t)v74 !=\n (uint32_t)v75) {\n return 0LL;\n }\n v71 += 16LL;\n v70 += 16LL;\n if (v71 == v72) {\n v64 = v94;\n v42 = v95;\n v45 = v73;\n v43 = v96;\n break;\n }\n }\n }\n } else if ((uint32_t)v66 !=\n (uint32_t)v67) {\n return 0LL;\n }\n v63 += 16LL;\n v64 += 16LL;\n if (v65 == v63) {\n v59 = v90;\n v58 = v91;\n v57 = v92;\n v51 = v93;\n break;\n }\n }\n }\n } else if ((uint32_t)v60 !=\n (uint32_t)v61) {\n return 0LL;\n }\n v57 += 16LL;\n v58 += 16LL;\n if (v59 == v57) {\n v52 = v87;\n v50 = v88;\n v53 = v89;\n break;\n }\n }\n }\n } else if ((uint32_t)v54 != (uint32_t)v55) {\n return 0LL;\n }\n v50 += 16LL;\n v52 += 16LL;\n if (v50 == v53) {\n v40 = v83;\n v44 = v84;\n v41 = v51;\n v46 = v85;\n v33 = v86;\n break;\n }\n }\n }\n } else if ((uint32_t)v47 != (uint32_t)v48) {\n return 0LL;\n }\n v40 += 16LL;\n v44 += 16LL;\n if (v40 == v46) {\n v35 = v45;\n v32 = v80;\n v34 = v81;\n v26 = v41;\n v36 = v82;\n v24 = v43;\n v22 = v42;\n break;\n }\n }\n }\n } else if ((uint32_t)v37 != (uint32_t)v38) {\n return 0LL;\n }\n v32 += 16LL;\n v34 += 16LL;\n if (v32 == v36) {\n v28 = v35;\n v19 = v78;\n v25 = v79;\n v27 = v33;\n break;\n }\n }\n }\n } else if ((uint32_t)v29 != (uint32_t)v30) {\n return 0LL;\n }\n v19 += 16LL;\n v25 += 16LL;\n if (v19 == v26) {\n v10 = v27;\n v11 = v76;\n v15 = v77;\n v12 = v22;\n v14 = v24;\n v6 = v28;\n break;\n }\n }\n }\n } else if ((uint32_t)v16 != (uint32_t)v17) {\n return 0LL;\n }\n v10 += 16LL;\n v11 += 16LL;\n if (v10 == v15) {\n v4 = v12;\n v5 = v14;\n break;\n }\n }\n }\n } else if ((uint32_t)v7 != (uint32_t)v8) {\n return 0LL;\n }\n v4 += 16LL;\n v5 += 16LL;\n } while (v4 != v6);\n return 1LL;\n}" + }, + { + "index": 581, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int b, int s) { return 2 * b * s + pow(b, 2); }", + "test": "int main() {\n\n assert(func0(3, 4) == 33);\n\n assert(func0(4, 5) == 56);\n\n assert(func0(1, 2) == 5);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %edi,-0x4(%rbp)\nmov %esi,-0x8(%rbp)\nmov -0x4(%rbp),%eax\nimul -0x8(%rbp),%eax\nadd %eax,%eax\ncvtsi2sd %eax,%xmm2\nmovsd %xmm2,-0x10(%rbp)\ncvtsi2sdl -0x4(%rbp),%xmm0\nmovsd 0xee6(%rip),%xmm1\ncallq 1060 \naddsd -0x10(%rbp),%xmm0\ncvttsd2si %xmm0,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov eax, [rbp+var_4]\nimul eax, [rbp+var_8]\nadd eax, eax\npxor xmm2, xmm2\ncvtsi2sd xmm2, eax\nmovsd [rbp+var_10], xmm2\npxor xmm3, xmm3\ncvtsi2sd xmm3, [rbp+var_4]\nmovq rax, xmm3\nmovsd xmm0, cs:y\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\naddsd xmm0, [rbp+var_10]\ncvttsd2si eax, xmm0\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n return (unsigned int)(int)(pow((double)a1, 2.0) + (double)(2 * a2 * a1));\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov eax, [rbp+var_4]\nimul eax, [rbp+var_8]\nadd eax, eax\npxor xmm2, xmm2\ncvtsi2sd xmm2, eax\nmovsd [rbp+var_10], xmm2\npxor xmm3, xmm3\ncvtsi2sd xmm3, [rbp+var_4]\nmovq rax, xmm3\nmovsd xmm0, cs:y\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\naddsd xmm0, [rbp+var_10]\ncvttsd2si eax, xmm0\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1, int a2)\n{\n return (unsigned int)(int)(pow((double)a1, 2.0) + (double)(2 * a2 * a1));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1, int a2) {\n return (unsigned int)(int)(pow((double)a1, 2.0) + (double)(2 * a2 * a1));\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n return (unsigned int)(int)(pow((double)a1, 2.0) + (double)(2 * a2 * a1));\n}" + }, + { + "index": 582, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int dict1) {\n if (dict1) {\n return false;\n } else {\n return true;\n }\n}", + "test": "int main() {\n\n assert(func0(10) == false);\n\n assert(func0(11) == false);\n\n assert(func0(0) == true);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\ncmpl $0x0,-0x4(%rbp)\nje 1161 \nmov $0x0,%eax\njmp 1166 \nmov $0x1,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\ncmp [rbp+var_4], 0\njz short loc_1161\nmov eax, 0\njmp short loc_1166\nloc_1161:\nmov eax, 1\nloc_1166:\npop rbp\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(int a1)\n{\n return a1 == 0;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\ncmp [rbp+var_4], 0\njz short loc_1161\nmov eax, 0\njmp short loc_1166\nloc_1161:\nmov eax, 1\nloc_1166:\npop rbp\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1149(int a1)\n{\n return a1 == 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1149(int a1) { return a1 == 0; }", + "ida_pseudo_norm": "uint8_t func0(int a1) { return a1 == 0; }" + }, + { + "index": 583, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int num) {\n if (num <= 1) return 1;\n int res_num = 0;\n for (int i = 0; i < num; i++) res_num += func0(i) * func0(num - i - 1);\n return res_num;\n}", + "test": "int main() {\n\n assert(func0(10) == 16796);\n\n assert(func0(9) == 4862);\n\n assert(func0(7) == 429);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x28,%rsp\nmov %edi,-0x24(%rbp)\ncmpl $0x1,-0x24(%rbp)\njg 1166 \nmov $0x1,%eax\njmp 11a7 \nmovl $0x0,-0x18(%rbp)\nmovl $0x0,-0x14(%rbp)\njmp 119c \nmov -0x14(%rbp),%eax\nmov %eax,%edi\ncallq 1149 \nmov %eax,%ebx\nmov -0x24(%rbp),%eax\nsub -0x14(%rbp),%eax\nsub $0x1,%eax\nmov %eax,%edi\ncallq 1149 \nimul %ebx,%eax\nadd %eax,-0x18(%rbp)\naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\ncmp -0x24(%rbp),%eax\njl 1176 \nmov -0x18(%rbp),%eax\nadd $0x28,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+var_24], edi\ncmp [rbp+var_24], 1\njg short loc_1166\nmov eax, 1\njmp short loc_11A7\nloc_1166:\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp short loc_119C\nloc_1176:\nmov eax, [rbp+var_14]\nmov edi, eax\ncall func0\nmov ebx, eax\nmov eax, [rbp+var_24]\nsub eax, [rbp+var_14]\nsub eax, 1\nmov edi, eax\ncall func0\nimul eax, ebx\nadd [rbp+var_18], eax\nadd [rbp+var_14], 1\nloc_119C:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_24]\njl short loc_1176\nmov eax, [rbp+var_18]\nloc_11A7:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v2; // ebx\n unsigned int v3; // [rsp+18h] [rbp-18h]\n int i; // [rsp+1Ch] [rbp-14h]\n\n if ( a1 <= 1 )\n return 1LL;\n v3 = 0;\n for ( i = 0; i < a1; ++i )\n {\n v2 = func0((unsigned int)i);\n v3 += v2 * func0((unsigned int)(a1 - i - 1));\n }\n return v3;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+var_24], edi\ncmp [rbp+var_24], 1\njg short loc_1166\nmov eax, 1\njmp short loc_11A7\nloc_1166:\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp short loc_119C\nloc_1176:\nmov eax, [rbp+var_14]\nmov edi, eax\ncall sub_1149\nmov ebx, eax\nmov eax, [rbp+var_24]\nsub eax, [rbp+var_14]\nsub eax, 1\nmov edi, eax\ncall sub_1149\nimul eax, ebx\nadd [rbp+var_18], eax\nadd [rbp+var_14], 1\nloc_119C:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_24]\njl short loc_1176\nmov eax, [rbp+var_18]\nloc_11A7:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v2; // ebx\n unsigned int v3; // [rsp+18h] [rbp-18h]\n int i; // [rsp+1Ch] [rbp-14h]\n\n if ( a1 <= 1 )\n return 1LL;\n v3 = 0;\n for ( i = 0; i < a1; ++i )\n {\n v2 = sub_1149((unsigned int)i);\n v3 += v2 * sub_1149((unsigned int)(a1 - i - 1));\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v2;\n unsigned int v3;\n int i;\n if (a1 <= 1) return 1LL;\n v3 = 0;\n for (i = 0; i < a1; ++i) {\n v2 = sub_1149((unsigned int)i);\n v3 += v2 * sub_1149((unsigned int)(a1 - i - 1));\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v2;\n unsigned int v3;\n int i;\n if (a1 <= 1) return 1LL;\n v3 = 0;\n for (i = 0; i < a1; ++i) {\n v2 = func0((unsigned int)i);\n v3 += v2 * func0((unsigned int)(a1 - i - 1));\n }\n return v3;\n}" + }, + { + "index": 583, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int num) {\n if (num <= 1) return 1;\n int res_num = 0;\n for (int i = 0; i < num; i++) res_num += func0(i) * func0(num - i - 1);\n return res_num;\n}", + "test": "int main() {\n\n assert(func0(10) == 16796);\n\n assert(func0(9) == 4862);\n\n assert(func0(7) == 429);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov $0x1,%r12d\ncmp $0x1,%edi\njle 118f \nlea -0x1(%rdi),%ebp\nmov $0x0,%r12d\nmov %ebp,%r13d\nmov %r13d,%edi\nsub %ebp,%edi\ncallq 1149 \nmov %eax,%ebx\nmov %ebp,%edi\ncallq 1149 \nimul %eax,%ebx\nadd %ebx,%r12d\nsub $0x1,%ebp\ncmp $0xffffffff,%ebp\njne 116e \nmov %r12d,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12d, 1\ncmp edi, 1\njle short loc_118F\nlea ebp, [rdi-1]\nmov r12d, 0\nmov r13d, ebp\nloc_116E:\nmov edi, r13d\nsub edi, ebp\ncall func0\nmov ebx, eax\nmov edi, ebp\ncall func0\nimul ebx, eax\nadd r12d, ebx\nsub ebp, 1\ncmp ebp, 0FFFFFFFFh\njnz short loc_116E\nloc_118F:\nmov eax, r12d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v1; // r12d\n unsigned int v2; // ebp\n int v3; // ebx\n\n v1 = 1;\n if ( a1 > 1 )\n {\n v2 = a1 - 1;\n v1 = 0;\n do\n {\n v3 = func0(a1 - 1 - v2);\n v1 += func0(v2--) * v3;\n }\n while ( v2 != -1 );\n }\n return v1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12d, 1\ncmp edi, 1\njle short loc_118F\nlea ebp, [rdi-1]\nmov r12d, 0\nmov r13d, ebp\nloc_116E:\nmov edi, r13d\nsub edi, ebp\ncall sub_1149\nmov ebx, eax\nmov edi, ebp\ncall sub_1149\nimul ebx, eax\nadd r12d, ebx\nsub ebp, 1\ncmp ebp, 0FFFFFFFFh\njnz short loc_116E\nloc_118F:\nmov eax, r12d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n unsigned int v1; // r12d\n unsigned int v2; // ebp\n int v3; // ebx\n\n v1 = 1;\n if ( a1 > 1 )\n {\n v2 = a1 - 1;\n v1 = 0;\n do\n {\n v3 = sub_1149(a1 - 1 - v2);\n v1 += sub_1149(v2--) * v3;\n }\n while ( v2 != -1 );\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n unsigned int v1;\n unsigned int v2;\n int v3;\n v1 = 1;\n if (a1 > 1) {\n v2 = a1 - 1;\n v1 = 0;\n do {\n v3 = sub_1149(a1 - 1 - v2);\n v1 += sub_1149(v2--) * v3;\n } while (v2 != -1);\n }\n return v1;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v1;\n unsigned int v2;\n int v3;\n v1 = 1;\n if (a1 > 1) {\n v2 = a1 - 1;\n v1 = 0;\n do {\n v3 = func0(a1 - 1 - v2);\n v1 += func0(v2--) * v3;\n } while (v2 != -1);\n }\n return v1;\n}" + }, + { + "index": 583, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int num) {\n if (num <= 1) return 1;\n int res_num = 0;\n for (int i = 0; i < num; i++) res_num += func0(i) * func0(num - i - 1);\n return res_num;\n}", + "test": "int main() {\n\n assert(func0(10) == 16796);\n\n assert(func0(9) == 4862);\n\n assert(func0(7) == 429);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%edi\njle 1200 \njmp 1210 \nnopl 0x0(%rax,%rax,1)\nmov $0x1,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0_part_0:\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 48h\nmov [rsp+78h+var_5C], 0\ntest edi, edi\njle loc_2441\nmov [rsp+78h+var_60], 0\nlea ebx, [rdi-1]\nmov [rsp+78h+var_6C], 1\nmov r12d, ebx\nloc_1224:\ncmp r12d, 1\njle loc_2414\nloc_122E:\nlea ebp, [r12-1]\nxor r15d, r15d\nmov [rsp+78h+var_68], 0\nmov r13d, 1\nmov r12d, ebp\nmov [rsp+78h+var_58], ebp\nmov ebp, r15d\nmov r15d, r13d\nmov r13d, r12d\nloc_1254:\ncmp r13d, 1\njle loc_1AF0\nmov [rsp+78h+var_64], r15d\nsub r13d, 1\nxor ebx, ebx\nxor esi, esi\nmov r14d, r13d\nmov r12d, 1\nmov r9d, ebx\nloc_1277:\ncmp r14d, 1\njle loc_1680\nsub r14d, 1\nxor r11d, r11d\nmov [rsp+78h+var_70], esi\nxor r10d, r10d\nmov edx, r14d\nmov r15d, 1\nmov esi, r11d\nloc_129B:\ncmp edx, 1\njle loc_1458\nsub edx, 1\nxor ecx, ecx\nxor r8d, r8d\nmov r11d, 1\nmov ebx, edx\nloc_12B4:\ncmp ebx, 1\njle loc_1370\nloc_12BD:\nmov edi, ebx\nmov [rsp+78h+var_3C], edx\nsub ebx, 1\nmov [rsp+78h+var_40], esi\nmov [rsp+78h+var_44], r10d\nmov [rsp+78h+var_48], r9d\nmov [rsp+78h+var_4C], ecx\nmov [rsp+78h+var_50], r8d\nmov [rsp+78h+var_54], r11d\ncall func0_part_0\nmov r11d, [rsp+78h+var_54]\nmov r8d, [rsp+78h+var_50]\nmov ecx, [rsp+78h+var_4C]\nmov r9d, [rsp+78h+var_48]\nimul eax, r11d\nmov r10d, [rsp+78h+var_44]\nmov esi, [rsp+78h+var_40]\nmov edx, [rsp+78h+var_3C]\nadd ecx, 1\nadd r8d, eax\nnop dword ptr [rax+00000000h]\nloc_1318:\ncmp ecx, 1\njz loc_24F8\nmov edi, ecx\nmov [rsp+78h+var_40], edx\nmov [rsp+78h+var_44], esi\nmov [rsp+78h+var_48], r10d\nmov [rsp+78h+var_4C], r9d\nmov [rsp+78h+var_50], r8d\nmov [rsp+78h+var_54], ecx\ncall func0_part_0\nmov ecx, [rsp+78h+var_54]\nmov r8d, [rsp+78h+var_50]\nmov r9d, [rsp+78h+var_4C]\nmov r10d, [rsp+78h+var_48]\nmov r11d, eax\nmov esi, [rsp+78h+var_44]\nmov edx, [rsp+78h+var_40]\ncmp ebx, 1\njg loc_12BD\nnop word ptr [rax+rax+00h]\nloc_1370:\nadd r8d, r11d\nadd ecx, 1\ntest ebx, ebx\njz short loc_1380\nxor ebx, ebx\njmp short loc_1318\nloc_1380:\nimul r8d, r15d\nadd esi, 1\nadd r10d, r8d\nloc_138A:\ncmp esi, 1\njz loc_24ED\nlea ebx, [rsi-1]\nxor r15d, r15d\nxor ecx, ecx\nmov r8d, 1\nloc_13A1:\ncmp ebx, 1\njle loc_1440\nloc_13AA:\nmov edi, ebx\nmov [rsp+78h+var_40], esi\nsub ebx, 1\nmov [rsp+78h+var_44], edx\nmov [rsp+78h+var_48], r10d\nmov [rsp+78h+var_4C], r9d\nmov [rsp+78h+var_50], ecx\nmov [rsp+78h+var_54], r8d\ncall func0_part_0\nmov r8d, [rsp+78h+var_54]\nmov ecx, [rsp+78h+var_50]\nmov r9d, [rsp+78h+var_4C]\nmov r10d, [rsp+78h+var_48]\nimul eax, r8d\nmov edx, [rsp+78h+var_44]\nmov esi, [rsp+78h+var_40]\nadd ecx, 1\nadd r15d, eax\nnop dword ptr [rax+00h]\nloc_13F8:\ncmp ecx, 1\njz loc_24E2\nmov edi, ecx\nmov [rsp+78h+var_44], esi\nmov [rsp+78h+var_48], edx\nmov [rsp+78h+var_4C], r10d\nmov [rsp+78h+var_50], r9d\nmov [rsp+78h+var_54], ecx\ncall func0_part_0\nmov ecx, [rsp+78h+var_54]\nmov r9d, [rsp+78h+var_50]\nmov r10d, [rsp+78h+var_4C]\nmov edx, [rsp+78h+var_48]\nmov r8d, eax\nmov esi, [rsp+78h+var_44]\ncmp ebx, 1\njg loc_13AA\nloc_1440:\nadd r15d, r8d\nadd ecx, 1\ntest ebx, ebx\njz loc_129B\nxor ebx, ebx\njmp short loc_13F8\nloc_1458:\nadd r10d, r15d\ntest edx, edx\njz short loc_1470\nadd esi, 1\nxor edx, edx\njmp loc_138A\nloc_1470:\nimul r10d, r12d\nmov esi, [rsp+78h+var_70]\nadd esi, 1\nadd r9d, r10d\nloc_147E:\ncmp esi, 1\njz loc_24D7\nlea r10d, [rsi-1]\nxor r12d, r12d\nxor r11d, r11d\nmov r15d, 1\nloc_1497:\ncmp r10d, 1\njle loc_1668\nlea ecx, [r10-1]\nxor r8d, r8d\nxor edx, edx\nmov r10d, 1\nmov ebx, ecx\nloc_14B2:\ncmp ebx, 1\njle loc_1568\nloc_14BB:\nmov edi, ebx\nmov [rsp+78h+var_40], ecx\nsub ebx, 1\nmov [rsp+78h+var_44], r11d\nmov [rsp+78h+var_48], r9d\nmov [rsp+78h+var_4C], esi\nmov [rsp+78h+var_50], r10d\nmov [rsp+78h+var_54], edx\nmov [rsp+78h+var_70], r8d\ncall func0_part_0\nmov r10d, [rsp+78h+var_50]\nmov r8d, [rsp+78h+var_70]\nmov edx, [rsp+78h+var_54]\nmov esi, [rsp+78h+var_4C]\nimul eax, r10d\nmov r9d, [rsp+78h+var_48]\nmov r11d, [rsp+78h+var_44]\nmov ecx, [rsp+78h+var_40]\nadd edx, 1\nadd r8d, eax\nnop\nloc_1510:\ncmp edx, 1\njz loc_24CC\nmov edi, edx\nmov [rsp+78h+var_44], ecx\nmov [rsp+78h+var_48], r11d\nmov [rsp+78h+var_4C], r9d\nmov [rsp+78h+var_50], esi\nmov [rsp+78h+var_54], r8d\nmov [rsp+78h+var_70], edx\ncall func0_part_0\nmov edx, [rsp+78h+var_70]\nmov r8d, [rsp+78h+var_54]\nmov esi, [rsp+78h+var_50]\nmov r9d, [rsp+78h+var_4C]\nmov r10d, eax\nmov r11d, [rsp+78h+var_48]\nmov ecx, [rsp+78h+var_44]\ncmp ebx, 1\njg loc_14BB\nnop word ptr [rax+rax+00h]\nloc_1568:\nadd r8d, r10d\nadd edx, 1\ntest ebx, ebx\njz short loc_1580\nxor ebx, ebx\njmp short loc_1510\nloc_1580:\nimul r8d, r15d\nadd r11d, 1\nmov r10d, ecx\nadd r12d, r8d\nloc_158E:\ncmp r11d, 1\njz loc_24C1\nlea ebx, [r11-1]\nxor edx, edx\nxor r15d, r15d\nmov r8d, 1\nloc_15A7:\ncmp ebx, 1\njle loc_1650\nloc_15B0:\nmov edi, ebx\nmov [rsp+78h+var_44], r10d\nsub ebx, 1\nmov [rsp+78h+var_48], r11d\nmov [rsp+78h+var_4C], r9d\nmov [rsp+78h+var_50], esi\nmov [rsp+78h+var_54], edx\nmov [rsp+78h+var_70], r8d\ncall func0_part_0\nmov r8d, [rsp+78h+var_70]\nmov edx, [rsp+78h+var_54]\nmov esi, [rsp+78h+var_50]\nmov r9d, [rsp+78h+var_4C]\nimul eax, r8d\nmov r11d, [rsp+78h+var_48]\nmov r10d, [rsp+78h+var_44]\nadd edx, 1\nadd r15d, eax\nnop dword ptr [rax+00h]\nloc_1600:\ncmp edx, 1\njz loc_24B6\nmov edi, edx\nmov [rsp+78h+var_48], r10d\nmov [rsp+78h+var_4C], r11d\nmov [rsp+78h+var_50], r9d\nmov [rsp+78h+var_54], esi\nmov [rsp+78h+var_70], edx\ncall func0_part_0\nmov edx, [rsp+78h+var_70]\nmov esi, [rsp+78h+var_54]\nmov r9d, [rsp+78h+var_50]\nmov r11d, [rsp+78h+var_4C]\nmov r8d, eax\nmov r10d, [rsp+78h+var_48]\ncmp ebx, 1\njg loc_15B0\nnop word ptr [rax+rax+00h]\nloc_1650:\nadd r15d, r8d\nadd edx, 1\ntest ebx, ebx\njz loc_1497\nxor ebx, ebx\njmp short loc_1600\nloc_1668:\nadd r12d, r15d\ntest r10d, r10d\njz loc_1277\nadd r11d, 1\nxor r10d, r10d\njmp loc_158E\nloc_1680:\nadd r9d, r12d\ntest r14d, r14d\njz short loc_1698\nadd esi, 1\nxor r14d, r14d\njmp loc_147E\nloc_1698:\nmov r15d, [rsp+78h+var_64]\nadd ebp, 1\nimul r15d, r9d\nadd [rsp+78h+var_68], r15d\nloc_16A9:\ncmp ebp, 1\njz loc_24AB\nlea r12d, [rbp-1]\nxor r15d, r15d\nxor ebx, ebx\nmov r14d, 1\nloc_16C1:\ncmp r12d, 1\njle loc_1AD0\nlea edx, [r12-1]\nxor r8d, r8d\nxor r9d, r9d\nmov r12d, 1\nmov [rsp+78h+var_70], edx\nmov r10d, edx\nloc_16E3:\ncmp r10d, 1\njle loc_18B8\nlea edx, [r10-1]\nxor r11d, r11d\nxor esi, esi\nmov r10d, 1\nmov ecx, edx\nloc_16FE:\ncmp ecx, 1\njle loc_17B8\nloc_1707:\nmov edi, ecx\nmov [rsp+78h+var_40], edx\nmov [rsp+78h+var_44], r8d\nmov [rsp+78h+var_48], r9d\nmov [rsp+78h+var_4C], esi\nmov [rsp+78h+var_50], r11d\nmov [rsp+78h+var_54], r10d\nmov [rsp+78h+var_64], ecx\ncall func0_part_0\nmov r10d, [rsp+78h+var_54]\nmov r11d, [rsp+78h+var_50]\nmov esi, [rsp+78h+var_4C]\nmov ecx, [rsp+78h+var_64]\nimul eax, r10d\nmov r9d, [rsp+78h+var_48]\nmov r8d, [rsp+78h+var_44]\nmov edx, [rsp+78h+var_40]\nadd esi, 1\nsub ecx, 1\nadd r11d, eax\nnop dword ptr [rax+rax+00h]\nloc_1760:\ncmp esi, 1\njz loc_24A0\nmov edi, esi\nmov [rsp+78h+var_44], edx\nmov [rsp+78h+var_48], r8d\nmov [rsp+78h+var_4C], r9d\nmov [rsp+78h+var_50], ecx\nmov [rsp+78h+var_54], r11d\nmov [rsp+78h+var_64], esi\ncall func0_part_0\nmov ecx, [rsp+78h+var_50]\nmov esi, [rsp+78h+var_64]\nmov r11d, [rsp+78h+var_54]\nmov r9d, [rsp+78h+var_4C]\nmov r10d, eax\nmov r8d, [rsp+78h+var_48]\nmov edx, [rsp+78h+var_44]\ncmp ecx, 1\njg loc_1707\nnop word ptr [rax+rax+00h]\nloc_17B8:\nadd r11d, r10d\nadd esi, 1\ntest ecx, ecx\njz short loc_17D0\nxor ecx, ecx\njmp short loc_1760\nloc_17D0:\nimul r11d, r12d\nadd r9d, 1\nmov r10d, edx\nadd r8d, r11d\nloc_17DE:\ncmp r9d, 1\njz loc_2495\nlea ecx, [r9-1]\nxor r12d, r12d\nxor esi, esi\nmov r11d, 1\nloc_17F7:\ncmp ecx, 1\njle loc_18A0\nloc_1800:\nmov edi, ecx\nmov [rsp+78h+var_44], r10d\nmov [rsp+78h+var_48], r8d\nmov [rsp+78h+var_4C], r9d\nmov [rsp+78h+var_50], esi\nmov [rsp+78h+var_54], r11d\nmov [rsp+78h+var_64], ecx\ncall func0_part_0\nmov r11d, [rsp+78h+var_54]\nmov esi, [rsp+78h+var_50]\nmov ecx, [rsp+78h+var_64]\nmov r9d, [rsp+78h+var_4C]\nimul eax, r11d\nmov r8d, [rsp+78h+var_48]\nmov r10d, [rsp+78h+var_44]\nadd esi, 1\nsub ecx, 1\nadd r12d, eax\nnop dword ptr [rax+00h]\nloc_1850:\ncmp esi, 1\njz loc_248A\nmov edi, esi\nmov [rsp+78h+var_48], r10d\nmov [rsp+78h+var_4C], r8d\nmov [rsp+78h+var_50], r9d\nmov [rsp+78h+var_54], ecx\nmov [rsp+78h+var_64], esi\ncall func0_part_0\nmov ecx, [rsp+78h+var_54]\nmov esi, [rsp+78h+var_64]\nmov r9d, [rsp+78h+var_50]\nmov r8d, [rsp+78h+var_4C]\nmov r11d, eax\nmov r10d, [rsp+78h+var_48]\ncmp ecx, 1\njg loc_1800\nnop word ptr [rax+rax+00h]\nloc_18A0:\nadd r12d, r11d\nadd esi, 1\ntest ecx, ecx\njz loc_16E3\nxor ecx, ecx\njmp short loc_1850\nloc_18B8:\nadd r8d, r12d\ntest r10d, r10d\njz short loc_18D0\nadd r9d, 1\nxor r10d, r10d\njmp loc_17DE\nloc_18D0:\nimul r8d, r14d\nmov edx, [rsp+78h+var_70]\nadd ebx, 1\nmov r12d, edx\nadd r15d, r8d\nloc_18E1:\ncmp ebx, 1\njz loc_247F\nlea r8d, [rbx-1]\nxor r14d, r14d\nxor r9d, r9d\nmov esi, 1\nloc_18F9:\ncmp r8d, 1\njle loc_1AB8\nsub r8d, 1\nxor r10d, r10d\nxor ecx, ecx\nmov r11d, 1\nmov edx, r8d\nloc_1915:\ncmp edx, 1\njle loc_19D0\nloc_191E:\nmov edi, edx\nmov [rsp+78h+var_44], r8d\nmov [rsp+78h+var_48], r9d\nmov [rsp+78h+var_4C], r11d\nmov [rsp+78h+var_50], ecx\nmov [rsp+78h+var_54], r10d\nmov [rsp+78h+var_64], esi\nmov [rsp+78h+var_70], edx\ncall func0_part_0\nmov r11d, [rsp+78h+var_4C]\nmov r10d, [rsp+78h+var_54]\nmov ecx, [rsp+78h+var_50]\nmov edx, [rsp+78h+var_70]\nimul eax, r11d\nmov esi, [rsp+78h+var_64]\nmov r9d, [rsp+78h+var_48]\nmov r8d, [rsp+78h+var_44]\nadd ecx, 1\nsub edx, 1\nadd r10d, eax\nnop word ptr [rax+rax+00h]\nloc_1978:\ncmp ecx, 1\njz loc_2474\nmov edi, ecx\nmov [rsp+78h+var_48], r8d\nmov [rsp+78h+var_4C], r9d\nmov [rsp+78h+var_50], r10d\nmov [rsp+78h+var_54], esi\nmov [rsp+78h+var_64], edx\nmov [rsp+78h+var_70], ecx\ncall func0_part_0\nmov edx, [rsp+78h+var_64]\nmov ecx, [rsp+78h+var_70]\nmov esi, [rsp+78h+var_54]\nmov r10d, [rsp+78h+var_50]\nmov r11d, eax\nmov r9d, [rsp+78h+var_4C]\nmov r8d, [rsp+78h+var_48]\ncmp edx, 1\njg loc_191E\nnop word ptr [rax+rax+00h]\nloc_19D0:\nadd r10d, r11d\nadd ecx, 1\ntest edx, edx\njz short loc_19E0\nxor edx, edx\njmp short loc_1978\nloc_19E0:\nimul r10d, esi\nadd r9d, 1\nadd r14d, r10d\nloc_19EB:\ncmp r9d, 1\njz loc_246A\nlea edx, [r9-1]\nxor esi, esi\nxor ecx, ecx\nmov r10d, 1\nloc_1A03:\ncmp edx, 1\njle loc_1AA0\nloc_1A0C:\nmov edi, edx\nmov [rsp+78h+var_48], r8d\nmov [rsp+78h+var_4C], r9d\nmov [rsp+78h+var_50], r10d\nmov [rsp+78h+var_54], ecx\nmov [rsp+78h+var_64], esi\nmov [rsp+78h+var_70], edx\ncall func0_part_0\nmov r10d, [rsp+78h+var_50]\nmov esi, [rsp+78h+var_64]\nmov ecx, [rsp+78h+var_54]\nmov edx, [rsp+78h+var_70]\nimul eax, r10d\nmov r9d, [rsp+78h+var_4C]\nmov r8d, [rsp+78h+var_48]\nadd ecx, 1\nsub edx, 1\nadd esi, eax\nnop dword ptr [rax]\nloc_1A58:\ncmp ecx, 1\njz loc_245F\nmov edi, ecx\nmov [rsp+78h+var_4C], r8d\nmov [rsp+78h+var_50], r9d\nmov [rsp+78h+var_54], esi\nmov [rsp+78h+var_64], edx\nmov [rsp+78h+var_70], ecx\ncall func0_part_0\nmov edx, [rsp+78h+var_64]\nmov ecx, [rsp+78h+var_70]\nmov esi, [rsp+78h+var_54]\nmov r9d, [rsp+78h+var_50]\nmov r10d, eax\nmov r8d, [rsp+78h+var_4C]\ncmp edx, 1\njg loc_1A0C\nloc_1AA0:\nadd esi, r10d\nadd ecx, 1\ntest edx, edx\njz loc_18F9\nxor edx, edx\njmp short loc_1A58\nloc_1AB8:\nadd r14d, esi\ntest r8d, r8d\njz loc_16C1\nadd r9d, 1\nxor r8d, r8d\njmp loc_19EB\nloc_1AD0:\nadd r15d, r14d\ntest r12d, r12d\njz loc_1254\nadd ebx, 1\nxor r12d, r12d\njmp loc_18E1\nloc_1AF0:\nadd [rsp+78h+var_68], r15d\ntest r13d, r13d\njz short loc_1B05\nadd ebp, 1\nxor r13d, r13d\njmp loc_16A9\nloc_1B05:\nmov eax, [rsp+78h+var_6C]\nmov edi, [rsp+78h+var_68]\nmov ebp, [rsp+78h+var_58]\nadd [rsp+78h+var_60], 1\nimul eax, edi\nadd [rsp+78h+var_5C], eax\ncmp [rsp+78h+var_60], 1\nmov r12d, ebp\njz loc_2434\nloc_1B2B:\nmov eax, [rsp+78h+var_60]\nmov [rsp+78h+var_6C], 0\nxor r15d, r15d\nmov r13d, 1\nmov [rsp+78h+var_64], r12d\nlea ebp, [rax-1]\nmov eax, ebp\nmov ebp, r15d\nmov r15d, r13d\nmov r13d, eax\nloc_1B53:\ncmp r13d, 1\njle loc_23F0\nmov [rsp+78h+var_68], r15d\nsub r13d, 1\nxor ebx, ebx\nxor esi, esi\nmov r14d, r13d\nmov r12d, 1\nmov r9d, ebx\nloc_1B76:\ncmp r14d, 1\njle loc_1F80\nsub r14d, 1\nxor r11d, r11d\nmov [rsp+78h+var_70], esi\nxor r10d, r10d\nmov edx, r14d\nmov r15d, 1\nmov esi, r11d\nloc_1B9A:\ncmp edx, 1\njle loc_1D58\nsub edx, 1\nxor r8d, r8d\nxor ecx, ecx\nmov r11d, 1\nmov ebx, edx\nloc_1BB3:\ncmp ebx, 1\njle loc_1C68\nloc_1BBC:\nmov edi, ebx\nmov [rsp+78h+var_40], edx\nsub ebx, 1\nmov [rsp+78h+var_44], r10d\nmov [rsp+78h+var_48], esi\nmov [rsp+78h+var_4C], r9d\nmov [rsp+78h+var_50], r11d\nmov [rsp+78h+var_54], ecx\nmov [rsp+78h+var_58], r8d\ncall func0_part_0\nmov r11d, [rsp+78h+var_50]\nmov r8d, [rsp+78h+var_58]\nmov ecx, [rsp+78h+var_54]\nmov r9d, [rsp+78h+var_4C]\nimul eax, r11d\nmov esi, [rsp+78h+var_48]\nmov r10d, [rsp+78h+var_44]\nmov edx, [rsp+78h+var_40]\nadd ecx, 1\nadd r8d, eax\nloc_1C10:\ncmp ecx, 1\njz loc_2454\nmov edi, ecx\nmov [rsp+78h+var_44], edx\nmov [rsp+78h+var_48], r10d\nmov [rsp+78h+var_4C], esi\nmov [rsp+78h+var_50], r9d\nmov [rsp+78h+var_54], r8d\nmov [rsp+78h+var_58], ecx\ncall func0_part_0\nmov ecx, [rsp+78h+var_58]\nmov r8d, [rsp+78h+var_54]\nmov r9d, [rsp+78h+var_50]\nmov esi, [rsp+78h+var_4C]\nmov r11d, eax\nmov r10d, [rsp+78h+var_48]\nmov edx, [rsp+78h+var_44]\ncmp ebx, 1\njg loc_1BBC\nnop word ptr [rax+rax+00h]\nloc_1C68:\nadd r8d, r11d\nadd ecx, 1\ntest ebx, ebx\njz short loc_1C80\nxor ebx, ebx\njmp short loc_1C10\nloc_1C80:\nimul r8d, r15d\nadd esi, 1\nadd r10d, r8d\nloc_1C8A:\ncmp esi, 1\njz loc_2590\nlea ebx, [rsi-1]\nxor r15d, r15d\nxor ecx, ecx\nmov r8d, 1\nloc_1CA1:\ncmp ebx, 1\njle loc_1D40\nloc_1CAA:\nmov edi, ebx\nmov [rsp+78h+var_44], r10d\nsub ebx, 1\nmov [rsp+78h+var_48], esi\nmov [rsp+78h+var_4C], edx\nmov [rsp+78h+var_50], r9d\nmov [rsp+78h+var_54], r8d\nmov [rsp+78h+var_58], ecx\ncall func0_part_0\nmov r8d, [rsp+78h+var_54]\nmov ecx, [rsp+78h+var_58]\nmov r9d, [rsp+78h+var_50]\nmov edx, [rsp+78h+var_4C]\nimul eax, r8d\nmov esi, [rsp+78h+var_48]\nmov r10d, [rsp+78h+var_44]\nadd ecx, 1\nadd r15d, eax\nnop dword ptr [rax+00h]\nloc_1CF8:\ncmp ecx, 1\njz loc_2585\nmov edi, ecx\nmov [rsp+78h+var_48], r10d\nmov [rsp+78h+var_4C], esi\nmov [rsp+78h+var_50], edx\nmov [rsp+78h+var_54], r9d\nmov [rsp+78h+var_58], ecx\ncall func0_part_0\nmov ecx, [rsp+78h+var_58]\nmov r9d, [rsp+78h+var_54]\nmov edx, [rsp+78h+var_50]\nmov esi, [rsp+78h+var_4C]\nmov r8d, eax\nmov r10d, [rsp+78h+var_48]\ncmp ebx, 1\njg loc_1CAA\nloc_1D40:\nadd r15d, r8d\nadd ecx, 1\ntest ebx, ebx\njz loc_1B9A\nxor ebx, ebx\njmp short loc_1CF8\nloc_1D58:\nadd r10d, r15d\ntest edx, edx\njz short loc_1D70\nadd esi, 1\nxor edx, edx\njmp loc_1C8A\nloc_1D70:\nimul r10d, r12d\nmov esi, [rsp+78h+var_70]\nadd esi, 1\nadd r9d, r10d\nloc_1D7E:\ncmp esi, 1\njz loc_257A\nlea r10d, [rsi-1]\nxor r11d, r11d\nxor r12d, r12d\nmov r15d, 1\nloc_1D97:\ncmp r10d, 1\njle loc_1F68\nlea ecx, [r10-1]\nxor r8d, r8d\nxor edx, edx\nmov r10d, 1\nmov ebx, ecx\nloc_1DB2:\ncmp ebx, 1\njle loc_1E68\nloc_1DBB:\nmov edi, ebx\nmov [rsp+78h+var_44], ecx\nsub ebx, 1\nmov [rsp+78h+var_48], r11d\nmov [rsp+78h+var_4C], esi\nmov [rsp+78h+var_50], r9d\nmov [rsp+78h+var_54], r10d\nmov [rsp+78h+var_58], edx\nmov [rsp+78h+var_70], r8d\ncall func0_part_0\nmov r10d, [rsp+78h+var_54]\nmov r8d, [rsp+78h+var_70]\nmov edx, [rsp+78h+var_58]\nmov r9d, [rsp+78h+var_50]\nimul eax, r10d\nmov esi, [rsp+78h+var_4C]\nmov r11d, [rsp+78h+var_48]\nmov ecx, [rsp+78h+var_44]\nadd edx, 1\nadd r8d, eax\nnop\nloc_1E10:\ncmp edx, 1\njz loc_256F\nmov edi, edx\nmov [rsp+78h+var_48], ecx\nmov [rsp+78h+var_4C], r11d\nmov [rsp+78h+var_50], esi\nmov [rsp+78h+var_54], r9d\nmov [rsp+78h+var_58], r8d\nmov [rsp+78h+var_70], edx\ncall func0_part_0\nmov edx, [rsp+78h+var_70]\nmov r8d, [rsp+78h+var_58]\nmov r9d, [rsp+78h+var_54]\nmov esi, [rsp+78h+var_50]\nmov r10d, eax\nmov r11d, [rsp+78h+var_4C]\nmov ecx, [rsp+78h+var_48]\ncmp ebx, 1\njg loc_1DBB\nnop word ptr [rax+rax+00h]\nloc_1E68:\nadd r8d, r10d\nadd edx, 1\ntest ebx, ebx\njz short loc_1E80\nxor ebx, ebx\njmp short loc_1E10\nloc_1E80:\nimul r8d, r15d\nadd r11d, 1\nmov r10d, ecx\nadd r12d, r8d\nloc_1E8E:\ncmp r11d, 1\njz loc_2564\nlea ebx, [r11-1]\nxor edx, edx\nxor r15d, r15d\nmov r8d, 1\nloc_1EA7:\ncmp ebx, 1\njle loc_1F50\nloc_1EB0:\nmov edi, ebx\nmov [rsp+78h+var_48], r11d\nsub ebx, 1\nmov [rsp+78h+var_4C], esi\nmov [rsp+78h+var_50], r9d\nmov [rsp+78h+var_54], r10d\nmov [rsp+78h+var_58], r8d\nmov [rsp+78h+var_70], edx\ncall func0_part_0\nmov r8d, [rsp+78h+var_58]\nmov edx, [rsp+78h+var_70]\nmov r10d, [rsp+78h+var_54]\nmov r9d, [rsp+78h+var_50]\nimul eax, r8d\nmov esi, [rsp+78h+var_4C]\nmov r11d, [rsp+78h+var_48]\nadd edx, 1\nadd r15d, eax\nnop dword ptr [rax+00h]\nloc_1F00:\ncmp edx, 1\njz loc_2559\nmov edi, edx\nmov [rsp+78h+var_4C], r11d\nmov [rsp+78h+var_50], esi\nmov [rsp+78h+var_54], r9d\nmov [rsp+78h+var_58], r10d\nmov [rsp+78h+var_70], edx\ncall func0_part_0\nmov edx, [rsp+78h+var_70]\nmov r10d, [rsp+78h+var_58]\nmov r9d, [rsp+78h+var_54]\nmov esi, [rsp+78h+var_50]\nmov r8d, eax\nmov r11d, [rsp+78h+var_4C]\ncmp ebx, 1\njg loc_1EB0\nnop word ptr [rax+rax+00h]\nloc_1F50:\nadd r15d, r8d\nadd edx, 1\ntest ebx, ebx\njz loc_1D97\nxor ebx, ebx\njmp short loc_1F00\nloc_1F68:\nadd r12d, r15d\ntest r10d, r10d\njz loc_1B76\nadd r11d, 1\nxor r10d, r10d\njmp loc_1E8E\nloc_1F80:\nadd r9d, r12d\ntest r14d, r14d\njz short loc_1F98\nadd esi, 1\nxor r14d, r14d\njmp loc_1D7E\nloc_1F98:\nmov r15d, [rsp+78h+var_68]\nadd ebp, 1\nimul r15d, r9d\nadd [rsp+78h+var_6C], r15d\nloc_1FA9:\ncmp ebp, 1\njz loc_254E\nlea ebx, [rbp-1]\nxor r15d, r15d\nxor r12d, r12d\nmov r14d, 1\nloc_1FC1:\ncmp ebx, 1\njle loc_23D0\nlea edx, [rbx-1]\nxor r9d, r9d\nxor r8d, r8d\nmov ebx, 1\nmov [rsp+78h+var_70], edx\nmov r10d, edx\nloc_1FDF:\ncmp r10d, 1\njle loc_21B8\nlea edx, [r10-1]\nxor esi, esi\nxor r11d, r11d\nmov r10d, 1\nmov ecx, edx\nloc_1FFA:\ncmp ecx, 1\njle loc_20B8\nloc_2003:\nmov edi, ecx\nmov [rsp+78h+var_44], edx\nmov [rsp+78h+var_48], r9d\nmov [rsp+78h+var_4C], r8d\nmov [rsp+78h+var_50], r10d\nmov [rsp+78h+var_54], esi\nmov [rsp+78h+var_58], r11d\nmov [rsp+78h+var_68], ecx\ncall func0_part_0\nmov r10d, [rsp+78h+var_50]\nmov r11d, [rsp+78h+var_58]\nmov esi, [rsp+78h+var_54]\nmov ecx, [rsp+78h+var_68]\nimul eax, r10d\nmov r8d, [rsp+78h+var_4C]\nmov r9d, [rsp+78h+var_48]\nmov edx, [rsp+78h+var_44]\nadd esi, 1\nsub ecx, 1\nadd r11d, eax\nnop word ptr [rax+rax+00000000h]\nloc_2060:\ncmp esi, 1\njz loc_2543\nmov edi, esi\nmov [rsp+78h+var_48], edx\nmov [rsp+78h+var_4C], r9d\nmov [rsp+78h+var_50], r8d\nmov [rsp+78h+var_54], r11d\nmov [rsp+78h+var_58], ecx\nmov [rsp+78h+var_68], esi\ncall func0_part_0\nmov ecx, [rsp+78h+var_58]\nmov esi, [rsp+78h+var_68]\nmov r11d, [rsp+78h+var_54]\nmov r8d, [rsp+78h+var_50]\nmov r10d, eax\nmov r9d, [rsp+78h+var_4C]\nmov edx, [rsp+78h+var_48]\ncmp ecx, 1\njg loc_2003\nnop word ptr [rax+rax+00h]\nloc_20B8:\nadd r11d, r10d\nadd esi, 1\ntest ecx, ecx\njz short loc_20D0\nxor ecx, ecx\njmp short loc_2060\nloc_20D0:\nimul r11d, ebx\nadd r9d, 1\nmov r10d, edx\nadd r8d, r11d\nloc_20DE:\ncmp r9d, 1\njz loc_2539\nlea ecx, [r9-1]\nxor ebx, ebx\nxor esi, esi\nmov r11d, 1\nloc_20F6:\ncmp ecx, 1\njle loc_21A0\nloc_20FF:\nmov edi, ecx\nmov [rsp+78h+var_48], r9d\nmov [rsp+78h+var_4C], r8d\nmov [rsp+78h+var_50], r10d\nmov [rsp+78h+var_54], r11d\nmov [rsp+78h+var_58], esi\nmov [rsp+78h+var_68], ecx\ncall func0_part_0\nmov r11d, [rsp+78h+var_54]\nmov esi, [rsp+78h+var_58]\nmov ecx, [rsp+78h+var_68]\nmov r10d, [rsp+78h+var_50]\nimul eax, r11d\nmov r8d, [rsp+78h+var_4C]\nmov r9d, [rsp+78h+var_48]\nadd esi, 1\nsub ecx, 1\nadd ebx, eax\nnop word ptr [rax+rax+00h]\nloc_2150:\ncmp esi, 1\njz loc_252E\nmov edi, esi\nmov [rsp+78h+var_4C], r9d\nmov [rsp+78h+var_50], r8d\nmov [rsp+78h+var_54], r10d\nmov [rsp+78h+var_58], ecx\nmov [rsp+78h+var_68], esi\ncall func0_part_0\nmov ecx, [rsp+78h+var_58]\nmov esi, [rsp+78h+var_68]\nmov r10d, [rsp+78h+var_54]\nmov r8d, [rsp+78h+var_50]\nmov r11d, eax\nmov r9d, [rsp+78h+var_4C]\ncmp ecx, 1\njg loc_20FF\nnop word ptr [rax+rax+00h]\nloc_21A0:\nadd ebx, r11d\nadd esi, 1\ntest ecx, ecx\njz loc_1FDF\nxor ecx, ecx\njmp short loc_2150\nloc_21B8:\nadd r8d, ebx\ntest r10d, r10d\njz short loc_21D0\nadd r9d, 1\nxor r10d, r10d\njmp loc_20DE\nloc_21D0:\nimul r8d, r14d\nmov edx, [rsp+78h+var_70]\nadd r12d, 1\nmov ebx, edx\nadd r15d, r8d\nloc_21E1:\ncmp r12d, 1\njz loc_2523\nlea r8d, [r12-1]\nxor r14d, r14d\nxor r9d, r9d\nmov esi, 1\nloc_21FB:\ncmp r8d, 1\njle loc_23B8\nsub r8d, 1\nxor r10d, r10d\nxor ecx, ecx\nmov r11d, 1\nmov edx, r8d\nloc_2217:\ncmp edx, 1\njle loc_22D0\nloc_2220:\nmov edi, edx\nmov [rsp+78h+var_48], r8d\nmov [rsp+78h+var_4C], r9d\nmov [rsp+78h+var_50], r11d\nmov [rsp+78h+var_54], ecx\nmov [rsp+78h+var_58], r10d\nmov [rsp+78h+var_68], esi\nmov [rsp+78h+var_70], edx\ncall func0_part_0\nmov r11d, [rsp+78h+var_50]\nmov r10d, [rsp+78h+var_58]\nmov ecx, [rsp+78h+var_54]\nmov edx, [rsp+78h+var_70]\nimul eax, r11d\nmov esi, [rsp+78h+var_68]\nmov r9d, [rsp+78h+var_4C]\nmov r8d, [rsp+78h+var_48]\nadd ecx, 1\nsub edx, 1\nadd r10d, eax\nnop dword ptr [rax+00h]\nloc_2278:\ncmp ecx, 1\njz loc_2518\nmov edi, ecx\nmov [rsp+78h+var_4C], r8d\nmov [rsp+78h+var_50], r9d\nmov [rsp+78h+var_54], r10d\nmov [rsp+78h+var_58], esi\nmov [rsp+78h+var_68], edx\nmov [rsp+78h+var_70], ecx\ncall func0_part_0\nmov edx, [rsp+78h+var_68]\nmov ecx, [rsp+78h+var_70]\nmov esi, [rsp+78h+var_58]\nmov r10d, [rsp+78h+var_54]\nmov r11d, eax\nmov r9d, [rsp+78h+var_50]\nmov r8d, [rsp+78h+var_4C]\ncmp edx, 1\njg loc_2220\nnop word ptr [rax+rax+00h]\nloc_22D0:\nadd r10d, r11d\nadd ecx, 1\ntest edx, edx\njz short loc_22E0\nxor edx, edx\njmp short loc_2278\nloc_22E0:\nimul r10d, esi\nadd r9d, 1\nadd r14d, r10d\nloc_22EB:\ncmp r9d, 1\njz loc_250E\nlea edx, [r9-1]\nxor ecx, ecx\nxor esi, esi\nmov r10d, 1\nloc_2303:\ncmp edx, 1\njle loc_23A0\nloc_230C:\nmov edi, edx\nmov [rsp+78h+var_4C], r9d\nmov [rsp+78h+var_50], r8d\nmov [rsp+78h+var_54], r10d\nmov [rsp+78h+var_58], ecx\nmov [rsp+78h+var_68], esi\nmov [rsp+78h+var_70], edx\ncall func0_part_0\nmov r10d, [rsp+78h+var_54]\nmov esi, [rsp+78h+var_68]\nmov ecx, [rsp+78h+var_58]\nmov edx, [rsp+78h+var_70]\nimul eax, r10d\nmov r8d, [rsp+78h+var_50]\nmov r9d, [rsp+78h+var_4C]\nadd ecx, 1\nsub edx, 1\nadd esi, eax\nnop dword ptr [rax]\nloc_2358:\ncmp ecx, 1\njz loc_2503\nmov edi, ecx\nmov [rsp+78h+var_50], r9d\nmov [rsp+78h+var_54], r8d\nmov [rsp+78h+var_58], edx\nmov [rsp+78h+var_68], esi\nmov [rsp+78h+var_70], ecx\ncall func0_part_0\nmov edx, [rsp+78h+var_58]\nmov ecx, [rsp+78h+var_70]\nmov esi, [rsp+78h+var_68]\nmov r8d, [rsp+78h+var_54]\nmov r10d, eax\nmov r9d, [rsp+78h+var_50]\ncmp edx, 1\njg loc_230C\nloc_23A0:\nadd esi, r10d\nadd ecx, 1\ntest edx, edx\njz loc_21FB\nxor edx, edx\njmp short loc_2358\nloc_23B8:\nadd r14d, esi\ntest r8d, r8d\njz loc_1FC1\nadd r9d, 1\nxor r8d, r8d\njmp loc_22EB\nloc_23D0:\nadd r15d, r14d\ntest ebx, ebx\njz loc_1B53\nadd r12d, 1\nxor ebx, ebx\njmp loc_21E1\nloc_23F0:\nadd [rsp+78h+var_6C], r15d\ntest r13d, r13d\njz short loc_2405\nadd ebp, 1\nxor r13d, r13d\njmp loc_1FA9\nloc_2405:\nmov r12d, [rsp+78h+var_64]\ncmp r12d, 1\njg loc_122E\nloc_2414:\nmov edi, [rsp+78h+var_6C]\nadd [rsp+78h+var_5C], edi\ntest r12d, r12d\njz short loc_2441\nadd [rsp+78h+var_60], 1\nxor r12d, r12d\ncmp [rsp+78h+var_60], 1\njnz loc_1B2B\nloc_2434:\nmov [rsp+78h+var_6C], 1\njmp loc_1224\nloc_2441:\nmov eax, [rsp+78h+var_5C]\nadd rsp, 48h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_2454:\nmov r11d, 1\njmp loc_1BB3\nloc_245F:\nmov r10d, 1\njmp loc_1A03\nloc_246A:\nmov esi, 1\njmp loc_18F9\nloc_2474:\nmov r11d, 1\njmp loc_1915\nloc_247F:\nmov r14d, 1\njmp loc_16C1\nloc_248A:\nmov r11d, 1\njmp loc_17F7\nloc_2495:\nmov r12d, 1\njmp loc_16E3\nloc_24A0:\nmov r10d, 1\njmp loc_16FE\nloc_24AB:\nmov r15d, 1\njmp loc_1254\nloc_24B6:\nmov r8d, 1\njmp loc_15A7\nloc_24C1:\nmov r15d, 1\njmp loc_1497\nloc_24CC:\nmov r10d, 1\njmp loc_14B2\nloc_24D7:\nmov r12d, 1\njmp loc_1277\nloc_24E2:\nmov r8d, 1\njmp loc_13A1\nloc_24ED:\nmov r15d, 1\njmp loc_129B\nloc_24F8:\nmov r11d, 1\njmp loc_12B4\nloc_2503:\nmov r10d, 1\njmp loc_2303\nloc_250E:\nmov esi, 1\njmp loc_21FB\nloc_2518:\nmov r11d, 1\njmp loc_2217\nloc_2523:\nmov r14d, 1\njmp loc_1FC1\nloc_252E:\nmov r11d, 1\njmp loc_20F6\nloc_2539:\nmov ebx, 1\njmp loc_1FDF\nloc_2543:\nmov r10d, 1\njmp loc_1FFA\nloc_254E:\nmov r15d, 1\njmp loc_1B53\nloc_2559:\nmov r8d, 1\njmp loc_1EA7\nloc_2564:\nmov r15d, 1\njmp loc_1D97\nloc_256F:\nmov r10d, 1\njmp loc_1DB2\nloc_257A:\nmov r12d, 1\njmp loc_1B76\nloc_2585:\nmov r8d, 1\njmp loc_1CA1\nloc_2590:\nmov r15d, 1\njmp loc_1B9A", + "ida_pseudo": "__int64 __fastcall func0_part_0(int a1)\n{\n int v1; // r12d\n int v2; // ebp\n int v3; // r15d\n int v4; // r13d\n int v5; // esi\n int v6; // r14d\n int v7; // r12d\n int v8; // r9d\n int v9; // r10d\n int v10; // edx\n int v11; // r15d\n int v12; // esi\n unsigned int v13; // ecx\n int v14; // r8d\n int v15; // r11d\n int v16; // ebx\n __int64 v17; // rdi\n int v18; // eax\n int v19; // eax\n int v20; // ebx\n unsigned int v21; // ecx\n int v22; // r8d\n __int64 v23; // rdi\n int v24; // eax\n int v25; // eax\n int v26; // r10d\n int v27; // r11d\n int v28; // r15d\n int v29; // ecx\n int v30; // r8d\n unsigned int v31; // edx\n int v32; // r10d\n int v33; // ebx\n __int64 v34; // rdi\n int v35; // eax\n int v36; // eax\n int v37; // ebx\n unsigned int v38; // edx\n int v39; // r8d\n __int64 v40; // rdi\n int v41; // eax\n int v42; // eax\n int v43; // r12d\n int v44; // ebx\n int i; // r14d\n int v46; // edx\n int v47; // r8d\n int v48; // r9d\n int v49; // r12d\n int v50; // r10d\n int v51; // edx\n int v52; // r11d\n unsigned int v53; // esi\n int v54; // r10d\n int v55; // ecx\n int v56; // eax\n int v57; // eax\n int v58; // ecx\n unsigned int v59; // esi\n int v60; // r11d\n int v61; // eax\n int v62; // eax\n int v63; // r8d\n int v64; // r9d\n int v65; // esi\n int v66; // r10d\n unsigned int v67; // ecx\n int v68; // r11d\n int v69; // edx\n int v70; // eax\n int v71; // eax\n int v72; // edx\n unsigned int v73; // ecx\n int v74; // r10d\n int v75; // eax\n int v76; // eax\n int v77; // ebp\n int v78; // r15d\n int v79; // r13d\n int v80; // esi\n int v81; // r14d\n int v82; // r12d\n int v83; // r9d\n int v84; // r10d\n int v85; // edx\n int v86; // r15d\n int v87; // esi\n int v88; // r8d\n unsigned int v89; // ecx\n int v90; // r11d\n int v91; // ebx\n __int64 v92; // rdi\n int v93; // eax\n int v94; // eax\n int v95; // ebx\n unsigned int v96; // ecx\n int v97; // r8d\n __int64 v98; // rdi\n int v99; // eax\n int v100; // eax\n int v101; // r10d\n int v102; // r11d\n int v103; // r15d\n int v104; // ecx\n int v105; // r8d\n unsigned int v106; // edx\n int v107; // r10d\n int v108; // ebx\n __int64 v109; // rdi\n int v110; // eax\n int v111; // eax\n int v112; // ebx\n unsigned int v113; // edx\n int v114; // r8d\n __int64 v115; // rdi\n int v116; // eax\n int v117; // eax\n int v118; // ebx\n int v119; // r12d\n int j; // r14d\n int v121; // edx\n int v122; // r9d\n int v123; // r8d\n int v124; // ebx\n int v125; // r10d\n int v126; // edx\n unsigned int v127; // esi\n int v128; // r11d\n int v129; // r10d\n int v130; // ecx\n int v131; // eax\n int v132; // eax\n int v133; // ecx\n unsigned int v134; // esi\n int v135; // r11d\n int v136; // eax\n int v137; // eax\n int v138; // r8d\n int v139; // r9d\n int v140; // esi\n int v141; // r10d\n unsigned int v142; // ecx\n int v143; // r11d\n int v144; // edx\n int v145; // eax\n int v146; // eax\n int v147; // edx\n unsigned int v148; // ecx\n int v149; // r10d\n int v150; // eax\n int v151; // eax\n int v153; // [rsp+8h] [rbp-70h]\n int v154; // [rsp+8h] [rbp-70h]\n unsigned int v155; // [rsp+8h] [rbp-70h]\n int v156; // [rsp+8h] [rbp-70h]\n unsigned int v157; // [rsp+8h] [rbp-70h]\n int v158; // [rsp+8h] [rbp-70h]\n int v159; // [rsp+8h] [rbp-70h]\n unsigned int v160; // [rsp+8h] [rbp-70h]\n int v161; // [rsp+8h] [rbp-70h]\n unsigned int v162; // [rsp+8h] [rbp-70h]\n int v163; // [rsp+8h] [rbp-70h]\n int v164; // [rsp+8h] [rbp-70h]\n unsigned int v165; // [rsp+8h] [rbp-70h]\n unsigned int v166; // [rsp+8h] [rbp-70h]\n unsigned int v167; // [rsp+8h] [rbp-70h]\n int v168; // [rsp+8h] [rbp-70h]\n int v169; // [rsp+8h] [rbp-70h]\n unsigned int v170; // [rsp+8h] [rbp-70h]\n int v171; // [rsp+8h] [rbp-70h]\n unsigned int v172; // [rsp+8h] [rbp-70h]\n int v173; // [rsp+Ch] [rbp-6Ch]\n int v174; // [rsp+10h] [rbp-68h]\n int v175; // [rsp+10h] [rbp-68h]\n int v176; // [rsp+10h] [rbp-68h]\n int v177; // [rsp+10h] [rbp-68h]\n int v178; // [rsp+10h] [rbp-68h]\n int v179; // [rsp+14h] [rbp-64h]\n int v180; // [rsp+14h] [rbp-64h]\n int v181; // [rsp+14h] [rbp-64h]\n int v182; // [rsp+14h] [rbp-64h]\n int v183; // [rsp+14h] [rbp-64h]\n int v184; // [rsp+14h] [rbp-64h]\n int v185; // [rsp+18h] [rbp-60h]\n unsigned int v186; // [rsp+1Ch] [rbp-5Ch]\n int v187; // [rsp+20h] [rbp-58h]\n int v188; // [rsp+20h] [rbp-58h]\n unsigned int v189; // [rsp+20h] [rbp-58h]\n unsigned int v190; // [rsp+20h] [rbp-58h]\n unsigned int v191; // [rsp+20h] [rbp-58h]\n unsigned int v192; // [rsp+20h] [rbp-58h]\n int v193; // [rsp+20h] [rbp-58h]\n int v194; // [rsp+20h] [rbp-58h]\n int v195; // [rsp+20h] [rbp-58h]\n int v196; // [rsp+20h] [rbp-58h]\n int v197; // [rsp+20h] [rbp-58h]\n int v198; // [rsp+20h] [rbp-58h]\n int v199; // [rsp+20h] [rbp-58h]\n unsigned int v200; // [rsp+20h] [rbp-58h]\n int v201; // [rsp+20h] [rbp-58h]\n int v202; // [rsp+24h] [rbp-54h]\n unsigned int v203; // [rsp+24h] [rbp-54h]\n int v204; // [rsp+24h] [rbp-54h]\n unsigned int v205; // [rsp+24h] [rbp-54h]\n unsigned int v206; // [rsp+24h] [rbp-54h]\n int v207; // [rsp+24h] [rbp-54h]\n unsigned int v208; // [rsp+24h] [rbp-54h]\n int v209; // [rsp+24h] [rbp-54h]\n int v210; // [rsp+24h] [rbp-54h]\n int v211; // [rsp+24h] [rbp-54h]\n int v212; // [rsp+24h] [rbp-54h]\n int v213; // [rsp+24h] [rbp-54h]\n unsigned int v214; // [rsp+24h] [rbp-54h]\n unsigned int v215; // [rsp+24h] [rbp-54h]\n int v216; // [rsp+24h] [rbp-54h]\n int v217; // [rsp+24h] [rbp-54h]\n int v218; // [rsp+24h] [rbp-54h]\n int v219; // [rsp+24h] [rbp-54h]\n int v220; // [rsp+24h] [rbp-54h]\n int v221; // [rsp+24h] [rbp-54h]\n int v222; // [rsp+24h] [rbp-54h]\n int v223; // [rsp+24h] [rbp-54h]\n int v224; // [rsp+24h] [rbp-54h]\n int v225; // [rsp+24h] [rbp-54h]\n unsigned int v226; // [rsp+24h] [rbp-54h]\n int v227; // [rsp+24h] [rbp-54h]\n int v228; // [rsp+24h] [rbp-54h]\n int v229; // [rsp+24h] [rbp-54h]\n int v230; // [rsp+28h] [rbp-50h]\n int v231; // [rsp+28h] [rbp-50h]\n unsigned int v232; // [rsp+28h] [rbp-50h]\n int v233; // [rsp+28h] [rbp-50h]\n int v234; // [rsp+28h] [rbp-50h]\n int v235; // [rsp+28h] [rbp-50h]\n int v236; // [rsp+28h] [rbp-50h]\n int v237; // [rsp+28h] [rbp-50h]\n int v238; // [rsp+28h] [rbp-50h]\n unsigned int v239; // [rsp+28h] [rbp-50h]\n int v240; // [rsp+28h] [rbp-50h]\n int v241; // [rsp+28h] [rbp-50h]\n int v242; // [rsp+28h] [rbp-50h]\n int v243; // [rsp+28h] [rbp-50h]\n int v244; // [rsp+28h] [rbp-50h]\n int v245; // [rsp+28h] [rbp-50h]\n int v246; // [rsp+28h] [rbp-50h]\n int v247; // [rsp+28h] [rbp-50h]\n int v248; // [rsp+28h] [rbp-50h]\n int v249; // [rsp+28h] [rbp-50h]\n int v250; // [rsp+28h] [rbp-50h]\n int v251; // [rsp+28h] [rbp-50h]\n int v252; // [rsp+28h] [rbp-50h]\n int v253; // [rsp+28h] [rbp-50h]\n int v254; // [rsp+28h] [rbp-50h]\n int v255; // [rsp+28h] [rbp-50h]\n int v256; // [rsp+28h] [rbp-50h]\n unsigned int v257; // [rsp+2Ch] [rbp-4Ch]\n int v258; // [rsp+2Ch] [rbp-4Ch]\n int v259; // [rsp+2Ch] [rbp-4Ch]\n int v260; // [rsp+2Ch] [rbp-4Ch]\n int v261; // [rsp+2Ch] [rbp-4Ch]\n int v262; // [rsp+2Ch] [rbp-4Ch]\n int v263; // [rsp+2Ch] [rbp-4Ch]\n int v264; // [rsp+2Ch] [rbp-4Ch]\n int v265; // [rsp+2Ch] [rbp-4Ch]\n int v266; // [rsp+2Ch] [rbp-4Ch]\n int v267; // [rsp+2Ch] [rbp-4Ch]\n int v268; // [rsp+2Ch] [rbp-4Ch]\n int v269; // [rsp+2Ch] [rbp-4Ch]\n int v270; // [rsp+2Ch] [rbp-4Ch]\n int v271; // [rsp+2Ch] [rbp-4Ch]\n int v272; // [rsp+2Ch] [rbp-4Ch]\n int v273; // [rsp+2Ch] [rbp-4Ch]\n int v274; // [rsp+2Ch] [rbp-4Ch]\n int v275; // [rsp+2Ch] [rbp-4Ch]\n int v276; // [rsp+2Ch] [rbp-4Ch]\n int v277; // [rsp+2Ch] [rbp-4Ch]\n int v278; // [rsp+2Ch] [rbp-4Ch]\n int v279; // [rsp+2Ch] [rbp-4Ch]\n int v280; // [rsp+2Ch] [rbp-4Ch]\n int v281; // [rsp+2Ch] [rbp-4Ch]\n int v282; // [rsp+30h] [rbp-48h]\n int v283; // [rsp+30h] [rbp-48h]\n int v284; // [rsp+30h] [rbp-48h]\n int v285; // [rsp+30h] [rbp-48h]\n int v286; // [rsp+30h] [rbp-48h]\n int v287; // [rsp+30h] [rbp-48h]\n int v288; // [rsp+30h] [rbp-48h]\n int v289; // [rsp+30h] [rbp-48h]\n int v290; // [rsp+30h] [rbp-48h]\n int v291; // [rsp+30h] [rbp-48h]\n int v292; // [rsp+30h] [rbp-48h]\n int v293; // [rsp+30h] [rbp-48h]\n int v294; // [rsp+30h] [rbp-48h]\n int v295; // [rsp+30h] [rbp-48h]\n int v296; // [rsp+30h] [rbp-48h]\n int v297; // [rsp+30h] [rbp-48h]\n int v298; // [rsp+30h] [rbp-48h]\n int v299; // [rsp+30h] [rbp-48h]\n int v300; // [rsp+30h] [rbp-48h]\n int v301; // [rsp+30h] [rbp-48h]\n int v302; // [rsp+30h] [rbp-48h]\n int v303; // [rsp+30h] [rbp-48h]\n int v304; // [rsp+30h] [rbp-48h]\n int v305; // [rsp+30h] [rbp-48h]\n int v306; // [rsp+34h] [rbp-44h]\n int v307; // [rsp+34h] [rbp-44h]\n int v308; // [rsp+34h] [rbp-44h]\n int v309; // [rsp+34h] [rbp-44h]\n int v310; // [rsp+34h] [rbp-44h]\n int v311; // [rsp+34h] [rbp-44h]\n int v312; // [rsp+34h] [rbp-44h]\n int v313; // [rsp+34h] [rbp-44h]\n int v314; // [rsp+34h] [rbp-44h]\n int v315; // [rsp+34h] [rbp-44h]\n int v316; // [rsp+34h] [rbp-44h]\n int v317; // [rsp+34h] [rbp-44h]\n int v318; // [rsp+34h] [rbp-44h]\n int v319; // [rsp+34h] [rbp-44h]\n int v320; // [rsp+38h] [rbp-40h]\n int v321; // [rsp+38h] [rbp-40h]\n int v322; // [rsp+38h] [rbp-40h]\n int v323; // [rsp+38h] [rbp-40h]\n int v324; // [rsp+3Ch] [rbp-3Ch]\n\n v186 = 0;\n if ( a1 <= 0 )\n return v186;\n v185 = 0;\n v173 = 1;\n v1 = a1 - 1;\nLABEL_3:\n if ( v1 <= 1 )\n goto LABEL_202;\n do\n {\n v174 = 0;\n v187 = v1 - 1;\n v2 = 0;\n v3 = 1;\n v4 = v1 - 1;\n while ( 1 )\n {\n if ( v4 > 1 )\n {\n v179 = v3;\n --v4;\n v5 = 0;\n v6 = v4;\n v7 = 1;\n v8 = 0;\n while ( 1 )\n {\nLABEL_7:\n if ( v6 > 1 )\n {\n --v6;\n v153 = v5;\n v9 = 0;\n v10 = v6;\n v11 = 1;\n v12 = 0;\n while ( 1 )\n {\n if ( v10 <= 1 )\n {\n v9 += v11;\n if ( !v10 )\n {\n v5 = v153 + 1;\n v8 += v7 * v9;\n goto LABEL_29;\n }\n ++v12;\n v10 = 0;\n }\n else\n {\n --v10;\n v13 = 0;\n v14 = 0;\n v15 = 1;\n v16 = v10;\nLABEL_11:\n if ( v16 > 1 )\n {\nLABEL_12:\n v17 = (unsigned int)v16;\n v324 = v10;\n --v16;\n v306 = v9;\n v282 = v8;\n v257 = v13;\n v230 = v14;\n v202 = v15;\n v18 = func0_part_0(v17);\n v8 = v282;\n v9 = v306;\n v10 = v324;\n v13 = v257 + 1;\n v14 = v202 * v18 + v230;\n goto LABEL_13;\n }\n while ( 1 )\n {\n v14 += v15;\n ++v13;\n if ( !v16 )\n break;\n v16 = 0;\nLABEL_13:\n if ( v13 == 1 )\n {\n v15 = 1;\n goto LABEL_11;\n }\n v320 = v10;\n v283 = v9;\n v258 = v8;\n v231 = v14;\n v203 = v13;\n v19 = func0_part_0(v13);\n v13 = v203;\n v14 = v231;\n v8 = v258;\n v9 = v283;\n v15 = v19;\n v10 = v320;\n if ( v16 > 1 )\n goto LABEL_12;\n }\n ++v12;\n v9 += v11 * v14;\n }\n if ( v12 == 1 )\n {\n v11 = 1;\n }\n else\n {\n v20 = v12 - 1;\n v11 = 0;\n v21 = 0;\n v22 = 1;\nLABEL_20:\n if ( v20 > 1 )\n {\nLABEL_21:\n v23 = (unsigned int)v20--;\n v307 = v10;\n v284 = v9;\n v259 = v8;\n v232 = v21;\n v204 = v22;\n v24 = func0_part_0(v23);\n v8 = v259;\n v9 = v284;\n v10 = v307;\n v21 = v232 + 1;\n v11 += v204 * v24;\n goto LABEL_22;\n }\n while ( 1 )\n {\n v11 += v22;\n ++v21;\n if ( !v20 )\n break;\n v20 = 0;\nLABEL_22:\n if ( v21 == 1 )\n {\n v22 = 1;\n goto LABEL_20;\n }\n v285 = v10;\n v260 = v9;\n v233 = v8;\n v205 = v21;\n v25 = func0_part_0(v21);\n v21 = v205;\n v8 = v233;\n v9 = v260;\n v10 = v285;\n v22 = v25;\n if ( v20 > 1 )\n goto LABEL_21;\n }\n }\n }\n }\n v8 += v7;\n if ( !v6 )\n break;\n ++v5;\n v6 = 0;\nLABEL_29:\n if ( v5 != 1 )\n {\n v26 = v5 - 1;\n v7 = 0;\n v27 = 0;\n v28 = 1;\n while ( 1 )\n {\n if ( v26 <= 1 )\n {\n v7 += v28;\n if ( !v26 )\n goto LABEL_7;\n ++v27;\n v26 = 0;\n }\n else\n {\n v29 = v26 - 1;\n v30 = 0;\n v31 = 0;\n v32 = 1;\n v33 = v29;\nLABEL_33:\n if ( v33 > 1 )\n {\nLABEL_34:\n v34 = (unsigned int)v33;\n v321 = v29;\n --v33;\n v308 = v27;\n v286 = v8;\n v234 = v32;\n v206 = v31;\n v154 = v30;\n v35 = func0_part_0(v34);\n v8 = v286;\n v27 = v308;\n v29 = v321;\n v31 = v206 + 1;\n v30 = v234 * v35 + v154;\n goto LABEL_35;\n }\n while ( 1 )\n {\n v30 += v32;\n ++v31;\n if ( !v33 )\n break;\n v33 = 0;\nLABEL_35:\n if ( v31 == 1 )\n {\n v32 = 1;\n goto LABEL_33;\n }\n v309 = v29;\n v287 = v27;\n v261 = v8;\n v207 = v30;\n v155 = v31;\n v36 = func0_part_0(v31);\n v31 = v155;\n v30 = v207;\n v8 = v261;\n v32 = v36;\n v27 = v287;\n v29 = v309;\n if ( v33 > 1 )\n goto LABEL_34;\n }\n ++v27;\n v26 = v29;\n v7 += v28 * v30;\n }\n if ( v27 == 1 )\n {\n v28 = 1;\n }\n else\n {\n v37 = v27 - 1;\n v38 = 0;\n v28 = 0;\n v39 = 1;\nLABEL_42:\n if ( v37 > 1 )\n {\nLABEL_43:\n v40 = (unsigned int)v37;\n v310 = v26;\n --v37;\n v288 = v27;\n v262 = v8;\n v208 = v38;\n v156 = v39;\n v41 = func0_part_0(v40);\n v8 = v262;\n v27 = v288;\n v26 = v310;\n v38 = v208 + 1;\n v28 += v156 * v41;\n goto LABEL_44;\n }\n while ( 1 )\n {\n v28 += v39;\n ++v38;\n if ( !v37 )\n break;\n v37 = 0;\nLABEL_44:\n if ( v38 == 1 )\n {\n v39 = 1;\n goto LABEL_42;\n }\n v289 = v26;\n v263 = v27;\n v235 = v8;\n v157 = v38;\n v42 = func0_part_0(v38);\n v38 = v157;\n v8 = v235;\n v27 = v263;\n v39 = v42;\n v26 = v289;\n if ( v37 > 1 )\n goto LABEL_43;\n }\n }\n }\n }\n v7 = 1;\n }\n ++v2;\n v174 += v8 * v179;\n goto LABEL_53;\n }\n v174 += v3;\n if ( !v4 )\n break;\n ++v2;\n v4 = 0;\nLABEL_53:\n if ( v2 == 1 )\n {\n v3 = 1;\n }\n else\n {\n v43 = v2 - 1;\n v3 = 0;\n v44 = 0;\n for ( i = 1; ; i = 1 )\n {\nLABEL_55:\n if ( v43 > 1 )\n {\n v46 = v43 - 1;\n v47 = 0;\n v48 = 0;\n v49 = 1;\n v158 = v46;\n v50 = v46;\n while ( 1 )\n {\n if ( v50 <= 1 )\n {\n v47 += v49;\n if ( !v50 )\n {\n ++v44;\n v43 = v158;\n v3 += i * v47;\n goto LABEL_77;\n }\n ++v48;\n v50 = 0;\n }\n else\n {\n v51 = v50 - 1;\n v52 = 0;\n v53 = 0;\n v54 = 1;\n v55 = v51;\nLABEL_59:\n if ( v55 > 1 )\n {\nLABEL_60:\n v322 = v51;\n v311 = v47;\n v290 = v48;\n v236 = v52;\n v209 = v54;\n v180 = v55;\n v56 = func0_part_0((unsigned int)v55);\n v48 = v290;\n v47 = v311;\n v51 = v322;\n ++v53;\n v55 = v180 - 1;\n v52 = v209 * v56 + v236;\n goto LABEL_61;\n }\n while ( 1 )\n {\n v52 += v54;\n ++v53;\n if ( !v55 )\n break;\n v55 = 0;\nLABEL_61:\n if ( v53 == 1 )\n {\n v54 = 1;\n goto LABEL_59;\n }\n v312 = v51;\n v291 = v47;\n v264 = v48;\n v237 = v55;\n v210 = v52;\n v57 = func0_part_0(v53);\n v55 = v237;\n v52 = v210;\n v48 = v264;\n v54 = v57;\n v47 = v291;\n v51 = v312;\n if ( v237 > 1 )\n goto LABEL_60;\n }\n ++v48;\n v50 = v51;\n v47 += v49 * v52;\n }\n if ( v48 == 1 )\n {\n v49 = 1;\n }\n else\n {\n v58 = v48 - 1;\n v49 = 0;\n v59 = 0;\n v60 = 1;\nLABEL_68:\n if ( v58 > 1 )\n {\nLABEL_69:\n v313 = v50;\n v292 = v47;\n v265 = v48;\n v211 = v60;\n v181 = v58;\n v61 = func0_part_0((unsigned int)v58);\n v48 = v265;\n v47 = v292;\n v50 = v313;\n ++v59;\n v58 = v181 - 1;\n v49 += v211 * v61;\n goto LABEL_70;\n }\n while ( 1 )\n {\n v49 += v60;\n ++v59;\n if ( !v58 )\n break;\n v58 = 0;\nLABEL_70:\n if ( v59 == 1 )\n {\n v60 = 1;\n goto LABEL_68;\n }\n v293 = v50;\n v266 = v47;\n v238 = v48;\n v212 = v58;\n v62 = func0_part_0(v59);\n v58 = v212;\n v48 = v238;\n v47 = v266;\n v60 = v62;\n v50 = v293;\n if ( v212 > 1 )\n goto LABEL_69;\n }\n }\n }\n }\n v3 += i;\n if ( !v43 )\n break;\n ++v44;\n v43 = 0;\nLABEL_77:\n if ( v44 != 1 )\n {\n v63 = v44 - 1;\n i = 0;\n v64 = 0;\n v65 = 1;\n while ( 1 )\n {\n if ( v63 <= 1 )\n {\n i += v65;\n if ( !v63 )\n goto LABEL_55;\n ++v64;\n v63 = 0;\n }\n else\n {\n --v63;\n v66 = 0;\n v67 = 0;\n v68 = 1;\n v69 = v63;\nLABEL_81:\n if ( v69 > 1 )\n {\nLABEL_82:\n v314 = v63;\n v294 = v64;\n v267 = v68;\n v239 = v67;\n v213 = v66;\n v159 = v69;\n v70 = func0_part_0((unsigned int)v69);\n v64 = v294;\n v63 = v314;\n v67 = v239 + 1;\n v69 = v159 - 1;\n v66 = v267 * v70 + v213;\n goto LABEL_83;\n }\n while ( 1 )\n {\n v66 += v68;\n ++v67;\n if ( !v69 )\n break;\n v69 = 0;\nLABEL_83:\n if ( v67 == 1 )\n {\n v68 = 1;\n goto LABEL_81;\n }\n v295 = v63;\n v268 = v64;\n v240 = v66;\n v182 = v69;\n v160 = v67;\n v71 = func0_part_0(v67);\n v69 = v182;\n v67 = v160;\n v66 = v240;\n v68 = v71;\n v64 = v268;\n v63 = v295;\n if ( v182 > 1 )\n goto LABEL_82;\n }\n ++v64;\n i += v65 * v66;\n }\n if ( v64 == 1 )\n {\n v65 = 1;\n }\n else\n {\n v72 = v64 - 1;\n v65 = 0;\n v73 = 0;\n v74 = 1;\nLABEL_90:\n if ( v72 > 1 )\n {\nLABEL_91:\n v296 = v63;\n v269 = v64;\n v241 = v74;\n v214 = v73;\n v161 = v72;\n v75 = func0_part_0((unsigned int)v72);\n v64 = v269;\n v63 = v296;\n v73 = v214 + 1;\n v72 = v161 - 1;\n v65 += v241 * v75;\n goto LABEL_92;\n }\n while ( 1 )\n {\n v65 += v74;\n ++v73;\n if ( !v72 )\n break;\n v72 = 0;\nLABEL_92:\n if ( v73 == 1 )\n {\n v74 = 1;\n goto LABEL_90;\n }\n v270 = v63;\n v242 = v64;\n v183 = v72;\n v162 = v73;\n v76 = func0_part_0(v73);\n v72 = v183;\n v73 = v162;\n v64 = v242;\n v74 = v76;\n v63 = v270;\n if ( v183 > 1 )\n goto LABEL_91;\n }\n }\n }\n }\n }\n }\n }\n ++v185;\n v186 += v174 * v173;\n v1 = v187;\n if ( v185 == 1 )\n {\nLABEL_204:\n v173 = 1;\n goto LABEL_3;\n }\nLABEL_103:\n v173 = 0;\n v184 = v1;\n v77 = 0;\n v78 = 1;\n v79 = v185 - 1;\n while ( 2 )\n {\n if ( v79 > 1 )\n {\n v175 = v78;\n --v79;\n v80 = 0;\n v81 = v79;\n v82 = 1;\n v83 = 0;\n while ( 1 )\n {\nLABEL_106:\n if ( v81 > 1 )\n {\n --v81;\n v163 = v80;\n v84 = 0;\n v85 = v81;\n v86 = 1;\n v87 = 0;\n while ( 1 )\n {\n if ( v85 <= 1 )\n {\n v84 += v86;\n if ( !v85 )\n {\n v80 = v163 + 1;\n v83 += v82 * v84;\n goto LABEL_128;\n }\n ++v87;\n v85 = 0;\n }\n else\n {\n --v85;\n v88 = 0;\n v89 = 0;\n v90 = 1;\n v91 = v85;\nLABEL_110:\n if ( v91 > 1 )\n {\nLABEL_111:\n v92 = (unsigned int)v91;\n v323 = v85;\n --v91;\n v315 = v84;\n v271 = v83;\n v243 = v90;\n v215 = v89;\n v188 = v88;\n v93 = func0_part_0(v92);\n v83 = v271;\n v84 = v315;\n v85 = v323;\n v89 = v215 + 1;\n v88 = v243 * v93 + v188;\n goto LABEL_112;\n }\n while ( 1 )\n {\n v88 += v90;\n ++v89;\n if ( !v91 )\n break;\n v91 = 0;\nLABEL_112:\n if ( v89 == 1 )\n {\n v90 = 1;\n goto LABEL_110;\n }\n v316 = v85;\n v297 = v84;\n v244 = v83;\n v216 = v88;\n v189 = v89;\n v94 = func0_part_0(v89);\n v89 = v189;\n v88 = v216;\n v83 = v244;\n v90 = v94;\n v84 = v297;\n v85 = v316;\n if ( v91 > 1 )\n goto LABEL_111;\n }\n ++v87;\n v84 += v86 * v88;\n }\n if ( v87 == 1 )\n {\n v86 = 1;\n }\n else\n {\n v95 = v87 - 1;\n v86 = 0;\n v96 = 0;\n v97 = 1;\nLABEL_119:\n if ( v95 > 1 )\n {\nLABEL_120:\n v98 = (unsigned int)v95;\n v317 = v84;\n --v95;\n v272 = v85;\n v245 = v83;\n v217 = v97;\n v190 = v96;\n v99 = func0_part_0(v98);\n v83 = v245;\n v85 = v272;\n v84 = v317;\n v96 = v190 + 1;\n v86 += v217 * v99;\n goto LABEL_121;\n }\n while ( 1 )\n {\n v86 += v97;\n ++v96;\n if ( !v95 )\n break;\n v95 = 0;\nLABEL_121:\n if ( v96 == 1 )\n {\n v97 = 1;\n goto LABEL_119;\n }\n v298 = v84;\n v246 = v85;\n v218 = v83;\n v191 = v96;\n v100 = func0_part_0(v96);\n v96 = v191;\n v83 = v218;\n v85 = v246;\n v97 = v100;\n v84 = v298;\n if ( v95 > 1 )\n goto LABEL_120;\n }\n }\n }\n }\n v83 += v82;\n if ( !v81 )\n break;\n ++v80;\n v81 = 0;\nLABEL_128:\n if ( v80 != 1 )\n {\n v101 = v80 - 1;\n v102 = 0;\n v82 = 0;\n v103 = 1;\n while ( 1 )\n {\n if ( v101 <= 1 )\n {\n v82 += v103;\n if ( !v101 )\n goto LABEL_106;\n ++v102;\n v101 = 0;\n }\n else\n {\n v104 = v101 - 1;\n v105 = 0;\n v106 = 0;\n v107 = 1;\n v108 = v104;\nLABEL_132:\n if ( v108 > 1 )\n {\nLABEL_133:\n v109 = (unsigned int)v108;\n v318 = v104;\n --v108;\n v299 = v102;\n v247 = v83;\n v219 = v107;\n v192 = v106;\n v164 = v105;\n v110 = func0_part_0(v109);\n v83 = v247;\n v102 = v299;\n v104 = v318;\n v106 = v192 + 1;\n v105 = v219 * v110 + v164;\n goto LABEL_134;\n }\n while ( 1 )\n {\n v105 += v107;\n ++v106;\n if ( !v108 )\n break;\n v108 = 0;\nLABEL_134:\n if ( v106 == 1 )\n {\n v107 = 1;\n goto LABEL_132;\n }\n v300 = v104;\n v273 = v102;\n v220 = v83;\n v193 = v105;\n v165 = v106;\n v111 = func0_part_0(v106);\n v106 = v165;\n v105 = v193;\n v83 = v220;\n v107 = v111;\n v102 = v273;\n v104 = v300;\n if ( v108 > 1 )\n goto LABEL_133;\n }\n ++v102;\n v101 = v104;\n v82 += v103 * v105;\n }\n if ( v102 == 1 )\n {\n v103 = 1;\n }\n else\n {\n v112 = v102 - 1;\n v113 = 0;\n v103 = 0;\n v114 = 1;\nLABEL_141:\n if ( v112 > 1 )\n {\nLABEL_142:\n v115 = (unsigned int)v112;\n v301 = v102;\n --v112;\n v248 = v83;\n v221 = v101;\n v194 = v114;\n v166 = v113;\n v116 = func0_part_0(v115);\n v101 = v221;\n v83 = v248;\n v102 = v301;\n v113 = v166 + 1;\n v103 += v194 * v116;\n goto LABEL_143;\n }\n while ( 1 )\n {\n v103 += v114;\n ++v113;\n if ( !v112 )\n break;\n v112 = 0;\nLABEL_143:\n if ( v113 == 1 )\n {\n v114 = 1;\n goto LABEL_141;\n }\n v274 = v102;\n v222 = v83;\n v195 = v101;\n v167 = v113;\n v117 = func0_part_0(v113);\n v113 = v167;\n v101 = v195;\n v83 = v222;\n v114 = v117;\n v102 = v274;\n if ( v112 > 1 )\n goto LABEL_142;\n }\n }\n }\n }\n v82 = 1;\n }\n ++v77;\n v173 += v83 * v175;\nLABEL_152:\n if ( v77 == 1 )\n {\n v78 = 1;\n }\n else\n {\n v118 = v77 - 1;\n v78 = 0;\n v119 = 0;\n for ( j = 1; ; j = 1 )\n {\nLABEL_154:\n if ( v118 > 1 )\n {\n v121 = v118 - 1;\n v122 = 0;\n v123 = 0;\n v124 = 1;\n v168 = v121;\n v125 = v121;\n while ( 1 )\n {\n if ( v125 <= 1 )\n {\n v123 += v124;\n if ( !v125 )\n {\n ++v119;\n v118 = v168;\n v78 += j * v123;\n goto LABEL_176;\n }\n ++v122;\n v125 = 0;\n }\n else\n {\n v126 = v125 - 1;\n v127 = 0;\n v128 = 0;\n v129 = 1;\n v130 = v126;\nLABEL_158:\n if ( v130 > 1 )\n {\nLABEL_159:\n v319 = v126;\n v302 = v122;\n v275 = v123;\n v249 = v129;\n v196 = v128;\n v176 = v130;\n v131 = func0_part_0((unsigned int)v130);\n v123 = v275;\n v122 = v302;\n v126 = v319;\n ++v127;\n v130 = v176 - 1;\n v128 = v249 * v131 + v196;\n goto LABEL_160;\n }\n while ( 1 )\n {\n v128 += v129;\n ++v127;\n if ( !v130 )\n break;\n v130 = 0;\nLABEL_160:\n if ( v127 == 1 )\n {\n v129 = 1;\n goto LABEL_158;\n }\n v303 = v126;\n v276 = v122;\n v250 = v123;\n v223 = v128;\n v197 = v130;\n v132 = func0_part_0(v127);\n v130 = v197;\n v128 = v223;\n v123 = v250;\n v129 = v132;\n v122 = v276;\n v126 = v303;\n if ( v197 > 1 )\n goto LABEL_159;\n }\n ++v122;\n v125 = v126;\n v123 += v124 * v128;\n }\n if ( v122 == 1 )\n {\n v124 = 1;\n }\n else\n {\n v133 = v122 - 1;\n v124 = 0;\n v134 = 0;\n v135 = 1;\nLABEL_167:\n if ( v133 > 1 )\n {\nLABEL_168:\n v304 = v122;\n v277 = v123;\n v251 = v125;\n v224 = v135;\n v177 = v133;\n v136 = func0_part_0((unsigned int)v133);\n v125 = v251;\n v123 = v277;\n v122 = v304;\n ++v134;\n v133 = v177 - 1;\n v124 += v224 * v136;\n goto LABEL_169;\n }\n while ( 1 )\n {\n v124 += v135;\n ++v134;\n if ( !v133 )\n break;\n v133 = 0;\nLABEL_169:\n if ( v134 == 1 )\n {\n v135 = 1;\n goto LABEL_167;\n }\n v278 = v122;\n v252 = v123;\n v225 = v125;\n v198 = v133;\n v137 = func0_part_0(v134);\n v133 = v198;\n v125 = v225;\n v123 = v252;\n v135 = v137;\n v122 = v278;\n if ( v198 > 1 )\n goto LABEL_168;\n }\n }\n }\n }\n v78 += j;\n if ( !v118 )\n break;\n ++v119;\n v118 = 0;\nLABEL_176:\n if ( v119 != 1 )\n {\n v138 = v119 - 1;\n j = 0;\n v139 = 0;\n v140 = 1;\n while ( 1 )\n {\n if ( v138 <= 1 )\n {\n j += v140;\n if ( !v138 )\n goto LABEL_154;\n ++v139;\n v138 = 0;\n }\n else\n {\n --v138;\n v141 = 0;\n v142 = 0;\n v143 = 1;\n v144 = v138;\nLABEL_180:\n if ( v144 > 1 )\n {\nLABEL_181:\n v305 = v138;\n v279 = v139;\n v253 = v143;\n v226 = v142;\n v199 = v141;\n v169 = v144;\n v145 = func0_part_0((unsigned int)v144);\n v139 = v279;\n v138 = v305;\n v142 = v226 + 1;\n v144 = v169 - 1;\n v141 = v253 * v145 + v199;\n goto LABEL_182;\n }\n while ( 1 )\n {\n v141 += v143;\n ++v142;\n if ( !v144 )\n break;\n v144 = 0;\nLABEL_182:\n if ( v142 == 1 )\n {\n v143 = 1;\n goto LABEL_180;\n }\n v280 = v138;\n v254 = v139;\n v227 = v141;\n v178 = v144;\n v170 = v142;\n v146 = func0_part_0(v142);\n v144 = v178;\n v142 = v170;\n v141 = v227;\n v143 = v146;\n v139 = v254;\n v138 = v280;\n if ( v178 > 1 )\n goto LABEL_181;\n }\n ++v139;\n j += v140 * v141;\n }\n if ( v139 == 1 )\n {\n v140 = 1;\n }\n else\n {\n v147 = v139 - 1;\n v148 = 0;\n v140 = 0;\n v149 = 1;\nLABEL_189:\n if ( v147 > 1 )\n {\nLABEL_190:\n v281 = v139;\n v255 = v138;\n v228 = v149;\n v200 = v148;\n v171 = v147;\n v150 = func0_part_0((unsigned int)v147);\n v138 = v255;\n v139 = v281;\n v148 = v200 + 1;\n v147 = v171 - 1;\n v140 += v228 * v150;\n goto LABEL_191;\n }\n while ( 1 )\n {\n v140 += v149;\n ++v148;\n if ( !v147 )\n break;\n v147 = 0;\nLABEL_191:\n if ( v148 == 1 )\n {\n v149 = 1;\n goto LABEL_189;\n }\n v256 = v139;\n v229 = v138;\n v201 = v147;\n v172 = v148;\n v151 = func0_part_0(v148);\n v147 = v201;\n v148 = v172;\n v138 = v229;\n v149 = v151;\n v139 = v256;\n if ( v201 > 1 )\n goto LABEL_190;\n }\n }\n }\n }\n }\n }\n continue;\n }\n break;\n }\n v173 += v78;\n if ( v79 )\n {\n ++v77;\n v79 = 0;\n goto LABEL_152;\n }\n v1 = v184;\n }\n while ( v184 > 1 );\nLABEL_202:\n v186 += v173;\n if ( v1 )\n {\n ++v185;\n v1 = 0;\n if ( v185 != 1 )\n goto LABEL_103;\n goto LABEL_204;\n }\n return v186;\n}", + "ida_strip_asm": "sub_11F0:\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 48h\nmov [rsp+78h+var_5C], 0\ntest edi, edi\njle loc_2441\nmov [rsp+78h+var_60], 0\nlea ebx, [rdi-1]\nmov [rsp+78h+var_6C], 1\nmov r12d, ebx\nloc_1224:\ncmp r12d, 1\njle loc_2414\nloc_122E:\nlea ebp, [r12-1]\nxor r15d, r15d\nmov [rsp+78h+var_68], 0\nmov r13d, 1\nmov r12d, ebp\nmov [rsp+78h+var_58], ebp\nmov ebp, r15d\nmov r15d, r13d\nmov r13d, r12d\nloc_1254:\ncmp r13d, 1\njle loc_1AF0\nmov [rsp+78h+var_64], r15d\nsub r13d, 1\nxor ebx, ebx\nxor esi, esi\nmov r14d, r13d\nmov r12d, 1\nmov r9d, ebx\nloc_1277:\ncmp r14d, 1\njle loc_1680\nsub r14d, 1\nxor r11d, r11d\nmov [rsp+78h+var_70], esi\nxor r10d, r10d\nmov edx, r14d\nmov r15d, 1\nmov esi, r11d\nloc_129B:\ncmp edx, 1\njle loc_1458\nsub edx, 1\nxor ecx, ecx\nxor r8d, r8d\nmov r11d, 1\nmov ebx, edx\nloc_12B4:\ncmp ebx, 1\njle loc_1370\nloc_12BD:\nmov edi, ebx\nmov [rsp+78h+var_3C], edx\nsub ebx, 1\nmov [rsp+78h+var_40], esi\nmov [rsp+78h+var_44], r10d\nmov [rsp+78h+var_48], r9d\nmov [rsp+78h+var_4C], ecx\nmov [rsp+78h+var_50], r8d\nmov [rsp+78h+var_54], r11d\ncall sub_11F0\nmov r11d, [rsp+78h+var_54]\nmov r8d, [rsp+78h+var_50]\nmov ecx, [rsp+78h+var_4C]\nmov r9d, [rsp+78h+var_48]\nimul eax, r11d\nmov r10d, [rsp+78h+var_44]\nmov esi, [rsp+78h+var_40]\nmov edx, [rsp+78h+var_3C]\nadd ecx, 1\nadd r8d, eax\nnop dword ptr [rax+00000000h]\nloc_1318:\ncmp ecx, 1\njz loc_24F8\nmov edi, ecx\nmov [rsp+78h+var_40], edx\nmov [rsp+78h+var_44], esi\nmov [rsp+78h+var_48], r10d\nmov [rsp+78h+var_4C], r9d\nmov [rsp+78h+var_50], r8d\nmov [rsp+78h+var_54], ecx\ncall sub_11F0\nmov ecx, [rsp+78h+var_54]\nmov r8d, [rsp+78h+var_50]\nmov r9d, [rsp+78h+var_4C]\nmov r10d, [rsp+78h+var_48]\nmov r11d, eax\nmov esi, [rsp+78h+var_44]\nmov edx, [rsp+78h+var_40]\ncmp ebx, 1\njg loc_12BD\nnop word ptr [rax+rax+00h]\nloc_1370:\nadd r8d, r11d\nadd ecx, 1\ntest ebx, ebx\njz short loc_1380\nxor ebx, ebx\njmp short loc_1318\nloc_1380:\nimul r8d, r15d\nadd esi, 1\nadd r10d, r8d\nloc_138A:\ncmp esi, 1\njz loc_24ED\nlea ebx, [rsi-1]\nxor r15d, r15d\nxor ecx, ecx\nmov r8d, 1\nloc_13A1:\ncmp ebx, 1\njle loc_1440\nloc_13AA:\nmov edi, ebx\nmov [rsp+78h+var_40], esi\nsub ebx, 1\nmov [rsp+78h+var_44], edx\nmov [rsp+78h+var_48], r10d\nmov [rsp+78h+var_4C], r9d\nmov [rsp+78h+var_50], ecx\nmov [rsp+78h+var_54], r8d\ncall sub_11F0\nmov r8d, [rsp+78h+var_54]\nmov ecx, [rsp+78h+var_50]\nmov r9d, [rsp+78h+var_4C]\nmov r10d, [rsp+78h+var_48]\nimul eax, r8d\nmov edx, [rsp+78h+var_44]\nmov esi, [rsp+78h+var_40]\nadd ecx, 1\nadd r15d, eax\nnop dword ptr [rax+00h]\nloc_13F8:\ncmp ecx, 1\njz loc_24E2\nmov edi, ecx\nmov [rsp+78h+var_44], esi\nmov [rsp+78h+var_48], edx\nmov [rsp+78h+var_4C], r10d\nmov [rsp+78h+var_50], r9d\nmov [rsp+78h+var_54], ecx\ncall sub_11F0\nmov ecx, [rsp+78h+var_54]\nmov r9d, [rsp+78h+var_50]\nmov r10d, [rsp+78h+var_4C]\nmov edx, [rsp+78h+var_48]\nmov r8d, eax\nmov esi, [rsp+78h+var_44]\ncmp ebx, 1\njg loc_13AA\nloc_1440:\nadd r15d, r8d\nadd ecx, 1\ntest ebx, ebx\njz loc_129B\nxor ebx, ebx\njmp short loc_13F8\nloc_1458:\nadd r10d, r15d\ntest edx, edx\njz short loc_1470\nadd esi, 1\nxor edx, edx\njmp loc_138A\nloc_1470:\nimul r10d, r12d\nmov esi, [rsp+78h+var_70]\nadd esi, 1\nadd r9d, r10d\nloc_147E:\ncmp esi, 1\njz loc_24D7\nlea r10d, [rsi-1]\nxor r12d, r12d\nxor r11d, r11d\nmov r15d, 1\nloc_1497:\ncmp r10d, 1\njle loc_1668\nlea ecx, [r10-1]\nxor r8d, r8d\nxor edx, edx\nmov r10d, 1\nmov ebx, ecx\nloc_14B2:\ncmp ebx, 1\njle loc_1568\nloc_14BB:\nmov edi, ebx\nmov [rsp+78h+var_40], ecx\nsub ebx, 1\nmov [rsp+78h+var_44], r11d\nmov [rsp+78h+var_48], r9d\nmov [rsp+78h+var_4C], esi\nmov [rsp+78h+var_50], r10d\nmov [rsp+78h+var_54], edx\nmov [rsp+78h+var_70], r8d\ncall sub_11F0\nmov r10d, [rsp+78h+var_50]\nmov r8d, [rsp+78h+var_70]\nmov edx, [rsp+78h+var_54]\nmov esi, [rsp+78h+var_4C]\nimul eax, r10d\nmov r9d, [rsp+78h+var_48]\nmov r11d, [rsp+78h+var_44]\nmov ecx, [rsp+78h+var_40]\nadd edx, 1\nadd r8d, eax\nnop\nloc_1510:\ncmp edx, 1\njz loc_24CC\nmov edi, edx\nmov [rsp+78h+var_44], ecx\nmov [rsp+78h+var_48], r11d\nmov [rsp+78h+var_4C], r9d\nmov [rsp+78h+var_50], esi\nmov [rsp+78h+var_54], r8d\nmov [rsp+78h+var_70], edx\ncall sub_11F0\nmov edx, [rsp+78h+var_70]\nmov r8d, [rsp+78h+var_54]\nmov esi, [rsp+78h+var_50]\nmov r9d, [rsp+78h+var_4C]\nmov r10d, eax\nmov r11d, [rsp+78h+var_48]\nmov ecx, [rsp+78h+var_44]\ncmp ebx, 1\njg loc_14BB\nnop word ptr [rax+rax+00h]\nloc_1568:\nadd r8d, r10d\nadd edx, 1\ntest ebx, ebx\njz short loc_1580\nxor ebx, ebx\njmp short loc_1510\nloc_1580:\nimul r8d, r15d\nadd r11d, 1\nmov r10d, ecx\nadd r12d, r8d\nloc_158E:\ncmp r11d, 1\njz loc_24C1\nlea ebx, [r11-1]\nxor edx, edx\nxor r15d, r15d\nmov r8d, 1\nloc_15A7:\ncmp ebx, 1\njle loc_1650\nloc_15B0:\nmov edi, ebx\nmov [rsp+78h+var_44], r10d\nsub ebx, 1\nmov [rsp+78h+var_48], r11d\nmov [rsp+78h+var_4C], r9d\nmov [rsp+78h+var_50], esi\nmov [rsp+78h+var_54], edx\nmov [rsp+78h+var_70], r8d\ncall sub_11F0\nmov r8d, [rsp+78h+var_70]\nmov edx, [rsp+78h+var_54]\nmov esi, [rsp+78h+var_50]\nmov r9d, [rsp+78h+var_4C]\nimul eax, r8d\nmov r11d, [rsp+78h+var_48]\nmov r10d, [rsp+78h+var_44]\nadd edx, 1\nadd r15d, eax\nnop dword ptr [rax+00h]\nloc_1600:\ncmp edx, 1\njz loc_24B6\nmov edi, edx\nmov [rsp+78h+var_48], r10d\nmov [rsp+78h+var_4C], r11d\nmov [rsp+78h+var_50], r9d\nmov [rsp+78h+var_54], esi\nmov [rsp+78h+var_70], edx\ncall sub_11F0\nmov edx, [rsp+78h+var_70]\nmov esi, [rsp+78h+var_54]\nmov r9d, [rsp+78h+var_50]\nmov r11d, [rsp+78h+var_4C]\nmov r8d, eax\nmov r10d, [rsp+78h+var_48]\ncmp ebx, 1\njg loc_15B0\nnop word ptr [rax+rax+00h]\nloc_1650:\nadd r15d, r8d\nadd edx, 1\ntest ebx, ebx\njz loc_1497\nxor ebx, ebx\njmp short loc_1600\nloc_1668:\nadd r12d, r15d\ntest r10d, r10d\njz loc_1277\nadd r11d, 1\nxor r10d, r10d\njmp loc_158E\nloc_1680:\nadd r9d, r12d\ntest r14d, r14d\njz short loc_1698\nadd esi, 1\nxor r14d, r14d\njmp loc_147E\nloc_1698:\nmov r15d, [rsp+78h+var_64]\nadd ebp, 1\nimul r15d, r9d\nadd [rsp+78h+var_68], r15d\nloc_16A9:\ncmp ebp, 1\njz loc_24AB\nlea r12d, [rbp-1]\nxor r15d, r15d\nxor ebx, ebx\nmov r14d, 1\nloc_16C1:\ncmp r12d, 1\njle loc_1AD0\nlea edx, [r12-1]\nxor r8d, r8d\nxor r9d, r9d\nmov r12d, 1\nmov [rsp+78h+var_70], edx\nmov r10d, edx\nloc_16E3:\ncmp r10d, 1\njle loc_18B8\nlea edx, [r10-1]\nxor r11d, r11d\nxor esi, esi\nmov r10d, 1\nmov ecx, edx\nloc_16FE:\ncmp ecx, 1\njle loc_17B8\nloc_1707:\nmov edi, ecx\nmov [rsp+78h+var_40], edx\nmov [rsp+78h+var_44], r8d\nmov [rsp+78h+var_48], r9d\nmov [rsp+78h+var_4C], esi\nmov [rsp+78h+var_50], r11d\nmov [rsp+78h+var_54], r10d\nmov [rsp+78h+var_64], ecx\ncall sub_11F0\nmov r10d, [rsp+78h+var_54]\nmov r11d, [rsp+78h+var_50]\nmov esi, [rsp+78h+var_4C]\nmov ecx, [rsp+78h+var_64]\nimul eax, r10d\nmov r9d, [rsp+78h+var_48]\nmov r8d, [rsp+78h+var_44]\nmov edx, [rsp+78h+var_40]\nadd esi, 1\nsub ecx, 1\nadd r11d, eax\nnop dword ptr [rax+rax+00h]\nloc_1760:\ncmp esi, 1\njz loc_24A0\nmov edi, esi\nmov [rsp+78h+var_44], edx\nmov [rsp+78h+var_48], r8d\nmov [rsp+78h+var_4C], r9d\nmov [rsp+78h+var_50], ecx\nmov [rsp+78h+var_54], r11d\nmov [rsp+78h+var_64], esi\ncall sub_11F0\nmov ecx, [rsp+78h+var_50]\nmov esi, [rsp+78h+var_64]\nmov r11d, [rsp+78h+var_54]\nmov r9d, [rsp+78h+var_4C]\nmov r10d, eax\nmov r8d, [rsp+78h+var_48]\nmov edx, [rsp+78h+var_44]\ncmp ecx, 1\njg loc_1707\nnop word ptr [rax+rax+00h]\nloc_17B8:\nadd r11d, r10d\nadd esi, 1\ntest ecx, ecx\njz short loc_17D0\nxor ecx, ecx\njmp short loc_1760\nloc_17D0:\nimul r11d, r12d\nadd r9d, 1\nmov r10d, edx\nadd r8d, r11d\nloc_17DE:\ncmp r9d, 1\njz loc_2495\nlea ecx, [r9-1]\nxor r12d, r12d\nxor esi, esi\nmov r11d, 1\nloc_17F7:\ncmp ecx, 1\njle loc_18A0\nloc_1800:\nmov edi, ecx\nmov [rsp+78h+var_44], r10d\nmov [rsp+78h+var_48], r8d\nmov [rsp+78h+var_4C], r9d\nmov [rsp+78h+var_50], esi\nmov [rsp+78h+var_54], r11d\nmov [rsp+78h+var_64], ecx\ncall sub_11F0\nmov r11d, [rsp+78h+var_54]\nmov esi, [rsp+78h+var_50]\nmov ecx, [rsp+78h+var_64]\nmov r9d, [rsp+78h+var_4C]\nimul eax, r11d\nmov r8d, [rsp+78h+var_48]\nmov r10d, [rsp+78h+var_44]\nadd esi, 1\nsub ecx, 1\nadd r12d, eax\nnop dword ptr [rax+00h]\nloc_1850:\ncmp esi, 1\njz loc_248A\nmov edi, esi\nmov [rsp+78h+var_48], r10d\nmov [rsp+78h+var_4C], r8d\nmov [rsp+78h+var_50], r9d\nmov [rsp+78h+var_54], ecx\nmov [rsp+78h+var_64], esi\ncall sub_11F0\nmov ecx, [rsp+78h+var_54]\nmov esi, [rsp+78h+var_64]\nmov r9d, [rsp+78h+var_50]\nmov r8d, [rsp+78h+var_4C]\nmov r11d, eax\nmov r10d, [rsp+78h+var_48]\ncmp ecx, 1\njg loc_1800\nnop word ptr [rax+rax+00h]\nloc_18A0:\nadd r12d, r11d\nadd esi, 1\ntest ecx, ecx\njz loc_16E3\nxor ecx, ecx\njmp short loc_1850\nloc_18B8:\nadd r8d, r12d\ntest r10d, r10d\njz short loc_18D0\nadd r9d, 1\nxor r10d, r10d\njmp loc_17DE\nloc_18D0:\nimul r8d, r14d\nmov edx, [rsp+78h+var_70]\nadd ebx, 1\nmov r12d, edx\nadd r15d, r8d\nloc_18E1:\ncmp ebx, 1\njz loc_247F\nlea r8d, [rbx-1]\nxor r14d, r14d\nxor r9d, r9d\nmov esi, 1\nloc_18F9:\ncmp r8d, 1\njle loc_1AB8\nsub r8d, 1\nxor r10d, r10d\nxor ecx, ecx\nmov r11d, 1\nmov edx, r8d\nloc_1915:\ncmp edx, 1\njle loc_19D0\nloc_191E:\nmov edi, edx\nmov [rsp+78h+var_44], r8d\nmov [rsp+78h+var_48], r9d\nmov [rsp+78h+var_4C], r11d\nmov [rsp+78h+var_50], ecx\nmov [rsp+78h+var_54], r10d\nmov [rsp+78h+var_64], esi\nmov [rsp+78h+var_70], edx\ncall sub_11F0\nmov r11d, [rsp+78h+var_4C]\nmov r10d, [rsp+78h+var_54]\nmov ecx, [rsp+78h+var_50]\nmov edx, [rsp+78h+var_70]\nimul eax, r11d\nmov esi, [rsp+78h+var_64]\nmov r9d, [rsp+78h+var_48]\nmov r8d, [rsp+78h+var_44]\nadd ecx, 1\nsub edx, 1\nadd r10d, eax\nnop word ptr [rax+rax+00h]\nloc_1978:\ncmp ecx, 1\njz loc_2474\nmov edi, ecx\nmov [rsp+78h+var_48], r8d\nmov [rsp+78h+var_4C], r9d\nmov [rsp+78h+var_50], r10d\nmov [rsp+78h+var_54], esi\nmov [rsp+78h+var_64], edx\nmov [rsp+78h+var_70], ecx\ncall sub_11F0\nmov edx, [rsp+78h+var_64]\nmov ecx, [rsp+78h+var_70]\nmov esi, [rsp+78h+var_54]\nmov r10d, [rsp+78h+var_50]\nmov r11d, eax\nmov r9d, [rsp+78h+var_4C]\nmov r8d, [rsp+78h+var_48]\ncmp edx, 1\njg loc_191E\nnop word ptr [rax+rax+00h]\nloc_19D0:\nadd r10d, r11d\nadd ecx, 1\ntest edx, edx\njz short loc_19E0\nxor edx, edx\njmp short loc_1978\nloc_19E0:\nimul r10d, esi\nadd r9d, 1\nadd r14d, r10d\nloc_19EB:\ncmp r9d, 1\njz loc_246A\nlea edx, [r9-1]\nxor esi, esi\nxor ecx, ecx\nmov r10d, 1\nloc_1A03:\ncmp edx, 1\njle loc_1AA0\nloc_1A0C:\nmov edi, edx\nmov [rsp+78h+var_48], r8d\nmov [rsp+78h+var_4C], r9d\nmov [rsp+78h+var_50], r10d\nmov [rsp+78h+var_54], ecx\nmov [rsp+78h+var_64], esi\nmov [rsp+78h+var_70], edx\ncall sub_11F0\nmov r10d, [rsp+78h+var_50]\nmov esi, [rsp+78h+var_64]\nmov ecx, [rsp+78h+var_54]\nmov edx, [rsp+78h+var_70]\nimul eax, r10d\nmov r9d, [rsp+78h+var_4C]\nmov r8d, [rsp+78h+var_48]\nadd ecx, 1\nsub edx, 1\nadd esi, eax\nnop dword ptr [rax]\nloc_1A58:\ncmp ecx, 1\njz loc_245F\nmov edi, ecx\nmov [rsp+78h+var_4C], r8d\nmov [rsp+78h+var_50], r9d\nmov [rsp+78h+var_54], esi\nmov [rsp+78h+var_64], edx\nmov [rsp+78h+var_70], ecx\ncall sub_11F0\nmov edx, [rsp+78h+var_64]\nmov ecx, [rsp+78h+var_70]\nmov esi, [rsp+78h+var_54]\nmov r9d, [rsp+78h+var_50]\nmov r10d, eax\nmov r8d, [rsp+78h+var_4C]\ncmp edx, 1\njg loc_1A0C\nloc_1AA0:\nadd esi, r10d\nadd ecx, 1\ntest edx, edx\njz loc_18F9\nxor edx, edx\njmp short loc_1A58\nloc_1AB8:\nadd r14d, esi\ntest r8d, r8d\njz loc_16C1\nadd r9d, 1\nxor r8d, r8d\njmp loc_19EB\nloc_1AD0:\nadd r15d, r14d\ntest r12d, r12d\njz loc_1254\nadd ebx, 1\nxor r12d, r12d\njmp loc_18E1\nloc_1AF0:\nadd [rsp+78h+var_68], r15d\ntest r13d, r13d\njz short loc_1B05\nadd ebp, 1\nxor r13d, r13d\njmp loc_16A9\nloc_1B05:\nmov eax, [rsp+78h+var_6C]\nmov edi, [rsp+78h+var_68]\nmov ebp, [rsp+78h+var_58]\nadd [rsp+78h+var_60], 1\nimul eax, edi\nadd [rsp+78h+var_5C], eax\ncmp [rsp+78h+var_60], 1\nmov r12d, ebp\njz loc_2434\nloc_1B2B:\nmov eax, [rsp+78h+var_60]\nmov [rsp+78h+var_6C], 0\nxor r15d, r15d\nmov r13d, 1\nmov [rsp+78h+var_64], r12d\nlea ebp, [rax-1]\nmov eax, ebp\nmov ebp, r15d\nmov r15d, r13d\nmov r13d, eax\nloc_1B53:\ncmp r13d, 1\njle loc_23F0\nmov [rsp+78h+var_68], r15d\nsub r13d, 1\nxor ebx, ebx\nxor esi, esi\nmov r14d, r13d\nmov r12d, 1\nmov r9d, ebx\nloc_1B76:\ncmp r14d, 1\njle loc_1F80\nsub r14d, 1\nxor r11d, r11d\nmov [rsp+78h+var_70], esi\nxor r10d, r10d\nmov edx, r14d\nmov r15d, 1\nmov esi, r11d\nloc_1B9A:\ncmp edx, 1\njle loc_1D58\nsub edx, 1\nxor r8d, r8d\nxor ecx, ecx\nmov r11d, 1\nmov ebx, edx\nloc_1BB3:\ncmp ebx, 1\njle loc_1C68\nloc_1BBC:\nmov edi, ebx\nmov [rsp+78h+var_40], edx\nsub ebx, 1\nmov [rsp+78h+var_44], r10d\nmov [rsp+78h+var_48], esi\nmov [rsp+78h+var_4C], r9d\nmov [rsp+78h+var_50], r11d\nmov [rsp+78h+var_54], ecx\nmov [rsp+78h+var_58], r8d\ncall sub_11F0\nmov r11d, [rsp+78h+var_50]\nmov r8d, [rsp+78h+var_58]\nmov ecx, [rsp+78h+var_54]\nmov r9d, [rsp+78h+var_4C]\nimul eax, r11d\nmov esi, [rsp+78h+var_48]\nmov r10d, [rsp+78h+var_44]\nmov edx, [rsp+78h+var_40]\nadd ecx, 1\nadd r8d, eax\nloc_1C10:\ncmp ecx, 1\njz loc_2454\nmov edi, ecx\nmov [rsp+78h+var_44], edx\nmov [rsp+78h+var_48], r10d\nmov [rsp+78h+var_4C], esi\nmov [rsp+78h+var_50], r9d\nmov [rsp+78h+var_54], r8d\nmov [rsp+78h+var_58], ecx\ncall sub_11F0\nmov ecx, [rsp+78h+var_58]\nmov r8d, [rsp+78h+var_54]\nmov r9d, [rsp+78h+var_50]\nmov esi, [rsp+78h+var_4C]\nmov r11d, eax\nmov r10d, [rsp+78h+var_48]\nmov edx, [rsp+78h+var_44]\ncmp ebx, 1\njg loc_1BBC\nnop word ptr [rax+rax+00h]\nloc_1C68:\nadd r8d, r11d\nadd ecx, 1\ntest ebx, ebx\njz short loc_1C80\nxor ebx, ebx\njmp short loc_1C10\nloc_1C80:\nimul r8d, r15d\nadd esi, 1\nadd r10d, r8d\nloc_1C8A:\ncmp esi, 1\njz loc_2590\nlea ebx, [rsi-1]\nxor r15d, r15d\nxor ecx, ecx\nmov r8d, 1\nloc_1CA1:\ncmp ebx, 1\njle loc_1D40\nloc_1CAA:\nmov edi, ebx\nmov [rsp+78h+var_44], r10d\nsub ebx, 1\nmov [rsp+78h+var_48], esi\nmov [rsp+78h+var_4C], edx\nmov [rsp+78h+var_50], r9d\nmov [rsp+78h+var_54], r8d\nmov [rsp+78h+var_58], ecx\ncall sub_11F0\nmov r8d, [rsp+78h+var_54]\nmov ecx, [rsp+78h+var_58]\nmov r9d, [rsp+78h+var_50]\nmov edx, [rsp+78h+var_4C]\nimul eax, r8d\nmov esi, [rsp+78h+var_48]\nmov r10d, [rsp+78h+var_44]\nadd ecx, 1\nadd r15d, eax\nnop dword ptr [rax+00h]\nloc_1CF8:\ncmp ecx, 1\njz loc_2585\nmov edi, ecx\nmov [rsp+78h+var_48], r10d\nmov [rsp+78h+var_4C], esi\nmov [rsp+78h+var_50], edx\nmov [rsp+78h+var_54], r9d\nmov [rsp+78h+var_58], ecx\ncall sub_11F0\nmov ecx, [rsp+78h+var_58]\nmov r9d, [rsp+78h+var_54]\nmov edx, [rsp+78h+var_50]\nmov esi, [rsp+78h+var_4C]\nmov r8d, eax\nmov r10d, [rsp+78h+var_48]\ncmp ebx, 1\njg loc_1CAA\nloc_1D40:\nadd r15d, r8d\nadd ecx, 1\ntest ebx, ebx\njz loc_1B9A\nxor ebx, ebx\njmp short loc_1CF8\nloc_1D58:\nadd r10d, r15d\ntest edx, edx\njz short loc_1D70\nadd esi, 1\nxor edx, edx\njmp loc_1C8A\nloc_1D70:\nimul r10d, r12d\nmov esi, [rsp+78h+var_70]\nadd esi, 1\nadd r9d, r10d\nloc_1D7E:\ncmp esi, 1\njz loc_257A\nlea r10d, [rsi-1]\nxor r11d, r11d\nxor r12d, r12d\nmov r15d, 1\nloc_1D97:\ncmp r10d, 1\njle loc_1F68\nlea ecx, [r10-1]\nxor r8d, r8d\nxor edx, edx\nmov r10d, 1\nmov ebx, ecx\nloc_1DB2:\ncmp ebx, 1\njle loc_1E68\nloc_1DBB:\nmov edi, ebx\nmov [rsp+78h+var_44], ecx\nsub ebx, 1\nmov [rsp+78h+var_48], r11d\nmov [rsp+78h+var_4C], esi\nmov [rsp+78h+var_50], r9d\nmov [rsp+78h+var_54], r10d\nmov [rsp+78h+var_58], edx\nmov [rsp+78h+var_70], r8d\ncall sub_11F0\nmov r10d, [rsp+78h+var_54]\nmov r8d, [rsp+78h+var_70]\nmov edx, [rsp+78h+var_58]\nmov r9d, [rsp+78h+var_50]\nimul eax, r10d\nmov esi, [rsp+78h+var_4C]\nmov r11d, [rsp+78h+var_48]\nmov ecx, [rsp+78h+var_44]\nadd edx, 1\nadd r8d, eax\nnop\nloc_1E10:\ncmp edx, 1\njz loc_256F\nmov edi, edx\nmov [rsp+78h+var_48], ecx\nmov [rsp+78h+var_4C], r11d\nmov [rsp+78h+var_50], esi\nmov [rsp+78h+var_54], r9d\nmov [rsp+78h+var_58], r8d\nmov [rsp+78h+var_70], edx\ncall sub_11F0\nmov edx, [rsp+78h+var_70]\nmov r8d, [rsp+78h+var_58]\nmov r9d, [rsp+78h+var_54]\nmov esi, [rsp+78h+var_50]\nmov r10d, eax\nmov r11d, [rsp+78h+var_4C]\nmov ecx, [rsp+78h+var_48]\ncmp ebx, 1\njg loc_1DBB\nnop word ptr [rax+rax+00h]\nloc_1E68:\nadd r8d, r10d\nadd edx, 1\ntest ebx, ebx\njz short loc_1E80\nxor ebx, ebx\njmp short loc_1E10\nloc_1E80:\nimul r8d, r15d\nadd r11d, 1\nmov r10d, ecx\nadd r12d, r8d\nloc_1E8E:\ncmp r11d, 1\njz loc_2564\nlea ebx, [r11-1]\nxor edx, edx\nxor r15d, r15d\nmov r8d, 1\nloc_1EA7:\ncmp ebx, 1\njle loc_1F50\nloc_1EB0:\nmov edi, ebx\nmov [rsp+78h+var_48], r11d\nsub ebx, 1\nmov [rsp+78h+var_4C], esi\nmov [rsp+78h+var_50], r9d\nmov [rsp+78h+var_54], r10d\nmov [rsp+78h+var_58], r8d\nmov [rsp+78h+var_70], edx\ncall sub_11F0\nmov r8d, [rsp+78h+var_58]\nmov edx, [rsp+78h+var_70]\nmov r10d, [rsp+78h+var_54]\nmov r9d, [rsp+78h+var_50]\nimul eax, r8d\nmov esi, [rsp+78h+var_4C]\nmov r11d, [rsp+78h+var_48]\nadd edx, 1\nadd r15d, eax\nnop dword ptr [rax+00h]\nloc_1F00:\ncmp edx, 1\njz loc_2559\nmov edi, edx\nmov [rsp+78h+var_4C], r11d\nmov [rsp+78h+var_50], esi\nmov [rsp+78h+var_54], r9d\nmov [rsp+78h+var_58], r10d\nmov [rsp+78h+var_70], edx\ncall sub_11F0\nmov edx, [rsp+78h+var_70]\nmov r10d, [rsp+78h+var_58]\nmov r9d, [rsp+78h+var_54]\nmov esi, [rsp+78h+var_50]\nmov r8d, eax\nmov r11d, [rsp+78h+var_4C]\ncmp ebx, 1\njg loc_1EB0\nnop word ptr [rax+rax+00h]\nloc_1F50:\nadd r15d, r8d\nadd edx, 1\ntest ebx, ebx\njz loc_1D97\nxor ebx, ebx\njmp short loc_1F00\nloc_1F68:\nadd r12d, r15d\ntest r10d, r10d\njz loc_1B76\nadd r11d, 1\nxor r10d, r10d\njmp loc_1E8E\nloc_1F80:\nadd r9d, r12d\ntest r14d, r14d\njz short loc_1F98\nadd esi, 1\nxor r14d, r14d\njmp loc_1D7E\nloc_1F98:\nmov r15d, [rsp+78h+var_68]\nadd ebp, 1\nimul r15d, r9d\nadd [rsp+78h+var_6C], r15d\nloc_1FA9:\ncmp ebp, 1\njz loc_254E\nlea ebx, [rbp-1]\nxor r15d, r15d\nxor r12d, r12d\nmov r14d, 1\nloc_1FC1:\ncmp ebx, 1\njle loc_23D0\nlea edx, [rbx-1]\nxor r9d, r9d\nxor r8d, r8d\nmov ebx, 1\nmov [rsp+78h+var_70], edx\nmov r10d, edx\nloc_1FDF:\ncmp r10d, 1\njle loc_21B8\nlea edx, [r10-1]\nxor esi, esi\nxor r11d, r11d\nmov r10d, 1\nmov ecx, edx\nloc_1FFA:\ncmp ecx, 1\njle loc_20B8\nloc_2003:\nmov edi, ecx\nmov [rsp+78h+var_44], edx\nmov [rsp+78h+var_48], r9d\nmov [rsp+78h+var_4C], r8d\nmov [rsp+78h+var_50], r10d\nmov [rsp+78h+var_54], esi\nmov [rsp+78h+var_58], r11d\nmov [rsp+78h+var_68], ecx\ncall sub_11F0\nmov r10d, [rsp+78h+var_50]\nmov r11d, [rsp+78h+var_58]\nmov esi, [rsp+78h+var_54]\nmov ecx, [rsp+78h+var_68]\nimul eax, r10d\nmov r8d, [rsp+78h+var_4C]\nmov r9d, [rsp+78h+var_48]\nmov edx, [rsp+78h+var_44]\nadd esi, 1\nsub ecx, 1\nadd r11d, eax\nnop word ptr [rax+rax+00000000h]\nloc_2060:\ncmp esi, 1\njz loc_2543\nmov edi, esi\nmov [rsp+78h+var_48], edx\nmov [rsp+78h+var_4C], r9d\nmov [rsp+78h+var_50], r8d\nmov [rsp+78h+var_54], r11d\nmov [rsp+78h+var_58], ecx\nmov [rsp+78h+var_68], esi\ncall sub_11F0\nmov ecx, [rsp+78h+var_58]\nmov esi, [rsp+78h+var_68]\nmov r11d, [rsp+78h+var_54]\nmov r8d, [rsp+78h+var_50]\nmov r10d, eax\nmov r9d, [rsp+78h+var_4C]\nmov edx, [rsp+78h+var_48]\ncmp ecx, 1\njg loc_2003\nnop word ptr [rax+rax+00h]\nloc_20B8:\nadd r11d, r10d\nadd esi, 1\ntest ecx, ecx\njz short loc_20D0\nxor ecx, ecx\njmp short loc_2060\nloc_20D0:\nimul r11d, ebx\nadd r9d, 1\nmov r10d, edx\nadd r8d, r11d\nloc_20DE:\ncmp r9d, 1\njz loc_2539\nlea ecx, [r9-1]\nxor ebx, ebx\nxor esi, esi\nmov r11d, 1\nloc_20F6:\ncmp ecx, 1\njle loc_21A0\nloc_20FF:\nmov edi, ecx\nmov [rsp+78h+var_48], r9d\nmov [rsp+78h+var_4C], r8d\nmov [rsp+78h+var_50], r10d\nmov [rsp+78h+var_54], r11d\nmov [rsp+78h+var_58], esi\nmov [rsp+78h+var_68], ecx\ncall sub_11F0\nmov r11d, [rsp+78h+var_54]\nmov esi, [rsp+78h+var_58]\nmov ecx, [rsp+78h+var_68]\nmov r10d, [rsp+78h+var_50]\nimul eax, r11d\nmov r8d, [rsp+78h+var_4C]\nmov r9d, [rsp+78h+var_48]\nadd esi, 1\nsub ecx, 1\nadd ebx, eax\nnop word ptr [rax+rax+00h]\nloc_2150:\ncmp esi, 1\njz loc_252E\nmov edi, esi\nmov [rsp+78h+var_4C], r9d\nmov [rsp+78h+var_50], r8d\nmov [rsp+78h+var_54], r10d\nmov [rsp+78h+var_58], ecx\nmov [rsp+78h+var_68], esi\ncall sub_11F0\nmov ecx, [rsp+78h+var_58]\nmov esi, [rsp+78h+var_68]\nmov r10d, [rsp+78h+var_54]\nmov r8d, [rsp+78h+var_50]\nmov r11d, eax\nmov r9d, [rsp+78h+var_4C]\ncmp ecx, 1\njg loc_20FF\nnop word ptr [rax+rax+00h]\nloc_21A0:\nadd ebx, r11d\nadd esi, 1\ntest ecx, ecx\njz loc_1FDF\nxor ecx, ecx\njmp short loc_2150\nloc_21B8:\nadd r8d, ebx\ntest r10d, r10d\njz short loc_21D0\nadd r9d, 1\nxor r10d, r10d\njmp loc_20DE\nloc_21D0:\nimul r8d, r14d\nmov edx, [rsp+78h+var_70]\nadd r12d, 1\nmov ebx, edx\nadd r15d, r8d\nloc_21E1:\ncmp r12d, 1\njz loc_2523\nlea r8d, [r12-1]\nxor r14d, r14d\nxor r9d, r9d\nmov esi, 1\nloc_21FB:\ncmp r8d, 1\njle loc_23B8\nsub r8d, 1\nxor r10d, r10d\nxor ecx, ecx\nmov r11d, 1\nmov edx, r8d\nloc_2217:\ncmp edx, 1\njle loc_22D0\nloc_2220:\nmov edi, edx\nmov [rsp+78h+var_48], r8d\nmov [rsp+78h+var_4C], r9d\nmov [rsp+78h+var_50], r11d\nmov [rsp+78h+var_54], ecx\nmov [rsp+78h+var_58], r10d\nmov [rsp+78h+var_68], esi\nmov [rsp+78h+var_70], edx\ncall sub_11F0\nmov r11d, [rsp+78h+var_50]\nmov r10d, [rsp+78h+var_58]\nmov ecx, [rsp+78h+var_54]\nmov edx, [rsp+78h+var_70]\nimul eax, r11d\nmov esi, [rsp+78h+var_68]\nmov r9d, [rsp+78h+var_4C]\nmov r8d, [rsp+78h+var_48]\nadd ecx, 1\nsub edx, 1\nadd r10d, eax\nnop dword ptr [rax+00h]\nloc_2278:\ncmp ecx, 1\njz loc_2518\nmov edi, ecx\nmov [rsp+78h+var_4C], r8d\nmov [rsp+78h+var_50], r9d\nmov [rsp+78h+var_54], r10d\nmov [rsp+78h+var_58], esi\nmov [rsp+78h+var_68], edx\nmov [rsp+78h+var_70], ecx\ncall sub_11F0\nmov edx, [rsp+78h+var_68]\nmov ecx, [rsp+78h+var_70]\nmov esi, [rsp+78h+var_58]\nmov r10d, [rsp+78h+var_54]\nmov r11d, eax\nmov r9d, [rsp+78h+var_50]\nmov r8d, [rsp+78h+var_4C]\ncmp edx, 1\njg loc_2220\nnop word ptr [rax+rax+00h]\nloc_22D0:\nadd r10d, r11d\nadd ecx, 1\ntest edx, edx\njz short loc_22E0\nxor edx, edx\njmp short loc_2278\nloc_22E0:\nimul r10d, esi\nadd r9d, 1\nadd r14d, r10d\nloc_22EB:\ncmp r9d, 1\njz loc_250E\nlea edx, [r9-1]\nxor ecx, ecx\nxor esi, esi\nmov r10d, 1\nloc_2303:\ncmp edx, 1\njle loc_23A0\nloc_230C:\nmov edi, edx\nmov [rsp+78h+var_4C], r9d\nmov [rsp+78h+var_50], r8d\nmov [rsp+78h+var_54], r10d\nmov [rsp+78h+var_58], ecx\nmov [rsp+78h+var_68], esi\nmov [rsp+78h+var_70], edx\ncall sub_11F0\nmov r10d, [rsp+78h+var_54]\nmov esi, [rsp+78h+var_68]\nmov ecx, [rsp+78h+var_58]\nmov edx, [rsp+78h+var_70]\nimul eax, r10d\nmov r8d, [rsp+78h+var_50]\nmov r9d, [rsp+78h+var_4C]\nadd ecx, 1\nsub edx, 1\nadd esi, eax\nnop dword ptr [rax]\nloc_2358:\ncmp ecx, 1\njz loc_2503\nmov edi, ecx\nmov [rsp+78h+var_50], r9d\nmov [rsp+78h+var_54], r8d\nmov [rsp+78h+var_58], edx\nmov [rsp+78h+var_68], esi\nmov [rsp+78h+var_70], ecx\ncall sub_11F0\nmov edx, [rsp+78h+var_58]\nmov ecx, [rsp+78h+var_70]\nmov esi, [rsp+78h+var_68]\nmov r8d, [rsp+78h+var_54]\nmov r10d, eax\nmov r9d, [rsp+78h+var_50]\ncmp edx, 1\njg loc_230C\nloc_23A0:\nadd esi, r10d\nadd ecx, 1\ntest edx, edx\njz loc_21FB\nxor edx, edx\njmp short loc_2358\nloc_23B8:\nadd r14d, esi\ntest r8d, r8d\njz loc_1FC1\nadd r9d, 1\nxor r8d, r8d\njmp loc_22EB\nloc_23D0:\nadd r15d, r14d\ntest ebx, ebx\njz loc_1B53\nadd r12d, 1\nxor ebx, ebx\njmp loc_21E1\nloc_23F0:\nadd [rsp+78h+var_6C], r15d\ntest r13d, r13d\njz short loc_2405\nadd ebp, 1\nxor r13d, r13d\njmp loc_1FA9\nloc_2405:\nmov r12d, [rsp+78h+var_64]\ncmp r12d, 1\njg loc_122E\nloc_2414:\nmov edi, [rsp+78h+var_6C]\nadd [rsp+78h+var_5C], edi\ntest r12d, r12d\njz short loc_2441\nadd [rsp+78h+var_60], 1\nxor r12d, r12d\ncmp [rsp+78h+var_60], 1\njnz loc_1B2B\nloc_2434:\nmov [rsp+78h+var_6C], 1\njmp loc_1224\nloc_2441:\nmov eax, [rsp+78h+var_5C]\nadd rsp, 48h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_2454:\nmov r11d, 1\njmp loc_1BB3\nloc_245F:\nmov r10d, 1\njmp loc_1A03\nloc_246A:\nmov esi, 1\njmp loc_18F9\nloc_2474:\nmov r11d, 1\njmp loc_1915\nloc_247F:\nmov r14d, 1\njmp loc_16C1\nloc_248A:\nmov r11d, 1\njmp loc_17F7\nloc_2495:\nmov r12d, 1\njmp loc_16E3\nloc_24A0:\nmov r10d, 1\njmp loc_16FE\nloc_24AB:\nmov r15d, 1\njmp loc_1254\nloc_24B6:\nmov r8d, 1\njmp loc_15A7\nloc_24C1:\nmov r15d, 1\njmp loc_1497\nloc_24CC:\nmov r10d, 1\njmp loc_14B2\nloc_24D7:\nmov r12d, 1\njmp loc_1277\nloc_24E2:\nmov r8d, 1\njmp loc_13A1\nloc_24ED:\nmov r15d, 1\njmp loc_129B\nloc_24F8:\nmov r11d, 1\njmp loc_12B4\nloc_2503:\nmov r10d, 1\njmp loc_2303\nloc_250E:\nmov esi, 1\njmp loc_21FB\nloc_2518:\nmov r11d, 1\njmp loc_2217\nloc_2523:\nmov r14d, 1\njmp loc_1FC1\nloc_252E:\nmov r11d, 1\njmp loc_20F6\nloc_2539:\nmov ebx, 1\njmp loc_1FDF\nloc_2543:\nmov r10d, 1\njmp loc_1FFA\nloc_254E:\nmov r15d, 1\njmp loc_1B53\nloc_2559:\nmov r8d, 1\njmp loc_1EA7\nloc_2564:\nmov r15d, 1\njmp loc_1D97\nloc_256F:\nmov r10d, 1\njmp loc_1DB2\nloc_257A:\nmov r12d, 1\njmp loc_1B76\nloc_2585:\nmov r8d, 1\njmp loc_1CA1\nloc_2590:\nmov r15d, 1\njmp loc_1B9A", + "ida_strip_pseudo": "__int64 __fastcall sub_11F0(int a1)\n{\n int v1; // r12d\n int v2; // ebp\n int v3; // r15d\n int v4; // r13d\n int v5; // esi\n int v6; // r14d\n int v7; // r12d\n int v8; // r9d\n int v9; // r10d\n int v10; // edx\n int v11; // r15d\n int v12; // esi\n unsigned int v13; // ecx\n int v14; // r8d\n int v15; // r11d\n int v16; // ebx\n __int64 v17; // rdi\n int v18; // eax\n int v19; // eax\n int v20; // ebx\n unsigned int v21; // ecx\n int v22; // r8d\n __int64 v23; // rdi\n int v24; // eax\n int v25; // eax\n int v26; // r10d\n int v27; // r11d\n int v28; // r15d\n int v29; // ecx\n int v30; // r8d\n unsigned int v31; // edx\n int v32; // r10d\n int v33; // ebx\n __int64 v34; // rdi\n int v35; // eax\n int v36; // eax\n int v37; // ebx\n unsigned int v38; // edx\n int v39; // r8d\n __int64 v40; // rdi\n int v41; // eax\n int v42; // eax\n int v43; // r12d\n int v44; // ebx\n int i; // r14d\n int v46; // edx\n int v47; // r8d\n int v48; // r9d\n int v49; // r12d\n int v50; // r10d\n int v51; // edx\n int v52; // r11d\n unsigned int v53; // esi\n int v54; // r10d\n int v55; // ecx\n int v56; // eax\n int v57; // eax\n int v58; // ecx\n unsigned int v59; // esi\n int v60; // r11d\n int v61; // eax\n int v62; // eax\n int v63; // r8d\n int v64; // r9d\n int v65; // esi\n int v66; // r10d\n unsigned int v67; // ecx\n int v68; // r11d\n int v69; // edx\n int v70; // eax\n int v71; // eax\n int v72; // edx\n unsigned int v73; // ecx\n int v74; // r10d\n int v75; // eax\n int v76; // eax\n int v77; // ebp\n int v78; // r15d\n int v79; // r13d\n int v80; // esi\n int v81; // r14d\n int v82; // r12d\n int v83; // r9d\n int v84; // r10d\n int v85; // edx\n int v86; // r15d\n int v87; // esi\n int v88; // r8d\n unsigned int v89; // ecx\n int v90; // r11d\n int v91; // ebx\n __int64 v92; // rdi\n int v93; // eax\n int v94; // eax\n int v95; // ebx\n unsigned int v96; // ecx\n int v97; // r8d\n __int64 v98; // rdi\n int v99; // eax\n int v100; // eax\n int v101; // r10d\n int v102; // r11d\n int v103; // r15d\n int v104; // ecx\n int v105; // r8d\n unsigned int v106; // edx\n int v107; // r10d\n int v108; // ebx\n __int64 v109; // rdi\n int v110; // eax\n int v111; // eax\n int v112; // ebx\n unsigned int v113; // edx\n int v114; // r8d\n __int64 v115; // rdi\n int v116; // eax\n int v117; // eax\n int v118; // ebx\n int v119; // r12d\n int j; // r14d\n int v121; // edx\n int v122; // r9d\n int v123; // r8d\n int v124; // ebx\n int v125; // r10d\n int v126; // edx\n unsigned int v127; // esi\n int v128; // r11d\n int v129; // r10d\n int v130; // ecx\n int v131; // eax\n int v132; // eax\n int v133; // ecx\n unsigned int v134; // esi\n int v135; // r11d\n int v136; // eax\n int v137; // eax\n int v138; // r8d\n int v139; // r9d\n int v140; // esi\n int v141; // r10d\n unsigned int v142; // ecx\n int v143; // r11d\n int v144; // edx\n int v145; // eax\n int v146; // eax\n int v147; // edx\n unsigned int v148; // ecx\n int v149; // r10d\n int v150; // eax\n int v151; // eax\n int v153; // [rsp+8h] [rbp-70h]\n int v154; // [rsp+8h] [rbp-70h]\n unsigned int v155; // [rsp+8h] [rbp-70h]\n int v156; // [rsp+8h] [rbp-70h]\n unsigned int v157; // [rsp+8h] [rbp-70h]\n int v158; // [rsp+8h] [rbp-70h]\n int v159; // [rsp+8h] [rbp-70h]\n unsigned int v160; // [rsp+8h] [rbp-70h]\n int v161; // [rsp+8h] [rbp-70h]\n unsigned int v162; // [rsp+8h] [rbp-70h]\n int v163; // [rsp+8h] [rbp-70h]\n int v164; // [rsp+8h] [rbp-70h]\n unsigned int v165; // [rsp+8h] [rbp-70h]\n unsigned int v166; // [rsp+8h] [rbp-70h]\n unsigned int v167; // [rsp+8h] [rbp-70h]\n int v168; // [rsp+8h] [rbp-70h]\n int v169; // [rsp+8h] [rbp-70h]\n unsigned int v170; // [rsp+8h] [rbp-70h]\n int v171; // [rsp+8h] [rbp-70h]\n unsigned int v172; // [rsp+8h] [rbp-70h]\n int v173; // [rsp+Ch] [rbp-6Ch]\n int v174; // [rsp+10h] [rbp-68h]\n int v175; // [rsp+10h] [rbp-68h]\n int v176; // [rsp+10h] [rbp-68h]\n int v177; // [rsp+10h] [rbp-68h]\n int v178; // [rsp+10h] [rbp-68h]\n int v179; // [rsp+14h] [rbp-64h]\n int v180; // [rsp+14h] [rbp-64h]\n int v181; // [rsp+14h] [rbp-64h]\n int v182; // [rsp+14h] [rbp-64h]\n int v183; // [rsp+14h] [rbp-64h]\n int v184; // [rsp+14h] [rbp-64h]\n int v185; // [rsp+18h] [rbp-60h]\n unsigned int v186; // [rsp+1Ch] [rbp-5Ch]\n int v187; // [rsp+20h] [rbp-58h]\n int v188; // [rsp+20h] [rbp-58h]\n unsigned int v189; // [rsp+20h] [rbp-58h]\n unsigned int v190; // [rsp+20h] [rbp-58h]\n unsigned int v191; // [rsp+20h] [rbp-58h]\n unsigned int v192; // [rsp+20h] [rbp-58h]\n int v193; // [rsp+20h] [rbp-58h]\n int v194; // [rsp+20h] [rbp-58h]\n int v195; // [rsp+20h] [rbp-58h]\n int v196; // [rsp+20h] [rbp-58h]\n int v197; // [rsp+20h] [rbp-58h]\n int v198; // [rsp+20h] [rbp-58h]\n int v199; // [rsp+20h] [rbp-58h]\n unsigned int v200; // [rsp+20h] [rbp-58h]\n int v201; // [rsp+20h] [rbp-58h]\n int v202; // [rsp+24h] [rbp-54h]\n unsigned int v203; // [rsp+24h] [rbp-54h]\n int v204; // [rsp+24h] [rbp-54h]\n unsigned int v205; // [rsp+24h] [rbp-54h]\n unsigned int v206; // [rsp+24h] [rbp-54h]\n int v207; // [rsp+24h] [rbp-54h]\n unsigned int v208; // [rsp+24h] [rbp-54h]\n int v209; // [rsp+24h] [rbp-54h]\n int v210; // [rsp+24h] [rbp-54h]\n int v211; // [rsp+24h] [rbp-54h]\n int v212; // [rsp+24h] [rbp-54h]\n int v213; // [rsp+24h] [rbp-54h]\n unsigned int v214; // [rsp+24h] [rbp-54h]\n unsigned int v215; // [rsp+24h] [rbp-54h]\n int v216; // [rsp+24h] [rbp-54h]\n int v217; // [rsp+24h] [rbp-54h]\n int v218; // [rsp+24h] [rbp-54h]\n int v219; // [rsp+24h] [rbp-54h]\n int v220; // [rsp+24h] [rbp-54h]\n int v221; // [rsp+24h] [rbp-54h]\n int v222; // [rsp+24h] [rbp-54h]\n int v223; // [rsp+24h] [rbp-54h]\n int v224; // [rsp+24h] [rbp-54h]\n int v225; // [rsp+24h] [rbp-54h]\n unsigned int v226; // [rsp+24h] [rbp-54h]\n int v227; // [rsp+24h] [rbp-54h]\n int v228; // [rsp+24h] [rbp-54h]\n int v229; // [rsp+24h] [rbp-54h]\n int v230; // [rsp+28h] [rbp-50h]\n int v231; // [rsp+28h] [rbp-50h]\n unsigned int v232; // [rsp+28h] [rbp-50h]\n int v233; // [rsp+28h] [rbp-50h]\n int v234; // [rsp+28h] [rbp-50h]\n int v235; // [rsp+28h] [rbp-50h]\n int v236; // [rsp+28h] [rbp-50h]\n int v237; // [rsp+28h] [rbp-50h]\n int v238; // [rsp+28h] [rbp-50h]\n unsigned int v239; // [rsp+28h] [rbp-50h]\n int v240; // [rsp+28h] [rbp-50h]\n int v241; // [rsp+28h] [rbp-50h]\n int v242; // [rsp+28h] [rbp-50h]\n int v243; // [rsp+28h] [rbp-50h]\n int v244; // [rsp+28h] [rbp-50h]\n int v245; // [rsp+28h] [rbp-50h]\n int v246; // [rsp+28h] [rbp-50h]\n int v247; // [rsp+28h] [rbp-50h]\n int v248; // [rsp+28h] [rbp-50h]\n int v249; // [rsp+28h] [rbp-50h]\n int v250; // [rsp+28h] [rbp-50h]\n int v251; // [rsp+28h] [rbp-50h]\n int v252; // [rsp+28h] [rbp-50h]\n int v253; // [rsp+28h] [rbp-50h]\n int v254; // [rsp+28h] [rbp-50h]\n int v255; // [rsp+28h] [rbp-50h]\n int v256; // [rsp+28h] [rbp-50h]\n unsigned int v257; // [rsp+2Ch] [rbp-4Ch]\n int v258; // [rsp+2Ch] [rbp-4Ch]\n int v259; // [rsp+2Ch] [rbp-4Ch]\n int v260; // [rsp+2Ch] [rbp-4Ch]\n int v261; // [rsp+2Ch] [rbp-4Ch]\n int v262; // [rsp+2Ch] [rbp-4Ch]\n int v263; // [rsp+2Ch] [rbp-4Ch]\n int v264; // [rsp+2Ch] [rbp-4Ch]\n int v265; // [rsp+2Ch] [rbp-4Ch]\n int v266; // [rsp+2Ch] [rbp-4Ch]\n int v267; // [rsp+2Ch] [rbp-4Ch]\n int v268; // [rsp+2Ch] [rbp-4Ch]\n int v269; // [rsp+2Ch] [rbp-4Ch]\n int v270; // [rsp+2Ch] [rbp-4Ch]\n int v271; // [rsp+2Ch] [rbp-4Ch]\n int v272; // [rsp+2Ch] [rbp-4Ch]\n int v273; // [rsp+2Ch] [rbp-4Ch]\n int v274; // [rsp+2Ch] [rbp-4Ch]\n int v275; // [rsp+2Ch] [rbp-4Ch]\n int v276; // [rsp+2Ch] [rbp-4Ch]\n int v277; // [rsp+2Ch] [rbp-4Ch]\n int v278; // [rsp+2Ch] [rbp-4Ch]\n int v279; // [rsp+2Ch] [rbp-4Ch]\n int v280; // [rsp+2Ch] [rbp-4Ch]\n int v281; // [rsp+2Ch] [rbp-4Ch]\n int v282; // [rsp+30h] [rbp-48h]\n int v283; // [rsp+30h] [rbp-48h]\n int v284; // [rsp+30h] [rbp-48h]\n int v285; // [rsp+30h] [rbp-48h]\n int v286; // [rsp+30h] [rbp-48h]\n int v287; // [rsp+30h] [rbp-48h]\n int v288; // [rsp+30h] [rbp-48h]\n int v289; // [rsp+30h] [rbp-48h]\n int v290; // [rsp+30h] [rbp-48h]\n int v291; // [rsp+30h] [rbp-48h]\n int v292; // [rsp+30h] [rbp-48h]\n int v293; // [rsp+30h] [rbp-48h]\n int v294; // [rsp+30h] [rbp-48h]\n int v295; // [rsp+30h] [rbp-48h]\n int v296; // [rsp+30h] [rbp-48h]\n int v297; // [rsp+30h] [rbp-48h]\n int v298; // [rsp+30h] [rbp-48h]\n int v299; // [rsp+30h] [rbp-48h]\n int v300; // [rsp+30h] [rbp-48h]\n int v301; // [rsp+30h] [rbp-48h]\n int v302; // [rsp+30h] [rbp-48h]\n int v303; // [rsp+30h] [rbp-48h]\n int v304; // [rsp+30h] [rbp-48h]\n int v305; // [rsp+30h] [rbp-48h]\n int v306; // [rsp+34h] [rbp-44h]\n int v307; // [rsp+34h] [rbp-44h]\n int v308; // [rsp+34h] [rbp-44h]\n int v309; // [rsp+34h] [rbp-44h]\n int v310; // [rsp+34h] [rbp-44h]\n int v311; // [rsp+34h] [rbp-44h]\n int v312; // [rsp+34h] [rbp-44h]\n int v313; // [rsp+34h] [rbp-44h]\n int v314; // [rsp+34h] [rbp-44h]\n int v315; // [rsp+34h] [rbp-44h]\n int v316; // [rsp+34h] [rbp-44h]\n int v317; // [rsp+34h] [rbp-44h]\n int v318; // [rsp+34h] [rbp-44h]\n int v319; // [rsp+34h] [rbp-44h]\n int v320; // [rsp+38h] [rbp-40h]\n int v321; // [rsp+38h] [rbp-40h]\n int v322; // [rsp+38h] [rbp-40h]\n int v323; // [rsp+38h] [rbp-40h]\n int v324; // [rsp+3Ch] [rbp-3Ch]\n\n v186 = 0;\n if ( a1 <= 0 )\n return v186;\n v185 = 0;\n v173 = 1;\n v1 = a1 - 1;\nLABEL_3:\n if ( v1 <= 1 )\n goto LABEL_202;\n do\n {\n v174 = 0;\n v187 = v1 - 1;\n v2 = 0;\n v3 = 1;\n v4 = v1 - 1;\n while ( 1 )\n {\n if ( v4 > 1 )\n {\n v179 = v3;\n --v4;\n v5 = 0;\n v6 = v4;\n v7 = 1;\n v8 = 0;\n while ( 1 )\n {\nLABEL_7:\n if ( v6 > 1 )\n {\n --v6;\n v153 = v5;\n v9 = 0;\n v10 = v6;\n v11 = 1;\n v12 = 0;\n while ( 1 )\n {\n if ( v10 <= 1 )\n {\n v9 += v11;\n if ( !v10 )\n {\n v5 = v153 + 1;\n v8 += v7 * v9;\n goto LABEL_29;\n }\n ++v12;\n v10 = 0;\n }\n else\n {\n --v10;\n v13 = 0;\n v14 = 0;\n v15 = 1;\n v16 = v10;\nLABEL_11:\n if ( v16 > 1 )\n {\nLABEL_12:\n v17 = (unsigned int)v16;\n v324 = v10;\n --v16;\n v306 = v9;\n v282 = v8;\n v257 = v13;\n v230 = v14;\n v202 = v15;\n v18 = sub_11F0(v17);\n v8 = v282;\n v9 = v306;\n v10 = v324;\n v13 = v257 + 1;\n v14 = v202 * v18 + v230;\n goto LABEL_13;\n }\n while ( 1 )\n {\n v14 += v15;\n ++v13;\n if ( !v16 )\n break;\n v16 = 0;\nLABEL_13:\n if ( v13 == 1 )\n {\n v15 = 1;\n goto LABEL_11;\n }\n v320 = v10;\n v283 = v9;\n v258 = v8;\n v231 = v14;\n v203 = v13;\n v19 = sub_11F0(v13);\n v13 = v203;\n v14 = v231;\n v8 = v258;\n v9 = v283;\n v15 = v19;\n v10 = v320;\n if ( v16 > 1 )\n goto LABEL_12;\n }\n ++v12;\n v9 += v11 * v14;\n }\n if ( v12 == 1 )\n {\n v11 = 1;\n }\n else\n {\n v20 = v12 - 1;\n v11 = 0;\n v21 = 0;\n v22 = 1;\nLABEL_20:\n if ( v20 > 1 )\n {\nLABEL_21:\n v23 = (unsigned int)v20--;\n v307 = v10;\n v284 = v9;\n v259 = v8;\n v232 = v21;\n v204 = v22;\n v24 = sub_11F0(v23);\n v8 = v259;\n v9 = v284;\n v10 = v307;\n v21 = v232 + 1;\n v11 += v204 * v24;\n goto LABEL_22;\n }\n while ( 1 )\n {\n v11 += v22;\n ++v21;\n if ( !v20 )\n break;\n v20 = 0;\nLABEL_22:\n if ( v21 == 1 )\n {\n v22 = 1;\n goto LABEL_20;\n }\n v285 = v10;\n v260 = v9;\n v233 = v8;\n v205 = v21;\n v25 = sub_11F0(v21);\n v21 = v205;\n v8 = v233;\n v9 = v260;\n v10 = v285;\n v22 = v25;\n if ( v20 > 1 )\n goto LABEL_21;\n }\n }\n }\n }\n v8 += v7;\n if ( !v6 )\n break;\n ++v5;\n v6 = 0;\nLABEL_29:\n if ( v5 != 1 )\n {\n v26 = v5 - 1;\n v7 = 0;\n v27 = 0;\n v28 = 1;\n while ( 1 )\n {\n if ( v26 <= 1 )\n {\n v7 += v28;\n if ( !v26 )\n goto LABEL_7;\n ++v27;\n v26 = 0;\n }\n else\n {\n v29 = v26 - 1;\n v30 = 0;\n v31 = 0;\n v32 = 1;\n v33 = v29;\nLABEL_33:\n if ( v33 > 1 )\n {\nLABEL_34:\n v34 = (unsigned int)v33;\n v321 = v29;\n --v33;\n v308 = v27;\n v286 = v8;\n v234 = v32;\n v206 = v31;\n v154 = v30;\n v35 = sub_11F0(v34);\n v8 = v286;\n v27 = v308;\n v29 = v321;\n v31 = v206 + 1;\n v30 = v234 * v35 + v154;\n goto LABEL_35;\n }\n while ( 1 )\n {\n v30 += v32;\n ++v31;\n if ( !v33 )\n break;\n v33 = 0;\nLABEL_35:\n if ( v31 == 1 )\n {\n v32 = 1;\n goto LABEL_33;\n }\n v309 = v29;\n v287 = v27;\n v261 = v8;\n v207 = v30;\n v155 = v31;\n v36 = sub_11F0(v31);\n v31 = v155;\n v30 = v207;\n v8 = v261;\n v32 = v36;\n v27 = v287;\n v29 = v309;\n if ( v33 > 1 )\n goto LABEL_34;\n }\n ++v27;\n v26 = v29;\n v7 += v28 * v30;\n }\n if ( v27 == 1 )\n {\n v28 = 1;\n }\n else\n {\n v37 = v27 - 1;\n v38 = 0;\n v28 = 0;\n v39 = 1;\nLABEL_42:\n if ( v37 > 1 )\n {\nLABEL_43:\n v40 = (unsigned int)v37;\n v310 = v26;\n --v37;\n v288 = v27;\n v262 = v8;\n v208 = v38;\n v156 = v39;\n v41 = sub_11F0(v40);\n v8 = v262;\n v27 = v288;\n v26 = v310;\n v38 = v208 + 1;\n v28 += v156 * v41;\n goto LABEL_44;\n }\n while ( 1 )\n {\n v28 += v39;\n ++v38;\n if ( !v37 )\n break;\n v37 = 0;\nLABEL_44:\n if ( v38 == 1 )\n {\n v39 = 1;\n goto LABEL_42;\n }\n v289 = v26;\n v263 = v27;\n v235 = v8;\n v157 = v38;\n v42 = sub_11F0(v38);\n v38 = v157;\n v8 = v235;\n v27 = v263;\n v39 = v42;\n v26 = v289;\n if ( v37 > 1 )\n goto LABEL_43;\n }\n }\n }\n }\n v7 = 1;\n }\n ++v2;\n v174 += v8 * v179;\n goto LABEL_53;\n }\n v174 += v3;\n if ( !v4 )\n break;\n ++v2;\n v4 = 0;\nLABEL_53:\n if ( v2 == 1 )\n {\n v3 = 1;\n }\n else\n {\n v43 = v2 - 1;\n v3 = 0;\n v44 = 0;\n for ( i = 1; ; i = 1 )\n {\nLABEL_55:\n if ( v43 > 1 )\n {\n v46 = v43 - 1;\n v47 = 0;\n v48 = 0;\n v49 = 1;\n v158 = v46;\n v50 = v46;\n while ( 1 )\n {\n if ( v50 <= 1 )\n {\n v47 += v49;\n if ( !v50 )\n {\n ++v44;\n v43 = v158;\n v3 += i * v47;\n goto LABEL_77;\n }\n ++v48;\n v50 = 0;\n }\n else\n {\n v51 = v50 - 1;\n v52 = 0;\n v53 = 0;\n v54 = 1;\n v55 = v51;\nLABEL_59:\n if ( v55 > 1 )\n {\nLABEL_60:\n v322 = v51;\n v311 = v47;\n v290 = v48;\n v236 = v52;\n v209 = v54;\n v180 = v55;\n v56 = sub_11F0((unsigned int)v55);\n v48 = v290;\n v47 = v311;\n v51 = v322;\n ++v53;\n v55 = v180 - 1;\n v52 = v209 * v56 + v236;\n goto LABEL_61;\n }\n while ( 1 )\n {\n v52 += v54;\n ++v53;\n if ( !v55 )\n break;\n v55 = 0;\nLABEL_61:\n if ( v53 == 1 )\n {\n v54 = 1;\n goto LABEL_59;\n }\n v312 = v51;\n v291 = v47;\n v264 = v48;\n v237 = v55;\n v210 = v52;\n v57 = sub_11F0(v53);\n v55 = v237;\n v52 = v210;\n v48 = v264;\n v54 = v57;\n v47 = v291;\n v51 = v312;\n if ( v237 > 1 )\n goto LABEL_60;\n }\n ++v48;\n v50 = v51;\n v47 += v49 * v52;\n }\n if ( v48 == 1 )\n {\n v49 = 1;\n }\n else\n {\n v58 = v48 - 1;\n v49 = 0;\n v59 = 0;\n v60 = 1;\nLABEL_68:\n if ( v58 > 1 )\n {\nLABEL_69:\n v313 = v50;\n v292 = v47;\n v265 = v48;\n v211 = v60;\n v181 = v58;\n v61 = sub_11F0((unsigned int)v58);\n v48 = v265;\n v47 = v292;\n v50 = v313;\n ++v59;\n v58 = v181 - 1;\n v49 += v211 * v61;\n goto LABEL_70;\n }\n while ( 1 )\n {\n v49 += v60;\n ++v59;\n if ( !v58 )\n break;\n v58 = 0;\nLABEL_70:\n if ( v59 == 1 )\n {\n v60 = 1;\n goto LABEL_68;\n }\n v293 = v50;\n v266 = v47;\n v238 = v48;\n v212 = v58;\n v62 = sub_11F0(v59);\n v58 = v212;\n v48 = v238;\n v47 = v266;\n v60 = v62;\n v50 = v293;\n if ( v212 > 1 )\n goto LABEL_69;\n }\n }\n }\n }\n v3 += i;\n if ( !v43 )\n break;\n ++v44;\n v43 = 0;\nLABEL_77:\n if ( v44 != 1 )\n {\n v63 = v44 - 1;\n i = 0;\n v64 = 0;\n v65 = 1;\n while ( 1 )\n {\n if ( v63 <= 1 )\n {\n i += v65;\n if ( !v63 )\n goto LABEL_55;\n ++v64;\n v63 = 0;\n }\n else\n {\n --v63;\n v66 = 0;\n v67 = 0;\n v68 = 1;\n v69 = v63;\nLABEL_81:\n if ( v69 > 1 )\n {\nLABEL_82:\n v314 = v63;\n v294 = v64;\n v267 = v68;\n v239 = v67;\n v213 = v66;\n v159 = v69;\n v70 = sub_11F0((unsigned int)v69);\n v64 = v294;\n v63 = v314;\n v67 = v239 + 1;\n v69 = v159 - 1;\n v66 = v267 * v70 + v213;\n goto LABEL_83;\n }\n while ( 1 )\n {\n v66 += v68;\n ++v67;\n if ( !v69 )\n break;\n v69 = 0;\nLABEL_83:\n if ( v67 == 1 )\n {\n v68 = 1;\n goto LABEL_81;\n }\n v295 = v63;\n v268 = v64;\n v240 = v66;\n v182 = v69;\n v160 = v67;\n v71 = sub_11F0(v67);\n v69 = v182;\n v67 = v160;\n v66 = v240;\n v68 = v71;\n v64 = v268;\n v63 = v295;\n if ( v182 > 1 )\n goto LABEL_82;\n }\n ++v64;\n i += v65 * v66;\n }\n if ( v64 == 1 )\n {\n v65 = 1;\n }\n else\n {\n v72 = v64 - 1;\n v65 = 0;\n v73 = 0;\n v74 = 1;\nLABEL_90:\n if ( v72 > 1 )\n {\nLABEL_91:\n v296 = v63;\n v269 = v64;\n v241 = v74;\n v214 = v73;\n v161 = v72;\n v75 = sub_11F0((unsigned int)v72);\n v64 = v269;\n v63 = v296;\n v73 = v214 + 1;\n v72 = v161 - 1;\n v65 += v241 * v75;\n goto LABEL_92;\n }\n while ( 1 )\n {\n v65 += v74;\n ++v73;\n if ( !v72 )\n break;\n v72 = 0;\nLABEL_92:\n if ( v73 == 1 )\n {\n v74 = 1;\n goto LABEL_90;\n }\n v270 = v63;\n v242 = v64;\n v183 = v72;\n v162 = v73;\n v76 = sub_11F0(v73);\n v72 = v183;\n v73 = v162;\n v64 = v242;\n v74 = v76;\n v63 = v270;\n if ( v183 > 1 )\n goto LABEL_91;\n }\n }\n }\n }\n }\n }\n }\n ++v185;\n v186 += v174 * v173;\n v1 = v187;\n if ( v185 == 1 )\n {\nLABEL_204:\n v173 = 1;\n goto LABEL_3;\n }\nLABEL_103:\n v173 = 0;\n v184 = v1;\n v77 = 0;\n v78 = 1;\n v79 = v185 - 1;\n while ( 2 )\n {\n if ( v79 > 1 )\n {\n v175 = v78;\n --v79;\n v80 = 0;\n v81 = v79;\n v82 = 1;\n v83 = 0;\n while ( 1 )\n {\nLABEL_106:\n if ( v81 > 1 )\n {\n --v81;\n v163 = v80;\n v84 = 0;\n v85 = v81;\n v86 = 1;\n v87 = 0;\n while ( 1 )\n {\n if ( v85 <= 1 )\n {\n v84 += v86;\n if ( !v85 )\n {\n v80 = v163 + 1;\n v83 += v82 * v84;\n goto LABEL_128;\n }\n ++v87;\n v85 = 0;\n }\n else\n {\n --v85;\n v88 = 0;\n v89 = 0;\n v90 = 1;\n v91 = v85;\nLABEL_110:\n if ( v91 > 1 )\n {\nLABEL_111:\n v92 = (unsigned int)v91;\n v323 = v85;\n --v91;\n v315 = v84;\n v271 = v83;\n v243 = v90;\n v215 = v89;\n v188 = v88;\n v93 = sub_11F0(v92);\n v83 = v271;\n v84 = v315;\n v85 = v323;\n v89 = v215 + 1;\n v88 = v243 * v93 + v188;\n goto LABEL_112;\n }\n while ( 1 )\n {\n v88 += v90;\n ++v89;\n if ( !v91 )\n break;\n v91 = 0;\nLABEL_112:\n if ( v89 == 1 )\n {\n v90 = 1;\n goto LABEL_110;\n }\n v316 = v85;\n v297 = v84;\n v244 = v83;\n v216 = v88;\n v189 = v89;\n v94 = sub_11F0(v89);\n v89 = v189;\n v88 = v216;\n v83 = v244;\n v90 = v94;\n v84 = v297;\n v85 = v316;\n if ( v91 > 1 )\n goto LABEL_111;\n }\n ++v87;\n v84 += v86 * v88;\n }\n if ( v87 == 1 )\n {\n v86 = 1;\n }\n else\n {\n v95 = v87 - 1;\n v86 = 0;\n v96 = 0;\n v97 = 1;\nLABEL_119:\n if ( v95 > 1 )\n {\nLABEL_120:\n v98 = (unsigned int)v95;\n v317 = v84;\n --v95;\n v272 = v85;\n v245 = v83;\n v217 = v97;\n v190 = v96;\n v99 = sub_11F0(v98);\n v83 = v245;\n v85 = v272;\n v84 = v317;\n v96 = v190 + 1;\n v86 += v217 * v99;\n goto LABEL_121;\n }\n while ( 1 )\n {\n v86 += v97;\n ++v96;\n if ( !v95 )\n break;\n v95 = 0;\nLABEL_121:\n if ( v96 == 1 )\n {\n v97 = 1;\n goto LABEL_119;\n }\n v298 = v84;\n v246 = v85;\n v218 = v83;\n v191 = v96;\n v100 = sub_11F0(v96);\n v96 = v191;\n v83 = v218;\n v85 = v246;\n v97 = v100;\n v84 = v298;\n if ( v95 > 1 )\n goto LABEL_120;\n }\n }\n }\n }\n v83 += v82;\n if ( !v81 )\n break;\n ++v80;\n v81 = 0;\nLABEL_128:\n if ( v80 != 1 )\n {\n v101 = v80 - 1;\n v102 = 0;\n v82 = 0;\n v103 = 1;\n while ( 1 )\n {\n if ( v101 <= 1 )\n {\n v82 += v103;\n if ( !v101 )\n goto LABEL_106;\n ++v102;\n v101 = 0;\n }\n else\n {\n v104 = v101 - 1;\n v105 = 0;\n v106 = 0;\n v107 = 1;\n v108 = v104;\nLABEL_132:\n if ( v108 > 1 )\n {\nLABEL_133:\n v109 = (unsigned int)v108;\n v318 = v104;\n --v108;\n v299 = v102;\n v247 = v83;\n v219 = v107;\n v192 = v106;\n v164 = v105;\n v110 = sub_11F0(v109);\n v83 = v247;\n v102 = v299;\n v104 = v318;\n v106 = v192 + 1;\n v105 = v219 * v110 + v164;\n goto LABEL_134;\n }\n while ( 1 )\n {\n v105 += v107;\n ++v106;\n if ( !v108 )\n break;\n v108 = 0;\nLABEL_134:\n if ( v106 == 1 )\n {\n v107 = 1;\n goto LABEL_132;\n }\n v300 = v104;\n v273 = v102;\n v220 = v83;\n v193 = v105;\n v165 = v106;\n v111 = sub_11F0(v106);\n v106 = v165;\n v105 = v193;\n v83 = v220;\n v107 = v111;\n v102 = v273;\n v104 = v300;\n if ( v108 > 1 )\n goto LABEL_133;\n }\n ++v102;\n v101 = v104;\n v82 += v103 * v105;\n }\n if ( v102 == 1 )\n {\n v103 = 1;\n }\n else\n {\n v112 = v102 - 1;\n v113 = 0;\n v103 = 0;\n v114 = 1;\nLABEL_141:\n if ( v112 > 1 )\n {\nLABEL_142:\n v115 = (unsigned int)v112;\n v301 = v102;\n --v112;\n v248 = v83;\n v221 = v101;\n v194 = v114;\n v166 = v113;\n v116 = sub_11F0(v115);\n v101 = v221;\n v83 = v248;\n v102 = v301;\n v113 = v166 + 1;\n v103 += v194 * v116;\n goto LABEL_143;\n }\n while ( 1 )\n {\n v103 += v114;\n ++v113;\n if ( !v112 )\n break;\n v112 = 0;\nLABEL_143:\n if ( v113 == 1 )\n {\n v114 = 1;\n goto LABEL_141;\n }\n v274 = v102;\n v222 = v83;\n v195 = v101;\n v167 = v113;\n v117 = sub_11F0(v113);\n v113 = v167;\n v101 = v195;\n v83 = v222;\n v114 = v117;\n v102 = v274;\n if ( v112 > 1 )\n goto LABEL_142;\n }\n }\n }\n }\n v82 = 1;\n }\n ++v77;\n v173 += v83 * v175;\nLABEL_152:\n if ( v77 == 1 )\n {\n v78 = 1;\n }\n else\n {\n v118 = v77 - 1;\n v78 = 0;\n v119 = 0;\n for ( j = 1; ; j = 1 )\n {\nLABEL_154:\n if ( v118 > 1 )\n {\n v121 = v118 - 1;\n v122 = 0;\n v123 = 0;\n v124 = 1;\n v168 = v121;\n v125 = v121;\n while ( 1 )\n {\n if ( v125 <= 1 )\n {\n v123 += v124;\n if ( !v125 )\n {\n ++v119;\n v118 = v168;\n v78 += j * v123;\n goto LABEL_176;\n }\n ++v122;\n v125 = 0;\n }\n else\n {\n v126 = v125 - 1;\n v127 = 0;\n v128 = 0;\n v129 = 1;\n v130 = v126;\nLABEL_158:\n if ( v130 > 1 )\n {\nLABEL_159:\n v319 = v126;\n v302 = v122;\n v275 = v123;\n v249 = v129;\n v196 = v128;\n v176 = v130;\n v131 = sub_11F0((unsigned int)v130);\n v123 = v275;\n v122 = v302;\n v126 = v319;\n ++v127;\n v130 = v176 - 1;\n v128 = v249 * v131 + v196;\n goto LABEL_160;\n }\n while ( 1 )\n {\n v128 += v129;\n ++v127;\n if ( !v130 )\n break;\n v130 = 0;\nLABEL_160:\n if ( v127 == 1 )\n {\n v129 = 1;\n goto LABEL_158;\n }\n v303 = v126;\n v276 = v122;\n v250 = v123;\n v223 = v128;\n v197 = v130;\n v132 = sub_11F0(v127);\n v130 = v197;\n v128 = v223;\n v123 = v250;\n v129 = v132;\n v122 = v276;\n v126 = v303;\n if ( v197 > 1 )\n goto LABEL_159;\n }\n ++v122;\n v125 = v126;\n v123 += v124 * v128;\n }\n if ( v122 == 1 )\n {\n v124 = 1;\n }\n else\n {\n v133 = v122 - 1;\n v124 = 0;\n v134 = 0;\n v135 = 1;\nLABEL_167:\n if ( v133 > 1 )\n {\nLABEL_168:\n v304 = v122;\n v277 = v123;\n v251 = v125;\n v224 = v135;\n v177 = v133;\n v136 = sub_11F0((unsigned int)v133);\n v125 = v251;\n v123 = v277;\n v122 = v304;\n ++v134;\n v133 = v177 - 1;\n v124 += v224 * v136;\n goto LABEL_169;\n }\n while ( 1 )\n {\n v124 += v135;\n ++v134;\n if ( !v133 )\n break;\n v133 = 0;\nLABEL_169:\n if ( v134 == 1 )\n {\n v135 = 1;\n goto LABEL_167;\n }\n v278 = v122;\n v252 = v123;\n v225 = v125;\n v198 = v133;\n v137 = sub_11F0(v134);\n v133 = v198;\n v125 = v225;\n v123 = v252;\n v135 = v137;\n v122 = v278;\n if ( v198 > 1 )\n goto LABEL_168;\n }\n }\n }\n }\n v78 += j;\n if ( !v118 )\n break;\n ++v119;\n v118 = 0;\nLABEL_176:\n if ( v119 != 1 )\n {\n v138 = v119 - 1;\n j = 0;\n v139 = 0;\n v140 = 1;\n while ( 1 )\n {\n if ( v138 <= 1 )\n {\n j += v140;\n if ( !v138 )\n goto LABEL_154;\n ++v139;\n v138 = 0;\n }\n else\n {\n --v138;\n v141 = 0;\n v142 = 0;\n v143 = 1;\n v144 = v138;\nLABEL_180:\n if ( v144 > 1 )\n {\nLABEL_181:\n v305 = v138;\n v279 = v139;\n v253 = v143;\n v226 = v142;\n v199 = v141;\n v169 = v144;\n v145 = sub_11F0((unsigned int)v144);\n v139 = v279;\n v138 = v305;\n v142 = v226 + 1;\n v144 = v169 - 1;\n v141 = v253 * v145 + v199;\n goto LABEL_182;\n }\n while ( 1 )\n {\n v141 += v143;\n ++v142;\n if ( !v144 )\n break;\n v144 = 0;\nLABEL_182:\n if ( v142 == 1 )\n {\n v143 = 1;\n goto LABEL_180;\n }\n v280 = v138;\n v254 = v139;\n v227 = v141;\n v178 = v144;\n v170 = v142;\n v146 = sub_11F0(v142);\n v144 = v178;\n v142 = v170;\n v141 = v227;\n v143 = v146;\n v139 = v254;\n v138 = v280;\n if ( v178 > 1 )\n goto LABEL_181;\n }\n ++v139;\n j += v140 * v141;\n }\n if ( v139 == 1 )\n {\n v140 = 1;\n }\n else\n {\n v147 = v139 - 1;\n v148 = 0;\n v140 = 0;\n v149 = 1;\nLABEL_189:\n if ( v147 > 1 )\n {\nLABEL_190:\n v281 = v139;\n v255 = v138;\n v228 = v149;\n v200 = v148;\n v171 = v147;\n v150 = sub_11F0((unsigned int)v147);\n v138 = v255;\n v139 = v281;\n v148 = v200 + 1;\n v147 = v171 - 1;\n v140 += v228 * v150;\n goto LABEL_191;\n }\n while ( 1 )\n {\n v140 += v149;\n ++v148;\n if ( !v147 )\n break;\n v147 = 0;\nLABEL_191:\n if ( v148 == 1 )\n {\n v149 = 1;\n goto LABEL_189;\n }\n v256 = v139;\n v229 = v138;\n v201 = v147;\n v172 = v148;\n v151 = sub_11F0(v148);\n v147 = v201;\n v148 = v172;\n v138 = v229;\n v149 = v151;\n v139 = v256;\n if ( v201 > 1 )\n goto LABEL_190;\n }\n }\n }\n }\n }\n }\n continue;\n }\n break;\n }\n v173 += v78;\n if ( v79 )\n {\n ++v77;\n v79 = 0;\n goto LABEL_152;\n }\n v1 = v184;\n }\n while ( v184 > 1 );\nLABEL_202:\n v186 += v173;\n if ( v1 )\n {\n ++v185;\n v1 = 0;\n if ( v185 != 1 )\n goto LABEL_103;\n goto LABEL_204;\n }\n return v186;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11F0(int a1) {\n int v1;\n int v2;\n int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n int v8;\n int v9;\n int v10;\n int v11;\n int v12;\n unsigned int v13;\n int v14;\n int v15;\n int v16;\n long long v17;\n int v18;\n int v19;\n int v20;\n unsigned int v21;\n int v22;\n long long v23;\n int v24;\n int v25;\n int v26;\n int v27;\n int v28;\n int v29;\n int v30;\n unsigned int v31;\n int v32;\n int v33;\n long long v34;\n int v35;\n int v36;\n int v37;\n unsigned int v38;\n int v39;\n long long v40;\n int v41;\n int v42;\n int v43;\n int v44;\n int i;\n int v46;\n int v47;\n int v48;\n int v49;\n int v50;\n int v51;\n int v52;\n unsigned int v53;\n int v54;\n int v55;\n int v56;\n int v57;\n int v58;\n unsigned int v59;\n int v60;\n int v61;\n int v62;\n int v63;\n int v64;\n int v65;\n int v66;\n unsigned int v67;\n int v68;\n int v69;\n int v70;\n int v71;\n int v72;\n unsigned int v73;\n int v74;\n int v75;\n int v76;\n int v77;\n int v78;\n int v79;\n int v80;\n int v81;\n int v82;\n int v83;\n int v84;\n int v85;\n int v86;\n int v87;\n int v88;\n unsigned int v89;\n int v90;\n int v91;\n long long v92;\n int v93;\n int v94;\n int v95;\n unsigned int v96;\n int v97;\n long long v98;\n int v99;\n int v100;\n int v101;\n int v102;\n int v103;\n int v104;\n int v105;\n unsigned int v106;\n int v107;\n int v108;\n long long v109;\n int v110;\n int v111;\n int v112;\n unsigned int v113;\n int v114;\n long long v115;\n int v116;\n int v117;\n int v118;\n int v119;\n int j;\n int v121;\n int v122;\n int v123;\n int v124;\n int v125;\n int v126;\n unsigned int v127;\n int v128;\n int v129;\n int v130;\n int v131;\n int v132;\n int v133;\n unsigned int v134;\n int v135;\n int v136;\n int v137;\n int v138;\n int v139;\n int v140;\n int v141;\n unsigned int v142;\n int v143;\n int v144;\n int v145;\n int v146;\n int v147;\n unsigned int v148;\n int v149;\n int v150;\n int v151;\n int v153;\n int v154;\n unsigned int v155;\n int v156;\n unsigned int v157;\n int v158;\n int v159;\n unsigned int v160;\n int v161;\n unsigned int v162;\n int v163;\n int v164;\n unsigned int v165;\n unsigned int v166;\n unsigned int v167;\n int v168;\n int v169;\n unsigned int v170;\n int v171;\n unsigned int v172;\n int v173;\n int v174;\n int v175;\n int v176;\n int v177;\n int v178;\n int v179;\n int v180;\n int v181;\n int v182;\n int v183;\n int v184;\n int v185;\n unsigned int v186;\n int v187;\n int v188;\n unsigned int v189;\n unsigned int v190;\n unsigned int v191;\n unsigned int v192;\n int v193;\n int v194;\n int v195;\n int v196;\n int v197;\n int v198;\n int v199;\n unsigned int v200;\n int v201;\n int v202;\n unsigned int v203;\n int v204;\n unsigned int v205;\n unsigned int v206;\n int v207;\n unsigned int v208;\n int v209;\n int v210;\n int v211;\n int v212;\n int v213;\n unsigned int v214;\n unsigned int v215;\n int v216;\n int v217;\n int v218;\n int v219;\n int v220;\n int v221;\n int v222;\n int v223;\n int v224;\n int v225;\n unsigned int v226;\n int v227;\n int v228;\n int v229;\n int v230;\n int v231;\n unsigned int v232;\n int v233;\n int v234;\n int v235;\n int v236;\n int v237;\n int v238;\n unsigned int v239;\n int v240;\n int v241;\n int v242;\n int v243;\n int v244;\n int v245;\n int v246;\n int v247;\n int v248;\n int v249;\n int v250;\n int v251;\n int v252;\n int v253;\n int v254;\n int v255;\n int v256;\n unsigned int v257;\n int v258;\n int v259;\n int v260;\n int v261;\n int v262;\n int v263;\n int v264;\n int v265;\n int v266;\n int v267;\n int v268;\n int v269;\n int v270;\n int v271;\n int v272;\n int v273;\n int v274;\n int v275;\n int v276;\n int v277;\n int v278;\n int v279;\n int v280;\n int v281;\n int v282;\n int v283;\n int v284;\n int v285;\n int v286;\n int v287;\n int v288;\n int v289;\n int v290;\n int v291;\n int v292;\n int v293;\n int v294;\n int v295;\n int v296;\n int v297;\n int v298;\n int v299;\n int v300;\n int v301;\n int v302;\n int v303;\n int v304;\n int v305;\n int v306;\n int v307;\n int v308;\n int v309;\n int v310;\n int v311;\n int v312;\n int v313;\n int v314;\n int v315;\n int v316;\n int v317;\n int v318;\n int v319;\n int v320;\n int v321;\n int v322;\n int v323;\n int v324;\n v186 = 0;\n if (a1 <= 0) return v186;\n v185 = 0;\n v173 = 1;\n v1 = a1 - 1;\nLABEL_3:\n if (v1 <= 1) goto LABEL_202;\n do {\n v174 = 0;\n v187 = v1 - 1;\n v2 = 0;\n v3 = 1;\n v4 = v1 - 1;\n while (1) {\n if (v4 > 1) {\n v179 = v3;\n --v4;\n v5 = 0;\n v6 = v4;\n v7 = 1;\n v8 = 0;\n while (1) {\n LABEL_7:\n if (v6 > 1) {\n --v6;\n v153 = v5;\n v9 = 0;\n v10 = v6;\n v11 = 1;\n v12 = 0;\n while (1) {\n if (v10 <= 1) {\n v9 += v11;\n if (!v10) {\n v5 = v153 + 1;\n v8 += v7 * v9;\n goto LABEL_29;\n }\n ++v12;\n v10 = 0;\n } else {\n --v10;\n v13 = 0;\n v14 = 0;\n v15 = 1;\n v16 = v10;\n LABEL_11:\n if (v16 > 1) {\n LABEL_12:\n v17 = (unsigned int)v16;\n v324 = v10;\n --v16;\n v306 = v9;\n v282 = v8;\n v257 = v13;\n v230 = v14;\n v202 = v15;\n v18 = sub_11F0(v17);\n v8 = v282;\n v9 = v306;\n v10 = v324;\n v13 = v257 + 1;\n v14 = v202 * v18 + v230;\n goto LABEL_13;\n }\n while (1) {\n v14 += v15;\n ++v13;\n if (!v16) break;\n v16 = 0;\n LABEL_13:\n if (v13 == 1) {\n v15 = 1;\n goto LABEL_11;\n }\n v320 = v10;\n v283 = v9;\n v258 = v8;\n v231 = v14;\n v203 = v13;\n v19 = sub_11F0(v13);\n v13 = v203;\n v14 = v231;\n v8 = v258;\n v9 = v283;\n v15 = v19;\n v10 = v320;\n if (v16 > 1) goto LABEL_12;\n }\n ++v12;\n v9 += v11 * v14;\n }\n if (v12 == 1) {\n v11 = 1;\n } else {\n v20 = v12 - 1;\n v11 = 0;\n v21 = 0;\n v22 = 1;\n LABEL_20:\n if (v20 > 1) {\n LABEL_21:\n v23 = (unsigned int)v20--;\n v307 = v10;\n v284 = v9;\n v259 = v8;\n v232 = v21;\n v204 = v22;\n v24 = sub_11F0(v23);\n v8 = v259;\n v9 = v284;\n v10 = v307;\n v21 = v232 + 1;\n v11 += v204 * v24;\n goto LABEL_22;\n }\n while (1) {\n v11 += v22;\n ++v21;\n if (!v20) break;\n v20 = 0;\n LABEL_22:\n if (v21 == 1) {\n v22 = 1;\n goto LABEL_20;\n }\n v285 = v10;\n v260 = v9;\n v233 = v8;\n v205 = v21;\n v25 = sub_11F0(v21);\n v21 = v205;\n v8 = v233;\n v9 = v260;\n v10 = v285;\n v22 = v25;\n if (v20 > 1) goto LABEL_21;\n }\n }\n }\n }\n v8 += v7;\n if (!v6) break;\n ++v5;\n v6 = 0;\n LABEL_29:\n if (v5 != 1) {\n v26 = v5 - 1;\n v7 = 0;\n v27 = 0;\n v28 = 1;\n while (1) {\n if (v26 <= 1) {\n v7 += v28;\n if (!v26) goto LABEL_7;\n ++v27;\n v26 = 0;\n } else {\n v29 = v26 - 1;\n v30 = 0;\n v31 = 0;\n v32 = 1;\n v33 = v29;\n LABEL_33:\n if (v33 > 1) {\n LABEL_34:\n v34 = (unsigned int)v33;\n v321 = v29;\n --v33;\n v308 = v27;\n v286 = v8;\n v234 = v32;\n v206 = v31;\n v154 = v30;\n v35 = sub_11F0(v34);\n v8 = v286;\n v27 = v308;\n v29 = v321;\n v31 = v206 + 1;\n v30 = v234 * v35 + v154;\n goto LABEL_35;\n }\n while (1) {\n v30 += v32;\n ++v31;\n if (!v33) break;\n v33 = 0;\n LABEL_35:\n if (v31 == 1) {\n v32 = 1;\n goto LABEL_33;\n }\n v309 = v29;\n v287 = v27;\n v261 = v8;\n v207 = v30;\n v155 = v31;\n v36 = sub_11F0(v31);\n v31 = v155;\n v30 = v207;\n v8 = v261;\n v32 = v36;\n v27 = v287;\n v29 = v309;\n if (v33 > 1) goto LABEL_34;\n }\n ++v27;\n v26 = v29;\n v7 += v28 * v30;\n }\n if (v27 == 1) {\n v28 = 1;\n } else {\n v37 = v27 - 1;\n v38 = 0;\n v28 = 0;\n v39 = 1;\n LABEL_42:\n if (v37 > 1) {\n LABEL_43:\n v40 = (unsigned int)v37;\n v310 = v26;\n --v37;\n v288 = v27;\n v262 = v8;\n v208 = v38;\n v156 = v39;\n v41 = sub_11F0(v40);\n v8 = v262;\n v27 = v288;\n v26 = v310;\n v38 = v208 + 1;\n v28 += v156 * v41;\n goto LABEL_44;\n }\n while (1) {\n v28 += v39;\n ++v38;\n if (!v37) break;\n v37 = 0;\n LABEL_44:\n if (v38 == 1) {\n v39 = 1;\n goto LABEL_42;\n }\n v289 = v26;\n v263 = v27;\n v235 = v8;\n v157 = v38;\n v42 = sub_11F0(v38);\n v38 = v157;\n v8 = v235;\n v27 = v263;\n v39 = v42;\n v26 = v289;\n if (v37 > 1) goto LABEL_43;\n }\n }\n }\n }\n v7 = 1;\n }\n ++v2;\n v174 += v8 * v179;\n goto LABEL_53;\n }\n v174 += v3;\n if (!v4) break;\n ++v2;\n v4 = 0;\n LABEL_53:\n if (v2 == 1) {\n v3 = 1;\n } else {\n v43 = v2 - 1;\n v3 = 0;\n v44 = 0;\n for (i = 1;; i = 1) {\n LABEL_55:\n if (v43 > 1) {\n v46 = v43 - 1;\n v47 = 0;\n v48 = 0;\n v49 = 1;\n v158 = v46;\n v50 = v46;\n while (1) {\n if (v50 <= 1) {\n v47 += v49;\n if (!v50) {\n ++v44;\n v43 = v158;\n v3 += i * v47;\n goto LABEL_77;\n }\n ++v48;\n v50 = 0;\n } else {\n v51 = v50 - 1;\n v52 = 0;\n v53 = 0;\n v54 = 1;\n v55 = v51;\n LABEL_59:\n if (v55 > 1) {\n LABEL_60:\n v322 = v51;\n v311 = v47;\n v290 = v48;\n v236 = v52;\n v209 = v54;\n v180 = v55;\n v56 = sub_11F0((unsigned int)v55);\n v48 = v290;\n v47 = v311;\n v51 = v322;\n ++v53;\n v55 = v180 - 1;\n v52 = v209 * v56 + v236;\n goto LABEL_61;\n }\n while (1) {\n v52 += v54;\n ++v53;\n if (!v55) break;\n v55 = 0;\n LABEL_61:\n if (v53 == 1) {\n v54 = 1;\n goto LABEL_59;\n }\n v312 = v51;\n v291 = v47;\n v264 = v48;\n v237 = v55;\n v210 = v52;\n v57 = sub_11F0(v53);\n v55 = v237;\n v52 = v210;\n v48 = v264;\n v54 = v57;\n v47 = v291;\n v51 = v312;\n if (v237 > 1) goto LABEL_60;\n }\n ++v48;\n v50 = v51;\n v47 += v49 * v52;\n }\n if (v48 == 1) {\n v49 = 1;\n } else {\n v58 = v48 - 1;\n v49 = 0;\n v59 = 0;\n v60 = 1;\n LABEL_68:\n if (v58 > 1) {\n LABEL_69:\n v313 = v50;\n v292 = v47;\n v265 = v48;\n v211 = v60;\n v181 = v58;\n v61 = sub_11F0((unsigned int)v58);\n v48 = v265;\n v47 = v292;\n v50 = v313;\n ++v59;\n v58 = v181 - 1;\n v49 += v211 * v61;\n goto LABEL_70;\n }\n while (1) {\n v49 += v60;\n ++v59;\n if (!v58) break;\n v58 = 0;\n LABEL_70:\n if (v59 == 1) {\n v60 = 1;\n goto LABEL_68;\n }\n v293 = v50;\n v266 = v47;\n v238 = v48;\n v212 = v58;\n v62 = sub_11F0(v59);\n v58 = v212;\n v48 = v238;\n v47 = v266;\n v60 = v62;\n v50 = v293;\n if (v212 > 1) goto LABEL_69;\n }\n }\n }\n }\n v3 += i;\n if (!v43) break;\n ++v44;\n v43 = 0;\n LABEL_77:\n if (v44 != 1) {\n v63 = v44 - 1;\n i = 0;\n v64 = 0;\n v65 = 1;\n while (1) {\n if (v63 <= 1) {\n i += v65;\n if (!v63) goto LABEL_55;\n ++v64;\n v63 = 0;\n } else {\n --v63;\n v66 = 0;\n v67 = 0;\n v68 = 1;\n v69 = v63;\n LABEL_81:\n if (v69 > 1) {\n LABEL_82:\n v314 = v63;\n v294 = v64;\n v267 = v68;\n v239 = v67;\n v213 = v66;\n v159 = v69;\n v70 = sub_11F0((unsigned int)v69);\n v64 = v294;\n v63 = v314;\n v67 = v239 + 1;\n v69 = v159 - 1;\n v66 = v267 * v70 + v213;\n goto LABEL_83;\n }\n while (1) {\n v66 += v68;\n ++v67;\n if (!v69) break;\n v69 = 0;\n LABEL_83:\n if (v67 == 1) {\n v68 = 1;\n goto LABEL_81;\n }\n v295 = v63;\n v268 = v64;\n v240 = v66;\n v182 = v69;\n v160 = v67;\n v71 = sub_11F0(v67);\n v69 = v182;\n v67 = v160;\n v66 = v240;\n v68 = v71;\n v64 = v268;\n v63 = v295;\n if (v182 > 1) goto LABEL_82;\n }\n ++v64;\n i += v65 * v66;\n }\n if (v64 == 1) {\n v65 = 1;\n } else {\n v72 = v64 - 1;\n v65 = 0;\n v73 = 0;\n v74 = 1;\n LABEL_90:\n if (v72 > 1) {\n LABEL_91:\n v296 = v63;\n v269 = v64;\n v241 = v74;\n v214 = v73;\n v161 = v72;\n v75 = sub_11F0((unsigned int)v72);\n v64 = v269;\n v63 = v296;\n v73 = v214 + 1;\n v72 = v161 - 1;\n v65 += v241 * v75;\n goto LABEL_92;\n }\n while (1) {\n v65 += v74;\n ++v73;\n if (!v72) break;\n v72 = 0;\n LABEL_92:\n if (v73 == 1) {\n v74 = 1;\n goto LABEL_90;\n }\n v270 = v63;\n v242 = v64;\n v183 = v72;\n v162 = v73;\n v76 = sub_11F0(v73);\n v72 = v183;\n v73 = v162;\n v64 = v242;\n v74 = v76;\n v63 = v270;\n if (v183 > 1) goto LABEL_91;\n }\n }\n }\n }\n }\n }\n }\n ++v185;\n v186 += v174 * v173;\n v1 = v187;\n if (v185 == 1) {\n LABEL_204:\n v173 = 1;\n goto LABEL_3;\n }\n LABEL_103:\n v173 = 0;\n v184 = v1;\n v77 = 0;\n v78 = 1;\n v79 = v185 - 1;\n while (2) {\n if (v79 > 1) {\n v175 = v78;\n --v79;\n v80 = 0;\n v81 = v79;\n v82 = 1;\n v83 = 0;\n while (1) {\n LABEL_106:\n if (v81 > 1) {\n --v81;\n v163 = v80;\n v84 = 0;\n v85 = v81;\n v86 = 1;\n v87 = 0;\n while (1) {\n if (v85 <= 1) {\n v84 += v86;\n if (!v85) {\n v80 = v163 + 1;\n v83 += v82 * v84;\n goto LABEL_128;\n }\n ++v87;\n v85 = 0;\n } else {\n --v85;\n v88 = 0;\n v89 = 0;\n v90 = 1;\n v91 = v85;\n LABEL_110:\n if (v91 > 1) {\n LABEL_111:\n v92 = (unsigned int)v91;\n v323 = v85;\n --v91;\n v315 = v84;\n v271 = v83;\n v243 = v90;\n v215 = v89;\n v188 = v88;\n v93 = sub_11F0(v92);\n v83 = v271;\n v84 = v315;\n v85 = v323;\n v89 = v215 + 1;\n v88 = v243 * v93 + v188;\n goto LABEL_112;\n }\n while (1) {\n v88 += v90;\n ++v89;\n if (!v91) break;\n v91 = 0;\n LABEL_112:\n if (v89 == 1) {\n v90 = 1;\n goto LABEL_110;\n }\n v316 = v85;\n v297 = v84;\n v244 = v83;\n v216 = v88;\n v189 = v89;\n v94 = sub_11F0(v89);\n v89 = v189;\n v88 = v216;\n v83 = v244;\n v90 = v94;\n v84 = v297;\n v85 = v316;\n if (v91 > 1) goto LABEL_111;\n }\n ++v87;\n v84 += v86 * v88;\n }\n if (v87 == 1) {\n v86 = 1;\n } else {\n v95 = v87 - 1;\n v86 = 0;\n v96 = 0;\n v97 = 1;\n LABEL_119:\n if (v95 > 1) {\n LABEL_120:\n v98 = (unsigned int)v95;\n v317 = v84;\n --v95;\n v272 = v85;\n v245 = v83;\n v217 = v97;\n v190 = v96;\n v99 = sub_11F0(v98);\n v83 = v245;\n v85 = v272;\n v84 = v317;\n v96 = v190 + 1;\n v86 += v217 * v99;\n goto LABEL_121;\n }\n while (1) {\n v86 += v97;\n ++v96;\n if (!v95) break;\n v95 = 0;\n LABEL_121:\n if (v96 == 1) {\n v97 = 1;\n goto LABEL_119;\n }\n v298 = v84;\n v246 = v85;\n v218 = v83;\n v191 = v96;\n v100 = sub_11F0(v96);\n v96 = v191;\n v83 = v218;\n v85 = v246;\n v97 = v100;\n v84 = v298;\n if (v95 > 1) goto LABEL_120;\n }\n }\n }\n }\n v83 += v82;\n if (!v81) break;\n ++v80;\n v81 = 0;\n LABEL_128:\n if (v80 != 1) {\n v101 = v80 - 1;\n v102 = 0;\n v82 = 0;\n v103 = 1;\n while (1) {\n if (v101 <= 1) {\n v82 += v103;\n if (!v101) goto LABEL_106;\n ++v102;\n v101 = 0;\n } else {\n v104 = v101 - 1;\n v105 = 0;\n v106 = 0;\n v107 = 1;\n v108 = v104;\n LABEL_132:\n if (v108 > 1) {\n LABEL_133:\n v109 = (unsigned int)v108;\n v318 = v104;\n --v108;\n v299 = v102;\n v247 = v83;\n v219 = v107;\n v192 = v106;\n v164 = v105;\n v110 = sub_11F0(v109);\n v83 = v247;\n v102 = v299;\n v104 = v318;\n v106 = v192 + 1;\n v105 = v219 * v110 + v164;\n goto LABEL_134;\n }\n while (1) {\n v105 += v107;\n ++v106;\n if (!v108) break;\n v108 = 0;\n LABEL_134:\n if (v106 == 1) {\n v107 = 1;\n goto LABEL_132;\n }\n v300 = v104;\n v273 = v102;\n v220 = v83;\n v193 = v105;\n v165 = v106;\n v111 = sub_11F0(v106);\n v106 = v165;\n v105 = v193;\n v83 = v220;\n v107 = v111;\n v102 = v273;\n v104 = v300;\n if (v108 > 1) goto LABEL_133;\n }\n ++v102;\n v101 = v104;\n v82 += v103 * v105;\n }\n if (v102 == 1) {\n v103 = 1;\n } else {\n v112 = v102 - 1;\n v113 = 0;\n v103 = 0;\n v114 = 1;\n LABEL_141:\n if (v112 > 1) {\n LABEL_142:\n v115 = (unsigned int)v112;\n v301 = v102;\n --v112;\n v248 = v83;\n v221 = v101;\n v194 = v114;\n v166 = v113;\n v116 = sub_11F0(v115);\n v101 = v221;\n v83 = v248;\n v102 = v301;\n v113 = v166 + 1;\n v103 += v194 * v116;\n goto LABEL_143;\n }\n while (1) {\n v103 += v114;\n ++v113;\n if (!v112) break;\n v112 = 0;\n LABEL_143:\n if (v113 == 1) {\n v114 = 1;\n goto LABEL_141;\n }\n v274 = v102;\n v222 = v83;\n v195 = v101;\n v167 = v113;\n v117 = sub_11F0(v113);\n v113 = v167;\n v101 = v195;\n v83 = v222;\n v114 = v117;\n v102 = v274;\n if (v112 > 1) goto LABEL_142;\n }\n }\n }\n }\n v82 = 1;\n }\n ++v77;\n v173 += v83 * v175;\n LABEL_152:\n if (v77 == 1) {\n v78 = 1;\n } else {\n v118 = v77 - 1;\n v78 = 0;\n v119 = 0;\n for (j = 1;; j = 1) {\n LABEL_154:\n if (v118 > 1) {\n v121 = v118 - 1;\n v122 = 0;\n v123 = 0;\n v124 = 1;\n v168 = v121;\n v125 = v121;\n while (1) {\n if (v125 <= 1) {\n v123 += v124;\n if (!v125) {\n ++v119;\n v118 = v168;\n v78 += j * v123;\n goto LABEL_176;\n }\n ++v122;\n v125 = 0;\n } else {\n v126 = v125 - 1;\n v127 = 0;\n v128 = 0;\n v129 = 1;\n v130 = v126;\n LABEL_158:\n if (v130 > 1) {\n LABEL_159:\n v319 = v126;\n v302 = v122;\n v275 = v123;\n v249 = v129;\n v196 = v128;\n v176 = v130;\n v131 = sub_11F0((unsigned int)v130);\n v123 = v275;\n v122 = v302;\n v126 = v319;\n ++v127;\n v130 = v176 - 1;\n v128 = v249 * v131 + v196;\n goto LABEL_160;\n }\n while (1) {\n v128 += v129;\n ++v127;\n if (!v130) break;\n v130 = 0;\n LABEL_160:\n if (v127 == 1) {\n v129 = 1;\n goto LABEL_158;\n }\n v303 = v126;\n v276 = v122;\n v250 = v123;\n v223 = v128;\n v197 = v130;\n v132 = sub_11F0(v127);\n v130 = v197;\n v128 = v223;\n v123 = v250;\n v129 = v132;\n v122 = v276;\n v126 = v303;\n if (v197 > 1) goto LABEL_159;\n }\n ++v122;\n v125 = v126;\n v123 += v124 * v128;\n }\n if (v122 == 1) {\n v124 = 1;\n } else {\n v133 = v122 - 1;\n v124 = 0;\n v134 = 0;\n v135 = 1;\n LABEL_167:\n if (v133 > 1) {\n LABEL_168:\n v304 = v122;\n v277 = v123;\n v251 = v125;\n v224 = v135;\n v177 = v133;\n v136 = sub_11F0((unsigned int)v133);\n v125 = v251;\n v123 = v277;\n v122 = v304;\n ++v134;\n v133 = v177 - 1;\n v124 += v224 * v136;\n goto LABEL_169;\n }\n while (1) {\n v124 += v135;\n ++v134;\n if (!v133) break;\n v133 = 0;\n LABEL_169:\n if (v134 == 1) {\n v135 = 1;\n goto LABEL_167;\n }\n v278 = v122;\n v252 = v123;\n v225 = v125;\n v198 = v133;\n v137 = sub_11F0(v134);\n v133 = v198;\n v125 = v225;\n v123 = v252;\n v135 = v137;\n v122 = v278;\n if (v198 > 1) goto LABEL_168;\n }\n }\n }\n }\n v78 += j;\n if (!v118) break;\n ++v119;\n v118 = 0;\n LABEL_176:\n if (v119 != 1) {\n v138 = v119 - 1;\n j = 0;\n v139 = 0;\n v140 = 1;\n while (1) {\n if (v138 <= 1) {\n j += v140;\n if (!v138) goto LABEL_154;\n ++v139;\n v138 = 0;\n } else {\n --v138;\n v141 = 0;\n v142 = 0;\n v143 = 1;\n v144 = v138;\n LABEL_180:\n if (v144 > 1) {\n LABEL_181:\n v305 = v138;\n v279 = v139;\n v253 = v143;\n v226 = v142;\n v199 = v141;\n v169 = v144;\n v145 = sub_11F0((unsigned int)v144);\n v139 = v279;\n v138 = v305;\n v142 = v226 + 1;\n v144 = v169 - 1;\n v141 = v253 * v145 + v199;\n goto LABEL_182;\n }\n while (1) {\n v141 += v143;\n ++v142;\n if (!v144) break;\n v144 = 0;\n LABEL_182:\n if (v142 == 1) {\n v143 = 1;\n goto LABEL_180;\n }\n v280 = v138;\n v254 = v139;\n v227 = v141;\n v178 = v144;\n v170 = v142;\n v146 = sub_11F0(v142);\n v144 = v178;\n v142 = v170;\n v141 = v227;\n v143 = v146;\n v139 = v254;\n v138 = v280;\n if (v178 > 1) goto LABEL_181;\n }\n ++v139;\n j += v140 * v141;\n }\n if (v139 == 1) {\n v140 = 1;\n } else {\n v147 = v139 - 1;\n v148 = 0;\n v140 = 0;\n v149 = 1;\n LABEL_189:\n if (v147 > 1) {\n LABEL_190:\n v281 = v139;\n v255 = v138;\n v228 = v149;\n v200 = v148;\n v171 = v147;\n v150 = sub_11F0((unsigned int)v147);\n v138 = v255;\n v139 = v281;\n v148 = v200 + 1;\n v147 = v171 - 1;\n v140 += v228 * v150;\n goto LABEL_191;\n }\n while (1) {\n v140 += v149;\n ++v148;\n if (!v147) break;\n v147 = 0;\n LABEL_191:\n if (v148 == 1) {\n v149 = 1;\n goto LABEL_189;\n }\n v256 = v139;\n v229 = v138;\n v201 = v147;\n v172 = v148;\n v151 = sub_11F0(v148);\n v147 = v201;\n v148 = v172;\n v138 = v229;\n v149 = v151;\n v139 = v256;\n if (v201 > 1) goto LABEL_190;\n }\n }\n }\n }\n }\n }\n continue;\n }\n break;\n }\n v173 += v78;\n if (v79) {\n ++v77;\n v79 = 0;\n goto LABEL_152;\n }\n v1 = v184;\n } while (v184 > 1);\nLABEL_202:\n v186 += v173;\n if (v1) {\n ++v185;\n v1 = 0;\n if (v185 != 1) goto LABEL_103;\n goto LABEL_204;\n }\n return v186;\n}", + "ida_pseudo_norm": "long long func0_part_0(int a1) {\n int v1;\n int v2;\n int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n int v8;\n int v9;\n int v10;\n int v11;\n int v12;\n unsigned int v13;\n int v14;\n int v15;\n int v16;\n long long v17;\n int v18;\n int v19;\n int v20;\n unsigned int v21;\n int v22;\n long long v23;\n int v24;\n int v25;\n int v26;\n int v27;\n int v28;\n int v29;\n int v30;\n unsigned int v31;\n int v32;\n int v33;\n long long v34;\n int v35;\n int v36;\n int v37;\n unsigned int v38;\n int v39;\n long long v40;\n int v41;\n int v42;\n int v43;\n int v44;\n int i;\n int v46;\n int v47;\n int v48;\n int v49;\n int v50;\n int v51;\n int v52;\n unsigned int v53;\n int v54;\n int v55;\n int v56;\n int v57;\n int v58;\n unsigned int v59;\n int v60;\n int v61;\n int v62;\n int v63;\n int v64;\n int v65;\n int v66;\n unsigned int v67;\n int v68;\n int v69;\n int v70;\n int v71;\n int v72;\n unsigned int v73;\n int v74;\n int v75;\n int v76;\n int v77;\n int v78;\n int v79;\n int v80;\n int v81;\n int v82;\n int v83;\n int v84;\n int v85;\n int v86;\n int v87;\n int v88;\n unsigned int v89;\n int v90;\n int v91;\n long long v92;\n int v93;\n int v94;\n int v95;\n unsigned int v96;\n int v97;\n long long v98;\n int v99;\n int v100;\n int v101;\n int v102;\n int v103;\n int v104;\n int v105;\n unsigned int v106;\n int v107;\n int v108;\n long long v109;\n int v110;\n int v111;\n int v112;\n unsigned int v113;\n int v114;\n long long v115;\n int v116;\n int v117;\n int v118;\n int v119;\n int j;\n int v121;\n int v122;\n int v123;\n int v124;\n int v125;\n int v126;\n unsigned int v127;\n int v128;\n int v129;\n int v130;\n int v131;\n int v132;\n int v133;\n unsigned int v134;\n int v135;\n int v136;\n int v137;\n int v138;\n int v139;\n int v140;\n int v141;\n unsigned int v142;\n int v143;\n int v144;\n int v145;\n int v146;\n int v147;\n unsigned int v148;\n int v149;\n int v150;\n int v151;\n int v153;\n int v154;\n unsigned int v155;\n int v156;\n unsigned int v157;\n int v158;\n int v159;\n unsigned int v160;\n int v161;\n unsigned int v162;\n int v163;\n int v164;\n unsigned int v165;\n unsigned int v166;\n unsigned int v167;\n int v168;\n int v169;\n unsigned int v170;\n int v171;\n unsigned int v172;\n int v173;\n int v174;\n int v175;\n int v176;\n int v177;\n int v178;\n int v179;\n int v180;\n int v181;\n int v182;\n int v183;\n int v184;\n int v185;\n unsigned int v186;\n int v187;\n int v188;\n unsigned int v189;\n unsigned int v190;\n unsigned int v191;\n unsigned int v192;\n int v193;\n int v194;\n int v195;\n int v196;\n int v197;\n int v198;\n int v199;\n unsigned int v200;\n int v201;\n int v202;\n unsigned int v203;\n int v204;\n unsigned int v205;\n unsigned int v206;\n int v207;\n unsigned int v208;\n int v209;\n int v210;\n int v211;\n int v212;\n int v213;\n unsigned int v214;\n unsigned int v215;\n int v216;\n int v217;\n int v218;\n int v219;\n int v220;\n int v221;\n int v222;\n int v223;\n int v224;\n int v225;\n unsigned int v226;\n int v227;\n int v228;\n int v229;\n int v230;\n int v231;\n unsigned int v232;\n int v233;\n int v234;\n int v235;\n int v236;\n int v237;\n int v238;\n unsigned int v239;\n int v240;\n int v241;\n int v242;\n int v243;\n int v244;\n int v245;\n int v246;\n int v247;\n int v248;\n int v249;\n int v250;\n int v251;\n int v252;\n int v253;\n int v254;\n int v255;\n int v256;\n unsigned int v257;\n int v258;\n int v259;\n int v260;\n int v261;\n int v262;\n int v263;\n int v264;\n int v265;\n int v266;\n int v267;\n int v268;\n int v269;\n int v270;\n int v271;\n int v272;\n int v273;\n int v274;\n int v275;\n int v276;\n int v277;\n int v278;\n int v279;\n int v280;\n int v281;\n int v282;\n int v283;\n int v284;\n int v285;\n int v286;\n int v287;\n int v288;\n int v289;\n int v290;\n int v291;\n int v292;\n int v293;\n int v294;\n int v295;\n int v296;\n int v297;\n int v298;\n int v299;\n int v300;\n int v301;\n int v302;\n int v303;\n int v304;\n int v305;\n int v306;\n int v307;\n int v308;\n int v309;\n int v310;\n int v311;\n int v312;\n int v313;\n int v314;\n int v315;\n int v316;\n int v317;\n int v318;\n int v319;\n int v320;\n int v321;\n int v322;\n int v323;\n int v324;\n v186 = 0;\n if (a1 <= 0) return v186;\n v185 = 0;\n v173 = 1;\n v1 = a1 - 1;\nLABEL_3:\n if (v1 <= 1) goto LABEL_202;\n do {\n v174 = 0;\n v187 = v1 - 1;\n v2 = 0;\n v3 = 1;\n v4 = v1 - 1;\n while (1) {\n if (v4 > 1) {\n v179 = v3;\n --v4;\n v5 = 0;\n v6 = v4;\n v7 = 1;\n v8 = 0;\n while (1) {\n LABEL_7:\n if (v6 > 1) {\n --v6;\n v153 = v5;\n v9 = 0;\n v10 = v6;\n v11 = 1;\n v12 = 0;\n while (1) {\n if (v10 <= 1) {\n v9 += v11;\n if (!v10) {\n v5 = v153 + 1;\n v8 += v7 * v9;\n goto LABEL_29;\n }\n ++v12;\n v10 = 0;\n } else {\n --v10;\n v13 = 0;\n v14 = 0;\n v15 = 1;\n v16 = v10;\n LABEL_11:\n if (v16 > 1) {\n LABEL_12:\n v17 = (unsigned int)v16;\n v324 = v10;\n --v16;\n v306 = v9;\n v282 = v8;\n v257 = v13;\n v230 = v14;\n v202 = v15;\n v18 = func0_part_0(v17);\n v8 = v282;\n v9 = v306;\n v10 = v324;\n v13 = v257 + 1;\n v14 = v202 * v18 + v230;\n goto LABEL_13;\n }\n while (1) {\n v14 += v15;\n ++v13;\n if (!v16) break;\n v16 = 0;\n LABEL_13:\n if (v13 == 1) {\n v15 = 1;\n goto LABEL_11;\n }\n v320 = v10;\n v283 = v9;\n v258 = v8;\n v231 = v14;\n v203 = v13;\n v19 = func0_part_0(v13);\n v13 = v203;\n v14 = v231;\n v8 = v258;\n v9 = v283;\n v15 = v19;\n v10 = v320;\n if (v16 > 1) goto LABEL_12;\n }\n ++v12;\n v9 += v11 * v14;\n }\n if (v12 == 1) {\n v11 = 1;\n } else {\n v20 = v12 - 1;\n v11 = 0;\n v21 = 0;\n v22 = 1;\n LABEL_20:\n if (v20 > 1) {\n LABEL_21:\n v23 = (unsigned int)v20--;\n v307 = v10;\n v284 = v9;\n v259 = v8;\n v232 = v21;\n v204 = v22;\n v24 = func0_part_0(v23);\n v8 = v259;\n v9 = v284;\n v10 = v307;\n v21 = v232 + 1;\n v11 += v204 * v24;\n goto LABEL_22;\n }\n while (1) {\n v11 += v22;\n ++v21;\n if (!v20) break;\n v20 = 0;\n LABEL_22:\n if (v21 == 1) {\n v22 = 1;\n goto LABEL_20;\n }\n v285 = v10;\n v260 = v9;\n v233 = v8;\n v205 = v21;\n v25 = func0_part_0(v21);\n v21 = v205;\n v8 = v233;\n v9 = v260;\n v10 = v285;\n v22 = v25;\n if (v20 > 1) goto LABEL_21;\n }\n }\n }\n }\n v8 += v7;\n if (!v6) break;\n ++v5;\n v6 = 0;\n LABEL_29:\n if (v5 != 1) {\n v26 = v5 - 1;\n v7 = 0;\n v27 = 0;\n v28 = 1;\n while (1) {\n if (v26 <= 1) {\n v7 += v28;\n if (!v26) goto LABEL_7;\n ++v27;\n v26 = 0;\n } else {\n v29 = v26 - 1;\n v30 = 0;\n v31 = 0;\n v32 = 1;\n v33 = v29;\n LABEL_33:\n if (v33 > 1) {\n LABEL_34:\n v34 = (unsigned int)v33;\n v321 = v29;\n --v33;\n v308 = v27;\n v286 = v8;\n v234 = v32;\n v206 = v31;\n v154 = v30;\n v35 = func0_part_0(v34);\n v8 = v286;\n v27 = v308;\n v29 = v321;\n v31 = v206 + 1;\n v30 = v234 * v35 + v154;\n goto LABEL_35;\n }\n while (1) {\n v30 += v32;\n ++v31;\n if (!v33) break;\n v33 = 0;\n LABEL_35:\n if (v31 == 1) {\n v32 = 1;\n goto LABEL_33;\n }\n v309 = v29;\n v287 = v27;\n v261 = v8;\n v207 = v30;\n v155 = v31;\n v36 = func0_part_0(v31);\n v31 = v155;\n v30 = v207;\n v8 = v261;\n v32 = v36;\n v27 = v287;\n v29 = v309;\n if (v33 > 1) goto LABEL_34;\n }\n ++v27;\n v26 = v29;\n v7 += v28 * v30;\n }\n if (v27 == 1) {\n v28 = 1;\n } else {\n v37 = v27 - 1;\n v38 = 0;\n v28 = 0;\n v39 = 1;\n LABEL_42:\n if (v37 > 1) {\n LABEL_43:\n v40 = (unsigned int)v37;\n v310 = v26;\n --v37;\n v288 = v27;\n v262 = v8;\n v208 = v38;\n v156 = v39;\n v41 = func0_part_0(v40);\n v8 = v262;\n v27 = v288;\n v26 = v310;\n v38 = v208 + 1;\n v28 += v156 * v41;\n goto LABEL_44;\n }\n while (1) {\n v28 += v39;\n ++v38;\n if (!v37) break;\n v37 = 0;\n LABEL_44:\n if (v38 == 1) {\n v39 = 1;\n goto LABEL_42;\n }\n v289 = v26;\n v263 = v27;\n v235 = v8;\n v157 = v38;\n v42 = func0_part_0(v38);\n v38 = v157;\n v8 = v235;\n v27 = v263;\n v39 = v42;\n v26 = v289;\n if (v37 > 1) goto LABEL_43;\n }\n }\n }\n }\n v7 = 1;\n }\n ++v2;\n v174 += v8 * v179;\n goto LABEL_53;\n }\n v174 += v3;\n if (!v4) break;\n ++v2;\n v4 = 0;\n LABEL_53:\n if (v2 == 1) {\n v3 = 1;\n } else {\n v43 = v2 - 1;\n v3 = 0;\n v44 = 0;\n for (i = 1;; i = 1) {\n LABEL_55:\n if (v43 > 1) {\n v46 = v43 - 1;\n v47 = 0;\n v48 = 0;\n v49 = 1;\n v158 = v46;\n v50 = v46;\n while (1) {\n if (v50 <= 1) {\n v47 += v49;\n if (!v50) {\n ++v44;\n v43 = v158;\n v3 += i * v47;\n goto LABEL_77;\n }\n ++v48;\n v50 = 0;\n } else {\n v51 = v50 - 1;\n v52 = 0;\n v53 = 0;\n v54 = 1;\n v55 = v51;\n LABEL_59:\n if (v55 > 1) {\n LABEL_60:\n v322 = v51;\n v311 = v47;\n v290 = v48;\n v236 = v52;\n v209 = v54;\n v180 = v55;\n v56 = func0_part_0((unsigned int)v55);\n v48 = v290;\n v47 = v311;\n v51 = v322;\n ++v53;\n v55 = v180 - 1;\n v52 = v209 * v56 + v236;\n goto LABEL_61;\n }\n while (1) {\n v52 += v54;\n ++v53;\n if (!v55) break;\n v55 = 0;\n LABEL_61:\n if (v53 == 1) {\n v54 = 1;\n goto LABEL_59;\n }\n v312 = v51;\n v291 = v47;\n v264 = v48;\n v237 = v55;\n v210 = v52;\n v57 = func0_part_0(v53);\n v55 = v237;\n v52 = v210;\n v48 = v264;\n v54 = v57;\n v47 = v291;\n v51 = v312;\n if (v237 > 1) goto LABEL_60;\n }\n ++v48;\n v50 = v51;\n v47 += v49 * v52;\n }\n if (v48 == 1) {\n v49 = 1;\n } else {\n v58 = v48 - 1;\n v49 = 0;\n v59 = 0;\n v60 = 1;\n LABEL_68:\n if (v58 > 1) {\n LABEL_69:\n v313 = v50;\n v292 = v47;\n v265 = v48;\n v211 = v60;\n v181 = v58;\n v61 = func0_part_0((unsigned int)v58);\n v48 = v265;\n v47 = v292;\n v50 = v313;\n ++v59;\n v58 = v181 - 1;\n v49 += v211 * v61;\n goto LABEL_70;\n }\n while (1) {\n v49 += v60;\n ++v59;\n if (!v58) break;\n v58 = 0;\n LABEL_70:\n if (v59 == 1) {\n v60 = 1;\n goto LABEL_68;\n }\n v293 = v50;\n v266 = v47;\n v238 = v48;\n v212 = v58;\n v62 = func0_part_0(v59);\n v58 = v212;\n v48 = v238;\n v47 = v266;\n v60 = v62;\n v50 = v293;\n if (v212 > 1) goto LABEL_69;\n }\n }\n }\n }\n v3 += i;\n if (!v43) break;\n ++v44;\n v43 = 0;\n LABEL_77:\n if (v44 != 1) {\n v63 = v44 - 1;\n i = 0;\n v64 = 0;\n v65 = 1;\n while (1) {\n if (v63 <= 1) {\n i += v65;\n if (!v63) goto LABEL_55;\n ++v64;\n v63 = 0;\n } else {\n --v63;\n v66 = 0;\n v67 = 0;\n v68 = 1;\n v69 = v63;\n LABEL_81:\n if (v69 > 1) {\n LABEL_82:\n v314 = v63;\n v294 = v64;\n v267 = v68;\n v239 = v67;\n v213 = v66;\n v159 = v69;\n v70 = func0_part_0((unsigned int)v69);\n v64 = v294;\n v63 = v314;\n v67 = v239 + 1;\n v69 = v159 - 1;\n v66 = v267 * v70 + v213;\n goto LABEL_83;\n }\n while (1) {\n v66 += v68;\n ++v67;\n if (!v69) break;\n v69 = 0;\n LABEL_83:\n if (v67 == 1) {\n v68 = 1;\n goto LABEL_81;\n }\n v295 = v63;\n v268 = v64;\n v240 = v66;\n v182 = v69;\n v160 = v67;\n v71 = func0_part_0(v67);\n v69 = v182;\n v67 = v160;\n v66 = v240;\n v68 = v71;\n v64 = v268;\n v63 = v295;\n if (v182 > 1) goto LABEL_82;\n }\n ++v64;\n i += v65 * v66;\n }\n if (v64 == 1) {\n v65 = 1;\n } else {\n v72 = v64 - 1;\n v65 = 0;\n v73 = 0;\n v74 = 1;\n LABEL_90:\n if (v72 > 1) {\n LABEL_91:\n v296 = v63;\n v269 = v64;\n v241 = v74;\n v214 = v73;\n v161 = v72;\n v75 = func0_part_0((unsigned int)v72);\n v64 = v269;\n v63 = v296;\n v73 = v214 + 1;\n v72 = v161 - 1;\n v65 += v241 * v75;\n goto LABEL_92;\n }\n while (1) {\n v65 += v74;\n ++v73;\n if (!v72) break;\n v72 = 0;\n LABEL_92:\n if (v73 == 1) {\n v74 = 1;\n goto LABEL_90;\n }\n v270 = v63;\n v242 = v64;\n v183 = v72;\n v162 = v73;\n v76 = func0_part_0(v73);\n v72 = v183;\n v73 = v162;\n v64 = v242;\n v74 = v76;\n v63 = v270;\n if (v183 > 1) goto LABEL_91;\n }\n }\n }\n }\n }\n }\n }\n ++v185;\n v186 += v174 * v173;\n v1 = v187;\n if (v185 == 1) {\n LABEL_204:\n v173 = 1;\n goto LABEL_3;\n }\n LABEL_103:\n v173 = 0;\n v184 = v1;\n v77 = 0;\n v78 = 1;\n v79 = v185 - 1;\n while (2) {\n if (v79 > 1) {\n v175 = v78;\n --v79;\n v80 = 0;\n v81 = v79;\n v82 = 1;\n v83 = 0;\n while (1) {\n LABEL_106:\n if (v81 > 1) {\n --v81;\n v163 = v80;\n v84 = 0;\n v85 = v81;\n v86 = 1;\n v87 = 0;\n while (1) {\n if (v85 <= 1) {\n v84 += v86;\n if (!v85) {\n v80 = v163 + 1;\n v83 += v82 * v84;\n goto LABEL_128;\n }\n ++v87;\n v85 = 0;\n } else {\n --v85;\n v88 = 0;\n v89 = 0;\n v90 = 1;\n v91 = v85;\n LABEL_110:\n if (v91 > 1) {\n LABEL_111:\n v92 = (unsigned int)v91;\n v323 = v85;\n --v91;\n v315 = v84;\n v271 = v83;\n v243 = v90;\n v215 = v89;\n v188 = v88;\n v93 = func0_part_0(v92);\n v83 = v271;\n v84 = v315;\n v85 = v323;\n v89 = v215 + 1;\n v88 = v243 * v93 + v188;\n goto LABEL_112;\n }\n while (1) {\n v88 += v90;\n ++v89;\n if (!v91) break;\n v91 = 0;\n LABEL_112:\n if (v89 == 1) {\n v90 = 1;\n goto LABEL_110;\n }\n v316 = v85;\n v297 = v84;\n v244 = v83;\n v216 = v88;\n v189 = v89;\n v94 = func0_part_0(v89);\n v89 = v189;\n v88 = v216;\n v83 = v244;\n v90 = v94;\n v84 = v297;\n v85 = v316;\n if (v91 > 1) goto LABEL_111;\n }\n ++v87;\n v84 += v86 * v88;\n }\n if (v87 == 1) {\n v86 = 1;\n } else {\n v95 = v87 - 1;\n v86 = 0;\n v96 = 0;\n v97 = 1;\n LABEL_119:\n if (v95 > 1) {\n LABEL_120:\n v98 = (unsigned int)v95;\n v317 = v84;\n --v95;\n v272 = v85;\n v245 = v83;\n v217 = v97;\n v190 = v96;\n v99 = func0_part_0(v98);\n v83 = v245;\n v85 = v272;\n v84 = v317;\n v96 = v190 + 1;\n v86 += v217 * v99;\n goto LABEL_121;\n }\n while (1) {\n v86 += v97;\n ++v96;\n if (!v95) break;\n v95 = 0;\n LABEL_121:\n if (v96 == 1) {\n v97 = 1;\n goto LABEL_119;\n }\n v298 = v84;\n v246 = v85;\n v218 = v83;\n v191 = v96;\n v100 = func0_part_0(v96);\n v96 = v191;\n v83 = v218;\n v85 = v246;\n v97 = v100;\n v84 = v298;\n if (v95 > 1) goto LABEL_120;\n }\n }\n }\n }\n v83 += v82;\n if (!v81) break;\n ++v80;\n v81 = 0;\n LABEL_128:\n if (v80 != 1) {\n v101 = v80 - 1;\n v102 = 0;\n v82 = 0;\n v103 = 1;\n while (1) {\n if (v101 <= 1) {\n v82 += v103;\n if (!v101) goto LABEL_106;\n ++v102;\n v101 = 0;\n } else {\n v104 = v101 - 1;\n v105 = 0;\n v106 = 0;\n v107 = 1;\n v108 = v104;\n LABEL_132:\n if (v108 > 1) {\n LABEL_133:\n v109 = (unsigned int)v108;\n v318 = v104;\n --v108;\n v299 = v102;\n v247 = v83;\n v219 = v107;\n v192 = v106;\n v164 = v105;\n v110 = func0_part_0(v109);\n v83 = v247;\n v102 = v299;\n v104 = v318;\n v106 = v192 + 1;\n v105 = v219 * v110 + v164;\n goto LABEL_134;\n }\n while (1) {\n v105 += v107;\n ++v106;\n if (!v108) break;\n v108 = 0;\n LABEL_134:\n if (v106 == 1) {\n v107 = 1;\n goto LABEL_132;\n }\n v300 = v104;\n v273 = v102;\n v220 = v83;\n v193 = v105;\n v165 = v106;\n v111 = func0_part_0(v106);\n v106 = v165;\n v105 = v193;\n v83 = v220;\n v107 = v111;\n v102 = v273;\n v104 = v300;\n if (v108 > 1) goto LABEL_133;\n }\n ++v102;\n v101 = v104;\n v82 += v103 * v105;\n }\n if (v102 == 1) {\n v103 = 1;\n } else {\n v112 = v102 - 1;\n v113 = 0;\n v103 = 0;\n v114 = 1;\n LABEL_141:\n if (v112 > 1) {\n LABEL_142:\n v115 = (unsigned int)v112;\n v301 = v102;\n --v112;\n v248 = v83;\n v221 = v101;\n v194 = v114;\n v166 = v113;\n v116 = func0_part_0(v115);\n v101 = v221;\n v83 = v248;\n v102 = v301;\n v113 = v166 + 1;\n v103 += v194 * v116;\n goto LABEL_143;\n }\n while (1) {\n v103 += v114;\n ++v113;\n if (!v112) break;\n v112 = 0;\n LABEL_143:\n if (v113 == 1) {\n v114 = 1;\n goto LABEL_141;\n }\n v274 = v102;\n v222 = v83;\n v195 = v101;\n v167 = v113;\n v117 = func0_part_0(v113);\n v113 = v167;\n v101 = v195;\n v83 = v222;\n v114 = v117;\n v102 = v274;\n if (v112 > 1) goto LABEL_142;\n }\n }\n }\n }\n v82 = 1;\n }\n ++v77;\n v173 += v83 * v175;\n LABEL_152:\n if (v77 == 1) {\n v78 = 1;\n } else {\n v118 = v77 - 1;\n v78 = 0;\n v119 = 0;\n for (j = 1;; j = 1) {\n LABEL_154:\n if (v118 > 1) {\n v121 = v118 - 1;\n v122 = 0;\n v123 = 0;\n v124 = 1;\n v168 = v121;\n v125 = v121;\n while (1) {\n if (v125 <= 1) {\n v123 += v124;\n if (!v125) {\n ++v119;\n v118 = v168;\n v78 += j * v123;\n goto LABEL_176;\n }\n ++v122;\n v125 = 0;\n } else {\n v126 = v125 - 1;\n v127 = 0;\n v128 = 0;\n v129 = 1;\n v130 = v126;\n LABEL_158:\n if (v130 > 1) {\n LABEL_159:\n v319 = v126;\n v302 = v122;\n v275 = v123;\n v249 = v129;\n v196 = v128;\n v176 = v130;\n v131 = func0_part_0((unsigned int)v130);\n v123 = v275;\n v122 = v302;\n v126 = v319;\n ++v127;\n v130 = v176 - 1;\n v128 = v249 * v131 + v196;\n goto LABEL_160;\n }\n while (1) {\n v128 += v129;\n ++v127;\n if (!v130) break;\n v130 = 0;\n LABEL_160:\n if (v127 == 1) {\n v129 = 1;\n goto LABEL_158;\n }\n v303 = v126;\n v276 = v122;\n v250 = v123;\n v223 = v128;\n v197 = v130;\n v132 = func0_part_0(v127);\n v130 = v197;\n v128 = v223;\n v123 = v250;\n v129 = v132;\n v122 = v276;\n v126 = v303;\n if (v197 > 1) goto LABEL_159;\n }\n ++v122;\n v125 = v126;\n v123 += v124 * v128;\n }\n if (v122 == 1) {\n v124 = 1;\n } else {\n v133 = v122 - 1;\n v124 = 0;\n v134 = 0;\n v135 = 1;\n LABEL_167:\n if (v133 > 1) {\n LABEL_168:\n v304 = v122;\n v277 = v123;\n v251 = v125;\n v224 = v135;\n v177 = v133;\n v136 = func0_part_0((unsigned int)v133);\n v125 = v251;\n v123 = v277;\n v122 = v304;\n ++v134;\n v133 = v177 - 1;\n v124 += v224 * v136;\n goto LABEL_169;\n }\n while (1) {\n v124 += v135;\n ++v134;\n if (!v133) break;\n v133 = 0;\n LABEL_169:\n if (v134 == 1) {\n v135 = 1;\n goto LABEL_167;\n }\n v278 = v122;\n v252 = v123;\n v225 = v125;\n v198 = v133;\n v137 = func0_part_0(v134);\n v133 = v198;\n v125 = v225;\n v123 = v252;\n v135 = v137;\n v122 = v278;\n if (v198 > 1) goto LABEL_168;\n }\n }\n }\n }\n v78 += j;\n if (!v118) break;\n ++v119;\n v118 = 0;\n LABEL_176:\n if (v119 != 1) {\n v138 = v119 - 1;\n j = 0;\n v139 = 0;\n v140 = 1;\n while (1) {\n if (v138 <= 1) {\n j += v140;\n if (!v138) goto LABEL_154;\n ++v139;\n v138 = 0;\n } else {\n --v138;\n v141 = 0;\n v142 = 0;\n v143 = 1;\n v144 = v138;\n LABEL_180:\n if (v144 > 1) {\n LABEL_181:\n v305 = v138;\n v279 = v139;\n v253 = v143;\n v226 = v142;\n v199 = v141;\n v169 = v144;\n v145 = func0_part_0((unsigned int)v144);\n v139 = v279;\n v138 = v305;\n v142 = v226 + 1;\n v144 = v169 - 1;\n v141 = v253 * v145 + v199;\n goto LABEL_182;\n }\n while (1) {\n v141 += v143;\n ++v142;\n if (!v144) break;\n v144 = 0;\n LABEL_182:\n if (v142 == 1) {\n v143 = 1;\n goto LABEL_180;\n }\n v280 = v138;\n v254 = v139;\n v227 = v141;\n v178 = v144;\n v170 = v142;\n v146 = func0_part_0(v142);\n v144 = v178;\n v142 = v170;\n v141 = v227;\n v143 = v146;\n v139 = v254;\n v138 = v280;\n if (v178 > 1) goto LABEL_181;\n }\n ++v139;\n j += v140 * v141;\n }\n if (v139 == 1) {\n v140 = 1;\n } else {\n v147 = v139 - 1;\n v148 = 0;\n v140 = 0;\n v149 = 1;\n LABEL_189:\n if (v147 > 1) {\n LABEL_190:\n v281 = v139;\n v255 = v138;\n v228 = v149;\n v200 = v148;\n v171 = v147;\n v150 = func0_part_0((unsigned int)v147);\n v138 = v255;\n v139 = v281;\n v148 = v200 + 1;\n v147 = v171 - 1;\n v140 += v228 * v150;\n goto LABEL_191;\n }\n while (1) {\n v140 += v149;\n ++v148;\n if (!v147) break;\n v147 = 0;\n LABEL_191:\n if (v148 == 1) {\n v149 = 1;\n goto LABEL_189;\n }\n v256 = v139;\n v229 = v138;\n v201 = v147;\n v172 = v148;\n v151 = func0_part_0(v148);\n v147 = v201;\n v148 = v172;\n v138 = v229;\n v149 = v151;\n v139 = v256;\n if (v201 > 1) goto LABEL_190;\n }\n }\n }\n }\n }\n }\n continue;\n }\n break;\n }\n v173 += v78;\n if (v79) {\n ++v77;\n v79 = 0;\n goto LABEL_152;\n }\n v1 = v184;\n } while (v184 > 1);\nLABEL_202:\n v186 += v173;\n if (v1) {\n ++v185;\n v1 = 0;\n if (v185 != 1) goto LABEL_103;\n goto LABEL_204;\n }\n return v186;\n}" + }, + { + "index": 583, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int num) {\n if (num <= 1) return 1;\n int res_num = 0;\n for (int i = 0; i < num; i++) res_num += func0(i) * func0(num - i - 1);\n return res_num;\n}", + "test": "int main() {\n\n assert(func0(10) == 16796);\n\n assert(func0(9) == 4862);\n\n assert(func0(7) == 429);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%edi\njle 12c0 \nlea -0x1(%rdi),%edx\nsub $0x8,%rsp\nmov %edi,%esi\nxor %r8d,%r8d\nmov $0x1,%ecx\ncmp $0x1,%edx\njbe 12a4 \nmov %edx,%edi\ncallq 11f0 \nimul %eax,%ecx\nmov %esi,%edi\nsub %edx,%edi\nadd %ecx,%r8d\ncmp $0x1,%edi\njle 12ca \ncallq 11f0 \nmov %eax,%ecx\nsub $0x1,%edx\ncmp $0x1,%edx\nja 127f \nmov %esi,%edi\nadd %ecx,%r8d\nsub %edx,%edi\ntest %edx,%edx\njne 1290 \nmov %r8d,%eax\nadd $0x8,%rsp\nretq\nnopw 0x0(%rax,%rax,1)\nmov $0x1,%r8d\nmov %r8d,%eax\nretq\nmov $0x1,%ecx\njmp 129c \nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0_part_0:\npush r15\npush r14\npush r13\npush r12\npush rbp\nxor ebp, ebp\npush rbx\nsub rsp, 48h\ntest edi, edi\njle loc_2571\nxor r12d, r12d\nmov [rsp+78h+var_58], 1\nlea ebx, [rdi-1]\nmov [rsp+78h+var_4C], r12d\nmov [rsp+78h+var_48], ebp\nloc_121F:\ncmp ebx, 1\njle loc_2542\nloc_1228:\nsub ebx, 1\nmov [rsp+78h+var_5C], 0\nmov [rsp+78h+var_54], 0\nmov r12d, ebx\nmov [rsp+78h+var_68], 1\nmov [rsp+78h+var_44], ebx\nloc_124A:\ncmp r12d, 1\njle loc_1B27\nloc_1254:\nsub r12d, 1\nxor r14d, r14d\nmov [rsp+78h+var_6C], 0\nmov [rsp+78h+var_74], 1\nmov ebp, r12d\nmov [rsp+78h+var_64], r14d\nmov [rsp+78h+var_50], r12d\nloc_1278:\ncmp ebp, 1\njle loc_162D\nloc_1281:\nlea eax, [rbp-1]\nsub ebp, 2\nxor r12d, r12d\nmov ebx, 1\nmov [rsp+78h+var_60], eax\nmov r14d, eax\nmov r15d, ebp\nmov [rsp+78h+var_70], 0\nloc_12A1:\ncmp r14d, 1\njle loc_1420\nmov edi, r15d\ncmp r15d, 1\njle loc_1350\nmov edx, r15d\nxor ecx, ecx\nlea ebp, [r15-1]\nxor r13d, r13d\nloc_12C4:\nmov [rsp+78h+var_3C], ecx\nmov [rsp+78h+var_40], edx\ncall func0_part_0\nmov ecx, [rsp+78h+var_3C]\nmov edi, 1\nmov edx, [rsp+78h+var_40]\nadd r13d, eax\ntest r15d, r15d\ncmovle edi, r15d\nlea eax, [rcx+1]\ncmp edi, eax\njge loc_2683\nnop dword ptr [rax+rax+00h]\nloc_12F8:\ncmp r14d, eax\njle short loc_136D\nnop dword ptr [rax]\nloc_1300:\nmov edx, r14d\nsub r14d, 1\nsub edx, eax\nlea r15d, [rdx-1]\nloc_130D:\nmov edi, r14d\nsub edi, r15d\ncall func0_part_0\ncmp r15d, 1\njle short loc_1340\nmov edi, r15d\nmov [rsp+78h+var_40], eax\nsub r15d, 1\ncall func0_part_0\nmov edx, [rsp+78h+var_40]\nimul edx, eax\nadd r13d, edx\njmp short loc_130D\nloc_1340:\nadd r13d, eax\ntest r15d, r15d\njz short loc_1371\nxor r15d, r15d\njmp short loc_130D\nloc_1350:\ntest r15d, r15d\njg loc_1678\nmov eax, 1\nmov r13d, 1\nlea ebp, [r15-1]\ncmp r14d, eax\njg short loc_1300\nloc_136D:\nsub r14d, 1\nloc_1371:\nmov esi, r13d\nadd r12d, 1\nmov r15d, ebp\nimul esi, ebx\nadd [rsp+78h+var_70], esi\nloc_1382:\ncmp r12d, 1\njz loc_26DD\nlea r13d, [r12-1]\nmov edi, r13d\ncmp r13d, 1\njz loc_1B58\nmov ebp, r13d\nxor ebx, ebx\nxor edx, edx\nloc_13A5:\nmov [rsp+78h+var_40], edx\ncall func0_part_0\nmov edx, [rsp+78h+var_40]\nadd ebx, eax\ntest edx, edx\njz loc_266B\nnop dword ptr [rax+00h]\nloc_13C0:\nlea ebp, [r12-3]\ncmp r12d, 2\njz loc_12A1\nloc_13CF:\nmov edi, r13d\nsub edi, ebp\ncall func0_part_0\ncmp ebp, 1\njle short loc_1408\nloc_13DE:\nmov edi, ebp\nmov [rsp+78h+var_40], eax\nsub ebp, 1\ncall func0_part_0\nmov edx, [rsp+78h+var_40]\nmov edi, r13d\nsub edi, ebp\nimul edx, eax\nadd ebx, edx\ncall func0_part_0\ncmp ebp, 1\njg short loc_13DE\nnop dword ptr [rax+00h]\nloc_1408:\nadd ebx, eax\ntest ebp, ebp\njz loc_12A1\nxor ebp, ebp\njmp short loc_13CF\nloc_1420:\nadd [rsp+78h+var_70], ebx\ntest r14d, r14d\njz short loc_1440\nadd r12d, 1\nsub r15d, 1\nxor r14d, r14d\njmp loc_1382\nloc_1440:\nmov r13d, [rsp+78h+var_74]\nmov eax, [rsp+78h+var_70]\nadd [rsp+78h+var_6C], 1\nmov ebp, [rsp+78h+var_60]\nimul r13d, eax\nadd [rsp+78h+var_64], r13d\nloc_145B:\ncmp [rsp+78h+var_6C], 1\njz loc_26A2\nmov eax, [rsp+78h+var_6C]\nmov [rsp+78h+var_70], ebp\nxor r13d, r13d\nmov ebx, 1\nmov [rsp+78h+var_74], 0\nlea r12d, [rax-2]\nlea r14d, [rax-1]\nmov ebp, r12d\nloc_1489:\ncmp r14d, 1\njle loc_1600\nmov edi, ebp\ncmp ebp, 1\njle loc_1540\nmov r8d, ebp\nxor r15d, r15d\nlea r12d, [rbp-1]\nxor edx, edx\nloc_14AA:\nmov [rsp+78h+var_40], edx\nmov [rsp+78h+var_60], r8d\ncall func0_part_0\nmov edx, [rsp+78h+var_40]\nmov r8d, [rsp+78h+var_60]\nadd r15d, eax\ntest ebp, ebp\nlea eax, [rdx+1]\nmov edx, 1\ncmovle edx, ebp\ncmp edx, eax\njge loc_2662\nnop dword ptr [rax+00000000h]\nloc_14E0:\ncmp r14d, eax\njle short loc_155C\nnop dword ptr [rax]\nloc_14E8:\nmov edx, r14d\nsub r14d, 1\nsub edx, eax\nlea ebp, [rdx-1]\nloc_14F4:\nmov edi, r14d\nsub edi, ebp\ncall func0_part_0\ncmp ebp, 1\njle short loc_1530\nloc_1503:\nmov edi, ebp\nmov [rsp+78h+var_60], eax\nsub ebp, 1\ncall func0_part_0\nmov edx, [rsp+78h+var_60]\nmov edi, r14d\nsub edi, ebp\nimul edx, eax\nadd r15d, edx\ncall func0_part_0\ncmp ebp, 1\njg short loc_1503\nnop word ptr [rax+rax+00h]\nloc_1530:\nadd r15d, eax\ntest ebp, ebp\njz short loc_1560\nxor ebp, ebp\njmp short loc_14F4\nloc_1540:\ntest ebp, ebp\njg loc_1648\nmov eax, 1\nmov r15d, 1\nlea r12d, [rbp-1]\ncmp r14d, eax\njg short loc_14E8\nloc_155C:\nsub r14d, 1\nloc_1560:\nmov esi, ebx\nadd r13d, 1\nmov ebp, r12d\nimul esi, r15d\nadd [rsp+78h+var_74], esi\nloc_1571:\ncmp r13d, 1\njz loc_268B\nlea r12d, [r13-1]\nmov edi, r12d\ncmp r12d, 1\njz loc_1B78\nmov edx, r12d\nxor r15d, r15d\nxor ebx, ebx\nloc_1594:\nmov [rsp+78h+var_60], edx\ncall func0_part_0\nmov edx, [rsp+78h+var_60]\nadd ebx, eax\ntest r15d, r15d\njz loc_2649\nnop dword ptr [rax+00h]\nloc_15B0:\nlea r15d, [r13-3]\ncmp r13d, 2\njz loc_1489\nloc_15BE:\nmov edi, r12d\nsub edi, r15d\ncall func0_part_0\ncmp r15d, 1\njle short loc_15F0\nmov edi, r15d\nmov [rsp+78h+var_60], eax\nsub r15d, 1\ncall func0_part_0\nmov edx, [rsp+78h+var_60]\nimul eax, edx\nadd ebx, eax\njmp short loc_15BE\nloc_15F0:\nadd ebx, eax\ntest r15d, r15d\njz loc_1489\nxor r15d, r15d\njmp short loc_15BE\nloc_1600:\nadd [rsp+78h+var_74], ebx\ntest r14d, r14d\njz short loc_1620\nadd r13d, 1\nsub ebp, 1\nxor r14d, r14d\njmp loc_1571\nloc_1620:\nmov ebp, [rsp+78h+var_70]\ncmp ebp, 1\njg loc_1281\nloc_162D:\nmov ecx, [rsp+78h+var_74]\nadd [rsp+78h+var_64], ecx\ntest ebp, ebp\njz short loc_16A8\nadd [rsp+78h+var_6C], 1\nxor ebp, ebp\njmp loc_145B\nloc_1648:\nlea r12d, [rbp-1]\nmov r15d, 1\nmov r8d, r12d\nloc_1655:\nmov edi, r8d\nmov edx, 1\ncmp r8d, 1\njg loc_14AA\nadd r15d, 1\nmov eax, 2\njmp loc_14E0\nloc_1678:\nlea ebp, [r15-1]\nmov r13d, 1\nmov edx, ebp\nloc_1684:\nmov edi, edx\nmov ecx, 1\ncmp edx, 1\njg loc_12C4\nadd r13d, 1\nmov eax, 2\njmp loc_12F8\nloc_16A8:\nmov r14d, [rsp+78h+var_64]\nmov eax, [rsp+78h+var_68]\nadd [rsp+78h+var_5C], 1\nmov r12d, [rsp+78h+var_50]\nimul eax, r14d\nadd [rsp+78h+var_54], eax\nloc_16C3:\ncmp [rsp+78h+var_5C], 1\njz loc_26D0\nmov eax, [rsp+78h+var_5C]\nmov [rsp+78h+var_68], 0\nmov [rsp+78h+var_6C], 0\nmov [rsp+78h+var_74], 1\nsub eax, 1\nmov [rsp+78h+var_60], r12d\nmov ebp, eax\nloc_16F4:\ncmp ebp, 1\njle loc_1A9D\nloc_16FD:\nlea eax, [rbp-1]\nsub ebp, 2\nxor r12d, r12d\nmov ebx, 1\nmov [rsp+78h+var_64], eax\nmov r14d, ebp\nmov r15d, eax\nmov [rsp+78h+var_70], 0\nloc_171D:\ncmp r15d, 1\njle loc_1890\nmov edi, r14d\ncmp r14d, 1\njle loc_17C8\nmov edx, r14d\nxor r13d, r13d\nlea ebp, [r14-1]\nxor ecx, ecx\nloc_1740:\nmov [rsp+78h+var_40], ecx\nmov [rsp+78h+var_50], edx\ncall func0_part_0\nmov ecx, [rsp+78h+var_40]\nmov edi, 1\nmov edx, [rsp+78h+var_50]\nadd r13d, eax\ntest r14d, r14d\ncmovle edi, r14d\nlea eax, [rcx+1]\ncmp eax, edi\njle loc_2641\nnop\nloc_1770:\ncmp r15d, eax\njle short loc_17E5\nnop dword ptr [rax]\nloc_1778:\nmov edx, r15d\nsub r15d, 1\nsub edx, eax\nlea r14d, [rdx-1]\nloc_1785:\nmov edi, r15d\nsub edi, r14d\ncall func0_part_0\ncmp r14d, 1\njle short loc_17B8\nmov edi, r14d\nmov [rsp+78h+var_50], eax\nsub r14d, 1\ncall func0_part_0\nmov edx, [rsp+78h+var_50]\nimul edx, eax\nadd r13d, edx\njmp short loc_1785\nloc_17B8:\nadd r13d, eax\ntest r14d, r14d\njz short loc_17E9\nxor r14d, r14d\njmp short loc_1785\nloc_17C8:\ntest r14d, r14d\njg loc_1AB8\nmov eax, 1\nmov r13d, 1\nlea ebp, [r14-1]\ncmp r15d, eax\njg short loc_1778\nloc_17E5:\nsub r15d, 1\nloc_17E9:\nmov esi, ebx\nadd r12d, 1\nmov r14d, ebp\nimul esi, r13d\nadd [rsp+78h+var_70], esi\nloc_17FA:\ncmp r12d, 1\njz loc_26C6\nlea r13d, [r12-1]\nmov edi, r13d\ncmp r13d, 1\njz loc_1B48\nmov ebp, r13d\nxor ebx, ebx\nxor edx, edx\nloc_181D:\nmov [rsp+78h+var_50], edx\ncall func0_part_0\nmov edx, [rsp+78h+var_50]\nadd ebx, eax\ntest edx, edx\njz loc_2629\nnop dword ptr [rax+00h]\nloc_1838:\nlea ebp, [r12-3]\ncmp r12d, 2\njz loc_171D\nloc_1847:\nmov edi, r13d\nsub edi, ebp\ncall func0_part_0\ncmp ebp, 1\njle short loc_1880\nloc_1856:\nmov edi, ebp\nmov [rsp+78h+var_50], eax\nsub ebp, 1\ncall func0_part_0\nmov edx, [rsp+78h+var_50]\nmov edi, r13d\nsub edi, ebp\nimul edx, eax\nadd ebx, edx\ncall func0_part_0\ncmp ebp, 1\njg short loc_1856\nnop dword ptr [rax+00h]\nloc_1880:\nadd ebx, eax\ntest ebp, ebp\njz loc_171D\nxor ebp, ebp\njmp short loc_1847\nloc_1890:\nadd [rsp+78h+var_70], ebx\ntest r15d, r15d\njz short loc_18B0\nadd r12d, 1\nsub r14d, 1\nxor r15d, r15d\njmp loc_17FA\nloc_18B0:\nmov r13d, [rsp+78h+var_74]\nmov eax, [rsp+78h+var_70]\nadd [rsp+78h+var_6C], 1\nmov ebp, [rsp+78h+var_64]\nimul r13d, eax\nadd [rsp+78h+var_68], r13d\nloc_18CB:\ncmp [rsp+78h+var_6C], 1\njz loc_26B9\nmov eax, [rsp+78h+var_6C]\nmov [rsp+78h+var_70], ebp\nxor r13d, r13d\nmov ebx, 1\nmov [rsp+78h+var_74], 0\nlea r12d, [rax-2]\nlea r14d, [rax-1]\nmov ebp, r12d\nloc_18F9:\ncmp r14d, 1\njle loc_1A70\nmov edi, ebp\ncmp ebp, 1\njle loc_19B0\nmov r8d, ebp\nxor r15d, r15d\nlea r12d, [rbp-1]\nxor edx, edx\nloc_191A:\nmov [rsp+78h+var_50], edx\nmov [rsp+78h+var_64], r8d\ncall func0_part_0\nmov edx, [rsp+78h+var_50]\nmov r8d, [rsp+78h+var_64]\nadd r15d, eax\ntest ebp, ebp\nlea eax, [rdx+1]\nmov edx, 1\ncmovle edx, ebp\ncmp edx, eax\njge loc_2620\nnop dword ptr [rax+00000000h]\nloc_1950:\ncmp r14d, eax\njle short loc_19CC\nnop dword ptr [rax]\nloc_1958:\nmov edx, r14d\nsub r14d, 1\nsub edx, eax\nlea ebp, [rdx-1]\nloc_1964:\nmov edi, r14d\nsub edi, ebp\ncall func0_part_0\ncmp ebp, 1\njle short loc_19A0\nloc_1973:\nmov edi, ebp\nmov [rsp+78h+var_64], eax\nsub ebp, 1\ncall func0_part_0\nmov edx, [rsp+78h+var_64]\nmov edi, r14d\nsub edi, ebp\nimul edx, eax\nadd r15d, edx\ncall func0_part_0\ncmp ebp, 1\njg short loc_1973\nnop word ptr [rax+rax+00h]\nloc_19A0:\nadd r15d, eax\ntest ebp, ebp\njz short loc_19D0\nxor ebp, ebp\njmp short loc_1964\nloc_19B0:\ntest ebp, ebp\njg loc_1AE8\nmov eax, 1\nmov r15d, 1\nlea r12d, [rbp-1]\ncmp r14d, eax\njg short loc_1958\nloc_19CC:\nsub r14d, 1\nloc_19D0:\nmov esi, ebx\nadd r13d, 1\nmov ebp, r12d\nimul esi, r15d\nadd [rsp+78h+var_74], esi\nloc_19E1:\ncmp r13d, 1\njz loc_26AF\nlea r12d, [r13-1]\nmov edi, r12d\ncmp r12d, 1\njz loc_1B68\nmov edx, r12d\nxor ebx, ebx\nxor r15d, r15d\nloc_1A04:\nmov [rsp+78h+var_64], edx\ncall func0_part_0\nmov edx, [rsp+78h+var_64]\nadd ebx, eax\ntest r15d, r15d\njz loc_2607\nnop dword ptr [rax+00h]\nloc_1A20:\nlea r15d, [r13-3]\ncmp r13d, 2\njz loc_18F9\nloc_1A2E:\nmov edi, r12d\nsub edi, r15d\ncall func0_part_0\ncmp r15d, 1\njle short loc_1A60\nmov edi, r15d\nmov [rsp+78h+var_64], eax\nsub r15d, 1\ncall func0_part_0\nmov edx, [rsp+78h+var_64]\nimul eax, edx\nadd ebx, eax\njmp short loc_1A2E\nloc_1A60:\nadd ebx, eax\ntest r15d, r15d\njz loc_18F9\nxor r15d, r15d\njmp short loc_1A2E\nloc_1A70:\nadd [rsp+78h+var_74], ebx\ntest r14d, r14d\njz short loc_1A90\nadd r13d, 1\nsub ebp, 1\nxor r14d, r14d\njmp loc_19E1\nloc_1A90:\nmov ebp, [rsp+78h+var_70]\ncmp ebp, 1\njg loc_16FD\nloc_1A9D:\nmov ecx, [rsp+78h+var_74]\nadd [rsp+78h+var_68], ecx\ntest ebp, ebp\njz short loc_1B18\nadd [rsp+78h+var_6C], 1\nxor ebp, ebp\njmp loc_18CB\nloc_1AB8:\nlea ebp, [r14-1]\nmov r13d, 1\nmov edx, ebp\nloc_1AC4:\nmov edi, edx\nmov ecx, 1\ncmp edx, 1\njg loc_1740\nadd r13d, 1\nmov eax, 2\njmp loc_1770\nloc_1AE8:\nlea r12d, [rbp-1]\nmov r15d, 1\nmov r8d, r12d\nloc_1AF5:\nmov edi, r8d\nmov edx, 1\ncmp r8d, 1\njg loc_191A\nadd r15d, 1\nmov eax, 2\njmp loc_1950\nloc_1B18:\nmov r12d, [rsp+78h+var_60]\ncmp r12d, 1\njg loc_1254\nloc_1B27:\nmov ecx, [rsp+78h+var_68]\nadd [rsp+78h+var_54], ecx\ntest r12d, r12d\njz short loc_1B85\nadd [rsp+78h+var_5C], 1\nxor r12d, r12d\njmp loc_16C3\nloc_1B48:\nmov ebx, 1\nloc_1B4D:\nadd ebx, 1\njmp loc_1838\nloc_1B58:\nmov ebx, 1\nloc_1B5D:\nadd ebx, 1\njmp loc_13C0\nloc_1B68:\nmov ebx, 1\nloc_1B6D:\nadd ebx, 1\njmp loc_1A20\nloc_1B78:\nmov ebx, 1\nloc_1B7D:\nadd ebx, 1\njmp loc_15B0\nloc_1B85:\nmov eax, [rsp+78h+var_58]\nmov ecx, [rsp+78h+var_54]\nadd [rsp+78h+var_4C], 1\nmov ebx, [rsp+78h+var_44]\nimul eax, ecx\nadd [rsp+78h+var_48], eax\ncmp [rsp+78h+var_4C], 1\njz loc_2560\nloc_1BA8:\nmov eax, [rsp+78h+var_4C]\nxor r15d, r15d\nmov [rsp+78h+var_50], ebx\nmov [rsp+78h+var_58], 0\nmov [rsp+78h+var_68], 1\nlea r14d, [rax-1]\nmov [rsp+78h+var_5C], r15d\nmov ebp, r14d\nloc_1BCF:\ncmp ebp, 1\njle loc_24DD\nloc_1BD8:\nlea r12d, [rbp-1]\nmov [rsp+78h+var_70], 0\nmov ebp, 1\nmov [rsp+78h+var_6C], 0\nmov r15d, r12d\nmov [rsp+78h+var_54], r12d\nloc_1BF9:\ncmp r15d, 1\njle loc_1FCF\nloc_1C03:\nlea eax, [r15-1]\nlea r12d, [r15-2]\nmov [rsp+78h+var_60], ebp\nxor r13d, r13d\nmov [rsp+78h+var_64], eax\nmov ebx, 1\nmov r15d, r12d\nmov ebp, eax\nmov [rsp+78h+var_74], 0\nloc_1C28:\ncmp ebp, 1\njle loc_1DA0\nmov edi, r15d\ncmp r15d, 1\njle loc_1CE0\nmov edx, r15d\nxor r14d, r14d\nlea r12d, [r15-1]\nxor ecx, ecx\nloc_1C4A:\nmov [rsp+78h+var_40], ecx\nmov [rsp+78h+var_44], edx\ncall func0_part_0\nmov ecx, [rsp+78h+var_40]\nmov edi, 1\nmov edx, [rsp+78h+var_44]\nadd r14d, eax\ntest r15d, r15d\ncmovle edi, r15d\nlea eax, [rcx+1]\ncmp eax, edi\njle loc_25FF\nnop dword ptr [rax+00000000h]\nloc_1C80:\ncmp ebp, eax\njle short loc_1CFC\nnop dword ptr [rax+00h]\nloc_1C88:\nmov edx, ebp\nsub ebp, 1\nsub edx, eax\nlea r15d, [rdx-1]\nloc_1C93:\nmov edi, ebp\nsub edi, r15d\ncall func0_part_0\ncmp r15d, 1\njle short loc_1CD0\nloc_1CA3:\nmov edi, r15d\nmov [rsp+78h+var_44], eax\nsub r15d, 1\ncall func0_part_0\nmov edx, [rsp+78h+var_44]\nmov edi, ebp\nsub edi, r15d\nimul edx, eax\nadd r14d, edx\ncall func0_part_0\ncmp r15d, 1\njg short loc_1CA3\nnop dword ptr [rax]\nloc_1CD0:\nadd r14d, eax\ntest r15d, r15d\njz short loc_1CFF\nxor r15d, r15d\njmp short loc_1C93\nloc_1CE0:\ntest r15d, r15d\njg loc_2020\nmov eax, 1\nmov r14d, 1\nlea r12d, [r15-1]\ncmp ebp, eax\njg short loc_1C88\nloc_1CFC:\nsub ebp, 1\nloc_1CFF:\nmov esi, ebx\nadd r13d, 1\nmov r15d, r12d\nimul esi, r14d\nadd [rsp+78h+var_74], esi\nloc_1D10:\ncmp r13d, 1\njz loc_26E7\nlea r14d, [r13-1]\nmov edi, r14d\ncmp r14d, 1\njz loc_2508\nmov r12d, r14d\nxor ebx, ebx\nxor edx, edx\nloc_1D32:\nmov [rsp+78h+var_44], edx\ncall func0_part_0\nmov edx, [rsp+78h+var_44]\nadd ebx, eax\ntest edx, edx\njz loc_25E4\nnop dword ptr [rax+00000000h]\nloc_1D50:\nlea r12d, [r13-3]\ncmp r13d, 2\njz loc_1C28\nloc_1D5E:\nmov edi, r14d\nsub edi, r12d\ncall func0_part_0\ncmp r12d, 1\njle short loc_1D90\nmov edi, r12d\nmov [rsp+78h+var_44], eax\nsub r12d, 1\ncall func0_part_0\nmov edx, [rsp+78h+var_44]\nimul eax, edx\nadd ebx, eax\njmp short loc_1D5E\nloc_1D90:\nadd ebx, eax\ntest r12d, r12d\njz loc_1C28\nxor r12d, r12d\njmp short loc_1D5E\nloc_1DA0:\nadd [rsp+78h+var_74], ebx\ntest ebp, ebp\njz short loc_1DC0\nadd r13d, 1\nsub r15d, 1\nxor ebp, ebp\njmp loc_1D10\nloc_1DC0:\nmov ebp, [rsp+78h+var_60]\nmov r14d, [rsp+78h+var_74]\nadd [rsp+78h+var_70], 1\nmov r15d, [rsp+78h+var_64]\nimul r14d, ebp\nadd [rsp+78h+var_6C], r14d\nloc_1DDC:\ncmp [rsp+78h+var_70], 1\njz loc_26FB\nmov eax, [rsp+78h+var_70]\nmov [rsp+78h+var_64], r15d\nxor r13d, r13d\nxor ebp, ebp\nmov ebx, 1\nlea r12d, [rax-1]\nlea esi, [rax-2]\nmov ecx, r12d\nmov r15d, esi\nloc_1E07:\ncmp ecx, 1\njle loc_1F90\nmov edi, r15d\ncmp r15d, 1\njle loc_1EB8\nlea eax, [r15-1]\nmov edx, r15d\nxor r14d, r14d\nxor r12d, r12d\nmov [rsp+78h+var_74], eax\nloc_1E2E:\nmov [rsp+78h+var_44], ecx\nmov [rsp+78h+var_60], edx\ncall func0_part_0\nmov edi, 1\nmov edx, [rsp+78h+var_60]\nmov ecx, [rsp+78h+var_44]\nadd r14d, eax\ntest r15d, r15d\nlea eax, [r12+1]\ncmovle edi, r15d\ncmp edi, eax\njge loc_25DC\nnop\nloc_1E60:\ncmp ecx, eax\njle short loc_1ED8\nnop dword ptr [rax+00h]\nloc_1E68:\nmov edx, ecx\nlea r12d, [rcx-1]\nsub edx, eax\nlea r15d, [rdx-1]\nloc_1E74:\nmov edi, r12d\nsub edi, r15d\ncall func0_part_0\ncmp r15d, 1\njle short loc_1EA8\nmov edi, r15d\nmov [rsp+78h+var_60], eax\nsub r15d, 1\ncall func0_part_0\nmov edx, [rsp+78h+var_60]\nimul edx, eax\nadd r14d, edx\njmp short loc_1E74\nloc_1EA8:\nadd r14d, eax\ntest r15d, r15d\njz short loc_1EDC\nxor r15d, r15d\njmp short loc_1E74\nloc_1EB8:\ntest r15d, r15d\njg loc_1FE8\nlea esi, [r15-1]\nmov eax, 1\nmov r14d, 1\nmov [rsp+78h+var_74], esi\ncmp ecx, eax\njg short loc_1E68\nloc_1ED8:\nlea r12d, [rcx-1]\nloc_1EDC:\nimul ebx, r14d\nmov r15d, [rsp+78h+var_74]\nadd r13d, 1\nmov ecx, r12d\nadd ebp, ebx\nloc_1EEE:\ncmp r13d, 1\njz loc_26F1\nlea r12d, [r13-1]\nmov edi, r12d\ncmp r12d, 1\njz loc_2528\nmov r14d, r12d\nxor edx, edx\nxor ebx, ebx\nloc_1F10:\nmov [rsp+78h+var_60], edx\nmov [rsp+78h+var_74], ecx\ncall func0_part_0\nmov edx, [rsp+78h+var_60]\nmov ecx, [rsp+78h+var_74]\nadd ebx, eax\ntest edx, edx\njz loc_25C1\nnop\nloc_1F30:\nlea r14d, [r13-3]\ncmp r13d, 2\njz loc_1E07\nmov [rsp+78h+var_74], ebp\nmov ebp, ebx\nmov ebx, r14d\nmov r14d, ecx\nloc_1F4A:\nmov edi, r12d\nsub edi, ebx\ncall func0_part_0\ncmp ebx, 1\njle short loc_1F80\nloc_1F59:\nmov edi, ebx\nmov [rsp+78h+var_60], eax\nsub ebx, 1\ncall func0_part_0\nmov edx, [rsp+78h+var_60]\nmov edi, r12d\nsub edi, ebx\nimul edx, eax\nadd ebp, edx\ncall func0_part_0\ncmp ebx, 1\njg short loc_1F59\nnop\nloc_1F80:\nadd ebp, eax\ntest ebx, ebx\njz short loc_1FA8\nxor ebx, ebx\njmp short loc_1F4A\nloc_1F90:\nadd ebp, ebx\ntest ecx, ecx\njz short loc_1FC0\nadd r13d, 1\nsub r15d, 1\nxor ecx, ecx\njmp loc_1EEE\nloc_1FA8:\nmov ebx, ebp\nmov ecx, r14d\nmov ebp, [rsp+78h+var_74]\njmp loc_1E07\nloc_1FC0:\nmov r15d, [rsp+78h+var_64]\ncmp r15d, 1\njg loc_1C03\nloc_1FCF:\nadd [rsp+78h+var_6C], ebp\ntest r15d, r15d\njz short loc_2050\nadd [rsp+78h+var_70], 1\nxor r15d, r15d\njmp loc_1DDC\nloc_1FE8:\nlea eax, [r15-1]\nmov r14d, 1\nmov [rsp+78h+var_74], eax\nmov edx, eax\nloc_1FF8:\nmov edi, edx\nmov r12d, 1\ncmp edx, 1\njg loc_1E2E\nadd r14d, 1\nmov eax, 2\njmp loc_1E60\nloc_2020:\nlea r12d, [r15-1]\nmov r14d, 1\nmov edx, r12d\nloc_202D:\nmov edi, edx\nmov ecx, 1\ncmp edx, 1\njg loc_1C4A\nadd r14d, 1\nmov eax, 2\njmp loc_1C80\nloc_2050:\nmov eax, [rsp+78h+var_68]\nmov ecx, [rsp+78h+var_6C]\nadd [rsp+78h+var_5C], 1\nmov r12d, [rsp+78h+var_54]\nimul eax, ecx\nadd [rsp+78h+var_58], eax\nmov ebp, r12d\nloc_206C:\ncmp [rsp+78h+var_5C], 1\njz loc_2695\nmov eax, [rsp+78h+var_5C]\nmov [rsp+78h+var_68], 0\nmov [rsp+78h+var_6C], 0\nmov [rsp+78h+var_74], 1\nlea r12d, [rax-1]\nmov [rsp+78h+var_60], ebp\nloc_209B:\ncmp r12d, 1\njle loc_244F\nloc_20A5:\nlea r15d, [r12-1]\nlea ebp, [r12-2]\nxor r13d, r13d\nmov ebx, 1\nmov [rsp+78h+var_70], 0\nmov r12d, ebp\nmov [rsp+78h+var_64], r15d\nloc_20C7:\ncmp r15d, 1\njle loc_2240\nmov edi, r12d\ncmp r12d, 1\njle loc_2178\nmov edx, r12d\nxor ecx, ecx\nlea ebp, [r12-1]\nxor r14d, r14d\nloc_20EB:\nmov [rsp+78h+var_44], ecx\nmov [rsp+78h+var_54], edx\ncall func0_part_0\nmov ecx, [rsp+78h+var_44]\nmov edi, 1\nmov edx, [rsp+78h+var_54]\nadd r14d, eax\ntest r12d, r12d\ncmovle edi, r12d\nlea eax, [rcx+1]\ncmp edi, eax\njge loc_25B9\nnop word ptr [rax+rax+00h]\nloc_2120:\ncmp r15d, eax\njle short loc_2196\nnop dword ptr [rax]\nloc_2128:\nmov edx, r15d\nsub r15d, 1\nsub edx, eax\nlea r12d, [rdx-1]\nloc_2135:\nmov edi, r15d\nsub edi, r12d\ncall func0_part_0\ncmp r12d, 1\njle short loc_2168\nmov edi, r12d\nmov [rsp+78h+var_54], eax\nsub r12d, 1\ncall func0_part_0\nmov edx, [rsp+78h+var_54]\nimul edx, eax\nadd r14d, edx\njmp short loc_2135\nloc_2168:\nadd r14d, eax\ntest r12d, r12d\njz short loc_219A\nxor r12d, r12d\njmp short loc_2135\nloc_2178:\ntest r12d, r12d\njg loc_2470\nmov eax, 1\nmov r14d, 1\nlea ebp, [r12-1]\ncmp r15d, eax\njg short loc_2128\nloc_2196:\nsub r15d, 1\nloc_219A:\nmov esi, ebx\nadd r13d, 1\nmov r12d, ebp\nimul esi, r14d\nadd [rsp+78h+var_70], esi\nloc_21AB:\ncmp r13d, 1\njz loc_271C\nlea r14d, [r13-1]\nmov edi, r14d\ncmp r14d, 1\njz loc_24F8\nmov ebp, r14d\nxor ebx, ebx\nxor edx, edx\nloc_21CD:\nmov [rsp+78h+var_54], edx\ncall func0_part_0\nmov edx, [rsp+78h+var_54]\nadd ebx, eax\ntest edx, edx\njz loc_25A1\nnop dword ptr [rax+00h]\nloc_21E8:\nlea ebp, [r13-3]\ncmp r13d, 2\njz loc_20C7\nloc_21F6:\nmov edi, r14d\nsub edi, ebp\ncall func0_part_0\ncmp ebp, 1\njle short loc_2230\nloc_2205:\nmov edi, ebp\nmov [rsp+78h+var_54], eax\nsub ebp, 1\ncall func0_part_0\nmov edx, [rsp+78h+var_54]\nmov edi, r14d\nsub edi, ebp\nimul edx, eax\nadd ebx, edx\ncall func0_part_0\ncmp ebp, 1\njg short loc_2205\nnop dword ptr [rax+rax+00h]\nloc_2230:\nadd ebx, eax\ntest ebp, ebp\njz loc_20C7\nxor ebp, ebp\njmp short loc_21F6\nloc_2240:\nadd [rsp+78h+var_70], ebx\ntest r15d, r15d\njz short loc_2260\nadd r13d, 1\nsub r12d, 1\nxor r15d, r15d\njmp loc_21AB\nloc_2260:\nmov r14d, [rsp+78h+var_74]\nmov eax, [rsp+78h+var_70]\nadd [rsp+78h+var_6C], 1\nmov r15d, [rsp+78h+var_64]\nimul r14d, eax\nadd [rsp+78h+var_68], r14d\nmov r12d, r15d\nloc_227F:\ncmp [rsp+78h+var_6C], 1\njz loc_270F\nmov eax, [rsp+78h+var_6C]\nmov [rsp+78h+var_70], r12d\nxor r13d, r13d\nmov ebx, 1\nmov [rsp+78h+var_74], 0\nlea ebp, [rax-1]\nlea r15d, [rax-2]\nmov r14d, r15d\nmov r12d, ebp\nloc_22B0:\ncmp r12d, 1\njle loc_2420\nmov edi, r14d\ncmp r14d, 1\njle loc_2358\nmov edx, r14d\nxor ebp, ebp\nlea r15d, [r14-1]\nxor ecx, ecx\nloc_22D2:\nmov [rsp+78h+var_54], ecx\nmov [rsp+78h+var_64], edx\ncall func0_part_0\nmov ecx, [rsp+78h+var_54]\nmov edi, 1\nmov edx, [rsp+78h+var_64]\nadd ebp, eax\ntest r14d, r14d\ncmovle edi, r14d\nlea eax, [rcx+1]\ncmp edi, eax\njge loc_2599\nloc_2300:\ncmp r12d, eax\njle short loc_2374\nnop dword ptr [rax]\nloc_2308:\nmov edx, r12d\nsub r12d, 1\nsub edx, eax\nlea r14d, [rdx-1]\nloc_2315:\nmov edi, r12d\nsub edi, r14d\ncall func0_part_0\ncmp r14d, 1\njle short loc_2348\nmov edi, r14d\nmov [rsp+78h+var_64], eax\nsub r14d, 1\ncall func0_part_0\nmov edx, [rsp+78h+var_64]\nimul edx, eax\nadd ebp, edx\njmp short loc_2315\nloc_2348:\nadd ebp, eax\ntest r14d, r14d\njz short loc_2378\nxor r14d, r14d\njmp short loc_2315\nloc_2358:\ntest r14d, r14d\njg loc_24A0\nmov eax, 1\nmov ebp, 1\nlea r15d, [r14-1]\ncmp r12d, eax\njg short loc_2308\nloc_2374:\nsub r12d, 1\nloc_2378:\nmov esi, ebx\nadd r13d, 1\nmov r14d, r15d\nimul esi, ebp\nadd [rsp+78h+var_74], esi\nloc_2388:\ncmp r13d, 1\njz loc_2705\nlea ebp, [r13-1]\nmov edi, ebp\ncmp ebp, 1\njz loc_2518\nmov r15d, ebp\nxor edx, edx\nxor ebx, ebx\nloc_23A8:\nmov [rsp+78h+var_64], edx\ncall func0_part_0\nmov edx, [rsp+78h+var_64]\nadd ebx, eax\ntest edx, edx\njz loc_2582\nnop\nloc_23C0:\nlea r15d, [r13-3]\ncmp r13d, 2\njz loc_22B0\nloc_23CE:\nmov edi, ebp\nsub edi, r15d\ncall func0_part_0\ncmp r15d, 1\njle short loc_2410\nloc_23DE:\nmov edi, r15d\nmov [rsp+78h+var_64], eax\nsub r15d, 1\ncall func0_part_0\nmov edx, [rsp+78h+var_64]\nmov edi, ebp\nsub edi, r15d\nimul edx, eax\nadd ebx, edx\ncall func0_part_0\ncmp r15d, 1\njg short loc_23DE\nnop word ptr [rax+rax+00000000h]\nloc_2410:\nadd ebx, eax\ntest r15d, r15d\njz loc_22B0\nxor r15d, r15d\njmp short loc_23CE\nloc_2420:\nadd [rsp+78h+var_74], ebx\ntest r12d, r12d\njz short loc_2440\nadd r13d, 1\nsub r14d, 1\nxor r12d, r12d\njmp loc_2388\nloc_2440:\nmov r12d, [rsp+78h+var_70]\ncmp r12d, 1\njg loc_20A5\nloc_244F:\nmov ecx, [rsp+78h+var_74]\nadd [rsp+78h+var_68], ecx\ntest r12d, r12d\njz short loc_24D0\nadd [rsp+78h+var_6C], 1\nxor r12d, r12d\njmp loc_227F\nloc_2470:\nlea ebp, [r12-1]\nmov r14d, 1\nmov edx, ebp\nloc_247D:\nmov edi, edx\nmov ecx, 1\ncmp edx, 1\njg loc_20EB\nadd r14d, 1\nmov eax, 2\njmp loc_2120\nloc_24A0:\nlea r15d, [r14-1]\nmov ebp, 1\nmov edx, r15d\nloc_24AC:\nmov edi, edx\nmov ecx, 1\ncmp edx, 1\njg loc_22D2\nadd ebp, 1\nmov eax, 2\njmp loc_2300\nloc_24D0:\nmov ebp, [rsp+78h+var_60]\ncmp ebp, 1\njg loc_1BD8\nloc_24DD:\nmov ecx, [rsp+78h+var_68]\nadd [rsp+78h+var_58], ecx\ntest ebp, ebp\njz short loc_2535\nadd [rsp+78h+var_5C], 1\nxor ebp, ebp\njmp loc_206C\nloc_24F8:\nmov ebx, 1\nloc_24FD:\nadd ebx, 1\njmp loc_21E8\nloc_2508:\nmov ebx, 1\nloc_250D:\nadd ebx, 1\njmp loc_1D50\nloc_2518:\nmov ebx, 1\nloc_251D:\nadd ebx, 1\njmp loc_23C0\nloc_2528:\nmov ebx, 1\nloc_252D:\nadd ebx, 1\njmp loc_1F30\nloc_2535:\nmov ebx, [rsp+78h+var_50]\ncmp ebx, 1\njg loc_1228\nloc_2542:\nmov ecx, [rsp+78h+var_58]\nadd [rsp+78h+var_48], ecx\ntest ebx, ebx\njz short loc_256D\nadd [rsp+78h+var_4C], 1\nxor ebx, ebx\ncmp [rsp+78h+var_4C], 1\njnz loc_1BA8\nloc_2560:\nmov [rsp+78h+var_58], 1\njmp loc_121F\nloc_256D:\nmov ebp, [rsp+78h+var_48]\nloc_2571:\nadd rsp, 48h\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_2582:\nsub r15d, 1\ncmp r15d, 1\njbe short loc_251D\nmov edi, r15d\nmov edx, 1\njmp loc_23A8\nloc_2599:\nsub edx, 1\njmp loc_24AC\nloc_25A1:\nsub ebp, 1\ncmp ebp, 1\njbe loc_24FD\nmov edi, ebp\nmov edx, 1\njmp loc_21CD\nloc_25B9:\nsub edx, 1\njmp loc_247D\nloc_25C1:\nsub r14d, 1\ncmp r14d, 1\njbe loc_252D\nmov edi, r14d\nmov edx, 1\njmp loc_1F10\nloc_25DC:\nsub edx, 1\njmp loc_1FF8\nloc_25E4:\nsub r12d, 1\ncmp r12d, 1\njbe loc_250D\nmov edi, r12d\nmov edx, 1\njmp loc_1D32\nloc_25FF:\nsub edx, 1\njmp loc_202D\nloc_2607:\nsub edx, 1\ncmp edx, 1\njbe loc_1B6D\nmov edi, edx\nmov r15d, 1\njmp loc_1A04\nloc_2620:\nsub r8d, 1\njmp loc_1AF5\nloc_2629:\nsub ebp, 1\ncmp ebp, 1\njbe loc_1B4D\nmov edi, ebp\nmov edx, 1\njmp loc_181D\nloc_2641:\nsub edx, 1\njmp loc_1AC4\nloc_2649:\nsub edx, 1\ncmp edx, 1\njbe loc_1B7D\nmov edi, edx\nmov r15d, 1\njmp loc_1594\nloc_2662:\nsub r8d, 1\njmp loc_1655\nloc_266B:\nsub ebp, 1\ncmp ebp, 1\njbe loc_1B5D\nmov edi, ebp\nmov edx, 1\njmp loc_13A5\nloc_2683:\nsub edx, 1\njmp loc_1684\nloc_268B:\nmov ebx, 1\njmp loc_1489\nloc_2695:\nmov [rsp+78h+var_68], 1\njmp loc_1BCF\nloc_26A2:\nmov [rsp+78h+var_74], 1\njmp loc_1278\nloc_26AF:\nmov ebx, 1\njmp loc_18F9\nloc_26B9:\nmov [rsp+78h+var_74], 1\njmp loc_16F4\nloc_26C6:\nmov ebx, 1\njmp loc_171D\nloc_26D0:\nmov [rsp+78h+var_68], 1\njmp loc_124A\nloc_26DD:\nmov ebx, 1\njmp loc_12A1\nloc_26E7:\nmov ebx, 1\njmp loc_1C28\nloc_26F1:\nmov ebx, 1\njmp loc_1E07\nloc_26FB:\nmov ebp, 1\njmp loc_1BF9\nloc_2705:\nmov ebx, 1\njmp loc_22B0\nloc_270F:\nmov [rsp+78h+var_74], 1\njmp loc_209B\nloc_271C:\nmov ebx, 1\njmp loc_20C7", + "ida_pseudo": "__int64 __fastcall func0_part_0(int a1)\n{\n unsigned int v1; // ebp\n int v2; // ebx\n int v3; // r12d\n int v4; // ebp\n int v5; // r12d\n int v6; // ebx\n int v7; // r14d\n int v8; // r15d\n __int64 v9; // rdi\n int j; // edx\n int v11; // ecx\n int v12; // ebp\n int v13; // r13d\n int v14; // eax\n int v15; // edx\n int i; // r15d\n int v17; // eax\n __int64 v18; // rdi\n int v19; // r13d\n __int64 v20; // rdi\n unsigned int v21; // ebp\n int k; // edx\n int v23; // ebp\n int m; // eax\n __int64 v25; // rdi\n int v26; // r13d\n int v27; // ebx\n int v28; // r14d\n int v29; // ebp\n __int64 v30; // rdi\n int n; // r8d\n int v32; // r15d\n int v33; // r12d\n int v34; // edx\n int v35; // eax\n int v36; // edx\n int ii; // ebp\n int jj; // eax\n __int64 v39; // rdi\n __int64 v40; // rdi\n unsigned int v41; // edx\n int v42; // r15d\n int v43; // r15d\n int v44; // eax\n __int64 v45; // rdi\n int v46; // ebp\n int v47; // r12d\n int v48; // ebx\n int v49; // r14d\n int v50; // r15d\n __int64 v51; // rdi\n int kk; // edx\n int v53; // r13d\n int v54; // ebp\n int v55; // ecx\n int v56; // eax\n int v57; // edx\n int mm; // r14d\n int v59; // eax\n __int64 v60; // rdi\n int v61; // r13d\n __int64 v62; // rdi\n unsigned int v63; // ebp\n int nn; // edx\n int v65; // ebp\n int i1; // eax\n __int64 v67; // rdi\n int v68; // r13d\n int v69; // ebx\n int v70; // r14d\n int v71; // ebp\n __int64 v72; // rdi\n int i2; // r8d\n int v74; // r15d\n int v75; // r12d\n int v76; // edx\n int v77; // eax\n int v78; // edx\n int i3; // ebp\n int i4; // eax\n __int64 v81; // rdi\n __int64 v82; // rdi\n unsigned int v83; // edx\n int i5; // r15d\n int v85; // r15d\n int v86; // eax\n __int64 v87; // rdi\n int v88; // ebp\n int v89; // r12d\n int v90; // ebp\n int v91; // r15d\n int v92; // r13d\n int v93; // ebx\n int v94; // r15d\n int v95; // ebp\n __int64 v96; // rdi\n int i6; // edx\n int v98; // r14d\n int v99; // r12d\n int v100; // ecx\n int v101; // eax\n int v102; // edx\n int i7; // r15d\n int i8; // eax\n __int64 v105; // rdi\n __int64 v106; // rdi\n unsigned int v107; // r12d\n int i9; // edx\n int v109; // r12d\n int v110; // eax\n __int64 v111; // rdi\n int v112; // r13d\n int v113; // ebx\n int v114; // ecx\n int v115; // r15d\n __int64 v116; // rdi\n int i10; // edx\n int v118; // r14d\n int v119; // r12d\n int v120; // eax\n int v121; // eax\n int v122; // r12d\n int i11; // r15d\n int v124; // eax\n __int64 v125; // rdi\n int v126; // r12d\n __int64 v127; // rdi\n unsigned int v128; // r14d\n int v129; // edx\n int v130; // eax\n int v131; // ebp\n int v132; // ebx\n int v133; // r14d\n int i12; // eax\n __int64 v135; // rdi\n int v136; // r12d\n int v137; // r15d\n int v138; // r13d\n int v139; // ebx\n int v140; // r12d\n __int64 v141; // rdi\n int i13; // edx\n int v143; // ecx\n int v144; // ebp\n int v145; // r14d\n int v146; // eax\n int v147; // edx\n int i14; // r12d\n int v149; // eax\n __int64 v150; // rdi\n int v151; // r14d\n __int64 v152; // rdi\n unsigned int v153; // ebp\n int i15; // edx\n int v155; // ebp\n int i16; // eax\n __int64 v157; // rdi\n int v158; // r13d\n int v159; // ebx\n int v160; // r14d\n int v161; // r12d\n __int64 v162; // rdi\n int i17; // edx\n int v164; // ebp\n int v165; // r15d\n int v166; // ecx\n int v167; // eax\n int v168; // edx\n int i18; // r14d\n int v170; // eax\n __int64 v171; // rdi\n int v172; // ebp\n __int64 v173; // rdi\n unsigned int v174; // r15d\n int v175; // edx\n int v176; // r15d\n int i19; // eax\n __int64 v178; // rdi\n int v180; // [rsp+4h] [rbp-74h]\n int v181; // [rsp+4h] [rbp-74h]\n int v182; // [rsp+4h] [rbp-74h]\n int v183; // [rsp+4h] [rbp-74h]\n int v184; // [rsp+4h] [rbp-74h]\n int v185; // [rsp+4h] [rbp-74h]\n int v186; // [rsp+4h] [rbp-74h]\n int v187; // [rsp+8h] [rbp-70h]\n int v188; // [rsp+8h] [rbp-70h]\n int v189; // [rsp+8h] [rbp-70h]\n int v190; // [rsp+8h] [rbp-70h]\n int v191; // [rsp+8h] [rbp-70h]\n int v192; // [rsp+8h] [rbp-70h]\n int v193; // [rsp+8h] [rbp-70h]\n int v194; // [rsp+Ch] [rbp-6Ch]\n int v195; // [rsp+Ch] [rbp-6Ch]\n int v196; // [rsp+Ch] [rbp-6Ch]\n int v197; // [rsp+Ch] [rbp-6Ch]\n int v198; // [rsp+10h] [rbp-68h]\n int v199; // [rsp+10h] [rbp-68h]\n int v200; // [rsp+14h] [rbp-64h]\n int v201; // [rsp+14h] [rbp-64h]\n int v202; // [rsp+14h] [rbp-64h]\n unsigned int v203; // [rsp+14h] [rbp-64h]\n int v204; // [rsp+14h] [rbp-64h]\n int v205; // [rsp+14h] [rbp-64h]\n int v206; // [rsp+14h] [rbp-64h]\n int v207; // [rsp+14h] [rbp-64h]\n int v208; // [rsp+14h] [rbp-64h]\n int v209; // [rsp+18h] [rbp-60h]\n int v210; // [rsp+18h] [rbp-60h]\n unsigned int v211; // [rsp+18h] [rbp-60h]\n int v212; // [rsp+18h] [rbp-60h]\n int v213; // [rsp+18h] [rbp-60h]\n int v214; // [rsp+18h] [rbp-60h]\n int v215; // [rsp+18h] [rbp-60h]\n int v216; // [rsp+18h] [rbp-60h]\n int v217; // [rsp+1Ch] [rbp-5Ch]\n int v218; // [rsp+1Ch] [rbp-5Ch]\n int v219; // [rsp+20h] [rbp-58h]\n int v220; // [rsp+24h] [rbp-54h]\n int v221; // [rsp+24h] [rbp-54h]\n int v222; // [rsp+24h] [rbp-54h]\n int v223; // [rsp+24h] [rbp-54h]\n int v224; // [rsp+24h] [rbp-54h]\n int v225; // [rsp+28h] [rbp-50h]\n int v226; // [rsp+28h] [rbp-50h]\n int v227; // [rsp+28h] [rbp-50h]\n int v228; // [rsp+28h] [rbp-50h]\n int v229; // [rsp+28h] [rbp-50h]\n int v230; // [rsp+2Ch] [rbp-4Ch]\n unsigned int v231; // [rsp+30h] [rbp-48h]\n int v232; // [rsp+34h] [rbp-44h]\n int v233; // [rsp+34h] [rbp-44h]\n int v234; // [rsp+34h] [rbp-44h]\n int v235; // [rsp+34h] [rbp-44h]\n int v236; // [rsp+34h] [rbp-44h]\n int v237; // [rsp+38h] [rbp-40h]\n int v238; // [rsp+38h] [rbp-40h]\n int v239; // [rsp+38h] [rbp-40h]\n int v240; // [rsp+38h] [rbp-40h]\n int v241; // [rsp+38h] [rbp-40h]\n int v242; // [rsp+3Ch] [rbp-3Ch]\n\n v1 = 0;\n if ( a1 <= 0 )\n return v1;\n v219 = 1;\n v2 = a1 - 1;\n v230 = 0;\n v231 = 0;\nLABEL_3:\n if ( v2 <= 1 )\n goto LABEL_298;\n do\n {\n v217 = 0;\n v220 = 0;\n v3 = v2 - 1;\n v198 = 1;\n v232 = v2 - 1;\nLABEL_5:\n if ( v3 <= 1 )\n goto LABEL_139;\n do\n {\n v194 = 0;\n v180 = 1;\n v4 = v3 - 1;\n v200 = 0;\n v225 = v3 - 1;\nLABEL_7:\n if ( v4 <= 1 )\n goto LABEL_63;\n do\n {\n v5 = 0;\n v6 = 1;\n v209 = v4 - 1;\n v7 = v4 - 1;\n v8 = v4 - 2;\n v187 = 0;\n while ( v7 > 1 )\n {\n v9 = (unsigned int)v8;\n if ( v8 > 1 )\n {\n j = v8;\n v11 = 0;\n v12 = v8 - 1;\n v13 = 0;\n goto LABEL_12;\n }\n if ( v8 <= 0 )\n {\n v14 = 1;\n v13 = 1;\n v12 = v8 - 1;\nLABEL_14:\n v15 = v7--;\n for ( i = v15 - v14 - 1; ; i = 0 )\n {\n while ( 1 )\n {\n v17 = func0_part_0((unsigned int)(v7 - i));\n if ( i <= 1 )\n break;\n v18 = (unsigned int)i--;\n v13 += func0_part_0(v18) * v17;\n }\n v13 += v17;\n if ( !i )\n break;\n }\n goto LABEL_22;\n }\n v12 = v8 - 1;\n v13 = 1;\n for ( j = v8 - 1; ; j = v237 - 1 )\n {\n v9 = (unsigned int)j;\n v11 = 1;\n if ( j <= 1 )\n break;\nLABEL_12:\n v242 = v11;\n v237 = j;\n v13 += func0_part_0(v9);\n v14 = v242 + 1;\n if ( v242 + 1 > 1 )\n goto LABEL_13;\n }\n ++v13;\n v14 = 2;\nLABEL_13:\n if ( v7 > v14 )\n goto LABEL_14;\n --v7;\nLABEL_22:\n ++v5;\n v8 = v12;\n v187 += v6 * v13;\nLABEL_23:\n if ( v5 == 1 )\n {\n v6 = 1;\n }\n else\n {\n v19 = v5 - 1;\n v20 = (unsigned int)(v5 - 1);\n if ( v5 == 2 )\n {\n v6 = 1;\nLABEL_144:\n ++v6;\n }\n else\n {\n v21 = v5 - 1;\n v6 = 0;\n for ( k = 0; ; k = 1 )\n {\n v238 = k;\n v6 += func0_part_0(v20);\n if ( v238 )\n break;\n if ( --v21 <= 1 )\n goto LABEL_144;\n v20 = v21;\n }\n }\n v23 = v5 - 3;\n if ( v5 != 2 )\n {\n while ( 1 )\n {\n for ( m = func0_part_0((unsigned int)(v19 - v23)); v23 > 1; m = func0_part_0((unsigned int)(v19 - v23)) )\n {\n v25 = (unsigned int)v23--;\n v6 += func0_part_0(v25) * m;\n }\n v6 += m;\n if ( !v23 )\n break;\n v23 = 0;\n }\n }\n }\n }\n v187 += v6;\n if ( v7 )\n {\n ++v5;\n --v8;\n v7 = 0;\n goto LABEL_23;\n }\n ++v194;\n v4 = v209;\n v200 += v187 * v180;\nLABEL_35:\n if ( v194 == 1 )\n {\n v180 = 1;\n goto LABEL_7;\n }\n v188 = v4;\n v26 = 0;\n v27 = 1;\n v180 = 0;\n v28 = v194 - 1;\n v29 = v194 - 2;\n while ( 2 )\n {\n if ( v28 > 1 )\n {\n v30 = (unsigned int)v29;\n if ( v29 > 1 )\n {\n n = v29;\n v32 = 0;\n v33 = v29 - 1;\n v34 = 0;\n goto LABEL_40;\n }\n if ( v29 <= 0 )\n {\n v35 = 1;\n v32 = 1;\n v33 = v29 - 1;\n goto LABEL_42;\n }\n v33 = v29 - 1;\n v32 = 1;\n for ( n = v29 - 1; ; n = v210 - 1 )\n {\n v30 = (unsigned int)n;\n v34 = 1;\n if ( n <= 1 )\n break;\nLABEL_40:\n v239 = v34;\n v210 = n;\n v32 += func0_part_0(v30);\n v35 = v239 + 1;\n if ( v239 + 1 > 1 )\n goto LABEL_41;\n }\n ++v32;\n v35 = 2;\nLABEL_41:\n if ( v28 <= v35 )\n {\n --v28;\n }\n else\n {\nLABEL_42:\n v36 = v28--;\n for ( ii = v36 - v35 - 1; ; ii = 0 )\n {\n for ( jj = func0_part_0((unsigned int)(v28 - ii)); ii > 1; jj = func0_part_0((unsigned int)(v28 - ii)) )\n {\n v39 = (unsigned int)ii--;\n v32 += func0_part_0(v39) * jj;\n }\n v32 += jj;\n if ( !ii )\n break;\n }\n }\n ++v26;\n v29 = v33;\n v180 += v32 * v27;\nLABEL_51:\n if ( v26 == 1 )\n {\n v27 = 1;\n }\n else\n {\n v40 = (unsigned int)(v26 - 1);\n if ( v26 == 2 )\n {\n v27 = 1;\nLABEL_148:\n ++v27;\n }\n else\n {\n v41 = v26 - 1;\n v42 = 0;\n v27 = 0;\n while ( 1 )\n {\n v211 = v41;\n v27 += func0_part_0(v40);\n if ( v42 )\n break;\n v41 = v211 - 1;\n if ( v211 - 1 <= 1 )\n goto LABEL_148;\n v40 = v41;\n v42 = 1;\n }\n }\n v43 = v26 - 3;\n if ( v26 != 2 )\n {\n while ( 1 )\n {\n while ( 1 )\n {\n v44 = func0_part_0((unsigned int)(v26 - 1 - v43));\n if ( v43 <= 1 )\n break;\n v45 = (unsigned int)v43--;\n v27 += v44 * func0_part_0(v45);\n }\n v27 += v44;\n if ( !v43 )\n break;\n v43 = 0;\n }\n }\n }\n continue;\n }\n break;\n }\n v180 += v27;\n if ( v28 )\n {\n ++v26;\n --v29;\n v28 = 0;\n goto LABEL_51;\n }\n v4 = v188;\n }\n while ( v188 > 1 );\nLABEL_63:\n v200 += v180;\n if ( v4 )\n {\n ++v194;\n v4 = 0;\n goto LABEL_35;\n }\n ++v217;\n v3 = v225;\n v220 += v200 * v198;\nLABEL_72:\n if ( v217 == 1 )\n {\n v198 = 1;\n goto LABEL_5;\n }\n v198 = 0;\n v195 = 0;\n v181 = 1;\n v212 = v3;\n v46 = v217 - 1;\n while ( 2 )\n {\n if ( v46 <= 1 )\n goto LABEL_130;\nLABEL_75:\n v47 = 0;\n v48 = 1;\n v201 = v46 - 1;\n v49 = v46 - 2;\n v50 = v46 - 1;\n v189 = 0;\n while ( 2 )\n {\n if ( v50 > 1 )\n {\n v51 = (unsigned int)v49;\n if ( v49 > 1 )\n {\n kk = v49;\n v53 = 0;\n v54 = v49 - 1;\n v55 = 0;\n goto LABEL_79;\n }\n if ( v49 <= 0 )\n {\n v56 = 1;\n v53 = 1;\n v54 = v49 - 1;\n goto LABEL_81;\n }\n v54 = v49 - 1;\n v53 = 1;\n for ( kk = v49 - 1; ; kk = v226 - 1 )\n {\n v51 = (unsigned int)kk;\n v55 = 1;\n if ( kk <= 1 )\n break;\nLABEL_79:\n v240 = v55;\n v226 = kk;\n v53 += func0_part_0(v51);\n v56 = v240 + 1;\n if ( v240 + 1 > 1 )\n goto LABEL_80;\n }\n ++v53;\n v56 = 2;\nLABEL_80:\n if ( v50 <= v56 )\n {\n --v50;\n }\n else\n {\nLABEL_81:\n v57 = v50--;\n for ( mm = v57 - v56 - 1; ; mm = 0 )\n {\n while ( 1 )\n {\n v59 = func0_part_0((unsigned int)(v50 - mm));\n if ( mm <= 1 )\n break;\n v60 = (unsigned int)mm--;\n v53 += func0_part_0(v60) * v59;\n }\n v53 += v59;\n if ( !mm )\n break;\n }\n }\n ++v47;\n v49 = v54;\n v189 += v53 * v48;\nLABEL_90:\n if ( v47 == 1 )\n {\n v48 = 1;\n }\n else\n {\n v61 = v47 - 1;\n v62 = (unsigned int)(v47 - 1);\n if ( v47 == 2 )\n {\n v48 = 1;\nLABEL_142:\n ++v48;\n }\n else\n {\n v63 = v47 - 1;\n v48 = 0;\n for ( nn = 0; ; nn = 1 )\n {\n v227 = nn;\n v48 += func0_part_0(v62);\n if ( v227 )\n break;\n if ( --v63 <= 1 )\n goto LABEL_142;\n v62 = v63;\n }\n }\n v65 = v47 - 3;\n if ( v47 != 2 )\n {\n while ( 1 )\n {\n for ( i1 = func0_part_0((unsigned int)(v61 - v65)); v65 > 1; i1 = func0_part_0((unsigned int)(v61 - v65)) )\n {\n v67 = (unsigned int)v65--;\n v48 += func0_part_0(v67) * i1;\n }\n v48 += i1;\n if ( !v65 )\n break;\n v65 = 0;\n }\n }\n }\n continue;\n }\n break;\n }\n v189 += v48;\n if ( v50 )\n {\n ++v47;\n --v49;\n v50 = 0;\n goto LABEL_90;\n }\n ++v195;\n v46 = v201;\n v198 += v189 * v181;\nLABEL_102:\n if ( v195 == 1 )\n {\n v181 = 1;\n continue;\n }\n break;\n }\n v190 = v46;\n v68 = 0;\n v69 = 1;\n v181 = 0;\n v70 = v195 - 1;\n v71 = v195 - 2;\n while ( 2 )\n {\n if ( v70 > 1 )\n {\n v72 = (unsigned int)v71;\n if ( v71 > 1 )\n {\n i2 = v71;\n v74 = 0;\n v75 = v71 - 1;\n v76 = 0;\n goto LABEL_107;\n }\n if ( v71 <= 0 )\n {\n v77 = 1;\n v74 = 1;\n v75 = v71 - 1;\n goto LABEL_109;\n }\n v75 = v71 - 1;\n v74 = 1;\n for ( i2 = v71 - 1; ; i2 = v202 - 1 )\n {\n v72 = (unsigned int)i2;\n v76 = 1;\n if ( i2 <= 1 )\n break;\nLABEL_107:\n v228 = v76;\n v202 = i2;\n v74 += func0_part_0(v72);\n v77 = v228 + 1;\n if ( v228 + 1 > 1 )\n goto LABEL_108;\n }\n ++v74;\n v77 = 2;\nLABEL_108:\n if ( v70 <= v77 )\n {\n --v70;\n }\n else\n {\nLABEL_109:\n v78 = v70--;\n for ( i3 = v78 - v77 - 1; ; i3 = 0 )\n {\n for ( i4 = func0_part_0((unsigned int)(v70 - i3)); i3 > 1; i4 = func0_part_0((unsigned int)(v70 - i3)) )\n {\n v81 = (unsigned int)i3--;\n v74 += func0_part_0(v81) * i4;\n }\n v74 += i4;\n if ( !i3 )\n break;\n }\n }\n ++v68;\n v71 = v75;\n v181 += v74 * v69;\nLABEL_118:\n if ( v68 == 1 )\n {\n v69 = 1;\n }\n else\n {\n v82 = (unsigned int)(v68 - 1);\n if ( v68 == 2 )\n {\n v69 = 1;\nLABEL_146:\n ++v69;\n }\n else\n {\n v83 = v68 - 1;\n v69 = 0;\n for ( i5 = 0; ; i5 = 1 )\n {\n v203 = v83;\n v69 += func0_part_0(v82);\n if ( i5 )\n break;\n v83 = v203 - 1;\n if ( v203 - 1 <= 1 )\n goto LABEL_146;\n v82 = v83;\n }\n }\n v85 = v68 - 3;\n if ( v68 != 2 )\n {\n while ( 1 )\n {\n while ( 1 )\n {\n v86 = func0_part_0((unsigned int)(v68 - 1 - v85));\n if ( v85 <= 1 )\n break;\n v87 = (unsigned int)v85--;\n v69 += v86 * func0_part_0(v87);\n }\n v69 += v86;\n if ( !v85 )\n break;\n v85 = 0;\n }\n }\n }\n continue;\n }\n break;\n }\n v181 += v69;\n if ( v70 )\n {\n ++v68;\n --v71;\n v70 = 0;\n goto LABEL_118;\n }\n v46 = v190;\n if ( v190 > 1 )\n goto LABEL_75;\nLABEL_130:\n v198 += v181;\n if ( v46 )\n {\n ++v195;\n v46 = 0;\n goto LABEL_102;\n }\n v3 = v212;\n }\n while ( v212 > 1 );\nLABEL_139:\n v220 += v198;\n if ( v3 )\n {\n ++v217;\n v3 = 0;\n goto LABEL_72;\n }\n ++v230;\n v2 = v232;\n v231 += v220 * v219;\n if ( v230 == 1 )\n {\nLABEL_300:\n v219 = 1;\n goto LABEL_3;\n }\nLABEL_150:\n v229 = v2;\n v219 = 0;\n v199 = 1;\n v218 = 0;\n v88 = v230 - 1;\n while ( 2 )\n {\n if ( v88 <= 1 )\n goto LABEL_287;\nLABEL_152:\n v89 = v88 - 1;\n v191 = 0;\n v90 = 1;\n v196 = 0;\n v91 = v89;\n v221 = v89;\n while ( 2 )\n {\n if ( v91 <= 1 )\n goto LABEL_211;\nLABEL_154:\n v213 = v90;\n v92 = 0;\n v204 = v91 - 1;\n v93 = 1;\n v94 = v91 - 2;\n v95 = v204;\n v182 = 0;\n while ( 2 )\n {\n if ( v95 > 1 )\n {\n v96 = (unsigned int)v94;\n if ( v94 > 1 )\n {\n i6 = v94;\n v98 = 0;\n v99 = v94 - 1;\n v100 = 0;\n goto LABEL_158;\n }\n if ( v94 <= 0 )\n {\n v101 = 1;\n v98 = 1;\n v99 = v94 - 1;\n goto LABEL_160;\n }\n v99 = v94 - 1;\n v98 = 1;\n for ( i6 = v94 - 1; ; i6 = v233 - 1 )\n {\n v96 = (unsigned int)i6;\n v100 = 1;\n if ( i6 <= 1 )\n break;\nLABEL_158:\n v241 = v100;\n v233 = i6;\n v98 += func0_part_0(v96);\n v101 = v241 + 1;\n if ( v241 + 1 > 1 )\n goto LABEL_159;\n }\n ++v98;\n v101 = 2;\nLABEL_159:\n if ( v95 <= v101 )\n {\n --v95;\n }\n else\n {\nLABEL_160:\n v102 = v95--;\n for ( i7 = v102 - v101 - 1; ; i7 = 0 )\n {\n for ( i8 = func0_part_0((unsigned int)(v95 - i7)); i7 > 1; i8 = func0_part_0((unsigned int)(v95 - i7)) )\n {\n v105 = (unsigned int)i7--;\n v98 += func0_part_0(v105) * i8;\n }\n v98 += i8;\n if ( !i7 )\n break;\n }\n }\n ++v92;\n v94 = v99;\n v182 += v98 * v93;\nLABEL_169:\n if ( v92 == 1 )\n {\n v93 = 1;\n }\n else\n {\n v106 = (unsigned int)(v92 - 1);\n if ( v92 == 2 )\n {\n v93 = 1;\nLABEL_292:\n ++v93;\n }\n else\n {\n v107 = v92 - 1;\n v93 = 0;\n for ( i9 = 0; ; i9 = 1 )\n {\n v234 = i9;\n v93 += func0_part_0(v106);\n if ( v234 )\n break;\n if ( --v107 <= 1 )\n goto LABEL_292;\n v106 = v107;\n }\n }\n v109 = v92 - 3;\n if ( v92 != 2 )\n {\n while ( 1 )\n {\n while ( 1 )\n {\n v110 = func0_part_0((unsigned int)(v92 - 1 - v109));\n if ( v109 <= 1 )\n break;\n v111 = (unsigned int)v109--;\n v93 += v110 * func0_part_0(v111);\n }\n v93 += v110;\n if ( !v109 )\n break;\n v109 = 0;\n }\n }\n }\n continue;\n }\n break;\n }\n v182 += v93;\n if ( v95 )\n {\n ++v92;\n --v94;\n v95 = 0;\n goto LABEL_169;\n }\n ++v191;\n v91 = v204;\n v196 += v213 * v182;\nLABEL_181:\n if ( v191 == 1 )\n {\n v90 = 1;\n continue;\n }\n break;\n }\n v205 = v91;\n v112 = 0;\n v90 = 0;\n v113 = 1;\n v114 = v191 - 1;\n v115 = v191 - 2;\n while ( 2 )\n {\n if ( v114 > 1 )\n {\n v116 = (unsigned int)v115;\n if ( v115 > 1 )\n {\n i10 = v115;\n v118 = 0;\n v119 = 0;\n v183 = v115 - 1;\n goto LABEL_186;\n }\n if ( v115 <= 0 )\n {\n v121 = 1;\n v118 = 1;\n v183 = v115 - 1;\n goto LABEL_188;\n }\n v118 = 1;\n v183 = v115 - 1;\n for ( i10 = v115 - 1; ; i10 = v214 - 1 )\n {\n v116 = (unsigned int)i10;\n v119 = 1;\n if ( i10 <= 1 )\n break;\nLABEL_186:\n v235 = v114;\n v214 = i10;\n v120 = func0_part_0(v116);\n v114 = v235;\n v118 += v120;\n v121 = v119 + 1;\n if ( v119 + 1 > 1 )\n goto LABEL_187;\n }\n ++v118;\n v121 = 2;\nLABEL_187:\n if ( v114 <= v121 )\n {\n v122 = v114 - 1;\n }\n else\n {\nLABEL_188:\n v122 = v114 - 1;\n for ( i11 = v114 - v121 - 1; ; i11 = 0 )\n {\n while ( 1 )\n {\n v124 = func0_part_0((unsigned int)(v122 - i11));\n if ( i11 <= 1 )\n break;\n v125 = (unsigned int)i11--;\n v118 += func0_part_0(v125) * v124;\n }\n v118 += v124;\n if ( !i11 )\n break;\n }\n }\n v115 = v183;\n ++v112;\n v114 = v122;\n v90 += v118 * v113;\nLABEL_197:\n if ( v112 == 1 )\n {\n v113 = 1;\n }\n else\n {\n v126 = v112 - 1;\n v127 = (unsigned int)(v112 - 1);\n if ( v112 == 2 )\n {\n v113 = 1;\nLABEL_296:\n ++v113;\n }\n else\n {\n v128 = v112 - 1;\n v129 = 0;\n v113 = 0;\n while ( 1 )\n {\n v215 = v129;\n v184 = v114;\n v130 = func0_part_0(v127);\n v114 = v184;\n v113 += v130;\n if ( v215 )\n break;\n if ( --v128 <= 1 )\n goto LABEL_296;\n v127 = v128;\n v129 = 1;\n }\n }\n if ( v112 != 2 )\n {\n v185 = v90;\n v131 = v113;\n v132 = v112 - 3;\n v133 = v114;\n while ( 1 )\n {\n for ( i12 = func0_part_0((unsigned int)(v126 - v132));\n v132 > 1;\n i12 = func0_part_0((unsigned int)(v126 - v132)) )\n {\n v135 = (unsigned int)v132--;\n v131 += func0_part_0(v135) * i12;\n }\n v131 += i12;\n if ( !v132 )\n break;\n v132 = 0;\n }\n v113 = v131;\n v114 = v133;\n v90 = v185;\n }\n }\n continue;\n }\n break;\n }\n v90 += v113;\n if ( v114 )\n {\n ++v112;\n --v115;\n v114 = 0;\n goto LABEL_197;\n }\n v91 = v205;\n if ( v205 > 1 )\n goto LABEL_154;\nLABEL_211:\n v196 += v90;\n if ( v91 )\n {\n ++v191;\n v91 = 0;\n goto LABEL_181;\n }\n ++v218;\n v219 += v196 * v199;\n v88 = v221;\nLABEL_220:\n if ( v218 == 1 )\n {\n v199 = 1;\n continue;\n }\n break;\n }\n v199 = 0;\n v197 = 0;\n v186 = 1;\n v136 = v218 - 1;\n v216 = v88;\n while ( 2 )\n {\n if ( v136 <= 1 )\n goto LABEL_278;\nLABEL_223:\n v137 = v136 - 1;\n v138 = 0;\n v139 = 1;\n v192 = 0;\n v140 = v136 - 2;\n v206 = v137;\n while ( 2 )\n {\n if ( v137 > 1 )\n {\n v141 = (unsigned int)v140;\n if ( v140 > 1 )\n {\n i13 = v140;\n v143 = 0;\n v144 = v140 - 1;\n v145 = 0;\n goto LABEL_227;\n }\n if ( v140 <= 0 )\n {\n v146 = 1;\n v145 = 1;\n v144 = v140 - 1;\n goto LABEL_229;\n }\n v144 = v140 - 1;\n v145 = 1;\n for ( i13 = v140 - 1; ; i13 = v222 - 1 )\n {\n v141 = (unsigned int)i13;\n v143 = 1;\n if ( i13 <= 1 )\n break;\nLABEL_227:\n v236 = v143;\n v222 = i13;\n v145 += func0_part_0(v141);\n v146 = v236 + 1;\n if ( v236 + 1 > 1 )\n goto LABEL_228;\n }\n ++v145;\n v146 = 2;\nLABEL_228:\n if ( v137 <= v146 )\n {\n --v137;\n }\n else\n {\nLABEL_229:\n v147 = v137--;\n for ( i14 = v147 - v146 - 1; ; i14 = 0 )\n {\n while ( 1 )\n {\n v149 = func0_part_0((unsigned int)(v137 - i14));\n if ( i14 <= 1 )\n break;\n v150 = (unsigned int)i14--;\n v145 += func0_part_0(v150) * v149;\n }\n v145 += v149;\n if ( !i14 )\n break;\n }\n }\n ++v138;\n v140 = v144;\n v192 += v145 * v139;\nLABEL_238:\n if ( v138 == 1 )\n {\n v139 = 1;\n }\n else\n {\n v151 = v138 - 1;\n v152 = (unsigned int)(v138 - 1);\n if ( v138 == 2 )\n {\n v139 = 1;\nLABEL_290:\n ++v139;\n }\n else\n {\n v153 = v138 - 1;\n v139 = 0;\n for ( i15 = 0; ; i15 = 1 )\n {\n v223 = i15;\n v139 += func0_part_0(v152);\n if ( v223 )\n break;\n if ( --v153 <= 1 )\n goto LABEL_290;\n v152 = v153;\n }\n }\n v155 = v138 - 3;\n if ( v138 != 2 )\n {\n while ( 1 )\n {\n for ( i16 = func0_part_0((unsigned int)(v151 - v155));\n v155 > 1;\n i16 = func0_part_0((unsigned int)(v151 - v155)) )\n {\n v157 = (unsigned int)v155--;\n v139 += func0_part_0(v157) * i16;\n }\n v139 += i16;\n if ( !v155 )\n break;\n v155 = 0;\n }\n }\n }\n continue;\n }\n break;\n }\n v192 += v139;\n if ( v137 )\n {\n ++v138;\n --v140;\n v137 = 0;\n goto LABEL_238;\n }\n ++v197;\n v199 += v192 * v186;\n v136 = v206;\nLABEL_250:\n if ( v197 == 1 )\n {\n v186 = 1;\n continue;\n }\n break;\n }\n v193 = v136;\n v158 = 0;\n v159 = 1;\n v186 = 0;\n v160 = v197 - 2;\n v161 = v197 - 1;\n while ( 2 )\n {\n if ( v161 > 1 )\n {\n v162 = (unsigned int)v160;\n if ( v160 > 1 )\n {\n i17 = v160;\n v164 = 0;\n v165 = v160 - 1;\n v166 = 0;\n goto LABEL_255;\n }\n if ( v160 <= 0 )\n {\n v167 = 1;\n v164 = 1;\n v165 = v160 - 1;\n goto LABEL_257;\n }\n v165 = v160 - 1;\n v164 = 1;\n for ( i17 = v160 - 1; ; i17 = v207 - 1 )\n {\n v162 = (unsigned int)i17;\n v166 = 1;\n if ( i17 <= 1 )\n break;\nLABEL_255:\n v224 = v166;\n v207 = i17;\n v164 += func0_part_0(v162);\n v167 = v224 + 1;\n if ( v224 + 1 > 1 )\n goto LABEL_256;\n }\n ++v164;\n v167 = 2;\nLABEL_256:\n if ( v161 <= v167 )\n {\n --v161;\n }\n else\n {\nLABEL_257:\n v168 = v161--;\n for ( i18 = v168 - v167 - 1; ; i18 = 0 )\n {\n while ( 1 )\n {\n v170 = func0_part_0((unsigned int)(v161 - i18));\n if ( i18 <= 1 )\n break;\n v171 = (unsigned int)i18--;\n v164 += func0_part_0(v171) * v170;\n }\n v164 += v170;\n if ( !i18 )\n break;\n }\n }\n ++v158;\n v160 = v165;\n v186 += v164 * v159;\nLABEL_266:\n if ( v158 == 1 )\n {\n v159 = 1;\n }\n else\n {\n v172 = v158 - 1;\n v173 = (unsigned int)(v158 - 1);\n if ( v158 == 2 )\n {\n v159 = 1;\nLABEL_294:\n ++v159;\n }\n else\n {\n v174 = v158 - 1;\n v175 = 0;\n v159 = 0;\n while ( 1 )\n {\n v208 = v175;\n v159 += func0_part_0(v173);\n if ( v208 )\n break;\n if ( --v174 <= 1 )\n goto LABEL_294;\n v173 = v174;\n v175 = 1;\n }\n }\n v176 = v158 - 3;\n if ( v158 != 2 )\n {\n while ( 1 )\n {\n for ( i19 = func0_part_0((unsigned int)(v172 - v176));\n v176 > 1;\n i19 = func0_part_0((unsigned int)(v172 - v176)) )\n {\n v178 = (unsigned int)v176--;\n v159 += func0_part_0(v178) * i19;\n }\n v159 += i19;\n if ( !v176 )\n break;\n v176 = 0;\n }\n }\n }\n continue;\n }\n break;\n }\n v186 += v159;\n if ( v161 )\n {\n ++v158;\n --v160;\n v161 = 0;\n goto LABEL_266;\n }\n v136 = v193;\n if ( v193 > 1 )\n goto LABEL_223;\nLABEL_278:\n v199 += v186;\n if ( v136 )\n {\n ++v197;\n v136 = 0;\n goto LABEL_250;\n }\n v88 = v216;\n if ( v216 > 1 )\n goto LABEL_152;\nLABEL_287:\n v219 += v199;\n if ( v88 )\n {\n ++v218;\n v88 = 0;\n goto LABEL_220;\n }\n v2 = v229;\n }\n while ( v229 > 1 );\nLABEL_298:\n v231 += v219;\n if ( v2 )\n {\n ++v230;\n v2 = 0;\n if ( v230 != 1 )\n goto LABEL_150;\n goto LABEL_300;\n }\n return v231;\n}", + "ida_strip_asm": "sub_11F0:\npush r15\npush r14\npush r13\npush r12\npush rbp\nxor ebp, ebp\npush rbx\nsub rsp, 48h\ntest edi, edi\njle loc_2571\nxor r12d, r12d\nmov [rsp+78h+var_58], 1\nlea ebx, [rdi-1]\nmov [rsp+78h+var_4C], r12d\nmov [rsp+78h+var_48], ebp\nloc_121F:\ncmp ebx, 1\njle loc_2542\nloc_1228:\nsub ebx, 1\nmov [rsp+78h+var_5C], 0\nmov [rsp+78h+var_54], 0\nmov r12d, ebx\nmov [rsp+78h+var_68], 1\nmov [rsp+78h+var_44], ebx\nloc_124A:\ncmp r12d, 1\njle loc_1B27\nloc_1254:\nsub r12d, 1\nxor r14d, r14d\nmov [rsp+78h+var_6C], 0\nmov [rsp+78h+var_74], 1\nmov ebp, r12d\nmov [rsp+78h+var_64], r14d\nmov [rsp+78h+var_50], r12d\nloc_1278:\ncmp ebp, 1\njle loc_162D\nloc_1281:\nlea eax, [rbp-1]\nsub ebp, 2\nxor r12d, r12d\nmov ebx, 1\nmov [rsp+78h+var_60], eax\nmov r14d, eax\nmov r15d, ebp\nmov [rsp+78h+var_70], 0\nloc_12A1:\ncmp r14d, 1\njle loc_1420\nmov edi, r15d\ncmp r15d, 1\njle loc_1350\nmov edx, r15d\nxor ecx, ecx\nlea ebp, [r15-1]\nxor r13d, r13d\nloc_12C4:\nmov [rsp+78h+var_3C], ecx\nmov [rsp+78h+var_40], edx\ncall sub_11F0\nmov ecx, [rsp+78h+var_3C]\nmov edi, 1\nmov edx, [rsp+78h+var_40]\nadd r13d, eax\ntest r15d, r15d\ncmovle edi, r15d\nlea eax, [rcx+1]\ncmp edi, eax\njge loc_2683\nnop dword ptr [rax+rax+00h]\nloc_12F8:\ncmp r14d, eax\njle short loc_136D\nnop dword ptr [rax]\nloc_1300:\nmov edx, r14d\nsub r14d, 1\nsub edx, eax\nlea r15d, [rdx-1]\nloc_130D:\nmov edi, r14d\nsub edi, r15d\ncall sub_11F0\ncmp r15d, 1\njle short loc_1340\nmov edi, r15d\nmov [rsp+78h+var_40], eax\nsub r15d, 1\ncall sub_11F0\nmov edx, [rsp+78h+var_40]\nimul edx, eax\nadd r13d, edx\njmp short loc_130D\nloc_1340:\nadd r13d, eax\ntest r15d, r15d\njz short loc_1371\nxor r15d, r15d\njmp short loc_130D\nloc_1350:\ntest r15d, r15d\njg loc_1678\nmov eax, 1\nmov r13d, 1\nlea ebp, [r15-1]\ncmp r14d, eax\njg short loc_1300\nloc_136D:\nsub r14d, 1\nloc_1371:\nmov esi, r13d\nadd r12d, 1\nmov r15d, ebp\nimul esi, ebx\nadd [rsp+78h+var_70], esi\nloc_1382:\ncmp r12d, 1\njz loc_26DD\nlea r13d, [r12-1]\nmov edi, r13d\ncmp r13d, 1\njz loc_1B58\nmov ebp, r13d\nxor ebx, ebx\nxor edx, edx\nloc_13A5:\nmov [rsp+78h+var_40], edx\ncall sub_11F0\nmov edx, [rsp+78h+var_40]\nadd ebx, eax\ntest edx, edx\njz loc_266B\nnop dword ptr [rax+00h]\nloc_13C0:\nlea ebp, [r12-3]\ncmp r12d, 2\njz loc_12A1\nloc_13CF:\nmov edi, r13d\nsub edi, ebp\ncall sub_11F0\ncmp ebp, 1\njle short loc_1408\nloc_13DE:\nmov edi, ebp\nmov [rsp+78h+var_40], eax\nsub ebp, 1\ncall sub_11F0\nmov edx, [rsp+78h+var_40]\nmov edi, r13d\nsub edi, ebp\nimul edx, eax\nadd ebx, edx\ncall sub_11F0\ncmp ebp, 1\njg short loc_13DE\nnop dword ptr [rax+00h]\nloc_1408:\nadd ebx, eax\ntest ebp, ebp\njz loc_12A1\nxor ebp, ebp\njmp short loc_13CF\nloc_1420:\nadd [rsp+78h+var_70], ebx\ntest r14d, r14d\njz short loc_1440\nadd r12d, 1\nsub r15d, 1\nxor r14d, r14d\njmp loc_1382\nloc_1440:\nmov r13d, [rsp+78h+var_74]\nmov eax, [rsp+78h+var_70]\nadd [rsp+78h+var_6C], 1\nmov ebp, [rsp+78h+var_60]\nimul r13d, eax\nadd [rsp+78h+var_64], r13d\nloc_145B:\ncmp [rsp+78h+var_6C], 1\njz loc_26A2\nmov eax, [rsp+78h+var_6C]\nmov [rsp+78h+var_70], ebp\nxor r13d, r13d\nmov ebx, 1\nmov [rsp+78h+var_74], 0\nlea r12d, [rax-2]\nlea r14d, [rax-1]\nmov ebp, r12d\nloc_1489:\ncmp r14d, 1\njle loc_1600\nmov edi, ebp\ncmp ebp, 1\njle loc_1540\nmov r8d, ebp\nxor r15d, r15d\nlea r12d, [rbp-1]\nxor edx, edx\nloc_14AA:\nmov [rsp+78h+var_40], edx\nmov [rsp+78h+var_60], r8d\ncall sub_11F0\nmov edx, [rsp+78h+var_40]\nmov r8d, [rsp+78h+var_60]\nadd r15d, eax\ntest ebp, ebp\nlea eax, [rdx+1]\nmov edx, 1\ncmovle edx, ebp\ncmp edx, eax\njge loc_2662\nnop dword ptr [rax+00000000h]\nloc_14E0:\ncmp r14d, eax\njle short loc_155C\nnop dword ptr [rax]\nloc_14E8:\nmov edx, r14d\nsub r14d, 1\nsub edx, eax\nlea ebp, [rdx-1]\nloc_14F4:\nmov edi, r14d\nsub edi, ebp\ncall sub_11F0\ncmp ebp, 1\njle short loc_1530\nloc_1503:\nmov edi, ebp\nmov [rsp+78h+var_60], eax\nsub ebp, 1\ncall sub_11F0\nmov edx, [rsp+78h+var_60]\nmov edi, r14d\nsub edi, ebp\nimul edx, eax\nadd r15d, edx\ncall sub_11F0\ncmp ebp, 1\njg short loc_1503\nnop word ptr [rax+rax+00h]\nloc_1530:\nadd r15d, eax\ntest ebp, ebp\njz short loc_1560\nxor ebp, ebp\njmp short loc_14F4\nloc_1540:\ntest ebp, ebp\njg loc_1648\nmov eax, 1\nmov r15d, 1\nlea r12d, [rbp-1]\ncmp r14d, eax\njg short loc_14E8\nloc_155C:\nsub r14d, 1\nloc_1560:\nmov esi, ebx\nadd r13d, 1\nmov ebp, r12d\nimul esi, r15d\nadd [rsp+78h+var_74], esi\nloc_1571:\ncmp r13d, 1\njz loc_268B\nlea r12d, [r13-1]\nmov edi, r12d\ncmp r12d, 1\njz loc_1B78\nmov edx, r12d\nxor r15d, r15d\nxor ebx, ebx\nloc_1594:\nmov [rsp+78h+var_60], edx\ncall sub_11F0\nmov edx, [rsp+78h+var_60]\nadd ebx, eax\ntest r15d, r15d\njz loc_2649\nnop dword ptr [rax+00h]\nloc_15B0:\nlea r15d, [r13-3]\ncmp r13d, 2\njz loc_1489\nloc_15BE:\nmov edi, r12d\nsub edi, r15d\ncall sub_11F0\ncmp r15d, 1\njle short loc_15F0\nmov edi, r15d\nmov [rsp+78h+var_60], eax\nsub r15d, 1\ncall sub_11F0\nmov edx, [rsp+78h+var_60]\nimul eax, edx\nadd ebx, eax\njmp short loc_15BE\nloc_15F0:\nadd ebx, eax\ntest r15d, r15d\njz loc_1489\nxor r15d, r15d\njmp short loc_15BE\nloc_1600:\nadd [rsp+78h+var_74], ebx\ntest r14d, r14d\njz short loc_1620\nadd r13d, 1\nsub ebp, 1\nxor r14d, r14d\njmp loc_1571\nloc_1620:\nmov ebp, [rsp+78h+var_70]\ncmp ebp, 1\njg loc_1281\nloc_162D:\nmov ecx, [rsp+78h+var_74]\nadd [rsp+78h+var_64], ecx\ntest ebp, ebp\njz short loc_16A8\nadd [rsp+78h+var_6C], 1\nxor ebp, ebp\njmp loc_145B\nloc_1648:\nlea r12d, [rbp-1]\nmov r15d, 1\nmov r8d, r12d\nloc_1655:\nmov edi, r8d\nmov edx, 1\ncmp r8d, 1\njg loc_14AA\nadd r15d, 1\nmov eax, 2\njmp loc_14E0\nloc_1678:\nlea ebp, [r15-1]\nmov r13d, 1\nmov edx, ebp\nloc_1684:\nmov edi, edx\nmov ecx, 1\ncmp edx, 1\njg loc_12C4\nadd r13d, 1\nmov eax, 2\njmp loc_12F8\nloc_16A8:\nmov r14d, [rsp+78h+var_64]\nmov eax, [rsp+78h+var_68]\nadd [rsp+78h+var_5C], 1\nmov r12d, [rsp+78h+var_50]\nimul eax, r14d\nadd [rsp+78h+var_54], eax\nloc_16C3:\ncmp [rsp+78h+var_5C], 1\njz loc_26D0\nmov eax, [rsp+78h+var_5C]\nmov [rsp+78h+var_68], 0\nmov [rsp+78h+var_6C], 0\nmov [rsp+78h+var_74], 1\nsub eax, 1\nmov [rsp+78h+var_60], r12d\nmov ebp, eax\nloc_16F4:\ncmp ebp, 1\njle loc_1A9D\nloc_16FD:\nlea eax, [rbp-1]\nsub ebp, 2\nxor r12d, r12d\nmov ebx, 1\nmov [rsp+78h+var_64], eax\nmov r14d, ebp\nmov r15d, eax\nmov [rsp+78h+var_70], 0\nloc_171D:\ncmp r15d, 1\njle loc_1890\nmov edi, r14d\ncmp r14d, 1\njle loc_17C8\nmov edx, r14d\nxor r13d, r13d\nlea ebp, [r14-1]\nxor ecx, ecx\nloc_1740:\nmov [rsp+78h+var_40], ecx\nmov [rsp+78h+var_50], edx\ncall sub_11F0\nmov ecx, [rsp+78h+var_40]\nmov edi, 1\nmov edx, [rsp+78h+var_50]\nadd r13d, eax\ntest r14d, r14d\ncmovle edi, r14d\nlea eax, [rcx+1]\ncmp eax, edi\njle loc_2641\nnop\nloc_1770:\ncmp r15d, eax\njle short loc_17E5\nnop dword ptr [rax]\nloc_1778:\nmov edx, r15d\nsub r15d, 1\nsub edx, eax\nlea r14d, [rdx-1]\nloc_1785:\nmov edi, r15d\nsub edi, r14d\ncall sub_11F0\ncmp r14d, 1\njle short loc_17B8\nmov edi, r14d\nmov [rsp+78h+var_50], eax\nsub r14d, 1\ncall sub_11F0\nmov edx, [rsp+78h+var_50]\nimul edx, eax\nadd r13d, edx\njmp short loc_1785\nloc_17B8:\nadd r13d, eax\ntest r14d, r14d\njz short loc_17E9\nxor r14d, r14d\njmp short loc_1785\nloc_17C8:\ntest r14d, r14d\njg loc_1AB8\nmov eax, 1\nmov r13d, 1\nlea ebp, [r14-1]\ncmp r15d, eax\njg short loc_1778\nloc_17E5:\nsub r15d, 1\nloc_17E9:\nmov esi, ebx\nadd r12d, 1\nmov r14d, ebp\nimul esi, r13d\nadd [rsp+78h+var_70], esi\nloc_17FA:\ncmp r12d, 1\njz loc_26C6\nlea r13d, [r12-1]\nmov edi, r13d\ncmp r13d, 1\njz loc_1B48\nmov ebp, r13d\nxor ebx, ebx\nxor edx, edx\nloc_181D:\nmov [rsp+78h+var_50], edx\ncall sub_11F0\nmov edx, [rsp+78h+var_50]\nadd ebx, eax\ntest edx, edx\njz loc_2629\nnop dword ptr [rax+00h]\nloc_1838:\nlea ebp, [r12-3]\ncmp r12d, 2\njz loc_171D\nloc_1847:\nmov edi, r13d\nsub edi, ebp\ncall sub_11F0\ncmp ebp, 1\njle short loc_1880\nloc_1856:\nmov edi, ebp\nmov [rsp+78h+var_50], eax\nsub ebp, 1\ncall sub_11F0\nmov edx, [rsp+78h+var_50]\nmov edi, r13d\nsub edi, ebp\nimul edx, eax\nadd ebx, edx\ncall sub_11F0\ncmp ebp, 1\njg short loc_1856\nnop dword ptr [rax+00h]\nloc_1880:\nadd ebx, eax\ntest ebp, ebp\njz loc_171D\nxor ebp, ebp\njmp short loc_1847\nloc_1890:\nadd [rsp+78h+var_70], ebx\ntest r15d, r15d\njz short loc_18B0\nadd r12d, 1\nsub r14d, 1\nxor r15d, r15d\njmp loc_17FA\nloc_18B0:\nmov r13d, [rsp+78h+var_74]\nmov eax, [rsp+78h+var_70]\nadd [rsp+78h+var_6C], 1\nmov ebp, [rsp+78h+var_64]\nimul r13d, eax\nadd [rsp+78h+var_68], r13d\nloc_18CB:\ncmp [rsp+78h+var_6C], 1\njz loc_26B9\nmov eax, [rsp+78h+var_6C]\nmov [rsp+78h+var_70], ebp\nxor r13d, r13d\nmov ebx, 1\nmov [rsp+78h+var_74], 0\nlea r12d, [rax-2]\nlea r14d, [rax-1]\nmov ebp, r12d\nloc_18F9:\ncmp r14d, 1\njle loc_1A70\nmov edi, ebp\ncmp ebp, 1\njle loc_19B0\nmov r8d, ebp\nxor r15d, r15d\nlea r12d, [rbp-1]\nxor edx, edx\nloc_191A:\nmov [rsp+78h+var_50], edx\nmov [rsp+78h+var_64], r8d\ncall sub_11F0\nmov edx, [rsp+78h+var_50]\nmov r8d, [rsp+78h+var_64]\nadd r15d, eax\ntest ebp, ebp\nlea eax, [rdx+1]\nmov edx, 1\ncmovle edx, ebp\ncmp edx, eax\njge loc_2620\nnop dword ptr [rax+00000000h]\nloc_1950:\ncmp r14d, eax\njle short loc_19CC\nnop dword ptr [rax]\nloc_1958:\nmov edx, r14d\nsub r14d, 1\nsub edx, eax\nlea ebp, [rdx-1]\nloc_1964:\nmov edi, r14d\nsub edi, ebp\ncall sub_11F0\ncmp ebp, 1\njle short loc_19A0\nloc_1973:\nmov edi, ebp\nmov [rsp+78h+var_64], eax\nsub ebp, 1\ncall sub_11F0\nmov edx, [rsp+78h+var_64]\nmov edi, r14d\nsub edi, ebp\nimul edx, eax\nadd r15d, edx\ncall sub_11F0\ncmp ebp, 1\njg short loc_1973\nnop word ptr [rax+rax+00h]\nloc_19A0:\nadd r15d, eax\ntest ebp, ebp\njz short loc_19D0\nxor ebp, ebp\njmp short loc_1964\nloc_19B0:\ntest ebp, ebp\njg loc_1AE8\nmov eax, 1\nmov r15d, 1\nlea r12d, [rbp-1]\ncmp r14d, eax\njg short loc_1958\nloc_19CC:\nsub r14d, 1\nloc_19D0:\nmov esi, ebx\nadd r13d, 1\nmov ebp, r12d\nimul esi, r15d\nadd [rsp+78h+var_74], esi\nloc_19E1:\ncmp r13d, 1\njz loc_26AF\nlea r12d, [r13-1]\nmov edi, r12d\ncmp r12d, 1\njz loc_1B68\nmov edx, r12d\nxor ebx, ebx\nxor r15d, r15d\nloc_1A04:\nmov [rsp+78h+var_64], edx\ncall sub_11F0\nmov edx, [rsp+78h+var_64]\nadd ebx, eax\ntest r15d, r15d\njz loc_2607\nnop dword ptr [rax+00h]\nloc_1A20:\nlea r15d, [r13-3]\ncmp r13d, 2\njz loc_18F9\nloc_1A2E:\nmov edi, r12d\nsub edi, r15d\ncall sub_11F0\ncmp r15d, 1\njle short loc_1A60\nmov edi, r15d\nmov [rsp+78h+var_64], eax\nsub r15d, 1\ncall sub_11F0\nmov edx, [rsp+78h+var_64]\nimul eax, edx\nadd ebx, eax\njmp short loc_1A2E\nloc_1A60:\nadd ebx, eax\ntest r15d, r15d\njz loc_18F9\nxor r15d, r15d\njmp short loc_1A2E\nloc_1A70:\nadd [rsp+78h+var_74], ebx\ntest r14d, r14d\njz short loc_1A90\nadd r13d, 1\nsub ebp, 1\nxor r14d, r14d\njmp loc_19E1\nloc_1A90:\nmov ebp, [rsp+78h+var_70]\ncmp ebp, 1\njg loc_16FD\nloc_1A9D:\nmov ecx, [rsp+78h+var_74]\nadd [rsp+78h+var_68], ecx\ntest ebp, ebp\njz short loc_1B18\nadd [rsp+78h+var_6C], 1\nxor ebp, ebp\njmp loc_18CB\nloc_1AB8:\nlea ebp, [r14-1]\nmov r13d, 1\nmov edx, ebp\nloc_1AC4:\nmov edi, edx\nmov ecx, 1\ncmp edx, 1\njg loc_1740\nadd r13d, 1\nmov eax, 2\njmp loc_1770\nloc_1AE8:\nlea r12d, [rbp-1]\nmov r15d, 1\nmov r8d, r12d\nloc_1AF5:\nmov edi, r8d\nmov edx, 1\ncmp r8d, 1\njg loc_191A\nadd r15d, 1\nmov eax, 2\njmp loc_1950\nloc_1B18:\nmov r12d, [rsp+78h+var_60]\ncmp r12d, 1\njg loc_1254\nloc_1B27:\nmov ecx, [rsp+78h+var_68]\nadd [rsp+78h+var_54], ecx\ntest r12d, r12d\njz short loc_1B85\nadd [rsp+78h+var_5C], 1\nxor r12d, r12d\njmp loc_16C3\nloc_1B48:\nmov ebx, 1\nloc_1B4D:\nadd ebx, 1\njmp loc_1838\nloc_1B58:\nmov ebx, 1\nloc_1B5D:\nadd ebx, 1\njmp loc_13C0\nloc_1B68:\nmov ebx, 1\nloc_1B6D:\nadd ebx, 1\njmp loc_1A20\nloc_1B78:\nmov ebx, 1\nloc_1B7D:\nadd ebx, 1\njmp loc_15B0\nloc_1B85:\nmov eax, [rsp+78h+var_58]\nmov ecx, [rsp+78h+var_54]\nadd [rsp+78h+var_4C], 1\nmov ebx, [rsp+78h+var_44]\nimul eax, ecx\nadd [rsp+78h+var_48], eax\ncmp [rsp+78h+var_4C], 1\njz loc_2560\nloc_1BA8:\nmov eax, [rsp+78h+var_4C]\nxor r15d, r15d\nmov [rsp+78h+var_50], ebx\nmov [rsp+78h+var_58], 0\nmov [rsp+78h+var_68], 1\nlea r14d, [rax-1]\nmov [rsp+78h+var_5C], r15d\nmov ebp, r14d\nloc_1BCF:\ncmp ebp, 1\njle loc_24DD\nloc_1BD8:\nlea r12d, [rbp-1]\nmov [rsp+78h+var_70], 0\nmov ebp, 1\nmov [rsp+78h+var_6C], 0\nmov r15d, r12d\nmov [rsp+78h+var_54], r12d\nloc_1BF9:\ncmp r15d, 1\njle loc_1FCF\nloc_1C03:\nlea eax, [r15-1]\nlea r12d, [r15-2]\nmov [rsp+78h+var_60], ebp\nxor r13d, r13d\nmov [rsp+78h+var_64], eax\nmov ebx, 1\nmov r15d, r12d\nmov ebp, eax\nmov [rsp+78h+var_74], 0\nloc_1C28:\ncmp ebp, 1\njle loc_1DA0\nmov edi, r15d\ncmp r15d, 1\njle loc_1CE0\nmov edx, r15d\nxor r14d, r14d\nlea r12d, [r15-1]\nxor ecx, ecx\nloc_1C4A:\nmov [rsp+78h+var_40], ecx\nmov [rsp+78h+var_44], edx\ncall sub_11F0\nmov ecx, [rsp+78h+var_40]\nmov edi, 1\nmov edx, [rsp+78h+var_44]\nadd r14d, eax\ntest r15d, r15d\ncmovle edi, r15d\nlea eax, [rcx+1]\ncmp eax, edi\njle loc_25FF\nnop dword ptr [rax+00000000h]\nloc_1C80:\ncmp ebp, eax\njle short loc_1CFC\nnop dword ptr [rax+00h]\nloc_1C88:\nmov edx, ebp\nsub ebp, 1\nsub edx, eax\nlea r15d, [rdx-1]\nloc_1C93:\nmov edi, ebp\nsub edi, r15d\ncall sub_11F0\ncmp r15d, 1\njle short loc_1CD0\nloc_1CA3:\nmov edi, r15d\nmov [rsp+78h+var_44], eax\nsub r15d, 1\ncall sub_11F0\nmov edx, [rsp+78h+var_44]\nmov edi, ebp\nsub edi, r15d\nimul edx, eax\nadd r14d, edx\ncall sub_11F0\ncmp r15d, 1\njg short loc_1CA3\nnop dword ptr [rax]\nloc_1CD0:\nadd r14d, eax\ntest r15d, r15d\njz short loc_1CFF\nxor r15d, r15d\njmp short loc_1C93\nloc_1CE0:\ntest r15d, r15d\njg loc_2020\nmov eax, 1\nmov r14d, 1\nlea r12d, [r15-1]\ncmp ebp, eax\njg short loc_1C88\nloc_1CFC:\nsub ebp, 1\nloc_1CFF:\nmov esi, ebx\nadd r13d, 1\nmov r15d, r12d\nimul esi, r14d\nadd [rsp+78h+var_74], esi\nloc_1D10:\ncmp r13d, 1\njz loc_26E7\nlea r14d, [r13-1]\nmov edi, r14d\ncmp r14d, 1\njz loc_2508\nmov r12d, r14d\nxor ebx, ebx\nxor edx, edx\nloc_1D32:\nmov [rsp+78h+var_44], edx\ncall sub_11F0\nmov edx, [rsp+78h+var_44]\nadd ebx, eax\ntest edx, edx\njz loc_25E4\nnop dword ptr [rax+00000000h]\nloc_1D50:\nlea r12d, [r13-3]\ncmp r13d, 2\njz loc_1C28\nloc_1D5E:\nmov edi, r14d\nsub edi, r12d\ncall sub_11F0\ncmp r12d, 1\njle short loc_1D90\nmov edi, r12d\nmov [rsp+78h+var_44], eax\nsub r12d, 1\ncall sub_11F0\nmov edx, [rsp+78h+var_44]\nimul eax, edx\nadd ebx, eax\njmp short loc_1D5E\nloc_1D90:\nadd ebx, eax\ntest r12d, r12d\njz loc_1C28\nxor r12d, r12d\njmp short loc_1D5E\nloc_1DA0:\nadd [rsp+78h+var_74], ebx\ntest ebp, ebp\njz short loc_1DC0\nadd r13d, 1\nsub r15d, 1\nxor ebp, ebp\njmp loc_1D10\nloc_1DC0:\nmov ebp, [rsp+78h+var_60]\nmov r14d, [rsp+78h+var_74]\nadd [rsp+78h+var_70], 1\nmov r15d, [rsp+78h+var_64]\nimul r14d, ebp\nadd [rsp+78h+var_6C], r14d\nloc_1DDC:\ncmp [rsp+78h+var_70], 1\njz loc_26FB\nmov eax, [rsp+78h+var_70]\nmov [rsp+78h+var_64], r15d\nxor r13d, r13d\nxor ebp, ebp\nmov ebx, 1\nlea r12d, [rax-1]\nlea esi, [rax-2]\nmov ecx, r12d\nmov r15d, esi\nloc_1E07:\ncmp ecx, 1\njle loc_1F90\nmov edi, r15d\ncmp r15d, 1\njle loc_1EB8\nlea eax, [r15-1]\nmov edx, r15d\nxor r14d, r14d\nxor r12d, r12d\nmov [rsp+78h+var_74], eax\nloc_1E2E:\nmov [rsp+78h+var_44], ecx\nmov [rsp+78h+var_60], edx\ncall sub_11F0\nmov edi, 1\nmov edx, [rsp+78h+var_60]\nmov ecx, [rsp+78h+var_44]\nadd r14d, eax\ntest r15d, r15d\nlea eax, [r12+1]\ncmovle edi, r15d\ncmp edi, eax\njge loc_25DC\nnop\nloc_1E60:\ncmp ecx, eax\njle short loc_1ED8\nnop dword ptr [rax+00h]\nloc_1E68:\nmov edx, ecx\nlea r12d, [rcx-1]\nsub edx, eax\nlea r15d, [rdx-1]\nloc_1E74:\nmov edi, r12d\nsub edi, r15d\ncall sub_11F0\ncmp r15d, 1\njle short loc_1EA8\nmov edi, r15d\nmov [rsp+78h+var_60], eax\nsub r15d, 1\ncall sub_11F0\nmov edx, [rsp+78h+var_60]\nimul edx, eax\nadd r14d, edx\njmp short loc_1E74\nloc_1EA8:\nadd r14d, eax\ntest r15d, r15d\njz short loc_1EDC\nxor r15d, r15d\njmp short loc_1E74\nloc_1EB8:\ntest r15d, r15d\njg loc_1FE8\nlea esi, [r15-1]\nmov eax, 1\nmov r14d, 1\nmov [rsp+78h+var_74], esi\ncmp ecx, eax\njg short loc_1E68\nloc_1ED8:\nlea r12d, [rcx-1]\nloc_1EDC:\nimul ebx, r14d\nmov r15d, [rsp+78h+var_74]\nadd r13d, 1\nmov ecx, r12d\nadd ebp, ebx\nloc_1EEE:\ncmp r13d, 1\njz loc_26F1\nlea r12d, [r13-1]\nmov edi, r12d\ncmp r12d, 1\njz loc_2528\nmov r14d, r12d\nxor edx, edx\nxor ebx, ebx\nloc_1F10:\nmov [rsp+78h+var_60], edx\nmov [rsp+78h+var_74], ecx\ncall sub_11F0\nmov edx, [rsp+78h+var_60]\nmov ecx, [rsp+78h+var_74]\nadd ebx, eax\ntest edx, edx\njz loc_25C1\nnop\nloc_1F30:\nlea r14d, [r13-3]\ncmp r13d, 2\njz loc_1E07\nmov [rsp+78h+var_74], ebp\nmov ebp, ebx\nmov ebx, r14d\nmov r14d, ecx\nloc_1F4A:\nmov edi, r12d\nsub edi, ebx\ncall sub_11F0\ncmp ebx, 1\njle short loc_1F80\nloc_1F59:\nmov edi, ebx\nmov [rsp+78h+var_60], eax\nsub ebx, 1\ncall sub_11F0\nmov edx, [rsp+78h+var_60]\nmov edi, r12d\nsub edi, ebx\nimul edx, eax\nadd ebp, edx\ncall sub_11F0\ncmp ebx, 1\njg short loc_1F59\nnop\nloc_1F80:\nadd ebp, eax\ntest ebx, ebx\njz short loc_1FA8\nxor ebx, ebx\njmp short loc_1F4A\nloc_1F90:\nadd ebp, ebx\ntest ecx, ecx\njz short loc_1FC0\nadd r13d, 1\nsub r15d, 1\nxor ecx, ecx\njmp loc_1EEE\nloc_1FA8:\nmov ebx, ebp\nmov ecx, r14d\nmov ebp, [rsp+78h+var_74]\njmp loc_1E07\nloc_1FC0:\nmov r15d, [rsp+78h+var_64]\ncmp r15d, 1\njg loc_1C03\nloc_1FCF:\nadd [rsp+78h+var_6C], ebp\ntest r15d, r15d\njz short loc_2050\nadd [rsp+78h+var_70], 1\nxor r15d, r15d\njmp loc_1DDC\nloc_1FE8:\nlea eax, [r15-1]\nmov r14d, 1\nmov [rsp+78h+var_74], eax\nmov edx, eax\nloc_1FF8:\nmov edi, edx\nmov r12d, 1\ncmp edx, 1\njg loc_1E2E\nadd r14d, 1\nmov eax, 2\njmp loc_1E60\nloc_2020:\nlea r12d, [r15-1]\nmov r14d, 1\nmov edx, r12d\nloc_202D:\nmov edi, edx\nmov ecx, 1\ncmp edx, 1\njg loc_1C4A\nadd r14d, 1\nmov eax, 2\njmp loc_1C80\nloc_2050:\nmov eax, [rsp+78h+var_68]\nmov ecx, [rsp+78h+var_6C]\nadd [rsp+78h+var_5C], 1\nmov r12d, [rsp+78h+var_54]\nimul eax, ecx\nadd [rsp+78h+var_58], eax\nmov ebp, r12d\nloc_206C:\ncmp [rsp+78h+var_5C], 1\njz loc_2695\nmov eax, [rsp+78h+var_5C]\nmov [rsp+78h+var_68], 0\nmov [rsp+78h+var_6C], 0\nmov [rsp+78h+var_74], 1\nlea r12d, [rax-1]\nmov [rsp+78h+var_60], ebp\nloc_209B:\ncmp r12d, 1\njle loc_244F\nloc_20A5:\nlea r15d, [r12-1]\nlea ebp, [r12-2]\nxor r13d, r13d\nmov ebx, 1\nmov [rsp+78h+var_70], 0\nmov r12d, ebp\nmov [rsp+78h+var_64], r15d\nloc_20C7:\ncmp r15d, 1\njle loc_2240\nmov edi, r12d\ncmp r12d, 1\njle loc_2178\nmov edx, r12d\nxor ecx, ecx\nlea ebp, [r12-1]\nxor r14d, r14d\nloc_20EB:\nmov [rsp+78h+var_44], ecx\nmov [rsp+78h+var_54], edx\ncall sub_11F0\nmov ecx, [rsp+78h+var_44]\nmov edi, 1\nmov edx, [rsp+78h+var_54]\nadd r14d, eax\ntest r12d, r12d\ncmovle edi, r12d\nlea eax, [rcx+1]\ncmp edi, eax\njge loc_25B9\nnop word ptr [rax+rax+00h]\nloc_2120:\ncmp r15d, eax\njle short loc_2196\nnop dword ptr [rax]\nloc_2128:\nmov edx, r15d\nsub r15d, 1\nsub edx, eax\nlea r12d, [rdx-1]\nloc_2135:\nmov edi, r15d\nsub edi, r12d\ncall sub_11F0\ncmp r12d, 1\njle short loc_2168\nmov edi, r12d\nmov [rsp+78h+var_54], eax\nsub r12d, 1\ncall sub_11F0\nmov edx, [rsp+78h+var_54]\nimul edx, eax\nadd r14d, edx\njmp short loc_2135\nloc_2168:\nadd r14d, eax\ntest r12d, r12d\njz short loc_219A\nxor r12d, r12d\njmp short loc_2135\nloc_2178:\ntest r12d, r12d\njg loc_2470\nmov eax, 1\nmov r14d, 1\nlea ebp, [r12-1]\ncmp r15d, eax\njg short loc_2128\nloc_2196:\nsub r15d, 1\nloc_219A:\nmov esi, ebx\nadd r13d, 1\nmov r12d, ebp\nimul esi, r14d\nadd [rsp+78h+var_70], esi\nloc_21AB:\ncmp r13d, 1\njz loc_271C\nlea r14d, [r13-1]\nmov edi, r14d\ncmp r14d, 1\njz loc_24F8\nmov ebp, r14d\nxor ebx, ebx\nxor edx, edx\nloc_21CD:\nmov [rsp+78h+var_54], edx\ncall sub_11F0\nmov edx, [rsp+78h+var_54]\nadd ebx, eax\ntest edx, edx\njz loc_25A1\nnop dword ptr [rax+00h]\nloc_21E8:\nlea ebp, [r13-3]\ncmp r13d, 2\njz loc_20C7\nloc_21F6:\nmov edi, r14d\nsub edi, ebp\ncall sub_11F0\ncmp ebp, 1\njle short loc_2230\nloc_2205:\nmov edi, ebp\nmov [rsp+78h+var_54], eax\nsub ebp, 1\ncall sub_11F0\nmov edx, [rsp+78h+var_54]\nmov edi, r14d\nsub edi, ebp\nimul edx, eax\nadd ebx, edx\ncall sub_11F0\ncmp ebp, 1\njg short loc_2205\nnop dword ptr [rax+rax+00h]\nloc_2230:\nadd ebx, eax\ntest ebp, ebp\njz loc_20C7\nxor ebp, ebp\njmp short loc_21F6\nloc_2240:\nadd [rsp+78h+var_70], ebx\ntest r15d, r15d\njz short loc_2260\nadd r13d, 1\nsub r12d, 1\nxor r15d, r15d\njmp loc_21AB\nloc_2260:\nmov r14d, [rsp+78h+var_74]\nmov eax, [rsp+78h+var_70]\nadd [rsp+78h+var_6C], 1\nmov r15d, [rsp+78h+var_64]\nimul r14d, eax\nadd [rsp+78h+var_68], r14d\nmov r12d, r15d\nloc_227F:\ncmp [rsp+78h+var_6C], 1\njz loc_270F\nmov eax, [rsp+78h+var_6C]\nmov [rsp+78h+var_70], r12d\nxor r13d, r13d\nmov ebx, 1\nmov [rsp+78h+var_74], 0\nlea ebp, [rax-1]\nlea r15d, [rax-2]\nmov r14d, r15d\nmov r12d, ebp\nloc_22B0:\ncmp r12d, 1\njle loc_2420\nmov edi, r14d\ncmp r14d, 1\njle loc_2358\nmov edx, r14d\nxor ebp, ebp\nlea r15d, [r14-1]\nxor ecx, ecx\nloc_22D2:\nmov [rsp+78h+var_54], ecx\nmov [rsp+78h+var_64], edx\ncall sub_11F0\nmov ecx, [rsp+78h+var_54]\nmov edi, 1\nmov edx, [rsp+78h+var_64]\nadd ebp, eax\ntest r14d, r14d\ncmovle edi, r14d\nlea eax, [rcx+1]\ncmp edi, eax\njge loc_2599\nloc_2300:\ncmp r12d, eax\njle short loc_2374\nnop dword ptr [rax]\nloc_2308:\nmov edx, r12d\nsub r12d, 1\nsub edx, eax\nlea r14d, [rdx-1]\nloc_2315:\nmov edi, r12d\nsub edi, r14d\ncall sub_11F0\ncmp r14d, 1\njle short loc_2348\nmov edi, r14d\nmov [rsp+78h+var_64], eax\nsub r14d, 1\ncall sub_11F0\nmov edx, [rsp+78h+var_64]\nimul edx, eax\nadd ebp, edx\njmp short loc_2315\nloc_2348:\nadd ebp, eax\ntest r14d, r14d\njz short loc_2378\nxor r14d, r14d\njmp short loc_2315\nloc_2358:\ntest r14d, r14d\njg loc_24A0\nmov eax, 1\nmov ebp, 1\nlea r15d, [r14-1]\ncmp r12d, eax\njg short loc_2308\nloc_2374:\nsub r12d, 1\nloc_2378:\nmov esi, ebx\nadd r13d, 1\nmov r14d, r15d\nimul esi, ebp\nadd [rsp+78h+var_74], esi\nloc_2388:\ncmp r13d, 1\njz loc_2705\nlea ebp, [r13-1]\nmov edi, ebp\ncmp ebp, 1\njz loc_2518\nmov r15d, ebp\nxor edx, edx\nxor ebx, ebx\nloc_23A8:\nmov [rsp+78h+var_64], edx\ncall sub_11F0\nmov edx, [rsp+78h+var_64]\nadd ebx, eax\ntest edx, edx\njz loc_2582\nnop\nloc_23C0:\nlea r15d, [r13-3]\ncmp r13d, 2\njz loc_22B0\nloc_23CE:\nmov edi, ebp\nsub edi, r15d\ncall sub_11F0\ncmp r15d, 1\njle short loc_2410\nloc_23DE:\nmov edi, r15d\nmov [rsp+78h+var_64], eax\nsub r15d, 1\ncall sub_11F0\nmov edx, [rsp+78h+var_64]\nmov edi, ebp\nsub edi, r15d\nimul edx, eax\nadd ebx, edx\ncall sub_11F0\ncmp r15d, 1\njg short loc_23DE\nnop word ptr [rax+rax+00000000h]\nloc_2410:\nadd ebx, eax\ntest r15d, r15d\njz loc_22B0\nxor r15d, r15d\njmp short loc_23CE\nloc_2420:\nadd [rsp+78h+var_74], ebx\ntest r12d, r12d\njz short loc_2440\nadd r13d, 1\nsub r14d, 1\nxor r12d, r12d\njmp loc_2388\nloc_2440:\nmov r12d, [rsp+78h+var_70]\ncmp r12d, 1\njg loc_20A5\nloc_244F:\nmov ecx, [rsp+78h+var_74]\nadd [rsp+78h+var_68], ecx\ntest r12d, r12d\njz short loc_24D0\nadd [rsp+78h+var_6C], 1\nxor r12d, r12d\njmp loc_227F\nloc_2470:\nlea ebp, [r12-1]\nmov r14d, 1\nmov edx, ebp\nloc_247D:\nmov edi, edx\nmov ecx, 1\ncmp edx, 1\njg loc_20EB\nadd r14d, 1\nmov eax, 2\njmp loc_2120\nloc_24A0:\nlea r15d, [r14-1]\nmov ebp, 1\nmov edx, r15d\nloc_24AC:\nmov edi, edx\nmov ecx, 1\ncmp edx, 1\njg loc_22D2\nadd ebp, 1\nmov eax, 2\njmp loc_2300\nloc_24D0:\nmov ebp, [rsp+78h+var_60]\ncmp ebp, 1\njg loc_1BD8\nloc_24DD:\nmov ecx, [rsp+78h+var_68]\nadd [rsp+78h+var_58], ecx\ntest ebp, ebp\njz short loc_2535\nadd [rsp+78h+var_5C], 1\nxor ebp, ebp\njmp loc_206C\nloc_24F8:\nmov ebx, 1\nloc_24FD:\nadd ebx, 1\njmp loc_21E8\nloc_2508:\nmov ebx, 1\nloc_250D:\nadd ebx, 1\njmp loc_1D50\nloc_2518:\nmov ebx, 1\nloc_251D:\nadd ebx, 1\njmp loc_23C0\nloc_2528:\nmov ebx, 1\nloc_252D:\nadd ebx, 1\njmp loc_1F30\nloc_2535:\nmov ebx, [rsp+78h+var_50]\ncmp ebx, 1\njg loc_1228\nloc_2542:\nmov ecx, [rsp+78h+var_58]\nadd [rsp+78h+var_48], ecx\ntest ebx, ebx\njz short loc_256D\nadd [rsp+78h+var_4C], 1\nxor ebx, ebx\ncmp [rsp+78h+var_4C], 1\njnz loc_1BA8\nloc_2560:\nmov [rsp+78h+var_58], 1\njmp loc_121F\nloc_256D:\nmov ebp, [rsp+78h+var_48]\nloc_2571:\nadd rsp, 48h\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_2582:\nsub r15d, 1\ncmp r15d, 1\njbe short loc_251D\nmov edi, r15d\nmov edx, 1\njmp loc_23A8\nloc_2599:\nsub edx, 1\njmp loc_24AC\nloc_25A1:\nsub ebp, 1\ncmp ebp, 1\njbe loc_24FD\nmov edi, ebp\nmov edx, 1\njmp loc_21CD\nloc_25B9:\nsub edx, 1\njmp loc_247D\nloc_25C1:\nsub r14d, 1\ncmp r14d, 1\njbe loc_252D\nmov edi, r14d\nmov edx, 1\njmp loc_1F10\nloc_25DC:\nsub edx, 1\njmp loc_1FF8\nloc_25E4:\nsub r12d, 1\ncmp r12d, 1\njbe loc_250D\nmov edi, r12d\nmov edx, 1\njmp loc_1D32\nloc_25FF:\nsub edx, 1\njmp loc_202D\nloc_2607:\nsub edx, 1\ncmp edx, 1\njbe loc_1B6D\nmov edi, edx\nmov r15d, 1\njmp loc_1A04\nloc_2620:\nsub r8d, 1\njmp loc_1AF5\nloc_2629:\nsub ebp, 1\ncmp ebp, 1\njbe loc_1B4D\nmov edi, ebp\nmov edx, 1\njmp loc_181D\nloc_2641:\nsub edx, 1\njmp loc_1AC4\nloc_2649:\nsub edx, 1\ncmp edx, 1\njbe loc_1B7D\nmov edi, edx\nmov r15d, 1\njmp loc_1594\nloc_2662:\nsub r8d, 1\njmp loc_1655\nloc_266B:\nsub ebp, 1\ncmp ebp, 1\njbe loc_1B5D\nmov edi, ebp\nmov edx, 1\njmp loc_13A5\nloc_2683:\nsub edx, 1\njmp loc_1684\nloc_268B:\nmov ebx, 1\njmp loc_1489\nloc_2695:\nmov [rsp+78h+var_68], 1\njmp loc_1BCF\nloc_26A2:\nmov [rsp+78h+var_74], 1\njmp loc_1278\nloc_26AF:\nmov ebx, 1\njmp loc_18F9\nloc_26B9:\nmov [rsp+78h+var_74], 1\njmp loc_16F4\nloc_26C6:\nmov ebx, 1\njmp loc_171D\nloc_26D0:\nmov [rsp+78h+var_68], 1\njmp loc_124A\nloc_26DD:\nmov ebx, 1\njmp loc_12A1\nloc_26E7:\nmov ebx, 1\njmp loc_1C28\nloc_26F1:\nmov ebx, 1\njmp loc_1E07\nloc_26FB:\nmov ebp, 1\njmp loc_1BF9\nloc_2705:\nmov ebx, 1\njmp loc_22B0\nloc_270F:\nmov [rsp+78h+var_74], 1\njmp loc_209B\nloc_271C:\nmov ebx, 1\njmp loc_20C7", + "ida_strip_pseudo": "__int64 __fastcall sub_11F0(int a1)\n{\n unsigned int v1; // ebp\n int v2; // ebx\n int v3; // r12d\n int v4; // ebp\n int v5; // r12d\n int v6; // ebx\n int v7; // r14d\n int v8; // r15d\n __int64 v9; // rdi\n int j; // edx\n int v11; // ecx\n int v12; // ebp\n int v13; // r13d\n int v14; // eax\n int v15; // edx\n int i; // r15d\n int v17; // eax\n __int64 v18; // rdi\n int v19; // r13d\n __int64 v20; // rdi\n unsigned int v21; // ebp\n int k; // edx\n int v23; // ebp\n int m; // eax\n __int64 v25; // rdi\n int v26; // r13d\n int v27; // ebx\n int v28; // r14d\n int v29; // ebp\n __int64 v30; // rdi\n int n; // r8d\n int v32; // r15d\n int v33; // r12d\n int v34; // edx\n int v35; // eax\n int v36; // edx\n int ii; // ebp\n int jj; // eax\n __int64 v39; // rdi\n __int64 v40; // rdi\n unsigned int v41; // edx\n int v42; // r15d\n int v43; // r15d\n int v44; // eax\n __int64 v45; // rdi\n int v46; // ebp\n int v47; // r12d\n int v48; // ebx\n int v49; // r14d\n int v50; // r15d\n __int64 v51; // rdi\n int kk; // edx\n int v53; // r13d\n int v54; // ebp\n int v55; // ecx\n int v56; // eax\n int v57; // edx\n int mm; // r14d\n int v59; // eax\n __int64 v60; // rdi\n int v61; // r13d\n __int64 v62; // rdi\n unsigned int v63; // ebp\n int nn; // edx\n int v65; // ebp\n int i1; // eax\n __int64 v67; // rdi\n int v68; // r13d\n int v69; // ebx\n int v70; // r14d\n int v71; // ebp\n __int64 v72; // rdi\n int i2; // r8d\n int v74; // r15d\n int v75; // r12d\n int v76; // edx\n int v77; // eax\n int v78; // edx\n int i3; // ebp\n int i4; // eax\n __int64 v81; // rdi\n __int64 v82; // rdi\n unsigned int v83; // edx\n int i5; // r15d\n int v85; // r15d\n int v86; // eax\n __int64 v87; // rdi\n int v88; // ebp\n int v89; // r12d\n int v90; // ebp\n int v91; // r15d\n int v92; // r13d\n int v93; // ebx\n int v94; // r15d\n int v95; // ebp\n __int64 v96; // rdi\n int i6; // edx\n int v98; // r14d\n int v99; // r12d\n int v100; // ecx\n int v101; // eax\n int v102; // edx\n int i7; // r15d\n int i8; // eax\n __int64 v105; // rdi\n __int64 v106; // rdi\n unsigned int v107; // r12d\n int i9; // edx\n int v109; // r12d\n int v110; // eax\n __int64 v111; // rdi\n int v112; // r13d\n int v113; // ebx\n int v114; // ecx\n int v115; // r15d\n __int64 v116; // rdi\n int i10; // edx\n int v118; // r14d\n int v119; // r12d\n int v120; // eax\n int v121; // eax\n int v122; // r12d\n int i11; // r15d\n int v124; // eax\n __int64 v125; // rdi\n int v126; // r12d\n __int64 v127; // rdi\n unsigned int v128; // r14d\n int v129; // edx\n int v130; // eax\n int v131; // ebp\n int v132; // ebx\n int v133; // r14d\n int i12; // eax\n __int64 v135; // rdi\n int v136; // r12d\n int v137; // r15d\n int v138; // r13d\n int v139; // ebx\n int v140; // r12d\n __int64 v141; // rdi\n int i13; // edx\n int v143; // ecx\n int v144; // ebp\n int v145; // r14d\n int v146; // eax\n int v147; // edx\n int i14; // r12d\n int v149; // eax\n __int64 v150; // rdi\n int v151; // r14d\n __int64 v152; // rdi\n unsigned int v153; // ebp\n int i15; // edx\n int v155; // ebp\n int i16; // eax\n __int64 v157; // rdi\n int v158; // r13d\n int v159; // ebx\n int v160; // r14d\n int v161; // r12d\n __int64 v162; // rdi\n int i17; // edx\n int v164; // ebp\n int v165; // r15d\n int v166; // ecx\n int v167; // eax\n int v168; // edx\n int i18; // r14d\n int v170; // eax\n __int64 v171; // rdi\n int v172; // ebp\n __int64 v173; // rdi\n unsigned int v174; // r15d\n int v175; // edx\n int v176; // r15d\n int i19; // eax\n __int64 v178; // rdi\n int v180; // [rsp+4h] [rbp-74h]\n int v181; // [rsp+4h] [rbp-74h]\n int v182; // [rsp+4h] [rbp-74h]\n int v183; // [rsp+4h] [rbp-74h]\n int v184; // [rsp+4h] [rbp-74h]\n int v185; // [rsp+4h] [rbp-74h]\n int v186; // [rsp+4h] [rbp-74h]\n int v187; // [rsp+8h] [rbp-70h]\n int v188; // [rsp+8h] [rbp-70h]\n int v189; // [rsp+8h] [rbp-70h]\n int v190; // [rsp+8h] [rbp-70h]\n int v191; // [rsp+8h] [rbp-70h]\n int v192; // [rsp+8h] [rbp-70h]\n int v193; // [rsp+8h] [rbp-70h]\n int v194; // [rsp+Ch] [rbp-6Ch]\n int v195; // [rsp+Ch] [rbp-6Ch]\n int v196; // [rsp+Ch] [rbp-6Ch]\n int v197; // [rsp+Ch] [rbp-6Ch]\n int v198; // [rsp+10h] [rbp-68h]\n int v199; // [rsp+10h] [rbp-68h]\n int v200; // [rsp+14h] [rbp-64h]\n int v201; // [rsp+14h] [rbp-64h]\n int v202; // [rsp+14h] [rbp-64h]\n unsigned int v203; // [rsp+14h] [rbp-64h]\n int v204; // [rsp+14h] [rbp-64h]\n int v205; // [rsp+14h] [rbp-64h]\n int v206; // [rsp+14h] [rbp-64h]\n int v207; // [rsp+14h] [rbp-64h]\n int v208; // [rsp+14h] [rbp-64h]\n int v209; // [rsp+18h] [rbp-60h]\n int v210; // [rsp+18h] [rbp-60h]\n unsigned int v211; // [rsp+18h] [rbp-60h]\n int v212; // [rsp+18h] [rbp-60h]\n int v213; // [rsp+18h] [rbp-60h]\n int v214; // [rsp+18h] [rbp-60h]\n int v215; // [rsp+18h] [rbp-60h]\n int v216; // [rsp+18h] [rbp-60h]\n int v217; // [rsp+1Ch] [rbp-5Ch]\n int v218; // [rsp+1Ch] [rbp-5Ch]\n int v219; // [rsp+20h] [rbp-58h]\n int v220; // [rsp+24h] [rbp-54h]\n int v221; // [rsp+24h] [rbp-54h]\n int v222; // [rsp+24h] [rbp-54h]\n int v223; // [rsp+24h] [rbp-54h]\n int v224; // [rsp+24h] [rbp-54h]\n int v225; // [rsp+28h] [rbp-50h]\n int v226; // [rsp+28h] [rbp-50h]\n int v227; // [rsp+28h] [rbp-50h]\n int v228; // [rsp+28h] [rbp-50h]\n int v229; // [rsp+28h] [rbp-50h]\n int v230; // [rsp+2Ch] [rbp-4Ch]\n unsigned int v231; // [rsp+30h] [rbp-48h]\n int v232; // [rsp+34h] [rbp-44h]\n int v233; // [rsp+34h] [rbp-44h]\n int v234; // [rsp+34h] [rbp-44h]\n int v235; // [rsp+34h] [rbp-44h]\n int v236; // [rsp+34h] [rbp-44h]\n int v237; // [rsp+38h] [rbp-40h]\n int v238; // [rsp+38h] [rbp-40h]\n int v239; // [rsp+38h] [rbp-40h]\n int v240; // [rsp+38h] [rbp-40h]\n int v241; // [rsp+38h] [rbp-40h]\n int v242; // [rsp+3Ch] [rbp-3Ch]\n\n v1 = 0;\n if ( a1 <= 0 )\n return v1;\n v219 = 1;\n v2 = a1 - 1;\n v230 = 0;\n v231 = 0;\nLABEL_3:\n if ( v2 <= 1 )\n goto LABEL_298;\n do\n {\n v217 = 0;\n v220 = 0;\n v3 = v2 - 1;\n v198 = 1;\n v232 = v2 - 1;\nLABEL_5:\n if ( v3 <= 1 )\n goto LABEL_139;\n do\n {\n v194 = 0;\n v180 = 1;\n v4 = v3 - 1;\n v200 = 0;\n v225 = v3 - 1;\nLABEL_7:\n if ( v4 <= 1 )\n goto LABEL_63;\n do\n {\n v5 = 0;\n v6 = 1;\n v209 = v4 - 1;\n v7 = v4 - 1;\n v8 = v4 - 2;\n v187 = 0;\n while ( v7 > 1 )\n {\n v9 = (unsigned int)v8;\n if ( v8 > 1 )\n {\n j = v8;\n v11 = 0;\n v12 = v8 - 1;\n v13 = 0;\n goto LABEL_12;\n }\n if ( v8 <= 0 )\n {\n v14 = 1;\n v13 = 1;\n v12 = v8 - 1;\nLABEL_14:\n v15 = v7--;\n for ( i = v15 - v14 - 1; ; i = 0 )\n {\n while ( 1 )\n {\n v17 = sub_11F0((unsigned int)(v7 - i));\n if ( i <= 1 )\n break;\n v18 = (unsigned int)i--;\n v13 += sub_11F0(v18) * v17;\n }\n v13 += v17;\n if ( !i )\n break;\n }\n goto LABEL_22;\n }\n v12 = v8 - 1;\n v13 = 1;\n for ( j = v8 - 1; ; j = v237 - 1 )\n {\n v9 = (unsigned int)j;\n v11 = 1;\n if ( j <= 1 )\n break;\nLABEL_12:\n v242 = v11;\n v237 = j;\n v13 += sub_11F0(v9);\n v14 = v242 + 1;\n if ( v242 + 1 > 1 )\n goto LABEL_13;\n }\n ++v13;\n v14 = 2;\nLABEL_13:\n if ( v7 > v14 )\n goto LABEL_14;\n --v7;\nLABEL_22:\n ++v5;\n v8 = v12;\n v187 += v6 * v13;\nLABEL_23:\n if ( v5 == 1 )\n {\n v6 = 1;\n }\n else\n {\n v19 = v5 - 1;\n v20 = (unsigned int)(v5 - 1);\n if ( v5 == 2 )\n {\n v6 = 1;\nLABEL_144:\n ++v6;\n }\n else\n {\n v21 = v5 - 1;\n v6 = 0;\n for ( k = 0; ; k = 1 )\n {\n v238 = k;\n v6 += sub_11F0(v20);\n if ( v238 )\n break;\n if ( --v21 <= 1 )\n goto LABEL_144;\n v20 = v21;\n }\n }\n v23 = v5 - 3;\n if ( v5 != 2 )\n {\n while ( 1 )\n {\n for ( m = sub_11F0((unsigned int)(v19 - v23)); v23 > 1; m = sub_11F0((unsigned int)(v19 - v23)) )\n {\n v25 = (unsigned int)v23--;\n v6 += sub_11F0(v25) * m;\n }\n v6 += m;\n if ( !v23 )\n break;\n v23 = 0;\n }\n }\n }\n }\n v187 += v6;\n if ( v7 )\n {\n ++v5;\n --v8;\n v7 = 0;\n goto LABEL_23;\n }\n ++v194;\n v4 = v209;\n v200 += v187 * v180;\nLABEL_35:\n if ( v194 == 1 )\n {\n v180 = 1;\n goto LABEL_7;\n }\n v188 = v4;\n v26 = 0;\n v27 = 1;\n v180 = 0;\n v28 = v194 - 1;\n v29 = v194 - 2;\n while ( 2 )\n {\n if ( v28 > 1 )\n {\n v30 = (unsigned int)v29;\n if ( v29 > 1 )\n {\n n = v29;\n v32 = 0;\n v33 = v29 - 1;\n v34 = 0;\n goto LABEL_40;\n }\n if ( v29 <= 0 )\n {\n v35 = 1;\n v32 = 1;\n v33 = v29 - 1;\n goto LABEL_42;\n }\n v33 = v29 - 1;\n v32 = 1;\n for ( n = v29 - 1; ; n = v210 - 1 )\n {\n v30 = (unsigned int)n;\n v34 = 1;\n if ( n <= 1 )\n break;\nLABEL_40:\n v239 = v34;\n v210 = n;\n v32 += sub_11F0(v30);\n v35 = v239 + 1;\n if ( v239 + 1 > 1 )\n goto LABEL_41;\n }\n ++v32;\n v35 = 2;\nLABEL_41:\n if ( v28 <= v35 )\n {\n --v28;\n }\n else\n {\nLABEL_42:\n v36 = v28--;\n for ( ii = v36 - v35 - 1; ; ii = 0 )\n {\n for ( jj = sub_11F0((unsigned int)(v28 - ii)); ii > 1; jj = sub_11F0((unsigned int)(v28 - ii)) )\n {\n v39 = (unsigned int)ii--;\n v32 += sub_11F0(v39) * jj;\n }\n v32 += jj;\n if ( !ii )\n break;\n }\n }\n ++v26;\n v29 = v33;\n v180 += v32 * v27;\nLABEL_51:\n if ( v26 == 1 )\n {\n v27 = 1;\n }\n else\n {\n v40 = (unsigned int)(v26 - 1);\n if ( v26 == 2 )\n {\n v27 = 1;\nLABEL_148:\n ++v27;\n }\n else\n {\n v41 = v26 - 1;\n v42 = 0;\n v27 = 0;\n while ( 1 )\n {\n v211 = v41;\n v27 += sub_11F0(v40);\n if ( v42 )\n break;\n v41 = v211 - 1;\n if ( v211 - 1 <= 1 )\n goto LABEL_148;\n v40 = v41;\n v42 = 1;\n }\n }\n v43 = v26 - 3;\n if ( v26 != 2 )\n {\n while ( 1 )\n {\n while ( 1 )\n {\n v44 = sub_11F0((unsigned int)(v26 - 1 - v43));\n if ( v43 <= 1 )\n break;\n v45 = (unsigned int)v43--;\n v27 += v44 * sub_11F0(v45);\n }\n v27 += v44;\n if ( !v43 )\n break;\n v43 = 0;\n }\n }\n }\n continue;\n }\n break;\n }\n v180 += v27;\n if ( v28 )\n {\n ++v26;\n --v29;\n v28 = 0;\n goto LABEL_51;\n }\n v4 = v188;\n }\n while ( v188 > 1 );\nLABEL_63:\n v200 += v180;\n if ( v4 )\n {\n ++v194;\n v4 = 0;\n goto LABEL_35;\n }\n ++v217;\n v3 = v225;\n v220 += v200 * v198;\nLABEL_72:\n if ( v217 == 1 )\n {\n v198 = 1;\n goto LABEL_5;\n }\n v198 = 0;\n v195 = 0;\n v181 = 1;\n v212 = v3;\n v46 = v217 - 1;\n while ( 2 )\n {\n if ( v46 <= 1 )\n goto LABEL_130;\nLABEL_75:\n v47 = 0;\n v48 = 1;\n v201 = v46 - 1;\n v49 = v46 - 2;\n v50 = v46 - 1;\n v189 = 0;\n while ( 2 )\n {\n if ( v50 > 1 )\n {\n v51 = (unsigned int)v49;\n if ( v49 > 1 )\n {\n kk = v49;\n v53 = 0;\n v54 = v49 - 1;\n v55 = 0;\n goto LABEL_79;\n }\n if ( v49 <= 0 )\n {\n v56 = 1;\n v53 = 1;\n v54 = v49 - 1;\n goto LABEL_81;\n }\n v54 = v49 - 1;\n v53 = 1;\n for ( kk = v49 - 1; ; kk = v226 - 1 )\n {\n v51 = (unsigned int)kk;\n v55 = 1;\n if ( kk <= 1 )\n break;\nLABEL_79:\n v240 = v55;\n v226 = kk;\n v53 += sub_11F0(v51);\n v56 = v240 + 1;\n if ( v240 + 1 > 1 )\n goto LABEL_80;\n }\n ++v53;\n v56 = 2;\nLABEL_80:\n if ( v50 <= v56 )\n {\n --v50;\n }\n else\n {\nLABEL_81:\n v57 = v50--;\n for ( mm = v57 - v56 - 1; ; mm = 0 )\n {\n while ( 1 )\n {\n v59 = sub_11F0((unsigned int)(v50 - mm));\n if ( mm <= 1 )\n break;\n v60 = (unsigned int)mm--;\n v53 += sub_11F0(v60) * v59;\n }\n v53 += v59;\n if ( !mm )\n break;\n }\n }\n ++v47;\n v49 = v54;\n v189 += v53 * v48;\nLABEL_90:\n if ( v47 == 1 )\n {\n v48 = 1;\n }\n else\n {\n v61 = v47 - 1;\n v62 = (unsigned int)(v47 - 1);\n if ( v47 == 2 )\n {\n v48 = 1;\nLABEL_142:\n ++v48;\n }\n else\n {\n v63 = v47 - 1;\n v48 = 0;\n for ( nn = 0; ; nn = 1 )\n {\n v227 = nn;\n v48 += sub_11F0(v62);\n if ( v227 )\n break;\n if ( --v63 <= 1 )\n goto LABEL_142;\n v62 = v63;\n }\n }\n v65 = v47 - 3;\n if ( v47 != 2 )\n {\n while ( 1 )\n {\n for ( i1 = sub_11F0((unsigned int)(v61 - v65)); v65 > 1; i1 = sub_11F0((unsigned int)(v61 - v65)) )\n {\n v67 = (unsigned int)v65--;\n v48 += sub_11F0(v67) * i1;\n }\n v48 += i1;\n if ( !v65 )\n break;\n v65 = 0;\n }\n }\n }\n continue;\n }\n break;\n }\n v189 += v48;\n if ( v50 )\n {\n ++v47;\n --v49;\n v50 = 0;\n goto LABEL_90;\n }\n ++v195;\n v46 = v201;\n v198 += v189 * v181;\nLABEL_102:\n if ( v195 == 1 )\n {\n v181 = 1;\n continue;\n }\n break;\n }\n v190 = v46;\n v68 = 0;\n v69 = 1;\n v181 = 0;\n v70 = v195 - 1;\n v71 = v195 - 2;\n while ( 2 )\n {\n if ( v70 > 1 )\n {\n v72 = (unsigned int)v71;\n if ( v71 > 1 )\n {\n i2 = v71;\n v74 = 0;\n v75 = v71 - 1;\n v76 = 0;\n goto LABEL_107;\n }\n if ( v71 <= 0 )\n {\n v77 = 1;\n v74 = 1;\n v75 = v71 - 1;\n goto LABEL_109;\n }\n v75 = v71 - 1;\n v74 = 1;\n for ( i2 = v71 - 1; ; i2 = v202 - 1 )\n {\n v72 = (unsigned int)i2;\n v76 = 1;\n if ( i2 <= 1 )\n break;\nLABEL_107:\n v228 = v76;\n v202 = i2;\n v74 += sub_11F0(v72);\n v77 = v228 + 1;\n if ( v228 + 1 > 1 )\n goto LABEL_108;\n }\n ++v74;\n v77 = 2;\nLABEL_108:\n if ( v70 <= v77 )\n {\n --v70;\n }\n else\n {\nLABEL_109:\n v78 = v70--;\n for ( i3 = v78 - v77 - 1; ; i3 = 0 )\n {\n for ( i4 = sub_11F0((unsigned int)(v70 - i3)); i3 > 1; i4 = sub_11F0((unsigned int)(v70 - i3)) )\n {\n v81 = (unsigned int)i3--;\n v74 += sub_11F0(v81) * i4;\n }\n v74 += i4;\n if ( !i3 )\n break;\n }\n }\n ++v68;\n v71 = v75;\n v181 += v74 * v69;\nLABEL_118:\n if ( v68 == 1 )\n {\n v69 = 1;\n }\n else\n {\n v82 = (unsigned int)(v68 - 1);\n if ( v68 == 2 )\n {\n v69 = 1;\nLABEL_146:\n ++v69;\n }\n else\n {\n v83 = v68 - 1;\n v69 = 0;\n for ( i5 = 0; ; i5 = 1 )\n {\n v203 = v83;\n v69 += sub_11F0(v82);\n if ( i5 )\n break;\n v83 = v203 - 1;\n if ( v203 - 1 <= 1 )\n goto LABEL_146;\n v82 = v83;\n }\n }\n v85 = v68 - 3;\n if ( v68 != 2 )\n {\n while ( 1 )\n {\n while ( 1 )\n {\n v86 = sub_11F0((unsigned int)(v68 - 1 - v85));\n if ( v85 <= 1 )\n break;\n v87 = (unsigned int)v85--;\n v69 += v86 * sub_11F0(v87);\n }\n v69 += v86;\n if ( !v85 )\n break;\n v85 = 0;\n }\n }\n }\n continue;\n }\n break;\n }\n v181 += v69;\n if ( v70 )\n {\n ++v68;\n --v71;\n v70 = 0;\n goto LABEL_118;\n }\n v46 = v190;\n if ( v190 > 1 )\n goto LABEL_75;\nLABEL_130:\n v198 += v181;\n if ( v46 )\n {\n ++v195;\n v46 = 0;\n goto LABEL_102;\n }\n v3 = v212;\n }\n while ( v212 > 1 );\nLABEL_139:\n v220 += v198;\n if ( v3 )\n {\n ++v217;\n v3 = 0;\n goto LABEL_72;\n }\n ++v230;\n v2 = v232;\n v231 += v220 * v219;\n if ( v230 == 1 )\n {\nLABEL_300:\n v219 = 1;\n goto LABEL_3;\n }\nLABEL_150:\n v229 = v2;\n v219 = 0;\n v199 = 1;\n v218 = 0;\n v88 = v230 - 1;\n while ( 2 )\n {\n if ( v88 <= 1 )\n goto LABEL_287;\nLABEL_152:\n v89 = v88 - 1;\n v191 = 0;\n v90 = 1;\n v196 = 0;\n v91 = v89;\n v221 = v89;\n while ( 2 )\n {\n if ( v91 <= 1 )\n goto LABEL_211;\nLABEL_154:\n v213 = v90;\n v92 = 0;\n v204 = v91 - 1;\n v93 = 1;\n v94 = v91 - 2;\n v95 = v204;\n v182 = 0;\n while ( 2 )\n {\n if ( v95 > 1 )\n {\n v96 = (unsigned int)v94;\n if ( v94 > 1 )\n {\n i6 = v94;\n v98 = 0;\n v99 = v94 - 1;\n v100 = 0;\n goto LABEL_158;\n }\n if ( v94 <= 0 )\n {\n v101 = 1;\n v98 = 1;\n v99 = v94 - 1;\n goto LABEL_160;\n }\n v99 = v94 - 1;\n v98 = 1;\n for ( i6 = v94 - 1; ; i6 = v233 - 1 )\n {\n v96 = (unsigned int)i6;\n v100 = 1;\n if ( i6 <= 1 )\n break;\nLABEL_158:\n v241 = v100;\n v233 = i6;\n v98 += sub_11F0(v96);\n v101 = v241 + 1;\n if ( v241 + 1 > 1 )\n goto LABEL_159;\n }\n ++v98;\n v101 = 2;\nLABEL_159:\n if ( v95 <= v101 )\n {\n --v95;\n }\n else\n {\nLABEL_160:\n v102 = v95--;\n for ( i7 = v102 - v101 - 1; ; i7 = 0 )\n {\n for ( i8 = sub_11F0((unsigned int)(v95 - i7)); i7 > 1; i8 = sub_11F0((unsigned int)(v95 - i7)) )\n {\n v105 = (unsigned int)i7--;\n v98 += sub_11F0(v105) * i8;\n }\n v98 += i8;\n if ( !i7 )\n break;\n }\n }\n ++v92;\n v94 = v99;\n v182 += v98 * v93;\nLABEL_169:\n if ( v92 == 1 )\n {\n v93 = 1;\n }\n else\n {\n v106 = (unsigned int)(v92 - 1);\n if ( v92 == 2 )\n {\n v93 = 1;\nLABEL_292:\n ++v93;\n }\n else\n {\n v107 = v92 - 1;\n v93 = 0;\n for ( i9 = 0; ; i9 = 1 )\n {\n v234 = i9;\n v93 += sub_11F0(v106);\n if ( v234 )\n break;\n if ( --v107 <= 1 )\n goto LABEL_292;\n v106 = v107;\n }\n }\n v109 = v92 - 3;\n if ( v92 != 2 )\n {\n while ( 1 )\n {\n while ( 1 )\n {\n v110 = sub_11F0((unsigned int)(v92 - 1 - v109));\n if ( v109 <= 1 )\n break;\n v111 = (unsigned int)v109--;\n v93 += v110 * sub_11F0(v111);\n }\n v93 += v110;\n if ( !v109 )\n break;\n v109 = 0;\n }\n }\n }\n continue;\n }\n break;\n }\n v182 += v93;\n if ( v95 )\n {\n ++v92;\n --v94;\n v95 = 0;\n goto LABEL_169;\n }\n ++v191;\n v91 = v204;\n v196 += v213 * v182;\nLABEL_181:\n if ( v191 == 1 )\n {\n v90 = 1;\n continue;\n }\n break;\n }\n v205 = v91;\n v112 = 0;\n v90 = 0;\n v113 = 1;\n v114 = v191 - 1;\n v115 = v191 - 2;\n while ( 2 )\n {\n if ( v114 > 1 )\n {\n v116 = (unsigned int)v115;\n if ( v115 > 1 )\n {\n i10 = v115;\n v118 = 0;\n v119 = 0;\n v183 = v115 - 1;\n goto LABEL_186;\n }\n if ( v115 <= 0 )\n {\n v121 = 1;\n v118 = 1;\n v183 = v115 - 1;\n goto LABEL_188;\n }\n v118 = 1;\n v183 = v115 - 1;\n for ( i10 = v115 - 1; ; i10 = v214 - 1 )\n {\n v116 = (unsigned int)i10;\n v119 = 1;\n if ( i10 <= 1 )\n break;\nLABEL_186:\n v235 = v114;\n v214 = i10;\n v120 = sub_11F0(v116);\n v114 = v235;\n v118 += v120;\n v121 = v119 + 1;\n if ( v119 + 1 > 1 )\n goto LABEL_187;\n }\n ++v118;\n v121 = 2;\nLABEL_187:\n if ( v114 <= v121 )\n {\n v122 = v114 - 1;\n }\n else\n {\nLABEL_188:\n v122 = v114 - 1;\n for ( i11 = v114 - v121 - 1; ; i11 = 0 )\n {\n while ( 1 )\n {\n v124 = sub_11F0((unsigned int)(v122 - i11));\n if ( i11 <= 1 )\n break;\n v125 = (unsigned int)i11--;\n v118 += sub_11F0(v125) * v124;\n }\n v118 += v124;\n if ( !i11 )\n break;\n }\n }\n v115 = v183;\n ++v112;\n v114 = v122;\n v90 += v118 * v113;\nLABEL_197:\n if ( v112 == 1 )\n {\n v113 = 1;\n }\n else\n {\n v126 = v112 - 1;\n v127 = (unsigned int)(v112 - 1);\n if ( v112 == 2 )\n {\n v113 = 1;\nLABEL_296:\n ++v113;\n }\n else\n {\n v128 = v112 - 1;\n v129 = 0;\n v113 = 0;\n while ( 1 )\n {\n v215 = v129;\n v184 = v114;\n v130 = sub_11F0(v127);\n v114 = v184;\n v113 += v130;\n if ( v215 )\n break;\n if ( --v128 <= 1 )\n goto LABEL_296;\n v127 = v128;\n v129 = 1;\n }\n }\n if ( v112 != 2 )\n {\n v185 = v90;\n v131 = v113;\n v132 = v112 - 3;\n v133 = v114;\n while ( 1 )\n {\n for ( i12 = sub_11F0((unsigned int)(v126 - v132)); v132 > 1; i12 = sub_11F0((unsigned int)(v126 - v132)) )\n {\n v135 = (unsigned int)v132--;\n v131 += sub_11F0(v135) * i12;\n }\n v131 += i12;\n if ( !v132 )\n break;\n v132 = 0;\n }\n v113 = v131;\n v114 = v133;\n v90 = v185;\n }\n }\n continue;\n }\n break;\n }\n v90 += v113;\n if ( v114 )\n {\n ++v112;\n --v115;\n v114 = 0;\n goto LABEL_197;\n }\n v91 = v205;\n if ( v205 > 1 )\n goto LABEL_154;\nLABEL_211:\n v196 += v90;\n if ( v91 )\n {\n ++v191;\n v91 = 0;\n goto LABEL_181;\n }\n ++v218;\n v219 += v196 * v199;\n v88 = v221;\nLABEL_220:\n if ( v218 == 1 )\n {\n v199 = 1;\n continue;\n }\n break;\n }\n v199 = 0;\n v197 = 0;\n v186 = 1;\n v136 = v218 - 1;\n v216 = v88;\n while ( 2 )\n {\n if ( v136 <= 1 )\n goto LABEL_278;\nLABEL_223:\n v137 = v136 - 1;\n v138 = 0;\n v139 = 1;\n v192 = 0;\n v140 = v136 - 2;\n v206 = v137;\n while ( 2 )\n {\n if ( v137 > 1 )\n {\n v141 = (unsigned int)v140;\n if ( v140 > 1 )\n {\n i13 = v140;\n v143 = 0;\n v144 = v140 - 1;\n v145 = 0;\n goto LABEL_227;\n }\n if ( v140 <= 0 )\n {\n v146 = 1;\n v145 = 1;\n v144 = v140 - 1;\n goto LABEL_229;\n }\n v144 = v140 - 1;\n v145 = 1;\n for ( i13 = v140 - 1; ; i13 = v222 - 1 )\n {\n v141 = (unsigned int)i13;\n v143 = 1;\n if ( i13 <= 1 )\n break;\nLABEL_227:\n v236 = v143;\n v222 = i13;\n v145 += sub_11F0(v141);\n v146 = v236 + 1;\n if ( v236 + 1 > 1 )\n goto LABEL_228;\n }\n ++v145;\n v146 = 2;\nLABEL_228:\n if ( v137 <= v146 )\n {\n --v137;\n }\n else\n {\nLABEL_229:\n v147 = v137--;\n for ( i14 = v147 - v146 - 1; ; i14 = 0 )\n {\n while ( 1 )\n {\n v149 = sub_11F0((unsigned int)(v137 - i14));\n if ( i14 <= 1 )\n break;\n v150 = (unsigned int)i14--;\n v145 += sub_11F0(v150) * v149;\n }\n v145 += v149;\n if ( !i14 )\n break;\n }\n }\n ++v138;\n v140 = v144;\n v192 += v145 * v139;\nLABEL_238:\n if ( v138 == 1 )\n {\n v139 = 1;\n }\n else\n {\n v151 = v138 - 1;\n v152 = (unsigned int)(v138 - 1);\n if ( v138 == 2 )\n {\n v139 = 1;\nLABEL_290:\n ++v139;\n }\n else\n {\n v153 = v138 - 1;\n v139 = 0;\n for ( i15 = 0; ; i15 = 1 )\n {\n v223 = i15;\n v139 += sub_11F0(v152);\n if ( v223 )\n break;\n if ( --v153 <= 1 )\n goto LABEL_290;\n v152 = v153;\n }\n }\n v155 = v138 - 3;\n if ( v138 != 2 )\n {\n while ( 1 )\n {\n for ( i16 = sub_11F0((unsigned int)(v151 - v155)); v155 > 1; i16 = sub_11F0((unsigned int)(v151 - v155)) )\n {\n v157 = (unsigned int)v155--;\n v139 += sub_11F0(v157) * i16;\n }\n v139 += i16;\n if ( !v155 )\n break;\n v155 = 0;\n }\n }\n }\n continue;\n }\n break;\n }\n v192 += v139;\n if ( v137 )\n {\n ++v138;\n --v140;\n v137 = 0;\n goto LABEL_238;\n }\n ++v197;\n v199 += v192 * v186;\n v136 = v206;\nLABEL_250:\n if ( v197 == 1 )\n {\n v186 = 1;\n continue;\n }\n break;\n }\n v193 = v136;\n v158 = 0;\n v159 = 1;\n v186 = 0;\n v160 = v197 - 2;\n v161 = v197 - 1;\n while ( 2 )\n {\n if ( v161 > 1 )\n {\n v162 = (unsigned int)v160;\n if ( v160 > 1 )\n {\n i17 = v160;\n v164 = 0;\n v165 = v160 - 1;\n v166 = 0;\n goto LABEL_255;\n }\n if ( v160 <= 0 )\n {\n v167 = 1;\n v164 = 1;\n v165 = v160 - 1;\n goto LABEL_257;\n }\n v165 = v160 - 1;\n v164 = 1;\n for ( i17 = v160 - 1; ; i17 = v207 - 1 )\n {\n v162 = (unsigned int)i17;\n v166 = 1;\n if ( i17 <= 1 )\n break;\nLABEL_255:\n v224 = v166;\n v207 = i17;\n v164 += sub_11F0(v162);\n v167 = v224 + 1;\n if ( v224 + 1 > 1 )\n goto LABEL_256;\n }\n ++v164;\n v167 = 2;\nLABEL_256:\n if ( v161 <= v167 )\n {\n --v161;\n }\n else\n {\nLABEL_257:\n v168 = v161--;\n for ( i18 = v168 - v167 - 1; ; i18 = 0 )\n {\n while ( 1 )\n {\n v170 = sub_11F0((unsigned int)(v161 - i18));\n if ( i18 <= 1 )\n break;\n v171 = (unsigned int)i18--;\n v164 += sub_11F0(v171) * v170;\n }\n v164 += v170;\n if ( !i18 )\n break;\n }\n }\n ++v158;\n v160 = v165;\n v186 += v164 * v159;\nLABEL_266:\n if ( v158 == 1 )\n {\n v159 = 1;\n }\n else\n {\n v172 = v158 - 1;\n v173 = (unsigned int)(v158 - 1);\n if ( v158 == 2 )\n {\n v159 = 1;\nLABEL_294:\n ++v159;\n }\n else\n {\n v174 = v158 - 1;\n v175 = 0;\n v159 = 0;\n while ( 1 )\n {\n v208 = v175;\n v159 += sub_11F0(v173);\n if ( v208 )\n break;\n if ( --v174 <= 1 )\n goto LABEL_294;\n v173 = v174;\n v175 = 1;\n }\n }\n v176 = v158 - 3;\n if ( v158 != 2 )\n {\n while ( 1 )\n {\n for ( i19 = sub_11F0((unsigned int)(v172 - v176)); v176 > 1; i19 = sub_11F0((unsigned int)(v172 - v176)) )\n {\n v178 = (unsigned int)v176--;\n v159 += sub_11F0(v178) * i19;\n }\n v159 += i19;\n if ( !v176 )\n break;\n v176 = 0;\n }\n }\n }\n continue;\n }\n break;\n }\n v186 += v159;\n if ( v161 )\n {\n ++v158;\n --v160;\n v161 = 0;\n goto LABEL_266;\n }\n v136 = v193;\n if ( v193 > 1 )\n goto LABEL_223;\nLABEL_278:\n v199 += v186;\n if ( v136 )\n {\n ++v197;\n v136 = 0;\n goto LABEL_250;\n }\n v88 = v216;\n if ( v216 > 1 )\n goto LABEL_152;\nLABEL_287:\n v219 += v199;\n if ( v88 )\n {\n ++v218;\n v88 = 0;\n goto LABEL_220;\n }\n v2 = v229;\n }\n while ( v229 > 1 );\nLABEL_298:\n v231 += v219;\n if ( v2 )\n {\n ++v230;\n v2 = 0;\n if ( v230 != 1 )\n goto LABEL_150;\n goto LABEL_300;\n }\n return v231;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11F0(int a1) {\n unsigned int v1;\n int v2;\n int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n int v8;\n long long v9;\n int j;\n int v11;\n int v12;\n int v13;\n int v14;\n int v15;\n int i;\n int v17;\n long long v18;\n int v19;\n long long v20;\n unsigned int v21;\n int k;\n int v23;\n int m;\n long long v25;\n int v26;\n int v27;\n int v28;\n int v29;\n long long v30;\n int n;\n int v32;\n int v33;\n int v34;\n int v35;\n int v36;\n int ii;\n int jj;\n long long v39;\n long long v40;\n unsigned int v41;\n int v42;\n int v43;\n int v44;\n long long v45;\n int v46;\n int v47;\n int v48;\n int v49;\n int v50;\n long long v51;\n int kk;\n int v53;\n int v54;\n int v55;\n int v56;\n int v57;\n int mm;\n int v59;\n long long v60;\n int v61;\n long long v62;\n unsigned int v63;\n int nn;\n int v65;\n int i1;\n long long v67;\n int v68;\n int v69;\n int v70;\n int v71;\n long long v72;\n int i2;\n int v74;\n int v75;\n int v76;\n int v77;\n int v78;\n int i3;\n int i4;\n long long v81;\n long long v82;\n unsigned int v83;\n int i5;\n int v85;\n int v86;\n long long v87;\n int v88;\n int v89;\n int v90;\n int v91;\n int v92;\n int v93;\n int v94;\n int v95;\n long long v96;\n int i6;\n int v98;\n int v99;\n int v100;\n int v101;\n int v102;\n int i7;\n int i8;\n long long v105;\n long long v106;\n unsigned int v107;\n int i9;\n int v109;\n int v110;\n long long v111;\n int v112;\n int v113;\n int v114;\n int v115;\n long long v116;\n int i10;\n int v118;\n int v119;\n int v120;\n int v121;\n int v122;\n int i11;\n int v124;\n long long v125;\n int v126;\n long long v127;\n unsigned int v128;\n int v129;\n int v130;\n int v131;\n int v132;\n int v133;\n int i12;\n long long v135;\n int v136;\n int v137;\n int v138;\n int v139;\n int v140;\n long long v141;\n int i13;\n int v143;\n int v144;\n int v145;\n int v146;\n int v147;\n int i14;\n int v149;\n long long v150;\n int v151;\n long long v152;\n unsigned int v153;\n int i15;\n int v155;\n int i16;\n long long v157;\n int v158;\n int v159;\n int v160;\n int v161;\n long long v162;\n int i17;\n int v164;\n int v165;\n int v166;\n int v167;\n int v168;\n int i18;\n int v170;\n long long v171;\n int v172;\n long long v173;\n unsigned int v174;\n int v175;\n int v176;\n int i19;\n long long v178;\n int v180;\n int v181;\n int v182;\n int v183;\n int v184;\n int v185;\n int v186;\n int v187;\n int v188;\n int v189;\n int v190;\n int v191;\n int v192;\n int v193;\n int v194;\n int v195;\n int v196;\n int v197;\n int v198;\n int v199;\n int v200;\n int v201;\n int v202;\n unsigned int v203;\n int v204;\n int v205;\n int v206;\n int v207;\n int v208;\n int v209;\n int v210;\n unsigned int v211;\n int v212;\n int v213;\n int v214;\n int v215;\n int v216;\n int v217;\n int v218;\n int v219;\n int v220;\n int v221;\n int v222;\n int v223;\n int v224;\n int v225;\n int v226;\n int v227;\n int v228;\n int v229;\n int v230;\n unsigned int v231;\n int v232;\n int v233;\n int v234;\n int v235;\n int v236;\n int v237;\n int v238;\n int v239;\n int v240;\n int v241;\n int v242;\n v1 = 0;\n if (a1 <= 0) return v1;\n v219 = 1;\n v2 = a1 - 1;\n v230 = 0;\n v231 = 0;\nLABEL_3:\n if (v2 <= 1) goto LABEL_298;\n do {\n v217 = 0;\n v220 = 0;\n v3 = v2 - 1;\n v198 = 1;\n v232 = v2 - 1;\n LABEL_5:\n if (v3 <= 1) goto LABEL_139;\n do {\n v194 = 0;\n v180 = 1;\n v4 = v3 - 1;\n v200 = 0;\n v225 = v3 - 1;\n LABEL_7:\n if (v4 <= 1) goto LABEL_63;\n do {\n v5 = 0;\n v6 = 1;\n v209 = v4 - 1;\n v7 = v4 - 1;\n v8 = v4 - 2;\n v187 = 0;\n while (v7 > 1) {\n v9 = (unsigned int)v8;\n if (v8 > 1) {\n j = v8;\n v11 = 0;\n v12 = v8 - 1;\n v13 = 0;\n goto LABEL_12;\n }\n if (v8 <= 0) {\n v14 = 1;\n v13 = 1;\n v12 = v8 - 1;\n LABEL_14:\n v15 = v7--;\n for (i = v15 - v14 - 1;; i = 0) {\n while (1) {\n v17 = sub_11F0((unsigned int)(v7 - i));\n if (i <= 1) break;\n v18 = (unsigned int)i--;\n v13 += sub_11F0(v18) * v17;\n }\n v13 += v17;\n if (!i) break;\n }\n goto LABEL_22;\n }\n v12 = v8 - 1;\n v13 = 1;\n for (j = v8 - 1;; j = v237 - 1) {\n v9 = (unsigned int)j;\n v11 = 1;\n if (j <= 1) break;\n LABEL_12:\n v242 = v11;\n v237 = j;\n v13 += sub_11F0(v9);\n v14 = v242 + 1;\n if (v242 + 1 > 1) goto LABEL_13;\n }\n ++v13;\n v14 = 2;\n LABEL_13:\n if (v7 > v14) goto LABEL_14;\n --v7;\n LABEL_22:\n ++v5;\n v8 = v12;\n v187 += v6 * v13;\n LABEL_23:\n if (v5 == 1) {\n v6 = 1;\n } else {\n v19 = v5 - 1;\n v20 = (unsigned int)(v5 - 1);\n if (v5 == 2) {\n v6 = 1;\n LABEL_144:\n ++v6;\n } else {\n v21 = v5 - 1;\n v6 = 0;\n for (k = 0;; k = 1) {\n v238 = k;\n v6 += sub_11F0(v20);\n if (v238) break;\n if (--v21 <= 1) goto LABEL_144;\n v20 = v21;\n }\n }\n v23 = v5 - 3;\n if (v5 != 2) {\n while (1) {\n for (m = sub_11F0((unsigned int)(v19 - v23)); v23 > 1;\n m = sub_11F0((unsigned int)(v19 - v23))) {\n v25 = (unsigned int)v23--;\n v6 += sub_11F0(v25) * m;\n }\n v6 += m;\n if (!v23) break;\n v23 = 0;\n }\n }\n }\n }\n v187 += v6;\n if (v7) {\n ++v5;\n --v8;\n v7 = 0;\n goto LABEL_23;\n }\n ++v194;\n v4 = v209;\n v200 += v187 * v180;\n LABEL_35:\n if (v194 == 1) {\n v180 = 1;\n goto LABEL_7;\n }\n v188 = v4;\n v26 = 0;\n v27 = 1;\n v180 = 0;\n v28 = v194 - 1;\n v29 = v194 - 2;\n while (2) {\n if (v28 > 1) {\n v30 = (unsigned int)v29;\n if (v29 > 1) {\n n = v29;\n v32 = 0;\n v33 = v29 - 1;\n v34 = 0;\n goto LABEL_40;\n }\n if (v29 <= 0) {\n v35 = 1;\n v32 = 1;\n v33 = v29 - 1;\n goto LABEL_42;\n }\n v33 = v29 - 1;\n v32 = 1;\n for (n = v29 - 1;; n = v210 - 1) {\n v30 = (unsigned int)n;\n v34 = 1;\n if (n <= 1) break;\n LABEL_40:\n v239 = v34;\n v210 = n;\n v32 += sub_11F0(v30);\n v35 = v239 + 1;\n if (v239 + 1 > 1) goto LABEL_41;\n }\n ++v32;\n v35 = 2;\n LABEL_41:\n if (v28 <= v35) {\n --v28;\n } else {\n LABEL_42:\n v36 = v28--;\n for (ii = v36 - v35 - 1;; ii = 0) {\n for (jj = sub_11F0((unsigned int)(v28 - ii)); ii > 1;\n jj = sub_11F0((unsigned int)(v28 - ii))) {\n v39 = (unsigned int)ii--;\n v32 += sub_11F0(v39) * jj;\n }\n v32 += jj;\n if (!ii) break;\n }\n }\n ++v26;\n v29 = v33;\n v180 += v32 * v27;\n LABEL_51:\n if (v26 == 1) {\n v27 = 1;\n } else {\n v40 = (unsigned int)(v26 - 1);\n if (v26 == 2) {\n v27 = 1;\n LABEL_148:\n ++v27;\n } else {\n v41 = v26 - 1;\n v42 = 0;\n v27 = 0;\n while (1) {\n v211 = v41;\n v27 += sub_11F0(v40);\n if (v42) break;\n v41 = v211 - 1;\n if (v211 - 1 <= 1) goto LABEL_148;\n v40 = v41;\n v42 = 1;\n }\n }\n v43 = v26 - 3;\n if (v26 != 2) {\n while (1) {\n while (1) {\n v44 = sub_11F0((unsigned int)(v26 - 1 - v43));\n if (v43 <= 1) break;\n v45 = (unsigned int)v43--;\n v27 += v44 * sub_11F0(v45);\n }\n v27 += v44;\n if (!v43) break;\n v43 = 0;\n }\n }\n }\n continue;\n }\n break;\n }\n v180 += v27;\n if (v28) {\n ++v26;\n --v29;\n v28 = 0;\n goto LABEL_51;\n }\n v4 = v188;\n } while (v188 > 1);\n LABEL_63:\n v200 += v180;\n if (v4) {\n ++v194;\n v4 = 0;\n goto LABEL_35;\n }\n ++v217;\n v3 = v225;\n v220 += v200 * v198;\n LABEL_72:\n if (v217 == 1) {\n v198 = 1;\n goto LABEL_5;\n }\n v198 = 0;\n v195 = 0;\n v181 = 1;\n v212 = v3;\n v46 = v217 - 1;\n while (2) {\n if (v46 <= 1) goto LABEL_130;\n LABEL_75:\n v47 = 0;\n v48 = 1;\n v201 = v46 - 1;\n v49 = v46 - 2;\n v50 = v46 - 1;\n v189 = 0;\n while (2) {\n if (v50 > 1) {\n v51 = (unsigned int)v49;\n if (v49 > 1) {\n kk = v49;\n v53 = 0;\n v54 = v49 - 1;\n v55 = 0;\n goto LABEL_79;\n }\n if (v49 <= 0) {\n v56 = 1;\n v53 = 1;\n v54 = v49 - 1;\n goto LABEL_81;\n }\n v54 = v49 - 1;\n v53 = 1;\n for (kk = v49 - 1;; kk = v226 - 1) {\n v51 = (unsigned int)kk;\n v55 = 1;\n if (kk <= 1) break;\n LABEL_79:\n v240 = v55;\n v226 = kk;\n v53 += sub_11F0(v51);\n v56 = v240 + 1;\n if (v240 + 1 > 1) goto LABEL_80;\n }\n ++v53;\n v56 = 2;\n LABEL_80:\n if (v50 <= v56) {\n --v50;\n } else {\n LABEL_81:\n v57 = v50--;\n for (mm = v57 - v56 - 1;; mm = 0) {\n while (1) {\n v59 = sub_11F0((unsigned int)(v50 - mm));\n if (mm <= 1) break;\n v60 = (unsigned int)mm--;\n v53 += sub_11F0(v60) * v59;\n }\n v53 += v59;\n if (!mm) break;\n }\n }\n ++v47;\n v49 = v54;\n v189 += v53 * v48;\n LABEL_90:\n if (v47 == 1) {\n v48 = 1;\n } else {\n v61 = v47 - 1;\n v62 = (unsigned int)(v47 - 1);\n if (v47 == 2) {\n v48 = 1;\n LABEL_142:\n ++v48;\n } else {\n v63 = v47 - 1;\n v48 = 0;\n for (nn = 0;; nn = 1) {\n v227 = nn;\n v48 += sub_11F0(v62);\n if (v227) break;\n if (--v63 <= 1) goto LABEL_142;\n v62 = v63;\n }\n }\n v65 = v47 - 3;\n if (v47 != 2) {\n while (1) {\n for (i1 = sub_11F0((unsigned int)(v61 - v65)); v65 > 1;\n i1 = sub_11F0((unsigned int)(v61 - v65))) {\n v67 = (unsigned int)v65--;\n v48 += sub_11F0(v67) * i1;\n }\n v48 += i1;\n if (!v65) break;\n v65 = 0;\n }\n }\n }\n continue;\n }\n break;\n }\n v189 += v48;\n if (v50) {\n ++v47;\n --v49;\n v50 = 0;\n goto LABEL_90;\n }\n ++v195;\n v46 = v201;\n v198 += v189 * v181;\n LABEL_102:\n if (v195 == 1) {\n v181 = 1;\n continue;\n }\n break;\n }\n v190 = v46;\n v68 = 0;\n v69 = 1;\n v181 = 0;\n v70 = v195 - 1;\n v71 = v195 - 2;\n while (2) {\n if (v70 > 1) {\n v72 = (unsigned int)v71;\n if (v71 > 1) {\n i2 = v71;\n v74 = 0;\n v75 = v71 - 1;\n v76 = 0;\n goto LABEL_107;\n }\n if (v71 <= 0) {\n v77 = 1;\n v74 = 1;\n v75 = v71 - 1;\n goto LABEL_109;\n }\n v75 = v71 - 1;\n v74 = 1;\n for (i2 = v71 - 1;; i2 = v202 - 1) {\n v72 = (unsigned int)i2;\n v76 = 1;\n if (i2 <= 1) break;\n LABEL_107:\n v228 = v76;\n v202 = i2;\n v74 += sub_11F0(v72);\n v77 = v228 + 1;\n if (v228 + 1 > 1) goto LABEL_108;\n }\n ++v74;\n v77 = 2;\n LABEL_108:\n if (v70 <= v77) {\n --v70;\n } else {\n LABEL_109:\n v78 = v70--;\n for (i3 = v78 - v77 - 1;; i3 = 0) {\n for (i4 = sub_11F0((unsigned int)(v70 - i3)); i3 > 1;\n i4 = sub_11F0((unsigned int)(v70 - i3))) {\n v81 = (unsigned int)i3--;\n v74 += sub_11F0(v81) * i4;\n }\n v74 += i4;\n if (!i3) break;\n }\n }\n ++v68;\n v71 = v75;\n v181 += v74 * v69;\n LABEL_118:\n if (v68 == 1) {\n v69 = 1;\n } else {\n v82 = (unsigned int)(v68 - 1);\n if (v68 == 2) {\n v69 = 1;\n LABEL_146:\n ++v69;\n } else {\n v83 = v68 - 1;\n v69 = 0;\n for (i5 = 0;; i5 = 1) {\n v203 = v83;\n v69 += sub_11F0(v82);\n if (i5) break;\n v83 = v203 - 1;\n if (v203 - 1 <= 1) goto LABEL_146;\n v82 = v83;\n }\n }\n v85 = v68 - 3;\n if (v68 != 2) {\n while (1) {\n while (1) {\n v86 = sub_11F0((unsigned int)(v68 - 1 - v85));\n if (v85 <= 1) break;\n v87 = (unsigned int)v85--;\n v69 += v86 * sub_11F0(v87);\n }\n v69 += v86;\n if (!v85) break;\n v85 = 0;\n }\n }\n }\n continue;\n }\n break;\n }\n v181 += v69;\n if (v70) {\n ++v68;\n --v71;\n v70 = 0;\n goto LABEL_118;\n }\n v46 = v190;\n if (v190 > 1) goto LABEL_75;\n LABEL_130:\n v198 += v181;\n if (v46) {\n ++v195;\n v46 = 0;\n goto LABEL_102;\n }\n v3 = v212;\n } while (v212 > 1);\n LABEL_139:\n v220 += v198;\n if (v3) {\n ++v217;\n v3 = 0;\n goto LABEL_72;\n }\n ++v230;\n v2 = v232;\n v231 += v220 * v219;\n if (v230 == 1) {\n LABEL_300:\n v219 = 1;\n goto LABEL_3;\n }\n LABEL_150:\n v229 = v2;\n v219 = 0;\n v199 = 1;\n v218 = 0;\n v88 = v230 - 1;\n while (2) {\n if (v88 <= 1) goto LABEL_287;\n LABEL_152:\n v89 = v88 - 1;\n v191 = 0;\n v90 = 1;\n v196 = 0;\n v91 = v89;\n v221 = v89;\n while (2) {\n if (v91 <= 1) goto LABEL_211;\n LABEL_154:\n v213 = v90;\n v92 = 0;\n v204 = v91 - 1;\n v93 = 1;\n v94 = v91 - 2;\n v95 = v204;\n v182 = 0;\n while (2) {\n if (v95 > 1) {\n v96 = (unsigned int)v94;\n if (v94 > 1) {\n i6 = v94;\n v98 = 0;\n v99 = v94 - 1;\n v100 = 0;\n goto LABEL_158;\n }\n if (v94 <= 0) {\n v101 = 1;\n v98 = 1;\n v99 = v94 - 1;\n goto LABEL_160;\n }\n v99 = v94 - 1;\n v98 = 1;\n for (i6 = v94 - 1;; i6 = v233 - 1) {\n v96 = (unsigned int)i6;\n v100 = 1;\n if (i6 <= 1) break;\n LABEL_158:\n v241 = v100;\n v233 = i6;\n v98 += sub_11F0(v96);\n v101 = v241 + 1;\n if (v241 + 1 > 1) goto LABEL_159;\n }\n ++v98;\n v101 = 2;\n LABEL_159:\n if (v95 <= v101) {\n --v95;\n } else {\n LABEL_160:\n v102 = v95--;\n for (i7 = v102 - v101 - 1;; i7 = 0) {\n for (i8 = sub_11F0((unsigned int)(v95 - i7)); i7 > 1;\n i8 = sub_11F0((unsigned int)(v95 - i7))) {\n v105 = (unsigned int)i7--;\n v98 += sub_11F0(v105) * i8;\n }\n v98 += i8;\n if (!i7) break;\n }\n }\n ++v92;\n v94 = v99;\n v182 += v98 * v93;\n LABEL_169:\n if (v92 == 1) {\n v93 = 1;\n } else {\n v106 = (unsigned int)(v92 - 1);\n if (v92 == 2) {\n v93 = 1;\n LABEL_292:\n ++v93;\n } else {\n v107 = v92 - 1;\n v93 = 0;\n for (i9 = 0;; i9 = 1) {\n v234 = i9;\n v93 += sub_11F0(v106);\n if (v234) break;\n if (--v107 <= 1) goto LABEL_292;\n v106 = v107;\n }\n }\n v109 = v92 - 3;\n if (v92 != 2) {\n while (1) {\n while (1) {\n v110 = sub_11F0((unsigned int)(v92 - 1 - v109));\n if (v109 <= 1) break;\n v111 = (unsigned int)v109--;\n v93 += v110 * sub_11F0(v111);\n }\n v93 += v110;\n if (!v109) break;\n v109 = 0;\n }\n }\n }\n continue;\n }\n break;\n }\n v182 += v93;\n if (v95) {\n ++v92;\n --v94;\n v95 = 0;\n goto LABEL_169;\n }\n ++v191;\n v91 = v204;\n v196 += v213 * v182;\n LABEL_181:\n if (v191 == 1) {\n v90 = 1;\n continue;\n }\n break;\n }\n v205 = v91;\n v112 = 0;\n v90 = 0;\n v113 = 1;\n v114 = v191 - 1;\n v115 = v191 - 2;\n while (2) {\n if (v114 > 1) {\n v116 = (unsigned int)v115;\n if (v115 > 1) {\n i10 = v115;\n v118 = 0;\n v119 = 0;\n v183 = v115 - 1;\n goto LABEL_186;\n }\n if (v115 <= 0) {\n v121 = 1;\n v118 = 1;\n v183 = v115 - 1;\n goto LABEL_188;\n }\n v118 = 1;\n v183 = v115 - 1;\n for (i10 = v115 - 1;; i10 = v214 - 1) {\n v116 = (unsigned int)i10;\n v119 = 1;\n if (i10 <= 1) break;\n LABEL_186:\n v235 = v114;\n v214 = i10;\n v120 = sub_11F0(v116);\n v114 = v235;\n v118 += v120;\n v121 = v119 + 1;\n if (v119 + 1 > 1) goto LABEL_187;\n }\n ++v118;\n v121 = 2;\n LABEL_187:\n if (v114 <= v121) {\n v122 = v114 - 1;\n } else {\n LABEL_188:\n v122 = v114 - 1;\n for (i11 = v114 - v121 - 1;; i11 = 0) {\n while (1) {\n v124 = sub_11F0((unsigned int)(v122 - i11));\n if (i11 <= 1) break;\n v125 = (unsigned int)i11--;\n v118 += sub_11F0(v125) * v124;\n }\n v118 += v124;\n if (!i11) break;\n }\n }\n v115 = v183;\n ++v112;\n v114 = v122;\n v90 += v118 * v113;\n LABEL_197:\n if (v112 == 1) {\n v113 = 1;\n } else {\n v126 = v112 - 1;\n v127 = (unsigned int)(v112 - 1);\n if (v112 == 2) {\n v113 = 1;\n LABEL_296:\n ++v113;\n } else {\n v128 = v112 - 1;\n v129 = 0;\n v113 = 0;\n while (1) {\n v215 = v129;\n v184 = v114;\n v130 = sub_11F0(v127);\n v114 = v184;\n v113 += v130;\n if (v215) break;\n if (--v128 <= 1) goto LABEL_296;\n v127 = v128;\n v129 = 1;\n }\n }\n if (v112 != 2) {\n v185 = v90;\n v131 = v113;\n v132 = v112 - 3;\n v133 = v114;\n while (1) {\n for (i12 = sub_11F0((unsigned int)(v126 - v132)); v132 > 1;\n i12 = sub_11F0((unsigned int)(v126 - v132))) {\n v135 = (unsigned int)v132--;\n v131 += sub_11F0(v135) * i12;\n }\n v131 += i12;\n if (!v132) break;\n v132 = 0;\n }\n v113 = v131;\n v114 = v133;\n v90 = v185;\n }\n }\n continue;\n }\n break;\n }\n v90 += v113;\n if (v114) {\n ++v112;\n --v115;\n v114 = 0;\n goto LABEL_197;\n }\n v91 = v205;\n if (v205 > 1) goto LABEL_154;\n LABEL_211:\n v196 += v90;\n if (v91) {\n ++v191;\n v91 = 0;\n goto LABEL_181;\n }\n ++v218;\n v219 += v196 * v199;\n v88 = v221;\n LABEL_220:\n if (v218 == 1) {\n v199 = 1;\n continue;\n }\n break;\n }\n v199 = 0;\n v197 = 0;\n v186 = 1;\n v136 = v218 - 1;\n v216 = v88;\n while (2) {\n if (v136 <= 1) goto LABEL_278;\n LABEL_223:\n v137 = v136 - 1;\n v138 = 0;\n v139 = 1;\n v192 = 0;\n v140 = v136 - 2;\n v206 = v137;\n while (2) {\n if (v137 > 1) {\n v141 = (unsigned int)v140;\n if (v140 > 1) {\n i13 = v140;\n v143 = 0;\n v144 = v140 - 1;\n v145 = 0;\n goto LABEL_227;\n }\n if (v140 <= 0) {\n v146 = 1;\n v145 = 1;\n v144 = v140 - 1;\n goto LABEL_229;\n }\n v144 = v140 - 1;\n v145 = 1;\n for (i13 = v140 - 1;; i13 = v222 - 1) {\n v141 = (unsigned int)i13;\n v143 = 1;\n if (i13 <= 1) break;\n LABEL_227:\n v236 = v143;\n v222 = i13;\n v145 += sub_11F0(v141);\n v146 = v236 + 1;\n if (v236 + 1 > 1) goto LABEL_228;\n }\n ++v145;\n v146 = 2;\n LABEL_228:\n if (v137 <= v146) {\n --v137;\n } else {\n LABEL_229:\n v147 = v137--;\n for (i14 = v147 - v146 - 1;; i14 = 0) {\n while (1) {\n v149 = sub_11F0((unsigned int)(v137 - i14));\n if (i14 <= 1) break;\n v150 = (unsigned int)i14--;\n v145 += sub_11F0(v150) * v149;\n }\n v145 += v149;\n if (!i14) break;\n }\n }\n ++v138;\n v140 = v144;\n v192 += v145 * v139;\n LABEL_238:\n if (v138 == 1) {\n v139 = 1;\n } else {\n v151 = v138 - 1;\n v152 = (unsigned int)(v138 - 1);\n if (v138 == 2) {\n v139 = 1;\n LABEL_290:\n ++v139;\n } else {\n v153 = v138 - 1;\n v139 = 0;\n for (i15 = 0;; i15 = 1) {\n v223 = i15;\n v139 += sub_11F0(v152);\n if (v223) break;\n if (--v153 <= 1) goto LABEL_290;\n v152 = v153;\n }\n }\n v155 = v138 - 3;\n if (v138 != 2) {\n while (1) {\n for (i16 = sub_11F0((unsigned int)(v151 - v155)); v155 > 1;\n i16 = sub_11F0((unsigned int)(v151 - v155))) {\n v157 = (unsigned int)v155--;\n v139 += sub_11F0(v157) * i16;\n }\n v139 += i16;\n if (!v155) break;\n v155 = 0;\n }\n }\n }\n continue;\n }\n break;\n }\n v192 += v139;\n if (v137) {\n ++v138;\n --v140;\n v137 = 0;\n goto LABEL_238;\n }\n ++v197;\n v199 += v192 * v186;\n v136 = v206;\n LABEL_250:\n if (v197 == 1) {\n v186 = 1;\n continue;\n }\n break;\n }\n v193 = v136;\n v158 = 0;\n v159 = 1;\n v186 = 0;\n v160 = v197 - 2;\n v161 = v197 - 1;\n while (2) {\n if (v161 > 1) {\n v162 = (unsigned int)v160;\n if (v160 > 1) {\n i17 = v160;\n v164 = 0;\n v165 = v160 - 1;\n v166 = 0;\n goto LABEL_255;\n }\n if (v160 <= 0) {\n v167 = 1;\n v164 = 1;\n v165 = v160 - 1;\n goto LABEL_257;\n }\n v165 = v160 - 1;\n v164 = 1;\n for (i17 = v160 - 1;; i17 = v207 - 1) {\n v162 = (unsigned int)i17;\n v166 = 1;\n if (i17 <= 1) break;\n LABEL_255:\n v224 = v166;\n v207 = i17;\n v164 += sub_11F0(v162);\n v167 = v224 + 1;\n if (v224 + 1 > 1) goto LABEL_256;\n }\n ++v164;\n v167 = 2;\n LABEL_256:\n if (v161 <= v167) {\n --v161;\n } else {\n LABEL_257:\n v168 = v161--;\n for (i18 = v168 - v167 - 1;; i18 = 0) {\n while (1) {\n v170 = sub_11F0((unsigned int)(v161 - i18));\n if (i18 <= 1) break;\n v171 = (unsigned int)i18--;\n v164 += sub_11F0(v171) * v170;\n }\n v164 += v170;\n if (!i18) break;\n }\n }\n ++v158;\n v160 = v165;\n v186 += v164 * v159;\n LABEL_266:\n if (v158 == 1) {\n v159 = 1;\n } else {\n v172 = v158 - 1;\n v173 = (unsigned int)(v158 - 1);\n if (v158 == 2) {\n v159 = 1;\n LABEL_294:\n ++v159;\n } else {\n v174 = v158 - 1;\n v175 = 0;\n v159 = 0;\n while (1) {\n v208 = v175;\n v159 += sub_11F0(v173);\n if (v208) break;\n if (--v174 <= 1) goto LABEL_294;\n v173 = v174;\n v175 = 1;\n }\n }\n v176 = v158 - 3;\n if (v158 != 2) {\n while (1) {\n for (i19 = sub_11F0((unsigned int)(v172 - v176)); v176 > 1;\n i19 = sub_11F0((unsigned int)(v172 - v176))) {\n v178 = (unsigned int)v176--;\n v159 += sub_11F0(v178) * i19;\n }\n v159 += i19;\n if (!v176) break;\n v176 = 0;\n }\n }\n }\n continue;\n }\n break;\n }\n v186 += v159;\n if (v161) {\n ++v158;\n --v160;\n v161 = 0;\n goto LABEL_266;\n }\n v136 = v193;\n if (v193 > 1) goto LABEL_223;\n LABEL_278:\n v199 += v186;\n if (v136) {\n ++v197;\n v136 = 0;\n goto LABEL_250;\n }\n v88 = v216;\n if (v216 > 1) goto LABEL_152;\n LABEL_287:\n v219 += v199;\n if (v88) {\n ++v218;\n v88 = 0;\n goto LABEL_220;\n }\n v2 = v229;\n } while (v229 > 1);\nLABEL_298:\n v231 += v219;\n if (v2) {\n ++v230;\n v2 = 0;\n if (v230 != 1) goto LABEL_150;\n goto LABEL_300;\n }\n return v231;\n}", + "ida_pseudo_norm": "long long func0_part_0(int a1) {\n unsigned int v1;\n int v2;\n int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n int v8;\n long long v9;\n int j;\n int v11;\n int v12;\n int v13;\n int v14;\n int v15;\n int i;\n int v17;\n long long v18;\n int v19;\n long long v20;\n unsigned int v21;\n int k;\n int v23;\n int m;\n long long v25;\n int v26;\n int v27;\n int v28;\n int v29;\n long long v30;\n int n;\n int v32;\n int v33;\n int v34;\n int v35;\n int v36;\n int ii;\n int jj;\n long long v39;\n long long v40;\n unsigned int v41;\n int v42;\n int v43;\n int v44;\n long long v45;\n int v46;\n int v47;\n int v48;\n int v49;\n int v50;\n long long v51;\n int kk;\n int v53;\n int v54;\n int v55;\n int v56;\n int v57;\n int mm;\n int v59;\n long long v60;\n int v61;\n long long v62;\n unsigned int v63;\n int nn;\n int v65;\n int i1;\n long long v67;\n int v68;\n int v69;\n int v70;\n int v71;\n long long v72;\n int i2;\n int v74;\n int v75;\n int v76;\n int v77;\n int v78;\n int i3;\n int i4;\n long long v81;\n long long v82;\n unsigned int v83;\n int i5;\n int v85;\n int v86;\n long long v87;\n int v88;\n int v89;\n int v90;\n int v91;\n int v92;\n int v93;\n int v94;\n int v95;\n long long v96;\n int i6;\n int v98;\n int v99;\n int v100;\n int v101;\n int v102;\n int i7;\n int i8;\n long long v105;\n long long v106;\n unsigned int v107;\n int i9;\n int v109;\n int v110;\n long long v111;\n int v112;\n int v113;\n int v114;\n int v115;\n long long v116;\n int i10;\n int v118;\n int v119;\n int v120;\n int v121;\n int v122;\n int i11;\n int v124;\n long long v125;\n int v126;\n long long v127;\n unsigned int v128;\n int v129;\n int v130;\n int v131;\n int v132;\n int v133;\n int i12;\n long long v135;\n int v136;\n int v137;\n int v138;\n int v139;\n int v140;\n long long v141;\n int i13;\n int v143;\n int v144;\n int v145;\n int v146;\n int v147;\n int i14;\n int v149;\n long long v150;\n int v151;\n long long v152;\n unsigned int v153;\n int i15;\n int v155;\n int i16;\n long long v157;\n int v158;\n int v159;\n int v160;\n int v161;\n long long v162;\n int i17;\n int v164;\n int v165;\n int v166;\n int v167;\n int v168;\n int i18;\n int v170;\n long long v171;\n int v172;\n long long v173;\n unsigned int v174;\n int v175;\n int v176;\n int i19;\n long long v178;\n int v180;\n int v181;\n int v182;\n int v183;\n int v184;\n int v185;\n int v186;\n int v187;\n int v188;\n int v189;\n int v190;\n int v191;\n int v192;\n int v193;\n int v194;\n int v195;\n int v196;\n int v197;\n int v198;\n int v199;\n int v200;\n int v201;\n int v202;\n unsigned int v203;\n int v204;\n int v205;\n int v206;\n int v207;\n int v208;\n int v209;\n int v210;\n unsigned int v211;\n int v212;\n int v213;\n int v214;\n int v215;\n int v216;\n int v217;\n int v218;\n int v219;\n int v220;\n int v221;\n int v222;\n int v223;\n int v224;\n int v225;\n int v226;\n int v227;\n int v228;\n int v229;\n int v230;\n unsigned int v231;\n int v232;\n int v233;\n int v234;\n int v235;\n int v236;\n int v237;\n int v238;\n int v239;\n int v240;\n int v241;\n int v242;\n v1 = 0;\n if (a1 <= 0) return v1;\n v219 = 1;\n v2 = a1 - 1;\n v230 = 0;\n v231 = 0;\nLABEL_3:\n if (v2 <= 1) goto LABEL_298;\n do {\n v217 = 0;\n v220 = 0;\n v3 = v2 - 1;\n v198 = 1;\n v232 = v2 - 1;\n LABEL_5:\n if (v3 <= 1) goto LABEL_139;\n do {\n v194 = 0;\n v180 = 1;\n v4 = v3 - 1;\n v200 = 0;\n v225 = v3 - 1;\n LABEL_7:\n if (v4 <= 1) goto LABEL_63;\n do {\n v5 = 0;\n v6 = 1;\n v209 = v4 - 1;\n v7 = v4 - 1;\n v8 = v4 - 2;\n v187 = 0;\n while (v7 > 1) {\n v9 = (unsigned int)v8;\n if (v8 > 1) {\n j = v8;\n v11 = 0;\n v12 = v8 - 1;\n v13 = 0;\n goto LABEL_12;\n }\n if (v8 <= 0) {\n v14 = 1;\n v13 = 1;\n v12 = v8 - 1;\n LABEL_14:\n v15 = v7--;\n for (i = v15 - v14 - 1;; i = 0) {\n while (1) {\n v17 = func0_part_0((unsigned int)(v7 - i));\n if (i <= 1) break;\n v18 = (unsigned int)i--;\n v13 += func0_part_0(v18) * v17;\n }\n v13 += v17;\n if (!i) break;\n }\n goto LABEL_22;\n }\n v12 = v8 - 1;\n v13 = 1;\n for (j = v8 - 1;; j = v237 - 1) {\n v9 = (unsigned int)j;\n v11 = 1;\n if (j <= 1) break;\n LABEL_12:\n v242 = v11;\n v237 = j;\n v13 += func0_part_0(v9);\n v14 = v242 + 1;\n if (v242 + 1 > 1) goto LABEL_13;\n }\n ++v13;\n v14 = 2;\n LABEL_13:\n if (v7 > v14) goto LABEL_14;\n --v7;\n LABEL_22:\n ++v5;\n v8 = v12;\n v187 += v6 * v13;\n LABEL_23:\n if (v5 == 1) {\n v6 = 1;\n } else {\n v19 = v5 - 1;\n v20 = (unsigned int)(v5 - 1);\n if (v5 == 2) {\n v6 = 1;\n LABEL_144:\n ++v6;\n } else {\n v21 = v5 - 1;\n v6 = 0;\n for (k = 0;; k = 1) {\n v238 = k;\n v6 += func0_part_0(v20);\n if (v238) break;\n if (--v21 <= 1) goto LABEL_144;\n v20 = v21;\n }\n }\n v23 = v5 - 3;\n if (v5 != 2) {\n while (1) {\n for (m = func0_part_0((unsigned int)(v19 - v23)); v23 > 1;\n m = func0_part_0((unsigned int)(v19 - v23))) {\n v25 = (unsigned int)v23--;\n v6 += func0_part_0(v25) * m;\n }\n v6 += m;\n if (!v23) break;\n v23 = 0;\n }\n }\n }\n }\n v187 += v6;\n if (v7) {\n ++v5;\n --v8;\n v7 = 0;\n goto LABEL_23;\n }\n ++v194;\n v4 = v209;\n v200 += v187 * v180;\n LABEL_35:\n if (v194 == 1) {\n v180 = 1;\n goto LABEL_7;\n }\n v188 = v4;\n v26 = 0;\n v27 = 1;\n v180 = 0;\n v28 = v194 - 1;\n v29 = v194 - 2;\n while (2) {\n if (v28 > 1) {\n v30 = (unsigned int)v29;\n if (v29 > 1) {\n n = v29;\n v32 = 0;\n v33 = v29 - 1;\n v34 = 0;\n goto LABEL_40;\n }\n if (v29 <= 0) {\n v35 = 1;\n v32 = 1;\n v33 = v29 - 1;\n goto LABEL_42;\n }\n v33 = v29 - 1;\n v32 = 1;\n for (n = v29 - 1;; n = v210 - 1) {\n v30 = (unsigned int)n;\n v34 = 1;\n if (n <= 1) break;\n LABEL_40:\n v239 = v34;\n v210 = n;\n v32 += func0_part_0(v30);\n v35 = v239 + 1;\n if (v239 + 1 > 1) goto LABEL_41;\n }\n ++v32;\n v35 = 2;\n LABEL_41:\n if (v28 <= v35) {\n --v28;\n } else {\n LABEL_42:\n v36 = v28--;\n for (ii = v36 - v35 - 1;; ii = 0) {\n for (jj = func0_part_0((unsigned int)(v28 - ii)); ii > 1;\n jj = func0_part_0((unsigned int)(v28 - ii))) {\n v39 = (unsigned int)ii--;\n v32 += func0_part_0(v39) * jj;\n }\n v32 += jj;\n if (!ii) break;\n }\n }\n ++v26;\n v29 = v33;\n v180 += v32 * v27;\n LABEL_51:\n if (v26 == 1) {\n v27 = 1;\n } else {\n v40 = (unsigned int)(v26 - 1);\n if (v26 == 2) {\n v27 = 1;\n LABEL_148:\n ++v27;\n } else {\n v41 = v26 - 1;\n v42 = 0;\n v27 = 0;\n while (1) {\n v211 = v41;\n v27 += func0_part_0(v40);\n if (v42) break;\n v41 = v211 - 1;\n if (v211 - 1 <= 1) goto LABEL_148;\n v40 = v41;\n v42 = 1;\n }\n }\n v43 = v26 - 3;\n if (v26 != 2) {\n while (1) {\n while (1) {\n v44 = func0_part_0((unsigned int)(v26 - 1 - v43));\n if (v43 <= 1) break;\n v45 = (unsigned int)v43--;\n v27 += v44 * func0_part_0(v45);\n }\n v27 += v44;\n if (!v43) break;\n v43 = 0;\n }\n }\n }\n continue;\n }\n break;\n }\n v180 += v27;\n if (v28) {\n ++v26;\n --v29;\n v28 = 0;\n goto LABEL_51;\n }\n v4 = v188;\n } while (v188 > 1);\n LABEL_63:\n v200 += v180;\n if (v4) {\n ++v194;\n v4 = 0;\n goto LABEL_35;\n }\n ++v217;\n v3 = v225;\n v220 += v200 * v198;\n LABEL_72:\n if (v217 == 1) {\n v198 = 1;\n goto LABEL_5;\n }\n v198 = 0;\n v195 = 0;\n v181 = 1;\n v212 = v3;\n v46 = v217 - 1;\n while (2) {\n if (v46 <= 1) goto LABEL_130;\n LABEL_75:\n v47 = 0;\n v48 = 1;\n v201 = v46 - 1;\n v49 = v46 - 2;\n v50 = v46 - 1;\n v189 = 0;\n while (2) {\n if (v50 > 1) {\n v51 = (unsigned int)v49;\n if (v49 > 1) {\n kk = v49;\n v53 = 0;\n v54 = v49 - 1;\n v55 = 0;\n goto LABEL_79;\n }\n if (v49 <= 0) {\n v56 = 1;\n v53 = 1;\n v54 = v49 - 1;\n goto LABEL_81;\n }\n v54 = v49 - 1;\n v53 = 1;\n for (kk = v49 - 1;; kk = v226 - 1) {\n v51 = (unsigned int)kk;\n v55 = 1;\n if (kk <= 1) break;\n LABEL_79:\n v240 = v55;\n v226 = kk;\n v53 += func0_part_0(v51);\n v56 = v240 + 1;\n if (v240 + 1 > 1) goto LABEL_80;\n }\n ++v53;\n v56 = 2;\n LABEL_80:\n if (v50 <= v56) {\n --v50;\n } else {\n LABEL_81:\n v57 = v50--;\n for (mm = v57 - v56 - 1;; mm = 0) {\n while (1) {\n v59 = func0_part_0((unsigned int)(v50 - mm));\n if (mm <= 1) break;\n v60 = (unsigned int)mm--;\n v53 += func0_part_0(v60) * v59;\n }\n v53 += v59;\n if (!mm) break;\n }\n }\n ++v47;\n v49 = v54;\n v189 += v53 * v48;\n LABEL_90:\n if (v47 == 1) {\n v48 = 1;\n } else {\n v61 = v47 - 1;\n v62 = (unsigned int)(v47 - 1);\n if (v47 == 2) {\n v48 = 1;\n LABEL_142:\n ++v48;\n } else {\n v63 = v47 - 1;\n v48 = 0;\n for (nn = 0;; nn = 1) {\n v227 = nn;\n v48 += func0_part_0(v62);\n if (v227) break;\n if (--v63 <= 1) goto LABEL_142;\n v62 = v63;\n }\n }\n v65 = v47 - 3;\n if (v47 != 2) {\n while (1) {\n for (i1 = func0_part_0((unsigned int)(v61 - v65)); v65 > 1;\n i1 = func0_part_0((unsigned int)(v61 - v65))) {\n v67 = (unsigned int)v65--;\n v48 += func0_part_0(v67) * i1;\n }\n v48 += i1;\n if (!v65) break;\n v65 = 0;\n }\n }\n }\n continue;\n }\n break;\n }\n v189 += v48;\n if (v50) {\n ++v47;\n --v49;\n v50 = 0;\n goto LABEL_90;\n }\n ++v195;\n v46 = v201;\n v198 += v189 * v181;\n LABEL_102:\n if (v195 == 1) {\n v181 = 1;\n continue;\n }\n break;\n }\n v190 = v46;\n v68 = 0;\n v69 = 1;\n v181 = 0;\n v70 = v195 - 1;\n v71 = v195 - 2;\n while (2) {\n if (v70 > 1) {\n v72 = (unsigned int)v71;\n if (v71 > 1) {\n i2 = v71;\n v74 = 0;\n v75 = v71 - 1;\n v76 = 0;\n goto LABEL_107;\n }\n if (v71 <= 0) {\n v77 = 1;\n v74 = 1;\n v75 = v71 - 1;\n goto LABEL_109;\n }\n v75 = v71 - 1;\n v74 = 1;\n for (i2 = v71 - 1;; i2 = v202 - 1) {\n v72 = (unsigned int)i2;\n v76 = 1;\n if (i2 <= 1) break;\n LABEL_107:\n v228 = v76;\n v202 = i2;\n v74 += func0_part_0(v72);\n v77 = v228 + 1;\n if (v228 + 1 > 1) goto LABEL_108;\n }\n ++v74;\n v77 = 2;\n LABEL_108:\n if (v70 <= v77) {\n --v70;\n } else {\n LABEL_109:\n v78 = v70--;\n for (i3 = v78 - v77 - 1;; i3 = 0) {\n for (i4 = func0_part_0((unsigned int)(v70 - i3)); i3 > 1;\n i4 = func0_part_0((unsigned int)(v70 - i3))) {\n v81 = (unsigned int)i3--;\n v74 += func0_part_0(v81) * i4;\n }\n v74 += i4;\n if (!i3) break;\n }\n }\n ++v68;\n v71 = v75;\n v181 += v74 * v69;\n LABEL_118:\n if (v68 == 1) {\n v69 = 1;\n } else {\n v82 = (unsigned int)(v68 - 1);\n if (v68 == 2) {\n v69 = 1;\n LABEL_146:\n ++v69;\n } else {\n v83 = v68 - 1;\n v69 = 0;\n for (i5 = 0;; i5 = 1) {\n v203 = v83;\n v69 += func0_part_0(v82);\n if (i5) break;\n v83 = v203 - 1;\n if (v203 - 1 <= 1) goto LABEL_146;\n v82 = v83;\n }\n }\n v85 = v68 - 3;\n if (v68 != 2) {\n while (1) {\n while (1) {\n v86 = func0_part_0((unsigned int)(v68 - 1 - v85));\n if (v85 <= 1) break;\n v87 = (unsigned int)v85--;\n v69 += v86 * func0_part_0(v87);\n }\n v69 += v86;\n if (!v85) break;\n v85 = 0;\n }\n }\n }\n continue;\n }\n break;\n }\n v181 += v69;\n if (v70) {\n ++v68;\n --v71;\n v70 = 0;\n goto LABEL_118;\n }\n v46 = v190;\n if (v190 > 1) goto LABEL_75;\n LABEL_130:\n v198 += v181;\n if (v46) {\n ++v195;\n v46 = 0;\n goto LABEL_102;\n }\n v3 = v212;\n } while (v212 > 1);\n LABEL_139:\n v220 += v198;\n if (v3) {\n ++v217;\n v3 = 0;\n goto LABEL_72;\n }\n ++v230;\n v2 = v232;\n v231 += v220 * v219;\n if (v230 == 1) {\n LABEL_300:\n v219 = 1;\n goto LABEL_3;\n }\n LABEL_150:\n v229 = v2;\n v219 = 0;\n v199 = 1;\n v218 = 0;\n v88 = v230 - 1;\n while (2) {\n if (v88 <= 1) goto LABEL_287;\n LABEL_152:\n v89 = v88 - 1;\n v191 = 0;\n v90 = 1;\n v196 = 0;\n v91 = v89;\n v221 = v89;\n while (2) {\n if (v91 <= 1) goto LABEL_211;\n LABEL_154:\n v213 = v90;\n v92 = 0;\n v204 = v91 - 1;\n v93 = 1;\n v94 = v91 - 2;\n v95 = v204;\n v182 = 0;\n while (2) {\n if (v95 > 1) {\n v96 = (unsigned int)v94;\n if (v94 > 1) {\n i6 = v94;\n v98 = 0;\n v99 = v94 - 1;\n v100 = 0;\n goto LABEL_158;\n }\n if (v94 <= 0) {\n v101 = 1;\n v98 = 1;\n v99 = v94 - 1;\n goto LABEL_160;\n }\n v99 = v94 - 1;\n v98 = 1;\n for (i6 = v94 - 1;; i6 = v233 - 1) {\n v96 = (unsigned int)i6;\n v100 = 1;\n if (i6 <= 1) break;\n LABEL_158:\n v241 = v100;\n v233 = i6;\n v98 += func0_part_0(v96);\n v101 = v241 + 1;\n if (v241 + 1 > 1) goto LABEL_159;\n }\n ++v98;\n v101 = 2;\n LABEL_159:\n if (v95 <= v101) {\n --v95;\n } else {\n LABEL_160:\n v102 = v95--;\n for (i7 = v102 - v101 - 1;; i7 = 0) {\n for (i8 = func0_part_0((unsigned int)(v95 - i7)); i7 > 1;\n i8 = func0_part_0((unsigned int)(v95 - i7))) {\n v105 = (unsigned int)i7--;\n v98 += func0_part_0(v105) * i8;\n }\n v98 += i8;\n if (!i7) break;\n }\n }\n ++v92;\n v94 = v99;\n v182 += v98 * v93;\n LABEL_169:\n if (v92 == 1) {\n v93 = 1;\n } else {\n v106 = (unsigned int)(v92 - 1);\n if (v92 == 2) {\n v93 = 1;\n LABEL_292:\n ++v93;\n } else {\n v107 = v92 - 1;\n v93 = 0;\n for (i9 = 0;; i9 = 1) {\n v234 = i9;\n v93 += func0_part_0(v106);\n if (v234) break;\n if (--v107 <= 1) goto LABEL_292;\n v106 = v107;\n }\n }\n v109 = v92 - 3;\n if (v92 != 2) {\n while (1) {\n while (1) {\n v110 = func0_part_0((unsigned int)(v92 - 1 - v109));\n if (v109 <= 1) break;\n v111 = (unsigned int)v109--;\n v93 += v110 * func0_part_0(v111);\n }\n v93 += v110;\n if (!v109) break;\n v109 = 0;\n }\n }\n }\n continue;\n }\n break;\n }\n v182 += v93;\n if (v95) {\n ++v92;\n --v94;\n v95 = 0;\n goto LABEL_169;\n }\n ++v191;\n v91 = v204;\n v196 += v213 * v182;\n LABEL_181:\n if (v191 == 1) {\n v90 = 1;\n continue;\n }\n break;\n }\n v205 = v91;\n v112 = 0;\n v90 = 0;\n v113 = 1;\n v114 = v191 - 1;\n v115 = v191 - 2;\n while (2) {\n if (v114 > 1) {\n v116 = (unsigned int)v115;\n if (v115 > 1) {\n i10 = v115;\n v118 = 0;\n v119 = 0;\n v183 = v115 - 1;\n goto LABEL_186;\n }\n if (v115 <= 0) {\n v121 = 1;\n v118 = 1;\n v183 = v115 - 1;\n goto LABEL_188;\n }\n v118 = 1;\n v183 = v115 - 1;\n for (i10 = v115 - 1;; i10 = v214 - 1) {\n v116 = (unsigned int)i10;\n v119 = 1;\n if (i10 <= 1) break;\n LABEL_186:\n v235 = v114;\n v214 = i10;\n v120 = func0_part_0(v116);\n v114 = v235;\n v118 += v120;\n v121 = v119 + 1;\n if (v119 + 1 > 1) goto LABEL_187;\n }\n ++v118;\n v121 = 2;\n LABEL_187:\n if (v114 <= v121) {\n v122 = v114 - 1;\n } else {\n LABEL_188:\n v122 = v114 - 1;\n for (i11 = v114 - v121 - 1;; i11 = 0) {\n while (1) {\n v124 = func0_part_0((unsigned int)(v122 - i11));\n if (i11 <= 1) break;\n v125 = (unsigned int)i11--;\n v118 += func0_part_0(v125) * v124;\n }\n v118 += v124;\n if (!i11) break;\n }\n }\n v115 = v183;\n ++v112;\n v114 = v122;\n v90 += v118 * v113;\n LABEL_197:\n if (v112 == 1) {\n v113 = 1;\n } else {\n v126 = v112 - 1;\n v127 = (unsigned int)(v112 - 1);\n if (v112 == 2) {\n v113 = 1;\n LABEL_296:\n ++v113;\n } else {\n v128 = v112 - 1;\n v129 = 0;\n v113 = 0;\n while (1) {\n v215 = v129;\n v184 = v114;\n v130 = func0_part_0(v127);\n v114 = v184;\n v113 += v130;\n if (v215) break;\n if (--v128 <= 1) goto LABEL_296;\n v127 = v128;\n v129 = 1;\n }\n }\n if (v112 != 2) {\n v185 = v90;\n v131 = v113;\n v132 = v112 - 3;\n v133 = v114;\n while (1) {\n for (i12 = func0_part_0((unsigned int)(v126 - v132)); v132 > 1;\n i12 = func0_part_0((unsigned int)(v126 - v132))) {\n v135 = (unsigned int)v132--;\n v131 += func0_part_0(v135) * i12;\n }\n v131 += i12;\n if (!v132) break;\n v132 = 0;\n }\n v113 = v131;\n v114 = v133;\n v90 = v185;\n }\n }\n continue;\n }\n break;\n }\n v90 += v113;\n if (v114) {\n ++v112;\n --v115;\n v114 = 0;\n goto LABEL_197;\n }\n v91 = v205;\n if (v205 > 1) goto LABEL_154;\n LABEL_211:\n v196 += v90;\n if (v91) {\n ++v191;\n v91 = 0;\n goto LABEL_181;\n }\n ++v218;\n v219 += v196 * v199;\n v88 = v221;\n LABEL_220:\n if (v218 == 1) {\n v199 = 1;\n continue;\n }\n break;\n }\n v199 = 0;\n v197 = 0;\n v186 = 1;\n v136 = v218 - 1;\n v216 = v88;\n while (2) {\n if (v136 <= 1) goto LABEL_278;\n LABEL_223:\n v137 = v136 - 1;\n v138 = 0;\n v139 = 1;\n v192 = 0;\n v140 = v136 - 2;\n v206 = v137;\n while (2) {\n if (v137 > 1) {\n v141 = (unsigned int)v140;\n if (v140 > 1) {\n i13 = v140;\n v143 = 0;\n v144 = v140 - 1;\n v145 = 0;\n goto LABEL_227;\n }\n if (v140 <= 0) {\n v146 = 1;\n v145 = 1;\n v144 = v140 - 1;\n goto LABEL_229;\n }\n v144 = v140 - 1;\n v145 = 1;\n for (i13 = v140 - 1;; i13 = v222 - 1) {\n v141 = (unsigned int)i13;\n v143 = 1;\n if (i13 <= 1) break;\n LABEL_227:\n v236 = v143;\n v222 = i13;\n v145 += func0_part_0(v141);\n v146 = v236 + 1;\n if (v236 + 1 > 1) goto LABEL_228;\n }\n ++v145;\n v146 = 2;\n LABEL_228:\n if (v137 <= v146) {\n --v137;\n } else {\n LABEL_229:\n v147 = v137--;\n for (i14 = v147 - v146 - 1;; i14 = 0) {\n while (1) {\n v149 = func0_part_0((unsigned int)(v137 - i14));\n if (i14 <= 1) break;\n v150 = (unsigned int)i14--;\n v145 += func0_part_0(v150) * v149;\n }\n v145 += v149;\n if (!i14) break;\n }\n }\n ++v138;\n v140 = v144;\n v192 += v145 * v139;\n LABEL_238:\n if (v138 == 1) {\n v139 = 1;\n } else {\n v151 = v138 - 1;\n v152 = (unsigned int)(v138 - 1);\n if (v138 == 2) {\n v139 = 1;\n LABEL_290:\n ++v139;\n } else {\n v153 = v138 - 1;\n v139 = 0;\n for (i15 = 0;; i15 = 1) {\n v223 = i15;\n v139 += func0_part_0(v152);\n if (v223) break;\n if (--v153 <= 1) goto LABEL_290;\n v152 = v153;\n }\n }\n v155 = v138 - 3;\n if (v138 != 2) {\n while (1) {\n for (i16 = func0_part_0((unsigned int)(v151 - v155)); v155 > 1;\n i16 = func0_part_0((unsigned int)(v151 - v155))) {\n v157 = (unsigned int)v155--;\n v139 += func0_part_0(v157) * i16;\n }\n v139 += i16;\n if (!v155) break;\n v155 = 0;\n }\n }\n }\n continue;\n }\n break;\n }\n v192 += v139;\n if (v137) {\n ++v138;\n --v140;\n v137 = 0;\n goto LABEL_238;\n }\n ++v197;\n v199 += v192 * v186;\n v136 = v206;\n LABEL_250:\n if (v197 == 1) {\n v186 = 1;\n continue;\n }\n break;\n }\n v193 = v136;\n v158 = 0;\n v159 = 1;\n v186 = 0;\n v160 = v197 - 2;\n v161 = v197 - 1;\n while (2) {\n if (v161 > 1) {\n v162 = (unsigned int)v160;\n if (v160 > 1) {\n i17 = v160;\n v164 = 0;\n v165 = v160 - 1;\n v166 = 0;\n goto LABEL_255;\n }\n if (v160 <= 0) {\n v167 = 1;\n v164 = 1;\n v165 = v160 - 1;\n goto LABEL_257;\n }\n v165 = v160 - 1;\n v164 = 1;\n for (i17 = v160 - 1;; i17 = v207 - 1) {\n v162 = (unsigned int)i17;\n v166 = 1;\n if (i17 <= 1) break;\n LABEL_255:\n v224 = v166;\n v207 = i17;\n v164 += func0_part_0(v162);\n v167 = v224 + 1;\n if (v224 + 1 > 1) goto LABEL_256;\n }\n ++v164;\n v167 = 2;\n LABEL_256:\n if (v161 <= v167) {\n --v161;\n } else {\n LABEL_257:\n v168 = v161--;\n for (i18 = v168 - v167 - 1;; i18 = 0) {\n while (1) {\n v170 = func0_part_0((unsigned int)(v161 - i18));\n if (i18 <= 1) break;\n v171 = (unsigned int)i18--;\n v164 += func0_part_0(v171) * v170;\n }\n v164 += v170;\n if (!i18) break;\n }\n }\n ++v158;\n v160 = v165;\n v186 += v164 * v159;\n LABEL_266:\n if (v158 == 1) {\n v159 = 1;\n } else {\n v172 = v158 - 1;\n v173 = (unsigned int)(v158 - 1);\n if (v158 == 2) {\n v159 = 1;\n LABEL_294:\n ++v159;\n } else {\n v174 = v158 - 1;\n v175 = 0;\n v159 = 0;\n while (1) {\n v208 = v175;\n v159 += func0_part_0(v173);\n if (v208) break;\n if (--v174 <= 1) goto LABEL_294;\n v173 = v174;\n v175 = 1;\n }\n }\n v176 = v158 - 3;\n if (v158 != 2) {\n while (1) {\n for (i19 = func0_part_0((unsigned int)(v172 - v176)); v176 > 1;\n i19 = func0_part_0((unsigned int)(v172 - v176))) {\n v178 = (unsigned int)v176--;\n v159 += func0_part_0(v178) * i19;\n }\n v159 += i19;\n if (!v176) break;\n v176 = 0;\n }\n }\n }\n continue;\n }\n break;\n }\n v186 += v159;\n if (v161) {\n ++v158;\n --v160;\n v161 = 0;\n goto LABEL_266;\n }\n v136 = v193;\n if (v193 > 1) goto LABEL_223;\n LABEL_278:\n v199 += v186;\n if (v136) {\n ++v197;\n v136 = 0;\n goto LABEL_250;\n }\n v88 = v216;\n if (v216 > 1) goto LABEL_152;\n LABEL_287:\n v219 += v199;\n if (v88) {\n ++v218;\n v88 = 0;\n goto LABEL_220;\n }\n v2 = v229;\n } while (v229 > 1);\nLABEL_298:\n v231 += v219;\n if (v2) {\n ++v230;\n v2 = 0;\n if (v230 != 1) goto LABEL_150;\n goto LABEL_300;\n }\n return v231;\n}" + }, + { + "index": 584, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n regex_t regex;\n regmatch_t match[1];\n static char result[100];\n if (regcomp(®ex, \"\\\\w+ly\", REG_EXTENDED) != 0) {\n printf(\"Could not compile regex\\n\");\n return NULL;\n }\n if (regexec(®ex, text, 1, match, 0) == 0) {\n int start = match[0].rm_so;\n int end = match[0].rm_eo;\n char word[100];\n strncpy(word, text + start, end - start);\n word[end - start] = '\\0';\n snprintf(result, sizeof(result), \"%d-%d: %s\", start, end, word);\n regfree(®ex);\n return result;\n }\n regfree(®ex);\n return NULL;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"Clearly, he has no excuse for such behavior.\"), \"0-7: Clearly\") == 0);\n\n assert(strcmp(func0(\"Please handle the situation carefuly\"), \"28-36: carefuly\") == 0);\n\n assert(strcmp(func0(\"Complete the task quickly\"), \"18-25: quickly\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0xe0,%rsp\nmov %rdi,-0xd8(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea -0xc0(%rbp),%rax\nmov $0x1,%edx\nlea 0xd87(%rip),%rsi\nmov %rax,%rdi\ncallq 1130 \ntest %eax,%eax\nje 12a3 \nlea 0xd7a(%rip),%rdi\ncallq 10e0 \nmov $0x0,%eax\njmpq 138a \nlea -0x78(%rbp),%rdx\nmov -0xd8(%rbp),%rsi\nlea -0xc0(%rbp),%rax\nmov $0x0,%r8d\nmov %rdx,%rcx\nmov $0x1,%edx\nmov %rax,%rdi\ncallq 1150 \ntest %eax,%eax\njne 1376 \nmov -0x78(%rbp),%eax\nmov %eax,-0xc8(%rbp)\nmov -0x74(%rbp),%eax\nmov %eax,-0xc4(%rbp)\nmov -0xc4(%rbp),%eax\nsub -0xc8(%rbp),%eax\nmovslq %eax,%rdx\nmov -0xc8(%rbp),%eax\nmovslq %eax,%rcx\nmov -0xd8(%rbp),%rax\nadd %rax,%rcx\nlea -0x70(%rbp),%rax\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 10d0 \nmov -0xc4(%rbp),%eax\nsub -0xc8(%rbp),%eax\ncltq\nmovb $0x0,-0x70(%rbp,%rax,1)\nlea -0x70(%rbp),%rcx\nmov -0xc4(%rbp),%edx\nmov -0xc8(%rbp),%eax\nmov %rcx,%r9\nmov %edx,%r8d\nmov %eax,%ecx\nlea 0xcde(%rip),%rdx\nmov $0x64,%esi\nlea 0x2cec(%rip),%rdi\nmov $0x0,%eax\ncallq 1110 \nlea -0xc0(%rbp),%rax\nmov %rax,%rdi\ncallq 10f0 \nlea 0x2ccc(%rip),%rax\njmp 138a \nlea -0xc0(%rbp),%rax\nmov %rax,%rdi\ncallq 10f0 \nmov $0x0,%eax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 139e \ncallq 1100 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0E0h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nlea rcx, pattern; \"\\\\w+ly\"\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\ntest eax, eax\njz short loc_12A9\nlea rax, s; \"Could not compile regex\"\nmov rdi, rax; s\ncall _puts\nmov eax, 0\njmp loc_1396\nloc_12A9:\nlea rdx, [rbp+pmatch]\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov rcx, rdx; pmatch\nmov edx, 1; nmatch\nmov rdi, rax; preg\ncall _regexec\ntest eax, eax\njnz loc_1382\nmov eax, [rbp+pmatch.rm_so]\nmov [rbp+var_C8], eax\nmov eax, [rbp+pmatch.rm_eo]\nmov [rbp+var_C4], eax\nmov eax, [rbp+var_C4]\nsub eax, [rbp+var_C8]\nmovsxd rdx, eax; n\nmov eax, [rbp+var_C8]\nmovsxd rcx, eax\nmov rax, [rbp+string]\nadd rcx, rax\nlea rax, [rbp+dest]\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strncpy\nmov eax, [rbp+var_C4]\nsub eax, [rbp+var_C8]\ncdqe\nmov [rbp+rax+dest], 0\nlea rcx, [rbp+dest]\nmov edx, [rbp+var_C4]\nmov eax, [rbp+var_C8]\nmov r9, rcx\nmov r8d, edx\nmov ecx, eax\nlea rax, format; \"%d-%d: %s\"\nmov rdx, rax; format\nmov esi, 64h ; 'd'; maxlen\nlea rax, result_1\nmov rdi, rax; s\nmov eax, 0\ncall _snprintf\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nlea rax, result_1\njmp short loc_1396\nloc_1382:\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nmov eax, 0\nloc_1396:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_13AA\ncall ___stack_chk_fail\nlocret_13AA:\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(const char *a1)\n{\n regmatch_t v2; // [rsp+18h] [rbp-C8h]\n regex_t preg; // [rsp+20h] [rbp-C0h] BYREF\n regmatch_t pmatch; // [rsp+68h] [rbp-78h] BYREF\n char dest[104]; // [rsp+70h] [rbp-70h] BYREF\n unsigned __int64 v6; // [rsp+D8h] [rbp-8h]\n\n v6 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"\\\\w+ly\", 1) )\n {\n puts(\"Could not compile regex\");\n return 0LL;\n }\n else if ( regexec(&preg, a1, 1uLL, &pmatch, 0) )\n {\n regfree(&preg);\n return 0LL;\n }\n else\n {\n v2 = pmatch;\n strncpy(dest, &a1[pmatch.rm_so], pmatch.rm_eo - pmatch.rm_so);\n dest[v2.rm_eo - v2.rm_so] = 0;\n snprintf(result_1, 0x64uLL, \"%d-%d: %s\", v2.rm_so, v2.rm_eo, dest);\n regfree(&preg);\n return result_1;\n }\n}", + "ida_strip_asm": "sub_1249:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0E0h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nlea rcx, pattern; \"\\\\w+ly\"\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\ntest eax, eax\njz short loc_12A9\nlea rax, s; \"Could not compile regex\"\nmov rdi, rax; s\ncall _puts\nmov eax, 0\njmp loc_1396\nloc_12A9:\nlea rdx, [rbp+pmatch]\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov rcx, rdx; pmatch\nmov edx, 1; nmatch\nmov rdi, rax; preg\ncall _regexec\ntest eax, eax\njnz loc_1382\nmov eax, [rbp+pmatch.rm_so]\nmov [rbp+var_C8], eax\nmov eax, [rbp+pmatch.rm_eo]\nmov [rbp+var_C4], eax\nmov eax, [rbp+var_C4]\nsub eax, [rbp+var_C8]\nmovsxd rdx, eax; n\nmov eax, [rbp+var_C8]\nmovsxd rcx, eax\nmov rax, [rbp+string]\nadd rcx, rax\nlea rax, [rbp+dest]\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strncpy\nmov eax, [rbp+var_C4]\nsub eax, [rbp+var_C8]\ncdqe\nmov [rbp+rax+dest], 0\nlea rcx, [rbp+dest]\nmov edx, [rbp+var_C4]\nmov eax, [rbp+var_C8]\nmov r9, rcx\nmov r8d, edx\nmov ecx, eax\nlea rax, format; \"%d-%d: %s\"\nmov rdx, rax; format\nmov esi, 64h ; 'd'; maxlen\nlea rax, byte_4040\nmov rdi, rax; s\nmov eax, 0\ncall _snprintf\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nlea rax, byte_4040\njmp short loc_1396\nloc_1382:\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nmov eax, 0\nloc_1396:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_13AA\ncall ___stack_chk_fail\nlocret_13AA:\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1249(const char *a1)\n{\n regmatch_t v2; // [rsp+18h] [rbp-C8h]\n regex_t preg; // [rsp+20h] [rbp-C0h] BYREF\n regmatch_t pmatch; // [rsp+68h] [rbp-78h] BYREF\n char dest[104]; // [rsp+70h] [rbp-70h] BYREF\n unsigned __int64 v6; // [rsp+D8h] [rbp-8h]\n\n v6 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"\\\\w+ly\", 1) )\n {\n puts(\"Could not compile regex\");\n return 0LL;\n }\n else if ( regexec(&preg, a1, 1uLL, &pmatch, 0) )\n {\n regfree(&preg);\n return 0LL;\n }\n else\n {\n v2 = pmatch;\n strncpy(dest, &a1[pmatch.rm_so], pmatch.rm_eo - pmatch.rm_so);\n dest[v2.rm_eo - v2.rm_so] = 0;\n snprintf(byte_4040, 0x64uLL, \"%d-%d: %s\", v2.rm_so, v2.rm_eo, dest);\n regfree(&preg);\n return byte_4040;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1249(const char *a1) {\n regmatch_t v2;\n regex_t preg;\n regmatch_t pmatch;\n char dest[104];\n unsigned long long v6;\n v6 = __readfsqword(40u);\n if (regcomp(&preg, \"\\\\w+ly\", 1)) {\n puts(\"Could not compile regex\");\n return 0LL;\n } else if (regexec(&preg, a1, 1uLL, &pmatch, 0)) {\n regfree(&preg);\n return 0LL;\n } else {\n v2 = pmatch;\n strncpy(dest, &a1[pmatch.rm_so], pmatch.rm_eo - pmatch.rm_so);\n dest[v2.rm_eo - v2.rm_so] = 0;\n snprintf(byte_4040, 100uLL, \"%d-%d: %s\", v2.rm_so, v2.rm_eo, dest);\n regfree(&preg);\n return byte_4040;\n }\n}", + "ida_pseudo_norm": "char *func0(const char *a1) {\n regmatch_t v2;\n regex_t preg;\n regmatch_t pmatch;\n char dest[104];\n unsigned long long v6;\n v6 = __readfsqword(40u);\n if (regcomp(&preg, \"\\\\w+ly\", 1)) {\n puts(\"Could not compile regex\");\n return 0LL;\n } else if (regexec(&preg, a1, 1uLL, &pmatch, 0)) {\n regfree(&preg);\n return 0LL;\n } else {\n v2 = pmatch;\n strncpy(dest, &a1[pmatch.rm_so], pmatch.rm_eo - pmatch.rm_so);\n dest[v2.rm_eo - v2.rm_so] = 0;\n snprintf(result_1, 100uLL, \"%d-%d: %s\", v2.rm_so, v2.rm_eo, dest);\n regfree(&preg);\n return result_1;\n }\n}" + }, + { + "index": 584, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n regex_t regex;\n regmatch_t match[1];\n static char result[100];\n if (regcomp(®ex, \"\\\\w+ly\", REG_EXTENDED) != 0) {\n printf(\"Could not compile regex\\n\");\n return NULL;\n }\n if (regexec(®ex, text, 1, match, 0) == 0) {\n int start = match[0].rm_so;\n int end = match[0].rm_eo;\n char word[100];\n strncpy(word, text + start, end - start);\n word[end - start] = '\\0';\n snprintf(result, sizeof(result), \"%d-%d: %s\", start, end, word);\n regfree(®ex);\n return result;\n }\n regfree(®ex);\n return NULL;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"Clearly, he has no excuse for such behavior.\"), \"0-7: Clearly\") == 0);\n\n assert(strcmp(func0(\"Please handle the situation carefuly\"), \"28-36: carefuly\") == 0);\n\n assert(strcmp(func0(\"Complete the task quickly\"), \"18-25: quickly\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0xc8,%rsp\nmov %rdi,%rbx\nmov %fs:0x28,%rax\nmov %rax,0xb8(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nmov $0x1,%edx\nlea 0xda5(%rip),%rsi\ncallq 1110 \ntest %eax,%eax\njne 1325 \nlea 0x48(%rsp),%rcx\nmov %rsp,%rdi\nmov $0x0,%r8d\nmov $0x1,%edx\nmov %rbx,%rsi\ncallq 1120 \ntest %eax,%eax\njne 1338 \nmov 0x48(%rsp),%r12d\nmov 0x4c(%rsp),%r13d\nmov %r13d,%ebp\nsub %r12d,%ebp\nmovslq %ebp,%rbp\nmovslq %r12d,%rsi\nadd %rbx,%rsi\nlea 0x50(%rsp),%rbx\nmov $0x64,%ecx\nmov %rbp,%rdx\nmov %rbx,%rdi\ncallq 1130 <__strncpy_chk@plt>\nmovb $0x0,0x50(%rsp,%rbp,1)\npush %rbx\npush %r13\nmov %r12d,%r9d\nlea 0xd53(%rip),%r8\nmov $0x64,%ecx\nmov $0x1,%edx\nmov $0x64,%esi\nlea 0x2d5b(%rip),%rdi\nmov $0x0,%eax\ncallq 10c0 <__snprintf_chk@plt>\nlea 0x10(%rsp),%rdi\ncallq 10e0 \nadd $0x10,%rsp\nlea 0x2d3c(%rip),%rax\nmov 0xb8(%rsp),%rdx\nxor %fs:0x28,%rdx\njne 1347 \nadd $0xc8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nlea 0xcde(%rip),%rdi\ncallq 10d0 \nmov $0x0,%eax\njmp 1304 \nmov %rsp,%rdi\ncallq 10e0 \nmov $0x0,%eax\njmp 1304 \ncallq 10f0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 0C8h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+0E8h+var_30], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"\\\\w+ly\"\ncall _regcomp\ntest eax, eax\njnz loc_1345\nlea rcx, [rsp+0E8h+pmatch]; pmatch\nmov rdi, rsp; preg\nmov r8d, 0; eflags\nmov edx, 1; nmatch\nmov rsi, rbx; string\ncall _regexec\ntest eax, eax\njnz loc_1358\nmov r12d, [rsp+0E8h+pmatch.rm_so]\nmov r13d, [rsp+0E8h+pmatch.rm_eo]\nmov ebp, r13d\nsub ebp, r12d\nmovsxd rbp, ebp\nmovsxd rax, r12d\nlea rsi, [rbx+rax]\nlea rbx, [rsp+0E8h+var_98]\nmov ecx, 64h ; 'd'\nmov rdx, rbp\nmov rdi, rbx\ncall ___strncpy_chk\nmov [rsp+rbp+0E8h+var_98], 0\npush rbx\npush r13\nmov r9d, r12d\nlea r8, aDDS; \"%d-%d: %s\"\nmov ecx, 64h ; 'd'\nmov edx, 2\nmov esi, 64h ; 'd'\nlea rbx, result_1\nmov rdi, rbx\nmov eax, 0\ncall ___snprintf_chk\nlea rdi, [rsp+0F8h+preg]; preg\ncall _regfree\nadd rsp, 10h\nmov rax, rbx\nloc_1324:\nmov rdx, [rsp+0E8h+var_30]\nsub rdx, fs:28h\njnz short loc_1367\nadd rsp, 0C8h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1345:\nlea rdi, s; \"Could not compile regex\"\ncall _puts\nmov eax, 0\njmp short loc_1324\nloc_1358:\nmov rdi, rsp; preg\ncall _regfree\nmov eax, 0\njmp short loc_1324\nloc_1367:\ncall ___stack_chk_fail", + "ida_pseudo": "void *__fastcall func0(char *string)\n{\n regoff_t rm_so; // r12d\n regoff_t rm_eo; // r13d\n __int64 v3; // rbp\n regex_t preg; // [rsp+0h] [rbp-E8h] BYREF\n regmatch_t pmatch; // [rsp+48h] [rbp-A0h] BYREF\n char v7[104]; // [rsp+50h] [rbp-98h] BYREF\n unsigned __int64 v8; // [rsp+B8h] [rbp-30h]\n\n v8 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"\\\\w+ly\", 1) )\n {\n puts(\"Could not compile regex\");\n return 0LL;\n }\n else if ( regexec(&preg, string, 1uLL, &pmatch, 0) )\n {\n regfree(&preg);\n return 0LL;\n }\n else\n {\n rm_so = pmatch.rm_so;\n rm_eo = pmatch.rm_eo;\n v3 = pmatch.rm_eo - pmatch.rm_so;\n __strncpy_chk(v7, &string[pmatch.rm_so], v3, 100LL);\n v7[v3] = 0;\n __snprintf_chk(&result_1, 100LL, 2LL, 100LL, \"%d-%d: %s\", rm_so, rm_eo, v7);\n regfree(&preg);\n return &result_1;\n }\n}", + "ida_strip_asm": "sub_1249:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 0C8h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+0E8h+var_30], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"\\\\w+ly\"\ncall _regcomp\ntest eax, eax\njnz loc_1345\nlea rcx, [rsp+0E8h+pmatch]; pmatch\nmov rdi, rsp; preg\nmov r8d, 0; eflags\nmov edx, 1; nmatch\nmov rsi, rbx; string\ncall _regexec\ntest eax, eax\njnz loc_1358\nmov r12d, [rsp+0E8h+pmatch.rm_so]\nmov r13d, [rsp+0E8h+pmatch.rm_eo]\nmov ebp, r13d\nsub ebp, r12d\nmovsxd rbp, ebp\nmovsxd rax, r12d\nlea rsi, [rbx+rax]\nlea rbx, [rsp+0E8h+var_98]\nmov ecx, 64h ; 'd'\nmov rdx, rbp\nmov rdi, rbx\ncall ___strncpy_chk\nmov [rsp+rbp+0E8h+var_98], 0\npush rbx\npush r13\nmov r9d, r12d\nlea r8, aDDS; \"%d-%d: %s\"\nmov ecx, 64h ; 'd'\nmov edx, 2\nmov esi, 64h ; 'd'\nlea rbx, unk_4040\nmov rdi, rbx\nmov eax, 0\ncall ___snprintf_chk\nlea rdi, [rsp+0F8h+preg]; preg\ncall _regfree\nadd rsp, 10h\nmov rax, rbx\nloc_1324:\nmov rdx, [rsp+0E8h+var_30]\nsub rdx, fs:28h\njnz short loc_1367\nadd rsp, 0C8h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1345:\nlea rdi, s; \"Could not compile regex\"\ncall _puts\nmov eax, 0\njmp short loc_1324\nloc_1358:\nmov rdi, rsp; preg\ncall _regfree\nmov eax, 0\njmp short loc_1324\nloc_1367:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "void *__fastcall sub_1249(char *string)\n{\n regoff_t rm_so; // r12d\n regoff_t rm_eo; // r13d\n __int64 v3; // rbp\n regex_t preg; // [rsp+0h] [rbp-E8h] BYREF\n regmatch_t pmatch; // [rsp+48h] [rbp-A0h] BYREF\n char v7[104]; // [rsp+50h] [rbp-98h] BYREF\n unsigned __int64 v8; // [rsp+B8h] [rbp-30h]\n\n v8 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"\\\\w+ly\", 1) )\n {\n puts(\"Could not compile regex\");\n return 0LL;\n }\n else if ( regexec(&preg, string, 1uLL, &pmatch, 0) )\n {\n regfree(&preg);\n return 0LL;\n }\n else\n {\n rm_so = pmatch.rm_so;\n rm_eo = pmatch.rm_eo;\n v3 = pmatch.rm_eo - pmatch.rm_so;\n __strncpy_chk(v7, &string[pmatch.rm_so], v3, 100LL);\n v7[v3] = 0;\n __snprintf_chk(&unk_4040, 100LL, 2LL, 100LL, \"%d-%d: %s\", rm_so, rm_eo, v7);\n regfree(&preg);\n return &unk_4040;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1249(char *string) {\n regoff_t rm_so;\n regoff_t rm_eo;\n long long v3;\n regex_t preg;\n regmatch_t pmatch;\n char v7[104];\n unsigned long long v8;\n v8 = __readfsqword(40u);\n if (regcomp(&preg, \"\\\\w+ly\", 1)) {\n puts(\"Could not compile regex\");\n return 0LL;\n } else if (regexec(&preg, string, 1uLL, &pmatch, 0)) {\n regfree(&preg);\n return 0LL;\n } else {\n rm_so = pmatch.rm_so;\n rm_eo = pmatch.rm_eo;\n v3 = pmatch.rm_eo - pmatch.rm_so;\n __strncpy_chk(v7, &string[pmatch.rm_so], v3, 100LL);\n v7[v3] = 0;\n __snprintf_chk(&unk_4040, 100LL, 2LL, 100LL, \"%d-%d: %s\", rm_so, rm_eo, v7);\n regfree(&preg);\n return &unk_4040;\n }\n}", + "ida_pseudo_norm": "void *func0(char *string) {\n regoff_t rm_so;\n regoff_t rm_eo;\n long long v3;\n regex_t preg;\n regmatch_t pmatch;\n char v7[104];\n unsigned long long v8;\n v8 = __readfsqword(40u);\n if (regcomp(&preg, \"\\\\w+ly\", 1)) {\n puts(\"Could not compile regex\");\n return 0LL;\n } else if (regexec(&preg, string, 1uLL, &pmatch, 0)) {\n regfree(&preg);\n return 0LL;\n } else {\n rm_so = pmatch.rm_so;\n rm_eo = pmatch.rm_eo;\n v3 = pmatch.rm_eo - pmatch.rm_so;\n __strncpy_chk(v7, &string[pmatch.rm_so], v3, 100LL);\n v7[v3] = 0;\n __snprintf_chk(&result_1, 100LL, 2LL, 100LL, \"%d-%d: %s\", rm_so, rm_eo, v7);\n regfree(&preg);\n return &result_1;\n }\n}" + }, + { + "index": 584, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n regex_t regex;\n regmatch_t match[1];\n static char result[100];\n if (regcomp(®ex, \"\\\\w+ly\", REG_EXTENDED) != 0) {\n printf(\"Could not compile regex\\n\");\n return NULL;\n }\n if (regexec(®ex, text, 1, match, 0) == 0) {\n int start = match[0].rm_so;\n int end = match[0].rm_eo;\n char word[100];\n strncpy(word, text + start, end - start);\n word[end - start] = '\\0';\n snprintf(result, sizeof(result), \"%d-%d: %s\", start, end, word);\n regfree(®ex);\n return result;\n }\n regfree(®ex);\n return NULL;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"Clearly, he has no excuse for such behavior.\"), \"0-7: Clearly\") == 0);\n\n assert(strcmp(func0(\"Please handle the situation carefuly\"), \"28-36: carefuly\") == 0);\n\n assert(strcmp(func0(\"Complete the task quickly\"), \"18-25: quickly\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\nmov $0x1,%edx\nlea 0xce2(%rip),%rsi\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nsub $0xc0,%rsp\nmov %fs:0x28,%rax\nmov %rax,0xb8(%rsp)\nxor %eax,%eax\nmov %rsp,%rbp\nmov %rbp,%rdi\ncallq 1110 \ntest %eax,%eax\njne 1420 \nxor %r8d,%r8d\nlea 0x48(%rsp),%rcx\nmov $0x1,%edx\nmov %rbx,%rsi\nmov %rbp,%rdi\ncallq 1120 \ntest %eax,%eax\njne 1410 \nmov 0x4c(%rsp),%r14d\nmovslq 0x48(%rsp),%rsi\nlea 0x50(%rsp),%rdi\nmov $0x64,%ecx\nmov %r14d,%r12d\nmov %rsi,%r13\nsub %esi,%r12d\nadd %rbx,%rsi\nmovslq %r12d,%r12\nmov %r12,%rdx\ncallq 1130 <__strncpy_chk@plt>\nmovb $0x0,0x50(%rsp,%r12,1)\nmov %r13d,%r9d\nmov $0x1,%edx\npush %rax\nlea 0xc69(%rip),%r8\nxor %eax,%eax\nmov $0x64,%ecx\npush %r14\nmov $0x64,%esi\nlea 0x2c72(%rip),%rdi\ncallq 10c0 <__snprintf_chk@plt>\nmov %rbp,%rdi\ncallq 10e0 \npop %rax\nlea 0x2c5d(%rip),%rax\npop %rdx\nmov 0xb8(%rsp),%rbx\nxor %fs:0x28,%rbx\njne 1430 \nadd $0xc0,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopw 0x0(%rax,%rax,1)\nmov %rbp,%rdi\ncallq 10e0 \nxor %eax,%eax\njmp 13e4 \nnopl 0x0(%rax)\nlea 0xbe3(%rip),%rdi\ncallq 10d0 \nxor %eax,%eax\njmp 13e4 \ncallq 10f0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\nmov edx, 1; cflags\nlea rsi, pattern; \"\\\\w+ly\"\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 0C0h\nmov rax, fs:28h\nmov [rsp+var_sB8], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njnz loc_1430\nxor r8d, r8d; eflags\nlea rcx, [rsp+pmatch]; pmatch\nmov edx, 1; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\ntest eax, eax\njnz loc_1420\nmov r14d, [rsp+pmatch.rm_eo]\nmovsxd rax, [rsp+pmatch.rm_so]\nlea rdi, [rsp+var_s50]\nmov ecx, 64h ; 'd'\nmov r12d, r14d\nlea rsi, [rbx+rax]\nmov r13, rax\nsub r12d, eax\nlea rbx, result_1\nmovsxd r12, r12d\nmov rdx, r12\ncall ___strncpy_chk\nmov edx, 2\nmov r9d, r13d\nmov rdi, rbx\nmov [rsp+r12+var_s50], 0\nmov ecx, 64h ; 'd'\nmov esi, 64h ; 'd'\nlea r8, aDDS; \"%d-%d: %s\"\npush rax\nxor eax, eax\npush r14\ncall ___snprintf_chk\nmov rdi, rbp; preg\ncall _regfree\npop rax\nmov rax, rbx\npop rdx\nloc_13F4:\nmov rdx, [rsp+var_sB8]\nsub rdx, fs:28h\njnz short loc_1440\nadd rsp, 0C0h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1420:\nmov rdi, rbp; preg\ncall _regfree\nxor eax, eax\njmp short loc_13F4\nloc_1430:\nlea rdi, s; \"Could not compile regex\"\ncall _puts\nxor eax, eax\njmp short loc_13F4\nloc_1440:\ncall ___stack_chk_fail", + "ida_pseudo": "void *__fastcall func0(char *string)\n{\n regoff_t rm_eo; // r14d\n regoff_t rm_so; // r13d\n __int64 v3; // r12\n const char *v4; // rax\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n regmatch_t pmatch; // [rsp+48h] [rbp+48h] BYREF\n _BYTE vars50[104]; // [rsp+50h] [rbp+50h] BYREF\n unsigned __int64 varsB8; // [rsp+B8h] [rbp+B8h]\n\n varsB8 = __readfsqword(0x28u);\n if ( regcomp(&_0, \"\\\\w+ly\", 1) )\n {\n puts(\"Could not compile regex\");\n return 0LL;\n }\n else if ( regexec(&_0, string, 1uLL, &pmatch, 0) )\n {\n regfree(&_0);\n return 0LL;\n }\n else\n {\n rm_eo = pmatch.rm_eo;\n rm_so = pmatch.rm_so;\n v3 = pmatch.rm_eo - pmatch.rm_so;\n v4 = (const char *)__strncpy_chk(vars50, &string[pmatch.rm_so], v3, 100LL);\n vars50[v3] = 0;\n __snprintf_chk(&result_1, 100LL, 2LL, 100LL, \"%d-%d: %s\", rm_so, rm_eo, v4);\n regfree(&_0);\n return &result_1;\n }\n}", + "ida_strip_asm": "sub_1320:\nendbr64\npush r14\nmov edx, 1; cflags\nlea rsi, pattern; \"\\\\w+ly\"\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 0C0h\nmov rax, fs:28h\nmov [rsp+var_sB8], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njnz loc_1430\nxor r8d, r8d; eflags\nlea rcx, [rsp+pmatch]; pmatch\nmov edx, 1; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\ntest eax, eax\njnz loc_1420\nmov r14d, [rsp+pmatch.rm_eo]\nmovsxd rax, [rsp+pmatch.rm_so]\nlea rdi, [rsp+var_s50]\nmov ecx, 64h ; 'd'\nmov r12d, r14d\nlea rsi, [rbx+rax]\nmov r13, rax\nsub r12d, eax\nlea rbx, unk_4040\nmovsxd r12, r12d\nmov rdx, r12\ncall ___strncpy_chk\nmov edx, 2\nmov r9d, r13d\nmov rdi, rbx\nmov [rsp+r12+var_s50], 0\nmov ecx, 64h ; 'd'\nmov esi, 64h ; 'd'\nlea r8, aDDS; \"%d-%d: %s\"\npush rax\nxor eax, eax\npush r14\ncall ___snprintf_chk\nmov rdi, rbp; preg\ncall _regfree\npop rax\nmov rax, rbx\npop rdx\nloc_13F4:\nmov rdx, [rsp+var_sB8]\nsub rdx, fs:28h\njnz short loc_1440\nadd rsp, 0C0h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1420:\nmov rdi, rbp; preg\ncall _regfree\nxor eax, eax\njmp short loc_13F4\nloc_1430:\nlea rdi, s; \"Could not compile regex\"\ncall _puts\nxor eax, eax\njmp short loc_13F4\nloc_1440:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "void *__fastcall sub_1320(char *string)\n{\n regoff_t rm_eo; // r14d\n regoff_t rm_so; // r13d\n __int64 v3; // r12\n const char *v4; // rax\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n regmatch_t pmatch; // [rsp+48h] [rbp+48h] BYREF\n _BYTE vars50[104]; // [rsp+50h] [rbp+50h] BYREF\n unsigned __int64 varsB8; // [rsp+B8h] [rbp+B8h]\n\n varsB8 = __readfsqword(0x28u);\n if ( regcomp(&_0, \"\\\\w+ly\", 1) )\n {\n puts(\"Could not compile regex\");\n return 0LL;\n }\n else if ( regexec(&_0, string, 1uLL, &pmatch, 0) )\n {\n regfree(&_0);\n return 0LL;\n }\n else\n {\n rm_eo = pmatch.rm_eo;\n rm_so = pmatch.rm_so;\n v3 = pmatch.rm_eo - pmatch.rm_so;\n v4 = (const char *)__strncpy_chk(vars50, &string[pmatch.rm_so], v3, 100LL);\n vars50[v3] = 0;\n __snprintf_chk(&unk_4040, 100LL, 2LL, 100LL, \"%d-%d: %s\", rm_so, rm_eo, v4);\n regfree(&_0);\n return &unk_4040;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1320(char *string) {\n regoff_t rm_eo;\n regoff_t rm_so;\n long long v3;\n const char *v4;\n regex_t _0;\n regmatch_t pmatch;\n uint8_t vars50[104];\n unsigned long long varsB8;\n varsB8 = __readfsqword(40u);\n if (regcomp(&_0, \"\\\\w+ly\", 1)) {\n puts(\"Could not compile regex\");\n return 0LL;\n } else if (regexec(&_0, string, 1uLL, &pmatch, 0)) {\n regfree(&_0);\n return 0LL;\n } else {\n rm_eo = pmatch.rm_eo;\n rm_so = pmatch.rm_so;\n v3 = pmatch.rm_eo - pmatch.rm_so;\n v4 = (const char *)__strncpy_chk(vars50, &string[pmatch.rm_so], v3, 100LL);\n vars50[v3] = 0;\n __snprintf_chk(&unk_4040, 100LL, 2LL, 100LL, \"%d-%d: %s\", rm_so, rm_eo, v4);\n regfree(&_0);\n return &unk_4040;\n }\n}", + "ida_pseudo_norm": "void *func0(char *string) {\n regoff_t rm_eo;\n regoff_t rm_so;\n long long v3;\n const char *v4;\n regex_t _0;\n regmatch_t pmatch;\n uint8_t vars50[104];\n unsigned long long varsB8;\n varsB8 = __readfsqword(40u);\n if (regcomp(&_0, \"\\\\w+ly\", 1)) {\n puts(\"Could not compile regex\");\n return 0LL;\n } else if (regexec(&_0, string, 1uLL, &pmatch, 0)) {\n regfree(&_0);\n return 0LL;\n } else {\n rm_eo = pmatch.rm_eo;\n rm_so = pmatch.rm_so;\n v3 = pmatch.rm_eo - pmatch.rm_so;\n v4 = (const char *)__strncpy_chk(vars50, &string[pmatch.rm_so], v3, 100LL);\n vars50[v3] = 0;\n __snprintf_chk(&result_1, 100LL, 2LL, 100LL, \"%d-%d: %s\", rm_so, rm_eo, v4);\n regfree(&_0);\n return &result_1;\n }\n}" + }, + { + "index": 584, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n regex_t regex;\n regmatch_t match[1];\n static char result[100];\n if (regcomp(®ex, \"\\\\w+ly\", REG_EXTENDED) != 0) {\n printf(\"Could not compile regex\\n\");\n return NULL;\n }\n if (regexec(®ex, text, 1, match, 0) == 0) {\n int start = match[0].rm_so;\n int end = match[0].rm_eo;\n char word[100];\n strncpy(word, text + start, end - start);\n word[end - start] = '\\0';\n snprintf(result, sizeof(result), \"%d-%d: %s\", start, end, word);\n regfree(®ex);\n return result;\n }\n regfree(®ex);\n return NULL;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"Clearly, he has no excuse for such behavior.\"), \"0-7: Clearly\") == 0);\n\n assert(strcmp(func0(\"Please handle the situation carefuly\"), \"28-36: carefuly\") == 0);\n\n assert(strcmp(func0(\"Complete the task quickly\"), \"18-25: quickly\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\nmov $0x1,%edx\nlea 0xce2(%rip),%rsi\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nsub $0xc0,%rsp\nmov %fs:0x28,%rax\nmov %rax,0xb8(%rsp)\nxor %eax,%eax\nmov %rsp,%rbp\nmov %rbp,%rdi\ncallq 1110 \ntest %eax,%eax\njne 1420 \nxor %r8d,%r8d\nlea 0x48(%rsp),%rcx\nmov $0x1,%edx\nmov %rbx,%rsi\nmov %rbp,%rdi\ncallq 1120 \ntest %eax,%eax\njne 1410 \nmov 0x4c(%rsp),%r14d\nmovslq 0x48(%rsp),%rsi\nlea 0x50(%rsp),%rdi\nmov $0x64,%ecx\nmov %r14d,%r12d\nmov %rsi,%r13\nsub %esi,%r12d\nadd %rbx,%rsi\nmovslq %r12d,%r12\nmov %r12,%rdx\ncallq 1130 <__strncpy_chk@plt>\nmovb $0x0,0x50(%rsp,%r12,1)\nmov %r13d,%r9d\nmov $0x1,%edx\npush %rax\nlea 0xc69(%rip),%r8\nxor %eax,%eax\nmov $0x64,%ecx\npush %r14\nmov $0x64,%esi\nlea 0x2c72(%rip),%rdi\ncallq 10c0 <__snprintf_chk@plt>\nmov %rbp,%rdi\ncallq 10e0 \npop %rax\nlea 0x2c5d(%rip),%rax\npop %rdx\nmov 0xb8(%rsp),%rbx\nxor %fs:0x28,%rbx\njne 1430 \nadd $0xc0,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopw 0x0(%rax,%rax,1)\nmov %rbp,%rdi\ncallq 10e0 \nxor %eax,%eax\njmp 13e4 \nnopl 0x0(%rax)\nlea 0xbe3(%rip),%rdi\ncallq 10d0 \nxor %eax,%eax\njmp 13e4 \ncallq 10f0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\nmov edx, 1; cflags\nlea rsi, pattern; \"\\\\w+ly\"\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 0C0h\nmov rax, fs:28h\nmov [rsp+var_sB8], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njnz loc_1430\nxor r8d, r8d; eflags\nlea rcx, [rsp+pmatch]; pmatch\nmov edx, 1; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\ntest eax, eax\njnz loc_1420\nmov r14d, [rsp+pmatch.rm_eo]\nmovsxd rax, [rsp+pmatch.rm_so]\nlea rdi, [rsp+var_s50]\nmov ecx, 64h ; 'd'\nmov r12d, r14d\nlea rsi, [rbx+rax]\nmov r13, rax\nsub r12d, eax\nlea rbx, result_1\nmovsxd r12, r12d\nmov rdx, r12\ncall ___strncpy_chk\nmov edx, 2\nmov r9d, r13d\nmov rdi, rbx\nmov [rsp+r12+var_s50], 0\nmov ecx, 64h ; 'd'\nmov esi, 64h ; 'd'\nlea r8, aDDS; \"%d-%d: %s\"\npush rax\nxor eax, eax\npush r14\ncall ___snprintf_chk\nmov rdi, rbp; preg\ncall _regfree\npop rax\nmov rax, rbx\npop rdx\nloc_13F4:\nmov rdx, [rsp+var_sB8]\nsub rdx, fs:28h\njnz short loc_1440\nadd rsp, 0C0h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1420:\nmov rdi, rbp; preg\ncall _regfree\nxor eax, eax\njmp short loc_13F4\nloc_1430:\nlea rdi, s; \"Could not compile regex\"\ncall _puts\nxor eax, eax\njmp short loc_13F4\nloc_1440:\ncall ___stack_chk_fail", + "ida_pseudo": "void *__fastcall func0(char *string)\n{\n regoff_t rm_eo; // r14d\n regoff_t rm_so; // r13d\n __int64 v3; // r12\n const char *v4; // rax\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n regmatch_t pmatch; // [rsp+48h] [rbp+48h] BYREF\n _BYTE vars50[104]; // [rsp+50h] [rbp+50h] BYREF\n unsigned __int64 varsB8; // [rsp+B8h] [rbp+B8h]\n\n varsB8 = __readfsqword(0x28u);\n if ( regcomp(&_0, \"\\\\w+ly\", 1) )\n {\n puts(\"Could not compile regex\");\n return 0LL;\n }\n else if ( regexec(&_0, string, 1uLL, &pmatch, 0) )\n {\n regfree(&_0);\n return 0LL;\n }\n else\n {\n rm_eo = pmatch.rm_eo;\n rm_so = pmatch.rm_so;\n v3 = pmatch.rm_eo - pmatch.rm_so;\n v4 = (const char *)__strncpy_chk(vars50, &string[pmatch.rm_so], v3, 100LL);\n vars50[v3] = 0;\n __snprintf_chk(&result_1, 100LL, 2LL, 100LL, \"%d-%d: %s\", rm_so, rm_eo, v4);\n regfree(&_0);\n return &result_1;\n }\n}", + "ida_strip_asm": "sub_1320:\nendbr64\npush r14\nmov edx, 1; cflags\nlea rsi, pattern; \"\\\\w+ly\"\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 0C0h\nmov rax, fs:28h\nmov [rsp+var_sB8], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njnz loc_1430\nxor r8d, r8d; eflags\nlea rcx, [rsp+pmatch]; pmatch\nmov edx, 1; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\ntest eax, eax\njnz loc_1420\nmov r14d, [rsp+pmatch.rm_eo]\nmovsxd rax, [rsp+pmatch.rm_so]\nlea rdi, [rsp+var_s50]\nmov ecx, 64h ; 'd'\nmov r12d, r14d\nlea rsi, [rbx+rax]\nmov r13, rax\nsub r12d, eax\nlea rbx, unk_4040\nmovsxd r12, r12d\nmov rdx, r12\ncall ___strncpy_chk\nmov edx, 2\nmov r9d, r13d\nmov rdi, rbx\nmov [rsp+r12+var_s50], 0\nmov ecx, 64h ; 'd'\nmov esi, 64h ; 'd'\nlea r8, aDDS; \"%d-%d: %s\"\npush rax\nxor eax, eax\npush r14\ncall ___snprintf_chk\nmov rdi, rbp; preg\ncall _regfree\npop rax\nmov rax, rbx\npop rdx\nloc_13F4:\nmov rdx, [rsp+var_sB8]\nsub rdx, fs:28h\njnz short loc_1440\nadd rsp, 0C0h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1420:\nmov rdi, rbp; preg\ncall _regfree\nxor eax, eax\njmp short loc_13F4\nloc_1430:\nlea rdi, s; \"Could not compile regex\"\ncall _puts\nxor eax, eax\njmp short loc_13F4\nloc_1440:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "void *__fastcall sub_1320(char *string)\n{\n regoff_t rm_eo; // r14d\n regoff_t rm_so; // r13d\n __int64 v3; // r12\n const char *v4; // rax\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n regmatch_t pmatch; // [rsp+48h] [rbp+48h] BYREF\n _BYTE vars50[104]; // [rsp+50h] [rbp+50h] BYREF\n unsigned __int64 varsB8; // [rsp+B8h] [rbp+B8h]\n\n varsB8 = __readfsqword(0x28u);\n if ( regcomp(&_0, \"\\\\w+ly\", 1) )\n {\n puts(\"Could not compile regex\");\n return 0LL;\n }\n else if ( regexec(&_0, string, 1uLL, &pmatch, 0) )\n {\n regfree(&_0);\n return 0LL;\n }\n else\n {\n rm_eo = pmatch.rm_eo;\n rm_so = pmatch.rm_so;\n v3 = pmatch.rm_eo - pmatch.rm_so;\n v4 = (const char *)__strncpy_chk(vars50, &string[pmatch.rm_so], v3, 100LL);\n vars50[v3] = 0;\n __snprintf_chk(&unk_4040, 100LL, 2LL, 100LL, \"%d-%d: %s\", rm_so, rm_eo, v4);\n regfree(&_0);\n return &unk_4040;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1320(char *string) {\n regoff_t rm_eo;\n regoff_t rm_so;\n long long v3;\n const char *v4;\n regex_t _0;\n regmatch_t pmatch;\n uint8_t vars50[104];\n unsigned long long varsB8;\n varsB8 = __readfsqword(40u);\n if (regcomp(&_0, \"\\\\w+ly\", 1)) {\n puts(\"Could not compile regex\");\n return 0LL;\n } else if (regexec(&_0, string, 1uLL, &pmatch, 0)) {\n regfree(&_0);\n return 0LL;\n } else {\n rm_eo = pmatch.rm_eo;\n rm_so = pmatch.rm_so;\n v3 = pmatch.rm_eo - pmatch.rm_so;\n v4 = (const char *)__strncpy_chk(vars50, &string[pmatch.rm_so], v3, 100LL);\n vars50[v3] = 0;\n __snprintf_chk(&unk_4040, 100LL, 2LL, 100LL, \"%d-%d: %s\", rm_so, rm_eo, v4);\n regfree(&_0);\n return &unk_4040;\n }\n}", + "ida_pseudo_norm": "void *func0(char *string) {\n regoff_t rm_eo;\n regoff_t rm_so;\n long long v3;\n const char *v4;\n regex_t _0;\n regmatch_t pmatch;\n uint8_t vars50[104];\n unsigned long long varsB8;\n varsB8 = __readfsqword(40u);\n if (regcomp(&_0, \"\\\\w+ly\", 1)) {\n puts(\"Could not compile regex\");\n return 0LL;\n } else if (regexec(&_0, string, 1uLL, &pmatch, 0)) {\n regfree(&_0);\n return 0LL;\n } else {\n rm_eo = pmatch.rm_eo;\n rm_so = pmatch.rm_so;\n v3 = pmatch.rm_eo - pmatch.rm_so;\n v4 = (const char *)__strncpy_chk(vars50, &string[pmatch.rm_so], v3, 100LL);\n vars50[v3] = 0;\n __snprintf_chk(&result_1, 100LL, 2LL, 100LL, \"%d-%d: %s\", rm_so, rm_eo, v4);\n regfree(&_0);\n return &result_1;\n }\n}" + }, + { + "index": 585, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char name[20];\n\n double price;\n\n} Item;\n\n\n\nint compare(const void *a, const void *b) {\n\n Item *itemA = (Item*)a;\n\n Item *itemB = (Item*)b;\n\n if (itemB->price > itemA->price) {\n\n return 1;\n\n } else if (itemB->price < itemA->price) {\n\n return -1;\n\n } else {\n\n return 0;\n\n }\n\n}\n\n\n\n", + "func": "Item* func0(Item items[], int total_items, int n) {\n qsort(items, total_items, sizeof(Item), compare);\n Item* expensiveItems = malloc(n * sizeof(Item));\n for (int i = 0; i < n; i++) {\n expensiveItems[i] = items[i];\n }\n return expensiveItems;\n}", + "test": "int main() {\n\n Item items1[] = {{.name = \"Item-1\", .price = 101.1}, {.name = \"Item-2\", .price = 555.22}};\n\n Item items2[] = {{.name = \"Item-1\", .price = 101.1}, {.name = \"Item-2\", .price = 555.22}, {.name = \"Item-3\", .price = 45.09}};\n\n Item items3[] = {{.name = \"Item-1\", .price = 101.1}, {.name = \"Item-2\", .price = 555.22}, {.name = \"Item-3\", .price = 45.09}, {.name = \"Item-4\", .price = 22.75}};\n\n \n\n Item *result;\n\n\n\n result = func0(items1, 2, 1);\n\n assert(result[0].price == 555.22);\n\n \n\n result = func0(items2, 3, 2);\n\n assert(result[0].price == 555.22 && result[1].price == 101.1);\n\n \n\n result = func0(items3, 4, 1);\n\n assert(result[0].price == 555.22);\n\n \n\n free(result);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmov -0x1c(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x18(%rbp),%rax\nlea -0x8c(%rip),%rcx\nmov $0x20,%edx\nmov %rax,%rdi\ncallq 10a0 \nmov -0x20(%rbp),%eax\ncltq\nshl $0x5,%rax\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 12ca \nmov -0xc(%rbp),%eax\ncltq\nshl $0x5,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rsi\nmov -0xc(%rbp),%eax\ncltq\nshl $0x5,%rax\nmov %rax,%rdx\nmov -0x8(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov (%rsi),%rax\nmov 0x8(%rsi),%rdx\nmov %rax,(%rcx)\nmov %rdx,0x8(%rcx)\nmov 0x10(%rsi),%rax\nmov 0x18(%rsi),%rdx\nmov %rax,0x10(%rcx)\nmov %rdx,0x18(%rcx)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x20(%rbp),%eax\njl 1280 \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+base], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov eax, [rbp+var_1C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compare\nmov rcx, rdx; compar\nmov edx, 20h ; ' '; size\nmov rdi, rax; base\ncall _qsort\nmov eax, [rbp+var_20]\ncdqe\nshl rax, 5\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp short loc_12CD\nloc_1283:\nmov eax, [rbp+var_C]\ncdqe\nshl rax, 5\nmov rdx, rax\nmov rax, [rbp+base]\nlea rsi, [rdx+rax]\nmov eax, [rbp+var_C]\ncdqe\nshl rax, 5\nmov rdx, rax\nmov rax, [rbp+var_8]\nlea rcx, [rdx+rax]\nmov rax, [rsi]\nmov rdx, [rsi+8]\nmov [rcx], rax\nmov [rcx+8], rdx\nmov rax, [rsi+10h]\nmov rdx, [rsi+18h]\nmov [rcx+10h], rax\nmov [rcx+18h], rdx\nadd [rbp+var_C], 1\nloc_12CD:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_20]\njl short loc_1283\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(char *a1, int a2, int a3)\n{\n char *v3; // rsi\n char *v4; // rcx\n __int64 v5; // rdx\n __int64 v6; // rdx\n int i; // [rsp+14h] [rbp-Ch]\n char *v10; // [rsp+18h] [rbp-8h]\n\n qsort(a1, a2, 0x20uLL, compare);\n v10 = (char *)malloc(32LL * a3);\n for ( i = 0; i < a3; ++i )\n {\n v3 = &a1[32 * i];\n v4 = &v10[32 * i];\n v5 = *((_QWORD *)v3 + 1);\n *(_QWORD *)v4 = *(_QWORD *)v3;\n *((_QWORD *)v4 + 1) = v5;\n v6 = *((_QWORD *)v3 + 3);\n *((_QWORD *)v4 + 2) = *((_QWORD *)v3 + 2);\n *((_QWORD *)v4 + 3) = v6;\n }\n return v10;\n}", + "ida_strip_asm": "sub_122E:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+base], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov eax, [rbp+var_1C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 20h ; ' '; size\nmov rdi, rax; base\ncall _qsort\nmov eax, [rbp+var_20]\ncdqe\nshl rax, 5\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp short loc_12CD\nloc_1283:\nmov eax, [rbp+var_C]\ncdqe\nshl rax, 5\nmov rdx, rax\nmov rax, [rbp+base]\nlea rsi, [rdx+rax]\nmov eax, [rbp+var_C]\ncdqe\nshl rax, 5\nmov rdx, rax\nmov rax, [rbp+var_8]\nlea rcx, [rdx+rax]\nmov rax, [rsi]\nmov rdx, [rsi+8]\nmov [rcx], rax\nmov [rcx+8], rdx\nmov rax, [rsi+10h]\nmov rdx, [rsi+18h]\nmov [rcx+10h], rax\nmov [rcx+18h], rdx\nadd [rbp+var_C], 1\nloc_12CD:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_20]\njl short loc_1283\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_122E(char *a1, int a2, int a3)\n{\n char *v3; // rsi\n char *v4; // rcx\n __int64 v5; // rdx\n __int64 v6; // rdx\n int i; // [rsp+14h] [rbp-Ch]\n char *v10; // [rsp+18h] [rbp-8h]\n\n qsort(a1, a2, 0x20uLL, compar);\n v10 = (char *)malloc(32LL * a3);\n for ( i = 0; i < a3; ++i )\n {\n v3 = &a1[32 * i];\n v4 = &v10[32 * i];\n v5 = *((_QWORD *)v3 + 1);\n *(_QWORD *)v4 = *(_QWORD *)v3;\n *((_QWORD *)v4 + 1) = v5;\n v6 = *((_QWORD *)v3 + 3);\n *((_QWORD *)v4 + 2) = *((_QWORD *)v3 + 2);\n *((_QWORD *)v4 + 3) = v6;\n }\n return v10;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_122E(char *a1, int a2, int a3) {\n char *v3;\n char *v4;\n long long v5;\n long long v6;\n int i;\n char *v10;\n qsort(a1, a2, 32uLL, compar);\n v10 = (char *)malloc(32LL * a3);\n for (i = 0; i < a3; ++i) {\n v3 = &a1[32 * i];\n v4 = &v10[32 * i];\n v5 = *((uint64_t *)v3 + 1);\n *(uint64_t *)v4 = *(uint64_t *)v3;\n *((uint64_t *)v4 + 1) = v5;\n v6 = *((uint64_t *)v3 + 3);\n *((uint64_t *)v4 + 2) = *((uint64_t *)v3 + 2);\n *((uint64_t *)v4 + 3) = v6;\n }\n return v10;\n}", + "ida_pseudo_norm": "char *func0(char *a1, int a2, int a3) {\n char *v3;\n char *v4;\n long long v5;\n long long v6;\n int i;\n char *v10;\n qsort(a1, a2, 32uLL, compare);\n v10 = (char *)malloc(32LL * a3);\n for (i = 0; i < a3; ++i) {\n v3 = &a1[32 * i];\n v4 = &v10[32 * i];\n v5 = *((uint64_t *)v3 + 1);\n *(uint64_t *)v4 = *(uint64_t *)v3;\n *((uint64_t *)v4 + 1) = v5;\n v6 = *((uint64_t *)v3 + 3);\n *((uint64_t *)v4 + 2) = *((uint64_t *)v3 + 2);\n *((uint64_t *)v4 + 3) = v6;\n }\n return v10;\n}" + }, + { + "index": 585, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char name[20];\n\n double price;\n\n} Item;\n\n\n\nint compare(const void *a, const void *b) {\n\n Item *itemA = (Item*)a;\n\n Item *itemB = (Item*)b;\n\n if (itemB->price > itemA->price) {\n\n return 1;\n\n } else if (itemB->price < itemA->price) {\n\n return -1;\n\n } else {\n\n return 0;\n\n }\n\n}\n\n\n\n", + "func": "Item* func0(Item items[], int total_items, int n) {\n qsort(items, total_items, sizeof(Item), compare);\n Item* expensiveItems = malloc(n * sizeof(Item));\n for (int i = 0; i < n; i++) {\n expensiveItems[i] = items[i];\n }\n return expensiveItems;\n}", + "test": "int main() {\n\n Item items1[] = {{.name = \"Item-1\", .price = 101.1}, {.name = \"Item-2\", .price = 555.22}};\n\n Item items2[] = {{.name = \"Item-1\", .price = 101.1}, {.name = \"Item-2\", .price = 555.22}, {.name = \"Item-3\", .price = 45.09}};\n\n Item items3[] = {{.name = \"Item-1\", .price = 101.1}, {.name = \"Item-2\", .price = 555.22}, {.name = \"Item-3\", .price = 45.09}, {.name = \"Item-4\", .price = 22.75}};\n\n \n\n Item *result;\n\n\n\n result = func0(items1, 2, 1);\n\n assert(result[0].price == 555.22);\n\n \n\n result = func0(items2, 3, 2);\n\n assert(result[0].price == 555.22 && result[1].price == 101.1);\n\n \n\n result = func0(items3, 4, 1);\n\n assert(result[0].price == 555.22);\n\n \n\n free(result);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbx\nmov %edx,%ebp\nmovslq %esi,%rsi\nlea -0x3f(%rip),%rcx\nmov $0x20,%edx\ncallq 10a0 \nmovslq %ebp,%rdi\nshl $0x5,%rdi\ncallq 10d0 \ntest %ebp,%ebp\njle 124f \nlea -0x1(%rbp),%ecx\nadd $0x1,%rcx\nshl $0x5,%rcx\nmov $0x0,%edx\nmovdqu (%rbx,%rdx,1),%xmm0\nmovups %xmm0,(%rax,%rdx,1)\nmovdqu 0x10(%rbx,%rdx,1),%xmm1\nmovups %xmm1,0x10(%rax,%rdx,1)\nadd $0x20,%rdx\ncmp %rcx,%rdx\njne 1232 \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nmov r12d, edx\nmovsxd rsi, esi; nmemb\nlea rcx, compare; compar\nmov edx, 20h ; ' '; size\ncall _qsort\nmovsxd rbp, r12d\nshl rbp, 5\nmov rdi, rbp; size\ncall _malloc\ntest r12d, r12d\njle short loc_1247\nmov edx, 0\nloc_122A:\nmovdqu xmm0, xmmword ptr [rbx+rdx]\nmovups xmmword ptr [rax+rdx], xmm0\nmovdqu xmm1, xmmword ptr [rbx+rdx+10h]\nmovups xmmword ptr [rax+rdx+10h], xmm1\nadd rdx, 20h ; ' '\ncmp rbp, rdx\njnz short loc_122A\nloc_1247:\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "char *__fastcall func0(char *a1, int a2, int a3)\n{\n char *result; // rax\n __int64 v5; // rdx\n\n qsort(a1, a2, 0x20uLL, compare);\n result = (char *)malloc(32LL * a3);\n if ( a3 > 0 )\n {\n v5 = 0LL;\n do\n {\n *(__m128i *)&result[v5] = _mm_loadu_si128((const __m128i *)&a1[v5]);\n *(__m128i *)&result[v5 + 16] = _mm_loadu_si128((const __m128i *)&a1[v5 + 16]);\n v5 += 32LL;\n }\n while ( 32LL * a3 != v5 );\n }\n return result;\n}", + "ida_strip_asm": "sub_11EF:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nmov r12d, edx\nmovsxd rsi, esi; nmemb\nlea rcx, compar; compar\nmov edx, 20h ; ' '; size\ncall _qsort\nmovsxd rbp, r12d\nshl rbp, 5\nmov rdi, rbp; size\ncall _malloc\ntest r12d, r12d\njle short loc_1247\nmov edx, 0\nloc_122A:\nmovdqu xmm0, xmmword ptr [rbx+rdx]\nmovups xmmword ptr [rax+rdx], xmm0\nmovdqu xmm1, xmmword ptr [rbx+rdx+10h]\nmovups xmmword ptr [rax+rdx+10h], xmm1\nadd rdx, 20h ; ' '\ncmp rbp, rdx\njnz short loc_122A\nloc_1247:\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11EF(char *a1, int a2, int a3)\n{\n char *result; // rax\n __int64 v5; // rdx\n\n qsort(a1, a2, 0x20uLL, compar);\n result = (char *)malloc(32LL * a3);\n if ( a3 > 0 )\n {\n v5 = 0LL;\n do\n {\n *(__m128i *)&result[v5] = _mm_loadu_si128((const __m128i *)&a1[v5]);\n *(__m128i *)&result[v5 + 16] = _mm_loadu_si128((const __m128i *)&a1[v5 + 16]);\n v5 += 32LL;\n }\n while ( 32LL * a3 != v5 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11EF(char *a1, int a2, int a3) {\n char *result;\n long long v5;\n qsort(a1, a2, 32uLL, compar);\n result = (char *)malloc(32LL * a3);\n if (a3 > 0) {\n v5 = 0LL;\n do {\n *(__m128i *)&result[v5] = _mm_loadu_si128((const __m128i *)&a1[v5]);\n *(__m128i *)&result[v5 + 16] =\n _mm_loadu_si128((const __m128i *)&a1[v5 + 16]);\n v5 += 32LL;\n } while (32LL * a3 != v5);\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(char *a1, int a2, int a3) {\n char *result;\n long long v5;\n qsort(a1, a2, 32uLL, compare);\n result = (char *)malloc(32LL * a3);\n if (a3 > 0) {\n v5 = 0LL;\n do {\n *(__m128i *)&result[v5] = _mm_loadu_si128((const __m128i *)&a1[v5]);\n *(__m128i *)&result[v5 + 16] =\n _mm_loadu_si128((const __m128i *)&a1[v5 + 16]);\n v5 += 32LL;\n } while (32LL * a3 != v5);\n }\n return result;\n}" + }, + { + "index": 585, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char name[20];\n\n double price;\n\n} Item;\n\n\n\nint compare(const void *a, const void *b) {\n\n Item *itemA = (Item*)a;\n\n Item *itemB = (Item*)b;\n\n if (itemB->price > itemA->price) {\n\n return 1;\n\n } else if (itemB->price < itemA->price) {\n\n return -1;\n\n } else {\n\n return 0;\n\n }\n\n}\n\n\n\n", + "func": "Item* func0(Item items[], int total_items, int n) {\n qsort(items, total_items, sizeof(Item), compare);\n Item* expensiveItems = malloc(n * sizeof(Item));\n for (int i = 0; i < n; i++) {\n expensiveItems[i] = items[i];\n }\n return expensiveItems;\n}", + "test": "int main() {\n\n Item items1[] = {{.name = \"Item-1\", .price = 101.1}, {.name = \"Item-2\", .price = 555.22}};\n\n Item items2[] = {{.name = \"Item-1\", .price = 101.1}, {.name = \"Item-2\", .price = 555.22}, {.name = \"Item-3\", .price = 45.09}};\n\n Item items3[] = {{.name = \"Item-1\", .price = 101.1}, {.name = \"Item-2\", .price = 555.22}, {.name = \"Item-3\", .price = 45.09}, {.name = \"Item-4\", .price = 22.75}};\n\n \n\n Item *result;\n\n\n\n result = func0(items1, 2, 1);\n\n assert(result[0].price == 555.22);\n\n \n\n result = func0(items2, 3, 2);\n\n assert(result[0].price == 555.22 && result[1].price == 101.1);\n\n \n\n result = func0(items3, 4, 1);\n\n assert(result[0].price == 555.22);\n\n \n\n free(result);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmovslq %esi,%rsi\nmov %edx,%ebp\nlea -0x41(%rip),%rcx\npush %rbx\nmov $0x20,%edx\nmov %rdi,%rbx\nsub $0x8,%rsp\ncallq 10a0 \nmovslq %ebp,%rdi\nshl $0x5,%rdi\ncallq 10d0 \ntest %ebp,%ebp\njle 14fd \nlea -0x1(%rbp),%ecx\nxor %edx,%edx\nadd $0x1,%rcx\nshl $0x5,%rcx\nmovdqu (%rbx,%rdx,1),%xmm0\nmovdqu 0x10(%rbx,%rdx,1),%xmm1\nmovups %xmm0,(%rax,%rdx,1)\nmovups %xmm1,0x10(%rax,%rdx,1)\nadd $0x20,%rdx\ncmp %rcx,%rdx\njne 14e0 \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\nlea rcx, compare; compar\nmovsxd rsi, esi; nmemb\nmov rbp, rdi\npush rbx\nmov ebx, edx\nmov edx, 20h ; ' '; size\nsub rsp, 8\ncall _qsort\nmovsxd rdi, ebx\nshl rdi, 5; size\ncall _malloc\nmov rcx, rax\ntest ebx, ebx\njle short loc_150A\nmov edx, ebx\nmov rsi, rbp; src\nmov rdi, rax; dest\nshl rdx, 5; n\ncall _memcpy\nmov rcx, rax\nloc_150A:\nadd rsp, 8\nmov rax, rcx\npop rbx\npop rbp\nretn", + "ida_pseudo": "void *__fastcall func0(void *src, int a2, int a3)\n{\n void *v4; // rax\n void *v5; // rcx\n\n qsort(src, a2, 0x20uLL, compare);\n v4 = malloc(32LL * a3);\n v5 = v4;\n if ( a3 > 0 )\n return memcpy(v4, src, 32LL * (unsigned int)a3);\n return v5;\n}", + "ida_strip_asm": "sub_14C0:\nendbr64\npush rbp\nlea rcx, compar; compar\nmovsxd rsi, esi; nmemb\nmov rbp, rdi\npush rbx\nmov ebx, edx\nmov edx, 20h ; ' '; size\nsub rsp, 8\ncall _qsort\nmovsxd rdi, ebx\nshl rdi, 5; size\ncall _malloc\nmov rcx, rax\ntest ebx, ebx\njle short loc_150A\nmov edx, ebx\nmov rsi, rbp; src\nmov rdi, rax; dest\nshl rdx, 5; n\ncall _memcpy\nmov rcx, rax\nloc_150A:\nadd rsp, 8\nmov rax, rcx\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "void *__fastcall sub_14C0(void *src, int a2, int a3)\n{\n void *v4; // rax\n void *v5; // rcx\n\n qsort(src, a2, 0x20uLL, compar);\n v4 = malloc(32LL * a3);\n v5 = v4;\n if ( a3 > 0 )\n return memcpy(v4, src, 32LL * (unsigned int)a3);\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_14C0(void *src, int a2, int a3) {\n void *v4;\n void *v5;\n qsort(src, a2, 32uLL, compar);\n v4 = malloc(32LL * a3);\n v5 = v4;\n if (a3 > 0) return memcpy(v4, src, 32LL * (unsigned int)a3);\n return v5;\n}", + "ida_pseudo_norm": "void *func0(void *src, int a2, int a3) {\n void *v4;\n void *v5;\n qsort(src, a2, 32uLL, compare);\n v4 = malloc(32LL * a3);\n v5 = v4;\n if (a3 > 0) return memcpy(v4, src, 32LL * (unsigned int)a3);\n return v5;\n}" + }, + { + "index": 585, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char name[20];\n\n double price;\n\n} Item;\n\n\n\nint compare(const void *a, const void *b) {\n\n Item *itemA = (Item*)a;\n\n Item *itemB = (Item*)b;\n\n if (itemB->price > itemA->price) {\n\n return 1;\n\n } else if (itemB->price < itemA->price) {\n\n return -1;\n\n } else {\n\n return 0;\n\n }\n\n}\n\n\n\n", + "func": "Item* func0(Item items[], int total_items, int n) {\n qsort(items, total_items, sizeof(Item), compare);\n Item* expensiveItems = malloc(n * sizeof(Item));\n for (int i = 0; i < n; i++) {\n expensiveItems[i] = items[i];\n }\n return expensiveItems;\n}", + "test": "int main() {\n\n Item items1[] = {{.name = \"Item-1\", .price = 101.1}, {.name = \"Item-2\", .price = 555.22}};\n\n Item items2[] = {{.name = \"Item-1\", .price = 101.1}, {.name = \"Item-2\", .price = 555.22}, {.name = \"Item-3\", .price = 45.09}};\n\n Item items3[] = {{.name = \"Item-1\", .price = 101.1}, {.name = \"Item-2\", .price = 555.22}, {.name = \"Item-3\", .price = 45.09}, {.name = \"Item-4\", .price = 22.75}};\n\n \n\n Item *result;\n\n\n\n result = func0(items1, 2, 1);\n\n assert(result[0].price == 555.22);\n\n \n\n result = func0(items2, 3, 2);\n\n assert(result[0].price == 555.22 && result[1].price == 101.1);\n\n \n\n result = func0(items3, 4, 1);\n\n assert(result[0].price == 555.22);\n\n \n\n free(result);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmovslq %esi,%rsi\nlea -0x3f(%rip),%rcx\nmov %rdi,%rbp\npush %rbx\nmov %edx,%ebx\nmov $0x20,%edx\nsub $0x8,%rsp\ncallq 10b0 \nmovslq %ebx,%rdi\nshl $0x5,%rdi\ncallq 10f0 \nmov %rax,%r8\ntest %ebx,%ebx\njle 150f \nlea -0x1(%rbx),%edx\nmov %rbp,%rsi\nmov %rax,%rdi\nadd $0x1,%rdx\nshl $0x5,%rdx\ncallq 10e0 \nmov %rax,%r8\nadd $0x8,%rsp\nmov %r8,%rax\npop %rbx\npop %rbp\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nlea rcx, compare; compar\nmovsxd rsi, esi; nmemb\nmov rbp, rdi\npush rbx\nmov ebx, edx\nmov edx, 20h ; ' '; size\nsub rsp, 8\ncall _qsort\nmovsxd rdi, ebx\nshl rdi, 5; size\ncall _malloc\nmov rcx, rax\ntest ebx, ebx\njle short loc_150A\nmov edx, ebx\nmov rsi, rbp; src\nmov rdi, rax; dest\nshl rdx, 5; n\ncall _memcpy\nmov rcx, rax\nloc_150A:\nadd rsp, 8\nmov rax, rcx\npop rbx\npop rbp\nretn", + "ida_pseudo": "void *__fastcall func0(void *src, int a2, int a3)\n{\n void *v4; // rax\n void *v5; // rcx\n\n qsort(src, a2, 0x20uLL, compare);\n v4 = malloc(32LL * a3);\n v5 = v4;\n if ( a3 > 0 )\n return memcpy(v4, src, 32LL * (unsigned int)a3);\n return v5;\n}", + "ida_strip_asm": "sub_14C0:\nendbr64\npush rbp\nlea rcx, compar; compar\nmovsxd rsi, esi; nmemb\nmov rbp, rdi\npush rbx\nmov ebx, edx\nmov edx, 20h ; ' '; size\nsub rsp, 8\ncall _qsort\nmovsxd rdi, ebx\nshl rdi, 5; size\ncall _malloc\nmov rcx, rax\ntest ebx, ebx\njle short loc_150A\nmov edx, ebx\nmov rsi, rbp; src\nmov rdi, rax; dest\nshl rdx, 5; n\ncall _memcpy\nmov rcx, rax\nloc_150A:\nadd rsp, 8\nmov rax, rcx\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "void *__fastcall sub_14C0(void *src, int a2, int a3)\n{\n void *v4; // rax\n void *v5; // rcx\n\n qsort(src, a2, 0x20uLL, compar);\n v4 = malloc(32LL * a3);\n v5 = v4;\n if ( a3 > 0 )\n return memcpy(v4, src, 32LL * (unsigned int)a3);\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_14C0(void *src, int a2, int a3) {\n void *v4;\n void *v5;\n qsort(src, a2, 32uLL, compar);\n v4 = malloc(32LL * a3);\n v5 = v4;\n if (a3 > 0) return memcpy(v4, src, 32LL * (unsigned int)a3);\n return v5;\n}", + "ida_pseudo_norm": "void *func0(void *src, int a2, int a3) {\n void *v4;\n void *v5;\n qsort(src, a2, 32uLL, compare);\n v4 = malloc(32LL * a3);\n v5 = v4;\n if (a3 > 0) return memcpy(v4, src, 32LL * (unsigned int)a3);\n return v5;\n}" + }, + { + "index": 586, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "void func0(int a[], int n, int k, int result[]) {\n int b[k];\n int i;\n for (i = 0; i < k; i++) {\n b[i] = a[i];\n }\n int j = 0;\n for (i = k; i < n; i++) {\n result[j++] = a[i];\n }\n for (i = 0; i < k; i++) {\n result[j++] = b[i];\n }\n}", + "test": "int main() {\n\n int result[6];\n\n\n\n func0((int[]){12, 10, 5, 6, 52, 36}, 6, 2, result);\n\n assert(result[0] == 5 && result[1] == 6 && result[2] == 52 && result[3] == 36 && result[4] == 12 && result[5] == 10);\n\n\n\n func0((int[]){1, 2, 3, 4}, 4, 1, result);\n\n assert(result[0] == 2 && result[1] == 3 && result[2] == 4 && result[3] == 1);\n\n\n\n func0((int[]){0, 1, 2, 3, 4, 5, 6, 7}, 8, 3, result);\n\n assert(result[0] == 3 && result[1] == 4 && result[2] == 5 && result[3] == 6 && result[4] == 7 && result[5] == 0 && result[6] == 1 && result[7] == 2);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x40,%rsp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmov %edx,-0x30(%rbp)\nmov %rcx,-0x38(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmov %rsp,%rax\nmov %rax,%rsi\nmov -0x30(%rbp),%eax\nmovslq %eax,%rdx\nsub $0x1,%rdx\nmov %rdx,-0x18(%rbp)\nmovslq %eax,%rdx\nmov %rdx,%r10\nmov $0x0,%r11d\nmovslq %eax,%rdx\nmov %rdx,%r8\nmov $0x0,%r9d\ncltq\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%edi\nmov $0x0,%edx\ndiv %rdi\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rdi\nsub %rdx,%rdi\nmov %rdi,%rdx\ncmp %rdx,%rsp\nje 120f \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11f8 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 1239 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x10(%rbp)\nmovl $0x0,-0x1c(%rbp)\njmp 127c \nmov -0x1c(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%ecx\nmov -0x10(%rbp),%rax\nmov -0x1c(%rbp),%edx\nmovslq %edx,%rdx\nmov %ecx,(%rax,%rdx,4)\naddl $0x1,-0x1c(%rbp)\nmov -0x1c(%rbp),%eax\ncmp -0x30(%rbp),%eax\njl 1255 \nmovl $0x0,-0x20(%rbp)\nmov -0x30(%rbp),%eax\nmov %eax,-0x1c(%rbp)\njmp 12ca \nmov -0x1c(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x20(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x20(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x38(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x1c(%rbp)\nmov -0x1c(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 1293 \nmovl $0x0,-0x1c(%rbp)\njmp 1309 \nmov -0x20(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x20(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x38(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x10(%rbp),%rax\nmov -0x1c(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nmov %eax,(%rcx)\naddl $0x1,-0x1c(%rbp)\nmov -0x1c(%rbp),%eax\ncmp -0x30(%rbp),%eax\njl 12db \nmov %rsi,%rsp\nmov -0x8(%rbp),%rax\nxor %fs:0x28,%rax\nje 1329 \ncallq 1060 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_30], edx\nmov [rbp+var_38], rcx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov eax, [rbp+var_30]\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11DD:\ncmp rsp, rdx\njz short loc_11F4\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_11DD\nloc_11F4:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_121E\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_121E:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov [rbp+var_20], 0\njmp short loc_1261\nloc_123A:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov ecx, [rax]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nadd [rbp+var_20], 1\nloc_1261:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_30]\njl short loc_123A\nmov [rbp+var_1C], 0\nmov eax, [rbp+var_30]\nmov [rbp+var_20], eax\njmp short loc_12AF\nloc_1278:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_1C]\nlea edx, [rax+1]\nmov [rbp+var_1C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nadd [rbp+var_20], 1\nloc_12AF:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_2C]\njl short loc_1278\nmov [rbp+var_20], 0\njmp short loc_12EE\nloc_12C0:\nmov eax, [rbp+var_1C]\nlea edx, [rax+1]\nmov [rbp+var_1C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nlea rcx, [rdx+rax]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov [rcx], eax\nadd [rbp+var_20], 1\nloc_12EE:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_30]\njl short loc_12C0\nmov rsp, rsi\nnop\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njz short locret_130E\ncall ___stack_chk_fail\nlocret_130E:\nleave\nretn", + "ida_pseudo": "unsigned __int64 __fastcall func0(__int64 a1, int a2, int a3, __int64 a4)\n{\n unsigned __int64 v4; // rax\n void *v5; // rsp\n int v6; // eax\n int v7; // eax\n _BYTE v9[8]; // [rsp+8h] [rbp-40h] BYREF\n __int64 v10; // [rsp+10h] [rbp-38h]\n int v11; // [rsp+18h] [rbp-30h]\n int v12; // [rsp+1Ch] [rbp-2Ch]\n __int64 v13; // [rsp+20h] [rbp-28h]\n int i; // [rsp+28h] [rbp-20h]\n int v15; // [rsp+2Ch] [rbp-1Ch]\n __int64 v16; // [rsp+30h] [rbp-18h]\n _BYTE *v17; // [rsp+38h] [rbp-10h]\n unsigned __int64 v18; // [rsp+40h] [rbp-8h]\n\n v13 = a1;\n v12 = a2;\n v11 = a3;\n v10 = a4;\n v18 = __readfsqword(0x28u);\n v16 = a3 - 1LL;\n v4 = 16 * ((4LL * a3 + 15) / 0x10uLL);\n while ( v9 != &v9[-(v4 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v5 = alloca(v4 & 0xFFF);\n if ( (v4 & 0xFFF) != 0 )\n *(_QWORD *)&v9[(v4 & 0xFFF) - 8] = *(_QWORD *)&v9[(v4 & 0xFFF) - 8];\n v17 = v9;\n for ( i = 0; i < v11; ++i )\n *(_DWORD *)&v17[4 * i] = *(_DWORD *)(4LL * i + v13);\n v15 = 0;\n for ( i = v11; i < v12; ++i )\n {\n v6 = v15++;\n *(_DWORD *)(v10 + 4LL * v6) = *(_DWORD *)(4LL * i + v13);\n }\n for ( i = 0; i < v11; ++i )\n {\n v7 = v15++;\n *(_DWORD *)(4LL * v7 + v10) = *(_DWORD *)&v17[4 * i];\n }\n return v18 - __readfsqword(0x28u);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_30], edx\nmov [rbp+var_38], rcx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov eax, [rbp+var_30]\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11DD:\ncmp rsp, rdx\njz short loc_11F4\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_11DD\nloc_11F4:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_121E\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_121E:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov [rbp+var_20], 0\njmp short loc_1261\nloc_123A:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov ecx, [rax]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nadd [rbp+var_20], 1\nloc_1261:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_30]\njl short loc_123A\nmov [rbp+var_1C], 0\nmov eax, [rbp+var_30]\nmov [rbp+var_20], eax\njmp short loc_12AF\nloc_1278:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_1C]\nlea edx, [rax+1]\nmov [rbp+var_1C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nadd [rbp+var_20], 1\nloc_12AF:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_2C]\njl short loc_1278\nmov [rbp+var_20], 0\njmp short loc_12EE\nloc_12C0:\nmov eax, [rbp+var_1C]\nlea edx, [rax+1]\nmov [rbp+var_1C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nlea rcx, [rdx+rax]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov [rcx], eax\nadd [rbp+var_20], 1\nloc_12EE:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_30]\njl short loc_12C0\nmov rsp, rsi\nnop\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njz short locret_130E\ncall ___stack_chk_fail\nlocret_130E:\nleave\nretn", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_1169(__int64 a1, int a2, int a3, __int64 a4)\n{\n unsigned __int64 v4; // rax\n void *v5; // rsp\n int v6; // eax\n int v7; // eax\n _BYTE v9[8]; // [rsp+8h] [rbp-40h] BYREF\n __int64 v10; // [rsp+10h] [rbp-38h]\n int v11; // [rsp+18h] [rbp-30h]\n int v12; // [rsp+1Ch] [rbp-2Ch]\n __int64 v13; // [rsp+20h] [rbp-28h]\n int i; // [rsp+28h] [rbp-20h]\n int v15; // [rsp+2Ch] [rbp-1Ch]\n __int64 v16; // [rsp+30h] [rbp-18h]\n _BYTE *v17; // [rsp+38h] [rbp-10h]\n unsigned __int64 v18; // [rsp+40h] [rbp-8h]\n\n v13 = a1;\n v12 = a2;\n v11 = a3;\n v10 = a4;\n v18 = __readfsqword(0x28u);\n v16 = a3 - 1LL;\n v4 = 16 * ((4LL * a3 + 15) / 0x10uLL);\n while ( v9 != &v9[-(v4 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v5 = alloca(v4 & 0xFFF);\n if ( (v4 & 0xFFF) != 0 )\n *(_QWORD *)&v9[(v4 & 0xFFF) - 8] = *(_QWORD *)&v9[(v4 & 0xFFF) - 8];\n v17 = v9;\n for ( i = 0; i < v11; ++i )\n *(_DWORD *)&v17[4 * i] = *(_DWORD *)(4LL * i + v13);\n v15 = 0;\n for ( i = v11; i < v12; ++i )\n {\n v6 = v15++;\n *(_DWORD *)(v10 + 4LL * v6) = *(_DWORD *)(4LL * i + v13);\n }\n for ( i = 0; i < v11; ++i )\n {\n v7 = v15++;\n *(_DWORD *)(4LL * v7 + v10) = *(_DWORD *)&v17[4 * i];\n }\n return v18 - __readfsqword(0x28u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_1169(long long a1, int a2, int a3, long long a4) {\n unsigned long long v4;\n void *v5;\n int v6;\n int v7;\n uint8_t v9[8];\n long long v10;\n int v11;\n int v12;\n long long v13;\n int i;\n int v15;\n long long v16;\n uint8_t *v17;\n unsigned long long v18;\n v13 = a1;\n v12 = a2;\n v11 = a3;\n v10 = a4;\n v18 = __readfsqword(40u);\n v16 = a3 - 1LL;\n v4 = 16 * ((4LL * a3 + 15) / 16uLL);\n while (v9 != &v9[-(v4 & 18446744073709547520LL)])\n ;\n v5 = alloca(v4 & 4095);\n if ((v4 & 4095) != 0)\n *(uint64_t *)&v9[(v4 & 4095) - 8] = *(uint64_t *)&v9[(v4 & 4095) - 8];\n v17 = v9;\n for (i = 0; i < v11; ++i)\n *(uint32_t *)&v17[4 * i] = *(uint32_t *)(4LL * i + v13);\n v15 = 0;\n for (i = v11; i < v12; ++i) {\n v6 = v15++;\n *(uint32_t *)(v10 + 4LL * v6) = *(uint32_t *)(4LL * i + v13);\n }\n for (i = 0; i < v11; ++i) {\n v7 = v15++;\n *(uint32_t *)(4LL * v7 + v10) = *(uint32_t *)&v17[4 * i];\n }\n return v18 - __readfsqword(40u);\n}", + "ida_pseudo_norm": "unsigned long long func0(long long a1, int a2, int a3, long long a4) {\n unsigned long long v4;\n void *v5;\n int v6;\n int v7;\n uint8_t v9[8];\n long long v10;\n int v11;\n int v12;\n long long v13;\n int i;\n int v15;\n long long v16;\n uint8_t *v17;\n unsigned long long v18;\n v13 = a1;\n v12 = a2;\n v11 = a3;\n v10 = a4;\n v18 = __readfsqword(40u);\n v16 = a3 - 1LL;\n v4 = 16 * ((4LL * a3 + 15) / 16uLL);\n while (v9 != &v9[-(v4 & 18446744073709547520LL)])\n ;\n v5 = alloca(v4 & 4095);\n if ((v4 & 4095) != 0)\n *(uint64_t *)&v9[(v4 & 4095) - 8] = *(uint64_t *)&v9[(v4 & 4095) - 8];\n v17 = v9;\n for (i = 0; i < v11; ++i)\n *(uint32_t *)&v17[4 * i] = *(uint32_t *)(4LL * i + v13);\n v15 = 0;\n for (i = v11; i < v12; ++i) {\n v6 = v15++;\n *(uint32_t *)(v10 + 4LL * v6) = *(uint32_t *)(4LL * i + v13);\n }\n for (i = 0; i < v11; ++i) {\n v7 = v15++;\n *(uint32_t *)(4LL * v7 + v10) = *(uint32_t *)&v17[4 * i];\n }\n return v18 - __readfsqword(40u);\n}" + }, + { + "index": 586, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "void func0(int a[], int n, int k, int result[]) {\n int b[k];\n int i;\n for (i = 0; i < k; i++) {\n b[i] = a[i];\n }\n int j = 0;\n for (i = k; i < n; i++) {\n result[j++] = a[i];\n }\n for (i = 0; i < k; i++) {\n result[j++] = b[i];\n }\n}", + "test": "int main() {\n\n int result[6];\n\n\n\n func0((int[]){12, 10, 5, 6, 52, 36}, 6, 2, result);\n\n assert(result[0] == 5 && result[1] == 6 && result[2] == 52 && result[3] == 36 && result[4] == 12 && result[5] == 10);\n\n\n\n func0((int[]){1, 2, 3, 4}, 4, 1, result);\n\n assert(result[0] == 2 && result[1] == 3 && result[2] == 4 && result[3] == 1);\n\n\n\n func0((int[]){0, 1, 2, 3, 4, 5, 6, 7}, 8, 3, result);\n\n assert(result[0] == 3 && result[1] == 4 && result[2] == 5 && result[3] == 6 && result[4] == 7 && result[5] == 0 && result[6] == 1 && result[7] == 2);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovslq %edx,%rax\nlea 0xf(,%rax,4),%r8\nmov %r8,%r9\nand $0xfffffffffffffff0,%r9\nand $0xfffffffffffff000,%r8\nmov %rsp,%r11\nsub %r8,%r11\nmov %r11,%r8\ncmp %r8,%rsp\nje 11bd \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11a6 \nmov %r9,%r8\nand $0xfff,%r8d\nsub %r8,%rsp\ntest %r8,%r8\nje 11d5 \norq $0x0,-0x8(%rsp,%r8,1)\nmov %rsp,%r9\ntest %edx,%edx\njle 1260 \nlea -0x1(%rdx),%r11d\nmov $0x0,%r8d\nmov (%rdi,%r8,4),%r10d\nmov %r10d,(%r9,%r8,4)\nmov %r8,%r10\nadd $0x1,%r8\ncmp %r11,%r10\njne 11ea \ncmp %esi,%edx\njge 1259 \nmov %rax,%r8\nneg %r8\nlea (%rcx,%r8,4),%r10\nmov (%rdi,%rax,4),%r8d\nmov %r8d,(%r10,%rax,4)\nadd $0x1,%rax\ncmp %eax,%esi\njg 120c \nmov %esi,%eax\nsub %edx,%eax\ncmp %esi,%edx\nmov $0x1,%esi\ncmovge %esi,%eax\ntest %edx,%edx\njle 1248 \ncltq\nlea (%rcx,%rax,4),%rsi\nmov $0x0,%eax\nmov (%r9,%rax,4),%ecx\nmov %ecx,(%rsi,%rax,4)\nadd $0x1,%rax\ncmp %eax,%edx\njg 1239 \nmov -0x8(%rbp),%rax\nxor %fs:0x28,%rax\njne 1266 \nleaveq\nretq\nmov $0x0,%eax\njmp 122e \ncmp %esi,%edx\njl 1202 \njmp 1248 \ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov r9d, esi\nmov r10d, edx\nmov r11, rcx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmovsxd rax, edx\nlea rcx, ds:0[rax*4]\nlea rdx, [rcx+0Fh]\nmov r8, rdx\nand r8, 0FFFFFFFFFFFFFFF0h\nand rdx, 0FFFFFFFFFFFFF000h\nmov rsi, rsp\nsub rsi, rdx\nloc_11B0:\ncmp rsp, rsi\njz short loc_11C7\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11B0\nloc_11C7:\nmov rdx, r8\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njz short loc_11DE\nor [rsp+rdx+10h+var_18], 0\nloc_11DE:\nmov rsi, rsp\ntest r10d, r10d\njle short loc_1263\nmov edx, 0\nloc_11EB:\nmov r8d, [rdi+rdx]\nmov [rsi+rdx], r8d\nadd rdx, 4\ncmp rcx, rdx\njnz short loc_11EB\ncmp r10d, r9d\njge short loc_125C\nloc_1201:\nmov rdx, rax\nneg rdx\nlea r8, [r11+rdx*4]\nloc_120B:\nmov edx, [rdi+rax*4]\nmov [r8+rax*4], edx\nadd rax, 1\ncmp r9d, eax\njg short loc_120B\nmov eax, r9d\nsub eax, r10d\ncmp r10d, r9d\nmov edx, 1\ncmovge eax, edx\ntest r10d, r10d\njle short loc_124B\nloc_1231:\ncdqe\nlea rdi, [r11+rax*4]\nmov eax, 0\nloc_123C:\nmov edx, [rsi+rax]\nmov [rdi+rax], edx\nadd rax, 4\ncmp rcx, rax\njnz short loc_123C\nloc_124B:\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njnz short loc_126A\nleave\nretn\nloc_125C:\nmov eax, 0\njmp short loc_1231\nloc_1263:\ncmp r10d, r9d\njl short loc_1201\njmp short loc_124B\nloc_126A:\ncall ___stack_chk_fail", + "ida_pseudo": "unsigned __int64 __fastcall func0(__int64 a1, int a2, int a3, __int64 a4)\n{\n __int64 v6; // rax\n __int64 v7; // rcx\n signed __int64 v8; // rdx\n void *v9; // rsp\n __int64 v10; // rdx\n __int64 v11; // r8\n int v12; // eax\n __int64 v13; // rdi\n __int64 v14; // rax\n _BYTE v17[8]; // [rsp+8h] [rbp-10h] BYREF\n unsigned __int64 v18; // [rsp+10h] [rbp-8h]\n\n v18 = __readfsqword(0x28u);\n v6 = a3;\n v7 = 4LL * a3;\n while ( v17 != &v17[-((v7 + 15) & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v8 = ((_WORD)v7 + 15) & 0xFF0;\n v9 = alloca(v8);\n if ( (((_WORD)v7 + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v17[v8 - 8] = *(_QWORD *)&v17[v8 - 8];\n if ( a3 <= 0 )\n {\n if ( a3 >= a2 )\n return v18 - __readfsqword(0x28u);\n }\n else\n {\n v10 = 0LL;\n do\n {\n *(_DWORD *)&v17[v10] = *(_DWORD *)(a1 + v10);\n v10 += 4LL;\n }\n while ( v7 != v10 );\n if ( a3 >= a2 )\n {\n v12 = 0;\nLABEL_14:\n v13 = a4 + 4LL * v12;\n v14 = 0LL;\n do\n {\n *(_DWORD *)(v13 + v14) = *(_DWORD *)&v17[v14];\n v14 += 4LL;\n }\n while ( v7 != v14 );\n return v18 - __readfsqword(0x28u);\n }\n }\n v11 = a4 - 4 * v6;\n do\n {\n *(_DWORD *)(v11 + 4 * v6) = *(_DWORD *)(a1 + 4 * v6);\n ++v6;\n }\n while ( a2 > (int)v6 );\n v12 = a2 - a3;\n if ( a3 >= a2 )\n v12 = 1;\n if ( a3 > 0 )\n goto LABEL_14;\n return v18 - __readfsqword(0x28u);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov r9d, esi\nmov r10d, edx\nmov r11, rcx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmovsxd rax, edx\nlea rcx, ds:0[rax*4]\nlea rdx, [rcx+0Fh]\nmov r8, rdx\nand r8, 0FFFFFFFFFFFFFFF0h\nand rdx, 0FFFFFFFFFFFFF000h\nmov rsi, rsp\nsub rsi, rdx\nloc_11B0:\ncmp rsp, rsi\njz short loc_11C7\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11B0\nloc_11C7:\nmov rdx, r8\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njz short loc_11DE\nor [rsp+rdx+10h+var_18], 0\nloc_11DE:\nmov rsi, rsp\ntest r10d, r10d\njle short loc_1263\nmov edx, 0\nloc_11EB:\nmov r8d, [rdi+rdx]\nmov [rsi+rdx], r8d\nadd rdx, 4\ncmp rcx, rdx\njnz short loc_11EB\ncmp r10d, r9d\njge short loc_125C\nloc_1201:\nmov rdx, rax\nneg rdx\nlea r8, [r11+rdx*4]\nloc_120B:\nmov edx, [rdi+rax*4]\nmov [r8+rax*4], edx\nadd rax, 1\ncmp r9d, eax\njg short loc_120B\nmov eax, r9d\nsub eax, r10d\ncmp r10d, r9d\nmov edx, 1\ncmovge eax, edx\ntest r10d, r10d\njle short loc_124B\nloc_1231:\ncdqe\nlea rdi, [r11+rax*4]\nmov eax, 0\nloc_123C:\nmov edx, [rsi+rax]\nmov [rdi+rax], edx\nadd rax, 4\ncmp rcx, rax\njnz short loc_123C\nloc_124B:\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njnz short loc_126A\nleave\nretn\nloc_125C:\nmov eax, 0\njmp short loc_1231\nloc_1263:\ncmp r10d, r9d\njl short loc_1201\njmp short loc_124B\nloc_126A:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_1169(__int64 a1, int a2, int a3, __int64 a4)\n{\n __int64 v6; // rax\n __int64 v7; // rcx\n signed __int64 v8; // rdx\n void *v9; // rsp\n __int64 v10; // rdx\n __int64 v11; // r8\n int v12; // eax\n __int64 v13; // rdi\n __int64 v14; // rax\n _BYTE v17[8]; // [rsp+8h] [rbp-10h] BYREF\n unsigned __int64 v18; // [rsp+10h] [rbp-8h]\n\n v18 = __readfsqword(0x28u);\n v6 = a3;\n v7 = 4LL * a3;\n while ( v17 != &v17[-((v7 + 15) & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v8 = ((_WORD)v7 + 15) & 0xFF0;\n v9 = alloca(v8);\n if ( (((_WORD)v7 + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v17[v8 - 8] = *(_QWORD *)&v17[v8 - 8];\n if ( a3 <= 0 )\n {\n if ( a3 >= a2 )\n return v18 - __readfsqword(0x28u);\n }\n else\n {\n v10 = 0LL;\n do\n {\n *(_DWORD *)&v17[v10] = *(_DWORD *)(a1 + v10);\n v10 += 4LL;\n }\n while ( v7 != v10 );\n if ( a3 >= a2 )\n {\n v12 = 0;\nLABEL_14:\n v13 = a4 + 4LL * v12;\n v14 = 0LL;\n do\n {\n *(_DWORD *)(v13 + v14) = *(_DWORD *)&v17[v14];\n v14 += 4LL;\n }\n while ( v7 != v14 );\n return v18 - __readfsqword(0x28u);\n }\n }\n v11 = a4 - 4 * v6;\n do\n {\n *(_DWORD *)(v11 + 4 * v6) = *(_DWORD *)(a1 + 4 * v6);\n ++v6;\n }\n while ( a2 > (int)v6 );\n v12 = a2 - a3;\n if ( a3 >= a2 )\n v12 = 1;\n if ( a3 > 0 )\n goto LABEL_14;\n return v18 - __readfsqword(0x28u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_1169(long long a1, int a2, int a3, long long a4) {\n long long v6;\n long long v7;\n signed long long v8;\n void *v9;\n long long v10;\n long long v11;\n int v12;\n long long v13;\n long long v14;\n uint8_t v17[8];\n unsigned long long v18;\n v18 = __readfsqword(40u);\n v6 = a3;\n v7 = 4LL * a3;\n while (v17 != &v17[-((v7 + 15) & 18446744073709547520LL)])\n ;\n v8 = ((unsigned short)v7 + 15) & 4080;\n v9 = alloca(v8);\n if ((((unsigned short)v7 + 15) & 4080) != 0)\n *(uint64_t *)&v17[v8 - 8] = *(uint64_t *)&v17[v8 - 8];\n if (a3 <= 0) {\n if (a3 >= a2) return v18 - __readfsqword(40u);\n } else {\n v10 = 0LL;\n do {\n *(uint32_t *)&v17[v10] = *(uint32_t *)(a1 + v10);\n v10 += 4LL;\n } while (v7 != v10);\n if (a3 >= a2) {\n v12 = 0;\n LABEL_14:\n v13 = a4 + 4LL * v12;\n v14 = 0LL;\n do {\n *(uint32_t *)(v13 + v14) = *(uint32_t *)&v17[v14];\n v14 += 4LL;\n } while (v7 != v14);\n return v18 - __readfsqword(40u);\n }\n }\n v11 = a4 - 4 * v6;\n do {\n *(uint32_t *)(v11 + 4 * v6) = *(uint32_t *)(a1 + 4 * v6);\n ++v6;\n } while (a2 > (int)v6);\n v12 = a2 - a3;\n if (a3 >= a2) v12 = 1;\n if (a3 > 0) goto LABEL_14;\n return v18 - __readfsqword(40u);\n}", + "ida_pseudo_norm": "unsigned long long func0(long long a1, int a2, int a3, long long a4) {\n long long v6;\n long long v7;\n signed long long v8;\n void *v9;\n long long v10;\n long long v11;\n int v12;\n long long v13;\n long long v14;\n uint8_t v17[8];\n unsigned long long v18;\n v18 = __readfsqword(40u);\n v6 = a3;\n v7 = 4LL * a3;\n while (v17 != &v17[-((v7 + 15) & 18446744073709547520LL)])\n ;\n v8 = ((unsigned short)v7 + 15) & 4080;\n v9 = alloca(v8);\n if ((((unsigned short)v7 + 15) & 4080) != 0)\n *(uint64_t *)&v17[v8 - 8] = *(uint64_t *)&v17[v8 - 8];\n if (a3 <= 0) {\n if (a3 >= a2) return v18 - __readfsqword(40u);\n } else {\n v10 = 0LL;\n do {\n *(uint32_t *)&v17[v10] = *(uint32_t *)(a1 + v10);\n v10 += 4LL;\n } while (v7 != v10);\n if (a3 >= a2) {\n v12 = 0;\n LABEL_14:\n v13 = a4 + 4LL * v12;\n v14 = 0LL;\n do {\n *(uint32_t *)(v13 + v14) = *(uint32_t *)&v17[v14];\n v14 += 4LL;\n } while (v7 != v14);\n return v18 - __readfsqword(40u);\n }\n }\n v11 = a4 - 4 * v6;\n do {\n *(uint32_t *)(v11 + 4 * v6) = *(uint32_t *)(a1 + 4 * v6);\n ++v6;\n } while (a2 > (int)v6);\n v12 = a2 - a3;\n if (a3 >= a2) v12 = 1;\n if (a3 > 0) goto LABEL_14;\n return v18 - __readfsqword(40u);\n}" + }, + { + "index": 586, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "void func0(int a[], int n, int k, int result[]) {\n int b[k];\n int i;\n for (i = 0; i < k; i++) {\n b[i] = a[i];\n }\n int j = 0;\n for (i = k; i < n; i++) {\n result[j++] = a[i];\n }\n for (i = 0; i < k; i++) {\n result[j++] = b[i];\n }\n}", + "test": "int main() {\n\n int result[6];\n\n\n\n func0((int[]){12, 10, 5, 6, 52, 36}, 6, 2, result);\n\n assert(result[0] == 5 && result[1] == 6 && result[2] == 52 && result[3] == 36 && result[4] == 12 && result[5] == 10);\n\n\n\n func0((int[]){1, 2, 3, 4}, 4, 1, result);\n\n assert(result[0] == 2 && result[1] == 3 && result[2] == 4 && result[3] == 1);\n\n\n\n func0((int[]){0, 1, 2, 3, 4, 5, 6, 7}, 8, 3, result);\n\n assert(result[0] == 3 && result[1] == 4 && result[2] == 5 && result[3] == 6 && result[4] == 7 && result[5] == 0 && result[6] == 1 && result[7] == 2);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovslq %edx,%rax\nmov %rsp,%r11\nlea 0xf(,%rax,4),%r8\nmov %r8,%r9\nand $0xfffffffffffff000,%r8\nsub %r8,%r11\nand $0xfffffffffffffff0,%r9\nmov %r11,%r8\ncmp %r8,%rsp\nje 13d7 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %r8,%rsp\njne 13c2 \nand $0xfff,%r9d\nsub %r9,%rsp\ntest %r9,%r9\njne 1480 \nmov %rsp,%r9\ntest %edx,%edx\njle 148b \nlea -0x1(%rdx),%r11d\nxor %r8d,%r8d\nnopl 0x0(%rax)\nmov (%rdi,%r8,4),%r10d\nmov %r10d,(%r9,%r8,4)\nmov %r8,%r10\nadd $0x1,%r8\ncmp %r10,%r11\njne 1400 \ncmp %esi,%edx\njge 1498 \nmov %rax,%r8\nneg %r8\nlea (%rcx,%r8,4),%r10\nnopw %cs:0x0(%rax,%rax,1)\nmov (%rdi,%rax,4),%r8d\nmov %r8d,(%r10,%rax,4)\nadd $0x1,%rax\ncmp %eax,%esi\njg 1430 \nmov %esi,%eax\nsub %edx,%eax\ncmp %esi,%edx\nmov $0x1,%esi\ncmovge %esi,%eax\ntest %edx,%edx\njle 146f \ncltq\nlea (%rcx,%rax,4),%rsi\nxor %eax,%eax\nnopw 0x0(%rax,%rax,1)\nmov (%r9,%rax,4),%ecx\nmov %ecx,(%rsi,%rax,4)\nadd $0x1,%rax\ncmp %eax,%edx\njg 1460 \nmov -0x8(%rbp),%rax\nxor %fs:0x28,%rax\njne 149c \nleaveq\nretq\norq $0x0,-0x8(%rsp,%r9,1)\njmpq 13ea \ncmp %esi,%edx\njl 141c \njmp 146f \nnopl 0x0(%rax)\nxor %eax,%eax\njmp 1452 \ncallq 1060 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\nmov r15, rcx\npush r14\npush r13\nmov r13, rdi\npush r12\nmov r12d, esi\npush rbx\nmovsxd rbx, edx\nlea r9, ds:0[rbx*4]\nmov r14, rbx\nsub rsp, 28h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nlea rax, [r9+0Fh]\nmov rcx, rsp\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_13CC\nloc_13B7:\nsub rsp, 1000h\nor [rsp+1050h+var_58], 0\ncmp rsp, rcx\njnz short loc_13B7\nloc_13CC:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1480\nloc_13DE:\nmov rcx, rsp\ntest r14d, r14d\njle loc_148B\nmov r8d, r14d\nmov rdi, rcx; dest\nmov rsi, r13; src\nmov [rbp+var_50], r9\nlea rdx, ds:0[r8*4]; n\nmov [rbp+var_48], r8\ncall _memcpy\nmov r8, [rbp+var_48]\nmov r9, [rbp+var_50]\nmov rcx, rax\nxor eax, eax\ncmp r14d, r12d\njge short loc_144A\nloc_141A:\nmov rdx, r15\nsub rdx, r9\nloc_1420:\nmov eax, [r13+rbx*4+0]\nmov [rdx+rbx*4], eax\nadd rbx, 1\ncmp r12d, ebx\njg short loc_1420\nmov eax, r12d\nmov edx, 1\nsub eax, r14d\ncmp r14d, r12d\ncmovge eax, edx\ntest r14d, r14d\njle short loc_1460\nmov r8d, r14d\nloc_144A:\ncdqe\nlea rdx, ds:0[r8*4]; n\nmov rsi, rcx; src\nlea rdi, [r15+rax*4]; dest\ncall _memcpy\nloc_1460:\nmov rax, [rbp+var_38]\nsub rax, fs:28h\njnz short loc_1492\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1480:\nor [rsp+rdx+1050h+var_1058], 0\njmp loc_13DE\nloc_148B:\ncmp r14d, r12d\njl short loc_141A\njmp short loc_1460\nloc_1492:\ncall ___stack_chk_fail", + "ida_pseudo": "unsigned __int64 __fastcall func0(void *src, int a2, int a3, __int64 a4)\n{\n __int64 v5; // rbx\n __int64 v6; // r9\n __int64 *v8; // rcx\n signed __int64 v9; // rdx\n void *v10; // rsp\n _BYTE *v11; // rcx\n _BYTE *v12; // rax\n __int64 v13; // r8\n int v14; // eax\n _BYTE v17[4088]; // [rsp+8h] [rbp-1050h] BYREF\n __int64 v18; // [rsp+1008h] [rbp-50h] BYREF\n __int64 v19; // [rsp+1010h] [rbp-48h]\n unsigned __int64 v20; // [rsp+1020h] [rbp-38h]\n\n v5 = a3;\n v6 = 4LL * a3;\n v20 = __readfsqword(0x28u);\n v8 = (__int64 *)((char *)&v18 - ((v6 + 15) & 0xFFFFFFFFFFFFF000LL));\n if ( &v18 != v8 )\n {\n while ( v17 != (_BYTE *)v8 )\n ;\n }\n v9 = ((_WORD)v6 + 15) & 0xFF0;\n v10 = alloca(v9);\n if ( (((_WORD)v6 + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v17[v9 - 8] = *(_QWORD *)&v17[v9 - 8];\n v11 = v17;\n if ( a3 <= 0 )\n {\n if ( a3 >= a2 )\n return v20 - __readfsqword(0x28u);\n }\n else\n {\n v18 = v6;\n v19 = (unsigned int)a3;\n v12 = memcpy(v17, src, 4LL * (unsigned int)a3);\n v13 = v19;\n v6 = v18;\n v11 = v12;\n v14 = 0;\n if ( a3 >= a2 )\n {\nLABEL_12:\n memcpy((void *)(a4 + 4LL * v14), v11, 4 * v13);\n return v20 - __readfsqword(0x28u);\n }\n }\n do\n {\n *(_DWORD *)(a4 - v6 + 4 * v5) = *((_DWORD *)src + v5);\n ++v5;\n }\n while ( a2 > (int)v5 );\n v14 = a2 - a3;\n if ( a3 >= a2 )\n v14 = 1;\n if ( a3 > 0 )\n {\n v13 = (unsigned int)a3;\n goto LABEL_12;\n }\n return v20 - __readfsqword(0x28u);\n}", + "ida_strip_asm": "sub_1360:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\nmov r15, rcx\npush r14\npush r13\nmov r13, rdi\npush r12\nmov r12d, esi\npush rbx\nmovsxd rbx, edx\nlea r9, ds:0[rbx*4]\nmov r14, rbx\nsub rsp, 28h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nlea rax, [r9+0Fh]\nmov rcx, rsp\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_13CC\nloc_13B7:\nsub rsp, 1000h\nor [rsp+1050h+var_58], 0\ncmp rsp, rcx\njnz short loc_13B7\nloc_13CC:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1480\nloc_13DE:\nmov rcx, rsp\ntest r14d, r14d\njle loc_148B\nmov r8d, r14d\nmov rdi, rcx; dest\nmov rsi, r13; src\nmov [rbp+var_50], r9\nlea rdx, ds:0[r8*4]; n\nmov [rbp+var_48], r8\ncall _memcpy\nmov r8, [rbp+var_48]\nmov r9, [rbp+var_50]\nmov rcx, rax\nxor eax, eax\ncmp r14d, r12d\njge short loc_144A\nloc_141A:\nmov rdx, r15\nsub rdx, r9\nloc_1420:\nmov eax, [r13+rbx*4+0]\nmov [rdx+rbx*4], eax\nadd rbx, 1\ncmp r12d, ebx\njg short loc_1420\nmov eax, r12d\nmov edx, 1\nsub eax, r14d\ncmp r14d, r12d\ncmovge eax, edx\ntest r14d, r14d\njle short loc_1460\nmov r8d, r14d\nloc_144A:\ncdqe\nlea rdx, ds:0[r8*4]; n\nmov rsi, rcx; src\nlea rdi, [r15+rax*4]; dest\ncall _memcpy\nloc_1460:\nmov rax, [rbp+var_38]\nsub rax, fs:28h\njnz short loc_1492\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1480:\nor [rsp+rdx+1050h+var_1058], 0\njmp loc_13DE\nloc_148B:\ncmp r14d, r12d\njl short loc_141A\njmp short loc_1460\nloc_1492:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_1360(void *src, int a2, int a3, __int64 a4)\n{\n __int64 v5; // rbx\n __int64 v6; // r9\n __int64 *v8; // rcx\n signed __int64 v9; // rdx\n void *v10; // rsp\n _BYTE *v11; // rcx\n _BYTE *v12; // rax\n __int64 v13; // r8\n int v14; // eax\n _BYTE v17[4088]; // [rsp+8h] [rbp-1050h] BYREF\n __int64 v18; // [rsp+1008h] [rbp-50h] BYREF\n __int64 v19; // [rsp+1010h] [rbp-48h]\n unsigned __int64 v20; // [rsp+1020h] [rbp-38h]\n\n v5 = a3;\n v6 = 4LL * a3;\n v20 = __readfsqword(0x28u);\n v8 = (__int64 *)((char *)&v18 - ((v6 + 15) & 0xFFFFFFFFFFFFF000LL));\n if ( &v18 != v8 )\n {\n while ( v17 != (_BYTE *)v8 )\n ;\n }\n v9 = ((_WORD)v6 + 15) & 0xFF0;\n v10 = alloca(v9);\n if ( (((_WORD)v6 + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v17[v9 - 8] = *(_QWORD *)&v17[v9 - 8];\n v11 = v17;\n if ( a3 <= 0 )\n {\n if ( a3 >= a2 )\n return v20 - __readfsqword(0x28u);\n }\n else\n {\n v18 = v6;\n v19 = (unsigned int)a3;\n v12 = memcpy(v17, src, 4LL * (unsigned int)a3);\n v13 = v19;\n v6 = v18;\n v11 = v12;\n v14 = 0;\n if ( a3 >= a2 )\n {\nLABEL_12:\n memcpy((void *)(a4 + 4LL * v14), v11, 4 * v13);\n return v20 - __readfsqword(0x28u);\n }\n }\n do\n {\n *(_DWORD *)(a4 - v6 + 4 * v5) = *((_DWORD *)src + v5);\n ++v5;\n }\n while ( a2 > (int)v5 );\n v14 = a2 - a3;\n if ( a3 >= a2 )\n v14 = 1;\n if ( a3 > 0 )\n {\n v13 = (unsigned int)a3;\n goto LABEL_12;\n }\n return v20 - __readfsqword(0x28u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_1360(void *src, int a2, int a3, long long a4) {\n long long v5;\n long long v6;\n long long *v8;\n signed long long v9;\n void *v10;\n uint8_t *v11;\n uint8_t *v12;\n long long v13;\n int v14;\n uint8_t v17[4088];\n long long v18;\n long long v19;\n unsigned long long v20;\n v5 = a3;\n v6 = 4LL * a3;\n v20 = __readfsqword(40u);\n v8 = (long long *)((char *)&v18 - ((v6 + 15) & 18446744073709547520LL));\n if (&v18 != v8) {\n while (v17 != (uint8_t *)v8)\n ;\n }\n v9 = ((unsigned short)v6 + 15) & 4080;\n v10 = alloca(v9);\n if ((((unsigned short)v6 + 15) & 4080) != 0)\n *(uint64_t *)&v17[v9 - 8] = *(uint64_t *)&v17[v9 - 8];\n v11 = v17;\n if (a3 <= 0) {\n if (a3 >= a2) return v20 - __readfsqword(40u);\n } else {\n v18 = v6;\n v19 = (unsigned int)a3;\n v12 = memcpy(v17, src, 4LL * (unsigned int)a3);\n v13 = v19;\n v6 = v18;\n v11 = v12;\n v14 = 0;\n if (a3 >= a2) {\n LABEL_12:\n memcpy((void *)(a4 + 4LL * v14), v11, 4 * v13);\n return v20 - __readfsqword(40u);\n }\n }\n do {\n *(uint32_t *)(a4 - v6 + 4 * v5) = *((uint32_t *)src + v5);\n ++v5;\n } while (a2 > (int)v5);\n v14 = a2 - a3;\n if (a3 >= a2) v14 = 1;\n if (a3 > 0) {\n v13 = (unsigned int)a3;\n goto LABEL_12;\n }\n return v20 - __readfsqword(40u);\n}", + "ida_pseudo_norm": "unsigned long long func0(void *src, int a2, int a3, long long a4) {\n long long v5;\n long long v6;\n long long *v8;\n signed long long v9;\n void *v10;\n uint8_t *v11;\n uint8_t *v12;\n long long v13;\n int v14;\n uint8_t v17[4088];\n long long v18;\n long long v19;\n unsigned long long v20;\n v5 = a3;\n v6 = 4LL * a3;\n v20 = __readfsqword(40u);\n v8 = (long long *)((char *)&v18 - ((v6 + 15) & 18446744073709547520LL));\n if (&v18 != v8) {\n while (v17 != (uint8_t *)v8)\n ;\n }\n v9 = ((unsigned short)v6 + 15) & 4080;\n v10 = alloca(v9);\n if ((((unsigned short)v6 + 15) & 4080) != 0)\n *(uint64_t *)&v17[v9 - 8] = *(uint64_t *)&v17[v9 - 8];\n v11 = v17;\n if (a3 <= 0) {\n if (a3 >= a2) return v20 - __readfsqword(40u);\n } else {\n v18 = v6;\n v19 = (unsigned int)a3;\n v12 = memcpy(v17, src, 4LL * (unsigned int)a3);\n v13 = v19;\n v6 = v18;\n v11 = v12;\n v14 = 0;\n if (a3 >= a2) {\n LABEL_12:\n memcpy((void *)(a4 + 4LL * v14), v11, 4 * v13);\n return v20 - __readfsqword(40u);\n }\n }\n do {\n *(uint32_t *)(a4 - v6 + 4 * v5) = *((uint32_t *)src + v5);\n ++v5;\n } while (a2 > (int)v5);\n v14 = a2 - a3;\n if (a3 >= a2) v14 = 1;\n if (a3 > 0) {\n v13 = (unsigned int)a3;\n goto LABEL_12;\n }\n return v20 - __readfsqword(40u);\n}" + }, + { + "index": 586, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "void func0(int a[], int n, int k, int result[]) {\n int b[k];\n int i;\n for (i = 0; i < k; i++) {\n b[i] = a[i];\n }\n int j = 0;\n for (i = k; i < n; i++) {\n result[j++] = a[i];\n }\n for (i = 0; i < k; i++) {\n result[j++] = b[i];\n }\n}", + "test": "int main() {\n\n int result[6];\n\n\n\n func0((int[]){12, 10, 5, 6, 52, 36}, 6, 2, result);\n\n assert(result[0] == 5 && result[1] == 6 && result[2] == 52 && result[3] == 36 && result[4] == 12 && result[5] == 10);\n\n\n\n func0((int[]){1, 2, 3, 4}, 4, 1, result);\n\n assert(result[0] == 2 && result[1] == 3 && result[2] == 4 && result[3] == 1);\n\n\n\n func0((int[]){0, 1, 2, 3, 4, 5, 6, 7}, 8, 3, result);\n\n assert(result[0] == 3 && result[1] == 4 && result[2] == 5 && result[3] == 6 && result[4] == 7 && result[5] == 0 && result[6] == 1 && result[7] == 2);\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\nmov %rdi,%r15\npush %r14\nmovslq %edx,%r14\npush %r13\nlea 0x0(,%r14,4),%r9\nmov %esi,%r13d\npush %r12\nmov %rcx,%r12\npush %rbx\nmov %r14,%rbx\nsub $0x28,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nlea 0xf(%r9),%rax\nmov %rsp,%rdi\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rdi\nand $0xfffffffffffffff0,%rdx\nmov %rdi,%rax\ncmp %rax,%rsp\nje 13cf \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 13ba \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 1530 \nmov %rsp,%r8\ntest %ebx,%ebx\njle 1566 \nlea -0x1(%rbx),%eax\nmov %r8,%rdi\nmov %r15,%rsi\nmov %r9,-0x50(%rbp)\nlea 0x4(,%rax,4),%rdx\nmov %eax,-0x44(%rbp)\ncallq 1090 \ncmp %r13d,%ebx\nmov -0x44(%rbp),%ecx\nmov -0x50(%rbp),%r9\nmov %rax,%r8\njge 1578 \nlea 0x10(%r15,%r9,1),%rax\nlea (%r15,%r9,1),%rcx\ncmp %rax,%r12\nlea 0x10(%r12),%rax\nsetae %dl\ncmp %rax,%rcx\nsetae %al\nor %al,%dl\nje 1540 \nlea -0x1(%r13),%eax\nsub %ebx,%eax\ncmp $0x3,%eax\njbe 1540 \nmov %r13d,%esi\nmov $0x1,%eax\nsub %ebx,%esi\ncmp %r13d,%ebx\ncmovge %eax,%esi\nxor %eax,%eax\nmov %esi,%edx\nshr $0x2,%edx\nshl $0x4,%rdx\nnopl 0x0(%rax,%rax,1)\nmovdqu (%rcx,%rax,1),%xmm0\nmovups %xmm0,(%r12,%rax,1)\nadd $0x10,%rax\ncmp %rdx,%rax\njne 1470 \nmov %esi,%edx\nand $0xfffffffc,%edx\nlea (%rbx,%rdx,1),%eax\ncmp %edx,%esi\nje 14d1 \nmovslq %eax,%rsi\nlea 0x1(%rdx),%ecx\nmovslq %edx,%rdx\nmov (%r15,%rsi,4),%esi\nmov %esi,(%r12,%rdx,4)\nlea 0x1(%rax),%edx\ncmp %edx,%r13d\njle 14d1 \nmovslq %edx,%rdx\nmovslq %ecx,%rcx\nadd $0x2,%eax\nmov (%r15,%rdx,4),%edx\nlea 0x0(,%rcx,4),%rsi\nmov %edx,(%r12,%rcx,4)\ncmp %eax,%r13d\njle 14d1 \ncltq\nmov (%r15,%rax,4),%eax\nmov %eax,0x4(%r12,%rsi,1)\nmov %r13d,%eax\nmov $0x1,%edx\nsub %ebx,%eax\ncmp %r13d,%ebx\ncmovge %edx,%eax\ntest %ebx,%ebx\njle 1509 \nlea -0x1(%rbx),%ecx\ncltq\nlea 0x4(,%rcx,4),%rdx\ntest %ebx,%ebx\nmov %r8,%rsi\nlea (%r12,%rax,4),%rdi\nmov $0x4,%eax\ncmovle %rax,%rdx\ncallq 1090 \nmov -0x38(%rbp),%rax\nxor %fs:0x28,%rax\njne 157f \nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\nnopw 0x0(%rax,%rax,1)\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 13e1 \nnopl 0x0(%rax,%rax,1)\nmov %r14,%rax\nneg %rax\nlea (%r12,%rax,4),%rdx\nnopw 0x0(%rax,%rax,1)\nmov (%r15,%r14,4),%eax\nmov %eax,(%rdx,%r14,4)\nadd $0x1,%r14\ncmp %r14d,%r13d\njg 1550 \njmpq 14d1 \ncmp %r13d,%ebx\njl 141c \njmp 1509 \nnopl 0x0(%rax)\nxor %eax,%eax\njmpq 14e8 \ncallq 1070 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\nmov r15, rcx\npush r14\npush r13\nmov r13, rdi\npush r12\nmov r12d, esi\npush rbx\nmovsxd rbx, edx\nlea r8, ds:0[rbx*4]\nmov r14, rbx\nsub rsp, 28h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nlea rax, [r8+0Fh]\nmov rcx, rsp\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_13CC\nloc_13B7:\nsub rsp, 1000h\nor [rsp+1050h+var_58], 0\ncmp rsp, rcx\njnz short loc_13B7\nloc_13CC:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1540\nloc_13DE:\nmov rcx, rsp\ntest r14d, r14d\njle loc_154B\nmov r9d, r14d\nmov rdi, rcx; dest\nmov rsi, r13; src\nmov [rbp+var_50], r8\nlea rdx, ds:0[r9*4]; n\nmov [rbp+var_48], r9\ncall _memcpy\nxor edx, edx\ncmp r14d, r12d\nmov r9, [rbp+var_48]\nmov r8, [rbp+var_50]\nmov rcx, rax\njge short loc_1474\nloc_141A:\ncmp r14d, r12d\nmov edx, r12d\nsetl dil\nsub edx, r14d\nlea eax, [rdx-1]\ncmp eax, 2\njbe short loc_1445\ntest dil, dil\njz short loc_1445\nlea rsi, [r13+r8+4]\nmov rax, r15\nsub rax, rsi\ncmp rax, 8\nja short loc_14B0\nloc_1445:\nmov rsi, r15\nsub rsi, r8\nnop dword ptr [rax+rax+00h]\nloc_1450:\nmov eax, [r13+rbx*4+0]\nmov [rsi+rbx*4], eax\nadd rbx, 1\ncmp r12d, ebx\njg short loc_1450\nloc_1461:\ntest dil, dil\nmov eax, 1\ncmovz edx, eax\ntest r14d, r14d\njle short loc_148B\nmov r9d, r14d\nloc_1474:\nmovsxd rdx, edx\nmov rsi, rcx; src\nlea rdi, [r15+rdx*4]; dest\nlea rdx, ds:0[r9*4]; n\ncall _memcpy\nloc_148B:\nmov rax, [rbp+var_38]\nsub rax, fs:28h\njnz loc_1559\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_14B0:\nmov esi, edx\nadd r8, r13\nxor eax, eax\nshr esi, 2\nshl rsi, 4\nxchg ax, ax\nloc_14C0:\nmovdqu xmm0, xmmword ptr [r8+rax]\nmovups xmmword ptr [r15+rax], xmm0\nadd rax, 10h\ncmp rax, rsi\njnz short loc_14C0\nmov eax, edx\nand eax, 0FFFFFFFCh\nlea esi, [r14+rax]\ntest dl, 3\njz loc_1461\nmovsxd r9, esi\ncdqe\nmov r9d, [r13+r9*4+0]\nlea r8, ds:0[rax*4]\nmov [r15+rax*4], r9d\nlea eax, [rsi+1]\ncmp r12d, eax\njle loc_1461\ncdqe\nadd esi, 2\nlea r9, ds:0[rax*4]\nmov eax, [r13+rax*4+0]\nmov [r15+r8+4], eax\ncmp r12d, esi\njle loc_1461\nmov eax, [r13+r9+4]\nmov [r15+r8+8], eax\njmp loc_1461\nloc_1540:\nor [rsp+rdx+1050h+var_1058], 0\njmp loc_13DE\nloc_154B:\ncmp r14d, r12d\njl loc_141A\njmp loc_148B\nloc_1559:\ncall ___stack_chk_fail", + "ida_pseudo": "unsigned __int64 __fastcall func0(char *src, int a2, int a3, __int64 a4)\n{\n __int64 v6; // rbx\n __int64 v7; // r8\n __int64 *v9; // rcx\n signed __int64 v10; // rdx\n void *v11; // rsp\n _BYTE *v12; // rcx\n _BYTE *v13; // rax\n int v14; // edx\n __int64 v15; // r9\n char *v17; // r8\n __int64 v18; // rax\n unsigned int v19; // esi\n __int64 v20; // r8\n __int64 v21; // r9\n _BYTE v23[4088]; // [rsp+8h] [rbp-1050h] BYREF\n __int64 v24; // [rsp+1008h] [rbp-50h] BYREF\n __int64 v25; // [rsp+1010h] [rbp-48h]\n unsigned __int64 v26; // [rsp+1020h] [rbp-38h]\n\n v6 = a3;\n v7 = 4LL * a3;\n v26 = __readfsqword(0x28u);\n v9 = (__int64 *)((char *)&v24 - ((v7 + 15) & 0xFFFFFFFFFFFFF000LL));\n if ( &v24 != v9 )\n {\n while ( v23 != (_BYTE *)v9 )\n ;\n }\n v10 = ((_WORD)v7 + 15) & 0xFF0;\n v11 = alloca(v10);\n if ( (((_WORD)v7 + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v23[v10 - 8] = *(_QWORD *)&v23[v10 - 8];\n v12 = v23;\n if ( a3 <= 0 )\n {\n if ( a3 >= a2 )\n return v26 - __readfsqword(0x28u);\n }\n else\n {\n v24 = v7;\n v25 = (unsigned int)a3;\n v13 = memcpy(v23, src, 4LL * (unsigned int)a3);\n v14 = 0;\n v15 = v25;\n v7 = v24;\n v12 = v13;\n if ( a3 >= a2 )\n {\nLABEL_15:\n memcpy((void *)(a4 + 4LL * v14), v12, 4 * v15);\n return v26 - __readfsqword(0x28u);\n }\n }\n v14 = a2 - a3;\n if ( (unsigned int)(a2 - a3 - 1) > 2 && a3 < a2 && (unsigned __int64)(a4 - (_QWORD)&src[v7 + 4]) > 8 )\n {\n v17 = &src[v7];\n v18 = 0LL;\n do\n {\n *(__m128i *)(a4 + v18) = _mm_loadu_si128((const __m128i *)&v17[v18]);\n v18 += 16LL;\n }\n while ( v18 != 16LL * ((unsigned int)v14 >> 2) );\n v19 = a3 + (v14 & 0xFFFFFFFC);\n if ( (v14 & 3) != 0 )\n {\n v20 = 4LL * (int)(v14 & 0xFFFFFFFC);\n *(_DWORD *)(a4 + v20) = *(_DWORD *)&src[4 * v19];\n if ( a2 > (int)(v19 + 1) )\n {\n v21 = 4LL * (int)(v19 + 1);\n *(_DWORD *)(a4 + v20 + 4) = *(_DWORD *)&src[v21];\n if ( a2 > (int)(v19 + 2) )\n *(_DWORD *)(a4 + v20 + 8) = *(_DWORD *)&src[v21 + 4];\n }\n }\n }\n else\n {\n do\n {\n *(_DWORD *)(a4 - v7 + 4 * v6) = *(_DWORD *)&src[4 * v6];\n ++v6;\n }\n while ( a2 > (int)v6 );\n }\n if ( a3 >= a2 )\n v14 = 1;\n if ( a3 > 0 )\n {\n v15 = (unsigned int)a3;\n goto LABEL_15;\n }\n return v26 - __readfsqword(0x28u);\n}", + "ida_strip_asm": "sub_1360:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\nmov r15, rcx\npush r14\npush r13\nmov r13, rdi\npush r12\nmov r12d, esi\npush rbx\nmovsxd rbx, edx\nlea r8, ds:0[rbx*4]\nmov r14, rbx\nsub rsp, 28h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nlea rax, [r8+0Fh]\nmov rcx, rsp\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_13CC\nloc_13B7:\nsub rsp, 1000h\nor [rsp+1050h+var_58], 0\ncmp rsp, rcx\njnz short loc_13B7\nloc_13CC:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1540\nloc_13DE:\nmov rcx, rsp\ntest r14d, r14d\njle loc_154B\nmov r9d, r14d\nmov rdi, rcx; dest\nmov rsi, r13; src\nmov [rbp+var_50], r8\nlea rdx, ds:0[r9*4]; n\nmov [rbp+var_48], r9\ncall _memcpy\nxor edx, edx\ncmp r14d, r12d\nmov r9, [rbp+var_48]\nmov r8, [rbp+var_50]\nmov rcx, rax\njge short loc_1474\nloc_141A:\ncmp r14d, r12d\nmov edx, r12d\nsetl dil\nsub edx, r14d\nlea eax, [rdx-1]\ncmp eax, 2\njbe short loc_1445\ntest dil, dil\njz short loc_1445\nlea rsi, [r13+r8+4]\nmov rax, r15\nsub rax, rsi\ncmp rax, 8\nja short loc_14B0\nloc_1445:\nmov rsi, r15\nsub rsi, r8\nnop dword ptr [rax+rax+00h]\nloc_1450:\nmov eax, [r13+rbx*4+0]\nmov [rsi+rbx*4], eax\nadd rbx, 1\ncmp r12d, ebx\njg short loc_1450\nloc_1461:\ntest dil, dil\nmov eax, 1\ncmovz edx, eax\ntest r14d, r14d\njle short loc_148B\nmov r9d, r14d\nloc_1474:\nmovsxd rdx, edx\nmov rsi, rcx; src\nlea rdi, [r15+rdx*4]; dest\nlea rdx, ds:0[r9*4]; n\ncall _memcpy\nloc_148B:\nmov rax, [rbp+var_38]\nsub rax, fs:28h\njnz loc_1559\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_14B0:\nmov esi, edx\nadd r8, r13\nxor eax, eax\nshr esi, 2\nshl rsi, 4\nxchg ax, ax\nloc_14C0:\nmovdqu xmm0, xmmword ptr [r8+rax]\nmovups xmmword ptr [r15+rax], xmm0\nadd rax, 10h\ncmp rax, rsi\njnz short loc_14C0\nmov eax, edx\nand eax, 0FFFFFFFCh\nlea esi, [r14+rax]\ntest dl, 3\njz loc_1461\nmovsxd r9, esi\ncdqe\nmov r9d, [r13+r9*4+0]\nlea r8, ds:0[rax*4]\nmov [r15+rax*4], r9d\nlea eax, [rsi+1]\ncmp r12d, eax\njle loc_1461\ncdqe\nadd esi, 2\nlea r9, ds:0[rax*4]\nmov eax, [r13+rax*4+0]\nmov [r15+r8+4], eax\ncmp r12d, esi\njle loc_1461\nmov eax, [r13+r9+4]\nmov [r15+r8+8], eax\njmp loc_1461\nloc_1540:\nor [rsp+rdx+1050h+var_1058], 0\njmp loc_13DE\nloc_154B:\ncmp r14d, r12d\njl loc_141A\njmp loc_148B\nloc_1559:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_1360(char *src, int a2, int a3, __int64 a4)\n{\n __int64 v6; // rbx\n __int64 v7; // r8\n __int64 *v9; // rcx\n signed __int64 v10; // rdx\n void *v11; // rsp\n _BYTE *v12; // rcx\n _BYTE *v13; // rax\n int v14; // edx\n __int64 v15; // r9\n char *v17; // r8\n __int64 v18; // rax\n unsigned int v19; // esi\n __int64 v20; // r8\n __int64 v21; // r9\n _BYTE v23[4088]; // [rsp+8h] [rbp-1050h] BYREF\n __int64 v24; // [rsp+1008h] [rbp-50h] BYREF\n __int64 v25; // [rsp+1010h] [rbp-48h]\n unsigned __int64 v26; // [rsp+1020h] [rbp-38h]\n\n v6 = a3;\n v7 = 4LL * a3;\n v26 = __readfsqword(0x28u);\n v9 = (__int64 *)((char *)&v24 - ((v7 + 15) & 0xFFFFFFFFFFFFF000LL));\n if ( &v24 != v9 )\n {\n while ( v23 != (_BYTE *)v9 )\n ;\n }\n v10 = ((_WORD)v7 + 15) & 0xFF0;\n v11 = alloca(v10);\n if ( (((_WORD)v7 + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v23[v10 - 8] = *(_QWORD *)&v23[v10 - 8];\n v12 = v23;\n if ( a3 <= 0 )\n {\n if ( a3 >= a2 )\n return v26 - __readfsqword(0x28u);\n }\n else\n {\n v24 = v7;\n v25 = (unsigned int)a3;\n v13 = memcpy(v23, src, 4LL * (unsigned int)a3);\n v14 = 0;\n v15 = v25;\n v7 = v24;\n v12 = v13;\n if ( a3 >= a2 )\n {\nLABEL_15:\n memcpy((void *)(a4 + 4LL * v14), v12, 4 * v15);\n return v26 - __readfsqword(0x28u);\n }\n }\n v14 = a2 - a3;\n if ( (unsigned int)(a2 - a3 - 1) > 2 && a3 < a2 && (unsigned __int64)(a4 - (_QWORD)&src[v7 + 4]) > 8 )\n {\n v17 = &src[v7];\n v18 = 0LL;\n do\n {\n *(__m128i *)(a4 + v18) = _mm_loadu_si128((const __m128i *)&v17[v18]);\n v18 += 16LL;\n }\n while ( v18 != 16LL * ((unsigned int)v14 >> 2) );\n v19 = a3 + (v14 & 0xFFFFFFFC);\n if ( (v14 & 3) != 0 )\n {\n v20 = 4LL * (int)(v14 & 0xFFFFFFFC);\n *(_DWORD *)(a4 + v20) = *(_DWORD *)&src[4 * v19];\n if ( a2 > (int)(v19 + 1) )\n {\n v21 = 4LL * (int)(v19 + 1);\n *(_DWORD *)(a4 + v20 + 4) = *(_DWORD *)&src[v21];\n if ( a2 > (int)(v19 + 2) )\n *(_DWORD *)(a4 + v20 + 8) = *(_DWORD *)&src[v21 + 4];\n }\n }\n }\n else\n {\n do\n {\n *(_DWORD *)(a4 - v7 + 4 * v6) = *(_DWORD *)&src[4 * v6];\n ++v6;\n }\n while ( a2 > (int)v6 );\n }\n if ( a3 >= a2 )\n v14 = 1;\n if ( a3 > 0 )\n {\n v15 = (unsigned int)a3;\n goto LABEL_15;\n }\n return v26 - __readfsqword(0x28u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_1360(char *src, int a2, int a3, long long a4) {\n long long v6;\n long long v7;\n long long *v9;\n signed long long v10;\n void *v11;\n uint8_t *v12;\n uint8_t *v13;\n int v14;\n long long v15;\n char *v17;\n long long v18;\n unsigned int v19;\n long long v20;\n long long v21;\n uint8_t v23[4088];\n long long v24;\n long long v25;\n unsigned long long v26;\n v6 = a3;\n v7 = 4LL * a3;\n v26 = __readfsqword(40u);\n v9 = (long long *)((char *)&v24 - ((v7 + 15) & 18446744073709547520LL));\n if (&v24 != v9) {\n while (v23 != (uint8_t *)v9)\n ;\n }\n v10 = ((unsigned short)v7 + 15) & 4080;\n v11 = alloca(v10);\n if ((((unsigned short)v7 + 15) & 4080) != 0)\n *(uint64_t *)&v23[v10 - 8] = *(uint64_t *)&v23[v10 - 8];\n v12 = v23;\n if (a3 <= 0) {\n if (a3 >= a2) return v26 - __readfsqword(40u);\n } else {\n v24 = v7;\n v25 = (unsigned int)a3;\n v13 = memcpy(v23, src, 4LL * (unsigned int)a3);\n v14 = 0;\n v15 = v25;\n v7 = v24;\n v12 = v13;\n if (a3 >= a2) {\n LABEL_15:\n memcpy((void *)(a4 + 4LL * v14), v12, 4 * v15);\n return v26 - __readfsqword(40u);\n }\n }\n v14 = a2 - a3;\n if ((unsigned int)(a2 - a3 - 1) > 2 && a3 < a2 &&\n (unsigned long long)(a4 - (uint64_t)&src[v7 + 4]) > 8) {\n v17 = &src[v7];\n v18 = 0LL;\n do {\n *(__m128i *)(a4 + v18) = _mm_loadu_si128((const __m128i *)&v17[v18]);\n v18 += 16LL;\n } while (v18 != 16LL * ((unsigned int)v14 >> 2));\n v19 = a3 + (v14 & 4294967292);\n if ((v14 & 3) != 0) {\n v20 = 4LL * (int)(v14 & 4294967292);\n *(uint32_t *)(a4 + v20) = *(uint32_t *)&src[4 * v19];\n if (a2 > (int)(v19 + 1)) {\n v21 = 4LL * (int)(v19 + 1);\n *(uint32_t *)(a4 + v20 + 4) = *(uint32_t *)&src[v21];\n if (a2 > (int)(v19 + 2))\n *(uint32_t *)(a4 + v20 + 8) = *(uint32_t *)&src[v21 + 4];\n }\n }\n } else {\n do {\n *(uint32_t *)(a4 - v7 + 4 * v6) = *(uint32_t *)&src[4 * v6];\n ++v6;\n } while (a2 > (int)v6);\n }\n if (a3 >= a2) v14 = 1;\n if (a3 > 0) {\n v15 = (unsigned int)a3;\n goto LABEL_15;\n }\n return v26 - __readfsqword(40u);\n}", + "ida_pseudo_norm": "unsigned long long func0(char *src, int a2, int a3, long long a4) {\n long long v6;\n long long v7;\n long long *v9;\n signed long long v10;\n void *v11;\n uint8_t *v12;\n uint8_t *v13;\n int v14;\n long long v15;\n char *v17;\n long long v18;\n unsigned int v19;\n long long v20;\n long long v21;\n uint8_t v23[4088];\n long long v24;\n long long v25;\n unsigned long long v26;\n v6 = a3;\n v7 = 4LL * a3;\n v26 = __readfsqword(40u);\n v9 = (long long *)((char *)&v24 - ((v7 + 15) & 18446744073709547520LL));\n if (&v24 != v9) {\n while (v23 != (uint8_t *)v9)\n ;\n }\n v10 = ((unsigned short)v7 + 15) & 4080;\n v11 = alloca(v10);\n if ((((unsigned short)v7 + 15) & 4080) != 0)\n *(uint64_t *)&v23[v10 - 8] = *(uint64_t *)&v23[v10 - 8];\n v12 = v23;\n if (a3 <= 0) {\n if (a3 >= a2) return v26 - __readfsqword(40u);\n } else {\n v24 = v7;\n v25 = (unsigned int)a3;\n v13 = memcpy(v23, src, 4LL * (unsigned int)a3);\n v14 = 0;\n v15 = v25;\n v7 = v24;\n v12 = v13;\n if (a3 >= a2) {\n LABEL_15:\n memcpy((void *)(a4 + 4LL * v14), v12, 4 * v15);\n return v26 - __readfsqword(40u);\n }\n }\n v14 = a2 - a3;\n if ((unsigned int)(a2 - a3 - 1) > 2 && a3 < a2 &&\n (unsigned long long)(a4 - (uint64_t)&src[v7 + 4]) > 8) {\n v17 = &src[v7];\n v18 = 0LL;\n do {\n *(__m128i *)(a4 + v18) = _mm_loadu_si128((const __m128i *)&v17[v18]);\n v18 += 16LL;\n } while (v18 != 16LL * ((unsigned int)v14 >> 2));\n v19 = a3 + (v14 & 4294967292);\n if ((v14 & 3) != 0) {\n v20 = 4LL * (int)(v14 & 4294967292);\n *(uint32_t *)(a4 + v20) = *(uint32_t *)&src[4 * v19];\n if (a2 > (int)(v19 + 1)) {\n v21 = 4LL * (int)(v19 + 1);\n *(uint32_t *)(a4 + v20 + 4) = *(uint32_t *)&src[v21];\n if (a2 > (int)(v19 + 2))\n *(uint32_t *)(a4 + v20 + 8) = *(uint32_t *)&src[v21 + 4];\n }\n }\n } else {\n do {\n *(uint32_t *)(a4 - v7 + 4 * v6) = *(uint32_t *)&src[4 * v6];\n ++v6;\n } while (a2 > (int)v6);\n }\n if (a3 >= a2) v14 = 1;\n if (a3 > 0) {\n v15 = (unsigned int)a3;\n goto LABEL_15;\n }\n return v26 - __readfsqword(40u);\n}" + }, + { + "index": 587, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n", + "func": "void *func0(int *listx, int size, int *result) {\n for (int i = 0; i < size; i++) {\n result[i] = listx[i];\n }\n return result;\n}", + "test": "int main() {\n\n int result1[6];\n\n int list1[6] = {5, 10, 7, 4, 15, 3};\n\n func0(list1, 6, result1);\n\n assert(memcmp(result1, (int[]){5, 10, 7, 4, 15, 3}, sizeof(result1)) == 0);\n\n\n\n int result2[9];\n\n int list2[9] = {2, 4, 5, 6, 2, 3, 4, 4, 7};\n\n func0(list2, 9, result2);\n\n assert(memcmp(result2, (int[]){2, 4, 5, 6, 2, 3, 4, 4, 7}, sizeof(result2)) == 0);\n\n\n\n int result3[3];\n\n int list3[3] = {58, 44, 56};\n\n func0(list3, 3, result3);\n\n assert(memcmp(result3, (int[]){58, 44, 56}, sizeof(result3)) == 0);\n\n \n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11f6 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0x4(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x28(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11c5 \nmov -0x28(%rbp),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_4], 0\njmp short loc_11F6\nloc_11C5:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_4], 1\nloc_11F6:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11C5\nmov rax, [rbp+var_28]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3)\n{\n int i; // [rsp+24h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n *(_DWORD *)(4LL * i + a3) = *(_DWORD *)(4LL * i + a1);\n return a3;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_4], 0\njmp short loc_11F6\nloc_11C5:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_4], 1\nloc_11F6:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11C5\nmov rax, [rbp+var_28]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(__int64 a1, int a2, __int64 a3)\n{\n int i; // [rsp+24h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n *(_DWORD *)(4LL * i + a3) = *(_DWORD *)(4LL * i + a1);\n return a3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(long long a1, int a2, long long a3) {\n int i;\n for (i = 0; i < a2; ++i)\n *(uint32_t *)(4LL * i + a3) = *(uint32_t *)(4LL * i + a1);\n return a3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3) {\n int i;\n for (i = 0; i < a2; ++i)\n *(uint32_t *)(4LL * i + a3) = *(uint32_t *)(4LL * i + a1);\n return a3;\n}" + }, + { + "index": 587, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n", + "func": "void *func0(int *listx, int size, int *result) {\n for (int i = 0; i < size; i++) {\n result[i] = listx[i];\n }\n return result;\n}", + "test": "int main() {\n\n int result1[6];\n\n int list1[6] = {5, 10, 7, 4, 15, 3};\n\n func0(list1, 6, result1);\n\n assert(memcmp(result1, (int[]){5, 10, 7, 4, 15, 3}, sizeof(result1)) == 0);\n\n\n\n int result2[9];\n\n int list2[9] = {2, 4, 5, 6, 2, 3, 4, 4, 7};\n\n func0(list2, 9, result2);\n\n assert(memcmp(result2, (int[]){2, 4, 5, 6, 2, 3, 4, 4, 7}, sizeof(result2)) == 0);\n\n\n\n int result3[3];\n\n int list3[3] = {58, 44, 56};\n\n func0(list3, 3, result3);\n\n assert(memcmp(result3, (int[]){58, 44, 56}, sizeof(result3)) == 0);\n\n \n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdx,%rax\ntest %esi,%esi\njle 11ce \nlea -0x1(%rsi),%edx\nmov $0x0,%ecx\nmov (%rdi,%rcx,4),%esi\nmov %esi,(%rax,%rcx,4)\nmov %rcx,%rsi\nadd $0x1,%rcx\ncmp %rdx,%rsi\njne 11bc \nretq\n", + "ida_asm": "func0:\nendbr64\nmov rax, rdx\ntest esi, esi\njle short locret_11D3\nmovsxd rsi, esi\nlea r8, ds:0[rsi*4]\nmov ecx, 0\nloc_11C4:\nmov esi, [rdi+rcx]\nmov [rax+rcx], esi\nadd rcx, 4\ncmp rcx, r8\njnz short loc_11C4\nlocret_11D3:\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3)\n{\n __int64 result; // rax\n __int64 v4; // rcx\n\n result = a3;\n if ( a2 > 0 )\n {\n v4 = 0LL;\n do\n {\n *(_DWORD *)(a3 + v4) = *(_DWORD *)(a1 + v4);\n v4 += 4LL;\n }\n while ( v4 != 4LL * a2 );\n }\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\nmov rax, rdx\ntest esi, esi\njle short locret_11D3\nmovsxd rsi, esi\nlea r8, ds:0[rsi*4]\nmov ecx, 0\nloc_11C4:\nmov esi, [rdi+rcx]\nmov [rax+rcx], esi\nadd rcx, 4\ncmp rcx, r8\njnz short loc_11C4\nlocret_11D3:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(__int64 a1, int a2, __int64 a3)\n{\n __int64 result; // rax\n __int64 v4; // rcx\n\n result = a3;\n if ( a2 > 0 )\n {\n v4 = 0LL;\n do\n {\n *(_DWORD *)(a3 + v4) = *(_DWORD *)(a1 + v4);\n v4 += 4LL;\n }\n while ( v4 != 4LL * a2 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(long long a1, int a2, long long a3) {\n long long result;\n long long v4;\n result = a3;\n if (a2 > 0) {\n v4 = 0LL;\n do {\n *(uint32_t *)(a3 + v4) = *(uint32_t *)(a1 + v4);\n v4 += 4LL;\n } while (v4 != 4LL * a2);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3) {\n long long result;\n long long v4;\n result = a3;\n if (a2 > 0) {\n v4 = 0LL;\n do {\n *(uint32_t *)(a3 + v4) = *(uint32_t *)(a1 + v4);\n v4 += 4LL;\n } while (v4 != 4LL * a2);\n }\n return result;\n}" + }, + { + "index": 588, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int nums[], int size) {\n int max_val = INT_MIN;\n int min_val = INT_MAX;\n for (int i = 0; i < size; i++) {\n if (nums[i] > max_val) {\n max_val = nums[i];\n }\n if (nums[i] < min_val) {\n min_val = nums[i];\n }\n }\n return max_val - min_val;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4};\n\n int arr2[] = {4, 5, 12};\n\n int arr3[] = {9, 2, 3};\n\n assert(func0(arr1, 4) == 3);\n\n assert(func0(arr2, 3) == 8);\n\n assert(func0(arr3, 3) == 7);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x80000000,-0xc(%rbp)\nmovl $0x7fffffff,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11fb \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0xc(%rbp)\njge 11c3 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0xc(%rbp)\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x8(%rbp)\njle 11f7 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 118f \nmov -0xc(%rbp),%eax\nsub -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 80000000h\nmov [rbp+var_8], 7FFFFFFFh\nmov [rbp+var_4], 0\njmp short loc_11FB\nloc_118F:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_C], eax\njge short loc_11C3\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nloc_11C3:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_8], eax\njle short loc_11F7\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_8], eax\nloc_11F7:\nadd [rbp+var_4], 1\nloc_11FB:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_118F\nmov eax, [rbp+var_C]\nsub eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n signed int v3; // [rsp+10h] [rbp-Ch]\n int v4; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0x80000000;\n v4 = 0x7FFFFFFF;\n for ( i = 0; i < a2; ++i )\n {\n if ( v3 < *(_DWORD *)(4LL * i + a1) )\n v3 = *(_DWORD *)(4LL * i + a1);\n if ( v4 > *(_DWORD *)(4LL * i + a1) )\n v4 = *(_DWORD *)(4LL * i + a1);\n }\n return (unsigned int)(v3 - v4);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 80000000h\nmov [rbp+var_8], 7FFFFFFFh\nmov [rbp+var_4], 0\njmp short loc_11FB\nloc_118F:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_C], eax\njge short loc_11C3\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nloc_11C3:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_8], eax\njle short loc_11F7\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_8], eax\nloc_11F7:\nadd [rbp+var_4], 1\nloc_11FB:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_118F\nmov eax, [rbp+var_C]\nsub eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n signed int v3; // [rsp+10h] [rbp-Ch]\n int v4; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0x80000000;\n v4 = 0x7FFFFFFF;\n for ( i = 0; i < a2; ++i )\n {\n if ( v3 < *(_DWORD *)(4LL * i + a1) )\n v3 = *(_DWORD *)(4LL * i + a1);\n if ( v4 > *(_DWORD *)(4LL * i + a1) )\n v4 = *(_DWORD *)(4LL * i + a1);\n }\n return (unsigned int)(v3 - v4);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n signed int v3;\n int v4;\n int i;\n v3 = 2147483648;\n v4 = 2147483647;\n for (i = 0; i < a2; ++i) {\n if (v3 < *(uint32_t *)(4LL * i + a1)) v3 = *(uint32_t *)(4LL * i + a1);\n if (v4 > *(uint32_t *)(4LL * i + a1)) v4 = *(uint32_t *)(4LL * i + a1);\n }\n return (unsigned int)(v3 - v4);\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n signed int v3;\n int v4;\n int i;\n v3 = 2147483648;\n v4 = 2147483647;\n for (i = 0; i < a2; ++i) {\n if (v3 < *(uint32_t *)(4LL * i + a1)) v3 = *(uint32_t *)(4LL * i + a1);\n if (v4 > *(uint32_t *)(4LL * i + a1)) v4 = *(uint32_t *)(4LL * i + a1);\n }\n return (unsigned int)(v3 - v4);\n}" + }, + { + "index": 588, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int nums[], int size) {\n int max_val = INT_MIN;\n int min_val = INT_MAX;\n for (int i = 0; i < size; i++) {\n if (nums[i] > max_val) {\n max_val = nums[i];\n }\n if (nums[i] < min_val) {\n min_val = nums[i];\n }\n }\n return max_val - min_val;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4};\n\n int arr2[] = {4, 5, 12};\n\n int arr3[] = {9, 2, 3};\n\n assert(func0(arr1, 4) == 3);\n\n assert(func0(arr2, 3) == 8);\n\n assert(func0(arr3, 3) == 7);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 119e \nmov %rdi,%rcx\nlea -0x1(%rsi),%eax\nlea 0x4(%rdi,%rax,4),%rdi\nmov $0x7fffffff,%esi\nmov $0x80000000,%eax\nmov (%rcx),%edx\ncmp %edx,%eax\ncmovl %edx,%eax\ncmp %edx,%esi\ncmovg %edx,%esi\nadd $0x4,%rcx\ncmp %rdi,%rcx\njne 1186 \nsub %esi,%eax\nretq\nmov $0x7fffffff,%esi\nmov $0x80000000,%eax\njmp 119b \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_119D\nmov rcx, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*4]\nmov esi, 7FFFFFFFh\nmov eax, 80000000h\nloc_1185:\nmov edx, [rcx]\ncmp eax, edx\ncmovl eax, edx\ncmp esi, edx\ncmovg esi, edx\nadd rcx, 4\ncmp rcx, rdi\njnz short loc_1185\nloc_119A:\nsub eax, esi\nretn\nloc_119D:\nmov esi, 7FFFFFFFh\nmov eax, 80000000h\njmp short loc_119A", + "ida_pseudo": "__int64 __fastcall func0(signed int *a1, int a2)\n{\n signed int *v2; // rcx\n signed int *v3; // rdi\n int v4; // esi\n signed int v5; // eax\n\n if ( a2 <= 0 )\n {\n v4 = 0x7FFFFFFF;\n v5 = 0x80000000;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0x7FFFFFFF;\n v5 = 0x80000000;\n do\n {\n if ( v5 < *v2 )\n v5 = *v2;\n if ( v4 > *v2 )\n v4 = *v2;\n ++v2;\n }\n while ( v2 != v3 );\n }\n return (unsigned int)(v5 - v4);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_119D\nmov rcx, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*4]\nmov esi, 7FFFFFFFh\nmov eax, 80000000h\nloc_1185:\nmov edx, [rcx]\ncmp eax, edx\ncmovl eax, edx\ncmp esi, edx\ncmovg esi, edx\nadd rcx, 4\ncmp rcx, rdi\njnz short loc_1185\nloc_119A:\nsub eax, esi\nretn\nloc_119D:\nmov esi, 7FFFFFFFh\nmov eax, 80000000h\njmp short loc_119A", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(signed int *a1, int a2)\n{\n signed int *v2; // rcx\n signed int *v3; // rdi\n int v4; // esi\n signed int v5; // eax\n\n if ( a2 <= 0 )\n {\n v4 = 0x7FFFFFFF;\n v5 = 0x80000000;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0x7FFFFFFF;\n v5 = 0x80000000;\n do\n {\n if ( v5 < *v2 )\n v5 = *v2;\n if ( v4 > *v2 )\n v4 = *v2;\n ++v2;\n }\n while ( v2 != v3 );\n }\n return (unsigned int)(v5 - v4);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(signed int *a1, int a2) {\n signed int *v2;\n signed int *v3;\n int v4;\n signed int v5;\n if (a2 <= 0) {\n v4 = 2147483647;\n v5 = 2147483648;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 2147483647;\n v5 = 2147483648;\n do {\n if (v5 < *v2) v5 = *v2;\n if (v4 > *v2) v4 = *v2;\n ++v2;\n } while (v2 != v3);\n }\n return (unsigned int)(v5 - v4);\n}", + "ida_pseudo_norm": "long long func0(signed int *a1, int a2) {\n signed int *v2;\n signed int *v3;\n int v4;\n signed int v5;\n if (a2 <= 0) {\n v4 = 2147483647;\n v5 = 2147483648;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 2147483647;\n v5 = 2147483648;\n do {\n if (v5 < *v2) v5 = *v2;\n if (v4 > *v2) v4 = *v2;\n ++v2;\n } while (v2 != v3);\n }\n return (unsigned int)(v5 - v4);\n}" + }, + { + "index": 589, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int a, int b, int* size) {\n int* lists = malloc((b - a + 1) * sizeof(int));\n int idx = 0;\n for (int i = a; i <= b; i++) {\n int j = 1;\n while (j * j <= i) {\n if (j * j == i) {\n lists[idx++] = i;\n break;\n }\n j++;\n }\n }\n *size = idx;\n return lists;\n}", + "test": "int main() {\n\n int size;\n\n int *result;\n\n\n\n result = func0(1, 30, &size);\n\n int expected_1[] = {1, 4, 9, 16, 25};\n\n int expected_1_size = sizeof(expected_1) / sizeof(expected_1[0]);\n\n assert(size == expected_1_size);\n\n for (int i = 0; i < size; i++) {\n\n assert(result[i] == expected_1[i]);\n\n }\n\n free(result);\n\n\n\n result = func0(50, 100, &size);\n\n int expected_2[] = {64, 81, 100};\n\n int expected_2_size = sizeof(expected_2) / sizeof(expected_2[0]);\n\n assert(size == expected_2_size);\n\n for (int i = 0; i < size; i++) {\n\n assert(result[i] == expected_2[i]);\n\n }\n\n free(result);\n\n\n\n result = func0(100, 200, &size);\n\n int expected_3[] = {100, 121, 144, 169, 196};\n\n int expected_3_size = sizeof(expected_3) / sizeof(expected_3[0]);\n\n assert(size == expected_3_size);\n\n for (int i = 0; i < size; i++) {\n\n assert(result[i] == expected_3[i]);\n\n }\n\n free(result);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %edi,-0x24(%rbp)\nmov %esi,-0x28(%rbp)\nmov %rdx,-0x30(%rbp)\nmov -0x28(%rbp),%eax\nsub -0x24(%rbp),%eax\nadd $0x1,%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0x14(%rbp)\nmov -0x24(%rbp),%eax\nmov %eax,-0x10(%rbp)\njmp 1231 \nmovl $0x1,-0xc(%rbp)\njmp 1222 \nmov -0xc(%rbp),%eax\nimul %eax,%eax\ncmp %eax,-0x10(%rbp)\njne 121e \nmov -0x14(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x14(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov -0x10(%rbp),%eax\nmov %eax,(%rdx)\njmp 122d \naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\nimul %eax,%eax\ncmp %eax,-0x10(%rbp)\njge 11f2 \naddl $0x1,-0x10(%rbp)\nmov -0x10(%rbp),%eax\ncmp -0x28(%rbp),%eax\njle 11e9 \nmov -0x30(%rbp),%rax\nmov -0x14(%rbp),%edx\nmov %edx,(%rax)\nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_24], edi\nmov [rbp+var_28], esi\nmov [rbp+var_30], rdx\nmov eax, [rbp+var_28]\nsub eax, [rbp+var_24]\nadd eax, 1\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_14], 0\nmov eax, [rbp+var_24]\nmov [rbp+var_10], eax\njmp short loc_1231\nloc_11E9:\nmov [rbp+var_C], 1\njmp short loc_1222\nloc_11F2:\nmov eax, [rbp+var_C]\nimul eax, eax\ncmp [rbp+var_10], eax\njnz short loc_121E\nmov eax, [rbp+var_14]\nlea edx, [rax+1]\nmov [rbp+var_14], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_10]\nmov [rdx], eax\njmp short loc_122D\nloc_121E:\nadd [rbp+var_C], 1\nloc_1222:\nmov eax, [rbp+var_C]\nimul eax, eax\ncmp [rbp+var_10], eax\njge short loc_11F2\nloc_122D:\nadd [rbp+var_10], 1\nloc_1231:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_28]\njle short loc_11E9\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_14]\nmov [rax], edx\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int a1, int a2, _DWORD *a3)\n{\n int v3; // eax\n int v6; // [rsp+1Ch] [rbp-14h]\n int i; // [rsp+20h] [rbp-10h]\n int j; // [rsp+24h] [rbp-Ch]\n _DWORD *v9; // [rsp+28h] [rbp-8h]\n\n v9 = malloc(4LL * (a2 - a1 + 1));\n v6 = 0;\n for ( i = a1; i <= a2; ++i )\n {\n for ( j = 1; i >= j * j; ++j )\n {\n if ( i == j * j )\n {\n v3 = v6++;\n v9[v3] = i;\n break;\n }\n }\n }\n *a3 = v6;\n return v9;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_24], edi\nmov [rbp+var_28], esi\nmov [rbp+var_30], rdx\nmov eax, [rbp+var_28]\nsub eax, [rbp+var_24]\nadd eax, 1\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_14], 0\nmov eax, [rbp+var_24]\nmov [rbp+var_10], eax\njmp short loc_1231\nloc_11E9:\nmov [rbp+var_C], 1\njmp short loc_1222\nloc_11F2:\nmov eax, [rbp+var_C]\nimul eax, eax\ncmp [rbp+var_10], eax\njnz short loc_121E\nmov eax, [rbp+var_14]\nlea edx, [rax+1]\nmov [rbp+var_14], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_10]\nmov [rdx], eax\njmp short loc_122D\nloc_121E:\nadd [rbp+var_C], 1\nloc_1222:\nmov eax, [rbp+var_C]\nimul eax, eax\ncmp [rbp+var_10], eax\njge short loc_11F2\nloc_122D:\nadd [rbp+var_10], 1\nloc_1231:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_28]\njle short loc_11E9\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_14]\nmov [rax], edx\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(int a1, int a2, _DWORD *a3)\n{\n int v3; // eax\n int v6; // [rsp+1Ch] [rbp-14h]\n int i; // [rsp+20h] [rbp-10h]\n int j; // [rsp+24h] [rbp-Ch]\n _DWORD *v9; // [rsp+28h] [rbp-8h]\n\n v9 = malloc(4LL * (a2 - a1 + 1));\n v6 = 0;\n for ( i = a1; i <= a2; ++i )\n {\n for ( j = 1; i >= j * j; ++j )\n {\n if ( i == j * j )\n {\n v3 = v6++;\n v9[v3] = i;\n break;\n }\n }\n }\n *a3 = v6;\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(int a1, int a2, uint32_t *a3) {\n int v3;\n int v6;\n int i;\n int j;\n uint32_t *v9;\n v9 = malloc(4LL * (a2 - a1 + 1));\n v6 = 0;\n for (i = a1; i <= a2; ++i) {\n for (j = 1; i >= j * j; ++j) {\n if (i == j * j) {\n v3 = v6++;\n v9[v3] = i;\n break;\n }\n }\n }\n *a3 = v6;\n return v9;\n}", + "ida_pseudo_norm": "uint32_t *func0(int a1, int a2, uint32_t *a3) {\n int v3;\n int v6;\n int i;\n int j;\n uint32_t *v9;\n v9 = malloc(4LL * (a2 - a1 + 1));\n v6 = 0;\n for (i = a1; i <= a2; ++i) {\n for (j = 1; i >= j * j; ++j) {\n if (i == j * j) {\n v3 = v6++;\n v9[v3] = i;\n break;\n }\n }\n }\n *a3 = v6;\n return v9;\n}" + }, + { + "index": 589, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int a, int b, int* size) {\n int* lists = malloc((b - a + 1) * sizeof(int));\n int idx = 0;\n for (int i = a; i <= b; i++) {\n int j = 1;\n while (j * j <= i) {\n if (j * j == i) {\n lists[idx++] = i;\n break;\n }\n j++;\n }\n }\n *size = idx;\n return lists;\n}", + "test": "int main() {\n\n int size;\n\n int *result;\n\n\n\n result = func0(1, 30, &size);\n\n int expected_1[] = {1, 4, 9, 16, 25};\n\n int expected_1_size = sizeof(expected_1) / sizeof(expected_1[0]);\n\n assert(size == expected_1_size);\n\n for (int i = 0; i < size; i++) {\n\n assert(result[i] == expected_1[i]);\n\n }\n\n free(result);\n\n\n\n result = func0(50, 100, &size);\n\n int expected_2[] = {64, 81, 100};\n\n int expected_2_size = sizeof(expected_2) / sizeof(expected_2[0]);\n\n assert(size == expected_2_size);\n\n for (int i = 0; i < size; i++) {\n\n assert(result[i] == expected_2[i]);\n\n }\n\n free(result);\n\n\n\n result = func0(100, 200, &size);\n\n int expected_3[] = {100, 121, 144, 169, 196};\n\n int expected_3_size = sizeof(expected_3) / sizeof(expected_3[0]);\n\n assert(size == expected_3_size);\n\n for (int i = 0; i < size; i++) {\n\n assert(result[i] == expected_3[i]);\n\n }\n\n free(result);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmov %edi,%ebx\nmov %esi,%r12d\nmov %rdx,%rbp\nmov %esi,%edi\nsub %ebx,%edi\nadd $0x1,%edi\nmovslq %edi,%rdi\nshl $0x2,%rdi\ncallq 10b0 \ncmp %ebx,%r12d\njl 120b \nlea 0x1(%r12),%edi\nmov $0x0,%esi\njmp 11ed \nmovslq %esi,%rdx\nmov %ebx,(%rax,%rdx,4)\nlea 0x1(%rsi),%esi\nadd $0x1,%ebx\ncmp %ebx,%edi\nje 1210 \ntest %ebx,%ebx\njle 11e6 \ncmp $0x1,%ebx\nje 11dd \nmov $0x1,%edx\nadd $0x1,%edx\nmov %edx,%ecx\nimul %edx,%ecx\ncmp %ebx,%ecx\njg 11e6 \njne 11fb \njmp 11dd \nmov $0x0,%esi\nmov %esi,0x0(%rbp)\npop %rbx\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov ebx, edi\nmov r12d, esi\nmov rbp, rdx\nmov edi, esi\nsub edi, ebx\nadd edi, 1\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\ncmp r12d, ebx\njl short loc_120B\nlea edi, [r12+1]\nmov esi, 0\njmp short loc_11ED\nloc_11DD:\nmovsxd rdx, esi\nmov [rax+rdx*4], ebx\nlea esi, [rsi+1]\nloc_11E6:\nadd ebx, 1\ncmp ebx, edi\njz short loc_1210\nloc_11ED:\ntest ebx, ebx\njle short loc_11E6\ncmp ebx, 1\njz short loc_11DD\nmov edx, 1\nloc_11FB:\nadd edx, 1\nmov ecx, edx\nimul ecx, edx\ncmp ecx, ebx\njg short loc_11E6\njnz short loc_11FB\njmp short loc_11DD\nloc_120B:\nmov esi, 0\nloc_1210:\nmov [rbp+0], esi\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int a1, int a2, _DWORD *a3)\n{\n int v3; // ebx\n _DWORD *result; // rax\n int v7; // esi\n int v8; // edx\n\n v3 = a1;\n result = malloc(4LL * (a2 - a1 + 1));\n if ( a2 < a1 )\n {\n v7 = 0;\n }\n else\n {\n v7 = 0;\n do\n {\n if ( v3 > 0 )\n {\n if ( v3 == 1 )\n {\nLABEL_3:\n result[v7++] = v3;\n }\n else\n {\n v8 = 1;\n while ( 1 )\n {\n ++v8;\n if ( v8 * v8 > v3 )\n break;\n if ( v8 * v8 == v3 )\n goto LABEL_3;\n }\n }\n }\n ++v3;\n }\n while ( v3 != a2 + 1 );\n }\n *a3 = v7;\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r12\npush rbp\npush rbx\nmov ebx, edi\nmov r12d, esi\nmov rbp, rdx\nmov edi, esi\nsub edi, ebx\nadd edi, 1\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\ncmp r12d, ebx\njl short loc_120B\nlea edi, [r12+1]\nmov esi, 0\njmp short loc_11ED\nloc_11DD:\nmovsxd rdx, esi\nmov [rax+rdx*4], ebx\nlea esi, [rsi+1]\nloc_11E6:\nadd ebx, 1\ncmp ebx, edi\njz short loc_1210\nloc_11ED:\ntest ebx, ebx\njle short loc_11E6\ncmp ebx, 1\njz short loc_11DD\nmov edx, 1\nloc_11FB:\nadd edx, 1\nmov ecx, edx\nimul ecx, edx\ncmp ecx, ebx\njg short loc_11E6\njnz short loc_11FB\njmp short loc_11DD\nloc_120B:\nmov esi, 0\nloc_1210:\nmov [rbp+0], esi\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(int a1, int a2, _DWORD *a3)\n{\n int v3; // ebx\n _DWORD *result; // rax\n int v7; // esi\n int v8; // edx\n\n v3 = a1;\n result = malloc(4LL * (a2 - a1 + 1));\n if ( a2 < a1 )\n {\n v7 = 0;\n }\n else\n {\n v7 = 0;\n do\n {\n if ( v3 > 0 )\n {\n if ( v3 == 1 )\n {\nLABEL_3:\n result[v7++] = v3;\n }\n else\n {\n v8 = 1;\n while ( 1 )\n {\n ++v8;\n if ( v8 * v8 > v3 )\n break;\n if ( v8 * v8 == v3 )\n goto LABEL_3;\n }\n }\n }\n ++v3;\n }\n while ( v3 != a2 + 1 );\n }\n *a3 = v7;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(int a1, int a2, uint32_t *a3) {\n int v3;\n uint32_t *result;\n int v7;\n int v8;\n v3 = a1;\n result = malloc(4LL * (a2 - a1 + 1));\n if (a2 < a1) {\n v7 = 0;\n } else {\n v7 = 0;\n do {\n if (v3 > 0) {\n if (v3 == 1) {\n LABEL_3:\n result[v7++] = v3;\n } else {\n v8 = 1;\n while (1) {\n ++v8;\n if (v8 * v8 > v3) break;\n if (v8 * v8 == v3) goto LABEL_3;\n }\n }\n }\n ++v3;\n } while (v3 != a2 + 1);\n }\n *a3 = v7;\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(int a1, int a2, uint32_t *a3) {\n int v3;\n uint32_t *result;\n int v7;\n int v8;\n v3 = a1;\n result = malloc(4LL * (a2 - a1 + 1));\n if (a2 < a1) {\n v7 = 0;\n } else {\n v7 = 0;\n do {\n if (v3 > 0) {\n if (v3 == 1) {\n LABEL_3:\n result[v7++] = v3;\n } else {\n v8 = 1;\n while (1) {\n ++v8;\n if (v8 * v8 > v3) break;\n if (v8 * v8 == v3) goto LABEL_3;\n }\n }\n }\n ++v3;\n } while (v3 != a2 + 1);\n }\n *a3 = v7;\n return result;\n}" + }, + { + "index": 589, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int a, int b, int* size) {\n int* lists = malloc((b - a + 1) * sizeof(int));\n int idx = 0;\n for (int i = a; i <= b; i++) {\n int j = 1;\n while (j * j <= i) {\n if (j * j == i) {\n lists[idx++] = i;\n break;\n }\n j++;\n }\n }\n *size = idx;\n return lists;\n}", + "test": "int main() {\n\n int size;\n\n int *result;\n\n\n\n result = func0(1, 30, &size);\n\n int expected_1[] = {1, 4, 9, 16, 25};\n\n int expected_1_size = sizeof(expected_1) / sizeof(expected_1[0]);\n\n assert(size == expected_1_size);\n\n for (int i = 0; i < size; i++) {\n\n assert(result[i] == expected_1[i]);\n\n }\n\n free(result);\n\n\n\n result = func0(50, 100, &size);\n\n int expected_2[] = {64, 81, 100};\n\n int expected_2_size = sizeof(expected_2) / sizeof(expected_2[0]);\n\n assert(size == expected_2_size);\n\n for (int i = 0; i < size; i++) {\n\n assert(result[i] == expected_2[i]);\n\n }\n\n free(result);\n\n\n\n result = func0(100, 200, &size);\n\n int expected_3[] = {100, 121, 144, 169, 196};\n\n int expected_3_size = sizeof(expected_3) / sizeof(expected_3[0]);\n\n assert(size == expected_3_size);\n\n for (int i = 0; i < size; i++) {\n\n assert(result[i] == expected_3[i]);\n\n }\n\n free(result);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %rdx,%r12\npush %rbp\nmov %esi,%ebp\npush %rbx\nmov %edi,%ebx\nmov %esi,%edi\nsub %ebx,%edi\nadd $0x1,%edi\nmovslq %edi,%rdi\nshl $0x2,%rdi\ncallq 10b0 \ncmp %ebx,%ebp\njl 1433 \nlea 0x1(%rbp),%edi\nxor %r8d,%r8d\nnopl 0x0(%rax)\ntest %ebx,%ebx\njle 140e \ncmp $0x1,%ebx\nje 1420 \nmov $0x1,%ecx\njmp 1402 \nje 1420 \nadd $0x1,%ecx\nmov %ecx,%esi\nimul %ecx,%esi\ncmp %ebx,%esi\njle 1400 \nadd $0x1,%ebx\ncmp %ebx,%edi\njne 13f0 \npop %rbx\npop %rbp\nmov %r8d,(%r12)\npop %r12\nretq\nxchg %ax,%ax\nmovslq %r8d,%rdx\nadd $0x1,%r8d\nmov %ebx,(%rax,%rdx,4)\nadd $0x1,%ebx\ncmp %ebx,%edi\njne 13f0 \njmp 1415 \nxor %r8d,%r8d\npop %rbx\npop %rbp\nmov %r8d,(%r12)\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\npush r12\nmov r12, rdx\npush rbp\nmov ebp, esi\npush rbx\nmov ebx, edi\nmov edi, esi\nsub edi, ebx\nadd edi, 1\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\ncmp ebp, ebx\njl short loc_1422\nlea esi, [rbp+1]\nxor edi, edi\nnop dword ptr [rax+rax+00h]\nloc_13E0:\ntest ebx, ebx\njle short loc_13FE\ncmp ebx, 1\njz short loc_1410\nmov edx, 1\njmp short loc_13F2\nloc_13F0:\njz short loc_1410\nloc_13F2:\nadd edx, 1\nmov ecx, edx\nimul ecx, edx\ncmp ecx, ebx\njle short loc_13F0\nloc_13FE:\nadd ebx, 1\ncmp ebx, esi\njnz short loc_13E0\nloc_1405:\nmov [r12], edi\npop rbx\npop rbp\npop r12\nretn\nloc_1410:\nmovsxd rdx, edi\nadd edi, 1\nmov [rax+rdx*4], ebx\nadd ebx, 1\ncmp ebx, esi\njnz short loc_13E0\njmp short loc_1405\nloc_1422:\nxor edi, edi\nmov [r12], edi\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int a1, int a2, _DWORD *a3)\n{\n int v4; // ebx\n _DWORD *result; // rax\n int v6; // esi\n int v7; // edi\n int v8; // edx\n __int64 v9; // rdx\n\n v4 = a1;\n result = malloc(4LL * (a2 - a1 + 1));\n if ( a2 >= a1 )\n {\n v6 = a2 + 1;\n v7 = 0;\n while ( 1 )\n {\n while ( v4 <= 0 )\n {\nLABEL_8:\n if ( ++v4 == v6 )\n goto LABEL_9;\n }\n if ( v4 != 1 )\n {\n v8 = 1;\n do\n {\n ++v8;\n if ( v8 * v8 > v4 )\n goto LABEL_8;\n }\n while ( v8 * v8 != v4 );\n }\n v9 = v7++;\n result[v9] = v4++;\n if ( v4 == v6 )\n {\nLABEL_9:\n *a3 = v7;\n return result;\n }\n }\n }\n *a3 = 0;\n return result;\n}", + "ida_strip_asm": "sub_13B0:\nendbr64\npush r12\nmov r12, rdx\npush rbp\nmov ebp, esi\npush rbx\nmov ebx, edi\nmov edi, esi\nsub edi, ebx\nadd edi, 1\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\ncmp ebp, ebx\njl short loc_1422\nlea esi, [rbp+1]\nxor edi, edi\nnop dword ptr [rax+rax+00h]\nloc_13E0:\ntest ebx, ebx\njle short loc_13FE\ncmp ebx, 1\njz short loc_1410\nmov edx, 1\njmp short loc_13F2\nloc_13F0:\njz short loc_1410\nloc_13F2:\nadd edx, 1\nmov ecx, edx\nimul ecx, edx\ncmp ecx, ebx\njle short loc_13F0\nloc_13FE:\nadd ebx, 1\ncmp ebx, esi\njnz short loc_13E0\nloc_1405:\nmov [r12], edi\npop rbx\npop rbp\npop r12\nretn\nloc_1410:\nmovsxd rdx, edi\nadd edi, 1\nmov [rax+rdx*4], ebx\nadd ebx, 1\ncmp ebx, esi\njnz short loc_13E0\njmp short loc_1405\nloc_1422:\nxor edi, edi\nmov [r12], edi\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_13B0(int a1, int a2, _DWORD *a3)\n{\n int v4; // ebx\n _DWORD *result; // rax\n int v6; // esi\n int v7; // edi\n int v8; // edx\n __int64 v9; // rdx\n\n v4 = a1;\n result = malloc(4LL * (a2 - a1 + 1));\n if ( a2 >= a1 )\n {\n v6 = a2 + 1;\n v7 = 0;\n while ( 1 )\n {\n while ( v4 <= 0 )\n {\nLABEL_8:\n if ( ++v4 == v6 )\n goto LABEL_9;\n }\n if ( v4 != 1 )\n {\n v8 = 1;\n do\n {\n ++v8;\n if ( v8 * v8 > v4 )\n goto LABEL_8;\n }\n while ( v8 * v8 != v4 );\n }\n v9 = v7++;\n result[v9] = v4++;\n if ( v4 == v6 )\n {\nLABEL_9:\n *a3 = v7;\n return result;\n }\n }\n }\n *a3 = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_13B0(int a1, int a2, uint32_t *a3) {\n int v4;\n uint32_t *result;\n int v6;\n int v7;\n int v8;\n long long v9;\n v4 = a1;\n result = malloc(4LL * (a2 - a1 + 1));\n if (a2 >= a1) {\n v6 = a2 + 1;\n v7 = 0;\n while (1) {\n while (v4 <= 0) {\n LABEL_8:\n if (++v4 == v6) goto LABEL_9;\n }\n if (v4 != 1) {\n v8 = 1;\n do {\n ++v8;\n if (v8 * v8 > v4) goto LABEL_8;\n } while (v8 * v8 != v4);\n }\n v9 = v7++;\n result[v9] = v4++;\n if (v4 == v6) {\n LABEL_9:\n *a3 = v7;\n return result;\n }\n }\n }\n *a3 = 0;\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(int a1, int a2, uint32_t *a3) {\n int v4;\n uint32_t *result;\n int v6;\n int v7;\n int v8;\n long long v9;\n v4 = a1;\n result = malloc(4LL * (a2 - a1 + 1));\n if (a2 >= a1) {\n v6 = a2 + 1;\n v7 = 0;\n while (1) {\n while (v4 <= 0) {\n LABEL_8:\n if (++v4 == v6) goto LABEL_9;\n }\n if (v4 != 1) {\n v8 = 1;\n do {\n ++v8;\n if (v8 * v8 > v4) goto LABEL_8;\n } while (v8 * v8 != v4);\n }\n v9 = v7++;\n result[v9] = v4++;\n if (v4 == v6) {\n LABEL_9:\n *a3 = v7;\n return result;\n }\n }\n }\n *a3 = 0;\n return result;\n}" + }, + { + "index": 589, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int a, int b, int* size) {\n int* lists = malloc((b - a + 1) * sizeof(int));\n int idx = 0;\n for (int i = a; i <= b; i++) {\n int j = 1;\n while (j * j <= i) {\n if (j * j == i) {\n lists[idx++] = i;\n break;\n }\n j++;\n }\n }\n *size = idx;\n return lists;\n}", + "test": "int main() {\n\n int size;\n\n int *result;\n\n\n\n result = func0(1, 30, &size);\n\n int expected_1[] = {1, 4, 9, 16, 25};\n\n int expected_1_size = sizeof(expected_1) / sizeof(expected_1[0]);\n\n assert(size == expected_1_size);\n\n for (int i = 0; i < size; i++) {\n\n assert(result[i] == expected_1[i]);\n\n }\n\n free(result);\n\n\n\n result = func0(50, 100, &size);\n\n int expected_2[] = {64, 81, 100};\n\n int expected_2_size = sizeof(expected_2) / sizeof(expected_2[0]);\n\n assert(size == expected_2_size);\n\n for (int i = 0; i < size; i++) {\n\n assert(result[i] == expected_2[i]);\n\n }\n\n free(result);\n\n\n\n result = func0(100, 200, &size);\n\n int expected_3[] = {100, 121, 144, 169, 196};\n\n int expected_3_size = sizeof(expected_3) / sizeof(expected_3[0]);\n\n assert(size == expected_3_size);\n\n for (int i = 0; i < size; i++) {\n\n assert(result[i] == expected_3[i]);\n\n }\n\n free(result);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %rdx,%r12\npush %rbp\nmov %esi,%ebp\npush %rbx\nmov %edi,%ebx\nmov %esi,%edi\nsub %ebx,%edi\nadd $0x1,%edi\nmovslq %edi,%rdi\nshl $0x2,%rdi\ncallq 10b0 \ncmp %ebx,%ebp\njl 14e4 \ntest %ebx,%ebx\njle 1428 \nxor %esi,%esi\nmov $0x1,%ecx\ncmp $0x1,%ebx\njne 1406 \njmpq 14f0 \nje 14f0 \nadd $0x1,%ecx\nmov %ecx,%edi\nimul %ecx,%edi\ncmp %edi,%ebx\njge 1400 \nadd $0x1,%ebx\ncmp %ebx,%ebp\njge 13f0 \npop %rbx\npop %rbp\nmov %esi,(%r12)\npop %r12\nretq\nnopw 0x0(%rax,%rax,1)\ntest %ebp,%ebp\nmov $0x1,%ecx\nmov $0x0,%esi\ncmovle %ebp,%esi\nmov %ecx,%edx\nsub %ebx,%edx\nadd %esi,%edx\ncmp %esi,%ebx\ncmovg %ecx,%edx\nmov %esi,%ecx\nsub %ebx,%ecx\ncmp $0x7,%ecx\njbe 14a7 \ncmp %esi,%ebx\njg 14a7 \nmovd %ebx,%xmm4\nmov %edx,%edi\nmovdqa 0xca3(%rip),%xmm3\nxor %ecx,%ecx\npshufd $0x0,%xmm4,%xmm1\nmovdqa 0xca4(%rip),%xmm2\npaddd 0xc7c(%rip),%xmm1\nshr $0x2,%edi\nnopw 0x0(%rax,%rax,1)\nmovdqa %xmm1,%xmm0\nadd $0x1,%ecx\npaddd %xmm3,%xmm1\npaddd %xmm2,%xmm0\ncmp %edi,%ecx\njne 1480 \nmov %edx,%edi\npshufd $0xff,%xmm0,%xmm0\nand $0xfffffffc,%edi\nmovd %xmm0,%ecx\nadd %edi,%ebx\ncmp %edi,%edx\nje 150d \nlea 0x1(%rbx),%edx\ncmp %esi,%edx\njg 1509 \nlea 0x2(%rbx),%edx\ncmp %edx,%esi\njl 1509 \nlea 0x3(%rbx),%edx\ncmp %edx,%esi\njl 1509 \nlea 0x4(%rbx),%edx\ncmp %edx,%esi\njl 1509 \nlea 0x5(%rbx),%edx\ncmp %edx,%esi\njl 1509 \nlea 0x6(%rbx),%edx\ncmp %edx,%esi\njl 1509 \nlea 0x7(%rbx),%edx\nadd $0x8,%ebx\ncmp %edx,%esi\ncmovl %edx,%ebx\ncmp %ebx,%ebp\njge 13ee \nxor %esi,%esi\npop %rbx\npop %rbp\nmov %esi,(%r12)\npop %r12\nretq\nmovslq %esi,%rdx\nadd $0x1,%esi\nmov %ebx,(%rax,%rdx,4)\nadd $0x1,%ebx\ncmp %ebx,%ebp\njge 13f0 \njmpq 1419 \nmov %edx,%ebx\njmp 14dc \nmov %ecx,%ebx\njmp 14dc \nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r12\nmov r12, rdx\npush rbp\nmov ebp, esi\npush rbx\nmov ebx, edi\nmov edi, esi\nsub edi, ebx\nadd edi, 1\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov rdi, rax\ncmp ebp, ebx\njl loc_1470\nmov eax, ebx\ntest ebx, ebx\njg short loc_1439\nxor edx, edx\ntest ebp, ebp\nmov ecx, 1\ncmovle edx, ebp\nmov eax, edx\nsub eax, ebx\ncmp ebx, edx\nlea esi, [rax+1]\ncmovg esi, ecx\njg short loc_1423\ncmp eax, 2\njbe short loc_1423\nmovd xmm3, ebx\nmov ecx, esi\nmovdqa xmm2, cs:xmmword_20F0\nxor eax, eax\npshufd xmm0, xmm3, 0\npaddd xmm0, cs:xmmword_20E0\nshr ecx, 2\nnop word ptr [rax+rax+00h]\nloc_1408:\nadd eax, 1\nmovdqa xmm1, xmm0\npaddd xmm0, xmm2\ncmp eax, ecx\njnz short loc_1408\nmov eax, esi\nand eax, 0FFFFFFFCh\nadd ebx, eax\nand esi, 3\njz short loc_147E\nloc_1423:\nlea eax, [rbx+1]\ncmp edx, eax\njl short loc_1435\nlea eax, [rbx+2]\nadd ebx, 3\ncmp edx, eax\ncmovge eax, ebx\nloc_1435:\ncmp ebp, eax\njl short loc_1470\nloc_1439:\nxor esi, esi\nloc_143B:\nmov edx, 1\ncmp eax, 1\njnz short loc_1452\njmp short loc_1491\nloc_1450:\njz short loc_1491\nloc_1452:\nadd edx, 1\nmov ecx, edx\nimul ecx, edx\ncmp ecx, eax\njle short loc_1450\nadd eax, 1\ncmp ebp, eax\njge short loc_143B\njmp short loc_1472\nloc_1470:\nxor esi, esi\nloc_1472:\nmov [r12], esi\nmov rax, rdi\npop rbx\npop rbp\npop r12\nretn\nloc_147E:\npaddd xmm1, cs:xmmword_20D0\npshufd xmm0, xmm1, 0FFh\nmovd eax, xmm0\njmp short loc_1435\nloc_1491:\nmovsxd rdx, esi\nadd esi, 1\nmov [rdi+rdx*4], eax\nadd eax, 1\ncmp ebp, eax\njge short loc_143B\njmp short loc_1472", + "ida_pseudo": "_DWORD *__fastcall func0(signed int a1, int a2, _DWORD *a3)\n{\n signed int v5; // ebx\n _DWORD *v6; // rdi\n int v7; // eax\n signed int v8; // edx\n unsigned int v9; // esi\n __m128i si128; // xmm2\n int v11; // eax\n __m128i v12; // xmm0\n __m128i v13; // xmm1\n int v14; // ebx\n int v15; // esi\n int v16; // edx\n __int64 v18; // rdx\n\n v5 = a1;\n v6 = malloc(4LL * (a2 - a1 + 1));\n if ( a2 < v5 )\n goto LABEL_21;\n v7 = v5;\n if ( v5 > 0 )\n goto LABEL_14;\n v8 = 0;\n if ( a2 <= 0 )\n v8 = a2;\n v9 = v8 - v5 + 1;\n if ( v5 > v8 )\n goto LABEL_10;\n if ( (unsigned int)(v8 - v5) <= 2 )\n goto LABEL_10;\n si128 = _mm_load_si128((const __m128i *)&xmmword_20F0);\n v11 = 0;\n v12 = _mm_add_epi32(_mm_shuffle_epi32(_mm_cvtsi32_si128(v5), 0), (__m128i)xmmword_20E0);\n do\n {\n ++v11;\n v13 = v12;\n v12 = _mm_add_epi32(v12, si128);\n }\n while ( v11 != v9 >> 2 );\n v5 += v9 & 0xFFFFFFFC;\n if ( (v9 & 3) != 0 )\n {\nLABEL_10:\n v7 = v5 + 1;\n if ( v8 >= v5 + 1 )\n {\n v7 = v5 + 2;\n v14 = v5 + 3;\n if ( v8 >= v7 )\n v7 = v14;\n }\n }\n else\n {\n v7 = _mm_cvtsi128_si32(_mm_shuffle_epi32(_mm_add_epi32(v13, (__m128i)xmmword_20D0), 255));\n }\n if ( a2 < v7 )\n {\nLABEL_21:\n v15 = 0;\n }\n else\n {\nLABEL_14:\n v15 = 0;\n do\n {\n while ( 1 )\n {\n v16 = 1;\n if ( v7 != 1 )\n break;\nLABEL_24:\n v18 = v15++;\n v6[v18] = v7++;\n if ( a2 < v7 )\n goto LABEL_22;\n }\n while ( 1 )\n {\n ++v16;\n if ( v16 * v16 > v7 )\n break;\n if ( v16 * v16 == v7 )\n goto LABEL_24;\n }\n ++v7;\n }\n while ( a2 >= v7 );\n }\nLABEL_22:\n *a3 = v15;\n return v6;\n}", + "ida_strip_asm": "sub_1390:\nendbr64\npush r12\nmov r12, rdx\npush rbp\nmov ebp, esi\npush rbx\nmov ebx, edi\nmov edi, esi\nsub edi, ebx\nadd edi, 1\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov rdi, rax\ncmp ebp, ebx\njl loc_1470\nmov eax, ebx\ntest ebx, ebx\njg short loc_1439\nxor edx, edx\ntest ebp, ebp\nmov ecx, 1\ncmovle edx, ebp\nmov eax, edx\nsub eax, ebx\ncmp ebx, edx\nlea esi, [rax+1]\ncmovg esi, ecx\njg short loc_1423\ncmp eax, 2\njbe short loc_1423\nmovd xmm3, ebx\nmov ecx, esi\nmovdqa xmm2, cs:xmmword_20F0\nxor eax, eax\npshufd xmm0, xmm3, 0\npaddd xmm0, cs:xmmword_20E0\nshr ecx, 2\nnop word ptr [rax+rax+00h]\nloc_1408:\nadd eax, 1\nmovdqa xmm1, xmm0\npaddd xmm0, xmm2\ncmp eax, ecx\njnz short loc_1408\nmov eax, esi\nand eax, 0FFFFFFFCh\nadd ebx, eax\nand esi, 3\njz short loc_147E\nloc_1423:\nlea eax, [rbx+1]\ncmp edx, eax\njl short loc_1435\nlea eax, [rbx+2]\nadd ebx, 3\ncmp edx, eax\ncmovge eax, ebx\nloc_1435:\ncmp ebp, eax\njl short loc_1470\nloc_1439:\nxor esi, esi\nloc_143B:\nmov edx, 1\ncmp eax, 1\njnz short loc_1452\njmp short loc_1491\nloc_1450:\njz short loc_1491\nloc_1452:\nadd edx, 1\nmov ecx, edx\nimul ecx, edx\ncmp ecx, eax\njle short loc_1450\nadd eax, 1\ncmp ebp, eax\njge short loc_143B\njmp short loc_1472\nloc_1470:\nxor esi, esi\nloc_1472:\nmov [r12], esi\nmov rax, rdi\npop rbx\npop rbp\npop r12\nretn\nloc_147E:\npaddd xmm1, cs:xmmword_20D0\npshufd xmm0, xmm1, 0FFh\nmovd eax, xmm0\njmp short loc_1435\nloc_1491:\nmovsxd rdx, esi\nadd esi, 1\nmov [rdi+rdx*4], eax\nadd eax, 1\ncmp ebp, eax\njge short loc_143B\njmp short loc_1472", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1390(signed int a1, int a2, _DWORD *a3)\n{\n signed int v5; // ebx\n _DWORD *v6; // rdi\n int v7; // eax\n signed int v8; // edx\n unsigned int v9; // esi\n __m128i si128; // xmm2\n int v11; // eax\n __m128i v12; // xmm0\n __m128i v13; // xmm1\n int v14; // ebx\n int v15; // esi\n int v16; // edx\n __int64 v18; // rdx\n\n v5 = a1;\n v6 = malloc(4LL * (a2 - a1 + 1));\n if ( a2 < v5 )\n goto LABEL_21;\n v7 = v5;\n if ( v5 > 0 )\n goto LABEL_14;\n v8 = 0;\n if ( a2 <= 0 )\n v8 = a2;\n v9 = v8 - v5 + 1;\n if ( v5 > v8 )\n goto LABEL_10;\n if ( (unsigned int)(v8 - v5) <= 2 )\n goto LABEL_10;\n si128 = _mm_load_si128((const __m128i *)&xmmword_20F0);\n v11 = 0;\n v12 = _mm_add_epi32(_mm_shuffle_epi32(_mm_cvtsi32_si128(v5), 0), (__m128i)xmmword_20E0);\n do\n {\n ++v11;\n v13 = v12;\n v12 = _mm_add_epi32(v12, si128);\n }\n while ( v11 != v9 >> 2 );\n v5 += v9 & 0xFFFFFFFC;\n if ( (v9 & 3) != 0 )\n {\nLABEL_10:\n v7 = v5 + 1;\n if ( v8 >= v5 + 1 )\n {\n v7 = v5 + 2;\n v14 = v5 + 3;\n if ( v8 >= v7 )\n v7 = v14;\n }\n }\n else\n {\n v7 = _mm_cvtsi128_si32(_mm_shuffle_epi32(_mm_add_epi32(v13, (__m128i)xmmword_20D0), 255));\n }\n if ( a2 < v7 )\n {\nLABEL_21:\n v15 = 0;\n }\n else\n {\nLABEL_14:\n v15 = 0;\n do\n {\n while ( 1 )\n {\n v16 = 1;\n if ( v7 != 1 )\n break;\nLABEL_24:\n v18 = v15++;\n v6[v18] = v7++;\n if ( a2 < v7 )\n goto LABEL_22;\n }\n while ( 1 )\n {\n ++v16;\n if ( v16 * v16 > v7 )\n break;\n if ( v16 * v16 == v7 )\n goto LABEL_24;\n }\n ++v7;\n }\n while ( a2 >= v7 );\n }\nLABEL_22:\n *a3 = v15;\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1390(signed int a1, int a2, uint32_t *a3) {\n signed int v5;\n uint32_t *v6;\n int v7;\n signed int v8;\n unsigned int v9;\n __m128i si128;\n int v11;\n __m128i v12;\n __m128i v13;\n int v14;\n int v15;\n int v16;\n long long v18;\n v5 = a1;\n v6 = malloc(4LL * (a2 - a1 + 1));\n if (a2 < v5) goto LABEL_21;\n v7 = v5;\n if (v5 > 0) goto LABEL_14;\n v8 = 0;\n if (a2 <= 0) v8 = a2;\n v9 = v8 - v5 + 1;\n if (v5 > v8) goto LABEL_10;\n if ((unsigned int)(v8 - v5) <= 2) goto LABEL_10;\n si128 = _mm_load_si128((const __m128i *)&xmmword_20F0);\n v11 = 0;\n v12 = _mm_add_epi32(_mm_shuffle_epi32(_mm_cvtsi32_si128(v5), 0),\n (__m128i)xmmword_20E0);\n do {\n ++v11;\n v13 = v12;\n v12 = _mm_add_epi32(v12, si128);\n } while (v11 != v9 >> 2);\n v5 += v9 & 4294967292;\n if ((v9 & 3) != 0) {\n LABEL_10:\n v7 = v5 + 1;\n if (v8 >= v5 + 1) {\n v7 = v5 + 2;\n v14 = v5 + 3;\n if (v8 >= v7) v7 = v14;\n }\n } else {\n v7 = _mm_cvtsi128_si32(\n _mm_shuffle_epi32(_mm_add_epi32(v13, (__m128i)xmmword_20D0), 255));\n }\n if (a2 < v7) {\n LABEL_21:\n v15 = 0;\n } else {\n LABEL_14:\n v15 = 0;\n do {\n while (1) {\n v16 = 1;\n if (v7 != 1) break;\n LABEL_24:\n v18 = v15++;\n v6[v18] = v7++;\n if (a2 < v7) goto LABEL_22;\n }\n while (1) {\n ++v16;\n if (v16 * v16 > v7) break;\n if (v16 * v16 == v7) goto LABEL_24;\n }\n ++v7;\n } while (a2 >= v7);\n }\nLABEL_22:\n *a3 = v15;\n return v6;\n}", + "ida_pseudo_norm": "uint32_t *func0(signed int a1, int a2, uint32_t *a3) {\n signed int v5;\n uint32_t *v6;\n int v7;\n signed int v8;\n unsigned int v9;\n __m128i si128;\n int v11;\n __m128i v12;\n __m128i v13;\n int v14;\n int v15;\n int v16;\n long long v18;\n v5 = a1;\n v6 = malloc(4LL * (a2 - a1 + 1));\n if (a2 < v5) goto LABEL_21;\n v7 = v5;\n if (v5 > 0) goto LABEL_14;\n v8 = 0;\n if (a2 <= 0) v8 = a2;\n v9 = v8 - v5 + 1;\n if (v5 > v8) goto LABEL_10;\n if ((unsigned int)(v8 - v5) <= 2) goto LABEL_10;\n si128 = _mm_load_si128((const __m128i *)&xmmword_20F0);\n v11 = 0;\n v12 = _mm_add_epi32(_mm_shuffle_epi32(_mm_cvtsi32_si128(v5), 0),\n (__m128i)xmmword_20E0);\n do {\n ++v11;\n v13 = v12;\n v12 = _mm_add_epi32(v12, si128);\n } while (v11 != v9 >> 2);\n v5 += v9 & 4294967292;\n if ((v9 & 3) != 0) {\n LABEL_10:\n v7 = v5 + 1;\n if (v8 >= v5 + 1) {\n v7 = v5 + 2;\n v14 = v5 + 3;\n if (v8 >= v7) v7 = v14;\n }\n } else {\n v7 = _mm_cvtsi128_si32(\n _mm_shuffle_epi32(_mm_add_epi32(v13, (__m128i)xmmword_20D0), 255));\n }\n if (a2 < v7) {\n LABEL_21:\n v15 = 0;\n } else {\n LABEL_14:\n v15 = 0;\n do {\n while (1) {\n v16 = 1;\n if (v7 != 1) break;\n LABEL_24:\n v18 = v15++;\n v6[v18] = v7++;\n if (a2 < v7) goto LABEL_22;\n }\n while (1) {\n ++v16;\n if (v16 * v16 > v7) break;\n if (v16 * v16 == v7) goto LABEL_24;\n }\n ++v7;\n } while (a2 >= v7);\n }\nLABEL_22:\n *a3 = v15;\n return v6;\n}" + }, + { + "index": 590, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n double r;\n\n double theta;\n\n double complex cn1;\n\n} PolarRect;\n\n\n\n", + "func": "PolarRect func0(double x, double y) {\n double complex cn = x + y * I;\n double r = cabs(cn);\n double theta = carg(cn);\n double complex cn1 = 2 * cexp(I * M_PI);\n PolarRect result;\n result.r = r;\n result.theta = theta;\n result.cn1 = cn1;\n return result;\n}", + "test": "int main() {\n\n PolarRect pr;\n\n\n\n pr = func0(3, 4);\n\n assert(pr.r == 5.0);\n\n assert(pr.theta == 0.9272952180016122);\n\n assert(creal(pr.cn1) == -2.0);\n\n assert(cimag(pr.cn1) == 2.4492935982947064e-16);\n\n\n\n pr = func0(4, 7);\n\n assert(pr.r == 8.06225774829855);\n\n assert(pr.theta == 1.0516502125483738);\n\n assert(creal(pr.cn1) == -2.0);\n\n assert(cimag(pr.cn1) == 2.4492935982947064e-16);\n\n\n\n pr = func0(15, 17);\n\n assert(pr.r == 22.67156809750927);\n\n assert(pr.theta == 0.8478169733934057);\n\n assert(creal(pr.cn1) == -2.0);\n\n assert(cimag(pr.cn1) == 2.4492935982947064e-16);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x70,%rsp\nmov %rdi,-0x58(%rbp)\nmovsd %xmm0,-0x60(%rbp)\nmovsd %xmm1,-0x68(%rbp)\nmovsd -0x68(%rbp),%xmm0\npxor %xmm1,%xmm1\nmulsd %xmm0,%xmm1\naddsd -0x60(%rbp),%xmm1\nmovsd %xmm1,-0x40(%rbp)\nmovsd %xmm0,-0x38(%rbp)\nmov -0x40(%rbp),%rax\nmovsd -0x38(%rbp),%xmm1\nmovq %rax,%xmm0\ncallq 10b0 \nmovq %xmm0,%rax\nmov %rax,-0x50(%rbp)\nmovsd -0x40(%rbp),%xmm0\nmov -0x38(%rbp),%rax\nmovapd %xmm0,%xmm1\nmovq %rax,%xmm0\ncallq 10a0 \nmovq %xmm0,%rax\nmov %rax,-0x48(%rbp)\nmovsd 0xde5(%rip),%xmm0\nmovsd %xmm0,-0x30(%rbp)\nmovsd 0xde0(%rip),%xmm0\nmovsd %xmm0,-0x28(%rbp)\nmovsd -0x50(%rbp),%xmm0\nmovsd %xmm0,-0x20(%rbp)\nmovsd -0x48(%rbp),%xmm0\nmovsd %xmm0,-0x18(%rbp)\nmovsd -0x30(%rbp),%xmm0\nmovsd %xmm0,-0x10(%rbp)\nmovsd -0x28(%rbp),%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmov -0x58(%rbp),%rcx\nmov -0x20(%rbp),%rax\nmov -0x18(%rbp),%rdx\nmov %rax,(%rcx)\nmov %rdx,0x8(%rcx)\nmov -0x10(%rbp),%rax\nmov -0x8(%rbp),%rdx\nmov %rax,0x10(%rcx)\nmov %rdx,0x18(%rcx)\nmov -0x58(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nadd rsp, 0FFFFFFFFFFFFFF80h\nmov [rbp+var_68], rdi\nmovsd [rbp+var_70], xmm0\nmovsd [rbp+var_78], xmm1\nmovsd xmm0, [rbp+var_78]\nmovsd [rbp+y], xmm0\nmovsd xmm1, [rbp+y]\npxor xmm0, xmm0\nmulsd xmm0, xmm1\nmovsd xmm1, [rbp+var_70]\naddsd xmm0, xmm1\nmovsd [rbp+x], xmm0\nmovsd xmm0, [rbp+y]\nmovsd xmm1, [rbp+x]\nmovsd [rbp+var_40], xmm1\nmovsd [rbp+var_38], xmm0\nmov rax, [rbp+var_40]\nmovsd xmm1, [rbp+var_38]\nmovq xmm0, rax\ncall _cabs\nmovq rax, xmm0\nmov [rbp+var_50], rax\nmovsd xmm0, [rbp+x]\nmov rax, [rbp+y]\nmovapd xmm1, xmm0; x\nmovq xmm0, rax; y\ncall _atan2\nmovq rax, xmm0\nmov [rbp+var_48], rax\nmovsd xmm0, cs:qword_2120\nmovsd [rbp+var_30], xmm0\nmovsd xmm0, cs:qword_2128\nmovsd [rbp+var_28], xmm0\nmovsd xmm0, [rbp+var_50]\nmovsd [rbp+var_20], xmm0\nmovsd xmm0, [rbp+var_48]\nmovsd [rbp+var_18], xmm0\nmovsd xmm0, cs:qword_2120\nmovsd [rbp+var_10], xmm0\nmovsd xmm0, cs:qword_2128\nmovsd [rbp+var_8], xmm0\nmov rcx, [rbp+var_68]\nmov rax, [rbp+var_20]\nmov rdx, [rbp+var_18]\nmov [rcx], rax\nmov [rcx+8], rdx\nmov rax, [rbp+var_10]\nmov rdx, [rbp+var_8]\nmov [rcx+10h], rax\nmov [rcx+18h], rdx\nmov rax, [rbp+var_68]\nleave\nretn", + "ida_pseudo": "double *__fastcall func0(double *a1, double a2, double a3)\n{\n double x; // [rsp+20h] [rbp-60h]\n double v5; // [rsp+60h] [rbp-20h]\n double v6; // [rsp+68h] [rbp-18h]\n\n x = 0.0 * a3 + a2;\n v5 = cabs(x, a3);\n v6 = atan2(a3, x);\n *a1 = v5;\n a1[1] = v6;\n a1[2] = -2.0;\n a1[3] = 2.449293598294706e-16;\n return a1;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nadd rsp, 0FFFFFFFFFFFFFF80h\nmov [rbp+var_68], rdi\nmovsd [rbp+var_70], xmm0\nmovsd [rbp+var_78], xmm1\nmovsd xmm0, [rbp+var_78]\nmovsd [rbp+y], xmm0\nmovsd xmm1, [rbp+y]\npxor xmm0, xmm0\nmulsd xmm0, xmm1\nmovsd xmm1, [rbp+var_70]\naddsd xmm0, xmm1\nmovsd [rbp+x], xmm0\nmovsd xmm0, [rbp+y]\nmovsd xmm1, [rbp+x]\nmovsd [rbp+var_40], xmm1\nmovsd [rbp+var_38], xmm0\nmov rax, [rbp+var_40]\nmovsd xmm1, [rbp+var_38]\nmovq xmm0, rax\ncall _cabs\nmovq rax, xmm0\nmov [rbp+var_50], rax\nmovsd xmm0, [rbp+x]\nmov rax, [rbp+y]\nmovapd xmm1, xmm0; x\nmovq xmm0, rax; y\ncall _atan2\nmovq rax, xmm0\nmov [rbp+var_48], rax\nmovsd xmm0, cs:qword_2120\nmovsd [rbp+var_30], xmm0\nmovsd xmm0, cs:qword_2128\nmovsd [rbp+var_28], xmm0\nmovsd xmm0, [rbp+var_50]\nmovsd [rbp+var_20], xmm0\nmovsd xmm0, [rbp+var_48]\nmovsd [rbp+var_18], xmm0\nmovsd xmm0, cs:qword_2120\nmovsd [rbp+var_10], xmm0\nmovsd xmm0, cs:qword_2128\nmovsd [rbp+var_8], xmm0\nmov rcx, [rbp+var_68]\nmov rax, [rbp+var_20]\nmov rdx, [rbp+var_18]\nmov [rcx], rax\nmov [rcx+8], rdx\nmov rax, [rbp+var_10]\nmov rdx, [rbp+var_8]\nmov [rcx+10h], rax\nmov [rcx+18h], rdx\nmov rax, [rbp+var_68]\nleave\nretn", + "ida_strip_pseudo": "double *__fastcall sub_11A9(double *a1, double a2, double a3)\n{\n double x; // [rsp+20h] [rbp-60h]\n double v5; // [rsp+60h] [rbp-20h]\n double v6; // [rsp+68h] [rbp-18h]\n\n x = 0.0 * a3 + a2;\n v5 = cabs(x, a3);\n v6 = atan2(a3, x);\n *a1 = v5;\n a1[1] = v6;\n a1[2] = -2.0;\n a1[3] = 2.449293598294706e-16;\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double *sub_11A9(double *a1, double a2, double a3) {\n double x;\n double v5;\n double v6;\n x = 0.0 * a3 + a2;\n v5 = cabs(x, a3);\n v6 = atan2(a3, x);\n *a1 = v5;\n a1[1] = v6;\n a1[2] = -2.0;\n a1[3] = 2.449293598294706e-16;\n return a1;\n}", + "ida_pseudo_norm": "double *func0(double *a1, double a2, double a3) {\n double x;\n double v5;\n double v6;\n x = 0.0 * a3 + a2;\n v5 = cabs(x, a3);\n v6 = atan2(a3, x);\n *a1 = v5;\n a1[1] = v6;\n a1[2] = -2.0;\n a1[3] = 2.449293598294706e-16;\n return a1;\n}" + }, + { + "index": 590, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n double r;\n\n double theta;\n\n double complex cn1;\n\n} PolarRect;\n\n\n\n", + "func": "PolarRect func0(double x, double y) {\n double complex cn = x + y * I;\n double r = cabs(cn);\n double theta = carg(cn);\n double complex cn1 = 2 * cexp(I * M_PI);\n PolarRect result;\n result.r = r;\n result.theta = theta;\n result.cn1 = cn1;\n return result;\n}", + "test": "int main() {\n\n PolarRect pr;\n\n\n\n pr = func0(3, 4);\n\n assert(pr.r == 5.0);\n\n assert(pr.theta == 0.9272952180016122);\n\n assert(creal(pr.cn1) == -2.0);\n\n assert(cimag(pr.cn1) == 2.4492935982947064e-16);\n\n\n\n pr = func0(4, 7);\n\n assert(pr.r == 8.06225774829855);\n\n assert(pr.theta == 1.0516502125483738);\n\n assert(creal(pr.cn1) == -2.0);\n\n assert(cimag(pr.cn1) == 2.4492935982947064e-16);\n\n\n\n pr = func0(15, 17);\n\n assert(pr.r == 22.67156809750927);\n\n assert(pr.theta == 0.8478169733934057);\n\n assert(creal(pr.cn1) == -2.0);\n\n assert(cimag(pr.cn1) == 2.4492935982947064e-16);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov %rdi,%rbx\nmovapd %xmm1,%xmm2\nmulsd 0xf7e(%rip),%xmm1\naddsd %xmm0,%xmm1\nmovsd %xmm1,(%rsp)\nmovapd %xmm1,%xmm0\nmovsd %xmm2,0x8(%rsp)\nmovapd %xmm2,%xmm1\ncallq 10b0 \nmovq %xmm0,%rbp\nmovsd (%rsp),%xmm1\nmovsd 0x8(%rsp),%xmm0\ncallq 10a0 \nmov %rbp,(%rbx)\nmovsd %xmm0,0x8(%rbx)\nmovsd 0xe05(%rip),%xmm0\nmovsd %xmm0,0x10(%rbx)\nmovsd 0xe00(%rip),%xmm0\nmovsd %xmm0,0x18(%rbx)\nmov %rbx,%rax\nadd $0x18,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush r14\npush rbp\npush rbx\nsub rsp, 10h\nmov rbx, rdi\nmovapd xmm2, xmm0\npxor xmm0, xmm0\nmulsd xmm0, xmm1\naddsd xmm0, xmm2\nmovq r14, xmm0\nmovsd [rsp+28h+y], xmm1\ncall _cabs\nmovq rbp, xmm0\nmovq xmm1, r14; x\nmovsd xmm0, [rsp+28h+y]; y\ncall _atan2\nmov [rbx], rbp\nmovsd qword ptr [rbx+8], xmm0\nmov rax, cs:qword_2110\nmov [rbx+10h], rax\nmov rax, cs:qword_2118\nmov [rbx+18h], rax\nmov rax, rbx\nadd rsp, 10h\npop rbx\npop rbp\npop r14\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, double a2, double a3)\n{\n double v3; // r14\n double v4; // rbp\n double v5; // xmm0_8\n\n v3 = 0.0 * a3 + a2;\n v4 = cabs();\n v5 = atan2(a3, v3);\n *(double *)a1 = v4;\n *(double *)(a1 + 8) = v5;\n *(_QWORD *)(a1 + 16) = 0xC000000000000000LL;\n *(_QWORD *)(a1 + 24) = 0x3CB1A62633145C07LL;\n return a1;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r14\npush rbp\npush rbx\nsub rsp, 10h\nmov rbx, rdi\nmovapd xmm2, xmm0\npxor xmm0, xmm0\nmulsd xmm0, xmm1\naddsd xmm0, xmm2\nmovq r14, xmm0\nmovsd [rsp+28h+y], xmm1\ncall _cabs\nmovq rbp, xmm0\nmovq xmm1, r14; x\nmovsd xmm0, [rsp+28h+y]; y\ncall _atan2\nmov [rbx], rbp\nmovsd qword ptr [rbx+8], xmm0\nmov rax, cs:qword_2110\nmov [rbx+10h], rax\nmov rax, cs:qword_2118\nmov [rbx+18h], rax\nmov rax, rbx\nadd rsp, 10h\npop rbx\npop rbp\npop r14\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(__int64 a1, double a2, double a3)\n{\n double v3; // r14\n double v4; // rbp\n double v5; // xmm0_8\n\n v3 = 0.0 * a3 + a2;\n v4 = cabs();\n v5 = atan2(a3, v3);\n *(double *)a1 = v4;\n *(double *)(a1 + 8) = v5;\n *(_QWORD *)(a1 + 16) = 0xC000000000000000LL;\n *(_QWORD *)(a1 + 24) = 0x3CB1A62633145C07LL;\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(long long a1, double a2, double a3) {\n double v3;\n double v4;\n double v5;\n v3 = 0.0 * a3 + a2;\n v4 = cabs();\n v5 = atan2(a3, v3);\n *(double *)a1 = v4;\n *(double *)(a1 + 8) = v5;\n *(uint64_t *)(a1 + 16) = 13835058055282163712LL;\n *(uint64_t *)(a1 + 24) = 4373459396149402631LL;\n return a1;\n}", + "ida_pseudo_norm": "long long func0(long long a1, double a2, double a3) {\n double v3;\n double v4;\n double v5;\n v3 = 0.0 * a3 + a2;\n v4 = cabs();\n v5 = atan2(a3, v3);\n *(double *)a1 = v4;\n *(double *)(a1 + 8) = v5;\n *(uint64_t *)(a1 + 16) = 13835058055282163712LL;\n *(uint64_t *)(a1 + 24) = 4373459396149402631LL;\n return a1;\n}" + }, + { + "index": 590, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n double r;\n\n double theta;\n\n double complex cn1;\n\n} PolarRect;\n\n\n\n", + "func": "PolarRect func0(double x, double y) {\n double complex cn = x + y * I;\n double r = cabs(cn);\n double theta = carg(cn);\n double complex cn1 = 2 * cexp(I * M_PI);\n PolarRect result;\n result.r = r;\n result.theta = theta;\n result.cn1 = cn1;\n return result;\n}", + "test": "int main() {\n\n PolarRect pr;\n\n\n\n pr = func0(3, 4);\n\n assert(pr.r == 5.0);\n\n assert(pr.theta == 0.9272952180016122);\n\n assert(creal(pr.cn1) == -2.0);\n\n assert(cimag(pr.cn1) == 2.4492935982947064e-16);\n\n\n\n pr = func0(4, 7);\n\n assert(pr.r == 8.06225774829855);\n\n assert(pr.theta == 1.0516502125483738);\n\n assert(creal(pr.cn1) == -2.0);\n\n assert(cimag(pr.cn1) == 2.4492935982947064e-16);\n\n\n\n pr = func0(15, 17);\n\n assert(pr.r == 22.67156809750927);\n\n assert(pr.theta == 0.8478169733934057);\n\n assert(creal(pr.cn1) == -2.0);\n\n assert(cimag(pr.cn1) == 2.4492935982947064e-16);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npxor %xmm3,%xmm3\npush %r12\nmov %rdi,%r12\nmulsd %xmm1,%xmm3\nsub $0x20,%rsp\nmovsd %xmm1,0x10(%rsp)\naddsd %xmm0,%xmm3\nmovapd %xmm3,%xmm0\nmovsd %xmm3,0x18(%rsp)\ncallq 1070 \nmovsd 0x18(%rsp),%xmm3\nmovsd 0x10(%rsp),%xmm2\nmovsd %xmm0,0x8(%rsp)\nmovapd %xmm3,%xmm1\nmovapd %xmm2,%xmm0\ncallq 1060 \nmovsd 0x8(%rsp),%xmm4\nmov %r12,%rax\nmovsd %xmm0,0x8(%r12)\nmovsd 0xe23(%rip),%xmm0\nmovsd %xmm4,(%r12)\nmovsd %xmm0,0x10(%r12)\nmovsd 0xe16(%rip),%xmm0\nmovsd %xmm0,0x18(%r12)\nadd $0x20,%rsp\npop %r12\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npxor xmm2, xmm2\npush rbx\nmov rbx, rdi\nmulsd xmm2, xmm1\nsub rsp, 20h\nmovsd [rsp+28h+y], xmm1\naddsd xmm2, xmm0\nmovapd xmm0, xmm2\nmovsd [rsp+28h+x], xmm2\ncall _cabs\nmovsd xmm2, [rsp+28h+x]\nmovsd xmm4, [rsp+28h+y]\nmovsd [rsp+28h+var_20], xmm0\nmovapd xmm1, xmm2; x\nmovapd xmm0, xmm4; y\ncall _atan2\nmovsd xmm3, [rsp+28h+var_20]\nmov rax, rbx\nmovapd xmm1, xmm0\nmovapd xmm0, xmm3\nunpcklpd xmm0, xmm1\nmovups xmmword ptr [rbx], xmm0\nmovapd xmm0, cs:xmmword_2110\nmovups xmmword ptr [rbx+10h], xmm0\nadd rsp, 20h\npop rbx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, double a2, double a3)\n{\n __m128d v3; // xmm0\n __int64 result; // rax\n double v5; // [rsp+0h] [rbp-20h]\n double x; // [rsp+10h] [rbp-10h]\n\n x = 0.0 * a3 + a2;\n v5 = cabs(x);\n v3 = (__m128d)*(unsigned __int64 *)&a3;\n v3.m128d_f64[0] = atan2(a3, x);\n result = a1;\n *(__m128d *)a1 = _mm_unpacklo_pd((__m128d)*(unsigned __int64 *)&v5, v3);\n *(_OWORD *)(a1 + 16) = xmmword_2110;\n return result;\n}", + "ida_strip_asm": "sub_14D0:\nendbr64\npxor xmm2, xmm2\npush rbx\nmov rbx, rdi\nmulsd xmm2, xmm1\nsub rsp, 20h\nmovsd [rsp+28h+y], xmm1\naddsd xmm2, xmm0\nmovapd xmm0, xmm2\nmovsd [rsp+28h+x], xmm2\ncall _cabs\nmovsd xmm2, [rsp+28h+x]\nmovsd xmm4, [rsp+28h+y]\nmovsd [rsp+28h+var_20], xmm0\nmovapd xmm1, xmm2; x\nmovapd xmm0, xmm4; y\ncall _atan2\nmovsd xmm3, [rsp+28h+var_20]\nmov rax, rbx\nmovapd xmm1, xmm0\nmovapd xmm0, xmm3\nunpcklpd xmm0, xmm1\nmovups xmmword ptr [rbx], xmm0\nmovapd xmm0, cs:xmmword_2110\nmovups xmmword ptr [rbx+10h], xmm0\nadd rsp, 20h\npop rbx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_14D0(__int64 a1, double a2, double a3)\n{\n __m128d v3; // xmm0\n __int64 result; // rax\n double v5; // [rsp+0h] [rbp-20h]\n double x; // [rsp+10h] [rbp-10h]\n\n x = 0.0 * a3 + a2;\n v5 = cabs(x);\n v3 = (__m128d)*(unsigned __int64 *)&a3;\n v3.m128d_f64[0] = atan2(a3, x);\n result = a1;\n *(__m128d *)a1 = _mm_unpacklo_pd((__m128d)*(unsigned __int64 *)&v5, v3);\n *(_OWORD *)(a1 + 16) = xmmword_2110;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_14D0(long long a1, double a2, double a3) {\n __m128d v3;\n long long result;\n double v5;\n double x;\n x = 0.0 * a3 + a2;\n v5 = cabs(x);\n v3 = (__m128d) * (unsigned long long *)&a3;\n v3.m128d_f64[0] = atan2(a3, x);\n result = a1;\n *(__m128d *)a1 = _mm_unpacklo_pd((__m128d) * (unsigned long long *)&v5, v3);\n *(long double *)(a1 + 16) = xmmword_2110;\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, double a2, double a3) {\n __m128d v3;\n long long result;\n double v5;\n double x;\n x = 0.0 * a3 + a2;\n v5 = cabs(x);\n v3 = (__m128d) * (unsigned long long *)&a3;\n v3.m128d_f64[0] = atan2(a3, x);\n result = a1;\n *(__m128d *)a1 = _mm_unpacklo_pd((__m128d) * (unsigned long long *)&v5, v3);\n *(long double *)(a1 + 16) = xmmword_2110;\n return result;\n}" + }, + { + "index": 590, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n double r;\n\n double theta;\n\n double complex cn1;\n\n} PolarRect;\n\n\n\n", + "func": "PolarRect func0(double x, double y) {\n double complex cn = x + y * I;\n double r = cabs(cn);\n double theta = carg(cn);\n double complex cn1 = 2 * cexp(I * M_PI);\n PolarRect result;\n result.r = r;\n result.theta = theta;\n result.cn1 = cn1;\n return result;\n}", + "test": "int main() {\n\n PolarRect pr;\n\n\n\n pr = func0(3, 4);\n\n assert(pr.r == 5.0);\n\n assert(pr.theta == 0.9272952180016122);\n\n assert(creal(pr.cn1) == -2.0);\n\n assert(cimag(pr.cn1) == 2.4492935982947064e-16);\n\n\n\n pr = func0(4, 7);\n\n assert(pr.r == 8.06225774829855);\n\n assert(pr.theta == 1.0516502125483738);\n\n assert(creal(pr.cn1) == -2.0);\n\n assert(cimag(pr.cn1) == 2.4492935982947064e-16);\n\n\n\n pr = func0(15, 17);\n\n assert(pr.r == 22.67156809750927);\n\n assert(pr.theta == 0.8478169733934057);\n\n assert(creal(pr.cn1) == -2.0);\n\n assert(cimag(pr.cn1) == 2.4492935982947064e-16);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npxor %xmm4,%xmm4\npush %r12\nmov %rdi,%r12\nmulsd %xmm1,%xmm4\nsub $0x20,%rsp\nmovsd %xmm1,0x10(%rsp)\naddsd %xmm0,%xmm4\nmovapd %xmm4,%xmm0\nmovsd %xmm4,0x18(%rsp)\ncallq 1070 \nmovsd 0x18(%rsp),%xmm4\nmovsd 0x10(%rsp),%xmm3\nmovsd %xmm0,0x8(%rsp)\nmovapd %xmm4,%xmm1\nmovapd %xmm3,%xmm0\ncallq 1060 \nmovsd 0x8(%rsp),%xmm2\nmov %r12,%rax\nunpcklpd %xmm0,%xmm2\nmovsd 0xe26(%rip),%xmm0\nmovups %xmm2,(%r12)\nmovsd %xmm0,0x10(%r12)\nmovsd 0xe1a(%rip),%xmm0\nmovsd %xmm0,0x18(%r12)\nadd $0x20,%rsp\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npxor xmm2, xmm2\npush rbx\nmov rbx, rdi\nmulsd xmm2, xmm1\nsub rsp, 20h\nmovsd [rsp+28h+y], xmm1\naddsd xmm2, xmm0\nmovapd xmm0, xmm2\nmovsd [rsp+28h+x], xmm2\ncall _cabs\nmovsd xmm2, [rsp+28h+x]\nmovsd xmm4, [rsp+28h+y]\nmovsd [rsp+28h+var_20], xmm0\nmovapd xmm1, xmm2; x\nmovapd xmm0, xmm4; y\ncall _atan2\nmovsd xmm3, [rsp+28h+var_20]\nmov rax, rbx\nmovapd xmm1, xmm0\nmovapd xmm0, xmm3\nunpcklpd xmm0, xmm1\nmovups xmmword ptr [rbx], xmm0\nmovapd xmm0, cs:xmmword_2010\nmovups xmmword ptr [rbx+10h], xmm0\nadd rsp, 20h\npop rbx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, double a2, double a3)\n{\n __m128d v3; // xmm0\n __int64 result; // rax\n double v5; // [rsp+0h] [rbp-20h]\n double x; // [rsp+10h] [rbp-10h]\n\n x = 0.0 * a3 + a2;\n v5 = cabs(x);\n v3 = (__m128d)*(unsigned __int64 *)&a3;\n v3.m128d_f64[0] = atan2(a3, x);\n result = a1;\n *(__m128d *)a1 = _mm_unpacklo_pd((__m128d)*(unsigned __int64 *)&v5, v3);\n *(_OWORD *)(a1 + 16) = xmmword_2010;\n return result;\n}", + "ida_strip_asm": "sub_1180:\nendbr64\npxor xmm2, xmm2\npush rbx\nmov rbx, rdi\nmulsd xmm2, xmm1\nsub rsp, 20h\nmovsd [rsp+28h+y], xmm1\naddsd xmm2, xmm0\nmovapd xmm0, xmm2\nmovsd [rsp+28h+x], xmm2\ncall _cabs\nmovsd xmm2, [rsp+28h+x]\nmovsd xmm4, [rsp+28h+y]\nmovsd [rsp+28h+var_20], xmm0\nmovapd xmm1, xmm2; x\nmovapd xmm0, xmm4; y\ncall _atan2\nmovsd xmm3, [rsp+28h+var_20]\nmov rax, rbx\nmovapd xmm1, xmm0\nmovapd xmm0, xmm3\nunpcklpd xmm0, xmm1\nmovups xmmword ptr [rbx], xmm0\nmovapd xmm0, cs:xmmword_2010\nmovups xmmword ptr [rbx+10h], xmm0\nadd rsp, 20h\npop rbx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1180(__int64 a1, double a2, double a3)\n{\n __m128d v3; // xmm0\n __int64 result; // rax\n double v5; // [rsp+0h] [rbp-20h]\n double x; // [rsp+10h] [rbp-10h]\n\n x = 0.0 * a3 + a2;\n v5 = cabs(x);\n v3 = (__m128d)*(unsigned __int64 *)&a3;\n v3.m128d_f64[0] = atan2(a3, x);\n result = a1;\n *(__m128d *)a1 = _mm_unpacklo_pd((__m128d)*(unsigned __int64 *)&v5, v3);\n *(_OWORD *)(a1 + 16) = xmmword_2010;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1180(long long a1, double a2, double a3) {\n __m128d v3;\n long long result;\n double v5;\n double x;\n x = 0.0 * a3 + a2;\n v5 = cabs(x);\n v3 = (__m128d) * (unsigned long long *)&a3;\n v3.m128d_f64[0] = atan2(a3, x);\n result = a1;\n *(__m128d *)a1 = _mm_unpacklo_pd((__m128d) * (unsigned long long *)&v5, v3);\n *(long double *)(a1 + 16) = xmmword_2010;\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, double a2, double a3) {\n __m128d v3;\n long long result;\n double v5;\n double x;\n x = 0.0 * a3 + a2;\n v5 = cabs(x);\n v3 = (__m128d) * (unsigned long long *)&a3;\n v3.m128d_f64[0] = atan2(a3, x);\n result = a1;\n *(__m128d *)a1 = _mm_unpacklo_pd((__m128d) * (unsigned long long *)&v5, v3);\n *(long double *)(a1 + 16) = xmmword_2010;\n return result;\n}" + }, + { + "index": 591, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int* newList, int size) {\n int temp = newList[0];\n newList[0] = newList[size - 1];\n newList[size - 1] = temp;\n return newList;\n}", + "test": "int main() {\n\n int list1[] = {12, 35, 9, 56, 24};\n\n int list2[] = {1, 2, 3};\n\n int list3[] = {4, 5, 6};\n\n \n\n int* result1 = func0(list1, 5);\n\n int* result2 = func0(list2, 3);\n\n int* result3 = func0(list3, 3);\n\n \n\n assert(result1[0] == 24 && result1[1] == 35 && result1[2] == 9 && result1[3] == 56 && result1[4] == 12);\n\n assert(result2[0] == 3 && result2[1] == 2 && result2[2] == 1);\n\n assert(result3[0] == 6 && result3[1] == 5 && result3[2] == 4);\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov -0x18(%rbp),%rax\nmov (%rax),%eax\nmov %eax,-0x4(%rbp)\nmov -0x1c(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x18(%rbp),%rax\nmov %edx,(%rax)\nmov -0x1c(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0x4(%rbp),%eax\nmov %eax,(%rdx)\nmov -0x18(%rbp),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov rax, [rbp+var_18]\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_18]\nmov [rax], edx\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nmov rax, [rbp+var_18]\npop rbp\nretn", + "ida_pseudo": "int *__fastcall func0(int *a1, int a2)\n{\n int v3; // [rsp+18h] [rbp-4h]\n\n v3 = *a1;\n *a1 = a1[a2 - 1];\n a1[a2 - 1] = v3;\n return a1;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov rax, [rbp+var_18]\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_18]\nmov [rax], edx\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nmov rax, [rbp+var_18]\npop rbp\nretn", + "ida_strip_pseudo": "int *__fastcall sub_1189(int *a1, int a2)\n{\n int v3; // [rsp+18h] [rbp-4h]\n\n v3 = *a1;\n *a1 = a1[a2 - 1];\n a1[a2 - 1] = v3;\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "int *sub_1189(int *a1, int a2) {\n int v3;\n v3 = *a1;\n *a1 = a1[a2 - 1];\n a1[a2 - 1] = v3;\n return a1;\n}", + "ida_pseudo_norm": "int *func0(int *a1, int a2) {\n int v3;\n v3 = *a1;\n *a1 = a1[a2 - 1];\n a1[a2 - 1] = v3;\n return a1;\n}" + }, + { + "index": 592, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n\n\n", + "func": "int func0(int n) {\n int k = n - 1;\n n = n * 2;\n int C[k + 1];\n for (int i = 0; i < k + 1; i++) {\n C[i] = 0;\n }\n C[0] = 1;\n for (int i = 1; i <= n; i++) {\n for (int j = (i < k ? i : k); j > 0; j--) {\n C[j] = C[j] + C[j - 1];\n }\n }\n return C[k];\n}", + "test": "int main() {\n\n assert(func0(3) == 15);\n\n assert(func0(4) == 56);\n\n assert(func0(1) == 1);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x48,%rsp\nmov %edi,-0x44(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmov %rsp,%rax\nmov %rax,%rsi\nmov -0x44(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0x2c(%rbp)\nshll -0x44(%rbp)\nmov -0x2c(%rbp),%eax\nadd $0x1,%eax\nmovslq %eax,%rdx\nsub $0x1,%rdx\nmov %rdx,-0x28(%rbp)\nmovslq %eax,%rdx\nmov %rdx,%r8\nmov $0x0,%r9d\nmovslq %eax,%rdx\nmov %rdx,%rcx\nmov $0x0,%ebx\ncltq\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%edi\nmov $0x0,%edx\ndiv %rdi\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rbx\nsub %rdx,%rbx\nmov %rbx,%rdx\ncmp %rdx,%rsp\nje 1213 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11fc \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 123d \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x20(%rbp)\nmovl $0x0,-0x30(%rbp)\njmp 126e \nmov -0x20(%rbp),%rax\nmov -0x30(%rbp),%edx\nmovslq %edx,%rdx\nmovl $0x0,(%rax,%rdx,4)\naddl $0x1,-0x30(%rbp)\nmov -0x2c(%rbp),%eax\ncmp -0x30(%rbp),%eax\njge 1259 \nmov -0x20(%rbp),%rax\nmovl $0x1,(%rax)\nmovl $0x1,-0x34(%rbp)\njmp 12d2 \nmov -0x34(%rbp),%eax\ncmp %eax,-0x2c(%rbp)\ncmovle -0x2c(%rbp),%eax\nmov %eax,-0x38(%rbp)\njmp 12c8 \nmov -0x20(%rbp),%rax\nmov -0x38(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%ecx\nmov -0x38(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x20(%rbp),%rax\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nadd %eax,%ecx\nmov -0x20(%rbp),%rax\nmov -0x38(%rbp),%edx\nmovslq %edx,%rdx\nmov %ecx,(%rax,%rdx,4)\nsubl $0x1,-0x38(%rbp)\ncmpl $0x0,-0x38(%rbp)\njg 1298 \naddl $0x1,-0x34(%rbp)\nmov -0x34(%rbp),%eax\ncmp -0x44(%rbp),%eax\njle 1289 \nmov -0x20(%rbp),%rax\nmov -0x2c(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nmov %rsi,%rsp\nmov -0x18(%rbp),%rdi\nxor %fs:0x28,%rdi\nje 12fe \ncallq 1060 <__stack_chk_fail@plt>\nmov -0x8(%rbp),%rbx\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_34], edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov eax, [rbp+var_34]\nsub eax, 1\nmov [rbp+var_1C], eax\nshl [rbp+var_34], 1\nmov eax, [rbp+var_1C]\nadd eax, 1\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11E1:\ncmp rsp, rdx\njz short loc_11F8\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_11E1\nloc_11F8:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1222\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1222:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov [rbp+var_28], 0\njmp short loc_1253\nloc_123E:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nmov dword ptr [rax+rdx*4], 0\nadd [rbp+var_28], 1\nloc_1253:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_28]\njge short loc_123E\nmov rax, [rbp+var_10]\nmov dword ptr [rax], 1\nmov [rbp+var_24], 1\njmp short loc_12B8\nloc_126E:\nmov edx, [rbp+var_1C]\nmov eax, [rbp+var_24]\ncmp edx, eax\ncmovle eax, edx\nmov [rbp+var_20], eax\njmp short loc_12AE\nloc_127E:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov eax, [rbp+var_20]\nlea edx, [rax-1]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nadd ecx, eax\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nsub [rbp+var_20], 1\nloc_12AE:\ncmp [rbp+var_20], 0\njg short loc_127E\nadd [rbp+var_24], 1\nloc_12B8:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_34]\njle short loc_126E\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12E4\ncall ___stack_chk_fail\nlocret_12E4:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned __int64 v1; // rax\n void *v2; // rsp\n int v3; // eax\n _BYTE v5[12]; // [rsp+8h] [rbp-40h] BYREF\n int v6; // [rsp+14h] [rbp-34h]\n int i; // [rsp+20h] [rbp-28h]\n int j; // [rsp+24h] [rbp-24h]\n int k; // [rsp+28h] [rbp-20h]\n int v10; // [rsp+2Ch] [rbp-1Ch]\n __int64 v11; // [rsp+30h] [rbp-18h]\n _DWORD *v12; // [rsp+38h] [rbp-10h]\n unsigned __int64 v13; // [rsp+40h] [rbp-8h]\n\n v13 = __readfsqword(0x28u);\n v10 = a1 - 1;\n v6 = 2 * a1;\n v11 = a1 - 1LL;\n v1 = 16 * ((4LL * a1 + 15) / 0x10uLL);\n while ( v5 != &v5[-(v1 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v2 = alloca(v1 & 0xFFF);\n if ( (v1 & 0xFFF) != 0 )\n *(_QWORD *)&v5[(v1 & 0xFFF) - 8] = *(_QWORD *)&v5[(v1 & 0xFFF) - 8];\n v12 = v5;\n for ( i = 0; v10 >= i; ++i )\n v12[i] = 0;\n *v12 = 1;\n for ( j = 1; j <= v6; ++j )\n {\n v3 = j;\n if ( v10 <= j )\n v3 = v10;\n for ( k = v3; k > 0; --k )\n v12[k] += v12[k - 1];\n }\n return (unsigned int)v12[v10];\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_34], edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov eax, [rbp+var_34]\nsub eax, 1\nmov [rbp+var_1C], eax\nshl [rbp+var_34], 1\nmov eax, [rbp+var_1C]\nadd eax, 1\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11E1:\ncmp rsp, rdx\njz short loc_11F8\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_11E1\nloc_11F8:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1222\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1222:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov [rbp+var_28], 0\njmp short loc_1253\nloc_123E:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nmov dword ptr [rax+rdx*4], 0\nadd [rbp+var_28], 1\nloc_1253:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_28]\njge short loc_123E\nmov rax, [rbp+var_10]\nmov dword ptr [rax], 1\nmov [rbp+var_24], 1\njmp short loc_12B8\nloc_126E:\nmov edx, [rbp+var_1C]\nmov eax, [rbp+var_24]\ncmp edx, eax\ncmovle eax, edx\nmov [rbp+var_20], eax\njmp short loc_12AE\nloc_127E:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov eax, [rbp+var_20]\nlea edx, [rax-1]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nadd ecx, eax\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nsub [rbp+var_20], 1\nloc_12AE:\ncmp [rbp+var_20], 0\njg short loc_127E\nadd [rbp+var_24], 1\nloc_12B8:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_34]\njle short loc_126E\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12E4\ncall ___stack_chk_fail\nlocret_12E4:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n unsigned __int64 v1; // rax\n void *v2; // rsp\n int v3; // eax\n _BYTE v5[12]; // [rsp+8h] [rbp-40h] BYREF\n int v6; // [rsp+14h] [rbp-34h]\n int i; // [rsp+20h] [rbp-28h]\n int j; // [rsp+24h] [rbp-24h]\n int k; // [rsp+28h] [rbp-20h]\n int v10; // [rsp+2Ch] [rbp-1Ch]\n __int64 v11; // [rsp+30h] [rbp-18h]\n _DWORD *v12; // [rsp+38h] [rbp-10h]\n unsigned __int64 v13; // [rsp+40h] [rbp-8h]\n\n v13 = __readfsqword(0x28u);\n v10 = a1 - 1;\n v6 = 2 * a1;\n v11 = a1 - 1LL;\n v1 = 16 * ((4LL * a1 + 15) / 0x10uLL);\n while ( v5 != &v5[-(v1 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v2 = alloca(v1 & 0xFFF);\n if ( (v1 & 0xFFF) != 0 )\n *(_QWORD *)&v5[(v1 & 0xFFF) - 8] = *(_QWORD *)&v5[(v1 & 0xFFF) - 8];\n v12 = v5;\n for ( i = 0; v10 >= i; ++i )\n v12[i] = 0;\n *v12 = 1;\n for ( j = 1; j <= v6; ++j )\n {\n v3 = j;\n if ( v10 <= j )\n v3 = v10;\n for ( k = v3; k > 0; --k )\n v12[k] += v12[k - 1];\n }\n return (unsigned int)v12[v10];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n unsigned long long v1;\n void *v2;\n int v3;\n uint8_t v5[12];\n int v6;\n int i;\n int j;\n int k;\n int v10;\n long long v11;\n uint32_t *v12;\n unsigned long long v13;\n v13 = __readfsqword(40u);\n v10 = a1 - 1;\n v6 = 2 * a1;\n v11 = a1 - 1LL;\n v1 = 16 * ((4LL * a1 + 15) / 16uLL);\n while (v5 != &v5[-(v1 & 18446744073709547520LL)])\n ;\n v2 = alloca(v1 & 4095);\n if ((v1 & 4095) != 0)\n *(uint64_t *)&v5[(v1 & 4095) - 8] = *(uint64_t *)&v5[(v1 & 4095) - 8];\n v12 = v5;\n for (i = 0; v10 >= i; ++i) v12[i] = 0;\n *v12 = 1;\n for (j = 1; j <= v6; ++j) {\n v3 = j;\n if (v10 <= j) v3 = v10;\n for (k = v3; k > 0; --k) v12[k] += v12[k - 1];\n }\n return (unsigned int)v12[v10];\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned long long v1;\n void *v2;\n int v3;\n uint8_t v5[12];\n int v6;\n int i;\n int j;\n int k;\n int v10;\n long long v11;\n uint32_t *v12;\n unsigned long long v13;\n v13 = __readfsqword(40u);\n v10 = a1 - 1;\n v6 = 2 * a1;\n v11 = a1 - 1LL;\n v1 = 16 * ((4LL * a1 + 15) / 16uLL);\n while (v5 != &v5[-(v1 & 18446744073709547520LL)])\n ;\n v2 = alloca(v1 & 4095);\n if ((v1 & 4095) != 0)\n *(uint64_t *)&v5[(v1 & 4095) - 8] = *(uint64_t *)&v5[(v1 & 4095) - 8];\n v12 = v5;\n for (i = 0; v10 >= i; ++i) v12[i] = 0;\n *v12 = 1;\n for (j = 1; j <= v6; ++j) {\n v3 = j;\n if (v10 <= j) v3 = v10;\n for (k = v3; k > 0; --k) v12[k] += v12[k - 1];\n }\n return (unsigned int)v12[v10];\n}" + }, + { + "index": 592, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n\n\n", + "func": "int func0(int n) {\n int k = n - 1;\n n = n * 2;\n int C[k + 1];\n for (int i = 0; i < k + 1; i++) {\n C[i] = 0;\n }\n C[0] = 1;\n for (int i = 1; i <= n; i++) {\n for (int j = (i < k ? i : k); j > 0; j--) {\n C[j] = C[j] + C[j - 1];\n }\n }\n return C[k];\n}", + "test": "int main() {\n\n assert(func0(3) == 15);\n\n assert(func0(4) == 56);\n\n assert(func0(1) == 1);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea -0x1(%rdi),%r8d\nlea (%rdi,%rdi,1),%ecx\nmovslq %edi,%rax\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffffff0,%rdx\nand $0xfffffffffffff000,%rax\nmov %rsp,%rsi\nsub %rax,%rsi\nmov %rsi,%rax\ncmp %rax,%rsp\nje 11c3 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11ac \nmov %rdx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 11d9 \norq $0x0,-0x8(%rsp,%rax,1)\nlea 0x3(%rsp),%r10\nmov %r10,%rsi\nshr $0x2,%rsi\nand $0xfffffffffffffffc,%r10\nmov %r10,%r9\ntest %r8d,%r8d\njs 120b \nmov %r10,%rax\nlea -0x1(%rdi),%edx\nlea 0x4(%r10,%rdx,4),%rdx\nmovl $0x0,(%rax)\nadd $0x4,%rax\ncmp %rdx,%rax\njne 11fc \nmovl $0x1,0x0(,%rsi,4)\ntest %ecx,%ecx\njle 1264 \nlea 0x1(%rcx),%edi\nmov $0x1,%esi\nlea -0x4(%r9),%r11\njmp 122f \nadd $0x1,%esi\ncmp %edi,%esi\nje 1264 \ncmp %esi,%r8d\nmov %esi,%edx\ncmovle %r8d,%edx\ntest %edx,%edx\njle 1228 \nmovslq %edx,%rcx\nshl $0x2,%rcx\nlea (%r9,%rcx,1),%rax\nadd %r11,%rcx\nlea -0x1(%rdx),%edx\nshl $0x2,%rdx\nsub %rdx,%rcx\nmov -0x4(%rax),%edx\nadd %edx,(%rax)\nsub $0x4,%rax\ncmp %rcx,%rax\njne 1254 \njmp 1228 \nmovslq %r8d,%r8\nmov (%r10,%r8,4),%eax\nmov -0x8(%rbp),%rdi\nxor %fs:0x28,%rdi\njne 127c \nleaveq\nretq\ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov ecx, edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea edi, [rdi-1]\nmovsxd rdx, ecx\nshl rdx, 2\nlea rax, [rdx+0Fh]\nmov r8, rax\nand r8, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rsi, rsp\nsub rsi, rax\nloc_11A7:\ncmp rsp, rsi\njz short loc_11BE\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11A7\nloc_11BE:\nmov rax, r8\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11D4\nor [rsp+rax+10h+var_18], 0\nloc_11D4:\nlea r8, [rsp+10h+var_D]\nmov rsi, r8\nshr rsi, 2\nand r8, 0FFFFFFFFFFFFFFFCh\ntest edi, edi\njs short loc_1267\nmov rax, r8\nadd rdx, r8\nloc_11EE:\nmov dword ptr [rax], 0\nadd rax, 4\ncmp rax, rdx\njnz short loc_11EE\nmov ds:dword_0[rsi*4], 1\nloc_1208:\nlea r9d, [rcx+rcx+1]\nmov esi, 1\nlea r10, [r8-4]\nloc_1216:\ncmp edi, esi\nmov edx, esi\ncmovle edx, edi\ntest edx, edx\njle short loc_1247\nmovsxd rcx, edx\nshl rcx, 2\nlea rax, [r8+rcx]\nadd rcx, r10\nlea edx, [rdx-1]\nshl rdx, 2\nsub rcx, rdx\nloc_1239:\nmov edx, [rax-4]\nadd [rax], edx\nsub rax, 4\ncmp rax, rcx\njnz short loc_1239\nloc_1247:\nadd esi, 1\ncmp esi, r9d\njnz short loc_1216\nloc_124F:\nmovsxd rdi, edi\nmov eax, [r8+rdi*4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_1278\nleave\nretn\nloc_1267:\nmov ds:dword_0[rsi*4], 1\ntest ecx, ecx\njle short loc_124F\njmp short loc_1208\nloc_1278:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v2; // edi\n unsigned __int64 v3; // rdx\n signed __int64 v4; // rax\n void *v5; // rsp\n _DWORD *v6; // rax\n _DWORD *v7; // rdx\n int v8; // r9d\n int v9; // esi\n int v10; // edx\n __int64 v11; // rcx\n _DWORD *v12; // rax\n _DWORD *v13; // rcx\n _DWORD v16[2]; // [rsp+8h] [rbp-10h] BYREF\n unsigned __int64 v17; // [rsp+10h] [rbp-8h]\n\n v17 = __readfsqword(0x28u);\n v2 = a1 - 1;\n v3 = 4LL * a1;\n while ( v16 != (_DWORD *)((char *)v16 - ((v3 + 15) & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v4 = ((_WORD)v3 + 15) & 0xFF0;\n v5 = alloca(v4);\n if ( (((_WORD)v3 + 15) & 0xFF0) != 0 )\n *(_QWORD *)((char *)&v16[-2] + v4) = *(_QWORD *)((char *)&v16[-2] + v4);\n if ( v2 < 0 )\n {\n v16[0] = 1;\n if ( a1 <= 0 )\n return (unsigned int)v16[v2];\n }\n else\n {\n v6 = v16;\n v7 = &v16[v3 / 4];\n do\n *v6++ = 0;\n while ( v6 != v7 );\n v16[0] = 1;\n }\n v8 = 2 * a1 + 1;\n v9 = 1;\n do\n {\n v10 = v9;\n if ( v2 <= v9 )\n v10 = v2;\n if ( v10 > 0 )\n {\n v11 = v10;\n v12 = &v16[v11];\n v13 = &v16[v11 - 1 - (unsigned int)(v10 - 1)];\n do\n {\n *v12 += *(v12 - 1);\n --v12;\n }\n while ( v12 != v13 );\n }\n ++v9;\n }\n while ( v9 != v8 );\n return (unsigned int)v16[v2];\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov ecx, edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea edi, [rdi-1]\nmovsxd rdx, ecx\nshl rdx, 2\nlea rax, [rdx+0Fh]\nmov r8, rax\nand r8, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rsi, rsp\nsub rsi, rax\nloc_11A7:\ncmp rsp, rsi\njz short loc_11BE\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11A7\nloc_11BE:\nmov rax, r8\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11D4\nor [rsp+rax+10h+var_18], 0\nloc_11D4:\nlea r8, [rsp+10h+var_D]\nmov rsi, r8\nshr rsi, 2\nand r8, 0FFFFFFFFFFFFFFFCh\ntest edi, edi\njs short loc_1267\nmov rax, r8\nadd rdx, r8\nloc_11EE:\nmov dword ptr [rax], 0\nadd rax, 4\ncmp rax, rdx\njnz short loc_11EE\nmov ds:dword_0[rsi*4], 1\nloc_1208:\nlea r9d, [rcx+rcx+1]\nmov esi, 1\nlea r10, [r8-4]\nloc_1216:\ncmp edi, esi\nmov edx, esi\ncmovle edx, edi\ntest edx, edx\njle short loc_1247\nmovsxd rcx, edx\nshl rcx, 2\nlea rax, [r8+rcx]\nadd rcx, r10\nlea edx, [rdx-1]\nshl rdx, 2\nsub rcx, rdx\nloc_1239:\nmov edx, [rax-4]\nadd [rax], edx\nsub rax, 4\ncmp rax, rcx\njnz short loc_1239\nloc_1247:\nadd esi, 1\ncmp esi, r9d\njnz short loc_1216\nloc_124F:\nmovsxd rdi, edi\nmov eax, [r8+rdi*4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_1278\nleave\nretn\nloc_1267:\nmov ds:dword_0[rsi*4], 1\ntest ecx, ecx\njle short loc_124F\njmp short loc_1208\nloc_1278:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n int v2; // edi\n unsigned __int64 v3; // rdx\n signed __int64 v4; // rax\n void *v5; // rsp\n _DWORD *v6; // rax\n _DWORD *v7; // rdx\n int v8; // r9d\n int v9; // esi\n int v10; // edx\n __int64 v11; // rcx\n _DWORD *v12; // rax\n _DWORD *v13; // rcx\n _DWORD v16[2]; // [rsp+8h] [rbp-10h] BYREF\n unsigned __int64 v17; // [rsp+10h] [rbp-8h]\n\n v17 = __readfsqword(0x28u);\n v2 = a1 - 1;\n v3 = 4LL * a1;\n while ( v16 != (_DWORD *)((char *)v16 - ((v3 + 15) & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v4 = ((_WORD)v3 + 15) & 0xFF0;\n v5 = alloca(v4);\n if ( (((_WORD)v3 + 15) & 0xFF0) != 0 )\n *(_QWORD *)((char *)&v16[-2] + v4) = *(_QWORD *)((char *)&v16[-2] + v4);\n if ( v2 < 0 )\n {\n v16[0] = 1;\n if ( a1 <= 0 )\n return (unsigned int)v16[v2];\n }\n else\n {\n v6 = v16;\n v7 = &v16[v3 / 4];\n do\n *v6++ = 0;\n while ( v6 != v7 );\n v16[0] = 1;\n }\n v8 = 2 * a1 + 1;\n v9 = 1;\n do\n {\n v10 = v9;\n if ( v2 <= v9 )\n v10 = v2;\n if ( v10 > 0 )\n {\n v11 = v10;\n v12 = &v16[v11];\n v13 = &v16[v11 - 1 - (unsigned int)(v10 - 1)];\n do\n {\n *v12 += *(v12 - 1);\n --v12;\n }\n while ( v12 != v13 );\n }\n ++v9;\n }\n while ( v9 != v8 );\n return (unsigned int)v16[v2];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n int v2;\n unsigned long long v3;\n signed long long v4;\n void *v5;\n uint32_t *v6;\n uint32_t *v7;\n int v8;\n int v9;\n int v10;\n long long v11;\n uint32_t *v12;\n uint32_t *v13;\n uint32_t v16[2];\n unsigned long long v17;\n v17 = __readfsqword(40u);\n v2 = a1 - 1;\n v3 = 4LL * a1;\n while (v16 !=\n (uint32_t *)((char *)v16 - ((v3 + 15) & 18446744073709547520LL)))\n ;\n v4 = ((unsigned short)v3 + 15) & 4080;\n v5 = alloca(v4);\n if ((((unsigned short)v3 + 15) & 4080) != 0)\n *(uint64_t *)((char *)&v16[-2] + v4) = *(uint64_t *)((char *)&v16[-2] + v4);\n if (v2 < 0) {\n v16[0] = 1;\n if (a1 <= 0) return (unsigned int)v16[v2];\n } else {\n v6 = v16;\n v7 = &v16[v3 / 4];\n do\n *v6++ = 0;\n while (v6 != v7);\n v16[0] = 1;\n }\n v8 = 2 * a1 + 1;\n v9 = 1;\n do {\n v10 = v9;\n if (v2 <= v9) v10 = v2;\n if (v10 > 0) {\n v11 = v10;\n v12 = &v16[v11];\n v13 = &v16[v11 - 1 - (unsigned int)(v10 - 1)];\n do {\n *v12 += *(v12 - 1);\n --v12;\n } while (v12 != v13);\n }\n ++v9;\n } while (v9 != v8);\n return (unsigned int)v16[v2];\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v2;\n unsigned long long v3;\n signed long long v4;\n void *v5;\n uint32_t *v6;\n uint32_t *v7;\n int v8;\n int v9;\n int v10;\n long long v11;\n uint32_t *v12;\n uint32_t *v13;\n uint32_t v16[2];\n unsigned long long v17;\n v17 = __readfsqword(40u);\n v2 = a1 - 1;\n v3 = 4LL * a1;\n while (v16 !=\n (uint32_t *)((char *)v16 - ((v3 + 15) & 18446744073709547520LL)))\n ;\n v4 = ((unsigned short)v3 + 15) & 4080;\n v5 = alloca(v4);\n if ((((unsigned short)v3 + 15) & 4080) != 0)\n *(uint64_t *)((char *)&v16[-2] + v4) = *(uint64_t *)((char *)&v16[-2] + v4);\n if (v2 < 0) {\n v16[0] = 1;\n if (a1 <= 0) return (unsigned int)v16[v2];\n } else {\n v6 = v16;\n v7 = &v16[v3 / 4];\n do\n *v6++ = 0;\n while (v6 != v7);\n v16[0] = 1;\n }\n v8 = 2 * a1 + 1;\n v9 = 1;\n do {\n v10 = v9;\n if (v2 <= v9) v10 = v2;\n if (v10 > 0) {\n v11 = v10;\n v12 = &v16[v11];\n v13 = &v16[v11 - 1 - (unsigned int)(v10 - 1)];\n do {\n *v12 += *(v12 - 1);\n --v12;\n } while (v12 != v13);\n }\n ++v9;\n } while (v9 != v8);\n return (unsigned int)v16[v2];\n}" + }, + { + "index": 592, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n\n\n", + "func": "int func0(int n) {\n int k = n - 1;\n n = n * 2;\n int C[k + 1];\n for (int i = 0; i < k + 1; i++) {\n C[i] = 0;\n }\n C[0] = 1;\n for (int i = 1; i <= n; i++) {\n for (int j = (i < k ? i : k); j > 0; j--) {\n C[j] = C[j] + C[j - 1];\n }\n }\n return C[k];\n}", + "test": "int main() {\n\n assert(func0(3) == 15);\n\n assert(func0(4) == 56);\n\n assert(func0(1) == 1);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nlea -0x1(%rdi),%r8d\nlea (%rdi,%rdi,1),%r9d\nmovslq %edi,%rdi\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0xf(,%rdi,4),%rax\nmov %rsp,%rdi\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rdi\nand $0xfffffffffffffff0,%rdx\nmov %rdi,%rax\ncmp %rax,%rsp\nje 126e \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 1259 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 1326 \nlea 0x3(%rsp),%rdi\nmov %rdi,%rcx\nand $0xfffffffffffffffc,%rdi\nshr $0x2,%rcx\ntest %r8d,%r8d\njs 12af \nmov %r8d,%edx\nmov %rdi,%rax\nlea 0x4(%rdi,%rdx,4),%rdx\nmovl $0x0,(%rax)\nadd $0x4,%rax\ncmp %rdx,%rax\njne 12a0 \nmovl $0x1,0x0(,%rcx,4)\ntest %r9d,%r9d\njle 130e \nadd $0x1,%r9d\nmov $0x1,%esi\nlea -0x4(%rdi),%r10\nnopl 0x0(%rax)\ncmp %esi,%r8d\nmov %esi,%edx\ncmovle %r8d,%edx\ntest %edx,%edx\njle 1306 \nmovslq %edx,%rcx\nsub $0x1,%edx\nshl $0x2,%rcx\nshl $0x2,%rdx\nlea (%rdi,%rcx,1),%rax\nadd %r10,%rcx\nsub %rdx,%rcx\nnopl (%rax)\nmov -0x4(%rax),%edx\nadd %edx,(%rax)\nsub $0x4,%rax\ncmp %rcx,%rax\njne 12f8 \nadd $0x1,%esi\ncmp %r9d,%esi\njne 12d0 \nmovslq %r8d,%r8\nmov (%rdi,%r8,4),%eax\nmov -0x8(%rbp),%rdi\nxor %fs:0x28,%rdi\njne 1331 \nleaveq\nretq\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 1280 \ncallq 1060 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r13\npush r12\nmov r12d, edi\npush rbx\nlea ebx, [rdi-1]\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nmovsxd rax, edi\nmov rcx, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_128E\nloc_1279:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rcx\njnz short loc_1279\nloc_128E:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1354\nloc_12A0:\nlea r8, [rsp+1030h+var_102D]\nmov r13, r8\nand r8, 0FFFFFFFFFFFFFFFCh\nshr r13, 2\ntest ebx, ebx\njs loc_135F\nmov edx, r12d\nmov rdi, r8; s\nxor esi, esi; c\nshl rdx, 2; n\ncall _memset\nlea r9d, [r12+r12+1]\nmov edi, 1\nmov ds:dword_0[r13*4], 1\nmov r8, rax\nlea r10, [rax-4]\nnop word ptr [rax+rax+00000000h]\nloc_12F0:\ncmp ebx, edi\nmov edx, edi\ncmovle edx, ebx\ntest edx, edx\njz short loc_132B\nmovsxd rsi, edx\nsub edx, 1\nshl rsi, 2\nshl rdx, 2\nlea rax, [r8+rsi]\nadd rsi, r10\nmov ecx, [rax]\nsub rsi, rdx\nnop dword ptr [rax]\nloc_1318:\nmov edx, ecx\nmov ecx, [rax-4]\nsub rax, 4\nadd edx, ecx\nmov [rax+4], edx\ncmp rax, rsi\njnz short loc_1318\nloc_132B:\nadd edi, 1\ncmp edi, r9d\njnz short loc_12F0\nloc_1333:\nmovsxd rbx, ebx\nmov eax, [r8+rbx*4]\nmov rdx, [rbp+var_28]\nsub rdx, fs:28h\njnz short loc_136D\nlea rsp, [rbp-18h]\npop rbx\npop r12\npop r13\npop rbp\nretn\nloc_1354:\nor [rsp+rdx+1030h+var_1038], 0\njmp loc_12A0\nloc_135F:\nmov ds:dword_0[r13*4], 1\njmp short loc_1333\nloc_136D:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1)\n{\n int v1; // ebx\n __int64 v2; // rdx\n _DWORD *v3; // rcx\n __int16 v4; // dx\n signed __int64 v5; // rdx\n void *v6; // rsp\n _DWORD *v7; // r8\n _DWORD *v8; // rax\n int v9; // r9d\n int v10; // edi\n char *v11; // r10\n int v12; // edx\n __int64 v13; // rsi\n _DWORD *v14; // rax\n int v15; // ecx\n __int64 v16; // rsi\n int v17; // edx\n _DWORD v20[1022]; // [rsp+8h] [rbp-1030h] BYREF\n _QWORD v21[6]; // [rsp+1008h] [rbp-30h] BYREF\n\n v1 = a1 - 1;\n v21[1] = __readfsqword(0x28u);\n v2 = 4LL * (int)a1 + 15;\n v3 = (_DWORD *)((char *)v21 - (v2 & 0xFFFFFFFFFFFFF000LL));\n v4 = v2 & 0xFFF0;\n if ( v21 != (_QWORD *)v3 )\n {\n while ( v20 != v3 )\n ;\n }\n v5 = v4 & 0xFFF;\n v6 = alloca(v5);\n if ( v5 )\n *(_QWORD *)((char *)&v20[-2] + v5) = *(_QWORD *)((char *)&v20[-2] + v5);\n v7 = v20;\n if ( v1 < 0 )\n {\n v20[0] = 1;\n }\n else\n {\n v8 = memset(v20, 0, 4LL * a1);\n v9 = 2 * a1 + 1;\n v10 = 1;\n v20[0] = 1;\n v7 = v8;\n v11 = (char *)(v8 - 1);\n do\n {\n v12 = v10;\n if ( v1 <= v10 )\n v12 = v1;\n if ( v12 )\n {\n v13 = v12;\n v14 = &v7[v13];\n v15 = v7[v13];\n v16 = (__int64)&v11[v13 * 4 + -4 * (unsigned int)(v12 - 1)];\n do\n {\n v17 = v15;\n v15 = *--v14;\n v14[1] = v15 + v17;\n }\n while ( v14 != (_DWORD *)v16 );\n }\n ++v10;\n }\n while ( v10 != v9 );\n }\n return (unsigned int)v7[v1];\n}", + "ida_strip_asm": "sub_1230:\nendbr64\npush rbp\nmov rbp, rsp\npush r13\npush r12\nmov r12d, edi\npush rbx\nlea ebx, [rdi-1]\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nmovsxd rax, edi\nmov rcx, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_128E\nloc_1279:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rcx\njnz short loc_1279\nloc_128E:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1354\nloc_12A0:\nlea r8, [rsp+1030h+var_102D]\nmov r13, r8\nand r8, 0FFFFFFFFFFFFFFFCh\nshr r13, 2\ntest ebx, ebx\njs loc_135F\nmov edx, r12d\nmov rdi, r8; s\nxor esi, esi; c\nshl rdx, 2; n\ncall _memset\nlea r9d, [r12+r12+1]\nmov edi, 1\nmov ds:dword_0[r13*4], 1\nmov r8, rax\nlea r10, [rax-4]\nnop word ptr [rax+rax+00000000h]\nloc_12F0:\ncmp ebx, edi\nmov edx, edi\ncmovle edx, ebx\ntest edx, edx\njz short loc_132B\nmovsxd rsi, edx\nsub edx, 1\nshl rsi, 2\nshl rdx, 2\nlea rax, [r8+rsi]\nadd rsi, r10\nmov ecx, [rax]\nsub rsi, rdx\nnop dword ptr [rax]\nloc_1318:\nmov edx, ecx\nmov ecx, [rax-4]\nsub rax, 4\nadd edx, ecx\nmov [rax+4], edx\ncmp rax, rsi\njnz short loc_1318\nloc_132B:\nadd edi, 1\ncmp edi, r9d\njnz short loc_12F0\nloc_1333:\nmovsxd rbx, ebx\nmov eax, [r8+rbx*4]\nmov rdx, [rbp+var_28]\nsub rdx, fs:28h\njnz short loc_136D\nlea rsp, [rbp-18h]\npop rbx\npop r12\npop r13\npop rbp\nretn\nloc_1354:\nor [rsp+rdx+1030h+var_1038], 0\njmp loc_12A0\nloc_135F:\nmov ds:dword_0[r13*4], 1\njmp short loc_1333\nloc_136D:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1230(unsigned int a1)\n{\n int v1; // ebx\n __int64 v2; // rdx\n _DWORD *v3; // rcx\n __int16 v4; // dx\n signed __int64 v5; // rdx\n void *v6; // rsp\n _DWORD *v7; // r8\n _DWORD *v8; // rax\n int v9; // r9d\n int v10; // edi\n char *v11; // r10\n int v12; // edx\n __int64 v13; // rsi\n _DWORD *v14; // rax\n int v15; // ecx\n __int64 v16; // rsi\n int v17; // edx\n _DWORD v20[1022]; // [rsp+8h] [rbp-1030h] BYREF\n _QWORD v21[6]; // [rsp+1008h] [rbp-30h] BYREF\n\n v1 = a1 - 1;\n v21[1] = __readfsqword(0x28u);\n v2 = 4LL * (int)a1 + 15;\n v3 = (_DWORD *)((char *)v21 - (v2 & 0xFFFFFFFFFFFFF000LL));\n v4 = v2 & 0xFFF0;\n if ( v21 != (_QWORD *)v3 )\n {\n while ( v20 != v3 )\n ;\n }\n v5 = v4 & 0xFFF;\n v6 = alloca(v5);\n if ( v5 )\n *(_QWORD *)((char *)&v20[-2] + v5) = *(_QWORD *)((char *)&v20[-2] + v5);\n v7 = v20;\n if ( v1 < 0 )\n {\n v20[0] = 1;\n }\n else\n {\n v8 = memset(v20, 0, 4LL * a1);\n v9 = 2 * a1 + 1;\n v10 = 1;\n v20[0] = 1;\n v7 = v8;\n v11 = (char *)(v8 - 1);\n do\n {\n v12 = v10;\n if ( v1 <= v10 )\n v12 = v1;\n if ( v12 )\n {\n v13 = v12;\n v14 = &v7[v13];\n v15 = v7[v13];\n v16 = (__int64)&v11[v13 * 4 + -4 * (unsigned int)(v12 - 1)];\n do\n {\n v17 = v15;\n v15 = *--v14;\n v14[1] = v15 + v17;\n }\n while ( v14 != (_DWORD *)v16 );\n }\n ++v10;\n }\n while ( v10 != v9 );\n }\n return (unsigned int)v7[v1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1230(unsigned int a1) {\n int v1;\n long long v2;\n uint32_t *v3;\n short v4;\n signed long long v5;\n void *v6;\n uint32_t *v7;\n uint32_t *v8;\n int v9;\n int v10;\n char *v11;\n int v12;\n long long v13;\n uint32_t *v14;\n int v15;\n long long v16;\n int v17;\n uint32_t v20[1022];\n uint64_t v21[6];\n v1 = a1 - 1;\n v21[1] = __readfsqword(40u);\n v2 = 4LL * (int)a1 + 15;\n v3 = (uint32_t *)((char *)v21 - (v2 & 18446744073709547520LL));\n v4 = v2 & 65520;\n if (v21 != (uint64_t *)v3) {\n while (v20 != v3)\n ;\n }\n v5 = v4 & 4095;\n v6 = alloca(v5);\n if (v5)\n *(uint64_t *)((char *)&v20[-2] + v5) = *(uint64_t *)((char *)&v20[-2] + v5);\n v7 = v20;\n if (v1 < 0) {\n v20[0] = 1;\n } else {\n v8 = memset(v20, 0, 4LL * a1);\n v9 = 2 * a1 + 1;\n v10 = 1;\n v20[0] = 1;\n v7 = v8;\n v11 = (char *)(v8 - 1);\n do {\n v12 = v10;\n if (v1 <= v10) v12 = v1;\n if (v12) {\n v13 = v12;\n v14 = &v7[v13];\n v15 = v7[v13];\n v16 = (long long)&v11[v13 * 4 + -4 * (unsigned int)(v12 - 1)];\n do {\n v17 = v15;\n v15 = *--v14;\n v14[1] = v15 + v17;\n } while (v14 != (uint32_t *)v16);\n }\n ++v10;\n } while (v10 != v9);\n }\n return (unsigned int)v7[v1];\n}", + "ida_pseudo_norm": "long long func0(unsigned int a1) {\n int v1;\n long long v2;\n uint32_t *v3;\n short v4;\n signed long long v5;\n void *v6;\n uint32_t *v7;\n uint32_t *v8;\n int v9;\n int v10;\n char *v11;\n int v12;\n long long v13;\n uint32_t *v14;\n int v15;\n long long v16;\n int v17;\n uint32_t v20[1022];\n uint64_t v21[6];\n v1 = a1 - 1;\n v21[1] = __readfsqword(40u);\n v2 = 4LL * (int)a1 + 15;\n v3 = (uint32_t *)((char *)v21 - (v2 & 18446744073709547520LL));\n v4 = v2 & 65520;\n if (v21 != (uint64_t *)v3) {\n while (v20 != v3)\n ;\n }\n v5 = v4 & 4095;\n v6 = alloca(v5);\n if (v5)\n *(uint64_t *)((char *)&v20[-2] + v5) = *(uint64_t *)((char *)&v20[-2] + v5);\n v7 = v20;\n if (v1 < 0) {\n v20[0] = 1;\n } else {\n v8 = memset(v20, 0, 4LL * a1);\n v9 = 2 * a1 + 1;\n v10 = 1;\n v20[0] = 1;\n v7 = v8;\n v11 = (char *)(v8 - 1);\n do {\n v12 = v10;\n if (v1 <= v10) v12 = v1;\n if (v12) {\n v13 = v12;\n v14 = &v7[v13];\n v15 = v7[v13];\n v16 = (long long)&v11[v13 * 4 + -4 * (unsigned int)(v12 - 1)];\n do {\n v17 = v15;\n v15 = *--v14;\n v14[1] = v15 + v17;\n } while (v14 != (uint32_t *)v16);\n }\n ++v10;\n } while (v10 != v9);\n }\n return (unsigned int)v7[v1];\n}" + }, + { + "index": 592, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n\n\n", + "func": "int func0(int n) {\n int k = n - 1;\n n = n * 2;\n int C[k + 1];\n for (int i = 0; i < k + 1; i++) {\n C[i] = 0;\n }\n C[0] = 1;\n for (int i = 1; i <= n; i++) {\n for (int j = (i < k ? i : k); j > 0; j--) {\n C[j] = C[j] + C[j - 1];\n }\n }\n return C[k];\n}", + "test": "int main() {\n\n assert(func0(3) == 15);\n\n assert(func0(4) == 56);\n\n assert(func0(1) == 1);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r13\npush %r12\nlea (%rdi,%rdi,1),%r12d\npush %rbx\nlea -0x1(%rdi),%ebx\nmovslq %edi,%rdi\nsub $0x18,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x28(%rbp)\nxor %eax,%eax\nlea 0xf(,%rdi,4),%rax\nmov %rsp,%rdi\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rdi\nand $0xfffffffffffffff0,%rdx\nmov %rdi,%rax\ncmp %rax,%rsp\nje 1292 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 127d \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 13b8 \nlea 0x3(%rsp),%r9\nmov %r9,%r13\nand $0xfffffffffffffffc,%r9\nshr $0x2,%r13\ntest %ebx,%ebx\njs 12cf \nmov %ebx,%eax\nmov %r9,%rdi\nxor %esi,%esi\nlea 0x4(,%rax,4),%rdx\ncallq 1090 \nmov %rax,%r9\nmovl $0x1,0x0(,%r13,4)\ntest %r12d,%r12d\njle 1397 \nlea 0x1(%r12),%r10d\nmov $0x1,%r8d\ncmp %r8d,%ebx\nmov %r8d,%esi\ncmovle %ebx,%esi\ntest %esi,%esi\njle 138a \nmov %esi,%r11d\ncmp $0x3,%esi\njle 1366 \nmov %esi,%edx\nmovslq %esi,%rax\nshr $0x2,%edx\nshl $0x2,%rax\nneg %rdx\nlea -0xc(%r9,%rax,1),%rcx\nlea -0x10(%r9,%rax,1),%rdi\nxor %eax,%eax\nshl $0x4,%rdx\nnopl 0x0(%rax,%rax,1)\nmovdqu (%rcx,%rax,1),%xmm2\nmovdqu (%rdi,%rax,1),%xmm3\npshufd $0x1b,%xmm2,%xmm0\npshufd $0x1b,%xmm3,%xmm1\npaddd %xmm1,%xmm0\npshufd $0x1b,%xmm0,%xmm0\nmovups %xmm0,(%rcx,%rax,1)\nsub $0x10,%rax\ncmp %rdx,%rax\njne 1330 \nmov %esi,%eax\nand $0xfffffffc,%eax\nsub %eax,%esi\ncmp %eax,%r11d\nje 138a \nmovslq %esi,%rax\nlea (%r9,%rax,4),%rax\nmov -0x4(%rax),%edx\nadd %edx,(%rax)\ncmp $0x1,%esi\nje 138a \nmov -0x8(%rax),%ecx\nadd %ecx,%edx\nmov %edx,-0x4(%rax)\ncmp $0x2,%esi\nje 138a \nadd -0xc(%rax),%ecx\nmov %ecx,-0x8(%rax)\nadd $0x1,%r8d\ncmp %r10d,%r8d\njne 12f0 \nmovslq %ebx,%rbx\nmov (%r9,%rbx,4),%eax\nmov -0x28(%rbp),%rbx\nxor %fs:0x28,%rbx\njne 13c3 \nlea -0x18(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %rbp\nretq\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 12a4 \ncallq 1070 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r13\npush r12\nmov r12d, edi\npush rbx\nlea ebx, [rdi-1]\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nmovsxd rax, edi\nmov rcx, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_128E\nloc_1279:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rcx\njnz short loc_1279\nloc_128E:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_13C7\nloc_12A0:\nlea rdi, [rsp+1030h+var_102D]\nmov r13, rdi\nand rdi, 0FFFFFFFFFFFFFFFCh; s\nshr r13, 2\ntest ebx, ebx\njs loc_13D2\nmov edx, r12d\nxor esi, esi; c\nshl rdx, 2; n\ncall _memset\nlea r8d, [r12+r12+1]\nmov esi, 1\nmov ds:dword_0[r13*4], 1\nmov rdi, rax\nnop\nloc_12E0:\ncmp ebx, esi\nmov edx, esi\ncmovle edx, ebx\ntest edx, edx\njz loc_1395\ncmp edx, 3\njle loc_13C1\nmov ecx, edx\nmovsxd rax, edx\nshr ecx, 2\nshl rax, 2\nneg rcx\nlea r9, [rdi+rax-0Ch]\nlea r10, [rdi+rax-10h]\nxor eax, eax\nshl rcx, 4\nnop word ptr [rax+rax+00000000h]\nloc_1320:\nmovdqu xmm0, xmmword ptr [r9+rax]\nmovdqu xmm2, xmmword ptr [r10+rax]\npaddd xmm0, xmm2\nmovups xmmword ptr [r9+rax], xmm0\nsub rax, 10h\ncmp rcx, rax\njnz short loc_1320\nmov ecx, edx\nand ecx, 0FFFFFFFCh\ntest dl, 3\njz short loc_1395\nmov eax, edx\nsub eax, ecx\nloc_134C:\nmov r9d, edx\nsub r9d, ecx\ncmp r9d, 1\njz short loc_138A\nmovsxd rdx, edx\nsub rdx, rcx\nlea rcx, ds:0[rdx*4]\nlea rdx, [rdi+rcx-4]\nmovq xmm0, qword ptr [rdi+rcx-8]\nmovq xmm1, qword ptr [rdx]\npaddd xmm0, xmm1\nmovq qword ptr [rdx], xmm0\ntest r9b, 1\njz short loc_1395\nand r9d, 0FFFFFFFEh\nsub eax, r9d\nloc_138A:\ncdqe\nlea rax, [rdi+rax*4]\nmov edx, [rax-4]\nadd [rax], edx\nloc_1395:\nadd esi, 1\ncmp esi, r8d\njnz loc_12E0\nloc_13A1:\nmovsxd rbx, ebx\nmov eax, [rdi+rbx*4]\nmov rdx, [rbp+var_28]\nsub rdx, fs:28h\njnz short loc_13E0\nlea rsp, [rbp-18h]\npop rbx\npop r12\npop r13\npop rbp\nretn\nloc_13C1:\nmov eax, edx\nxor ecx, ecx\njmp short loc_134C\nloc_13C7:\nor [rsp+rdx+1030h+var_1038], 0\njmp loc_12A0\nloc_13D2:\nmov ds:dword_0[r13*4], 1\njmp short loc_13A1\nloc_13E0:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1)\n{\n int v2; // ebx\n __int64 v3; // rdx\n _DWORD *v4; // rcx\n __int16 v5; // dx\n signed __int64 v6; // rdx\n void *v7; // rsp\n _DWORD *v8; // rdi\n _DWORD *v9; // rax\n int v10; // esi\n int v11; // edx\n __int64 v12; // rax\n __int64 v13; // r9\n __int64 v14; // r10\n __int64 v15; // rax\n __int64 v16; // rcx\n int v17; // eax\n int v18; // r9d\n _DWORD v21[1022]; // [rsp+8h] [rbp-1030h] BYREF\n _QWORD v22[6]; // [rsp+1008h] [rbp-30h] BYREF\n\n v2 = a1 - 1;\n v22[1] = __readfsqword(0x28u);\n v3 = 4LL * (int)a1 + 15;\n v4 = (_DWORD *)((char *)v22 - (v3 & 0xFFFFFFFFFFFFF000LL));\n v5 = v3 & 0xFFF0;\n if ( v22 != (_QWORD *)v4 )\n {\n while ( v21 != v4 )\n ;\n }\n v6 = v5 & 0xFFF;\n v7 = alloca(v6);\n if ( v6 )\n *(_QWORD *)((char *)&v21[-2] + v6) = *(_QWORD *)((char *)&v21[-2] + v6);\n v8 = v21;\n if ( v2 >= 0 )\n {\n v9 = memset(v21, 0, 4LL * a1);\n v10 = 1;\n v21[0] = 1;\n v8 = v9;\n while ( 1 )\n {\n v11 = v10;\n if ( v2 <= v10 )\n v11 = v2;\n if ( !v11 )\n goto LABEL_19;\n if ( v11 <= 3 )\n {\n v17 = v11;\n v16 = 0LL;\n }\n else\n {\n v12 = v11;\n v13 = (__int64)&v8[v12 - 3];\n v14 = (__int64)&v8[v12 - 4];\n v15 = 0LL;\n do\n {\n *(__m128i *)(v13 + v15) = _mm_add_epi32(\n _mm_loadu_si128((const __m128i *)(v13 + v15)),\n _mm_loadu_si128((const __m128i *)(v14 + v15)));\n v15 -= 16LL;\n }\n while ( -16LL * ((unsigned int)v11 >> 2) != v15 );\n v16 = v11 & 0xFFFFFFFC;\n if ( (v11 & 3) == 0 )\n goto LABEL_19;\n v17 = v11 - v16;\n }\n v18 = v11 - v16;\n if ( v11 - (_DWORD)v16 == 1 )\n goto LABEL_18;\n *(_QWORD *)&v8[v11 - v16 - 1] = _mm_add_epi32(\n _mm_loadl_epi64((const __m128i *)&v8[v11 - v16 - 2]),\n _mm_loadl_epi64((const __m128i *)&v8[v11 - v16 - 1])).m128i_u64[0];\n if ( (v18 & 1) != 0 )\n break;\nLABEL_19:\n if ( ++v10 == 2 * a1 + 1 )\n return (unsigned int)v8[v2];\n }\n v17 -= v18 & 0xFFFFFFFE;\nLABEL_18:\n v8[v17] += v8[v17 - 1];\n goto LABEL_19;\n }\n v21[0] = 1;\n return (unsigned int)v8[v2];\n}", + "ida_strip_asm": "sub_1230:\nendbr64\npush rbp\nmov rbp, rsp\npush r13\npush r12\nmov r12d, edi\npush rbx\nlea ebx, [rdi-1]\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nmovsxd rax, edi\nmov rcx, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_128E\nloc_1279:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rcx\njnz short loc_1279\nloc_128E:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_13C7\nloc_12A0:\nlea rdi, [rsp+1030h+var_102D]\nmov r13, rdi\nand rdi, 0FFFFFFFFFFFFFFFCh; s\nshr r13, 2\ntest ebx, ebx\njs loc_13D2\nmov edx, r12d\nxor esi, esi; c\nshl rdx, 2; n\ncall _memset\nlea r8d, [r12+r12+1]\nmov esi, 1\nmov ds:dword_0[r13*4], 1\nmov rdi, rax\nnop\nloc_12E0:\ncmp ebx, esi\nmov edx, esi\ncmovle edx, ebx\ntest edx, edx\njz loc_1395\ncmp edx, 3\njle loc_13C1\nmov ecx, edx\nmovsxd rax, edx\nshr ecx, 2\nshl rax, 2\nneg rcx\nlea r9, [rdi+rax-0Ch]\nlea r10, [rdi+rax-10h]\nxor eax, eax\nshl rcx, 4\nnop word ptr [rax+rax+00000000h]\nloc_1320:\nmovdqu xmm0, xmmword ptr [r9+rax]\nmovdqu xmm2, xmmword ptr [r10+rax]\npaddd xmm0, xmm2\nmovups xmmword ptr [r9+rax], xmm0\nsub rax, 10h\ncmp rcx, rax\njnz short loc_1320\nmov ecx, edx\nand ecx, 0FFFFFFFCh\ntest dl, 3\njz short loc_1395\nmov eax, edx\nsub eax, ecx\nloc_134C:\nmov r9d, edx\nsub r9d, ecx\ncmp r9d, 1\njz short loc_138A\nmovsxd rdx, edx\nsub rdx, rcx\nlea rcx, ds:0[rdx*4]\nlea rdx, [rdi+rcx-4]\nmovq xmm0, qword ptr [rdi+rcx-8]\nmovq xmm1, qword ptr [rdx]\npaddd xmm0, xmm1\nmovq qword ptr [rdx], xmm0\ntest r9b, 1\njz short loc_1395\nand r9d, 0FFFFFFFEh\nsub eax, r9d\nloc_138A:\ncdqe\nlea rax, [rdi+rax*4]\nmov edx, [rax-4]\nadd [rax], edx\nloc_1395:\nadd esi, 1\ncmp esi, r8d\njnz loc_12E0\nloc_13A1:\nmovsxd rbx, ebx\nmov eax, [rdi+rbx*4]\nmov rdx, [rbp+var_28]\nsub rdx, fs:28h\njnz short loc_13E0\nlea rsp, [rbp-18h]\npop rbx\npop r12\npop r13\npop rbp\nretn\nloc_13C1:\nmov eax, edx\nxor ecx, ecx\njmp short loc_134C\nloc_13C7:\nor [rsp+rdx+1030h+var_1038], 0\njmp loc_12A0\nloc_13D2:\nmov ds:dword_0[r13*4], 1\njmp short loc_13A1\nloc_13E0:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1230(unsigned int a1)\n{\n int v2; // ebx\n __int64 v3; // rdx\n _DWORD *v4; // rcx\n __int16 v5; // dx\n signed __int64 v6; // rdx\n void *v7; // rsp\n _DWORD *v8; // rdi\n _DWORD *v9; // rax\n int v10; // esi\n int v11; // edx\n __int64 v12; // rax\n __int64 v13; // r9\n __int64 v14; // r10\n __int64 v15; // rax\n __int64 v16; // rcx\n int v17; // eax\n int v18; // r9d\n _DWORD v21[1022]; // [rsp+8h] [rbp-1030h] BYREF\n _QWORD v22[6]; // [rsp+1008h] [rbp-30h] BYREF\n\n v2 = a1 - 1;\n v22[1] = __readfsqword(0x28u);\n v3 = 4LL * (int)a1 + 15;\n v4 = (_DWORD *)((char *)v22 - (v3 & 0xFFFFFFFFFFFFF000LL));\n v5 = v3 & 0xFFF0;\n if ( v22 != (_QWORD *)v4 )\n {\n while ( v21 != v4 )\n ;\n }\n v6 = v5 & 0xFFF;\n v7 = alloca(v6);\n if ( v6 )\n *(_QWORD *)((char *)&v21[-2] + v6) = *(_QWORD *)((char *)&v21[-2] + v6);\n v8 = v21;\n if ( v2 >= 0 )\n {\n v9 = memset(v21, 0, 4LL * a1);\n v10 = 1;\n v21[0] = 1;\n v8 = v9;\n while ( 1 )\n {\n v11 = v10;\n if ( v2 <= v10 )\n v11 = v2;\n if ( !v11 )\n goto LABEL_19;\n if ( v11 <= 3 )\n {\n v17 = v11;\n v16 = 0LL;\n }\n else\n {\n v12 = v11;\n v13 = (__int64)&v8[v12 - 3];\n v14 = (__int64)&v8[v12 - 4];\n v15 = 0LL;\n do\n {\n *(__m128i *)(v13 + v15) = _mm_add_epi32(\n _mm_loadu_si128((const __m128i *)(v13 + v15)),\n _mm_loadu_si128((const __m128i *)(v14 + v15)));\n v15 -= 16LL;\n }\n while ( -16LL * ((unsigned int)v11 >> 2) != v15 );\n v16 = v11 & 0xFFFFFFFC;\n if ( (v11 & 3) == 0 )\n goto LABEL_19;\n v17 = v11 - v16;\n }\n v18 = v11 - v16;\n if ( v11 - (_DWORD)v16 == 1 )\n goto LABEL_18;\n *(_QWORD *)&v8[v11 - v16 - 1] = _mm_add_epi32(\n _mm_loadl_epi64((const __m128i *)&v8[v11 - v16 - 2]),\n _mm_loadl_epi64((const __m128i *)&v8[v11 - v16 - 1])).m128i_u64[0];\n if ( (v18 & 1) != 0 )\n break;\nLABEL_19:\n if ( ++v10 == 2 * a1 + 1 )\n return (unsigned int)v8[v2];\n }\n v17 -= v18 & 0xFFFFFFFE;\nLABEL_18:\n v8[v17] += v8[v17 - 1];\n goto LABEL_19;\n }\n v21[0] = 1;\n return (unsigned int)v8[v2];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1230(unsigned int a1) {\n int v2;\n long long v3;\n uint32_t *v4;\n short v5;\n signed long long v6;\n void *v7;\n uint32_t *v8;\n uint32_t *v9;\n int v10;\n int v11;\n long long v12;\n long long v13;\n long long v14;\n long long v15;\n long long v16;\n int v17;\n int v18;\n uint32_t v21[1022];\n uint64_t v22[6];\n v2 = a1 - 1;\n v22[1] = __readfsqword(40u);\n v3 = 4LL * (int)a1 + 15;\n v4 = (uint32_t *)((char *)v22 - (v3 & 18446744073709547520LL));\n v5 = v3 & 65520;\n if (v22 != (uint64_t *)v4) {\n while (v21 != v4)\n ;\n }\n v6 = v5 & 4095;\n v7 = alloca(v6);\n if (v6)\n *(uint64_t *)((char *)&v21[-2] + v6) = *(uint64_t *)((char *)&v21[-2] + v6);\n v8 = v21;\n if (v2 >= 0) {\n v9 = memset(v21, 0, 4LL * a1);\n v10 = 1;\n v21[0] = 1;\n v8 = v9;\n while (1) {\n v11 = v10;\n if (v2 <= v10) v11 = v2;\n if (!v11) goto LABEL_19;\n if (v11 <= 3) {\n v17 = v11;\n v16 = 0LL;\n } else {\n v12 = v11;\n v13 = (long long)&v8[v12 - 3];\n v14 = (long long)&v8[v12 - 4];\n v15 = 0LL;\n do {\n *(__m128i *)(v13 + v15) =\n _mm_add_epi32(_mm_loadu_si128((const __m128i *)(v13 + v15)),\n _mm_loadu_si128((const __m128i *)(v14 + v15)));\n v15 -= 16LL;\n } while (-16LL * ((unsigned int)v11 >> 2) != v15);\n v16 = v11 & 4294967292;\n if ((v11 & 3) == 0) goto LABEL_19;\n v17 = v11 - v16;\n }\n v18 = v11 - v16;\n if (v11 - (uint32_t)v16 == 1) goto LABEL_18;\n *(uint64_t *)&v8[v11 - v16 - 1] =\n _mm_add_epi32(_mm_loadl_epi64((const __m128i *)&v8[v11 - v16 - 2]),\n _mm_loadl_epi64((const __m128i *)&v8[v11 - v16 - 1]))\n .m128i_u64[0];\n if ((v18 & 1) != 0) break;\n LABEL_19:\n if (++v10 == 2 * a1 + 1) return (unsigned int)v8[v2];\n }\n v17 -= v18 & 4294967294;\n LABEL_18:\n v8[v17] += v8[v17 - 1];\n goto LABEL_19;\n }\n v21[0] = 1;\n return (unsigned int)v8[v2];\n}", + "ida_pseudo_norm": "long long func0(unsigned int a1) {\n int v2;\n long long v3;\n uint32_t *v4;\n short v5;\n signed long long v6;\n void *v7;\n uint32_t *v8;\n uint32_t *v9;\n int v10;\n int v11;\n long long v12;\n long long v13;\n long long v14;\n long long v15;\n long long v16;\n int v17;\n int v18;\n uint32_t v21[1022];\n uint64_t v22[6];\n v2 = a1 - 1;\n v22[1] = __readfsqword(40u);\n v3 = 4LL * (int)a1 + 15;\n v4 = (uint32_t *)((char *)v22 - (v3 & 18446744073709547520LL));\n v5 = v3 & 65520;\n if (v22 != (uint64_t *)v4) {\n while (v21 != v4)\n ;\n }\n v6 = v5 & 4095;\n v7 = alloca(v6);\n if (v6)\n *(uint64_t *)((char *)&v21[-2] + v6) = *(uint64_t *)((char *)&v21[-2] + v6);\n v8 = v21;\n if (v2 >= 0) {\n v9 = memset(v21, 0, 4LL * a1);\n v10 = 1;\n v21[0] = 1;\n v8 = v9;\n while (1) {\n v11 = v10;\n if (v2 <= v10) v11 = v2;\n if (!v11) goto LABEL_19;\n if (v11 <= 3) {\n v17 = v11;\n v16 = 0LL;\n } else {\n v12 = v11;\n v13 = (long long)&v8[v12 - 3];\n v14 = (long long)&v8[v12 - 4];\n v15 = 0LL;\n do {\n *(__m128i *)(v13 + v15) =\n _mm_add_epi32(_mm_loadu_si128((const __m128i *)(v13 + v15)),\n _mm_loadu_si128((const __m128i *)(v14 + v15)));\n v15 -= 16LL;\n } while (-16LL * ((unsigned int)v11 >> 2) != v15);\n v16 = v11 & 4294967292;\n if ((v11 & 3) == 0) goto LABEL_19;\n v17 = v11 - v16;\n }\n v18 = v11 - v16;\n if (v11 - (uint32_t)v16 == 1) goto LABEL_18;\n *(uint64_t *)&v8[v11 - v16 - 1] =\n _mm_add_epi32(_mm_loadl_epi64((const __m128i *)&v8[v11 - v16 - 2]),\n _mm_loadl_epi64((const __m128i *)&v8[v11 - v16 - 1]))\n .m128i_u64[0];\n if ((v18 & 1) != 0) break;\n LABEL_19:\n if (++v10 == 2 * a1 + 1) return (unsigned int)v8[v2];\n }\n v17 -= v18 & 4294967294;\n LABEL_18:\n v8[v17] += v8[v17 - 1];\n goto LABEL_19;\n }\n v21[0] = 1;\n return (unsigned int)v8[v2];\n}" + }, + { + "index": 593, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* ip) {\n regex_t regex;\n regmatch_t matches[1];\n char pattern[] = \"\\\\.0+\";\n char* result = (char*)malloc(strlen(ip) + 1);\n char* current_location;\n regcomp(®ex, pattern, REG_EXTENDED);\n strcpy(result, ip);\n current_location = result;\n while (regexec(®ex, current_location, 1, matches, 0) == 0) {\n size_t len = strlen(current_location);\n size_t start = matches[0].rm_so;\n size_t end = matches[0].rm_eo;\n memmove(current_location + start + 1, current_location + end,\n len - end + 1);\n current_location += start + 1;\n }\n regfree(®ex);\n return result;\n}", + "test": "int main() {\n\n char* test1 = func0(\"216.08.094.196\");\n\n assert(strcmp(test1, \"216.8.94.196\") == 0);\n\n free(test1);\n\n\n\n char* test2 = func0(\"12.01.024\");\n\n assert(strcmp(test2, \"12.1.24\") == 0);\n\n free(test2);\n\n \n\n char* test3 = func0(\"216.08.094.0196\");\n\n assert(strcmp(test3, \"216.8.94.196\") == 0);\n\n free(test3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0xa0,%rsp\nmov %rdi,-0x98(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovl $0x2b302e5c,-0xd(%rbp)\nmovb $0x0,-0x9(%rbp)\nmov -0x98(%rbp),%rax\nmov %rax,%rdi\ncallq 1120 \nadd $0x1,%rax\nmov %rax,%rdi\ncallq 1170 \nmov %rax,-0x80(%rbp)\nlea -0xd(%rbp),%rcx\nlea -0x60(%rbp),%rax\nmov $0x1,%edx\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 1150 \nmov -0x98(%rbp),%rdx\nmov -0x80(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1100 \nmov -0x80(%rbp),%rax\nmov %rax,-0x88(%rbp)\njmp 137e \nmov -0x88(%rbp),%rax\nmov %rax,%rdi\ncallq 1120 \nmov %rax,-0x78(%rbp)\nmov -0x18(%rbp),%eax\ncltq\nmov %rax,-0x70(%rbp)\nmov -0x14(%rbp),%eax\ncltq\nmov %rax,-0x68(%rbp)\nmov -0x78(%rbp),%rax\nsub -0x68(%rbp),%rax\nlea 0x1(%rax),%rdx\nmov -0x88(%rbp),%rcx\nmov -0x68(%rbp),%rax\nadd %rax,%rcx\nmov -0x70(%rbp),%rax\nlea 0x1(%rax),%rsi\nmov -0x88(%rbp),%rax\nadd %rsi,%rax\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 1190 \nmov -0x70(%rbp),%rax\nadd $0x1,%rax\nadd %rax,-0x88(%rbp)\nlea -0x18(%rbp),%rdx\nmov -0x88(%rbp),%rsi\nlea -0x60(%rbp),%rax\nmov $0x0,%r8d\nmov %rdx,%rcx\nmov $0x1,%edx\nmov %rax,%rdi\ncallq 1180 \ntest %eax,%eax\nje 1313 \nlea -0x60(%rbp),%rax\nmov %rax,%rdi\ncallq 1110 \nmov -0x80(%rbp),%rax\nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 13cf \ncallq 1130 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0A0h\nmov [rbp+s], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov dword ptr [rbp+pattern], 2B302E5Ch\nmov [rbp+var_9], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nadd rax, 1\nmov rdi, rax; size\ncall _malloc\nmov [rbp+dest], rax\nlea rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov rdx, [rbp+s]\nmov rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\nmov rax, [rbp+dest]\nmov [rbp+string], rax\njmp short loc_137E\nloc_1313:\nmov rax, [rbp+string]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_78], rax\nmov eax, [rbp+pmatch.rm_so]\ncdqe\nmov [rbp+var_70], rax\nmov eax, [rbp+pmatch.rm_eo]\ncdqe\nmov [rbp+var_68], rax\nmov rax, [rbp+var_78]\nsub rax, [rbp+var_68]\nlea rdx, [rax+1]; n\nmov rcx, [rbp+string]\nmov rax, [rbp+var_68]\nadd rcx, rax\nmov rax, [rbp+var_70]\nlea rsi, [rax+1]\nmov rax, [rbp+string]\nadd rax, rsi\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _memmove\nmov rax, [rbp+var_70]\nadd rax, 1\nadd [rbp+string], rax\nloc_137E:\nlea rdx, [rbp+pmatch]\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov rcx, rdx; pmatch\nmov edx, 1; nmatch\nmov rdi, rax; preg\ncall _regexec\ntest eax, eax\njz loc_1313\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nmov rax, [rbp+dest]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_13CF\ncall ___stack_chk_fail\nlocret_13CF:\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(const char *a1)\n{\n size_t v1; // rax\n int i; // eax\n char *string; // [rsp+18h] [rbp-88h]\n char *dest; // [rsp+20h] [rbp-80h]\n size_t v6; // [rsp+28h] [rbp-78h]\n __int64 rm_so; // [rsp+30h] [rbp-70h]\n regex_t preg; // [rsp+40h] [rbp-60h] BYREF\n regmatch_t pmatch; // [rsp+88h] [rbp-18h] BYREF\n char pattern[5]; // [rsp+93h] [rbp-Dh] BYREF\n unsigned __int64 v11; // [rsp+98h] [rbp-8h]\n\n v11 = __readfsqword(0x28u);\n strcpy(pattern, \"\\\\.0+\");\n v1 = strlen(a1);\n dest = (char *)malloc(v1 + 1);\n regcomp(&preg, pattern, 1);\n strcpy(dest, a1);\n string = dest;\n for ( i = regexec(&preg, dest, 1uLL, &pmatch, 0); !i; i = regexec(&preg, string, 1uLL, &pmatch, 0) )\n {\n v6 = strlen(string);\n rm_so = pmatch.rm_so;\n memmove(&string[pmatch.rm_so + 1], &string[pmatch.rm_eo], v6 - pmatch.rm_eo + 1);\n string += rm_so + 1;\n }\n regfree(&preg);\n return dest;\n}", + "ida_strip_asm": "sub_1289:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0A0h\nmov [rbp+s], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov dword ptr [rbp+pattern], 2B302E5Ch\nmov [rbp+var_9], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nadd rax, 1\nmov rdi, rax; size\ncall _malloc\nmov [rbp+dest], rax\nlea rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov rdx, [rbp+s]\nmov rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\nmov rax, [rbp+dest]\nmov [rbp+string], rax\njmp short loc_137E\nloc_1313:\nmov rax, [rbp+string]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_78], rax\nmov eax, [rbp+pmatch.rm_so]\ncdqe\nmov [rbp+var_70], rax\nmov eax, [rbp+pmatch.rm_eo]\ncdqe\nmov [rbp+var_68], rax\nmov rax, [rbp+var_78]\nsub rax, [rbp+var_68]\nlea rdx, [rax+1]; n\nmov rcx, [rbp+string]\nmov rax, [rbp+var_68]\nadd rcx, rax\nmov rax, [rbp+var_70]\nlea rsi, [rax+1]\nmov rax, [rbp+string]\nadd rax, rsi\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _memmove\nmov rax, [rbp+var_70]\nadd rax, 1\nadd [rbp+string], rax\nloc_137E:\nlea rdx, [rbp+pmatch]\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov rcx, rdx; pmatch\nmov edx, 1; nmatch\nmov rdi, rax; preg\ncall _regexec\ntest eax, eax\njz loc_1313\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nmov rax, [rbp+dest]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_13CF\ncall ___stack_chk_fail\nlocret_13CF:\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1289(const char *a1)\n{\n size_t v1; // rax\n int i; // eax\n char *string; // [rsp+18h] [rbp-88h]\n char *dest; // [rsp+20h] [rbp-80h]\n size_t v6; // [rsp+28h] [rbp-78h]\n __int64 rm_so; // [rsp+30h] [rbp-70h]\n regex_t preg; // [rsp+40h] [rbp-60h] BYREF\n regmatch_t pmatch; // [rsp+88h] [rbp-18h] BYREF\n char pattern[5]; // [rsp+93h] [rbp-Dh] BYREF\n unsigned __int64 v11; // [rsp+98h] [rbp-8h]\n\n v11 = __readfsqword(0x28u);\n strcpy(pattern, \"\\\\.0+\");\n v1 = strlen(a1);\n dest = (char *)malloc(v1 + 1);\n regcomp(&preg, pattern, 1);\n strcpy(dest, a1);\n string = dest;\n for ( i = regexec(&preg, dest, 1uLL, &pmatch, 0); !i; i = regexec(&preg, string, 1uLL, &pmatch, 0) )\n {\n v6 = strlen(string);\n rm_so = pmatch.rm_so;\n memmove(&string[pmatch.rm_so + 1], &string[pmatch.rm_eo], v6 - pmatch.rm_eo + 1);\n string += rm_so + 1;\n }\n regfree(&preg);\n return dest;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1289(const char *a1) {\n unsigned int v1;\n int i;\n char *string;\n char *dest;\n unsigned int v6;\n long long rm_so;\n regex_t preg;\n regmatch_t pmatch;\n char pattern[5];\n unsigned long long v11;\n v11 = __readfsqword(40u);\n strcpy(pattern, \"\\\\.0+\");\n v1 = strlen(a1);\n dest = (char *)malloc(v1 + 1);\n regcomp(&preg, pattern, 1);\n strcpy(dest, a1);\n string = dest;\n for (i = regexec(&preg, dest, 1uLL, &pmatch, 0); !i;\n i = regexec(&preg, string, 1uLL, &pmatch, 0)) {\n v6 = strlen(string);\n rm_so = pmatch.rm_so;\n memmove(&string[pmatch.rm_so + 1], &string[pmatch.rm_eo],\n v6 - pmatch.rm_eo + 1);\n string += rm_so + 1;\n }\n regfree(&preg);\n return dest;\n}", + "ida_pseudo_norm": "char *func0(const char *a1) {\n unsigned int v1;\n int i;\n char *string;\n char *dest;\n unsigned int v6;\n long long rm_so;\n regex_t preg;\n regmatch_t pmatch;\n char pattern[5];\n unsigned long long v11;\n v11 = __readfsqword(40u);\n strcpy(pattern, \"\\\\.0+\");\n v1 = strlen(a1);\n dest = (char *)malloc(v1 + 1);\n regcomp(&preg, pattern, 1);\n strcpy(dest, a1);\n string = dest;\n for (i = regexec(&preg, dest, 1uLL, &pmatch, 0); !i;\n i = regexec(&preg, string, 1uLL, &pmatch, 0)) {\n v6 = strlen(string);\n rm_so = pmatch.rm_so;\n memmove(&string[pmatch.rm_so + 1], &string[pmatch.rm_eo],\n v6 - pmatch.rm_eo + 1);\n string += rm_so + 1;\n }\n regfree(&preg);\n return dest;\n}" + }, + { + "index": 593, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* ip) {\n regex_t regex;\n regmatch_t matches[1];\n char pattern[] = \"\\\\.0+\";\n char* result = (char*)malloc(strlen(ip) + 1);\n char* current_location;\n regcomp(®ex, pattern, REG_EXTENDED);\n strcpy(result, ip);\n current_location = result;\n while (regexec(®ex, current_location, 1, matches, 0) == 0) {\n size_t len = strlen(current_location);\n size_t start = matches[0].rm_so;\n size_t end = matches[0].rm_eo;\n memmove(current_location + start + 1, current_location + end,\n len - end + 1);\n current_location += start + 1;\n }\n regfree(®ex);\n return result;\n}", + "test": "int main() {\n\n char* test1 = func0(\"216.08.094.196\");\n\n assert(strcmp(test1, \"216.8.94.196\") == 0);\n\n free(test1);\n\n\n\n char* test2 = func0(\"12.01.024\");\n\n assert(strcmp(test2, \"12.1.24\") == 0);\n\n free(test2);\n\n \n\n char* test3 = func0(\"216.08.094.0196\");\n\n assert(strcmp(test3, \"216.8.94.196\") == 0);\n\n free(test3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nsub $0x60,%rsp\nmov %rdi,%rbx\nmov %fs:0x28,%rax\nmov %rax,0x58(%rsp)\nxor %eax,%eax\nmovl $0x2b302e5c,0x53(%rsp)\nmovb $0x0,0x57(%rsp)\nmov $0xffffffffffffffff,%rcx\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rdi\nnot %rdi\ncallq 1130 \nmov %rax,%r12\nlea 0x53(%rsp),%rsi\nmov %rsp,%rdi\nmov $0x1,%edx\ncallq 1120 \nmov %rbx,%rsi\nmov %r12,%rdi\ncallq 10e0 \nmov %r12,%rbx\nlea 0x48(%rsp),%rbp\nmov %rsp,%rdi\nmov $0x0,%r8d\nmov %rbp,%rcx\nmov $0x1,%edx\nmov %rbx,%rsi\ncallq 1140 \ntest %eax,%eax\njne 1305 \nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nmov %rbx,%rdi\nrepnz scas %es:(%rdi),%al\nnot %rcx\nmovslq 0x4c(%rsp),%rax\nlea (%rbx,%rax,1),%rsi\nmovslq 0x48(%rsp),%rdx\nlea 0x1(%rbx,%rdx,1),%rbx\nmov %rcx,%rdx\nsub %rax,%rdx\nmov %rbx,%rdi\ncallq 1150 \njmp 12b1 \nmov %rsp,%rdi\ncallq 10f0 \nmov 0x58(%rsp),%rax\nxor %fs:0x28,%rax\njne 1329 \nmov %r12,%rax\nadd $0x60,%rsp\npop %rbx\npop %rbp\npop %r12\nretq\ncallq 1100 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 60h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+88h+var_30], rax\nxor eax, eax\nmov dword ptr [rsp+88h+pattern], 2B302E5Ch\nmov [rsp+88h+var_31], 0\ncall _strlen\nlea r12, [rax+1]\nmov rdi, r12; size\ncall _malloc\nmov r14, rax\nlea rsi, [rsp+88h+pattern]; pattern\nmov rdi, rsp; preg\nmov edx, 1; cflags\ncall _regcomp\nmov rdx, r12\nmov rsi, rbx\nmov rdi, r14\ncall ___strcpy_chk\nmov rbx, r12\nmov rbp, r14\nlea r13, [rsp+88h+pmatch]\njmp short loc_134E\nloc_12FA:\nmov rdi, rbp; s\ncall _strlen\nmovsxd r8, [rsp+88h+pmatch.rm_eo]\nlea rdi, [rbp+r8+0]\nmovsxd rdx, [rsp+88h+pmatch.rm_so]\nadd rdx, 1\ncmp r12, rbx\nmov rsi, rbx\ncmovnb rsi, r12\nlea r9, [rdx+rsi]\nmov rcx, r9\nsub rcx, rbx\ncmp rcx, rsi\ncmovb rcx, rsi\nsub rbx, r9\nadd rbx, rcx\nadd rbp, rdx\nsub rax, r8\nlea rdx, [rax+1]\nmov rcx, rbx\nmov rsi, rdi\nmov rdi, rbp\ncall ___memmove_chk\nloc_134E:\nmov rdi, rsp; preg\nmov r8d, 0; eflags\nmov rcx, r13; pmatch\nmov edx, 1; nmatch\nmov rsi, rbp; string\ncall _regexec\ntest eax, eax\njz short loc_12FA\nmov rdi, rsp; preg\ncall _regfree\nmov rax, [rsp+88h+var_30]\nsub rax, fs:28h\njnz short loc_1393\nmov rax, r14\nadd rsp, 60h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1393:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n size_t v1; // r12\n const char *v2; // r14\n size_t v3; // rbx\n const char *i; // rbp\n size_t v5; // rax\n const char *v6; // rdi\n __int64 v7; // rdx\n size_t v8; // rsi\n size_t v9; // rcx\n regex_t v11; // [rsp+0h] [rbp-88h] BYREF\n regmatch_t pmatch; // [rsp+48h] [rbp-40h] BYREF\n char pattern[5]; // [rsp+53h] [rbp-35h] BYREF\n unsigned __int64 v14; // [rsp+58h] [rbp-30h]\n\n v14 = __readfsqword(0x28u);\n strcpy(pattern, \"\\\\.0+\");\n v1 = strlen(a1) + 1;\n v2 = (const char *)malloc(v1);\n regcomp(&v11, pattern, 1);\n __strcpy_chk(v2, a1, v1);\n v3 = v1;\n for ( i = v2; !regexec(&v11, i, 1uLL, &pmatch, 0); __memmove_chk(i, v6, v5 - pmatch.rm_eo + 1, v3) )\n {\n v5 = strlen(i);\n v6 = &i[pmatch.rm_eo];\n v7 = pmatch.rm_so + 1LL;\n v8 = v3;\n if ( v1 >= v3 )\n v8 = v1;\n v9 = v7 + v8 - v3;\n if ( v9 < v8 )\n v9 = v8;\n v3 = v9 + v3 - (v7 + v8);\n i += v7;\n }\n regfree(&v11);\n return v2;\n}", + "ida_strip_asm": "sub_1289:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 60h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+88h+var_30], rax\nxor eax, eax\nmov dword ptr [rsp+88h+pattern], 2B302E5Ch\nmov [rsp+88h+var_31], 0\ncall _strlen\nlea r12, [rax+1]\nmov rdi, r12; size\ncall _malloc\nmov r14, rax\nlea rsi, [rsp+88h+pattern]; pattern\nmov rdi, rsp; preg\nmov edx, 1; cflags\ncall _regcomp\nmov rdx, r12\nmov rsi, rbx\nmov rdi, r14\ncall ___strcpy_chk\nmov rbx, r12\nmov rbp, r14\nlea r13, [rsp+88h+pmatch]\njmp short loc_134E\nloc_12FA:\nmov rdi, rbp; s\ncall _strlen\nmovsxd r8, [rsp+88h+pmatch.rm_eo]\nlea rdi, [rbp+r8+0]\nmovsxd rdx, [rsp+88h+pmatch.rm_so]\nadd rdx, 1\ncmp r12, rbx\nmov rsi, rbx\ncmovnb rsi, r12\nlea r9, [rdx+rsi]\nmov rcx, r9\nsub rcx, rbx\ncmp rcx, rsi\ncmovb rcx, rsi\nsub rbx, r9\nadd rbx, rcx\nadd rbp, rdx\nsub rax, r8\nlea rdx, [rax+1]\nmov rcx, rbx\nmov rsi, rdi\nmov rdi, rbp\ncall ___memmove_chk\nloc_134E:\nmov rdi, rsp; preg\nmov r8d, 0; eflags\nmov rcx, r13; pmatch\nmov edx, 1; nmatch\nmov rsi, rbp; string\ncall _regexec\ntest eax, eax\njz short loc_12FA\nmov rdi, rsp; preg\ncall _regfree\nmov rax, [rsp+88h+var_30]\nsub rax, fs:28h\njnz short loc_1393\nmov rax, r14\nadd rsp, 60h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1393:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_1289(const char *a1)\n{\n size_t v1; // r12\n const char *v2; // r14\n size_t v3; // rbx\n const char *i; // rbp\n size_t v5; // rax\n const char *v6; // rdi\n __int64 v7; // rdx\n size_t v8; // rsi\n size_t v9; // rcx\n regex_t v11; // [rsp+0h] [rbp-88h] BYREF\n regmatch_t pmatch; // [rsp+48h] [rbp-40h] BYREF\n char pattern[5]; // [rsp+53h] [rbp-35h] BYREF\n unsigned __int64 v14; // [rsp+58h] [rbp-30h]\n\n v14 = __readfsqword(0x28u);\n strcpy(pattern, \"\\\\.0+\");\n v1 = strlen(a1) + 1;\n v2 = (const char *)malloc(v1);\n regcomp(&v11, pattern, 1);\n __strcpy_chk(v2, a1, v1);\n v3 = v1;\n for ( i = v2; !regexec(&v11, i, 1uLL, &pmatch, 0); __memmove_chk(i, v6, v5 - pmatch.rm_eo + 1, v3) )\n {\n v5 = strlen(i);\n v6 = &i[pmatch.rm_eo];\n v7 = pmatch.rm_so + 1LL;\n v8 = v3;\n if ( v1 >= v3 )\n v8 = v1;\n v9 = v7 + v8 - v3;\n if ( v9 < v8 )\n v9 = v8;\n v3 = v9 + v3 - (v7 + v8);\n i += v7;\n }\n regfree(&v11);\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1289(const char *a1) {\n unsigned int v1;\n const char *v2;\n unsigned int v3;\n const char *i;\n unsigned int v5;\n const char *v6;\n long long v7;\n unsigned int v8;\n unsigned int v9;\n regex_t v11;\n regmatch_t pmatch;\n char pattern[5];\n unsigned long long v14;\n v14 = __readfsqword(40u);\n strcpy(pattern, \"\\\\.0+\");\n v1 = strlen(a1) + 1;\n v2 = (const char *)malloc(v1);\n regcomp(&v11, pattern, 1);\n __strcpy_chk(v2, a1, v1);\n v3 = v1;\n for (i = v2; !regexec(&v11, i, 1uLL, &pmatch, 0);\n __memmove_chk(i, v6, v5 - pmatch.rm_eo + 1, v3)) {\n v5 = strlen(i);\n v6 = &i[pmatch.rm_eo];\n v7 = pmatch.rm_so + 1LL;\n v8 = v3;\n if (v1 >= v3) v8 = v1;\n v9 = v7 + v8 - v3;\n if (v9 < v8) v9 = v8;\n v3 = v9 + v3 - (v7 + v8);\n i += v7;\n }\n regfree(&v11);\n return v2;\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n unsigned int v1;\n const char *v2;\n unsigned int v3;\n const char *i;\n unsigned int v5;\n const char *v6;\n long long v7;\n unsigned int v8;\n unsigned int v9;\n regex_t v11;\n regmatch_t pmatch;\n char pattern[5];\n unsigned long long v14;\n v14 = __readfsqword(40u);\n strcpy(pattern, \"\\\\.0+\");\n v1 = strlen(a1) + 1;\n v2 = (const char *)malloc(v1);\n regcomp(&v11, pattern, 1);\n __strcpy_chk(v2, a1, v1);\n v3 = v1;\n for (i = v2; !regexec(&v11, i, 1uLL, &pmatch, 0);\n __memmove_chk(i, v6, v5 - pmatch.rm_eo + 1, v3)) {\n v5 = strlen(i);\n v6 = &i[pmatch.rm_eo];\n v7 = pmatch.rm_so + 1LL;\n v8 = v3;\n if (v1 >= v3) v8 = v1;\n v9 = v7 + v8 - v3;\n if (v9 < v8) v9 = v8;\n v3 = v9 + v3 - (v7 + v8);\n i += v7;\n }\n regfree(&v11);\n return v2;\n}" + }, + { + "index": 593, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* ip) {\n regex_t regex;\n regmatch_t matches[1];\n char pattern[] = \"\\\\.0+\";\n char* result = (char*)malloc(strlen(ip) + 1);\n char* current_location;\n regcomp(®ex, pattern, REG_EXTENDED);\n strcpy(result, ip);\n current_location = result;\n while (regexec(®ex, current_location, 1, matches, 0) == 0) {\n size_t len = strlen(current_location);\n size_t start = matches[0].rm_so;\n size_t end = matches[0].rm_eo;\n memmove(current_location + start + 1, current_location + end,\n len - end + 1);\n current_location += start + 1;\n }\n regfree(®ex);\n return result;\n}", + "test": "int main() {\n\n char* test1 = func0(\"216.08.094.196\");\n\n assert(strcmp(test1, \"216.8.94.196\") == 0);\n\n free(test1);\n\n\n\n char* test2 = func0(\"12.01.024\");\n\n assert(strcmp(test2, \"12.1.24\") == 0);\n\n free(test2);\n\n \n\n char* test3 = func0(\"216.08.094.0196\");\n\n assert(strcmp(test3, \"216.8.94.196\") == 0);\n\n free(test3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\nmov %rdi,%r12\npush %rbp\npush %rbx\nsub $0x68,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x58(%rsp)\nxor %eax,%eax\nmovl $0x2b302e5c,0x53(%rsp)\nmov %rsp,%rbp\nmovb $0x0,0x57(%rsp)\ncallq 1110 \nlea 0x1(%rax),%rdi\ncallq 1150 \nlea 0x53(%rsp),%rsi\nmov $0x1,%edx\nmov %rbp,%rdi\nmov %rax,%r13\ncallq 1140 \nmov %r12,%rsi\nmov %r13,%rdi\nmov %r13,%rbx\ncallq 10f0 \nlea 0x48(%rsp),%r12\njmp 140a \nnopl 0x0(%rax)\nmov %rbx,%rdi\ncallq 1110 \nmovslq 0x4c(%rsp),%rdx\nmovslq 0x48(%rsp),%rcx\nlea (%rbx,%rdx,1),%rsi\nsub %rdx,%rax\nlea 0x1(%rbx,%rcx,1),%rbx\nlea 0x1(%rax),%rdx\nmov %rbx,%rdi\ncallq 1170 \nxor %r8d,%r8d\nmov %r12,%rcx\nmov $0x1,%edx\nmov %rbx,%rsi\nmov %rbp,%rdi\ncallq 1160 \ntest %eax,%eax\nje 13e0 \nmov %rbp,%rdi\ncallq 1100 \nmov 0x58(%rsp),%rax\nxor %fs:0x28,%rax\njne 144a \nadd $0x68,%rsp\nmov %r13,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\ncallq 1120 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 68h\nmov rax, fs:28h\nmov [rsp+98h+var_40], rax\nxor eax, eax\nmov [rsp+98h+var_41], 0\nmov r13, rsp\nlea r14, [rsp+98h+pmatch]\nmov dword ptr [rsp+98h+pattern], 2B302E5Ch\ncall _strlen\nlea r12, [rax+1]\nmov rdi, r12; size\ncall _malloc\nlea rsi, [rsp+98h+pattern]; pattern\nmov edx, 1; cflags\nmov rdi, r13; preg\nmov r15, rax\ncall _regcomp\nmov rsi, rbx\nmov rdx, r12\nmov rdi, r15\ncall ___strcpy_chk\nmov rbx, r12\nmov rbp, r15\njmp short loc_1457\nloc_1400:\nmov rdi, rbp; s\ncall _strlen\nmov rdi, rbx\nmovsxd r8, [rsp+98h+pmatch.rm_eo]\nmov rcx, rax\nmovsxd rax, [rsp+98h+pmatch.rm_so]\nlea rsi, [rbp+r8+0]\nadd rax, 1\ncmp r12, rbx\ncmovnb rdi, r12\nlea r9, [rax+rdi]\nmov rdx, r9\nsub rdx, rbx\ncmp rdx, rdi\ncmovb rdx, rdi\nadd rbp, rax\nsub rbx, r9\nmov rax, rcx\nsub rax, r8\nmov rdi, rbp\nadd rbx, rdx\nlea rdx, [rax+1]\nmov rcx, rbx\ncall ___memmove_chk\nloc_1457:\nxor r8d, r8d; eflags\nmov rcx, r14; pmatch\nmov edx, 1; nmatch\nmov rsi, rbp; string\nmov rdi, r13; preg\ncall _regexec\ntest eax, eax\njz short loc_1400\nmov rdi, r13; preg\ncall _regfree\nmov rax, [rsp+98h+var_40]\nsub rax, fs:28h\njnz short loc_149B\nadd rsp, 68h\nmov rax, r15\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_149B:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n size_t v1; // r12\n const char *v2; // r15\n size_t v3; // rbx\n const char *i; // rbp\n size_t v5; // rdi\n size_t v6; // rcx\n const char *v7; // rsi\n __int64 v8; // rax\n size_t v9; // rdx\n regex_t v11; // [rsp+0h] [rbp-98h] BYREF\n regmatch_t pmatch; // [rsp+48h] [rbp-50h] BYREF\n char pattern[5]; // [rsp+53h] [rbp-45h] BYREF\n unsigned __int64 v14; // [rsp+58h] [rbp-40h]\n\n v14 = __readfsqword(0x28u);\n strcpy(pattern, \"\\\\.0+\");\n v1 = strlen(a1) + 1;\n v2 = (const char *)malloc(v1);\n regcomp(&v11, pattern, 1);\n __strcpy_chk(v2, a1, v1);\n v3 = v1;\n for ( i = v2; !regexec(&v11, i, 1uLL, &pmatch, 0); __memmove_chk(i, v7, v6 - pmatch.rm_eo + 1, v3) )\n {\n v5 = v3;\n v6 = strlen(i);\n v7 = &i[pmatch.rm_eo];\n v8 = pmatch.rm_so + 1LL;\n if ( v1 >= v3 )\n v5 = v1;\n v9 = v8 + v5 - v3;\n if ( v9 < v5 )\n v9 = v5;\n i += v8;\n v3 = v9 + v3 - (v8 + v5);\n }\n regfree(&v11);\n return v2;\n}", + "ida_strip_asm": "sub_1380:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 68h\nmov rax, fs:28h\nmov [rsp+98h+var_40], rax\nxor eax, eax\nmov [rsp+98h+var_41], 0\nmov r13, rsp\nlea r14, [rsp+98h+pmatch]\nmov dword ptr [rsp+98h+pattern], 2B302E5Ch\ncall _strlen\nlea r12, [rax+1]\nmov rdi, r12; size\ncall _malloc\nlea rsi, [rsp+98h+pattern]; pattern\nmov edx, 1; cflags\nmov rdi, r13; preg\nmov r15, rax\ncall _regcomp\nmov rsi, rbx\nmov rdx, r12\nmov rdi, r15\ncall ___strcpy_chk\nmov rbx, r12\nmov rbp, r15\njmp short loc_1457\nloc_1400:\nmov rdi, rbp; s\ncall _strlen\nmov rdi, rbx\nmovsxd r8, [rsp+98h+pmatch.rm_eo]\nmov rcx, rax\nmovsxd rax, [rsp+98h+pmatch.rm_so]\nlea rsi, [rbp+r8+0]\nadd rax, 1\ncmp r12, rbx\ncmovnb rdi, r12\nlea r9, [rax+rdi]\nmov rdx, r9\nsub rdx, rbx\ncmp rdx, rdi\ncmovb rdx, rdi\nadd rbp, rax\nsub rbx, r9\nmov rax, rcx\nsub rax, r8\nmov rdi, rbp\nadd rbx, rdx\nlea rdx, [rax+1]\nmov rcx, rbx\ncall ___memmove_chk\nloc_1457:\nxor r8d, r8d; eflags\nmov rcx, r14; pmatch\nmov edx, 1; nmatch\nmov rsi, rbp; string\nmov rdi, r13; preg\ncall _regexec\ntest eax, eax\njz short loc_1400\nmov rdi, r13; preg\ncall _regfree\nmov rax, [rsp+98h+var_40]\nsub rax, fs:28h\njnz short loc_149B\nadd rsp, 68h\nmov rax, r15\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_149B:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_1380(const char *a1)\n{\n size_t v1; // r12\n const char *v2; // r15\n size_t v3; // rbx\n const char *i; // rbp\n size_t v5; // rdi\n size_t v6; // rcx\n const char *v7; // rsi\n __int64 v8; // rax\n size_t v9; // rdx\n regex_t v11; // [rsp+0h] [rbp-98h] BYREF\n regmatch_t pmatch; // [rsp+48h] [rbp-50h] BYREF\n char pattern[5]; // [rsp+53h] [rbp-45h] BYREF\n unsigned __int64 v14; // [rsp+58h] [rbp-40h]\n\n v14 = __readfsqword(0x28u);\n strcpy(pattern, \"\\\\.0+\");\n v1 = strlen(a1) + 1;\n v2 = (const char *)malloc(v1);\n regcomp(&v11, pattern, 1);\n __strcpy_chk(v2, a1, v1);\n v3 = v1;\n for ( i = v2; !regexec(&v11, i, 1uLL, &pmatch, 0); __memmove_chk(i, v7, v6 - pmatch.rm_eo + 1, v3) )\n {\n v5 = v3;\n v6 = strlen(i);\n v7 = &i[pmatch.rm_eo];\n v8 = pmatch.rm_so + 1LL;\n if ( v1 >= v3 )\n v5 = v1;\n v9 = v8 + v5 - v3;\n if ( v9 < v5 )\n v9 = v5;\n i += v8;\n v3 = v9 + v3 - (v8 + v5);\n }\n regfree(&v11);\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1380(const char *a1) {\n unsigned int v1;\n const char *v2;\n unsigned int v3;\n const char *i;\n unsigned int v5;\n unsigned int v6;\n const char *v7;\n long long v8;\n unsigned int v9;\n regex_t v11;\n regmatch_t pmatch;\n char pattern[5];\n unsigned long long v14;\n v14 = __readfsqword(40u);\n strcpy(pattern, \"\\\\.0+\");\n v1 = strlen(a1) + 1;\n v2 = (const char *)malloc(v1);\n regcomp(&v11, pattern, 1);\n __strcpy_chk(v2, a1, v1);\n v3 = v1;\n for (i = v2; !regexec(&v11, i, 1uLL, &pmatch, 0);\n __memmove_chk(i, v7, v6 - pmatch.rm_eo + 1, v3)) {\n v5 = v3;\n v6 = strlen(i);\n v7 = &i[pmatch.rm_eo];\n v8 = pmatch.rm_so + 1LL;\n if (v1 >= v3) v5 = v1;\n v9 = v8 + v5 - v3;\n if (v9 < v5) v9 = v5;\n i += v8;\n v3 = v9 + v3 - (v8 + v5);\n }\n regfree(&v11);\n return v2;\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n unsigned int v1;\n const char *v2;\n unsigned int v3;\n const char *i;\n unsigned int v5;\n unsigned int v6;\n const char *v7;\n long long v8;\n unsigned int v9;\n regex_t v11;\n regmatch_t pmatch;\n char pattern[5];\n unsigned long long v14;\n v14 = __readfsqword(40u);\n strcpy(pattern, \"\\\\.0+\");\n v1 = strlen(a1) + 1;\n v2 = (const char *)malloc(v1);\n regcomp(&v11, pattern, 1);\n __strcpy_chk(v2, a1, v1);\n v3 = v1;\n for (i = v2; !regexec(&v11, i, 1uLL, &pmatch, 0);\n __memmove_chk(i, v7, v6 - pmatch.rm_eo + 1, v3)) {\n v5 = v3;\n v6 = strlen(i);\n v7 = &i[pmatch.rm_eo];\n v8 = pmatch.rm_so + 1LL;\n if (v1 >= v3) v5 = v1;\n v9 = v8 + v5 - v3;\n if (v9 < v5) v9 = v5;\n i += v8;\n v3 = v9 + v3 - (v8 + v5);\n }\n regfree(&v11);\n return v2;\n}" + }, + { + "index": 593, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* ip) {\n regex_t regex;\n regmatch_t matches[1];\n char pattern[] = \"\\\\.0+\";\n char* result = (char*)malloc(strlen(ip) + 1);\n char* current_location;\n regcomp(®ex, pattern, REG_EXTENDED);\n strcpy(result, ip);\n current_location = result;\n while (regexec(®ex, current_location, 1, matches, 0) == 0) {\n size_t len = strlen(current_location);\n size_t start = matches[0].rm_so;\n size_t end = matches[0].rm_eo;\n memmove(current_location + start + 1, current_location + end,\n len - end + 1);\n current_location += start + 1;\n }\n regfree(®ex);\n return result;\n}", + "test": "int main() {\n\n char* test1 = func0(\"216.08.094.196\");\n\n assert(strcmp(test1, \"216.8.94.196\") == 0);\n\n free(test1);\n\n\n\n char* test2 = func0(\"12.01.024\");\n\n assert(strcmp(test2, \"12.1.24\") == 0);\n\n free(test2);\n\n \n\n char* test3 = func0(\"216.08.094.0196\");\n\n assert(strcmp(test3, \"216.8.94.196\") == 0);\n\n free(test3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\nmov %rdi,%r12\npush %rbp\npush %rbx\nsub $0x68,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x58(%rsp)\nxor %eax,%eax\nmovl $0x2b302e5c,0x53(%rsp)\nmov %rsp,%rbp\nmovb $0x0,0x57(%rsp)\ncallq 1110 \nlea 0x1(%rax),%rdi\ncallq 1150 \nlea 0x53(%rsp),%rsi\nmov $0x1,%edx\nmov %rbp,%rdi\nmov %rax,%r13\ncallq 1140 \nmov %r12,%rsi\nmov %r13,%rdi\nmov %r13,%rbx\ncallq 10f0 \nlea 0x48(%rsp),%r12\njmp 140a \nnopl 0x0(%rax)\nmov %rbx,%rdi\ncallq 1110 \nmovslq 0x4c(%rsp),%rdx\nmovslq 0x48(%rsp),%rcx\nlea (%rbx,%rdx,1),%rsi\nsub %rdx,%rax\nlea 0x1(%rbx,%rcx,1),%rbx\nlea 0x1(%rax),%rdx\nmov %rbx,%rdi\ncallq 1170 \nxor %r8d,%r8d\nmov %r12,%rcx\nmov $0x1,%edx\nmov %rbx,%rsi\nmov %rbp,%rdi\ncallq 1160 \ntest %eax,%eax\nje 13e0 \nmov %rbp,%rdi\ncallq 1100 \nmov 0x58(%rsp),%rax\nxor %fs:0x28,%rax\njne 144a \nadd $0x68,%rsp\nmov %r13,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\ncallq 1120 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 68h\nmov rax, fs:28h\nmov [rsp+98h+var_40], rax\nxor eax, eax\nmov [rsp+98h+var_41], 0\nmov r13, rsp\nlea r14, [rsp+98h+pmatch]\nmov dword ptr [rsp+98h+pattern], 2B302E5Ch\ncall _strlen\nlea r12, [rax+1]\nmov rdi, r12; size\ncall _malloc\nlea rsi, [rsp+98h+pattern]; pattern\nmov edx, 1; cflags\nmov rdi, r13; preg\nmov r15, rax\ncall _regcomp\nmov rsi, rbx\nmov rdx, r12\nmov rdi, r15\ncall ___strcpy_chk\nmov rbx, r12\nmov rbp, r15\njmp short loc_1457\nloc_1400:\nmov rdi, rbp; s\ncall _strlen\nmov rdi, rbx\nmovsxd r8, [rsp+98h+pmatch.rm_eo]\nmov rcx, rax\nmovsxd rax, [rsp+98h+pmatch.rm_so]\nlea rsi, [rbp+r8+0]\nadd rax, 1\ncmp r12, rbx\ncmovnb rdi, r12\nlea r9, [rax+rdi]\nmov rdx, r9\nsub rdx, rbx\ncmp rdx, rdi\ncmovb rdx, rdi\nadd rbp, rax\nsub rbx, r9\nmov rax, rcx\nsub rax, r8\nmov rdi, rbp\nadd rbx, rdx\nlea rdx, [rax+1]\nmov rcx, rbx\ncall ___memmove_chk\nloc_1457:\nxor r8d, r8d; eflags\nmov rcx, r14; pmatch\nmov edx, 1; nmatch\nmov rsi, rbp; string\nmov rdi, r13; preg\ncall _regexec\ntest eax, eax\njz short loc_1400\nmov rdi, r13; preg\ncall _regfree\nmov rax, [rsp+98h+var_40]\nsub rax, fs:28h\njnz short loc_149B\nadd rsp, 68h\nmov rax, r15\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_149B:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n size_t v1; // r12\n const char *v2; // r15\n size_t v3; // rbx\n const char *i; // rbp\n size_t v5; // rdi\n size_t v6; // rcx\n const char *v7; // rsi\n __int64 v8; // rax\n size_t v9; // rdx\n regex_t v11; // [rsp+0h] [rbp-98h] BYREF\n regmatch_t pmatch; // [rsp+48h] [rbp-50h] BYREF\n char pattern[5]; // [rsp+53h] [rbp-45h] BYREF\n unsigned __int64 v14; // [rsp+58h] [rbp-40h]\n\n v14 = __readfsqword(0x28u);\n strcpy(pattern, \"\\\\.0+\");\n v1 = strlen(a1) + 1;\n v2 = (const char *)malloc(v1);\n regcomp(&v11, pattern, 1);\n __strcpy_chk(v2, a1, v1);\n v3 = v1;\n for ( i = v2; !regexec(&v11, i, 1uLL, &pmatch, 0); __memmove_chk(i, v7, v6 - pmatch.rm_eo + 1, v3) )\n {\n v5 = v3;\n v6 = strlen(i);\n v7 = &i[pmatch.rm_eo];\n v8 = pmatch.rm_so + 1LL;\n if ( v1 >= v3 )\n v5 = v1;\n v9 = v8 + v5 - v3;\n if ( v9 < v5 )\n v9 = v5;\n i += v8;\n v3 = v9 + v3 - (v8 + v5);\n }\n regfree(&v11);\n return v2;\n}", + "ida_strip_asm": "sub_1380:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 68h\nmov rax, fs:28h\nmov [rsp+98h+var_40], rax\nxor eax, eax\nmov [rsp+98h+var_41], 0\nmov r13, rsp\nlea r14, [rsp+98h+pmatch]\nmov dword ptr [rsp+98h+pattern], 2B302E5Ch\ncall _strlen\nlea r12, [rax+1]\nmov rdi, r12; size\ncall _malloc\nlea rsi, [rsp+98h+pattern]; pattern\nmov edx, 1; cflags\nmov rdi, r13; preg\nmov r15, rax\ncall _regcomp\nmov rsi, rbx\nmov rdx, r12\nmov rdi, r15\ncall ___strcpy_chk\nmov rbx, r12\nmov rbp, r15\njmp short loc_1457\nloc_1400:\nmov rdi, rbp; s\ncall _strlen\nmov rdi, rbx\nmovsxd r8, [rsp+98h+pmatch.rm_eo]\nmov rcx, rax\nmovsxd rax, [rsp+98h+pmatch.rm_so]\nlea rsi, [rbp+r8+0]\nadd rax, 1\ncmp r12, rbx\ncmovnb rdi, r12\nlea r9, [rax+rdi]\nmov rdx, r9\nsub rdx, rbx\ncmp rdx, rdi\ncmovb rdx, rdi\nadd rbp, rax\nsub rbx, r9\nmov rax, rcx\nsub rax, r8\nmov rdi, rbp\nadd rbx, rdx\nlea rdx, [rax+1]\nmov rcx, rbx\ncall ___memmove_chk\nloc_1457:\nxor r8d, r8d; eflags\nmov rcx, r14; pmatch\nmov edx, 1; nmatch\nmov rsi, rbp; string\nmov rdi, r13; preg\ncall _regexec\ntest eax, eax\njz short loc_1400\nmov rdi, r13; preg\ncall _regfree\nmov rax, [rsp+98h+var_40]\nsub rax, fs:28h\njnz short loc_149B\nadd rsp, 68h\nmov rax, r15\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_149B:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_1380(const char *a1)\n{\n size_t v1; // r12\n const char *v2; // r15\n size_t v3; // rbx\n const char *i; // rbp\n size_t v5; // rdi\n size_t v6; // rcx\n const char *v7; // rsi\n __int64 v8; // rax\n size_t v9; // rdx\n regex_t v11; // [rsp+0h] [rbp-98h] BYREF\n regmatch_t pmatch; // [rsp+48h] [rbp-50h] BYREF\n char pattern[5]; // [rsp+53h] [rbp-45h] BYREF\n unsigned __int64 v14; // [rsp+58h] [rbp-40h]\n\n v14 = __readfsqword(0x28u);\n strcpy(pattern, \"\\\\.0+\");\n v1 = strlen(a1) + 1;\n v2 = (const char *)malloc(v1);\n regcomp(&v11, pattern, 1);\n __strcpy_chk(v2, a1, v1);\n v3 = v1;\n for ( i = v2; !regexec(&v11, i, 1uLL, &pmatch, 0); __memmove_chk(i, v7, v6 - pmatch.rm_eo + 1, v3) )\n {\n v5 = v3;\n v6 = strlen(i);\n v7 = &i[pmatch.rm_eo];\n v8 = pmatch.rm_so + 1LL;\n if ( v1 >= v3 )\n v5 = v1;\n v9 = v8 + v5 - v3;\n if ( v9 < v5 )\n v9 = v5;\n i += v8;\n v3 = v9 + v3 - (v8 + v5);\n }\n regfree(&v11);\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1380(const char *a1) {\n unsigned int v1;\n const char *v2;\n unsigned int v3;\n const char *i;\n unsigned int v5;\n unsigned int v6;\n const char *v7;\n long long v8;\n unsigned int v9;\n regex_t v11;\n regmatch_t pmatch;\n char pattern[5];\n unsigned long long v14;\n v14 = __readfsqword(40u);\n strcpy(pattern, \"\\\\.0+\");\n v1 = strlen(a1) + 1;\n v2 = (const char *)malloc(v1);\n regcomp(&v11, pattern, 1);\n __strcpy_chk(v2, a1, v1);\n v3 = v1;\n for (i = v2; !regexec(&v11, i, 1uLL, &pmatch, 0);\n __memmove_chk(i, v7, v6 - pmatch.rm_eo + 1, v3)) {\n v5 = v3;\n v6 = strlen(i);\n v7 = &i[pmatch.rm_eo];\n v8 = pmatch.rm_so + 1LL;\n if (v1 >= v3) v5 = v1;\n v9 = v8 + v5 - v3;\n if (v9 < v5) v9 = v5;\n i += v8;\n v3 = v9 + v3 - (v8 + v5);\n }\n regfree(&v11);\n return v2;\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n unsigned int v1;\n const char *v2;\n unsigned int v3;\n const char *i;\n unsigned int v5;\n unsigned int v6;\n const char *v7;\n long long v8;\n unsigned int v9;\n regex_t v11;\n regmatch_t pmatch;\n char pattern[5];\n unsigned long long v14;\n v14 = __readfsqword(40u);\n strcpy(pattern, \"\\\\.0+\");\n v1 = strlen(a1) + 1;\n v2 = (const char *)malloc(v1);\n regcomp(&v11, pattern, 1);\n __strcpy_chk(v2, a1, v1);\n v3 = v1;\n for (i = v2; !regexec(&v11, i, 1uLL, &pmatch, 0);\n __memmove_chk(i, v7, v6 - pmatch.rm_eo + 1, v3)) {\n v5 = v3;\n v6 = strlen(i);\n v7 = &i[pmatch.rm_eo];\n v8 = pmatch.rm_so + 1LL;\n if (v1 >= v3) v5 = v1;\n v9 = v8 + v5 - v3;\n if (v9 < v5) v9 = v5;\n i += v8;\n v3 = v9 + v3 - (v8 + v5);\n }\n regfree(&v11);\n return v2;\n}" + }, + { + "index": 594, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int list1[], int size) {\n int first_even = -1;\n int first_odd = -1;\n for (int i = 0; i < size; i++) {\n if (list1[i] % 2 == 0) {\n first_even = list1[i];\n break;\n }\n }\n for (int i = 0; i < size; i++) {\n if (list1[i] % 2 != 0) {\n first_odd = list1[i];\n break;\n }\n }\n return (first_even - first_odd);\n}", + "test": "int main() {\n\n int list1[] = {1,3,5,7,4,1,6,8};\n\n int list2[] = {1,2,3,4,5,6,7,8,9,10};\n\n int list3[] = {1,5,7,9,10};\n\n\n\n assert(func0(list1, 8) == 3);\n\n assert(func0(list2, 10) == 1);\n\n assert(func0(list3, 5) == 9);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0xffffffff,-0x10(%rbp)\nmovl $0xffffffff,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11cb \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nand $0x1,%eax\ntest %eax,%eax\njne 11c7 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x10(%rbp)\njmp 11d3 \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 118f \nmovl $0x0,-0x4(%rbp)\njmp 1218 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nand $0x1,%eax\ntest %eax,%eax\nje 1214 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0xc(%rbp)\njmp 1220 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11dc \nmov -0x10(%rbp),%eax\nsub -0xc(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_10], 0FFFFFFFFh\nmov [rbp+var_C], 0FFFFFFFFh\nmov [rbp+var_8], 0\njmp short loc_11CB\nloc_118F:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njnz short loc_11C7\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_10], eax\njmp short loc_11D3\nloc_11C7:\nadd [rbp+var_8], 1\nloc_11CB:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_118F\nloc_11D3:\nmov [rbp+var_4], 0\njmp short loc_1218\nloc_11DC:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njz short loc_1214\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\njmp short loc_1220\nloc_1214:\nadd [rbp+var_4], 1\nloc_1218:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11DC\nloc_1220:\nmov eax, [rbp+var_10]\nsub eax, [rbp+var_C]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int v3; // [rsp+Ch] [rbp-10h]\n int v4; // [rsp+10h] [rbp-Ch]\n int i; // [rsp+14h] [rbp-8h]\n int j; // [rsp+18h] [rbp-4h]\n\n v3 = -1;\n v4 = -1;\n for ( i = 0; i < a2; ++i )\n {\n if ( (*(_DWORD *)(4LL * i + a1) & 1) == 0 )\n {\n v3 = *(_DWORD *)(4LL * i + a1);\n break;\n }\n }\n for ( j = 0; j < a2; ++j )\n {\n if ( (*(_DWORD *)(4LL * j + a1) & 1) != 0 )\n {\n v4 = *(_DWORD *)(4LL * j + a1);\n return (unsigned int)(v3 - v4);\n }\n }\n return (unsigned int)(v3 - v4);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_10], 0FFFFFFFFh\nmov [rbp+var_C], 0FFFFFFFFh\nmov [rbp+var_8], 0\njmp short loc_11CB\nloc_118F:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njnz short loc_11C7\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_10], eax\njmp short loc_11D3\nloc_11C7:\nadd [rbp+var_8], 1\nloc_11CB:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_118F\nloc_11D3:\nmov [rbp+var_4], 0\njmp short loc_1218\nloc_11DC:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njz short loc_1214\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\njmp short loc_1220\nloc_1214:\nadd [rbp+var_4], 1\nloc_1218:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11DC\nloc_1220:\nmov eax, [rbp+var_10]\nsub eax, [rbp+var_C]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int v3; // [rsp+Ch] [rbp-10h]\n int v4; // [rsp+10h] [rbp-Ch]\n int i; // [rsp+14h] [rbp-8h]\n int j; // [rsp+18h] [rbp-4h]\n\n v3 = -1;\n v4 = -1;\n for ( i = 0; i < a2; ++i )\n {\n if ( (*(_DWORD *)(4LL * i + a1) & 1) == 0 )\n {\n v3 = *(_DWORD *)(4LL * i + a1);\n break;\n }\n }\n for ( j = 0; j < a2; ++j )\n {\n if ( (*(_DWORD *)(4LL * j + a1) & 1) != 0 )\n {\n v4 = *(_DWORD *)(4LL * j + a1);\n return (unsigned int)(v3 - v4);\n }\n }\n return (unsigned int)(v3 - v4);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int v3;\n int v4;\n int i;\n int j;\n v3 = -1;\n v4 = -1;\n for (i = 0; i < a2; ++i) {\n if ((*(uint32_t *)(4LL * i + a1) & 1) == 0) {\n v3 = *(uint32_t *)(4LL * i + a1);\n break;\n }\n }\n for (j = 0; j < a2; ++j) {\n if ((*(uint32_t *)(4LL * j + a1) & 1) != 0) {\n v4 = *(uint32_t *)(4LL * j + a1);\n return (unsigned int)(v3 - v4);\n }\n }\n return (unsigned int)(v3 - v4);\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int v3;\n int v4;\n int i;\n int j;\n v3 = -1;\n v4 = -1;\n for (i = 0; i < a2; ++i) {\n if ((*(uint32_t *)(4LL * i + a1) & 1) == 0) {\n v3 = *(uint32_t *)(4LL * i + a1);\n break;\n }\n }\n for (j = 0; j < a2; ++j) {\n if ((*(uint32_t *)(4LL * j + a1) & 1) != 0) {\n v4 = *(uint32_t *)(4LL * j + a1);\n return (unsigned int)(v3 - v4);\n }\n }\n return (unsigned int)(v3 - v4);\n}" + }, + { + "index": 594, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int list1[], int size) {\n int first_even = -1;\n int first_odd = -1;\n for (int i = 0; i < size; i++) {\n if (list1[i] % 2 == 0) {\n first_even = list1[i];\n break;\n }\n }\n for (int i = 0; i < size; i++) {\n if (list1[i] % 2 != 0) {\n first_odd = list1[i];\n break;\n }\n }\n return (first_even - first_odd);\n}", + "test": "int main() {\n\n int list1[] = {1,3,5,7,4,1,6,8};\n\n int list2[] = {1,2,3,4,5,6,7,8,9,10};\n\n int list3[] = {1,5,7,9,10};\n\n\n\n assert(func0(list1, 8) == 3);\n\n assert(func0(list2, 10) == 1);\n\n assert(func0(list3, 5) == 9);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11a8 \nmov %rdi,%rdx\nlea -0x1(%rsi),%eax\nlea 0x4(%rdi,%rax,4),%rsi\nmov (%rdi),%eax\ntest $0x1,%al\nje 1190 \nadd $0x4,%rdi\ncmp %rsi,%rdi\njne 117c \nmov $0xffffffff,%eax\nmov (%rdx),%ecx\ntest $0x1,%cl\njne 11a5 \nadd $0x4,%rdx\ncmp %rsi,%rdx\njne 1190 \nmov $0xffffffff,%ecx\nsub %ecx,%eax\nretq\nmov $0xffffffff,%eax\nmov $0xffffffff,%ecx\njmp 11a5 \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11A7\nmov rdx, rdi\nmovsxd rsi, esi\nlea rsi, [rdi+rsi*4]\nloc_117B:\nmov eax, [rdi]\ntest al, 1\njz short loc_118F\nadd rdi, 4\ncmp rdi, rsi\njnz short loc_117B\nmov eax, 0FFFFFFFFh\nloc_118F:\nmov ecx, [rdx]\ntest cl, 1\njnz short loc_11A4\nadd rdx, 4\ncmp rdx, rsi\njnz short loc_118F\nmov ecx, 0FFFFFFFFh\nloc_11A4:\nsub eax, ecx\nretn\nloc_11A7:\nmov eax, 0FFFFFFFFh\nmov ecx, 0FFFFFFFFh\njmp short loc_11A4", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int *v2; // rdx\n int *v3; // rsi\n int v4; // eax\n int v5; // ecx\n\n if ( a2 <= 0 )\n {\n v4 = -1;\n v5 = -1;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n do\n {\n v4 = *a1;\n if ( (*a1 & 1) == 0 )\n goto LABEL_6;\n ++a1;\n }\n while ( a1 != v3 );\n v4 = -1;\nLABEL_6:\n while ( 1 )\n {\n v5 = *v2;\n if ( (*v2 & 1) != 0 )\n break;\n if ( ++v2 == v3 )\n {\n v5 = -1;\n return (unsigned int)(v4 - v5);\n }\n }\n }\n return (unsigned int)(v4 - v5);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11A7\nmov rdx, rdi\nmovsxd rsi, esi\nlea rsi, [rdi+rsi*4]\nloc_117B:\nmov eax, [rdi]\ntest al, 1\njz short loc_118F\nadd rdi, 4\ncmp rdi, rsi\njnz short loc_117B\nmov eax, 0FFFFFFFFh\nloc_118F:\nmov ecx, [rdx]\ntest cl, 1\njnz short loc_11A4\nadd rdx, 4\ncmp rdx, rsi\njnz short loc_118F\nmov ecx, 0FFFFFFFFh\nloc_11A4:\nsub eax, ecx\nretn\nloc_11A7:\nmov eax, 0FFFFFFFFh\nmov ecx, 0FFFFFFFFh\njmp short loc_11A4", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int *a1, int a2)\n{\n int *v2; // rdx\n int *v3; // rsi\n int v4; // eax\n int v5; // ecx\n\n if ( a2 <= 0 )\n {\n v4 = -1;\n v5 = -1;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n do\n {\n v4 = *a1;\n if ( (*a1 & 1) == 0 )\n goto LABEL_6;\n ++a1;\n }\n while ( a1 != v3 );\n v4 = -1;\nLABEL_6:\n while ( 1 )\n {\n v5 = *v2;\n if ( (*v2 & 1) != 0 )\n break;\n if ( ++v2 == v3 )\n {\n v5 = -1;\n return (unsigned int)(v4 - v5);\n }\n }\n }\n return (unsigned int)(v4 - v5);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int *a1, int a2) {\n int *v2;\n int *v3;\n int v4;\n int v5;\n if (a2 <= 0) {\n v4 = -1;\n v5 = -1;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n do {\n v4 = *a1;\n if ((*a1 & 1) == 0) goto LABEL_6;\n ++a1;\n } while (a1 != v3);\n v4 = -1;\n LABEL_6:\n while (1) {\n v5 = *v2;\n if ((*v2 & 1) != 0) break;\n if (++v2 == v3) {\n v5 = -1;\n return (unsigned int)(v4 - v5);\n }\n }\n }\n return (unsigned int)(v4 - v5);\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int *v2;\n int *v3;\n int v4;\n int v5;\n if (a2 <= 0) {\n v4 = -1;\n v5 = -1;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n do {\n v4 = *a1;\n if ((*a1 & 1) == 0) goto LABEL_6;\n ++a1;\n } while (a1 != v3);\n v4 = -1;\n LABEL_6:\n while (1) {\n v5 = *v2;\n if ((*v2 & 1) != 0) break;\n if (++v2 == v3) {\n v5 = -1;\n return (unsigned int)(v4 - v5);\n }\n }\n }\n return (unsigned int)(v4 - v5);\n}" + }, + { + "index": 594, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int list1[], int size) {\n int first_even = -1;\n int first_odd = -1;\n for (int i = 0; i < size; i++) {\n if (list1[i] % 2 == 0) {\n first_even = list1[i];\n break;\n }\n }\n for (int i = 0; i < size; i++) {\n if (list1[i] % 2 != 0) {\n first_odd = list1[i];\n break;\n }\n }\n return (first_even - first_odd);\n}", + "test": "int main() {\n\n int list1[] = {1,3,5,7,4,1,6,8};\n\n int list2[] = {1,2,3,4,5,6,7,8,9,10};\n\n int list3[] = {1,5,7,9,10};\n\n\n\n assert(func0(list1, 8) == 3);\n\n assert(func0(list2, 10) == 1);\n\n assert(func0(list3, 5) == 9);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1344 \nlea -0x1(%rsi),%eax\nmov %rdi,%rdx\nlea 0x4(%rdi,%rax,4),%rcx\njmp 1311 \nnopl (%rax)\nadd $0x4,%rdx\ncmp %rcx,%rdx\nje 1338 \nmov (%rdx),%eax\ntest $0x1,%al\njne 1308 \njmp 1329 \nnopl 0x0(%rax)\nadd $0x4,%rdi\ncmp %rcx,%rdi\nje 1340 \nmov (%rdi),%edx\ntest $0x1,%dl\nje 1320 \nsub %edx,%eax\nretq\nnopl 0x0(%rax,%rax,1)\nmov $0xffffffff,%eax\njmp 1329 \nadd $0x1,%eax\nretq\nxor %eax,%eax\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_12E4\nmovsxd rsi, esi\nmov rdx, rdi\nlea rcx, [rdi+rsi*4]\njmp short loc_12B1\nloc_12A8:\nadd rdx, 4\ncmp rdx, rcx\njz short loc_12D8\nloc_12B1:\nmov eax, [rdx]\ntest al, 1\njnz short loc_12A8\njmp short loc_12C9\nloc_12C0:\nadd rdi, 4\ncmp rdi, rcx\njz short loc_12E0\nloc_12C9:\nmov edx, [rdi]\ntest dl, 1\njz short loc_12C0\nsub eax, edx\nretn\nloc_12D8:\nmov eax, 0FFFFFFFFh\njmp short loc_12C9\nloc_12E0:\nadd eax, 1\nretn\nloc_12E4:\nxor eax, eax\nretn", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int *v2; // rdx\n int *v3; // rcx\n int v4; // eax\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = a1;\n v3 = &a1[a2];\n while ( 1 )\n {\n v4 = *v2;\n if ( (*v2 & 1) == 0 )\n break;\n if ( ++v2 == v3 )\n {\n v4 = -1;\n goto LABEL_7;\n }\n }\n do\n {\nLABEL_7:\n if ( (*a1 & 1) != 0 )\n return (unsigned int)(v4 - *a1);\n ++a1;\n }\n while ( a1 != v3 );\n return (unsigned int)(v4 + 1);\n}", + "ida_strip_asm": "sub_1290:\nendbr64\ntest esi, esi\njle short loc_12E4\nmovsxd rsi, esi\nmov rdx, rdi\nlea rcx, [rdi+rsi*4]\njmp short loc_12B1\nloc_12A8:\nadd rdx, 4\ncmp rdx, rcx\njz short loc_12D8\nloc_12B1:\nmov eax, [rdx]\ntest al, 1\njnz short loc_12A8\njmp short loc_12C9\nloc_12C0:\nadd rdi, 4\ncmp rdi, rcx\njz short loc_12E0\nloc_12C9:\nmov edx, [rdi]\ntest dl, 1\njz short loc_12C0\nsub eax, edx\nretn\nloc_12D8:\nmov eax, 0FFFFFFFFh\njmp short loc_12C9\nloc_12E0:\nadd eax, 1\nretn\nloc_12E4:\nxor eax, eax\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1290(int *a1, int a2)\n{\n int *v2; // rdx\n int *v3; // rcx\n int v4; // eax\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = a1;\n v3 = &a1[a2];\n while ( 1 )\n {\n v4 = *v2;\n if ( (*v2 & 1) == 0 )\n break;\n if ( ++v2 == v3 )\n {\n v4 = -1;\n goto LABEL_7;\n }\n }\n do\n {\nLABEL_7:\n if ( (*a1 & 1) != 0 )\n return (unsigned int)(v4 - *a1);\n ++a1;\n }\n while ( a1 != v3 );\n return (unsigned int)(v4 + 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1290(int *a1, int a2) {\n int *v2;\n int *v3;\n int v4;\n if (a2 <= 0) return 0LL;\n v2 = a1;\n v3 = &a1[a2];\n while (1) {\n v4 = *v2;\n if ((*v2 & 1) == 0) break;\n if (++v2 == v3) {\n v4 = -1;\n goto LABEL_7;\n }\n }\n do {\n LABEL_7:\n if ((*a1 & 1) != 0) return (unsigned int)(v4 - *a1);\n ++a1;\n } while (a1 != v3);\n return (unsigned int)(v4 + 1);\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int *v2;\n int *v3;\n int v4;\n if (a2 <= 0) return 0LL;\n v2 = a1;\n v3 = &a1[a2];\n while (1) {\n v4 = *v2;\n if ((*v2 & 1) == 0) break;\n if (++v2 == v3) {\n v4 = -1;\n goto LABEL_7;\n }\n }\n do {\n LABEL_7:\n if ((*a1 & 1) != 0) return (unsigned int)(v4 - *a1);\n ++a1;\n } while (a1 != v3);\n return (unsigned int)(v4 + 1);\n}" + }, + { + "index": 594, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int list1[], int size) {\n int first_even = -1;\n int first_odd = -1;\n for (int i = 0; i < size; i++) {\n if (list1[i] % 2 == 0) {\n first_even = list1[i];\n break;\n }\n }\n for (int i = 0; i < size; i++) {\n if (list1[i] % 2 != 0) {\n first_odd = list1[i];\n break;\n }\n }\n return (first_even - first_odd);\n}", + "test": "int main() {\n\n int list1[] = {1,3,5,7,4,1,6,8};\n\n int list2[] = {1,2,3,4,5,6,7,8,9,10};\n\n int list3[] = {1,5,7,9,10};\n\n\n\n assert(func0(list1, 8) == 3);\n\n assert(func0(list2, 10) == 1);\n\n assert(func0(list3, 5) == 9);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 12f4 \nlea -0x1(%rsi),%eax\nmov %rdi,%rdx\nlea 0x4(%rdi,%rax,4),%rcx\njmp 12c1 \nnopl (%rax)\nadd $0x4,%rdx\ncmp %rcx,%rdx\nje 12e8 \nmov (%rdx),%eax\ntest $0x1,%al\njne 12b8 \njmp 12d9 \nnopl 0x0(%rax)\nadd $0x4,%rdi\ncmp %rcx,%rdi\nje 12f0 \nmov (%rdi),%edx\ntest $0x1,%dl\nje 12d0 \nsub %edx,%eax\nretq\nnopl 0x0(%rax,%rax,1)\nmov $0xffffffff,%eax\njmp 12d9 \nadd $0x1,%eax\nretq\nxor %eax,%eax\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_12E4\nmovsxd rsi, esi\nmov rdx, rdi\nlea rcx, [rdi+rsi*4]\njmp short loc_12B1\nloc_12A8:\nadd rdx, 4\ncmp rdx, rcx\njz short loc_12D8\nloc_12B1:\nmov eax, [rdx]\ntest al, 1\njnz short loc_12A8\njmp short loc_12C9\nloc_12C0:\nadd rdi, 4\ncmp rdi, rcx\njz short loc_12E0\nloc_12C9:\nmov edx, [rdi]\ntest dl, 1\njz short loc_12C0\nsub eax, edx\nretn\nloc_12D8:\nmov eax, 0FFFFFFFFh\njmp short loc_12C9\nloc_12E0:\nadd eax, 1\nretn\nloc_12E4:\nxor eax, eax\nretn", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int *v2; // rdx\n int *v3; // rcx\n int v4; // eax\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = a1;\n v3 = &a1[a2];\n while ( 1 )\n {\n v4 = *v2;\n if ( (*v2 & 1) == 0 )\n break;\n if ( ++v2 == v3 )\n {\n v4 = -1;\n goto LABEL_7;\n }\n }\n do\n {\nLABEL_7:\n if ( (*a1 & 1) != 0 )\n return (unsigned int)(v4 - *a1);\n ++a1;\n }\n while ( a1 != v3 );\n return (unsigned int)(v4 + 1);\n}", + "ida_strip_asm": "sub_1290:\nendbr64\ntest esi, esi\njle short loc_12E4\nmovsxd rsi, esi\nmov rdx, rdi\nlea rcx, [rdi+rsi*4]\njmp short loc_12B1\nloc_12A8:\nadd rdx, 4\ncmp rdx, rcx\njz short loc_12D8\nloc_12B1:\nmov eax, [rdx]\ntest al, 1\njnz short loc_12A8\njmp short loc_12C9\nloc_12C0:\nadd rdi, 4\ncmp rdi, rcx\njz short loc_12E0\nloc_12C9:\nmov edx, [rdi]\ntest dl, 1\njz short loc_12C0\nsub eax, edx\nretn\nloc_12D8:\nmov eax, 0FFFFFFFFh\njmp short loc_12C9\nloc_12E0:\nadd eax, 1\nretn\nloc_12E4:\nxor eax, eax\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1290(int *a1, int a2)\n{\n int *v2; // rdx\n int *v3; // rcx\n int v4; // eax\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = a1;\n v3 = &a1[a2];\n while ( 1 )\n {\n v4 = *v2;\n if ( (*v2 & 1) == 0 )\n break;\n if ( ++v2 == v3 )\n {\n v4 = -1;\n goto LABEL_7;\n }\n }\n do\n {\nLABEL_7:\n if ( (*a1 & 1) != 0 )\n return (unsigned int)(v4 - *a1);\n ++a1;\n }\n while ( a1 != v3 );\n return (unsigned int)(v4 + 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1290(int *a1, int a2) {\n int *v2;\n int *v3;\n int v4;\n if (a2 <= 0) return 0LL;\n v2 = a1;\n v3 = &a1[a2];\n while (1) {\n v4 = *v2;\n if ((*v2 & 1) == 0) break;\n if (++v2 == v3) {\n v4 = -1;\n goto LABEL_7;\n }\n }\n do {\n LABEL_7:\n if ((*a1 & 1) != 0) return (unsigned int)(v4 - *a1);\n ++a1;\n } while (a1 != v3);\n return (unsigned int)(v4 + 1);\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int *v2;\n int *v3;\n int v4;\n if (a2 <= 0) return 0LL;\n v2 = a1;\n v3 = &a1[a2];\n while (1) {\n v4 = *v2;\n if ((*v2 & 1) == 0) break;\n if (++v2 == v3) {\n v4 = -1;\n goto LABEL_7;\n }\n }\n do {\n LABEL_7:\n if ((*a1 & 1) != 0) return (unsigned int)(v4 - *a1);\n ++a1;\n } while (a1 != v3);\n return (unsigned int)(v4 + 1);\n}" + }, + { + "index": 595, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *str1, const char *str2) {\n int count = 0;\n int len = strlen(str1);\n for (int i = 0; i < len; i++) {\n if (str1[i] != str2[i]) {\n count++;\n }\n }\n if (count % 2 == 0) {\n return count / 2;\n } else {\n return -1;\n }\n}", + "test": "int main() {\n\n assert(func0(\"1101\", \"1110\") == 1);\n\n assert(func0(\"111\", \"000\") == -1); // -1 is returned for \"Not Possible\"\n\n assert(func0(\"111\", \"110\") == -1); // -1 is returned for \"Not Possible\"\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmovl $0x0,-0xc(%rbp)\nmov -0x18(%rbp),%rax\nmov %rax,%rdi\ncallq 1060 \nmov %eax,-0x4(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11c8 \nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%edx\nmov -0x8(%rbp),%eax\nmovslq %eax,%rcx\nmov -0x20(%rbp),%rax\nadd %rcx,%rax\nmovzbl (%rax),%eax\ncmp %al,%dl\nje 11c4 \naddl $0x1,-0xc(%rbp)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x4(%rbp),%eax\njl 119c \nmov -0xc(%rbp),%eax\nand $0x1,%eax\ntest %eax,%eax\njne 11e8 \nmov -0xc(%rbp),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\njmp 11ed \nmov $0xffffffff,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_C], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_8], 0\njmp short loc_11C8\nloc_119C:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_8]\nmovsxd rcx, eax\nmov rax, [rbp+var_20]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njz short loc_11C4\nadd [rbp+var_C], 1\nloc_11C4:\nadd [rbp+var_8], 1\nloc_11C8:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njl short loc_119C\nmov eax, [rbp+var_C]\nand eax, 1\ntest eax, eax\njnz short loc_11E8\nmov eax, [rbp+var_C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\njmp short locret_11ED\nloc_11E8:\nmov eax, 0FFFFFFFFh\nlocret_11ED:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, __int64 a2)\n{\n int v3; // [rsp+14h] [rbp-Ch]\n int i; // [rsp+18h] [rbp-8h]\n int v5; // [rsp+1Ch] [rbp-4h]\n\n v3 = 0;\n v5 = strlen(a1);\n for ( i = 0; i < v5; ++i )\n {\n if ( a1[i] != *(_BYTE *)(i + a2) )\n ++v3;\n }\n if ( (v3 & 1) != 0 )\n return 0xFFFFFFFFLL;\n else\n return (unsigned int)(v3 / 2);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_C], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_8], 0\njmp short loc_11C8\nloc_119C:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_8]\nmovsxd rcx, eax\nmov rax, [rbp+var_20]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njz short loc_11C4\nadd [rbp+var_C], 1\nloc_11C4:\nadd [rbp+var_8], 1\nloc_11C8:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njl short loc_119C\nmov eax, [rbp+var_C]\nand eax, 1\ntest eax, eax\njnz short loc_11E8\nmov eax, [rbp+var_C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\njmp short locret_11ED\nloc_11E8:\nmov eax, 0FFFFFFFFh\nlocret_11ED:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1, __int64 a2)\n{\n int v3; // [rsp+14h] [rbp-Ch]\n int i; // [rsp+18h] [rbp-8h]\n int v5; // [rsp+1Ch] [rbp-4h]\n\n v3 = 0;\n v5 = strlen(a1);\n for ( i = 0; i < v5; ++i )\n {\n if ( a1[i] != *(_BYTE *)(i + a2) )\n ++v3;\n }\n if ( (v3 & 1) != 0 )\n return 0xFFFFFFFFLL;\n else\n return (unsigned int)(v3 / 2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1, long long a2) {\n int v3;\n int i;\n int v5;\n v3 = 0;\n v5 = strlen(a1);\n for (i = 0; i < v5; ++i) {\n if (a1[i] != *(uint8_t *)(i + a2)) ++v3;\n }\n if ((v3 & 1) != 0)\n return 4294967295LL;\n else\n return (unsigned int)(v3 / 2);\n}", + "ida_pseudo_norm": "long long func0(const char *a1, long long a2) {\n int v3;\n int i;\n int v5;\n v3 = 0;\n v5 = strlen(a1);\n for (i = 0; i < v5; ++i) {\n if (a1[i] != *(uint8_t *)(i + a2)) ++v3;\n }\n if ((v3 & 1) != 0)\n return 4294967295LL;\n else\n return (unsigned int)(v3 / 2);\n}" + }, + { + "index": 595, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *str1, const char *str2) {\n int count = 0;\n int len = strlen(str1);\n for (int i = 0; i < len; i++) {\n if (str1[i] != str2[i]) {\n count++;\n }\n }\n if (count % 2 == 0) {\n return count / 2;\n } else {\n return -1;\n }\n}", + "test": "int main() {\n\n assert(func0(\"1101\", \"1110\") == 1);\n\n assert(func0(\"111\", \"000\") == -1); // -1 is returned for \"Not Possible\"\n\n assert(func0(\"111\", \"110\") == -1); // -1 is returned for \"Not Possible\"\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%r8\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nsub $0x1,%rcx\ntest %ecx,%ecx\njle 11a3 \nlea -0x1(%rcx),%edi\nmov $0x0,%eax\nmov $0x0,%edx\njmp 117b \nmov %rcx,%rax\nmovzbl (%rsi,%rax,1),%ecx\ncmp %cl,(%r8,%rax,1)\nsetne %cl\nmovzbl %cl,%ecx\nadd %ecx,%edx\nlea 0x1(%rax),%rcx\ncmp %rdi,%rax\njne 1178 \ntest $0x1,%dl\njne 11aa \nmov %edx,%eax\nshr $0x1f,%eax\nadd %edx,%eax\nsar %eax\nretq\nmov $0x0,%edx\njmp 1199 \nmov $0xffffffff,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov rbp, rsi\ncall _strlen\ntest eax, eax\njle short loc_11C2\nlea esi, [rax-1]\nmov eax, 0\nmov ecx, 0\njmp short loc_119D\nloc_1191:\nlea rdx, [rax+1]\ncmp rax, rsi\njz short loc_11AD\nmov rax, rdx\nloc_119D:\nmovzx edi, byte ptr [rbp+rax+0]\ncmp [rbx+rax], dil\njz short loc_1191\nadd ecx, 1\njmp short loc_1191\nloc_11AD:\ntest cl, 1\njnz short loc_11C9\nloc_11B2:\nmov eax, ecx\nshr eax, 1Fh\nadd eax, ecx\nsar eax, 1\nloc_11BB:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_11C2:\nmov ecx, 0\njmp short loc_11B2\nloc_11C9:\nmov eax, 0FFFFFFFFh\njmp short loc_11BB", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, __int64 a2)\n{\n int v3; // eax\n __int64 v4; // rsi\n __int64 v5; // rax\n int v6; // ecx\n\n v3 = strlen(a1);\n if ( v3 <= 0 )\n {\n v6 = 0;\n return (unsigned int)(v6 / 2);\n }\n v4 = (unsigned int)(v3 - 1);\n v5 = 0LL;\n v6 = 0;\n while ( 1 )\n {\n if ( a1[v5] != *(_BYTE *)(a2 + v5) )\n ++v6;\n if ( v5 == v4 )\n break;\n ++v5;\n }\n if ( (v6 & 1) == 0 )\n return (unsigned int)(v6 / 2);\n return 0xFFFFFFFFLL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov rbp, rsi\ncall _strlen\ntest eax, eax\njle short loc_11C2\nlea esi, [rax-1]\nmov eax, 0\nmov ecx, 0\njmp short loc_119D\nloc_1191:\nlea rdx, [rax+1]\ncmp rax, rsi\njz short loc_11AD\nmov rax, rdx\nloc_119D:\nmovzx edi, byte ptr [rbp+rax+0]\ncmp [rbx+rax], dil\njz short loc_1191\nadd ecx, 1\njmp short loc_1191\nloc_11AD:\ntest cl, 1\njnz short loc_11C9\nloc_11B2:\nmov eax, ecx\nshr eax, 1Fh\nadd eax, ecx\nsar eax, 1\nloc_11BB:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_11C2:\nmov ecx, 0\njmp short loc_11B2\nloc_11C9:\nmov eax, 0FFFFFFFFh\njmp short loc_11BB", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1, __int64 a2)\n{\n int v3; // eax\n __int64 v4; // rsi\n __int64 v5; // rax\n int v6; // ecx\n\n v3 = strlen(a1);\n if ( v3 <= 0 )\n {\n v6 = 0;\n return (unsigned int)(v6 / 2);\n }\n v4 = (unsigned int)(v3 - 1);\n v5 = 0LL;\n v6 = 0;\n while ( 1 )\n {\n if ( a1[v5] != *(_BYTE *)(a2 + v5) )\n ++v6;\n if ( v5 == v4 )\n break;\n ++v5;\n }\n if ( (v6 & 1) == 0 )\n return (unsigned int)(v6 / 2);\n return 0xFFFFFFFFLL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1, long long a2) {\n int v3;\n long long v4;\n long long v5;\n int v6;\n v3 = strlen(a1);\n if (v3 <= 0) {\n v6 = 0;\n return (unsigned int)(v6 / 2);\n }\n v4 = (unsigned int)(v3 - 1);\n v5 = 0LL;\n v6 = 0;\n while (1) {\n if (a1[v5] != *(uint8_t *)(a2 + v5)) ++v6;\n if (v5 == v4) break;\n ++v5;\n }\n if ((v6 & 1) == 0) return (unsigned int)(v6 / 2);\n return 4294967295LL;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, long long a2) {\n int v3;\n long long v4;\n long long v5;\n int v6;\n v3 = strlen(a1);\n if (v3 <= 0) {\n v6 = 0;\n return (unsigned int)(v6 / 2);\n }\n v4 = (unsigned int)(v3 - 1);\n v5 = 0LL;\n v6 = 0;\n while (1) {\n if (a1[v5] != *(uint8_t *)(a2 + v5)) ++v6;\n if (v5 == v4) break;\n ++v5;\n }\n if ((v6 & 1) == 0) return (unsigned int)(v6 / 2);\n return 4294967295LL;\n}" + }, + { + "index": 595, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *str1, const char *str2) {\n int count = 0;\n int len = strlen(str1);\n for (int i = 0; i < len; i++) {\n if (str1[i] != str2[i]) {\n count++;\n }\n }\n if (count % 2 == 0) {\n return count / 2;\n } else {\n return -1;\n }\n}", + "test": "int main() {\n\n assert(func0(\"1101\", \"1110\") == 1);\n\n assert(func0(\"111\", \"000\") == -1); // -1 is returned for \"Not Possible\"\n\n assert(func0(\"111\", \"110\") == -1); // -1 is returned for \"Not Possible\"\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsi,%rbp\npush %rbx\nmov %rdi,%rbx\nsub $0x8,%rsp\ncallq 1060 \ntest %eax,%eax\njle 1290 \nlea -0x1(%rax),%esi\nxor %edx,%edx\nxor %eax,%eax\njmp 125b \nnopw 0x0(%rax,%rax,1)\nmov %rcx,%rax\nxor %ecx,%ecx\nmovzbl 0x0(%rbp,%rax,1),%edi\ncmp %dil,(%rbx,%rax,1)\nsetne %cl\nadd %ecx,%edx\nlea 0x1(%rax),%rcx\ncmp %rax,%rsi\njne 1258 \nmov %edx,%eax\nsar %eax\nand $0x1,%edx\nmov $0xffffffff,%edx\ncmovne %edx,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopw 0x0(%rax,%rax,1)\nadd $0x8,%rsp\nxor %eax,%eax\npop %rbx\npop %rbp\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsi\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\ntest eax, eax\njle short loc_1280\nlea esi, [rax-1]\nxor ecx, ecx\nxor eax, eax\njmp short loc_124B\nloc_1248:\nmov rax, rdx\nloc_124B:\nmovzx edi, byte ptr [rbp+rax+0]\ncmp [rbx+rax], dil\njz short loc_1259\nadd ecx, 1\nloc_1259:\nlea rdx, [rax+1]\ncmp rsi, rax\njnz short loc_1248\ntest cl, 1\njnz short loc_1289\nmov eax, ecx\nshr eax, 1Fh\nadd eax, ecx\nsar eax, 1\nloc_1270:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1280:\nadd rsp, 8\nxor eax, eax\npop rbx\npop rbp\nretn\nloc_1289:\nmov eax, 0FFFFFFFFh\njmp short loc_1270", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, __int64 a2)\n{\n int v3; // eax\n __int64 v4; // rsi\n int v5; // ecx\n __int64 i; // rax\n\n v3 = strlen(a1);\n if ( v3 <= 0 )\n return 0LL;\n v4 = (unsigned int)(v3 - 1);\n v5 = 0;\n for ( i = 0LL; ; ++i )\n {\n if ( a1[i] != *(_BYTE *)(a2 + i) )\n ++v5;\n if ( v4 == i )\n break;\n }\n if ( (v5 & 1) != 0 )\n return 0xFFFFFFFFLL;\n else\n return (unsigned int)(v5 / 2);\n}", + "ida_strip_asm": "sub_1220:\nendbr64\npush rbp\nmov rbp, rsi\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\ntest eax, eax\njle short loc_1280\nlea esi, [rax-1]\nxor ecx, ecx\nxor eax, eax\njmp short loc_124B\nloc_1248:\nmov rax, rdx\nloc_124B:\nmovzx edi, byte ptr [rbp+rax+0]\ncmp [rbx+rax], dil\njz short loc_1259\nadd ecx, 1\nloc_1259:\nlea rdx, [rax+1]\ncmp rsi, rax\njnz short loc_1248\ntest cl, 1\njnz short loc_1289\nmov eax, ecx\nshr eax, 1Fh\nadd eax, ecx\nsar eax, 1\nloc_1270:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1280:\nadd rsp, 8\nxor eax, eax\npop rbx\npop rbp\nretn\nloc_1289:\nmov eax, 0FFFFFFFFh\njmp short loc_1270", + "ida_strip_pseudo": "__int64 __fastcall sub_1220(const char *a1, __int64 a2)\n{\n int v3; // eax\n __int64 v4; // rsi\n int v5; // ecx\n __int64 i; // rax\n\n v3 = strlen(a1);\n if ( v3 <= 0 )\n return 0LL;\n v4 = (unsigned int)(v3 - 1);\n v5 = 0;\n for ( i = 0LL; ; ++i )\n {\n if ( a1[i] != *(_BYTE *)(a2 + i) )\n ++v5;\n if ( v4 == i )\n break;\n }\n if ( (v5 & 1) != 0 )\n return 0xFFFFFFFFLL;\n else\n return (unsigned int)(v5 / 2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1220(const char *a1, long long a2) {\n int v3;\n long long v4;\n int v5;\n long long i;\n v3 = strlen(a1);\n if (v3 <= 0) return 0LL;\n v4 = (unsigned int)(v3 - 1);\n v5 = 0;\n for (i = 0LL;; ++i) {\n if (a1[i] != *(uint8_t *)(a2 + i)) ++v5;\n if (v4 == i) break;\n }\n if ((v5 & 1) != 0)\n return 4294967295LL;\n else\n return (unsigned int)(v5 / 2);\n}", + "ida_pseudo_norm": "long long func0(const char *a1, long long a2) {\n int v3;\n long long v4;\n int v5;\n long long i;\n v3 = strlen(a1);\n if (v3 <= 0) return 0LL;\n v4 = (unsigned int)(v3 - 1);\n v5 = 0;\n for (i = 0LL;; ++i) {\n if (a1[i] != *(uint8_t *)(a2 + i)) ++v5;\n if (v4 == i) break;\n }\n if ((v5 & 1) != 0)\n return 4294967295LL;\n else\n return (unsigned int)(v5 / 2);\n}" + }, + { + "index": 595, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *str1, const char *str2) {\n int count = 0;\n int len = strlen(str1);\n for (int i = 0; i < len; i++) {\n if (str1[i] != str2[i]) {\n count++;\n }\n }\n if (count % 2 == 0) {\n return count / 2;\n } else {\n return -1;\n }\n}", + "test": "int main() {\n\n assert(func0(\"1101\", \"1110\") == 1);\n\n assert(func0(\"111\", \"000\") == -1); // -1 is returned for \"Not Possible\"\n\n assert(func0(\"111\", \"110\") == -1); // -1 is returned for \"Not Possible\"\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsi,%rbp\npush %rbx\nmov %rdi,%rbx\nsub $0x8,%rsp\ncallq 1060 \ntest %eax,%eax\njle 1500 \nlea -0x1(%rax),%edx\ncmp $0xe,%edx\njbe 1509 \nmov %eax,%ecx\nmovdqa 0xe4d(%rip),%xmm6\nxor %edx,%edx\npxor %xmm1,%xmm1\nshr $0x4,%ecx\npxor %xmm5,%xmm5\npxor %xmm4,%xmm4\nshl $0x4,%rcx\nnopl 0x0(%rax,%rax,1)\nmovdqu 0x0(%rbp,%rdx,1),%xmm7\nmovdqu (%rbx,%rdx,1),%xmm0\nmovdqa %xmm5,%xmm3\nadd $0x10,%rdx\npcmpeqb %xmm7,%xmm0\npandn %xmm6,%xmm0\npcmpgtb %xmm0,%xmm3\nmovdqa %xmm0,%xmm2\npunpcklbw %xmm3,%xmm2\npunpckhbw %xmm3,%xmm0\nmovdqa %xmm4,%xmm3\npcmpgtw %xmm2,%xmm3\nmovdqa %xmm2,%xmm7\npunpcklwd %xmm3,%xmm7\npunpckhwd %xmm3,%xmm2\nmovdqa %xmm0,%xmm3\npaddd %xmm7,%xmm1\npaddd %xmm2,%xmm1\nmovdqa %xmm4,%xmm2\npcmpgtw %xmm0,%xmm2\npunpcklwd %xmm2,%xmm3\npunpckhwd %xmm2,%xmm0\npaddd %xmm3,%xmm1\npaddd %xmm0,%xmm1\ncmp %rcx,%rdx\njne 1280 \nmovdqa %xmm1,%xmm0\nmov %eax,%ecx\npsrldq $0x8,%xmm0\nand $0xfffffff0,%ecx\npaddd %xmm1,%xmm0\nmovdqa %xmm0,%xmm1\npsrldq $0x4,%xmm1\npaddd %xmm1,%xmm0\nmovd %xmm0,%edx\ntest $0xf,%al\nje 14e4 \nmovslq %ecx,%rsi\nmovzbl 0x0(%rbp,%rsi,1),%edi\ncmp %dil,(%rbx,%rsi,1)\nsetne %sil\nmovzbl %sil,%esi\nadd %esi,%edx\nlea 0x1(%rcx),%esi\ncmp %eax,%esi\njge 14e4 \nmovslq %esi,%rsi\nmovzbl (%rbx,%rsi,1),%edi\ncmp %dil,0x0(%rbp,%rsi,1)\nsetne %sil\nmovzbl %sil,%esi\nadd %esi,%edx\nlea 0x2(%rcx),%esi\ncmp %esi,%eax\njle 14e4 \nmovslq %esi,%rsi\nmovzbl 0x0(%rbp,%rsi,1),%edi\ncmp %dil,(%rbx,%rsi,1)\nsetne %sil\nmovzbl %sil,%esi\nadd %esi,%edx\nlea 0x3(%rcx),%esi\ncmp %esi,%eax\njle 14e4 \nmovslq %esi,%rsi\nmovzbl 0x0(%rbp,%rsi,1),%edi\ncmp %dil,(%rbx,%rsi,1)\nsetne %sil\nmovzbl %sil,%esi\nadd %esi,%edx\nlea 0x4(%rcx),%esi\ncmp %esi,%eax\njle 14e4 \nmovslq %esi,%rsi\nmovzbl 0x0(%rbp,%rsi,1),%edi\ncmp %dil,(%rbx,%rsi,1)\nsetne %sil\nmovzbl %sil,%esi\nadd %esi,%edx\nlea 0x5(%rcx),%esi\ncmp %esi,%eax\njle 14e4 \nmovslq %esi,%rsi\nmovzbl 0x0(%rbp,%rsi,1),%edi\ncmp %dil,(%rbx,%rsi,1)\nsetne %sil\nmovzbl %sil,%esi\nadd %esi,%edx\nlea 0x6(%rcx),%esi\ncmp %esi,%eax\njle 14e4 \nmovslq %esi,%rsi\nmovzbl 0x0(%rbp,%rsi,1),%edi\ncmp %dil,(%rbx,%rsi,1)\nsetne %sil\nmovzbl %sil,%esi\nadd %esi,%edx\nlea 0x7(%rcx),%esi\ncmp %esi,%eax\njle 14e4 \nmovslq %esi,%rsi\nmovzbl 0x0(%rbp,%rsi,1),%edi\ncmp %dil,(%rbx,%rsi,1)\nsetne %sil\nmovzbl %sil,%esi\nadd %esi,%edx\nlea 0x8(%rcx),%esi\ncmp %esi,%eax\njle 14e4 \nmovslq %esi,%rsi\nmovzbl 0x0(%rbp,%rsi,1),%edi\ncmp %dil,(%rbx,%rsi,1)\nsetne %sil\nmovzbl %sil,%esi\nadd %esi,%edx\nlea 0x9(%rcx),%esi\ncmp %esi,%eax\njle 14e4 \nmovslq %esi,%rsi\nmovzbl 0x0(%rbp,%rsi,1),%edi\ncmp %dil,(%rbx,%rsi,1)\nsetne %sil\nmovzbl %sil,%esi\nadd %esi,%edx\nlea 0xa(%rcx),%esi\ncmp %esi,%eax\njle 14e4 \nmovslq %esi,%rsi\nmovzbl 0x0(%rbp,%rsi,1),%edi\ncmp %dil,(%rbx,%rsi,1)\nsetne %sil\nmovzbl %sil,%esi\nadd %esi,%edx\nlea 0xb(%rcx),%esi\ncmp %esi,%eax\njle 14e4 \nmovslq %esi,%rsi\nmovzbl 0x0(%rbp,%rsi,1),%edi\ncmp %dil,(%rbx,%rsi,1)\nsetne %sil\nmovzbl %sil,%esi\nadd %esi,%edx\nlea 0xc(%rcx),%esi\ncmp %esi,%eax\njle 14e4 \nmovslq %esi,%rsi\nmovzbl 0x0(%rbp,%rsi,1),%edi\ncmp %dil,(%rbx,%rsi,1)\nsetne %sil\nmovzbl %sil,%esi\nadd %esi,%edx\nlea 0xd(%rcx),%esi\ncmp %esi,%eax\njle 14e4 \nmovslq %esi,%rsi\nmovzbl 0x0(%rbp,%rsi,1),%edi\ncmp %dil,(%rbx,%rsi,1)\nsetne %sil\nadd $0xe,%ecx\nmovzbl %sil,%esi\nadd %esi,%edx\ncmp %ecx,%eax\njle 14e4 \nmovslq %ecx,%rcx\nmovzbl 0x0(%rbp,%rcx,1),%eax\ncmp %al,(%rbx,%rcx,1)\nsetne %al\nmovzbl %al,%eax\nadd %eax,%edx\nmov %edx,%eax\nsar %eax\nand $0x1,%edx\nmov $0xffffffff,%edx\ncmovne %edx,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopw 0x0(%rax,%rax,1)\nadd $0x8,%rsp\nxor %eax,%eax\npop %rbx\npop %rbp\nretq\nxor %ecx,%ecx\nxor %edx,%edx\njmpq 1313 \nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsi\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\ntest eax, eax\njle loc_1460\nmov rdx, rax\nlea eax, [rax-1]\ncmp eax, 0Eh\njbe loc_1469\nmov ecx, edx\npxor xmm1, xmm1\npxor xmm5, xmm5\nxor eax, eax\nshr ecx, 4\npxor xmm4, xmm4\nshl rcx, 4\nnop dword ptr [rax+rax+00h]\nloc_1268:\nmovdqu xmm0, xmmword ptr [rbx+rax]\nmovdqu xmm7, xmmword ptr [rbp+rax+0]\nmovdqa xmm3, xmm5\nadd rax, 10h\npcmpeqb xmm0, xmm7\npcmpeqb xmm0, xmm5\npcmpgtb xmm3, xmm0\nmovdqa xmm2, xmm0\npunpcklbw xmm2, xmm3\npunpckhbw xmm0, xmm3\nmovdqa xmm3, xmm4\npcmpgtw xmm3, xmm2\nmovdqa xmm6, xmm2\npunpcklwd xmm6, xmm3\npunpckhwd xmm2, xmm3\nmovdqa xmm3, xmm0\npsubd xmm1, xmm6\npsubd xmm1, xmm2\nmovdqa xmm2, xmm4\npcmpgtw xmm2, xmm0\npunpcklwd xmm3, xmm2\npunpckhwd xmm0, xmm2\npsubd xmm1, xmm3\npsubd xmm1, xmm0\ncmp rax, rcx\njnz short loc_1268\nmovdqa xmm0, xmm1\nmov eax, edx\npsrldq xmm0, 8\nand eax, 0FFFFFFF0h\npaddd xmm0, xmm1\nmov ecx, eax\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\npaddd xmm0, xmm2\nmovd edi, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm1, 8\npaddd xmm1, xmm0\ntest dl, 0Fh\njz loc_1449\nloc_130B:\nmov esi, edx\nsub esi, eax\nlea r8d, [rsi-1]\ncmp r8d, 6\njbe loc_13AA\nmovq xmm2, qword ptr [rbp+rax+0]\nmovq xmm0, qword ptr [rbx+rax]\npcmpeqb xmm0, xmm2\npxor xmm2, xmm2\npcmpeqb xmm0, xmm2\npcmpgtb xmm2, xmm0\nmovdqa xmm3, xmm0\npunpcklbw xmm3, xmm2\npunpcklbw xmm0, xmm2\npxor xmm2, xmm2\nmovdqa xmm4, xmm2\nmovdqa xmm5, xmm3\npshufd xmm0, xmm0, 4Eh ; 'N'\npcmpgtw xmm4, xmm3\npcmpgtw xmm2, xmm0\npunpcklwd xmm5, xmm4\npunpcklwd xmm3, xmm4\npsubd xmm1, xmm5\npshufd xmm3, xmm3, 4Eh ; 'N'\npsubd xmm1, xmm3\nmovdqa xmm3, xmm0\npunpcklwd xmm0, xmm2\npunpcklwd xmm3, xmm2\npshufd xmm0, xmm0, 4Eh ; 'N'\npsubd xmm1, xmm3\npsubd xmm1, xmm0\nmovd edi, xmm1\npshufd xmm7, xmm1, 0E5h\nmovd eax, xmm7\nadd edi, eax\nmov eax, esi\nand eax, 0FFFFFFF8h\nadd ecx, eax\nand esi, 7\njz loc_1449\nloc_13AA:\nmovsxd rax, ecx\nmovzx esi, byte ptr [rbp+rax+0]\ncmp [rbx+rax], sil\njz short loc_13BB\nadd edi, 1\nloc_13BB:\nlea eax, [rcx+1]\ncmp edx, eax\njle loc_1449\ncdqe\nmovzx esi, byte ptr [rbp+rax+0]\ncmp [rbx+rax], sil\njz short loc_13D6\nadd edi, 1\nloc_13D6:\nlea eax, [rcx+2]\ncmp edx, eax\njle short loc_1449\ncdqe\nmovzx esi, byte ptr [rbx+rax]\ncmp [rbp+rax+0], sil\njz short loc_13ED\nadd edi, 1\nloc_13ED:\nlea eax, [rcx+3]\ncmp edx, eax\njle short loc_1449\ncdqe\nmovzx esi, byte ptr [rbp+rax+0]\ncmp [rbx+rax], sil\njz short loc_1404\nadd edi, 1\nloc_1404:\nlea eax, [rcx+4]\ncmp edx, eax\njle short loc_1449\ncdqe\nmovzx esi, byte ptr [rbx+rax]\ncmp [rbp+rax+0], sil\njz short loc_141B\nadd edi, 1\nloc_141B:\nlea eax, [rcx+5]\ncmp edx, eax\njle short loc_1449\ncdqe\nmovzx esi, byte ptr [rbp+rax+0]\ncmp [rbx+rax], sil\njz short loc_1432\nadd edi, 1\nloc_1432:\nadd ecx, 6\ncmp edx, ecx\njle short loc_1449\nmovsxd rcx, ecx\nmovzx eax, byte ptr [rbp+rcx+0]\ncmp [rbx+rcx], al\njz short loc_1449\nadd edi, 1\nloc_1449:\ntest dil, 1\njnz short loc_1478\nmov eax, edi\nshr eax, 1Fh\nadd eax, edi\nsar eax, 1\nloc_1458:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1460:\nadd rsp, 8\nxor eax, eax\npop rbx\npop rbp\nretn\nloc_1469:\npxor xmm1, xmm1\nxor eax, eax\nxor ecx, ecx\nxor edi, edi\njmp loc_130B\nloc_1478:\nmov eax, 0FFFFFFFFh\njmp short loc_1458", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, __int64 a2)\n{\n int v4; // eax\n int v5; // edx\n __m128i v6; // xmm1\n __int64 v7; // rax\n __m128i v8; // xmm0\n __m128i v9; // xmm7\n __m128i v10; // xmm0\n __m128i v11; // xmm3\n __m128i v12; // xmm2\n __m128i v13; // xmm0\n __m128i v14; // xmm3\n __m128i v15; // xmm1\n __m128i v16; // xmm2\n __int64 v17; // rax\n __m128i v18; // xmm0\n signed int v19; // ecx\n int v20; // edi\n __m128i v21; // xmm1\n int v22; // esi\n __m128i v23; // xmm0\n __m128i v24; // xmm3\n __m128i v25; // xmm0\n __m128i v26; // xmm2\n __m128i v27; // xmm3\n __m128i v28; // xmm1\n int v29; // ecx\n\n v4 = strlen(a1);\n if ( v4 <= 0 )\n return 0LL;\n v5 = v4;\n if ( (unsigned int)(v4 - 1) <= 0xE )\n {\n v21 = 0LL;\n v17 = 0LL;\n v19 = 0;\n v20 = 0;\n goto LABEL_6;\n }\n v6 = 0LL;\n v7 = 0LL;\n do\n {\n v8 = _mm_loadu_si128((const __m128i *)&a1[v7]);\n v9 = _mm_loadu_si128((const __m128i *)(a2 + v7));\n v7 += 16LL;\n v10 = _mm_cmpeq_epi8(_mm_cmpeq_epi8(v8, v9), (__m128i)0LL);\n v11 = _mm_cmpgt_epi8((__m128i)0LL, v10);\n v12 = _mm_unpacklo_epi8(v10, v11);\n v13 = _mm_unpackhi_epi8(v10, v11);\n v14 = _mm_cmpgt_epi16((__m128i)0LL, v12);\n v15 = _mm_sub_epi32(_mm_sub_epi32(v6, _mm_unpacklo_epi16(v12, v14)), _mm_unpackhi_epi16(v12, v14));\n v16 = _mm_cmpgt_epi16((__m128i)0LL, v13);\n v6 = _mm_sub_epi32(_mm_sub_epi32(v15, _mm_unpacklo_epi16(v13, v16)), _mm_unpackhi_epi16(v13, v16));\n }\n while ( v7 != 16LL * ((unsigned int)v5 >> 4) );\n v17 = v5 & 0xFFFFFFF0;\n v18 = _mm_add_epi32(_mm_srli_si128(v6, 8), v6);\n v19 = v5 & 0xFFFFFFF0;\n v20 = _mm_cvtsi128_si32(_mm_add_epi32(v18, _mm_srli_si128(v18, 4)));\n v21 = v18;\n if ( (v5 & 0xF) != 0 )\n {\nLABEL_6:\n v22 = v5 - v17;\n if ( (unsigned int)(v5 - v17 - 1) <= 6 )\n goto LABEL_8;\n v23 = _mm_cmpeq_epi8(\n _mm_cmpeq_epi8(_mm_loadl_epi64((const __m128i *)&a1[v17]), _mm_loadl_epi64((const __m128i *)(a2 + v17))),\n (__m128i)0LL);\n v24 = _mm_unpacklo_epi8(v23, _mm_cmpgt_epi8((__m128i)0LL, v23));\n v25 = _mm_shuffle_epi32(v24, 78);\n v26 = _mm_cmpgt_epi16((__m128i)0LL, v25);\n v27 = _mm_unpacklo_epi16(v24, _mm_cmpgt_epi16((__m128i)0LL, v24));\n v28 = _mm_sub_epi32(\n _mm_sub_epi32(\n _mm_sub_epi32(_mm_sub_epi32(v21, v27), _mm_shuffle_epi32(v27, 78)),\n _mm_unpacklo_epi16(v25, v26)),\n _mm_shuffle_epi32(_mm_unpacklo_epi16(v25, v26), 78));\n v20 = _mm_cvtsi128_si32(_mm_shuffle_epi32(v28, 229)) + _mm_cvtsi128_si32(v28);\n v19 += v22 & 0xFFFFFFF8;\n if ( (v22 & 7) != 0 )\n {\nLABEL_8:\n if ( a1[v19] != *(_BYTE *)(a2 + v19) )\n ++v20;\n if ( v5 > v19 + 1 )\n {\n if ( a1[v19 + 1] != *(_BYTE *)(a2 + v19 + 1) )\n ++v20;\n if ( v5 > v19 + 2 )\n {\n if ( *(_BYTE *)(a2 + v19 + 2) != a1[v19 + 2] )\n ++v20;\n if ( v5 > v19 + 3 )\n {\n if ( a1[v19 + 3] != *(_BYTE *)(a2 + v19 + 3) )\n ++v20;\n if ( v5 > v19 + 4 )\n {\n if ( *(_BYTE *)(a2 + v19 + 4) != a1[v19 + 4] )\n ++v20;\n if ( v5 > v19 + 5 )\n {\n if ( a1[v19 + 5] != *(_BYTE *)(a2 + v19 + 5) )\n ++v20;\n v29 = v19 + 6;\n if ( v5 > v29 && a1[v29] != *(_BYTE *)(a2 + v29) )\n ++v20;\n }\n }\n }\n }\n }\n }\n }\n if ( (v20 & 1) != 0 )\n return 0xFFFFFFFFLL;\n else\n return (unsigned int)(v20 / 2);\n}", + "ida_strip_asm": "sub_1220:\nendbr64\npush rbp\nmov rbp, rsi\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\ntest eax, eax\njle loc_1460\nmov rdx, rax\nlea eax, [rax-1]\ncmp eax, 0Eh\njbe loc_1469\nmov ecx, edx\npxor xmm1, xmm1\npxor xmm5, xmm5\nxor eax, eax\nshr ecx, 4\npxor xmm4, xmm4\nshl rcx, 4\nnop dword ptr [rax+rax+00h]\nloc_1268:\nmovdqu xmm0, xmmword ptr [rbx+rax]\nmovdqu xmm7, xmmword ptr [rbp+rax+0]\nmovdqa xmm3, xmm5\nadd rax, 10h\npcmpeqb xmm0, xmm7\npcmpeqb xmm0, xmm5\npcmpgtb xmm3, xmm0\nmovdqa xmm2, xmm0\npunpcklbw xmm2, xmm3\npunpckhbw xmm0, xmm3\nmovdqa xmm3, xmm4\npcmpgtw xmm3, xmm2\nmovdqa xmm6, xmm2\npunpcklwd xmm6, xmm3\npunpckhwd xmm2, xmm3\nmovdqa xmm3, xmm0\npsubd xmm1, xmm6\npsubd xmm1, xmm2\nmovdqa xmm2, xmm4\npcmpgtw xmm2, xmm0\npunpcklwd xmm3, xmm2\npunpckhwd xmm0, xmm2\npsubd xmm1, xmm3\npsubd xmm1, xmm0\ncmp rax, rcx\njnz short loc_1268\nmovdqa xmm0, xmm1\nmov eax, edx\npsrldq xmm0, 8\nand eax, 0FFFFFFF0h\npaddd xmm0, xmm1\nmov ecx, eax\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\npaddd xmm0, xmm2\nmovd edi, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm1, 8\npaddd xmm1, xmm0\ntest dl, 0Fh\njz loc_1449\nloc_130B:\nmov esi, edx\nsub esi, eax\nlea r8d, [rsi-1]\ncmp r8d, 6\njbe loc_13AA\nmovq xmm2, qword ptr [rbp+rax+0]\nmovq xmm0, qword ptr [rbx+rax]\npcmpeqb xmm0, xmm2\npxor xmm2, xmm2\npcmpeqb xmm0, xmm2\npcmpgtb xmm2, xmm0\nmovdqa xmm3, xmm0\npunpcklbw xmm3, xmm2\npunpcklbw xmm0, xmm2\npxor xmm2, xmm2\nmovdqa xmm4, xmm2\nmovdqa xmm5, xmm3\npshufd xmm0, xmm0, 4Eh ; 'N'\npcmpgtw xmm4, xmm3\npcmpgtw xmm2, xmm0\npunpcklwd xmm5, xmm4\npunpcklwd xmm3, xmm4\npsubd xmm1, xmm5\npshufd xmm3, xmm3, 4Eh ; 'N'\npsubd xmm1, xmm3\nmovdqa xmm3, xmm0\npunpcklwd xmm0, xmm2\npunpcklwd xmm3, xmm2\npshufd xmm0, xmm0, 4Eh ; 'N'\npsubd xmm1, xmm3\npsubd xmm1, xmm0\nmovd edi, xmm1\npshufd xmm7, xmm1, 0E5h\nmovd eax, xmm7\nadd edi, eax\nmov eax, esi\nand eax, 0FFFFFFF8h\nadd ecx, eax\nand esi, 7\njz loc_1449\nloc_13AA:\nmovsxd rax, ecx\nmovzx esi, byte ptr [rbp+rax+0]\ncmp [rbx+rax], sil\njz short loc_13BB\nadd edi, 1\nloc_13BB:\nlea eax, [rcx+1]\ncmp edx, eax\njle loc_1449\ncdqe\nmovzx esi, byte ptr [rbp+rax+0]\ncmp [rbx+rax], sil\njz short loc_13D6\nadd edi, 1\nloc_13D6:\nlea eax, [rcx+2]\ncmp edx, eax\njle short loc_1449\ncdqe\nmovzx esi, byte ptr [rbx+rax]\ncmp [rbp+rax+0], sil\njz short loc_13ED\nadd edi, 1\nloc_13ED:\nlea eax, [rcx+3]\ncmp edx, eax\njle short loc_1449\ncdqe\nmovzx esi, byte ptr [rbp+rax+0]\ncmp [rbx+rax], sil\njz short loc_1404\nadd edi, 1\nloc_1404:\nlea eax, [rcx+4]\ncmp edx, eax\njle short loc_1449\ncdqe\nmovzx esi, byte ptr [rbx+rax]\ncmp [rbp+rax+0], sil\njz short loc_141B\nadd edi, 1\nloc_141B:\nlea eax, [rcx+5]\ncmp edx, eax\njle short loc_1449\ncdqe\nmovzx esi, byte ptr [rbp+rax+0]\ncmp [rbx+rax], sil\njz short loc_1432\nadd edi, 1\nloc_1432:\nadd ecx, 6\ncmp edx, ecx\njle short loc_1449\nmovsxd rcx, ecx\nmovzx eax, byte ptr [rbp+rcx+0]\ncmp [rbx+rcx], al\njz short loc_1449\nadd edi, 1\nloc_1449:\ntest dil, 1\njnz short loc_1478\nmov eax, edi\nshr eax, 1Fh\nadd eax, edi\nsar eax, 1\nloc_1458:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1460:\nadd rsp, 8\nxor eax, eax\npop rbx\npop rbp\nretn\nloc_1469:\npxor xmm1, xmm1\nxor eax, eax\nxor ecx, ecx\nxor edi, edi\njmp loc_130B\nloc_1478:\nmov eax, 0FFFFFFFFh\njmp short loc_1458", + "ida_strip_pseudo": "__int64 __fastcall sub_1220(const char *a1, __int64 a2)\n{\n int v4; // eax\n int v5; // edx\n __m128i v6; // xmm1\n __int64 v7; // rax\n __m128i v8; // xmm0\n __m128i v9; // xmm7\n __m128i v10; // xmm0\n __m128i v11; // xmm3\n __m128i v12; // xmm2\n __m128i v13; // xmm0\n __m128i v14; // xmm3\n __m128i v15; // xmm1\n __m128i v16; // xmm2\n __int64 v17; // rax\n __m128i v18; // xmm0\n signed int v19; // ecx\n int v20; // edi\n __m128i v21; // xmm1\n int v22; // esi\n __m128i v23; // xmm0\n __m128i v24; // xmm3\n __m128i v25; // xmm0\n __m128i v26; // xmm2\n __m128i v27; // xmm3\n __m128i v28; // xmm1\n int v29; // ecx\n\n v4 = strlen(a1);\n if ( v4 <= 0 )\n return 0LL;\n v5 = v4;\n if ( (unsigned int)(v4 - 1) <= 0xE )\n {\n v21 = 0LL;\n v17 = 0LL;\n v19 = 0;\n v20 = 0;\n goto LABEL_6;\n }\n v6 = 0LL;\n v7 = 0LL;\n do\n {\n v8 = _mm_loadu_si128((const __m128i *)&a1[v7]);\n v9 = _mm_loadu_si128((const __m128i *)(a2 + v7));\n v7 += 16LL;\n v10 = _mm_cmpeq_epi8(_mm_cmpeq_epi8(v8, v9), (__m128i)0LL);\n v11 = _mm_cmpgt_epi8((__m128i)0LL, v10);\n v12 = _mm_unpacklo_epi8(v10, v11);\n v13 = _mm_unpackhi_epi8(v10, v11);\n v14 = _mm_cmpgt_epi16((__m128i)0LL, v12);\n v15 = _mm_sub_epi32(_mm_sub_epi32(v6, _mm_unpacklo_epi16(v12, v14)), _mm_unpackhi_epi16(v12, v14));\n v16 = _mm_cmpgt_epi16((__m128i)0LL, v13);\n v6 = _mm_sub_epi32(_mm_sub_epi32(v15, _mm_unpacklo_epi16(v13, v16)), _mm_unpackhi_epi16(v13, v16));\n }\n while ( v7 != 16LL * ((unsigned int)v5 >> 4) );\n v17 = v5 & 0xFFFFFFF0;\n v18 = _mm_add_epi32(_mm_srli_si128(v6, 8), v6);\n v19 = v5 & 0xFFFFFFF0;\n v20 = _mm_cvtsi128_si32(_mm_add_epi32(v18, _mm_srli_si128(v18, 4)));\n v21 = v18;\n if ( (v5 & 0xF) != 0 )\n {\nLABEL_6:\n v22 = v5 - v17;\n if ( (unsigned int)(v5 - v17 - 1) <= 6 )\n goto LABEL_8;\n v23 = _mm_cmpeq_epi8(\n _mm_cmpeq_epi8(_mm_loadl_epi64((const __m128i *)&a1[v17]), _mm_loadl_epi64((const __m128i *)(a2 + v17))),\n (__m128i)0LL);\n v24 = _mm_unpacklo_epi8(v23, _mm_cmpgt_epi8((__m128i)0LL, v23));\n v25 = _mm_shuffle_epi32(v24, 78);\n v26 = _mm_cmpgt_epi16((__m128i)0LL, v25);\n v27 = _mm_unpacklo_epi16(v24, _mm_cmpgt_epi16((__m128i)0LL, v24));\n v28 = _mm_sub_epi32(\n _mm_sub_epi32(\n _mm_sub_epi32(_mm_sub_epi32(v21, v27), _mm_shuffle_epi32(v27, 78)),\n _mm_unpacklo_epi16(v25, v26)),\n _mm_shuffle_epi32(_mm_unpacklo_epi16(v25, v26), 78));\n v20 = _mm_cvtsi128_si32(_mm_shuffle_epi32(v28, 229)) + _mm_cvtsi128_si32(v28);\n v19 += v22 & 0xFFFFFFF8;\n if ( (v22 & 7) != 0 )\n {\nLABEL_8:\n if ( a1[v19] != *(_BYTE *)(a2 + v19) )\n ++v20;\n if ( v5 > v19 + 1 )\n {\n if ( a1[v19 + 1] != *(_BYTE *)(a2 + v19 + 1) )\n ++v20;\n if ( v5 > v19 + 2 )\n {\n if ( *(_BYTE *)(a2 + v19 + 2) != a1[v19 + 2] )\n ++v20;\n if ( v5 > v19 + 3 )\n {\n if ( a1[v19 + 3] != *(_BYTE *)(a2 + v19 + 3) )\n ++v20;\n if ( v5 > v19 + 4 )\n {\n if ( *(_BYTE *)(a2 + v19 + 4) != a1[v19 + 4] )\n ++v20;\n if ( v5 > v19 + 5 )\n {\n if ( a1[v19 + 5] != *(_BYTE *)(a2 + v19 + 5) )\n ++v20;\n v29 = v19 + 6;\n if ( v5 > v29 && a1[v29] != *(_BYTE *)(a2 + v29) )\n ++v20;\n }\n }\n }\n }\n }\n }\n }\n if ( (v20 & 1) != 0 )\n return 0xFFFFFFFFLL;\n else\n return (unsigned int)(v20 / 2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1220(const char *a1, long long a2) {\n int v4;\n int v5;\n __m128i v6;\n long long v7;\n __m128i v8;\n __m128i v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n __m128i v15;\n __m128i v16;\n long long v17;\n __m128i v18;\n signed int v19;\n int v20;\n __m128i v21;\n int v22;\n __m128i v23;\n __m128i v24;\n __m128i v25;\n __m128i v26;\n __m128i v27;\n __m128i v28;\n int v29;\n v4 = strlen(a1);\n if (v4 <= 0) return 0LL;\n v5 = v4;\n if ((unsigned int)(v4 - 1) <= 14) {\n v21 = 0LL;\n v17 = 0LL;\n v19 = 0;\n v20 = 0;\n goto LABEL_6;\n }\n v6 = 0LL;\n v7 = 0LL;\n do {\n v8 = _mm_loadu_si128((const __m128i *)&a1[v7]);\n v9 = _mm_loadu_si128((const __m128i *)(a2 + v7));\n v7 += 16LL;\n v10 = _mm_cmpeq_epi8(_mm_cmpeq_epi8(v8, v9), (__m128i)0LL);\n v11 = _mm_cmpgt_epi8((__m128i)0LL, v10);\n v12 = _mm_unpacklo_epi8(v10, v11);\n v13 = _mm_unpackhi_epi8(v10, v11);\n v14 = _mm_cmpgt_epi16((__m128i)0LL, v12);\n v15 = _mm_sub_epi32(_mm_sub_epi32(v6, _mm_unpacklo_epi16(v12, v14)),\n _mm_unpackhi_epi16(v12, v14));\n v16 = _mm_cmpgt_epi16((__m128i)0LL, v13);\n v6 = _mm_sub_epi32(_mm_sub_epi32(v15, _mm_unpacklo_epi16(v13, v16)),\n _mm_unpackhi_epi16(v13, v16));\n } while (v7 != 16LL * ((unsigned int)v5 >> 4));\n v17 = v5 & 4294967280;\n v18 = _mm_add_epi32(_mm_srli_si128(v6, 8), v6);\n v19 = v5 & 4294967280;\n v20 = _mm_cvtsi128_si32(_mm_add_epi32(v18, _mm_srli_si128(v18, 4)));\n v21 = v18;\n if ((v5 & 15) != 0) {\n LABEL_6:\n v22 = v5 - v17;\n if ((unsigned int)(v5 - v17 - 1) <= 6) goto LABEL_8;\n v23 = _mm_cmpeq_epi8(\n _mm_cmpeq_epi8(_mm_loadl_epi64((const __m128i *)&a1[v17]),\n _mm_loadl_epi64((const __m128i *)(a2 + v17))),\n (__m128i)0LL);\n v24 = _mm_unpacklo_epi8(v23, _mm_cmpgt_epi8((__m128i)0LL, v23));\n v25 = _mm_shuffle_epi32(v24, 78);\n v26 = _mm_cmpgt_epi16((__m128i)0LL, v25);\n v27 = _mm_unpacklo_epi16(v24, _mm_cmpgt_epi16((__m128i)0LL, v24));\n v28 = _mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(v21, v27),\n _mm_shuffle_epi32(v27, 78)),\n _mm_unpacklo_epi16(v25, v26)),\n _mm_shuffle_epi32(_mm_unpacklo_epi16(v25, v26), 78));\n v20 =\n _mm_cvtsi128_si32(_mm_shuffle_epi32(v28, 229)) + _mm_cvtsi128_si32(v28);\n v19 += v22 & 4294967288;\n if ((v22 & 7) != 0) {\n LABEL_8:\n if (a1[v19] != *(uint8_t *)(a2 + v19)) ++v20;\n if (v5 > v19 + 1) {\n if (a1[v19 + 1] != *(uint8_t *)(a2 + v19 + 1)) ++v20;\n if (v5 > v19 + 2) {\n if (*(uint8_t *)(a2 + v19 + 2) != a1[v19 + 2]) ++v20;\n if (v5 > v19 + 3) {\n if (a1[v19 + 3] != *(uint8_t *)(a2 + v19 + 3)) ++v20;\n if (v5 > v19 + 4) {\n if (*(uint8_t *)(a2 + v19 + 4) != a1[v19 + 4]) ++v20;\n if (v5 > v19 + 5) {\n if (a1[v19 + 5] != *(uint8_t *)(a2 + v19 + 5)) ++v20;\n v29 = v19 + 6;\n if (v5 > v29 && a1[v29] != *(uint8_t *)(a2 + v29)) ++v20;\n }\n }\n }\n }\n }\n }\n }\n if ((v20 & 1) != 0)\n return 4294967295LL;\n else\n return (unsigned int)(v20 / 2);\n}", + "ida_pseudo_norm": "long long func0(const char *a1, long long a2) {\n int v4;\n int v5;\n __m128i v6;\n long long v7;\n __m128i v8;\n __m128i v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n __m128i v15;\n __m128i v16;\n long long v17;\n __m128i v18;\n signed int v19;\n int v20;\n __m128i v21;\n int v22;\n __m128i v23;\n __m128i v24;\n __m128i v25;\n __m128i v26;\n __m128i v27;\n __m128i v28;\n int v29;\n v4 = strlen(a1);\n if (v4 <= 0) return 0LL;\n v5 = v4;\n if ((unsigned int)(v4 - 1) <= 14) {\n v21 = 0LL;\n v17 = 0LL;\n v19 = 0;\n v20 = 0;\n goto LABEL_6;\n }\n v6 = 0LL;\n v7 = 0LL;\n do {\n v8 = _mm_loadu_si128((const __m128i *)&a1[v7]);\n v9 = _mm_loadu_si128((const __m128i *)(a2 + v7));\n v7 += 16LL;\n v10 = _mm_cmpeq_epi8(_mm_cmpeq_epi8(v8, v9), (__m128i)0LL);\n v11 = _mm_cmpgt_epi8((__m128i)0LL, v10);\n v12 = _mm_unpacklo_epi8(v10, v11);\n v13 = _mm_unpackhi_epi8(v10, v11);\n v14 = _mm_cmpgt_epi16((__m128i)0LL, v12);\n v15 = _mm_sub_epi32(_mm_sub_epi32(v6, _mm_unpacklo_epi16(v12, v14)),\n _mm_unpackhi_epi16(v12, v14));\n v16 = _mm_cmpgt_epi16((__m128i)0LL, v13);\n v6 = _mm_sub_epi32(_mm_sub_epi32(v15, _mm_unpacklo_epi16(v13, v16)),\n _mm_unpackhi_epi16(v13, v16));\n } while (v7 != 16LL * ((unsigned int)v5 >> 4));\n v17 = v5 & 4294967280;\n v18 = _mm_add_epi32(_mm_srli_si128(v6, 8), v6);\n v19 = v5 & 4294967280;\n v20 = _mm_cvtsi128_si32(_mm_add_epi32(v18, _mm_srli_si128(v18, 4)));\n v21 = v18;\n if ((v5 & 15) != 0) {\n LABEL_6:\n v22 = v5 - v17;\n if ((unsigned int)(v5 - v17 - 1) <= 6) goto LABEL_8;\n v23 = _mm_cmpeq_epi8(\n _mm_cmpeq_epi8(_mm_loadl_epi64((const __m128i *)&a1[v17]),\n _mm_loadl_epi64((const __m128i *)(a2 + v17))),\n (__m128i)0LL);\n v24 = _mm_unpacklo_epi8(v23, _mm_cmpgt_epi8((__m128i)0LL, v23));\n v25 = _mm_shuffle_epi32(v24, 78);\n v26 = _mm_cmpgt_epi16((__m128i)0LL, v25);\n v27 = _mm_unpacklo_epi16(v24, _mm_cmpgt_epi16((__m128i)0LL, v24));\n v28 = _mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(v21, v27),\n _mm_shuffle_epi32(v27, 78)),\n _mm_unpacklo_epi16(v25, v26)),\n _mm_shuffle_epi32(_mm_unpacklo_epi16(v25, v26), 78));\n v20 =\n _mm_cvtsi128_si32(_mm_shuffle_epi32(v28, 229)) + _mm_cvtsi128_si32(v28);\n v19 += v22 & 4294967288;\n if ((v22 & 7) != 0) {\n LABEL_8:\n if (a1[v19] != *(uint8_t *)(a2 + v19)) ++v20;\n if (v5 > v19 + 1) {\n if (a1[v19 + 1] != *(uint8_t *)(a2 + v19 + 1)) ++v20;\n if (v5 > v19 + 2) {\n if (*(uint8_t *)(a2 + v19 + 2) != a1[v19 + 2]) ++v20;\n if (v5 > v19 + 3) {\n if (a1[v19 + 3] != *(uint8_t *)(a2 + v19 + 3)) ++v20;\n if (v5 > v19 + 4) {\n if (*(uint8_t *)(a2 + v19 + 4) != a1[v19 + 4]) ++v20;\n if (v5 > v19 + 5) {\n if (a1[v19 + 5] != *(uint8_t *)(a2 + v19 + 5)) ++v20;\n v29 = v19 + 6;\n if (v5 > v29 && a1[v29] != *(uint8_t *)(a2 + v29)) ++v20;\n }\n }\n }\n }\n }\n }\n }\n if ((v20 & 1) != 0)\n return 4294967295LL;\n else\n return (unsigned int)(v20 / 2);\n}" + }, + { + "index": 596, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "size_t func0(const char *tuple[], size_t size) {\n size_t total_size = 0;\n for (size_t i = 0; i < size; i++) {\n total_size += sizeof(tuple[i]);\n }\n return total_size;\n}", + "test": "int main() {\n\n // Tuple 1 with string elements\n\n const char *tuple1[] = {\"A\", \"1\", \"B\", \"2\", \"C\", \"3\"};\n\n // Tuple 2 with string elements\n\n const char *tuple2[] = {\"1\", \"Raju\", \"2\", \"Nikhil\", \"3\", \"Deepanshu\"};\n\n\n\n // Get the size of the tuples by the number of elements\n\n size_t tuple1_size = sizeof(tuple1) / sizeof(tuple1[0]); // Number of elements in tuple1\n\n size_t tuple2_size = sizeof(tuple2) / sizeof(tuple2[0]); // Number of elements in tuple2\n\n\n\n // Assert the sizes are correct\n\n assert(func0(tuple1, tuple1_size) == sizeof(tuple1));\n\n assert(func0(tuple2, tuple2_size) == sizeof(tuple2));\n\n\n\n printf(\"Assertions passed!\\n\");\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmovq $0x0,-0x10(%rbp)\nmovq $0x0,-0x8(%rbp)\njmp 11b5 \naddq $0x8,-0x10(%rbp)\naddq $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%rax\ncmp -0x20(%rbp),%rax\njb 11ab \nmov -0x10(%rbp),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_10], 0\nmov [rbp+var_8], 0\njmp short loc_11B5\nloc_11AB:\nadd [rbp+var_10], 8\nadd [rbp+var_8], 1\nloc_11B5:\nmov rax, [rbp+var_8]\ncmp rax, [rbp+var_20]\njb short loc_11AB\nmov rax, [rbp+var_10]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, unsigned __int64 a2)\n{\n __int64 v3; // [rsp+10h] [rbp-10h]\n unsigned __int64 i; // [rsp+18h] [rbp-8h]\n\n v3 = 0LL;\n for ( i = 0LL; i < a2; ++i )\n v3 += 8LL;\n return v3;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_10], 0\nmov [rbp+var_8], 0\njmp short loc_11B5\nloc_11AB:\nadd [rbp+var_10], 8\nadd [rbp+var_8], 1\nloc_11B5:\nmov rax, [rbp+var_8]\ncmp rax, [rbp+var_20]\njb short loc_11AB\nmov rax, [rbp+var_10]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, unsigned __int64 a2)\n{\n __int64 v3; // [rsp+10h] [rbp-10h]\n unsigned __int64 i; // [rsp+18h] [rbp-8h]\n\n v3 = 0LL;\n for ( i = 0LL; i < a2; ++i )\n v3 += 8LL;\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, unsigned long long a2) {\n long long v3;\n unsigned long long i;\n v3 = 0LL;\n for (i = 0LL; i < a2; ++i) v3 += 8LL;\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, unsigned long long a2) {\n long long v3;\n unsigned long long i;\n v3 = 0LL;\n for (i = 0LL; i < a2; ++i) v3 += 8LL;\n return v3;\n}" + }, + { + "index": 597, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr1[], int arr2[], int m, int n, int k) {\n int sorted1[m + n];\n int i = 0, j = 0, d = 0;\n while (i < m && j < n) {\n if (arr1[i] < arr2[j]) {\n sorted1[d] = arr1[i];\n i++;\n } else {\n sorted1[d] = arr2[j];\n j++;\n }\n d++;\n }\n while (i < m) {\n sorted1[d] = arr1[i];\n d++;\n i++;\n }\n while (j < n) {\n sorted1[d] = arr2[j];\n d++;\n j++;\n }\n return sorted1[k - 1];\n}", + "test": "int main() {\n\n int arr1_1[] = {2, 3, 6, 7, 9};\n\n int arr2_1[] = {1, 4, 8, 10};\n\n int arr1_2[] = {100, 112, 256, 349, 770};\n\n int arr2_2[] = {72, 86, 113, 119, 265, 445, 892};\n\n int arr1_3[] = {3, 4, 7, 8, 10};\n\n int arr2_3[] = {2, 5, 9, 11};\n\n\n\n assert(func0(arr1_1, arr2_1, 5, 4, 5) == 6);\n\n assert(func0(arr1_2, arr2_2, 5, 7, 7) == 256);\n\n assert(func0(arr1_3, arr2_3, 5, 4, 6) == 8);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r13\npush %r12\nsub $0x50,%rsp\nmov %rdi,-0x48(%rbp)\nmov %rsi,-0x50(%rbp)\nmov %edx,-0x54(%rbp)\nmov %ecx,-0x58(%rbp)\nmov %r8d,-0x5c(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmov %rsp,%rax\nmov %rax,%rsi\nmov -0x54(%rbp),%edx\nmov -0x58(%rbp),%eax\nadd %edx,%eax\nmovslq %eax,%rdx\nsub $0x1,%rdx\nmov %rdx,-0x28(%rbp)\nmovslq %eax,%rdx\nmov %rdx,%r12\nmov $0x0,%r13d\nmovslq %eax,%rdx\nmov %rdx,%r10\nmov $0x0,%r11d\ncltq\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%edi\nmov $0x0,%edx\ndiv %rdi\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rdi\nsub %rdx,%rdi\nmov %rdi,%rdx\ncmp %rdx,%rsp\nje 121c \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 1205 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 1246 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x20(%rbp)\nmovl $0x0,-0x30(%rbp)\nmovl $0x0,-0x34(%rbp)\nmovl $0x0,-0x2c(%rbp)\njmpq 12f7 \nmov -0x30(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x34(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x50(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njge 12cc \nmov -0x30(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%ecx\nmov -0x20(%rbp),%rax\nmov -0x2c(%rbp),%edx\nmovslq %edx,%rdx\nmov %ecx,(%rax,%rdx,4)\naddl $0x1,-0x30(%rbp)\njmp 12f3 \nmov -0x34(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x50(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%ecx\nmov -0x20(%rbp),%rax\nmov -0x2c(%rbp),%edx\nmovslq %edx,%rdx\nmov %ecx,(%rax,%rdx,4)\naddl $0x1,-0x34(%rbp)\naddl $0x1,-0x2c(%rbp)\nmov -0x30(%rbp),%eax\ncmp -0x54(%rbp),%eax\njge 1338 \nmov -0x34(%rbp),%eax\ncmp -0x58(%rbp),%eax\njl 1273 \njmp 1338 \nmov -0x30(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%ecx\nmov -0x20(%rbp),%rax\nmov -0x2c(%rbp),%edx\nmovslq %edx,%rdx\nmov %ecx,(%rax,%rdx,4)\naddl $0x1,-0x2c(%rbp)\naddl $0x1,-0x30(%rbp)\nmov -0x30(%rbp),%eax\ncmp -0x54(%rbp),%eax\njl 130d \njmp 136d \nmov -0x34(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x50(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%ecx\nmov -0x20(%rbp),%rax\nmov -0x2c(%rbp),%edx\nmovslq %edx,%rdx\nmov %ecx,(%rax,%rdx,4)\naddl $0x1,-0x2c(%rbp)\naddl $0x1,-0x34(%rbp)\nmov -0x34(%rbp),%eax\ncmp -0x58(%rbp),%eax\njl 1342 \nmov -0x5c(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x20(%rbp),%rax\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nmov %rsi,%rsp\nmov -0x18(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 139c \ncallq 1060 <__stack_chk_fail@plt>\nlea -0x10(%rbp),%rsp\npop %r12\npop %r13\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+var_38], rdi\nmov [rbp+var_40], rsi\nmov [rbp+var_44], edx\nmov [rbp+var_48], ecx\nmov [rbp+var_4C], r8d\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov edx, [rbp+var_44]\nmov eax, [rbp+var_48]\nadd eax, edx\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11E6:\ncmp rsp, rdx\njz short loc_11FD\nsub rsp, 1000h\nor [rsp+1050h+var_58], 0\njmp short loc_11E6\nloc_11FD:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1227\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1227:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov [rbp+var_24], 0\nmov [rbp+var_20], 0\nmov [rbp+var_1C], 0\njmp loc_12D8\nloc_1254:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_20]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njge short loc_12AD\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov ecx, [rax]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nadd [rbp+var_24], 1\njmp short loc_12D4\nloc_12AD:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nadd rax, rdx\nmov ecx, [rax]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nadd [rbp+var_20], 1\nloc_12D4:\nadd [rbp+var_1C], 1\nloc_12D8:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_44]\njge short loc_1319\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_48]\njl loc_1254\njmp short loc_1319\nloc_12EE:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov ecx, [rax]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nadd [rbp+var_1C], 1\nadd [rbp+var_24], 1\nloc_1319:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_44]\njl short loc_12EE\njmp short loc_134E\nloc_1323:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nadd rax, rdx\nmov ecx, [rax]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nadd [rbp+var_1C], 1\nadd [rbp+var_20], 1\nloc_134E:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_48]\njl short loc_1323\nmov eax, [rbp+var_4C]\nlea edx, [rax-1]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_137D\ncall ___stack_chk_fail\nlocret_137D:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3, int a4, int a5)\n{\n unsigned __int64 v5; // rax\n void *v6; // rsp\n _BYTE v8[4]; // [rsp+8h] [rbp-50h] BYREF\n int v9; // [rsp+Ch] [rbp-4Ch]\n int v10; // [rsp+10h] [rbp-48h]\n int v11; // [rsp+14h] [rbp-44h]\n __int64 v12; // [rsp+18h] [rbp-40h]\n __int64 v13; // [rsp+20h] [rbp-38h]\n int v14; // [rsp+34h] [rbp-24h]\n int v15; // [rsp+38h] [rbp-20h]\n int v16; // [rsp+3Ch] [rbp-1Ch]\n __int64 v17; // [rsp+40h] [rbp-18h]\n _BYTE *v18; // [rsp+48h] [rbp-10h]\n unsigned __int64 v19; // [rsp+50h] [rbp-8h]\n\n v13 = a1;\n v12 = a2;\n v11 = a3;\n v10 = a4;\n v9 = a5;\n v19 = __readfsqword(0x28u);\n v17 = a3 + a4 - 1LL;\n v5 = 16 * ((4LL * (a3 + a4) + 15) / 0x10uLL);\n while ( v8 != &v8[-(v5 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v6 = alloca(v5 & 0xFFF);\n if ( (v5 & 0xFFF) != 0 )\n *(_QWORD *)&v8[(v5 & 0xFFF) - 8] = *(_QWORD *)&v8[(v5 & 0xFFF) - 8];\n v18 = v8;\n v14 = 0;\n v15 = 0;\n v16 = 0;\n while ( v14 < v11 && v15 < v10 )\n {\n if ( *(_DWORD *)(4LL * v14 + v13) >= *(_DWORD *)(4LL * v15 + v12) )\n *(_DWORD *)&v18[4 * v16] = *(_DWORD *)(4LL * v15++ + v12);\n else\n *(_DWORD *)&v18[4 * v16] = *(_DWORD *)(4LL * v14++ + v13);\n ++v16;\n }\n while ( v14 < v11 )\n *(_DWORD *)&v18[4 * v16++] = *(_DWORD *)(4LL * v14++ + v13);\n while ( v15 < v10 )\n *(_DWORD *)&v18[4 * v16++] = *(_DWORD *)(4LL * v15++ + v12);\n return *(unsigned int *)&v18[4 * v9 - 4];\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+var_38], rdi\nmov [rbp+var_40], rsi\nmov [rbp+var_44], edx\nmov [rbp+var_48], ecx\nmov [rbp+var_4C], r8d\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov edx, [rbp+var_44]\nmov eax, [rbp+var_48]\nadd eax, edx\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11E6:\ncmp rsp, rdx\njz short loc_11FD\nsub rsp, 1000h\nor [rsp+1050h+var_58], 0\njmp short loc_11E6\nloc_11FD:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1227\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1227:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov [rbp+var_24], 0\nmov [rbp+var_20], 0\nmov [rbp+var_1C], 0\njmp loc_12D8\nloc_1254:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_20]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njge short loc_12AD\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov ecx, [rax]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nadd [rbp+var_24], 1\njmp short loc_12D4\nloc_12AD:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nadd rax, rdx\nmov ecx, [rax]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nadd [rbp+var_20], 1\nloc_12D4:\nadd [rbp+var_1C], 1\nloc_12D8:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_44]\njge short loc_1319\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_48]\njl loc_1254\njmp short loc_1319\nloc_12EE:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov ecx, [rax]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nadd [rbp+var_1C], 1\nadd [rbp+var_24], 1\nloc_1319:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_44]\njl short loc_12EE\njmp short loc_134E\nloc_1323:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nadd rax, rdx\nmov ecx, [rax]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nadd [rbp+var_1C], 1\nadd [rbp+var_20], 1\nloc_134E:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_48]\njl short loc_1323\nmov eax, [rbp+var_4C]\nlea edx, [rax-1]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_137D\ncall ___stack_chk_fail\nlocret_137D:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, int a3, int a4, int a5)\n{\n unsigned __int64 v5; // rax\n void *v6; // rsp\n _BYTE v8[4]; // [rsp+8h] [rbp-50h] BYREF\n int v9; // [rsp+Ch] [rbp-4Ch]\n int v10; // [rsp+10h] [rbp-48h]\n int v11; // [rsp+14h] [rbp-44h]\n __int64 v12; // [rsp+18h] [rbp-40h]\n __int64 v13; // [rsp+20h] [rbp-38h]\n int v14; // [rsp+34h] [rbp-24h]\n int v15; // [rsp+38h] [rbp-20h]\n int v16; // [rsp+3Ch] [rbp-1Ch]\n __int64 v17; // [rsp+40h] [rbp-18h]\n _BYTE *v18; // [rsp+48h] [rbp-10h]\n unsigned __int64 v19; // [rsp+50h] [rbp-8h]\n\n v13 = a1;\n v12 = a2;\n v11 = a3;\n v10 = a4;\n v9 = a5;\n v19 = __readfsqword(0x28u);\n v17 = a3 + a4 - 1LL;\n v5 = 16 * ((4LL * (a3 + a4) + 15) / 0x10uLL);\n while ( v8 != &v8[-(v5 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v6 = alloca(v5 & 0xFFF);\n if ( (v5 & 0xFFF) != 0 )\n *(_QWORD *)&v8[(v5 & 0xFFF) - 8] = *(_QWORD *)&v8[(v5 & 0xFFF) - 8];\n v18 = v8;\n v14 = 0;\n v15 = 0;\n v16 = 0;\n while ( v14 < v11 && v15 < v10 )\n {\n if ( *(_DWORD *)(4LL * v14 + v13) >= *(_DWORD *)(4LL * v15 + v12) )\n *(_DWORD *)&v18[4 * v16] = *(_DWORD *)(4LL * v15++ + v12);\n else\n *(_DWORD *)&v18[4 * v16] = *(_DWORD *)(4LL * v14++ + v13);\n ++v16;\n }\n while ( v14 < v11 )\n *(_DWORD *)&v18[4 * v16++] = *(_DWORD *)(4LL * v14++ + v13);\n while ( v15 < v10 )\n *(_DWORD *)&v18[4 * v16++] = *(_DWORD *)(4LL * v15++ + v12);\n return *(unsigned int *)&v18[4 * v9 - 4];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, int a3, int a4, int a5) {\n unsigned long long v5;\n void *v6;\n uint8_t v8[4];\n int v9;\n int v10;\n int v11;\n long long v12;\n long long v13;\n int v14;\n int v15;\n int v16;\n long long v17;\n uint8_t *v18;\n unsigned long long v19;\n v13 = a1;\n v12 = a2;\n v11 = a3;\n v10 = a4;\n v9 = a5;\n v19 = __readfsqword(40u);\n v17 = a3 + a4 - 1LL;\n v5 = 16 * ((4LL * (a3 + a4) + 15) / 16uLL);\n while (v8 != &v8[-(v5 & 18446744073709547520LL)])\n ;\n v6 = alloca(v5 & 4095);\n if ((v5 & 4095) != 0)\n *(uint64_t *)&v8[(v5 & 4095) - 8] = *(uint64_t *)&v8[(v5 & 4095) - 8];\n v18 = v8;\n v14 = 0;\n v15 = 0;\n v16 = 0;\n while (v14 < v11 && v15 < v10) {\n if (*(uint32_t *)(4LL * v14 + v13) >= *(uint32_t *)(4LL * v15 + v12))\n *(uint32_t *)&v18[4 * v16] = *(uint32_t *)(4LL * v15++ + v12);\n else\n *(uint32_t *)&v18[4 * v16] = *(uint32_t *)(4LL * v14++ + v13);\n ++v16;\n }\n while (v14 < v11)\n *(uint32_t *)&v18[4 * v16++] = *(uint32_t *)(4LL * v14++ + v13);\n while (v15 < v10)\n *(uint32_t *)&v18[4 * v16++] = *(uint32_t *)(4LL * v15++ + v12);\n return *(unsigned int *)&v18[4 * v9 - 4];\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3, int a4, int a5) {\n unsigned long long v5;\n void *v6;\n uint8_t v8[4];\n int v9;\n int v10;\n int v11;\n long long v12;\n long long v13;\n int v14;\n int v15;\n int v16;\n long long v17;\n uint8_t *v18;\n unsigned long long v19;\n v13 = a1;\n v12 = a2;\n v11 = a3;\n v10 = a4;\n v9 = a5;\n v19 = __readfsqword(40u);\n v17 = a3 + a4 - 1LL;\n v5 = 16 * ((4LL * (a3 + a4) + 15) / 16uLL);\n while (v8 != &v8[-(v5 & 18446744073709547520LL)])\n ;\n v6 = alloca(v5 & 4095);\n if ((v5 & 4095) != 0)\n *(uint64_t *)&v8[(v5 & 4095) - 8] = *(uint64_t *)&v8[(v5 & 4095) - 8];\n v18 = v8;\n v14 = 0;\n v15 = 0;\n v16 = 0;\n while (v14 < v11 && v15 < v10) {\n if (*(uint32_t *)(4LL * v14 + v13) >= *(uint32_t *)(4LL * v15 + v12))\n *(uint32_t *)&v18[4 * v16] = *(uint32_t *)(4LL * v15++ + v12);\n else\n *(uint32_t *)&v18[4 * v16] = *(uint32_t *)(4LL * v14++ + v13);\n ++v16;\n }\n while (v14 < v11)\n *(uint32_t *)&v18[4 * v16++] = *(uint32_t *)(4LL * v14++ + v13);\n while (v15 < v10)\n *(uint32_t *)&v18[4 * v16++] = *(uint32_t *)(4LL * v15++ + v12);\n return *(unsigned int *)&v18[4 * v9 - 4];\n}" + }, + { + "index": 597, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr1[], int arr2[], int m, int n, int k) {\n int sorted1[m + n];\n int i = 0, j = 0, d = 0;\n while (i < m && j < n) {\n if (arr1[i] < arr2[j]) {\n sorted1[d] = arr1[i];\n i++;\n } else {\n sorted1[d] = arr2[j];\n j++;\n }\n d++;\n }\n while (i < m) {\n sorted1[d] = arr1[i];\n d++;\n i++;\n }\n while (j < n) {\n sorted1[d] = arr2[j];\n d++;\n j++;\n }\n return sorted1[k - 1];\n}", + "test": "int main() {\n\n int arr1_1[] = {2, 3, 6, 7, 9};\n\n int arr2_1[] = {1, 4, 8, 10};\n\n int arr1_2[] = {100, 112, 256, 349, 770};\n\n int arr2_2[] = {72, 86, 113, 119, 265, 445, 892};\n\n int arr1_3[] = {3, 4, 7, 8, 10};\n\n int arr2_3[] = {2, 5, 9, 11};\n\n\n\n assert(func0(arr1_1, arr2_1, 5, 4, 5) == 6);\n\n assert(func0(arr1_2, arr2_2, 5, 7, 7) == 256);\n\n assert(func0(arr1_3, arr2_3, 5, 4, 6) == 8);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r13\npush %r12\npush %rbx\nsub $0x18,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x28(%rbp)\nxor %eax,%eax\nlea (%rdx,%rcx,1),%eax\ncltq\nlea 0xf(,%rax,4),%rax\nmov %rax,%r9\nand $0xfffffffffffffff0,%r9\nand $0xfffffffffffff000,%rax\nmov %rsp,%rbx\nsub %rax,%rbx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 11c3 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11ac \nmov %r9,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 11d9 \norq $0x0,-0x8(%rsp,%rax,1)\nmov %rsp,%r12\nmov %r12,%r13\ntest %edx,%edx\njle 122d \ntest %ecx,%ecx\njle 122d \nmov $0x1,%r9d\nmov $0x0,%r11d\nmov $0x0,%eax\njmp 1215 \nadd $0x1,%eax\nmov %ebx,%r10d\nmov %r10d,-0x4(%r13,%r9,4)\nmov %r9d,%ebx\nadd $0x1,%r9\ncmp %edx,%r11d\njge 123d \ncmp %ecx,%eax\njge 123d \nmovslq %r11d,%r10\nmov (%rdi,%r10,4),%r10d\nmovslq %eax,%rbx\nmov (%rsi,%rbx,4),%ebx\ncmp %ebx,%r10d\njge 11fa \nadd $0x1,%r11d\njmp 1200 \nmov $0x0,%ebx\nmov $0x0,%r11d\nmov $0x0,%eax\ncmp %r11d,%edx\njle 1268 \nmovslq %r11d,%r9\nmovslq %ebx,%r10\nsub %r9,%r10\nlea (%r12,%r10,4),%r13\nmov (%rdi,%r9,4),%r10d\nmov %r10d,0x0(%r13,%r9,4)\nadd $0x1,%r9\ncmp %r9d,%edx\njg 124f \nadd %ebx,%edx\nsub %r11d,%edx\nmov %edx,%ebx\ncmp %eax,%ecx\njle 1286 \ncltq\nmovslq %ebx,%rdx\nsub %rax,%rdx\nlea (%r12,%rdx,4),%rdi\nmov (%rsi,%rax,4),%edx\nmov %edx,(%rdi,%rax,4)\nadd $0x1,%rax\ncmp %eax,%ecx\njg 1278 \nsub $0x1,%r8d\nmovslq %r8d,%r8\nmov (%r12,%r8,4),%eax\nmov -0x28(%rbp),%rsi\nxor %fs:0x28,%rsi\njne 12ab \nlea -0x18(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %rbp\nretq\ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 10h\nmov r10, rdi\nmov r9, rsi\nmov edi, edx\nmov ebx, ecx\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nlea eax, [rdx+rcx]\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11B5:\ncmp rsp, rdx\njz short loc_11CC\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\njmp short loc_11B5\nloc_11CC:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11E2\nor [rsp+rax+30h+var_38], 0\nloc_11E2:\nmov r11, rsp\ntest edi, edi\njle short loc_1230\ntest ebx, ebx\njle short loc_1230\nmov ecx, 1\nmov esi, 0\nmov eax, 0\njmp short loc_1218\nloc_11FE:\nadd esi, 1\nmov edx, r12d\nloc_1204:\nmov [r11+rcx*4-4], edx\nlea rdx, [rcx+1]\ncmp eax, edi\njge short loc_123F\ncmp esi, ebx\njge short loc_123F\nmov rcx, rdx\nloc_1218:\nmovsxd rdx, eax\nmov edx, [r10+rdx*4]\nmovsxd r12, esi\nmov r12d, [r9+r12*4]\ncmp edx, r12d\njge short loc_11FE\nadd eax, 1\njmp short loc_1204\nloc_1230:\nmov ecx, 0\nmov esi, 0\nmov eax, 0\nloc_123F:\ncmp edi, eax\njle short loc_127A\nmov r12d, eax\nmov r13d, edi\nsub r13d, eax\nshl r13, 2\ncdqe\nlea r14, [r10+rax*4]\nmovsxd rax, ecx\nlea r10, [r11+rax*4]\nmov eax, 0\nloc_1262:\nmov edx, [r14+rax]\nmov [r10+rax], edx\nadd rax, 4\ncmp rax, r13\njnz short loc_1262\nadd edi, ecx\nsub edi, r12d\nmov ecx, edi\nloc_127A:\ncmp ebx, esi\njle short loc_12A6\nsub ebx, esi\nshl rbx, 2\nmovsxd rax, esi\nlea rsi, [r9+rax*4]\nmovsxd rcx, ecx\nlea rcx, [r11+rcx*4]\nmov eax, 0\nloc_1297:\nmov edx, [rsi+rax]\nmov [rcx+rax], edx\nadd rax, 4\ncmp rax, rbx\njnz short loc_1297\nloc_12A6:\nsub r8d, 1\nmovsxd r8, r8d\nmov eax, [r11+r8*4]\nmov rdx, [rbp+var_28]\nsub rdx, fs:28h\njnz short loc_12CD\nlea rsp, [rbp-20h]\npop rbx\npop r12\npop r13\npop r14\npop rbp\nretn\nloc_12CD:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3, int a4, int a5)\n{\n __int64 v9; // rax\n __int16 v10; // cx\n signed __int64 v11; // rax\n void *v12; // rsp\n __int64 v13; // rcx\n int v14; // esi\n int v15; // eax\n int v16; // edx\n int v17; // r12d\n int v18; // r12d\n __int64 v19; // r13\n __int64 v20; // r14\n unsigned __int64 v21; // rax\n __int64 v22; // rbx\n __int64 v23; // rsi\n _DWORD *v24; // rcx\n unsigned __int64 v25; // rax\n _DWORD v28[2]; // [rsp+8h] [rbp-30h] BYREF\n unsigned __int64 v29; // [rsp+10h] [rbp-28h]\n\n v29 = __readfsqword(0x28u);\n v9 = 4LL * (a3 + a4) + 15;\n v10 = (4 * (a3 + a4) + 15) & 0xFFF0;\n while ( v28 != (_DWORD *)((char *)v28 - (v9 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v11 = v10 & 0xFFF;\n v12 = alloca(v11);\n if ( (v10 & 0xFFF) != 0 )\n *(_QWORD *)((char *)&v28[-2] + v11) = *(_QWORD *)((char *)&v28[-2] + v11);\n if ( a3 <= 0 || a4 <= 0 )\n {\n LODWORD(v13) = 0;\n v14 = 0;\n v15 = 0;\n }\n else\n {\n v13 = 1LL;\n v14 = 0;\n v15 = 0;\n while ( 1 )\n {\n v16 = *(_DWORD *)(a1 + 4LL * v15);\n v17 = *(_DWORD *)(a2 + 4LL * v14);\n if ( v16 >= v17 )\n {\n ++v14;\n v16 = v17;\n }\n else\n {\n ++v15;\n }\n v28[v13 - 1] = v16;\n if ( v15 >= a3 || v14 >= a4 )\n break;\n ++v13;\n }\n }\n if ( a3 > v15 )\n {\n v18 = v15;\n v19 = 4LL * (unsigned int)(a3 - v15);\n v20 = a1 + 4LL * v15;\n v21 = 0LL;\n do\n {\n v28[(int)v13 + v21 / 4] = *(_DWORD *)(v20 + v21);\n v21 += 4LL;\n }\n while ( v21 != v19 );\n LODWORD(v13) = v13 + a3 - v18;\n }\n if ( a4 > v14 )\n {\n v22 = 4LL * (unsigned int)(a4 - v14);\n v23 = a2 + 4LL * v14;\n v24 = &v28[(int)v13];\n v25 = 0LL;\n do\n {\n v24[v25 / 4] = *(_DWORD *)(v23 + v25);\n v25 += 4LL;\n }\n while ( v25 != v22 );\n }\n return (unsigned int)v28[a5 - 1];\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 10h\nmov r10, rdi\nmov r9, rsi\nmov edi, edx\nmov ebx, ecx\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nlea eax, [rdx+rcx]\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11B5:\ncmp rsp, rdx\njz short loc_11CC\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\njmp short loc_11B5\nloc_11CC:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11E2\nor [rsp+rax+30h+var_38], 0\nloc_11E2:\nmov r11, rsp\ntest edi, edi\njle short loc_1230\ntest ebx, ebx\njle short loc_1230\nmov ecx, 1\nmov esi, 0\nmov eax, 0\njmp short loc_1218\nloc_11FE:\nadd esi, 1\nmov edx, r12d\nloc_1204:\nmov [r11+rcx*4-4], edx\nlea rdx, [rcx+1]\ncmp eax, edi\njge short loc_123F\ncmp esi, ebx\njge short loc_123F\nmov rcx, rdx\nloc_1218:\nmovsxd rdx, eax\nmov edx, [r10+rdx*4]\nmovsxd r12, esi\nmov r12d, [r9+r12*4]\ncmp edx, r12d\njge short loc_11FE\nadd eax, 1\njmp short loc_1204\nloc_1230:\nmov ecx, 0\nmov esi, 0\nmov eax, 0\nloc_123F:\ncmp edi, eax\njle short loc_127A\nmov r12d, eax\nmov r13d, edi\nsub r13d, eax\nshl r13, 2\ncdqe\nlea r14, [r10+rax*4]\nmovsxd rax, ecx\nlea r10, [r11+rax*4]\nmov eax, 0\nloc_1262:\nmov edx, [r14+rax]\nmov [r10+rax], edx\nadd rax, 4\ncmp rax, r13\njnz short loc_1262\nadd edi, ecx\nsub edi, r12d\nmov ecx, edi\nloc_127A:\ncmp ebx, esi\njle short loc_12A6\nsub ebx, esi\nshl rbx, 2\nmovsxd rax, esi\nlea rsi, [r9+rax*4]\nmovsxd rcx, ecx\nlea rcx, [r11+rcx*4]\nmov eax, 0\nloc_1297:\nmov edx, [rsi+rax]\nmov [rcx+rax], edx\nadd rax, 4\ncmp rax, rbx\njnz short loc_1297\nloc_12A6:\nsub r8d, 1\nmovsxd r8, r8d\nmov eax, [r11+r8*4]\nmov rdx, [rbp+var_28]\nsub rdx, fs:28h\njnz short loc_12CD\nlea rsp, [rbp-20h]\npop rbx\npop r12\npop r13\npop r14\npop rbp\nretn\nloc_12CD:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, int a3, int a4, int a5)\n{\n __int64 v9; // rax\n __int16 v10; // cx\n signed __int64 v11; // rax\n void *v12; // rsp\n __int64 v13; // rcx\n int v14; // esi\n int v15; // eax\n int v16; // edx\n int v17; // r12d\n int v18; // r12d\n __int64 v19; // r13\n __int64 v20; // r14\n unsigned __int64 v21; // rax\n __int64 v22; // rbx\n __int64 v23; // rsi\n _DWORD *v24; // rcx\n unsigned __int64 v25; // rax\n _DWORD v28[2]; // [rsp+8h] [rbp-30h] BYREF\n unsigned __int64 v29; // [rsp+10h] [rbp-28h]\n\n v29 = __readfsqword(0x28u);\n v9 = 4LL * (a3 + a4) + 15;\n v10 = (4 * (a3 + a4) + 15) & 0xFFF0;\n while ( v28 != (_DWORD *)((char *)v28 - (v9 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v11 = v10 & 0xFFF;\n v12 = alloca(v11);\n if ( (v10 & 0xFFF) != 0 )\n *(_QWORD *)((char *)&v28[-2] + v11) = *(_QWORD *)((char *)&v28[-2] + v11);\n if ( a3 <= 0 || a4 <= 0 )\n {\n LODWORD(v13) = 0;\n v14 = 0;\n v15 = 0;\n }\n else\n {\n v13 = 1LL;\n v14 = 0;\n v15 = 0;\n while ( 1 )\n {\n v16 = *(_DWORD *)(a1 + 4LL * v15);\n v17 = *(_DWORD *)(a2 + 4LL * v14);\n if ( v16 >= v17 )\n {\n ++v14;\n v16 = v17;\n }\n else\n {\n ++v15;\n }\n v28[v13 - 1] = v16;\n if ( v15 >= a3 || v14 >= a4 )\n break;\n ++v13;\n }\n }\n if ( a3 > v15 )\n {\n v18 = v15;\n v19 = 4LL * (unsigned int)(a3 - v15);\n v20 = a1 + 4LL * v15;\n v21 = 0LL;\n do\n {\n v28[(int)v13 + v21 / 4] = *(_DWORD *)(v20 + v21);\n v21 += 4LL;\n }\n while ( v21 != v19 );\n LODWORD(v13) = v13 + a3 - v18;\n }\n if ( a4 > v14 )\n {\n v22 = 4LL * (unsigned int)(a4 - v14);\n v23 = a2 + 4LL * v14;\n v24 = &v28[(int)v13];\n v25 = 0LL;\n do\n {\n v24[v25 / 4] = *(_DWORD *)(v23 + v25);\n v25 += 4LL;\n }\n while ( v25 != v22 );\n }\n return (unsigned int)v28[a5 - 1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, int a3, int a4, int a5) {\n long long v9;\n short v10;\n signed long long v11;\n void *v12;\n long long v13;\n int v14;\n int v15;\n int v16;\n int v17;\n int v18;\n long long v19;\n long long v20;\n unsigned long long v21;\n long long v22;\n long long v23;\n uint32_t *v24;\n unsigned long long v25;\n uint32_t v28[2];\n unsigned long long v29;\n v29 = __readfsqword(40u);\n v9 = 4LL * (a3 + a4) + 15;\n v10 = (4 * (a3 + a4) + 15) & 65520;\n while (v28 != (uint32_t *)((char *)v28 - (v9 & 18446744073709547520LL)))\n ;\n v11 = v10 & 4095;\n v12 = alloca(v11);\n if ((v10 & 4095) != 0)\n *(uint64_t *)((char *)&v28[-2] + v11) =\n *(uint64_t *)((char *)&v28[-2] + v11);\n if (a3 <= 0 || a4 <= 0) {\n LODWORD(v13) = 0;\n v14 = 0;\n v15 = 0;\n } else {\n v13 = 1LL;\n v14 = 0;\n v15 = 0;\n while (1) {\n v16 = *(uint32_t *)(a1 + 4LL * v15);\n v17 = *(uint32_t *)(a2 + 4LL * v14);\n if (v16 >= v17) {\n ++v14;\n v16 = v17;\n } else {\n ++v15;\n }\n v28[v13 - 1] = v16;\n if (v15 >= a3 || v14 >= a4) break;\n ++v13;\n }\n }\n if (a3 > v15) {\n v18 = v15;\n v19 = 4LL * (unsigned int)(a3 - v15);\n v20 = a1 + 4LL * v15;\n v21 = 0LL;\n do {\n v28[(int)v13 + v21 / 4] = *(uint32_t *)(v20 + v21);\n v21 += 4LL;\n } while (v21 != v19);\n LODWORD(v13) = v13 + a3 - v18;\n }\n if (a4 > v14) {\n v22 = 4LL * (unsigned int)(a4 - v14);\n v23 = a2 + 4LL * v14;\n v24 = &v28[(int)v13];\n v25 = 0LL;\n do {\n v24[v25 / 4] = *(uint32_t *)(v23 + v25);\n v25 += 4LL;\n } while (v25 != v22);\n }\n return (unsigned int)v28[a5 - 1];\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3, int a4, int a5) {\n long long v9;\n short v10;\n signed long long v11;\n void *v12;\n long long v13;\n int v14;\n int v15;\n int v16;\n int v17;\n int v18;\n long long v19;\n long long v20;\n unsigned long long v21;\n long long v22;\n long long v23;\n uint32_t *v24;\n unsigned long long v25;\n uint32_t v28[2];\n unsigned long long v29;\n v29 = __readfsqword(40u);\n v9 = 4LL * (a3 + a4) + 15;\n v10 = (4 * (a3 + a4) + 15) & 65520;\n while (v28 != (uint32_t *)((char *)v28 - (v9 & 18446744073709547520LL)))\n ;\n v11 = v10 & 4095;\n v12 = alloca(v11);\n if ((v10 & 4095) != 0)\n *(uint64_t *)((char *)&v28[-2] + v11) =\n *(uint64_t *)((char *)&v28[-2] + v11);\n if (a3 <= 0 || a4 <= 0) {\n LODWORD(v13) = 0;\n v14 = 0;\n v15 = 0;\n } else {\n v13 = 1LL;\n v14 = 0;\n v15 = 0;\n while (1) {\n v16 = *(uint32_t *)(a1 + 4LL * v15);\n v17 = *(uint32_t *)(a2 + 4LL * v14);\n if (v16 >= v17) {\n ++v14;\n v16 = v17;\n } else {\n ++v15;\n }\n v28[v13 - 1] = v16;\n if (v15 >= a3 || v14 >= a4) break;\n ++v13;\n }\n }\n if (a3 > v15) {\n v18 = v15;\n v19 = 4LL * (unsigned int)(a3 - v15);\n v20 = a1 + 4LL * v15;\n v21 = 0LL;\n do {\n v28[(int)v13 + v21 / 4] = *(uint32_t *)(v20 + v21);\n v21 += 4LL;\n } while (v21 != v19);\n LODWORD(v13) = v13 + a3 - v18;\n }\n if (a4 > v14) {\n v22 = 4LL * (unsigned int)(a4 - v14);\n v23 = a2 + 4LL * v14;\n v24 = &v28[(int)v13];\n v25 = 0LL;\n do {\n v24[v25 / 4] = *(uint32_t *)(v23 + v25);\n v25 += 4LL;\n } while (v25 != v22);\n }\n return (unsigned int)v28[a5 - 1];\n}" + }, + { + "index": 597, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr1[], int arr2[], int m, int n, int k) {\n int sorted1[m + n];\n int i = 0, j = 0, d = 0;\n while (i < m && j < n) {\n if (arr1[i] < arr2[j]) {\n sorted1[d] = arr1[i];\n i++;\n } else {\n sorted1[d] = arr2[j];\n j++;\n }\n d++;\n }\n while (i < m) {\n sorted1[d] = arr1[i];\n d++;\n i++;\n }\n while (j < n) {\n sorted1[d] = arr2[j];\n d++;\n j++;\n }\n return sorted1[k - 1];\n}", + "test": "int main() {\n\n int arr1_1[] = {2, 3, 6, 7, 9};\n\n int arr2_1[] = {1, 4, 8, 10};\n\n int arr1_2[] = {100, 112, 256, 349, 770};\n\n int arr2_2[] = {72, 86, 113, 119, 265, 445, 892};\n\n int arr1_3[] = {3, 4, 7, 8, 10};\n\n int arr2_3[] = {2, 5, 9, 11};\n\n\n\n assert(func0(arr1_1, arr2_1, 5, 4, 5) == 6);\n\n assert(func0(arr1_2, arr2_2, 5, 7, 7) == 256);\n\n assert(func0(arr1_3, arr2_3, 5, 4, 6) == 8);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r13\npush %r12\npush %rbx\nsub $0x18,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x28(%rbp)\nxor %eax,%eax\nlea (%rdx,%rcx,1),%eax\nmov %rsp,%rbx\ncltq\nlea 0xf(,%rax,4),%rax\nmov %rax,%r9\nand $0xfffffffffffff000,%rax\nsub %rax,%rbx\nand $0xfffffffffffffff0,%r9\nmov %rbx,%rax\ncmp %rax,%rsp\nje 13cd \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 13b8 \nand $0xfff,%r9d\nsub %r9,%rsp\ntest %r9,%r9\njne 14c0 \nmov %rsp,%r12\ntest %edx,%edx\njle 1433 \ntest %ecx,%ecx\njle 1433 \nmov $0x1,%r9d\nxor %r11d,%r11d\nxor %eax,%eax\njmp 1419 \nnopl 0x0(%rax,%rax,1)\nadd $0x1,%r11d\nmov %r10d,-0x4(%r12,%r9,4)\nmov %r9d,%ebx\nadd $0x1,%r9\ncmp %edx,%r11d\njge 1440 \ncmp %ecx,%eax\njge 1440 \nmovslq %r11d,%r10\nmovslq %eax,%rbx\nmov (%rdi,%r10,4),%r10d\nmov (%rsi,%rbx,4),%ebx\ncmp %ebx,%r10d\njl 1400 \nadd $0x1,%eax\nmov %ebx,%r10d\njmp 1404 \nxor %ebx,%ebx\nxor %r11d,%r11d\nxor %eax,%eax\nnopw 0x0(%rax,%rax,1)\ncmp %r11d,%edx\njle 1471 \nmovslq %r11d,%r9\nmovslq %ebx,%r10\nsub %r9,%r10\nlea (%r12,%r10,4),%r13\nnopw 0x0(%rax,%rax,1)\nmov (%rdi,%r9,4),%r10d\nmov %r10d,0x0(%r13,%r9,4)\nadd $0x1,%r9\ncmp %r9d,%edx\njg 1458 \nadd %ebx,%edx\nsub %r11d,%edx\nmov %edx,%ebx\ncmp %eax,%ecx\njle 1496 \ncltq\nmovslq %ebx,%rdx\nsub %rax,%rdx\nlea (%r12,%rdx,4),%rdi\nnopl 0x0(%rax)\nmov (%rsi,%rax,4),%edx\nmov %edx,(%rdi,%rax,4)\nadd $0x1,%rax\ncmp %eax,%ecx\njg 1488 \nsub $0x1,%r8d\nmov -0x28(%rbp),%rsi\nxor %fs:0x28,%rsi\nmovslq %r8d,%r8\nmov (%r12,%r8,4),%eax\njne 14cb \nlea -0x18(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %rbp\nretq\nnopl 0x0(%rax,%rax,1)\norq $0x0,-0x8(%rsp,%r9,1)\njmpq 13e0 \ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov r9d, edx\nmov rbp, rsp\npush r15\nmov r15, rsi\npush r14\nmov r14d, ecx\npush r13\npush r12\nmov r12d, r8d\npush rbx\nsub rsp, 38h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nlea eax, [rdx+rcx]\nmov rcx, rsp\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_139A\nloc_1385:\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\ncmp rsp, rcx\njnz short loc_1385\nloc_139A:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_14B8\nloc_13AC:\nmov rcx, rsp\ntest r9d, r9d\njle loc_14C3\ntest r14d, r14d\njle loc_14C3\nmov edx, 1\nxor ebx, ebx\nxor r13d, r13d\njmp short loc_13EB\nloc_13D0:\nmov eax, esi\nadd r13d, 1\nmov [rcx+rdx*4-4], eax\nlea rax, [rdx+1]\ncmp r13d, r9d\njge short loc_140C\nloc_13E3:\ncmp ebx, r14d\njge short loc_140C\nmov rdx, rax\nloc_13EB:\nmovsxd rax, r13d\nmov esi, [rdi+rax*4]\nmovsxd rax, ebx\nmov eax, [r15+rax*4]\ncmp esi, eax\njl short loc_13D0\nmov [rcx+rdx*4-4], eax\nadd ebx, 1\nlea rax, [rdx+1]\ncmp r13d, r9d\njl short loc_13E3\nloc_140C:\nmov r8d, edx\nloc_140F:\ncmp r9d, r13d\njle short loc_145A\nmovsxd rax, r8d\nmov [rbp+var_54], r8d\nlea r10, [rcx+rax*4]\nlea eax, [r9-1]\nmov [rbp+var_50], rcx\nsub eax, r13d\nmov dword ptr [rbp+var_48], r9d\nlea rdx, ds:4[rax*4]; n\nmovsxd rax, r13d\nlea rsi, [rdi+rax*4]; src\nmov rdi, r10; dest\ncall _memcpy\nmov r8d, [rbp+var_54]\nmov r9d, dword ptr [rbp+var_48]\nmov rcx, [rbp+var_50]\nadd r9d, r8d\nmov r8d, r9d\nsub r8d, r13d\nloc_145A:\ncmp r14d, ebx\njle short loc_1489\nsub r14d, 1\nmovsxd rdx, r8d\nmovsxd rax, ebx\nmov [rbp+var_48], rcx\nsub r14d, ebx\nlea rdi, [rcx+rdx*4]; dest\nlea rsi, [r15+rax*4]; src\nlea rdx, ds:4[r14*4]; n\ncall _memcpy\nmov rcx, [rbp+var_48]\nloc_1489:\nsub r12d, 1\nmovsxd r12, r12d\nmov eax, [rcx+r12*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_14D0\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_14B8:\nor [rsp+rdx+1060h+var_1068], 0\njmp loc_13AC\nloc_14C3:\nxor r8d, r8d\nxor ebx, ebx\nxor r13d, r13d\njmp loc_140F\nloc_14D0:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3, int a4, int a5)\n{\n __int64 v9; // rdx\n _DWORD *v10; // rcx\n __int16 v11; // dx\n signed __int64 v12; // rdx\n void *v13; // rsp\n _DWORD *v14; // rcx\n __int64 v15; // rdx\n int v16; // ebx\n int v17; // r13d\n __int64 v18; // rax\n int v19; // esi\n int v20; // eax\n int v21; // r8d\n _DWORD v24[1022]; // [rsp+8h] [rbp-1060h] BYREF\n _BYTE v25[12]; // [rsp+1008h] [rbp-60h] BYREF\n int v26; // [rsp+1014h] [rbp-54h]\n _DWORD *v27; // [rsp+1018h] [rbp-50h]\n _DWORD *v28; // [rsp+1020h] [rbp-48h]\n unsigned __int64 v29; // [rsp+1030h] [rbp-38h]\n\n v29 = __readfsqword(0x28u);\n v9 = 4LL * (a3 + a4) + 15;\n v10 = &v25[-(v9 & 0xFFFFFFFFFFFFF000LL)];\n v11 = v9 & 0xFFF0;\n if ( v25 != (_BYTE *)v10 )\n {\n while ( v24 != v10 )\n ;\n }\n v12 = v11 & 0xFFF;\n v13 = alloca(v12);\n if ( v12 )\n *(_QWORD *)((char *)&v24[-2] + v12) = *(_QWORD *)((char *)&v24[-2] + v12);\n v14 = v24;\n if ( a3 > 0 && a4 > 0 )\n {\n v15 = 1LL;\n v16 = 0;\n v17 = 0;\n while ( 1 )\n {\n v19 = *(_DWORD *)(a1 + 4LL * v17);\n v20 = *(_DWORD *)(a2 + 4LL * v16);\n if ( v19 < v20 )\n {\n ++v17;\n v24[v15 - 1] = v19;\n v18 = v15 + 1;\n if ( v17 >= a3 )\n goto LABEL_13;\n }\n else\n {\n v24[v15 - 1] = v20;\n ++v16;\n v18 = v15 + 1;\n if ( v17 >= a3 )\n {\nLABEL_13:\n v21 = v15;\n goto LABEL_14;\n }\n }\n if ( v16 >= a4 )\n goto LABEL_13;\n v15 = v18;\n }\n }\n v21 = 0;\n v16 = 0;\n v17 = 0;\nLABEL_14:\n if ( a3 > v17 )\n {\n v26 = v21;\n v27 = v24;\n LODWORD(v28) = a3;\n memcpy(&v24[v21], (const void *)(a1 + 4LL * v17), 4LL * (unsigned int)(a3 - 1 - v17) + 4);\n v14 = v27;\n v21 = v26 + (_DWORD)v28 - v17;\n }\n if ( a4 > v16 )\n {\n v28 = v14;\n memcpy(&v14[v21], (const void *)(a2 + 4LL * v16), 4LL * (unsigned int)(a4 - 1 - v16) + 4);\n v14 = v28;\n }\n return (unsigned int)v14[a5 - 1];\n}", + "ida_strip_asm": "sub_1330:\nendbr64\npush rbp\nmov r9d, edx\nmov rbp, rsp\npush r15\nmov r15, rsi\npush r14\nmov r14d, ecx\npush r13\npush r12\nmov r12d, r8d\npush rbx\nsub rsp, 38h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nlea eax, [rdx+rcx]\nmov rcx, rsp\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_139A\nloc_1385:\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\ncmp rsp, rcx\njnz short loc_1385\nloc_139A:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_14B8\nloc_13AC:\nmov rcx, rsp\ntest r9d, r9d\njle loc_14C3\ntest r14d, r14d\njle loc_14C3\nmov edx, 1\nxor ebx, ebx\nxor r13d, r13d\njmp short loc_13EB\nloc_13D0:\nmov eax, esi\nadd r13d, 1\nmov [rcx+rdx*4-4], eax\nlea rax, [rdx+1]\ncmp r13d, r9d\njge short loc_140C\nloc_13E3:\ncmp ebx, r14d\njge short loc_140C\nmov rdx, rax\nloc_13EB:\nmovsxd rax, r13d\nmov esi, [rdi+rax*4]\nmovsxd rax, ebx\nmov eax, [r15+rax*4]\ncmp esi, eax\njl short loc_13D0\nmov [rcx+rdx*4-4], eax\nadd ebx, 1\nlea rax, [rdx+1]\ncmp r13d, r9d\njl short loc_13E3\nloc_140C:\nmov r8d, edx\nloc_140F:\ncmp r9d, r13d\njle short loc_145A\nmovsxd rax, r8d\nmov [rbp+var_54], r8d\nlea r10, [rcx+rax*4]\nlea eax, [r9-1]\nmov [rbp+var_50], rcx\nsub eax, r13d\nmov dword ptr [rbp+var_48], r9d\nlea rdx, ds:4[rax*4]; n\nmovsxd rax, r13d\nlea rsi, [rdi+rax*4]; src\nmov rdi, r10; dest\ncall _memcpy\nmov r8d, [rbp+var_54]\nmov r9d, dword ptr [rbp+var_48]\nmov rcx, [rbp+var_50]\nadd r9d, r8d\nmov r8d, r9d\nsub r8d, r13d\nloc_145A:\ncmp r14d, ebx\njle short loc_1489\nsub r14d, 1\nmovsxd rdx, r8d\nmovsxd rax, ebx\nmov [rbp+var_48], rcx\nsub r14d, ebx\nlea rdi, [rcx+rdx*4]; dest\nlea rsi, [r15+rax*4]; src\nlea rdx, ds:4[r14*4]; n\ncall _memcpy\nmov rcx, [rbp+var_48]\nloc_1489:\nsub r12d, 1\nmovsxd r12, r12d\nmov eax, [rcx+r12*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_14D0\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_14B8:\nor [rsp+rdx+1060h+var_1068], 0\njmp loc_13AC\nloc_14C3:\nxor r8d, r8d\nxor ebx, ebx\nxor r13d, r13d\njmp loc_140F\nloc_14D0:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1330(__int64 a1, __int64 a2, int a3, int a4, int a5)\n{\n __int64 v9; // rdx\n _DWORD *v10; // rcx\n __int16 v11; // dx\n signed __int64 v12; // rdx\n void *v13; // rsp\n _DWORD *v14; // rcx\n __int64 v15; // rdx\n int v16; // ebx\n int v17; // r13d\n __int64 v18; // rax\n int v19; // esi\n int v20; // eax\n int v21; // r8d\n _DWORD v24[1022]; // [rsp+8h] [rbp-1060h] BYREF\n _BYTE v25[12]; // [rsp+1008h] [rbp-60h] BYREF\n int v26; // [rsp+1014h] [rbp-54h]\n _DWORD *v27; // [rsp+1018h] [rbp-50h]\n _DWORD *v28; // [rsp+1020h] [rbp-48h]\n unsigned __int64 v29; // [rsp+1030h] [rbp-38h]\n\n v29 = __readfsqword(0x28u);\n v9 = 4LL * (a3 + a4) + 15;\n v10 = &v25[-(v9 & 0xFFFFFFFFFFFFF000LL)];\n v11 = v9 & 0xFFF0;\n if ( v25 != (_BYTE *)v10 )\n {\n while ( v24 != v10 )\n ;\n }\n v12 = v11 & 0xFFF;\n v13 = alloca(v12);\n if ( v12 )\n *(_QWORD *)((char *)&v24[-2] + v12) = *(_QWORD *)((char *)&v24[-2] + v12);\n v14 = v24;\n if ( a3 > 0 && a4 > 0 )\n {\n v15 = 1LL;\n v16 = 0;\n v17 = 0;\n while ( 1 )\n {\n v19 = *(_DWORD *)(a1 + 4LL * v17);\n v20 = *(_DWORD *)(a2 + 4LL * v16);\n if ( v19 < v20 )\n {\n ++v17;\n v24[v15 - 1] = v19;\n v18 = v15 + 1;\n if ( v17 >= a3 )\n goto LABEL_13;\n }\n else\n {\n v24[v15 - 1] = v20;\n ++v16;\n v18 = v15 + 1;\n if ( v17 >= a3 )\n {\nLABEL_13:\n v21 = v15;\n goto LABEL_14;\n }\n }\n if ( v16 >= a4 )\n goto LABEL_13;\n v15 = v18;\n }\n }\n v21 = 0;\n v16 = 0;\n v17 = 0;\nLABEL_14:\n if ( a3 > v17 )\n {\n v26 = v21;\n v27 = v24;\n LODWORD(v28) = a3;\n memcpy(&v24[v21], (const void *)(a1 + 4LL * v17), 4LL * (unsigned int)(a3 - 1 - v17) + 4);\n v14 = v27;\n v21 = v26 + (_DWORD)v28 - v17;\n }\n if ( a4 > v16 )\n {\n v28 = v14;\n memcpy(&v14[v21], (const void *)(a2 + 4LL * v16), 4LL * (unsigned int)(a4 - 1 - v16) + 4);\n v14 = v28;\n }\n return (unsigned int)v14[a5 - 1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1330(long long a1, long long a2, int a3, int a4, int a5) {\n long long v9;\n uint32_t *v10;\n short v11;\n signed long long v12;\n void *v13;\n uint32_t *v14;\n long long v15;\n int v16;\n int v17;\n long long v18;\n int v19;\n int v20;\n int v21;\n uint32_t v24[1022];\n uint8_t v25[12];\n int v26;\n uint32_t *v27;\n uint32_t *v28;\n unsigned long long v29;\n v29 = __readfsqword(40u);\n v9 = 4LL * (a3 + a4) + 15;\n v10 = &v25[-(v9 & 18446744073709547520LL)];\n v11 = v9 & 65520;\n if (v25 != (uint8_t *)v10) {\n while (v24 != v10)\n ;\n }\n v12 = v11 & 4095;\n v13 = alloca(v12);\n if (v12)\n *(uint64_t *)((char *)&v24[-2] + v12) =\n *(uint64_t *)((char *)&v24[-2] + v12);\n v14 = v24;\n if (a3 > 0 && a4 > 0) {\n v15 = 1LL;\n v16 = 0;\n v17 = 0;\n while (1) {\n v19 = *(uint32_t *)(a1 + 4LL * v17);\n v20 = *(uint32_t *)(a2 + 4LL * v16);\n if (v19 < v20) {\n ++v17;\n v24[v15 - 1] = v19;\n v18 = v15 + 1;\n if (v17 >= a3) goto LABEL_13;\n } else {\n v24[v15 - 1] = v20;\n ++v16;\n v18 = v15 + 1;\n if (v17 >= a3) {\n LABEL_13:\n v21 = v15;\n goto LABEL_14;\n }\n }\n if (v16 >= a4) goto LABEL_13;\n v15 = v18;\n }\n }\n v21 = 0;\n v16 = 0;\n v17 = 0;\nLABEL_14:\n if (a3 > v17) {\n v26 = v21;\n v27 = v24;\n LODWORD(v28) = a3;\n memcpy(&v24[v21], (const void *)(a1 + 4LL * v17),\n 4LL * (unsigned int)(a3 - 1 - v17) + 4);\n v14 = v27;\n v21 = v26 + (uint32_t)v28 - v17;\n }\n if (a4 > v16) {\n v28 = v14;\n memcpy(&v14[v21], (const void *)(a2 + 4LL * v16),\n 4LL * (unsigned int)(a4 - 1 - v16) + 4);\n v14 = v28;\n }\n return (unsigned int)v14[a5 - 1];\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3, int a4, int a5) {\n long long v9;\n uint32_t *v10;\n short v11;\n signed long long v12;\n void *v13;\n uint32_t *v14;\n long long v15;\n int v16;\n int v17;\n long long v18;\n int v19;\n int v20;\n int v21;\n uint32_t v24[1022];\n uint8_t v25[12];\n int v26;\n uint32_t *v27;\n uint32_t *v28;\n unsigned long long v29;\n v29 = __readfsqword(40u);\n v9 = 4LL * (a3 + a4) + 15;\n v10 = &v25[-(v9 & 18446744073709547520LL)];\n v11 = v9 & 65520;\n if (v25 != (uint8_t *)v10) {\n while (v24 != v10)\n ;\n }\n v12 = v11 & 4095;\n v13 = alloca(v12);\n if (v12)\n *(uint64_t *)((char *)&v24[-2] + v12) =\n *(uint64_t *)((char *)&v24[-2] + v12);\n v14 = v24;\n if (a3 > 0 && a4 > 0) {\n v15 = 1LL;\n v16 = 0;\n v17 = 0;\n while (1) {\n v19 = *(uint32_t *)(a1 + 4LL * v17);\n v20 = *(uint32_t *)(a2 + 4LL * v16);\n if (v19 < v20) {\n ++v17;\n v24[v15 - 1] = v19;\n v18 = v15 + 1;\n if (v17 >= a3) goto LABEL_13;\n } else {\n v24[v15 - 1] = v20;\n ++v16;\n v18 = v15 + 1;\n if (v17 >= a3) {\n LABEL_13:\n v21 = v15;\n goto LABEL_14;\n }\n }\n if (v16 >= a4) goto LABEL_13;\n v15 = v18;\n }\n }\n v21 = 0;\n v16 = 0;\n v17 = 0;\nLABEL_14:\n if (a3 > v17) {\n v26 = v21;\n v27 = v24;\n LODWORD(v28) = a3;\n memcpy(&v24[v21], (const void *)(a1 + 4LL * v17),\n 4LL * (unsigned int)(a3 - 1 - v17) + 4);\n v14 = v27;\n v21 = v26 + (uint32_t)v28 - v17;\n }\n if (a4 > v16) {\n v28 = v14;\n memcpy(&v14[v21], (const void *)(a2 + 4LL * v16),\n 4LL * (unsigned int)(a4 - 1 - v16) + 4);\n v14 = v28;\n }\n return (unsigned int)v14[a5 - 1];\n}" + }, + { + "index": 597, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr1[], int arr2[], int m, int n, int k) {\n int sorted1[m + n];\n int i = 0, j = 0, d = 0;\n while (i < m && j < n) {\n if (arr1[i] < arr2[j]) {\n sorted1[d] = arr1[i];\n i++;\n } else {\n sorted1[d] = arr2[j];\n j++;\n }\n d++;\n }\n while (i < m) {\n sorted1[d] = arr1[i];\n d++;\n i++;\n }\n while (j < n) {\n sorted1[d] = arr2[j];\n d++;\n j++;\n }\n return sorted1[k - 1];\n}", + "test": "int main() {\n\n int arr1_1[] = {2, 3, 6, 7, 9};\n\n int arr2_1[] = {1, 4, 8, 10};\n\n int arr1_2[] = {100, 112, 256, 349, 770};\n\n int arr2_2[] = {72, 86, 113, 119, 265, 445, 892};\n\n int arr1_3[] = {3, 4, 7, 8, 10};\n\n int arr2_3[] = {2, 5, 9, 11};\n\n\n\n assert(func0(arr1_1, arr2_1, 5, 4, 5) == 6);\n\n assert(func0(arr1_2, arr2_2, 5, 7, 7) == 256);\n\n assert(func0(arr1_3, arr2_3, 5, 4, 6) == 8);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %edx,%r9d\nmov %rsp,%rbp\npush %r15\nmov %rsi,%r15\npush %r14\nmov %ecx,%r14d\npush %r13\nmov %r8d,%r13d\npush %r12\npush %rbx\nsub $0x38,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nlea (%rdx,%rcx,1),%eax\nmov %rsp,%rsi\ncltq\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rsi\nand $0xfffffffffffffff0,%rdx\nmov %rsi,%rax\ncmp %rax,%rsp\nje 139d \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 1388 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 14d8 \nmov %rsp,%r10\ntest %r9d,%r9d\njle 1421 \ntest %r14d,%r14d\njle 1421 \nmov $0x1,%eax\nxor %r12d,%r12d\nxor %ebx,%ebx\nxor %r8d,%r8d\nxor %esi,%esi\nnopl 0x0(%rax,%rax,1)\nmov (%rdi,%r8,4),%ecx\nmov (%r15,%rsi,4),%edx\ncmp %edx,%ecx\njge 1404 \nmov %ecx,-0x4(%r10,%rax,4)\nadd $0x1,%r12d\nmov %eax,%ecx\nadd $0x1,%rax\ncmp %ebx,%r14d\njle 1430 \ncmp %r9d,%r12d\njge 1430 \nmovslq %r12d,%r8\nmov (%r15,%rsi,4),%edx\nmov (%rdi,%r8,4),%ecx\ncmp %edx,%ecx\njl 13dc \nmov %edx,-0x4(%r10,%rax,4)\nmov %eax,%ecx\nadd $0x1,%ebx\nadd $0x1,%rax\ncmp %r12d,%r9d\njle 1479 \ncmp %r14d,%ebx\njge 1430 \nmovslq %ebx,%rsi\njmp 13d0 \nxor %ecx,%ecx\nxor %r12d,%r12d\nxor %ebx,%ebx\nnopl 0x0(%rax,%rax,1)\ncmp %r12d,%r9d\njle 1479 \nmovslq %ecx,%rax\nmov %ecx,-0x54(%rbp)\nlea (%r10,%rax,4),%r8\nlea -0x1(%r9),%eax\nmov %r10,-0x50(%rbp)\nsub %r12d,%eax\nmov %r9d,-0x48(%rbp)\nlea 0x4(,%rax,4),%rdx\nmovslq %r12d,%rax\nlea (%rdi,%rax,4),%rsi\nmov %r8,%rdi\ncallq 1090 \nmov -0x54(%rbp),%ecx\nmov -0x48(%rbp),%r9d\nmov -0x50(%rbp),%r10\nadd %ecx,%r9d\nmov %r9d,%ecx\nsub %r12d,%ecx\ncmp %ebx,%r14d\njle 14a8 \nsub $0x1,%r14d\nmovslq %ecx,%r9\nmov %r10,-0x48(%rbp)\nsub %ebx,%r14d\nmovslq %ebx,%rbx\nlea (%r10,%r9,4),%rdi\nlea 0x4(,%r14,4),%rdx\nlea (%r15,%rbx,4),%rsi\ncallq 1090 \nmov -0x48(%rbp),%r10\nsub $0x1,%r13d\nmov -0x38(%rbp),%rdi\nxor %fs:0x28,%rdi\nmovslq %r13d,%r13\nmov (%r10,%r13,4),%eax\njne 14e3 \nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\nnopl 0x0(%rax)\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 13af \ncallq 1070 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov r9d, edx\nmov rbp, rsp\npush r15\nmov r15, rsi\npush r14\nmov r14d, ecx\npush r13\nmov r13d, r8d\npush r12\npush rbx\nsub rsp, 38h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nlea eax, [rdx+rcx]\nmov rcx, rsp\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_139A\nloc_1385:\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\ncmp rsp, rcx\njnz short loc_1385\nloc_139A:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_14E0\nloc_13AC:\nmov rcx, rsp\ntest r9d, r9d\njle loc_14EB\ntest r14d, r14d\njle loc_14EB\nmov eax, 1\nxor ebx, ebx\nxor r12d, r12d\nxor r10d, r10d\nxor r8d, r8d\nnop dword ptr [rax+00000000h]\nloc_13D8:\nmov esi, [rdi+r10*4]\nmov edx, [r15+r8*4]\ncmp esi, edx\njge short loc_140C\nloc_13E4:\nmov [rcx+rax*4-4], esi\nadd r12d, 1\nlea rdx, [rax+1]\ncmp r14d, ebx\njle short loc_1430\ncmp r12d, r9d\njge short loc_1430\nmovsxd r10, r12d\nmov rax, rdx\nmov edx, [r15+r8*4]\nmov esi, [rdi+r10*4]\ncmp esi, edx\njl short loc_13E4\nloc_140C:\nmov [rcx+rax*4-4], edx\nadd ebx, 1\nlea rdx, [rax+1]\ncmp r9d, r12d\njle short loc_1430\ncmp ebx, r14d\njge short loc_1430\nmov rax, rdx\nmovsxd r8, ebx\njmp short loc_13D8\nloc_1430:\nmov r8d, eax\nloc_1433:\ncmp r9d, r12d\njle short loc_147E\nmovsxd rax, r8d\nmov [rbp+var_54], r8d\nlea r10, [rcx+rax*4]\nlea eax, [r9-1]\nmov [rbp+var_50], rcx\nsub eax, r12d\nmov dword ptr [rbp+var_48], r9d\nlea rdx, ds:4[rax*4]; n\nmovsxd rax, r12d\nlea rsi, [rdi+rax*4]; src\nmov rdi, r10; dest\ncall _memcpy\nmov r8d, [rbp+var_54]\nmov r9d, dword ptr [rbp+var_48]\nmov rcx, [rbp+var_50]\nadd r9d, r8d\nsub r9d, r12d\nmov r8d, r9d\nloc_147E:\ncmp r14d, ebx\njle short loc_14AD\nsub r14d, 1\nmovsxd rax, r8d\nmov [rbp+var_48], rcx\nsub r14d, ebx\nmovsxd rbx, ebx\nlea rdi, [rcx+rax*4]; dest\nlea rdx, ds:4[r14*4]; n\nlea rsi, [r15+rbx*4]; src\ncall _memcpy\nmov rcx, [rbp+var_48]\nloc_14AD:\nsub r13d, 1\nmovsxd r13, r13d\nmov eax, [rcx+r13*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_14F8\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_14E0:\nor [rsp+rdx+1060h+var_1068], 0\njmp loc_13AC\nloc_14EB:\nxor r8d, r8d\nxor ebx, ebx\nxor r12d, r12d\njmp loc_1433\nloc_14F8:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3, int a4, int a5)\n{\n __int64 v9; // rdx\n _DWORD *v10; // rcx\n __int16 v11; // dx\n signed __int64 v12; // rdx\n void *v13; // rsp\n _DWORD *v14; // rcx\n __int64 v15; // rax\n int v16; // ebx\n int v17; // r12d\n __int64 v18; // r10\n __int64 i; // r8\n int v20; // esi\n int v21; // edx\n int v22; // r8d\n _DWORD v25[1022]; // [rsp+8h] [rbp-1060h] BYREF\n _BYTE v26[12]; // [rsp+1008h] [rbp-60h] BYREF\n int v27; // [rsp+1014h] [rbp-54h]\n _DWORD *v28; // [rsp+1018h] [rbp-50h]\n _DWORD *v29; // [rsp+1020h] [rbp-48h]\n unsigned __int64 v30; // [rsp+1030h] [rbp-38h]\n\n v30 = __readfsqword(0x28u);\n v9 = 4LL * (a3 + a4) + 15;\n v10 = &v26[-(v9 & 0xFFFFFFFFFFFFF000LL)];\n v11 = v9 & 0xFFF0;\n if ( v26 != (_BYTE *)v10 )\n {\n while ( v25 != v10 )\n ;\n }\n v12 = v11 & 0xFFF;\n v13 = alloca(v12);\n if ( v12 )\n *(_QWORD *)((char *)&v25[-2] + v12) = *(_QWORD *)((char *)&v25[-2] + v12);\n v14 = v25;\n if ( a3 <= 0 || a4 <= 0 )\n {\n v22 = 0;\n v16 = 0;\n v17 = 0;\n }\n else\n {\n v15 = 1LL;\n v16 = 0;\n v17 = 0;\n v18 = 0LL;\n for ( i = 0LL; ; i = v16 )\n {\n v20 = *(_DWORD *)(a1 + 4 * v18);\n v21 = *(_DWORD *)(a2 + 4 * i);\n if ( v20 < v21 )\n break;\nLABEL_12:\n v25[v15 - 1] = v21;\n ++v16;\n if ( a3 <= v17 || v16 >= a4 )\n goto LABEL_15;\n ++v15;\n }\n while ( 1 )\n {\n v25[v15 - 1] = v20;\n ++v17;\n if ( a4 <= v16 || v17 >= a3 )\n break;\n v18 = v17;\n ++v15;\n v21 = *(_DWORD *)(a2 + 4 * i);\n v20 = *(_DWORD *)(a1 + 4LL * v17);\n if ( v20 >= v21 )\n goto LABEL_12;\n }\nLABEL_15:\n v22 = v15;\n }\n if ( a3 > v17 )\n {\n v27 = v22;\n v28 = v25;\n LODWORD(v29) = a3;\n memcpy(&v25[v22], (const void *)(a1 + 4LL * v17), 4LL * (unsigned int)(a3 - 1 - v17) + 4);\n v14 = v28;\n v22 = v27 + (_DWORD)v29 - v17;\n }\n if ( a4 > v16 )\n {\n v29 = v14;\n memcpy(&v14[v22], (const void *)(a2 + 4LL * v16), 4LL * (unsigned int)(a4 - 1 - v16) + 4);\n v14 = v29;\n }\n return (unsigned int)v14[a5 - 1];\n}", + "ida_strip_asm": "sub_1330:\nendbr64\npush rbp\nmov r9d, edx\nmov rbp, rsp\npush r15\nmov r15, rsi\npush r14\nmov r14d, ecx\npush r13\nmov r13d, r8d\npush r12\npush rbx\nsub rsp, 38h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nlea eax, [rdx+rcx]\nmov rcx, rsp\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_139A\nloc_1385:\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\ncmp rsp, rcx\njnz short loc_1385\nloc_139A:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_14E0\nloc_13AC:\nmov rcx, rsp\ntest r9d, r9d\njle loc_14EB\ntest r14d, r14d\njle loc_14EB\nmov eax, 1\nxor ebx, ebx\nxor r12d, r12d\nxor r10d, r10d\nxor r8d, r8d\nnop dword ptr [rax+00000000h]\nloc_13D8:\nmov esi, [rdi+r10*4]\nmov edx, [r15+r8*4]\ncmp esi, edx\njge short loc_140C\nloc_13E4:\nmov [rcx+rax*4-4], esi\nadd r12d, 1\nlea rdx, [rax+1]\ncmp r14d, ebx\njle short loc_1430\ncmp r12d, r9d\njge short loc_1430\nmovsxd r10, r12d\nmov rax, rdx\nmov edx, [r15+r8*4]\nmov esi, [rdi+r10*4]\ncmp esi, edx\njl short loc_13E4\nloc_140C:\nmov [rcx+rax*4-4], edx\nadd ebx, 1\nlea rdx, [rax+1]\ncmp r9d, r12d\njle short loc_1430\ncmp ebx, r14d\njge short loc_1430\nmov rax, rdx\nmovsxd r8, ebx\njmp short loc_13D8\nloc_1430:\nmov r8d, eax\nloc_1433:\ncmp r9d, r12d\njle short loc_147E\nmovsxd rax, r8d\nmov [rbp+var_54], r8d\nlea r10, [rcx+rax*4]\nlea eax, [r9-1]\nmov [rbp+var_50], rcx\nsub eax, r12d\nmov dword ptr [rbp+var_48], r9d\nlea rdx, ds:4[rax*4]; n\nmovsxd rax, r12d\nlea rsi, [rdi+rax*4]; src\nmov rdi, r10; dest\ncall _memcpy\nmov r8d, [rbp+var_54]\nmov r9d, dword ptr [rbp+var_48]\nmov rcx, [rbp+var_50]\nadd r9d, r8d\nsub r9d, r12d\nmov r8d, r9d\nloc_147E:\ncmp r14d, ebx\njle short loc_14AD\nsub r14d, 1\nmovsxd rax, r8d\nmov [rbp+var_48], rcx\nsub r14d, ebx\nmovsxd rbx, ebx\nlea rdi, [rcx+rax*4]; dest\nlea rdx, ds:4[r14*4]; n\nlea rsi, [r15+rbx*4]; src\ncall _memcpy\nmov rcx, [rbp+var_48]\nloc_14AD:\nsub r13d, 1\nmovsxd r13, r13d\nmov eax, [rcx+r13*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_14F8\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_14E0:\nor [rsp+rdx+1060h+var_1068], 0\njmp loc_13AC\nloc_14EB:\nxor r8d, r8d\nxor ebx, ebx\nxor r12d, r12d\njmp loc_1433\nloc_14F8:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1330(__int64 a1, __int64 a2, int a3, int a4, int a5)\n{\n __int64 v9; // rdx\n _DWORD *v10; // rcx\n __int16 v11; // dx\n signed __int64 v12; // rdx\n void *v13; // rsp\n _DWORD *v14; // rcx\n __int64 v15; // rax\n int v16; // ebx\n int v17; // r12d\n __int64 v18; // r10\n __int64 i; // r8\n int v20; // esi\n int v21; // edx\n int v22; // r8d\n _DWORD v25[1022]; // [rsp+8h] [rbp-1060h] BYREF\n _BYTE v26[12]; // [rsp+1008h] [rbp-60h] BYREF\n int v27; // [rsp+1014h] [rbp-54h]\n _DWORD *v28; // [rsp+1018h] [rbp-50h]\n _DWORD *v29; // [rsp+1020h] [rbp-48h]\n unsigned __int64 v30; // [rsp+1030h] [rbp-38h]\n\n v30 = __readfsqword(0x28u);\n v9 = 4LL * (a3 + a4) + 15;\n v10 = &v26[-(v9 & 0xFFFFFFFFFFFFF000LL)];\n v11 = v9 & 0xFFF0;\n if ( v26 != (_BYTE *)v10 )\n {\n while ( v25 != v10 )\n ;\n }\n v12 = v11 & 0xFFF;\n v13 = alloca(v12);\n if ( v12 )\n *(_QWORD *)((char *)&v25[-2] + v12) = *(_QWORD *)((char *)&v25[-2] + v12);\n v14 = v25;\n if ( a3 <= 0 || a4 <= 0 )\n {\n v22 = 0;\n v16 = 0;\n v17 = 0;\n }\n else\n {\n v15 = 1LL;\n v16 = 0;\n v17 = 0;\n v18 = 0LL;\n for ( i = 0LL; ; i = v16 )\n {\n v20 = *(_DWORD *)(a1 + 4 * v18);\n v21 = *(_DWORD *)(a2 + 4 * i);\n if ( v20 < v21 )\n break;\nLABEL_12:\n v25[v15 - 1] = v21;\n ++v16;\n if ( a3 <= v17 || v16 >= a4 )\n goto LABEL_15;\n ++v15;\n }\n while ( 1 )\n {\n v25[v15 - 1] = v20;\n ++v17;\n if ( a4 <= v16 || v17 >= a3 )\n break;\n v18 = v17;\n ++v15;\n v21 = *(_DWORD *)(a2 + 4 * i);\n v20 = *(_DWORD *)(a1 + 4LL * v17);\n if ( v20 >= v21 )\n goto LABEL_12;\n }\nLABEL_15:\n v22 = v15;\n }\n if ( a3 > v17 )\n {\n v27 = v22;\n v28 = v25;\n LODWORD(v29) = a3;\n memcpy(&v25[v22], (const void *)(a1 + 4LL * v17), 4LL * (unsigned int)(a3 - 1 - v17) + 4);\n v14 = v28;\n v22 = v27 + (_DWORD)v29 - v17;\n }\n if ( a4 > v16 )\n {\n v29 = v14;\n memcpy(&v14[v22], (const void *)(a2 + 4LL * v16), 4LL * (unsigned int)(a4 - 1 - v16) + 4);\n v14 = v29;\n }\n return (unsigned int)v14[a5 - 1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1330(long long a1, long long a2, int a3, int a4, int a5) {\n long long v9;\n uint32_t *v10;\n short v11;\n signed long long v12;\n void *v13;\n uint32_t *v14;\n long long v15;\n int v16;\n int v17;\n long long v18;\n long long i;\n int v20;\n int v21;\n int v22;\n uint32_t v25[1022];\n uint8_t v26[12];\n int v27;\n uint32_t *v28;\n uint32_t *v29;\n unsigned long long v30;\n v30 = __readfsqword(40u);\n v9 = 4LL * (a3 + a4) + 15;\n v10 = &v26[-(v9 & 18446744073709547520LL)];\n v11 = v9 & 65520;\n if (v26 != (uint8_t *)v10) {\n while (v25 != v10)\n ;\n }\n v12 = v11 & 4095;\n v13 = alloca(v12);\n if (v12)\n *(uint64_t *)((char *)&v25[-2] + v12) =\n *(uint64_t *)((char *)&v25[-2] + v12);\n v14 = v25;\n if (a3 <= 0 || a4 <= 0) {\n v22 = 0;\n v16 = 0;\n v17 = 0;\n } else {\n v15 = 1LL;\n v16 = 0;\n v17 = 0;\n v18 = 0LL;\n for (i = 0LL;; i = v16) {\n v20 = *(uint32_t *)(a1 + 4 * v18);\n v21 = *(uint32_t *)(a2 + 4 * i);\n if (v20 < v21) break;\n LABEL_12:\n v25[v15 - 1] = v21;\n ++v16;\n if (a3 <= v17 || v16 >= a4) goto LABEL_15;\n ++v15;\n }\n while (1) {\n v25[v15 - 1] = v20;\n ++v17;\n if (a4 <= v16 || v17 >= a3) break;\n v18 = v17;\n ++v15;\n v21 = *(uint32_t *)(a2 + 4 * i);\n v20 = *(uint32_t *)(a1 + 4LL * v17);\n if (v20 >= v21) goto LABEL_12;\n }\n LABEL_15:\n v22 = v15;\n }\n if (a3 > v17) {\n v27 = v22;\n v28 = v25;\n LODWORD(v29) = a3;\n memcpy(&v25[v22], (const void *)(a1 + 4LL * v17),\n 4LL * (unsigned int)(a3 - 1 - v17) + 4);\n v14 = v28;\n v22 = v27 + (uint32_t)v29 - v17;\n }\n if (a4 > v16) {\n v29 = v14;\n memcpy(&v14[v22], (const void *)(a2 + 4LL * v16),\n 4LL * (unsigned int)(a4 - 1 - v16) + 4);\n v14 = v29;\n }\n return (unsigned int)v14[a5 - 1];\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3, int a4, int a5) {\n long long v9;\n uint32_t *v10;\n short v11;\n signed long long v12;\n void *v13;\n uint32_t *v14;\n long long v15;\n int v16;\n int v17;\n long long v18;\n long long i;\n int v20;\n int v21;\n int v22;\n uint32_t v25[1022];\n uint8_t v26[12];\n int v27;\n uint32_t *v28;\n uint32_t *v29;\n unsigned long long v30;\n v30 = __readfsqword(40u);\n v9 = 4LL * (a3 + a4) + 15;\n v10 = &v26[-(v9 & 18446744073709547520LL)];\n v11 = v9 & 65520;\n if (v26 != (uint8_t *)v10) {\n while (v25 != v10)\n ;\n }\n v12 = v11 & 4095;\n v13 = alloca(v12);\n if (v12)\n *(uint64_t *)((char *)&v25[-2] + v12) =\n *(uint64_t *)((char *)&v25[-2] + v12);\n v14 = v25;\n if (a3 <= 0 || a4 <= 0) {\n v22 = 0;\n v16 = 0;\n v17 = 0;\n } else {\n v15 = 1LL;\n v16 = 0;\n v17 = 0;\n v18 = 0LL;\n for (i = 0LL;; i = v16) {\n v20 = *(uint32_t *)(a1 + 4 * v18);\n v21 = *(uint32_t *)(a2 + 4 * i);\n if (v20 < v21) break;\n LABEL_12:\n v25[v15 - 1] = v21;\n ++v16;\n if (a3 <= v17 || v16 >= a4) goto LABEL_15;\n ++v15;\n }\n while (1) {\n v25[v15 - 1] = v20;\n ++v17;\n if (a4 <= v16 || v17 >= a3) break;\n v18 = v17;\n ++v15;\n v21 = *(uint32_t *)(a2 + 4 * i);\n v20 = *(uint32_t *)(a1 + 4LL * v17);\n if (v20 >= v21) goto LABEL_12;\n }\n LABEL_15:\n v22 = v15;\n }\n if (a3 > v17) {\n v27 = v22;\n v28 = v25;\n LODWORD(v29) = a3;\n memcpy(&v25[v22], (const void *)(a1 + 4LL * v17),\n 4LL * (unsigned int)(a3 - 1 - v17) + 4);\n v14 = v28;\n v22 = v27 + (uint32_t)v29 - v17;\n }\n if (a4 > v16) {\n v29 = v14;\n memcpy(&v14[v22], (const void *)(a2 + 4LL * v16),\n 4LL * (unsigned int)(a4 - 1 - v16) + 4);\n v14 = v29;\n }\n return (unsigned int)v14[a5 - 1];\n}" + }, + { + "index": 598, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int number) {\n int sum = 0;\n int times = 0;\n int temp = number;\n while (temp > 0) {\n times++;\n temp /= 10;\n }\n temp = number;\n while (temp > 0) {\n int reminder = temp % 10;\n sum += pow(reminder, times);\n temp /= 10;\n }\n if (number == sum) {\n return 1;\n } else {\n return 0;\n }\n}", + "test": "int main() {\n\n assert(func0(153) == 1);\n\n assert(func0(259) == 0);\n\n assert(func0(4458) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %edi,-0x14(%rbp)\nmovl $0x0,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\nmov -0x14(%rbp),%eax\nmov %eax,-0x8(%rbp)\njmp 11b0 \naddl $0x1,-0xc(%rbp)\nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nimul $0x66666667,%rdx,%rdx\nshr $0x20,%rdx\nsar $0x2,%edx\nsar $0x1f,%eax\nsub %eax,%edx\nmov %edx,%eax\nmov %eax,-0x8(%rbp)\ncmpl $0x0,-0x8(%rbp)\njg 118e \nmov -0x14(%rbp),%eax\nmov %eax,-0x8(%rbp)\njmp 1228 \nmov -0x8(%rbp),%edx\nmovslq %edx,%rax\nimul $0x66666667,%rax,%rax\nshr $0x20,%rax\nmov %eax,%ecx\nsar $0x2,%ecx\nmov %edx,%eax\nsar $0x1f,%eax\nsub %eax,%ecx\nmov %ecx,%eax\nshl $0x2,%eax\nadd %ecx,%eax\nadd %eax,%eax\nsub %eax,%edx\nmov %edx,%eax\nmov %eax,-0x4(%rbp)\ncvtsi2sdl -0xc(%rbp),%xmm1\ncvtsi2sdl -0x4(%rbp),%xmm0\ncallq 1060 \ncvtsi2sdl -0x10(%rbp),%xmm1\naddsd %xmm1,%xmm0\ncvttsd2si %xmm0,%eax\nmov %eax,-0x10(%rbp)\nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nimul $0x66666667,%rdx,%rdx\nshr $0x20,%rdx\nsar $0x2,%edx\nsar $0x1f,%eax\nsub %eax,%edx\nmov %edx,%eax\nmov %eax,-0x8(%rbp)\ncmpl $0x0,-0x8(%rbp)\njg 11be \nmov -0x14(%rbp),%eax\ncmp -0x10(%rbp),%eax\njne 123d \nmov $0x1,%eax\njmp 1242 \nmov $0x0,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\nmov eax, [rbp+var_14]\nmov [rbp+var_8], eax\njmp short loc_11B0\nloc_118E:\nadd [rbp+var_C], 1\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_8], eax\nloc_11B0:\ncmp [rbp+var_8], 0\njg short loc_118E\nmov eax, [rbp+var_14]\nmov [rbp+var_8], eax\njmp loc_1243\nloc_11C1:\nmov edx, [rbp+var_8]\nmovsxd rax, edx\nimul rax, 66666667h\nshr rax, 20h\nmov ecx, eax\nsar ecx, 2\nmov eax, edx\nsar eax, 1Fh\nsub ecx, eax\nmov eax, ecx\nshl eax, 2\nadd eax, ecx\nadd eax, eax\nsub edx, eax\nmov [rbp+var_4], edx\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_C]\npxor xmm2, xmm2\ncvtsi2sd xmm2, [rbp+var_4]\nmovq rax, xmm2\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_10]\naddsd xmm0, xmm1\ncvttsd2si eax, xmm0\nmov [rbp+var_10], eax\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_8], eax\nloc_1243:\ncmp [rbp+var_8], 0\njg loc_11C1\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_10]\njnz short loc_125C\nmov eax, 1\njmp short locret_1261\nloc_125C:\nmov eax, 0\nlocret_1261:\nleave\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(int a1)\n{\n int v2; // [rsp+10h] [rbp-10h]\n int v3; // [rsp+14h] [rbp-Ch]\n int i; // [rsp+18h] [rbp-8h]\n int j; // [rsp+18h] [rbp-8h]\n\n v2 = 0;\n v3 = 0;\n for ( i = a1; i > 0; i /= 10 )\n ++v3;\n for ( j = a1; j > 0; j /= 10 )\n v2 = (int)(pow((double)(j % 10), (double)v3) + (double)v2);\n return a1 == v2;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\nmov eax, [rbp+var_14]\nmov [rbp+var_8], eax\njmp short loc_11B0\nloc_118E:\nadd [rbp+var_C], 1\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_8], eax\nloc_11B0:\ncmp [rbp+var_8], 0\njg short loc_118E\nmov eax, [rbp+var_14]\nmov [rbp+var_8], eax\njmp loc_1243\nloc_11C1:\nmov edx, [rbp+var_8]\nmovsxd rax, edx\nimul rax, 66666667h\nshr rax, 20h\nmov ecx, eax\nsar ecx, 2\nmov eax, edx\nsar eax, 1Fh\nsub ecx, eax\nmov eax, ecx\nshl eax, 2\nadd eax, ecx\nadd eax, eax\nsub edx, eax\nmov [rbp+var_4], edx\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_C]\npxor xmm2, xmm2\ncvtsi2sd xmm2, [rbp+var_4]\nmovq rax, xmm2\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_10]\naddsd xmm0, xmm1\ncvttsd2si eax, xmm0\nmov [rbp+var_10], eax\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_8], eax\nloc_1243:\ncmp [rbp+var_8], 0\njg loc_11C1\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_10]\njnz short loc_125C\nmov eax, 1\njmp short locret_1261\nloc_125C:\nmov eax, 0\nlocret_1261:\nleave\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1169(int a1)\n{\n int v2; // [rsp+10h] [rbp-10h]\n int v3; // [rsp+14h] [rbp-Ch]\n int i; // [rsp+18h] [rbp-8h]\n int j; // [rsp+18h] [rbp-8h]\n\n v2 = 0;\n v3 = 0;\n for ( i = a1; i > 0; i /= 10 )\n ++v3;\n for ( j = a1; j > 0; j /= 10 )\n v2 = (int)(pow((double)(j % 10), (double)v3) + (double)v2);\n return a1 == v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1169(int a1) {\n int v2;\n int v3;\n int i;\n int j;\n v2 = 0;\n v3 = 0;\n for (i = a1; i > 0; i /= 10) ++v3;\n for (j = a1; j > 0; j /= 10)\n v2 = (int)(pow((double)(j % 10), (double)v3) + (double)v2);\n return a1 == v2;\n}", + "ida_pseudo_norm": "uint8_t func0(int a1) {\n int v2;\n int v3;\n int i;\n int j;\n v2 = 0;\n v3 = 0;\n for (i = a1; i > 0; i /= 10) ++v3;\n for (j = a1; j > 0; j /= 10)\n v2 = (int)(pow((double)(j % 10), (double)v3) + (double)v2);\n return a1 == v2;\n}" + }, + { + "index": 598, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int number) {\n int sum = 0;\n int times = 0;\n int temp = number;\n while (temp > 0) {\n times++;\n temp /= 10;\n }\n temp = number;\n while (temp > 0) {\n int reminder = temp % 10;\n sum += pow(reminder, times);\n temp /= 10;\n }\n if (number == sum) {\n return 1;\n } else {\n return 0;\n }\n}", + "test": "int main() {\n\n assert(func0(153) == 1);\n\n assert(func0(259) == 0);\n\n assert(func0(4458) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov %edi,%ebp\ntest %edi,%edi\njle 1226 \nmov %edi,%eax\nmov $0x0,%ecx\nadd $0x1,%ecx\nmov %eax,%esi\nmovslq %eax,%rdx\nimul $0x66666667,%rdx,%rdx\nsar $0x22,%rdx\nsar $0x1f,%eax\nsub %eax,%edx\nmov %edx,%eax\ncmp $0x9,%esi\njg 1188 \nmov %ebp,%r13d\nmov $0x0,%r12d\npxor %xmm2,%xmm2\ncvtsi2sd %ecx,%xmm2\nmovsd %xmm2,0x8(%rsp)\nmovslq %r13d,%rbx\nimul $0x66666667,%rbx,%rbx\nsar $0x22,%rbx\nmov %r13d,%eax\nsar $0x1f,%eax\nsub %eax,%ebx\nlea (%rbx,%rbx,4),%eax\nadd %eax,%eax\nmov %r13d,%edi\nsub %eax,%edi\npxor %xmm0,%xmm0\ncvtsi2sd %edi,%xmm0\nmovsd 0x8(%rsp),%xmm1\ncallq 1060 \nmovapd %xmm0,%xmm1\npxor %xmm0,%xmm0\ncvtsi2sd %r12d,%xmm0\naddsd %xmm1,%xmm0\ncvttsd2si %xmm0,%r12d\nmov %r13d,%eax\nmov %ebx,%r13d\ncmp $0x9,%eax\njg 11be \ncmp %r12d,%ebp\nsete %al\nmovzbl %al,%eax\nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nmov $0x0,%r12d\njmp 1212 \n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r13d, edi\ntest edi, edi\njle loc_121F\nmov edx, edi\nmov ecx, 0\nloc_1187:\nadd ecx, 1\nmov esi, edx\nmovsxd rax, edx\nimul rax, 66666667h\nsar rax, 22h\nmov edi, edx\nsar edi, 1Fh\nsub eax, edi\nmov edx, eax\ncmp esi, 9\njg short loc_1187\nmov ebp, r13d\nmov r12d, 0\npxor xmm2, xmm2\ncvtsi2sd xmm2, ecx\nmovq r14, xmm2\nloc_11BE:\nmovsxd rbx, ebp\nimul rbx, 66666667h\nsar rbx, 22h\nmov eax, ebp\nsar eax, 1Fh\nsub ebx, eax\nlea eax, [rbx+rbx*4]\nadd eax, eax\nmov edx, ebp\nsub edx, eax\npxor xmm0, xmm0\ncvtsi2sd xmm0, edx; x\nmovq xmm1, r14; y\ncall _pow\nmovapd xmm1, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, r12d\naddsd xmm0, xmm1\ncvttsd2si r12d, xmm0\nmov eax, ebp\nmov ebp, ebx\ncmp eax, 9\njg short loc_11BE\nloc_120D:\ncmp r13d, r12d\nsetz al\nmovzx eax, al\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_121F:\nmov r12d, 0\njmp short loc_120D", + "ida_pseudo": "_BOOL8 __fastcall func0(int a1)\n{\n int v1; // edx\n int v2; // ecx\n int v3; // esi\n int v4; // ebp\n int v5; // r12d\n double v6; // r14\n int v7; // eax\n\n if ( a1 <= 0 )\n {\n v5 = 0;\n }\n else\n {\n v1 = a1;\n v2 = 0;\n do\n {\n ++v2;\n v3 = v1;\n v1 /= 10;\n }\n while ( v3 > 9 );\n v4 = a1;\n v5 = 0;\n v6 = (double)v2;\n do\n {\n v5 = (int)((double)v5 + pow((double)(v4 % 10), v6));\n v7 = v4;\n v4 /= 10;\n }\n while ( v7 > 9 );\n }\n return a1 == v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r13d, edi\ntest edi, edi\njle loc_121F\nmov edx, edi\nmov ecx, 0\nloc_1187:\nadd ecx, 1\nmov esi, edx\nmovsxd rax, edx\nimul rax, 66666667h\nsar rax, 22h\nmov edi, edx\nsar edi, 1Fh\nsub eax, edi\nmov edx, eax\ncmp esi, 9\njg short loc_1187\nmov ebp, r13d\nmov r12d, 0\npxor xmm2, xmm2\ncvtsi2sd xmm2, ecx\nmovq r14, xmm2\nloc_11BE:\nmovsxd rbx, ebp\nimul rbx, 66666667h\nsar rbx, 22h\nmov eax, ebp\nsar eax, 1Fh\nsub ebx, eax\nlea eax, [rbx+rbx*4]\nadd eax, eax\nmov edx, ebp\nsub edx, eax\npxor xmm0, xmm0\ncvtsi2sd xmm0, edx; x\nmovq xmm1, r14; y\ncall _pow\nmovapd xmm1, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, r12d\naddsd xmm0, xmm1\ncvttsd2si r12d, xmm0\nmov eax, ebp\nmov ebp, ebx\ncmp eax, 9\njg short loc_11BE\nloc_120D:\ncmp r13d, r12d\nsetz al\nmovzx eax, al\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_121F:\nmov r12d, 0\njmp short loc_120D", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1169(int a1)\n{\n int v1; // edx\n int v2; // ecx\n int v3; // esi\n int v4; // ebp\n int v5; // r12d\n double v6; // r14\n int v7; // eax\n\n if ( a1 <= 0 )\n {\n v5 = 0;\n }\n else\n {\n v1 = a1;\n v2 = 0;\n do\n {\n ++v2;\n v3 = v1;\n v1 /= 10;\n }\n while ( v3 > 9 );\n v4 = a1;\n v5 = 0;\n v6 = (double)v2;\n do\n {\n v5 = (int)((double)v5 + pow((double)(v4 % 10), v6));\n v7 = v4;\n v4 /= 10;\n }\n while ( v7 > 9 );\n }\n return a1 == v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1169(int a1) {\n int v1;\n int v2;\n int v3;\n int v4;\n int v5;\n double v6;\n int v7;\n if (a1 <= 0) {\n v5 = 0;\n } else {\n v1 = a1;\n v2 = 0;\n do {\n ++v2;\n v3 = v1;\n v1 /= 10;\n } while (v3 > 9);\n v4 = a1;\n v5 = 0;\n v6 = (double)v2;\n do {\n v5 = (int)((double)v5 + pow((double)(v4 % 10), v6));\n v7 = v4;\n v4 /= 10;\n } while (v7 > 9);\n }\n return a1 == v5;\n}", + "ida_pseudo_norm": "uint8_t func0(int a1) {\n int v1;\n int v2;\n int v3;\n int v4;\n int v5;\n double v6;\n int v7;\n if (a1 <= 0) {\n v5 = 0;\n } else {\n v1 = a1;\n v2 = 0;\n do {\n ++v2;\n v3 = v1;\n v1 /= 10;\n } while (v3 > 9);\n v4 = a1;\n v5 = 0;\n v6 = (double)v2;\n do {\n v5 = (int)((double)v5 + pow((double)(v4 % 10), v6));\n v7 = v4;\n v4 /= 10;\n } while (v7 > 9);\n }\n return a1 == v5;\n}" + }, + { + "index": 598, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int number) {\n int sum = 0;\n int times = 0;\n int temp = number;\n while (temp > 0) {\n times++;\n temp /= 10;\n }\n temp = number;\n while (temp > 0) {\n int reminder = temp % 10;\n sum += pow(reminder, times);\n temp /= 10;\n }\n if (number == sum) {\n return 1;\n } else {\n return 0;\n }\n}", + "test": "int main() {\n\n assert(func0(153) == 1);\n\n assert(func0(259) == 0);\n\n assert(func0(4458) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\nmov %edi,%r12d\npush %rbp\npush %rbx\nsub $0x10,%rsp\ntest %edi,%edi\njle 12c8 \nmov %edi,%eax\nxor %ecx,%ecx\nmov $0xcccccccd,%esi\nnopl 0x0(%rax)\nmov %eax,%eax\nadd $0x1,%ecx\nmov %rax,%rdx\nimul %rsi,%rax\nshr $0x23,%rax\ncmp $0x9,%edx\njg 1238 \npxor %xmm1,%xmm1\nmov %r12d,%r14d\nxor %ebp,%ebp\nmov $0xcccccccd,%r13d\ncvtsi2sd %ecx,%xmm1\nmov %r14d,%ebx\nmov %r14d,%edi\npxor %xmm0,%xmm0\nmovsd %xmm1,0x8(%rsp)\nimul %r13,%rbx\nshr $0x23,%rbx\nlea (%rbx,%rbx,4),%eax\nadd %eax,%eax\nsub %eax,%edi\ncvtsi2sd %edi,%xmm0\ncallq 1060 \nmov %r14d,%eax\nmovsd 0x8(%rsp),%xmm1\nmov %ebx,%r14d\nmovapd %xmm0,%xmm2\npxor %xmm0,%xmm0\ncmp $0x9,%eax\ncvtsi2sd %ebp,%xmm0\naddsd %xmm2,%xmm0\ncvttsd2si %xmm0,%ebp\njg 1260 \nxor %eax,%eax\ncmp %ebp,%r12d\nsete %al\nadd $0x10,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopw 0x0(%rax,%rax,1)\nxor %ebp,%ebp\njmp 12ad \nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\nmov ebp, edi\npush rbx\nsub rsp, 10h\ntest edi, edi\njle loc_12D0\nmov eax, edi\nxor ecx, ecx\nmov esi, 0CCCCCCCDh\nnop dword ptr [rax+rax+00h]\nloc_1238:\nmov eax, eax\nadd ecx, 1\nmov rdx, rax\nimul rax, rsi\nshr rax, 23h\ncmp edx, 9\njg short loc_1238\npxor xmm1, xmm1\nmov r12d, ebp\nxor r14d, r14d\nmov r13d, 0CCCCCCCDh\ncvtsi2sd xmm1, ecx; y\nnop dword ptr [rax+00000000h]\nloc_1268:\nmov ebx, r12d\nmov edx, r12d\npxor xmm0, xmm0\nmovsd [rsp+38h+var_30], xmm1\nimul rbx, r13\nshr rbx, 23h\nlea eax, [rbx+rbx*4]\nadd eax, eax\nsub edx, eax\ncvtsi2sd xmm0, edx; x\ncall _pow\nmov eax, r12d\nmovsd xmm1, [rsp+38h+var_30]\nmov r12d, ebx\nmovapd xmm2, xmm0\npxor xmm0, xmm0\ncmp eax, 9\ncvtsi2sd xmm0, r14d\naddsd xmm0, xmm2\ncvttsd2si r14d, xmm0\njg short loc_1268\nloc_12B7:\nxor eax, eax\ncmp ebp, r14d\nsetz al\nadd rsp, 10h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_12D0:\nxor r14d, r14d\njmp short loc_12B7", + "ida_pseudo": "_BOOL8 __fastcall func0(int a1)\n{\n unsigned int v1; // eax\n int v2; // ecx\n int v3; // edx\n unsigned int v4; // r12d\n int v5; // r14d\n double v6; // xmm1_8\n double v7; // xmm0_8\n int v8; // eax\n\n if ( a1 <= 0 )\n {\n v5 = 0;\n }\n else\n {\n v1 = a1;\n v2 = 0;\n do\n {\n ++v2;\n v3 = v1;\n v1 /= 0xAu;\n }\n while ( v3 > 9 );\n v4 = a1;\n v5 = 0;\n v6 = (double)v2;\n do\n {\n v7 = pow((double)(v4 % 0xA), v6);\n v8 = v4;\n v4 /= 0xAu;\n v5 = (int)((double)v5 + v7);\n }\n while ( v8 > 9 );\n }\n return a1 == v5;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush r14\npush r13\npush r12\npush rbp\nmov ebp, edi\npush rbx\nsub rsp, 10h\ntest edi, edi\njle loc_12D0\nmov eax, edi\nxor ecx, ecx\nmov esi, 0CCCCCCCDh\nnop dword ptr [rax+rax+00h]\nloc_1238:\nmov eax, eax\nadd ecx, 1\nmov rdx, rax\nimul rax, rsi\nshr rax, 23h\ncmp edx, 9\njg short loc_1238\npxor xmm1, xmm1\nmov r12d, ebp\nxor r14d, r14d\nmov r13d, 0CCCCCCCDh\ncvtsi2sd xmm1, ecx; y\nnop dword ptr [rax+00000000h]\nloc_1268:\nmov ebx, r12d\nmov edx, r12d\npxor xmm0, xmm0\nmovsd [rsp+38h+var_30], xmm1\nimul rbx, r13\nshr rbx, 23h\nlea eax, [rbx+rbx*4]\nadd eax, eax\nsub edx, eax\ncvtsi2sd xmm0, edx; x\ncall _pow\nmov eax, r12d\nmovsd xmm1, [rsp+38h+var_30]\nmov r12d, ebx\nmovapd xmm2, xmm0\npxor xmm0, xmm0\ncmp eax, 9\ncvtsi2sd xmm0, r14d\naddsd xmm0, xmm2\ncvttsd2si r14d, xmm0\njg short loc_1268\nloc_12B7:\nxor eax, eax\ncmp ebp, r14d\nsetz al\nadd rsp, 10h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_12D0:\nxor r14d, r14d\njmp short loc_12B7", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1210(int a1)\n{\n unsigned int v1; // eax\n int v2; // ecx\n int v3; // edx\n unsigned int v4; // r12d\n int v5; // r14d\n double v6; // xmm1_8\n double v7; // xmm0_8\n int v8; // eax\n\n if ( a1 <= 0 )\n {\n v5 = 0;\n }\n else\n {\n v1 = a1;\n v2 = 0;\n do\n {\n ++v2;\n v3 = v1;\n v1 /= 0xAu;\n }\n while ( v3 > 9 );\n v4 = a1;\n v5 = 0;\n v6 = (double)v2;\n do\n {\n v7 = pow((double)(v4 % 0xA), v6);\n v8 = v4;\n v4 /= 0xAu;\n v5 = (int)((double)v5 + v7);\n }\n while ( v8 > 9 );\n }\n return a1 == v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1210(int a1) {\n unsigned int v1;\n int v2;\n int v3;\n unsigned int v4;\n int v5;\n double v6;\n double v7;\n int v8;\n if (a1 <= 0) {\n v5 = 0;\n } else {\n v1 = a1;\n v2 = 0;\n do {\n ++v2;\n v3 = v1;\n v1 /= 10u;\n } while (v3 > 9);\n v4 = a1;\n v5 = 0;\n v6 = (double)v2;\n do {\n v7 = pow((double)(v4 % 10), v6);\n v8 = v4;\n v4 /= 10u;\n v5 = (int)((double)v5 + v7);\n } while (v8 > 9);\n }\n return a1 == v5;\n}", + "ida_pseudo_norm": "uint8_t func0(int a1) {\n unsigned int v1;\n int v2;\n int v3;\n unsigned int v4;\n int v5;\n double v6;\n double v7;\n int v8;\n if (a1 <= 0) {\n v5 = 0;\n } else {\n v1 = a1;\n v2 = 0;\n do {\n ++v2;\n v3 = v1;\n v1 /= 10u;\n } while (v3 > 9);\n v4 = a1;\n v5 = 0;\n v6 = (double)v2;\n do {\n v7 = pow((double)(v4 % 10), v6);\n v8 = v4;\n v4 /= 10u;\n v5 = (int)((double)v5 + v7);\n } while (v8 > 9);\n }\n return a1 == v5;\n}" + }, + { + "index": 598, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int number) {\n int sum = 0;\n int times = 0;\n int temp = number;\n while (temp > 0) {\n times++;\n temp /= 10;\n }\n temp = number;\n while (temp > 0) {\n int reminder = temp % 10;\n sum += pow(reminder, times);\n temp /= 10;\n }\n if (number == sum) {\n return 1;\n } else {\n return 0;\n }\n}", + "test": "int main() {\n\n assert(func0(153) == 1);\n\n assert(func0(259) == 0);\n\n assert(func0(4458) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\nmov %edi,%r12d\npush %rbp\npush %rbx\nsub $0x10,%rsp\ntest %edi,%edi\njle 12c8 \nmov %edi,%eax\nxor %ecx,%ecx\nmov $0xcccccccd,%esi\nnopl 0x0(%rax)\nmov %eax,%eax\nadd $0x1,%ecx\nmov %rax,%rdx\nimul %rsi,%rax\nshr $0x23,%rax\ncmp $0x9,%edx\njg 1238 \npxor %xmm1,%xmm1\nmov %r12d,%r14d\nxor %ebp,%ebp\nmov $0xcccccccd,%r13d\ncvtsi2sd %ecx,%xmm1\nmov %r14d,%ebx\nmov %r14d,%edi\npxor %xmm0,%xmm0\nmovsd %xmm1,0x8(%rsp)\nimul %r13,%rbx\nshr $0x23,%rbx\nlea (%rbx,%rbx,4),%eax\nadd %eax,%eax\nsub %eax,%edi\ncvtsi2sd %edi,%xmm0\ncallq 1060 \nmov %r14d,%eax\nmovsd 0x8(%rsp),%xmm1\nmov %ebx,%r14d\nmovapd %xmm0,%xmm2\npxor %xmm0,%xmm0\ncmp $0x9,%eax\ncvtsi2sd %ebp,%xmm0\naddsd %xmm2,%xmm0\ncvttsd2si %xmm0,%ebp\njg 1260 \nxor %eax,%eax\ncmp %ebp,%r12d\nsete %al\nadd $0x10,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopw 0x0(%rax,%rax,1)\nxor %ebp,%ebp\njmp 12ad \nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\nmov ebp, edi\npush rbx\nsub rsp, 10h\ntest edi, edi\njle loc_12D0\nmov eax, edi\nxor ecx, ecx\nmov esi, 0CCCCCCCDh\nnop dword ptr [rax+rax+00h]\nloc_1238:\nmov eax, eax\nadd ecx, 1\nmov rdx, rax\nimul rax, rsi\nshr rax, 23h\ncmp edx, 9\njg short loc_1238\npxor xmm1, xmm1\nmov r12d, ebp\nxor r14d, r14d\nmov r13d, 0CCCCCCCDh\ncvtsi2sd xmm1, ecx; y\nnop dword ptr [rax+00000000h]\nloc_1268:\nmov ebx, r12d\nmov edx, r12d\npxor xmm0, xmm0\nmovsd [rsp+38h+var_30], xmm1\nimul rbx, r13\nshr rbx, 23h\nlea eax, [rbx+rbx*4]\nadd eax, eax\nsub edx, eax\ncvtsi2sd xmm0, edx; x\ncall _pow\nmov eax, r12d\nmovsd xmm1, [rsp+38h+var_30]\nmov r12d, ebx\nmovapd xmm2, xmm0\npxor xmm0, xmm0\ncmp eax, 9\ncvtsi2sd xmm0, r14d\naddsd xmm0, xmm2\ncvttsd2si r14d, xmm0\njg short loc_1268\nloc_12B7:\nxor eax, eax\ncmp ebp, r14d\nsetz al\nadd rsp, 10h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_12D0:\nxor r14d, r14d\njmp short loc_12B7", + "ida_pseudo": "_BOOL8 __fastcall func0(int a1)\n{\n unsigned int v1; // eax\n int v2; // ecx\n int v3; // edx\n unsigned int v4; // r12d\n int v5; // r14d\n double v6; // xmm1_8\n double v7; // xmm0_8\n int v8; // eax\n\n if ( a1 <= 0 )\n {\n v5 = 0;\n }\n else\n {\n v1 = a1;\n v2 = 0;\n do\n {\n ++v2;\n v3 = v1;\n v1 /= 0xAu;\n }\n while ( v3 > 9 );\n v4 = a1;\n v5 = 0;\n v6 = (double)v2;\n do\n {\n v7 = pow((double)(v4 % 0xA), v6);\n v8 = v4;\n v4 /= 0xAu;\n v5 = (int)((double)v5 + v7);\n }\n while ( v8 > 9 );\n }\n return a1 == v5;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush r14\npush r13\npush r12\npush rbp\nmov ebp, edi\npush rbx\nsub rsp, 10h\ntest edi, edi\njle loc_12D0\nmov eax, edi\nxor ecx, ecx\nmov esi, 0CCCCCCCDh\nnop dword ptr [rax+rax+00h]\nloc_1238:\nmov eax, eax\nadd ecx, 1\nmov rdx, rax\nimul rax, rsi\nshr rax, 23h\ncmp edx, 9\njg short loc_1238\npxor xmm1, xmm1\nmov r12d, ebp\nxor r14d, r14d\nmov r13d, 0CCCCCCCDh\ncvtsi2sd xmm1, ecx; y\nnop dword ptr [rax+00000000h]\nloc_1268:\nmov ebx, r12d\nmov edx, r12d\npxor xmm0, xmm0\nmovsd [rsp+38h+var_30], xmm1\nimul rbx, r13\nshr rbx, 23h\nlea eax, [rbx+rbx*4]\nadd eax, eax\nsub edx, eax\ncvtsi2sd xmm0, edx; x\ncall _pow\nmov eax, r12d\nmovsd xmm1, [rsp+38h+var_30]\nmov r12d, ebx\nmovapd xmm2, xmm0\npxor xmm0, xmm0\ncmp eax, 9\ncvtsi2sd xmm0, r14d\naddsd xmm0, xmm2\ncvttsd2si r14d, xmm0\njg short loc_1268\nloc_12B7:\nxor eax, eax\ncmp ebp, r14d\nsetz al\nadd rsp, 10h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_12D0:\nxor r14d, r14d\njmp short loc_12B7", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1210(int a1)\n{\n unsigned int v1; // eax\n int v2; // ecx\n int v3; // edx\n unsigned int v4; // r12d\n int v5; // r14d\n double v6; // xmm1_8\n double v7; // xmm0_8\n int v8; // eax\n\n if ( a1 <= 0 )\n {\n v5 = 0;\n }\n else\n {\n v1 = a1;\n v2 = 0;\n do\n {\n ++v2;\n v3 = v1;\n v1 /= 0xAu;\n }\n while ( v3 > 9 );\n v4 = a1;\n v5 = 0;\n v6 = (double)v2;\n do\n {\n v7 = pow((double)(v4 % 0xA), v6);\n v8 = v4;\n v4 /= 0xAu;\n v5 = (int)((double)v5 + v7);\n }\n while ( v8 > 9 );\n }\n return a1 == v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1210(int a1) {\n unsigned int v1;\n int v2;\n int v3;\n unsigned int v4;\n int v5;\n double v6;\n double v7;\n int v8;\n if (a1 <= 0) {\n v5 = 0;\n } else {\n v1 = a1;\n v2 = 0;\n do {\n ++v2;\n v3 = v1;\n v1 /= 10u;\n } while (v3 > 9);\n v4 = a1;\n v5 = 0;\n v6 = (double)v2;\n do {\n v7 = pow((double)(v4 % 10), v6);\n v8 = v4;\n v4 /= 10u;\n v5 = (int)((double)v5 + v7);\n } while (v8 > 9);\n }\n return a1 == v5;\n}", + "ida_pseudo_norm": "uint8_t func0(int a1) {\n unsigned int v1;\n int v2;\n int v3;\n unsigned int v4;\n int v5;\n double v6;\n double v7;\n int v8;\n if (a1 <= 0) {\n v5 = 0;\n } else {\n v1 = a1;\n v2 = 0;\n do {\n ++v2;\n v3 = v1;\n v1 /= 10u;\n } while (v3 > 9);\n v4 = a1;\n v5 = 0;\n v6 = (double)v2;\n do {\n v7 = pow((double)(v4 % 10), v6);\n v8 = v4;\n v4 /= 10u;\n v5 = (int)((double)v5 + v7);\n } while (v8 > 9);\n }\n return a1 == v5;\n}" + }, + { + "index": 599, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "double* func0(int number) {\n static double result[2];\n int total = 0;\n for (int value = 1; value <= number; value++) {\n total += value;\n }\n double average = (double)total / number;\n result[0] = total;\n result[1] = average;\n return result;\n}", + "test": "int main() {\n\n double* result;\n\n\n\n result = func0(10);\n\n assert(result[0] == 55 && result[1] == 5.5);\n\n\n\n result = func0(15);\n\n assert(result[0] == 120 && result[1] == 8.0);\n\n\n\n result = func0(20);\n\n assert(result[0] == 210 && result[1] == 10.5);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmovl $0x0,-0x10(%rbp)\nmovl $0x1,-0xc(%rbp)\njmp 116e \nmov -0xc(%rbp),%eax\nadd %eax,-0x10(%rbp)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x14(%rbp),%eax\njle 1164 \ncvtsi2sdl -0x10(%rbp),%xmm0\ncvtsi2sdl -0x14(%rbp),%xmm1\ndivsd %xmm1,%xmm0\nmovsd %xmm0,-0x8(%rbp)\ncvtsi2sdl -0x10(%rbp),%xmm0\nmovsd %xmm0,0x2e8a(%rip)\nmovsd -0x8(%rbp),%xmm0\nmovsd %xmm0,0x2e85(%rip)\nlea 0x2e76(%rip),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_10], 0\nmov [rbp+var_C], 1\njmp short loc_116E\nloc_1164:\nmov eax, [rbp+var_C]\nadd [rbp+var_10], eax\nadd [rbp+var_C], 1\nloc_116E:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_14]\njle short loc_1164\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_10]\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_14]\ndivsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_10]\nmovsd cs:result_1, xmm0\nmovsd xmm0, [rbp+var_8]\nmovsd cs:qword_4028, xmm0\nlea rax, result_1\npop rbp\nretn", + "ida_pseudo": "__int64 *__fastcall func0(int a1)\n{\n int v2; // [rsp+4h] [rbp-10h]\n int i; // [rsp+8h] [rbp-Ch]\n\n v2 = 0;\n for ( i = 1; i <= a1; ++i )\n v2 += i;\n *(double *)&result_1 = (double)v2;\n *(double *)&qword_4028 = (double)v2 / (double)a1;\n return &result_1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_10], 0\nmov [rbp+var_C], 1\njmp short loc_116E\nloc_1164:\nmov eax, [rbp+var_C]\nadd [rbp+var_10], eax\nadd [rbp+var_C], 1\nloc_116E:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_14]\njle short loc_1164\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_10]\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_14]\ndivsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_10]\nmovsd cs:qword_4020, xmm0\nmovsd xmm0, [rbp+var_8]\nmovsd cs:qword_4028, xmm0\nlea rax, qword_4020\npop rbp\nretn", + "ida_strip_pseudo": "__int64 *__fastcall sub_1149(int a1)\n{\n int v2; // [rsp+4h] [rbp-10h]\n int i; // [rsp+8h] [rbp-Ch]\n\n v2 = 0;\n for ( i = 1; i <= a1; ++i )\n v2 += i;\n *(double *)&qword_4020 = (double)v2;\n *(double *)&qword_4028 = (double)v2 / (double)a1;\n return &qword_4020;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long *sub_1149(int a1) {\n int v2;\n int i;\n v2 = 0;\n for (i = 1; i <= a1; ++i) v2 += i;\n *(double *)&qword_4020 = (double)v2;\n *(double *)&qword_4028 = (double)v2 / (double)a1;\n return &qword_4020;\n}", + "ida_pseudo_norm": "long long *func0(int a1) {\n int v2;\n int i;\n v2 = 0;\n for (i = 1; i <= a1; ++i) v2 += i;\n *(double *)&result_1 = (double)v2;\n *(double *)&qword_4028 = (double)v2 / (double)a1;\n return &result_1;\n}" + }, + { + "index": 599, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "double* func0(int number) {\n static double result[2];\n int total = 0;\n for (int value = 1; value <= number; value++) {\n total += value;\n }\n double average = (double)total / number;\n result[0] = total;\n result[1] = average;\n return result;\n}", + "test": "int main() {\n\n double* result;\n\n\n\n result = func0(10);\n\n assert(result[0] == 55 && result[1] == 5.5);\n\n\n\n result = func0(15);\n\n assert(result[0] == 120 && result[1] == 8.0);\n\n\n\n result = func0(20);\n\n assert(result[0] == 210 && result[1] == 10.5);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\njle 1193 \nlea 0x1(%rdi),%ecx\nmov $0x1,%eax\nmov $0x0,%edx\nadd %eax,%edx\nadd $0x1,%eax\ncmp %ecx,%eax\njne 115e \npxor %xmm0,%xmm0\ncvtsi2sd %edx,%xmm0\nmovsd %xmm0,0x2ea9(%rip)\npxor %xmm1,%xmm1\ncvtsi2sd %edi,%xmm1\ndivsd %xmm1,%xmm0\nmovsd %xmm0,0x2e9d(%rip)\nlea 0x2e8e(%rip),%rax\nretq\nmov $0x0,%edx\njmp 1167 \n", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njle short loc_1193\nlea ecx, [rdi+1]\nmov eax, 1\nmov edx, 0\nloc_115E:\nadd edx, eax\nadd eax, 1\ncmp eax, ecx\njnz short loc_115E\nloc_1167:\npxor xmm0, xmm0\ncvtsi2sd xmm0, edx\nmovsd cs:result_1, xmm0\npxor xmm1, xmm1\ncvtsi2sd xmm1, edi\ndivsd xmm0, xmm1\nmovsd cs:qword_4028, xmm0\nlea rax, result_1\nretn\nloc_1193:\nmov edx, 0\njmp short loc_1167", + "ida_pseudo": "__int64 *__fastcall func0(int a1)\n{\n int v1; // eax\n int v2; // edx\n\n if ( a1 <= 0 )\n {\n v2 = 0;\n }\n else\n {\n v1 = 1;\n v2 = 0;\n do\n v2 += v1++;\n while ( v1 != a1 + 1 );\n }\n *(double *)&result_1 = (double)v2;\n *(double *)&qword_4028 = (double)v2 / (double)a1;\n return &result_1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ntest edi, edi\njle short loc_1193\nlea ecx, [rdi+1]\nmov eax, 1\nmov edx, 0\nloc_115E:\nadd edx, eax\nadd eax, 1\ncmp eax, ecx\njnz short loc_115E\nloc_1167:\npxor xmm0, xmm0\ncvtsi2sd xmm0, edx\nmovsd cs:qword_4020, xmm0\npxor xmm1, xmm1\ncvtsi2sd xmm1, edi\ndivsd xmm0, xmm1\nmovsd cs:qword_4028, xmm0\nlea rax, qword_4020\nretn\nloc_1193:\nmov edx, 0\njmp short loc_1167", + "ida_strip_pseudo": "__int64 *__fastcall sub_1149(int a1)\n{\n int v1; // eax\n int v2; // edx\n\n if ( a1 <= 0 )\n {\n v2 = 0;\n }\n else\n {\n v1 = 1;\n v2 = 0;\n do\n v2 += v1++;\n while ( v1 != a1 + 1 );\n }\n *(double *)&qword_4020 = (double)v2;\n *(double *)&qword_4028 = (double)v2 / (double)a1;\n return &qword_4020;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long *sub_1149(int a1) {\n int v1;\n int v2;\n if (a1 <= 0) {\n v2 = 0;\n } else {\n v1 = 1;\n v2 = 0;\n do\n v2 += v1++;\n while (v1 != a1 + 1);\n }\n *(double *)&qword_4020 = (double)v2;\n *(double *)&qword_4028 = (double)v2 / (double)a1;\n return &qword_4020;\n}", + "ida_pseudo_norm": "long long *func0(int a1) {\n int v1;\n int v2;\n if (a1 <= 0) {\n v2 = 0;\n } else {\n v1 = 1;\n v2 = 0;\n do\n v2 += v1++;\n while (v1 != a1 + 1);\n }\n *(double *)&result_1 = (double)v2;\n *(double *)&qword_4028 = (double)v2 / (double)a1;\n return &result_1;\n}" + }, + { + "index": 600, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "bool func0(int n) {\n if ((n ^ 1) == n + 1) {\n return true;\n } else {\n return false;\n }\n}", + "test": "int main() {\n\n assert(func0(1) == false);\n\n assert(func0(2) == true);\n\n assert(func0(3) == false);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nxor $0x1,%eax\nmov %eax,%edx\nmov -0x4(%rbp),%eax\nadd $0x1,%eax\ncmp %eax,%edx\njne 116d \nmov $0x1,%eax\njmp 1172 \nmov $0x0,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov eax, [rbp+var_4]\nxor eax, 1\nmov edx, eax\nmov eax, [rbp+var_4]\nadd eax, 1\ncmp edx, eax\njnz short loc_116D\nmov eax, 1\njmp short loc_1172\nloc_116D:\nmov eax, 0\nloc_1172:\npop rbp\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(int a1)\n{\n return (a1 ^ 1) == a1 + 1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov eax, [rbp+var_4]\nxor eax, 1\nmov edx, eax\nmov eax, [rbp+var_4]\nadd eax, 1\ncmp edx, eax\njnz short loc_116D\nmov eax, 1\njmp short loc_1172\nloc_116D:\nmov eax, 0\nloc_1172:\npop rbp\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1149(int a1)\n{\n return (a1 ^ 1) == a1 + 1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1149(int a1) { return (a1 ^ 1) == a1 + 1; }", + "ida_pseudo_norm": "uint8_t func0(int a1) { return (a1 ^ 1) == a1 + 1; }" + }, + { + "index": 601, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\ntypedef struct {\n\n int a;\n\n int b;\n\n} Pair;\n\n\n\n", + "func": "int func0(Pair arr[], int n) {\n int max = 0;\n int mcl[100];\n for (int i = 0; i < n; i++) {\n mcl[i] = 1;\n }\n for (int i = 1; i < n; i++) {\n for (int j = 0; j < i; j++) {\n if (arr[i].a > arr[j].b && mcl[i] < mcl[j] + 1) {\n mcl[i] = mcl[j] + 1;\n }\n }\n }\n for (int i = 0; i < n; i++) {\n if (max < mcl[i]) {\n max = mcl[i];\n }\n }\n return max;\n}", + "test": "int main() {\n\n Pair arr1[] = {{5, 24}, {15, 25}, {27, 40}, {50, 60}};\n\n assert(func0(arr1, 4) == 3);\n\n\n\n Pair arr2[] = {{1, 2}, {3, 4}, {5, 6}, {7, 8}};\n\n assert(func0(arr2, 4) == 4);\n\n\n\n Pair arr3[] = {{19, 10}, {11, 12}, {13, 14}, {15, 16}, {31, 54}};\n\n assert(func0(arr3, 5) == 5);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x1d0,%rsp\nmov %rdi,-0x1c8(%rbp)\nmov %esi,-0x1cc(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovl $0x0,-0x1b4(%rbp)\nmovl $0x0,-0x1b0(%rbp)\njmp 11c4 \nmov -0x1b0(%rbp),%eax\ncltq\nmovl $0x1,-0x1a0(%rbp,%rax,4)\naddl $0x1,-0x1b0(%rbp)\nmov -0x1b0(%rbp),%eax\ncmp -0x1cc(%rbp),%eax\njl 11aa \nmovl $0x1,-0x1ac(%rbp)\njmpq 1290 \nmovl $0x0,-0x1a8(%rbp)\njmpq 1277 \nmov -0x1ac(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x1c8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x1a8(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x1c8(%rbp),%rax\nadd %rcx,%rax\nmov 0x4(%rax),%eax\ncmp %eax,%edx\njle 1270 \nmov -0x1a8(%rbp),%eax\ncltq\nmov -0x1a0(%rbp,%rax,4),%edx\nmov -0x1ac(%rbp),%eax\ncltq\nmov -0x1a0(%rbp,%rax,4),%eax\ncmp %eax,%edx\njl 1270 \nmov -0x1a8(%rbp),%eax\ncltq\nmov -0x1a0(%rbp,%rax,4),%eax\nlea 0x1(%rax),%edx\nmov -0x1ac(%rbp),%eax\ncltq\nmov %edx,-0x1a0(%rbp,%rax,4)\naddl $0x1,-0x1a8(%rbp)\nmov -0x1a8(%rbp),%eax\ncmp -0x1ac(%rbp),%eax\njl 11f0 \naddl $0x1,-0x1ac(%rbp)\nmov -0x1ac(%rbp),%eax\ncmp -0x1cc(%rbp),%eax\njl 11e1 \nmovl $0x0,-0x1a4(%rbp)\njmp 12e1 \nmov -0x1a4(%rbp),%eax\ncltq\nmov -0x1a0(%rbp,%rax,4),%eax\ncmp %eax,-0x1b4(%rbp)\njge 12da \nmov -0x1a4(%rbp),%eax\ncltq\nmov -0x1a0(%rbp,%rax,4),%eax\nmov %eax,-0x1b4(%rbp)\naddl $0x1,-0x1a4(%rbp)\nmov -0x1a4(%rbp),%eax\ncmp -0x1cc(%rbp),%eax\njl 12ae \nmov -0x1b4(%rbp),%eax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 1309 \ncallq 1060 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 1D0h\nmov [rbp+var_1C8], rdi\nmov [rbp+var_1CC], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_1B4], 0\nmov [rbp+var_1B0], 0\njmp short loc_11C4\nloc_11AA:\nmov eax, [rbp+var_1B0]\ncdqe\nmov [rbp+rax*4+var_1A0], 1\nadd [rbp+var_1B0], 1\nloc_11C4:\nmov eax, [rbp+var_1B0]\ncmp eax, [rbp+var_1CC]\njl short loc_11AA\nmov [rbp+var_1AC], 1\njmp loc_1290\nloc_11E1:\nmov [rbp+var_1A8], 0\njmp loc_1277\nloc_11F0:\nmov eax, [rbp+var_1AC]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_1C8]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_1A8]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_1C8]\nadd rax, rcx\nmov eax, [rax+4]\ncmp edx, eax\njle short loc_1270\nmov eax, [rbp+var_1A8]\ncdqe\nmov edx, [rbp+rax*4+var_1A0]\nmov eax, [rbp+var_1AC]\ncdqe\nmov eax, [rbp+rax*4+var_1A0]\ncmp edx, eax\njl short loc_1270\nmov eax, [rbp+var_1A8]\ncdqe\nmov eax, [rbp+rax*4+var_1A0]\nlea edx, [rax+1]\nmov eax, [rbp+var_1AC]\ncdqe\nmov [rbp+rax*4+var_1A0], edx\nloc_1270:\nadd [rbp+var_1A8], 1\nloc_1277:\nmov eax, [rbp+var_1A8]\ncmp eax, [rbp+var_1AC]\njl loc_11F0\nadd [rbp+var_1AC], 1\nloc_1290:\nmov eax, [rbp+var_1AC]\ncmp eax, [rbp+var_1CC]\njl loc_11E1\nmov [rbp+var_1A4], 0\njmp short loc_12E1\nloc_12AE:\nmov eax, [rbp+var_1A4]\ncdqe\nmov eax, [rbp+rax*4+var_1A0]\ncmp [rbp+var_1B4], eax\njge short loc_12DA\nmov eax, [rbp+var_1A4]\ncdqe\nmov eax, [rbp+rax*4+var_1A0]\nmov [rbp+var_1B4], eax\nloc_12DA:\nadd [rbp+var_1A4], 1\nloc_12E1:\nmov eax, [rbp+var_1A4]\ncmp eax, [rbp+var_1CC]\njl short loc_12AE\nmov eax, [rbp+var_1B4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1309\ncall ___stack_chk_fail\nlocret_1309:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+1Ch] [rbp-1B4h]\n int i; // [rsp+20h] [rbp-1B0h]\n int j; // [rsp+24h] [rbp-1ACh]\n int k; // [rsp+28h] [rbp-1A8h]\n int m; // [rsp+2Ch] [rbp-1A4h]\n _DWORD v8[102]; // [rsp+30h] [rbp-1A0h]\n unsigned __int64 v9; // [rsp+1C8h] [rbp-8h]\n\n v9 = __readfsqword(0x28u);\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n v8[i] = 1;\n for ( j = 1; j < a2; ++j )\n {\n for ( k = 0; k < j; ++k )\n {\n if ( *(_DWORD *)(8LL * j + a1) > *(_DWORD *)(8LL * k + a1 + 4) && v8[k] >= v8[j] )\n v8[j] = v8[k] + 1;\n }\n }\n for ( m = 0; m < a2; ++m )\n {\n if ( (signed int)v3 < v8[m] )\n v3 = v8[m];\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 1D0h\nmov [rbp+var_1C8], rdi\nmov [rbp+var_1CC], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_1B4], 0\nmov [rbp+var_1B0], 0\njmp short loc_11C4\nloc_11AA:\nmov eax, [rbp+var_1B0]\ncdqe\nmov [rbp+rax*4+var_1A0], 1\nadd [rbp+var_1B0], 1\nloc_11C4:\nmov eax, [rbp+var_1B0]\ncmp eax, [rbp+var_1CC]\njl short loc_11AA\nmov [rbp+var_1AC], 1\njmp loc_1290\nloc_11E1:\nmov [rbp+var_1A8], 0\njmp loc_1277\nloc_11F0:\nmov eax, [rbp+var_1AC]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_1C8]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_1A8]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_1C8]\nadd rax, rcx\nmov eax, [rax+4]\ncmp edx, eax\njle short loc_1270\nmov eax, [rbp+var_1A8]\ncdqe\nmov edx, [rbp+rax*4+var_1A0]\nmov eax, [rbp+var_1AC]\ncdqe\nmov eax, [rbp+rax*4+var_1A0]\ncmp edx, eax\njl short loc_1270\nmov eax, [rbp+var_1A8]\ncdqe\nmov eax, [rbp+rax*4+var_1A0]\nlea edx, [rax+1]\nmov eax, [rbp+var_1AC]\ncdqe\nmov [rbp+rax*4+var_1A0], edx\nloc_1270:\nadd [rbp+var_1A8], 1\nloc_1277:\nmov eax, [rbp+var_1A8]\ncmp eax, [rbp+var_1AC]\njl loc_11F0\nadd [rbp+var_1AC], 1\nloc_1290:\nmov eax, [rbp+var_1AC]\ncmp eax, [rbp+var_1CC]\njl loc_11E1\nmov [rbp+var_1A4], 0\njmp short loc_12E1\nloc_12AE:\nmov eax, [rbp+var_1A4]\ncdqe\nmov eax, [rbp+rax*4+var_1A0]\ncmp [rbp+var_1B4], eax\njge short loc_12DA\nmov eax, [rbp+var_1A4]\ncdqe\nmov eax, [rbp+rax*4+var_1A0]\nmov [rbp+var_1B4], eax\nloc_12DA:\nadd [rbp+var_1A4], 1\nloc_12E1:\nmov eax, [rbp+var_1A4]\ncmp eax, [rbp+var_1CC]\njl short loc_12AE\nmov eax, [rbp+var_1B4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1309\ncall ___stack_chk_fail\nlocret_1309:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+1Ch] [rbp-1B4h]\n int i; // [rsp+20h] [rbp-1B0h]\n int j; // [rsp+24h] [rbp-1ACh]\n int k; // [rsp+28h] [rbp-1A8h]\n int m; // [rsp+2Ch] [rbp-1A4h]\n _DWORD v8[102]; // [rsp+30h] [rbp-1A0h]\n unsigned __int64 v9; // [rsp+1C8h] [rbp-8h]\n\n v9 = __readfsqword(0x28u);\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n v8[i] = 1;\n for ( j = 1; j < a2; ++j )\n {\n for ( k = 0; k < j; ++k )\n {\n if ( *(_DWORD *)(8LL * j + a1) > *(_DWORD *)(8LL * k + a1 + 4) && v8[k] >= v8[j] )\n v8[j] = v8[k] + 1;\n }\n }\n for ( m = 0; m < a2; ++m )\n {\n if ( (signed int)v3 < v8[m] )\n v3 = v8[m];\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n unsigned int v3;\n int i;\n int j;\n int k;\n int m;\n uint32_t v8[102];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n v3 = 0;\n for (i = 0; i < a2; ++i) v8[i] = 1;\n for (j = 1; j < a2; ++j) {\n for (k = 0; k < j; ++k) {\n if (*(uint32_t *)(8LL * j + a1) > *(uint32_t *)(8LL * k + a1 + 4) &&\n v8[k] >= v8[j])\n v8[j] = v8[k] + 1;\n }\n }\n for (m = 0; m < a2; ++m) {\n if ((signed int)v3 < v8[m]) v3 = v8[m];\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n int j;\n int k;\n int m;\n uint32_t v8[102];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n v3 = 0;\n for (i = 0; i < a2; ++i) v8[i] = 1;\n for (j = 1; j < a2; ++j) {\n for (k = 0; k < j; ++k) {\n if (*(uint32_t *)(8LL * j + a1) > *(uint32_t *)(8LL * k + a1 + 4) &&\n v8[k] >= v8[j])\n v8[j] = v8[k] + 1;\n }\n }\n for (m = 0; m < a2; ++m) {\n if ((signed int)v3 < v8[m]) v3 = v8[m];\n }\n return v3;\n}" + }, + { + "index": 601, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\ntypedef struct {\n\n int a;\n\n int b;\n\n} Pair;\n\n\n\n", + "func": "int func0(Pair arr[], int n) {\n int max = 0;\n int mcl[100];\n for (int i = 0; i < n; i++) {\n mcl[i] = 1;\n }\n for (int i = 1; i < n; i++) {\n for (int j = 0; j < i; j++) {\n if (arr[i].a > arr[j].b && mcl[i] < mcl[j] + 1) {\n mcl[i] = mcl[j] + 1;\n }\n }\n }\n for (int i = 0; i < n; i++) {\n if (max < mcl[i]) {\n max = mcl[i];\n }\n }\n return max;\n}", + "test": "int main() {\n\n Pair arr1[] = {{5, 24}, {15, 25}, {27, 40}, {50, 60}};\n\n assert(func0(arr1, 4) == 3);\n\n\n\n Pair arr2[] = {{1, 2}, {3, 4}, {5, 6}, {7, 8}};\n\n assert(func0(arr2, 4) == 4);\n\n\n\n Pair arr3[] = {{19, 10}, {11, 12}, {13, 14}, {15, 16}, {31, 54}};\n\n assert(func0(arr3, 5) == 5);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x1a8,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x198(%rsp)\nxor %eax,%eax\ntest %esi,%esi\njle 11a5 \nmov %rsp,%rax\nlea -0x1(%rsi),%edx\nlea 0x4(%rsp,%rdx,4),%rdx\nmovl $0x1,(%rax)\nadd $0x4,%rax\ncmp %rdx,%rax\njne 1196 \ncmp $0x1,%esi\njle 11fa \nlea 0x4(%rsp),%r9\nlea -0x2(%rsi),%r10d\nadd $0x2,%r10\nmov $0x1,%ecx\njmp 11eb \nadd $0x1,%rax\ncmp %rcx,%rax\nje 11de \ncmp 0x4(%rdi,%rax,8),%r8d\njle 11be \nmov (%rsp,%rax,4),%edx\ncmp (%r9),%edx\njl 11be \nadd $0x1,%edx\nmov %edx,(%r9)\njmp 11be \nadd $0x1,%rcx\nadd $0x4,%r9\ncmp %r10,%rcx\nje 1203 \ntest %ecx,%ecx\njle 11de \nmov (%rdi,%rcx,8),%r8d\nmov $0x0,%eax\njmp 11c7 \nje 123a \nmov $0x0,%edx\njmp 121d \nmov $0x0,%eax\nmov $0x0,%edx\nmov (%rsp,%rax,4),%ecx\ncmp %ecx,%edx\ncmovl %ecx,%edx\nadd $0x1,%rax\ncmp %eax,%esi\njg 120d \nmov 0x198(%rsp),%rax\nxor %fs:0x28,%rax\njne 1249 \nmov %edx,%eax\nadd $0x1a8,%rsp\nretq\ncmpl $0x0,(%rsp)\nmov $0x0,%edx\ncmovns (%rsp),%edx\njmp 121d \ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 1A8h\nmov rax, fs:28h\nmov [rsp+1A8h+var_10], rax\nxor eax, eax\ntest esi, esi\njle short loc_11F4\nmov rax, rsp\nmovsxd rdx, esi\nlea rdx, [rax+rdx*4]\nloc_1195:\nmov dword ptr [rax], 1\nadd rax, 4\ncmp rax, rdx\njnz short loc_1195\ncmp esi, 1\njle short loc_11FB\nlea r9, [rsp+1A8h+var_1A4]\nmov r10d, esi\nmov ecx, 1\njmp short loc_11E5\nloc_11B8:\nadd rax, 1\ncmp rcx, rax\njz short loc_11D8\nloc_11C1:\ncmp r8d, [rdi+rax*8+4]\njle short loc_11B8\nmov edx, [rsp+rax*4+1A8h+var_1A8]\ncmp edx, [r9]\njl short loc_11B8\nadd edx, 1\nmov [r9], edx\njmp short loc_11B8\nloc_11D8:\nadd rcx, 1\nadd r9, 4\ncmp rcx, r10\njz short loc_11FB\nloc_11E5:\ntest ecx, ecx\njle short loc_1237\nmov r8d, [rdi+rcx*8]\nmov eax, 0\njmp short loc_11C1\nloc_11F4:\nmov edx, 0\njmp short loc_121A\nloc_11FB:\nmov rax, rsp\nmovsxd rsi, esi\nlea rsi, [rax+rsi*4]\nmov edx, 0\nloc_120A:\nmov ecx, [rax]\ncmp edx, ecx\ncmovl edx, ecx\nadd rax, 4\ncmp rax, rsi\njnz short loc_120A\nloc_121A:\nmov rax, [rsp+1A8h+var_10]\nsub rax, fs:28h\njnz short loc_1241\nmov eax, edx\nadd rsp, 1A8h\nretn\nloc_1237:\nadd rcx, 1\nadd r9, 4\njmp short loc_11E5\nloc_1241:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int *v2; // rax\n char *v3; // r9\n __int64 i; // rcx\n __int64 v5; // rax\n int v6; // edx\n int v7; // r8d\n unsigned int v8; // edx\n int *v9; // rax\n int *v10; // rsi\n int v12; // [rsp+0h] [rbp-1A8h] BYREF\n char v13; // [rsp+4h] [rbp-1A4h] BYREF\n unsigned __int64 v14; // [rsp+198h] [rbp-10h]\n\n v14 = __readfsqword(0x28u);\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = &v12;\n do\n *v2++ = 1;\n while ( v2 != &v12 + a2 );\n if ( a2 > 1 )\n {\n v3 = &v13;\n for ( i = 1LL; i != a2; ++i )\n {\n while ( (int)i <= 0 )\n {\n ++i;\n v3 += 4;\n }\n v7 = *(_DWORD *)(a1 + 8 * i);\n v5 = 0LL;\n do\n {\n if ( v7 > *(_DWORD *)(a1 + 8 * v5 + 4) )\n {\n v6 = *(&v12 + v5);\n if ( v6 >= *(_DWORD *)v3 )\n *(_DWORD *)v3 = v6 + 1;\n }\n ++v5;\n }\n while ( i != v5 );\n v3 += 4;\n }\n }\n v9 = &v12;\n v10 = &v12 + a2;\n v8 = 0;\n do\n {\n if ( (int)v8 < *v9 )\n v8 = *v9;\n ++v9;\n }\n while ( v9 != v10 );\n }\n return v8;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nsub rsp, 1A8h\nmov rax, fs:28h\nmov [rsp+1A8h+var_10], rax\nxor eax, eax\ntest esi, esi\njle short loc_11F4\nmov rax, rsp\nmovsxd rdx, esi\nlea rdx, [rax+rdx*4]\nloc_1195:\nmov dword ptr [rax], 1\nadd rax, 4\ncmp rax, rdx\njnz short loc_1195\ncmp esi, 1\njle short loc_11FB\nlea r9, [rsp+1A8h+var_1A4]\nmov r10d, esi\nmov ecx, 1\njmp short loc_11E5\nloc_11B8:\nadd rax, 1\ncmp rcx, rax\njz short loc_11D8\nloc_11C1:\ncmp r8d, [rdi+rax*8+4]\njle short loc_11B8\nmov edx, [rsp+rax*4+1A8h+var_1A8]\ncmp edx, [r9]\njl short loc_11B8\nadd edx, 1\nmov [r9], edx\njmp short loc_11B8\nloc_11D8:\nadd rcx, 1\nadd r9, 4\ncmp rcx, r10\njz short loc_11FB\nloc_11E5:\ntest ecx, ecx\njle short loc_1237\nmov r8d, [rdi+rcx*8]\nmov eax, 0\njmp short loc_11C1\nloc_11F4:\nmov edx, 0\njmp short loc_121A\nloc_11FB:\nmov rax, rsp\nmovsxd rsi, esi\nlea rsi, [rax+rsi*4]\nmov edx, 0\nloc_120A:\nmov ecx, [rax]\ncmp edx, ecx\ncmovl edx, ecx\nadd rax, 4\ncmp rax, rsi\njnz short loc_120A\nloc_121A:\nmov rax, [rsp+1A8h+var_10]\nsub rax, fs:28h\njnz short loc_1241\nmov eax, edx\nadd rsp, 1A8h\nretn\nloc_1237:\nadd rcx, 1\nadd r9, 4\njmp short loc_11E5\nloc_1241:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int *v2; // rax\n char *v3; // r9\n __int64 i; // rcx\n __int64 v5; // rax\n int v6; // edx\n int v7; // r8d\n unsigned int v8; // edx\n int *v9; // rax\n int *v10; // rsi\n int v12; // [rsp+0h] [rbp-1A8h] BYREF\n char v13; // [rsp+4h] [rbp-1A4h] BYREF\n unsigned __int64 v14; // [rsp+198h] [rbp-10h]\n\n v14 = __readfsqword(0x28u);\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = &v12;\n do\n *v2++ = 1;\n while ( v2 != &v12 + a2 );\n if ( a2 > 1 )\n {\n v3 = &v13;\n for ( i = 1LL; i != a2; ++i )\n {\n while ( (int)i <= 0 )\n {\n ++i;\n v3 += 4;\n }\n v7 = *(_DWORD *)(a1 + 8 * i);\n v5 = 0LL;\n do\n {\n if ( v7 > *(_DWORD *)(a1 + 8 * v5 + 4) )\n {\n v6 = *(&v12 + v5);\n if ( v6 >= *(_DWORD *)v3 )\n *(_DWORD *)v3 = v6 + 1;\n }\n ++v5;\n }\n while ( i != v5 );\n v3 += 4;\n }\n }\n v9 = &v12;\n v10 = &v12 + a2;\n v8 = 0;\n do\n {\n if ( (int)v8 < *v9 )\n v8 = *v9;\n ++v9;\n }\n while ( v9 != v10 );\n }\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int *v2;\n char *v3;\n long long i;\n long long v5;\n int v6;\n int v7;\n unsigned int v8;\n int *v9;\n int *v10;\n int v12;\n char v13;\n unsigned long long v14;\n v14 = __readfsqword(40u);\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = &v12;\n do\n *v2++ = 1;\n while (v2 != &v12 + a2);\n if (a2 > 1) {\n v3 = &v13;\n for (i = 1LL; i != a2; ++i) {\n while ((int)i <= 0) {\n ++i;\n v3 += 4;\n }\n v7 = *(uint32_t *)(a1 + 8 * i);\n v5 = 0LL;\n do {\n if (v7 > *(uint32_t *)(a1 + 8 * v5 + 4)) {\n v6 = *(&v12 + v5);\n if (v6 >= *(uint32_t *)v3) *(uint32_t *)v3 = v6 + 1;\n }\n ++v5;\n } while (i != v5);\n v3 += 4;\n }\n }\n v9 = &v12;\n v10 = &v12 + a2;\n v8 = 0;\n do {\n if ((int)v8 < *v9) v8 = *v9;\n ++v9;\n } while (v9 != v10);\n }\n return v8;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int *v2;\n char *v3;\n long long i;\n long long v5;\n int v6;\n int v7;\n unsigned int v8;\n int *v9;\n int *v10;\n int v12;\n char v13;\n unsigned long long v14;\n v14 = __readfsqword(40u);\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = &v12;\n do\n *v2++ = 1;\n while (v2 != &v12 + a2);\n if (a2 > 1) {\n v3 = &v13;\n for (i = 1LL; i != a2; ++i) {\n while ((int)i <= 0) {\n ++i;\n v3 += 4;\n }\n v7 = *(uint32_t *)(a1 + 8 * i);\n v5 = 0LL;\n do {\n if (v7 > *(uint32_t *)(a1 + 8 * v5 + 4)) {\n v6 = *(&v12 + v5);\n if (v6 >= *(uint32_t *)v3) *(uint32_t *)v3 = v6 + 1;\n }\n ++v5;\n } while (i != v5);\n v3 += 4;\n }\n }\n v9 = &v12;\n v10 = &v12 + a2;\n v8 = 0;\n do {\n if ((int)v8 < *v9) v8 = *v9;\n ++v9;\n } while (v9 != v10);\n }\n return v8;\n}" + }, + { + "index": 601, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\ntypedef struct {\n\n int a;\n\n int b;\n\n} Pair;\n\n\n\n", + "func": "int func0(Pair arr[], int n) {\n int max = 0;\n int mcl[100];\n for (int i = 0; i < n; i++) {\n mcl[i] = 1;\n }\n for (int i = 1; i < n; i++) {\n for (int j = 0; j < i; j++) {\n if (arr[i].a > arr[j].b && mcl[i] < mcl[j] + 1) {\n mcl[i] = mcl[j] + 1;\n }\n }\n }\n for (int i = 0; i < n; i++) {\n if (max < mcl[i]) {\n max = mcl[i];\n }\n }\n return max;\n}", + "test": "int main() {\n\n Pair arr1[] = {{5, 24}, {15, 25}, {27, 40}, {50, 60}};\n\n assert(func0(arr1, 4) == 3);\n\n\n\n Pair arr2[] = {{1, 2}, {3, 4}, {5, 6}, {7, 8}};\n\n assert(func0(arr2, 4) == 4);\n\n\n\n Pair arr3[] = {{19, 10}, {11, 12}, {13, 14}, {15, 16}, {31, 54}};\n\n assert(func0(arr3, 5) == 5);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x1a8,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x198(%rsp)\nxor %eax,%eax\ntest %esi,%esi\njle 13e9 \nmov %rsp,%r10\nlea -0x1(%rsi),%edx\nlea 0x4(%rsp),%r9\nmov %r10,%rax\nlea (%r9,%rdx,4),%rdx\nnopl 0x0(%rax,%rax,1)\nmovl $0x1,(%rax)\nadd $0x4,%rax\ncmp %rdx,%rax\njne 1350 \ncmp $0x1,%esi\njle 13e9 \nlea -0x2(%rsi),%r11d\nmov $0x1,%ecx\nadd $0x2,%r11\nnopl (%rax)\nmov (%rdi,%rcx,8),%r8d\nxor %eax,%eax\nxchg %ax,%ax\ncmp 0x4(%rdi,%rax,8),%r8d\njle 1396 \nmov (%r10,%rax,4),%edx\ncmp (%r9),%edx\njl 1396 \nadd $0x1,%edx\nmov %edx,(%r9)\nadd $0x1,%rax\ncmp %rax,%rcx\njne 1380 \nadd $0x1,%rcx\nadd $0x4,%r9\ncmp %rcx,%r11\njne 1378 \nxor %eax,%eax\nxor %r8d,%r8d\nnopl 0x0(%rax)\nmov (%r10,%rax,4),%edx\ncmp %edx,%r8d\ncmovl %edx,%r8d\nadd $0x1,%rax\ncmp %eax,%esi\njg 13b8 \nmov 0x198(%rsp),%rax\nxor %fs:0x28,%rax\njne 1404 \nmov %r8d,%eax\nadd $0x1a8,%rsp\nretq\ncmp $0x1,%esi\nje 13f3 \nxor %r8d,%r8d\njmp 13cb \ncmpl $0x0,(%rsp)\nmov $0x0,%r8d\ncmovns (%rsp),%r8d\njmp 13cb \ncallq 1060 <__stack_chk_fail@plt>\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nsub rsp, 1A0h\nmov rax, fs:28h\nmov [rsp+1A8h+var_10], rax\nxor eax, eax\ntest esi, esi\njle loc_13A6\nmov r9, rsp\nmovsxd rdx, esi\nlea rbx, [r9+rdx*4]\nand edx, 1\nmov r10, r9\nmov rax, r9\njz short loc_12F0\nlea rax, [rsp+1A8h+var_1A4]\nmov dword ptr [r9], 1\ncmp rax, rbx\njz short loc_1306\nnop dword ptr [rax]\nloc_12F0:\nmov dword ptr [rax], 1\nadd rax, 8\nmov dword ptr [rax-4], 1\ncmp rax, rbx\njnz short loc_12F0\nloc_1306:\ncmp esi, 1\njz short loc_1353\nlea r8, [rsp+1A8h+var_1A4]\nmov r11d, esi\nmov ecx, 1\nnop dword ptr [rax+rax+00000000h]\nloc_1320:\nmov esi, [rdi+rcx*8]\nxor eax, eax\nnop dword ptr [rax]\nloc_1328:\ncmp esi, [rdi+rax*8+4]\njle short loc_133D\nmov edx, [r9+rax*4]\ncmp edx, [r8]\njl short loc_133D\nadd edx, 1\nmov [r8], edx\nloc_133D:\nadd rax, 1\ncmp rcx, rax\njnz short loc_1328\nadd rcx, 1\nadd r8, 4\ncmp rcx, r11\njnz short loc_1320\nloc_1353:\nxor eax, eax\ntest bl, 4\njz short loc_1370\nmov edx, [r9]\nlea r10, [r9+4]\ncmp eax, edx\ncmovl eax, edx\ncmp r10, rbx\njz short loc_138A\nnop dword ptr [rax+rax+00h]\nloc_1370:\nmov edx, [r10]\ncmp eax, edx\ncmovl eax, edx\nmov edx, [r10+4]\ncmp eax, edx\ncmovl eax, edx\nadd r10, 8\ncmp r10, rbx\njnz short loc_1370\nloc_138A:\nmov rdx, [rsp+1A8h+var_10]\nsub rdx, fs:28h\njnz short loc_13AA\nadd rsp, 1A0h\npop rbx\nretn\nloc_13A6:\nxor eax, eax\njmp short loc_138A\nloc_13AA:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int *v2; // rbx\n int *v3; // r10\n int *v4; // rax\n _DWORD *v5; // r8\n __int64 v6; // r11\n __int64 i; // rcx\n int v8; // esi\n __int64 v9; // rax\n int v10; // edx\n __int64 result; // rax\n int v12; // edx\n int v13; // [rsp+0h] [rbp-1A8h] BYREF\n _BYTE v14[404]; // [rsp+4h] [rbp-1A4h] BYREF\n unsigned __int64 v15; // [rsp+198h] [rbp-10h]\n\n v15 = __readfsqword(0x28u);\n if ( a2 <= 0 )\n return 0LL;\n v2 = (int *)&v14[4 * a2 - 4];\n v3 = &v13;\n v4 = &v13;\n if ( (a2 & 1) == 0 || (v4 = (int *)v14, v13 = 1, v14 != (_BYTE *)v2) )\n {\n do\n {\n *v4 = 1;\n v4 += 2;\n *(v4 - 1) = 1;\n }\n while ( v4 != v2 );\n }\n if ( a2 != 1 )\n {\n v5 = v14;\n v6 = (unsigned int)a2;\n for ( i = 1LL; i != v6; ++i )\n {\n v8 = *(_DWORD *)(a1 + 8 * i);\n v9 = 0LL;\n do\n {\n if ( v8 > *(_DWORD *)(a1 + 8 * v9 + 4) )\n {\n v10 = *(_DWORD *)&v14[4 * v9 - 4];\n if ( v10 >= *v5 )\n *v5 = v10 + 1;\n }\n ++v9;\n }\n while ( i != v9 );\n ++v5;\n }\n }\n result = 0LL;\n if ( ((unsigned __int8)v2 & 4) == 0 )\n goto LABEL_26;\n v3 = (int *)v14;\n if ( v13 > 0 )\n result = (unsigned int)v13;\n if ( v14 != (_BYTE *)v2 )\n {\nLABEL_26:\n do\n {\n if ( (int)result < *v3 )\n result = (unsigned int)*v3;\n v12 = v3[1];\n if ( (int)result < v12 )\n result = (unsigned int)v12;\n v3 += 2;\n }\n while ( v3 != v2 );\n }\n return result;\n}", + "ida_strip_asm": "sub_12A0:\nendbr64\npush rbx\nsub rsp, 1A0h\nmov rax, fs:28h\nmov [rsp+1A8h+var_10], rax\nxor eax, eax\ntest esi, esi\njle loc_13A6\nmov r9, rsp\nmovsxd rdx, esi\nlea rbx, [r9+rdx*4]\nand edx, 1\nmov r10, r9\nmov rax, r9\njz short loc_12F0\nlea rax, [rsp+1A8h+var_1A4]\nmov dword ptr [r9], 1\ncmp rax, rbx\njz short loc_1306\nnop dword ptr [rax]\nloc_12F0:\nmov dword ptr [rax], 1\nadd rax, 8\nmov dword ptr [rax-4], 1\ncmp rax, rbx\njnz short loc_12F0\nloc_1306:\ncmp esi, 1\njz short loc_1353\nlea r8, [rsp+1A8h+var_1A4]\nmov r11d, esi\nmov ecx, 1\nnop dword ptr [rax+rax+00000000h]\nloc_1320:\nmov esi, [rdi+rcx*8]\nxor eax, eax\nnop dword ptr [rax]\nloc_1328:\ncmp esi, [rdi+rax*8+4]\njle short loc_133D\nmov edx, [r9+rax*4]\ncmp edx, [r8]\njl short loc_133D\nadd edx, 1\nmov [r8], edx\nloc_133D:\nadd rax, 1\ncmp rcx, rax\njnz short loc_1328\nadd rcx, 1\nadd r8, 4\ncmp rcx, r11\njnz short loc_1320\nloc_1353:\nxor eax, eax\ntest bl, 4\njz short loc_1370\nmov edx, [r9]\nlea r10, [r9+4]\ncmp eax, edx\ncmovl eax, edx\ncmp r10, rbx\njz short loc_138A\nnop dword ptr [rax+rax+00h]\nloc_1370:\nmov edx, [r10]\ncmp eax, edx\ncmovl eax, edx\nmov edx, [r10+4]\ncmp eax, edx\ncmovl eax, edx\nadd r10, 8\ncmp r10, rbx\njnz short loc_1370\nloc_138A:\nmov rdx, [rsp+1A8h+var_10]\nsub rdx, fs:28h\njnz short loc_13AA\nadd rsp, 1A0h\npop rbx\nretn\nloc_13A6:\nxor eax, eax\njmp short loc_138A\nloc_13AA:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12A0(__int64 a1, int a2)\n{\n int *v2; // rbx\n int *v3; // r10\n int *v4; // rax\n _DWORD *v5; // r8\n __int64 v6; // r11\n __int64 i; // rcx\n int v8; // esi\n __int64 v9; // rax\n int v10; // edx\n __int64 result; // rax\n int v12; // edx\n int v13; // [rsp+0h] [rbp-1A8h] BYREF\n _BYTE v14[404]; // [rsp+4h] [rbp-1A4h] BYREF\n unsigned __int64 v15; // [rsp+198h] [rbp-10h]\n\n v15 = __readfsqword(0x28u);\n if ( a2 <= 0 )\n return 0LL;\n v2 = (int *)&v14[4 * a2 - 4];\n v3 = &v13;\n v4 = &v13;\n if ( (a2 & 1) == 0 || (v4 = (int *)v14, v13 = 1, v14 != (_BYTE *)v2) )\n {\n do\n {\n *v4 = 1;\n v4 += 2;\n *(v4 - 1) = 1;\n }\n while ( v4 != v2 );\n }\n if ( a2 != 1 )\n {\n v5 = v14;\n v6 = (unsigned int)a2;\n for ( i = 1LL; i != v6; ++i )\n {\n v8 = *(_DWORD *)(a1 + 8 * i);\n v9 = 0LL;\n do\n {\n if ( v8 > *(_DWORD *)(a1 + 8 * v9 + 4) )\n {\n v10 = *(_DWORD *)&v14[4 * v9 - 4];\n if ( v10 >= *v5 )\n *v5 = v10 + 1;\n }\n ++v9;\n }\n while ( i != v9 );\n ++v5;\n }\n }\n result = 0LL;\n if ( ((unsigned __int8)v2 & 4) == 0 )\n goto LABEL_26;\n v3 = (int *)v14;\n if ( v13 > 0 )\n result = (unsigned int)v13;\n if ( v14 != (_BYTE *)v2 )\n {\nLABEL_26:\n do\n {\n if ( (int)result < *v3 )\n result = (unsigned int)*v3;\n v12 = v3[1];\n if ( (int)result < v12 )\n result = (unsigned int)v12;\n v3 += 2;\n }\n while ( v3 != v2 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12A0(long long a1, int a2) {\n int *v2;\n int *v3;\n int *v4;\n uint32_t *v5;\n long long v6;\n long long i;\n int v8;\n long long v9;\n int v10;\n long long result;\n int v12;\n int v13;\n uint8_t v14[404];\n unsigned long long v15;\n v15 = __readfsqword(40u);\n if (a2 <= 0) return 0LL;\n v2 = (int *)&v14[4 * a2 - 4];\n v3 = &v13;\n v4 = &v13;\n if ((a2 & 1) == 0 || (v4 = (int *)v14, v13 = 1, v14 != (uint8_t *)v2)) {\n do {\n *v4 = 1;\n v4 += 2;\n *(v4 - 1) = 1;\n } while (v4 != v2);\n }\n if (a2 != 1) {\n v5 = v14;\n v6 = (unsigned int)a2;\n for (i = 1LL; i != v6; ++i) {\n v8 = *(uint32_t *)(a1 + 8 * i);\n v9 = 0LL;\n do {\n if (v8 > *(uint32_t *)(a1 + 8 * v9 + 4)) {\n v10 = *(uint32_t *)&v14[4 * v9 - 4];\n if (v10 >= *v5) *v5 = v10 + 1;\n }\n ++v9;\n } while (i != v9);\n ++v5;\n }\n }\n result = 0LL;\n if (((unsigned char)v2 & 4) == 0) goto LABEL_26;\n v3 = (int *)v14;\n if (v13 > 0) result = (unsigned int)v13;\n if (v14 != (uint8_t *)v2) {\n LABEL_26:\n do {\n if ((int)result < *v3) result = (unsigned int)*v3;\n v12 = v3[1];\n if ((int)result < v12) result = (unsigned int)v12;\n v3 += 2;\n } while (v3 != v2);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int *v2;\n int *v3;\n int *v4;\n uint32_t *v5;\n long long v6;\n long long i;\n int v8;\n long long v9;\n int v10;\n long long result;\n int v12;\n int v13;\n uint8_t v14[404];\n unsigned long long v15;\n v15 = __readfsqword(40u);\n if (a2 <= 0) return 0LL;\n v2 = (int *)&v14[4 * a2 - 4];\n v3 = &v13;\n v4 = &v13;\n if ((a2 & 1) == 0 || (v4 = (int *)v14, v13 = 1, v14 != (uint8_t *)v2)) {\n do {\n *v4 = 1;\n v4 += 2;\n *(v4 - 1) = 1;\n } while (v4 != v2);\n }\n if (a2 != 1) {\n v5 = v14;\n v6 = (unsigned int)a2;\n for (i = 1LL; i != v6; ++i) {\n v8 = *(uint32_t *)(a1 + 8 * i);\n v9 = 0LL;\n do {\n if (v8 > *(uint32_t *)(a1 + 8 * v9 + 4)) {\n v10 = *(uint32_t *)&v14[4 * v9 - 4];\n if (v10 >= *v5) *v5 = v10 + 1;\n }\n ++v9;\n } while (i != v9);\n ++v5;\n }\n }\n result = 0LL;\n if (((unsigned char)v2 & 4) == 0) goto LABEL_26;\n v3 = (int *)v14;\n if (v13 > 0) result = (unsigned int)v13;\n if (v14 != (uint8_t *)v2) {\n LABEL_26:\n do {\n if ((int)result < *v3) result = (unsigned int)*v3;\n v12 = v3[1];\n if ((int)result < v12) result = (unsigned int)v12;\n v3 += 2;\n } while (v3 != v2);\n }\n return result;\n}" + }, + { + "index": 601, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\ntypedef struct {\n\n int a;\n\n int b;\n\n} Pair;\n\n\n\n", + "func": "int func0(Pair arr[], int n) {\n int max = 0;\n int mcl[100];\n for (int i = 0; i < n; i++) {\n mcl[i] = 1;\n }\n for (int i = 1; i < n; i++) {\n for (int j = 0; j < i; j++) {\n if (arr[i].a > arr[j].b && mcl[i] < mcl[j] + 1) {\n mcl[i] = mcl[j] + 1;\n }\n }\n }\n for (int i = 0; i < n; i++) {\n if (max < mcl[i]) {\n max = mcl[i];\n }\n }\n return max;\n}", + "test": "int main() {\n\n Pair arr1[] = {{5, 24}, {15, 25}, {27, 40}, {50, 60}};\n\n assert(func0(arr1, 4) == 3);\n\n\n\n Pair arr2[] = {{1, 2}, {3, 4}, {5, 6}, {7, 8}};\n\n assert(func0(arr2, 4) == 4);\n\n\n\n Pair arr3[] = {{19, 10}, {11, 12}, {13, 14}, {15, 16}, {31, 54}};\n\n assert(func0(arr3, 5) == 5);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x1a8,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x198(%rsp)\nxor %eax,%eax\ntest %esi,%esi\njle 1471 \nlea -0x1(%rsi),%eax\ncmp $0x2,%eax\njbe 147a \nmov %esi,%edx\nmov %rsp,%rax\nmovdqa 0xdb1(%rip),%xmm0\nshr $0x2,%edx\nshl $0x4,%rdx\nadd %rax,%rdx\nnopl 0x0(%rax)\nmovaps %xmm0,(%rax)\nadd $0x10,%rax\ncmp %rdx,%rax\njne 12f0 \nmov %esi,%eax\nand $0xfffffffc,%eax\ntest $0x3,%sil\nje 1332 \nmovslq %eax,%rdx\nmovl $0x1,(%rsp,%rdx,4)\nlea 0x1(%rax),%edx\ncmp %edx,%esi\njle 1332 \nmovslq %edx,%rdx\nadd $0x2,%eax\nmovl $0x1,(%rsp,%rdx,4)\ncmp %eax,%esi\njle 1332 \ncltq\nmovl $0x1,(%rsp,%rax,4)\ncmp $0x1,%esi\njle 1471 \nlea -0x2(%rsi),%r10d\nlea 0x4(%rsp),%r9\nmov $0x1,%ecx\nadd $0x2,%r10\nnopl (%rax)\nmov (%rdi,%rcx,8),%r8d\nxor %eax,%eax\nnopw %cs:0x0(%rax,%rax,1)\ncmp 0x4(%rdi,%rax,8),%r8d\njle 1375 \nmov (%rsp,%rax,4),%edx\ncmp (%r9),%edx\njl 1375 \nadd $0x1,%edx\nmov %edx,(%r9)\nadd $0x1,%rax\ncmp %rcx,%rax\njne 1360 \nlea 0x1(%rax),%rcx\nadd $0x4,%r9\ncmp %r10,%rcx\njne 1350 \ntest %esi,%esi\nmov $0x1,%ecx\ncmovg %esi,%ecx\ncmp $0x3,%esi\njle 1481 \nmov %ecx,%edx\npxor %xmm0,%xmm0\nmov %rsp,%rax\nshr $0x2,%edx\nshl $0x4,%rdx\nadd %rax,%rdx\nnopl 0x0(%rax)\nmovdqa %xmm0,%xmm1\nadd $0x10,%rax\npcmpgtd -0x10(%rax),%xmm1\npand %xmm1,%xmm0\npandn -0x10(%rax),%xmm1\npor %xmm1,%xmm0\ncmp %rdx,%rax\njne 13b8 \nmovdqa %xmm0,%xmm1\nmov %ecx,%edx\npsrldq $0x8,%xmm1\nand $0xfffffffc,%edx\nand $0x3,%ecx\nmovdqa %xmm1,%xmm2\nmovdqa %xmm1,%xmm3\npcmpgtd %xmm0,%xmm2\npand %xmm2,%xmm3\npandn %xmm0,%xmm2\nmovdqa %xmm2,%xmm1\npor %xmm3,%xmm1\nmovdqa %xmm1,%xmm2\npsrldq $0x4,%xmm2\nmovdqa %xmm2,%xmm0\npcmpgtd %xmm1,%xmm0\npand %xmm0,%xmm2\npandn %xmm1,%xmm0\npor %xmm2,%xmm0\nmovd %xmm0,%eax\nje 1456 \nmovslq %edx,%rcx\nmov (%rsp,%rcx,4),%ecx\ncmp %ecx,%eax\ncmovl %ecx,%eax\nadd $0x1,%edx\ncmp %edx,%esi\njle 1456 \nmovslq %edx,%rcx\nmov (%rsp,%rcx,4),%ecx\ncmp %ecx,%eax\ncmovl %ecx,%eax\nadd $0x1,%edx\ncmp %edx,%esi\njle 1456 \nmovslq %edx,%rdx\nmov (%rsp,%rdx,4),%edx\ncmp %edx,%eax\ncmovl %edx,%eax\nmov 0x198(%rsp),%rsi\nxor %fs:0x28,%rsi\njne 14a5 \nadd $0x1a8,%rsp\nretq\ncmp $0x1,%esi\nje 1496 \nxor %eax,%eax\njmp 1456 \nxor %eax,%eax\njmpq 1307 \nmov (%rsp),%eax\nmov $0x1,%edx\ntest %eax,%eax\nmov $0x0,%eax\ncmovns (%rsp),%eax\njmp 1439 \ncmpl $0x0,(%rsp)\nmov $0x0,%eax\ncmovns (%rsp),%eax\njmp 1456 \ncallq 1060 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 1A8h\nmov rax, fs:28h\nmov [rsp+1A8h+var_10], rax\nxor eax, eax\ntest esi, esi\njle loc_1465\nlea r11d, [rsi-1]\nmov r9d, esi\ncmp r11d, 2\njbe loc_147A\nmov edx, esi\nmov rax, rsp\nmovdqa xmm0, cs:xmmword_2070\nshr edx, 2\nshl rdx, 4\nlea rcx, [rdx+rax]\nand edx, 10h\njz short loc_1308\nmovaps xmmword ptr [rax], xmm0\nlea rax, [rsp+1A8h+var_198]\ncmp rax, rcx\njz short loc_1318\nnop dword ptr [rax+00000000h]\nloc_1308:\nmovaps xmmword ptr [rax], xmm0\nadd rax, 20h ; ' '\nmovaps xmmword ptr [rax-10h], xmm0\ncmp rax, rcx\njnz short loc_1308\nloc_1318:\nmov eax, r9d\nand eax, 0FFFFFFFCh\ntest r9b, 3\njz short loc_1351\nmovsxd rdx, eax\nmov [rsp+rdx*4+1A8h+var_1A8], 1\nlea edx, [rax+1]\ncmp r9d, edx\njle short loc_1351\nloc_1336:\nmovsxd rdx, edx\nadd eax, 2\nmov [rsp+rdx*4+1A8h+var_1A8], 1\ncmp eax, r9d\njge short loc_1351\ncdqe\nmov [rsp+rax*4+1A8h+var_1A8], 1\nloc_1351:\nlea r8, [rsp+1A8h+var_1A4]\nmov r10d, r9d\nmov ecx, 1\nxchg ax, ax\nloc_1360:\nmov esi, [rdi+rcx*8]\nxor eax, eax\nnop dword ptr [rax]\nloc_1368:\ncmp esi, [rdi+rax*8+4]\njle short loc_137C\nmov edx, [rsp+rax*4+1A8h+var_1A8]\ncmp edx, [r8]\njl short loc_137C\nadd edx, 1\nmov [r8], edx\nloc_137C:\nadd rax, 1\ncmp rax, rcx\njnz short loc_1368\nlea rcx, [rax+1]\nadd r8, 4\ncmp rcx, r10\njnz short loc_1360\ncmp r11d, 2\njbe loc_1469\nmov edx, r9d\nmov rax, rsp\npxor xmm0, xmm0\nshr edx, 2\nshl rdx, 4\nadd rdx, rax\nloc_13B0:\nmovdqa xmm1, xmm0\nadd rax, 10h\npcmpgtd xmm1, xmmword ptr [rax-10h]\npand xmm0, xmm1\npandn xmm1, xmmword ptr [rax-10h]\npor xmm0, xmm1\ncmp rdx, rax\njnz short loc_13B0\nmovdqa xmm2, xmm0\nmov edx, r9d\npsrldq xmm2, 8\nand edx, 0FFFFFFFCh\nmovdqa xmm1, xmm2\npcmpgtd xmm1, xmm0\npand xmm2, xmm1\npandn xmm1, xmm0\npor xmm1, xmm2\nmovdqa xmm2, xmm1\npsrldq xmm2, 4\nmovdqa xmm0, xmm2\npcmpgtd xmm0, xmm1\npand xmm2, xmm0\npandn xmm0, xmm1\npor xmm0, xmm2\nmovd eax, xmm0\ntest r9b, 3\njz short loc_144A\nmovsxd rcx, edx\nmov ecx, [rsp+rcx*4+1A8h+var_1A8]\ncmp eax, ecx\ncmovl eax, ecx\nlea ecx, [rdx+1]\ncmp ecx, r9d\njge short loc_144A\nloc_142C:\nmovsxd rcx, ecx\nmov ecx, [rsp+rcx*4+1A8h+var_1A8]\ncmp eax, ecx\ncmovl eax, ecx\nadd edx, 2\ncmp r9d, edx\njle short loc_144A\nmovsxd rdx, edx\nmov edx, [rsp+rdx*4+1A8h+var_1A8]\ncmp eax, edx\ncmovl eax, edx\nloc_144A:\nmov rdx, [rsp+1A8h+var_10]\nsub rdx, fs:28h\njnz short loc_1496\nadd rsp, 1A8h\nretn\nloc_1465:\nxor eax, eax\njmp short loc_144A\nloc_1469:\nmov eax, [rsp+1A8h+var_1A8]\nxor edx, edx\nmov ecx, 1\ntest eax, eax\ncmovs eax, edx\njmp short loc_142C\nloc_147A:\nmov [rsp+1A8h+var_1A8], 1\nmov edx, 1\ncmp esi, 1\njnz loc_1336\nmov eax, 1\njmp short loc_144A\nloc_1496:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int v2; // eax\n unsigned int v3; // r11d\n __m128i *v5; // rax\n __m128i si128; // xmm0\n __int64 v7; // rdx\n __m128i *v8; // rcx\n int v9; // edx\n int v10; // eax\n __int32 *v11; // r8\n __int64 v12; // rcx\n int v13; // esi\n __int64 v14; // rax\n __int32 v15; // edx\n __m128i *v16; // rax\n __m128i v17; // xmm0\n __m128i v18; // xmm1\n __m128i v19; // xmm2\n unsigned int v20; // edx\n __m128i v21; // xmm1\n __m128i v22; // xmm1\n __m128i v23; // xmm2\n __m128i v24; // xmm0\n __int64 result; // rax\n int v26; // ecx\n int v27; // ecx\n int v28; // ecx\n int v29; // edx\n int v30; // edx\n __m128i v31; // [rsp+0h] [rbp-1A8h] BYREF\n _BYTE v32[392]; // [rsp+10h] [rbp-198h] BYREF\n unsigned __int64 v33; // [rsp+198h] [rbp-10h]\n\n v33 = __readfsqword(0x28u);\n v2 = 0;\n if ( a2 <= 0 )\n return 0LL;\n v3 = a2 - 1;\n if ( (unsigned int)(a2 - 1) <= 2 )\n {\n v31.m128i_i32[0] = 1;\n v9 = 1;\n if ( a2 == 1 )\n return 1LL;\n goto LABEL_8;\n }\n v5 = &v31;\n si128 = _mm_load_si128((const __m128i *)&xmmword_2070);\n v7 = 16LL * ((unsigned int)a2 >> 2);\n v8 = (__m128i *)((char *)&v31 + v7);\n if ( (v7 & 0x10) == 0 || (v31 = si128, v5 = (__m128i *)v32, v32 != (_BYTE *)v8) )\n {\n do\n {\n *v5 = si128;\n v5 += 2;\n v5[-1] = si128;\n }\n while ( v5 != v8 );\n }\n v2 = a2 & 0x7FFFFFFC;\n if ( (a2 & 3) != 0 )\n {\n v31.m128i_i32[v2] = 1;\n v9 = v2 + 1;\n if ( a2 > v2 + 1 )\n {\nLABEL_8:\n v10 = v2 + 2;\n v31.m128i_i32[v9] = 1;\n if ( v10 < a2 )\n v31.m128i_i32[v10] = 1;\n }\n }\n v11 = &v31.m128i_i32[1];\n v12 = 1LL;\n do\n {\n v13 = *(_DWORD *)(a1 + 8 * v12);\n v14 = 0LL;\n do\n {\n if ( v13 > *(_DWORD *)(a1 + 8 * v14 + 4) )\n {\n v15 = v31.m128i_i32[v14];\n if ( v15 >= *v11 )\n *v11 = v15 + 1;\n }\n ++v14;\n }\n while ( v14 != v12 );\n v12 = v14 + 1;\n ++v11;\n }\n while ( v14 + 1 != a2 );\n if ( v3 <= 2 )\n {\n result = v31.m128i_u32[0];\n v20 = 0;\n v27 = 1;\n if ( v31.m128i_i32[0] < 0 )\n result = 0LL;\n goto LABEL_24;\n }\n v16 = &v31;\n v17 = 0LL;\n do\n {\n ++v16;\n v18 = _mm_cmpgt_epi32(v17, v16[-1]);\n v17 = _mm_or_si128(_mm_and_si128(v17, v18), _mm_andnot_si128(v18, v16[-1]));\n }\n while ( &v31 + ((unsigned int)a2 >> 2) != v16 );\n v19 = _mm_srli_si128(v17, 8);\n v20 = a2 & 0xFFFFFFFC;\n v21 = _mm_cmpgt_epi32(v19, v17);\n v22 = _mm_or_si128(_mm_andnot_si128(v21, v17), _mm_and_si128(v19, v21));\n v23 = _mm_srli_si128(v22, 4);\n v24 = _mm_cmpgt_epi32(v23, v22);\n result = (unsigned int)_mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v24, v22), _mm_and_si128(v23, v24)));\n if ( (a2 & 3) != 0 )\n {\n v26 = v31.m128i_i32[v20];\n if ( (int)result < v26 )\n result = (unsigned int)v26;\n v27 = v20 + 1;\n if ( (int)(v20 + 1) < a2 )\n {\nLABEL_24:\n v28 = v31.m128i_i32[v27];\n if ( (int)result < v28 )\n result = (unsigned int)v28;\n v29 = v20 + 2;\n if ( a2 > v29 )\n {\n v30 = v31.m128i_i32[v29];\n if ( (int)result < v30 )\n return (unsigned int)v30;\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_12A0:\nendbr64\nsub rsp, 1A8h\nmov rax, fs:28h\nmov [rsp+1A8h+var_10], rax\nxor eax, eax\ntest esi, esi\njle loc_1465\nlea r11d, [rsi-1]\nmov r9d, esi\ncmp r11d, 2\njbe loc_147A\nmov edx, esi\nmov rax, rsp\nmovdqa xmm0, cs:xmmword_2070\nshr edx, 2\nshl rdx, 4\nlea rcx, [rdx+rax]\nand edx, 10h\njz short loc_1308\nmovaps xmmword ptr [rax], xmm0\nlea rax, [rsp+1A8h+var_198]\ncmp rax, rcx\njz short loc_1318\nnop dword ptr [rax+00000000h]\nloc_1308:\nmovaps xmmword ptr [rax], xmm0\nadd rax, 20h ; ' '\nmovaps xmmword ptr [rax-10h], xmm0\ncmp rax, rcx\njnz short loc_1308\nloc_1318:\nmov eax, r9d\nand eax, 0FFFFFFFCh\ntest r9b, 3\njz short loc_1351\nmovsxd rdx, eax\nmov [rsp+rdx*4+1A8h+var_1A8], 1\nlea edx, [rax+1]\ncmp r9d, edx\njle short loc_1351\nloc_1336:\nmovsxd rdx, edx\nadd eax, 2\nmov [rsp+rdx*4+1A8h+var_1A8], 1\ncmp eax, r9d\njge short loc_1351\ncdqe\nmov [rsp+rax*4+1A8h+var_1A8], 1\nloc_1351:\nlea r8, [rsp+1A8h+var_1A4]\nmov r10d, r9d\nmov ecx, 1\nxchg ax, ax\nloc_1360:\nmov esi, [rdi+rcx*8]\nxor eax, eax\nnop dword ptr [rax]\nloc_1368:\ncmp esi, [rdi+rax*8+4]\njle short loc_137C\nmov edx, [rsp+rax*4+1A8h+var_1A8]\ncmp edx, [r8]\njl short loc_137C\nadd edx, 1\nmov [r8], edx\nloc_137C:\nadd rax, 1\ncmp rax, rcx\njnz short loc_1368\nlea rcx, [rax+1]\nadd r8, 4\ncmp rcx, r10\njnz short loc_1360\ncmp r11d, 2\njbe loc_1469\nmov edx, r9d\nmov rax, rsp\npxor xmm0, xmm0\nshr edx, 2\nshl rdx, 4\nadd rdx, rax\nloc_13B0:\nmovdqa xmm1, xmm0\nadd rax, 10h\npcmpgtd xmm1, xmmword ptr [rax-10h]\npand xmm0, xmm1\npandn xmm1, xmmword ptr [rax-10h]\npor xmm0, xmm1\ncmp rdx, rax\njnz short loc_13B0\nmovdqa xmm2, xmm0\nmov edx, r9d\npsrldq xmm2, 8\nand edx, 0FFFFFFFCh\nmovdqa xmm1, xmm2\npcmpgtd xmm1, xmm0\npand xmm2, xmm1\npandn xmm1, xmm0\npor xmm1, xmm2\nmovdqa xmm2, xmm1\npsrldq xmm2, 4\nmovdqa xmm0, xmm2\npcmpgtd xmm0, xmm1\npand xmm2, xmm0\npandn xmm0, xmm1\npor xmm0, xmm2\nmovd eax, xmm0\ntest r9b, 3\njz short loc_144A\nmovsxd rcx, edx\nmov ecx, [rsp+rcx*4+1A8h+var_1A8]\ncmp eax, ecx\ncmovl eax, ecx\nlea ecx, [rdx+1]\ncmp ecx, r9d\njge short loc_144A\nloc_142C:\nmovsxd rcx, ecx\nmov ecx, [rsp+rcx*4+1A8h+var_1A8]\ncmp eax, ecx\ncmovl eax, ecx\nadd edx, 2\ncmp r9d, edx\njle short loc_144A\nmovsxd rdx, edx\nmov edx, [rsp+rdx*4+1A8h+var_1A8]\ncmp eax, edx\ncmovl eax, edx\nloc_144A:\nmov rdx, [rsp+1A8h+var_10]\nsub rdx, fs:28h\njnz short loc_1496\nadd rsp, 1A8h\nretn\nloc_1465:\nxor eax, eax\njmp short loc_144A\nloc_1469:\nmov eax, [rsp+1A8h+var_1A8]\nxor edx, edx\nmov ecx, 1\ntest eax, eax\ncmovs eax, edx\njmp short loc_142C\nloc_147A:\nmov [rsp+1A8h+var_1A8], 1\nmov edx, 1\ncmp esi, 1\njnz loc_1336\nmov eax, 1\njmp short loc_144A\nloc_1496:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12A0(__int64 a1, int a2)\n{\n int v2; // eax\n unsigned int v3; // r11d\n __m128i *v5; // rax\n __m128i si128; // xmm0\n __int64 v7; // rdx\n __m128i *v8; // rcx\n int v9; // edx\n int v10; // eax\n __int32 *v11; // r8\n __int64 v12; // rcx\n int v13; // esi\n __int64 v14; // rax\n __int32 v15; // edx\n __m128i *v16; // rax\n __m128i v17; // xmm0\n __m128i v18; // xmm1\n __m128i v19; // xmm2\n unsigned int v20; // edx\n __m128i v21; // xmm1\n __m128i v22; // xmm1\n __m128i v23; // xmm2\n __m128i v24; // xmm0\n __int64 result; // rax\n int v26; // ecx\n int v27; // ecx\n int v28; // ecx\n int v29; // edx\n int v30; // edx\n __m128i v31; // [rsp+0h] [rbp-1A8h] BYREF\n _BYTE v32[392]; // [rsp+10h] [rbp-198h] BYREF\n unsigned __int64 v33; // [rsp+198h] [rbp-10h]\n\n v33 = __readfsqword(0x28u);\n v2 = 0;\n if ( a2 <= 0 )\n return 0LL;\n v3 = a2 - 1;\n if ( (unsigned int)(a2 - 1) <= 2 )\n {\n v31.m128i_i32[0] = 1;\n v9 = 1;\n if ( a2 == 1 )\n return 1LL;\n goto LABEL_8;\n }\n v5 = &v31;\n si128 = _mm_load_si128((const __m128i *)&xmmword_2070);\n v7 = 16LL * ((unsigned int)a2 >> 2);\n v8 = (__m128i *)((char *)&v31 + v7);\n if ( (v7 & 0x10) == 0 || (v31 = si128, v5 = (__m128i *)v32, v32 != (_BYTE *)v8) )\n {\n do\n {\n *v5 = si128;\n v5 += 2;\n v5[-1] = si128;\n }\n while ( v5 != v8 );\n }\n v2 = a2 & 0x7FFFFFFC;\n if ( (a2 & 3) != 0 )\n {\n v31.m128i_i32[v2] = 1;\n v9 = v2 + 1;\n if ( a2 > v2 + 1 )\n {\nLABEL_8:\n v10 = v2 + 2;\n v31.m128i_i32[v9] = 1;\n if ( v10 < a2 )\n v31.m128i_i32[v10] = 1;\n }\n }\n v11 = &v31.m128i_i32[1];\n v12 = 1LL;\n do\n {\n v13 = *(_DWORD *)(a1 + 8 * v12);\n v14 = 0LL;\n do\n {\n if ( v13 > *(_DWORD *)(a1 + 8 * v14 + 4) )\n {\n v15 = v31.m128i_i32[v14];\n if ( v15 >= *v11 )\n *v11 = v15 + 1;\n }\n ++v14;\n }\n while ( v14 != v12 );\n v12 = v14 + 1;\n ++v11;\n }\n while ( v14 + 1 != a2 );\n if ( v3 <= 2 )\n {\n result = v31.m128i_u32[0];\n v20 = 0;\n v27 = 1;\n if ( v31.m128i_i32[0] < 0 )\n result = 0LL;\n goto LABEL_24;\n }\n v16 = &v31;\n v17 = 0LL;\n do\n {\n ++v16;\n v18 = _mm_cmpgt_epi32(v17, v16[-1]);\n v17 = _mm_or_si128(_mm_and_si128(v17, v18), _mm_andnot_si128(v18, v16[-1]));\n }\n while ( &v31 + ((unsigned int)a2 >> 2) != v16 );\n v19 = _mm_srli_si128(v17, 8);\n v20 = a2 & 0xFFFFFFFC;\n v21 = _mm_cmpgt_epi32(v19, v17);\n v22 = _mm_or_si128(_mm_andnot_si128(v21, v17), _mm_and_si128(v19, v21));\n v23 = _mm_srli_si128(v22, 4);\n v24 = _mm_cmpgt_epi32(v23, v22);\n result = (unsigned int)_mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v24, v22), _mm_and_si128(v23, v24)));\n if ( (a2 & 3) != 0 )\n {\n v26 = v31.m128i_i32[v20];\n if ( (int)result < v26 )\n result = (unsigned int)v26;\n v27 = v20 + 1;\n if ( (int)(v20 + 1) < a2 )\n {\nLABEL_24:\n v28 = v31.m128i_i32[v27];\n if ( (int)result < v28 )\n result = (unsigned int)v28;\n v29 = v20 + 2;\n if ( a2 > v29 )\n {\n v30 = v31.m128i_i32[v29];\n if ( (int)result < v30 )\n return (unsigned int)v30;\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12A0(long long a1, int a2) {\n int v2;\n unsigned int v3;\n __m128i *v5;\n __m128i si128;\n long long v7;\n __m128i *v8;\n int v9;\n int v10;\n int *v11;\n long long v12;\n int v13;\n long long v14;\n int v15;\n __m128i *v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n unsigned int v20;\n __m128i v21;\n __m128i v22;\n __m128i v23;\n __m128i v24;\n long long result;\n int v26;\n int v27;\n int v28;\n int v29;\n int v30;\n __m128i v31;\n uint8_t v32[392];\n unsigned long long v33;\n v33 = __readfsqword(40u);\n v2 = 0;\n if (a2 <= 0) return 0LL;\n v3 = a2 - 1;\n if ((unsigned int)(a2 - 1) <= 2) {\n v31.m128i_i32[0] = 1;\n v9 = 1;\n if (a2 == 1) return 1LL;\n goto LABEL_8;\n }\n v5 = &v31;\n si128 = _mm_load_si128((const __m128i *)&xmmword_2070);\n v7 = 16LL * ((unsigned int)a2 >> 2);\n v8 = (__m128i *)((char *)&v31 + v7);\n if ((v7 & 16) == 0 ||\n (v31 = si128, v5 = (__m128i *)v32, v32 != (uint8_t *)v8)) {\n do {\n *v5 = si128;\n v5 += 2;\n v5[-1] = si128;\n } while (v5 != v8);\n }\n v2 = a2 & 2147483644;\n if ((a2 & 3) != 0) {\n v31.m128i_i32[v2] = 1;\n v9 = v2 + 1;\n if (a2 > v2 + 1) {\n LABEL_8:\n v10 = v2 + 2;\n v31.m128i_i32[v9] = 1;\n if (v10 < a2) v31.m128i_i32[v10] = 1;\n }\n }\n v11 = &v31.m128i_i32[1];\n v12 = 1LL;\n do {\n v13 = *(uint32_t *)(a1 + 8 * v12);\n v14 = 0LL;\n do {\n if (v13 > *(uint32_t *)(a1 + 8 * v14 + 4)) {\n v15 = v31.m128i_i32[v14];\n if (v15 >= *v11) *v11 = v15 + 1;\n }\n ++v14;\n } while (v14 != v12);\n v12 = v14 + 1;\n ++v11;\n } while (v14 + 1 != a2);\n if (v3 <= 2) {\n result = v31.m128i_u32[0];\n v20 = 0;\n v27 = 1;\n if (v31.m128i_i32[0] < 0) result = 0LL;\n goto LABEL_24;\n }\n v16 = &v31;\n v17 = 0LL;\n do {\n ++v16;\n v18 = _mm_cmpgt_epi32(v17, v16[-1]);\n v17 = _mm_or_si128(_mm_and_si128(v17, v18), _mm_andnot_si128(v18, v16[-1]));\n } while (&v31 + ((unsigned int)a2 >> 2) != v16);\n v19 = _mm_srli_si128(v17, 8);\n v20 = a2 & 4294967292;\n v21 = _mm_cmpgt_epi32(v19, v17);\n v22 = _mm_or_si128(_mm_andnot_si128(v21, v17), _mm_and_si128(v19, v21));\n v23 = _mm_srli_si128(v22, 4);\n v24 = _mm_cmpgt_epi32(v23, v22);\n result = (unsigned int)_mm_cvtsi128_si32(\n _mm_or_si128(_mm_andnot_si128(v24, v22), _mm_and_si128(v23, v24)));\n if ((a2 & 3) != 0) {\n v26 = v31.m128i_i32[v20];\n if ((int)result < v26) result = (unsigned int)v26;\n v27 = v20 + 1;\n if ((int)(v20 + 1) < a2) {\n LABEL_24:\n v28 = v31.m128i_i32[v27];\n if ((int)result < v28) result = (unsigned int)v28;\n v29 = v20 + 2;\n if (a2 > v29) {\n v30 = v31.m128i_i32[v29];\n if ((int)result < v30) return (unsigned int)v30;\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int v2;\n unsigned int v3;\n __m128i *v5;\n __m128i si128;\n long long v7;\n __m128i *v8;\n int v9;\n int v10;\n int *v11;\n long long v12;\n int v13;\n long long v14;\n int v15;\n __m128i *v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n unsigned int v20;\n __m128i v21;\n __m128i v22;\n __m128i v23;\n __m128i v24;\n long long result;\n int v26;\n int v27;\n int v28;\n int v29;\n int v30;\n __m128i v31;\n uint8_t v32[392];\n unsigned long long v33;\n v33 = __readfsqword(40u);\n v2 = 0;\n if (a2 <= 0) return 0LL;\n v3 = a2 - 1;\n if ((unsigned int)(a2 - 1) <= 2) {\n v31.m128i_i32[0] = 1;\n v9 = 1;\n if (a2 == 1) return 1LL;\n goto LABEL_8;\n }\n v5 = &v31;\n si128 = _mm_load_si128((const __m128i *)&xmmword_2070);\n v7 = 16LL * ((unsigned int)a2 >> 2);\n v8 = (__m128i *)((char *)&v31 + v7);\n if ((v7 & 16) == 0 ||\n (v31 = si128, v5 = (__m128i *)v32, v32 != (uint8_t *)v8)) {\n do {\n *v5 = si128;\n v5 += 2;\n v5[-1] = si128;\n } while (v5 != v8);\n }\n v2 = a2 & 2147483644;\n if ((a2 & 3) != 0) {\n v31.m128i_i32[v2] = 1;\n v9 = v2 + 1;\n if (a2 > v2 + 1) {\n LABEL_8:\n v10 = v2 + 2;\n v31.m128i_i32[v9] = 1;\n if (v10 < a2) v31.m128i_i32[v10] = 1;\n }\n }\n v11 = &v31.m128i_i32[1];\n v12 = 1LL;\n do {\n v13 = *(uint32_t *)(a1 + 8 * v12);\n v14 = 0LL;\n do {\n if (v13 > *(uint32_t *)(a1 + 8 * v14 + 4)) {\n v15 = v31.m128i_i32[v14];\n if (v15 >= *v11) *v11 = v15 + 1;\n }\n ++v14;\n } while (v14 != v12);\n v12 = v14 + 1;\n ++v11;\n } while (v14 + 1 != a2);\n if (v3 <= 2) {\n result = v31.m128i_u32[0];\n v20 = 0;\n v27 = 1;\n if (v31.m128i_i32[0] < 0) result = 0LL;\n goto LABEL_24;\n }\n v16 = &v31;\n v17 = 0LL;\n do {\n ++v16;\n v18 = _mm_cmpgt_epi32(v17, v16[-1]);\n v17 = _mm_or_si128(_mm_and_si128(v17, v18), _mm_andnot_si128(v18, v16[-1]));\n } while (&v31 + ((unsigned int)a2 >> 2) != v16);\n v19 = _mm_srli_si128(v17, 8);\n v20 = a2 & 4294967292;\n v21 = _mm_cmpgt_epi32(v19, v17);\n v22 = _mm_or_si128(_mm_andnot_si128(v21, v17), _mm_and_si128(v19, v21));\n v23 = _mm_srli_si128(v22, 4);\n v24 = _mm_cmpgt_epi32(v23, v22);\n result = (unsigned int)_mm_cvtsi128_si32(\n _mm_or_si128(_mm_andnot_si128(v24, v22), _mm_and_si128(v23, v24)));\n if ((a2 & 3) != 0) {\n v26 = v31.m128i_i32[v20];\n if ((int)result < v26) result = (unsigned int)v26;\n v27 = v20 + 1;\n if ((int)(v20 + 1) < a2) {\n LABEL_24:\n v28 = v31.m128i_i32[v27];\n if ((int)result < v28) result = (unsigned int)v28;\n v29 = v20 + 2;\n if (a2 > v29) {\n v30 = v31.m128i_i32[v29];\n if ((int)result < v30) return (unsigned int)v30;\n }\n }\n }\n return result;\n}" + }, + { + "index": 602, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char func0(char* str1) {\n int length = strlen(str1);\n for (int i = 0; i < length; i++) {\n char c = str1[i];\n int count = 0;\n for (int j = 0; j <= i; j++) {\n if (str1[j] == c) {\n count++;\n }\n }\n if (count > 1) {\n return c;\n }\n }\n return '0';\n}", + "test": "int main() {\n\n assert(func0(\"abcabc\") == 'a');\n\n assert(func0(\"abc\") == '0');\n\n assert(func0(\"123123\") == '1');\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x28(%rbp)\nmov -0x28(%rbp),%rax\nmov %rax,%rdi\ncallq 1060 \nmov %eax,-0x4(%rbp)\nmovl $0x0,-0x10(%rbp)\njmp 11e9 \nmov -0x10(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmov %al,-0x11(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11d1 \nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp %al,-0x11(%rbp)\njne 11cd \naddl $0x1,-0xc(%rbp)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x10(%rbp),%eax\njle 11b4 \ncmpl $0x1,-0xc(%rbp)\njle 11e5 \nmovzbl -0x11(%rbp),%eax\njmp 11f6 \naddl $0x1,-0x10(%rbp)\nmov -0x10(%rbp),%eax\ncmp -0x4(%rbp),%eax\njl 1191 \nmov $0x30,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_10], 0\njmp short loc_11E9\nloc_1191:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_11], al\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_11D1\nloc_11B4:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp [rbp+var_11], al\njnz short loc_11CD\nadd [rbp+var_C], 1\nloc_11CD:\nadd [rbp+var_8], 1\nloc_11D1:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_10]\njle short loc_11B4\ncmp [rbp+var_C], 1\njle short loc_11E5\nmovzx eax, [rbp+var_11]\njmp short locret_11F6\nloc_11E5:\nadd [rbp+var_10], 1\nloc_11E9:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_4]\njl short loc_1191\nmov eax, 30h ; '0'\nlocret_11F6:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n unsigned __int8 v2; // [rsp+1Fh] [rbp-11h]\n int i; // [rsp+20h] [rbp-10h]\n int v4; // [rsp+24h] [rbp-Ch]\n int j; // [rsp+28h] [rbp-8h]\n int v6; // [rsp+2Ch] [rbp-4h]\n\n v6 = strlen(a1);\n for ( i = 0; i < v6; ++i )\n {\n v2 = a1[i];\n v4 = 0;\n for ( j = 0; j <= i; ++j )\n {\n if ( v2 == a1[j] )\n ++v4;\n }\n if ( v4 > 1 )\n return v2;\n }\n return 48LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_10], 0\njmp short loc_11E9\nloc_1191:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_11], al\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_11D1\nloc_11B4:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp [rbp+var_11], al\njnz short loc_11CD\nadd [rbp+var_C], 1\nloc_11CD:\nadd [rbp+var_8], 1\nloc_11D1:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_10]\njle short loc_11B4\ncmp [rbp+var_C], 1\njle short loc_11E5\nmovzx eax, [rbp+var_11]\njmp short locret_11F6\nloc_11E5:\nadd [rbp+var_10], 1\nloc_11E9:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_4]\njl short loc_1191\nmov eax, 30h ; '0'\nlocret_11F6:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1)\n{\n unsigned __int8 v2; // [rsp+1Fh] [rbp-11h]\n int i; // [rsp+20h] [rbp-10h]\n int v4; // [rsp+24h] [rbp-Ch]\n int j; // [rsp+28h] [rbp-8h]\n int v6; // [rsp+2Ch] [rbp-4h]\n\n v6 = strlen(a1);\n for ( i = 0; i < v6; ++i )\n {\n v2 = a1[i];\n v4 = 0;\n for ( j = 0; j <= i; ++j )\n {\n if ( v2 == a1[j] )\n ++v4;\n }\n if ( v4 > 1 )\n return v2;\n }\n return 48LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1) {\n unsigned char v2;\n int i;\n int v4;\n int j;\n int v6;\n v6 = strlen(a1);\n for (i = 0; i < v6; ++i) {\n v2 = a1[i];\n v4 = 0;\n for (j = 0; j <= i; ++j) {\n if (v2 == a1[j]) ++v4;\n }\n if (v4 > 1) return v2;\n }\n return 48LL;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n unsigned char v2;\n int i;\n int v4;\n int j;\n int v6;\n v6 = strlen(a1);\n for (i = 0; i < v6; ++i) {\n v2 = a1[i];\n v4 = 0;\n for (j = 0; j <= i; ++j) {\n if (v2 == a1[j]) ++v4;\n }\n if (v4 > 1) return v2;\n }\n return 48LL;\n}" + }, + { + "index": 602, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char func0(char* str1) {\n int length = strlen(str1);\n for (int i = 0; i < length; i++) {\n char c = str1[i];\n int count = 0;\n for (int j = 0; j <= i; j++) {\n if (str1[j] == c) {\n count++;\n }\n }\n if (count > 1) {\n return c;\n }\n }\n return '0';\n}", + "test": "int main() {\n\n assert(func0(\"abcabc\") == 'a');\n\n assert(func0(\"abc\") == '0');\n\n assert(func0(\"123123\") == '1');\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%rdx\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nsub $0x1,%rcx\nmov %ecx,%r10d\ntest %ecx,%ecx\njle 11ba \nmov %rdx,%r9\nlea 0x1(%rdx),%rdi\nmov $0x0,%r8d\nmovzbl -0x1(%rdi),%esi\ntest %r8d,%r8d\njs 11a6 \nmov %r9,%rax\nmov $0x0,%edx\ncmp %sil,(%rax)\nsete %cl\nmovzbl %cl,%ecx\nadd %ecx,%edx\nadd $0x1,%rax\ncmp %rdi,%rax\njne 118a \ncmp $0x1,%edx\njle 11a6 \nmov %esi,%eax\nretq\nadd $0x1,%r8d\nadd $0x1,%rdi\ncmp %r8d,%r10d\njne 1179 \nmov $0x30,%esi\njmp 11a3 \nmov $0x30,%esi\njmp 11a3 \n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest eax, eax\njle short loc_1189\nmov r9d, eax\nlea rsi, [rbx+1]\nmov r8d, 0\njmp short loc_1198\nloc_1189:\nmov edi, 30h ; '0'\njmp short loc_11D4\nloc_1190:\nadd r8d, 1\nadd rsi, 1\nloc_1198:\nmovzx edi, byte ptr [rsi-1]\ntest r8d, r8d\njs short loc_1190\nmov rax, rbx\nmov edx, 0\nloc_11A9:\ncmp [rax], dil\nsetz cl\nmovzx ecx, cl\nadd edx, ecx\nadd rax, 1\ncmp rax, rsi\njnz short loc_11A9\ncmp edx, 1\njg short loc_11D4\nadd r8d, 1\nadd rsi, 1\ncmp r9d, r8d\njnz short loc_1198\nmov edi, 30h ; '0'\nloc_11D4:\nmov eax, edi\npop rbx\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v2; // eax\n int v3; // r9d\n const char *v4; // rsi\n int v5; // r8d\n unsigned int v6; // edi\n const char *v7; // rax\n int v8; // edx\n\n v2 = strlen(a1);\n if ( v2 <= 0 )\n {\n return 48;\n }\n else\n {\n v3 = v2;\n v4 = a1 + 1;\n v5 = 0;\n while ( 1 )\n {\n while ( 1 )\n {\n v6 = *((unsigned __int8 *)v4 - 1);\n if ( v5 >= 0 )\n break;\n ++v5;\n ++v4;\n }\n v7 = a1;\n v8 = 0;\n do\n v8 += *v7++ == (unsigned __int8)v6;\n while ( v7 != v4 );\n if ( v8 > 1 )\n break;\n ++v5;\n ++v4;\n if ( v3 == v5 )\n return 48;\n }\n }\n return v6;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest eax, eax\njle short loc_1189\nmov r9d, eax\nlea rsi, [rbx+1]\nmov r8d, 0\njmp short loc_1198\nloc_1189:\nmov edi, 30h ; '0'\njmp short loc_11D4\nloc_1190:\nadd r8d, 1\nadd rsi, 1\nloc_1198:\nmovzx edi, byte ptr [rsi-1]\ntest r8d, r8d\njs short loc_1190\nmov rax, rbx\nmov edx, 0\nloc_11A9:\ncmp [rax], dil\nsetz cl\nmovzx ecx, cl\nadd edx, ecx\nadd rax, 1\ncmp rax, rsi\njnz short loc_11A9\ncmp edx, 1\njg short loc_11D4\nadd r8d, 1\nadd rsi, 1\ncmp r9d, r8d\njnz short loc_1198\nmov edi, 30h ; '0'\nloc_11D4:\nmov eax, edi\npop rbx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1)\n{\n int v2; // eax\n int v3; // r9d\n const char *v4; // rsi\n int v5; // r8d\n unsigned int v6; // edi\n const char *v7; // rax\n int v8; // edx\n\n v2 = strlen(a1);\n if ( v2 <= 0 )\n {\n return 48;\n }\n else\n {\n v3 = v2;\n v4 = a1 + 1;\n v5 = 0;\n while ( 1 )\n {\n while ( 1 )\n {\n v6 = *((unsigned __int8 *)v4 - 1);\n if ( v5 >= 0 )\n break;\n ++v5;\n ++v4;\n }\n v7 = a1;\n v8 = 0;\n do\n v8 += *v7++ == (unsigned __int8)v6;\n while ( v7 != v4 );\n if ( v8 > 1 )\n break;\n ++v5;\n ++v4;\n if ( v3 == v5 )\n return 48;\n }\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1) {\n int v2;\n int v3;\n const char *v4;\n int v5;\n unsigned int v6;\n const char *v7;\n int v8;\n v2 = strlen(a1);\n if (v2 <= 0) {\n return 48;\n } else {\n v3 = v2;\n v4 = a1 + 1;\n v5 = 0;\n while (1) {\n while (1) {\n v6 = *((unsigned char *)v4 - 1);\n if (v5 >= 0) break;\n ++v5;\n ++v4;\n }\n v7 = a1;\n v8 = 0;\n do\n v8 += *v7++ == (unsigned char)v6;\n while (v7 != v4);\n if (v8 > 1) break;\n ++v5;\n ++v4;\n if (v3 == v5) return 48;\n }\n }\n return v6;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v2;\n int v3;\n const char *v4;\n int v5;\n unsigned int v6;\n const char *v7;\n int v8;\n v2 = strlen(a1);\n if (v2 <= 0) {\n return 48;\n } else {\n v3 = v2;\n v4 = a1 + 1;\n v5 = 0;\n while (1) {\n while (1) {\n v6 = *((unsigned char *)v4 - 1);\n if (v5 >= 0) break;\n ++v5;\n ++v4;\n }\n v7 = a1;\n v8 = 0;\n do\n v8 += *v7++ == (unsigned char)v6;\n while (v7 != v4);\n if (v8 > 1) break;\n ++v5;\n ++v4;\n if (v3 == v5) return 48;\n }\n }\n return v6;\n}" + }, + { + "index": 602, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char func0(char* str1) {\n int length = strlen(str1);\n for (int i = 0; i < length; i++) {\n char c = str1[i];\n int count = 0;\n for (int j = 0; j <= i; j++) {\n if (str1[j] == c) {\n count++;\n }\n }\n if (count > 1) {\n return c;\n }\n }\n return '0';\n}", + "test": "int main() {\n\n assert(func0(\"abcabc\") == 'a');\n\n assert(func0(\"abc\") == '0');\n\n assert(func0(\"123123\") == '1');\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\ncallq 1060 \ntest %eax,%eax\njle 1261 \nsub $0x1,%eax\nlea 0x1(%rbx),%rsi\nlea 0x2(%rbx,%rax,1),%rdi\nnopl (%rax)\nmovzbl -0x1(%rsi),%r8d\nmov %rbx,%rax\nxor %edx,%edx\nnopw 0x0(%rax,%rax,1)\nxor %ecx,%ecx\ncmp %r8b,(%rax)\nsete %cl\nadd $0x1,%rax\nadd %ecx,%edx\ncmp %rsi,%rax\njne 1240 \ncmp $0x1,%edx\njg 1267 \nlea 0x1(%rax),%rsi\ncmp %rdi,%rsi\njne 1230 \nmov $0x30,%r8d\nmov %r8d,%eax\npop %rbx\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest eax, eax\njle short loc_1261\nsub eax, 1\nlea rsi, [rbx+1]\nlea rdi, [rbx+rax+2]\nnop dword ptr [rax]\nloc_1230:\nmovzx r8d, byte ptr [rsi-1]\nmov rax, rbx\nxor edx, edx\nnop word ptr [rax+rax+00h]\nloc_1240:\nxor ecx, ecx\ncmp r8b, [rax]\nsetz cl\nadd rax, 1\nadd edx, ecx\ncmp rsi, rax\njnz short loc_1240\ncmp edx, 1\njg short loc_1267\nadd rsi, 1\ncmp rsi, rdi\njnz short loc_1230\nloc_1261:\nmov r8d, 30h ; '0'\nloc_1267:\nmov eax, r8d\npop rbx\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v2; // eax\n const char *v3; // rsi\n __int64 v4; // rdi\n unsigned int v5; // r8d\n const char *v6; // rax\n int v7; // edx\n int v8; // ecx\n\n v2 = strlen(a1);\n if ( v2 <= 0 )\n {\n return 48;\n }\n else\n {\n v3 = a1 + 1;\n v4 = (__int64)&a1[v2 - 1 + 2];\n while ( 1 )\n {\n v5 = *((unsigned __int8 *)v3 - 1);\n v6 = a1;\n v7 = 0;\n do\n {\n v8 = (_BYTE)v5 == *v6++;\n v7 += v8;\n }\n while ( v3 != v6 );\n if ( v7 > 1 )\n break;\n if ( ++v3 == (const char *)v4 )\n return 48;\n }\n }\n return v5;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest eax, eax\njle short loc_1261\nsub eax, 1\nlea rsi, [rbx+1]\nlea rdi, [rbx+rax+2]\nnop dword ptr [rax]\nloc_1230:\nmovzx r8d, byte ptr [rsi-1]\nmov rax, rbx\nxor edx, edx\nnop word ptr [rax+rax+00h]\nloc_1240:\nxor ecx, ecx\ncmp r8b, [rax]\nsetz cl\nadd rax, 1\nadd edx, ecx\ncmp rsi, rax\njnz short loc_1240\ncmp edx, 1\njg short loc_1267\nadd rsi, 1\ncmp rsi, rdi\njnz short loc_1230\nloc_1261:\nmov r8d, 30h ; '0'\nloc_1267:\nmov eax, r8d\npop rbx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(const char *a1)\n{\n int v2; // eax\n const char *v3; // rsi\n __int64 v4; // rdi\n unsigned int v5; // r8d\n const char *v6; // rax\n int v7; // edx\n int v8; // ecx\n\n v2 = strlen(a1);\n if ( v2 <= 0 )\n {\n return 48;\n }\n else\n {\n v3 = a1 + 1;\n v4 = (__int64)&a1[v2 - 1 + 2];\n while ( 1 )\n {\n v5 = *((unsigned __int8 *)v3 - 1);\n v6 = a1;\n v7 = 0;\n do\n {\n v8 = (_BYTE)v5 == *v6++;\n v7 += v8;\n }\n while ( v3 != v6 );\n if ( v7 > 1 )\n break;\n if ( ++v3 == (const char *)v4 )\n return 48;\n }\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(const char *a1) {\n int v2;\n const char *v3;\n long long v4;\n unsigned int v5;\n const char *v6;\n int v7;\n int v8;\n v2 = strlen(a1);\n if (v2 <= 0) {\n return 48;\n } else {\n v3 = a1 + 1;\n v4 = (long long)&a1[v2 - 1 + 2];\n while (1) {\n v5 = *((unsigned char *)v3 - 1);\n v6 = a1;\n v7 = 0;\n do {\n v8 = (uint8_t)v5 == *v6++;\n v7 += v8;\n } while (v3 != v6);\n if (v7 > 1) break;\n if (++v3 == (const char *)v4) return 48;\n }\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v2;\n const char *v3;\n long long v4;\n unsigned int v5;\n const char *v6;\n int v7;\n int v8;\n v2 = strlen(a1);\n if (v2 <= 0) {\n return 48;\n } else {\n v3 = a1 + 1;\n v4 = (long long)&a1[v2 - 1 + 2];\n while (1) {\n v5 = *((unsigned char *)v3 - 1);\n v6 = a1;\n v7 = 0;\n do {\n v8 = (uint8_t)v5 == *v6++;\n v7 += v8;\n } while (v3 != v6);\n if (v7 > 1) break;\n if (++v3 == (const char *)v4) return 48;\n }\n }\n return v5;\n}" + }, + { + "index": 602, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char func0(char* str1) {\n int length = strlen(str1);\n for (int i = 0; i < length; i++) {\n char c = str1[i];\n int count = 0;\n for (int j = 0; j <= i; j++) {\n if (str1[j] == c) {\n count++;\n }\n }\n if (count > 1) {\n return c;\n }\n }\n return '0';\n}", + "test": "int main() {\n\n assert(func0(\"abcabc\") == 'a');\n\n assert(func0(\"abc\") == '0');\n\n assert(func0(\"123123\") == '1');\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\ncallq 1060 \ntest %eax,%eax\njle 14ad \nmov %eax,%r9d\nmov $0x1,%esi\npxor %xmm4,%xmm4\nxor %ecx,%ecx\nmovdqa 0xe65(%rip),%xmm5\npxor %xmm3,%xmm3\nmovzbl -0x1(%rbx,%rsi,1),%r8d\nmov %esi,%edi\ncmp $0xe,%ecx\njle 14c0 \nmovd %r8d,%xmm7\nmov %esi,%edx\npxor %xmm1,%xmm1\nmov %rbx,%rax\npunpcklbw %xmm7,%xmm7\nshr $0x4,%edx\npunpcklwd %xmm7,%xmm7\nshl $0x4,%rdx\npshufd $0x0,%xmm7,%xmm7\nadd %rbx,%rdx\nnopw %cs:0x0(%rax,%rax,1)\nmovdqu (%rax),%xmm0\nmovdqa %xmm4,%xmm6\nadd $0x10,%rax\npcmpeqb %xmm7,%xmm0\npand %xmm5,%xmm0\npcmpgtb %xmm0,%xmm6\nmovdqa %xmm0,%xmm2\npunpcklbw %xmm6,%xmm2\npunpckhbw %xmm6,%xmm0\nmovdqa %xmm3,%xmm6\npcmpgtw %xmm2,%xmm6\nmovdqa %xmm2,%xmm8\npunpcklwd %xmm6,%xmm8\npunpckhwd %xmm6,%xmm2\nmovdqa %xmm0,%xmm6\npaddd %xmm8,%xmm1\npaddd %xmm2,%xmm1\nmovdqa %xmm3,%xmm2\npcmpgtw %xmm0,%xmm2\npunpcklwd %xmm2,%xmm6\npunpckhwd %xmm2,%xmm0\npaddd %xmm6,%xmm1\npaddd %xmm0,%xmm1\ncmp %rax,%rdx\njne 1280 \nmovdqa %xmm1,%xmm0\nmov %edi,%edx\npsrldq $0x8,%xmm0\nand $0xfffffff0,%edx\nand $0xf,%edi\npaddd %xmm1,%xmm0\nmovdqa %xmm0,%xmm1\npsrldq $0x4,%xmm1\npaddd %xmm1,%xmm0\nmovd %xmm0,%eax\nje 1498 \nmovslq %edx,%rdi\ncmp %r8b,(%rbx,%rdi,1)\nsete %dil\nmovzbl %dil,%edi\nadd %edi,%eax\nlea 0x1(%rdx),%edi\ncmp %ecx,%edi\njg 1498 \nmovslq %edi,%rdi\ncmp (%rbx,%rdi,1),%r8b\nsete %dil\nmovzbl %dil,%edi\nadd %edi,%eax\nlea 0x2(%rdx),%edi\ncmp %edi,%ecx\njl 1498 \nmovslq %edi,%rdi\ncmp (%rbx,%rdi,1),%r8b\nsete %dil\nmovzbl %dil,%edi\nadd %edi,%eax\nlea 0x3(%rdx),%edi\ncmp %edi,%ecx\njl 1498 \nmovslq %edi,%rdi\ncmp (%rbx,%rdi,1),%r8b\nsete %dil\nmovzbl %dil,%edi\nadd %edi,%eax\nlea 0x4(%rdx),%edi\ncmp %edi,%ecx\njl 1498 \nmovslq %edi,%rdi\ncmp (%rbx,%rdi,1),%r8b\nsete %dil\nmovzbl %dil,%edi\nadd %edi,%eax\nlea 0x5(%rdx),%edi\ncmp %edi,%ecx\njl 1498 \nmovslq %edi,%rdi\ncmp (%rbx,%rdi,1),%r8b\nsete %dil\nmovzbl %dil,%edi\nadd %edi,%eax\nlea 0x6(%rdx),%edi\ncmp %edi,%ecx\njl 1498 \nmovslq %edi,%rdi\ncmp (%rbx,%rdi,1),%r8b\nsete %dil\nmovzbl %dil,%edi\nadd %edi,%eax\nlea 0x7(%rdx),%edi\ncmp %edi,%ecx\njl 1498 \nmovslq %edi,%rdi\ncmp (%rbx,%rdi,1),%r8b\nsete %dil\nmovzbl %dil,%edi\nadd %edi,%eax\nlea 0x8(%rdx),%edi\ncmp %edi,%ecx\njl 1498 \nmovslq %edi,%rdi\ncmp (%rbx,%rdi,1),%r8b\nsete %dil\nmovzbl %dil,%edi\nadd %edi,%eax\nlea 0x9(%rdx),%edi\ncmp %edi,%ecx\njl 1498 \nmovslq %edi,%rdi\ncmp (%rbx,%rdi,1),%r8b\nsete %dil\nmovzbl %dil,%edi\nadd %edi,%eax\nlea 0xa(%rdx),%edi\ncmp %edi,%ecx\njl 1498 \nmovslq %edi,%rdi\ncmp (%rbx,%rdi,1),%r8b\nsete %dil\nmovzbl %dil,%edi\nadd %edi,%eax\nlea 0xb(%rdx),%edi\ncmp %edi,%ecx\njl 1498 \nmovslq %edi,%rdi\ncmp (%rbx,%rdi,1),%r8b\nsete %dil\nmovzbl %dil,%edi\nadd %edi,%eax\nlea 0xc(%rdx),%edi\ncmp %edi,%ecx\njl 1498 \nmovslq %edi,%rdi\ncmp (%rbx,%rdi,1),%r8b\nsete %dil\nmovzbl %dil,%edi\nadd %edi,%eax\nlea 0xd(%rdx),%edi\ncmp %edi,%ecx\njl 1498 \nmovslq %edi,%rdi\ncmp (%rbx,%rdi,1),%r8b\nsete %dil\nadd $0xe,%edx\nmovzbl %dil,%edi\nadd %edi,%eax\ncmp %edx,%ecx\njl 1498 \nmovslq %edx,%rdx\ncmp (%rbx,%rdx,1),%r8b\nsete %dl\nmovzbl %dl,%edx\nadd %edx,%eax\nnopl 0x0(%rax,%rax,1)\ncmp $0x1,%eax\njg 14b3 \nadd $0x1,%ecx\nadd $0x1,%rsi\ncmp %ecx,%r9d\njne 1240 \nmov $0x30,%r8d\nmov %r8d,%eax\npop %rbx\nretq\nnopl 0x0(%rax,%rax,1)\nxor %edx,%edx\nxor %eax,%eax\njmpq 1310 \nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest eax, eax\njle loc_1474\nmov edi, eax\nmov esi, 1\npxor xmm6, xmm6\nxor edx, edx\npxor xmm5, xmm5\npxor xmm4, xmm4\npxor xmm3, xmm3\nxchg ax, ax\nloc_1240:\nmovzx ecx, byte ptr [rbx+rsi-1]\nmov r9d, esi\ncmp edx, 0Eh\njle loc_1480\nmovd xmm8, ecx\nmov r8d, esi\npxor xmm1, xmm1\nmov rax, rbx\npunpcklbw xmm8, xmm8\nshr r8d, 4\npunpcklwd xmm8, xmm8\nshl r8, 4\npshufd xmm8, xmm8, 0\nadd r8, rbx\nnop dword ptr [rax+rax+00h]\nloc_1280:\nmovdqu xmm0, xmmword ptr [rax]\nmovdqa xmm7, xmm4\nadd rax, 10h\npcmpeqb xmm0, xmm8\npcmpgtb xmm7, xmm0\nmovdqa xmm2, xmm0\npunpcklbw xmm2, xmm7\npunpckhbw xmm0, xmm7\nmovdqa xmm7, xmm3\npcmpgtw xmm7, xmm2\nmovdqa xmm9, xmm2\npunpcklwd xmm9, xmm7\npunpckhwd xmm2, xmm7\nmovdqa xmm7, xmm0\npsubd xmm1, xmm9\npsubd xmm1, xmm2\nmovdqa xmm2, xmm3\npcmpgtw xmm2, xmm0\npunpcklwd xmm7, xmm2\npunpckhwd xmm0, xmm2\npsubd xmm1, xmm7\npsubd xmm1, xmm0\ncmp r8, rax\njnz short loc_1280\nmovdqa xmm0, xmm1\nmov r10d, r9d\npsrldq xmm0, 8\nand r10d, 0FFFFFFF0h\nand r9d, 0Fh\npaddd xmm0, xmm1\nmov r8d, r10d\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\npaddd xmm0, xmm2\nmovd eax, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm1, 8\npaddd xmm0, xmm1\njz loc_1460\nloc_1320:\nmov r11d, edx\nsub r11d, r10d\nlea r9d, [r11+1]\ncmp r11d, 6\njbe loc_13CF\nmovzx eax, cl\nmovq xmm1, qword ptr [rbx+r10]\nmovdqa xmm7, xmm6\nmov ah, al\nmovd xmm2, eax\npshuflw xmm2, xmm2, 0\npcmpeqb xmm1, xmm2\npcmpgtb xmm7, xmm1\nmovdqa xmm2, xmm1\npunpcklbw xmm2, xmm7\npunpcklbw xmm1, xmm7\nmovdqa xmm7, xmm5\npcmpgtw xmm7, xmm2\nmovdqa xmm8, xmm2\npshufd xmm1, xmm1, 4Eh ; 'N'\npunpcklwd xmm8, xmm7\npunpcklwd xmm2, xmm7\nmovdqa xmm7, xmm1\npsubd xmm0, xmm8\npshufd xmm2, xmm2, 4Eh ; 'N'\npsubd xmm0, xmm2\nmovdqa xmm2, xmm5\npcmpgtw xmm2, xmm1\npunpcklwd xmm7, xmm2\npunpcklwd xmm1, xmm2\npsubd xmm0, xmm7\npshufd xmm1, xmm1, 4Eh ; 'N'\npsubd xmm0, xmm1\nmovd r10d, xmm0\npshufd xmm1, xmm0, 0E5h\nmovd eax, xmm1\nadd eax, r10d\nmov r10d, r9d\nand r10d, 0FFFFFFF8h\nadd r8d, r10d\nand r9d, 7\njz loc_1460\nloc_13CF:\nmovsxd r9, r8d\ncmp [rbx+r9], cl\njnz short loc_13DB\nadd eax, 1\nloc_13DB:\nlea r9d, [r8+1]\ncmp edx, r9d\njl short loc_1460\nmovsxd r9, r9d\ncmp cl, [rbx+r9]\njnz short loc_13F0\nadd eax, 1\nloc_13F0:\nlea r9d, [r8+2]\ncmp edx, r9d\njl short loc_1460\nmovsxd r9, r9d\ncmp cl, [rbx+r9]\njnz short loc_1405\nadd eax, 1\nloc_1405:\nlea r9d, [r8+3]\ncmp edx, r9d\njl short loc_1460\nmovsxd r9, r9d\ncmp [rbx+r9], cl\njnz short loc_141A\nadd eax, 1\nloc_141A:\nlea r9d, [r8+4]\ncmp edx, r9d\njl short loc_1460\nmovsxd r9, r9d\ncmp cl, [rbx+r9]\njnz short loc_142F\nadd eax, 1\nloc_142F:\nlea r9d, [r8+5]\ncmp r9d, edx\njg short loc_1460\nmovsxd r9, r9d\ncmp cl, [rbx+r9]\njnz short loc_1444\nadd eax, 1\nloc_1444:\nadd r8d, 6\ncmp edx, r8d\njl short loc_1460\nmovsxd r8, r8d\ncmp cl, [rbx+r8]\njnz short loc_1460\nadd eax, 1\nnop dword ptr [rax+00000000h]\nloc_1460:\ncmp eax, 1\njg short loc_1479\nadd edx, 1\nadd rsi, 1\ncmp edi, edx\njnz loc_1240\nloc_1474:\nmov ecx, 30h ; '0'\nloc_1479:\nmov eax, ecx\npop rbx\nretn\nloc_1480:\npxor xmm0, xmm0\nxor r10d, r10d\nxor r8d, r8d\nxor eax, eax\njmp loc_1320", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v2; // eax\n int v3; // edi\n __int64 v4; // rsi\n int v5; // edx\n unsigned int v6; // ecx\n __m128i v7; // xmm8\n __m128i v8; // xmm1\n const __m128i *v9; // rax\n __m128i v10; // xmm8\n __m128i v11; // xmm8\n __m128i v12; // xmm0\n __m128i v13; // xmm0\n __m128i v14; // xmm7\n __m128i v15; // xmm2\n __m128i v16; // xmm0\n __m128i v17; // xmm7\n __m128i v18; // xmm1\n __m128i v19; // xmm2\n __int64 v20; // r10\n __m128i v21; // xmm0\n int v22; // r8d\n int v23; // eax\n __m128i v24; // xmm0\n int v25; // r9d\n unsigned int v26; // eax\n __m128i v27; // xmm1\n __m128i v28; // xmm2\n __m128i v29; // xmm1\n __m128i v30; // xmm2\n __m128i v31; // xmm1\n __m128i v32; // xmm0\n int v33; // r8d\n\n v2 = strlen(a1);\n if ( v2 > 0 )\n {\n v3 = v2;\n v4 = 1LL;\n v5 = 0;\n while ( 1 )\n {\n v6 = (unsigned __int8)a1[v4 - 1];\n if ( v5 <= 14 )\n break;\n v7 = _mm_cvtsi32_si128(v6);\n v8 = 0LL;\n v9 = (const __m128i *)a1;\n v10 = _mm_unpacklo_epi8(v7, v7);\n v11 = _mm_shuffle_epi32(_mm_unpacklo_epi16(v10, v10), 0);\n do\n {\n v12 = _mm_loadu_si128(v9++);\n v13 = _mm_cmpeq_epi8(v12, v11);\n v14 = _mm_cmpgt_epi8((__m128i)0LL, v13);\n v15 = _mm_unpacklo_epi8(v13, v14);\n v16 = _mm_unpackhi_epi8(v13, v14);\n v17 = _mm_cmpgt_epi16((__m128i)0LL, v15);\n v18 = _mm_sub_epi32(_mm_sub_epi32(v8, _mm_unpacklo_epi16(v15, v17)), _mm_unpackhi_epi16(v15, v17));\n v19 = _mm_cmpgt_epi16((__m128i)0LL, v16);\n v8 = _mm_sub_epi32(_mm_sub_epi32(v18, _mm_unpacklo_epi16(v16, v19)), _mm_unpackhi_epi16(v16, v19));\n }\n while ( &a1[16 * ((unsigned int)v4 >> 4)] != (const char *)v9 );\n v20 = (unsigned int)v4 & 0xFFFFFFF0;\n v21 = _mm_add_epi32(_mm_srli_si128(v8, 8), v8);\n v22 = v4 & 0xFFFFFFF0;\n v23 = _mm_cvtsi128_si32(_mm_add_epi32(v21, _mm_srli_si128(v21, 4)));\n v24 = _mm_add_epi32(v8, _mm_srli_si128(v8, 8));\n if ( (v4 & 0xF) != 0 )\n goto LABEL_7;\nLABEL_29:\n if ( v23 > 1 )\n return v6;\n ++v5;\n ++v4;\n if ( v3 == v5 )\n return 48;\n }\n v24 = 0LL;\n v20 = 0LL;\n v22 = 0;\n v23 = 0;\nLABEL_7:\n v25 = v5 - v20 + 1;\n if ( (unsigned int)(v5 - v20) <= 6 )\n goto LABEL_9;\n v26 = (unsigned __int8)v6;\n BYTE1(v26) = a1[v4 - 1];\n v27 = _mm_cmpeq_epi8(_mm_loadl_epi64((const __m128i *)&a1[v20]), _mm_shufflelo_epi16(_mm_cvtsi32_si128(v26), 0));\n v28 = _mm_unpacklo_epi8(v27, _mm_cmpgt_epi8((__m128i)0LL, v27));\n v29 = _mm_shuffle_epi32(v28, 78);\n v30 = _mm_unpacklo_epi16(v28, _mm_cmpgt_epi16((__m128i)0LL, v28));\n v31 = _mm_unpacklo_epi16(v29, _mm_cmpgt_epi16((__m128i)0LL, v29));\n v32 = _mm_sub_epi32(\n _mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(v24, v30), _mm_shuffle_epi32(v30, 78)), v31),\n _mm_shuffle_epi32(v31, 78));\n v23 = _mm_cvtsi128_si32(v32) + _mm_cvtsi128_si32(_mm_shuffle_epi32(v32, 229));\n v22 += v25 & 0xFFFFFFF8;\n if ( (v25 & 7) != 0 )\n {\nLABEL_9:\n if ( a1[v22] == (_BYTE)v6 )\n ++v23;\n if ( v5 >= v22 + 1 )\n {\n if ( (_BYTE)v6 == a1[v22 + 1] )\n ++v23;\n if ( v5 >= v22 + 2 )\n {\n if ( (_BYTE)v6 == a1[v22 + 2] )\n ++v23;\n if ( v5 >= v22 + 3 )\n {\n if ( a1[v22 + 3] == (_BYTE)v6 )\n ++v23;\n if ( v5 >= v22 + 4 )\n {\n if ( (_BYTE)v6 == a1[v22 + 4] )\n ++v23;\n if ( v22 + 5 <= v5 )\n {\n if ( (_BYTE)v6 == a1[v22 + 5] )\n ++v23;\n v33 = v22 + 6;\n if ( v5 >= v33 && (_BYTE)v6 == a1[v33] )\n ++v23;\n }\n }\n }\n }\n }\n }\n goto LABEL_29;\n }\n return 48;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest eax, eax\njle loc_1474\nmov edi, eax\nmov esi, 1\npxor xmm6, xmm6\nxor edx, edx\npxor xmm5, xmm5\npxor xmm4, xmm4\npxor xmm3, xmm3\nxchg ax, ax\nloc_1240:\nmovzx ecx, byte ptr [rbx+rsi-1]\nmov r9d, esi\ncmp edx, 0Eh\njle loc_1480\nmovd xmm8, ecx\nmov r8d, esi\npxor xmm1, xmm1\nmov rax, rbx\npunpcklbw xmm8, xmm8\nshr r8d, 4\npunpcklwd xmm8, xmm8\nshl r8, 4\npshufd xmm8, xmm8, 0\nadd r8, rbx\nnop dword ptr [rax+rax+00h]\nloc_1280:\nmovdqu xmm0, xmmword ptr [rax]\nmovdqa xmm7, xmm4\nadd rax, 10h\npcmpeqb xmm0, xmm8\npcmpgtb xmm7, xmm0\nmovdqa xmm2, xmm0\npunpcklbw xmm2, xmm7\npunpckhbw xmm0, xmm7\nmovdqa xmm7, xmm3\npcmpgtw xmm7, xmm2\nmovdqa xmm9, xmm2\npunpcklwd xmm9, xmm7\npunpckhwd xmm2, xmm7\nmovdqa xmm7, xmm0\npsubd xmm1, xmm9\npsubd xmm1, xmm2\nmovdqa xmm2, xmm3\npcmpgtw xmm2, xmm0\npunpcklwd xmm7, xmm2\npunpckhwd xmm0, xmm2\npsubd xmm1, xmm7\npsubd xmm1, xmm0\ncmp r8, rax\njnz short loc_1280\nmovdqa xmm0, xmm1\nmov r10d, r9d\npsrldq xmm0, 8\nand r10d, 0FFFFFFF0h\nand r9d, 0Fh\npaddd xmm0, xmm1\nmov r8d, r10d\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\npaddd xmm0, xmm2\nmovd eax, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm1, 8\npaddd xmm0, xmm1\njz loc_1460\nloc_1320:\nmov r11d, edx\nsub r11d, r10d\nlea r9d, [r11+1]\ncmp r11d, 6\njbe loc_13CF\nmovzx eax, cl\nmovq xmm1, qword ptr [rbx+r10]\nmovdqa xmm7, xmm6\nmov ah, al\nmovd xmm2, eax\npshuflw xmm2, xmm2, 0\npcmpeqb xmm1, xmm2\npcmpgtb xmm7, xmm1\nmovdqa xmm2, xmm1\npunpcklbw xmm2, xmm7\npunpcklbw xmm1, xmm7\nmovdqa xmm7, xmm5\npcmpgtw xmm7, xmm2\nmovdqa xmm8, xmm2\npshufd xmm1, xmm1, 4Eh ; 'N'\npunpcklwd xmm8, xmm7\npunpcklwd xmm2, xmm7\nmovdqa xmm7, xmm1\npsubd xmm0, xmm8\npshufd xmm2, xmm2, 4Eh ; 'N'\npsubd xmm0, xmm2\nmovdqa xmm2, xmm5\npcmpgtw xmm2, xmm1\npunpcklwd xmm7, xmm2\npunpcklwd xmm1, xmm2\npsubd xmm0, xmm7\npshufd xmm1, xmm1, 4Eh ; 'N'\npsubd xmm0, xmm1\nmovd r10d, xmm0\npshufd xmm1, xmm0, 0E5h\nmovd eax, xmm1\nadd eax, r10d\nmov r10d, r9d\nand r10d, 0FFFFFFF8h\nadd r8d, r10d\nand r9d, 7\njz loc_1460\nloc_13CF:\nmovsxd r9, r8d\ncmp [rbx+r9], cl\njnz short loc_13DB\nadd eax, 1\nloc_13DB:\nlea r9d, [r8+1]\ncmp edx, r9d\njl short loc_1460\nmovsxd r9, r9d\ncmp cl, [rbx+r9]\njnz short loc_13F0\nadd eax, 1\nloc_13F0:\nlea r9d, [r8+2]\ncmp edx, r9d\njl short loc_1460\nmovsxd r9, r9d\ncmp cl, [rbx+r9]\njnz short loc_1405\nadd eax, 1\nloc_1405:\nlea r9d, [r8+3]\ncmp edx, r9d\njl short loc_1460\nmovsxd r9, r9d\ncmp [rbx+r9], cl\njnz short loc_141A\nadd eax, 1\nloc_141A:\nlea r9d, [r8+4]\ncmp edx, r9d\njl short loc_1460\nmovsxd r9, r9d\ncmp cl, [rbx+r9]\njnz short loc_142F\nadd eax, 1\nloc_142F:\nlea r9d, [r8+5]\ncmp r9d, edx\njg short loc_1460\nmovsxd r9, r9d\ncmp cl, [rbx+r9]\njnz short loc_1444\nadd eax, 1\nloc_1444:\nadd r8d, 6\ncmp edx, r8d\njl short loc_1460\nmovsxd r8, r8d\ncmp cl, [rbx+r8]\njnz short loc_1460\nadd eax, 1\nnop dword ptr [rax+00000000h]\nloc_1460:\ncmp eax, 1\njg short loc_1479\nadd edx, 1\nadd rsi, 1\ncmp edi, edx\njnz loc_1240\nloc_1474:\nmov ecx, 30h ; '0'\nloc_1479:\nmov eax, ecx\npop rbx\nretn\nloc_1480:\npxor xmm0, xmm0\nxor r10d, r10d\nxor r8d, r8d\nxor eax, eax\njmp loc_1320", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(const char *a1)\n{\n int v2; // eax\n int v3; // edi\n __int64 v4; // rsi\n int v5; // edx\n unsigned int v6; // ecx\n __m128i v7; // xmm8\n __m128i v8; // xmm1\n const __m128i *v9; // rax\n __m128i v10; // xmm8\n __m128i v11; // xmm8\n __m128i v12; // xmm0\n __m128i v13; // xmm0\n __m128i v14; // xmm7\n __m128i v15; // xmm2\n __m128i v16; // xmm0\n __m128i v17; // xmm7\n __m128i v18; // xmm1\n __m128i v19; // xmm2\n __int64 v20; // r10\n __m128i v21; // xmm0\n int v22; // r8d\n int v23; // eax\n __m128i v24; // xmm0\n int v25; // r9d\n unsigned int v26; // eax\n __m128i v27; // xmm1\n __m128i v28; // xmm2\n __m128i v29; // xmm1\n __m128i v30; // xmm2\n __m128i v31; // xmm1\n __m128i v32; // xmm0\n int v33; // r8d\n\n v2 = strlen(a1);\n if ( v2 > 0 )\n {\n v3 = v2;\n v4 = 1LL;\n v5 = 0;\n while ( 1 )\n {\n v6 = (unsigned __int8)a1[v4 - 1];\n if ( v5 <= 14 )\n break;\n v7 = _mm_cvtsi32_si128(v6);\n v8 = 0LL;\n v9 = (const __m128i *)a1;\n v10 = _mm_unpacklo_epi8(v7, v7);\n v11 = _mm_shuffle_epi32(_mm_unpacklo_epi16(v10, v10), 0);\n do\n {\n v12 = _mm_loadu_si128(v9++);\n v13 = _mm_cmpeq_epi8(v12, v11);\n v14 = _mm_cmpgt_epi8((__m128i)0LL, v13);\n v15 = _mm_unpacklo_epi8(v13, v14);\n v16 = _mm_unpackhi_epi8(v13, v14);\n v17 = _mm_cmpgt_epi16((__m128i)0LL, v15);\n v18 = _mm_sub_epi32(_mm_sub_epi32(v8, _mm_unpacklo_epi16(v15, v17)), _mm_unpackhi_epi16(v15, v17));\n v19 = _mm_cmpgt_epi16((__m128i)0LL, v16);\n v8 = _mm_sub_epi32(_mm_sub_epi32(v18, _mm_unpacklo_epi16(v16, v19)), _mm_unpackhi_epi16(v16, v19));\n }\n while ( &a1[16 * ((unsigned int)v4 >> 4)] != (const char *)v9 );\n v20 = (unsigned int)v4 & 0xFFFFFFF0;\n v21 = _mm_add_epi32(_mm_srli_si128(v8, 8), v8);\n v22 = v4 & 0xFFFFFFF0;\n v23 = _mm_cvtsi128_si32(_mm_add_epi32(v21, _mm_srli_si128(v21, 4)));\n v24 = _mm_add_epi32(v8, _mm_srli_si128(v8, 8));\n if ( (v4 & 0xF) != 0 )\n goto LABEL_7;\nLABEL_29:\n if ( v23 > 1 )\n return v6;\n ++v5;\n ++v4;\n if ( v3 == v5 )\n return 48;\n }\n v24 = 0LL;\n v20 = 0LL;\n v22 = 0;\n v23 = 0;\nLABEL_7:\n v25 = v5 - v20 + 1;\n if ( (unsigned int)(v5 - v20) <= 6 )\n goto LABEL_9;\n v26 = (unsigned __int8)v6;\n BYTE1(v26) = a1[v4 - 1];\n v27 = _mm_cmpeq_epi8(_mm_loadl_epi64((const __m128i *)&a1[v20]), _mm_shufflelo_epi16(_mm_cvtsi32_si128(v26), 0));\n v28 = _mm_unpacklo_epi8(v27, _mm_cmpgt_epi8((__m128i)0LL, v27));\n v29 = _mm_shuffle_epi32(v28, 78);\n v30 = _mm_unpacklo_epi16(v28, _mm_cmpgt_epi16((__m128i)0LL, v28));\n v31 = _mm_unpacklo_epi16(v29, _mm_cmpgt_epi16((__m128i)0LL, v29));\n v32 = _mm_sub_epi32(\n _mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(v24, v30), _mm_shuffle_epi32(v30, 78)), v31),\n _mm_shuffle_epi32(v31, 78));\n v23 = _mm_cvtsi128_si32(v32) + _mm_cvtsi128_si32(_mm_shuffle_epi32(v32, 229));\n v22 += v25 & 0xFFFFFFF8;\n if ( (v25 & 7) != 0 )\n {\nLABEL_9:\n if ( a1[v22] == (_BYTE)v6 )\n ++v23;\n if ( v5 >= v22 + 1 )\n {\n if ( (_BYTE)v6 == a1[v22 + 1] )\n ++v23;\n if ( v5 >= v22 + 2 )\n {\n if ( (_BYTE)v6 == a1[v22 + 2] )\n ++v23;\n if ( v5 >= v22 + 3 )\n {\n if ( a1[v22 + 3] == (_BYTE)v6 )\n ++v23;\n if ( v5 >= v22 + 4 )\n {\n if ( (_BYTE)v6 == a1[v22 + 4] )\n ++v23;\n if ( v22 + 5 <= v5 )\n {\n if ( (_BYTE)v6 == a1[v22 + 5] )\n ++v23;\n v33 = v22 + 6;\n if ( v5 >= v33 && (_BYTE)v6 == a1[v33] )\n ++v23;\n }\n }\n }\n }\n }\n }\n goto LABEL_29;\n }\n return 48;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(const char *a1) {\n int v2;\n int v3;\n long long v4;\n int v5;\n unsigned int v6;\n __m128i v7;\n __m128i v8;\n const __m128i *v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n __m128i v15;\n __m128i v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n long long v20;\n __m128i v21;\n int v22;\n int v23;\n __m128i v24;\n int v25;\n unsigned int v26;\n __m128i v27;\n __m128i v28;\n __m128i v29;\n __m128i v30;\n __m128i v31;\n __m128i v32;\n int v33;\n v2 = strlen(a1);\n if (v2 > 0) {\n v3 = v2;\n v4 = 1LL;\n v5 = 0;\n while (1) {\n v6 = (unsigned char)a1[v4 - 1];\n if (v5 <= 14) break;\n v7 = _mm_cvtsi32_si128(v6);\n v8 = 0LL;\n v9 = (const __m128i *)a1;\n v10 = _mm_unpacklo_epi8(v7, v7);\n v11 = _mm_shuffle_epi32(_mm_unpacklo_epi16(v10, v10), 0);\n do {\n v12 = _mm_loadu_si128(v9++);\n v13 = _mm_cmpeq_epi8(v12, v11);\n v14 = _mm_cmpgt_epi8((__m128i)0LL, v13);\n v15 = _mm_unpacklo_epi8(v13, v14);\n v16 = _mm_unpackhi_epi8(v13, v14);\n v17 = _mm_cmpgt_epi16((__m128i)0LL, v15);\n v18 = _mm_sub_epi32(_mm_sub_epi32(v8, _mm_unpacklo_epi16(v15, v17)),\n _mm_unpackhi_epi16(v15, v17));\n v19 = _mm_cmpgt_epi16((__m128i)0LL, v16);\n v8 = _mm_sub_epi32(_mm_sub_epi32(v18, _mm_unpacklo_epi16(v16, v19)),\n _mm_unpackhi_epi16(v16, v19));\n } while (&a1[16 * ((unsigned int)v4 >> 4)] != (const char *)v9);\n v20 = (unsigned int)v4 & 4294967280;\n v21 = _mm_add_epi32(_mm_srli_si128(v8, 8), v8);\n v22 = v4 & 4294967280;\n v23 = _mm_cvtsi128_si32(_mm_add_epi32(v21, _mm_srli_si128(v21, 4)));\n v24 = _mm_add_epi32(v8, _mm_srli_si128(v8, 8));\n if ((v4 & 15) != 0) goto LABEL_7;\n LABEL_29:\n if (v23 > 1) return v6;\n ++v5;\n ++v4;\n if (v3 == v5) return 48;\n }\n v24 = 0LL;\n v20 = 0LL;\n v22 = 0;\n v23 = 0;\n LABEL_7:\n v25 = v5 - v20 + 1;\n if ((unsigned int)(v5 - v20) <= 6) goto LABEL_9;\n v26 = (unsigned char)v6;\n BYTE1(v26) = a1[v4 - 1];\n v27 = _mm_cmpeq_epi8(_mm_loadl_epi64((const __m128i *)&a1[v20]),\n _mm_shufflelo_epi16(_mm_cvtsi32_si128(v26), 0));\n v28 = _mm_unpacklo_epi8(v27, _mm_cmpgt_epi8((__m128i)0LL, v27));\n v29 = _mm_shuffle_epi32(v28, 78);\n v30 = _mm_unpacklo_epi16(v28, _mm_cmpgt_epi16((__m128i)0LL, v28));\n v31 = _mm_unpacklo_epi16(v29, _mm_cmpgt_epi16((__m128i)0LL, v29));\n v32 = _mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(v24, v30),\n _mm_shuffle_epi32(v30, 78)),\n v31),\n _mm_shuffle_epi32(v31, 78));\n v23 =\n _mm_cvtsi128_si32(v32) + _mm_cvtsi128_si32(_mm_shuffle_epi32(v32, 229));\n v22 += v25 & 4294967288;\n if ((v25 & 7) != 0) {\n LABEL_9:\n if (a1[v22] == (uint8_t)v6) ++v23;\n if (v5 >= v22 + 1) {\n if ((uint8_t)v6 == a1[v22 + 1]) ++v23;\n if (v5 >= v22 + 2) {\n if ((uint8_t)v6 == a1[v22 + 2]) ++v23;\n if (v5 >= v22 + 3) {\n if (a1[v22 + 3] == (uint8_t)v6) ++v23;\n if (v5 >= v22 + 4) {\n if ((uint8_t)v6 == a1[v22 + 4]) ++v23;\n if (v22 + 5 <= v5) {\n if ((uint8_t)v6 == a1[v22 + 5]) ++v23;\n v33 = v22 + 6;\n if (v5 >= v33 && (uint8_t)v6 == a1[v33]) ++v23;\n }\n }\n }\n }\n }\n }\n goto LABEL_29;\n }\n return 48;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v2;\n int v3;\n long long v4;\n int v5;\n unsigned int v6;\n __m128i v7;\n __m128i v8;\n const __m128i *v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n __m128i v15;\n __m128i v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n long long v20;\n __m128i v21;\n int v22;\n int v23;\n __m128i v24;\n int v25;\n unsigned int v26;\n __m128i v27;\n __m128i v28;\n __m128i v29;\n __m128i v30;\n __m128i v31;\n __m128i v32;\n int v33;\n v2 = strlen(a1);\n if (v2 > 0) {\n v3 = v2;\n v4 = 1LL;\n v5 = 0;\n while (1) {\n v6 = (unsigned char)a1[v4 - 1];\n if (v5 <= 14) break;\n v7 = _mm_cvtsi32_si128(v6);\n v8 = 0LL;\n v9 = (const __m128i *)a1;\n v10 = _mm_unpacklo_epi8(v7, v7);\n v11 = _mm_shuffle_epi32(_mm_unpacklo_epi16(v10, v10), 0);\n do {\n v12 = _mm_loadu_si128(v9++);\n v13 = _mm_cmpeq_epi8(v12, v11);\n v14 = _mm_cmpgt_epi8((__m128i)0LL, v13);\n v15 = _mm_unpacklo_epi8(v13, v14);\n v16 = _mm_unpackhi_epi8(v13, v14);\n v17 = _mm_cmpgt_epi16((__m128i)0LL, v15);\n v18 = _mm_sub_epi32(_mm_sub_epi32(v8, _mm_unpacklo_epi16(v15, v17)),\n _mm_unpackhi_epi16(v15, v17));\n v19 = _mm_cmpgt_epi16((__m128i)0LL, v16);\n v8 = _mm_sub_epi32(_mm_sub_epi32(v18, _mm_unpacklo_epi16(v16, v19)),\n _mm_unpackhi_epi16(v16, v19));\n } while (&a1[16 * ((unsigned int)v4 >> 4)] != (const char *)v9);\n v20 = (unsigned int)v4 & 4294967280;\n v21 = _mm_add_epi32(_mm_srli_si128(v8, 8), v8);\n v22 = v4 & 4294967280;\n v23 = _mm_cvtsi128_si32(_mm_add_epi32(v21, _mm_srli_si128(v21, 4)));\n v24 = _mm_add_epi32(v8, _mm_srli_si128(v8, 8));\n if ((v4 & 15) != 0) goto LABEL_7;\n LABEL_29:\n if (v23 > 1) return v6;\n ++v5;\n ++v4;\n if (v3 == v5) return 48;\n }\n v24 = 0LL;\n v20 = 0LL;\n v22 = 0;\n v23 = 0;\n LABEL_7:\n v25 = v5 - v20 + 1;\n if ((unsigned int)(v5 - v20) <= 6) goto LABEL_9;\n v26 = (unsigned char)v6;\n BYTE1(v26) = a1[v4 - 1];\n v27 = _mm_cmpeq_epi8(_mm_loadl_epi64((const __m128i *)&a1[v20]),\n _mm_shufflelo_epi16(_mm_cvtsi32_si128(v26), 0));\n v28 = _mm_unpacklo_epi8(v27, _mm_cmpgt_epi8((__m128i)0LL, v27));\n v29 = _mm_shuffle_epi32(v28, 78);\n v30 = _mm_unpacklo_epi16(v28, _mm_cmpgt_epi16((__m128i)0LL, v28));\n v31 = _mm_unpacklo_epi16(v29, _mm_cmpgt_epi16((__m128i)0LL, v29));\n v32 = _mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(v24, v30),\n _mm_shuffle_epi32(v30, 78)),\n v31),\n _mm_shuffle_epi32(v31, 78));\n v23 =\n _mm_cvtsi128_si32(v32) + _mm_cvtsi128_si32(_mm_shuffle_epi32(v32, 229));\n v22 += v25 & 4294967288;\n if ((v25 & 7) != 0) {\n LABEL_9:\n if (a1[v22] == (uint8_t)v6) ++v23;\n if (v5 >= v22 + 1) {\n if ((uint8_t)v6 == a1[v22 + 1]) ++v23;\n if (v5 >= v22 + 2) {\n if ((uint8_t)v6 == a1[v22 + 2]) ++v23;\n if (v5 >= v22 + 3) {\n if (a1[v22 + 3] == (uint8_t)v6) ++v23;\n if (v5 >= v22 + 4) {\n if ((uint8_t)v6 == a1[v22 + 4]) ++v23;\n if (v22 + 5 <= v5) {\n if ((uint8_t)v6 == a1[v22 + 5]) ++v23;\n v33 = v22 + 6;\n if (v5 >= v33 && (uint8_t)v6 == a1[v33]) ++v23;\n }\n }\n }\n }\n }\n }\n goto LABEL_29;\n }\n return 48;\n}" + }, + { + "index": 603, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int n, int* ludic_size) {\n int* ludics = (int*)malloc(sizeof(int) * n);\n for (int i = 0; i < n; i++) {\n ludics[i] = i + 1;\n }\n int current_size = n;\n int index = 1;\n while (index < current_size) {\n int first_ludic = ludics[index];\n int remove_index = index + first_ludic;\n while (remove_index < current_size) {\n for (int j = remove_index; j < current_size - 1; j++) {\n ludics[j] = ludics[j + 1];\n }\n current_size -= 1;\n remove_index += first_ludic - 1;\n }\n index += 1;\n }\n *ludic_size = current_size;\n return ludics;\n}", + "test": "int main() {\n\n int size;\n\n int* result;\n\n\n\n result = func0(10, &size);\n\n assert(size == 5 && result[0] == 1 && result[1] == 2 && result[2] == 3 && result[3] == 5 && result[4] == 7);\n\n free(result);\n\n\n\n result = func0(25, &size);\n\n assert(size == 10 && result[0] == 1 && result[1] == 2 && result[2] == 3 && result[3] == 5 && result[4] == 7 && result[5] == 11 && result[6] == 13 && result[7] == 17 && result[8] == 23 && result[9] == 25);\n\n free(result);\n\n\n\n result = func0(45, &size);\n\n assert(size == 14 && result[0] == 1 && result[1] == 2 && result[2] == 3 && result[3] == 5 && result[4] == 7 && result[5] == 11 && result[6] == 13 && result[7] == 17 && result[8] == 23 && result[9] == 25 && result[10] == 29 && result[11] == 37 && result[12] == 41 && result[13] == 43);\n\n free(result);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %edi,-0x24(%rbp)\nmov %rsi,-0x30(%rbp)\nmov -0x24(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0x20(%rbp)\njmp 11fa \nmov -0x20(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov -0x20(%rbp),%edx\nadd $0x1,%edx\nmov %edx,(%rax)\naddl $0x1,-0x20(%rbp)\nmov -0x20(%rbp),%eax\ncmp -0x24(%rbp),%eax\njl 11da \nmov -0x24(%rbp),%eax\nmov %eax,-0x1c(%rbp)\nmovl $0x1,-0x18(%rbp)\njmpq 129b \nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0xc(%rbp)\nmov -0x18(%rbp),%edx\nmov -0xc(%rbp),%eax\nadd %edx,%eax\nmov %eax,-0x14(%rbp)\njmp 128f \nmov -0x14(%rbp),%eax\nmov %eax,-0x10(%rbp)\njmp 1277 \nmov -0x10(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov -0x10(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x10(%rbp)\nmov -0x1c(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x10(%rbp)\njl 1242 \nsubl $0x1,-0x1c(%rbp)\nmov -0xc(%rbp),%eax\nsub $0x1,%eax\nadd %eax,-0x14(%rbp)\nmov -0x14(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 123a \naddl $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1214 \nmov -0x30(%rbp),%rax\nmov -0x1c(%rbp),%edx\nmov %edx,(%rax)\nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_24], edi\nmov [rbp+var_30], rsi\nmov eax, [rbp+var_24]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_20], 0\njmp short loc_11FA\nloc_11DA:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rbp+var_20]\nadd edx, 1\nmov [rax], edx\nadd [rbp+var_20], 1\nloc_11FA:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_24]\njl short loc_11DA\nmov eax, [rbp+var_24]\nmov [rbp+var_1C], eax\nmov [rbp+var_18], 1\njmp loc_129B\nloc_1214:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nmov edx, [rbp+var_18]\nmov eax, [rbp+var_C]\nadd eax, edx\nmov [rbp+var_14], eax\njmp short loc_128F\nloc_123A:\nmov eax, [rbp+var_14]\nmov [rbp+var_10], eax\njmp short loc_1277\nloc_1242:\nmov eax, [rbp+var_10]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_10], 1\nloc_1277:\nmov eax, [rbp+var_1C]\nsub eax, 1\ncmp [rbp+var_10], eax\njl short loc_1242\nsub [rbp+var_1C], 1\nmov eax, [rbp+var_C]\nsub eax, 1\nadd [rbp+var_14], eax\nloc_128F:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_1C]\njl short loc_123A\nadd [rbp+var_18], 1\nloc_129B:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_1C]\njl loc_1214\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_1C]\nmov [rax], edx\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int a1, int *a2)\n{\n int i; // [rsp+10h] [rbp-20h]\n int v4; // [rsp+14h] [rbp-1Ch]\n int j; // [rsp+18h] [rbp-18h]\n int k; // [rsp+1Ch] [rbp-14h]\n int m; // [rsp+20h] [rbp-10h]\n int v8; // [rsp+24h] [rbp-Ch]\n _DWORD *v9; // [rsp+28h] [rbp-8h]\n\n v9 = malloc(4LL * a1);\n for ( i = 0; i < a1; ++i )\n v9[i] = i + 1;\n v4 = a1;\n for ( j = 1; j < v4; ++j )\n {\n v8 = v9[j];\n for ( k = j + v8; k < v4; k += v8 - 1 )\n {\n for ( m = k; m < v4 - 1; ++m )\n v9[m] = v9[m + 1];\n --v4;\n }\n }\n *a2 = v4;\n return v9;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_24], edi\nmov [rbp+var_30], rsi\nmov eax, [rbp+var_24]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_20], 0\njmp short loc_11FA\nloc_11DA:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rbp+var_20]\nadd edx, 1\nmov [rax], edx\nadd [rbp+var_20], 1\nloc_11FA:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_24]\njl short loc_11DA\nmov eax, [rbp+var_24]\nmov [rbp+var_1C], eax\nmov [rbp+var_18], 1\njmp loc_129B\nloc_1214:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nmov edx, [rbp+var_18]\nmov eax, [rbp+var_C]\nadd eax, edx\nmov [rbp+var_14], eax\njmp short loc_128F\nloc_123A:\nmov eax, [rbp+var_14]\nmov [rbp+var_10], eax\njmp short loc_1277\nloc_1242:\nmov eax, [rbp+var_10]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_10], 1\nloc_1277:\nmov eax, [rbp+var_1C]\nsub eax, 1\ncmp [rbp+var_10], eax\njl short loc_1242\nsub [rbp+var_1C], 1\nmov eax, [rbp+var_C]\nsub eax, 1\nadd [rbp+var_14], eax\nloc_128F:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_1C]\njl short loc_123A\nadd [rbp+var_18], 1\nloc_129B:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_1C]\njl loc_1214\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_1C]\nmov [rax], edx\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(int a1, int *a2)\n{\n int i; // [rsp+10h] [rbp-20h]\n int v4; // [rsp+14h] [rbp-1Ch]\n int j; // [rsp+18h] [rbp-18h]\n int k; // [rsp+1Ch] [rbp-14h]\n int m; // [rsp+20h] [rbp-10h]\n int v8; // [rsp+24h] [rbp-Ch]\n _DWORD *v9; // [rsp+28h] [rbp-8h]\n\n v9 = malloc(4LL * a1);\n for ( i = 0; i < a1; ++i )\n v9[i] = i + 1;\n v4 = a1;\n for ( j = 1; j < v4; ++j )\n {\n v8 = v9[j];\n for ( k = j + v8; k < v4; k += v8 - 1 )\n {\n for ( m = k; m < v4 - 1; ++m )\n v9[m] = v9[m + 1];\n --v4;\n }\n }\n *a2 = v4;\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(int a1, int *a2) {\n int i;\n int v4;\n int j;\n int k;\n int m;\n int v8;\n uint32_t *v9;\n v9 = malloc(4LL * a1);\n for (i = 0; i < a1; ++i) v9[i] = i + 1;\n v4 = a1;\n for (j = 1; j < v4; ++j) {\n v8 = v9[j];\n for (k = j + v8; k < v4; k += v8 - 1) {\n for (m = k; m < v4 - 1; ++m) v9[m] = v9[m + 1];\n --v4;\n }\n }\n *a2 = v4;\n return v9;\n}", + "ida_pseudo_norm": "uint32_t *func0(int a1, int *a2) {\n int i;\n int v4;\n int j;\n int k;\n int m;\n int v8;\n uint32_t *v9;\n v9 = malloc(4LL * a1);\n for (i = 0; i < a1; ++i) v9[i] = i + 1;\n v4 = a1;\n for (j = 1; j < v4; ++j) {\n v8 = v9[j];\n for (k = j + v8; k < v4; k += v8 - 1) {\n for (m = k; m < v4 - 1; ++m) v9[m] = v9[m + 1];\n --v4;\n }\n }\n *a2 = v4;\n return v9;\n}" + }, + { + "index": 603, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int n, int* ludic_size) {\n int* ludics = (int*)malloc(sizeof(int) * n);\n for (int i = 0; i < n; i++) {\n ludics[i] = i + 1;\n }\n int current_size = n;\n int index = 1;\n while (index < current_size) {\n int first_ludic = ludics[index];\n int remove_index = index + first_ludic;\n while (remove_index < current_size) {\n for (int j = remove_index; j < current_size - 1; j++) {\n ludics[j] = ludics[j + 1];\n }\n current_size -= 1;\n remove_index += first_ludic - 1;\n }\n index += 1;\n }\n *ludic_size = current_size;\n return ludics;\n}", + "test": "int main() {\n\n int size;\n\n int* result;\n\n\n\n result = func0(10, &size);\n\n assert(size == 5 && result[0] == 1 && result[1] == 2 && result[2] == 3 && result[3] == 5 && result[4] == 7);\n\n free(result);\n\n\n\n result = func0(25, &size);\n\n assert(size == 10 && result[0] == 1 && result[1] == 2 && result[2] == 3 && result[3] == 5 && result[4] == 7 && result[5] == 11 && result[6] == 13 && result[7] == 17 && result[8] == 23 && result[9] == 25);\n\n free(result);\n\n\n\n result = func0(45, &size);\n\n assert(size == 14 && result[0] == 1 && result[1] == 2 && result[2] == 3 && result[3] == 5 && result[4] == 7 && result[5] == 11 && result[6] == 13 && result[7] == 17 && result[8] == 23 && result[9] == 25 && result[10] == 29 && result[11] == 37 && result[12] == 41 && result[13] == 43);\n\n free(result);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %edi,%ebx\nmov %rsi,%r14\nmovslq %edi,%rdi\nshl $0x2,%rdi\ncallq 10b0 \nmov %rax,%r11\ntest %ebx,%ebx\njle 11e7 \nlea -0x1(%rbx),%edx\nadd $0x2,%rdx\nmov $0x1,%eax\nmov %eax,-0x4(%r11,%rax,4)\nadd $0x1,%rax\ncmp %rdx,%rax\njne 11d9 \ncmp $0x1,%ebx\njle 1255 \nmov $0x1,%r13d\nlea 0x4(%r11),%r12\njmp 1232 \nlea (%r11,%rdi,4),%rax\nmov %r8d,%edx\nadd %rdi,%rdx\nlea (%r12,%rdx,4),%rcx\nmov 0x4(%rax),%edx\nmov %edx,(%rax)\nadd $0x4,%rax\ncmp %rcx,%rax\njne 1206 \nadd %ebp,%esi\nsub %r9d,%r8d\nadd %r10,%rdi\ncmp %ebx,%esi\njge 1229 \nsub $0x1,%ebx\ncmp %esi,%ebx\njg 11f8 \njmp 1214 \nadd $0x1,%r13\ncmp %r13d,%ebx\njle 1255 \nmov (%r11,%r13,4),%r9d\nlea (%r9,%r13,1),%esi\ncmp %ebx,%esi\njge 1229 \nlea -0x2(%rbx),%r8d\nsub %esi,%r8d\nmovslq %r9d,%r10\nsub $0x1,%r10\nmovslq %esi,%rdi\nlea -0x1(%r9),%ebp\njmp 1220 \nmov %ebx,(%r14)\nmov %r11,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov ebx, edi\nmov r14, rsi\nmovsxd rbp, edi\nlea rdi, ds:0[rbp*4]; size\ncall _malloc\nmov r11, rax\ntest ebx, ebx\njle loc_1259\nmov eax, 1\nloc_11DA:\nmov [r11+rax*4-4], eax\nmov rdx, rax\nadd rax, 1\ncmp rbp, rdx\njnz short loc_11DA\ncmp ebx, 1\njle short loc_1259\nmov r13d, 1\nlea r12, [r11+4]\njmp short loc_1236\nloc_11FC:\nlea rax, [r11+rdi*4]\nmov edx, r8d\nadd rdx, rdi\nlea rcx, [r12+rdx*4]\nloc_120A:\nmov edx, [rax+4]\nmov [rax], edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_120A\nloc_1218:\nadd esi, ebp\nsub r8d, r9d\nadd rdi, r10\ncmp esi, ebx\njge short loc_122D\nloc_1224:\nsub ebx, 1\ncmp ebx, esi\njg short loc_11FC\njmp short loc_1218\nloc_122D:\nadd r13, 1\ncmp ebx, r13d\njle short loc_1259\nloc_1236:\nmov r9d, [r11+r13*4]\nlea esi, [r9+r13]\ncmp esi, ebx\njge short loc_122D\nlea r8d, [rbx-2]\nsub r8d, esi\nmovsxd r10, r9d\nsub r10, 1\nmovsxd rdi, esi\nlea ebp, [r9-1]\njmp short loc_1224\nloc_1259:\nmov [r14], ebx\nmov rax, r11\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int a1, int *a2)\n{\n int v2; // ebx\n _DWORD *v4; // r11\n __int64 v5; // rax\n __int64 v6; // rdx\n __int64 v7; // r13\n _DWORD *v8; // rax\n int v9; // esi\n unsigned int v10; // r8d\n __int64 v11; // rdi\n int v12; // r9d\n\n v2 = a1;\n v4 = malloc(4LL * a1);\n if ( a1 > 0 )\n {\n v5 = 1LL;\n do\n {\n v4[v5 - 1] = v5;\n v6 = v5++;\n }\n while ( a1 != v6 );\n if ( a1 > 1 )\n {\n v7 = 1LL;\n do\n {\n v12 = v4[v7];\n v9 = v12 + v7;\n if ( v12 + (int)v7 < v2 )\n {\n v10 = v2 - 2 - v9;\n v11 = v9;\n do\n {\n if ( --v2 > v9 )\n {\n v8 = &v4[v11];\n do\n {\n *v8 = v8[1];\n ++v8;\n }\n while ( v8 != &v4[v11 + 1 + v10] );\n }\n v9 += v12 - 1;\n v10 -= v12;\n v11 += v12 - 1LL;\n }\n while ( v9 < v2 );\n }\n ++v7;\n }\n while ( v2 > (int)v7 );\n }\n }\n *a2 = v2;\n return v4;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov ebx, edi\nmov r14, rsi\nmovsxd rbp, edi\nlea rdi, ds:0[rbp*4]; size\ncall _malloc\nmov r11, rax\ntest ebx, ebx\njle loc_1259\nmov eax, 1\nloc_11DA:\nmov [r11+rax*4-4], eax\nmov rdx, rax\nadd rax, 1\ncmp rbp, rdx\njnz short loc_11DA\ncmp ebx, 1\njle short loc_1259\nmov r13d, 1\nlea r12, [r11+4]\njmp short loc_1236\nloc_11FC:\nlea rax, [r11+rdi*4]\nmov edx, r8d\nadd rdx, rdi\nlea rcx, [r12+rdx*4]\nloc_120A:\nmov edx, [rax+4]\nmov [rax], edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_120A\nloc_1218:\nadd esi, ebp\nsub r8d, r9d\nadd rdi, r10\ncmp esi, ebx\njge short loc_122D\nloc_1224:\nsub ebx, 1\ncmp ebx, esi\njg short loc_11FC\njmp short loc_1218\nloc_122D:\nadd r13, 1\ncmp ebx, r13d\njle short loc_1259\nloc_1236:\nmov r9d, [r11+r13*4]\nlea esi, [r9+r13]\ncmp esi, ebx\njge short loc_122D\nlea r8d, [rbx-2]\nsub r8d, esi\nmovsxd r10, r9d\nsub r10, 1\nmovsxd rdi, esi\nlea ebp, [r9-1]\njmp short loc_1224\nloc_1259:\nmov [r14], ebx\nmov rax, r11\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(int a1, int *a2)\n{\n int v2; // ebx\n _DWORD *v4; // r11\n __int64 v5; // rax\n __int64 v6; // rdx\n __int64 v7; // r13\n _DWORD *v8; // rax\n int v9; // esi\n unsigned int v10; // r8d\n __int64 v11; // rdi\n int v12; // r9d\n\n v2 = a1;\n v4 = malloc(4LL * a1);\n if ( a1 > 0 )\n {\n v5 = 1LL;\n do\n {\n v4[v5 - 1] = v5;\n v6 = v5++;\n }\n while ( a1 != v6 );\n if ( a1 > 1 )\n {\n v7 = 1LL;\n do\n {\n v12 = v4[v7];\n v9 = v12 + v7;\n if ( v12 + (int)v7 < v2 )\n {\n v10 = v2 - 2 - v9;\n v11 = v9;\n do\n {\n if ( --v2 > v9 )\n {\n v8 = &v4[v11];\n do\n {\n *v8 = v8[1];\n ++v8;\n }\n while ( v8 != &v4[v11 + 1 + v10] );\n }\n v9 += v12 - 1;\n v10 -= v12;\n v11 += v12 - 1LL;\n }\n while ( v9 < v2 );\n }\n ++v7;\n }\n while ( v2 > (int)v7 );\n }\n }\n *a2 = v2;\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(int a1, int *a2) {\n int v2;\n uint32_t *v4;\n long long v5;\n long long v6;\n long long v7;\n uint32_t *v8;\n int v9;\n unsigned int v10;\n long long v11;\n int v12;\n v2 = a1;\n v4 = malloc(4LL * a1);\n if (a1 > 0) {\n v5 = 1LL;\n do {\n v4[v5 - 1] = v5;\n v6 = v5++;\n } while (a1 != v6);\n if (a1 > 1) {\n v7 = 1LL;\n do {\n v12 = v4[v7];\n v9 = v12 + v7;\n if (v12 + (int)v7 < v2) {\n v10 = v2 - 2 - v9;\n v11 = v9;\n do {\n if (--v2 > v9) {\n v8 = &v4[v11];\n do {\n *v8 = v8[1];\n ++v8;\n } while (v8 != &v4[v11 + 1 + v10]);\n }\n v9 += v12 - 1;\n v10 -= v12;\n v11 += v12 - 1LL;\n } while (v9 < v2);\n }\n ++v7;\n } while (v2 > (int)v7);\n }\n }\n *a2 = v2;\n return v4;\n}", + "ida_pseudo_norm": "uint32_t *func0(int a1, int *a2) {\n int v2;\n uint32_t *v4;\n long long v5;\n long long v6;\n long long v7;\n uint32_t *v8;\n int v9;\n unsigned int v10;\n long long v11;\n int v12;\n v2 = a1;\n v4 = malloc(4LL * a1);\n if (a1 > 0) {\n v5 = 1LL;\n do {\n v4[v5 - 1] = v5;\n v6 = v5++;\n } while (a1 != v6);\n if (a1 > 1) {\n v7 = 1LL;\n do {\n v12 = v4[v7];\n v9 = v12 + v7;\n if (v12 + (int)v7 < v2) {\n v10 = v2 - 2 - v9;\n v11 = v9;\n do {\n if (--v2 > v9) {\n v8 = &v4[v11];\n do {\n *v8 = v8[1];\n ++v8;\n } while (v8 != &v4[v11 + 1 + v10]);\n }\n v9 += v12 - 1;\n v10 -= v12;\n v11 += v12 - 1LL;\n } while (v9 < v2);\n }\n ++v7;\n } while (v2 > (int)v7);\n }\n }\n *a2 = v2;\n return v4;\n}" + }, + { + "index": 603, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int n, int* ludic_size) {\n int* ludics = (int*)malloc(sizeof(int) * n);\n for (int i = 0; i < n; i++) {\n ludics[i] = i + 1;\n }\n int current_size = n;\n int index = 1;\n while (index < current_size) {\n int first_ludic = ludics[index];\n int remove_index = index + first_ludic;\n while (remove_index < current_size) {\n for (int j = remove_index; j < current_size - 1; j++) {\n ludics[j] = ludics[j + 1];\n }\n current_size -= 1;\n remove_index += first_ludic - 1;\n }\n index += 1;\n }\n *ludic_size = current_size;\n return ludics;\n}", + "test": "int main() {\n\n int size;\n\n int* result;\n\n\n\n result = func0(10, &size);\n\n assert(size == 5 && result[0] == 1 && result[1] == 2 && result[2] == 3 && result[3] == 5 && result[4] == 7);\n\n free(result);\n\n\n\n result = func0(25, &size);\n\n assert(size == 10 && result[0] == 1 && result[1] == 2 && result[2] == 3 && result[3] == 5 && result[4] == 7 && result[5] == 11 && result[6] == 13 && result[7] == 17 && result[8] == 23 && result[9] == 25);\n\n free(result);\n\n\n\n result = func0(45, &size);\n\n assert(size == 14 && result[0] == 1 && result[1] == 2 && result[2] == 3 && result[3] == 5 && result[4] == 7 && result[5] == 11 && result[6] == 13 && result[7] == 17 && result[8] == 23 && result[9] == 25 && result[10] == 29 && result[11] == 37 && result[12] == 41 && result[13] == 43);\n\n free(result);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\nmovslq %edi,%rdi\npush %r13\npush %r12\nmov %rsi,%r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nshl $0x2,%rdi\ncallq 10b0 \nmov %rax,%r11\ntest %ebx,%ebx\njle 1445 \nlea -0x1(%rbx),%edx\nmov $0x1,%eax\nadd $0x2,%rdx\nnopl (%rax)\nmov %eax,-0x4(%r11,%rax,4)\nadd $0x1,%rax\ncmp %rdx,%rax\njne 13c8 \ncmp $0x1,%ebx\njle 1445 \nmov $0x1,%r14d\nlea 0x4(%r11),%r13\nnopl (%rax)\nmov (%r11,%r14,4),%r9d\nlea (%r9,%r14,1),%esi\ncmp %ebx,%esi\njge 143c \nlea -0x1(%r9),%r10d\nlea -0x2(%rbx),%r8d\nmovslq %esi,%rdi\nsub %esi,%r8d\nmovslq %r10d,%rbp\nnopl (%rax)\nsub $0x1,%ebx\ncmp %esi,%ebx\njle 142f \nmov %r8d,%edx\nlea (%r11,%rdi,4),%rax\nadd %rdi,%rdx\nlea 0x0(%r13,%rdx,4),%rcx\nxchg %ax,%ax\nmov 0x4(%rax),%edx\nadd $0x4,%rax\nmov %edx,-0x4(%rax)\ncmp %rax,%rcx\njne 1420 \nadd %r10d,%esi\nsub %r9d,%r8d\nadd %rbp,%rdi\ncmp %ebx,%esi\njl 1408 \nadd $0x1,%r14\ncmp %r14d,%ebx\njg 13e8 \nmov %ebx,(%r12)\nmov %r11,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmovsxd rbx, edi\nlea rdi, ds:0[rbx*4]; size\nmov r14, rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rsi\ncall _malloc\nmov [rsp+48h+var_48], rax\ntest ebx, ebx\njle loc_147C\nmov eax, 1\nnop dword ptr [rax+rax+00h]\nloc_13F0:\nmov rdi, [rsp+48h+var_48]\nmov rdx, rax\nmov [rdi+rax*4-4], eax\nadd rax, 1\ncmp rbx, rdx\njnz short loc_13F0\ncmp r14d, 1\njz short loc_147C\nmov r12d, 1\nloc_1410:\nmov rdi, [rsp+48h+var_48]\nmov r9d, [rdi+r12*4]\nlea r15d, [r9+r12]\ncmp r15d, r14d\njge short loc_1473\nlea r13d, [r9-1]\nlea ebx, [r14-2]\nmovsxd rax, r15d\nmovsxd rbp, r13d\nsub ebx, r15d\nlea rcx, [rdi+rax*4]\nshl rbp, 2\nnop word ptr [rax+rax+00h]\nloc_1440:\nsub r14d, 1\ncmp r14d, r15d\njle short loc_1462\nmov eax, ebx\nlea rsi, [rcx+4]; src\nmov rdi, rcx; dest\nlea rdx, ds:4[rax*4]; n\ncall _memmove\nmov rcx, rax\nloc_1462:\nsub ebx, r13d\nadd r15d, r13d\nadd rcx, rbp\nsub ebx, 1\ncmp r15d, r14d\njl short loc_1440\nloc_1473:\nadd r12, 1\ncmp r14d, r12d\njg short loc_1410\nloc_147C:\nmov rax, [rsp+48h+var_40]\nmov [rax], r14d\nmov rax, [rsp+48h+var_48]\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int a1, int *a2)\n{\n int v2; // r14d\n __int64 v3; // rax\n __int64 v4; // rdx\n __int64 v5; // r12\n int v6; // r9d\n int v7; // r15d\n int v8; // r13d\n unsigned int v9; // ebx\n char *v10; // rcx\n __int64 v11; // rbp\n _DWORD *v13; // [rsp+0h] [rbp-48h]\n\n v2 = a1;\n v13 = malloc(4LL * a1);\n if ( a1 > 0 )\n {\n v3 = 1LL;\n do\n {\n v4 = v3;\n v13[v3 - 1] = v3;\n ++v3;\n }\n while ( a1 != v4 );\n if ( a1 != 1 )\n {\n v5 = 1LL;\n do\n {\n v6 = v13[v5];\n v7 = v6 + v5;\n if ( v6 + (int)v5 < v2 )\n {\n v8 = v6 - 1;\n v9 = v2 - 2 - v7;\n v10 = (char *)&v13[v7];\n v11 = 4LL * (v6 - 1);\n do\n {\n if ( --v2 > v7 )\n v10 = (char *)memmove(v10, v10 + 4, 4LL * v9 + 4);\n v7 += v8;\n v10 += v11;\n v9 = v9 - v8 - 1;\n }\n while ( v7 < v2 );\n }\n ++v5;\n }\n while ( v2 > (int)v5 );\n }\n }\n *a2 = v2;\n return v13;\n}", + "ida_strip_asm": "sub_13B0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmovsxd rbx, edi\nlea rdi, ds:0[rbx*4]; size\nmov r14, rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rsi\ncall _malloc\nmov [rsp+48h+var_48], rax\ntest ebx, ebx\njle loc_147C\nmov eax, 1\nnop dword ptr [rax+rax+00h]\nloc_13F0:\nmov rdi, [rsp+48h+var_48]\nmov rdx, rax\nmov [rdi+rax*4-4], eax\nadd rax, 1\ncmp rbx, rdx\njnz short loc_13F0\ncmp r14d, 1\njz short loc_147C\nmov r12d, 1\nloc_1410:\nmov rdi, [rsp+48h+var_48]\nmov r9d, [rdi+r12*4]\nlea r15d, [r9+r12]\ncmp r15d, r14d\njge short loc_1473\nlea r13d, [r9-1]\nlea ebx, [r14-2]\nmovsxd rax, r15d\nmovsxd rbp, r13d\nsub ebx, r15d\nlea rcx, [rdi+rax*4]\nshl rbp, 2\nnop word ptr [rax+rax+00h]\nloc_1440:\nsub r14d, 1\ncmp r14d, r15d\njle short loc_1462\nmov eax, ebx\nlea rsi, [rcx+4]; src\nmov rdi, rcx; dest\nlea rdx, ds:4[rax*4]; n\ncall _memmove\nmov rcx, rax\nloc_1462:\nsub ebx, r13d\nadd r15d, r13d\nadd rcx, rbp\nsub ebx, 1\ncmp r15d, r14d\njl short loc_1440\nloc_1473:\nadd r12, 1\ncmp r14d, r12d\njg short loc_1410\nloc_147C:\nmov rax, [rsp+48h+var_40]\nmov [rax], r14d\nmov rax, [rsp+48h+var_48]\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_13B0(int a1, int *a2)\n{\n int v2; // r14d\n __int64 v3; // rax\n __int64 v4; // rdx\n __int64 v5; // r12\n int v6; // r9d\n int v7; // r15d\n int v8; // r13d\n unsigned int v9; // ebx\n char *v10; // rcx\n __int64 v11; // rbp\n _DWORD *v13; // [rsp+0h] [rbp-48h]\n\n v2 = a1;\n v13 = malloc(4LL * a1);\n if ( a1 > 0 )\n {\n v3 = 1LL;\n do\n {\n v4 = v3;\n v13[v3 - 1] = v3;\n ++v3;\n }\n while ( a1 != v4 );\n if ( a1 != 1 )\n {\n v5 = 1LL;\n do\n {\n v6 = v13[v5];\n v7 = v6 + v5;\n if ( v6 + (int)v5 < v2 )\n {\n v8 = v6 - 1;\n v9 = v2 - 2 - v7;\n v10 = (char *)&v13[v7];\n v11 = 4LL * (v6 - 1);\n do\n {\n if ( --v2 > v7 )\n v10 = (char *)memmove(v10, v10 + 4, 4LL * v9 + 4);\n v7 += v8;\n v10 += v11;\n v9 = v9 - v8 - 1;\n }\n while ( v7 < v2 );\n }\n ++v5;\n }\n while ( v2 > (int)v5 );\n }\n }\n *a2 = v2;\n return v13;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_13B0(int a1, int *a2) {\n int v2;\n long long v3;\n long long v4;\n long long v5;\n int v6;\n int v7;\n int v8;\n unsigned int v9;\n char *v10;\n long long v11;\n uint32_t *v13;\n v2 = a1;\n v13 = malloc(4LL * a1);\n if (a1 > 0) {\n v3 = 1LL;\n do {\n v4 = v3;\n v13[v3 - 1] = v3;\n ++v3;\n } while (a1 != v4);\n if (a1 != 1) {\n v5 = 1LL;\n do {\n v6 = v13[v5];\n v7 = v6 + v5;\n if (v6 + (int)v5 < v2) {\n v8 = v6 - 1;\n v9 = v2 - 2 - v7;\n v10 = (char *)&v13[v7];\n v11 = 4LL * (v6 - 1);\n do {\n if (--v2 > v7) v10 = (char *)memmove(v10, v10 + 4, 4LL * v9 + 4);\n v7 += v8;\n v10 += v11;\n v9 = v9 - v8 - 1;\n } while (v7 < v2);\n }\n ++v5;\n } while (v2 > (int)v5);\n }\n }\n *a2 = v2;\n return v13;\n}", + "ida_pseudo_norm": "uint32_t *func0(int a1, int *a2) {\n int v2;\n long long v3;\n long long v4;\n long long v5;\n int v6;\n int v7;\n int v8;\n unsigned int v9;\n char *v10;\n long long v11;\n uint32_t *v13;\n v2 = a1;\n v13 = malloc(4LL * a1);\n if (a1 > 0) {\n v3 = 1LL;\n do {\n v4 = v3;\n v13[v3 - 1] = v3;\n ++v3;\n } while (a1 != v4);\n if (a1 != 1) {\n v5 = 1LL;\n do {\n v6 = v13[v5];\n v7 = v6 + v5;\n if (v6 + (int)v5 < v2) {\n v8 = v6 - 1;\n v9 = v2 - 2 - v7;\n v10 = (char *)&v13[v7];\n v11 = 4LL * (v6 - 1);\n do {\n if (--v2 > v7) v10 = (char *)memmove(v10, v10 + 4, 4LL * v9 + 4);\n v7 += v8;\n v10 += v11;\n v9 = v9 - v8 - 1;\n } while (v7 < v2);\n }\n ++v5;\n } while (v2 > (int)v5);\n }\n }\n *a2 = v2;\n return v13;\n}" + }, + { + "index": 603, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int n, int* ludic_size) {\n int* ludics = (int*)malloc(sizeof(int) * n);\n for (int i = 0; i < n; i++) {\n ludics[i] = i + 1;\n }\n int current_size = n;\n int index = 1;\n while (index < current_size) {\n int first_ludic = ludics[index];\n int remove_index = index + first_ludic;\n while (remove_index < current_size) {\n for (int j = remove_index; j < current_size - 1; j++) {\n ludics[j] = ludics[j + 1];\n }\n current_size -= 1;\n remove_index += first_ludic - 1;\n }\n index += 1;\n }\n *ludic_size = current_size;\n return ludics;\n}", + "test": "int main() {\n\n int size;\n\n int* result;\n\n\n\n result = func0(10, &size);\n\n assert(size == 5 && result[0] == 1 && result[1] == 2 && result[2] == 3 && result[3] == 5 && result[4] == 7);\n\n free(result);\n\n\n\n result = func0(25, &size);\n\n assert(size == 10 && result[0] == 1 && result[1] == 2 && result[2] == 3 && result[3] == 5 && result[4] == 7 && result[5] == 11 && result[6] == 13 && result[7] == 17 && result[8] == 23 && result[9] == 25);\n\n free(result);\n\n\n\n result = func0(45, &size);\n\n assert(size == 14 && result[0] == 1 && result[1] == 2 && result[2] == 3 && result[3] == 5 && result[4] == 7 && result[5] == 11 && result[6] == 13 && result[7] == 17 && result[8] == 23 && result[9] == 25 && result[10] == 29 && result[11] == 37 && result[12] == 41 && result[13] == 43);\n\n free(result);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmovslq %edi,%rdi\npush %r14\nmov %rdi,%r15\nshl $0x2,%rdi\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x28,%rsp\nmov %rsi,0x18(%rsp)\ncallq 10c0 \nmov %rax,0x10(%rsp)\ntest %r15d,%r15d\njle 14f6 \nmov %rax,%rcx\nlea -0x1(%r15),%eax\ncmp $0x2,%eax\njbe 1512 \nmov %r15d,%edx\nmovdqa 0xea1(%rip),%xmm1\nmov %rcx,%rax\nmovdqa 0xea6(%rip),%xmm3\nshr $0x2,%edx\nmovdqa 0xeab(%rip),%xmm2\nshl $0x4,%rdx\nadd %rcx,%rdx\nmovdqa %xmm1,%xmm0\nadd $0x10,%rax\npaddd %xmm3,%xmm1\npaddd %xmm2,%xmm0\nmovups %xmm0,-0x10(%rax)\ncmp %rdx,%rax\njne 141c \nmov %r15d,%eax\nand $0xfffffffc,%eax\ntest $0x3,%r15b\nje 146f \nmov 0x10(%rsp),%rcx\nlea 0x1(%rax),%esi\nmovslq %eax,%rdx\nmov %esi,(%rcx,%rdx,4)\ncmp %esi,%r15d\njle 1519 \nlea 0x2(%rax),%edx\nmovslq %esi,%rsi\nmov %edx,(%rcx,%rsi,4)\ncmp %edx,%r15d\njle 146f \nmovslq %edx,%rdx\nadd $0x3,%eax\nmov %eax,(%rcx,%rdx,4)\nmovq $0x1,0x8(%rsp)\nnopl 0x0(%rax,%rax,1)\nmov 0x8(%rsp),%rax\nmov 0x10(%rsp),%rcx\nmov (%rcx,%rax,4),%ebx\nlea (%rbx,%rax,1),%r14d\ncmp %r15d,%r14d\njge 14e6 \nlea -0x1(%rbx),%r12d\nlea -0x2(%r15),%r9d\nmovslq %r14d,%rax\nsub %r14d,%r9d\nmovslq %r12d,%rbp\nlea (%rcx,%rax,4),%rdi\nmov %r9d,%r13d\nshl $0x2,%rbp\nnopw 0x0(%rax,%rax,1)\nsub $0x1,%r15d\ncmp %r14d,%r15d\njle 14d8 \nmov %r13d,%eax\nlea 0x4(%rdi),%rsi\nlea 0x4(,%rax,4),%rdx\ncallq 10d0 \nmov %rax,%rdi\nadd %r12d,%r14d\nsub %ebx,%r13d\nadd %rbp,%rdi\ncmp %r15d,%r14d\njl 14b8 \naddq $0x1,0x8(%rsp)\nmov 0x8(%rsp),%rax\ncmp %eax,%r15d\njg 1480 \nmov 0x18(%rsp),%rax\nmov %r15d,(%rax)\nmov 0x10(%rsp),%rax\nadd $0x28,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nxor %eax,%eax\njmpq 1441 \ncmp $0x1,%r15d\njg 146f \njmp 14f6 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmovsxd rdi, edi\npush r14\nmov r15, rdi\nshl rdi, 2; size\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rsi\ncall _malloc\nmov [rsp+48h+var_48], rax\ntest r15d, r15d\njle loc_14EC\nlea eax, [r15-1]\ncmp eax, 2\njbe loc_1507\nmov edx, r15d\nmov rdi, [rsp+48h+var_48]\nmovdqa xmm1, cs:xmmword_2280\nshr edx, 2\nmovdqa xmm3, cs:xmmword_2290\nmovdqa xmm2, cs:xmmword_22A0\nshl rdx, 4\nmov rax, rdi\nadd rdx, rdi\nloc_141C:\nmovdqa xmm0, xmm1\nadd rax, 10h\npaddd xmm1, xmm3\npaddd xmm0, xmm2\nmovups xmmword ptr [rax-10h], xmm0\ncmp rax, rdx\njnz short loc_141C\nmov eax, r15d\nand eax, 0FFFFFFFCh\ntest r15b, 3\njz short loc_1471\nmov rdi, [rsp+48h+var_48]\nmov esi, eax\nlea ecx, [rax+1]\nlea rdx, ds:0[rsi*4]\nmov [rdi+rsi*4], ecx\ncmp r15d, ecx\njle short loc_1471\nloc_145A:\nmov rdi, [rsp+48h+var_48]\nlea ecx, [rax+2]\nmov [rdi+rdx+4], ecx\ncmp ecx, r15d\njge short loc_1471\nadd eax, 3\nmov [rdi+rdx+8], eax\nloc_1471:\nmov r12d, 1\nnop word ptr [rax+rax+00000000h]\nloc_1480:\nmov rdi, [rsp+48h+var_48]\nmov r9d, [rdi+r12*4]\nlea r14d, [r9+r12]\ncmp r14d, r15d\njge short loc_14E3\nlea r13d, [r9-1]\nlea ebx, [r15-2]\nmovsxd rax, r14d\nmovsxd rbp, r13d\nsub ebx, r14d\nlea rcx, [rdi+rax*4]\nshl rbp, 2\nnop word ptr [rax+rax+00h]\nloc_14B0:\nsub r15d, 1\ncmp r15d, r14d\njle short loc_14D2\nmov eax, ebx\nlea rsi, [rcx+4]; src\nmov rdi, rcx; dest\nlea rdx, ds:4[rax*4]; n\ncall _memmove\nmov rcx, rax\nloc_14D2:\nsub ebx, r13d\nadd r14d, r13d\nadd rcx, rbp\nsub ebx, 1\ncmp r14d, r15d\njl short loc_14B0\nloc_14E3:\nadd r12, 1\ncmp r15d, r12d\njg short loc_1480\nloc_14EC:\nmov rax, [rsp+48h+var_40]\nmov [rax], r15d\nmov rax, [rsp+48h+var_48]\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1507:\nmov rax, [rsp+48h+var_48]\nxor edx, edx\nmov dword ptr [rax], 1\nxor eax, eax\ncmp r15d, 1\njnz loc_145A\njmp short loc_14EC", + "ida_pseudo": "__m128i *__fastcall func0(int a1, int *a2)\n{\n int v2; // r15d\n __m128i si128; // xmm1\n __m128i v4; // xmm3\n __m128i v5; // xmm2\n __m128i *v6; // rax\n __m128i v7; // xmm0\n unsigned int v8; // eax\n __int64 v9; // rdx\n __int64 v10; // r12\n int v11; // r9d\n int v12; // r14d\n int v13; // r13d\n unsigned int v14; // ebx\n char *v15; // rcx\n __int64 v16; // rbp\n __m128i *v18; // [rsp+0h] [rbp-48h]\n\n v2 = a1;\n v18 = (__m128i *)malloc(4LL * a1);\n if ( a1 <= 0 )\n goto LABEL_16;\n if ( (unsigned int)(a1 - 1) <= 2 )\n {\n v9 = 0LL;\n v18->m128i_i32[0] = 1;\n v8 = 0;\n if ( a1 == 1 )\n goto LABEL_16;\n goto LABEL_7;\n }\n si128 = _mm_load_si128((const __m128i *)&xmmword_2280);\n v4 = _mm_load_si128((const __m128i *)&xmmword_2290);\n v5 = _mm_load_si128((const __m128i *)&xmmword_22A0);\n v6 = v18;\n do\n {\n v7 = si128;\n ++v6;\n si128 = _mm_add_epi32(si128, v4);\n v6[-1] = _mm_add_epi32(v7, v5);\n }\n while ( v6 != &v18[(unsigned int)a1 >> 2] );\n v8 = a1 & 0x7FFFFFFC;\n if ( (a1 & 3) != 0 )\n {\n v9 = v8;\n v18->m128i_i32[v9] = v8 + 1;\n if ( a1 > (int)(v8 + 1) )\n {\nLABEL_7:\n v18->m128i_i32[v9 + 1] = v8 + 2;\n if ( (int)(v8 + 2) < a1 )\n v18->m128i_i32[v9 + 2] = v8 + 3;\n }\n }\n v10 = 1LL;\n do\n {\n v11 = v18->m128i_i32[v10];\n v12 = v11 + v10;\n if ( v11 + (int)v10 < v2 )\n {\n v13 = v11 - 1;\n v14 = v2 - 2 - v12;\n v15 = &v18->m128i_i8[4 * v12];\n v16 = 4LL * (v11 - 1);\n do\n {\n if ( --v2 > v12 )\n v15 = (char *)memmove(v15, v15 + 4, 4LL * v14 + 4);\n v12 += v13;\n v15 += v16;\n v14 = v14 - v13 - 1;\n }\n while ( v12 < v2 );\n }\n ++v10;\n }\n while ( v2 > (int)v10 );\nLABEL_16:\n *a2 = v2;\n return v18;\n}", + "ida_strip_asm": "sub_13B0:\nendbr64\npush r15\nmovsxd rdi, edi\npush r14\nmov r15, rdi\nshl rdi, 2; size\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rsi\ncall _malloc\nmov [rsp+48h+var_48], rax\ntest r15d, r15d\njle loc_14EC\nlea eax, [r15-1]\ncmp eax, 2\njbe loc_1507\nmov edx, r15d\nmov rdi, [rsp+48h+var_48]\nmovdqa xmm1, cs:xmmword_2280\nshr edx, 2\nmovdqa xmm3, cs:xmmword_2290\nmovdqa xmm2, cs:xmmword_22A0\nshl rdx, 4\nmov rax, rdi\nadd rdx, rdi\nloc_141C:\nmovdqa xmm0, xmm1\nadd rax, 10h\npaddd xmm1, xmm3\npaddd xmm0, xmm2\nmovups xmmword ptr [rax-10h], xmm0\ncmp rax, rdx\njnz short loc_141C\nmov eax, r15d\nand eax, 0FFFFFFFCh\ntest r15b, 3\njz short loc_1471\nmov rdi, [rsp+48h+var_48]\nmov esi, eax\nlea ecx, [rax+1]\nlea rdx, ds:0[rsi*4]\nmov [rdi+rsi*4], ecx\ncmp r15d, ecx\njle short loc_1471\nloc_145A:\nmov rdi, [rsp+48h+var_48]\nlea ecx, [rax+2]\nmov [rdi+rdx+4], ecx\ncmp ecx, r15d\njge short loc_1471\nadd eax, 3\nmov [rdi+rdx+8], eax\nloc_1471:\nmov r12d, 1\nnop word ptr [rax+rax+00000000h]\nloc_1480:\nmov rdi, [rsp+48h+var_48]\nmov r9d, [rdi+r12*4]\nlea r14d, [r9+r12]\ncmp r14d, r15d\njge short loc_14E3\nlea r13d, [r9-1]\nlea ebx, [r15-2]\nmovsxd rax, r14d\nmovsxd rbp, r13d\nsub ebx, r14d\nlea rcx, [rdi+rax*4]\nshl rbp, 2\nnop word ptr [rax+rax+00h]\nloc_14B0:\nsub r15d, 1\ncmp r15d, r14d\njle short loc_14D2\nmov eax, ebx\nlea rsi, [rcx+4]; src\nmov rdi, rcx; dest\nlea rdx, ds:4[rax*4]; n\ncall _memmove\nmov rcx, rax\nloc_14D2:\nsub ebx, r13d\nadd r14d, r13d\nadd rcx, rbp\nsub ebx, 1\ncmp r14d, r15d\njl short loc_14B0\nloc_14E3:\nadd r12, 1\ncmp r15d, r12d\njg short loc_1480\nloc_14EC:\nmov rax, [rsp+48h+var_40]\nmov [rax], r15d\nmov rax, [rsp+48h+var_48]\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1507:\nmov rax, [rsp+48h+var_48]\nxor edx, edx\nmov dword ptr [rax], 1\nxor eax, eax\ncmp r15d, 1\njnz loc_145A\njmp short loc_14EC", + "ida_strip_pseudo": "__m128i *__fastcall sub_13B0(int a1, int *a2)\n{\n int v2; // r15d\n __m128i si128; // xmm1\n __m128i v4; // xmm3\n __m128i v5; // xmm2\n __m128i *v6; // rax\n __m128i v7; // xmm0\n unsigned int v8; // eax\n __int64 v9; // rdx\n __int64 v10; // r12\n int v11; // r9d\n int v12; // r14d\n int v13; // r13d\n unsigned int v14; // ebx\n char *v15; // rcx\n __int64 v16; // rbp\n __m128i *v18; // [rsp+0h] [rbp-48h]\n\n v2 = a1;\n v18 = (__m128i *)malloc(4LL * a1);\n if ( a1 <= 0 )\n goto LABEL_16;\n if ( (unsigned int)(a1 - 1) <= 2 )\n {\n v9 = 0LL;\n v18->m128i_i32[0] = 1;\n v8 = 0;\n if ( a1 == 1 )\n goto LABEL_16;\n goto LABEL_7;\n }\n si128 = _mm_load_si128((const __m128i *)&xmmword_2280);\n v4 = _mm_load_si128((const __m128i *)&xmmword_2290);\n v5 = _mm_load_si128((const __m128i *)&xmmword_22A0);\n v6 = v18;\n do\n {\n v7 = si128;\n ++v6;\n si128 = _mm_add_epi32(si128, v4);\n v6[-1] = _mm_add_epi32(v7, v5);\n }\n while ( v6 != &v18[(unsigned int)a1 >> 2] );\n v8 = a1 & 0x7FFFFFFC;\n if ( (a1 & 3) != 0 )\n {\n v9 = v8;\n v18->m128i_i32[v9] = v8 + 1;\n if ( a1 > (int)(v8 + 1) )\n {\nLABEL_7:\n v18->m128i_i32[v9 + 1] = v8 + 2;\n if ( (int)(v8 + 2) < a1 )\n v18->m128i_i32[v9 + 2] = v8 + 3;\n }\n }\n v10 = 1LL;\n do\n {\n v11 = v18->m128i_i32[v10];\n v12 = v11 + v10;\n if ( v11 + (int)v10 < v2 )\n {\n v13 = v11 - 1;\n v14 = v2 - 2 - v12;\n v15 = &v18->m128i_i8[4 * v12];\n v16 = 4LL * (v11 - 1);\n do\n {\n if ( --v2 > v12 )\n v15 = (char *)memmove(v15, v15 + 4, 4LL * v14 + 4);\n v12 += v13;\n v15 += v16;\n v14 = v14 - v13 - 1;\n }\n while ( v12 < v2 );\n }\n ++v10;\n }\n while ( v2 > (int)v10 );\nLABEL_16:\n *a2 = v2;\n return v18;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__m128i *sub_13B0(int a1, int *a2) {\n int v2;\n __m128i si128;\n __m128i v4;\n __m128i v5;\n __m128i *v6;\n __m128i v7;\n unsigned int v8;\n long long v9;\n long long v10;\n int v11;\n int v12;\n int v13;\n unsigned int v14;\n char *v15;\n long long v16;\n __m128i *v18;\n v2 = a1;\n v18 = (__m128i *)malloc(4LL * a1);\n if (a1 <= 0) goto LABEL_16;\n if ((unsigned int)(a1 - 1) <= 2) {\n v9 = 0LL;\n v18->m128i_i32[0] = 1;\n v8 = 0;\n if (a1 == 1) goto LABEL_16;\n goto LABEL_7;\n }\n si128 = _mm_load_si128((const __m128i *)&xmmword_2280);\n v4 = _mm_load_si128((const __m128i *)&xmmword_2290);\n v5 = _mm_load_si128((const __m128i *)&xmmword_22A0);\n v6 = v18;\n do {\n v7 = si128;\n ++v6;\n si128 = _mm_add_epi32(si128, v4);\n v6[-1] = _mm_add_epi32(v7, v5);\n } while (v6 != &v18[(unsigned int)a1 >> 2]);\n v8 = a1 & 2147483644;\n if ((a1 & 3) != 0) {\n v9 = v8;\n v18->m128i_i32[v9] = v8 + 1;\n if (a1 > (int)(v8 + 1)) {\n LABEL_7:\n v18->m128i_i32[v9 + 1] = v8 + 2;\n if ((int)(v8 + 2) < a1) v18->m128i_i32[v9 + 2] = v8 + 3;\n }\n }\n v10 = 1LL;\n do {\n v11 = v18->m128i_i32[v10];\n v12 = v11 + v10;\n if (v11 + (int)v10 < v2) {\n v13 = v11 - 1;\n v14 = v2 - 2 - v12;\n v15 = &v18->m128i_i8[4 * v12];\n v16 = 4LL * (v11 - 1);\n do {\n if (--v2 > v12) v15 = (char *)memmove(v15, v15 + 4, 4LL * v14 + 4);\n v12 += v13;\n v15 += v16;\n v14 = v14 - v13 - 1;\n } while (v12 < v2);\n }\n ++v10;\n } while (v2 > (int)v10);\nLABEL_16:\n *a2 = v2;\n return v18;\n}", + "ida_pseudo_norm": "__m128i *func0(int a1, int *a2) {\n int v2;\n __m128i si128;\n __m128i v4;\n __m128i v5;\n __m128i *v6;\n __m128i v7;\n unsigned int v8;\n long long v9;\n long long v10;\n int v11;\n int v12;\n int v13;\n unsigned int v14;\n char *v15;\n long long v16;\n __m128i *v18;\n v2 = a1;\n v18 = (__m128i *)malloc(4LL * a1);\n if (a1 <= 0) goto LABEL_16;\n if ((unsigned int)(a1 - 1) <= 2) {\n v9 = 0LL;\n v18->m128i_i32[0] = 1;\n v8 = 0;\n if (a1 == 1) goto LABEL_16;\n goto LABEL_7;\n }\n si128 = _mm_load_si128((const __m128i *)&xmmword_2280);\n v4 = _mm_load_si128((const __m128i *)&xmmword_2290);\n v5 = _mm_load_si128((const __m128i *)&xmmword_22A0);\n v6 = v18;\n do {\n v7 = si128;\n ++v6;\n si128 = _mm_add_epi32(si128, v4);\n v6[-1] = _mm_add_epi32(v7, v5);\n } while (v6 != &v18[(unsigned int)a1 >> 2]);\n v8 = a1 & 2147483644;\n if ((a1 & 3) != 0) {\n v9 = v8;\n v18->m128i_i32[v9] = v8 + 1;\n if (a1 > (int)(v8 + 1)) {\n LABEL_7:\n v18->m128i_i32[v9 + 1] = v8 + 2;\n if ((int)(v8 + 2) < a1) v18->m128i_i32[v9 + 2] = v8 + 3;\n }\n }\n v10 = 1LL;\n do {\n v11 = v18->m128i_i32[v10];\n v12 = v11 + v10;\n if (v11 + (int)v10 < v2) {\n v13 = v11 - 1;\n v14 = v2 - 2 - v12;\n v15 = &v18->m128i_i8[4 * v12];\n v16 = 4LL * (v11 - 1);\n do {\n if (--v2 > v12) v15 = (char *)memmove(v15, v15 + 4, 4LL * v14 + 4);\n v12 += v13;\n v15 += v16;\n v14 = v14 - v13 - 1;\n } while (v12 < v2);\n }\n ++v10;\n } while (v2 > (int)v10);\nLABEL_16:\n *a2 = v2;\n return v18;\n}" + }, + { + "index": 604, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* s) {\n static char result[100];\n int word_count = 0;\n char* words[10];\n char* token = strtok(s, \" \");\n while (token != NULL) {\n words[word_count++] = token;\n token = strtok(NULL, \" \");\n }\n result[0] = '\\0';\n for (int i = word_count - 1; i >= 0; i--) {\n strcat(result, words[i]);\n if (i > 0) {\n strcat(result, \" \");\n }\n }\n return result;\n}", + "test": "int main() {\n\n char test_string1[] = \"python program\";\n\n char test_string2[] = \"java language\";\n\n char test_string3[] = \"indian man\";\n\n \n\n assert(strcmp(func0(test_string1), \"program python\") == 0);\n\n assert(strcmp(func0(test_string2), \"language java\") == 0);\n\n assert(strcmp(func0(test_string3), \"man indian\") == 0);\n\n \n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nadd $0xffffffffffffff80,%rsp\nmov %rdi,-0x78(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovl $0x0,-0x70(%rbp)\nmov -0x78(%rbp),%rax\nlea 0xe0e(%rip),%rsi\nmov %rax,%rdi\ncallq 10c0 \nmov %rax,-0x68(%rbp)\njmp 1231 \nmov -0x70(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x70(%rbp)\ncltq\nmov -0x68(%rbp),%rdx\nmov %rdx,-0x60(%rbp,%rax,8)\nlea 0xde5(%rip),%rsi\nmov $0x0,%edi\ncallq 10c0 \nmov %rax,-0x68(%rbp)\ncmpq $0x0,-0x68(%rbp)\njne 1208 \nmovb $0x0,0x2e01(%rip)\nmov -0x70(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0x6c(%rbp)\njmp 12a1 \nmov -0x6c(%rbp),%eax\ncltq\nmov -0x60(%rbp,%rax,8),%rax\nmov %rax,%rsi\nlea 0x2de2(%rip),%rdi\ncallq 10d0 \ncmpl $0x0,-0x6c(%rbp)\njle 129d \nlea 0x2dd0(%rip),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nlea 0x2dab(%rip),%rax\nadd %rdx,%rax\nmovw $0x20,(%rax)\nsubl $0x1,-0x6c(%rbp)\ncmpl $0x0,-0x6c(%rbp)\njns 124a \nlea 0x2d92(%rip),%rax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 12c2 \ncallq 1090 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nadd rsp, 0FFFFFFFFFFFFFF80h\nmov [rbp+s], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_70], 0\nmov rax, [rbp+s]\nlea rdx, delim; \" \"\nmov rsi, rdx; delim\nmov rdi, rax; s\ncall _strtok\nmov [rbp+var_68], rax\njmp short loc_1257\nloc_122B:\nmov eax, [rbp+var_70]\nlea edx, [rax+1]\nmov [rbp+var_70], edx\ncdqe\nmov rdx, [rbp+var_68]\nmov [rbp+rax*8+src], rdx\nlea rax, delim; \" \"\nmov rsi, rax; delim\nmov edi, 0; s\ncall _strtok\nmov [rbp+var_68], rax\nloc_1257:\ncmp [rbp+var_68], 0\njnz short loc_122B\nmov cs:result_1, 0\nmov eax, [rbp+var_70]\nsub eax, 1\nmov [rbp+var_6C], eax\njmp short loc_12B7\nloc_1270:\nmov eax, [rbp+var_6C]\ncdqe\nmov rax, [rbp+rax*8+src]\nmov rsi, rax; src\nlea rax, result_1\nmov rdi, rax; dest\ncall _strcat\ncmp [rbp+var_6C], 0\njle short loc_12B3\nlea rax, result_1\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nlea rax, result_1\nadd rax, rdx\nmov word ptr [rax], 20h ; ' '\nloc_12B3:\nsub [rbp+var_6C], 1\nloc_12B7:\ncmp [rbp+var_6C], 0\njns short loc_1270\nlea rax, result_1\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12D8\ncall ___stack_chk_fail\nlocret_12D8:\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(char *a1)\n{\n int v1; // eax\n int v3; // [rsp+10h] [rbp-70h]\n __int64 j; // [rsp+14h] [rbp-6Ch]\n char *i; // [rsp+18h] [rbp-68h]\n char *src[12]; // [rsp+20h] [rbp-60h]\n\n src[11] = (char *)__readfsqword(0x28u);\n v3 = 0;\n for ( i = strtok(a1, \" \"); i; i = strtok(0LL, \" \") )\n {\n v1 = v3++;\n src[v1] = i;\n }\n result_1 = 0;\n for ( j = (unsigned int)(v3 - 1); (int)j >= 0; LODWORD(j) = j - 1 )\n {\n strcat(&result_1, src[(int)j]);\n if ( (int)j > 0 )\n *(_WORD *)(&result_1 + strlen(&result_1)) = 32;\n }\n return &result_1;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\nadd rsp, 0FFFFFFFFFFFFFF80h\nmov [rbp+s], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_70], 0\nmov rax, [rbp+s]\nlea rdx, delim; \" \"\nmov rsi, rdx; delim\nmov rdi, rax; s\ncall _strtok\nmov [rbp+var_68], rax\njmp short loc_1257\nloc_122B:\nmov eax, [rbp+var_70]\nlea edx, [rax+1]\nmov [rbp+var_70], edx\ncdqe\nmov rdx, [rbp+var_68]\nmov [rbp+rax*8+src], rdx\nlea rax, delim; \" \"\nmov rsi, rax; delim\nmov edi, 0; s\ncall _strtok\nmov [rbp+var_68], rax\nloc_1257:\ncmp [rbp+var_68], 0\njnz short loc_122B\nmov cs:s, 0\nmov eax, [rbp+var_70]\nsub eax, 1\nmov [rbp+var_6C], eax\njmp short loc_12B7\nloc_1270:\nmov eax, [rbp+var_6C]\ncdqe\nmov rax, [rbp+rax*8+src]\nmov rsi, rax; src\nlea rax, s\nmov rdi, rax; dest\ncall _strcat\ncmp [rbp+var_6C], 0\njle short loc_12B3\nlea rax, s\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nlea rax, s\nadd rax, rdx\nmov word ptr [rax], 20h ; ' '\nloc_12B3:\nsub [rbp+var_6C], 1\nloc_12B7:\ncmp [rbp+var_6C], 0\njns short loc_1270\nlea rax, s\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12D8\ncall ___stack_chk_fail\nlocret_12D8:\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11E9(char *a1)\n{\n int v1; // eax\n int v3; // [rsp+10h] [rbp-70h]\n __int64 j; // [rsp+14h] [rbp-6Ch]\n char *i; // [rsp+18h] [rbp-68h]\n char *src[12]; // [rsp+20h] [rbp-60h]\n\n src[11] = (char *)__readfsqword(0x28u);\n v3 = 0;\n for ( i = strtok(a1, \" \"); i; i = strtok(0LL, \" \") )\n {\n v1 = v3++;\n src[v1] = i;\n }\n s = 0;\n for ( j = (unsigned int)(v3 - 1); (int)j >= 0; LODWORD(j) = j - 1 )\n {\n strcat(&s, src[(int)j]);\n if ( (int)j > 0 )\n *(_WORD *)(&s + strlen(&s)) = 32;\n }\n return &s;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11E9(char *a1) {\n int v1;\n int v3;\n long long j;\n char *i;\n char *src[12];\n src[11] = (char *)__readfsqword(40u);\n v3 = 0;\n for (i = strtok(a1, \" \"); i; i = strtok(0LL, \" \")) {\n v1 = v3++;\n src[v1] = i;\n }\n s = 0;\n for (j = (unsigned int)(v3 - 1); (int)j >= 0; LODWORD(j) = j - 1) {\n strcat(&s, src[(int)j]);\n if ((int)j > 0) *(unsigned short *)(&s + strlen(&s)) = 32;\n }\n return &s;\n}", + "ida_pseudo_norm": "char *func0(char *a1) {\n int v1;\n int v3;\n long long j;\n char *i;\n char *src[12];\n src[11] = (char *)__readfsqword(40u);\n v3 = 0;\n for (i = strtok(a1, \" \"); i; i = strtok(0LL, \" \")) {\n v1 = v3++;\n src[v1] = i;\n }\n result_1 = 0;\n for (j = (unsigned int)(v3 - 1); (int)j >= 0; LODWORD(j) = j - 1) {\n strcat(&result_1, src[(int)j]);\n if ((int)j > 0) *(unsigned short *)(&result_1 + strlen(&result_1)) = 32;\n }\n return &result_1;\n}" + }, + { + "index": 604, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* s) {\n static char result[100];\n int word_count = 0;\n char* words[10];\n char* token = strtok(s, \" \");\n while (token != NULL) {\n words[word_count++] = token;\n token = strtok(NULL, \" \");\n }\n result[0] = '\\0';\n for (int i = word_count - 1; i >= 0; i--) {\n strcat(result, words[i]);\n if (i > 0) {\n strcat(result, \" \");\n }\n }\n return result;\n}", + "test": "int main() {\n\n char test_string1[] = \"python program\";\n\n char test_string2[] = \"java language\";\n\n char test_string3[] = \"indian man\";\n\n \n\n assert(strcmp(func0(test_string1), \"program python\") == 0);\n\n assert(strcmp(func0(test_string2), \"language java\") == 0);\n\n assert(strcmp(func0(test_string3), \"man indian\") == 0);\n\n \n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nsub $0x60,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x58(%rsp)\nxor %eax,%eax\nlea 0xe38(%rip),%rsi\ncallq 10b0 \ntest %rax,%rax\nje 1279 \nmov $0x0,%ebx\nlea 0xe1e(%rip),%r12\nmov %ebx,%ebp\nmov %rax,(%rsp,%rbx,8)\nmov %r12,%rsi\nmov $0x0,%edi\ncallq 10b0 \nmov %rbx,%rdx\nadd $0x1,%rbx\ntest %rax,%rax\njne 11e6 \nmovb $0x0,0x2e34(%rip)\ntest %ebp,%ebp\njs 1259 \nmovslq %ebp,%rbp\nlea (%rsp,%rbp,8),%rbp\nmov %edx,%ebx\nlea 0x2e20(%rip),%r12\njmp 123d \nmov $0x64,%edx\nlea 0xdd6(%rip),%rsi\nmov %r12,%rdi\ncallq 1080 <__strcat_chk@plt>\nsub $0x8,%rbp\nsub $0x1,%ebx\nmov $0x64,%edx\nmov 0x0(%rbp),%rsi\nmov %r12,%rdi\ncallq 1080 <__strcat_chk@plt>\ntest %ebx,%ebx\njg 1222 \nmov %ebx,%eax\nsub $0x1,%eax\njns 1236 \nmov 0x58(%rsp),%rax\nxor %fs:0x28,%rax\njne 1282 \nlea 0x2dd0(%rip),%rax\nadd $0x60,%rsp\npop %rbx\npop %rbp\npop %r12\nretq\nmovb $0x0,0x2dc0(%rip)\njmp 1259 \ncallq 1090 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 60h\nmov rax, fs:28h\nmov [rsp+88h+var_30], rax\nxor eax, eax\nlea rsi, delim; \" \"\ncall _strtok\ntest rax, rax\njz loc_12B3\nmov ebx, 0\nlea rbp, delim; \" \"\nloc_120A:\nmov [rsp+rbx*8+88h+var_88], rax\nmov rsi, rbp; delim\nmov edi, 0; s\ncall _strtok\nmov rdx, rbx\nadd rbx, 1\ntest rax, rax\njnz short loc_120A\nmov cs:result_1, 0\ntest edx, edx\njs short loc_128F\nmovsxd rax, edx\nshl rax, 3\nlea rbx, [rsp+rax+88h+var_88]\nmov edx, edx\nshl rdx, 3\nmov r13, rbx\nsub r13, rdx\nlea r12, [rsp+rax+88h+var_90]\nsub r12, rdx\nlea rbp, result_1\nlea r14, delim; \" \"\njmp short loc_127A\nloc_1261:\nmov edx, 64h ; 'd'\nmov rsi, r14\nmov rdi, rbp\ncall ___strcat_chk\nsub rbx, 8\ncmp rbx, r12\njz short loc_128F\nloc_127A:\nmov rsi, [rbx]\nmov edx, 64h ; 'd'\nmov rdi, rbp\ncall ___strcat_chk\ncmp rbx, r13\njnz short loc_1261\nloc_128F:\nmov rax, [rsp+88h+var_30]\nsub rax, fs:28h\njnz short loc_12BC\nlea rax, result_1\nadd rsp, 60h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_12B3:\nmov cs:result_1, 0\njmp short loc_128F\nloc_12BC:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(char *a1)\n{\n char *v1; // rax\n __int64 v2; // rbx\n int v3; // edx\n __int64 v4; // rax\n _QWORD *v5; // rbx\n __int64 v6; // rdx\n _BYTE *v7; // r13\n _BYTE *v8; // r12\n _BYTE v10[96]; // [rsp+0h] [rbp-90h] BYREF\n unsigned __int64 v11; // [rsp+60h] [rbp-30h]\n\n v11 = __readfsqword(0x28u);\n v1 = strtok(a1, \" \");\n if ( v1 )\n {\n v2 = 0LL;\n do\n {\n *(_QWORD *)&v10[8 * v2 + 8] = v1;\n v1 = strtok(0LL, \" \");\n v3 = v2++;\n }\n while ( v1 );\n result_1 = 0;\n if ( v3 >= 0 )\n {\n v4 = 8LL * v3;\n v5 = &v10[v4 + 8];\n v6 = 8LL * (unsigned int)v3;\n v7 = &v10[v4 + 8 - v6];\n v8 = &v10[v4 - v6];\n do\n {\n __strcat_chk(&result_1, *v5, 100LL);\n if ( v5 == (_QWORD *)v7 )\n break;\n __strcat_chk(&result_1, \" \", 100LL);\n --v5;\n }\n while ( v5 != (_QWORD *)v8 );\n }\n }\n else\n {\n result_1 = 0;\n }\n return &result_1;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 60h\nmov rax, fs:28h\nmov [rsp+88h+var_30], rax\nxor eax, eax\nlea rsi, delim; \" \"\ncall _strtok\ntest rax, rax\njz loc_12B3\nmov ebx, 0\nlea rbp, delim; \" \"\nloc_120A:\nmov [rsp+rbx*8+88h+var_88], rax\nmov rsi, rbp; delim\nmov edi, 0; s\ncall _strtok\nmov rdx, rbx\nadd rbx, 1\ntest rax, rax\njnz short loc_120A\nmov cs:byte_4040, 0\ntest edx, edx\njs short loc_128F\nmovsxd rax, edx\nshl rax, 3\nlea rbx, [rsp+rax+88h+var_88]\nmov edx, edx\nshl rdx, 3\nmov r13, rbx\nsub r13, rdx\nlea r12, [rsp+rax+88h+var_90]\nsub r12, rdx\nlea rbp, byte_4040\nlea r14, delim; \" \"\njmp short loc_127A\nloc_1261:\nmov edx, 64h ; 'd'\nmov rsi, r14\nmov rdi, rbp\ncall ___strcat_chk\nsub rbx, 8\ncmp rbx, r12\njz short loc_128F\nloc_127A:\nmov rsi, [rbx]\nmov edx, 64h ; 'd'\nmov rdi, rbp\ncall ___strcat_chk\ncmp rbx, r13\njnz short loc_1261\nloc_128F:\nmov rax, [rsp+88h+var_30]\nsub rax, fs:28h\njnz short loc_12BC\nlea rax, byte_4040\nadd rsp, 60h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_12B3:\nmov cs:byte_4040, 0\njmp short loc_128F\nloc_12BC:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_11C9(char *a1)\n{\n char *v1; // rax\n __int64 v2; // rbx\n int v3; // edx\n __int64 v4; // rax\n _QWORD *v5; // rbx\n __int64 v6; // rdx\n _BYTE *v7; // r13\n _BYTE *v8; // r12\n _BYTE v10[96]; // [rsp+0h] [rbp-90h] BYREF\n unsigned __int64 v11; // [rsp+60h] [rbp-30h]\n\n v11 = __readfsqword(0x28u);\n v1 = strtok(a1, \" \");\n if ( v1 )\n {\n v2 = 0LL;\n do\n {\n *(_QWORD *)&v10[8 * v2 + 8] = v1;\n v1 = strtok(0LL, \" \");\n v3 = v2++;\n }\n while ( v1 );\n byte_4040 = 0;\n if ( v3 >= 0 )\n {\n v4 = 8LL * v3;\n v5 = &v10[v4 + 8];\n v6 = 8LL * (unsigned int)v3;\n v7 = &v10[v4 + 8 - v6];\n v8 = &v10[v4 - v6];\n do\n {\n __strcat_chk(&byte_4040, *v5, 100LL);\n if ( v5 == (_QWORD *)v7 )\n break;\n __strcat_chk(&byte_4040, \" \", 100LL);\n --v5;\n }\n while ( v5 != (_QWORD *)v8 );\n }\n }\n else\n {\n byte_4040 = 0;\n }\n return &byte_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11C9(char *a1) {\n char *v1;\n long long v2;\n int v3;\n long long v4;\n uint64_t *v5;\n long long v6;\n uint8_t *v7;\n uint8_t *v8;\n uint8_t v10[96];\n unsigned long long v11;\n v11 = __readfsqword(40u);\n v1 = strtok(a1, \" \");\n if (v1) {\n v2 = 0LL;\n do {\n *(uint64_t *)&v10[8 * v2 + 8] = v1;\n v1 = strtok(0LL, \" \");\n v3 = v2++;\n } while (v1);\n byte_4040 = 0;\n if (v3 >= 0) {\n v4 = 8LL * v3;\n v5 = &v10[v4 + 8];\n v6 = 8LL * (unsigned int)v3;\n v7 = &v10[v4 + 8 - v6];\n v8 = &v10[v4 - v6];\n do {\n __strcat_chk(&byte_4040, *v5, 100LL);\n if (v5 == (uint64_t *)v7) break;\n __strcat_chk(&byte_4040, \" \", 100LL);\n --v5;\n } while (v5 != (uint64_t *)v8);\n }\n } else {\n byte_4040 = 0;\n }\n return &byte_4040;\n}", + "ida_pseudo_norm": "char *func0(char *a1) {\n char *v1;\n long long v2;\n int v3;\n long long v4;\n uint64_t *v5;\n long long v6;\n uint8_t *v7;\n uint8_t *v8;\n uint8_t v10[96];\n unsigned long long v11;\n v11 = __readfsqword(40u);\n v1 = strtok(a1, \" \");\n if (v1) {\n v2 = 0LL;\n do {\n *(uint64_t *)&v10[8 * v2 + 8] = v1;\n v1 = strtok(0LL, \" \");\n v3 = v2++;\n } while (v1);\n result_1 = 0;\n if (v3 >= 0) {\n v4 = 8LL * v3;\n v5 = &v10[v4 + 8];\n v6 = 8LL * (unsigned int)v3;\n v7 = &v10[v4 + 8 - v6];\n v8 = &v10[v4 - v6];\n do {\n __strcat_chk(&result_1, *v5, 100LL);\n if (v5 == (uint64_t *)v7) break;\n __strcat_chk(&result_1, \" \", 100LL);\n --v5;\n } while (v5 != (uint64_t *)v8);\n }\n } else {\n result_1 = 0;\n }\n return &result_1;\n}" + }, + { + "index": 604, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* s) {\n static char result[100];\n int word_count = 0;\n char* words[10];\n char* token = strtok(s, \" \");\n while (token != NULL) {\n words[word_count++] = token;\n token = strtok(NULL, \" \");\n }\n result[0] = '\\0';\n for (int i = word_count - 1; i >= 0; i--) {\n strcat(result, words[i]);\n if (i > 0) {\n strcat(result, \" \");\n }\n }\n return result;\n}", + "test": "int main() {\n\n char test_string1[] = \"python program\";\n\n char test_string2[] = \"java language\";\n\n char test_string3[] = \"indian man\";\n\n \n\n assert(strcmp(func0(test_string1), \"program python\") == 0);\n\n assert(strcmp(func0(test_string2), \"language java\") == 0);\n\n assert(strcmp(func0(test_string3), \"man indian\") == 0);\n\n \n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nlea 0xcc7(%rip),%rsi\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x68,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x58(%rsp)\nxor %eax,%eax\ncallq 10d0 \ntest %rax,%rax\nje 1458 \nxor %r13d,%r13d\nmov %rsp,%rbp\nlea 0xc90(%rip),%r12\nnopl 0x0(%rax)\nmov %r12,%rsi\nxor %edi,%edi\nmov %rax,0x0(%rbp,%r13,8)\nmov %rax,%r15\ncallq 10d0 \nmovslq %r13d,%rbx\nadd $0x1,%r13\ntest %rax,%rax\njne 1378 \nlea 0x2ca3(%rip),%r12\nmovb $0x0,0x2c9c(%rip)\nlea 0x0(%rbp,%rbx,8),%rbx\nmov %r12,%r13\nlea 0x64(%r12),%r14\njmp 13d6 \nnopl 0x0(%rax,%rax,1)\nmov %r14,%rcx\nmov $0x2,%edx\nlea 0xc3d(%rip),%rsi\nsub $0x8,%rbx\nsub %rax,%rcx\ncallq 10b0 <__memcpy_chk@plt>\nmov (%rbx),%r15\nlea 0x2c63(%rip),%rdi\nmov (%rdi),%edx\nadd $0x4,%rdi\nlea -0x1010101(%rdx),%eax\nnot %edx\nand %edx,%eax\nand $0x80808080,%eax\nje 13dd \nmov %eax,%edx\nshr $0x10,%edx\ntest $0x8080,%eax\ncmove %edx,%eax\nlea 0x2(%rdi),%rdx\ncmove %rdx,%rdi\nmov $0x64,%edx\nmov %eax,%esi\nadd %al,%sil\nmov %r15,%rsi\nsbb $0x3,%rdi\nsub %r12,%rdi\nadd %r13,%rdi\ncallq 10c0 <__stpcpy_chk@plt>\nmov %rax,%rdi\ncmp %rbp,%rbx\njne 13b8 \nmov 0x58(%rsp),%rax\nxor %fs:0x28,%rax\njne 1461 \nadd $0x68,%rsp\nlea 0x2bf8(%rip),%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax,%rax,1)\nmovb $0x0,0x2be1(%rip)\njmp 142d \ncallq 1090 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\nlea rbp, delim; \" \"\npush rbx\nmov rsi, rbp; delim\nsub rsp, 60h\nmov rax, fs:28h\nmov [rsp+88h+var_30], rax\nxor eax, eax\ncall _strtok\ntest rax, rax\njz loc_1430\nxor ebx, ebx\nmov r12, rsp\nnop dword ptr [rax]\nloc_1390:\nmov rsi, rbp; delim\nxor edi, edi; s\nmov [r12+rbx*8], rax\ncall _strtok\nmov rdx, rbx\nadd rbx, 1\ntest rax, rax\njnz short loc_1390\nmovsxd rax, edx\nmov cs:result_1, 0\nshl rdx, 3\nlea rbx, [r12+rax*8]\nlea r12, result_1\nmov r13, rbx\nlea r14, [r12+64h]\nsub r13, rdx\nxchg ax, ax\nloc_13D0:\nmov rdi, r12; s\ncall _strlen\nmov rsi, [rbx]\nmov edx, 64h ; 'd'\nlea rdi, [r12+rax]\ncall ___stpcpy_chk\ncmp rbx, r13\njnz short loc_1410\nloc_13EE:\nmov rax, [rsp+88h+var_30]\nsub rax, fs:28h\njnz short loc_1440\nadd rsp, 60h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1410:\nmov rcx, r14\nmov edx, 2\nmov rsi, rbp\nmov rdi, rax\nsub rcx, rax\nsub rbx, 8\ncall ___memcpy_chk\njmp short loc_13D0\nloc_1430:\nmov cs:result_1, 0\nlea r12, result_1\njmp short loc_13EE\nloc_1440:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(char *a1)\n{\n char *v1; // rax\n __int64 v2; // rbx\n __int64 v3; // rdx\n _QWORD *v4; // rbx\n _QWORD *v5; // r13\n size_t v6; // rax\n __int64 v7; // rax\n _QWORD v9[17]; // [rsp+0h] [rbp-88h] BYREF\n\n v9[11] = __readfsqword(0x28u);\n v1 = strtok(a1, \" \");\n if ( v1 )\n {\n v2 = 0LL;\n do\n {\n v9[v2] = v1;\n v1 = strtok(0LL, \" \");\n v3 = v2++;\n }\n while ( v1 );\n result_1[0] = 0;\n v4 = &v9[(int)v3];\n v5 = &v4[-v3];\n while ( 1 )\n {\n v6 = strlen(result_1);\n v7 = __stpcpy_chk(&result_1[v6], *v4, 100LL);\n if ( v4 == v5 )\n break;\n --v4;\n __memcpy_chk(v7, \" \", 2LL, &result_1[-v7 + 100]);\n }\n }\n else\n {\n result_1[0] = 0;\n }\n return result_1;\n}", + "ida_strip_asm": "sub_1350:\nendbr64\npush r14\npush r13\npush r12\npush rbp\nlea rbp, delim; \" \"\npush rbx\nmov rsi, rbp; delim\nsub rsp, 60h\nmov rax, fs:28h\nmov [rsp+88h+var_30], rax\nxor eax, eax\ncall _strtok\ntest rax, rax\njz loc_1430\nxor ebx, ebx\nmov r12, rsp\nnop dword ptr [rax]\nloc_1390:\nmov rsi, rbp; delim\nxor edi, edi; s\nmov [r12+rbx*8], rax\ncall _strtok\nmov rdx, rbx\nadd rbx, 1\ntest rax, rax\njnz short loc_1390\nmovsxd rax, edx\nmov cs:s, 0\nshl rdx, 3\nlea rbx, [r12+rax*8]\nlea r12, s\nmov r13, rbx\nlea r14, [r12+64h]\nsub r13, rdx\nxchg ax, ax\nloc_13D0:\nmov rdi, r12; s\ncall _strlen\nmov rsi, [rbx]\nmov edx, 64h ; 'd'\nlea rdi, [r12+rax]\ncall ___stpcpy_chk\ncmp rbx, r13\njnz short loc_1410\nloc_13EE:\nmov rax, [rsp+88h+var_30]\nsub rax, fs:28h\njnz short loc_1440\nadd rsp, 60h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1410:\nmov rcx, r14\nmov edx, 2\nmov rsi, rbp\nmov rdi, rax\nsub rcx, rax\nsub rbx, 8\ncall ___memcpy_chk\njmp short loc_13D0\nloc_1430:\nmov cs:s, 0\nlea r12, s\njmp short loc_13EE\nloc_1440:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_1350(char *a1)\n{\n char *v1; // rax\n __int64 v2; // rbx\n __int64 v3; // rdx\n _QWORD *v4; // rbx\n _QWORD *v5; // r13\n size_t v6; // rax\n __int64 v7; // rax\n _QWORD v9[17]; // [rsp+0h] [rbp-88h] BYREF\n\n v9[11] = __readfsqword(0x28u);\n v1 = strtok(a1, \" \");\n if ( v1 )\n {\n v2 = 0LL;\n do\n {\n v9[v2] = v1;\n v1 = strtok(0LL, \" \");\n v3 = v2++;\n }\n while ( v1 );\n s[0] = 0;\n v4 = &v9[(int)v3];\n v5 = &v4[-v3];\n while ( 1 )\n {\n v6 = strlen(s);\n v7 = __stpcpy_chk(&s[v6], *v4, 100LL);\n if ( v4 == v5 )\n break;\n --v4;\n __memcpy_chk(v7, \" \", 2LL, &s[-v7 + 100]);\n }\n }\n else\n {\n s[0] = 0;\n }\n return s;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1350(char *a1) {\n char *v1;\n long long v2;\n long long v3;\n uint64_t *v4;\n uint64_t *v5;\n unsigned int v6;\n long long v7;\n uint64_t v9[17];\n v9[11] = __readfsqword(40u);\n v1 = strtok(a1, \" \");\n if (v1) {\n v2 = 0LL;\n do {\n v9[v2] = v1;\n v1 = strtok(0LL, \" \");\n v3 = v2++;\n } while (v1);\n s[0] = 0;\n v4 = &v9[(int)v3];\n v5 = &v4[-v3];\n while (1) {\n v6 = strlen(s);\n v7 = __stpcpy_chk(&s[v6], *v4, 100LL);\n if (v4 == v5) break;\n --v4;\n __memcpy_chk(v7, \" \", 2LL, &s[-v7 + 100]);\n }\n } else {\n s[0] = 0;\n }\n return s;\n}", + "ida_pseudo_norm": "char *func0(char *a1) {\n char *v1;\n long long v2;\n long long v3;\n uint64_t *v4;\n uint64_t *v5;\n unsigned int v6;\n long long v7;\n uint64_t v9[17];\n v9[11] = __readfsqword(40u);\n v1 = strtok(a1, \" \");\n if (v1) {\n v2 = 0LL;\n do {\n v9[v2] = v1;\n v1 = strtok(0LL, \" \");\n v3 = v2++;\n } while (v1);\n result_1[0] = 0;\n v4 = &v9[(int)v3];\n v5 = &v4[-v3];\n while (1) {\n v6 = strlen(result_1);\n v7 = __stpcpy_chk(&result_1[v6], *v4, 100LL);\n if (v4 == v5) break;\n --v4;\n __memcpy_chk(v7, \" \", 2LL, &result_1[-v7 + 100]);\n }\n } else {\n result_1[0] = 0;\n }\n return result_1;\n}" + }, + { + "index": 604, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* s) {\n static char result[100];\n int word_count = 0;\n char* words[10];\n char* token = strtok(s, \" \");\n while (token != NULL) {\n words[word_count++] = token;\n token = strtok(NULL, \" \");\n }\n result[0] = '\\0';\n for (int i = word_count - 1; i >= 0; i--) {\n strcat(result, words[i]);\n if (i > 0) {\n strcat(result, \" \");\n }\n }\n return result;\n}", + "test": "int main() {\n\n char test_string1[] = \"python program\";\n\n char test_string2[] = \"java language\";\n\n char test_string3[] = \"indian man\";\n\n \n\n assert(strcmp(func0(test_string1), \"program python\") == 0);\n\n assert(strcmp(func0(test_string2), \"language java\") == 0);\n\n assert(strcmp(func0(test_string3), \"man indian\") == 0);\n\n \n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nlea 0xcc7(%rip),%rsi\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x68,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x58(%rsp)\nxor %eax,%eax\ncallq 10d0 \ntest %rax,%rax\nje 1458 \nxor %ebp,%ebp\nmov %rsp,%rbx\nlea 0xc91(%rip),%r13\nnopl 0x0(%rax,%rax,1)\nmov %r13,%rsi\nxor %edi,%edi\nmov %rax,(%rbx,%rbp,8)\nmovslq %ebp,%r12\ncallq 10d0 \nadd $0x1,%rbp\ntest %rax,%rax\njne 1378 \nlea (%rbx,%r12,8),%r15\nlea 0x2ca3(%rip),%rbp\nmovb $0x0,0x2c9c(%rip)\nlea -0x8(%rsp),%r14\nmov %rbp,%r12\nlea 0x64(%rbp),%r13\njmp 13d8 \nnopw 0x0(%rax,%rax,1)\nmov %r13,%rcx\nmov $0x2,%edx\nlea 0xc3d(%rip),%rsi\nsub $0x8,%r15\nsub %rax,%rcx\ncallq 10b0 <__memcpy_chk@plt>\ncmp %r14,%r15\nje 142f \nlea 0x2c61(%rip),%rdi\nmov (%rdi),%edx\nadd $0x4,%rdi\nlea -0x1010101(%rdx),%eax\nnot %edx\nand %edx,%eax\nand $0x80808080,%eax\nje 13df \nmov %eax,%edx\nshr $0x10,%edx\ntest $0x8080,%eax\ncmove %edx,%eax\nlea 0x2(%rdi),%rdx\ncmove %rdx,%rdi\nmov $0x64,%edx\nmov %eax,%esi\nadd %al,%sil\nmov (%r15),%rsi\nsbb $0x3,%rdi\nsub %rbp,%rdi\nadd %r12,%rdi\ncallq 10c0 <__stpcpy_chk@plt>\nmov %rax,%rdi\ncmp %rbx,%r15\njne 13b8 \nmov 0x58(%rsp),%rax\nxor %fs:0x28,%rax\njne 1461 \nadd $0x68,%rsp\nlea 0x2bf6(%rip),%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl (%rax)\nmovb $0x0,0x2be1(%rip)\njmp 142f \ncallq 1090 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\nlea rbp, delim; \" \"\npush rbx\nmov rsi, rbp; delim\nsub rsp, 60h\nmov rax, fs:28h\nmov [rsp+88h+var_30], rax\nxor eax, eax\ncall _strtok\ntest rax, rax\njz loc_1430\nxor ebx, ebx\nmov r12, rsp\nnop dword ptr [rax]\nloc_1390:\nmov rsi, rbp; delim\nxor edi, edi; s\nmov [r12+rbx*8], rax\ncall _strtok\nmov rdx, rbx\nadd rbx, 1\ntest rax, rax\njnz short loc_1390\nmovsxd rax, edx\nmov cs:result_1, 0\nshl rdx, 3\nlea rbx, [r12+rax*8]\nlea r12, result_1\nmov r13, rbx\nlea r14, [r12+64h]\nsub r13, rdx\nxchg ax, ax\nloc_13D0:\nmov rdi, r12; s\ncall _strlen\nmov rsi, [rbx]\nmov edx, 64h ; 'd'\nlea rdi, [r12+rax]\ncall ___stpcpy_chk\ncmp rbx, r13\njnz short loc_1410\nloc_13EE:\nmov rax, [rsp+88h+var_30]\nsub rax, fs:28h\njnz short loc_1440\nadd rsp, 60h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1410:\nmov rcx, r14\nmov edx, 2\nmov rsi, rbp\nmov rdi, rax\nsub rcx, rax\nsub rbx, 8\ncall ___memcpy_chk\njmp short loc_13D0\nloc_1430:\nmov cs:result_1, 0\nlea r12, result_1\njmp short loc_13EE\nloc_1440:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(char *a1)\n{\n char *v1; // rax\n __int64 v2; // rbx\n __int64 v3; // rdx\n _QWORD *v4; // rbx\n _QWORD *v5; // r13\n size_t v6; // rax\n __int64 v7; // rax\n _QWORD v9[17]; // [rsp+0h] [rbp-88h] BYREF\n\n v9[11] = __readfsqword(0x28u);\n v1 = strtok(a1, \" \");\n if ( v1 )\n {\n v2 = 0LL;\n do\n {\n v9[v2] = v1;\n v1 = strtok(0LL, \" \");\n v3 = v2++;\n }\n while ( v1 );\n result_1[0] = 0;\n v4 = &v9[(int)v3];\n v5 = &v4[-v3];\n while ( 1 )\n {\n v6 = strlen(result_1);\n v7 = __stpcpy_chk(&result_1[v6], *v4, 100LL);\n if ( v4 == v5 )\n break;\n --v4;\n __memcpy_chk(v7, \" \", 2LL, &result_1[-v7 + 100]);\n }\n }\n else\n {\n result_1[0] = 0;\n }\n return result_1;\n}", + "ida_strip_asm": "sub_1350:\nendbr64\npush r14\npush r13\npush r12\npush rbp\nlea rbp, delim; \" \"\npush rbx\nmov rsi, rbp; delim\nsub rsp, 60h\nmov rax, fs:28h\nmov [rsp+88h+var_30], rax\nxor eax, eax\ncall _strtok\ntest rax, rax\njz loc_1430\nxor ebx, ebx\nmov r12, rsp\nnop dword ptr [rax]\nloc_1390:\nmov rsi, rbp; delim\nxor edi, edi; s\nmov [r12+rbx*8], rax\ncall _strtok\nmov rdx, rbx\nadd rbx, 1\ntest rax, rax\njnz short loc_1390\nmovsxd rax, edx\nmov cs:s, 0\nshl rdx, 3\nlea rbx, [r12+rax*8]\nlea r12, s\nmov r13, rbx\nlea r14, [r12+64h]\nsub r13, rdx\nxchg ax, ax\nloc_13D0:\nmov rdi, r12; s\ncall _strlen\nmov rsi, [rbx]\nmov edx, 64h ; 'd'\nlea rdi, [r12+rax]\ncall ___stpcpy_chk\ncmp rbx, r13\njnz short loc_1410\nloc_13EE:\nmov rax, [rsp+88h+var_30]\nsub rax, fs:28h\njnz short loc_1440\nadd rsp, 60h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1410:\nmov rcx, r14\nmov edx, 2\nmov rsi, rbp\nmov rdi, rax\nsub rcx, rax\nsub rbx, 8\ncall ___memcpy_chk\njmp short loc_13D0\nloc_1430:\nmov cs:s, 0\nlea r12, s\njmp short loc_13EE\nloc_1440:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_1350(char *a1)\n{\n char *v1; // rax\n __int64 v2; // rbx\n __int64 v3; // rdx\n _QWORD *v4; // rbx\n _QWORD *v5; // r13\n size_t v6; // rax\n __int64 v7; // rax\n _QWORD v9[17]; // [rsp+0h] [rbp-88h] BYREF\n\n v9[11] = __readfsqword(0x28u);\n v1 = strtok(a1, \" \");\n if ( v1 )\n {\n v2 = 0LL;\n do\n {\n v9[v2] = v1;\n v1 = strtok(0LL, \" \");\n v3 = v2++;\n }\n while ( v1 );\n s[0] = 0;\n v4 = &v9[(int)v3];\n v5 = &v4[-v3];\n while ( 1 )\n {\n v6 = strlen(s);\n v7 = __stpcpy_chk(&s[v6], *v4, 100LL);\n if ( v4 == v5 )\n break;\n --v4;\n __memcpy_chk(v7, \" \", 2LL, &s[-v7 + 100]);\n }\n }\n else\n {\n s[0] = 0;\n }\n return s;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1350(char *a1) {\n char *v1;\n long long v2;\n long long v3;\n uint64_t *v4;\n uint64_t *v5;\n unsigned int v6;\n long long v7;\n uint64_t v9[17];\n v9[11] = __readfsqword(40u);\n v1 = strtok(a1, \" \");\n if (v1) {\n v2 = 0LL;\n do {\n v9[v2] = v1;\n v1 = strtok(0LL, \" \");\n v3 = v2++;\n } while (v1);\n s[0] = 0;\n v4 = &v9[(int)v3];\n v5 = &v4[-v3];\n while (1) {\n v6 = strlen(s);\n v7 = __stpcpy_chk(&s[v6], *v4, 100LL);\n if (v4 == v5) break;\n --v4;\n __memcpy_chk(v7, \" \", 2LL, &s[-v7 + 100]);\n }\n } else {\n s[0] = 0;\n }\n return s;\n}", + "ida_pseudo_norm": "char *func0(char *a1) {\n char *v1;\n long long v2;\n long long v3;\n uint64_t *v4;\n uint64_t *v5;\n unsigned int v6;\n long long v7;\n uint64_t v9[17];\n v9[11] = __readfsqword(40u);\n v1 = strtok(a1, \" \");\n if (v1) {\n v2 = 0LL;\n do {\n v9[v2] = v1;\n v1 = strtok(0LL, \" \");\n v3 = v2++;\n } while (v1);\n result_1[0] = 0;\n v4 = &v9[(int)v3];\n v5 = &v4[-v3];\n while (1) {\n v6 = strlen(result_1);\n v7 = __stpcpy_chk(&result_1[v6], *v4, 100LL);\n if (v4 == v5) break;\n --v4;\n __memcpy_chk(v7, \" \", 2LL, &result_1[-v7 + 100]);\n }\n } else {\n result_1[0] = 0;\n }\n return result_1;\n}" + }, + { + "index": 605, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int num) {\n if (num >= 1) {\n for (int i = 2; i <= num / 2; i++) {\n if (num % i == 0) {\n return false;\n }\n }\n return true;\n }\n else {\n return false;\n }\n}", + "test": "int main() {\n\n assert(func0(13) == true);\n\n assert(func0(7) == true);\n\n assert(func0(-1010) == false);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\ncmpl $0x0,-0x14(%rbp)\njle 1193 \nmovl $0x2,-0x4(%rbp)\njmp 117b \nmov -0x14(%rbp),%eax\ncltd\nidivl -0x4(%rbp)\nmov %edx,%eax\ntest %eax,%eax\njne 1177 \nmov $0x0,%eax\njmp 1198 \naddl $0x1,-0x4(%rbp)\nmov -0x14(%rbp),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\ncmp %eax,-0x4(%rbp)\njle 1163 \nmov $0x1,%eax\njmp 1198 \nmov $0x0,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\ncmp [rbp+var_14], 0\njle short loc_1193\nmov [rbp+var_4], 2\njmp short loc_117B\nloc_1163:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njnz short loc_1177\nmov eax, 0\njmp short loc_1198\nloc_1177:\nadd [rbp+var_4], 1\nloc_117B:\nmov eax, [rbp+var_14]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\ncmp [rbp+var_4], eax\njle short loc_1163\nmov eax, 1\njmp short loc_1198\nloc_1193:\nmov eax, 0\nloc_1198:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int i; // [rsp+10h] [rbp-4h]\n\n if ( a1 <= 0 )\n return 0LL;\n for ( i = 2; i <= a1 / 2; ++i )\n {\n if ( !(a1 % i) )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\ncmp [rbp+var_14], 0\njle short loc_1193\nmov [rbp+var_4], 2\njmp short loc_117B\nloc_1163:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njnz short loc_1177\nmov eax, 0\njmp short loc_1198\nloc_1177:\nadd [rbp+var_4], 1\nloc_117B:\nmov eax, [rbp+var_14]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\ncmp [rbp+var_4], eax\njle short loc_1163\nmov eax, 1\njmp short loc_1198\nloc_1193:\nmov eax, 0\nloc_1198:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int i; // [rsp+10h] [rbp-4h]\n\n if ( a1 <= 0 )\n return 0LL;\n for ( i = 2; i <= a1 / 2; ++i )\n {\n if ( !(a1 % i) )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int i;\n if (a1 <= 0) return 0LL;\n for (i = 2; i <= a1 / 2; ++i) {\n if (!(a1 % i)) return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int i;\n if (a1 <= 0) return 0LL;\n for (i = 2; i <= a1 / 2; ++i) {\n if (!(a1 % i)) return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": 605, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int num) {\n if (num >= 1) {\n for (int i = 2; i <= num / 2; i++) {\n if (num % i == 0) {\n return false;\n }\n }\n return true;\n }\n else {\n return false;\n }\n}", + "test": "int main() {\n\n assert(func0(13) == true);\n\n assert(func0(7) == true);\n\n assert(func0(-1010) == false);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x0,%eax\ntest %edi,%edi\njle 1184 \nmov %edi,%esi\nshr $0x1f,%esi\nadd %edi,%esi\nsar %esi\ncmp $0x3,%edi\njle 118b \ntest $0x1,%dil\nje 1191 \nmov $0x2,%ecx\nadd $0x1,%ecx\ncmp %esi,%ecx\njg 1185 \nmov %edi,%eax\ncltd\nidiv %ecx\ntest %edx,%edx\njne 116f \nmov $0x0,%eax\nretq\nmov $0x1,%eax\nretq\nmov $0x1,%eax\nretq\nmov $0x0,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov eax, 0\ntest edi, edi\njle short locret_1184\nmov esi, edi\nshr esi, 1Fh\nadd esi, edi\nsar esi, 1\ncmp edi, 3\njle short loc_118B\ntest dil, 1\njz short loc_1191\nmov ecx, 2\nloc_116F:\nadd ecx, 1\ncmp ecx, esi\njg short loc_1185\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_116F\nmov eax, 0\nlocret_1184:\nretn\nloc_1185:\nmov eax, 1\nretn\nloc_118B:\nmov eax, 1\nretn\nloc_1191:\nmov eax, 0\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n __int64 result; // rax\n int v2; // ecx\n\n result = 0LL;\n if ( a1 > 0 )\n {\n if ( a1 <= 3 )\n {\n return 1LL;\n }\n else if ( (a1 & 1) != 0 )\n {\n v2 = 2;\n while ( ++v2 <= a1 / 2 )\n {\n if ( !(a1 % v2) )\n return 0LL;\n }\n return 1LL;\n }\n else\n {\n return 0LL;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmov eax, 0\ntest edi, edi\njle short locret_1184\nmov esi, edi\nshr esi, 1Fh\nadd esi, edi\nsar esi, 1\ncmp edi, 3\njle short loc_118B\ntest dil, 1\njz short loc_1191\nmov ecx, 2\nloc_116F:\nadd ecx, 1\ncmp ecx, esi\njg short loc_1185\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_116F\nmov eax, 0\nlocret_1184:\nretn\nloc_1185:\nmov eax, 1\nretn\nloc_118B:\nmov eax, 1\nretn\nloc_1191:\nmov eax, 0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n __int64 result; // rax\n int v2; // ecx\n\n result = 0LL;\n if ( a1 > 0 )\n {\n if ( a1 <= 3 )\n {\n return 1LL;\n }\n else if ( (a1 & 1) != 0 )\n {\n v2 = 2;\n while ( ++v2 <= a1 / 2 )\n {\n if ( !(a1 % v2) )\n return 0LL;\n }\n return 1LL;\n }\n else\n {\n return 0LL;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n long long result;\n int v2;\n result = 0LL;\n if (a1 > 0) {\n if (a1 <= 3) {\n return 1LL;\n } else if ((a1 & 1) != 0) {\n v2 = 2;\n while (++v2 <= a1 / 2) {\n if (!(a1 % v2)) return 0LL;\n }\n return 1LL;\n } else {\n return 0LL;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n long long result;\n int v2;\n result = 0LL;\n if (a1 > 0) {\n if (a1 <= 3) {\n return 1LL;\n } else if ((a1 & 1) != 0) {\n v2 = 2;\n while (++v2 <= a1 / 2) {\n if (!(a1 % v2)) return 0LL;\n }\n return 1LL;\n } else {\n return 0LL;\n }\n }\n return result;\n}" + }, + { + "index": 606, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "double func0(double degree) {\n double radian = degree * (M_PI / 180);\n return radian;\n}", + "test": "int main() {\n\n assert(func0(90) == 1.5707963267948966);\n\n assert(func0(60) == 1.0471975511965976);\n\n assert(func0(120) == 2.0943951023931953);\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmovsd %xmm0,-0x18(%rbp)\nmovsd -0x18(%rbp),%xmm1\nmovsd 0xf4d(%rip),%xmm0\nmulsd %xmm1,%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmovsd -0x8(%rbp),%xmm0\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmovsd [rbp+var_18], xmm0\nmovsd xmm1, [rbp+var_18]\nmovsd xmm0, cs:qword_2090\nmulsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "double __fastcall func0(double a1)\n{\n return 0.0174532925199433 * a1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmovsd [rbp+var_18], xmm0\nmovsd xmm1, [rbp+var_18]\nmovsd xmm0, cs:qword_2090\nmulsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "double __fastcall sub_1149(double a1)\n{\n return 0.0174532925199433 * a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1149(double a1) { return 0.0174532925199433 * a1; }", + "ida_pseudo_norm": "double func0(double a1) { return 0.0174532925199433 * a1; }" + }, + { + "index": 607, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct MatchResult {\n\n char* pattern;\n\n int start;\n\n int end;\n\n} MatchResult;\n\n\n\n", + "func": "MatchResult func0(const char* text, const char* pattern) {\n MatchResult result;\n result.pattern = NULL;\n result.start = -1;\n result.end = -1;\n const char *start, *end;\n start = strstr(text, pattern);\n if (start != NULL) {\n end = start + strlen(pattern);\n result.pattern = (char*)malloc(strlen(pattern) + 1);\n strcpy(result.pattern, pattern);\n result.start = (int)(start - text);\n result.end = (int)(end - text);\n }\n return result;\n}", + "test": "int main() {\n\n MatchResult r1, r2, r3;\n\n \n\n r1 = func0(\"The quick brown fox jumps over the lazy dog.\", \"fox\");\n\n r2 = func0(\"Its been a very crazy procedure right\", \"crazy\");\n\n r3 = func0(\"Hardest choices required strongest will\", \"will\");\n\n \n\n assert(strcmp(r1.pattern, \"fox\") == 0 && r1.start == 16 && r1.end == 19);\n\n assert(strcmp(r2.pattern, \"crazy\") == 0 && r2.start == 16 && r2.end == 21);\n\n assert(strcmp(r3.pattern, \"will\") == 0 && r3.start == 35 && r3.end == 39);\n\n \n\n free(r1.pattern);\n\n free(r2.pattern);\n\n free(r3.pattern);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x28(%rbp)\nmov %rsi,-0x30(%rbp)\nmovq $0x0,-0x10(%rbp)\nmovl $0xffffffff,-0x8(%rbp)\nmovl $0xffffffff,-0x4(%rbp)\nmov -0x30(%rbp),%rdx\nmov -0x28(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1110 \nmov %rax,-0x20(%rbp)\ncmpq $0x0,-0x20(%rbp)\nje 12ad \nmov -0x30(%rbp),%rax\nmov %rax,%rdi\ncallq 10d0 \nmov -0x20(%rbp),%rdx\nadd %rdx,%rax\nmov %rax,-0x18(%rbp)\nmov -0x30(%rbp),%rax\nmov %rax,%rdi\ncallq 10d0 \nadd $0x1,%rax\nmov %rax,%rdi\ncallq 1100 \nmov %rax,-0x10(%rbp)\nmov -0x10(%rbp),%rax\nmov -0x30(%rbp),%rdx\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10c0 \nmov -0x20(%rbp),%rax\nsub -0x28(%rbp),%rax\nmov %eax,-0x8(%rbp)\nmov -0x18(%rbp),%rax\nsub -0x28(%rbp),%rax\nmov %eax,-0x4(%rbp)\nmov -0x10(%rbp),%rax\nmov -0x8(%rbp),%rdx\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+haystack], rdi\nmov [rbp+needle], rsi\nmov [rbp+dest], 0\nmov dword ptr [rbp+var_8], 0FFFFFFFFh\nmov dword ptr [rbp+var_8+4], 0FFFFFFFFh\nmov rdx, [rbp+needle]\nmov rax, [rbp+haystack]\nmov rsi, rdx; needle\nmov rdi, rax; haystack\ncall _strstr\nmov [rbp+var_20], rax\ncmp [rbp+var_20], 0\njz short loc_12AD\nmov rax, [rbp+needle]\nmov rdi, rax; s\ncall _strlen\nmov rdx, [rbp+var_20]\nadd rax, rdx\nmov [rbp+var_18], rax\nmov rax, [rbp+needle]\nmov rdi, rax; s\ncall _strlen\nadd rax, 1\nmov rdi, rax; size\ncall _malloc\nmov [rbp+dest], rax\nmov rax, [rbp+dest]\nmov rdx, [rbp+needle]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\nmov rax, [rbp+var_20]\nsub rax, [rbp+haystack]\nmov dword ptr [rbp+var_8], eax\nmov rax, [rbp+var_18]\nsub rax, [rbp+haystack]\nmov dword ptr [rbp+var_8+4], eax\nloc_12AD:\nmov rax, [rbp+dest]\nmov rdx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(const char *a1, const char *a2)\n{\n size_t v2; // rax\n char *dest; // [rsp+20h] [rbp-10h]\n\n dest = 0LL;\n if ( strstr(a1, a2) )\n {\n strlen(a2);\n v2 = strlen(a2);\n dest = (char *)malloc(v2 + 1);\n strcpy(dest, a2);\n }\n return dest;\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+haystack], rdi\nmov [rbp+needle], rsi\nmov [rbp+dest], 0\nmov dword ptr [rbp+var_8], 0FFFFFFFFh\nmov dword ptr [rbp+var_8+4], 0FFFFFFFFh\nmov rdx, [rbp+needle]\nmov rax, [rbp+haystack]\nmov rsi, rdx; needle\nmov rdi, rax; haystack\ncall _strstr\nmov [rbp+var_20], rax\ncmp [rbp+var_20], 0\njz short loc_12AD\nmov rax, [rbp+needle]\nmov rdi, rax; s\ncall _strlen\nmov rdx, [rbp+var_20]\nadd rax, rdx\nmov [rbp+var_18], rax\nmov rax, [rbp+needle]\nmov rdi, rax; s\ncall _strlen\nadd rax, 1\nmov rdi, rax; size\ncall _malloc\nmov [rbp+dest], rax\nmov rax, [rbp+dest]\nmov rdx, [rbp+needle]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\nmov rax, [rbp+var_20]\nsub rax, [rbp+haystack]\nmov dword ptr [rbp+var_8], eax\nmov rax, [rbp+var_18]\nsub rax, [rbp+haystack]\nmov dword ptr [rbp+var_8+4], eax\nloc_12AD:\nmov rax, [rbp+dest]\nmov rdx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1209(const char *a1, const char *a2)\n{\n size_t v2; // rax\n char *dest; // [rsp+20h] [rbp-10h]\n\n dest = 0LL;\n if ( strstr(a1, a2) )\n {\n strlen(a2);\n v2 = strlen(a2);\n dest = (char *)malloc(v2 + 1);\n strcpy(dest, a2);\n }\n return dest;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1209(const char *a1, const char *a2) {\n unsigned int v2;\n char *dest;\n dest = 0LL;\n if (strstr(a1, a2)) {\n strlen(a2);\n v2 = strlen(a2);\n dest = (char *)malloc(v2 + 1);\n strcpy(dest, a2);\n }\n return dest;\n}", + "ida_pseudo_norm": "char *func0(const char *a1, const char *a2) {\n unsigned int v2;\n char *dest;\n dest = 0LL;\n if (strstr(a1, a2)) {\n strlen(a2);\n v2 = strlen(a2);\n dest = (char *)malloc(v2 + 1);\n strcpy(dest, a2);\n }\n return dest;\n}" + }, + { + "index": 607, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct MatchResult {\n\n char* pattern;\n\n int start;\n\n int end;\n\n} MatchResult;\n\n\n\n", + "func": "MatchResult func0(const char* text, const char* pattern) {\n MatchResult result;\n result.pattern = NULL;\n result.start = -1;\n result.end = -1;\n const char *start, *end;\n start = strstr(text, pattern);\n if (start != NULL) {\n end = start + strlen(pattern);\n result.pattern = (char*)malloc(strlen(pattern) + 1);\n strcpy(result.pattern, pattern);\n result.start = (int)(start - text);\n result.end = (int)(end - text);\n }\n return result;\n}", + "test": "int main() {\n\n MatchResult r1, r2, r3;\n\n \n\n r1 = func0(\"The quick brown fox jumps over the lazy dog.\", \"fox\");\n\n r2 = func0(\"Its been a very crazy procedure right\", \"crazy\");\n\n r3 = func0(\"Hardest choices required strongest will\", \"will\");\n\n \n\n assert(strcmp(r1.pattern, \"fox\") == 0 && r1.start == 16 && r1.end == 19);\n\n assert(strcmp(r2.pattern, \"crazy\") == 0 && r2.start == 16 && r2.end == 21);\n\n assert(strcmp(r3.pattern, \"will\") == 0 && r3.start == 35 && r3.end == 39);\n\n \n\n free(r1.pattern);\n\n free(r2.pattern);\n\n free(r3.pattern);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%r13\nmov %rsi,%r14\ncallq 10d0 \nmov %rax,%rbx\ntest %rax,%rax\nje 123a \nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nmov %r14,%rdi\nrepnz scas %es:(%rdi),%al\nnot %rcx\nmov %rcx,%rdi\nlea -0x1(%rcx),%rbp\ncallq 10c0 \nmov %rax,%r12\nmov %r14,%rsi\nmov %rax,%rdi\ncallq 10a0 \nmov %ebx,%eax\nsub %r13d,%eax\nlea (%rbx,%rbp,1),%rdx\nsub %r13d,%edx\nmov %r12,%rbx\nshl $0x20,%rdx\nmov %eax,%eax\nor %rax,%rdx\nmov %rbx,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nmov $0xffffffff,%edx\nmov $0xffffffff,%eax\njmp 1225 \n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12, rdi\nmov r14, rsi\ncall _strstr\nmov rbp, rax\ntest rax, rax\njz short loc_1281\nmov rdi, r14; s\ncall _strlen\nmov rbx, rax\nlea r15, [rax+1]\nmov rdi, r15; size\ncall _malloc\nmov r13, rax\nmov rdx, r15\nmov rsi, r14\nmov rdi, rax\ncall ___strcpy_chk\nmov edx, ebp\nsub edx, r12d\nlea rax, [rbp+rbx+0]\nsub eax, r12d\nmov rbp, r13\nloc_1266:\nshl rax, 20h\nmov edx, edx\nor rdx, rax\nmov rax, rbp\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1281:\nmov eax, 0FFFFFFFFh\nmov edx, 0FFFFFFFFh\njmp short loc_1266", + "ida_pseudo": "char *__fastcall func0(const char *a1, const char *a2)\n{\n char *v2; // rbp\n size_t v3; // rbx\n void *v4; // r13\n\n v2 = strstr(a1, a2);\n if ( v2 )\n {\n v3 = strlen(a2);\n v4 = malloc(v3 + 1);\n __strcpy_chk(v4, a2, v3 + 1);\n return (char *)v4;\n }\n return v2;\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12, rdi\nmov r14, rsi\ncall _strstr\nmov rbp, rax\ntest rax, rax\njz short loc_1281\nmov rdi, r14; s\ncall _strlen\nmov rbx, rax\nlea r15, [rax+1]\nmov rdi, r15; size\ncall _malloc\nmov r13, rax\nmov rdx, r15\nmov rsi, r14\nmov rdi, rax\ncall ___strcpy_chk\nmov edx, ebp\nsub edx, r12d\nlea rax, [rbp+rbx+0]\nsub eax, r12d\nmov rbp, r13\nloc_1266:\nshl rax, 20h\nmov edx, edx\nor rdx, rax\nmov rax, rbp\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1281:\nmov eax, 0FFFFFFFFh\nmov edx, 0FFFFFFFFh\njmp short loc_1266", + "ida_strip_pseudo": "char *__fastcall sub_1209(const char *a1, const char *a2)\n{\n char *v2; // rbp\n size_t v3; // rbx\n void *v4; // r13\n\n v2 = strstr(a1, a2);\n if ( v2 )\n {\n v3 = strlen(a2);\n v4 = malloc(v3 + 1);\n __strcpy_chk(v4, a2, v3 + 1);\n return (char *)v4;\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1209(const char *a1, const char *a2) {\n char *v2;\n unsigned int v3;\n void *v4;\n v2 = strstr(a1, a2);\n if (v2) {\n v3 = strlen(a2);\n v4 = malloc(v3 + 1);\n __strcpy_chk(v4, a2, v3 + 1);\n return (char *)v4;\n }\n return v2;\n}", + "ida_pseudo_norm": "char *func0(const char *a1, const char *a2) {\n char *v2;\n unsigned int v3;\n void *v4;\n v2 = strstr(a1, a2);\n if (v2) {\n v3 = strlen(a2);\n v4 = malloc(v3 + 1);\n __strcpy_chk(v4, a2, v3 + 1);\n return (char *)v4;\n }\n return v2;\n}" + }, + { + "index": 607, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct MatchResult {\n\n char* pattern;\n\n int start;\n\n int end;\n\n} MatchResult;\n\n\n\n", + "func": "MatchResult func0(const char* text, const char* pattern) {\n MatchResult result;\n result.pattern = NULL;\n result.start = -1;\n result.end = -1;\n const char *start, *end;\n start = strstr(text, pattern);\n if (start != NULL) {\n end = start + strlen(pattern);\n result.pattern = (char*)malloc(strlen(pattern) + 1);\n strcpy(result.pattern, pattern);\n result.start = (int)(start - text);\n result.end = (int)(end - text);\n }\n return result;\n}", + "test": "int main() {\n\n MatchResult r1, r2, r3;\n\n \n\n r1 = func0(\"The quick brown fox jumps over the lazy dog.\", \"fox\");\n\n r2 = func0(\"Its been a very crazy procedure right\", \"crazy\");\n\n r3 = func0(\"Hardest choices required strongest will\", \"will\");\n\n \n\n assert(strcmp(r1.pattern, \"fox\") == 0 && r1.start == 16 && r1.end == 19);\n\n assert(strcmp(r2.pattern, \"crazy\") == 0 && r2.start == 16 && r2.end == 21);\n\n assert(strcmp(r3.pattern, \"will\") == 0 && r3.start == 35 && r3.end == 39);\n\n \n\n free(r1.pattern);\n\n free(r2.pattern);\n\n free(r3.pattern);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\nmov %rsi,%r13\npush %r12\npush %rbp\nmov %rdi,%rbp\npush %rbx\ncallq 10f0 \nmov %rax,%r12\ntest %rax,%rax\nje 13c0 \nmov %r13,%rdi\ncallq 10b0 \nlea 0x1(%rax),%r14\nmov %rax,%rbx\nmov %r14,%rdi\ncallq 10e0 \nmov %r14,%rdx\nmov %r13,%rsi\nmov %rax,%rdi\ncallq 10d0 \nlea (%r12,%rbx,1),%rdx\nmov %rax,%rcx\nmov %r12d,%eax\nsub %ebp,%edx\nsub %ebp,%eax\nmov %rcx,%r12\nshl $0x20,%rdx\npop %rbx\npop %rbp\nor %rax,%rdx\nmov %r12,%rax\npop %r12\npop %r13\npop %r14\nretq\nnopl 0x0(%rax,%rax,1)\nmov $0xffffffff,%edx\nmov $0xffffffff,%eax\njmp 13a5 \nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\nmov r13, rsi\npush r12\nmov r12, rdi\npush rbp\npush rbx\ncall _strstr\nmov rbp, rax\ntest rax, rax\njz short loc_13E0\nmov rdi, r13; s\ncall _strlen\nlea r14, [rax+1]\nmov rbx, rax\nmov rdi, r14; size\ncall _malloc\nmov rdx, r14\nmov rcx, r14\nmov rsi, r13\nmov rdi, rax\ncall ___memcpy_chk\nmov edx, ebp\nmov rdi, rax\nlea rax, [rbp+rbx+0]\nsub edx, r12d\nsub eax, r12d\nmov rbp, rdi\nloc_13CA:\nshl rax, 20h\npop rbx\nor rdx, rax\nmov rax, rbp\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_13E0:\nmov eax, 0FFFFFFFFh\nmov edx, 0FFFFFFFFh\njmp short loc_13CA", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, const char *a2)\n{\n char *v2; // rbp\n size_t v3; // r14\n void *v4; // rax\n\n v2 = strstr(a1, a2);\n if ( v2 )\n {\n v3 = strlen(a2) + 1;\n v4 = malloc(v3);\n return __memcpy_chk(v4, a2, v3, v3);\n }\n return (__int64)v2;\n}", + "ida_strip_asm": "sub_1370:\nendbr64\npush r14\npush r13\nmov r13, rsi\npush r12\nmov r12, rdi\npush rbp\npush rbx\ncall _strstr\nmov rbp, rax\ntest rax, rax\njz short loc_13E0\nmov rdi, r13; s\ncall _strlen\nlea r14, [rax+1]\nmov rbx, rax\nmov rdi, r14; size\ncall _malloc\nmov rdx, r14\nmov rcx, r14\nmov rsi, r13\nmov rdi, rax\ncall ___memcpy_chk\nmov edx, ebp\nmov rdi, rax\nlea rax, [rbp+rbx+0]\nsub edx, r12d\nsub eax, r12d\nmov rbp, rdi\nloc_13CA:\nshl rax, 20h\npop rbx\nor rdx, rax\nmov rax, rbp\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_13E0:\nmov eax, 0FFFFFFFFh\nmov edx, 0FFFFFFFFh\njmp short loc_13CA", + "ida_strip_pseudo": "__int64 __fastcall sub_1370(const char *a1, const char *a2)\n{\n char *v2; // rbp\n size_t v3; // r14\n void *v4; // rax\n\n v2 = strstr(a1, a2);\n if ( v2 )\n {\n v3 = strlen(a2) + 1;\n v4 = malloc(v3);\n return __memcpy_chk(v4, a2, v3, v3);\n }\n return (__int64)v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1370(const char *a1, const char *a2) {\n char *v2;\n unsigned int v3;\n void *v4;\n v2 = strstr(a1, a2);\n if (v2) {\n v3 = strlen(a2) + 1;\n v4 = malloc(v3);\n return __memcpy_chk(v4, a2, v3, v3);\n }\n return (long long)v2;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, const char *a2) {\n char *v2;\n unsigned int v3;\n void *v4;\n v2 = strstr(a1, a2);\n if (v2) {\n v3 = strlen(a2) + 1;\n v4 = malloc(v3);\n return __memcpy_chk(v4, a2, v3, v3);\n }\n return (long long)v2;\n}" + }, + { + "index": 607, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct MatchResult {\n\n char* pattern;\n\n int start;\n\n int end;\n\n} MatchResult;\n\n\n\n", + "func": "MatchResult func0(const char* text, const char* pattern) {\n MatchResult result;\n result.pattern = NULL;\n result.start = -1;\n result.end = -1;\n const char *start, *end;\n start = strstr(text, pattern);\n if (start != NULL) {\n end = start + strlen(pattern);\n result.pattern = (char*)malloc(strlen(pattern) + 1);\n strcpy(result.pattern, pattern);\n result.start = (int)(start - text);\n result.end = (int)(end - text);\n }\n return result;\n}", + "test": "int main() {\n\n MatchResult r1, r2, r3;\n\n \n\n r1 = func0(\"The quick brown fox jumps over the lazy dog.\", \"fox\");\n\n r2 = func0(\"Its been a very crazy procedure right\", \"crazy\");\n\n r3 = func0(\"Hardest choices required strongest will\", \"will\");\n\n \n\n assert(strcmp(r1.pattern, \"fox\") == 0 && r1.start == 16 && r1.end == 19);\n\n assert(strcmp(r2.pattern, \"crazy\") == 0 && r2.start == 16 && r2.end == 21);\n\n assert(strcmp(r3.pattern, \"will\") == 0 && r3.start == 35 && r3.end == 39);\n\n \n\n free(r1.pattern);\n\n free(r2.pattern);\n\n free(r3.pattern);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\nmov %rsi,%r13\npush %r12\npush %rbp\nmov %rdi,%rbp\npush %rbx\ncallq 10f0 \nmov %rax,%r12\ntest %rax,%rax\nje 13c0 \nmov %r13,%rdi\ncallq 10b0 \nlea 0x1(%rax),%r14\nmov %rax,%rbx\nmov %r14,%rdi\ncallq 10e0 \nmov %r14,%rdx\nmov %r13,%rsi\nmov %rax,%rdi\ncallq 10d0 \nlea (%r12,%rbx,1),%rdx\nmov %rax,%rcx\nmov %r12d,%eax\nsub %ebp,%edx\nsub %ebp,%eax\nmov %rcx,%r12\nshl $0x20,%rdx\npop %rbx\npop %rbp\nor %rax,%rdx\nmov %r12,%rax\npop %r12\npop %r13\npop %r14\nretq\nnopl 0x0(%rax,%rax,1)\nmov $0xffffffff,%edx\nmov $0xffffffff,%eax\njmp 13a5 \nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\nmov r13, rsi\npush r12\nmov r12, rdi\npush rbp\npush rbx\ncall _strstr\nmov rbp, rax\ntest rax, rax\njz short loc_13E0\nmov rdi, r13; s\ncall _strlen\nlea r14, [rax+1]\nmov rbx, rax\nmov rdi, r14; size\ncall _malloc\nmov rdx, r14\nmov rcx, r14\nmov rsi, r13\nmov rdi, rax\ncall ___memcpy_chk\nmov edx, ebp\nmov rdi, rax\nlea rax, [rbp+rbx+0]\nsub edx, r12d\nsub eax, r12d\nmov rbp, rdi\nloc_13CA:\nshl rax, 20h\npop rbx\nor rdx, rax\nmov rax, rbp\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_13E0:\nmov eax, 0FFFFFFFFh\nmov edx, 0FFFFFFFFh\njmp short loc_13CA", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, const char *a2)\n{\n char *v2; // rbp\n size_t v3; // r14\n void *v4; // rax\n\n v2 = strstr(a1, a2);\n if ( v2 )\n {\n v3 = strlen(a2) + 1;\n v4 = malloc(v3);\n return __memcpy_chk(v4, a2, v3, v3);\n }\n return (__int64)v2;\n}", + "ida_strip_asm": "sub_1370:\nendbr64\npush r14\npush r13\nmov r13, rsi\npush r12\nmov r12, rdi\npush rbp\npush rbx\ncall _strstr\nmov rbp, rax\ntest rax, rax\njz short loc_13E0\nmov rdi, r13; s\ncall _strlen\nlea r14, [rax+1]\nmov rbx, rax\nmov rdi, r14; size\ncall _malloc\nmov rdx, r14\nmov rcx, r14\nmov rsi, r13\nmov rdi, rax\ncall ___memcpy_chk\nmov edx, ebp\nmov rdi, rax\nlea rax, [rbp+rbx+0]\nsub edx, r12d\nsub eax, r12d\nmov rbp, rdi\nloc_13CA:\nshl rax, 20h\npop rbx\nor rdx, rax\nmov rax, rbp\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_13E0:\nmov eax, 0FFFFFFFFh\nmov edx, 0FFFFFFFFh\njmp short loc_13CA", + "ida_strip_pseudo": "__int64 __fastcall sub_1370(const char *a1, const char *a2)\n{\n char *v2; // rbp\n size_t v3; // r14\n void *v4; // rax\n\n v2 = strstr(a1, a2);\n if ( v2 )\n {\n v3 = strlen(a2) + 1;\n v4 = malloc(v3);\n return __memcpy_chk(v4, a2, v3, v3);\n }\n return (__int64)v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1370(const char *a1, const char *a2) {\n char *v2;\n unsigned int v3;\n void *v4;\n v2 = strstr(a1, a2);\n if (v2) {\n v3 = strlen(a2) + 1;\n v4 = malloc(v3);\n return __memcpy_chk(v4, a2, v3, v3);\n }\n return (long long)v2;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, const char *a2) {\n char *v2;\n unsigned int v3;\n void *v4;\n v2 = strstr(a1, a2);\n if (v2) {\n v3 = strlen(a2) + 1;\n v4 = malloc(v3);\n return __memcpy_chk(v4, a2, v3, v3);\n }\n return (long long)v2;\n}" + }, + { + "index": 608, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int bell[n + 1][n + 1];\n bell[0][0] = 1;\n for (int i = 1; i <= n; i++) {\n bell[i][0] = bell[i - 1][i - 1];\n for (int j = 1; j <= i; j++) {\n bell[i][j] = bell[i - 1][j - 1] + bell[i][j - 1];\n }\n }\n return bell[n][0];\n}", + "test": "int main() {\n\n assert(func0(2) == 2);\n\n assert(func0(3) == 5);\n\n assert(func0(4) == 15);\n\n\n\n printf(\"All assertions passed successfully.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0x58,%rsp\nmov %edi,-0x64(%rbp)\nmov %fs:0x28,%rbx\nmov %rbx,-0x38(%rbp)\nxor %ebx,%ebx\nmov %rsp,%rcx\nmov %rcx,%r15\nmov -0x64(%rbp),%ecx\nlea 0x1(%rcx),%esi\nmov -0x64(%rbp),%ecx\nlea 0x1(%rcx),%edi\nmovslq %esi,%rcx\nsub $0x1,%rcx\nmov %rcx,-0x50(%rbp)\nmovslq %esi,%rcx\nmov %rcx,-0x80(%rbp)\nmovq $0x0,-0x78(%rbp)\nmovslq %esi,%rcx\nshl $0x2,%rcx\nmovslq %edi,%rbx\nsub $0x1,%rbx\nmov %rbx,-0x48(%rbp)\nmovslq %esi,%rbx\nmov %rbx,%r12\nmov $0x0,%r13d\nmovslq %edi,%rbx\nmov %rbx,%rax\nmov $0x0,%edx\nmov %r13,%r14\nimul %rax,%r14\nmov %rdx,%rbx\nimul %r12,%rbx\nadd %r14,%rbx\nmul %r12\nadd %rdx,%rbx\nmov %rbx,%rdx\nmovslq %esi,%rax\nmov %rax,%r10\nmov $0x0,%r11d\nmovslq %edi,%rax\nmov %rax,%r8\nmov $0x0,%r9d\nmov %r11,%rdx\nimul %r8,%rdx\nmov %r9,%rax\nimul %r10,%rax\nlea (%rdx,%rax,1),%rbx\nmov %r10,%rax\nmul %r8\nlea (%rbx,%rdx,1),%r8\nmov %r8,%rdx\nmovslq %esi,%rdx\nmovslq %edi,%rax\nimul %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%ebx\nmov $0x0,%edx\ndiv %rbx\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rdi\nsub %rdx,%rdi\nmov %rdi,%rdx\ncmp %rdx,%rsp\nje 12af \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 1298 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 12d9 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x40(%rbp)\nmov -0x40(%rbp),%rax\nmovl $0x1,(%rax)\nmovl $0x1,-0x54(%rbp)\njmpq 13c9 \nmov %rcx,%r8\nshr $0x2,%r8\nmov -0x54(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x54(%rbp),%eax\nlea -0x1(%rax),%esi\nmov %rcx,%rdi\nshr $0x2,%rdi\nmov -0x40(%rbp),%rax\nmovslq %esi,%rsi\nmovslq %edx,%rdx\nimul %r8,%rdx\nadd %rsi,%rdx\nmov (%rax,%rdx,4),%esi\nmov -0x40(%rbp),%rax\nmov -0x54(%rbp),%edx\nmovslq %edx,%rdx\nimul %rdi,%rdx\nmov %esi,(%rax,%rdx,4)\nmovl $0x1,-0x58(%rbp)\njmp 13bd \nmov %rcx,%rdi\nshr $0x2,%rdi\nmov -0x54(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x58(%rbp),%eax\nlea -0x1(%rax),%esi\nmov -0x40(%rbp),%rax\nmovslq %esi,%rsi\nmovslq %edx,%rdx\nimul %rdi,%rdx\nadd %rsi,%rdx\nmov (%rax,%rdx,4),%edx\nmov %rcx,%r8\nshr $0x2,%r8\nmov -0x58(%rbp),%eax\nlea -0x1(%rax),%esi\nmov -0x40(%rbp),%rax\nmovslq %esi,%rdi\nmov -0x54(%rbp),%esi\nmovslq %esi,%rsi\nimul %r8,%rsi\nadd %rdi,%rsi\nmov (%rax,%rsi,4),%eax\nmov %rcx,%r8\nshr $0x2,%r8\nlea (%rdx,%rax,1),%esi\nmov -0x40(%rbp),%rax\nmov -0x58(%rbp),%edx\nmovslq %edx,%rdi\nmov -0x54(%rbp),%edx\nmovslq %edx,%rdx\nimul %r8,%rdx\nadd %rdi,%rdx\nmov %esi,(%rax,%rdx,4)\naddl $0x1,-0x58(%rbp)\nmov -0x58(%rbp),%eax\ncmp -0x54(%rbp),%eax\njle 134a \naddl $0x1,-0x54(%rbp)\nmov -0x54(%rbp),%eax\ncmp -0x64(%rbp),%eax\njle 1302 \nshr $0x2,%rcx\nmov -0x40(%rbp),%rax\nmov -0x64(%rbp),%edx\nmovslq %edx,%rdx\nimul %rcx,%rdx\nmov (%rax,%rdx,4),%eax\nmov %r15,%rsp\nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\nje 1401 \ncallq 1080 <__stack_chk_fail@plt>\nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 48h\nmov [rbp+var_44], edi\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov rax, rsp\nmov r11, rax\nmov eax, [rbp+var_44]\nlea edi, [rax+1]\nmov eax, [rbp+var_44]\nlea r8d, [rax+1]\nmovsxd rax, edi\nsub rax, 1\nmov [rbp+var_30], rax\nmovsxd rax, edi\nlea rsi, ds:0[rax*4]\nmovsxd rax, r8d\nsub rax, 1\nmov [rbp+var_28], rax\nmovsxd rax, edi\nmov rcx, rax\nmov ebx, 0\nmovsxd rax, r8d\nmov rax, rax\nmov edx, 0\nmov r10, rbx\nimul r10, rax\nmov r9, rdx\nimul r9, rcx\nadd r9, r10\nmul rcx\nlea rcx, [r9+rdx]\nmov rdx, rcx\nmovsxd rax, edi\nmov rcx, rax\nmov ebx, 0\nmovsxd rax, r8d\nmov rax, rax\nmov edx, 0\nmov r10, rbx\nimul r10, rax\nmov r9, rdx\nimul r9, rcx\nadd r9, r10\nmul rcx\nlea rcx, [r9+rdx]\nmov rdx, rcx\nmovsxd rdx, edi\nmovsxd rax, r8d\nimul rax, rdx\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov ebx, 10h\nmov edx, 0\ndiv rbx\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_127D:\ncmp rsp, rdx\njz short loc_1294\nsub rsp, 1000h\nor [rsp+1050h+var_58], 0\njmp short loc_127D\nloc_1294:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_12BE\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_12BE:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_20], rax\nmov rax, [rbp+var_20]\nmov dword ptr [rax], 1\nmov [rbp+var_38], 1\njmp loc_13AD\nloc_12E7:\nmov r8, rsi\nshr r8, 2\nmov eax, [rbp+var_38]\nlea edx, [rax-1]\nmov eax, [rbp+var_38]\nlea ecx, [rax-1]\nmov rdi, rsi\nshr rdi, 2\nmov rax, [rbp+var_20]\nmovsxd rcx, ecx\nmovsxd rdx, edx\nimul rdx, r8\nadd rdx, rcx\nmov ecx, [rax+rdx*4]\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nimul rdx, rdi\nmov [rax+rdx*4], ecx\nmov [rbp+var_34], 1\njmp short loc_13A1\nloc_132F:\nmov rdi, rsi\nshr rdi, 2\nmov eax, [rbp+var_38]\nlea edx, [rax-1]\nmov eax, [rbp+var_34]\nlea ecx, [rax-1]\nmov rax, [rbp+var_20]\nmovsxd rcx, ecx\nmovsxd rdx, edx\nimul rdx, rdi\nadd rdx, rcx\nmov ecx, [rax+rdx*4]\nmov r8, rsi\nshr r8, 2\nmov eax, [rbp+var_34]\nlea edx, [rax-1]\nmov rax, [rbp+var_20]\nmovsxd rdi, edx\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nimul rdx, r8\nadd rdx, rdi\nmov eax, [rax+rdx*4]\nmov r8, rsi\nshr r8, 2\nadd ecx, eax\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_34]\nmovsxd rdi, edx\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nimul rdx, r8\nadd rdx, rdi\nmov [rax+rdx*4], ecx\nadd [rbp+var_34], 1\nloc_13A1:\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_38]\njle short loc_132F\nadd [rbp+var_38], 1\nloc_13AD:\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_44]\njle loc_12E7\nshr rsi, 2\nmov rcx, rsi\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_44]\nmovsxd rdx, edx\nimul rdx, rcx\nmov eax, [rax+rdx*4]\nmov rsp, r11\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njz short loc_13E8\ncall ___stack_chk_fail\nloc_13E8:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // edi\n unsigned __int64 v2; // rsi\n unsigned __int64 v3; // rax\n void *v4; // rsp\n _DWORD v6[3]; // [rsp+8h] [rbp-50h] BYREF\n int v7; // [rsp+14h] [rbp-44h]\n int i; // [rsp+20h] [rbp-38h]\n int j; // [rsp+24h] [rbp-34h]\n __int64 v10; // [rsp+28h] [rbp-30h]\n __int64 v11; // [rsp+30h] [rbp-28h]\n _DWORD *v12; // [rsp+38h] [rbp-20h]\n unsigned __int64 v13; // [rsp+40h] [rbp-18h]\n\n v7 = a1;\n v13 = __readfsqword(0x28u);\n v1 = a1 + 1;\n v10 = v1 - 1LL;\n v2 = 4LL * v1;\n v11 = v7 + 1 - 1LL;\n v3 = 16 * ((4 * v1 * (__int64)(v7 + 1) + 15) / 0x10uLL);\n while ( v6 != (_DWORD *)((char *)v6 - (v3 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v4 = alloca(v3 & 0xFFF);\n if ( (v3 & 0xFFF) != 0 )\n *(_QWORD *)((char *)&v6[-2] + (v3 & 0xFFF)) = *(_QWORD *)((char *)&v6[-2] + (v3 & 0xFFF));\n v12 = v6;\n v6[0] = 1;\n for ( i = 1; i <= v7; ++i )\n {\n v12[(v2 >> 2) * i] = v12[i - 1 + (v2 >> 2) * (i - 1)];\n for ( j = 1; j <= i; ++j )\n v12[j + (v2 >> 2) * i] = v12[j - 1 + (v2 >> 2) * i] + v12[j - 1 + (v2 >> 2) * (i - 1)];\n }\n return (unsigned int)v12[(v2 >> 2) * v7];\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 48h\nmov [rbp+var_44], edi\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov rax, rsp\nmov r11, rax\nmov eax, [rbp+var_44]\nlea edi, [rax+1]\nmov eax, [rbp+var_44]\nlea r8d, [rax+1]\nmovsxd rax, edi\nsub rax, 1\nmov [rbp+var_30], rax\nmovsxd rax, edi\nlea rsi, ds:0[rax*4]\nmovsxd rax, r8d\nsub rax, 1\nmov [rbp+var_28], rax\nmovsxd rax, edi\nmov rcx, rax\nmov ebx, 0\nmovsxd rax, r8d\nmov rax, rax\nmov edx, 0\nmov r10, rbx\nimul r10, rax\nmov r9, rdx\nimul r9, rcx\nadd r9, r10\nmul rcx\nlea rcx, [r9+rdx]\nmov rdx, rcx\nmovsxd rax, edi\nmov rcx, rax\nmov ebx, 0\nmovsxd rax, r8d\nmov rax, rax\nmov edx, 0\nmov r10, rbx\nimul r10, rax\nmov r9, rdx\nimul r9, rcx\nadd r9, r10\nmul rcx\nlea rcx, [r9+rdx]\nmov rdx, rcx\nmovsxd rdx, edi\nmovsxd rax, r8d\nimul rax, rdx\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov ebx, 10h\nmov edx, 0\ndiv rbx\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_127D:\ncmp rsp, rdx\njz short loc_1294\nsub rsp, 1000h\nor [rsp+1050h+var_58], 0\njmp short loc_127D\nloc_1294:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_12BE\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_12BE:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_20], rax\nmov rax, [rbp+var_20]\nmov dword ptr [rax], 1\nmov [rbp+var_38], 1\njmp loc_13AD\nloc_12E7:\nmov r8, rsi\nshr r8, 2\nmov eax, [rbp+var_38]\nlea edx, [rax-1]\nmov eax, [rbp+var_38]\nlea ecx, [rax-1]\nmov rdi, rsi\nshr rdi, 2\nmov rax, [rbp+var_20]\nmovsxd rcx, ecx\nmovsxd rdx, edx\nimul rdx, r8\nadd rdx, rcx\nmov ecx, [rax+rdx*4]\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nimul rdx, rdi\nmov [rax+rdx*4], ecx\nmov [rbp+var_34], 1\njmp short loc_13A1\nloc_132F:\nmov rdi, rsi\nshr rdi, 2\nmov eax, [rbp+var_38]\nlea edx, [rax-1]\nmov eax, [rbp+var_34]\nlea ecx, [rax-1]\nmov rax, [rbp+var_20]\nmovsxd rcx, ecx\nmovsxd rdx, edx\nimul rdx, rdi\nadd rdx, rcx\nmov ecx, [rax+rdx*4]\nmov r8, rsi\nshr r8, 2\nmov eax, [rbp+var_34]\nlea edx, [rax-1]\nmov rax, [rbp+var_20]\nmovsxd rdi, edx\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nimul rdx, r8\nadd rdx, rdi\nmov eax, [rax+rdx*4]\nmov r8, rsi\nshr r8, 2\nadd ecx, eax\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_34]\nmovsxd rdi, edx\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nimul rdx, r8\nadd rdx, rdi\nmov [rax+rdx*4], ecx\nadd [rbp+var_34], 1\nloc_13A1:\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_38]\njle short loc_132F\nadd [rbp+var_38], 1\nloc_13AD:\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_44]\njle loc_12E7\nshr rsi, 2\nmov rcx, rsi\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_44]\nmovsxd rdx, edx\nimul rdx, rcx\nmov eax, [rax+rdx*4]\nmov rsp, r11\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njz short loc_13E8\ncall ___stack_chk_fail\nloc_13E8:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(int a1)\n{\n int v1; // edi\n unsigned __int64 v2; // rsi\n unsigned __int64 v3; // rax\n void *v4; // rsp\n _DWORD v6[3]; // [rsp+8h] [rbp-50h] BYREF\n int v7; // [rsp+14h] [rbp-44h]\n int i; // [rsp+20h] [rbp-38h]\n int j; // [rsp+24h] [rbp-34h]\n __int64 v10; // [rsp+28h] [rbp-30h]\n __int64 v11; // [rsp+30h] [rbp-28h]\n _DWORD *v12; // [rsp+38h] [rbp-20h]\n unsigned __int64 v13; // [rsp+40h] [rbp-18h]\n\n v7 = a1;\n v13 = __readfsqword(0x28u);\n v1 = a1 + 1;\n v10 = v1 - 1LL;\n v2 = 4LL * v1;\n v11 = v7 + 1 - 1LL;\n v3 = 16 * ((4 * v1 * (__int64)(v7 + 1) + 15) / 0x10uLL);\n while ( v6 != (_DWORD *)((char *)v6 - (v3 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v4 = alloca(v3 & 0xFFF);\n if ( (v3 & 0xFFF) != 0 )\n *(_QWORD *)((char *)&v6[-2] + (v3 & 0xFFF)) = *(_QWORD *)((char *)&v6[-2] + (v3 & 0xFFF));\n v12 = v6;\n v6[0] = 1;\n for ( i = 1; i <= v7; ++i )\n {\n v12[(v2 >> 2) * i] = v12[i - 1 + (v2 >> 2) * (i - 1)];\n for ( j = 1; j <= i; ++j )\n v12[j + (v2 >> 2) * i] = v12[j - 1 + (v2 >> 2) * i] + v12[j - 1 + (v2 >> 2) * (i - 1)];\n }\n return (unsigned int)v12[(v2 >> 2) * v7];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(int a1) {\n int v1;\n unsigned long long v2;\n unsigned long long v3;\n void *v4;\n uint32_t v6[3];\n int v7;\n int i;\n int j;\n long long v10;\n long long v11;\n uint32_t *v12;\n unsigned long long v13;\n v7 = a1;\n v13 = __readfsqword(40u);\n v1 = a1 + 1;\n v10 = v1 - 1LL;\n v2 = 4LL * v1;\n v11 = v7 + 1 - 1LL;\n v3 = 16 * ((4 * v1 * (long long)(v7 + 1) + 15) / 16uLL);\n while (v6 != (uint32_t *)((char *)v6 - (v3 & 18446744073709547520LL)))\n ;\n v4 = alloca(v3 & 4095);\n if ((v3 & 4095) != 0)\n *(uint64_t *)((char *)&v6[-2] + (v3 & 4095)) =\n *(uint64_t *)((char *)&v6[-2] + (v3 & 4095));\n v12 = v6;\n v6[0] = 1;\n for (i = 1; i <= v7; ++i) {\n v12[(v2 >> 2) * i] = v12[i - 1 + (v2 >> 2) * (i - 1)];\n for (j = 1; j <= i; ++j)\n v12[j + (v2 >> 2) * i] =\n v12[j - 1 + (v2 >> 2) * i] + v12[j - 1 + (v2 >> 2) * (i - 1)];\n }\n return (unsigned int)v12[(v2 >> 2) * v7];\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n unsigned long long v2;\n unsigned long long v3;\n void *v4;\n uint32_t v6[3];\n int v7;\n int i;\n int j;\n long long v10;\n long long v11;\n uint32_t *v12;\n unsigned long long v13;\n v7 = a1;\n v13 = __readfsqword(40u);\n v1 = a1 + 1;\n v10 = v1 - 1LL;\n v2 = 4LL * v1;\n v11 = v7 + 1 - 1LL;\n v3 = 16 * ((4 * v1 * (long long)(v7 + 1) + 15) / 16uLL);\n while (v6 != (uint32_t *)((char *)v6 - (v3 & 18446744073709547520LL)))\n ;\n v4 = alloca(v3 & 4095);\n if ((v3 & 4095) != 0)\n *(uint64_t *)((char *)&v6[-2] + (v3 & 4095)) =\n *(uint64_t *)((char *)&v6[-2] + (v3 & 4095));\n v12 = v6;\n v6[0] = 1;\n for (i = 1; i <= v7; ++i) {\n v12[(v2 >> 2) * i] = v12[i - 1 + (v2 >> 2) * (i - 1)];\n for (j = 1; j <= i; ++j)\n v12[j + (v2 >> 2) * i] =\n v12[j - 1 + (v2 >> 2) * i] + v12[j - 1 + (v2 >> 2) * (i - 1)];\n }\n return (unsigned int)v12[(v2 >> 2) * v7];\n}" + }, + { + "index": 608, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int bell[n + 1][n + 1];\n bell[0][0] = 1;\n for (int i = 1; i <= n; i++) {\n bell[i][0] = bell[i - 1][i - 1];\n for (int j = 1; j <= i; j++) {\n bell[i][j] = bell[i - 1][j - 1] + bell[i][j - 1];\n }\n }\n return bell[n][0];\n}", + "test": "int main() {\n\n assert(func0(2) == 2);\n\n assert(func0(3) == 5);\n\n assert(func0(4) == 15);\n\n\n\n printf(\"All assertions passed successfully.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0x28,%rsp\nmov %edi,%eax\nmov %edi,-0x44(%rbp)\nmov %fs:0x28,%rbx\nmov %rbx,-0x38(%rbp)\nxor %ebx,%ebx\nadd $0x1,%eax\ncltq\nlea 0x0(,%rax,4),%rbx\nimul %rax,%rax\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffffff0,%rdx\nand $0xfffffffffffff000,%rax\nmov %rsp,%rdi\nsub %rax,%rdi\nmov %rdi,%rax\ncmp %rax,%rsp\nje 11f8 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11e1 \nmov %rdx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 120e \norq $0x0,-0x8(%rsp,%rax,1)\nlea 0x3(%rsp),%r15\nmov %r15,%rax\nshr $0x2,%rax\nand $0xfffffffffffffffc,%r15\nmov %r15,%r11\nmov %rbx,%r10\nshr $0x2,%r10\nmovl $0x1,0x0(,%rax,4)\nmov -0x44(%rbp),%eax\ntest %eax,%eax\njle 12ac \nlea (%r15,%rbx,1),%r9\nlea 0x4(%rbx),%r13\nlea (%r15,%r13,1),%rsi\nlea -0x1(%rax),%r12d\nadd $0x2,%r12\nmov $0x1,%edi\nmov $0x0,%r8d\nlea 0x1(%r10),%r14\njmp 1272 \nadd $0x1,%r8\nadd $0x1,%rdi\nadd %rbx,%r9\nadd %r13,%rsi\ncmp %r12,%rdi\nje 12ac \nmovslq %r8d,%rax\nimul %r14,%rax\nmov (%r11,%rax,4),%edx\nmovslq %edi,%rax\nimul %r10,%rax\nmov %edx,(%r11,%rax,4)\ntest %edi,%edi\njle 125f \nmov %r8,%rcx\nsub %rdi,%rcx\nimul %r10,%rcx\nmov %r9,%rax\nmov (%rax),%edx\nadd (%rax,%rcx,4),%edx\nmov %edx,0x4(%rax)\nadd $0x4,%rax\ncmp %rsi,%rax\njne 1299 \njmp 125f \nmovslq -0x44(%rbp),%rax\nimul %rax,%r10\nmov (%r15,%r10,4),%eax\nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\njne 12d6 \nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\ncallq 1080 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 18h\nmov r12d, edi\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nlea eax, [rdi+1]\ncdqe\nlea rbx, ds:0[rax*4]\nimul rax, rax\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11DC:\ncmp rsp, rdx\njz short loc_11F3\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_11DC\nloc_11F3:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_1209\nor [rsp+rax+40h+var_48], 0\nloc_1209:\nlea r10, [rsp+40h+var_3D]\nmov rax, r10\nshr rax, 2\nand r10, 0FFFFFFFFFFFFFFFCh\nmov r11, rbx\nshr r11, 2\nmov ds:dword_0[rax*4], 1\ntest r12d, r12d\njle short loc_129B\nlea r9, [r10+rbx]\nlea r13, [rbx+4]\nlea rsi, [r10+r13]\nlea r15d, [r12+1]\nmov edi, 1\nmov r8d, 0\nlea r14, [r11+1]\nloc_1250:\nmovsxd rax, r8d\nimul rax, r14\nmov edx, [r10+rax*4]\nmovsxd rax, edi\nimul rax, r11\nmov [r10+rax*4], edx\ntest edi, edi\njle short loc_12C4\nmov rcx, r8\nsub rcx, rdi\nimul rcx, r11\nmov rax, r9\nloc_1277:\nmov edx, [rax]\nadd edx, [rax+rcx*4]\nmov [rax+4], edx\nadd rax, 4\ncmp rax, rsi\njnz short loc_1277\nadd r8, 1\nadd rdi, 1\nadd r9, rbx\nadd rsi, r13\ncmp rdi, r15\njnz short loc_1250\nloc_129B:\nmovsxd r12, r12d\nimul r12, r11\nmov eax, [r10+r12*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_12D7\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_12C4:\nadd r8, 1\nadd rdi, 1\nadd r9, rbx\nadd rsi, r13\njmp loc_1250\nloc_12D7:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n __int64 v2; // rax\n unsigned __int64 v3; // rbx\n __int64 v4; // rax\n __int16 v5; // cx\n signed __int64 v6; // rax\n void *v7; // rsp\n unsigned __int64 v8; // r11\n _DWORD *v9; // r9\n unsigned __int64 v10; // r13\n _DWORD *v11; // rsi\n __int64 v12; // r15\n __int64 v13; // rdi\n __int64 v14; // r8\n _DWORD *v15; // rax\n _DWORD v18[2]; // [rsp+8h] [rbp-40h] BYREF\n unsigned __int64 v19; // [rsp+10h] [rbp-38h]\n\n v19 = __readfsqword(0x28u);\n v2 = a1 + 1;\n v3 = 4 * v2;\n v4 = 4 * v2 * v2 + 15;\n v5 = v4 & 0xFFF0;\n while ( v18 != (_DWORD *)((char *)v18 - (v4 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v6 = v4 & 0xFF0;\n v7 = alloca(v6);\n if ( (v5 & 0xFFF) != 0 )\n *(_QWORD *)((char *)&v18[-2] + v6) = *(_QWORD *)((char *)&v18[-2] + v6);\n v8 = v3 >> 2;\n v18[0] = 1;\n if ( a1 > 0 )\n {\n v9 = &v18[v3 / 4];\n v10 = v3 + 4;\n v11 = &v18[v3 / 4 + 1];\n v12 = (unsigned int)(a1 + 1);\n v13 = 1LL;\n v14 = 0LL;\n do\n {\n while ( 1 )\n {\n v18[v8 * (int)v13] = v18[(v8 + 1) * (int)v14];\n if ( (int)v13 > 0 )\n break;\n ++v14;\n ++v13;\n v9 = (_DWORD *)((char *)v9 + v3);\n v11 = (_DWORD *)((char *)v11 + v10);\n }\n v15 = v9;\n do\n {\n v15[1] = v15[v8 * (v14 - v13)] + *v15;\n ++v15;\n }\n while ( v15 != v11 );\n ++v14;\n ++v13;\n v9 = (_DWORD *)((char *)v9 + v3);\n v11 = (_DWORD *)((char *)v11 + v10);\n }\n while ( v13 != v12 );\n }\n return (unsigned int)v18[v8 * a1];\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 18h\nmov r12d, edi\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nlea eax, [rdi+1]\ncdqe\nlea rbx, ds:0[rax*4]\nimul rax, rax\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11DC:\ncmp rsp, rdx\njz short loc_11F3\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_11DC\nloc_11F3:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_1209\nor [rsp+rax+40h+var_48], 0\nloc_1209:\nlea r10, [rsp+40h+var_3D]\nmov rax, r10\nshr rax, 2\nand r10, 0FFFFFFFFFFFFFFFCh\nmov r11, rbx\nshr r11, 2\nmov ds:dword_0[rax*4], 1\ntest r12d, r12d\njle short loc_129B\nlea r9, [r10+rbx]\nlea r13, [rbx+4]\nlea rsi, [r10+r13]\nlea r15d, [r12+1]\nmov edi, 1\nmov r8d, 0\nlea r14, [r11+1]\nloc_1250:\nmovsxd rax, r8d\nimul rax, r14\nmov edx, [r10+rax*4]\nmovsxd rax, edi\nimul rax, r11\nmov [r10+rax*4], edx\ntest edi, edi\njle short loc_12C4\nmov rcx, r8\nsub rcx, rdi\nimul rcx, r11\nmov rax, r9\nloc_1277:\nmov edx, [rax]\nadd edx, [rax+rcx*4]\nmov [rax+4], edx\nadd rax, 4\ncmp rax, rsi\njnz short loc_1277\nadd r8, 1\nadd rdi, 1\nadd r9, rbx\nadd rsi, r13\ncmp rdi, r15\njnz short loc_1250\nloc_129B:\nmovsxd r12, r12d\nimul r12, r11\nmov eax, [r10+r12*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_12D7\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_12C4:\nadd r8, 1\nadd rdi, 1\nadd r9, rbx\nadd rsi, r13\njmp loc_1250\nloc_12D7:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(int a1)\n{\n __int64 v2; // rax\n unsigned __int64 v3; // rbx\n __int64 v4; // rax\n __int16 v5; // cx\n signed __int64 v6; // rax\n void *v7; // rsp\n unsigned __int64 v8; // r11\n _DWORD *v9; // r9\n unsigned __int64 v10; // r13\n _DWORD *v11; // rsi\n __int64 v12; // r15\n __int64 v13; // rdi\n __int64 v14; // r8\n _DWORD *v15; // rax\n _DWORD v18[2]; // [rsp+8h] [rbp-40h] BYREF\n unsigned __int64 v19; // [rsp+10h] [rbp-38h]\n\n v19 = __readfsqword(0x28u);\n v2 = a1 + 1;\n v3 = 4 * v2;\n v4 = 4 * v2 * v2 + 15;\n v5 = v4 & 0xFFF0;\n while ( v18 != (_DWORD *)((char *)v18 - (v4 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v6 = v4 & 0xFF0;\n v7 = alloca(v6);\n if ( (v5 & 0xFFF) != 0 )\n *(_QWORD *)((char *)&v18[-2] + v6) = *(_QWORD *)((char *)&v18[-2] + v6);\n v8 = v3 >> 2;\n v18[0] = 1;\n if ( a1 > 0 )\n {\n v9 = &v18[v3 / 4];\n v10 = v3 + 4;\n v11 = &v18[v3 / 4 + 1];\n v12 = (unsigned int)(a1 + 1);\n v13 = 1LL;\n v14 = 0LL;\n do\n {\n while ( 1 )\n {\n v18[v8 * (int)v13] = v18[(v8 + 1) * (int)v14];\n if ( (int)v13 > 0 )\n break;\n ++v14;\n ++v13;\n v9 = (_DWORD *)((char *)v9 + v3);\n v11 = (_DWORD *)((char *)v11 + v10);\n }\n v15 = v9;\n do\n {\n v15[1] = v15[v8 * (v14 - v13)] + *v15;\n ++v15;\n }\n while ( v15 != v11 );\n ++v14;\n ++v13;\n v9 = (_DWORD *)((char *)v9 + v3);\n v11 = (_DWORD *)((char *)v11 + v10);\n }\n while ( v13 != v12 );\n }\n return (unsigned int)v18[v8 * a1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(int a1) {\n long long v2;\n unsigned long long v3;\n long long v4;\n short v5;\n signed long long v6;\n void *v7;\n unsigned long long v8;\n uint32_t *v9;\n unsigned long long v10;\n uint32_t *v11;\n long long v12;\n long long v13;\n long long v14;\n uint32_t *v15;\n uint32_t v18[2];\n unsigned long long v19;\n v19 = __readfsqword(40u);\n v2 = a1 + 1;\n v3 = 4 * v2;\n v4 = 4 * v2 * v2 + 15;\n v5 = v4 & 65520;\n while (v18 != (uint32_t *)((char *)v18 - (v4 & 18446744073709547520LL)))\n ;\n v6 = v4 & 4080;\n v7 = alloca(v6);\n if ((v5 & 4095) != 0)\n *(uint64_t *)((char *)&v18[-2] + v6) = *(uint64_t *)((char *)&v18[-2] + v6);\n v8 = v3 >> 2;\n v18[0] = 1;\n if (a1 > 0) {\n v9 = &v18[v3 / 4];\n v10 = v3 + 4;\n v11 = &v18[v3 / 4 + 1];\n v12 = (unsigned int)(a1 + 1);\n v13 = 1LL;\n v14 = 0LL;\n do {\n while (1) {\n v18[v8 * (int)v13] = v18[(v8 + 1) * (int)v14];\n if ((int)v13 > 0) break;\n ++v14;\n ++v13;\n v9 = (uint32_t *)((char *)v9 + v3);\n v11 = (uint32_t *)((char *)v11 + v10);\n }\n v15 = v9;\n do {\n v15[1] = v15[v8 * (v14 - v13)] + *v15;\n ++v15;\n } while (v15 != v11);\n ++v14;\n ++v13;\n v9 = (uint32_t *)((char *)v9 + v3);\n v11 = (uint32_t *)((char *)v11 + v10);\n } while (v13 != v12);\n }\n return (unsigned int)v18[v8 * a1];\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n long long v2;\n unsigned long long v3;\n long long v4;\n short v5;\n signed long long v6;\n void *v7;\n unsigned long long v8;\n uint32_t *v9;\n unsigned long long v10;\n uint32_t *v11;\n long long v12;\n long long v13;\n long long v14;\n uint32_t *v15;\n uint32_t v18[2];\n unsigned long long v19;\n v19 = __readfsqword(40u);\n v2 = a1 + 1;\n v3 = 4 * v2;\n v4 = 4 * v2 * v2 + 15;\n v5 = v4 & 65520;\n while (v18 != (uint32_t *)((char *)v18 - (v4 & 18446744073709547520LL)))\n ;\n v6 = v4 & 4080;\n v7 = alloca(v6);\n if ((v5 & 4095) != 0)\n *(uint64_t *)((char *)&v18[-2] + v6) = *(uint64_t *)((char *)&v18[-2] + v6);\n v8 = v3 >> 2;\n v18[0] = 1;\n if (a1 > 0) {\n v9 = &v18[v3 / 4];\n v10 = v3 + 4;\n v11 = &v18[v3 / 4 + 1];\n v12 = (unsigned int)(a1 + 1);\n v13 = 1LL;\n v14 = 0LL;\n do {\n while (1) {\n v18[v8 * (int)v13] = v18[(v8 + 1) * (int)v14];\n if ((int)v13 > 0) break;\n ++v14;\n ++v13;\n v9 = (uint32_t *)((char *)v9 + v3);\n v11 = (uint32_t *)((char *)v11 + v10);\n }\n v15 = v9;\n do {\n v15[1] = v15[v8 * (v14 - v13)] + *v15;\n ++v15;\n } while (v15 != v11);\n ++v14;\n ++v13;\n v9 = (uint32_t *)((char *)v9 + v3);\n v11 = (uint32_t *)((char *)v11 + v10);\n } while (v13 != v12);\n }\n return (unsigned int)v18[v8 * a1];\n}" + }, + { + "index": 608, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int bell[n + 1][n + 1];\n bell[0][0] = 1;\n for (int i = 1; i <= n; i++) {\n bell[i][0] = bell[i - 1][i - 1];\n for (int j = 1; j <= i; j++) {\n bell[i][j] = bell[i - 1][j - 1] + bell[i][j - 1];\n }\n }\n return bell[n][0];\n}", + "test": "int main() {\n\n assert(func0(2) == 2);\n\n assert(func0(3) == 5);\n\n assert(func0(4) == 15);\n\n\n\n printf(\"All assertions passed successfully.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\nmovslq %edi,%r14\npush %r13\npush %r12\npush %rbx\nsub $0x18,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nlea 0x1(%r14),%eax\nmov %rsp,%rbx\ncltq\nlea 0x0(,%rax,4),%r12\nimul %rax,%rax\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rbx\nand $0xfffffffffffffff0,%rdx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 1451 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 143c \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 1526 \nlea 0x3(%rsp),%rdi\nmov %r12,%r11\nmov %rdi,%rax\nshr $0x2,%r11\nand $0xfffffffffffffffc,%rdi\nshr $0x2,%rax\nmovl $0x1,0x0(,%rax,4)\ntest %r14d,%r14d\njle 1500 \nlea -0x1(%r14),%ebx\nxor %r9d,%r9d\nlea 0x1(%r11),%r15\nmov $0x1,%edx\nlea 0x4(%r12),%r13\nadd $0x2,%rbx\nmov $0x1,%r8d\nlea (%rdi,%r13,1),%r10\nmov %r10,%rsi\nmovslq %r8d,%rax\nmov %r9,%rcx\nimul %r11,%rax\nsub %r8,%rcx\nimul %r11,%rcx\nmov %edx,(%rdi,%rax,4)\nmov %r10,%rax\njmp 14d4 \nnopl 0x0(%rax)\nadd $0x4,%rax\nadd -0x4(%rax,%rcx,4),%edx\nmov %edx,(%rax)\ncmp %rsi,%rax\njne 14d0 \nadd $0x1,%r8\nadd $0x1,%r9\nadd %r12,%r10\nadd %r13,%rsi\ncmp %rbx,%r8\nje 1500 \nmovslq %r9d,%rax\nimul %r15,%rax\nmov (%rdi,%rax,4),%edx\njmp 14b0 \nxchg %ax,%ax\nimul %r14,%r11\nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\nmov (%rdi,%r11,4),%eax\njne 1531 \nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 1463 \ncallq 1080 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\nmov r12d, edi\npush rbx\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nlea eax, [rdi+1]\nmov rcx, rsp\ncdqe\nlea rbx, ds:0[rax*4]\nimul rax, rax\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_12AD\nloc_1298:\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\ncmp rsp, rcx\njnz short loc_1298\nloc_12AD:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1389\nloc_12BF:\nlea r11, [rsp+1040h+var_103D]\nmov r10, rbx\nmov rax, r11\nshr r10, 2\nand r11, 0FFFFFFFFFFFFFFFCh\nshr rax, 2\nmov ds:dword_0[rax*4], 1\ntest r12d, r12d\njle short loc_1360\nmov r8, r11\nlea r14, [rbx+4]\nlea rsi, [r11+4]\nmov r13d, r12d\nmov r9d, 1\nxor edi, edi\nlea r15, [r10+1]\nmov edx, 1\nnop dword ptr [rax]\nloc_1308:\nmovsxd rax, r9d\nmov rcx, r9\nimul rax, r10\nsub rcx, rdi\nimul rcx, r10\nmov [r11+rax*4], edx\nmov edx, [r8+r10*4]\nmov rax, r8\nnop dword ptr [rax+00h]\nloc_1328:\nadd edx, [rax]\nmov [rax+rcx*4+4], edx\nadd rax, 4\ncmp rax, rsi\njnz short loc_1328\nadd rdi, 1\nadd r8, rbx\nadd rsi, r14\ncmp rdi, r13\njz short loc_1360\nmovsxd rax, edi\nadd r9, 1\nimul rax, r15\nmov edx, [r11+rax*4]\njmp short loc_1308\nloc_1360:\nmovsxd r12, r12d\nimul r12, r10\nmov eax, [r11+r12*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_1394\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1389:\nor [rsp+rdx+1040h+var_1048], 0\njmp loc_12BF\nloc_1394:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n __int64 v2; // rax\n unsigned __int64 v3; // rbx\n __int64 v4; // rdx\n int *v5; // rcx\n __int16 v6; // dx\n signed __int64 v7; // rdx\n void *v8; // rsp\n unsigned __int64 v9; // r10\n int *v10; // r8\n int *v11; // rsi\n __int64 v12; // r9\n __int64 v13; // rdi\n int i; // edx\n int v15; // edx\n int *v16; // rax\n __int64 v18; // [rsp+0h] [rbp-1048h]\n int v19; // [rsp+8h] [rbp-1040h] BYREF\n int v20; // [rsp+Ch] [rbp-103Ch] BYREF\n _QWORD v21[8]; // [rsp+1008h] [rbp-40h] BYREF\n\n v21[1] = __readfsqword(0x28u);\n v2 = a1 + 1;\n v3 = 4 * v2;\n v4 = 4 * v2 * v2 + 15;\n v5 = (int *)((char *)v21 - (v4 & 0xFFFFFFFFFFFFF000LL));\n v6 = v4 & 0xFFF0;\n if ( v21 != (_QWORD *)v5 )\n {\n while ( &v19 != v5 )\n ;\n }\n v7 = v6 & 0xFFF;\n v8 = alloca(v7);\n if ( v7 )\n *(__int64 *)((char *)&v18 + v7) = *(__int64 *)((char *)&v18 + v7);\n v9 = v3 >> 2;\n v19 = 1;\n if ( a1 > 0 )\n {\n v10 = &v19;\n v11 = &v20;\n v12 = 1LL;\n v13 = 0LL;\n for ( i = 1; ; i = *(&v19 + (v9 + 1) * (int)v13) )\n {\n *(&v19 + v9 * (int)v12) = i;\n v15 = v10[v9];\n v16 = v10;\n do\n {\n v15 += *v16;\n v16[v9 * (v12 - v13) + 1] = v15;\n ++v16;\n }\n while ( v16 != v11 );\n ++v13;\n v10 = (int *)((char *)v10 + v3);\n v11 = (int *)((char *)v11 + v3 + 4);\n if ( v13 == a1 )\n break;\n ++v12;\n }\n }\n return (unsigned int)*(&v19 + v9 * a1);\n}", + "ida_strip_asm": "sub_1240:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\nmov r12d, edi\npush rbx\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nlea eax, [rdi+1]\nmov rcx, rsp\ncdqe\nlea rbx, ds:0[rax*4]\nimul rax, rax\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_12AD\nloc_1298:\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\ncmp rsp, rcx\njnz short loc_1298\nloc_12AD:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1389\nloc_12BF:\nlea r11, [rsp+1040h+var_103D]\nmov r10, rbx\nmov rax, r11\nshr r10, 2\nand r11, 0FFFFFFFFFFFFFFFCh\nshr rax, 2\nmov ds:dword_0[rax*4], 1\ntest r12d, r12d\njle short loc_1360\nmov r8, r11\nlea r14, [rbx+4]\nlea rsi, [r11+4]\nmov r13d, r12d\nmov r9d, 1\nxor edi, edi\nlea r15, [r10+1]\nmov edx, 1\nnop dword ptr [rax]\nloc_1308:\nmovsxd rax, r9d\nmov rcx, r9\nimul rax, r10\nsub rcx, rdi\nimul rcx, r10\nmov [r11+rax*4], edx\nmov edx, [r8+r10*4]\nmov rax, r8\nnop dword ptr [rax+00h]\nloc_1328:\nadd edx, [rax]\nmov [rax+rcx*4+4], edx\nadd rax, 4\ncmp rax, rsi\njnz short loc_1328\nadd rdi, 1\nadd r8, rbx\nadd rsi, r14\ncmp rdi, r13\njz short loc_1360\nmovsxd rax, edi\nadd r9, 1\nimul rax, r15\nmov edx, [r11+rax*4]\njmp short loc_1308\nloc_1360:\nmovsxd r12, r12d\nimul r12, r10\nmov eax, [r11+r12*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_1394\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1389:\nor [rsp+rdx+1040h+var_1048], 0\njmp loc_12BF\nloc_1394:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1240(int a1)\n{\n __int64 v2; // rax\n unsigned __int64 v3; // rbx\n __int64 v4; // rdx\n int *v5; // rcx\n __int16 v6; // dx\n signed __int64 v7; // rdx\n void *v8; // rsp\n unsigned __int64 v9; // r10\n int *v10; // r8\n int *v11; // rsi\n __int64 v12; // r9\n __int64 v13; // rdi\n int i; // edx\n int v15; // edx\n int *v16; // rax\n __int64 v18; // [rsp+0h] [rbp-1048h]\n int v19; // [rsp+8h] [rbp-1040h] BYREF\n int v20; // [rsp+Ch] [rbp-103Ch] BYREF\n _QWORD v21[8]; // [rsp+1008h] [rbp-40h] BYREF\n\n v21[1] = __readfsqword(0x28u);\n v2 = a1 + 1;\n v3 = 4 * v2;\n v4 = 4 * v2 * v2 + 15;\n v5 = (int *)((char *)v21 - (v4 & 0xFFFFFFFFFFFFF000LL));\n v6 = v4 & 0xFFF0;\n if ( v21 != (_QWORD *)v5 )\n {\n while ( &v19 != v5 )\n ;\n }\n v7 = v6 & 0xFFF;\n v8 = alloca(v7);\n if ( v7 )\n *(__int64 *)((char *)&v18 + v7) = *(__int64 *)((char *)&v18 + v7);\n v9 = v3 >> 2;\n v19 = 1;\n if ( a1 > 0 )\n {\n v10 = &v19;\n v11 = &v20;\n v12 = 1LL;\n v13 = 0LL;\n for ( i = 1; ; i = *(&v19 + (v9 + 1) * (int)v13) )\n {\n *(&v19 + v9 * (int)v12) = i;\n v15 = v10[v9];\n v16 = v10;\n do\n {\n v15 += *v16;\n v16[v9 * (v12 - v13) + 1] = v15;\n ++v16;\n }\n while ( v16 != v11 );\n ++v13;\n v10 = (int *)((char *)v10 + v3);\n v11 = (int *)((char *)v11 + v3 + 4);\n if ( v13 == a1 )\n break;\n ++v12;\n }\n }\n return (unsigned int)*(&v19 + v9 * a1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1240(int a1) {\n long long v2;\n unsigned long long v3;\n long long v4;\n int *v5;\n short v6;\n signed long long v7;\n void *v8;\n unsigned long long v9;\n int *v10;\n int *v11;\n long long v12;\n long long v13;\n int i;\n int v15;\n int *v16;\n long long v18;\n int v19;\n int v20;\n uint64_t v21[8];\n v21[1] = __readfsqword(40u);\n v2 = a1 + 1;\n v3 = 4 * v2;\n v4 = 4 * v2 * v2 + 15;\n v5 = (int *)((char *)v21 - (v4 & 18446744073709547520LL));\n v6 = v4 & 65520;\n if (v21 != (uint64_t *)v5) {\n while (&v19 != v5)\n ;\n }\n v7 = v6 & 4095;\n v8 = alloca(v7);\n if (v7) *(long long *)((char *)&v18 + v7) = *(long long *)((char *)&v18 + v7);\n v9 = v3 >> 2;\n v19 = 1;\n if (a1 > 0) {\n v10 = &v19;\n v11 = &v20;\n v12 = 1LL;\n v13 = 0LL;\n for (i = 1;; i = *(&v19 + (v9 + 1) * (int)v13)) {\n *(&v19 + v9 * (int)v12) = i;\n v15 = v10[v9];\n v16 = v10;\n do {\n v15 += *v16;\n v16[v9 * (v12 - v13) + 1] = v15;\n ++v16;\n } while (v16 != v11);\n ++v13;\n v10 = (int *)((char *)v10 + v3);\n v11 = (int *)((char *)v11 + v3 + 4);\n if (v13 == a1) break;\n ++v12;\n }\n }\n return (unsigned int)*(&v19 + v9 * a1);\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n long long v2;\n unsigned long long v3;\n long long v4;\n int *v5;\n short v6;\n signed long long v7;\n void *v8;\n unsigned long long v9;\n int *v10;\n int *v11;\n long long v12;\n long long v13;\n int i;\n int v15;\n int *v16;\n long long v18;\n int v19;\n int v20;\n uint64_t v21[8];\n v21[1] = __readfsqword(40u);\n v2 = a1 + 1;\n v3 = 4 * v2;\n v4 = 4 * v2 * v2 + 15;\n v5 = (int *)((char *)v21 - (v4 & 18446744073709547520LL));\n v6 = v4 & 65520;\n if (v21 != (uint64_t *)v5) {\n while (&v19 != v5)\n ;\n }\n v7 = v6 & 4095;\n v8 = alloca(v7);\n if (v7) *(long long *)((char *)&v18 + v7) = *(long long *)((char *)&v18 + v7);\n v9 = v3 >> 2;\n v19 = 1;\n if (a1 > 0) {\n v10 = &v19;\n v11 = &v20;\n v12 = 1LL;\n v13 = 0LL;\n for (i = 1;; i = *(&v19 + (v9 + 1) * (int)v13)) {\n *(&v19 + v9 * (int)v12) = i;\n v15 = v10[v9];\n v16 = v10;\n do {\n v15 += *v16;\n v16[v9 * (v12 - v13) + 1] = v15;\n ++v16;\n } while (v16 != v11);\n ++v13;\n v10 = (int *)((char *)v10 + v3);\n v11 = (int *)((char *)v11 + v3 + 4);\n if (v13 == a1) break;\n ++v12;\n }\n }\n return (unsigned int)*(&v19 + v9 * a1);\n}" + }, + { + "index": 608, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int bell[n + 1][n + 1];\n bell[0][0] = 1;\n for (int i = 1; i <= n; i++) {\n bell[i][0] = bell[i - 1][i - 1];\n for (int j = 1; j <= i; j++) {\n bell[i][j] = bell[i - 1][j - 1] + bell[i][j - 1];\n }\n }\n return bell[n][0];\n}", + "test": "int main() {\n\n assert(func0(2) == 2);\n\n assert(func0(3) == 5);\n\n assert(func0(4) == 15);\n\n\n\n printf(\"All assertions passed successfully.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\npush %r12\nmovslq %edi,%r12\npush %rbx\nsub $0x18,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nlea 0x1(%r12),%eax\nmov %rsp,%rdi\ncltq\nlea 0x0(,%rax,4),%rbx\nimul %rax,%rax\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rdi\nand $0xfffffffffffffff0,%rdx\nmov %rdi,%rax\ncmp %rax,%rsp\nje 1402 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 13ed \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 14de \nlea 0x3(%rsp),%rdi\nmov %rbx,%r11\nmov %rdi,%rax\nshr $0x2,%r11\nand $0xfffffffffffffffc,%rdi\nshr $0x2,%rax\nmovl $0x1,0x0(,%rax,4)\ntest %r12d,%r12d\njle 14b8 \nmov %rdi,%r8\nlea 0x4(%rbx),%r14\nlea 0x4(%rdi),%rsi\nxor %r9d,%r9d\nlea -0x1(%r12),%r13d\nmov $0x1,%r10d\nmov $0x1,%edx\nlea 0x1(%r11),%r15\nnopl (%rax)\nmovslq %r10d,%rax\nmov %r10,%rcx\nimul %r11,%rax\nsub %r9,%rcx\nimul %r11,%rcx\nmov %edx,(%rdi,%rax,4)\nmov (%r8,%r11,4),%edx\nmov %r8,%rax\nnopl 0x0(%rax,%rax,1)\nadd (%rax),%edx\nmov %edx,0x4(%rax,%rcx,4)\nadd $0x4,%rax\ncmp %rsi,%rax\njne 1480 \nlea 0x1(%r9),%rcx\nadd %rbx,%r8\nadd %r14,%rsi\ncmp %r13,%r9\nje 14b8 \nmovslq %ecx,%rax\nadd $0x1,%r10\nmov %rcx,%r9\nimul %r15,%rax\nmov (%rdi,%rax,4),%edx\njmp 1460 \nnopl 0x0(%rax)\nimul %r12,%r11\nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\nmov (%rdi,%r11,4),%eax\njne 14e9 \nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 1414 \ncallq 1070 <__stack_chk_fail@plt>\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\nmov r12d, edi\npush rbx\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nlea eax, [rdi+1]\nmov rcx, rsp\ncdqe\nlea rbx, ds:0[rax*4]\nimul rax, rax\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_12AD\nloc_1298:\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\ncmp rsp, rcx\njnz short loc_1298\nloc_12AD:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1389\nloc_12BF:\nlea r11, [rsp+1040h+var_103D]\nmov r10, rbx\nmov rax, r11\nshr r10, 2\nand r11, 0FFFFFFFFFFFFFFFCh\nshr rax, 2\nmov ds:dword_0[rax*4], 1\ntest r12d, r12d\njle short loc_1360\nmov r8, r11\nlea r14, [rbx+4]\nlea rsi, [r11+4]\nmov r13d, r12d\nmov r9d, 1\nxor edi, edi\nlea r15, [r10+1]\nmov edx, 1\nnop dword ptr [rax]\nloc_1308:\nmovsxd rax, r9d\nmov rcx, r9\nimul rax, r10\nsub rcx, rdi\nimul rcx, r10\nmov [r11+rax*4], edx\nmov edx, [r8+r10*4]\nmov rax, r8\nnop dword ptr [rax+00h]\nloc_1328:\nadd edx, [rax]\nmov [rax+rcx*4+4], edx\nadd rax, 4\ncmp rax, rsi\njnz short loc_1328\nadd rdi, 1\nadd r8, rbx\nadd rsi, r14\ncmp rdi, r13\njz short loc_1360\nmovsxd rax, edi\nadd r9, 1\nimul rax, r15\nmov edx, [r11+rax*4]\njmp short loc_1308\nloc_1360:\nmovsxd r12, r12d\nimul r12, r10\nmov eax, [r11+r12*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_1394\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1389:\nor [rsp+rdx+1040h+var_1048], 0\njmp loc_12BF\nloc_1394:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n __int64 v2; // rax\n unsigned __int64 v3; // rbx\n __int64 v4; // rdx\n int *v5; // rcx\n __int16 v6; // dx\n signed __int64 v7; // rdx\n void *v8; // rsp\n unsigned __int64 v9; // r10\n int *v10; // r8\n int *v11; // rsi\n __int64 v12; // r9\n __int64 v13; // rdi\n int i; // edx\n int v15; // edx\n int *v16; // rax\n __int64 v18; // [rsp+0h] [rbp-1048h]\n int v19; // [rsp+8h] [rbp-1040h] BYREF\n int v20; // [rsp+Ch] [rbp-103Ch] BYREF\n _QWORD v21[8]; // [rsp+1008h] [rbp-40h] BYREF\n\n v21[1] = __readfsqword(0x28u);\n v2 = a1 + 1;\n v3 = 4 * v2;\n v4 = 4 * v2 * v2 + 15;\n v5 = (int *)((char *)v21 - (v4 & 0xFFFFFFFFFFFFF000LL));\n v6 = v4 & 0xFFF0;\n if ( v21 != (_QWORD *)v5 )\n {\n while ( &v19 != v5 )\n ;\n }\n v7 = v6 & 0xFFF;\n v8 = alloca(v7);\n if ( v7 )\n *(__int64 *)((char *)&v18 + v7) = *(__int64 *)((char *)&v18 + v7);\n v9 = v3 >> 2;\n v19 = 1;\n if ( a1 > 0 )\n {\n v10 = &v19;\n v11 = &v20;\n v12 = 1LL;\n v13 = 0LL;\n for ( i = 1; ; i = *(&v19 + (v9 + 1) * (int)v13) )\n {\n *(&v19 + v9 * (int)v12) = i;\n v15 = v10[v9];\n v16 = v10;\n do\n {\n v15 += *v16;\n v16[v9 * (v12 - v13) + 1] = v15;\n ++v16;\n }\n while ( v16 != v11 );\n ++v13;\n v10 = (int *)((char *)v10 + v3);\n v11 = (int *)((char *)v11 + v3 + 4);\n if ( v13 == a1 )\n break;\n ++v12;\n }\n }\n return (unsigned int)*(&v19 + v9 * a1);\n}", + "ida_strip_asm": "sub_1240:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\nmov r12d, edi\npush rbx\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nlea eax, [rdi+1]\nmov rcx, rsp\ncdqe\nlea rbx, ds:0[rax*4]\nimul rax, rax\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_12AD\nloc_1298:\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\ncmp rsp, rcx\njnz short loc_1298\nloc_12AD:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1389\nloc_12BF:\nlea r11, [rsp+1040h+var_103D]\nmov r10, rbx\nmov rax, r11\nshr r10, 2\nand r11, 0FFFFFFFFFFFFFFFCh\nshr rax, 2\nmov ds:dword_0[rax*4], 1\ntest r12d, r12d\njle short loc_1360\nmov r8, r11\nlea r14, [rbx+4]\nlea rsi, [r11+4]\nmov r13d, r12d\nmov r9d, 1\nxor edi, edi\nlea r15, [r10+1]\nmov edx, 1\nnop dword ptr [rax]\nloc_1308:\nmovsxd rax, r9d\nmov rcx, r9\nimul rax, r10\nsub rcx, rdi\nimul rcx, r10\nmov [r11+rax*4], edx\nmov edx, [r8+r10*4]\nmov rax, r8\nnop dword ptr [rax+00h]\nloc_1328:\nadd edx, [rax]\nmov [rax+rcx*4+4], edx\nadd rax, 4\ncmp rax, rsi\njnz short loc_1328\nadd rdi, 1\nadd r8, rbx\nadd rsi, r14\ncmp rdi, r13\njz short loc_1360\nmovsxd rax, edi\nadd r9, 1\nimul rax, r15\nmov edx, [r11+rax*4]\njmp short loc_1308\nloc_1360:\nmovsxd r12, r12d\nimul r12, r10\nmov eax, [r11+r12*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_1394\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1389:\nor [rsp+rdx+1040h+var_1048], 0\njmp loc_12BF\nloc_1394:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1240(int a1)\n{\n __int64 v2; // rax\n unsigned __int64 v3; // rbx\n __int64 v4; // rdx\n int *v5; // rcx\n __int16 v6; // dx\n signed __int64 v7; // rdx\n void *v8; // rsp\n unsigned __int64 v9; // r10\n int *v10; // r8\n int *v11; // rsi\n __int64 v12; // r9\n __int64 v13; // rdi\n int i; // edx\n int v15; // edx\n int *v16; // rax\n __int64 v18; // [rsp+0h] [rbp-1048h]\n int v19; // [rsp+8h] [rbp-1040h] BYREF\n int v20; // [rsp+Ch] [rbp-103Ch] BYREF\n _QWORD v21[8]; // [rsp+1008h] [rbp-40h] BYREF\n\n v21[1] = __readfsqword(0x28u);\n v2 = a1 + 1;\n v3 = 4 * v2;\n v4 = 4 * v2 * v2 + 15;\n v5 = (int *)((char *)v21 - (v4 & 0xFFFFFFFFFFFFF000LL));\n v6 = v4 & 0xFFF0;\n if ( v21 != (_QWORD *)v5 )\n {\n while ( &v19 != v5 )\n ;\n }\n v7 = v6 & 0xFFF;\n v8 = alloca(v7);\n if ( v7 )\n *(__int64 *)((char *)&v18 + v7) = *(__int64 *)((char *)&v18 + v7);\n v9 = v3 >> 2;\n v19 = 1;\n if ( a1 > 0 )\n {\n v10 = &v19;\n v11 = &v20;\n v12 = 1LL;\n v13 = 0LL;\n for ( i = 1; ; i = *(&v19 + (v9 + 1) * (int)v13) )\n {\n *(&v19 + v9 * (int)v12) = i;\n v15 = v10[v9];\n v16 = v10;\n do\n {\n v15 += *v16;\n v16[v9 * (v12 - v13) + 1] = v15;\n ++v16;\n }\n while ( v16 != v11 );\n ++v13;\n v10 = (int *)((char *)v10 + v3);\n v11 = (int *)((char *)v11 + v3 + 4);\n if ( v13 == a1 )\n break;\n ++v12;\n }\n }\n return (unsigned int)*(&v19 + v9 * a1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1240(int a1) {\n long long v2;\n unsigned long long v3;\n long long v4;\n int *v5;\n short v6;\n signed long long v7;\n void *v8;\n unsigned long long v9;\n int *v10;\n int *v11;\n long long v12;\n long long v13;\n int i;\n int v15;\n int *v16;\n long long v18;\n int v19;\n int v20;\n uint64_t v21[8];\n v21[1] = __readfsqword(40u);\n v2 = a1 + 1;\n v3 = 4 * v2;\n v4 = 4 * v2 * v2 + 15;\n v5 = (int *)((char *)v21 - (v4 & 18446744073709547520LL));\n v6 = v4 & 65520;\n if (v21 != (uint64_t *)v5) {\n while (&v19 != v5)\n ;\n }\n v7 = v6 & 4095;\n v8 = alloca(v7);\n if (v7) *(long long *)((char *)&v18 + v7) = *(long long *)((char *)&v18 + v7);\n v9 = v3 >> 2;\n v19 = 1;\n if (a1 > 0) {\n v10 = &v19;\n v11 = &v20;\n v12 = 1LL;\n v13 = 0LL;\n for (i = 1;; i = *(&v19 + (v9 + 1) * (int)v13)) {\n *(&v19 + v9 * (int)v12) = i;\n v15 = v10[v9];\n v16 = v10;\n do {\n v15 += *v16;\n v16[v9 * (v12 - v13) + 1] = v15;\n ++v16;\n } while (v16 != v11);\n ++v13;\n v10 = (int *)((char *)v10 + v3);\n v11 = (int *)((char *)v11 + v3 + 4);\n if (v13 == a1) break;\n ++v12;\n }\n }\n return (unsigned int)*(&v19 + v9 * a1);\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n long long v2;\n unsigned long long v3;\n long long v4;\n int *v5;\n short v6;\n signed long long v7;\n void *v8;\n unsigned long long v9;\n int *v10;\n int *v11;\n long long v12;\n long long v13;\n int i;\n int v15;\n int *v16;\n long long v18;\n int v19;\n int v20;\n uint64_t v21[8];\n v21[1] = __readfsqword(40u);\n v2 = a1 + 1;\n v3 = 4 * v2;\n v4 = 4 * v2 * v2 + 15;\n v5 = (int *)((char *)v21 - (v4 & 18446744073709547520LL));\n v6 = v4 & 65520;\n if (v21 != (uint64_t *)v5) {\n while (&v19 != v5)\n ;\n }\n v7 = v6 & 4095;\n v8 = alloca(v7);\n if (v7) *(long long *)((char *)&v18 + v7) = *(long long *)((char *)&v18 + v7);\n v9 = v3 >> 2;\n v19 = 1;\n if (a1 > 0) {\n v10 = &v19;\n v11 = &v20;\n v12 = 1LL;\n v13 = 0LL;\n for (i = 1;; i = *(&v19 + (v9 + 1) * (int)v13)) {\n *(&v19 + v9 * (int)v12) = i;\n v15 = v10[v9];\n v16 = v10;\n do {\n v15 += *v16;\n v16[v9 * (v12 - v13) + 1] = v15;\n ++v16;\n } while (v16 != v11);\n ++v13;\n v10 = (int *)((char *)v10 + v3);\n v11 = (int *)((char *)v11 + v3 + 4);\n if (v13 == a1) break;\n ++v12;\n }\n }\n return (unsigned int)*(&v19 + v9 * a1);\n}" + }, + { + "index": 609, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int A, int B, int N) {\n int x = (B - 1 > N) ? B - 1 : N;\n return (A * x) / B;\n}", + "test": "int main() {\n\n assert(func0(10, 20, 30) == 15);\n\n assert(func0(1, 2, 1) == 0);\n\n assert(func0(11, 10, 9) == 9);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov %edx,-0x1c(%rbp)\nmov -0x18(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x1c(%rbp)\ncmovge -0x1c(%rbp),%eax\nmov %eax,-0x4(%rbp)\nmov -0x14(%rbp),%eax\nimul -0x4(%rbp),%eax\ncltd\nidivl -0x18(%rbp)\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov eax, [rbp+var_18]\nsub eax, 1\nmov edx, [rbp+var_1C]\ncmp edx, eax\ncmovge eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_14]\nimul eax, [rbp+var_4]\ncdq\nidiv [rbp+var_18]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, int a3)\n{\n int v3; // eax\n\n v3 = a2 - 1;\n if ( a3 >= a2 - 1 )\n v3 = a3;\n return (unsigned int)(v3 * a1 / a2);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov eax, [rbp+var_18]\nsub eax, 1\nmov edx, [rbp+var_1C]\ncmp edx, eax\ncmovge eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_14]\nimul eax, [rbp+var_4]\ncdq\nidiv [rbp+var_18]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2, int a3)\n{\n int v3; // eax\n\n v3 = a2 - 1;\n if ( a3 >= a2 - 1 )\n v3 = a3;\n return (unsigned int)(v3 * a1 / a2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2, int a3) {\n int v3;\n v3 = a2 - 1;\n if (a3 >= a2 - 1) v3 = a3;\n return (unsigned int)(v3 * a1 / a2);\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, int a3) {\n int v3;\n v3 = a2 - 1;\n if (a3 >= a2 - 1) v3 = a3;\n return (unsigned int)(v3 * a1 / a2);\n}" + }, + { + "index": 610, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "void func0(int list1[], int size, int L) {\n if (L > 0 && L <= size) {\n for (int i = L - 1; i < size - 1; i++) {\n list1[i] = list1[i + 1];\n }\n }\n}", + "test": "int main() {\n\n int list1[] = {1, 1, 2, 3, 4, 4, 5, 1};\n\n func0(list1, 8, 3);\n\n int expected1[] = {1, 1, 3, 4, 4, 5, 1};\n\n for (int i = 0; i < 7; i++) {\n\n assert(list1[i] == expected1[i]);\n\n }\n\n\n\n int list2[] = {0, 0, 1, 2, 3, 4, 4, 5, 6, 6, 6, 7, 8, 9, 4, 4};\n\n func0(list2, 16, 4);\n\n int expected2[] = {0, 0, 1, 3, 4, 4, 5, 6, 6, 6, 7, 8, 9, 4, 4};\n\n for (int i = 0; i < 15; i++) {\n\n assert(list2[i] == expected2[i]);\n\n }\n\n\n\n int list3[] = {10, 10, 15, 19, 18, 18, 17, 26, 26, 17, 18, 10};\n\n func0(list3, 12, 5);\n\n int expected3[] = {10, 10, 15, 19, 18, 17, 26, 26, 17, 18, 10};\n\n for (int i = 0; i < 11; i++) {\n\n assert(list3[i] == expected3[i]);\n\n }\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\ncmpl $0x0,-0x20(%rbp)\njle 11f4 \nmov -0x20(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njg 11f4 \nmov -0x20(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0x4(%rbp)\njmp 11e9 \nmov -0x4(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0x4(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x4(%rbp)\nmov -0x1c(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x4(%rbp)\njl 11b4 \npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\ncmp [rbp+var_20], 0\njle short loc_11F4\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_1C]\njg short loc_11F4\nmov eax, [rbp+var_20]\nsub eax, 1\nmov [rbp+var_4], eax\njmp short loc_11E9\nloc_11B4:\nmov eax, [rbp+var_4]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_4], 1\nloc_11E9:\nmov eax, [rbp+var_1C]\nsub eax, 1\ncmp [rbp+var_4], eax\njl short loc_11B4\nloc_11F4:\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n __int64 result; // rax\n int i; // [rsp+1Ch] [rbp-4h]\n\n if ( a3 > 0 )\n {\n result = (unsigned int)a3;\n if ( a3 <= a2 )\n {\n for ( i = a3 - 1; ; ++i )\n {\n result = (unsigned int)(a2 - 1);\n if ( i >= (int)result )\n break;\n *(_DWORD *)(4LL * i + a1) = *(_DWORD *)(4 * (i + 1LL) + a1);\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\ncmp [rbp+var_20], 0\njle short loc_11F4\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_1C]\njg short loc_11F4\nmov eax, [rbp+var_20]\nsub eax, 1\nmov [rbp+var_4], eax\njmp short loc_11E9\nloc_11B4:\nmov eax, [rbp+var_4]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_4], 1\nloc_11E9:\nmov eax, [rbp+var_1C]\nsub eax, 1\ncmp [rbp+var_4], eax\njl short loc_11B4\nloc_11F4:\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2, int a3)\n{\n __int64 result; // rax\n int i; // [rsp+1Ch] [rbp-4h]\n\n if ( a3 > 0 )\n {\n result = (unsigned int)a3;\n if ( a3 <= a2 )\n {\n for ( i = a3 - 1; ; ++i )\n {\n result = (unsigned int)(a2 - 1);\n if ( i >= (int)result )\n break;\n *(_DWORD *)(4LL * i + a1) = *(_DWORD *)(4 * (i + 1LL) + a1);\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2, int a3) {\n long long result;\n int i;\n if (a3 > 0) {\n result = (unsigned int)a3;\n if (a3 <= a2) {\n for (i = a3 - 1;; ++i) {\n result = (unsigned int)(a2 - 1);\n if (i >= (int)result) break;\n *(uint32_t *)(4LL * i + a1) = *(uint32_t *)(4 * (i + 1LL) + a1);\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n long long result;\n int i;\n if (a3 > 0) {\n result = (unsigned int)a3;\n if (a3 <= a2) {\n for (i = a3 - 1;; ++i) {\n result = (unsigned int)(a2 - 1);\n if (i >= (int)result) break;\n *(uint32_t *)(4LL * i + a1) = *(uint32_t *)(4 * (i + 1LL) + a1);\n }\n }\n }\n return result;\n}" + }, + { + "index": 610, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "void func0(int list1[], int size, int L) {\n if (L > 0 && L <= size) {\n for (int i = L - 1; i < size - 1; i++) {\n list1[i] = list1[i + 1];\n }\n }\n}", + "test": "int main() {\n\n int list1[] = {1, 1, 2, 3, 4, 4, 5, 1};\n\n func0(list1, 8, 3);\n\n int expected1[] = {1, 1, 3, 4, 4, 5, 1};\n\n for (int i = 0; i < 7; i++) {\n\n assert(list1[i] == expected1[i]);\n\n }\n\n\n\n int list2[] = {0, 0, 1, 2, 3, 4, 4, 5, 6, 6, 6, 7, 8, 9, 4, 4};\n\n func0(list2, 16, 4);\n\n int expected2[] = {0, 0, 1, 3, 4, 4, 5, 6, 6, 6, 7, 8, 9, 4, 4};\n\n for (int i = 0; i < 15; i++) {\n\n assert(list2[i] == expected2[i]);\n\n }\n\n\n\n int list3[] = {10, 10, 15, 19, 18, 18, 17, 26, 26, 17, 18, 10};\n\n func0(list3, 12, 5);\n\n int expected3[] = {10, 10, 15, 19, 18, 17, 26, 26, 17, 18, 10};\n\n for (int i = 0; i < 11; i++) {\n\n assert(list3[i] == expected3[i]);\n\n }\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edx,%edx\njle 11bd \ncmp %esi,%edx\njg 11bd \nlea -0x1(%rdx),%eax\njge 11bd \ncltq\nlea (%rdi,%rax,4),%rax\nsub $0x1,%esi\nsub %edx,%esi\nmovslq %edx,%rdx\nadd %rsi,%rdx\nlea (%rdi,%rdx,4),%rcx\nmov 0x4(%rax),%edx\nmov %edx,(%rax)\nadd $0x4,%rax\ncmp %rcx,%rax\njne 11af \nretq\n", + "ida_asm": "func0:\nendbr64\ntest edx, edx\njle short locret_11BD\ncmp edx, esi\njg short locret_11BD\nlea eax, [rdx-1]\njge short locret_11BD\ncdqe\nlea rax, [rdi+rax*4]\nsub esi, 1\nsub esi, edx\nmovsxd rdx, edx\nadd rsi, rdx\nlea rcx, [rdi+rsi*4]\nloc_11AF:\nmov edx, [rax+4]\nmov [rax], edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_11AF\nlocret_11BD:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2, int a3)\n{\n _DWORD *v3; // rax\n\n if ( a3 > 0 && a3 < a2 )\n {\n v3 = (_DWORD *)(a1 + 4LL * (a3 - 1));\n do\n {\n *v3 = v3[1];\n ++v3;\n }\n while ( v3 != (_DWORD *)(a1 + 4 * (a3 + (unsigned __int64)(unsigned int)(a2 - 1 - a3))) );\n }\n}", + "ida_strip_asm": "sub_1189:\nendbr64\ntest edx, edx\njle short locret_11BD\ncmp edx, esi\njg short locret_11BD\nlea eax, [rdx-1]\njge short locret_11BD\ncdqe\nlea rax, [rdi+rax*4]\nsub esi, 1\nsub esi, edx\nmovsxd rdx, edx\nadd rsi, rdx\nlea rcx, [rdi+rsi*4]\nloc_11AF:\nmov edx, [rax+4]\nmov [rax], edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_11AF\nlocret_11BD:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1189(__int64 a1, int a2, int a3)\n{\n _DWORD *v3; // rax\n\n if ( a3 > 0 && a3 < a2 )\n {\n v3 = (_DWORD *)(a1 + 4LL * (a3 - 1));\n do\n {\n *v3 = v3[1];\n ++v3;\n }\n while ( v3 != (_DWORD *)(a1 + 4 * (a3 + (unsigned __int64)(unsigned int)(a2 - 1 - a3))) );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1189(long long a1, int a2, int a3) {\n uint32_t *v3;\n if (a3 > 0 && a3 < a2) {\n v3 = (uint32_t *)(a1 + 4LL * (a3 - 1));\n do {\n *v3 = v3[1];\n ++v3;\n } while (\n v3 !=\n (uint32_t *)(a1 + 4 * (a3 + (unsigned long long)(unsigned int)(a2 - 1 -\n a3))));\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2, int a3) {\n uint32_t *v3;\n if (a3 > 0 && a3 < a2) {\n v3 = (uint32_t *)(a1 + 4LL * (a3 - 1));\n do {\n *v3 = v3[1];\n ++v3;\n } while (\n v3 !=\n (uint32_t *)(a1 + 4 * (a3 + (unsigned long long)(unsigned int)(a2 - 1 -\n a3))));\n }\n}" + }, + { + "index": 610, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "void func0(int list1[], int size, int L) {\n if (L > 0 && L <= size) {\n for (int i = L - 1; i < size - 1; i++) {\n list1[i] = list1[i + 1];\n }\n }\n}", + "test": "int main() {\n\n int list1[] = {1, 1, 2, 3, 4, 4, 5, 1};\n\n func0(list1, 8, 3);\n\n int expected1[] = {1, 1, 3, 4, 4, 5, 1};\n\n for (int i = 0; i < 7; i++) {\n\n assert(list1[i] == expected1[i]);\n\n }\n\n\n\n int list2[] = {0, 0, 1, 2, 3, 4, 4, 5, 6, 6, 6, 7, 8, 9, 4, 4};\n\n func0(list2, 16, 4);\n\n int expected2[] = {0, 0, 1, 3, 4, 4, 5, 6, 6, 6, 7, 8, 9, 4, 4};\n\n for (int i = 0; i < 15; i++) {\n\n assert(list2[i] == expected2[i]);\n\n }\n\n\n\n int list3[] = {10, 10, 15, 19, 18, 18, 17, 26, 26, 17, 18, 10};\n\n func0(list3, 12, 5);\n\n int expected3[] = {10, 10, 15, 19, 18, 17, 26, 26, 17, 18, 10};\n\n for (int i = 0; i < 11; i++) {\n\n assert(list3[i] == expected3[i]);\n\n }\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %edx,%edx\njle 14e0 \ncmp %esi,%edx\njg 14e0 \njmp 14a0 \nxchg %ax,%ax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0_part_0:\nlea eax, [rdx-1]\ncmp edx, esi\njge short locret_1450\ncdqe\nsub esi, 1\nshl rax, 2\nsub esi, edx\nlea rdx, ds:4[rsi*4]; n\nlea rsi, [rdi+rax+4]; src\nadd rdi, rax; dest\njmp _memmove\nlocret_1450:\nretn", + "ida_pseudo": "unsigned __int64 __fastcall func0_part_0(__int64 a1, int a2, int a3)\n{\n unsigned __int64 result; // rax\n\n result = (unsigned int)(a3 - 1);\n if ( a3 < a2 )\n return (unsigned __int64)memmove(\n (void *)(4LL * (int)result + a1),\n (const void *)(a1 + 4LL * (int)result + 4),\n 4LL * (unsigned int)(a2 - 1 - a3) + 4);\n return result;\n}", + "ida_strip_asm": "sub_1420:\nlea eax, [rdx-1]\ncmp edx, esi\njge short locret_1450\ncdqe\nsub esi, 1\nshl rax, 2\nsub esi, edx\nlea rdx, ds:4[rsi*4]; n\nlea rsi, [rdi+rax+4]; src\nadd rdi, rax; dest\njmp _memmove\nlocret_1450:\nretn", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_1420(__int64 a1, int a2, int a3)\n{\n unsigned __int64 result; // rax\n\n result = (unsigned int)(a3 - 1);\n if ( a3 < a2 )\n return (unsigned __int64)memmove(\n (void *)(4LL * (int)result + a1),\n (const void *)(a1 + 4LL * (int)result + 4),\n 4LL * (unsigned int)(a2 - 1 - a3) + 4);\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_1420(long long a1, int a2, int a3) {\n unsigned long long result;\n result = (unsigned int)(a3 - 1);\n if (a3 < a2)\n return (unsigned long long)memmove(\n (void *)(4LL * (int)result + a1),\n (const void *)(a1 + 4LL * (int)result + 4),\n 4LL * (unsigned int)(a2 - 1 - a3) + 4);\n return result;\n}", + "ida_pseudo_norm": "unsigned long long func0_part_0(long long a1, int a2, int a3) {\n unsigned long long result;\n result = (unsigned int)(a3 - 1);\n if (a3 < a2)\n return (unsigned long long)memmove(\n (void *)(4LL * (int)result + a1),\n (const void *)(a1 + 4LL * (int)result + 4),\n 4LL * (unsigned int)(a2 - 1 - a3) + 4);\n return result;\n}" + }, + { + "index": 610, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "void func0(int list1[], int size, int L) {\n if (L > 0 && L <= size) {\n for (int i = L - 1; i < size - 1; i++) {\n list1[i] = list1[i + 1];\n }\n }\n}", + "test": "int main() {\n\n int list1[] = {1, 1, 2, 3, 4, 4, 5, 1};\n\n func0(list1, 8, 3);\n\n int expected1[] = {1, 1, 3, 4, 4, 5, 1};\n\n for (int i = 0; i < 7; i++) {\n\n assert(list1[i] == expected1[i]);\n\n }\n\n\n\n int list2[] = {0, 0, 1, 2, 3, 4, 4, 5, 6, 6, 6, 7, 8, 9, 4, 4};\n\n func0(list2, 16, 4);\n\n int expected2[] = {0, 0, 1, 3, 4, 4, 5, 6, 6, 6, 7, 8, 9, 4, 4};\n\n for (int i = 0; i < 15; i++) {\n\n assert(list2[i] == expected2[i]);\n\n }\n\n\n\n int list3[] = {10, 10, 15, 19, 18, 18, 17, 26, 26, 17, 18, 10};\n\n func0(list3, 12, 5);\n\n int expected3[] = {10, 10, 15, 19, 18, 17, 26, 26, 17, 18, 10};\n\n for (int i = 0; i < 11; i++) {\n\n assert(list3[i] == expected3[i]);\n\n }\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ntest %edx,%edx\njle 1760 \ncmp %esi,%edx\njg 1760 \nlea -0x1(%rdx),%r9d\nlea -0x1(%rsi),%r10d\njge 1760 \nmovslq %edx,%r11\npush %rbp\nlea 0x10(,%r11,4),%rcx\npush %rbx\nmov %r10d,%ebx\nlea 0x0(,%r11,4),%r8\nlea -0x14(%rcx),%rax\nsub %edx,%ebx\ncmp %rcx,%rax\nsetge %bpl\nsub $0x4,%rcx\ncmp %r8,%rcx\nsetle %cl\nor %cl,%bpl\nje 1768 \ncmp $0x3,%ebx\njbe 1768 \nsub %edx,%esi\nadd %rdi,%r8\nlea (%rdi,%rax,1),%rdx\nxor %eax,%eax\nmov %esi,%ecx\nshr $0x2,%ecx\nshl $0x4,%rcx\nnopw 0x0(%rax,%rax,1)\nmovdqu (%r8,%rax,1),%xmm0\nmovups %xmm0,(%rdx,%rax,1)\nadd $0x10,%rax\ncmp %rcx,%rax\njne 1700 \nmov %esi,%eax\nand $0xfffffffc,%eax\nadd %eax,%r9d\ncmp %eax,%esi\nje 1756 \nmovslq %r9d,%rax\nadd $0x1,%rax\nmov (%rdi,%rax,4),%ecx\nlea 0x0(,%rax,4),%rdx\nmov %ecx,-0x4(%rdi,%rdx,1)\nlea 0x1(%r9),%ecx\ncmp %ecx,%r10d\njle 1756 \nmov 0x4(%rdi,%rdx,1),%ecx\nadd $0x2,%r9d\nmov %ecx,(%rdi,%rax,4)\ncmp %r9d,%r10d\njle 1756 \nmov 0x8(%rdi,%rdx,1),%eax\nmov %eax,0x4(%rdi,%rdx,1)\npop %rbx\npop %rbp\nretq\nnopl 0x0(%rax)\nretq\nnopl 0x0(%rax)\nadd %rbx,%r11\nadd %rdi,%rax\nlea (%rdi,%r11,4),%rcx\nnopw 0x0(%rax,%rax,1)\nmov 0x4(%rax),%edx\nadd $0x4,%rax\nmov %edx,-0x4(%rax)\ncmp %rcx,%rax\njne 1778 \njmp 1756 \nnopl 0x0(%rax)\n", + "ida_asm": "func0_part_0:\nlea eax, [rdx-1]\ncmp edx, esi\njge short locret_1490\ncdqe\nsub esi, 1\nshl rax, 2\nsub esi, edx\nlea rdx, ds:4[rsi*4]; n\nlea rsi, [rdi+rax+4]; src\nadd rdi, rax; dest\njmp _memmove\nlocret_1490:\nretn", + "ida_pseudo": "unsigned __int64 __fastcall func0_part_0(__int64 a1, int a2, int a3)\n{\n unsigned __int64 result; // rax\n\n result = (unsigned int)(a3 - 1);\n if ( a3 < a2 )\n return (unsigned __int64)memmove(\n (void *)(4LL * (int)result + a1),\n (const void *)(a1 + 4LL * (int)result + 4),\n 4LL * (unsigned int)(a2 - 1 - a3) + 4);\n return result;\n}", + "ida_strip_asm": "sub_1460:\nlea eax, [rdx-1]\ncmp edx, esi\njge short locret_1490\ncdqe\nsub esi, 1\nshl rax, 2\nsub esi, edx\nlea rdx, ds:4[rsi*4]; n\nlea rsi, [rdi+rax+4]; src\nadd rdi, rax; dest\njmp _memmove\nlocret_1490:\nretn", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_1460(__int64 a1, int a2, int a3)\n{\n unsigned __int64 result; // rax\n\n result = (unsigned int)(a3 - 1);\n if ( a3 < a2 )\n return (unsigned __int64)memmove(\n (void *)(4LL * (int)result + a1),\n (const void *)(a1 + 4LL * (int)result + 4),\n 4LL * (unsigned int)(a2 - 1 - a3) + 4);\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_1460(long long a1, int a2, int a3) {\n unsigned long long result;\n result = (unsigned int)(a3 - 1);\n if (a3 < a2)\n return (unsigned long long)memmove(\n (void *)(4LL * (int)result + a1),\n (const void *)(a1 + 4LL * (int)result + 4),\n 4LL * (unsigned int)(a2 - 1 - a3) + 4);\n return result;\n}", + "ida_pseudo_norm": "unsigned long long func0_part_0(long long a1, int a2, int a3) {\n unsigned long long result;\n result = (unsigned int)(a3 - 1);\n if (a3 < a2)\n return (unsigned long long)memmove(\n (void *)(4LL * (int)result + a1),\n (const void *)(a1 + 4LL * (int)result + 4),\n 4LL * (unsigned int)(a2 - 1 - a3) + 4);\n return result;\n}" + }, + { + "index": 611, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int test_list[][3], int list_size, int N) {\n int res = test_list[0][N];\n for (int i = 1; i < list_size; i++) {\n if (test_list[i][N] > res) {\n res = test_list[i][N];\n }\n }\n return res;\n}", + "test": "int main() {\n\n int test_list1[3][3] = {{5, 6, 7}, {1, 3, 5}, {8, 9, 19}};\n\n int test_list2[3][3] = {{6, 7, 8}, {2, 4, 6}, {9, 10, 20}};\n\n int test_list3[3][3] = {{7, 8, 9}, {3, 5, 7}, {10, 11, 21}};\n\n \n\n assert(func0(test_list1, 3, 2) == 19);\n\n assert(func0(test_list2, 3, 1) == 10);\n\n assert(func0(test_list3, 3, 1) == 11);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmov -0x18(%rbp),%rax\nmov -0x20(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nmov %eax,-0x8(%rbp)\nmovl $0x1,-0x4(%rbp)\njmp 11ea \nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0x20(%rbp),%eax\ncltq\nmov (%rdx,%rax,4),%eax\ncmp %eax,-0x8(%rbp)\njge 11e6 \nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0x20(%rbp),%eax\ncltq\nmov (%rdx,%rax,4),%eax\nmov %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1194 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov rax, [rbp+var_18]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov [rbp+var_8], eax\nmov [rbp+var_4], 1\njmp short loc_11EA\nloc_1194:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_20]\ncdqe\nmov eax, [rdx+rax*4]\ncmp [rbp+var_8], eax\njge short loc_11E6\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_20]\ncdqe\nmov eax, [rdx+rax*4]\nmov [rbp+var_8], eax\nloc_11E6:\nadd [rbp+var_4], 1\nloc_11EA:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1194\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n unsigned int v4; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v4 = *(_DWORD *)(a1 + 4LL * a3);\n for ( i = 1; i < a2; ++i )\n {\n if ( (signed int)v4 < *(_DWORD *)(a1 + 12LL * i + 4LL * a3) )\n v4 = *(_DWORD *)(a1 + 12LL * i + 4LL * a3);\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov rax, [rbp+var_18]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov [rbp+var_8], eax\nmov [rbp+var_4], 1\njmp short loc_11EA\nloc_1194:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_20]\ncdqe\nmov eax, [rdx+rax*4]\ncmp [rbp+var_8], eax\njge short loc_11E6\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_20]\ncdqe\nmov eax, [rdx+rax*4]\nmov [rbp+var_8], eax\nloc_11E6:\nadd [rbp+var_4], 1\nloc_11EA:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1194\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n unsigned int v4; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v4 = *(_DWORD *)(a1 + 4LL * a3);\n for ( i = 1; i < a2; ++i )\n {\n if ( (signed int)v4 < *(_DWORD *)(a1 + 12LL * i + 4LL * a3) )\n v4 = *(_DWORD *)(a1 + 12LL * i + 4LL * a3);\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n unsigned int v4;\n int i;\n v4 = *(uint32_t *)(a1 + 4LL * a3);\n for (i = 1; i < a2; ++i) {\n if ((signed int)v4 < *(uint32_t *)(a1 + 12LL * i + 4LL * a3))\n v4 = *(uint32_t *)(a1 + 12LL * i + 4LL * a3);\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n unsigned int v4;\n int i;\n v4 = *(uint32_t *)(a1 + 4LL * a3);\n for (i = 1; i < a2; ++i) {\n if ((signed int)v4 < *(uint32_t *)(a1 + 12LL * i + 4LL * a3))\n v4 = *(uint32_t *)(a1 + 12LL * i + 4LL * a3);\n }\n return v4;\n}" + }, + { + "index": 611, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int test_list[][3], int list_size, int N) {\n int res = test_list[0][N];\n for (int i = 1; i < list_size; i++) {\n if (test_list[i][N] > res) {\n res = test_list[i][N];\n }\n }\n return res;\n}", + "test": "int main() {\n\n int test_list1[3][3] = {{5, 6, 7}, {1, 3, 5}, {8, 9, 19}};\n\n int test_list2[3][3] = {{6, 7, 8}, {2, 4, 6}, {9, 10, 20}};\n\n int test_list3[3][3] = {{7, 8, 9}, {3, 5, 7}, {10, 11, 21}};\n\n \n\n assert(func0(test_list1, 3, 2) == 19);\n\n assert(func0(test_list2, 3, 1) == 10);\n\n assert(func0(test_list3, 3, 1) == 11);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmovslq %edx,%rax\nmov (%rdi,%rax,4),%ecx\ncmp $0x1,%esi\njle 119f \nmov %rax,%rdx\nlea (%rdi,%rax,4),%rax\nlea -0x2(%rsi),%esi\nlea (%rsi,%rsi,2),%rsi\nadd %rsi,%rdx\nlea 0xc(%rdi,%rdx,4),%rsi\nmov 0xc(%rax),%edx\ncmp %edx,%ecx\ncmovl %edx,%ecx\nadd $0xc,%rax\ncmp %rsi,%rax\njne 118e \nmov %ecx,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmovsxd rax, edx\nmov ecx, [rdi+rax*4]\ncmp esi, 1\njle short loc_119F\nmov rdx, rax\nlea rax, [rdi+rax*4]\nlea esi, [rsi-2]\nlea rsi, [rsi+rsi*2]\nadd rdx, rsi\nlea rsi, [rdi+rdx*4+0Ch]\nloc_118E:\nmov edx, [rax+0Ch]\ncmp ecx, edx\ncmovl ecx, edx\nadd rax, 0Ch\ncmp rax, rsi\njnz short loc_118E\nloc_119F:\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n unsigned int v3; // ecx\n __int64 v4; // rax\n __int64 v5; // rsi\n\n v3 = *(_DWORD *)(a1 + 4LL * a3);\n if ( a2 > 1 )\n {\n v4 = a1 + 4LL * a3;\n v5 = a1 + 4 * (3LL * (unsigned int)(a2 - 2) + a3) + 12;\n do\n {\n if ( (signed int)v3 < *(_DWORD *)(v4 + 12) )\n v3 = *(_DWORD *)(v4 + 12);\n v4 += 12LL;\n }\n while ( v4 != v5 );\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmovsxd rax, edx\nmov ecx, [rdi+rax*4]\ncmp esi, 1\njle short loc_119F\nmov rdx, rax\nlea rax, [rdi+rax*4]\nlea esi, [rsi-2]\nlea rsi, [rsi+rsi*2]\nadd rdx, rsi\nlea rsi, [rdi+rdx*4+0Ch]\nloc_118E:\nmov edx, [rax+0Ch]\ncmp ecx, edx\ncmovl ecx, edx\nadd rax, 0Ch\ncmp rax, rsi\njnz short loc_118E\nloc_119F:\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n unsigned int v3; // ecx\n __int64 v4; // rax\n __int64 v5; // rsi\n\n v3 = *(_DWORD *)(a1 + 4LL * a3);\n if ( a2 > 1 )\n {\n v4 = a1 + 4LL * a3;\n v5 = a1 + 4 * (3LL * (unsigned int)(a2 - 2) + a3) + 12;\n do\n {\n if ( (signed int)v3 < *(_DWORD *)(v4 + 12) )\n v3 = *(_DWORD *)(v4 + 12);\n v4 += 12LL;\n }\n while ( v4 != v5 );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n unsigned int v3;\n long long v4;\n long long v5;\n v3 = *(uint32_t *)(a1 + 4LL * a3);\n if (a2 > 1) {\n v4 = a1 + 4LL * a3;\n v5 = a1 + 4 * (3LL * (unsigned int)(a2 - 2) + a3) + 12;\n do {\n if ((signed int)v3 < *(uint32_t *)(v4 + 12)) v3 = *(uint32_t *)(v4 + 12);\n v4 += 12LL;\n } while (v4 != v5);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n unsigned int v3;\n long long v4;\n long long v5;\n v3 = *(uint32_t *)(a1 + 4LL * a3);\n if (a2 > 1) {\n v4 = a1 + 4LL * a3;\n v5 = a1 + 4 * (3LL * (unsigned int)(a2 - 2) + a3) + 12;\n do {\n if ((signed int)v3 < *(uint32_t *)(v4 + 12)) v3 = *(uint32_t *)(v4 + 12);\n v4 += 12LL;\n } while (v4 != v5);\n }\n return v3;\n}" + }, + { + "index": 612, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int** func0(int** lst, int rows, int cols) {\n int** result = malloc(sizeof(int*) * cols);\n for (int i = 0; i < cols; i++) {\n result[i] = malloc(sizeof(int) * rows);\n for (int j = 0; j < rows; j++) {\n result[i][j] = lst[j][i];\n }\n }\n return result;\n}", + "test": "int main() {\n\n int* test1[] = {(int[]){1, 2}, (int[]){3, 4}, (int[]){5, 6}, (int[]){7, 8}};\n\n int** result1 = func0(test1, 4, 2);\n\n assert(result1[0][0] == 1 && result1[0][1] == 3 && result1[0][2] == 5 && result1[0][3] == 7);\n\n assert(result1[1][0] == 2 && result1[1][1] == 4 && result1[1][2] == 6 && result1[1][3] == 8);\n\n\n\n int* test2[] = {(int[]){'x', 'y'}, (int[]){'a', 'b'}, (int[]){'m', 'n'}};\n\n int** result2 = func0(test2, 3, 2);\n\n assert(result2[0][0] == 'x' && result2[0][1] == 'a' && result2[0][2] == 'm');\n\n assert(result2[1][0] == 'y' && result2[1][1] == 'b' && result2[1][2] == 'n');\n\n\n\n int* test3[] = {(int[]){'x', 'y', 'z'}, (int[]){'a', 'b', 'c'}, (int[]){'m', 'n', 'o'}};\n\n int** result3 = func0(test3, 3, 3);\n\n assert(result3[0][0] == 'x' && result3[0][1] == 'a' && result3[0][2] == 'm');\n\n assert(result3[1][0] == 'y' && result3[1][1] == 'b' && result3[1][2] == 'n');\n\n assert(result3[2][0] == 'z' && result3[2][1] == 'c' && result3[2][2] == 'o');\n\n\n\n // Free allocated memory\n\n for (int i = 0; i < 2; i++) free(result1[i]);\n\n free(result1);\n\n for (int i = 0; i < 2; i++) free(result2[i]);\n\n free(result2);\n\n for (int i = 0; i < 3; i++) free(result3[i]);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x28,%rsp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmov %edx,-0x30(%rbp)\nmov -0x30(%rbp),%eax\ncltq\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x18(%rbp)\nmovl $0x0,-0x20(%rbp)\njmpq 1271 \nmov -0x2c(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov -0x20(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x18(%rbp),%rdx\nlea (%rcx,%rdx,1),%rbx\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,(%rbx)\nmovl $0x0,-0x1c(%rbp)\njmp 1265 \nmov -0x1c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0x20(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x2,%rdx\nadd %rdx,%rax\nmov -0x20(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rdx),%rdx\nmov -0x1c(%rbp),%ecx\nmovslq %ecx,%rcx\nshl $0x2,%rcx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x1c(%rbp)\nmov -0x1c(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 1214 \naddl $0x1,-0x20(%rbp)\nmov -0x20(%rbp),%eax\ncmp -0x30(%rbp),%eax\njl 11e1 \nmov -0x18(%rbp),%rax\nadd $0x28,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_30], edx\nmov eax, [rbp+var_30]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_20], 0\njmp loc_1271\nloc_11E1:\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nlea rbx, [rcx+rdx]\nmov rdi, rax; size\ncall _malloc\nmov [rbx], rax\nmov [rbp+var_1C], 0\njmp short loc_1265\nloc_1214:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov rdx, [rdx]\nmov ecx, [rbp+var_1C]\nmovsxd rcx, ecx\nshl rcx, 2\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_1C], 1\nloc_1265:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_2C]\njl short loc_1214\nadd [rbp+var_20], 1\nloc_1271:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_30]\njl loc_11E1\nmov rax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, int a2, int a3)\n{\n int i; // [rsp+10h] [rbp-20h]\n int j; // [rsp+14h] [rbp-1Ch]\n _QWORD *v7; // [rsp+18h] [rbp-18h]\n\n v7 = malloc(8LL * a3);\n for ( i = 0; i < a3; ++i )\n {\n v7[i] = malloc(4LL * a2);\n for ( j = 0; j < a2; ++j )\n *(_DWORD *)(4LL * j + v7[i]) = *(_DWORD *)(4LL * i + *(_QWORD *)(8LL * j + a1));\n }\n return v7;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_30], edx\nmov eax, [rbp+var_30]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_20], 0\njmp loc_1271\nloc_11E1:\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nlea rbx, [rcx+rdx]\nmov rdi, rax; size\ncall _malloc\nmov [rbx], rax\nmov [rbp+var_1C], 0\njmp short loc_1265\nloc_1214:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov rdx, [rdx]\nmov ecx, [rbp+var_1C]\nmovsxd rcx, ecx\nshl rcx, 2\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_1C], 1\nloc_1265:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_2C]\njl short loc_1214\nadd [rbp+var_20], 1\nloc_1271:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_30]\njl loc_11E1\nmov rax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11A9(__int64 a1, int a2, int a3)\n{\n int i; // [rsp+10h] [rbp-20h]\n int j; // [rsp+14h] [rbp-1Ch]\n _QWORD *v7; // [rsp+18h] [rbp-18h]\n\n v7 = malloc(8LL * a3);\n for ( i = 0; i < a3; ++i )\n {\n v7[i] = malloc(4LL * a2);\n for ( j = 0; j < a2; ++j )\n *(_DWORD *)(4LL * j + v7[i]) = *(_DWORD *)(4LL * i + *(_QWORD *)(8LL * j + a1));\n }\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11A9(long long a1, int a2, int a3) {\n int i;\n int j;\n uint64_t *v7;\n v7 = malloc(8LL * a3);\n for (i = 0; i < a3; ++i) {\n v7[i] = malloc(4LL * a2);\n for (j = 0; j < a2; ++j)\n *(uint32_t *)(4LL * j + v7[i]) =\n *(uint32_t *)(4LL * i + *(uint64_t *)(8LL * j + a1));\n }\n return v7;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, int a2, int a3) {\n int i;\n int j;\n uint64_t *v7;\n v7 = malloc(8LL * a3);\n for (i = 0; i < a3; ++i) {\n v7[i] = malloc(4LL * a2);\n for (j = 0; j < a2; ++j)\n *(uint32_t *)(4LL * j + v7[i]) =\n *(uint32_t *)(4LL * i + *(uint64_t *)(8LL * j + a1));\n }\n return v7;\n}" + }, + { + "index": 612, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int** func0(int** lst, int rows, int cols) {\n int** result = malloc(sizeof(int*) * cols);\n for (int i = 0; i < cols; i++) {\n result[i] = malloc(sizeof(int) * rows);\n for (int j = 0; j < rows; j++) {\n result[i][j] = lst[j][i];\n }\n }\n return result;\n}", + "test": "int main() {\n\n int* test1[] = {(int[]){1, 2}, (int[]){3, 4}, (int[]){5, 6}, (int[]){7, 8}};\n\n int** result1 = func0(test1, 4, 2);\n\n assert(result1[0][0] == 1 && result1[0][1] == 3 && result1[0][2] == 5 && result1[0][3] == 7);\n\n assert(result1[1][0] == 2 && result1[1][1] == 4 && result1[1][2] == 6 && result1[1][3] == 8);\n\n\n\n int* test2[] = {(int[]){'x', 'y'}, (int[]){'a', 'b'}, (int[]){'m', 'n'}};\n\n int** result2 = func0(test2, 3, 2);\n\n assert(result2[0][0] == 'x' && result2[0][1] == 'a' && result2[0][2] == 'm');\n\n assert(result2[1][0] == 'y' && result2[1][1] == 'b' && result2[1][2] == 'n');\n\n\n\n int* test3[] = {(int[]){'x', 'y', 'z'}, (int[]){'a', 'b', 'c'}, (int[]){'m', 'n', 'o'}};\n\n int** result3 = func0(test3, 3, 3);\n\n assert(result3[0][0] == 'x' && result3[0][1] == 'a' && result3[0][2] == 'm');\n\n assert(result3[1][0] == 'y' && result3[1][1] == 'b' && result3[1][2] == 'n');\n\n assert(result3[2][0] == 'z' && result3[2][1] == 'c' && result3[2][2] == 'o');\n\n\n\n // Free allocated memory\n\n for (int i = 0; i < 2; i++) free(result1[i]);\n\n free(result1);\n\n for (int i = 0; i < 2; i++) free(result2[i]);\n\n free(result2);\n\n for (int i = 0; i < 3; i++) free(result3[i]);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov %rdi,%rbp\nmov %esi,%r14d\nmov %edx,%ebx\nmovslq %edx,%rdi\nshl $0x3,%rdi\ncallq 10b0 \nmov %rax,0x8(%rsp)\ntest %ebx,%ebx\njle 1244 \nmov %rax,%rdi\nmovslq %r14d,%rax\nshl $0x2,%rax\nmov %rax,(%rsp)\nmov %rdi,%r13\nlea -0x1(%rbx),%eax\nlea 0x8(%rdi,%rax,8),%r15\nlea -0x1(%r14),%eax\nlea 0x4(,%rax,4),%r12\nmov $0x0,%ebx\njmp 1211 \nadd $0x8,%r13\nadd $0x4,%rbx\ncmp %r15,%r13\nje 1244 \nmov (%rsp),%rdi\ncallq 10b0 \nmov %r13,%rsi\nmov %rax,0x0(%r13)\ntest %r14d,%r14d\njle 1204 \nmov $0x0,%eax\nmov 0x0(%rbp,%rax,2),%rdx\nmov (%rdx,%rbx,1),%ecx\nmov (%rsi),%rdx\nmov %ecx,(%rdx,%rax,1)\nadd $0x4,%rax\ncmp %r12,%rax\njne 122b \njmp 1204 \nmov 0x8(%rsp),%rax\nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov rbp, rdi\nmov r14d, esi\nmov ebx, edx\nmovsxd r15, edx\nlea rdi, ds:0[r15*8]; size\ncall _malloc\nmov r13, rax\ntest ebx, ebx\njle short loc_1229\nmovsxd r12, r14d\nlea rax, ds:0[r12*4]\nmov [rsp+48h+size], rax\nshl r15, 2\nmov ebx, 0\nloc_11F3:\nmov rdi, [rsp+48h+size]; size\ncall _malloc\nmov [r13+rbx*2+0], rax\ntest r14d, r14d\njle short loc_1220\nmov edx, 0\nloc_120C:\nmov rcx, [rbp+rdx*8+0]\nmov ecx, [rcx+rbx]\nmov [rax+rdx*4], ecx\nadd rdx, 1\ncmp r12, rdx\njnz short loc_120C\nloc_1220:\nadd rbx, 4\ncmp rbx, r15\njnz short loc_11F3\nloc_1229:\nmov rax, r13\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2, int a3)\n{\n __int64 v4; // r15\n char *v5; // r13\n __int64 v6; // r15\n __int64 v7; // rbx\n _DWORD *v8; // rax\n __int64 i; // rdx\n\n v4 = a3;\n v5 = (char *)malloc(8LL * a3);\n if ( a3 > 0 )\n {\n v6 = 4 * v4;\n v7 = 0LL;\n do\n {\n v8 = malloc(4LL * a2);\n *(_QWORD *)&v5[2 * v7] = v8;\n if ( a2 > 0 )\n {\n for ( i = 0LL; i != a2; ++i )\n v8[i] = *(_DWORD *)(*(_QWORD *)(a1 + 8 * i) + v7);\n }\n v7 += 4LL;\n }\n while ( v7 != v6 );\n }\n return v5;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov rbp, rdi\nmov r14d, esi\nmov ebx, edx\nmovsxd r15, edx\nlea rdi, ds:0[r15*8]; size\ncall _malloc\nmov r13, rax\ntest ebx, ebx\njle short loc_1229\nmovsxd r12, r14d\nlea rax, ds:0[r12*4]\nmov [rsp+48h+size], rax\nshl r15, 2\nmov ebx, 0\nloc_11F3:\nmov rdi, [rsp+48h+size]; size\ncall _malloc\nmov [r13+rbx*2+0], rax\ntest r14d, r14d\njle short loc_1220\nmov edx, 0\nloc_120C:\nmov rcx, [rbp+rdx*8+0]\nmov ecx, [rcx+rbx]\nmov [rax+rdx*4], ecx\nadd rdx, 1\ncmp r12, rdx\njnz short loc_120C\nloc_1220:\nadd rbx, 4\ncmp rbx, r15\njnz short loc_11F3\nloc_1229:\nmov rax, r13\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11A9(__int64 a1, int a2, int a3)\n{\n __int64 v4; // r15\n char *v5; // r13\n __int64 v6; // r15\n __int64 v7; // rbx\n _DWORD *v8; // rax\n __int64 i; // rdx\n\n v4 = a3;\n v5 = (char *)malloc(8LL * a3);\n if ( a3 > 0 )\n {\n v6 = 4 * v4;\n v7 = 0LL;\n do\n {\n v8 = malloc(4LL * a2);\n *(_QWORD *)&v5[2 * v7] = v8;\n if ( a2 > 0 )\n {\n for ( i = 0LL; i != a2; ++i )\n v8[i] = *(_DWORD *)(*(_QWORD *)(a1 + 8 * i) + v7);\n }\n v7 += 4LL;\n }\n while ( v7 != v6 );\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11A9(long long a1, int a2, int a3) {\n long long v4;\n char *v5;\n long long v6;\n long long v7;\n uint32_t *v8;\n long long i;\n v4 = a3;\n v5 = (char *)malloc(8LL * a3);\n if (a3 > 0) {\n v6 = 4 * v4;\n v7 = 0LL;\n do {\n v8 = malloc(4LL * a2);\n *(uint64_t *)&v5[2 * v7] = v8;\n if (a2 > 0) {\n for (i = 0LL; i != a2; ++i)\n v8[i] = *(uint32_t *)(*(uint64_t *)(a1 + 8 * i) + v7);\n }\n v7 += 4LL;\n } while (v7 != v6);\n }\n return v5;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2, int a3) {\n long long v4;\n char *v5;\n long long v6;\n long long v7;\n uint32_t *v8;\n long long i;\n v4 = a3;\n v5 = (char *)malloc(8LL * a3);\n if (a3 > 0) {\n v6 = 4 * v4;\n v7 = 0LL;\n do {\n v8 = malloc(4LL * a2);\n *(uint64_t *)&v5[2 * v7] = v8;\n if (a2 > 0) {\n for (i = 0LL; i != a2; ++i)\n v8[i] = *(uint32_t *)(*(uint64_t *)(a1 + 8 * i) + v7);\n }\n v7 += 4LL;\n } while (v7 != v6);\n }\n return v5;\n}" + }, + { + "index": 612, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int** func0(int** lst, int rows, int cols) {\n int** result = malloc(sizeof(int*) * cols);\n for (int i = 0; i < cols; i++) {\n result[i] = malloc(sizeof(int) * rows);\n for (int j = 0; j < rows; j++) {\n result[i][j] = lst[j][i];\n }\n }\n return result;\n}", + "test": "int main() {\n\n int* test1[] = {(int[]){1, 2}, (int[]){3, 4}, (int[]){5, 6}, (int[]){7, 8}};\n\n int** result1 = func0(test1, 4, 2);\n\n assert(result1[0][0] == 1 && result1[0][1] == 3 && result1[0][2] == 5 && result1[0][3] == 7);\n\n assert(result1[1][0] == 2 && result1[1][1] == 4 && result1[1][2] == 6 && result1[1][3] == 8);\n\n\n\n int* test2[] = {(int[]){'x', 'y'}, (int[]){'a', 'b'}, (int[]){'m', 'n'}};\n\n int** result2 = func0(test2, 3, 2);\n\n assert(result2[0][0] == 'x' && result2[0][1] == 'a' && result2[0][2] == 'm');\n\n assert(result2[1][0] == 'y' && result2[1][1] == 'b' && result2[1][2] == 'n');\n\n\n\n int* test3[] = {(int[]){'x', 'y', 'z'}, (int[]){'a', 'b', 'c'}, (int[]){'m', 'n', 'o'}};\n\n int** result3 = func0(test3, 3, 3);\n\n assert(result3[0][0] == 'x' && result3[0][1] == 'a' && result3[0][2] == 'm');\n\n assert(result3[1][0] == 'y' && result3[1][1] == 'b' && result3[1][2] == 'n');\n\n assert(result3[2][0] == 'z' && result3[2][1] == 'c' && result3[2][2] == 'o');\n\n\n\n // Free allocated memory\n\n for (int i = 0; i < 2; i++) free(result1[i]);\n\n free(result1);\n\n for (int i = 0; i < 2; i++) free(result2[i]);\n\n free(result2);\n\n for (int i = 0; i < 3; i++) free(result3[i]);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\nmov %rdi,%r14\nmovslq %edx,%rdi\npush %r13\nmov %rdi,%r13\nshl $0x3,%rdi\npush %r12\npush %rbp\npush %rbx\nmov %esi,%ebx\nsub $0x18,%rsp\ncallq 10b0 \nmov %rax,%r12\ntest %r13d,%r13d\njle 1630 \nlea -0x1(%r13),%eax\nmovslq %ebx,%rbp\nxor %r15d,%r15d\nlea 0x4(,%rax,4),%r13\nlea -0x1(%rbx),%eax\nshl $0x2,%rbp\nmov %eax,0xc(%rsp)\nnopl 0x0(%rax,%rax,1)\nmov %rbp,%rdi\ncallq 10b0 \nmov %rax,(%r12,%r15,2)\ntest %ebx,%ebx\njle 1627 \nmov 0xc(%rsp),%esi\nxor %edx,%edx\nnopw %cs:0x0(%rax,%rax,1)\nmov (%r14,%rdx,8),%rcx\nmov (%rcx,%r15,1),%ecx\nmov %ecx,(%rax,%rdx,4)\nmov %rdx,%rcx\nadd $0x1,%rdx\ncmp %rcx,%rsi\njne 1610 \nadd $0x4,%r15\ncmp %r13,%r15\njne 15f0 \nadd $0x18,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov r15, rdi\npush r14\npush r13\npush r12\nmovsxd r12, edx\npush rbp\nlea rdi, ds:0[r12*8]; size\nmov ebp, esi\npush rbx\nsub rsp, 18h\ncall _malloc\nmov rbx, rax\ntest r12d, r12d\njle short loc_1645\nmovsxd r13, ebp\nshl r12, 2\nxor r14d, r14d\nlea rax, ds:0[r13*4]\nmov [rsp+48h+size], rax\nnop word ptr [rax+rax+00000000h]\nloc_1610:\nmov rdi, [rsp+48h+size]; size\ncall _malloc\nmov [rbx+r14*2], rax\ntest ebp, ebp\njle short loc_163C\nxor edx, edx\nnop dword ptr [rax+00h]\nloc_1628:\nmov rcx, [r15+rdx*8]\nmov ecx, [rcx+r14]\nmov [rax+rdx*4], ecx\nadd rdx, 1\ncmp r13, rdx\njnz short loc_1628\nloc_163C:\nadd r14, 4\ncmp r12, r14\njnz short loc_1610\nloc_1645:\nadd rsp, 18h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2, int a3)\n{\n __int64 v3; // r12\n char *v4; // rbx\n __int64 v5; // r12\n __int64 v6; // r14\n _DWORD *v7; // rax\n __int64 i; // rdx\n\n v3 = a3;\n v4 = (char *)malloc(8LL * a3);\n if ( (int)v3 > 0 )\n {\n v5 = 4 * v3;\n v6 = 0LL;\n do\n {\n v7 = malloc(4LL * a2);\n *(_QWORD *)&v4[2 * v6] = v7;\n if ( a2 > 0 )\n {\n for ( i = 0LL; i != a2; ++i )\n v7[i] = *(_DWORD *)(*(_QWORD *)(a1 + 8 * i) + v6);\n }\n v6 += 4LL;\n }\n while ( v5 != v6 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_15C0:\nendbr64\npush r15\nmov r15, rdi\npush r14\npush r13\npush r12\nmovsxd r12, edx\npush rbp\nlea rdi, ds:0[r12*8]; size\nmov ebp, esi\npush rbx\nsub rsp, 18h\ncall _malloc\nmov rbx, rax\ntest r12d, r12d\njle short loc_1645\nmovsxd r13, ebp\nshl r12, 2\nxor r14d, r14d\nlea rax, ds:0[r13*4]\nmov [rsp+48h+size], rax\nnop word ptr [rax+rax+00000000h]\nloc_1610:\nmov rdi, [rsp+48h+size]; size\ncall _malloc\nmov [rbx+r14*2], rax\ntest ebp, ebp\njle short loc_163C\nxor edx, edx\nnop dword ptr [rax+00h]\nloc_1628:\nmov rcx, [r15+rdx*8]\nmov ecx, [rcx+r14]\nmov [rax+rdx*4], ecx\nadd rdx, 1\ncmp r13, rdx\njnz short loc_1628\nloc_163C:\nadd r14, 4\ncmp r12, r14\njnz short loc_1610\nloc_1645:\nadd rsp, 18h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "char *__fastcall sub_15C0(__int64 a1, int a2, int a3)\n{\n __int64 v3; // r12\n char *v4; // rbx\n __int64 v5; // r12\n __int64 v6; // r14\n _DWORD *v7; // rax\n __int64 i; // rdx\n\n v3 = a3;\n v4 = (char *)malloc(8LL * a3);\n if ( (int)v3 > 0 )\n {\n v5 = 4 * v3;\n v6 = 0LL;\n do\n {\n v7 = malloc(4LL * a2);\n *(_QWORD *)&v4[2 * v6] = v7;\n if ( a2 > 0 )\n {\n for ( i = 0LL; i != a2; ++i )\n v7[i] = *(_DWORD *)(*(_QWORD *)(a1 + 8 * i) + v6);\n }\n v6 += 4LL;\n }\n while ( v5 != v6 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_15C0(long long a1, int a2, int a3) {\n long long v3;\n char *v4;\n long long v5;\n long long v6;\n uint32_t *v7;\n long long i;\n v3 = a3;\n v4 = (char *)malloc(8LL * a3);\n if ((int)v3 > 0) {\n v5 = 4 * v3;\n v6 = 0LL;\n do {\n v7 = malloc(4LL * a2);\n *(uint64_t *)&v4[2 * v6] = v7;\n if (a2 > 0) {\n for (i = 0LL; i != a2; ++i)\n v7[i] = *(uint32_t *)(*(uint64_t *)(a1 + 8 * i) + v6);\n }\n v6 += 4LL;\n } while (v5 != v6);\n }\n return v4;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2, int a3) {\n long long v3;\n char *v4;\n long long v5;\n long long v6;\n uint32_t *v7;\n long long i;\n v3 = a3;\n v4 = (char *)malloc(8LL * a3);\n if ((int)v3 > 0) {\n v5 = 4 * v3;\n v6 = 0LL;\n do {\n v7 = malloc(4LL * a2);\n *(uint64_t *)&v4[2 * v6] = v7;\n if (a2 > 0) {\n for (i = 0LL; i != a2; ++i)\n v7[i] = *(uint32_t *)(*(uint64_t *)(a1 + 8 * i) + v6);\n }\n v6 += 4LL;\n } while (v5 != v6);\n }\n return v4;\n}" + }, + { + "index": 612, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int** func0(int** lst, int rows, int cols) {\n int** result = malloc(sizeof(int*) * cols);\n for (int i = 0; i < cols; i++) {\n result[i] = malloc(sizeof(int) * rows);\n for (int j = 0; j < rows; j++) {\n result[i][j] = lst[j][i];\n }\n }\n return result;\n}", + "test": "int main() {\n\n int* test1[] = {(int[]){1, 2}, (int[]){3, 4}, (int[]){5, 6}, (int[]){7, 8}};\n\n int** result1 = func0(test1, 4, 2);\n\n assert(result1[0][0] == 1 && result1[0][1] == 3 && result1[0][2] == 5 && result1[0][3] == 7);\n\n assert(result1[1][0] == 2 && result1[1][1] == 4 && result1[1][2] == 6 && result1[1][3] == 8);\n\n\n\n int* test2[] = {(int[]){'x', 'y'}, (int[]){'a', 'b'}, (int[]){'m', 'n'}};\n\n int** result2 = func0(test2, 3, 2);\n\n assert(result2[0][0] == 'x' && result2[0][1] == 'a' && result2[0][2] == 'm');\n\n assert(result2[1][0] == 'y' && result2[1][1] == 'b' && result2[1][2] == 'n');\n\n\n\n int* test3[] = {(int[]){'x', 'y', 'z'}, (int[]){'a', 'b', 'c'}, (int[]){'m', 'n', 'o'}};\n\n int** result3 = func0(test3, 3, 3);\n\n assert(result3[0][0] == 'x' && result3[0][1] == 'a' && result3[0][2] == 'm');\n\n assert(result3[1][0] == 'y' && result3[1][1] == 'b' && result3[1][2] == 'n');\n\n assert(result3[2][0] == 'z' && result3[2][1] == 'c' && result3[2][2] == 'o');\n\n\n\n // Free allocated memory\n\n for (int i = 0; i < 2; i++) free(result1[i]);\n\n free(result1);\n\n for (int i = 0; i < 2; i++) free(result2[i]);\n\n free(result2);\n\n for (int i = 0; i < 3; i++) free(result3[i]);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\nmov %rdi,%r14\nmovslq %edx,%rdi\npush %r13\nmov %rdi,%r13\nshl $0x3,%rdi\npush %r12\npush %rbp\npush %rbx\nmov %esi,%ebx\nsub $0x18,%rsp\ncallq 10b0 \nmov %rax,%r12\ntest %r13d,%r13d\njle 1650 \nlea -0x1(%r13),%eax\nmovslq %ebx,%rbp\nxor %r15d,%r15d\nlea 0x4(,%rax,4),%r13\nlea -0x1(%rbx),%eax\nshl $0x2,%rbp\nmov %eax,0xc(%rsp)\nnopl 0x0(%rax,%rax,1)\nmov %rbp,%rdi\ncallq 10b0 \nmov %rax,(%r12,%r15,2)\ntest %ebx,%ebx\njle 1647 \nmov 0xc(%rsp),%esi\nxor %edx,%edx\nnopw %cs:0x0(%rax,%rax,1)\nmov (%r14,%rdx,8),%rcx\nmov (%rcx,%r15,1),%ecx\nmov %ecx,(%rax,%rdx,4)\nmov %rdx,%rcx\nadd $0x1,%rdx\ncmp %rsi,%rcx\njne 1630 \nadd $0x4,%r15\ncmp %r15,%r13\njne 1610 \nadd $0x18,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov r15, rdi\npush r14\npush r13\npush r12\nmovsxd r12, edx\npush rbp\nlea rdi, ds:0[r12*8]; size\nmov ebp, esi\npush rbx\nsub rsp, 18h\ncall _malloc\nmov rbx, rax\ntest r12d, r12d\njle short loc_1645\nmovsxd r13, ebp\nshl r12, 2\nxor r14d, r14d\nlea rax, ds:0[r13*4]\nmov [rsp+48h+size], rax\nnop word ptr [rax+rax+00000000h]\nloc_1610:\nmov rdi, [rsp+48h+size]; size\ncall _malloc\nmov [rbx+r14*2], rax\ntest ebp, ebp\njle short loc_163C\nxor edx, edx\nnop dword ptr [rax+00h]\nloc_1628:\nmov rcx, [r15+rdx*8]\nmov ecx, [rcx+r14]\nmov [rax+rdx*4], ecx\nadd rdx, 1\ncmp r13, rdx\njnz short loc_1628\nloc_163C:\nadd r14, 4\ncmp r12, r14\njnz short loc_1610\nloc_1645:\nadd rsp, 18h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2, int a3)\n{\n __int64 v3; // r12\n char *v4; // rbx\n __int64 v5; // r12\n __int64 v6; // r14\n _DWORD *v7; // rax\n __int64 i; // rdx\n\n v3 = a3;\n v4 = (char *)malloc(8LL * a3);\n if ( (int)v3 > 0 )\n {\n v5 = 4 * v3;\n v6 = 0LL;\n do\n {\n v7 = malloc(4LL * a2);\n *(_QWORD *)&v4[2 * v6] = v7;\n if ( a2 > 0 )\n {\n for ( i = 0LL; i != a2; ++i )\n v7[i] = *(_DWORD *)(*(_QWORD *)(a1 + 8 * i) + v6);\n }\n v6 += 4LL;\n }\n while ( v5 != v6 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_15C0:\nendbr64\npush r15\nmov r15, rdi\npush r14\npush r13\npush r12\nmovsxd r12, edx\npush rbp\nlea rdi, ds:0[r12*8]; size\nmov ebp, esi\npush rbx\nsub rsp, 18h\ncall _malloc\nmov rbx, rax\ntest r12d, r12d\njle short loc_1645\nmovsxd r13, ebp\nshl r12, 2\nxor r14d, r14d\nlea rax, ds:0[r13*4]\nmov [rsp+48h+size], rax\nnop word ptr [rax+rax+00000000h]\nloc_1610:\nmov rdi, [rsp+48h+size]; size\ncall _malloc\nmov [rbx+r14*2], rax\ntest ebp, ebp\njle short loc_163C\nxor edx, edx\nnop dword ptr [rax+00h]\nloc_1628:\nmov rcx, [r15+rdx*8]\nmov ecx, [rcx+r14]\nmov [rax+rdx*4], ecx\nadd rdx, 1\ncmp r13, rdx\njnz short loc_1628\nloc_163C:\nadd r14, 4\ncmp r12, r14\njnz short loc_1610\nloc_1645:\nadd rsp, 18h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "char *__fastcall sub_15C0(__int64 a1, int a2, int a3)\n{\n __int64 v3; // r12\n char *v4; // rbx\n __int64 v5; // r12\n __int64 v6; // r14\n _DWORD *v7; // rax\n __int64 i; // rdx\n\n v3 = a3;\n v4 = (char *)malloc(8LL * a3);\n if ( (int)v3 > 0 )\n {\n v5 = 4 * v3;\n v6 = 0LL;\n do\n {\n v7 = malloc(4LL * a2);\n *(_QWORD *)&v4[2 * v6] = v7;\n if ( a2 > 0 )\n {\n for ( i = 0LL; i != a2; ++i )\n v7[i] = *(_DWORD *)(*(_QWORD *)(a1 + 8 * i) + v6);\n }\n v6 += 4LL;\n }\n while ( v5 != v6 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_15C0(long long a1, int a2, int a3) {\n long long v3;\n char *v4;\n long long v5;\n long long v6;\n uint32_t *v7;\n long long i;\n v3 = a3;\n v4 = (char *)malloc(8LL * a3);\n if ((int)v3 > 0) {\n v5 = 4 * v3;\n v6 = 0LL;\n do {\n v7 = malloc(4LL * a2);\n *(uint64_t *)&v4[2 * v6] = v7;\n if (a2 > 0) {\n for (i = 0LL; i != a2; ++i)\n v7[i] = *(uint32_t *)(*(uint64_t *)(a1 + 8 * i) + v6);\n }\n v6 += 4LL;\n } while (v5 != v6);\n }\n return v4;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2, int a3) {\n long long v3;\n char *v4;\n long long v5;\n long long v6;\n uint32_t *v7;\n long long i;\n v3 = a3;\n v4 = (char *)malloc(8LL * a3);\n if ((int)v3 > 0) {\n v5 = 4 * v3;\n v6 = 0LL;\n do {\n v7 = malloc(4LL * a2);\n *(uint64_t *)&v4[2 * v6] = v7;\n if (a2 > 0) {\n for (i = 0LL; i != a2; ++i)\n v7[i] = *(uint32_t *)(*(uint64_t *)(a1 + 8 * i) + v6);\n }\n v6 += 4LL;\n } while (v5 != v6);\n }\n return v4;\n}" + }, + { + "index": 613, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char *key;\n\n int *values;\n\n int length;\n\n} KeyValue;\n\n\n\ntypedef struct {\n\n KeyValue *items;\n\n int length;\n\n} KeyValueList;\n\n\n\ntypedef struct {\n\n char *key;\n\n int max_value;\n\n} Result;\n\n\n\n", + "func": "Result* func0(KeyValueList test_list) {\n Result* res = (Result*)malloc(test_list.length * sizeof(Result));\n for (int i = 0; i < test_list.length; i++) {\n int max = test_list.items[i].values[0];\n for (int j = 1; j < test_list.items[i].length; j++) {\n if (test_list.items[i].values[j] > max) {\n max = test_list.items[i].values[j];\n }\n }\n res[i].key = test_list.items[i].key;\n res[i].max_value = max;\n }\n return res;\n}", + "test": "int main() {\n\n int a1[] = {3, 4, 5}, a2[] = {1, 4, 2}, a3[] = {9, 3};\n\n KeyValue items1[] = {{\"key1\", a1, 3}, {\"key2\", a2, 3}, {\"key3\", a3, 2}};\n\n KeyValueList kv1 = {items1, 3};\n\n\n\n int a4[] = {4, 5, 6}, a5[] = {2, 5, 3}, a6[] = {10, 4};\n\n KeyValue items2[] = {{\"key1\", a4, 3}, {\"key2\", a5, 3}, {\"key3\", a6, 2}};\n\n KeyValueList kv2 = {items2, 3};\n\n\n\n int a7[] = {5, 6, 7}, a8[] = {3, 6, 4}, a9[] = {11, 5};\n\n KeyValue items3[] = {{\"key1\", a7, 3}, {\"key2\", a8, 3}, {\"key3\", a9, 2}};\n\n KeyValueList kv3 = {items3, 3};\n\n\n\n Result *result1 = func0(kv1);\n\n Result *result2 = func0(kv2);\n\n Result *result3 = func0(kv3);\n\n\n\n assert(result1[0].max_value == 5 && result1[1].max_value == 4 && result1[2].max_value == 9);\n\n assert(result2[0].max_value == 6 && result2[1].max_value == 5 && result2[2].max_value == 10);\n\n assert(result3[0].max_value == 7 && result3[1].max_value == 6 && result3[2].max_value == 11);\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,%rax\nmov %rsi,%rcx\nmov %rcx,%rdx\nmov %rax,-0x30(%rbp)\nmov %rdx,-0x28(%rbp)\nmov -0x28(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0x14(%rbp)\njmpq 12f0 \nmov -0x30(%rbp),%rcx\nmov -0x14(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nadd %rcx,%rax\nmov 0x8(%rax),%rax\nmov (%rax),%eax\nmov %eax,-0x10(%rbp)\nmovl $0x1,-0xc(%rbp)\njmp 1279 \nmov -0x30(%rbp),%rcx\nmov -0x14(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nadd %rcx,%rax\nmov 0x8(%rax),%rax\nmov -0xc(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x2,%rdx\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x10(%rbp)\njge 1275 \nmov -0x30(%rbp),%rcx\nmov -0x14(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nadd %rcx,%rax\nmov 0x8(%rax),%rax\nmov -0xc(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x2,%rdx\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x10(%rbp)\naddl $0x1,-0xc(%rbp)\nmov -0x30(%rbp),%rcx\nmov -0x14(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nadd %rcx,%rax\nmov 0x10(%rax),%eax\ncmp %eax,-0xc(%rbp)\njl 1213 \nmov -0x30(%rbp),%rcx\nmov -0x14(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nadd %rcx,%rax\nmov -0x14(%rbp),%edx\nmovslq %edx,%rdx\nmov %rdx,%rcx\nshl $0x4,%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%rax\nmov %rax,(%rdx)\nmov -0x14(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov -0x10(%rbp),%eax\nmov %eax,0x8(%rdx)\naddl $0x1,-0x14(%rbp)\nmov -0x28(%rbp),%eax\ncmp %eax,-0x14(%rbp)\njl 11e7 \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov rax, rdi\nmov rcx, rsi\nmov rdx, rcx\nmov [rbp+var_30], rax\nmov [rbp+var_28], rdx\nmov eax, dword ptr [rbp+var_28]\ncdqe\nshl rax, 4\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_14], 0\njmp loc_12F0\nloc_11E7:\nmov rcx, [rbp+var_30]\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nadd rax, rcx\nmov rax, [rax+8]\nmov eax, [rax]\nmov [rbp+var_10], eax\nmov [rbp+var_C], 1\njmp short loc_1279\nloc_1213:\nmov rcx, [rbp+var_30]\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nadd rax, rcx\nmov rax, [rax+8]\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_10], eax\njge short loc_1275\nmov rcx, [rbp+var_30]\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nadd rax, rcx\nmov rax, [rax+8]\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_10], eax\nloc_1275:\nadd [rbp+var_C], 1\nloc_1279:\nmov rcx, [rbp+var_30]\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nadd rax, rcx\nmov eax, [rax+10h]\ncmp [rbp+var_C], eax\njl loc_1213\nmov rcx, [rbp+var_30]\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nadd rax, rcx\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nmov rcx, rdx\nshl rcx, 4\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov rax, [rax]\nmov [rdx], rax\nmov eax, [rbp+var_14]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_10]\nmov [rdx+8], eax\nadd [rbp+var_14], 1\nloc_12F0:\nmov eax, dword ptr [rbp+var_28]\ncmp [rbp+var_14], eax\njl loc_11E7\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+1Ch] [rbp-14h]\n int v4; // [rsp+20h] [rbp-10h]\n int j; // [rsp+24h] [rbp-Ch]\n _QWORD *v6; // [rsp+28h] [rbp-8h]\n\n v6 = malloc(16LL * a2);\n for ( i = 0; i < a2; ++i )\n {\n v4 = **(_DWORD **)(a1 + 24LL * i + 8);\n for ( j = 1; j < *(_DWORD *)(a1 + 24LL * i + 16); ++j )\n {\n if ( v4 < *(_DWORD *)(4LL * j + *(_QWORD *)(a1 + 24LL * i + 8)) )\n v4 = *(_DWORD *)(4LL * j + *(_QWORD *)(a1 + 24LL * i + 8));\n }\n v6[2 * i] = *(_QWORD *)(a1 + 24LL * i);\n LODWORD(v6[2 * i + 1]) = v4;\n }\n return v6;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov rax, rdi\nmov rcx, rsi\nmov rdx, rcx\nmov [rbp+var_30], rax\nmov [rbp+var_28], rdx\nmov eax, dword ptr [rbp+var_28]\ncdqe\nshl rax, 4\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_14], 0\njmp loc_12F0\nloc_11E7:\nmov rcx, [rbp+var_30]\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nadd rax, rcx\nmov rax, [rax+8]\nmov eax, [rax]\nmov [rbp+var_10], eax\nmov [rbp+var_C], 1\njmp short loc_1279\nloc_1213:\nmov rcx, [rbp+var_30]\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nadd rax, rcx\nmov rax, [rax+8]\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_10], eax\njge short loc_1275\nmov rcx, [rbp+var_30]\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nadd rax, rcx\nmov rax, [rax+8]\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_10], eax\nloc_1275:\nadd [rbp+var_C], 1\nloc_1279:\nmov rcx, [rbp+var_30]\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nadd rax, rcx\nmov eax, [rax+10h]\ncmp [rbp+var_C], eax\njl loc_1213\nmov rcx, [rbp+var_30]\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nadd rax, rcx\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nmov rcx, rdx\nshl rcx, 4\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov rax, [rax]\nmov [rdx], rax\nmov eax, [rbp+var_14]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_10]\nmov [rdx+8], eax\nadd [rbp+var_14], 1\nloc_12F0:\nmov eax, dword ptr [rbp+var_28]\ncmp [rbp+var_14], eax\njl loc_11E7\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11A9(__int64 a1, int a2)\n{\n int i; // [rsp+1Ch] [rbp-14h]\n int v4; // [rsp+20h] [rbp-10h]\n int j; // [rsp+24h] [rbp-Ch]\n _QWORD *v6; // [rsp+28h] [rbp-8h]\n\n v6 = malloc(16LL * a2);\n for ( i = 0; i < a2; ++i )\n {\n v4 = **(_DWORD **)(a1 + 24LL * i + 8);\n for ( j = 1; j < *(_DWORD *)(a1 + 24LL * i + 16); ++j )\n {\n if ( v4 < *(_DWORD *)(4LL * j + *(_QWORD *)(a1 + 24LL * i + 8)) )\n v4 = *(_DWORD *)(4LL * j + *(_QWORD *)(a1 + 24LL * i + 8));\n }\n v6[2 * i] = *(_QWORD *)(a1 + 24LL * i);\n LODWORD(v6[2 * i + 1]) = v4;\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11A9(long long a1, int a2) {\n int i;\n int v4;\n int j;\n uint64_t *v6;\n v6 = malloc(16LL * a2);\n for (i = 0; i < a2; ++i) {\n v4 = **(uint32_t **)(a1 + 24LL * i + 8);\n for (j = 1; j < *(uint32_t *)(a1 + 24LL * i + 16); ++j) {\n if (v4 < *(uint32_t *)(4LL * j + *(uint64_t *)(a1 + 24LL * i + 8)))\n v4 = *(uint32_t *)(4LL * j + *(uint64_t *)(a1 + 24LL * i + 8));\n }\n v6[2 * i] = *(uint64_t *)(a1 + 24LL * i);\n LODWORD(v6[2 * i + 1]) = v4;\n }\n return v6;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, int a2) {\n int i;\n int v4;\n int j;\n uint64_t *v6;\n v6 = malloc(16LL * a2);\n for (i = 0; i < a2; ++i) {\n v4 = **(uint32_t **)(a1 + 24LL * i + 8);\n for (j = 1; j < *(uint32_t *)(a1 + 24LL * i + 16); ++j) {\n if (v4 < *(uint32_t *)(4LL * j + *(uint64_t *)(a1 + 24LL * i + 8)))\n v4 = *(uint32_t *)(4LL * j + *(uint64_t *)(a1 + 24LL * i + 8));\n }\n v6[2 * i] = *(uint64_t *)(a1 + 24LL * i);\n LODWORD(v6[2 * i + 1]) = v4;\n }\n return v6;\n}" + }, + { + "index": 613, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char *key;\n\n int *values;\n\n int length;\n\n} KeyValue;\n\n\n\ntypedef struct {\n\n KeyValue *items;\n\n int length;\n\n} KeyValueList;\n\n\n\ntypedef struct {\n\n char *key;\n\n int max_value;\n\n} Result;\n\n\n\n", + "func": "Result* func0(KeyValueList test_list) {\n Result* res = (Result*)malloc(test_list.length * sizeof(Result));\n for (int i = 0; i < test_list.length; i++) {\n int max = test_list.items[i].values[0];\n for (int j = 1; j < test_list.items[i].length; j++) {\n if (test_list.items[i].values[j] > max) {\n max = test_list.items[i].values[j];\n }\n }\n res[i].key = test_list.items[i].key;\n res[i].max_value = max;\n }\n return res;\n}", + "test": "int main() {\n\n int a1[] = {3, 4, 5}, a2[] = {1, 4, 2}, a3[] = {9, 3};\n\n KeyValue items1[] = {{\"key1\", a1, 3}, {\"key2\", a2, 3}, {\"key3\", a3, 2}};\n\n KeyValueList kv1 = {items1, 3};\n\n\n\n int a4[] = {4, 5, 6}, a5[] = {2, 5, 3}, a6[] = {10, 4};\n\n KeyValue items2[] = {{\"key1\", a4, 3}, {\"key2\", a5, 3}, {\"key3\", a6, 2}};\n\n KeyValueList kv2 = {items2, 3};\n\n\n\n int a7[] = {5, 6, 7}, a8[] = {3, 6, 4}, a9[] = {11, 5};\n\n KeyValue items3[] = {{\"key1\", a7, 3}, {\"key2\", a8, 3}, {\"key3\", a9, 2}};\n\n KeyValueList kv3 = {items3, 3};\n\n\n\n Result *result1 = func0(kv1);\n\n Result *result2 = func0(kv2);\n\n Result *result3 = func0(kv3);\n\n\n\n assert(result1[0].max_value == 5 && result1[1].max_value == 4 && result1[2].max_value == 9);\n\n assert(result2[0].max_value == 6 && result2[1].max_value == 5 && result2[2].max_value == 10);\n\n assert(result3[0].max_value == 7 && result3[1].max_value == 6 && result3[2].max_value == 11);\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbp\nmov %rsi,%rbx\nmovslq %esi,%rdi\nshl $0x4,%rdi\ncallq 10b0 \ntest %ebx,%ebx\njle 1227 \nmov %rbp,%r8\nmov %rax,%r9\nlea -0x1(%rbx),%r11d\nadd $0x1,%r11\nshl $0x4,%r11\nadd %rax,%r11\njmp 11f7 \nmov (%r10),%rdx\nmov %rdx,(%r9)\nmov %ecx,0x8(%r9)\nadd $0x18,%r8\nadd $0x10,%r9\ncmp %r11,%r9\nje 1227 \nmov %r8,%r10\nmov 0x8(%r8),%rsi\nmov (%rsi),%ecx\nmov 0x10(%r8),%edi\ncmp $0x1,%edi\njle 11e0 \nlea 0x4(%rsi),%rdx\nlea -0x2(%rdi),%edi\nlea 0x8(%rsi,%rdi,4),%rdi\nmov (%rdx),%esi\ncmp %esi,%ecx\ncmovl %esi,%ecx\nadd $0x4,%rdx\ncmp %rdi,%rdx\njne 1215 \njmp 11e0 \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nmov r12, rsi\nmovsxd r10, esi\nshl r10, 4\nmov rbp, r10\nmov rdi, r10; size\ncall _malloc\nmov r11, rax\ntest r12d, r12d\njle short loc_1220\nmov rdi, rbx\nmov r8, rax\nlea r10, [rbp+rax+0]\nloc_11DC:\nmov r9, rdi\nmov rcx, [rdi+8]\nmov edx, [rcx]\nmov esi, [rdi+10h]\ncmp esi, 1\njle short loc_1209\nlea rax, [rcx+4]\nlea esi, [rsi-2]\nlea rsi, [rcx+rsi*4+8]\nloc_11F9:\nmov ecx, [rax]\ncmp edx, ecx\ncmovl edx, ecx\nadd rax, 4\ncmp rax, rsi\njnz short loc_11F9\nloc_1209:\nmov rax, [r9]\nmov [r8], rax\nmov [r8+8], edx\nadd rdi, 18h\nadd r8, 10h\ncmp r8, r10\njnz short loc_11DC\nloc_1220:\nmov rax, r11\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2)\n{\n char *v2; // rax\n char *v3; // r11\n char *v4; // r8\n char *v5; // r10\n int *v6; // rcx\n int v7; // edx\n int v8; // esi\n int *v9; // rax\n __int64 v10; // rsi\n\n v2 = (char *)malloc(16LL * a2);\n v3 = v2;\n if ( a2 > 0 )\n {\n v4 = v2;\n v5 = &v2[16 * a2];\n do\n {\n v6 = *(int **)(a1 + 8);\n v7 = *v6;\n v8 = *(_DWORD *)(a1 + 16);\n if ( v8 > 1 )\n {\n v9 = v6 + 1;\n v10 = (__int64)&v6[v8 - 2 + 2];\n do\n {\n if ( v7 < *v9 )\n v7 = *v9;\n ++v9;\n }\n while ( v9 != (int *)v10 );\n }\n *(_QWORD *)v4 = *(_QWORD *)a1;\n *((_DWORD *)v4 + 2) = v7;\n a1 += 24LL;\n v4 += 16;\n }\n while ( v4 != v5 );\n }\n return v3;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nmov r12, rsi\nmovsxd r10, esi\nshl r10, 4\nmov rbp, r10\nmov rdi, r10; size\ncall _malloc\nmov r11, rax\ntest r12d, r12d\njle short loc_1220\nmov rdi, rbx\nmov r8, rax\nlea r10, [rbp+rax+0]\nloc_11DC:\nmov r9, rdi\nmov rcx, [rdi+8]\nmov edx, [rcx]\nmov esi, [rdi+10h]\ncmp esi, 1\njle short loc_1209\nlea rax, [rcx+4]\nlea esi, [rsi-2]\nlea rsi, [rcx+rsi*4+8]\nloc_11F9:\nmov ecx, [rax]\ncmp edx, ecx\ncmovl edx, ecx\nadd rax, 4\ncmp rax, rsi\njnz short loc_11F9\nloc_1209:\nmov rax, [r9]\nmov [r8], rax\nmov [r8+8], edx\nadd rdi, 18h\nadd r8, 10h\ncmp r8, r10\njnz short loc_11DC\nloc_1220:\nmov rax, r11\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11A9(__int64 a1, int a2)\n{\n char *v2; // rax\n char *v3; // r11\n char *v4; // r8\n char *v5; // r10\n int *v6; // rcx\n int v7; // edx\n int v8; // esi\n int *v9; // rax\n __int64 v10; // rsi\n\n v2 = (char *)malloc(16LL * a2);\n v3 = v2;\n if ( a2 > 0 )\n {\n v4 = v2;\n v5 = &v2[16 * a2];\n do\n {\n v6 = *(int **)(a1 + 8);\n v7 = *v6;\n v8 = *(_DWORD *)(a1 + 16);\n if ( v8 > 1 )\n {\n v9 = v6 + 1;\n v10 = (__int64)&v6[v8 - 2 + 2];\n do\n {\n if ( v7 < *v9 )\n v7 = *v9;\n ++v9;\n }\n while ( v9 != (int *)v10 );\n }\n *(_QWORD *)v4 = *(_QWORD *)a1;\n *((_DWORD *)v4 + 2) = v7;\n a1 += 24LL;\n v4 += 16;\n }\n while ( v4 != v5 );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11A9(long long a1, int a2) {\n char *v2;\n char *v3;\n char *v4;\n char *v5;\n int *v6;\n int v7;\n int v8;\n int *v9;\n long long v10;\n v2 = (char *)malloc(16LL * a2);\n v3 = v2;\n if (a2 > 0) {\n v4 = v2;\n v5 = &v2[16 * a2];\n do {\n v6 = *(int **)(a1 + 8);\n v7 = *v6;\n v8 = *(uint32_t *)(a1 + 16);\n if (v8 > 1) {\n v9 = v6 + 1;\n v10 = (long long)&v6[v8 - 2 + 2];\n do {\n if (v7 < *v9) v7 = *v9;\n ++v9;\n } while (v9 != (int *)v10);\n }\n *(uint64_t *)v4 = *(uint64_t *)a1;\n *((uint32_t *)v4 + 2) = v7;\n a1 += 24LL;\n v4 += 16;\n } while (v4 != v5);\n }\n return v3;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2) {\n char *v2;\n char *v3;\n char *v4;\n char *v5;\n int *v6;\n int v7;\n int v8;\n int *v9;\n long long v10;\n v2 = (char *)malloc(16LL * a2);\n v3 = v2;\n if (a2 > 0) {\n v4 = v2;\n v5 = &v2[16 * a2];\n do {\n v6 = *(int **)(a1 + 8);\n v7 = *v6;\n v8 = *(uint32_t *)(a1 + 16);\n if (v8 > 1) {\n v9 = v6 + 1;\n v10 = (long long)&v6[v8 - 2 + 2];\n do {\n if (v7 < *v9) v7 = *v9;\n ++v9;\n } while (v9 != (int *)v10);\n }\n *(uint64_t *)v4 = *(uint64_t *)a1;\n *((uint32_t *)v4 + 2) = v7;\n a1 += 24LL;\n v4 += 16;\n } while (v4 != v5);\n }\n return v3;\n}" + }, + { + "index": 613, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char *key;\n\n int *values;\n\n int length;\n\n} KeyValue;\n\n\n\ntypedef struct {\n\n KeyValue *items;\n\n int length;\n\n} KeyValueList;\n\n\n\ntypedef struct {\n\n char *key;\n\n int max_value;\n\n} Result;\n\n\n\n", + "func": "Result* func0(KeyValueList test_list) {\n Result* res = (Result*)malloc(test_list.length * sizeof(Result));\n for (int i = 0; i < test_list.length; i++) {\n int max = test_list.items[i].values[0];\n for (int j = 1; j < test_list.items[i].length; j++) {\n if (test_list.items[i].values[j] > max) {\n max = test_list.items[i].values[j];\n }\n }\n res[i].key = test_list.items[i].key;\n res[i].max_value = max;\n }\n return res;\n}", + "test": "int main() {\n\n int a1[] = {3, 4, 5}, a2[] = {1, 4, 2}, a3[] = {9, 3};\n\n KeyValue items1[] = {{\"key1\", a1, 3}, {\"key2\", a2, 3}, {\"key3\", a3, 2}};\n\n KeyValueList kv1 = {items1, 3};\n\n\n\n int a4[] = {4, 5, 6}, a5[] = {2, 5, 3}, a6[] = {10, 4};\n\n KeyValue items2[] = {{\"key1\", a4, 3}, {\"key2\", a5, 3}, {\"key3\", a6, 2}};\n\n KeyValueList kv2 = {items2, 3};\n\n\n\n int a7[] = {5, 6, 7}, a8[] = {3, 6, 4}, a9[] = {11, 5};\n\n KeyValue items3[] = {{\"key1\", a7, 3}, {\"key2\", a8, 3}, {\"key3\", a9, 2}};\n\n KeyValueList kv3 = {items3, 3};\n\n\n\n Result *result1 = func0(kv1);\n\n Result *result2 = func0(kv2);\n\n Result *result3 = func0(kv3);\n\n\n\n assert(result1[0].max_value == 5 && result1[1].max_value == 4 && result1[2].max_value == 9);\n\n assert(result2[0].max_value == 6 && result2[1].max_value == 5 && result2[2].max_value == 10);\n\n assert(result3[0].max_value == 7 && result3[1].max_value == 6 && result3[2].max_value == 11);\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rdi,%rbp\nmovslq %esi,%rdi\npush %rbx\nshl $0x4,%rdi\nmov %rsi,%rbx\nsub $0x8,%rsp\ncallq 10b0 \ntest %ebx,%ebx\njle 1550 \nlea -0x1(%rbx),%r10d\nmov %rbp,%r8\nmov %rax,%r9\nadd $0x1,%r10\nshl $0x4,%r10\nadd %rax,%r10\nnopl (%rax)\nmov 0x8(%r8),%rsi\nmov 0x10(%r8),%edi\nmov (%rsi),%ecx\ncmp $0x1,%edi\njle 1538 \nsub $0x2,%edi\nlea 0x4(%rsi),%rdx\nlea 0x8(%rsi,%rdi,4),%rdi\nnopl 0x0(%rax,%rax,1)\nmov (%rdx),%esi\ncmp %esi,%ecx\ncmovl %esi,%ecx\nadd $0x4,%rdx\ncmp %rdx,%rdi\njne 1528 \nmov (%r8),%rdx\nmov %ecx,0x8(%r9)\nadd $0x10,%r9\nadd $0x18,%r8\nmov %rdx,-0x10(%r9)\ncmp %r10,%r9\njne 1508 \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmovsxd r10, esi\npush r12\nmov r12, rdi\npush rbp\nmov rbp, rsi\npush rbx\nmov rbx, r10\nshl rbx, 4\nmov rdi, rbx; size\ncall _malloc\nmov r11, rax\ntest ebp, ebp\njle short loc_15A0\nmov rdi, r12\nmov r8, rax\nlea r10, [rbx+rax]\nnop dword ptr [rax+00000000h]\nloc_1538:\nmov rcx, [rdi+8]\nmov esi, [rdi+10h]\nmov eax, [rcx]\ncmp esi, 1\njle short loc_1588\nsub esi, 2\nlea rdx, [rcx+4]\nlea rsi, [rcx+rsi*4+8]\nmov r9, rsi\nsub r9, rdx\nand r9d, 4\njz short loc_1570\nmov edx, [rcx+4]\ncmp eax, edx\ncmovl eax, edx\nlea rdx, [rcx+8]\ncmp rdx, rsi\njz short loc_1588\nnop\nloc_1570:\nmov ecx, [rdx]\ncmp eax, ecx\ncmovl eax, ecx\nmov ecx, [rdx+4]\ncmp eax, ecx\ncmovl eax, ecx\nadd rdx, 8\ncmp rdx, rsi\njnz short loc_1570\nloc_1588:\nmov rdx, [rdi]\nmov [r8+8], eax\nadd r8, 10h\nadd rdi, 18h\nmov [r8-10h], rdx\ncmp r8, r10\njnz short loc_1538\nloc_15A0:\npop rbx\nmov rax, r11\npop rbp\npop r12\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 *a1, int a2)\n{\n char *v2; // rax\n char *v3; // r11\n char *v4; // r8\n char *v5; // r10\n int *v6; // rcx\n int v7; // esi\n int v8; // eax\n int *v9; // rdx\n __int64 v10; // rsi\n __int64 v11; // rdx\n\n v2 = (char *)malloc(16LL * a2);\n v3 = v2;\n if ( a2 > 0 )\n {\n v4 = v2;\n v5 = &v2[16 * a2];\n do\n {\n v6 = (int *)a1[1];\n v7 = *((_DWORD *)a1 + 4);\n v8 = *v6;\n if ( v7 > 1 )\n {\n v9 = v6 + 1;\n v10 = (__int64)&v6[v7 - 2 + 2];\n if ( (((_BYTE)v10 - ((_BYTE)v6 + 4)) & 4) == 0 )\n goto LABEL_17;\n if ( v8 < v6[1] )\n v8 = v6[1];\n v9 = v6 + 2;\n if ( v6 + 2 != (int *)v10 )\n {\nLABEL_17:\n do\n {\n if ( v8 < *v9 )\n v8 = *v9;\n if ( v8 < v9[1] )\n v8 = v9[1];\n v9 += 2;\n }\n while ( v9 != (int *)v10 );\n }\n }\n v11 = *a1;\n *((_DWORD *)v4 + 2) = v8;\n v4 += 16;\n a1 += 3;\n *((_QWORD *)v4 - 2) = v11;\n }\n while ( v4 != v5 );\n }\n return v3;\n}", + "ida_strip_asm": "sub_1500:\nendbr64\nmovsxd r10, esi\npush r12\nmov r12, rdi\npush rbp\nmov rbp, rsi\npush rbx\nmov rbx, r10\nshl rbx, 4\nmov rdi, rbx; size\ncall _malloc\nmov r11, rax\ntest ebp, ebp\njle short loc_15A0\nmov rdi, r12\nmov r8, rax\nlea r10, [rbx+rax]\nnop dword ptr [rax+00000000h]\nloc_1538:\nmov rcx, [rdi+8]\nmov esi, [rdi+10h]\nmov eax, [rcx]\ncmp esi, 1\njle short loc_1588\nsub esi, 2\nlea rdx, [rcx+4]\nlea rsi, [rcx+rsi*4+8]\nmov r9, rsi\nsub r9, rdx\nand r9d, 4\njz short loc_1570\nmov edx, [rcx+4]\ncmp eax, edx\ncmovl eax, edx\nlea rdx, [rcx+8]\ncmp rdx, rsi\njz short loc_1588\nnop\nloc_1570:\nmov ecx, [rdx]\ncmp eax, ecx\ncmovl eax, ecx\nmov ecx, [rdx+4]\ncmp eax, ecx\ncmovl eax, ecx\nadd rdx, 8\ncmp rdx, rsi\njnz short loc_1570\nloc_1588:\nmov rdx, [rdi]\nmov [r8+8], eax\nadd r8, 10h\nadd rdi, 18h\nmov [r8-10h], rdx\ncmp r8, r10\njnz short loc_1538\nloc_15A0:\npop rbx\nmov rax, r11\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1500(__int64 *a1, int a2)\n{\n char *v2; // rax\n char *v3; // r11\n char *v4; // r8\n char *v5; // r10\n int *v6; // rcx\n int v7; // esi\n int v8; // eax\n int *v9; // rdx\n __int64 v10; // rsi\n __int64 v11; // rdx\n\n v2 = (char *)malloc(16LL * a2);\n v3 = v2;\n if ( a2 > 0 )\n {\n v4 = v2;\n v5 = &v2[16 * a2];\n do\n {\n v6 = (int *)a1[1];\n v7 = *((_DWORD *)a1 + 4);\n v8 = *v6;\n if ( v7 > 1 )\n {\n v9 = v6 + 1;\n v10 = (__int64)&v6[v7 - 2 + 2];\n if ( (((_BYTE)v10 - ((_BYTE)v6 + 4)) & 4) == 0 )\n goto LABEL_17;\n if ( v8 < v6[1] )\n v8 = v6[1];\n v9 = v6 + 2;\n if ( v6 + 2 != (int *)v10 )\n {\nLABEL_17:\n do\n {\n if ( v8 < *v9 )\n v8 = *v9;\n if ( v8 < v9[1] )\n v8 = v9[1];\n v9 += 2;\n }\n while ( v9 != (int *)v10 );\n }\n }\n v11 = *a1;\n *((_DWORD *)v4 + 2) = v8;\n v4 += 16;\n a1 += 3;\n *((_QWORD *)v4 - 2) = v11;\n }\n while ( v4 != v5 );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1500(long long *a1, int a2) {\n char *v2;\n char *v3;\n char *v4;\n char *v5;\n int *v6;\n int v7;\n int v8;\n int *v9;\n long long v10;\n long long v11;\n v2 = (char *)malloc(16LL * a2);\n v3 = v2;\n if (a2 > 0) {\n v4 = v2;\n v5 = &v2[16 * a2];\n do {\n v6 = (int *)a1[1];\n v7 = *((uint32_t *)a1 + 4);\n v8 = *v6;\n if (v7 > 1) {\n v9 = v6 + 1;\n v10 = (long long)&v6[v7 - 2 + 2];\n if ((((uint8_t)v10 - ((uint8_t)v6 + 4)) & 4) == 0) goto LABEL_17;\n if (v8 < v6[1]) v8 = v6[1];\n v9 = v6 + 2;\n if (v6 + 2 != (int *)v10) {\n LABEL_17:\n do {\n if (v8 < *v9) v8 = *v9;\n if (v8 < v9[1]) v8 = v9[1];\n v9 += 2;\n } while (v9 != (int *)v10);\n }\n }\n v11 = *a1;\n *((uint32_t *)v4 + 2) = v8;\n v4 += 16;\n a1 += 3;\n *((uint64_t *)v4 - 2) = v11;\n } while (v4 != v5);\n }\n return v3;\n}", + "ida_pseudo_norm": "char *func0(long long *a1, int a2) {\n char *v2;\n char *v3;\n char *v4;\n char *v5;\n int *v6;\n int v7;\n int v8;\n int *v9;\n long long v10;\n long long v11;\n v2 = (char *)malloc(16LL * a2);\n v3 = v2;\n if (a2 > 0) {\n v4 = v2;\n v5 = &v2[16 * a2];\n do {\n v6 = (int *)a1[1];\n v7 = *((uint32_t *)a1 + 4);\n v8 = *v6;\n if (v7 > 1) {\n v9 = v6 + 1;\n v10 = (long long)&v6[v7 - 2 + 2];\n if ((((uint8_t)v10 - ((uint8_t)v6 + 4)) & 4) == 0) goto LABEL_17;\n if (v8 < v6[1]) v8 = v6[1];\n v9 = v6 + 2;\n if (v6 + 2 != (int *)v10) {\n LABEL_17:\n do {\n if (v8 < *v9) v8 = *v9;\n if (v8 < v9[1]) v8 = v9[1];\n v9 += 2;\n } while (v9 != (int *)v10);\n }\n }\n v11 = *a1;\n *((uint32_t *)v4 + 2) = v8;\n v4 += 16;\n a1 += 3;\n *((uint64_t *)v4 - 2) = v11;\n } while (v4 != v5);\n }\n return v3;\n}" + }, + { + "index": 613, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char *key;\n\n int *values;\n\n int length;\n\n} KeyValue;\n\n\n\ntypedef struct {\n\n KeyValue *items;\n\n int length;\n\n} KeyValueList;\n\n\n\ntypedef struct {\n\n char *key;\n\n int max_value;\n\n} Result;\n\n\n\n", + "func": "Result* func0(KeyValueList test_list) {\n Result* res = (Result*)malloc(test_list.length * sizeof(Result));\n for (int i = 0; i < test_list.length; i++) {\n int max = test_list.items[i].values[0];\n for (int j = 1; j < test_list.items[i].length; j++) {\n if (test_list.items[i].values[j] > max) {\n max = test_list.items[i].values[j];\n }\n }\n res[i].key = test_list.items[i].key;\n res[i].max_value = max;\n }\n return res;\n}", + "test": "int main() {\n\n int a1[] = {3, 4, 5}, a2[] = {1, 4, 2}, a3[] = {9, 3};\n\n KeyValue items1[] = {{\"key1\", a1, 3}, {\"key2\", a2, 3}, {\"key3\", a3, 2}};\n\n KeyValueList kv1 = {items1, 3};\n\n\n\n int a4[] = {4, 5, 6}, a5[] = {2, 5, 3}, a6[] = {10, 4};\n\n KeyValue items2[] = {{\"key1\", a4, 3}, {\"key2\", a5, 3}, {\"key3\", a6, 2}};\n\n KeyValueList kv2 = {items2, 3};\n\n\n\n int a7[] = {5, 6, 7}, a8[] = {3, 6, 4}, a9[] = {11, 5};\n\n KeyValue items3[] = {{\"key1\", a7, 3}, {\"key2\", a8, 3}, {\"key3\", a9, 2}};\n\n KeyValueList kv3 = {items3, 3};\n\n\n\n Result *result1 = func0(kv1);\n\n Result *result2 = func0(kv2);\n\n Result *result3 = func0(kv3);\n\n\n\n assert(result1[0].max_value == 5 && result1[1].max_value == 4 && result1[2].max_value == 9);\n\n assert(result2[0].max_value == 6 && result2[1].max_value == 5 && result2[2].max_value == 10);\n\n assert(result3[0].max_value == 7 && result3[1].max_value == 6 && result3[2].max_value == 11);\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rdi,%rbp\nmovslq %esi,%rdi\npush %rbx\nshl $0x4,%rdi\nmov %rsi,%rbx\nsub $0x8,%rsp\ncallq 10b0 \ntest %ebx,%ebx\njle 164a \nlea -0x1(%rbx),%r11d\nmov %rbp,%rdi\nmov %rax,%r8\nadd $0x1,%r11\nshl $0x4,%r11\nadd %rax,%r11\nnopl 0x0(%rax)\nmov 0x8(%rdi),%rsi\nmov 0x10(%rdi),%r9d\nmov (%rsi),%edx\ncmp $0x1,%r9d\njle 162e \nlea -0x2(%r9),%ecx\nlea -0x1(%r9),%r10d\ncmp $0x2,%ecx\njbe 1651 \nmov %r10d,%ecx\nmovd %edx,%xmm3\nmov %rsi,%rdx\nshr $0x2,%ecx\npshufd $0x0,%xmm3,%xmm2\nshl $0x4,%rcx\nadd %rsi,%rcx\nxchg %ax,%ax\nmovdqu 0x4(%rdx),%xmm0\nadd $0x10,%rdx\nmovdqa %xmm0,%xmm1\npcmpgtd %xmm2,%xmm1\npand %xmm1,%xmm0\npandn %xmm2,%xmm1\nmovdqa %xmm1,%xmm2\npor %xmm0,%xmm2\ncmp %rcx,%rdx\njne 1580 \nmovdqa %xmm2,%xmm0\nmov %r10d,%ebx\npsrldq $0x8,%xmm0\nand $0xfffffffc,%ebx\nmovdqa %xmm0,%xmm1\nlea 0x1(%rbx),%ecx\npcmpgtd %xmm2,%xmm1\npand %xmm1,%xmm0\npandn %xmm2,%xmm1\npor %xmm1,%xmm0\nmovdqa %xmm0,%xmm2\npsrldq $0x4,%xmm2\nmovdqa %xmm2,%xmm1\npcmpgtd %xmm0,%xmm1\npand %xmm1,%xmm2\npandn %xmm0,%xmm1\npor %xmm2,%xmm1\nmovd %xmm1,%edx\ncmp %r10d,%ebx\nje 162e \nmovslq %ecx,%r10\nlea 0x0(,%r10,4),%rbx\nmov (%rsi,%r10,4),%r10d\ncmp %r10d,%edx\ncmovl %r10d,%edx\nlea 0x1(%rcx),%r10d\ncmp %r9d,%r10d\njge 162e \nmov 0x4(%rsi,%rbx,1),%r10d\ncmp %r10d,%edx\ncmovl %r10d,%edx\nadd $0x2,%ecx\ncmp %ecx,%r9d\njle 162e \nmov 0x8(%rsi,%rbx,1),%ecx\ncmp %ecx,%edx\ncmovl %ecx,%edx\nmov (%rdi),%rcx\nmov %edx,0x8(%r8)\nadd $0x10,%r8\nadd $0x18,%rdi\nmov %rcx,-0x10(%r8)\ncmp %r11,%r8\njne 1540 \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nmov $0x1,%ecx\njmp 15f2 \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r12\nmovsxd r10, esi\nmov r12, rdi\npush rbp\nshl r10, 4\npush rbx\nmov rdi, r10; size\nmov rbx, rsi\nmov rbp, r10\ncall _malloc\nmov r11, rax\ntest ebx, ebx\njle loc_1640\nmov rsi, r12\nmov r8, rax\nlea r10, [rbp+rax+0]\nnop word ptr [rax+rax+00000000h]\nloc_1540:\nmov rdi, [rsi+8]\nmov r9d, [rsi+10h]\nmov eax, [rdi]\ncmp r9d, 1\njle loc_1624\nlea edx, [r9-2]\nlea ecx, [r9-1]\ncmp edx, 2\njbe loc_1648\nmov edx, ecx\nmovd xmm3, eax\nmov rax, rdi\nshr edx, 2\npshufd xmm2, xmm3, 0\nshl rdx, 4\nadd rdx, rdi\nnop dword ptr [rax]\nloc_1580:\nmovdqu xmm0, xmmword ptr [rax+4]\nadd rax, 10h\nmovdqa xmm1, xmm0\npcmpgtd xmm1, xmm2\npand xmm0, xmm1\npandn xmm1, xmm2\nmovdqa xmm2, xmm1\npor xmm2, xmm0\ncmp rax, rdx\njnz short loc_1580\nmovdqa xmm1, xmm2\npsrldq xmm1, 8\nmovdqa xmm0, xmm1\npcmpgtd xmm0, xmm2\npand xmm1, xmm0\npandn xmm0, xmm2\npor xmm0, xmm1\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\nmovdqa xmm1, xmm2\npcmpgtd xmm1, xmm0\npand xmm2, xmm1\npandn xmm1, xmm0\npor xmm1, xmm2\nmovd eax, xmm1\ntest cl, 3\njz short loc_1624\nand ecx, 0FFFFFFFCh\nadd ecx, 1\nloc_15EF:\nmovsxd rdx, ecx\nlea rbx, ds:0[rdx*4]\nmov edx, [rdi+rdx*4]\ncmp eax, edx\ncmovl eax, edx\nlea edx, [rcx+1]\ncmp edx, r9d\njge short loc_1624\nmov edx, [rdi+rbx+4]\ncmp eax, edx\ncmovl eax, edx\nadd ecx, 2\ncmp r9d, ecx\njle short loc_1624\nmov edx, [rdi+rbx+8]\ncmp eax, edx\ncmovl eax, edx\nloc_1624:\nmov rdx, [rsi]\nmov [r8+8], eax\nadd r8, 10h\nadd rsi, 18h\nmov [r8-10h], rdx\ncmp r8, r10\njnz loc_1540\nloc_1640:\npop rbx\nmov rax, r11\npop rbp\npop r12\nretn\nloc_1648:\nmov ecx, 1\njmp short loc_15EF", + "ida_pseudo": "char *__fastcall func0(__int64 *a1, int a2)\n{\n size_t v2; // rbp\n char *v3; // rax\n char *v4; // r11\n char *v6; // r8\n char *v7; // r10\n signed int *v8; // rdi\n int v9; // r9d\n signed int v10; // eax\n unsigned int v11; // ecx\n __m128i v12; // xmm3\n __int64 v13; // rax\n __m128i v14; // xmm2\n __m128i v15; // xmm0\n __m128i v16; // xmm1\n __m128i v17; // xmm1\n __m128i v18; // xmm0\n __m128i v19; // xmm0\n __m128i v20; // xmm2\n __m128i v21; // xmm1\n signed int v22; // ecx\n __int64 v23; // rbx\n __int64 v24; // rdx\n\n v2 = 16LL * a2;\n v3 = (char *)malloc(v2);\n v4 = v3;\n if ( a2 > 0 )\n {\n v6 = v3;\n v7 = &v3[v2];\n do\n {\n v8 = (signed int *)a1[1];\n v9 = *((_DWORD *)a1 + 4);\n v10 = *v8;\n if ( v9 > 1 )\n {\n v11 = v9 - 1;\n if ( (unsigned int)(v9 - 2) <= 2 )\n {\n v22 = 1;\n goto LABEL_9;\n }\n v12 = _mm_cvtsi32_si128(v10);\n v13 = a1[1];\n v14 = _mm_shuffle_epi32(v12, 0);\n do\n {\n v15 = _mm_loadu_si128((const __m128i *)(v13 + 4));\n v13 += 16LL;\n v16 = _mm_cmpgt_epi32(v15, v14);\n v14 = _mm_or_si128(_mm_andnot_si128(v16, v14), _mm_and_si128(v15, v16));\n }\n while ( (signed int *)v13 != &v8[4 * (v11 >> 2)] );\n v17 = _mm_srli_si128(v14, 8);\n v18 = _mm_cmpgt_epi32(v17, v14);\n v19 = _mm_or_si128(_mm_andnot_si128(v18, v14), _mm_and_si128(v17, v18));\n v20 = _mm_srli_si128(v19, 4);\n v21 = _mm_cmpgt_epi32(v20, v19);\n v10 = _mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v21, v19), _mm_and_si128(v20, v21)));\n if ( (v11 & 3) != 0 )\n {\n v22 = (v11 & 0xFFFFFFFC) + 1;\nLABEL_9:\n v23 = v22;\n if ( v10 < v8[v23] )\n v10 = v8[v22];\n if ( v22 + 1 < v9 )\n {\n if ( v10 < v8[v23 + 1] )\n v10 = v8[v23 + 1];\n if ( v9 > v22 + 2 && v10 < v8[v23 + 2] )\n v10 = v8[v23 + 2];\n }\n }\n }\n v24 = *a1;\n *((_DWORD *)v6 + 2) = v10;\n v6 += 16;\n a1 += 3;\n *((_QWORD *)v6 - 2) = v24;\n }\n while ( v6 != v7 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_1500:\nendbr64\npush r12\nmovsxd r10, esi\nmov r12, rdi\npush rbp\nshl r10, 4\npush rbx\nmov rdi, r10; size\nmov rbx, rsi\nmov rbp, r10\ncall _malloc\nmov r11, rax\ntest ebx, ebx\njle loc_1640\nmov rsi, r12\nmov r8, rax\nlea r10, [rbp+rax+0]\nnop word ptr [rax+rax+00000000h]\nloc_1540:\nmov rdi, [rsi+8]\nmov r9d, [rsi+10h]\nmov eax, [rdi]\ncmp r9d, 1\njle loc_1624\nlea edx, [r9-2]\nlea ecx, [r9-1]\ncmp edx, 2\njbe loc_1648\nmov edx, ecx\nmovd xmm3, eax\nmov rax, rdi\nshr edx, 2\npshufd xmm2, xmm3, 0\nshl rdx, 4\nadd rdx, rdi\nnop dword ptr [rax]\nloc_1580:\nmovdqu xmm0, xmmword ptr [rax+4]\nadd rax, 10h\nmovdqa xmm1, xmm0\npcmpgtd xmm1, xmm2\npand xmm0, xmm1\npandn xmm1, xmm2\nmovdqa xmm2, xmm1\npor xmm2, xmm0\ncmp rax, rdx\njnz short loc_1580\nmovdqa xmm1, xmm2\npsrldq xmm1, 8\nmovdqa xmm0, xmm1\npcmpgtd xmm0, xmm2\npand xmm1, xmm0\npandn xmm0, xmm2\npor xmm0, xmm1\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\nmovdqa xmm1, xmm2\npcmpgtd xmm1, xmm0\npand xmm2, xmm1\npandn xmm1, xmm0\npor xmm1, xmm2\nmovd eax, xmm1\ntest cl, 3\njz short loc_1624\nand ecx, 0FFFFFFFCh\nadd ecx, 1\nloc_15EF:\nmovsxd rdx, ecx\nlea rbx, ds:0[rdx*4]\nmov edx, [rdi+rdx*4]\ncmp eax, edx\ncmovl eax, edx\nlea edx, [rcx+1]\ncmp edx, r9d\njge short loc_1624\nmov edx, [rdi+rbx+4]\ncmp eax, edx\ncmovl eax, edx\nadd ecx, 2\ncmp r9d, ecx\njle short loc_1624\nmov edx, [rdi+rbx+8]\ncmp eax, edx\ncmovl eax, edx\nloc_1624:\nmov rdx, [rsi]\nmov [r8+8], eax\nadd r8, 10h\nadd rsi, 18h\nmov [r8-10h], rdx\ncmp r8, r10\njnz loc_1540\nloc_1640:\npop rbx\nmov rax, r11\npop rbp\npop r12\nretn\nloc_1648:\nmov ecx, 1\njmp short loc_15EF", + "ida_strip_pseudo": "char *__fastcall sub_1500(__int64 *a1, int a2)\n{\n size_t v2; // rbp\n char *v3; // rax\n char *v4; // r11\n char *v6; // r8\n char *v7; // r10\n signed int *v8; // rdi\n int v9; // r9d\n signed int v10; // eax\n unsigned int v11; // ecx\n __m128i v12; // xmm3\n __int64 v13; // rax\n __m128i v14; // xmm2\n __m128i v15; // xmm0\n __m128i v16; // xmm1\n __m128i v17; // xmm1\n __m128i v18; // xmm0\n __m128i v19; // xmm0\n __m128i v20; // xmm2\n __m128i v21; // xmm1\n signed int v22; // ecx\n __int64 v23; // rbx\n __int64 v24; // rdx\n\n v2 = 16LL * a2;\n v3 = (char *)malloc(v2);\n v4 = v3;\n if ( a2 > 0 )\n {\n v6 = v3;\n v7 = &v3[v2];\n do\n {\n v8 = (signed int *)a1[1];\n v9 = *((_DWORD *)a1 + 4);\n v10 = *v8;\n if ( v9 > 1 )\n {\n v11 = v9 - 1;\n if ( (unsigned int)(v9 - 2) <= 2 )\n {\n v22 = 1;\n goto LABEL_9;\n }\n v12 = _mm_cvtsi32_si128(v10);\n v13 = a1[1];\n v14 = _mm_shuffle_epi32(v12, 0);\n do\n {\n v15 = _mm_loadu_si128((const __m128i *)(v13 + 4));\n v13 += 16LL;\n v16 = _mm_cmpgt_epi32(v15, v14);\n v14 = _mm_or_si128(_mm_andnot_si128(v16, v14), _mm_and_si128(v15, v16));\n }\n while ( (signed int *)v13 != &v8[4 * (v11 >> 2)] );\n v17 = _mm_srli_si128(v14, 8);\n v18 = _mm_cmpgt_epi32(v17, v14);\n v19 = _mm_or_si128(_mm_andnot_si128(v18, v14), _mm_and_si128(v17, v18));\n v20 = _mm_srli_si128(v19, 4);\n v21 = _mm_cmpgt_epi32(v20, v19);\n v10 = _mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v21, v19), _mm_and_si128(v20, v21)));\n if ( (v11 & 3) != 0 )\n {\n v22 = (v11 & 0xFFFFFFFC) + 1;\nLABEL_9:\n v23 = v22;\n if ( v10 < v8[v23] )\n v10 = v8[v22];\n if ( v22 + 1 < v9 )\n {\n if ( v10 < v8[v23 + 1] )\n v10 = v8[v23 + 1];\n if ( v9 > v22 + 2 && v10 < v8[v23 + 2] )\n v10 = v8[v23 + 2];\n }\n }\n }\n v24 = *a1;\n *((_DWORD *)v6 + 2) = v10;\n v6 += 16;\n a1 += 3;\n *((_QWORD *)v6 - 2) = v24;\n }\n while ( v6 != v7 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1500(long long *a1, int a2) {\n unsigned int v2;\n char *v3;\n char *v4;\n char *v6;\n char *v7;\n signed int *v8;\n int v9;\n signed int v10;\n unsigned int v11;\n __m128i v12;\n long long v13;\n __m128i v14;\n __m128i v15;\n __m128i v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n __m128i v20;\n __m128i v21;\n signed int v22;\n long long v23;\n long long v24;\n v2 = 16LL * a2;\n v3 = (char *)malloc(v2);\n v4 = v3;\n if (a2 > 0) {\n v6 = v3;\n v7 = &v3[v2];\n do {\n v8 = (signed int *)a1[1];\n v9 = *((uint32_t *)a1 + 4);\n v10 = *v8;\n if (v9 > 1) {\n v11 = v9 - 1;\n if ((unsigned int)(v9 - 2) <= 2) {\n v22 = 1;\n goto LABEL_9;\n }\n v12 = _mm_cvtsi32_si128(v10);\n v13 = a1[1];\n v14 = _mm_shuffle_epi32(v12, 0);\n do {\n v15 = _mm_loadu_si128((const __m128i *)(v13 + 4));\n v13 += 16LL;\n v16 = _mm_cmpgt_epi32(v15, v14);\n v14 =\n _mm_or_si128(_mm_andnot_si128(v16, v14), _mm_and_si128(v15, v16));\n } while ((signed int *)v13 != &v8[4 * (v11 >> 2)]);\n v17 = _mm_srli_si128(v14, 8);\n v18 = _mm_cmpgt_epi32(v17, v14);\n v19 = _mm_or_si128(_mm_andnot_si128(v18, v14), _mm_and_si128(v17, v18));\n v20 = _mm_srli_si128(v19, 4);\n v21 = _mm_cmpgt_epi32(v20, v19);\n v10 = _mm_cvtsi128_si32(\n _mm_or_si128(_mm_andnot_si128(v21, v19), _mm_and_si128(v20, v21)));\n if ((v11 & 3) != 0) {\n v22 = (v11 & 4294967292) + 1;\n LABEL_9:\n v23 = v22;\n if (v10 < v8[v23]) v10 = v8[v22];\n if (v22 + 1 < v9) {\n if (v10 < v8[v23 + 1]) v10 = v8[v23 + 1];\n if (v9 > v22 + 2 && v10 < v8[v23 + 2]) v10 = v8[v23 + 2];\n }\n }\n }\n v24 = *a1;\n *((uint32_t *)v6 + 2) = v10;\n v6 += 16;\n a1 += 3;\n *((uint64_t *)v6 - 2) = v24;\n } while (v6 != v7);\n }\n return v4;\n}", + "ida_pseudo_norm": "char *func0(long long *a1, int a2) {\n unsigned int v2;\n char *v3;\n char *v4;\n char *v6;\n char *v7;\n signed int *v8;\n int v9;\n signed int v10;\n unsigned int v11;\n __m128i v12;\n long long v13;\n __m128i v14;\n __m128i v15;\n __m128i v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n __m128i v20;\n __m128i v21;\n signed int v22;\n long long v23;\n long long v24;\n v2 = 16LL * a2;\n v3 = (char *)malloc(v2);\n v4 = v3;\n if (a2 > 0) {\n v6 = v3;\n v7 = &v3[v2];\n do {\n v8 = (signed int *)a1[1];\n v9 = *((uint32_t *)a1 + 4);\n v10 = *v8;\n if (v9 > 1) {\n v11 = v9 - 1;\n if ((unsigned int)(v9 - 2) <= 2) {\n v22 = 1;\n goto LABEL_9;\n }\n v12 = _mm_cvtsi32_si128(v10);\n v13 = a1[1];\n v14 = _mm_shuffle_epi32(v12, 0);\n do {\n v15 = _mm_loadu_si128((const __m128i *)(v13 + 4));\n v13 += 16LL;\n v16 = _mm_cmpgt_epi32(v15, v14);\n v14 =\n _mm_or_si128(_mm_andnot_si128(v16, v14), _mm_and_si128(v15, v16));\n } while ((signed int *)v13 != &v8[4 * (v11 >> 2)]);\n v17 = _mm_srli_si128(v14, 8);\n v18 = _mm_cmpgt_epi32(v17, v14);\n v19 = _mm_or_si128(_mm_andnot_si128(v18, v14), _mm_and_si128(v17, v18));\n v20 = _mm_srli_si128(v19, 4);\n v21 = _mm_cmpgt_epi32(v20, v19);\n v10 = _mm_cvtsi128_si32(\n _mm_or_si128(_mm_andnot_si128(v21, v19), _mm_and_si128(v20, v21)));\n if ((v11 & 3) != 0) {\n v22 = (v11 & 4294967292) + 1;\n LABEL_9:\n v23 = v22;\n if (v10 < v8[v23]) v10 = v8[v22];\n if (v22 + 1 < v9) {\n if (v10 < v8[v23 + 1]) v10 = v8[v23 + 1];\n if (v9 > v22 + 2 && v10 < v8[v23 + 2]) v10 = v8[v23 + 2];\n }\n }\n }\n v24 = *a1;\n *((uint32_t *)v6 + 2) = v10;\n v6 += 16;\n a1 += 3;\n *((uint64_t *)v6 - 2) = v24;\n } while (v6 != v7);\n }\n return v4;\n}" + }, + { + "index": 614, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int test_list[][10], int list_of_sizes[], int list_size) {\n int res = 0;\n for (int i = 0; i < list_size; i++) {\n for (int j = 0; j < list_of_sizes[i]; j++) {\n res += test_list[i][j];\n }\n }\n return res;\n}", + "test": "int main() {\n\n int list1[][10] = {{1, 3}, {5, 6, 7}, {2, 6}};\n\n int list1_sizes[] = {2, 3, 2};\n\n int list2[][10] = {{2, 4}, {6, 7, 8}, {3, 7}};\n\n int list2_sizes[] = {2, 3, 2};\n\n int list3[][10] = {{3, 5}, {7, 8, 9}, {4, 8}};\n\n int list3_sizes[] = {2, 3, 2};\n\n \n\n assert(func0(list1, list1_sizes, 3) == 30);\n\n assert(func0(list2, list2_sizes, 3) == 37);\n\n assert(func0(list3, list3_sizes, 3) == 44);\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %edx,-0x24(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 1201 \nmovl $0x0,-0x4(%rbp)\njmp 11e2 \nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0x4(%rbp),%eax\ncltq\nmov (%rdx,%rax,4),%eax\nadd %eax,-0xc(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x4(%rbp)\njl 11b5 \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x24(%rbp),%eax\njl 11ac \nmov -0xc(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_1201\nloc_11AC:\nmov [rbp+var_4], 0\njmp short loc_11E2\nloc_11B5:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\ncdqe\nmov eax, [rdx+rax*4]\nadd [rbp+var_C], eax\nadd [rbp+var_4], 1\nloc_11E2:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_4], eax\njl short loc_11B5\nadd [rbp+var_8], 1\nloc_1201:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_24]\njl short loc_11AC\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n unsigned int v4; // [rsp+18h] [rbp-Ch]\n int i; // [rsp+1Ch] [rbp-8h]\n int j; // [rsp+20h] [rbp-4h]\n\n v4 = 0;\n for ( i = 0; i < a3; ++i )\n {\n for ( j = 0; j < *(_DWORD *)(4LL * i + a2); ++j )\n v4 += *(_DWORD *)(a1 + 40LL * i + 4LL * j);\n }\n return v4;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_1201\nloc_11AC:\nmov [rbp+var_4], 0\njmp short loc_11E2\nloc_11B5:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\ncdqe\nmov eax, [rdx+rax*4]\nadd [rbp+var_C], eax\nadd [rbp+var_4], 1\nloc_11E2:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_4], eax\njl short loc_11B5\nadd [rbp+var_8], 1\nloc_1201:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_24]\njl short loc_11AC\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, __int64 a2, int a3)\n{\n unsigned int v4; // [rsp+18h] [rbp-Ch]\n int i; // [rsp+1Ch] [rbp-8h]\n int j; // [rsp+20h] [rbp-4h]\n\n v4 = 0;\n for ( i = 0; i < a3; ++i )\n {\n for ( j = 0; j < *(_DWORD *)(4LL * i + a2); ++j )\n v4 += *(_DWORD *)(a1 + 40LL * i + 4LL * j);\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, long long a2, int a3) {\n unsigned int v4;\n int i;\n int j;\n v4 = 0;\n for (i = 0; i < a3; ++i) {\n for (j = 0; j < *(uint32_t *)(4LL * i + a2); ++j)\n v4 += *(uint32_t *)(a1 + 40LL * i + 4LL * j);\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3) {\n unsigned int v4;\n int i;\n int j;\n v4 = 0;\n for (i = 0; i < a3; ++i) {\n for (j = 0; j < *(uint32_t *)(4LL * i + a2); ++j)\n v4 += *(uint32_t *)(a1 + 40LL * i + 4LL * j);\n }\n return v4;\n}" + }, + { + "index": 614, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int test_list[][10], int list_of_sizes[], int list_size) {\n int res = 0;\n for (int i = 0; i < list_size; i++) {\n for (int j = 0; j < list_of_sizes[i]; j++) {\n res += test_list[i][j];\n }\n }\n return res;\n}", + "test": "int main() {\n\n int list1[][10] = {{1, 3}, {5, 6, 7}, {2, 6}};\n\n int list1_sizes[] = {2, 3, 2};\n\n int list2[][10] = {{2, 4}, {6, 7, 8}, {3, 7}};\n\n int list2_sizes[] = {2, 3, 2};\n\n int list3[][10] = {{3, 5}, {7, 8, 9}, {4, 8}};\n\n int list3_sizes[] = {2, 3, 2};\n\n \n\n assert(func0(list1, list1_sizes, 3) == 30);\n\n assert(func0(list2, list2_sizes, 3) == 37);\n\n assert(func0(list3, list3_sizes, 3) == 44);\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edx,%edx\njle 11cf \nmov %rsi,%r8\nlea -0x1(%rdx),%eax\nlea 0x4(%rsi,%rax,4),%rsi\nmov $0x0,%edx\njmp 11c6 \nlea -0x1(%rax),%eax\nlea 0x4(%rdi,%rax,4),%rcx\nmov %rdi,%rax\nadd (%rax),%edx\nadd $0x4,%rax\ncmp %rcx,%rax\njne 11ae \nadd $0x4,%r8\nadd $0x28,%rdi\ncmp %rsi,%r8\nje 11d4 \nmov (%r8),%eax\ntest %eax,%eax\njg 11a3 \njmp 11b9 \nmov $0x0,%edx\nmov %edx,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest edx, edx\njle short loc_11CC\nmov r8, rsi\nmovsxd rdx, edx\nlea rsi, [rsi+rdx*4]\nmov edx, 0\njmp short loc_11C3\nloc_11A2:\ncdqe\nlea rcx, [rdi+rax*4]\nmov rax, rdi\nloc_11AB:\nadd edx, [rax]\nadd rax, 4\ncmp rax, rcx\njnz short loc_11AB\nloc_11B6:\nadd r8, 4\nadd rdi, 28h ; '('\ncmp r8, rsi\njz short loc_11D1\nloc_11C3:\nmov eax, [r8]\ntest eax, eax\njg short loc_11A2\njmp short loc_11B6\nloc_11CC:\nmov edx, 0\nloc_11D1:\nmov eax, edx\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int *a2, int a3)\n{\n int *v3; // r8\n int *v4; // rsi\n unsigned int v5; // edx\n _DWORD *v6; // rax\n\n if ( a3 <= 0 )\n {\n return 0;\n }\n else\n {\n v3 = a2;\n v4 = &a2[a3];\n v5 = 0;\n do\n {\n if ( *v3 > 0 )\n {\n v6 = a1;\n do\n v5 += *v6++;\n while ( v6 != &a1[*v3] );\n }\n ++v3;\n a1 += 10;\n }\n while ( v3 != v4 );\n }\n return v5;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\ntest edx, edx\njle short loc_11CC\nmov r8, rsi\nmovsxd rdx, edx\nlea rsi, [rsi+rdx*4]\nmov edx, 0\njmp short loc_11C3\nloc_11A2:\ncdqe\nlea rcx, [rdi+rax*4]\nmov rax, rdi\nloc_11AB:\nadd edx, [rax]\nadd rax, 4\ncmp rax, rcx\njnz short loc_11AB\nloc_11B6:\nadd r8, 4\nadd rdi, 28h ; '('\ncmp r8, rsi\njz short loc_11D1\nloc_11C3:\nmov eax, [r8]\ntest eax, eax\njg short loc_11A2\njmp short loc_11B6\nloc_11CC:\nmov edx, 0\nloc_11D1:\nmov eax, edx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(_DWORD *a1, int *a2, int a3)\n{\n int *v3; // r8\n int *v4; // rsi\n unsigned int v5; // edx\n _DWORD *v6; // rax\n\n if ( a3 <= 0 )\n {\n return 0;\n }\n else\n {\n v3 = a2;\n v4 = &a2[a3];\n v5 = 0;\n do\n {\n if ( *v3 > 0 )\n {\n v6 = a1;\n do\n v5 += *v6++;\n while ( v6 != &a1[*v3] );\n }\n ++v3;\n a1 += 10;\n }\n while ( v3 != v4 );\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(uint32_t *a1, int *a2, int a3) {\n int *v3;\n int *v4;\n unsigned int v5;\n uint32_t *v6;\n if (a3 <= 0) {\n return 0;\n } else {\n v3 = a2;\n v4 = &a2[a3];\n v5 = 0;\n do {\n if (*v3 > 0) {\n v6 = a1;\n do\n v5 += *v6++;\n while (v6 != &a1[*v3]);\n }\n ++v3;\n a1 += 10;\n } while (v3 != v4);\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int *a2, int a3) {\n int *v3;\n int *v4;\n unsigned int v5;\n uint32_t *v6;\n if (a3 <= 0) {\n return 0;\n } else {\n v3 = a2;\n v4 = &a2[a3];\n v5 = 0;\n do {\n if (*v3 > 0) {\n v6 = a1;\n do\n v5 += *v6++;\n while (v6 != &a1[*v3]);\n }\n ++v3;\n a1 += 10;\n } while (v3 != v4);\n }\n return v5;\n}" + }, + { + "index": 614, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int test_list[][10], int list_of_sizes[], int list_size) {\n int res = 0;\n for (int i = 0; i < list_size; i++) {\n for (int j = 0; j < list_of_sizes[i]; j++) {\n res += test_list[i][j];\n }\n }\n return res;\n}", + "test": "int main() {\n\n int list1[][10] = {{1, 3}, {5, 6, 7}, {2, 6}};\n\n int list1_sizes[] = {2, 3, 2};\n\n int list2[][10] = {{2, 4}, {6, 7, 8}, {3, 7}};\n\n int list2_sizes[] = {2, 3, 2};\n\n int list3[][10] = {{3, 5}, {7, 8, 9}, {4, 8}};\n\n int list3_sizes[] = {2, 3, 2};\n\n \n\n assert(func0(list1, list1_sizes, 3) == 30);\n\n assert(func0(list2, list2_sizes, 3) == 37);\n\n assert(func0(list3, list3_sizes, 3) == 44);\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %edx,%edx\njle 147d \nlea -0x1(%rdx),%eax\nxor %r8d,%r8d\nlea 0x4(%rsi,%rax,4),%rcx\nnopl 0x0(%rax,%rax,1)\nmov (%rsi),%eax\ntest %eax,%eax\njle 146c \nsub $0x1,%eax\nlea 0x4(%rdi,%rax,4),%rdx\nmov %rdi,%rax\nnopl 0x0(%rax)\nadd (%rax),%r8d\nadd $0x4,%rax\ncmp %rax,%rdx\njne 1460 \nadd $0x4,%rsi\nadd $0x28,%rdi\ncmp %rcx,%rsi\njne 1448 \nmov %r8d,%eax\nretq\nxor %r8d,%r8d\nmov %r8d,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\ntest edx, edx\njle short loc_13DB\nmovsxd rdx, edx\nlea r8, [rsi+rdx*4]\nxor edx, edx\nnop dword ptr [rax+00000000h]\nloc_13A8:\nmovsxd rax, dword ptr [rsi]\ntest eax, eax\njle short loc_13CB\nlea rcx, [rdi+rax*4]\nmov rax, rdi\nnop word ptr [rax+rax+00000000h]\nloc_13C0:\nadd edx, [rax]\nadd rax, 4\ncmp rax, rcx\njnz short loc_13C0\nloc_13CB:\nadd rsi, 4\nadd rdi, 28h ; '('\ncmp rsi, r8\njnz short loc_13A8\nmov eax, edx\nretn\nloc_13DB:\nxor edx, edx\nmov eax, edx\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int *a2, int a3)\n{\n int *v3; // r8\n unsigned int v4; // edx\n __int64 v5; // rax\n _DWORD *v6; // rcx\n _DWORD *v7; // rax\n\n if ( a3 <= 0 )\n return 0LL;\n v3 = &a2[a3];\n v4 = 0;\n do\n {\n v5 = *a2;\n if ( (int)v5 > 0 )\n {\n v6 = &a1[v5];\n v7 = a1;\n do\n v4 += *v7++;\n while ( v7 != v6 );\n }\n ++a2;\n a1 += 10;\n }\n while ( a2 != v3 );\n return v4;\n}", + "ida_strip_asm": "sub_1390:\nendbr64\ntest edx, edx\njle short loc_13DB\nmovsxd rdx, edx\nlea r8, [rsi+rdx*4]\nxor edx, edx\nnop dword ptr [rax+00000000h]\nloc_13A8:\nmovsxd rax, dword ptr [rsi]\ntest eax, eax\njle short loc_13CB\nlea rcx, [rdi+rax*4]\nmov rax, rdi\nnop word ptr [rax+rax+00000000h]\nloc_13C0:\nadd edx, [rax]\nadd rax, 4\ncmp rax, rcx\njnz short loc_13C0\nloc_13CB:\nadd rsi, 4\nadd rdi, 28h ; '('\ncmp rsi, r8\njnz short loc_13A8\nmov eax, edx\nretn\nloc_13DB:\nxor edx, edx\nmov eax, edx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1390(_DWORD *a1, int *a2, int a3)\n{\n int *v3; // r8\n unsigned int v4; // edx\n __int64 v5; // rax\n _DWORD *v6; // rcx\n _DWORD *v7; // rax\n\n if ( a3 <= 0 )\n return 0LL;\n v3 = &a2[a3];\n v4 = 0;\n do\n {\n v5 = *a2;\n if ( (int)v5 > 0 )\n {\n v6 = &a1[v5];\n v7 = a1;\n do\n v4 += *v7++;\n while ( v7 != v6 );\n }\n ++a2;\n a1 += 10;\n }\n while ( a2 != v3 );\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1390(uint32_t *a1, int *a2, int a3) {\n int *v3;\n unsigned int v4;\n long long v5;\n uint32_t *v6;\n uint32_t *v7;\n if (a3 <= 0) return 0LL;\n v3 = &a2[a3];\n v4 = 0;\n do {\n v5 = *a2;\n if ((int)v5 > 0) {\n v6 = &a1[v5];\n v7 = a1;\n do\n v4 += *v7++;\n while (v7 != v6);\n }\n ++a2;\n a1 += 10;\n } while (a2 != v3);\n return v4;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int *a2, int a3) {\n int *v3;\n unsigned int v4;\n long long v5;\n uint32_t *v6;\n uint32_t *v7;\n if (a3 <= 0) return 0LL;\n v3 = &a2[a3];\n v4 = 0;\n do {\n v5 = *a2;\n if ((int)v5 > 0) {\n v6 = &a1[v5];\n v7 = a1;\n do\n v4 += *v7++;\n while (v7 != v6);\n }\n ++a2;\n a1 += 10;\n } while (a2 != v3);\n return v4;\n}" + }, + { + "index": 615, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "double* func0(int num_tuples, int tuple_length, int nums[][tuple_length]) {\n double* result = malloc(tuple_length * sizeof(double));\n for (int i = 0; i < tuple_length; i++) {\n double sum = 0.0;\n for (int j = 0; j < num_tuples; j++) {\n sum += nums[j][i];\n }\n result[i] = sum / num_tuples;\n }\n return result;\n}", + "test": "int main() {\n\n // First assertion\n\n int nums1[][4] = {\n\n {10, 10, 10, 12},\n\n {30, 45, 56, 45},\n\n {81, 80, 39, 32},\n\n {1, 2, 3, 4}\n\n };\n\n double expected1[] = {30.5, 34.25, 27.0, 23.25};\n\n double* result1 = func0(4, 4, nums1);\n\n for(int i = 0; i < 4; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n free(result1);\n\n\n\n // Second assertion\n\n int nums2[][3] = {\n\n {1, 1, -5},\n\n {30, -15, 56},\n\n {81, -60, -39},\n\n {-10, 2, 3}\n\n };\n\n double expected2[] = {25.5, -18.0, 3.75};\n\n double* result2 = func0(4, 3, nums2);\n\n for(int i = 0; i < 3; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n free(result2);\n\n\n\n // Third assertion\n\n int nums3[][4] = {\n\n {100, 100, 100, 120},\n\n {300, 450, 560, 450},\n\n {810, 800, 390, 320},\n\n {10, 20, 30, 40}\n\n };\n\n double expected3[] = {305.0, 342.5, 270.0, 232.5};\n\n double* result3 = func0(4, 4, nums3);\n\n for(int i = 0; i < 4; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x38,%rsp\nmov %edi,-0x34(%rbp)\nmov %esi,-0x38(%rbp)\nmov %rdx,-0x40(%rbp)\nmov -0x38(%rbp),%ebx\nmovslq %ebx,%rax\nsub $0x1,%rax\nmov %rax,-0x20(%rbp)\nmovslq %ebx,%rax\nmov %rax,%r8\nmov $0x0,%r9d\nmov -0x38(%rbp),%eax\ncltq\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x18(%rbp)\nmovl $0x0,-0x2c(%rbp)\njmp 1276 \npxor %xmm0,%xmm0\nmovsd %xmm0,-0x28(%rbp)\nmovl $0x0,-0x30(%rbp)\njmp 1244 \nmov -0x30(%rbp),%eax\nmovslq %eax,%rdx\nmovslq %ebx,%rax\nimul %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x40(%rbp),%rax\nadd %rax,%rdx\nmov -0x2c(%rbp),%eax\ncltq\nmov (%rdx,%rax,4),%eax\ncvtsi2sd %eax,%xmm0\nmovsd -0x28(%rbp),%xmm1\naddsd %xmm1,%xmm0\nmovsd %xmm0,-0x28(%rbp)\naddl $0x1,-0x30(%rbp)\nmov -0x30(%rbp),%eax\ncmp -0x34(%rbp),%eax\njl 120a \ncvtsi2sdl -0x34(%rbp),%xmm1\nmov -0x2c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovsd -0x28(%rbp),%xmm0\ndivsd %xmm1,%xmm0\nmovsd %xmm0,(%rax)\naddl $0x1,-0x2c(%rbp)\nmov -0x2c(%rbp),%eax\ncmp -0x38(%rbp),%eax\njl 11f8 \nmov -0x18(%rbp),%rax\nadd $0x38,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+var_34], edi\nmov [rbp+var_38], esi\nmov [rbp+var_40], rdx\nmov ebx, [rbp+var_38]\nmovsxd rax, ebx\nsub rax, 1\nmov [rbp+var_20], rax\nmov eax, [rbp+var_38]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_30], 0\njmp loc_1275\nloc_11EF:\npxor xmm0, xmm0\nmovsd [rbp+var_28], xmm0\nmov [rbp+var_2C], 0\njmp short loc_123F\nloc_1201:\nmov eax, [rbp+var_2C]\nmovsxd rdx, eax\nmovsxd rax, ebx\nimul rax, rdx\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nadd rdx, rax\nmov eax, [rbp+var_30]\ncdqe\nmov eax, [rdx+rax*4]\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmovsd xmm1, [rbp+var_28]\naddsd xmm0, xmm1\nmovsd [rbp+var_28], xmm0\nadd [rbp+var_2C], 1\nloc_123F:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_34]\njl short loc_1201\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_34]\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovsd xmm0, [rbp+var_28]\ndivsd xmm0, xmm1\nmovsd qword ptr [rax], xmm0\nadd [rbp+var_30], 1\nloc_1275:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_38]\njl loc_11EF\nmov rax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "double *__fastcall func0(int a1, int a2, __int64 a3)\n{\n int i; // [rsp+10h] [rbp-30h]\n int j; // [rsp+14h] [rbp-2Ch]\n double v7; // [rsp+18h] [rbp-28h]\n double *v8; // [rsp+28h] [rbp-18h]\n\n v8 = (double *)malloc(8LL * a2);\n for ( i = 0; i < a2; ++i )\n {\n v7 = 0.0;\n for ( j = 0; j < a1; ++j )\n v7 = (double)*(int *)(a3 + 4 * j * (__int64)a2 + 4LL * i) + v7;\n v8[i] = v7 / (double)a1;\n }\n return v8;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+var_34], edi\nmov [rbp+var_38], esi\nmov [rbp+var_40], rdx\nmov ebx, [rbp+var_38]\nmovsxd rax, ebx\nsub rax, 1\nmov [rbp+var_20], rax\nmov eax, [rbp+var_38]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_30], 0\njmp loc_1275\nloc_11EF:\npxor xmm0, xmm0\nmovsd [rbp+var_28], xmm0\nmov [rbp+var_2C], 0\njmp short loc_123F\nloc_1201:\nmov eax, [rbp+var_2C]\nmovsxd rdx, eax\nmovsxd rax, ebx\nimul rax, rdx\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nadd rdx, rax\nmov eax, [rbp+var_30]\ncdqe\nmov eax, [rdx+rax*4]\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmovsd xmm1, [rbp+var_28]\naddsd xmm0, xmm1\nmovsd [rbp+var_28], xmm0\nadd [rbp+var_2C], 1\nloc_123F:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_34]\njl short loc_1201\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_34]\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovsd xmm0, [rbp+var_28]\ndivsd xmm0, xmm1\nmovsd qword ptr [rax], xmm0\nadd [rbp+var_30], 1\nloc_1275:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_38]\njl loc_11EF\nmov rax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "double *__fastcall sub_11A9(int a1, int a2, __int64 a3)\n{\n int i; // [rsp+10h] [rbp-30h]\n int j; // [rsp+14h] [rbp-2Ch]\n double v7; // [rsp+18h] [rbp-28h]\n double *v8; // [rsp+28h] [rbp-18h]\n\n v8 = (double *)malloc(8LL * a2);\n for ( i = 0; i < a2; ++i )\n {\n v7 = 0.0;\n for ( j = 0; j < a1; ++j )\n v7 = (double)*(int *)(a3 + 4 * j * (__int64)a2 + 4LL * i) + v7;\n v8[i] = v7 / (double)a1;\n }\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double *sub_11A9(int a1, int a2, long long a3) {\n int i;\n int j;\n double v7;\n double *v8;\n v8 = (double *)malloc(8LL * a2);\n for (i = 0; i < a2; ++i) {\n v7 = 0.0;\n for (j = 0; j < a1; ++j)\n v7 = (double)*(int *)(a3 + 4 * j * (long long)a2 + 4LL * i) + v7;\n v8[i] = v7 / (double)a1;\n }\n return v8;\n}", + "ida_pseudo_norm": "double *func0(int a1, int a2, long long a3) {\n int i;\n int j;\n double v7;\n double *v8;\n v8 = (double *)malloc(8LL * a2);\n for (i = 0; i < a2; ++i) {\n v7 = 0.0;\n for (j = 0; j < a1; ++j)\n v7 = (double)*(int *)(a3 + 4 * j * (long long)a2 + 4LL * i) + v7;\n v8[i] = v7 / (double)a1;\n }\n return v8;\n}" + }, + { + "index": 615, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "double* func0(int num_tuples, int tuple_length, int nums[][tuple_length]) {\n double* result = malloc(tuple_length * sizeof(double));\n for (int i = 0; i < tuple_length; i++) {\n double sum = 0.0;\n for (int j = 0; j < num_tuples; j++) {\n sum += nums[j][i];\n }\n result[i] = sum / num_tuples;\n }\n return result;\n}", + "test": "int main() {\n\n // First assertion\n\n int nums1[][4] = {\n\n {10, 10, 10, 12},\n\n {30, 45, 56, 45},\n\n {81, 80, 39, 32},\n\n {1, 2, 3, 4}\n\n };\n\n double expected1[] = {30.5, 34.25, 27.0, 23.25};\n\n double* result1 = func0(4, 4, nums1);\n\n for(int i = 0; i < 4; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n free(result1);\n\n\n\n // Second assertion\n\n int nums2[][3] = {\n\n {1, 1, -5},\n\n {30, -15, 56},\n\n {81, -60, -39},\n\n {-10, 2, 3}\n\n };\n\n double expected2[] = {25.5, -18.0, 3.75};\n\n double* result2 = func0(4, 3, nums2);\n\n for(int i = 0; i < 3; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n free(result2);\n\n\n\n // Third assertion\n\n int nums3[][4] = {\n\n {100, 100, 100, 120},\n\n {300, 450, 560, 450},\n\n {810, 800, 390, 320},\n\n {10, 20, 30, 40}\n\n };\n\n double expected3[] = {305.0, 342.5, 270.0, 232.5};\n\n double* result3 = func0(4, 4, nums3);\n\n for(int i = 0; i < 4; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %edi,%ebx\nmov %esi,%r13d\nmov %rdx,%r12\nmovslq %esi,%rbp\nlea 0x0(,%rbp,8),%rdi\ncallq 10b0 \ntest %r13d,%r13d\njle 1236 \nmov %rax,%rdi\nmov %r12,%r8\nlea -0x1(%r13),%edx\nlea 0x8(%rax,%rdx,8),%r9\nlea 0x0(,%rbp,4),%rsi\njmp 122c \nmov %r8,%rcx\npxor %xmm0,%xmm0\nmov $0x0,%edx\npxor %xmm1,%xmm1\ncvtsi2sdl (%rcx),%xmm1\naddsd %xmm1,%xmm0\nadd $0x1,%edx\nadd %rsi,%rcx\ncmp %edx,%ebx\njne 11f9 \npxor %xmm1,%xmm1\ncvtsi2sd %ebx,%xmm1\ndivsd %xmm1,%xmm0\nmovsd %xmm0,(%rdi)\nadd $0x8,%rdi\nadd $0x4,%r8\ncmp %r9,%rdi\nje 1236 \npxor %xmm0,%xmm0\ntest %ebx,%ebx\njg 11ed \njmp 120f \nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov ebx, edi\nmov r13d, esi\nmov r12, rdx\nmovsxd rbp, esi\nlea rdi, ds:0[rbp*8]; size\ncall _malloc\ntest r13d, r13d\njle short loc_122E\nmov r8, rax\nmov rdi, r12\nlea rsi, ds:0[rbp*4]\nlea r9, [r12+rsi]\njmp short loc_121C\nloc_11E8:\npxor xmm1, xmm1\ncvtsi2sd xmm1, dword ptr [rcx]\naddsd xmm0, xmm1\nadd edx, 1\nadd rcx, rsi\ncmp ebx, edx\njnz short loc_11E8\nloc_11FE:\npxor xmm1, xmm1\ncvtsi2sd xmm1, ebx\ndivsd xmm0, xmm1\nmovsd qword ptr [r8], xmm0\nadd r8, 8\nadd rdi, 4\ncmp rdi, r9\njz short loc_122E\nloc_121C:\nmov rcx, rdi\nmov edx, 0\npxor xmm0, xmm0\ntest ebx, ebx\njg short loc_11E8\njmp short loc_11FE\nloc_122E:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "double *__fastcall func0(int a1, int a2, int *a3)\n{\n double *result; // rax\n double *v6; // r8\n int *v7; // rdi\n double v8; // xmm0_8\n int v9; // edx\n int *v10; // rcx\n\n result = (double *)malloc(8LL * a2);\n if ( a2 > 0 )\n {\n v6 = result;\n v7 = a3;\n do\n {\n v10 = v7;\n v9 = 0;\n v8 = 0.0;\n if ( a1 > 0 )\n {\n do\n {\n v8 = v8 + (double)*v10;\n ++v9;\n v10 += a2;\n }\n while ( a1 != v9 );\n }\n *v6++ = v8 / (double)a1;\n ++v7;\n }\n while ( v7 != &a3[a2] );\n }\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov ebx, edi\nmov r13d, esi\nmov r12, rdx\nmovsxd rbp, esi\nlea rdi, ds:0[rbp*8]; size\ncall _malloc\ntest r13d, r13d\njle short loc_122E\nmov r8, rax\nmov rdi, r12\nlea rsi, ds:0[rbp*4]\nlea r9, [r12+rsi]\njmp short loc_121C\nloc_11E8:\npxor xmm1, xmm1\ncvtsi2sd xmm1, dword ptr [rcx]\naddsd xmm0, xmm1\nadd edx, 1\nadd rcx, rsi\ncmp ebx, edx\njnz short loc_11E8\nloc_11FE:\npxor xmm1, xmm1\ncvtsi2sd xmm1, ebx\ndivsd xmm0, xmm1\nmovsd qword ptr [r8], xmm0\nadd r8, 8\nadd rdi, 4\ncmp rdi, r9\njz short loc_122E\nloc_121C:\nmov rcx, rdi\nmov edx, 0\npxor xmm0, xmm0\ntest ebx, ebx\njg short loc_11E8\njmp short loc_11FE\nloc_122E:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "double *__fastcall sub_11A9(int a1, int a2, int *a3)\n{\n double *result; // rax\n double *v6; // r8\n int *v7; // rdi\n double v8; // xmm0_8\n int v9; // edx\n int *v10; // rcx\n\n result = (double *)malloc(8LL * a2);\n if ( a2 > 0 )\n {\n v6 = result;\n v7 = a3;\n do\n {\n v10 = v7;\n v9 = 0;\n v8 = 0.0;\n if ( a1 > 0 )\n {\n do\n {\n v8 = v8 + (double)*v10;\n ++v9;\n v10 += a2;\n }\n while ( a1 != v9 );\n }\n *v6++ = v8 / (double)a1;\n ++v7;\n }\n while ( v7 != &a3[a2] );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double *sub_11A9(int a1, int a2, int *a3) {\n double *result;\n double *v6;\n int *v7;\n double v8;\n int v9;\n int *v10;\n result = (double *)malloc(8LL * a2);\n if (a2 > 0) {\n v6 = result;\n v7 = a3;\n do {\n v10 = v7;\n v9 = 0;\n v8 = 0.0;\n if (a1 > 0) {\n do {\n v8 = v8 + (double)*v10;\n ++v9;\n v10 += a2;\n } while (a1 != v9);\n }\n *v6++ = v8 / (double)a1;\n ++v7;\n } while (v7 != &a3[a2]);\n }\n return result;\n}", + "ida_pseudo_norm": "double *func0(int a1, int a2, int *a3) {\n double *result;\n double *v6;\n int *v7;\n double v8;\n int v9;\n int *v10;\n result = (double *)malloc(8LL * a2);\n if (a2 > 0) {\n v6 = result;\n v7 = a3;\n do {\n v10 = v7;\n v9 = 0;\n v8 = 0.0;\n if (a1 > 0) {\n do {\n v8 = v8 + (double)*v10;\n ++v9;\n v10 += a2;\n } while (a1 != v9);\n }\n *v6++ = v8 / (double)a1;\n ++v7;\n } while (v7 != &a3[a2]);\n }\n return result;\n}" + }, + { + "index": 615, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "double* func0(int num_tuples, int tuple_length, int nums[][tuple_length]) {\n double* result = malloc(tuple_length * sizeof(double));\n for (int i = 0; i < tuple_length; i++) {\n double sum = 0.0;\n for (int j = 0; j < num_tuples; j++) {\n sum += nums[j][i];\n }\n result[i] = sum / num_tuples;\n }\n return result;\n}", + "test": "int main() {\n\n // First assertion\n\n int nums1[][4] = {\n\n {10, 10, 10, 12},\n\n {30, 45, 56, 45},\n\n {81, 80, 39, 32},\n\n {1, 2, 3, 4}\n\n };\n\n double expected1[] = {30.5, 34.25, 27.0, 23.25};\n\n double* result1 = func0(4, 4, nums1);\n\n for(int i = 0; i < 4; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n free(result1);\n\n\n\n // Second assertion\n\n int nums2[][3] = {\n\n {1, 1, -5},\n\n {30, -15, 56},\n\n {81, -60, -39},\n\n {-10, 2, 3}\n\n };\n\n double expected2[] = {25.5, -18.0, 3.75};\n\n double* result2 = func0(4, 3, nums2);\n\n for(int i = 0; i < 3; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n free(result2);\n\n\n\n // Third assertion\n\n int nums3[][4] = {\n\n {100, 100, 100, 120},\n\n {300, 450, 560, 450},\n\n {810, 800, 390, 320},\n\n {10, 20, 30, 40}\n\n };\n\n double expected3[] = {305.0, 342.5, 270.0, 232.5};\n\n double* result3 = func0(4, 4, nums3);\n\n for(int i = 0; i < 4; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\nmov %rdx,%r12\npush %rbp\nmovslq %esi,%rbp\npush %rbx\nmov %edi,%ebx\nlea 0x0(,%rbp,8),%rdi\nsub $0x8,%rsp\ncallq 10b0 \ntest %ebp,%ebp\njle 158c \npxor %xmm3,%xmm3\nlea -0x1(%rbp),%edx\nmov %rax,%rdi\nmov %r12,%r8\ncvtsi2sd %ebx,%xmm3\nlea 0x8(%rax,%rdx,8),%r9\npxor %xmm2,%xmm2\nlea 0x0(,%rbp,4),%rsi\nnopl 0x0(%rax)\nmov %r8,%rcx\nmovapd %xmm2,%xmm0\nxor %edx,%edx\ntest %ebx,%ebx\njle 1576 \nnopl (%rax)\npxor %xmm1,%xmm1\nadd $0x1,%edx\ncvtsi2sdl (%rcx),%xmm1\nadd %rsi,%rcx\naddsd %xmm1,%xmm0\ncmp %edx,%ebx\njne 1560 \ndivsd %xmm3,%xmm0\nadd $0x8,%rdi\nadd $0x4,%r8\nmovsd %xmm0,-0x8(%rdi)\ncmp %r9,%rdi\njne 1550 \nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\nmov r12, rdx\npush rbp\nmovsxd rbp, esi\npush rbx\nmov ebx, edi\nlea rdi, ds:0[rbp*8]; size\nsub rsp, 8\ncall _malloc\ntest ebp, ebp\njle short loc_1495\npxor xmm2, xmm2\nlea rsi, ds:0[rbp*4]\nmov r8, rax\nmov rdi, r12\ncvtsi2sd xmm2, ebx\nlea r9, [r12+rsi]\nnop dword ptr [rax+00000000h]\nloc_1458:\nmov rcx, rdi\nxor edx, edx\npxor xmm0, xmm0\ntest ebx, ebx\njle short loc_147E\nnop dword ptr [rax]\nloc_1468:\npxor xmm1, xmm1\nadd edx, 1\ncvtsi2sd xmm1, dword ptr [rcx]\nadd rcx, rsi\naddsd xmm0, xmm1\ncmp ebx, edx\njnz short loc_1468\nloc_147E:\ndivsd xmm0, xmm2\nadd rdi, 4\nadd r8, 8\nmovsd qword ptr [r8-8], xmm0\ncmp rdi, r9\njnz short loc_1458\nloc_1495:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "double *__fastcall func0(int a1, int a2, int *a3)\n{\n double *result; // rax\n double *v6; // r8\n int *v7; // rdi\n int *v8; // rcx\n int v9; // edx\n double v10; // xmm0_8\n double v11; // xmm1_8\n\n result = (double *)malloc(8LL * a2);\n if ( a2 > 0 )\n {\n v6 = result;\n v7 = a3;\n do\n {\n v8 = v7;\n v9 = 0;\n v10 = 0.0;\n if ( a1 > 0 )\n {\n do\n {\n ++v9;\n v11 = (double)*v8;\n v8 += a2;\n v10 = v10 + v11;\n }\n while ( a1 != v9 );\n }\n ++v7;\n *v6++ = v10 / (double)a1;\n }\n while ( v7 != &a3[a2] );\n }\n return result;\n}", + "ida_strip_asm": "sub_1410:\nendbr64\npush r13\npush r12\nmov r12, rdx\npush rbp\nmovsxd rbp, esi\npush rbx\nmov ebx, edi\nlea rdi, ds:0[rbp*8]; size\nsub rsp, 8\ncall _malloc\ntest ebp, ebp\njle short loc_1495\npxor xmm2, xmm2\nlea rsi, ds:0[rbp*4]\nmov r8, rax\nmov rdi, r12\ncvtsi2sd xmm2, ebx\nlea r9, [r12+rsi]\nnop dword ptr [rax+00000000h]\nloc_1458:\nmov rcx, rdi\nxor edx, edx\npxor xmm0, xmm0\ntest ebx, ebx\njle short loc_147E\nnop dword ptr [rax]\nloc_1468:\npxor xmm1, xmm1\nadd edx, 1\ncvtsi2sd xmm1, dword ptr [rcx]\nadd rcx, rsi\naddsd xmm0, xmm1\ncmp ebx, edx\njnz short loc_1468\nloc_147E:\ndivsd xmm0, xmm2\nadd rdi, 4\nadd r8, 8\nmovsd qword ptr [r8-8], xmm0\ncmp rdi, r9\njnz short loc_1458\nloc_1495:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "double *__fastcall sub_1410(int a1, int a2, int *a3)\n{\n double *result; // rax\n double *v6; // r8\n int *v7; // rdi\n int *v8; // rcx\n int v9; // edx\n double v10; // xmm0_8\n double v11; // xmm1_8\n\n result = (double *)malloc(8LL * a2);\n if ( a2 > 0 )\n {\n v6 = result;\n v7 = a3;\n do\n {\n v8 = v7;\n v9 = 0;\n v10 = 0.0;\n if ( a1 > 0 )\n {\n do\n {\n ++v9;\n v11 = (double)*v8;\n v8 += a2;\n v10 = v10 + v11;\n }\n while ( a1 != v9 );\n }\n ++v7;\n *v6++ = v10 / (double)a1;\n }\n while ( v7 != &a3[a2] );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double *sub_1410(int a1, int a2, int *a3) {\n double *result;\n double *v6;\n int *v7;\n int *v8;\n int v9;\n double v10;\n double v11;\n result = (double *)malloc(8LL * a2);\n if (a2 > 0) {\n v6 = result;\n v7 = a3;\n do {\n v8 = v7;\n v9 = 0;\n v10 = 0.0;\n if (a1 > 0) {\n do {\n ++v9;\n v11 = (double)*v8;\n v8 += a2;\n v10 = v10 + v11;\n } while (a1 != v9);\n }\n ++v7;\n *v6++ = v10 / (double)a1;\n } while (v7 != &a3[a2]);\n }\n return result;\n}", + "ida_pseudo_norm": "double *func0(int a1, int a2, int *a3) {\n double *result;\n double *v6;\n int *v7;\n int *v8;\n int v9;\n double v10;\n double v11;\n result = (double *)malloc(8LL * a2);\n if (a2 > 0) {\n v6 = result;\n v7 = a3;\n do {\n v8 = v7;\n v9 = 0;\n v10 = 0.0;\n if (a1 > 0) {\n do {\n ++v9;\n v11 = (double)*v8;\n v8 += a2;\n v10 = v10 + v11;\n } while (a1 != v9);\n }\n ++v7;\n *v6++ = v10 / (double)a1;\n } while (v7 != &a3[a2]);\n }\n return result;\n}" + }, + { + "index": 615, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "double* func0(int num_tuples, int tuple_length, int nums[][tuple_length]) {\n double* result = malloc(tuple_length * sizeof(double));\n for (int i = 0; i < tuple_length; i++) {\n double sum = 0.0;\n for (int j = 0; j < num_tuples; j++) {\n sum += nums[j][i];\n }\n result[i] = sum / num_tuples;\n }\n return result;\n}", + "test": "int main() {\n\n // First assertion\n\n int nums1[][4] = {\n\n {10, 10, 10, 12},\n\n {30, 45, 56, 45},\n\n {81, 80, 39, 32},\n\n {1, 2, 3, 4}\n\n };\n\n double expected1[] = {30.5, 34.25, 27.0, 23.25};\n\n double* result1 = func0(4, 4, nums1);\n\n for(int i = 0; i < 4; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n free(result1);\n\n\n\n // Second assertion\n\n int nums2[][3] = {\n\n {1, 1, -5},\n\n {30, -15, 56},\n\n {81, -60, -39},\n\n {-10, 2, 3}\n\n };\n\n double expected2[] = {25.5, -18.0, 3.75};\n\n double* result2 = func0(4, 3, nums2);\n\n for(int i = 0; i < 3; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n free(result2);\n\n\n\n // Third assertion\n\n int nums3[][4] = {\n\n {100, 100, 100, 120},\n\n {300, 450, 560, 450},\n\n {810, 800, 390, 320},\n\n {10, 20, 30, 40}\n\n };\n\n double expected3[] = {305.0, 342.5, 270.0, 232.5};\n\n double* result3 = func0(4, 4, nums3);\n\n for(int i = 0; i < 4; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\nmov %rdx,%r12\npush %rbp\nmovslq %esi,%rbp\npush %rbx\nmov %edi,%ebx\nlea 0x0(,%rbp,8),%rdi\nsub $0x8,%rsp\ncallq 10b0 \ntest %ebp,%ebp\njle 14fc \npxor %xmm3,%xmm3\nlea -0x1(%rbp),%edx\nmov %rax,%rdi\nmov %r12,%r8\ncvtsi2sd %ebx,%xmm3\nlea 0x8(%rax,%rdx,8),%r9\npxor %xmm2,%xmm2\nlea 0x0(,%rbp,4),%rsi\nnopl 0x0(%rax)\nmov %r8,%rcx\nmovapd %xmm2,%xmm0\nxor %edx,%edx\ntest %ebx,%ebx\njle 14e6 \nnopl (%rax)\npxor %xmm1,%xmm1\nadd $0x1,%edx\ncvtsi2sdl (%rcx),%xmm1\nadd %rsi,%rcx\naddsd %xmm1,%xmm0\ncmp %edx,%ebx\njne 14d0 \ndivsd %xmm3,%xmm0\nadd $0x8,%rdi\nadd $0x4,%r8\nmovsd %xmm0,-0x8(%rdi)\ncmp %r9,%rdi\njne 14c0 \nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\nmov r12, rdx\npush rbp\nmovsxd rbp, esi\npush rbx\nmov ebx, edi\nlea rdi, ds:0[rbp*8]; size\nsub rsp, 8\ncall _malloc\ntest ebp, ebp\njle short loc_14B5\npxor xmm2, xmm2\nlea rsi, ds:0[rbp*4]\nmov r8, rax\nmov rdi, r12\ncvtsi2sd xmm2, ebx\nlea r9, [r12+rsi]\nnop dword ptr [rax+00000000h]\nloc_1478:\nmov rcx, rdi\nxor edx, edx\npxor xmm0, xmm0\ntest ebx, ebx\njle short loc_149E\nnop dword ptr [rax]\nloc_1488:\npxor xmm1, xmm1\nadd edx, 1\ncvtsi2sd xmm1, dword ptr [rcx]\nadd rcx, rsi\naddsd xmm0, xmm1\ncmp ebx, edx\njnz short loc_1488\nloc_149E:\ndivsd xmm0, xmm2\nadd rdi, 4\nadd r8, 8\nmovsd qword ptr [r8-8], xmm0\ncmp r9, rdi\njnz short loc_1478\nloc_14B5:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "double *__fastcall func0(int a1, int a2, int *a3)\n{\n double *result; // rax\n double *v6; // r8\n int *v7; // rdi\n int *v8; // rcx\n int v9; // edx\n double v10; // xmm0_8\n double v11; // xmm1_8\n\n result = (double *)malloc(8LL * a2);\n if ( a2 > 0 )\n {\n v6 = result;\n v7 = a3;\n do\n {\n v8 = v7;\n v9 = 0;\n v10 = 0.0;\n if ( a1 > 0 )\n {\n do\n {\n ++v9;\n v11 = (double)*v8;\n v8 += a2;\n v10 = v10 + v11;\n }\n while ( a1 != v9 );\n }\n ++v7;\n *v6++ = v10 / (double)a1;\n }\n while ( &a3[a2] != v7 );\n }\n return result;\n}", + "ida_strip_asm": "sub_1430:\nendbr64\npush r13\npush r12\nmov r12, rdx\npush rbp\nmovsxd rbp, esi\npush rbx\nmov ebx, edi\nlea rdi, ds:0[rbp*8]; size\nsub rsp, 8\ncall _malloc\ntest ebp, ebp\njle short loc_14B5\npxor xmm2, xmm2\nlea rsi, ds:0[rbp*4]\nmov r8, rax\nmov rdi, r12\ncvtsi2sd xmm2, ebx\nlea r9, [r12+rsi]\nnop dword ptr [rax+00000000h]\nloc_1478:\nmov rcx, rdi\nxor edx, edx\npxor xmm0, xmm0\ntest ebx, ebx\njle short loc_149E\nnop dword ptr [rax]\nloc_1488:\npxor xmm1, xmm1\nadd edx, 1\ncvtsi2sd xmm1, dword ptr [rcx]\nadd rcx, rsi\naddsd xmm0, xmm1\ncmp ebx, edx\njnz short loc_1488\nloc_149E:\ndivsd xmm0, xmm2\nadd rdi, 4\nadd r8, 8\nmovsd qword ptr [r8-8], xmm0\ncmp r9, rdi\njnz short loc_1478\nloc_14B5:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "double *__fastcall sub_1430(int a1, int a2, int *a3)\n{\n double *result; // rax\n double *v6; // r8\n int *v7; // rdi\n int *v8; // rcx\n int v9; // edx\n double v10; // xmm0_8\n double v11; // xmm1_8\n\n result = (double *)malloc(8LL * a2);\n if ( a2 > 0 )\n {\n v6 = result;\n v7 = a3;\n do\n {\n v8 = v7;\n v9 = 0;\n v10 = 0.0;\n if ( a1 > 0 )\n {\n do\n {\n ++v9;\n v11 = (double)*v8;\n v8 += a2;\n v10 = v10 + v11;\n }\n while ( a1 != v9 );\n }\n ++v7;\n *v6++ = v10 / (double)a1;\n }\n while ( &a3[a2] != v7 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double *sub_1430(int a1, int a2, int *a3) {\n double *result;\n double *v6;\n int *v7;\n int *v8;\n int v9;\n double v10;\n double v11;\n result = (double *)malloc(8LL * a2);\n if (a2 > 0) {\n v6 = result;\n v7 = a3;\n do {\n v8 = v7;\n v9 = 0;\n v10 = 0.0;\n if (a1 > 0) {\n do {\n ++v9;\n v11 = (double)*v8;\n v8 += a2;\n v10 = v10 + v11;\n } while (a1 != v9);\n }\n ++v7;\n *v6++ = v10 / (double)a1;\n } while (&a3[a2] != v7);\n }\n return result;\n}", + "ida_pseudo_norm": "double *func0(int a1, int a2, int *a3) {\n double *result;\n double *v6;\n int *v7;\n int *v8;\n int v9;\n double v10;\n double v11;\n result = (double *)malloc(8LL * a2);\n if (a2 > 0) {\n v6 = result;\n v7 = a3;\n do {\n v8 = v7;\n v9 = 0;\n v10 = 0.0;\n if (a1 > 0) {\n do {\n ++v9;\n v11 = (double)*v8;\n v8 += a2;\n v10 = v10 + v11;\n } while (a1 != v9);\n }\n ++v7;\n *v6++ = v10 / (double)a1;\n } while (&a3[a2] != v7);\n }\n return result;\n}" + }, + { + "index": 616, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int test_tup1[], int test_tup2[], int res[], int size) {\n for (int i = 0; i < size; i++) {\n res[i] = test_tup1[i] % test_tup2[i];\n }\n}", + "test": "int main() {\n\n int result[4];\n\n\n\n int a1[] = {10, 4, 5, 6};\n\n int b1[] = {5, 6, 7, 5};\n\n int expected1[] = {0, 4, 5, 1};\n\n func0(a1, b1, result, 4);\n\n for (int i = 0; i < 4; i++) {\n\n assert(result[i] == expected1[i]);\n\n }\n\n\n\n int a2[] = {11, 5, 6, 7};\n\n int b2[] = {6, 7, 8, 6};\n\n int expected2[] = {5, 5, 6, 1};\n\n func0(a2, b2, result, 4);\n\n for (int i = 0; i < 4; i++) {\n\n assert(result[i] == expected2[i]);\n\n }\n\n\n\n int a3[] = {12, 6, 7, 8};\n\n int b3[] = {7, 8, 9, 7};\n\n int expected3[] = {5, 6, 7, 1};\n\n func0(a3, b3, result, 4);\n\n for (int i = 0; i < 4; i++) {\n\n assert(result[i] == expected3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %ecx,-0x2c(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11d6 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov -0x4(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x20(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rdx),%esi\nmov -0x4(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x28(%rbp),%rdx\nadd %rdx,%rcx\ncltd\nidiv %esi\nmov %edx,%eax\nmov %eax,(%rcx)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 1189 \npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_28], rdx\nmov [rbp+var_2C], ecx\nmov [rbp+var_4], 0\njmp short loc_11D8\nloc_1189:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_20]\nadd rdx, rcx\nmov edi, [rdx]\nmov ecx, [rbp+var_4]\nmovsxd rcx, ecx\nlea rsi, ds:0[rcx*4]\nmov rcx, [rbp+var_28]\nadd rcx, rsi\ncdq\nidiv edi\nmov esi, edx\nmov eax, esi\nmov [rcx], eax\nadd [rbp+var_4], 1\nloc_11D8:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_2C]\njl short loc_1189\nnop\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+28h] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a4 )\n break;\n *(_DWORD *)(4LL * (int)i + a3) = *(_DWORD *)(4LL * (int)i + a1) % *(_DWORD *)(4LL * (int)i + a2);\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_28], rdx\nmov [rbp+var_2C], ecx\nmov [rbp+var_4], 0\njmp short loc_11D8\nloc_1189:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_20]\nadd rdx, rcx\nmov edi, [rdx]\nmov ecx, [rbp+var_4]\nmovsxd rcx, ecx\nlea rsi, ds:0[rcx*4]\nmov rcx, [rbp+var_28]\nadd rcx, rsi\ncdq\nidiv edi\nmov esi, edx\nmov eax, esi\nmov [rcx], eax\nadd [rbp+var_4], 1\nloc_11D8:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_2C]\njl short loc_1189\nnop\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+28h] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a4 )\n break;\n *(_DWORD *)(4LL * (int)i + a3) = *(_DWORD *)(4LL * (int)i + a1) % *(_DWORD *)(4LL * (int)i + a2);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, long long a3, int a4) {\n long long result;\n unsigned int i;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a4) break;\n *(uint32_t *)(4LL * (int)i + a3) =\n *(uint32_t *)(4LL * (int)i + a1) % *(uint32_t *)(4LL * (int)i + a2);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, long long a3, int a4) {\n long long result;\n unsigned int i;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a4) break;\n *(uint32_t *)(4LL * (int)i + a3) =\n *(uint32_t *)(4LL * (int)i + a1) % *(uint32_t *)(4LL * (int)i + a2);\n }\n return result;\n}" + }, + { + "index": 616, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int test_tup1[], int test_tup2[], int res[], int size) {\n for (int i = 0; i < size; i++) {\n res[i] = test_tup1[i] % test_tup2[i];\n }\n}", + "test": "int main() {\n\n int result[4];\n\n\n\n int a1[] = {10, 4, 5, 6};\n\n int b1[] = {5, 6, 7, 5};\n\n int expected1[] = {0, 4, 5, 1};\n\n func0(a1, b1, result, 4);\n\n for (int i = 0; i < 4; i++) {\n\n assert(result[i] == expected1[i]);\n\n }\n\n\n\n int a2[] = {11, 5, 6, 7};\n\n int b2[] = {6, 7, 8, 6};\n\n int expected2[] = {5, 5, 6, 1};\n\n func0(a2, b2, result, 4);\n\n for (int i = 0; i < 4; i++) {\n\n assert(result[i] == expected2[i]);\n\n }\n\n\n\n int a3[] = {12, 6, 7, 8};\n\n int b3[] = {7, 8, 9, 7};\n\n int expected3[] = {5, 6, 7, 1};\n\n func0(a3, b3, result, 4);\n\n for (int i = 0; i < 4; i++) {\n\n assert(result[i] == expected3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdx,%r8\ntest %ecx,%ecx\njle 1194 \nlea -0x1(%rcx),%r9d\nmov $0x0,%ecx\nmov (%rdi,%rcx,4),%eax\ncltd\nidivl (%rsi,%rcx,4)\nmov %edx,(%r8,%rcx,4)\nmov %rcx,%rax\nadd $0x1,%rcx\ncmp %r9,%rax\njne 117d \nretq\n", + "ida_asm": "func0:\nendbr64\nmov r8, rdi\nmov r9, rdx\ntest ecx, ecx\njle short locret_119C\nmovsxd rcx, ecx\nlea rdi, ds:0[rcx*4]\nmov ecx, 0\nloc_1187:\nmov eax, [r8+rcx]\ncdq\nidiv dword ptr [rsi+rcx]\nmov [r9+rcx], edx\nadd rcx, 4\ncmp rcx, rdi\njnz short loc_1187\nlocret_119C:\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 v5; // rdi\n __int64 v6; // rcx\n __int64 result; // rax\n\n if ( a4 > 0 )\n {\n v5 = 4LL * a4;\n v6 = 0LL;\n do\n {\n result = (unsigned int)(*(_DWORD *)(a1 + v6) / *(_DWORD *)(a2 + v6));\n *(_DWORD *)(a3 + v6) = *(_DWORD *)(a1 + v6) % *(_DWORD *)(a2 + v6);\n v6 += 4LL;\n }\n while ( v6 != v5 );\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov r8, rdi\nmov r9, rdx\ntest ecx, ecx\njle short locret_119C\nmovsxd rcx, ecx\nlea rdi, ds:0[rcx*4]\nmov ecx, 0\nloc_1187:\nmov eax, [r8+rcx]\ncdq\nidiv dword ptr [rsi+rcx]\nmov [r9+rcx], edx\nadd rcx, 4\ncmp rcx, rdi\njnz short loc_1187\nlocret_119C:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 v5; // rdi\n __int64 v6; // rcx\n __int64 result; // rax\n\n if ( a4 > 0 )\n {\n v5 = 4LL * a4;\n v6 = 0LL;\n do\n {\n result = (unsigned int)(*(_DWORD *)(a1 + v6) / *(_DWORD *)(a2 + v6));\n *(_DWORD *)(a3 + v6) = *(_DWORD *)(a1 + v6) % *(_DWORD *)(a2 + v6);\n v6 += 4LL;\n }\n while ( v6 != v5 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, long long a3, int a4) {\n long long v5;\n long long v6;\n long long result;\n if (a4 > 0) {\n v5 = 4LL * a4;\n v6 = 0LL;\n do {\n result = (unsigned int)(*(uint32_t *)(a1 + v6) / *(uint32_t *)(a2 + v6));\n *(uint32_t *)(a3 + v6) = *(uint32_t *)(a1 + v6) % *(uint32_t *)(a2 + v6);\n v6 += 4LL;\n } while (v6 != v5);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, long long a3, int a4) {\n long long v5;\n long long v6;\n long long result;\n if (a4 > 0) {\n v5 = 4LL * a4;\n v6 = 0LL;\n do {\n result = (unsigned int)(*(uint32_t *)(a1 + v6) / *(uint32_t *)(a2 + v6));\n *(uint32_t *)(a3 + v6) = *(uint32_t *)(a1 + v6) % *(uint32_t *)(a2 + v6);\n v6 += 4LL;\n } while (v6 != v5);\n }\n return result;\n}" + }, + { + "index": 617, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int a, int b, int d) {\n int temp = a;\n a = a < b ? a : b;\n b = temp > b ? temp : b;\n if (d >= b) {\n return (d + b - 1) / b;\n }\n if (d == 0) {\n return 0;\n }\n if (d == a) {\n return 1;\n }\n return 2;\n}", + "test": "int main() {\n\n assert(func0(3, 4, 11) == 3);\n\n assert(func0(3, 4, 0) == 0);\n\n assert(func0(11, 14, 11) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov %edx,-0x1c(%rbp)\nmov -0x14(%rbp),%eax\nmov %eax,-0x4(%rbp)\nmov -0x14(%rbp),%eax\ncmp %eax,-0x18(%rbp)\ncmovle -0x18(%rbp),%eax\nmov %eax,-0x14(%rbp)\nmov -0x4(%rbp),%eax\ncmp %eax,-0x18(%rbp)\ncmovge -0x18(%rbp),%eax\nmov %eax,-0x18(%rbp)\nmov -0x1c(%rbp),%eax\ncmp -0x18(%rbp),%eax\njl 1193 \nmov -0x1c(%rbp),%edx\nmov -0x18(%rbp),%eax\nadd %edx,%eax\nsub $0x1,%eax\ncltd\nidivl -0x18(%rbp)\njmp 11b4 \ncmpl $0x0,-0x1c(%rbp)\njne 11a0 \nmov $0x0,%eax\njmp 11b4 \nmov -0x1c(%rbp),%eax\ncmp -0x14(%rbp),%eax\njne 11af \nmov $0x1,%eax\njmp 11b4 \nmov $0x2,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov eax, [rbp+var_14]\nmov [rbp+var_4], eax\nmov edx, [rbp+var_14]\nmov eax, [rbp+var_18]\ncmp edx, eax\ncmovle eax, edx\nmov [rbp+var_14], eax\nmov edx, [rbp+var_18]\nmov eax, [rbp+var_4]\ncmp edx, eax\ncmovge eax, edx\nmov [rbp+var_18], eax\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_18]\njl short loc_1195\nmov edx, [rbp+var_1C]\nmov eax, [rbp+var_18]\nadd eax, edx\nsub eax, 1\ncdq\nidiv [rbp+var_18]\njmp short loc_11B6\nloc_1195:\ncmp [rbp+var_1C], 0\njnz short loc_11A2\nmov eax, 0\njmp short loc_11B6\nloc_11A2:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_14]\njnz short loc_11B1\nmov eax, 1\njmp short loc_11B6\nloc_11B1:\nmov eax, 2\nloc_11B6:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, int a3)\n{\n int v3; // eax\n int v4; // eax\n int v6; // [rsp+8h] [rbp-14h]\n\n v3 = a2;\n if ( a1 <= a2 )\n v3 = a1;\n v6 = v3;\n v4 = a1;\n if ( a2 >= a1 )\n v4 = a2;\n if ( a3 >= v4 )\n return (unsigned int)((a3 + v4 - 1) / v4);\n if ( !a3 )\n return 0LL;\n if ( a3 == v6 )\n return 1LL;\n return 2LL;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov eax, [rbp+var_14]\nmov [rbp+var_4], eax\nmov edx, [rbp+var_14]\nmov eax, [rbp+var_18]\ncmp edx, eax\ncmovle eax, edx\nmov [rbp+var_14], eax\nmov edx, [rbp+var_18]\nmov eax, [rbp+var_4]\ncmp edx, eax\ncmovge eax, edx\nmov [rbp+var_18], eax\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_18]\njl short loc_1195\nmov edx, [rbp+var_1C]\nmov eax, [rbp+var_18]\nadd eax, edx\nsub eax, 1\ncdq\nidiv [rbp+var_18]\njmp short loc_11B6\nloc_1195:\ncmp [rbp+var_1C], 0\njnz short loc_11A2\nmov eax, 0\njmp short loc_11B6\nloc_11A2:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_14]\njnz short loc_11B1\nmov eax, 1\njmp short loc_11B6\nloc_11B1:\nmov eax, 2\nloc_11B6:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2, int a3)\n{\n int v3; // eax\n int v4; // eax\n int v6; // [rsp+8h] [rbp-14h]\n\n v3 = a2;\n if ( a1 <= a2 )\n v3 = a1;\n v6 = v3;\n v4 = a1;\n if ( a2 >= a1 )\n v4 = a2;\n if ( a3 >= v4 )\n return (unsigned int)((a3 + v4 - 1) / v4);\n if ( !a3 )\n return 0LL;\n if ( a3 == v6 )\n return 1LL;\n return 2LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2, int a3) {\n int v3;\n int v4;\n int v6;\n v3 = a2;\n if (a1 <= a2) v3 = a1;\n v6 = v3;\n v4 = a1;\n if (a2 >= a1) v4 = a2;\n if (a3 >= v4) return (unsigned int)((a3 + v4 - 1) / v4);\n if (!a3) return 0LL;\n if (a3 == v6) return 1LL;\n return 2LL;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, int a3) {\n int v3;\n int v4;\n int v6;\n v3 = a2;\n if (a1 <= a2) v3 = a1;\n v6 = v3;\n v4 = a1;\n if (a2 >= a1) v4 = a2;\n if (a3 >= v4) return (unsigned int)((a3 + v4 - 1) / v4);\n if (!a3) return 0LL;\n if (a3 == v6) return 1LL;\n return 2LL;\n}" + }, + { + "index": 618, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "double* func0(int* nums1, int* nums2, int size) {\n double* result = malloc(sizeof(double) * size);\n for (int i = 0; i < size; i++) {\n result[i] = (double)nums1[i] / nums2[i];\n }\n return result;\n}", + "test": "int main() {\n\n int nums1a[] = {4, 5, 6}, nums2a[] = {1, 2, 3};\n\n double* result1 = func0(nums1a, nums2a, 3);\n\n assert(result1[0] == 4.0 && result1[1] == 2.5 && result1[2] == 2.0);\n\n free(result1);\n\n\n\n int nums1b[] = {3, 2}, nums2b[] = {1, 4};\n\n double* result2 = func0(nums1b, nums2b, 2);\n\n assert(result2[0] == 3.0 && result2[1] == 0.5);\n\n free(result2);\n\n\n\n int nums1c[] = {90, 120}, nums2c[] = {50, 70};\n\n double* result3 = func0(nums1c, nums2c, 2);\n\n assert(result3[0] == 1.8 && result3[1] == 1.7142857142857142);\n\n free(result3);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %edx,-0x24(%rbp)\nmov -0x24(%rbp),%eax\ncltq\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 1232 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncvtsi2sd %eax,%xmm0\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncvtsi2sd %eax,%xmm1\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\ndivsd %xmm1,%xmm0\nmovsd %xmm0,(%rax)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x24(%rbp),%eax\njl 11de \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov eax, [rbp+var_24]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp short loc_123A\nloc_11DE:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov eax, [rax]\npxor xmm1, xmm1\ncvtsi2sd xmm1, eax\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rdx\ndivsd xmm0, xmm1\nmovsd qword ptr [rax], xmm0\nadd [rbp+var_C], 1\nloc_123A:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_24]\njl short loc_11DE\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "double *__fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n int i; // [rsp+24h] [rbp-Ch]\n double *v6; // [rsp+28h] [rbp-8h]\n\n v6 = (double *)malloc(8LL * a3);\n for ( i = 0; i < a3; ++i )\n v6[i] = (double)*(int *)(4LL * i + a1) / (double)*(int *)(4LL * i + a2);\n return v6;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov eax, [rbp+var_24]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp short loc_123A\nloc_11DE:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov eax, [rax]\npxor xmm1, xmm1\ncvtsi2sd xmm1, eax\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rdx\ndivsd xmm0, xmm1\nmovsd qword ptr [rax], xmm0\nadd [rbp+var_C], 1\nloc_123A:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_24]\njl short loc_11DE\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "double *__fastcall sub_11A9(__int64 a1, __int64 a2, int a3)\n{\n int i; // [rsp+24h] [rbp-Ch]\n double *v6; // [rsp+28h] [rbp-8h]\n\n v6 = (double *)malloc(8LL * a3);\n for ( i = 0; i < a3; ++i )\n v6[i] = (double)*(int *)(4LL * i + a1) / (double)*(int *)(4LL * i + a2);\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double *sub_11A9(long long a1, long long a2, int a3) {\n int i;\n double *v6;\n v6 = (double *)malloc(8LL * a3);\n for (i = 0; i < a3; ++i)\n v6[i] = (double)*(int *)(4LL * i + a1) / (double)*(int *)(4LL * i + a2);\n return v6;\n}", + "ida_pseudo_norm": "double *func0(long long a1, long long a2, int a3) {\n int i;\n double *v6;\n v6 = (double *)malloc(8LL * a3);\n for (i = 0; i < a3; ++i)\n v6[i] = (double)*(int *)(4LL * i + a1) / (double)*(int *)(4LL * i + a2);\n return v6;\n}" + }, + { + "index": 618, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "double* func0(int* nums1, int* nums2, int size) {\n double* result = malloc(sizeof(double) * size);\n for (int i = 0; i < size; i++) {\n result[i] = (double)nums1[i] / nums2[i];\n }\n return result;\n}", + "test": "int main() {\n\n int nums1a[] = {4, 5, 6}, nums2a[] = {1, 2, 3};\n\n double* result1 = func0(nums1a, nums2a, 3);\n\n assert(result1[0] == 4.0 && result1[1] == 2.5 && result1[2] == 2.0);\n\n free(result1);\n\n\n\n int nums1b[] = {3, 2}, nums2b[] = {1, 4};\n\n double* result2 = func0(nums1b, nums2b, 2);\n\n assert(result2[0] == 3.0 && result2[1] == 0.5);\n\n free(result2);\n\n\n\n int nums1c[] = {90, 120}, nums2c[] = {50, 70};\n\n double* result3 = func0(nums1c, nums2c, 2);\n\n assert(result3[0] == 1.8 && result3[1] == 1.7142857142857142);\n\n free(result3);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nmov %rsi,%rbp\nmov %edx,%r12d\nmovslq %edx,%rdi\nshl $0x3,%rdi\ncallq 10b0 \ntest %r12d,%r12d\njle 11fd \nlea -0x1(%r12),%esi\nmov $0x0,%edx\npxor %xmm0,%xmm0\ncvtsi2sdl (%rbx,%rdx,4),%xmm0\npxor %xmm1,%xmm1\ncvtsi2sdl 0x0(%rbp,%rdx,4),%xmm1\ndivsd %xmm1,%xmm0\nmovsd %xmm0,(%rax,%rdx,8)\nmov %rdx,%rcx\nadd $0x1,%rdx\ncmp %rsi,%rcx\njne 11d5 \npop %rbx\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov rbp, rsi\nmov r13d, edx\nmovsxd r12, edx\nlea rdi, ds:0[r12*8]; size\ncall _malloc\ntest r13d, r13d\njle short loc_1207\nlea rcx, ds:0[r12*4]\nmov edx, 0\nloc_11E2:\npxor xmm0, xmm0\ncvtsi2sd xmm0, dword ptr [rbx+rdx]\npxor xmm1, xmm1\ncvtsi2sd xmm1, dword ptr [rbp+rdx+0]\ndivsd xmm0, xmm1\nmovsd qword ptr [rax+rdx*2], xmm0\nadd rdx, 4\ncmp rdx, rcx\njnz short loc_11E2\nloc_1207:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n __int64 v4; // r12\n char *result; // rax\n __int64 v6; // rdx\n\n v4 = a3;\n result = (char *)malloc(8LL * a3);\n if ( a3 > 0 )\n {\n v6 = 0LL;\n do\n {\n *(double *)&result[2 * v6] = (double)*(int *)(a1 + v6) / (double)*(int *)(a2 + v6);\n v6 += 4LL;\n }\n while ( v6 != 4 * v4 );\n }\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov rbp, rsi\nmov r13d, edx\nmovsxd r12, edx\nlea rdi, ds:0[r12*8]; size\ncall _malloc\ntest r13d, r13d\njle short loc_1207\nlea rcx, ds:0[r12*4]\nmov edx, 0\nloc_11E2:\npxor xmm0, xmm0\ncvtsi2sd xmm0, dword ptr [rbx+rdx]\npxor xmm1, xmm1\ncvtsi2sd xmm1, dword ptr [rbp+rdx+0]\ndivsd xmm0, xmm1\nmovsd qword ptr [rax+rdx*2], xmm0\nadd rdx, 4\ncmp rdx, rcx\njnz short loc_11E2\nloc_1207:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11A9(__int64 a1, __int64 a2, int a3)\n{\n __int64 v4; // r12\n char *result; // rax\n __int64 v6; // rdx\n\n v4 = a3;\n result = (char *)malloc(8LL * a3);\n if ( a3 > 0 )\n {\n v6 = 0LL;\n do\n {\n *(double *)&result[2 * v6] = (double)*(int *)(a1 + v6) / (double)*(int *)(a2 + v6);\n v6 += 4LL;\n }\n while ( v6 != 4 * v4 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11A9(long long a1, long long a2, int a3) {\n long long v4;\n char *result;\n long long v6;\n v4 = a3;\n result = (char *)malloc(8LL * a3);\n if (a3 > 0) {\n v6 = 0LL;\n do {\n *(double *)&result[2 * v6] =\n (double)*(int *)(a1 + v6) / (double)*(int *)(a2 + v6);\n v6 += 4LL;\n } while (v6 != 4 * v4);\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(long long a1, long long a2, int a3) {\n long long v4;\n char *result;\n long long v6;\n v4 = a3;\n result = (char *)malloc(8LL * a3);\n if (a3 > 0) {\n v6 = 0LL;\n do {\n *(double *)&result[2 * v6] =\n (double)*(int *)(a1 + v6) / (double)*(int *)(a2 + v6);\n v6 += 4LL;\n } while (v6 != 4 * v4);\n }\n return result;\n}" + }, + { + "index": 618, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "double* func0(int* nums1, int* nums2, int size) {\n double* result = malloc(sizeof(double) * size);\n for (int i = 0; i < size; i++) {\n result[i] = (double)nums1[i] / nums2[i];\n }\n return result;\n}", + "test": "int main() {\n\n int nums1a[] = {4, 5, 6}, nums2a[] = {1, 2, 3};\n\n double* result1 = func0(nums1a, nums2a, 3);\n\n assert(result1[0] == 4.0 && result1[1] == 2.5 && result1[2] == 2.0);\n\n free(result1);\n\n\n\n int nums1b[] = {3, 2}, nums2b[] = {1, 4};\n\n double* result2 = func0(nums1b, nums2b, 2);\n\n assert(result2[0] == 3.0 && result2[1] == 0.5);\n\n free(result2);\n\n\n\n int nums1c[] = {90, 120}, nums2c[] = {50, 70};\n\n double* result3 = func0(nums1c, nums2c, 2);\n\n assert(result3[0] == 1.8 && result3[1] == 1.7142857142857142);\n\n free(result3);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\nmov %rsi,%rbp\npush %rbx\nmov %rdi,%rbx\nmovslq %edx,%rdi\nmov %rdi,%r12\nshl $0x3,%rdi\ncallq 10b0 \ntest %r12d,%r12d\njle 13f8 \nlea -0x1(%r12),%esi\nxor %edx,%edx\nnopl 0x0(%rax)\npxor %xmm0,%xmm0\npxor %xmm1,%xmm1\nmov %rdx,%rcx\ncvtsi2sdl (%rbx,%rdx,4),%xmm0\ncvtsi2sdl 0x0(%rbp,%rdx,4),%xmm1\ndivsd %xmm1,%xmm0\nmovsd %xmm0,(%rax,%rdx,8)\nadd $0x1,%rdx\ncmp %rsi,%rcx\njne 13d0 \npop %rbx\npop %rbp\npop %r12\nretq\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\nmov r12, rsi\npush rbp\nmov rbp, rdi\npush rbx\nmovsxd rbx, edx\nlea rdi, ds:0[rbx*8]; size\nsub rsp, 8\ncall _malloc\ntest ebx, ebx\njle short loc_13EE\nlea rcx, ds:0[rbx*4]\nxor edx, edx\nnop word ptr [rax+rax+00h]\nloc_13C8:\npxor xmm0, xmm0\npxor xmm1, xmm1\ncvtsi2sd xmm0, dword ptr [rbp+rdx+0]\ncvtsi2sd xmm1, dword ptr [r12+rdx]\ndivsd xmm0, xmm1\nmovsd qword ptr [rax+rdx*2], xmm0\nadd rdx, 4\ncmp rdx, rcx\njnz short loc_13C8\nloc_13EE:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n __int64 v3; // rbx\n char *result; // rax\n __int64 v5; // rdx\n\n v3 = a3;\n result = (char *)malloc(8LL * a3);\n if ( (int)v3 > 0 )\n {\n v5 = 0LL;\n do\n {\n *(double *)&result[2 * v5] = (double)*(int *)(a1 + v5) / (double)*(int *)(a2 + v5);\n v5 += 4LL;\n }\n while ( v5 != 4 * v3 );\n }\n return result;\n}", + "ida_strip_asm": "sub_1390:\nendbr64\npush r13\npush r12\nmov r12, rsi\npush rbp\nmov rbp, rdi\npush rbx\nmovsxd rbx, edx\nlea rdi, ds:0[rbx*8]; size\nsub rsp, 8\ncall _malloc\ntest ebx, ebx\njle short loc_13EE\nlea rcx, ds:0[rbx*4]\nxor edx, edx\nnop word ptr [rax+rax+00h]\nloc_13C8:\npxor xmm0, xmm0\npxor xmm1, xmm1\ncvtsi2sd xmm0, dword ptr [rbp+rdx+0]\ncvtsi2sd xmm1, dword ptr [r12+rdx]\ndivsd xmm0, xmm1\nmovsd qword ptr [rax+rdx*2], xmm0\nadd rdx, 4\ncmp rdx, rcx\njnz short loc_13C8\nloc_13EE:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1390(__int64 a1, __int64 a2, int a3)\n{\n __int64 v3; // rbx\n char *result; // rax\n __int64 v5; // rdx\n\n v3 = a3;\n result = (char *)malloc(8LL * a3);\n if ( (int)v3 > 0 )\n {\n v5 = 0LL;\n do\n {\n *(double *)&result[2 * v5] = (double)*(int *)(a1 + v5) / (double)*(int *)(a2 + v5);\n v5 += 4LL;\n }\n while ( v5 != 4 * v3 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1390(long long a1, long long a2, int a3) {\n long long v3;\n char *result;\n long long v5;\n v3 = a3;\n result = (char *)malloc(8LL * a3);\n if ((int)v3 > 0) {\n v5 = 0LL;\n do {\n *(double *)&result[2 * v5] =\n (double)*(int *)(a1 + v5) / (double)*(int *)(a2 + v5);\n v5 += 4LL;\n } while (v5 != 4 * v3);\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(long long a1, long long a2, int a3) {\n long long v3;\n char *result;\n long long v5;\n v3 = a3;\n result = (char *)malloc(8LL * a3);\n if ((int)v3 > 0) {\n v5 = 0LL;\n do {\n *(double *)&result[2 * v5] =\n (double)*(int *)(a1 + v5) / (double)*(int *)(a2 + v5);\n v5 += 4LL;\n } while (v5 != 4 * v3);\n }\n return result;\n}" + }, + { + "index": 618, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "double* func0(int* nums1, int* nums2, int size) {\n double* result = malloc(sizeof(double) * size);\n for (int i = 0; i < size; i++) {\n result[i] = (double)nums1[i] / nums2[i];\n }\n return result;\n}", + "test": "int main() {\n\n int nums1a[] = {4, 5, 6}, nums2a[] = {1, 2, 3};\n\n double* result1 = func0(nums1a, nums2a, 3);\n\n assert(result1[0] == 4.0 && result1[1] == 2.5 && result1[2] == 2.0);\n\n free(result1);\n\n\n\n int nums1b[] = {3, 2}, nums2b[] = {1, 4};\n\n double* result2 = func0(nums1b, nums2b, 2);\n\n assert(result2[0] == 3.0 && result2[1] == 0.5);\n\n free(result2);\n\n\n\n int nums1c[] = {90, 120}, nums2c[] = {50, 70};\n\n double* result3 = func0(nums1c, nums2c, 2);\n\n assert(result3[0] == 1.8 && result3[1] == 1.7142857142857142);\n\n free(result3);\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\nmov %rdi,%rbp\nmovslq %edx,%rdi\npush %rbx\nmov %rdi,%r12\nshl $0x3,%rdi\nmov %rsi,%rbx\ncallq 10b0 \ntest %r12d,%r12d\njle 149b \nlea -0x1(%r12),%edx\ncmp $0x2,%edx\njbe 14a0 \nmov %r12d,%edx\nxor %ecx,%ecx\nshr $0x2,%edx\nshl $0x4,%rdx\ncvtdq2pd (%rbx,%rcx,1),%xmm1\ncvtdq2pd 0x0(%rbp,%rcx,1),%xmm0\ndivpd %xmm1,%xmm0\nmovdqu 0x0(%rbp,%rcx,1),%xmm2\nmovdqu (%rbx,%rcx,1),%xmm3\npshufd $0xee,%xmm3,%xmm1\ncvtdq2pd %xmm1,%xmm1\nmovups %xmm0,(%rax,%rcx,2)\npshufd $0xee,%xmm2,%xmm0\ncvtdq2pd %xmm0,%xmm0\ndivpd %xmm1,%xmm0\nmovups %xmm0,0x10(%rax,%rcx,2)\nadd $0x10,%rcx\ncmp %rdx,%rcx\njne 13e0 \nmov %r12d,%edx\nand $0xfffffffc,%edx\ntest $0x3,%r12b\nje 149b \nmovslq %edx,%rcx\npxor %xmm0,%xmm0\npxor %xmm1,%xmm1\ncvtsi2sdl 0x0(%rbp,%rcx,4),%xmm0\ncvtsi2sdl (%rbx,%rcx,4),%xmm1\ndivsd %xmm1,%xmm0\nmovsd %xmm0,(%rax,%rcx,8)\nlea 0x1(%rdx),%ecx\ncmp %ecx,%r12d\njle 149b \nmovslq %ecx,%rcx\npxor %xmm0,%xmm0\npxor %xmm1,%xmm1\nadd $0x2,%edx\ncvtsi2sdl 0x0(%rbp,%rcx,4),%xmm0\ncvtsi2sdl (%rbx,%rcx,4),%xmm1\ndivsd %xmm1,%xmm0\nmovsd %xmm0,(%rax,%rcx,8)\ncmp %edx,%r12d\njle 149b \nmovslq %edx,%rdx\npxor %xmm0,%xmm0\npxor %xmm1,%xmm1\ncvtsi2sdl 0x0(%rbp,%rdx,4),%xmm0\ncvtsi2sdl (%rbx,%rdx,4),%xmm1\ndivsd %xmm1,%xmm0\nmovsd %xmm0,(%rax,%rdx,8)\npop %rbx\npop %rbp\npop %r12\nretq\nxor %edx,%edx\njmp 142e \nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\nmov rbp, rdi\nmovsxd rdi, edx\npush rbx\nmov r12, rdi\nshl rdi, 3; size\nmov rbx, rsi\ncall _malloc\nmov rdx, rax\ntest r12d, r12d\njle loc_14A1\nlea eax, [r12-1]\ncmp eax, 2\njbe loc_14A9\nmov ecx, r12d\nxor eax, eax\nshr ecx, 2\nshl rcx, 4\nnop dword ptr [rax+rax+00h]\nloc_13D8:\ncvtdq2pd xmm1, qword ptr [rbx+rax]\ncvtdq2pd xmm0, qword ptr [rbp+rax+0]\ndivpd xmm0, xmm1\nmovdqu xmm2, xmmword ptr [rbp+rax+0]\nmovdqu xmm3, xmmword ptr [rbx+rax]\npshufd xmm1, xmm3, 0EEh\ncvtdq2pd xmm1, xmm1\nmovups xmmword ptr [rdx+rax*2], xmm0\npshufd xmm0, xmm2, 0EEh\ncvtdq2pd xmm0, xmm0\ndivpd xmm0, xmm1\nmovups xmmword ptr [rdx+rax*2+10h], xmm0\nadd rax, 10h\ncmp rax, rcx\njnz short loc_13D8\nmov ecx, r12d\nand ecx, 0FFFFFFFCh\ntest r12b, 3\njz short loc_14A1\nloc_1426:\nmovsxd rax, ecx\npxor xmm0, xmm0\npxor xmm1, xmm1\ncvtsi2sd xmm0, dword ptr [rbp+rax*4+0]\nlea rsi, ds:0[rax*4]\ncvtsi2sd xmm1, dword ptr [rbx+rax*4]\nlea rdi, ds:0[rax*8]\ndivsd xmm0, xmm1\nmovsd qword ptr [rdx+rax*8], xmm0\nlea eax, [rcx+1]\ncmp r12d, eax\njle short loc_14A1\npxor xmm0, xmm0\npxor xmm1, xmm1\nadd ecx, 2\ncvtsi2sd xmm0, dword ptr [rbp+rsi+4]\ncvtsi2sd xmm1, dword ptr [rbx+rsi+4]\ndivsd xmm0, xmm1\nmovsd qword ptr [rdx+rdi+8], xmm0\ncmp r12d, ecx\njle short loc_14A1\npxor xmm0, xmm0\npxor xmm1, xmm1\ncvtsi2sd xmm0, dword ptr [rbp+rsi+8]\ncvtsi2sd xmm1, dword ptr [rbx+rsi+8]\ndivsd xmm0, xmm1\nmovsd qword ptr [rdx+rdi+10h], xmm0\nloc_14A1:\npop rbx\nmov rax, rdx\npop rbp\npop r12\nretn\nloc_14A9:\nxor ecx, ecx\njmp loc_1426", + "ida_pseudo": "char *__fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n char *v6; // rdx\n __int64 v7; // rax\n __m128i v8; // xmm2\n __m128d v9; // xmm1\n int v10; // ecx\n __int64 v11; // rsi\n __int64 v12; // rdi\n\n v6 = (char *)malloc(8LL * a3);\n if ( a3 > 0 )\n {\n if ( (unsigned int)(a3 - 1) <= 2 )\n {\n v10 = 0;\n }\n else\n {\n v7 = 0LL;\n do\n {\n v8 = _mm_loadu_si128((const __m128i *)(a1 + v7));\n v9 = _mm_cvtepi32_pd(_mm_shuffle_epi32(_mm_loadu_si128((const __m128i *)(a2 + v7)), 238));\n *(__m128d *)&v6[2 * v7] = _mm_div_pd(_mm_cvtepi32_pd(*(__m64 *)(a1 + v7)), _mm_cvtepi32_pd(*(__m64 *)(a2 + v7)));\n *(__m128d *)&v6[2 * v7 + 16] = _mm_div_pd(_mm_cvtepi32_pd(_mm_shuffle_epi32(v8, 238)), v9);\n v7 += 16LL;\n }\n while ( v7 != 16LL * ((unsigned int)a3 >> 2) );\n v10 = a3 & 0x7FFFFFFC;\n if ( (a3 & 3) == 0 )\n return v6;\n }\n v11 = 4LL * v10;\n v12 = 8LL * v10;\n *(double *)&v6[v12] = (double)*(int *)(a1 + v11) / (double)*(int *)(a2 + v11);\n if ( a3 > v10 + 1 )\n {\n *(double *)&v6[v12 + 8] = (double)*(int *)(a1 + v11 + 4) / (double)*(int *)(a2 + v11 + 4);\n if ( a3 > v10 + 2 )\n *(double *)&v6[v12 + 16] = (double)*(int *)(a1 + v11 + 8) / (double)*(int *)(a2 + v11 + 8);\n }\n }\n return v6;\n}", + "ida_strip_asm": "sub_1390:\nendbr64\npush r12\npush rbp\nmov rbp, rdi\nmovsxd rdi, edx\npush rbx\nmov r12, rdi\nshl rdi, 3; size\nmov rbx, rsi\ncall _malloc\nmov rdx, rax\ntest r12d, r12d\njle loc_14A1\nlea eax, [r12-1]\ncmp eax, 2\njbe loc_14A9\nmov ecx, r12d\nxor eax, eax\nshr ecx, 2\nshl rcx, 4\nnop dword ptr [rax+rax+00h]\nloc_13D8:\ncvtdq2pd xmm1, qword ptr [rbx+rax]\ncvtdq2pd xmm0, qword ptr [rbp+rax+0]\ndivpd xmm0, xmm1\nmovdqu xmm2, xmmword ptr [rbp+rax+0]\nmovdqu xmm3, xmmword ptr [rbx+rax]\npshufd xmm1, xmm3, 0EEh\ncvtdq2pd xmm1, xmm1\nmovups xmmword ptr [rdx+rax*2], xmm0\npshufd xmm0, xmm2, 0EEh\ncvtdq2pd xmm0, xmm0\ndivpd xmm0, xmm1\nmovups xmmword ptr [rdx+rax*2+10h], xmm0\nadd rax, 10h\ncmp rax, rcx\njnz short loc_13D8\nmov ecx, r12d\nand ecx, 0FFFFFFFCh\ntest r12b, 3\njz short loc_14A1\nloc_1426:\nmovsxd rax, ecx\npxor xmm0, xmm0\npxor xmm1, xmm1\ncvtsi2sd xmm0, dword ptr [rbp+rax*4+0]\nlea rsi, ds:0[rax*4]\ncvtsi2sd xmm1, dword ptr [rbx+rax*4]\nlea rdi, ds:0[rax*8]\ndivsd xmm0, xmm1\nmovsd qword ptr [rdx+rax*8], xmm0\nlea eax, [rcx+1]\ncmp r12d, eax\njle short loc_14A1\npxor xmm0, xmm0\npxor xmm1, xmm1\nadd ecx, 2\ncvtsi2sd xmm0, dword ptr [rbp+rsi+4]\ncvtsi2sd xmm1, dword ptr [rbx+rsi+4]\ndivsd xmm0, xmm1\nmovsd qword ptr [rdx+rdi+8], xmm0\ncmp r12d, ecx\njle short loc_14A1\npxor xmm0, xmm0\npxor xmm1, xmm1\ncvtsi2sd xmm0, dword ptr [rbp+rsi+8]\ncvtsi2sd xmm1, dword ptr [rbx+rsi+8]\ndivsd xmm0, xmm1\nmovsd qword ptr [rdx+rdi+10h], xmm0\nloc_14A1:\npop rbx\nmov rax, rdx\npop rbp\npop r12\nretn\nloc_14A9:\nxor ecx, ecx\njmp loc_1426", + "ida_strip_pseudo": "char *__fastcall sub_1390(__int64 a1, __int64 a2, int a3)\n{\n char *v6; // rdx\n __int64 v7; // rax\n __m128i v8; // xmm2\n __m128d v9; // xmm1\n int v10; // ecx\n __int64 v11; // rsi\n __int64 v12; // rdi\n\n v6 = (char *)malloc(8LL * a3);\n if ( a3 > 0 )\n {\n if ( (unsigned int)(a3 - 1) <= 2 )\n {\n v10 = 0;\n }\n else\n {\n v7 = 0LL;\n do\n {\n v8 = _mm_loadu_si128((const __m128i *)(a1 + v7));\n v9 = _mm_cvtepi32_pd(_mm_shuffle_epi32(_mm_loadu_si128((const __m128i *)(a2 + v7)), 238));\n *(__m128d *)&v6[2 * v7] = _mm_div_pd(_mm_cvtepi32_pd(*(__m64 *)(a1 + v7)), _mm_cvtepi32_pd(*(__m64 *)(a2 + v7)));\n *(__m128d *)&v6[2 * v7 + 16] = _mm_div_pd(_mm_cvtepi32_pd(_mm_shuffle_epi32(v8, 238)), v9);\n v7 += 16LL;\n }\n while ( v7 != 16LL * ((unsigned int)a3 >> 2) );\n v10 = a3 & 0x7FFFFFFC;\n if ( (a3 & 3) == 0 )\n return v6;\n }\n v11 = 4LL * v10;\n v12 = 8LL * v10;\n *(double *)&v6[v12] = (double)*(int *)(a1 + v11) / (double)*(int *)(a2 + v11);\n if ( a3 > v10 + 1 )\n {\n *(double *)&v6[v12 + 8] = (double)*(int *)(a1 + v11 + 4) / (double)*(int *)(a2 + v11 + 4);\n if ( a3 > v10 + 2 )\n *(double *)&v6[v12 + 16] = (double)*(int *)(a1 + v11 + 8) / (double)*(int *)(a2 + v11 + 8);\n }\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1390(long long a1, long long a2, int a3) {\n char *v6;\n long long v7;\n __m128i v8;\n __m128d v9;\n int v10;\n long long v11;\n long long v12;\n v6 = (char *)malloc(8LL * a3);\n if (a3 > 0) {\n if ((unsigned int)(a3 - 1) <= 2) {\n v10 = 0;\n } else {\n v7 = 0LL;\n do {\n v8 = _mm_loadu_si128((const __m128i *)(a1 + v7));\n v9 = _mm_cvtepi32_pd(_mm_shuffle_epi32(\n _mm_loadu_si128((const __m128i *)(a2 + v7)), 238));\n *(__m128d *)&v6[2 * v7] =\n _mm_div_pd(_mm_cvtepi32_pd(*(__m64 *)(a1 + v7)),\n _mm_cvtepi32_pd(*(__m64 *)(a2 + v7)));\n *(__m128d *)&v6[2 * v7 + 16] =\n _mm_div_pd(_mm_cvtepi32_pd(_mm_shuffle_epi32(v8, 238)), v9);\n v7 += 16LL;\n } while (v7 != 16LL * ((unsigned int)a3 >> 2));\n v10 = a3 & 2147483644;\n if ((a3 & 3) == 0) return v6;\n }\n v11 = 4LL * v10;\n v12 = 8LL * v10;\n *(double *)&v6[v12] =\n (double)*(int *)(a1 + v11) / (double)*(int *)(a2 + v11);\n if (a3 > v10 + 1) {\n *(double *)&v6[v12 + 8] =\n (double)*(int *)(a1 + v11 + 4) / (double)*(int *)(a2 + v11 + 4);\n if (a3 > v10 + 2)\n *(double *)&v6[v12 + 16] =\n (double)*(int *)(a1 + v11 + 8) / (double)*(int *)(a2 + v11 + 8);\n }\n }\n return v6;\n}", + "ida_pseudo_norm": "char *func0(long long a1, long long a2, int a3) {\n char *v6;\n long long v7;\n __m128i v8;\n __m128d v9;\n int v10;\n long long v11;\n long long v12;\n v6 = (char *)malloc(8LL * a3);\n if (a3 > 0) {\n if ((unsigned int)(a3 - 1) <= 2) {\n v10 = 0;\n } else {\n v7 = 0LL;\n do {\n v8 = _mm_loadu_si128((const __m128i *)(a1 + v7));\n v9 = _mm_cvtepi32_pd(_mm_shuffle_epi32(\n _mm_loadu_si128((const __m128i *)(a2 + v7)), 238));\n *(__m128d *)&v6[2 * v7] =\n _mm_div_pd(_mm_cvtepi32_pd(*(__m64 *)(a1 + v7)),\n _mm_cvtepi32_pd(*(__m64 *)(a2 + v7)));\n *(__m128d *)&v6[2 * v7 + 16] =\n _mm_div_pd(_mm_cvtepi32_pd(_mm_shuffle_epi32(v8, 238)), v9);\n v7 += 16LL;\n } while (v7 != 16LL * ((unsigned int)a3 >> 2));\n v10 = a3 & 2147483644;\n if ((a3 & 3) == 0) return v6;\n }\n v11 = 4LL * v10;\n v12 = 8LL * v10;\n *(double *)&v6[v12] =\n (double)*(int *)(a1 + v11) / (double)*(int *)(a2 + v11);\n if (a3 > v10 + 1) {\n *(double *)&v6[v12 + 8] =\n (double)*(int *)(a1 + v11 + 4) / (double)*(int *)(a2 + v11 + 4);\n if (a3 > v10 + 2)\n *(double *)&v6[v12 + 16] =\n (double)*(int *)(a1 + v11 + 8) / (double)*(int *)(a2 + v11 + 8);\n }\n }\n return v6;\n}" + }, + { + "index": 619, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n", + "func": "char* func0(const char* test_str) {\n static char res[1024];\n char dig[1024];\n int i = 0, j = 0;\n for (int idx = 0; test_str[idx] != '\\0'; idx++) {\n if (isdigit(test_str[idx])) {\n dig[j++] = test_str[idx];\n } else {\n res[i++] = test_str[idx];\n }\n }\n dig[j] = '\\0';\n res[i] = '\\0';\n strcat(res, dig);\n return res;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"I1love143you55three3000thousand\"), \"Iloveyouthreethousand1143553000\") == 0);\n\n assert(strcmp(func0(\"Avengers124Assemble\"), \"AvengersAssemble124\") == 0);\n\n assert(strcmp(func0(\"Its11our12path13to14see15things16do17things\"), \"Itsourpathtoseethingsdothings11121314151617\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x430,%rsp\nmov %rdi,-0x428(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovl $0x0,-0x41c(%rbp)\nmovl $0x0,-0x418(%rbp)\nmovl $0x0,-0x414(%rbp)\njmpq 12b2 \ncallq 10d0 <__ctype_b_loc@plt>\nmov (%rax),%rax\nmov -0x414(%rbp),%edx\nmovslq %edx,%rcx\nmov -0x428(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rdx),%edx\nmovsbq %dl,%rdx\nadd %rdx,%rdx\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x800,%eax\ntest %eax,%eax\nje 1279 \nmov -0x414(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x428(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x418(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x418(%rbp)\nmovzbl (%rcx),%edx\ncltq\nmov %dl,-0x410(%rbp,%rax,1)\njmp 12ab \nmov -0x414(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x428(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x41c(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x41c(%rbp)\nmovzbl (%rcx),%edx\ncltq\nlea 0x2d98(%rip),%rcx\nmov %dl,(%rax,%rcx,1)\naddl $0x1,-0x414(%rbp)\nmov -0x414(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x428(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 1211 \nmov -0x418(%rbp),%eax\ncltq\nmovb $0x0,-0x410(%rbp,%rax,1)\nmov -0x41c(%rbp),%eax\ncltq\nlea 0x2d51(%rip),%rdx\nmovb $0x0,(%rax,%rdx,1)\nlea -0x410(%rbp),%rax\nmov %rax,%rsi\nlea 0x2d3c(%rip),%rdi\ncallq 10c0 \nlea 0x2d30(%rip),%rax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 1324 \ncallq 1090 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 430h\nmov [rbp+var_428], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_41C], 0\nmov [rbp+var_418], 0\nmov [rbp+var_414], 0\njmp loc_12B2\nloc_1211:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_414]\nmovsxd rcx, edx\nmov rdx, [rbp+var_428]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 800h\ntest eax, eax\njz short loc_1279\nmov eax, [rbp+var_414]\nmovsxd rdx, eax\nmov rax, [rbp+var_428]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_418]\nlea edx, [rax+1]\nmov [rbp+var_418], edx\nmovzx edx, byte ptr [rcx]\ncdqe\nmov [rbp+rax+src], dl\njmp short loc_12AB\nloc_1279:\nmov eax, [rbp+var_414]\nmovsxd rdx, eax\nmov rax, [rbp+var_428]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_41C]\nlea edx, [rax+1]\nmov [rbp+var_41C], edx\nmovzx edx, byte ptr [rcx]\ncdqe\nlea rcx, res_1\nmov [rax+rcx], dl\nloc_12AB:\nadd [rbp+var_414], 1\nloc_12B2:\nmov eax, [rbp+var_414]\nmovsxd rdx, eax\nmov rax, [rbp+var_428]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_1211\nmov eax, [rbp+var_418]\ncdqe\nmov [rbp+rax+src], 0\nmov eax, [rbp+var_41C]\ncdqe\nlea rdx, res_1\nmov byte ptr [rax+rdx], 0\nlea rax, [rbp+src]\nmov rsi, rax; src\nlea rax, res_1\nmov rdi, rax; dest\ncall _strcat\nlea rax, res_1\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1327\ncall ___stack_chk_fail\nlocret_1327:\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1)\n{\n int v1; // eax\n int v2; // eax\n int v4; // [rsp+14h] [rbp-41Ch]\n int v5; // [rsp+18h] [rbp-418h]\n int i; // [rsp+1Ch] [rbp-414h]\n char src[1032]; // [rsp+20h] [rbp-410h] BYREF\n unsigned __int64 v8; // [rsp+428h] [rbp-8h]\n\n v8 = __readfsqword(0x28u);\n v4 = 0;\n v5 = 0;\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n {\n if ( ((*__ctype_b_loc())[*(char *)(i + a1)] & 0x800) != 0 )\n {\n v1 = v5++;\n src[v1] = *(_BYTE *)(i + a1);\n }\n else\n {\n v2 = v4++;\n res_1[v2] = *(_BYTE *)(i + a1);\n }\n }\n src[v5] = 0;\n res_1[v4] = 0;\n strcat(res_1, src);\n return res_1;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 430h\nmov [rbp+var_428], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_41C], 0\nmov [rbp+var_418], 0\nmov [rbp+var_414], 0\njmp loc_12B2\nloc_1211:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_414]\nmovsxd rcx, edx\nmov rdx, [rbp+var_428]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 800h\ntest eax, eax\njz short loc_1279\nmov eax, [rbp+var_414]\nmovsxd rdx, eax\nmov rax, [rbp+var_428]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_418]\nlea edx, [rax+1]\nmov [rbp+var_418], edx\nmovzx edx, byte ptr [rcx]\ncdqe\nmov [rbp+rax+src], dl\njmp short loc_12AB\nloc_1279:\nmov eax, [rbp+var_414]\nmovsxd rdx, eax\nmov rax, [rbp+var_428]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_41C]\nlea edx, [rax+1]\nmov [rbp+var_41C], edx\nmovzx edx, byte ptr [rcx]\ncdqe\nlea rcx, dest\nmov [rax+rcx], dl\nloc_12AB:\nadd [rbp+var_414], 1\nloc_12B2:\nmov eax, [rbp+var_414]\nmovsxd rdx, eax\nmov rax, [rbp+var_428]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_1211\nmov eax, [rbp+var_418]\ncdqe\nmov [rbp+rax+src], 0\nmov eax, [rbp+var_41C]\ncdqe\nlea rdx, dest\nmov byte ptr [rax+rdx], 0\nlea rax, [rbp+src]\nmov rsi, rax; src\nlea rax, dest\nmov rdi, rax; dest\ncall _strcat\nlea rax, dest\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1327\ncall ___stack_chk_fail\nlocret_1327:\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11C9(__int64 a1)\n{\n int v1; // eax\n int v2; // eax\n int v4; // [rsp+14h] [rbp-41Ch]\n int v5; // [rsp+18h] [rbp-418h]\n int i; // [rsp+1Ch] [rbp-414h]\n char src[1032]; // [rsp+20h] [rbp-410h] BYREF\n unsigned __int64 v8; // [rsp+428h] [rbp-8h]\n\n v8 = __readfsqword(0x28u);\n v4 = 0;\n v5 = 0;\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n {\n if ( ((*__ctype_b_loc())[*(char *)(i + a1)] & 0x800) != 0 )\n {\n v1 = v5++;\n src[v1] = *(_BYTE *)(i + a1);\n }\n else\n {\n v2 = v4++;\n dest[v2] = *(_BYTE *)(i + a1);\n }\n }\n src[v5] = 0;\n dest[v4] = 0;\n strcat(dest, src);\n return dest;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11C9(long long a1) {\n int v1;\n int v2;\n int v4;\n int v5;\n int i;\n char src[1032];\n unsigned long long v8;\n v8 = __readfsqword(40u);\n v4 = 0;\n v5 = 0;\n for (i = 0; *(uint8_t *)(i + a1); ++i) {\n if (((*__ctype_b_loc())[*(char *)(i + a1)] & 2048) != 0) {\n v1 = v5++;\n src[v1] = *(uint8_t *)(i + a1);\n } else {\n v2 = v4++;\n dest[v2] = *(uint8_t *)(i + a1);\n }\n }\n src[v5] = 0;\n dest[v4] = 0;\n strcat(dest, src);\n return dest;\n}", + "ida_pseudo_norm": "char *func0(long long a1) {\n int v1;\n int v2;\n int v4;\n int v5;\n int i;\n char src[1032];\n unsigned long long v8;\n v8 = __readfsqword(40u);\n v4 = 0;\n v5 = 0;\n for (i = 0; *(uint8_t *)(i + a1); ++i) {\n if (((*__ctype_b_loc())[*(char *)(i + a1)] & 2048) != 0) {\n v1 = v5++;\n src[v1] = *(uint8_t *)(i + a1);\n } else {\n v2 = v4++;\n res_1[v2] = *(uint8_t *)(i + a1);\n }\n }\n src[v5] = 0;\n res_1[v4] = 0;\n strcat(res_1, src);\n return res_1;\n}" + }, + { + "index": 619, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n", + "func": "char* func0(const char* test_str) {\n static char res[1024];\n char dig[1024];\n int i = 0, j = 0;\n for (int idx = 0; test_str[idx] != '\\0'; idx++) {\n if (isdigit(test_str[idx])) {\n dig[j++] = test_str[idx];\n } else {\n res[i++] = test_str[idx];\n }\n }\n dig[j] = '\\0';\n res[i] = '\\0';\n strcat(res, dig);\n return res;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"I1love143you55three3000thousand\"), \"Iloveyouthreethousand1143553000\") == 0);\n\n assert(strcmp(func0(\"Avengers124Assemble\"), \"AvengersAssemble124\") == 0);\n\n assert(strcmp(func0(\"Its11our12path13to14see15things16do17things\"), \"Itsourpathtoseethingsdothings11121314151617\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x418,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x408(%rsp)\nxor %eax,%eax\nmovzbl (%rdi),%ebx\ntest %bl,%bl\nje 1220 \nmov %rdi,%rbp\ncallq 10b0 <__ctype_b_loc@plt>\nlea 0x1(%rbp),%rdi\nmov $0x0,%r8d\nmov $0x0,%esi\nlea 0x2e52(%rip),%r9\njmp 1206 \nmovslq %esi,%rdx\nmov %bl,(%r9,%rdx,1)\nlea 0x1(%rsi),%esi\nadd $0x1,%rdi\nmovzbl -0x1(%rdi),%ebx\ntest %bl,%bl\nje 122b \nmovsbq %bl,%rdx\nmov (%rax),%rcx\ntestb $0x8,0x1(%rcx,%rdx,2)\nje 11f0 \nmovslq %r8d,%rdx\nmov %bl,(%rsp,%rdx,1)\nlea 0x1(%r8),%r8d\njmp 11fa \nmov $0x0,%r8d\nmov $0x0,%esi\nmovslq %r8d,%r8\nmovb $0x0,(%rsp,%r8,1)\nlea 0x2e06(%rip),%rbx\nmovslq %esi,%rsi\nmovb $0x0,(%rbx,%rsi,1)\nmov %rsp,%rsi\nmov $0x400,%edx\nmov %rbx,%rdi\ncallq 1080 <__strcat_chk@plt>\nmov 0x408(%rsp),%rax\nxor %fs:0x28,%rax\njne 1271 \nmov %rbx,%rax\nadd $0x418,%rsp\npop %rbx\npop %rbp\nretq\ncallq 1090 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 418h\nmov rax, fs:28h\nmov [rsp+428h+var_20], rax\nxor eax, eax\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_1240\nmov rbp, rdi\ncall ___ctype_b_loc\nlea rdi, [rbp+1]\nmov r8d, 0\nmov esi, 0\nlea r9, res_1\njmp short loc_1226\nloc_1210:\nmovsxd rdx, esi\nmov [r9+rdx], bl\nlea esi, [rsi+1]\nloc_121A:\nadd rdi, 1\nmovzx ebx, byte ptr [rdi-1]\ntest bl, bl\njz short loc_124B\nloc_1226:\nmovsx rdx, bl\nmov rcx, [rax]\ntest byte ptr [rcx+rdx*2+1], 8\njz short loc_1210\nmovsxd rdx, r8d\nmov [rsp+rdx+428h+var_428], bl\nlea r8d, [r8+1]\njmp short loc_121A\nloc_1240:\nmov r8d, 0\nmov esi, 0\nloc_124B:\nmovsxd r8, r8d\nmov [rsp+r8+428h+var_428], 0\nlea rbx, res_1\nmovsxd rsi, esi\nmov byte ptr [rbx+rsi], 0\nmov rsi, rsp\nmov edx, 400h\nmov rdi, rbx\ncall ___strcat_chk\nmov rax, [rsp+428h+var_20]\nsub rax, fs:28h\njnz short loc_1291\nmov rax, rbx\nadd rsp, 418h\npop rbx\npop rbp\nretn\nloc_1291:\ncall ___stack_chk_fail", + "ida_pseudo": "_BYTE *__fastcall func0(char *a1, __int64 a2, __int64 a3, const unsigned __int16 *a4, __int64 a5, _BYTE *a6)\n{\n char v6; // bl\n const unsigned __int16 **v7; // rax\n char *v8; // rdi\n int v9; // r8d\n int v10; // esi\n _BYTE v12[1032]; // [rsp+0h] [rbp-428h] BYREF\n unsigned __int64 v13; // [rsp+408h] [rbp-20h]\n\n v13 = __readfsqword(0x28u);\n v6 = *a1;\n if ( *a1 )\n {\n v7 = __ctype_b_loc();\n v8 = a1 + 1;\n v9 = 0;\n v10 = 0;\n a6 = res_1;\n do\n {\n a4 = *v7;\n if ( ((*v7)[v6] & 0x800) != 0 )\n v12[v9++] = v6;\n else\n res_1[v10++] = v6;\n v6 = *v8++;\n }\n while ( v6 );\n }\n else\n {\n v9 = 0;\n v10 = 0;\n }\n v12[v9] = 0;\n res_1[v10] = 0;\n __strcat_chk(res_1, v12, 1024LL, a4, v9, a6);\n return res_1;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\npush rbx\nsub rsp, 418h\nmov rax, fs:28h\nmov [rsp+428h+var_20], rax\nxor eax, eax\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_1240\nmov rbp, rdi\ncall ___ctype_b_loc\nlea rdi, [rbp+1]\nmov r8d, 0\nmov esi, 0\nlea r9, unk_4040\njmp short loc_1226\nloc_1210:\nmovsxd rdx, esi\nmov [r9+rdx], bl\nlea esi, [rsi+1]\nloc_121A:\nadd rdi, 1\nmovzx ebx, byte ptr [rdi-1]\ntest bl, bl\njz short loc_124B\nloc_1226:\nmovsx rdx, bl\nmov rcx, [rax]\ntest byte ptr [rcx+rdx*2+1], 8\njz short loc_1210\nmovsxd rdx, r8d\nmov [rsp+rdx+428h+var_428], bl\nlea r8d, [r8+1]\njmp short loc_121A\nloc_1240:\nmov r8d, 0\nmov esi, 0\nloc_124B:\nmovsxd r8, r8d\nmov [rsp+r8+428h+var_428], 0\nlea rbx, unk_4040\nmovsxd rsi, esi\nmov byte ptr [rbx+rsi], 0\nmov rsi, rsp\nmov edx, 400h\nmov rdi, rbx\ncall ___strcat_chk\nmov rax, [rsp+428h+var_20]\nsub rax, fs:28h\njnz short loc_1291\nmov rax, rbx\nadd rsp, 418h\npop rbx\npop rbp\nretn\nloc_1291:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_BYTE *__fastcall sub_11C9(char *a1, __int64 a2, __int64 a3, const unsigned __int16 *a4, __int64 a5, _BYTE *a6)\n{\n char v6; // bl\n const unsigned __int16 **v7; // rax\n char *v8; // rdi\n int v9; // r8d\n int v10; // esi\n _BYTE v12[1032]; // [rsp+0h] [rbp-428h] BYREF\n unsigned __int64 v13; // [rsp+408h] [rbp-20h]\n\n v13 = __readfsqword(0x28u);\n v6 = *a1;\n if ( *a1 )\n {\n v7 = __ctype_b_loc();\n v8 = a1 + 1;\n v9 = 0;\n v10 = 0;\n a6 = byte_4040;\n do\n {\n a4 = *v7;\n if ( ((*v7)[v6] & 0x800) != 0 )\n v12[v9++] = v6;\n else\n byte_4040[v10++] = v6;\n v6 = *v8++;\n }\n while ( v6 );\n }\n else\n {\n v9 = 0;\n v10 = 0;\n }\n v12[v9] = 0;\n byte_4040[v10] = 0;\n __strcat_chk(byte_4040, v12, 1024LL, a4, v9, a6);\n return byte_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_11C9(char *a1, long long a2, long long a3,\n const unsigned short *a4, long long a5, uint8_t *a6) {\n char v6;\n const unsigned short **v7;\n char *v8;\n int v9;\n int v10;\n uint8_t v12[1032];\n unsigned long long v13;\n v13 = __readfsqword(40u);\n v6 = *a1;\n if (*a1) {\n v7 = __ctype_b_loc();\n v8 = a1 + 1;\n v9 = 0;\n v10 = 0;\n a6 = byte_4040;\n do {\n a4 = *v7;\n if (((*v7)[v6] & 2048) != 0)\n v12[v9++] = v6;\n else\n byte_4040[v10++] = v6;\n v6 = *v8++;\n } while (v6);\n } else {\n v9 = 0;\n v10 = 0;\n }\n v12[v9] = 0;\n byte_4040[v10] = 0;\n __strcat_chk(byte_4040, v12, 1024LL, a4, v9, a6);\n return byte_4040;\n}", + "ida_pseudo_norm": "uint8_t *func0(char *a1, long long a2, long long a3, const unsigned short *a4,\n long long a5, uint8_t *a6) {\n char v6;\n const unsigned short **v7;\n char *v8;\n int v9;\n int v10;\n uint8_t v12[1032];\n unsigned long long v13;\n v13 = __readfsqword(40u);\n v6 = *a1;\n if (*a1) {\n v7 = __ctype_b_loc();\n v8 = a1 + 1;\n v9 = 0;\n v10 = 0;\n a6 = res_1;\n do {\n a4 = *v7;\n if (((*v7)[v6] & 2048) != 0)\n v12[v9++] = v6;\n else\n res_1[v10++] = v6;\n v6 = *v8++;\n } while (v6);\n } else {\n v9 = 0;\n v10 = 0;\n }\n v12[v9] = 0;\n res_1[v10] = 0;\n __strcat_chk(res_1, v12, 1024LL, a4, v9, a6);\n return res_1;\n}" + }, + { + "index": 619, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n", + "func": "char* func0(const char* test_str) {\n static char res[1024];\n char dig[1024];\n int i = 0, j = 0;\n for (int idx = 0; test_str[idx] != '\\0'; idx++) {\n if (isdigit(test_str[idx])) {\n dig[j++] = test_str[idx];\n } else {\n res[i++] = test_str[idx];\n }\n }\n dig[j] = '\\0';\n res[i] = '\\0';\n strcat(res, dig);\n return res;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"I1love143you55three3000thousand\"), \"Iloveyouthreethousand1143553000\") == 0);\n\n assert(strcmp(func0(\"Avengers124Assemble\"), \"AvengersAssemble124\") == 0);\n\n assert(strcmp(func0(\"Its11our12path13to14see15things16do17things\"), \"Itsourpathtoseethingsdothings11121314151617\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x418,%rsp\nmovzbl (%rdi),%ebx\nmov %fs:0x28,%rax\nmov %rax,0x408(%rsp)\nxor %eax,%eax\ntest %bl,%bl\nje 1360 \nmov %rdi,%rbp\ncallq 10b0 <__ctype_b_loc@plt>\nlea 0x1(%rbp),%rdi\nxor %r8d,%r8d\nxor %esi,%esi\nlea 0x2d6d(%rip),%r9\njmp 12ee \nnopl (%rax)\nmovslq %r8d,%rdx\nadd $0x1,%rdi\nadd $0x1,%r8d\nmov %bl,(%rsp,%rdx,1)\nmovzbl -0x1(%rdi),%ebx\ntest %bl,%bl\nje 1312 \nmov (%rax),%rcx\nmovsbq %bl,%rdx\ntestb $0x8,0x1(%rcx,%rdx,2)\njne 12d8 \nmovslq %esi,%rdx\nadd $0x1,%rdi\nadd $0x1,%esi\nmov %bl,(%r9,%rdx,1)\nmovzbl -0x1(%rdi),%ebx\ntest %bl,%bl\njne 12ee \nmovslq %esi,%rsi\nmovslq %r8d,%r8\nmov $0x400,%edx\nmovb $0x0,(%r9,%rsi,1)\nlea 0x2d17(%rip),%rdi\nmov %rsp,%rsi\nmovb $0x0,(%rsp,%r8,1)\ncallq 1080 <__strcat_chk@plt>\nmov 0x408(%rsp),%rax\nxor %fs:0x28,%rax\njne 136e \nadd $0x418,%rsp\nlea 0x2ce9(%rip),%rax\npop %rbx\npop %rbp\nretq\nnopw 0x0(%rax,%rax,1)\nxor %r8d,%r8d\nxor %esi,%esi\nlea 0x2cd4(%rip),%r9\njmp 1312 \ncallq 1090 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 418h\nmovzx ebx, byte ptr [rdi]\nmov rax, fs:28h\nmov [rsp+428h+var_20], rax\nxor eax, eax\ntest bl, bl\njz loc_1368\nmov rbp, rdi\ncall ___ctype_b_loc\nlea rdi, [rbp+1]\nxor r8d, r8d\nxor esi, esi\nlea r9, res_1\njmp short loc_12FE\nloc_12E8:\nmovsxd rdx, r8d\nadd rdi, 1\nadd r8d, 1\nmov [rsp+rdx+428h+var_428], bl\nmovzx ebx, byte ptr [rdi-1]\ntest bl, bl\njz short loc_1322\nloc_12FE:\nmov rcx, [rax]\nmovsx rdx, bl\ntest byte ptr [rcx+rdx*2+1], 8\njnz short loc_12E8\nmovsxd rdx, esi\nadd rdi, 1\nadd esi, 1\nmov [r9+rdx], bl\nmovzx ebx, byte ptr [rdi-1]\ntest bl, bl\njnz short loc_12FE\nloc_1322:\nmovsxd rsi, esi\nmovsxd r8, r8d\nmov rdi, r9\nmov edx, 400h\nmov byte ptr [r9+rsi], 0\nmov rsi, rsp\nmov [rsp+r8+428h+var_428], 0\ncall ___strcat_chk\nmov r9, rax\nmov rax, [rsp+428h+var_20]\nsub rax, fs:28h\njnz short loc_1376\nadd rsp, 418h\nmov rax, r9\npop rbx\npop rbp\nretn\nloc_1368:\nxor r8d, r8d\nxor esi, esi\nlea r9, res_1\njmp short loc_1322\nloc_1376:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(char *a1)\n{\n char v1; // bl\n const unsigned __int16 **v2; // rax\n _BYTE *v3; // rdi\n int v4; // r8d\n int v5; // esi\n __int64 v6; // rdx\n __int64 v7; // rdx\n _BYTE v9[1032]; // [rsp+0h] [rbp-428h] BYREF\n unsigned __int64 v10; // [rsp+408h] [rbp-20h]\n\n v1 = *a1;\n v10 = __readfsqword(0x28u);\n if ( v1 )\n {\n v2 = __ctype_b_loc();\n v3 = a1 + 1;\n v4 = 0;\n v5 = 0;\n do\n {\n while ( ((*v2)[v1] & 0x800) != 0 )\n {\n v6 = v4;\n ++v3;\n ++v4;\n v9[v6] = v1;\n v1 = *(v3 - 1);\n if ( !v1 )\n goto LABEL_6;\n }\n v7 = v5;\n ++v3;\n ++v5;\n res_1[v7] = v1;\n v1 = *(v3 - 1);\n }\n while ( v1 );\n }\n else\n {\n v4 = 0;\n v5 = 0;\n }\nLABEL_6:\n res_1[v5] = 0;\n v9[v4] = 0;\n return __strcat_chk(res_1, v9, 1024LL);\n}", + "ida_strip_asm": "sub_12A0:\nendbr64\npush rbp\npush rbx\nsub rsp, 418h\nmovzx ebx, byte ptr [rdi]\nmov rax, fs:28h\nmov [rsp+428h+var_20], rax\nxor eax, eax\ntest bl, bl\njz loc_1368\nmov rbp, rdi\ncall ___ctype_b_loc\nlea rdi, [rbp+1]\nxor r8d, r8d\nxor esi, esi\nlea r9, unk_4040\njmp short loc_12FE\nloc_12E8:\nmovsxd rdx, r8d\nadd rdi, 1\nadd r8d, 1\nmov [rsp+rdx+428h+var_428], bl\nmovzx ebx, byte ptr [rdi-1]\ntest bl, bl\njz short loc_1322\nloc_12FE:\nmov rcx, [rax]\nmovsx rdx, bl\ntest byte ptr [rcx+rdx*2+1], 8\njnz short loc_12E8\nmovsxd rdx, esi\nadd rdi, 1\nadd esi, 1\nmov [r9+rdx], bl\nmovzx ebx, byte ptr [rdi-1]\ntest bl, bl\njnz short loc_12FE\nloc_1322:\nmovsxd rsi, esi\nmovsxd r8, r8d\nmov rdi, r9\nmov edx, 400h\nmov byte ptr [r9+rsi], 0\nmov rsi, rsp\nmov [rsp+r8+428h+var_428], 0\ncall ___strcat_chk\nmov r9, rax\nmov rax, [rsp+428h+var_20]\nsub rax, fs:28h\njnz short loc_1376\nadd rsp, 418h\nmov rax, r9\npop rbx\npop rbp\nretn\nloc_1368:\nxor r8d, r8d\nxor esi, esi\nlea r9, unk_4040\njmp short loc_1322\nloc_1376:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12A0(char *a1)\n{\n char v1; // bl\n const unsigned __int16 **v2; // rax\n _BYTE *v3; // rdi\n int v4; // r8d\n int v5; // esi\n __int64 v6; // rdx\n __int64 v7; // rdx\n _BYTE v9[1032]; // [rsp+0h] [rbp-428h] BYREF\n unsigned __int64 v10; // [rsp+408h] [rbp-20h]\n\n v1 = *a1;\n v10 = __readfsqword(0x28u);\n if ( v1 )\n {\n v2 = __ctype_b_loc();\n v3 = a1 + 1;\n v4 = 0;\n v5 = 0;\n do\n {\n while ( ((*v2)[v1] & 0x800) != 0 )\n {\n v6 = v4;\n ++v3;\n ++v4;\n v9[v6] = v1;\n v1 = *(v3 - 1);\n if ( !v1 )\n goto LABEL_6;\n }\n v7 = v5;\n ++v3;\n ++v5;\n byte_4040[v7] = v1;\n v1 = *(v3 - 1);\n }\n while ( v1 );\n }\n else\n {\n v4 = 0;\n v5 = 0;\n }\nLABEL_6:\n byte_4040[v5] = 0;\n v9[v4] = 0;\n return __strcat_chk(byte_4040, v9, 1024LL);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12A0(char *a1) {\n char v1;\n const unsigned short **v2;\n uint8_t *v3;\n int v4;\n int v5;\n long long v6;\n long long v7;\n uint8_t v9[1032];\n unsigned long long v10;\n v1 = *a1;\n v10 = __readfsqword(40u);\n if (v1) {\n v2 = __ctype_b_loc();\n v3 = a1 + 1;\n v4 = 0;\n v5 = 0;\n do {\n while (((*v2)[v1] & 2048) != 0) {\n v6 = v4;\n ++v3;\n ++v4;\n v9[v6] = v1;\n v1 = *(v3 - 1);\n if (!v1) goto LABEL_6;\n }\n v7 = v5;\n ++v3;\n ++v5;\n byte_4040[v7] = v1;\n v1 = *(v3 - 1);\n } while (v1);\n } else {\n v4 = 0;\n v5 = 0;\n }\nLABEL_6:\n byte_4040[v5] = 0;\n v9[v4] = 0;\n return __strcat_chk(byte_4040, v9, 1024LL);\n}", + "ida_pseudo_norm": "long long func0(char *a1) {\n char v1;\n const unsigned short **v2;\n uint8_t *v3;\n int v4;\n int v5;\n long long v6;\n long long v7;\n uint8_t v9[1032];\n unsigned long long v10;\n v1 = *a1;\n v10 = __readfsqword(40u);\n if (v1) {\n v2 = __ctype_b_loc();\n v3 = a1 + 1;\n v4 = 0;\n v5 = 0;\n do {\n while (((*v2)[v1] & 2048) != 0) {\n v6 = v4;\n ++v3;\n ++v4;\n v9[v6] = v1;\n v1 = *(v3 - 1);\n if (!v1) goto LABEL_6;\n }\n v7 = v5;\n ++v3;\n ++v5;\n res_1[v7] = v1;\n v1 = *(v3 - 1);\n } while (v1);\n } else {\n v4 = 0;\n v5 = 0;\n }\nLABEL_6:\n res_1[v5] = 0;\n v9[v4] = 0;\n return __strcat_chk(res_1, v9, 1024LL);\n}" + }, + { + "index": 619, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n", + "func": "char* func0(const char* test_str) {\n static char res[1024];\n char dig[1024];\n int i = 0, j = 0;\n for (int idx = 0; test_str[idx] != '\\0'; idx++) {\n if (isdigit(test_str[idx])) {\n dig[j++] = test_str[idx];\n } else {\n res[i++] = test_str[idx];\n }\n }\n dig[j] = '\\0';\n res[i] = '\\0';\n strcat(res, dig);\n return res;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"I1love143you55three3000thousand\"), \"Iloveyouthreethousand1143553000\") == 0);\n\n assert(strcmp(func0(\"Avengers124Assemble\"), \"AvengersAssemble124\") == 0);\n\n assert(strcmp(func0(\"Its11our12path13to14see15things16do17things\"), \"Itsourpathtoseethingsdothings11121314151617\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x418,%rsp\nmovzbl (%rdi),%ebx\nmov %fs:0x28,%rax\nmov %rax,0x408(%rsp)\nxor %eax,%eax\ntest %bl,%bl\nje 1328 \nmov %rdi,%rbp\ncallq 10b0 <__ctype_b_loc@plt>\nlea 0x1(%rbp),%rdi\nxor %ecx,%ecx\nxor %edx,%edx\nmov (%rax),%r8\nlea 0x2d6f(%rip),%r9\nnopl 0x0(%rax)\nmovsbq %bl,%rsi\ntestb $0x8,0x1(%r8,%rsi,2)\nje 1305 \nadd $0x1,%rdi\nmov %bl,(%rsp,%rcx,1)\nlea 0x1(%rcx),%esi\nmovzbl -0x1(%rdi),%ebx\ntest %bl,%bl\nje 1338 \nmovslq %esi,%rcx\nmovsbq %bl,%rsi\ntestb $0x8,0x1(%r8,%rsi,2)\njne 12e4 \nadd $0x1,%rdi\nmov %bl,(%r9,%rdx,1)\nlea 0x1(%rdx),%r8d\nmovzbl -0x1(%rdi),%ebx\ntest %bl,%bl\nje 1380 \nmovslq %r8d,%rdx\nmov (%rax),%r8\njmp 12d8 \nnopl 0x0(%rax)\nxor %esi,%esi\nxor %edx,%edx\nlea 0x2d0d(%rip),%r9\nnopl 0x0(%rax,%rax,1)\nmovslq %esi,%rsi\nmovb $0x0,(%r9,%rdx,1)\nlea 0x2cf9(%rip),%rdi\nmov $0x400,%edx\nmovb $0x0,(%rsp,%rsi,1)\nmov %rsp,%rsi\ncallq 1080 <__strcat_chk@plt>\nmov 0x408(%rsp),%rax\nxor %fs:0x28,%rax\njne 1387 \nadd $0x418,%rsp\nlea 0x2cc7(%rip),%rax\npop %rbx\npop %rbp\nretq\nnopl 0x0(%rax)\nmov %ecx,%esi\nmovslq %r8d,%rdx\njmp 1338 \ncallq 1090 <__stack_chk_fail@plt>\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 418h\nmovzx ebx, byte ptr [rdi]\nmov rax, fs:28h\nmov [rsp+428h+var_20], rax\nxor eax, eax\ntest bl, bl\njz loc_1370\nmov rbp, rdi\ncall ___ctype_b_loc\nlea rdi, [rbp+1]\nxor edx, edx\nxor ecx, ecx\nmov r8, [rax]\nlea r9, res_1\nnop dword ptr [rax]\nloc_12E8:\nmovsx rsi, bl\ntest byte ptr [r8+rsi*2+1], 8\njz short loc_1350\nadd rdi, 1\nmov [rsp+rdx+428h+var_428], bl\nlea esi, [rdx+1]\nmovzx ebx, byte ptr [rdi-1]\nmovsxd rdx, esi\ntest bl, bl\njnz short loc_12E8\nmov esi, ecx\nloc_130B:\nmovsxd rsi, esi\nmov [rsp+rdx+428h+var_428], 0\nmov rdi, r9\nmov edx, 400h\nmov byte ptr [r9+rsi], 0\nmov rsi, rsp\ncall ___strcat_chk\nmov r9, rax\nmov rax, [rsp+428h+var_20]\nsub rax, fs:28h\njnz short loc_137D\nadd rsp, 418h\nmov rax, r9\npop rbx\npop rbp\nretn\nloc_1350:\nadd rdi, 1\nmov [r9+rcx], bl\nlea esi, [rcx+1]\nmovzx ebx, byte ptr [rdi-1]\ntest bl, bl\njz short loc_130B\nmov r8, [rax]\nmovsxd rcx, esi\njmp loc_12E8\nloc_1370:\nxor edx, edx\nxor esi, esi\nlea r9, res_1\njmp short loc_130B\nloc_137D:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(char *a1)\n{\n char v1; // bl\n const unsigned __int16 **v2; // rax\n _BYTE *v3; // rdi\n __int64 v4; // rdx\n __int64 v5; // rcx\n const unsigned __int16 *v6; // r8\n int v7; // esi\n _BYTE v9[1032]; // [rsp+0h] [rbp-428h] BYREF\n unsigned __int64 v10; // [rsp+408h] [rbp-20h]\n\n v1 = *a1;\n v10 = __readfsqword(0x28u);\n if ( v1 )\n {\n v2 = __ctype_b_loc();\n v3 = a1 + 1;\n v4 = 0LL;\n v5 = 0LL;\n v6 = *v2;\n do\n {\n while ( (v6[v1] & 0x800) == 0 )\n {\n ++v3;\n res_1[v5] = v1;\n v7 = v5 + 1;\n v1 = *(v3 - 1);\n if ( !v1 )\n goto LABEL_6;\n v6 = *v2;\n v5 = v7;\n }\n ++v3;\n v9[v4] = v1;\n v1 = *(v3 - 1);\n v4 = (int)v4 + 1;\n }\n while ( v1 );\n v7 = v5;\n }\n else\n {\n v4 = 0LL;\n v7 = 0;\n }\nLABEL_6:\n v9[v4] = 0;\n res_1[v7] = 0;\n return __strcat_chk(res_1, v9, 1024LL);\n}", + "ida_strip_asm": "sub_12A0:\nendbr64\npush rbp\npush rbx\nsub rsp, 418h\nmovzx ebx, byte ptr [rdi]\nmov rax, fs:28h\nmov [rsp+428h+var_20], rax\nxor eax, eax\ntest bl, bl\njz loc_1370\nmov rbp, rdi\ncall ___ctype_b_loc\nlea rdi, [rbp+1]\nxor edx, edx\nxor ecx, ecx\nmov r8, [rax]\nlea r9, unk_4040\nnop dword ptr [rax]\nloc_12E8:\nmovsx rsi, bl\ntest byte ptr [r8+rsi*2+1], 8\njz short loc_1350\nadd rdi, 1\nmov [rsp+rdx+428h+var_428], bl\nlea esi, [rdx+1]\nmovzx ebx, byte ptr [rdi-1]\nmovsxd rdx, esi\ntest bl, bl\njnz short loc_12E8\nmov esi, ecx\nloc_130B:\nmovsxd rsi, esi\nmov [rsp+rdx+428h+var_428], 0\nmov rdi, r9\nmov edx, 400h\nmov byte ptr [r9+rsi], 0\nmov rsi, rsp\ncall ___strcat_chk\nmov r9, rax\nmov rax, [rsp+428h+var_20]\nsub rax, fs:28h\njnz short loc_137D\nadd rsp, 418h\nmov rax, r9\npop rbx\npop rbp\nretn\nloc_1350:\nadd rdi, 1\nmov [r9+rcx], bl\nlea esi, [rcx+1]\nmovzx ebx, byte ptr [rdi-1]\ntest bl, bl\njz short loc_130B\nmov r8, [rax]\nmovsxd rcx, esi\njmp loc_12E8\nloc_1370:\nxor edx, edx\nxor esi, esi\nlea r9, unk_4040\njmp short loc_130B\nloc_137D:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12A0(char *a1)\n{\n char v1; // bl\n const unsigned __int16 **v2; // rax\n _BYTE *v3; // rdi\n __int64 v4; // rdx\n __int64 v5; // rcx\n const unsigned __int16 *v6; // r8\n int v7; // esi\n _BYTE v9[1032]; // [rsp+0h] [rbp-428h] BYREF\n unsigned __int64 v10; // [rsp+408h] [rbp-20h]\n\n v1 = *a1;\n v10 = __readfsqword(0x28u);\n if ( v1 )\n {\n v2 = __ctype_b_loc();\n v3 = a1 + 1;\n v4 = 0LL;\n v5 = 0LL;\n v6 = *v2;\n do\n {\n while ( (v6[v1] & 0x800) == 0 )\n {\n ++v3;\n byte_4040[v5] = v1;\n v7 = v5 + 1;\n v1 = *(v3 - 1);\n if ( !v1 )\n goto LABEL_6;\n v6 = *v2;\n v5 = v7;\n }\n ++v3;\n v9[v4] = v1;\n v1 = *(v3 - 1);\n v4 = (int)v4 + 1;\n }\n while ( v1 );\n v7 = v5;\n }\n else\n {\n v4 = 0LL;\n v7 = 0;\n }\nLABEL_6:\n v9[v4] = 0;\n byte_4040[v7] = 0;\n return __strcat_chk(byte_4040, v9, 1024LL);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12A0(char *a1) {\n char v1;\n const unsigned short **v2;\n uint8_t *v3;\n long long v4;\n long long v5;\n const unsigned short *v6;\n int v7;\n uint8_t v9[1032];\n unsigned long long v10;\n v1 = *a1;\n v10 = __readfsqword(40u);\n if (v1) {\n v2 = __ctype_b_loc();\n v3 = a1 + 1;\n v4 = 0LL;\n v5 = 0LL;\n v6 = *v2;\n do {\n while ((v6[v1] & 2048) == 0) {\n ++v3;\n byte_4040[v5] = v1;\n v7 = v5 + 1;\n v1 = *(v3 - 1);\n if (!v1) goto LABEL_6;\n v6 = *v2;\n v5 = v7;\n }\n ++v3;\n v9[v4] = v1;\n v1 = *(v3 - 1);\n v4 = (int)v4 + 1;\n } while (v1);\n v7 = v5;\n } else {\n v4 = 0LL;\n v7 = 0;\n }\nLABEL_6:\n v9[v4] = 0;\n byte_4040[v7] = 0;\n return __strcat_chk(byte_4040, v9, 1024LL);\n}", + "ida_pseudo_norm": "long long func0(char *a1) {\n char v1;\n const unsigned short **v2;\n uint8_t *v3;\n long long v4;\n long long v5;\n const unsigned short *v6;\n int v7;\n uint8_t v9[1032];\n unsigned long long v10;\n v1 = *a1;\n v10 = __readfsqword(40u);\n if (v1) {\n v2 = __ctype_b_loc();\n v3 = a1 + 1;\n v4 = 0LL;\n v5 = 0LL;\n v6 = *v2;\n do {\n while ((v6[v1] & 2048) == 0) {\n ++v3;\n res_1[v5] = v1;\n v7 = v5 + 1;\n v1 = *(v3 - 1);\n if (!v1) goto LABEL_6;\n v6 = *v2;\n v5 = v7;\n }\n ++v3;\n v9[v4] = v1;\n v1 = *(v3 - 1);\n v4 = (int)v4 + 1;\n } while (v1);\n v7 = v5;\n } else {\n v4 = 0LL;\n v7 = 0;\n }\nLABEL_6:\n v9[v4] = 0;\n res_1[v7] = 0;\n return __strcat_chk(res_1, v9, 1024LL);\n}" + }, + { + "index": 620, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int a[], int n) {\n int dp[n];\n dp[n - 1] = 1;\n for (int i = n - 2; i >= 0; i--) {\n int mxm = 0;\n for (int j = i + 1; j < n; j++) {\n if (a[j] % a[i] == 0 || a[i] % a[j] == 0) {\n if (mxm < dp[j]) {\n mxm = dp[j];\n }\n }\n }\n dp[i] = 1 + mxm;\n }\n int max_val = dp[0];\n for (int i = 1; i < n; i++) {\n if (max_val < dp[i]) {\n max_val = dp[i];\n }\n }\n return max_val;\n}", + "test": "int main() {\n\n int array1[] = {1, 3, 6, 13, 17, 18};\n\n int array2[] = {10, 5, 3, 15, 20};\n\n int array3[] = {18, 1, 3, 6, 13, 17};\n\n\n\n assert(func0(array1, 6) == 4);\n\n assert(func0(array2, 5) == 3);\n\n assert(func0(array3, 6) == 4);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x48,%rsp\nmov %rdi,-0x48(%rbp)\nmov %esi,-0x4c(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmov %rsp,%rax\nmov %rax,%rsi\nmov -0x4c(%rbp),%eax\nmovslq %eax,%rdx\nsub $0x1,%rdx\nmov %rdx,-0x28(%rbp)\nmovslq %eax,%rdx\nmov %rdx,%r8\nmov $0x0,%r9d\nmovslq %eax,%rdx\nmov %rdx,%rcx\nmov $0x0,%ebx\ncltq\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%edi\nmov $0x0,%edx\ndiv %rdi\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rbx\nsub %rdx,%rbx\nmov %rbx,%rdx\ncmp %rdx,%rsp\nje 1208 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11f1 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 1232 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x20(%rbp)\nmov -0x4c(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x20(%rbp),%rax\nmovslq %edx,%rdx\nmovl $0x1,(%rax,%rdx,4)\nmov -0x4c(%rbp),%eax\nsub $0x2,%eax\nmov %eax,-0x30(%rbp)\njmpq 1331 \nmovl $0x0,-0x34(%rbp)\nmov -0x30(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x38(%rbp)\njmpq 130e \nmov -0x38(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov -0x30(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x48(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rdx),%ecx\ncltd\nidiv %ecx\nmov %edx,%eax\ntest %eax,%eax\nje 12e8 \nmov -0x30(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov -0x38(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x48(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rdx),%ecx\ncltd\nidiv %ecx\nmov %edx,%eax\ntest %eax,%eax\njne 130a \nmov -0x20(%rbp),%rax\nmov -0x38(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\ncmp %eax,-0x34(%rbp)\njge 130a \nmov -0x20(%rbp),%rax\nmov -0x38(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nmov %eax,-0x34(%rbp)\naddl $0x1,-0x38(%rbp)\nmov -0x38(%rbp),%eax\ncmp -0x4c(%rbp),%eax\njl 127c \nmov -0x34(%rbp),%eax\nlea 0x1(%rax),%ecx\nmov -0x20(%rbp),%rax\nmov -0x30(%rbp),%edx\nmovslq %edx,%rdx\nmov %ecx,(%rax,%rdx,4)\nsubl $0x1,-0x30(%rbp)\ncmpl $0x0,-0x30(%rbp)\njns 1267 \nmov -0x20(%rbp),%rax\nmov (%rax),%eax\nmov %eax,-0x3c(%rbp)\nmovl $0x1,-0x2c(%rbp)\njmp 1373 \nmov -0x20(%rbp),%rax\nmov -0x2c(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\ncmp %eax,-0x3c(%rbp)\njge 136f \nmov -0x20(%rbp),%rax\nmov -0x2c(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nmov %eax,-0x3c(%rbp)\naddl $0x1,-0x2c(%rbp)\nmov -0x2c(%rbp),%eax\ncmp -0x4c(%rbp),%eax\njl 134d \nmov -0x3c(%rbp),%eax\nmov %rsi,%rsp\nmov -0x18(%rbp),%rdi\nxor %fs:0x28,%rdi\nje 1395 \ncallq 1060 <__stack_chk_fail@plt>\nmov -0x8(%rbp),%rbx\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov eax, [rbp+var_3C]\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11D6:\ncmp rsp, rdx\njz short loc_11ED\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_11D6\nloc_11ED:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1217\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1217:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov eax, [rbp+var_3C]\nlea edx, [rax-1]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov dword ptr [rax+rdx*4], 1\nmov eax, [rbp+var_3C]\nsub eax, 2\nmov [rbp+var_2C], eax\njmp loc_131A\nloc_124C:\nmov [rbp+var_28], 0\nmov eax, [rbp+var_2C]\nadd eax, 1\nmov [rbp+var_24], eax\njmp loc_12F7\nloc_1261:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_2C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_38]\nadd rdx, rcx\nmov edi, [rdx]\ncdq\nidiv edi\nmov ecx, edx\nmov eax, ecx\ntest eax, eax\njz short loc_12D1\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_38]\nadd rdx, rcx\nmov edi, [rdx]\ncdq\nidiv edi\nmov ecx, edx\nmov eax, ecx\ntest eax, eax\njnz short loc_12F3\nloc_12D1:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ncmp [rbp+var_28], eax\njge short loc_12F3\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov [rbp+var_28], eax\nloc_12F3:\nadd [rbp+var_24], 1\nloc_12F7:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_3C]\njl loc_1261\nmov eax, [rbp+var_28]\nlea ecx, [rax+1]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_2C]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nsub [rbp+var_2C], 1\nloc_131A:\ncmp [rbp+var_2C], 0\njns loc_124C\nmov rax, [rbp+var_10]\nmov eax, [rax]\nmov [rbp+var_20], eax\nmov [rbp+var_1C], 1\njmp short loc_135C\nloc_1336:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ncmp [rbp+var_20], eax\njge short loc_1358\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov [rbp+var_20], eax\nloc_1358:\nadd [rbp+var_1C], 1\nloc_135C:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_3C]\njl short loc_1336\nmov eax, [rbp+var_20]\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_137E\ncall ___stack_chk_fail\nlocret_137E:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned __int64 v2; // rax\n void *v3; // rsp\n _BYTE v5[4]; // [rsp+8h] [rbp-40h] BYREF\n int v6; // [rsp+Ch] [rbp-3Ch]\n __int64 v7; // [rsp+10h] [rbp-38h]\n int i; // [rsp+1Ch] [rbp-2Ch]\n int v9; // [rsp+20h] [rbp-28h]\n int j; // [rsp+24h] [rbp-24h]\n unsigned int v11; // [rsp+28h] [rbp-20h]\n int k; // [rsp+2Ch] [rbp-1Ch]\n __int64 v13; // [rsp+30h] [rbp-18h]\n unsigned int *v14; // [rsp+38h] [rbp-10h]\n unsigned __int64 v15; // [rsp+40h] [rbp-8h]\n\n v7 = a1;\n v6 = a2;\n v15 = __readfsqword(0x28u);\n v13 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 0x10uLL);\n while ( v5 != &v5[-(v2 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = alloca(v2 & 0xFFF);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)&v5[(v2 & 0xFFF) - 8] = *(_QWORD *)&v5[(v2 & 0xFFF) - 8];\n v14 = (unsigned int *)v5;\n *(_DWORD *)&v5[4 * v6 - 4] = 1;\n for ( i = v6 - 2; i >= 0; --i )\n {\n v9 = 0;\n for ( j = i + 1; j < v6; ++j )\n {\n if ( (!(*(_DWORD *)(4LL * j + v7) % *(_DWORD *)(4LL * i + v7))\n || !(*(_DWORD *)(4LL * i + v7) % *(_DWORD *)(4LL * j + v7)))\n && v9 < (int)v14[j] )\n {\n v9 = v14[j];\n }\n }\n v14[i] = v9 + 1;\n }\n v11 = *v14;\n for ( k = 1; k < v6; ++k )\n {\n if ( (int)v11 < (int)v14[k] )\n v11 = v14[k];\n }\n return v11;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov eax, [rbp+var_3C]\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11D6:\ncmp rsp, rdx\njz short loc_11ED\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_11D6\nloc_11ED:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1217\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1217:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov eax, [rbp+var_3C]\nlea edx, [rax-1]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov dword ptr [rax+rdx*4], 1\nmov eax, [rbp+var_3C]\nsub eax, 2\nmov [rbp+var_2C], eax\njmp loc_131A\nloc_124C:\nmov [rbp+var_28], 0\nmov eax, [rbp+var_2C]\nadd eax, 1\nmov [rbp+var_24], eax\njmp loc_12F7\nloc_1261:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_2C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_38]\nadd rdx, rcx\nmov edi, [rdx]\ncdq\nidiv edi\nmov ecx, edx\nmov eax, ecx\ntest eax, eax\njz short loc_12D1\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_38]\nadd rdx, rcx\nmov edi, [rdx]\ncdq\nidiv edi\nmov ecx, edx\nmov eax, ecx\ntest eax, eax\njnz short loc_12F3\nloc_12D1:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ncmp [rbp+var_28], eax\njge short loc_12F3\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov [rbp+var_28], eax\nloc_12F3:\nadd [rbp+var_24], 1\nloc_12F7:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_3C]\njl loc_1261\nmov eax, [rbp+var_28]\nlea ecx, [rax+1]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_2C]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nsub [rbp+var_2C], 1\nloc_131A:\ncmp [rbp+var_2C], 0\njns loc_124C\nmov rax, [rbp+var_10]\nmov eax, [rax]\nmov [rbp+var_20], eax\nmov [rbp+var_1C], 1\njmp short loc_135C\nloc_1336:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ncmp [rbp+var_20], eax\njge short loc_1358\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov [rbp+var_20], eax\nloc_1358:\nadd [rbp+var_1C], 1\nloc_135C:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_3C]\njl short loc_1336\nmov eax, [rbp+var_20]\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_137E\ncall ___stack_chk_fail\nlocret_137E:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned __int64 v2; // rax\n void *v3; // rsp\n _BYTE v5[4]; // [rsp+8h] [rbp-40h] BYREF\n int v6; // [rsp+Ch] [rbp-3Ch]\n __int64 v7; // [rsp+10h] [rbp-38h]\n int i; // [rsp+1Ch] [rbp-2Ch]\n int v9; // [rsp+20h] [rbp-28h]\n int j; // [rsp+24h] [rbp-24h]\n unsigned int v11; // [rsp+28h] [rbp-20h]\n int k; // [rsp+2Ch] [rbp-1Ch]\n __int64 v13; // [rsp+30h] [rbp-18h]\n unsigned int *v14; // [rsp+38h] [rbp-10h]\n unsigned __int64 v15; // [rsp+40h] [rbp-8h]\n\n v7 = a1;\n v6 = a2;\n v15 = __readfsqword(0x28u);\n v13 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 0x10uLL);\n while ( v5 != &v5[-(v2 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = alloca(v2 & 0xFFF);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)&v5[(v2 & 0xFFF) - 8] = *(_QWORD *)&v5[(v2 & 0xFFF) - 8];\n v14 = (unsigned int *)v5;\n *(_DWORD *)&v5[4 * v6 - 4] = 1;\n for ( i = v6 - 2; i >= 0; --i )\n {\n v9 = 0;\n for ( j = i + 1; j < v6; ++j )\n {\n if ( (!(*(_DWORD *)(4LL * j + v7) % *(_DWORD *)(4LL * i + v7))\n || !(*(_DWORD *)(4LL * i + v7) % *(_DWORD *)(4LL * j + v7)))\n && v9 < (int)v14[j] )\n {\n v9 = v14[j];\n }\n }\n v14[i] = v9 + 1;\n }\n v11 = *v14;\n for ( k = 1; k < v6; ++k )\n {\n if ( (int)v11 < (int)v14[k] )\n v11 = v14[k];\n }\n return v11;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n unsigned long long v2;\n void *v3;\n uint8_t v5[4];\n int v6;\n long long v7;\n int i;\n int v9;\n int j;\n unsigned int v11;\n int k;\n long long v13;\n unsigned int *v14;\n unsigned long long v15;\n v7 = a1;\n v6 = a2;\n v15 = __readfsqword(40u);\n v13 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 16uLL);\n while (v5 != &v5[-(v2 & 18446744073709547520LL)])\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)&v5[(v2 & 4095) - 8] = *(uint64_t *)&v5[(v2 & 4095) - 8];\n v14 = (unsigned int *)v5;\n *(uint32_t *)&v5[4 * v6 - 4] = 1;\n for (i = v6 - 2; i >= 0; --i) {\n v9 = 0;\n for (j = i + 1; j < v6; ++j) {\n if ((!(*(uint32_t *)(4LL * j + v7) % *(uint32_t *)(4LL * i + v7)) ||\n !(*(uint32_t *)(4LL * i + v7) % *(uint32_t *)(4LL * j + v7))) &&\n v9 < (int)v14[j]) {\n v9 = v14[j];\n }\n }\n v14[i] = v9 + 1;\n }\n v11 = *v14;\n for (k = 1; k < v6; ++k) {\n if ((int)v11 < (int)v14[k]) v11 = v14[k];\n }\n return v11;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned long long v2;\n void *v3;\n uint8_t v5[4];\n int v6;\n long long v7;\n int i;\n int v9;\n int j;\n unsigned int v11;\n int k;\n long long v13;\n unsigned int *v14;\n unsigned long long v15;\n v7 = a1;\n v6 = a2;\n v15 = __readfsqword(40u);\n v13 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 16uLL);\n while (v5 != &v5[-(v2 & 18446744073709547520LL)])\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)&v5[(v2 & 4095) - 8] = *(uint64_t *)&v5[(v2 & 4095) - 8];\n v14 = (unsigned int *)v5;\n *(uint32_t *)&v5[4 * v6 - 4] = 1;\n for (i = v6 - 2; i >= 0; --i) {\n v9 = 0;\n for (j = i + 1; j < v6; ++j) {\n if ((!(*(uint32_t *)(4LL * j + v7) % *(uint32_t *)(4LL * i + v7)) ||\n !(*(uint32_t *)(4LL * i + v7) % *(uint32_t *)(4LL * j + v7))) &&\n v9 < (int)v14[j]) {\n v9 = v14[j];\n }\n }\n v14[i] = v9 + 1;\n }\n v11 = *v14;\n for (k = 1; k < v6; ++k) {\n if ((int)v11 < (int)v14[k]) v11 = v14[k];\n }\n return v11;\n}" + }, + { + "index": 620, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int a[], int n) {\n int dp[n];\n dp[n - 1] = 1;\n for (int i = n - 2; i >= 0; i--) {\n int mxm = 0;\n for (int j = i + 1; j < n; j++) {\n if (a[j] % a[i] == 0 || a[i] % a[j] == 0) {\n if (mxm < dp[j]) {\n mxm = dp[j];\n }\n }\n }\n dp[i] = 1 + mxm;\n }\n int max_val = dp[0];\n for (int i = 1; i < n; i++) {\n if (max_val < dp[i]) {\n max_val = dp[i];\n }\n }\n return max_val;\n}", + "test": "int main() {\n\n int array1[] = {1, 3, 6, 13, 17, 18};\n\n int array2[] = {10, 5, 3, 15, 20};\n\n int array3[] = {18, 1, 3, 6, 13, 17};\n\n\n\n assert(func0(array1, 6) == 4);\n\n assert(func0(array2, 5) == 3);\n\n assert(func0(array3, 6) == 4);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x28(%rbp)\nxor %eax,%eax\nmovslq %esi,%rax\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffffff0,%rdx\nand $0xfffffffffffff000,%rax\nmov %rsp,%rbx\nsub %rax,%rbx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 11c3 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11ac \nmov %rdx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 11d9 \norq $0x0,-0x8(%rsp,%rax,1)\nlea 0x3(%rsp),%r13\nmov %r13,%r14\nshr $0x2,%r14\nand $0xfffffffffffffffc,%r13\nmov %r13,%r11\nlea -0x1(%rsi),%r12d\nmovslq %r12d,%rax\nmovl $0x1,0x0(%r13,%rax,4)\nmov %esi,%ebx\nsub $0x2,%ebx\njs 1265 \nmovslq %ebx,%rbx\njmp 1251 \nmov (%r11,%rcx,4),%eax\ncmp %eax,%r10d\ncmovl %eax,%r10d\nadd $0x1,%rcx\ncmp %ecx,%esi\njle 123d \nmov (%rdi,%rcx,4),%r8d\nmov %r8d,%eax\ncltd\nidiv %r9d\ntest %edx,%edx\nje 1208 \nmov %r9d,%eax\ncltd\nidiv %r8d\ntest %edx,%edx\njne 1213 \njmp 1208 \nmov $0x0,%r10d\nadd $0x1,%r10d\nmov %r10d,(%r11,%rbx,4)\nsub $0x1,%rbx\nsub $0x1,%r12d\ntest %ebx,%ebx\njs 1265 \ncmp %r12d,%esi\njle 1237 \nmov (%rdi,%rbx,4),%r9d\nmovslq %r12d,%rcx\nmov $0x0,%r10d\njmp 121b \nmov 0x0(,%r14,4),%edx\ncmp $0x1,%esi\njle 128e \nlea 0x4(%r13),%rax\nlea -0x2(%rsi),%ecx\nlea 0x8(%r13,%rcx,4),%rsi\nmov (%rax),%ecx\ncmp %ecx,%edx\ncmovl %ecx,%edx\nadd $0x4,%rax\ncmp %rsi,%rax\njne 127e \nmov -0x28(%rbp),%rax\nxor %fs:0x28,%rax\njne 12ac \nmov %edx,%eax\nlea -0x20(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %rbp\nretq\ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r13\npush r12\npush rbx\nsub rsp, 18h\nmov r10, rdi\nmov r9d, esi\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nmovsxd rax, esi\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11AD:\ncmp rsp, rdx\njz short loc_11C4\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\njmp short loc_11AD\nloc_11C4:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11DA\nor [rsp+rax+30h+var_38], 0\nloc_11DA:\nlea r11, [rsp+30h+var_2D]\nmov r13, r11\nshr r13, 2\nand r11, 0FFFFFFFFFFFFFFFCh\nlea r12d, [r9-1]\nmovsxd rax, r12d\nmov dword ptr [r11+rax*4], 1\nmov ebx, r9d\nsub ebx, 2\njs loc_12A5\nmovsxd rbx, ebx\njmp short loc_1250\nloc_120A:\nmov eax, [r11+rcx*4]\ncmp r8d, eax\ncmovl r8d, eax\nloc_1215:\nadd rcx, 1\ncmp r9d, ecx\njle short loc_123C\nloc_121E:\nmov esi, [r10+rcx*4]\nmov eax, esi\ncdq\nidiv edi\ntest edx, edx\njz short loc_120A\nmov eax, edi\ncdq\nidiv esi\ntest edx, edx\njnz short loc_1215\njmp short loc_120A\nloc_1236:\nmov r8d, 0\nloc_123C:\nadd r8d, 1\nmov [r11+rbx*4], r8d\nsub rbx, 1\nsub r12d, 1\ntest ebx, ebx\njs short loc_1264\nloc_1250:\ncmp r9d, r12d\njle short loc_1236\nmov edi, [r10+rbx*4]\nmovsxd rcx, r12d\nmov r8d, 0\njmp short loc_121E\nloc_1264:\nmov edx, ds:dword_0[r13*4]\nlea rax, [r11+4]\nlea ecx, [r9-2]\nlea rsi, [r11+rcx*4+8]\nloc_1279:\nmov ecx, [rax]\ncmp edx, ecx\ncmovl edx, ecx\nadd rax, 4\ncmp rax, rsi\njnz short loc_1279\nloc_1289:\nmov rax, [rbp+var_28]\nsub rax, fs:28h\njnz short loc_12AF\nmov eax, edx\nlea rsp, [rbp-18h]\npop rbx\npop r12\npop r13\npop rbp\nretn\nloc_12A5:\nmov edx, ds:dword_0[r13*4]\njmp short loc_1289\nloc_12AF:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n signed __int64 v3; // rax\n void *v4; // rsp\n int v5; // r12d\n __int64 v6; // rbx\n int v7; // r8d\n __int64 v8; // rcx\n int v9; // edi\n unsigned int v10; // edx\n int *v11; // rax\n __int64 v13; // [rsp+0h] [rbp-38h]\n unsigned int v14; // [rsp+8h] [rbp-30h] BYREF\n int v15; // [rsp+Ch] [rbp-2Ch] BYREF\n _QWORD v16[5]; // [rsp+10h] [rbp-28h] BYREF\n\n v16[0] = __readfsqword(0x28u);\n while ( &v14 != (unsigned int *)((char *)&v14 - ((4LL * a2 + 15) & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v3 = (4 * (_WORD)a2 + 15) & 0xFF0;\n v4 = alloca(v3);\n if ( ((4 * (_WORD)a2 + 15) & 0xFF0) != 0 )\n *(__int64 *)((char *)&v13 + v3) = *(__int64 *)((char *)&v13 + v3);\n v5 = a2 - 1;\n *(&v14 + a2 - 1) = 1;\n LODWORD(v6) = a2 - 2;\n if ( a2 - 2 < 0 )\n {\n return v14;\n }\n else\n {\n v6 = (int)v6;\n do\n {\n if ( a2 <= v5 )\n {\n v7 = 0;\n }\n else\n {\n v9 = *(_DWORD *)(a1 + 4 * v6);\n v8 = v5;\n v7 = 0;\n do\n {\n if ( (!(*(_DWORD *)(a1 + 4 * v8) % v9) || !(v9 % *(_DWORD *)(a1 + 4 * v8))) && v7 < (int)*(&v14 + v8) )\n v7 = *(&v14 + v8);\n ++v8;\n }\n while ( a2 > (int)v8 );\n }\n *(&v14 + v6--) = v7 + 1;\n --v5;\n }\n while ( (int)v6 >= 0 );\n v10 = v14;\n v11 = &v15;\n do\n {\n if ( (int)v10 < *v11 )\n v10 = *v11;\n ++v11;\n }\n while ( v11 != (int *)((char *)v16 + 4 * (unsigned int)(a2 - 2)) );\n }\n return v10;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\npush r13\npush r12\npush rbx\nsub rsp, 18h\nmov r10, rdi\nmov r9d, esi\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nmovsxd rax, esi\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11AD:\ncmp rsp, rdx\njz short loc_11C4\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\njmp short loc_11AD\nloc_11C4:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11DA\nor [rsp+rax+30h+var_38], 0\nloc_11DA:\nlea r11, [rsp+30h+var_2D]\nmov r13, r11\nshr r13, 2\nand r11, 0FFFFFFFFFFFFFFFCh\nlea r12d, [r9-1]\nmovsxd rax, r12d\nmov dword ptr [r11+rax*4], 1\nmov ebx, r9d\nsub ebx, 2\njs loc_12A5\nmovsxd rbx, ebx\njmp short loc_1250\nloc_120A:\nmov eax, [r11+rcx*4]\ncmp r8d, eax\ncmovl r8d, eax\nloc_1215:\nadd rcx, 1\ncmp r9d, ecx\njle short loc_123C\nloc_121E:\nmov esi, [r10+rcx*4]\nmov eax, esi\ncdq\nidiv edi\ntest edx, edx\njz short loc_120A\nmov eax, edi\ncdq\nidiv esi\ntest edx, edx\njnz short loc_1215\njmp short loc_120A\nloc_1236:\nmov r8d, 0\nloc_123C:\nadd r8d, 1\nmov [r11+rbx*4], r8d\nsub rbx, 1\nsub r12d, 1\ntest ebx, ebx\njs short loc_1264\nloc_1250:\ncmp r9d, r12d\njle short loc_1236\nmov edi, [r10+rbx*4]\nmovsxd rcx, r12d\nmov r8d, 0\njmp short loc_121E\nloc_1264:\nmov edx, ds:dword_0[r13*4]\nlea rax, [r11+4]\nlea ecx, [r9-2]\nlea rsi, [r11+rcx*4+8]\nloc_1279:\nmov ecx, [rax]\ncmp edx, ecx\ncmovl edx, ecx\nadd rax, 4\ncmp rax, rsi\njnz short loc_1279\nloc_1289:\nmov rax, [rbp+var_28]\nsub rax, fs:28h\njnz short loc_12AF\nmov eax, edx\nlea rsp, [rbp-18h]\npop rbx\npop r12\npop r13\npop rbp\nretn\nloc_12A5:\nmov edx, ds:dword_0[r13*4]\njmp short loc_1289\nloc_12AF:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n signed __int64 v3; // rax\n void *v4; // rsp\n int v5; // r12d\n __int64 v6; // rbx\n int v7; // r8d\n __int64 v8; // rcx\n int v9; // edi\n unsigned int v10; // edx\n int *v11; // rax\n __int64 v13; // [rsp+0h] [rbp-38h]\n unsigned int v14; // [rsp+8h] [rbp-30h] BYREF\n int v15; // [rsp+Ch] [rbp-2Ch] BYREF\n _QWORD v16[5]; // [rsp+10h] [rbp-28h] BYREF\n\n v16[0] = __readfsqword(0x28u);\n while ( &v14 != (unsigned int *)((char *)&v14 - ((4LL * a2 + 15) & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v3 = (4 * (_WORD)a2 + 15) & 0xFF0;\n v4 = alloca(v3);\n if ( ((4 * (_WORD)a2 + 15) & 0xFF0) != 0 )\n *(__int64 *)((char *)&v13 + v3) = *(__int64 *)((char *)&v13 + v3);\n v5 = a2 - 1;\n *(&v14 + a2 - 1) = 1;\n LODWORD(v6) = a2 - 2;\n if ( a2 - 2 < 0 )\n {\n return v14;\n }\n else\n {\n v6 = (int)v6;\n do\n {\n if ( a2 <= v5 )\n {\n v7 = 0;\n }\n else\n {\n v9 = *(_DWORD *)(a1 + 4 * v6);\n v8 = v5;\n v7 = 0;\n do\n {\n if ( (!(*(_DWORD *)(a1 + 4 * v8) % v9) || !(v9 % *(_DWORD *)(a1 + 4 * v8))) && v7 < (int)*(&v14 + v8) )\n v7 = *(&v14 + v8);\n ++v8;\n }\n while ( a2 > (int)v8 );\n }\n *(&v14 + v6--) = v7 + 1;\n --v5;\n }\n while ( (int)v6 >= 0 );\n v10 = v14;\n v11 = &v15;\n do\n {\n if ( (int)v10 < *v11 )\n v10 = *v11;\n ++v11;\n }\n while ( v11 != (int *)((char *)v16 + 4 * (unsigned int)(a2 - 2)) );\n }\n return v10;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n signed long long v3;\n void *v4;\n int v5;\n long long v6;\n int v7;\n long long v8;\n int v9;\n unsigned int v10;\n int *v11;\n long long v13;\n unsigned int v14;\n int v15;\n uint64_t v16[5];\n v16[0] = __readfsqword(40u);\n while (&v14 != (unsigned int *)((char *)&v14 -\n ((4LL * a2 + 15) & 18446744073709547520LL)))\n ;\n v3 = (4 * (unsigned short)a2 + 15) & 4080;\n v4 = alloca(v3);\n if (((4 * (unsigned short)a2 + 15) & 4080) != 0)\n *(long long *)((char *)&v13 + v3) = *(long long *)((char *)&v13 + v3);\n v5 = a2 - 1;\n *(&v14 + a2 - 1) = 1;\n LODWORD(v6) = a2 - 2;\n if (a2 - 2 < 0) {\n return v14;\n } else {\n v6 = (int)v6;\n do {\n if (a2 <= v5) {\n v7 = 0;\n } else {\n v9 = *(uint32_t *)(a1 + 4 * v6);\n v8 = v5;\n v7 = 0;\n do {\n if ((!(*(uint32_t *)(a1 + 4 * v8) % v9) ||\n !(v9 % *(uint32_t *)(a1 + 4 * v8))) &&\n v7 < (int)*(&v14 + v8))\n v7 = *(&v14 + v8);\n ++v8;\n } while (a2 > (int)v8);\n }\n *(&v14 + v6--) = v7 + 1;\n --v5;\n } while ((int)v6 >= 0);\n v10 = v14;\n v11 = &v15;\n do {\n if ((int)v10 < *v11) v10 = *v11;\n ++v11;\n } while (v11 != (int *)((char *)v16 + 4 * (unsigned int)(a2 - 2)));\n }\n return v10;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n signed long long v3;\n void *v4;\n int v5;\n long long v6;\n int v7;\n long long v8;\n int v9;\n unsigned int v10;\n int *v11;\n long long v13;\n unsigned int v14;\n int v15;\n uint64_t v16[5];\n v16[0] = __readfsqword(40u);\n while (&v14 != (unsigned int *)((char *)&v14 -\n ((4LL * a2 + 15) & 18446744073709547520LL)))\n ;\n v3 = (4 * (unsigned short)a2 + 15) & 4080;\n v4 = alloca(v3);\n if (((4 * (unsigned short)a2 + 15) & 4080) != 0)\n *(long long *)((char *)&v13 + v3) = *(long long *)((char *)&v13 + v3);\n v5 = a2 - 1;\n *(&v14 + a2 - 1) = 1;\n LODWORD(v6) = a2 - 2;\n if (a2 - 2 < 0) {\n return v14;\n } else {\n v6 = (int)v6;\n do {\n if (a2 <= v5) {\n v7 = 0;\n } else {\n v9 = *(uint32_t *)(a1 + 4 * v6);\n v8 = v5;\n v7 = 0;\n do {\n if ((!(*(uint32_t *)(a1 + 4 * v8) % v9) ||\n !(v9 % *(uint32_t *)(a1 + 4 * v8))) &&\n v7 < (int)*(&v14 + v8))\n v7 = *(&v14 + v8);\n ++v8;\n } while (a2 > (int)v8);\n }\n *(&v14 + v6--) = v7 + 1;\n --v5;\n } while ((int)v6 >= 0);\n v10 = v14;\n v11 = &v15;\n do {\n if ((int)v10 < *v11) v10 = *v11;\n ++v11;\n } while (v11 != (int *)((char *)v16 + 4 * (unsigned int)(a2 - 2)));\n }\n return v10;\n}" + }, + { + "index": 620, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int a[], int n) {\n int dp[n];\n dp[n - 1] = 1;\n for (int i = n - 2; i >= 0; i--) {\n int mxm = 0;\n for (int j = i + 1; j < n; j++) {\n if (a[j] % a[i] == 0 || a[i] % a[j] == 0) {\n if (mxm < dp[j]) {\n mxm = dp[j];\n }\n }\n }\n dp[i] = 1 + mxm;\n }\n int max_val = dp[0];\n for (int i = 1; i < n; i++) {\n if (max_val < dp[i]) {\n max_val = dp[i];\n }\n }\n return max_val;\n}", + "test": "int main() {\n\n int array1[] = {1, 3, 6, 13, 17, 18};\n\n int array2[] = {10, 5, 3, 15, 20};\n\n int array3[] = {18, 1, 3, 6, 13, 17};\n\n\n\n assert(func0(array1, 6) == 4);\n\n assert(func0(array2, 5) == 3);\n\n assert(func0(array3, 6) == 4);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x28(%rbp)\nxor %eax,%eax\nmovslq %esi,%rax\nmov %rsp,%rbx\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rbx\nand $0xfffffffffffffff0,%rdx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 131d \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 1308 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 1418 \nlea 0x3(%rsp),%r11\nlea -0x1(%rsi),%r12d\nmov %r11,%r14\nmovslq %r12d,%rax\nlea -0x2(%rsi),%r13d\nand $0xfffffffffffffffc,%r11\nmovl $0x1,(%r11,%rax,4)\nshr $0x2,%r14\nmovslq %r13d,%rbx\ntest %r13d,%r13d\njs 13b9 \nnopw 0x0(%rax,%rax,1)\ncmp %r12d,%esi\njle 1410 \nmov (%rdi,%rbx,4),%r9d\nmovslq %r12d,%rcx\nxor %r10d,%r10d\nnopl 0x0(%rax,%rax,1)\nmov (%rdi,%rcx,4),%r8d\nmov %r8d,%eax\ncltd\nidiv %r9d\ntest %edx,%edx\nje 1392 \nmov %r9d,%eax\ncltd\nidiv %r8d\ntest %edx,%edx\njne 139d \nmov (%r11,%rcx,4),%eax\ncmp %eax,%r10d\ncmovl %eax,%r10d\nadd $0x1,%rcx\ncmp %ecx,%esi\njg 1378 \nadd $0x1,%r10d\nmov %r10d,(%r11,%rbx,4)\nsub $0x1,%rbx\nsub $0x1,%r12d\ntest %ebx,%ebx\njns 1360 \nmov 0x0(,%r14,4),%r8d\ncmp $0x1,%esi\njle 13ea \nmov %r13d,%r13d\nlea 0x4(%r11),%rax\nlea 0x8(%r11,%r13,4),%rcx\nnopw 0x0(%rax,%rax,1)\nmov (%rax),%edx\ncmp %edx,%r8d\ncmovl %edx,%r8d\nadd $0x4,%rax\ncmp %rax,%rcx\njne 13d8 \nmov -0x28(%rbp),%rax\nxor %fs:0x28,%rax\njne 1423 \nlea -0x20(%rbp),%rsp\nmov %r8d,%eax\npop %rbx\npop %r12\npop %r13\npop %r14\npop %rbp\nretq\nnopl 0x0(%rax)\nmov $0x1,%r10d\njmp 13a9 \norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 132f \ncallq 1060 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov r10, rdi\nmov r9d, esi\nmov rbp, rsp\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nmovsxd rax, esi\nmov rcx, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_12F0\nloc_12DB:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rcx\njnz short loc_12DB\nloc_12F0:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1403\nloc_1302:\nlea r11, [rsp+1030h+var_102D]\nlea r12d, [r9-1]\nmov r13d, r9d\nmov r14, r11\nmovsxd rax, r12d\nand r11, 0FFFFFFFFFFFFFFFCh\nmov dword ptr [r11+rax*4], 1\nshr r14, 2\nsub r13d, 2\njs loc_140E\nmovsxd rbx, r13d\nnop dword ptr [rax+00000000h]\nloc_1338:\ncmp r9d, r12d\njle loc_13F8\nmov edi, [r10+rbx*4]\nmov ecx, r12d\nxor r8d, r8d\nnop dword ptr [rax+rax+00h]\nloc_1350:\nmov esi, [r10+rcx*4]\nmov eax, esi\ncdq\nidiv edi\ntest edx, edx\njz short loc_1366\nmov eax, edi\ncdq\nidiv esi\ntest edx, edx\njnz short loc_1371\nloc_1366:\nmov eax, [r11+rcx*4]\ncmp r8d, eax\ncmovl r8d, eax\nloc_1371:\nadd rcx, 1\ncmp r9d, ecx\njg short loc_1350\nadd r8d, 1\nloc_137E:\nmov [r11+rbx*4], r8d\nsub rbx, 1\nsub r12d, 1\ntest ebx, ebx\njns short loc_1338\nmov r13d, r13d\nlea rdx, [r11+4]\nmov eax, ds:dword_0[r14*4]\nlea rsi, [r11+r13*4+8]\nmov rcx, rsi\nsub rcx, rdx\nand ecx, 4\njz short loc_13C0\nmov edx, [rdx]\ncmp eax, edx\ncmovl eax, edx\nlea rdx, [r11+8]\ncmp rdx, rsi\njz short loc_13D8\nnop dword ptr [rax]\nloc_13C0:\nmov ecx, [rdx]\ncmp eax, ecx\ncmovl eax, ecx\nmov ecx, [rdx+4]\ncmp eax, ecx\ncmovl eax, ecx\nadd rdx, 8\ncmp rdx, rsi\njnz short loc_13C0\nloc_13D8:\nmov rdx, [rbp+var_28]\nsub rdx, fs:28h\njnz short loc_1418\nlea rsp, [rbp-20h]\npop rbx\npop r12\npop r13\npop r14\npop rbp\nretn\nloc_13F8:\nmov r8d, 1\njmp loc_137E\nloc_1403:\nor [rsp+rdx+1030h+var_1038], 0\njmp loc_1302\nloc_140E:\nmov eax, ds:dword_0[r14*4]\njmp short loc_13D8\nloc_1418:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v3; // rdx\n unsigned int *v4; // rcx\n __int16 v5; // dx\n signed __int64 v6; // rdx\n void *v7; // rsp\n int v8; // r12d\n int v9; // r13d\n __int64 v10; // rbx\n int v11; // edi\n __int64 v12; // rcx\n int v13; // r8d\n int v14; // r8d\n int *v15; // rdx\n __int64 result; // rax\n int *v17; // rsi\n int v18; // ecx\n __int64 v19; // [rsp+0h] [rbp-1038h]\n unsigned int v20; // [rsp+8h] [rbp-1030h] BYREF\n unsigned int v21; // [rsp+Ch] [rbp-102Ch] BYREF\n _DWORD v22[1020]; // [rsp+10h] [rbp-1028h] BYREF\n _QWORD v23[6]; // [rsp+1008h] [rbp-30h] BYREF\n\n v23[1] = __readfsqword(0x28u);\n v3 = 4LL * a2 + 15;\n v4 = (unsigned int *)((char *)v23 - (v3 & 0xFFFFFFFFFFFFF000LL));\n v5 = v3 & 0xFFF0;\n if ( v23 != (_QWORD *)v4 )\n {\n while ( &v20 != v4 )\n ;\n }\n v6 = v5 & 0xFFF;\n v7 = alloca(v6);\n if ( v6 )\n *(__int64 *)((char *)&v19 + v6) = *(__int64 *)((char *)&v19 + v6);\n v8 = a2 - 1;\n *(&v20 + a2 - 1) = 1;\n v9 = a2 - 2;\n if ( a2 - 2 < 0 )\n return v20;\n v10 = v9;\n do\n {\n if ( a2 <= v8 )\n {\n v14 = 1;\n }\n else\n {\n v11 = *(_DWORD *)(a1 + 4 * v10);\n v12 = (unsigned int)v8;\n v13 = 0;\n do\n {\n if ( (!(*(_DWORD *)(a1 + 4 * v12) % v11) || !(v11 % *(_DWORD *)(a1 + 4 * v12))) && v13 < (int)*(&v20 + v12) )\n v13 = *(&v20 + v12);\n ++v12;\n }\n while ( a2 > (int)v12 );\n v14 = v13 + 1;\n }\n *(&v20 + v10--) = v14;\n --v8;\n }\n while ( (int)v10 >= 0 );\n v15 = (int *)&v21;\n result = v20;\n v17 = &v22[v9];\n if ( ((4 * (_BYTE)v9 + 4) & 4) == 0 )\n goto LABEL_30;\n if ( (int)v20 < (int)v21 )\n result = v21;\n v15 = v22;\n if ( v22 != v17 )\n {\nLABEL_30:\n do\n {\n if ( (int)result < *v15 )\n result = (unsigned int)*v15;\n v18 = v15[1];\n if ( (int)result < v18 )\n result = (unsigned int)v18;\n v15 += 2;\n }\n while ( v15 != v17 );\n }\n return result;\n}", + "ida_strip_asm": "sub_1290:\nendbr64\npush rbp\nmov r10, rdi\nmov r9d, esi\nmov rbp, rsp\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nmovsxd rax, esi\nmov rcx, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_12F0\nloc_12DB:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rcx\njnz short loc_12DB\nloc_12F0:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1403\nloc_1302:\nlea r11, [rsp+1030h+var_102D]\nlea r12d, [r9-1]\nmov r13d, r9d\nmov r14, r11\nmovsxd rax, r12d\nand r11, 0FFFFFFFFFFFFFFFCh\nmov dword ptr [r11+rax*4], 1\nshr r14, 2\nsub r13d, 2\njs loc_140E\nmovsxd rbx, r13d\nnop dword ptr [rax+00000000h]\nloc_1338:\ncmp r9d, r12d\njle loc_13F8\nmov edi, [r10+rbx*4]\nmov ecx, r12d\nxor r8d, r8d\nnop dword ptr [rax+rax+00h]\nloc_1350:\nmov esi, [r10+rcx*4]\nmov eax, esi\ncdq\nidiv edi\ntest edx, edx\njz short loc_1366\nmov eax, edi\ncdq\nidiv esi\ntest edx, edx\njnz short loc_1371\nloc_1366:\nmov eax, [r11+rcx*4]\ncmp r8d, eax\ncmovl r8d, eax\nloc_1371:\nadd rcx, 1\ncmp r9d, ecx\njg short loc_1350\nadd r8d, 1\nloc_137E:\nmov [r11+rbx*4], r8d\nsub rbx, 1\nsub r12d, 1\ntest ebx, ebx\njns short loc_1338\nmov r13d, r13d\nlea rdx, [r11+4]\nmov eax, ds:dword_0[r14*4]\nlea rsi, [r11+r13*4+8]\nmov rcx, rsi\nsub rcx, rdx\nand ecx, 4\njz short loc_13C0\nmov edx, [rdx]\ncmp eax, edx\ncmovl eax, edx\nlea rdx, [r11+8]\ncmp rdx, rsi\njz short loc_13D8\nnop dword ptr [rax]\nloc_13C0:\nmov ecx, [rdx]\ncmp eax, ecx\ncmovl eax, ecx\nmov ecx, [rdx+4]\ncmp eax, ecx\ncmovl eax, ecx\nadd rdx, 8\ncmp rdx, rsi\njnz short loc_13C0\nloc_13D8:\nmov rdx, [rbp+var_28]\nsub rdx, fs:28h\njnz short loc_1418\nlea rsp, [rbp-20h]\npop rbx\npop r12\npop r13\npop r14\npop rbp\nretn\nloc_13F8:\nmov r8d, 1\njmp loc_137E\nloc_1403:\nor [rsp+rdx+1030h+var_1038], 0\njmp loc_1302\nloc_140E:\nmov eax, ds:dword_0[r14*4]\njmp short loc_13D8\nloc_1418:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1290(__int64 a1, int a2)\n{\n __int64 v3; // rdx\n unsigned int *v4; // rcx\n __int16 v5; // dx\n signed __int64 v6; // rdx\n void *v7; // rsp\n int v8; // r12d\n int v9; // r13d\n __int64 v10; // rbx\n int v11; // edi\n __int64 v12; // rcx\n int v13; // r8d\n int v14; // r8d\n int *v15; // rdx\n __int64 result; // rax\n int *v17; // rsi\n int v18; // ecx\n __int64 v19; // [rsp+0h] [rbp-1038h]\n unsigned int v20; // [rsp+8h] [rbp-1030h] BYREF\n unsigned int v21; // [rsp+Ch] [rbp-102Ch] BYREF\n _DWORD v22[1020]; // [rsp+10h] [rbp-1028h] BYREF\n _QWORD v23[6]; // [rsp+1008h] [rbp-30h] BYREF\n\n v23[1] = __readfsqword(0x28u);\n v3 = 4LL * a2 + 15;\n v4 = (unsigned int *)((char *)v23 - (v3 & 0xFFFFFFFFFFFFF000LL));\n v5 = v3 & 0xFFF0;\n if ( v23 != (_QWORD *)v4 )\n {\n while ( &v20 != v4 )\n ;\n }\n v6 = v5 & 0xFFF;\n v7 = alloca(v6);\n if ( v6 )\n *(__int64 *)((char *)&v19 + v6) = *(__int64 *)((char *)&v19 + v6);\n v8 = a2 - 1;\n *(&v20 + a2 - 1) = 1;\n v9 = a2 - 2;\n if ( a2 - 2 < 0 )\n return v20;\n v10 = v9;\n do\n {\n if ( a2 <= v8 )\n {\n v14 = 1;\n }\n else\n {\n v11 = *(_DWORD *)(a1 + 4 * v10);\n v12 = (unsigned int)v8;\n v13 = 0;\n do\n {\n if ( (!(*(_DWORD *)(a1 + 4 * v12) % v11) || !(v11 % *(_DWORD *)(a1 + 4 * v12))) && v13 < (int)*(&v20 + v12) )\n v13 = *(&v20 + v12);\n ++v12;\n }\n while ( a2 > (int)v12 );\n v14 = v13 + 1;\n }\n *(&v20 + v10--) = v14;\n --v8;\n }\n while ( (int)v10 >= 0 );\n v15 = (int *)&v21;\n result = v20;\n v17 = &v22[v9];\n if ( ((4 * (_BYTE)v9 + 4) & 4) == 0 )\n goto LABEL_30;\n if ( (int)v20 < (int)v21 )\n result = v21;\n v15 = v22;\n if ( v22 != v17 )\n {\nLABEL_30:\n do\n {\n if ( (int)result < *v15 )\n result = (unsigned int)*v15;\n v18 = v15[1];\n if ( (int)result < v18 )\n result = (unsigned int)v18;\n v15 += 2;\n }\n while ( v15 != v17 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1290(long long a1, int a2) {\n long long v3;\n unsigned int *v4;\n short v5;\n signed long long v6;\n void *v7;\n int v8;\n int v9;\n long long v10;\n int v11;\n long long v12;\n int v13;\n int v14;\n int *v15;\n long long result;\n int *v17;\n int v18;\n long long v19;\n unsigned int v20;\n unsigned int v21;\n uint32_t v22[1020];\n uint64_t v23[6];\n v23[1] = __readfsqword(40u);\n v3 = 4LL * a2 + 15;\n v4 = (unsigned int *)((char *)v23 - (v3 & 18446744073709547520LL));\n v5 = v3 & 65520;\n if (v23 != (uint64_t *)v4) {\n while (&v20 != v4)\n ;\n }\n v6 = v5 & 4095;\n v7 = alloca(v6);\n if (v6) *(long long *)((char *)&v19 + v6) = *(long long *)((char *)&v19 + v6);\n v8 = a2 - 1;\n *(&v20 + a2 - 1) = 1;\n v9 = a2 - 2;\n if (a2 - 2 < 0) return v20;\n v10 = v9;\n do {\n if (a2 <= v8) {\n v14 = 1;\n } else {\n v11 = *(uint32_t *)(a1 + 4 * v10);\n v12 = (unsigned int)v8;\n v13 = 0;\n do {\n if ((!(*(uint32_t *)(a1 + 4 * v12) % v11) ||\n !(v11 % *(uint32_t *)(a1 + 4 * v12))) &&\n v13 < (int)*(&v20 + v12))\n v13 = *(&v20 + v12);\n ++v12;\n } while (a2 > (int)v12);\n v14 = v13 + 1;\n }\n *(&v20 + v10--) = v14;\n --v8;\n } while ((int)v10 >= 0);\n v15 = (int *)&v21;\n result = v20;\n v17 = &v22[v9];\n if (((4 * (uint8_t)v9 + 4) & 4) == 0) goto LABEL_30;\n if ((int)v20 < (int)v21) result = v21;\n v15 = v22;\n if (v22 != v17) {\n LABEL_30:\n do {\n if ((int)result < *v15) result = (unsigned int)*v15;\n v18 = v15[1];\n if ((int)result < v18) result = (unsigned int)v18;\n v15 += 2;\n } while (v15 != v17);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v3;\n unsigned int *v4;\n short v5;\n signed long long v6;\n void *v7;\n int v8;\n int v9;\n long long v10;\n int v11;\n long long v12;\n int v13;\n int v14;\n int *v15;\n long long result;\n int *v17;\n int v18;\n long long v19;\n unsigned int v20;\n unsigned int v21;\n uint32_t v22[1020];\n uint64_t v23[6];\n v23[1] = __readfsqword(40u);\n v3 = 4LL * a2 + 15;\n v4 = (unsigned int *)((char *)v23 - (v3 & 18446744073709547520LL));\n v5 = v3 & 65520;\n if (v23 != (uint64_t *)v4) {\n while (&v20 != v4)\n ;\n }\n v6 = v5 & 4095;\n v7 = alloca(v6);\n if (v6) *(long long *)((char *)&v19 + v6) = *(long long *)((char *)&v19 + v6);\n v8 = a2 - 1;\n *(&v20 + a2 - 1) = 1;\n v9 = a2 - 2;\n if (a2 - 2 < 0) return v20;\n v10 = v9;\n do {\n if (a2 <= v8) {\n v14 = 1;\n } else {\n v11 = *(uint32_t *)(a1 + 4 * v10);\n v12 = (unsigned int)v8;\n v13 = 0;\n do {\n if ((!(*(uint32_t *)(a1 + 4 * v12) % v11) ||\n !(v11 % *(uint32_t *)(a1 + 4 * v12))) &&\n v13 < (int)*(&v20 + v12))\n v13 = *(&v20 + v12);\n ++v12;\n } while (a2 > (int)v12);\n v14 = v13 + 1;\n }\n *(&v20 + v10--) = v14;\n --v8;\n } while ((int)v10 >= 0);\n v15 = (int *)&v21;\n result = v20;\n v17 = &v22[v9];\n if (((4 * (uint8_t)v9 + 4) & 4) == 0) goto LABEL_30;\n if ((int)v20 < (int)v21) result = v21;\n v15 = v22;\n if (v22 != v17) {\n LABEL_30:\n do {\n if ((int)result < *v15) result = (unsigned int)*v15;\n v18 = v15[1];\n if ((int)result < v18) result = (unsigned int)v18;\n v15 += 2;\n } while (v15 != v17);\n }\n return result;\n}" + }, + { + "index": 620, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int a[], int n) {\n int dp[n];\n dp[n - 1] = 1;\n for (int i = n - 2; i >= 0; i--) {\n int mxm = 0;\n for (int j = i + 1; j < n; j++) {\n if (a[j] % a[i] == 0 || a[i] % a[j] == 0) {\n if (mxm < dp[j]) {\n mxm = dp[j];\n }\n }\n }\n dp[i] = 1 + mxm;\n }\n int max_val = dp[0];\n for (int i = 1; i < n; i++) {\n if (max_val < dp[i]) {\n max_val = dp[i];\n }\n }\n return max_val;\n}", + "test": "int main() {\n\n int array1[] = {1, 3, 6, 13, 17, 18};\n\n int array2[] = {10, 5, 3, 15, 20};\n\n int array3[] = {18, 1, 3, 6, 13, 17};\n\n\n\n assert(func0(array1, 6) == 4);\n\n assert(func0(array2, 5) == 3);\n\n assert(func0(array3, 6) == 4);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0x18,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nmovslq %esi,%rax\nmov %rsp,%rbx\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rbx\nand $0xfffffffffffffff0,%rdx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 12ef \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 12da \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 149b \nlea 0x3(%rsp),%r11\nlea -0x1(%rsi),%r13d\nmov %r11,%r15\nmovslq %r13d,%rax\nand $0xfffffffffffffffc,%r11\nmov %r13d,%r12d\nlea -0x2(%rsi),%r14d\nmovl $0x1,(%r11,%rax,4)\nshr $0x2,%r15\nmovslq %r14d,%rbx\ntest %r14d,%r14d\njs 1389 \ncmp %r12d,%esi\njle 1490 \nmov (%rdi,%rbx,4),%r9d\nmovslq %r12d,%rcx\nxor %r10d,%r10d\nnopl 0x0(%rax,%rax,1)\nmov (%rdi,%rcx,4),%r8d\nmov %r8d,%eax\ncltd\nidiv %r9d\ntest %edx,%edx\nje 1362 \nmov %r9d,%eax\ncltd\nidiv %r8d\ntest %edx,%edx\njne 136d \nmov (%r11,%rcx,4),%eax\ncmp %eax,%r10d\ncmovl %eax,%r10d\nadd $0x1,%rcx\ncmp %ecx,%esi\njg 1348 \nadd $0x1,%r10d\nmov %r10d,(%r11,%rbx,4)\nsub $0x1,%rbx\nsub $0x1,%r12d\ntest %ebx,%ebx\njns 1330 \nmov 0x0(,%r15,4),%eax\ncmp $0x1,%esi\njle 146c \ncmp $0x2,%r14d\njbe 14a6 \nmov %r13d,%edx\nmovd %eax,%xmm4\nmov %r11,%rax\nshr $0x2,%edx\npshufd $0x0,%xmm4,%xmm2\nshl $0x4,%rdx\nadd %r11,%rdx\nnopl (%rax)\nmovdqu 0x4(%rax),%xmm0\nadd $0x10,%rax\nmovdqa %xmm0,%xmm1\npcmpgtd %xmm2,%xmm1\npand %xmm1,%xmm0\npandn %xmm2,%xmm1\nmovdqa %xmm1,%xmm2\npor %xmm0,%xmm2\ncmp %rdx,%rax\njne 13c0 \nmovdqa %xmm2,%xmm0\nmov %r13d,%ecx\npsrldq $0x8,%xmm0\nand $0xfffffffc,%ecx\nmovdqa %xmm0,%xmm1\nmovdqa %xmm0,%xmm3\nlea 0x1(%rcx),%edx\npcmpgtd %xmm2,%xmm1\nmovdqa %xmm1,%xmm0\npand %xmm1,%xmm3\npandn %xmm2,%xmm0\npor %xmm3,%xmm0\nmovdqa %xmm0,%xmm2\npsrldq $0x4,%xmm2\nmovdqa %xmm2,%xmm1\npcmpgtd %xmm0,%xmm1\npand %xmm1,%xmm2\npandn %xmm0,%xmm1\npor %xmm2,%xmm1\nmovd %xmm1,%eax\ncmp %r13d,%ecx\nje 146c \nmovslq %edx,%rcx\nmov (%r11,%rcx,4),%ecx\ncmp %ecx,%eax\ncmovl %ecx,%eax\nlea 0x1(%rdx),%ecx\ncmp %ecx,%esi\njle 146c \nmovslq %ecx,%rcx\nmov (%r11,%rcx,4),%ecx\ncmp %ecx,%eax\ncmovl %ecx,%eax\nadd $0x2,%edx\ncmp %edx,%esi\njle 146c \nmovslq %edx,%rdx\nmov (%r11,%rdx,4),%edx\ncmp %edx,%eax\ncmovl %edx,%eax\nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\njne 14ad \nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\nnopw 0x0(%rax,%rax,1)\nmov $0x1,%r10d\njmpq 1379 \norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 1301 \nmov $0x1,%edx\njmp 143a \ncallq 1060 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov r10, rdi\nmov r9d, esi\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nmovsxd rax, esi\nmov rcx, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_12F2\nloc_12DD:\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\ncmp rsp, rcx\njnz short loc_12DD\nloc_12F2:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_149B\nloc_1304:\nlea r11, [rsp+1040h+var_103D]\nlea r13d, [r9-1]\nmov r14d, r9d\nmov r15, r11\nmovsxd rax, r13d\nand r11, 0FFFFFFFFFFFFFFFCh\nmov dword ptr [r11+rax*4], 1\nshr r15, 2\nsub r14d, 2\njs loc_14A6\nmovsxd rbx, r14d\nmov r12d, r13d\nnop word ptr [rax+rax+00000000h]\nloc_1340:\ncmp r9d, r12d\njle loc_1490\nmov edi, [r10+rbx*4]\nmov ecx, r12d\nxor r8d, r8d\nnop dword ptr [rax+rax+00h]\nloc_1358:\nmov esi, [r10+rcx*4]\nmov eax, esi\ncdq\nidiv edi\ntest edx, edx\njz short loc_136E\nmov eax, edi\ncdq\nidiv esi\ntest edx, edx\njnz short loc_1379\nloc_136E:\nmov eax, [r11+rcx*4]\ncmp r8d, eax\ncmovl r8d, eax\nloc_1379:\nadd rcx, 1\ncmp r9d, ecx\njg short loc_1358\nadd r8d, 1\nloc_1386:\nmov [r11+rbx*4], r8d\nsub rbx, 1\nsub r12d, 1\ntest ebx, ebx\njns short loc_1340\nmov eax, ds:dword_0[r15*4]\ncmp r14d, 2\njbe loc_14B0\nmov edx, r13d\nmovd xmm3, eax\nmov rax, r11\nshr edx, 2\npshufd xmm2, xmm3, 0\nshl rdx, 4\nadd rdx, r11\nnop dword ptr [rax+00000000h]\nloc_13C8:\nmovdqu xmm0, xmmword ptr [rax+4]\nadd rax, 10h\nmovdqa xmm1, xmm0\npcmpgtd xmm1, xmm2\npand xmm0, xmm1\npandn xmm1, xmm2\nmovdqa xmm2, xmm1\npor xmm2, xmm0\ncmp rax, rdx\njnz short loc_13C8\nmovdqa xmm1, xmm2\nmov edx, r13d\npsrldq xmm1, 8\nand edx, 0FFFFFFFCh\nmovdqa xmm0, xmm1\nadd edx, 1\nand r13d, 3\npcmpgtd xmm0, xmm2\npand xmm1, xmm0\npandn xmm0, xmm2\npor xmm0, xmm1\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\nmovdqa xmm1, xmm2\npcmpgtd xmm1, xmm0\npand xmm2, xmm1\npandn xmm1, xmm0\npor xmm1, xmm2\nmovd eax, xmm1\njz short loc_1469\nloc_143B:\nmovsxd rcx, edx\nlea rcx, [r11+rcx*4]\nmov esi, [rcx]\ncmp eax, esi\ncmovl eax, esi\nlea esi, [rdx+1]\ncmp r9d, esi\njle short loc_1469\nmov esi, [rcx+4]\ncmp eax, esi\ncmovl eax, esi\nadd edx, 2\ncmp r9d, edx\njle short loc_1469\nmov edx, [rcx+8]\ncmp eax, edx\ncmovl eax, edx\nloc_1469:\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_14B7\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1490:\nmov r8d, 1\njmp loc_1386\nloc_149B:\nor [rsp+rdx+1040h+var_1048], 0\njmp loc_1304\nloc_14A6:\nmov eax, ds:dword_0[r15*4]\njmp short loc_1469\nloc_14B0:\nmov edx, 1\njmp short loc_143B\nloc_14B7:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v4; // rdx\n unsigned int *v5; // rcx\n __int16 v6; // dx\n signed __int64 v7; // rdx\n void *v8; // rsp\n unsigned int v9; // r13d\n unsigned int v10; // r14d\n __int64 v11; // rbx\n int v12; // r12d\n int v13; // edi\n __int64 v14; // rcx\n signed int v15; // r8d\n unsigned int v16; // r8d\n __int64 result; // rax\n unsigned int *v18; // rax\n __m128i v19; // xmm2\n __m128i v20; // xmm0\n __m128i v21; // xmm1\n __m128i v22; // xmm1\n unsigned int v23; // edx\n __m128i v24; // xmm0\n __m128i v25; // xmm0\n __m128i v26; // xmm2\n __m128i v27; // xmm1\n unsigned int *v28; // rcx\n int v29; // esi\n int v30; // edx\n unsigned int v32[1022]; // [rsp+8h] [rbp-1040h] BYREF\n _QWORD v33[8]; // [rsp+1008h] [rbp-40h] BYREF\n\n v33[1] = __readfsqword(0x28u);\n v4 = 4LL * a2 + 15;\n v5 = (unsigned int *)((char *)v33 - (v4 & 0xFFFFFFFFFFFFF000LL));\n v6 = v4 & 0xFFF0;\n if ( v33 != (_QWORD *)v5 )\n {\n while ( v32 != v5 )\n ;\n }\n v7 = v6 & 0xFFF;\n v8 = alloca(v7);\n if ( v7 )\n *(_QWORD *)((char *)&v32[-2] + v7) = *(_QWORD *)((char *)&v32[-2] + v7);\n v9 = a2 - 1;\n v32[a2 - 1] = 1;\n v10 = a2 - 2;\n if ( a2 - 2 < 0 )\n return v32[0];\n v11 = (int)v10;\n v12 = a2 - 1;\n do\n {\n if ( a2 <= v12 )\n {\n v16 = 1;\n }\n else\n {\n v13 = *(_DWORD *)(a1 + 4 * v11);\n v14 = (unsigned int)v12;\n v15 = 0;\n do\n {\n if ( (!(*(_DWORD *)(a1 + 4 * v14) % v13) || !(v13 % *(_DWORD *)(a1 + 4 * v14))) && v15 < (int)v32[v14] )\n v15 = v32[v14];\n ++v14;\n }\n while ( a2 > (int)v14 );\n v16 = v15 + 1;\n }\n v32[v11--] = v16;\n --v12;\n }\n while ( (int)v11 >= 0 );\n result = v32[0];\n if ( v10 <= 2 )\n {\n v23 = 1;\n }\n else\n {\n v18 = v32;\n v19 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v32[0]), 0);\n do\n {\n v20 = _mm_loadu_si128((const __m128i *)(v18 + 1));\n v18 += 4;\n v21 = _mm_cmpgt_epi32(v20, v19);\n v19 = _mm_or_si128(_mm_andnot_si128(v21, v19), _mm_and_si128(v20, v21));\n }\n while ( v18 != &v32[4 * (v9 >> 2)] );\n v22 = _mm_srli_si128(v19, 8);\n v23 = (v9 & 0xFFFFFFFC) + 1;\n v24 = _mm_cmpgt_epi32(v22, v19);\n v25 = _mm_or_si128(_mm_andnot_si128(v24, v19), _mm_and_si128(v22, v24));\n v26 = _mm_srli_si128(v25, 4);\n v27 = _mm_cmpgt_epi32(v26, v25);\n result = (unsigned int)_mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v27, v25), _mm_and_si128(v26, v27)));\n if ( (v9 & 3) == 0 )\n return result;\n }\n v28 = &v32[v23];\n if ( (int)result < (int)*v28 )\n result = *v28;\n if ( a2 > (int)(v23 + 1) )\n {\n v29 = v28[1];\n if ( (int)result < v29 )\n result = (unsigned int)v29;\n if ( a2 > (int)(v23 + 2) )\n {\n v30 = v28[2];\n if ( (int)result < v30 )\n return (unsigned int)v30;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1290:\nendbr64\npush rbp\nmov r10, rdi\nmov r9d, esi\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nmovsxd rax, esi\nmov rcx, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_12F2\nloc_12DD:\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\ncmp rsp, rcx\njnz short loc_12DD\nloc_12F2:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_149B\nloc_1304:\nlea r11, [rsp+1040h+var_103D]\nlea r13d, [r9-1]\nmov r14d, r9d\nmov r15, r11\nmovsxd rax, r13d\nand r11, 0FFFFFFFFFFFFFFFCh\nmov dword ptr [r11+rax*4], 1\nshr r15, 2\nsub r14d, 2\njs loc_14A6\nmovsxd rbx, r14d\nmov r12d, r13d\nnop word ptr [rax+rax+00000000h]\nloc_1340:\ncmp r9d, r12d\njle loc_1490\nmov edi, [r10+rbx*4]\nmov ecx, r12d\nxor r8d, r8d\nnop dword ptr [rax+rax+00h]\nloc_1358:\nmov esi, [r10+rcx*4]\nmov eax, esi\ncdq\nidiv edi\ntest edx, edx\njz short loc_136E\nmov eax, edi\ncdq\nidiv esi\ntest edx, edx\njnz short loc_1379\nloc_136E:\nmov eax, [r11+rcx*4]\ncmp r8d, eax\ncmovl r8d, eax\nloc_1379:\nadd rcx, 1\ncmp r9d, ecx\njg short loc_1358\nadd r8d, 1\nloc_1386:\nmov [r11+rbx*4], r8d\nsub rbx, 1\nsub r12d, 1\ntest ebx, ebx\njns short loc_1340\nmov eax, ds:dword_0[r15*4]\ncmp r14d, 2\njbe loc_14B0\nmov edx, r13d\nmovd xmm3, eax\nmov rax, r11\nshr edx, 2\npshufd xmm2, xmm3, 0\nshl rdx, 4\nadd rdx, r11\nnop dword ptr [rax+00000000h]\nloc_13C8:\nmovdqu xmm0, xmmword ptr [rax+4]\nadd rax, 10h\nmovdqa xmm1, xmm0\npcmpgtd xmm1, xmm2\npand xmm0, xmm1\npandn xmm1, xmm2\nmovdqa xmm2, xmm1\npor xmm2, xmm0\ncmp rax, rdx\njnz short loc_13C8\nmovdqa xmm1, xmm2\nmov edx, r13d\npsrldq xmm1, 8\nand edx, 0FFFFFFFCh\nmovdqa xmm0, xmm1\nadd edx, 1\nand r13d, 3\npcmpgtd xmm0, xmm2\npand xmm1, xmm0\npandn xmm0, xmm2\npor xmm0, xmm1\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\nmovdqa xmm1, xmm2\npcmpgtd xmm1, xmm0\npand xmm2, xmm1\npandn xmm1, xmm0\npor xmm1, xmm2\nmovd eax, xmm1\njz short loc_1469\nloc_143B:\nmovsxd rcx, edx\nlea rcx, [r11+rcx*4]\nmov esi, [rcx]\ncmp eax, esi\ncmovl eax, esi\nlea esi, [rdx+1]\ncmp r9d, esi\njle short loc_1469\nmov esi, [rcx+4]\ncmp eax, esi\ncmovl eax, esi\nadd edx, 2\ncmp r9d, edx\njle short loc_1469\nmov edx, [rcx+8]\ncmp eax, edx\ncmovl eax, edx\nloc_1469:\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_14B7\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1490:\nmov r8d, 1\njmp loc_1386\nloc_149B:\nor [rsp+rdx+1040h+var_1048], 0\njmp loc_1304\nloc_14A6:\nmov eax, ds:dword_0[r15*4]\njmp short loc_1469\nloc_14B0:\nmov edx, 1\njmp short loc_143B\nloc_14B7:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1290(__int64 a1, int a2)\n{\n __int64 v4; // rdx\n unsigned int *v5; // rcx\n __int16 v6; // dx\n signed __int64 v7; // rdx\n void *v8; // rsp\n unsigned int v9; // r13d\n unsigned int v10; // r14d\n __int64 v11; // rbx\n int v12; // r12d\n int v13; // edi\n __int64 v14; // rcx\n signed int v15; // r8d\n unsigned int v16; // r8d\n __int64 result; // rax\n unsigned int *v18; // rax\n __m128i v19; // xmm2\n __m128i v20; // xmm0\n __m128i v21; // xmm1\n __m128i v22; // xmm1\n unsigned int v23; // edx\n __m128i v24; // xmm0\n __m128i v25; // xmm0\n __m128i v26; // xmm2\n __m128i v27; // xmm1\n unsigned int *v28; // rcx\n int v29; // esi\n int v30; // edx\n unsigned int v32[1022]; // [rsp+8h] [rbp-1040h] BYREF\n _QWORD v33[8]; // [rsp+1008h] [rbp-40h] BYREF\n\n v33[1] = __readfsqword(0x28u);\n v4 = 4LL * a2 + 15;\n v5 = (unsigned int *)((char *)v33 - (v4 & 0xFFFFFFFFFFFFF000LL));\n v6 = v4 & 0xFFF0;\n if ( v33 != (_QWORD *)v5 )\n {\n while ( v32 != v5 )\n ;\n }\n v7 = v6 & 0xFFF;\n v8 = alloca(v7);\n if ( v7 )\n *(_QWORD *)((char *)&v32[-2] + v7) = *(_QWORD *)((char *)&v32[-2] + v7);\n v9 = a2 - 1;\n v32[a2 - 1] = 1;\n v10 = a2 - 2;\n if ( a2 - 2 < 0 )\n return v32[0];\n v11 = (int)v10;\n v12 = a2 - 1;\n do\n {\n if ( a2 <= v12 )\n {\n v16 = 1;\n }\n else\n {\n v13 = *(_DWORD *)(a1 + 4 * v11);\n v14 = (unsigned int)v12;\n v15 = 0;\n do\n {\n if ( (!(*(_DWORD *)(a1 + 4 * v14) % v13) || !(v13 % *(_DWORD *)(a1 + 4 * v14))) && v15 < (int)v32[v14] )\n v15 = v32[v14];\n ++v14;\n }\n while ( a2 > (int)v14 );\n v16 = v15 + 1;\n }\n v32[v11--] = v16;\n --v12;\n }\n while ( (int)v11 >= 0 );\n result = v32[0];\n if ( v10 <= 2 )\n {\n v23 = 1;\n }\n else\n {\n v18 = v32;\n v19 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v32[0]), 0);\n do\n {\n v20 = _mm_loadu_si128((const __m128i *)(v18 + 1));\n v18 += 4;\n v21 = _mm_cmpgt_epi32(v20, v19);\n v19 = _mm_or_si128(_mm_andnot_si128(v21, v19), _mm_and_si128(v20, v21));\n }\n while ( v18 != &v32[4 * (v9 >> 2)] );\n v22 = _mm_srli_si128(v19, 8);\n v23 = (v9 & 0xFFFFFFFC) + 1;\n v24 = _mm_cmpgt_epi32(v22, v19);\n v25 = _mm_or_si128(_mm_andnot_si128(v24, v19), _mm_and_si128(v22, v24));\n v26 = _mm_srli_si128(v25, 4);\n v27 = _mm_cmpgt_epi32(v26, v25);\n result = (unsigned int)_mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v27, v25), _mm_and_si128(v26, v27)));\n if ( (v9 & 3) == 0 )\n return result;\n }\n v28 = &v32[v23];\n if ( (int)result < (int)*v28 )\n result = *v28;\n if ( a2 > (int)(v23 + 1) )\n {\n v29 = v28[1];\n if ( (int)result < v29 )\n result = (unsigned int)v29;\n if ( a2 > (int)(v23 + 2) )\n {\n v30 = v28[2];\n if ( (int)result < v30 )\n return (unsigned int)v30;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1290(long long a1, int a2) {\n long long v4;\n unsigned int *v5;\n short v6;\n signed long long v7;\n void *v8;\n unsigned int v9;\n unsigned int v10;\n long long v11;\n int v12;\n int v13;\n long long v14;\n signed int v15;\n unsigned int v16;\n long long result;\n unsigned int *v18;\n __m128i v19;\n __m128i v20;\n __m128i v21;\n __m128i v22;\n unsigned int v23;\n __m128i v24;\n __m128i v25;\n __m128i v26;\n __m128i v27;\n unsigned int *v28;\n int v29;\n int v30;\n unsigned int v32[1022];\n uint64_t v33[8];\n v33[1] = __readfsqword(40u);\n v4 = 4LL * a2 + 15;\n v5 = (unsigned int *)((char *)v33 - (v4 & 18446744073709547520LL));\n v6 = v4 & 65520;\n if (v33 != (uint64_t *)v5) {\n while (v32 != v5)\n ;\n }\n v7 = v6 & 4095;\n v8 = alloca(v7);\n if (v7)\n *(uint64_t *)((char *)&v32[-2] + v7) = *(uint64_t *)((char *)&v32[-2] + v7);\n v9 = a2 - 1;\n v32[a2 - 1] = 1;\n v10 = a2 - 2;\n if (a2 - 2 < 0) return v32[0];\n v11 = (int)v10;\n v12 = a2 - 1;\n do {\n if (a2 <= v12) {\n v16 = 1;\n } else {\n v13 = *(uint32_t *)(a1 + 4 * v11);\n v14 = (unsigned int)v12;\n v15 = 0;\n do {\n if ((!(*(uint32_t *)(a1 + 4 * v14) % v13) ||\n !(v13 % *(uint32_t *)(a1 + 4 * v14))) &&\n v15 < (int)v32[v14])\n v15 = v32[v14];\n ++v14;\n } while (a2 > (int)v14);\n v16 = v15 + 1;\n }\n v32[v11--] = v16;\n --v12;\n } while ((int)v11 >= 0);\n result = v32[0];\n if (v10 <= 2) {\n v23 = 1;\n } else {\n v18 = v32;\n v19 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v32[0]), 0);\n do {\n v20 = _mm_loadu_si128((const __m128i *)(v18 + 1));\n v18 += 4;\n v21 = _mm_cmpgt_epi32(v20, v19);\n v19 = _mm_or_si128(_mm_andnot_si128(v21, v19), _mm_and_si128(v20, v21));\n } while (v18 != &v32[4 * (v9 >> 2)]);\n v22 = _mm_srli_si128(v19, 8);\n v23 = (v9 & 4294967292) + 1;\n v24 = _mm_cmpgt_epi32(v22, v19);\n v25 = _mm_or_si128(_mm_andnot_si128(v24, v19), _mm_and_si128(v22, v24));\n v26 = _mm_srli_si128(v25, 4);\n v27 = _mm_cmpgt_epi32(v26, v25);\n result = (unsigned int)_mm_cvtsi128_si32(\n _mm_or_si128(_mm_andnot_si128(v27, v25), _mm_and_si128(v26, v27)));\n if ((v9 & 3) == 0) return result;\n }\n v28 = &v32[v23];\n if ((int)result < (int)*v28) result = *v28;\n if (a2 > (int)(v23 + 1)) {\n v29 = v28[1];\n if ((int)result < v29) result = (unsigned int)v29;\n if (a2 > (int)(v23 + 2)) {\n v30 = v28[2];\n if ((int)result < v30) return (unsigned int)v30;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v4;\n unsigned int *v5;\n short v6;\n signed long long v7;\n void *v8;\n unsigned int v9;\n unsigned int v10;\n long long v11;\n int v12;\n int v13;\n long long v14;\n signed int v15;\n unsigned int v16;\n long long result;\n unsigned int *v18;\n __m128i v19;\n __m128i v20;\n __m128i v21;\n __m128i v22;\n unsigned int v23;\n __m128i v24;\n __m128i v25;\n __m128i v26;\n __m128i v27;\n unsigned int *v28;\n int v29;\n int v30;\n unsigned int v32[1022];\n uint64_t v33[8];\n v33[1] = __readfsqword(40u);\n v4 = 4LL * a2 + 15;\n v5 = (unsigned int *)((char *)v33 - (v4 & 18446744073709547520LL));\n v6 = v4 & 65520;\n if (v33 != (uint64_t *)v5) {\n while (v32 != v5)\n ;\n }\n v7 = v6 & 4095;\n v8 = alloca(v7);\n if (v7)\n *(uint64_t *)((char *)&v32[-2] + v7) = *(uint64_t *)((char *)&v32[-2] + v7);\n v9 = a2 - 1;\n v32[a2 - 1] = 1;\n v10 = a2 - 2;\n if (a2 - 2 < 0) return v32[0];\n v11 = (int)v10;\n v12 = a2 - 1;\n do {\n if (a2 <= v12) {\n v16 = 1;\n } else {\n v13 = *(uint32_t *)(a1 + 4 * v11);\n v14 = (unsigned int)v12;\n v15 = 0;\n do {\n if ((!(*(uint32_t *)(a1 + 4 * v14) % v13) ||\n !(v13 % *(uint32_t *)(a1 + 4 * v14))) &&\n v15 < (int)v32[v14])\n v15 = v32[v14];\n ++v14;\n } while (a2 > (int)v14);\n v16 = v15 + 1;\n }\n v32[v11--] = v16;\n --v12;\n } while ((int)v11 >= 0);\n result = v32[0];\n if (v10 <= 2) {\n v23 = 1;\n } else {\n v18 = v32;\n v19 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v32[0]), 0);\n do {\n v20 = _mm_loadu_si128((const __m128i *)(v18 + 1));\n v18 += 4;\n v21 = _mm_cmpgt_epi32(v20, v19);\n v19 = _mm_or_si128(_mm_andnot_si128(v21, v19), _mm_and_si128(v20, v21));\n } while (v18 != &v32[4 * (v9 >> 2)]);\n v22 = _mm_srli_si128(v19, 8);\n v23 = (v9 & 4294967292) + 1;\n v24 = _mm_cmpgt_epi32(v22, v19);\n v25 = _mm_or_si128(_mm_andnot_si128(v24, v19), _mm_and_si128(v22, v24));\n v26 = _mm_srli_si128(v25, 4);\n v27 = _mm_cmpgt_epi32(v26, v25);\n result = (unsigned int)_mm_cvtsi128_si32(\n _mm_or_si128(_mm_andnot_si128(v27, v25), _mm_and_si128(v26, v27)));\n if ((v9 & 3) == 0) return result;\n }\n v28 = &v32[v23];\n if ((int)result < (int)*v28) result = *v28;\n if (a2 > (int)(v23 + 1)) {\n v29 = v28[1];\n if ((int)result < v29) result = (unsigned int)v29;\n if (a2 > (int)(v23 + 2)) {\n v30 = v28[2];\n if ((int)result < v30) return (unsigned int)v30;\n }\n }\n return result;\n}" + }, + { + "index": 621, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(char** test_list, int size, int K) {\n char** res = malloc(size * sizeof(char*));\n for (int i = 0; i < size; i++) {\n if (isdigit(test_list[i][0])) {\n int num = atoi(test_list[i]);\n int incremented = num + K;\n int length = snprintf(NULL, 0, \"%d\", incremented);\n res[i] = malloc(length + 1);\n sprintf(res[i], \"%d\", incremented);\n } else {\n res[i] = strdup(test_list[i]);\n }\n }\n return res;\n}", + "test": "int main() {\n\n char* test1[] = {\"MSM\", \"234\", \"is\", \"98\", \"123\", \"best\", \"4\"};\n\n char* test2[] = {\"Dart\", \"356\", \"is\", \"88\", \"169\", \"Super\", \"6\"};\n\n char* test3[] = {\"Flutter\", \"451\", \"is\", \"44\", \"96\", \"Magnificent\", \"12\"};\n\n int size1 = sizeof(test1) / sizeof(test1[0]);\n\n int size2 = sizeof(test2) / sizeof(test2[0]);\n\n int size3 = sizeof(test3) / sizeof(test3[0]);\n\n\n\n char** res1 = func0(test1, size1, 6);\n\n char** res2 = func0(test2, size2, 12);\n\n char** res3 = func0(test3, size3, 33);\n\n\n\n assert(strcmp(res1[1], \"240\") == 0 && strcmp(res1[3], \"104\") == 0 && strcmp(res1[4], \"129\") == 0 && strcmp(res1[6], \"10\") == 0);\n\n assert(strcmp(res2[1], \"368\") == 0 && strcmp(res2[3], \"100\") == 0 && strcmp(res2[4], \"181\") == 0 && strcmp(res2[6], \"18\") == 0);\n\n assert(strcmp(res3[1], \"484\") == 0 && strcmp(res3[3], \"77\") == 0 && strcmp(res3[4], \"129\") == 0 && strcmp(res3[6], \"45\") == 0);\n\n\n\n // Freeing dynamically allocated memory\n\n for (int i = 0; i < size1; ++i) {\n\n free(res1[i]);\n\n }\n\n free(res1);\n\n\n\n for (int i = 0; i < size2; ++i) {\n\n free(res2[i]);\n\n }\n\n free(res2);\n\n\n\n for (int i = 0; i < size3; ++i) {\n\n free(res3[i]);\n\n }\n\n free(res3);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x38,%rsp\nmov %rdi,-0x38(%rbp)\nmov %esi,-0x3c(%rbp)\nmov %edx,-0x40(%rbp)\nmov -0x3c(%rbp),%eax\ncltq\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 1130 \nmov %rax,-0x18(%rbp)\nmovl $0x0,-0x28(%rbp)\njmpq 13c5 \ncallq 1170 <__ctype_b_loc@plt>\nmov (%rax),%rdx\nmov -0x28(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x38(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%rax\nmovzbl (%rax),%eax\nmovsbq %al,%rax\nadd %rax,%rax\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x800,%eax\ntest %eax,%eax\nje 1389 \nmov -0x28(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov %rax,%rdi\ncallq 1140 \nmov %eax,-0x24(%rbp)\nmov -0x24(%rbp),%edx\nmov -0x40(%rbp),%eax\nadd %edx,%eax\nmov %eax,-0x20(%rbp)\nmov -0x20(%rbp),%eax\nmov %eax,%ecx\nlea 0xcef(%rip),%rdx\nmov $0x0,%esi\nmov $0x0,%edi\nmov $0x0,%eax\ncallq 1100 \nmov %eax,-0x1c(%rbp)\nmov -0x1c(%rbp),%eax\nadd $0x1,%eax\ncltq\nmov -0x28(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x18(%rbp),%rdx\nlea (%rcx,%rdx,1),%rbx\nmov %rax,%rdi\ncallq 1130 \nmov %rax,(%rbx)\nmov -0x28(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0x20(%rbp),%edx\nlea 0xc8e(%rip),%rsi\nmov %rax,%rdi\nmov $0x0,%eax\ncallq 1150 \njmp 13c1 \nmov -0x28(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0x28(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x18(%rbp),%rdx\nlea (%rcx,%rdx,1),%rbx\nmov %rax,%rdi\ncallq 1160 \nmov %rax,(%rbx)\naddl $0x1,-0x28(%rbp)\nmov -0x28(%rbp),%eax\ncmp -0x3c(%rbp),%eax\njl 12a1 \nmov -0x18(%rbp),%rax\nadd $0x38,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov [rbp+var_40], edx\nmov eax, [rbp+var_3C]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_28], 0\njmp loc_13CB\nloc_12A1:\ncall ___ctype_b_loc\nmov rdx, [rax]\nmov eax, [rbp+var_28]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov rax, [rax]\nmovzx eax, byte ptr [rax]\nmovsx rax, al\nadd rax, rax\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 800h\ntest eax, eax\njz loc_138F\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; nptr\ncall _atoi\nmov [rbp+var_24], eax\nmov edx, [rbp+var_24]\nmov eax, [rbp+var_40]\nadd eax, edx\nmov [rbp+var_20], eax\nmov eax, [rbp+var_20]\nmov ecx, eax\nlea rax, format; \"%d\"\nmov rdx, rax; format\nmov esi, 0; maxlen\nmov edi, 0; s\nmov eax, 0\ncall _snprintf\nmov [rbp+var_1C], eax\nmov eax, [rbp+var_1C]\nadd eax, 1\ncdqe\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nlea rbx, [rcx+rdx]\nmov rdi, rax; size\ncall _malloc\nmov [rbx], rax\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_20]\nlea rcx, format; \"%d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\njmp short loc_13C7\nloc_138F:\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nlea rbx, [rcx+rdx]\nmov rdi, rax; s\ncall _strdup\nmov [rbx], rax\nloc_13C7:\nadd [rbp+var_28], 1\nloc_13CB:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_3C]\njl loc_12A1\nmov rax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, int a2, int a3)\n{\n int i; // [rsp+18h] [rbp-28h]\n int v6; // [rsp+20h] [rbp-20h]\n int v7; // [rsp+24h] [rbp-1Ch]\n _QWORD *v8; // [rsp+28h] [rbp-18h]\n\n v8 = malloc(8LL * a2);\n for ( i = 0; i < a2; ++i )\n {\n if ( ((*__ctype_b_loc())[**(char **)(8LL * i + a1)] & 0x800) != 0 )\n {\n v6 = atoi(*(const char **)(8LL * i + a1)) + a3;\n v7 = snprintf(0LL, 0LL, \"%d\", v6);\n v8[i] = malloc(v7 + 1);\n sprintf((char *)v8[i], \"%d\", v6);\n }\n else\n {\n v8[i] = strdup(*(const char **)(8LL * i + a1));\n }\n }\n return v8;\n}", + "ida_strip_asm": "sub_1269:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov [rbp+var_40], edx\nmov eax, [rbp+var_3C]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_28], 0\njmp loc_13CB\nloc_12A1:\ncall ___ctype_b_loc\nmov rdx, [rax]\nmov eax, [rbp+var_28]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov rax, [rax]\nmovzx eax, byte ptr [rax]\nmovsx rax, al\nadd rax, rax\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 800h\ntest eax, eax\njz loc_138F\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; nptr\ncall _atoi\nmov [rbp+var_24], eax\nmov edx, [rbp+var_24]\nmov eax, [rbp+var_40]\nadd eax, edx\nmov [rbp+var_20], eax\nmov eax, [rbp+var_20]\nmov ecx, eax\nlea rax, format; \"%d\"\nmov rdx, rax; format\nmov esi, 0; maxlen\nmov edi, 0; s\nmov eax, 0\ncall _snprintf\nmov [rbp+var_1C], eax\nmov eax, [rbp+var_1C]\nadd eax, 1\ncdqe\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nlea rbx, [rcx+rdx]\nmov rdi, rax; size\ncall _malloc\nmov [rbx], rax\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_20]\nlea rcx, format; \"%d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\njmp short loc_13C7\nloc_138F:\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nlea rbx, [rcx+rdx]\nmov rdi, rax; s\ncall _strdup\nmov [rbx], rax\nloc_13C7:\nadd [rbp+var_28], 1\nloc_13CB:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_3C]\njl loc_12A1\nmov rax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1269(__int64 a1, int a2, int a3)\n{\n int i; // [rsp+18h] [rbp-28h]\n int v6; // [rsp+20h] [rbp-20h]\n int v7; // [rsp+24h] [rbp-1Ch]\n _QWORD *v8; // [rsp+28h] [rbp-18h]\n\n v8 = malloc(8LL * a2);\n for ( i = 0; i < a2; ++i )\n {\n if ( ((*__ctype_b_loc())[**(char **)(8LL * i + a1)] & 0x800) != 0 )\n {\n v6 = atoi(*(const char **)(8LL * i + a1)) + a3;\n v7 = snprintf(0LL, 0LL, \"%d\", v6);\n v8[i] = malloc(v7 + 1);\n sprintf((char *)v8[i], \"%d\", v6);\n }\n else\n {\n v8[i] = strdup(*(const char **)(8LL * i + a1));\n }\n }\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1269(long long a1, int a2, int a3) {\n int i;\n int v6;\n int v7;\n uint64_t *v8;\n v8 = malloc(8LL * a2);\n for (i = 0; i < a2; ++i) {\n if (((*__ctype_b_loc())[**(char **)(8LL * i + a1)] & 2048) != 0) {\n v6 = atoi(*(const char **)(8LL * i + a1)) + a3;\n v7 = snprintf(0LL, 0LL, \"%d\", v6);\n v8[i] = malloc(v7 + 1);\n sprintf((char *)v8[i], \"%d\", v6);\n } else {\n v8[i] = strdup(*(const char **)(8LL * i + a1));\n }\n }\n return v8;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, int a2, int a3) {\n int i;\n int v6;\n int v7;\n uint64_t *v8;\n v8 = malloc(8LL * a2);\n for (i = 0; i < a2; ++i) {\n if (((*__ctype_b_loc())[**(char **)(8LL * i + a1)] & 2048) != 0) {\n v6 = atoi(*(const char **)(8LL * i + a1)) + a3;\n v7 = snprintf(0LL, 0LL, \"%d\", v6);\n v8[i] = malloc(v7 + 1);\n sprintf((char *)v8[i], \"%d\", v6);\n } else {\n v8[i] = strdup(*(const char **)(8LL * i + a1));\n }\n }\n return v8;\n}" + }, + { + "index": 621, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(char** test_list, int size, int K) {\n char** res = malloc(size * sizeof(char*));\n for (int i = 0; i < size; i++) {\n if (isdigit(test_list[i][0])) {\n int num = atoi(test_list[i]);\n int incremented = num + K;\n int length = snprintf(NULL, 0, \"%d\", incremented);\n res[i] = malloc(length + 1);\n sprintf(res[i], \"%d\", incremented);\n } else {\n res[i] = strdup(test_list[i]);\n }\n }\n return res;\n}", + "test": "int main() {\n\n char* test1[] = {\"MSM\", \"234\", \"is\", \"98\", \"123\", \"best\", \"4\"};\n\n char* test2[] = {\"Dart\", \"356\", \"is\", \"88\", \"169\", \"Super\", \"6\"};\n\n char* test3[] = {\"Flutter\", \"451\", \"is\", \"44\", \"96\", \"Magnificent\", \"12\"};\n\n int size1 = sizeof(test1) / sizeof(test1[0]);\n\n int size2 = sizeof(test2) / sizeof(test2[0]);\n\n int size3 = sizeof(test3) / sizeof(test3[0]);\n\n\n\n char** res1 = func0(test1, size1, 6);\n\n char** res2 = func0(test2, size2, 12);\n\n char** res3 = func0(test3, size3, 33);\n\n\n\n assert(strcmp(res1[1], \"240\") == 0 && strcmp(res1[3], \"104\") == 0 && strcmp(res1[4], \"129\") == 0 && strcmp(res1[6], \"10\") == 0);\n\n assert(strcmp(res2[1], \"368\") == 0 && strcmp(res2[3], \"100\") == 0 && strcmp(res2[4], \"181\") == 0 && strcmp(res2[6], \"18\") == 0);\n\n assert(strcmp(res3[1], \"484\") == 0 && strcmp(res3[3], \"77\") == 0 && strcmp(res3[4], \"129\") == 0 && strcmp(res3[6], \"45\") == 0);\n\n\n\n // Freeing dynamically allocated memory\n\n for (int i = 0; i < size1; ++i) {\n\n free(res1[i]);\n\n }\n\n free(res1);\n\n\n\n for (int i = 0; i < size2; ++i) {\n\n free(res2[i]);\n\n }\n\n free(res2);\n\n\n\n for (int i = 0; i < size3; ++i) {\n\n free(res3[i]);\n\n }\n\n free(res3);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov %rdi,%r13\nmov %esi,%ebx\nmov %edx,0xc(%rsp)\nmovslq %esi,%rdi\nshl $0x3,%rdi\ncallq 1120 \nmov %rax,%r12\ntest %ebx,%ebx\njle 1331 \ncallq 1140 <__ctype_b_loc@plt>\nmov %rax,%r14\nlea -0x1(%rbx),%r15d\nmov $0x0,%ebx\njmp 12a7 \ncallq 1130 \nmov %rax,(%r12,%rbx,8)\nlea 0x1(%rbx),%rax\ncmp %r15,%rbx\nje 1331 \nmov %rax,%rbx\nmov 0x0(%r13,%rbx,8),%rdi\nmovsbq (%rdi),%rdx\nmov (%r14),%rax\ntestb $0x8,0x1(%rax,%rdx,2)\nje 128e \nmov $0xa,%edx\nmov $0x0,%esi\ncallq 1110 \nmov 0xc(%rsp),%ecx\nlea (%rcx,%rax,1),%ebp\nmov %ebp,%r9d\nlea 0xd2a(%rip),%r8\nmov $0xffffffffffffffff,%rcx\nmov $0x1,%edx\nmov $0x0,%esi\nmov $0x0,%edi\nmov $0x0,%eax\ncallq 10d0 <__snprintf_chk@plt>\nlea 0x1(%rax),%edi\nmovslq %edi,%rdi\ncallq 1120 \nmov %rax,%rdi\nmov %rax,(%r12,%rbx,8)\nmov %ebp,%r8d\nlea 0xcee(%rip),%rcx\nmov $0xffffffffffffffff,%rdx\nmov $0x1,%esi\nmov $0x0,%eax\ncallq 1150 <__sprintf_chk@plt>\njmpq 1297 \nmov %r12,%rax\nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov r14, rdi\nmov ebx, esi\nmov [rsp+48h+var_44], edx\nmovsxd rbp, esi\nshl rbp, 3\nmov rdi, rbp; size\ncall _malloc\nmov [rsp+48h+var_40], rax\ntest ebx, ebx\njle loc_1355\nmov r12, rax\ncall ___ctype_b_loc\nmov r15, rax\nmov rbx, r14\nadd r14, rbp\njmp short loc_12CD\nloc_12B3:\ncall _strdup\nmov [r12], rax\nloc_12BC:\nadd rbx, 8\nadd r12, 8\ncmp rbx, r14\njz loc_1355\nloc_12CD:\nmov rdi, [rbx]; nptr\nmovsx rdx, byte ptr [rdi]\nmov rax, [r15]\ntest byte ptr [rax+rdx*2+1], 8\njz short loc_12B3\nmov edx, 0Ah; base\nmov esi, 0; endptr\ncall _strtol\nmov ecx, [rsp+48h+var_44]\nlea r13d, [rcx+rax]\nmov r9d, r13d\nlea r8, unk_2004\nmov rcx, 0FFFFFFFFFFFFFFFFh\nmov edx, 2\nmov esi, 0\nmov edi, 0\nmov eax, 0\ncall ___snprintf_chk\nlea ebp, [rax+1]\nmovsxd rbp, ebp\nmov rdi, rbp; size\ncall _malloc\nmov rdi, rax\nmov [r12], rax\nmov r8d, r13d\nlea rcx, unk_2004\nmov rdx, rbp\nmov esi, 2\nmov eax, 0\ncall ___sprintf_chk\njmp loc_12BC\nloc_1355:\nmov rax, [rsp+48h+var_40]\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(const char **a1, int a2, int a3)\n{\n _QWORD *v3; // rax\n char **v4; // r12\n const unsigned __int16 **v5; // r15\n const char **v6; // rbx\n const char **v7; // r14\n const char *v8; // rdi\n __int64 v9; // r13\n size_t v10; // rbp\n char *v11; // rax\n _QWORD *v14; // [rsp+8h] [rbp-40h]\n\n v3 = malloc(8LL * a2);\n v14 = v3;\n if ( a2 > 0 )\n {\n v4 = (char **)v3;\n v5 = __ctype_b_loc();\n v6 = a1;\n v7 = &a1[a2];\n do\n {\n v8 = *v6;\n if ( ((*v5)[**v6] & 0x800) != 0 )\n {\n v9 = a3 + (unsigned int)strtol(v8, 0LL, 10);\n v10 = (int)(__snprintf_chk(0LL, 0LL, 2LL, -1LL, &unk_2004, v9) + 1);\n v11 = (char *)malloc(v10);\n *v4 = v11;\n __sprintf_chk(v11, 2LL, v10, &unk_2004, (unsigned int)v9);\n }\n else\n {\n *v4 = strdup(v8);\n }\n ++v6;\n ++v4;\n }\n while ( v6 != v7 );\n }\n return v14;\n}", + "ida_strip_asm": "sub_1269:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov r14, rdi\nmov ebx, esi\nmov [rsp+48h+var_44], edx\nmovsxd rbp, esi\nshl rbp, 3\nmov rdi, rbp; size\ncall _malloc\nmov [rsp+48h+var_40], rax\ntest ebx, ebx\njle loc_1355\nmov r12, rax\ncall ___ctype_b_loc\nmov r15, rax\nmov rbx, r14\nadd r14, rbp\njmp short loc_12CD\nloc_12B3:\ncall _strdup\nmov [r12], rax\nloc_12BC:\nadd rbx, 8\nadd r12, 8\ncmp rbx, r14\njz loc_1355\nloc_12CD:\nmov rdi, [rbx]; nptr\nmovsx rdx, byte ptr [rdi]\nmov rax, [r15]\ntest byte ptr [rax+rdx*2+1], 8\njz short loc_12B3\nmov edx, 0Ah; base\nmov esi, 0; endptr\ncall _strtol\nmov ecx, [rsp+48h+var_44]\nlea r13d, [rcx+rax]\nmov r9d, r13d\nlea r8, unk_2004\nmov rcx, 0FFFFFFFFFFFFFFFFh\nmov edx, 2\nmov esi, 0\nmov edi, 0\nmov eax, 0\ncall ___snprintf_chk\nlea ebp, [rax+1]\nmovsxd rbp, ebp\nmov rdi, rbp; size\ncall _malloc\nmov rdi, rax\nmov [r12], rax\nmov r8d, r13d\nlea rcx, unk_2004\nmov rdx, rbp\nmov esi, 2\nmov eax, 0\ncall ___sprintf_chk\njmp loc_12BC\nloc_1355:\nmov rax, [rsp+48h+var_40]\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1269(const char **a1, int a2, int a3)\n{\n _QWORD *v3; // rax\n char **v4; // r12\n const unsigned __int16 **v5; // r15\n const char **v6; // rbx\n const char **v7; // r14\n const char *v8; // rdi\n __int64 v9; // r13\n size_t v10; // rbp\n char *v11; // rax\n _QWORD *v14; // [rsp+8h] [rbp-40h]\n\n v3 = malloc(8LL * a2);\n v14 = v3;\n if ( a2 > 0 )\n {\n v4 = (char **)v3;\n v5 = __ctype_b_loc();\n v6 = a1;\n v7 = &a1[a2];\n do\n {\n v8 = *v6;\n if ( ((*v5)[**v6] & 0x800) != 0 )\n {\n v9 = a3 + (unsigned int)strtol(v8, 0LL, 10);\n v10 = (int)(__snprintf_chk(0LL, 0LL, 2LL, -1LL, &unk_2004, v9) + 1);\n v11 = (char *)malloc(v10);\n *v4 = v11;\n __sprintf_chk(v11, 2LL, v10, &unk_2004, (unsigned int)v9);\n }\n else\n {\n *v4 = strdup(v8);\n }\n ++v6;\n ++v4;\n }\n while ( v6 != v7 );\n }\n return v14;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1269(const char **a1, int a2, int a3) {\n uint64_t *v3;\n char **v4;\n const unsigned short **v5;\n const char **v6;\n const char **v7;\n const char *v8;\n long long v9;\n unsigned int v10;\n char *v11;\n uint64_t *v14;\n v3 = malloc(8LL * a2);\n v14 = v3;\n if (a2 > 0) {\n v4 = (char **)v3;\n v5 = __ctype_b_loc();\n v6 = a1;\n v7 = &a1[a2];\n do {\n v8 = *v6;\n if (((*v5)[**v6] & 2048) != 0) {\n v9 = a3 + (unsigned int)strtol(v8, 0LL, 10);\n v10 = (int)(__snprintf_chk(0LL, 0LL, 2LL, -1LL, &unk_2004, v9) + 1);\n v11 = (char *)malloc(v10);\n *v4 = v11;\n __sprintf_chk(v11, 2LL, v10, &unk_2004, (unsigned int)v9);\n } else {\n *v4 = strdup(v8);\n }\n ++v6;\n ++v4;\n } while (v6 != v7);\n }\n return v14;\n}", + "ida_pseudo_norm": "uint64_t *func0(const char **a1, int a2, int a3) {\n uint64_t *v3;\n char **v4;\n const unsigned short **v5;\n const char **v6;\n const char **v7;\n const char *v8;\n long long v9;\n unsigned int v10;\n char *v11;\n uint64_t *v14;\n v3 = malloc(8LL * a2);\n v14 = v3;\n if (a2 > 0) {\n v4 = (char **)v3;\n v5 = __ctype_b_loc();\n v6 = a1;\n v7 = &a1[a2];\n do {\n v8 = *v6;\n if (((*v5)[**v6] & 2048) != 0) {\n v9 = a3 + (unsigned int)strtol(v8, 0LL, 10);\n v10 = (int)(__snprintf_chk(0LL, 0LL, 2LL, -1LL, &unk_2004, v9) + 1);\n v11 = (char *)malloc(v10);\n *v4 = v11;\n __sprintf_chk(v11, 2LL, v10, &unk_2004, (unsigned int)v9);\n } else {\n *v4 = strdup(v8);\n }\n ++v6;\n ++v4;\n } while (v6 != v7);\n }\n return v14;\n}" + }, + { + "index": 621, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(char** test_list, int size, int K) {\n char** res = malloc(size * sizeof(char*));\n for (int i = 0; i < size; i++) {\n if (isdigit(test_list[i][0])) {\n int num = atoi(test_list[i]);\n int incremented = num + K;\n int length = snprintf(NULL, 0, \"%d\", incremented);\n res[i] = malloc(length + 1);\n sprintf(res[i], \"%d\", incremented);\n } else {\n res[i] = strdup(test_list[i]);\n }\n }\n return res;\n}", + "test": "int main() {\n\n char* test1[] = {\"MSM\", \"234\", \"is\", \"98\", \"123\", \"best\", \"4\"};\n\n char* test2[] = {\"Dart\", \"356\", \"is\", \"88\", \"169\", \"Super\", \"6\"};\n\n char* test3[] = {\"Flutter\", \"451\", \"is\", \"44\", \"96\", \"Magnificent\", \"12\"};\n\n int size1 = sizeof(test1) / sizeof(test1[0]);\n\n int size2 = sizeof(test2) / sizeof(test2[0]);\n\n int size3 = sizeof(test3) / sizeof(test3[0]);\n\n\n\n char** res1 = func0(test1, size1, 6);\n\n char** res2 = func0(test2, size2, 12);\n\n char** res3 = func0(test3, size3, 33);\n\n\n\n assert(strcmp(res1[1], \"240\") == 0 && strcmp(res1[3], \"104\") == 0 && strcmp(res1[4], \"129\") == 0 && strcmp(res1[6], \"10\") == 0);\n\n assert(strcmp(res2[1], \"368\") == 0 && strcmp(res2[3], \"100\") == 0 && strcmp(res2[4], \"181\") == 0 && strcmp(res2[6], \"18\") == 0);\n\n assert(strcmp(res3[1], \"484\") == 0 && strcmp(res3[3], \"77\") == 0 && strcmp(res3[4], \"129\") == 0 && strcmp(res3[6], \"45\") == 0);\n\n\n\n // Freeing dynamically allocated memory\n\n for (int i = 0; i < size1; ++i) {\n\n free(res1[i]);\n\n }\n\n free(res1);\n\n\n\n for (int i = 0; i < size2; ++i) {\n\n free(res2[i]);\n\n }\n\n free(res2);\n\n\n\n for (int i = 0; i < size3; ++i) {\n\n free(res3[i]);\n\n }\n\n free(res3);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\nmov %rdi,%rbp\nmovslq %esi,%rdi\npush %rbx\nmov %rdi,%rbx\nshl $0x3,%rdi\nsub $0x18,%rsp\nmov %edx,0xc(%rsp)\ncallq 1120 \nmov %rax,%r12\ntest %ebx,%ebx\njle 16e8 \ncallq 1140 <__ctype_b_loc@plt>\nlea -0x1(%rbx),%r14d\nlea 0x9c1(%rip),%r13\nxor %ebx,%ebx\nmov %rax,%r15\njmp 16bf \nnopw 0x0(%rax,%rax,1)\nmov $0xa,%edx\nxor %esi,%esi\ncallq 1110 \nmov 0xc(%rsp),%ecx\nmov %r13,%r8\nxor %esi,%esi\nmov $0x1,%edx\nxor %edi,%edi\nlea (%rcx,%rax,1),%r9d\nmov $0xffffffffffffffff,%rcx\nxor %eax,%eax\nmov %r9d,0x8(%rsp)\ncallq 10d0 <__snprintf_chk@plt>\nlea 0x1(%rax),%edi\nmovslq %edi,%rdi\ncallq 1120 \nmov 0x8(%rsp),%r9d\nmov %r13,%rcx\nmov $0xffffffffffffffff,%rdx\nmov %rax,(%r12,%rbx,8)\nmov %rax,%rdi\nmov $0x1,%esi\nxor %eax,%eax\nmov %r9d,%r8d\ncallq 1150 <__sprintf_chk@plt>\nlea 0x1(%rbx),%rax\ncmp %r14,%rbx\nje 16e8 \nmov %rax,%rbx\nmov 0x0(%rbp,%rbx,8),%rdi\nmov (%r15),%rax\nmovsbq (%rdi),%rdx\ntestb $0x8,0x1(%rax,%rdx,2)\njne 1650 \ncallq 1130 \nmov %rax,(%r12,%rbx,8)\nlea 0x1(%rbx),%rax\ncmp %r14,%rbx\njne 16bc \nadd $0x18,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmovsxd r12, esi\npush rbp\nmov rbp, r12\nshl r12, 3\npush rbx\nmov rbx, rdi\nmov rdi, r12; size\nsub rsp, 18h\nmov [rsp+48h+var_44], edx\ncall _malloc\nmov [rsp+48h+var_40], rax\ntest ebp, ebp\njle loc_170B\nmov r14, rax\nadd r12, rbx\ncall ___ctype_b_loc\nmov rbp, r14\nmov r15, rax\njmp short loc_16E0\nloc_1670:\nmov edx, 0Ah; base\nxor esi, esi; endptr\nadd rbx, 8\nadd rbp, 8\ncall _strtol\nmov ecx, [rsp+48h+var_44]\nxor esi, esi\nmov edx, 2\nlea r8, unk_2004\nxor edi, edi\nlea r13d, [rcx+rax]\nmov rcx, 0FFFFFFFFFFFFFFFFh\nxor eax, eax\nmov r9d, r13d\ncall ___snprintf_chk\nlea edx, [rax+1]\nmovsxd r14, edx\nmov rdi, r14; size\ncall _malloc\nmov r8d, r13d\nmov rdx, r14\nmov esi, 2\nmov [rbp-8], rax\nmov rdi, rax\nlea rcx, unk_2004\nxor eax, eax\ncall ___sprintf_chk\ncmp r12, rbx\njz short loc_170B\nloc_16E0:\nmov rdi, [rbx]; s\nmov rax, [r15]\nmovsx rdx, byte ptr [rdi]\ntest byte ptr [rax+rdx*2+1], 8\njnz loc_1670\ncall _strdup\nadd rbx, 8\nadd rbp, 8\nmov [rbp-8], rax\ncmp r12, rbx\njnz short loc_16E0\nloc_170B:\nmov rax, [rsp+48h+var_40]\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "void *__fastcall func0(const char **a1, int a2, int a3)\n{\n const char **v3; // rbx\n void *v4; // rax\n const char **v5; // r12\n _QWORD *v6; // rbp\n const unsigned __int16 **v7; // r15\n unsigned int v8; // r13d\n size_t v9; // r14\n void *v10; // rax\n const char *v11; // rdi\n void *v14; // [rsp+8h] [rbp-40h]\n\n v3 = a1;\n v4 = malloc(8LL * a2);\n v14 = v4;\n if ( a2 > 0 )\n {\n v5 = &a1[a2];\n v6 = v4;\n v7 = __ctype_b_loc();\n do\n {\n while ( 1 )\n {\n v11 = *v3;\n if ( ((*v7)[**v3] & 0x800) == 0 )\n break;\n ++v3;\n ++v6;\n v8 = a3 + strtol(v11, 0LL, 10);\n v9 = (int)(__snprintf_chk(0LL, 0LL, 2LL, -1LL, &unk_2004, v8) + 1);\n v10 = malloc(v9);\n *(v6 - 1) = v10;\n __sprintf_chk(v10, 2LL, v9, &unk_2004, v8);\n if ( v5 == v3 )\n return v14;\n }\n ++v3;\n *v6++ = strdup(v11);\n }\n while ( v5 != v3 );\n }\n return v14;\n}", + "ida_strip_asm": "sub_1620:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmovsxd r12, esi\npush rbp\nmov rbp, r12\nshl r12, 3\npush rbx\nmov rbx, rdi\nmov rdi, r12; size\nsub rsp, 18h\nmov [rsp+48h+var_44], edx\ncall _malloc\nmov [rsp+48h+var_40], rax\ntest ebp, ebp\njle loc_170B\nmov r14, rax\nadd r12, rbx\ncall ___ctype_b_loc\nmov rbp, r14\nmov r15, rax\njmp short loc_16E0\nloc_1670:\nmov edx, 0Ah; base\nxor esi, esi; endptr\nadd rbx, 8\nadd rbp, 8\ncall _strtol\nmov ecx, [rsp+48h+var_44]\nxor esi, esi\nmov edx, 2\nlea r8, unk_2004\nxor edi, edi\nlea r13d, [rcx+rax]\nmov rcx, 0FFFFFFFFFFFFFFFFh\nxor eax, eax\nmov r9d, r13d\ncall ___snprintf_chk\nlea edx, [rax+1]\nmovsxd r14, edx\nmov rdi, r14; size\ncall _malloc\nmov r8d, r13d\nmov rdx, r14\nmov esi, 2\nmov [rbp-8], rax\nmov rdi, rax\nlea rcx, unk_2004\nxor eax, eax\ncall ___sprintf_chk\ncmp r12, rbx\njz short loc_170B\nloc_16E0:\nmov rdi, [rbx]; s\nmov rax, [r15]\nmovsx rdx, byte ptr [rdi]\ntest byte ptr [rax+rdx*2+1], 8\njnz loc_1670\ncall _strdup\nadd rbx, 8\nadd rbp, 8\nmov [rbp-8], rax\ncmp r12, rbx\njnz short loc_16E0\nloc_170B:\nmov rax, [rsp+48h+var_40]\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "void *__fastcall sub_1620(const char **a1, int a2, int a3)\n{\n const char **v3; // rbx\n void *v4; // rax\n const char **v5; // r12\n _QWORD *v6; // rbp\n const unsigned __int16 **v7; // r15\n unsigned int v8; // r13d\n size_t v9; // r14\n void *v10; // rax\n const char *v11; // rdi\n void *v14; // [rsp+8h] [rbp-40h]\n\n v3 = a1;\n v4 = malloc(8LL * a2);\n v14 = v4;\n if ( a2 > 0 )\n {\n v5 = &a1[a2];\n v6 = v4;\n v7 = __ctype_b_loc();\n do\n {\n while ( 1 )\n {\n v11 = *v3;\n if ( ((*v7)[**v3] & 0x800) == 0 )\n break;\n ++v3;\n ++v6;\n v8 = a3 + strtol(v11, 0LL, 10);\n v9 = (int)(__snprintf_chk(0LL, 0LL, 2LL, -1LL, &unk_2004, v8) + 1);\n v10 = malloc(v9);\n *(v6 - 1) = v10;\n __sprintf_chk(v10, 2LL, v9, &unk_2004, v8);\n if ( v5 == v3 )\n return v14;\n }\n ++v3;\n *v6++ = strdup(v11);\n }\n while ( v5 != v3 );\n }\n return v14;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1620(const char **a1, int a2, int a3) {\n const char **v3;\n void *v4;\n const char **v5;\n uint64_t *v6;\n const unsigned short **v7;\n unsigned int v8;\n unsigned int v9;\n void *v10;\n const char *v11;\n void *v14;\n v3 = a1;\n v4 = malloc(8LL * a2);\n v14 = v4;\n if (a2 > 0) {\n v5 = &a1[a2];\n v6 = v4;\n v7 = __ctype_b_loc();\n do {\n while (1) {\n v11 = *v3;\n if (((*v7)[**v3] & 2048) == 0) break;\n ++v3;\n ++v6;\n v8 = a3 + strtol(v11, 0LL, 10);\n v9 = (int)(__snprintf_chk(0LL, 0LL, 2LL, -1LL, &unk_2004, v8) + 1);\n v10 = malloc(v9);\n *(v6 - 1) = v10;\n __sprintf_chk(v10, 2LL, v9, &unk_2004, v8);\n if (v5 == v3) return v14;\n }\n ++v3;\n *v6++ = strdup(v11);\n } while (v5 != v3);\n }\n return v14;\n}", + "ida_pseudo_norm": "void *func0(const char **a1, int a2, int a3) {\n const char **v3;\n void *v4;\n const char **v5;\n uint64_t *v6;\n const unsigned short **v7;\n unsigned int v8;\n unsigned int v9;\n void *v10;\n const char *v11;\n void *v14;\n v3 = a1;\n v4 = malloc(8LL * a2);\n v14 = v4;\n if (a2 > 0) {\n v5 = &a1[a2];\n v6 = v4;\n v7 = __ctype_b_loc();\n do {\n while (1) {\n v11 = *v3;\n if (((*v7)[**v3] & 2048) == 0) break;\n ++v3;\n ++v6;\n v8 = a3 + strtol(v11, 0LL, 10);\n v9 = (int)(__snprintf_chk(0LL, 0LL, 2LL, -1LL, &unk_2004, v8) + 1);\n v10 = malloc(v9);\n *(v6 - 1) = v10;\n __sprintf_chk(v10, 2LL, v9, &unk_2004, v8);\n if (v5 == v3) return v14;\n }\n ++v3;\n *v6++ = strdup(v11);\n } while (v5 != v3);\n }\n return v14;\n}" + }, + { + "index": 621, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(char** test_list, int size, int K) {\n char** res = malloc(size * sizeof(char*));\n for (int i = 0; i < size; i++) {\n if (isdigit(test_list[i][0])) {\n int num = atoi(test_list[i]);\n int incremented = num + K;\n int length = snprintf(NULL, 0, \"%d\", incremented);\n res[i] = malloc(length + 1);\n sprintf(res[i], \"%d\", incremented);\n } else {\n res[i] = strdup(test_list[i]);\n }\n }\n return res;\n}", + "test": "int main() {\n\n char* test1[] = {\"MSM\", \"234\", \"is\", \"98\", \"123\", \"best\", \"4\"};\n\n char* test2[] = {\"Dart\", \"356\", \"is\", \"88\", \"169\", \"Super\", \"6\"};\n\n char* test3[] = {\"Flutter\", \"451\", \"is\", \"44\", \"96\", \"Magnificent\", \"12\"};\n\n int size1 = sizeof(test1) / sizeof(test1[0]);\n\n int size2 = sizeof(test2) / sizeof(test2[0]);\n\n int size3 = sizeof(test3) / sizeof(test3[0]);\n\n\n\n char** res1 = func0(test1, size1, 6);\n\n char** res2 = func0(test2, size2, 12);\n\n char** res3 = func0(test3, size3, 33);\n\n\n\n assert(strcmp(res1[1], \"240\") == 0 && strcmp(res1[3], \"104\") == 0 && strcmp(res1[4], \"129\") == 0 && strcmp(res1[6], \"10\") == 0);\n\n assert(strcmp(res2[1], \"368\") == 0 && strcmp(res2[3], \"100\") == 0 && strcmp(res2[4], \"181\") == 0 && strcmp(res2[6], \"18\") == 0);\n\n assert(strcmp(res3[1], \"484\") == 0 && strcmp(res3[3], \"77\") == 0 && strcmp(res3[4], \"129\") == 0 && strcmp(res3[6], \"45\") == 0);\n\n\n\n // Freeing dynamically allocated memory\n\n for (int i = 0; i < size1; ++i) {\n\n free(res1[i]);\n\n }\n\n free(res1);\n\n\n\n for (int i = 0; i < size2; ++i) {\n\n free(res2[i]);\n\n }\n\n free(res2);\n\n\n\n for (int i = 0; i < size3; ++i) {\n\n free(res3[i]);\n\n }\n\n free(res3);\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\nmov %rdi,%rbp\nmovslq %esi,%rdi\npush %rbx\nmov %rdi,%rbx\nshl $0x3,%rdi\nsub $0x18,%rsp\nmov %edx,0xc(%rsp)\ncallq 1120 \nmov %rax,%r12\ntest %ebx,%ebx\njle 1728 \ncallq 1140 <__ctype_b_loc@plt>\nlea -0x1(%rbx),%r14d\nlea 0x981(%rip),%r13\nxor %ebx,%ebx\nmov %rax,%r15\njmp 16ff \nnopw 0x0(%rax,%rax,1)\nmov $0xa,%edx\nxor %esi,%esi\ncallq 1110 \nmov 0xc(%rsp),%ecx\nmov %r13,%r8\nxor %esi,%esi\nmov $0x1,%edx\nxor %edi,%edi\nlea (%rcx,%rax,1),%r9d\nmov $0xffffffffffffffff,%rcx\nxor %eax,%eax\nmov %r9d,0x8(%rsp)\ncallq 10d0 <__snprintf_chk@plt>\nlea 0x1(%rax),%edi\nmovslq %edi,%rdi\ncallq 1120 \nmov 0x8(%rsp),%r9d\nmov %r13,%rcx\nmov $0xffffffffffffffff,%rdx\nmov %rax,(%r12,%rbx,8)\nmov %rax,%rdi\nmov $0x1,%esi\nxor %eax,%eax\nmov %r9d,%r8d\ncallq 1150 <__sprintf_chk@plt>\nlea 0x1(%rbx),%rax\ncmp %r14,%rbx\nje 1728 \nmov %rax,%rbx\nmov 0x0(%rbp,%rbx,8),%rdi\nmov (%r15),%rax\nmovsbq (%rdi),%rdx\ntestb $0x8,0x1(%rax,%rdx,2)\njne 1690 \ncallq 1130 \nmov %rax,(%r12,%rbx,8)\nlea 0x1(%rbx),%rax\ncmp %r14,%rbx\njne 16fc \nadd $0x18,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmovsxd r12, esi\npush rbp\nmov rbp, r12\nshl r12, 3\npush rbx\nmov rbx, rdi\nmov rdi, r12; size\nsub rsp, 18h\nmov [rsp+48h+var_44], edx\ncall _malloc\nmov [rsp+48h+var_40], rax\ntest ebp, ebp\njle loc_170B\nmov r14, rax\nadd r12, rbx\ncall ___ctype_b_loc\nmov rbp, r14\nmov r15, rax\njmp short loc_16E0\nloc_1670:\nmov edx, 0Ah; base\nxor esi, esi; endptr\nadd rbx, 8\nadd rbp, 8\ncall _strtol\nmov ecx, [rsp+48h+var_44]\nxor esi, esi\nmov edx, 2\nlea r8, unk_2004\nxor edi, edi\nlea r13d, [rcx+rax]\nmov rcx, 0FFFFFFFFFFFFFFFFh\nxor eax, eax\nmov r9d, r13d\ncall ___snprintf_chk\nlea edx, [rax+1]\nmovsxd r14, edx\nmov rdi, r14; size\ncall _malloc\nmov r8d, r13d\nmov rdx, r14\nmov esi, 2\nmov [rbp-8], rax\nmov rdi, rax\nlea rcx, unk_2004\nxor eax, eax\ncall ___sprintf_chk\ncmp r12, rbx\njz short loc_170B\nloc_16E0:\nmov rdi, [rbx]; s\nmov rax, [r15]\nmovsx rdx, byte ptr [rdi]\ntest byte ptr [rax+rdx*2+1], 8\njnz loc_1670\ncall _strdup\nadd rbx, 8\nadd rbp, 8\nmov [rbp-8], rax\ncmp r12, rbx\njnz short loc_16E0\nloc_170B:\nmov rax, [rsp+48h+var_40]\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "void *__fastcall func0(const char **a1, int a2, int a3)\n{\n const char **v3; // rbx\n void *v4; // rax\n const char **v5; // r12\n _QWORD *v6; // rbp\n const unsigned __int16 **v7; // r15\n unsigned int v8; // r13d\n size_t v9; // r14\n void *v10; // rax\n const char *v11; // rdi\n void *v14; // [rsp+8h] [rbp-40h]\n\n v3 = a1;\n v4 = malloc(8LL * a2);\n v14 = v4;\n if ( a2 > 0 )\n {\n v5 = &a1[a2];\n v6 = v4;\n v7 = __ctype_b_loc();\n do\n {\n while ( 1 )\n {\n v11 = *v3;\n if ( ((*v7)[**v3] & 0x800) == 0 )\n break;\n ++v3;\n ++v6;\n v8 = a3 + strtol(v11, 0LL, 10);\n v9 = (int)(__snprintf_chk(0LL, 0LL, 2LL, -1LL, &unk_2004, v8) + 1);\n v10 = malloc(v9);\n *(v6 - 1) = v10;\n __sprintf_chk(v10, 2LL, v9, &unk_2004, v8);\n if ( v5 == v3 )\n return v14;\n }\n ++v3;\n *v6++ = strdup(v11);\n }\n while ( v5 != v3 );\n }\n return v14;\n}", + "ida_strip_asm": "sub_1620:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmovsxd r12, esi\npush rbp\nmov rbp, r12\nshl r12, 3\npush rbx\nmov rbx, rdi\nmov rdi, r12; size\nsub rsp, 18h\nmov [rsp+48h+var_44], edx\ncall _malloc\nmov [rsp+48h+var_40], rax\ntest ebp, ebp\njle loc_170B\nmov r14, rax\nadd r12, rbx\ncall ___ctype_b_loc\nmov rbp, r14\nmov r15, rax\njmp short loc_16E0\nloc_1670:\nmov edx, 0Ah; base\nxor esi, esi; endptr\nadd rbx, 8\nadd rbp, 8\ncall _strtol\nmov ecx, [rsp+48h+var_44]\nxor esi, esi\nmov edx, 2\nlea r8, unk_2004\nxor edi, edi\nlea r13d, [rcx+rax]\nmov rcx, 0FFFFFFFFFFFFFFFFh\nxor eax, eax\nmov r9d, r13d\ncall ___snprintf_chk\nlea edx, [rax+1]\nmovsxd r14, edx\nmov rdi, r14; size\ncall _malloc\nmov r8d, r13d\nmov rdx, r14\nmov esi, 2\nmov [rbp-8], rax\nmov rdi, rax\nlea rcx, unk_2004\nxor eax, eax\ncall ___sprintf_chk\ncmp r12, rbx\njz short loc_170B\nloc_16E0:\nmov rdi, [rbx]; s\nmov rax, [r15]\nmovsx rdx, byte ptr [rdi]\ntest byte ptr [rax+rdx*2+1], 8\njnz loc_1670\ncall _strdup\nadd rbx, 8\nadd rbp, 8\nmov [rbp-8], rax\ncmp r12, rbx\njnz short loc_16E0\nloc_170B:\nmov rax, [rsp+48h+var_40]\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "void *__fastcall sub_1620(const char **a1, int a2, int a3)\n{\n const char **v3; // rbx\n void *v4; // rax\n const char **v5; // r12\n _QWORD *v6; // rbp\n const unsigned __int16 **v7; // r15\n unsigned int v8; // r13d\n size_t v9; // r14\n void *v10; // rax\n const char *v11; // rdi\n void *v14; // [rsp+8h] [rbp-40h]\n\n v3 = a1;\n v4 = malloc(8LL * a2);\n v14 = v4;\n if ( a2 > 0 )\n {\n v5 = &a1[a2];\n v6 = v4;\n v7 = __ctype_b_loc();\n do\n {\n while ( 1 )\n {\n v11 = *v3;\n if ( ((*v7)[**v3] & 0x800) == 0 )\n break;\n ++v3;\n ++v6;\n v8 = a3 + strtol(v11, 0LL, 10);\n v9 = (int)(__snprintf_chk(0LL, 0LL, 2LL, -1LL, &unk_2004, v8) + 1);\n v10 = malloc(v9);\n *(v6 - 1) = v10;\n __sprintf_chk(v10, 2LL, v9, &unk_2004, v8);\n if ( v5 == v3 )\n return v14;\n }\n ++v3;\n *v6++ = strdup(v11);\n }\n while ( v5 != v3 );\n }\n return v14;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1620(const char **a1, int a2, int a3) {\n const char **v3;\n void *v4;\n const char **v5;\n uint64_t *v6;\n const unsigned short **v7;\n unsigned int v8;\n unsigned int v9;\n void *v10;\n const char *v11;\n void *v14;\n v3 = a1;\n v4 = malloc(8LL * a2);\n v14 = v4;\n if (a2 > 0) {\n v5 = &a1[a2];\n v6 = v4;\n v7 = __ctype_b_loc();\n do {\n while (1) {\n v11 = *v3;\n if (((*v7)[**v3] & 2048) == 0) break;\n ++v3;\n ++v6;\n v8 = a3 + strtol(v11, 0LL, 10);\n v9 = (int)(__snprintf_chk(0LL, 0LL, 2LL, -1LL, &unk_2004, v8) + 1);\n v10 = malloc(v9);\n *(v6 - 1) = v10;\n __sprintf_chk(v10, 2LL, v9, &unk_2004, v8);\n if (v5 == v3) return v14;\n }\n ++v3;\n *v6++ = strdup(v11);\n } while (v5 != v3);\n }\n return v14;\n}", + "ida_pseudo_norm": "void *func0(const char **a1, int a2, int a3) {\n const char **v3;\n void *v4;\n const char **v5;\n uint64_t *v6;\n const unsigned short **v7;\n unsigned int v8;\n unsigned int v9;\n void *v10;\n const char *v11;\n void *v14;\n v3 = a1;\n v4 = malloc(8LL * a2);\n v14 = v4;\n if (a2 > 0) {\n v5 = &a1[a2];\n v6 = v4;\n v7 = __ctype_b_loc();\n do {\n while (1) {\n v11 = *v3;\n if (((*v7)[**v3] & 2048) == 0) break;\n ++v3;\n ++v6;\n v8 = a3 + strtol(v11, 0LL, 10);\n v9 = (int)(__snprintf_chk(0LL, 0LL, 2LL, -1LL, &unk_2004, v8) + 1);\n v10 = malloc(v9);\n *(v6 - 1) = v10;\n __sprintf_chk(v10, 2LL, v9, &unk_2004, v8);\n if (v5 == v3) return v14;\n }\n ++v3;\n *v6++ = strdup(v11);\n } while (v5 != v3);\n }\n return v14;\n}" + }, + { + "index": 622, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "float func0(int arr1[], int arr2[], int n) {\n int i = 0;\n int j = 0;\n int m1 = -1;\n int m2 = -1;\n int count = 0;\n while (count < n + 1) {\n count++;\n if (i == n) {\n m1 = m2;\n m2 = arr2[0];\n break;\n } else if (j == n) {\n m1 = m2;\n m2 = arr1[0];\n break;\n }\n if (arr1[i] <= arr2[j]) {\n m1 = m2;\n m2 = arr1[i];\n i++;\n } else {\n m1 = m2;\n m2 = arr2[j];\n j++;\n }\n }\n return (m1 + m2) / 2.0;\n}", + "test": "int main() {\n\n int arr1_1[] = {1, 12, 15, 26, 38};\n\n int arr2_1[] = {2, 13, 17, 30, 45};\n\n int arr1_2[] = {2, 4, 8, 9};\n\n int arr2_2[] = {7, 13, 19, 28};\n\n int arr1_3[] = {3, 6, 14, 23, 36, 42};\n\n int arr2_3[] = {2, 18, 27, 39, 49, 55};\n\n\n\n assert(func0(arr1_1, arr2_1, 5) == 16.0);\n\n assert(func0(arr1_2, arr2_2, 4) == 8.5);\n\n assert(func0(arr1_3, arr2_3, 6) == 25.0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x28(%rbp)\nmov %rsi,-0x30(%rbp)\nmov %edx,-0x34(%rbp)\nmovl $0x0,-0x14(%rbp)\nmovl $0x0,-0x10(%rbp)\nmovl $0xffffffff,-0xc(%rbp)\nmovl $0xffffffff,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmpq 1258 \naddl $0x1,-0x4(%rbp)\nmov -0x14(%rbp),%eax\ncmp -0x34(%rbp),%eax\njne 11c4 \nmov -0x8(%rbp),%eax\nmov %eax,-0xc(%rbp)\nmov -0x30(%rbp),%rax\nmov (%rax),%eax\nmov %eax,-0x8(%rbp)\njmpq 1264 \nmov -0x10(%rbp),%eax\ncmp -0x34(%rbp),%eax\njne 11e0 \nmov -0x8(%rbp),%eax\nmov %eax,-0xc(%rbp)\nmov -0x28(%rbp),%rax\nmov (%rax),%eax\nmov %eax,-0x8(%rbp)\njmpq 1264 \nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x30(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njg 1235 \nmov -0x8(%rbp),%eax\nmov %eax,-0xc(%rbp)\nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x8(%rbp)\naddl $0x1,-0x14(%rbp)\njmp 1258 \nmov -0x8(%rbp),%eax\nmov %eax,-0xc(%rbp)\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x30(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x8(%rbp)\naddl $0x1,-0x10(%rbp)\nmov -0x34(%rbp),%eax\ncmp -0x4(%rbp),%eax\njge 11a4 \nmov -0xc(%rbp),%edx\nmov -0x8(%rbp),%eax\nadd %edx,%eax\ncvtsi2sd %eax,%xmm0\nmovsd 0xe40(%rip),%xmm1\ndivsd %xmm1,%xmm0\ncvtsd2ss %xmm0,%xmm0\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_30], rsi\nmov [rbp+var_34], edx\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0FFFFFFFFh\nmov [rbp+var_8], 0FFFFFFFFh\nmov [rbp+var_4], 0\njmp loc_1258\nloc_11A4:\nadd [rbp+var_4], 1\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_34]\njnz short loc_11C4\nmov eax, [rbp+var_8]\nmov [rbp+var_C], eax\nmov rax, [rbp+var_30]\nmov eax, [rax]\nmov [rbp+var_8], eax\njmp loc_1264\nloc_11C4:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_34]\njnz short loc_11E0\nmov eax, [rbp+var_8]\nmov [rbp+var_C], eax\nmov rax, [rbp+var_28]\nmov eax, [rax]\nmov [rbp+var_8], eax\njmp loc_1264\nloc_11E0:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_30]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njg short loc_1235\nmov eax, [rbp+var_8]\nmov [rbp+var_C], eax\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_8], eax\nadd [rbp+var_14], 1\njmp short loc_1258\nloc_1235:\nmov eax, [rbp+var_8]\nmov [rbp+var_C], eax\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_8], eax\nadd [rbp+var_10], 1\nloc_1258:\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_4]\njge loc_11A4\nloc_1264:\nmov edx, [rbp+var_C]\nmov eax, [rbp+var_8]\nadd eax, edx\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmovsd xmm1, cs:qword_2098\ndivsd xmm0, xmm1\ncvtsd2ss xmm0, xmm0\npop rbp\nretn", + "ida_pseudo": "float __fastcall func0(int *a1, int *a2, int a3)\n{\n int v4; // [rsp+20h] [rbp-14h]\n int v5; // [rsp+24h] [rbp-10h]\n int v6; // [rsp+28h] [rbp-Ch]\n int v7; // [rsp+2Ch] [rbp-8h]\n int v8; // [rsp+30h] [rbp-4h]\n\n v4 = 0;\n v5 = 0;\n v6 = -1;\n v7 = -1;\n v8 = 0;\n while ( a3 >= v8 )\n {\n ++v8;\n if ( v4 == a3 )\n {\n v6 = v7;\n v7 = *a2;\n return (double)(v6 + v7) / 2.0;\n }\n if ( v5 == a3 )\n {\n v6 = v7;\n v7 = *a1;\n return (double)(v6 + v7) / 2.0;\n }\n v6 = v7;\n if ( a1[v4] > a2[v5] )\n v7 = a2[v5++];\n else\n v7 = a1[v4++];\n }\n return (double)(v6 + v7) / 2.0;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_30], rsi\nmov [rbp+var_34], edx\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0FFFFFFFFh\nmov [rbp+var_8], 0FFFFFFFFh\nmov [rbp+var_4], 0\njmp loc_1258\nloc_11A4:\nadd [rbp+var_4], 1\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_34]\njnz short loc_11C4\nmov eax, [rbp+var_8]\nmov [rbp+var_C], eax\nmov rax, [rbp+var_30]\nmov eax, [rax]\nmov [rbp+var_8], eax\njmp loc_1264\nloc_11C4:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_34]\njnz short loc_11E0\nmov eax, [rbp+var_8]\nmov [rbp+var_C], eax\nmov rax, [rbp+var_28]\nmov eax, [rax]\nmov [rbp+var_8], eax\njmp loc_1264\nloc_11E0:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_30]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njg short loc_1235\nmov eax, [rbp+var_8]\nmov [rbp+var_C], eax\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_8], eax\nadd [rbp+var_14], 1\njmp short loc_1258\nloc_1235:\nmov eax, [rbp+var_8]\nmov [rbp+var_C], eax\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_8], eax\nadd [rbp+var_10], 1\nloc_1258:\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_4]\njge loc_11A4\nloc_1264:\nmov edx, [rbp+var_C]\nmov eax, [rbp+var_8]\nadd eax, edx\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmovsd xmm1, cs:qword_2098\ndivsd xmm0, xmm1\ncvtsd2ss xmm0, xmm0\npop rbp\nretn", + "ida_strip_pseudo": "float __fastcall sub_1169(int *a1, int *a2, int a3)\n{\n int v4; // [rsp+20h] [rbp-14h]\n int v5; // [rsp+24h] [rbp-10h]\n int v6; // [rsp+28h] [rbp-Ch]\n int v7; // [rsp+2Ch] [rbp-8h]\n int v8; // [rsp+30h] [rbp-4h]\n\n v4 = 0;\n v5 = 0;\n v6 = -1;\n v7 = -1;\n v8 = 0;\n while ( a3 >= v8 )\n {\n ++v8;\n if ( v4 == a3 )\n {\n v6 = v7;\n v7 = *a2;\n return (double)(v6 + v7) / 2.0;\n }\n if ( v5 == a3 )\n {\n v6 = v7;\n v7 = *a1;\n return (double)(v6 + v7) / 2.0;\n }\n v6 = v7;\n if ( a1[v4] > a2[v5] )\n v7 = a2[v5++];\n else\n v7 = a1[v4++];\n }\n return (double)(v6 + v7) / 2.0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "float sub_1169(int *a1, int *a2, int a3) {\n int v4;\n int v5;\n int v6;\n int v7;\n int v8;\n v4 = 0;\n v5 = 0;\n v6 = -1;\n v7 = -1;\n v8 = 0;\n while (a3 >= v8) {\n ++v8;\n if (v4 == a3) {\n v6 = v7;\n v7 = *a2;\n return (double)(v6 + v7) / 2.0;\n }\n if (v5 == a3) {\n v6 = v7;\n v7 = *a1;\n return (double)(v6 + v7) / 2.0;\n }\n v6 = v7;\n if (a1[v4] > a2[v5])\n v7 = a2[v5++];\n else\n v7 = a1[v4++];\n }\n return (double)(v6 + v7) / 2.0;\n}", + "ida_pseudo_norm": "float func0(int *a1, int *a2, int a3) {\n int v4;\n int v5;\n int v6;\n int v7;\n int v8;\n v4 = 0;\n v5 = 0;\n v6 = -1;\n v7 = -1;\n v8 = 0;\n while (a3 >= v8) {\n ++v8;\n if (v4 == a3) {\n v6 = v7;\n v7 = *a2;\n return (double)(v6 + v7) / 2.0;\n }\n if (v5 == a3) {\n v6 = v7;\n v7 = *a1;\n return (double)(v6 + v7) / 2.0;\n }\n v6 = v7;\n if (a1[v4] > a2[v5])\n v7 = a2[v5++];\n else\n v7 = a1[v4++];\n }\n return (double)(v6 + v7) / 2.0;\n}" + }, + { + "index": 622, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "float func0(int arr1[], int arr2[], int n) {\n int i = 0;\n int j = 0;\n int m1 = -1;\n int m2 = -1;\n int count = 0;\n while (count < n + 1) {\n count++;\n if (i == n) {\n m1 = m2;\n m2 = arr2[0];\n break;\n } else if (j == n) {\n m1 = m2;\n m2 = arr1[0];\n break;\n }\n if (arr1[i] <= arr2[j]) {\n m1 = m2;\n m2 = arr1[i];\n i++;\n } else {\n m1 = m2;\n m2 = arr2[j];\n j++;\n }\n }\n return (m1 + m2) / 2.0;\n}", + "test": "int main() {\n\n int arr1_1[] = {1, 12, 15, 26, 38};\n\n int arr2_1[] = {2, 13, 17, 30, 45};\n\n int arr1_2[] = {2, 4, 8, 9};\n\n int arr2_2[] = {7, 13, 19, 28};\n\n int arr1_3[] = {3, 6, 14, 23, 36, 42};\n\n int arr2_3[] = {2, 18, 27, 39, 49, 55};\n\n\n\n assert(func0(arr1_1, arr2_1, 5) == 16.0);\n\n assert(func0(arr1_2, arr2_2, 4) == 8.5);\n\n assert(func0(arr1_3, arr2_3, 6) == 25.0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edx,%edx\njs 11e8 \nje 118c \nmov $0x1,%r9d\nmov $0xffffffff,%r11d\nmov $0x0,%r8d\nmov $0x0,%ecx\njmp 11ce \nmov $0xffffffff,%eax\nmov %eax,%r11d\nmov (%rsi),%eax\nadd %r11d,%eax\npxor %xmm0,%xmm0\ncvtsi2sd %eax,%xmm0\nmulsd 0xf0f(%rip),%xmm0\ncvtsd2ss %xmm0,%xmm0\nretq\nmov %eax,%r11d\nmov (%rdi),%eax\njmp 1196 \nadd $0x1,%r8d\ncmp %r9d,%edx\njl 1196 \nadd $0x1,%r9d\ncmp %edx,%ecx\nje 1191 \ncmp %edx,%r8d\nje 11ae \nmov %eax,%r11d\nmovslq %ecx,%rax\nmov (%rdi,%rax,4),%r10d\nmovslq %r8d,%rax\nmov (%rsi,%rax,4),%eax\ncmp %eax,%r10d\njg 11b5 \nadd $0x1,%ecx\nmov %r10d,%eax\njmp 11b9 \nmov $0xffffffff,%eax\nmov $0xffffffff,%r11d\njmp 1196 \n", + "ida_asm": "func0:\nendbr64\ntest edx, edx\njs short loc_11E9\njz short loc_118C\nmov r9d, 1\nmov r11d, 0FFFFFFFFh\nmov r8d, 0\nmov ecx, 0\njmp short loc_11CF\nloc_118C:\nmov eax, 0FFFFFFFFh\nloc_1191:\nmov r11d, eax\nmov eax, [rsi]\nloc_1196:\nadd r11d, eax\npxor xmm0, xmm0\ncvtsi2sd xmm0, r11d\nmulsd xmm0, cs:qword_20A0\ncvtsd2ss xmm0, xmm0\nretn\nloc_11AF:\nmov r11d, eax\nmov eax, [rdi]\njmp short loc_1196\nloc_11B6:\nadd r8d, 1\nloc_11BA:\ncmp edx, r9d\njl short loc_1196\nadd r9d, 1\ncmp ecx, edx\njz short loc_1191\ncmp r8d, edx\njz short loc_11AF\nmov r11d, eax\nloc_11CF:\nmovsxd rax, ecx\nmov r10d, [rdi+rax*4]\nmovsxd rax, r8d\nmov eax, [rsi+rax*4]\ncmp r10d, eax\njg short loc_11B6\nadd ecx, 1\nmov eax, r10d\njmp short loc_11BA\nloc_11E9:\nmov eax, 0FFFFFFFFh\nmov r11d, 0FFFFFFFFh\njmp short loc_1196", + "ida_pseudo": "float __fastcall func0(int *a1, int *a2, int a3)\n{\n int v3; // r9d\n int v4; // r11d\n int v5; // r8d\n int v6; // ecx\n int v7; // eax\n int v9; // r10d\n\n if ( a3 < 0 )\n {\n v7 = -1;\n v4 = -1;\n }\n else if ( a3 )\n {\n v3 = 1;\n v4 = -1;\n v5 = 0;\n v6 = 0;\n while ( 1 )\n {\n v9 = a1[v6];\n v7 = a2[v5];\n if ( v9 > v7 )\n {\n ++v5;\n }\n else\n {\n ++v6;\n v7 = v9;\n }\n if ( a3 < v3 )\n break;\n ++v3;\n if ( v6 == a3 )\n goto LABEL_5;\n if ( v5 == a3 )\n {\n v4 = v7;\n v7 = *a1;\n return (double)(v7 + v4) * 0.5;\n }\n v4 = v7;\n }\n }\n else\n {\n v7 = -1;\nLABEL_5:\n v4 = v7;\n v7 = *a2;\n }\n return (double)(v7 + v4) * 0.5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest edx, edx\njs short loc_11E9\njz short loc_118C\nmov r9d, 1\nmov r11d, 0FFFFFFFFh\nmov r8d, 0\nmov ecx, 0\njmp short loc_11CF\nloc_118C:\nmov eax, 0FFFFFFFFh\nloc_1191:\nmov r11d, eax\nmov eax, [rsi]\nloc_1196:\nadd r11d, eax\npxor xmm0, xmm0\ncvtsi2sd xmm0, r11d\nmulsd xmm0, cs:qword_20A0\ncvtsd2ss xmm0, xmm0\nretn\nloc_11AF:\nmov r11d, eax\nmov eax, [rdi]\njmp short loc_1196\nloc_11B6:\nadd r8d, 1\nloc_11BA:\ncmp edx, r9d\njl short loc_1196\nadd r9d, 1\ncmp ecx, edx\njz short loc_1191\ncmp r8d, edx\njz short loc_11AF\nmov r11d, eax\nloc_11CF:\nmovsxd rax, ecx\nmov r10d, [rdi+rax*4]\nmovsxd rax, r8d\nmov eax, [rsi+rax*4]\ncmp r10d, eax\njg short loc_11B6\nadd ecx, 1\nmov eax, r10d\njmp short loc_11BA\nloc_11E9:\nmov eax, 0FFFFFFFFh\nmov r11d, 0FFFFFFFFh\njmp short loc_1196", + "ida_strip_pseudo": "float __fastcall sub_1169(int *a1, int *a2, int a3)\n{\n int v3; // r9d\n int v4; // r11d\n int v5; // r8d\n int v6; // ecx\n int v7; // eax\n int v9; // r10d\n\n if ( a3 < 0 )\n {\n v7 = -1;\n v4 = -1;\n }\n else if ( a3 )\n {\n v3 = 1;\n v4 = -1;\n v5 = 0;\n v6 = 0;\n while ( 1 )\n {\n v9 = a1[v6];\n v7 = a2[v5];\n if ( v9 > v7 )\n {\n ++v5;\n }\n else\n {\n ++v6;\n v7 = v9;\n }\n if ( a3 < v3 )\n break;\n ++v3;\n if ( v6 == a3 )\n goto LABEL_5;\n if ( v5 == a3 )\n {\n v4 = v7;\n v7 = *a1;\n return (double)(v7 + v4) * 0.5;\n }\n v4 = v7;\n }\n }\n else\n {\n v7 = -1;\nLABEL_5:\n v4 = v7;\n v7 = *a2;\n }\n return (double)(v7 + v4) * 0.5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "float sub_1169(int *a1, int *a2, int a3) {\n int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n int v9;\n if (a3 < 0) {\n v7 = -1;\n v4 = -1;\n } else if (a3) {\n v3 = 1;\n v4 = -1;\n v5 = 0;\n v6 = 0;\n while (1) {\n v9 = a1[v6];\n v7 = a2[v5];\n if (v9 > v7) {\n ++v5;\n } else {\n ++v6;\n v7 = v9;\n }\n if (a3 < v3) break;\n ++v3;\n if (v6 == a3) goto LABEL_5;\n if (v5 == a3) {\n v4 = v7;\n v7 = *a1;\n return (double)(v7 + v4) * 0.5;\n }\n v4 = v7;\n }\n } else {\n v7 = -1;\n LABEL_5:\n v4 = v7;\n v7 = *a2;\n }\n return (double)(v7 + v4) * 0.5;\n}", + "ida_pseudo_norm": "float func0(int *a1, int *a2, int a3) {\n int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n int v9;\n if (a3 < 0) {\n v7 = -1;\n v4 = -1;\n } else if (a3) {\n v3 = 1;\n v4 = -1;\n v5 = 0;\n v6 = 0;\n while (1) {\n v9 = a1[v6];\n v7 = a2[v5];\n if (v9 > v7) {\n ++v5;\n } else {\n ++v6;\n v7 = v9;\n }\n if (a3 < v3) break;\n ++v3;\n if (v6 == a3) goto LABEL_5;\n if (v5 == a3) {\n v4 = v7;\n v7 = *a1;\n return (double)(v7 + v4) * 0.5;\n }\n v4 = v7;\n }\n } else {\n v7 = -1;\n LABEL_5:\n v4 = v7;\n v7 = *a2;\n }\n return (double)(v7 + v4) * 0.5;\n}" + }, + { + "index": 622, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "float func0(int arr1[], int arr2[], int n) {\n int i = 0;\n int j = 0;\n int m1 = -1;\n int m2 = -1;\n int count = 0;\n while (count < n + 1) {\n count++;\n if (i == n) {\n m1 = m2;\n m2 = arr2[0];\n break;\n } else if (j == n) {\n m1 = m2;\n m2 = arr1[0];\n break;\n }\n if (arr1[i] <= arr2[j]) {\n m1 = m2;\n m2 = arr1[i];\n i++;\n } else {\n m1 = m2;\n m2 = arr2[j];\n j++;\n }\n }\n return (m1 + m2) / 2.0;\n}", + "test": "int main() {\n\n int arr1_1[] = {1, 12, 15, 26, 38};\n\n int arr2_1[] = {2, 13, 17, 30, 45};\n\n int arr1_2[] = {2, 4, 8, 9};\n\n int arr2_2[] = {7, 13, 19, 28};\n\n int arr1_3[] = {3, 6, 14, 23, 36, 42};\n\n int arr2_3[] = {2, 18, 27, 39, 49, 55};\n\n\n\n assert(func0(arr1_1, arr2_1, 5) == 16.0);\n\n assert(func0(arr1_2, arr2_2, 4) == 8.5);\n\n assert(func0(arr1_3, arr2_3, 6) == 25.0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %edx,%edx\njs 140f \nje 13d7 \nmov $0x1,%r9d\nmov $0xffffffff,%r11d\nxor %r8d,%r8d\nxor %ecx,%ecx\njmp 13a0 \nnopl 0x0(%rax)\nadd $0x1,%ecx\ncmp %r9d,%edx\njl 13bf \nadd $0x1,%r9d\ncmp %edx,%ecx\nje 13dc \ncmp %edx,%r8d\nje 13f8 \nmov %eax,%r11d\nmovslq %ecx,%r10\nmov (%rdi,%r10,4),%eax\nmovslq %r8d,%r10\nmov (%rsi,%r10,4),%r10d\ncmp %r10d,%eax\njle 1388 \nadd $0x1,%r8d\nmov %r10d,%eax\ncmp %r9d,%edx\njge 1390 \nadd %r11d,%eax\npxor %xmm0,%xmm0\ncvtsi2sd %eax,%xmm0\nmulsd 0xcf6(%rip),%xmm0\ncvtsd2ss %xmm0,%xmm0\nretq\nmov $0xffffffff,%eax\nadd (%rsi),%eax\npxor %xmm0,%xmm0\ncvtsi2sd %eax,%xmm0\nmulsd 0xcda(%rip),%xmm0\ncvtsd2ss %xmm0,%xmm0\nretq\nnopl 0x0(%rax,%rax,1)\nadd (%rdi),%eax\npxor %xmm0,%xmm0\ncvtsi2sd %eax,%xmm0\nmulsd 0xcbe(%rip),%xmm0\ncvtsd2ss %xmm0,%xmm0\nretq\nmovss 0xca1(%rip),%xmm0\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest edx, edx\njs loc_139F\njz short loc_1366\nmov r9d, 1\nmov r11d, 0FFFFFFFFh\nxor r8d, r8d\nxor ecx, ecx\njmp short loc_1330\nloc_1318:\nadd ecx, 1\ncmp edx, r9d\njl short loc_134E\nloc_1320:\nadd r9d, 1\ncmp ecx, edx\njz short loc_136B\ncmp edx, r8d\njz short loc_1388\nmov r11d, eax\nloc_1330:\nmovsxd rax, ecx\nmovsxd r10, r8d\nmov eax, [rdi+rax*4]\nmov r10d, [rsi+r10*4]\ncmp eax, r10d\njle short loc_1318\nadd r8d, 1\nmov eax, r10d\ncmp edx, r9d\njge short loc_1320\nloc_134E:\nadd eax, r11d\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmulsd xmm0, cs:qword_20A8\ncvtsd2ss xmm0, xmm0\nretn\nloc_1366:\nmov eax, 0FFFFFFFFh\nloc_136B:\nadd eax, [rsi]\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmulsd xmm0, cs:qword_20A8\ncvtsd2ss xmm0, xmm0\nretn\nloc_1388:\nadd eax, [rdi]\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmulsd xmm0, cs:qword_20A8\ncvtsd2ss xmm0, xmm0\nretn\nloc_139F:\nmovss xmm0, cs:dword_2004\nretn", + "ida_pseudo": "float __fastcall func0(_DWORD *a1, _DWORD *a2, int a3)\n{\n int v3; // r9d\n int v4; // r11d\n int v5; // r8d\n int v6; // ecx\n int v7; // eax\n int v8; // r10d\n\n if ( a3 < 0 )\n return -1.0;\n if ( a3 )\n {\n v3 = 1;\n v4 = -1;\n v5 = 0;\n v6 = 0;\n while ( 1 )\n {\n v7 = a1[v6];\n v8 = a2[v5];\n if ( v7 <= v8 )\n {\n ++v6;\n if ( a3 < v3 )\n return (double)(v4 + v7) * 0.5;\n }\n else\n {\n ++v5;\n v7 = v8;\n if ( a3 < v3 )\n return (double)(v4 + v7) * 0.5;\n }\n ++v3;\n if ( v6 == a3 )\n return (double)(*a2 + v7) * 0.5;\n if ( a3 == v5 )\n break;\n v4 = v7;\n }\n return (double)(*a1 + v7) * 0.5;\n }\n else\n {\n v7 = -1;\n return (double)(*a2 + v7) * 0.5;\n }\n}", + "ida_strip_asm": "sub_12F0:\nendbr64\ntest edx, edx\njs loc_139F\njz short loc_1366\nmov r9d, 1\nmov r11d, 0FFFFFFFFh\nxor r8d, r8d\nxor ecx, ecx\njmp short loc_1330\nloc_1318:\nadd ecx, 1\ncmp edx, r9d\njl short loc_134E\nloc_1320:\nadd r9d, 1\ncmp ecx, edx\njz short loc_136B\ncmp edx, r8d\njz short loc_1388\nmov r11d, eax\nloc_1330:\nmovsxd rax, ecx\nmovsxd r10, r8d\nmov eax, [rdi+rax*4]\nmov r10d, [rsi+r10*4]\ncmp eax, r10d\njle short loc_1318\nadd r8d, 1\nmov eax, r10d\ncmp edx, r9d\njge short loc_1320\nloc_134E:\nadd eax, r11d\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmulsd xmm0, cs:qword_20A8\ncvtsd2ss xmm0, xmm0\nretn\nloc_1366:\nmov eax, 0FFFFFFFFh\nloc_136B:\nadd eax, [rsi]\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmulsd xmm0, cs:qword_20A8\ncvtsd2ss xmm0, xmm0\nretn\nloc_1388:\nadd eax, [rdi]\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmulsd xmm0, cs:qword_20A8\ncvtsd2ss xmm0, xmm0\nretn\nloc_139F:\nmovss xmm0, cs:dword_2004\nretn", + "ida_strip_pseudo": "float __fastcall sub_12F0(_DWORD *a1, _DWORD *a2, int a3)\n{\n int v3; // r9d\n int v4; // r11d\n int v5; // r8d\n int v6; // ecx\n int v7; // eax\n int v8; // r10d\n\n if ( a3 < 0 )\n return -1.0;\n if ( a3 )\n {\n v3 = 1;\n v4 = -1;\n v5 = 0;\n v6 = 0;\n while ( 1 )\n {\n v7 = a1[v6];\n v8 = a2[v5];\n if ( v7 <= v8 )\n {\n ++v6;\n if ( a3 < v3 )\n return (double)(v4 + v7) * 0.5;\n }\n else\n {\n ++v5;\n v7 = v8;\n if ( a3 < v3 )\n return (double)(v4 + v7) * 0.5;\n }\n ++v3;\n if ( v6 == a3 )\n return (double)(*a2 + v7) * 0.5;\n if ( a3 == v5 )\n break;\n v4 = v7;\n }\n return (double)(*a1 + v7) * 0.5;\n }\n else\n {\n v7 = -1;\n return (double)(*a2 + v7) * 0.5;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "float sub_12F0(uint32_t *a1, uint32_t *a2, int a3) {\n int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n int v8;\n if (a3 < 0) return -1.0;\n if (a3) {\n v3 = 1;\n v4 = -1;\n v5 = 0;\n v6 = 0;\n while (1) {\n v7 = a1[v6];\n v8 = a2[v5];\n if (v7 <= v8) {\n ++v6;\n if (a3 < v3) return (double)(v4 + v7) * 0.5;\n } else {\n ++v5;\n v7 = v8;\n if (a3 < v3) return (double)(v4 + v7) * 0.5;\n }\n ++v3;\n if (v6 == a3) return (double)(*a2 + v7) * 0.5;\n if (a3 == v5) break;\n v4 = v7;\n }\n return (double)(*a1 + v7) * 0.5;\n } else {\n v7 = -1;\n return (double)(*a2 + v7) * 0.5;\n }\n}", + "ida_pseudo_norm": "float func0(uint32_t *a1, uint32_t *a2, int a3) {\n int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n int v8;\n if (a3 < 0) return -1.0;\n if (a3) {\n v3 = 1;\n v4 = -1;\n v5 = 0;\n v6 = 0;\n while (1) {\n v7 = a1[v6];\n v8 = a2[v5];\n if (v7 <= v8) {\n ++v6;\n if (a3 < v3) return (double)(v4 + v7) * 0.5;\n } else {\n ++v5;\n v7 = v8;\n if (a3 < v3) return (double)(v4 + v7) * 0.5;\n }\n ++v3;\n if (v6 == a3) return (double)(*a2 + v7) * 0.5;\n if (a3 == v5) break;\n v4 = v7;\n }\n return (double)(*a1 + v7) * 0.5;\n } else {\n v7 = -1;\n return (double)(*a2 + v7) * 0.5;\n }\n}" + }, + { + "index": 622, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "float func0(int arr1[], int arr2[], int n) {\n int i = 0;\n int j = 0;\n int m1 = -1;\n int m2 = -1;\n int count = 0;\n while (count < n + 1) {\n count++;\n if (i == n) {\n m1 = m2;\n m2 = arr2[0];\n break;\n } else if (j == n) {\n m1 = m2;\n m2 = arr1[0];\n break;\n }\n if (arr1[i] <= arr2[j]) {\n m1 = m2;\n m2 = arr1[i];\n i++;\n } else {\n m1 = m2;\n m2 = arr2[j];\n j++;\n }\n }\n return (m1 + m2) / 2.0;\n}", + "test": "int main() {\n\n int arr1_1[] = {1, 12, 15, 26, 38};\n\n int arr2_1[] = {2, 13, 17, 30, 45};\n\n int arr1_2[] = {2, 4, 8, 9};\n\n int arr2_2[] = {7, 13, 19, 28};\n\n int arr1_3[] = {3, 6, 14, 23, 36, 42};\n\n int arr2_3[] = {2, 18, 27, 39, 49, 55};\n\n\n\n assert(func0(arr1_1, arr2_1, 5) == 16.0);\n\n assert(func0(arr1_2, arr2_2, 4) == 8.5);\n\n assert(func0(arr1_3, arr2_3, 6) == 25.0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ntest %edx,%edx\njs 13af \nje 1377 \nmov $0x1,%r9d\nmov $0xffffffff,%r11d\nxor %r8d,%r8d\nxor %ecx,%ecx\njmp 1340 \nnopl 0x0(%rax)\nadd $0x1,%ecx\ncmp %r9d,%edx\njl 135f \nadd $0x1,%r9d\ncmp %edx,%ecx\nje 137c \ncmp %edx,%r8d\nje 1398 \nmov %eax,%r11d\nmovslq %ecx,%r10\nmov (%rdi,%r10,4),%eax\nmovslq %r8d,%r10\nmov (%rsi,%r10,4),%r10d\ncmp %r10d,%eax\njle 1328 \nadd $0x1,%r8d\nmov %r10d,%eax\ncmp %r9d,%edx\njge 1330 \nadd %r11d,%eax\npxor %xmm0,%xmm0\ncvtsi2sd %eax,%xmm0\nmulsd 0xd56(%rip),%xmm0\ncvtsd2ss %xmm0,%xmm0\nretq\nmov $0xffffffff,%eax\nadd (%rsi),%eax\npxor %xmm0,%xmm0\ncvtsi2sd %eax,%xmm0\nmulsd 0xd3a(%rip),%xmm0\ncvtsd2ss %xmm0,%xmm0\nretq\nnopl 0x0(%rax,%rax,1)\nadd (%rdi),%eax\npxor %xmm0,%xmm0\ncvtsi2sd %eax,%xmm0\nmulsd 0xd1e(%rip),%xmm0\ncvtsd2ss %xmm0,%xmm0\nretq\nmovss 0xd01(%rip),%xmm0\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest edx, edx\njs loc_139F\njz short loc_1366\nmov r9d, 1\nmov r11d, 0FFFFFFFFh\nxor r8d, r8d\nxor ecx, ecx\njmp short loc_1330\nloc_1318:\nadd ecx, 1\ncmp edx, r9d\njl short loc_134E\nloc_1320:\nadd r9d, 1\ncmp ecx, edx\njz short loc_136B\ncmp edx, r8d\njz short loc_1388\nmov r11d, eax\nloc_1330:\nmovsxd rax, ecx\nmovsxd r10, r8d\nmov eax, [rdi+rax*4]\nmov r10d, [rsi+r10*4]\ncmp eax, r10d\njle short loc_1318\nadd r8d, 1\nmov eax, r10d\ncmp edx, r9d\njge short loc_1320\nloc_134E:\nadd eax, r11d\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmulsd xmm0, cs:qword_20A8\ncvtsd2ss xmm0, xmm0\nretn\nloc_1366:\nmov eax, 0FFFFFFFFh\nloc_136B:\nadd eax, [rsi]\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmulsd xmm0, cs:qword_20A8\ncvtsd2ss xmm0, xmm0\nretn\nloc_1388:\nadd eax, [rdi]\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmulsd xmm0, cs:qword_20A8\ncvtsd2ss xmm0, xmm0\nretn\nloc_139F:\nmovss xmm0, cs:dword_2004\nretn", + "ida_pseudo": "float __fastcall func0(_DWORD *a1, _DWORD *a2, int a3)\n{\n int v3; // r9d\n int v4; // r11d\n int v5; // r8d\n int v6; // ecx\n int v7; // eax\n int v8; // r10d\n\n if ( a3 < 0 )\n return -1.0;\n if ( a3 )\n {\n v3 = 1;\n v4 = -1;\n v5 = 0;\n v6 = 0;\n while ( 1 )\n {\n v7 = a1[v6];\n v8 = a2[v5];\n if ( v7 <= v8 )\n {\n ++v6;\n if ( a3 < v3 )\n return (double)(v4 + v7) * 0.5;\n }\n else\n {\n ++v5;\n v7 = v8;\n if ( a3 < v3 )\n return (double)(v4 + v7) * 0.5;\n }\n ++v3;\n if ( v6 == a3 )\n return (double)(*a2 + v7) * 0.5;\n if ( a3 == v5 )\n break;\n v4 = v7;\n }\n return (double)(*a1 + v7) * 0.5;\n }\n else\n {\n v7 = -1;\n return (double)(*a2 + v7) * 0.5;\n }\n}", + "ida_strip_asm": "sub_12F0:\nendbr64\ntest edx, edx\njs loc_139F\njz short loc_1366\nmov r9d, 1\nmov r11d, 0FFFFFFFFh\nxor r8d, r8d\nxor ecx, ecx\njmp short loc_1330\nloc_1318:\nadd ecx, 1\ncmp edx, r9d\njl short loc_134E\nloc_1320:\nadd r9d, 1\ncmp ecx, edx\njz short loc_136B\ncmp edx, r8d\njz short loc_1388\nmov r11d, eax\nloc_1330:\nmovsxd rax, ecx\nmovsxd r10, r8d\nmov eax, [rdi+rax*4]\nmov r10d, [rsi+r10*4]\ncmp eax, r10d\njle short loc_1318\nadd r8d, 1\nmov eax, r10d\ncmp edx, r9d\njge short loc_1320\nloc_134E:\nadd eax, r11d\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmulsd xmm0, cs:qword_20A8\ncvtsd2ss xmm0, xmm0\nretn\nloc_1366:\nmov eax, 0FFFFFFFFh\nloc_136B:\nadd eax, [rsi]\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmulsd xmm0, cs:qword_20A8\ncvtsd2ss xmm0, xmm0\nretn\nloc_1388:\nadd eax, [rdi]\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmulsd xmm0, cs:qword_20A8\ncvtsd2ss xmm0, xmm0\nretn\nloc_139F:\nmovss xmm0, cs:dword_2004\nretn", + "ida_strip_pseudo": "float __fastcall sub_12F0(_DWORD *a1, _DWORD *a2, int a3)\n{\n int v3; // r9d\n int v4; // r11d\n int v5; // r8d\n int v6; // ecx\n int v7; // eax\n int v8; // r10d\n\n if ( a3 < 0 )\n return -1.0;\n if ( a3 )\n {\n v3 = 1;\n v4 = -1;\n v5 = 0;\n v6 = 0;\n while ( 1 )\n {\n v7 = a1[v6];\n v8 = a2[v5];\n if ( v7 <= v8 )\n {\n ++v6;\n if ( a3 < v3 )\n return (double)(v4 + v7) * 0.5;\n }\n else\n {\n ++v5;\n v7 = v8;\n if ( a3 < v3 )\n return (double)(v4 + v7) * 0.5;\n }\n ++v3;\n if ( v6 == a3 )\n return (double)(*a2 + v7) * 0.5;\n if ( a3 == v5 )\n break;\n v4 = v7;\n }\n return (double)(*a1 + v7) * 0.5;\n }\n else\n {\n v7 = -1;\n return (double)(*a2 + v7) * 0.5;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "float sub_12F0(uint32_t *a1, uint32_t *a2, int a3) {\n int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n int v8;\n if (a3 < 0) return -1.0;\n if (a3) {\n v3 = 1;\n v4 = -1;\n v5 = 0;\n v6 = 0;\n while (1) {\n v7 = a1[v6];\n v8 = a2[v5];\n if (v7 <= v8) {\n ++v6;\n if (a3 < v3) return (double)(v4 + v7) * 0.5;\n } else {\n ++v5;\n v7 = v8;\n if (a3 < v3) return (double)(v4 + v7) * 0.5;\n }\n ++v3;\n if (v6 == a3) return (double)(*a2 + v7) * 0.5;\n if (a3 == v5) break;\n v4 = v7;\n }\n return (double)(*a1 + v7) * 0.5;\n } else {\n v7 = -1;\n return (double)(*a2 + v7) * 0.5;\n }\n}", + "ida_pseudo_norm": "float func0(uint32_t *a1, uint32_t *a2, int a3) {\n int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n int v8;\n if (a3 < 0) return -1.0;\n if (a3) {\n v3 = 1;\n v4 = -1;\n v5 = 0;\n v6 = 0;\n while (1) {\n v7 = a1[v6];\n v8 = a2[v5];\n if (v7 <= v8) {\n ++v6;\n if (a3 < v3) return (double)(v4 + v7) * 0.5;\n } else {\n ++v5;\n v7 = v8;\n if (a3 < v3) return (double)(v4 + v7) * 0.5;\n }\n ++v3;\n if (v6 == a3) return (double)(*a2 + v7) * 0.5;\n if (a3 == v5) break;\n v4 = v7;\n }\n return (double)(*a1 + v7) * 0.5;\n } else {\n v7 = -1;\n return (double)(*a2 + v7) * 0.5;\n }\n}" + }, + { + "index": 623, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include // For pow function\n\n\n\n", + "func": "void func0(int nums[], int length, int n, int result[]) {\n for (int i = 0; i < length; i++) {\n result[i] = pow(nums[i], n);\n }\n}", + "test": "int main() {\n\n int result1[10], result2[3], result3[2];\n\n int arr1[10] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n int arr2[3] = {10, 20, 30};\n\n int arr3[2] = {12, 15};\n\n\n\n func0(arr1, 10, 2, result1);\n\n func0(arr2, 3, 3, result2);\n\n func0(arr3, 2, 5, result3);\n\n\n\n assert(result1[0] == 1 && result1[1] == 4 && result1[2] == 9 && result1[3] == 16 \n\n && result1[4] == 25 && result1[5] == 36 && result1[6] == 49 && result1[7] == 64\n\n && result1[8] == 81 && result1[9] == 100);\n\n\n\n assert(result2[0] == 1000 && result2[1] == 8000 && result2[2] == 27000);\n\n\n\n assert(result3[0] == 248832 && result3[1] == 759375);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmov %rcx,-0x28(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11ee \ncvtsi2sdl -0x20(%rbp),%xmm1\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncvtsi2sd %eax,%xmm0\ncallq 1070 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rax,%rdx\ncvttsd2si %xmm0,%eax\nmov %eax,(%rdx)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11ac \nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_28], rcx\nmov [rbp+var_4], 0\njmp short loc_1204\nloc_11AC:\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_20]\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\npxor xmm2, xmm2\ncvtsi2sd xmm2, eax\nmovq rax, xmm2\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rdx, rax\ncvttsd2si eax, xmm0\nmov [rdx], eax\nadd [rbp+var_4], 1\nloc_1204:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11AC\nnop\nnop\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3, __int64 a4)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+2Ch] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a2 )\n break;\n *(_DWORD *)(a4 + 4LL * (int)i) = (int)pow((double)*(int *)(4LL * (int)i + a1), (double)a3);\n }\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_28], rcx\nmov [rbp+var_4], 0\njmp short loc_1204\nloc_11AC:\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_20]\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\npxor xmm2, xmm2\ncvtsi2sd xmm2, eax\nmovq rax, xmm2\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rdx, rax\ncvttsd2si eax, xmm0\nmov [rdx], eax\nadd [rbp+var_4], 1\nloc_1204:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11AC\nnop\nnop\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2, int a3, __int64 a4)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+2Ch] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a2 )\n break;\n *(_DWORD *)(a4 + 4LL * (int)i) = (int)pow((double)*(int *)(4LL * (int)i + a1), (double)a3);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2, int a3, long long a4) {\n long long result;\n unsigned int i;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a2) break;\n *(uint32_t *)(a4 + 4LL * (int)i) =\n (int)pow((double)*(int *)(4LL * (int)i + a1), (double)a3);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3, long long a4) {\n long long result;\n unsigned int i;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a2) break;\n *(uint32_t *)(a4 + 4LL * (int)i) =\n (int)pow((double)*(int *)(4LL * (int)i + a1), (double)a3);\n }\n return result;\n}" + }, + { + "index": 623, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include // For pow function\n\n\n\n", + "func": "void func0(int nums[], int length, int n, int result[]) {\n for (int i = 0; i < length; i++) {\n result[i] = pow(nums[i], n);\n }\n}", + "test": "int main() {\n\n int result1[10], result2[3], result3[2];\n\n int arr1[10] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n int arr2[3] = {10, 20, 30};\n\n int arr3[2] = {12, 15};\n\n\n\n func0(arr1, 10, 2, result1);\n\n func0(arr2, 3, 3, result2);\n\n func0(arr3, 2, 5, result3);\n\n\n\n assert(result1[0] == 1 && result1[1] == 4 && result1[2] == 9 && result1[3] == 16 \n\n && result1[4] == 25 && result1[5] == 36 && result1[6] == 49 && result1[7] == 64\n\n && result1[8] == 81 && result1[9] == 100);\n\n\n\n assert(result2[0] == 1000 && result2[1] == 8000 && result2[2] == 27000);\n\n\n\n assert(result3[0] == 248832 && result3[1] == 759375);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11ec \npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov %rdi,%rbp\nmov %rcx,%r12\nlea -0x1(%rsi),%r13d\nmov $0x0,%ebx\npxor %xmm2,%xmm2\ncvtsi2sd %edx,%xmm2\nmovsd %xmm2,0x8(%rsp)\npxor %xmm0,%xmm0\ncvtsi2sdl 0x0(%rbp,%rbx,4),%xmm0\nmovsd 0x8(%rsp),%xmm1\ncallq 1070 \ncvttsd2si %xmm0,%eax\nmov %eax,(%r12,%rbx,4)\nmov %rbx,%rax\nadd $0x1,%rbx\ncmp %r13,%rax\njne 11b8 \nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short locret_11E6\npush r14\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov rbp, rcx\nmovsxd rsi, esi\nlea r12, [rdi+rsi*4]\npxor xmm2, xmm2\ncvtsi2sd xmm2, edx\nmovq r14, xmm2\nloc_11B5:\npxor xmm0, xmm0\ncvtsi2sd xmm0, dword ptr [rbx]; x\nmovq xmm1, r14; y\ncall _pow\ncvttsd2si eax, xmm0\nmov [rbp+0], eax\nadd rbx, 4\nadd rbp, 4\ncmp rbx, r12\njnz short loc_11B5\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r14\nretn\nlocret_11E6:\nretn", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2, int a3, _DWORD *a4)\n{\n int *v4; // rbx\n double v6; // r14\n __int64 result; // rax\n\n if ( a2 > 0 )\n {\n v4 = a1;\n v6 = (double)a3;\n do\n {\n result = (unsigned int)(int)pow((double)*v4, v6);\n *a4 = result;\n ++v4;\n ++a4;\n }\n while ( v4 != &a1[a2] );\n }\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\ntest esi, esi\njle short locret_11E6\npush r14\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov rbp, rcx\nmovsxd rsi, esi\nlea r12, [rdi+rsi*4]\npxor xmm2, xmm2\ncvtsi2sd xmm2, edx\nmovq r14, xmm2\nloc_11B5:\npxor xmm0, xmm0\ncvtsi2sd xmm0, dword ptr [rbx]; x\nmovq xmm1, r14; y\ncall _pow\ncvttsd2si eax, xmm0\nmov [rbp+0], eax\nadd rbx, 4\nadd rbp, 4\ncmp rbx, r12\njnz short loc_11B5\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r14\nretn\nlocret_11E6:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(int *a1, int a2, int a3, _DWORD *a4)\n{\n int *v4; // rbx\n double v6; // r14\n __int64 result; // rax\n\n if ( a2 > 0 )\n {\n v4 = a1;\n v6 = (double)a3;\n do\n {\n result = (unsigned int)(int)pow((double)*v4, v6);\n *a4 = result;\n ++v4;\n ++a4;\n }\n while ( v4 != &a1[a2] );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(int *a1, int a2, int a3, uint32_t *a4) {\n int *v4;\n double v6;\n long long result;\n if (a2 > 0) {\n v4 = a1;\n v6 = (double)a3;\n do {\n result = (unsigned int)(int)pow((double)*v4, v6);\n *a4 = result;\n ++v4;\n ++a4;\n } while (v4 != &a1[a2]);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2, int a3, uint32_t *a4) {\n int *v4;\n double v6;\n long long result;\n if (a2 > 0) {\n v4 = a1;\n v6 = (double)a3;\n do {\n result = (unsigned int)(int)pow((double)*v4, v6);\n *a4 = result;\n ++v4;\n ++a4;\n } while (v4 != &a1[a2]);\n }\n return result;\n}" + }, + { + "index": 623, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include // For pow function\n\n\n\n", + "func": "void func0(int nums[], int length, int n, int result[]) {\n for (int i = 0; i < length; i++) {\n result[i] = pow(nums[i], n);\n }\n}", + "test": "int main() {\n\n int result1[10], result2[3], result3[2];\n\n int arr1[10] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n int arr2[3] = {10, 20, 30};\n\n int arr3[2] = {12, 15};\n\n\n\n func0(arr1, 10, 2, result1);\n\n func0(arr2, 3, 3, result2);\n\n func0(arr3, 2, 5, result3);\n\n\n\n assert(result1[0] == 1 && result1[1] == 4 && result1[2] == 9 && result1[3] == 16 \n\n && result1[4] == 25 && result1[5] == 36 && result1[6] == 49 && result1[7] == 64\n\n && result1[8] == 81 && result1[9] == 100);\n\n\n\n assert(result2[0] == 1000 && result2[1] == 8000 && result2[2] == 27000);\n\n\n\n assert(result3[0] == 248832 && result3[1] == 759375);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 13e0 \npxor %xmm1,%xmm1\npush %r13\nlea -0x1(%rsi),%r13d\npush %r12\ncvtsi2sd %edx,%xmm1\nmov %rcx,%r12\npush %rbp\nmov %rdi,%rbp\npush %rbx\nxor %ebx,%ebx\nsub $0x18,%rsp\nnopw %cs:0x0(%rax,%rax,1)\npxor %xmm0,%xmm0\nmovsd %xmm1,0x8(%rsp)\ncvtsi2sdl 0x0(%rbp,%rbx,4),%xmm0\ncallq 1070 \nmovsd 0x8(%rsp),%xmm1\ncvttsd2si %xmm0,%eax\nmov %eax,(%r12,%rbx,4)\nmov %rbx,%rax\nadd $0x1,%rbx\ncmp %rax,%r13\njne 13a0 \nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopw 0x0(%rax,%rax,1)\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short locret_13B0\npxor xmm1, xmm1\npush r12\nmovsxd rsi, esi\npush rbp\ncvtsi2sd xmm1, edx; y\nmov rbp, rcx\nlea r12, [rdi+rsi*4]\npush rbx\nmov rbx, rdi\nsub rsp, 10h\nnop dword ptr [rax]\nloc_1378:\npxor xmm0, xmm0\nmovsd [rsp+28h+var_20], xmm1\nadd rbx, 4\nadd rbp, 4\ncvtsi2sd xmm0, dword ptr [rbx-4]; x\ncall _pow\nmovsd xmm1, [rsp+28h+var_20]\ncvttsd2si eax, xmm0\nmov [rbp-4], eax\ncmp rbx, r12\njnz short loc_1378\nadd rsp, 10h\npop rbx\npop rbp\npop r12\nretn\nlocret_13B0:\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3, __int64 a4)\n{\n double v4; // xmm1_8\n __int64 v6; // rbx\n __int64 result; // rax\n\n if ( a2 > 0 )\n {\n v4 = (double)a3;\n v6 = a1;\n do\n {\n v6 += 4LL;\n a4 += 4LL;\n result = (unsigned int)(int)pow((double)*(int *)(v6 - 4), v4);\n *(_DWORD *)(a4 - 4) = result;\n }\n while ( v6 != a1 + 4LL * a2 );\n }\n return result;\n}", + "ida_strip_asm": "sub_1350:\nendbr64\ntest esi, esi\njle short locret_13B0\npxor xmm1, xmm1\npush r12\nmovsxd rsi, esi\npush rbp\ncvtsi2sd xmm1, edx; y\nmov rbp, rcx\nlea r12, [rdi+rsi*4]\npush rbx\nmov rbx, rdi\nsub rsp, 10h\nnop dword ptr [rax]\nloc_1378:\npxor xmm0, xmm0\nmovsd [rsp+28h+var_20], xmm1\nadd rbx, 4\nadd rbp, 4\ncvtsi2sd xmm0, dword ptr [rbx-4]; x\ncall _pow\nmovsd xmm1, [rsp+28h+var_20]\ncvttsd2si eax, xmm0\nmov [rbp-4], eax\ncmp rbx, r12\njnz short loc_1378\nadd rsp, 10h\npop rbx\npop rbp\npop r12\nretn\nlocret_13B0:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1350(__int64 a1, int a2, int a3, __int64 a4)\n{\n double v4; // xmm1_8\n __int64 v6; // rbx\n __int64 result; // rax\n\n if ( a2 > 0 )\n {\n v4 = (double)a3;\n v6 = a1;\n do\n {\n v6 += 4LL;\n a4 += 4LL;\n result = (unsigned int)(int)pow((double)*(int *)(v6 - 4), v4);\n *(_DWORD *)(a4 - 4) = result;\n }\n while ( v6 != a1 + 4LL * a2 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1350(long long a1, int a2, int a3, long long a4) {\n double v4;\n long long v6;\n long long result;\n if (a2 > 0) {\n v4 = (double)a3;\n v6 = a1;\n do {\n v6 += 4LL;\n a4 += 4LL;\n result = (unsigned int)(int)pow((double)*(int *)(v6 - 4), v4);\n *(uint32_t *)(a4 - 4) = result;\n } while (v6 != a1 + 4LL * a2);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3, long long a4) {\n double v4;\n long long v6;\n long long result;\n if (a2 > 0) {\n v4 = (double)a3;\n v6 = a1;\n do {\n v6 += 4LL;\n a4 += 4LL;\n result = (unsigned int)(int)pow((double)*(int *)(v6 - 4), v4);\n *(uint32_t *)(a4 - 4) = result;\n } while (v6 != a1 + 4LL * a2);\n }\n return result;\n}" + }, + { + "index": 623, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include // For pow function\n\n\n\n", + "func": "void func0(int nums[], int length, int n, int result[]) {\n for (int i = 0; i < length; i++) {\n result[i] = pow(nums[i], n);\n }\n}", + "test": "int main() {\n\n int result1[10], result2[3], result3[2];\n\n int arr1[10] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n int arr2[3] = {10, 20, 30};\n\n int arr3[2] = {12, 15};\n\n\n\n func0(arr1, 10, 2, result1);\n\n func0(arr2, 3, 3, result2);\n\n func0(arr3, 2, 5, result3);\n\n\n\n assert(result1[0] == 1 && result1[1] == 4 && result1[2] == 9 && result1[3] == 16 \n\n && result1[4] == 25 && result1[5] == 36 && result1[6] == 49 && result1[7] == 64\n\n && result1[8] == 81 && result1[9] == 100);\n\n\n\n assert(result2[0] == 1000 && result2[1] == 8000 && result2[2] == 27000);\n\n\n\n assert(result3[0] == 248832 && result3[1] == 759375);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 13c0 \npxor %xmm1,%xmm1\npush %r13\nlea -0x1(%rsi),%r13d\npush %r12\ncvtsi2sd %edx,%xmm1\nmov %rcx,%r12\npush %rbp\nmov %rdi,%rbp\npush %rbx\nxor %ebx,%ebx\nsub $0x18,%rsp\nnopw %cs:0x0(%rax,%rax,1)\npxor %xmm0,%xmm0\nmovsd %xmm1,0x8(%rsp)\ncvtsi2sdl 0x0(%rbp,%rbx,4),%xmm0\ncallq 1070 \nmovsd 0x8(%rsp),%xmm1\ncvttsd2si %xmm0,%eax\nmov %eax,(%r12,%rbx,4)\nmov %rbx,%rax\nadd $0x1,%rbx\ncmp %rax,%r13\njne 1380 \nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopw 0x0(%rax,%rax,1)\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short locret_13B0\npxor xmm1, xmm1\npush r12\nmovsxd rsi, esi\npush rbp\ncvtsi2sd xmm1, edx; y\nmov rbp, rcx\nlea r12, [rdi+rsi*4]\npush rbx\nmov rbx, rdi\nsub rsp, 10h\nnop dword ptr [rax]\nloc_1378:\npxor xmm0, xmm0\nmovsd [rsp+28h+var_20], xmm1\nadd rbx, 4\nadd rbp, 4\ncvtsi2sd xmm0, dword ptr [rbx-4]; x\ncall _pow\nmovsd xmm1, [rsp+28h+var_20]\ncvttsd2si eax, xmm0\nmov [rbp-4], eax\ncmp rbx, r12\njnz short loc_1378\nadd rsp, 10h\npop rbx\npop rbp\npop r12\nretn\nlocret_13B0:\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3, __int64 a4)\n{\n double v4; // xmm1_8\n __int64 v6; // rbx\n __int64 result; // rax\n\n if ( a2 > 0 )\n {\n v4 = (double)a3;\n v6 = a1;\n do\n {\n v6 += 4LL;\n a4 += 4LL;\n result = (unsigned int)(int)pow((double)*(int *)(v6 - 4), v4);\n *(_DWORD *)(a4 - 4) = result;\n }\n while ( v6 != a1 + 4LL * a2 );\n }\n return result;\n}", + "ida_strip_asm": "sub_1350:\nendbr64\ntest esi, esi\njle short locret_13B0\npxor xmm1, xmm1\npush r12\nmovsxd rsi, esi\npush rbp\ncvtsi2sd xmm1, edx; y\nmov rbp, rcx\nlea r12, [rdi+rsi*4]\npush rbx\nmov rbx, rdi\nsub rsp, 10h\nnop dword ptr [rax]\nloc_1378:\npxor xmm0, xmm0\nmovsd [rsp+28h+var_20], xmm1\nadd rbx, 4\nadd rbp, 4\ncvtsi2sd xmm0, dword ptr [rbx-4]; x\ncall _pow\nmovsd xmm1, [rsp+28h+var_20]\ncvttsd2si eax, xmm0\nmov [rbp-4], eax\ncmp rbx, r12\njnz short loc_1378\nadd rsp, 10h\npop rbx\npop rbp\npop r12\nretn\nlocret_13B0:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1350(__int64 a1, int a2, int a3, __int64 a4)\n{\n double v4; // xmm1_8\n __int64 v6; // rbx\n __int64 result; // rax\n\n if ( a2 > 0 )\n {\n v4 = (double)a3;\n v6 = a1;\n do\n {\n v6 += 4LL;\n a4 += 4LL;\n result = (unsigned int)(int)pow((double)*(int *)(v6 - 4), v4);\n *(_DWORD *)(a4 - 4) = result;\n }\n while ( v6 != a1 + 4LL * a2 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1350(long long a1, int a2, int a3, long long a4) {\n double v4;\n long long v6;\n long long result;\n if (a2 > 0) {\n v4 = (double)a3;\n v6 = a1;\n do {\n v6 += 4LL;\n a4 += 4LL;\n result = (unsigned int)(int)pow((double)*(int *)(v6 - 4), v4);\n *(uint32_t *)(a4 - 4) = result;\n } while (v6 != a1 + 4LL * a2);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3, long long a4) {\n double v4;\n long long v6;\n long long result;\n if (a2 > 0) {\n v4 = (double)a3;\n v6 = a1;\n do {\n v6 += 4LL;\n a4 += 4LL;\n result = (unsigned int)(int)pow((double)*(int *)(v6 - 4), v4);\n *(uint32_t *)(a4 - 4) = result;\n } while (v6 != a1 + 4LL * a2);\n }\n return result;\n}" + }, + { + "index": 624, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* string) {\n static char result[100];\n int i;\n for (i = 0; string[i] != '\\0'; i++) {\n result[i] = toupper((unsigned char)string[i]);\n }\n result[i] = '\\0';\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"person\"), \"PERSON\") == 0);\n\n assert(strcmp(func0(\"final\"), \"FINAL\") == 0);\n\n assert(strcmp(func0(\"Valid\"), \"VALID\") == 0);\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11d1 \nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmovzbl %al,%eax\nmov %eax,%edi\ncallq 1070 \nmov %eax,%ecx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x2e76(%rip),%rdx\nmov %cl,(%rax,%rdx,1)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 11a2 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x2e4f(%rip),%rdx\nmovb $0x0,(%rax,%rdx,1)\nlea 0x2e44(%rip),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_4], 0\njmp short loc_11D1\nloc_11A2:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovzx eax, al\nmov edi, eax; c\ncall _toupper\nmov ecx, eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, result_1\nmov [rax+rdx], cl\nadd [rbp+var_4], 1\nloc_11D1:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_11A2\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, result_1\nmov byte ptr [rax+rdx], 0\nlea rax, result_1\nleave\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(__int64 a1)\n{\n int i; // [rsp+1Ch] [rbp-4h]\n\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n result_1[i] = toupper(*(unsigned __int8 *)(i + a1));\n result_1[i] = 0;\n return result_1;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_4], 0\njmp short loc_11D1\nloc_11A2:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovzx eax, al\nmov edi, eax; c\ncall _toupper\nmov ecx, eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, unk_4040\nmov [rax+rdx], cl\nadd [rbp+var_4], 1\nloc_11D1:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_11A2\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, unk_4040\nmov byte ptr [rax+rdx], 0\nlea rax, unk_4040\nleave\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1189(__int64 a1)\n{\n int i; // [rsp+1Ch] [rbp-4h]\n\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n byte_4040[i] = toupper(*(unsigned __int8 *)(i + a1));\n byte_4040[i] = 0;\n return byte_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1189(long long a1) {\n int i;\n for (i = 0; *(uint8_t *)(i + a1); ++i)\n byte_4040[i] = toupper(*(unsigned char *)(i + a1));\n byte_4040[i] = 0;\n return byte_4040;\n}", + "ida_pseudo_norm": "uint8_t *func0(long long a1) {\n int i;\n for (i = 0; *(uint8_t *)(i + a1); ++i)\n result_1[i] = toupper(*(unsigned char *)(i + a1));\n result_1[i] = 0;\n return result_1;\n}" + }, + { + "index": 624, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* string) {\n static char result[100];\n int i;\n for (i = 0; string[i] != '\\0'; i++) {\n result[i] = toupper((unsigned char)string[i]);\n }\n result[i] = '\\0';\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"person\"), \"PERSON\") == 0);\n\n assert(strcmp(func0(\"final\"), \"FINAL\") == 0);\n\n assert(strcmp(func0(\"Valid\"), \"VALID\") == 0);\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmovzbl (%rdi),%ebx\ntest %bl,%bl\nje 11be \nmov %rdi,%rbp\ncallq 1060 <__ctype_toupper_loc@plt>\nmov $0x1,%edx\nlea 0x2eb1(%rip),%rsi\nmovzbl %bl,%ebx\nmov (%rax),%rcx\nmov (%rcx,%rbx,4),%ecx\nmov %cl,(%rdx,%rsi,1)\nmov %edx,%ecx\nadd $0x1,%rdx\nmovzbl -0x1(%rbp,%rdx,1),%ebx\ntest %bl,%bl\njne 118e \nlea 0x2e90(%rip),%rax\nmovslq %ecx,%rcx\nmovb $0x0,(%rax,%rcx,1)\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nmov $0x0,%ecx\njmp 11a9 \n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_11DF\nmov rbp, rdi\ncall ___ctype_toupper_loc\nmov edx, 1\nlea rsi, unk_403F\nloc_11AE:\nmovzx ebx, bl\nmov rcx, [rax]\nmov ecx, [rcx+rbx*4]\nmov [rdx+rsi], cl\nmov rcx, rdx\nadd rdx, 1\nmovzx ebx, byte ptr [rbp+rdx-1]\ntest bl, bl\njnz short loc_11AE\nloc_11CA:\nlea rax, result_1\nmovsxd rcx, ecx\nmov byte ptr [rax+rcx], 0\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_11DF:\nmov ecx, 0\njmp short loc_11CA", + "ida_pseudo": "_BYTE *__fastcall func0(unsigned __int8 *a1)\n{\n unsigned __int8 v1; // bl\n const __int32_t **v2; // rax\n __int64 v3; // rdx\n int v4; // ecx\n _BYTE *result; // rax\n\n v1 = *a1;\n if ( *a1 )\n {\n v2 = __ctype_toupper_loc();\n v3 = 1LL;\n do\n {\n *((_BYTE *)&unk_403F + v3) = (*v2)[v1];\n v4 = v3++;\n v1 = a1[v3 - 1];\n }\n while ( v1 );\n }\n else\n {\n v4 = 0;\n }\n result = result_1;\n result_1[v4] = 0;\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_11DF\nmov rbp, rdi\ncall ___ctype_toupper_loc\nmov edx, 1\nlea rsi, unk_403F\nloc_11AE:\nmovzx ebx, bl\nmov rcx, [rax]\nmov ecx, [rcx+rbx*4]\nmov [rdx+rsi], cl\nmov rcx, rdx\nadd rdx, 1\nmovzx ebx, byte ptr [rbp+rdx-1]\ntest bl, bl\njnz short loc_11AE\nloc_11CA:\nlea rax, unk_4040\nmovsxd rcx, ecx\nmov byte ptr [rax+rcx], 0\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_11DF:\nmov ecx, 0\njmp short loc_11CA", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1189(unsigned __int8 *a1)\n{\n unsigned __int8 v1; // bl\n const __int32_t **v2; // rax\n __int64 v3; // rdx\n int v4; // ecx\n _BYTE *result; // rax\n\n v1 = *a1;\n if ( *a1 )\n {\n v2 = __ctype_toupper_loc();\n v3 = 1LL;\n do\n {\n *((_BYTE *)&unk_403F + v3) = (*v2)[v1];\n v4 = v3++;\n v1 = a1[v3 - 1];\n }\n while ( v1 );\n }\n else\n {\n v4 = 0;\n }\n result = byte_4040;\n byte_4040[v4] = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1189(unsigned char *a1) {\n unsigned char v1;\n const __int32_t **v2;\n long long v3;\n int v4;\n uint8_t *result;\n v1 = *a1;\n if (*a1) {\n v2 = __ctype_toupper_loc();\n v3 = 1LL;\n do {\n *((uint8_t *)&unk_403F + v3) = (*v2)[v1];\n v4 = v3++;\n v1 = a1[v3 - 1];\n } while (v1);\n } else {\n v4 = 0;\n }\n result = byte_4040;\n byte_4040[v4] = 0;\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(unsigned char *a1) {\n unsigned char v1;\n const __int32_t **v2;\n long long v3;\n int v4;\n uint8_t *result;\n v1 = *a1;\n if (*a1) {\n v2 = __ctype_toupper_loc();\n v3 = 1LL;\n do {\n *((uint8_t *)&unk_403F + v3) = (*v2)[v1];\n v4 = v3++;\n v1 = a1[v3 - 1];\n } while (v1);\n } else {\n v4 = 0;\n }\n result = result_1;\n result_1[v4] = 0;\n return result;\n}" + }, + { + "index": 624, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* string) {\n static char result[100];\n int i;\n for (i = 0; string[i] != '\\0'; i++) {\n result[i] = toupper((unsigned char)string[i]);\n }\n result[i] = '\\0';\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"person\"), \"PERSON\") == 0);\n\n assert(strcmp(func0(\"final\"), \"FINAL\") == 0);\n\n assert(strcmp(func0(\"Valid\"), \"VALID\") == 0);\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmovzbl (%rdi),%ebx\ntest %bl,%bl\nje 12b0 \nmov %rdi,%rbp\ncallq 1060 <__ctype_toupper_loc@plt>\nmov $0x1,%edx\nlea 0x2dca(%rip),%rsi\nnopl (%rax)\nmov (%rax),%rcx\nmovzbl %bl,%ebx\nmov (%rcx,%rbx,4),%ecx\nmov %cl,(%rsi,%rdx,1)\nmovslq %edx,%rcx\nadd $0x1,%rdx\nmovzbl -0x1(%rbp,%rdx,1),%ebx\ntest %bl,%bl\njne 1278 \nlea 0x2da5(%rip),%rax\nmovb $0x0,(%rax,%rcx,1)\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxor %ecx,%ecx\njmp 1294 \nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_12C0\nmov rbp, rdi\ncall ___ctype_toupper_loc\nmov edx, 1\nlea rsi, unk_403F\nnop dword ptr [rax]\nloc_1288:\nmov rcx, [rax]\nmov ecx, [rcx+rbx*4]\nmov [rsi+rdx], cl\nmov rcx, rdx\nadd rdx, 1\nmovzx ebx, byte ptr [rbp+rdx-1]\ntest bl, bl\njnz short loc_1288\nloc_12A1:\nlea rax, result_1\nmovsxd rcx, ecx\nmov byte ptr [rax+rcx], 0\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_12C0:\nxor ecx, ecx\njmp short loc_12A1", + "ida_pseudo": "_BYTE *__fastcall func0(unsigned __int8 *a1)\n{\n __int64 v1; // rbx\n const __int32_t **v2; // rax\n __int64 v3; // rdx\n int v4; // ecx\n _BYTE *result; // rax\n\n v1 = *a1;\n if ( (_BYTE)v1 )\n {\n v2 = __ctype_toupper_loc();\n v3 = 1LL;\n do\n {\n *((_BYTE *)&unk_403F + v3) = (*v2)[v1];\n v4 = v3++;\n v1 = a1[v3 - 1];\n }\n while ( (_BYTE)v1 );\n }\n else\n {\n v4 = 0;\n }\n result = result_1;\n result_1[v4] = 0;\n return result;\n}", + "ida_strip_asm": "sub_1260:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_12C0\nmov rbp, rdi\ncall ___ctype_toupper_loc\nmov edx, 1\nlea rsi, unk_403F\nnop dword ptr [rax]\nloc_1288:\nmov rcx, [rax]\nmov ecx, [rcx+rbx*4]\nmov [rsi+rdx], cl\nmov rcx, rdx\nadd rdx, 1\nmovzx ebx, byte ptr [rbp+rdx-1]\ntest bl, bl\njnz short loc_1288\nloc_12A1:\nlea rax, unk_4040\nmovsxd rcx, ecx\nmov byte ptr [rax+rcx], 0\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_12C0:\nxor ecx, ecx\njmp short loc_12A1", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1260(unsigned __int8 *a1)\n{\n __int64 v1; // rbx\n const __int32_t **v2; // rax\n __int64 v3; // rdx\n int v4; // ecx\n _BYTE *result; // rax\n\n v1 = *a1;\n if ( (_BYTE)v1 )\n {\n v2 = __ctype_toupper_loc();\n v3 = 1LL;\n do\n {\n *((_BYTE *)&unk_403F + v3) = (*v2)[v1];\n v4 = v3++;\n v1 = a1[v3 - 1];\n }\n while ( (_BYTE)v1 );\n }\n else\n {\n v4 = 0;\n }\n result = byte_4040;\n byte_4040[v4] = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1260(unsigned char *a1) {\n long long v1;\n const __int32_t **v2;\n long long v3;\n int v4;\n uint8_t *result;\n v1 = *a1;\n if ((uint8_t)v1) {\n v2 = __ctype_toupper_loc();\n v3 = 1LL;\n do {\n *((uint8_t *)&unk_403F + v3) = (*v2)[v1];\n v4 = v3++;\n v1 = a1[v3 - 1];\n } while ((uint8_t)v1);\n } else {\n v4 = 0;\n }\n result = byte_4040;\n byte_4040[v4] = 0;\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(unsigned char *a1) {\n long long v1;\n const __int32_t **v2;\n long long v3;\n int v4;\n uint8_t *result;\n v1 = *a1;\n if ((uint8_t)v1) {\n v2 = __ctype_toupper_loc();\n v3 = 1LL;\n do {\n *((uint8_t *)&unk_403F + v3) = (*v2)[v1];\n v4 = v3++;\n v1 = a1[v3 - 1];\n } while ((uint8_t)v1);\n } else {\n v4 = 0;\n }\n result = result_1;\n result_1[v4] = 0;\n return result;\n}" + }, + { + "index": 624, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* string) {\n static char result[100];\n int i;\n for (i = 0; string[i] != '\\0'; i++) {\n result[i] = toupper((unsigned char)string[i]);\n }\n result[i] = '\\0';\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"person\"), \"PERSON\") == 0);\n\n assert(strcmp(func0(\"final\"), \"FINAL\") == 0);\n\n assert(strcmp(func0(\"Valid\"), \"VALID\") == 0);\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmovzbl (%rdi),%ebx\ntest %bl,%bl\nje 12b0 \nmov %rdi,%rbp\ncallq 1060 <__ctype_toupper_loc@plt>\nmov $0x1,%edx\nlea 0x2dca(%rip),%rsi\nnopl (%rax)\nmov (%rax),%rcx\nmovzbl %bl,%ebx\nmov (%rcx,%rbx,4),%ecx\nmov %cl,(%rsi,%rdx,1)\nmovslq %edx,%rcx\nadd $0x1,%rdx\nmovzbl -0x1(%rbp,%rdx,1),%ebx\ntest %bl,%bl\njne 1278 \nlea 0x2da5(%rip),%rax\nmovb $0x0,(%rax,%rcx,1)\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxor %ecx,%ecx\njmp 1294 \nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_12C0\nmov rbp, rdi\ncall ___ctype_toupper_loc\nmov edx, 1\nlea rsi, unk_403F\nnop dword ptr [rax]\nloc_1288:\nmov rcx, [rax]\nmov ecx, [rcx+rbx*4]\nmov [rsi+rdx], cl\nmov rcx, rdx\nadd rdx, 1\nmovzx ebx, byte ptr [rbp+rdx-1]\ntest bl, bl\njnz short loc_1288\nloc_12A1:\nlea rax, result_1\nmovsxd rcx, ecx\nmov byte ptr [rax+rcx], 0\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_12C0:\nxor ecx, ecx\njmp short loc_12A1", + "ida_pseudo": "_BYTE *__fastcall func0(unsigned __int8 *a1)\n{\n __int64 v1; // rbx\n const __int32_t **v2; // rax\n __int64 v3; // rdx\n int v4; // ecx\n _BYTE *result; // rax\n\n v1 = *a1;\n if ( (_BYTE)v1 )\n {\n v2 = __ctype_toupper_loc();\n v3 = 1LL;\n do\n {\n *((_BYTE *)&unk_403F + v3) = (*v2)[v1];\n v4 = v3++;\n v1 = a1[v3 - 1];\n }\n while ( (_BYTE)v1 );\n }\n else\n {\n v4 = 0;\n }\n result = result_1;\n result_1[v4] = 0;\n return result;\n}", + "ida_strip_asm": "sub_1260:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_12C0\nmov rbp, rdi\ncall ___ctype_toupper_loc\nmov edx, 1\nlea rsi, unk_403F\nnop dword ptr [rax]\nloc_1288:\nmov rcx, [rax]\nmov ecx, [rcx+rbx*4]\nmov [rsi+rdx], cl\nmov rcx, rdx\nadd rdx, 1\nmovzx ebx, byte ptr [rbp+rdx-1]\ntest bl, bl\njnz short loc_1288\nloc_12A1:\nlea rax, unk_4040\nmovsxd rcx, ecx\nmov byte ptr [rax+rcx], 0\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_12C0:\nxor ecx, ecx\njmp short loc_12A1", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1260(unsigned __int8 *a1)\n{\n __int64 v1; // rbx\n const __int32_t **v2; // rax\n __int64 v3; // rdx\n int v4; // ecx\n _BYTE *result; // rax\n\n v1 = *a1;\n if ( (_BYTE)v1 )\n {\n v2 = __ctype_toupper_loc();\n v3 = 1LL;\n do\n {\n *((_BYTE *)&unk_403F + v3) = (*v2)[v1];\n v4 = v3++;\n v1 = a1[v3 - 1];\n }\n while ( (_BYTE)v1 );\n }\n else\n {\n v4 = 0;\n }\n result = byte_4040;\n byte_4040[v4] = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1260(unsigned char *a1) {\n long long v1;\n const __int32_t **v2;\n long long v3;\n int v4;\n uint8_t *result;\n v1 = *a1;\n if ((uint8_t)v1) {\n v2 = __ctype_toupper_loc();\n v3 = 1LL;\n do {\n *((uint8_t *)&unk_403F + v3) = (*v2)[v1];\n v4 = v3++;\n v1 = a1[v3 - 1];\n } while ((uint8_t)v1);\n } else {\n v4 = 0;\n }\n result = byte_4040;\n byte_4040[v4] = 0;\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(unsigned char *a1) {\n long long v1;\n const __int32_t **v2;\n long long v3;\n int v4;\n uint8_t *result;\n v1 = *a1;\n if ((uint8_t)v1) {\n v2 = __ctype_toupper_loc();\n v3 = 1LL;\n do {\n *((uint8_t *)&unk_403F + v3) = (*v2)[v1];\n v4 = v3++;\n v1 = a1[v3 - 1];\n } while ((uint8_t)v1);\n } else {\n v4 = 0;\n }\n result = result_1;\n result_1[v4] = 0;\n return result;\n}" + }, + { + "index": 625, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int newList[], int size) {\n int temp = newList[0];\n newList[0] = newList[size - 1];\n newList[size - 1] = temp;\n return newList;\n}", + "test": "int main() {\n\n // Test case 1\n\n int array1[] = {1, 2, 3};\n\n int size1 = sizeof(array1) / sizeof(array1[0]);\n\n int* result1 = func0(array1, size1);\n\n assert(result1[0] == 3);\n\n assert(result1[1] == 2);\n\n assert(result1[2] == 1);\n\n\n\n // Test case 2\n\n int array2[] = {1, 2, 3, 4, 4};\n\n int size2 = sizeof(array2) / sizeof(array2[0]);\n\n int* result2 = func0(array2, size2);\n\n assert(result2[0] == 4);\n\n assert(result2[1] == 2);\n\n assert(result2[2] == 3);\n\n assert(result2[3] == 4);\n\n assert(result2[4] == 1);\n\n\n\n // Test case 3\n\n int array3[] = {4, 5, 6};\n\n int size3 = sizeof(array3) / sizeof(array3[0]);\n\n int* result3 = func0(array3, size3);\n\n assert(result3[0] == 6);\n\n assert(result3[1] == 5);\n\n assert(result3[2] == 4);\n\n\n\n printf(\"All tests passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov -0x18(%rbp),%rax\nmov (%rax),%eax\nmov %eax,-0x4(%rbp)\nmov -0x1c(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x18(%rbp),%rax\nmov %edx,(%rax)\nmov -0x1c(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0x4(%rbp),%eax\nmov %eax,(%rdx)\nmov -0x18(%rbp),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov rax, [rbp+var_18]\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_18]\nmov [rax], edx\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nmov rax, [rbp+var_18]\npop rbp\nretn", + "ida_pseudo": "int *__fastcall func0(int *a1, int a2)\n{\n int v3; // [rsp+18h] [rbp-4h]\n\n v3 = *a1;\n *a1 = a1[a2 - 1];\n a1[a2 - 1] = v3;\n return a1;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov rax, [rbp+var_18]\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_18]\nmov [rax], edx\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nmov rax, [rbp+var_18]\npop rbp\nretn", + "ida_strip_pseudo": "int *__fastcall sub_1189(int *a1, int a2)\n{\n int v3; // [rsp+18h] [rbp-4h]\n\n v3 = *a1;\n *a1 = a1[a2 - 1];\n a1[a2 - 1] = v3;\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "int *sub_1189(int *a1, int a2) {\n int v3;\n v3 = *a1;\n *a1 = a1[a2 - 1];\n a1[a2 - 1] = v3;\n return a1;\n}", + "ida_pseudo_norm": "int *func0(int *a1, int a2) {\n int v3;\n v3 = *a1;\n *a1 = a1[a2 - 1];\n a1[a2 - 1] = v3;\n return a1;\n}" + }, + { + "index": 626, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int r) {\n if (r < 0) {\n return -1;\n }\n return r * r;\n}", + "test": "int main() {\n\n assert(func0(0) == 0);\n\n assert(func0(-1) == -1);\n\n assert(func0(2) == 4);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\ncmpl $0x0,-0x4(%rbp)\njns 1161 \nmov $0xffffffff,%eax\njmp 1167 \nmov -0x4(%rbp),%eax\nimul %eax,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\ncmp [rbp+var_4], 0\njns short loc_1161\nmov eax, 0FFFFFFFFh\njmp short loc_1167\nloc_1161:\nmov eax, [rbp+var_4]\nimul eax, eax\nloc_1167:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n if ( a1 >= 0 )\n return (unsigned int)(a1 * a1);\n else\n return 0xFFFFFFFFLL;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\ncmp [rbp+var_4], 0\njns short loc_1161\nmov eax, 0FFFFFFFFh\njmp short loc_1167\nloc_1161:\nmov eax, [rbp+var_4]\nimul eax, eax\nloc_1167:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n if ( a1 >= 0 )\n return (unsigned int)(a1 * a1);\n else\n return 0xFFFFFFFFLL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n if (a1 >= 0)\n return (unsigned int)(a1 * a1);\n else\n return 4294967295LL;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n if (a1 >= 0)\n return (unsigned int)(a1 * a1);\n else\n return 4294967295LL;\n}" + }, + { + "index": 627, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int array[], int start, int end) {\n if (start > end) {\n return end + 1;\n }\n if (start != array[start]) {\n return start;\n }\n int mid = (start + end) / 2;\n if (array[mid] == mid) {\n return func0(array, mid + 1, end);\n }\n return func0(array, start, mid);\n}", + "test": "int main() {\n\n int array1[] = {0, 1, 2, 3};\n\n int array2[] = {0, 1, 2, 6, 9};\n\n int array3[] = {2, 3, 5, 8, 9};\n\n\n\n assert(func0(array1, 0, 3) == 4);\n\n assert(func0(array2, 0, 4) == 3);\n\n assert(func0(array3, 0, 4) == 0);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmov -0x1c(%rbp),%eax\ncmp -0x20(%rbp),%eax\njle 11af \nmov -0x20(%rbp),%eax\nadd $0x1,%eax\njmp 122b \nmov -0x1c(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x1c(%rbp)\nje 11cf \nmov -0x1c(%rbp),%eax\njmp 122b \nmov -0x1c(%rbp),%edx\nmov -0x20(%rbp),%eax\nadd %edx,%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x4(%rbp)\njne 1217 \nmov -0x4(%rbp),%eax\nlea 0x1(%rax),%ecx\nmov -0x20(%rbp),%edx\nmov -0x18(%rbp),%rax\nmov %ecx,%esi\nmov %rax,%rdi\ncallq 1189 \njmp 122b \nmov -0x4(%rbp),%edx\nmov -0x1c(%rbp),%ecx\nmov -0x18(%rbp),%rax\nmov %ecx,%esi\nmov %rax,%rdi\ncallq 1189 \nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_20]\njle short loc_11AF\nmov eax, [rbp+var_20]\nadd eax, 1\njmp short locret_122B\nloc_11AF:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_1C], eax\njz short loc_11CF\nmov eax, [rbp+var_1C]\njmp short locret_122B\nloc_11CF:\nmov edx, [rbp+var_1C]\nmov eax, [rbp+var_20]\nadd eax, edx\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_4], eax\njnz short loc_1217\nmov eax, [rbp+var_4]\nlea ecx, [rax+1]\nmov edx, [rbp+var_20]\nmov rax, [rbp+var_18]\nmov esi, ecx\nmov rdi, rax\ncall func0\njmp short locret_122B\nloc_1217:\nmov edx, [rbp+var_4]\nmov ecx, [rbp+var_1C]\nmov rax, [rbp+var_18]\nmov esi, ecx\nmov rdi, rax\ncall func0\nlocret_122B:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, unsigned int a2, unsigned int a3)\n{\n int v4; // [rsp+1Ch] [rbp-4h]\n\n if ( (int)a2 > (int)a3 )\n return a3 + 1;\n if ( a2 != *(_DWORD *)(4LL * (int)a2 + a1) )\n return a2;\n v4 = (int)(a2 + a3) / 2;\n if ( v4 == *(_DWORD *)(4LL * v4 + a1) )\n return func0(a1, (unsigned int)(v4 + 1), a3);\n else\n return func0(a1, a2, (unsigned int)v4);\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_20]\njle short loc_11AF\nmov eax, [rbp+var_20]\nadd eax, 1\njmp short locret_122B\nloc_11AF:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_1C], eax\njz short loc_11CF\nmov eax, [rbp+var_1C]\njmp short locret_122B\nloc_11CF:\nmov edx, [rbp+var_1C]\nmov eax, [rbp+var_20]\nadd eax, edx\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_4], eax\njnz short loc_1217\nmov eax, [rbp+var_4]\nlea ecx, [rax+1]\nmov edx, [rbp+var_20]\nmov rax, [rbp+var_18]\nmov esi, ecx\nmov rdi, rax\ncall sub_1189\njmp short locret_122B\nloc_1217:\nmov edx, [rbp+var_4]\nmov ecx, [rbp+var_1C]\nmov rax, [rbp+var_18]\nmov esi, ecx\nmov rdi, rax\ncall sub_1189\nlocret_122B:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, unsigned int a2, unsigned int a3)\n{\n int v4; // [rsp+1Ch] [rbp-4h]\n\n if ( (int)a2 > (int)a3 )\n return a3 + 1;\n if ( a2 != *(_DWORD *)(4LL * (int)a2 + a1) )\n return a2;\n v4 = (int)(a2 + a3) / 2;\n if ( v4 == *(_DWORD *)(4LL * v4 + a1) )\n return sub_1189(a1, (unsigned int)(v4 + 1), a3);\n else\n return sub_1189(a1, a2, (unsigned int)v4);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, unsigned int a2, unsigned int a3) {\n int v4;\n if ((int)a2 > (int)a3) return a3 + 1;\n if (a2 != *(uint32_t *)(4LL * (int)a2 + a1)) return a2;\n v4 = (int)(a2 + a3) / 2;\n if (v4 == *(uint32_t *)(4LL * v4 + a1))\n return sub_1189(a1, (unsigned int)(v4 + 1), a3);\n else\n return sub_1189(a1, a2, (unsigned int)v4);\n}", + "ida_pseudo_norm": "long long func0(long long a1, unsigned int a2, unsigned int a3) {\n int v4;\n if ((int)a2 > (int)a3) return a3 + 1;\n if (a2 != *(uint32_t *)(4LL * (int)a2 + a1)) return a2;\n v4 = (int)(a2 + a3) / 2;\n if (v4 == *(uint32_t *)(4LL * v4 + a1))\n return func0(a1, (unsigned int)(v4 + 1), a3);\n else\n return func0(a1, a2, (unsigned int)v4);\n}" + }, + { + "index": 627, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int array[], int start, int end) {\n if (start > end) {\n return end + 1;\n }\n if (start != array[start]) {\n return start;\n }\n int mid = (start + end) / 2;\n if (array[mid] == mid) {\n return func0(array, mid + 1, end);\n }\n return func0(array, start, mid);\n}", + "test": "int main() {\n\n int array1[] = {0, 1, 2, 3};\n\n int array2[] = {0, 1, 2, 6, 9};\n\n int array3[] = {2, 3, 5, 8, 9};\n\n\n\n assert(func0(array1, 0, 3) == 4);\n\n assert(func0(array2, 0, 4) == 3);\n\n assert(func0(array3, 0, 4) == 0);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ncmp %edx,%esi\njg 11bf \nmovslq %esi,%rcx\nmov %esi,%eax\ncmp %esi,(%rdi,%rcx,4)\njne 11cd \nsub $0x8,%rsp\nlea (%rsi,%rdx,1),%ecx\nmov %ecx,%eax\nshr $0x1f,%eax\nadd %ecx,%eax\nsar %eax\nmovslq %eax,%rcx\ncmp %eax,(%rdi,%rcx,4)\nje 11c3 \nmov %eax,%edx\ncallq 1189 \nadd $0x8,%rsp\nretq\nlea 0x1(%rdx),%eax\nretq\nlea 0x1(%rax),%esi\ncallq 1189 \njmp 11ba \nretq\n", + "ida_asm": "func0:\nendbr64\ncmp esi, edx\njg short loc_11BF\nmovsxd rcx, esi\nmov eax, esi\ncmp [rdi+rcx*4], esi\njnz short locret_11CD\nsub rsp, 8\nlea ecx, [rsi+rdx]\nmov eax, ecx\nshr eax, 1Fh\nadd eax, ecx\nsar eax, 1\nmovsxd rcx, eax\ncmp [rdi+rcx*4], eax\njz short loc_11C3\nmov edx, eax\ncall func0\nloc_11BA:\nadd rsp, 8\nretn\nloc_11BF:\nlea eax, [rdx+1]\nretn\nloc_11C3:\nlea esi, [rax+1]\ncall func0\njmp short loc_11BA\nlocret_11CD:\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n __int64 result; // rax\n int v4; // eax\n\n if ( (int)a2 > a3 )\n return (unsigned int)(a3 + 1);\n result = (unsigned int)a2;\n if ( *(_DWORD *)(a1 + 4LL * (int)a2) == (_DWORD)a2 )\n {\n v4 = ((int)a2 + a3) / 2;\n if ( *(_DWORD *)(a1 + 4LL * v4) == v4 )\n return func0(a1, (unsigned int)(v4 + 1));\n else\n return func0(a1, a2);\n }\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\ncmp esi, edx\njg short loc_11BF\nmovsxd rcx, esi\nmov eax, esi\ncmp [rdi+rcx*4], esi\njnz short locret_11CD\nsub rsp, 8\nlea ecx, [rsi+rdx]\nmov eax, ecx\nshr eax, 1Fh\nadd eax, ecx\nsar eax, 1\nmovsxd rcx, eax\ncmp [rdi+rcx*4], eax\njz short loc_11C3\nmov edx, eax\ncall sub_1189\nloc_11BA:\nadd rsp, 8\nretn\nloc_11BF:\nlea eax, [rdx+1]\nretn\nloc_11C3:\nlea esi, [rax+1]\ncall sub_1189\njmp short loc_11BA\nlocret_11CD:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, __int64 a2, int a3)\n{\n __int64 result; // rax\n int v4; // eax\n\n if ( (int)a2 > a3 )\n return (unsigned int)(a3 + 1);\n result = (unsigned int)a2;\n if ( *(_DWORD *)(a1 + 4LL * (int)a2) == (_DWORD)a2 )\n {\n v4 = ((int)a2 + a3) / 2;\n if ( *(_DWORD *)(a1 + 4LL * v4) == v4 )\n return sub_1189(a1, (unsigned int)(v4 + 1));\n else\n return sub_1189(a1, a2);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, long long a2, int a3) {\n long long result;\n int v4;\n if ((int)a2 > a3) return (unsigned int)(a3 + 1);\n result = (unsigned int)a2;\n if (*(uint32_t *)(a1 + 4LL * (int)a2) == (uint32_t)a2) {\n v4 = ((int)a2 + a3) / 2;\n if (*(uint32_t *)(a1 + 4LL * v4) == v4)\n return sub_1189(a1, (unsigned int)(v4 + 1));\n else\n return sub_1189(a1, a2);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3) {\n long long result;\n int v4;\n if ((int)a2 > a3) return (unsigned int)(a3 + 1);\n result = (unsigned int)a2;\n if (*(uint32_t *)(a1 + 4LL * (int)a2) == (uint32_t)a2) {\n v4 = ((int)a2 + a3) / 2;\n if (*(uint32_t *)(a1 + 4LL * v4) == v4)\n return func0(a1, (unsigned int)(v4 + 1));\n else\n return func0(a1, a2);\n }\n return result;\n}" + }, + { + "index": 627, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int array[], int start, int end) {\n if (start > end) {\n return end + 1;\n }\n if (start != array[start]) {\n return start;\n }\n int mid = (start + end) / 2;\n if (array[mid] == mid) {\n return func0(array, mid + 1, end);\n }\n return func0(array, start, mid);\n}", + "test": "int main() {\n\n int array1[] = {0, 1, 2, 3};\n\n int array2[] = {0, 1, 2, 6, 9};\n\n int array3[] = {2, 3, 5, 8, 9};\n\n\n\n assert(func0(array1, 0, 3) == 4);\n\n assert(func0(array2, 0, 4) == 3);\n\n assert(func0(array3, 0, 4) == 0);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmovslq %esi,%rax\nlea (%rdi,%rax,4),%r8\njmp 12fb \nnopl (%rax)\ncmp %esi,(%r8)\njne 1308 \nlea (%rdx,%rsi,1),%eax\nmov %eax,%ecx\nshr $0x1f,%ecx\nadd %eax,%ecx\nsar %ecx\nmovslq %ecx,%rax\ncmp %ecx,(%rdi,%rax,4)\nje 1310 \nmov %ecx,%edx\ncmp %esi,%edx\njge 12e0 \nlea 0x1(%rdx),%eax\nretq\nnopl 0x0(%rax,%rax,1)\nmov %esi,%eax\nretq\nnopl 0x0(%rax,%rax,1)\nlea 0x1(%rcx),%esi\njmp 12d4 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nloc_12B4:\nmovsxd rax, esi\nlea r8, [rdi+rax*4]\njmp short loc_12DB\nloc_12C0:\ncmp [r8], esi\njnz short loc_12E8\nlea eax, [rdx+rsi]\nmov ecx, eax\nshr ecx, 1Fh\nadd ecx, eax\nsar ecx, 1\nmovsxd rax, ecx\ncmp [rdi+rax*4], ecx\njz short loc_12F0\nmov edx, ecx\nloc_12DB:\ncmp edx, esi\njge short loc_12C0\nlea eax, [rdx+1]\nretn\nloc_12E8:\nmov eax, esi\nretn\nloc_12F0:\nlea esi, [rcx+1]\njmp short loc_12B4", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n int v3; // ecx\n\n while ( 1 )\n {\n if ( a3 < a2 )\n return (unsigned int)(a3 + 1);\n if ( *(_DWORD *)(a1 + 4LL * a2) != a2 )\n break;\n v3 = (a3 + a2) / 2;\n if ( *(_DWORD *)(a1 + 4LL * v3) == v3 )\n a2 = v3 + 1;\n else\n a3 = (a3 + a2) / 2;\n }\n return (unsigned int)a2;\n}", + "ida_strip_asm": "sub_12B0:\nendbr64\nloc_12B4:\nmovsxd rax, esi\nlea r8, [rdi+rax*4]\njmp short loc_12DB\nloc_12C0:\ncmp [r8], esi\njnz short loc_12E8\nlea eax, [rdx+rsi]\nmov ecx, eax\nshr ecx, 1Fh\nadd ecx, eax\nsar ecx, 1\nmovsxd rax, ecx\ncmp [rdi+rax*4], ecx\njz short loc_12F0\nmov edx, ecx\nloc_12DB:\ncmp edx, esi\njge short loc_12C0\nlea eax, [rdx+1]\nretn\nloc_12E8:\nmov eax, esi\nretn\nloc_12F0:\nlea esi, [rcx+1]\njmp short loc_12B4", + "ida_strip_pseudo": "__int64 __fastcall sub_12B0(__int64 a1, int a2, int a3)\n{\n int v3; // ecx\n\n while ( 1 )\n {\n if ( a3 < a2 )\n return (unsigned int)(a3 + 1);\n if ( *(_DWORD *)(a1 + 4LL * a2) != a2 )\n break;\n v3 = (a3 + a2) / 2;\n if ( *(_DWORD *)(a1 + 4LL * v3) == v3 )\n a2 = v3 + 1;\n else\n a3 = (a3 + a2) / 2;\n }\n return (unsigned int)a2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12B0(long long a1, int a2, int a3) {\n int v3;\n while (1) {\n if (a3 < a2) return (unsigned int)(a3 + 1);\n if (*(uint32_t *)(a1 + 4LL * a2) != a2) break;\n v3 = (a3 + a2) / 2;\n if (*(uint32_t *)(a1 + 4LL * v3) == v3)\n a2 = v3 + 1;\n else\n a3 = (a3 + a2) / 2;\n }\n return (unsigned int)a2;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n int v3;\n while (1) {\n if (a3 < a2) return (unsigned int)(a3 + 1);\n if (*(uint32_t *)(a1 + 4LL * a2) != a2) break;\n v3 = (a3 + a2) / 2;\n if (*(uint32_t *)(a1 + 4LL * v3) == v3)\n a2 = v3 + 1;\n else\n a3 = (a3 + a2) / 2;\n }\n return (unsigned int)a2;\n}" + }, + { + "index": 628, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n#define MAX 1000\n\n\n\n", + "func": "char* func0(char* string) {\n char new_string[MAX];\n int i, j, space_count = 0, new_length;\n char* result;\n i = strlen(string);\n for (j = 0; j < i; j++) {\n if (string[j] == ' ') space_count++;\n }\n new_length = i + space_count * 2;\n if (new_length > MAX) {\n return \"\";\n }\n int index = new_length - 1;\n new_string[new_length] = '\\0';\n for (j = i - 1; j >= 0; j--) {\n if (string[j] == ' ') {\n new_string[index] = '0';\n new_string[index - 1] = '2';\n new_string[index - 2] = '%';\n index -= 3;\n } else {\n new_string[index] = string[j];\n index--;\n }\n }\n result = (char*)malloc(new_length + 1);\n strcpy(result, new_string);\n return result;\n}", + "test": "int main() {\n\n\tassert(strcmp(func0(\"My Name is Dawood\"), \"My%20Name%20is%20Dawood\") == 0);\n\n\tassert(strcmp(func0(\"I am a Programmer\"), \"I%20am%20a%20Programmer\") == 0);\n\n\tassert(strcmp(func0(\"I love Coding\"), \"I%20love%20Coding\") == 0);\n\n\n\n\treturn 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x420,%rsp\nmov %rdi,-0x418(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovl $0x0,-0x408(%rbp)\nmov -0x418(%rbp),%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %eax,-0x400(%rbp)\nmovl $0x0,-0x40c(%rbp)\njmp 1261 \nmov -0x40c(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x418(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x20,%al\njne 125a \naddl $0x1,-0x408(%rbp)\naddl $0x1,-0x40c(%rbp)\nmov -0x40c(%rbp),%eax\ncmp -0x400(%rbp),%eax\njl 1239 \nmov -0x408(%rbp),%eax\nlea (%rax,%rax,1),%edx\nmov -0x400(%rbp),%eax\nadd %edx,%eax\nmov %eax,-0x3fc(%rbp)\ncmpl $0x3e8,-0x3fc(%rbp)\njle 129e \nlea 0xd6f(%rip),%rax\njmpq 13a4 \nmov -0x3fc(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0x404(%rbp)\nmov -0x3fc(%rbp),%eax\ncltq\nmovb $0x0,-0x3f0(%rbp,%rax,1)\nmov -0x400(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0x40c(%rbp)\njmpq 135d \nmov -0x40c(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x418(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x20,%al\njne 132a \nmov -0x404(%rbp),%eax\ncltq\nmovb $0x30,-0x3f0(%rbp,%rax,1)\nmov -0x404(%rbp),%eax\nsub $0x1,%eax\ncltq\nmovb $0x32,-0x3f0(%rbp,%rax,1)\nmov -0x404(%rbp),%eax\nsub $0x2,%eax\ncltq\nmovb $0x25,-0x3f0(%rbp,%rax,1)\nsubl $0x3,-0x404(%rbp)\njmp 1356 \nmov -0x40c(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x418(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%edx\nmov -0x404(%rbp),%eax\ncltq\nmov %dl,-0x3f0(%rbp,%rax,1)\nsubl $0x1,-0x404(%rbp)\nsubl $0x1,-0x40c(%rbp)\ncmpl $0x0,-0x40c(%rbp)\njns 12d1 \nmov -0x3fc(%rbp),%eax\nadd $0x1,%eax\ncltq\nmov %rax,%rdi\ncallq 10f0 \nmov %rax,-0x3f8(%rbp)\nlea -0x3f0(%rbp),%rdx\nmov -0x3f8(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10a0 \nmov -0x3f8(%rbp),%rax\nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 13b8 \ncallq 10c0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 420h\nmov [rbp+s], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_408], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_400], eax\nmov [rbp+var_40C], 0\njmp short loc_1261\nloc_1239:\nmov eax, [rbp+var_40C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njnz short loc_125A\nadd [rbp+var_408], 1\nloc_125A:\nadd [rbp+var_40C], 1\nloc_1261:\nmov eax, [rbp+var_40C]\ncmp eax, [rbp+var_400]\njl short loc_1239\nmov eax, [rbp+var_408]\nlea edx, [rax+rax]\nmov eax, [rbp+var_400]\nadd eax, edx\nmov [rbp+var_3FC], eax\ncmp [rbp+var_3FC], 3E8h\njle short loc_129E\nlea rax, unk_2008\njmp loc_13A4\nloc_129E:\nmov eax, [rbp+var_3FC]\nsub eax, 1\nmov [rbp+var_404], eax\nmov eax, [rbp+var_3FC]\ncdqe\nmov [rbp+rax+src], 0\nmov eax, [rbp+var_400]\nsub eax, 1\nmov [rbp+var_40C], eax\njmp loc_135D\nloc_12D1:\nmov eax, [rbp+var_40C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njnz short loc_132A\nmov eax, [rbp+var_404]\ncdqe\nmov [rbp+rax+src], 30h ; '0'\nmov eax, [rbp+var_404]\nsub eax, 1\ncdqe\nmov [rbp+rax+src], 32h ; '2'\nmov eax, [rbp+var_404]\nsub eax, 2\ncdqe\nmov [rbp+rax+src], 25h ; '%'\nsub [rbp+var_404], 3\njmp short loc_1356\nloc_132A:\nmov eax, [rbp+var_40C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_404]\ncdqe\nmov [rbp+rax+src], dl\nsub [rbp+var_404], 1\nloc_1356:\nsub [rbp+var_40C], 1\nloc_135D:\ncmp [rbp+var_40C], 0\njns loc_12D1\nmov eax, [rbp+var_3FC]\nadd eax, 1\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+dest], rax\nlea rdx, [rbp+src]\nmov rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\nmov rax, [rbp+dest]\nloc_13A4:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_13B8\ncall ___stack_chk_fail\nlocret_13B8:\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(const char *a1)\n{\n int i; // [rsp+14h] [rbp-40Ch]\n int j; // [rsp+14h] [rbp-40Ch]\n int v4; // [rsp+18h] [rbp-408h]\n int v5; // [rsp+1Ch] [rbp-404h]\n int v6; // [rsp+20h] [rbp-400h]\n int v7; // [rsp+24h] [rbp-3FCh]\n char *dest; // [rsp+28h] [rbp-3F8h]\n char src[1000]; // [rsp+30h] [rbp-3F0h] BYREF\n unsigned __int64 v10; // [rsp+418h] [rbp-8h]\n\n v10 = __readfsqword(0x28u);\n v4 = 0;\n v6 = strlen(a1);\n for ( i = 0; i < v6; ++i )\n {\n if ( a1[i] == 32 )\n ++v4;\n }\n v7 = 2 * v4 + v6;\n if ( v7 > 1000 )\n return (char *)&unk_2008;\n v5 = v7 - 1;\n src[v7] = 0;\n for ( j = v6 - 1; j >= 0; --j )\n {\n if ( a1[j] == 32 )\n {\n src[v5] = 48;\n src[v5 - 1] = 50;\n src[v5 - 2] = 37;\n v5 -= 3;\n }\n else\n {\n src[v5--] = a1[j];\n }\n }\n dest = (char *)malloc(v7 + 1);\n strcpy(dest, src);\n return dest;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 420h\nmov [rbp+s], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_408], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_400], eax\nmov [rbp+var_40C], 0\njmp short loc_1261\nloc_1239:\nmov eax, [rbp+var_40C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njnz short loc_125A\nadd [rbp+var_408], 1\nloc_125A:\nadd [rbp+var_40C], 1\nloc_1261:\nmov eax, [rbp+var_40C]\ncmp eax, [rbp+var_400]\njl short loc_1239\nmov eax, [rbp+var_408]\nlea edx, [rax+rax]\nmov eax, [rbp+var_400]\nadd eax, edx\nmov [rbp+var_3FC], eax\ncmp [rbp+var_3FC], 3E8h\njle short loc_129E\nlea rax, unk_2008\njmp loc_13A4\nloc_129E:\nmov eax, [rbp+var_3FC]\nsub eax, 1\nmov [rbp+var_404], eax\nmov eax, [rbp+var_3FC]\ncdqe\nmov [rbp+rax+src], 0\nmov eax, [rbp+var_400]\nsub eax, 1\nmov [rbp+var_40C], eax\njmp loc_135D\nloc_12D1:\nmov eax, [rbp+var_40C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njnz short loc_132A\nmov eax, [rbp+var_404]\ncdqe\nmov [rbp+rax+src], 30h ; '0'\nmov eax, [rbp+var_404]\nsub eax, 1\ncdqe\nmov [rbp+rax+src], 32h ; '2'\nmov eax, [rbp+var_404]\nsub eax, 2\ncdqe\nmov [rbp+rax+src], 25h ; '%'\nsub [rbp+var_404], 3\njmp short loc_1356\nloc_132A:\nmov eax, [rbp+var_40C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_404]\ncdqe\nmov [rbp+rax+src], dl\nsub [rbp+var_404], 1\nloc_1356:\nsub [rbp+var_40C], 1\nloc_135D:\ncmp [rbp+var_40C], 0\njns loc_12D1\nmov eax, [rbp+var_3FC]\nadd eax, 1\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+dest], rax\nlea rdx, [rbp+src]\nmov rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\nmov rax, [rbp+dest]\nloc_13A4:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_13B8\ncall ___stack_chk_fail\nlocret_13B8:\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11E9(const char *a1)\n{\n int i; // [rsp+14h] [rbp-40Ch]\n int j; // [rsp+14h] [rbp-40Ch]\n int v4; // [rsp+18h] [rbp-408h]\n int v5; // [rsp+1Ch] [rbp-404h]\n int v6; // [rsp+20h] [rbp-400h]\n int v7; // [rsp+24h] [rbp-3FCh]\n char *dest; // [rsp+28h] [rbp-3F8h]\n char src[1000]; // [rsp+30h] [rbp-3F0h] BYREF\n unsigned __int64 v10; // [rsp+418h] [rbp-8h]\n\n v10 = __readfsqword(0x28u);\n v4 = 0;\n v6 = strlen(a1);\n for ( i = 0; i < v6; ++i )\n {\n if ( a1[i] == 32 )\n ++v4;\n }\n v7 = 2 * v4 + v6;\n if ( v7 > 1000 )\n return (char *)&unk_2008;\n v5 = v7 - 1;\n src[v7] = 0;\n for ( j = v6 - 1; j >= 0; --j )\n {\n if ( a1[j] == 32 )\n {\n src[v5] = 48;\n src[v5 - 1] = 50;\n src[v5 - 2] = 37;\n v5 -= 3;\n }\n else\n {\n src[v5--] = a1[j];\n }\n }\n dest = (char *)malloc(v7 + 1);\n strcpy(dest, src);\n return dest;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11E9(const char *a1) {\n int i;\n int j;\n int v4;\n int v5;\n int v6;\n int v7;\n char *dest;\n char src[1000];\n unsigned long long v10;\n v10 = __readfsqword(40u);\n v4 = 0;\n v6 = strlen(a1);\n for (i = 0; i < v6; ++i) {\n if (a1[i] == 32) ++v4;\n }\n v7 = 2 * v4 + v6;\n if (v7 > 1000) return (char *)&unk_2008;\n v5 = v7 - 1;\n src[v7] = 0;\n for (j = v6 - 1; j >= 0; --j) {\n if (a1[j] == 32) {\n src[v5] = 48;\n src[v5 - 1] = 50;\n src[v5 - 2] = 37;\n v5 -= 3;\n } else {\n src[v5--] = a1[j];\n }\n }\n dest = (char *)malloc(v7 + 1);\n strcpy(dest, src);\n return dest;\n}", + "ida_pseudo_norm": "char *func0(const char *a1) {\n int i;\n int j;\n int v4;\n int v5;\n int v6;\n int v7;\n char *dest;\n char src[1000];\n unsigned long long v10;\n v10 = __readfsqword(40u);\n v4 = 0;\n v6 = strlen(a1);\n for (i = 0; i < v6; ++i) {\n if (a1[i] == 32) ++v4;\n }\n v7 = 2 * v4 + v6;\n if (v7 > 1000) return (char *)&unk_2008;\n v5 = v7 - 1;\n src[v7] = 0;\n for (j = v6 - 1; j >= 0; --j) {\n if (a1[j] == 32) {\n src[v5] = 48;\n src[v5 - 1] = 50;\n src[v5 - 2] = 37;\n v5 -= 3;\n } else {\n src[v5--] = a1[j];\n }\n }\n dest = (char *)malloc(v7 + 1);\n strcpy(dest, src);\n return dest;\n}" + }, + { + "index": 628, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n#define MAX 1000\n\n\n\n", + "func": "char* func0(char* string) {\n char new_string[MAX];\n int i, j, space_count = 0, new_length;\n char* result;\n i = strlen(string);\n for (j = 0; j < i; j++) {\n if (string[j] == ' ') space_count++;\n }\n new_length = i + space_count * 2;\n if (new_length > MAX) {\n return \"\";\n }\n int index = new_length - 1;\n new_string[new_length] = '\\0';\n for (j = i - 1; j >= 0; j--) {\n if (string[j] == ' ') {\n new_string[index] = '0';\n new_string[index - 1] = '2';\n new_string[index - 2] = '%';\n index -= 3;\n } else {\n new_string[index] = string[j];\n index--;\n }\n }\n result = (char*)malloc(new_length + 1);\n strcpy(result, new_string);\n return result;\n}", + "test": "int main() {\n\n\tassert(strcmp(func0(\"My Name is Dawood\"), \"My%20Name%20is%20Dawood\") == 0);\n\n\tassert(strcmp(func0(\"I am a Programmer\"), \"I%20am%20a%20Programmer\") == 0);\n\n\tassert(strcmp(func0(\"I love Coding\"), \"I%20love%20Coding\") == 0);\n\n\n\n\treturn 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nsub $0x3f0,%rsp\nmov %rdi,%r8\nmov %fs:0x28,%rax\nmov %rax,0x3e8(%rsp)\nxor %eax,%eax\nmov $0xffffffffffffffff,%rcx\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nsub $0x1,%rax\ntest %eax,%eax\njle 122b \nmov %r8,%rdx\nlea -0x1(%rax),%ecx\nlea 0x1(%r8,%rcx,1),%rdi\nmov $0x0,%ecx\ncmpb $0x20,(%rdx)\nsete %sil\nmovzbl %sil,%esi\nadd %esi,%ecx\nadd $0x1,%rdx\ncmp %rdi,%rdx\njne 11f2 \nlea (%rax,%rcx,2),%edi\nlea 0xe03(%rip),%rbx\ncmp $0x3e8,%edi\njg 124d \nlea -0x1(%rdi),%edx\nmovslq %edi,%rcx\nmovb $0x0,(%rsp,%rcx,1)\nsub $0x1,%eax\ncltq\njmp 127d \nmovslq %eax,%rdx\nmovb $0x0,(%rsp,%rdx,1)\nmov %eax,%edi\nadd $0x1,%edi\nmovslq %edi,%rdi\ncallq 10b0 \nmov %rax,%rbx\nmov %rsp,%rsi\nmov %rax,%rdi\ncallq 1080 \nmov 0x3e8(%rsp),%rax\nxor %fs:0x28,%rax\njne 12a7 \nmov %rbx,%rax\nadd $0x3f0,%rsp\npop %rbx\nretq\nmovslq %edx,%rsi\nmov %cl,(%rsp,%rsi,1)\nsub $0x1,%edx\nsub $0x1,%rax\ntest %eax,%eax\njs 1234 \nmovzbl (%r8,%rax,1),%ecx\ncmp $0x20,%cl\njne 126c \nmovslq %edx,%rcx\nmovb $0x30,(%rsp,%rcx,1)\nlea -0x1(%rdx),%ecx\nmovslq %ecx,%rcx\nmovb $0x32,(%rsp,%rcx,1)\nlea -0x2(%rdx),%ecx\nmovslq %ecx,%rcx\nmovb $0x25,(%rsp,%rcx,1)\nsub $0x3,%edx\njmp 1275 \ncallq 1090 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 3F8h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+408h+var_20], rax\nxor eax, eax\ncall _strlen\nmov rdi, rax\ntest eax, eax\njle loc_12B9\nmov rax, rbx\nlea edx, [rdi-1]\nlea rsi, [rbx+rdx+1]\nmov edx, 0\nloc_122C:\ncmp byte ptr [rax], 20h ; ' '\nsetz cl\nmovzx ecx, cl\nadd edx, ecx\nadd rax, 1\ncmp rax, rsi\njnz short loc_122C\nlea r8d, [rdi+rdx*2]\nlea rbp, aMyNameIsDawood+11h; \"\"\ncmp r8d, 3E8h\njg loc_12E2\nlea r9d, [r8-1]\nmovsxd rax, r8d\nmov [rsp+rax+408h+var_408], 0\nlea eax, [rdi-1]\ncdqe\nadd rax, rbx\nmovsxd rdx, edi\nlea rcx, [rbx+rdx-2]\nlea edx, [rdi-1]\nsub rcx, rdx\njmp short loc_12A5\nloc_127B:\nmovsxd rdx, r9d\nmov [rsp+rdx+408h+var_408], 30h ; '0'\nlea edx, [r9-1]\nmovsxd rdx, edx\nmov [rsp+rdx+408h+var_408], 32h ; '2'\nlea edx, [r9-2]\nmovsxd rdx, edx\nmov [rsp+rdx+408h+var_408], 25h ; '%'\nsub r9d, 3\nloc_129C:\nsub rax, 1\ncmp rax, rcx\njz short loc_12C2\nloc_12A5:\nmovzx edx, byte ptr [rax]\ncmp dl, 20h ; ' '\njz short loc_127B\nmovsxd rsi, r9d\nmov [rsp+rsi+408h+var_408], dl\nsub r9d, 1\njmp short loc_129C\nloc_12B9:\ncdqe\nmov [rsp+rax+408h+var_408], 0\nmov r8d, edi\nloc_12C2:\nlea ebx, [r8+1]\nmovsxd rbx, ebx\nmov rdi, rbx; size\ncall _malloc\nmov rbp, rax\nmov rsi, rsp\nmov rdx, rbx\nmov rdi, rax\ncall ___strcpy_chk\nloc_12E2:\nmov rax, [rsp+408h+var_20]\nsub rax, fs:28h\njnz short loc_1302\nmov rax, rbp\nadd rsp, 3F8h\npop rbx\npop rbp\nretn\nloc_1302:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(const char *a1)\n{\n int v2; // eax\n int v3; // edi\n const char *v4; // rax\n int v5; // edx\n int v6; // r8d\n char *v7; // rbp\n int v8; // r9d\n const char *v9; // rax\n size_t v10; // rbx\n _BYTE v12[1000]; // [rsp+0h] [rbp-408h] BYREF\n unsigned __int64 v13; // [rsp+3E8h] [rbp-20h]\n\n v13 = __readfsqword(0x28u);\n v2 = strlen(a1);\n v3 = v2;\n if ( v2 <= 0 )\n {\n v12[v2] = 0;\n v6 = v2;\nLABEL_11:\n v10 = v6 + 1;\n v7 = (char *)malloc(v10);\n __strcpy_chk(v7, v12, v10);\n return v7;\n }\n v4 = a1;\n v5 = 0;\n do\n v5 += *v4++ == 32;\n while ( v4 != &a1[v3 - 1 + 1] );\n v6 = v3 + 2 * v5;\n v7 = \"\";\n if ( v6 <= 1000 )\n {\n v8 = v6 - 1;\n v12[v6] = 0;\n v9 = &a1[v3 - 1];\n do\n {\n if ( *v9 == 32 )\n {\n v12[v8] = 48;\n v12[v8 - 1] = 50;\n v12[v8 - 2] = 37;\n v8 -= 3;\n }\n else\n {\n v12[v8--] = *v9;\n }\n --v9;\n }\n while ( v9 != &a1[v3 - 2 - (v3 - 1)] );\n goto LABEL_11;\n }\n return v7;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\npush rbx\nsub rsp, 3F8h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+408h+var_20], rax\nxor eax, eax\ncall _strlen\nmov rdi, rax\ntest eax, eax\njle loc_12B9\nmov rax, rbx\nlea edx, [rdi-1]\nlea rsi, [rbx+rdx+1]\nmov edx, 0\nloc_122C:\ncmp byte ptr [rax], 20h ; ' '\nsetz cl\nmovzx ecx, cl\nadd edx, ecx\nadd rax, 1\ncmp rax, rsi\njnz short loc_122C\nlea r8d, [rdi+rdx*2]\nlea rbp, aMyNameIsDawood+11h; \"\"\ncmp r8d, 3E8h\njg loc_12E2\nlea r9d, [r8-1]\nmovsxd rax, r8d\nmov [rsp+rax+408h+var_408], 0\nlea eax, [rdi-1]\ncdqe\nadd rax, rbx\nmovsxd rdx, edi\nlea rcx, [rbx+rdx-2]\nlea edx, [rdi-1]\nsub rcx, rdx\njmp short loc_12A5\nloc_127B:\nmovsxd rdx, r9d\nmov [rsp+rdx+408h+var_408], 30h ; '0'\nlea edx, [r9-1]\nmovsxd rdx, edx\nmov [rsp+rdx+408h+var_408], 32h ; '2'\nlea edx, [r9-2]\nmovsxd rdx, edx\nmov [rsp+rdx+408h+var_408], 25h ; '%'\nsub r9d, 3\nloc_129C:\nsub rax, 1\ncmp rax, rcx\njz short loc_12C2\nloc_12A5:\nmovzx edx, byte ptr [rax]\ncmp dl, 20h ; ' '\njz short loc_127B\nmovsxd rsi, r9d\nmov [rsp+rsi+408h+var_408], dl\nsub r9d, 1\njmp short loc_129C\nloc_12B9:\ncdqe\nmov [rsp+rax+408h+var_408], 0\nmov r8d, edi\nloc_12C2:\nlea ebx, [r8+1]\nmovsxd rbx, ebx\nmov rdi, rbx; size\ncall _malloc\nmov rbp, rax\nmov rsi, rsp\nmov rdx, rbx\nmov rdi, rax\ncall ___strcpy_chk\nloc_12E2:\nmov rax, [rsp+408h+var_20]\nsub rax, fs:28h\njnz short loc_1302\nmov rax, rbp\nadd rsp, 3F8h\npop rbx\npop rbp\nretn\nloc_1302:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_11E9(const char *a1)\n{\n int v2; // eax\n int v3; // edi\n const char *v4; // rax\n int v5; // edx\n int v6; // r8d\n char *v7; // rbp\n int v8; // r9d\n const char *v9; // rax\n size_t v10; // rbx\n _BYTE v12[1000]; // [rsp+0h] [rbp-408h] BYREF\n unsigned __int64 v13; // [rsp+3E8h] [rbp-20h]\n\n v13 = __readfsqword(0x28u);\n v2 = strlen(a1);\n v3 = v2;\n if ( v2 <= 0 )\n {\n v12[v2] = 0;\n v6 = v2;\nLABEL_11:\n v10 = v6 + 1;\n v7 = (char *)malloc(v10);\n __strcpy_chk(v7, v12, v10);\n return v7;\n }\n v4 = a1;\n v5 = 0;\n do\n v5 += *v4++ == 32;\n while ( v4 != &a1[v3 - 1 + 1] );\n v6 = v3 + 2 * v5;\n v7 = \"\";\n if ( v6 <= 1000 )\n {\n v8 = v6 - 1;\n v12[v6] = 0;\n v9 = &a1[v3 - 1];\n do\n {\n if ( *v9 == 32 )\n {\n v12[v8] = 48;\n v12[v8 - 1] = 50;\n v12[v8 - 2] = 37;\n v8 -= 3;\n }\n else\n {\n v12[v8--] = *v9;\n }\n --v9;\n }\n while ( v9 != &a1[v3 - 2 - (v3 - 1)] );\n goto LABEL_11;\n }\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11E9(const char *a1) {\n int v2;\n int v3;\n const char *v4;\n int v5;\n int v6;\n char *v7;\n int v8;\n const char *v9;\n unsigned int v10;\n uint8_t v12[1000];\n unsigned long long v13;\n v13 = __readfsqword(40u);\n v2 = strlen(a1);\n v3 = v2;\n if (v2 <= 0) {\n v12[v2] = 0;\n v6 = v2;\n LABEL_11:\n v10 = v6 + 1;\n v7 = (char *)malloc(v10);\n __strcpy_chk(v7, v12, v10);\n return v7;\n }\n v4 = a1;\n v5 = 0;\n do\n v5 += *v4++ == 32;\n while (v4 != &a1[v3 - 1 + 1]);\n v6 = v3 + 2 * v5;\n v7 = \"\";\n if (v6 <= 1000) {\n v8 = v6 - 1;\n v12[v6] = 0;\n v9 = &a1[v3 - 1];\n do {\n if (*v9 == 32) {\n v12[v8] = 48;\n v12[v8 - 1] = 50;\n v12[v8 - 2] = 37;\n v8 -= 3;\n } else {\n v12[v8--] = *v9;\n }\n --v9;\n } while (v9 != &a1[v3 - 2 - (v3 - 1)]);\n goto LABEL_11;\n }\n return v7;\n}", + "ida_pseudo_norm": "char *func0(const char *a1) {\n int v2;\n int v3;\n const char *v4;\n int v5;\n int v6;\n char *v7;\n int v8;\n const char *v9;\n unsigned int v10;\n uint8_t v12[1000];\n unsigned long long v13;\n v13 = __readfsqword(40u);\n v2 = strlen(a1);\n v3 = v2;\n if (v2 <= 0) {\n v12[v2] = 0;\n v6 = v2;\n LABEL_11:\n v10 = v6 + 1;\n v7 = (char *)malloc(v10);\n __strcpy_chk(v7, v12, v10);\n return v7;\n }\n v4 = a1;\n v5 = 0;\n do\n v5 += *v4++ == 32;\n while (v4 != &a1[v3 - 1 + 1]);\n v6 = v3 + 2 * v5;\n v7 = \"\";\n if (v6 <= 1000) {\n v8 = v6 - 1;\n v12[v6] = 0;\n v9 = &a1[v3 - 1];\n do {\n if (*v9 == 32) {\n v12[v8] = 48;\n v12[v8 - 1] = 50;\n v12[v8 - 2] = 37;\n v8 -= 3;\n } else {\n v12[v8--] = *v9;\n }\n --v9;\n } while (v9 != &a1[v3 - 2 - (v3 - 1)]);\n goto LABEL_11;\n }\n return v7;\n}" + }, + { + "index": 628, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n#define MAX 1000\n\n\n\n", + "func": "char* func0(char* string) {\n char new_string[MAX];\n int i, j, space_count = 0, new_length;\n char* result;\n i = strlen(string);\n for (j = 0; j < i; j++) {\n if (string[j] == ' ') space_count++;\n }\n new_length = i + space_count * 2;\n if (new_length > MAX) {\n return \"\";\n }\n int index = new_length - 1;\n new_string[new_length] = '\\0';\n for (j = i - 1; j >= 0; j--) {\n if (string[j] == ' ') {\n new_string[index] = '0';\n new_string[index - 1] = '2';\n new_string[index - 2] = '%';\n index -= 3;\n } else {\n new_string[index] = string[j];\n index--;\n }\n }\n result = (char*)malloc(new_length + 1);\n strcpy(result, new_string);\n return result;\n}", + "test": "int main() {\n\n\tassert(strcmp(func0(\"My Name is Dawood\"), \"My%20Name%20is%20Dawood\") == 0);\n\n\tassert(strcmp(func0(\"I am a Programmer\"), \"I%20am%20a%20Programmer\") == 0);\n\n\tassert(strcmp(func0(\"I love Coding\"), \"I%20love%20Coding\") == 0);\n\n\n\n\treturn 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\nsub $0x3f0,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x3e8(%rsp)\nxor %eax,%eax\ncallq 10a0 \ntest %eax,%eax\njle 13b0 \nlea -0x1(%rax),%esi\nmov %rbx,%rdx\nmov %rsi,%rcx\nlea 0x1(%rbx,%rsi,1),%rdi\nxor %esi,%esi\nxor %r8d,%r8d\ncmpb $0x20,(%rdx)\nsete %r8b\nadd $0x1,%rdx\nadd %r8d,%esi\ncmp %rdx,%rdi\njne 12f0 \nlea (%rax,%rsi,2),%r8d\nlea 0xd04(%rip),%r9\ncmp $0x3e8,%r8d\njg 138a \nmovslq %r8d,%rdx\nlea -0x1(%r8),%eax\nmovb $0x0,(%rsp,%rdx,1)\nmovslq %ecx,%rdx\njmp 1340 \nnopw 0x0(%rax,%rax,1)\ncltq\nsub $0x1,%rdx\nmov %sil,(%rsp,%rax,1)\nmov %ecx,%eax\ntest %edx,%edx\njs 1370 \nmovzbl (%rbx,%rdx,1),%esi\nlea -0x1(%rax),%ecx\ncmp $0x20,%sil\njne 1330 \nmovslq %eax,%rsi\nmovslq %ecx,%rcx\nsub $0x1,%rdx\nmovb $0x30,(%rsp,%rsi,1)\nmovb $0x32,(%rsp,%rcx,1)\nlea -0x2(%rax),%ecx\nsub $0x3,%eax\nmovslq %ecx,%rcx\nmovb $0x25,(%rsp,%rcx,1)\ntest %edx,%edx\njns 1340 \nlea 0x1(%r8),%eax\nmovslq %eax,%rdi\ncallq 10d0 \nmov %rsp,%rsi\nmov %rax,%rdi\ncallq 1090 \nmov %rax,%r9\nmov 0x3e8(%rsp),%rax\nxor %fs:0x28,%rax\njne 13bc \nadd $0x3f0,%rsp\nmov %r9,%rax\npop %rbx\nretq\nnopl 0x0(%rax)\nmovslq %eax,%rdx\nmov %eax,%r8d\nmovb $0x0,(%rsp,%rdx,1)\njmp 1370 \ncallq 10b0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 3F8h\nmov rax, fs:28h\nmov [rsp+408h+var_20], rax\nxor eax, eax\ncall _strlen\ntest eax, eax\njle loc_13C8\nlea r9d, [rax-1]\nmov rdx, rbp\nxor ecx, ecx\nmov rsi, r9\nlea r8, [rbp+r9+1]\nnop dword ptr [rax+00000000h]\nloc_1308:\nxor edi, edi\ncmp byte ptr [rdx], 20h ; ' '\nsetz dil\nadd rdx, 1\nadd ecx, edi\ncmp rdx, r8\njnz short loc_1308\nlea ebx, [rax+rcx*2]\nlea rcx, aMyNameIsDawood+11h; \"\"\ncmp ebx, 3E8h\njg short loc_13A4\ncdqe\nmovsxd rdx, ebx\nlea ecx, [rbx-1]\nmovsxd rsi, esi\nlea r8, [rbp+rax-2]\nmov [rsp+rdx+408h+var_408], 0\nadd rsi, rbp\nmovzx edx, cs:word_216E\nsub r8, r9\nmov rbp, rsp\njmp short loc_135A\nloc_1358:\nmov ecx, edi\nloc_135A:\nmovzx eax, byte ptr [rsi]\nlea edi, [rcx-1]\ncmp al, 20h ; ' '\njnz short loc_1376\nlea eax, [rcx-2]\nlea edi, [rcx-3]\ncdqe\nmov [rbp+rax+0], dx\nmov eax, 30h ; '0'\nloc_1376:\nmovsxd rcx, ecx\nsub rsi, 1\nmov [rsp+rcx+408h+var_408], al\ncmp rsi, r8\njnz short loc_1358\nloc_1385:\nadd ebx, 1\nmovsxd rbx, ebx\nmov rdi, rbx; size\ncall _malloc\nmov rdx, rbx\nmov rsi, rbp\nmov rdi, rax\ncall ___strcpy_chk\nmov rcx, rax\nloc_13A4:\nmov rax, [rsp+408h+var_20]\nsub rax, fs:28h\njnz short loc_13D6\nadd rsp, 3F8h\nmov rax, rcx\npop rbx\npop rbp\nretn\nloc_13C8:\nmovsxd rdx, eax\nmov ebx, eax\nmov rbp, rsp\nmov [rsp+rdx+408h+var_408], 0\njmp short loc_1385\nloc_13D6:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v2; // eax\n __int64 v3; // r9\n const char *v4; // rdx\n int v5; // ecx\n __int64 v6; // r8\n int v7; // edi\n int v8; // ebx\n char *v9; // rcx\n int v10; // ecx\n char *v11; // rsi\n const char *v12; // r8\n char v13; // al\n int v14; // edi\n size_t v15; // rbx\n void *v16; // rax\n _BYTE v18[1000]; // [rsp+0h] [rbp-408h] BYREF\n unsigned __int64 v19; // [rsp+3E8h] [rbp-20h]\n\n v19 = __readfsqword(0x28u);\n v2 = strlen(a1);\n if ( v2 <= 0 )\n {\n v8 = v2;\n v18[v2] = 0;\nLABEL_10:\n v15 = v8 + 1;\n v16 = malloc(v15);\n return __strcpy_chk(v16, v18, v15);\n }\n v3 = (unsigned int)(v2 - 1);\n v4 = a1;\n v5 = 0;\n v6 = (__int64)&a1[v3 + 1];\n do\n {\n v7 = *v4++ == 32;\n v5 += v7;\n }\n while ( v4 != (const char *)v6 );\n v8 = v2 + 2 * v5;\n v9 = \"\";\n if ( v8 <= 1000 )\n {\n v10 = v8 - 1;\n v18[v8] = 0;\n v11 = (char *)&a1[(int)v3];\n v12 = &a1[v2 - 2 - v3];\n while ( 1 )\n {\n v13 = *v11;\n v14 = v10 - 1;\n if ( *v11 == 32 )\n {\n v14 = v10 - 3;\n *(_WORD *)&v18[v10 - 2] = 12837;\n v13 = 48;\n }\n --v11;\n v18[v10] = v13;\n if ( v11 == v12 )\n break;\n v10 = v14;\n }\n goto LABEL_10;\n }\n return (__int64)v9;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 3F8h\nmov rax, fs:28h\nmov [rsp+408h+var_20], rax\nxor eax, eax\ncall _strlen\ntest eax, eax\njle loc_13C8\nlea r9d, [rax-1]\nmov rdx, rbp\nxor ecx, ecx\nmov rsi, r9\nlea r8, [rbp+r9+1]\nnop dword ptr [rax+00000000h]\nloc_1308:\nxor edi, edi\ncmp byte ptr [rdx], 20h ; ' '\nsetz dil\nadd rdx, 1\nadd ecx, edi\ncmp rdx, r8\njnz short loc_1308\nlea ebx, [rax+rcx*2]\nlea rcx, aMyNameIsDawood+11h; \"\"\ncmp ebx, 3E8h\njg short loc_13A4\ncdqe\nmovsxd rdx, ebx\nlea ecx, [rbx-1]\nmovsxd rsi, esi\nlea r8, [rbp+rax-2]\nmov [rsp+rdx+408h+var_408], 0\nadd rsi, rbp\nmovzx edx, cs:word_216E\nsub r8, r9\nmov rbp, rsp\njmp short loc_135A\nloc_1358:\nmov ecx, edi\nloc_135A:\nmovzx eax, byte ptr [rsi]\nlea edi, [rcx-1]\ncmp al, 20h ; ' '\njnz short loc_1376\nlea eax, [rcx-2]\nlea edi, [rcx-3]\ncdqe\nmov [rbp+rax+0], dx\nmov eax, 30h ; '0'\nloc_1376:\nmovsxd rcx, ecx\nsub rsi, 1\nmov [rsp+rcx+408h+var_408], al\ncmp rsi, r8\njnz short loc_1358\nloc_1385:\nadd ebx, 1\nmovsxd rbx, ebx\nmov rdi, rbx; size\ncall _malloc\nmov rdx, rbx\nmov rsi, rbp\nmov rdi, rax\ncall ___strcpy_chk\nmov rcx, rax\nloc_13A4:\nmov rax, [rsp+408h+var_20]\nsub rax, fs:28h\njnz short loc_13D6\nadd rsp, 3F8h\nmov rax, rcx\npop rbx\npop rbp\nretn\nloc_13C8:\nmovsxd rdx, eax\nmov ebx, eax\nmov rbp, rsp\nmov [rsp+rdx+408h+var_408], 0\njmp short loc_1385\nloc_13D6:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12C0(const char *a1)\n{\n int v2; // eax\n __int64 v3; // r9\n const char *v4; // rdx\n int v5; // ecx\n __int64 v6; // r8\n int v7; // edi\n int v8; // ebx\n char *v9; // rcx\n int v10; // ecx\n char *v11; // rsi\n const char *v12; // r8\n char v13; // al\n int v14; // edi\n size_t v15; // rbx\n void *v16; // rax\n _BYTE v18[1000]; // [rsp+0h] [rbp-408h] BYREF\n unsigned __int64 v19; // [rsp+3E8h] [rbp-20h]\n\n v19 = __readfsqword(0x28u);\n v2 = strlen(a1);\n if ( v2 <= 0 )\n {\n v8 = v2;\n v18[v2] = 0;\nLABEL_10:\n v15 = v8 + 1;\n v16 = malloc(v15);\n return __strcpy_chk(v16, v18, v15);\n }\n v3 = (unsigned int)(v2 - 1);\n v4 = a1;\n v5 = 0;\n v6 = (__int64)&a1[v3 + 1];\n do\n {\n v7 = *v4++ == 32;\n v5 += v7;\n }\n while ( v4 != (const char *)v6 );\n v8 = v2 + 2 * v5;\n v9 = \"\";\n if ( v8 <= 1000 )\n {\n v10 = v8 - 1;\n v18[v8] = 0;\n v11 = (char *)&a1[(int)v3];\n v12 = &a1[v2 - 2 - v3];\n while ( 1 )\n {\n v13 = *v11;\n v14 = v10 - 1;\n if ( *v11 == 32 )\n {\n v14 = v10 - 3;\n *(_WORD *)&v18[v10 - 2] = 12837;\n v13 = 48;\n }\n --v11;\n v18[v10] = v13;\n if ( v11 == v12 )\n break;\n v10 = v14;\n }\n goto LABEL_10;\n }\n return (__int64)v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12C0(const char *a1) {\n int v2;\n long long v3;\n const char *v4;\n int v5;\n long long v6;\n int v7;\n int v8;\n char *v9;\n int v10;\n char *v11;\n const char *v12;\n char v13;\n int v14;\n unsigned int v15;\n void *v16;\n uint8_t v18[1000];\n unsigned long long v19;\n v19 = __readfsqword(40u);\n v2 = strlen(a1);\n if (v2 <= 0) {\n v8 = v2;\n v18[v2] = 0;\n LABEL_10:\n v15 = v8 + 1;\n v16 = malloc(v15);\n return __strcpy_chk(v16, v18, v15);\n }\n v3 = (unsigned int)(v2 - 1);\n v4 = a1;\n v5 = 0;\n v6 = (long long)&a1[v3 + 1];\n do {\n v7 = *v4++ == 32;\n v5 += v7;\n } while (v4 != (const char *)v6);\n v8 = v2 + 2 * v5;\n v9 = \"\";\n if (v8 <= 1000) {\n v10 = v8 - 1;\n v18[v8] = 0;\n v11 = (char *)&a1[(int)v3];\n v12 = &a1[v2 - 2 - v3];\n while (1) {\n v13 = *v11;\n v14 = v10 - 1;\n if (*v11 == 32) {\n v14 = v10 - 3;\n *(unsigned short *)&v18[v10 - 2] = 12837;\n v13 = 48;\n }\n --v11;\n v18[v10] = v13;\n if (v11 == v12) break;\n v10 = v14;\n }\n goto LABEL_10;\n }\n return (long long)v9;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v2;\n long long v3;\n const char *v4;\n int v5;\n long long v6;\n int v7;\n int v8;\n char *v9;\n int v10;\n char *v11;\n const char *v12;\n char v13;\n int v14;\n unsigned int v15;\n void *v16;\n uint8_t v18[1000];\n unsigned long long v19;\n v19 = __readfsqword(40u);\n v2 = strlen(a1);\n if (v2 <= 0) {\n v8 = v2;\n v18[v2] = 0;\n LABEL_10:\n v15 = v8 + 1;\n v16 = malloc(v15);\n return __strcpy_chk(v16, v18, v15);\n }\n v3 = (unsigned int)(v2 - 1);\n v4 = a1;\n v5 = 0;\n v6 = (long long)&a1[v3 + 1];\n do {\n v7 = *v4++ == 32;\n v5 += v7;\n } while (v4 != (const char *)v6);\n v8 = v2 + 2 * v5;\n v9 = \"\";\n if (v8 <= 1000) {\n v10 = v8 - 1;\n v18[v8] = 0;\n v11 = (char *)&a1[(int)v3];\n v12 = &a1[v2 - 2 - v3];\n while (1) {\n v13 = *v11;\n v14 = v10 - 1;\n if (*v11 == 32) {\n v14 = v10 - 3;\n *(unsigned short *)&v18[v10 - 2] = 12837;\n v13 = 48;\n }\n --v11;\n v18[v10] = v13;\n if (v11 == v12) break;\n v10 = v14;\n }\n goto LABEL_10;\n }\n return (long long)v9;\n}" + }, + { + "index": 628, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n#define MAX 1000\n\n\n\n", + "func": "char* func0(char* string) {\n char new_string[MAX];\n int i, j, space_count = 0, new_length;\n char* result;\n i = strlen(string);\n for (j = 0; j < i; j++) {\n if (string[j] == ' ') space_count++;\n }\n new_length = i + space_count * 2;\n if (new_length > MAX) {\n return \"\";\n }\n int index = new_length - 1;\n new_string[new_length] = '\\0';\n for (j = i - 1; j >= 0; j--) {\n if (string[j] == ' ') {\n new_string[index] = '0';\n new_string[index - 1] = '2';\n new_string[index - 2] = '%';\n index -= 3;\n } else {\n new_string[index] = string[j];\n index--;\n }\n }\n result = (char*)malloc(new_length + 1);\n strcpy(result, new_string);\n return result;\n}", + "test": "int main() {\n\n\tassert(strcmp(func0(\"My Name is Dawood\"), \"My%20Name%20is%20Dawood\") == 0);\n\n\tassert(strcmp(func0(\"I am a Programmer\"), \"I%20am%20a%20Programmer\") == 0);\n\n\tassert(strcmp(func0(\"I love Coding\"), \"I%20love%20Coding\") == 0);\n\n\n\n\treturn 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\nsub $0x3f0,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x3e8(%rsp)\nxor %eax,%eax\ncallq 10a0 \ntest %eax,%eax\njle 15e8 \nlea -0x1(%rax),%ecx\ncmp $0xe,%ecx\njbe 15d8 \nmov %eax,%esi\npxor %xmm1,%xmm1\npxor %xmm5,%xmm5\nmov %rbx,%rdx\nshr $0x4,%esi\nmovdqa 0xe8d(%rip),%xmm7\nmovdqa 0xe95(%rip),%xmm6\npxor %xmm4,%xmm4\nshl $0x4,%rsi\nadd %rbx,%rsi\nnopw %cs:0x0(%rax,%rax,1)\nmovdqu (%rdx),%xmm0\nmovdqa %xmm5,%xmm3\nadd $0x10,%rdx\npcmpeqb %xmm7,%xmm0\npand %xmm6,%xmm0\npcmpgtb %xmm0,%xmm3\nmovdqa %xmm0,%xmm2\npunpcklbw %xmm3,%xmm2\npunpckhbw %xmm3,%xmm0\nmovdqa %xmm4,%xmm3\npcmpgtw %xmm2,%xmm3\nmovdqa %xmm2,%xmm8\npunpcklwd %xmm3,%xmm8\npunpckhwd %xmm3,%xmm2\nmovdqa %xmm0,%xmm3\npaddd %xmm8,%xmm1\npaddd %xmm2,%xmm1\nmovdqa %xmm4,%xmm2\npcmpgtw %xmm0,%xmm2\npunpcklwd %xmm2,%xmm3\npunpckhwd %xmm2,%xmm0\npaddd %xmm3,%xmm1\npaddd %xmm0,%xmm1\ncmp %rsi,%rdx\njne 1320 \nmovdqa %xmm1,%xmm0\nmov %eax,%esi\npsrldq $0x8,%xmm0\nand $0xfffffff0,%esi\npaddd %xmm1,%xmm0\nmovdqa %xmm0,%xmm1\npsrldq $0x4,%xmm1\npaddd %xmm1,%xmm0\nmovd %xmm0,%edx\ntest $0xf,%al\nje 1538 \nmovslq %esi,%rdi\ncmpb $0x20,(%rbx,%rdi,1)\nsete %dil\nmovzbl %dil,%edi\nadd %edi,%edx\nlea 0x1(%rsi),%edi\ncmp %eax,%edi\njge 1538 \nmovslq %edi,%rdi\ncmpb $0x20,(%rbx,%rdi,1)\nsete %dil\nmovzbl %dil,%edi\nadd %edi,%edx\nlea 0x2(%rsi),%edi\ncmp %edi,%eax\njle 1538 \nmovslq %edi,%rdi\ncmpb $0x20,(%rbx,%rdi,1)\nsete %dil\nmovzbl %dil,%edi\nadd %edi,%edx\nlea 0x3(%rsi),%edi\ncmp %edi,%eax\njle 1538 \nmovslq %edi,%rdi\ncmpb $0x20,(%rbx,%rdi,1)\nsete %dil\nmovzbl %dil,%edi\nadd %edi,%edx\nlea 0x4(%rsi),%edi\ncmp %edi,%eax\njle 1538 \nmovslq %edi,%rdi\ncmpb $0x20,(%rbx,%rdi,1)\nsete %dil\nmovzbl %dil,%edi\nadd %edi,%edx\nlea 0x5(%rsi),%edi\ncmp %edi,%eax\njle 1538 \nmovslq %edi,%rdi\ncmpb $0x20,(%rbx,%rdi,1)\nsete %dil\nmovzbl %dil,%edi\nadd %edi,%edx\nlea 0x6(%rsi),%edi\ncmp %edi,%eax\njle 1538 \nmovslq %edi,%rdi\ncmpb $0x20,(%rbx,%rdi,1)\nsete %dil\nmovzbl %dil,%edi\nadd %edi,%edx\nlea 0x7(%rsi),%edi\ncmp %edi,%eax\njle 1538 \nmovslq %edi,%rdi\ncmpb $0x20,(%rbx,%rdi,1)\nsete %dil\nmovzbl %dil,%edi\nadd %edi,%edx\nlea 0x8(%rsi),%edi\ncmp %edi,%eax\njle 1538 \nmovslq %edi,%rdi\ncmpb $0x20,(%rbx,%rdi,1)\nsete %dil\nmovzbl %dil,%edi\nadd %edi,%edx\nlea 0x9(%rsi),%edi\ncmp %edi,%eax\njle 1538 \nmovslq %edi,%rdi\ncmpb $0x20,(%rbx,%rdi,1)\nsete %dil\nmovzbl %dil,%edi\nadd %edi,%edx\nlea 0xa(%rsi),%edi\ncmp %edi,%eax\njle 1538 \nmovslq %edi,%rdi\ncmpb $0x20,(%rbx,%rdi,1)\nsete %dil\nmovzbl %dil,%edi\nadd %edi,%edx\nlea 0xb(%rsi),%edi\ncmp %edi,%eax\njle 1538 \nmovslq %edi,%rdi\ncmpb $0x20,(%rbx,%rdi,1)\nsete %dil\nmovzbl %dil,%edi\nadd %edi,%edx\nlea 0xc(%rsi),%edi\ncmp %edi,%eax\njle 1538 \nmovslq %edi,%rdi\ncmpb $0x20,(%rbx,%rdi,1)\nsete %dil\nmovzbl %dil,%edi\nadd %edi,%edx\nlea 0xd(%rsi),%edi\ncmp %edi,%eax\njle 1538 \nmovslq %edi,%rdi\ncmpb $0x20,(%rbx,%rdi,1)\nsete %dil\nadd $0xe,%esi\nmovzbl %dil,%edi\nadd %edi,%edx\ncmp %esi,%eax\njle 1538 \nmovslq %esi,%rsi\ncmpb $0x20,(%rbx,%rsi,1)\nsete %sil\nmovzbl %sil,%esi\nadd %esi,%edx\nnopl 0x0(%rax)\nlea (%rax,%rdx,2),%esi\nlea 0xad3(%rip),%r8\ncmp $0x3e8,%esi\njg 15b9 \nmovslq %esi,%rdx\nlea -0x1(%rsi),%eax\nmovb $0x0,(%rsp,%rdx,1)\nmovslq %ecx,%rdx\njmp 1570 \nnopl 0x0(%rax)\ncltq\nsub $0x1,%rdx\nmov %dil,(%rsp,%rax,1)\nmov %ecx,%eax\ntest %edx,%edx\njs 15a0 \nmovzbl (%rbx,%rdx,1),%edi\nlea -0x1(%rax),%ecx\ncmp $0x20,%dil\njne 1560 \nmovslq %eax,%rdi\nmovslq %ecx,%rcx\nsub $0x1,%rdx\nmovb $0x30,(%rsp,%rdi,1)\nmovb $0x32,(%rsp,%rcx,1)\nlea -0x2(%rax),%ecx\nsub $0x3,%eax\nmovslq %ecx,%rcx\nmovb $0x25,(%rsp,%rcx,1)\ntest %edx,%edx\njns 1570 \nlea 0x1(%rsi),%eax\nmovslq %eax,%rdi\ncallq 10d0 \nmov %rsp,%rsi\nmov %rax,%rdi\ncallq 1090 \nmov %rax,%r8\nmov 0x3e8(%rsp),%rax\nxor %fs:0x28,%rax\njne 15f3 \nadd $0x3f0,%rsp\nmov %r8,%rax\npop %rbx\nretq\nxor %edx,%edx\nxor %esi,%esi\njmpq 13af \nnopl 0x0(%rax)\nmovslq %eax,%rdx\nmov %eax,%esi\nmovb $0x0,(%rsp,%rdx,1)\njmp 15a0 \ncallq 10b0 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 3F8h\nmov rax, fs:28h\nmov [rsp+408h+var_20], rax\nxor eax, eax\ncall _strlen\nmov rsi, rax\ntest eax, eax\njle loc_1578\nlea edi, [rax-1]\ncmp edi, 0Eh\njbe loc_1620\nmov edx, esi\npxor xmm1, xmm1\npxor xmm5, xmm5\nmov rax, rbx\nshr edx, 4\nmovdqa xmm6, cs:xmmword_2170\npxor xmm4, xmm4\nshl rdx, 4\nadd rdx, rbx\nnop word ptr [rax+rax+00h]\nloc_1328:\nmovdqu xmm0, xmmword ptr [rax]\nmovdqa xmm3, xmm5\nadd rax, 10h\npcmpeqb xmm0, xmm6\npcmpgtb xmm3, xmm0\nmovdqa xmm2, xmm0\npunpcklbw xmm2, xmm3\npunpckhbw xmm0, xmm3\nmovdqa xmm3, xmm4\npcmpgtw xmm3, xmm2\nmovdqa xmm7, xmm2\npunpcklwd xmm7, xmm3\npunpckhwd xmm2, xmm3\nmovdqa xmm3, xmm0\npsubd xmm1, xmm7\npsubd xmm1, xmm2\nmovdqa xmm2, xmm4\npcmpgtw xmm2, xmm0\npunpcklwd xmm3, xmm2\npunpckhwd xmm0, xmm2\npsubd xmm1, xmm3\npsubd xmm1, xmm0\ncmp rax, rdx\njnz short loc_1328\nmovdqa xmm0, xmm1\nmov r8d, esi\npsrldq xmm0, 8\nand r8d, 0FFFFFFF0h\npaddd xmm0, xmm1\nmov edx, r8d\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\npaddd xmm0, xmm2\nmovd eax, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm1, 8\npaddd xmm0, xmm1\ntest sil, 0Fh\njz loc_14EB\nloc_13C4:\nmov ecx, esi\nsub ecx, r8d\nlea r9d, [rcx-1]\ncmp r9d, 6\njbe loc_1468\nmovq xmm2, qword ptr cs:xmmword_2170\nmovq xmm1, qword ptr [rbx+r8]\npcmpeqb xmm1, xmm2\npxor xmm2, xmm2\npcmpgtb xmm2, xmm1\nmovdqa xmm3, xmm1\npunpcklbw xmm3, xmm2\npunpcklbw xmm1, xmm2\npxor xmm2, xmm2\nmovdqa xmm4, xmm2\nmovdqa xmm5, xmm3\npshufd xmm1, xmm1, 4Eh ; 'N'\npcmpgtw xmm4, xmm3\npcmpgtw xmm2, xmm1\npunpcklwd xmm5, xmm4\npunpcklwd xmm3, xmm4\npsubd xmm0, xmm5\npshufd xmm3, xmm3, 4Eh ; 'N'\npsubd xmm0, xmm3\nmovdqa xmm3, xmm1\npunpcklwd xmm1, xmm2\npunpcklwd xmm3, xmm2\npshufd xmm1, xmm1, 4Eh ; 'N'\npsubd xmm0, xmm3\npsubd xmm0, xmm1\nmovd r8d, xmm0\npshufd xmm6, xmm0, 0E5h\nmovd eax, xmm6\nadd eax, r8d\nmov r8d, ecx\nand r8d, 0FFFFFFF8h\nadd edx, r8d\nand ecx, 7\njz loc_14EB\nloc_1468:\nmovsxd rcx, edx\ncmp byte ptr [rbx+rcx], 20h ; ' '\njz loc_15D0\nloc_1475:\nlea ecx, [rdx+1]\ncmp esi, ecx\njle short loc_14EB\nmovsxd rcx, ecx\ncmp byte ptr [rbx+rcx], 20h ; ' '\njz loc_15E0\nloc_1489:\nlea ecx, [rdx+2]\ncmp ecx, esi\njge short loc_14EB\nmovsxd rcx, ecx\ncmp byte ptr [rbx+rcx], 20h ; ' '\njz loc_15F0\nloc_149D:\nlea ecx, [rdx+3]\ncmp esi, ecx\njle short loc_14EB\nmovsxd rcx, ecx\ncmp byte ptr [rbx+rcx], 20h ; ' '\njz loc_1600\nlea ecx, [rdx+4]\ncmp esi, ecx\njle short loc_14EB\nloc_14B8:\nmovsxd rcx, ecx\ncmp byte ptr [rbx+rcx], 20h ; ' '\njnz short loc_14C4\nadd eax, 1\nloc_14C4:\nlea ecx, [rdx+5]\ncmp esi, ecx\njle short loc_14EB\nmovsxd rcx, ecx\ncmp byte ptr [rbx+rcx], 20h ; ' '\njnz short loc_14D7\nadd eax, 1\nloc_14D7:\nadd edx, 6\ncmp esi, edx\njle short loc_14EB\nmovsxd rdx, edx\ncmp byte ptr [rbx+rdx], 20h ; ' '\njz loc_1618\nloc_14EB:\nlea edx, [rsi+rax*2]\nlea rcx, aMyNameIsDawood+11h; \"\"\ncmp edx, 3E8h\njg loc_15A7\nmovsxd rax, edx\nmovsxd rsi, esi\nlea ecx, [rdx-1]\nmov rbp, rsp\nmov [rsp+rax+408h+var_408], 0\nlea r8, [rbx+rsi-2]\nmovsxd rax, edi\nmov edi, edi\nmovzx r9d, cs:word_2180\nadd rax, rbx\nsub r8, rdi\nloc_1529:\nmovzx esi, byte ptr [rax]\ncmp sil, 20h ; ' '\njz short loc_154E\nloc_1532:\nmovsxd rdi, ecx\nsub rax, 1\nmov [rsp+rdi+408h+var_408], sil\ncmp rax, r8\njz short loc_1588\nmovzx esi, byte ptr [rax]\nsub ecx, 1\ncmp sil, 20h ; ' '\njnz short loc_1532\nloc_154E:\nlea esi, [rcx-2]\nsub rax, 1\nmovsxd rsi, esi\nmov [rbp+rsi+0], r9w\nlea esi, [rcx-3]\nmovsxd rcx, ecx\nmov [rsp+rcx+408h+var_408], 30h ; '0'\ncmp rax, r8\njz short loc_1588\nmov ecx, esi\njmp short loc_1529\nloc_1578:\ncdqe\nmov edx, esi\nmov rbp, rsp\nmov [rsp+rax+408h+var_408], 0\nnop dword ptr [rax+rax+00h]\nloc_1588:\nlea ebx, [rdx+1]\nmovsxd rbx, ebx\nmov rdi, rbx; size\ncall _malloc\nmov rdx, rbx\nmov rsi, rbp\nmov rdi, rax\ncall ___strcpy_chk\nmov rcx, rax\nloc_15A7:\nmov rax, [rsp+408h+var_20]\nsub rax, fs:28h\njnz short loc_1630\nadd rsp, 3F8h\nmov rax, rcx\npop rbx\npop rbp\nretn\nloc_15D0:\nadd eax, 1\njmp loc_1475\nloc_15E0:\nadd eax, 1\njmp loc_1489\nloc_15F0:\nadd eax, 1\njmp loc_149D\nloc_1600:\nlea ecx, [rdx+4]\nadd eax, 1\ncmp esi, ecx\njg loc_14B8\njmp loc_14EB\nloc_1618:\nadd eax, 1\njmp loc_14EB\nloc_1620:\npxor xmm0, xmm0\nxor r8d, r8d\nxor eax, eax\nxor edx, edx\njmp loc_13C4\nloc_1630:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, __m128i a2)\n{\n int v3; // eax\n int v4; // esi\n int v5; // edi\n __m128i v6; // xmm1\n const __m128i *v7; // rax\n __m128i si128; // xmm6\n __m128i v9; // xmm0\n __m128i v10; // xmm0\n __m128i v11; // xmm3\n __m128i v12; // xmm2\n __m128i v13; // xmm0\n __m128i v14; // xmm3\n __m128i v15; // xmm1\n __m128i v16; // xmm2\n __int64 v17; // r8\n __m128i v18; // xmm0\n signed int v19; // edx\n int v20; // eax\n int v21; // ecx\n __m128i v22; // xmm1\n __m128i v23; // xmm3\n __m128i v24; // xmm1\n __m128i v25; // xmm3\n __m128i v26; // xmm0\n __m128i v27; // xmm3\n int v28; // ecx\n int v29; // edx\n int v30; // edx\n char *v31; // rcx\n int v32; // ecx\n const char *v33; // rax\n __int64 v34; // r8\n char v35; // si\n size_t v36; // rbx\n void *v37; // rax\n _BYTE v39[1000]; // [rsp+0h] [rbp-408h] BYREF\n unsigned __int64 v40; // [rsp+3E8h] [rbp-20h]\n\n v40 = __readfsqword(0x28u);\n v3 = strlen(a1);\n v4 = v3;\n if ( v3 <= 0 )\n {\n v30 = v3;\n v39[v3] = 0;\nLABEL_35:\n v36 = v30 + 1;\n v37 = malloc(v36);\n return __strcpy_chk(v37, v39, v36, *(double *)a2.m128i_i64);\n }\n v5 = v3 - 1;\n if ( (unsigned int)(v3 - 1) <= 0xE )\n {\n a2 = 0LL;\n v17 = 0LL;\n v20 = 0;\n v19 = 0;\n }\n else\n {\n v6 = 0LL;\n v7 = (const __m128i *)a1;\n si128 = _mm_load_si128((const __m128i *)&xmmword_2170);\n do\n {\n v9 = _mm_loadu_si128(v7++);\n v10 = _mm_cmpeq_epi8(v9, si128);\n v11 = _mm_cmpgt_epi8((__m128i)0LL, v10);\n v12 = _mm_unpacklo_epi8(v10, v11);\n v13 = _mm_unpackhi_epi8(v10, v11);\n v14 = _mm_cmpgt_epi16((__m128i)0LL, v12);\n v15 = _mm_sub_epi32(_mm_sub_epi32(v6, _mm_unpacklo_epi16(v12, v14)), _mm_unpackhi_epi16(v12, v14));\n v16 = _mm_cmpgt_epi16((__m128i)0LL, v13);\n v6 = _mm_sub_epi32(_mm_sub_epi32(v15, _mm_unpacklo_epi16(v13, v16)), _mm_unpackhi_epi16(v13, v16));\n }\n while ( v7 != (const __m128i *)&a1[16 * ((unsigned int)v4 >> 4)] );\n v17 = v4 & 0xFFFFFFF0;\n v18 = _mm_add_epi32(_mm_srli_si128(v6, 8), v6);\n v19 = v4 & 0xFFFFFFF0;\n v20 = _mm_cvtsi128_si32(_mm_add_epi32(v18, _mm_srli_si128(v18, 4)));\n a2 = _mm_add_epi32(v6, _mm_srli_si128(v6, 8));\n if ( (v4 & 0xF) == 0 )\n goto LABEL_27;\n }\n v21 = v4 - v17;\n if ( (unsigned int)(v4 - v17 - 1) <= 6 )\n goto LABEL_16;\n v22 = _mm_cmpeq_epi8(_mm_loadl_epi64((const __m128i *)&a1[v17]), _mm_loadl_epi64((const __m128i *)&xmmword_2170));\n v23 = _mm_unpacklo_epi8(v22, _mm_cmpgt_epi8((__m128i)0LL, v22));\n v24 = _mm_shuffle_epi32(v23, 78);\n v25 = _mm_unpacklo_epi16(v23, _mm_cmpgt_epi16((__m128i)0LL, v23));\n v26 = _mm_sub_epi32(_mm_sub_epi32(a2, v25), _mm_shuffle_epi32(v25, 78));\n v27 = _mm_unpacklo_epi16(v24, _mm_cmpgt_epi16((__m128i)0LL, v24));\n a2 = _mm_sub_epi32(_mm_sub_epi32(v26, v27), _mm_shuffle_epi32(v27, 78));\n v20 = _mm_cvtsi128_si32(a2) + _mm_cvtsi128_si32(_mm_shuffle_epi32(a2, 229));\n v19 += v21 & 0xFFFFFFF8;\n if ( (v21 & 7) != 0 )\n {\nLABEL_16:\n if ( a1[v19] == 32 )\n ++v20;\n if ( v4 > v19 + 1 )\n {\n if ( a1[v19 + 1] == 32 )\n ++v20;\n if ( v19 + 2 < v4 )\n {\n if ( a1[v19 + 2] == 32 )\n ++v20;\n if ( v4 > v19 + 3 )\n {\n if ( a1[v19 + 3] == 32 )\n {\n v28 = v19 + 4;\n ++v20;\n if ( v4 <= v19 + 4 )\n goto LABEL_27;\n }\n else\n {\n v28 = v19 + 4;\n if ( v4 <= v19 + 4 )\n goto LABEL_27;\n }\n if ( a1[v28] == 32 )\n ++v20;\n if ( v4 > v19 + 5 )\n {\n if ( a1[v19 + 5] == 32 )\n ++v20;\n v29 = v19 + 6;\n if ( v4 > v29 && a1[v29] == 32 )\n ++v20;\n }\n }\n }\n }\n }\nLABEL_27:\n v30 = v4 + 2 * v20;\n v31 = \"\";\n if ( v30 <= 1000 )\n {\n v32 = v30 - 1;\n v39[v30] = 0;\n v33 = &a1[v5];\n v34 = (__int64)&a1[v4 - 2 - v5];\n while ( 1 )\n {\n v35 = *v33;\n if ( *v33 != 32 )\n break;\nLABEL_32:\n --v33;\n *(_WORD *)&v39[v32 - 2] = 12837;\n v39[v32] = 48;\n if ( v33 == (const char *)v34 )\n goto LABEL_35;\n v32 -= 3;\n }\n while ( 1 )\n {\n --v33;\n v39[v32] = v35;\n if ( v33 == (const char *)v34 )\n goto LABEL_35;\n v35 = *v33;\n --v32;\n if ( *v33 == 32 )\n goto LABEL_32;\n }\n }\n return (__int64)v31;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 3F8h\nmov rax, fs:28h\nmov [rsp+408h+var_20], rax\nxor eax, eax\ncall _strlen\nmov rsi, rax\ntest eax, eax\njle loc_1578\nlea edi, [rax-1]\ncmp edi, 0Eh\njbe loc_1620\nmov edx, esi\npxor xmm1, xmm1\npxor xmm5, xmm5\nmov rax, rbx\nshr edx, 4\nmovdqa xmm6, cs:xmmword_2170\npxor xmm4, xmm4\nshl rdx, 4\nadd rdx, rbx\nnop word ptr [rax+rax+00h]\nloc_1328:\nmovdqu xmm0, xmmword ptr [rax]\nmovdqa xmm3, xmm5\nadd rax, 10h\npcmpeqb xmm0, xmm6\npcmpgtb xmm3, xmm0\nmovdqa xmm2, xmm0\npunpcklbw xmm2, xmm3\npunpckhbw xmm0, xmm3\nmovdqa xmm3, xmm4\npcmpgtw xmm3, xmm2\nmovdqa xmm7, xmm2\npunpcklwd xmm7, xmm3\npunpckhwd xmm2, xmm3\nmovdqa xmm3, xmm0\npsubd xmm1, xmm7\npsubd xmm1, xmm2\nmovdqa xmm2, xmm4\npcmpgtw xmm2, xmm0\npunpcklwd xmm3, xmm2\npunpckhwd xmm0, xmm2\npsubd xmm1, xmm3\npsubd xmm1, xmm0\ncmp rax, rdx\njnz short loc_1328\nmovdqa xmm0, xmm1\nmov r8d, esi\npsrldq xmm0, 8\nand r8d, 0FFFFFFF0h\npaddd xmm0, xmm1\nmov edx, r8d\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\npaddd xmm0, xmm2\nmovd eax, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm1, 8\npaddd xmm0, xmm1\ntest sil, 0Fh\njz loc_14EB\nloc_13C4:\nmov ecx, esi\nsub ecx, r8d\nlea r9d, [rcx-1]\ncmp r9d, 6\njbe loc_1468\nmovq xmm2, qword ptr cs:xmmword_2170\nmovq xmm1, qword ptr [rbx+r8]\npcmpeqb xmm1, xmm2\npxor xmm2, xmm2\npcmpgtb xmm2, xmm1\nmovdqa xmm3, xmm1\npunpcklbw xmm3, xmm2\npunpcklbw xmm1, xmm2\npxor xmm2, xmm2\nmovdqa xmm4, xmm2\nmovdqa xmm5, xmm3\npshufd xmm1, xmm1, 4Eh ; 'N'\npcmpgtw xmm4, xmm3\npcmpgtw xmm2, xmm1\npunpcklwd xmm5, xmm4\npunpcklwd xmm3, xmm4\npsubd xmm0, xmm5\npshufd xmm3, xmm3, 4Eh ; 'N'\npsubd xmm0, xmm3\nmovdqa xmm3, xmm1\npunpcklwd xmm1, xmm2\npunpcklwd xmm3, xmm2\npshufd xmm1, xmm1, 4Eh ; 'N'\npsubd xmm0, xmm3\npsubd xmm0, xmm1\nmovd r8d, xmm0\npshufd xmm6, xmm0, 0E5h\nmovd eax, xmm6\nadd eax, r8d\nmov r8d, ecx\nand r8d, 0FFFFFFF8h\nadd edx, r8d\nand ecx, 7\njz loc_14EB\nloc_1468:\nmovsxd rcx, edx\ncmp byte ptr [rbx+rcx], 20h ; ' '\njz loc_15D0\nloc_1475:\nlea ecx, [rdx+1]\ncmp esi, ecx\njle short loc_14EB\nmovsxd rcx, ecx\ncmp byte ptr [rbx+rcx], 20h ; ' '\njz loc_15E0\nloc_1489:\nlea ecx, [rdx+2]\ncmp ecx, esi\njge short loc_14EB\nmovsxd rcx, ecx\ncmp byte ptr [rbx+rcx], 20h ; ' '\njz loc_15F0\nloc_149D:\nlea ecx, [rdx+3]\ncmp esi, ecx\njle short loc_14EB\nmovsxd rcx, ecx\ncmp byte ptr [rbx+rcx], 20h ; ' '\njz loc_1600\nlea ecx, [rdx+4]\ncmp esi, ecx\njle short loc_14EB\nloc_14B8:\nmovsxd rcx, ecx\ncmp byte ptr [rbx+rcx], 20h ; ' '\njnz short loc_14C4\nadd eax, 1\nloc_14C4:\nlea ecx, [rdx+5]\ncmp esi, ecx\njle short loc_14EB\nmovsxd rcx, ecx\ncmp byte ptr [rbx+rcx], 20h ; ' '\njnz short loc_14D7\nadd eax, 1\nloc_14D7:\nadd edx, 6\ncmp esi, edx\njle short loc_14EB\nmovsxd rdx, edx\ncmp byte ptr [rbx+rdx], 20h ; ' '\njz loc_1618\nloc_14EB:\nlea edx, [rsi+rax*2]\nlea rcx, aMyNameIsDawood+11h; \"\"\ncmp edx, 3E8h\njg loc_15A7\nmovsxd rax, edx\nmovsxd rsi, esi\nlea ecx, [rdx-1]\nmov rbp, rsp\nmov [rsp+rax+408h+var_408], 0\nlea r8, [rbx+rsi-2]\nmovsxd rax, edi\nmov edi, edi\nmovzx r9d, cs:word_2180\nadd rax, rbx\nsub r8, rdi\nloc_1529:\nmovzx esi, byte ptr [rax]\ncmp sil, 20h ; ' '\njz short loc_154E\nloc_1532:\nmovsxd rdi, ecx\nsub rax, 1\nmov [rsp+rdi+408h+var_408], sil\ncmp rax, r8\njz short loc_1588\nmovzx esi, byte ptr [rax]\nsub ecx, 1\ncmp sil, 20h ; ' '\njnz short loc_1532\nloc_154E:\nlea esi, [rcx-2]\nsub rax, 1\nmovsxd rsi, esi\nmov [rbp+rsi+0], r9w\nlea esi, [rcx-3]\nmovsxd rcx, ecx\nmov [rsp+rcx+408h+var_408], 30h ; '0'\ncmp rax, r8\njz short loc_1588\nmov ecx, esi\njmp short loc_1529\nloc_1578:\ncdqe\nmov edx, esi\nmov rbp, rsp\nmov [rsp+rax+408h+var_408], 0\nnop dword ptr [rax+rax+00h]\nloc_1588:\nlea ebx, [rdx+1]\nmovsxd rbx, ebx\nmov rdi, rbx; size\ncall _malloc\nmov rdx, rbx\nmov rsi, rbp\nmov rdi, rax\ncall ___strcpy_chk\nmov rcx, rax\nloc_15A7:\nmov rax, [rsp+408h+var_20]\nsub rax, fs:28h\njnz short loc_1630\nadd rsp, 3F8h\nmov rax, rcx\npop rbx\npop rbp\nretn\nloc_15D0:\nadd eax, 1\njmp loc_1475\nloc_15E0:\nadd eax, 1\njmp loc_1489\nloc_15F0:\nadd eax, 1\njmp loc_149D\nloc_1600:\nlea ecx, [rdx+4]\nadd eax, 1\ncmp esi, ecx\njg loc_14B8\njmp loc_14EB\nloc_1618:\nadd eax, 1\njmp loc_14EB\nloc_1620:\npxor xmm0, xmm0\nxor r8d, r8d\nxor eax, eax\nxor edx, edx\njmp loc_13C4\nloc_1630:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12C0(const char *a1, __m128i a2)\n{\n int v3; // eax\n int v4; // esi\n int v5; // edi\n __m128i v6; // xmm1\n const __m128i *v7; // rax\n __m128i si128; // xmm6\n __m128i v9; // xmm0\n __m128i v10; // xmm0\n __m128i v11; // xmm3\n __m128i v12; // xmm2\n __m128i v13; // xmm0\n __m128i v14; // xmm3\n __m128i v15; // xmm1\n __m128i v16; // xmm2\n __int64 v17; // r8\n __m128i v18; // xmm0\n signed int v19; // edx\n int v20; // eax\n int v21; // ecx\n __m128i v22; // xmm1\n __m128i v23; // xmm3\n __m128i v24; // xmm1\n __m128i v25; // xmm3\n __m128i v26; // xmm0\n __m128i v27; // xmm3\n int v28; // ecx\n int v29; // edx\n int v30; // edx\n char *v31; // rcx\n int v32; // ecx\n const char *v33; // rax\n __int64 v34; // r8\n char v35; // si\n size_t v36; // rbx\n void *v37; // rax\n _BYTE v39[1000]; // [rsp+0h] [rbp-408h] BYREF\n unsigned __int64 v40; // [rsp+3E8h] [rbp-20h]\n\n v40 = __readfsqword(0x28u);\n v3 = strlen(a1);\n v4 = v3;\n if ( v3 <= 0 )\n {\n v30 = v3;\n v39[v3] = 0;\nLABEL_35:\n v36 = v30 + 1;\n v37 = malloc(v36);\n return __strcpy_chk(v37, v39, v36, *(double *)a2.m128i_i64);\n }\n v5 = v3 - 1;\n if ( (unsigned int)(v3 - 1) <= 0xE )\n {\n a2 = 0LL;\n v17 = 0LL;\n v20 = 0;\n v19 = 0;\n }\n else\n {\n v6 = 0LL;\n v7 = (const __m128i *)a1;\n si128 = _mm_load_si128((const __m128i *)&xmmword_2170);\n do\n {\n v9 = _mm_loadu_si128(v7++);\n v10 = _mm_cmpeq_epi8(v9, si128);\n v11 = _mm_cmpgt_epi8((__m128i)0LL, v10);\n v12 = _mm_unpacklo_epi8(v10, v11);\n v13 = _mm_unpackhi_epi8(v10, v11);\n v14 = _mm_cmpgt_epi16((__m128i)0LL, v12);\n v15 = _mm_sub_epi32(_mm_sub_epi32(v6, _mm_unpacklo_epi16(v12, v14)), _mm_unpackhi_epi16(v12, v14));\n v16 = _mm_cmpgt_epi16((__m128i)0LL, v13);\n v6 = _mm_sub_epi32(_mm_sub_epi32(v15, _mm_unpacklo_epi16(v13, v16)), _mm_unpackhi_epi16(v13, v16));\n }\n while ( v7 != (const __m128i *)&a1[16 * ((unsigned int)v4 >> 4)] );\n v17 = v4 & 0xFFFFFFF0;\n v18 = _mm_add_epi32(_mm_srli_si128(v6, 8), v6);\n v19 = v4 & 0xFFFFFFF0;\n v20 = _mm_cvtsi128_si32(_mm_add_epi32(v18, _mm_srli_si128(v18, 4)));\n a2 = _mm_add_epi32(v6, _mm_srli_si128(v6, 8));\n if ( (v4 & 0xF) == 0 )\n goto LABEL_27;\n }\n v21 = v4 - v17;\n if ( (unsigned int)(v4 - v17 - 1) <= 6 )\n goto LABEL_16;\n v22 = _mm_cmpeq_epi8(_mm_loadl_epi64((const __m128i *)&a1[v17]), _mm_loadl_epi64((const __m128i *)&xmmword_2170));\n v23 = _mm_unpacklo_epi8(v22, _mm_cmpgt_epi8((__m128i)0LL, v22));\n v24 = _mm_shuffle_epi32(v23, 78);\n v25 = _mm_unpacklo_epi16(v23, _mm_cmpgt_epi16((__m128i)0LL, v23));\n v26 = _mm_sub_epi32(_mm_sub_epi32(a2, v25), _mm_shuffle_epi32(v25, 78));\n v27 = _mm_unpacklo_epi16(v24, _mm_cmpgt_epi16((__m128i)0LL, v24));\n a2 = _mm_sub_epi32(_mm_sub_epi32(v26, v27), _mm_shuffle_epi32(v27, 78));\n v20 = _mm_cvtsi128_si32(a2) + _mm_cvtsi128_si32(_mm_shuffle_epi32(a2, 229));\n v19 += v21 & 0xFFFFFFF8;\n if ( (v21 & 7) != 0 )\n {\nLABEL_16:\n if ( a1[v19] == 32 )\n ++v20;\n if ( v4 > v19 + 1 )\n {\n if ( a1[v19 + 1] == 32 )\n ++v20;\n if ( v19 + 2 < v4 )\n {\n if ( a1[v19 + 2] == 32 )\n ++v20;\n if ( v4 > v19 + 3 )\n {\n if ( a1[v19 + 3] == 32 )\n {\n v28 = v19 + 4;\n ++v20;\n if ( v4 <= v19 + 4 )\n goto LABEL_27;\n }\n else\n {\n v28 = v19 + 4;\n if ( v4 <= v19 + 4 )\n goto LABEL_27;\n }\n if ( a1[v28] == 32 )\n ++v20;\n if ( v4 > v19 + 5 )\n {\n if ( a1[v19 + 5] == 32 )\n ++v20;\n v29 = v19 + 6;\n if ( v4 > v29 && a1[v29] == 32 )\n ++v20;\n }\n }\n }\n }\n }\nLABEL_27:\n v30 = v4 + 2 * v20;\n v31 = \"\";\n if ( v30 <= 1000 )\n {\n v32 = v30 - 1;\n v39[v30] = 0;\n v33 = &a1[v5];\n v34 = (__int64)&a1[v4 - 2 - v5];\n while ( 1 )\n {\n v35 = *v33;\n if ( *v33 != 32 )\n break;\nLABEL_32:\n --v33;\n *(_WORD *)&v39[v32 - 2] = 12837;\n v39[v32] = 48;\n if ( v33 == (const char *)v34 )\n goto LABEL_35;\n v32 -= 3;\n }\n while ( 1 )\n {\n --v33;\n v39[v32] = v35;\n if ( v33 == (const char *)v34 )\n goto LABEL_35;\n v35 = *v33;\n --v32;\n if ( *v33 == 32 )\n goto LABEL_32;\n }\n }\n return (__int64)v31;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12C0(const char *a1, __m128i a2) {\n int v3;\n int v4;\n int v5;\n __m128i v6;\n const __m128i *v7;\n __m128i si128;\n __m128i v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n __m128i v15;\n __m128i v16;\n long long v17;\n __m128i v18;\n signed int v19;\n int v20;\n int v21;\n __m128i v22;\n __m128i v23;\n __m128i v24;\n __m128i v25;\n __m128i v26;\n __m128i v27;\n int v28;\n int v29;\n int v30;\n char *v31;\n int v32;\n const char *v33;\n long long v34;\n char v35;\n unsigned int v36;\n void *v37;\n uint8_t v39[1000];\n unsigned long long v40;\n v40 = __readfsqword(40u);\n v3 = strlen(a1);\n v4 = v3;\n if (v3 <= 0) {\n v30 = v3;\n v39[v3] = 0;\n LABEL_35:\n v36 = v30 + 1;\n v37 = malloc(v36);\n return __strcpy_chk(v37, v39, v36, *(double *)a2.m128i_i64);\n }\n v5 = v3 - 1;\n if ((unsigned int)(v3 - 1) <= 14) {\n a2 = 0LL;\n v17 = 0LL;\n v20 = 0;\n v19 = 0;\n } else {\n v6 = 0LL;\n v7 = (const __m128i *)a1;\n si128 = _mm_load_si128((const __m128i *)&xmmword_2170);\n do {\n v9 = _mm_loadu_si128(v7++);\n v10 = _mm_cmpeq_epi8(v9, si128);\n v11 = _mm_cmpgt_epi8((__m128i)0LL, v10);\n v12 = _mm_unpacklo_epi8(v10, v11);\n v13 = _mm_unpackhi_epi8(v10, v11);\n v14 = _mm_cmpgt_epi16((__m128i)0LL, v12);\n v15 = _mm_sub_epi32(_mm_sub_epi32(v6, _mm_unpacklo_epi16(v12, v14)),\n _mm_unpackhi_epi16(v12, v14));\n v16 = _mm_cmpgt_epi16((__m128i)0LL, v13);\n v6 = _mm_sub_epi32(_mm_sub_epi32(v15, _mm_unpacklo_epi16(v13, v16)),\n _mm_unpackhi_epi16(v13, v16));\n } while (v7 != (const __m128i *)&a1[16 * ((unsigned int)v4 >> 4)]);\n v17 = v4 & 4294967280;\n v18 = _mm_add_epi32(_mm_srli_si128(v6, 8), v6);\n v19 = v4 & 4294967280;\n v20 = _mm_cvtsi128_si32(_mm_add_epi32(v18, _mm_srli_si128(v18, 4)));\n a2 = _mm_add_epi32(v6, _mm_srli_si128(v6, 8));\n if ((v4 & 15) == 0) goto LABEL_27;\n }\n v21 = v4 - v17;\n if ((unsigned int)(v4 - v17 - 1) <= 6) goto LABEL_16;\n v22 = _mm_cmpeq_epi8(_mm_loadl_epi64((const __m128i *)&a1[v17]),\n _mm_loadl_epi64((const __m128i *)&xmmword_2170));\n v23 = _mm_unpacklo_epi8(v22, _mm_cmpgt_epi8((__m128i)0LL, v22));\n v24 = _mm_shuffle_epi32(v23, 78);\n v25 = _mm_unpacklo_epi16(v23, _mm_cmpgt_epi16((__m128i)0LL, v23));\n v26 = _mm_sub_epi32(_mm_sub_epi32(a2, v25), _mm_shuffle_epi32(v25, 78));\n v27 = _mm_unpacklo_epi16(v24, _mm_cmpgt_epi16((__m128i)0LL, v24));\n a2 = _mm_sub_epi32(_mm_sub_epi32(v26, v27), _mm_shuffle_epi32(v27, 78));\n v20 = _mm_cvtsi128_si32(a2) + _mm_cvtsi128_si32(_mm_shuffle_epi32(a2, 229));\n v19 += v21 & 4294967288;\n if ((v21 & 7) != 0) {\n LABEL_16:\n if (a1[v19] == 32) ++v20;\n if (v4 > v19 + 1) {\n if (a1[v19 + 1] == 32) ++v20;\n if (v19 + 2 < v4) {\n if (a1[v19 + 2] == 32) ++v20;\n if (v4 > v19 + 3) {\n if (a1[v19 + 3] == 32) {\n v28 = v19 + 4;\n ++v20;\n if (v4 <= v19 + 4) goto LABEL_27;\n } else {\n v28 = v19 + 4;\n if (v4 <= v19 + 4) goto LABEL_27;\n }\n if (a1[v28] == 32) ++v20;\n if (v4 > v19 + 5) {\n if (a1[v19 + 5] == 32) ++v20;\n v29 = v19 + 6;\n if (v4 > v29 && a1[v29] == 32) ++v20;\n }\n }\n }\n }\n }\nLABEL_27:\n v30 = v4 + 2 * v20;\n v31 = \"\";\n if (v30 <= 1000) {\n v32 = v30 - 1;\n v39[v30] = 0;\n v33 = &a1[v5];\n v34 = (long long)&a1[v4 - 2 - v5];\n while (1) {\n v35 = *v33;\n if (*v33 != 32) break;\n LABEL_32:\n --v33;\n *(unsigned short *)&v39[v32 - 2] = 12837;\n v39[v32] = 48;\n if (v33 == (const char *)v34) goto LABEL_35;\n v32 -= 3;\n }\n while (1) {\n --v33;\n v39[v32] = v35;\n if (v33 == (const char *)v34) goto LABEL_35;\n v35 = *v33;\n --v32;\n if (*v33 == 32) goto LABEL_32;\n }\n }\n return (long long)v31;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, __m128i a2) {\n int v3;\n int v4;\n int v5;\n __m128i v6;\n const __m128i *v7;\n __m128i si128;\n __m128i v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n __m128i v15;\n __m128i v16;\n long long v17;\n __m128i v18;\n signed int v19;\n int v20;\n int v21;\n __m128i v22;\n __m128i v23;\n __m128i v24;\n __m128i v25;\n __m128i v26;\n __m128i v27;\n int v28;\n int v29;\n int v30;\n char *v31;\n int v32;\n const char *v33;\n long long v34;\n char v35;\n unsigned int v36;\n void *v37;\n uint8_t v39[1000];\n unsigned long long v40;\n v40 = __readfsqword(40u);\n v3 = strlen(a1);\n v4 = v3;\n if (v3 <= 0) {\n v30 = v3;\n v39[v3] = 0;\n LABEL_35:\n v36 = v30 + 1;\n v37 = malloc(v36);\n return __strcpy_chk(v37, v39, v36, *(double *)a2.m128i_i64);\n }\n v5 = v3 - 1;\n if ((unsigned int)(v3 - 1) <= 14) {\n a2 = 0LL;\n v17 = 0LL;\n v20 = 0;\n v19 = 0;\n } else {\n v6 = 0LL;\n v7 = (const __m128i *)a1;\n si128 = _mm_load_si128((const __m128i *)&xmmword_2170);\n do {\n v9 = _mm_loadu_si128(v7++);\n v10 = _mm_cmpeq_epi8(v9, si128);\n v11 = _mm_cmpgt_epi8((__m128i)0LL, v10);\n v12 = _mm_unpacklo_epi8(v10, v11);\n v13 = _mm_unpackhi_epi8(v10, v11);\n v14 = _mm_cmpgt_epi16((__m128i)0LL, v12);\n v15 = _mm_sub_epi32(_mm_sub_epi32(v6, _mm_unpacklo_epi16(v12, v14)),\n _mm_unpackhi_epi16(v12, v14));\n v16 = _mm_cmpgt_epi16((__m128i)0LL, v13);\n v6 = _mm_sub_epi32(_mm_sub_epi32(v15, _mm_unpacklo_epi16(v13, v16)),\n _mm_unpackhi_epi16(v13, v16));\n } while (v7 != (const __m128i *)&a1[16 * ((unsigned int)v4 >> 4)]);\n v17 = v4 & 4294967280;\n v18 = _mm_add_epi32(_mm_srli_si128(v6, 8), v6);\n v19 = v4 & 4294967280;\n v20 = _mm_cvtsi128_si32(_mm_add_epi32(v18, _mm_srli_si128(v18, 4)));\n a2 = _mm_add_epi32(v6, _mm_srli_si128(v6, 8));\n if ((v4 & 15) == 0) goto LABEL_27;\n }\n v21 = v4 - v17;\n if ((unsigned int)(v4 - v17 - 1) <= 6) goto LABEL_16;\n v22 = _mm_cmpeq_epi8(_mm_loadl_epi64((const __m128i *)&a1[v17]),\n _mm_loadl_epi64((const __m128i *)&xmmword_2170));\n v23 = _mm_unpacklo_epi8(v22, _mm_cmpgt_epi8((__m128i)0LL, v22));\n v24 = _mm_shuffle_epi32(v23, 78);\n v25 = _mm_unpacklo_epi16(v23, _mm_cmpgt_epi16((__m128i)0LL, v23));\n v26 = _mm_sub_epi32(_mm_sub_epi32(a2, v25), _mm_shuffle_epi32(v25, 78));\n v27 = _mm_unpacklo_epi16(v24, _mm_cmpgt_epi16((__m128i)0LL, v24));\n a2 = _mm_sub_epi32(_mm_sub_epi32(v26, v27), _mm_shuffle_epi32(v27, 78));\n v20 = _mm_cvtsi128_si32(a2) + _mm_cvtsi128_si32(_mm_shuffle_epi32(a2, 229));\n v19 += v21 & 4294967288;\n if ((v21 & 7) != 0) {\n LABEL_16:\n if (a1[v19] == 32) ++v20;\n if (v4 > v19 + 1) {\n if (a1[v19 + 1] == 32) ++v20;\n if (v19 + 2 < v4) {\n if (a1[v19 + 2] == 32) ++v20;\n if (v4 > v19 + 3) {\n if (a1[v19 + 3] == 32) {\n v28 = v19 + 4;\n ++v20;\n if (v4 <= v19 + 4) goto LABEL_27;\n } else {\n v28 = v19 + 4;\n if (v4 <= v19 + 4) goto LABEL_27;\n }\n if (a1[v28] == 32) ++v20;\n if (v4 > v19 + 5) {\n if (a1[v19 + 5] == 32) ++v20;\n v29 = v19 + 6;\n if (v4 > v29 && a1[v29] == 32) ++v20;\n }\n }\n }\n }\n }\nLABEL_27:\n v30 = v4 + 2 * v20;\n v31 = \"\";\n if (v30 <= 1000) {\n v32 = v30 - 1;\n v39[v30] = 0;\n v33 = &a1[v5];\n v34 = (long long)&a1[v4 - 2 - v5];\n while (1) {\n v35 = *v33;\n if (*v33 != 32) break;\n LABEL_32:\n --v33;\n *(unsigned short *)&v39[v32 - 2] = 12837;\n v39[v32] = 48;\n if (v33 == (const char *)v34) goto LABEL_35;\n v32 -= 3;\n }\n while (1) {\n --v33;\n v39[v32] = v35;\n if (v33 == (const char *)v34) goto LABEL_35;\n v35 = *v33;\n --v32;\n if (*v33 == 32) goto LABEL_32;\n }\n }\n return (long long)v31;\n}" + }, + { + "index": 629, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int* func0(int* list, int size, int* result_size) {\n static int ev_li[100];\n int j = 0;\n for (int i = 0; i < size; i++) {\n if (list[i] % 2 == 0) {\n ev_li[j++] = list[i];\n }\n }\n *result_size = j;\n return ev_li;\n}", + "test": "int main() {\n\n int size;\n\n \n\n int test1[] = {1,2,3,4,5};\n\n int expected1[] = {2,4};\n\n int* result1 = func0(test1, 5, &size);\n\n assert(size == 2);\n\n for (int i = 0; i < size; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n\n\n int test2[] = {4,5,6,7,8,0,1};\n\n int expected2[] = {4,6,8,0};\n\n int* result2 = func0(test2, 7, &size);\n\n assert(size == 4);\n\n for (int i = 0; i < size; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n \n\n int test3[] = {8,12,15,19};\n\n int expected3[] = {8,12};\n\n int* result3 = func0(test3, 4, &size);\n\n assert(size == 2);\n\n for (int i = 0; i < size; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n\n\n printf(\"All test cases passed.\\n\");\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 1201 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nand $0x1,%eax\ntest %eax,%eax\njne 11fd \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x8(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x8(%rbp)\nmov (%rcx),%edx\ncltq\nlea 0x0(,%rax,4),%rcx\nlea 0x2e46(%rip),%rax\nmov %edx,(%rcx,%rax,1)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11ac \nmov -0x28(%rbp),%rax\nmov -0x8(%rbp),%edx\nmov %edx,(%rax)\nlea 0x2e27(%rip),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_1201\nloc_11AC:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njnz short loc_11FD\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_8]\nlea edx, [rax+1]\nmov [rbp+var_8], edx\nmov edx, [rcx]\ncdqe\nlea rcx, ds:0[rax*4]\nlea rax, ev_li_1\nmov [rcx+rax], edx\nloc_11FD:\nadd [rbp+var_4], 1\nloc_1201:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11AC\nmov rax, [rbp+var_28]\nmov edx, [rbp+var_8]\nmov [rax], edx\nlea rax, ev_li_1\npop rbp\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, _DWORD *a3)\n{\n int v3; // eax\n int v5; // [rsp+20h] [rbp-8h]\n int i; // [rsp+24h] [rbp-4h]\n\n v5 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( (*(_DWORD *)(4LL * i + a1) & 1) == 0 )\n {\n v3 = v5++;\n ev_li_1[v3] = *(_DWORD *)(4LL * i + a1);\n }\n }\n *a3 = v5;\n return ev_li_1;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_1201\nloc_11AC:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njnz short loc_11FD\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_8]\nlea edx, [rax+1]\nmov [rbp+var_8], edx\nmov edx, [rcx]\ncdqe\nlea rcx, ds:0[rax*4]\nlea rax, unk_4040\nmov [rcx+rax], edx\nloc_11FD:\nadd [rbp+var_4], 1\nloc_1201:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11AC\nmov rax, [rbp+var_28]\nmov edx, [rbp+var_8]\nmov [rax], edx\nlea rax, unk_4040\npop rbp\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1189(__int64 a1, int a2, _DWORD *a3)\n{\n int v3; // eax\n int v5; // [rsp+20h] [rbp-8h]\n int i; // [rsp+24h] [rbp-4h]\n\n v5 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( (*(_DWORD *)(4LL * i + a1) & 1) == 0 )\n {\n v3 = v5++;\n dword_4040[v3] = *(_DWORD *)(4LL * i + a1);\n }\n }\n *a3 = v5;\n return dword_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1189(long long a1, int a2, uint32_t *a3) {\n int v3;\n int v5;\n int i;\n v5 = 0;\n for (i = 0; i < a2; ++i) {\n if ((*(uint32_t *)(4LL * i + a1) & 1) == 0) {\n v3 = v5++;\n dword_4040[v3] = *(uint32_t *)(4LL * i + a1);\n }\n }\n *a3 = v5;\n return dword_4040;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, uint32_t *a3) {\n int v3;\n int v5;\n int i;\n v5 = 0;\n for (i = 0; i < a2; ++i) {\n if ((*(uint32_t *)(4LL * i + a1) & 1) == 0) {\n v3 = v5++;\n ev_li_1[v3] = *(uint32_t *)(4LL * i + a1);\n }\n }\n *a3 = v5;\n return ev_li_1;\n}" + }, + { + "index": 629, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int* func0(int* list, int size, int* result_size) {\n static int ev_li[100];\n int j = 0;\n for (int i = 0; i < size; i++) {\n if (list[i] % 2 == 0) {\n ev_li[j++] = list[i];\n }\n }\n *result_size = j;\n return ev_li;\n}", + "test": "int main() {\n\n int size;\n\n \n\n int test1[] = {1,2,3,4,5};\n\n int expected1[] = {2,4};\n\n int* result1 = func0(test1, 5, &size);\n\n assert(size == 2);\n\n for (int i = 0; i < size; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n\n\n int test2[] = {4,5,6,7,8,0,1};\n\n int expected2[] = {4,6,8,0};\n\n int* result2 = func0(test2, 7, &size);\n\n assert(size == 4);\n\n for (int i = 0; i < size; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n \n\n int test3[] = {8,12,15,19};\n\n int expected3[] = {8,12};\n\n int* result3 = func0(test3, 4, &size);\n\n assert(size == 2);\n\n for (int i = 0; i < size; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n\n\n printf(\"All test cases passed.\\n\");\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11c6 \nmov %rdi,%rax\nlea -0x1(%rsi),%ecx\nlea 0x4(%rdi,%rcx,4),%rdi\nmov $0x0,%esi\nlea 0x2e98(%rip),%r9\njmp 11b3 \nadd $0x4,%rax\ncmp %rdi,%rax\nje 11cb \nmov (%rax),%ecx\ntest $0x1,%cl\njne 11aa \nmovslq %esi,%r8\nmov %ecx,(%r9,%r8,4)\nlea 0x1(%rsi),%esi\njmp 11aa \nmov $0x0,%esi\nmov %esi,(%rdx)\nlea 0x2e6c(%rip),%rax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11C5\nmov rax, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*4]\nmov esi, 0\nlea r9, ev_li_1\njmp short loc_11B2\nloc_11A9:\nadd rax, 4\ncmp rax, rdi\njz short loc_11CA\nloc_11B2:\nmov ecx, [rax]\ntest cl, 1\njnz short loc_11A9\nmovsxd r8, esi\nmov [r9+r8*4], ecx\nlea esi, [rsi+1]\njmp short loc_11A9\nloc_11C5:\nmov esi, 0\nloc_11CA:\nmov [rdx], esi\nlea rax, ev_li_1\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(_DWORD *a1, int a2, _DWORD *a3)\n{\n _DWORD *v3; // rax\n _DWORD *v4; // rdi\n int v5; // esi\n\n if ( a2 <= 0 )\n {\n v5 = 0;\n }\n else\n {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n do\n {\n if ( (*v3 & 1) == 0 )\n ev_li_1[v5++] = *v3;\n ++v3;\n }\n while ( v3 != v4 );\n }\n *a3 = v5;\n return ev_li_1;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\ntest esi, esi\njle short loc_11C5\nmov rax, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*4]\nmov esi, 0\nlea r9, unk_4040\njmp short loc_11B2\nloc_11A9:\nadd rax, 4\ncmp rax, rdi\njz short loc_11CA\nloc_11B2:\nmov ecx, [rax]\ntest cl, 1\njnz short loc_11A9\nmovsxd r8, esi\nmov [r9+r8*4], ecx\nlea esi, [rsi+1]\njmp short loc_11A9\nloc_11C5:\nmov esi, 0\nloc_11CA:\nmov [rdx], esi\nlea rax, unk_4040\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1189(_DWORD *a1, int a2, _DWORD *a3)\n{\n _DWORD *v3; // rax\n _DWORD *v4; // rdi\n int v5; // esi\n\n if ( a2 <= 0 )\n {\n v5 = 0;\n }\n else\n {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n do\n {\n if ( (*v3 & 1) == 0 )\n dword_4040[v5++] = *v3;\n ++v3;\n }\n while ( v3 != v4 );\n }\n *a3 = v5;\n return dword_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1189(uint32_t *a1, int a2, uint32_t *a3) {\n uint32_t *v3;\n uint32_t *v4;\n int v5;\n if (a2 <= 0) {\n v5 = 0;\n } else {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n do {\n if ((*v3 & 1) == 0) dword_4040[v5++] = *v3;\n ++v3;\n } while (v3 != v4);\n }\n *a3 = v5;\n return dword_4040;\n}", + "ida_pseudo_norm": "uint32_t *func0(uint32_t *a1, int a2, uint32_t *a3) {\n uint32_t *v3;\n uint32_t *v4;\n int v5;\n if (a2 <= 0) {\n v5 = 0;\n } else {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n do {\n if ((*v3 & 1) == 0) ev_li_1[v5++] = *v3;\n ++v3;\n } while (v3 != v4);\n }\n *a3 = v5;\n return ev_li_1;\n}" + }, + { + "index": 629, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int* func0(int* list, int size, int* result_size) {\n static int ev_li[100];\n int j = 0;\n for (int i = 0; i < size; i++) {\n if (list[i] % 2 == 0) {\n ev_li[j++] = list[i];\n }\n }\n *result_size = j;\n return ev_li;\n}", + "test": "int main() {\n\n int size;\n\n \n\n int test1[] = {1,2,3,4,5};\n\n int expected1[] = {2,4};\n\n int* result1 = func0(test1, 5, &size);\n\n assert(size == 2);\n\n for (int i = 0; i < size; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n\n\n int test2[] = {4,5,6,7,8,0,1};\n\n int expected2[] = {4,6,8,0};\n\n int* result2 = func0(test2, 7, &size);\n\n assert(size == 4);\n\n for (int i = 0; i < size; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n \n\n int test3[] = {8,12,15,19};\n\n int expected3[] = {8,12};\n\n int* result3 = func0(test3, 4, &size);\n\n assert(size == 2);\n\n for (int i = 0; i < size; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n\n\n printf(\"All test cases passed.\\n\");\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1468 \nlea -0x1(%rsi),%eax\nxor %ecx,%ecx\nlea 0x2c0c(%rip),%r9\nlea 0x4(%rdi,%rax,4),%rsi\nnopl 0x0(%rax)\nmov (%rdi),%eax\ntest $0x1,%al\njne 1450 \nmovslq %ecx,%r8\nadd $0x1,%ecx\nmov %eax,(%r9,%r8,4)\nadd $0x4,%rdi\ncmp %rsi,%rdi\njne 1440 \nmov %ecx,(%rdx)\nlea 0x2bde(%rip),%rax\nretq\nnopl 0x0(%rax,%rax,1)\nxor %ecx,%ecx\nlea 0x2bcf(%rip),%rax\nmov %ecx,(%rdx)\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_13C0\nmovsxd rsi, esi\nxor ecx, ecx\nlea r9, ev_li_1\nlea rsi, [rdi+rsi*4]\nnop dword ptr [rax+rax+00000000h]\nloc_13A0:\nmov eax, [rdi]\ntest al, 1\njnz short loc_13B0\nmovsxd r8, ecx\nadd ecx, 1\nmov [r9+r8*4], eax\nloc_13B0:\nadd rdi, 4\ncmp rdi, rsi\njnz short loc_13A0\nmov [rdx], ecx\nmov rax, r9\nretn\nloc_13C0:\nxor ecx, ecx\nlea r9, ev_li_1\nmov [rdx], ecx\nmov rax, r9\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(_DWORD *a1, int a2, _DWORD *a3)\n{\n int v3; // ecx\n _DWORD *v4; // rsi\n __int64 v5; // r8\n\n if ( a2 <= 0 )\n {\n *a3 = 0;\n return ev_li_1;\n }\n else\n {\n v3 = 0;\n v4 = &a1[a2];\n do\n {\n if ( (*a1 & 1) == 0 )\n {\n v5 = v3++;\n ev_li_1[v5] = *a1;\n }\n ++a1;\n }\n while ( a1 != v4 );\n *a3 = v3;\n return ev_li_1;\n }\n}", + "ida_strip_asm": "sub_1380:\nendbr64\ntest esi, esi\njle short loc_13C0\nmovsxd rsi, esi\nxor ecx, ecx\nlea r9, unk_4040\nlea rsi, [rdi+rsi*4]\nnop dword ptr [rax+rax+00000000h]\nloc_13A0:\nmov eax, [rdi]\ntest al, 1\njnz short loc_13B0\nmovsxd r8, ecx\nadd ecx, 1\nmov [r9+r8*4], eax\nloc_13B0:\nadd rdi, 4\ncmp rdi, rsi\njnz short loc_13A0\nmov [rdx], ecx\nmov rax, r9\nretn\nloc_13C0:\nxor ecx, ecx\nlea r9, unk_4040\nmov [rdx], ecx\nmov rax, r9\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1380(_DWORD *a1, int a2, _DWORD *a3)\n{\n int v3; // ecx\n _DWORD *v4; // rsi\n __int64 v5; // r8\n\n if ( a2 <= 0 )\n {\n *a3 = 0;\n return dword_4040;\n }\n else\n {\n v3 = 0;\n v4 = &a1[a2];\n do\n {\n if ( (*a1 & 1) == 0 )\n {\n v5 = v3++;\n dword_4040[v5] = *a1;\n }\n ++a1;\n }\n while ( a1 != v4 );\n *a3 = v3;\n return dword_4040;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1380(uint32_t *a1, int a2, uint32_t *a3) {\n int v3;\n uint32_t *v4;\n long long v5;\n if (a2 <= 0) {\n *a3 = 0;\n return dword_4040;\n } else {\n v3 = 0;\n v4 = &a1[a2];\n do {\n if ((*a1 & 1) == 0) {\n v5 = v3++;\n dword_4040[v5] = *a1;\n }\n ++a1;\n } while (a1 != v4);\n *a3 = v3;\n return dword_4040;\n }\n}", + "ida_pseudo_norm": "uint32_t *func0(uint32_t *a1, int a2, uint32_t *a3) {\n int v3;\n uint32_t *v4;\n long long v5;\n if (a2 <= 0) {\n *a3 = 0;\n return ev_li_1;\n } else {\n v3 = 0;\n v4 = &a1[a2];\n do {\n if ((*a1 & 1) == 0) {\n v5 = v3++;\n ev_li_1[v5] = *a1;\n }\n ++a1;\n } while (a1 != v4);\n *a3 = v3;\n return ev_li_1;\n }\n}" + }, + { + "index": 630, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\nvoid adjac(int *ele, int ele_size, int *sub, int sub_size, int ***results, int *results_size, int *cap) {\n\n if (ele_size == 0) {\n\n if (*results_size == *cap) {\n\n *cap *= 2;\n\n *results = realloc(*results, *cap * sizeof(int *));\n\n }\n\n (*results)[*results_size] = malloc(sub_size * sizeof(int));\n\n for (int i = 0; i < sub_size; i++) {\n\n (*results)[*results_size][i] = sub[i];\n\n }\n\n (*results_size)++;\n\n } else {\n\n int *new_sub = (int*)malloc((sub_size + 1) * sizeof(int));\n\n if (sub_size > 0) {\n\n memcpy(new_sub, sub, sub_size * sizeof(int));\n\n }\n\n for (int j = ele[0] - 1; j <= ele[0] + 1; j++) {\n\n new_sub[sub_size] = j;\n\n adjac(ele + 1, ele_size - 1, new_sub, sub_size + 1, results, results_size, cap);\n\n }\n\n free(new_sub);\n\n }\n\n}\n\n\n\n", + "func": "int **func0(int *test_tup, int size, int *result_size) {\n int **results = malloc(10 * sizeof(int *));\n int cap = 10;\n *result_size = 0;\n adjac(test_tup, size, NULL, 0, &results, result_size, &cap);\n return results;\n}", + "test": "int main() {\n\n int size;\n\n int test_tup1[] = {3, 4};\n\n int **res1 = func0(test_tup1, 2, &size);\n\n assert(size == 9);\n\n\n\n int test_tup2[] = {4, 5};\n\n int **res2 = func0(test_tup2, 2, &size);\n\n assert(size == 9);\n\n\n\n int test_tup3[] = {5, 6};\n\n int **res3 = func0(test_tup3, 2, &size);\n\n assert(size == 9);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x40,%rsp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmov %rdx,-0x38(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmov $0x50,%edi\ncallq 10e0 \nmov %rax,-0x10(%rbp)\nmovl $0xa,-0x14(%rbp)\nmov -0x38(%rbp),%rax\nmovl $0x0,(%rax)\nmov -0x38(%rbp),%rdi\nlea -0x10(%rbp),%rcx\nmov -0x2c(%rbp),%esi\nmov -0x28(%rbp),%rax\nsub $0x8,%rsp\nlea -0x14(%rbp),%rdx\npush %rdx\nmov %rdi,%r9\nmov %rcx,%r8\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rax,%rdi\ncallq 11e9 \nadd $0x10,%rsp\nmov -0x10(%rbp),%rax\nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 1448 \ncallq 10b0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov edi, 50h ; 'P'; size\ncall _malloc\nmov [rbp+var_10], rax\nmov [rbp+var_14], 0Ah\nmov rax, [rbp+var_38]\nmov dword ptr [rax], 0\nmov rdi, [rbp+var_38]\nlea rcx, [rbp+var_10]\nmov esi, [rbp+var_2C]\nmov rax, [rbp+var_28]\nsub rsp, 8\nlea rdx, [rbp+var_14]\npush rdx\nmov r9, rdi\nmov r8, rcx\nmov ecx, 0\nmov edx, 0\nmov rdi, rax\ncall adjac\nadd rsp, 10h\nmov rax, [rbp+var_10]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1448\ncall ___stack_chk_fail\nlocret_1448:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, _DWORD *a3)\n{\n int v5; // [rsp+2Ch] [rbp-14h] BYREF\n _QWORD v6[2]; // [rsp+30h] [rbp-10h] BYREF\n\n v6[1] = __readfsqword(0x28u);\n v6[0] = malloc(0x50uLL);\n v5 = 10;\n *a3 = 0;\n adjac(a1, a2, 0, 0, (unsigned int)v6, (_DWORD)a3, (__int64)&v5);\n return v6[0];\n}", + "ida_strip_asm": "sub_13B7:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov edi, 50h ; 'P'; size\ncall _malloc\nmov [rbp+var_10], rax\nmov [rbp+var_14], 0Ah\nmov rax, [rbp+var_38]\nmov dword ptr [rax], 0\nmov rdi, [rbp+var_38]\nlea rcx, [rbp+var_10]\nmov esi, [rbp+var_2C]\nmov rax, [rbp+var_28]\nsub rsp, 8\nlea rdx, [rbp+var_14]\npush rdx\nmov r9, rdi\nmov r8, rcx\nmov ecx, 0\nmov edx, 0\nmov rdi, rax\ncall sub_11E9\nadd rsp, 10h\nmov rax, [rbp+var_10]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1448\ncall ___stack_chk_fail\nlocret_1448:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_13B7(int a1, int a2, _DWORD *a3)\n{\n int v5; // [rsp+2Ch] [rbp-14h] BYREF\n _QWORD v6[2]; // [rsp+30h] [rbp-10h] BYREF\n\n v6[1] = __readfsqword(0x28u);\n v6[0] = malloc(0x50uLL);\n v5 = 10;\n *a3 = 0;\n sub_11E9(a1, a2, 0, 0, (unsigned int)v6, (_DWORD)a3, (__int64)&v5);\n return v6[0];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_13B7(int a1, int a2, uint32_t *a3) {\n int v5;\n uint64_t v6[2];\n v6[1] = __readfsqword(40u);\n v6[0] = malloc(80uLL);\n v5 = 10;\n *a3 = 0;\n sub_11E9(a1, a2, 0, 0, (unsigned int)v6, (uint32_t)a3, (long long)&v5);\n return v6[0];\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, uint32_t *a3) {\n int v5;\n uint64_t v6[2];\n v6[1] = __readfsqword(40u);\n v6[0] = malloc(80uLL);\n v5 = 10;\n *a3 = 0;\n adjac(a1, a2, 0, 0, (unsigned int)v6, (uint32_t)a3, (long long)&v5);\n return v6[0];\n}" + }, + { + "index": 630, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\nvoid adjac(int *ele, int ele_size, int *sub, int sub_size, int ***results, int *results_size, int *cap) {\n\n if (ele_size == 0) {\n\n if (*results_size == *cap) {\n\n *cap *= 2;\n\n *results = realloc(*results, *cap * sizeof(int *));\n\n }\n\n (*results)[*results_size] = malloc(sub_size * sizeof(int));\n\n for (int i = 0; i < sub_size; i++) {\n\n (*results)[*results_size][i] = sub[i];\n\n }\n\n (*results_size)++;\n\n } else {\n\n int *new_sub = (int*)malloc((sub_size + 1) * sizeof(int));\n\n if (sub_size > 0) {\n\n memcpy(new_sub, sub, sub_size * sizeof(int));\n\n }\n\n for (int j = ele[0] - 1; j <= ele[0] + 1; j++) {\n\n new_sub[sub_size] = j;\n\n adjac(ele + 1, ele_size - 1, new_sub, sub_size + 1, results, results_size, cap);\n\n }\n\n free(new_sub);\n\n }\n\n}\n\n\n\n", + "func": "int **func0(int *test_tup, int size, int *result_size) {\n int **results = malloc(10 * sizeof(int *));\n int cap = 10;\n *result_size = 0;\n adjac(test_tup, size, NULL, 0, &results, result_size, &cap);\n return results;\n}", + "test": "int main() {\n\n int size;\n\n int test_tup1[] = {3, 4};\n\n int **res1 = func0(test_tup1, 2, &size);\n\n assert(size == 9);\n\n\n\n int test_tup2[] = {4, 5};\n\n int **res2 = func0(test_tup2, 2, &size);\n\n assert(size == 9);\n\n\n\n int test_tup3[] = {5, 6};\n\n int **res3 = func0(test_tup3, 2, &size);\n\n assert(size == 9);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x28,%rsp\nmov %rdi,%rbp\nmov %esi,%r12d\nmov %rdx,%rbx\nmov $0x28,%r13d\nmov %fs:0x0(%r13),%rax\nmov %rax,0x18(%rsp)\nxor %eax,%eax\nmov $0x50,%edi\ncallq 10e0 \nmov %rax,0x10(%rsp)\nmovl $0xa,0xc(%rsp)\nmovl $0x0,(%rbx)\nsub $0x8,%rsp\nlea 0x14(%rsp),%rax\npush %rax\nmov %rbx,%r9\nlea 0x20(%rsp),%r8\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %r12d,%esi\nmov %rbp,%rdi\ncallq 11e9 \nmov 0x20(%rsp),%rax\nadd $0x10,%rsp\nmov 0x18(%rsp),%rcx\nxor %fs:0x0(%r13),%rcx\njne 13c5 \nadd $0x28,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\ncallq 10b0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 20h\nmov rbp, rdi\nmov r12d, esi\nmov rbx, rdx\nmov rax, fs:28h\nmov [rsp+38h+var_20], rax\nxor eax, eax\nmov edi, 50h ; 'P'; size\ncall _malloc\nmov [rsp+38h+var_28], rax\nmov [rsp+38h+var_2C], 0Ah\nmov dword ptr [rbx], 0\nsub rsp, 8\nlea rax, [rsp+40h+var_2C]\npush rax\nmov r9, rbx\nlea r8, [rsp+48h+var_28]\nmov ecx, 0\nmov edx, 0\nmov esi, r12d\nmov rdi, rbp\ncall adjac\nmov rax, [rsp+48h+var_28]\nadd rsp, 10h\nmov rdx, [rsp+38h+var_20]\nsub rdx, fs:28h\njnz short loc_13BD\nadd rsp, 20h\npop rbx\npop rbp\npop r12\nretn\nloc_13BD:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, _DWORD *a3)\n{\n int v5; // [rsp+Ch] [rbp-2Ch] BYREF\n _QWORD v6[5]; // [rsp+10h] [rbp-28h] BYREF\n\n v6[1] = __readfsqword(0x28u);\n v6[0] = malloc(0x50uLL);\n v5 = 10;\n *a3 = 0;\n adjac(a1, a2, 0, 0, (unsigned int)v6, (_DWORD)a3, (__int64)&v5);\n return v6[0];\n}", + "ida_strip_asm": "sub_1332:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 20h\nmov rbp, rdi\nmov r12d, esi\nmov rbx, rdx\nmov rax, fs:28h\nmov [rsp+38h+var_20], rax\nxor eax, eax\nmov edi, 50h ; 'P'; size\ncall _malloc\nmov [rsp+38h+var_28], rax\nmov [rsp+38h+var_2C], 0Ah\nmov dword ptr [rbx], 0\nsub rsp, 8\nlea rax, [rsp+40h+var_2C]\npush rax\nmov r9, rbx\nlea r8, [rsp+48h+var_28]\nmov ecx, 0\nmov edx, 0\nmov esi, r12d\nmov rdi, rbp\ncall sub_11E9\nmov rax, [rsp+48h+var_28]\nadd rsp, 10h\nmov rdx, [rsp+38h+var_20]\nsub rdx, fs:28h\njnz short loc_13BD\nadd rsp, 20h\npop rbx\npop rbp\npop r12\nretn\nloc_13BD:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1332(int a1, int a2, _DWORD *a3)\n{\n int v5; // [rsp+Ch] [rbp-2Ch] BYREF\n _QWORD v6[5]; // [rsp+10h] [rbp-28h] BYREF\n\n v6[1] = __readfsqword(0x28u);\n v6[0] = malloc(0x50uLL);\n v5 = 10;\n *a3 = 0;\n sub_11E9(a1, a2, 0, 0, (unsigned int)v6, (_DWORD)a3, (__int64)&v5);\n return v6[0];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1332(int a1, int a2, uint32_t *a3) {\n int v5;\n uint64_t v6[5];\n v6[1] = __readfsqword(40u);\n v6[0] = malloc(80uLL);\n v5 = 10;\n *a3 = 0;\n sub_11E9(a1, a2, 0, 0, (unsigned int)v6, (uint32_t)a3, (long long)&v5);\n return v6[0];\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, uint32_t *a3) {\n int v5;\n uint64_t v6[5];\n v6[1] = __readfsqword(40u);\n v6[0] = malloc(80uLL);\n v5 = 10;\n *a3 = 0;\n adjac(a1, a2, 0, 0, (unsigned int)v6, (uint32_t)a3, (long long)&v5);\n return v6[0];\n}" + }, + { + "index": 630, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\nvoid adjac(int *ele, int ele_size, int *sub, int sub_size, int ***results, int *results_size, int *cap) {\n\n if (ele_size == 0) {\n\n if (*results_size == *cap) {\n\n *cap *= 2;\n\n *results = realloc(*results, *cap * sizeof(int *));\n\n }\n\n (*results)[*results_size] = malloc(sub_size * sizeof(int));\n\n for (int i = 0; i < sub_size; i++) {\n\n (*results)[*results_size][i] = sub[i];\n\n }\n\n (*results_size)++;\n\n } else {\n\n int *new_sub = (int*)malloc((sub_size + 1) * sizeof(int));\n\n if (sub_size > 0) {\n\n memcpy(new_sub, sub, sub_size * sizeof(int));\n\n }\n\n for (int j = ele[0] - 1; j <= ele[0] + 1; j++) {\n\n new_sub[sub_size] = j;\n\n adjac(ele + 1, ele_size - 1, new_sub, sub_size + 1, results, results_size, cap);\n\n }\n\n free(new_sub);\n\n }\n\n}\n\n\n\n", + "func": "int **func0(int *test_tup, int size, int *result_size) {\n int **results = malloc(10 * sizeof(int *));\n int cap = 10;\n *result_size = 0;\n adjac(test_tup, size, NULL, 0, &results, result_size, &cap);\n return results;\n}", + "test": "int main() {\n\n int size;\n\n int test_tup1[] = {3, 4};\n\n int **res1 = func0(test_tup1, 2, &size);\n\n assert(size == 9);\n\n\n\n int test_tup2[] = {4, 5};\n\n int **res2 = func0(test_tup2, 2, &size);\n\n assert(size == 9);\n\n\n\n int test_tup3[] = {5, 6};\n\n int **res3 = func0(test_tup3, 2, &size);\n\n assert(size == 9);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %esi,%r12d\npush %rbp\nmov %rdi,%rbp\nmov $0x50,%edi\npush %rbx\nmov %rdx,%rbx\nsub $0x20,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x18(%rsp)\nxor %eax,%eax\ncallq 10e0 \nsub $0x8,%rsp\nxor %ecx,%ecx\nxor %edx,%edx\nmov %rax,0x18(%rsp)\nmov %rbx,%r9\nmov %r12d,%esi\nmov %rbp,%rdi\nmovl $0xa,0x14(%rsp)\nlea 0x14(%rsp),%rax\npush %rax\nmovl $0x0,(%rbx)\nlea 0x20(%rsp),%r8\ncallq 1310 \nmov 0x20(%rsp),%rax\npop %rdx\npop %rcx\nmov 0x18(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 1533 \nadd $0x20,%rsp\npop %rbx\npop %rbp\npop %r12\nretq\ncallq 10b0 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r12\nmov r12d, esi\npush rbp\nmov rbp, rdi\nmov edi, 50h ; 'P'; size\npush rbx\nmov rbx, rdx\nsub rsp, 20h\nmov rax, fs:28h\nmov [rsp+38h+var_20], rax\nxor eax, eax\ncall _malloc\nsub rsp, 8\nxor ecx, ecx\nxor edx, edx\nmov [rsp+40h+var_28], rax\nmov r9, rbx\nmov esi, r12d\nmov rdi, rbp\nmov [rsp+40h+var_2C], 0Ah\nlea rax, [rsp+40h+var_2C]\nmov dword ptr [rbx], 0\npush rax\nlea r8, [rsp+48h+var_28]\ncall adjac\nmov rax, [rsp+48h+var_28]\npop rdx\npop rcx\nmov rdx, [rsp+38h+var_20]\nsub rdx, fs:28h\njnz short loc_1523\nadd rsp, 20h\npop rbx\npop rbp\npop r12\nretn\nloc_1523:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, _DWORD *a3)\n{\n int v5; // [rsp+Ch] [rbp-2Ch] BYREF\n _QWORD v6[5]; // [rsp+10h] [rbp-28h] BYREF\n\n v6[1] = __readfsqword(0x28u);\n v6[0] = malloc(0x50uLL);\n v5 = 10;\n *a3 = 0;\n adjac(a1, a2, 0, 0, (unsigned int)v6, (_DWORD)a3, (__int64)&v5);\n return v6[0];\n}", + "ida_strip_asm": "sub_14A0:\nendbr64\npush r12\nmov r12d, esi\npush rbp\nmov rbp, rdi\nmov edi, 50h ; 'P'; size\npush rbx\nmov rbx, rdx\nsub rsp, 20h\nmov rax, fs:28h\nmov [rsp+38h+var_20], rax\nxor eax, eax\ncall _malloc\nsub rsp, 8\nxor ecx, ecx\nxor edx, edx\nmov [rsp+40h+var_28], rax\nmov r9, rbx\nmov esi, r12d\nmov rdi, rbp\nmov [rsp+40h+var_2C], 0Ah\nlea rax, [rsp+40h+var_2C]\nmov dword ptr [rbx], 0\npush rax\nlea r8, [rsp+48h+var_28]\ncall sub_1300\nmov rax, [rsp+48h+var_28]\npop rdx\npop rcx\nmov rdx, [rsp+38h+var_20]\nsub rdx, fs:28h\njnz short loc_1523\nadd rsp, 20h\npop rbx\npop rbp\npop r12\nretn\nloc_1523:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_14A0(int a1, int a2, _DWORD *a3)\n{\n int v5; // [rsp+Ch] [rbp-2Ch] BYREF\n _QWORD v6[5]; // [rsp+10h] [rbp-28h] BYREF\n\n v6[1] = __readfsqword(0x28u);\n v6[0] = malloc(0x50uLL);\n v5 = 10;\n *a3 = 0;\n sub_1300(a1, a2, 0, 0, (unsigned int)v6, (_DWORD)a3, (__int64)&v5);\n return v6[0];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_14A0(int a1, int a2, uint32_t *a3) {\n int v5;\n uint64_t v6[5];\n v6[1] = __readfsqword(40u);\n v6[0] = malloc(80uLL);\n v5 = 10;\n *a3 = 0;\n sub_1300(a1, a2, 0, 0, (unsigned int)v6, (uint32_t)a3, (long long)&v5);\n return v6[0];\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, uint32_t *a3) {\n int v5;\n uint64_t v6[5];\n v6[1] = __readfsqword(40u);\n v6[0] = malloc(80uLL);\n v5 = 10;\n *a3 = 0;\n adjac(a1, a2, 0, 0, (unsigned int)v6, (uint32_t)a3, (long long)&v5);\n return v6[0];\n}" + }, + { + "index": 630, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\nvoid adjac(int *ele, int ele_size, int *sub, int sub_size, int ***results, int *results_size, int *cap) {\n\n if (ele_size == 0) {\n\n if (*results_size == *cap) {\n\n *cap *= 2;\n\n *results = realloc(*results, *cap * sizeof(int *));\n\n }\n\n (*results)[*results_size] = malloc(sub_size * sizeof(int));\n\n for (int i = 0; i < sub_size; i++) {\n\n (*results)[*results_size][i] = sub[i];\n\n }\n\n (*results_size)++;\n\n } else {\n\n int *new_sub = (int*)malloc((sub_size + 1) * sizeof(int));\n\n if (sub_size > 0) {\n\n memcpy(new_sub, sub, sub_size * sizeof(int));\n\n }\n\n for (int j = ele[0] - 1; j <= ele[0] + 1; j++) {\n\n new_sub[sub_size] = j;\n\n adjac(ele + 1, ele_size - 1, new_sub, sub_size + 1, results, results_size, cap);\n\n }\n\n free(new_sub);\n\n }\n\n}\n\n\n\n", + "func": "int **func0(int *test_tup, int size, int *result_size) {\n int **results = malloc(10 * sizeof(int *));\n int cap = 10;\n *result_size = 0;\n adjac(test_tup, size, NULL, 0, &results, result_size, &cap);\n return results;\n}", + "test": "int main() {\n\n int size;\n\n int test_tup1[] = {3, 4};\n\n int **res1 = func0(test_tup1, 2, &size);\n\n assert(size == 9);\n\n\n\n int test_tup2[] = {4, 5};\n\n int **res2 = func0(test_tup2, 2, &size);\n\n assert(size == 9);\n\n\n\n int test_tup3[] = {5, 6};\n\n int **res3 = func0(test_tup3, 2, &size);\n\n assert(size == 9);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\nmov %esi,%r13d\npush %r12\npush %rbp\nmov %rdi,%rbp\nmov $0x50,%edi\npush %rbx\nmov %rdx,%rbx\nsub $0x48,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x38(%rsp)\nxor %eax,%eax\ncallq 10e0 \nmovl $0xa,0x2c(%rsp)\nmov %rax,0x30(%rsp)\nmovl $0x0,(%rbx)\ntest %r13d,%r13d\njne 1538 \nxor %edi,%edi\nmov %rax,%r12\ncallq 10e0 \naddl $0x1,(%rbx)\nmov %rax,(%r12)\nmov 0x38(%rsp),%rax\nxor %fs:0x28,%rax\njne 1683 \nadd $0x48,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\nmov $0x4,%edi\nmov %rbx,%r15\ncallq 10e0 \nmov %r13d,0x18(%rsp)\ncmpl $0x1,0x18(%rsp)\nmov %rax,(%rsp)\nmov 0x0(%rbp),%eax\nlea -0x1(%rax),%r12d\nlea -0x2(%r13),%eax\nmov %eax,0x14(%rsp)\nmov (%rsp),%rax\nmov %r12d,(%rax)\njne 15bc \nmovslq (%r15),%r14\nmov 0x30(%rsp),%r13\ncmp 0x2c(%rsp),%r14d\nje 1658 \nmov $0x4,%edi\ncallq 10e0 \nmov %rax,0x0(%r13,%r14,8)\nmovslq (%r15),%rax\nmov 0x0(%r13,%rax,8),%rax\nmov %r12d,(%rax)\nlea 0x1(%r12),%eax\naddl $0x1,(%r15)\ncmp 0x0(%rbp),%r12d\njg 163f \nmov %eax,%r12d\nmov (%rsp),%rax\ncmpl $0x1,0x18(%rsp)\nmov %r12d,(%rax)\nje 156b \nmov $0x8,%edi\nlea 0x30(%rsp),%rbx\nlea 0x8(%rbp),%r14\ncallq 10e0 \nmov %r12d,0x1c(%rsp)\nmov %r12d,(%rax)\nmov %rax,%r13\nmov 0x4(%rbp),%eax\nmov %rbx,%r12\nlea -0x1(%rax),%r10d\nlea 0x2c(%rsp),%rax\nmov %rax,0x8(%rsp)\nmov %r10d,%ebx\nsub $0x8,%rsp\nmov %ebx,0x4(%r13)\nmov $0x2,%ecx\nmov %r13,%rdx\npushq 0x10(%rsp)\nmov 0x24(%rsp),%esi\nmov %r15,%r9\nmov %r12,%r8\nmov %r14,%rdi\ncallq 1310 \nmov %ebx,%eax\npop %rdx\nadd $0x1,%ebx\npop %rcx\ncmp 0x4(%rbp),%eax\njle 15f1 \nmov 0x1c(%rsp),%r12d\nmov %r13,%rdi\ncallq 10a0 \nlea 0x1(%r12),%eax\ncmp 0x0(%rbp),%r12d\njle 15ab \nmov (%rsp),%rdi\ncallq 10a0 \nmov 0x30(%rsp),%r12\njmpq 150e \nnopw 0x0(%rax,%rax,1)\nadd %r14d,%r14d\nmov %r13,%rdi\nmov %r14d,0x2c(%rsp)\nmovslq %r14d,%r14\nlea 0x0(,%r14,8),%rsi\ncallq 10f0 \nmovslq (%r15),%r14\nmov %rax,0x30(%rsp)\nmov %rax,%r13\njmpq 157e \ncallq 10b0 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov r15d, esi\npush r14\nmov r14, rdx\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 0A8h\nmov [rsp+0D8h+var_B8], rdi\nmov edi, 50h ; 'P'; size\nmov [rsp+0D8h+var_CC], esi\nmov rax, fs:28h\nmov [rsp+0D8h+var_40], rax\nxor eax, eax\ncall _malloc\nmov dword ptr [r14], 0\nmov [rsp+0D8h+ptr], rax\nmov [rsp+0D8h+var_4C], 0Ah\ntest r15d, r15d\njnz short loc_1540\nxor edi, edi; size\nmov rbx, rax\ncall _malloc\nadd dword ptr [r14], 1\nmov [rbx], rax\nloc_1511:\nmov rax, [rsp+0D8h+var_40]\nsub rax, fs:28h\njnz loc_1EA5\nadd rsp, 0A8h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1540:\nmov edi, 4; size\ncall _malloc\ncmp [rsp+0D8h+var_CC], 1\nmov rbp, [rsp+0D8h+var_B8]\nmov r12, rax\nmov rax, [rsp+0D8h+var_B8]\nmov eax, [rax]\nlea r13d, [rax-1]\nmov dword ptr [rsp+0D8h+var_C8], eax\nmov [r12], r13d\njnz loc_15F9\nloc_1570:\nmovsxd rbx, dword ptr [r14]\nmov r15, [rsp+0D8h+ptr]\ncmp ebx, [rsp+0D8h+var_4C]\njz short loc_15CD\nloc_1584:\nmov edi, 4; size\ncall _malloc\nmov [r15+rbx*8], rax\nmovsxd rax, dword ptr [r14]\nmov rax, [r15+rax*8]\nmov [rax], r13d\nlea eax, [r13+1]\nadd dword ptr [r14], 1\ncmp r13d, [rbp+0]\njg short loc_15B8\nmov [r12], eax\nmov r13d, eax\njmp short loc_1570\nloc_15B3:\nmov r12, [rsp+0D8h+var_98]\nloc_15B8:\nmov rdi, r12; ptr\ncall _free\nmov rbx, [rsp+0D8h+ptr]\njmp loc_1511\nloc_15CD:\nadd ebx, ebx\nmov rdi, r15; ptr\nmov [rsp+0D8h+var_4C], ebx\nmovsxd rbx, ebx\nlea rsi, ds:0[rbx*8]; size\ncall _realloc\nmovsxd rbx, dword ptr [r14]\nmov [rsp+0D8h+ptr], rax\nmov r15, rax\njmp short loc_1584\nloc_15F9:\nmov eax, [rsp+0D8h+var_CC]\nmov [rsp+0D8h+var_98], r12\nsub eax, 8\nmov [rsp+0D8h+var_A0], eax\nmov rax, r14\nmov r14d, r13d\nmov r13, rax\nloc_1612:\nmov edi, 8; size\ncall _malloc\ncmp [rsp+0D8h+var_CC], 2\nmov [rax], r14d\nmov r15, rax\nmov rax, [rsp+0D8h+var_B8]\nmov eax, [rax+4]\nlea ecx, [rax-1]\nmov dword ptr [rsp+0D8h+var_C8], eax\nmov [r15+4], ecx\njnz loc_1700\nmov ebp, ecx\nloc_1642:\nmovsxd rbx, dword ptr [r13+0]\nmov r12, [rsp+0D8h+ptr]\ncmp ebx, [rsp+0D8h+var_4C]\njz short loc_16D0\nloc_1657:\nmov edi, 8; size\ncall _malloc\nmov rcx, [rsp+0D8h+var_B8]\nmov [r12+rbx*8], rax\nmovsxd rax, dword ptr [r13+0]\nmov rax, [r12+rax*8]\nmov [rax], r14d\nmovsxd rax, dword ptr [r13+0]\nmov rax, [r12+rax*8]\nmov [rax+4], ebp\nlea eax, [rbp+1]\nadd dword ptr [r13+0], 1\ncmp [rcx+4], ebp\njl short loc_16A0\nmov [r15+4], eax\nmov ebp, eax\njmp short loc_1642\nloc_1695:\nmov r13, r14\nmov r14d, [rsp+0D8h+var_5C]\nmov r15, rbp\nloc_16A0:\nmov rdi, r15; ptr\ncall _free\nmov rcx, [rsp+0D8h+var_B8]\nlea eax, [r14+1]\ncmp [rcx], r14d\njl loc_15B3\nmov rcx, [rsp+0D8h+var_98]\nmov r14d, eax\nmov [rcx], eax\njmp loc_1612\nloc_16D0:\nadd ebx, ebx\nmov rdi, r12; ptr\nmov [rsp+0D8h+var_4C], ebx\nmovsxd rbx, ebx\nlea rsi, ds:0[rbx*8]; size\ncall _realloc\nmovsxd rbx, dword ptr [r13+0]\nmov [rsp+0D8h+ptr], rax\nmov r12, rax\njmp loc_1657\nloc_1700:\nmov r12, [rsp+0D8h+var_B8]\nmov [rsp+0D8h+var_5C], r14d\nmov rbp, r15\nmov r14, r13\nmov r13d, ecx\nloc_1713:\nmov edi, 0Ch; size\ncall _malloc\nmov r15, [rbp+0]\ncmp [rsp+0D8h+var_CC], 3\nmov rcx, rax\nmov [rax], r15\nmov eax, [r12+8]\nlea r8d, [rax-1]\nmov [rcx+8], r8d\njnz loc_1839\nmov rax, r15\nmov [rsp+0D8h+var_C0], rcx\nsar rax, 20h\nmov [rsp+0D8h+var_B0], rbp\nmov ebp, r8d\nmov [rsp+0D8h+var_C8], rax\nmov dword ptr [rsp+0D8h+var_A8], r13d\nmov r13, r14\nloc_1760:\nmov ebx, [r13+0]\nmov r14, [rsp+0D8h+ptr]\ncmp ebx, [rsp+0D8h+var_4C]\njz loc_1808\nloc_1779:\nmov edi, 0Ch; size\ncall _malloc\nmovsxd rdx, ebx\nmov edi, dword ptr [rsp+0D8h+var_C8]\nmov [r14+rdx*8], rax\nmovsxd rax, dword ptr [r13+0]\nmov rax, [r14+rax*8]\nmov [rax], r15d\nmovsxd rax, dword ptr [r13+0]\nmov rax, [r14+rax*8]\nmov [rax+4], edi\nmovsxd rax, dword ptr [r13+0]\nmov rax, [r14+rax*8]\nmov [rax+8], ebp\nlea eax, [rbp+1]\nadd dword ptr [r13+0], 1\ncmp ebp, [r12+8]\njg short loc_17D0\nmov rdi, [rsp+0D8h+var_C0]\nmov ebp, eax\nmov [rdi+8], eax\njmp short loc_1760\nloc_17D0:\nmov r14, r13\nmov rbp, [rsp+0D8h+var_B0]\nmov rcx, [rsp+0D8h+var_C0]\nmov r13d, dword ptr [rsp+0D8h+var_A8]\nloc_17E2:\nmov rdi, rcx; ptr\ncall _free\nlea eax, [r13+1]\ncmp r13d, [r12+4]\njg loc_1695\nmov [rbp+4], eax\nmov r13d, eax\njmp loc_1713\nloc_1808:\nlea edx, [rbx+rbx]\nmov rdi, r14; ptr\nmov [rsp+0D8h+var_4C], edx\nmovsxd rdx, edx\nlea rsi, ds:0[rdx*8]; size\ncall _realloc\nmov ebx, [r13+0]\nmov [rsp+0D8h+ptr], rax\nmov r14, rax\njmp loc_1779\nloc_1839:\nmov [rsp+0D8h+var_60], r13d\nmov rbx, rcx\nmov [rsp+0D8h+var_68], rbp\nmov ebp, r8d\nloc_1849:\nmov edi, 10h; size\ncall _malloc\ncmp [rsp+0D8h+var_CC], 4\nmov r8, rax\nmov rax, [rbx]\nmov [r8], rax\nmov eax, [rbx+8]\nmov [r8+8], eax\nmov eax, [r12+0Ch]\nlea ecx, [rax-1]\nmov [r8+0Ch], ecx\njnz loc_1961\nmov dword ptr [rsp+0D8h+var_C8], ebp\nmov ebp, ecx\nmov [rsp+0D8h+var_C0], rbx\nmov rbx, r8\nloc_1888:\nmovsxd r15, dword ptr [r14]\nmov r13, [rsp+0D8h+ptr]\ncmp r15d, [rsp+0D8h+var_4C]\njz loc_1930\nloc_18A1:\nmov edi, 10h; size\ncall _malloc\nmov edx, [rbx]\nmov [r13+r15*8+0], rax\nmovsxd rax, dword ptr [r14]\nmov rax, [r13+rax*8+0]\nmov [rax], edx\nmovsxd rax, dword ptr [r14]\nmov edx, [rbx+4]\nmov rax, [r13+rax*8+0]\nmov [rax+4], edx\nmovsxd rax, dword ptr [r14]\nmov edx, dword ptr [rsp+0D8h+var_C8]\nmov rax, [r13+rax*8+0]\nmov [rax+8], edx\nmovsxd rax, dword ptr [r14]\nmov rax, [r13+rax*8+0]\nmov [rax+0Ch], ebp\nlea eax, [rbp+1]\nadd dword ptr [r14], 1\ncmp ebp, [r12+0Ch]\njg short loc_1900\nmov [rbx+0Ch], eax\nmov ebp, eax\njmp short loc_1888\nloc_1900:\nmov r8, rbx\nmov rbx, [rsp+0D8h+var_C0]\nmov ebp, edx\nloc_190A:\nmov rdi, r8; ptr\ncall _free\nlea eax, [rbp+1]\ncmp ebp, [r12+8]\njg loc_1E93\nmov [rbx+8], eax\nmov ebp, eax\njmp loc_1849\nloc_1930:\nadd r15d, r15d\nmov rdi, r13; ptr\nmov [rsp+0D8h+var_4C], r15d\nmovsxd r15, r15d\nlea rsi, ds:0[r15*8]; size\ncall _realloc\nmovsxd r15, dword ptr [r14]\nmov [rsp+0D8h+ptr], rax\nmov r13, rax\njmp loc_18A1\nloc_1961:\nmov [rsp+0D8h+var_70], rbx\nmov r15d, ecx\nmov [rsp+0D8h+var_74], ebp\nmov rbp, r8\nloc_1970:\nmov edi, 14h; size\ncall _malloc\nmov rsi, [rbp+0]\nmov rbx, [rbp+8]\nmov r8, rax\ncmp [rsp+0D8h+var_CC], 5\nmov [rax], rsi\nmov [rax+8], rbx\nmov eax, [r12+10h]\nlea r9d, [rax-1]\nmov [r8+10h], r9d\njnz loc_1AD0\nmov r13, rsi\nmov [rsp+0D8h+var_A8], rbp\nsar r13, 20h\nmov [rsp+0D8h+var_B0], r8\nmov [rsp+0D8h+var_C8], r13\nmov [rsp+0D8h+var_C0], rsi\nmov [rsp+0D8h+var_9C], r15d\nmov r15d, r9d\nloc_19C7:\nmov r13d, [r14]\nmov rbp, [rsp+0D8h+ptr]\ncmp r13d, [rsp+0D8h+var_4C]\njz loc_1A98\nloc_19E0:\nmov edi, 14h; size\ncall _malloc\nmovsxd rsi, r13d\nmov edi, dword ptr [rsp+0D8h+var_C0]\nmov [rbp+rsi*8+0], rax\nmovsxd rax, dword ptr [r14]\nmov rsi, rbx\nsar rsi, 20h\nmov rax, [rbp+rax*8+0]\nmov [rax], edi\nmovsxd rax, dword ptr [r14]\nmov edi, dword ptr [rsp+0D8h+var_C8]\nmov rax, [rbp+rax*8+0]\nmov [rax+4], edi\nmovsxd rax, dword ptr [r14]\nmov rax, [rbp+rax*8+0]\nmov [rax+8], ebx\nmovsxd rax, dword ptr [r14]\nmov rax, [rbp+rax*8+0]\nmov [rax+0Ch], esi\nmovsxd rax, dword ptr [r14]\nmov rax, [rbp+rax*8+0]\nmov [rax+10h], r15d\nlea eax, [r15+1]\nadd dword ptr [r14], 1\ncmp r15d, [r12+10h]\njg short loc_1A60\nmov rdi, [rsp+0D8h+var_B0]\nmov r15d, eax\nmov [rdi+10h], eax\njmp loc_19C7\nloc_1A60:\nmov rbp, [rsp+0D8h+var_A8]\nmov r15d, [rsp+0D8h+var_9C]\nmov r8, [rsp+0D8h+var_B0]\nloc_1A6F:\nmov rdi, r8; ptr\ncall _free\nlea eax, [r15+1]\ncmp r15d, [r12+0Ch]\njg loc_1E82\nmov [rbp+0Ch], eax\nmov r15d, eax\njmp loc_1970\nloc_1A98:\nlea esi, [r13+r13+0]\nmov rdi, rbp; ptr\nmov [rsp+0D8h+var_4C], esi\nmovsxd rsi, esi\nshl rsi, 3; size\ncall _realloc\nmov r13d, [r14]\nmov [rsp+0D8h+ptr], rax\nmov rbp, rax\njmp loc_19E0\nloc_1AD0:\nmov dword ptr [rsp+0D8h+var_B0], r9d\nmov [rsp+0D8h+var_78], r15d\nmov [rsp+0D8h+var_80], rbp\nmov rbp, r8\nloc_1AE2:\nmov edi, 18h; size\ncall _malloc\nmovdqu xmm3, xmmword ptr [rbp+0]\ncmp [rsp+0D8h+var_CC], 6\nmov rdx, rax\nmovups xmmword ptr [rax], xmm3\nmov eax, [rbp+10h]\nmov [rdx+10h], eax\nmov eax, [r12+14h]\nlea ecx, [rax-1]\nmov [rdx+14h], ecx\njnz loc_1C10\nmov [rsp+0D8h+var_C8], rbp\nmov r15, rdx\nmov ebp, ecx\nloc_1B1D:\nmov r13d, [r14]\nmov rbx, [rsp+0D8h+ptr]\ncmp r13d, [rsp+0D8h+var_4C]\njz loc_1BE0\nloc_1B36:\nmov edi, 18h; size\ncall _malloc\nmovsxd rsi, r13d\nmov edx, dword ptr [rsp+0D8h+var_B0]\nmov [rbx+rsi*8], rax\nmovsxd rax, dword ptr [r14]\nmov esi, [r15]\nmov rax, [rbx+rax*8]\nmov [rax], esi\nmovsxd rax, dword ptr [r14]\nmov esi, [r15+4]\nmov rax, [rbx+rax*8]\nmov [rax+4], esi\nmovsxd rax, dword ptr [r14]\nmov esi, [r15+8]\nmov rax, [rbx+rax*8]\nmov [rax+8], esi\nmovsxd rax, dword ptr [r14]\nmov esi, [r15+0Ch]\nmov rax, [rbx+rax*8]\nmov [rax+0Ch], esi\nmovsxd rax, dword ptr [r14]\nmov rax, [rbx+rax*8]\nmov [rax+10h], edx\nmovsxd rax, dword ptr [r14]\nmov rax, [rbx+rax*8]\nmov [rax+14h], ebp\nlea eax, [rbp+1]\nadd dword ptr [r14], 1\ncmp ebp, [r12+14h]\njg short loc_1BB0\nmov [r15+14h], eax\nmov ebp, eax\njmp loc_1B1D\nloc_1BB0:\nmov rbp, [rsp+0D8h+var_C8]\nmov rdx, r15\nloc_1BB8:\nmov rdi, rdx; ptr\ncall _free\nmov edx, dword ptr [rsp+0D8h+var_B0]\nlea eax, [rdx+1]\ncmp edx, [r12+10h]\njg loc_1E70\nmov [rbp+10h], eax\nmov dword ptr [rsp+0D8h+var_B0], eax\njmp loc_1AE2\nloc_1BE0:\nlea esi, [r13+r13+0]\nmov rdi, rbx; ptr\nmov [rsp+0D8h+var_4C], esi\nmovsxd rsi, esi\nshl rsi, 3; size\ncall _realloc\nmov r13d, [r14]\nmov [rsp+0D8h+ptr], rax\nmov rbx, rax\njmp loc_1B36\nloc_1C10:\nmov [rsp+0D8h+var_88], rbp\nmov r15, r14\nmov ebx, ecx\nmov r14, rdx\nloc_1C1D:\nmov edi, 1Ch; size\ncall _malloc\nmovdqu xmm2, xmmword ptr [r14]\ncmp [rsp+0D8h+var_CC], 7\nmov r13, rax\nmovups xmmword ptr [rax], xmm2\nmov rax, [r14+10h]\nmov [r13+10h], rax\nmov eax, [r12+18h]\nlea r8d, [rax-1]\nmov [r13+18h], r8d\njnz loc_1D80\nmov dword ptr [rsp+0D8h+var_C8], ebx\nmov rax, r12\nmov r12, r13\nmov [rsp+0D8h+var_C0], r14\nmov r13, rax\nmov r14d, r8d\nloc_1C67:\nmovsxd rbx, dword ptr [r15]\nmov rbp, [rsp+0D8h+ptr]\ncmp ebx, [rsp+0D8h+var_4C]\njz loc_1D50\nloc_1C7F:\nmov edi, 1Ch; size\ncall _malloc\nmov ecx, [r12]\nmov edx, dword ptr [rsp+0D8h+var_C8]\nmov [rbp+rbx*8+0], rax\nmovsxd rax, dword ptr [r15]\nmov rax, [rbp+rax*8+0]\nmov [rax], ecx\nmovsxd rax, dword ptr [r15]\nmov ecx, [r12+4]\nmov rax, [rbp+rax*8+0]\nmov [rax+4], ecx\nmovsxd rax, dword ptr [r15]\nmov ecx, [r12+8]\nmov rax, [rbp+rax*8+0]\nmov [rax+8], ecx\nmovsxd rax, dword ptr [r15]\nmov ecx, [r12+0Ch]\nmov rax, [rbp+rax*8+0]\nmov [rax+0Ch], ecx\nmovsxd rax, dword ptr [r15]\nmov ecx, [r12+10h]\nmov rax, [rbp+rax*8+0]\nmov [rax+10h], ecx\nmovsxd rax, dword ptr [r15]\nmov rax, [rbp+rax*8+0]\nmov [rax+14h], edx\nmovsxd rax, dword ptr [r15]\nmov rax, [rbp+rax*8+0]\nmov [rax+18h], r14d\nlea eax, [r14+1]\nadd dword ptr [r15], 1\ncmp r14d, [r13+18h]\njg short loc_1D18\nmov [r12+18h], eax\nmov r14d, eax\njmp loc_1C67\nloc_1D18:\nmov rax, r13\nmov r14, [rsp+0D8h+var_C0]\nmov r13, r12\nmov ebx, edx\nmov r12, rax\nloc_1D28:\nmov rdi, r13; ptr\ncall _free\nlea eax, [rbx+1]\ncmp ebx, [r12+14h]\njg loc_1E60\nmov [r14+14h], eax\nmov ebx, eax\njmp loc_1C1D\nloc_1D50:\nadd ebx, ebx\nmov rdi, rbp; ptr\nmov [rsp+0D8h+var_4C], ebx\nmovsxd rbx, ebx\nlea rsi, ds:0[rbx*8]; size\ncall _realloc\nmovsxd rbx, dword ptr [r15]\nmov [rsp+0D8h+ptr], rax\nmov rbp, rax\njmp loc_1C7F\nloc_1D80:\nlea rdi, [rsp+0D8h+ptr]\nmov dword ptr [rsp+0D8h+var_A8], r8d\nlea rax, [r12+20h]\nmov [rsp+0D8h+var_C0], rdi\nlea rbp, [rsp+0D8h+var_4C]\nmov [rsp+0D8h+var_90], r14\nmov [rsp+0D8h+var_C8], r15\nmov [rsp+0D8h+var_9C], ebx\nmov rbx, rax\nloc_1DB0:\nmov edi, 20h ; ' '; size\ncall _malloc\nmovdqu xmm0, xmmword ptr [r13+0]\nmovdqu xmm1, xmmword ptr [r13+0Ch]\nmov r14, rax\nmovups xmmword ptr [rax], xmm0\nmovups xmmword ptr [rax+0Ch], xmm1\nmov eax, [r12+1Ch]\nlea r15d, [rax-1]\nmov rax, r14\nmov r14, r13\nmov r13, rax\nloc_1DE2:\nsub rsp, 8\nmov [r13+1Ch], r15d\nmov ecx, 8\nmov rdx, r13\npush rbp\nmov r9, [rsp+0E8h+var_C8]\nmov rdi, rbx\nmov r8, [rsp+0E8h+var_C0]\nmov esi, [rsp+0E8h+var_A0]\ncall adjac\nmov ecx, r15d\npop rax\nadd r15d, 1\npop rdx\ncmp [r12+1Ch], ecx\njge short loc_1DE2\nmov rax, r13\nmov r13, r14\nmov rdi, rax; ptr\ncall _free\nmov edx, dword ptr [rsp+0D8h+var_A8]\nlea eax, [rdx+1]\ncmp edx, [r12+18h]\njg short loc_1E48\nmov [r14+18h], eax\nmov dword ptr [rsp+0D8h+var_A8], eax\njmp loc_1DB0\nloc_1E48:\nmov ebx, [rsp+0D8h+var_9C]\nmov r14, [rsp+0D8h+var_90]\nmov r15, [rsp+0D8h+var_C8]\njmp loc_1D28\nloc_1E60:\nmov rdx, r14\nmov rbp, [rsp+0D8h+var_88]\nmov r14, r15\njmp loc_1BB8\nloc_1E70:\nmov r8, rbp\nmov r15d, [rsp+0D8h+var_78]\nmov rbp, [rsp+0D8h+var_80]\njmp loc_1A6F\nloc_1E82:\nmov r8, rbp\nmov rbx, [rsp+0D8h+var_70]\nmov ebp, [rsp+0D8h+var_74]\njmp loc_190A\nloc_1E93:\nmov rbp, [rsp+0D8h+var_68]\nmov r13d, [rsp+0D8h+var_60]\nmov rcx, rbx\njmp loc_17E2\nloc_1EA5:\ncall ___stack_chk_fail", + "ida_pseudo": "_QWORD *__fastcall func0(int *a1, int a2, int *a3)\n{\n void *v4; // rax\n _QWORD *v5; // rbx\n void *v6; // rax\n int *v8; // r12\n int v9; // r13d\n __int64 v10; // rbx\n _QWORD *v11; // r15\n void *v12; // rax\n int *v13; // rax\n int v14; // r14d\n int *v15; // r13\n _DWORD *v16; // rax\n _DWORD *v17; // r15\n int v18; // ecx\n int i; // ebp\n __int64 v20; // rbx\n _QWORD *v21; // r12\n int v22; // eax\n void *v23; // rax\n int *v24; // r12\n _DWORD *v25; // rbp\n int *v26; // r14\n int j; // r13d\n _DWORD *v28; // rax\n __int64 v29; // r15\n int v30; // r8d\n int v31; // ebp\n int *v32; // r13\n int v33; // ebx\n _QWORD *v34; // r14\n int v35; // eax\n void *v36; // rcx\n int v37; // r13d\n void *v38; // rax\n _DWORD *v39; // rbx\n int k; // ebp\n int *v41; // r8\n int v42; // ecx\n int v43; // ebp\n int *m; // rbx\n __int64 v45; // r15\n _QWORD *v46; // r13\n void *v47; // rax\n int v48; // edx\n __int64 *v49; // r8\n int v50; // ebp\n void *v51; // rax\n int v52; // r15d\n __int64 *v53; // rbp\n __m128i *v54; // rax\n __int64 v55; // rsi\n __int64 v56; // rbx\n int v57; // r9d\n int n; // r15d\n int v59; // r13d\n _QWORD *v60; // rbp\n int v61; // eax\n int v62; // r15d\n __m128i *v63; // r8\n void *v64; // rax\n const __m128i *ii; // rbp\n __m128i *v66; // rdx\n int v67; // ecx\n __m128i *v68; // r15\n int jj; // ebp\n int v70; // r13d\n _QWORD *v71; // rbx\n __m128i *v72; // rdx\n void *v73; // rax\n int *v74; // r15\n int v75; // ebx\n const __m128i *kk; // r14\n char *v77; // r13\n int v78; // r8d\n int *v79; // rax\n char *v80; // r12\n int *v81; // r13\n int mm; // r14d\n __int64 v83; // rbx\n _QWORD *v84; // rbp\n void *v85; // rax\n int v86; // ecx\n int *v87; // rax\n void *v88; // rax\n char *v89; // rax\n __m128i v90; // xmm1\n int v91; // r15d\n char *v92; // r14\n _DWORD *v93; // r13\n int v94; // ecx\n void *v95; // rax\n int v97; // [rsp+10h] [rbp-C8h]\n const __m128i *v98; // [rsp+10h] [rbp-C8h]\n int v99; // [rsp+10h] [rbp-C8h]\n int *v100; // [rsp+10h] [rbp-C8h]\n _DWORD *v101; // [rsp+18h] [rbp-C0h]\n _DWORD *v102; // [rsp+18h] [rbp-C0h]\n const __m128i *v103; // [rsp+18h] [rbp-C0h]\n _DWORD *v104; // [rsp+28h] [rbp-B0h]\n __m128i *v105; // [rsp+28h] [rbp-B0h]\n int v106; // [rsp+28h] [rbp-B0h]\n int v107; // [rsp+30h] [rbp-A8h]\n __int64 *v108; // [rsp+30h] [rbp-A8h]\n int v109; // [rsp+30h] [rbp-A8h]\n int v110; // [rsp+38h] [rbp-A0h]\n int v111; // [rsp+3Ch] [rbp-9Ch]\n int *v112; // [rsp+40h] [rbp-98h]\n const __m128i *v113; // [rsp+48h] [rbp-90h]\n const __m128i *v114; // [rsp+50h] [rbp-88h]\n __int64 *v115; // [rsp+58h] [rbp-80h]\n int v116; // [rsp+60h] [rbp-78h]\n int v117; // [rsp+64h] [rbp-74h]\n _DWORD *v118; // [rsp+68h] [rbp-70h]\n _DWORD *v119; // [rsp+70h] [rbp-68h]\n int v120; // [rsp+78h] [rbp-60h]\n int v121; // [rsp+7Ch] [rbp-5Ch]\n int v122; // [rsp+8Ch] [rbp-4Ch] BYREF\n void *ptr[9]; // [rsp+90h] [rbp-48h] BYREF\n\n ptr[1] = (void *)__readfsqword(0x28u);\n v4 = malloc(0x50uLL);\n *a3 = 0;\n ptr[0] = v4;\n v122 = 10;\n if ( a2 )\n {\n v8 = (int *)malloc(4uLL);\n v9 = *a1 - 1;\n *v8 = v9;\n if ( a2 == 1 )\n {\n while ( 1 )\n {\n v10 = *a3;\n v11 = ptr[0];\n if ( (_DWORD)v10 == v122 )\n {\n v122 = 2 * v10;\n v12 = realloc(ptr[0], 16LL * (_DWORD)v10);\n v10 = *a3;\n ptr[0] = v12;\n v11 = v12;\n }\n v11[v10] = malloc(4uLL);\n *(_DWORD *)v11[(*a3)++] = v9;\n if ( v9 > *a1 )\n break;\n *v8 = ++v9;\n }\n }\n else\n {\n v112 = v8;\n v110 = a2 - 8;\n v13 = a3;\n v14 = v9;\n v15 = v13;\n while ( 1 )\n {\n v16 = malloc(8uLL);\n *v16 = v14;\n v17 = v16;\n v18 = a1[1] - 1;\n v16[1] = v18;\n if ( a2 == 2 )\n {\n for ( i = v18; ; ++i )\n {\n v20 = *v15;\n v21 = ptr[0];\n if ( (_DWORD)v20 == v122 )\n {\n v122 = 2 * v20;\n v23 = realloc(ptr[0], 16LL * (_DWORD)v20);\n v20 = *v15;\n ptr[0] = v23;\n v21 = v23;\n }\n v21[v20] = malloc(8uLL);\n *(_DWORD *)v21[*v15] = v14;\n *(_DWORD *)(v21[(*v15)++] + 4LL) = i;\n if ( a1[1] < i )\n break;\n v17[1] = i + 1;\n }\n }\n else\n {\n v24 = a1;\n v121 = v14;\n v25 = v16;\n v26 = v15;\n for ( j = v18; ; j = v37 + 1 )\n {\n v28 = malloc(0xCuLL);\n v29 = *(_QWORD *)v25;\n *(_QWORD *)v28 = *(_QWORD *)v25;\n v30 = v24[2] - 1;\n v28[2] = v30;\n if ( a2 == 3 )\n {\n v101 = v28;\n v104 = v25;\n v31 = v30;\n v107 = j;\n v32 = v26;\n while ( 1 )\n {\n v33 = *v32;\n v34 = ptr[0];\n if ( *v32 == v122 )\n {\n v122 = 2 * v33;\n v38 = realloc(ptr[0], 16LL * v33);\n v33 = *v32;\n ptr[0] = v38;\n v34 = v38;\n }\n v34[v33] = malloc(0xCuLL);\n *(_QWORD *)v34[*v32] = v29;\n *(_DWORD *)(v34[*v32] + 8LL) = v31;\n v35 = v31 + 1;\n ++*v32;\n if ( v31 > v24[2] )\n break;\n ++v31;\n v101[2] = v35;\n }\n v26 = v32;\n v25 = v104;\n v36 = v101;\n v37 = v107;\n }\n else\n {\n v120 = j;\n v39 = v28;\n v119 = v25;\n for ( k = v30; ; k = v50 + 1 )\n {\n v41 = (int *)malloc(0x10uLL);\n *(_QWORD *)v41 = *(_QWORD *)v39;\n v41[2] = v39[2];\n v42 = v24[3] - 1;\n v41[3] = v42;\n if ( a2 == 4 )\n {\n v97 = k;\n v43 = v42;\n v102 = v39;\n for ( m = v41; ; m[3] = ++v43 )\n {\n v45 = *v26;\n v46 = ptr[0];\n if ( (_DWORD)v45 == v122 )\n {\n v122 = 2 * v45;\n v51 = realloc(ptr[0], 16LL * (_DWORD)v45);\n v45 = *v26;\n ptr[0] = v51;\n v46 = v51;\n }\n v47 = malloc(0x10uLL);\n v48 = *m;\n v46[v45] = v47;\n *(_DWORD *)v46[*v26] = v48;\n *(_DWORD *)(v46[*v26] + 4LL) = m[1];\n *(_DWORD *)(v46[*v26] + 8LL) = v97;\n *(_DWORD *)(v46[(*v26)++] + 12LL) = v43;\n if ( v43 > v24[3] )\n break;\n }\n v49 = (__int64 *)m;\n v39 = v102;\n v50 = v97;\n }\n else\n {\n v118 = v39;\n v52 = v42;\n v117 = k;\n v53 = (__int64 *)v41;\n while ( 1 )\n {\n v54 = (__m128i *)malloc(0x14uLL);\n v55 = *v53;\n v56 = v53[1];\n v54->m128i_i64[0] = *v53;\n v54->m128i_i64[1] = v56;\n v57 = v24[4] - 1;\n v54[1].m128i_i32[0] = v57;\n if ( a2 == 5 )\n {\n v108 = v53;\n v105 = v54;\n v111 = v52;\n for ( n = v57; ; ++n )\n {\n v59 = *v26;\n v60 = ptr[0];\n if ( *v26 == v122 )\n {\n v122 = 2 * v59;\n v64 = realloc(ptr[0], 16LL * v59);\n v59 = *v26;\n ptr[0] = v64;\n v60 = v64;\n }\n v60[v59] = malloc(0x14uLL);\n *(_QWORD *)v60[*v26] = v55;\n *(_QWORD *)(v60[*v26] + 8LL) = v56;\n *(_DWORD *)(v60[*v26] + 16LL) = n;\n v61 = n + 1;\n ++*v26;\n if ( n > v24[4] )\n break;\n v105[1].m128i_i32[0] = v61;\n }\n v53 = v108;\n v62 = v111;\n v63 = v105;\n }\n else\n {\n v106 = v57;\n v116 = v52;\n v115 = v53;\n for ( ii = v54; ; ii[1].m128i_i32[0] = ++v106 )\n {\n v66 = (__m128i *)malloc(0x18uLL);\n *v66 = _mm_loadu_si128(ii);\n v66[1].m128i_i32[0] = ii[1].m128i_i32[0];\n v67 = v24[5] - 1;\n v66[1].m128i_i32[1] = v67;\n if ( a2 == 6 )\n {\n v98 = ii;\n v68 = v66;\n for ( jj = v67; ; ++jj )\n {\n v70 = *v26;\n v71 = ptr[0];\n if ( *v26 == v122 )\n {\n v122 = 2 * v70;\n v73 = realloc(ptr[0], 16LL * v70);\n v70 = *v26;\n ptr[0] = v73;\n v71 = v73;\n }\n v71[v70] = malloc(0x18uLL);\n *(_DWORD *)v71[*v26] = v68->m128i_i32[0];\n *(_DWORD *)(v71[*v26] + 4LL) = v68->m128i_i32[1];\n *(_DWORD *)(v71[*v26] + 8LL) = v68->m128i_i32[2];\n *(_DWORD *)(v71[*v26] + 12LL) = v68->m128i_i32[3];\n *(_DWORD *)(v71[*v26] + 16LL) = v106;\n *(_DWORD *)(v71[(*v26)++] + 20LL) = jj;\n if ( jj > v24[5] )\n break;\n v68[1].m128i_i32[1] = jj + 1;\n }\n ii = v98;\n v72 = v68;\n }\n else\n {\n v114 = ii;\n v74 = v26;\n v75 = v67;\n for ( kk = v66; ; kk[1].m128i_i32[1] = ++v75 )\n {\n v77 = (char *)malloc(0x1CuLL);\n *(__m128i *)v77 = _mm_loadu_si128(kk);\n *((_QWORD *)v77 + 2) = kk[1].m128i_i64[0];\n v78 = v24[6] - 1;\n *((_DWORD *)v77 + 6) = v78;\n if ( a2 == 7 )\n {\n v99 = v75;\n v79 = v24;\n v80 = v77;\n v103 = kk;\n v81 = v79;\n for ( mm = v78; ; ++mm )\n {\n v83 = *v74;\n v84 = ptr[0];\n if ( (_DWORD)v83 == v122 )\n {\n v122 = 2 * v83;\n v88 = realloc(ptr[0], 16LL * (_DWORD)v83);\n v83 = *v74;\n ptr[0] = v88;\n v84 = v88;\n }\n v85 = malloc(0x1CuLL);\n v86 = *(_DWORD *)v80;\n v84[v83] = v85;\n *(_DWORD *)v84[*v74] = v86;\n *(_DWORD *)(v84[*v74] + 4LL) = *((_DWORD *)v80 + 1);\n *(_DWORD *)(v84[*v74] + 8LL) = *((_DWORD *)v80 + 2);\n *(_DWORD *)(v84[*v74] + 12LL) = *((_DWORD *)v80 + 3);\n *(_DWORD *)(v84[*v74] + 16LL) = *((_DWORD *)v80 + 4);\n *(_DWORD *)(v84[*v74] + 20LL) = v99;\n *(_DWORD *)(v84[(*v74)++] + 24LL) = mm;\n if ( mm > v81[6] )\n break;\n *((_DWORD *)v80 + 6) = mm + 1;\n }\n v87 = v81;\n kk = v103;\n v77 = v80;\n v75 = v99;\n v24 = v87;\n }\n else\n {\n v109 = v78;\n v113 = kk;\n v100 = v74;\n while ( 1 )\n {\n v89 = (char *)malloc(0x20uLL);\n v90 = _mm_loadu_si128((const __m128i *)(v77 + 12));\n *(__m128i *)v89 = _mm_loadu_si128((const __m128i *)v77);\n *(__m128i *)(v89 + 12) = v90;\n v91 = v24[7] - 1;\n v92 = v77;\n v93 = v89;\n do\n {\n v93[7] = v91;\n adjac(\n (_DWORD)v24 + 32,\n v110,\n (_DWORD)v93,\n 8,\n (unsigned int)ptr,\n (_DWORD)v100,\n (__int64)&v122);\n v94 = v91++;\n }\n while ( v24[7] >= v94 );\n v95 = v93;\n v77 = v92;\n free(v95);\n if ( v109 > v24[6] )\n break;\n *((_DWORD *)v92 + 6) = ++v109;\n }\n kk = v113;\n v74 = v100;\n }\n free(v77);\n if ( v75 > v24[5] )\n break;\n }\n v72 = (__m128i *)kk;\n ii = v114;\n v26 = v74;\n }\n free(v72);\n if ( v106 > v24[4] )\n break;\n }\n v63 = (__m128i *)ii;\n v62 = v116;\n v53 = v115;\n }\n free(v63);\n if ( v62 > v24[3] )\n break;\n *((_DWORD *)v53 + 3) = v62 + 1;\n v52 = v62 + 1;\n }\n v49 = v53;\n v39 = v118;\n v50 = v117;\n }\n free(v49);\n if ( v50 > v24[2] )\n break;\n v39[2] = v50 + 1;\n }\n v25 = v119;\n v37 = v120;\n v36 = v39;\n }\n free(v36);\n if ( v37 > v24[1] )\n break;\n v25[1] = v37 + 1;\n }\n v15 = v26;\n v14 = v121;\n v17 = v25;\n }\n free(v17);\n v22 = v14 + 1;\n if ( *a1 < v14 )\n break;\n ++v14;\n *v112 = v22;\n }\n v8 = v112;\n }\n free(v8);\n return ptr[0];\n }\n else\n {\n v5 = v4;\n v6 = malloc(0LL);\n ++*a3;\n *v5 = v6;\n }\n return v5;\n}", + "ida_strip_asm": "sub_14A0:\nendbr64\npush r15\nmov r15d, esi\npush r14\nmov r14, rdx\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 0A8h\nmov [rsp+0D8h+var_B8], rdi\nmov edi, 50h ; 'P'; size\nmov [rsp+0D8h+var_CC], esi\nmov rax, fs:28h\nmov [rsp+0D8h+var_40], rax\nxor eax, eax\ncall _malloc\nmov dword ptr [r14], 0\nmov [rsp+0D8h+ptr], rax\nmov [rsp+0D8h+var_4C], 0Ah\ntest r15d, r15d\njnz short loc_1540\nxor edi, edi; size\nmov rbx, rax\ncall _malloc\nadd dword ptr [r14], 1\nmov [rbx], rax\nloc_1511:\nmov rax, [rsp+0D8h+var_40]\nsub rax, fs:28h\njnz loc_1EA5\nadd rsp, 0A8h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1540:\nmov edi, 4; size\ncall _malloc\ncmp [rsp+0D8h+var_CC], 1\nmov rbp, [rsp+0D8h+var_B8]\nmov r12, rax\nmov rax, [rsp+0D8h+var_B8]\nmov eax, [rax]\nlea r13d, [rax-1]\nmov dword ptr [rsp+0D8h+var_C8], eax\nmov [r12], r13d\njnz loc_15F9\nloc_1570:\nmovsxd rbx, dword ptr [r14]\nmov r15, [rsp+0D8h+ptr]\ncmp ebx, [rsp+0D8h+var_4C]\njz short loc_15CD\nloc_1584:\nmov edi, 4; size\ncall _malloc\nmov [r15+rbx*8], rax\nmovsxd rax, dword ptr [r14]\nmov rax, [r15+rax*8]\nmov [rax], r13d\nlea eax, [r13+1]\nadd dword ptr [r14], 1\ncmp r13d, [rbp+0]\njg short loc_15B8\nmov [r12], eax\nmov r13d, eax\njmp short loc_1570\nloc_15B3:\nmov r12, [rsp+0D8h+var_98]\nloc_15B8:\nmov rdi, r12; ptr\ncall _free\nmov rbx, [rsp+0D8h+ptr]\njmp loc_1511\nloc_15CD:\nadd ebx, ebx\nmov rdi, r15; ptr\nmov [rsp+0D8h+var_4C], ebx\nmovsxd rbx, ebx\nlea rsi, ds:0[rbx*8]; size\ncall _realloc\nmovsxd rbx, dword ptr [r14]\nmov [rsp+0D8h+ptr], rax\nmov r15, rax\njmp short loc_1584\nloc_15F9:\nmov eax, [rsp+0D8h+var_CC]\nmov [rsp+0D8h+var_98], r12\nsub eax, 8\nmov [rsp+0D8h+var_A0], eax\nmov rax, r14\nmov r14d, r13d\nmov r13, rax\nloc_1612:\nmov edi, 8; size\ncall _malloc\ncmp [rsp+0D8h+var_CC], 2\nmov [rax], r14d\nmov r15, rax\nmov rax, [rsp+0D8h+var_B8]\nmov eax, [rax+4]\nlea ecx, [rax-1]\nmov dword ptr [rsp+0D8h+var_C8], eax\nmov [r15+4], ecx\njnz loc_1700\nmov ebp, ecx\nloc_1642:\nmovsxd rbx, dword ptr [r13+0]\nmov r12, [rsp+0D8h+ptr]\ncmp ebx, [rsp+0D8h+var_4C]\njz short loc_16D0\nloc_1657:\nmov edi, 8; size\ncall _malloc\nmov rcx, [rsp+0D8h+var_B8]\nmov [r12+rbx*8], rax\nmovsxd rax, dword ptr [r13+0]\nmov rax, [r12+rax*8]\nmov [rax], r14d\nmovsxd rax, dword ptr [r13+0]\nmov rax, [r12+rax*8]\nmov [rax+4], ebp\nlea eax, [rbp+1]\nadd dword ptr [r13+0], 1\ncmp [rcx+4], ebp\njl short loc_16A0\nmov [r15+4], eax\nmov ebp, eax\njmp short loc_1642\nloc_1695:\nmov r13, r14\nmov r14d, [rsp+0D8h+var_5C]\nmov r15, rbp\nloc_16A0:\nmov rdi, r15; ptr\ncall _free\nmov rcx, [rsp+0D8h+var_B8]\nlea eax, [r14+1]\ncmp [rcx], r14d\njl loc_15B3\nmov rcx, [rsp+0D8h+var_98]\nmov r14d, eax\nmov [rcx], eax\njmp loc_1612\nloc_16D0:\nadd ebx, ebx\nmov rdi, r12; ptr\nmov [rsp+0D8h+var_4C], ebx\nmovsxd rbx, ebx\nlea rsi, ds:0[rbx*8]; size\ncall _realloc\nmovsxd rbx, dword ptr [r13+0]\nmov [rsp+0D8h+ptr], rax\nmov r12, rax\njmp loc_1657\nloc_1700:\nmov r12, [rsp+0D8h+var_B8]\nmov [rsp+0D8h+var_5C], r14d\nmov rbp, r15\nmov r14, r13\nmov r13d, ecx\nloc_1713:\nmov edi, 0Ch; size\ncall _malloc\nmov r15, [rbp+0]\ncmp [rsp+0D8h+var_CC], 3\nmov rcx, rax\nmov [rax], r15\nmov eax, [r12+8]\nlea r8d, [rax-1]\nmov [rcx+8], r8d\njnz loc_1839\nmov rax, r15\nmov [rsp+0D8h+var_C0], rcx\nsar rax, 20h\nmov [rsp+0D8h+var_B0], rbp\nmov ebp, r8d\nmov [rsp+0D8h+var_C8], rax\nmov dword ptr [rsp+0D8h+var_A8], r13d\nmov r13, r14\nloc_1760:\nmov ebx, [r13+0]\nmov r14, [rsp+0D8h+ptr]\ncmp ebx, [rsp+0D8h+var_4C]\njz loc_1808\nloc_1779:\nmov edi, 0Ch; size\ncall _malloc\nmovsxd rdx, ebx\nmov edi, dword ptr [rsp+0D8h+var_C8]\nmov [r14+rdx*8], rax\nmovsxd rax, dword ptr [r13+0]\nmov rax, [r14+rax*8]\nmov [rax], r15d\nmovsxd rax, dword ptr [r13+0]\nmov rax, [r14+rax*8]\nmov [rax+4], edi\nmovsxd rax, dword ptr [r13+0]\nmov rax, [r14+rax*8]\nmov [rax+8], ebp\nlea eax, [rbp+1]\nadd dword ptr [r13+0], 1\ncmp ebp, [r12+8]\njg short loc_17D0\nmov rdi, [rsp+0D8h+var_C0]\nmov ebp, eax\nmov [rdi+8], eax\njmp short loc_1760\nloc_17D0:\nmov r14, r13\nmov rbp, [rsp+0D8h+var_B0]\nmov rcx, [rsp+0D8h+var_C0]\nmov r13d, dword ptr [rsp+0D8h+var_A8]\nloc_17E2:\nmov rdi, rcx; ptr\ncall _free\nlea eax, [r13+1]\ncmp r13d, [r12+4]\njg loc_1695\nmov [rbp+4], eax\nmov r13d, eax\njmp loc_1713\nloc_1808:\nlea edx, [rbx+rbx]\nmov rdi, r14; ptr\nmov [rsp+0D8h+var_4C], edx\nmovsxd rdx, edx\nlea rsi, ds:0[rdx*8]; size\ncall _realloc\nmov ebx, [r13+0]\nmov [rsp+0D8h+ptr], rax\nmov r14, rax\njmp loc_1779\nloc_1839:\nmov [rsp+0D8h+var_60], r13d\nmov rbx, rcx\nmov [rsp+0D8h+var_68], rbp\nmov ebp, r8d\nloc_1849:\nmov edi, 10h; size\ncall _malloc\ncmp [rsp+0D8h+var_CC], 4\nmov r8, rax\nmov rax, [rbx]\nmov [r8], rax\nmov eax, [rbx+8]\nmov [r8+8], eax\nmov eax, [r12+0Ch]\nlea ecx, [rax-1]\nmov [r8+0Ch], ecx\njnz loc_1961\nmov dword ptr [rsp+0D8h+var_C8], ebp\nmov ebp, ecx\nmov [rsp+0D8h+var_C0], rbx\nmov rbx, r8\nloc_1888:\nmovsxd r15, dword ptr [r14]\nmov r13, [rsp+0D8h+ptr]\ncmp r15d, [rsp+0D8h+var_4C]\njz loc_1930\nloc_18A1:\nmov edi, 10h; size\ncall _malloc\nmov edx, [rbx]\nmov [r13+r15*8+0], rax\nmovsxd rax, dword ptr [r14]\nmov rax, [r13+rax*8+0]\nmov [rax], edx\nmovsxd rax, dword ptr [r14]\nmov edx, [rbx+4]\nmov rax, [r13+rax*8+0]\nmov [rax+4], edx\nmovsxd rax, dword ptr [r14]\nmov edx, dword ptr [rsp+0D8h+var_C8]\nmov rax, [r13+rax*8+0]\nmov [rax+8], edx\nmovsxd rax, dword ptr [r14]\nmov rax, [r13+rax*8+0]\nmov [rax+0Ch], ebp\nlea eax, [rbp+1]\nadd dword ptr [r14], 1\ncmp ebp, [r12+0Ch]\njg short loc_1900\nmov [rbx+0Ch], eax\nmov ebp, eax\njmp short loc_1888\nloc_1900:\nmov r8, rbx\nmov rbx, [rsp+0D8h+var_C0]\nmov ebp, edx\nloc_190A:\nmov rdi, r8; ptr\ncall _free\nlea eax, [rbp+1]\ncmp ebp, [r12+8]\njg loc_1E93\nmov [rbx+8], eax\nmov ebp, eax\njmp loc_1849\nloc_1930:\nadd r15d, r15d\nmov rdi, r13; ptr\nmov [rsp+0D8h+var_4C], r15d\nmovsxd r15, r15d\nlea rsi, ds:0[r15*8]; size\ncall _realloc\nmovsxd r15, dword ptr [r14]\nmov [rsp+0D8h+ptr], rax\nmov r13, rax\njmp loc_18A1\nloc_1961:\nmov [rsp+0D8h+var_70], rbx\nmov r15d, ecx\nmov [rsp+0D8h+var_74], ebp\nmov rbp, r8\nloc_1970:\nmov edi, 14h; size\ncall _malloc\nmov rsi, [rbp+0]\nmov rbx, [rbp+8]\nmov r8, rax\ncmp [rsp+0D8h+var_CC], 5\nmov [rax], rsi\nmov [rax+8], rbx\nmov eax, [r12+10h]\nlea r9d, [rax-1]\nmov [r8+10h], r9d\njnz loc_1AD0\nmov r13, rsi\nmov [rsp+0D8h+var_A8], rbp\nsar r13, 20h\nmov [rsp+0D8h+var_B0], r8\nmov [rsp+0D8h+var_C8], r13\nmov [rsp+0D8h+var_C0], rsi\nmov [rsp+0D8h+var_9C], r15d\nmov r15d, r9d\nloc_19C7:\nmov r13d, [r14]\nmov rbp, [rsp+0D8h+ptr]\ncmp r13d, [rsp+0D8h+var_4C]\njz loc_1A98\nloc_19E0:\nmov edi, 14h; size\ncall _malloc\nmovsxd rsi, r13d\nmov edi, dword ptr [rsp+0D8h+var_C0]\nmov [rbp+rsi*8+0], rax\nmovsxd rax, dword ptr [r14]\nmov rsi, rbx\nsar rsi, 20h\nmov rax, [rbp+rax*8+0]\nmov [rax], edi\nmovsxd rax, dword ptr [r14]\nmov edi, dword ptr [rsp+0D8h+var_C8]\nmov rax, [rbp+rax*8+0]\nmov [rax+4], edi\nmovsxd rax, dword ptr [r14]\nmov rax, [rbp+rax*8+0]\nmov [rax+8], ebx\nmovsxd rax, dword ptr [r14]\nmov rax, [rbp+rax*8+0]\nmov [rax+0Ch], esi\nmovsxd rax, dword ptr [r14]\nmov rax, [rbp+rax*8+0]\nmov [rax+10h], r15d\nlea eax, [r15+1]\nadd dword ptr [r14], 1\ncmp r15d, [r12+10h]\njg short loc_1A60\nmov rdi, [rsp+0D8h+var_B0]\nmov r15d, eax\nmov [rdi+10h], eax\njmp loc_19C7\nloc_1A60:\nmov rbp, [rsp+0D8h+var_A8]\nmov r15d, [rsp+0D8h+var_9C]\nmov r8, [rsp+0D8h+var_B0]\nloc_1A6F:\nmov rdi, r8; ptr\ncall _free\nlea eax, [r15+1]\ncmp r15d, [r12+0Ch]\njg loc_1E82\nmov [rbp+0Ch], eax\nmov r15d, eax\njmp loc_1970\nloc_1A98:\nlea esi, [r13+r13+0]\nmov rdi, rbp; ptr\nmov [rsp+0D8h+var_4C], esi\nmovsxd rsi, esi\nshl rsi, 3; size\ncall _realloc\nmov r13d, [r14]\nmov [rsp+0D8h+ptr], rax\nmov rbp, rax\njmp loc_19E0\nloc_1AD0:\nmov dword ptr [rsp+0D8h+var_B0], r9d\nmov [rsp+0D8h+var_78], r15d\nmov [rsp+0D8h+var_80], rbp\nmov rbp, r8\nloc_1AE2:\nmov edi, 18h; size\ncall _malloc\nmovdqu xmm3, xmmword ptr [rbp+0]\ncmp [rsp+0D8h+var_CC], 6\nmov rdx, rax\nmovups xmmword ptr [rax], xmm3\nmov eax, [rbp+10h]\nmov [rdx+10h], eax\nmov eax, [r12+14h]\nlea ecx, [rax-1]\nmov [rdx+14h], ecx\njnz loc_1C10\nmov [rsp+0D8h+var_C8], rbp\nmov r15, rdx\nmov ebp, ecx\nloc_1B1D:\nmov r13d, [r14]\nmov rbx, [rsp+0D8h+ptr]\ncmp r13d, [rsp+0D8h+var_4C]\njz loc_1BE0\nloc_1B36:\nmov edi, 18h; size\ncall _malloc\nmovsxd rsi, r13d\nmov edx, dword ptr [rsp+0D8h+var_B0]\nmov [rbx+rsi*8], rax\nmovsxd rax, dword ptr [r14]\nmov esi, [r15]\nmov rax, [rbx+rax*8]\nmov [rax], esi\nmovsxd rax, dword ptr [r14]\nmov esi, [r15+4]\nmov rax, [rbx+rax*8]\nmov [rax+4], esi\nmovsxd rax, dword ptr [r14]\nmov esi, [r15+8]\nmov rax, [rbx+rax*8]\nmov [rax+8], esi\nmovsxd rax, dword ptr [r14]\nmov esi, [r15+0Ch]\nmov rax, [rbx+rax*8]\nmov [rax+0Ch], esi\nmovsxd rax, dword ptr [r14]\nmov rax, [rbx+rax*8]\nmov [rax+10h], edx\nmovsxd rax, dword ptr [r14]\nmov rax, [rbx+rax*8]\nmov [rax+14h], ebp\nlea eax, [rbp+1]\nadd dword ptr [r14], 1\ncmp ebp, [r12+14h]\njg short loc_1BB0\nmov [r15+14h], eax\nmov ebp, eax\njmp loc_1B1D\nloc_1BB0:\nmov rbp, [rsp+0D8h+var_C8]\nmov rdx, r15\nloc_1BB8:\nmov rdi, rdx; ptr\ncall _free\nmov edx, dword ptr [rsp+0D8h+var_B0]\nlea eax, [rdx+1]\ncmp edx, [r12+10h]\njg loc_1E70\nmov [rbp+10h], eax\nmov dword ptr [rsp+0D8h+var_B0], eax\njmp loc_1AE2\nloc_1BE0:\nlea esi, [r13+r13+0]\nmov rdi, rbx; ptr\nmov [rsp+0D8h+var_4C], esi\nmovsxd rsi, esi\nshl rsi, 3; size\ncall _realloc\nmov r13d, [r14]\nmov [rsp+0D8h+ptr], rax\nmov rbx, rax\njmp loc_1B36\nloc_1C10:\nmov [rsp+0D8h+var_88], rbp\nmov r15, r14\nmov ebx, ecx\nmov r14, rdx\nloc_1C1D:\nmov edi, 1Ch; size\ncall _malloc\nmovdqu xmm2, xmmword ptr [r14]\ncmp [rsp+0D8h+var_CC], 7\nmov r13, rax\nmovups xmmword ptr [rax], xmm2\nmov rax, [r14+10h]\nmov [r13+10h], rax\nmov eax, [r12+18h]\nlea r8d, [rax-1]\nmov [r13+18h], r8d\njnz loc_1D80\nmov dword ptr [rsp+0D8h+var_C8], ebx\nmov rax, r12\nmov r12, r13\nmov [rsp+0D8h+var_C0], r14\nmov r13, rax\nmov r14d, r8d\nloc_1C67:\nmovsxd rbx, dword ptr [r15]\nmov rbp, [rsp+0D8h+ptr]\ncmp ebx, [rsp+0D8h+var_4C]\njz loc_1D50\nloc_1C7F:\nmov edi, 1Ch; size\ncall _malloc\nmov ecx, [r12]\nmov edx, dword ptr [rsp+0D8h+var_C8]\nmov [rbp+rbx*8+0], rax\nmovsxd rax, dword ptr [r15]\nmov rax, [rbp+rax*8+0]\nmov [rax], ecx\nmovsxd rax, dword ptr [r15]\nmov ecx, [r12+4]\nmov rax, [rbp+rax*8+0]\nmov [rax+4], ecx\nmovsxd rax, dword ptr [r15]\nmov ecx, [r12+8]\nmov rax, [rbp+rax*8+0]\nmov [rax+8], ecx\nmovsxd rax, dword ptr [r15]\nmov ecx, [r12+0Ch]\nmov rax, [rbp+rax*8+0]\nmov [rax+0Ch], ecx\nmovsxd rax, dword ptr [r15]\nmov ecx, [r12+10h]\nmov rax, [rbp+rax*8+0]\nmov [rax+10h], ecx\nmovsxd rax, dword ptr [r15]\nmov rax, [rbp+rax*8+0]\nmov [rax+14h], edx\nmovsxd rax, dword ptr [r15]\nmov rax, [rbp+rax*8+0]\nmov [rax+18h], r14d\nlea eax, [r14+1]\nadd dword ptr [r15], 1\ncmp r14d, [r13+18h]\njg short loc_1D18\nmov [r12+18h], eax\nmov r14d, eax\njmp loc_1C67\nloc_1D18:\nmov rax, r13\nmov r14, [rsp+0D8h+var_C0]\nmov r13, r12\nmov ebx, edx\nmov r12, rax\nloc_1D28:\nmov rdi, r13; ptr\ncall _free\nlea eax, [rbx+1]\ncmp ebx, [r12+14h]\njg loc_1E60\nmov [r14+14h], eax\nmov ebx, eax\njmp loc_1C1D\nloc_1D50:\nadd ebx, ebx\nmov rdi, rbp; ptr\nmov [rsp+0D8h+var_4C], ebx\nmovsxd rbx, ebx\nlea rsi, ds:0[rbx*8]; size\ncall _realloc\nmovsxd rbx, dword ptr [r15]\nmov [rsp+0D8h+ptr], rax\nmov rbp, rax\njmp loc_1C7F\nloc_1D80:\nlea rdi, [rsp+0D8h+ptr]\nmov dword ptr [rsp+0D8h+var_A8], r8d\nlea rax, [r12+20h]\nmov [rsp+0D8h+var_C0], rdi\nlea rbp, [rsp+0D8h+var_4C]\nmov [rsp+0D8h+var_90], r14\nmov [rsp+0D8h+var_C8], r15\nmov [rsp+0D8h+var_9C], ebx\nmov rbx, rax\nloc_1DB0:\nmov edi, 20h ; ' '; size\ncall _malloc\nmovdqu xmm0, xmmword ptr [r13+0]\nmovdqu xmm1, xmmword ptr [r13+0Ch]\nmov r14, rax\nmovups xmmword ptr [rax], xmm0\nmovups xmmword ptr [rax+0Ch], xmm1\nmov eax, [r12+1Ch]\nlea r15d, [rax-1]\nmov rax, r14\nmov r14, r13\nmov r13, rax\nloc_1DE2:\nsub rsp, 8\nmov [r13+1Ch], r15d\nmov ecx, 8\nmov rdx, r13\npush rbp\nmov r9, [rsp+0E8h+var_C8]\nmov rdi, rbx\nmov r8, [rsp+0E8h+var_C0]\nmov esi, [rsp+0E8h+var_A0]\ncall sub_1300\nmov ecx, r15d\npop rax\nadd r15d, 1\npop rdx\ncmp [r12+1Ch], ecx\njge short loc_1DE2\nmov rax, r13\nmov r13, r14\nmov rdi, rax; ptr\ncall _free\nmov edx, dword ptr [rsp+0D8h+var_A8]\nlea eax, [rdx+1]\ncmp edx, [r12+18h]\njg short loc_1E48\nmov [r14+18h], eax\nmov dword ptr [rsp+0D8h+var_A8], eax\njmp loc_1DB0\nloc_1E48:\nmov ebx, [rsp+0D8h+var_9C]\nmov r14, [rsp+0D8h+var_90]\nmov r15, [rsp+0D8h+var_C8]\njmp loc_1D28\nloc_1E60:\nmov rdx, r14\nmov rbp, [rsp+0D8h+var_88]\nmov r14, r15\njmp loc_1BB8\nloc_1E70:\nmov r8, rbp\nmov r15d, [rsp+0D8h+var_78]\nmov rbp, [rsp+0D8h+var_80]\njmp loc_1A6F\nloc_1E82:\nmov r8, rbp\nmov rbx, [rsp+0D8h+var_70]\nmov ebp, [rsp+0D8h+var_74]\njmp loc_190A\nloc_1E93:\nmov rbp, [rsp+0D8h+var_68]\nmov r13d, [rsp+0D8h+var_60]\nmov rcx, rbx\njmp loc_17E2\nloc_1EA5:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_QWORD *__fastcall sub_14A0(int *a1, int a2, int *a3)\n{\n void *v4; // rax\n _QWORD *v5; // rbx\n void *v6; // rax\n int *v8; // r12\n int v9; // r13d\n __int64 v10; // rbx\n _QWORD *v11; // r15\n void *v12; // rax\n int *v13; // rax\n int v14; // r14d\n int *v15; // r13\n _DWORD *v16; // rax\n _DWORD *v17; // r15\n int v18; // ecx\n int i; // ebp\n __int64 v20; // rbx\n _QWORD *v21; // r12\n int v22; // eax\n void *v23; // rax\n int *v24; // r12\n _DWORD *v25; // rbp\n int *v26; // r14\n int j; // r13d\n _DWORD *v28; // rax\n __int64 v29; // r15\n int v30; // r8d\n int v31; // ebp\n int *v32; // r13\n int v33; // ebx\n _QWORD *v34; // r14\n int v35; // eax\n void *v36; // rcx\n int v37; // r13d\n void *v38; // rax\n _DWORD *v39; // rbx\n int k; // ebp\n int *v41; // r8\n int v42; // ecx\n int v43; // ebp\n int *m; // rbx\n __int64 v45; // r15\n _QWORD *v46; // r13\n void *v47; // rax\n int v48; // edx\n __int64 *v49; // r8\n int v50; // ebp\n void *v51; // rax\n int v52; // r15d\n __int64 *v53; // rbp\n __m128i *v54; // rax\n __int64 v55; // rsi\n __int64 v56; // rbx\n int v57; // r9d\n int n; // r15d\n int v59; // r13d\n _QWORD *v60; // rbp\n int v61; // eax\n int v62; // r15d\n __m128i *v63; // r8\n void *v64; // rax\n const __m128i *ii; // rbp\n __m128i *v66; // rdx\n int v67; // ecx\n __m128i *v68; // r15\n int jj; // ebp\n int v70; // r13d\n _QWORD *v71; // rbx\n __m128i *v72; // rdx\n void *v73; // rax\n int *v74; // r15\n int v75; // ebx\n const __m128i *kk; // r14\n char *v77; // r13\n int v78; // r8d\n int *v79; // rax\n char *v80; // r12\n int *v81; // r13\n int mm; // r14d\n __int64 v83; // rbx\n _QWORD *v84; // rbp\n void *v85; // rax\n int v86; // ecx\n int *v87; // rax\n void *v88; // rax\n char *v89; // rax\n __m128i v90; // xmm1\n int v91; // r15d\n char *v92; // r14\n _DWORD *v93; // r13\n int v94; // ecx\n void *v95; // rax\n int v97; // [rsp+10h] [rbp-C8h]\n const __m128i *v98; // [rsp+10h] [rbp-C8h]\n int v99; // [rsp+10h] [rbp-C8h]\n int *v100; // [rsp+10h] [rbp-C8h]\n _DWORD *v101; // [rsp+18h] [rbp-C0h]\n _DWORD *v102; // [rsp+18h] [rbp-C0h]\n const __m128i *v103; // [rsp+18h] [rbp-C0h]\n _DWORD *v104; // [rsp+28h] [rbp-B0h]\n __m128i *v105; // [rsp+28h] [rbp-B0h]\n int v106; // [rsp+28h] [rbp-B0h]\n int v107; // [rsp+30h] [rbp-A8h]\n __int64 *v108; // [rsp+30h] [rbp-A8h]\n int v109; // [rsp+30h] [rbp-A8h]\n int v110; // [rsp+38h] [rbp-A0h]\n int v111; // [rsp+3Ch] [rbp-9Ch]\n int *v112; // [rsp+40h] [rbp-98h]\n const __m128i *v113; // [rsp+48h] [rbp-90h]\n const __m128i *v114; // [rsp+50h] [rbp-88h]\n __int64 *v115; // [rsp+58h] [rbp-80h]\n int v116; // [rsp+60h] [rbp-78h]\n int v117; // [rsp+64h] [rbp-74h]\n _DWORD *v118; // [rsp+68h] [rbp-70h]\n _DWORD *v119; // [rsp+70h] [rbp-68h]\n int v120; // [rsp+78h] [rbp-60h]\n int v121; // [rsp+7Ch] [rbp-5Ch]\n int v122; // [rsp+8Ch] [rbp-4Ch] BYREF\n void *ptr[9]; // [rsp+90h] [rbp-48h] BYREF\n\n ptr[1] = (void *)__readfsqword(0x28u);\n v4 = malloc(0x50uLL);\n *a3 = 0;\n ptr[0] = v4;\n v122 = 10;\n if ( a2 )\n {\n v8 = (int *)malloc(4uLL);\n v9 = *a1 - 1;\n *v8 = v9;\n if ( a2 == 1 )\n {\n while ( 1 )\n {\n v10 = *a3;\n v11 = ptr[0];\n if ( (_DWORD)v10 == v122 )\n {\n v122 = 2 * v10;\n v12 = realloc(ptr[0], 16LL * (_DWORD)v10);\n v10 = *a3;\n ptr[0] = v12;\n v11 = v12;\n }\n v11[v10] = malloc(4uLL);\n *(_DWORD *)v11[(*a3)++] = v9;\n if ( v9 > *a1 )\n break;\n *v8 = ++v9;\n }\n }\n else\n {\n v112 = v8;\n v110 = a2 - 8;\n v13 = a3;\n v14 = v9;\n v15 = v13;\n while ( 1 )\n {\n v16 = malloc(8uLL);\n *v16 = v14;\n v17 = v16;\n v18 = a1[1] - 1;\n v16[1] = v18;\n if ( a2 == 2 )\n {\n for ( i = v18; ; ++i )\n {\n v20 = *v15;\n v21 = ptr[0];\n if ( (_DWORD)v20 == v122 )\n {\n v122 = 2 * v20;\n v23 = realloc(ptr[0], 16LL * (_DWORD)v20);\n v20 = *v15;\n ptr[0] = v23;\n v21 = v23;\n }\n v21[v20] = malloc(8uLL);\n *(_DWORD *)v21[*v15] = v14;\n *(_DWORD *)(v21[(*v15)++] + 4LL) = i;\n if ( a1[1] < i )\n break;\n v17[1] = i + 1;\n }\n }\n else\n {\n v24 = a1;\n v121 = v14;\n v25 = v16;\n v26 = v15;\n for ( j = v18; ; j = v37 + 1 )\n {\n v28 = malloc(0xCuLL);\n v29 = *(_QWORD *)v25;\n *(_QWORD *)v28 = *(_QWORD *)v25;\n v30 = v24[2] - 1;\n v28[2] = v30;\n if ( a2 == 3 )\n {\n v101 = v28;\n v104 = v25;\n v31 = v30;\n v107 = j;\n v32 = v26;\n while ( 1 )\n {\n v33 = *v32;\n v34 = ptr[0];\n if ( *v32 == v122 )\n {\n v122 = 2 * v33;\n v38 = realloc(ptr[0], 16LL * v33);\n v33 = *v32;\n ptr[0] = v38;\n v34 = v38;\n }\n v34[v33] = malloc(0xCuLL);\n *(_QWORD *)v34[*v32] = v29;\n *(_DWORD *)(v34[*v32] + 8LL) = v31;\n v35 = v31 + 1;\n ++*v32;\n if ( v31 > v24[2] )\n break;\n ++v31;\n v101[2] = v35;\n }\n v26 = v32;\n v25 = v104;\n v36 = v101;\n v37 = v107;\n }\n else\n {\n v120 = j;\n v39 = v28;\n v119 = v25;\n for ( k = v30; ; k = v50 + 1 )\n {\n v41 = (int *)malloc(0x10uLL);\n *(_QWORD *)v41 = *(_QWORD *)v39;\n v41[2] = v39[2];\n v42 = v24[3] - 1;\n v41[3] = v42;\n if ( a2 == 4 )\n {\n v97 = k;\n v43 = v42;\n v102 = v39;\n for ( m = v41; ; m[3] = ++v43 )\n {\n v45 = *v26;\n v46 = ptr[0];\n if ( (_DWORD)v45 == v122 )\n {\n v122 = 2 * v45;\n v51 = realloc(ptr[0], 16LL * (_DWORD)v45);\n v45 = *v26;\n ptr[0] = v51;\n v46 = v51;\n }\n v47 = malloc(0x10uLL);\n v48 = *m;\n v46[v45] = v47;\n *(_DWORD *)v46[*v26] = v48;\n *(_DWORD *)(v46[*v26] + 4LL) = m[1];\n *(_DWORD *)(v46[*v26] + 8LL) = v97;\n *(_DWORD *)(v46[(*v26)++] + 12LL) = v43;\n if ( v43 > v24[3] )\n break;\n }\n v49 = (__int64 *)m;\n v39 = v102;\n v50 = v97;\n }\n else\n {\n v118 = v39;\n v52 = v42;\n v117 = k;\n v53 = (__int64 *)v41;\n while ( 1 )\n {\n v54 = (__m128i *)malloc(0x14uLL);\n v55 = *v53;\n v56 = v53[1];\n v54->m128i_i64[0] = *v53;\n v54->m128i_i64[1] = v56;\n v57 = v24[4] - 1;\n v54[1].m128i_i32[0] = v57;\n if ( a2 == 5 )\n {\n v108 = v53;\n v105 = v54;\n v111 = v52;\n for ( n = v57; ; ++n )\n {\n v59 = *v26;\n v60 = ptr[0];\n if ( *v26 == v122 )\n {\n v122 = 2 * v59;\n v64 = realloc(ptr[0], 16LL * v59);\n v59 = *v26;\n ptr[0] = v64;\n v60 = v64;\n }\n v60[v59] = malloc(0x14uLL);\n *(_QWORD *)v60[*v26] = v55;\n *(_QWORD *)(v60[*v26] + 8LL) = v56;\n *(_DWORD *)(v60[*v26] + 16LL) = n;\n v61 = n + 1;\n ++*v26;\n if ( n > v24[4] )\n break;\n v105[1].m128i_i32[0] = v61;\n }\n v53 = v108;\n v62 = v111;\n v63 = v105;\n }\n else\n {\n v106 = v57;\n v116 = v52;\n v115 = v53;\n for ( ii = v54; ; ii[1].m128i_i32[0] = ++v106 )\n {\n v66 = (__m128i *)malloc(0x18uLL);\n *v66 = _mm_loadu_si128(ii);\n v66[1].m128i_i32[0] = ii[1].m128i_i32[0];\n v67 = v24[5] - 1;\n v66[1].m128i_i32[1] = v67;\n if ( a2 == 6 )\n {\n v98 = ii;\n v68 = v66;\n for ( jj = v67; ; ++jj )\n {\n v70 = *v26;\n v71 = ptr[0];\n if ( *v26 == v122 )\n {\n v122 = 2 * v70;\n v73 = realloc(ptr[0], 16LL * v70);\n v70 = *v26;\n ptr[0] = v73;\n v71 = v73;\n }\n v71[v70] = malloc(0x18uLL);\n *(_DWORD *)v71[*v26] = v68->m128i_i32[0];\n *(_DWORD *)(v71[*v26] + 4LL) = v68->m128i_i32[1];\n *(_DWORD *)(v71[*v26] + 8LL) = v68->m128i_i32[2];\n *(_DWORD *)(v71[*v26] + 12LL) = v68->m128i_i32[3];\n *(_DWORD *)(v71[*v26] + 16LL) = v106;\n *(_DWORD *)(v71[(*v26)++] + 20LL) = jj;\n if ( jj > v24[5] )\n break;\n v68[1].m128i_i32[1] = jj + 1;\n }\n ii = v98;\n v72 = v68;\n }\n else\n {\n v114 = ii;\n v74 = v26;\n v75 = v67;\n for ( kk = v66; ; kk[1].m128i_i32[1] = ++v75 )\n {\n v77 = (char *)malloc(0x1CuLL);\n *(__m128i *)v77 = _mm_loadu_si128(kk);\n *((_QWORD *)v77 + 2) = kk[1].m128i_i64[0];\n v78 = v24[6] - 1;\n *((_DWORD *)v77 + 6) = v78;\n if ( a2 == 7 )\n {\n v99 = v75;\n v79 = v24;\n v80 = v77;\n v103 = kk;\n v81 = v79;\n for ( mm = v78; ; ++mm )\n {\n v83 = *v74;\n v84 = ptr[0];\n if ( (_DWORD)v83 == v122 )\n {\n v122 = 2 * v83;\n v88 = realloc(ptr[0], 16LL * (_DWORD)v83);\n v83 = *v74;\n ptr[0] = v88;\n v84 = v88;\n }\n v85 = malloc(0x1CuLL);\n v86 = *(_DWORD *)v80;\n v84[v83] = v85;\n *(_DWORD *)v84[*v74] = v86;\n *(_DWORD *)(v84[*v74] + 4LL) = *((_DWORD *)v80 + 1);\n *(_DWORD *)(v84[*v74] + 8LL) = *((_DWORD *)v80 + 2);\n *(_DWORD *)(v84[*v74] + 12LL) = *((_DWORD *)v80 + 3);\n *(_DWORD *)(v84[*v74] + 16LL) = *((_DWORD *)v80 + 4);\n *(_DWORD *)(v84[*v74] + 20LL) = v99;\n *(_DWORD *)(v84[(*v74)++] + 24LL) = mm;\n if ( mm > v81[6] )\n break;\n *((_DWORD *)v80 + 6) = mm + 1;\n }\n v87 = v81;\n kk = v103;\n v77 = v80;\n v75 = v99;\n v24 = v87;\n }\n else\n {\n v109 = v78;\n v113 = kk;\n v100 = v74;\n while ( 1 )\n {\n v89 = (char *)malloc(0x20uLL);\n v90 = _mm_loadu_si128((const __m128i *)(v77 + 12));\n *(__m128i *)v89 = _mm_loadu_si128((const __m128i *)v77);\n *(__m128i *)(v89 + 12) = v90;\n v91 = v24[7] - 1;\n v92 = v77;\n v93 = v89;\n do\n {\n v93[7] = v91;\n sub_1300(\n (_DWORD)v24 + 32,\n v110,\n (_DWORD)v93,\n 8,\n (unsigned int)ptr,\n (_DWORD)v100,\n (__int64)&v122);\n v94 = v91++;\n }\n while ( v24[7] >= v94 );\n v95 = v93;\n v77 = v92;\n free(v95);\n if ( v109 > v24[6] )\n break;\n *((_DWORD *)v92 + 6) = ++v109;\n }\n kk = v113;\n v74 = v100;\n }\n free(v77);\n if ( v75 > v24[5] )\n break;\n }\n v72 = (__m128i *)kk;\n ii = v114;\n v26 = v74;\n }\n free(v72);\n if ( v106 > v24[4] )\n break;\n }\n v63 = (__m128i *)ii;\n v62 = v116;\n v53 = v115;\n }\n free(v63);\n if ( v62 > v24[3] )\n break;\n *((_DWORD *)v53 + 3) = v62 + 1;\n v52 = v62 + 1;\n }\n v49 = v53;\n v39 = v118;\n v50 = v117;\n }\n free(v49);\n if ( v50 > v24[2] )\n break;\n v39[2] = v50 + 1;\n }\n v25 = v119;\n v37 = v120;\n v36 = v39;\n }\n free(v36);\n if ( v37 > v24[1] )\n break;\n v25[1] = v37 + 1;\n }\n v15 = v26;\n v14 = v121;\n v17 = v25;\n }\n free(v17);\n v22 = v14 + 1;\n if ( *a1 < v14 )\n break;\n ++v14;\n *v112 = v22;\n }\n v8 = v112;\n }\n free(v8);\n return ptr[0];\n }\n else\n {\n v5 = v4;\n v6 = malloc(0LL);\n ++*a3;\n *v5 = v6;\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_14A0(int *a1, int a2, int *a3) {\n void *v4;\n uint64_t *v5;\n void *v6;\n int *v8;\n int v9;\n long long v10;\n uint64_t *v11;\n void *v12;\n int *v13;\n int v14;\n int *v15;\n uint32_t *v16;\n uint32_t *v17;\n int v18;\n int i;\n long long v20;\n uint64_t *v21;\n int v22;\n void *v23;\n int *v24;\n uint32_t *v25;\n int *v26;\n int j;\n uint32_t *v28;\n long long v29;\n int v30;\n int v31;\n int *v32;\n int v33;\n uint64_t *v34;\n int v35;\n void *v36;\n int v37;\n void *v38;\n uint32_t *v39;\n int k;\n int *v41;\n int v42;\n int v43;\n int *m;\n long long v45;\n uint64_t *v46;\n void *v47;\n int v48;\n long long *v49;\n int v50;\n void *v51;\n int v52;\n long long *v53;\n __m128i *v54;\n long long v55;\n long long v56;\n int v57;\n int n;\n int v59;\n uint64_t *v60;\n int v61;\n int v62;\n __m128i *v63;\n void *v64;\n const __m128i *ii;\n __m128i *v66;\n int v67;\n __m128i *v68;\n int jj;\n int v70;\n uint64_t *v71;\n __m128i *v72;\n void *v73;\n int *v74;\n int v75;\n const __m128i *kk;\n char *v77;\n int v78;\n int *v79;\n char *v80;\n int *v81;\n int mm;\n long long v83;\n uint64_t *v84;\n void *v85;\n int v86;\n int *v87;\n void *v88;\n char *v89;\n __m128i v90;\n int v91;\n char *v92;\n uint32_t *v93;\n int v94;\n void *v95;\n int v97;\n const __m128i *v98;\n int v99;\n int *v100;\n uint32_t *v101;\n uint32_t *v102;\n const __m128i *v103;\n uint32_t *v104;\n __m128i *v105;\n int v106;\n int v107;\n long long *v108;\n int v109;\n int v110;\n int v111;\n int *v112;\n const __m128i *v113;\n const __m128i *v114;\n long long *v115;\n int v116;\n int v117;\n uint32_t *v118;\n uint32_t *v119;\n int v120;\n int v121;\n int v122;\n void *ptr[9];\n ptr[1] = (void *)__readfsqword(40u);\n v4 = malloc(80uLL);\n *a3 = 0;\n ptr[0] = v4;\n v122 = 10;\n if (a2) {\n v8 = (int *)malloc(4uLL);\n v9 = *a1 - 1;\n *v8 = v9;\n if (a2 == 1) {\n while (1) {\n v10 = *a3;\n v11 = ptr[0];\n if ((uint32_t)v10 == v122) {\n v122 = 2 * v10;\n v12 = realloc(ptr[0], 16LL * (uint32_t)v10);\n v10 = *a3;\n ptr[0] = v12;\n v11 = v12;\n }\n v11[v10] = malloc(4uLL);\n *(uint32_t *)v11[(*a3)++] = v9;\n if (v9 > *a1) break;\n *v8 = ++v9;\n }\n } else {\n v112 = v8;\n v110 = a2 - 8;\n v13 = a3;\n v14 = v9;\n v15 = v13;\n while (1) {\n v16 = malloc(8uLL);\n *v16 = v14;\n v17 = v16;\n v18 = a1[1] - 1;\n v16[1] = v18;\n if (a2 == 2) {\n for (i = v18;; ++i) {\n v20 = *v15;\n v21 = ptr[0];\n if ((uint32_t)v20 == v122) {\n v122 = 2 * v20;\n v23 = realloc(ptr[0], 16LL * (uint32_t)v20);\n v20 = *v15;\n ptr[0] = v23;\n v21 = v23;\n }\n v21[v20] = malloc(8uLL);\n *(uint32_t *)v21[*v15] = v14;\n *(uint32_t *)(v21[(*v15)++] + 4LL) = i;\n if (a1[1] < i) break;\n v17[1] = i + 1;\n }\n } else {\n v24 = a1;\n v121 = v14;\n v25 = v16;\n v26 = v15;\n for (j = v18;; j = v37 + 1) {\n v28 = malloc(12uLL);\n v29 = *(uint64_t *)v25;\n *(uint64_t *)v28 = *(uint64_t *)v25;\n v30 = v24[2] - 1;\n v28[2] = v30;\n if (a2 == 3) {\n v101 = v28;\n v104 = v25;\n v31 = v30;\n v107 = j;\n v32 = v26;\n while (1) {\n v33 = *v32;\n v34 = ptr[0];\n if (*v32 == v122) {\n v122 = 2 * v33;\n v38 = realloc(ptr[0], 16LL * v33);\n v33 = *v32;\n ptr[0] = v38;\n v34 = v38;\n }\n v34[v33] = malloc(12uLL);\n *(uint64_t *)v34[*v32] = v29;\n *(uint32_t *)(v34[*v32] + 8LL) = v31;\n v35 = v31 + 1;\n ++*v32;\n if (v31 > v24[2]) break;\n ++v31;\n v101[2] = v35;\n }\n v26 = v32;\n v25 = v104;\n v36 = v101;\n v37 = v107;\n } else {\n v120 = j;\n v39 = v28;\n v119 = v25;\n for (k = v30;; k = v50 + 1) {\n v41 = (int *)malloc(16uLL);\n *(uint64_t *)v41 = *(uint64_t *)v39;\n v41[2] = v39[2];\n v42 = v24[3] - 1;\n v41[3] = v42;\n if (a2 == 4) {\n v97 = k;\n v43 = v42;\n v102 = v39;\n for (m = v41;; m[3] = ++v43) {\n v45 = *v26;\n v46 = ptr[0];\n if ((uint32_t)v45 == v122) {\n v122 = 2 * v45;\n v51 = realloc(ptr[0], 16LL * (uint32_t)v45);\n v45 = *v26;\n ptr[0] = v51;\n v46 = v51;\n }\n v47 = malloc(16uLL);\n v48 = *m;\n v46[v45] = v47;\n *(uint32_t *)v46[*v26] = v48;\n *(uint32_t *)(v46[*v26] + 4LL) = m[1];\n *(uint32_t *)(v46[*v26] + 8LL) = v97;\n *(uint32_t *)(v46[(*v26)++] + 12LL) = v43;\n if (v43 > v24[3]) break;\n }\n v49 = (long long *)m;\n v39 = v102;\n v50 = v97;\n } else {\n v118 = v39;\n v52 = v42;\n v117 = k;\n v53 = (long long *)v41;\n while (1) {\n v54 = (__m128i *)malloc(20uLL);\n v55 = *v53;\n v56 = v53[1];\n v54->m128i_i64[0] = *v53;\n v54->m128i_i64[1] = v56;\n v57 = v24[4] - 1;\n v54[1].m128i_i32[0] = v57;\n if (a2 == 5) {\n v108 = v53;\n v105 = v54;\n v111 = v52;\n for (n = v57;; ++n) {\n v59 = *v26;\n v60 = ptr[0];\n if (*v26 == v122) {\n v122 = 2 * v59;\n v64 = realloc(ptr[0], 16LL * v59);\n v59 = *v26;\n ptr[0] = v64;\n v60 = v64;\n }\n v60[v59] = malloc(20uLL);\n *(uint64_t *)v60[*v26] = v55;\n *(uint64_t *)(v60[*v26] + 8LL) = v56;\n *(uint32_t *)(v60[*v26] + 16LL) = n;\n v61 = n + 1;\n ++*v26;\n if (n > v24[4]) break;\n v105[1].m128i_i32[0] = v61;\n }\n v53 = v108;\n v62 = v111;\n v63 = v105;\n } else {\n v106 = v57;\n v116 = v52;\n v115 = v53;\n for (ii = v54;; ii[1].m128i_i32[0] = ++v106) {\n v66 = (__m128i *)malloc(24uLL);\n *v66 = _mm_loadu_si128(ii);\n v66[1].m128i_i32[0] = ii[1].m128i_i32[0];\n v67 = v24[5] - 1;\n v66[1].m128i_i32[1] = v67;\n if (a2 == 6) {\n v98 = ii;\n v68 = v66;\n for (jj = v67;; ++jj) {\n v70 = *v26;\n v71 = ptr[0];\n if (*v26 == v122) {\n v122 = 2 * v70;\n v73 = realloc(ptr[0], 16LL * v70);\n v70 = *v26;\n ptr[0] = v73;\n v71 = v73;\n }\n v71[v70] = malloc(24uLL);\n *(uint32_t *)v71[*v26] = v68->m128i_i32[0];\n *(uint32_t *)(v71[*v26] + 4LL) = v68->m128i_i32[1];\n *(uint32_t *)(v71[*v26] + 8LL) = v68->m128i_i32[2];\n *(uint32_t *)(v71[*v26] + 12LL) = v68->m128i_i32[3];\n *(uint32_t *)(v71[*v26] + 16LL) = v106;\n *(uint32_t *)(v71[(*v26)++] + 20LL) = jj;\n if (jj > v24[5]) break;\n v68[1].m128i_i32[1] = jj + 1;\n }\n ii = v98;\n v72 = v68;\n } else {\n v114 = ii;\n v74 = v26;\n v75 = v67;\n for (kk = v66;; kk[1].m128i_i32[1] = ++v75) {\n v77 = (char *)malloc(28uLL);\n *(__m128i *)v77 = _mm_loadu_si128(kk);\n *((uint64_t *)v77 + 2) = kk[1].m128i_i64[0];\n v78 = v24[6] - 1;\n *((uint32_t *)v77 + 6) = v78;\n if (a2 == 7) {\n v99 = v75;\n v79 = v24;\n v80 = v77;\n v103 = kk;\n v81 = v79;\n for (mm = v78;; ++mm) {\n v83 = *v74;\n v84 = ptr[0];\n if ((uint32_t)v83 == v122) {\n v122 = 2 * v83;\n v88 = realloc(ptr[0], 16LL * (uint32_t)v83);\n v83 = *v74;\n ptr[0] = v88;\n v84 = v88;\n }\n v85 = malloc(28uLL);\n v86 = *(uint32_t *)v80;\n v84[v83] = v85;\n *(uint32_t *)v84[*v74] = v86;\n *(uint32_t *)(v84[*v74] + 4LL) =\n *((uint32_t *)v80 + 1);\n *(uint32_t *)(v84[*v74] + 8LL) =\n *((uint32_t *)v80 + 2);\n *(uint32_t *)(v84[*v74] + 12LL) =\n *((uint32_t *)v80 + 3);\n *(uint32_t *)(v84[*v74] + 16LL) =\n *((uint32_t *)v80 + 4);\n *(uint32_t *)(v84[*v74] + 20LL) = v99;\n *(uint32_t *)(v84[(*v74)++] + 24LL) = mm;\n if (mm > v81[6]) break;\n *((uint32_t *)v80 + 6) = mm + 1;\n }\n v87 = v81;\n kk = v103;\n v77 = v80;\n v75 = v99;\n v24 = v87;\n } else {\n v109 = v78;\n v113 = kk;\n v100 = v74;\n while (1) {\n v89 = (char *)malloc(32uLL);\n v90 = _mm_loadu_si128(\n (const __m128i *)(v77 + 12));\n *(__m128i *)v89 =\n _mm_loadu_si128((const __m128i *)v77);\n *(__m128i *)(v89 + 12) = v90;\n v91 = v24[7] - 1;\n v92 = v77;\n v93 = v89;\n do {\n v93[7] = v91;\n sub_1300((uint32_t)v24 + 32, v110,\n (uint32_t)v93, 8, (unsigned int)ptr,\n (uint32_t)v100, (long long)&v122);\n v94 = v91++;\n } while (v24[7] >= v94);\n v95 = v93;\n v77 = v92;\n free(v95);\n if (v109 > v24[6]) break;\n *((uint32_t *)v92 + 6) = ++v109;\n }\n kk = v113;\n v74 = v100;\n }\n free(v77);\n if (v75 > v24[5]) break;\n }\n v72 = (__m128i *)kk;\n ii = v114;\n v26 = v74;\n }\n free(v72);\n if (v106 > v24[4]) break;\n }\n v63 = (__m128i *)ii;\n v62 = v116;\n v53 = v115;\n }\n free(v63);\n if (v62 > v24[3]) break;\n *((uint32_t *)v53 + 3) = v62 + 1;\n v52 = v62 + 1;\n }\n v49 = v53;\n v39 = v118;\n v50 = v117;\n }\n free(v49);\n if (v50 > v24[2]) break;\n v39[2] = v50 + 1;\n }\n v25 = v119;\n v37 = v120;\n v36 = v39;\n }\n free(v36);\n if (v37 > v24[1]) break;\n v25[1] = v37 + 1;\n }\n v15 = v26;\n v14 = v121;\n v17 = v25;\n }\n free(v17);\n v22 = v14 + 1;\n if (*a1 < v14) break;\n ++v14;\n *v112 = v22;\n }\n v8 = v112;\n }\n free(v8);\n return ptr[0];\n } else {\n v5 = v4;\n v6 = malloc(0LL);\n ++*a3;\n *v5 = v6;\n }\n return v5;\n}", + "ida_pseudo_norm": "uint64_t *func0(int *a1, int a2, int *a3) {\n void *v4;\n uint64_t *v5;\n void *v6;\n int *v8;\n int v9;\n long long v10;\n uint64_t *v11;\n void *v12;\n int *v13;\n int v14;\n int *v15;\n uint32_t *v16;\n uint32_t *v17;\n int v18;\n int i;\n long long v20;\n uint64_t *v21;\n int v22;\n void *v23;\n int *v24;\n uint32_t *v25;\n int *v26;\n int j;\n uint32_t *v28;\n long long v29;\n int v30;\n int v31;\n int *v32;\n int v33;\n uint64_t *v34;\n int v35;\n void *v36;\n int v37;\n void *v38;\n uint32_t *v39;\n int k;\n int *v41;\n int v42;\n int v43;\n int *m;\n long long v45;\n uint64_t *v46;\n void *v47;\n int v48;\n long long *v49;\n int v50;\n void *v51;\n int v52;\n long long *v53;\n __m128i *v54;\n long long v55;\n long long v56;\n int v57;\n int n;\n int v59;\n uint64_t *v60;\n int v61;\n int v62;\n __m128i *v63;\n void *v64;\n const __m128i *ii;\n __m128i *v66;\n int v67;\n __m128i *v68;\n int jj;\n int v70;\n uint64_t *v71;\n __m128i *v72;\n void *v73;\n int *v74;\n int v75;\n const __m128i *kk;\n char *v77;\n int v78;\n int *v79;\n char *v80;\n int *v81;\n int mm;\n long long v83;\n uint64_t *v84;\n void *v85;\n int v86;\n int *v87;\n void *v88;\n char *v89;\n __m128i v90;\n int v91;\n char *v92;\n uint32_t *v93;\n int v94;\n void *v95;\n int v97;\n const __m128i *v98;\n int v99;\n int *v100;\n uint32_t *v101;\n uint32_t *v102;\n const __m128i *v103;\n uint32_t *v104;\n __m128i *v105;\n int v106;\n int v107;\n long long *v108;\n int v109;\n int v110;\n int v111;\n int *v112;\n const __m128i *v113;\n const __m128i *v114;\n long long *v115;\n int v116;\n int v117;\n uint32_t *v118;\n uint32_t *v119;\n int v120;\n int v121;\n int v122;\n void *ptr[9];\n ptr[1] = (void *)__readfsqword(40u);\n v4 = malloc(80uLL);\n *a3 = 0;\n ptr[0] = v4;\n v122 = 10;\n if (a2) {\n v8 = (int *)malloc(4uLL);\n v9 = *a1 - 1;\n *v8 = v9;\n if (a2 == 1) {\n while (1) {\n v10 = *a3;\n v11 = ptr[0];\n if ((uint32_t)v10 == v122) {\n v122 = 2 * v10;\n v12 = realloc(ptr[0], 16LL * (uint32_t)v10);\n v10 = *a3;\n ptr[0] = v12;\n v11 = v12;\n }\n v11[v10] = malloc(4uLL);\n *(uint32_t *)v11[(*a3)++] = v9;\n if (v9 > *a1) break;\n *v8 = ++v9;\n }\n } else {\n v112 = v8;\n v110 = a2 - 8;\n v13 = a3;\n v14 = v9;\n v15 = v13;\n while (1) {\n v16 = malloc(8uLL);\n *v16 = v14;\n v17 = v16;\n v18 = a1[1] - 1;\n v16[1] = v18;\n if (a2 == 2) {\n for (i = v18;; ++i) {\n v20 = *v15;\n v21 = ptr[0];\n if ((uint32_t)v20 == v122) {\n v122 = 2 * v20;\n v23 = realloc(ptr[0], 16LL * (uint32_t)v20);\n v20 = *v15;\n ptr[0] = v23;\n v21 = v23;\n }\n v21[v20] = malloc(8uLL);\n *(uint32_t *)v21[*v15] = v14;\n *(uint32_t *)(v21[(*v15)++] + 4LL) = i;\n if (a1[1] < i) break;\n v17[1] = i + 1;\n }\n } else {\n v24 = a1;\n v121 = v14;\n v25 = v16;\n v26 = v15;\n for (j = v18;; j = v37 + 1) {\n v28 = malloc(12uLL);\n v29 = *(uint64_t *)v25;\n *(uint64_t *)v28 = *(uint64_t *)v25;\n v30 = v24[2] - 1;\n v28[2] = v30;\n if (a2 == 3) {\n v101 = v28;\n v104 = v25;\n v31 = v30;\n v107 = j;\n v32 = v26;\n while (1) {\n v33 = *v32;\n v34 = ptr[0];\n if (*v32 == v122) {\n v122 = 2 * v33;\n v38 = realloc(ptr[0], 16LL * v33);\n v33 = *v32;\n ptr[0] = v38;\n v34 = v38;\n }\n v34[v33] = malloc(12uLL);\n *(uint64_t *)v34[*v32] = v29;\n *(uint32_t *)(v34[*v32] + 8LL) = v31;\n v35 = v31 + 1;\n ++*v32;\n if (v31 > v24[2]) break;\n ++v31;\n v101[2] = v35;\n }\n v26 = v32;\n v25 = v104;\n v36 = v101;\n v37 = v107;\n } else {\n v120 = j;\n v39 = v28;\n v119 = v25;\n for (k = v30;; k = v50 + 1) {\n v41 = (int *)malloc(16uLL);\n *(uint64_t *)v41 = *(uint64_t *)v39;\n v41[2] = v39[2];\n v42 = v24[3] - 1;\n v41[3] = v42;\n if (a2 == 4) {\n v97 = k;\n v43 = v42;\n v102 = v39;\n for (m = v41;; m[3] = ++v43) {\n v45 = *v26;\n v46 = ptr[0];\n if ((uint32_t)v45 == v122) {\n v122 = 2 * v45;\n v51 = realloc(ptr[0], 16LL * (uint32_t)v45);\n v45 = *v26;\n ptr[0] = v51;\n v46 = v51;\n }\n v47 = malloc(16uLL);\n v48 = *m;\n v46[v45] = v47;\n *(uint32_t *)v46[*v26] = v48;\n *(uint32_t *)(v46[*v26] + 4LL) = m[1];\n *(uint32_t *)(v46[*v26] + 8LL) = v97;\n *(uint32_t *)(v46[(*v26)++] + 12LL) = v43;\n if (v43 > v24[3]) break;\n }\n v49 = (long long *)m;\n v39 = v102;\n v50 = v97;\n } else {\n v118 = v39;\n v52 = v42;\n v117 = k;\n v53 = (long long *)v41;\n while (1) {\n v54 = (__m128i *)malloc(20uLL);\n v55 = *v53;\n v56 = v53[1];\n v54->m128i_i64[0] = *v53;\n v54->m128i_i64[1] = v56;\n v57 = v24[4] - 1;\n v54[1].m128i_i32[0] = v57;\n if (a2 == 5) {\n v108 = v53;\n v105 = v54;\n v111 = v52;\n for (n = v57;; ++n) {\n v59 = *v26;\n v60 = ptr[0];\n if (*v26 == v122) {\n v122 = 2 * v59;\n v64 = realloc(ptr[0], 16LL * v59);\n v59 = *v26;\n ptr[0] = v64;\n v60 = v64;\n }\n v60[v59] = malloc(20uLL);\n *(uint64_t *)v60[*v26] = v55;\n *(uint64_t *)(v60[*v26] + 8LL) = v56;\n *(uint32_t *)(v60[*v26] + 16LL) = n;\n v61 = n + 1;\n ++*v26;\n if (n > v24[4]) break;\n v105[1].m128i_i32[0] = v61;\n }\n v53 = v108;\n v62 = v111;\n v63 = v105;\n } else {\n v106 = v57;\n v116 = v52;\n v115 = v53;\n for (ii = v54;; ii[1].m128i_i32[0] = ++v106) {\n v66 = (__m128i *)malloc(24uLL);\n *v66 = _mm_loadu_si128(ii);\n v66[1].m128i_i32[0] = ii[1].m128i_i32[0];\n v67 = v24[5] - 1;\n v66[1].m128i_i32[1] = v67;\n if (a2 == 6) {\n v98 = ii;\n v68 = v66;\n for (jj = v67;; ++jj) {\n v70 = *v26;\n v71 = ptr[0];\n if (*v26 == v122) {\n v122 = 2 * v70;\n v73 = realloc(ptr[0], 16LL * v70);\n v70 = *v26;\n ptr[0] = v73;\n v71 = v73;\n }\n v71[v70] = malloc(24uLL);\n *(uint32_t *)v71[*v26] = v68->m128i_i32[0];\n *(uint32_t *)(v71[*v26] + 4LL) = v68->m128i_i32[1];\n *(uint32_t *)(v71[*v26] + 8LL) = v68->m128i_i32[2];\n *(uint32_t *)(v71[*v26] + 12LL) = v68->m128i_i32[3];\n *(uint32_t *)(v71[*v26] + 16LL) = v106;\n *(uint32_t *)(v71[(*v26)++] + 20LL) = jj;\n if (jj > v24[5]) break;\n v68[1].m128i_i32[1] = jj + 1;\n }\n ii = v98;\n v72 = v68;\n } else {\n v114 = ii;\n v74 = v26;\n v75 = v67;\n for (kk = v66;; kk[1].m128i_i32[1] = ++v75) {\n v77 = (char *)malloc(28uLL);\n *(__m128i *)v77 = _mm_loadu_si128(kk);\n *((uint64_t *)v77 + 2) = kk[1].m128i_i64[0];\n v78 = v24[6] - 1;\n *((uint32_t *)v77 + 6) = v78;\n if (a2 == 7) {\n v99 = v75;\n v79 = v24;\n v80 = v77;\n v103 = kk;\n v81 = v79;\n for (mm = v78;; ++mm) {\n v83 = *v74;\n v84 = ptr[0];\n if ((uint32_t)v83 == v122) {\n v122 = 2 * v83;\n v88 = realloc(ptr[0], 16LL * (uint32_t)v83);\n v83 = *v74;\n ptr[0] = v88;\n v84 = v88;\n }\n v85 = malloc(28uLL);\n v86 = *(uint32_t *)v80;\n v84[v83] = v85;\n *(uint32_t *)v84[*v74] = v86;\n *(uint32_t *)(v84[*v74] + 4LL) =\n *((uint32_t *)v80 + 1);\n *(uint32_t *)(v84[*v74] + 8LL) =\n *((uint32_t *)v80 + 2);\n *(uint32_t *)(v84[*v74] + 12LL) =\n *((uint32_t *)v80 + 3);\n *(uint32_t *)(v84[*v74] + 16LL) =\n *((uint32_t *)v80 + 4);\n *(uint32_t *)(v84[*v74] + 20LL) = v99;\n *(uint32_t *)(v84[(*v74)++] + 24LL) = mm;\n if (mm > v81[6]) break;\n *((uint32_t *)v80 + 6) = mm + 1;\n }\n v87 = v81;\n kk = v103;\n v77 = v80;\n v75 = v99;\n v24 = v87;\n } else {\n v109 = v78;\n v113 = kk;\n v100 = v74;\n while (1) {\n v89 = (char *)malloc(32uLL);\n v90 = _mm_loadu_si128(\n (const __m128i *)(v77 + 12));\n *(__m128i *)v89 =\n _mm_loadu_si128((const __m128i *)v77);\n *(__m128i *)(v89 + 12) = v90;\n v91 = v24[7] - 1;\n v92 = v77;\n v93 = v89;\n do {\n v93[7] = v91;\n adjac((uint32_t)v24 + 32, v110, (uint32_t)v93,\n 8, (unsigned int)ptr, (uint32_t)v100,\n (long long)&v122);\n v94 = v91++;\n } while (v24[7] >= v94);\n v95 = v93;\n v77 = v92;\n free(v95);\n if (v109 > v24[6]) break;\n *((uint32_t *)v92 + 6) = ++v109;\n }\n kk = v113;\n v74 = v100;\n }\n free(v77);\n if (v75 > v24[5]) break;\n }\n v72 = (__m128i *)kk;\n ii = v114;\n v26 = v74;\n }\n free(v72);\n if (v106 > v24[4]) break;\n }\n v63 = (__m128i *)ii;\n v62 = v116;\n v53 = v115;\n }\n free(v63);\n if (v62 > v24[3]) break;\n *((uint32_t *)v53 + 3) = v62 + 1;\n v52 = v62 + 1;\n }\n v49 = v53;\n v39 = v118;\n v50 = v117;\n }\n free(v49);\n if (v50 > v24[2]) break;\n v39[2] = v50 + 1;\n }\n v25 = v119;\n v37 = v120;\n v36 = v39;\n }\n free(v36);\n if (v37 > v24[1]) break;\n v25[1] = v37 + 1;\n }\n v15 = v26;\n v14 = v121;\n v17 = v25;\n }\n free(v17);\n v22 = v14 + 1;\n if (*a1 < v14) break;\n ++v14;\n *v112 = v22;\n }\n v8 = v112;\n }\n free(v8);\n return ptr[0];\n } else {\n v5 = v4;\n v6 = malloc(0LL);\n ++*a3;\n *v5 = v6;\n }\n return v5;\n}" + }, + { + "index": 631, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(char* text) {\n for (int i = 0; text[i] != '\\0'; ++i) {\n if (text[i] == ' ') {\n text[i] = '_';\n }\n }\n}", + "test": "int main() {\n\n char text1[] = \"Jumanji The Jungle\";\n\n char text2[] = \"The Avengers\";\n\n char text3[] = \"Fast and Furious\";\n\n\n\n func0(text1);\n\n func0(text2);\n\n func0(text3);\n\n\n\n assert(strcmp(text1, \"Jumanji_The_Jungle\") == 0);\n\n assert(strcmp(text2, \"The_Avengers\") == 0);\n\n assert(strcmp(text3, \"Fast_and_Furious\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11c6 \nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x20,%al\njne 11c2 \nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovb $0x5f,(%rax)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 119e \npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_4], 0\njmp short loc_11C6\nloc_119E:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njnz short loc_11C2\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov byte ptr [rax], 5Fh ; '_'\nloc_11C2:\nadd [rbp+var_4], 1\nloc_11C6:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_119E\nnop\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1)\n{\n __int64 result; // rax\n int i; // [rsp+14h] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = *(unsigned __int8 *)(i + a1);\n if ( !(_BYTE)result )\n break;\n if ( *(_BYTE *)(i + a1) == 32 )\n *(_BYTE *)(i + a1) = 95;\n }\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_4], 0\njmp short loc_11C6\nloc_119E:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njnz short loc_11C2\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov byte ptr [rax], 5Fh ; '_'\nloc_11C2:\nadd [rbp+var_4], 1\nloc_11C6:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_119E\nnop\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1)\n{\n __int64 result; // rax\n int i; // [rsp+14h] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = *(unsigned __int8 *)(i + a1);\n if ( !(_BYTE)result )\n break;\n if ( *(_BYTE *)(i + a1) == 32 )\n *(_BYTE *)(i + a1) = 95;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1) {\n long long result;\n int i;\n for (i = 0;; ++i) {\n result = *(unsigned char *)(i + a1);\n if (!(uint8_t)result) break;\n if (*(uint8_t *)(i + a1) == 32) *(uint8_t *)(i + a1) = 95;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1) {\n long long result;\n int i;\n for (i = 0;; ++i) {\n result = *(unsigned char *)(i + a1);\n if (!(uint8_t)result) break;\n if (*(uint8_t *)(i + a1) == 32) *(uint8_t *)(i + a1) = 95;\n }\n return result;\n}" + }, + { + "index": 631, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(char* text) {\n for (int i = 0; text[i] != '\\0'; ++i) {\n if (text[i] == ' ') {\n text[i] = '_';\n }\n }\n}", + "test": "int main() {\n\n char text1[] = \"Jumanji The Jungle\";\n\n char text2[] = \"The Avengers\";\n\n char text3[] = \"Fast and Furious\";\n\n\n\n func0(text1);\n\n func0(text2);\n\n func0(text3);\n\n\n\n assert(strcmp(text1, \"Jumanji_The_Jungle\") == 0);\n\n assert(strcmp(text2, \"The_Avengers\") == 0);\n\n assert(strcmp(text3, \"Fast_and_Furious\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmovzbl (%rdi),%eax\ntest %al,%al\njne 1180 \nretq\nadd $0x1,%rdi\nmovzbl (%rdi),%eax\ntest %al,%al\nje 1174 \ncmp $0x20,%al\njne 1175 \nmovb $0x5f,(%rdi)\njmp 1175 \n", + "ida_asm": "func0:\nendbr64\nmovzx eax, byte ptr [rdi]\ntest al, al\njnz short loc_11A0\nlocret_1194:\nretn\nloc_1195:\nadd rdi, 1\nmovzx eax, byte ptr [rdi]\ntest al, al\njz short locret_1194\nloc_11A0:\ncmp al, 20h ; ' '\njnz short loc_1195\nmov byte ptr [rdi], 5Fh ; '_'\njmp short loc_1195", + "ida_pseudo": "__int64 __fastcall func0(_BYTE *a1)\n{\n __int64 result; // rax\n\n for ( result = (unsigned __int8)*a1; (_BYTE)result; result = (unsigned __int8)*a1 )\n {\n if ( (_BYTE)result == 32 )\n *a1 = 95;\n ++a1;\n }\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\nmovzx eax, byte ptr [rdi]\ntest al, al\njnz short loc_11A0\nlocret_1194:\nretn\nloc_1195:\nadd rdi, 1\nmovzx eax, byte ptr [rdi]\ntest al, al\njz short locret_1194\nloc_11A0:\ncmp al, 20h ; ' '\njnz short loc_1195\nmov byte ptr [rdi], 5Fh ; '_'\njmp short loc_1195", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(_BYTE *a1)\n{\n __int64 result; // rax\n\n for ( result = (unsigned __int8)*a1; (_BYTE)result; result = (unsigned __int8)*a1 )\n {\n if ( (_BYTE)result == 32 )\n *a1 = 95;\n ++a1;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(uint8_t *a1) {\n long long result;\n for (result = (unsigned char)*a1; (uint8_t)result;\n result = (unsigned char)*a1) {\n if ((uint8_t)result == 32) *a1 = 95;\n ++a1;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(uint8_t *a1) {\n long long result;\n for (result = (unsigned char)*a1; (uint8_t)result;\n result = (unsigned char)*a1) {\n if ((uint8_t)result == 32) *a1 = 95;\n ++a1;\n }\n return result;\n}" + }, + { + "index": 632, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int num_list[], int size, int result[]) {\n int zero_count = 0;\n int j = 0;\n for (int i = 0; i < size; i++) {\n if (num_list[i] == 0) {\n zero_count++;\n } else {\n result[j++] = num_list[i];\n }\n }\n for (int i = 0; i < zero_count; i++) {\n result[j++] = 0;\n }\n}", + "test": "int main() {\n\n int result[6];\n\n int list1[6] = {1, 0, 2, 0, 3, 4};\n\n func0(list1, 6, result);\n\n int expected1[6] = {1, 2, 3, 4, 0, 0};\n\n for (int i = 0; i < 6; i++) {\n\n assert(result[i] == expected1[i]);\n\n }\n\n\n\n int result2[9];\n\n int list2[9] = {2, 3, 2, 0, 0, 4, 0, 5, 0};\n\n func0(list2, 9, result2);\n\n int expected2[9] = {2, 3, 2, 4, 5, 0, 0, 0, 0};\n\n for (int i = 0; i < 9; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n\n\n int result3[5];\n\n int list3[5] = {0, 1, 0, 1, 1};\n\n func0(list3, 5, result3);\n\n int expected3[5] = {1, 1, 1, 0, 0};\n\n for (int i = 0; i < 5; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n\n\n printf(\"All tests passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmovl $0x0,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 120a \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ntest %eax,%eax\njne 11d3 \naddl $0x1,-0x10(%rbp)\njmp 1206 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0xc(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0xc(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11b3 \nmovl $0x0,-0x4(%rbp)\njmp 123f \nmov -0xc(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0xc(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovl $0x0,(%rax)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x10(%rbp),%eax\njl 121b \npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_120A\nloc_11B3:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njnz short loc_11D3\nadd [rbp+var_10], 1\njmp short loc_1206\nloc_11D3:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_1206:\nadd [rbp+var_8], 1\nloc_120A:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_11B3\nmov [rbp+var_4], 0\njmp short loc_123F\nloc_121B:\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov dword ptr [rax], 0\nadd [rbp+var_4], 1\nloc_123F:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_10]\njl short loc_121B\nnop\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3)\n{\n int v3; // eax\n int v4; // eax\n __int64 result; // rax\n int v6; // [rsp+18h] [rbp-10h]\n int v7; // [rsp+1Ch] [rbp-Ch]\n int i; // [rsp+20h] [rbp-8h]\n unsigned int j; // [rsp+24h] [rbp-4h]\n\n v6 = 0;\n v7 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) )\n {\n v3 = v7++;\n *(_DWORD *)(a3 + 4LL * v3) = *(_DWORD *)(4LL * i + a1);\n }\n else\n {\n ++v6;\n }\n }\n for ( j = 0; ; ++j )\n {\n result = j;\n if ( (int)j >= v6 )\n break;\n v4 = v7++;\n *(_DWORD *)(4LL * v4 + a3) = 0;\n }\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_120A\nloc_11B3:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njnz short loc_11D3\nadd [rbp+var_10], 1\njmp short loc_1206\nloc_11D3:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_1206:\nadd [rbp+var_8], 1\nloc_120A:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_11B3\nmov [rbp+var_4], 0\njmp short loc_123F\nloc_121B:\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov dword ptr [rax], 0\nadd [rbp+var_4], 1\nloc_123F:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_10]\njl short loc_121B\nnop\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2, __int64 a3)\n{\n int v3; // eax\n int v4; // eax\n __int64 result; // rax\n int v6; // [rsp+18h] [rbp-10h]\n int v7; // [rsp+1Ch] [rbp-Ch]\n int i; // [rsp+20h] [rbp-8h]\n unsigned int j; // [rsp+24h] [rbp-4h]\n\n v6 = 0;\n v7 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) )\n {\n v3 = v7++;\n *(_DWORD *)(a3 + 4LL * v3) = *(_DWORD *)(4LL * i + a1);\n }\n else\n {\n ++v6;\n }\n }\n for ( j = 0; ; ++j )\n {\n result = j;\n if ( (int)j >= v6 )\n break;\n v4 = v7++;\n *(_DWORD *)(4LL * v4 + a3) = 0;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2, long long a3) {\n int v3;\n int v4;\n long long result;\n int v6;\n int v7;\n int i;\n unsigned int j;\n v6 = 0;\n v7 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(uint32_t *)(4LL * i + a1)) {\n v3 = v7++;\n *(uint32_t *)(a3 + 4LL * v3) = *(uint32_t *)(4LL * i + a1);\n } else {\n ++v6;\n }\n }\n for (j = 0;; ++j) {\n result = j;\n if ((int)j >= v6) break;\n v4 = v7++;\n *(uint32_t *)(4LL * v4 + a3) = 0;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3) {\n int v3;\n int v4;\n long long result;\n int v6;\n int v7;\n int i;\n unsigned int j;\n v6 = 0;\n v7 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(uint32_t *)(4LL * i + a1)) {\n v3 = v7++;\n *(uint32_t *)(a3 + 4LL * v3) = *(uint32_t *)(4LL * i + a1);\n } else {\n ++v6;\n }\n }\n for (j = 0;; ++j) {\n result = j;\n if ((int)j >= v6) break;\n v4 = v7++;\n *(uint32_t *)(4LL * v4 + a3) = 0;\n }\n return result;\n}" + }, + { + "index": 632, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int num_list[], int size, int result[]) {\n int zero_count = 0;\n int j = 0;\n for (int i = 0; i < size; i++) {\n if (num_list[i] == 0) {\n zero_count++;\n } else {\n result[j++] = num_list[i];\n }\n }\n for (int i = 0; i < zero_count; i++) {\n result[j++] = 0;\n }\n}", + "test": "int main() {\n\n int result[6];\n\n int list1[6] = {1, 0, 2, 0, 3, 4};\n\n func0(list1, 6, result);\n\n int expected1[6] = {1, 2, 3, 4, 0, 0};\n\n for (int i = 0; i < 6; i++) {\n\n assert(result[i] == expected1[i]);\n\n }\n\n\n\n int result2[9];\n\n int list2[9] = {2, 3, 2, 0, 0, 4, 0, 5, 0};\n\n func0(list2, 9, result2);\n\n int expected2[9] = {2, 3, 2, 4, 5, 0, 0, 0, 0};\n\n for (int i = 0; i < 9; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n\n\n int result3[5];\n\n int list3[5] = {0, 1, 0, 1, 1};\n\n func0(list3, 5, result3);\n\n int expected3[5] = {1, 1, 1, 0, 0};\n\n for (int i = 0; i < 5; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n\n\n printf(\"All tests passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11eb \nmov %rdi,%rax\nlea -0x1(%rsi),%ecx\nlea 0x4(%rdi,%rcx,4),%r8\nmov $0x0,%esi\nmov $0x0,%edi\njmp 11bb \nmovslq %esi,%r9\nmov %ecx,(%rdx,%r9,4)\nlea 0x1(%rsi),%esi\nadd $0x4,%rax\ncmp %r8,%rax\nje 11c6 \nmov (%rax),%ecx\ntest %ecx,%ecx\njne 11a8 \nadd $0x1,%edi\njmp 11b2 \ntest %edi,%edi\njle 11eb \nmovslq %esi,%rsi\nlea (%rdx,%rsi,4),%rax\nlea -0x1(%rdi),%ecx\nadd %rcx,%rsi\nlea 0x4(%rdx,%rsi,4),%rdx\nmovl $0x0,(%rax)\nadd $0x4,%rax\ncmp %rdx,%rax\njne 11dc \nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short locret_11E9\nmov rax, rdi\nmovsxd rsi, esi\nlea r8, [rdi+rsi*4]\nmov esi, 0\nmov edi, 0\njmp short loc_11BA\nloc_11A7:\nmovsxd r9, esi\nmov [rdx+r9*4], ecx\nlea esi, [rsi+1]\nloc_11B1:\nadd rax, 4\ncmp rax, r8\njz short loc_11C5\nloc_11BA:\nmov ecx, [rax]\ntest ecx, ecx\njnz short loc_11A7\nadd edi, 1\njmp short loc_11B1\nloc_11C5:\ntest edi, edi\njle short locret_11E9\nmovsxd rsi, esi\nlea rax, [rdx+rsi*4]\nmovsxd rdi, edi\nadd rdi, rsi\nlea rdx, [rdx+rdi*4]\nloc_11DA:\nmov dword ptr [rax], 0\nadd rax, 4\ncmp rdx, rax\njnz short loc_11DA\nlocret_11E9:\nretn", + "ida_pseudo": "void __fastcall func0(_DWORD *a1, int a2, __int64 a3)\n{\n _DWORD *v3; // rax\n _DWORD *v4; // r8\n int v5; // esi\n int v6; // edi\n _DWORD *v7; // rax\n _DWORD *v8; // rdx\n\n if ( a2 > 0 )\n {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n v6 = 0;\n do\n {\n if ( *v3 )\n *(_DWORD *)(a3 + 4LL * v5++) = *v3;\n else\n ++v6;\n ++v3;\n }\n while ( v3 != v4 );\n if ( v6 > 0 )\n {\n v7 = (_DWORD *)(a3 + 4LL * v5);\n v8 = (_DWORD *)(a3 + 4 * (v5 + (__int64)v6));\n do\n *v7++ = 0;\n while ( v8 != v7 );\n }\n }\n}", + "ida_strip_asm": "sub_1189:\nendbr64\ntest esi, esi\njle short locret_11E9\nmov rax, rdi\nmovsxd rsi, esi\nlea r8, [rdi+rsi*4]\nmov esi, 0\nmov edi, 0\njmp short loc_11BA\nloc_11A7:\nmovsxd r9, esi\nmov [rdx+r9*4], ecx\nlea esi, [rsi+1]\nloc_11B1:\nadd rax, 4\ncmp rax, r8\njz short loc_11C5\nloc_11BA:\nmov ecx, [rax]\ntest ecx, ecx\njnz short loc_11A7\nadd edi, 1\njmp short loc_11B1\nloc_11C5:\ntest edi, edi\njle short locret_11E9\nmovsxd rsi, esi\nlea rax, [rdx+rsi*4]\nmovsxd rdi, edi\nadd rdi, rsi\nlea rdx, [rdx+rdi*4]\nloc_11DA:\nmov dword ptr [rax], 0\nadd rax, 4\ncmp rdx, rax\njnz short loc_11DA\nlocret_11E9:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1189(_DWORD *a1, int a2, __int64 a3)\n{\n _DWORD *v3; // rax\n _DWORD *v4; // r8\n int v5; // esi\n int v6; // edi\n _DWORD *v7; // rax\n _DWORD *v8; // rdx\n\n if ( a2 > 0 )\n {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n v6 = 0;\n do\n {\n if ( *v3 )\n *(_DWORD *)(a3 + 4LL * v5++) = *v3;\n else\n ++v6;\n ++v3;\n }\n while ( v3 != v4 );\n if ( v6 > 0 )\n {\n v7 = (_DWORD *)(a3 + 4LL * v5);\n v8 = (_DWORD *)(a3 + 4 * (v5 + (__int64)v6));\n do\n *v7++ = 0;\n while ( v8 != v7 );\n }\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1189(uint32_t *a1, int a2, long long a3) {\n uint32_t *v3;\n uint32_t *v4;\n int v5;\n int v6;\n uint32_t *v7;\n uint32_t *v8;\n if (a2 > 0) {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n v6 = 0;\n do {\n if (*v3)\n *(uint32_t *)(a3 + 4LL * v5++) = *v3;\n else\n ++v6;\n ++v3;\n } while (v3 != v4);\n if (v6 > 0) {\n v7 = (uint32_t *)(a3 + 4LL * v5);\n v8 = (uint32_t *)(a3 + 4 * (v5 + (long long)v6));\n do\n *v7++ = 0;\n while (v8 != v7);\n }\n }\n}", + "ida_pseudo_norm": "void func0(uint32_t *a1, int a2, long long a3) {\n uint32_t *v3;\n uint32_t *v4;\n int v5;\n int v6;\n uint32_t *v7;\n uint32_t *v8;\n if (a2 > 0) {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n v6 = 0;\n do {\n if (*v3)\n *(uint32_t *)(a3 + 4LL * v5++) = *v3;\n else\n ++v6;\n ++v3;\n } while (v3 != v4);\n if (v6 > 0) {\n v7 = (uint32_t *)(a3 + 4LL * v5);\n v8 = (uint32_t *)(a3 + 4 * (v5 + (long long)v6));\n do\n *v7++ = 0;\n while (v8 != v7);\n }\n }\n}" + }, + { + "index": 632, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int num_list[], int size, int result[]) {\n int zero_count = 0;\n int j = 0;\n for (int i = 0; i < size; i++) {\n if (num_list[i] == 0) {\n zero_count++;\n } else {\n result[j++] = num_list[i];\n }\n }\n for (int i = 0; i < zero_count; i++) {\n result[j++] = 0;\n }\n}", + "test": "int main() {\n\n int result[6];\n\n int list1[6] = {1, 0, 2, 0, 3, 4};\n\n func0(list1, 6, result);\n\n int expected1[6] = {1, 2, 3, 4, 0, 0};\n\n for (int i = 0; i < 6; i++) {\n\n assert(result[i] == expected1[i]);\n\n }\n\n\n\n int result2[9];\n\n int list2[9] = {2, 3, 2, 0, 0, 4, 0, 5, 0};\n\n func0(list2, 9, result2);\n\n int expected2[9] = {2, 3, 2, 4, 5, 0, 0, 0, 0};\n\n for (int i = 0; i < 9; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n\n\n int result3[5];\n\n int list3[5] = {0, 1, 0, 1, 1};\n\n func0(list3, 5, result3);\n\n int expected3[5] = {1, 1, 1, 0, 0};\n\n for (int i = 0; i < 5; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n\n\n printf(\"All tests passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 147f \nlea -0x1(%rsi),%eax\nxor %ecx,%ecx\nxor %esi,%esi\nlea 0x4(%rdi,%rax,4),%r8\njmp 143c \nnopw %cs:0x0(%rax,%rax,1)\nadd $0x4,%rdi\nadd $0x1,%esi\ncmp %r8,%rdi\nje 1455 \nmov (%rdi),%eax\ntest %eax,%eax\nje 1430 \nmovslq %ecx,%r9\nadd $0x4,%rdi\nadd $0x1,%ecx\nmov %eax,(%rdx,%r9,4)\ncmp %r8,%rdi\njne 143c \ntest %esi,%esi\nje 147f \nmovslq %ecx,%rcx\nsub $0x1,%esi\nlea (%rdx,%rcx,4),%rax\nadd %rsi,%rcx\nlea 0x4(%rdx,%rcx,4),%rdx\nnopl 0x0(%rax,%rax,1)\nmovl $0x0,(%rax)\nadd $0x4,%rax\ncmp %rdx,%rax\njne 1470 \nretq\n", + "ida_asm": "func0:\nendbr64\nmov r10, rdx\ntest esi, esi\njle short locret_1430\nmovsxd rsi, esi\nxor ecx, ecx\nlea r8, [rdi+rsi*4]\nxor esi, esi\njmp short loc_13FC\nloc_13F0:\nadd rdi, 4\nadd esi, 1\ncmp r8, rdi\njz short loc_1415\nloc_13FC:\nmov eax, [rdi]\ntest eax, eax\njz short loc_13F0\nmovsxd r9, ecx\nadd rdi, 4\nadd ecx, 1\nmov [r10+r9*4], eax\ncmp r8, rdi\njnz short loc_13FC\nloc_1415:\ntest esi, esi\njle short locret_1430\nmovsxd rcx, ecx\nlea rdx, ds:0[rsi*4]; n\nxor esi, esi; c\nlea rdi, [r10+rcx*4]; s\njmp _memset\nlocret_1430:\nretn", + "ida_pseudo": "void __fastcall func0(int *a1, int a2, __int64 a3)\n{\n int v3; // ecx\n int *v4; // r8\n __int64 v5; // rsi\n int v6; // eax\n __int64 v7; // r9\n\n if ( a2 > 0 )\n {\n v3 = 0;\n v4 = &a1[a2];\n v5 = 0LL;\n do\n {\n while ( 1 )\n {\n v6 = *a1;\n if ( *a1 )\n break;\n ++a1;\n v5 = (unsigned int)(v5 + 1);\n if ( v4 == a1 )\n goto LABEL_6;\n }\n v7 = v3;\n ++a1;\n ++v3;\n *(_DWORD *)(a3 + 4 * v7) = v6;\n }\n while ( v4 != a1 );\nLABEL_6:\n if ( (int)v5 > 0 )\n memset((void *)(a3 + 4LL * v3), 0, 4 * v5);\n }\n}", + "ida_strip_asm": "sub_13D0:\nendbr64\nmov r10, rdx\ntest esi, esi\njle short locret_1430\nmovsxd rsi, esi\nxor ecx, ecx\nlea r8, [rdi+rsi*4]\nxor esi, esi\njmp short loc_13FC\nloc_13F0:\nadd rdi, 4\nadd esi, 1\ncmp r8, rdi\njz short loc_1415\nloc_13FC:\nmov eax, [rdi]\ntest eax, eax\njz short loc_13F0\nmovsxd r9, ecx\nadd rdi, 4\nadd ecx, 1\nmov [r10+r9*4], eax\ncmp r8, rdi\njnz short loc_13FC\nloc_1415:\ntest esi, esi\njle short locret_1430\nmovsxd rcx, ecx\nlea rdx, ds:0[rsi*4]; n\nxor esi, esi; c\nlea rdi, [r10+rcx*4]; s\njmp _memset\nlocret_1430:\nretn", + "ida_strip_pseudo": "void __fastcall sub_13D0(int *a1, int a2, __int64 a3)\n{\n int v3; // ecx\n int *v4; // r8\n __int64 v5; // rsi\n int v6; // eax\n __int64 v7; // r9\n\n if ( a2 > 0 )\n {\n v3 = 0;\n v4 = &a1[a2];\n v5 = 0LL;\n do\n {\n while ( 1 )\n {\n v6 = *a1;\n if ( *a1 )\n break;\n ++a1;\n v5 = (unsigned int)(v5 + 1);\n if ( v4 == a1 )\n goto LABEL_6;\n }\n v7 = v3;\n ++a1;\n ++v3;\n *(_DWORD *)(a3 + 4 * v7) = v6;\n }\n while ( v4 != a1 );\nLABEL_6:\n if ( (int)v5 > 0 )\n memset((void *)(a3 + 4LL * v3), 0, 4 * v5);\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_13D0(int *a1, int a2, long long a3) {\n int v3;\n int *v4;\n long long v5;\n int v6;\n long long v7;\n if (a2 > 0) {\n v3 = 0;\n v4 = &a1[a2];\n v5 = 0LL;\n do {\n while (1) {\n v6 = *a1;\n if (*a1) break;\n ++a1;\n v5 = (unsigned int)(v5 + 1);\n if (v4 == a1) goto LABEL_6;\n }\n v7 = v3;\n ++a1;\n ++v3;\n *(uint32_t *)(a3 + 4 * v7) = v6;\n } while (v4 != a1);\n LABEL_6:\n if ((int)v5 > 0) memset((void *)(a3 + 4LL * v3), 0, 4 * v5);\n }\n}", + "ida_pseudo_norm": "void func0(int *a1, int a2, long long a3) {\n int v3;\n int *v4;\n long long v5;\n int v6;\n long long v7;\n if (a2 > 0) {\n v3 = 0;\n v4 = &a1[a2];\n v5 = 0LL;\n do {\n while (1) {\n v6 = *a1;\n if (*a1) break;\n ++a1;\n v5 = (unsigned int)(v5 + 1);\n if (v4 == a1) goto LABEL_6;\n }\n v7 = v3;\n ++a1;\n ++v3;\n *(uint32_t *)(a3 + 4 * v7) = v6;\n } while (v4 != a1);\n LABEL_6:\n if ((int)v5 > 0) memset((void *)(a3 + 4LL * v3), 0, 4 * v5);\n }\n}" + }, + { + "index": 632, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int num_list[], int size, int result[]) {\n int zero_count = 0;\n int j = 0;\n for (int i = 0; i < size; i++) {\n if (num_list[i] == 0) {\n zero_count++;\n } else {\n result[j++] = num_list[i];\n }\n }\n for (int i = 0; i < zero_count; i++) {\n result[j++] = 0;\n }\n}", + "test": "int main() {\n\n int result[6];\n\n int list1[6] = {1, 0, 2, 0, 3, 4};\n\n func0(list1, 6, result);\n\n int expected1[6] = {1, 2, 3, 4, 0, 0};\n\n for (int i = 0; i < 6; i++) {\n\n assert(result[i] == expected1[i]);\n\n }\n\n\n\n int result2[9];\n\n int list2[9] = {2, 3, 2, 0, 0, 4, 0, 5, 0};\n\n func0(list2, 9, result2);\n\n int expected2[9] = {2, 3, 2, 4, 5, 0, 0, 0, 0};\n\n for (int i = 0; i < 9; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n\n\n int result3[5];\n\n int list3[5] = {0, 1, 0, 1, 1};\n\n func0(list3, 5, result3);\n\n int expected3[5] = {1, 1, 1, 0, 0};\n\n for (int i = 0; i < 5; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n\n\n printf(\"All tests passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 14e8 \nlea -0x1(%rsi),%eax\nxor %ecx,%ecx\nxor %esi,%esi\nlea 0x4(%rdi,%rax,4),%r8\njmp 14ac \nnopw %cs:0x0(%rax,%rax,1)\nadd $0x4,%rdi\nadd $0x1,%esi\ncmp %rdi,%r8\nje 14c5 \nmov (%rdi),%eax\ntest %eax,%eax\nje 14a0 \nmovslq %ecx,%r9\nadd $0x4,%rdi\nadd $0x1,%ecx\nmov %eax,(%rdx,%r9,4)\ncmp %rdi,%r8\njne 14ac \ntest %esi,%esi\nje 14e8 \nlea -0x1(%rsi),%eax\nmovslq %ecx,%rcx\nxor %esi,%esi\nlea 0x4(,%rax,4),%r8\nlea (%rdx,%rcx,4),%rdi\nmov %r8,%rdx\njmpq 10b0 \nnopl (%rax)\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\nmov r10, rdx\ntest esi, esi\njle short locret_1410\nmovsxd rsi, esi\nxor ecx, ecx\nlea r8, [rdi+rsi*4]\nxor esi, esi\njmp short loc_13DC\nloc_13D0:\nadd rdi, 4\nadd esi, 1\ncmp r8, rdi\njz short loc_13F5\nloc_13DC:\nmov eax, [rdi]\ntest eax, eax\njz short loc_13D0\nmovsxd r9, ecx\nadd rdi, 4\nadd ecx, 1\nmov [r10+r9*4], eax\ncmp r8, rdi\njnz short loc_13DC\nloc_13F5:\ntest esi, esi\njle short locret_1410\nmovsxd rcx, ecx\nlea rdx, ds:0[rsi*4]; n\nxor esi, esi; c\nlea rdi, [r10+rcx*4]; s\njmp _memset\nlocret_1410:\nretn", + "ida_pseudo": "void __fastcall func0(int *a1, int a2, __int64 a3)\n{\n int v3; // ecx\n int *v4; // r8\n __int64 v5; // rsi\n int v6; // eax\n __int64 v7; // r9\n\n if ( a2 > 0 )\n {\n v3 = 0;\n v4 = &a1[a2];\n v5 = 0LL;\n do\n {\n while ( 1 )\n {\n v6 = *a1;\n if ( *a1 )\n break;\n ++a1;\n v5 = (unsigned int)(v5 + 1);\n if ( v4 == a1 )\n goto LABEL_6;\n }\n v7 = v3;\n ++a1;\n ++v3;\n *(_DWORD *)(a3 + 4 * v7) = v6;\n }\n while ( v4 != a1 );\nLABEL_6:\n if ( (int)v5 > 0 )\n memset((void *)(a3 + 4LL * v3), 0, 4 * v5);\n }\n}", + "ida_strip_asm": "sub_13B0:\nendbr64\nmov r10, rdx\ntest esi, esi\njle short locret_1410\nmovsxd rsi, esi\nxor ecx, ecx\nlea r8, [rdi+rsi*4]\nxor esi, esi\njmp short loc_13DC\nloc_13D0:\nadd rdi, 4\nadd esi, 1\ncmp r8, rdi\njz short loc_13F5\nloc_13DC:\nmov eax, [rdi]\ntest eax, eax\njz short loc_13D0\nmovsxd r9, ecx\nadd rdi, 4\nadd ecx, 1\nmov [r10+r9*4], eax\ncmp r8, rdi\njnz short loc_13DC\nloc_13F5:\ntest esi, esi\njle short locret_1410\nmovsxd rcx, ecx\nlea rdx, ds:0[rsi*4]; n\nxor esi, esi; c\nlea rdi, [r10+rcx*4]; s\njmp _memset\nlocret_1410:\nretn", + "ida_strip_pseudo": "void __fastcall sub_13B0(int *a1, int a2, __int64 a3)\n{\n int v3; // ecx\n int *v4; // r8\n __int64 v5; // rsi\n int v6; // eax\n __int64 v7; // r9\n\n if ( a2 > 0 )\n {\n v3 = 0;\n v4 = &a1[a2];\n v5 = 0LL;\n do\n {\n while ( 1 )\n {\n v6 = *a1;\n if ( *a1 )\n break;\n ++a1;\n v5 = (unsigned int)(v5 + 1);\n if ( v4 == a1 )\n goto LABEL_6;\n }\n v7 = v3;\n ++a1;\n ++v3;\n *(_DWORD *)(a3 + 4 * v7) = v6;\n }\n while ( v4 != a1 );\nLABEL_6:\n if ( (int)v5 > 0 )\n memset((void *)(a3 + 4LL * v3), 0, 4 * v5);\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_13B0(int *a1, int a2, long long a3) {\n int v3;\n int *v4;\n long long v5;\n int v6;\n long long v7;\n if (a2 > 0) {\n v3 = 0;\n v4 = &a1[a2];\n v5 = 0LL;\n do {\n while (1) {\n v6 = *a1;\n if (*a1) break;\n ++a1;\n v5 = (unsigned int)(v5 + 1);\n if (v4 == a1) goto LABEL_6;\n }\n v7 = v3;\n ++a1;\n ++v3;\n *(uint32_t *)(a3 + 4 * v7) = v6;\n } while (v4 != a1);\n LABEL_6:\n if ((int)v5 > 0) memset((void *)(a3 + 4LL * v3), 0, 4 * v5);\n }\n}", + "ida_pseudo_norm": "void func0(int *a1, int a2, long long a3) {\n int v3;\n int *v4;\n long long v5;\n int v6;\n long long v7;\n if (a2 > 0) {\n v3 = 0;\n v4 = &a1[a2];\n v5 = 0LL;\n do {\n while (1) {\n v6 = *a1;\n if (*a1) break;\n ++a1;\n v5 = (unsigned int)(v5 + 1);\n if (v4 == a1) goto LABEL_6;\n }\n v7 = v3;\n ++a1;\n ++v3;\n *(uint32_t *)(a3 + 4 * v7) = v6;\n } while (v4 != a1);\n LABEL_6:\n if ((int)v5 > 0) memset((void *)(a3 + 4LL * v3), 0, 4 * v5);\n }\n}" + }, + { + "index": 633, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int ans = 0;\n for (int i = 0; i < n; i++) {\n for (int j = i + 1; j < n; j++) {\n ans += (arr[i] ^ arr[j]);\n }\n }\n return ans;\n}", + "test": "int main() {\n\n int arr1[] = {5, 9, 7, 6};\n\n int arr2[] = {7, 3, 5};\n\n int arr3[] = {7, 3};\n\n\n\n assert(func0(arr1, 4) == 47);\n\n assert(func0(arr2, 3) == 12);\n\n assert(func0(arr3, 2) == 4);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11d4 \nmov -0x8(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x4(%rbp)\njmp 11c8 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\nxor %edx,%eax\nadd %eax,-0xc(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1193 \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1188 \nmov -0xc(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_11D4\nloc_1188:\nmov eax, [rbp+var_8]\nadd eax, 1\nmov [rbp+var_4], eax\njmp short loc_11C8\nloc_1193:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nxor eax, edx\nadd [rbp+var_C], eax\nadd [rbp+var_4], 1\nloc_11C8:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1193\nadd [rbp+var_8], 1\nloc_11D4:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+10h] [rbp-Ch]\n int i; // [rsp+14h] [rbp-8h]\n int j; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n v3 += *(_DWORD *)(4LL * i + a1) ^ *(_DWORD *)(4LL * j + a1);\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_11D4\nloc_1188:\nmov eax, [rbp+var_8]\nadd eax, 1\nmov [rbp+var_4], eax\njmp short loc_11C8\nloc_1193:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nxor eax, edx\nadd [rbp+var_C], eax\nadd [rbp+var_4], 1\nloc_11C8:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1193\nadd [rbp+var_8], 1\nloc_11D4:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+10h] [rbp-Ch]\n int i; // [rsp+14h] [rbp-8h]\n int j; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n v3 += *(_DWORD *)(4LL * i + a1) ^ *(_DWORD *)(4LL * j + a1);\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n unsigned int v3;\n int i;\n int j;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j)\n v3 += *(uint32_t *)(4LL * i + a1) ^ *(uint32_t *)(4LL * j + a1);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n int j;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j)\n v3 += *(uint32_t *)(4LL * i + a1) ^ *(uint32_t *)(4LL * j + a1);\n }\n return v3;\n}" + }, + { + "index": 633, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int ans = 0;\n for (int i = 0; i < n; i++) {\n for (int j = i + 1; j < n; j++) {\n ans += (arr[i] ^ arr[j]);\n }\n }\n return ans;\n}", + "test": "int main() {\n\n int arr1[] = {5, 9, 7, 6};\n\n int arr2[] = {7, 3, 5};\n\n int arr3[] = {7, 3};\n\n\n\n assert(func0(arr1, 4) == 47);\n\n assert(func0(arr2, 3) == 12);\n\n assert(func0(arr3, 2) == 4);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11a7 \nlea -0x1(%rsi),%r10d\nadd $0x1,%r10\nmov $0x1,%r9d\nmov $0x0,%edx\ncmp %r10,%r9\nje 11ac \nmov -0x4(%rdi,%r9,4),%r8d\nmov %r9,%rax\nmov %r8d,%ecx\nxor (%rdi,%rax,4),%ecx\nadd %ecx,%edx\nadd $0x1,%rax\ncmp %eax,%esi\njg 1191 \nadd $0x1,%r9\njmp 1184 \nmov $0x0,%edx\nmov %edx,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11AF\nmov r10d, esi\nmovsxd r11, esi\nmov r9d, 1\nmov edx, 0\njmp short loc_1187\nloc_1184:\nmov r9, rax\nloc_1187:\ncmp r9, r10\njz short loc_11B4\nmov r8d, [rdi+r9*4-4]\nmov rax, r9\nloc_1194:\nmov ecx, r8d\nxor ecx, [rdi+rax*4]\nadd edx, ecx\nadd rax, 1\ncmp esi, eax\njg short loc_1194\nlea rax, [r9+1]\ncmp r9, r11\njnz short loc_1184\njmp short loc_11B4\nloc_11AF:\nmov edx, 0\nloc_11B4:\nmov eax, edx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // r9\n unsigned int v3; // edx\n __int64 v4; // rax\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = 1LL;\n v3 = 0;\n while ( v2 != a2 )\n {\n v4 = v2;\n do\n v3 += *(_DWORD *)(a1 + 4 * v4++) ^ *(_DWORD *)(a1 + 4 * v2 - 4);\n while ( a2 > (int)v4 );\n if ( v2 == a2 )\n break;\n ++v2;\n }\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11AF\nmov r10d, esi\nmovsxd r11, esi\nmov r9d, 1\nmov edx, 0\njmp short loc_1187\nloc_1184:\nmov r9, rax\nloc_1187:\ncmp r9, r10\njz short loc_11B4\nmov r8d, [rdi+r9*4-4]\nmov rax, r9\nloc_1194:\nmov ecx, r8d\nxor ecx, [rdi+rax*4]\nadd edx, ecx\nadd rax, 1\ncmp esi, eax\njg short loc_1194\nlea rax, [r9+1]\ncmp r9, r11\njnz short loc_1184\njmp short loc_11B4\nloc_11AF:\nmov edx, 0\nloc_11B4:\nmov eax, edx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n __int64 v2; // r9\n unsigned int v3; // edx\n __int64 v4; // rax\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = 1LL;\n v3 = 0;\n while ( v2 != a2 )\n {\n v4 = v2;\n do\n v3 += *(_DWORD *)(a1 + 4 * v4++) ^ *(_DWORD *)(a1 + 4 * v2 - 4);\n while ( a2 > (int)v4 );\n if ( v2 == a2 )\n break;\n ++v2;\n }\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n long long v4;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = 1LL;\n v3 = 0;\n while (v2 != a2) {\n v4 = v2;\n do\n v3 += *(uint32_t *)(a1 + 4 * v4++) ^ *(uint32_t *)(a1 + 4 * v2 - 4);\n while (a2 > (int)v4);\n if (v2 == a2) break;\n ++v2;\n }\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n long long v4;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = 1LL;\n v3 = 0;\n while (v2 != a2) {\n v4 = v2;\n do\n v3 += *(uint32_t *)(a1 + 4 * v4++) ^ *(uint32_t *)(a1 + 4 * v2 - 4);\n while (a2 > (int)v4);\n if (v2 == a2) break;\n ++v2;\n }\n }\n return v3;\n}" + }, + { + "index": 633, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int ans = 0;\n for (int i = 0; i < n; i++) {\n for (int j = i + 1; j < n; j++) {\n ans += (arr[i] ^ arr[j]);\n }\n }\n return ans;\n}", + "test": "int main() {\n\n int arr1[] = {5, 9, 7, 6};\n\n int arr2[] = {7, 3, 5};\n\n int arr3[] = {7, 3};\n\n\n\n assert(func0(arr1, 4) == 47);\n\n assert(func0(arr2, 3) == 12);\n\n assert(func0(arr3, 2) == 4);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 12fd \nlea -0x1(%rsi),%r10d\nmov $0x1,%r9d\nxor %r8d,%r8d\nadd $0x1,%r10\ncmp %r10,%r9\nje 12f9 \nxchg %ax,%ax\nmov -0x4(%rdi,%r9,4),%ecx\nmov %r9,%rax\nnopl 0x0(%rax,%rax,1)\nmov (%rdi,%rax,4),%edx\nadd $0x1,%rax\nxor %ecx,%edx\nadd %edx,%r8d\ncmp %eax,%esi\njg 12e0 \nadd $0x1,%r9\ncmp %r10,%r9\njne 12d0 \nmov %r8d,%eax\nretq\nxor %r8d,%r8d\nmov %r8d,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_12BC\nmov r10d, esi\nmov r9d, 1\nxor edx, edx\ncmp esi, 1\njz short loc_12B9\nnop dword ptr [rax+rax+00000000h]\nloc_1290:\nmov r8d, [rdi+r9*4-4]\nmov rax, r9\nnop dword ptr [rax+rax+00000000h]\nloc_12A0:\nmov ecx, [rdi+rax*4]\nadd rax, 1\nxor ecx, r8d\nadd edx, ecx\ncmp esi, eax\njg short loc_12A0\nadd r9, 1\ncmp r9, r10\njnz short loc_1290\nloc_12B9:\nmov eax, edx\nretn\nloc_12BC:\nxor edx, edx\nmov eax, edx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // r9\n unsigned int v3; // edx\n __int64 v4; // rax\n int v5; // ecx\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 1LL;\n v3 = 0;\n if ( a2 != 1 )\n {\n do\n {\n v4 = v2;\n do\n {\n v5 = *(_DWORD *)(a1 + 4 * v4++);\n v3 += *(_DWORD *)(a1 + 4 * v2 - 4) ^ v5;\n }\n while ( a2 > (int)v4 );\n ++v2;\n }\n while ( v2 != a2 );\n }\n return v3;\n}", + "ida_strip_asm": "sub_1270:\nendbr64\ntest esi, esi\njle short loc_12BC\nmov r10d, esi\nmov r9d, 1\nxor edx, edx\ncmp esi, 1\njz short loc_12B9\nnop dword ptr [rax+rax+00000000h]\nloc_1290:\nmov r8d, [rdi+r9*4-4]\nmov rax, r9\nnop dword ptr [rax+rax+00000000h]\nloc_12A0:\nmov ecx, [rdi+rax*4]\nadd rax, 1\nxor ecx, r8d\nadd edx, ecx\ncmp esi, eax\njg short loc_12A0\nadd r9, 1\ncmp r9, r10\njnz short loc_1290\nloc_12B9:\nmov eax, edx\nretn\nloc_12BC:\nxor edx, edx\nmov eax, edx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1270(__int64 a1, int a2)\n{\n __int64 v2; // r9\n unsigned int v3; // edx\n __int64 v4; // rax\n int v5; // ecx\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 1LL;\n v3 = 0;\n if ( a2 != 1 )\n {\n do\n {\n v4 = v2;\n do\n {\n v5 = *(_DWORD *)(a1 + 4 * v4++);\n v3 += *(_DWORD *)(a1 + 4 * v2 - 4) ^ v5;\n }\n while ( a2 > (int)v4 );\n ++v2;\n }\n while ( v2 != a2 );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1270(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n long long v4;\n int v5;\n if (a2 <= 0) return 0LL;\n v2 = 1LL;\n v3 = 0;\n if (a2 != 1) {\n do {\n v4 = v2;\n do {\n v5 = *(uint32_t *)(a1 + 4 * v4++);\n v3 += *(uint32_t *)(a1 + 4 * v2 - 4) ^ v5;\n } while (a2 > (int)v4);\n ++v2;\n } while (v2 != a2);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n long long v4;\n int v5;\n if (a2 <= 0) return 0LL;\n v2 = 1LL;\n v3 = 0;\n if (a2 != 1) {\n do {\n v4 = v2;\n do {\n v5 = *(uint32_t *)(a1 + 4 * v4++);\n v3 += *(uint32_t *)(a1 + 4 * v2 - 4) ^ v5;\n } while (a2 > (int)v4);\n ++v2;\n } while (v2 != a2);\n }\n return v3;\n}" + }, + { + "index": 634, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int sum = 0;\n for (int i = 1; i <= n; i++) {\n int j = 2 * i;\n sum += j * j * j * j;\n }\n return sum;\n}", + "test": "int main() {\n\n assert(func0(2) == 272);\n\n assert(func0(3) == 1568);\n\n assert(func0(4) == 5664);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x1,-0x8(%rbp)\njmp 1181 \nmov -0x8(%rbp),%eax\nadd %eax,%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nimul %eax,%eax\nimul -0x4(%rbp),%eax\nimul -0x4(%rbp),%eax\nadd %eax,-0xc(%rbp)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x14(%rbp),%eax\njle 1164 \nmov -0xc(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 1\njmp short loc_1181\nloc_1164:\nmov eax, [rbp+var_8]\nadd eax, eax\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\nimul eax, eax\nimul eax, [rbp+var_4]\nimul eax, [rbp+var_4]\nadd [rbp+var_C], eax\nadd [rbp+var_8], 1\nloc_1181:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_14]\njle short loc_1164\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v2; // [rsp+8h] [rbp-Ch]\n int i; // [rsp+Ch] [rbp-8h]\n\n v2 = 0;\n for ( i = 1; i <= a1; ++i )\n v2 += 2 * i * 2 * i * 2 * i * 2 * i;\n return v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 1\njmp short loc_1181\nloc_1164:\nmov eax, [rbp+var_8]\nadd eax, eax\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\nimul eax, eax\nimul eax, [rbp+var_4]\nimul eax, [rbp+var_4]\nadd [rbp+var_C], eax\nadd [rbp+var_8], 1\nloc_1181:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_14]\njle short loc_1164\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n unsigned int v2; // [rsp+8h] [rbp-Ch]\n int i; // [rsp+Ch] [rbp-8h]\n\n v2 = 0;\n for ( i = 1; i <= a1; ++i )\n v2 += 2 * i * 2 * i * 2 * i * 2 * i;\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n unsigned int v2;\n int i;\n v2 = 0;\n for (i = 1; i <= a1; ++i) v2 += 2 * i * 2 * i * 2 * i * 2 * i;\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v2;\n int i;\n v2 = 0;\n for (i = 1; i <= a1; ++i) v2 += 2 * i * 2 * i * 2 * i * 2 * i;\n return v2;\n}" + }, + { + "index": 634, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int sum = 0;\n for (int i = 1; i <= n; i++) {\n int j = 2 * i;\n sum += j * j * j * j;\n }\n return sum;\n}", + "test": "int main() {\n\n assert(func0(2) == 272);\n\n assert(func0(3) == 1568);\n\n assert(func0(4) == 5664);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\njle 1173 \nlea 0x2(%rdi,%rdi,1),%esi\nmov $0x2,%eax\nmov $0x0,%ecx\nmov %eax,%edx\nimul %eax,%edx\nimul %edx,%edx\nadd %edx,%ecx\nadd $0x2,%eax\ncmp %esi,%eax\njne 115f \nmov %ecx,%eax\nretq\nmov $0x0,%ecx\njmp 1170 \n", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njle short loc_1173\nlea esi, [rdi+rdi+2]\nmov eax, 2\nmov ecx, 0\nloc_115F:\nmov edx, eax\nimul edx, eax\nimul edx, edx\nadd ecx, edx\nadd eax, 2\ncmp eax, esi\njnz short loc_115F\nloc_1170:\nmov eax, ecx\nretn\nloc_1173:\nmov ecx, 0\njmp short loc_1170", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // eax\n unsigned int v2; // ecx\n\n if ( a1 <= 0 )\n {\n return 0;\n }\n else\n {\n v1 = 2;\n v2 = 0;\n do\n {\n v2 += v1 * v1 * v1 * v1;\n v1 += 2;\n }\n while ( v1 != 2 * a1 + 2 );\n }\n return v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ntest edi, edi\njle short loc_1173\nlea esi, [rdi+rdi+2]\nmov eax, 2\nmov ecx, 0\nloc_115F:\nmov edx, eax\nimul edx, eax\nimul edx, edx\nadd ecx, edx\nadd eax, 2\ncmp eax, esi\njnz short loc_115F\nloc_1170:\nmov eax, ecx\nretn\nloc_1173:\nmov ecx, 0\njmp short loc_1170", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v1; // eax\n unsigned int v2; // ecx\n\n if ( a1 <= 0 )\n {\n return 0;\n }\n else\n {\n v1 = 2;\n v2 = 0;\n do\n {\n v2 += v1 * v1 * v1 * v1;\n v1 += 2;\n }\n while ( v1 != 2 * a1 + 2 );\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v1;\n unsigned int v2;\n if (a1 <= 0) {\n return 0;\n } else {\n v1 = 2;\n v2 = 0;\n do {\n v2 += v1 * v1 * v1 * v1;\n v1 += 2;\n } while (v1 != 2 * a1 + 2);\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n unsigned int v2;\n if (a1 <= 0) {\n return 0;\n } else {\n v1 = 2;\n v2 = 0;\n do {\n v2 += v1 * v1 * v1 * v1;\n v1 += 2;\n } while (v1 != 2 * a1 + 2);\n }\n return v2;\n}" + }, + { + "index": 635, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int *data;\n\n int size;\n\n int capacity;\n\n} MinHeap;\n\n\n\nMinHeap* heap_init(int capacity) {\n\n MinHeap *heap = malloc(sizeof(MinHeap));\n\n heap->data = malloc(sizeof(int) * capacity);\n\n heap->size = 0;\n\n heap->capacity = capacity;\n\n return heap;\n\n}\n\n\n\nvoid heap_push(MinHeap *heap, int value) {\n\n if (heap->size >= heap->capacity) {\n\n heap->capacity *= 2;\n\n heap->data = realloc(heap->data, sizeof(int) * heap->capacity);\n\n }\n\n heap->data[heap->size] = value;\n\n int i = heap->size;\n\n heap->size++;\n\n while (i != 0) {\n\n int parent = (i -1)/2;\n\n if (heap->data[parent] > heap->data[i]) {\n\n int temp = heap->data[parent];\n\n heap->data[parent] = heap->data[i];\n\n heap->data[i] = temp;\n\n i = parent;\n\n }\n\n else {\n\n break;\n\n }\n\n }\n\n}\n\n\n\nint heap_pop(MinHeap *heap) {\n\n if (heap->size == 0) {\n\n return -1;\n\n }\n\n int min = heap->data[0];\n\n heap->size--;\n\n heap->data[0] = heap->data[heap->size];\n\n int i = 0;\n\n while (1) {\n\n int left = 2*i +1;\n\n int right = 2*i +2;\n\n int smallest = i;\n\n if (left < heap->size && heap->data[left] < heap->data[smallest]) {\n\n smallest = left;\n\n }\n\n if (right < heap->size && heap->data[right] < heap->data[smallest]) {\n\n smallest = right;\n\n }\n\n if (smallest != i) {\n\n int temp = heap->data[i];\n\n heap->data[i] = heap->data[smallest];\n\n heap->data[smallest] = temp;\n\n i = smallest;\n\n }\n\n else {\n\n break;\n\n }\n\n }\n\n return min;\n\n}\n\n\n\nvoid heap_free(MinHeap *heap) {\n\n free(heap->data);\n\n free(heap);\n\n}\n\n\n\n\n\nint arrays_equal(int *a1, int *a2, int size) {\n\n for(int i=0;i 0 ? size : 1);\n for (int i = 0; i < size; i++) {\n heap_push(heap, array[i]);\n }\n int *sorted = malloc(sizeof(int) * size);\n for (int i = 0; i < size; i++) {\n sorted[i] = heap_pop(heap);\n }\n heap_free(heap);\n return sorted;\n}", + "test": "int main() {\n\n int input1[] = {1,3,5,7,9,2,4,6,8,0};\n\n int expected1[] = {0,1,2,3,4,5,6,7,8,9};\n\n int size1 = sizeof(input1)/sizeof(input1[0]);\n\n int *sorted1 = func0(input1, size1);\n\n assert(arrays_equal(sorted1, expected1, size1));\n\n free(sorted1);\n\n \n\n int input2[] = {25,35,22,85,14,65,75,25,58};\n\n int expected2[] = {14,22,25,25,35,58,65,75,85};\n\n int size2 = sizeof(input2)/sizeof(input2[0]);\n\n int *sorted2 = func0(input2, size2);\n\n assert(arrays_equal(sorted2, expected2, size2));\n\n free(sorted2);\n\n \n\n int input3[] = {7,1,9,5};\n\n int expected3[] = {1,5,7,9};\n\n int size3 = sizeof(input3)/sizeof(input3[0]);\n\n int *sorted3 = func0(input3, size3);\n\n assert(arrays_equal(sorted3, expected3, size3));\n\n free(sorted3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x38,%rsp\nmov %rdi,-0x38(%rbp)\nmov %esi,-0x3c(%rbp)\nmov $0x1,%eax\ncmpl $0x0,-0x3c(%rbp)\ncmovg -0x3c(%rbp),%eax\nmov %eax,%edi\ncallq 11c9 \nmov %rax,-0x20(%rbp)\nmovl $0x0,-0x28(%rbp)\njmp 15df \nmov -0x28(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x20(%rbp),%rax\nmov %edx,%esi\nmov %rax,%rdi\ncallq 121c \naddl $0x1,-0x28(%rbp)\nmov -0x28(%rbp),%eax\ncmp -0x3c(%rbp),%eax\njl 15b7 \nmov -0x3c(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10c0 \nmov %rax,-0x18(%rbp)\nmovl $0x0,-0x24(%rbp)\njmp 162c \nmov -0x24(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rbx\nmov -0x20(%rbp),%rax\nmov %rax,%rdi\ncallq 136f \nmov %eax,(%rbx)\naddl $0x1,-0x24(%rbp)\nmov -0x24(%rbp),%eax\ncmp -0x3c(%rbp),%eax\njl 1605 \nmov -0x20(%rbp),%rax\nmov %rax,%rdi\ncallq 14ee \nmov -0x18(%rbp),%rax\nadd $0x38,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov eax, [rbp+var_3C]\nmov edx, 1\ntest eax, eax\ncmovle eax, edx\nmov edi, eax\ncall heap_init\nmov [rbp+var_20], rax\nmov [rbp+var_28], 0\njmp short loc_15DF\nloc_15B7:\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_20]\nmov esi, edx\nmov rdi, rax\ncall heap_push\nadd [rbp+var_28], 1\nloc_15DF:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_3C]\njl short loc_15B7\nmov eax, [rbp+var_3C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_24], 0\njmp short loc_162C\nloc_1605:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nlea rbx, [rdx+rax]\nmov rax, [rbp+var_20]\nmov rdi, rax\ncall heap_pop\nmov [rbx], eax\nadd [rbp+var_24], 1\nloc_162C:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_3C]\njl short loc_1605\nmov rax, [rbp+var_20]\nmov rdi, rax\ncall heap_free\nmov rax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2)\n{\n unsigned int v2; // eax\n int i; // [rsp+18h] [rbp-28h]\n int j; // [rsp+1Ch] [rbp-24h]\n __int64 v6; // [rsp+20h] [rbp-20h]\n _DWORD *v7; // [rsp+28h] [rbp-18h]\n\n v2 = a2;\n if ( a2 <= 0 )\n v2 = 1;\n v6 = heap_init(v2);\n for ( i = 0; i < a2; ++i )\n heap_push(v6, *(unsigned int *)(4LL * i + a1));\n v7 = malloc(4LL * a2);\n for ( j = 0; j < a2; ++j )\n v7[j] = heap_pop(v6);\n heap_free(v6);\n return v7;\n}", + "ida_strip_asm": "sub_1582:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov eax, [rbp+var_3C]\nmov edx, 1\ntest eax, eax\ncmovle eax, edx\nmov edi, eax\ncall sub_11C9\nmov [rbp+var_20], rax\nmov [rbp+var_28], 0\njmp short loc_15DF\nloc_15B7:\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_20]\nmov esi, edx\nmov rdi, rax\ncall sub_121C\nadd [rbp+var_28], 1\nloc_15DF:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_3C]\njl short loc_15B7\nmov eax, [rbp+var_3C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_24], 0\njmp short loc_162C\nloc_1605:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nlea rbx, [rdx+rax]\nmov rax, [rbp+var_20]\nmov rdi, rax\ncall sub_136F\nmov [rbx], eax\nadd [rbp+var_24], 1\nloc_162C:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_3C]\njl short loc_1605\nmov rax, [rbp+var_20]\nmov rdi, rax\ncall sub_14EE\nmov rax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1582(__int64 a1, int a2)\n{\n unsigned int v2; // eax\n int i; // [rsp+18h] [rbp-28h]\n int j; // [rsp+1Ch] [rbp-24h]\n __int64 v6; // [rsp+20h] [rbp-20h]\n _DWORD *v7; // [rsp+28h] [rbp-18h]\n\n v2 = a2;\n if ( a2 <= 0 )\n v2 = 1;\n v6 = sub_11C9(v2);\n for ( i = 0; i < a2; ++i )\n sub_121C(v6, *(unsigned int *)(4LL * i + a1));\n v7 = malloc(4LL * a2);\n for ( j = 0; j < a2; ++j )\n v7[j] = sub_136F(v6);\n sub_14EE(v6);\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1582(long long a1, int a2) {\n unsigned int v2;\n int i;\n int j;\n long long v6;\n uint32_t *v7;\n v2 = a2;\n if (a2 <= 0) v2 = 1;\n v6 = sub_11C9(v2);\n for (i = 0; i < a2; ++i) sub_121C(v6, *(unsigned int *)(4LL * i + a1));\n v7 = malloc(4LL * a2);\n for (j = 0; j < a2; ++j) v7[j] = sub_136F(v6);\n sub_14EE(v6);\n return v7;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2) {\n unsigned int v2;\n int i;\n int j;\n long long v6;\n uint32_t *v7;\n v2 = a2;\n if (a2 <= 0) v2 = 1;\n v6 = heap_init(v2);\n for (i = 0; i < a2; ++i) heap_push(v6, *(unsigned int *)(4LL * i + a1));\n v7 = malloc(4LL * a2);\n for (j = 0; j < a2; ++j) v7[j] = heap_pop(v6);\n heap_free(v6);\n return v7;\n}" + }, + { + "index": 635, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int *data;\n\n int size;\n\n int capacity;\n\n} MinHeap;\n\n\n\nMinHeap* heap_init(int capacity) {\n\n MinHeap *heap = malloc(sizeof(MinHeap));\n\n heap->data = malloc(sizeof(int) * capacity);\n\n heap->size = 0;\n\n heap->capacity = capacity;\n\n return heap;\n\n}\n\n\n\nvoid heap_push(MinHeap *heap, int value) {\n\n if (heap->size >= heap->capacity) {\n\n heap->capacity *= 2;\n\n heap->data = realloc(heap->data, sizeof(int) * heap->capacity);\n\n }\n\n heap->data[heap->size] = value;\n\n int i = heap->size;\n\n heap->size++;\n\n while (i != 0) {\n\n int parent = (i -1)/2;\n\n if (heap->data[parent] > heap->data[i]) {\n\n int temp = heap->data[parent];\n\n heap->data[parent] = heap->data[i];\n\n heap->data[i] = temp;\n\n i = parent;\n\n }\n\n else {\n\n break;\n\n }\n\n }\n\n}\n\n\n\nint heap_pop(MinHeap *heap) {\n\n if (heap->size == 0) {\n\n return -1;\n\n }\n\n int min = heap->data[0];\n\n heap->size--;\n\n heap->data[0] = heap->data[heap->size];\n\n int i = 0;\n\n while (1) {\n\n int left = 2*i +1;\n\n int right = 2*i +2;\n\n int smallest = i;\n\n if (left < heap->size && heap->data[left] < heap->data[smallest]) {\n\n smallest = left;\n\n }\n\n if (right < heap->size && heap->data[right] < heap->data[smallest]) {\n\n smallest = right;\n\n }\n\n if (smallest != i) {\n\n int temp = heap->data[i];\n\n heap->data[i] = heap->data[smallest];\n\n heap->data[smallest] = temp;\n\n i = smallest;\n\n }\n\n else {\n\n break;\n\n }\n\n }\n\n return min;\n\n}\n\n\n\nvoid heap_free(MinHeap *heap) {\n\n free(heap->data);\n\n free(heap);\n\n}\n\n\n\n\n\nint arrays_equal(int *a1, int *a2, int size) {\n\n for(int i=0;i 0 ? size : 1);\n for (int i = 0; i < size; i++) {\n heap_push(heap, array[i]);\n }\n int *sorted = malloc(sizeof(int) * size);\n for (int i = 0; i < size; i++) {\n sorted[i] = heap_pop(heap);\n }\n heap_free(heap);\n return sorted;\n}", + "test": "int main() {\n\n int input1[] = {1,3,5,7,9,2,4,6,8,0};\n\n int expected1[] = {0,1,2,3,4,5,6,7,8,9};\n\n int size1 = sizeof(input1)/sizeof(input1[0]);\n\n int *sorted1 = func0(input1, size1);\n\n assert(arrays_equal(sorted1, expected1, size1));\n\n free(sorted1);\n\n \n\n int input2[] = {25,35,22,85,14,65,75,25,58};\n\n int expected2[] = {14,22,25,25,35,58,65,75,85};\n\n int size2 = sizeof(input2)/sizeof(input2[0]);\n\n int *sorted2 = func0(input2, size2);\n\n assert(arrays_equal(sorted2, expected2, size2));\n\n free(sorted2);\n\n \n\n int input3[] = {7,1,9,5};\n\n int expected3[] = {1,5,7,9};\n\n int size3 = sizeof(input3)/sizeof(input3[0]);\n\n int *sorted3 = func0(input3, size3);\n\n assert(arrays_equal(sorted3, expected3, size3));\n\n free(sorted3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%r13\nmov %esi,%r12d\ntest %esi,%esi\nmov $0x1,%edi\ncmovg %esi,%edi\ncallq 11c9 \nmov %rax,%rbp\ntest %r12d,%r12d\njle 140d \nmov %r13,%rbx\nlea -0x1(%r12),%r14d\nshl $0x2,%r14\nlea 0x4(%r13,%r14,1),%r13\nmov (%rbx),%esi\nmov %rbp,%rdi\ncallq 1205 \nadd $0x4,%rbx\ncmp %r13,%rbx\njne 13bc \nmovslq %r12d,%rdi\nshl $0x2,%rdi\ncallq 10c0 \nmov %rax,%r13\nmov %rax,%rbx\nlea 0x4(%rax,%r14,1),%r12\nmov %rbp,%rdi\ncallq 128a \nmov %eax,(%rbx)\nadd $0x4,%rbx\ncmp %r12,%rbx\njne 13e6 \nmov %rbp,%rdi\ncallq 1330 \nmov %r13,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nmovslq %r12d,%rdi\nshl $0x2,%rdi\ncallq 10c0 \nmov %rax,%r13\njmp 13f9 \n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r13, rdi\nmov ebp, esi\ntest esi, esi\nmov edi, 1\ncmovg edi, esi\ncall heap_init\nmov r12, rax\ntest ebp, ebp\njle short loc_1407\nmov rbx, r13\nmovsxd rbp, ebp\nshl rbp, 2\nadd r13, rbp\nloc_13BA:\nmov esi, [rbx]\nmov rdi, r12\ncall heap_push\nadd rbx, 4\ncmp rbx, r13\njnz short loc_13BA\nmov rdi, rbp; size\ncall _malloc\nmov r13, rax\nmov rbx, rax\nadd rbp, rax\nloc_13DE:\nmov rdi, r12\ncall heap_pop\nmov [rbx], eax\nadd rbx, 4\ncmp rbx, rbp\njnz short loc_13DE\nloc_13F1:\nmov rdi, r12; ptr\ncall heap_free\nmov rax, r13\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1407:\nmovsxd rdi, ebp\nshl rdi, 2; size\ncall _malloc\nmov r13, rax\njmp short loc_13F1", + "ida_pseudo": "_DWORD *__fastcall func0(unsigned int *a1, int a2)\n{\n __int64 v3; // rdi\n void *v4; // r12\n unsigned int *v5; // rbx\n size_t v6; // rbp\n unsigned int *v7; // r13\n _DWORD *v8; // r13\n _DWORD *v9; // rbx\n _DWORD *v10; // rbp\n\n v3 = 1LL;\n if ( a2 > 0 )\n v3 = (unsigned int)a2;\n v4 = (void *)heap_init(v3);\n if ( a2 <= 0 )\n {\n v8 = malloc(4LL * a2);\n }\n else\n {\n v5 = a1;\n v6 = a2;\n v7 = &a1[v6];\n do\n heap_push(v4, *v5++);\n while ( v5 != v7 );\n v8 = malloc(v6 * 4);\n v9 = v8;\n v10 = &v8[v6];\n do\n *v9++ = heap_pop(v4);\n while ( v9 != v10 );\n }\n heap_free(v4);\n return v8;\n}", + "ida_strip_asm": "sub_1384:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r13, rdi\nmov ebp, esi\ntest esi, esi\nmov edi, 1\ncmovg edi, esi\ncall sub_11C9\nmov r12, rax\ntest ebp, ebp\njle short loc_1407\nmov rbx, r13\nmovsxd rbp, ebp\nshl rbp, 2\nadd r13, rbp\nloc_13BA:\nmov esi, [rbx]\nmov rdi, r12\ncall sub_1205\nadd rbx, 4\ncmp rbx, r13\njnz short loc_13BA\nmov rdi, rbp; size\ncall _malloc\nmov r13, rax\nmov rbx, rax\nadd rbp, rax\nloc_13DE:\nmov rdi, r12\ncall sub_128A\nmov [rbx], eax\nadd rbx, 4\ncmp rbx, rbp\njnz short loc_13DE\nloc_13F1:\nmov rdi, r12; ptr\ncall sub_1333\nmov rax, r13\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1407:\nmovsxd rdi, ebp\nshl rdi, 2; size\ncall _malloc\nmov r13, rax\njmp short loc_13F1", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1384(unsigned int *a1, int a2)\n{\n __int64 v3; // rdi\n void *v4; // r12\n unsigned int *v5; // rbx\n size_t v6; // rbp\n unsigned int *v7; // r13\n _DWORD *v8; // r13\n _DWORD *v9; // rbx\n _DWORD *v10; // rbp\n\n v3 = 1LL;\n if ( a2 > 0 )\n v3 = (unsigned int)a2;\n v4 = (void *)sub_11C9(v3);\n if ( a2 <= 0 )\n {\n v8 = malloc(4LL * a2);\n }\n else\n {\n v5 = a1;\n v6 = a2;\n v7 = &a1[v6];\n do\n sub_1205(v4, *v5++);\n while ( v5 != v7 );\n v8 = malloc(v6 * 4);\n v9 = v8;\n v10 = &v8[v6];\n do\n *v9++ = sub_128A(v4);\n while ( v9 != v10 );\n }\n sub_1333(v4);\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1384(unsigned int *a1, int a2) {\n long long v3;\n void *v4;\n unsigned int *v5;\n unsigned int v6;\n unsigned int *v7;\n uint32_t *v8;\n uint32_t *v9;\n uint32_t *v10;\n v3 = 1LL;\n if (a2 > 0) v3 = (unsigned int)a2;\n v4 = (void *)sub_11C9(v3);\n if (a2 <= 0) {\n v8 = malloc(4LL * a2);\n } else {\n v5 = a1;\n v6 = a2;\n v7 = &a1[v6];\n do\n sub_1205(v4, *v5++);\n while (v5 != v7);\n v8 = malloc(v6 * 4);\n v9 = v8;\n v10 = &v8[v6];\n do\n *v9++ = sub_128A(v4);\n while (v9 != v10);\n }\n sub_1333(v4);\n return v8;\n}", + "ida_pseudo_norm": "uint32_t *func0(unsigned int *a1, int a2) {\n long long v3;\n void *v4;\n unsigned int *v5;\n unsigned int v6;\n unsigned int *v7;\n uint32_t *v8;\n uint32_t *v9;\n uint32_t *v10;\n v3 = 1LL;\n if (a2 > 0) v3 = (unsigned int)a2;\n v4 = (void *)heap_init(v3);\n if (a2 <= 0) {\n v8 = malloc(4LL * a2);\n } else {\n v5 = a1;\n v6 = a2;\n v7 = &a1[v6];\n do\n heap_push(v4, *v5++);\n while (v5 != v7);\n v8 = malloc(v6 * 4);\n v9 = v8;\n v10 = &v8[v6];\n do\n *v9++ = heap_pop(v4);\n while (v9 != v10);\n }\n heap_free(v4);\n return v8;\n}" + }, + { + "index": 635, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int *data;\n\n int size;\n\n int capacity;\n\n} MinHeap;\n\n\n\nMinHeap* heap_init(int capacity) {\n\n MinHeap *heap = malloc(sizeof(MinHeap));\n\n heap->data = malloc(sizeof(int) * capacity);\n\n heap->size = 0;\n\n heap->capacity = capacity;\n\n return heap;\n\n}\n\n\n\nvoid heap_push(MinHeap *heap, int value) {\n\n if (heap->size >= heap->capacity) {\n\n heap->capacity *= 2;\n\n heap->data = realloc(heap->data, sizeof(int) * heap->capacity);\n\n }\n\n heap->data[heap->size] = value;\n\n int i = heap->size;\n\n heap->size++;\n\n while (i != 0) {\n\n int parent = (i -1)/2;\n\n if (heap->data[parent] > heap->data[i]) {\n\n int temp = heap->data[parent];\n\n heap->data[parent] = heap->data[i];\n\n heap->data[i] = temp;\n\n i = parent;\n\n }\n\n else {\n\n break;\n\n }\n\n }\n\n}\n\n\n\nint heap_pop(MinHeap *heap) {\n\n if (heap->size == 0) {\n\n return -1;\n\n }\n\n int min = heap->data[0];\n\n heap->size--;\n\n heap->data[0] = heap->data[heap->size];\n\n int i = 0;\n\n while (1) {\n\n int left = 2*i +1;\n\n int right = 2*i +2;\n\n int smallest = i;\n\n if (left < heap->size && heap->data[left] < heap->data[smallest]) {\n\n smallest = left;\n\n }\n\n if (right < heap->size && heap->data[right] < heap->data[smallest]) {\n\n smallest = right;\n\n }\n\n if (smallest != i) {\n\n int temp = heap->data[i];\n\n heap->data[i] = heap->data[smallest];\n\n heap->data[smallest] = temp;\n\n i = smallest;\n\n }\n\n else {\n\n break;\n\n }\n\n }\n\n return min;\n\n}\n\n\n\nvoid heap_free(MinHeap *heap) {\n\n free(heap->data);\n\n free(heap);\n\n}\n\n\n\n\n\nint arrays_equal(int *a1, int *a2, int size) {\n\n for(int i=0;i 0 ? size : 1);\n for (int i = 0; i < size; i++) {\n heap_push(heap, array[i]);\n }\n int *sorted = malloc(sizeof(int) * size);\n for (int i = 0; i < size; i++) {\n sorted[i] = heap_pop(heap);\n }\n heap_free(heap);\n return sorted;\n}", + "test": "int main() {\n\n int input1[] = {1,3,5,7,9,2,4,6,8,0};\n\n int expected1[] = {0,1,2,3,4,5,6,7,8,9};\n\n int size1 = sizeof(input1)/sizeof(input1[0]);\n\n int *sorted1 = func0(input1, size1);\n\n assert(arrays_equal(sorted1, expected1, size1));\n\n free(sorted1);\n\n \n\n int input2[] = {25,35,22,85,14,65,75,25,58};\n\n int expected2[] = {14,22,25,25,35,58,65,75,85};\n\n int size2 = sizeof(input2)/sizeof(input2[0]);\n\n int *sorted2 = func0(input2, size2);\n\n assert(arrays_equal(sorted2, expected2, size2));\n\n free(sorted2);\n\n \n\n int input3[] = {7,1,9,5};\n\n int expected3[] = {1,5,7,9};\n\n int size3 = sizeof(input3)/sizeof(input3[0]);\n\n int *sorted3 = func0(input3, size3);\n\n assert(arrays_equal(sorted3, expected3, size3));\n\n free(sorted3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\nmovslq %esi,%r13\npush %r12\ntest %r13d,%r13d\nmov %r13,%r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nmov $0x1,%edi\ncmovg %r13d,%edi\nshl $0x2,%r13\ncallq 1490 \nmov %rax,%rbp\ntest %r12d,%r12d\njle 1718 \nlea -0x1(%r12),%r14d\nshl $0x2,%r14\nlea 0x4(%rbx,%r14,1),%r12\nmov (%rbx),%esi\nmov %rbp,%rdi\nadd $0x4,%rbx\ncallq 14e0 \ncmp %r12,%rbx\njne 16b0 \nmov %r13,%rdi\ncallq 10c0 \nmov %rax,%r13\nmov %rax,%rbx\nlea 0x4(%rax,%r14,1),%r12\nnopw %cs:0x0(%rax,%rax,1)\nmov %rbp,%rdi\nadd $0x4,%rbx\ncallq 1570 \nmov %eax,-0x4(%rbx)\ncmp %rbx,%r12\njne 16e0 \nmov 0x0(%rbp),%rdi\ncallq 1090 \nmov %rbp,%rdi\ncallq 1090 \npop %rbx\nmov %r13,%rax\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopl 0x0(%rax)\nmov %r13,%rdi\ncallq 10c0 \nmov %rax,%r13\njmp 16f4 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\ntest esi, esi\npush r13\nmov r13d, esi\npush r12\nmov r12d, 1\npush rbp\ncmovg r12d, esi\npush rbx\nmov rbx, rdi\nmov edi, 10h; size\ncall _malloc\nmovsxd rdi, r12d\nmov rbp, rax\nshl rdi, 2; size\ncall _malloc\nmov [rbp+0Ch], r12d\nmovsxd r12, r13d\nmov [rbp+0], rax\nshl r12, 2\nmov dword ptr [rbp+8], 0\ntest r13d, r13d\njle short loc_1680\nlea r13, [rbx+r12]\nnop word ptr [rax+rax+00000000h]\nloc_1620:\nmov esi, [rbx]\nmov rdi, rbp\nadd rbx, 4\ncall heap_push\ncmp rbx, r13\njnz short loc_1620\nmov rdi, r12; size\ncall _malloc\nmov r13, rax\nmov rbx, rax\nadd r12, rax\nnop dword ptr [rax+00h]\nloc_1648:\nmov rdi, rbp\nadd rbx, 4\ncall heap_pop\nmov [rbx-4], eax\ncmp rbx, r12\njnz short loc_1648\nmov r14, [rbp+0]\nloc_1660:\nmov rdi, r14; ptr\ncall _free\nmov rdi, rbp; ptr\ncall _free\npop rbx\nmov rax, r13\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1680:\nmov rdi, r12; size\nmov r14, rax\ncall _malloc\nmov r13, rax\njmp short loc_1660", + "ida_pseudo": "char *__fastcall func0(unsigned int *a1, int a2)\n{\n int v2; // r12d\n unsigned int *v3; // rbx\n _DWORD *v4; // rbp\n void *v5; // rax\n size_t v6; // r12\n __int64 v7; // rsi\n char *v8; // r13\n char *v9; // rbx\n char *v10; // r12\n void *v11; // r14\n\n v2 = 1;\n if ( a2 > 0 )\n v2 = a2;\n v3 = a1;\n v4 = malloc(0x10uLL);\n v5 = malloc(4LL * v2);\n v4[3] = v2;\n *(_QWORD *)v4 = v5;\n v6 = 4LL * a2;\n v4[2] = 0;\n if ( a2 <= 0 )\n {\n v11 = v5;\n v8 = (char *)malloc(4LL * a2);\n }\n else\n {\n do\n {\n v7 = *v3++;\n heap_push(v4, v7);\n }\n while ( v3 != &a1[v6 / 4] );\n v8 = (char *)malloc(v6);\n v9 = v8;\n v10 = &v8[v6];\n do\n {\n v9 += 4;\n *((_DWORD *)v9 - 1) = heap_pop(v4);\n }\n while ( v9 != v10 );\n v11 = *(void **)v4;\n }\n free(v11);\n free(v4);\n return v8;\n}", + "ida_strip_asm": "sub_15C0:\nendbr64\npush r14\ntest esi, esi\npush r13\nmov r13d, esi\npush r12\nmov r12d, 1\npush rbp\ncmovg r12d, esi\npush rbx\nmov rbx, rdi\nmov edi, 10h; size\ncall _malloc\nmovsxd rdi, r12d\nmov rbp, rax\nshl rdi, 2; size\ncall _malloc\nmov [rbp+0Ch], r12d\nmovsxd r12, r13d\nmov [rbp+0], rax\nshl r12, 2\nmov dword ptr [rbp+8], 0\ntest r13d, r13d\njle short loc_1680\nlea r13, [rbx+r12]\nnop word ptr [rax+rax+00000000h]\nloc_1620:\nmov esi, [rbx]\nmov rdi, rbp\nadd rbx, 4\ncall sub_1420\ncmp rbx, r13\njnz short loc_1620\nmov rdi, r12; size\ncall _malloc\nmov r13, rax\nmov rbx, rax\nadd r12, rax\nnop dword ptr [rax+00h]\nloc_1648:\nmov rdi, rbp\nadd rbx, 4\ncall sub_14B0\nmov [rbx-4], eax\ncmp rbx, r12\njnz short loc_1648\nmov r14, [rbp+0]\nloc_1660:\nmov rdi, r14; ptr\ncall _free\nmov rdi, rbp; ptr\ncall _free\npop rbx\nmov rax, r13\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1680:\nmov rdi, r12; size\nmov r14, rax\ncall _malloc\nmov r13, rax\njmp short loc_1660", + "ida_strip_pseudo": "char *__fastcall sub_15C0(unsigned int *a1, int a2)\n{\n int v2; // r12d\n unsigned int *v3; // rbx\n _DWORD *v4; // rbp\n void *v5; // rax\n size_t v6; // r12\n __int64 v7; // rsi\n char *v8; // r13\n char *v9; // rbx\n char *v10; // r12\n void *v11; // r14\n\n v2 = 1;\n if ( a2 > 0 )\n v2 = a2;\n v3 = a1;\n v4 = malloc(0x10uLL);\n v5 = malloc(4LL * v2);\n v4[3] = v2;\n *(_QWORD *)v4 = v5;\n v6 = 4LL * a2;\n v4[2] = 0;\n if ( a2 <= 0 )\n {\n v11 = v5;\n v8 = (char *)malloc(4LL * a2);\n }\n else\n {\n do\n {\n v7 = *v3++;\n sub_1420(v4, v7);\n }\n while ( v3 != &a1[v6 / 4] );\n v8 = (char *)malloc(v6);\n v9 = v8;\n v10 = &v8[v6];\n do\n {\n v9 += 4;\n *((_DWORD *)v9 - 1) = sub_14B0(v4);\n }\n while ( v9 != v10 );\n v11 = *(void **)v4;\n }\n free(v11);\n free(v4);\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_15C0(unsigned int *a1, int a2) {\n int v2;\n unsigned int *v3;\n uint32_t *v4;\n void *v5;\n unsigned int v6;\n long long v7;\n char *v8;\n char *v9;\n char *v10;\n void *v11;\n v2 = 1;\n if (a2 > 0) v2 = a2;\n v3 = a1;\n v4 = malloc(16uLL);\n v5 = malloc(4LL * v2);\n v4[3] = v2;\n *(uint64_t *)v4 = v5;\n v6 = 4LL * a2;\n v4[2] = 0;\n if (a2 <= 0) {\n v11 = v5;\n v8 = (char *)malloc(4LL * a2);\n } else {\n do {\n v7 = *v3++;\n sub_1420(v4, v7);\n } while (v3 != &a1[v6 / 4]);\n v8 = (char *)malloc(v6);\n v9 = v8;\n v10 = &v8[v6];\n do {\n v9 += 4;\n *((uint32_t *)v9 - 1) = sub_14B0(v4);\n } while (v9 != v10);\n v11 = *(void **)v4;\n }\n free(v11);\n free(v4);\n return v8;\n}", + "ida_pseudo_norm": "char *func0(unsigned int *a1, int a2) {\n int v2;\n unsigned int *v3;\n uint32_t *v4;\n void *v5;\n unsigned int v6;\n long long v7;\n char *v8;\n char *v9;\n char *v10;\n void *v11;\n v2 = 1;\n if (a2 > 0) v2 = a2;\n v3 = a1;\n v4 = malloc(16uLL);\n v5 = malloc(4LL * v2);\n v4[3] = v2;\n *(uint64_t *)v4 = v5;\n v6 = 4LL * a2;\n v4[2] = 0;\n if (a2 <= 0) {\n v11 = v5;\n v8 = (char *)malloc(4LL * a2);\n } else {\n do {\n v7 = *v3++;\n heap_push(v4, v7);\n } while (v3 != &a1[v6 / 4]);\n v8 = (char *)malloc(v6);\n v9 = v8;\n v10 = &v8[v6];\n do {\n v9 += 4;\n *((uint32_t *)v9 - 1) = heap_pop(v4);\n } while (v9 != v10);\n v11 = *(void **)v4;\n }\n free(v11);\n free(v4);\n return v8;\n}" + }, + { + "index": 635, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int *data;\n\n int size;\n\n int capacity;\n\n} MinHeap;\n\n\n\nMinHeap* heap_init(int capacity) {\n\n MinHeap *heap = malloc(sizeof(MinHeap));\n\n heap->data = malloc(sizeof(int) * capacity);\n\n heap->size = 0;\n\n heap->capacity = capacity;\n\n return heap;\n\n}\n\n\n\nvoid heap_push(MinHeap *heap, int value) {\n\n if (heap->size >= heap->capacity) {\n\n heap->capacity *= 2;\n\n heap->data = realloc(heap->data, sizeof(int) * heap->capacity);\n\n }\n\n heap->data[heap->size] = value;\n\n int i = heap->size;\n\n heap->size++;\n\n while (i != 0) {\n\n int parent = (i -1)/2;\n\n if (heap->data[parent] > heap->data[i]) {\n\n int temp = heap->data[parent];\n\n heap->data[parent] = heap->data[i];\n\n heap->data[i] = temp;\n\n i = parent;\n\n }\n\n else {\n\n break;\n\n }\n\n }\n\n}\n\n\n\nint heap_pop(MinHeap *heap) {\n\n if (heap->size == 0) {\n\n return -1;\n\n }\n\n int min = heap->data[0];\n\n heap->size--;\n\n heap->data[0] = heap->data[heap->size];\n\n int i = 0;\n\n while (1) {\n\n int left = 2*i +1;\n\n int right = 2*i +2;\n\n int smallest = i;\n\n if (left < heap->size && heap->data[left] < heap->data[smallest]) {\n\n smallest = left;\n\n }\n\n if (right < heap->size && heap->data[right] < heap->data[smallest]) {\n\n smallest = right;\n\n }\n\n if (smallest != i) {\n\n int temp = heap->data[i];\n\n heap->data[i] = heap->data[smallest];\n\n heap->data[smallest] = temp;\n\n i = smallest;\n\n }\n\n else {\n\n break;\n\n }\n\n }\n\n return min;\n\n}\n\n\n\nvoid heap_free(MinHeap *heap) {\n\n free(heap->data);\n\n free(heap);\n\n}\n\n\n\n\n\nint arrays_equal(int *a1, int *a2, int size) {\n\n for(int i=0;i 0 ? size : 1);\n for (int i = 0; i < size; i++) {\n heap_push(heap, array[i]);\n }\n int *sorted = malloc(sizeof(int) * size);\n for (int i = 0; i < size; i++) {\n sorted[i] = heap_pop(heap);\n }\n heap_free(heap);\n return sorted;\n}", + "test": "int main() {\n\n int input1[] = {1,3,5,7,9,2,4,6,8,0};\n\n int expected1[] = {0,1,2,3,4,5,6,7,8,9};\n\n int size1 = sizeof(input1)/sizeof(input1[0]);\n\n int *sorted1 = func0(input1, size1);\n\n assert(arrays_equal(sorted1, expected1, size1));\n\n free(sorted1);\n\n \n\n int input2[] = {25,35,22,85,14,65,75,25,58};\n\n int expected2[] = {14,22,25,25,35,58,65,75,85};\n\n int size2 = sizeof(input2)/sizeof(input2[0]);\n\n int *sorted2 = func0(input2, size2);\n\n assert(arrays_equal(sorted2, expected2, size2));\n\n free(sorted2);\n\n \n\n int input3[] = {7,1,9,5};\n\n int expected3[] = {1,5,7,9};\n\n int size3 = sizeof(input3)/sizeof(input3[0]);\n\n int *sorted3 = func0(input3, size3);\n\n assert(arrays_equal(sorted3, expected3, size3));\n\n free(sorted3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\nmov %rdi,%r14\nmov $0x10,%edi\npush %r13\npush %r12\nmov $0x1,%r12d\npush %rbp\npush %rbx\nmov %esi,%ebx\nsub $0x18,%rsp\ntest %esi,%esi\ncmovg %esi,%r12d\ncallq 10c0 \nmovslq %r12d,%rdi\nmov %rax,%rbp\nshl $0x2,%rdi\ncallq 10c0 \nmov %r12d,0xc(%rbp)\nmovslq %ebx,%r12\nmov %rax,0x0(%rbp)\nmov %rax,%r13\nlea 0x0(,%r12,4),%rax\nmovl $0x0,0x8(%rbp)\nmov %rax,0x8(%rsp)\ntest %ebx,%ebx\njle 17e8 \nsub $0x1,%ebx\nmov (%r14),%r12d\nadd $0x4,%r14\nxor %eax,%eax\nshl $0x2,%rbx\nlea (%r14,%rbx,1),%r15\nnopw 0x0(%rax,%rax,1)\nmov %r12d,0x0(%r13,%rax,4)\nmov 0x8(%rbp),%edx\nlea 0x1(%rdx),%eax\nmov %eax,0x8(%rbp)\ntest %edx,%edx\njne 1730 \njmp 1754 \nnopl 0x0(%rax)\nmov %edi,(%rsi)\nmov %ecx,(%rax)\ntest %edx,%edx\nje 1754 \nmovslq %edx,%rax\nlea -0x1(%rax),%ecx\nlea 0x0(%r13,%rax,4),%rax\nmov %ecx,%edx\nmov (%rax),%edi\nshr $0x1f,%edx\nadd %ecx,%edx\nsar %edx\nmovslq %edx,%rcx\nlea 0x0(%r13,%rcx,4),%rsi\nmov (%rsi),%ecx\ncmp %edi,%ecx\njg 1728 \ncmp %r14,%r15\nje 1790 \nmovslq 0x8(%rbp),%rax\nmov 0xc(%rbp),%esi\nmov (%r14),%r12d\ncmp %esi,%eax\njl 1786 \nadd %esi,%esi\nmov %r13,%rdi\nmov %esi,0xc(%rbp)\nmovslq %esi,%rsi\nshl $0x2,%rsi\ncallq 10d0 \nmov %rax,0x0(%rbp)\nmov %rax,%r13\nmovslq 0x8(%rbp),%rax\nadd $0x4,%r14\njmp 1710 \nnopl 0x0(%rax)\nmov 0x8(%rsp),%rdi\ncallq 10c0 \nmov %rax,%r14\nmov %rax,%r12\nlea 0x4(%rax,%rbx,1),%rbx\nnopl (%rax)\nmov %rbp,%rdi\nadd $0x4,%r12\ncallq 1580 \nmov %eax,-0x4(%r12)\ncmp %rbx,%r12\njne 17a8 \nmov 0x0(%rbp),%r13\nmov %r13,%rdi\ncallq 1090 \nmov %rbp,%rdi\ncallq 1090 \nadd $0x18,%rsp\nmov %r14,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\nmov %rax,%rdi\ncallq 10c0 \nmov %rax,%r14\njmp 17c2 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov edx, 1\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov ebx, esi\nsub rsp, 28h\ntest esi, esi\ncmovg edx, esi\nmov [rsp+58h+var_58], rdi\nmov edi, 10h; size\nmov ebp, edx\ncall _malloc\nmovsxd rdi, ebp\nshl rdi, 2; size\nmov r15, rax\ncall _malloc\nmovsxd r8, ebx\nmov [r15+0Ch], ebp\nmov [r15], rax\nmov r13, rax\nlea rax, ds:0[r8*4]\nmov dword ptr [r15+8], 0\nmov [rsp+58h+size], rax\ntest ebx, ebx\njle loc_174E\nmov rcx, [rsp+58h+var_58]\nxor r14d, r14d\nmov r9d, r14d\nmovsxd rbx, r14d\nmov r12d, [rcx+r14*4]\ncmp ebp, r14d\njle short loc_16B3\nnop dword ptr [rax]\nloc_1650:\nlea eax, [r9+1]\nmov [r13+r14*4+0], r12d\nmov [r15+8], eax\ntest r14, r14\njnz short loc_1677\njmp short loc_1697\nloc_1668:\nmov [rdx], r12d\nmov [rdi], esi\ntest eax, eax\njz short loc_1697\nmov r12d, [rdx]\nmovsxd rbx, eax\nloc_1677:\nlea edx, [rbx-1]\nlea rdi, [r13+rbx*4+0]\nmov eax, edx\nshr eax, 1Fh\nadd eax, edx\nsar eax, 1\nmovsxd rdx, eax\nlea rdx, [r13+rdx*4+0]\nmov esi, [rdx]\ncmp esi, r12d\njg short loc_1668\nloc_1697:\nadd r14, 1\ncmp r14, r8\njz short loc_16F8\nmov ebp, [r15+0Ch]\nmov r12d, [rcx+r14*4]\nmov r9d, r14d\nmovsxd rbx, r14d\ncmp ebp, r14d\njg short loc_1650\nloc_16B3:\nlea edx, [rbp+rbp+0]\nmov rdi, r13; ptr\nmov [rsp+58h+var_48], rcx\nmov [r15+0Ch], edx\nmovsxd rdx, edx\nlea rsi, ds:0[rdx*4]; size\nmov [rsp+58h+var_50], r8\nmov dword ptr [rsp+58h+var_58], r14d\ncall _realloc\nmov rcx, [rsp+58h+var_48]\nmov r8, [rsp+58h+var_50]\nmov [r15], rax\nmov r9d, dword ptr [rsp+58h+var_58]\nmov r13, rax\njmp loc_1650\nloc_16F8:\nmov r14, [rsp+58h+size]\nmov rdi, r14; size\ncall _malloc\nadd r14, rax\nmov r12, rax\nmov rbx, rax\nmov rbp, r14\nnop dword ptr [rax+00000000h]\nloc_1718:\nmov rdi, r15\nadd rbx, 4\ncall heap_pop\nmov [rbx-4], eax\ncmp rbp, rbx\njnz short loc_1718\nloc_172C:\nmov rdi, r13; ptr\ncall _free\nmov rdi, r15; ptr\ncall _free\nadd rsp, 28h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_174E:\nmov rdi, rax; size\ncall _malloc\nmov r12, rax\njmp short loc_172C", + "ida_pseudo": "void *__fastcall func0(_DWORD *a1, int a2)\n{\n int v2; // edx\n int v3; // ebp\n _DWORD *v4; // r15\n _DWORD *v5; // rax\n __int64 v6; // r8\n _DWORD *v7; // r13\n _DWORD *v8; // rcx\n __int64 v9; // r14\n int v10; // r9d\n __int64 v11; // rbx\n int v12; // r12d\n int v13; // eax\n int *v14; // rdx\n int v15; // esi\n int v16; // ebp\n _DWORD *v17; // rax\n char *v18; // rax\n char *v19; // r14\n void *v20; // r12\n char *v21; // rbx\n __int64 v23; // [rsp+8h] [rbp-50h]\n _DWORD *v24; // [rsp+10h] [rbp-48h]\n __int64 size; // [rsp+18h] [rbp-40h]\n\n v2 = 1;\n if ( a2 > 0 )\n v2 = a2;\n v3 = v2;\n v4 = malloc(0x10uLL);\n v5 = malloc(4LL * v3);\n v6 = a2;\n v4[3] = v3;\n *(_QWORD *)v4 = v5;\n v7 = v5;\n v4[2] = 0;\n size = 4LL * a2;\n if ( a2 <= 0 )\n {\n v20 = malloc(4LL * a2);\n }\n else\n {\n v8 = a1;\n v9 = 0LL;\n v10 = 0;\n v11 = 0LL;\n v12 = *a1;\n while ( 1 )\n {\n v7[v9] = v12;\n v4[2] = v10 + 1;\n if ( v9 )\n {\n while ( 1 )\n {\n v13 = ((int)v11 - 1) / 2;\n v14 = &v7[v13];\n v15 = *v14;\n if ( *v14 <= v12 )\n break;\n *v14 = v12;\n v7[v11] = v15;\n if ( !v13 )\n break;\n v12 = *v14;\n v11 = v13;\n }\n }\n if ( ++v9 == v6 )\n break;\n v16 = v4[3];\n v12 = v8[v9];\n v10 = v9;\n v11 = (int)v9;\n if ( v16 <= (int)v9 )\n {\n v24 = v8;\n v4[3] = 2 * v16;\n v23 = v6;\n v17 = realloc(v7, 8LL * v16);\n v8 = v24;\n v6 = v23;\n *(_QWORD *)v4 = v17;\n v10 = v9;\n v7 = v17;\n }\n }\n v18 = (char *)malloc(size);\n v19 = &v18[size];\n v20 = v18;\n v21 = v18;\n do\n {\n v21 += 4;\n *((_DWORD *)v21 - 1) = heap_pop(v4);\n }\n while ( v19 != v21 );\n }\n free(v7);\n free(v4);\n return v20;\n}", + "ida_strip_asm": "sub_15D0:\nendbr64\npush r15\nmov edx, 1\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov ebx, esi\nsub rsp, 28h\ntest esi, esi\ncmovg edx, esi\nmov [rsp+58h+var_58], rdi\nmov edi, 10h; size\nmov ebp, edx\ncall _malloc\nmovsxd rdi, ebp\nshl rdi, 2; size\nmov r15, rax\ncall _malloc\nmovsxd r8, ebx\nmov [r15+0Ch], ebp\nmov [r15], rax\nmov r13, rax\nlea rax, ds:0[r8*4]\nmov dword ptr [r15+8], 0\nmov [rsp+58h+size], rax\ntest ebx, ebx\njle loc_174E\nmov rcx, [rsp+58h+var_58]\nxor r14d, r14d\nmov r9d, r14d\nmovsxd rbx, r14d\nmov r12d, [rcx+r14*4]\ncmp ebp, r14d\njle short loc_16B3\nnop dword ptr [rax]\nloc_1650:\nlea eax, [r9+1]\nmov [r13+r14*4+0], r12d\nmov [r15+8], eax\ntest r14, r14\njnz short loc_1677\njmp short loc_1697\nloc_1668:\nmov [rdx], r12d\nmov [rdi], esi\ntest eax, eax\njz short loc_1697\nmov r12d, [rdx]\nmovsxd rbx, eax\nloc_1677:\nlea edx, [rbx-1]\nlea rdi, [r13+rbx*4+0]\nmov eax, edx\nshr eax, 1Fh\nadd eax, edx\nsar eax, 1\nmovsxd rdx, eax\nlea rdx, [r13+rdx*4+0]\nmov esi, [rdx]\ncmp esi, r12d\njg short loc_1668\nloc_1697:\nadd r14, 1\ncmp r14, r8\njz short loc_16F8\nmov ebp, [r15+0Ch]\nmov r12d, [rcx+r14*4]\nmov r9d, r14d\nmovsxd rbx, r14d\ncmp ebp, r14d\njg short loc_1650\nloc_16B3:\nlea edx, [rbp+rbp+0]\nmov rdi, r13; ptr\nmov [rsp+58h+var_48], rcx\nmov [r15+0Ch], edx\nmovsxd rdx, edx\nlea rsi, ds:0[rdx*4]; size\nmov [rsp+58h+var_50], r8\nmov dword ptr [rsp+58h+var_58], r14d\ncall _realloc\nmov rcx, [rsp+58h+var_48]\nmov r8, [rsp+58h+var_50]\nmov [r15], rax\nmov r9d, dword ptr [rsp+58h+var_58]\nmov r13, rax\njmp loc_1650\nloc_16F8:\nmov r14, [rsp+58h+size]\nmov rdi, r14; size\ncall _malloc\nadd r14, rax\nmov r12, rax\nmov rbx, rax\nmov rbp, r14\nnop dword ptr [rax+00000000h]\nloc_1718:\nmov rdi, r15\nadd rbx, 4\ncall sub_14A0\nmov [rbx-4], eax\ncmp rbp, rbx\njnz short loc_1718\nloc_172C:\nmov rdi, r13; ptr\ncall _free\nmov rdi, r15; ptr\ncall _free\nadd rsp, 28h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_174E:\nmov rdi, rax; size\ncall _malloc\nmov r12, rax\njmp short loc_172C", + "ida_strip_pseudo": "void *__fastcall sub_15D0(_DWORD *a1, int a2)\n{\n int v2; // edx\n int v3; // ebp\n _DWORD *v4; // r15\n _DWORD *v5; // rax\n __int64 v6; // r8\n _DWORD *v7; // r13\n _DWORD *v8; // rcx\n __int64 v9; // r14\n int v10; // r9d\n __int64 v11; // rbx\n int v12; // r12d\n int v13; // eax\n int *v14; // rdx\n int v15; // esi\n int v16; // ebp\n _DWORD *v17; // rax\n char *v18; // rax\n char *v19; // r14\n void *v20; // r12\n char *v21; // rbx\n __int64 v23; // [rsp+8h] [rbp-50h]\n _DWORD *v24; // [rsp+10h] [rbp-48h]\n __int64 size; // [rsp+18h] [rbp-40h]\n\n v2 = 1;\n if ( a2 > 0 )\n v2 = a2;\n v3 = v2;\n v4 = malloc(0x10uLL);\n v5 = malloc(4LL * v3);\n v6 = a2;\n v4[3] = v3;\n *(_QWORD *)v4 = v5;\n v7 = v5;\n v4[2] = 0;\n size = 4LL * a2;\n if ( a2 <= 0 )\n {\n v20 = malloc(4LL * a2);\n }\n else\n {\n v8 = a1;\n v9 = 0LL;\n v10 = 0;\n v11 = 0LL;\n v12 = *a1;\n while ( 1 )\n {\n v7[v9] = v12;\n v4[2] = v10 + 1;\n if ( v9 )\n {\n while ( 1 )\n {\n v13 = ((int)v11 - 1) / 2;\n v14 = &v7[v13];\n v15 = *v14;\n if ( *v14 <= v12 )\n break;\n *v14 = v12;\n v7[v11] = v15;\n if ( !v13 )\n break;\n v12 = *v14;\n v11 = v13;\n }\n }\n if ( ++v9 == v6 )\n break;\n v16 = v4[3];\n v12 = v8[v9];\n v10 = v9;\n v11 = (int)v9;\n if ( v16 <= (int)v9 )\n {\n v24 = v8;\n v4[3] = 2 * v16;\n v23 = v6;\n v17 = realloc(v7, 8LL * v16);\n v8 = v24;\n v6 = v23;\n *(_QWORD *)v4 = v17;\n v10 = v9;\n v7 = v17;\n }\n }\n v18 = (char *)malloc(size);\n v19 = &v18[size];\n v20 = v18;\n v21 = v18;\n do\n {\n v21 += 4;\n *((_DWORD *)v21 - 1) = sub_14A0(v4);\n }\n while ( v19 != v21 );\n }\n free(v7);\n free(v4);\n return v20;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_15D0(uint32_t *a1, int a2) {\n int v2;\n int v3;\n uint32_t *v4;\n uint32_t *v5;\n long long v6;\n uint32_t *v7;\n uint32_t *v8;\n long long v9;\n int v10;\n long long v11;\n int v12;\n int v13;\n int *v14;\n int v15;\n int v16;\n uint32_t *v17;\n char *v18;\n char *v19;\n void *v20;\n char *v21;\n long long v23;\n uint32_t *v24;\n long long size;\n v2 = 1;\n if (a2 > 0) v2 = a2;\n v3 = v2;\n v4 = malloc(16uLL);\n v5 = malloc(4LL * v3);\n v6 = a2;\n v4[3] = v3;\n *(uint64_t *)v4 = v5;\n v7 = v5;\n v4[2] = 0;\n size = 4LL * a2;\n if (a2 <= 0) {\n v20 = malloc(4LL * a2);\n } else {\n v8 = a1;\n v9 = 0LL;\n v10 = 0;\n v11 = 0LL;\n v12 = *a1;\n while (1) {\n v7[v9] = v12;\n v4[2] = v10 + 1;\n if (v9) {\n while (1) {\n v13 = ((int)v11 - 1) / 2;\n v14 = &v7[v13];\n v15 = *v14;\n if (*v14 <= v12) break;\n *v14 = v12;\n v7[v11] = v15;\n if (!v13) break;\n v12 = *v14;\n v11 = v13;\n }\n }\n if (++v9 == v6) break;\n v16 = v4[3];\n v12 = v8[v9];\n v10 = v9;\n v11 = (int)v9;\n if (v16 <= (int)v9) {\n v24 = v8;\n v4[3] = 2 * v16;\n v23 = v6;\n v17 = realloc(v7, 8LL * v16);\n v8 = v24;\n v6 = v23;\n *(uint64_t *)v4 = v17;\n v10 = v9;\n v7 = v17;\n }\n }\n v18 = (char *)malloc(size);\n v19 = &v18[size];\n v20 = v18;\n v21 = v18;\n do {\n v21 += 4;\n *((uint32_t *)v21 - 1) = sub_14A0(v4);\n } while (v19 != v21);\n }\n free(v7);\n free(v4);\n return v20;\n}", + "ida_pseudo_norm": "void *func0(uint32_t *a1, int a2) {\n int v2;\n int v3;\n uint32_t *v4;\n uint32_t *v5;\n long long v6;\n uint32_t *v7;\n uint32_t *v8;\n long long v9;\n int v10;\n long long v11;\n int v12;\n int v13;\n int *v14;\n int v15;\n int v16;\n uint32_t *v17;\n char *v18;\n char *v19;\n void *v20;\n char *v21;\n long long v23;\n uint32_t *v24;\n long long size;\n v2 = 1;\n if (a2 > 0) v2 = a2;\n v3 = v2;\n v4 = malloc(16uLL);\n v5 = malloc(4LL * v3);\n v6 = a2;\n v4[3] = v3;\n *(uint64_t *)v4 = v5;\n v7 = v5;\n v4[2] = 0;\n size = 4LL * a2;\n if (a2 <= 0) {\n v20 = malloc(4LL * a2);\n } else {\n v8 = a1;\n v9 = 0LL;\n v10 = 0;\n v11 = 0LL;\n v12 = *a1;\n while (1) {\n v7[v9] = v12;\n v4[2] = v10 + 1;\n if (v9) {\n while (1) {\n v13 = ((int)v11 - 1) / 2;\n v14 = &v7[v13];\n v15 = *v14;\n if (*v14 <= v12) break;\n *v14 = v12;\n v7[v11] = v15;\n if (!v13) break;\n v12 = *v14;\n v11 = v13;\n }\n }\n if (++v9 == v6) break;\n v16 = v4[3];\n v12 = v8[v9];\n v10 = v9;\n v11 = (int)v9;\n if (v16 <= (int)v9) {\n v24 = v8;\n v4[3] = 2 * v16;\n v23 = v6;\n v17 = realloc(v7, 8LL * v16);\n v8 = v24;\n v6 = v23;\n *(uint64_t *)v4 = v17;\n v10 = v9;\n v7 = v17;\n }\n }\n v18 = (char *)malloc(size);\n v19 = &v18[size];\n v20 = v18;\n v21 = v18;\n do {\n v21 += 4;\n *((uint32_t *)v21 - 1) = heap_pop(v4);\n } while (v19 != v21);\n }\n free(v7);\n free(v4);\n return v20;\n}" + }, + { + "index": 636, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(int a, int b, int c) {\n if (a == c) {\n return \"Yes\";\n } else {\n return \"No\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(2, 0, 2), \"Yes\") == 0);\n\n assert(strcmp(func0(2, -5, 2), \"Yes\") == 0);\n\n assert(strcmp(func0(1, 2, 3), \"No\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov %esi,-0x8(%rbp)\nmov %edx,-0xc(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0xc(%rbp),%eax\njne 118b \nlea 0xe7f(%rip),%rax\njmp 1192 \nlea 0xe7a(%rip),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov [rbp+var_C], edx\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_C]\njnz short loc_118B\nlea rax, s2; \"Yes\"\njmp short loc_1192\nloc_118B:\nlea rax, aNo; \"No\"\nloc_1192:\npop rbp\nretn", + "ida_pseudo": "const char *__fastcall func0(int a1, __int64 a2, int a3)\n{\n if ( a1 == a3 )\n return \"Yes\";\n else\n return \"No\";\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov [rbp+var_C], edx\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_C]\njnz short loc_118B\nlea rax, s2; \"Yes\"\njmp short loc_1192\nloc_118B:\nlea rax, aNo; \"No\"\nloc_1192:\npop rbp\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1169(int a1, __int64 a2, int a3)\n{\n if ( a1 == a3 )\n return \"Yes\";\n else\n return \"No\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char* sub_1169(int a1, long long a2, int a3) {\n if (a1 == a3)\n return \"Yes\";\n else\n return \"No\";\n}", + "ida_pseudo_norm": "const char* func0(int a1, long long a2, int a3) {\n if (a1 == a3)\n return \"Yes\";\n else\n return \"No\";\n}" + }, + { + "index": 637, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int actual_cost, int sale_amount) {\n if (sale_amount == actual_cost) {\n return true;\n } else {\n return false;\n }\n}", + "test": "int main() {\n\n assert(func0(1500, 1200) == false);\n\n assert(func0(100, 100) == true);\n\n assert(func0(2000, 5000) == false);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov %esi,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x4(%rbp),%eax\njne 1166 \nmov $0x1,%eax\njmp 116b \nmov $0x0,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njnz short loc_1166\nmov eax, 1\njmp short loc_116B\nloc_1166:\nmov eax, 0\nloc_116B:\npop rbp\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(int a1, int a2)\n{\n return a2 == a1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njnz short loc_1166\nmov eax, 1\njmp short loc_116B\nloc_1166:\nmov eax, 0\nloc_116B:\npop rbp\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1149(int a1, int a2)\n{\n return a2 == a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1149(int a1, int a2) { return a2 == a1; }", + "ida_pseudo_norm": "uint8_t func0(int a1, int a2) { return a2 == a1; }" + }, + { + "index": 638, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int v, int t) {\n double windchill =\n 13.12 + 0.6215 * t - 11.37 * pow(v, 0.16) + 0.3965 * t * pow(v, 0.16);\n return (int)(round(windchill));\n}", + "test": "int main() {\n\n assert(func0(120, 35) == 40);\n\n assert(func0(40, 70) == 86);\n\n assert(func0(10, 100) == 116);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\ncvtsi2sdl -0x18(%rbp),%xmm1\nmovsd 0xee0(%rip),%xmm0\nmulsd %xmm0,%xmm1\nmovsd 0xedc(%rip),%xmm0\naddsd %xmm0,%xmm1\nmovsd %xmm1,-0x20(%rbp)\ncvtsi2sdl -0x14(%rbp),%xmm0\nmovsd 0xece(%rip),%xmm1\ncallq 1080 \nmovsd 0xec9(%rip),%xmm1\nmulsd %xmm1,%xmm0\nmovsd -0x20(%rbp),%xmm1\nsubsd %xmm0,%xmm1\nmovsd %xmm1,-0x20(%rbp)\ncvtsi2sdl -0x18(%rbp),%xmm1\nmovsd 0xeb2(%rip),%xmm0\nmovapd %xmm1,%xmm2\nmulsd %xmm0,%xmm2\nmovsd %xmm2,-0x28(%rbp)\ncvtsi2sdl -0x14(%rbp),%xmm0\nmovsd 0xe88(%rip),%xmm1\ncallq 1080 \nmulsd -0x28(%rbp),%xmm0\naddsd -0x20(%rbp),%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmov -0x8(%rbp),%rax\nmovq %rax,%xmm0\ncallq 1070 \ncvttsd2si %xmm0,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_18]\nmovsd xmm0, cs:qword_2070\nmulsd xmm1, xmm0\nmovsd xmm0, cs:qword_2078\naddsd xmm1, xmm0\nmovsd [rbp+var_20], xmm1\npxor xmm3, xmm3\ncvtsi2sd xmm3, [rbp+var_14]\nmovq rax, xmm3\nmovsd xmm0, cs:y\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\nmovsd xmm1, cs:qword_2088\nmulsd xmm0, xmm1\nmovsd xmm1, [rbp+var_20]\nsubsd xmm1, xmm0\nmovsd [rbp+var_20], xmm1\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_18]\nmovsd xmm0, cs:qword_2090\nmovapd xmm2, xmm1\nmulsd xmm2, xmm0\nmovsd [rbp+var_28], xmm2\npxor xmm4, xmm4\ncvtsi2sd xmm4, [rbp+var_14]\nmovq rax, xmm4\nmovsd xmm0, cs:y\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\nmulsd xmm0, [rbp+var_28]\naddsd xmm0, [rbp+var_20]\nmovsd [rbp+x], xmm0\nmov rax, [rbp+x]\nmovq xmm0, rax; x\ncall _round\ncvttsd2si eax, xmm0\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n double v3; // [rsp+10h] [rbp-20h]\n double x; // [rsp+28h] [rbp-8h]\n\n v3 = (double)a2 * 0.6215000000000001 + 13.12 - pow((double)a1, 0.16) * 11.37;\n x = pow((double)a1, 0.16) * ((double)a2 * 0.3965) + v3;\n return (unsigned int)(int)round(x);\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_18]\nmovsd xmm0, cs:qword_2070\nmulsd xmm1, xmm0\nmovsd xmm0, cs:qword_2078\naddsd xmm1, xmm0\nmovsd [rbp+var_20], xmm1\npxor xmm3, xmm3\ncvtsi2sd xmm3, [rbp+var_14]\nmovq rax, xmm3\nmovsd xmm0, cs:y\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\nmovsd xmm1, cs:qword_2088\nmulsd xmm0, xmm1\nmovsd xmm1, [rbp+var_20]\nsubsd xmm1, xmm0\nmovsd [rbp+var_20], xmm1\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_18]\nmovsd xmm0, cs:qword_2090\nmovapd xmm2, xmm1\nmulsd xmm2, xmm0\nmovsd [rbp+var_28], xmm2\npxor xmm4, xmm4\ncvtsi2sd xmm4, [rbp+var_14]\nmovq rax, xmm4\nmovsd xmm0, cs:y\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\nmulsd xmm0, [rbp+var_28]\naddsd xmm0, [rbp+var_20]\nmovsd [rbp+x], xmm0\nmov rax, [rbp+x]\nmovq xmm0, rax; x\ncall _round\ncvttsd2si eax, xmm0\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(int a1, int a2)\n{\n double v3; // [rsp+10h] [rbp-20h]\n double x; // [rsp+28h] [rbp-8h]\n\n v3 = (double)a2 * 0.6215000000000001 + 13.12 - pow((double)a1, 0.16) * 11.37;\n x = pow((double)a1, 0.16) * ((double)a2 * 0.3965) + v3;\n return (unsigned int)(int)round(x);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(int a1, int a2) {\n double v3;\n double x;\n v3 = (double)a2 * 0.6215000000000001 + 13.12 - pow((double)a1, 0.16) * 11.37;\n x = pow((double)a1, 0.16) * ((double)a2 * 0.3965) + v3;\n return (unsigned int)(int)round(x);\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n double v3;\n double x;\n v3 = (double)a2 * 0.6215000000000001 + 13.12 - pow((double)a1, 0.16) * 11.37;\n x = pow((double)a1, 0.16) * ((double)a2 * 0.3965) + v3;\n return (unsigned int)(int)round(x);\n}" + }, + { + "index": 638, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int v, int t) {\n double windchill =\n 13.12 + 0.6215 * t - 11.37 * pow(v, 0.16) + 0.3965 * t * pow(v, 0.16);\n return (int)(round(windchill));\n}", + "test": "int main() {\n\n assert(func0(120, 35) == 40);\n\n assert(func0(40, 70) == 86);\n\n assert(func0(10, 100) == 116);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x28,%rsp\npxor %xmm4,%xmm4\ncvtsi2sd %esi,%xmm4\nmovsd %xmm4,0x8(%rsp)\npxor %xmm6,%xmm6\ncvtsi2sd %edi,%xmm6\nmov 0xeda(%rip),%rax\nmovq %rax,%xmm1\nmovsd %xmm6,0x10(%rsp)\nmovapd %xmm6,%xmm0\ncallq 1080 \nmovsd %xmm0,0x18(%rsp)\nmov 0xeb9(%rip),%rax\nmovq %rax,%xmm1\nmovsd 0x10(%rsp),%xmm0\ncallq 1080 \nmovapd %xmm0,%xmm3\nmovsd 0x8(%rsp),%xmm4\nmovapd %xmm4,%xmm5\nmulsd 0xe9b(%rip),%xmm5\nmovapd %xmm5,%xmm0\naddsd 0xe97(%rip),%xmm0\nmovsd 0x18(%rsp),%xmm2\nmulsd 0xe91(%rip),%xmm2\nsubsd %xmm2,%xmm0\nmulsd 0xe8d(%rip),%xmm4\nmovapd %xmm4,%xmm1\nmulsd %xmm3,%xmm1\naddsd %xmm1,%xmm0\ncallq 1070 \ncvttsd2si %xmm0,%eax\nadd $0x28,%rsp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbx\nsub rsp, 10h\npxor xmm3, xmm3\ncvtsi2sd xmm3, esi\nmovsd [rsp+18h+var_18], xmm3\npxor xmm5, xmm5\ncvtsi2sd xmm5, edi\nmovq rbx, xmm5\nmovsd xmm1, cs:y; y\nmovapd xmm0, xmm5; x\ncall _pow\nmovsd [rsp+18h+var_10], xmm0\nmovsd xmm1, cs:y; y\nmovq xmm0, rbx; x\ncall _pow\nmovapd xmm2, xmm0\nmovsd xmm3, [rsp+18h+var_18]\nmovapd xmm4, xmm3\nmulsd xmm4, cs:qword_2078\nmovapd xmm0, xmm4\naddsd xmm0, cs:qword_2080\nmovsd xmm1, [rsp+18h+var_10]\nmulsd xmm1, cs:qword_2088\nsubsd xmm0, xmm1\nmulsd xmm3, cs:qword_2090\nmovapd xmm1, xmm3\nmulsd xmm1, xmm2\naddsd xmm0, xmm1; x\ncall _round\ncvttsd2si eax, xmm0\nadd rsp, 10h\npop rbx\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n double v2; // xmm0_8\n double v4; // [rsp+8h] [rbp-10h]\n\n v4 = pow((double)a1, 0.16);\n v2 = pow((double)a1, 0.16);\n return (unsigned int)(int)round((double)a2 * 0.6215000000000001 + 13.12 - v4 * 11.37 + (double)a2 * 0.3965 * v2);\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbx\nsub rsp, 10h\npxor xmm3, xmm3\ncvtsi2sd xmm3, esi\nmovsd [rsp+18h+var_18], xmm3\npxor xmm5, xmm5\ncvtsi2sd xmm5, edi\nmovq rbx, xmm5\nmovsd xmm1, cs:y; y\nmovapd xmm0, xmm5; x\ncall _pow\nmovsd [rsp+18h+var_10], xmm0\nmovsd xmm1, cs:y; y\nmovq xmm0, rbx; x\ncall _pow\nmovapd xmm2, xmm0\nmovsd xmm3, [rsp+18h+var_18]\nmovapd xmm4, xmm3\nmulsd xmm4, cs:qword_2078\nmovapd xmm0, xmm4\naddsd xmm0, cs:qword_2080\nmovsd xmm1, [rsp+18h+var_10]\nmulsd xmm1, cs:qword_2088\nsubsd xmm0, xmm1\nmulsd xmm3, cs:qword_2090\nmovapd xmm1, xmm3\nmulsd xmm1, xmm2\naddsd xmm0, xmm1; x\ncall _round\ncvttsd2si eax, xmm0\nadd rsp, 10h\npop rbx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(int a1, int a2)\n{\n double v2; // xmm0_8\n double v4; // [rsp+8h] [rbp-10h]\n\n v4 = pow((double)a1, 0.16);\n v2 = pow((double)a1, 0.16);\n return (unsigned int)(int)round((double)a2 * 0.6215000000000001 + 13.12 - v4 * 11.37 + (double)a2 * 0.3965 * v2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(int a1, int a2) {\n double v2;\n double v4;\n v4 = pow((double)a1, 0.16);\n v2 = pow((double)a1, 0.16);\n return (unsigned int)(int)round((double)a2 * 0.6215000000000001 + 13.12 -\n v4 * 11.37 + (double)a2 * 0.3965 * v2);\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n double v2;\n double v4;\n v4 = pow((double)a1, 0.16);\n v2 = pow((double)a1, 0.16);\n return (unsigned int)(int)round((double)a2 * 0.6215000000000001 + 13.12 -\n v4 * 11.37 + (double)a2 * 0.3965 * v2);\n}" + }, + { + "index": 638, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int v, int t) {\n double windchill =\n 13.12 + 0.6215 * t - 11.37 * pow(v, 0.16) + 0.3965 * t * pow(v, 0.16);\n return (int)(round(windchill));\n}", + "test": "int main() {\n\n assert(func0(120, 35) == 40);\n\n assert(func0(40, 70) == 86);\n\n assert(func0(10, 100) == 116);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npxor %xmm4,%xmm4\npxor %xmm2,%xmm2\nsub $0x28,%rsp\nmovsd 0xe30(%rip),%xmm1\ncvtsi2sd %edi,%xmm4\ncvtsi2sd %esi,%xmm2\nmovapd %xmm4,%xmm0\nmovsd %xmm4,0x10(%rsp)\nmovsd %xmm2,0x18(%rsp)\ncallq 1080 \nmov 0xe0c(%rip),%rax\nmovsd 0x10(%rsp),%xmm4\nmovsd %xmm0,0x8(%rsp)\nmovq %rax,%xmm1\nmovapd %xmm4,%xmm0\ncallq 1080 \nmovsd 0x18(%rsp),%xmm2\nmovsd 0x8(%rsp),%xmm3\nmulsd 0xdf6(%rip),%xmm3\nmovapd %xmm0,%xmm1\nmovsd 0xdda(%rip),%xmm0\nmulsd %xmm2,%xmm0\nmulsd 0xde6(%rip),%xmm2\naddsd 0xdce(%rip),%xmm0\nsubsd %xmm3,%xmm0\nmulsd %xmm1,%xmm2\naddsd %xmm2,%xmm0\ncallq 1070 \nadd $0x28,%rsp\ncvttsd2si %xmm0,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npxor xmm4, xmm4\npxor xmm2, xmm2\nsub rsp, 28h\nmovsd xmm1, cs:y; y\ncvtsi2sd xmm4, edi\ncvtsi2sd xmm2, esi\nmovapd xmm0, xmm4; x\nmovsd [rsp+28h+x], xmm4\nmovsd [rsp+28h+var_10], xmm2\ncall _pow\nmovsd xmm4, [rsp+28h+x]\nmovsd xmm1, cs:y; y\nmovsd [rsp+28h+var_20], xmm0\nmovapd xmm0, xmm4; x\ncall _pow\nmovsd xmm2, [rsp+28h+var_10]\nmovsd xmm3, [rsp+28h+var_20]\nmovapd xmm4, xmm0\nmovsd xmm0, cs:qword_2078\nmovsd xmm1, cs:qword_2088\nmulsd xmm0, xmm2\nmulsd xmm2, cs:qword_2090\naddsd xmm0, cs:qword_2080\nmulsd xmm1, xmm3\nmulsd xmm2, xmm4\nsubsd xmm0, xmm1\naddsd xmm0, xmm2; x\ncall _round\nadd rsp, 28h\ncvttsd2si eax, xmm0\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n double v2; // xmm4_8\n double v4; // [rsp+8h] [rbp-20h]\n\n v4 = pow((double)a1, 0.16);\n v2 = pow((double)a1, 0.16);\n return (unsigned int)(int)round(0.6215000000000001 * (double)a2 + 13.12 - 11.37 * v4 + (double)a2 * 0.3965 * v2);\n}", + "ida_strip_asm": "sub_1240:\nendbr64\npxor xmm4, xmm4\npxor xmm2, xmm2\nsub rsp, 28h\nmovsd xmm1, cs:y; y\ncvtsi2sd xmm4, edi\ncvtsi2sd xmm2, esi\nmovapd xmm0, xmm4; x\nmovsd [rsp+28h+x], xmm4\nmovsd [rsp+28h+var_10], xmm2\ncall _pow\nmovsd xmm4, [rsp+28h+x]\nmovsd xmm1, cs:y; y\nmovsd [rsp+28h+var_20], xmm0\nmovapd xmm0, xmm4; x\ncall _pow\nmovsd xmm2, [rsp+28h+var_10]\nmovsd xmm3, [rsp+28h+var_20]\nmovapd xmm4, xmm0\nmovsd xmm0, cs:qword_2078\nmovsd xmm1, cs:qword_2088\nmulsd xmm0, xmm2\nmulsd xmm2, cs:qword_2090\naddsd xmm0, cs:qword_2080\nmulsd xmm1, xmm3\nmulsd xmm2, xmm4\nsubsd xmm0, xmm1\naddsd xmm0, xmm2; x\ncall _round\nadd rsp, 28h\ncvttsd2si eax, xmm0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1240(int a1, int a2)\n{\n double v2; // xmm4_8\n double v4; // [rsp+8h] [rbp-20h]\n\n v4 = pow((double)a1, 0.16);\n v2 = pow((double)a1, 0.16);\n return (unsigned int)(int)round(0.6215000000000001 * (double)a2 + 13.12 - 11.37 * v4 + (double)a2 * 0.3965 * v2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1240(int a1, int a2) {\n double v2;\n double v4;\n v4 = pow((double)a1, 0.16);\n v2 = pow((double)a1, 0.16);\n return (unsigned int)(int)round(0.6215000000000001 * (double)a2 + 13.12 -\n 11.37 * v4 + (double)a2 * 0.3965 * v2);\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n double v2;\n double v4;\n v4 = pow((double)a1, 0.16);\n v2 = pow((double)a1, 0.16);\n return (unsigned int)(int)round(0.6215000000000001 * (double)a2 + 13.12 -\n 11.37 * v4 + (double)a2 * 0.3965 * v2);\n}" + }, + { + "index": 638, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int v, int t) {\n double windchill =\n 13.12 + 0.6215 * t - 11.37 * pow(v, 0.16) + 0.3965 * t * pow(v, 0.16);\n return (int)(round(windchill));\n}", + "test": "int main() {\n\n assert(func0(120, 35) == 40);\n\n assert(func0(40, 70) == 86);\n\n assert(func0(10, 100) == 116);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npxor %xmm4,%xmm4\npxor %xmm2,%xmm2\nsub $0x28,%rsp\nmovsd 0xe30(%rip),%xmm1\ncvtsi2sd %edi,%xmm4\ncvtsi2sd %esi,%xmm2\nmovapd %xmm4,%xmm0\nmovsd %xmm4,0x10(%rsp)\nmovsd %xmm2,0x18(%rsp)\ncallq 1080 \nmov 0xe0c(%rip),%rax\nmovsd 0x10(%rsp),%xmm4\nmovsd %xmm0,0x8(%rsp)\nmovq %rax,%xmm1\nmovapd %xmm4,%xmm0\ncallq 1080 \nmovsd 0x18(%rsp),%xmm2\nmovsd 0x8(%rsp),%xmm3\nmulsd 0xdf6(%rip),%xmm3\nmovapd %xmm0,%xmm1\nmovsd 0xdda(%rip),%xmm0\nmulsd %xmm2,%xmm0\nmulsd 0xde6(%rip),%xmm2\naddsd 0xdce(%rip),%xmm0\nsubsd %xmm3,%xmm0\nmulsd %xmm1,%xmm2\naddsd %xmm2,%xmm0\ncallq 1070 \nadd $0x28,%rsp\ncvttsd2si %xmm0,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npxor xmm4, xmm4\npxor xmm2, xmm2\nsub rsp, 28h\nmovsd xmm1, cs:y; y\ncvtsi2sd xmm4, edi\ncvtsi2sd xmm2, esi\nmovapd xmm0, xmm4; x\nmovsd [rsp+28h+x], xmm4\nmovsd [rsp+28h+var_10], xmm2\ncall _pow\nmovsd xmm4, [rsp+28h+x]\nmovsd xmm1, cs:y; y\nmovsd [rsp+28h+var_20], xmm0\nmovapd xmm0, xmm4; x\ncall _pow\nmovsd xmm2, [rsp+28h+var_10]\nmovsd xmm3, [rsp+28h+var_20]\nmovapd xmm4, xmm0\nmovsd xmm0, cs:qword_2078\nmovsd xmm1, cs:qword_2088\nmulsd xmm0, xmm2\nmulsd xmm2, cs:qword_2090\naddsd xmm0, cs:qword_2080\nmulsd xmm1, xmm3\nmulsd xmm2, xmm4\nsubsd xmm0, xmm1\naddsd xmm0, xmm2; x\ncall _round\nadd rsp, 28h\ncvttsd2si eax, xmm0\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n double v2; // xmm4_8\n double v4; // [rsp+8h] [rbp-20h]\n\n v4 = pow((double)a1, 0.16);\n v2 = pow((double)a1, 0.16);\n return (unsigned int)(int)round(0.6215000000000001 * (double)a2 + 13.12 - 11.37 * v4 + (double)a2 * 0.3965 * v2);\n}", + "ida_strip_asm": "sub_1240:\nendbr64\npxor xmm4, xmm4\npxor xmm2, xmm2\nsub rsp, 28h\nmovsd xmm1, cs:y; y\ncvtsi2sd xmm4, edi\ncvtsi2sd xmm2, esi\nmovapd xmm0, xmm4; x\nmovsd [rsp+28h+x], xmm4\nmovsd [rsp+28h+var_10], xmm2\ncall _pow\nmovsd xmm4, [rsp+28h+x]\nmovsd xmm1, cs:y; y\nmovsd [rsp+28h+var_20], xmm0\nmovapd xmm0, xmm4; x\ncall _pow\nmovsd xmm2, [rsp+28h+var_10]\nmovsd xmm3, [rsp+28h+var_20]\nmovapd xmm4, xmm0\nmovsd xmm0, cs:qword_2078\nmovsd xmm1, cs:qword_2088\nmulsd xmm0, xmm2\nmulsd xmm2, cs:qword_2090\naddsd xmm0, cs:qword_2080\nmulsd xmm1, xmm3\nmulsd xmm2, xmm4\nsubsd xmm0, xmm1\naddsd xmm0, xmm2; x\ncall _round\nadd rsp, 28h\ncvttsd2si eax, xmm0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1240(int a1, int a2)\n{\n double v2; // xmm4_8\n double v4; // [rsp+8h] [rbp-20h]\n\n v4 = pow((double)a1, 0.16);\n v2 = pow((double)a1, 0.16);\n return (unsigned int)(int)round(0.6215000000000001 * (double)a2 + 13.12 - 11.37 * v4 + (double)a2 * 0.3965 * v2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1240(int a1, int a2) {\n double v2;\n double v4;\n v4 = pow((double)a1, 0.16);\n v2 = pow((double)a1, 0.16);\n return (unsigned int)(int)round(0.6215000000000001 * (double)a2 + 13.12 -\n 11.37 * v4 + (double)a2 * 0.3965 * v2);\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n double v2;\n double v4;\n v4 = pow((double)a1, 0.16);\n v2 = pow((double)a1, 0.16);\n return (unsigned int)(int)round(0.6215000000000001 * (double)a2 + 13.12 -\n 11.37 * v4 + (double)a2 * 0.3965 * v2);\n}" + }, + { + "index": 639, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char *sample_names[], int length) {\n int i, j, valid;\n int total_length = 0;\n for (i = 0; i < length; i++) {\n char *name = sample_names[i];\n if (isupper(name[0])) {\n valid = 1;\n for (j = 1; name[j] != '\\0'; j++) {\n if (!islower(name[j])) {\n valid = 0;\n break;\n }\n }\n if (valid) total_length += strlen(name);\n }\n }\n return total_length;\n}", + "test": "int main() {\n\n char *names1[] = {\"sally\", \"Dylan\", \"rebecca\", \"Diana\", \"Joanne\", \"keith\"};\n\n assert(func0(names1, 6) == 16);\n\n\n\n char *names2[] = {\"php\", \"res\", \"Python\", \"abcd\", \"Java\", \"aaa\"};\n\n assert(func0(names2, 6) == 10);\n\n\n\n char *names3[] = {\"abcd\", \"Python\", \"abba\", \"aba\"};\n\n assert(func0(names3, 4) == 6);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x0,-0x18(%rbp)\njmpq 1294 \nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov %rax,-0x8(%rbp)\ncallq 10b0 <__ctype_b_loc@plt>\nmov (%rax),%rdx\nmov -0x8(%rbp),%rax\nmovzbl (%rax),%eax\nmovsbq %al,%rax\nadd %rax,%rax\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x100,%eax\ntest %eax,%eax\nje 1290 \nmovl $0x1,-0x10(%rbp)\nmovl $0x1,-0x14(%rbp)\njmp 1260 \ncallq 10b0 <__ctype_b_loc@plt>\nmov (%rax),%rax\nmov -0x14(%rbp),%edx\nmovslq %edx,%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rdx),%edx\nmovsbq %dl,%rdx\nadd %rdx,%rdx\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x200,%eax\ntest %eax,%eax\njne 125c \nmovl $0x0,-0x10(%rbp)\njmp 1274 \naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 1222 \ncmpl $0x0,-0x10(%rbp)\nje 1290 \nmov -0x8(%rbp),%rax\nmov %rax,%rdi\ncallq 1080 \nmov %eax,%edx\nmov -0xc(%rbp),%eax\nadd %edx,%eax\nmov %eax,-0xc(%rbp)\naddl $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 11cf \nmov -0xc(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_C], 0\nmov [rbp+var_18], 0\njmp loc_1294\nloc_11CF:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov [rbp+s], rax\ncall ___ctype_b_loc\nmov rdx, [rax]\nmov rax, [rbp+s]\nmovzx eax, byte ptr [rax]\nmovsx rax, al\nadd rax, rax\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 100h\ntest eax, eax\njz short loc_1290\nmov [rbp+var_10], 1\nmov [rbp+var_14], 1\njmp short loc_1260\nloc_1222:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_14]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 200h\ntest eax, eax\njnz short loc_125C\nmov [rbp+var_10], 0\njmp short loc_1274\nloc_125C:\nadd [rbp+var_14], 1\nloc_1260:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1222\nloc_1274:\ncmp [rbp+var_10], 0\njz short loc_1290\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov edx, eax\nmov eax, [rbp+var_C]\nadd eax, edx\nmov [rbp+var_C], eax\nloc_1290:\nadd [rbp+var_18], 1\nloc_1294:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_2C]\njl loc_11CF\nmov eax, [rbp+var_C]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-18h]\n int j; // [rsp+1Ch] [rbp-14h]\n int v5; // [rsp+20h] [rbp-10h]\n unsigned int v6; // [rsp+24h] [rbp-Ch]\n char *s; // [rsp+28h] [rbp-8h]\n\n v6 = 0;\n for ( i = 0; i < a2; ++i )\n {\n s = *(char **)(8LL * i + a1);\n if ( ((*__ctype_b_loc())[*s] & 0x100) != 0 )\n {\n v5 = 1;\n for ( j = 1; s[j]; ++j )\n {\n if ( ((*__ctype_b_loc())[s[j]] & 0x200) == 0 )\n {\n v5 = 0;\n break;\n }\n }\n if ( v5 )\n v6 += strlen(s);\n }\n }\n return v6;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_C], 0\nmov [rbp+var_18], 0\njmp loc_1294\nloc_11CF:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov [rbp+s], rax\ncall ___ctype_b_loc\nmov rdx, [rax]\nmov rax, [rbp+s]\nmovzx eax, byte ptr [rax]\nmovsx rax, al\nadd rax, rax\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 100h\ntest eax, eax\njz short loc_1290\nmov [rbp+var_10], 1\nmov [rbp+var_14], 1\njmp short loc_1260\nloc_1222:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_14]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 200h\ntest eax, eax\njnz short loc_125C\nmov [rbp+var_10], 0\njmp short loc_1274\nloc_125C:\nadd [rbp+var_14], 1\nloc_1260:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1222\nloc_1274:\ncmp [rbp+var_10], 0\njz short loc_1290\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov edx, eax\nmov eax, [rbp+var_C]\nadd eax, edx\nmov [rbp+var_C], eax\nloc_1290:\nadd [rbp+var_18], 1\nloc_1294:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_2C]\njl loc_11CF\nmov eax, [rbp+var_C]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-18h]\n int j; // [rsp+1Ch] [rbp-14h]\n int v5; // [rsp+20h] [rbp-10h]\n unsigned int v6; // [rsp+24h] [rbp-Ch]\n char *s; // [rsp+28h] [rbp-8h]\n\n v6 = 0;\n for ( i = 0; i < a2; ++i )\n {\n s = *(char **)(8LL * i + a1);\n if ( ((*__ctype_b_loc())[*s] & 0x100) != 0 )\n {\n v5 = 1;\n for ( j = 1; s[j]; ++j )\n {\n if ( ((*__ctype_b_loc())[s[j]] & 0x200) == 0 )\n {\n v5 = 0;\n break;\n }\n }\n if ( v5 )\n v6 += strlen(s);\n }\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(long long a1, int a2) {\n int i;\n int j;\n int v5;\n unsigned int v6;\n char *s;\n v6 = 0;\n for (i = 0; i < a2; ++i) {\n s = *(char **)(8LL * i + a1);\n if (((*__ctype_b_loc())[*s] & 256) != 0) {\n v5 = 1;\n for (j = 1; s[j]; ++j) {\n if (((*__ctype_b_loc())[s[j]] & 512) == 0) {\n v5 = 0;\n break;\n }\n }\n if (v5) v6 += strlen(s);\n }\n }\n return v6;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int i;\n int j;\n int v5;\n unsigned int v6;\n char *s;\n v6 = 0;\n for (i = 0; i < a2; ++i) {\n s = *(char **)(8LL * i + a1);\n if (((*__ctype_b_loc())[*s] & 256) != 0) {\n v5 = 1;\n for (j = 1; s[j]; ++j) {\n if (((*__ctype_b_loc())[s[j]] & 512) == 0) {\n v5 = 0;\n break;\n }\n }\n if (v5) v6 += strlen(s);\n }\n }\n return v6;\n}" + }, + { + "index": 639, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char *sample_names[], int length) {\n int i, j, valid;\n int total_length = 0;\n for (i = 0; i < length; i++) {\n char *name = sample_names[i];\n if (isupper(name[0])) {\n valid = 1;\n for (j = 1; name[j] != '\\0'; j++) {\n if (!islower(name[j])) {\n valid = 0;\n break;\n }\n }\n if (valid) total_length += strlen(name);\n }\n }\n return total_length;\n}", + "test": "int main() {\n\n char *names1[] = {\"sally\", \"Dylan\", \"rebecca\", \"Diana\", \"Joanne\", \"keith\"};\n\n assert(func0(names1, 6) == 16);\n\n\n\n char *names2[] = {\"php\", \"res\", \"Python\", \"abcd\", \"Java\", \"aaa\"};\n\n assert(func0(names2, 6) == 10);\n\n\n\n char *names3[] = {\"abcd\", \"Python\", \"abba\", \"aba\"};\n\n assert(func0(names3, 4) == 6);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11c3 \npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbp\nmov %esi,%ebx\ncallq 1090 <__ctype_b_loc@plt>\nmov (%rax),%r9\nmov %rbp,%r8\nlea -0x1(%rbx),%eax\nlea 0x8(%rbp,%rax,8),%r10\nmov $0x0,%r11d\nmov $0xffffffffffffffff,%rbx\nmov $0x0,%eax\njmp 11e3 \nmov $0x0,%r11d\nmov %r11d,%eax\nretq\nmov %rbx,%rcx\nrepnz scas %es:(%rdi),%al\nnot %rcx\nlea -0x1(%r11,%rcx,1),%r11d\nadd $0x8,%r8\ncmp %r10,%r8\nje 1218 \nmov (%r8),%rdi\nmovsbq (%rdi),%rdx\ntestb $0x1,0x1(%r9,%rdx,2)\nje 11da \nmovzbl 0x1(%rdi),%edx\ntest %dl,%dl\nje 11cd \nlea 0x2(%rdi),%rsi\nmovsbq %dl,%rdx\ntestb $0x2,0x1(%r9,%rdx,2)\nje 11da \nadd $0x1,%rsi\nmovzbl -0x1(%rsi),%edx\ntest %dl,%dl\njne 11fe \njmp 11cd \nmov %r11d,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\ntest esi, esi\njle short loc_1220\nmov r13, rdi\nmov r12d, esi\ncall ___ctype_b_loc\nmov rbp, [rax]\nmov rbx, r13\nmovsxd r12, r12d\nlea r12, [r13+r12*8+0]\nmov r13d, 0\njmp short loc_11ED\nloc_11DC:\ncall _strlen\nadd r13d, eax\nloc_11E4:\nadd rbx, 8\ncmp rbx, r12\njz short loc_1226\nloc_11ED:\nmov rdi, [rbx]; s\nmovsx rax, byte ptr [rdi]\ntest byte ptr [rbp+rax*2+1], 1\njz short loc_11E4\nmovzx eax, byte ptr [rdi+1]\ntest al, al\njz short loc_11DC\nlea rdx, [rdi+2]\nloc_1207:\nmovsx rax, al\ntest byte ptr [rbp+rax*2+1], 2\njz short loc_11E4\nadd rdx, 1\nmovzx eax, byte ptr [rdx-1]\ntest al, al\njnz short loc_1207\njmp short loc_11DC\nloc_1220:\nmov r13d, 0\nloc_1226:\nmov eax, r13d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "__int64 __fastcall func0(char **a1, int a2)\n{\n const unsigned __int16 *v2; // rbp\n char **v3; // rbx\n char **v4; // r12\n unsigned int v5; // r13d\n char *v6; // rdi\n char v7; // al\n char *v8; // rdx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = *__ctype_b_loc();\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n do\n {\n v6 = *v3;\n if ( (v2[**v3] & 0x100) != 0 )\n {\n v7 = v6[1];\n if ( v7 )\n {\n v8 = v6 + 2;\n while ( (v2[v7] & 0x200) != 0 )\n {\n v7 = *v8++;\n if ( !v7 )\n goto LABEL_3;\n }\n }\n else\n {\nLABEL_3:\n v5 += strlen(v6);\n }\n }\n ++v3;\n }\n while ( v3 != v4 );\n }\n return v5;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\ntest esi, esi\njle short loc_1220\nmov r13, rdi\nmov r12d, esi\ncall ___ctype_b_loc\nmov rbp, [rax]\nmov rbx, r13\nmovsxd r12, r12d\nlea r12, [r13+r12*8+0]\nmov r13d, 0\njmp short loc_11ED\nloc_11DC:\ncall _strlen\nadd r13d, eax\nloc_11E4:\nadd rbx, 8\ncmp rbx, r12\njz short loc_1226\nloc_11ED:\nmov rdi, [rbx]; s\nmovsx rax, byte ptr [rdi]\ntest byte ptr [rbp+rax*2+1], 1\njz short loc_11E4\nmovzx eax, byte ptr [rdi+1]\ntest al, al\njz short loc_11DC\nlea rdx, [rdi+2]\nloc_1207:\nmovsx rax, al\ntest byte ptr [rbp+rax*2+1], 2\njz short loc_11E4\nadd rdx, 1\nmovzx eax, byte ptr [rdx-1]\ntest al, al\njnz short loc_1207\njmp short loc_11DC\nloc_1220:\nmov r13d, 0\nloc_1226:\nmov eax, r13d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(char **a1, int a2)\n{\n const unsigned __int16 *v2; // rbp\n char **v3; // rbx\n char **v4; // r12\n unsigned int v5; // r13d\n char *v6; // rdi\n char v7; // al\n char *v8; // rdx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = *__ctype_b_loc();\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n do\n {\n v6 = *v3;\n if ( (v2[**v3] & 0x100) != 0 )\n {\n v7 = v6[1];\n if ( v7 )\n {\n v8 = v6 + 2;\n while ( (v2[v7] & 0x200) != 0 )\n {\n v7 = *v8++;\n if ( !v7 )\n goto LABEL_3;\n }\n }\n else\n {\nLABEL_3:\n v5 += strlen(v6);\n }\n }\n ++v3;\n }\n while ( v3 != v4 );\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(char **a1, int a2) {\n const unsigned short *v2;\n char **v3;\n char **v4;\n unsigned int v5;\n char *v6;\n char v7;\n char *v8;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = *__ctype_b_loc();\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n do {\n v6 = *v3;\n if ((v2[**v3] & 256) != 0) {\n v7 = v6[1];\n if (v7) {\n v8 = v6 + 2;\n while ((v2[v7] & 512) != 0) {\n v7 = *v8++;\n if (!v7) goto LABEL_3;\n }\n } else {\n LABEL_3:\n v5 += strlen(v6);\n }\n }\n ++v3;\n } while (v3 != v4);\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(char **a1, int a2) {\n const unsigned short *v2;\n char **v3;\n char **v4;\n unsigned int v5;\n char *v6;\n char v7;\n char *v8;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = *__ctype_b_loc();\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n do {\n v6 = *v3;\n if ((v2[**v3] & 256) != 0) {\n v7 = v6[1];\n if (v7) {\n v8 = v6 + 2;\n while ((v2[v7] & 512) != 0) {\n v7 = *v8++;\n if (!v7) goto LABEL_3;\n }\n } else {\n LABEL_3:\n v5 += strlen(v6);\n }\n }\n ++v3;\n } while (v3 != v4);\n }\n return v5;\n}" + }, + { + "index": 639, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char *sample_names[], int length) {\n int i, j, valid;\n int total_length = 0;\n for (i = 0; i < length; i++) {\n char *name = sample_names[i];\n if (isupper(name[0])) {\n valid = 1;\n for (j = 1; name[j] != '\\0'; j++) {\n if (!islower(name[j])) {\n valid = 0;\n break;\n }\n }\n if (valid) total_length += strlen(name);\n }\n }\n return total_length;\n}", + "test": "int main() {\n\n char *names1[] = {\"sally\", \"Dylan\", \"rebecca\", \"Diana\", \"Joanne\", \"keith\"};\n\n assert(func0(names1, 6) == 16);\n\n\n\n char *names2[] = {\"php\", \"res\", \"Python\", \"abcd\", \"Java\", \"aaa\"};\n\n assert(func0(names2, 6) == 10);\n\n\n\n char *names3[] = {\"abcd\", \"Python\", \"abba\", \"aba\"};\n\n assert(func0(names3, 4) == 6);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\ntest %esi,%esi\njle 13da \nmov %esi,%r12d\nmov %rdi,%rbx\nxor %r13d,%r13d\ncallq 10b0 <__ctype_b_loc@plt>\nmov (%rax),%rbp\nlea -0x1(%r12),%eax\nlea 0x8(%rbx,%rax,8),%r12\njmp 1389 \nadd $0x8,%rbx\ncmp %rbx,%r12\nje 13cc \nmov (%rbx),%rdi\nmovsbq (%rdi),%rax\ntestb $0x1,0x1(%rbp,%rax,2)\nje 1380 \nmovsbq 0x1(%rdi),%rax\ntest %al,%al\nje 13bb \nlea 0x2(%rdi),%rdx\nnopl 0x0(%rax)\ntestb $0x2,0x1(%rbp,%rax,2)\nje 1380 \nmovsbq (%rdx),%rax\nadd $0x1,%rdx\ntest %al,%al\njne 13a8 \ncallq 1080 \nadd $0x8,%rbx\nadd %eax,%r13d\ncmp %rbx,%r12\njne 1389 \nadd $0x8,%rsp\nmov %r13d,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nadd $0x8,%rsp\nxor %r13d,%r13d\npop %rbx\nmov %r13d,%eax\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\nmovsxd r12, esi\npush rbp\npush rbx\nsub rsp, 8\ntest r12d, r12d\njle short loc_143A\nmov rbx, rdi\nxor r13d, r13d\ncall ___ctype_b_loc\nlea r12, [rbx+r12*8]\nmov rbp, [rax]\njmp short loc_13E9\nloc_13E0:\nadd rbx, 8\ncmp r12, rbx\njz short loc_142C\nloc_13E9:\nmov rdi, [rbx]; s\nmovsx rax, byte ptr [rdi]\ntest byte ptr [rbp+rax*2+1], 1\njz short loc_13E0\nmovsx rax, byte ptr [rdi+1]\ntest al, al\njz short loc_141B\nlea rdx, [rdi+2]\nnop dword ptr [rax+00h]\nloc_1408:\ntest byte ptr [rbp+rax*2+1], 2\njz short loc_13E0\nmovsx rax, byte ptr [rdx]\nadd rdx, 1\ntest al, al\njnz short loc_1408\nloc_141B:\ncall _strlen\nadd rbx, 8\nadd r13d, eax\ncmp r12, rbx\njnz short loc_13E9\nloc_142C:\nadd rsp, 8\nmov eax, r13d\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_143A:\nadd rsp, 8\nxor r13d, r13d\npop rbx\nmov eax, r13d\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "__int64 __fastcall func0(char **a1, int a2)\n{\n char **v2; // rbx\n unsigned int v3; // r13d\n char **v4; // r12\n const unsigned __int16 *v5; // rbp\n char *v6; // rdi\n __int64 v7; // rax\n char *v8; // rdx\n\n if ( a2 > 0 )\n {\n v2 = a1;\n v3 = 0;\n v4 = &a1[a2];\n v5 = *__ctype_b_loc();\n while ( 1 )\n {\n while ( 1 )\n {\n v6 = *v2;\n if ( (v5[**v2] & 0x100) != 0 )\n break;\nLABEL_3:\n if ( v4 == ++v2 )\n return v3;\n }\n v7 = v6[1];\n if ( (_BYTE)v7 )\n {\n v8 = v6 + 2;\n while ( (v5[v7] & 0x200) != 0 )\n {\n v7 = *v8++;\n if ( !(_BYTE)v7 )\n goto LABEL_9;\n }\n goto LABEL_3;\n }\nLABEL_9:\n ++v2;\n v3 += strlen(v6);\n if ( v4 == v2 )\n return v3;\n }\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_13B0:\nendbr64\npush r13\npush r12\nmovsxd r12, esi\npush rbp\npush rbx\nsub rsp, 8\ntest r12d, r12d\njle short loc_143A\nmov rbx, rdi\nxor r13d, r13d\ncall ___ctype_b_loc\nlea r12, [rbx+r12*8]\nmov rbp, [rax]\njmp short loc_13E9\nloc_13E0:\nadd rbx, 8\ncmp r12, rbx\njz short loc_142C\nloc_13E9:\nmov rdi, [rbx]; s\nmovsx rax, byte ptr [rdi]\ntest byte ptr [rbp+rax*2+1], 1\njz short loc_13E0\nmovsx rax, byte ptr [rdi+1]\ntest al, al\njz short loc_141B\nlea rdx, [rdi+2]\nnop dword ptr [rax+00h]\nloc_1408:\ntest byte ptr [rbp+rax*2+1], 2\njz short loc_13E0\nmovsx rax, byte ptr [rdx]\nadd rdx, 1\ntest al, al\njnz short loc_1408\nloc_141B:\ncall _strlen\nadd rbx, 8\nadd r13d, eax\ncmp r12, rbx\njnz short loc_13E9\nloc_142C:\nadd rsp, 8\nmov eax, r13d\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_143A:\nadd rsp, 8\nxor r13d, r13d\npop rbx\nmov eax, r13d\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_13B0(char **a1, int a2)\n{\n char **v2; // rbx\n unsigned int v3; // r13d\n char **v4; // r12\n const unsigned __int16 *v5; // rbp\n char *v6; // rdi\n __int64 v7; // rax\n char *v8; // rdx\n\n if ( a2 > 0 )\n {\n v2 = a1;\n v3 = 0;\n v4 = &a1[a2];\n v5 = *__ctype_b_loc();\n while ( 1 )\n {\n while ( 1 )\n {\n v6 = *v2;\n if ( (v5[**v2] & 0x100) != 0 )\n break;\nLABEL_3:\n if ( v4 == ++v2 )\n return v3;\n }\n v7 = v6[1];\n if ( (_BYTE)v7 )\n {\n v8 = v6 + 2;\n while ( (v5[v7] & 0x200) != 0 )\n {\n v7 = *v8++;\n if ( !(_BYTE)v7 )\n goto LABEL_9;\n }\n goto LABEL_3;\n }\nLABEL_9:\n ++v2;\n v3 += strlen(v6);\n if ( v4 == v2 )\n return v3;\n }\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_13B0(char **a1, int a2) {\n char **v2;\n unsigned int v3;\n char **v4;\n const unsigned short *v5;\n char *v6;\n long long v7;\n char *v8;\n if (a2 > 0) {\n v2 = a1;\n v3 = 0;\n v4 = &a1[a2];\n v5 = *__ctype_b_loc();\n while (1) {\n while (1) {\n v6 = *v2;\n if ((v5[**v2] & 256) != 0) break;\n LABEL_3:\n if (v4 == ++v2) return v3;\n }\n v7 = v6[1];\n if ((uint8_t)v7) {\n v8 = v6 + 2;\n while ((v5[v7] & 512) != 0) {\n v7 = *v8++;\n if (!(uint8_t)v7) goto LABEL_9;\n }\n goto LABEL_3;\n }\n LABEL_9:\n ++v2;\n v3 += strlen(v6);\n if (v4 == v2) return v3;\n }\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(char **a1, int a2) {\n char **v2;\n unsigned int v3;\n char **v4;\n const unsigned short *v5;\n char *v6;\n long long v7;\n char *v8;\n if (a2 > 0) {\n v2 = a1;\n v3 = 0;\n v4 = &a1[a2];\n v5 = *__ctype_b_loc();\n while (1) {\n while (1) {\n v6 = *v2;\n if ((v5[**v2] & 256) != 0) break;\n LABEL_3:\n if (v4 == ++v2) return v3;\n }\n v7 = v6[1];\n if ((uint8_t)v7) {\n v8 = v6 + 2;\n while ((v5[v7] & 512) != 0) {\n v7 = *v8++;\n if (!(uint8_t)v7) goto LABEL_9;\n }\n goto LABEL_3;\n }\n LABEL_9:\n ++v2;\n v3 += strlen(v6);\n if (v4 == v2) return v3;\n }\n }\n return 0LL;\n}" + }, + { + "index": 639, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char *sample_names[], int length) {\n int i, j, valid;\n int total_length = 0;\n for (i = 0; i < length; i++) {\n char *name = sample_names[i];\n if (isupper(name[0])) {\n valid = 1;\n for (j = 1; name[j] != '\\0'; j++) {\n if (!islower(name[j])) {\n valid = 0;\n break;\n }\n }\n if (valid) total_length += strlen(name);\n }\n }\n return total_length;\n}", + "test": "int main() {\n\n char *names1[] = {\"sally\", \"Dylan\", \"rebecca\", \"Diana\", \"Joanne\", \"keith\"};\n\n assert(func0(names1, 6) == 16);\n\n\n\n char *names2[] = {\"php\", \"res\", \"Python\", \"abcd\", \"Java\", \"aaa\"};\n\n assert(func0(names2, 6) == 10);\n\n\n\n char *names3[] = {\"abcd\", \"Python\", \"abba\", \"aba\"};\n\n assert(func0(names3, 4) == 6);\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\ntest %esi,%esi\njle 140a \nmov %esi,%r12d\nmov %rdi,%rbx\nxor %r13d,%r13d\ncallq 10b0 <__ctype_b_loc@plt>\nmov (%rax),%rbp\nlea -0x1(%r12),%eax\nlea 0x8(%rbx,%rax,8),%r12\njmp 13b9 \nadd $0x8,%rbx\ncmp %rbx,%r12\nje 13fc \nmov (%rbx),%rdi\nmovsbq (%rdi),%rax\ntestb $0x1,0x1(%rbp,%rax,2)\nje 13b0 \nmovsbq 0x1(%rdi),%rax\ntest %al,%al\nje 13eb \nlea 0x2(%rdi),%rdx\nnopl 0x0(%rax)\ntestb $0x2,0x1(%rbp,%rax,2)\nje 13b0 \nmovsbq (%rdx),%rax\nadd $0x1,%rdx\ntest %al,%al\njne 13d8 \ncallq 1080 \nadd $0x8,%rbx\nadd %eax,%r13d\ncmp %rbx,%r12\njne 13b9 \nadd $0x8,%rsp\nmov %r13d,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nadd $0x8,%rsp\nxor %r13d,%r13d\npop %rbx\nmov %r13d,%eax\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\nmovsxd r12, esi\npush rbp\npush rbx\nsub rsp, 8\ntest r12d, r12d\njle short loc_143A\nmov rbx, rdi\nxor r13d, r13d\ncall ___ctype_b_loc\nlea r12, [rbx+r12*8]\nmov rbp, [rax]\njmp short loc_13E9\nloc_13E0:\nadd rbx, 8\ncmp r12, rbx\njz short loc_142C\nloc_13E9:\nmov rdi, [rbx]; s\nmovsx rax, byte ptr [rdi]\ntest byte ptr [rbp+rax*2+1], 1\njz short loc_13E0\nmovsx rax, byte ptr [rdi+1]\ntest al, al\njz short loc_141B\nlea rdx, [rdi+2]\nnop dword ptr [rax+00h]\nloc_1408:\ntest byte ptr [rbp+rax*2+1], 2\njz short loc_13E0\nmovsx rax, byte ptr [rdx]\nadd rdx, 1\ntest al, al\njnz short loc_1408\nloc_141B:\ncall _strlen\nadd rbx, 8\nadd r13d, eax\ncmp r12, rbx\njnz short loc_13E9\nloc_142C:\nadd rsp, 8\nmov eax, r13d\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_143A:\nadd rsp, 8\nxor r13d, r13d\npop rbx\nmov eax, r13d\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "__int64 __fastcall func0(char **a1, int a2)\n{\n char **v2; // rbx\n unsigned int v3; // r13d\n char **v4; // r12\n const unsigned __int16 *v5; // rbp\n char *v6; // rdi\n __int64 v7; // rax\n char *v8; // rdx\n\n if ( a2 > 0 )\n {\n v2 = a1;\n v3 = 0;\n v4 = &a1[a2];\n v5 = *__ctype_b_loc();\n while ( 1 )\n {\n while ( 1 )\n {\n v6 = *v2;\n if ( (v5[**v2] & 0x100) != 0 )\n break;\nLABEL_3:\n if ( v4 == ++v2 )\n return v3;\n }\n v7 = v6[1];\n if ( (_BYTE)v7 )\n {\n v8 = v6 + 2;\n while ( (v5[v7] & 0x200) != 0 )\n {\n v7 = *v8++;\n if ( !(_BYTE)v7 )\n goto LABEL_9;\n }\n goto LABEL_3;\n }\nLABEL_9:\n ++v2;\n v3 += strlen(v6);\n if ( v4 == v2 )\n return v3;\n }\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_13B0:\nendbr64\npush r13\npush r12\nmovsxd r12, esi\npush rbp\npush rbx\nsub rsp, 8\ntest r12d, r12d\njle short loc_143A\nmov rbx, rdi\nxor r13d, r13d\ncall ___ctype_b_loc\nlea r12, [rbx+r12*8]\nmov rbp, [rax]\njmp short loc_13E9\nloc_13E0:\nadd rbx, 8\ncmp r12, rbx\njz short loc_142C\nloc_13E9:\nmov rdi, [rbx]; s\nmovsx rax, byte ptr [rdi]\ntest byte ptr [rbp+rax*2+1], 1\njz short loc_13E0\nmovsx rax, byte ptr [rdi+1]\ntest al, al\njz short loc_141B\nlea rdx, [rdi+2]\nnop dword ptr [rax+00h]\nloc_1408:\ntest byte ptr [rbp+rax*2+1], 2\njz short loc_13E0\nmovsx rax, byte ptr [rdx]\nadd rdx, 1\ntest al, al\njnz short loc_1408\nloc_141B:\ncall _strlen\nadd rbx, 8\nadd r13d, eax\ncmp r12, rbx\njnz short loc_13E9\nloc_142C:\nadd rsp, 8\nmov eax, r13d\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_143A:\nadd rsp, 8\nxor r13d, r13d\npop rbx\nmov eax, r13d\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_13B0(char **a1, int a2)\n{\n char **v2; // rbx\n unsigned int v3; // r13d\n char **v4; // r12\n const unsigned __int16 *v5; // rbp\n char *v6; // rdi\n __int64 v7; // rax\n char *v8; // rdx\n\n if ( a2 > 0 )\n {\n v2 = a1;\n v3 = 0;\n v4 = &a1[a2];\n v5 = *__ctype_b_loc();\n while ( 1 )\n {\n while ( 1 )\n {\n v6 = *v2;\n if ( (v5[**v2] & 0x100) != 0 )\n break;\nLABEL_3:\n if ( v4 == ++v2 )\n return v3;\n }\n v7 = v6[1];\n if ( (_BYTE)v7 )\n {\n v8 = v6 + 2;\n while ( (v5[v7] & 0x200) != 0 )\n {\n v7 = *v8++;\n if ( !(_BYTE)v7 )\n goto LABEL_9;\n }\n goto LABEL_3;\n }\nLABEL_9:\n ++v2;\n v3 += strlen(v6);\n if ( v4 == v2 )\n return v3;\n }\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_13B0(char **a1, int a2) {\n char **v2;\n unsigned int v3;\n char **v4;\n const unsigned short *v5;\n char *v6;\n long long v7;\n char *v8;\n if (a2 > 0) {\n v2 = a1;\n v3 = 0;\n v4 = &a1[a2];\n v5 = *__ctype_b_loc();\n while (1) {\n while (1) {\n v6 = *v2;\n if ((v5[**v2] & 256) != 0) break;\n LABEL_3:\n if (v4 == ++v2) return v3;\n }\n v7 = v6[1];\n if ((uint8_t)v7) {\n v8 = v6 + 2;\n while ((v5[v7] & 512) != 0) {\n v7 = *v8++;\n if (!(uint8_t)v7) goto LABEL_9;\n }\n goto LABEL_3;\n }\n LABEL_9:\n ++v2;\n v3 += strlen(v6);\n if (v4 == v2) return v3;\n }\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(char **a1, int a2) {\n char **v2;\n unsigned int v3;\n char **v4;\n const unsigned short *v5;\n char *v6;\n long long v7;\n char *v8;\n if (a2 > 0) {\n v2 = a1;\n v3 = 0;\n v4 = &a1[a2];\n v5 = *__ctype_b_loc();\n while (1) {\n while (1) {\n v6 = *v2;\n if ((v5[**v2] & 256) != 0) break;\n LABEL_3:\n if (v4 == ++v2) return v3;\n }\n v7 = v6[1];\n if ((uint8_t)v7) {\n v8 = v6 + 2;\n while ((v5[v7] & 512) != 0) {\n v7 = *v8++;\n if (!(uint8_t)v7) goto LABEL_9;\n }\n goto LABEL_3;\n }\n LABEL_9:\n ++v2;\n v3 += strlen(v6);\n if (v4 == v2) return v3;\n }\n }\n return 0LL;\n}" + }, + { + "index": 640, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* item) {\n regex_t regex;\n regmatch_t matches[2];\n char* result = (char*)malloc(strlen(item) + 1);\n strcpy(result, item);\n if (regcomp(®ex, \" ?\\\\([^)]+\\\\)\", REG_EXTENDED) == 0) {\n while (regexec(®ex, result, 2, matches, 0) == 0) {\n int start = matches[0].rm_so;\n int end = matches[0].rm_eo;\n memmove(&result[start], &result[end], strlen(result) - end + 1);\n }\n regfree(®ex);\n }\n return result;\n}", + "test": "int main() {\n\n char result[256];\n\n strcpy(result, func0(\"python (chrome)\"));\n\n assert(strcmp(result, \"python\") == 0);\n\n\n\n strcpy(result, func0(\"string(.abc)\"));\n\n assert(strcmp(result, \"string\") == 0);\n\n\n\n strcpy(result, func0(\"alpha(num)\"));\n\n assert(strcmp(result, \"alpha\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nadd $0xffffffffffffff80,%rsp\nmov %rdi,-0x78(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmov -0x78(%rbp),%rax\nmov %rax,%rdi\ncallq 1100 \nadd $0x1,%rax\nmov %rax,%rdi\ncallq 1150 \nmov %rax,-0x68(%rbp)\nmov -0x78(%rbp),%rdx\nmov -0x68(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10e0 \nlea -0x60(%rbp),%rax\nmov $0x1,%edx\nlea 0xd41(%rip),%rsi\nmov %rax,%rdi\ncallq 1130 \ntest %eax,%eax\njne 1351 \njmp 131f \nmov -0x20(%rbp),%eax\nmov %eax,-0x70(%rbp)\nmov -0x1c(%rbp),%eax\nmov %eax,-0x6c(%rbp)\nmov -0x68(%rbp),%rax\nmov %rax,%rdi\ncallq 1100 \nmov -0x6c(%rbp),%edx\nmovslq %edx,%rdx\nsub %rdx,%rax\nlea 0x1(%rax),%rdx\nmov -0x6c(%rbp),%eax\nmovslq %eax,%rcx\nmov -0x68(%rbp),%rax\nadd %rax,%rcx\nmov -0x70(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x68(%rbp),%rax\nadd %rsi,%rax\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 1170 \nlea -0x20(%rbp),%rdx\nmov -0x68(%rbp),%rsi\nlea -0x60(%rbp),%rax\nmov $0x0,%r8d\nmov %rdx,%rcx\nmov $0x2,%edx\nmov %rax,%rdi\ncallq 1160 \ntest %eax,%eax\nje 12d5 \nlea -0x60(%rbp),%rax\nmov %rax,%rdi\ncallq 10f0 \nmov -0x68(%rbp),%rax\nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 1369 \ncallq 1110 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nadd rsp, 0FFFFFFFFFFFFFF80h\nmov [rbp+s], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nadd rax, 1\nmov rdi, rax; size\ncall _malloc\nmov [rbp+dest], rax\nmov rdx, [rbp+s]\nmov rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nlea rcx, pattern; \" ?\\\\([^)]+\\\\)\"\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\ntest eax, eax\njnz loc_135A\njmp short loc_1328\nloc_12DC:\nmov eax, [rbp+pmatch.rm_so]\nmov [rbp+var_70], eax\nmov eax, [rbp+pmatch.rm_eo]\nmov [rbp+var_6C], eax\nmov rax, [rbp+dest]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov eax, [rbp+var_6C]\ncdqe\nsub rdx, rax\nadd rdx, 1; n\nmov eax, [rbp+var_6C]\nmovsxd rcx, eax\nmov rax, [rbp+dest]\nadd rcx, rax\nmov eax, [rbp+var_70]\nmovsxd rsi, eax\nmov rax, [rbp+dest]\nadd rax, rsi\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _memmove\nloc_1328:\nlea rdx, [rbp+pmatch]\nmov rsi, [rbp+dest]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov rcx, rdx; pmatch\nmov edx, 2; nmatch\nmov rdi, rax; preg\ncall _regexec\ntest eax, eax\njz short loc_12DC\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nloc_135A:\nmov rax, [rbp+dest]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1372\ncall ___stack_chk_fail\nlocret_1372:\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(const char *a1)\n{\n size_t v1; // rax\n size_t v2; // rax\n regmatch_t v4; // [rsp+10h] [rbp-70h]\n char *dest; // [rsp+18h] [rbp-68h]\n regex_t preg; // [rsp+20h] [rbp-60h] BYREF\n regmatch_t pmatch; // [rsp+60h] [rbp-20h] BYREF\n unsigned __int64 v8; // [rsp+78h] [rbp-8h]\n\n v8 = __readfsqword(0x28u);\n v1 = strlen(a1);\n dest = (char *)malloc(v1 + 1);\n strcpy(dest, a1);\n if ( !regcomp(&preg, \" ?\\\\([^)]+\\\\)\", 1) )\n {\n while ( !regexec(&preg, dest, 2uLL, &pmatch, 0) )\n {\n v4 = pmatch;\n v2 = strlen(dest);\n memmove(&dest[v4.rm_so], &dest[v4.rm_eo], v2 - v4.rm_eo + 1);\n }\n regfree(&preg);\n }\n return dest;\n}", + "ida_strip_asm": "sub_1269:\nendbr64\npush rbp\nmov rbp, rsp\nadd rsp, 0FFFFFFFFFFFFFF80h\nmov [rbp+s], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nadd rax, 1\nmov rdi, rax; size\ncall _malloc\nmov [rbp+dest], rax\nmov rdx, [rbp+s]\nmov rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nlea rcx, pattern; \" ?\\\\([^)]+\\\\)\"\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\ntest eax, eax\njnz loc_135A\njmp short loc_1328\nloc_12DC:\nmov eax, [rbp+pmatch.rm_so]\nmov [rbp+var_70], eax\nmov eax, [rbp+pmatch.rm_eo]\nmov [rbp+var_6C], eax\nmov rax, [rbp+dest]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov eax, [rbp+var_6C]\ncdqe\nsub rdx, rax\nadd rdx, 1; n\nmov eax, [rbp+var_6C]\nmovsxd rcx, eax\nmov rax, [rbp+dest]\nadd rcx, rax\nmov eax, [rbp+var_70]\nmovsxd rsi, eax\nmov rax, [rbp+dest]\nadd rax, rsi\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _memmove\nloc_1328:\nlea rdx, [rbp+pmatch]\nmov rsi, [rbp+dest]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov rcx, rdx; pmatch\nmov edx, 2; nmatch\nmov rdi, rax; preg\ncall _regexec\ntest eax, eax\njz short loc_12DC\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nloc_135A:\nmov rax, [rbp+dest]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1372\ncall ___stack_chk_fail\nlocret_1372:\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1269(const char *a1)\n{\n size_t v1; // rax\n size_t v2; // rax\n regmatch_t v4; // [rsp+10h] [rbp-70h]\n char *dest; // [rsp+18h] [rbp-68h]\n regex_t preg; // [rsp+20h] [rbp-60h] BYREF\n regmatch_t pmatch; // [rsp+60h] [rbp-20h] BYREF\n unsigned __int64 v8; // [rsp+78h] [rbp-8h]\n\n v8 = __readfsqword(0x28u);\n v1 = strlen(a1);\n dest = (char *)malloc(v1 + 1);\n strcpy(dest, a1);\n if ( !regcomp(&preg, \" ?\\\\([^)]+\\\\)\", 1) )\n {\n while ( !regexec(&preg, dest, 2uLL, &pmatch, 0) )\n {\n v4 = pmatch;\n v2 = strlen(dest);\n memmove(&dest[v4.rm_so], &dest[v4.rm_eo], v2 - v4.rm_eo + 1);\n }\n regfree(&preg);\n }\n return dest;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1269(const char *a1) {\n unsigned int v1;\n unsigned int v2;\n regmatch_t v4;\n char *dest;\n regex_t preg;\n regmatch_t pmatch;\n unsigned long long v8;\n v8 = __readfsqword(40u);\n v1 = strlen(a1);\n dest = (char *)malloc(v1 + 1);\n strcpy(dest, a1);\n if (!regcomp(&preg, \" ?\\\\([^)]+\\\\)\", 1)) {\n while (!regexec(&preg, dest, 2uLL, &pmatch, 0)) {\n v4 = pmatch;\n v2 = strlen(dest);\n memmove(&dest[v4.rm_so], &dest[v4.rm_eo], v2 - v4.rm_eo + 1);\n }\n regfree(&preg);\n }\n return dest;\n}", + "ida_pseudo_norm": "char *func0(const char *a1) {\n unsigned int v1;\n unsigned int v2;\n regmatch_t v4;\n char *dest;\n regex_t preg;\n regmatch_t pmatch;\n unsigned long long v8;\n v8 = __readfsqword(40u);\n v1 = strlen(a1);\n dest = (char *)malloc(v1 + 1);\n strcpy(dest, a1);\n if (!regcomp(&preg, \" ?\\\\([^)]+\\\\)\", 1)) {\n while (!regexec(&preg, dest, 2uLL, &pmatch, 0)) {\n v4 = pmatch;\n v2 = strlen(dest);\n memmove(&dest[v4.rm_so], &dest[v4.rm_eo], v2 - v4.rm_eo + 1);\n }\n regfree(&preg);\n }\n return dest;\n}" + }, + { + "index": 640, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* item) {\n regex_t regex;\n regmatch_t matches[2];\n char* result = (char*)malloc(strlen(item) + 1);\n strcpy(result, item);\n if (regcomp(®ex, \" ?\\\\([^)]+\\\\)\", REG_EXTENDED) == 0) {\n while (regexec(®ex, result, 2, matches, 0) == 0) {\n int start = matches[0].rm_so;\n int end = matches[0].rm_eo;\n memmove(&result[start], &result[end], strlen(result) - end + 1);\n }\n regfree(®ex);\n }\n return result;\n}", + "test": "int main() {\n\n char result[256];\n\n strcpy(result, func0(\"python (chrome)\"));\n\n assert(strcmp(result, \"python\") == 0);\n\n\n\n strcpy(result, func0(\"string(.abc)\"));\n\n assert(strcmp(result, \"string\") == 0);\n\n\n\n strcpy(result, func0(\"alpha(num)\"));\n\n assert(strcmp(result, \"alpha\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x68,%rsp\nmov %rdi,%rbp\nmov %fs:0x28,%rax\nmov %rax,0x58(%rsp)\nxor %eax,%eax\nmov $0xffffffffffffffff,%rcx\nrepnz scas %es:(%rdi),%al\nnot %rcx\nmov %rcx,%rdi\ncallq 1120 \nmov %rax,%rbx\nmov %rbp,%rsi\nmov %rax,%rdi\ncallq 10d0 \nmov %rsp,%rdi\nmov $0x1,%edx\nlea 0xd6d(%rip),%rsi\ncallq 1110 \nlea 0x40(%rsp),%rbp\ntest %eax,%eax\njne 12fb \nmov %rsp,%rdi\nmov $0x0,%r8d\nmov %rbp,%rcx\nmov $0x2,%edx\nmov %rbx,%rsi\ncallq 1130 \ntest %eax,%eax\njne 12f3 \nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nmov %rbx,%rdi\nrepnz scas %es:(%rdi),%al\nnot %rcx\nmovslq 0x44(%rsp),%rsi\nmov %rcx,%rdx\nsub %rsi,%rdx\nadd %rbx,%rsi\nmovslq 0x40(%rsp),%rdi\nadd %rbx,%rdi\ncallq 1150 \njmp 12a5 \nmov %rsp,%rdi\ncallq 10e0 \nmov 0x58(%rsp),%rax\nxor %fs:0x28,%rax\njne 1315 \nmov %rbx,%rax\nadd $0x68,%rsp\npop %rbx\npop %rbp\nretq\ncallq 10f0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 60h\nmov r12, rdi\nmov rax, fs:28h\nmov [rsp+78h+var_20], rax\nxor eax, eax\ncall _strlen\nlea rbp, [rax+1]\nmov rdi, rbp; size\ncall _malloc\nmov rbx, rax\nmov rdx, rbp\nmov rsi, r12\nmov rdi, rax\ncall ___strcpy_chk\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \" ?\\\\([^)]+\\\\)\"\ncall _regcomp\nlea r12, [rsp+78h+pmatch]\ntest eax, eax\njz short loc_1314\nloc_12C7:\nmov rax, [rsp+78h+var_20]\nsub rax, fs:28h\njnz short loc_133B\nmov rax, rbx\nadd rsp, 60h\npop rbx\npop rbp\npop r12\nretn\nloc_12E3:\nmov rdi, rbx; s\ncall _strlen\nmovsxd rsi, [rsp+78h+pmatch.rm_eo]\nmovsxd rdi, [rsp+78h+pmatch.rm_so]\ncmp rbp, rdi\nmov rcx, rdi\ncmovnb rcx, rbp\nsub rcx, rdi\nsub rax, rsi\nlea rdx, [rax+1]\nadd rsi, rbx\nadd rdi, rbx\ncall ___memmove_chk\nloc_1314:\nmov rdi, rsp; preg\nmov r8d, 0; eflags\nmov rcx, r12; pmatch\nmov edx, 2; nmatch\nmov rsi, rbx; string\ncall _regexec\ntest eax, eax\njz short loc_12E3\nmov rdi, rsp; preg\ncall _regfree\njmp short loc_12C7\nloc_133B:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n size_t v1; // rbp\n const char *v2; // rbx\n size_t v4; // rax\n size_t rm_so; // rcx\n regex_t v6; // [rsp+0h] [rbp-78h] BYREF\n regmatch_t pmatch; // [rsp+40h] [rbp-38h] BYREF\n unsigned __int64 v8; // [rsp+58h] [rbp-20h]\n\n v8 = __readfsqword(0x28u);\n v1 = strlen(a1) + 1;\n v2 = (const char *)malloc(v1);\n __strcpy_chk(v2, a1, v1);\n if ( !regcomp(&v6, \" ?\\\\([^)]+\\\\)\", 1) )\n {\n while ( !regexec(&v6, v2, 2uLL, &pmatch, 0) )\n {\n v4 = strlen(v2);\n rm_so = pmatch.rm_so;\n if ( v1 >= pmatch.rm_so )\n rm_so = v1;\n __memmove_chk(&v2[pmatch.rm_so], &v2[pmatch.rm_eo], v4 - pmatch.rm_eo + 1, rm_so - pmatch.rm_so);\n }\n regfree(&v6);\n }\n return v2;\n}", + "ida_strip_asm": "sub_1269:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 60h\nmov r12, rdi\nmov rax, fs:28h\nmov [rsp+78h+var_20], rax\nxor eax, eax\ncall _strlen\nlea rbp, [rax+1]\nmov rdi, rbp; size\ncall _malloc\nmov rbx, rax\nmov rdx, rbp\nmov rsi, r12\nmov rdi, rax\ncall ___strcpy_chk\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \" ?\\\\([^)]+\\\\)\"\ncall _regcomp\nlea r12, [rsp+78h+pmatch]\ntest eax, eax\njz short loc_1314\nloc_12C7:\nmov rax, [rsp+78h+var_20]\nsub rax, fs:28h\njnz short loc_133B\nmov rax, rbx\nadd rsp, 60h\npop rbx\npop rbp\npop r12\nretn\nloc_12E3:\nmov rdi, rbx; s\ncall _strlen\nmovsxd rsi, [rsp+78h+pmatch.rm_eo]\nmovsxd rdi, [rsp+78h+pmatch.rm_so]\ncmp rbp, rdi\nmov rcx, rdi\ncmovnb rcx, rbp\nsub rcx, rdi\nsub rax, rsi\nlea rdx, [rax+1]\nadd rsi, rbx\nadd rdi, rbx\ncall ___memmove_chk\nloc_1314:\nmov rdi, rsp; preg\nmov r8d, 0; eflags\nmov rcx, r12; pmatch\nmov edx, 2; nmatch\nmov rsi, rbx; string\ncall _regexec\ntest eax, eax\njz short loc_12E3\nmov rdi, rsp; preg\ncall _regfree\njmp short loc_12C7\nloc_133B:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_1269(const char *a1)\n{\n size_t v1; // rbp\n const char *v2; // rbx\n size_t v4; // rax\n size_t rm_so; // rcx\n regex_t v6; // [rsp+0h] [rbp-78h] BYREF\n regmatch_t pmatch; // [rsp+40h] [rbp-38h] BYREF\n unsigned __int64 v8; // [rsp+58h] [rbp-20h]\n\n v8 = __readfsqword(0x28u);\n v1 = strlen(a1) + 1;\n v2 = (const char *)malloc(v1);\n __strcpy_chk(v2, a1, v1);\n if ( !regcomp(&v6, \" ?\\\\([^)]+\\\\)\", 1) )\n {\n while ( !regexec(&v6, v2, 2uLL, &pmatch, 0) )\n {\n v4 = strlen(v2);\n rm_so = pmatch.rm_so;\n if ( v1 >= pmatch.rm_so )\n rm_so = v1;\n __memmove_chk(&v2[pmatch.rm_so], &v2[pmatch.rm_eo], v4 - pmatch.rm_eo + 1, rm_so - pmatch.rm_so);\n }\n regfree(&v6);\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1269(const char *a1) {\n unsigned int v1;\n const char *v2;\n unsigned int v4;\n unsigned int rm_so;\n regex_t v6;\n regmatch_t pmatch;\n unsigned long long v8;\n v8 = __readfsqword(40u);\n v1 = strlen(a1) + 1;\n v2 = (const char *)malloc(v1);\n __strcpy_chk(v2, a1, v1);\n if (!regcomp(&v6, \" ?\\\\([^)]+\\\\)\", 1)) {\n while (!regexec(&v6, v2, 2uLL, &pmatch, 0)) {\n v4 = strlen(v2);\n rm_so = pmatch.rm_so;\n if (v1 >= pmatch.rm_so) rm_so = v1;\n __memmove_chk(&v2[pmatch.rm_so], &v2[pmatch.rm_eo], v4 - pmatch.rm_eo + 1,\n rm_so - pmatch.rm_so);\n }\n regfree(&v6);\n }\n return v2;\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n unsigned int v1;\n const char *v2;\n unsigned int v4;\n unsigned int rm_so;\n regex_t v6;\n regmatch_t pmatch;\n unsigned long long v8;\n v8 = __readfsqword(40u);\n v1 = strlen(a1) + 1;\n v2 = (const char *)malloc(v1);\n __strcpy_chk(v2, a1, v1);\n if (!regcomp(&v6, \" ?\\\\([^)]+\\\\)\", 1)) {\n while (!regexec(&v6, v2, 2uLL, &pmatch, 0)) {\n v4 = strlen(v2);\n rm_so = pmatch.rm_so;\n if (v1 >= pmatch.rm_so) rm_so = v1;\n __memmove_chk(&v2[pmatch.rm_so], &v2[pmatch.rm_eo], v4 - pmatch.rm_eo + 1,\n rm_so - pmatch.rm_so);\n }\n regfree(&v6);\n }\n return v2;\n}" + }, + { + "index": 640, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* item) {\n regex_t regex;\n regmatch_t matches[2];\n char* result = (char*)malloc(strlen(item) + 1);\n strcpy(result, item);\n if (regcomp(®ex, \" ?\\\\([^)]+\\\\)\", REG_EXTENDED) == 0) {\n while (regexec(®ex, result, 2, matches, 0) == 0) {\n int start = matches[0].rm_so;\n int end = matches[0].rm_eo;\n memmove(&result[start], &result[end], strlen(result) - end + 1);\n }\n regfree(®ex);\n }\n return result;\n}", + "test": "int main() {\n\n char result[256];\n\n strcpy(result, func0(\"python (chrome)\"));\n\n assert(strcmp(result, \"python\") == 0);\n\n\n\n strcpy(result, func0(\"string(.abc)\"));\n\n assert(strcmp(result, \"string\") == 0);\n\n\n\n strcpy(result, func0(\"alpha(num)\"));\n\n assert(strcmp(result, \"alpha\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\nmov %rdi,%rbp\npush %rbx\nsub $0x68,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x58(%rsp)\nxor %eax,%eax\ncallq 10f0 \nlea 0x1(%rax),%r13\nmov %r13,%rdi\ncallq 1140 \nmov %rbp,%rsi\nmov %r13,%rdx\nmov %rsp,%rbp\nmov %rax,%rdi\nmov %rax,%r12\ncallq 1130 \nmov $0x1,%edx\nlea 0xbf2(%rip),%rsi\nmov %rbp,%rdi\ncallq 1120 \ntest %eax,%eax\njne 14ab \nlea 0x40(%rsp),%r13\nmov $0x1,%ebx\njmp 1489 \nxchg %ax,%ax\nmov %r12,%rdx\nmov (%rdx),%ecx\nadd $0x4,%rdx\nlea -0x1010101(%rcx),%eax\nnot %ecx\nand %ecx,%eax\nand $0x80808080,%eax\nje 1433 \nmov %eax,%ecx\nmovslq 0x40(%rsp),%rdi\nshr $0x10,%ecx\ntest $0x8080,%eax\ncmove %ecx,%eax\nlea 0x2(%rdx),%rcx\ncmove %rcx,%rdx\nmov %eax,%esi\nadd %al,%sil\nmovslq 0x44(%rsp),%rsi\nmov %rbx,%rax\nsbb $0x3,%rdx\nadd %r12,%rdi\nsub %rsi,%rax\nsub %r12,%rdx\nadd %r12,%rsi\nadd %rax,%rdx\ncallq 1170 \nxor %r8d,%r8d\nmov %r13,%rcx\nmov $0x2,%edx\nmov %r12,%rsi\nmov %rbp,%rdi\ncallq 1150 \ntest %eax,%eax\nje 1430 \nmov %rbp,%rdi\ncallq 10e0 \nmov 0x58(%rsp),%rax\nxor %fs:0x28,%rax\njne 14c9 \nadd $0x68,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\ncallq 1100 <__stack_chk_fail@plt>\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 60h\nmov rax, fs:28h\nmov [rsp+88h+var_30], rax\nxor eax, eax\ncall _strlen\nlea rbp, [rax+1]\nmov rdi, rbp; size\ncall _malloc\nmov rsi, r12\nmov rdx, rbp\nmov rcx, rbp\nmov rdi, rax\nmov r12, rsp\nmov rbx, rax\ncall ___memcpy_chk\nmov edx, 1; cflags\nlea rsi, pattern; \" ?\\\\([^)]+\\\\)\"\nmov rdi, r12; preg\ncall _regcomp\ntest eax, eax\njnz short loc_1495\nlea r13, [rsp+88h+pmatch]\nmov r14d, 1\njmp short loc_1473\nloc_1440:\nmov rdi, rbx; s\ncall _strlen\nmovsxd rdi, [rsp+88h+pmatch.rm_so]\nmovsxd rsi, [rsp+88h+pmatch.rm_eo]\nmov rdx, r14\ncmp rbp, rdi\nmov rcx, rdi\ncmovnb rcx, rbp\nsub rdx, rsi\nadd rsi, rbx\nadd rdx, rax\nsub rcx, rdi\nadd rdi, rbx\ncall ___memmove_chk\nloc_1473:\nxor r8d, r8d; eflags\nmov rcx, r13; pmatch\nmov edx, 2; nmatch\nmov rsi, rbx; string\nmov rdi, r12; preg\ncall _regexec\ntest eax, eax\njz short loc_1440\nmov rdi, r12; preg\ncall _regfree\nloc_1495:\nmov rax, [rsp+88h+var_30]\nsub rax, fs:28h\njnz short loc_14B5\nadd rsp, 60h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_14B5:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n size_t v1; // rbp\n const char *v2; // rbx\n size_t v3; // rax\n size_t rm_so; // rcx\n regex_t v6; // [rsp+0h] [rbp-88h] BYREF\n regmatch_t pmatch; // [rsp+40h] [rbp-48h] BYREF\n unsigned __int64 v8; // [rsp+58h] [rbp-30h]\n\n v8 = __readfsqword(0x28u);\n v1 = strlen(a1) + 1;\n v2 = (const char *)malloc(v1);\n __memcpy_chk(v2, a1, v1, v1);\n if ( !regcomp(&v6, \" ?\\\\([^)]+\\\\)\", 1) )\n {\n while ( !regexec(&v6, v2, 2uLL, &pmatch, 0) )\n {\n v3 = strlen(v2);\n rm_so = pmatch.rm_so;\n if ( v1 >= pmatch.rm_so )\n rm_so = v1;\n __memmove_chk(&v2[pmatch.rm_so], &v2[pmatch.rm_eo], v3 + 1LL - pmatch.rm_eo, rm_so - pmatch.rm_so);\n }\n regfree(&v6);\n }\n return v2;\n}", + "ida_strip_asm": "sub_13D0:\nendbr64\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 60h\nmov rax, fs:28h\nmov [rsp+88h+var_30], rax\nxor eax, eax\ncall _strlen\nlea rbp, [rax+1]\nmov rdi, rbp; size\ncall _malloc\nmov rsi, r12\nmov rdx, rbp\nmov rcx, rbp\nmov rdi, rax\nmov r12, rsp\nmov rbx, rax\ncall ___memcpy_chk\nmov edx, 1; cflags\nlea rsi, pattern; \" ?\\\\([^)]+\\\\)\"\nmov rdi, r12; preg\ncall _regcomp\ntest eax, eax\njnz short loc_1495\nlea r13, [rsp+88h+pmatch]\nmov r14d, 1\njmp short loc_1473\nloc_1440:\nmov rdi, rbx; s\ncall _strlen\nmovsxd rdi, [rsp+88h+pmatch.rm_so]\nmovsxd rsi, [rsp+88h+pmatch.rm_eo]\nmov rdx, r14\ncmp rbp, rdi\nmov rcx, rdi\ncmovnb rcx, rbp\nsub rdx, rsi\nadd rsi, rbx\nadd rdx, rax\nsub rcx, rdi\nadd rdi, rbx\ncall ___memmove_chk\nloc_1473:\nxor r8d, r8d; eflags\nmov rcx, r13; pmatch\nmov edx, 2; nmatch\nmov rsi, rbx; string\nmov rdi, r12; preg\ncall _regexec\ntest eax, eax\njz short loc_1440\nmov rdi, r12; preg\ncall _regfree\nloc_1495:\nmov rax, [rsp+88h+var_30]\nsub rax, fs:28h\njnz short loc_14B5\nadd rsp, 60h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_14B5:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_13D0(const char *a1)\n{\n size_t v1; // rbp\n const char *v2; // rbx\n size_t v3; // rax\n size_t rm_so; // rcx\n regex_t v6; // [rsp+0h] [rbp-88h] BYREF\n regmatch_t pmatch; // [rsp+40h] [rbp-48h] BYREF\n unsigned __int64 v8; // [rsp+58h] [rbp-30h]\n\n v8 = __readfsqword(0x28u);\n v1 = strlen(a1) + 1;\n v2 = (const char *)malloc(v1);\n __memcpy_chk(v2, a1, v1, v1);\n if ( !regcomp(&v6, \" ?\\\\([^)]+\\\\)\", 1) )\n {\n while ( !regexec(&v6, v2, 2uLL, &pmatch, 0) )\n {\n v3 = strlen(v2);\n rm_so = pmatch.rm_so;\n if ( v1 >= pmatch.rm_so )\n rm_so = v1;\n __memmove_chk(&v2[pmatch.rm_so], &v2[pmatch.rm_eo], v3 + 1LL - pmatch.rm_eo, rm_so - pmatch.rm_so);\n }\n regfree(&v6);\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_13D0(const char *a1) {\n unsigned int v1;\n const char *v2;\n unsigned int v3;\n unsigned int rm_so;\n regex_t v6;\n regmatch_t pmatch;\n unsigned long long v8;\n v8 = __readfsqword(40u);\n v1 = strlen(a1) + 1;\n v2 = (const char *)malloc(v1);\n __memcpy_chk(v2, a1, v1, v1);\n if (!regcomp(&v6, \" ?\\\\([^)]+\\\\)\", 1)) {\n while (!regexec(&v6, v2, 2uLL, &pmatch, 0)) {\n v3 = strlen(v2);\n rm_so = pmatch.rm_so;\n if (v1 >= pmatch.rm_so) rm_so = v1;\n __memmove_chk(&v2[pmatch.rm_so], &v2[pmatch.rm_eo],\n v3 + 1LL - pmatch.rm_eo, rm_so - pmatch.rm_so);\n }\n regfree(&v6);\n }\n return v2;\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n unsigned int v1;\n const char *v2;\n unsigned int v3;\n unsigned int rm_so;\n regex_t v6;\n regmatch_t pmatch;\n unsigned long long v8;\n v8 = __readfsqword(40u);\n v1 = strlen(a1) + 1;\n v2 = (const char *)malloc(v1);\n __memcpy_chk(v2, a1, v1, v1);\n if (!regcomp(&v6, \" ?\\\\([^)]+\\\\)\", 1)) {\n while (!regexec(&v6, v2, 2uLL, &pmatch, 0)) {\n v3 = strlen(v2);\n rm_so = pmatch.rm_so;\n if (v1 >= pmatch.rm_so) rm_so = v1;\n __memmove_chk(&v2[pmatch.rm_so], &v2[pmatch.rm_eo],\n v3 + 1LL - pmatch.rm_eo, rm_so - pmatch.rm_so);\n }\n regfree(&v6);\n }\n return v2;\n}" + }, + { + "index": 640, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* item) {\n regex_t regex;\n regmatch_t matches[2];\n char* result = (char*)malloc(strlen(item) + 1);\n strcpy(result, item);\n if (regcomp(®ex, \" ?\\\\([^)]+\\\\)\", REG_EXTENDED) == 0) {\n while (regexec(®ex, result, 2, matches, 0) == 0) {\n int start = matches[0].rm_so;\n int end = matches[0].rm_eo;\n memmove(&result[start], &result[end], strlen(result) - end + 1);\n }\n regfree(®ex);\n }\n return result;\n}", + "test": "int main() {\n\n char result[256];\n\n strcpy(result, func0(\"python (chrome)\"));\n\n assert(strcmp(result, \"python\") == 0);\n\n\n\n strcpy(result, func0(\"string(.abc)\"));\n\n assert(strcmp(result, \"string\") == 0);\n\n\n\n strcpy(result, func0(\"alpha(num)\"));\n\n assert(strcmp(result, \"alpha\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\nmov %rdi,%rbp\npush %rbx\nsub $0x68,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x58(%rsp)\nxor %eax,%eax\ncallq 10f0 \nlea 0x1(%rax),%r13\nmov %r13,%rdi\ncallq 1140 \nmov %rbp,%rsi\nmov %r13,%rdx\nmov %rsp,%rbp\nmov %rax,%rdi\nmov %rax,%r12\ncallq 1130 \nmov $0x1,%edx\nlea 0xbf2(%rip),%rsi\nmov %rbp,%rdi\ncallq 1120 \ntest %eax,%eax\njne 14ab \nlea 0x40(%rsp),%r13\nmov $0x1,%ebx\njmp 1489 \nxchg %ax,%ax\nmov %r12,%rdx\nmov (%rdx),%ecx\nadd $0x4,%rdx\nlea -0x1010101(%rcx),%eax\nnot %ecx\nand %ecx,%eax\nand $0x80808080,%eax\nje 1433 \nmov %eax,%ecx\nmovslq 0x40(%rsp),%rdi\nshr $0x10,%ecx\ntest $0x8080,%eax\ncmove %ecx,%eax\nlea 0x2(%rdx),%rcx\ncmove %rcx,%rdx\nmov %eax,%esi\nadd %al,%sil\nmovslq 0x44(%rsp),%rsi\nmov %rbx,%rax\nsbb $0x3,%rdx\nadd %r12,%rdi\nsub %rsi,%rax\nsub %r12,%rdx\nadd %r12,%rsi\nadd %rax,%rdx\ncallq 1170 \nxor %r8d,%r8d\nmov %r13,%rcx\nmov $0x2,%edx\nmov %r12,%rsi\nmov %rbp,%rdi\ncallq 1150 \ntest %eax,%eax\nje 1430 \nmov %rbp,%rdi\ncallq 10e0 \nmov 0x58(%rsp),%rax\nxor %fs:0x28,%rax\njne 14c9 \nadd $0x68,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\ncallq 1100 <__stack_chk_fail@plt>\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 60h\nmov rax, fs:28h\nmov [rsp+88h+var_30], rax\nxor eax, eax\ncall _strlen\nlea rbp, [rax+1]\nmov rdi, rbp; size\ncall _malloc\nmov rsi, r12\nmov rdx, rbp\nmov rcx, rbp\nmov rdi, rax\nmov r12, rsp\nmov rbx, rax\ncall ___memcpy_chk\nmov edx, 1; cflags\nlea rsi, pattern; \" ?\\\\([^)]+\\\\)\"\nmov rdi, r12; preg\ncall _regcomp\ntest eax, eax\njnz short loc_1495\nlea r13, [rsp+88h+pmatch]\nmov r14d, 1\njmp short loc_1473\nloc_1440:\nmov rdi, rbx; s\ncall _strlen\nmovsxd rdi, [rsp+88h+pmatch.rm_so]\nmovsxd rsi, [rsp+88h+pmatch.rm_eo]\nmov rdx, r14\ncmp rbp, rdi\nmov rcx, rdi\ncmovnb rcx, rbp\nsub rdx, rsi\nadd rsi, rbx\nadd rdx, rax\nsub rcx, rdi\nadd rdi, rbx\ncall ___memmove_chk\nloc_1473:\nxor r8d, r8d; eflags\nmov rcx, r13; pmatch\nmov edx, 2; nmatch\nmov rsi, rbx; string\nmov rdi, r12; preg\ncall _regexec\ntest eax, eax\njz short loc_1440\nmov rdi, r12; preg\ncall _regfree\nloc_1495:\nmov rax, [rsp+88h+var_30]\nsub rax, fs:28h\njnz short loc_14B5\nadd rsp, 60h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_14B5:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n size_t v1; // rbp\n const char *v2; // rbx\n size_t v3; // rax\n size_t rm_so; // rcx\n regex_t v6; // [rsp+0h] [rbp-88h] BYREF\n regmatch_t pmatch; // [rsp+40h] [rbp-48h] BYREF\n unsigned __int64 v8; // [rsp+58h] [rbp-30h]\n\n v8 = __readfsqword(0x28u);\n v1 = strlen(a1) + 1;\n v2 = (const char *)malloc(v1);\n __memcpy_chk(v2, a1, v1, v1);\n if ( !regcomp(&v6, \" ?\\\\([^)]+\\\\)\", 1) )\n {\n while ( !regexec(&v6, v2, 2uLL, &pmatch, 0) )\n {\n v3 = strlen(v2);\n rm_so = pmatch.rm_so;\n if ( v1 >= pmatch.rm_so )\n rm_so = v1;\n __memmove_chk(&v2[pmatch.rm_so], &v2[pmatch.rm_eo], v3 + 1LL - pmatch.rm_eo, rm_so - pmatch.rm_so);\n }\n regfree(&v6);\n }\n return v2;\n}", + "ida_strip_asm": "sub_13D0:\nendbr64\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 60h\nmov rax, fs:28h\nmov [rsp+88h+var_30], rax\nxor eax, eax\ncall _strlen\nlea rbp, [rax+1]\nmov rdi, rbp; size\ncall _malloc\nmov rsi, r12\nmov rdx, rbp\nmov rcx, rbp\nmov rdi, rax\nmov r12, rsp\nmov rbx, rax\ncall ___memcpy_chk\nmov edx, 1; cflags\nlea rsi, pattern; \" ?\\\\([^)]+\\\\)\"\nmov rdi, r12; preg\ncall _regcomp\ntest eax, eax\njnz short loc_1495\nlea r13, [rsp+88h+pmatch]\nmov r14d, 1\njmp short loc_1473\nloc_1440:\nmov rdi, rbx; s\ncall _strlen\nmovsxd rdi, [rsp+88h+pmatch.rm_so]\nmovsxd rsi, [rsp+88h+pmatch.rm_eo]\nmov rdx, r14\ncmp rbp, rdi\nmov rcx, rdi\ncmovnb rcx, rbp\nsub rdx, rsi\nadd rsi, rbx\nadd rdx, rax\nsub rcx, rdi\nadd rdi, rbx\ncall ___memmove_chk\nloc_1473:\nxor r8d, r8d; eflags\nmov rcx, r13; pmatch\nmov edx, 2; nmatch\nmov rsi, rbx; string\nmov rdi, r12; preg\ncall _regexec\ntest eax, eax\njz short loc_1440\nmov rdi, r12; preg\ncall _regfree\nloc_1495:\nmov rax, [rsp+88h+var_30]\nsub rax, fs:28h\njnz short loc_14B5\nadd rsp, 60h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_14B5:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_13D0(const char *a1)\n{\n size_t v1; // rbp\n const char *v2; // rbx\n size_t v3; // rax\n size_t rm_so; // rcx\n regex_t v6; // [rsp+0h] [rbp-88h] BYREF\n regmatch_t pmatch; // [rsp+40h] [rbp-48h] BYREF\n unsigned __int64 v8; // [rsp+58h] [rbp-30h]\n\n v8 = __readfsqword(0x28u);\n v1 = strlen(a1) + 1;\n v2 = (const char *)malloc(v1);\n __memcpy_chk(v2, a1, v1, v1);\n if ( !regcomp(&v6, \" ?\\\\([^)]+\\\\)\", 1) )\n {\n while ( !regexec(&v6, v2, 2uLL, &pmatch, 0) )\n {\n v3 = strlen(v2);\n rm_so = pmatch.rm_so;\n if ( v1 >= pmatch.rm_so )\n rm_so = v1;\n __memmove_chk(&v2[pmatch.rm_so], &v2[pmatch.rm_eo], v3 + 1LL - pmatch.rm_eo, rm_so - pmatch.rm_so);\n }\n regfree(&v6);\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_13D0(const char *a1) {\n unsigned int v1;\n const char *v2;\n unsigned int v3;\n unsigned int rm_so;\n regex_t v6;\n regmatch_t pmatch;\n unsigned long long v8;\n v8 = __readfsqword(40u);\n v1 = strlen(a1) + 1;\n v2 = (const char *)malloc(v1);\n __memcpy_chk(v2, a1, v1, v1);\n if (!regcomp(&v6, \" ?\\\\([^)]+\\\\)\", 1)) {\n while (!regexec(&v6, v2, 2uLL, &pmatch, 0)) {\n v3 = strlen(v2);\n rm_so = pmatch.rm_so;\n if (v1 >= pmatch.rm_so) rm_so = v1;\n __memmove_chk(&v2[pmatch.rm_so], &v2[pmatch.rm_eo],\n v3 + 1LL - pmatch.rm_eo, rm_so - pmatch.rm_so);\n }\n regfree(&v6);\n }\n return v2;\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n unsigned int v1;\n const char *v2;\n unsigned int v3;\n unsigned int rm_so;\n regex_t v6;\n regmatch_t pmatch;\n unsigned long long v8;\n v8 = __readfsqword(40u);\n v1 = strlen(a1) + 1;\n v2 = (const char *)malloc(v1);\n __memcpy_chk(v2, a1, v1, v1);\n if (!regcomp(&v6, \" ?\\\\([^)]+\\\\)\", 1)) {\n while (!regexec(&v6, v2, 2uLL, &pmatch, 0)) {\n v3 = strlen(v2);\n rm_so = pmatch.rm_so;\n if (v1 >= pmatch.rm_so) rm_so = v1;\n __memmove_chk(&v2[pmatch.rm_so], &v2[pmatch.rm_eo],\n v3 + 1LL - pmatch.rm_eo, rm_so - pmatch.rm_so);\n }\n regfree(&v6);\n }\n return v2;\n}" + }, + { + "index": 641, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int n) { return (int)(n * (7 * n - 5) / 2); }", + "test": "int main() {\n\n assert(func0(10) == 325);\n\n assert(func0(15) == 750);\n\n assert(func0(18) == 1089);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov -0x4(%rbp),%edx\nmov %edx,%eax\nshl $0x3,%eax\nsub %edx,%eax\nsub $0x5,%eax\nimul -0x4(%rbp),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov edx, [rbp+var_4]\nmov eax, edx\nshl eax, 3\nsub eax, edx\nsub eax, 5\nimul eax, [rbp+var_4]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n return (unsigned int)(a1 * (7 * a1 - 5) / 2);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov edx, [rbp+var_4]\nmov eax, edx\nshl eax, 3\nsub eax, edx\nsub eax, 5\nimul eax, [rbp+var_4]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n return (unsigned int)(a1 * (7 * a1 - 5) / 2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) { return (unsigned int)(a1 * (7 * a1 - 5) / 2); }", + "ida_pseudo_norm": "long long func0(int a1) { return (unsigned int)(a1 * (7 * a1 - 5) / 2); }" + }, + { + "index": 642, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n} Pair;\n\n\n\ntypedef Pair* Sublist;\n\n\n\nint compare_pairs(const void *a, const void *b) {\n\n Pair pa = *(Pair*)a;\n\n Pair pb = *(Pair*)b;\n\n if (pa.first != pb.first) return (pa.first - pb.first);\n\n return (pa.second - pb.second);\n\n}\n\n\n\nSublist sorted_sublist(Sublist sub, int len) {\n\n qsort(sub, len, sizeof(Pair), compare_pairs);\n\n return sub;\n\n}\n\n\n\nint sublist_length(Sublist sub) {\n\n int len = 0;\n\n while (sub[len].first != 0 && sub[len].second != 0) len++;\n\n return len;\n\n}\n\n\n\nbool are_sublists_equal(Sublist a, Sublist b) {\n\n int len_a = sublist_length(a);\n\n int len_b = sublist_length(b);\n\n if (len_a != len_b) return false;\n\n qsort(a, len_a, sizeof(Pair), compare_pairs);\n\n qsort(b, len_b, sizeof(Pair), compare_pairs);\n\n for (int i = 0; i < len_a; i++) {\n\n if (a[i].first != b[i].first || a[i].second != b[i].second) {\n\n return false;\n\n }\n\n }\n\n return true;\n\n}\n\n\n\n", + "func": "void func0(Sublist *test_list, int num_lists, Sublist *result,\n int *result_size) {\n int added = 0;\n for (int i = 0; i < num_lists; i++) {\n Sublist current =\n sorted_sublist(test_list[i], sublist_length(test_list[i]));\n bool found = false;\n for (int j = 0; j < added; j++) {\n if (are_sublists_equal(result[j], current)) {\n found = true;\n break;\n }\n }\n if (!found) {\n result[added++] = current;\n }\n }\n *result_size = added;\n}", + "test": "int main() {\n\n Pair list1[] = {{4, 5}, {3, 2}, {0, 0}};\n\n Pair list2[] = {{2, 2}, {4, 6}, {0, 0}};\n\n Pair list3[] = {{3, 2}, {4, 5}, {0, 0}};\n\n Sublist test_list1[] = {list1, list2, list3};\n\n Sublist result1[3];\n\n int result1_size = 0;\n\n\n\n func0(test_list1, 3, result1, &result1_size);\n\n assert(result1_size == 2);\n\n\n\n Pair list4[] = {{5, 6}, {4, 3}, {0, 0}};\n\n Pair list5[] = {{3, 3}, {5, 7}, {0, 0}};\n\n Pair list6[] = {{4, 3}, {5, 6}, {0, 0}};\n\n Sublist test_list2[] = {list4, list5, list6};\n\n Sublist result2[3];\n\n int result2_size = 0;\n\n\n\n func0(test_list2, 3, result2, &result2_size);\n\n assert(result2_size == 2);\n\n\n\n Pair list7[] = {{6, 7}, {5, 4}, {0, 0}};\n\n Pair list8[] = {{4, 4}, {6, 8}, {0, 0}};\n\n Pair list9[] = {{5, 4}, {6, 7}, {0, 0}};\n\n Sublist test_list3[] = {list7, list8, list9};\n\n Sublist result3[3];\n\n int result3_size = 0;\n\n\n\n func0(test_list3, 3, result3, &result3_size);\n\n assert(result3_size == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x40,%rsp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmov %rdx,-0x38(%rbp)\nmov %rcx,-0x40(%rbp)\nmovl $0x0,-0x14(%rbp)\nmovl $0x0,-0x10(%rbp)\njmpq 144d \nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov %rax,%rdi\ncallq 1208 \nmov %eax,%edx\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%rax\nmov %edx,%esi\nmov %rax,%rdi\ncallq 11d1 \nmov %rax,-0x8(%rbp)\nmovb $0x0,-0x15(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 1415 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0x8(%rbp),%rdx\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 125b \ntest %al,%al\nje 1411 \nmovb $0x1,-0x15(%rbp)\njmp 141d \naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x14(%rbp),%eax\njl 13e1 \nmovzbl -0x15(%rbp),%eax\nxor $0x1,%eax\ntest %al,%al\nje 1449 \nmov -0x14(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x14(%rbp)\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x38(%rbp),%rax\nadd %rax,%rdx\nmov -0x8(%rbp),%rax\nmov %rax,(%rdx)\naddl $0x1,-0x10(%rbp)\nmov -0x10(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 138e \nmov -0x40(%rbp),%rax\nmov -0x14(%rbp),%edx\nmov %edx,(%rax)\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmov [rbp+var_40], rcx\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\njmp loc_1452\nloc_1393:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax\ncall sublist_length\nmov edx, eax\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov rax, [rax]\nmov esi, edx\nmov rdi, rax\ncall sorted_sublist\nmov [rbp+var_8], rax\nmov [rbp+var_15], 0\nmov [rbp+var_C], 0\njmp short loc_141A\nloc_13E6:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nmov rdx, [rbp+var_8]\nmov rsi, rdx\nmov rdi, rax\ncall are_sublists_equal\ntest al, al\njz short loc_1416\nmov [rbp+var_15], 1\njmp short loc_1422\nloc_1416:\nadd [rbp+var_C], 1\nloc_141A:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_14]\njl short loc_13E6\nloc_1422:\nmovzx eax, [rbp+var_15]\nxor eax, 1\ntest al, al\njz short loc_144E\nmov eax, [rbp+var_14]\nlea edx, [rax+1]\nmov [rbp+var_14], edx\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rdx, rax\nmov rax, [rbp+var_8]\nmov [rdx], rax\nloc_144E:\nadd [rbp+var_10], 1\nloc_1452:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_2C]\njl loc_1393\nmov rax, [rbp+var_40]\nmov edx, [rbp+var_14]\nmov [rax], edx\nnop\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, __int64 a3, _DWORD *a4)\n{\n unsigned int v4; // eax\n int v5; // eax\n _DWORD *result; // rax\n char v9; // [rsp+2Bh] [rbp-15h]\n int v10; // [rsp+2Ch] [rbp-14h]\n int i; // [rsp+30h] [rbp-10h]\n int j; // [rsp+34h] [rbp-Ch]\n __int64 v13; // [rsp+38h] [rbp-8h]\n\n v10 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v4 = sublist_length(*(_QWORD *)(8LL * i + a1));\n v13 = sorted_sublist(*(_QWORD *)(8LL * i + a1), v4);\n v9 = 0;\n for ( j = 0; j < v10; ++j )\n {\n if ( (unsigned __int8)are_sublists_equal(*(_QWORD *)(8LL * j + a3), v13) )\n {\n v9 = 1;\n break;\n }\n }\n if ( v9 != 1 )\n {\n v5 = v10++;\n *(_QWORD *)(a3 + 8LL * v5) = v13;\n }\n }\n result = a4;\n *a4 = v10;\n return result;\n}", + "ida_strip_asm": "sub_1365:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmov [rbp+var_40], rcx\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\njmp loc_1452\nloc_1393:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax\ncall sub_1207\nmov edx, eax\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov rax, [rax]\nmov esi, edx\nmov rdi, rax\ncall sub_11CD\nmov [rbp+var_8], rax\nmov [rbp+var_15], 0\nmov [rbp+var_C], 0\njmp short loc_141A\nloc_13E6:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nmov rdx, [rbp+var_8]\nmov rsi, rdx\nmov rdi, rax\ncall sub_125A\ntest al, al\njz short loc_1416\nmov [rbp+var_15], 1\njmp short loc_1422\nloc_1416:\nadd [rbp+var_C], 1\nloc_141A:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_14]\njl short loc_13E6\nloc_1422:\nmovzx eax, [rbp+var_15]\nxor eax, 1\ntest al, al\njz short loc_144E\nmov eax, [rbp+var_14]\nlea edx, [rax+1]\nmov [rbp+var_14], edx\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rdx, rax\nmov rax, [rbp+var_8]\nmov [rdx], rax\nloc_144E:\nadd [rbp+var_10], 1\nloc_1452:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_2C]\njl loc_1393\nmov rax, [rbp+var_40]\nmov edx, [rbp+var_14]\nmov [rax], edx\nnop\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1365(__int64 a1, int a2, __int64 a3, _DWORD *a4)\n{\n unsigned int v4; // eax\n int v5; // eax\n _DWORD *result; // rax\n char v9; // [rsp+2Bh] [rbp-15h]\n int v10; // [rsp+2Ch] [rbp-14h]\n int i; // [rsp+30h] [rbp-10h]\n int j; // [rsp+34h] [rbp-Ch]\n __int64 v13; // [rsp+38h] [rbp-8h]\n\n v10 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v4 = sub_1207(*(_QWORD *)(8LL * i + a1));\n v13 = sub_11CD(*(_QWORD *)(8LL * i + a1), v4);\n v9 = 0;\n for ( j = 0; j < v10; ++j )\n {\n if ( (unsigned __int8)sub_125A(*(_QWORD *)(8LL * j + a3), v13) )\n {\n v9 = 1;\n break;\n }\n }\n if ( v9 != 1 )\n {\n v5 = v10++;\n *(_QWORD *)(a3 + 8LL * v5) = v13;\n }\n }\n result = a4;\n *a4 = v10;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1365(long long a1, int a2, long long a3, uint32_t *a4) {\n unsigned int v4;\n int v5;\n uint32_t *result;\n char v9;\n int v10;\n int i;\n int j;\n long long v13;\n v10 = 0;\n for (i = 0; i < a2; ++i) {\n v4 = sub_1207(*(uint64_t *)(8LL * i + a1));\n v13 = sub_11CD(*(uint64_t *)(8LL * i + a1), v4);\n v9 = 0;\n for (j = 0; j < v10; ++j) {\n if ((unsigned char)sub_125A(*(uint64_t *)(8LL * j + a3), v13)) {\n v9 = 1;\n break;\n }\n }\n if (v9 != 1) {\n v5 = v10++;\n *(uint64_t *)(a3 + 8LL * v5) = v13;\n }\n }\n result = a4;\n *a4 = v10;\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, long long a3, uint32_t *a4) {\n unsigned int v4;\n int v5;\n uint32_t *result;\n char v9;\n int v10;\n int i;\n int j;\n long long v13;\n v10 = 0;\n for (i = 0; i < a2; ++i) {\n v4 = sublist_length(*(uint64_t *)(8LL * i + a1));\n v13 = sorted_sublist(*(uint64_t *)(8LL * i + a1), v4);\n v9 = 0;\n for (j = 0; j < v10; ++j) {\n if ((unsigned char)are_sublists_equal(*(uint64_t *)(8LL * j + a3), v13)) {\n v9 = 1;\n break;\n }\n }\n if (v9 != 1) {\n v5 = v10++;\n *(uint64_t *)(a3 + 8LL * v5) = v13;\n }\n }\n result = a4;\n *a4 = v10;\n return result;\n}" + }, + { + "index": 642, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n} Pair;\n\n\n\ntypedef Pair* Sublist;\n\n\n\nint compare_pairs(const void *a, const void *b) {\n\n Pair pa = *(Pair*)a;\n\n Pair pb = *(Pair*)b;\n\n if (pa.first != pb.first) return (pa.first - pb.first);\n\n return (pa.second - pb.second);\n\n}\n\n\n\nSublist sorted_sublist(Sublist sub, int len) {\n\n qsort(sub, len, sizeof(Pair), compare_pairs);\n\n return sub;\n\n}\n\n\n\nint sublist_length(Sublist sub) {\n\n int len = 0;\n\n while (sub[len].first != 0 && sub[len].second != 0) len++;\n\n return len;\n\n}\n\n\n\nbool are_sublists_equal(Sublist a, Sublist b) {\n\n int len_a = sublist_length(a);\n\n int len_b = sublist_length(b);\n\n if (len_a != len_b) return false;\n\n qsort(a, len_a, sizeof(Pair), compare_pairs);\n\n qsort(b, len_b, sizeof(Pair), compare_pairs);\n\n for (int i = 0; i < len_a; i++) {\n\n if (a[i].first != b[i].first || a[i].second != b[i].second) {\n\n return false;\n\n }\n\n }\n\n return true;\n\n}\n\n\n\n", + "func": "void func0(Sublist *test_list, int num_lists, Sublist *result,\n int *result_size) {\n int added = 0;\n for (int i = 0; i < num_lists; i++) {\n Sublist current =\n sorted_sublist(test_list[i], sublist_length(test_list[i]));\n bool found = false;\n for (int j = 0; j < added; j++) {\n if (are_sublists_equal(result[j], current)) {\n found = true;\n break;\n }\n }\n if (!found) {\n result[added++] = current;\n }\n }\n *result_size = added;\n}", + "test": "int main() {\n\n Pair list1[] = {{4, 5}, {3, 2}, {0, 0}};\n\n Pair list2[] = {{2, 2}, {4, 6}, {0, 0}};\n\n Pair list3[] = {{3, 2}, {4, 5}, {0, 0}};\n\n Sublist test_list1[] = {list1, list2, list3};\n\n Sublist result1[3];\n\n int result1_size = 0;\n\n\n\n func0(test_list1, 3, result1, &result1_size);\n\n assert(result1_size == 2);\n\n\n\n Pair list4[] = {{5, 6}, {4, 3}, {0, 0}};\n\n Pair list5[] = {{3, 3}, {5, 7}, {0, 0}};\n\n Pair list6[] = {{4, 3}, {5, 6}, {0, 0}};\n\n Sublist test_list2[] = {list4, list5, list6};\n\n Sublist result2[3];\n\n int result2_size = 0;\n\n\n\n func0(test_list2, 3, result2, &result2_size);\n\n assert(result2_size == 2);\n\n\n\n Pair list7[] = {{6, 7}, {5, 4}, {0, 0}};\n\n Pair list8[] = {{4, 4}, {6, 8}, {0, 0}};\n\n Pair list9[] = {{5, 4}, {6, 7}, {0, 0}};\n\n Sublist test_list3[] = {list7, list8, list9};\n\n Sublist result3[3];\n\n int result3_size = 0;\n\n\n\n func0(test_list3, 3, result3, &result3_size);\n\n assert(result3_size == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x28,%rsp\nmov %rcx,0x18(%rsp)\ntest %esi,%esi\njle 12e0 \nmov %rdx,%r15\nmov %rdi,%r13\nlea -0x1(%rsi),%eax\nlea 0x8(%rdi,%rax,8),%rax\nmov %rax,0x8(%rsp)\nmov $0x0,%r14d\nlea 0x8(%rdx),%rax\nmov %rax,0x10(%rsp)\njmp 1313 \nmov $0x0,%r14d\nmov 0x18(%rsp),%rax\nmov %r14d,(%rax)\nadd $0x28,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmovslq %r14d,%rax\nmov %rbp,(%r15,%rax,8)\nlea 0x1(%r14),%r14d\nadd $0x8,%r13\ncmp 0x8(%rsp),%r13\nje 12e6 \nmov 0x0(%r13),%rbx\nmov %rbx,%rdi\ncallq 11c2 \nmov %eax,%esi\nmov %rbx,%rdi\ncallq 11a1 \nmov %rax,%rbp\ntest %r14d,%r14d\njle 12fd \nmov %r15,%rbx\nlea -0x1(%r14),%eax\nmov 0x10(%rsp),%rdx\nlea (%rdx,%rax,8),%r12\nmov %rbp,%rsi\nmov (%rbx),%rdi\ncallq 11e9 \ntest %al,%al\njne 1308 \nadd $0x8,%rbx\ncmp %r12,%rbx\njne 1341 \njmp 12fd \n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rcx\ntest esi, esi\njle short loc_1339\nmov r15, rdx\nmov r13, rdi\nmovsxd rsi, esi\nlea rax, [rdi+rsi*8]\nmov [rsp+48h+var_48], rax\nmov r14d, 0\njmp short loc_12F7\nloc_12DF:\nmovsxd rax, r14d\nmov [r15+rax*8], rbp\nlea r14d, [r14+1]\nloc_12EA:\nadd r13, 8\nmov rax, [rsp+48h+var_48]\ncmp r13, rax\njz short loc_133F\nloc_12F7:\nmov rbx, [r13+0]\nmov rdi, rbx\ncall sublist_length\nmov esi, eax\nmov rdi, rbx\ncall sorted_sublist\nmov rbp, rax\ntest r14d, r14d\njle short loc_12DF\nmov rbx, r15\nmovsxd rax, r14d\nlea r12, [r15+rax*8]\nloc_131F:\nmov rdi, [rbx]; base\nmov rsi, rbp; void *\ncall are_sublists_equal\ntest al, al\njnz short loc_12EA\nadd rbx, 8\ncmp rbx, r12\njnz short loc_131F\njmp short loc_12DF\nloc_1339:\nmov r14d, 0\nloc_133F:\nmov rax, [rsp+48h+var_40]\nmov [rax], r14d\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "int *__fastcall func0(_QWORD *a1, int a2, void **a3, int *a4)\n{\n _QWORD *v5; // r13\n int v6; // r14d\n __int64 v7; // rbx\n unsigned int v8; // eax\n void *v9; // rbp\n void **v10; // rbx\n int *result; // rax\n\n if ( a2 <= 0 )\n {\n v6 = 0;\n }\n else\n {\n v5 = a1;\n v6 = 0;\n do\n {\n v7 = *v5;\n v8 = sublist_length(*v5);\n v9 = (void *)sorted_sublist(v7, v8);\n if ( v6 <= 0 )\n {\nLABEL_3:\n a3[v6++] = v9;\n }\n else\n {\n v10 = a3;\n while ( !(unsigned __int8)are_sublists_equal(*v10, v9) )\n {\n if ( ++v10 == &a3[v6] )\n goto LABEL_3;\n }\n }\n ++v5;\n }\n while ( v5 != &a1[a2] );\n }\n result = a4;\n *a4 = v6;\n return result;\n}", + "ida_strip_asm": "sub_12AB:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rcx\ntest esi, esi\njle short loc_1339\nmov r15, rdx\nmov r13, rdi\nmovsxd rsi, esi\nlea rax, [rdi+rsi*8]\nmov [rsp+48h+var_48], rax\nmov r14d, 0\njmp short loc_12F7\nloc_12DF:\nmovsxd rax, r14d\nmov [r15+rax*8], rbp\nlea r14d, [r14+1]\nloc_12EA:\nadd r13, 8\nmov rax, [rsp+48h+var_48]\ncmp r13, rax\njz short loc_133F\nloc_12F7:\nmov rbx, [r13+0]\nmov rdi, rbx\ncall sub_11C0\nmov esi, eax\nmov rdi, rbx\ncall sub_119F\nmov rbp, rax\ntest r14d, r14d\njle short loc_12DF\nmov rbx, r15\nmovsxd rax, r14d\nlea r12, [r15+rax*8]\nloc_131F:\nmov rdi, [rbx]; base\nmov rsi, rbp; void *\ncall sub_11E7\ntest al, al\njnz short loc_12EA\nadd rbx, 8\ncmp rbx, r12\njnz short loc_131F\njmp short loc_12DF\nloc_1339:\nmov r14d, 0\nloc_133F:\nmov rax, [rsp+48h+var_40]\nmov [rax], r14d\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "int *__fastcall sub_12AB(_QWORD *a1, int a2, void **a3, int *a4)\n{\n _QWORD *v5; // r13\n int v6; // r14d\n __int64 v7; // rbx\n unsigned int v8; // eax\n void *v9; // rbp\n void **v10; // rbx\n int *result; // rax\n\n if ( a2 <= 0 )\n {\n v6 = 0;\n }\n else\n {\n v5 = a1;\n v6 = 0;\n do\n {\n v7 = *v5;\n v8 = sub_11C0(*v5);\n v9 = (void *)sub_119F(v7, v8);\n if ( v6 <= 0 )\n {\nLABEL_3:\n a3[v6++] = v9;\n }\n else\n {\n v10 = a3;\n while ( !(unsigned __int8)sub_11E7(*v10, v9) )\n {\n if ( ++v10 == &a3[v6] )\n goto LABEL_3;\n }\n }\n ++v5;\n }\n while ( v5 != &a1[a2] );\n }\n result = a4;\n *a4 = v6;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "int *sub_12AB(uint64_t *a1, int a2, void **a3, int *a4) {\n uint64_t *v5;\n int v6;\n long long v7;\n unsigned int v8;\n void *v9;\n void **v10;\n int *result;\n if (a2 <= 0) {\n v6 = 0;\n } else {\n v5 = a1;\n v6 = 0;\n do {\n v7 = *v5;\n v8 = sub_11C0(*v5);\n v9 = (void *)sub_119F(v7, v8);\n if (v6 <= 0) {\n LABEL_3:\n a3[v6++] = v9;\n } else {\n v10 = a3;\n while (!(unsigned char)sub_11E7(*v10, v9)) {\n if (++v10 == &a3[v6]) goto LABEL_3;\n }\n }\n ++v5;\n } while (v5 != &a1[a2]);\n }\n result = a4;\n *a4 = v6;\n return result;\n}", + "ida_pseudo_norm": "int *func0(uint64_t *a1, int a2, void **a3, int *a4) {\n uint64_t *v5;\n int v6;\n long long v7;\n unsigned int v8;\n void *v9;\n void **v10;\n int *result;\n if (a2 <= 0) {\n v6 = 0;\n } else {\n v5 = a1;\n v6 = 0;\n do {\n v7 = *v5;\n v8 = sublist_length(*v5);\n v9 = (void *)sorted_sublist(v7, v8);\n if (v6 <= 0) {\n LABEL_3:\n a3[v6++] = v9;\n } else {\n v10 = a3;\n while (!(unsigned char)are_sublists_equal(*v10, v9)) {\n if (++v10 == &a3[v6]) goto LABEL_3;\n }\n }\n ++v5;\n } while (v5 != &a1[a2]);\n }\n result = a4;\n *a4 = v6;\n return result;\n}" + }, + { + "index": 642, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n} Pair;\n\n\n\ntypedef Pair* Sublist;\n\n\n\nint compare_pairs(const void *a, const void *b) {\n\n Pair pa = *(Pair*)a;\n\n Pair pb = *(Pair*)b;\n\n if (pa.first != pb.first) return (pa.first - pb.first);\n\n return (pa.second - pb.second);\n\n}\n\n\n\nSublist sorted_sublist(Sublist sub, int len) {\n\n qsort(sub, len, sizeof(Pair), compare_pairs);\n\n return sub;\n\n}\n\n\n\nint sublist_length(Sublist sub) {\n\n int len = 0;\n\n while (sub[len].first != 0 && sub[len].second != 0) len++;\n\n return len;\n\n}\n\n\n\nbool are_sublists_equal(Sublist a, Sublist b) {\n\n int len_a = sublist_length(a);\n\n int len_b = sublist_length(b);\n\n if (len_a != len_b) return false;\n\n qsort(a, len_a, sizeof(Pair), compare_pairs);\n\n qsort(b, len_b, sizeof(Pair), compare_pairs);\n\n for (int i = 0; i < len_a; i++) {\n\n if (a[i].first != b[i].first || a[i].second != b[i].second) {\n\n return false;\n\n }\n\n }\n\n return true;\n\n}\n\n\n\n", + "func": "void func0(Sublist *test_list, int num_lists, Sublist *result,\n int *result_size) {\n int added = 0;\n for (int i = 0; i < num_lists; i++) {\n Sublist current =\n sorted_sublist(test_list[i], sublist_length(test_list[i]));\n bool found = false;\n for (int j = 0; j < added; j++) {\n if (are_sublists_equal(result[j], current)) {\n found = true;\n break;\n }\n }\n if (!found) {\n result[added++] = current;\n }\n }\n *result_size = added;\n}", + "test": "int main() {\n\n Pair list1[] = {{4, 5}, {3, 2}, {0, 0}};\n\n Pair list2[] = {{2, 2}, {4, 6}, {0, 0}};\n\n Pair list3[] = {{3, 2}, {4, 5}, {0, 0}};\n\n Sublist test_list1[] = {list1, list2, list3};\n\n Sublist result1[3];\n\n int result1_size = 0;\n\n\n\n func0(test_list1, 3, result1, &result1_size);\n\n assert(result1_size == 2);\n\n\n\n Pair list4[] = {{5, 6}, {4, 3}, {0, 0}};\n\n Pair list5[] = {{3, 3}, {5, 7}, {0, 0}};\n\n Pair list6[] = {{4, 3}, {5, 6}, {0, 0}};\n\n Sublist test_list2[] = {list4, list5, list6};\n\n Sublist result2[3];\n\n int result2_size = 0;\n\n\n\n func0(test_list2, 3, result2, &result2_size);\n\n assert(result2_size == 2);\n\n\n\n Pair list7[] = {{6, 7}, {5, 4}, {0, 0}};\n\n Pair list8[] = {{4, 4}, {6, 8}, {0, 0}};\n\n Pair list9[] = {{5, 4}, {6, 7}, {0, 0}};\n\n Sublist test_list3[] = {list7, list8, list9};\n\n Sublist result3[3];\n\n int result3_size = 0;\n\n\n\n func0(test_list3, 3, result3, &result3_size);\n\n assert(result3_size == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x28,%rsp\nmov %rcx,0x18(%rsp)\ntest %esi,%esi\njle 1755 \nlea -0x1(%rsi),%eax\nmov %rdx,%r13\nmov %rdi,%rbp\nxor %r12d,%r12d\nlea 0x8(%rdi,%rax,8),%rax\nmov %rax,0x8(%rsp)\nlea 0x8(%rdx),%rax\nmov %rax,0x10(%rsp)\nxchg %ax,%ax\nmov 0x0(%rbp),%r14\nxor %esi,%esi\nmov (%r14),%ecx\ntest %ecx,%ecx\njne 16bc \njmp 16c5 \nadd $0x1,%rsi\nmov (%r14,%rsi,8),%edx\ntest %edx,%edx\nje 16c5 \nmov 0x4(%r14,%rsi,8),%eax\ntest %eax,%eax\njne 16b0 \nlea -0x22c(%rip),%rcx\nmov $0x8,%edx\nmov %r14,%rdi\ncallq 1070 \ntest %r12d,%r12d\nje 1738 \nmov 0x10(%rsp),%rdx\nlea -0x1(%r12),%eax\nmov %r13,%r15\nlea (%rdx,%rax,8),%rbx\njmp 1701 \nnopl 0x0(%rax)\nadd $0x8,%r15\ncmp %rbx,%r15\nje 1738 \nmov (%r15),%rdi\nmov %r14,%rsi\ncallq 1520 \ntest %al,%al\nje 16f8 \nadd $0x8,%rbp\ncmp 0x8(%rsp),%rbp\njne 16a0 \nmov 0x18(%rsp),%rax\nmov %r12d,(%rax)\nadd $0x28,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw 0x0(%rax,%rax,1)\nmovslq %r12d,%rax\nadd $0x8,%rbp\nadd $0x1,%r12d\nmov %r14,0x0(%r13,%rax,8)\ncmp 0x8(%rsp),%rbp\njne 16a0 \njmp 171b \nxor %r12d,%r12d\njmp 171b \nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov [rsp+58h+var_50], rdx\nmov [rsp+58h+var_40], rcx\ntest esi, esi\njle loc_1731\nmovsxd rsi, esi\nmov rbp, rdi\nxor r12d, r12d\nlea rax, [rdi+rsi*8]\nmov [rsp+58h+var_48], rax\nnop word ptr [rax+rax+00000000h]\nloc_1670:\nmov r15, [rbp+0]\nxor esi, esi\nmov ecx, [r15]\ntest ecx, ecx\njnz short loc_168C\njmp short loc_1695\nloc_1680:\nadd rsi, 1; nmemb\nmov edx, [r15+rsi*8]\ntest edx, edx\njz short loc_1695\nloc_168C:\nmov eax, [r15+rsi*8+4]\ntest eax, eax\njnz short loc_1680\nloc_1695:\nlea rcx, compare_pairs; compar\nmov edx, 8; size\nmov rdi, r15; base\nmovsxd r14, r12d\ncall _qsort\ntest r12d, r12d\njle short loc_1710\nmov rax, [rsp+58h+var_50]\nmovsxd r14, r12d\nmov r13, rax\nlea rbx, [rax+r14*8]\njmp short loc_16D1\nloc_16C8:\nadd r13, 8\ncmp r13, rbx\njz short loc_1710\nloc_16D1:\nmov rdi, [r13+0]; base\nmov rsi, r15; void *\ncall are_sublists_equal\ntest al, al\njz short loc_16C8\nmov rax, [rsp+58h+var_48]\nadd rbp, 8\ncmp rbp, rax\njnz short loc_1670\nloc_16EF:\nmov rax, [rsp+58h+var_40]\nmov [rax], r12d\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1710:\nmov rax, [rsp+58h+var_50]\nadd rbp, 8\nadd r12d, 1\nmov [rax+r14*8], r15\nmov rax, [rsp+58h+var_48]\ncmp rbp, rax\njnz loc_1670\njmp short loc_16EF\nloc_1731:\nxor r12d, r12d\njmp short loc_16EF", + "ida_pseudo": "int *__fastcall func0(void **a1, int a2, void **a3, int *a4)\n{\n void **v4; // rbp\n int v5; // r12d\n _DWORD *v6; // r15\n size_t v7; // rsi\n __int64 v8; // r14\n void **v9; // r13\n int *result; // rax\n void **v12; // [rsp+10h] [rbp-48h]\n\n if ( a2 <= 0 )\n {\n v5 = 0;\n }\n else\n {\n v4 = a1;\n v5 = 0;\n v12 = &a1[a2];\n do\n {\n while ( 1 )\n {\n v6 = *v4;\n v7 = 0LL;\n if ( *(_DWORD *)*v4 )\n {\n do\n {\n if ( !v6[2 * v7 + 1] )\n break;\n ++v7;\n }\n while ( v6[2 * v7] );\n }\n v8 = v5;\n qsort(*v4, v7, 8uLL, compare_pairs);\n if ( v5 > 0 )\n break;\nLABEL_13:\n ++v4;\n ++v5;\n a3[v8] = v6;\n if ( v4 == v12 )\n goto LABEL_12;\n }\n v8 = v5;\n v9 = a3;\n while ( !(unsigned __int8)are_sublists_equal(*v9, v6) )\n {\n if ( ++v9 == &a3[v5] )\n goto LABEL_13;\n }\n ++v4;\n }\n while ( v4 != v12 );\n }\nLABEL_12:\n result = a4;\n *a4 = v5;\n return result;\n}", + "ida_strip_asm": "sub_1630:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov [rsp+58h+var_50], rdx\nmov [rsp+58h+var_40], rcx\ntest esi, esi\njle loc_1731\nmovsxd rsi, esi\nmov rbp, rdi\nxor r12d, r12d\nlea rax, [rdi+rsi*8]\nmov [rsp+58h+var_48], rax\nnop word ptr [rax+rax+00000000h]\nloc_1670:\nmov r15, [rbp+0]\nxor esi, esi\nmov ecx, [r15]\ntest ecx, ecx\njnz short loc_168C\njmp short loc_1695\nloc_1680:\nadd rsi, 1; nmemb\nmov edx, [r15+rsi*8]\ntest edx, edx\njz short loc_1695\nloc_168C:\nmov eax, [r15+rsi*8+4]\ntest eax, eax\njnz short loc_1680\nloc_1695:\nlea rcx, compar; compar\nmov edx, 8; size\nmov rdi, r15; base\nmovsxd r14, r12d\ncall _qsort\ntest r12d, r12d\njle short loc_1710\nmov rax, [rsp+58h+var_50]\nmovsxd r14, r12d\nmov r13, rax\nlea rbx, [rax+r14*8]\njmp short loc_16D1\nloc_16C8:\nadd r13, 8\ncmp r13, rbx\njz short loc_1710\nloc_16D1:\nmov rdi, [r13+0]; base\nmov rsi, r15; void *\ncall sub_14D0\ntest al, al\njz short loc_16C8\nmov rax, [rsp+58h+var_48]\nadd rbp, 8\ncmp rbp, rax\njnz short loc_1670\nloc_16EF:\nmov rax, [rsp+58h+var_40]\nmov [rax], r12d\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1710:\nmov rax, [rsp+58h+var_50]\nadd rbp, 8\nadd r12d, 1\nmov [rax+r14*8], r15\nmov rax, [rsp+58h+var_48]\ncmp rbp, rax\njnz loc_1670\njmp short loc_16EF\nloc_1731:\nxor r12d, r12d\njmp short loc_16EF", + "ida_strip_pseudo": "int *__fastcall sub_1630(void **a1, int a2, void **a3, int *a4)\n{\n void **v4; // rbp\n int v5; // r12d\n _DWORD *v6; // r15\n size_t v7; // rsi\n __int64 v8; // r14\n void **v9; // r13\n int *result; // rax\n void **v12; // [rsp+10h] [rbp-48h]\n\n if ( a2 <= 0 )\n {\n v5 = 0;\n }\n else\n {\n v4 = a1;\n v5 = 0;\n v12 = &a1[a2];\n do\n {\n while ( 1 )\n {\n v6 = *v4;\n v7 = 0LL;\n if ( *(_DWORD *)*v4 )\n {\n do\n {\n if ( !v6[2 * v7 + 1] )\n break;\n ++v7;\n }\n while ( v6[2 * v7] );\n }\n v8 = v5;\n qsort(*v4, v7, 8uLL, compar);\n if ( v5 > 0 )\n break;\nLABEL_13:\n ++v4;\n ++v5;\n a3[v8] = v6;\n if ( v4 == v12 )\n goto LABEL_12;\n }\n v8 = v5;\n v9 = a3;\n while ( !(unsigned __int8)sub_14D0(*v9, v6) )\n {\n if ( ++v9 == &a3[v5] )\n goto LABEL_13;\n }\n ++v4;\n }\n while ( v4 != v12 );\n }\nLABEL_12:\n result = a4;\n *a4 = v5;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "int *sub_1630(void **a1, int a2, void **a3, int *a4) {\n void **v4;\n int v5;\n uint32_t *v6;\n unsigned int v7;\n long long v8;\n void **v9;\n int *result;\n void **v12;\n if (a2 <= 0) {\n v5 = 0;\n } else {\n v4 = a1;\n v5 = 0;\n v12 = &a1[a2];\n do {\n while (1) {\n v6 = *v4;\n v7 = 0LL;\n if (*(uint32_t *)*v4) {\n do {\n if (!v6[2 * v7 + 1]) break;\n ++v7;\n } while (v6[2 * v7]);\n }\n v8 = v5;\n qsort(*v4, v7, 8uLL, compar);\n if (v5 > 0) break;\n LABEL_13:\n ++v4;\n ++v5;\n a3[v8] = v6;\n if (v4 == v12) goto LABEL_12;\n }\n v8 = v5;\n v9 = a3;\n while (!(unsigned char)sub_14D0(*v9, v6)) {\n if (++v9 == &a3[v5]) goto LABEL_13;\n }\n ++v4;\n } while (v4 != v12);\n }\nLABEL_12:\n result = a4;\n *a4 = v5;\n return result;\n}", + "ida_pseudo_norm": "int *func0(void **a1, int a2, void **a3, int *a4) {\n void **v4;\n int v5;\n uint32_t *v6;\n unsigned int v7;\n long long v8;\n void **v9;\n int *result;\n void **v12;\n if (a2 <= 0) {\n v5 = 0;\n } else {\n v4 = a1;\n v5 = 0;\n v12 = &a1[a2];\n do {\n while (1) {\n v6 = *v4;\n v7 = 0LL;\n if (*(uint32_t *)*v4) {\n do {\n if (!v6[2 * v7 + 1]) break;\n ++v7;\n } while (v6[2 * v7]);\n }\n v8 = v5;\n qsort(*v4, v7, 8uLL, compare_pairs);\n if (v5 > 0) break;\n LABEL_13:\n ++v4;\n ++v5;\n a3[v8] = v6;\n if (v4 == v12) goto LABEL_12;\n }\n v8 = v5;\n v9 = a3;\n while (!(unsigned char)are_sublists_equal(*v9, v6)) {\n if (++v9 == &a3[v5]) goto LABEL_13;\n }\n ++v4;\n } while (v4 != v12);\n }\nLABEL_12:\n result = a4;\n *a4 = v5;\n return result;\n}" + }, + { + "index": 642, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n} Pair;\n\n\n\ntypedef Pair* Sublist;\n\n\n\nint compare_pairs(const void *a, const void *b) {\n\n Pair pa = *(Pair*)a;\n\n Pair pb = *(Pair*)b;\n\n if (pa.first != pb.first) return (pa.first - pb.first);\n\n return (pa.second - pb.second);\n\n}\n\n\n\nSublist sorted_sublist(Sublist sub, int len) {\n\n qsort(sub, len, sizeof(Pair), compare_pairs);\n\n return sub;\n\n}\n\n\n\nint sublist_length(Sublist sub) {\n\n int len = 0;\n\n while (sub[len].first != 0 && sub[len].second != 0) len++;\n\n return len;\n\n}\n\n\n\nbool are_sublists_equal(Sublist a, Sublist b) {\n\n int len_a = sublist_length(a);\n\n int len_b = sublist_length(b);\n\n if (len_a != len_b) return false;\n\n qsort(a, len_a, sizeof(Pair), compare_pairs);\n\n qsort(b, len_b, sizeof(Pair), compare_pairs);\n\n for (int i = 0; i < len_a; i++) {\n\n if (a[i].first != b[i].first || a[i].second != b[i].second) {\n\n return false;\n\n }\n\n }\n\n return true;\n\n}\n\n\n\n", + "func": "void func0(Sublist *test_list, int num_lists, Sublist *result,\n int *result_size) {\n int added = 0;\n for (int i = 0; i < num_lists; i++) {\n Sublist current =\n sorted_sublist(test_list[i], sublist_length(test_list[i]));\n bool found = false;\n for (int j = 0; j < added; j++) {\n if (are_sublists_equal(result[j], current)) {\n found = true;\n break;\n }\n }\n if (!found) {\n result[added++] = current;\n }\n }\n *result_size = added;\n}", + "test": "int main() {\n\n Pair list1[] = {{4, 5}, {3, 2}, {0, 0}};\n\n Pair list2[] = {{2, 2}, {4, 6}, {0, 0}};\n\n Pair list3[] = {{3, 2}, {4, 5}, {0, 0}};\n\n Sublist test_list1[] = {list1, list2, list3};\n\n Sublist result1[3];\n\n int result1_size = 0;\n\n\n\n func0(test_list1, 3, result1, &result1_size);\n\n assert(result1_size == 2);\n\n\n\n Pair list4[] = {{5, 6}, {4, 3}, {0, 0}};\n\n Pair list5[] = {{3, 3}, {5, 7}, {0, 0}};\n\n Pair list6[] = {{4, 3}, {5, 6}, {0, 0}};\n\n Sublist test_list2[] = {list4, list5, list6};\n\n Sublist result2[3];\n\n int result2_size = 0;\n\n\n\n func0(test_list2, 3, result2, &result2_size);\n\n assert(result2_size == 2);\n\n\n\n Pair list7[] = {{6, 7}, {5, 4}, {0, 0}};\n\n Pair list8[] = {{4, 4}, {6, 8}, {0, 0}};\n\n Pair list9[] = {{5, 4}, {6, 7}, {0, 0}};\n\n Sublist test_list3[] = {list7, list8, list9};\n\n Sublist result3[3];\n\n int result3_size = 0;\n\n\n\n func0(test_list3, 3, result3, &result3_size);\n\n assert(result3_size == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x28,%rsp\nmov %rcx,0x18(%rsp)\ntest %esi,%esi\njle 16f5 \nlea -0x1(%rsi),%eax\nmov %rdx,%r13\nmov %rdi,%rbp\nxor %r12d,%r12d\nlea 0x8(%rdi,%rax,8),%rax\nmov %rax,0x8(%rsp)\nlea 0x8(%rdx),%rax\nmov %rax,0x10(%rsp)\nxchg %ax,%ax\nmov 0x0(%rbp),%r14\nxor %esi,%esi\nmov (%r14),%ecx\ntest %ecx,%ecx\njne 165c \njmp 1665 \nadd $0x1,%rsi\nmov (%r14,%rsi,8),%edx\ntest %edx,%edx\nje 1665 \nmov 0x4(%r14,%rsi,8),%eax\ntest %eax,%eax\njne 1650 \nlea -0x22c(%rip),%rcx\nmov $0x8,%edx\nmov %r14,%rdi\ncallq 1070 \ntest %r12d,%r12d\nje 16d8 \nmov 0x10(%rsp),%rdx\nlea -0x1(%r12),%eax\nmov %r13,%r15\nlea (%rdx,%rax,8),%rbx\njmp 16a1 \nnopl 0x0(%rax)\nadd $0x8,%r15\ncmp %r15,%rbx\nje 16d8 \nmov (%r15),%rdi\nmov %r14,%rsi\ncallq 14c0 \ntest %al,%al\nje 1698 \nadd $0x8,%rbp\ncmp 0x8(%rsp),%rbp\njne 1640 \nmov 0x18(%rsp),%rax\nmov %r12d,(%rax)\nadd $0x28,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw 0x0(%rax,%rax,1)\nmovslq %r12d,%rax\nadd $0x8,%rbp\nadd $0x1,%r12d\nmov %r14,0x0(%r13,%rax,8)\ncmp 0x8(%rsp),%rbp\njne 1640 \njmp 16bb \nxor %r12d,%r12d\njmp 16bb \nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov [rsp+58h+var_50], rdx\nmov [rsp+58h+var_40], rcx\ntest esi, esi\njle loc_1731\nmovsxd rsi, esi\nmov rbp, rdi\nxor r12d, r12d\nlea rax, [rdi+rsi*8]\nmov [rsp+58h+var_48], rax\nnop word ptr [rax+rax+00000000h]\nloc_1670:\nmov r15, [rbp+0]\nxor esi, esi\nmov ecx, [r15]\ntest ecx, ecx\njnz short loc_168C\njmp short loc_1695\nloc_1680:\nadd rsi, 1; nmemb\nmov edx, [r15+rsi*8]\ntest edx, edx\njz short loc_1695\nloc_168C:\nmov eax, [r15+rsi*8+4]\ntest eax, eax\njnz short loc_1680\nloc_1695:\nlea rcx, compare_pairs; compar\nmov edx, 8; size\nmov rdi, r15; base\nmovsxd r14, r12d\ncall _qsort\ntest r12d, r12d\njle short loc_1710\nmov rax, [rsp+58h+var_50]\nmovsxd r14, r12d\nmov r13, rax\nlea rbx, [rax+r14*8]\njmp short loc_16D1\nloc_16C8:\nadd r13, 8\ncmp rbx, r13\njz short loc_1710\nloc_16D1:\nmov rdi, [r13+0]; base\nmov rsi, r15; void *\ncall are_sublists_equal\ntest al, al\njz short loc_16C8\nmov rax, [rsp+58h+var_48]\nadd rbp, 8\ncmp rbp, rax\njnz short loc_1670\nloc_16EF:\nmov rax, [rsp+58h+var_40]\nmov [rax], r12d\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1710:\nmov rax, [rsp+58h+var_50]\nadd rbp, 8\nadd r12d, 1\nmov [rax+r14*8], r15\nmov rax, [rsp+58h+var_48]\ncmp rbp, rax\njnz loc_1670\njmp short loc_16EF\nloc_1731:\nxor r12d, r12d\njmp short loc_16EF", + "ida_pseudo": "int *__fastcall func0(void **a1, int a2, void **a3, int *a4)\n{\n void **v4; // rbp\n int v5; // r12d\n _DWORD *v6; // r15\n size_t v7; // rsi\n __int64 v8; // r14\n void **v9; // r13\n int *result; // rax\n void **v12; // [rsp+10h] [rbp-48h]\n\n if ( a2 <= 0 )\n {\n v5 = 0;\n }\n else\n {\n v4 = a1;\n v5 = 0;\n v12 = &a1[a2];\n do\n {\n while ( 1 )\n {\n v6 = *v4;\n v7 = 0LL;\n if ( *(_DWORD *)*v4 )\n {\n do\n {\n if ( !v6[2 * v7 + 1] )\n break;\n ++v7;\n }\n while ( v6[2 * v7] );\n }\n v8 = v5;\n qsort(*v4, v7, 8uLL, compare_pairs);\n if ( v5 > 0 )\n break;\nLABEL_13:\n ++v4;\n ++v5;\n a3[v8] = v6;\n if ( v4 == v12 )\n goto LABEL_12;\n }\n v8 = v5;\n v9 = a3;\n while ( !(unsigned __int8)are_sublists_equal(*v9, v6) )\n {\n if ( &a3[v5] == ++v9 )\n goto LABEL_13;\n }\n ++v4;\n }\n while ( v4 != v12 );\n }\nLABEL_12:\n result = a4;\n *a4 = v5;\n return result;\n}", + "ida_strip_asm": "sub_1630:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov [rsp+58h+var_50], rdx\nmov [rsp+58h+var_40], rcx\ntest esi, esi\njle loc_1731\nmovsxd rsi, esi\nmov rbp, rdi\nxor r12d, r12d\nlea rax, [rdi+rsi*8]\nmov [rsp+58h+var_48], rax\nnop word ptr [rax+rax+00000000h]\nloc_1670:\nmov r15, [rbp+0]\nxor esi, esi\nmov ecx, [r15]\ntest ecx, ecx\njnz short loc_168C\njmp short loc_1695\nloc_1680:\nadd rsi, 1; nmemb\nmov edx, [r15+rsi*8]\ntest edx, edx\njz short loc_1695\nloc_168C:\nmov eax, [r15+rsi*8+4]\ntest eax, eax\njnz short loc_1680\nloc_1695:\nlea rcx, compar; compar\nmov edx, 8; size\nmov rdi, r15; base\nmovsxd r14, r12d\ncall _qsort\ntest r12d, r12d\njle short loc_1710\nmov rax, [rsp+58h+var_50]\nmovsxd r14, r12d\nmov r13, rax\nlea rbx, [rax+r14*8]\njmp short loc_16D1\nloc_16C8:\nadd r13, 8\ncmp rbx, r13\njz short loc_1710\nloc_16D1:\nmov rdi, [r13+0]; base\nmov rsi, r15; void *\ncall sub_14D0\ntest al, al\njz short loc_16C8\nmov rax, [rsp+58h+var_48]\nadd rbp, 8\ncmp rbp, rax\njnz short loc_1670\nloc_16EF:\nmov rax, [rsp+58h+var_40]\nmov [rax], r12d\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1710:\nmov rax, [rsp+58h+var_50]\nadd rbp, 8\nadd r12d, 1\nmov [rax+r14*8], r15\nmov rax, [rsp+58h+var_48]\ncmp rbp, rax\njnz loc_1670\njmp short loc_16EF\nloc_1731:\nxor r12d, r12d\njmp short loc_16EF", + "ida_strip_pseudo": "int *__fastcall sub_1630(void **a1, int a2, void **a3, int *a4)\n{\n void **v4; // rbp\n int v5; // r12d\n _DWORD *v6; // r15\n size_t v7; // rsi\n __int64 v8; // r14\n void **v9; // r13\n int *result; // rax\n void **v12; // [rsp+10h] [rbp-48h]\n\n if ( a2 <= 0 )\n {\n v5 = 0;\n }\n else\n {\n v4 = a1;\n v5 = 0;\n v12 = &a1[a2];\n do\n {\n while ( 1 )\n {\n v6 = *v4;\n v7 = 0LL;\n if ( *(_DWORD *)*v4 )\n {\n do\n {\n if ( !v6[2 * v7 + 1] )\n break;\n ++v7;\n }\n while ( v6[2 * v7] );\n }\n v8 = v5;\n qsort(*v4, v7, 8uLL, compar);\n if ( v5 > 0 )\n break;\nLABEL_13:\n ++v4;\n ++v5;\n a3[v8] = v6;\n if ( v4 == v12 )\n goto LABEL_12;\n }\n v8 = v5;\n v9 = a3;\n while ( !(unsigned __int8)sub_14D0(*v9, v6) )\n {\n if ( &a3[v5] == ++v9 )\n goto LABEL_13;\n }\n ++v4;\n }\n while ( v4 != v12 );\n }\nLABEL_12:\n result = a4;\n *a4 = v5;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "int *sub_1630(void **a1, int a2, void **a3, int *a4) {\n void **v4;\n int v5;\n uint32_t *v6;\n unsigned int v7;\n long long v8;\n void **v9;\n int *result;\n void **v12;\n if (a2 <= 0) {\n v5 = 0;\n } else {\n v4 = a1;\n v5 = 0;\n v12 = &a1[a2];\n do {\n while (1) {\n v6 = *v4;\n v7 = 0LL;\n if (*(uint32_t *)*v4) {\n do {\n if (!v6[2 * v7 + 1]) break;\n ++v7;\n } while (v6[2 * v7]);\n }\n v8 = v5;\n qsort(*v4, v7, 8uLL, compar);\n if (v5 > 0) break;\n LABEL_13:\n ++v4;\n ++v5;\n a3[v8] = v6;\n if (v4 == v12) goto LABEL_12;\n }\n v8 = v5;\n v9 = a3;\n while (!(unsigned char)sub_14D0(*v9, v6)) {\n if (&a3[v5] == ++v9) goto LABEL_13;\n }\n ++v4;\n } while (v4 != v12);\n }\nLABEL_12:\n result = a4;\n *a4 = v5;\n return result;\n}", + "ida_pseudo_norm": "int *func0(void **a1, int a2, void **a3, int *a4) {\n void **v4;\n int v5;\n uint32_t *v6;\n unsigned int v7;\n long long v8;\n void **v9;\n int *result;\n void **v12;\n if (a2 <= 0) {\n v5 = 0;\n } else {\n v4 = a1;\n v5 = 0;\n v12 = &a1[a2];\n do {\n while (1) {\n v6 = *v4;\n v7 = 0LL;\n if (*(uint32_t *)*v4) {\n do {\n if (!v6[2 * v7 + 1]) break;\n ++v7;\n } while (v6[2 * v7]);\n }\n v8 = v5;\n qsort(*v4, v7, 8uLL, compare_pairs);\n if (v5 > 0) break;\n LABEL_13:\n ++v4;\n ++v5;\n a3[v8] = v6;\n if (v4 == v12) goto LABEL_12;\n }\n v8 = v5;\n v9 = a3;\n while (!(unsigned char)are_sublists_equal(*v9, v6)) {\n if (&a3[v5] == ++v9) goto LABEL_13;\n }\n ++v4;\n } while (v4 != v12);\n }\nLABEL_12:\n result = a4;\n *a4 = v5;\n return result;\n}" + }, + { + "index": 643, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n", + "func": "char* func0(const char* text) {\n regex_t regex;\n char* pattern = \"\\\\Bz\\\\B\";\n int reti;\n reti = regcomp(®ex, pattern, REG_EXTENDED);\n if (reti) {\n fprintf(stderr, \"Could not compile regex\\n\");\n return \"Regex compilation error\";\n }\n reti = regexec(®ex, text, 0, NULL, 0);\n if (!reti) {\n return \"Found a match!\";\n } else if (reti == REG_NOMATCH) {\n return \"Not matched!\";\n } else {\n char msgbuf[100];\n regerror(reti, ®ex, msgbuf, sizeof(msgbuf));\n fprintf(stderr, \"Regex match failed: %s\\n\", msgbuf);\n return \"Regex execution error\";\n }\n regfree(®ex);\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"pythonzabc.\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\"xyzabc.\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\" lang .\"), \"Not matched!\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0xd0,%rsp\nmov %rdi,-0xc8(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0xdb3(%rip),%rax\nmov %rax,-0xb8(%rbp)\nmov -0xb8(%rbp),%rcx\nlea -0xb0(%rbp),%rax\nmov $0x1,%edx\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 10e0 \nmov %eax,-0xbc(%rbp)\ncmpl $0x0,-0xbc(%rbp)\nje 12b5 \nmov 0x2d90(%rip),%rax\nmov %rax,%rcx\nmov $0x18,%edx\nmov $0x1,%esi\nlea 0xd6a(%rip),%rdi\ncallq 1130 \nlea 0xd77(%rip),%rax\njmpq 1348 \nmov -0xc8(%rbp),%rsi\nlea -0xb0(%rbp),%rax\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rax,%rdi\ncallq 1120 \nmov %eax,-0xbc(%rbp)\ncmpl $0x0,-0xbc(%rbp)\njne 12f3 \nlea 0xd4e(%rip),%rax\njmp 1348 \ncmpl $0x1,-0xbc(%rbp)\njne 1305 \nlea 0xd4b(%rip),%rax\njmp 1348 \nlea -0x70(%rbp),%rdx\nlea -0xb0(%rbp),%rsi\nmov -0xbc(%rbp),%eax\nmov $0x64,%ecx\nmov %eax,%edi\ncallq 1110 \nmov 0x2cf7(%rip),%rax\nlea -0x70(%rbp),%rdx\nlea 0xd27(%rip),%rsi\nmov %rax,%rdi\nmov $0x0,%eax\ncallq 1100 \nlea 0xd2b(%rip),%rax\nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 135c \ncallq 10c0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0D0h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aBzB; \"\\\\Bz\\\\B\"\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+errcode], eax\ncmp [rbp+errcode], 0\njz short loc_12B8\nmov rax, cs:__bss_start\nmov rcx, rax; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rax, aCouldNotCompil; \"Could not compile regex\\n\"\nmov rdi, rax; ptr\ncall _fwrite\nlea rax, aRegexCompilati; \"Regex compilation error\"\njmp loc_134E\nloc_12B8:\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+errcode], eax\ncmp [rbp+errcode], 0\njnz short loc_12F6\nlea rax, s2; \"Found a match!\"\njmp short loc_134E\nloc_12F6:\ncmp [rbp+errcode], 1\njnz short loc_1308\nlea rax, aNotMatched; \"Not matched!\"\njmp short loc_134E\nloc_1308:\nlea rdx, [rbp+errbuf]; errbuf\nlea rsi, [rbp+preg]; preg\nmov eax, [rbp+errcode]\nmov ecx, 64h ; 'd'; errbuf_size\nmov edi, eax; errcode\ncall _regerror\nmov rax, cs:__bss_start\nlea rdx, [rbp+errbuf]\nlea rcx, format; \"Regex match failed: %s\\n\"\nmov rsi, rcx; format\nmov rdi, rax; stream\nmov eax, 0\ncall _fprintf\nlea rax, aRegexExecution; \"Regex execution error\"\nloc_134E:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1362\ncall ___stack_chk_fail\nlocret_1362:\nleave\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n int errcode; // [rsp+14h] [rbp-BCh]\n regex_t preg; // [rsp+20h] [rbp-B0h] BYREF\n char errbuf[104]; // [rsp+60h] [rbp-70h] BYREF\n unsigned __int64 v5; // [rsp+C8h] [rbp-8h]\n\n v5 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"\\\\Bz\\\\B\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n return \"Regex compilation error\";\n }\n else\n {\n errcode = regexec(&preg, a1, 0LL, 0LL, 0);\n if ( errcode )\n {\n if ( errcode == 1 )\n {\n return \"Not matched!\";\n }\n else\n {\n regerror(errcode, &preg, errbuf, 0x64uLL);\n fprintf(_bss_start, \"Regex match failed: %s\\n\", errbuf);\n return \"Regex execution error\";\n }\n }\n else\n {\n return \"Found a match!\";\n }\n }\n}", + "ida_strip_asm": "sub_1229:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0D0h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aBzB; \"\\\\Bz\\\\B\"\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+errcode], eax\ncmp [rbp+errcode], 0\njz short loc_12B8\nmov rax, cs:stderr\nmov rcx, rax; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rax, aCouldNotCompil; \"Could not compile regex\\n\"\nmov rdi, rax; ptr\ncall _fwrite\nlea rax, aRegexCompilati; \"Regex compilation error\"\njmp loc_134E\nloc_12B8:\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+errcode], eax\ncmp [rbp+errcode], 0\njnz short loc_12F6\nlea rax, s2; \"Found a match!\"\njmp short loc_134E\nloc_12F6:\ncmp [rbp+errcode], 1\njnz short loc_1308\nlea rax, aNotMatched; \"Not matched!\"\njmp short loc_134E\nloc_1308:\nlea rdx, [rbp+errbuf]; errbuf\nlea rsi, [rbp+preg]; preg\nmov eax, [rbp+errcode]\nmov ecx, 64h ; 'd'; errbuf_size\nmov edi, eax; errcode\ncall _regerror\nmov rax, cs:stderr\nlea rdx, [rbp+errbuf]\nlea rcx, format; \"Regex match failed: %s\\n\"\nmov rsi, rcx; format\nmov rdi, rax; stream\nmov eax, 0\ncall _fprintf\nlea rax, aRegexExecution; \"Regex execution error\"\nloc_134E:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1362\ncall ___stack_chk_fail\nlocret_1362:\nleave\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1229(const char *a1)\n{\n int errcode; // [rsp+14h] [rbp-BCh]\n regex_t preg; // [rsp+20h] [rbp-B0h] BYREF\n char errbuf[104]; // [rsp+60h] [rbp-70h] BYREF\n unsigned __int64 v5; // [rsp+C8h] [rbp-8h]\n\n v5 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"\\\\Bz\\\\B\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n return \"Regex compilation error\";\n }\n else\n {\n errcode = regexec(&preg, a1, 0LL, 0LL, 0);\n if ( errcode )\n {\n if ( errcode == 1 )\n {\n return \"Not matched!\";\n }\n else\n {\n regerror(errcode, &preg, errbuf, 0x64uLL);\n fprintf(stderr, \"Regex match failed: %s\\n\", errbuf);\n return \"Regex execution error\";\n }\n }\n else\n {\n return \"Found a match!\";\n }\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1229(const char *a1) {\n int errcode;\n regex_t preg;\n char errbuf[104];\n unsigned long long v5;\n v5 = __readfsqword(40u);\n if (regcomp(&preg, \"\\\\Bz\\\\B\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n return \"Regex compilation error\";\n } else {\n errcode = regexec(&preg, a1, 0LL, 0LL, 0);\n if (errcode) {\n if (errcode == 1) {\n return \"Not matched!\";\n } else {\n regerror(errcode, &preg, errbuf, 100uLL);\n fprintf(stderr, \"Regex match failed: %s\\n\", errbuf);\n return \"Regex execution error\";\n }\n } else {\n return \"Found a match!\";\n }\n }\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n int errcode;\n regex_t preg;\n char errbuf[104];\n unsigned long long v5;\n v5 = __readfsqword(40u);\n if (regcomp(&preg, \"\\\\Bz\\\\B\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n return \"Regex compilation error\";\n } else {\n errcode = regexec(&preg, a1, 0LL, 0LL, 0);\n if (errcode) {\n if (errcode == 1) {\n return \"Not matched!\";\n } else {\n regerror(errcode, &preg, errbuf, 100uLL);\n fprintf(_bss_start, \"Regex match failed: %s\\n\", errbuf);\n return \"Regex execution error\";\n }\n } else {\n return \"Found a match!\";\n }\n }\n}" + }, + { + "index": 643, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n", + "func": "char* func0(const char* text) {\n regex_t regex;\n char* pattern = \"\\\\Bz\\\\B\";\n int reti;\n reti = regcomp(®ex, pattern, REG_EXTENDED);\n if (reti) {\n fprintf(stderr, \"Could not compile regex\\n\");\n return \"Regex compilation error\";\n }\n reti = regexec(®ex, text, 0, NULL, 0);\n if (!reti) {\n return \"Found a match!\";\n } else if (reti == REG_NOMATCH) {\n return \"Not matched!\";\n } else {\n char msgbuf[100];\n regerror(reti, ®ex, msgbuf, sizeof(msgbuf));\n fprintf(stderr, \"Regex match failed: %s\\n\", msgbuf);\n return \"Regex execution error\";\n }\n regfree(®ex);\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"pythonzabc.\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\"xyzabc.\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\" lang .\"), \"Not matched!\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nsub $0xb0,%rsp\nmov %rdi,%rbx\nmov %fs:0x28,%rax\nmov %rax,0xa8(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nmov $0x1,%edx\nlea 0xe14(%rip),%rsi\ncallq 10d0 \ntest %eax,%eax\njne 12b5 \nmov %rsp,%rdi\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rbx,%rsi\ncallq 10f0 \nmov %eax,%edi\nlea 0xdcb(%rip),%rax\ntest %edi,%edi\nje 12d9 \nlea 0xdcf(%rip),%rax\ncmp $0x1,%edi\nje 12d9 \nlea 0x40(%rsp),%rbx\nmov %rsp,%rsi\nmov $0x64,%ecx\nmov %rbx,%rdx\ncallq 10e0 \nmov %rbx,%rcx\nlea 0xdd7(%rip),%rdx\nmov $0x1,%esi\nmov 0x2d7e(%rip),%rdi\nmov $0x0,%eax\ncallq 1110 <__fprintf_chk@plt>\nlea 0xd69(%rip),%rax\njmp 12d9 \nmov 0x2d64(%rip),%rcx\nmov $0x18,%edx\nmov $0x1,%esi\nlea 0xd87(%rip),%rdi\ncallq 1100 \nlea 0xd2b(%rip),%rax\nmov 0xa8(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 12f5 \nadd $0xb0,%rsp\npop %rbx\nretq\ncallq 10b0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbx\nsub rsp, 0B0h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+0B8h+var_10], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"\\\\Bz\\\\B\"\ncall _regcomp\ntest eax, eax\njnz short loc_12D5\nmov rdi, rsp; preg\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\ncall _regexec\nmov edi, eax; errcode\nlea rax, s2; \"Found a match!\"\ntest edi, edi\njz short loc_12F9\nlea rax, aNotMatched; \"Not matched!\"\ncmp edi, 1\njz short loc_12F9\nlea rbx, [rsp+0B8h+errbuf]\nmov rsi, rsp; preg\nmov ecx, 64h ; 'd'; errbuf_size\nmov rdx, rbx; errbuf\ncall _regerror\nmov rcx, rbx\nlea rdx, aRegexMatchFail; \"Regex match failed: %s\\n\"\nmov esi, 2\nmov rdi, cs:__bss_start\nmov eax, 0\ncall ___fprintf_chk\nlea rax, aRegexExecution; \"Regex execution error\"\njmp short loc_12F9\nloc_12D5:\nmov rcx, cs:__bss_start; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nlea rax, aRegexCompilati; \"Regex compilation error\"\nloc_12F9:\nmov rdx, [rsp+0B8h+var_10]\nsub rdx, fs:28h\njnz short loc_1315\nadd rsp, 0B0h\npop rbx\nretn\nloc_1315:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // edi\n const char *result; // rax\n regex_t v3; // [rsp+0h] [rbp-B8h] BYREF\n char errbuf[104]; // [rsp+40h] [rbp-78h] BYREF\n unsigned __int64 v5; // [rsp+A8h] [rbp-10h]\n\n v5 = __readfsqword(0x28u);\n if ( regcomp(&v3, \"\\\\Bz\\\\B\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n return \"Regex compilation error\";\n }\n else\n {\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n result = \"Found a match!\";\n if ( v1 )\n {\n result = \"Not matched!\";\n if ( v1 != 1 )\n {\n regerror(v1, &v3, errbuf, 0x64uLL);\n __fprintf_chk(_bss_start, 2LL, \"Regex match failed: %s\\n\", errbuf);\n return \"Regex execution error\";\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1229:\nendbr64\npush rbx\nsub rsp, 0B0h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+0B8h+var_10], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"\\\\Bz\\\\B\"\ncall _regcomp\ntest eax, eax\njnz short loc_12D5\nmov rdi, rsp; preg\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\ncall _regexec\nmov edi, eax; errcode\nlea rax, s2; \"Found a match!\"\ntest edi, edi\njz short loc_12F9\nlea rax, aNotMatched; \"Not matched!\"\ncmp edi, 1\njz short loc_12F9\nlea rbx, [rsp+0B8h+errbuf]\nmov rsi, rsp; preg\nmov ecx, 64h ; 'd'; errbuf_size\nmov rdx, rbx; errbuf\ncall _regerror\nmov rcx, rbx\nlea rdx, aRegexMatchFail; \"Regex match failed: %s\\n\"\nmov esi, 2\nmov rdi, cs:stderr\nmov eax, 0\ncall ___fprintf_chk\nlea rax, aRegexExecution; \"Regex execution error\"\njmp short loc_12F9\nloc_12D5:\nmov rcx, cs:stderr; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nlea rax, aRegexCompilati; \"Regex compilation error\"\nloc_12F9:\nmov rdx, [rsp+0B8h+var_10]\nsub rdx, fs:28h\njnz short loc_1315\nadd rsp, 0B0h\npop rbx\nretn\nloc_1315:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_1229(char *string)\n{\n int v1; // edi\n const char *result; // rax\n regex_t v3; // [rsp+0h] [rbp-B8h] BYREF\n char errbuf[104]; // [rsp+40h] [rbp-78h] BYREF\n unsigned __int64 v5; // [rsp+A8h] [rbp-10h]\n\n v5 = __readfsqword(0x28u);\n if ( regcomp(&v3, \"\\\\Bz\\\\B\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n return \"Regex compilation error\";\n }\n else\n {\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n result = \"Found a match!\";\n if ( v1 )\n {\n result = \"Not matched!\";\n if ( v1 != 1 )\n {\n regerror(v1, &v3, errbuf, 0x64uLL);\n __fprintf_chk(stderr, 2LL, \"Regex match failed: %s\\n\", errbuf);\n return \"Regex execution error\";\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1229(char *string) {\n int v1;\n const char *result;\n regex_t v3;\n char errbuf[104];\n unsigned long long v5;\n v5 = __readfsqword(40u);\n if (regcomp(&v3, \"\\\\Bz\\\\B\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n return \"Regex compilation error\";\n } else {\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n result = \"Found a match!\";\n if (v1) {\n result = \"Not matched!\";\n if (v1 != 1) {\n regerror(v1, &v3, errbuf, 100uLL);\n __fprintf_chk(stderr, 2LL, \"Regex match failed: %s\\n\", errbuf);\n return \"Regex execution error\";\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n const char *result;\n regex_t v3;\n char errbuf[104];\n unsigned long long v5;\n v5 = __readfsqword(40u);\n if (regcomp(&v3, \"\\\\Bz\\\\B\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n return \"Regex compilation error\";\n } else {\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n result = \"Found a match!\";\n if (v1) {\n result = \"Not matched!\";\n if (v1 != 1) {\n regerror(v1, &v3, errbuf, 100uLL);\n __fprintf_chk(_bss_start, 2LL, \"Regex match failed: %s\\n\", errbuf);\n return \"Regex execution error\";\n }\n }\n }\n return result;\n}" + }, + { + "index": 643, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n", + "func": "char* func0(const char* text) {\n regex_t regex;\n char* pattern = \"\\\\Bz\\\\B\";\n int reti;\n reti = regcomp(®ex, pattern, REG_EXTENDED);\n if (reti) {\n fprintf(stderr, \"Could not compile regex\\n\");\n return \"Regex compilation error\";\n }\n reti = regexec(®ex, text, 0, NULL, 0);\n if (!reti) {\n return \"Found a match!\";\n } else if (reti == REG_NOMATCH) {\n return \"Not matched!\";\n } else {\n char msgbuf[100];\n regerror(reti, ®ex, msgbuf, sizeof(msgbuf));\n fprintf(stderr, \"Regex match failed: %s\\n\", msgbuf);\n return \"Regex execution error\";\n }\n regfree(®ex);\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"pythonzabc.\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\"xyzabc.\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\" lang .\"), \"Not matched!\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov $0x1,%edx\nlea 0xd4c(%rip),%rsi\npush %r12\npush %rbp\nmov %rdi,%rbp\nsub $0xb0,%rsp\nmov %fs:0x28,%rax\nmov %rax,0xa8(%rsp)\nxor %eax,%eax\nmov %rsp,%r12\nmov %r12,%rdi\ncallq 10d0 \ntest %eax,%eax\njne 13c0 \nmov %r12,%rdi\nxor %r8d,%r8d\nxor %ecx,%ecx\nxor %edx,%edx\nmov %rbp,%rsi\ncallq 10f0 \nmov %eax,%edi\nlea 0xce2(%rip),%rax\ntest %edi,%edi\nje 1399 \nlea 0xce6(%rip),%rax\ncmp $0x1,%edi\nje 1399 \nlea 0x40(%rsp),%r13\nmov $0x64,%ecx\nmov %r12,%rsi\nmov %r13,%rdx\ncallq 10e0 \nmov %r13,%rcx\nmov $0x1,%esi\nxor %eax,%eax\nmov 0x2c9a(%rip),%rdi\nlea 0xce0(%rip),%rdx\ncallq 1110 <__fprintf_chk@plt>\nlea 0xc83(%rip),%rax\nmov 0xa8(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 13e6 \nadd $0xb0,%rsp\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax)\nmov 0x2c59(%rip),%rcx\nmov $0x18,%edx\nmov $0x1,%esi\nlea 0xc7c(%rip),%rdi\ncallq 1100 \nlea 0xc20(%rip),%rax\njmp 1399 \ncallq 10b0 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"\\\\Bz\\\\B\"\npush rbx\nmov rbx, rdi\nsub rsp, 0B8h\nmov rax, fs:28h\nmov [rsp+var_sA8], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njnz loc_13C8\nmov rdi, rbp; preg\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbx; string\ncall _regexec\nmov edi, eax; errcode\nlea rax, s2; \"Found a match!\"\ntest edi, edi\njz short loc_13A6\nlea rax, aNotMatched; \"Not matched!\"\ncmp edi, 1\njz short loc_13A6\nlea rbx, [rsp+errbuf]\nmov ecx, 64h ; 'd'; errbuf_size\nmov rsi, rbp; preg\nmov rdx, rbx; errbuf\ncall _regerror\nmov rcx, rbx\nmov esi, 2\nxor eax, eax\nmov rdi, cs:__bss_start\nlea rdx, aRegexMatchFail; \"Regex match failed: %s\\n\"\ncall ___fprintf_chk\nlea rax, aRegexExecution; \"Regex execution error\"\nloc_13A6:\nmov rdx, [rsp+var_sA8]\nsub rdx, fs:28h\njnz short loc_13EE\nadd rsp, 0B8h\npop rbx\npop rbp\nretn\nloc_13C8:\nmov rcx, cs:__bss_start; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nlea rax, aRegexCompilati; \"Regex compilation error\"\njmp short loc_13A6\nloc_13EE:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // edi\n const char *result; // rax\n regex_t vars0; // [rsp+0h] [rbp+0h] BYREF\n char errbuf[104]; // [rsp+40h] [rbp+40h] BYREF\n unsigned __int64 varsA8; // [rsp+A8h] [rbp+A8h]\n\n varsA8 = __readfsqword(0x28u);\n if ( regcomp(&vars0, \"\\\\Bz\\\\B\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n return \"Regex compilation error\";\n }\n else\n {\n v1 = regexec(&vars0, string, 0LL, 0LL, 0);\n result = \"Found a match!\";\n if ( v1 )\n {\n result = \"Not matched!\";\n if ( v1 != 1 )\n {\n regerror(v1, &vars0, errbuf, 0x64uLL);\n __fprintf_chk(_bss_start, 2LL, \"Regex match failed: %s\\n\", errbuf);\n return \"Regex execution error\";\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1300:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"\\\\Bz\\\\B\"\npush rbx\nmov rbx, rdi\nsub rsp, 0B8h\nmov rax, fs:28h\nmov [rsp+var_sA8], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njnz loc_13C8\nmov rdi, rbp; preg\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbx; string\ncall _regexec\nmov edi, eax; errcode\nlea rax, s2; \"Found a match!\"\ntest edi, edi\njz short loc_13A6\nlea rax, aNotMatched; \"Not matched!\"\ncmp edi, 1\njz short loc_13A6\nlea rbx, [rsp+errbuf]\nmov ecx, 64h ; 'd'; errbuf_size\nmov rsi, rbp; preg\nmov rdx, rbx; errbuf\ncall _regerror\nmov rcx, rbx\nmov esi, 2\nxor eax, eax\nmov rdi, cs:stderr\nlea rdx, aRegexMatchFail; \"Regex match failed: %s\\n\"\ncall ___fprintf_chk\nlea rax, aRegexExecution; \"Regex execution error\"\nloc_13A6:\nmov rdx, [rsp+var_sA8]\nsub rdx, fs:28h\njnz short loc_13EE\nadd rsp, 0B8h\npop rbx\npop rbp\nretn\nloc_13C8:\nmov rcx, cs:stderr; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nlea rax, aRegexCompilati; \"Regex compilation error\"\njmp short loc_13A6\nloc_13EE:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_1300(char *string)\n{\n int v1; // edi\n const char *result; // rax\n regex_t vars0; // [rsp+0h] [rbp+0h] BYREF\n char errbuf[104]; // [rsp+40h] [rbp+40h] BYREF\n unsigned __int64 varsA8; // [rsp+A8h] [rbp+A8h]\n\n varsA8 = __readfsqword(0x28u);\n if ( regcomp(&vars0, \"\\\\Bz\\\\B\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n return \"Regex compilation error\";\n }\n else\n {\n v1 = regexec(&vars0, string, 0LL, 0LL, 0);\n result = \"Found a match!\";\n if ( v1 )\n {\n result = \"Not matched!\";\n if ( v1 != 1 )\n {\n regerror(v1, &vars0, errbuf, 0x64uLL);\n __fprintf_chk(stderr, 2LL, \"Regex match failed: %s\\n\", errbuf);\n return \"Regex execution error\";\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1300(char *string) {\n int v1;\n const char *result;\n regex_t vars0;\n char errbuf[104];\n unsigned long long varsA8;\n varsA8 = __readfsqword(40u);\n if (regcomp(&vars0, \"\\\\Bz\\\\B\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n return \"Regex compilation error\";\n } else {\n v1 = regexec(&vars0, string, 0LL, 0LL, 0);\n result = \"Found a match!\";\n if (v1) {\n result = \"Not matched!\";\n if (v1 != 1) {\n regerror(v1, &vars0, errbuf, 100uLL);\n __fprintf_chk(stderr, 2LL, \"Regex match failed: %s\\n\", errbuf);\n return \"Regex execution error\";\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n const char *result;\n regex_t vars0;\n char errbuf[104];\n unsigned long long varsA8;\n varsA8 = __readfsqword(40u);\n if (regcomp(&vars0, \"\\\\Bz\\\\B\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n return \"Regex compilation error\";\n } else {\n v1 = regexec(&vars0, string, 0LL, 0LL, 0);\n result = \"Found a match!\";\n if (v1) {\n result = \"Not matched!\";\n if (v1 != 1) {\n regerror(v1, &vars0, errbuf, 100uLL);\n __fprintf_chk(_bss_start, 2LL, \"Regex match failed: %s\\n\", errbuf);\n return \"Regex execution error\";\n }\n }\n }\n return result;\n}" + }, + { + "index": 643, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n", + "func": "char* func0(const char* text) {\n regex_t regex;\n char* pattern = \"\\\\Bz\\\\B\";\n int reti;\n reti = regcomp(®ex, pattern, REG_EXTENDED);\n if (reti) {\n fprintf(stderr, \"Could not compile regex\\n\");\n return \"Regex compilation error\";\n }\n reti = regexec(®ex, text, 0, NULL, 0);\n if (!reti) {\n return \"Found a match!\";\n } else if (reti == REG_NOMATCH) {\n return \"Not matched!\";\n } else {\n char msgbuf[100];\n regerror(reti, ®ex, msgbuf, sizeof(msgbuf));\n fprintf(stderr, \"Regex match failed: %s\\n\", msgbuf);\n return \"Regex execution error\";\n }\n regfree(®ex);\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"pythonzabc.\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\"xyzabc.\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\" lang .\"), \"Not matched!\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov $0x1,%edx\nlea 0xd4c(%rip),%rsi\npush %r12\npush %rbp\nmov %rdi,%rbp\nsub $0xb0,%rsp\nmov %fs:0x28,%rax\nmov %rax,0xa8(%rsp)\nxor %eax,%eax\nmov %rsp,%r12\nmov %r12,%rdi\ncallq 10d0 \ntest %eax,%eax\njne 13c0 \nmov %r12,%rdi\nxor %r8d,%r8d\nxor %ecx,%ecx\nxor %edx,%edx\nmov %rbp,%rsi\ncallq 10f0 \nmov %eax,%edi\nlea 0xce2(%rip),%rax\ntest %edi,%edi\nje 1399 \nlea 0xce6(%rip),%rax\ncmp $0x1,%edi\nje 1399 \nlea 0x40(%rsp),%r13\nmov $0x64,%ecx\nmov %r12,%rsi\nmov %r13,%rdx\ncallq 10e0 \nmov %r13,%rcx\nmov $0x1,%esi\nxor %eax,%eax\nmov 0x2c9a(%rip),%rdi\nlea 0xce0(%rip),%rdx\ncallq 1110 <__fprintf_chk@plt>\nlea 0xc83(%rip),%rax\nmov 0xa8(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 13e6 \nadd $0xb0,%rsp\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax)\nmov 0x2c59(%rip),%rcx\nmov $0x18,%edx\nmov $0x1,%esi\nlea 0xc7c(%rip),%rdi\ncallq 1100 \nlea 0xc20(%rip),%rax\njmp 1399 \ncallq 10b0 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"\\\\Bz\\\\B\"\npush rbx\nmov rbx, rdi\nsub rsp, 0B8h\nmov rax, fs:28h\nmov [rsp+var_sA8], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njnz loc_13C8\nmov rdi, rbp; preg\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbx; string\ncall _regexec\nmov edi, eax; errcode\nlea rax, s2; \"Found a match!\"\ntest edi, edi\njz short loc_13A6\nlea rax, aNotMatched; \"Not matched!\"\ncmp edi, 1\njz short loc_13A6\nlea rbx, [rsp+errbuf]\nmov ecx, 64h ; 'd'; errbuf_size\nmov rsi, rbp; preg\nmov rdx, rbx; errbuf\ncall _regerror\nmov rcx, rbx\nmov esi, 2\nxor eax, eax\nmov rdi, cs:__bss_start\nlea rdx, aRegexMatchFail; \"Regex match failed: %s\\n\"\ncall ___fprintf_chk\nlea rax, aRegexExecution; \"Regex execution error\"\nloc_13A6:\nmov rdx, [rsp+var_sA8]\nsub rdx, fs:28h\njnz short loc_13EE\nadd rsp, 0B8h\npop rbx\npop rbp\nretn\nloc_13C8:\nmov rcx, cs:__bss_start; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nlea rax, aRegexCompilati; \"Regex compilation error\"\njmp short loc_13A6\nloc_13EE:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // edi\n const char *result; // rax\n regex_t vars0; // [rsp+0h] [rbp+0h] BYREF\n char errbuf[104]; // [rsp+40h] [rbp+40h] BYREF\n unsigned __int64 varsA8; // [rsp+A8h] [rbp+A8h]\n\n varsA8 = __readfsqword(0x28u);\n if ( regcomp(&vars0, \"\\\\Bz\\\\B\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n return \"Regex compilation error\";\n }\n else\n {\n v1 = regexec(&vars0, string, 0LL, 0LL, 0);\n result = \"Found a match!\";\n if ( v1 )\n {\n result = \"Not matched!\";\n if ( v1 != 1 )\n {\n regerror(v1, &vars0, errbuf, 0x64uLL);\n __fprintf_chk(_bss_start, 2LL, \"Regex match failed: %s\\n\", errbuf);\n return \"Regex execution error\";\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1300:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"\\\\Bz\\\\B\"\npush rbx\nmov rbx, rdi\nsub rsp, 0B8h\nmov rax, fs:28h\nmov [rsp+var_sA8], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njnz loc_13C8\nmov rdi, rbp; preg\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbx; string\ncall _regexec\nmov edi, eax; errcode\nlea rax, s2; \"Found a match!\"\ntest edi, edi\njz short loc_13A6\nlea rax, aNotMatched; \"Not matched!\"\ncmp edi, 1\njz short loc_13A6\nlea rbx, [rsp+errbuf]\nmov ecx, 64h ; 'd'; errbuf_size\nmov rsi, rbp; preg\nmov rdx, rbx; errbuf\ncall _regerror\nmov rcx, rbx\nmov esi, 2\nxor eax, eax\nmov rdi, cs:stderr\nlea rdx, aRegexMatchFail; \"Regex match failed: %s\\n\"\ncall ___fprintf_chk\nlea rax, aRegexExecution; \"Regex execution error\"\nloc_13A6:\nmov rdx, [rsp+var_sA8]\nsub rdx, fs:28h\njnz short loc_13EE\nadd rsp, 0B8h\npop rbx\npop rbp\nretn\nloc_13C8:\nmov rcx, cs:stderr; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nlea rax, aRegexCompilati; \"Regex compilation error\"\njmp short loc_13A6\nloc_13EE:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_1300(char *string)\n{\n int v1; // edi\n const char *result; // rax\n regex_t vars0; // [rsp+0h] [rbp+0h] BYREF\n char errbuf[104]; // [rsp+40h] [rbp+40h] BYREF\n unsigned __int64 varsA8; // [rsp+A8h] [rbp+A8h]\n\n varsA8 = __readfsqword(0x28u);\n if ( regcomp(&vars0, \"\\\\Bz\\\\B\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n return \"Regex compilation error\";\n }\n else\n {\n v1 = regexec(&vars0, string, 0LL, 0LL, 0);\n result = \"Found a match!\";\n if ( v1 )\n {\n result = \"Not matched!\";\n if ( v1 != 1 )\n {\n regerror(v1, &vars0, errbuf, 0x64uLL);\n __fprintf_chk(stderr, 2LL, \"Regex match failed: %s\\n\", errbuf);\n return \"Regex execution error\";\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1300(char *string) {\n int v1;\n const char *result;\n regex_t vars0;\n char errbuf[104];\n unsigned long long varsA8;\n varsA8 = __readfsqword(40u);\n if (regcomp(&vars0, \"\\\\Bz\\\\B\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n return \"Regex compilation error\";\n } else {\n v1 = regexec(&vars0, string, 0LL, 0LL, 0);\n result = \"Found a match!\";\n if (v1) {\n result = \"Not matched!\";\n if (v1 != 1) {\n regerror(v1, &vars0, errbuf, 100uLL);\n __fprintf_chk(stderr, 2LL, \"Regex match failed: %s\\n\", errbuf);\n return \"Regex execution error\";\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n const char *result;\n regex_t vars0;\n char errbuf[104];\n unsigned long long varsA8;\n varsA8 = __readfsqword(40u);\n if (regcomp(&vars0, \"\\\\Bz\\\\B\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n return \"Regex compilation error\";\n } else {\n v1 = regexec(&vars0, string, 0LL, 0LL, 0);\n result = \"Found a match!\";\n if (v1) {\n result = \"Not matched!\";\n if (v1 != 1) {\n regerror(v1, &vars0, errbuf, 100uLL);\n __fprintf_chk(_bss_start, 2LL, \"Regex match failed: %s\\n\", errbuf);\n return \"Regex execution error\";\n }\n }\n }\n return result;\n}" + }, + { + "index": 644, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int input[], int n, int k, int output[]) {\n int i, j;\n for (i = 0, j = k - 1; i < k; i++, j--) {\n output[i] = input[j];\n }\n for (i = k; i < n; i++) {\n output[i] = input[i];\n }\n}", + "test": "int main() {\n\n int output1[6], output2[4], output3[5];\n\n int arr1[] = {1, 2, 3, 4, 5, 6};\n\n int arr2[] = {4, 5, 6, 7};\n\n int arr3[] = {9, 8, 7, 6, 5};\n\n\n\n func0(arr1, 6, 4, output1);\n\n assert(output1[0] == 4 && output1[1] == 3 && output1[2] == 2 && output1[3] == 1 && output1[4] == 5 && output1[5] == 6);\n\n\n\n func0(arr2, 4, 2, output2);\n\n assert(output2[0] == 5 && output2[1] == 4 && output2[2] == 6 && output2[3] == 7);\n\n\n\n func0(arr3, 5, 3, output3);\n\n assert(output3[0] == 7 && output3[1] == 8 && output3[2] == 9 && output3[3] == 6 && output3[4] == 5);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmov %rcx,-0x28(%rbp)\nmovl $0x0,-0x8(%rbp)\nmov -0x20(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0x4(%rbp)\njmp 11c6 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0x8(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x28(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x8(%rbp)\nsubl $0x1,-0x4(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x20(%rbp),%eax\njl 1191 \nmov -0x20(%rbp),%eax\nmov %eax,-0x8(%rbp)\njmp 1207 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0x8(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x28(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11d6 \npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_28], rcx\nmov [rbp+var_8], 0\nmov eax, [rbp+var_20]\nsub eax, 1\nmov [rbp+var_4], eax\njmp short loc_11C6\nloc_1191:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_8], 1\nsub [rbp+var_4], 1\nloc_11C6:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_20]\njl short loc_1191\nmov eax, [rbp+var_20]\nmov [rbp+var_8], eax\njmp short loc_1207\nloc_11D6:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_8], 1\nloc_1207:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_11D6\nnop\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, signed int a3, __int64 a4)\n{\n __int64 result; // rax\n int v5; // [rsp+20h] [rbp-8h]\n unsigned int i; // [rsp+20h] [rbp-8h]\n int v7; // [rsp+24h] [rbp-4h]\n\n v5 = 0;\n v7 = a3 - 1;\n while ( v5 < a3 )\n *(_DWORD *)(4LL * v5++ + a4) = *(_DWORD *)(4LL * v7-- + a1);\n for ( i = a3; ; ++i )\n {\n result = i;\n if ( (int)i >= a2 )\n break;\n *(_DWORD *)(4LL * (int)i + a4) = *(_DWORD *)(4LL * (int)i + a1);\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_28], rcx\nmov [rbp+var_8], 0\nmov eax, [rbp+var_20]\nsub eax, 1\nmov [rbp+var_4], eax\njmp short loc_11C6\nloc_1191:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_8], 1\nsub [rbp+var_4], 1\nloc_11C6:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_20]\njl short loc_1191\nmov eax, [rbp+var_20]\nmov [rbp+var_8], eax\njmp short loc_1207\nloc_11D6:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_8], 1\nloc_1207:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_11D6\nnop\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, signed int a3, __int64 a4)\n{\n __int64 result; // rax\n int v5; // [rsp+20h] [rbp-8h]\n unsigned int i; // [rsp+20h] [rbp-8h]\n int v7; // [rsp+24h] [rbp-4h]\n\n v5 = 0;\n v7 = a3 - 1;\n while ( v5 < a3 )\n *(_DWORD *)(4LL * v5++ + a4) = *(_DWORD *)(4LL * v7-- + a1);\n for ( i = a3; ; ++i )\n {\n result = i;\n if ( (int)i >= a2 )\n break;\n *(_DWORD *)(4LL * (int)i + a4) = *(_DWORD *)(4LL * (int)i + a1);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, signed int a3, long long a4) {\n long long result;\n int v5;\n unsigned int i;\n int v7;\n v5 = 0;\n v7 = a3 - 1;\n while (v5 < a3)\n *(uint32_t *)(4LL * v5++ + a4) = *(uint32_t *)(4LL * v7-- + a1);\n for (i = a3;; ++i) {\n result = i;\n if ((int)i >= a2) break;\n *(uint32_t *)(4LL * (int)i + a4) = *(uint32_t *)(4LL * (int)i + a1);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, signed int a3, long long a4) {\n long long result;\n int v5;\n unsigned int i;\n int v7;\n v5 = 0;\n v7 = a3 - 1;\n while (v5 < a3)\n *(uint32_t *)(4LL * v5++ + a4) = *(uint32_t *)(4LL * v7-- + a1);\n for (i = a3;; ++i) {\n result = i;\n if ((int)i >= a2) break;\n *(uint32_t *)(4LL * (int)i + a4) = *(uint32_t *)(4LL * (int)i + a1);\n }\n return result;\n}" + }, + { + "index": 644, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int input[], int n, int k, int output[]) {\n int i, j;\n for (i = 0, j = k - 1; i < k; i++, j--) {\n output[i] = input[j];\n }\n for (i = k; i < n; i++) {\n output[i] = input[i];\n }\n}", + "test": "int main() {\n\n int output1[6], output2[4], output3[5];\n\n int arr1[] = {1, 2, 3, 4, 5, 6};\n\n int arr2[] = {4, 5, 6, 7};\n\n int arr3[] = {9, 8, 7, 6, 5};\n\n\n\n func0(arr1, 6, 4, output1);\n\n assert(output1[0] == 4 && output1[1] == 3 && output1[2] == 2 && output1[3] == 1 && output1[4] == 5 && output1[5] == 6);\n\n\n\n func0(arr2, 4, 2, output2);\n\n assert(output2[0] == 5 && output2[1] == 4 && output2[2] == 6 && output2[3] == 7);\n\n\n\n func0(arr3, 5, 3, output3);\n\n assert(output3[0] == 7 && output3[1] == 8 && output3[2] == 9 && output3[3] == 6 && output3[4] == 5);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nlea -0x1(%rdx),%eax\ntest %edx,%edx\njle 1199 \ncltq\nlea (%rdi,%rax,4),%r8\nmov %rcx,%rax\nlea -0x1(%rdx),%r9d\nlea 0x4(%rcx,%r9,4),%r10\nmov (%r8),%r9d\nmov %r9d,(%rax)\nsub $0x4,%r8\nadd $0x4,%rax\ncmp %r10,%rax\njne 1186 \ncmp %esi,%edx\njge 11ae \nmovslq %edx,%rdx\nmov (%rdi,%rdx,4),%eax\nmov %eax,(%rcx,%rdx,4)\nadd $0x1,%rdx\ncmp %edx,%esi\njg 11a0 \nretq\n", + "ida_asm": "func0:\nendbr64\nmov r9, rdi\nmov r8d, esi\nlea edi, [rdx-1]\ntest edx, edx\njle short loc_119E\nmovsxd rdi, edi\nshl rdi, 2\nlea rsi, [r9+rdi]\nmov rax, rcx\nlea r10, [rcx+rdi+4]\nloc_118D:\nmov edi, [rsi]\nmov [rax], edi\nsub rsi, 4\nadd rax, 4\ncmp rax, r10\njnz short loc_118D\nloc_119E:\ncmp edx, r8d\njge short locret_11B6\nmovsxd rdx, edx\nloc_11A6:\nmov eax, [r9+rdx*4]\nmov [rcx+rdx*4], eax\nadd rdx, 1\ncmp r8d, edx\njg short loc_11A6\nlocret_11B6:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2, __int64 a3, _DWORD *a4)\n{\n __int64 v6; // rdi\n _DWORD *v7; // rsi\n _DWORD *v8; // rax\n\n if ( (int)a3 > 0 )\n {\n v6 = (int)a3 - 1;\n v7 = (_DWORD *)(a1 + v6 * 4);\n v8 = a4;\n do\n *v8++ = *v7--;\n while ( v8 != &a4[v6 + 1] );\n }\n if ( (int)a3 < a2 )\n {\n a3 = (int)a3;\n do\n {\n a4[a3] = *(_DWORD *)(a1 + 4 * a3);\n ++a3;\n }\n while ( a2 > (int)a3 );\n }\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov r9, rdi\nmov r8d, esi\nlea edi, [rdx-1]\ntest edx, edx\njle short loc_119E\nmovsxd rdi, edi\nshl rdi, 2\nlea rsi, [r9+rdi]\nmov rax, rcx\nlea r10, [rcx+rdi+4]\nloc_118D:\nmov edi, [rsi]\nmov [rax], edi\nsub rsi, 4\nadd rax, 4\ncmp rax, r10\njnz short loc_118D\nloc_119E:\ncmp edx, r8d\njge short locret_11B6\nmovsxd rdx, edx\nloc_11A6:\nmov eax, [r9+rdx*4]\nmov [rcx+rdx*4], eax\nadd rdx, 1\ncmp r8d, edx\njg short loc_11A6\nlocret_11B6:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1169(__int64 a1, int a2, __int64 a3, _DWORD *a4)\n{\n __int64 v6; // rdi\n _DWORD *v7; // rsi\n _DWORD *v8; // rax\n\n if ( (int)a3 > 0 )\n {\n v6 = (int)a3 - 1;\n v7 = (_DWORD *)(a1 + v6 * 4);\n v8 = a4;\n do\n *v8++ = *v7--;\n while ( v8 != &a4[v6 + 1] );\n }\n if ( (int)a3 < a2 )\n {\n a3 = (int)a3;\n do\n {\n a4[a3] = *(_DWORD *)(a1 + 4 * a3);\n ++a3;\n }\n while ( a2 > (int)a3 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1169(long long a1, int a2, long long a3, uint32_t *a4) {\n long long v6;\n uint32_t *v7;\n uint32_t *v8;\n if ((int)a3 > 0) {\n v6 = (int)a3 - 1;\n v7 = (uint32_t *)(a1 + v6 * 4);\n v8 = a4;\n do\n *v8++ = *v7--;\n while (v8 != &a4[v6 + 1]);\n }\n if ((int)a3 < a2) {\n a3 = (int)a3;\n do {\n a4[a3] = *(uint32_t *)(a1 + 4 * a3);\n ++a3;\n } while (a2 > (int)a3);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2, long long a3, uint32_t *a4) {\n long long v6;\n uint32_t *v7;\n uint32_t *v8;\n if ((int)a3 > 0) {\n v6 = (int)a3 - 1;\n v7 = (uint32_t *)(a1 + v6 * 4);\n v8 = a4;\n do\n *v8++ = *v7--;\n while (v8 != &a4[v6 + 1]);\n }\n if ((int)a3 < a2) {\n a3 = (int)a3;\n do {\n a4[a3] = *(uint32_t *)(a1 + 4 * a3);\n ++a3;\n } while (a2 > (int)a3);\n }\n}" + }, + { + "index": 644, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int input[], int n, int k, int output[]) {\n int i, j;\n for (i = 0, j = k - 1; i < k; i++, j--) {\n output[i] = input[j];\n }\n for (i = k; i < n; i++) {\n output[i] = input[i];\n }\n}", + "test": "int main() {\n\n int output1[6], output2[4], output3[5];\n\n int arr1[] = {1, 2, 3, 4, 5, 6};\n\n int arr2[] = {4, 5, 6, 7};\n\n int arr3[] = {9, 8, 7, 6, 5};\n\n\n\n func0(arr1, 6, 4, output1);\n\n assert(output1[0] == 4 && output1[1] == 3 && output1[2] == 2 && output1[3] == 1 && output1[4] == 5 && output1[5] == 6);\n\n\n\n func0(arr2, 4, 2, output2);\n\n assert(output2[0] == 5 && output2[1] == 4 && output2[2] == 6 && output2[3] == 7);\n\n\n\n func0(arr3, 5, 3, output3);\n\n assert(output3[0] == 7 && output3[1] == 8 && output3[2] == 9 && output3[3] == 6 && output3[4] == 5);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nlea -0x1(%rdx),%r9d\ntest %edx,%edx\njle 1174 \nmovslq %r9d,%rax\nmov %r9d,%r9d\nlea (%rdi,%rax,4),%r8\nlea 0x4(%rcx,%r9,4),%r10\nmov %rcx,%rax\nxchg %ax,%ax\nmov (%r8),%r9d\nadd $0x4,%rax\nsub $0x4,%r8\nmov %r9d,-0x4(%rax)\ncmp %r10,%rax\njne 1160 \ncmp %esi,%edx\njge 118e \nmovslq %edx,%rdx\nnopl 0x0(%rax,%rax,1)\nmov (%rdi,%rdx,4),%eax\nmov %eax,(%rcx,%rdx,4)\nadd $0x1,%rdx\ncmp %edx,%esi\njg 1180 \nretq\n", + "ida_asm": "func0:\nendbr64\nmov r9, rdi\nmov r8d, esi\nlea edi, [rdx-1]\ntest edx, edx\njle short loc_136A\nmovsxd rdi, edi\nmov rax, rcx\nshl rdi, 2\nlea rsi, [r9+rdi]\nlea r10, [rcx+rdi+4]\nnop dword ptr [rax+00h]\nloc_1358:\nmov edi, [rsi]\nadd rax, 4\nsub rsi, 4\nmov [rax-4], edi\ncmp rax, r10\njnz short loc_1358\nloc_136A:\ncmp edx, r8d\njge short locret_1388\nmovsxd rdx, edx\nnop word ptr [rax+rax+00h]\nloc_1378:\nmov eax, [r9+rdx*4]\nmov [rcx+rdx*4], eax\nadd rdx, 1\ncmp r8d, edx\njg short loc_1378\nlocret_1388:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2, __int64 a3, __int64 a4)\n{\n __int64 v6; // rax\n __int64 v7; // rdi\n int *v8; // rsi\n __int64 v9; // r10\n int v10; // edi\n\n if ( (int)a3 > 0 )\n {\n v6 = a4;\n v7 = 4LL * ((int)a3 - 1);\n v8 = (int *)(a1 + v7);\n v9 = a4 + v7 + 4;\n do\n {\n v10 = *v8;\n v6 += 4LL;\n --v8;\n *(_DWORD *)(v6 - 4) = v10;\n }\n while ( v6 != v9 );\n }\n if ( (int)a3 < a2 )\n {\n a3 = (int)a3;\n do\n {\n *(_DWORD *)(a4 + 4 * a3) = *(_DWORD *)(a1 + 4 * a3);\n ++a3;\n }\n while ( a2 > (int)a3 );\n }\n}", + "ida_strip_asm": "sub_1330:\nendbr64\nmov r9, rdi\nmov r8d, esi\nlea edi, [rdx-1]\ntest edx, edx\njle short loc_136A\nmovsxd rdi, edi\nmov rax, rcx\nshl rdi, 2\nlea rsi, [r9+rdi]\nlea r10, [rcx+rdi+4]\nnop dword ptr [rax+00h]\nloc_1358:\nmov edi, [rsi]\nadd rax, 4\nsub rsi, 4\nmov [rax-4], edi\ncmp rax, r10\njnz short loc_1358\nloc_136A:\ncmp edx, r8d\njge short locret_1388\nmovsxd rdx, edx\nnop word ptr [rax+rax+00h]\nloc_1378:\nmov eax, [r9+rdx*4]\nmov [rcx+rdx*4], eax\nadd rdx, 1\ncmp r8d, edx\njg short loc_1378\nlocret_1388:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1330(__int64 a1, int a2, __int64 a3, __int64 a4)\n{\n __int64 v6; // rax\n __int64 v7; // rdi\n int *v8; // rsi\n __int64 v9; // r10\n int v10; // edi\n\n if ( (int)a3 > 0 )\n {\n v6 = a4;\n v7 = 4LL * ((int)a3 - 1);\n v8 = (int *)(a1 + v7);\n v9 = a4 + v7 + 4;\n do\n {\n v10 = *v8;\n v6 += 4LL;\n --v8;\n *(_DWORD *)(v6 - 4) = v10;\n }\n while ( v6 != v9 );\n }\n if ( (int)a3 < a2 )\n {\n a3 = (int)a3;\n do\n {\n *(_DWORD *)(a4 + 4 * a3) = *(_DWORD *)(a1 + 4 * a3);\n ++a3;\n }\n while ( a2 > (int)a3 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1330(long long a1, int a2, long long a3, long long a4) {\n long long v6;\n long long v7;\n int *v8;\n long long v9;\n int v10;\n if ((int)a3 > 0) {\n v6 = a4;\n v7 = 4LL * ((int)a3 - 1);\n v8 = (int *)(a1 + v7);\n v9 = a4 + v7 + 4;\n do {\n v10 = *v8;\n v6 += 4LL;\n --v8;\n *(uint32_t *)(v6 - 4) = v10;\n } while (v6 != v9);\n }\n if ((int)a3 < a2) {\n a3 = (int)a3;\n do {\n *(uint32_t *)(a4 + 4 * a3) = *(uint32_t *)(a1 + 4 * a3);\n ++a3;\n } while (a2 > (int)a3);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2, long long a3, long long a4) {\n long long v6;\n long long v7;\n int *v8;\n long long v9;\n int v10;\n if ((int)a3 > 0) {\n v6 = a4;\n v7 = 4LL * ((int)a3 - 1);\n v8 = (int *)(a1 + v7);\n v9 = a4 + v7 + 4;\n do {\n v10 = *v8;\n v6 += 4LL;\n --v8;\n *(uint32_t *)(v6 - 4) = v10;\n } while (v6 != v9);\n }\n if ((int)a3 < a2) {\n a3 = (int)a3;\n do {\n *(uint32_t *)(a4 + 4 * a3) = *(uint32_t *)(a1 + 4 * a3);\n ++a3;\n } while (a2 > (int)a3);\n }\n}" + }, + { + "index": 645, + "func_name": "func0", + "func_dep": "#include \n\n\n\nint get_product(int val[], int n) {\n\n int res = 1;\n\n for (int i = 0; i < n; i++) {\n\n res *= val[i];\n\n }\n\n return res;\n\n}\n\n\n\n", + "func": "int func0(int test_list[][3], int rows, int K) {\n int temp[rows];\n for (int i = 0; i < rows; i++) {\n temp[i] = test_list[i][K];\n }\n return get_product(temp, rows);\n}", + "test": "int main() {\n\n int test_list1[3][3] = {{5, 6, 7}, {1, 3, 5}, {8, 9, 19}};\n\n assert(func0(test_list1, 3, 2) == 665);\n\n \n\n int test_list2[3][3] = {{6, 7, 8}, {2, 4, 6}, {9, 10, 20}};\n\n assert(func0(test_list2, 3, 1) == 280);\n\n \n\n int test_list3[3][3] = {{7, 8, 9}, {3, 5, 7}, {10, 11, 21}};\n\n assert(func0(test_list3, 3, 0) == 210);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x38,%rsp\nmov %rdi,-0x38(%rbp)\nmov %esi,-0x3c(%rbp)\nmov %edx,-0x40(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmov %rsp,%rax\nmov %rax,%rbx\nmov -0x3c(%rbp),%eax\nmovslq %eax,%rdx\nsub $0x1,%rdx\nmov %rdx,-0x28(%rbp)\nmovslq %eax,%rdx\nmov %rdx,%r10\nmov $0x0,%r11d\nmovslq %eax,%rdx\nmov %rdx,%r8\nmov $0x0,%r9d\ncltq\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%edi\nmov $0x0,%edx\ndiv %rdi\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rcx\nsub %rdx,%rcx\nmov %rcx,%rdx\ncmp %rdx,%rsp\nje 125b \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 1244 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 1285 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x20(%rbp)\nmovl $0x0,-0x2c(%rbp)\njmp 12d7 \nmov -0x2c(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x38(%rbp),%rax\nadd %rax,%rdx\nmov -0x40(%rbp),%eax\ncltq\nmov (%rdx,%rax,4),%ecx\nmov -0x20(%rbp),%rax\nmov -0x2c(%rbp),%edx\nmovslq %edx,%rdx\nmov %ecx,(%rax,%rdx,4)\naddl $0x1,-0x2c(%rbp)\nmov -0x2c(%rbp),%eax\ncmp -0x3c(%rbp),%eax\njl 12a1 \nmov -0x3c(%rbp),%edx\nmov -0x20(%rbp),%rax\nmov %edx,%esi\nmov %rax,%rdi\ncallq 1169 \nmov %rbx,%rsp\nmov -0x18(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 1307 \ncallq 1060 <__stack_chk_fail@plt>\nmov -0x8(%rbp),%rbx\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov [rbp+var_40], edx\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov rax, rsp\nmov rbx, rax\nmov eax, [rbp+var_3C]\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_28], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov esi, 10h\nmov edx, 0\ndiv rsi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_1229:\ncmp rsp, rdx\njz short loc_1240\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_1229\nloc_1240:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_126A\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_126A:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_20], rax\nmov [rbp+var_2C], 0\njmp short loc_12BC\nloc_1286:\nmov eax, [rbp+var_2C]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_38]\nadd rdx, rax\nmov eax, [rbp+var_40]\ncdqe\nmov ecx, [rdx+rax*4]\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_2C]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nadd [rbp+var_2C], 1\nloc_12BC:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_3C]\njl short loc_1286\nmov edx, [rbp+var_3C]\nmov rax, [rbp+var_20]\nmov esi, edx\nmov rdi, rax\ncall get_product\nmov rsp, rbx\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njz short loc_12EC\ncall ___stack_chk_fail\nloc_12EC:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, unsigned int a2, int a3)\n{\n unsigned __int64 v3; // rax\n void *v4; // rsp\n int v6; // [rsp+8h] [rbp-40h] BYREF\n unsigned int v7; // [rsp+Ch] [rbp-3Ch]\n __int64 v8; // [rsp+10h] [rbp-38h]\n int i; // [rsp+1Ch] [rbp-2Ch]\n __int64 v10; // [rsp+20h] [rbp-28h]\n int *v11; // [rsp+28h] [rbp-20h]\n unsigned __int64 v12; // [rsp+30h] [rbp-18h]\n\n v8 = a1;\n v7 = a2;\n v6 = a3;\n v12 = __readfsqword(0x28u);\n v10 = (int)a2 - 1LL;\n v3 = 16 * ((4LL * (int)a2 + 15) / 0x10uLL);\n while ( &v6 != (int *)((char *)&v6 - (v3 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v4 = alloca(v3 & 0xFFF);\n if ( (v3 & 0xFFF) != 0 )\n *(_QWORD *)((char *)&v6 + (v3 & 0xFFF) - 8) = *(_QWORD *)((char *)&v6 + (v3 & 0xFFF) - 8);\n v11 = &v6;\n for ( i = 0; i < (int)v7; ++i )\n v11[i] = *(_DWORD *)(v8 + 12LL * i + 4LL * v6);\n return get_product(v11, v7);\n}", + "ida_strip_asm": "sub_11B8:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov [rbp+var_40], edx\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov rax, rsp\nmov rbx, rax\nmov eax, [rbp+var_3C]\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_28], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov esi, 10h\nmov edx, 0\ndiv rsi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_1229:\ncmp rsp, rdx\njz short loc_1240\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_1229\nloc_1240:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_126A\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_126A:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_20], rax\nmov [rbp+var_2C], 0\njmp short loc_12BC\nloc_1286:\nmov eax, [rbp+var_2C]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_38]\nadd rdx, rax\nmov eax, [rbp+var_40]\ncdqe\nmov ecx, [rdx+rax*4]\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_2C]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nadd [rbp+var_2C], 1\nloc_12BC:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_3C]\njl short loc_1286\nmov edx, [rbp+var_3C]\nmov rax, [rbp+var_20]\nmov esi, edx\nmov rdi, rax\ncall sub_1169\nmov rsp, rbx\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njz short loc_12EC\ncall ___stack_chk_fail\nloc_12EC:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11B8(__int64 a1, unsigned int a2, int a3)\n{\n unsigned __int64 v3; // rax\n void *v4; // rsp\n int v6; // [rsp+8h] [rbp-40h] BYREF\n unsigned int v7; // [rsp+Ch] [rbp-3Ch]\n __int64 v8; // [rsp+10h] [rbp-38h]\n int i; // [rsp+1Ch] [rbp-2Ch]\n __int64 v10; // [rsp+20h] [rbp-28h]\n int *v11; // [rsp+28h] [rbp-20h]\n unsigned __int64 v12; // [rsp+30h] [rbp-18h]\n\n v8 = a1;\n v7 = a2;\n v6 = a3;\n v12 = __readfsqword(0x28u);\n v10 = (int)a2 - 1LL;\n v3 = 16 * ((4LL * (int)a2 + 15) / 0x10uLL);\n while ( &v6 != (int *)((char *)&v6 - (v3 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v4 = alloca(v3 & 0xFFF);\n if ( (v3 & 0xFFF) != 0 )\n *(_QWORD *)((char *)&v6 + (v3 & 0xFFF) - 8) = *(_QWORD *)((char *)&v6 + (v3 & 0xFFF) - 8);\n v11 = &v6;\n for ( i = 0; i < (int)v7; ++i )\n v11[i] = *(_DWORD *)(v8 + 12LL * i + 4LL * v6);\n return sub_1169(v11, v7);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11B8(long long a1, unsigned int a2, int a3) {\n unsigned long long v3;\n void *v4;\n int v6;\n unsigned int v7;\n long long v8;\n int i;\n long long v10;\n int *v11;\n unsigned long long v12;\n v8 = a1;\n v7 = a2;\n v6 = a3;\n v12 = __readfsqword(40u);\n v10 = (int)a2 - 1LL;\n v3 = 16 * ((4LL * (int)a2 + 15) / 16uLL);\n while (&v6 != (int *)((char *)&v6 - (v3 & 18446744073709547520LL)))\n ;\n v4 = alloca(v3 & 4095);\n if ((v3 & 4095) != 0)\n *(uint64_t *)((char *)&v6 + (v3 & 4095) - 8) =\n *(uint64_t *)((char *)&v6 + (v3 & 4095) - 8);\n v11 = &v6;\n for (i = 0; i < (int)v7; ++i)\n v11[i] = *(uint32_t *)(v8 + 12LL * i + 4LL * v6);\n return sub_1169(v11, v7);\n}", + "ida_pseudo_norm": "long long func0(long long a1, unsigned int a2, int a3) {\n unsigned long long v3;\n void *v4;\n int v6;\n unsigned int v7;\n long long v8;\n int i;\n long long v10;\n int *v11;\n unsigned long long v12;\n v8 = a1;\n v7 = a2;\n v6 = a3;\n v12 = __readfsqword(40u);\n v10 = (int)a2 - 1LL;\n v3 = 16 * ((4LL * (int)a2 + 15) / 16uLL);\n while (&v6 != (int *)((char *)&v6 - (v3 & 18446744073709547520LL)))\n ;\n v4 = alloca(v3 & 4095);\n if ((v3 & 4095) != 0)\n *(uint64_t *)((char *)&v6 + (v3 & 4095) - 8) =\n *(uint64_t *)((char *)&v6 + (v3 & 4095) - 8);\n v11 = &v6;\n for (i = 0; i < (int)v7; ++i)\n v11[i] = *(uint32_t *)(v8 + 12LL * i + 4LL * v6);\n return get_product(v11, v7);\n}" + }, + { + "index": 645, + "func_name": "func0", + "func_dep": "#include \n\n\n\nint get_product(int val[], int n) {\n\n int res = 1;\n\n for (int i = 0; i < n; i++) {\n\n res *= val[i];\n\n }\n\n return res;\n\n}\n\n\n\n", + "func": "int func0(int test_list[][3], int rows, int K) {\n int temp[rows];\n for (int i = 0; i < rows; i++) {\n temp[i] = test_list[i][K];\n }\n return get_product(temp, rows);\n}", + "test": "int main() {\n\n int test_list1[3][3] = {{5, 6, 7}, {1, 3, 5}, {8, 9, 19}};\n\n assert(func0(test_list1, 3, 2) == 665);\n\n \n\n int test_list2[3][3] = {{6, 7, 8}, {2, 4, 6}, {9, 10, 20}};\n\n assert(func0(test_list2, 3, 1) == 280);\n\n \n\n int test_list3[3][3] = {{7, 8, 9}, {3, 5, 7}, {10, 11, 21}};\n\n assert(func0(test_list3, 3, 0) == 210);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovslq %esi,%rax\nlea 0xf(,%rax,4),%rax\nmov %rax,%rcx\nand $0xfffffffffffffff0,%rcx\nand $0xfffffffffffff000,%rax\nmov %rsp,%r9\nsub %rax,%r9\nmov %r9,%rax\ncmp %rax,%rsp\nje 11ea \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11d3 \nmov %rcx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 1200 \norq $0x0,-0x8(%rsp,%rax,1)\nmov %rsp,%r8\ntest %esi,%esi\njle 122a \nmovslq %edx,%rdx\nlea (%rdi,%rdx,4),%rdx\nmov %r8,%rax\nlea -0x1(%rsi),%ecx\nlea 0x4(%r8,%rcx,4),%rdi\nmov (%rdx),%ecx\nmov %ecx,(%rax)\nadd $0xc,%rdx\nadd $0x4,%rax\ncmp %rdi,%rax\njne 1219 \nmov %r8,%rdi\ncallq 1169 \nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\njne 1243 \nleaveq\nretq\ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov r9, rdi\nmov edi, esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmovsxd rsi, esi\nshl rsi, 2\nlea rax, [rsi+0Fh]\nmov r8, rax\nand r8, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rcx, rsp\nsub rcx, rax\nloc_11D4:\ncmp rsp, rcx\njz short loc_11EB\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11D4\nloc_11EB:\nmov rax, r8\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_1201\nor [rsp+rax+10h+var_18], 0\nloc_1201:\nmov r8, rsp\ntest edi, edi\njle short loc_1226\nmovsxd rdx, edx\nlea rdx, [r9+rdx*4]\nmov rax, r8\nadd rsi, r8\nloc_1215:\nmov ecx, [rdx]\nmov [rax], ecx\nadd rdx, 0Ch\nadd rax, 4\ncmp rax, rsi\njnz short loc_1215\nloc_1226:\nmov esi, edi\nmov rdi, r8\ncall get_product\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_1241\nleave\nretn\nloc_1241:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n __int64 v5; // rsi\n signed __int64 v6; // rax\n void *v7; // rsp\n _DWORD *v8; // rdx\n _DWORD *v9; // rax\n _BYTE *v10; // rsi\n _BYTE v13[8]; // [rsp+8h] [rbp-10h] BYREF\n unsigned __int64 v14; // [rsp+10h] [rbp-8h]\n\n v14 = __readfsqword(0x28u);\n v5 = 4LL * a2;\n while ( v13 != &v13[-((v5 + 15) & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v6 = ((_WORD)v5 + 15) & 0xFF0;\n v7 = alloca(v6);\n if ( (((_WORD)v5 + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v13[v6 - 8] = *(_QWORD *)&v13[v6 - 8];\n if ( a2 > 0 )\n {\n v8 = (_DWORD *)(a1 + 4LL * a3);\n v9 = v13;\n v10 = &v13[v5];\n do\n {\n *v9 = *v8;\n v8 += 3;\n ++v9;\n }\n while ( v9 != (_DWORD *)v10 );\n }\n return get_product(v13, (unsigned int)a2);\n}", + "ida_strip_asm": "sub_1196:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov r9, rdi\nmov edi, esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmovsxd rsi, esi\nshl rsi, 2\nlea rax, [rsi+0Fh]\nmov r8, rax\nand r8, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rcx, rsp\nsub rcx, rax\nloc_11D4:\ncmp rsp, rcx\njz short loc_11EB\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11D4\nloc_11EB:\nmov rax, r8\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_1201\nor [rsp+rax+10h+var_18], 0\nloc_1201:\nmov r8, rsp\ntest edi, edi\njle short loc_1226\nmovsxd rdx, edx\nlea rdx, [r9+rdx*4]\nmov rax, r8\nadd rsi, r8\nloc_1215:\nmov ecx, [rdx]\nmov [rax], ecx\nadd rdx, 0Ch\nadd rax, 4\ncmp rax, rsi\njnz short loc_1215\nloc_1226:\nmov esi, edi\nmov rdi, r8\ncall sub_1169\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_1241\nleave\nretn\nloc_1241:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1196(__int64 a1, int a2, int a3)\n{\n __int64 v5; // rsi\n signed __int64 v6; // rax\n void *v7; // rsp\n _DWORD *v8; // rdx\n _DWORD *v9; // rax\n _BYTE *v10; // rsi\n _BYTE v13[8]; // [rsp+8h] [rbp-10h] BYREF\n unsigned __int64 v14; // [rsp+10h] [rbp-8h]\n\n v14 = __readfsqword(0x28u);\n v5 = 4LL * a2;\n while ( v13 != &v13[-((v5 + 15) & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v6 = ((_WORD)v5 + 15) & 0xFF0;\n v7 = alloca(v6);\n if ( (((_WORD)v5 + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v13[v6 - 8] = *(_QWORD *)&v13[v6 - 8];\n if ( a2 > 0 )\n {\n v8 = (_DWORD *)(a1 + 4LL * a3);\n v9 = v13;\n v10 = &v13[v5];\n do\n {\n *v9 = *v8;\n v8 += 3;\n ++v9;\n }\n while ( v9 != (_DWORD *)v10 );\n }\n return sub_1169(v13, (unsigned int)a2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1196(long long a1, int a2, int a3) {\n long long v5;\n signed long long v6;\n void *v7;\n uint32_t *v8;\n uint32_t *v9;\n uint8_t *v10;\n uint8_t v13[8];\n unsigned long long v14;\n v14 = __readfsqword(40u);\n v5 = 4LL * a2;\n while (v13 != &v13[-((v5 + 15) & 18446744073709547520LL)])\n ;\n v6 = ((unsigned short)v5 + 15) & 4080;\n v7 = alloca(v6);\n if ((((unsigned short)v5 + 15) & 4080) != 0)\n *(uint64_t *)&v13[v6 - 8] = *(uint64_t *)&v13[v6 - 8];\n if (a2 > 0) {\n v8 = (uint32_t *)(a1 + 4LL * a3);\n v9 = v13;\n v10 = &v13[v5];\n do {\n *v9 = *v8;\n v8 += 3;\n ++v9;\n } while (v9 != (uint32_t *)v10);\n }\n return sub_1169(v13, (unsigned int)a2);\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n long long v5;\n signed long long v6;\n void *v7;\n uint32_t *v8;\n uint32_t *v9;\n uint8_t *v10;\n uint8_t v13[8];\n unsigned long long v14;\n v14 = __readfsqword(40u);\n v5 = 4LL * a2;\n while (v13 != &v13[-((v5 + 15) & 18446744073709547520LL)])\n ;\n v6 = ((unsigned short)v5 + 15) & 4080;\n v7 = alloca(v6);\n if ((((unsigned short)v5 + 15) & 4080) != 0)\n *(uint64_t *)&v13[v6 - 8] = *(uint64_t *)&v13[v6 - 8];\n if (a2 > 0) {\n v8 = (uint32_t *)(a1 + 4LL * a3);\n v9 = v13;\n v10 = &v13[v5];\n do {\n *v9 = *v8;\n v8 += 3;\n ++v9;\n } while (v9 != (uint32_t *)v10);\n }\n return get_product(v13, (unsigned int)a2);\n}" + }, + { + "index": 645, + "func_name": "func0", + "func_dep": "#include \n\n\n\nint get_product(int val[], int n) {\n\n int res = 1;\n\n for (int i = 0; i < n; i++) {\n\n res *= val[i];\n\n }\n\n return res;\n\n}\n\n\n\n", + "func": "int func0(int test_list[][3], int rows, int K) {\n int temp[rows];\n for (int i = 0; i < rows; i++) {\n temp[i] = test_list[i][K];\n }\n return get_product(temp, rows);\n}", + "test": "int main() {\n\n int test_list1[3][3] = {{5, 6, 7}, {1, 3, 5}, {8, 9, 19}};\n\n assert(func0(test_list1, 3, 2) == 665);\n\n \n\n int test_list2[3][3] = {{6, 7, 8}, {2, 4, 6}, {9, 10, 20}};\n\n assert(func0(test_list2, 3, 1) == 280);\n\n \n\n int test_list3[3][3] = {{7, 8, 9}, {3, 5, 7}, {10, 11, 21}};\n\n assert(func0(test_list3, 3, 0) == 210);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovslq %esi,%rax\nmov %rsp,%r9\nlea 0xf(,%rax,4),%rax\nmov %rax,%rcx\nand $0xfffffffffffff000,%rax\nsub %rax,%r9\nand $0xfffffffffffffff0,%rcx\nmov %r9,%rax\ncmp %rax,%rsp\nje 11e6 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 11d1 \nand $0xfff,%ecx\nsub %rcx,%rsp\ntest %rcx,%rcx\njne 1258 \nmov %rsp,%rax\ntest %esi,%esi\njle 1260 \nmovslq %edx,%rdx\nlea (%rdi,%rdx,4),%rcx\nlea -0x1(%rsi),%edx\nlea 0x4(%rax,%rdx,4),%rsi\nmov %rax,%rdx\nnopl (%rax)\nmov (%rcx),%edi\nadd $0x4,%rdx\nadd $0xc,%rcx\nmov %edi,-0x4(%rdx)\ncmp %rsi,%rdx\njne 1210 \nmov $0x1,%r8d\nnopl 0x0(%rax,%rax,1)\nimul (%rax),%r8d\nadd $0x4,%rax\ncmp %rsi,%rax\njne 1230 \nmov -0x8(%rbp),%rax\nxor %fs:0x28,%rax\njne 1268 \nleaveq\nmov %r8d,%eax\nretq\nnopl 0x0(%rax)\norq $0x0,-0x8(%rsp,%rcx,1)\njmp 11f4 \nmov $0x1,%r8d\njmp 123d \ncallq 1050 <__stack_chk_fail@plt>\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmovsxd rax, esi\nmov r9, rsp\nshl rax, 2\nlea rcx, [rax+0Fh]\nmov r8, rcx\nand rcx, 0FFFFFFFFFFFFF000h\nsub r9, rcx\nand r8, 0FFFFFFFFFFFFFFF0h\ncmp rsp, r9\njz short loc_1374\nloc_135F:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, r9\njnz short loc_135F\nloc_1374:\nand r8d, 0FFFh\nsub rsp, r8\ntest r8, r8\njnz short loc_13F8\nloc_1383:\nmov r8, rsp\ntest esi, esi\njle short loc_1400\nmovsxd rdx, edx\nlea rsi, [r8+rax]\nmov rcx, r8\nmov rax, r8\nlea rdx, [rdi+rdx*4]\nnop dword ptr [rax+rax+00h]\nloc_13A0:\nmov edi, [rdx]\nadd rax, 4\nadd rdx, 0Ch\nmov [rax-4], edi\ncmp rax, rsi\njnz short loc_13A0\nmov rdx, rsi\nmov eax, 1\nsub rdx, r8\nand edx, 4\njz short loc_13D0\nlea rcx, [r8+4]\nmov eax, [r8]\ncmp rcx, rsi\njz short loc_13E0\nxchg ax, ax\nloc_13D0:\nimul eax, [rcx]\nadd rcx, 8\nimul eax, [rcx-4]\ncmp rcx, rsi\njnz short loc_13D0\nloc_13E0:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_1407\nleave\nretn\nloc_13F8:\nor [rsp+r8+1010h+var_1018], 0\njmp short loc_1383\nloc_1400:\nmov eax, 1\njmp short loc_13E0\nloc_1407:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n __int64 v3; // rax\n unsigned int *v4; // r9\n signed __int64 v5; // r8\n void *v6; // rsp\n unsigned int *v7; // rsi\n unsigned int *v8; // rcx\n unsigned int *v9; // rax\n int *v10; // rdx\n int v11; // edi\n __int64 result; // rax\n int v13; // eax\n __int64 v14; // [rsp+0h] [rbp-1018h]\n unsigned int v15; // [rsp+8h] [rbp-1010h] BYREF\n _BYTE v16[4084]; // [rsp+Ch] [rbp-100Ch] BYREF\n _QWORD v17[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v17[1] = __readfsqword(0x28u);\n v3 = 4LL * a2;\n v4 = (unsigned int *)((char *)v17 - ((v3 + 15) & 0xFFFFFFFFFFFFF000LL));\n if ( v17 != (_QWORD *)v4 )\n {\n while ( &v15 != v4 )\n ;\n }\n v5 = ((_WORD)v3 + 15) & 0xFF0;\n v6 = alloca(v5);\n if ( (((_WORD)v3 + 15) & 0xFF0) != 0 )\n *(__int64 *)((char *)&v14 + v5) = *(__int64 *)((char *)&v14 + v5);\n if ( a2 <= 0 )\n return 1LL;\n v7 = (unsigned int *)&v16[v3 - 4];\n v8 = &v15;\n v9 = &v15;\n v10 = (int *)(a1 + 4LL * a3);\n do\n {\n v11 = *v10;\n ++v9;\n v10 += 3;\n *(v9 - 1) = v11;\n }\n while ( v9 != v7 );\n LODWORD(result) = 1;\n if ( (((_BYTE)v7 - (unsigned __int8)&v15) & 4) == 0 || (v8 = (unsigned int *)v16, result = v15, v16 != (_BYTE *)v7) )\n {\n do\n {\n v13 = *v8 * result;\n v8 += 2;\n result = *(v8 - 1) * v13;\n }\n while ( v8 != v7 );\n }\n return result;\n}", + "ida_strip_asm": "sub_1320:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmovsxd rax, esi\nmov r9, rsp\nshl rax, 2\nlea rcx, [rax+0Fh]\nmov r8, rcx\nand rcx, 0FFFFFFFFFFFFF000h\nsub r9, rcx\nand r8, 0FFFFFFFFFFFFFFF0h\ncmp rsp, r9\njz short loc_1374\nloc_135F:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, r9\njnz short loc_135F\nloc_1374:\nand r8d, 0FFFh\nsub rsp, r8\ntest r8, r8\njnz short loc_13F8\nloc_1383:\nmov r8, rsp\ntest esi, esi\njle short loc_1400\nmovsxd rdx, edx\nlea rsi, [r8+rax]\nmov rcx, r8\nmov rax, r8\nlea rdx, [rdi+rdx*4]\nnop dword ptr [rax+rax+00h]\nloc_13A0:\nmov edi, [rdx]\nadd rax, 4\nadd rdx, 0Ch\nmov [rax-4], edi\ncmp rax, rsi\njnz short loc_13A0\nmov rdx, rsi\nmov eax, 1\nsub rdx, r8\nand edx, 4\njz short loc_13D0\nlea rcx, [r8+4]\nmov eax, [r8]\ncmp rcx, rsi\njz short loc_13E0\nxchg ax, ax\nloc_13D0:\nimul eax, [rcx]\nadd rcx, 8\nimul eax, [rcx-4]\ncmp rcx, rsi\njnz short loc_13D0\nloc_13E0:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_1407\nleave\nretn\nloc_13F8:\nor [rsp+r8+1010h+var_1018], 0\njmp short loc_1383\nloc_1400:\nmov eax, 1\njmp short loc_13E0\nloc_1407:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1320(__int64 a1, int a2, int a3)\n{\n __int64 v3; // rax\n unsigned int *v4; // r9\n signed __int64 v5; // r8\n void *v6; // rsp\n unsigned int *v7; // rsi\n unsigned int *v8; // rcx\n unsigned int *v9; // rax\n int *v10; // rdx\n int v11; // edi\n __int64 result; // rax\n int v13; // eax\n __int64 v14; // [rsp+0h] [rbp-1018h]\n unsigned int v15; // [rsp+8h] [rbp-1010h] BYREF\n _BYTE v16[4084]; // [rsp+Ch] [rbp-100Ch] BYREF\n _QWORD v17[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v17[1] = __readfsqword(0x28u);\n v3 = 4LL * a2;\n v4 = (unsigned int *)((char *)v17 - ((v3 + 15) & 0xFFFFFFFFFFFFF000LL));\n if ( v17 != (_QWORD *)v4 )\n {\n while ( &v15 != v4 )\n ;\n }\n v5 = ((_WORD)v3 + 15) & 0xFF0;\n v6 = alloca(v5);\n if ( (((_WORD)v3 + 15) & 0xFF0) != 0 )\n *(__int64 *)((char *)&v14 + v5) = *(__int64 *)((char *)&v14 + v5);\n if ( a2 <= 0 )\n return 1LL;\n v7 = (unsigned int *)&v16[v3 - 4];\n v8 = &v15;\n v9 = &v15;\n v10 = (int *)(a1 + 4LL * a3);\n do\n {\n v11 = *v10;\n ++v9;\n v10 += 3;\n *(v9 - 1) = v11;\n }\n while ( v9 != v7 );\n LODWORD(result) = 1;\n if ( (((_BYTE)v7 - (unsigned __int8)&v15) & 4) == 0 || (v8 = (unsigned int *)v16, result = v15, v16 != (_BYTE *)v7) )\n {\n do\n {\n v13 = *v8 * result;\n v8 += 2;\n result = *(v8 - 1) * v13;\n }\n while ( v8 != v7 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1320(long long a1, int a2, int a3) {\n long long v3;\n unsigned int *v4;\n signed long long v5;\n void *v6;\n unsigned int *v7;\n unsigned int *v8;\n unsigned int *v9;\n int *v10;\n int v11;\n long long result;\n int v13;\n long long v14;\n unsigned int v15;\n uint8_t v16[4084];\n uint64_t v17[2];\n v17[1] = __readfsqword(40u);\n v3 = 4LL * a2;\n v4 = (unsigned int *)((char *)v17 - ((v3 + 15) & 18446744073709547520LL));\n if (v17 != (uint64_t *)v4) {\n while (&v15 != v4)\n ;\n }\n v5 = ((unsigned short)v3 + 15) & 4080;\n v6 = alloca(v5);\n if ((((unsigned short)v3 + 15) & 4080) != 0)\n *(long long *)((char *)&v14 + v5) = *(long long *)((char *)&v14 + v5);\n if (a2 <= 0) return 1LL;\n v7 = (unsigned int *)&v16[v3 - 4];\n v8 = &v15;\n v9 = &v15;\n v10 = (int *)(a1 + 4LL * a3);\n do {\n v11 = *v10;\n ++v9;\n v10 += 3;\n *(v9 - 1) = v11;\n } while (v9 != v7);\n LODWORD(result) = 1;\n if ((((uint8_t)v7 - (unsigned char)&v15) & 4) == 0 ||\n (v8 = (unsigned int *)v16, result = v15, v16 != (uint8_t *)v7)) {\n do {\n v13 = *v8 * result;\n v8 += 2;\n result = *(v8 - 1) * v13;\n } while (v8 != v7);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n long long v3;\n unsigned int *v4;\n signed long long v5;\n void *v6;\n unsigned int *v7;\n unsigned int *v8;\n unsigned int *v9;\n int *v10;\n int v11;\n long long result;\n int v13;\n long long v14;\n unsigned int v15;\n uint8_t v16[4084];\n uint64_t v17[2];\n v17[1] = __readfsqword(40u);\n v3 = 4LL * a2;\n v4 = (unsigned int *)((char *)v17 - ((v3 + 15) & 18446744073709547520LL));\n if (v17 != (uint64_t *)v4) {\n while (&v15 != v4)\n ;\n }\n v5 = ((unsigned short)v3 + 15) & 4080;\n v6 = alloca(v5);\n if ((((unsigned short)v3 + 15) & 4080) != 0)\n *(long long *)((char *)&v14 + v5) = *(long long *)((char *)&v14 + v5);\n if (a2 <= 0) return 1LL;\n v7 = (unsigned int *)&v16[v3 - 4];\n v8 = &v15;\n v9 = &v15;\n v10 = (int *)(a1 + 4LL * a3);\n do {\n v11 = *v10;\n ++v9;\n v10 += 3;\n *(v9 - 1) = v11;\n } while (v9 != v7);\n LODWORD(result) = 1;\n if ((((uint8_t)v7 - (unsigned char)&v15) & 4) == 0 ||\n (v8 = (unsigned int *)v16, result = v15, v16 != (uint8_t *)v7)) {\n do {\n v13 = *v8 * result;\n v8 += 2;\n result = *(v8 - 1) * v13;\n } while (v8 != v7);\n }\n return result;\n}" + }, + { + "index": 645, + "func_name": "func0", + "func_dep": "#include \n\n\n\nint get_product(int val[], int n) {\n\n int res = 1;\n\n for (int i = 0; i < n; i++) {\n\n res *= val[i];\n\n }\n\n return res;\n\n}\n\n\n\n", + "func": "int func0(int test_list[][3], int rows, int K) {\n int temp[rows];\n for (int i = 0; i < rows; i++) {\n temp[i] = test_list[i][K];\n }\n return get_product(temp, rows);\n}", + "test": "int main() {\n\n int test_list1[3][3] = {{5, 6, 7}, {1, 3, 5}, {8, 9, 19}};\n\n assert(func0(test_list1, 3, 2) == 665);\n\n \n\n int test_list2[3][3] = {{6, 7, 8}, {2, 4, 6}, {9, 10, 20}};\n\n assert(func0(test_list2, 3, 1) == 280);\n\n \n\n int test_list3[3][3] = {{7, 8, 9}, {3, 5, 7}, {10, 11, 21}};\n\n assert(func0(test_list3, 3, 0) == 210);\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovslq %esi,%rax\nmov %rsp,%r11\nlea 0xf(,%rax,4),%rax\nmov %rax,%rcx\nand $0xfffffffffffff000,%rax\nsub %rax,%r11\nand $0xfffffffffffffff0,%rcx\nmov %r11,%rax\ncmp %rax,%rsp\nje 1296 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 1281 \nand $0xfff,%ecx\nsub %rcx,%rsp\ntest %rcx,%rcx\njne 1420 \nmov %rsp,%rcx\ntest %esi,%esi\njle 142b \nlea -0x1(%rsi),%r10d\ncmp $0x2,%r10d\njbe 1433 \nmov %esi,%r8d\nmovslq %edx,%r9\nmov %rcx,%rdx\nshr $0x2,%r8d\nlea (%rdi,%r9,4),%rax\nshl $0x4,%r8\nadd %rcx,%r8\nnopl 0x0(%rax)\nmovd 0x18(%rax),%xmm1\nmovd 0x24(%rax),%xmm3\nadd $0x10,%rdx\nadd $0x30,%rax\nmovd -0x30(%rax),%xmm0\nmovd -0x24(%rax),%xmm4\npunpckldq %xmm3,%xmm1\npunpckldq %xmm4,%xmm0\npunpcklqdq %xmm1,%xmm0\nmovups %xmm0,-0x10(%rdx)\ncmp %r8,%rdx\njne 12e0 \nmov %esi,%eax\nand $0xfffffffc,%eax\ntest $0x3,%sil\nje 1353 \nmovslq %eax,%rdx\nlea (%rdi,%r9,4),%rdi\nlea (%rdx,%rdx,2),%r8\nlea (%rdi,%r8,4),%rdi\nmov (%rdi),%r8d\nmov %r8d,(%rcx,%rdx,4)\nlea 0x1(%rax),%edx\ncmp %edx,%esi\njle 1353 \nmov 0xc(%rdi),%r8d\nmovslq %edx,%rdx\nadd $0x2,%eax\nmov %r8d,(%rcx,%rdx,4)\ncmp %eax,%esi\njle 1353 \nmov 0x18(%rdi),%edx\ncltq\nmov %edx,(%rcx,%rax,4)\ncmp $0x1c,%r10d\njbe 143d \nmov %esi,%edx\nmovdqa 0xca9(%rip),%xmm1\nmov %rcx,%rax\nshr $0x2,%edx\nshl $0x4,%rdx\nadd %rcx,%rdx\nnopl 0x0(%rax)\nmovdqu (%rax),%xmm2\nmovdqu (%rax),%xmm0\nadd $0x10,%rax\npmuludq %xmm1,%xmm2\npsrlq $0x20,%xmm0\npsrlq $0x20,%xmm1\npmuludq %xmm1,%xmm0\npshufd $0x8,%xmm2,%xmm1\npshufd $0x8,%xmm0,%xmm0\npunpckldq %xmm0,%xmm1\ncmp %rdx,%rax\njne 1378 \nmovdqa %xmm1,%xmm2\nmovdqa %xmm1,%xmm0\nmov %esi,%eax\npsrldq $0x8,%xmm2\npsrlq $0x20,%xmm1\nand $0xfffffffc,%eax\npmuludq %xmm2,%xmm0\npsrlq $0x20,%xmm2\npmuludq %xmm2,%xmm1\npshufd $0x8,%xmm0,%xmm0\npshufd $0x8,%xmm1,%xmm1\npunpckldq %xmm1,%xmm0\nmovdqa %xmm0,%xmm1\npsrldq $0x4,%xmm1\npmuludq %xmm1,%xmm0\nmovd %xmm0,%r8d\ntest $0x3,%sil\nje 1405 \ncltq\nnopl (%rax)\nimul (%rcx,%rax,4),%r8d\nadd $0x1,%rax\ncmp %eax,%esi\njg 13f8 \nmov -0x8(%rbp),%rax\nxor %fs:0x28,%rax\njne 1447 \nleaveq\nmov %r8d,%eax\nretq\nnopl 0x0(%rax)\norq $0x0,-0x8(%rsp,%rcx,1)\njmpq 12a8 \nmov $0x1,%r8d\njmp 1405 \nxor %eax,%eax\nmovslq %edx,%r9\njmpq 131c \nmov $0x1,%r8d\nxor %eax,%eax\njmp 13f3 \ncallq 1050 <__stack_chk_fail@plt>\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov r9, rdi\nmov ecx, esi\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmovsxd rax, esi\nmov rdi, rsp\nlea rax, ds:0Fh[rax*4]\nmov rsi, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rdi, rax\nand rsi, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rdi\njz short loc_12C8\nloc_12B3:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rdi\njnz short loc_12B3\nloc_12C8:\nand esi, 0FFFh\nsub rsp, rsi\ntest rsi, rsi\njnz loc_1488\nloc_12DA:\nmov rdi, rsp\ntest ecx, ecx\njle loc_1493\nlea r10d, [rcx-1]\ncmp r10d, 3\njbe loc_149A\nmov esi, r10d\nmovsxd r8, edx\nmov rdx, rdi\nshr esi, 2\nlea rax, [r9+r8*4]\nshl rsi, 4\nadd rsi, rdi\nnop word ptr [rax+rax+00h]\nloc_1310:\nmovdqu xmm3, xmmword ptr [rax]\nmovdqu xmm1, xmmword ptr [rax+10h]\nadd rdx, 10h\nadd rax, 30h ; '0'\nmovdqa xmm0, xmm3\nshufps xmm1, xmm3, 0Ah\nshufps xmm0, xmm1, 8Ch\nmovdqu xmm1, xmmword ptr [rax-10h]\nshufps xmm1, xmm0, 0A5h\nshufps xmm0, xmm1, 24h ; '$'\nmovups xmmword ptr [rdx-10h], xmm0\ncmp rdx, rsi\njnz short loc_1310\nmov eax, r10d\nand eax, 0FFFFFFFCh\nloc_1349:\nmovsxd rdx, eax\nlea rsi, [rdx+rdx*2]\nlea rdx, [rdi+rdx*4]\nlea rsi, [r9+rsi*4]\nlea rsi, [rsi+r8*4]\nmov r8d, [rsi]\nmov [rdx], r8d\nlea r8d, [rax+1]\ncmp ecx, r8d\njle short loc_1391\nmov r8d, [rsi+0Ch]\nmov [rdx+4], r8d\nlea r8d, [rax+2]\ncmp ecx, r8d\njle short loc_1391\nmov r8d, [rsi+18h]\nadd eax, 3\nmov [rdx+8], r8d\ncmp ecx, eax\njle short loc_1391\nmov eax, [rsi+24h]\nmov [rdx+0Ch], eax\nloc_1391:\ncmp r10d, 1Ah\njbe loc_14A4\nmov edx, ecx\nmovdqa xmm1, cs:xmmword_2010\nmov rax, rdi\nshr edx, 2\nshl rdx, 4\nadd rdx, rdi\nnop word ptr [rax+rax+00h]\nloc_13B8:\nmovdqu xmm2, xmmword ptr [rax]\nmovdqu xmm0, xmmword ptr [rax]\nadd rax, 10h\npmuludq xmm2, xmm1\npsrlq xmm0, 20h ; ' '\npsrlq xmm1, 20h ; ' '\npmuludq xmm0, xmm1\npshufd xmm1, xmm2, 8\npshufd xmm0, xmm0, 8\npunpckldq xmm1, xmm0\ncmp rax, rdx\njnz short loc_13B8\nmovdqa xmm0, xmm1\npsrldq xmm0, 8\nmovdqa xmm2, xmm0\npsrlq xmm0, 20h ; ' '\npmuludq xmm2, xmm1\npsrlq xmm1, 20h ; ' '\npmuludq xmm0, xmm1\npshufd xmm1, xmm2, 8\npshufd xmm0, xmm0, 8\npunpckldq xmm1, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm0, 4\npmuludq xmm0, xmm1\nmovd edx, xmm0\ntest cl, 3\njz short loc_1471\nmov eax, ecx\nand eax, 0FFFFFFFCh\nloc_1431:\ncdqe\nmov rsi, rax\nimul edx, [rdi+rax*4]\nadd rax, 1\nnot rsi\nadd esi, ecx\nand esi, 1\ncmp ecx, eax\njle short loc_1471\ntest esi, esi\njz short loc_1460\nimul edx, [rdi+rax*4]\nadd rax, 1\ncmp ecx, eax\njle short loc_1471\nnop word ptr [rax+rax+00h]\nloc_1460:\nimul edx, [rdi+rax*4]\nimul edx, [rdi+rax*4+4]\nadd rax, 2\ncmp ecx, eax\njg short loc_1460\nloc_1471:\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njnz short loc_14AD\nleave\nmov eax, edx\nretn\nloc_1488:\nor [rsp+rsi+1010h+var_1018], 0\njmp loc_12DA\nloc_1493:\nmov edx, 1\njmp short loc_1471\nloc_149A:\nxor eax, eax\nmovsxd r8, edx\njmp loc_1349\nloc_14A4:\nmov edx, 1\nxor eax, eax\njmp short loc_1431\nloc_14AD:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n __int64 v5; // rsi\n _DWORD *v6; // rdi\n __int16 v7; // si\n signed __int64 v8; // rsi\n void *v9; // rsp\n unsigned int v10; // r10d\n __int64 v11; // r8\n __m128 *v12; // rdx\n const __m128i *v13; // rax\n __m128 v14; // xmm3\n __m128 v15; // xmm1\n __m128 v16; // xmm0\n signed int v17; // eax\n _DWORD *v18; // rdx\n _DWORD *v19; // rsi\n __m128i si128; // xmm1\n const __m128i *v21; // rax\n __m128i v22; // xmm2\n __m128i v23; // xmm2\n __m128i v24; // xmm1\n unsigned int v25; // edx\n int v26; // eax\n char v27; // si\n __int64 v28; // rax\n int v29; // esi\n _DWORD v32[1022]; // [rsp+8h] [rbp-1010h] BYREF\n _QWORD v33[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v33[1] = __readfsqword(0x28u);\n v5 = 4LL * a2 + 15;\n v6 = (_DWORD *)((char *)v33 - (v5 & 0xFFFFFFFFFFFFF000LL));\n v7 = v5 & 0xFFF0;\n if ( v33 != (_QWORD *)v6 )\n {\n while ( v32 != v6 )\n ;\n }\n v8 = v7 & 0xFFF;\n v9 = alloca(v8);\n if ( v8 )\n *(_QWORD *)((char *)&v32[-2] + v8) = *(_QWORD *)((char *)&v32[-2] + v8);\n if ( a2 <= 0 )\n return 1;\n v10 = a2 - 1;\n if ( (unsigned int)(a2 - 1) <= 3 )\n {\n v17 = 0;\n v11 = a3;\n }\n else\n {\n v11 = a3;\n v12 = (__m128 *)v32;\n v13 = (const __m128i *)(a1 + 4 * v11);\n do\n {\n v14 = (__m128)_mm_loadu_si128(v13);\n v15 = (__m128)_mm_loadu_si128(v13 + 1);\n ++v12;\n v13 += 3;\n v16 = _mm_shuffle_ps(v14, _mm_shuffle_ps(v15, v14, 10), 140);\n v12[-1] = _mm_shuffle_ps(v16, _mm_shuffle_ps((__m128)_mm_loadu_si128(v13 - 1), v16, 165), 36);\n }\n while ( v12 != (__m128 *)&v32[4 * (v10 >> 2)] );\n v17 = v10 & 0xFFFFFFFC;\n }\n v18 = &v32[v17];\n v19 = (_DWORD *)(a1 + 12LL * v17 + 4 * v11);\n *v18 = *v19;\n if ( a2 > v17 + 1 )\n {\n v18[1] = v19[3];\n if ( a2 > v17 + 2 )\n {\n v18[2] = v19[6];\n if ( a2 > v17 + 3 )\n v18[3] = v19[9];\n }\n }\n if ( v10 <= 0x1A )\n {\n v25 = 1;\n v26 = 0;\n }\n else\n {\n si128 = _mm_load_si128((const __m128i *)&xmmword_2010);\n v21 = (const __m128i *)v32;\n do\n {\n v22 = _mm_loadu_si128(v21++);\n si128 = _mm_unpacklo_epi32(\n _mm_shuffle_epi32(_mm_mul_epu32(v22, si128), 8),\n _mm_shuffle_epi32(_mm_mul_epu32(_mm_srli_epi64(v22, 0x20u), _mm_srli_epi64(si128, 0x20u)), 8));\n }\n while ( v21 != (const __m128i *)&v32[4 * ((unsigned int)a2 >> 2)] );\n v23 = _mm_srli_si128(si128, 8);\n v24 = _mm_unpacklo_epi32(\n _mm_shuffle_epi32(_mm_mul_epu32(v23, si128), 8),\n _mm_shuffle_epi32(_mm_mul_epu32(_mm_srli_epi64(v23, 0x20u), _mm_srli_epi64(si128, 0x20u)), 8));\n v25 = _mm_cvtsi128_si32(_mm_mul_epu32(_mm_srli_si128(v24, 4), v24));\n if ( (a2 & 3) == 0 )\n return v25;\n v26 = a2 & 0x7FFFFFFC;\n }\n v27 = v26;\n v25 *= v32[v26];\n v28 = v26 + 1LL;\n v29 = ((_BYTE)a2 + ~v27) & 1;\n if ( a2 > (int)v28 )\n {\n if ( !v29 || (v25 *= v32[v28], ++v28, a2 > (int)v28) )\n {\n do\n {\n v25 *= v32[v28 + 1] * v32[v28];\n v28 += 2LL;\n }\n while ( a2 > (int)v28 );\n }\n }\n return v25;\n}", + "ida_strip_asm": "sub_1270:\nendbr64\npush rbp\nmov r9, rdi\nmov ecx, esi\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmovsxd rax, esi\nmov rdi, rsp\nlea rax, ds:0Fh[rax*4]\nmov rsi, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rdi, rax\nand rsi, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rdi\njz short loc_12C8\nloc_12B3:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rdi\njnz short loc_12B3\nloc_12C8:\nand esi, 0FFFh\nsub rsp, rsi\ntest rsi, rsi\njnz loc_1488\nloc_12DA:\nmov rdi, rsp\ntest ecx, ecx\njle loc_1493\nlea r10d, [rcx-1]\ncmp r10d, 3\njbe loc_149A\nmov esi, r10d\nmovsxd r8, edx\nmov rdx, rdi\nshr esi, 2\nlea rax, [r9+r8*4]\nshl rsi, 4\nadd rsi, rdi\nnop word ptr [rax+rax+00h]\nloc_1310:\nmovdqu xmm3, xmmword ptr [rax]\nmovdqu xmm1, xmmword ptr [rax+10h]\nadd rdx, 10h\nadd rax, 30h ; '0'\nmovdqa xmm0, xmm3\nshufps xmm1, xmm3, 0Ah\nshufps xmm0, xmm1, 8Ch\nmovdqu xmm1, xmmword ptr [rax-10h]\nshufps xmm1, xmm0, 0A5h\nshufps xmm0, xmm1, 24h ; '$'\nmovups xmmword ptr [rdx-10h], xmm0\ncmp rdx, rsi\njnz short loc_1310\nmov eax, r10d\nand eax, 0FFFFFFFCh\nloc_1349:\nmovsxd rdx, eax\nlea rsi, [rdx+rdx*2]\nlea rdx, [rdi+rdx*4]\nlea rsi, [r9+rsi*4]\nlea rsi, [rsi+r8*4]\nmov r8d, [rsi]\nmov [rdx], r8d\nlea r8d, [rax+1]\ncmp ecx, r8d\njle short loc_1391\nmov r8d, [rsi+0Ch]\nmov [rdx+4], r8d\nlea r8d, [rax+2]\ncmp ecx, r8d\njle short loc_1391\nmov r8d, [rsi+18h]\nadd eax, 3\nmov [rdx+8], r8d\ncmp ecx, eax\njle short loc_1391\nmov eax, [rsi+24h]\nmov [rdx+0Ch], eax\nloc_1391:\ncmp r10d, 1Ah\njbe loc_14A4\nmov edx, ecx\nmovdqa xmm1, cs:xmmword_2010\nmov rax, rdi\nshr edx, 2\nshl rdx, 4\nadd rdx, rdi\nnop word ptr [rax+rax+00h]\nloc_13B8:\nmovdqu xmm2, xmmword ptr [rax]\nmovdqu xmm0, xmmword ptr [rax]\nadd rax, 10h\npmuludq xmm2, xmm1\npsrlq xmm0, 20h ; ' '\npsrlq xmm1, 20h ; ' '\npmuludq xmm0, xmm1\npshufd xmm1, xmm2, 8\npshufd xmm0, xmm0, 8\npunpckldq xmm1, xmm0\ncmp rax, rdx\njnz short loc_13B8\nmovdqa xmm0, xmm1\npsrldq xmm0, 8\nmovdqa xmm2, xmm0\npsrlq xmm0, 20h ; ' '\npmuludq xmm2, xmm1\npsrlq xmm1, 20h ; ' '\npmuludq xmm0, xmm1\npshufd xmm1, xmm2, 8\npshufd xmm0, xmm0, 8\npunpckldq xmm1, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm0, 4\npmuludq xmm0, xmm1\nmovd edx, xmm0\ntest cl, 3\njz short loc_1471\nmov eax, ecx\nand eax, 0FFFFFFFCh\nloc_1431:\ncdqe\nmov rsi, rax\nimul edx, [rdi+rax*4]\nadd rax, 1\nnot rsi\nadd esi, ecx\nand esi, 1\ncmp ecx, eax\njle short loc_1471\ntest esi, esi\njz short loc_1460\nimul edx, [rdi+rax*4]\nadd rax, 1\ncmp ecx, eax\njle short loc_1471\nnop word ptr [rax+rax+00h]\nloc_1460:\nimul edx, [rdi+rax*4]\nimul edx, [rdi+rax*4+4]\nadd rax, 2\ncmp ecx, eax\njg short loc_1460\nloc_1471:\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njnz short loc_14AD\nleave\nmov eax, edx\nretn\nloc_1488:\nor [rsp+rsi+1010h+var_1018], 0\njmp loc_12DA\nloc_1493:\nmov edx, 1\njmp short loc_1471\nloc_149A:\nxor eax, eax\nmovsxd r8, edx\njmp loc_1349\nloc_14A4:\nmov edx, 1\nxor eax, eax\njmp short loc_1431\nloc_14AD:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1270(__int64 a1, int a2, int a3)\n{\n __int64 v5; // rsi\n _DWORD *v6; // rdi\n __int16 v7; // si\n signed __int64 v8; // rsi\n void *v9; // rsp\n unsigned int v10; // r10d\n __int64 v11; // r8\n __m128 *v12; // rdx\n const __m128i *v13; // rax\n __m128 v14; // xmm3\n __m128 v15; // xmm1\n __m128 v16; // xmm0\n signed int v17; // eax\n _DWORD *v18; // rdx\n _DWORD *v19; // rsi\n __m128i si128; // xmm1\n const __m128i *v21; // rax\n __m128i v22; // xmm2\n __m128i v23; // xmm2\n __m128i v24; // xmm1\n unsigned int v25; // edx\n int v26; // eax\n char v27; // si\n __int64 v28; // rax\n int v29; // esi\n _DWORD v32[1022]; // [rsp+8h] [rbp-1010h] BYREF\n _QWORD v33[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v33[1] = __readfsqword(0x28u);\n v5 = 4LL * a2 + 15;\n v6 = (_DWORD *)((char *)v33 - (v5 & 0xFFFFFFFFFFFFF000LL));\n v7 = v5 & 0xFFF0;\n if ( v33 != (_QWORD *)v6 )\n {\n while ( v32 != v6 )\n ;\n }\n v8 = v7 & 0xFFF;\n v9 = alloca(v8);\n if ( v8 )\n *(_QWORD *)((char *)&v32[-2] + v8) = *(_QWORD *)((char *)&v32[-2] + v8);\n if ( a2 <= 0 )\n return 1;\n v10 = a2 - 1;\n if ( (unsigned int)(a2 - 1) <= 3 )\n {\n v17 = 0;\n v11 = a3;\n }\n else\n {\n v11 = a3;\n v12 = (__m128 *)v32;\n v13 = (const __m128i *)(a1 + 4 * v11);\n do\n {\n v14 = (__m128)_mm_loadu_si128(v13);\n v15 = (__m128)_mm_loadu_si128(v13 + 1);\n ++v12;\n v13 += 3;\n v16 = _mm_shuffle_ps(v14, _mm_shuffle_ps(v15, v14, 10), 140);\n v12[-1] = _mm_shuffle_ps(v16, _mm_shuffle_ps((__m128)_mm_loadu_si128(v13 - 1), v16, 165), 36);\n }\n while ( v12 != (__m128 *)&v32[4 * (v10 >> 2)] );\n v17 = v10 & 0xFFFFFFFC;\n }\n v18 = &v32[v17];\n v19 = (_DWORD *)(a1 + 12LL * v17 + 4 * v11);\n *v18 = *v19;\n if ( a2 > v17 + 1 )\n {\n v18[1] = v19[3];\n if ( a2 > v17 + 2 )\n {\n v18[2] = v19[6];\n if ( a2 > v17 + 3 )\n v18[3] = v19[9];\n }\n }\n if ( v10 <= 0x1A )\n {\n v25 = 1;\n v26 = 0;\n }\n else\n {\n si128 = _mm_load_si128((const __m128i *)&xmmword_2010);\n v21 = (const __m128i *)v32;\n do\n {\n v22 = _mm_loadu_si128(v21++);\n si128 = _mm_unpacklo_epi32(\n _mm_shuffle_epi32(_mm_mul_epu32(v22, si128), 8),\n _mm_shuffle_epi32(_mm_mul_epu32(_mm_srli_epi64(v22, 0x20u), _mm_srli_epi64(si128, 0x20u)), 8));\n }\n while ( v21 != (const __m128i *)&v32[4 * ((unsigned int)a2 >> 2)] );\n v23 = _mm_srli_si128(si128, 8);\n v24 = _mm_unpacklo_epi32(\n _mm_shuffle_epi32(_mm_mul_epu32(v23, si128), 8),\n _mm_shuffle_epi32(_mm_mul_epu32(_mm_srli_epi64(v23, 0x20u), _mm_srli_epi64(si128, 0x20u)), 8));\n v25 = _mm_cvtsi128_si32(_mm_mul_epu32(_mm_srli_si128(v24, 4), v24));\n if ( (a2 & 3) == 0 )\n return v25;\n v26 = a2 & 0x7FFFFFFC;\n }\n v27 = v26;\n v25 *= v32[v26];\n v28 = v26 + 1LL;\n v29 = ((_BYTE)a2 + ~v27) & 1;\n if ( a2 > (int)v28 )\n {\n if ( !v29 || (v25 *= v32[v28], ++v28, a2 > (int)v28) )\n {\n do\n {\n v25 *= v32[v28 + 1] * v32[v28];\n v28 += 2LL;\n }\n while ( a2 > (int)v28 );\n }\n }\n return v25;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1270(long long a1, int a2, int a3) {\n long long v5;\n uint32_t *v6;\n short v7;\n signed long long v8;\n void *v9;\n unsigned int v10;\n long long v11;\n __m128 *v12;\n const __m128i *v13;\n __m128 v14;\n __m128 v15;\n __m128 v16;\n signed int v17;\n uint32_t *v18;\n uint32_t *v19;\n __m128i si128;\n const __m128i *v21;\n __m128i v22;\n __m128i v23;\n __m128i v24;\n unsigned int v25;\n int v26;\n char v27;\n long long v28;\n int v29;\n uint32_t v32[1022];\n uint64_t v33[2];\n v33[1] = __readfsqword(40u);\n v5 = 4LL * a2 + 15;\n v6 = (uint32_t *)((char *)v33 - (v5 & 18446744073709547520LL));\n v7 = v5 & 65520;\n if (v33 != (uint64_t *)v6) {\n while (v32 != v6)\n ;\n }\n v8 = v7 & 4095;\n v9 = alloca(v8);\n if (v8)\n *(uint64_t *)((char *)&v32[-2] + v8) = *(uint64_t *)((char *)&v32[-2] + v8);\n if (a2 <= 0) return 1;\n v10 = a2 - 1;\n if ((unsigned int)(a2 - 1) <= 3) {\n v17 = 0;\n v11 = a3;\n } else {\n v11 = a3;\n v12 = (__m128 *)v32;\n v13 = (const __m128i *)(a1 + 4 * v11);\n do {\n v14 = (__m128)_mm_loadu_si128(v13);\n v15 = (__m128)_mm_loadu_si128(v13 + 1);\n ++v12;\n v13 += 3;\n v16 = _mm_shuffle_ps(v14, _mm_shuffle_ps(v15, v14, 10), 140);\n v12[-1] = _mm_shuffle_ps(\n v16, _mm_shuffle_ps((__m128)_mm_loadu_si128(v13 - 1), v16, 165), 36);\n } while (v12 != (__m128 *)&v32[4 * (v10 >> 2)]);\n v17 = v10 & 4294967292;\n }\n v18 = &v32[v17];\n v19 = (uint32_t *)(a1 + 12LL * v17 + 4 * v11);\n *v18 = *v19;\n if (a2 > v17 + 1) {\n v18[1] = v19[3];\n if (a2 > v17 + 2) {\n v18[2] = v19[6];\n if (a2 > v17 + 3) v18[3] = v19[9];\n }\n }\n if (v10 <= 26) {\n v25 = 1;\n v26 = 0;\n } else {\n si128 = _mm_load_si128((const __m128i *)&xmmword_2010);\n v21 = (const __m128i *)v32;\n do {\n v22 = _mm_loadu_si128(v21++);\n si128 = _mm_unpacklo_epi32(\n _mm_shuffle_epi32(_mm_mul_epu32(v22, si128), 8),\n _mm_shuffle_epi32(_mm_mul_epu32(_mm_srli_epi64(v22, 32u),\n _mm_srli_epi64(si128, 32u)),\n 8));\n } while (v21 != (const __m128i *)&v32[4 * ((unsigned int)a2 >> 2)]);\n v23 = _mm_srli_si128(si128, 8);\n v24 = _mm_unpacklo_epi32(\n _mm_shuffle_epi32(_mm_mul_epu32(v23, si128), 8),\n _mm_shuffle_epi32(\n _mm_mul_epu32(_mm_srli_epi64(v23, 32u), _mm_srli_epi64(si128, 32u)),\n 8));\n v25 = _mm_cvtsi128_si32(_mm_mul_epu32(_mm_srli_si128(v24, 4), v24));\n if ((a2 & 3) == 0) return v25;\n v26 = a2 & 2147483644;\n }\n v27 = v26;\n v25 *= v32[v26];\n v28 = v26 + 1LL;\n v29 = ((uint8_t)a2 + ~v27) & 1;\n if (a2 > (int)v28) {\n if (!v29 || (v25 *= v32[v28], ++v28, a2 > (int)v28)) {\n do {\n v25 *= v32[v28 + 1] * v32[v28];\n v28 += 2LL;\n } while (a2 > (int)v28);\n }\n }\n return v25;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n long long v5;\n uint32_t *v6;\n short v7;\n signed long long v8;\n void *v9;\n unsigned int v10;\n long long v11;\n __m128 *v12;\n const __m128i *v13;\n __m128 v14;\n __m128 v15;\n __m128 v16;\n signed int v17;\n uint32_t *v18;\n uint32_t *v19;\n __m128i si128;\n const __m128i *v21;\n __m128i v22;\n __m128i v23;\n __m128i v24;\n unsigned int v25;\n int v26;\n char v27;\n long long v28;\n int v29;\n uint32_t v32[1022];\n uint64_t v33[2];\n v33[1] = __readfsqword(40u);\n v5 = 4LL * a2 + 15;\n v6 = (uint32_t *)((char *)v33 - (v5 & 18446744073709547520LL));\n v7 = v5 & 65520;\n if (v33 != (uint64_t *)v6) {\n while (v32 != v6)\n ;\n }\n v8 = v7 & 4095;\n v9 = alloca(v8);\n if (v8)\n *(uint64_t *)((char *)&v32[-2] + v8) = *(uint64_t *)((char *)&v32[-2] + v8);\n if (a2 <= 0) return 1;\n v10 = a2 - 1;\n if ((unsigned int)(a2 - 1) <= 3) {\n v17 = 0;\n v11 = a3;\n } else {\n v11 = a3;\n v12 = (__m128 *)v32;\n v13 = (const __m128i *)(a1 + 4 * v11);\n do {\n v14 = (__m128)_mm_loadu_si128(v13);\n v15 = (__m128)_mm_loadu_si128(v13 + 1);\n ++v12;\n v13 += 3;\n v16 = _mm_shuffle_ps(v14, _mm_shuffle_ps(v15, v14, 10), 140);\n v12[-1] = _mm_shuffle_ps(\n v16, _mm_shuffle_ps((__m128)_mm_loadu_si128(v13 - 1), v16, 165), 36);\n } while (v12 != (__m128 *)&v32[4 * (v10 >> 2)]);\n v17 = v10 & 4294967292;\n }\n v18 = &v32[v17];\n v19 = (uint32_t *)(a1 + 12LL * v17 + 4 * v11);\n *v18 = *v19;\n if (a2 > v17 + 1) {\n v18[1] = v19[3];\n if (a2 > v17 + 2) {\n v18[2] = v19[6];\n if (a2 > v17 + 3) v18[3] = v19[9];\n }\n }\n if (v10 <= 26) {\n v25 = 1;\n v26 = 0;\n } else {\n si128 = _mm_load_si128((const __m128i *)&xmmword_2010);\n v21 = (const __m128i *)v32;\n do {\n v22 = _mm_loadu_si128(v21++);\n si128 = _mm_unpacklo_epi32(\n _mm_shuffle_epi32(_mm_mul_epu32(v22, si128), 8),\n _mm_shuffle_epi32(_mm_mul_epu32(_mm_srli_epi64(v22, 32u),\n _mm_srli_epi64(si128, 32u)),\n 8));\n } while (v21 != (const __m128i *)&v32[4 * ((unsigned int)a2 >> 2)]);\n v23 = _mm_srli_si128(si128, 8);\n v24 = _mm_unpacklo_epi32(\n _mm_shuffle_epi32(_mm_mul_epu32(v23, si128), 8),\n _mm_shuffle_epi32(\n _mm_mul_epu32(_mm_srli_epi64(v23, 32u), _mm_srli_epi64(si128, 32u)),\n 8));\n v25 = _mm_cvtsi128_si32(_mm_mul_epu32(_mm_srli_si128(v24, 4), v24));\n if ((a2 & 3) == 0) return v25;\n v26 = a2 & 2147483644;\n }\n v27 = v26;\n v25 *= v32[v26];\n v28 = v26 + 1LL;\n v29 = ((uint8_t)a2 + ~v27) & 1;\n if (a2 > (int)v28) {\n if (!v29 || (v25 *= v32[v28], ++v28, a2 > (int)v28)) {\n do {\n v25 *= v32[v28 + 1] * v32[v28];\n v28 += 2LL;\n } while (a2 > (int)v28);\n }\n }\n return v25;\n}" + }, + { + "index": 646, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(int N, int K) {\n int No = 0;\n No = (N - K + 1);\n No = pow(No, 3);\n return No;\n}", + "test": "int main() {\n\n assert(func0(2, 1) == 8);\n\n assert(func0(5, 2) == 64);\n\n assert(func0(1, 1) == 1);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmovl $0x0,-0x4(%rbp)\nmov -0x14(%rbp),%eax\nsub -0x18(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x4(%rbp)\ncvtsi2sdl -0x4(%rbp),%xmm0\nmovsd 0xee5(%rip),%xmm1\ncallq 1060 \ncvttsd2si %xmm0,%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_4], 0\nmov eax, [rbp+var_14]\nsub eax, [rbp+var_18]\nadd eax, 1\nmov [rbp+var_4], eax\npxor xmm2, xmm2\ncvtsi2sd xmm2, [rbp+var_4]\nmovq rax, xmm2\nmovsd xmm0, cs:y\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\ncvttsd2si eax, xmm0\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n return (unsigned int)(int)pow((double)(a1 - a2 + 1), 3.0);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_4], 0\nmov eax, [rbp+var_14]\nsub eax, [rbp+var_18]\nadd eax, 1\nmov [rbp+var_4], eax\npxor xmm2, xmm2\ncvtsi2sd xmm2, [rbp+var_4]\nmovq rax, xmm2\nmovsd xmm0, cs:y\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\ncvttsd2si eax, xmm0\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1, int a2)\n{\n return (unsigned int)(int)pow((double)(a1 - a2 + 1), 3.0);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1, int a2) {\n return (unsigned int)(int)pow((double)(a1 - a2 + 1), 3.0);\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n return (unsigned int)(int)pow((double)(a1 - a2 + 1), 3.0);\n}" + }, + { + "index": 646, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(int N, int K) {\n int No = 0;\n No = (N - K + 1);\n No = pow(No, 3);\n return No;\n}", + "test": "int main() {\n\n assert(func0(2, 1) == 8);\n\n assert(func0(5, 2) == 64);\n\n assert(func0(1, 1) == 1);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x8,%rsp\nsub %esi,%edi\nadd $0x1,%edi\npxor %xmm0,%xmm0\ncvtsi2sd %edi,%xmm0\nmovsd 0xefa(%rip),%xmm1\ncallq 1060 \ncvttsd2si %xmm0,%eax\nadd $0x8,%rsp\nretq\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\nsub edi, esi\nadd edi, 1\npxor xmm0, xmm0\ncvtsi2sd xmm0, edi; x\nmovsd xmm1, cs:y; y\ncall _pow\ncvttsd2si eax, xmm0\nadd rsp, 8\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n return (unsigned int)(int)pow((double)(a1 - a2 + 1), 3.0);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nsub rsp, 8\nsub edi, esi\nadd edi, 1\npxor xmm0, xmm0\ncvtsi2sd xmm0, edi; x\nmovsd xmm1, cs:y; y\ncall _pow\ncvttsd2si eax, xmm0\nadd rsp, 8\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1, int a2)\n{\n return (unsigned int)(int)pow((double)(a1 - a2 + 1), 3.0);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1, int a2) {\n return (unsigned int)(int)pow((double)(a1 - a2 + 1), 3.0);\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n return (unsigned int)(int)pow((double)(a1 - a2 + 1), 3.0);\n}" + }, + { + "index": 646, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(int N, int K) {\n int No = 0;\n No = (N - K + 1);\n No = pow(No, 3);\n return No;\n}", + "test": "int main() {\n\n assert(func0(2, 1) == 8);\n\n assert(func0(5, 2) == 64);\n\n assert(func0(1, 1) == 1);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nsub %esi,%edi\npxor %xmm0,%xmm0\nsub $0x8,%rsp\nmovsd 0xe92(%rip),%xmm1\nadd $0x1,%edi\ncvtsi2sd %edi,%xmm0\ncallq 1050 \nadd $0x8,%rsp\ncvttsd2si %xmm0,%eax\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nsub edi, esi\npxor xmm0, xmm0\nsub rsp, 8\nmovsd xmm1, cs:y; y\nadd edi, 1\ncvtsi2sd xmm0, edi; x\ncall _pow\nadd rsp, 8\ncvttsd2si eax, xmm0\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n return (unsigned int)(int)pow((double)(a1 - a2 + 1), 3.0);\n}", + "ida_strip_asm": "sub_1160:\nendbr64\nsub edi, esi\npxor xmm0, xmm0\nsub rsp, 8\nmovsd xmm1, cs:y; y\nadd edi, 1\ncvtsi2sd xmm0, edi; x\ncall _pow\nadd rsp, 8\ncvttsd2si eax, xmm0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1160(int a1, int a2)\n{\n return (unsigned int)(int)pow((double)(a1 - a2 + 1), 3.0);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1160(int a1, int a2) {\n return (unsigned int)(int)pow((double)(a1 - a2 + 1), 3.0);\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n return (unsigned int)(int)pow((double)(a1 - a2 + 1), 3.0);\n}" + }, + { + "index": 646, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(int N, int K) {\n int No = 0;\n No = (N - K + 1);\n No = pow(No, 3);\n return No;\n}", + "test": "int main() {\n\n assert(func0(2, 1) == 8);\n\n assert(func0(5, 2) == 64);\n\n assert(func0(1, 1) == 1);\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nsub %esi,%edi\npxor %xmm0,%xmm0\nsub $0x8,%rsp\nmovsd 0xe92(%rip),%xmm1\nadd $0x1,%edi\ncvtsi2sd %edi,%xmm0\ncallq 1050 \nadd $0x8,%rsp\ncvttsd2si %xmm0,%eax\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nsub edi, esi\npxor xmm0, xmm0\nsub rsp, 8\nmovsd xmm1, cs:y; y\nadd edi, 1\ncvtsi2sd xmm0, edi; x\ncall _pow\nadd rsp, 8\ncvttsd2si eax, xmm0\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n return (unsigned int)(int)pow((double)(a1 - a2 + 1), 3.0);\n}", + "ida_strip_asm": "sub_1160:\nendbr64\nsub edi, esi\npxor xmm0, xmm0\nsub rsp, 8\nmovsd xmm1, cs:y; y\nadd edi, 1\ncvtsi2sd xmm0, edi; x\ncall _pow\nadd rsp, 8\ncvttsd2si eax, xmm0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1160(int a1, int a2)\n{\n return (unsigned int)(int)pow((double)(a1 - a2 + 1), 3.0);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1160(int a1, int a2) {\n return (unsigned int)(int)pow((double)(a1 - a2 + 1), 3.0);\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n return (unsigned int)(int)pow((double)(a1 - a2 + 1), 3.0);\n}" + }, + { + "index": 647, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(const char* text, int* count) {\n int len = strlen(text);\n char** result = malloc(len * sizeof(char*));\n if (result == NULL) {\n perror(\"Failed to allocate memory\");\n exit(EXIT_FAILURE);\n }\n int current_word = 0;\n int start = 0;\n for (int i = 1; i <= len; i++) {\n if (isupper(text[i]) || text[i] == '\\0') {\n int word_length = i - start;\n result[current_word] = malloc(word_length + 1);\n if (result[current_word] == NULL) {\n perror(\"Failed to allocate memory\");\n exit(EXIT_FAILURE);\n }\n memcpy(result[current_word], text + start, word_length);\n result[current_word][word_length] = '\\0';\n start = i;\n current_word++;\n }\n }\n *count = current_word;\n return result;\n}", + "test": "int main() {\n\n int count = 0;\n\n char** result;\n\n\n\n result = func0(\"PythonProgramLanguage\", &count);\n\n assert(count == 3);\n\n assert(strcmp(result[0], \"Python\") == 0);\n\n assert(strcmp(result[1], \"Program\") == 0);\n\n assert(strcmp(result[2], \"Language\") == 0);\n\n for (int i = 0; i < count; i++) free(result[i]);\n\n free(result);\n\n\n\n result = func0(\"PythonProgram\", &count);\n\n assert(count == 2);\n\n assert(strcmp(result[0], \"Python\") == 0);\n\n assert(strcmp(result[1], \"Program\") == 0);\n\n for (int i = 0; i < count; i++) free(result[i]);\n\n free(result);\n\n\n\n result = func0(\"ProgrammingLanguage\", &count);\n\n assert(count == 2);\n\n assert(strcmp(result[0], \"Programming\") == 0);\n\n assert(strcmp(result[1], \"Language\") == 0);\n\n for (int i = 0; i < count; i++) free(result[i]);\n\n free(result);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x38,%rsp\nmov %rdi,-0x38(%rbp)\nmov %rsi,-0x40(%rbp)\nmov -0x38(%rbp),%rax\nmov %rax,%rdi\ncallq 10f0 \nmov %eax,-0x20(%rbp)\nmov -0x20(%rbp),%eax\ncltq\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 1140 \nmov %rax,-0x18(%rbp)\ncmpq $0x0,-0x18(%rbp)\njne 12bf \nlea 0xd58(%rip),%rdi\ncallq 1150 \nmov $0x1,%edi\ncallq 1160 \nmovl $0x0,-0x2c(%rbp)\nmovl $0x0,-0x28(%rbp)\nmovl $0x1,-0x24(%rbp)\njmpq 13eb \ncallq 1170 <__ctype_b_loc@plt>\nmov (%rax),%rax\nmov -0x24(%rbp),%edx\nmovslq %edx,%rcx\nmov -0x38(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rdx),%edx\nmovsbq %dl,%rdx\nadd %rdx,%rdx\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x100,%eax\ntest %eax,%eax\njne 1322 \nmov -0x24(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 13e7 \nmov -0x24(%rbp),%eax\nsub -0x28(%rbp),%eax\nmov %eax,-0x1c(%rbp)\nmov -0x1c(%rbp),%eax\nadd $0x1,%eax\ncltq\nmov -0x2c(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x18(%rbp),%rdx\nlea (%rcx,%rdx,1),%rbx\nmov %rax,%rdi\ncallq 1140 \nmov %rax,(%rbx)\nmov -0x2c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\ntest %rax,%rax\njne 1386 \nlea 0xc91(%rip),%rdi\ncallq 1150 \nmov $0x1,%edi\ncallq 1160 \nmov -0x1c(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%eax\nmovslq %eax,%rcx\nmov -0x38(%rbp),%rax\nadd %rax,%rcx\nmov -0x2c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rsi\nmov -0x18(%rbp),%rax\nadd %rsi,%rax\nmov (%rax),%rax\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 1130 \nmov -0x2c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rdx\nmov -0x1c(%rbp),%eax\ncltq\nadd %rdx,%rax\nmovb $0x0,(%rax)\nmov -0x24(%rbp),%eax\nmov %eax,-0x28(%rbp)\naddl $0x1,-0x2c(%rbp)\naddl $0x1,-0x24(%rbp)\nmov -0x24(%rbp),%eax\ncmp -0x20(%rbp),%eax\njle 12d9 \nmov -0x40(%rbp),%rax\nmov -0x2c(%rbp),%edx\nmov %edx,(%rax)\nmov -0x18(%rbp),%rax\nadd $0x38,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+s], rdi\nmov [rbp+var_40], rsi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_20], eax\nmov eax, [rbp+var_20]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\ncmp [rbp+var_18], 0\njnz short loc_12C2\nlea rax, s; \"Failed to allocate memory\"\nmov rdi, rax; s\ncall _perror\nmov edi, 1; status\ncall _exit\nloc_12C2:\nmov [rbp+var_2C], 0\nmov [rbp+var_28], 0\nmov [rbp+var_24], 1\njmp loc_13F1\nloc_12DC:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_24]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 100h\ntest eax, eax\njnz short loc_1325\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_13ED\nloc_1325:\nmov eax, [rbp+var_24]\nsub eax, [rbp+var_28]\nmov [rbp+var_1C], eax\nmov eax, [rbp+var_1C]\nadd eax, 1\ncdqe\nmov edx, [rbp+var_2C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nlea rbx, [rcx+rdx]\nmov rdi, rax; size\ncall _malloc\nmov [rbx], rax\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\ntest rax, rax\njnz short loc_138C\nlea rax, s; \"Failed to allocate memory\"\nmov rdi, rax; s\ncall _perror\nmov edi, 1; status\ncall _exit\nloc_138C:\nmov eax, [rbp+var_1C]\nmovsxd rdx, eax; n\nmov eax, [rbp+var_28]\nmovsxd rcx, eax\nmov rax, [rbp+s]\nadd rcx, rax\nmov eax, [rbp+var_2C]\ncdqe\nlea rsi, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rsi\nmov rax, [rax]\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _memcpy\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_1C]\ncdqe\nadd rax, rdx\nmov byte ptr [rax], 0\nmov eax, [rbp+var_24]\nmov [rbp+var_28], eax\nadd [rbp+var_2C], 1\nloc_13ED:\nadd [rbp+var_24], 1\nloc_13F1:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_20]\njle loc_12DC\nmov rax, [rbp+var_40]\nmov edx, [rbp+var_2C]\nmov [rax], edx\nmov rax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(const char *a1, _DWORD *a2)\n{\n int v3; // [rsp+14h] [rbp-2Ch]\n int v4; // [rsp+18h] [rbp-28h]\n int i; // [rsp+1Ch] [rbp-24h]\n int v6; // [rsp+20h] [rbp-20h]\n int v7; // [rsp+24h] [rbp-1Ch]\n _QWORD *v8; // [rsp+28h] [rbp-18h]\n\n v6 = strlen(a1);\n v8 = malloc(8LL * v6);\n if ( !v8 )\n {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v3 = 0;\n v4 = 0;\n for ( i = 1; i <= v6; ++i )\n {\n if ( ((*__ctype_b_loc())[a1[i]] & 0x100) != 0 || !a1[i] )\n {\n v7 = i - v4;\n v8[v3] = malloc(i - v4 + 1);\n if ( !v8[v3] )\n {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n memcpy((void *)v8[v3], &a1[v4], v7);\n *(_BYTE *)(v8[v3] + v7) = 0;\n v4 = i;\n ++v3;\n }\n }\n *a2 = v3;\n return v8;\n}", + "ida_strip_asm": "sub_1269:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+s], rdi\nmov [rbp+var_40], rsi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_20], eax\nmov eax, [rbp+var_20]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\ncmp [rbp+var_18], 0\njnz short loc_12C2\nlea rax, s; \"Failed to allocate memory\"\nmov rdi, rax; s\ncall _perror\nmov edi, 1; status\ncall _exit\nloc_12C2:\nmov [rbp+var_2C], 0\nmov [rbp+var_28], 0\nmov [rbp+var_24], 1\njmp loc_13F1\nloc_12DC:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_24]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 100h\ntest eax, eax\njnz short loc_1325\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_13ED\nloc_1325:\nmov eax, [rbp+var_24]\nsub eax, [rbp+var_28]\nmov [rbp+var_1C], eax\nmov eax, [rbp+var_1C]\nadd eax, 1\ncdqe\nmov edx, [rbp+var_2C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nlea rbx, [rcx+rdx]\nmov rdi, rax; size\ncall _malloc\nmov [rbx], rax\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\ntest rax, rax\njnz short loc_138C\nlea rax, s; \"Failed to allocate memory\"\nmov rdi, rax; s\ncall _perror\nmov edi, 1; status\ncall _exit\nloc_138C:\nmov eax, [rbp+var_1C]\nmovsxd rdx, eax; n\nmov eax, [rbp+var_28]\nmovsxd rcx, eax\nmov rax, [rbp+s]\nadd rcx, rax\nmov eax, [rbp+var_2C]\ncdqe\nlea rsi, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rsi\nmov rax, [rax]\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _memcpy\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_1C]\ncdqe\nadd rax, rdx\nmov byte ptr [rax], 0\nmov eax, [rbp+var_24]\nmov [rbp+var_28], eax\nadd [rbp+var_2C], 1\nloc_13ED:\nadd [rbp+var_24], 1\nloc_13F1:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_20]\njle loc_12DC\nmov rax, [rbp+var_40]\nmov edx, [rbp+var_2C]\nmov [rax], edx\nmov rax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1269(const char *a1, _DWORD *a2)\n{\n int v3; // [rsp+14h] [rbp-2Ch]\n int v4; // [rsp+18h] [rbp-28h]\n int i; // [rsp+1Ch] [rbp-24h]\n int v6; // [rsp+20h] [rbp-20h]\n int v7; // [rsp+24h] [rbp-1Ch]\n _QWORD *v8; // [rsp+28h] [rbp-18h]\n\n v6 = strlen(a1);\n v8 = malloc(8LL * v6);\n if ( !v8 )\n {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v3 = 0;\n v4 = 0;\n for ( i = 1; i <= v6; ++i )\n {\n if ( ((*__ctype_b_loc())[a1[i]] & 0x100) != 0 || !a1[i] )\n {\n v7 = i - v4;\n v8[v3] = malloc(i - v4 + 1);\n if ( !v8[v3] )\n {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n memcpy((void *)v8[v3], &a1[v4], v7);\n *(_BYTE *)(v8[v3] + v7) = 0;\n v4 = i;\n ++v3;\n }\n }\n *a2 = v3;\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1269(const char *a1, uint32_t *a2) {\n int v3;\n int v4;\n int i;\n int v6;\n int v7;\n uint64_t *v8;\n v6 = strlen(a1);\n v8 = malloc(8LL * v6);\n if (!v8) {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v3 = 0;\n v4 = 0;\n for (i = 1; i <= v6; ++i) {\n if (((*__ctype_b_loc())[a1[i]] & 256) != 0 || !a1[i]) {\n v7 = i - v4;\n v8[v3] = malloc(i - v4 + 1);\n if (!v8[v3]) {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n memcpy((void *)v8[v3], &a1[v4], v7);\n *(uint8_t *)(v8[v3] + v7) = 0;\n v4 = i;\n ++v3;\n }\n }\n *a2 = v3;\n return v8;\n}", + "ida_pseudo_norm": "uint64_t *func0(const char *a1, uint32_t *a2) {\n int v3;\n int v4;\n int i;\n int v6;\n int v7;\n uint64_t *v8;\n v6 = strlen(a1);\n v8 = malloc(8LL * v6);\n if (!v8) {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v3 = 0;\n v4 = 0;\n for (i = 1; i <= v6; ++i) {\n if (((*__ctype_b_loc())[a1[i]] & 256) != 0 || !a1[i]) {\n v7 = i - v4;\n v8[v3] = malloc(i - v4 + 1);\n if (!v8[v3]) {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n memcpy((void *)v8[v3], &a1[v4], v7);\n *(uint8_t *)(v8[v3] + v7) = 0;\n v4 = i;\n ++v3;\n }\n }\n *a2 = v3;\n return v8;\n}" + }, + { + "index": 647, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(const char* text, int* count) {\n int len = strlen(text);\n char** result = malloc(len * sizeof(char*));\n if (result == NULL) {\n perror(\"Failed to allocate memory\");\n exit(EXIT_FAILURE);\n }\n int current_word = 0;\n int start = 0;\n for (int i = 1; i <= len; i++) {\n if (isupper(text[i]) || text[i] == '\\0') {\n int word_length = i - start;\n result[current_word] = malloc(word_length + 1);\n if (result[current_word] == NULL) {\n perror(\"Failed to allocate memory\");\n exit(EXIT_FAILURE);\n }\n memcpy(result[current_word], text + start, word_length);\n result[current_word][word_length] = '\\0';\n start = i;\n current_word++;\n }\n }\n *count = current_word;\n return result;\n}", + "test": "int main() {\n\n int count = 0;\n\n char** result;\n\n\n\n result = func0(\"PythonProgramLanguage\", &count);\n\n assert(count == 3);\n\n assert(strcmp(result[0], \"Python\") == 0);\n\n assert(strcmp(result[1], \"Program\") == 0);\n\n assert(strcmp(result[2], \"Language\") == 0);\n\n for (int i = 0; i < count; i++) free(result[i]);\n\n free(result);\n\n\n\n result = func0(\"PythonProgram\", &count);\n\n assert(count == 2);\n\n assert(strcmp(result[0], \"Python\") == 0);\n\n assert(strcmp(result[1], \"Program\") == 0);\n\n for (int i = 0; i < count; i++) free(result[i]);\n\n free(result);\n\n\n\n result = func0(\"ProgrammingLanguage\", &count);\n\n assert(count == 2);\n\n assert(strcmp(result[0], \"Programming\") == 0);\n\n assert(strcmp(result[1], \"Language\") == 0);\n\n for (int i = 0; i < count; i++) free(result[i]);\n\n free(result);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x28,%rsp\nmov %rdi,%r14\nmov %rsi,0x18(%rsp)\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nlea -0x1(%rcx),%rbx\nmov %ebx,0xc(%rsp)\nmovslq %ebx,%rdi\nshl $0x3,%rdi\ncallq 1100 \nmov %rax,0x10(%rsp)\ntest %rax,%rax\nje 129d \nmov $0x0,%r13d\ntest %ebx,%ebx\njle 1343 \ncallq 1130 <__ctype_b_loc@plt>\nmov %rax,%r15\nmov $0x1,%ebx\nmovl $0x0,0x8(%rsp)\nmov $0x0,%r13d\njmp 1310 \nlea 0xd60(%rip),%rdi\ncallq 1110 \nmov $0x1,%edi\ncallq 1120 \nmov 0x4(%rsp),%r12d\nsub 0x8(%rsp),%r12d\nlea 0x1(%r12),%edi\nmovslq %edi,%rdi\ncallq 1100 \nmov %rax,%rbp\nmovslq %r13d,%rax\nmov 0x10(%rsp),%rcx\nmov %rbp,(%rcx,%rax,8)\ntest %rbp,%rbp\nje 132d \nmovslq %r12d,%r12\nmovslq 0x8(%rsp),%rsi\nadd %r14,%rsi\nmov %r12,%rdx\nmov %rbp,%rdi\ncallq 10f0 \nmovb $0x0,0x0(%rbp,%r12,1)\nadd $0x1,%r13d\nmov 0x4(%rsp),%eax\nmov %eax,0x8(%rsp)\nadd $0x1,%rbx\ncmp %ebx,0xc(%rsp)\njl 1343 \nmov %ebx,0x4(%rsp)\nmovzbl (%r14,%rbx,1),%eax\nmovsbq %al,%rcx\nmov (%r15),%rdx\ntestb $0x1,0x1(%rdx,%rcx,2)\njne 12b3 \ntest %al,%al\njne 1306 \njmp 12b3 \nlea 0xcd0(%rip),%rdi\ncallq 1110 \nmov $0x1,%edi\ncallq 1120 \nmov 0x18(%rsp),%rax\nmov %r13d,(%rax)\nmov 0x10(%rsp),%rax\nadd $0x28,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov r14, rdi\nmov [rsp+58h+var_40], rsi\ncall _strlen\nmov rbx, rax\nmov [rsp+58h+var_4C], eax\nmovsxd rdi, eax\nshl rdi, 3; size\ncall _malloc\nmov [rsp+58h+var_48], rax\ntest rax, rax\njz short loc_12D0\nmov r13d, 0\ntest ebx, ebx\njle loc_1378\ncall ___ctype_b_loc\nmov r15, rax\nmov ebx, 1\nmov [rsp+58h+var_50], 0\nmov r13d, 0\njmp short loc_1349\nloc_12D0:\nlea rdi, s; \"Failed to allocate memory\"\ncall _perror\nmov edi, 1; status\ncall _exit\nloc_12E6:\nmov r12d, ebx\nmov eax, [rsp+58h+var_50]\nsub r12d, eax\nlea eax, [r12+1]\ncdqe\nmov [rsp+58h+var_58], rax\nmov rdi, rax; size\ncall _malloc\nmov rbp, rax\nmovsxd rax, r13d\nmov rdi, [rsp+58h+var_48]\nmov [rdi+rax*8], rbp\ntest rbp, rbp\njz short loc_1362\nmovsxd r12, r12d\nmovsxd rsi, [rsp+58h+var_50]\nadd rsi, r14\nmov rcx, [rsp+58h+var_58]\nmov rdx, r12\nmov rdi, rbp\ncall ___memcpy_chk\nmov byte ptr [rbp+r12+0], 0\nadd r13d, 1\nmov [rsp+58h+var_50], ebx\nloc_133F:\nadd rbx, 1\ncmp [rsp+58h+var_4C], ebx\njl short loc_1378\nloc_1349:\nmovzx eax, byte ptr [r14+rbx]\nmovsx rcx, al\nmov rdx, [r15]\ntest byte ptr [rdx+rcx*2+1], 1\njnz short loc_12E6\ntest al, al\njnz short loc_133F\njmp short loc_12E6\nloc_1362:\nlea rdi, s; \"Failed to allocate memory\"\ncall _perror\nmov edi, 1; status\ncall _exit\nloc_1378:\nmov rax, [rsp+58h+var_40]\nmov [rax], r13d\nmov rax, [rsp+58h+var_48]\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(const char *a1, _DWORD *a2)\n{\n int v2; // ebx\n int v3; // r13d\n const unsigned __int16 **v4; // r15\n __int64 v5; // rbx\n int v6; // r12d\n _BYTE *v7; // rbp\n char v8; // al\n int v10; // [rsp+8h] [rbp-50h]\n int v11; // [rsp+Ch] [rbp-4Ch]\n _QWORD *v12; // [rsp+10h] [rbp-48h]\n\n v2 = strlen(a1);\n v11 = v2;\n v12 = malloc(8LL * v2);\n if ( !v12 )\n {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v3 = 0;\n if ( v2 > 0 )\n {\n v4 = __ctype_b_loc();\n v5 = 1LL;\n v10 = 0;\n v3 = 0;\n do\n {\n v8 = a1[v5];\n if ( ((*v4)[v8] & 0x100) != 0 || !v8 )\n {\n v6 = v5 - v10;\n v7 = malloc((int)v5 - v10 + 1);\n v12[v3] = v7;\n if ( !v7 )\n {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n __memcpy_chk(v7, &a1[v10], v6, (int)v5 - v10 + 1);\n v7[v6] = 0;\n ++v3;\n v10 = v5;\n }\n ++v5;\n }\n while ( v11 >= (int)v5 );\n }\n *a2 = v3;\n return v12;\n}", + "ida_strip_asm": "sub_1269:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov r14, rdi\nmov [rsp+58h+var_40], rsi\ncall _strlen\nmov rbx, rax\nmov [rsp+58h+var_4C], eax\nmovsxd rdi, eax\nshl rdi, 3; size\ncall _malloc\nmov [rsp+58h+var_48], rax\ntest rax, rax\njz short loc_12D0\nmov r13d, 0\ntest ebx, ebx\njle loc_1378\ncall ___ctype_b_loc\nmov r15, rax\nmov ebx, 1\nmov [rsp+58h+var_50], 0\nmov r13d, 0\njmp short loc_1349\nloc_12D0:\nlea rdi, s; \"Failed to allocate memory\"\ncall _perror\nmov edi, 1; status\ncall _exit\nloc_12E6:\nmov r12d, ebx\nmov eax, [rsp+58h+var_50]\nsub r12d, eax\nlea eax, [r12+1]\ncdqe\nmov [rsp+58h+var_58], rax\nmov rdi, rax; size\ncall _malloc\nmov rbp, rax\nmovsxd rax, r13d\nmov rdi, [rsp+58h+var_48]\nmov [rdi+rax*8], rbp\ntest rbp, rbp\njz short loc_1362\nmovsxd r12, r12d\nmovsxd rsi, [rsp+58h+var_50]\nadd rsi, r14\nmov rcx, [rsp+58h+var_58]\nmov rdx, r12\nmov rdi, rbp\ncall ___memcpy_chk\nmov byte ptr [rbp+r12+0], 0\nadd r13d, 1\nmov [rsp+58h+var_50], ebx\nloc_133F:\nadd rbx, 1\ncmp [rsp+58h+var_4C], ebx\njl short loc_1378\nloc_1349:\nmovzx eax, byte ptr [r14+rbx]\nmovsx rcx, al\nmov rdx, [r15]\ntest byte ptr [rdx+rcx*2+1], 1\njnz short loc_12E6\ntest al, al\njnz short loc_133F\njmp short loc_12E6\nloc_1362:\nlea rdi, s; \"Failed to allocate memory\"\ncall _perror\nmov edi, 1; status\ncall _exit\nloc_1378:\nmov rax, [rsp+58h+var_40]\nmov [rax], r13d\nmov rax, [rsp+58h+var_48]\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1269(const char *a1, _DWORD *a2)\n{\n int v2; // ebx\n int v3; // r13d\n const unsigned __int16 **v4; // r15\n __int64 v5; // rbx\n int v6; // r12d\n _BYTE *v7; // rbp\n char v8; // al\n int v10; // [rsp+8h] [rbp-50h]\n int v11; // [rsp+Ch] [rbp-4Ch]\n _QWORD *v12; // [rsp+10h] [rbp-48h]\n\n v2 = strlen(a1);\n v11 = v2;\n v12 = malloc(8LL * v2);\n if ( !v12 )\n {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v3 = 0;\n if ( v2 > 0 )\n {\n v4 = __ctype_b_loc();\n v5 = 1LL;\n v10 = 0;\n v3 = 0;\n do\n {\n v8 = a1[v5];\n if ( ((*v4)[v8] & 0x100) != 0 || !v8 )\n {\n v6 = v5 - v10;\n v7 = malloc((int)v5 - v10 + 1);\n v12[v3] = v7;\n if ( !v7 )\n {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n __memcpy_chk(v7, &a1[v10], v6, (int)v5 - v10 + 1);\n v7[v6] = 0;\n ++v3;\n v10 = v5;\n }\n ++v5;\n }\n while ( v11 >= (int)v5 );\n }\n *a2 = v3;\n return v12;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1269(const char *a1, uint32_t *a2) {\n int v2;\n int v3;\n const unsigned short **v4;\n long long v5;\n int v6;\n uint8_t *v7;\n char v8;\n int v10;\n int v11;\n uint64_t *v12;\n v2 = strlen(a1);\n v11 = v2;\n v12 = malloc(8LL * v2);\n if (!v12) {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v3 = 0;\n if (v2 > 0) {\n v4 = __ctype_b_loc();\n v5 = 1LL;\n v10 = 0;\n v3 = 0;\n do {\n v8 = a1[v5];\n if (((*v4)[v8] & 256) != 0 || !v8) {\n v6 = v5 - v10;\n v7 = malloc((int)v5 - v10 + 1);\n v12[v3] = v7;\n if (!v7) {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n __memcpy_chk(v7, &a1[v10], v6, (int)v5 - v10 + 1);\n v7[v6] = 0;\n ++v3;\n v10 = v5;\n }\n ++v5;\n } while (v11 >= (int)v5);\n }\n *a2 = v3;\n return v12;\n}", + "ida_pseudo_norm": "uint64_t *func0(const char *a1, uint32_t *a2) {\n int v2;\n int v3;\n const unsigned short **v4;\n long long v5;\n int v6;\n uint8_t *v7;\n char v8;\n int v10;\n int v11;\n uint64_t *v12;\n v2 = strlen(a1);\n v11 = v2;\n v12 = malloc(8LL * v2);\n if (!v12) {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v3 = 0;\n if (v2 > 0) {\n v4 = __ctype_b_loc();\n v5 = 1LL;\n v10 = 0;\n v3 = 0;\n do {\n v8 = a1[v5];\n if (((*v4)[v8] & 256) != 0 || !v8) {\n v6 = v5 - v10;\n v7 = malloc((int)v5 - v10 + 1);\n v12[v3] = v7;\n if (!v7) {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n __memcpy_chk(v7, &a1[v10], v6, (int)v5 - v10 + 1);\n v7[v6] = 0;\n ++v3;\n v10 = v5;\n }\n ++v5;\n } while (v11 >= (int)v5);\n }\n *a2 = v3;\n return v12;\n}" + }, + { + "index": 647, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(const char* text, int* count) {\n int len = strlen(text);\n char** result = malloc(len * sizeof(char*));\n if (result == NULL) {\n perror(\"Failed to allocate memory\");\n exit(EXIT_FAILURE);\n }\n int current_word = 0;\n int start = 0;\n for (int i = 1; i <= len; i++) {\n if (isupper(text[i]) || text[i] == '\\0') {\n int word_length = i - start;\n result[current_word] = malloc(word_length + 1);\n if (result[current_word] == NULL) {\n perror(\"Failed to allocate memory\");\n exit(EXIT_FAILURE);\n }\n memcpy(result[current_word], text + start, word_length);\n result[current_word][word_length] = '\\0';\n start = i;\n current_word++;\n }\n }\n *count = current_word;\n return result;\n}", + "test": "int main() {\n\n int count = 0;\n\n char** result;\n\n\n\n result = func0(\"PythonProgramLanguage\", &count);\n\n assert(count == 3);\n\n assert(strcmp(result[0], \"Python\") == 0);\n\n assert(strcmp(result[1], \"Program\") == 0);\n\n assert(strcmp(result[2], \"Language\") == 0);\n\n for (int i = 0; i < count; i++) free(result[i]);\n\n free(result);\n\n\n\n result = func0(\"PythonProgram\", &count);\n\n assert(count == 2);\n\n assert(strcmp(result[0], \"Python\") == 0);\n\n assert(strcmp(result[1], \"Program\") == 0);\n\n for (int i = 0; i < count; i++) free(result[i]);\n\n free(result);\n\n\n\n result = func0(\"ProgrammingLanguage\", &count);\n\n assert(count == 2);\n\n assert(strcmp(result[0], \"Programming\") == 0);\n\n assert(strcmp(result[1], \"Language\") == 0);\n\n for (int i = 0; i < count; i++) free(result[i]);\n\n free(result);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\nmov %rdi,%r12\npush %rbp\npush %rbx\nsub $0x28,%rsp\nmov %rsi,0x18(%rsp)\ncallq 10e0 \nmovslq %eax,%rdi\nmov %eax,0x4(%rsp)\nmov %rax,%rbx\nshl $0x3,%rdi\ncallq 1120 \nmov %rax,0x10(%rsp)\ntest %rax,%rax\nje 1670 \nxor %ebp,%ebp\ntest %ebx,%ebx\njle 1655 \ncallq 1150 <__ctype_b_loc@plt>\nmov $0x1,%r13d\nxor %r15d,%r15d\nxor %ebp,%ebp\nmov (%rax),%rax\nmov %rax,0x8(%rsp)\nxchg %ax,%ax\nmovsbq (%r12,%r13,1),%rdx\nmov 0x8(%rsp),%rcx\nmov %r13d,%ebx\ntestb $0x1,0x1(%rcx,%rdx,2)\njne 1608 \ntest %dl,%dl\njne 164a \nmov %ebx,%r14d\nsub %r15d,%r14d\nlea 0x1(%r14),%edi\nmovslq %edi,%rdi\ncallq 1120 \nmov 0x10(%rsp),%rcx\nmov %rax,%rdi\nmovslq %ebp,%rax\nmov %rdi,(%rcx,%rax,8)\ntest %rdi,%rdi\nje 1670 \nmovslq %r14d,%r14\nmovslq %r15d,%rsi\nadd $0x1,%ebp\nmov %ebx,%r15d\nadd %r12,%rsi\nmov %r14,%rdx\ncallq 1110 \nmovb $0x0,(%rax,%r14,1)\nadd $0x1,%r13\ncmp %r13d,0x4(%rsp)\njge 15f0 \nmov 0x18(%rsp),%rax\nmov %ebp,(%rax)\nmov 0x10(%rsp),%rax\nadd $0x28,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nlea 0x98d(%rip),%rdi\ncallq 1130 \nmov $0x1,%edi\ncallq 1140 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 28h\nmov [rsp+58h+var_40], rsi\ncall _strlen\nmovsxd rdi, eax\nmov [rsp+58h+var_4C], eax\nmov rbx, rax\nshl rdi, 3; size\ncall _malloc\nmov [rsp+58h+var_48], rax\ntest rax, rax\njz func0_cold\ntest ebx, ebx\njle loc_1660\ncall ___ctype_b_loc\nmov r13d, 1\nxor r15d, r15d\nxor ebx, ebx\nmov r14, [rax]\nnop dword ptr [rax+rax+00h]\nloc_15D0:\nmovsx rcx, byte ptr [rbp+r13+0]\ntest byte ptr [r14+rcx*2+1], 1\njnz short loc_15E2\ntest cl, cl\njnz short loc_1636\nloc_15E2:\nmov r12d, r13d\nsub r12d, r15d\nlea ecx, [r12+1]\nmovsxd rcx, ecx\nmov rdi, rcx; size\nmov [rsp+58h+var_58], rcx\ncall _malloc\nmov rdx, [rsp+58h+var_48]\nmov rdi, rax\nmovsxd rax, ebx\nmov [rdx+rax*8], rdi\ntest rdi, rdi\njz func0_cold\nmovsxd rdx, r15d\nmovsxd r12, r12d\nmov rcx, [rsp+58h+var_58]\nadd ebx, 1\nlea rsi, [rbp+rdx+0]\nmov rdx, r12\nmov r15d, r13d\ncall ___memcpy_chk\nmov byte ptr [rax+r12], 0\nloc_1636:\nadd r13, 1\ncmp [rsp+58h+var_4C], r13d\njge short loc_15D0\nloc_1641:\nmov rax, [rsp+58h+var_40]\nmov [rax], ebx\nmov rax, [rsp+58h+var_48]\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1660:\nxor ebx, ebx\njmp short loc_1641", + "ida_pseudo": "_QWORD *__fastcall func0(const char *a1, _DWORD *a2)\n{\n __int64 v3; // r13\n int v4; // r15d\n int v5; // ebx\n const unsigned __int16 *v6; // r14\n __int64 v7; // rcx\n int v8; // r12d\n void *v9; // rdi\n const char *v10; // rsi\n int v12; // [rsp+Ch] [rbp-4Ch]\n _QWORD *v13; // [rsp+10h] [rbp-48h]\n\n v12 = strlen(a1);\n v13 = malloc(8LL * v12);\n if ( !v13 )\nLABEL_11:\n func0_cold();\n if ( v12 <= 0 )\n {\n v5 = 0;\n }\n else\n {\n v3 = 1LL;\n v4 = 0;\n v5 = 0;\n v6 = *__ctype_b_loc();\n do\n {\n v7 = a1[v3];\n if ( (v6[v7] & 0x100) != 0 || !(_BYTE)v7 )\n {\n v8 = v3 - v4;\n v9 = malloc((int)v3 - v4 + 1);\n v13[v5] = v9;\n if ( !v9 )\n goto LABEL_11;\n ++v5;\n v10 = &a1[v4];\n v4 = v3;\n *(_BYTE *)(__memcpy_chk(v9, v10, v8, v8 + 1) + v8) = 0;\n }\n ++v3;\n }\n while ( v12 >= (int)v3 );\n }\n *a2 = v5;\n return v13;\n}", + "ida_strip_asm": "sub_1570:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 28h\nmov [rsp+58h+var_40], rsi\ncall _strlen\nmovsxd rdi, eax\nmov [rsp+58h+var_4C], eax\nmov rbx, rax\nshl rdi, 3; size\ncall _malloc\nmov [rsp+58h+var_48], rax\ntest rax, rax\njz loc_1180\ntest ebx, ebx\njle loc_1660\ncall ___ctype_b_loc\nmov r13d, 1\nxor r15d, r15d\nxor ebx, ebx\nmov r14, [rax]\nnop dword ptr [rax+rax+00h]\nloc_15D0:\nmovsx rcx, byte ptr [rbp+r13+0]\ntest byte ptr [r14+rcx*2+1], 1\njnz short loc_15E2\ntest cl, cl\njnz short loc_1636\nloc_15E2:\nmov r12d, r13d\nsub r12d, r15d\nlea ecx, [r12+1]\nmovsxd rcx, ecx\nmov rdi, rcx; size\nmov [rsp+58h+var_58], rcx\ncall _malloc\nmov rdx, [rsp+58h+var_48]\nmov rdi, rax\nmovsxd rax, ebx\nmov [rdx+rax*8], rdi\ntest rdi, rdi\njz loc_1180\nmovsxd rdx, r15d\nmovsxd r12, r12d\nmov rcx, [rsp+58h+var_58]\nadd ebx, 1\nlea rsi, [rbp+rdx+0]\nmov rdx, r12\nmov r15d, r13d\ncall ___memcpy_chk\nmov byte ptr [rax+r12], 0\nloc_1636:\nadd r13, 1\ncmp [rsp+58h+var_4C], r13d\njge short loc_15D0\nloc_1641:\nmov rax, [rsp+58h+var_40]\nmov [rax], ebx\nmov rax, [rsp+58h+var_48]\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1660:\nxor ebx, ebx\njmp short loc_1641", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1570(const char *a1, _DWORD *a2)\n{\n __int64 v3; // r13\n int v4; // r15d\n int v5; // ebx\n const unsigned __int16 *v6; // r14\n __int64 v7; // rcx\n void *v8; // rdi\n int v9; // r12d\n const char *v10; // rsi\n size_t v12; // [rsp+0h] [rbp-58h]\n int v13; // [rsp+Ch] [rbp-4Ch]\n _QWORD *v14; // [rsp+10h] [rbp-48h]\n\n v13 = strlen(a1);\n v14 = malloc(8LL * v13);\n if ( !v14 )\n {\nLABEL_11:\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n if ( v13 <= 0 )\n {\n v5 = 0;\n }\n else\n {\n v3 = 1LL;\n v4 = 0;\n v5 = 0;\n v6 = *__ctype_b_loc();\n do\n {\n v7 = a1[v3];\n if ( (v6[v7] & 0x100) != 0 || !(_BYTE)v7 )\n {\n v12 = (int)v3 - v4 + 1;\n v8 = malloc(v12);\n v14[v5] = v8;\n if ( !v8 )\n goto LABEL_11;\n v9 = v3 - v4;\n ++v5;\n v10 = &a1[v4];\n v4 = v3;\n *(_BYTE *)(__memcpy_chk(v8, v10, v9, v12) + v9) = 0;\n }\n ++v3;\n }\n while ( v13 >= (int)v3 );\n }\n *a2 = v5;\n return v14;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1570(const char *a1, uint32_t *a2) {\n long long v3;\n int v4;\n int v5;\n const unsigned short *v6;\n long long v7;\n void *v8;\n int v9;\n const char *v10;\n unsigned int v12;\n int v13;\n uint64_t *v14;\n v13 = strlen(a1);\n v14 = malloc(8LL * v13);\n if (!v14) {\n LABEL_11:\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n if (v13 <= 0) {\n v5 = 0;\n } else {\n v3 = 1LL;\n v4 = 0;\n v5 = 0;\n v6 = *__ctype_b_loc();\n do {\n v7 = a1[v3];\n if ((v6[v7] & 256) != 0 || !(uint8_t)v7) {\n v12 = (int)v3 - v4 + 1;\n v8 = malloc(v12);\n v14[v5] = v8;\n if (!v8) goto LABEL_11;\n v9 = v3 - v4;\n ++v5;\n v10 = &a1[v4];\n v4 = v3;\n *(uint8_t *)(__memcpy_chk(v8, v10, v9, v12) + v9) = 0;\n }\n ++v3;\n } while (v13 >= (int)v3);\n }\n *a2 = v5;\n return v14;\n}", + "ida_pseudo_norm": "uint64_t *func0(const char *a1, uint32_t *a2) {\n long long v3;\n int v4;\n int v5;\n const unsigned short *v6;\n long long v7;\n int v8;\n void *v9;\n const char *v10;\n int v12;\n uint64_t *v13;\n v12 = strlen(a1);\n v13 = malloc(8LL * v12);\n if (!v13)\n LABEL_11:\n func0_cold();\n if (v12 <= 0) {\n v5 = 0;\n } else {\n v3 = 1LL;\n v4 = 0;\n v5 = 0;\n v6 = *__ctype_b_loc();\n do {\n v7 = a1[v3];\n if ((v6[v7] & 256) != 0 || !(uint8_t)v7) {\n v8 = v3 - v4;\n v9 = malloc((int)v3 - v4 + 1);\n v13[v5] = v9;\n if (!v9) goto LABEL_11;\n ++v5;\n v10 = &a1[v4];\n v4 = v3;\n *(uint8_t *)(__memcpy_chk(v9, v10, v8, v8 + 1) + v8) = 0;\n }\n ++v3;\n } while (v12 >= (int)v3);\n }\n *a2 = v5;\n return v13;\n}" + }, + { + "index": 647, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(const char* text, int* count) {\n int len = strlen(text);\n char** result = malloc(len * sizeof(char*));\n if (result == NULL) {\n perror(\"Failed to allocate memory\");\n exit(EXIT_FAILURE);\n }\n int current_word = 0;\n int start = 0;\n for (int i = 1; i <= len; i++) {\n if (isupper(text[i]) || text[i] == '\\0') {\n int word_length = i - start;\n result[current_word] = malloc(word_length + 1);\n if (result[current_word] == NULL) {\n perror(\"Failed to allocate memory\");\n exit(EXIT_FAILURE);\n }\n memcpy(result[current_word], text + start, word_length);\n result[current_word][word_length] = '\\0';\n start = i;\n current_word++;\n }\n }\n *count = current_word;\n return result;\n}", + "test": "int main() {\n\n int count = 0;\n\n char** result;\n\n\n\n result = func0(\"PythonProgramLanguage\", &count);\n\n assert(count == 3);\n\n assert(strcmp(result[0], \"Python\") == 0);\n\n assert(strcmp(result[1], \"Program\") == 0);\n\n assert(strcmp(result[2], \"Language\") == 0);\n\n for (int i = 0; i < count; i++) free(result[i]);\n\n free(result);\n\n\n\n result = func0(\"PythonProgram\", &count);\n\n assert(count == 2);\n\n assert(strcmp(result[0], \"Python\") == 0);\n\n assert(strcmp(result[1], \"Program\") == 0);\n\n for (int i = 0; i < count; i++) free(result[i]);\n\n free(result);\n\n\n\n result = func0(\"ProgrammingLanguage\", &count);\n\n assert(count == 2);\n\n assert(strcmp(result[0], \"Programming\") == 0);\n\n assert(strcmp(result[1], \"Language\") == 0);\n\n for (int i = 0; i < count; i++) free(result[i]);\n\n free(result);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\nmov %rdi,%r12\npush %rbp\npush %rbx\nsub $0x28,%rsp\nmov %rsi,0x18(%rsp)\ncallq 10e0 \nmovslq %eax,%rdi\nmov %eax,0x4(%rsp)\nmov %rax,%rbx\nshl $0x3,%rdi\ncallq 1120 \nmov %rax,0x10(%rsp)\ntest %rax,%rax\nje 1650 \nxor %ebp,%ebp\ntest %ebx,%ebx\njle 1635 \ncallq 1150 <__ctype_b_loc@plt>\nmov $0x1,%r13d\nxor %r15d,%r15d\nxor %ebp,%ebp\nmov (%rax),%rax\nmov %rax,0x8(%rsp)\nxchg %ax,%ax\nmovsbq (%r12,%r13,1),%rdx\nmov 0x8(%rsp),%rcx\nmov %r13d,%ebx\ntestb $0x1,0x1(%rcx,%rdx,2)\njne 15e8 \ntest %dl,%dl\njne 162a \nmov %ebx,%r14d\nsub %r15d,%r14d\nlea 0x1(%r14),%edi\nmovslq %edi,%rdi\ncallq 1120 \nmov 0x10(%rsp),%rcx\nmov %rax,%rdi\nmovslq %ebp,%rax\nmov %rdi,(%rcx,%rax,8)\ntest %rdi,%rdi\nje 1650 \nmovslq %r14d,%r14\nmovslq %r15d,%rsi\nadd $0x1,%ebp\nmov %ebx,%r15d\nadd %r12,%rsi\nmov %r14,%rdx\ncallq 1110 \nmovb $0x0,(%rax,%r14,1)\nadd $0x1,%r13\ncmp %r13d,0x4(%rsp)\njge 15d0 \nmov 0x18(%rsp),%rax\nmov %ebp,(%rax)\nmov 0x10(%rsp),%rax\nadd $0x28,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nlea 0x9ad(%rip),%rdi\ncallq 1130 \nmov $0x1,%edi\ncallq 1140 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 28h\nmov [rsp+58h+var_40], rsi\ncall _strlen\nmovsxd rdi, eax\nmov [rsp+58h+var_4C], eax\nmov rbx, rax\nshl rdi, 3; size\ncall _malloc\nmov [rsp+58h+var_48], rax\ntest rax, rax\njz func0_cold\ntest ebx, ebx\njle loc_1660\ncall ___ctype_b_loc\nmov r13d, 1\nxor r15d, r15d\nxor ebx, ebx\nmov r14, [rax]\nnop dword ptr [rax+rax+00h]\nloc_15D0:\nmovsx rcx, byte ptr [rbp+r13+0]\ntest byte ptr [r14+rcx*2+1], 1\njnz short loc_15E2\ntest cl, cl\njnz short loc_1636\nloc_15E2:\nmov r12d, r13d\nsub r12d, r15d\nlea ecx, [r12+1]\nmovsxd rcx, ecx\nmov rdi, rcx; size\nmov [rsp+58h+var_58], rcx\ncall _malloc\nmov rdx, [rsp+58h+var_48]\nmov rdi, rax\nmovsxd rax, ebx\nmov [rdx+rax*8], rdi\ntest rdi, rdi\njz func0_cold\nmovsxd rdx, r15d\nmovsxd r12, r12d\nmov rcx, [rsp+58h+var_58]\nadd ebx, 1\nlea rsi, [rbp+rdx+0]\nmov rdx, r12\nmov r15d, r13d\ncall ___memcpy_chk\nmov byte ptr [rax+r12], 0\nloc_1636:\nadd r13, 1\ncmp [rsp+58h+var_4C], r13d\njge short loc_15D0\nloc_1641:\nmov rax, [rsp+58h+var_40]\nmov [rax], ebx\nmov rax, [rsp+58h+var_48]\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1660:\nxor ebx, ebx\njmp short loc_1641", + "ida_pseudo": "_QWORD *__fastcall func0(const char *a1, _DWORD *a2)\n{\n __int64 v3; // r13\n int v4; // r15d\n int v5; // ebx\n const unsigned __int16 *v6; // r14\n __int64 v7; // rcx\n int v8; // r12d\n void *v9; // rdi\n const char *v10; // rsi\n int v12; // [rsp+Ch] [rbp-4Ch]\n _QWORD *v13; // [rsp+10h] [rbp-48h]\n\n v12 = strlen(a1);\n v13 = malloc(8LL * v12);\n if ( !v13 )\nLABEL_11:\n func0_cold();\n if ( v12 <= 0 )\n {\n v5 = 0;\n }\n else\n {\n v3 = 1LL;\n v4 = 0;\n v5 = 0;\n v6 = *__ctype_b_loc();\n do\n {\n v7 = a1[v3];\n if ( (v6[v7] & 0x100) != 0 || !(_BYTE)v7 )\n {\n v8 = v3 - v4;\n v9 = malloc((int)v3 - v4 + 1);\n v13[v5] = v9;\n if ( !v9 )\n goto LABEL_11;\n ++v5;\n v10 = &a1[v4];\n v4 = v3;\n *(_BYTE *)(__memcpy_chk(v9, v10, v8, v8 + 1) + v8) = 0;\n }\n ++v3;\n }\n while ( v12 >= (int)v3 );\n }\n *a2 = v5;\n return v13;\n}", + "ida_strip_asm": "sub_1570:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 28h\nmov [rsp+58h+var_40], rsi\ncall _strlen\nmovsxd rdi, eax\nmov [rsp+58h+var_4C], eax\nmov rbx, rax\nshl rdi, 3; size\ncall _malloc\nmov [rsp+58h+var_48], rax\ntest rax, rax\njz loc_1180\ntest ebx, ebx\njle loc_1660\ncall ___ctype_b_loc\nmov r13d, 1\nxor r15d, r15d\nxor ebx, ebx\nmov r14, [rax]\nnop dword ptr [rax+rax+00h]\nloc_15D0:\nmovsx rcx, byte ptr [rbp+r13+0]\ntest byte ptr [r14+rcx*2+1], 1\njnz short loc_15E2\ntest cl, cl\njnz short loc_1636\nloc_15E2:\nmov r12d, r13d\nsub r12d, r15d\nlea ecx, [r12+1]\nmovsxd rcx, ecx\nmov rdi, rcx; size\nmov [rsp+58h+var_58], rcx\ncall _malloc\nmov rdx, [rsp+58h+var_48]\nmov rdi, rax\nmovsxd rax, ebx\nmov [rdx+rax*8], rdi\ntest rdi, rdi\njz loc_1180\nmovsxd rdx, r15d\nmovsxd r12, r12d\nmov rcx, [rsp+58h+var_58]\nadd ebx, 1\nlea rsi, [rbp+rdx+0]\nmov rdx, r12\nmov r15d, r13d\ncall ___memcpy_chk\nmov byte ptr [rax+r12], 0\nloc_1636:\nadd r13, 1\ncmp [rsp+58h+var_4C], r13d\njge short loc_15D0\nloc_1641:\nmov rax, [rsp+58h+var_40]\nmov [rax], ebx\nmov rax, [rsp+58h+var_48]\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1660:\nxor ebx, ebx\njmp short loc_1641", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1570(const char *a1, _DWORD *a2)\n{\n __int64 v3; // r13\n int v4; // r15d\n int v5; // ebx\n const unsigned __int16 *v6; // r14\n __int64 v7; // rcx\n void *v8; // rdi\n int v9; // r12d\n const char *v10; // rsi\n size_t v12; // [rsp+0h] [rbp-58h]\n int v13; // [rsp+Ch] [rbp-4Ch]\n _QWORD *v14; // [rsp+10h] [rbp-48h]\n\n v13 = strlen(a1);\n v14 = malloc(8LL * v13);\n if ( !v14 )\n {\nLABEL_11:\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n if ( v13 <= 0 )\n {\n v5 = 0;\n }\n else\n {\n v3 = 1LL;\n v4 = 0;\n v5 = 0;\n v6 = *__ctype_b_loc();\n do\n {\n v7 = a1[v3];\n if ( (v6[v7] & 0x100) != 0 || !(_BYTE)v7 )\n {\n v12 = (int)v3 - v4 + 1;\n v8 = malloc(v12);\n v14[v5] = v8;\n if ( !v8 )\n goto LABEL_11;\n v9 = v3 - v4;\n ++v5;\n v10 = &a1[v4];\n v4 = v3;\n *(_BYTE *)(__memcpy_chk(v8, v10, v9, v12) + v9) = 0;\n }\n ++v3;\n }\n while ( v13 >= (int)v3 );\n }\n *a2 = v5;\n return v14;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1570(const char *a1, uint32_t *a2) {\n long long v3;\n int v4;\n int v5;\n const unsigned short *v6;\n long long v7;\n void *v8;\n int v9;\n const char *v10;\n unsigned int v12;\n int v13;\n uint64_t *v14;\n v13 = strlen(a1);\n v14 = malloc(8LL * v13);\n if (!v14) {\n LABEL_11:\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n if (v13 <= 0) {\n v5 = 0;\n } else {\n v3 = 1LL;\n v4 = 0;\n v5 = 0;\n v6 = *__ctype_b_loc();\n do {\n v7 = a1[v3];\n if ((v6[v7] & 256) != 0 || !(uint8_t)v7) {\n v12 = (int)v3 - v4 + 1;\n v8 = malloc(v12);\n v14[v5] = v8;\n if (!v8) goto LABEL_11;\n v9 = v3 - v4;\n ++v5;\n v10 = &a1[v4];\n v4 = v3;\n *(uint8_t *)(__memcpy_chk(v8, v10, v9, v12) + v9) = 0;\n }\n ++v3;\n } while (v13 >= (int)v3);\n }\n *a2 = v5;\n return v14;\n}", + "ida_pseudo_norm": "uint64_t *func0(const char *a1, uint32_t *a2) {\n long long v3;\n int v4;\n int v5;\n const unsigned short *v6;\n long long v7;\n int v8;\n void *v9;\n const char *v10;\n int v12;\n uint64_t *v13;\n v12 = strlen(a1);\n v13 = malloc(8LL * v12);\n if (!v13)\n LABEL_11:\n func0_cold();\n if (v12 <= 0) {\n v5 = 0;\n } else {\n v3 = 1LL;\n v4 = 0;\n v5 = 0;\n v6 = *__ctype_b_loc();\n do {\n v7 = a1[v3];\n if ((v6[v7] & 256) != 0 || !(uint8_t)v7) {\n v8 = v3 - v4;\n v9 = malloc((int)v3 - v4 + 1);\n v13[v5] = v9;\n if (!v9) goto LABEL_11;\n ++v5;\n v10 = &a1[v4];\n v4 = v3;\n *(uint8_t *)(__memcpy_chk(v9, v10, v8, v8 + 1) + v8) = 0;\n }\n ++v3;\n } while (v12 >= (int)v3);\n }\n *a2 = v5;\n return v13;\n}" + }, + { + "index": 648, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int lst[], int size) {\n int* result = malloc(size * sizeof(int));\n int i;\n for (i = 0; i < size; i += 2) {\n if (i + 1 < size) {\n result[i] = lst[i + 1];\n result[i + 1] = lst[i];\n } else {\n result[i] = lst[i];\n }\n }\n return result;\n}", + "test": "int main() {\n\n int lst1[] = {0, 1, 2, 3, 4, 5};\n\n int size1 = sizeof(lst1) / sizeof(lst1[0]);\n\n int* result1 = func0(lst1, size1);\n\n int expected1[] = {1, 0, 3, 2, 5, 4};\n\n for (int i = 0; i < size1; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n\n\n int lst2[] = {5, 6, 7, 8, 9, 10};\n\n int size2 = sizeof(lst2) / sizeof(lst2[0]);\n\n int* result2 = func0(lst2, size2);\n\n int expected2[] = {6, 5, 8, 7, 10, 9};\n\n for (int i = 0; i < size2; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n\n\n int lst3[] = {25, 35, 45, 55, 75, 95};\n\n int size3 = sizeof(lst3) / sizeof(lst3[0]);\n\n int* result3 = func0(lst3, size3);\n\n int expected3[] = {35, 25, 55, 45, 95, 75};\n\n for (int i = 0; i < size3; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov -0x1c(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0xc(%rbp)\njmpq 127d \nmov -0xc(%rbp),%eax\nadd $0x1,%eax\ncmp %eax,-0x1c(%rbp)\njle 124c \nmov -0xc(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0xc(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0xc(%rbp),%edx\nmovslq %edx,%rdx\nadd $0x1,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\njmp 1279 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0xc(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x2,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11dd \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp loc_127D\nloc_11DD:\nmov eax, [rbp+var_C]\nadd eax, 1\ncmp [rbp+var_1C], eax\njle short loc_124C\nmov eax, [rbp+var_C]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nadd rdx, 1\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\njmp short loc_1279\nloc_124C:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nloc_1279:\nadd [rbp+var_C], 2\nloc_127D:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl loc_11DD\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // rcx\n int i; // [rsp+14h] [rbp-Ch]\n _DWORD *v5; // [rsp+18h] [rbp-8h]\n\n v5 = malloc(4LL * a2);\n for ( i = 0; i < a2; i += 2 )\n {\n if ( a2 <= i + 1 )\n {\n v2 = i;\n }\n else\n {\n v5[i] = *(_DWORD *)(4 * (i + 1LL) + a1);\n v2 = i + 1LL;\n }\n v5[v2] = *(_DWORD *)(4LL * i + a1);\n }\n return v5;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp loc_127D\nloc_11DD:\nmov eax, [rbp+var_C]\nadd eax, 1\ncmp [rbp+var_1C], eax\njle short loc_124C\nmov eax, [rbp+var_C]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nadd rdx, 1\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\njmp short loc_1279\nloc_124C:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nloc_1279:\nadd [rbp+var_C], 2\nloc_127D:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl loc_11DD\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(__int64 a1, int a2)\n{\n __int64 v2; // rcx\n int i; // [rsp+14h] [rbp-Ch]\n _DWORD *v5; // [rsp+18h] [rbp-8h]\n\n v5 = malloc(4LL * a2);\n for ( i = 0; i < a2; i += 2 )\n {\n if ( a2 <= i + 1 )\n {\n v2 = i;\n }\n else\n {\n v5[i] = *(_DWORD *)(4 * (i + 1LL) + a1);\n v2 = i + 1LL;\n }\n v5[v2] = *(_DWORD *)(4LL * i + a1);\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(long long a1, int a2) {\n long long v2;\n int i;\n uint32_t *v5;\n v5 = malloc(4LL * a2);\n for (i = 0; i < a2; i += 2) {\n if (a2 <= i + 1) {\n v2 = i;\n } else {\n v5[i] = *(uint32_t *)(4 * (i + 1LL) + a1);\n v2 = i + 1LL;\n }\n v5[v2] = *(uint32_t *)(4LL * i + a1);\n }\n return v5;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2) {\n long long v2;\n int i;\n uint32_t *v5;\n v5 = malloc(4LL * a2);\n for (i = 0; i < a2; i += 2) {\n if (a2 <= i + 1) {\n v2 = i;\n } else {\n v5[i] = *(uint32_t *)(4 * (i + 1LL) + a1);\n v2 = i + 1LL;\n }\n v5[v2] = *(uint32_t *)(4LL * i + a1);\n }\n return v5;\n}" + }, + { + "index": 648, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int lst[], int size) {\n int* result = malloc(size * sizeof(int));\n int i;\n for (i = 0; i < size; i += 2) {\n if (i + 1 < size) {\n result[i] = lst[i + 1];\n result[i + 1] = lst[i];\n } else {\n result[i] = lst[i];\n }\n }\n return result;\n}", + "test": "int main() {\n\n int lst1[] = {0, 1, 2, 3, 4, 5};\n\n int size1 = sizeof(lst1) / sizeof(lst1[0]);\n\n int* result1 = func0(lst1, size1);\n\n int expected1[] = {1, 0, 3, 2, 5, 4};\n\n for (int i = 0; i < size1; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n\n\n int lst2[] = {5, 6, 7, 8, 9, 10};\n\n int size2 = sizeof(lst2) / sizeof(lst2[0]);\n\n int* result2 = func0(lst2, size2);\n\n int expected2[] = {6, 5, 8, 7, 10, 9};\n\n for (int i = 0; i < size2; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n\n\n int lst3[] = {25, 35, 45, 55, 75, 95};\n\n int size3 = sizeof(lst3) / sizeof(lst3[0]);\n\n int* result3 = func0(lst3, size3);\n\n int expected3[] = {35, 25, 55, 45, 95, 75};\n\n for (int i = 0; i < size3; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbp\nmov %esi,%ebx\nmovslq %esi,%rdi\nshl $0x2,%rdi\ncallq 10b0 \ntest %ebx,%ebx\njle 11f6 \nmov $0x0,%edx\njmp 11de \nmov 0x0(%rbp,%rdx,4),%ecx\nmov %ecx,(%rax,%rdx,4)\nadd $0x2,%rdx\ncmp %edx,%ebx\njle 11f6 \nlea 0x1(%rdx),%ecx\ncmp %ecx,%ebx\njle 11cf \nmov 0x4(%rbp,%rdx,4),%ecx\nmov %ecx,(%rax,%rdx,4)\nmov 0x0(%rbp,%rdx,4),%ecx\nmov %ecx,0x4(%rax,%rdx,4)\njmp 11d6 \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov ebx, esi\nmovsxd rdi, esi\nshl rdi, 2; size\ncall _malloc\ntest ebx, ebx\njle short loc_11F6\nmov edx, 0\njmp short loc_11DE\nloc_11CF:\nmov ecx, [rbp+rdx*4+0]\nmov [rax+rdx*4], ecx\nloc_11D6:\nadd rdx, 2\ncmp ebx, edx\njle short loc_11F6\nloc_11DE:\nlea ecx, [rdx+1]\ncmp ebx, ecx\njle short loc_11CF\nmov ecx, [rbp+rdx*4+4]\nmov [rax+rdx*4], ecx\nmov ecx, [rbp+rdx*4+0]\nmov [rax+rdx*4+4], ecx\njmp short loc_11D6\nloc_11F6:\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2)\n{\n _DWORD *result; // rax\n __int64 v3; // rdx\n\n result = malloc(4LL * a2);\n if ( a2 > 0 )\n {\n v3 = 0LL;\n do\n {\n if ( a2 <= (int)v3 + 1 )\n {\n result[v3] = *(_DWORD *)(a1 + 4 * v3);\n }\n else\n {\n result[v3] = *(_DWORD *)(a1 + 4 * v3 + 4);\n result[v3 + 1] = *(_DWORD *)(a1 + 4 * v3);\n }\n v3 += 2LL;\n }\n while ( a2 > (int)v3 );\n }\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov ebx, esi\nmovsxd rdi, esi\nshl rdi, 2; size\ncall _malloc\ntest ebx, ebx\njle short loc_11F6\nmov edx, 0\njmp short loc_11DE\nloc_11CF:\nmov ecx, [rbp+rdx*4+0]\nmov [rax+rdx*4], ecx\nloc_11D6:\nadd rdx, 2\ncmp ebx, edx\njle short loc_11F6\nloc_11DE:\nlea ecx, [rdx+1]\ncmp ebx, ecx\njle short loc_11CF\nmov ecx, [rbp+rdx*4+4]\nmov [rax+rdx*4], ecx\nmov ecx, [rbp+rdx*4+0]\nmov [rax+rdx*4+4], ecx\njmp short loc_11D6\nloc_11F6:\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(__int64 a1, int a2)\n{\n _DWORD *result; // rax\n __int64 v3; // rdx\n\n result = malloc(4LL * a2);\n if ( a2 > 0 )\n {\n v3 = 0LL;\n do\n {\n if ( a2 <= (int)v3 + 1 )\n {\n result[v3] = *(_DWORD *)(a1 + 4 * v3);\n }\n else\n {\n result[v3] = *(_DWORD *)(a1 + 4 * v3 + 4);\n result[v3 + 1] = *(_DWORD *)(a1 + 4 * v3);\n }\n v3 += 2LL;\n }\n while ( a2 > (int)v3 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(long long a1, int a2) {\n uint32_t *result;\n long long v3;\n result = malloc(4LL * a2);\n if (a2 > 0) {\n v3 = 0LL;\n do {\n if (a2 <= (int)v3 + 1) {\n result[v3] = *(uint32_t *)(a1 + 4 * v3);\n } else {\n result[v3] = *(uint32_t *)(a1 + 4 * v3 + 4);\n result[v3 + 1] = *(uint32_t *)(a1 + 4 * v3);\n }\n v3 += 2LL;\n } while (a2 > (int)v3);\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2) {\n uint32_t *result;\n long long v3;\n result = malloc(4LL * a2);\n if (a2 > 0) {\n v3 = 0LL;\n do {\n if (a2 <= (int)v3 + 1) {\n result[v3] = *(uint32_t *)(a1 + 4 * v3);\n } else {\n result[v3] = *(uint32_t *)(a1 + 4 * v3 + 4);\n result[v3 + 1] = *(uint32_t *)(a1 + 4 * v3);\n }\n v3 += 2LL;\n } while (a2 > (int)v3);\n }\n return result;\n}" + }, + { + "index": 648, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int lst[], int size) {\n int* result = malloc(size * sizeof(int));\n int i;\n for (i = 0; i < size; i += 2) {\n if (i + 1 < size) {\n result[i] = lst[i + 1];\n result[i + 1] = lst[i];\n } else {\n result[i] = lst[i];\n }\n }\n return result;\n}", + "test": "int main() {\n\n int lst1[] = {0, 1, 2, 3, 4, 5};\n\n int size1 = sizeof(lst1) / sizeof(lst1[0]);\n\n int* result1 = func0(lst1, size1);\n\n int expected1[] = {1, 0, 3, 2, 5, 4};\n\n for (int i = 0; i < size1; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n\n\n int lst2[] = {5, 6, 7, 8, 9, 10};\n\n int size2 = sizeof(lst2) / sizeof(lst2[0]);\n\n int* result2 = func0(lst2, size2);\n\n int expected2[] = {6, 5, 8, 7, 10, 9};\n\n for (int i = 0; i < size2; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n\n\n int lst3[] = {25, 35, 45, 55, 75, 95};\n\n int size3 = sizeof(lst3) / sizeof(lst3[0]);\n\n int* result3 = func0(lst3, size3);\n\n int expected3[] = {35, 25, 55, 45, 95, 75};\n\n for (int i = 0; i < size3; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rdi,%rbp\nmovslq %esi,%rdi\npush %rbx\nmov %rdi,%rbx\nshl $0x2,%rdi\nsub $0x8,%rsp\ncallq 10b0 \ntest %ebx,%ebx\njle 1481 \nxor %edx,%edx\njmp 146b \nnopl 0x0(%rax)\nmov 0x4(%rbp,%rdx,4),%ecx\nmov %esi,0x4(%rax,%rdx,4)\nmov %ecx,(%rax,%rdx,4)\nadd $0x2,%rdx\ncmp %edx,%ebx\njle 1481 \nlea 0x1(%rdx),%ecx\nmov 0x0(%rbp,%rdx,4),%esi\ncmp %ecx,%ebx\njg 1458 \nmov %esi,(%rax,%rdx,4)\nadd $0x2,%rdx\ncmp %edx,%ebx\njg 146b \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rdi\nmovsxd rdi, esi\npush rbx\nmov rbx, rdi\nshl rdi, 2; size\nsub rsp, 8\ncall _malloc\ntest ebx, ebx\njle short loc_1409\nxor edx, edx\njmp short loc_13EF\nloc_13D8:\nmovd xmm1, dword ptr [rbp+rdx*4+4]\npunpckldq xmm1, xmm0\nmovq qword ptr [rax+rdx*4], xmm1\nadd rdx, 2\ncmp ebx, edx\njle short loc_1409\nloc_13EF:\nlea ecx, [rdx+1]\nmovd xmm0, dword ptr [rbp+rdx*4+0]\ncmp ebx, ecx\njg short loc_13D8\nmovd dword ptr [rax+rdx*4], xmm0\nadd rdx, 2\ncmp ebx, edx\njg short loc_13EF\nloc_1409:\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2)\n{\n _DWORD *result; // rax\n __int64 v3; // rdx\n __m128i v4; // xmm0\n\n result = malloc(4LL * a2);\n if ( a2 > 0 )\n {\n v3 = 0LL;\n do\n {\n while ( 1 )\n {\n v4 = _mm_cvtsi32_si128(*(_DWORD *)(a1 + 4 * v3));\n if ( a2 <= (int)v3 + 1 )\n break;\n *(_QWORD *)&result[v3] = _mm_unpacklo_epi32(_mm_cvtsi32_si128(*(_DWORD *)(a1 + 4 * v3 + 4)), v4).m128i_u64[0];\n v3 += 2LL;\n if ( a2 <= (int)v3 )\n return result;\n }\n result[v3] = _mm_cvtsi128_si32(v4);\n v3 += 2LL;\n }\n while ( a2 > (int)v3 );\n }\n return result;\n}", + "ida_strip_asm": "sub_13B0:\nendbr64\npush rbp\nmov rbp, rdi\nmovsxd rdi, esi\npush rbx\nmov rbx, rdi\nshl rdi, 2; size\nsub rsp, 8\ncall _malloc\ntest ebx, ebx\njle short loc_1409\nxor edx, edx\njmp short loc_13EF\nloc_13D8:\nmovd xmm1, dword ptr [rbp+rdx*4+4]\npunpckldq xmm1, xmm0\nmovq qword ptr [rax+rdx*4], xmm1\nadd rdx, 2\ncmp ebx, edx\njle short loc_1409\nloc_13EF:\nlea ecx, [rdx+1]\nmovd xmm0, dword ptr [rbp+rdx*4+0]\ncmp ebx, ecx\njg short loc_13D8\nmovd dword ptr [rax+rdx*4], xmm0\nadd rdx, 2\ncmp ebx, edx\njg short loc_13EF\nloc_1409:\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_13B0(__int64 a1, int a2)\n{\n _DWORD *result; // rax\n __int64 v3; // rdx\n __m128i v4; // xmm0\n\n result = malloc(4LL * a2);\n if ( a2 > 0 )\n {\n v3 = 0LL;\n do\n {\n while ( 1 )\n {\n v4 = _mm_cvtsi32_si128(*(_DWORD *)(a1 + 4 * v3));\n if ( a2 <= (int)v3 + 1 )\n break;\n *(_QWORD *)&result[v3] = _mm_unpacklo_epi32(_mm_cvtsi32_si128(*(_DWORD *)(a1 + 4 * v3 + 4)), v4).m128i_u64[0];\n v3 += 2LL;\n if ( a2 <= (int)v3 )\n return result;\n }\n result[v3] = _mm_cvtsi128_si32(v4);\n v3 += 2LL;\n }\n while ( a2 > (int)v3 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_13B0(long long a1, int a2) {\n uint32_t *result;\n long long v3;\n __m128i v4;\n result = malloc(4LL * a2);\n if (a2 > 0) {\n v3 = 0LL;\n do {\n while (1) {\n v4 = _mm_cvtsi32_si128(*(uint32_t *)(a1 + 4 * v3));\n if (a2 <= (int)v3 + 1) break;\n *(uint64_t *)&result[v3] =\n _mm_unpacklo_epi32(\n _mm_cvtsi32_si128(*(uint32_t *)(a1 + 4 * v3 + 4)), v4)\n .m128i_u64[0];\n v3 += 2LL;\n if (a2 <= (int)v3) return result;\n }\n result[v3] = _mm_cvtsi128_si32(v4);\n v3 += 2LL;\n } while (a2 > (int)v3);\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2) {\n uint32_t *result;\n long long v3;\n __m128i v4;\n result = malloc(4LL * a2);\n if (a2 > 0) {\n v3 = 0LL;\n do {\n while (1) {\n v4 = _mm_cvtsi32_si128(*(uint32_t *)(a1 + 4 * v3));\n if (a2 <= (int)v3 + 1) break;\n *(uint64_t *)&result[v3] =\n _mm_unpacklo_epi32(\n _mm_cvtsi32_si128(*(uint32_t *)(a1 + 4 * v3 + 4)), v4)\n .m128i_u64[0];\n v3 += 2LL;\n if (a2 <= (int)v3) return result;\n }\n result[v3] = _mm_cvtsi128_si32(v4);\n v3 += 2LL;\n } while (a2 > (int)v3);\n }\n return result;\n}" + }, + { + "index": 648, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int lst[], int size) {\n int* result = malloc(size * sizeof(int));\n int i;\n for (i = 0; i < size; i += 2) {\n if (i + 1 < size) {\n result[i] = lst[i + 1];\n result[i + 1] = lst[i];\n } else {\n result[i] = lst[i];\n }\n }\n return result;\n}", + "test": "int main() {\n\n int lst1[] = {0, 1, 2, 3, 4, 5};\n\n int size1 = sizeof(lst1) / sizeof(lst1[0]);\n\n int* result1 = func0(lst1, size1);\n\n int expected1[] = {1, 0, 3, 2, 5, 4};\n\n for (int i = 0; i < size1; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n\n\n int lst2[] = {5, 6, 7, 8, 9, 10};\n\n int size2 = sizeof(lst2) / sizeof(lst2[0]);\n\n int* result2 = func0(lst2, size2);\n\n int expected2[] = {6, 5, 8, 7, 10, 9};\n\n for (int i = 0; i < size2; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n\n\n int lst3[] = {25, 35, 45, 55, 75, 95};\n\n int size3 = sizeof(lst3) / sizeof(lst3[0]);\n\n int* result3 = func0(lst3, size3);\n\n int expected3[] = {35, 25, 55, 45, 95, 75};\n\n for (int i = 0; i < size3; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rdi,%rbp\nmovslq %esi,%rdi\npush %rbx\nmov %rdi,%rbx\nshl $0x2,%rdi\nsub $0x8,%rsp\ncallq 10b0 \ntest %ebx,%ebx\njle 1451 \nxor %edx,%edx\njmp 143b \nnopl 0x0(%rax)\nmov 0x4(%rbp,%rdx,4),%ecx\nmov %esi,0x4(%rax,%rdx,4)\nmov %ecx,(%rax,%rdx,4)\nadd $0x2,%rdx\ncmp %edx,%ebx\njle 1451 \nlea 0x1(%rdx),%ecx\nmov 0x0(%rbp,%rdx,4),%esi\ncmp %ebx,%ecx\njl 1428 \nmov %esi,(%rax,%rdx,4)\nadd $0x2,%rdx\ncmp %edx,%ebx\njg 143b \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rdi\nmovsxd rdi, esi\npush rbx\nmov rbx, rdi\nshl rdi, 2; size\nsub rsp, 8\ncall _malloc\ntest ebx, ebx\njle short loc_13D9\nxor edx, edx\njmp short loc_13BF\nloc_13A8:\nmovd xmm1, dword ptr [rbp+rdx*4+4]\npunpckldq xmm1, xmm0\nmovq qword ptr [rax+rdx*4], xmm1\nadd rdx, 2\ncmp ebx, edx\njle short loc_13D9\nloc_13BF:\nlea ecx, [rdx+1]\nmovd xmm0, dword ptr [rbp+rdx*4+0]\ncmp ebx, ecx\njg short loc_13A8\nmovd dword ptr [rax+rdx*4], xmm0\nadd rdx, 2\ncmp ebx, edx\njg short loc_13BF\nloc_13D9:\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2)\n{\n _DWORD *result; // rax\n __int64 v3; // rdx\n __m128i v4; // xmm0\n\n result = malloc(4LL * a2);\n if ( a2 > 0 )\n {\n v3 = 0LL;\n do\n {\n while ( 1 )\n {\n v4 = _mm_cvtsi32_si128(*(_DWORD *)(a1 + 4 * v3));\n if ( a2 <= (int)v3 + 1 )\n break;\n *(_QWORD *)&result[v3] = _mm_unpacklo_epi32(_mm_cvtsi32_si128(*(_DWORD *)(a1 + 4 * v3 + 4)), v4).m128i_u64[0];\n v3 += 2LL;\n if ( a2 <= (int)v3 )\n return result;\n }\n result[v3] = _mm_cvtsi128_si32(v4);\n v3 += 2LL;\n }\n while ( a2 > (int)v3 );\n }\n return result;\n}", + "ida_strip_asm": "sub_1380:\nendbr64\npush rbp\nmov rbp, rdi\nmovsxd rdi, esi\npush rbx\nmov rbx, rdi\nshl rdi, 2; size\nsub rsp, 8\ncall _malloc\ntest ebx, ebx\njle short loc_13D9\nxor edx, edx\njmp short loc_13BF\nloc_13A8:\nmovd xmm1, dword ptr [rbp+rdx*4+4]\npunpckldq xmm1, xmm0\nmovq qword ptr [rax+rdx*4], xmm1\nadd rdx, 2\ncmp ebx, edx\njle short loc_13D9\nloc_13BF:\nlea ecx, [rdx+1]\nmovd xmm0, dword ptr [rbp+rdx*4+0]\ncmp ebx, ecx\njg short loc_13A8\nmovd dword ptr [rax+rdx*4], xmm0\nadd rdx, 2\ncmp ebx, edx\njg short loc_13BF\nloc_13D9:\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1380(__int64 a1, int a2)\n{\n _DWORD *result; // rax\n __int64 v3; // rdx\n __m128i v4; // xmm0\n\n result = malloc(4LL * a2);\n if ( a2 > 0 )\n {\n v3 = 0LL;\n do\n {\n while ( 1 )\n {\n v4 = _mm_cvtsi32_si128(*(_DWORD *)(a1 + 4 * v3));\n if ( a2 <= (int)v3 + 1 )\n break;\n *(_QWORD *)&result[v3] = _mm_unpacklo_epi32(_mm_cvtsi32_si128(*(_DWORD *)(a1 + 4 * v3 + 4)), v4).m128i_u64[0];\n v3 += 2LL;\n if ( a2 <= (int)v3 )\n return result;\n }\n result[v3] = _mm_cvtsi128_si32(v4);\n v3 += 2LL;\n }\n while ( a2 > (int)v3 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1380(long long a1, int a2) {\n uint32_t *result;\n long long v3;\n __m128i v4;\n result = malloc(4LL * a2);\n if (a2 > 0) {\n v3 = 0LL;\n do {\n while (1) {\n v4 = _mm_cvtsi32_si128(*(uint32_t *)(a1 + 4 * v3));\n if (a2 <= (int)v3 + 1) break;\n *(uint64_t *)&result[v3] =\n _mm_unpacklo_epi32(\n _mm_cvtsi32_si128(*(uint32_t *)(a1 + 4 * v3 + 4)), v4)\n .m128i_u64[0];\n v3 += 2LL;\n if (a2 <= (int)v3) return result;\n }\n result[v3] = _mm_cvtsi128_si32(v4);\n v3 += 2LL;\n } while (a2 > (int)v3);\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2) {\n uint32_t *result;\n long long v3;\n __m128i v4;\n result = malloc(4LL * a2);\n if (a2 > 0) {\n v3 = 0LL;\n do {\n while (1) {\n v4 = _mm_cvtsi32_si128(*(uint32_t *)(a1 + 4 * v3));\n if (a2 <= (int)v3 + 1) break;\n *(uint64_t *)&result[v3] =\n _mm_unpacklo_epi32(\n _mm_cvtsi32_si128(*(uint32_t *)(a1 + 4 * v3 + 4)), v4)\n .m128i_u64[0];\n v3 += 2LL;\n if (a2 <= (int)v3) return result;\n }\n result[v3] = _mm_cvtsi128_si32(v4);\n v3 += 2LL;\n } while (a2 > (int)v3);\n }\n return result;\n}" + }, + { + "index": 649, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int nums[], int m, int n) {\n int sum_range = 0;\n for (int i = m; i <= n; i++) {\n sum_range += nums[i];\n }\n return sum_range;\n}", + "test": "int main() {\n\n int arr1[] = {2, 1, 5, 6, 8, 3, 4, 9, 10, 11, 8, 12};\n\n assert(func0(arr1, 8, 10) == 29);\n\n \n\n int arr2[] = {1, 2, 3, 4, 5};\n\n assert(func0(arr2, 1, 2) == 5);\n\n \n\n int arr3[] = {1, 0, 1, 2, 5, 6};\n\n assert(func0(arr3, 4, 5) == 11);\n\n \n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmovl $0x0,-0x8(%rbp)\nmov -0x1c(%rbp),%eax\nmov %eax,-0x4(%rbp)\njmp 11a7 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nadd %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x20(%rbp),%eax\njle 118a \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_8], 0\nmov eax, [rbp+var_1C]\nmov [rbp+var_4], eax\njmp short loc_11A7\nloc_118A:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_11A7:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_20]\njle short loc_118A\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n unsigned int v4; // [rsp+18h] [rbp-8h]\n\n v4 = 0;\n while ( a2 <= a3 )\n v4 += *(_DWORD *)(4LL * a2++ + a1);\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_8], 0\nmov eax, [rbp+var_1C]\nmov [rbp+var_4], eax\njmp short loc_11A7\nloc_118A:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_11A7:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_20]\njle short loc_118A\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n unsigned int v4; // [rsp+18h] [rbp-8h]\n\n v4 = 0;\n while ( a2 <= a3 )\n v4 += *(_DWORD *)(4LL * a2++ + a1);\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n unsigned int v4;\n v4 = 0;\n while (a2 <= a3) v4 += *(uint32_t *)(4LL * a2++ + a1);\n return v4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n unsigned int v4;\n v4 = 0;\n while (a2 <= a3) v4 += *(uint32_t *)(4LL * a2++ + a1);\n return v4;\n}" + }, + { + "index": 649, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int nums[], int m, int n) {\n int sum_range = 0;\n for (int i = m; i <= n; i++) {\n sum_range += nums[i];\n }\n return sum_range;\n}", + "test": "int main() {\n\n int arr1[] = {2, 1, 5, 6, 8, 3, 4, 9, 10, 11, 8, 12};\n\n assert(func0(arr1, 8, 10) == 29);\n\n \n\n int arr2[] = {1, 2, 3, 4, 5};\n\n assert(func0(arr2, 1, 2) == 5);\n\n \n\n int arr3[] = {1, 0, 1, 2, 5, 6};\n\n assert(func0(arr3, 4, 5) == 11);\n\n \n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ncmp %edx,%esi\njg 1195 \nmovslq %esi,%rcx\nlea (%rdi,%rcx,4),%rax\nsub %esi,%edx\nadd %rcx,%rdx\nlea 0x4(%rdi,%rdx,4),%rcx\nmov $0x0,%edx\nadd (%rax),%edx\nadd $0x4,%rax\ncmp %rcx,%rax\njne 1187 \nmov %edx,%eax\nretq\nmov $0x0,%edx\njmp 1192 \n", + "ida_asm": "func0:\nendbr64\ncmp esi, edx\njg short loc_1195\nmovsxd rcx, esi\nlea rax, [rdi+rcx*4]\nsub edx, esi\nadd rdx, rcx\nlea rcx, [rdi+rdx*4+4]\nmov edx, 0\nloc_1187:\nadd edx, [rax]\nadd rax, 4\ncmp rax, rcx\njnz short loc_1187\nloc_1192:\nmov eax, edx\nretn\nloc_1195:\nmov edx, 0\njmp short loc_1192", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n _DWORD *v3; // rax\n unsigned __int64 v4; // rcx\n unsigned int v5; // edx\n\n if ( a2 > a3 )\n {\n return 0;\n }\n else\n {\n v3 = (_DWORD *)(a1 + 4LL * a2);\n v4 = a1 + 4 * (a2 + (unsigned __int64)(unsigned int)(a3 - a2)) + 4;\n v5 = 0;\n do\n v5 += *v3++;\n while ( v3 != (_DWORD *)v4 );\n }\n return v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ncmp esi, edx\njg short loc_1195\nmovsxd rcx, esi\nlea rax, [rdi+rcx*4]\nsub edx, esi\nadd rdx, rcx\nlea rcx, [rdi+rdx*4+4]\nmov edx, 0\nloc_1187:\nadd edx, [rax]\nadd rax, 4\ncmp rax, rcx\njnz short loc_1187\nloc_1192:\nmov eax, edx\nretn\nloc_1195:\nmov edx, 0\njmp short loc_1192", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n _DWORD *v3; // rax\n unsigned __int64 v4; // rcx\n unsigned int v5; // edx\n\n if ( a2 > a3 )\n {\n return 0;\n }\n else\n {\n v3 = (_DWORD *)(a1 + 4LL * a2);\n v4 = a1 + 4 * (a2 + (unsigned __int64)(unsigned int)(a3 - a2)) + 4;\n v5 = 0;\n do\n v5 += *v3++;\n while ( v3 != (_DWORD *)v4 );\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n uint32_t *v3;\n unsigned long long v4;\n unsigned int v5;\n if (a2 > a3) {\n return 0;\n } else {\n v3 = (uint32_t *)(a1 + 4LL * a2);\n v4 = a1 + 4 * (a2 + (unsigned long long)(unsigned int)(a3 - a2)) + 4;\n v5 = 0;\n do\n v5 += *v3++;\n while (v3 != (uint32_t *)v4);\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n uint32_t *v3;\n unsigned long long v4;\n unsigned int v5;\n if (a2 > a3) {\n return 0;\n } else {\n v3 = (uint32_t *)(a1 + 4LL * a2);\n v4 = a1 + 4 * (a2 + (unsigned long long)(unsigned int)(a3 - a2)) + 4;\n v5 = 0;\n do\n v5 += *v3++;\n while (v3 != (uint32_t *)v4);\n }\n return v5;\n}" + }, + { + "index": 650, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int arr1[], int arr2[], int n, int m) {\n if (n != m) {\n return false;\n }\n for (int i = 0; i < n - 1; i++) {\n for (int j = 0; j < n - i - 1; j++) {\n if (arr1[j] > arr1[j + 1]) {\n int temp = arr1[j];\n arr1[j] = arr1[j + 1];\n arr1[j + 1] = temp;\n }\n }\n }\n for (int i = 0; i < n - 1; i++) {\n for (int j = 0; j < n - i - 1; j++) {\n if (arr2[j] > arr2[j + 1]) {\n int temp = arr2[j];\n arr2[j] = arr2[j + 1];\n arr2[j + 1] = temp;\n }\n }\n }\n for (int i = 0; i < n; i++) {\n if (arr1[i] != arr2[i]) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3};\n\n int arr2[] = {3, 2, 1};\n\n int arr3[] = {1, 1, 1};\n\n int arr4[] = {2, 2, 2};\n\n int arr5[] = {8, 9};\n\n int arr6[] = {4, 5, 6};\n\n\n\n assert(func0(arr1, arr2, 3, 3) == true);\n\n assert(func0(arr3, arr4, 3, 3) == false);\n\n assert(func0(arr5, arr6, 2, 3) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x28(%rbp)\nmov %rsi,-0x30(%rbp)\nmov %edx,-0x34(%rbp)\nmov %ecx,-0x38(%rbp)\nmov -0x34(%rbp),%eax\ncmp -0x38(%rbp),%eax\nje 1191 \nmov $0x0,%eax\njmpq 139a \nmovl $0x0,-0x1c(%rbp)\njmpq 125e \nmovl $0x0,-0x18(%rbp)\njmpq 1248 \nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x18(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njle 1244 \nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x4(%rbp)\nmov -0x18(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov -0x18(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x28(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\nmov -0x18(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rax,%rdx\nmov -0x4(%rbp),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x18(%rbp)\nmov -0x34(%rbp),%eax\nsub -0x1c(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x18(%rbp)\njl 11a9 \naddl $0x1,-0x1c(%rbp)\nmov -0x34(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x1c(%rbp)\njl 119d \nmovl $0x0,-0x14(%rbp)\njmpq 133a \nmovl $0x0,-0x10(%rbp)\njmpq 1324 \nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x30(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x10(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rcx\nmov -0x30(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njle 1320 \nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x30(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x8(%rbp)\nmov -0x10(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x30(%rbp),%rax\nadd %rdx,%rax\nmov -0x10(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x30(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\nmov -0x10(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x30(%rbp),%rax\nadd %rax,%rdx\nmov -0x8(%rbp),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x10(%rbp)\nmov -0x34(%rbp),%eax\nsub -0x14(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x10(%rbp)\njl 1285 \naddl $0x1,-0x14(%rbp)\nmov -0x34(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x14(%rbp)\njl 1279 \nmovl $0x0,-0xc(%rbp)\njmp 138d \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x30(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\nje 1389 \nmov $0x0,%eax\njmp 139a \naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x34(%rbp),%eax\njl 1352 \nmov $0x1,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_30], rsi\nmov [rbp+var_34], edx\nmov [rbp+var_38], ecx\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_38]\njz short loc_1191\nmov eax, 0\njmp loc_139A\nloc_1191:\nmov [rbp+var_1C], 0\njmp loc_125E\nloc_119D:\nmov [rbp+var_18], 0\njmp loc_1248\nloc_11A9:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_18]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_1244\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_18]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_18]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_18]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nloc_1244:\nadd [rbp+var_18], 1\nloc_1248:\nmov eax, [rbp+var_34]\nsub eax, [rbp+var_1C]\nsub eax, 1\ncmp [rbp+var_18], eax\njl loc_11A9\nadd [rbp+var_1C], 1\nloc_125E:\nmov eax, [rbp+var_34]\nsub eax, 1\ncmp [rbp+var_1C], eax\njl loc_119D\nmov [rbp+var_14], 0\njmp loc_133A\nloc_1279:\nmov [rbp+var_10], 0\njmp loc_1324\nloc_1285:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_30]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_1320\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_8], eax\nmov eax, [rbp+var_10]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_30]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_10]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_30]\nadd rdx, rax\nmov eax, [rbp+var_8]\nmov [rdx], eax\nloc_1320:\nadd [rbp+var_10], 1\nloc_1324:\nmov eax, [rbp+var_34]\nsub eax, [rbp+var_14]\nsub eax, 1\ncmp [rbp+var_10], eax\njl loc_1285\nadd [rbp+var_14], 1\nloc_133A:\nmov eax, [rbp+var_34]\nsub eax, 1\ncmp [rbp+var_14], eax\njl loc_1279\nmov [rbp+var_C], 0\njmp short loc_138D\nloc_1352:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_30]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_1389\nmov eax, 0\njmp short loc_139A\nloc_1389:\nadd [rbp+var_C], 1\nloc_138D:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_34]\njl short loc_1352\nmov eax, 1\nloc_139A:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3, int a4)\n{\n int i; // [rsp+1Ch] [rbp-1Ch]\n int j; // [rsp+20h] [rbp-18h]\n int k; // [rsp+24h] [rbp-14h]\n int m; // [rsp+28h] [rbp-10h]\n int n; // [rsp+2Ch] [rbp-Ch]\n int v10; // [rsp+30h] [rbp-8h]\n int v11; // [rsp+34h] [rbp-4h]\n\n if ( a3 != a4 )\n return 0LL;\n for ( i = 0; i < a3 - 1; ++i )\n {\n for ( j = 0; j < a3 - i - 1; ++j )\n {\n if ( *(_DWORD *)(4LL * j + a1) > *(_DWORD *)(4 * (j + 1LL) + a1) )\n {\n v11 = *(_DWORD *)(4LL * j + a1);\n *(_DWORD *)(4LL * j + a1) = *(_DWORD *)(4 * (j + 1LL) + a1);\n *(_DWORD *)(a1 + 4 * (j + 1LL)) = v11;\n }\n }\n }\n for ( k = 0; k < a3 - 1; ++k )\n {\n for ( m = 0; m < a3 - k - 1; ++m )\n {\n if ( *(_DWORD *)(4LL * m + a2) > *(_DWORD *)(4 * (m + 1LL) + a2) )\n {\n v10 = *(_DWORD *)(4LL * m + a2);\n *(_DWORD *)(4LL * m + a2) = *(_DWORD *)(4 * (m + 1LL) + a2);\n *(_DWORD *)(a2 + 4 * (m + 1LL)) = v10;\n }\n }\n }\n for ( n = 0; n < a3; ++n )\n {\n if ( *(_DWORD *)(4LL * n + a1) != *(_DWORD *)(4LL * n + a2) )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_30], rsi\nmov [rbp+var_34], edx\nmov [rbp+var_38], ecx\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_38]\njz short loc_1191\nmov eax, 0\njmp loc_139A\nloc_1191:\nmov [rbp+var_1C], 0\njmp loc_125E\nloc_119D:\nmov [rbp+var_18], 0\njmp loc_1248\nloc_11A9:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_18]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_1244\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_18]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_18]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_18]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nloc_1244:\nadd [rbp+var_18], 1\nloc_1248:\nmov eax, [rbp+var_34]\nsub eax, [rbp+var_1C]\nsub eax, 1\ncmp [rbp+var_18], eax\njl loc_11A9\nadd [rbp+var_1C], 1\nloc_125E:\nmov eax, [rbp+var_34]\nsub eax, 1\ncmp [rbp+var_1C], eax\njl loc_119D\nmov [rbp+var_14], 0\njmp loc_133A\nloc_1279:\nmov [rbp+var_10], 0\njmp loc_1324\nloc_1285:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_30]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_1320\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_8], eax\nmov eax, [rbp+var_10]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_30]\nadd rax, rdx\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_30]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_10]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_30]\nadd rdx, rax\nmov eax, [rbp+var_8]\nmov [rdx], eax\nloc_1320:\nadd [rbp+var_10], 1\nloc_1324:\nmov eax, [rbp+var_34]\nsub eax, [rbp+var_14]\nsub eax, 1\ncmp [rbp+var_10], eax\njl loc_1285\nadd [rbp+var_14], 1\nloc_133A:\nmov eax, [rbp+var_34]\nsub eax, 1\ncmp [rbp+var_14], eax\njl loc_1279\nmov [rbp+var_C], 0\njmp short loc_138D\nloc_1352:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_30]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_1389\nmov eax, 0\njmp short loc_139A\nloc_1389:\nadd [rbp+var_C], 1\nloc_138D:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_34]\njl short loc_1352\nmov eax, 1\nloc_139A:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, int a3, int a4)\n{\n int i; // [rsp+1Ch] [rbp-1Ch]\n int j; // [rsp+20h] [rbp-18h]\n int k; // [rsp+24h] [rbp-14h]\n int m; // [rsp+28h] [rbp-10h]\n int n; // [rsp+2Ch] [rbp-Ch]\n int v10; // [rsp+30h] [rbp-8h]\n int v11; // [rsp+34h] [rbp-4h]\n\n if ( a3 != a4 )\n return 0LL;\n for ( i = 0; i < a3 - 1; ++i )\n {\n for ( j = 0; j < a3 - i - 1; ++j )\n {\n if ( *(_DWORD *)(4LL * j + a1) > *(_DWORD *)(4 * (j + 1LL) + a1) )\n {\n v11 = *(_DWORD *)(4LL * j + a1);\n *(_DWORD *)(4LL * j + a1) = *(_DWORD *)(4 * (j + 1LL) + a1);\n *(_DWORD *)(a1 + 4 * (j + 1LL)) = v11;\n }\n }\n }\n for ( k = 0; k < a3 - 1; ++k )\n {\n for ( m = 0; m < a3 - k - 1; ++m )\n {\n if ( *(_DWORD *)(4LL * m + a2) > *(_DWORD *)(4 * (m + 1LL) + a2) )\n {\n v10 = *(_DWORD *)(4LL * m + a2);\n *(_DWORD *)(4LL * m + a2) = *(_DWORD *)(4 * (m + 1LL) + a2);\n *(_DWORD *)(a2 + 4 * (m + 1LL)) = v10;\n }\n }\n }\n for ( n = 0; n < a3; ++n )\n {\n if ( *(_DWORD *)(4LL * n + a1) != *(_DWORD *)(4LL * n + a2) )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, int a3, int a4) {\n int i;\n int j;\n int k;\n int m;\n int n;\n int v10;\n int v11;\n if (a3 != a4) return 0LL;\n for (i = 0; i < a3 - 1; ++i) {\n for (j = 0; j < a3 - i - 1; ++j) {\n if (*(uint32_t *)(4LL * j + a1) > *(uint32_t *)(4 * (j + 1LL) + a1)) {\n v11 = *(uint32_t *)(4LL * j + a1);\n *(uint32_t *)(4LL * j + a1) = *(uint32_t *)(4 * (j + 1LL) + a1);\n *(uint32_t *)(a1 + 4 * (j + 1LL)) = v11;\n }\n }\n }\n for (k = 0; k < a3 - 1; ++k) {\n for (m = 0; m < a3 - k - 1; ++m) {\n if (*(uint32_t *)(4LL * m + a2) > *(uint32_t *)(4 * (m + 1LL) + a2)) {\n v10 = *(uint32_t *)(4LL * m + a2);\n *(uint32_t *)(4LL * m + a2) = *(uint32_t *)(4 * (m + 1LL) + a2);\n *(uint32_t *)(a2 + 4 * (m + 1LL)) = v10;\n }\n }\n }\n for (n = 0; n < a3; ++n) {\n if (*(uint32_t *)(4LL * n + a1) != *(uint32_t *)(4LL * n + a2)) return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3, int a4) {\n int i;\n int j;\n int k;\n int m;\n int n;\n int v10;\n int v11;\n if (a3 != a4) return 0LL;\n for (i = 0; i < a3 - 1; ++i) {\n for (j = 0; j < a3 - i - 1; ++j) {\n if (*(uint32_t *)(4LL * j + a1) > *(uint32_t *)(4 * (j + 1LL) + a1)) {\n v11 = *(uint32_t *)(4LL * j + a1);\n *(uint32_t *)(4LL * j + a1) = *(uint32_t *)(4 * (j + 1LL) + a1);\n *(uint32_t *)(a1 + 4 * (j + 1LL)) = v11;\n }\n }\n }\n for (k = 0; k < a3 - 1; ++k) {\n for (m = 0; m < a3 - k - 1; ++m) {\n if (*(uint32_t *)(4LL * m + a2) > *(uint32_t *)(4 * (m + 1LL) + a2)) {\n v10 = *(uint32_t *)(4LL * m + a2);\n *(uint32_t *)(4LL * m + a2) = *(uint32_t *)(4 * (m + 1LL) + a2);\n *(uint32_t *)(a2 + 4 * (m + 1LL)) = v10;\n }\n }\n }\n for (n = 0; n < a3; ++n) {\n if (*(uint32_t *)(4LL * n + a1) != *(uint32_t *)(4LL * n + a2)) return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": 650, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int arr1[], int arr2[], int n, int m) {\n if (n != m) {\n return false;\n }\n for (int i = 0; i < n - 1; i++) {\n for (int j = 0; j < n - i - 1; j++) {\n if (arr1[j] > arr1[j + 1]) {\n int temp = arr1[j];\n arr1[j] = arr1[j + 1];\n arr1[j + 1] = temp;\n }\n }\n }\n for (int i = 0; i < n - 1; i++) {\n for (int j = 0; j < n - i - 1; j++) {\n if (arr2[j] > arr2[j + 1]) {\n int temp = arr2[j];\n arr2[j] = arr2[j + 1];\n arr2[j + 1] = temp;\n }\n }\n }\n for (int i = 0; i < n; i++) {\n if (arr1[i] != arr2[i]) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3};\n\n int arr2[] = {3, 2, 1};\n\n int arr3[] = {1, 1, 1};\n\n int arr4[] = {2, 2, 2};\n\n int arr5[] = {8, 9};\n\n int arr6[] = {4, 5, 6};\n\n\n\n assert(func0(arr1, arr2, 3, 3) == true);\n\n assert(func0(arr3, arr4, 3, 3) == false);\n\n assert(func0(arr5, arr6, 2, 3) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x0,%eax\ncmp %ecx,%edx\njne 1235 \npush %rbx\nlea -0x1(%rdx),%eax\nmov %eax,%r10d\nmov %eax,%r11d\nlea 0x4(%rdi),%rbx\ntest %eax,%eax\njg 11c0 \ntest %edx,%edx\njle 1227 \nlea -0x1(%rdx),%ecx\nmov $0x0,%eax\njmp 120f \nadd $0x4,%rax\ncmp %r9,%rax\nje 11ba \nmov (%rax),%ecx\nmov 0x4(%rax),%r8d\ncmp %r8d,%ecx\njle 119e \nmov %r8d,(%rax)\nmov %ecx,0x4(%rax)\njmp 119e \nsub $0x1,%r11d\nje 11d2 \ntest %r11d,%r11d\njle 11ba \nmov %rdi,%rax\nlea -0x1(%r11),%ecx\nlea (%rbx,%rcx,4),%r9\njmp 11a7 \nlea 0x4(%rsi),%r11\njmp 11fa \nadd $0x4,%rax\ncmp %r9,%rax\nje 11f4 \nmov (%rax),%ecx\nmov 0x4(%rax),%r8d\ncmp %r8d,%ecx\njle 11d8 \nmov %r8d,(%rax)\nmov %ecx,0x4(%rax)\njmp 11d8 \nsub $0x1,%r10d\nje 118c \ntest %r10d,%r10d\njle 11f4 \nmov %rsi,%rax\nlea -0x1(%r10),%ecx\nlea (%r11,%rcx,4),%r9\njmp 11e1 \nmov %rdx,%rax\nmov (%rsi,%rax,4),%ebx\ncmp %ebx,(%rdi,%rax,4)\njne 122e \nlea 0x1(%rax),%rdx\ncmp %rax,%rcx\njne 120c \nmov $0x1,%eax\njmp 1233 \nmov $0x1,%eax\njmp 1233 \nmov $0x0,%eax\npop %rbx\nretq\nretq\n", + "ida_asm": "func0:\nendbr64\nmov eax, 0\ncmp edx, ecx\njnz locret_124A\npush rbx\nmov r9, rdi\nmov r10, rsi\nmov r11d, edx\ncmp edx, 1\njle short loc_1206\nmov edi, edx\nmov r8d, edx\nlea rbx, [r9+4]\njmp short loc_11B7\nloc_1194:\nadd rax, 4\ncmp rax, rsi\njz short loc_11AD\nloc_119D:\nmov edx, [rax]\nmov ecx, [rax+4]\ncmp edx, ecx\njle short loc_1194\nmov [rax], ecx\nmov [rax+4], edx\njmp short loc_1194\nloc_11AD:\nsub r8d, 1\ncmp r8d, 1\njz short loc_11CE\nloc_11B7:\ncmp r8d, 1\njle loc_1241\nmov rax, r9\nlea edx, [r8-2]\nlea rsi, [rbx+rdx*4]\njmp short loc_119D\nloc_11CE:\nlea r8, [r10+4]\njmp short loc_11F5\nloc_11D4:\nadd rax, 4\ncmp rsi, rax\njz short loc_11ED\nloc_11DD:\nmov edx, [rax]\nmov ecx, [rax+4]\ncmp edx, ecx\njle short loc_11D4\nmov [rax], ecx\nmov [rax+4], edx\njmp short loc_11D4\nloc_11ED:\nsub edi, 1\ncmp edi, 1\njz short loc_120F\nloc_11F5:\ncmp edi, 1\njle short loc_123C\nmov rax, r10\nlea edx, [rdi-2]\nlea rsi, [r8+rdx*4]\njmp short loc_11DD\nloc_1206:\nmov eax, 1\ntest edx, edx\njle short loc_123A\nloc_120F:\nmovsxd rdx, r11d\nshl rdx, 2\nmov eax, 0\nloc_121B:\nmov ebx, [r10+rax]\ncmp [r9+rax], ebx\njnz short loc_1235\nadd rax, 4\ncmp rax, rdx\njnz short loc_121B\nmov eax, 1\njmp short loc_123A\nloc_1235:\nmov eax, 0\nloc_123A:\npop rbx\nretn\nloc_123C:\nsub edi, 1\njmp short loc_11F5\nloc_1241:\nsub r8d, 1\njmp loc_11B7\nlocret_124A:\nretn", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int *a2, int a3, int a4)\n{\n __int64 result; // rax\n int v7; // edi\n int i; // r8d\n int *v9; // rax\n int v10; // edx\n int v11; // ecx\n int *v12; // rax\n int v13; // edx\n int v14; // ecx\n __int64 v15; // rax\n\n result = 0LL;\n if ( a3 == a4 )\n {\n if ( a3 <= 1 )\n {\n result = 1LL;\n if ( a3 <= 0 )\n return result;\n }\n else\n {\n v7 = a3;\n for ( i = a3; i != 1; --i )\n {\n while ( i <= 1 )\n --i;\n v9 = a1;\n do\n {\n v10 = *v9;\n v11 = v9[1];\n if ( *v9 > v11 )\n {\n *v9 = v11;\n v9[1] = v10;\n }\n ++v9;\n }\n while ( v9 != &a1[i - 2 + 1] );\n }\n do\n {\n while ( v7 <= 1 )\n --v7;\n v12 = a2;\n do\n {\n v13 = *v12;\n v14 = v12[1];\n if ( *v12 > v14 )\n {\n *v12 = v14;\n v12[1] = v13;\n }\n ++v12;\n }\n while ( &a2[v7 - 2 + 1] != v12 );\n --v7;\n }\n while ( v7 != 1 );\n }\n v15 = 0LL;\n while ( a1[v15] == a2[v15] )\n {\n if ( ++v15 == a3 )\n return 1LL;\n }\n return 0LL;\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov eax, 0\ncmp edx, ecx\njnz locret_124A\npush rbx\nmov r9, rdi\nmov r10, rsi\nmov r11d, edx\ncmp edx, 1\njle short loc_1206\nmov edi, edx\nmov r8d, edx\nlea rbx, [r9+4]\njmp short loc_11B7\nloc_1194:\nadd rax, 4\ncmp rax, rsi\njz short loc_11AD\nloc_119D:\nmov edx, [rax]\nmov ecx, [rax+4]\ncmp edx, ecx\njle short loc_1194\nmov [rax], ecx\nmov [rax+4], edx\njmp short loc_1194\nloc_11AD:\nsub r8d, 1\ncmp r8d, 1\njz short loc_11CE\nloc_11B7:\ncmp r8d, 1\njle loc_1241\nmov rax, r9\nlea edx, [r8-2]\nlea rsi, [rbx+rdx*4]\njmp short loc_119D\nloc_11CE:\nlea r8, [r10+4]\njmp short loc_11F5\nloc_11D4:\nadd rax, 4\ncmp rsi, rax\njz short loc_11ED\nloc_11DD:\nmov edx, [rax]\nmov ecx, [rax+4]\ncmp edx, ecx\njle short loc_11D4\nmov [rax], ecx\nmov [rax+4], edx\njmp short loc_11D4\nloc_11ED:\nsub edi, 1\ncmp edi, 1\njz short loc_120F\nloc_11F5:\ncmp edi, 1\njle short loc_123C\nmov rax, r10\nlea edx, [rdi-2]\nlea rsi, [r8+rdx*4]\njmp short loc_11DD\nloc_1206:\nmov eax, 1\ntest edx, edx\njle short loc_123A\nloc_120F:\nmovsxd rdx, r11d\nshl rdx, 2\nmov eax, 0\nloc_121B:\nmov ebx, [r10+rax]\ncmp [r9+rax], ebx\njnz short loc_1235\nadd rax, 4\ncmp rax, rdx\njnz short loc_121B\nmov eax, 1\njmp short loc_123A\nloc_1235:\nmov eax, 0\nloc_123A:\npop rbx\nretn\nloc_123C:\nsub edi, 1\njmp short loc_11F5\nloc_1241:\nsub r8d, 1\njmp loc_11B7\nlocret_124A:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int *a1, int *a2, int a3, int a4)\n{\n __int64 result; // rax\n int v7; // edi\n int i; // r8d\n int *v9; // rax\n int v10; // edx\n int v11; // ecx\n int *v12; // rax\n int v13; // edx\n int v14; // ecx\n __int64 v15; // rax\n\n result = 0LL;\n if ( a3 == a4 )\n {\n if ( a3 <= 1 )\n {\n result = 1LL;\n if ( a3 <= 0 )\n return result;\n }\n else\n {\n v7 = a3;\n for ( i = a3; i != 1; --i )\n {\n while ( i <= 1 )\n --i;\n v9 = a1;\n do\n {\n v10 = *v9;\n v11 = v9[1];\n if ( *v9 > v11 )\n {\n *v9 = v11;\n v9[1] = v10;\n }\n ++v9;\n }\n while ( v9 != &a1[i - 2 + 1] );\n }\n do\n {\n while ( v7 <= 1 )\n --v7;\n v12 = a2;\n do\n {\n v13 = *v12;\n v14 = v12[1];\n if ( *v12 > v14 )\n {\n *v12 = v14;\n v12[1] = v13;\n }\n ++v12;\n }\n while ( &a2[v7 - 2 + 1] != v12 );\n --v7;\n }\n while ( v7 != 1 );\n }\n v15 = 0LL;\n while ( a1[v15] == a2[v15] )\n {\n if ( ++v15 == a3 )\n return 1LL;\n }\n return 0LL;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int *a1, int *a2, int a3, int a4) {\n long long result;\n int v7;\n int i;\n int *v9;\n int v10;\n int v11;\n int *v12;\n int v13;\n int v14;\n long long v15;\n result = 0LL;\n if (a3 == a4) {\n if (a3 <= 1) {\n result = 1LL;\n if (a3 <= 0) return result;\n } else {\n v7 = a3;\n for (i = a3; i != 1; --i) {\n while (i <= 1) --i;\n v9 = a1;\n do {\n v10 = *v9;\n v11 = v9[1];\n if (*v9 > v11) {\n *v9 = v11;\n v9[1] = v10;\n }\n ++v9;\n } while (v9 != &a1[i - 2 + 1]);\n }\n do {\n while (v7 <= 1) --v7;\n v12 = a2;\n do {\n v13 = *v12;\n v14 = v12[1];\n if (*v12 > v14) {\n *v12 = v14;\n v12[1] = v13;\n }\n ++v12;\n } while (&a2[v7 - 2 + 1] != v12);\n --v7;\n } while (v7 != 1);\n }\n v15 = 0LL;\n while (a1[v15] == a2[v15]) {\n if (++v15 == a3) return 1LL;\n }\n return 0LL;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int *a2, int a3, int a4) {\n long long result;\n int v7;\n int i;\n int *v9;\n int v10;\n int v11;\n int *v12;\n int v13;\n int v14;\n long long v15;\n result = 0LL;\n if (a3 == a4) {\n if (a3 <= 1) {\n result = 1LL;\n if (a3 <= 0) return result;\n } else {\n v7 = a3;\n for (i = a3; i != 1; --i) {\n while (i <= 1) --i;\n v9 = a1;\n do {\n v10 = *v9;\n v11 = v9[1];\n if (*v9 > v11) {\n *v9 = v11;\n v9[1] = v10;\n }\n ++v9;\n } while (v9 != &a1[i - 2 + 1]);\n }\n do {\n while (v7 <= 1) --v7;\n v12 = a2;\n do {\n v13 = *v12;\n v14 = v12[1];\n if (*v12 > v14) {\n *v12 = v14;\n v12[1] = v13;\n }\n ++v12;\n } while (&a2[v7 - 2 + 1] != v12);\n --v7;\n } while (v7 != 1);\n }\n v15 = 0LL;\n while (a1[v15] == a2[v15]) {\n if (++v15 == a3) return 1LL;\n }\n return 0LL;\n }\n return result;\n}" + }, + { + "index": 650, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int arr1[], int arr2[], int n, int m) {\n if (n != m) {\n return false;\n }\n for (int i = 0; i < n - 1; i++) {\n for (int j = 0; j < n - i - 1; j++) {\n if (arr1[j] > arr1[j + 1]) {\n int temp = arr1[j];\n arr1[j] = arr1[j + 1];\n arr1[j + 1] = temp;\n }\n }\n }\n for (int i = 0; i < n - 1; i++) {\n for (int j = 0; j < n - i - 1; j++) {\n if (arr2[j] > arr2[j + 1]) {\n int temp = arr2[j];\n arr2[j] = arr2[j + 1];\n arr2[j + 1] = temp;\n }\n }\n }\n for (int i = 0; i < n; i++) {\n if (arr1[i] != arr2[i]) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3};\n\n int arr2[] = {3, 2, 1};\n\n int arr3[] = {1, 1, 1};\n\n int arr4[] = {2, 2, 2};\n\n int arr5[] = {8, 9};\n\n int arr6[] = {4, 5, 6};\n\n\n\n assert(func0(arr1, arr2, 3, 3) == true);\n\n assert(func0(arr3, arr4, 3, 3) == false);\n\n assert(func0(arr5, arr6, 2, 3) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ncmp %ecx,%edx\njne 1370 \njmpq 1270 \nnopl (%rax)\nxor %eax,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\ncmp edx, ecx\njz short loc_12E0\nxor eax, eax\nretn\nloc_12E0:\npush rbx\nmov r8, rsi\nmov r10d, edx\nmov r9d, edx\nmov r11d, edx\nlea rbx, [rdi+4]\ncmp edx, 1\njle loc_13D6\nnop word ptr [rax+rax+00h]\nloc_1300:\nlea edx, [r11-2]\nmov rax, rdi\nlea rsi, [rbx+rdx*4]\nnop dword ptr [rax+rax+00h]\nloc_1310:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd edx, xmm0\nmovd ecx, xmm1\ncmp ecx, edx\njge short loc_132E\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_132E:\nadd rax, 4\ncmp rax, rsi\njnz short loc_1310\nsub r11d, 1\ncmp r11d, 1\njz short loc_1350\nloc_1341:\ncmp r11d, 1\njg short loc_1300\nsub r11d, 1\njmp short loc_1341\nloc_1350:\nlea r11, [r8+4]\nnop dword ptr [rax+00h]\nloc_1358:\ncmp r9d, 1\njle short loc_13D0\nlea edx, [r9-2]\nmov rax, r8\nlea rsi, [r11+rdx*4]\nnop dword ptr [rax+00000000h]\nloc_1370:\nmovq xmm0, qword ptr [rax]\npshufd xmm2, xmm0, 0E5h\nmovd edx, xmm0\nmovd ecx, xmm2\ncmp ecx, edx\njge short loc_138E\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_138E:\nadd rax, 4\ncmp rax, rsi\njnz short loc_1370\nsub r9d, 1\ncmp r9d, 1\njnz short loc_1358\nloc_13A1:\nmovsxd rdx, r10d\nxor eax, eax\nshl rdx, 2\njmp short loc_13B9\nloc_13B0:\nadd rax, 4\ncmp rax, rdx\njz short loc_13D8\nloc_13B9:\nmov ebx, [r8+rax]\ncmp [rdi+rax], ebx\njz short loc_13B0\nxor eax, eax\npop rbx\nretn\nloc_13D0:\nsub r9d, 1\njmp short loc_1358\nloc_13D6:\njz short loc_13A1\nloc_13D8:\nmov eax, 1\npop rbx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__m128i *a1, __m128i *a2, int a3, int a4)\n{\n int v5; // r9d\n int v6; // r11d\n __m128i *v7; // rax\n __m128i v8; // xmm0\n __m128i *v9; // rax\n __m128i v10; // xmm0\n unsigned __int64 v11; // rax\n __int64 v12; // rdx\n\n if ( a3 != a4 )\n return 0LL;\n v5 = a3;\n v6 = a3;\n if ( a3 <= 1 )\n {\n if ( a3 != 1 )\n return 1LL;\n }\n else\n {\n while ( 1 )\n {\n v7 = a1;\n do\n {\n v8 = _mm_loadl_epi64(v7);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v8, 229)) < _mm_cvtsi128_si32(v8) )\n v7->m128i_i64[0] = _mm_shuffle_epi32(v8, 225).m128i_u64[0];\n v7 = (__m128i *)((char *)v7 + 4);\n }\n while ( v7 != (__m128i *)((char *)a1->m128i_i64 + 4 * (unsigned int)(v6 - 2) + 4) );\n if ( --v6 == 1 )\n break;\n while ( v6 <= 1 )\n --v6;\n }\n do\n {\n while ( v5 <= 1 )\n --v5;\n v9 = a2;\n do\n {\n v10 = _mm_loadl_epi64(v9);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v10, 229)) < _mm_cvtsi128_si32(v10) )\n v9->m128i_i64[0] = _mm_shuffle_epi32(v10, 225).m128i_u64[0];\n v9 = (__m128i *)((char *)v9 + 4);\n }\n while ( v9 != (__m128i *)((char *)a2->m128i_i64 + 4 * (unsigned int)(v5 - 2) + 4) );\n --v5;\n }\n while ( v5 != 1 );\n }\n v11 = 0LL;\n v12 = 4LL * a3;\n while ( a1->m128i_i32[v11 / 4] == a2->m128i_i32[v11 / 4] )\n {\n v11 += 4LL;\n if ( v11 == v12 )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_12D0:\nendbr64\ncmp edx, ecx\njz short loc_12E0\nxor eax, eax\nretn\nloc_12E0:\npush rbx\nmov r8, rsi\nmov r10d, edx\nmov r9d, edx\nmov r11d, edx\nlea rbx, [rdi+4]\ncmp edx, 1\njle loc_13D6\nnop word ptr [rax+rax+00h]\nloc_1300:\nlea edx, [r11-2]\nmov rax, rdi\nlea rsi, [rbx+rdx*4]\nnop dword ptr [rax+rax+00h]\nloc_1310:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd edx, xmm0\nmovd ecx, xmm1\ncmp ecx, edx\njge short loc_132E\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_132E:\nadd rax, 4\ncmp rax, rsi\njnz short loc_1310\nsub r11d, 1\ncmp r11d, 1\njz short loc_1350\nloc_1341:\ncmp r11d, 1\njg short loc_1300\nsub r11d, 1\njmp short loc_1341\nloc_1350:\nlea r11, [r8+4]\nnop dword ptr [rax+00h]\nloc_1358:\ncmp r9d, 1\njle short loc_13D0\nlea edx, [r9-2]\nmov rax, r8\nlea rsi, [r11+rdx*4]\nnop dword ptr [rax+00000000h]\nloc_1370:\nmovq xmm0, qword ptr [rax]\npshufd xmm2, xmm0, 0E5h\nmovd edx, xmm0\nmovd ecx, xmm2\ncmp ecx, edx\njge short loc_138E\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_138E:\nadd rax, 4\ncmp rax, rsi\njnz short loc_1370\nsub r9d, 1\ncmp r9d, 1\njnz short loc_1358\nloc_13A1:\nmovsxd rdx, r10d\nxor eax, eax\nshl rdx, 2\njmp short loc_13B9\nloc_13B0:\nadd rax, 4\ncmp rax, rdx\njz short loc_13D8\nloc_13B9:\nmov ebx, [r8+rax]\ncmp [rdi+rax], ebx\njz short loc_13B0\nxor eax, eax\npop rbx\nretn\nloc_13D0:\nsub r9d, 1\njmp short loc_1358\nloc_13D6:\njz short loc_13A1\nloc_13D8:\nmov eax, 1\npop rbx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12D0(__m128i *a1, __m128i *a2, int a3, int a4)\n{\n int v5; // r9d\n int v6; // r11d\n __m128i *v7; // rax\n __m128i v8; // xmm0\n __m128i *v9; // rax\n __m128i v10; // xmm0\n unsigned __int64 v11; // rax\n __int64 v12; // rdx\n\n if ( a3 != a4 )\n return 0LL;\n v5 = a3;\n v6 = a3;\n if ( a3 <= 1 )\n {\n if ( a3 != 1 )\n return 1LL;\n }\n else\n {\n while ( 1 )\n {\n v7 = a1;\n do\n {\n v8 = _mm_loadl_epi64(v7);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v8, 229)) < _mm_cvtsi128_si32(v8) )\n v7->m128i_i64[0] = _mm_shuffle_epi32(v8, 225).m128i_u64[0];\n v7 = (__m128i *)((char *)v7 + 4);\n }\n while ( v7 != (__m128i *)((char *)a1->m128i_i64 + 4 * (unsigned int)(v6 - 2) + 4) );\n if ( --v6 == 1 )\n break;\n while ( v6 <= 1 )\n --v6;\n }\n do\n {\n while ( v5 <= 1 )\n --v5;\n v9 = a2;\n do\n {\n v10 = _mm_loadl_epi64(v9);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v10, 229)) < _mm_cvtsi128_si32(v10) )\n v9->m128i_i64[0] = _mm_shuffle_epi32(v10, 225).m128i_u64[0];\n v9 = (__m128i *)((char *)v9 + 4);\n }\n while ( v9 != (__m128i *)((char *)a2->m128i_i64 + 4 * (unsigned int)(v5 - 2) + 4) );\n --v5;\n }\n while ( v5 != 1 );\n }\n v11 = 0LL;\n v12 = 4LL * a3;\n while ( a1->m128i_i32[v11 / 4] == a2->m128i_i32[v11 / 4] )\n {\n v11 += 4LL;\n if ( v11 == v12 )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12D0(__m128i *a1, __m128i *a2, int a3, int a4) {\n int v5;\n int v6;\n __m128i *v7;\n __m128i v8;\n __m128i *v9;\n __m128i v10;\n unsigned long long v11;\n long long v12;\n if (a3 != a4) return 0LL;\n v5 = a3;\n v6 = a3;\n if (a3 <= 1) {\n if (a3 != 1) return 1LL;\n } else {\n while (1) {\n v7 = a1;\n do {\n v8 = _mm_loadl_epi64(v7);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v8, 229)) <\n _mm_cvtsi128_si32(v8))\n v7->m128i_i64[0] = _mm_shuffle_epi32(v8, 225).m128i_u64[0];\n v7 = (__m128i *)((char *)v7 + 4);\n } while (v7 != (__m128i *)((char *)a1->m128i_i64 +\n 4 * (unsigned int)(v6 - 2) + 4));\n if (--v6 == 1) break;\n while (v6 <= 1) --v6;\n }\n do {\n while (v5 <= 1) --v5;\n v9 = a2;\n do {\n v10 = _mm_loadl_epi64(v9);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v10, 229)) <\n _mm_cvtsi128_si32(v10))\n v9->m128i_i64[0] = _mm_shuffle_epi32(v10, 225).m128i_u64[0];\n v9 = (__m128i *)((char *)v9 + 4);\n } while (v9 != (__m128i *)((char *)a2->m128i_i64 +\n 4 * (unsigned int)(v5 - 2) + 4));\n --v5;\n } while (v5 != 1);\n }\n v11 = 0LL;\n v12 = 4LL * a3;\n while (a1->m128i_i32[v11 / 4] == a2->m128i_i32[v11 / 4]) {\n v11 += 4LL;\n if (v11 == v12) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(__m128i *a1, __m128i *a2, int a3, int a4) {\n int v5;\n int v6;\n __m128i *v7;\n __m128i v8;\n __m128i *v9;\n __m128i v10;\n unsigned long long v11;\n long long v12;\n if (a3 != a4) return 0LL;\n v5 = a3;\n v6 = a3;\n if (a3 <= 1) {\n if (a3 != 1) return 1LL;\n } else {\n while (1) {\n v7 = a1;\n do {\n v8 = _mm_loadl_epi64(v7);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v8, 229)) <\n _mm_cvtsi128_si32(v8))\n v7->m128i_i64[0] = _mm_shuffle_epi32(v8, 225).m128i_u64[0];\n v7 = (__m128i *)((char *)v7 + 4);\n } while (v7 != (__m128i *)((char *)a1->m128i_i64 +\n 4 * (unsigned int)(v6 - 2) + 4));\n if (--v6 == 1) break;\n while (v6 <= 1) --v6;\n }\n do {\n while (v5 <= 1) --v5;\n v9 = a2;\n do {\n v10 = _mm_loadl_epi64(v9);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v10, 229)) <\n _mm_cvtsi128_si32(v10))\n v9->m128i_i64[0] = _mm_shuffle_epi32(v10, 225).m128i_u64[0];\n v9 = (__m128i *)((char *)v9 + 4);\n } while (v9 != (__m128i *)((char *)a2->m128i_i64 +\n 4 * (unsigned int)(v5 - 2) + 4));\n --v5;\n } while (v5 != 1);\n }\n v11 = 0LL;\n v12 = 4LL * a3;\n while (a1->m128i_i32[v11 / 4] == a2->m128i_i32[v11 / 4]) {\n v11 += 4LL;\n if (v11 == v12) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 650, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int arr1[], int arr2[], int n, int m) {\n if (n != m) {\n return false;\n }\n for (int i = 0; i < n - 1; i++) {\n for (int j = 0; j < n - i - 1; j++) {\n if (arr1[j] > arr1[j + 1]) {\n int temp = arr1[j];\n arr1[j] = arr1[j + 1];\n arr1[j + 1] = temp;\n }\n }\n }\n for (int i = 0; i < n - 1; i++) {\n for (int j = 0; j < n - i - 1; j++) {\n if (arr2[j] > arr2[j + 1]) {\n int temp = arr2[j];\n arr2[j] = arr2[j + 1];\n arr2[j + 1] = temp;\n }\n }\n }\n for (int i = 0; i < n; i++) {\n if (arr1[i] != arr2[i]) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3};\n\n int arr2[] = {3, 2, 1};\n\n int arr3[] = {1, 1, 1};\n\n int arr4[] = {2, 2, 2};\n\n int arr5[] = {8, 9};\n\n int arr6[] = {4, 5, 6};\n\n\n\n assert(func0(arr1, arr2, 3, 3) == true);\n\n assert(func0(arr3, arr4, 3, 3) == false);\n\n assert(func0(arr5, arr6, 2, 3) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ncmp %ecx,%edx\njne 1370 \njmpq 1270 \nnopl (%rax)\nxor %eax,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\ncmp edx, ecx\njz short loc_12E0\nxor eax, eax\nretn\nloc_12E0:\npush rbx\nmov r8, rsi\nmov r10d, edx\nmov r9d, edx\nmov r11d, edx\nlea rbx, [rdi+4]\ncmp edx, 1\njle loc_13D6\nnop word ptr [rax+rax+00h]\nloc_1300:\nlea edx, [r11-2]\nmov rax, rdi\nlea rsi, [rbx+rdx*4]\nnop dword ptr [rax+rax+00h]\nloc_1310:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd edx, xmm0\nmovd ecx, xmm1\ncmp ecx, edx\njge short loc_132E\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_132E:\nadd rax, 4\ncmp rax, rsi\njnz short loc_1310\nsub r11d, 1\ncmp r11d, 1\njz short loc_1350\nloc_1341:\ncmp r11d, 1\njg short loc_1300\nsub r11d, 1\njmp short loc_1341\nloc_1350:\nlea r11, [r8+4]\nnop dword ptr [rax+00h]\nloc_1358:\ncmp r9d, 1\njle short loc_13D0\nlea edx, [r9-2]\nmov rax, r8\nlea rsi, [r11+rdx*4]\nnop dword ptr [rax+00000000h]\nloc_1370:\nmovq xmm0, qword ptr [rax]\npshufd xmm2, xmm0, 0E5h\nmovd edx, xmm0\nmovd ecx, xmm2\ncmp ecx, edx\njge short loc_138E\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_138E:\nadd rax, 4\ncmp rax, rsi\njnz short loc_1370\nsub r9d, 1\ncmp r9d, 1\njnz short loc_1358\nloc_13A1:\nmovsxd rdx, r10d\nxor eax, eax\nshl rdx, 2\njmp short loc_13B9\nloc_13B0:\nadd rax, 4\ncmp rax, rdx\njz short loc_13D8\nloc_13B9:\nmov ebx, [r8+rax]\ncmp [rdi+rax], ebx\njz short loc_13B0\nxor eax, eax\npop rbx\nretn\nloc_13D0:\nsub r9d, 1\njmp short loc_1358\nloc_13D6:\njz short loc_13A1\nloc_13D8:\nmov eax, 1\npop rbx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__m128i *a1, __m128i *a2, int a3, int a4)\n{\n int v5; // r9d\n int v6; // r11d\n __m128i *v7; // rax\n __m128i v8; // xmm0\n __m128i *v9; // rax\n __m128i v10; // xmm0\n unsigned __int64 v11; // rax\n __int64 v12; // rdx\n\n if ( a3 != a4 )\n return 0LL;\n v5 = a3;\n v6 = a3;\n if ( a3 <= 1 )\n {\n if ( a3 != 1 )\n return 1LL;\n }\n else\n {\n while ( 1 )\n {\n v7 = a1;\n do\n {\n v8 = _mm_loadl_epi64(v7);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v8, 229)) < _mm_cvtsi128_si32(v8) )\n v7->m128i_i64[0] = _mm_shuffle_epi32(v8, 225).m128i_u64[0];\n v7 = (__m128i *)((char *)v7 + 4);\n }\n while ( v7 != (__m128i *)((char *)a1->m128i_i64 + 4 * (unsigned int)(v6 - 2) + 4) );\n if ( --v6 == 1 )\n break;\n while ( v6 <= 1 )\n --v6;\n }\n do\n {\n while ( v5 <= 1 )\n --v5;\n v9 = a2;\n do\n {\n v10 = _mm_loadl_epi64(v9);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v10, 229)) < _mm_cvtsi128_si32(v10) )\n v9->m128i_i64[0] = _mm_shuffle_epi32(v10, 225).m128i_u64[0];\n v9 = (__m128i *)((char *)v9 + 4);\n }\n while ( v9 != (__m128i *)((char *)a2->m128i_i64 + 4 * (unsigned int)(v5 - 2) + 4) );\n --v5;\n }\n while ( v5 != 1 );\n }\n v11 = 0LL;\n v12 = 4LL * a3;\n while ( a1->m128i_i32[v11 / 4] == a2->m128i_i32[v11 / 4] )\n {\n v11 += 4LL;\n if ( v11 == v12 )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_12D0:\nendbr64\ncmp edx, ecx\njz short loc_12E0\nxor eax, eax\nretn\nloc_12E0:\npush rbx\nmov r8, rsi\nmov r10d, edx\nmov r9d, edx\nmov r11d, edx\nlea rbx, [rdi+4]\ncmp edx, 1\njle loc_13D6\nnop word ptr [rax+rax+00h]\nloc_1300:\nlea edx, [r11-2]\nmov rax, rdi\nlea rsi, [rbx+rdx*4]\nnop dword ptr [rax+rax+00h]\nloc_1310:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd edx, xmm0\nmovd ecx, xmm1\ncmp ecx, edx\njge short loc_132E\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_132E:\nadd rax, 4\ncmp rax, rsi\njnz short loc_1310\nsub r11d, 1\ncmp r11d, 1\njz short loc_1350\nloc_1341:\ncmp r11d, 1\njg short loc_1300\nsub r11d, 1\njmp short loc_1341\nloc_1350:\nlea r11, [r8+4]\nnop dword ptr [rax+00h]\nloc_1358:\ncmp r9d, 1\njle short loc_13D0\nlea edx, [r9-2]\nmov rax, r8\nlea rsi, [r11+rdx*4]\nnop dword ptr [rax+00000000h]\nloc_1370:\nmovq xmm0, qword ptr [rax]\npshufd xmm2, xmm0, 0E5h\nmovd edx, xmm0\nmovd ecx, xmm2\ncmp ecx, edx\njge short loc_138E\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_138E:\nadd rax, 4\ncmp rax, rsi\njnz short loc_1370\nsub r9d, 1\ncmp r9d, 1\njnz short loc_1358\nloc_13A1:\nmovsxd rdx, r10d\nxor eax, eax\nshl rdx, 2\njmp short loc_13B9\nloc_13B0:\nadd rax, 4\ncmp rax, rdx\njz short loc_13D8\nloc_13B9:\nmov ebx, [r8+rax]\ncmp [rdi+rax], ebx\njz short loc_13B0\nxor eax, eax\npop rbx\nretn\nloc_13D0:\nsub r9d, 1\njmp short loc_1358\nloc_13D6:\njz short loc_13A1\nloc_13D8:\nmov eax, 1\npop rbx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12D0(__m128i *a1, __m128i *a2, int a3, int a4)\n{\n int v5; // r9d\n int v6; // r11d\n __m128i *v7; // rax\n __m128i v8; // xmm0\n __m128i *v9; // rax\n __m128i v10; // xmm0\n unsigned __int64 v11; // rax\n __int64 v12; // rdx\n\n if ( a3 != a4 )\n return 0LL;\n v5 = a3;\n v6 = a3;\n if ( a3 <= 1 )\n {\n if ( a3 != 1 )\n return 1LL;\n }\n else\n {\n while ( 1 )\n {\n v7 = a1;\n do\n {\n v8 = _mm_loadl_epi64(v7);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v8, 229)) < _mm_cvtsi128_si32(v8) )\n v7->m128i_i64[0] = _mm_shuffle_epi32(v8, 225).m128i_u64[0];\n v7 = (__m128i *)((char *)v7 + 4);\n }\n while ( v7 != (__m128i *)((char *)a1->m128i_i64 + 4 * (unsigned int)(v6 - 2) + 4) );\n if ( --v6 == 1 )\n break;\n while ( v6 <= 1 )\n --v6;\n }\n do\n {\n while ( v5 <= 1 )\n --v5;\n v9 = a2;\n do\n {\n v10 = _mm_loadl_epi64(v9);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v10, 229)) < _mm_cvtsi128_si32(v10) )\n v9->m128i_i64[0] = _mm_shuffle_epi32(v10, 225).m128i_u64[0];\n v9 = (__m128i *)((char *)v9 + 4);\n }\n while ( v9 != (__m128i *)((char *)a2->m128i_i64 + 4 * (unsigned int)(v5 - 2) + 4) );\n --v5;\n }\n while ( v5 != 1 );\n }\n v11 = 0LL;\n v12 = 4LL * a3;\n while ( a1->m128i_i32[v11 / 4] == a2->m128i_i32[v11 / 4] )\n {\n v11 += 4LL;\n if ( v11 == v12 )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12D0(__m128i *a1, __m128i *a2, int a3, int a4) {\n int v5;\n int v6;\n __m128i *v7;\n __m128i v8;\n __m128i *v9;\n __m128i v10;\n unsigned long long v11;\n long long v12;\n if (a3 != a4) return 0LL;\n v5 = a3;\n v6 = a3;\n if (a3 <= 1) {\n if (a3 != 1) return 1LL;\n } else {\n while (1) {\n v7 = a1;\n do {\n v8 = _mm_loadl_epi64(v7);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v8, 229)) <\n _mm_cvtsi128_si32(v8))\n v7->m128i_i64[0] = _mm_shuffle_epi32(v8, 225).m128i_u64[0];\n v7 = (__m128i *)((char *)v7 + 4);\n } while (v7 != (__m128i *)((char *)a1->m128i_i64 +\n 4 * (unsigned int)(v6 - 2) + 4));\n if (--v6 == 1) break;\n while (v6 <= 1) --v6;\n }\n do {\n while (v5 <= 1) --v5;\n v9 = a2;\n do {\n v10 = _mm_loadl_epi64(v9);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v10, 229)) <\n _mm_cvtsi128_si32(v10))\n v9->m128i_i64[0] = _mm_shuffle_epi32(v10, 225).m128i_u64[0];\n v9 = (__m128i *)((char *)v9 + 4);\n } while (v9 != (__m128i *)((char *)a2->m128i_i64 +\n 4 * (unsigned int)(v5 - 2) + 4));\n --v5;\n } while (v5 != 1);\n }\n v11 = 0LL;\n v12 = 4LL * a3;\n while (a1->m128i_i32[v11 / 4] == a2->m128i_i32[v11 / 4]) {\n v11 += 4LL;\n if (v11 == v12) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(__m128i *a1, __m128i *a2, int a3, int a4) {\n int v5;\n int v6;\n __m128i *v7;\n __m128i v8;\n __m128i *v9;\n __m128i v10;\n unsigned long long v11;\n long long v12;\n if (a3 != a4) return 0LL;\n v5 = a3;\n v6 = a3;\n if (a3 <= 1) {\n if (a3 != 1) return 1LL;\n } else {\n while (1) {\n v7 = a1;\n do {\n v8 = _mm_loadl_epi64(v7);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v8, 229)) <\n _mm_cvtsi128_si32(v8))\n v7->m128i_i64[0] = _mm_shuffle_epi32(v8, 225).m128i_u64[0];\n v7 = (__m128i *)((char *)v7 + 4);\n } while (v7 != (__m128i *)((char *)a1->m128i_i64 +\n 4 * (unsigned int)(v6 - 2) + 4));\n if (--v6 == 1) break;\n while (v6 <= 1) --v6;\n }\n do {\n while (v5 <= 1) --v5;\n v9 = a2;\n do {\n v10 = _mm_loadl_epi64(v9);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v10, 229)) <\n _mm_cvtsi128_si32(v10))\n v9->m128i_i64[0] = _mm_shuffle_epi32(v10, 225).m128i_u64[0];\n v9 = (__m128i *)((char *)v9 + 4);\n } while (v9 != (__m128i *)((char *)a2->m128i_i64 +\n 4 * (unsigned int)(v5 - 2) + 4));\n --v5;\n } while (v5 != 1);\n }\n v11 = 0LL;\n v12 = 4LL * a3;\n while (a1->m128i_i32[v11 / 4] == a2->m128i_i32[v11 / 4]) {\n v11 += 4LL;\n if (v11 == v12) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 651, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int test_tup1[], int n1, int test_tup2[], int n2) {\n for (int i = 0; i < n2; i++) {\n bool found = false;\n for (int j = 0; j < n1; j++) {\n if (test_tup2[i] == test_tup1[j]) {\n found = true;\n break;\n }\n }\n if (!found) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n int set1[] = {10, 4, 5, 6};\n\n int subset1[] = {5, 10};\n\n assert(func0(set1, 4, subset1, 2) == true);\n\n\n\n int set2[] = {1, 2, 3, 4};\n\n int subset2[] = {5, 6};\n\n assert(func0(set2, 4, subset2, 2) == false);\n\n\n\n int set3[] = {7, 8, 9, 10};\n\n int subset3[] = {10, 8};\n\n assert(func0(set3, 4, subset3, 2) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %ecx,-0x20(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11ed \nmovb $0x0,-0x9(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11cf \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 11cb \nmovb $0x1,-0x9(%rbp)\njmp 11d7 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1195 \nmovzbl -0x9(%rbp),%eax\nxor $0x1,%eax\ntest %al,%al\nje 11e9 \nmov $0x0,%eax\njmp 11fa \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x20(%rbp),%eax\njl 1188 \nmov $0x1,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov [rbp+var_8], 0\njmp short loc_11ED\nloc_1188:\nmov [rbp+var_9], 0\nmov [rbp+var_4], 0\njmp short loc_11CF\nloc_1195:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11CB\nmov [rbp+var_9], 1\njmp short loc_11D7\nloc_11CB:\nadd [rbp+var_4], 1\nloc_11CF:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1195\nloc_11D7:\nmovzx eax, [rbp+var_9]\nxor eax, 1\ntest al, al\njz short loc_11E9\nmov eax, 0\njmp short loc_11FA\nloc_11E9:\nadd [rbp+var_8], 1\nloc_11ED:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_20]\njl short loc_1188\nmov eax, 1\nloc_11FA:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3, int a4)\n{\n char v5; // [rsp+1Fh] [rbp-9h]\n int i; // [rsp+20h] [rbp-8h]\n int j; // [rsp+24h] [rbp-4h]\n\n for ( i = 0; i < a4; ++i )\n {\n v5 = 0;\n for ( j = 0; j < a2; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a3) == *(_DWORD *)(4LL * j + a1) )\n {\n v5 = 1;\n break;\n }\n }\n if ( v5 != 1 )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov [rbp+var_8], 0\njmp short loc_11ED\nloc_1188:\nmov [rbp+var_9], 0\nmov [rbp+var_4], 0\njmp short loc_11CF\nloc_1195:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11CB\nmov [rbp+var_9], 1\njmp short loc_11D7\nloc_11CB:\nadd [rbp+var_4], 1\nloc_11CF:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1195\nloc_11D7:\nmovzx eax, [rbp+var_9]\nxor eax, 1\ntest al, al\njz short loc_11E9\nmov eax, 0\njmp short loc_11FA\nloc_11E9:\nadd [rbp+var_8], 1\nloc_11ED:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_20]\njl short loc_1188\nmov eax, 1\nloc_11FA:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, __int64 a3, int a4)\n{\n char v5; // [rsp+1Fh] [rbp-9h]\n int i; // [rsp+20h] [rbp-8h]\n int j; // [rsp+24h] [rbp-4h]\n\n for ( i = 0; i < a4; ++i )\n {\n v5 = 0;\n for ( j = 0; j < a2; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a3) == *(_DWORD *)(4LL * j + a1) )\n {\n v5 = 1;\n break;\n }\n }\n if ( v5 != 1 )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, long long a3, int a4) {\n char v5;\n int i;\n int j;\n for (i = 0; i < a4; ++i) {\n v5 = 0;\n for (j = 0; j < a2; ++j) {\n if (*(uint32_t *)(4LL * i + a3) == *(uint32_t *)(4LL * j + a1)) {\n v5 = 1;\n break;\n }\n }\n if (v5 != 1) return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3, int a4) {\n char v5;\n int i;\n int j;\n for (i = 0; i < a4; ++i) {\n v5 = 0;\n for (j = 0; j < a2; ++j) {\n if (*(uint32_t *)(4LL * i + a3) == *(uint32_t *)(4LL * j + a1)) {\n v5 = 1;\n break;\n }\n }\n if (v5 != 1) return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": 651, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int test_tup1[], int n1, int test_tup2[], int n2) {\n for (int i = 0; i < n2; i++) {\n bool found = false;\n for (int j = 0; j < n1; j++) {\n if (test_tup2[i] == test_tup1[j]) {\n found = true;\n break;\n }\n }\n if (!found) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n int set1[] = {10, 4, 5, 6};\n\n int subset1[] = {5, 10};\n\n assert(func0(set1, 4, subset1, 2) == true);\n\n\n\n int set2[] = {1, 2, 3, 4};\n\n int subset2[] = {5, 6};\n\n assert(func0(set2, 4, subset2, 2) == false);\n\n\n\n int set3[] = {7, 8, 9, 10};\n\n int subset3[] = {10, 8};\n\n assert(func0(set3, 4, subset3, 2) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %ecx,%ecx\njle 1189 \nmov %rdx,%r8\nlea -0x1(%rcx),%eax\nlea 0x4(%rdx,%rax,4),%r10\nmov %rdi,%r9\nlea -0x1(%rsi),%eax\nlea 0x4(%rdi,%rax,4),%rcx\njmp 119e \nmov $0x1,%eax\nretq\nmov $0x0,%eax\nretq\nadd $0x4,%r8\ncmp %r10,%r8\nje 11bb \ntest %esi,%esi\njle 118f \nmov (%r8),%edx\nmov %r9,%rax\ncmp (%rax),%edx\nje 1195 \nadd $0x4,%rax\ncmp %rcx,%rax\njne 11a8 \nmov $0x0,%eax\nretq\nmov $0x1,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov r8, rdi\ntest ecx, ecx\njle short loc_11B2\nmov rdi, rdx\nmovsxd rcx, ecx\nlea r9, [rdx+rcx*4]\nmovsxd rax, esi\nlea rcx, [r8+rax*4]\njmp short loc_1190\nloc_1187:\nadd rdi, 4\ncmp rdi, r9\njz short loc_11B8\nloc_1190:\ntest esi, esi\njle short loc_11AC\nmov edx, [rdi]\nmov rax, r8\nloc_1199:\ncmp edx, [rax]\njz short loc_1187\nadd rax, 4\ncmp rax, rcx\njnz short loc_1199\nmov eax, 0\nretn\nloc_11AC:\nmov eax, 0\nretn\nloc_11B2:\nmov eax, 1\nretn\nloc_11B8:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2, _DWORD *a3, int a4)\n{\n _DWORD *v5; // rdi\n _DWORD *v6; // rax\n\n if ( a4 <= 0 )\n return 1LL;\n v5 = a3;\n while ( 2 )\n {\n if ( a2 <= 0 )\n return 0LL;\n v6 = a1;\n while ( *v5 != *v6 )\n {\n if ( ++v6 == &a1[a2] )\n return 0LL;\n }\n if ( ++v5 != &a3[a4] )\n continue;\n break;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov r8, rdi\ntest ecx, ecx\njle short loc_11B2\nmov rdi, rdx\nmovsxd rcx, ecx\nlea r9, [rdx+rcx*4]\nmovsxd rax, esi\nlea rcx, [r8+rax*4]\njmp short loc_1190\nloc_1187:\nadd rdi, 4\ncmp rdi, r9\njz short loc_11B8\nloc_1190:\ntest esi, esi\njle short loc_11AC\nmov edx, [rdi]\nmov rax, r8\nloc_1199:\ncmp edx, [rax]\njz short loc_1187\nadd rax, 4\ncmp rax, rcx\njnz short loc_1199\nmov eax, 0\nretn\nloc_11AC:\nmov eax, 0\nretn\nloc_11B2:\nmov eax, 1\nretn\nloc_11B8:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2, _DWORD *a3, int a4)\n{\n _DWORD *v5; // rdi\n _DWORD *v6; // rax\n\n if ( a4 <= 0 )\n return 1LL;\n v5 = a3;\n while ( 2 )\n {\n if ( a2 <= 0 )\n return 0LL;\n v6 = a1;\n while ( *v5 != *v6 )\n {\n if ( ++v6 == &a1[a2] )\n return 0LL;\n }\n if ( ++v5 != &a3[a4] )\n continue;\n break;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2, uint32_t *a3, int a4) {\n uint32_t *v5;\n uint32_t *v6;\n if (a4 <= 0) return 1LL;\n v5 = a3;\n while (2) {\n if (a2 <= 0) return 0LL;\n v6 = a1;\n while (*v5 != *v6) {\n if (++v6 == &a1[a2]) return 0LL;\n }\n if (++v5 != &a3[a4]) continue;\n break;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2, uint32_t *a3, int a4) {\n uint32_t *v5;\n uint32_t *v6;\n if (a4 <= 0) return 1LL;\n v5 = a3;\n while (2) {\n if (a2 <= 0) return 0LL;\n v6 = a1;\n while (*v5 != *v6) {\n if (++v6 == &a1[a2]) return 0LL;\n }\n if (++v5 != &a3[a4]) continue;\n break;\n }\n return 1LL;\n}" + }, + { + "index": 651, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int test_tup1[], int n1, int test_tup2[], int n2) {\n for (int i = 0; i < n2; i++) {\n bool found = false;\n for (int j = 0; j < n1; j++) {\n if (test_tup2[i] == test_tup1[j]) {\n found = true;\n break;\n }\n }\n if (!found) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n int set1[] = {10, 4, 5, 6};\n\n int subset1[] = {5, 10};\n\n assert(func0(set1, 4, subset1, 2) == true);\n\n\n\n int set2[] = {1, 2, 3, 4};\n\n int subset2[] = {5, 6};\n\n assert(func0(set2, 4, subset2, 2) == false);\n\n\n\n int set3[] = {7, 8, 9, 10};\n\n int subset3[] = {10, 8};\n\n assert(func0(set3, 4, subset3, 2) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %ecx,%ecx\njle 1186 \nlea -0x1(%rcx),%eax\nmov %rdx,%r8\nlea 0x4(%rdx,%rax,4),%r9\nlea -0x1(%rsi),%eax\nlea 0x4(%rdi,%rax,4),%rcx\nnopl 0x0(%rax,%rax,1)\ntest %esi,%esi\njle 1190 \nmov (%r8),%edx\nmov %rdi,%rax\njmp 1179 \nnopl 0x0(%rax)\nadd $0x4,%rax\ncmp %rcx,%rax\nje 1190 \ncmp (%rax),%edx\njne 1170 \nadd $0x4,%r8\ncmp %r9,%r8\njne 1160 \nmov $0x1,%eax\nretq\nnopl 0x0(%rax)\nxor %eax,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\nmov r8, rdi\ntest ecx, ecx\njle short loc_12F6\nmovsxd rcx, ecx\nmovsxd rax, esi\nlea r9, [rdx+rcx*4]\nlea rdi, [rdi+rax*4]\ntest esi, esi\njle short loc_1300\nnop dword ptr [rax]\nloc_12D0:\nmov ecx, [rdx]\nmov rax, r8\njmp short loc_12E9\nloc_12E0:\nadd rax, 4\ncmp rax, rdi\njz short loc_1300\nloc_12E9:\ncmp ecx, [rax]\njnz short loc_12E0\nadd rdx, 4\ncmp rdx, r9\njnz short loc_12D0\nloc_12F6:\nmov eax, 1\nretn\nloc_1300:\nxor eax, eax\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2, _DWORD *a3, int a4)\n{\n _DWORD *v5; // r9\n _DWORD *v6; // rdi\n _DWORD *v7; // rax\n\n if ( a4 <= 0 )\n return 1LL;\n v5 = &a3[a4];\n v6 = &a1[a2];\n if ( a2 > 0 )\n {\n do\n {\n v7 = a1;\n while ( *a3 != *v7 )\n {\n if ( ++v7 == v6 )\n return 0LL;\n }\n ++a3;\n }\n while ( a3 != v5 );\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_12B0:\nendbr64\nmov r8, rdi\ntest ecx, ecx\njle short loc_12F6\nmovsxd rcx, ecx\nmovsxd rax, esi\nlea r9, [rdx+rcx*4]\nlea rdi, [rdi+rax*4]\ntest esi, esi\njle short loc_1300\nnop dword ptr [rax]\nloc_12D0:\nmov ecx, [rdx]\nmov rax, r8\njmp short loc_12E9\nloc_12E0:\nadd rax, 4\ncmp rax, rdi\njz short loc_1300\nloc_12E9:\ncmp ecx, [rax]\njnz short loc_12E0\nadd rdx, 4\ncmp rdx, r9\njnz short loc_12D0\nloc_12F6:\nmov eax, 1\nretn\nloc_1300:\nxor eax, eax\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12B0(_DWORD *a1, int a2, _DWORD *a3, int a4)\n{\n _DWORD *v5; // r9\n _DWORD *v6; // rdi\n _DWORD *v7; // rax\n\n if ( a4 <= 0 )\n return 1LL;\n v5 = &a3[a4];\n v6 = &a1[a2];\n if ( a2 > 0 )\n {\n do\n {\n v7 = a1;\n while ( *a3 != *v7 )\n {\n if ( ++v7 == v6 )\n return 0LL;\n }\n ++a3;\n }\n while ( a3 != v5 );\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12B0(uint32_t *a1, int a2, uint32_t *a3, int a4) {\n uint32_t *v5;\n uint32_t *v6;\n uint32_t *v7;\n if (a4 <= 0) return 1LL;\n v5 = &a3[a4];\n v6 = &a1[a2];\n if (a2 > 0) {\n do {\n v7 = a1;\n while (*a3 != *v7) {\n if (++v7 == v6) return 0LL;\n }\n ++a3;\n } while (a3 != v5);\n return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2, uint32_t *a3, int a4) {\n uint32_t *v5;\n uint32_t *v6;\n uint32_t *v7;\n if (a4 <= 0) return 1LL;\n v5 = &a3[a4];\n v6 = &a1[a2];\n if (a2 > 0) {\n do {\n v7 = a1;\n while (*a3 != *v7) {\n if (++v7 == v6) return 0LL;\n }\n ++a3;\n } while (a3 != v5);\n return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 652, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(int test_list[3][2][2], int rows, int cols, int pairs) {\n static char res[100];\n int flat_list[6][2];\n int f = 0;\n for (int i = 0; i < rows; i++) {\n for (int j = 0; j < cols; j++) {\n flat_list[f][0] = test_list[i][j][0];\n flat_list[f][1] = test_list[i][j][1];\n f++;\n }\n }\n char temp1[50] = \"\";\n char temp2[50] = \"\";\n char part1[10], part2[10];\n for (int k = 0; k < 6; k++) {\n sprintf(part1, \"%d\", flat_list[k][0]);\n sprintf(part2, \"%d\", flat_list[k][1]);\n strcat(temp1, part1);\n strcat(temp2, part2);\n if (k != 5) {\n strcat(temp1, \", \");\n strcat(temp2, \", \");\n }\n }\n sprintf(res, \"[(%s), (%s)]\", temp1, temp2);\n return res;\n}", + "test": "int main() {\n\n int test1[3][2][2] = {{{4, 5}, {7, 8}}, {{10, 13}, {18, 17}}, {{0, 4}, {10, 1}}};\n\n int test2[3][2][2] = {{{5, 6}, {8, 9}}, {{11, 14}, {19, 18}}, {{1, 5}, {11, 2}}};\n\n int test3[3][2][2] = {{{6, 7}, {9, 10}}, {{12, 15}, {20, 21}}, {{23, 7}, {15, 8}}};\n\n\n\n assert(strcmp(func0(test1, 3, 2, 2), \"[(4, 7, 10, 18, 0, 10), (5, 8, 13, 17, 4, 1)]\") == 0);\n\n assert(strcmp(func0(test2, 3, 2, 2), \"[(5, 8, 11, 19, 1, 11), (6, 9, 14, 18, 5, 2)]\") == 0);\n\n assert(strcmp(func0(test3, 3, 2, 2), \"[(6, 9, 12, 20, 23, 15), (7, 10, 15, 21, 7, 8)]\") == 0);\n\n\n\n printf(\"All tests passed!\\n\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x100,%rsp\nmov %rdi,-0xe8(%rbp)\nmov %esi,-0xec(%rbp)\nmov %edx,-0xf0(%rbp)\nmov %ecx,-0xf4(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovl $0x0,-0xe0(%rbp)\nmovl $0x0,-0xdc(%rbp)\njmpq 12d3 \nmovl $0x0,-0xd8(%rbp)\njmp 12ba \nmov -0xdc(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0xe8(%rbp),%rax\nadd %rax,%rdx\nmov -0xd8(%rbp),%eax\ncltq\nmov (%rdx,%rax,8),%edx\nmov -0xe0(%rbp),%eax\ncltq\nmov %edx,-0xd0(%rbp,%rax,8)\nmov -0xdc(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0xe8(%rbp),%rax\nadd %rax,%rdx\nmov -0xd8(%rbp),%eax\ncltq\nmov 0x4(%rdx,%rax,8),%edx\nmov -0xe0(%rbp),%eax\ncltq\nmov %edx,-0xcc(%rbp,%rax,8)\naddl $0x1,-0xe0(%rbp)\naddl $0x1,-0xd8(%rbp)\nmov -0xd8(%rbp),%eax\ncmp -0xf0(%rbp),%eax\njl 1245 \naddl $0x1,-0xdc(%rbp)\nmov -0xdc(%rbp),%eax\ncmp -0xec(%rbp),%eax\njl 1239 \nmovq $0x0,-0x80(%rbp)\nmovq $0x0,-0x78(%rbp)\nmovq $0x0,-0x70(%rbp)\nmovq $0x0,-0x68(%rbp)\nmovq $0x0,-0x60(%rbp)\nmovq $0x0,-0x58(%rbp)\nmovw $0x0,-0x50(%rbp)\nmovq $0x0,-0x40(%rbp)\nmovq $0x0,-0x38(%rbp)\nmovq $0x0,-0x30(%rbp)\nmovq $0x0,-0x28(%rbp)\nmovq $0x0,-0x20(%rbp)\nmovq $0x0,-0x18(%rbp)\nmovw $0x0,-0x10(%rbp)\nmovl $0x0,-0xd4(%rbp)\njmpq 1454 \nmov -0xd4(%rbp),%eax\ncltq\nmov -0xd0(%rbp,%rax,8),%edx\nlea -0x94(%rbp),%rax\nlea 0xc8b(%rip),%rsi\nmov %rax,%rdi\nmov $0x0,%eax\ncallq 10f0 \nmov -0xd4(%rbp),%eax\ncltq\nmov -0xcc(%rbp,%rax,8),%edx\nlea -0x8a(%rbp),%rax\nlea 0xc61(%rip),%rsi\nmov %rax,%rdi\nmov $0x0,%eax\ncallq 10f0 \nlea -0x94(%rbp),%rdx\nlea -0x80(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10e0 \nlea -0x8a(%rbp),%rdx\nlea -0x40(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10e0 \ncmpl $0x5,-0xd4(%rbp)\nje 144d \nlea -0x80(%rbp),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nlea -0x80(%rbp),%rax\nadd %rdx,%rax\nmovw $0x202c,(%rax)\nmovb $0x0,0x2(%rax)\nlea -0x40(%rbp),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nlea -0x40(%rbp),%rax\nadd %rdx,%rax\nmovw $0x202c,(%rax)\nmovb $0x0,0x2(%rax)\naddl $0x1,-0xd4(%rbp)\ncmpl $0x5,-0xd4(%rbp)\njle 1360 \nlea -0x40(%rbp),%rdx\nlea -0x80(%rbp),%rax\nmov %rdx,%rcx\nmov %rax,%rdx\nlea 0xb95(%rip),%rsi\nlea 0x2bc3(%rip),%rdi\nmov $0x0,%eax\ncallq 10f0 \nlea 0x2bb2(%rip),%rax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 14a2 \ncallq 10b0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 100h\nmov [rbp+var_E8], rdi\nmov [rbp+var_EC], esi\nmov [rbp+var_F0], edx\nmov [rbp+var_F4], ecx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_E0], 0\nmov [rbp+var_DC], 0\njmp loc_12F3\nloc_1259:\nmov [rbp+var_D8], 0\njmp short loc_12DA\nloc_1265:\nmov eax, [rbp+var_DC]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_E8]\nadd rdx, rax\nmov eax, [rbp+var_D8]\ncdqe\nmov edx, [rdx+rax*8]\nmov eax, [rbp+var_E0]\ncdqe\nmov [rbp+rax*8+var_D0], edx\nmov eax, [rbp+var_DC]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_E8]\nadd rdx, rax\nmov eax, [rbp+var_D8]\ncdqe\nmov edx, [rdx+rax*8+4]\nmov eax, [rbp+var_E0]\ncdqe\nmov [rbp+rax*8+var_CC], edx\nadd [rbp+var_E0], 1\nadd [rbp+var_D8], 1\nloc_12DA:\nmov eax, [rbp+var_D8]\ncmp eax, [rbp+var_F0]\njl loc_1265\nadd [rbp+var_DC], 1\nloc_12F3:\nmov eax, [rbp+var_DC]\ncmp eax, [rbp+var_EC]\njl loc_1259\nmov qword ptr [rbp+dest], 0\nmov [rbp+var_78], 0\nmov [rbp+var_70], 0\nmov [rbp+var_68], 0\nmov [rbp+var_60], 0\nmov [rbp+var_58], 0\nmov [rbp+var_50], 0\nmov qword ptr [rbp+var_40], 0\nmov [rbp+var_38], 0\nmov [rbp+var_30], 0\nmov [rbp+var_28], 0\nmov [rbp+var_20], 0\nmov [rbp+var_18], 0\nmov [rbp+var_10], 0\nmov [rbp+var_D4], 0\njmp loc_1454\nloc_1380:\nmov eax, [rbp+var_D4]\ncdqe\nmov edx, [rbp+rax*8+var_D0]\nlea rax, [rbp+s]\nlea rcx, format; \"%d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nmov eax, [rbp+var_D4]\ncdqe\nmov edx, [rbp+rax*8+var_CC]\nlea rax, [rbp+src]\nlea rcx, format; \"%d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rdx, [rbp+s]\nlea rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\nlea rdx, [rbp+src]\nlea rax, [rbp+var_40]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\ncmp [rbp+var_D4], 5\njz short loc_144D\nlea rax, [rbp+dest]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nlea rax, [rbp+dest]\nadd rax, rdx\nmov word ptr [rax], 202Ch\nmov byte ptr [rax+2], 0\nlea rax, [rbp+var_40]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nlea rax, [rbp+var_40]\nadd rax, rdx\nmov word ptr [rax], 202Ch\nmov byte ptr [rax+2], 0\nloc_144D:\nadd [rbp+var_D4], 1\nloc_1454:\ncmp [rbp+var_D4], 5\njle loc_1380\nlea rdx, [rbp+var_40]\nlea rax, [rbp+dest]\nmov rcx, rdx\nmov rdx, rax\nlea rax, aSS; \"[(%s), (%s)]\"\nmov rsi, rax; format\nlea rax, res_1\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rax, res_1\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_14A8\ncall ___stack_chk_fail\nlocret_14A8:\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2, int a3)\n{\n int v4; // [rsp+20h] [rbp-E0h]\n int i; // [rsp+24h] [rbp-DCh]\n int j; // [rsp+28h] [rbp-D8h]\n int k; // [rsp+2Ch] [rbp-D4h]\n _DWORD v8[15]; // [rsp+30h] [rbp-D0h]\n char s[10]; // [rsp+6Ch] [rbp-94h] BYREF\n char src[10]; // [rsp+76h] [rbp-8Ah] BYREF\n char dest[8]; // [rsp+80h] [rbp-80h] BYREF\n __int64 v12; // [rsp+88h] [rbp-78h]\n __int64 v13; // [rsp+90h] [rbp-70h]\n __int64 v14; // [rsp+98h] [rbp-68h]\n __int64 v15; // [rsp+A0h] [rbp-60h]\n __int64 v16; // [rsp+A8h] [rbp-58h]\n __int16 v17; // [rsp+B0h] [rbp-50h]\n char v18[8]; // [rsp+C0h] [rbp-40h] BYREF\n __int64 v19; // [rsp+C8h] [rbp-38h]\n __int64 v20; // [rsp+D0h] [rbp-30h]\n __int64 v21; // [rsp+D8h] [rbp-28h]\n __int64 v22; // [rsp+E0h] [rbp-20h]\n __int64 v23; // [rsp+E8h] [rbp-18h]\n __int16 v24; // [rsp+F0h] [rbp-10h]\n unsigned __int64 v25; // [rsp+F8h] [rbp-8h]\n\n v25 = __readfsqword(0x28u);\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = 0; j < a3; ++j )\n {\n v8[2 * v4] = *(_DWORD *)(a1 + 16LL * i + 8LL * j);\n v8[2 * v4++ + 1] = *(_DWORD *)(a1 + 16LL * i + 8LL * j + 4);\n }\n }\n *(_QWORD *)dest = 0LL;\n v12 = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0;\n *(_QWORD *)v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n v22 = 0LL;\n v23 = 0LL;\n v24 = 0;\n for ( k = 0; k <= 5; ++k )\n {\n sprintf(s, \"%d\", v8[2 * k]);\n sprintf(src, \"%d\", v8[2 * k + 1]);\n strcat(dest, s);\n strcat(v18, src);\n if ( k != 5 )\n {\n strcpy(&dest[strlen(dest)], \", \");\n strcpy(&v18[strlen(v18)], \", \");\n }\n }\n sprintf(res_1, \"[(%s), (%s)]\", dest, v18);\n return res_1;\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 100h\nmov [rbp+var_E8], rdi\nmov [rbp+var_EC], esi\nmov [rbp+var_F0], edx\nmov [rbp+var_F4], ecx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_E0], 0\nmov [rbp+var_DC], 0\njmp loc_12F3\nloc_1259:\nmov [rbp+var_D8], 0\njmp short loc_12DA\nloc_1265:\nmov eax, [rbp+var_DC]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_E8]\nadd rdx, rax\nmov eax, [rbp+var_D8]\ncdqe\nmov edx, [rdx+rax*8]\nmov eax, [rbp+var_E0]\ncdqe\nmov [rbp+rax*8+var_D0], edx\nmov eax, [rbp+var_DC]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_E8]\nadd rdx, rax\nmov eax, [rbp+var_D8]\ncdqe\nmov edx, [rdx+rax*8+4]\nmov eax, [rbp+var_E0]\ncdqe\nmov [rbp+rax*8+var_CC], edx\nadd [rbp+var_E0], 1\nadd [rbp+var_D8], 1\nloc_12DA:\nmov eax, [rbp+var_D8]\ncmp eax, [rbp+var_F0]\njl loc_1265\nadd [rbp+var_DC], 1\nloc_12F3:\nmov eax, [rbp+var_DC]\ncmp eax, [rbp+var_EC]\njl loc_1259\nmov qword ptr [rbp+dest], 0\nmov [rbp+var_78], 0\nmov [rbp+var_70], 0\nmov [rbp+var_68], 0\nmov [rbp+var_60], 0\nmov [rbp+var_58], 0\nmov [rbp+var_50], 0\nmov qword ptr [rbp+var_40], 0\nmov [rbp+var_38], 0\nmov [rbp+var_30], 0\nmov [rbp+var_28], 0\nmov [rbp+var_20], 0\nmov [rbp+var_18], 0\nmov [rbp+var_10], 0\nmov [rbp+var_D4], 0\njmp loc_1454\nloc_1380:\nmov eax, [rbp+var_D4]\ncdqe\nmov edx, [rbp+rax*8+var_D0]\nlea rax, [rbp+s]\nlea rcx, format; \"%d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nmov eax, [rbp+var_D4]\ncdqe\nmov edx, [rbp+rax*8+var_CC]\nlea rax, [rbp+src]\nlea rcx, format; \"%d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rdx, [rbp+s]\nlea rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\nlea rdx, [rbp+src]\nlea rax, [rbp+var_40]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\ncmp [rbp+var_D4], 5\njz short loc_144D\nlea rax, [rbp+dest]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nlea rax, [rbp+dest]\nadd rax, rdx\nmov word ptr [rax], 202Ch\nmov byte ptr [rax+2], 0\nlea rax, [rbp+var_40]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nlea rax, [rbp+var_40]\nadd rax, rdx\nmov word ptr [rax], 202Ch\nmov byte ptr [rax+2], 0\nloc_144D:\nadd [rbp+var_D4], 1\nloc_1454:\ncmp [rbp+var_D4], 5\njle loc_1380\nlea rdx, [rbp+var_40]\nlea rax, [rbp+dest]\nmov rcx, rdx\nmov rdx, rax\nlea rax, aSS; \"[(%s), (%s)]\"\nmov rsi, rax; format\nlea rax, s\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rax, s\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_14A8\ncall ___stack_chk_fail\nlocret_14A8:\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1209(__int64 a1, int a2, int a3)\n{\n int v4; // [rsp+20h] [rbp-E0h]\n int i; // [rsp+24h] [rbp-DCh]\n int j; // [rsp+28h] [rbp-D8h]\n int k; // [rsp+2Ch] [rbp-D4h]\n _DWORD v8[15]; // [rsp+30h] [rbp-D0h]\n char s[10]; // [rsp+6Ch] [rbp-94h] BYREF\n char src[10]; // [rsp+76h] [rbp-8Ah] BYREF\n char dest[8]; // [rsp+80h] [rbp-80h] BYREF\n __int64 v12; // [rsp+88h] [rbp-78h]\n __int64 v13; // [rsp+90h] [rbp-70h]\n __int64 v14; // [rsp+98h] [rbp-68h]\n __int64 v15; // [rsp+A0h] [rbp-60h]\n __int64 v16; // [rsp+A8h] [rbp-58h]\n __int16 v17; // [rsp+B0h] [rbp-50h]\n char v18[8]; // [rsp+C0h] [rbp-40h] BYREF\n __int64 v19; // [rsp+C8h] [rbp-38h]\n __int64 v20; // [rsp+D0h] [rbp-30h]\n __int64 v21; // [rsp+D8h] [rbp-28h]\n __int64 v22; // [rsp+E0h] [rbp-20h]\n __int64 v23; // [rsp+E8h] [rbp-18h]\n __int16 v24; // [rsp+F0h] [rbp-10h]\n unsigned __int64 v25; // [rsp+F8h] [rbp-8h]\n\n v25 = __readfsqword(0x28u);\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = 0; j < a3; ++j )\n {\n v8[2 * v4] = *(_DWORD *)(a1 + 16LL * i + 8LL * j);\n v8[2 * v4++ + 1] = *(_DWORD *)(a1 + 16LL * i + 8LL * j + 4);\n }\n }\n *(_QWORD *)dest = 0LL;\n v12 = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0;\n *(_QWORD *)v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n v22 = 0LL;\n v23 = 0LL;\n v24 = 0;\n for ( k = 0; k <= 5; ++k )\n {\n sprintf(s, \"%d\", v8[2 * k]);\n sprintf(src, \"%d\", v8[2 * k + 1]);\n strcat(dest, s);\n strcat(v18, src);\n if ( k != 5 )\n {\n strcpy(&dest[strlen(dest)], \", \");\n strcpy(&v18[strlen(v18)], \", \");\n }\n }\n sprintf(::s, \"[(%s), (%s)]\", dest, v18);\n return ::s;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1209(long long a1, int a2, int a3) {\n int v4;\n int i;\n int j;\n int k;\n uint32_t v8[15];\n char s[10];\n char src[10];\n char dest[8];\n long long v12;\n long long v13;\n long long v14;\n long long v15;\n long long v16;\n short v17;\n char v18[8];\n long long v19;\n long long v20;\n long long v21;\n long long v22;\n long long v23;\n short v24;\n unsigned long long v25;\n v25 = __readfsqword(40u);\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = 0; j < a3; ++j) {\n v8[2 * v4] = *(uint32_t *)(a1 + 16LL * i + 8LL * j);\n v8[2 * v4++ + 1] = *(uint32_t *)(a1 + 16LL * i + 8LL * j + 4);\n }\n }\n *(uint64_t *)dest = 0LL;\n v12 = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0;\n *(uint64_t *)v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n v22 = 0LL;\n v23 = 0LL;\n v24 = 0;\n for (k = 0; k <= 5; ++k) {\n sprintf(s, \"%d\", v8[2 * k]);\n sprintf(src, \"%d\", v8[2 * k + 1]);\n strcat(dest, s);\n strcat(v18, src);\n if (k != 5) {\n strcpy(&dest[strlen(dest)], \", \");\n strcpy(&v18[strlen(v18)], \", \");\n }\n }\n sprintf(::s, \"[(%s), (%s)]\", dest, v18);\n return ::s;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2, int a3) {\n int v4;\n int i;\n int j;\n int k;\n uint32_t v8[15];\n char s[10];\n char src[10];\n char dest[8];\n long long v12;\n long long v13;\n long long v14;\n long long v15;\n long long v16;\n short v17;\n char v18[8];\n long long v19;\n long long v20;\n long long v21;\n long long v22;\n long long v23;\n short v24;\n unsigned long long v25;\n v25 = __readfsqword(40u);\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = 0; j < a3; ++j) {\n v8[2 * v4] = *(uint32_t *)(a1 + 16LL * i + 8LL * j);\n v8[2 * v4++ + 1] = *(uint32_t *)(a1 + 16LL * i + 8LL * j + 4);\n }\n }\n *(uint64_t *)dest = 0LL;\n v12 = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0;\n *(uint64_t *)v18 = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n v21 = 0LL;\n v22 = 0LL;\n v23 = 0LL;\n v24 = 0;\n for (k = 0; k <= 5; ++k) {\n sprintf(s, \"%d\", v8[2 * k]);\n sprintf(src, \"%d\", v8[2 * k + 1]);\n strcat(dest, s);\n strcat(v18, src);\n if (k != 5) {\n strcpy(&dest[strlen(dest)], \", \");\n strcpy(&v18[strlen(v18)], \", \");\n }\n }\n sprintf(res_1, \"[(%s), (%s)]\", dest, v18);\n return res_1;\n}" + }, + { + "index": 652, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(int test_list[3][2][2], int rows, int cols, int pairs) {\n static char res[100];\n int flat_list[6][2];\n int f = 0;\n for (int i = 0; i < rows; i++) {\n for (int j = 0; j < cols; j++) {\n flat_list[f][0] = test_list[i][j][0];\n flat_list[f][1] = test_list[i][j][1];\n f++;\n }\n }\n char temp1[50] = \"\";\n char temp2[50] = \"\";\n char part1[10], part2[10];\n for (int k = 0; k < 6; k++) {\n sprintf(part1, \"%d\", flat_list[k][0]);\n sprintf(part2, \"%d\", flat_list[k][1]);\n strcat(temp1, part1);\n strcat(temp2, part2);\n if (k != 5) {\n strcat(temp1, \", \");\n strcat(temp2, \", \");\n }\n }\n sprintf(res, \"[(%s), (%s)]\", temp1, temp2);\n return res;\n}", + "test": "int main() {\n\n int test1[3][2][2] = {{{4, 5}, {7, 8}}, {{10, 13}, {18, 17}}, {{0, 4}, {10, 1}}};\n\n int test2[3][2][2] = {{{5, 6}, {8, 9}}, {{11, 14}, {19, 18}}, {{1, 5}, {11, 2}}};\n\n int test3[3][2][2] = {{{6, 7}, {9, 10}}, {{12, 15}, {20, 21}}, {{23, 7}, {15, 8}}};\n\n\n\n assert(strcmp(func0(test1, 3, 2, 2), \"[(4, 7, 10, 18, 0, 10), (5, 8, 13, 17, 4, 1)]\") == 0);\n\n assert(strcmp(func0(test2, 3, 2, 2), \"[(5, 8, 11, 19, 1, 11), (6, 9, 14, 18, 5, 2)]\") == 0);\n\n assert(strcmp(func0(test3, 3, 2, 2), \"[(6, 9, 12, 20, 23, 15), (7, 10, 15, 21, 7, 8)]\") == 0);\n\n\n\n printf(\"All tests passed!\\n\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0xd8,%rsp\nmov %fs:0x28,%rax\nmov %rax,0xc8(%rsp)\nxor %eax,%eax\ntest %esi,%esi\njle 1248 \nmov %rdi,%r8\nlea -0x1(%rsi),%eax\nshl $0x4,%rax\nlea 0x10(%rdi,%rax,1),%r10\nmov $0x0,%r9d\nmov %rsp,%r11\njmp 1242 \nmov %r8,%rsi\nmovslq %r9d,%rax\nlea (%r11,%rax,8),%rcx\nmov $0x0,%eax\nmov (%rsi,%rax,8),%edi\nmov %edi,(%rcx)\nmov 0x4(%rsi,%rax,8),%edi\nmov %edi,0x4(%rcx)\nadd $0x1,%rax\nadd $0x8,%rcx\ncmp %eax,%edx\njg 121e \nadd %edx,%r9d\nadd $0x10,%r8\ncmp %r10,%r8\nje 1248 \ntest %edx,%edx\njg 120f \njmp 1239 \nmovq $0x0,0x50(%rsp)\nmovq $0x0,0x58(%rsp)\nmovq $0x0,0x60(%rsp)\nmovq $0x0,0x68(%rsp)\nmovq $0x0,0x70(%rsp)\nmovq $0x0,0x78(%rsp)\nmovw $0x0,0x80(%rsp)\nmovq $0x0,0x90(%rsp)\nmovq $0x0,0x98(%rsp)\nmovq $0x0,0xa0(%rsp)\nmovq $0x0,0xa8(%rsp)\nmovq $0x0,0xb0(%rsp)\nmovq $0x0,0xb8(%rsp)\nmovw $0x0,0xc0(%rsp)\nlea 0x3c(%rsp),%rbp\nmov (%rsp),%r8d\nlea 0xd1a(%rip),%rcx\nmov $0xa,%edx\nmov $0x1,%esi\nmov %rbp,%rdi\nmov $0x0,%eax\ncallq 10d0 <__sprintf_chk@plt>\nlea 0x46(%rsp),%rbx\nmov 0x4(%rsp),%r8d\nlea 0xcf2(%rip),%rcx\nmov $0xa,%edx\nmov $0x1,%esi\nmov %rbx,%rdi\nmov $0x0,%eax\ncallq 10d0 <__sprintf_chk@plt>\nlea 0x50(%rsp),%rdi\nmov $0x32,%edx\nmov %rbp,%rsi\ncallq 1090 <__strcat_chk@plt>\nlea 0x90(%rsp),%rdi\nmov $0x32,%edx\nmov %rbx,%rsi\ncallq 1090 <__strcat_chk@plt>\nmov %rsp,%rbx\nlea 0x28(%rsp),%r15\nlea 0x50(%rsp),%r14\nmov $0x32,%edx\nlea 0xc9e(%rip),%rsi\nmov %r14,%rdi\ncallq 1090 <__strcat_chk@plt>\nlea 0x90(%rsp),%rbp\nmov $0x32,%edx\nlea 0xc82(%rip),%rsi\nmov %rbp,%rdi\ncallq 1090 <__strcat_chk@plt>\nlea 0x3c(%rsp),%r13\nmov 0x8(%rbx),%r8d\nlea 0xc67(%rip),%rcx\nmov $0xa,%edx\nmov $0x1,%esi\nmov %r13,%rdi\nmov $0x0,%eax\ncallq 10d0 <__sprintf_chk@plt>\nlea 0x46(%rsp),%r12\nmov 0xc(%rbx),%r8d\nlea 0xc40(%rip),%rcx\nmov $0xa,%edx\nmov $0x1,%esi\nmov %r12,%rdi\nmov $0x0,%eax\ncallq 10d0 <__sprintf_chk@plt>\nmov $0x32,%edx\nmov %r13,%rsi\nmov %r14,%rdi\ncallq 1090 <__strcat_chk@plt>\nmov $0x32,%edx\nmov %r12,%rsi\nmov %rbp,%rdi\ncallq 1090 <__strcat_chk@plt>\nadd $0x8,%rbx\ncmp %r15,%rbx\njne 135d \nlea 0x90(%rsp),%r9\nlea 0x50(%rsp),%r8\nlea 0xbee(%rip),%rcx\nmov $0x64,%edx\nmov $0x1,%esi\nlea 0x2c13(%rip),%rdi\nmov $0x0,%eax\ncallq 10d0 <__sprintf_chk@plt>\nmov 0xc8(%rsp),%rax\nxor %fs:0x28,%rax\njne 1463 \nlea 0x2bef(%rip),%rax\nadd $0xd8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\ncallq 10b0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 0E8h\nmov rax, fs:28h\nmov [rsp+118h+var_40], rax\nxor eax, eax\ntest esi, esi\njle short loc_1272\nmov r8d, edx\nmovsxd r9, edx\nlea rcx, [rdi+r9*8]\nmovsxd rsi, esi\nlea rax, [r9+rsi*2]\nlea r10, [rdi+rax*8]\nneg r9\nshl r9, 3\nmov edi, 0\nlea r11, [rsp+118h+var_108]\njmp short loc_126B\nloc_123D:\nlea rax, [rcx+r9]\nmovsxd rdx, edi\nlea rdx, [r11+rdx*8]\nloc_1248:\nmov esi, [rax]\nmov [rdx], esi\nmov esi, [rax+4]\nmov [rdx+4], esi\nadd rax, 8\nadd rdx, 8\ncmp rax, rcx\njnz short loc_1248\nadd edi, r8d\nloc_1262:\nadd rcx, 10h\ncmp rcx, r10\njz short loc_1272\nloc_126B:\ntest r8d, r8d\njg short loc_123D\njmp short loc_1262\nloc_1272:\nmov [rsp+118h+var_B8], 0\nmov [rsp+118h+var_B0], 0\nmov [rsp+118h+var_A8], 0\nmov [rsp+118h+var_A0], 0\nmov [rsp+118h+var_98], 0\nmov [rsp+118h+var_90], 0\nmov [rsp+118h+var_88], 0\nmov [rsp+118h+var_78], 0\nmov [rsp+118h+var_70], 0\nmov [rsp+118h+var_68], 0\nmov [rsp+118h+var_60], 0\nmov [rsp+118h+var_58], 0\nmov [rsp+118h+var_50], 0\nmov [rsp+118h+var_48], 0\nlea rbx, [rsp+118h+var_108]\nlea r15, [rsp+118h+var_E0]\nlea rax, [rsp+118h+var_D8]\nmov [rsp+118h+var_110], rax\nlea r13, [rsp+118h+var_CC]\nlea r12, unk_2004\nlea rbp, [rsp+118h+var_C2]\nlea r14, unk_2007\njmp short loc_136D\nloc_1338:\nlea rdi, [rsp+118h+var_B8]\nmov edx, 32h ; '2'\nmov rsi, r14\ncall ___strcat_chk\nlea rdi, [rsp+118h+var_78]\nmov edx, 32h ; '2'\nmov rsi, r14\ncall ___strcat_chk\nadd rbx, 8\nmov rax, [rsp+118h+var_110]\ncmp rbx, rax\njz short loc_13D8\nloc_136D:\nmov r8d, [rbx]\nmov rcx, r12\nmov edx, 0Ah\nmov esi, 2\nmov rdi, r13\nmov eax, 0\ncall ___sprintf_chk\nmov r8d, [rbx+4]\nmov rcx, r12\nmov edx, 0Ah\nmov esi, 2\nmov rdi, rbp\nmov eax, 0\ncall ___sprintf_chk\nlea rdi, [rsp+118h+var_B8]\nmov edx, 32h ; '2'\nmov rsi, r13\ncall ___strcat_chk\nlea rdi, [rsp+118h+var_78]\nmov edx, 32h ; '2'\nmov rsi, rbp\ncall ___strcat_chk\ncmp rbx, r15\njnz loc_1338\nloc_13D8:\nlea r9, [rsp+118h+var_78]\nlea r8, [rsp+118h+var_B8]\nlea rcx, aSS; \"[(%s), (%s)]\"\nmov edx, 64h ; 'd'\nmov esi, 2\nlea rbx, res_1\nmov rdi, rbx\nmov eax, 0\ncall ___sprintf_chk\nmov rax, [rsp+118h+var_40]\nsub rax, fs:28h\njnz short loc_1432\nmov rax, rbx\nadd rsp, 0E8h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1432:\ncall ___stack_chk_fail", + "ida_pseudo": "void *__fastcall func0(__int64 a1, int a2, int a3)\n{\n _DWORD *v4; // rcx\n _DWORD *v5; // r10\n __int64 v6; // r9\n int v7; // edi\n _DWORD *v8; // rax\n _DWORD *v9; // rdx\n char *v10; // rbx\n _QWORD v12[5]; // [rsp+10h] [rbp-108h] BYREF\n char v13; // [rsp+38h] [rbp-E0h] BYREF\n char v14; // [rsp+40h] [rbp-D8h] BYREF\n _BYTE v15[10]; // [rsp+4Ch] [rbp-CCh] BYREF\n _BYTE v16[10]; // [rsp+56h] [rbp-C2h] BYREF\n _QWORD v17[6]; // [rsp+60h] [rbp-B8h] BYREF\n __int16 v18; // [rsp+90h] [rbp-88h]\n _QWORD v19[6]; // [rsp+A0h] [rbp-78h] BYREF\n __int16 v20; // [rsp+D0h] [rbp-48h]\n unsigned __int64 v21; // [rsp+D8h] [rbp-40h]\n\n v21 = __readfsqword(0x28u);\n if ( a2 > 0 )\n {\n v4 = (_DWORD *)(a1 + 8LL * a3);\n v5 = (_DWORD *)(a1 + 8 * (a3 + 2LL * a2));\n v6 = 0x3FFFFFFFFFFFFFFELL * a3;\n v7 = 0;\n do\n {\n if ( a3 > 0 )\n {\n v8 = &v4[v6];\n v9 = &v12[v7];\n do\n {\n *v9 = *v8;\n v9[1] = v8[1];\n v8 += 2;\n v9 += 2;\n }\n while ( v8 != v4 );\n v7 += a3;\n }\n v4 += 4;\n }\n while ( v4 != v5 );\n }\n memset(v17, 0, sizeof(v17));\n v18 = 0;\n memset(v19, 0, sizeof(v19));\n v20 = 0;\n v10 = (char *)v12;\n do\n {\n __sprintf_chk(v15, 2LL, 10LL, &unk_2004, *(unsigned int *)v10);\n __sprintf_chk(v16, 2LL, 10LL, &unk_2004, *((unsigned int *)v10 + 1));\n __strcat_chk(v17, v15, 50LL);\n __strcat_chk(v19, v16, 50LL);\n if ( v10 == &v13 )\n break;\n __strcat_chk(v17, &unk_2007, 50LL);\n __strcat_chk(v19, &unk_2007, 50LL);\n v10 += 8;\n }\n while ( v10 != &v14 );\n __sprintf_chk(&res_1, 2LL, 100LL, \"[(%s), (%s)]\", v17);\n return &res_1;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 0E8h\nmov rax, fs:28h\nmov [rsp+118h+var_40], rax\nxor eax, eax\ntest esi, esi\njle short loc_1272\nmov r8d, edx\nmovsxd r9, edx\nlea rcx, [rdi+r9*8]\nmovsxd rsi, esi\nlea rax, [r9+rsi*2]\nlea r10, [rdi+rax*8]\nneg r9\nshl r9, 3\nmov edi, 0\nlea r11, [rsp+118h+var_108]\njmp short loc_126B\nloc_123D:\nlea rax, [rcx+r9]\nmovsxd rdx, edi\nlea rdx, [r11+rdx*8]\nloc_1248:\nmov esi, [rax]\nmov [rdx], esi\nmov esi, [rax+4]\nmov [rdx+4], esi\nadd rax, 8\nadd rdx, 8\ncmp rax, rcx\njnz short loc_1248\nadd edi, r8d\nloc_1262:\nadd rcx, 10h\ncmp rcx, r10\njz short loc_1272\nloc_126B:\ntest r8d, r8d\njg short loc_123D\njmp short loc_1262\nloc_1272:\nmov [rsp+118h+var_B8], 0\nmov [rsp+118h+var_B0], 0\nmov [rsp+118h+var_A8], 0\nmov [rsp+118h+var_A0], 0\nmov [rsp+118h+var_98], 0\nmov [rsp+118h+var_90], 0\nmov [rsp+118h+var_88], 0\nmov [rsp+118h+var_78], 0\nmov [rsp+118h+var_70], 0\nmov [rsp+118h+var_68], 0\nmov [rsp+118h+var_60], 0\nmov [rsp+118h+var_58], 0\nmov [rsp+118h+var_50], 0\nmov [rsp+118h+var_48], 0\nlea rbx, [rsp+118h+var_108]\nlea r15, [rsp+118h+var_E0]\nlea rax, [rsp+118h+var_D8]\nmov [rsp+118h+var_110], rax\nlea r13, [rsp+118h+var_CC]\nlea r12, unk_2004\nlea rbp, [rsp+118h+var_C2]\nlea r14, unk_2007\njmp short loc_136D\nloc_1338:\nlea rdi, [rsp+118h+var_B8]\nmov edx, 32h ; '2'\nmov rsi, r14\ncall ___strcat_chk\nlea rdi, [rsp+118h+var_78]\nmov edx, 32h ; '2'\nmov rsi, r14\ncall ___strcat_chk\nadd rbx, 8\nmov rax, [rsp+118h+var_110]\ncmp rbx, rax\njz short loc_13D8\nloc_136D:\nmov r8d, [rbx]\nmov rcx, r12\nmov edx, 0Ah\nmov esi, 2\nmov rdi, r13\nmov eax, 0\ncall ___sprintf_chk\nmov r8d, [rbx+4]\nmov rcx, r12\nmov edx, 0Ah\nmov esi, 2\nmov rdi, rbp\nmov eax, 0\ncall ___sprintf_chk\nlea rdi, [rsp+118h+var_B8]\nmov edx, 32h ; '2'\nmov rsi, r13\ncall ___strcat_chk\nlea rdi, [rsp+118h+var_78]\nmov edx, 32h ; '2'\nmov rsi, rbp\ncall ___strcat_chk\ncmp rbx, r15\njnz loc_1338\nloc_13D8:\nlea r9, [rsp+118h+var_78]\nlea r8, [rsp+118h+var_B8]\nlea rcx, aSS; \"[(%s), (%s)]\"\nmov edx, 64h ; 'd'\nmov esi, 2\nlea rbx, unk_4040\nmov rdi, rbx\nmov eax, 0\ncall ___sprintf_chk\nmov rax, [rsp+118h+var_40]\nsub rax, fs:28h\njnz short loc_1432\nmov rax, rbx\nadd rsp, 0E8h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1432:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "void *__fastcall sub_11E9(__int64 a1, int a2, int a3)\n{\n _DWORD *v4; // rcx\n _DWORD *v5; // r10\n __int64 v6; // r9\n int v7; // edi\n _DWORD *v8; // rax\n _DWORD *v9; // rdx\n char *v10; // rbx\n _QWORD v12[5]; // [rsp+10h] [rbp-108h] BYREF\n char v13; // [rsp+38h] [rbp-E0h] BYREF\n char v14; // [rsp+40h] [rbp-D8h] BYREF\n _BYTE v15[10]; // [rsp+4Ch] [rbp-CCh] BYREF\n _BYTE v16[10]; // [rsp+56h] [rbp-C2h] BYREF\n _QWORD v17[6]; // [rsp+60h] [rbp-B8h] BYREF\n __int16 v18; // [rsp+90h] [rbp-88h]\n _QWORD v19[6]; // [rsp+A0h] [rbp-78h] BYREF\n __int16 v20; // [rsp+D0h] [rbp-48h]\n unsigned __int64 v21; // [rsp+D8h] [rbp-40h]\n\n v21 = __readfsqword(0x28u);\n if ( a2 > 0 )\n {\n v4 = (_DWORD *)(a1 + 8LL * a3);\n v5 = (_DWORD *)(a1 + 8 * (a3 + 2LL * a2));\n v6 = 0x3FFFFFFFFFFFFFFELL * a3;\n v7 = 0;\n do\n {\n if ( a3 > 0 )\n {\n v8 = &v4[v6];\n v9 = &v12[v7];\n do\n {\n *v9 = *v8;\n v9[1] = v8[1];\n v8 += 2;\n v9 += 2;\n }\n while ( v8 != v4 );\n v7 += a3;\n }\n v4 += 4;\n }\n while ( v4 != v5 );\n }\n memset(v17, 0, sizeof(v17));\n v18 = 0;\n memset(v19, 0, sizeof(v19));\n v20 = 0;\n v10 = (char *)v12;\n do\n {\n __sprintf_chk(v15, 2LL, 10LL, &unk_2004, *(unsigned int *)v10);\n __sprintf_chk(v16, 2LL, 10LL, &unk_2004, *((unsigned int *)v10 + 1));\n __strcat_chk(v17, v15, 50LL);\n __strcat_chk(v19, v16, 50LL);\n if ( v10 == &v13 )\n break;\n __strcat_chk(v17, &unk_2007, 50LL);\n __strcat_chk(v19, &unk_2007, 50LL);\n v10 += 8;\n }\n while ( v10 != &v14 );\n __sprintf_chk(&unk_4040, 2LL, 100LL, \"[(%s), (%s)]\", v17);\n return &unk_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_11E9(long long a1, int a2, int a3) {\n uint32_t *v4;\n uint32_t *v5;\n long long v6;\n int v7;\n uint32_t *v8;\n uint32_t *v9;\n char *v10;\n uint64_t v12[5];\n char v13;\n char v14;\n uint8_t v15[10];\n uint8_t v16[10];\n uint64_t v17[6];\n short v18;\n uint64_t v19[6];\n short v20;\n unsigned long long v21;\n v21 = __readfsqword(40u);\n if (a2 > 0) {\n v4 = (uint32_t *)(a1 + 8LL * a3);\n v5 = (uint32_t *)(a1 + 8 * (a3 + 2LL * a2));\n v6 = 4611686018427387902LL * a3;\n v7 = 0;\n do {\n if (a3 > 0) {\n v8 = &v4[v6];\n v9 = &v12[v7];\n do {\n *v9 = *v8;\n v9[1] = v8[1];\n v8 += 2;\n v9 += 2;\n } while (v8 != v4);\n v7 += a3;\n }\n v4 += 4;\n } while (v4 != v5);\n }\n memset(v17, 0, sizeof(v17));\n v18 = 0;\n memset(v19, 0, sizeof(v19));\n v20 = 0;\n v10 = (char *)v12;\n do {\n __sprintf_chk(v15, 2LL, 10LL, &unk_2004, *(unsigned int *)v10);\n __sprintf_chk(v16, 2LL, 10LL, &unk_2004, *((unsigned int *)v10 + 1));\n __strcat_chk(v17, v15, 50LL);\n __strcat_chk(v19, v16, 50LL);\n if (v10 == &v13) break;\n __strcat_chk(v17, &unk_2007, 50LL);\n __strcat_chk(v19, &unk_2007, 50LL);\n v10 += 8;\n } while (v10 != &v14);\n __sprintf_chk(&unk_4040, 2LL, 100LL, \"[(%s), (%s)]\", v17);\n return &unk_4040;\n}", + "ida_pseudo_norm": "void *func0(long long a1, int a2, int a3) {\n uint32_t *v4;\n uint32_t *v5;\n long long v6;\n int v7;\n uint32_t *v8;\n uint32_t *v9;\n char *v10;\n uint64_t v12[5];\n char v13;\n char v14;\n uint8_t v15[10];\n uint8_t v16[10];\n uint64_t v17[6];\n short v18;\n uint64_t v19[6];\n short v20;\n unsigned long long v21;\n v21 = __readfsqword(40u);\n if (a2 > 0) {\n v4 = (uint32_t *)(a1 + 8LL * a3);\n v5 = (uint32_t *)(a1 + 8 * (a3 + 2LL * a2));\n v6 = 4611686018427387902LL * a3;\n v7 = 0;\n do {\n if (a3 > 0) {\n v8 = &v4[v6];\n v9 = &v12[v7];\n do {\n *v9 = *v8;\n v9[1] = v8[1];\n v8 += 2;\n v9 += 2;\n } while (v8 != v4);\n v7 += a3;\n }\n v4 += 4;\n } while (v4 != v5);\n }\n memset(v17, 0, sizeof(v17));\n v18 = 0;\n memset(v19, 0, sizeof(v19));\n v20 = 0;\n v10 = (char *)v12;\n do {\n __sprintf_chk(v15, 2LL, 10LL, &unk_2004, *(unsigned int *)v10);\n __sprintf_chk(v16, 2LL, 10LL, &unk_2004, *((unsigned int *)v10 + 1));\n __strcat_chk(v17, v15, 50LL);\n __strcat_chk(v19, v16, 50LL);\n if (v10 == &v13) break;\n __strcat_chk(v17, &unk_2007, 50LL);\n __strcat_chk(v19, &unk_2007, 50LL);\n v10 += 8;\n } while (v10 != &v14);\n __sprintf_chk(&res_1, 2LL, 100LL, \"[(%s), (%s)]\", v17);\n return &res_1;\n}" + }, + { + "index": 652, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(int test_list[3][2][2], int rows, int cols, int pairs) {\n static char res[100];\n int flat_list[6][2];\n int f = 0;\n for (int i = 0; i < rows; i++) {\n for (int j = 0; j < cols; j++) {\n flat_list[f][0] = test_list[i][j][0];\n flat_list[f][1] = test_list[i][j][1];\n f++;\n }\n }\n char temp1[50] = \"\";\n char temp2[50] = \"\";\n char part1[10], part2[10];\n for (int k = 0; k < 6; k++) {\n sprintf(part1, \"%d\", flat_list[k][0]);\n sprintf(part2, \"%d\", flat_list[k][1]);\n strcat(temp1, part1);\n strcat(temp2, part2);\n if (k != 5) {\n strcat(temp1, \", \");\n strcat(temp2, \", \");\n }\n }\n sprintf(res, \"[(%s), (%s)]\", temp1, temp2);\n return res;\n}", + "test": "int main() {\n\n int test1[3][2][2] = {{{4, 5}, {7, 8}}, {{10, 13}, {18, 17}}, {{0, 4}, {10, 1}}};\n\n int test2[3][2][2] = {{{5, 6}, {8, 9}}, {{11, 14}, {19, 18}}, {{1, 5}, {11, 2}}};\n\n int test3[3][2][2] = {{{6, 7}, {9, 10}}, {{12, 15}, {20, 21}}, {{23, 7}, {15, 8}}};\n\n\n\n assert(strcmp(func0(test1, 3, 2, 2), \"[(4, 7, 10, 18, 0, 10), (5, 8, 13, 17, 4, 1)]\") == 0);\n\n assert(strcmp(func0(test2, 3, 2, 2), \"[(5, 8, 11, 19, 1, 11), (6, 9, 14, 18, 5, 2)]\") == 0);\n\n assert(strcmp(func0(test3, 3, 2, 2), \"[(6, 9, 12, 20, 23, 15), (7, 10, 15, 21, 7, 8)]\") == 0);\n\n\n\n printf(\"All tests passed!\\n\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0xe8,%rsp\nmov %fs:0x28,%rax\nmov %rax,0xd8(%rsp)\nxor %eax,%eax\nlea 0x10(%rsp),%rbx\ntest %esi,%esi\njle 14aa \nlea -0x1(%rsi),%eax\nxor %r8d,%r8d\nlea 0x10(%rsp),%rbx\nshl $0x4,%rax\nlea 0x10(%rdi,%rax,1),%r9\nnopl (%rax)\ntest %edx,%edx\njle 14a1 \nmovslq %r8d,%rax\nlea (%rbx,%rax,8),%rcx\nxor %eax,%eax\nmov (%rdi,%rax,8),%esi\nadd $0x8,%rcx\nmov %esi,-0x8(%rcx)\nmov 0x4(%rdi,%rax,8),%esi\nadd $0x1,%rax\nmov %esi,-0x4(%rcx)\ncmp %eax,%edx\njg 1485 \nadd %edx,%r8d\nadd $0x10,%rdi\ncmp %r9,%rdi\njne 1478 \nmov 0x10(%rsp),%r8d\nxor %eax,%eax\nxor %edx,%edx\nlea 0x4c(%rsp),%r13\npxor %xmm0,%xmm0\nmov $0x1,%esi\nmov %r13,%rdi\nmov %ax,0x90(%rsp)\nmov %dx,0xd0(%rsp)\nlea 0xb29(%rip),%rcx\nmov $0xa,%edx\nxor %eax,%eax\nmovaps %xmm0,0x60(%rsp)\nlea 0x56(%rsp),%r12\nlea 0x60(%rsp),%r15\nmovaps %xmm0,0x70(%rsp)\nlea 0xa0(%rsp),%rbp\nlea 0xb0f(%rip),%r14\nmovaps %xmm0,0x80(%rsp)\nmovaps %xmm0,0xa0(%rsp)\nmovaps %xmm0,0xb0(%rsp)\nmovaps %xmm0,0xc0(%rsp)\ncallq 10d0 <__sprintf_chk@plt>\nmov 0x14(%rsp),%r8d\nmov %r12,%rdi\nxor %eax,%eax\nlea 0xac9(%rip),%rcx\nmov $0xa,%edx\nmov $0x1,%esi\ncallq 10d0 <__sprintf_chk@plt>\nmov $0x32,%edx\nmov %r13,%rsi\nmov %r15,%rdi\ncallq 1090 <__strcat_chk@plt>\nmov $0x32,%edx\nmov %r12,%rsi\nmov %rbp,%rdi\ncallq 1090 <__strcat_chk@plt>\nlea 0x38(%rsp),%rax\nmov %rax,0x8(%rsp)\nmov $0x32,%edx\nmov %r14,%rsi\nmov %r15,%rdi\nadd $0x8,%rbx\ncallq 1090 <__strcat_chk@plt>\nmov $0x32,%edx\nmov %r14,%rsi\nmov %rbp,%rdi\ncallq 1090 <__strcat_chk@plt>\nmov (%rbx),%r8d\nmov $0xa,%edx\nmov %r13,%rdi\nlea 0xa5a(%rip),%rcx\nmov $0x1,%esi\nxor %eax,%eax\ncallq 10d0 <__sprintf_chk@plt>\nmov 0x4(%rbx),%r8d\nmov $0xa,%edx\nxor %eax,%eax\nlea 0xa3c(%rip),%rcx\nmov $0x1,%esi\nmov %r12,%rdi\ncallq 10d0 <__sprintf_chk@plt>\nmov $0x32,%edx\nmov %r13,%rsi\nmov %r15,%rdi\ncallq 1090 <__strcat_chk@plt>\nmov $0x32,%edx\nmov %r12,%rsi\nmov %rbp,%rdi\ncallq 1090 <__strcat_chk@plt>\ncmp 0x8(%rsp),%rbx\njne 1574 \nxor %eax,%eax\nmov %rbp,%r9\nmov %r15,%r8\nmov $0x64,%edx\nlea 0x9f3(%rip),%rcx\nmov $0x1,%esi\nlea 0x2a20(%rip),%rdi\ncallq 10d0 <__sprintf_chk@plt>\nmov 0xd8(%rsp),%rax\nxor %fs:0x28,%rax\njne 1651 \nadd $0xe8,%rsp\nlea 0x29fa(%rip),%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\ncallq 10b0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 0F8h\nmov rax, fs:28h\nmov [rsp+128h+var_40], rax\nxor eax, eax\ntest esi, esi\njle short loc_1428\nmovsxd rsi, esi\nshl rsi, 4\nlea r8, [rdi+rsi]\nloc_1417:\ntest edx, edx\njg loc_1570\nadd rdi, 10h\ncmp rdi, r8\njnz short loc_1417\nloc_1428:\nlea rbx, [rsp+128h+var_108]\nloc_142D:\nxor eax, eax\npxor xmm0, xmm0\nlea r15, [rsp+128h+var_CC]\nxor edx, edx\nmov [rsp+128h+var_88], ax\nlea rax, [rsp+128h+var_D8]\nlea r14, unk_2004\nmov [rsp+128h+var_110], rax\nlea rax, [rsp+128h+var_C2]\nlea rbp, [rsp+128h+s]\nmov [rsp+128h+var_48], dx\nlea r12, [rsp+128h+var_78]\nmov [rsp+128h+var_120], rax\nmovaps xmmword ptr [rsp+128h+s], xmm0\nmovaps [rsp+128h+var_A8], xmm0\nmovaps [rsp+128h+var_98], xmm0\nmovaps xmmword ptr [rsp+128h+var_78], xmm0\nmovaps [rsp+128h+var_68], xmm0\nmovaps [rsp+128h+var_58], xmm0\nloc_149F:\nmov r8d, [rbx]\nmov rcx, r14\nmov edx, 0Ah\nmov esi, 2\nmov rdi, r15\nxor eax, eax\nadd rbx, 8\ncall ___sprintf_chk\nmov r8d, [rbx-4]\nmov rdi, [rsp+128h+var_120]\nxor eax, eax\nmov rcx, r14\nmov edx, 0Ah\nmov esi, 2\ncall ___sprintf_chk\nmov rdi, rbp; s\ncall _strlen\nmov edx, 32h ; '2'\nmov rsi, r15\nlea rdi, [rbp+rax+0]\ncall ___stpcpy_chk\nmov rdi, r12; s\nmov r13, rax\ncall _strlen\nmov rsi, [rsp+128h+var_120]\nmov edx, 32h ; '2'\nlea rdi, [r12+rax]\ncall ___stpcpy_chk\nmov r8, rax\nmov rax, [rsp+128h+var_110]\ncmp rbx, rax\njz loc_15B0\nmov rcx, rbp\nmov rdi, r13\nmov edx, 3\nmov [rsp+128h+var_118], r8\nsub rcx, r13\nlea rsi, asc_2014; \", \"\nadd rcx, 32h ; '2'\ncall ___memcpy_chk\nmov r8, [rsp+128h+var_118]\nmov rcx, r12\nmov edx, 3\nlea rsi, asc_2014; \", \"\nsub rcx, r8\nmov rdi, r8\nadd rcx, 32h ; '2'\ncall ___memcpy_chk\njmp loc_149F\nloc_1570:\nxor r9d, r9d\nlea rbx, [rsp+128h+var_108]\nnop dword ptr [rax+rax+00000000h]\nloc_1580:\nmovsxd rax, r9d\nlea rsi, [rbx+rax*8]\nxor eax, eax\nloc_1589:\nmov rcx, [rdi+rax*8]\nmov [rsi+rax*8], rcx\nadd rax, 1\ncmp eax, edx\njb short loc_1589\nadd rdi, 10h\nadd r9d, edx\ncmp rdi, r8\njnz short loc_1580\njmp loc_142D\nloc_15B0:\nlea rbx, res_1\nxor eax, eax\nmov r9, r12\nmov r8, rbp\nlea rcx, aSS; \"[(%s), (%s)]\"\nmov edx, 64h ; 'd'\nmov esi, 2\nmov rdi, rbx\ncall ___sprintf_chk\nmov rax, [rsp+128h+var_40]\nsub rax, fs:28h\njnz short loc_1600\nadd rsp, 0F8h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1600:\ncall ___stack_chk_fail", + "ida_pseudo": "void *__fastcall func0(__int64 a1, int a2, int a3)\n{\n __int64 v3; // r8\n char *v4; // rbx\n __int64 v5; // r8\n size_t v6; // rax\n __int64 v7; // r13\n size_t v8; // rax\n __int64 v9; // r8\n int v10; // r9d\n __int64 v11; // rax\n __int64 v13; // [rsp+10h] [rbp-118h]\n _QWORD v14[6]; // [rsp+20h] [rbp-108h] BYREF\n char v15; // [rsp+50h] [rbp-D8h] BYREF\n _BYTE v16[10]; // [rsp+5Ch] [rbp-CCh] BYREF\n char v17[10]; // [rsp+66h] [rbp-C2h] BYREF\n char s[16]; // [rsp+70h] [rbp-B8h] BYREF\n __int128 v19; // [rsp+80h] [rbp-A8h]\n __int128 v20; // [rsp+90h] [rbp-98h]\n __int16 v21; // [rsp+A0h] [rbp-88h]\n char v22[16]; // [rsp+B0h] [rbp-78h] BYREF\n __int128 v23; // [rsp+C0h] [rbp-68h]\n __int128 v24; // [rsp+D0h] [rbp-58h]\n __int16 v25; // [rsp+E0h] [rbp-48h]\n unsigned __int64 v26; // [rsp+E8h] [rbp-40h]\n\n v26 = __readfsqword(0x28u);\n if ( a2 <= 0 )\n {\nLABEL_5:\n v4 = (char *)v14;\n }\n else\n {\n v3 = a1 + 16LL * a2;\n while ( a3 <= 0 )\n {\n a1 += 16LL;\n if ( a1 == v3 )\n goto LABEL_5;\n }\n v10 = 0;\n v4 = (char *)v14;\n do\n {\n v11 = 0LL;\n do\n {\n v14[v10 + v11] = *(_QWORD *)(a1 + 8 * v11);\n ++v11;\n }\n while ( (unsigned int)v11 < a3 );\n a1 += 16LL;\n v10 += a3;\n }\n while ( a1 != v3 );\n }\n v21 = 0;\n v25 = 0;\n *(_OWORD *)s = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n *(_OWORD *)v22 = 0LL;\n v23 = 0LL;\n v24 = 0LL;\n while ( 1 )\n {\n v5 = *(unsigned int *)v4;\n v4 += 8;\n __sprintf_chk(v16, 2LL, 10LL, &unk_2004, v5);\n __sprintf_chk(v17, 2LL, 10LL, &unk_2004, *((unsigned int *)v4 - 1));\n v6 = strlen(s);\n v7 = __stpcpy_chk(&s[v6], v16, 50LL);\n v8 = strlen(v22);\n v9 = __stpcpy_chk(&v22[v8], v17, 50LL);\n if ( v4 == &v15 )\n break;\n v13 = v9;\n __memcpy_chk(v7, \", \", 3LL, &s[-v7 + 50]);\n __memcpy_chk(v13, \", \", 3LL, &v22[-v13 + 50]);\n }\n __sprintf_chk(&res_1, 2LL, 100LL, \"[(%s), (%s)]\", s);\n return &res_1;\n}", + "ida_strip_asm": "sub_13E0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 0F8h\nmov rax, fs:28h\nmov [rsp+128h+var_40], rax\nxor eax, eax\ntest esi, esi\njle short loc_1428\nmovsxd rsi, esi\nshl rsi, 4\nlea r8, [rdi+rsi]\nloc_1417:\ntest edx, edx\njg loc_1570\nadd rdi, 10h\ncmp rdi, r8\njnz short loc_1417\nloc_1428:\nlea rbx, [rsp+128h+var_108]\nloc_142D:\nxor eax, eax\npxor xmm0, xmm0\nlea r15, [rsp+128h+var_CC]\nxor edx, edx\nmov [rsp+128h+var_88], ax\nlea rax, [rsp+128h+var_D8]\nlea r14, unk_2004\nmov [rsp+128h+var_110], rax\nlea rax, [rsp+128h+var_C2]\nlea rbp, [rsp+128h+s]\nmov [rsp+128h+var_48], dx\nlea r12, [rsp+128h+var_78]\nmov [rsp+128h+var_120], rax\nmovaps xmmword ptr [rsp+128h+s], xmm0\nmovaps [rsp+128h+var_A8], xmm0\nmovaps [rsp+128h+var_98], xmm0\nmovaps xmmword ptr [rsp+128h+var_78], xmm0\nmovaps [rsp+128h+var_68], xmm0\nmovaps [rsp+128h+var_58], xmm0\nloc_149F:\nmov r8d, [rbx]\nmov rcx, r14\nmov edx, 0Ah\nmov esi, 2\nmov rdi, r15\nxor eax, eax\nadd rbx, 8\ncall ___sprintf_chk\nmov r8d, [rbx-4]\nmov rdi, [rsp+128h+var_120]\nxor eax, eax\nmov rcx, r14\nmov edx, 0Ah\nmov esi, 2\ncall ___sprintf_chk\nmov rdi, rbp; s\ncall _strlen\nmov edx, 32h ; '2'\nmov rsi, r15\nlea rdi, [rbp+rax+0]\ncall ___stpcpy_chk\nmov rdi, r12; s\nmov r13, rax\ncall _strlen\nmov rsi, [rsp+128h+var_120]\nmov edx, 32h ; '2'\nlea rdi, [r12+rax]\ncall ___stpcpy_chk\nmov r8, rax\nmov rax, [rsp+128h+var_110]\ncmp rbx, rax\njz loc_15B0\nmov rcx, rbp\nmov rdi, r13\nmov edx, 3\nmov [rsp+128h+var_118], r8\nsub rcx, r13\nlea rsi, asc_2014; \", \"\nadd rcx, 32h ; '2'\ncall ___memcpy_chk\nmov r8, [rsp+128h+var_118]\nmov rcx, r12\nmov edx, 3\nlea rsi, asc_2014; \", \"\nsub rcx, r8\nmov rdi, r8\nadd rcx, 32h ; '2'\ncall ___memcpy_chk\njmp loc_149F\nloc_1570:\nxor r9d, r9d\nlea rbx, [rsp+128h+var_108]\nnop dword ptr [rax+rax+00000000h]\nloc_1580:\nmovsxd rax, r9d\nlea rsi, [rbx+rax*8]\nxor eax, eax\nloc_1589:\nmov rcx, [rdi+rax*8]\nmov [rsi+rax*8], rcx\nadd rax, 1\ncmp eax, edx\njb short loc_1589\nadd rdi, 10h\nadd r9d, edx\ncmp rdi, r8\njnz short loc_1580\njmp loc_142D\nloc_15B0:\nlea rbx, unk_4040\nxor eax, eax\nmov r9, r12\nmov r8, rbp\nlea rcx, aSS; \"[(%s), (%s)]\"\nmov edx, 64h ; 'd'\nmov esi, 2\nmov rdi, rbx\ncall ___sprintf_chk\nmov rax, [rsp+128h+var_40]\nsub rax, fs:28h\njnz short loc_1600\nadd rsp, 0F8h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1600:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "void *__fastcall sub_13E0(__int64 a1, int a2, int a3)\n{\n __int64 v3; // r8\n char *v4; // rbx\n __int64 v5; // r8\n size_t v6; // rax\n __int64 v7; // r13\n size_t v8; // rax\n __int64 v9; // r8\n int v10; // r9d\n __int64 v11; // rax\n __int64 v13; // [rsp+10h] [rbp-118h]\n _QWORD v14[6]; // [rsp+20h] [rbp-108h] BYREF\n char v15; // [rsp+50h] [rbp-D8h] BYREF\n _BYTE v16[10]; // [rsp+5Ch] [rbp-CCh] BYREF\n char v17[10]; // [rsp+66h] [rbp-C2h] BYREF\n char s[16]; // [rsp+70h] [rbp-B8h] BYREF\n __int128 v19; // [rsp+80h] [rbp-A8h]\n __int128 v20; // [rsp+90h] [rbp-98h]\n __int16 v21; // [rsp+A0h] [rbp-88h]\n char v22[16]; // [rsp+B0h] [rbp-78h] BYREF\n __int128 v23; // [rsp+C0h] [rbp-68h]\n __int128 v24; // [rsp+D0h] [rbp-58h]\n __int16 v25; // [rsp+E0h] [rbp-48h]\n unsigned __int64 v26; // [rsp+E8h] [rbp-40h]\n\n v26 = __readfsqword(0x28u);\n if ( a2 <= 0 )\n {\nLABEL_5:\n v4 = (char *)v14;\n }\n else\n {\n v3 = a1 + 16LL * a2;\n while ( a3 <= 0 )\n {\n a1 += 16LL;\n if ( a1 == v3 )\n goto LABEL_5;\n }\n v10 = 0;\n v4 = (char *)v14;\n do\n {\n v11 = 0LL;\n do\n {\n v14[v10 + v11] = *(_QWORD *)(a1 + 8 * v11);\n ++v11;\n }\n while ( (unsigned int)v11 < a3 );\n a1 += 16LL;\n v10 += a3;\n }\n while ( a1 != v3 );\n }\n v21 = 0;\n v25 = 0;\n *(_OWORD *)s = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n *(_OWORD *)v22 = 0LL;\n v23 = 0LL;\n v24 = 0LL;\n while ( 1 )\n {\n v5 = *(unsigned int *)v4;\n v4 += 8;\n __sprintf_chk(v16, 2LL, 10LL, &unk_2004, v5);\n __sprintf_chk(v17, 2LL, 10LL, &unk_2004, *((unsigned int *)v4 - 1));\n v6 = strlen(s);\n v7 = __stpcpy_chk(&s[v6], v16, 50LL);\n v8 = strlen(v22);\n v9 = __stpcpy_chk(&v22[v8], v17, 50LL);\n if ( v4 == &v15 )\n break;\n v13 = v9;\n __memcpy_chk(v7, \", \", 3LL, &s[-v7 + 50]);\n __memcpy_chk(v13, \", \", 3LL, &v22[-v13 + 50]);\n }\n __sprintf_chk(&unk_4040, 2LL, 100LL, \"[(%s), (%s)]\", s);\n return &unk_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_13E0(long long a1, int a2, int a3) {\n long long v3;\n char *v4;\n long long v5;\n unsigned int v6;\n long long v7;\n unsigned int v8;\n long long v9;\n int v10;\n long long v11;\n long long v13;\n uint64_t v14[6];\n char v15;\n uint8_t v16[10];\n char v17[10];\n char s[16];\n __int128 v19;\n __int128 v20;\n short v21;\n char v22[16];\n __int128 v23;\n __int128 v24;\n short v25;\n unsigned long long v26;\n v26 = __readfsqword(40u);\n if (a2 <= 0) {\n LABEL_5:\n v4 = (char *)v14;\n } else {\n v3 = a1 + 16LL * a2;\n while (a3 <= 0) {\n a1 += 16LL;\n if (a1 == v3) goto LABEL_5;\n }\n v10 = 0;\n v4 = (char *)v14;\n do {\n v11 = 0LL;\n do {\n v14[v10 + v11] = *(uint64_t *)(a1 + 8 * v11);\n ++v11;\n } while ((unsigned int)v11 < a3);\n a1 += 16LL;\n v10 += a3;\n } while (a1 != v3);\n }\n v21 = 0;\n v25 = 0;\n *(long double *)s = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n *(long double *)v22 = 0LL;\n v23 = 0LL;\n v24 = 0LL;\n while (1) {\n v5 = *(unsigned int *)v4;\n v4 += 8;\n __sprintf_chk(v16, 2LL, 10LL, &unk_2004, v5);\n __sprintf_chk(v17, 2LL, 10LL, &unk_2004, *((unsigned int *)v4 - 1));\n v6 = strlen(s);\n v7 = __stpcpy_chk(&s[v6], v16, 50LL);\n v8 = strlen(v22);\n v9 = __stpcpy_chk(&v22[v8], v17, 50LL);\n if (v4 == &v15) break;\n v13 = v9;\n __memcpy_chk(v7, \", \", 3LL, &s[-v7 + 50]);\n __memcpy_chk(v13, \", \", 3LL, &v22[-v13 + 50]);\n }\n __sprintf_chk(&unk_4040, 2LL, 100LL, \"[(%s), (%s)]\", s);\n return &unk_4040;\n}", + "ida_pseudo_norm": "void *func0(long long a1, int a2, int a3) {\n long long v3;\n char *v4;\n long long v5;\n unsigned int v6;\n long long v7;\n unsigned int v8;\n long long v9;\n int v10;\n long long v11;\n long long v13;\n uint64_t v14[6];\n char v15;\n uint8_t v16[10];\n char v17[10];\n char s[16];\n __int128 v19;\n __int128 v20;\n short v21;\n char v22[16];\n __int128 v23;\n __int128 v24;\n short v25;\n unsigned long long v26;\n v26 = __readfsqword(40u);\n if (a2 <= 0) {\n LABEL_5:\n v4 = (char *)v14;\n } else {\n v3 = a1 + 16LL * a2;\n while (a3 <= 0) {\n a1 += 16LL;\n if (a1 == v3) goto LABEL_5;\n }\n v10 = 0;\n v4 = (char *)v14;\n do {\n v11 = 0LL;\n do {\n v14[v10 + v11] = *(uint64_t *)(a1 + 8 * v11);\n ++v11;\n } while ((unsigned int)v11 < a3);\n a1 += 16LL;\n v10 += a3;\n } while (a1 != v3);\n }\n v21 = 0;\n v25 = 0;\n *(long double *)s = 0LL;\n v19 = 0LL;\n v20 = 0LL;\n *(long double *)v22 = 0LL;\n v23 = 0LL;\n v24 = 0LL;\n while (1) {\n v5 = *(unsigned int *)v4;\n v4 += 8;\n __sprintf_chk(v16, 2LL, 10LL, &unk_2004, v5);\n __sprintf_chk(v17, 2LL, 10LL, &unk_2004, *((unsigned int *)v4 - 1));\n v6 = strlen(s);\n v7 = __stpcpy_chk(&s[v6], v16, 50LL);\n v8 = strlen(v22);\n v9 = __stpcpy_chk(&v22[v8], v17, 50LL);\n if (v4 == &v15) break;\n v13 = v9;\n __memcpy_chk(v7, \", \", 3LL, &s[-v7 + 50]);\n __memcpy_chk(v13, \", \", 3LL, &v22[-v13 + 50]);\n }\n __sprintf_chk(&res_1, 2LL, 100LL, \"[(%s), (%s)]\", s);\n return &res_1;\n}" + }, + { + "index": 652, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(int test_list[3][2][2], int rows, int cols, int pairs) {\n static char res[100];\n int flat_list[6][2];\n int f = 0;\n for (int i = 0; i < rows; i++) {\n for (int j = 0; j < cols; j++) {\n flat_list[f][0] = test_list[i][j][0];\n flat_list[f][1] = test_list[i][j][1];\n f++;\n }\n }\n char temp1[50] = \"\";\n char temp2[50] = \"\";\n char part1[10], part2[10];\n for (int k = 0; k < 6; k++) {\n sprintf(part1, \"%d\", flat_list[k][0]);\n sprintf(part2, \"%d\", flat_list[k][1]);\n strcat(temp1, part1);\n strcat(temp2, part2);\n if (k != 5) {\n strcat(temp1, \", \");\n strcat(temp2, \", \");\n }\n }\n sprintf(res, \"[(%s), (%s)]\", temp1, temp2);\n return res;\n}", + "test": "int main() {\n\n int test1[3][2][2] = {{{4, 5}, {7, 8}}, {{10, 13}, {18, 17}}, {{0, 4}, {10, 1}}};\n\n int test2[3][2][2] = {{{5, 6}, {8, 9}}, {{11, 14}, {19, 18}}, {{1, 5}, {11, 2}}};\n\n int test3[3][2][2] = {{{6, 7}, {9, 10}}, {{12, 15}, {20, 21}}, {{23, 7}, {15, 8}}};\n\n\n\n assert(strcmp(func0(test1, 3, 2, 2), \"[(4, 7, 10, 18, 0, 10), (5, 8, 13, 17, 4, 1)]\") == 0);\n\n assert(strcmp(func0(test2, 3, 2, 2), \"[(5, 8, 11, 19, 1, 11), (6, 9, 14, 18, 5, 2)]\") == 0);\n\n assert(strcmp(func0(test3, 3, 2, 2), \"[(6, 9, 12, 20, 23, 15), (7, 10, 15, 21, 7, 8)]\") == 0);\n\n\n\n printf(\"All tests passed!\\n\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0xe8,%rsp\nmov %fs:0x28,%rax\nmov %rax,0xd8(%rsp)\nxor %eax,%eax\nlea 0x10(%rsp),%rbx\ntest %esi,%esi\njle 1446 \ntest %edx,%edx\njle 1446 \nlea -0x1(%rsi),%eax\nmov %edx,%r10d\nmov %edx,%r9d\nxor %r8d,%r8d\nshl $0x4,%rax\nshr %r10d\nand $0xfffffffe,%r9d\nlea 0x10(%rdi,%rax,1),%r11\nnopl (%rax)\ncmp $0x1,%edx\nje 15f0 \nmovdqu (%rdi),%xmm1\nmovslq %r8d,%rax\nlea (%rbx,%rax,8),%rax\nmovups %xmm1,(%rax)\ncmp $0x1,%r10d\njbe 141d \nmovdqu 0x10(%rdi),%xmm2\nmovups %xmm2,0x10(%rax)\ncmp $0x2,%r10d\nje 141d \nmovdqu 0x20(%rdi),%xmm3\nmovups %xmm3,0x20(%rax)\nlea (%r8,%r9,1),%eax\nmovslq %r9d,%rcx\ncmp %r9d,%edx\nje 143a \nmov (%rdi,%rcx,8),%esi\nmov 0x4(%rdi,%rcx,8),%ecx\ncltq\nmov %esi,0x10(%rsp,%rax,8)\nmov %ecx,0x14(%rsp,%rax,8)\nadd $0x10,%rdi\nadd %edx,%r8d\ncmp %r11,%rdi\njne 13e8 \nmov 0x10(%rsp),%r8d\nxor %eax,%eax\nxor %edx,%edx\nlea 0x4c(%rsp),%r13\npxor %xmm0,%xmm0\nmov $0x1,%esi\nmov %r13,%rdi\nmov %ax,0x90(%rsp)\nmov %dx,0xd0(%rsp)\nlea 0xb8d(%rip),%rcx\nmov $0xa,%edx\nxor %eax,%eax\nmovaps %xmm0,0x60(%rsp)\nlea 0x56(%rsp),%r12\nlea 0x60(%rsp),%r15\nmovaps %xmm0,0x70(%rsp)\nlea 0xa0(%rsp),%rbp\nlea 0xb73(%rip),%r14\nmovaps %xmm0,0x80(%rsp)\nmovaps %xmm0,0xa0(%rsp)\nmovaps %xmm0,0xb0(%rsp)\nmovaps %xmm0,0xc0(%rsp)\ncallq 10d0 <__sprintf_chk@plt>\nmov 0x14(%rsp),%r8d\nmov %r12,%rdi\nxor %eax,%eax\nlea 0xb2d(%rip),%rcx\nmov $0xa,%edx\nmov $0x1,%esi\ncallq 10d0 <__sprintf_chk@plt>\nmov $0x32,%edx\nmov %r13,%rsi\nmov %r15,%rdi\ncallq 1090 <__strcat_chk@plt>\nmov $0x32,%edx\nmov %r12,%rsi\nmov %rbp,%rdi\ncallq 1090 <__strcat_chk@plt>\nlea 0x38(%rsp),%rax\nmov %rax,0x8(%rsp)\nmov $0x32,%edx\nmov %r14,%rsi\nmov %r15,%rdi\nadd $0x8,%rbx\ncallq 1090 <__strcat_chk@plt>\nmov $0x32,%edx\nmov %r14,%rsi\nmov %rbp,%rdi\ncallq 1090 <__strcat_chk@plt>\nmov (%rbx),%r8d\nmov $0xa,%edx\nmov %r13,%rdi\nlea 0xabe(%rip),%rcx\nmov $0x1,%esi\nxor %eax,%eax\ncallq 10d0 <__sprintf_chk@plt>\nmov 0x4(%rbx),%r8d\nmov $0xa,%edx\nxor %eax,%eax\nlea 0xaa0(%rip),%rcx\nmov $0x1,%esi\nmov %r12,%rdi\ncallq 10d0 <__sprintf_chk@plt>\nmov $0x32,%edx\nmov %r13,%rsi\nmov %r15,%rdi\ncallq 1090 <__strcat_chk@plt>\nmov $0x32,%edx\nmov %r12,%rsi\nmov %rbp,%rdi\ncallq 1090 <__strcat_chk@plt>\ncmp 0x8(%rsp),%rbx\njne 1510 \nxor %eax,%eax\nmov %rbp,%r9\nmov %r15,%r8\nmov $0x64,%edx\nlea 0xa57(%rip),%rcx\nmov $0x1,%esi\nlea 0x2a84(%rip),%rdi\ncallq 10d0 <__sprintf_chk@plt>\nmov 0xd8(%rsp),%rax\nxor %fs:0x28,%rax\njne 15fa \nadd $0xe8,%rsp\nlea 0x2a5e(%rip),%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl (%rax)\nmov %r8d,%eax\nxor %ecx,%ecx\njmpq 1429 \ncallq 10b0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 0F8h\nmov rax, fs:28h\nmov [rsp+128h+var_40], rax\nxor eax, eax\nlea rbx, [rsp+128h+var_108]\ntest esi, esi\njle loc_14B0\nmov ecx, edx\nlea rbx, [rsp+128h+var_108]\ntest edx, edx\njle loc_14B0\nmovsxd rsi, esi\nmov r11d, edx\nmov r10d, edx\nxor eax, eax\nlea r9, [rsi+rsi]\nshr r11d, 1\nand r10d, 0FFFFFFFEh\nxor r8d, r8d\njmp short loc_145F\nloc_1440:\nmov esi, r10d\nloc_1443:\nlea rbp, [rax+rsi]\nadd rdx, rsi\nadd rax, 2\nadd r8d, ecx\nmov rbp, [rdi+rbp*8]\nmov [rsp+rdx*8+128h+var_108], rbp\ncmp r9, rax\njz short loc_14B0\nloc_145F:\ncmp ecx, 1\njz loc_1640\nloc_1468:\nmovdqu xmm1, xmmword ptr [rdi+rax*8]\nmovsxd rdx, r8d\nlea rsi, [rbx+rdx*8]\nmovups xmmword ptr [rsi], xmm1\ncmp r11d, 1\njz short loc_1497\nmovdqu xmm2, xmmword ptr [rdi+rax*8+10h]\nmovups xmmword ptr [rsi+10h], xmm2\ncmp r11d, 2\njz short loc_1497\nmovdqu xmm3, xmmword ptr [rdi+rax*8+20h]\nmovups xmmword ptr [rsi+20h], xmm3\nloc_1497:\ncmp ecx, r10d\njnz short loc_1440\nadd rax, 2\nadd r8d, ecx\ncmp r9, rax\njnz short loc_1468\nnop dword ptr [rax+rax+00000000h]\nloc_14B0:\nxor eax, eax\npxor xmm0, xmm0\nlea r15, [rsp+128h+var_CC]\nxor edx, edx\nmov [rsp+128h+var_88], ax\nlea rax, [rsp+128h+var_D8]\nlea r14, unk_2004\nmov [rsp+128h+var_110], rax\nlea rax, [rsp+128h+var_C2]\nlea rbp, [rsp+128h+s]\nmov [rsp+128h+var_48], dx\nlea r12, [rsp+128h+var_78]\nmov [rsp+128h+var_120], rax\nmovaps xmmword ptr [rsp+128h+s], xmm0\nmovaps [rsp+128h+var_A8], xmm0\nmovaps [rsp+128h+var_98], xmm0\nmovaps xmmword ptr [rsp+128h+var_78], xmm0\nmovaps [rsp+128h+var_68], xmm0\nmovaps [rsp+128h+var_58], xmm0\nloc_1522:\nmov r8d, [rbx]\nmov rcx, r14\nmov edx, 0Ah\nmov esi, 2\nmov rdi, r15\nxor eax, eax\nadd rbx, 8\ncall ___sprintf_chk\nmov r8d, [rbx-4]\nmov rdi, [rsp+128h+var_120]\nxor eax, eax\nmov rcx, r14\nmov edx, 0Ah\nmov esi, 2\ncall ___sprintf_chk\nmov rdi, rbp; s\ncall _strlen\nmov edx, 32h ; '2'\nmov rsi, r15\nlea rdi, [rbp+rax+0]\ncall ___stpcpy_chk\nmov rdi, r12; s\nmov r13, rax\ncall _strlen\nmov rsi, [rsp+128h+var_120]\nmov edx, 32h ; '2'\nlea rdi, [r12+rax]\ncall ___stpcpy_chk\nmov r8, rax\nmov rax, [rsp+128h+var_110]\ncmp rbx, rax\njz short loc_15F0\nmov rcx, rbp\nmov rdi, r13\nmov edx, 3\nmov [rsp+128h+var_118], r8\nsub rcx, r13\nlea rsi, asc_2014; \", \"\nadd rcx, 32h ; '2'\ncall ___memcpy_chk\nmov r8, [rsp+128h+var_118]\nmov rcx, r12\nmov edx, 3\nlea rsi, asc_2014; \", \"\nsub rcx, r8\nmov rdi, r8\nadd rcx, 32h ; '2'\ncall ___memcpy_chk\njmp loc_1522\nloc_15F0:\nlea rbx, res_1\nxor eax, eax\nmov r9, r12\nmov r8, rbp\nlea rcx, aSS; \"[(%s), (%s)]\"\nmov edx, 64h ; 'd'\nmov esi, 2\nmov rdi, rbx\ncall ___sprintf_chk\nmov rax, [rsp+128h+var_40]\nsub rax, fs:28h\njnz short loc_164A\nadd rsp, 0F8h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1640:\nxor esi, esi\nmovsxd rdx, r8d\njmp loc_1443\nloc_164A:\ncall ___stack_chk_fail", + "ida_pseudo": "void *__fastcall func0(__int64 a1, int a2, int a3)\n{\n char *v3; // rbx\n __int64 v5; // rax\n __int64 v6; // r9\n unsigned int v7; // r11d\n unsigned int v8; // r10d\n int v9; // r8d\n __int64 v10; // rsi\n __int64 v11; // rbp\n __int64 v12; // rdx\n __m128i *v13; // rsi\n __int64 v14; // r8\n size_t v15; // rax\n __int64 v16; // r13\n size_t v17; // rax\n __int64 v18; // r8\n __int64 v20; // [rsp+10h] [rbp-118h]\n _QWORD v21[6]; // [rsp+20h] [rbp-108h] BYREF\n char v22; // [rsp+50h] [rbp-D8h] BYREF\n _BYTE v23[10]; // [rsp+5Ch] [rbp-CCh] BYREF\n char v24[10]; // [rsp+66h] [rbp-C2h] BYREF\n char s[16]; // [rsp+70h] [rbp-B8h] BYREF\n __int128 v26; // [rsp+80h] [rbp-A8h]\n __int128 v27; // [rsp+90h] [rbp-98h]\n __int16 v28; // [rsp+A0h] [rbp-88h]\n char v29[16]; // [rsp+B0h] [rbp-78h] BYREF\n __int128 v30; // [rsp+C0h] [rbp-68h]\n __int128 v31; // [rsp+D0h] [rbp-58h]\n __int16 v32; // [rsp+E0h] [rbp-48h]\n unsigned __int64 v33; // [rsp+E8h] [rbp-40h]\n\n v33 = __readfsqword(0x28u);\n v3 = (char *)v21;\n if ( a2 > 0 )\n {\n v3 = (char *)v21;\n if ( a3 > 0 )\n {\n v5 = 0LL;\n v6 = 2LL * a2;\n v7 = (unsigned int)a3 >> 1;\n v8 = a3 & 0xFFFFFFFE;\n v9 = 0;\n do\n {\n if ( a3 == 1 )\n {\n v10 = 0LL;\n v12 = v9;\n }\n else\n {\n while ( 1 )\n {\n v12 = v9;\n v13 = (__m128i *)&v21[v9];\n *v13 = _mm_loadu_si128((const __m128i *)(a1 + 8 * v5));\n if ( v7 != 1 )\n {\n v13[1] = _mm_loadu_si128((const __m128i *)(a1 + 8 * v5 + 16));\n if ( v7 != 2 )\n v13[2] = _mm_loadu_si128((const __m128i *)(a1 + 8 * v5 + 32));\n }\n if ( a3 != v8 )\n break;\n v5 += 2LL;\n v9 += a3;\n if ( v6 == v5 )\n goto LABEL_12;\n }\n v10 = v8;\n }\n v11 = v5 + v10;\n v5 += 2LL;\n v9 += a3;\n v21[v10 + v12] = *(_QWORD *)(a1 + 8 * v11);\n }\n while ( v6 != v5 );\n }\n }\nLABEL_12:\n v28 = 0;\n v32 = 0;\n *(_OWORD *)s = 0LL;\n v26 = 0LL;\n v27 = 0LL;\n *(_OWORD *)v29 = 0LL;\n v30 = 0LL;\n v31 = 0LL;\n while ( 1 )\n {\n v14 = *(unsigned int *)v3;\n v3 += 8;\n __sprintf_chk(v23, 2LL, 10LL, &unk_2004, v14);\n __sprintf_chk(v24, 2LL, 10LL, &unk_2004, *((unsigned int *)v3 - 1));\n v15 = strlen(s);\n v16 = __stpcpy_chk(&s[v15], v23, 50LL);\n v17 = strlen(v29);\n v18 = __stpcpy_chk(&v29[v17], v24, 50LL);\n if ( v3 == &v22 )\n break;\n v20 = v18;\n __memcpy_chk(v16, \", \", 3LL, &s[-v16 + 50]);\n __memcpy_chk(v20, \", \", 3LL, &v29[-v20 + 50]);\n }\n __sprintf_chk(&res_1, 2LL, 100LL, \"[(%s), (%s)]\", s);\n return &res_1;\n}", + "ida_strip_asm": "sub_13E0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 0F8h\nmov rax, fs:28h\nmov [rsp+128h+var_40], rax\nxor eax, eax\nlea rbx, [rsp+128h+var_108]\ntest esi, esi\njle loc_14B0\nmov ecx, edx\nlea rbx, [rsp+128h+var_108]\ntest edx, edx\njle loc_14B0\nmovsxd rsi, esi\nmov r11d, edx\nmov r10d, edx\nxor eax, eax\nlea r9, [rsi+rsi]\nshr r11d, 1\nand r10d, 0FFFFFFFEh\nxor r8d, r8d\njmp short loc_145F\nloc_1440:\nmov esi, r10d\nloc_1443:\nlea rbp, [rax+rsi]\nadd rdx, rsi\nadd rax, 2\nadd r8d, ecx\nmov rbp, [rdi+rbp*8]\nmov [rsp+rdx*8+128h+var_108], rbp\ncmp r9, rax\njz short loc_14B0\nloc_145F:\ncmp ecx, 1\njz loc_1640\nloc_1468:\nmovdqu xmm1, xmmword ptr [rdi+rax*8]\nmovsxd rdx, r8d\nlea rsi, [rbx+rdx*8]\nmovups xmmword ptr [rsi], xmm1\ncmp r11d, 1\njz short loc_1497\nmovdqu xmm2, xmmword ptr [rdi+rax*8+10h]\nmovups xmmword ptr [rsi+10h], xmm2\ncmp r11d, 2\njz short loc_1497\nmovdqu xmm3, xmmword ptr [rdi+rax*8+20h]\nmovups xmmword ptr [rsi+20h], xmm3\nloc_1497:\ncmp ecx, r10d\njnz short loc_1440\nadd rax, 2\nadd r8d, ecx\ncmp r9, rax\njnz short loc_1468\nnop dword ptr [rax+rax+00000000h]\nloc_14B0:\nxor eax, eax\npxor xmm0, xmm0\nlea r15, [rsp+128h+var_CC]\nxor edx, edx\nmov [rsp+128h+var_88], ax\nlea rax, [rsp+128h+var_D8]\nlea r14, unk_2004\nmov [rsp+128h+var_110], rax\nlea rax, [rsp+128h+var_C2]\nlea rbp, [rsp+128h+s]\nmov [rsp+128h+var_48], dx\nlea r12, [rsp+128h+var_78]\nmov [rsp+128h+var_120], rax\nmovaps xmmword ptr [rsp+128h+s], xmm0\nmovaps [rsp+128h+var_A8], xmm0\nmovaps [rsp+128h+var_98], xmm0\nmovaps xmmword ptr [rsp+128h+var_78], xmm0\nmovaps [rsp+128h+var_68], xmm0\nmovaps [rsp+128h+var_58], xmm0\nloc_1522:\nmov r8d, [rbx]\nmov rcx, r14\nmov edx, 0Ah\nmov esi, 2\nmov rdi, r15\nxor eax, eax\nadd rbx, 8\ncall ___sprintf_chk\nmov r8d, [rbx-4]\nmov rdi, [rsp+128h+var_120]\nxor eax, eax\nmov rcx, r14\nmov edx, 0Ah\nmov esi, 2\ncall ___sprintf_chk\nmov rdi, rbp; s\ncall _strlen\nmov edx, 32h ; '2'\nmov rsi, r15\nlea rdi, [rbp+rax+0]\ncall ___stpcpy_chk\nmov rdi, r12; s\nmov r13, rax\ncall _strlen\nmov rsi, [rsp+128h+var_120]\nmov edx, 32h ; '2'\nlea rdi, [r12+rax]\ncall ___stpcpy_chk\nmov r8, rax\nmov rax, [rsp+128h+var_110]\ncmp rbx, rax\njz short loc_15F0\nmov rcx, rbp\nmov rdi, r13\nmov edx, 3\nmov [rsp+128h+var_118], r8\nsub rcx, r13\nlea rsi, asc_2014; \", \"\nadd rcx, 32h ; '2'\ncall ___memcpy_chk\nmov r8, [rsp+128h+var_118]\nmov rcx, r12\nmov edx, 3\nlea rsi, asc_2014; \", \"\nsub rcx, r8\nmov rdi, r8\nadd rcx, 32h ; '2'\ncall ___memcpy_chk\njmp loc_1522\nloc_15F0:\nlea rbx, unk_4040\nxor eax, eax\nmov r9, r12\nmov r8, rbp\nlea rcx, aSS; \"[(%s), (%s)]\"\nmov edx, 64h ; 'd'\nmov esi, 2\nmov rdi, rbx\ncall ___sprintf_chk\nmov rax, [rsp+128h+var_40]\nsub rax, fs:28h\njnz short loc_164A\nadd rsp, 0F8h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1640:\nxor esi, esi\nmovsxd rdx, r8d\njmp loc_1443\nloc_164A:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "void *__fastcall sub_13E0(__int64 a1, int a2, int a3)\n{\n char *v3; // rbx\n __int64 v5; // rax\n __int64 v6; // r9\n unsigned int v7; // r11d\n unsigned int v8; // r10d\n int v9; // r8d\n __int64 v10; // rsi\n __int64 v11; // rbp\n __int64 v12; // rdx\n __m128i *v13; // rsi\n __int64 v14; // r8\n size_t v15; // rax\n __int64 v16; // r13\n size_t v17; // rax\n __int64 v18; // r8\n __int64 v20; // [rsp+10h] [rbp-118h]\n _QWORD v21[6]; // [rsp+20h] [rbp-108h] BYREF\n char v22; // [rsp+50h] [rbp-D8h] BYREF\n _BYTE v23[10]; // [rsp+5Ch] [rbp-CCh] BYREF\n char v24[10]; // [rsp+66h] [rbp-C2h] BYREF\n char s[16]; // [rsp+70h] [rbp-B8h] BYREF\n __int128 v26; // [rsp+80h] [rbp-A8h]\n __int128 v27; // [rsp+90h] [rbp-98h]\n __int16 v28; // [rsp+A0h] [rbp-88h]\n char v29[16]; // [rsp+B0h] [rbp-78h] BYREF\n __int128 v30; // [rsp+C0h] [rbp-68h]\n __int128 v31; // [rsp+D0h] [rbp-58h]\n __int16 v32; // [rsp+E0h] [rbp-48h]\n unsigned __int64 v33; // [rsp+E8h] [rbp-40h]\n\n v33 = __readfsqword(0x28u);\n v3 = (char *)v21;\n if ( a2 > 0 )\n {\n v3 = (char *)v21;\n if ( a3 > 0 )\n {\n v5 = 0LL;\n v6 = 2LL * a2;\n v7 = (unsigned int)a3 >> 1;\n v8 = a3 & 0xFFFFFFFE;\n v9 = 0;\n do\n {\n if ( a3 == 1 )\n {\n v10 = 0LL;\n v12 = v9;\n }\n else\n {\n while ( 1 )\n {\n v12 = v9;\n v13 = (__m128i *)&v21[v9];\n *v13 = _mm_loadu_si128((const __m128i *)(a1 + 8 * v5));\n if ( v7 != 1 )\n {\n v13[1] = _mm_loadu_si128((const __m128i *)(a1 + 8 * v5 + 16));\n if ( v7 != 2 )\n v13[2] = _mm_loadu_si128((const __m128i *)(a1 + 8 * v5 + 32));\n }\n if ( a3 != v8 )\n break;\n v5 += 2LL;\n v9 += a3;\n if ( v6 == v5 )\n goto LABEL_12;\n }\n v10 = v8;\n }\n v11 = v5 + v10;\n v5 += 2LL;\n v9 += a3;\n v21[v10 + v12] = *(_QWORD *)(a1 + 8 * v11);\n }\n while ( v6 != v5 );\n }\n }\nLABEL_12:\n v28 = 0;\n v32 = 0;\n *(_OWORD *)s = 0LL;\n v26 = 0LL;\n v27 = 0LL;\n *(_OWORD *)v29 = 0LL;\n v30 = 0LL;\n v31 = 0LL;\n while ( 1 )\n {\n v14 = *(unsigned int *)v3;\n v3 += 8;\n __sprintf_chk(v23, 2LL, 10LL, &unk_2004, v14);\n __sprintf_chk(v24, 2LL, 10LL, &unk_2004, *((unsigned int *)v3 - 1));\n v15 = strlen(s);\n v16 = __stpcpy_chk(&s[v15], v23, 50LL);\n v17 = strlen(v29);\n v18 = __stpcpy_chk(&v29[v17], v24, 50LL);\n if ( v3 == &v22 )\n break;\n v20 = v18;\n __memcpy_chk(v16, \", \", 3LL, &s[-v16 + 50]);\n __memcpy_chk(v20, \", \", 3LL, &v29[-v20 + 50]);\n }\n __sprintf_chk(&unk_4040, 2LL, 100LL, \"[(%s), (%s)]\", s);\n return &unk_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_13E0(long long a1, int a2, int a3) {\n char *v3;\n long long v5;\n long long v6;\n unsigned int v7;\n unsigned int v8;\n int v9;\n long long v10;\n long long v11;\n long long v12;\n __m128i *v13;\n long long v14;\n unsigned int v15;\n long long v16;\n unsigned int v17;\n long long v18;\n long long v20;\n uint64_t v21[6];\n char v22;\n uint8_t v23[10];\n char v24[10];\n char s[16];\n __int128 v26;\n __int128 v27;\n short v28;\n char v29[16];\n __int128 v30;\n __int128 v31;\n short v32;\n unsigned long long v33;\n v33 = __readfsqword(40u);\n v3 = (char *)v21;\n if (a2 > 0) {\n v3 = (char *)v21;\n if (a3 > 0) {\n v5 = 0LL;\n v6 = 2LL * a2;\n v7 = (unsigned int)a3 >> 1;\n v8 = a3 & 4294967294;\n v9 = 0;\n do {\n if (a3 == 1) {\n v10 = 0LL;\n v12 = v9;\n } else {\n while (1) {\n v12 = v9;\n v13 = (__m128i *)&v21[v9];\n *v13 = _mm_loadu_si128((const __m128i *)(a1 + 8 * v5));\n if (v7 != 1) {\n v13[1] = _mm_loadu_si128((const __m128i *)(a1 + 8 * v5 + 16));\n if (v7 != 2)\n v13[2] = _mm_loadu_si128((const __m128i *)(a1 + 8 * v5 + 32));\n }\n if (a3 != v8) break;\n v5 += 2LL;\n v9 += a3;\n if (v6 == v5) goto LABEL_12;\n }\n v10 = v8;\n }\n v11 = v5 + v10;\n v5 += 2LL;\n v9 += a3;\n v21[v10 + v12] = *(uint64_t *)(a1 + 8 * v11);\n } while (v6 != v5);\n }\n }\nLABEL_12:\n v28 = 0;\n v32 = 0;\n *(long double *)s = 0LL;\n v26 = 0LL;\n v27 = 0LL;\n *(long double *)v29 = 0LL;\n v30 = 0LL;\n v31 = 0LL;\n while (1) {\n v14 = *(unsigned int *)v3;\n v3 += 8;\n __sprintf_chk(v23, 2LL, 10LL, &unk_2004, v14);\n __sprintf_chk(v24, 2LL, 10LL, &unk_2004, *((unsigned int *)v3 - 1));\n v15 = strlen(s);\n v16 = __stpcpy_chk(&s[v15], v23, 50LL);\n v17 = strlen(v29);\n v18 = __stpcpy_chk(&v29[v17], v24, 50LL);\n if (v3 == &v22) break;\n v20 = v18;\n __memcpy_chk(v16, \", \", 3LL, &s[-v16 + 50]);\n __memcpy_chk(v20, \", \", 3LL, &v29[-v20 + 50]);\n }\n __sprintf_chk(&unk_4040, 2LL, 100LL, \"[(%s), (%s)]\", s);\n return &unk_4040;\n}", + "ida_pseudo_norm": "void *func0(long long a1, int a2, int a3) {\n char *v3;\n long long v5;\n long long v6;\n unsigned int v7;\n unsigned int v8;\n int v9;\n long long v10;\n long long v11;\n long long v12;\n __m128i *v13;\n long long v14;\n unsigned int v15;\n long long v16;\n unsigned int v17;\n long long v18;\n long long v20;\n uint64_t v21[6];\n char v22;\n uint8_t v23[10];\n char v24[10];\n char s[16];\n __int128 v26;\n __int128 v27;\n short v28;\n char v29[16];\n __int128 v30;\n __int128 v31;\n short v32;\n unsigned long long v33;\n v33 = __readfsqword(40u);\n v3 = (char *)v21;\n if (a2 > 0) {\n v3 = (char *)v21;\n if (a3 > 0) {\n v5 = 0LL;\n v6 = 2LL * a2;\n v7 = (unsigned int)a3 >> 1;\n v8 = a3 & 4294967294;\n v9 = 0;\n do {\n if (a3 == 1) {\n v10 = 0LL;\n v12 = v9;\n } else {\n while (1) {\n v12 = v9;\n v13 = (__m128i *)&v21[v9];\n *v13 = _mm_loadu_si128((const __m128i *)(a1 + 8 * v5));\n if (v7 != 1) {\n v13[1] = _mm_loadu_si128((const __m128i *)(a1 + 8 * v5 + 16));\n if (v7 != 2)\n v13[2] = _mm_loadu_si128((const __m128i *)(a1 + 8 * v5 + 32));\n }\n if (a3 != v8) break;\n v5 += 2LL;\n v9 += a3;\n if (v6 == v5) goto LABEL_12;\n }\n v10 = v8;\n }\n v11 = v5 + v10;\n v5 += 2LL;\n v9 += a3;\n v21[v10 + v12] = *(uint64_t *)(a1 + 8 * v11);\n } while (v6 != v5);\n }\n }\nLABEL_12:\n v28 = 0;\n v32 = 0;\n *(long double *)s = 0LL;\n v26 = 0LL;\n v27 = 0LL;\n *(long double *)v29 = 0LL;\n v30 = 0LL;\n v31 = 0LL;\n while (1) {\n v14 = *(unsigned int *)v3;\n v3 += 8;\n __sprintf_chk(v23, 2LL, 10LL, &unk_2004, v14);\n __sprintf_chk(v24, 2LL, 10LL, &unk_2004, *((unsigned int *)v3 - 1));\n v15 = strlen(s);\n v16 = __stpcpy_chk(&s[v15], v23, 50LL);\n v17 = strlen(v29);\n v18 = __stpcpy_chk(&v29[v17], v24, 50LL);\n if (v3 == &v22) break;\n v20 = v18;\n __memcpy_chk(v16, \", \", 3LL, &s[-v16 + 50]);\n __memcpy_chk(v20, \", \", 3LL, &v29[-v20 + 50]);\n }\n __sprintf_chk(&res_1, 2LL, 100LL, \"[(%s), (%s)]\", s);\n return &res_1;\n}" + }, + { + "index": 653, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct List {\n\n int *values;\n\n int size;\n\n int capacity;\n\n} List;\n\n\n\ntypedef struct Map {\n\n char **keys;\n\n List *values;\n\n int size;\n\n int capacity;\n\n} Map;\n\n\n\nvoid initList(List *list) {\n\n list->values = malloc(10 * sizeof(int));\n\n list->size = 0;\n\n list->capacity = 10;\n\n}\n\n\n\nvoid addToList(List *list, int value) {\n\n if (list->size >= list->capacity) {\n\n list->capacity *= 2;\n\n list->values = realloc(list->values, list->capacity * sizeof(int));\n\n }\n\n list->values[list->size++] = value;\n\n}\n\n\n\nvoid initMap(Map *map) {\n\n map->keys = malloc(10 * sizeof(char*));\n\n map->values = malloc(10 * sizeof(List));\n\n map->size = 0;\n\n map->capacity = 10;\n\n}\n\n\n\nint findKeyIndex(Map *map, char *key) {\n\n for (int i = 0; i < map->size; i++) {\n\n if (strcmp(map->keys[i], key) == 0) {\n\n return i;\n\n }\n\n }\n\n return -1;\n\n}\n\n\n\nvoid addToMap(Map *map, char *key, int value) {\n\n int index = findKeyIndex(map, key);\n\n\n\n if (index == -1) {\n\n if (map->size >= map->capacity) {\n\n map->capacity *= 2;\n\n map->keys = realloc(map->keys, map->capacity * sizeof(char*));\n\n map->values = realloc(map->values, map->capacity * sizeof(List));\n\n }\n\n map->keys[map->size] = strdup(key);\n\n initList(&map->values[map->size]);\n\n addToList(&map->values[map->size], value);\n\n map->size++;\n\n } else {\n\n addToList(&map->values[index], value);\n\n }\n\n}\n\n\n\n", + "func": "Map func0(const char *input[], int length) {\n Map map;\n initMap(&map);\n for (int i = 0; i < length; i += 2) {\n addToMap(&map, (char *)input[i], atoi(input[i + 1]));\n }\n return map;\n}", + "test": "int main() {\n\n const char *data1[] = {\"yellow\", \"1\", \"blue\", \"2\", \"yellow\", \"3\", \"blue\", \"4\", \"red\", \"1\"};\n\n const char *data2[] = {\"yellow\", \"10\", \"blue\", \"20\", \"yellow\", \"30\", \"blue\", \"40\", \"red\", \"10\"};\n\n const char *data3[] = {\"yellow\", \"15\", \"blue\", \"25\", \"yellow\", \"35\", \"blue\", \"45\", \"red\", \"15\"};\n\n\n\n Map result1 = func0(data1, 10);\n\n Map result2 = func0(data2, 10);\n\n Map result3 = func0(data3, 10);\n\n\n\n assert(result1.size == 3);\n\n assert(result2.size == 3);\n\n assert(result3.size == 3);\n\n\n\n // Additional asserts to compare the actual content of the dictionaries can be added here\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x50,%rsp\nmov %rdi,-0x38(%rbp)\nmov %rsi,-0x40(%rbp)\nmov %edx,-0x44(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea -0x20(%rbp),%rax\nmov %rax,%rdi\ncallq 12d0 \nmovl $0x0,-0x24(%rbp)\njmp 1568 \nmov -0x24(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,8),%rdx\nmov -0x40(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov %rax,%rdi\ncallq 1100 \nmov %eax,%edx\nmov -0x24(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x40(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%rcx\nlea -0x20(%rbp),%rax\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 1385 \naddl $0x2,-0x24(%rbp)\nmov -0x24(%rbp),%eax\ncmp -0x44(%rbp),%eax\njl 1519 \nmov -0x38(%rbp),%rcx\nmov -0x20(%rbp),%rax\nmov -0x18(%rbp),%rdx\nmov %rax,(%rcx)\nmov %rdx,0x8(%rcx)\nmov -0x10(%rbp),%rax\nmov %rax,0x10(%rcx)\nmov -0x8(%rbp),%rax\nxor %fs:0x28,%rax\nje 159f \ncallq 10b0 <__stack_chk_fail@plt>\nmov -0x38(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+var_38], rdi\nmov [rbp+var_40], rsi\nmov [rbp+var_44], edx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [rbp+var_20]\nmov rdi, rax\ncall initMap\nmov [rbp+var_24], 0\njmp short loc_1567\nloc_1518:\nmov eax, [rbp+var_24]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_40]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; nptr\ncall _atoi\nmov edx, eax\nmov eax, [rbp+var_24]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_40]\nadd rax, rcx\nmov rcx, [rax]\nlea rax, [rbp+var_20]\nmov rsi, rcx\nmov rdi, rax\ncall addToMap\nadd [rbp+var_24], 2\nloc_1567:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_44]\njl short loc_1518\nmov rcx, [rbp+var_38]\nmov rax, [rbp+var_20]\nmov rdx, [rbp+var_18]\nmov [rcx], rax\nmov [rcx+8], rdx\nmov rax, [rbp+var_10]\nmov [rcx+10h], rax\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njz short loc_159E\ncall ___stack_chk_fail\nloc_159E:\nmov rax, [rbp+var_38]\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(_QWORD *a1, __int64 a2, int a3)\n{\n unsigned int v3; // eax\n __int64 v4; // rdx\n int i; // [rsp+2Ch] [rbp-24h]\n _QWORD v8[4]; // [rsp+30h] [rbp-20h] BYREF\n\n v8[3] = __readfsqword(0x28u);\n initMap(v8);\n for ( i = 0; i < a3; i += 2 )\n {\n v3 = atoi(*(const char **)(8 * (i + 1LL) + a2));\n addToMap(v8, *(_QWORD *)(8LL * i + a2), v3);\n }\n v4 = v8[1];\n *a1 = v8[0];\n a1[1] = v4;\n a1[2] = v8[2];\n return a1;\n}", + "ida_strip_asm": "sub_14DD:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+var_38], rdi\nmov [rbp+var_40], rsi\nmov [rbp+var_44], edx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [rbp+var_20]\nmov rdi, rax\ncall sub_12D0\nmov [rbp+var_24], 0\njmp short loc_1567\nloc_1518:\nmov eax, [rbp+var_24]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_40]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; nptr\ncall _atoi\nmov edx, eax\nmov eax, [rbp+var_24]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_40]\nadd rax, rcx\nmov rcx, [rax]\nlea rax, [rbp+var_20]\nmov rsi, rcx\nmov rdi, rax\ncall sub_1385\nadd [rbp+var_24], 2\nloc_1567:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_44]\njl short loc_1518\nmov rcx, [rbp+var_38]\nmov rax, [rbp+var_20]\nmov rdx, [rbp+var_18]\nmov [rcx], rax\nmov [rcx+8], rdx\nmov rax, [rbp+var_10]\nmov [rcx+10h], rax\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njz short loc_159E\ncall ___stack_chk_fail\nloc_159E:\nmov rax, [rbp+var_38]\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_14DD(_QWORD *a1, __int64 a2, int a3)\n{\n unsigned int v3; // eax\n __int64 v4; // rdx\n int i; // [rsp+2Ch] [rbp-24h]\n _QWORD v8[4]; // [rsp+30h] [rbp-20h] BYREF\n\n v8[3] = __readfsqword(0x28u);\n sub_12D0(v8);\n for ( i = 0; i < a3; i += 2 )\n {\n v3 = atoi(*(const char **)(8 * (i + 1LL) + a2));\n sub_1385(v8, *(_QWORD *)(8LL * i + a2), v3);\n }\n v4 = v8[1];\n *a1 = v8[0];\n a1[1] = v4;\n a1[2] = v8[2];\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_14DD(uint64_t *a1, long long a2, int a3) {\n unsigned int v3;\n long long v4;\n int i;\n uint64_t v8[4];\n v8[3] = __readfsqword(40u);\n sub_12D0(v8);\n for (i = 0; i < a3; i += 2) {\n v3 = atoi(*(const char **)(8 * (i + 1LL) + a2));\n sub_1385(v8, *(uint64_t *)(8LL * i + a2), v3);\n }\n v4 = v8[1];\n *a1 = v8[0];\n a1[1] = v4;\n a1[2] = v8[2];\n return a1;\n}", + "ida_pseudo_norm": "uint64_t *func0(uint64_t *a1, long long a2, int a3) {\n unsigned int v3;\n long long v4;\n int i;\n uint64_t v8[4];\n v8[3] = __readfsqword(40u);\n initMap(v8);\n for (i = 0; i < a3; i += 2) {\n v3 = atoi(*(const char **)(8 * (i + 1LL) + a2));\n addToMap(v8, *(uint64_t *)(8LL * i + a2), v3);\n }\n v4 = v8[1];\n *a1 = v8[0];\n a1[1] = v4;\n a1[2] = v8[2];\n return a1;\n}" + }, + { + "index": 653, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct List {\n\n int *values;\n\n int size;\n\n int capacity;\n\n} List;\n\n\n\ntypedef struct Map {\n\n char **keys;\n\n List *values;\n\n int size;\n\n int capacity;\n\n} Map;\n\n\n\nvoid initList(List *list) {\n\n list->values = malloc(10 * sizeof(int));\n\n list->size = 0;\n\n list->capacity = 10;\n\n}\n\n\n\nvoid addToList(List *list, int value) {\n\n if (list->size >= list->capacity) {\n\n list->capacity *= 2;\n\n list->values = realloc(list->values, list->capacity * sizeof(int));\n\n }\n\n list->values[list->size++] = value;\n\n}\n\n\n\nvoid initMap(Map *map) {\n\n map->keys = malloc(10 * sizeof(char*));\n\n map->values = malloc(10 * sizeof(List));\n\n map->size = 0;\n\n map->capacity = 10;\n\n}\n\n\n\nint findKeyIndex(Map *map, char *key) {\n\n for (int i = 0; i < map->size; i++) {\n\n if (strcmp(map->keys[i], key) == 0) {\n\n return i;\n\n }\n\n }\n\n return -1;\n\n}\n\n\n\nvoid addToMap(Map *map, char *key, int value) {\n\n int index = findKeyIndex(map, key);\n\n\n\n if (index == -1) {\n\n if (map->size >= map->capacity) {\n\n map->capacity *= 2;\n\n map->keys = realloc(map->keys, map->capacity * sizeof(char*));\n\n map->values = realloc(map->values, map->capacity * sizeof(List));\n\n }\n\n map->keys[map->size] = strdup(key);\n\n initList(&map->values[map->size]);\n\n addToList(&map->values[map->size], value);\n\n map->size++;\n\n } else {\n\n addToList(&map->values[index], value);\n\n }\n\n}\n\n\n\n", + "func": "Map func0(const char *input[], int length) {\n Map map;\n initMap(&map);\n for (int i = 0; i < length; i += 2) {\n addToMap(&map, (char *)input[i], atoi(input[i + 1]));\n }\n return map;\n}", + "test": "int main() {\n\n const char *data1[] = {\"yellow\", \"1\", \"blue\", \"2\", \"yellow\", \"3\", \"blue\", \"4\", \"red\", \"1\"};\n\n const char *data2[] = {\"yellow\", \"10\", \"blue\", \"20\", \"yellow\", \"30\", \"blue\", \"40\", \"red\", \"10\"};\n\n const char *data3[] = {\"yellow\", \"15\", \"blue\", \"25\", \"yellow\", \"35\", \"blue\", \"45\", \"red\", \"15\"};\n\n\n\n Map result1 = func0(data1, 10);\n\n Map result2 = func0(data2, 10);\n\n Map result3 = func0(data3, 10);\n\n\n\n assert(result1.size == 3);\n\n assert(result2.size == 3);\n\n assert(result3.size == 3);\n\n\n\n // Additional asserts to compare the actual content of the dictionaries can be added here\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x28,%rsp\nmov %rdi,%r12\nmov %rsi,%r13\nmov %edx,%ebp\nmov %fs:0x28,%rax\nmov %rax,0x18(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\ncallq 1276 \ntest %ebp,%ebp\njle 1439 \nmov %r13,%rbx\nsub $0x1,%ebp\nshr %ebp\nmov %ebp,%ebp\nshl $0x4,%rbp\nlea 0x10(%r13,%rbp,1),%r13\nmov %rsp,%rbp\nmov 0x8(%rbx),%rdi\nmov $0xa,%edx\nmov $0x0,%esi\ncallq 10e0 \nmov %rax,%rdx\nmov (%rbx),%rsi\nmov %rbp,%rdi\ncallq 1306 \nadd $0x10,%rbx\ncmp %r13,%rbx\njne 140f \nmovdqa (%rsp),%xmm0\nmovups %xmm0,(%r12)\nmov 0x10(%rsp),%rax\nmov %rax,0x10(%r12)\nmov 0x18(%rsp),%rax\nxor %fs:0x28,%rax\njne 146b \nmov %r12,%rax\nadd $0x28,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\ncallq 10b0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov r12, rdi\nmov r13, rsi\nmov ebp, edx\nmov rax, fs:28h\nmov [rsp+48h+var_30], rax\nxor eax, eax\nmov rdi, rsp\ncall initMap\ntest ebp, ebp\njle short loc_142D\nmov rbx, r13\nsub ebp, 1\nshr ebp, 1\nmov ebp, ebp\nshl rbp, 4\nlea r13, [r13+rbp+10h]\nmov rbp, rsp\nloc_1404:\nmov rdi, [rbx+8]; nptr\nmov edx, 0Ah; base\nmov esi, 0; endptr\ncall _strtol\nmov rsi, [rbx]\nmov edx, eax\nmov rdi, rbp\ncall addToMap\nadd rbx, 10h\ncmp rbx, r13\njnz short loc_1404\nloc_142D:\nmovdqa xmm0, [rsp+48h+var_48]\nmovups xmmword ptr [r12], xmm0\nmov rax, [rsp+48h+var_38]\nmov [r12+10h], rax\nmov rax, [rsp+48h+var_30]\nsub rax, fs:28h\njnz short loc_145F\nmov rax, r12\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_145F:\ncall ___stack_chk_fail", + "ida_pseudo": "__m128i *__fastcall func0(__m128i *a1, __int64 a2, int a3)\n{\n __int64 v4; // rbx\n unsigned int v5; // eax\n __m128i v7; // [rsp+0h] [rbp-48h] BYREF\n __int64 v8; // [rsp+10h] [rbp-38h]\n unsigned __int64 v9; // [rsp+18h] [rbp-30h]\n\n v9 = __readfsqword(0x28u);\n initMap(&v7);\n if ( a3 > 0 )\n {\n v4 = a2;\n do\n {\n v5 = strtol(*(const char **)(v4 + 8), 0LL, 10);\n addToMap(&v7, *(_QWORD *)v4, v5);\n v4 += 16LL;\n }\n while ( v4 != a2 + 16LL * ((unsigned int)(a3 - 1) >> 1) + 16 );\n }\n *a1 = _mm_load_si128(&v7);\n a1[1].m128i_i64[0] = v8;\n return a1;\n}", + "ida_strip_asm": "sub_13BC:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov r12, rdi\nmov r13, rsi\nmov ebp, edx\nmov rax, fs:28h\nmov [rsp+48h+var_30], rax\nxor eax, eax\nmov rdi, rsp\ncall sub_1276\ntest ebp, ebp\njle short loc_142D\nmov rbx, r13\nsub ebp, 1\nshr ebp, 1\nmov ebp, ebp\nshl rbp, 4\nlea r13, [r13+rbp+10h]\nmov rbp, rsp\nloc_1404:\nmov rdi, [rbx+8]; nptr\nmov edx, 0Ah; base\nmov esi, 0; endptr\ncall _strtol\nmov rsi, [rbx]\nmov edx, eax\nmov rdi, rbp\ncall sub_1301\nadd rbx, 10h\ncmp rbx, r13\njnz short loc_1404\nloc_142D:\nmovdqa xmm0, [rsp+48h+var_48]\nmovups xmmword ptr [r12], xmm0\nmov rax, [rsp+48h+var_38]\nmov [r12+10h], rax\nmov rax, [rsp+48h+var_30]\nsub rax, fs:28h\njnz short loc_145F\nmov rax, r12\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_145F:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__m128i *__fastcall sub_13BC(__m128i *a1, __int64 a2, int a3)\n{\n __int64 v4; // rbx\n unsigned int v5; // eax\n __m128i v7; // [rsp+0h] [rbp-48h] BYREF\n __int64 v8; // [rsp+10h] [rbp-38h]\n unsigned __int64 v9; // [rsp+18h] [rbp-30h]\n\n v9 = __readfsqword(0x28u);\n sub_1276(&v7);\n if ( a3 > 0 )\n {\n v4 = a2;\n do\n {\n v5 = strtol(*(const char **)(v4 + 8), 0LL, 10);\n sub_1301(&v7, *(_QWORD *)v4, v5);\n v4 += 16LL;\n }\n while ( v4 != a2 + 16LL * ((unsigned int)(a3 - 1) >> 1) + 16 );\n }\n *a1 = _mm_load_si128(&v7);\n a1[1].m128i_i64[0] = v8;\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__m128i *sub_13BC(__m128i *a1, long long a2, int a3) {\n long long v4;\n unsigned int v5;\n __m128i v7;\n long long v8;\n unsigned long long v9;\n v9 = __readfsqword(40u);\n sub_1276(&v7);\n if (a3 > 0) {\n v4 = a2;\n do {\n v5 = strtol(*(const char **)(v4 + 8), 0LL, 10);\n sub_1301(&v7, *(uint64_t *)v4, v5);\n v4 += 16LL;\n } while (v4 != a2 + 16LL * ((unsigned int)(a3 - 1) >> 1) + 16);\n }\n *a1 = _mm_load_si128(&v7);\n a1[1].m128i_i64[0] = v8;\n return a1;\n}", + "ida_pseudo_norm": "__m128i *func0(__m128i *a1, long long a2, int a3) {\n long long v4;\n unsigned int v5;\n __m128i v7;\n long long v8;\n unsigned long long v9;\n v9 = __readfsqword(40u);\n initMap(&v7);\n if (a3 > 0) {\n v4 = a2;\n do {\n v5 = strtol(*(const char **)(v4 + 8), 0LL, 10);\n addToMap(&v7, *(uint64_t *)v4, v5);\n v4 += 16LL;\n } while (v4 != a2 + 16LL * ((unsigned int)(a3 - 1) >> 1) + 16);\n }\n *a1 = _mm_load_si128(&v7);\n a1[1].m128i_i64[0] = v8;\n return a1;\n}" + }, + { + "index": 653, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct List {\n\n int *values;\n\n int size;\n\n int capacity;\n\n} List;\n\n\n\ntypedef struct Map {\n\n char **keys;\n\n List *values;\n\n int size;\n\n int capacity;\n\n} Map;\n\n\n\nvoid initList(List *list) {\n\n list->values = malloc(10 * sizeof(int));\n\n list->size = 0;\n\n list->capacity = 10;\n\n}\n\n\n\nvoid addToList(List *list, int value) {\n\n if (list->size >= list->capacity) {\n\n list->capacity *= 2;\n\n list->values = realloc(list->values, list->capacity * sizeof(int));\n\n }\n\n list->values[list->size++] = value;\n\n}\n\n\n\nvoid initMap(Map *map) {\n\n map->keys = malloc(10 * sizeof(char*));\n\n map->values = malloc(10 * sizeof(List));\n\n map->size = 0;\n\n map->capacity = 10;\n\n}\n\n\n\nint findKeyIndex(Map *map, char *key) {\n\n for (int i = 0; i < map->size; i++) {\n\n if (strcmp(map->keys[i], key) == 0) {\n\n return i;\n\n }\n\n }\n\n return -1;\n\n}\n\n\n\nvoid addToMap(Map *map, char *key, int value) {\n\n int index = findKeyIndex(map, key);\n\n\n\n if (index == -1) {\n\n if (map->size >= map->capacity) {\n\n map->capacity *= 2;\n\n map->keys = realloc(map->keys, map->capacity * sizeof(char*));\n\n map->values = realloc(map->values, map->capacity * sizeof(List));\n\n }\n\n map->keys[map->size] = strdup(key);\n\n initList(&map->values[map->size]);\n\n addToList(&map->values[map->size], value);\n\n map->size++;\n\n } else {\n\n addToList(&map->values[index], value);\n\n }\n\n}\n\n\n\n", + "func": "Map func0(const char *input[], int length) {\n Map map;\n initMap(&map);\n for (int i = 0; i < length; i += 2) {\n addToMap(&map, (char *)input[i], atoi(input[i + 1]));\n }\n return map;\n}", + "test": "int main() {\n\n const char *data1[] = {\"yellow\", \"1\", \"blue\", \"2\", \"yellow\", \"3\", \"blue\", \"4\", \"red\", \"1\"};\n\n const char *data2[] = {\"yellow\", \"10\", \"blue\", \"20\", \"yellow\", \"30\", \"blue\", \"40\", \"red\", \"10\"};\n\n const char *data3[] = {\"yellow\", \"15\", \"blue\", \"25\", \"yellow\", \"35\", \"blue\", \"45\", \"red\", \"15\"};\n\n\n\n Map result1 = func0(data1, 10);\n\n Map result2 = func0(data2, 10);\n\n Map result3 = func0(data3, 10);\n\n\n\n assert(result1.size == 3);\n\n assert(result2.size == 3);\n\n assert(result3.size == 3);\n\n\n\n // Additional asserts to compare the actual content of the dictionaries can be added here\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov %rdi,%r13\npush %r12\nmov %edx,%r12d\npush %rbp\npush %rbx\nmov %rsi,%rbx\nsub $0x28,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x18(%rsp)\nxor %eax,%eax\nmov %rsp,%rbp\nmov %rbp,%rdi\ncallq 14e0 \ntest %r12d,%r12d\njle 16e8 \nsub $0x1,%r12d\nshr %r12d\nshl $0x4,%r12\nlea 0x10(%rbx,%r12,1),%r12\nnopw 0x0(%rax,%rax,1)\nmov 0x8(%rbx),%rdi\nmov $0xa,%edx\nxor %esi,%esi\nadd $0x10,%rbx\ncallq 10e0 \nmov -0x10(%rbx),%rsi\nmov %rbp,%rdi\nmov %rax,%rdx\ncallq 1590 \ncmp %r12,%rbx\njne 16c0 \nmov 0x10(%rsp),%rax\nmovdqa (%rsp),%xmm0\nmov %rax,0x10(%r13)\nmovups %xmm0,0x0(%r13)\nmov 0x18(%rsp),%rax\nxor %fs:0x28,%rax\njne 1719 \nadd $0x28,%rsp\nmov %r13,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\ncallq 10b0 <__stack_chk_fail@plt>\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\nmov r12, rdi\nmov edi, 50h ; 'P'; size\npush rbp\nmov ebp, edx\npush rbx\nmov rbx, rsi\nsub rsp, 28h\nmov rax, fs:28h\nmov [rsp+48h+var_30], rax\nxor eax, eax\ncall _malloc\nmov edi, 0A0h; size\nmov qword ptr [rsp+48h+var_48], rax\ncall _malloc\nmov qword ptr [rsp+48h+var_48+8], rax\nmov rax, cs:qword_2090\nmov [rsp+48h+var_38], rax\ntest ebp, ebp\njle short loc_179F\nsub ebp, 1\nshr ebp, 1\nshl rbp, 4\nlea r13, [rbx+rbp+10h]\nmov rbp, rsp\nnop dword ptr [rax+00h]\nloc_1778:\nmov rdi, [rbx+8]; nptr\nmov edx, 0Ah; base\nxor esi, esi; endptr\nadd rbx, 10h\ncall _strtol\nmov rsi, [rbx-10h]\nmov rdi, rbp\nmov edx, eax\ncall addToMap\ncmp rbx, r13\njnz short loc_1778\nloc_179F:\nmov rax, [rsp+48h+var_38]\nmovdqa xmm0, [rsp+48h+var_48]\nmov [r12+10h], rax\nmovups xmmword ptr [r12], xmm0\nmov rax, [rsp+48h+var_30]\nsub rax, fs:28h\njnz short loc_17D1\nadd rsp, 28h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_17D1:\ncall ___stack_chk_fail", + "ida_pseudo": "__m128i *__fastcall func0(__m128i *a1, __int64 a2, int a3)\n{\n __int64 v5; // rbx\n const char *v6; // rdi\n unsigned int v7; // eax\n __m128i v8; // xmm0\n __m128i v10; // [rsp+0h] [rbp-48h] BYREF\n __int64 v11; // [rsp+10h] [rbp-38h]\n unsigned __int64 v12; // [rsp+18h] [rbp-30h]\n\n v5 = a2;\n v12 = __readfsqword(0x28u);\n v10.m128i_i64[0] = (__int64)malloc(0x50uLL);\n v10.m128i_i64[1] = (__int64)malloc(0xA0uLL);\n v11 = 0xA00000000LL;\n if ( a3 > 0 )\n {\n do\n {\n v6 = *(const char **)(v5 + 8);\n v5 += 16LL;\n v7 = strtol(v6, 0LL, 10);\n addToMap(&v10, *(_QWORD *)(v5 - 16), v7);\n }\n while ( v5 != a2 + 16LL * ((unsigned int)(a3 - 1) >> 1) + 16 );\n }\n v8 = _mm_load_si128(&v10);\n a1[1].m128i_i64[0] = v11;\n *a1 = v8;\n return a1;\n}", + "ida_strip_asm": "sub_1710:\nendbr64\npush r13\npush r12\nmov r12, rdi\nmov edi, 50h ; 'P'; size\npush rbp\nmov ebp, edx\npush rbx\nmov rbx, rsi\nsub rsp, 28h\nmov rax, fs:28h\nmov [rsp+48h+var_30], rax\nxor eax, eax\ncall _malloc\nmov edi, 0A0h; size\nmov qword ptr [rsp+48h+var_48], rax\ncall _malloc\nmov qword ptr [rsp+48h+var_48+8], rax\nmov rax, cs:qword_2090\nmov [rsp+48h+var_38], rax\ntest ebp, ebp\njle short loc_179F\nsub ebp, 1\nshr ebp, 1\nshl rbp, 4\nlea r13, [rbx+rbp+10h]\nmov rbp, rsp\nnop dword ptr [rax+00h]\nloc_1778:\nmov rdi, [rbx+8]; nptr\nmov edx, 0Ah; base\nxor esi, esi; endptr\nadd rbx, 10h\ncall _strtol\nmov rsi, [rbx-10h]\nmov rdi, rbp\nmov edx, eax\ncall sub_15C0\ncmp rbx, r13\njnz short loc_1778\nloc_179F:\nmov rax, [rsp+48h+var_38]\nmovdqa xmm0, [rsp+48h+var_48]\nmov [r12+10h], rax\nmovups xmmword ptr [r12], xmm0\nmov rax, [rsp+48h+var_30]\nsub rax, fs:28h\njnz short loc_17D1\nadd rsp, 28h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_17D1:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__m128i *__fastcall sub_1710(__m128i *a1, __int64 a2, int a3)\n{\n __int64 v5; // rbx\n const char *v6; // rdi\n unsigned int v7; // eax\n __m128i v8; // xmm0\n __m128i v10; // [rsp+0h] [rbp-48h] BYREF\n __int64 v11; // [rsp+10h] [rbp-38h]\n unsigned __int64 v12; // [rsp+18h] [rbp-30h]\n\n v5 = a2;\n v12 = __readfsqword(0x28u);\n v10.m128i_i64[0] = (__int64)malloc(0x50uLL);\n v10.m128i_i64[1] = (__int64)malloc(0xA0uLL);\n v11 = 0xA00000000LL;\n if ( a3 > 0 )\n {\n do\n {\n v6 = *(const char **)(v5 + 8);\n v5 += 16LL;\n v7 = strtol(v6, 0LL, 10);\n sub_15C0(&v10, *(_QWORD *)(v5 - 16), v7);\n }\n while ( v5 != a2 + 16LL * ((unsigned int)(a3 - 1) >> 1) + 16 );\n }\n v8 = _mm_load_si128(&v10);\n a1[1].m128i_i64[0] = v11;\n *a1 = v8;\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__m128i *sub_1710(__m128i *a1, long long a2, int a3) {\n long long v5;\n const char *v6;\n unsigned int v7;\n __m128i v8;\n __m128i v10;\n long long v11;\n unsigned long long v12;\n v5 = a2;\n v12 = __readfsqword(40u);\n v10.m128i_i64[0] = (long long)malloc(80uLL);\n v10.m128i_i64[1] = (long long)malloc(160uLL);\n v11 = 42949672960LL;\n if (a3 > 0) {\n do {\n v6 = *(const char **)(v5 + 8);\n v5 += 16LL;\n v7 = strtol(v6, 0LL, 10);\n sub_15C0(&v10, *(uint64_t *)(v5 - 16), v7);\n } while (v5 != a2 + 16LL * ((unsigned int)(a3 - 1) >> 1) + 16);\n }\n v8 = _mm_load_si128(&v10);\n a1[1].m128i_i64[0] = v11;\n *a1 = v8;\n return a1;\n}", + "ida_pseudo_norm": "__m128i *func0(__m128i *a1, long long a2, int a3) {\n long long v5;\n const char *v6;\n unsigned int v7;\n __m128i v8;\n __m128i v10;\n long long v11;\n unsigned long long v12;\n v5 = a2;\n v12 = __readfsqword(40u);\n v10.m128i_i64[0] = (long long)malloc(80uLL);\n v10.m128i_i64[1] = (long long)malloc(160uLL);\n v11 = 42949672960LL;\n if (a3 > 0) {\n do {\n v6 = *(const char **)(v5 + 8);\n v5 += 16LL;\n v7 = strtol(v6, 0LL, 10);\n addToMap(&v10, *(uint64_t *)(v5 - 16), v7);\n } while (v5 != a2 + 16LL * ((unsigned int)(a3 - 1) >> 1) + 16);\n }\n v8 = _mm_load_si128(&v10);\n a1[1].m128i_i64[0] = v11;\n *a1 = v8;\n return a1;\n}" + }, + { + "index": 653, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct List {\n\n int *values;\n\n int size;\n\n int capacity;\n\n} List;\n\n\n\ntypedef struct Map {\n\n char **keys;\n\n List *values;\n\n int size;\n\n int capacity;\n\n} Map;\n\n\n\nvoid initList(List *list) {\n\n list->values = malloc(10 * sizeof(int));\n\n list->size = 0;\n\n list->capacity = 10;\n\n}\n\n\n\nvoid addToList(List *list, int value) {\n\n if (list->size >= list->capacity) {\n\n list->capacity *= 2;\n\n list->values = realloc(list->values, list->capacity * sizeof(int));\n\n }\n\n list->values[list->size++] = value;\n\n}\n\n\n\nvoid initMap(Map *map) {\n\n map->keys = malloc(10 * sizeof(char*));\n\n map->values = malloc(10 * sizeof(List));\n\n map->size = 0;\n\n map->capacity = 10;\n\n}\n\n\n\nint findKeyIndex(Map *map, char *key) {\n\n for (int i = 0; i < map->size; i++) {\n\n if (strcmp(map->keys[i], key) == 0) {\n\n return i;\n\n }\n\n }\n\n return -1;\n\n}\n\n\n\nvoid addToMap(Map *map, char *key, int value) {\n\n int index = findKeyIndex(map, key);\n\n\n\n if (index == -1) {\n\n if (map->size >= map->capacity) {\n\n map->capacity *= 2;\n\n map->keys = realloc(map->keys, map->capacity * sizeof(char*));\n\n map->values = realloc(map->values, map->capacity * sizeof(List));\n\n }\n\n map->keys[map->size] = strdup(key);\n\n initList(&map->values[map->size]);\n\n addToList(&map->values[map->size], value);\n\n map->size++;\n\n } else {\n\n addToList(&map->values[index], value);\n\n }\n\n}\n\n\n\n", + "func": "Map func0(const char *input[], int length) {\n Map map;\n initMap(&map);\n for (int i = 0; i < length; i += 2) {\n addToMap(&map, (char *)input[i], atoi(input[i + 1]));\n }\n return map;\n}", + "test": "int main() {\n\n const char *data1[] = {\"yellow\", \"1\", \"blue\", \"2\", \"yellow\", \"3\", \"blue\", \"4\", \"red\", \"1\"};\n\n const char *data2[] = {\"yellow\", \"10\", \"blue\", \"20\", \"yellow\", \"30\", \"blue\", \"40\", \"red\", \"10\"};\n\n const char *data3[] = {\"yellow\", \"15\", \"blue\", \"25\", \"yellow\", \"35\", \"blue\", \"45\", \"red\", \"15\"};\n\n\n\n Map result1 = func0(data1, 10);\n\n Map result2 = func0(data2, 10);\n\n Map result3 = func0(data3, 10);\n\n\n\n assert(result1.size == 3);\n\n assert(result2.size == 3);\n\n assert(result3.size == 3);\n\n\n\n // Additional asserts to compare the actual content of the dictionaries can be added here\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov %rdi,%r13\nmov $0x50,%edi\npush %r12\npush %rbp\nmov %edx,%ebp\npush %rbx\nmov %rsi,%rbx\nsub $0x28,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x18(%rsp)\nxor %eax,%eax\ncallq 10f0 \nmov $0xa0,%edi\nmov %rax,(%rsp)\ncallq 10f0 \nmov %rax,0x8(%rsp)\nmovabs $0xa00000000,%rax\nmov %rax,0x10(%rsp)\ntest %ebp,%ebp\njle 17b8 \nsub $0x1,%ebp\nshr %ebp\nshl $0x4,%rbp\nlea 0x10(%rbx,%rbp,1),%r12\nmov %rsp,%rbp\nnopw 0x0(%rax,%rax,1)\nmov 0x8(%rbx),%rdi\nmov $0xa,%edx\nxor %esi,%esi\nadd $0x10,%rbx\ncallq 10e0 \nmov -0x10(%rbx),%rsi\nmov %rbp,%rdi\nmov %rax,%rdx\ncallq 15d0 \ncmp %rbx,%r12\njne 1790 \nmov 0x10(%rsp),%rax\nmovdqa (%rsp),%xmm0\nmov %rax,0x10(%r13)\nmovups %xmm0,0x0(%r13)\nmov 0x18(%rsp),%rax\nxor %fs:0x28,%rax\njne 17e9 \nadd $0x28,%rsp\nmov %r13,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\ncallq 10b0 <__stack_chk_fail@plt>\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\nmov r12, rdi\nmov edi, 50h ; 'P'; size\npush rbp\nmov ebp, edx\npush rbx\nmov rbx, rsi\nsub rsp, 28h\nmov rax, fs:28h\nmov [rsp+48h+var_30], rax\nxor eax, eax\ncall _malloc\nmov edi, 0A0h; size\nmov qword ptr [rsp+48h+var_48], rax\ncall _malloc\nmov qword ptr [rsp+48h+var_48+8], rax\nmov rax, cs:qword_2090\nmov [rsp+48h+var_38], rax\ntest ebp, ebp\njle short loc_179F\nsub ebp, 1\nshr ebp, 1\nshl rbp, 4\nlea r13, [rbx+rbp+10h]\nmov rbp, rsp\nnop dword ptr [rax+00h]\nloc_1778:\nmov rdi, [rbx+8]; nptr\nmov edx, 0Ah; base\nxor esi, esi; endptr\nadd rbx, 10h\ncall _strtol\nmov rsi, [rbx-10h]\nmov rdi, rbp\nmov edx, eax\ncall addToMap\ncmp r13, rbx\njnz short loc_1778\nloc_179F:\nmov rax, [rsp+48h+var_38]\nmovdqa xmm0, [rsp+48h+var_48]\nmov [r12+10h], rax\nmovups xmmword ptr [r12], xmm0\nmov rax, [rsp+48h+var_30]\nsub rax, fs:28h\njnz short loc_17D1\nadd rsp, 28h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_17D1:\ncall ___stack_chk_fail", + "ida_pseudo": "__m128i *__fastcall func0(__m128i *a1, __int64 a2, int a3)\n{\n __int64 v5; // rbx\n const char *v6; // rdi\n unsigned int v7; // eax\n __m128i v8; // xmm0\n __m128i v10; // [rsp+0h] [rbp-48h] BYREF\n __int64 v11; // [rsp+10h] [rbp-38h]\n unsigned __int64 v12; // [rsp+18h] [rbp-30h]\n\n v5 = a2;\n v12 = __readfsqword(0x28u);\n v10.m128i_i64[0] = (__int64)malloc(0x50uLL);\n v10.m128i_i64[1] = (__int64)malloc(0xA0uLL);\n v11 = 0xA00000000LL;\n if ( a3 > 0 )\n {\n do\n {\n v6 = *(const char **)(v5 + 8);\n v5 += 16LL;\n v7 = strtol(v6, 0LL, 10);\n addToMap(&v10, *(_QWORD *)(v5 - 16), v7);\n }\n while ( a2 + 16LL * ((unsigned int)(a3 - 1) >> 1) + 16 != v5 );\n }\n v8 = _mm_load_si128(&v10);\n a1[1].m128i_i64[0] = v11;\n *a1 = v8;\n return a1;\n}", + "ida_strip_asm": "sub_1710:\nendbr64\npush r13\npush r12\nmov r12, rdi\nmov edi, 50h ; 'P'; size\npush rbp\nmov ebp, edx\npush rbx\nmov rbx, rsi\nsub rsp, 28h\nmov rax, fs:28h\nmov [rsp+48h+var_30], rax\nxor eax, eax\ncall _malloc\nmov edi, 0A0h; size\nmov qword ptr [rsp+48h+var_48], rax\ncall _malloc\nmov qword ptr [rsp+48h+var_48+8], rax\nmov rax, cs:qword_2090\nmov [rsp+48h+var_38], rax\ntest ebp, ebp\njle short loc_179F\nsub ebp, 1\nshr ebp, 1\nshl rbp, 4\nlea r13, [rbx+rbp+10h]\nmov rbp, rsp\nnop dword ptr [rax+00h]\nloc_1778:\nmov rdi, [rbx+8]; nptr\nmov edx, 0Ah; base\nxor esi, esi; endptr\nadd rbx, 10h\ncall _strtol\nmov rsi, [rbx-10h]\nmov rdi, rbp\nmov edx, eax\ncall sub_15C0\ncmp r13, rbx\njnz short loc_1778\nloc_179F:\nmov rax, [rsp+48h+var_38]\nmovdqa xmm0, [rsp+48h+var_48]\nmov [r12+10h], rax\nmovups xmmword ptr [r12], xmm0\nmov rax, [rsp+48h+var_30]\nsub rax, fs:28h\njnz short loc_17D1\nadd rsp, 28h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_17D1:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__m128i *__fastcall sub_1710(__m128i *a1, __int64 a2, int a3)\n{\n __int64 v5; // rbx\n const char *v6; // rdi\n unsigned int v7; // eax\n __m128i v8; // xmm0\n __m128i v10; // [rsp+0h] [rbp-48h] BYREF\n __int64 v11; // [rsp+10h] [rbp-38h]\n unsigned __int64 v12; // [rsp+18h] [rbp-30h]\n\n v5 = a2;\n v12 = __readfsqword(0x28u);\n v10.m128i_i64[0] = (__int64)malloc(0x50uLL);\n v10.m128i_i64[1] = (__int64)malloc(0xA0uLL);\n v11 = 0xA00000000LL;\n if ( a3 > 0 )\n {\n do\n {\n v6 = *(const char **)(v5 + 8);\n v5 += 16LL;\n v7 = strtol(v6, 0LL, 10);\n sub_15C0(&v10, *(_QWORD *)(v5 - 16), v7);\n }\n while ( a2 + 16LL * ((unsigned int)(a3 - 1) >> 1) + 16 != v5 );\n }\n v8 = _mm_load_si128(&v10);\n a1[1].m128i_i64[0] = v11;\n *a1 = v8;\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__m128i *sub_1710(__m128i *a1, long long a2, int a3) {\n long long v5;\n const char *v6;\n unsigned int v7;\n __m128i v8;\n __m128i v10;\n long long v11;\n unsigned long long v12;\n v5 = a2;\n v12 = __readfsqword(40u);\n v10.m128i_i64[0] = (long long)malloc(80uLL);\n v10.m128i_i64[1] = (long long)malloc(160uLL);\n v11 = 42949672960LL;\n if (a3 > 0) {\n do {\n v6 = *(const char **)(v5 + 8);\n v5 += 16LL;\n v7 = strtol(v6, 0LL, 10);\n sub_15C0(&v10, *(uint64_t *)(v5 - 16), v7);\n } while (a2 + 16LL * ((unsigned int)(a3 - 1) >> 1) + 16 != v5);\n }\n v8 = _mm_load_si128(&v10);\n a1[1].m128i_i64[0] = v11;\n *a1 = v8;\n return a1;\n}", + "ida_pseudo_norm": "__m128i *func0(__m128i *a1, long long a2, int a3) {\n long long v5;\n const char *v6;\n unsigned int v7;\n __m128i v8;\n __m128i v10;\n long long v11;\n unsigned long long v12;\n v5 = a2;\n v12 = __readfsqword(40u);\n v10.m128i_i64[0] = (long long)malloc(80uLL);\n v10.m128i_i64[1] = (long long)malloc(160uLL);\n v11 = 42949672960LL;\n if (a3 > 0) {\n do {\n v6 = *(const char **)(v5 + 8);\n v5 += 16LL;\n v7 = strtol(v6, 0LL, 10);\n addToMap(&v10, *(uint64_t *)(v5 - 16), v7);\n } while (a2 + 16LL * ((unsigned int)(a3 - 1) >> 1) + 16 != v5);\n }\n v8 = _mm_load_si128(&v10);\n a1[1].m128i_i64[0] = v11;\n *a1 = v8;\n return a1;\n}" + }, + { + "index": 654, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int l, int b) {\n int perimeter = 2 * (l + b);\n return perimeter;\n}", + "test": "int main() {\n\n assert(func0(10, 20) == 60);\n\n assert(func0(10, 5) == 30);\n\n assert(func0(4, 2) == 12);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov -0x14(%rbp),%edx\nmov -0x18(%rbp),%eax\nadd %edx,%eax\nadd %eax,%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov edx, [rbp+var_14]\nmov eax, [rbp+var_18]\nadd eax, edx\nadd eax, eax\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n return (unsigned int)(2 * (a1 + a2));\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov edx, [rbp+var_14]\nmov eax, [rbp+var_18]\nadd eax, edx\nadd eax, eax\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2)\n{\n return (unsigned int)(2 * (a1 + a2));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2) { return (unsigned int)(2 * (a1 + a2)); }", + "ida_pseudo_norm": "long long func0(int a1, int a2) { return (unsigned int)(2 * (a1 + a2)); }" + }, + { + "index": 655, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int sm = 0;\n for (int i = 1; i <= n; i++) {\n sm += i * i * i * i * i;\n }\n return sm;\n}", + "test": "int main() {\n\n assert(func0(2) == 33);\n\n assert(func0(4) == 1300);\n\n assert(func0(3) == 276);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x1,-0x4(%rbp)\njmp 117d \nmov -0x4(%rbp),%eax\nimul %eax,%eax\nimul -0x4(%rbp),%eax\nimul -0x4(%rbp),%eax\nimul -0x4(%rbp),%eax\nadd %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x14(%rbp),%eax\njle 1164 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 1\njmp short loc_117D\nloc_1164:\nmov eax, [rbp+var_4]\nimul eax, eax\nimul eax, [rbp+var_4]\nimul eax, [rbp+var_4]\nimul eax, [rbp+var_4]\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_117D:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_14]\njle short loc_1164\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v2; // [rsp+Ch] [rbp-8h]\n int i; // [rsp+10h] [rbp-4h]\n\n v2 = 0;\n for ( i = 1; i <= a1; ++i )\n v2 += i * i * i * i * i;\n return v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 1\njmp short loc_117D\nloc_1164:\nmov eax, [rbp+var_4]\nimul eax, eax\nimul eax, [rbp+var_4]\nimul eax, [rbp+var_4]\nimul eax, [rbp+var_4]\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_117D:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_14]\njle short loc_1164\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n unsigned int v2; // [rsp+Ch] [rbp-8h]\n int i; // [rsp+10h] [rbp-4h]\n\n v2 = 0;\n for ( i = 1; i <= a1; ++i )\n v2 += i * i * i * i * i;\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n unsigned int v2;\n int i;\n v2 = 0;\n for (i = 1; i <= a1; ++i) v2 += i * i * i * i * i;\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v2;\n int i;\n v2 = 0;\n for (i = 1; i <= a1; ++i) v2 += i * i * i * i * i;\n return v2;\n}" + }, + { + "index": 655, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int sm = 0;\n for (int i = 1; i <= n; i++) {\n sm += i * i * i * i * i;\n }\n return sm;\n}", + "test": "int main() {\n\n assert(func0(2) == 33);\n\n assert(func0(4) == 1300);\n\n assert(func0(3) == 276);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\njle 1175 \nadd $0x1,%edi\nmov $0x1,%edx\nmov $0x0,%ecx\nmov %edx,%eax\nimul %edx,%eax\nimul %eax,%eax\nimul %edx,%eax\nadd %eax,%ecx\nadd $0x1,%edx\ncmp %edi,%edx\njne 115e \nmov %ecx,%eax\nretq\nmov $0x0,%ecx\njmp 1172 \n", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njle short loc_1175\nadd edi, 1\nmov edx, 1\nmov ecx, 0\nloc_115E:\nmov eax, edx\nimul eax, edx\nimul eax, eax\nimul eax, edx\nadd ecx, eax\nadd edx, 1\ncmp edx, edi\njnz short loc_115E\nloc_1172:\nmov eax, ecx\nretn\nloc_1175:\nmov ecx, 0\njmp short loc_1172", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // edi\n int v2; // edx\n unsigned int v3; // ecx\n\n if ( a1 <= 0 )\n {\n return 0;\n }\n else\n {\n v1 = a1 + 1;\n v2 = 1;\n v3 = 0;\n do\n {\n v3 += v2 * v2 * v2 * v2 * v2;\n ++v2;\n }\n while ( v2 != v1 );\n }\n return v3;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ntest edi, edi\njle short loc_1175\nadd edi, 1\nmov edx, 1\nmov ecx, 0\nloc_115E:\nmov eax, edx\nimul eax, edx\nimul eax, eax\nimul eax, edx\nadd ecx, eax\nadd edx, 1\ncmp edx, edi\njnz short loc_115E\nloc_1172:\nmov eax, ecx\nretn\nloc_1175:\nmov ecx, 0\njmp short loc_1172", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v1; // edi\n int v2; // edx\n unsigned int v3; // ecx\n\n if ( a1 <= 0 )\n {\n return 0;\n }\n else\n {\n v1 = a1 + 1;\n v2 = 1;\n v3 = 0;\n do\n {\n v3 += v2 * v2 * v2 * v2 * v2;\n ++v2;\n }\n while ( v2 != v1 );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v1;\n int v2;\n unsigned int v3;\n if (a1 <= 0) {\n return 0;\n } else {\n v1 = a1 + 1;\n v2 = 1;\n v3 = 0;\n do {\n v3 += v2 * v2 * v2 * v2 * v2;\n ++v2;\n } while (v2 != v1);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v2;\n unsigned int v3;\n if (a1 <= 0) {\n return 0;\n } else {\n v1 = a1 + 1;\n v2 = 1;\n v3 = 0;\n do {\n v3 += v2 * v2 * v2 * v2 * v2;\n ++v2;\n } while (v2 != v1);\n }\n return v3;\n}" + }, + { + "index": 656, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nvoid sort(int arr[], int n) {\n\n int i, j;\n\n for (i = 0; i < n - 1; i++) {\n\n for (j = 0; j < n - i - 1; j++) {\n\n if (arr[j] > arr[j + 1]) {\n\n int temp = arr[j];\n\n arr[j] = arr[j + 1];\n\n arr[j + 1] = temp;\n\n }\n\n }\n\n }\n\n}\n\n\n\n", + "func": "int func0(int a[], int b[], int n) {\n sort(a, n);\n sort(b, n);\n int sum = 0;\n for (int i = 0; i < n; i++) {\n sum += abs(a[i] - b[i]);\n }\n return sum;\n}", + "test": "int main() {\n\n int a1[] = {3, 2, 1};\n\n int b1[] = {2, 1, 3};\n\n assert(func0(a1, b1, 3) == 0);\n\n\n\n int a2[] = {1, 2, 3};\n\n int b2[] = {4, 5, 6};\n\n assert(func0(a2, b2, 3) == 9);\n\n\n\n int a3[] = {4, 1, 8, 7};\n\n int b3[] = {2, 3, 6, 5};\n\n assert(func0(a3, b3, 4) == 6);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x28,%rsp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %edx,-0x24(%rbp)\nmov -0x24(%rbp),%edx\nmov -0x18(%rbp),%rax\nmov %edx,%esi\nmov %rax,%rdi\ncallq 1169 \nmov -0x24(%rbp),%edx\nmov -0x20(%rbp),%rax\nmov %edx,%esi\nmov %rax,%rdi\ncallq 1169 \nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 12dd \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x20(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\nsub %eax,%edx\nmov %edx,%eax\ncltd\nxor %edx,%eax\nsub %edx,%eax\nadd %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x24(%rbp),%eax\njl 12a1 \nmov -0x8(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 28h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov edx, [rbp+var_24]\nmov rax, [rbp+var_18]\nmov esi, edx\nmov rdi, rax\ncall sort\nmov edx, [rbp+var_24]\nmov rax, [rbp+var_20]\nmov esi, edx\nmov rdi, rax\ncall sort\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_12DE\nloc_12A1:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_20]\nadd rdx, rcx\nmov edx, [rdx]\nsub eax, edx\nmov edx, eax\nneg edx\ncmovns eax, edx\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_12DE:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_24]\njl short loc_12A1\nmov eax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, unsigned int a3)\n{\n __int64 v3; // rcx\n int v4; // eax\n unsigned int v7; // [rsp+20h] [rbp-8h]\n int i; // [rsp+24h] [rbp-4h]\n\n sort(a1, a3);\n sort(a2, a3);\n v7 = 0;\n for ( i = 0; i < (int)a3; ++i )\n {\n v3 = 4LL * i;\n v4 = *(_DWORD *)(v3 + a1) - *(_DWORD *)(v3 + a2);\n if ( *(_DWORD *)(v3 + a2) - *(_DWORD *)(v3 + a1) >= 0 )\n v4 = *(_DWORD *)(v3 + a2) - *(_DWORD *)(4LL * i + a1);\n v7 += v4;\n }\n return v7;\n}", + "ida_strip_asm": "sub_1258:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 28h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov edx, [rbp+var_24]\nmov rax, [rbp+var_18]\nmov esi, edx\nmov rdi, rax\ncall sub_1169\nmov edx, [rbp+var_24]\nmov rax, [rbp+var_20]\nmov esi, edx\nmov rdi, rax\ncall sub_1169\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_12DE\nloc_12A1:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_20]\nadd rdx, rcx\nmov edx, [rdx]\nsub eax, edx\nmov edx, eax\nneg edx\ncmovns eax, edx\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_12DE:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_24]\njl short loc_12A1\nmov eax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1258(__int64 a1, __int64 a2, unsigned int a3)\n{\n __int64 v3; // rcx\n int v4; // eax\n unsigned int v7; // [rsp+20h] [rbp-8h]\n int i; // [rsp+24h] [rbp-4h]\n\n sub_1169(a1, a3);\n sub_1169(a2, a3);\n v7 = 0;\n for ( i = 0; i < (int)a3; ++i )\n {\n v3 = 4LL * i;\n v4 = *(_DWORD *)(v3 + a1) - *(_DWORD *)(v3 + a2);\n if ( *(_DWORD *)(v3 + a2) - *(_DWORD *)(v3 + a1) >= 0 )\n v4 = *(_DWORD *)(v3 + a2) - *(_DWORD *)(4LL * i + a1);\n v7 += v4;\n }\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1258(long long a1, long long a2, unsigned int a3) {\n long long v3;\n int v4;\n unsigned int v7;\n int i;\n sub_1169(a1, a3);\n sub_1169(a2, a3);\n v7 = 0;\n for (i = 0; i < (int)a3; ++i) {\n v3 = 4LL * i;\n v4 = *(uint32_t *)(v3 + a1) - *(uint32_t *)(v3 + a2);\n if (*(uint32_t *)(v3 + a2) - *(uint32_t *)(v3 + a1) >= 0)\n v4 = *(uint32_t *)(v3 + a2) - *(uint32_t *)(4LL * i + a1);\n v7 += v4;\n }\n return v7;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, unsigned int a3) {\n long long v3;\n int v4;\n unsigned int v7;\n int i;\n sort(a1, a3);\n sort(a2, a3);\n v7 = 0;\n for (i = 0; i < (int)a3; ++i) {\n v3 = 4LL * i;\n v4 = *(uint32_t *)(v3 + a1) - *(uint32_t *)(v3 + a2);\n if (*(uint32_t *)(v3 + a2) - *(uint32_t *)(v3 + a1) >= 0)\n v4 = *(uint32_t *)(v3 + a2) - *(uint32_t *)(4LL * i + a1);\n v7 += v4;\n }\n return v7;\n}" + }, + { + "index": 656, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nvoid sort(int arr[], int n) {\n\n int i, j;\n\n for (i = 0; i < n - 1; i++) {\n\n for (j = 0; j < n - i - 1; j++) {\n\n if (arr[j] > arr[j + 1]) {\n\n int temp = arr[j];\n\n arr[j] = arr[j + 1];\n\n arr[j + 1] = temp;\n\n }\n\n }\n\n }\n\n}\n\n\n\n", + "func": "int func0(int a[], int b[], int n) {\n sort(a, n);\n sort(b, n);\n int sum = 0;\n for (int i = 0; i < n; i++) {\n sum += abs(a[i] - b[i]);\n }\n return sum;\n}", + "test": "int main() {\n\n int a1[] = {3, 2, 1};\n\n int b1[] = {2, 1, 3};\n\n assert(func0(a1, b1, 3) == 0);\n\n\n\n int a2[] = {1, 2, 3};\n\n int b2[] = {4, 5, 6};\n\n assert(func0(a2, b2, 3) == 9);\n\n\n\n int a3[] = {4, 1, 8, 7};\n\n int b3[] = {2, 3, 6, 5};\n\n assert(func0(a3, b3, 4) == 6);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nmov %rsi,%rbp\nmov %edx,%r12d\nmov %edx,%esi\ncallq 1169 \nmov %r12d,%esi\nmov %rbp,%rdi\ncallq 1169 \ntest %r12d,%r12d\njle 120a \nlea -0x1(%r12),%edi\nmov $0x0,%edx\nmov $0x0,%esi\nmov (%rbx,%rdx,4),%eax\nsub 0x0(%rbp,%rdx,4),%eax\nmov %eax,%ecx\nsar $0x1f,%ecx\nxor %ecx,%eax\nsub %ecx,%eax\nadd %eax,%esi\nmov %rdx,%rax\nadd $0x1,%rdx\ncmp %rdi,%rax\njne 11e5 \nmov %esi,%eax\npop %rbx\npop %rbp\npop %r12\nretq\nmov $0x0,%esi\njmp 1203 \n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nmov rbp, rsi\nmov r12d, edx\nmov esi, edx\ncall sort\nmov esi, r12d\nmov rdi, rbp\ncall sort\ntest r12d, r12d\njle short loc_1209\nmovsxd rdi, r12d\nshl rdi, 2\nmov edx, 0\nmov esi, 0\nloc_11E9:\nmov eax, [rbx+rdx]\nsub eax, [rbp+rdx+0]\nmov ecx, eax\nneg ecx\ncmovns eax, ecx\nadd esi, eax\nadd rdx, 4\ncmp rdx, rdi\njnz short loc_11E9\nloc_1202:\nmov eax, esi\npop rbx\npop rbp\npop r12\nretn\nloc_1209:\nmov esi, 0\njmp short loc_1202", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n __int64 v5; // rdx\n unsigned int v6; // esi\n int v7; // eax\n\n sort(a1, (unsigned int)a3);\n sort(a2, (unsigned int)a3);\n if ( a3 <= 0 )\n {\n return 0;\n }\n else\n {\n v5 = 0LL;\n v6 = 0;\n do\n {\n v7 = *(_DWORD *)(a1 + v5) - *(_DWORD *)(a2 + v5);\n if ( *(_DWORD *)(a2 + v5) - *(_DWORD *)(a1 + v5) >= 0 )\n v7 = *(_DWORD *)(a2 + v5) - *(_DWORD *)(a1 + v5);\n v6 += v7;\n v5 += 4LL;\n }\n while ( v5 != 4LL * a3 );\n }\n return v6;\n}", + "ida_strip_asm": "sub_11B0:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nmov rbp, rsi\nmov r12d, edx\nmov esi, edx\ncall sub_1169\nmov esi, r12d\nmov rdi, rbp\ncall sub_1169\ntest r12d, r12d\njle short loc_1209\nmovsxd rdi, r12d\nshl rdi, 2\nmov edx, 0\nmov esi, 0\nloc_11E9:\nmov eax, [rbx+rdx]\nsub eax, [rbp+rdx+0]\nmov ecx, eax\nneg ecx\ncmovns eax, ecx\nadd esi, eax\nadd rdx, 4\ncmp rdx, rdi\njnz short loc_11E9\nloc_1202:\nmov eax, esi\npop rbx\npop rbp\npop r12\nretn\nloc_1209:\nmov esi, 0\njmp short loc_1202", + "ida_strip_pseudo": "__int64 __fastcall sub_11B0(__int64 a1, __int64 a2, int a3)\n{\n __int64 v5; // rdx\n unsigned int v6; // esi\n int v7; // eax\n\n sub_1169(a1, (unsigned int)a3);\n sub_1169(a2, (unsigned int)a3);\n if ( a3 <= 0 )\n {\n return 0;\n }\n else\n {\n v5 = 0LL;\n v6 = 0;\n do\n {\n v7 = *(_DWORD *)(a1 + v5) - *(_DWORD *)(a2 + v5);\n if ( *(_DWORD *)(a2 + v5) - *(_DWORD *)(a1 + v5) >= 0 )\n v7 = *(_DWORD *)(a2 + v5) - *(_DWORD *)(a1 + v5);\n v6 += v7;\n v5 += 4LL;\n }\n while ( v5 != 4LL * a3 );\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11B0(long long a1, long long a2, int a3) {\n long long v5;\n unsigned int v6;\n int v7;\n sub_1169(a1, (unsigned int)a3);\n sub_1169(a2, (unsigned int)a3);\n if (a3 <= 0) {\n return 0;\n } else {\n v5 = 0LL;\n v6 = 0;\n do {\n v7 = *(uint32_t *)(a1 + v5) - *(uint32_t *)(a2 + v5);\n if (*(uint32_t *)(a2 + v5) - *(uint32_t *)(a1 + v5) >= 0)\n v7 = *(uint32_t *)(a2 + v5) - *(uint32_t *)(a1 + v5);\n v6 += v7;\n v5 += 4LL;\n } while (v5 != 4LL * a3);\n }\n return v6;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3) {\n long long v5;\n unsigned int v6;\n int v7;\n sort(a1, (unsigned int)a3);\n sort(a2, (unsigned int)a3);\n if (a3 <= 0) {\n return 0;\n } else {\n v5 = 0LL;\n v6 = 0;\n do {\n v7 = *(uint32_t *)(a1 + v5) - *(uint32_t *)(a2 + v5);\n if (*(uint32_t *)(a2 + v5) - *(uint32_t *)(a1 + v5) >= 0)\n v7 = *(uint32_t *)(a2 + v5) - *(uint32_t *)(a1 + v5);\n v6 += v7;\n v5 += 4LL;\n } while (v5 != 4LL * a3);\n }\n return v6;\n}" + }, + { + "index": 656, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nvoid sort(int arr[], int n) {\n\n int i, j;\n\n for (i = 0; i < n - 1; i++) {\n\n for (j = 0; j < n - i - 1; j++) {\n\n if (arr[j] > arr[j + 1]) {\n\n int temp = arr[j];\n\n arr[j] = arr[j + 1];\n\n arr[j + 1] = temp;\n\n }\n\n }\n\n }\n\n}\n\n\n\n", + "func": "int func0(int a[], int b[], int n) {\n sort(a, n);\n sort(b, n);\n int sum = 0;\n for (int i = 0; i < n; i++) {\n sum += abs(a[i] - b[i]);\n }\n return sum;\n}", + "test": "int main() {\n\n int a1[] = {3, 2, 1};\n\n int b1[] = {2, 1, 3};\n\n assert(func0(a1, b1, 3) == 0);\n\n\n\n int a2[] = {1, 2, 3};\n\n int b2[] = {4, 5, 6};\n\n assert(func0(a2, b2, 3) == 9);\n\n\n\n int a3[] = {4, 1, 8, 7};\n\n int b3[] = {2, 3, 6, 5};\n\n assert(func0(a3, b3, 4) == 6);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rsi,%r11\nmov %edx,%esi\nmov %edx,%ebx\nmov %rdi,%r10\ncallq 12f0 \nmov %ebx,%esi\nmov %r11,%rdi\ncallq 12f0 \ntest %ebx,%ebx\njle 1388 \nlea -0x1(%rbx),%esi\nxor %edx,%edx\nxor %r8d,%r8d\nnopw 0x0(%rax,%rax,1)\nmov (%r10,%rdx,4),%eax\nsub (%r11,%rdx,4),%eax\nmov %eax,%ecx\nsar $0x1f,%ecx\nxor %ecx,%eax\nsub %ecx,%eax\nadd %eax,%r8d\nmov %rdx,%rax\nadd $0x1,%rdx\ncmp %rax,%rsi\njne 1360 \nmov %r8d,%eax\npop %rbx\nretq\nnopl (%rax)\nxor %r8d,%r8d\npop %rbx\nmov %r8d,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov r10d, edx\nmov rbx, rsi\nmov esi, edx\nmov r11, rdi\ncall sort\nmov esi, r10d\nmov rdi, rbx\ncall sort\ntest r10d, r10d\njle short loc_1370\nmovsxd rdi, r10d\nxor edx, edx\nxor esi, esi\nshl rdi, 2\nloc_1350:\nmov eax, [r11+rdx]\nsub eax, [rbx+rdx]\nmov ecx, eax\nneg ecx\ncmovns eax, ecx\nadd rdx, 4\nadd esi, eax\ncmp rdi, rdx\njnz short loc_1350\nmov eax, esi\npop rbx\nretn\nloc_1370:\nxor esi, esi\npop rbx\nmov eax, esi\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, unsigned int a3)\n{\n unsigned int v4; // r10d\n int v5; // r10d\n __int64 v6; // r11\n __int64 v7; // rdx\n unsigned int v8; // esi\n int v9; // eax\n\n sort(a1, a3);\n sort(a2, v4);\n if ( v5 <= 0 )\n return 0LL;\n v7 = 0LL;\n v8 = 0;\n do\n {\n v9 = *(_DWORD *)(v6 + v7) - *(_DWORD *)(a2 + v7);\n if ( *(_DWORD *)(a2 + v7) - *(_DWORD *)(v6 + v7) >= 0 )\n v9 = *(_DWORD *)(a2 + v7) - *(_DWORD *)(v6 + v7);\n v7 += 4LL;\n v8 += v9;\n }\n while ( 4LL * v5 != v7 );\n return v8;\n}", + "ida_strip_asm": "sub_1320:\nendbr64\npush rbx\nmov r10d, edx\nmov rbx, rsi\nmov esi, edx\nmov r11, rdi\ncall sub_12C0\nmov esi, r10d\nmov rdi, rbx\ncall sub_12C0\ntest r10d, r10d\njle short loc_1370\nmovsxd rdi, r10d\nxor edx, edx\nxor esi, esi\nshl rdi, 2\nloc_1350:\nmov eax, [r11+rdx]\nsub eax, [rbx+rdx]\nmov ecx, eax\nneg ecx\ncmovns eax, ecx\nadd rdx, 4\nadd esi, eax\ncmp rdi, rdx\njnz short loc_1350\nmov eax, esi\npop rbx\nretn\nloc_1370:\nxor esi, esi\npop rbx\nmov eax, esi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1320(__int64 a1, __int64 a2, unsigned int a3)\n{\n unsigned int v4; // r10d\n int v5; // r10d\n __int64 v6; // r11\n __int64 v7; // rdx\n unsigned int v8; // esi\n int v9; // eax\n\n sub_12C0(a1, a3);\n sub_12C0(a2, v4);\n if ( v5 <= 0 )\n return 0LL;\n v7 = 0LL;\n v8 = 0;\n do\n {\n v9 = *(_DWORD *)(v6 + v7) - *(_DWORD *)(a2 + v7);\n if ( *(_DWORD *)(a2 + v7) - *(_DWORD *)(v6 + v7) >= 0 )\n v9 = *(_DWORD *)(a2 + v7) - *(_DWORD *)(v6 + v7);\n v7 += 4LL;\n v8 += v9;\n }\n while ( 4LL * v5 != v7 );\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1320(long long a1, long long a2, unsigned int a3) {\n unsigned int v4;\n int v5;\n long long v6;\n long long v7;\n unsigned int v8;\n int v9;\n sub_12C0(a1, a3);\n sub_12C0(a2, v4);\n if (v5 <= 0) return 0LL;\n v7 = 0LL;\n v8 = 0;\n do {\n v9 = *(uint32_t *)(v6 + v7) - *(uint32_t *)(a2 + v7);\n if (*(uint32_t *)(a2 + v7) - *(uint32_t *)(v6 + v7) >= 0)\n v9 = *(uint32_t *)(a2 + v7) - *(uint32_t *)(v6 + v7);\n v7 += 4LL;\n v8 += v9;\n } while (4LL * v5 != v7);\n return v8;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, unsigned int a3) {\n unsigned int v4;\n int v5;\n long long v6;\n long long v7;\n unsigned int v8;\n int v9;\n sort(a1, a3);\n sort(a2, v4);\n if (v5 <= 0) return 0LL;\n v7 = 0LL;\n v8 = 0;\n do {\n v9 = *(uint32_t *)(v6 + v7) - *(uint32_t *)(a2 + v7);\n if (*(uint32_t *)(a2 + v7) - *(uint32_t *)(v6 + v7) >= 0)\n v9 = *(uint32_t *)(a2 + v7) - *(uint32_t *)(v6 + v7);\n v7 += 4LL;\n v8 += v9;\n } while (4LL * v5 != v7);\n return v8;\n}" + }, + { + "index": 656, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nvoid sort(int arr[], int n) {\n\n int i, j;\n\n for (i = 0; i < n - 1; i++) {\n\n for (j = 0; j < n - i - 1; j++) {\n\n if (arr[j] > arr[j + 1]) {\n\n int temp = arr[j];\n\n arr[j] = arr[j + 1];\n\n arr[j + 1] = temp;\n\n }\n\n }\n\n }\n\n}\n\n\n\n", + "func": "int func0(int a[], int b[], int n) {\n sort(a, n);\n sort(b, n);\n int sum = 0;\n for (int i = 0; i < n; i++) {\n sum += abs(a[i] - b[i]);\n }\n return sum;\n}", + "test": "int main() {\n\n int a1[] = {3, 2, 1};\n\n int b1[] = {2, 1, 3};\n\n assert(func0(a1, b1, 3) == 0);\n\n\n\n int a2[] = {1, 2, 3};\n\n int b2[] = {4, 5, 6};\n\n assert(func0(a2, b2, 3) == 9);\n\n\n\n int a3[] = {4, 1, 8, 7};\n\n int b3[] = {2, 3, 6, 5};\n\n assert(func0(a3, b3, 4) == 6);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nlea -0x1(%rdx),%r11d\npush %rbp\nlea 0x4(%rdi),%rbp\npush %rbx\nmov %r11d,%ecx\nmov %r11d,%r8d\ntest %r11d,%r11d\njle 13a0 \nnopl 0x0(%rax)\nlea -0x1(%r8),%r9d\nmov %rdi,%rax\nmov %r9,%r8\nlea 0x0(%rbp,%r9,4),%rbx\nmov (%rax),%r9d\nmov 0x4(%rax),%r10d\ncmp %r10d,%r9d\njle 1353 \nmov %r10d,(%rax)\nmov %r9d,0x4(%rax)\nadd $0x4,%rax\ncmp %rax,%rbx\njne 1340 \ntest %r8d,%r8d\njne 1330 \nlea 0x4(%rsi),%rbx\nnopl (%rax)\nlea -0x1(%rcx),%r8d\nmov %rsi,%rax\nmov %r8,%rcx\nlea (%rbx,%r8,4),%r10\nnopw %cs:0x0(%rax,%rax,1)\nmov (%rax),%r8d\nmov 0x4(%rax),%r9d\ncmp %r9d,%r8d\njle 1393 \nmov %r9d,(%rax)\nmov %r8d,0x4(%rax)\nadd $0x4,%rax\ncmp %rax,%r10\njne 1380 \ntest %ecx,%ecx\njne 1368 \ntest %edx,%edx\njle 1480 \ncmp $0x2,%r11d\njbe 1485 \nmov %edx,%ecx\nxor %eax,%eax\npxor %xmm1,%xmm1\nshr $0x2,%ecx\nshl $0x4,%rcx\nnopl 0x0(%rax)\nmovdqu (%rdi,%rax,1),%xmm0\nmovdqu (%rsi,%rax,1),%xmm3\nadd $0x10,%rax\npsubd %xmm3,%xmm0\nmovdqa %xmm0,%xmm2\npsrad $0x1f,%xmm2\npxor %xmm2,%xmm0\npsubd %xmm2,%xmm0\npaddd %xmm0,%xmm1\ncmp %rax,%rcx\njne 13c8 \nmovdqa %xmm1,%xmm0\nmov %edx,%ecx\npsrldq $0x8,%xmm0\nand $0xfffffffc,%ecx\npaddd %xmm0,%xmm1\nmovdqa %xmm1,%xmm0\npsrldq $0x4,%xmm0\npaddd %xmm0,%xmm1\nmovd %xmm1,%eax\ntest $0x3,%dl\nje 1476 \nmovslq %ecx,%r9\nmov (%rdi,%r9,4),%r8d\nsub (%rsi,%r9,4),%r8d\nmov %r8d,%r9d\nsar $0x1f,%r9d\nxor %r9d,%r8d\nsub %r9d,%r8d\nadd %r8d,%eax\nlea 0x1(%rcx),%r8d\ncmp %r8d,%edx\njle 1476 \nmovslq %r8d,%r9\nadd $0x2,%ecx\nmov (%rdi,%r9,4),%r8d\nsub (%rsi,%r9,4),%r8d\nmov %r8d,%r9d\nsar $0x1f,%r9d\nxor %r9d,%r8d\nsub %r9d,%r8d\nadd %r8d,%eax\ncmp %ecx,%edx\njle 1476 \nmovslq %ecx,%rcx\nmov (%rdi,%rcx,4),%edx\nsub (%rsi,%rcx,4),%edx\nmov %edx,%ecx\nsar $0x1f,%ecx\nxor %ecx,%edx\nsub %ecx,%edx\nadd %edx,%eax\npop %rbx\npop %rbp\nretq\nnopl 0x0(%rax)\nxor %eax,%eax\npop %rbx\npop %rbp\nretq\nxor %ecx,%ecx\nxor %eax,%eax\njmp 141c \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmov r8, rdi\nmov r9, rsi\nmov r10d, edx\nmov edi, edx\nlea r11, [r8+4]\ncmp edx, 1\njle loc_14C0\nnop dword ptr [rax+00h]\nloc_1340:\nlea edx, [rdi-2]\nmov rax, r8\nlea rsi, [r11+rdx*4]\nnop word ptr [rax+rax+00h]\nloc_1350:\nmovq xmm0, qword ptr [rax]\npshufd xmm3, xmm0, 0E5h\nmovd edx, xmm0\nmovd ecx, xmm3\ncmp ecx, edx\njge short loc_136E\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_136E:\nadd rax, 4\ncmp rax, rsi\njnz short loc_1350\nsub edi, 1\ncmp edi, 1\njz short loc_1390\nloc_137F:\ncmp edi, 1\njg short loc_1340\nsub edi, 1\njmp short loc_137F\nloc_1390:\nmov edi, r10d\nlea r11, [r9+4]\nnop word ptr [rax+rax+00000000h]\nloc_13A0:\ncmp edi, 1\njle loc_14B8\nlea edx, [rdi-2]\nmov rax, r9\nlea rsi, [r11+rdx*4]\nnop dword ptr [rax+rax+00h]\nloc_13B8:\nmovq xmm0, qword ptr [rax]\npshufd xmm4, xmm0, 0E5h\nmovd edx, xmm0\nmovd ecx, xmm4\ncmp ecx, edx\njge short loc_13D6\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_13D6:\nadd rax, 4\ncmp rax, rsi\njnz short loc_13B8\nsub edi, 1\ncmp edi, 1\njnz short loc_13A0\nlea eax, [r10-1]\ncmp eax, 2\njbe loc_14CF\nmov edx, r10d\nxor eax, eax\npxor xmm1, xmm1\nshr edx, 2\nshl rdx, 4\nnop dword ptr [rax+00h]\nloc_1408:\nmovdqu xmm0, xmmword ptr [r8+rax]\nmovdqu xmm5, xmmword ptr [r9+rax]\nadd rax, 10h\npsubd xmm0, xmm5\nmovdqa xmm2, xmm0\npsrad xmm2, 1Fh\npxor xmm0, xmm2\npsubd xmm0, xmm2\npaddd xmm1, xmm0\ncmp rax, rdx\njnz short loc_1408\nmovdqa xmm0, xmm1\npsrldq xmm0, 8\npaddd xmm1, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm0, 4\npaddd xmm1, xmm0\nmovd eax, xmm1\ntest r10b, 3\njz short locret_14B3\nmov edx, r10d\nand edx, 0FFFFFFFCh\nmovsxd rdi, edx\nmov ecx, [r8+rdi*4]\nsub ecx, [r9+rdi*4]\nlea rsi, ds:0[rdi*4]\nmov edi, ecx\nneg edi\ncmovns ecx, edi\nadd eax, ecx\nlea ecx, [rdx+1]\ncmp r10d, ecx\njle short locret_14B3\nloc_1484:\nmov ecx, [r8+rsi+4]\nsub ecx, [r9+rsi+4]\nmov edi, ecx\nneg edi\ncmovns ecx, edi\nadd edx, 2\nadd eax, ecx\ncmp r10d, edx\njle short locret_14B3\nmov edx, [r8+rsi+8]\nsub edx, [r9+rsi+8]\nmov ecx, edx\nneg ecx\ncmovns edx, ecx\nadd eax, edx\nretn\nlocret_14B3:\nretn\nloc_14B8:\nsub edi, 1\njmp loc_13A0\nloc_14C0:\njnz short loc_14E2\nmov edx, [r8]\nsub edx, [rsi]\nmov eax, edx\nneg eax\ncmovs eax, edx\nretn\nloc_14CF:\nmov edx, [r8]\nsub edx, [r9]\nmov eax, edx\nneg eax\ncmovs eax, edx\nxor edx, edx\nxor esi, esi\njmp short loc_1484\nloc_14E2:\nxor eax, eax\nretn", + "ida_pseudo": "__int64 __fastcall func0(__m128i *a1, __m128i *a2, int a3)\n{\n int v6; // edi\n __m128i *v7; // rax\n __m128i v8; // xmm0\n int i; // edi\n __m128i *v10; // rax\n __m128i v11; // xmm0\n unsigned __int64 v12; // rax\n __m128i v13; // xmm1\n __int64 v14; // rdx\n __m128i v15; // xmm0\n __m128i v16; // xmm5\n __m128i v17; // xmm0\n __m128i v18; // xmm2\n __m128i v19; // xmm1\n __int64 result; // rax\n signed int v21; // edx\n int v22; // ecx\n __int64 v23; // rsi\n int v24; // ecx\n int v25; // edx\n\n v6 = a3;\n if ( a3 <= 1 )\n {\n if ( a3 == 1 )\n {\n result = (unsigned int)(a2->m128i_i32[0] - a1->m128i_i32[0]);\n if ( a2->m128i_i32[0] - a1->m128i_i32[0] < 0 )\n return (unsigned int)(a1->m128i_i32[0] - a2->m128i_i32[0]);\n }\n else\n {\n return 0LL;\n }\n }\n else\n {\n while ( 1 )\n {\n v7 = a1;\n do\n {\n v8 = _mm_loadl_epi64(v7);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v8, 229)) < _mm_cvtsi128_si32(v8) )\n v7->m128i_i64[0] = _mm_shuffle_epi32(v8, 225).m128i_u64[0];\n v7 = (__m128i *)((char *)v7 + 4);\n }\n while ( v7 != (__m128i *)((char *)a1->m128i_i64 + 4 * (unsigned int)(v6 - 2) + 4) );\n if ( --v6 == 1 )\n break;\n while ( v6 <= 1 )\n --v6;\n }\n for ( i = a3; i != 1; --i )\n {\n while ( i <= 1 )\n --i;\n v10 = a2;\n do\n {\n v11 = _mm_loadl_epi64(v10);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v11, 229)) < _mm_cvtsi128_si32(v11) )\n v10->m128i_i64[0] = _mm_shuffle_epi32(v11, 225).m128i_u64[0];\n v10 = (__m128i *)((char *)v10 + 4);\n }\n while ( v10 != (__m128i *)((char *)a2->m128i_i64 + 4 * (unsigned int)(i - 2) + 4) );\n }\n if ( (unsigned int)(a3 - 1) <= 2 )\n {\n LODWORD(result) = a2->m128i_i32[0] - a1->m128i_i32[0];\n if ( (int)result < 0 )\n LODWORD(result) = a1->m128i_i32[0] - a2->m128i_i32[0];\n v21 = 0;\n v23 = 0LL;\n goto LABEL_23;\n }\n v12 = 0LL;\n v13 = 0LL;\n v14 = 16LL * ((unsigned int)a3 >> 2);\n do\n {\n v15 = _mm_loadu_si128(&a1[v12 / 0x10]);\n v16 = _mm_loadu_si128(&a2[v12 / 0x10]);\n v12 += 16LL;\n v17 = _mm_sub_epi32(v15, v16);\n v18 = _mm_srai_epi32(v17, 0x1Fu);\n v13 = _mm_add_epi32(v13, _mm_sub_epi32(_mm_xor_si128(v17, v18), v18));\n }\n while ( v12 != v14 );\n v19 = _mm_add_epi32(v13, _mm_srli_si128(v13, 8));\n result = (unsigned int)_mm_cvtsi128_si32(_mm_add_epi32(v19, _mm_srli_si128(v19, 4)));\n if ( (a3 & 3) != 0 )\n {\n v21 = a3 & 0xFFFFFFFC;\n v22 = a1->m128i_i32[v21] - a2->m128i_i32[v21];\n v23 = (int)(a3 & 0xFFFFFFFC);\n if ( a2->m128i_i32[v21] - a1->m128i_i32[v21] >= 0 )\n v22 = a2->m128i_i32[v21] - a1->m128i_i32[v21];\n result = (unsigned int)(v22 + result);\n if ( a3 > v21 + 1 )\n {\nLABEL_23:\n v24 = a1->m128i_i32[v23 + 1] - a2->m128i_i32[v23 + 1];\n if ( a2->m128i_i32[v23 + 1] - a1->m128i_i32[v23 + 1] >= 0 )\n v24 = a2->m128i_i32[v23 + 1] - a1->m128i_i32[v23 + 1];\n result = (unsigned int)(v24 + result);\n if ( a3 > v21 + 2 )\n {\n v25 = a1->m128i_i32[v23 + 2] - a2->m128i_i32[v23 + 2];\n if ( a2->m128i_i32[v23 + 2] - a1->m128i_i32[v23 + 2] >= 0 )\n v25 = a2->m128i_i32[v23 + 2] - a1->m128i_i32[v23 + 2];\n return (unsigned int)(v25 + result);\n }\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1320:\nendbr64\nmov r8, rdi\nmov r9, rsi\nmov r10d, edx\nmov edi, edx\nlea r11, [r8+4]\ncmp edx, 1\njle loc_14C0\nnop dword ptr [rax+00h]\nloc_1340:\nlea edx, [rdi-2]\nmov rax, r8\nlea rsi, [r11+rdx*4]\nnop word ptr [rax+rax+00h]\nloc_1350:\nmovq xmm0, qword ptr [rax]\npshufd xmm3, xmm0, 0E5h\nmovd edx, xmm0\nmovd ecx, xmm3\ncmp ecx, edx\njge short loc_136E\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_136E:\nadd rax, 4\ncmp rax, rsi\njnz short loc_1350\nsub edi, 1\ncmp edi, 1\njz short loc_1390\nloc_137F:\ncmp edi, 1\njg short loc_1340\nsub edi, 1\njmp short loc_137F\nloc_1390:\nmov edi, r10d\nlea r11, [r9+4]\nnop word ptr [rax+rax+00000000h]\nloc_13A0:\ncmp edi, 1\njle loc_14B8\nlea edx, [rdi-2]\nmov rax, r9\nlea rsi, [r11+rdx*4]\nnop dword ptr [rax+rax+00h]\nloc_13B8:\nmovq xmm0, qword ptr [rax]\npshufd xmm4, xmm0, 0E5h\nmovd edx, xmm0\nmovd ecx, xmm4\ncmp ecx, edx\njge short loc_13D6\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_13D6:\nadd rax, 4\ncmp rax, rsi\njnz short loc_13B8\nsub edi, 1\ncmp edi, 1\njnz short loc_13A0\nlea eax, [r10-1]\ncmp eax, 2\njbe loc_14CF\nmov edx, r10d\nxor eax, eax\npxor xmm1, xmm1\nshr edx, 2\nshl rdx, 4\nnop dword ptr [rax+00h]\nloc_1408:\nmovdqu xmm0, xmmword ptr [r8+rax]\nmovdqu xmm5, xmmword ptr [r9+rax]\nadd rax, 10h\npsubd xmm0, xmm5\nmovdqa xmm2, xmm0\npsrad xmm2, 1Fh\npxor xmm0, xmm2\npsubd xmm0, xmm2\npaddd xmm1, xmm0\ncmp rax, rdx\njnz short loc_1408\nmovdqa xmm0, xmm1\npsrldq xmm0, 8\npaddd xmm1, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm0, 4\npaddd xmm1, xmm0\nmovd eax, xmm1\ntest r10b, 3\njz short locret_14B3\nmov edx, r10d\nand edx, 0FFFFFFFCh\nmovsxd rdi, edx\nmov ecx, [r8+rdi*4]\nsub ecx, [r9+rdi*4]\nlea rsi, ds:0[rdi*4]\nmov edi, ecx\nneg edi\ncmovns ecx, edi\nadd eax, ecx\nlea ecx, [rdx+1]\ncmp r10d, ecx\njle short locret_14B3\nloc_1484:\nmov ecx, [r8+rsi+4]\nsub ecx, [r9+rsi+4]\nmov edi, ecx\nneg edi\ncmovns ecx, edi\nadd edx, 2\nadd eax, ecx\ncmp r10d, edx\njle short locret_14B3\nmov edx, [r8+rsi+8]\nsub edx, [r9+rsi+8]\nmov ecx, edx\nneg ecx\ncmovns edx, ecx\nadd eax, edx\nretn\nlocret_14B3:\nretn\nloc_14B8:\nsub edi, 1\njmp loc_13A0\nloc_14C0:\njnz short loc_14E2\nmov edx, [r8]\nsub edx, [rsi]\nmov eax, edx\nneg eax\ncmovs eax, edx\nretn\nloc_14CF:\nmov edx, [r8]\nsub edx, [r9]\nmov eax, edx\nneg eax\ncmovs eax, edx\nxor edx, edx\nxor esi, esi\njmp short loc_1484\nloc_14E2:\nxor eax, eax\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1320(__m128i *a1, __m128i *a2, int a3)\n{\n int v6; // edi\n __m128i *v7; // rax\n __m128i v8; // xmm0\n int i; // edi\n __m128i *v10; // rax\n __m128i v11; // xmm0\n unsigned __int64 v12; // rax\n __m128i v13; // xmm1\n __int64 v14; // rdx\n __m128i v15; // xmm0\n __m128i v16; // xmm5\n __m128i v17; // xmm0\n __m128i v18; // xmm2\n __m128i v19; // xmm1\n __int64 result; // rax\n signed int v21; // edx\n int v22; // ecx\n __int64 v23; // rsi\n int v24; // ecx\n int v25; // edx\n\n v6 = a3;\n if ( a3 <= 1 )\n {\n if ( a3 == 1 )\n {\n result = (unsigned int)(a2->m128i_i32[0] - a1->m128i_i32[0]);\n if ( a2->m128i_i32[0] - a1->m128i_i32[0] < 0 )\n return (unsigned int)(a1->m128i_i32[0] - a2->m128i_i32[0]);\n }\n else\n {\n return 0LL;\n }\n }\n else\n {\n while ( 1 )\n {\n v7 = a1;\n do\n {\n v8 = _mm_loadl_epi64(v7);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v8, 229)) < _mm_cvtsi128_si32(v8) )\n v7->m128i_i64[0] = _mm_shuffle_epi32(v8, 225).m128i_u64[0];\n v7 = (__m128i *)((char *)v7 + 4);\n }\n while ( v7 != (__m128i *)((char *)a1->m128i_i64 + 4 * (unsigned int)(v6 - 2) + 4) );\n if ( --v6 == 1 )\n break;\n while ( v6 <= 1 )\n --v6;\n }\n for ( i = a3; i != 1; --i )\n {\n while ( i <= 1 )\n --i;\n v10 = a2;\n do\n {\n v11 = _mm_loadl_epi64(v10);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v11, 229)) < _mm_cvtsi128_si32(v11) )\n v10->m128i_i64[0] = _mm_shuffle_epi32(v11, 225).m128i_u64[0];\n v10 = (__m128i *)((char *)v10 + 4);\n }\n while ( v10 != (__m128i *)((char *)a2->m128i_i64 + 4 * (unsigned int)(i - 2) + 4) );\n }\n if ( (unsigned int)(a3 - 1) <= 2 )\n {\n LODWORD(result) = a2->m128i_i32[0] - a1->m128i_i32[0];\n if ( (int)result < 0 )\n LODWORD(result) = a1->m128i_i32[0] - a2->m128i_i32[0];\n v21 = 0;\n v23 = 0LL;\n goto LABEL_23;\n }\n v12 = 0LL;\n v13 = 0LL;\n v14 = 16LL * ((unsigned int)a3 >> 2);\n do\n {\n v15 = _mm_loadu_si128(&a1[v12 / 0x10]);\n v16 = _mm_loadu_si128(&a2[v12 / 0x10]);\n v12 += 16LL;\n v17 = _mm_sub_epi32(v15, v16);\n v18 = _mm_srai_epi32(v17, 0x1Fu);\n v13 = _mm_add_epi32(v13, _mm_sub_epi32(_mm_xor_si128(v17, v18), v18));\n }\n while ( v12 != v14 );\n v19 = _mm_add_epi32(v13, _mm_srli_si128(v13, 8));\n result = (unsigned int)_mm_cvtsi128_si32(_mm_add_epi32(v19, _mm_srli_si128(v19, 4)));\n if ( (a3 & 3) != 0 )\n {\n v21 = a3 & 0xFFFFFFFC;\n v22 = a1->m128i_i32[v21] - a2->m128i_i32[v21];\n v23 = (int)(a3 & 0xFFFFFFFC);\n if ( a2->m128i_i32[v21] - a1->m128i_i32[v21] >= 0 )\n v22 = a2->m128i_i32[v21] - a1->m128i_i32[v21];\n result = (unsigned int)(v22 + result);\n if ( a3 > v21 + 1 )\n {\nLABEL_23:\n v24 = a1->m128i_i32[v23 + 1] - a2->m128i_i32[v23 + 1];\n if ( a2->m128i_i32[v23 + 1] - a1->m128i_i32[v23 + 1] >= 0 )\n v24 = a2->m128i_i32[v23 + 1] - a1->m128i_i32[v23 + 1];\n result = (unsigned int)(v24 + result);\n if ( a3 > v21 + 2 )\n {\n v25 = a1->m128i_i32[v23 + 2] - a2->m128i_i32[v23 + 2];\n if ( a2->m128i_i32[v23 + 2] - a1->m128i_i32[v23 + 2] >= 0 )\n v25 = a2->m128i_i32[v23 + 2] - a1->m128i_i32[v23 + 2];\n return (unsigned int)(v25 + result);\n }\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1320(__m128i *a1, __m128i *a2, int a3) {\n int v6;\n __m128i *v7;\n __m128i v8;\n int i;\n __m128i *v10;\n __m128i v11;\n unsigned long long v12;\n __m128i v13;\n long long v14;\n __m128i v15;\n __m128i v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n long long result;\n signed int v21;\n int v22;\n long long v23;\n int v24;\n int v25;\n v6 = a3;\n if (a3 <= 1) {\n if (a3 == 1) {\n result = (unsigned int)(a2->m128i_i32[0] - a1->m128i_i32[0]);\n if (a2->m128i_i32[0] - a1->m128i_i32[0] < 0)\n return (unsigned int)(a1->m128i_i32[0] - a2->m128i_i32[0]);\n } else {\n return 0LL;\n }\n } else {\n while (1) {\n v7 = a1;\n do {\n v8 = _mm_loadl_epi64(v7);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v8, 229)) <\n _mm_cvtsi128_si32(v8))\n v7->m128i_i64[0] = _mm_shuffle_epi32(v8, 225).m128i_u64[0];\n v7 = (__m128i *)((char *)v7 + 4);\n } while (v7 != (__m128i *)((char *)a1->m128i_i64 +\n 4 * (unsigned int)(v6 - 2) + 4));\n if (--v6 == 1) break;\n while (v6 <= 1) --v6;\n }\n for (i = a3; i != 1; --i) {\n while (i <= 1) --i;\n v10 = a2;\n do {\n v11 = _mm_loadl_epi64(v10);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v11, 229)) <\n _mm_cvtsi128_si32(v11))\n v10->m128i_i64[0] = _mm_shuffle_epi32(v11, 225).m128i_u64[0];\n v10 = (__m128i *)((char *)v10 + 4);\n } while (v10 != (__m128i *)((char *)a2->m128i_i64 +\n 4 * (unsigned int)(i - 2) + 4));\n }\n if ((unsigned int)(a3 - 1) <= 2) {\n LODWORD(result) = a2->m128i_i32[0] - a1->m128i_i32[0];\n if ((int)result < 0)\n LODWORD(result) = a1->m128i_i32[0] - a2->m128i_i32[0];\n v21 = 0;\n v23 = 0LL;\n goto LABEL_23;\n }\n v12 = 0LL;\n v13 = 0LL;\n v14 = 16LL * ((unsigned int)a3 >> 2);\n do {\n v15 = _mm_loadu_si128(&a1[v12 / 16]);\n v16 = _mm_loadu_si128(&a2[v12 / 16]);\n v12 += 16LL;\n v17 = _mm_sub_epi32(v15, v16);\n v18 = _mm_srai_epi32(v17, 31u);\n v13 = _mm_add_epi32(v13, _mm_sub_epi32(_mm_xor_si128(v17, v18), v18));\n } while (v12 != v14);\n v19 = _mm_add_epi32(v13, _mm_srli_si128(v13, 8));\n result = (unsigned int)_mm_cvtsi128_si32(\n _mm_add_epi32(v19, _mm_srli_si128(v19, 4)));\n if ((a3 & 3) != 0) {\n v21 = a3 & 4294967292;\n v22 = a1->m128i_i32[v21] - a2->m128i_i32[v21];\n v23 = (int)(a3 & 4294967292);\n if (a2->m128i_i32[v21] - a1->m128i_i32[v21] >= 0)\n v22 = a2->m128i_i32[v21] - a1->m128i_i32[v21];\n result = (unsigned int)(v22 + result);\n if (a3 > v21 + 1) {\n LABEL_23:\n v24 = a1->m128i_i32[v23 + 1] - a2->m128i_i32[v23 + 1];\n if (a2->m128i_i32[v23 + 1] - a1->m128i_i32[v23 + 1] >= 0)\n v24 = a2->m128i_i32[v23 + 1] - a1->m128i_i32[v23 + 1];\n result = (unsigned int)(v24 + result);\n if (a3 > v21 + 2) {\n v25 = a1->m128i_i32[v23 + 2] - a2->m128i_i32[v23 + 2];\n if (a2->m128i_i32[v23 + 2] - a1->m128i_i32[v23 + 2] >= 0)\n v25 = a2->m128i_i32[v23 + 2] - a1->m128i_i32[v23 + 2];\n return (unsigned int)(v25 + result);\n }\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(__m128i *a1, __m128i *a2, int a3) {\n int v6;\n __m128i *v7;\n __m128i v8;\n int i;\n __m128i *v10;\n __m128i v11;\n unsigned long long v12;\n __m128i v13;\n long long v14;\n __m128i v15;\n __m128i v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n long long result;\n signed int v21;\n int v22;\n long long v23;\n int v24;\n int v25;\n v6 = a3;\n if (a3 <= 1) {\n if (a3 == 1) {\n result = (unsigned int)(a2->m128i_i32[0] - a1->m128i_i32[0]);\n if (a2->m128i_i32[0] - a1->m128i_i32[0] < 0)\n return (unsigned int)(a1->m128i_i32[0] - a2->m128i_i32[0]);\n } else {\n return 0LL;\n }\n } else {\n while (1) {\n v7 = a1;\n do {\n v8 = _mm_loadl_epi64(v7);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v8, 229)) <\n _mm_cvtsi128_si32(v8))\n v7->m128i_i64[0] = _mm_shuffle_epi32(v8, 225).m128i_u64[0];\n v7 = (__m128i *)((char *)v7 + 4);\n } while (v7 != (__m128i *)((char *)a1->m128i_i64 +\n 4 * (unsigned int)(v6 - 2) + 4));\n if (--v6 == 1) break;\n while (v6 <= 1) --v6;\n }\n for (i = a3; i != 1; --i) {\n while (i <= 1) --i;\n v10 = a2;\n do {\n v11 = _mm_loadl_epi64(v10);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v11, 229)) <\n _mm_cvtsi128_si32(v11))\n v10->m128i_i64[0] = _mm_shuffle_epi32(v11, 225).m128i_u64[0];\n v10 = (__m128i *)((char *)v10 + 4);\n } while (v10 != (__m128i *)((char *)a2->m128i_i64 +\n 4 * (unsigned int)(i - 2) + 4));\n }\n if ((unsigned int)(a3 - 1) <= 2) {\n LODWORD(result) = a2->m128i_i32[0] - a1->m128i_i32[0];\n if ((int)result < 0)\n LODWORD(result) = a1->m128i_i32[0] - a2->m128i_i32[0];\n v21 = 0;\n v23 = 0LL;\n goto LABEL_23;\n }\n v12 = 0LL;\n v13 = 0LL;\n v14 = 16LL * ((unsigned int)a3 >> 2);\n do {\n v15 = _mm_loadu_si128(&a1[v12 / 16]);\n v16 = _mm_loadu_si128(&a2[v12 / 16]);\n v12 += 16LL;\n v17 = _mm_sub_epi32(v15, v16);\n v18 = _mm_srai_epi32(v17, 31u);\n v13 = _mm_add_epi32(v13, _mm_sub_epi32(_mm_xor_si128(v17, v18), v18));\n } while (v12 != v14);\n v19 = _mm_add_epi32(v13, _mm_srli_si128(v13, 8));\n result = (unsigned int)_mm_cvtsi128_si32(\n _mm_add_epi32(v19, _mm_srli_si128(v19, 4)));\n if ((a3 & 3) != 0) {\n v21 = a3 & 4294967292;\n v22 = a1->m128i_i32[v21] - a2->m128i_i32[v21];\n v23 = (int)(a3 & 4294967292);\n if (a2->m128i_i32[v21] - a1->m128i_i32[v21] >= 0)\n v22 = a2->m128i_i32[v21] - a1->m128i_i32[v21];\n result = (unsigned int)(v22 + result);\n if (a3 > v21 + 1) {\n LABEL_23:\n v24 = a1->m128i_i32[v23 + 1] - a2->m128i_i32[v23 + 1];\n if (a2->m128i_i32[v23 + 1] - a1->m128i_i32[v23 + 1] >= 0)\n v24 = a2->m128i_i32[v23 + 1] - a1->m128i_i32[v23 + 1];\n result = (unsigned int)(v24 + result);\n if (a3 > v21 + 2) {\n v25 = a1->m128i_i32[v23 + 2] - a2->m128i_i32[v23 + 2];\n if (a2->m128i_i32[v23 + 2] - a1->m128i_i32[v23 + 2] >= 0)\n v25 = a2->m128i_i32[v23 + 2] - a1->m128i_i32[v23 + 2];\n return (unsigned int)(v25 + result);\n }\n }\n }\n }\n return result;\n}" + }, + { + "index": 657, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int fact = 1;\n for (int i = 2; i <= n; i++) {\n fact = fact * i;\n while (fact % 10 == 0) {\n fact = fact / 10;\n }\n }\n while (fact >= 10) {\n fact = fact / 10;\n }\n return floor(fact);\n}", + "test": "int main() {\n\n assert(func0(5) == 1);\n\n assert(func0(10) == 3);\n\n assert(func0(7) == 5);\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmovl $0x1,-0x8(%rbp)\nmovl $0x2,-0x4(%rbp)\njmp 11c0 \nmov -0x8(%rbp),%eax\nimul -0x4(%rbp),%eax\nmov %eax,-0x8(%rbp)\njmp 118e \nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nimul $0x66666667,%rdx,%rdx\nshr $0x20,%rdx\nsar $0x2,%edx\nsar $0x1f,%eax\nsub %eax,%edx\nmov %edx,%eax\nmov %eax,-0x8(%rbp)\nmov -0x8(%rbp),%ecx\nmovslq %ecx,%rax\nimul $0x66666667,%rax,%rax\nshr $0x20,%rax\nmov %eax,%edx\nsar $0x2,%edx\nmov %ecx,%eax\nsar $0x1f,%eax\nsub %eax,%edx\nmov %edx,%eax\nshl $0x2,%eax\nadd %edx,%eax\nadd %eax,%eax\nsub %eax,%ecx\nmov %ecx,%edx\ntest %edx,%edx\nje 1170 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x14(%rbp),%eax\njle 1164 \njmp 11e8 \nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nimul $0x66666667,%rdx,%rdx\nshr $0x20,%rdx\nsar $0x2,%edx\nsar $0x1f,%eax\nsub %eax,%edx\nmov %edx,%eax\nmov %eax,-0x8(%rbp)\ncmpl $0x9,-0x8(%rbp)\njg 11ca \ncvtsi2sdl -0x8(%rbp),%xmm0\ncvttsd2si %xmm0,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_8], 1\nmov [rbp+var_4], 2\njmp short loc_11C0\nloc_1164:\nmov eax, [rbp+var_8]\nimul eax, [rbp+var_4]\nmov [rbp+var_8], eax\njmp short loc_118E\nloc_1170:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_8], eax\nloc_118E:\nmov ecx, [rbp+var_8]\nmovsxd rax, ecx\nimul rax, 66666667h\nshr rax, 20h\nmov edx, eax\nsar edx, 2\nmov eax, ecx\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nsub ecx, eax\nmov edx, ecx\ntest edx, edx\njz short loc_1170\nadd [rbp+var_4], 1\nloc_11C0:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_14]\njle short loc_1164\njmp short loc_11E8\nloc_11CA:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_8], eax\nloc_11E8:\ncmp [rbp+var_8], 9\njg short loc_11CA\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_8]\ncvttsd2si eax, xmm0\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v2; // [rsp+Ch] [rbp-8h]\n int i; // [rsp+10h] [rbp-4h]\n\n v2 = 1;\n for ( i = 2; i <= a1; ++i )\n {\n for ( v2 *= i; !(v2 % 10); v2 /= 10 )\n ;\n }\n while ( v2 > 9 )\n v2 /= 10;\n return (unsigned int)(int)(double)v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_8], 1\nmov [rbp+var_4], 2\njmp short loc_11C0\nloc_1164:\nmov eax, [rbp+var_8]\nimul eax, [rbp+var_4]\nmov [rbp+var_8], eax\njmp short loc_118E\nloc_1170:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_8], eax\nloc_118E:\nmov ecx, [rbp+var_8]\nmovsxd rax, ecx\nimul rax, 66666667h\nshr rax, 20h\nmov edx, eax\nsar edx, 2\nmov eax, ecx\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nsub ecx, eax\nmov edx, ecx\ntest edx, edx\njz short loc_1170\nadd [rbp+var_4], 1\nloc_11C0:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_14]\njle short loc_1164\njmp short loc_11E8\nloc_11CA:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_8], eax\nloc_11E8:\ncmp [rbp+var_8], 9\njg short loc_11CA\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_8]\ncvttsd2si eax, xmm0\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v2; // [rsp+Ch] [rbp-8h]\n int i; // [rsp+10h] [rbp-4h]\n\n v2 = 1;\n for ( i = 2; i <= a1; ++i )\n {\n for ( v2 *= i; !(v2 % 10); v2 /= 10 )\n ;\n }\n while ( v2 > 9 )\n v2 /= 10;\n return (unsigned int)(int)(double)v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v2;\n int i;\n v2 = 1;\n for (i = 2; i <= a1; ++i) {\n for (v2 *= i; !(v2 % 10); v2 /= 10)\n ;\n }\n while (v2 > 9) v2 /= 10;\n return (unsigned int)(int)(double)v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v2;\n int i;\n v2 = 1;\n for (i = 2; i <= a1; ++i) {\n for (v2 *= i; !(v2 % 10); v2 /= 10)\n ;\n }\n while (v2 > 9) v2 /= 10;\n return (unsigned int)(int)(double)v2;\n}" + }, + { + "index": 657, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int fact = 1;\n for (int i = 2; i <= n; i++) {\n fact = fact * i;\n while (fact % 10 == 0) {\n fact = fact / 10;\n }\n }\n while (fact >= 10) {\n fact = fact / 10;\n }\n return floor(fact);\n}", + "test": "int main() {\n\n assert(func0(5) == 1);\n\n assert(func0(10) == 3);\n\n assert(func0(7) == 5);\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nlea 0x1(%rdi),%r9d\nmov $0x2,%r8d\nmov $0x2,%eax\ncmp $0x1,%edi\njle 11c1 \nadd $0x1,%r8d\ncmp %r9d,%r8d\nje 11c7 \nimul %r8d,%eax\nmovslq %eax,%rdx\nimul $0x66666667,%rdx,%rdx\nsar $0x22,%rdx\nmov %eax,%ecx\nsar $0x1f,%ecx\nsub %ecx,%edx\nlea (%rdx,%rdx,4),%edx\nadd %edx,%edx\ncmp %edx,%eax\njne 1161 \nmovslq %eax,%rdx\nimul $0x66666667,%rdx,%rdx\nsar $0x22,%rdx\nsar $0x1f,%eax\nsub %eax,%edx\nmov %edx,%eax\nmovslq %edx,%rcx\nimul $0x66666667,%rcx,%rcx\nsar $0x22,%rcx\nmov %edx,%esi\nsar $0x1f,%esi\nsub %esi,%ecx\nlea (%rcx,%rcx,4),%ecx\nadd %ecx,%ecx\ncmp %ecx,%edx\nje 118c \njmp 1161 \nmov $0x1,%eax\nretq\ncmp $0x9,%eax\njle 11e8 \nmov %eax,%ecx\nmovslq %eax,%rdx\nimul $0x66666667,%rdx,%rdx\nsar $0x22,%rdx\nsar $0x1f,%eax\nsub %eax,%edx\nmov %edx,%eax\ncmp $0x63,%ecx\njg 11cc \nretq\n", + "ida_asm": "func0:\nendbr64\ncmp edi, 1\njle loc_11E6\nlea r8d, [rdi+1]\nmov edi, 2\nmov ecx, 1\nloc_1164:\nimul ecx, edi\nmovsxd rax, ecx\nimul rax, 66666667h\nsar rax, 22h\nmov edx, ecx\nsar edx, 1Fh\nsub eax, edx\nlea eax, [rax+rax*4]\nadd eax, eax\ncmp ecx, eax\njnz short loc_11B8\nloc_1185:\nmovsxd rax, ecx\nimul rax, 66666667h\nsar rax, 22h\nsar ecx, 1Fh\nsub eax, ecx\nmov ecx, eax\nmovsxd rdx, eax\nimul rdx, 66666667h\nsar rdx, 22h\nmov esi, eax\nsar esi, 1Fh\nsub edx, esi\nlea edx, [rdx+rdx*4]\nadd edx, edx\ncmp eax, edx\njz short loc_1185\nloc_11B8:\nadd edi, 1\ncmp r8d, edi\njnz short loc_1164\ncmp ecx, 9\njle short loc_11E3\nloc_11C5:\nmov edx, ecx\nmovsxd rax, ecx\nimul rax, 66666667h\nsar rax, 22h\nmov esi, ecx\nsar esi, 1Fh\nsub eax, esi\nmov ecx, eax\ncmp edx, 63h ; 'c'\njg short loc_11C5\nloc_11E3:\nmov eax, ecx\nretn\nloc_11E6:\nmov ecx, 1\njmp short loc_11E3", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // r8d\n int v2; // edi\n int v3; // ecx\n int v4; // edx\n\n if ( a1 <= 1 )\n {\n return 1;\n }\n else\n {\n v1 = a1 + 1;\n v2 = 2;\n v3 = 1;\n do\n {\n for ( v3 *= v2; v3 == 10 * (v3 / 10); v3 /= 10 )\n ;\n ++v2;\n }\n while ( v1 != v2 );\n if ( v3 > 9 )\n {\n do\n {\n v4 = v3;\n v3 /= 10;\n }\n while ( v4 > 99 );\n }\n }\n return (unsigned int)v3;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ncmp edi, 1\njle loc_11E6\nlea r8d, [rdi+1]\nmov edi, 2\nmov ecx, 1\nloc_1164:\nimul ecx, edi\nmovsxd rax, ecx\nimul rax, 66666667h\nsar rax, 22h\nmov edx, ecx\nsar edx, 1Fh\nsub eax, edx\nlea eax, [rax+rax*4]\nadd eax, eax\ncmp ecx, eax\njnz short loc_11B8\nloc_1185:\nmovsxd rax, ecx\nimul rax, 66666667h\nsar rax, 22h\nsar ecx, 1Fh\nsub eax, ecx\nmov ecx, eax\nmovsxd rdx, eax\nimul rdx, 66666667h\nsar rdx, 22h\nmov esi, eax\nsar esi, 1Fh\nsub edx, esi\nlea edx, [rdx+rdx*4]\nadd edx, edx\ncmp eax, edx\njz short loc_1185\nloc_11B8:\nadd edi, 1\ncmp r8d, edi\njnz short loc_1164\ncmp ecx, 9\njle short loc_11E3\nloc_11C5:\nmov edx, ecx\nmovsxd rax, ecx\nimul rax, 66666667h\nsar rax, 22h\nmov esi, ecx\nsar esi, 1Fh\nsub eax, esi\nmov ecx, eax\ncmp edx, 63h ; 'c'\njg short loc_11C5\nloc_11E3:\nmov eax, ecx\nretn\nloc_11E6:\nmov ecx, 1\njmp short loc_11E3", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v1; // r8d\n int v2; // edi\n int v3; // ecx\n int v4; // edx\n\n if ( a1 <= 1 )\n {\n return 1;\n }\n else\n {\n v1 = a1 + 1;\n v2 = 2;\n v3 = 1;\n do\n {\n for ( v3 *= v2; v3 == 10 * (v3 / 10); v3 /= 10 )\n ;\n ++v2;\n }\n while ( v1 != v2 );\n if ( v3 > 9 )\n {\n do\n {\n v4 = v3;\n v3 /= 10;\n }\n while ( v4 > 99 );\n }\n }\n return (unsigned int)v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v1;\n int v2;\n int v3;\n int v4;\n if (a1 <= 1) {\n return 1;\n } else {\n v1 = a1 + 1;\n v2 = 2;\n v3 = 1;\n do {\n for (v3 *= v2; v3 == 10 * (v3 / 10); v3 /= 10)\n ;\n ++v2;\n } while (v1 != v2);\n if (v3 > 9) {\n do {\n v4 = v3;\n v3 /= 10;\n } while (v4 > 99);\n }\n }\n return (unsigned int)v3;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v2;\n int v3;\n int v4;\n if (a1 <= 1) {\n return 1;\n } else {\n v1 = a1 + 1;\n v2 = 2;\n v3 = 1;\n do {\n for (v3 *= v2; v3 == 10 * (v3 / 10); v3 /= 10)\n ;\n ++v2;\n } while (v1 != v2);\n if (v3 > 9) {\n do {\n v4 = v3;\n v3 /= 10;\n } while (v4 > 99);\n }\n }\n return (unsigned int)v3;\n}" + }, + { + "index": 657, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int fact = 1;\n for (int i = 2; i <= n; i++) {\n fact = fact * i;\n while (fact % 10 == 0) {\n fact = fact / 10;\n }\n }\n while (fact >= 10) {\n fact = fact / 10;\n }\n return floor(fact);\n}", + "test": "int main() {\n\n assert(func0(5) == 1);\n\n assert(func0(10) == 3);\n\n assert(func0(7) == 5);\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nlea 0x1(%rdi),%esi\nmov $0x2,%ecx\nmov $0x2,%eax\ncmp $0x1,%edi\njle 13b3 \nnopw %cs:0x0(%rax,%rax,1)\nadd $0x1,%ecx\ncmp %esi,%ecx\nje 1390 \nimul %ecx,%eax\nnopw 0x0(%rax,%rax,1)\nimul $0xcccccccd,%eax,%edx\nadd $0x19999998,%edx\nror %edx\ncmp $0x19999998,%edx\nja 1350 \nmovslq %eax,%rdx\nsar $0x1f,%eax\nimul $0x66666667,%rdx,%rdx\nsar $0x22,%rdx\nsub %eax,%edx\nmov %edx,%eax\njmp 1360 \nnopl (%rax)\ncmp $0x9,%eax\njle 13b2 \nmov $0xcccccccd,%ecx\nnopw 0x0(%rax,%rax,1)\nmov %eax,%eax\nmov %rax,%rdx\nimul %rcx,%rax\nshr $0x23,%rax\ncmp $0x63,%edx\njg 13a0 \nretq\nmov $0x1,%eax\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\ncmp edi, 1\njle short loc_1273\nadd edi, 1\nmov esi, 2\nmov eax, 1\nnop word ptr [rax+rax+00000000h]\nloc_1210:\nimul eax, esi\njmp short loc_122F\nloc_1218:\nmovsxd rdx, eax\nsar eax, 1Fh\nimul rdx, 66666667h\nmov ecx, eax\nsar rdx, 22h\nmov eax, edx\nsub eax, ecx\nloc_122F:\nimul edx, eax, 0CCCCCCCDh\nadd edx, 19999998h\nror edx, 1\ncmp edx, 19999998h\njbe short loc_1218\nadd esi, 1\ncmp edi, esi\njnz short loc_1210\ncmp eax, 9\njle short locret_1278\nmov ecx, 0CCCCCCCDh\nnop word ptr [rax+rax+00000000h]\nloc_1260:\nmov eax, eax\nmov rdx, rax\nimul rax, rcx\nshr rax, 23h\ncmp edx, 63h ; 'c'\njg short loc_1260\nretn\nloc_1273:\nmov eax, 1\nlocret_1278:\nretn", + "ida_pseudo": "unsigned __int64 __fastcall func0(int a1)\n{\n int v1; // edi\n int v2; // esi\n unsigned __int64 result; // rax\n int v4; // edx\n\n if ( a1 <= 1 )\n return 1LL;\n v1 = a1 + 1;\n v2 = 2;\n LODWORD(result) = 1;\n do\n {\n for ( result = (unsigned int)(v2 * result);\n __ROR4__(-858993459 * result + 429496728, 1) <= 0x19999998u;\n result = (unsigned int)((int)result / 10) )\n {\n ;\n }\n ++v2;\n }\n while ( v1 != v2 );\n if ( (int)result > 9 )\n {\n do\n {\n v4 = result;\n result = (unsigned int)result / 0xAuLL;\n }\n while ( v4 > 99 );\n }\n return result;\n}", + "ida_strip_asm": "sub_11F0:\nendbr64\ncmp edi, 1\njle short loc_1273\nadd edi, 1\nmov esi, 2\nmov eax, 1\nnop word ptr [rax+rax+00000000h]\nloc_1210:\nimul eax, esi\njmp short loc_122F\nloc_1218:\nmovsxd rdx, eax\nsar eax, 1Fh\nimul rdx, 66666667h\nmov ecx, eax\nsar rdx, 22h\nmov eax, edx\nsub eax, ecx\nloc_122F:\nimul edx, eax, 0CCCCCCCDh\nadd edx, 19999998h\nror edx, 1\ncmp edx, 19999998h\njbe short loc_1218\nadd esi, 1\ncmp edi, esi\njnz short loc_1210\ncmp eax, 9\njle short locret_1278\nmov ecx, 0CCCCCCCDh\nnop word ptr [rax+rax+00000000h]\nloc_1260:\nmov eax, eax\nmov rdx, rax\nimul rax, rcx\nshr rax, 23h\ncmp edx, 63h ; 'c'\njg short loc_1260\nretn\nloc_1273:\nmov eax, 1\nlocret_1278:\nretn", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_11F0(int a1)\n{\n int v1; // edi\n int v2; // esi\n unsigned __int64 result; // rax\n int v4; // edx\n\n if ( a1 <= 1 )\n return 1LL;\n v1 = a1 + 1;\n v2 = 2;\n LODWORD(result) = 1;\n do\n {\n for ( result = (unsigned int)(v2 * result);\n __ROR4__(-858993459 * result + 429496728, 1) <= 0x19999998u;\n result = (unsigned int)((int)result / 10) )\n {\n ;\n }\n ++v2;\n }\n while ( v1 != v2 );\n if ( (int)result > 9 )\n {\n do\n {\n v4 = result;\n result = (unsigned int)result / 0xAuLL;\n }\n while ( v4 > 99 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_11F0(int a1) {\n int v1;\n int v2;\n unsigned long long result;\n int v4;\n if (a1 <= 1) return 1LL;\n v1 = a1 + 1;\n v2 = 2;\n LODWORD(result) = 1;\n do {\n for (result = (unsigned int)(v2 * result);\n __ROR4__(-858993459 * result + 429496728, 1) <= 429496728u;\n result = (unsigned int)((int)result / 10)) {\n ;\n }\n ++v2;\n } while (v1 != v2);\n if ((int)result > 9) {\n do {\n v4 = result;\n result = (unsigned int)result / 10uLL;\n } while (v4 > 99);\n }\n return result;\n}", + "ida_pseudo_norm": "unsigned long long func0(int a1) {\n int v1;\n int v2;\n unsigned long long result;\n int v4;\n if (a1 <= 1) return 1LL;\n v1 = a1 + 1;\n v2 = 2;\n LODWORD(result) = 1;\n do {\n for (result = (unsigned int)(v2 * result);\n __ROR4__(-858993459 * result + 429496728, 1) <= 429496728u;\n result = (unsigned int)((int)result / 10)) {\n ;\n }\n ++v2;\n } while (v1 != v2);\n if ((int)result > 9) {\n do {\n v4 = result;\n result = (unsigned int)result / 10uLL;\n } while (v4 > 99);\n }\n return result;\n}" + }, + { + "index": 658, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int list1[], int length) {\n int max_val = 0;\n int result = list1[0];\n for (int i = 0; i < length; i++) {\n int occu = 0;\n for (int j = 0; j < length; j++) {\n if (list1[j] == list1[i]) {\n occu++;\n }\n }\n if (occu > max_val) {\n max_val = occu;\n result = list1[i];\n }\n }\n return result;\n}", + "test": "int main() {\n\n int list1[] = {2, 3, 8, 4, 7, 9, 8, 2, 6, 5, 1, 6, 1, 2, 3, 4, 6, 9, 1, 2};\n\n int list2[] = {1, 3, 5, 7, 1, 3, 13, 15, 17, 5, 7, 9, 1, 11};\n\n int list3[] = {1, 2, 3, 2, 4, 5, 1, 1, 1};\n\n\n\n assert(func0(list1, sizeof(list1)/sizeof(list1[0])) == 2);\n\n assert(func0(list2, sizeof(list2)/sizeof(list2[0])) == 1);\n\n assert(func0(list3, sizeof(list3)/sizeof(list3[0])) == 1);\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmovl $0x0,-0x14(%rbp)\nmov -0x28(%rbp),%rax\nmov (%rax),%eax\nmov %eax,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 122c \nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11f9 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 11f5 \naddl $0x1,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 11c1 \nmov -0x8(%rbp),%eax\ncmp -0x14(%rbp),%eax\njle 1228 \nmov -0x8(%rbp),%eax\nmov %eax,-0x14(%rbp)\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x10(%rbp)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 11b1 \nmov -0x10(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_14], 0\nmov rax, [rbp+var_28]\nmov eax, [rax]\nmov [rbp+var_10], eax\nmov [rbp+var_C], 0\njmp short loc_122C\nloc_11B1:\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11F9\nloc_11C1:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11F5\nadd [rbp+var_8], 1\nloc_11F5:\nadd [rbp+var_4], 1\nloc_11F9:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_2C]\njl short loc_11C1\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_14]\njle short loc_1228\nmov eax, [rbp+var_8]\nmov [rbp+var_14], eax\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_10], eax\nloc_1228:\nadd [rbp+var_C], 1\nloc_122C:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_2C]\njl loc_11B1\nmov eax, [rbp+var_10]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n int v3; // [rsp+18h] [rbp-14h]\n unsigned int v4; // [rsp+1Ch] [rbp-10h]\n int i; // [rsp+20h] [rbp-Ch]\n int v6; // [rsp+24h] [rbp-8h]\n int j; // [rsp+28h] [rbp-4h]\n\n v3 = 0;\n v4 = *a1;\n for ( i = 0; i < a2; ++i )\n {\n v6 = 0;\n for ( j = 0; j < a2; ++j )\n {\n if ( a1[j] == a1[i] )\n ++v6;\n }\n if ( v6 > v3 )\n {\n v3 = v6;\n v4 = a1[i];\n }\n }\n return v4;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_14], 0\nmov rax, [rbp+var_28]\nmov eax, [rax]\nmov [rbp+var_10], eax\nmov [rbp+var_C], 0\njmp short loc_122C\nloc_11B1:\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11F9\nloc_11C1:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11F5\nadd [rbp+var_8], 1\nloc_11F5:\nadd [rbp+var_4], 1\nloc_11F9:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_2C]\njl short loc_11C1\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_14]\njle short loc_1228\nmov eax, [rbp+var_8]\nmov [rbp+var_14], eax\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_10], eax\nloc_1228:\nadd [rbp+var_C], 1\nloc_122C:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_2C]\njl loc_11B1\nmov eax, [rbp+var_10]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(unsigned int *a1, int a2)\n{\n int v3; // [rsp+18h] [rbp-14h]\n unsigned int v4; // [rsp+1Ch] [rbp-10h]\n int i; // [rsp+20h] [rbp-Ch]\n int v6; // [rsp+24h] [rbp-8h]\n int j; // [rsp+28h] [rbp-4h]\n\n v3 = 0;\n v4 = *a1;\n for ( i = 0; i < a2; ++i )\n {\n v6 = 0;\n for ( j = 0; j < a2; ++j )\n {\n if ( a1[j] == a1[i] )\n ++v6;\n }\n if ( v6 > v3 )\n {\n v3 = v6;\n v4 = a1[i];\n }\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(unsigned int *a1, int a2) {\n int v3;\n unsigned int v4;\n int i;\n int v6;\n int j;\n v3 = 0;\n v4 = *a1;\n for (i = 0; i < a2; ++i) {\n v6 = 0;\n for (j = 0; j < a2; ++j) {\n if (a1[j] == a1[i]) ++v6;\n }\n if (v6 > v3) {\n v3 = v6;\n v4 = a1[i];\n }\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n int v3;\n unsigned int v4;\n int i;\n int v6;\n int j;\n v3 = 0;\n v4 = *a1;\n for (i = 0; i < a2; ++i) {\n v6 = 0;\n for (j = 0; j < a2; ++j) {\n if (a1[j] == a1[i]) ++v6;\n }\n if (v6 > v3) {\n v3 = v6;\n v4 = a1[i];\n }\n }\n return v4;\n}" + }, + { + "index": 658, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int list1[], int length) {\n int max_val = 0;\n int result = list1[0];\n for (int i = 0; i < length; i++) {\n int occu = 0;\n for (int j = 0; j < length; j++) {\n if (list1[j] == list1[i]) {\n occu++;\n }\n }\n if (occu > max_val) {\n max_val = occu;\n result = list1[i];\n }\n }\n return result;\n}", + "test": "int main() {\n\n int list1[] = {2, 3, 8, 4, 7, 9, 8, 2, 6, 5, 1, 6, 1, 2, 3, 4, 6, 9, 1, 2};\n\n int list2[] = {1, 3, 5, 7, 1, 3, 13, 15, 17, 5, 7, 9, 1, 11};\n\n int list3[] = {1, 2, 3, 2, 4, 5, 1, 1, 1};\n\n\n\n assert(func0(list1, sizeof(list1)/sizeof(list1[0])) == 2);\n\n assert(func0(list2, sizeof(list2)/sizeof(list2[0])) == 1);\n\n assert(func0(list3, sizeof(list3)/sizeof(list3[0])) == 1);\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov (%rdi),%r11d\ntest %esi,%esi\njle 11da \nmov %rdi,%r10\nlea -0x1(%rsi),%eax\nlea 0x4(%rdi,%rax,4),%r8\nmov $0x0,%r9d\njmp 11b0 \nadd $0x4,%rdi\ncmp %r8,%rdi\nje 11da \nmov (%rdi),%esi\nmov %r10,%rax\nmov $0x0,%edx\ncmp %esi,(%rax)\nsete %cl\nmovzbl %cl,%ecx\nadd %ecx,%edx\nadd $0x4,%rax\ncmp %r8,%rax\njne 11ba \ncmp %r9d,%edx\njle 11a7 \nmov %esi,%r11d\nmov %edx,%r9d\njmp 11a7 \nmov %r11d,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov r11d, [rdi]\ntest esi, esi\njle short loc_11DA\nmovsxd rsi, esi\nlea r8, [rdi+rsi*4]\nmov r9, rdi\nmov r10d, 0\njmp short loc_11AF\nloc_11A6:\nadd r9, 4\ncmp r9, r8\njz short loc_11DA\nloc_11AF:\nmov esi, [r9]\nmov rax, rdi\nmov edx, 0\nloc_11BA:\ncmp [rax], esi\nsetz cl\nmovzx ecx, cl\nadd edx, ecx\nadd rax, 4\ncmp rax, r8\njnz short loc_11BA\ncmp edx, r10d\njle short loc_11A6\nmov r11d, esi\nmov r10d, edx\njmp short loc_11A6\nloc_11DA:\nmov eax, r11d\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n unsigned int v2; // r11d\n unsigned int *v3; // r8\n unsigned int *v4; // r9\n int v5; // r10d\n unsigned int *v6; // rax\n int v7; // edx\n\n v2 = *a1;\n if ( a2 > 0 )\n {\n v3 = &a1[a2];\n v4 = a1;\n v5 = 0;\n do\n {\n v6 = a1;\n v7 = 0;\n do\n v7 += *v6++ == *v4;\n while ( v6 != v3 );\n if ( v7 > v5 )\n {\n v2 = *v4;\n v5 = v7;\n }\n ++v4;\n }\n while ( v4 != v3 );\n }\n return v2;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\nmov r11d, [rdi]\ntest esi, esi\njle short loc_11DA\nmovsxd rsi, esi\nlea r8, [rdi+rsi*4]\nmov r9, rdi\nmov r10d, 0\njmp short loc_11AF\nloc_11A6:\nadd r9, 4\ncmp r9, r8\njz short loc_11DA\nloc_11AF:\nmov esi, [r9]\nmov rax, rdi\nmov edx, 0\nloc_11BA:\ncmp [rax], esi\nsetz cl\nmovzx ecx, cl\nadd edx, ecx\nadd rax, 4\ncmp rax, r8\njnz short loc_11BA\ncmp edx, r10d\njle short loc_11A6\nmov r11d, esi\nmov r10d, edx\njmp short loc_11A6\nloc_11DA:\nmov eax, r11d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(unsigned int *a1, int a2)\n{\n unsigned int v2; // r11d\n unsigned int *v3; // r8\n unsigned int *v4; // r9\n int v5; // r10d\n unsigned int *v6; // rax\n int v7; // edx\n\n v2 = *a1;\n if ( a2 > 0 )\n {\n v3 = &a1[a2];\n v4 = a1;\n v5 = 0;\n do\n {\n v6 = a1;\n v7 = 0;\n do\n v7 += *v6++ == *v4;\n while ( v6 != v3 );\n if ( v7 > v5 )\n {\n v2 = *v4;\n v5 = v7;\n }\n ++v4;\n }\n while ( v4 != v3 );\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(unsigned int *a1, int a2) {\n unsigned int v2;\n unsigned int *v3;\n unsigned int *v4;\n int v5;\n unsigned int *v6;\n int v7;\n v2 = *a1;\n if (a2 > 0) {\n v3 = &a1[a2];\n v4 = a1;\n v5 = 0;\n do {\n v6 = a1;\n v7 = 0;\n do\n v7 += *v6++ == *v4;\n while (v6 != v3);\n if (v7 > v5) {\n v2 = *v4;\n v5 = v7;\n }\n ++v4;\n } while (v4 != v3);\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n unsigned int v2;\n unsigned int *v3;\n unsigned int *v4;\n int v5;\n unsigned int *v6;\n int v7;\n v2 = *a1;\n if (a2 > 0) {\n v3 = &a1[a2];\n v4 = a1;\n v5 = 0;\n do {\n v6 = a1;\n v7 = 0;\n do\n v7 += *v6++ == *v4;\n while (v6 != v3);\n if (v7 > v5) {\n v2 = *v4;\n v5 = v7;\n }\n ++v4;\n } while (v4 != v3);\n }\n return v2;\n}" + }, + { + "index": 658, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int list1[], int length) {\n int max_val = 0;\n int result = list1[0];\n for (int i = 0; i < length; i++) {\n int occu = 0;\n for (int j = 0; j < length; j++) {\n if (list1[j] == list1[i]) {\n occu++;\n }\n }\n if (occu > max_val) {\n max_val = occu;\n result = list1[i];\n }\n }\n return result;\n}", + "test": "int main() {\n\n int list1[] = {2, 3, 8, 4, 7, 9, 8, 2, 6, 5, 1, 6, 1, 2, 3, 4, 6, 9, 1, 2};\n\n int list2[] = {1, 3, 5, 7, 1, 3, 13, 15, 17, 5, 7, 9, 1, 11};\n\n int list3[] = {1, 2, 3, 2, 4, 5, 1, 1, 1};\n\n\n\n assert(func0(list1, sizeof(list1)/sizeof(list1[0])) == 2);\n\n assert(func0(list2, sizeof(list2)/sizeof(list2[0])) == 1);\n\n assert(func0(list3, sizeof(list3)/sizeof(list3[0])) == 1);\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov (%rdi),%r11d\ntest %esi,%esi\njle 1406 \nlea 0x4(%rdi),%r9\nlea -0x1(%rsi),%eax\nmov %r11d,%r12d\nmov %r11d,%esi\nlea (%r9,%rax,4),%rdi\nmov %r9,%r8\nxor %r10d,%r10d\nnopl 0x0(%rax)\nmov %r9,%rax\nmov %r11d,%ecx\nxor %edx,%edx\njmp 13de \nnopw 0x0(%rax,%rax,1)\nmov (%rax),%ecx\nadd $0x4,%rax\ncmp %ecx,%esi\nsete %cl\nmovzbl %cl,%ecx\nadd %ecx,%edx\ncmp %rdi,%rax\njne 13d8 \ncmp %r10d,%edx\njle 13f8 \nmov %esi,%r12d\nmov %edx,%r10d\ncmp %rdi,%r8\nje 1409 \nmov (%r8),%esi\nadd $0x4,%r8\njmp 13c8 \nmov %r11d,%r12d\nmov %r12d,%eax\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\nmov r11d, [rdi]\ntest esi, esi\njle short loc_1376\nmovsxd rsi, esi\nmov r9, rdi\nxor r10d, r10d\nlea r8, [rdi+rsi*4]\nnop dword ptr [rax+rax+00000000h]\nloc_1340:\nmov esi, [r9]\nmov rax, rdi\nxor edx, edx\nnop dword ptr [rax+rax+00000000h]\nloc_1350:\nxor ecx, ecx\ncmp esi, [rax]\nsetz cl\nadd rax, 4\nadd edx, ecx\ncmp r8, rax\njnz short loc_1350\ncmp edx, r10d\njle short loc_136D\nmov r11d, esi\nmov r10d, edx\nloc_136D:\nadd r9, 4\ncmp r8, r9\njnz short loc_1340\nloc_1376:\nmov eax, r11d\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n unsigned int v2; // r11d\n unsigned int *v3; // r9\n int v4; // r10d\n unsigned int *v5; // r8\n unsigned int *v6; // rax\n int v7; // edx\n int v8; // ecx\n\n v2 = *a1;\n if ( a2 > 0 )\n {\n v3 = a1;\n v4 = 0;\n v5 = &a1[a2];\n do\n {\n v6 = a1;\n v7 = 0;\n do\n {\n v8 = *v3 == *v6++;\n v7 += v8;\n }\n while ( v5 != v6 );\n if ( v7 > v4 )\n {\n v2 = *v3;\n v4 = v7;\n }\n ++v3;\n }\n while ( v5 != v3 );\n }\n return v2;\n}", + "ida_strip_asm": "sub_1320:\nendbr64\nmov r11d, [rdi]\ntest esi, esi\njle short loc_1376\nmovsxd rsi, esi\nmov r9, rdi\nxor r10d, r10d\nlea r8, [rdi+rsi*4]\nnop dword ptr [rax+rax+00000000h]\nloc_1340:\nmov esi, [r9]\nmov rax, rdi\nxor edx, edx\nnop dword ptr [rax+rax+00000000h]\nloc_1350:\nxor ecx, ecx\ncmp esi, [rax]\nsetz cl\nadd rax, 4\nadd edx, ecx\ncmp r8, rax\njnz short loc_1350\ncmp edx, r10d\njle short loc_136D\nmov r11d, esi\nmov r10d, edx\nloc_136D:\nadd r9, 4\ncmp r8, r9\njnz short loc_1340\nloc_1376:\nmov eax, r11d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1320(unsigned int *a1, int a2)\n{\n unsigned int v2; // r11d\n unsigned int *v3; // r9\n int v4; // r10d\n unsigned int *v5; // r8\n unsigned int *v6; // rax\n int v7; // edx\n int v8; // ecx\n\n v2 = *a1;\n if ( a2 > 0 )\n {\n v3 = a1;\n v4 = 0;\n v5 = &a1[a2];\n do\n {\n v6 = a1;\n v7 = 0;\n do\n {\n v8 = *v3 == *v6++;\n v7 += v8;\n }\n while ( v5 != v6 );\n if ( v7 > v4 )\n {\n v2 = *v3;\n v4 = v7;\n }\n ++v3;\n }\n while ( v5 != v3 );\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1320(unsigned int *a1, int a2) {\n unsigned int v2;\n unsigned int *v3;\n int v4;\n unsigned int *v5;\n unsigned int *v6;\n int v7;\n int v8;\n v2 = *a1;\n if (a2 > 0) {\n v3 = a1;\n v4 = 0;\n v5 = &a1[a2];\n do {\n v6 = a1;\n v7 = 0;\n do {\n v8 = *v3 == *v6++;\n v7 += v8;\n } while (v5 != v6);\n if (v7 > v4) {\n v2 = *v3;\n v4 = v7;\n }\n ++v3;\n } while (v5 != v3);\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n unsigned int v2;\n unsigned int *v3;\n int v4;\n unsigned int *v5;\n unsigned int *v6;\n int v7;\n int v8;\n v2 = *a1;\n if (a2 > 0) {\n v3 = a1;\n v4 = 0;\n v5 = &a1[a2];\n do {\n v6 = a1;\n v7 = 0;\n do {\n v8 = *v3 == *v6++;\n v7 += v8;\n } while (v5 != v6);\n if (v7 > v4) {\n v2 = *v3;\n v4 = v7;\n }\n ++v3;\n } while (v5 != v3);\n }\n return v2;\n}" + }, + { + "index": 658, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int list1[], int length) {\n int max_val = 0;\n int result = list1[0];\n for (int i = 0; i < length; i++) {\n int occu = 0;\n for (int j = 0; j < length; j++) {\n if (list1[j] == list1[i]) {\n occu++;\n }\n }\n if (occu > max_val) {\n max_val = occu;\n result = list1[i];\n }\n }\n return result;\n}", + "test": "int main() {\n\n int list1[] = {2, 3, 8, 4, 7, 9, 8, 2, 6, 5, 1, 6, 1, 2, 3, 4, 6, 9, 1, 2};\n\n int list2[] = {1, 3, 5, 7, 1, 3, 13, 15, 17, 5, 7, 9, 1, 11};\n\n int list3[] = {1, 2, 3, 2, 4, 5, 1, 1, 1};\n\n\n\n assert(func0(list1, sizeof(list1)/sizeof(list1[0])) == 2);\n\n assert(func0(list2, sizeof(list2)/sizeof(list2[0])) == 1);\n\n assert(func0(list3, sizeof(list3)/sizeof(list3[0])) == 1);\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\nmov (%rdi),%r13d\npush %r12\npush %rbp\npush %rbx\ntest %esi,%esi\njle 1426 \nmov %esi,%edx\nlea -0x1(%rsi),%eax\nmov %esi,%r11d\nmov %rdi,%r9\nshr $0x2,%edx\nmov %rax,%rbp\nlea 0x4(%rdi,%rax,4),%r12\nand $0xfffffffc,%r11d\nshl $0x4,%rdx\nxor %ebx,%ebx\nadd %rdi,%rdx\nnopw 0x0(%rax,%rax,1)\nmov (%r9),%ecx\ncmp $0x3,%ebp\njbe 1438 \nmovd %ecx,%xmm3\nmov %rdi,%rax\npxor %xmm1,%xmm1\npshufd $0x0,%xmm3,%xmm2\nnopl 0x0(%rax)\nmovdqu (%rax),%xmm0\nadd $0x10,%rax\npcmpeqd %xmm2,%xmm0\npsubd %xmm0,%xmm1\ncmp %rax,%rdx\njne 1380 \nmovdqa %xmm1,%xmm0\nmov %r11d,%r8d\npsrldq $0x8,%xmm0\npaddd %xmm0,%xmm1\nmovdqa %xmm1,%xmm0\npsrldq $0x4,%xmm0\npaddd %xmm0,%xmm1\nmovd %xmm1,%eax\ncmp %esi,%r11d\nje 1410 \nmovslq %r8d,%r14\ncmp %ecx,(%rdi,%r14,4)\nlea 0x0(,%r14,4),%r10\nsete %r14b\nmovzbl %r14b,%r14d\nadd %r14d,%eax\nlea 0x1(%r8),%r14d\ncmp %esi,%r14d\njge 1410 \ncmp 0x4(%rdi,%r10,1),%ecx\njne 13e8 \nadd $0x1,%eax\nlea 0x2(%r8),%r14d\ncmp %esi,%r14d\njge 1410 \ncmp 0x8(%rdi,%r10,1),%ecx\njne 13fb \nadd $0x1,%eax\nadd $0x3,%r8d\ncmp %r8d,%esi\njle 1410 \ncmp 0xc(%rdi,%r10,1),%ecx\njne 1410 \nadd $0x1,%eax\nxchg %ax,%ax\ncmp %eax,%ebx\njge 1419 \nmov %ecx,%r13d\nmov %eax,%ebx\nadd $0x4,%r9\ncmp %r12,%r9\njne 1360 \npop %rbx\nmov %r13d,%eax\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopw 0x0(%rax,%rax,1)\nxor %r8d,%r8d\nxor %eax,%eax\njmpq 13bb \nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\nmov r13d, [rdi]\npush r12\npush rbp\npush rbx\ntest esi, esi\njle loc_140A\nmov edx, esi\nmovsxd rax, esi\nmov r11d, esi\nmov r8, rdi\nshr edx, 2\nmov r9d, esi\nlea r12, [rdi+rax*4]\nand r11d, 0FFFFFFFCh\nshl rdx, 4\nlea ebp, [rsi-1]\nxor ebx, ebx\nadd rdx, rdi\nnop dword ptr [rax+00h]\nloc_1360:\nmov esi, [rdi]\ncmp ebp, 2\njbe loc_1420\nmovd xmm3, esi\nmov rax, r8\npxor xmm1, xmm1\npshufd xmm2, xmm3, 0\nnop dword ptr [rax+rax+00h]\nloc_1380:\nmovdqu xmm0, xmmword ptr [rax]\nadd rax, 10h\npcmpeqd xmm0, xmm2\npsubd xmm1, xmm0\ncmp rdx, rax\njnz short loc_1380\nmovdqa xmm0, xmm1\nmov ecx, r11d\npsrldq xmm0, 8\npaddd xmm1, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm0, 4\npaddd xmm1, xmm0\nmovd eax, xmm1\ncmp r9d, r11d\njz short loc_13F4\nloc_13BB:\nmovsxd r10, ecx\nlea r14, ds:0[r10*4]\ncmp [r8+r10*4], esi\njnz short loc_13CF\nadd eax, 1\nloc_13CF:\nlea r10d, [rcx+1]\ncmp r9d, r10d\njle short loc_13F4\ncmp esi, [r8+r14+4]\njnz short loc_13E2\nadd eax, 1\nloc_13E2:\nadd ecx, 2\ncmp ecx, r9d\njge short loc_13F4\ncmp esi, [r8+r14+8]\njnz short loc_13F4\nadd eax, 1\nloc_13F4:\ncmp ebx, eax\njge short loc_13FD\nmov r13d, esi\nmov ebx, eax\nloc_13FD:\nadd rdi, 4\ncmp r12, rdi\njnz loc_1360\nloc_140A:\npop rbx\nmov eax, r13d\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1420:\nxor ecx, ecx\nxor eax, eax\njmp short loc_13BB", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n unsigned int v2; // r13d\n const __m128i *v3; // r8\n unsigned int *v5; // r12\n unsigned int v6; // r11d\n unsigned int v7; // ebp\n int v8; // ebx\n const __m128i *v9; // rdx\n unsigned int v10; // esi\n const __m128i *v11; // rax\n __m128i v12; // xmm1\n __m128i v13; // xmm2\n __m128i v14; // xmm0\n signed int v15; // ecx\n __m128i v16; // xmm1\n int v17; // eax\n __int64 v18; // r14\n\n v2 = *a1;\n if ( a2 > 0 )\n {\n v3 = (const __m128i *)a1;\n v5 = &a1[a2];\n v6 = a2 & 0xFFFFFFFC;\n v7 = a2 - 1;\n v8 = 0;\n v9 = (const __m128i *)&a1[4 * ((unsigned int)a2 >> 2)];\n while ( 1 )\n {\n v10 = *a1;\n if ( v7 <= 2 )\n break;\n v11 = v3;\n v12 = 0LL;\n v13 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v10), 0);\n do\n {\n v14 = _mm_loadu_si128(v11++);\n v12 = _mm_sub_epi32(v12, _mm_cmpeq_epi32(v14, v13));\n }\n while ( v9 != v11 );\n v15 = v6;\n v16 = _mm_add_epi32(v12, _mm_srli_si128(v12, 8));\n v17 = _mm_cvtsi128_si32(_mm_add_epi32(v16, _mm_srli_si128(v16, 4)));\n if ( a2 != v6 )\n goto LABEL_7;\nLABEL_15:\n if ( v8 < v17 )\n {\n v2 = *a1;\n v8 = v17;\n }\n if ( v5 == ++a1 )\n return v2;\n }\n v15 = 0;\n v17 = 0;\nLABEL_7:\n v18 = v15;\n if ( v3->m128i_i32[v18] == v10 )\n ++v17;\n if ( a2 > v15 + 1 )\n {\n if ( v10 == v3->m128i_i32[v18 + 1] )\n ++v17;\n if ( v15 + 2 < a2 && v10 == v3->m128i_i32[v18 + 2] )\n ++v17;\n }\n goto LABEL_15;\n }\n return v2;\n}", + "ida_strip_asm": "sub_1320:\nendbr64\npush r14\npush r13\nmov r13d, [rdi]\npush r12\npush rbp\npush rbx\ntest esi, esi\njle loc_140A\nmov edx, esi\nmovsxd rax, esi\nmov r11d, esi\nmov r8, rdi\nshr edx, 2\nmov r9d, esi\nlea r12, [rdi+rax*4]\nand r11d, 0FFFFFFFCh\nshl rdx, 4\nlea ebp, [rsi-1]\nxor ebx, ebx\nadd rdx, rdi\nnop dword ptr [rax+00h]\nloc_1360:\nmov esi, [rdi]\ncmp ebp, 2\njbe loc_1420\nmovd xmm3, esi\nmov rax, r8\npxor xmm1, xmm1\npshufd xmm2, xmm3, 0\nnop dword ptr [rax+rax+00h]\nloc_1380:\nmovdqu xmm0, xmmword ptr [rax]\nadd rax, 10h\npcmpeqd xmm0, xmm2\npsubd xmm1, xmm0\ncmp rdx, rax\njnz short loc_1380\nmovdqa xmm0, xmm1\nmov ecx, r11d\npsrldq xmm0, 8\npaddd xmm1, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm0, 4\npaddd xmm1, xmm0\nmovd eax, xmm1\ncmp r9d, r11d\njz short loc_13F4\nloc_13BB:\nmovsxd r10, ecx\nlea r14, ds:0[r10*4]\ncmp [r8+r10*4], esi\njnz short loc_13CF\nadd eax, 1\nloc_13CF:\nlea r10d, [rcx+1]\ncmp r9d, r10d\njle short loc_13F4\ncmp esi, [r8+r14+4]\njnz short loc_13E2\nadd eax, 1\nloc_13E2:\nadd ecx, 2\ncmp ecx, r9d\njge short loc_13F4\ncmp esi, [r8+r14+8]\njnz short loc_13F4\nadd eax, 1\nloc_13F4:\ncmp ebx, eax\njge short loc_13FD\nmov r13d, esi\nmov ebx, eax\nloc_13FD:\nadd rdi, 4\ncmp r12, rdi\njnz loc_1360\nloc_140A:\npop rbx\nmov eax, r13d\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1420:\nxor ecx, ecx\nxor eax, eax\njmp short loc_13BB", + "ida_strip_pseudo": "__int64 __fastcall sub_1320(unsigned int *a1, int a2)\n{\n unsigned int v2; // r13d\n const __m128i *v3; // r8\n unsigned int *v5; // r12\n unsigned int v6; // r11d\n unsigned int v7; // ebp\n int v8; // ebx\n const __m128i *v9; // rdx\n unsigned int v10; // esi\n const __m128i *v11; // rax\n __m128i v12; // xmm1\n __m128i v13; // xmm2\n __m128i v14; // xmm0\n signed int v15; // ecx\n __m128i v16; // xmm1\n int v17; // eax\n __int64 v18; // r14\n\n v2 = *a1;\n if ( a2 > 0 )\n {\n v3 = (const __m128i *)a1;\n v5 = &a1[a2];\n v6 = a2 & 0xFFFFFFFC;\n v7 = a2 - 1;\n v8 = 0;\n v9 = (const __m128i *)&a1[4 * ((unsigned int)a2 >> 2)];\n while ( 1 )\n {\n v10 = *a1;\n if ( v7 <= 2 )\n break;\n v11 = v3;\n v12 = 0LL;\n v13 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v10), 0);\n do\n {\n v14 = _mm_loadu_si128(v11++);\n v12 = _mm_sub_epi32(v12, _mm_cmpeq_epi32(v14, v13));\n }\n while ( v9 != v11 );\n v15 = v6;\n v16 = _mm_add_epi32(v12, _mm_srli_si128(v12, 8));\n v17 = _mm_cvtsi128_si32(_mm_add_epi32(v16, _mm_srli_si128(v16, 4)));\n if ( a2 != v6 )\n goto LABEL_7;\nLABEL_15:\n if ( v8 < v17 )\n {\n v2 = *a1;\n v8 = v17;\n }\n if ( v5 == ++a1 )\n return v2;\n }\n v15 = 0;\n v17 = 0;\nLABEL_7:\n v18 = v15;\n if ( v3->m128i_i32[v18] == v10 )\n ++v17;\n if ( a2 > v15 + 1 )\n {\n if ( v10 == v3->m128i_i32[v18 + 1] )\n ++v17;\n if ( v15 + 2 < a2 && v10 == v3->m128i_i32[v18 + 2] )\n ++v17;\n }\n goto LABEL_15;\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1320(unsigned int *a1, int a2) {\n unsigned int v2;\n const __m128i *v3;\n unsigned int *v5;\n unsigned int v6;\n unsigned int v7;\n int v8;\n const __m128i *v9;\n unsigned int v10;\n const __m128i *v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n signed int v15;\n __m128i v16;\n int v17;\n long long v18;\n v2 = *a1;\n if (a2 > 0) {\n v3 = (const __m128i *)a1;\n v5 = &a1[a2];\n v6 = a2 & 4294967292;\n v7 = a2 - 1;\n v8 = 0;\n v9 = (const __m128i *)&a1[4 * ((unsigned int)a2 >> 2)];\n while (1) {\n v10 = *a1;\n if (v7 <= 2) break;\n v11 = v3;\n v12 = 0LL;\n v13 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v10), 0);\n do {\n v14 = _mm_loadu_si128(v11++);\n v12 = _mm_sub_epi32(v12, _mm_cmpeq_epi32(v14, v13));\n } while (v9 != v11);\n v15 = v6;\n v16 = _mm_add_epi32(v12, _mm_srli_si128(v12, 8));\n v17 = _mm_cvtsi128_si32(_mm_add_epi32(v16, _mm_srli_si128(v16, 4)));\n if (a2 != v6) goto LABEL_7;\n LABEL_15:\n if (v8 < v17) {\n v2 = *a1;\n v8 = v17;\n }\n if (v5 == ++a1) return v2;\n }\n v15 = 0;\n v17 = 0;\n LABEL_7:\n v18 = v15;\n if (v3->m128i_i32[v18] == v10) ++v17;\n if (a2 > v15 + 1) {\n if (v10 == v3->m128i_i32[v18 + 1]) ++v17;\n if (v15 + 2 < a2 && v10 == v3->m128i_i32[v18 + 2]) ++v17;\n }\n goto LABEL_15;\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n unsigned int v2;\n const __m128i *v3;\n unsigned int *v5;\n unsigned int v6;\n unsigned int v7;\n int v8;\n const __m128i *v9;\n unsigned int v10;\n const __m128i *v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n signed int v15;\n __m128i v16;\n int v17;\n long long v18;\n v2 = *a1;\n if (a2 > 0) {\n v3 = (const __m128i *)a1;\n v5 = &a1[a2];\n v6 = a2 & 4294967292;\n v7 = a2 - 1;\n v8 = 0;\n v9 = (const __m128i *)&a1[4 * ((unsigned int)a2 >> 2)];\n while (1) {\n v10 = *a1;\n if (v7 <= 2) break;\n v11 = v3;\n v12 = 0LL;\n v13 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v10), 0);\n do {\n v14 = _mm_loadu_si128(v11++);\n v12 = _mm_sub_epi32(v12, _mm_cmpeq_epi32(v14, v13));\n } while (v9 != v11);\n v15 = v6;\n v16 = _mm_add_epi32(v12, _mm_srli_si128(v12, 8));\n v17 = _mm_cvtsi128_si32(_mm_add_epi32(v16, _mm_srli_si128(v16, 4)));\n if (a2 != v6) goto LABEL_7;\n LABEL_15:\n if (v8 < v17) {\n v2 = *a1;\n v8 = v17;\n }\n if (v5 == ++a1) return v2;\n }\n v15 = 0;\n v17 = 0;\n LABEL_7:\n v18 = v15;\n if (v3->m128i_i32[v18] == v10) ++v17;\n if (a2 > v15 + 1) {\n if (v10 == v3->m128i_i32[v18 + 1]) ++v17;\n if (v15 + 2 < a2 && v10 == v3->m128i_i32[v18 + 2]) ++v17;\n }\n goto LABEL_15;\n }\n return v2;\n}" + }, + { + "index": 659, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\nvoid assertArrayEquals(int *expected, int expectedSize, int *actual, int actualSize) {\n\n assert(expectedSize == actualSize);\n\n for (int i = 0; i < expectedSize; i++) {\n\n assert(expected[i] == actual[i]);\n\n }\n\n}\n\n\n\n", + "func": "int *func0(int x[], int size, int *returnSize) {\n int *repeated = malloc(sizeof(int) * size);\n int count = 0;\n bool found;\n for (int i = 0; i < size; i++) {\n found = false;\n for (int j = i + 1; j < size; j++) {\n if (x[i] == x[j]) {\n found = true;\n for (int k = 0; k < count; k++) {\n if (repeated[k] == x[i]) {\n found = false;\n break;\n }\n }\n if (found) {\n repeated[count++] = x[i];\n break;\n }\n }\n }\n }\n *returnSize = count;\n return repeated;\n}", + "test": "int main() {\n\n int arr1[] = {10, 20, 30, 20, 20, 30, 40, 50, -20, 60, 60, -20, -20};\n\n int expected1[] = {20, 30, -20, 60};\n\n int size1;\n\n int *result1 = func0(arr1, 13, &size1);\n\n assertArrayEquals(expected1, 4, result1, size1);\n\n free(result1);\n\n \n\n int arr2[] = {-1, 1, -1, 8};\n\n int expected2[] = {-1};\n\n int size2;\n\n int *result2 = func0(arr2, 4, &size2);\n\n assertArrayEquals(expected2, 1, result2, size2);\n\n free(result2);\n\n \n\n int arr3[] = {1, 2, 3, 1, 2};\n\n int expected3[] = {1, 2};\n\n int size3;\n\n int *result3 = func0(arr3, 5, &size3);\n\n assertArrayEquals(expected3, 2, result3, size3);\n\n free(result3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x40,%rsp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmov %rdx,-0x38(%rbp)\nmov -0x2c(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0x18(%rbp)\nmovl $0x0,-0x14(%rbp)\njmpq 1375 \nmovb $0x0,-0x19(%rbp)\nmov -0x14(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x10(%rbp)\njmpq 1365 \nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 1361 \nmovb $0x1,-0x19(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 131e \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 131a \nmovb $0x0,-0x19(%rbp)\njmp 1326 \naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x18(%rbp),%eax\njl 12e4 \ncmpb $0x0,-0x19(%rbp)\nje 1361 \nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x18(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x18(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\njmp 1371 \naddl $0x1,-0x10(%rbp)\nmov -0x10(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 12a3 \naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 1291 \nmov -0x38(%rbp),%rax\nmov -0x18(%rbp),%edx\nmov %edx,(%rax)\nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp loc_1387\nloc_12A3:\nmov [rbp+var_19], 0\nmov eax, [rbp+var_14]\nadd eax, 1\nmov [rbp+var_10], eax\njmp loc_1377\nloc_12B5:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz loc_1373\nmov [rbp+var_19], 1\nmov [rbp+var_C], 0\njmp short loc_1330\nloc_12F6:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_14]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_132C\nmov [rbp+var_19], 0\njmp short loc_1338\nloc_132C:\nadd [rbp+var_C], 1\nloc_1330:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_18]\njl short loc_12F6\nloc_1338:\ncmp [rbp+var_19], 0\njz short loc_1373\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\njmp short loc_1383\nloc_1373:\nadd [rbp+var_10], 1\nloc_1377:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_2C]\njl loc_12B5\nloc_1383:\nadd [rbp+var_14], 1\nloc_1387:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl loc_12A3\nmov rax, [rbp+var_38]\nmov edx, [rbp+var_18]\nmov [rax], edx\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, _DWORD *a3)\n{\n int v3; // eax\n char v6; // [rsp+27h] [rbp-19h]\n int v7; // [rsp+28h] [rbp-18h]\n int i; // [rsp+2Ch] [rbp-14h]\n int j; // [rsp+30h] [rbp-10h]\n int k; // [rsp+34h] [rbp-Ch]\n _DWORD *v11; // [rsp+38h] [rbp-8h]\n\n v11 = malloc(4LL * a2);\n v7 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4LL * j + a1) )\n {\n v6 = 1;\n for ( k = 0; k < v7; ++k )\n {\n if ( v11[k] == *(_DWORD *)(4LL * i + a1) )\n {\n v6 = 0;\n break;\n }\n }\n if ( v6 )\n {\n v3 = v7++;\n v11[v3] = *(_DWORD *)(4LL * i + a1);\n break;\n }\n }\n }\n }\n *a3 = v7;\n return v11;\n}", + "ida_strip_asm": "sub_1264:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp loc_1387\nloc_12A3:\nmov [rbp+var_19], 0\nmov eax, [rbp+var_14]\nadd eax, 1\nmov [rbp+var_10], eax\njmp loc_1377\nloc_12B5:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz loc_1373\nmov [rbp+var_19], 1\nmov [rbp+var_C], 0\njmp short loc_1330\nloc_12F6:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_14]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_132C\nmov [rbp+var_19], 0\njmp short loc_1338\nloc_132C:\nadd [rbp+var_C], 1\nloc_1330:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_18]\njl short loc_12F6\nloc_1338:\ncmp [rbp+var_19], 0\njz short loc_1373\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\njmp short loc_1383\nloc_1373:\nadd [rbp+var_10], 1\nloc_1377:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_2C]\njl loc_12B5\nloc_1383:\nadd [rbp+var_14], 1\nloc_1387:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl loc_12A3\nmov rax, [rbp+var_38]\nmov edx, [rbp+var_18]\nmov [rax], edx\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1264(__int64 a1, int a2, _DWORD *a3)\n{\n int v3; // eax\n char v6; // [rsp+27h] [rbp-19h]\n int v7; // [rsp+28h] [rbp-18h]\n int i; // [rsp+2Ch] [rbp-14h]\n int j; // [rsp+30h] [rbp-10h]\n int k; // [rsp+34h] [rbp-Ch]\n _DWORD *v11; // [rsp+38h] [rbp-8h]\n\n v11 = malloc(4LL * a2);\n v7 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4LL * j + a1) )\n {\n v6 = 1;\n for ( k = 0; k < v7; ++k )\n {\n if ( v11[k] == *(_DWORD *)(4LL * i + a1) )\n {\n v6 = 0;\n break;\n }\n }\n if ( v6 )\n {\n v3 = v7++;\n v11[v3] = *(_DWORD *)(4LL * i + a1);\n break;\n }\n }\n }\n }\n *a3 = v7;\n return v11;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1264(long long a1, int a2, uint32_t *a3) {\n int v3;\n char v6;\n int v7;\n int i;\n int j;\n int k;\n uint32_t *v11;\n v11 = malloc(4LL * a2);\n v7 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if (*(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4LL * j + a1)) {\n v6 = 1;\n for (k = 0; k < v7; ++k) {\n if (v11[k] == *(uint32_t *)(4LL * i + a1)) {\n v6 = 0;\n break;\n }\n }\n if (v6) {\n v3 = v7++;\n v11[v3] = *(uint32_t *)(4LL * i + a1);\n break;\n }\n }\n }\n }\n *a3 = v7;\n return v11;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, uint32_t *a3) {\n int v3;\n char v6;\n int v7;\n int i;\n int j;\n int k;\n uint32_t *v11;\n v11 = malloc(4LL * a2);\n v7 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if (*(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4LL * j + a1)) {\n v6 = 1;\n for (k = 0; k < v7; ++k) {\n if (v11[k] == *(uint32_t *)(4LL * i + a1)) {\n v6 = 0;\n break;\n }\n }\n if (v6) {\n v3 = v7++;\n v11[v3] = *(uint32_t *)(4LL * i + a1);\n break;\n }\n }\n }\n }\n *a3 = v7;\n return v11;\n}" + }, + { + "index": 659, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\nvoid assertArrayEquals(int *expected, int expectedSize, int *actual, int actualSize) {\n\n assert(expectedSize == actualSize);\n\n for (int i = 0; i < expectedSize; i++) {\n\n assert(expected[i] == actual[i]);\n\n }\n\n}\n\n\n\n", + "func": "int *func0(int x[], int size, int *returnSize) {\n int *repeated = malloc(sizeof(int) * size);\n int count = 0;\n bool found;\n for (int i = 0; i < size; i++) {\n found = false;\n for (int j = i + 1; j < size; j++) {\n if (x[i] == x[j]) {\n found = true;\n for (int k = 0; k < count; k++) {\n if (repeated[k] == x[i]) {\n found = false;\n break;\n }\n }\n if (found) {\n repeated[count++] = x[i];\n break;\n }\n }\n }\n }\n *returnSize = count;\n return repeated;\n}", + "test": "int main() {\n\n int arr1[] = {10, 20, 30, 20, 20, 30, 40, 50, -20, 60, 60, -20, -20};\n\n int expected1[] = {20, 30, -20, 60};\n\n int size1;\n\n int *result1 = func0(arr1, 13, &size1);\n\n assertArrayEquals(expected1, 4, result1, size1);\n\n free(result1);\n\n \n\n int arr2[] = {-1, 1, -1, 8};\n\n int expected2[] = {-1};\n\n int size2;\n\n int *result2 = func0(arr2, 4, &size2);\n\n assertArrayEquals(expected2, 1, result2, size2);\n\n free(result2);\n\n \n\n int arr3[] = {1, 2, 3, 1, 2};\n\n int expected3[] = {1, 2};\n\n int size3;\n\n int *result3 = func0(arr3, 5, &size3);\n\n assertArrayEquals(expected3, 2, result3, size3);\n\n free(result3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbx\nmov %esi,%ebp\nmov %rdx,%r12\nmovslq %esi,%rdi\nshl $0x2,%rdi\ncallq 10b0 \nmov %rax,%r13\ntest %ebp,%ebp\njle 12a8 \nlea -0x1(%rbp),%r10d\nadd $0x1,%r10\nmov $0x1,%edi\nmov $0x0,%r8d\nmov %rax,%r9\nlea 0x4(%rax),%r11\njmp 1292 \nadd $0x1,%rdx\ncmp %edx,%ebp\njle 128e \ncmp (%rbx,%rdx,4),%ecx\njne 1260 \ntest %r8d,%r8d\njle 1282 \nmov %r9,%rax\ncmp (%rax),%ecx\nje 1260 \nadd $0x4,%rax\ncmp %rsi,%rax\njne 1275 \nmovslq %r8d,%rax\nmov %ecx,0x0(%r13,%rax,4)\nlea 0x1(%r8),%r8d\nadd $0x1,%rdi\ncmp %r10,%rdi\nje 12ae \nmov -0x4(%rbx,%rdi,4),%ecx\nlea -0x1(%r8),%eax\nlea (%r11,%rax,4),%rsi\nmov %rdi,%rdx\njmp 1268 \nmov $0x0,%r8d\nmov %r8d,(%r12)\nmov %r13,%rax\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov ebp, esi\nmov r13, rdx\nmovsxd r12, esi\nlea rdi, ds:0[r12*4]; size\ncall _malloc\ntest ebp, ebp\njle short loc_12A0\nmov r11d, ebp\nmov r8d, 1\nmov r9d, 0\njmp short loc_128A\nloc_1254:\nadd rcx, 1\ncmp ebp, ecx\njle short loc_127E\nloc_125C:\ncmp esi, [rbx+rcx*4]\njnz short loc_1254\ntest r9d, r9d\njle short loc_1276\nmov rdx, rax\nloc_1269:\ncmp esi, [rdx]\njz short loc_1254\nadd rdx, 4\ncmp rdx, rdi\njnz short loc_1269\nloc_1276:\nadd r9d, 1\nmov [rax+r10*4], esi\nloc_127E:\nlea rdx, [r8+1]\ncmp r12, r8\njz short loc_12A6\nmov r8, rdx\nloc_128A:\ncmp r8, r11\njz short loc_12A6\nmov esi, [rbx+r8*4-4]\nmovsxd r10, r9d\nlea rdi, [rax+r10*4]\nmov rcx, r8\njmp short loc_125C\nloc_12A0:\nmov r9d, 0\nloc_12A6:\nmov [r13+0], r9d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, int *a3)\n{\n __int64 v5; // r12\n _DWORD *result; // rax\n __int64 v7; // r8\n int v8; // r9d\n __int64 v9; // rcx\n _DWORD *v10; // rdx\n int v11; // esi\n __int64 v12; // r10\n\n v5 = a2;\n result = malloc(4LL * a2);\n if ( a2 > 0 )\n {\n v7 = 1LL;\n v8 = 0;\n while ( 1 )\n {\n if ( v7 == a2 )\n goto LABEL_15;\n v11 = *(_DWORD *)(a1 + 4 * v7 - 4);\n v12 = v8;\n v9 = v7;\n while ( v11 != *(_DWORD *)(a1 + 4 * v9) )\n {\nLABEL_3:\n if ( a2 <= (int)++v9 )\n goto LABEL_10;\n }\n if ( v8 > 0 )\n break;\nLABEL_9:\n ++v8;\n result[v12] = v11;\nLABEL_10:\n if ( v5 == v7 )\n goto LABEL_15;\n ++v7;\n }\n v10 = result;\n while ( v11 != *v10 )\n {\n if ( ++v10 == &result[v8] )\n goto LABEL_9;\n }\n goto LABEL_3;\n }\n v8 = 0;\nLABEL_15:\n *a3 = v8;\n return result;\n}", + "ida_strip_asm": "sub_1219:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov ebp, esi\nmov r13, rdx\nmovsxd r12, esi\nlea rdi, ds:0[r12*4]; size\ncall _malloc\ntest ebp, ebp\njle short loc_12A0\nmov r11d, ebp\nmov r8d, 1\nmov r9d, 0\njmp short loc_128A\nloc_1254:\nadd rcx, 1\ncmp ebp, ecx\njle short loc_127E\nloc_125C:\ncmp esi, [rbx+rcx*4]\njnz short loc_1254\ntest r9d, r9d\njle short loc_1276\nmov rdx, rax\nloc_1269:\ncmp esi, [rdx]\njz short loc_1254\nadd rdx, 4\ncmp rdx, rdi\njnz short loc_1269\nloc_1276:\nadd r9d, 1\nmov [rax+r10*4], esi\nloc_127E:\nlea rdx, [r8+1]\ncmp r12, r8\njz short loc_12A6\nmov r8, rdx\nloc_128A:\ncmp r8, r11\njz short loc_12A6\nmov esi, [rbx+r8*4-4]\nmovsxd r10, r9d\nlea rdi, [rax+r10*4]\nmov rcx, r8\njmp short loc_125C\nloc_12A0:\nmov r9d, 0\nloc_12A6:\nmov [r13+0], r9d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1219(__int64 a1, int a2, int *a3)\n{\n __int64 v5; // r12\n _DWORD *result; // rax\n __int64 v7; // r8\n int v8; // r9d\n __int64 v9; // rcx\n _DWORD *v10; // rdx\n int v11; // esi\n __int64 v12; // r10\n\n v5 = a2;\n result = malloc(4LL * a2);\n if ( a2 > 0 )\n {\n v7 = 1LL;\n v8 = 0;\n while ( 1 )\n {\n if ( v7 == a2 )\n goto LABEL_15;\n v11 = *(_DWORD *)(a1 + 4 * v7 - 4);\n v12 = v8;\n v9 = v7;\n while ( v11 != *(_DWORD *)(a1 + 4 * v9) )\n {\nLABEL_3:\n if ( a2 <= (int)++v9 )\n goto LABEL_10;\n }\n if ( v8 > 0 )\n break;\nLABEL_9:\n ++v8;\n result[v12] = v11;\nLABEL_10:\n if ( v5 == v7 )\n goto LABEL_15;\n ++v7;\n }\n v10 = result;\n while ( v11 != *v10 )\n {\n if ( ++v10 == &result[v8] )\n goto LABEL_9;\n }\n goto LABEL_3;\n }\n v8 = 0;\nLABEL_15:\n *a3 = v8;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1219(long long a1, int a2, int *a3) {\n long long v5;\n uint32_t *result;\n long long v7;\n int v8;\n long long v9;\n uint32_t *v10;\n int v11;\n long long v12;\n v5 = a2;\n result = malloc(4LL * a2);\n if (a2 > 0) {\n v7 = 1LL;\n v8 = 0;\n while (1) {\n if (v7 == a2) goto LABEL_15;\n v11 = *(uint32_t *)(a1 + 4 * v7 - 4);\n v12 = v8;\n v9 = v7;\n while (v11 != *(uint32_t *)(a1 + 4 * v9)) {\n LABEL_3:\n if (a2 <= (int)++v9) goto LABEL_10;\n }\n if (v8 > 0) break;\n LABEL_9:\n ++v8;\n result[v12] = v11;\n LABEL_10:\n if (v5 == v7) goto LABEL_15;\n ++v7;\n }\n v10 = result;\n while (v11 != *v10) {\n if (++v10 == &result[v8]) goto LABEL_9;\n }\n goto LABEL_3;\n }\n v8 = 0;\nLABEL_15:\n *a3 = v8;\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, int *a3) {\n long long v5;\n uint32_t *result;\n long long v7;\n int v8;\n long long v9;\n uint32_t *v10;\n int v11;\n long long v12;\n v5 = a2;\n result = malloc(4LL * a2);\n if (a2 > 0) {\n v7 = 1LL;\n v8 = 0;\n while (1) {\n if (v7 == a2) goto LABEL_15;\n v11 = *(uint32_t *)(a1 + 4 * v7 - 4);\n v12 = v8;\n v9 = v7;\n while (v11 != *(uint32_t *)(a1 + 4 * v9)) {\n LABEL_3:\n if (a2 <= (int)++v9) goto LABEL_10;\n }\n if (v8 > 0) break;\n LABEL_9:\n ++v8;\n result[v12] = v11;\n LABEL_10:\n if (v5 == v7) goto LABEL_15;\n ++v7;\n }\n v10 = result;\n while (v11 != *v10) {\n if (++v10 == &result[v8]) goto LABEL_9;\n }\n goto LABEL_3;\n }\n v8 = 0;\nLABEL_15:\n *a3 = v8;\n return result;\n}" + }, + { + "index": 659, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\nvoid assertArrayEquals(int *expected, int expectedSize, int *actual, int actualSize) {\n\n assert(expectedSize == actualSize);\n\n for (int i = 0; i < expectedSize; i++) {\n\n assert(expected[i] == actual[i]);\n\n }\n\n}\n\n\n\n", + "func": "int *func0(int x[], int size, int *returnSize) {\n int *repeated = malloc(sizeof(int) * size);\n int count = 0;\n bool found;\n for (int i = 0; i < size; i++) {\n found = false;\n for (int j = i + 1; j < size; j++) {\n if (x[i] == x[j]) {\n found = true;\n for (int k = 0; k < count; k++) {\n if (repeated[k] == x[i]) {\n found = false;\n break;\n }\n }\n if (found) {\n repeated[count++] = x[i];\n break;\n }\n }\n }\n }\n *returnSize = count;\n return repeated;\n}", + "test": "int main() {\n\n int arr1[] = {10, 20, 30, 20, 20, 30, 40, 50, -20, 60, 60, -20, -20};\n\n int expected1[] = {20, 30, -20, 60};\n\n int size1;\n\n int *result1 = func0(arr1, 13, &size1);\n\n assertArrayEquals(expected1, 4, result1, size1);\n\n free(result1);\n\n \n\n int arr2[] = {-1, 1, -1, 8};\n\n int expected2[] = {-1};\n\n int size2;\n\n int *result2 = func0(arr2, 4, &size2);\n\n assertArrayEquals(expected2, 1, result2, size2);\n\n free(result2);\n\n \n\n int arr3[] = {1, 2, 3, 1, 2};\n\n int expected3[] = {1, 2};\n\n int size3;\n\n int *result3 = func0(arr3, 5, &size3);\n\n assertArrayEquals(expected3, 2, result3, size3);\n\n free(result3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %rdx,%r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nmovslq %esi,%rdi\nmov %rdi,%rbp\nshl $0x2,%rdi\ncallq 10b0 \nmov %rax,%r9\ntest %ebp,%ebp\njle 1485 \nlea -0x1(%rbp),%r10d\nmov $0x1,%edi\nlea 0x4(%rax),%r11\nxor %r8d,%r8d\nadd $0x1,%r10\ncmp %r10,%rdi\nje 1479 \nnopl 0x0(%rax)\nlea -0x1(%r8),%eax\nmov -0x4(%rbx,%rdi,4),%ecx\nmov %rdi,%rdx\nlea (%r11,%rax,4),%rsi\njmp 1448 \nnopl 0x0(%rax)\nadd $0x1,%rdx\ncmp %edx,%ebp\njle 1470 \ncmp (%rbx,%rdx,4),%ecx\njne 1440 \ntest %r8d,%r8d\nje 1465 \nmov %r9,%rax\nnopl (%rax)\ncmp (%rax),%ecx\nje 1440 \nadd $0x4,%rax\ncmp %rsi,%rax\njne 1458 \nmovslq %r8d,%rax\nadd $0x1,%r8d\nmov %ecx,(%r9,%rax,4)\nadd $0x1,%rdi\ncmp %r10,%rdi\njne 1428 \npop %rbx\nmov %r9,%rax\npop %rbp\nmov %r8d,(%r12)\npop %r12\nretq\nxor %r8d,%r8d\npop %rbx\nmov %r9,%rax\npop %rbp\nmov %r8d,(%r12)\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r12\nmov r12, rdx\npush rbp\npush rbx\nmov rbx, rdi\nmovsxd rdi, esi\nmov rbp, rdi\nshl rdi, 2; size\ncall _malloc\ntest ebp, ebp\njle loc_1457\nmov r11d, ebp\nmov r8d, 1\nxor r9d, r9d\ncmp ebp, 1\njz short loc_1431\nnop word ptr [rax+rax+00000000h]\nloc_13D0:\nmovsxd r10, r9d\nmov esi, [rbx+r8*4-4]\nmov rcx, r8\nlea rdi, [rax+r10*4]\njmp short loc_13F0\nloc_13E8:\nadd rcx, 1\ncmp ebp, ecx\njle short loc_1428\nloc_13F0:\ncmp esi, [rbx+rcx*4]\njnz short loc_13E8\ntest r9d, r9d\njle short loc_1440\nloc_13FA:\nmov rdx, rax\njmp short loc_1409\nloc_1400:\nadd rdx, 4\ncmp rdi, rdx\njz short loc_1440\nloc_1409:\ncmp esi, [rdx]\njnz short loc_1400\nadd rcx, 1\ncmp ebp, ecx\njle short loc_1428\ncmp esi, [rbx+rcx*4]\njz short loc_13FA\nadd rcx, 1\ncmp ebp, ecx\njg short loc_13F0\nnop word ptr [rax+rax+00h]\nloc_1428:\nadd r8, 1\ncmp r8, r11\njnz short loc_13D0\nloc_1431:\nmov [r12], r9d\npop rbx\npop rbp\npop r12\nretn\nloc_1440:\nadd r8, 1\nmov [rax+r10*4], esi\nadd r9d, 1\ncmp r8, r11\njnz loc_13D0\njmp short loc_1431\nloc_1457:\nxor r9d, r9d\nmov [r12], r9d\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, int *a3)\n{\n _DWORD *result; // rax\n __int64 v6; // r8\n int v7; // r9d\n int v8; // esi\n __int64 v9; // rcx\n _DWORD *v10; // rdx\n\n result = malloc(4LL * a2);\n if ( a2 <= 0 )\n {\n *a3 = 0;\n }\n else\n {\n v6 = 1LL;\n v7 = 0;\n if ( a2 != 1 )\n {\n while ( 2 )\n {\n while ( 2 )\n {\n v8 = *(_DWORD *)(a1 + 4 * v6 - 4);\n v9 = v6;\nLABEL_5:\n while ( v8 != *(_DWORD *)(a1 + 4 * v9) )\n {\n if ( a2 <= (int)++v9 )\n goto LABEL_13;\n }\n if ( v7 > 0 )\n {\n while ( 1 )\n {\n v10 = result;\n while ( v8 != *v10 )\n {\n if ( &result[v7] == ++v10 )\n goto LABEL_15;\n }\n if ( a2 <= (int)++v9 )\n break;\n if ( v8 != *(_DWORD *)(a1 + 4 * v9) )\n {\n if ( a2 > (int)++v9 )\n goto LABEL_5;\n break;\n }\n }\nLABEL_13:\n if ( ++v6 != a2 )\n continue;\n goto LABEL_14;\n }\n break;\n }\nLABEL_15:\n ++v6;\n result[v7++] = v8;\n if ( v6 != a2 )\n continue;\n break;\n }\n }\nLABEL_14:\n *a3 = v7;\n }\n return result;\n}", + "ida_strip_asm": "sub_1390:\nendbr64\npush r12\nmov r12, rdx\npush rbp\npush rbx\nmov rbx, rdi\nmovsxd rdi, esi\nmov rbp, rdi\nshl rdi, 2; size\ncall _malloc\ntest ebp, ebp\njle loc_1457\nmov r11d, ebp\nmov r8d, 1\nxor r9d, r9d\ncmp ebp, 1\njz short loc_1431\nnop word ptr [rax+rax+00000000h]\nloc_13D0:\nmovsxd r10, r9d\nmov esi, [rbx+r8*4-4]\nmov rcx, r8\nlea rdi, [rax+r10*4]\njmp short loc_13F0\nloc_13E8:\nadd rcx, 1\ncmp ebp, ecx\njle short loc_1428\nloc_13F0:\ncmp esi, [rbx+rcx*4]\njnz short loc_13E8\ntest r9d, r9d\njle short loc_1440\nloc_13FA:\nmov rdx, rax\njmp short loc_1409\nloc_1400:\nadd rdx, 4\ncmp rdi, rdx\njz short loc_1440\nloc_1409:\ncmp esi, [rdx]\njnz short loc_1400\nadd rcx, 1\ncmp ebp, ecx\njle short loc_1428\ncmp esi, [rbx+rcx*4]\njz short loc_13FA\nadd rcx, 1\ncmp ebp, ecx\njg short loc_13F0\nnop word ptr [rax+rax+00h]\nloc_1428:\nadd r8, 1\ncmp r8, r11\njnz short loc_13D0\nloc_1431:\nmov [r12], r9d\npop rbx\npop rbp\npop r12\nretn\nloc_1440:\nadd r8, 1\nmov [rax+r10*4], esi\nadd r9d, 1\ncmp r8, r11\njnz loc_13D0\njmp short loc_1431\nloc_1457:\nxor r9d, r9d\nmov [r12], r9d\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1390(__int64 a1, int a2, int *a3)\n{\n _DWORD *result; // rax\n __int64 v6; // r8\n int v7; // r9d\n int v8; // esi\n __int64 v9; // rcx\n _DWORD *v10; // rdx\n\n result = malloc(4LL * a2);\n if ( a2 <= 0 )\n {\n *a3 = 0;\n }\n else\n {\n v6 = 1LL;\n v7 = 0;\n if ( a2 != 1 )\n {\n while ( 2 )\n {\n while ( 2 )\n {\n v8 = *(_DWORD *)(a1 + 4 * v6 - 4);\n v9 = v6;\nLABEL_5:\n while ( v8 != *(_DWORD *)(a1 + 4 * v9) )\n {\n if ( a2 <= (int)++v9 )\n goto LABEL_13;\n }\n if ( v7 > 0 )\n {\n while ( 1 )\n {\n v10 = result;\n while ( v8 != *v10 )\n {\n if ( &result[v7] == ++v10 )\n goto LABEL_15;\n }\n if ( a2 <= (int)++v9 )\n break;\n if ( v8 != *(_DWORD *)(a1 + 4 * v9) )\n {\n if ( a2 > (int)++v9 )\n goto LABEL_5;\n break;\n }\n }\nLABEL_13:\n if ( ++v6 != a2 )\n continue;\n goto LABEL_14;\n }\n break;\n }\nLABEL_15:\n ++v6;\n result[v7++] = v8;\n if ( v6 != a2 )\n continue;\n break;\n }\n }\nLABEL_14:\n *a3 = v7;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1390(long long a1, int a2, int *a3) {\n uint32_t *result;\n long long v6;\n int v7;\n int v8;\n long long v9;\n uint32_t *v10;\n result = malloc(4LL * a2);\n if (a2 <= 0) {\n *a3 = 0;\n } else {\n v6 = 1LL;\n v7 = 0;\n if (a2 != 1) {\n while (2) {\n while (2) {\n v8 = *(uint32_t *)(a1 + 4 * v6 - 4);\n v9 = v6;\n LABEL_5:\n while (v8 != *(uint32_t *)(a1 + 4 * v9)) {\n if (a2 <= (int)++v9) goto LABEL_13;\n }\n if (v7 > 0) {\n while (1) {\n v10 = result;\n while (v8 != *v10) {\n if (&result[v7] == ++v10) goto LABEL_15;\n }\n if (a2 <= (int)++v9) break;\n if (v8 != *(uint32_t *)(a1 + 4 * v9)) {\n if (a2 > (int)++v9) goto LABEL_5;\n break;\n }\n }\n LABEL_13:\n if (++v6 != a2) continue;\n goto LABEL_14;\n }\n break;\n }\n LABEL_15:\n ++v6;\n result[v7++] = v8;\n if (v6 != a2) continue;\n break;\n }\n }\n LABEL_14:\n *a3 = v7;\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, int *a3) {\n uint32_t *result;\n long long v6;\n int v7;\n int v8;\n long long v9;\n uint32_t *v10;\n result = malloc(4LL * a2);\n if (a2 <= 0) {\n *a3 = 0;\n } else {\n v6 = 1LL;\n v7 = 0;\n if (a2 != 1) {\n while (2) {\n while (2) {\n v8 = *(uint32_t *)(a1 + 4 * v6 - 4);\n v9 = v6;\n LABEL_5:\n while (v8 != *(uint32_t *)(a1 + 4 * v9)) {\n if (a2 <= (int)++v9) goto LABEL_13;\n }\n if (v7 > 0) {\n while (1) {\n v10 = result;\n while (v8 != *v10) {\n if (&result[v7] == ++v10) goto LABEL_15;\n }\n if (a2 <= (int)++v9) break;\n if (v8 != *(uint32_t *)(a1 + 4 * v9)) {\n if (a2 > (int)++v9) goto LABEL_5;\n break;\n }\n }\n LABEL_13:\n if (++v6 != a2) continue;\n goto LABEL_14;\n }\n break;\n }\n LABEL_15:\n ++v6;\n result[v7++] = v8;\n if (v6 != a2) continue;\n break;\n }\n }\n LABEL_14:\n *a3 = v7;\n }\n return result;\n}" + }, + { + "index": 659, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\nvoid assertArrayEquals(int *expected, int expectedSize, int *actual, int actualSize) {\n\n assert(expectedSize == actualSize);\n\n for (int i = 0; i < expectedSize; i++) {\n\n assert(expected[i] == actual[i]);\n\n }\n\n}\n\n\n\n", + "func": "int *func0(int x[], int size, int *returnSize) {\n int *repeated = malloc(sizeof(int) * size);\n int count = 0;\n bool found;\n for (int i = 0; i < size; i++) {\n found = false;\n for (int j = i + 1; j < size; j++) {\n if (x[i] == x[j]) {\n found = true;\n for (int k = 0; k < count; k++) {\n if (repeated[k] == x[i]) {\n found = false;\n break;\n }\n }\n if (found) {\n repeated[count++] = x[i];\n break;\n }\n }\n }\n }\n *returnSize = count;\n return repeated;\n}", + "test": "int main() {\n\n int arr1[] = {10, 20, 30, 20, 20, 30, 40, 50, -20, 60, 60, -20, -20};\n\n int expected1[] = {20, 30, -20, 60};\n\n int size1;\n\n int *result1 = func0(arr1, 13, &size1);\n\n assertArrayEquals(expected1, 4, result1, size1);\n\n free(result1);\n\n \n\n int arr2[] = {-1, 1, -1, 8};\n\n int expected2[] = {-1};\n\n int size2;\n\n int *result2 = func0(arr2, 4, &size2);\n\n assertArrayEquals(expected2, 1, result2, size2);\n\n free(result2);\n\n \n\n int arr3[] = {1, 2, 3, 1, 2};\n\n int expected3[] = {1, 2};\n\n int size3;\n\n int *result3 = func0(arr3, 5, &size3);\n\n assertArrayEquals(expected3, 2, result3, size3);\n\n free(result3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %rdx,%r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nmovslq %esi,%rdi\nmov %rdi,%rbp\nshl $0x2,%rdi\ncallq 10b0 \nmov %rax,%r9\ntest %ebp,%ebp\njle 1435 \ncmp $0x1,%ebp\nje 1435 \nlea -0x2(%rbp),%r10d\nmov $0x1,%edi\nlea 0x4(%rax),%r11\nxor %r8d,%r8d\nadd $0x2,%r10\nnopl 0x0(%rax)\nlea -0x1(%r8),%eax\nmov -0x4(%rbx,%rdi,4),%ecx\nmov %rdi,%rdx\nlea (%r11,%rax,4),%rsi\njmp 13f8 \nnopl 0x0(%rax)\nadd $0x1,%rdx\ncmp %edx,%ebp\njle 1420 \ncmp (%rbx,%rdx,4),%ecx\njne 13f0 \ntest %r8d,%r8d\nje 1415 \nmov %r9,%rax\nnopl (%rax)\ncmp (%rax),%ecx\nje 13f0 \nadd $0x4,%rax\ncmp %rsi,%rax\njne 1408 \nmovslq %r8d,%rax\nadd $0x1,%r8d\nmov %ecx,(%r9,%rax,4)\nadd $0x1,%rdi\ncmp %r10,%rdi\njne 13d8 \npop %rbx\nmov %r9,%rax\npop %rbp\nmov %r8d,(%r12)\npop %r12\nretq\nxor %r8d,%r8d\npop %rbx\nmov %r9,%rax\npop %rbp\nmov %r8d,(%r12)\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r12\nmov r12, rdx\npush rbp\npush rbx\nmov rbx, rdi\nmovsxd rdi, esi\nmov rbp, rdi\nshl rdi, 2; size\ncall _malloc\ntest ebp, ebp\njle loc_1457\nmov r11d, ebp\nmov r8d, 1\nxor r9d, r9d\ncmp ebp, 1\njz short loc_1431\nnop word ptr [rax+rax+00000000h]\nloc_13D0:\nmovsxd r10, r9d\nmov esi, [rbx+r8*4-4]\nmov rcx, r8\nlea rdi, [rax+r10*4]\njmp short loc_13F0\nloc_13E8:\nadd rcx, 1\ncmp ebp, ecx\njle short loc_1428\nloc_13F0:\ncmp esi, [rbx+rcx*4]\njnz short loc_13E8\ntest r9d, r9d\njle short loc_1440\nloc_13FA:\nmov rdx, rax\njmp short loc_1409\nloc_1400:\nadd rdx, 4\ncmp rdi, rdx\njz short loc_1440\nloc_1409:\ncmp esi, [rdx]\njnz short loc_1400\nadd rcx, 1\ncmp ebp, ecx\njle short loc_1428\ncmp esi, [rbx+rcx*4]\njz short loc_13FA\nadd rcx, 1\ncmp ebp, ecx\njg short loc_13F0\nnop word ptr [rax+rax+00h]\nloc_1428:\nadd r8, 1\ncmp r8, r11\njnz short loc_13D0\nloc_1431:\nmov [r12], r9d\npop rbx\npop rbp\npop r12\nretn\nloc_1440:\nadd r8, 1\nmov [rax+r10*4], esi\nadd r9d, 1\ncmp r8, r11\njnz loc_13D0\njmp short loc_1431\nloc_1457:\nxor r9d, r9d\nmov [r12], r9d\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, int *a3)\n{\n _DWORD *result; // rax\n __int64 v6; // r8\n int v7; // r9d\n int v8; // esi\n __int64 v9; // rcx\n _DWORD *v10; // rdx\n\n result = malloc(4LL * a2);\n if ( a2 <= 0 )\n {\n *a3 = 0;\n }\n else\n {\n v6 = 1LL;\n v7 = 0;\n if ( a2 != 1 )\n {\n while ( 2 )\n {\n while ( 2 )\n {\n v8 = *(_DWORD *)(a1 + 4 * v6 - 4);\n v9 = v6;\nLABEL_5:\n while ( v8 != *(_DWORD *)(a1 + 4 * v9) )\n {\n if ( a2 <= (int)++v9 )\n goto LABEL_13;\n }\n if ( v7 > 0 )\n {\n while ( 1 )\n {\n v10 = result;\n while ( v8 != *v10 )\n {\n if ( &result[v7] == ++v10 )\n goto LABEL_15;\n }\n if ( a2 <= (int)++v9 )\n break;\n if ( v8 != *(_DWORD *)(a1 + 4 * v9) )\n {\n if ( a2 > (int)++v9 )\n goto LABEL_5;\n break;\n }\n }\nLABEL_13:\n if ( ++v6 != a2 )\n continue;\n goto LABEL_14;\n }\n break;\n }\nLABEL_15:\n ++v6;\n result[v7++] = v8;\n if ( v6 != a2 )\n continue;\n break;\n }\n }\nLABEL_14:\n *a3 = v7;\n }\n return result;\n}", + "ida_strip_asm": "sub_1390:\nendbr64\npush r12\nmov r12, rdx\npush rbp\npush rbx\nmov rbx, rdi\nmovsxd rdi, esi\nmov rbp, rdi\nshl rdi, 2; size\ncall _malloc\ntest ebp, ebp\njle loc_1457\nmov r11d, ebp\nmov r8d, 1\nxor r9d, r9d\ncmp ebp, 1\njz short loc_1431\nnop word ptr [rax+rax+00000000h]\nloc_13D0:\nmovsxd r10, r9d\nmov esi, [rbx+r8*4-4]\nmov rcx, r8\nlea rdi, [rax+r10*4]\njmp short loc_13F0\nloc_13E8:\nadd rcx, 1\ncmp ebp, ecx\njle short loc_1428\nloc_13F0:\ncmp esi, [rbx+rcx*4]\njnz short loc_13E8\ntest r9d, r9d\njle short loc_1440\nloc_13FA:\nmov rdx, rax\njmp short loc_1409\nloc_1400:\nadd rdx, 4\ncmp rdi, rdx\njz short loc_1440\nloc_1409:\ncmp esi, [rdx]\njnz short loc_1400\nadd rcx, 1\ncmp ebp, ecx\njle short loc_1428\ncmp esi, [rbx+rcx*4]\njz short loc_13FA\nadd rcx, 1\ncmp ebp, ecx\njg short loc_13F0\nnop word ptr [rax+rax+00h]\nloc_1428:\nadd r8, 1\ncmp r8, r11\njnz short loc_13D0\nloc_1431:\nmov [r12], r9d\npop rbx\npop rbp\npop r12\nretn\nloc_1440:\nadd r8, 1\nmov [rax+r10*4], esi\nadd r9d, 1\ncmp r8, r11\njnz loc_13D0\njmp short loc_1431\nloc_1457:\nxor r9d, r9d\nmov [r12], r9d\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1390(__int64 a1, int a2, int *a3)\n{\n _DWORD *result; // rax\n __int64 v6; // r8\n int v7; // r9d\n int v8; // esi\n __int64 v9; // rcx\n _DWORD *v10; // rdx\n\n result = malloc(4LL * a2);\n if ( a2 <= 0 )\n {\n *a3 = 0;\n }\n else\n {\n v6 = 1LL;\n v7 = 0;\n if ( a2 != 1 )\n {\n while ( 2 )\n {\n while ( 2 )\n {\n v8 = *(_DWORD *)(a1 + 4 * v6 - 4);\n v9 = v6;\nLABEL_5:\n while ( v8 != *(_DWORD *)(a1 + 4 * v9) )\n {\n if ( a2 <= (int)++v9 )\n goto LABEL_13;\n }\n if ( v7 > 0 )\n {\n while ( 1 )\n {\n v10 = result;\n while ( v8 != *v10 )\n {\n if ( &result[v7] == ++v10 )\n goto LABEL_15;\n }\n if ( a2 <= (int)++v9 )\n break;\n if ( v8 != *(_DWORD *)(a1 + 4 * v9) )\n {\n if ( a2 > (int)++v9 )\n goto LABEL_5;\n break;\n }\n }\nLABEL_13:\n if ( ++v6 != a2 )\n continue;\n goto LABEL_14;\n }\n break;\n }\nLABEL_15:\n ++v6;\n result[v7++] = v8;\n if ( v6 != a2 )\n continue;\n break;\n }\n }\nLABEL_14:\n *a3 = v7;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1390(long long a1, int a2, int *a3) {\n uint32_t *result;\n long long v6;\n int v7;\n int v8;\n long long v9;\n uint32_t *v10;\n result = malloc(4LL * a2);\n if (a2 <= 0) {\n *a3 = 0;\n } else {\n v6 = 1LL;\n v7 = 0;\n if (a2 != 1) {\n while (2) {\n while (2) {\n v8 = *(uint32_t *)(a1 + 4 * v6 - 4);\n v9 = v6;\n LABEL_5:\n while (v8 != *(uint32_t *)(a1 + 4 * v9)) {\n if (a2 <= (int)++v9) goto LABEL_13;\n }\n if (v7 > 0) {\n while (1) {\n v10 = result;\n while (v8 != *v10) {\n if (&result[v7] == ++v10) goto LABEL_15;\n }\n if (a2 <= (int)++v9) break;\n if (v8 != *(uint32_t *)(a1 + 4 * v9)) {\n if (a2 > (int)++v9) goto LABEL_5;\n break;\n }\n }\n LABEL_13:\n if (++v6 != a2) continue;\n goto LABEL_14;\n }\n break;\n }\n LABEL_15:\n ++v6;\n result[v7++] = v8;\n if (v6 != a2) continue;\n break;\n }\n }\n LABEL_14:\n *a3 = v7;\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, int *a3) {\n uint32_t *result;\n long long v6;\n int v7;\n int v8;\n long long v9;\n uint32_t *v10;\n result = malloc(4LL * a2);\n if (a2 <= 0) {\n *a3 = 0;\n } else {\n v6 = 1LL;\n v7 = 0;\n if (a2 != 1) {\n while (2) {\n while (2) {\n v8 = *(uint32_t *)(a1 + 4 * v6 - 4);\n v9 = v6;\n LABEL_5:\n while (v8 != *(uint32_t *)(a1 + 4 * v9)) {\n if (a2 <= (int)++v9) goto LABEL_13;\n }\n if (v7 > 0) {\n while (1) {\n v10 = result;\n while (v8 != *v10) {\n if (&result[v7] == ++v10) goto LABEL_15;\n }\n if (a2 <= (int)++v9) break;\n if (v8 != *(uint32_t *)(a1 + 4 * v9)) {\n if (a2 > (int)++v9) goto LABEL_5;\n break;\n }\n }\n LABEL_13:\n if (++v6 != a2) continue;\n goto LABEL_14;\n }\n break;\n }\n LABEL_15:\n ++v6;\n result[v7++] = v8;\n if (v6 != a2) continue;\n break;\n }\n }\n LABEL_14:\n *a3 = v7;\n }\n return result;\n}" + }, + { + "index": 660, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int l1, int r1, int l2, int r2, int *x, int *y) {\n *x = (l1 != l2) ? ((l1 < l2) ? l1 : l2) : -1;\n *y = (r1 != r2) ? ((r1 > r2) ? r1 : r2) : -1;\n return 0;\n}", + "test": "int main() {\n\n int x, y;\n\n func0(5, 10, 1, 5, &x, &y);\n\n assert(x == 1 && y == 10);\n\n\n\n func0(3, 5, 7, 9, &x, &y);\n\n assert(x == 3 && y == 9);\n\n\n\n func0(1, 5, 2, 8, &x, &y);\n\n assert(x == 1 && y == 8);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov %esi,-0x8(%rbp)\nmov %edx,-0xc(%rbp)\nmov %ecx,-0x10(%rbp)\nmov %r8,-0x18(%rbp)\nmov %r9,-0x20(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0xc(%rbp),%eax\nje 1199 \nmov -0x4(%rbp),%eax\ncmp %eax,-0xc(%rbp)\ncmovle -0xc(%rbp),%eax\njmp 119e \nmov $0xffffffff,%eax\nmov -0x18(%rbp),%rdx\nmov %eax,(%rdx)\nmov -0x8(%rbp),%eax\ncmp -0x10(%rbp),%eax\nje 11b8 \nmov -0x8(%rbp),%eax\ncmp %eax,-0x10(%rbp)\ncmovge -0x10(%rbp),%eax\njmp 11bd \nmov $0xffffffff,%eax\nmov -0x20(%rbp),%rdx\nmov %eax,(%rdx)\nmov $0x0,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov [rbp+var_C], edx\nmov [rbp+var_10], ecx\nmov [rbp+var_18], r8\nmov [rbp+var_20], r9\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_C]\njz short loc_119A\nmov edx, [rbp+var_C]\nmov eax, [rbp+var_4]\ncmp edx, eax\ncmovle eax, edx\njmp short loc_119F\nloc_119A:\nmov eax, 0FFFFFFFFh\nloc_119F:\nmov rdx, [rbp+var_18]\nmov [rdx], eax\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_10]\njz short loc_11BA\nmov edx, [rbp+var_10]\nmov eax, [rbp+var_8]\ncmp edx, eax\ncmovge eax, edx\njmp short loc_11BF\nloc_11BA:\nmov eax, 0FFFFFFFFh\nloc_11BF:\nmov rdx, [rbp+var_20]\nmov [rdx], eax\nmov eax, 0\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, int a3, int a4, int *a5, int *a6)\n{\n int v6; // eax\n int v7; // eax\n\n if ( a1 == a3 )\n {\n v6 = -1;\n }\n else\n {\n v6 = a1;\n if ( a3 <= a1 )\n v6 = a3;\n }\n *a5 = v6;\n if ( a2 == a4 )\n {\n v7 = -1;\n }\n else\n {\n v7 = a2;\n if ( a4 >= a2 )\n v7 = a4;\n }\n *a6 = v7;\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov [rbp+var_C], edx\nmov [rbp+var_10], ecx\nmov [rbp+var_18], r8\nmov [rbp+var_20], r9\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_C]\njz short loc_119A\nmov edx, [rbp+var_C]\nmov eax, [rbp+var_4]\ncmp edx, eax\ncmovle eax, edx\njmp short loc_119F\nloc_119A:\nmov eax, 0FFFFFFFFh\nloc_119F:\nmov rdx, [rbp+var_18]\nmov [rdx], eax\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_10]\njz short loc_11BA\nmov edx, [rbp+var_10]\nmov eax, [rbp+var_8]\ncmp edx, eax\ncmovge eax, edx\njmp short loc_11BF\nloc_11BA:\nmov eax, 0FFFFFFFFh\nloc_11BF:\nmov rdx, [rbp+var_20]\nmov [rdx], eax\nmov eax, 0\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1, int a2, int a3, int a4, int *a5, int *a6)\n{\n int v6; // eax\n int v7; // eax\n\n if ( a1 == a3 )\n {\n v6 = -1;\n }\n else\n {\n v6 = a1;\n if ( a3 <= a1 )\n v6 = a3;\n }\n *a5 = v6;\n if ( a2 == a4 )\n {\n v7 = -1;\n }\n else\n {\n v7 = a2;\n if ( a4 >= a2 )\n v7 = a4;\n }\n *a6 = v7;\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1, int a2, int a3, int a4, int *a5, int *a6) {\n int v6;\n int v7;\n if (a1 == a3) {\n v6 = -1;\n } else {\n v6 = a1;\n if (a3 <= a1) v6 = a3;\n }\n *a5 = v6;\n if (a2 == a4) {\n v7 = -1;\n } else {\n v7 = a2;\n if (a4 >= a2) v7 = a4;\n }\n *a6 = v7;\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, int a3, int a4, int *a5, int *a6) {\n int v6;\n int v7;\n if (a1 == a3) {\n v6 = -1;\n } else {\n v6 = a1;\n if (a3 <= a1) v6 = a3;\n }\n *a5 = v6;\n if (a2 == a4) {\n v7 = -1;\n } else {\n v7 = a2;\n if (a4 >= a2) v7 = a4;\n }\n *a6 = v7;\n return 0LL;\n}" + }, + { + "index": 661, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int sum[n];\n if (n >= 1) sum[0] = arr[0];\n if (n >= 2) sum[1] = arr[0] + arr[1];\n if (n > 2)\n sum[2] = (sum[1] > (arr[1] + arr[2]) ? sum[1] : (arr[1] + arr[2])) >\n (arr[0] + arr[2])\n ? (sum[1] > (arr[1] + arr[2]) ? sum[1] : (arr[1] + arr[2]))\n : (arr[0] + arr[2]);\n for (int i = 3; i < n; i++) {\n int max1 = sum[i - 1];\n int max2 = sum[i - 2] + arr[i];\n int max3 = arr[i] + arr[i - 1] + sum[i - 3];\n sum[i] =\n (max1 > max2 ? max1 : max2) > max3 ? (max1 > max2 ? max1 : max2) : max3;\n }\n return sum[n - 1];\n}", + "test": "int main() {\n\n assert(func0((int[]){100, 1000, 100, 1000, 1}, 5) == 2101);\n\n assert(func0((int[]){3000, 2000, 1000, 3, 10}, 5) == 5013);\n\n assert(func0((int[]){1, 2, 3, 4, 5, 6, 7, 8}, 8) == 27);\n\n \n\n printf(\"All tests passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x48,%rsp\nmov %rdi,-0x48(%rbp)\nmov %esi,-0x4c(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmov %rsp,%rax\nmov %rax,%rsi\nmov -0x4c(%rbp),%eax\nmovslq %eax,%rdx\nsub $0x1,%rdx\nmov %rdx,-0x28(%rbp)\nmovslq %eax,%rdx\nmov %rdx,%r8\nmov $0x0,%r9d\nmovslq %eax,%rdx\nmov %rdx,%rcx\nmov $0x0,%ebx\ncltq\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%edi\nmov $0x0,%edx\ndiv %rdi\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rbx\nsub %rdx,%rbx\nmov %rbx,%rdx\ncmp %rdx,%rsp\nje 1228 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 1211 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 1252 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x20(%rbp)\ncmpl $0x0,-0x4c(%rbp)\njle 1277 \nmov -0x48(%rbp),%rax\nmov (%rax),%edx\nmov -0x20(%rbp),%rax\nmov %edx,(%rax)\ncmpl $0x1,-0x4c(%rbp)\njle 1296 \nmov -0x48(%rbp),%rax\nmov (%rax),%edx\nmov -0x48(%rbp),%rax\nadd $0x4,%rax\nmov (%rax),%eax\nadd %eax,%edx\nmov -0x20(%rbp),%rax\nmov %edx,0x4(%rax)\ncmpl $0x2,-0x4c(%rbp)\njle 12dc \nmov -0x48(%rbp),%rax\nmov (%rax),%edx\nmov -0x48(%rbp),%rax\nadd $0x8,%rax\nmov (%rax),%eax\nadd %eax,%edx\nmov -0x48(%rbp),%rax\nadd $0x4,%rax\nmov (%rax),%ecx\nmov -0x48(%rbp),%rax\nadd $0x8,%rax\nmov (%rax),%eax\nadd %eax,%ecx\nmov -0x20(%rbp),%rax\nmov 0x4(%rax),%eax\ncmp %eax,%ecx\ncmovge %ecx,%eax\ncmp %eax,%edx\ncmovl %eax,%edx\nmov -0x20(%rbp),%rax\nmov %edx,0x8(%rax)\nmovl $0x3,-0x38(%rbp)\njmpq 138e \nmov -0x38(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x20(%rbp),%rax\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nmov %eax,-0x34(%rbp)\nmov -0x38(%rbp),%eax\nlea -0x2(%rax),%edx\nmov -0x20(%rbp),%rax\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%edx\nmov -0x38(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x48(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\nadd %edx,%eax\nmov %eax,-0x30(%rbp)\nmov -0x38(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x38(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rcx\nmov -0x48(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\nlea (%rdx,%rax,1),%ecx\nmov -0x38(%rbp),%eax\nlea -0x3(%rax),%edx\nmov -0x20(%rbp),%rax\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nadd %ecx,%eax\nmov %eax,-0x2c(%rbp)\nmov -0x34(%rbp),%eax\ncmp %eax,-0x30(%rbp)\ncmovge -0x30(%rbp),%eax\ncmp %eax,-0x2c(%rbp)\ncmovge -0x2c(%rbp),%eax\nmov %eax,%ecx\nmov -0x20(%rbp),%rax\nmov -0x38(%rbp),%edx\nmovslq %edx,%rdx\nmov %ecx,(%rax,%rdx,4)\naddl $0x1,-0x38(%rbp)\nmov -0x38(%rbp),%eax\ncmp -0x4c(%rbp),%eax\njl 12e8 \nmov -0x4c(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x20(%rbp),%rax\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nmov %rsi,%rsp\nmov -0x18(%rbp),%rdi\nxor %fs:0x28,%rdi\nje 13c1 \ncallq 1080 <__stack_chk_fail@plt>\nmov -0x8(%rbp),%rbx\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov eax, [rbp+var_3C]\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11F6:\ncmp rsp, rdx\njz short loc_120D\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_11F6\nloc_120D:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1237\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1237:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\ncmp [rbp+var_3C], 0\njle short loc_125C\nmov rax, [rbp+var_38]\nmov edx, [rax]\nmov rax, [rbp+var_10]\nmov [rax], edx\nloc_125C:\ncmp [rbp+var_3C], 1\njle short loc_127B\nmov rax, [rbp+var_38]\nmov edx, [rax]\nmov rax, [rbp+var_38]\nadd rax, 4\nmov eax, [rax]\nadd edx, eax\nmov rax, [rbp+var_10]\nmov [rax+4], edx\nloc_127B:\ncmp [rbp+var_3C], 2\njle short loc_12C1\nmov rax, [rbp+var_38]\nmov edx, [rax]\nmov rax, [rbp+var_38]\nadd rax, 8\nmov eax, [rax]\nadd edx, eax\nmov rax, [rbp+var_38]\nadd rax, 4\nmov ecx, [rax]\nmov rax, [rbp+var_38]\nadd rax, 8\nmov eax, [rax]\nadd ecx, eax\nmov rax, [rbp+var_10]\nmov eax, [rax+4]\ncmp ecx, eax\ncmovge eax, ecx\ncmp edx, eax\ncmovl edx, eax\nmov rax, [rbp+var_10]\nmov [rax+8], edx\nloc_12C1:\nmov [rbp+var_28], 3\njmp loc_1375\nloc_12CD:\nmov eax, [rbp+var_28]\nlea edx, [rax-1]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov [rbp+var_24], eax\nmov eax, [rbp+var_28]\nlea edx, [rax-2]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov edx, [rax+rdx*4]\nmov eax, [rbp+var_28]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov eax, [rax]\nadd eax, edx\nmov [rbp+var_20], eax\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_28]\ncdqe\nshl rax, 2\nlea rcx, [rax-4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov eax, [rax]\nlea ecx, [rdx+rax]\nmov eax, [rbp+var_28]\nlea edx, [rax-3]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nadd eax, ecx\nmov [rbp+var_1C], eax\nmov edx, [rbp+var_20]\nmov eax, [rbp+var_24]\ncmp edx, eax\ncmovl edx, eax\nmov eax, [rbp+var_1C]\ncmp edx, eax\ncmovge eax, edx\nmov ecx, eax\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nadd [rbp+var_28], 1\nloc_1375:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_3C]\njl loc_12CD\nmov eax, [rbp+var_3C]\nlea edx, [rax-1]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_13A8\ncall ___stack_chk_fail\nlocret_13A8:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n unsigned __int64 v2; // rax\n void *v3; // rsp\n int v4; // edx\n int v5; // eax\n int v6; // edx\n int v7; // eax\n _BYTE v9[4]; // [rsp+8h] [rbp-40h] BYREF\n int v10; // [rsp+Ch] [rbp-3Ch]\n _DWORD *v11; // [rsp+10h] [rbp-38h]\n int i; // [rsp+20h] [rbp-28h]\n int v13; // [rsp+24h] [rbp-24h]\n int v14; // [rsp+28h] [rbp-20h]\n int v15; // [rsp+2Ch] [rbp-1Ch]\n __int64 v16; // [rsp+30h] [rbp-18h]\n _DWORD *v17; // [rsp+38h] [rbp-10h]\n unsigned __int64 v18; // [rsp+40h] [rbp-8h]\n\n v11 = a1;\n v10 = a2;\n v18 = __readfsqword(0x28u);\n v16 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 0x10uLL);\n while ( v9 != &v9[-(v2 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = alloca(v2 & 0xFFF);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)&v9[(v2 & 0xFFF) - 8] = *(_QWORD *)&v9[(v2 & 0xFFF) - 8];\n v17 = v9;\n if ( v10 > 0 )\n *v17 = *v11;\n if ( v10 > 1 )\n v17[1] = v11[1] + *v11;\n if ( v10 > 2 )\n {\n v4 = v11[2] + *v11;\n v5 = v17[1];\n if ( v11[2] + v11[1] >= v5 )\n v5 = v11[2] + v11[1];\n if ( v4 < v5 )\n v4 = v5;\n v17[2] = v4;\n }\n for ( i = 3; i < v10; ++i )\n {\n v13 = v17[i - 1];\n v14 = v17[i - 2] + v11[i];\n v15 = v11[i] + v11[i - 1] + v17[i - 3];\n v6 = v14;\n if ( v14 < v13 )\n v6 = v13;\n v7 = v15;\n if ( v6 >= v15 )\n v7 = v6;\n v17[i] = v7;\n }\n return (unsigned int)v17[v10 - 1];\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov eax, [rbp+var_3C]\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11F6:\ncmp rsp, rdx\njz short loc_120D\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_11F6\nloc_120D:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1237\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1237:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\ncmp [rbp+var_3C], 0\njle short loc_125C\nmov rax, [rbp+var_38]\nmov edx, [rax]\nmov rax, [rbp+var_10]\nmov [rax], edx\nloc_125C:\ncmp [rbp+var_3C], 1\njle short loc_127B\nmov rax, [rbp+var_38]\nmov edx, [rax]\nmov rax, [rbp+var_38]\nadd rax, 4\nmov eax, [rax]\nadd edx, eax\nmov rax, [rbp+var_10]\nmov [rax+4], edx\nloc_127B:\ncmp [rbp+var_3C], 2\njle short loc_12C1\nmov rax, [rbp+var_38]\nmov edx, [rax]\nmov rax, [rbp+var_38]\nadd rax, 8\nmov eax, [rax]\nadd edx, eax\nmov rax, [rbp+var_38]\nadd rax, 4\nmov ecx, [rax]\nmov rax, [rbp+var_38]\nadd rax, 8\nmov eax, [rax]\nadd ecx, eax\nmov rax, [rbp+var_10]\nmov eax, [rax+4]\ncmp ecx, eax\ncmovge eax, ecx\ncmp edx, eax\ncmovl edx, eax\nmov rax, [rbp+var_10]\nmov [rax+8], edx\nloc_12C1:\nmov [rbp+var_28], 3\njmp loc_1375\nloc_12CD:\nmov eax, [rbp+var_28]\nlea edx, [rax-1]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov [rbp+var_24], eax\nmov eax, [rbp+var_28]\nlea edx, [rax-2]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov edx, [rax+rdx*4]\nmov eax, [rbp+var_28]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov eax, [rax]\nadd eax, edx\nmov [rbp+var_20], eax\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_28]\ncdqe\nshl rax, 2\nlea rcx, [rax-4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov eax, [rax]\nlea ecx, [rdx+rax]\nmov eax, [rbp+var_28]\nlea edx, [rax-3]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nadd eax, ecx\nmov [rbp+var_1C], eax\nmov edx, [rbp+var_20]\nmov eax, [rbp+var_24]\ncmp edx, eax\ncmovl edx, eax\nmov eax, [rbp+var_1C]\ncmp edx, eax\ncmovge eax, edx\nmov ecx, eax\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nadd [rbp+var_28], 1\nloc_1375:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_3C]\njl loc_12CD\nmov eax, [rbp+var_3C]\nlea edx, [rax-1]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_13A8\ncall ___stack_chk_fail\nlocret_13A8:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(_DWORD *a1, int a2)\n{\n unsigned __int64 v2; // rax\n void *v3; // rsp\n int v4; // edx\n int v5; // eax\n int v6; // edx\n int v7; // eax\n _BYTE v9[4]; // [rsp+8h] [rbp-40h] BYREF\n int v10; // [rsp+Ch] [rbp-3Ch]\n _DWORD *v11; // [rsp+10h] [rbp-38h]\n int i; // [rsp+20h] [rbp-28h]\n int v13; // [rsp+24h] [rbp-24h]\n int v14; // [rsp+28h] [rbp-20h]\n int v15; // [rsp+2Ch] [rbp-1Ch]\n __int64 v16; // [rsp+30h] [rbp-18h]\n _DWORD *v17; // [rsp+38h] [rbp-10h]\n unsigned __int64 v18; // [rsp+40h] [rbp-8h]\n\n v11 = a1;\n v10 = a2;\n v18 = __readfsqword(0x28u);\n v16 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 0x10uLL);\n while ( v9 != &v9[-(v2 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = alloca(v2 & 0xFFF);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)&v9[(v2 & 0xFFF) - 8] = *(_QWORD *)&v9[(v2 & 0xFFF) - 8];\n v17 = v9;\n if ( v10 > 0 )\n *v17 = *v11;\n if ( v10 > 1 )\n v17[1] = v11[1] + *v11;\n if ( v10 > 2 )\n {\n v4 = v11[2] + *v11;\n v5 = v17[1];\n if ( v11[2] + v11[1] >= v5 )\n v5 = v11[2] + v11[1];\n if ( v4 < v5 )\n v4 = v5;\n v17[2] = v4;\n }\n for ( i = 3; i < v10; ++i )\n {\n v13 = v17[i - 1];\n v14 = v17[i - 2] + v11[i];\n v15 = v11[i] + v11[i - 1] + v17[i - 3];\n v6 = v14;\n if ( v14 < v13 )\n v6 = v13;\n v7 = v15;\n if ( v6 >= v15 )\n v7 = v6;\n v17[i] = v7;\n }\n return (unsigned int)v17[v10 - 1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(uint32_t *a1, int a2) {\n unsigned long long v2;\n void *v3;\n int v4;\n int v5;\n int v6;\n int v7;\n uint8_t v9[4];\n int v10;\n uint32_t *v11;\n int i;\n int v13;\n int v14;\n int v15;\n long long v16;\n uint32_t *v17;\n unsigned long long v18;\n v11 = a1;\n v10 = a2;\n v18 = __readfsqword(40u);\n v16 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 16uLL);\n while (v9 != &v9[-(v2 & 18446744073709547520LL)])\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)&v9[(v2 & 4095) - 8] = *(uint64_t *)&v9[(v2 & 4095) - 8];\n v17 = v9;\n if (v10 > 0) *v17 = *v11;\n if (v10 > 1) v17[1] = v11[1] + *v11;\n if (v10 > 2) {\n v4 = v11[2] + *v11;\n v5 = v17[1];\n if (v11[2] + v11[1] >= v5) v5 = v11[2] + v11[1];\n if (v4 < v5) v4 = v5;\n v17[2] = v4;\n }\n for (i = 3; i < v10; ++i) {\n v13 = v17[i - 1];\n v14 = v17[i - 2] + v11[i];\n v15 = v11[i] + v11[i - 1] + v17[i - 3];\n v6 = v14;\n if (v14 < v13) v6 = v13;\n v7 = v15;\n if (v6 >= v15) v7 = v6;\n v17[i] = v7;\n }\n return (unsigned int)v17[v10 - 1];\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n unsigned long long v2;\n void *v3;\n int v4;\n int v5;\n int v6;\n int v7;\n uint8_t v9[4];\n int v10;\n uint32_t *v11;\n int i;\n int v13;\n int v14;\n int v15;\n long long v16;\n uint32_t *v17;\n unsigned long long v18;\n v11 = a1;\n v10 = a2;\n v18 = __readfsqword(40u);\n v16 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 16uLL);\n while (v9 != &v9[-(v2 & 18446744073709547520LL)])\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)&v9[(v2 & 4095) - 8] = *(uint64_t *)&v9[(v2 & 4095) - 8];\n v17 = v9;\n if (v10 > 0) *v17 = *v11;\n if (v10 > 1) v17[1] = v11[1] + *v11;\n if (v10 > 2) {\n v4 = v11[2] + *v11;\n v5 = v17[1];\n if (v11[2] + v11[1] >= v5) v5 = v11[2] + v11[1];\n if (v4 < v5) v4 = v5;\n v17[2] = v4;\n }\n for (i = 3; i < v10; ++i) {\n v13 = v17[i - 1];\n v14 = v17[i - 2] + v11[i];\n v15 = v11[i] + v11[i - 1] + v17[i - 3];\n v6 = v14;\n if (v14 < v13) v6 = v13;\n v7 = v15;\n if (v6 >= v15) v7 = v6;\n v17[i] = v7;\n }\n return (unsigned int)v17[v10 - 1];\n}" + }, + { + "index": 661, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int sum[n];\n if (n >= 1) sum[0] = arr[0];\n if (n >= 2) sum[1] = arr[0] + arr[1];\n if (n > 2)\n sum[2] = (sum[1] > (arr[1] + arr[2]) ? sum[1] : (arr[1] + arr[2])) >\n (arr[0] + arr[2])\n ? (sum[1] > (arr[1] + arr[2]) ? sum[1] : (arr[1] + arr[2]))\n : (arr[0] + arr[2]);\n for (int i = 3; i < n; i++) {\n int max1 = sum[i - 1];\n int max2 = sum[i - 2] + arr[i];\n int max3 = arr[i] + arr[i - 1] + sum[i - 3];\n sum[i] =\n (max1 > max2 ? max1 : max2) > max3 ? (max1 > max2 ? max1 : max2) : max3;\n }\n return sum[n - 1];\n}", + "test": "int main() {\n\n assert(func0((int[]){100, 1000, 100, 1000, 1}, 5) == 2101);\n\n assert(func0((int[]){3000, 2000, 1000, 3, 10}, 5) == 5013);\n\n assert(func0((int[]){1, 2, 3, 4, 5, 6, 7, 8}, 8) == 27);\n\n \n\n printf(\"All tests passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovslq %esi,%rax\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffffff0,%rdx\nand $0xfffffffffffff000,%rax\nmov %rsp,%rcx\nsub %rax,%rcx\nmov %rcx,%rax\ncmp %rax,%rsp\nje 11dc \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11c5 \nmov %rdx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 11f2 \norq $0x0,-0x8(%rsp,%rax,1)\nlea 0x3(%rsp),%r9\nmov %r9,%rcx\nshr $0x2,%rcx\nand $0xfffffffffffffffc,%r9\ntest %esi,%esi\njle 120f \nmov (%rdi),%eax\nmov %eax,0x0(,%rcx,4)\ncmp $0x1,%esi\njle 1220 \nmov 0x4(%rdi),%eax\nadd (%rdi),%eax\nmov %eax,0x4(,%rcx,4)\ncmp $0x2,%esi\njle 1247 \nmov 0x8(%rdi),%edx\nmov %edx,%eax\nadd (%rdi),%eax\nadd 0x4(%rdi),%edx\ncmp %edx,%eax\ncmovl %edx,%eax\nmov 0x4(,%rcx,4),%edx\ncmp %edx,%eax\ncmovl %edx,%eax\nmov %eax,0x8(,%rcx,4)\ncmp $0x3,%esi\njle 1287 \nmov %r9,%rcx\nadd $0x8,%rdi\nlea -0x4(%rsi),%eax\nlea 0x4(%r9,%rax,4),%r10\nmov 0x4(%rdi),%edx\nmov %edx,%eax\nadd 0x4(%rcx),%eax\nmov 0x8(%rcx),%r8d\ncmp %r8d,%eax\ncmovl %r8d,%eax\nadd (%rdi),%edx\nadd (%rcx),%edx\ncmp %edx,%eax\ncmovl %edx,%eax\nmov %eax,0xc(%rcx)\nadd $0x4,%rcx\nadd $0x4,%rdi\ncmp %r10,%rcx\njne 125b \nsub $0x1,%esi\nmovslq %esi,%rsi\nmov (%r9,%rsi,4),%eax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\njne 12a2 \nleaveq\nretq\ncallq 1080 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov rax, rdi\nmov r8d, esi\nmov rdx, fs:28h\nmov [rbp+var_8], rdx\nxor edx, edx\nmovsxd rdx, esi\nlea rdx, ds:0Fh[rdx*4]\nmov rsi, rdx\nand rsi, 0FFFFFFFFFFFFFFF0h\nand rdx, 0FFFFFFFFFFFFF000h\nmov rcx, rsp\nsub rcx, rdx\nloc_11C9:\ncmp rsp, rcx\njz short loc_11E0\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11C9\nloc_11E0:\nmov rdx, rsi\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njz short loc_11F7\nor [rsp+rdx+10h+var_18], 0\nloc_11F7:\nlea r9, [rsp+10h+var_D]\nmov r10, r9\nshr r10, 2\nand r9, 0FFFFFFFFFFFFFFFCh\ntest r8d, r8d\njle short loc_1287\nmov edx, [rax]\nmov ds:dword_0[r10*4], edx\ncmp r8d, 1\njle short loc_1287\nmov ecx, [rax+4]\nlea edi, [rdx+rcx]\nmov dword ptr ds:byte_4[r10*4], edi\ncmp r8d, 2\njle short loc_1287\nmov esi, [rax+8]\nadd edx, esi\nadd ecx, esi\ncmp edx, ecx\ncmovl edx, ecx\ncmp edx, edi\ncmovl edx, edi\nmov dword ptr ds:byte_8[r10*4], edx\ncmp r8d, 3\njle short loc_1287\nmov rcx, r9\nlea rsi, [rax+8]\nlea eax, [r8-3]\nlea r10, [r9+rax*4]\nloc_125E:\nmov edx, [rsi+4]\nmov eax, edx\nadd eax, [rcx+4]\nmov edi, [rcx+8]\ncmp eax, edi\ncmovl eax, edi\nadd edx, [rsi]\nadd edx, [rcx]\ncmp eax, edx\ncmovl eax, edx\nmov [rcx+0Ch], eax\nadd rcx, 4\nadd rsi, 4\ncmp rcx, r10\njnz short loc_125E\nloc_1287:\nsub r8d, 1\nmovsxd r8, r8d\nmov eax, [r9+r8*4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_12A3\nleave\nretn\nloc_12A3:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n __int64 v4; // rdx\n __int16 v5; // si\n signed __int64 v6; // rdx\n void *v7; // rsp\n int v8; // edx\n int v9; // ecx\n int v10; // edi\n int v11; // esi\n int v12; // edx\n int v13; // ecx\n _DWORD *v14; // rcx\n _DWORD *v15; // rsi\n int v16; // eax\n _DWORD v19[2]; // [rsp+8h] [rbp-10h] BYREF\n unsigned __int64 v20; // [rsp+10h] [rbp-8h]\n\n v20 = __readfsqword(0x28u);\n v4 = 4LL * a2 + 15;\n v5 = (4 * a2 + 15) & 0xFFF0;\n while ( v19 != (_DWORD *)((char *)v19 - (v4 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v6 = v5 & 0xFFF;\n v7 = alloca(v6);\n if ( (v5 & 0xFFF) != 0 )\n *(_QWORD *)((char *)&v19[-2] + v6) = *(_QWORD *)((char *)&v19[-2] + v6);\n if ( a2 > 0 )\n {\n v8 = *a1;\n v19[0] = *a1;\n if ( a2 > 1 )\n {\n v9 = a1[1];\n v10 = v8 + v9;\n v19[1] = v8 + v9;\n if ( a2 > 2 )\n {\n v11 = a1[2];\n v12 = v11 + v8;\n v13 = v11 + v9;\n if ( v12 < v13 )\n v12 = v13;\n if ( v12 < v10 )\n v12 = v10;\n LODWORD(v20) = v12;\n if ( a2 > 3 )\n {\n v14 = v19;\n v15 = a1 + 2;\n do\n {\n v16 = v14[1] + v15[1];\n if ( v16 < v14[2] )\n v16 = v14[2];\n if ( v16 < *v14 + *v15 + v15[1] )\n v16 = *v14 + *v15 + v15[1];\n v14[3] = v16;\n ++v14;\n ++v15;\n }\n while ( v14 != &v19[a2 - 3] );\n }\n }\n }\n }\n return (unsigned int)v19[a2 - 1];\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov rax, rdi\nmov r8d, esi\nmov rdx, fs:28h\nmov [rbp+var_8], rdx\nxor edx, edx\nmovsxd rdx, esi\nlea rdx, ds:0Fh[rdx*4]\nmov rsi, rdx\nand rsi, 0FFFFFFFFFFFFFFF0h\nand rdx, 0FFFFFFFFFFFFF000h\nmov rcx, rsp\nsub rcx, rdx\nloc_11C9:\ncmp rsp, rcx\njz short loc_11E0\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11C9\nloc_11E0:\nmov rdx, rsi\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njz short loc_11F7\nor [rsp+rdx+10h+var_18], 0\nloc_11F7:\nlea r9, [rsp+10h+var_D]\nmov r10, r9\nshr r10, 2\nand r9, 0FFFFFFFFFFFFFFFCh\ntest r8d, r8d\njle short loc_1287\nmov edx, [rax]\nmov ds:dword_0[r10*4], edx\ncmp r8d, 1\njle short loc_1287\nmov ecx, [rax+4]\nlea edi, [rdx+rcx]\nmov dword ptr ds:byte_4[r10*4], edi\ncmp r8d, 2\njle short loc_1287\nmov esi, [rax+8]\nadd edx, esi\nadd ecx, esi\ncmp edx, ecx\ncmovl edx, ecx\ncmp edx, edi\ncmovl edx, edi\nmov dword ptr ds:byte_8[r10*4], edx\ncmp r8d, 3\njle short loc_1287\nmov rcx, r9\nlea rsi, [rax+8]\nlea eax, [r8-3]\nlea r10, [r9+rax*4]\nloc_125E:\nmov edx, [rsi+4]\nmov eax, edx\nadd eax, [rcx+4]\nmov edi, [rcx+8]\ncmp eax, edi\ncmovl eax, edi\nadd edx, [rsi]\nadd edx, [rcx]\ncmp eax, edx\ncmovl eax, edx\nmov [rcx+0Ch], eax\nadd rcx, 4\nadd rsi, 4\ncmp rcx, r10\njnz short loc_125E\nloc_1287:\nsub r8d, 1\nmovsxd r8, r8d\nmov eax, [r9+r8*4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_12A3\nleave\nretn\nloc_12A3:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(int *a1, int a2)\n{\n __int64 v4; // rdx\n __int16 v5; // si\n signed __int64 v6; // rdx\n void *v7; // rsp\n int v8; // edx\n int v9; // ecx\n int v10; // edi\n int v11; // esi\n int v12; // edx\n int v13; // ecx\n _DWORD *v14; // rcx\n _DWORD *v15; // rsi\n int v16; // eax\n _DWORD v19[2]; // [rsp+8h] [rbp-10h] BYREF\n unsigned __int64 v20; // [rsp+10h] [rbp-8h]\n\n v20 = __readfsqword(0x28u);\n v4 = 4LL * a2 + 15;\n v5 = (4 * a2 + 15) & 0xFFF0;\n while ( v19 != (_DWORD *)((char *)v19 - (v4 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v6 = v5 & 0xFFF;\n v7 = alloca(v6);\n if ( (v5 & 0xFFF) != 0 )\n *(_QWORD *)((char *)&v19[-2] + v6) = *(_QWORD *)((char *)&v19[-2] + v6);\n if ( a2 > 0 )\n {\n v8 = *a1;\n v19[0] = *a1;\n if ( a2 > 1 )\n {\n v9 = a1[1];\n v10 = v8 + v9;\n v19[1] = v8 + v9;\n if ( a2 > 2 )\n {\n v11 = a1[2];\n v12 = v11 + v8;\n v13 = v11 + v9;\n if ( v12 < v13 )\n v12 = v13;\n if ( v12 < v10 )\n v12 = v10;\n LODWORD(v20) = v12;\n if ( a2 > 3 )\n {\n v14 = v19;\n v15 = a1 + 2;\n do\n {\n v16 = v14[1] + v15[1];\n if ( v16 < v14[2] )\n v16 = v14[2];\n if ( v16 < *v14 + *v15 + v15[1] )\n v16 = *v14 + *v15 + v15[1];\n v14[3] = v16;\n ++v14;\n ++v15;\n }\n while ( v14 != &v19[a2 - 3] );\n }\n }\n }\n }\n return (unsigned int)v19[a2 - 1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(int *a1, int a2) {\n long long v4;\n short v5;\n signed long long v6;\n void *v7;\n int v8;\n int v9;\n int v10;\n int v11;\n int v12;\n int v13;\n uint32_t *v14;\n uint32_t *v15;\n int v16;\n uint32_t v19[2];\n unsigned long long v20;\n v20 = __readfsqword(40u);\n v4 = 4LL * a2 + 15;\n v5 = (4 * a2 + 15) & 65520;\n while (v19 != (uint32_t *)((char *)v19 - (v4 & 18446744073709547520LL)))\n ;\n v6 = v5 & 4095;\n v7 = alloca(v6);\n if ((v5 & 4095) != 0)\n *(uint64_t *)((char *)&v19[-2] + v6) = *(uint64_t *)((char *)&v19[-2] + v6);\n if (a2 > 0) {\n v8 = *a1;\n v19[0] = *a1;\n if (a2 > 1) {\n v9 = a1[1];\n v10 = v8 + v9;\n v19[1] = v8 + v9;\n if (a2 > 2) {\n v11 = a1[2];\n v12 = v11 + v8;\n v13 = v11 + v9;\n if (v12 < v13) v12 = v13;\n if (v12 < v10) v12 = v10;\n LODWORD(v20) = v12;\n if (a2 > 3) {\n v14 = v19;\n v15 = a1 + 2;\n do {\n v16 = v14[1] + v15[1];\n if (v16 < v14[2]) v16 = v14[2];\n if (v16 < *v14 + *v15 + v15[1]) v16 = *v14 + *v15 + v15[1];\n v14[3] = v16;\n ++v14;\n ++v15;\n } while (v14 != &v19[a2 - 3]);\n }\n }\n }\n }\n return (unsigned int)v19[a2 - 1];\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n long long v4;\n short v5;\n signed long long v6;\n void *v7;\n int v8;\n int v9;\n int v10;\n int v11;\n int v12;\n int v13;\n uint32_t *v14;\n uint32_t *v15;\n int v16;\n uint32_t v19[2];\n unsigned long long v20;\n v20 = __readfsqword(40u);\n v4 = 4LL * a2 + 15;\n v5 = (4 * a2 + 15) & 65520;\n while (v19 != (uint32_t *)((char *)v19 - (v4 & 18446744073709547520LL)))\n ;\n v6 = v5 & 4095;\n v7 = alloca(v6);\n if ((v5 & 4095) != 0)\n *(uint64_t *)((char *)&v19[-2] + v6) = *(uint64_t *)((char *)&v19[-2] + v6);\n if (a2 > 0) {\n v8 = *a1;\n v19[0] = *a1;\n if (a2 > 1) {\n v9 = a1[1];\n v10 = v8 + v9;\n v19[1] = v8 + v9;\n if (a2 > 2) {\n v11 = a1[2];\n v12 = v11 + v8;\n v13 = v11 + v9;\n if (v12 < v13) v12 = v13;\n if (v12 < v10) v12 = v10;\n LODWORD(v20) = v12;\n if (a2 > 3) {\n v14 = v19;\n v15 = a1 + 2;\n do {\n v16 = v14[1] + v15[1];\n if (v16 < v14[2]) v16 = v14[2];\n if (v16 < *v14 + *v15 + v15[1]) v16 = *v14 + *v15 + v15[1];\n v14[3] = v16;\n ++v14;\n ++v15;\n } while (v14 != &v19[a2 - 3]);\n }\n }\n }\n }\n return (unsigned int)v19[a2 - 1];\n}" + }, + { + "index": 661, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int sum[n];\n if (n >= 1) sum[0] = arr[0];\n if (n >= 2) sum[1] = arr[0] + arr[1];\n if (n > 2)\n sum[2] = (sum[1] > (arr[1] + arr[2]) ? sum[1] : (arr[1] + arr[2])) >\n (arr[0] + arr[2])\n ? (sum[1] > (arr[1] + arr[2]) ? sum[1] : (arr[1] + arr[2]))\n : (arr[0] + arr[2]);\n for (int i = 3; i < n; i++) {\n int max1 = sum[i - 1];\n int max2 = sum[i - 2] + arr[i];\n int max3 = arr[i] + arr[i - 1] + sum[i - 3];\n sum[i] =\n (max1 > max2 ? max1 : max2) > max3 ? (max1 > max2 ? max1 : max2) : max3;\n }\n return sum[n - 1];\n}", + "test": "int main() {\n\n assert(func0((int[]){100, 1000, 100, 1000, 1}, 5) == 2101);\n\n assert(func0((int[]){3000, 2000, 1000, 3, 10}, 5) == 5013);\n\n assert(func0((int[]){1, 2, 3, 4, 5, 6, 7, 8}, 8) == 27);\n\n \n\n printf(\"All tests passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovslq %esi,%rax\nmov %rsp,%rcx\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rcx\nand $0xfffffffffffffff0,%rdx\nmov %rcx,%rax\ncmp %rax,%rsp\nje 1346 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 1331 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 1410 \nlea 0x3(%rsp),%r9\nmov %r9,%r8\nand $0xfffffffffffffffc,%r9\nshr $0x2,%r8\ntest %esi,%esi\njle 13aa \nmov (%rdi),%eax\nmov %eax,0x0(,%r8,4)\ncmp $0x1,%esi\nje 13ec \nmov 0x4(%rdi),%edx\nlea (%rax,%rdx,1),%ecx\nmov %ecx,0x4(,%r8,4)\ncmp $0x2,%esi\nje 13ec \nmov 0x8(%rdi),%r10d\nadd %r10d,%eax\ncmp %ecx,%eax\ncmovl %ecx,%eax\nadd %r10d,%edx\ncmp %edx,%eax\ncmovl %edx,%eax\nmov %eax,0x8(,%r8,4)\ncmp $0x3,%esi\njle 13ec \nlea -0x4(%rsi),%eax\nmov %r9,%rcx\nadd $0x8,%rdi\nlea 0x4(%r9,%rax,4),%r10\nxchg %ax,%ax\nmov 0x4(%rdi),%edx\nmov 0x4(%rcx),%eax\nmov 0x8(%rcx),%r8d\nadd %edx,%eax\ncmp %r8d,%eax\ncmovl %r8d,%eax\nadd (%rdi),%edx\nadd (%rcx),%edx\ncmp %edx,%eax\ncmovl %edx,%eax\nadd $0x4,%rcx\nadd $0x4,%rdi\nmov %eax,0x8(%rcx)\ncmp %rcx,%r10\njne 13c0 \nsub $0x1,%esi\nmovslq %esi,%rsi\nmov (%r9,%rsi,4),%eax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\njne 141b \nleaveq\nretq\nnopw 0x0(%rax,%rax,1)\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 1358 \ncallq 1080 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov r10d, esi\nmov rax, rdi\nmov rbp, rsp\npush r12\npush rbx\nsub rsp, 10h\nmov rdx, fs:28h\nmov [rbp+var_18], rdx\nxor edx, edx\nmovsxd rdx, esi\nmov rsi, rsp\nlea rdx, ds:0Fh[rdx*4]\nmov rcx, rdx\nand rdx, 0FFFFFFFFFFFFF000h\nsub rsi, rdx\nand rcx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rsi\njz short loc_131D\nloc_1308:\nsub rsp, 1000h\nor [rsp+1020h+var_28], 0\ncmp rsp, rsi\njnz short loc_1308\nloc_131D:\nand ecx, 0FFFh\nsub rsp, rcx\ntest rcx, rcx\njnz loc_1400\nloc_132F:\nlea rbx, [rsp+1020h+var_101D]\nmov rdi, rbx\nand rbx, 0FFFFFFFFFFFFFFFCh\nshr rdi, 2\ntest r10d, r10d\njle loc_13D8\nmov r12d, [rax]\nmov ds:dword_0[rdi*4], r12d\ncmp r10d, 1\njz short loc_13D8\nmov edx, [rax+4]\nlea r8d, [r12+rdx]\nmov dword ptr ds:byte_4[rdi*4], r8d\ncmp r10d, 2\njz short loc_13D8\nmov esi, [rax+8]\nlea ecx, [r12+rsi]\ncmp ecx, r8d\ncmovl ecx, r8d\nadd edx, esi\ncmp ecx, edx\ncmovl ecx, edx\nmov dword ptr ds:byte_8[rdi*4], ecx\ncmp r10d, 3\njz short loc_13D8\nlea edx, [r10-4]\nlea rdi, [rax+0Ch]\nlea r9, [rbx+0Ch]\nlea r11, [rax+rdx*4+10h]\njmp short loc_13AA\nloc_13A8:\nmov ecx, eax\nloc_13AA:\nmov edx, esi\nmov esi, [rdi]\nlea eax, [rsi+r8]\ncmp eax, ecx\ncmovl eax, ecx\nadd edx, esi\nadd edx, r12d\nmov r12d, r8d\nmov r8d, ecx\ncmp eax, edx\ncmovl eax, edx\nadd rdi, 4\nadd r9, 4\nmov [r9-4], eax\ncmp rdi, r11\njnz short loc_13A8\nloc_13D8:\nsub r10d, 1\nmovsxd r10, r10d\nmov eax, [rbx+r10*4]\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njnz short loc_140B\nlea rsp, [rbp-10h]\npop rbx\npop r12\npop rbp\nretn\nloc_1400:\nor [rsp+rcx+1020h+var_1028], 0\njmp loc_132F\nloc_140B:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n __int64 v4; // rcx\n _DWORD *v5; // rsi\n __int16 v6; // cx\n signed __int64 v7; // rcx\n void *v8; // rsp\n int v9; // r12d\n int v10; // edx\n int v11; // r8d\n int v12; // esi\n int v13; // ecx\n int v14; // edx\n int *v15; // rdi\n int *v16; // r9\n __int64 v17; // r11\n int v18; // edx\n int v19; // eax\n int v20; // edx\n _DWORD v23[3]; // [rsp+8h] [rbp-1020h] BYREF\n int v24; // [rsp+14h] [rbp-1014h] BYREF\n _QWORD v25[4]; // [rsp+1008h] [rbp-20h] BYREF\n\n v25[1] = __readfsqword(0x28u);\n v4 = 4LL * a2 + 15;\n v5 = (_DWORD *)((char *)v25 - (v4 & 0xFFFFFFFFFFFFF000LL));\n v6 = v4 & 0xFFF0;\n if ( v25 != (_QWORD *)v5 )\n {\n while ( v23 != v5 )\n ;\n }\n v7 = v6 & 0xFFF;\n v8 = alloca(v7);\n if ( v7 )\n *(_QWORD *)((char *)&v23[-2] + v7) = *(_QWORD *)((char *)&v23[-2] + v7);\n if ( a2 > 0 )\n {\n v9 = *a1;\n v23[0] = *a1;\n if ( a2 != 1 )\n {\n v10 = a1[1];\n v11 = v9 + v10;\n v23[1] = v9 + v10;\n if ( a2 != 2 )\n {\n v12 = a1[2];\n v13 = v9 + v12;\n if ( v9 + v12 < v11 )\n v13 = v9 + v10;\n v14 = v12 + v10;\n if ( v13 < v14 )\n v13 = v14;\n v23[2] = v13;\n if ( a2 != 3 )\n {\n v15 = a1 + 3;\n v16 = &v24;\n v17 = (__int64)&a1[a2 - 4 + 4];\n while ( 1 )\n {\n v18 = v12;\n v12 = *v15;\n v19 = *v15 + v11;\n if ( v19 < v13 )\n v19 = v13;\n v20 = v9 + v12 + v18;\n v9 = v11;\n v11 = v13;\n if ( v19 < v20 )\n v19 = v20;\n ++v15;\n *v16++ = v19;\n if ( v15 == (int *)v17 )\n break;\n v13 = v19;\n }\n }\n }\n }\n }\n return (unsigned int)v23[a2 - 1];\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\npush rbp\nmov r10d, esi\nmov rax, rdi\nmov rbp, rsp\npush r12\npush rbx\nsub rsp, 10h\nmov rdx, fs:28h\nmov [rbp+var_18], rdx\nxor edx, edx\nmovsxd rdx, esi\nmov rsi, rsp\nlea rdx, ds:0Fh[rdx*4]\nmov rcx, rdx\nand rdx, 0FFFFFFFFFFFFF000h\nsub rsi, rdx\nand rcx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rsi\njz short loc_131D\nloc_1308:\nsub rsp, 1000h\nor [rsp+1020h+var_28], 0\ncmp rsp, rsi\njnz short loc_1308\nloc_131D:\nand ecx, 0FFFh\nsub rsp, rcx\ntest rcx, rcx\njnz loc_1400\nloc_132F:\nlea rbx, [rsp+1020h+var_101D]\nmov rdi, rbx\nand rbx, 0FFFFFFFFFFFFFFFCh\nshr rdi, 2\ntest r10d, r10d\njle loc_13D8\nmov r12d, [rax]\nmov ds:dword_0[rdi*4], r12d\ncmp r10d, 1\njz short loc_13D8\nmov edx, [rax+4]\nlea r8d, [r12+rdx]\nmov dword ptr ds:byte_4[rdi*4], r8d\ncmp r10d, 2\njz short loc_13D8\nmov esi, [rax+8]\nlea ecx, [r12+rsi]\ncmp ecx, r8d\ncmovl ecx, r8d\nadd edx, esi\ncmp ecx, edx\ncmovl ecx, edx\nmov dword ptr ds:byte_8[rdi*4], ecx\ncmp r10d, 3\njz short loc_13D8\nlea edx, [r10-4]\nlea rdi, [rax+0Ch]\nlea r9, [rbx+0Ch]\nlea r11, [rax+rdx*4+10h]\njmp short loc_13AA\nloc_13A8:\nmov ecx, eax\nloc_13AA:\nmov edx, esi\nmov esi, [rdi]\nlea eax, [rsi+r8]\ncmp eax, ecx\ncmovl eax, ecx\nadd edx, esi\nadd edx, r12d\nmov r12d, r8d\nmov r8d, ecx\ncmp eax, edx\ncmovl eax, edx\nadd rdi, 4\nadd r9, 4\nmov [r9-4], eax\ncmp rdi, r11\njnz short loc_13A8\nloc_13D8:\nsub r10d, 1\nmovsxd r10, r10d\nmov eax, [rbx+r10*4]\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njnz short loc_140B\nlea rsp, [rbp-10h]\npop rbx\npop r12\npop rbp\nretn\nloc_1400:\nor [rsp+rcx+1020h+var_1028], 0\njmp loc_132F\nloc_140B:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12C0(int *a1, int a2)\n{\n __int64 v4; // rcx\n _DWORD *v5; // rsi\n __int16 v6; // cx\n signed __int64 v7; // rcx\n void *v8; // rsp\n int v9; // r12d\n int v10; // edx\n int v11; // r8d\n int v12; // esi\n int v13; // ecx\n int v14; // edx\n int *v15; // rdi\n int *v16; // r9\n __int64 v17; // r11\n int v18; // edx\n int v19; // eax\n int v20; // edx\n _DWORD v23[3]; // [rsp+8h] [rbp-1020h] BYREF\n int v24; // [rsp+14h] [rbp-1014h] BYREF\n _QWORD v25[4]; // [rsp+1008h] [rbp-20h] BYREF\n\n v25[1] = __readfsqword(0x28u);\n v4 = 4LL * a2 + 15;\n v5 = (_DWORD *)((char *)v25 - (v4 & 0xFFFFFFFFFFFFF000LL));\n v6 = v4 & 0xFFF0;\n if ( v25 != (_QWORD *)v5 )\n {\n while ( v23 != v5 )\n ;\n }\n v7 = v6 & 0xFFF;\n v8 = alloca(v7);\n if ( v7 )\n *(_QWORD *)((char *)&v23[-2] + v7) = *(_QWORD *)((char *)&v23[-2] + v7);\n if ( a2 > 0 )\n {\n v9 = *a1;\n v23[0] = *a1;\n if ( a2 != 1 )\n {\n v10 = a1[1];\n v11 = v9 + v10;\n v23[1] = v9 + v10;\n if ( a2 != 2 )\n {\n v12 = a1[2];\n v13 = v9 + v12;\n if ( v9 + v12 < v11 )\n v13 = v9 + v10;\n v14 = v12 + v10;\n if ( v13 < v14 )\n v13 = v14;\n v23[2] = v13;\n if ( a2 != 3 )\n {\n v15 = a1 + 3;\n v16 = &v24;\n v17 = (__int64)&a1[a2 - 4 + 4];\n while ( 1 )\n {\n v18 = v12;\n v12 = *v15;\n v19 = *v15 + v11;\n if ( v19 < v13 )\n v19 = v13;\n v20 = v9 + v12 + v18;\n v9 = v11;\n v11 = v13;\n if ( v19 < v20 )\n v19 = v20;\n ++v15;\n *v16++ = v19;\n if ( v15 == (int *)v17 )\n break;\n v13 = v19;\n }\n }\n }\n }\n }\n return (unsigned int)v23[a2 - 1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12C0(int *a1, int a2) {\n long long v4;\n uint32_t *v5;\n short v6;\n signed long long v7;\n void *v8;\n int v9;\n int v10;\n int v11;\n int v12;\n int v13;\n int v14;\n int *v15;\n int *v16;\n long long v17;\n int v18;\n int v19;\n int v20;\n uint32_t v23[3];\n int v24;\n uint64_t v25[4];\n v25[1] = __readfsqword(40u);\n v4 = 4LL * a2 + 15;\n v5 = (uint32_t *)((char *)v25 - (v4 & 18446744073709547520LL));\n v6 = v4 & 65520;\n if (v25 != (uint64_t *)v5) {\n while (v23 != v5)\n ;\n }\n v7 = v6 & 4095;\n v8 = alloca(v7);\n if (v7)\n *(uint64_t *)((char *)&v23[-2] + v7) = *(uint64_t *)((char *)&v23[-2] + v7);\n if (a2 > 0) {\n v9 = *a1;\n v23[0] = *a1;\n if (a2 != 1) {\n v10 = a1[1];\n v11 = v9 + v10;\n v23[1] = v9 + v10;\n if (a2 != 2) {\n v12 = a1[2];\n v13 = v9 + v12;\n if (v9 + v12 < v11) v13 = v9 + v10;\n v14 = v12 + v10;\n if (v13 < v14) v13 = v14;\n v23[2] = v13;\n if (a2 != 3) {\n v15 = a1 + 3;\n v16 = &v24;\n v17 = (long long)&a1[a2 - 4 + 4];\n while (1) {\n v18 = v12;\n v12 = *v15;\n v19 = *v15 + v11;\n if (v19 < v13) v19 = v13;\n v20 = v9 + v12 + v18;\n v9 = v11;\n v11 = v13;\n if (v19 < v20) v19 = v20;\n ++v15;\n *v16++ = v19;\n if (v15 == (int *)v17) break;\n v13 = v19;\n }\n }\n }\n }\n }\n return (unsigned int)v23[a2 - 1];\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n long long v4;\n uint32_t *v5;\n short v6;\n signed long long v7;\n void *v8;\n int v9;\n int v10;\n int v11;\n int v12;\n int v13;\n int v14;\n int *v15;\n int *v16;\n long long v17;\n int v18;\n int v19;\n int v20;\n uint32_t v23[3];\n int v24;\n uint64_t v25[4];\n v25[1] = __readfsqword(40u);\n v4 = 4LL * a2 + 15;\n v5 = (uint32_t *)((char *)v25 - (v4 & 18446744073709547520LL));\n v6 = v4 & 65520;\n if (v25 != (uint64_t *)v5) {\n while (v23 != v5)\n ;\n }\n v7 = v6 & 4095;\n v8 = alloca(v7);\n if (v7)\n *(uint64_t *)((char *)&v23[-2] + v7) = *(uint64_t *)((char *)&v23[-2] + v7);\n if (a2 > 0) {\n v9 = *a1;\n v23[0] = *a1;\n if (a2 != 1) {\n v10 = a1[1];\n v11 = v9 + v10;\n v23[1] = v9 + v10;\n if (a2 != 2) {\n v12 = a1[2];\n v13 = v9 + v12;\n if (v9 + v12 < v11) v13 = v9 + v10;\n v14 = v12 + v10;\n if (v13 < v14) v13 = v14;\n v23[2] = v13;\n if (a2 != 3) {\n v15 = a1 + 3;\n v16 = &v24;\n v17 = (long long)&a1[a2 - 4 + 4];\n while (1) {\n v18 = v12;\n v12 = *v15;\n v19 = *v15 + v11;\n if (v19 < v13) v19 = v13;\n v20 = v9 + v12 + v18;\n v9 = v11;\n v11 = v13;\n if (v19 < v20) v19 = v20;\n ++v15;\n *v16++ = v19;\n if (v15 == (int *)v17) break;\n v13 = v19;\n }\n }\n }\n }\n }\n return (unsigned int)v23[a2 - 1];\n}" + }, + { + "index": 661, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int sum[n];\n if (n >= 1) sum[0] = arr[0];\n if (n >= 2) sum[1] = arr[0] + arr[1];\n if (n > 2)\n sum[2] = (sum[1] > (arr[1] + arr[2]) ? sum[1] : (arr[1] + arr[2])) >\n (arr[0] + arr[2])\n ? (sum[1] > (arr[1] + arr[2]) ? sum[1] : (arr[1] + arr[2]))\n : (arr[0] + arr[2]);\n for (int i = 3; i < n; i++) {\n int max1 = sum[i - 1];\n int max2 = sum[i - 2] + arr[i];\n int max3 = arr[i] + arr[i - 1] + sum[i - 3];\n sum[i] =\n (max1 > max2 ? max1 : max2) > max3 ? (max1 > max2 ? max1 : max2) : max3;\n }\n return sum[n - 1];\n}", + "test": "int main() {\n\n assert(func0((int[]){100, 1000, 100, 1000, 1}, 5) == 2101);\n\n assert(func0((int[]){3000, 2000, 1000, 3, 10}, 5) == 5013);\n\n assert(func0((int[]){1, 2, 3, 4, 5, 6, 7, 8}, 8) == 27);\n\n \n\n printf(\"All tests passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x28(%rbp)\nxor %eax,%eax\nmovslq %esi,%rax\nmov %rsp,%rbx\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rbx\nand $0xfffffffffffffff0,%rdx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 131d \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 1308 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 1500 \nlea 0x3(%rsp),%r8\nmov %r8,%rdx\nand $0xfffffffffffffffc,%r8\nshr $0x2,%rdx\ntest %esi,%esi\njle 138a \nmov (%rdi),%eax\nmov %eax,0x0(,%rdx,4)\ncmp $0x1,%esi\nje 14d8 \nmov 0x4(%rdi),%ecx\nlea (%rax,%rcx,1),%r9d\nmov %r9d,0x4(,%rdx,4)\ncmp $0x2,%esi\nje 14d8 \nmov 0x8(%rdi),%r10d\nadd %r10d,%eax\ncmp %r9d,%eax\ncmovl %r9d,%eax\nadd %r10d,%ecx\ncmp %ecx,%eax\ncmovl %ecx,%eax\nmov %eax,0x8(,%rdx,4)\ncmp $0x3,%esi\njle 14d8 \nlea -0x5(%rsi),%r13d\ncmp $0x9,%esi\njle 150b \nmov 0x0(,%rdx,4),%r10d\nmov 0x8(%rdi),%r11d\nlea 0xc(%rdi),%r12\nlea 0xc(%r8),%rbx\nmov 0x4(,%rdx,4),%r9d\nmov 0x8(,%rdx,4),%edx\nmov $0x3,%eax\nmov (%r12),%r14d\nlea (%r14,%r9,1),%ecx\ncmp %edx,%ecx\ncmovl %edx,%ecx\nadd %r14d,%r11d\nadd %r11d,%r10d\nmov 0x8(%r12),%r11d\ncmp %r10d,%ecx\ncmovge %ecx,%r10d\nmov 0x4(%r12),%ecx\nadd %ecx,%r14d\nmov %r10d,(%rbx)\nadd %r14d,%r9d\nlea (%rdx,%rcx,1),%r14d\ncmp %r14d,%r9d\ncmovl %r14d,%r9d\nlea (%r10,%r11,1),%r14d\ncmp %r10d,%r9d\ncmovl %r10d,%r9d\nadd %r11d,%ecx\nadd %ecx,%edx\nmov 0x10(%r12),%ecx\ncmp %r14d,%edx\nmov %r9d,0x4(%rbx)\ncmovl %r14d,%edx\ncmp %r9d,%edx\ncmovl %r9d,%edx\nmov %edx,%r14d\nmov %edx,0x8(%rbx)\nmov 0xc(%r12),%edx\nadd %edx,%r11d\nadd %r11d,%r10d\nlea (%r9,%rdx,1),%r11d\ncmp %r11d,%r10d\ncmovl %r11d,%r10d\nmov 0x14(%r12),%r11d\ncmp %r14d,%r10d\ncmovl %r14d,%r10d\nadd %ecx,%edx\nadd %edx,%r9d\nlea (%r14,%rcx,1),%edx\ncmp %edx,%r9d\nmov %r10d,0xc(%rbx)\ncmovl %edx,%r9d\nlea (%rcx,%r11,1),%edx\nlea (%r10,%r11,1),%ecx\ncmp %r10d,%r9d\ncmovl %r10d,%r9d\nadd %r14d,%edx\ncmp %ecx,%edx\ncmovl %ecx,%edx\nmov %eax,%ecx\nmov %r9d,0x10(%rbx)\ncmp %r9d,%edx\ncmovl %r9d,%edx\nadd $0x7,%ecx\nadd $0x6,%eax\nadd $0x18,%r12\nadd $0x18,%rbx\nmov %edx,-0x4(%rbx)\ncmp %ecx,%r13d\njg 13c8 \ncltq\nnopl 0x0(%rax,%rax,1)\nmov (%rdi,%rax,4),%ecx\nmov -0x8(%r8,%rax,4),%edx\nmov -0x4(%r8,%rax,4),%r9d\nadd %ecx,%edx\ncmp %r9d,%edx\ncmovl %r9d,%edx\nadd -0x4(%rdi,%rax,4),%ecx\nadd -0xc(%r8,%rax,4),%ecx\ncmp %ecx,%edx\ncmovl %ecx,%edx\nmov %edx,(%r8,%rax,4)\nadd $0x1,%rax\ncmp %eax,%esi\njg 14a8 \nsub $0x1,%esi\nmov -0x28(%rbp),%rbx\nxor %fs:0x28,%rbx\nmovslq %esi,%rsi\nmov (%r8,%rsi,4),%eax\njne 1512 \nlea -0x20(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %rbp\nretq\nxchg %ax,%ax\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 132f \nmov $0x3,%eax\njmp 14a1 \ncallq 1080 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov r9, rdi\nmov r8d, esi\nmov rbp, rsp\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nmovsxd rax, esi\nmov rcx, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_1320\nloc_130B:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rcx\njnz short loc_130B\nloc_1320:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_14E8\nloc_1332:\nlea rsi, [rsp+1030h+var_102D]\nmov r11, rsi\nand rsi, 0FFFFFFFFFFFFFFFCh\nshr r11, 2\ntest r8d, r8d\njle loc_14BD\nmov ecx, [r9]\nmov ds:dword_0[r11*4], ecx\ncmp r8d, 1\njz loc_14BD\nmov eax, [r9+4]\nlea edi, [rcx+rax]\nmov dword ptr ds:byte_4[r11*4], edi\ncmp r8d, 2\njz loc_14BD\nmov r10d, [r9+8]\nlea edx, [rcx+r10]\ncmp edx, edi\ncmovl edx, edi\nadd eax, r10d\ncmp edx, eax\ncmovl edx, eax\nmov dword ptr ds:byte_8[r11*4], edx\ncmp r8d, 3\njz loc_14BD\nlea r12d, [r8-5]\ncmp r8d, 9\njle loc_14F3\nlea rbx, [r9+0Ch]\nlea r11, [rsi+0Ch]\nmov eax, 3\nloc_13BB:\nmov r13d, [rbx]\nlea r14d, [r13+rdi+0]\ncmp r14d, edx\ncmovl r14d, edx\nadd r10d, r13d\nadd r10d, ecx\ncmp r14d, r10d\ncmovl r14d, r10d\nmov r10d, [rbx+4]\nadd r13d, r10d\nlea ecx, [rdx+r10]\nmov [r11], r14d\nadd edi, r13d\ncmp ecx, r14d\ncmovl ecx, r14d\ncmp edi, ecx\ncmovl edi, ecx\nmov ecx, [rbx+8]\nlea r13d, [r10+rcx]\nmov r10d, [rbx+0Ch]\nmov [r11+4], edi\nadd r13d, edx\nlea edx, [r14+rcx]\ncmp r13d, edx\ncmovl r13d, edx\nlea edx, [rdi+r10]\ncmp r13d, edi\ncmovl r13d, edi\nadd ecx, r10d\nadd ecx, r14d\ncmp ecx, edx\nmov [r11+8], r13d\ncmovl ecx, edx\nmov edx, [rbx+10h]\ncmp ecx, r13d\ncmovl ecx, r13d\nadd r10d, edx\nadd edi, r10d\nlea r10d, [r13+rdx+0]\ncmp edi, r10d\nmov [r11+0Ch], ecx\ncmovl edi, r10d\nmov r10d, [rbx+14h]\ncmp edi, ecx\ncmovl edi, ecx\nadd edx, r10d\nadd edx, r13d\nlea r13d, [rcx+r10]\ncmp edx, r13d\nmov [r11+10h], edi\ncmovl edx, r13d\nmov r13d, eax\ncmp edx, edi\ncmovl edx, edi\nadd r13d, 7\nadd eax, 6\nadd rbx, 18h\nadd r11, 18h\nmov [r11-4], edx\ncmp r12d, r13d\njg loc_13BB\nloc_148D:\ncdqe\nnop\nloc_1490:\nmov ecx, [r9+rax*4]\nmov edx, [rsi+rax*4-8]\nmov edi, [rsi+rax*4-4]\nadd edx, ecx\ncmp edx, edi\ncmovl edx, edi\nadd ecx, [r9+rax*4-4]\nadd ecx, [rsi+rax*4-0Ch]\ncmp edx, ecx\ncmovl edx, ecx\nmov [rsi+rax*4], edx\nadd rax, 1\ncmp r8d, eax\njg short loc_1490\nloc_14BD:\nsub r8d, 1\nmovsxd r8, r8d\nmov eax, [rsi+r8*4]\nmov rdx, [rbp+var_28]\nsub rdx, fs:28h\njnz short loc_14FA\nlea rsp, [rbp-20h]\npop rbx\npop r12\npop r13\npop r14\npop rbp\nretn\nloc_14E8:\nor [rsp+rdx+1030h+var_1038], 0\njmp loc_1332\nloc_14F3:\nmov eax, 3\njmp short loc_148D\nloc_14FA:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n __int64 v3; // rdx\n _DWORD *v4; // rcx\n __int16 v5; // dx\n signed __int64 v6; // rdx\n void *v7; // rsp\n int v8; // ecx\n int v9; // eax\n int v10; // edi\n int v11; // r10d\n int v12; // edx\n int v13; // eax\n int *v14; // rbx\n int *v15; // r11\n __int64 v16; // rax\n int v17; // r13d\n int v18; // r14d\n int v19; // r10d\n int v20; // r10d\n int v21; // ecx\n int v22; // edi\n int v23; // ecx\n int v24; // r13d\n int v25; // r10d\n int v26; // r13d\n int v27; // edx\n int v28; // r13d\n int v29; // ecx\n int v30; // edx\n int v31; // ecx\n _DWORD v34[3]; // [rsp+8h] [rbp-1030h] BYREF\n int v35; // [rsp+14h] [rbp-1024h] BYREF\n _QWORD v36[6]; // [rsp+1008h] [rbp-30h] BYREF\n\n v36[1] = __readfsqword(0x28u);\n v3 = 4LL * a2 + 15;\n v4 = (_DWORD *)((char *)v36 - (v3 & 0xFFFFFFFFFFFFF000LL));\n v5 = v3 & 0xFFF0;\n if ( v36 != (_QWORD *)v4 )\n {\n while ( v34 != v4 )\n ;\n }\n v6 = v5 & 0xFFF;\n v7 = alloca(v6);\n if ( v6 )\n *(_QWORD *)((char *)&v34[-2] + v6) = *(_QWORD *)((char *)&v34[-2] + v6);\n if ( a2 > 0 )\n {\n v8 = *a1;\n v34[0] = *a1;\n if ( a2 != 1 )\n {\n v9 = a1[1];\n v10 = v8 + v9;\n v34[1] = v8 + v9;\n if ( a2 != 2 )\n {\n v11 = a1[2];\n v12 = v8 + v11;\n if ( v8 + v11 < v10 )\n v12 = v8 + v9;\n v13 = v11 + v9;\n if ( v12 < v13 )\n v12 = v13;\n v34[2] = v12;\n if ( a2 != 3 )\n {\n if ( a2 <= 9 )\n {\n LODWORD(v16) = 3;\n }\n else\n {\n v14 = a1 + 3;\n v15 = &v35;\n LODWORD(v16) = 3;\n do\n {\n v17 = *v14;\n v18 = *v14 + v10;\n if ( v18 < v12 )\n v18 = v12;\n v19 = v8 + v17 + v11;\n if ( v18 < v19 )\n v18 = v19;\n v20 = v14[1];\n v21 = v12 + v20;\n *v15 = v18;\n v22 = v20 + v17 + v10;\n if ( v12 + v20 < v18 )\n v21 = v18;\n if ( v22 < v21 )\n v22 = v21;\n v23 = v14[2];\n v24 = v20 + v23;\n v25 = v14[3];\n v15[1] = v22;\n v26 = v12 + v24;\n if ( v26 < v18 + v23 )\n v26 = v18 + v23;\n if ( v26 < v22 )\n v26 = v22;\n v8 = v18 + v25 + v23;\n v15[2] = v26;\n if ( v8 < v22 + v25 )\n v8 = v22 + v25;\n v27 = v14[4];\n if ( v8 < v26 )\n v8 = v26;\n v10 = v27 + v25 + v22;\n v15[3] = v8;\n if ( v10 < v26 + v27 )\n v10 = v26 + v27;\n v11 = v14[5];\n if ( v10 < v8 )\n v10 = v8;\n v12 = v26 + v11 + v27;\n v15[4] = v10;\n if ( v12 < v8 + v11 )\n v12 = v8 + v11;\n v28 = v16;\n if ( v12 < v10 )\n v12 = v10;\n LODWORD(v16) = v16 + 6;\n v14 += 6;\n v15 += 6;\n *(v15 - 1) = v12;\n }\n while ( a2 - 5 > v28 + 7 );\n }\n v16 = (int)v16;\n do\n {\n v29 = a1[v16];\n v30 = v29 + v34[v16 - 2];\n if ( v30 < v34[v16 - 1] )\n v30 = v34[v16 - 1];\n v31 = v34[v16 - 3] + a1[v16 - 1] + v29;\n if ( v30 < v31 )\n v30 = v31;\n v34[v16++] = v30;\n }\n while ( a2 > (int)v16 );\n }\n }\n }\n }\n return (unsigned int)v34[a2 - 1];\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\npush rbp\nmov r9, rdi\nmov r8d, esi\nmov rbp, rsp\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nmovsxd rax, esi\nmov rcx, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_1320\nloc_130B:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rcx\njnz short loc_130B\nloc_1320:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_14E8\nloc_1332:\nlea rsi, [rsp+1030h+var_102D]\nmov r11, rsi\nand rsi, 0FFFFFFFFFFFFFFFCh\nshr r11, 2\ntest r8d, r8d\njle loc_14BD\nmov ecx, [r9]\nmov ds:dword_0[r11*4], ecx\ncmp r8d, 1\njz loc_14BD\nmov eax, [r9+4]\nlea edi, [rcx+rax]\nmov dword ptr ds:byte_4[r11*4], edi\ncmp r8d, 2\njz loc_14BD\nmov r10d, [r9+8]\nlea edx, [rcx+r10]\ncmp edx, edi\ncmovl edx, edi\nadd eax, r10d\ncmp edx, eax\ncmovl edx, eax\nmov dword ptr ds:byte_8[r11*4], edx\ncmp r8d, 3\njz loc_14BD\nlea r12d, [r8-5]\ncmp r8d, 9\njle loc_14F3\nlea rbx, [r9+0Ch]\nlea r11, [rsi+0Ch]\nmov eax, 3\nloc_13BB:\nmov r13d, [rbx]\nlea r14d, [r13+rdi+0]\ncmp r14d, edx\ncmovl r14d, edx\nadd r10d, r13d\nadd r10d, ecx\ncmp r14d, r10d\ncmovl r14d, r10d\nmov r10d, [rbx+4]\nadd r13d, r10d\nlea ecx, [rdx+r10]\nmov [r11], r14d\nadd edi, r13d\ncmp ecx, r14d\ncmovl ecx, r14d\ncmp edi, ecx\ncmovl edi, ecx\nmov ecx, [rbx+8]\nlea r13d, [r10+rcx]\nmov r10d, [rbx+0Ch]\nmov [r11+4], edi\nadd r13d, edx\nlea edx, [r14+rcx]\ncmp r13d, edx\ncmovl r13d, edx\nlea edx, [rdi+r10]\ncmp r13d, edi\ncmovl r13d, edi\nadd ecx, r10d\nadd ecx, r14d\ncmp ecx, edx\nmov [r11+8], r13d\ncmovl ecx, edx\nmov edx, [rbx+10h]\ncmp ecx, r13d\ncmovl ecx, r13d\nadd r10d, edx\nadd edi, r10d\nlea r10d, [r13+rdx+0]\ncmp edi, r10d\nmov [r11+0Ch], ecx\ncmovl edi, r10d\nmov r10d, [rbx+14h]\ncmp edi, ecx\ncmovl edi, ecx\nadd edx, r10d\nadd edx, r13d\nlea r13d, [rcx+r10]\ncmp edx, r13d\nmov [r11+10h], edi\ncmovl edx, r13d\nmov r13d, eax\ncmp edx, edi\ncmovl edx, edi\nadd r13d, 7\nadd eax, 6\nadd rbx, 18h\nadd r11, 18h\nmov [r11-4], edx\ncmp r12d, r13d\njg loc_13BB\nloc_148D:\ncdqe\nnop\nloc_1490:\nmov ecx, [r9+rax*4]\nmov edx, [rsi+rax*4-8]\nmov edi, [rsi+rax*4-4]\nadd edx, ecx\ncmp edx, edi\ncmovl edx, edi\nadd ecx, [r9+rax*4-4]\nadd ecx, [rsi+rax*4-0Ch]\ncmp edx, ecx\ncmovl edx, ecx\nmov [rsi+rax*4], edx\nadd rax, 1\ncmp r8d, eax\njg short loc_1490\nloc_14BD:\nsub r8d, 1\nmovsxd r8, r8d\nmov eax, [rsi+r8*4]\nmov rdx, [rbp+var_28]\nsub rdx, fs:28h\njnz short loc_14FA\nlea rsp, [rbp-20h]\npop rbx\npop r12\npop r13\npop r14\npop rbp\nretn\nloc_14E8:\nor [rsp+rdx+1030h+var_1038], 0\njmp loc_1332\nloc_14F3:\nmov eax, 3\njmp short loc_148D\nloc_14FA:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12C0(int *a1, int a2)\n{\n __int64 v3; // rdx\n _DWORD *v4; // rcx\n __int16 v5; // dx\n signed __int64 v6; // rdx\n void *v7; // rsp\n int v8; // ecx\n int v9; // eax\n int v10; // edi\n int v11; // r10d\n int v12; // edx\n int v13; // eax\n int *v14; // rbx\n int *v15; // r11\n __int64 v16; // rax\n int v17; // r13d\n int v18; // r14d\n int v19; // r10d\n int v20; // r10d\n int v21; // ecx\n int v22; // edi\n int v23; // ecx\n int v24; // r13d\n int v25; // r10d\n int v26; // r13d\n int v27; // edx\n int v28; // r13d\n int v29; // ecx\n int v30; // edx\n int v31; // ecx\n _DWORD v34[3]; // [rsp+8h] [rbp-1030h] BYREF\n int v35; // [rsp+14h] [rbp-1024h] BYREF\n _QWORD v36[6]; // [rsp+1008h] [rbp-30h] BYREF\n\n v36[1] = __readfsqword(0x28u);\n v3 = 4LL * a2 + 15;\n v4 = (_DWORD *)((char *)v36 - (v3 & 0xFFFFFFFFFFFFF000LL));\n v5 = v3 & 0xFFF0;\n if ( v36 != (_QWORD *)v4 )\n {\n while ( v34 != v4 )\n ;\n }\n v6 = v5 & 0xFFF;\n v7 = alloca(v6);\n if ( v6 )\n *(_QWORD *)((char *)&v34[-2] + v6) = *(_QWORD *)((char *)&v34[-2] + v6);\n if ( a2 > 0 )\n {\n v8 = *a1;\n v34[0] = *a1;\n if ( a2 != 1 )\n {\n v9 = a1[1];\n v10 = v8 + v9;\n v34[1] = v8 + v9;\n if ( a2 != 2 )\n {\n v11 = a1[2];\n v12 = v8 + v11;\n if ( v8 + v11 < v10 )\n v12 = v8 + v9;\n v13 = v11 + v9;\n if ( v12 < v13 )\n v12 = v13;\n v34[2] = v12;\n if ( a2 != 3 )\n {\n if ( a2 <= 9 )\n {\n LODWORD(v16) = 3;\n }\n else\n {\n v14 = a1 + 3;\n v15 = &v35;\n LODWORD(v16) = 3;\n do\n {\n v17 = *v14;\n v18 = *v14 + v10;\n if ( v18 < v12 )\n v18 = v12;\n v19 = v8 + v17 + v11;\n if ( v18 < v19 )\n v18 = v19;\n v20 = v14[1];\n v21 = v12 + v20;\n *v15 = v18;\n v22 = v20 + v17 + v10;\n if ( v12 + v20 < v18 )\n v21 = v18;\n if ( v22 < v21 )\n v22 = v21;\n v23 = v14[2];\n v24 = v20 + v23;\n v25 = v14[3];\n v15[1] = v22;\n v26 = v12 + v24;\n if ( v26 < v18 + v23 )\n v26 = v18 + v23;\n if ( v26 < v22 )\n v26 = v22;\n v8 = v18 + v25 + v23;\n v15[2] = v26;\n if ( v8 < v22 + v25 )\n v8 = v22 + v25;\n v27 = v14[4];\n if ( v8 < v26 )\n v8 = v26;\n v10 = v27 + v25 + v22;\n v15[3] = v8;\n if ( v10 < v26 + v27 )\n v10 = v26 + v27;\n v11 = v14[5];\n if ( v10 < v8 )\n v10 = v8;\n v12 = v26 + v11 + v27;\n v15[4] = v10;\n if ( v12 < v8 + v11 )\n v12 = v8 + v11;\n v28 = v16;\n if ( v12 < v10 )\n v12 = v10;\n LODWORD(v16) = v16 + 6;\n v14 += 6;\n v15 += 6;\n *(v15 - 1) = v12;\n }\n while ( a2 - 5 > v28 + 7 );\n }\n v16 = (int)v16;\n do\n {\n v29 = a1[v16];\n v30 = v29 + v34[v16 - 2];\n if ( v30 < v34[v16 - 1] )\n v30 = v34[v16 - 1];\n v31 = v34[v16 - 3] + a1[v16 - 1] + v29;\n if ( v30 < v31 )\n v30 = v31;\n v34[v16++] = v30;\n }\n while ( a2 > (int)v16 );\n }\n }\n }\n }\n return (unsigned int)v34[a2 - 1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12C0(int *a1, int a2) {\n long long v3;\n uint32_t *v4;\n short v5;\n signed long long v6;\n void *v7;\n int v8;\n int v9;\n int v10;\n int v11;\n int v12;\n int v13;\n int *v14;\n int *v15;\n long long v16;\n int v17;\n int v18;\n int v19;\n int v20;\n int v21;\n int v22;\n int v23;\n int v24;\n int v25;\n int v26;\n int v27;\n int v28;\n int v29;\n int v30;\n int v31;\n uint32_t v34[3];\n int v35;\n uint64_t v36[6];\n v36[1] = __readfsqword(40u);\n v3 = 4LL * a2 + 15;\n v4 = (uint32_t *)((char *)v36 - (v3 & 18446744073709547520LL));\n v5 = v3 & 65520;\n if (v36 != (uint64_t *)v4) {\n while (v34 != v4)\n ;\n }\n v6 = v5 & 4095;\n v7 = alloca(v6);\n if (v6)\n *(uint64_t *)((char *)&v34[-2] + v6) = *(uint64_t *)((char *)&v34[-2] + v6);\n if (a2 > 0) {\n v8 = *a1;\n v34[0] = *a1;\n if (a2 != 1) {\n v9 = a1[1];\n v10 = v8 + v9;\n v34[1] = v8 + v9;\n if (a2 != 2) {\n v11 = a1[2];\n v12 = v8 + v11;\n if (v8 + v11 < v10) v12 = v8 + v9;\n v13 = v11 + v9;\n if (v12 < v13) v12 = v13;\n v34[2] = v12;\n if (a2 != 3) {\n if (a2 <= 9) {\n LODWORD(v16) = 3;\n } else {\n v14 = a1 + 3;\n v15 = &v35;\n LODWORD(v16) = 3;\n do {\n v17 = *v14;\n v18 = *v14 + v10;\n if (v18 < v12) v18 = v12;\n v19 = v8 + v17 + v11;\n if (v18 < v19) v18 = v19;\n v20 = v14[1];\n v21 = v12 + v20;\n *v15 = v18;\n v22 = v20 + v17 + v10;\n if (v12 + v20 < v18) v21 = v18;\n if (v22 < v21) v22 = v21;\n v23 = v14[2];\n v24 = v20 + v23;\n v25 = v14[3];\n v15[1] = v22;\n v26 = v12 + v24;\n if (v26 < v18 + v23) v26 = v18 + v23;\n if (v26 < v22) v26 = v22;\n v8 = v18 + v25 + v23;\n v15[2] = v26;\n if (v8 < v22 + v25) v8 = v22 + v25;\n v27 = v14[4];\n if (v8 < v26) v8 = v26;\n v10 = v27 + v25 + v22;\n v15[3] = v8;\n if (v10 < v26 + v27) v10 = v26 + v27;\n v11 = v14[5];\n if (v10 < v8) v10 = v8;\n v12 = v26 + v11 + v27;\n v15[4] = v10;\n if (v12 < v8 + v11) v12 = v8 + v11;\n v28 = v16;\n if (v12 < v10) v12 = v10;\n LODWORD(v16) = v16 + 6;\n v14 += 6;\n v15 += 6;\n *(v15 - 1) = v12;\n } while (a2 - 5 > v28 + 7);\n }\n v16 = (int)v16;\n do {\n v29 = a1[v16];\n v30 = v29 + v34[v16 - 2];\n if (v30 < v34[v16 - 1]) v30 = v34[v16 - 1];\n v31 = v34[v16 - 3] + a1[v16 - 1] + v29;\n if (v30 < v31) v30 = v31;\n v34[v16++] = v30;\n } while (a2 > (int)v16);\n }\n }\n }\n }\n return (unsigned int)v34[a2 - 1];\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n long long v3;\n uint32_t *v4;\n short v5;\n signed long long v6;\n void *v7;\n int v8;\n int v9;\n int v10;\n int v11;\n int v12;\n int v13;\n int *v14;\n int *v15;\n long long v16;\n int v17;\n int v18;\n int v19;\n int v20;\n int v21;\n int v22;\n int v23;\n int v24;\n int v25;\n int v26;\n int v27;\n int v28;\n int v29;\n int v30;\n int v31;\n uint32_t v34[3];\n int v35;\n uint64_t v36[6];\n v36[1] = __readfsqword(40u);\n v3 = 4LL * a2 + 15;\n v4 = (uint32_t *)((char *)v36 - (v3 & 18446744073709547520LL));\n v5 = v3 & 65520;\n if (v36 != (uint64_t *)v4) {\n while (v34 != v4)\n ;\n }\n v6 = v5 & 4095;\n v7 = alloca(v6);\n if (v6)\n *(uint64_t *)((char *)&v34[-2] + v6) = *(uint64_t *)((char *)&v34[-2] + v6);\n if (a2 > 0) {\n v8 = *a1;\n v34[0] = *a1;\n if (a2 != 1) {\n v9 = a1[1];\n v10 = v8 + v9;\n v34[1] = v8 + v9;\n if (a2 != 2) {\n v11 = a1[2];\n v12 = v8 + v11;\n if (v8 + v11 < v10) v12 = v8 + v9;\n v13 = v11 + v9;\n if (v12 < v13) v12 = v13;\n v34[2] = v12;\n if (a2 != 3) {\n if (a2 <= 9) {\n LODWORD(v16) = 3;\n } else {\n v14 = a1 + 3;\n v15 = &v35;\n LODWORD(v16) = 3;\n do {\n v17 = *v14;\n v18 = *v14 + v10;\n if (v18 < v12) v18 = v12;\n v19 = v8 + v17 + v11;\n if (v18 < v19) v18 = v19;\n v20 = v14[1];\n v21 = v12 + v20;\n *v15 = v18;\n v22 = v20 + v17 + v10;\n if (v12 + v20 < v18) v21 = v18;\n if (v22 < v21) v22 = v21;\n v23 = v14[2];\n v24 = v20 + v23;\n v25 = v14[3];\n v15[1] = v22;\n v26 = v12 + v24;\n if (v26 < v18 + v23) v26 = v18 + v23;\n if (v26 < v22) v26 = v22;\n v8 = v18 + v25 + v23;\n v15[2] = v26;\n if (v8 < v22 + v25) v8 = v22 + v25;\n v27 = v14[4];\n if (v8 < v26) v8 = v26;\n v10 = v27 + v25 + v22;\n v15[3] = v8;\n if (v10 < v26 + v27) v10 = v26 + v27;\n v11 = v14[5];\n if (v10 < v8) v10 = v8;\n v12 = v26 + v11 + v27;\n v15[4] = v10;\n if (v12 < v8 + v11) v12 = v8 + v11;\n v28 = v16;\n if (v12 < v10) v12 = v10;\n LODWORD(v16) = v16 + 6;\n v14 += 6;\n v15 += 6;\n *(v15 - 1) = v12;\n } while (a2 - 5 > v28 + 7);\n }\n v16 = (int)v16;\n do {\n v29 = a1[v16];\n v30 = v29 + v34[v16 - 2];\n if (v30 < v34[v16 - 1]) v30 = v34[v16 - 1];\n v31 = v34[v16 - 3] + a1[v16 - 1] + v29;\n if (v30 < v31) v30 = v31;\n v34[v16++] = v30;\n } while (a2 > (int)v16);\n }\n }\n }\n }\n return (unsigned int)v34[a2 - 1];\n}" + }, + { + "index": 662, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char* key;\n\n int* values;\n\n int size;\n\n} Item;\n\n\n\ntypedef struct {\n\n Item* items;\n\n int size;\n\n} Dict;\n\n\n\nvoid swap(int* a, int* b) {\n\n int temp = *a;\n\n *a = *b;\n\n *b = temp;\n\n}\n\n\n\nvoid sortArray(int arr[], int size) {\n\n for (int i = 0; i < size - 1; i++) {\n\n for (int j = 0; j < size - i - 1; j++) {\n\n if (arr[j] > arr[j + 1]) {\n\n swap(&arr[j], &arr[j + 1]);\n\n }\n\n }\n\n }\n\n}\n\n\n\nint compareDicts(Dict dict1, Dict dict2) {\n\n if (dict1.size != dict2.size) return 0;\n\n \n\n for (int i = 0; i < dict1.size; i++) {\n\n if (strcmp(dict1.items[i].key, dict2.items[i].key) != 0) return 0;\n\n if (dict1.items[i].size != dict2.items[i].size) return 0;\n\n \n\n for (int j = 0; j < dict1.items[i].size; j++) {\n\n if (dict1.items[i].values[j] != dict2.items[i].values[j]) return 0;\n\n }\n\n }\n\n \n\n return 1;\n\n}\n\n\n\n", + "func": "Dict func0(Dict dict) {\n for (int i = 0; i < dict.size; i++) {\n sortArray(dict.items[i].values, dict.items[i].size);\n }\n return dict;\n}", + "test": "int main() {\n\n Item items1[3] = {{ \"n1\", (int[]){2, 3, 1}, 3 }, { \"n2\", (int[]){5, 1, 2}, 3 }, { \"n3\", (int[]){3, 2, 4}, 3 }};\n\n Dict dict1 = { items1, 3 };\n\n Dict expected1 = { (Item[]){ {\"n1\", (int[]){1, 2, 3}, 3}, {\"n2\", (int[]){1, 2, 5}, 3}, {\"n3\", (int[]){2, 3, 4}, 3} }, 3 };\n\n \n\n Item items2[3] = {{ \"n1\", (int[]){25, 37, 41}, 3 }, { \"n2\", (int[]){41, 54, 63}, 3 }, { \"n3\", (int[]){29, 38, 93}, 3 }};\n\n Dict dict2 = { items2, 3 };\n\n Dict expected2 = { (Item[]){ {\"n1\", (int[]){25, 37, 41}, 3}, {\"n2\", (int[]){41, 54, 63}, 3}, {\"n3\", (int[]){29, 38, 93}, 3} }, 3 };\n\n \n\n Item items3[3] = {{ \"n1\", (int[]){58, 44, 56}, 3 }, { \"n2\", (int[]){91, 34, 58}, 3 }, { \"n3\", (int[]){100, 200, 300}, 3 }};\n\n Dict dict3 = { items3, 3 };\n\n Dict expected3 = { (Item[]){ {\"n1\", (int[]){44, 56, 58}, 3}, {\"n2\", (int[]){34, 58, 91}, 3}, {\"n3\", (int[]){100, 200, 300}, 3} }, 3 };\n\n \n\n assert(compareDicts(func0(dict1), expected1));\n\n assert(compareDicts(func0(dict2), expected2));\n\n assert(compareDicts(func0(dict3), expected3));\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,%rax\nmov %rsi,%rcx\nmov %rcx,%rdx\nmov %rax,-0x20(%rbp)\nmov %rdx,-0x18(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 147a \nmov -0x20(%rbp),%rcx\nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nadd %rcx,%rax\nmov 0x10(%rax),%ecx\nmov -0x20(%rbp),%rsi\nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nadd %rsi,%rax\nmov 0x8(%rax),%rax\nmov %ecx,%esi\nmov %rax,%rdi\ncallq 11ba \naddl $0x1,-0x4(%rbp)\nmov -0x18(%rbp),%eax\ncmp %eax,-0x4(%rbp)\njl 1431 \nmov -0x20(%rbp),%rax\nmov -0x18(%rbp),%rdx\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov rax, rdi\nmov rcx, rsi\nmov rdx, rcx\nmov [rbp+var_20], rax\nmov [rbp+var_18], rdx\nmov [rbp+var_4], 0\njmp short loc_147A\nloc_1431:\nmov rcx, [rbp+var_20]\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nadd rax, rcx\nmov ecx, [rax+10h]\nmov rsi, [rbp+var_20]\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nadd rax, rsi\nmov rax, [rax+8]\nmov esi, ecx\nmov rdi, rax\ncall sortArray\nadd [rbp+var_4], 1\nloc_147A:\nmov eax, dword ptr [rbp+var_18]\ncmp [rbp+var_4], eax\njl short loc_1431\nmov rax, [rbp+var_20]\nmov rdx, [rbp+var_18]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+1Ch] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n sortArray(*(_QWORD *)(a1 + 24LL * i + 8), *(unsigned int *)(a1 + 24LL * i + 16));\n return a1;\n}", + "ida_strip_asm": "sub_140B:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov rax, rdi\nmov rcx, rsi\nmov rdx, rcx\nmov [rbp+var_20], rax\nmov [rbp+var_18], rdx\nmov [rbp+var_4], 0\njmp short loc_147A\nloc_1431:\nmov rcx, [rbp+var_20]\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nadd rax, rcx\nmov ecx, [rax+10h]\nmov rsi, [rbp+var_20]\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nadd rax, rsi\nmov rax, [rax+8]\nmov esi, ecx\nmov rdi, rax\ncall sub_11BA\nadd [rbp+var_4], 1\nloc_147A:\nmov eax, dword ptr [rbp+var_18]\ncmp [rbp+var_4], eax\njl short loc_1431\nmov rax, [rbp+var_20]\nmov rdx, [rbp+var_18]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_140B(__int64 a1, int a2)\n{\n int i; // [rsp+1Ch] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n sub_11BA(*(_QWORD *)(a1 + 24LL * i + 8), *(unsigned int *)(a1 + 24LL * i + 16));\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_140B(long long a1, int a2) {\n int i;\n for (i = 0; i < a2; ++i)\n sub_11BA(*(uint64_t *)(a1 + 24LL * i + 8),\n *(unsigned int *)(a1 + 24LL * i + 16));\n return a1;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int i;\n for (i = 0; i < a2; ++i)\n sortArray(*(uint64_t *)(a1 + 24LL * i + 8),\n *(unsigned int *)(a1 + 24LL * i + 16));\n return a1;\n}" + }, + { + "index": 662, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char* key;\n\n int* values;\n\n int size;\n\n} Item;\n\n\n\ntypedef struct {\n\n Item* items;\n\n int size;\n\n} Dict;\n\n\n\nvoid swap(int* a, int* b) {\n\n int temp = *a;\n\n *a = *b;\n\n *b = temp;\n\n}\n\n\n\nvoid sortArray(int arr[], int size) {\n\n for (int i = 0; i < size - 1; i++) {\n\n for (int j = 0; j < size - i - 1; j++) {\n\n if (arr[j] > arr[j + 1]) {\n\n swap(&arr[j], &arr[j + 1]);\n\n }\n\n }\n\n }\n\n}\n\n\n\nint compareDicts(Dict dict1, Dict dict2) {\n\n if (dict1.size != dict2.size) return 0;\n\n \n\n for (int i = 0; i < dict1.size; i++) {\n\n if (strcmp(dict1.items[i].key, dict2.items[i].key) != 0) return 0;\n\n if (dict1.items[i].size != dict2.items[i].size) return 0;\n\n \n\n for (int j = 0; j < dict1.items[i].size; j++) {\n\n if (dict1.items[i].values[j] != dict2.items[i].values[j]) return 0;\n\n }\n\n }\n\n \n\n return 1;\n\n}\n\n\n\n", + "func": "Dict func0(Dict dict) {\n for (int i = 0; i < dict.size; i++) {\n sortArray(dict.items[i].values, dict.items[i].size);\n }\n return dict;\n}", + "test": "int main() {\n\n Item items1[3] = {{ \"n1\", (int[]){2, 3, 1}, 3 }, { \"n2\", (int[]){5, 1, 2}, 3 }, { \"n3\", (int[]){3, 2, 4}, 3 }};\n\n Dict dict1 = { items1, 3 };\n\n Dict expected1 = { (Item[]){ {\"n1\", (int[]){1, 2, 3}, 3}, {\"n2\", (int[]){1, 2, 5}, 3}, {\"n3\", (int[]){2, 3, 4}, 3} }, 3 };\n\n \n\n Item items2[3] = {{ \"n1\", (int[]){25, 37, 41}, 3 }, { \"n2\", (int[]){41, 54, 63}, 3 }, { \"n3\", (int[]){29, 38, 93}, 3 }};\n\n Dict dict2 = { items2, 3 };\n\n Dict expected2 = { (Item[]){ {\"n1\", (int[]){25, 37, 41}, 3}, {\"n2\", (int[]){41, 54, 63}, 3}, {\"n3\", (int[]){29, 38, 93}, 3} }, 3 };\n\n \n\n Item items3[3] = {{ \"n1\", (int[]){58, 44, 56}, 3 }, { \"n2\", (int[]){91, 34, 58}, 3 }, { \"n3\", (int[]){100, 200, 300}, 3 }};\n\n Dict dict3 = { items3, 3 };\n\n Dict expected3 = { (Item[]){ {\"n1\", (int[]){44, 56, 58}, 3}, {\"n2\", (int[]){34, 58, 91}, 3}, {\"n3\", (int[]){100, 200, 300}, 3} }, 3 };\n\n \n\n assert(compareDicts(func0(dict1), expected1));\n\n assert(compareDicts(func0(dict2), expected2));\n\n assert(compareDicts(func0(dict3), expected3));\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%r13\nmov %rsi,%r12\ntest %esi,%esi\njle 12be \nlea 0x8(%rdi),%rbx\nlea -0x1(%rsi),%eax\nlea (%rax,%rax,2),%rax\nlea 0x20(%rdi,%rax,8),%rbp\nmov 0x8(%rbx),%esi\nmov (%rbx),%rdi\ncallq 1196 \nadd $0x18,%rbx\ncmp %rbp,%rbx\njne 12aa \nmov %r13,%rax\nmov %r12,%rdx\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r13, rdi\nmov r12, rsi\ntest esi, esi\njle short loc_12B8\nlea rbx, [rdi+8]\nmovsxd rax, esi\nlea rax, [rax+rax*2]\nlea rbp, [rbx+rax*8]\nloc_12A4:\nmov esi, [rbx+8]\nmov rdi, [rbx]\ncall sortArray\nadd rbx, 18h\ncmp rbx, rbp\njnz short loc_12A4\nloc_12B8:\nmov rax, r13\nmov rdx, r12\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // rbx\n\n if ( a2 > 0 )\n {\n v2 = a1 + 8;\n do\n {\n sortArray(*(_QWORD *)v2, *(unsigned int *)(v2 + 8));\n v2 += 24LL;\n }\n while ( v2 != a1 + 8 + 24LL * a2 );\n }\n return a1;\n}", + "ida_strip_asm": "sub_127D:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r13, rdi\nmov r12, rsi\ntest esi, esi\njle short loc_12B8\nlea rbx, [rdi+8]\nmovsxd rax, esi\nlea rax, [rax+rax*2]\nlea rbp, [rbx+rax*8]\nloc_12A4:\nmov esi, [rbx+8]\nmov rdi, [rbx]\ncall sub_1196\nadd rbx, 18h\ncmp rbx, rbp\njnz short loc_12A4\nloc_12B8:\nmov rax, r13\nmov rdx, r12\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_127D(__int64 a1, int a2)\n{\n __int64 v2; // rbx\n\n if ( a2 > 0 )\n {\n v2 = a1 + 8;\n do\n {\n sub_1196(*(_QWORD *)v2, *(unsigned int *)(v2 + 8));\n v2 += 24LL;\n }\n while ( v2 != a1 + 8 + 24LL * a2 );\n }\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_127D(long long a1, int a2) {\n long long v2;\n if (a2 > 0) {\n v2 = a1 + 8;\n do {\n sub_1196(*(uint64_t *)v2, *(unsigned int *)(v2 + 8));\n v2 += 24LL;\n } while (v2 != a1 + 8 + 24LL * a2);\n }\n return a1;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n if (a2 > 0) {\n v2 = a1 + 8;\n do {\n sortArray(*(uint64_t *)v2, *(unsigned int *)(v2 + 8));\n v2 += 24LL;\n } while (v2 != a1 + 8 + 24LL * a2);\n }\n return a1;\n}" + }, + { + "index": 662, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char* key;\n\n int* values;\n\n int size;\n\n} Item;\n\n\n\ntypedef struct {\n\n Item* items;\n\n int size;\n\n} Dict;\n\n\n\nvoid swap(int* a, int* b) {\n\n int temp = *a;\n\n *a = *b;\n\n *b = temp;\n\n}\n\n\n\nvoid sortArray(int arr[], int size) {\n\n for (int i = 0; i < size - 1; i++) {\n\n for (int j = 0; j < size - i - 1; j++) {\n\n if (arr[j] > arr[j + 1]) {\n\n swap(&arr[j], &arr[j + 1]);\n\n }\n\n }\n\n }\n\n}\n\n\n\nint compareDicts(Dict dict1, Dict dict2) {\n\n if (dict1.size != dict2.size) return 0;\n\n \n\n for (int i = 0; i < dict1.size; i++) {\n\n if (strcmp(dict1.items[i].key, dict2.items[i].key) != 0) return 0;\n\n if (dict1.items[i].size != dict2.items[i].size) return 0;\n\n \n\n for (int j = 0; j < dict1.items[i].size; j++) {\n\n if (dict1.items[i].values[j] != dict2.items[i].values[j]) return 0;\n\n }\n\n }\n\n \n\n return 1;\n\n}\n\n\n\n", + "func": "Dict func0(Dict dict) {\n for (int i = 0; i < dict.size; i++) {\n sortArray(dict.items[i].values, dict.items[i].size);\n }\n return dict;\n}", + "test": "int main() {\n\n Item items1[3] = {{ \"n1\", (int[]){2, 3, 1}, 3 }, { \"n2\", (int[]){5, 1, 2}, 3 }, { \"n3\", (int[]){3, 2, 4}, 3 }};\n\n Dict dict1 = { items1, 3 };\n\n Dict expected1 = { (Item[]){ {\"n1\", (int[]){1, 2, 3}, 3}, {\"n2\", (int[]){1, 2, 5}, 3}, {\"n3\", (int[]){2, 3, 4}, 3} }, 3 };\n\n \n\n Item items2[3] = {{ \"n1\", (int[]){25, 37, 41}, 3 }, { \"n2\", (int[]){41, 54, 63}, 3 }, { \"n3\", (int[]){29, 38, 93}, 3 }};\n\n Dict dict2 = { items2, 3 };\n\n Dict expected2 = { (Item[]){ {\"n1\", (int[]){25, 37, 41}, 3}, {\"n2\", (int[]){41, 54, 63}, 3}, {\"n3\", (int[]){29, 38, 93}, 3} }, 3 };\n\n \n\n Item items3[3] = {{ \"n1\", (int[]){58, 44, 56}, 3 }, { \"n2\", (int[]){91, 34, 58}, 3 }, { \"n3\", (int[]){100, 200, 300}, 3 }};\n\n Dict dict3 = { items3, 3 };\n\n Dict expected3 = { (Item[]){ {\"n1\", (int[]){44, 56, 58}, 3}, {\"n2\", (int[]){34, 58, 91}, 3}, {\"n3\", (int[]){100, 200, 300}, 3} }, 3 };\n\n \n\n assert(compareDicts(func0(dict1), expected1));\n\n assert(compareDicts(func0(dict2), expected2));\n\n assert(compareDicts(func0(dict3), expected3));\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov %rdi,%r13\npush %r12\nmov %rsi,%r12\ntest %esi,%esi\njle 181d \nlea -0x1(%rsi),%eax\nlea 0x8(%rdi),%r10\nlea (%rax,%rax,2),%rax\nlea 0x20(%rdi,%rax,8),%r11\nnopw 0x0(%rax,%rax,1)\nmov 0x8(%r10),%esi\nmov (%r10),%rdi\ncallq 1700 \nadd $0x18,%r10\ncmp %r11,%r10\njne 1808 \nmov %r13,%rax\nmov %r12,%rdx\npop %r12\npop %r13\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rdi\npush rbx\nmov rbx, rsi\nsub rsp, 8\ntest esi, esi\njle short loc_187D\nmovsxd rax, esi\nlea r10, [rdi+8]\nlea rax, [rax+rax*2]\nlea r11, [r10+rax*8]\nnop dword ptr [rax+rax+00h]\nloc_1868:\nmov esi, [r10+8]\nmov rdi, [r10]\nadd r10, 18h\ncall sortArray\ncmp r10, r11\njnz short loc_1868\nloc_187D:\nadd rsp, 8\nmov rax, rbp\nmov rdx, rbx\npop rbx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // r10\n __int64 v3; // r11\n\n if ( a2 > 0 )\n {\n v2 = a1 + 8;\n do\n sortArray(*(_QWORD *)v2, *(unsigned int *)(v2 + 8));\n while ( v2 != v3 );\n }\n return a1;\n}", + "ida_strip_asm": "sub_1840:\nendbr64\npush rbp\nmov rbp, rdi\npush rbx\nmov rbx, rsi\nsub rsp, 8\ntest esi, esi\njle short loc_187D\nmovsxd rax, esi\nlea r10, [rdi+8]\nlea rax, [rax+rax*2]\nlea r11, [r10+rax*8]\nnop dword ptr [rax+rax+00h]\nloc_1868:\nmov esi, [r10+8]\nmov rdi, [r10]\nadd r10, 18h\ncall sub_1740\ncmp r10, r11\njnz short loc_1868\nloc_187D:\nadd rsp, 8\nmov rax, rbp\nmov rdx, rbx\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1840(__int64 a1, int a2)\n{\n __int64 v2; // r10\n __int64 v3; // r11\n\n if ( a2 > 0 )\n {\n v2 = a1 + 8;\n do\n sub_1740(*(_QWORD *)v2, *(unsigned int *)(v2 + 8));\n while ( v2 != v3 );\n }\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1840(long long a1, int a2) {\n long long v2;\n long long v3;\n if (a2 > 0) {\n v2 = a1 + 8;\n do\n sub_1740(*(uint64_t *)v2, *(unsigned int *)(v2 + 8));\n while (v2 != v3);\n }\n return a1;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n long long v3;\n if (a2 > 0) {\n v2 = a1 + 8;\n do\n sortArray(*(uint64_t *)v2, *(unsigned int *)(v2 + 8));\n while (v2 != v3);\n }\n return a1;\n}" + }, + { + "index": 662, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char* key;\n\n int* values;\n\n int size;\n\n} Item;\n\n\n\ntypedef struct {\n\n Item* items;\n\n int size;\n\n} Dict;\n\n\n\nvoid swap(int* a, int* b) {\n\n int temp = *a;\n\n *a = *b;\n\n *b = temp;\n\n}\n\n\n\nvoid sortArray(int arr[], int size) {\n\n for (int i = 0; i < size - 1; i++) {\n\n for (int j = 0; j < size - i - 1; j++) {\n\n if (arr[j] > arr[j + 1]) {\n\n swap(&arr[j], &arr[j + 1]);\n\n }\n\n }\n\n }\n\n}\n\n\n\nint compareDicts(Dict dict1, Dict dict2) {\n\n if (dict1.size != dict2.size) return 0;\n\n \n\n for (int i = 0; i < dict1.size; i++) {\n\n if (strcmp(dict1.items[i].key, dict2.items[i].key) != 0) return 0;\n\n if (dict1.items[i].size != dict2.items[i].size) return 0;\n\n \n\n for (int j = 0; j < dict1.items[i].size; j++) {\n\n if (dict1.items[i].values[j] != dict2.items[i].values[j]) return 0;\n\n }\n\n }\n\n \n\n return 1;\n\n}\n\n\n\n", + "func": "Dict func0(Dict dict) {\n for (int i = 0; i < dict.size; i++) {\n sortArray(dict.items[i].values, dict.items[i].size);\n }\n return dict;\n}", + "test": "int main() {\n\n Item items1[3] = {{ \"n1\", (int[]){2, 3, 1}, 3 }, { \"n2\", (int[]){5, 1, 2}, 3 }, { \"n3\", (int[]){3, 2, 4}, 3 }};\n\n Dict dict1 = { items1, 3 };\n\n Dict expected1 = { (Item[]){ {\"n1\", (int[]){1, 2, 3}, 3}, {\"n2\", (int[]){1, 2, 5}, 3}, {\"n3\", (int[]){2, 3, 4}, 3} }, 3 };\n\n \n\n Item items2[3] = {{ \"n1\", (int[]){25, 37, 41}, 3 }, { \"n2\", (int[]){41, 54, 63}, 3 }, { \"n3\", (int[]){29, 38, 93}, 3 }};\n\n Dict dict2 = { items2, 3 };\n\n Dict expected2 = { (Item[]){ {\"n1\", (int[]){25, 37, 41}, 3}, {\"n2\", (int[]){41, 54, 63}, 3}, {\"n3\", (int[]){29, 38, 93}, 3} }, 3 };\n\n \n\n Item items3[3] = {{ \"n1\", (int[]){58, 44, 56}, 3 }, { \"n2\", (int[]){91, 34, 58}, 3 }, { \"n3\", (int[]){100, 200, 300}, 3 }};\n\n Dict dict3 = { items3, 3 };\n\n Dict expected3 = { (Item[]){ {\"n1\", (int[]){44, 56, 58}, 3}, {\"n2\", (int[]){34, 58, 91}, 3}, {\"n3\", (int[]){100, 200, 300}, 3} }, 3 };\n\n \n\n assert(compareDicts(func0(dict1), expected1));\n\n assert(compareDicts(func0(dict2), expected2));\n\n assert(compareDicts(func0(dict3), expected3));\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov %rdi,%r13\npush %r12\nmov %rsi,%r12\npush %rbp\npush %rbx\ntest %esi,%esi\njle 18a9 \nlea -0x1(%rsi),%eax\nlea 0x8(%rdi),%r9\nlea (%rax,%rax,2),%rax\nlea 0x20(%rdi,%rax,8),%rbp\nnopl 0x0(%rax)\nmov 0x8(%r9),%esi\nmov (%r9),%rax\nlea -0x1(%rsi),%ecx\ntest %ecx,%ecx\njle 18a0 \nlea 0x4(%rax),%rbx\nnopw 0x0(%rax,%rax,1)\nlea -0x1(%rcx),%r10d\nmov %rax,%r8\nmov %r10,%rcx\nlea (%rbx,%r10,4),%rdx\nxchg %ax,%ax\nmov (%r8),%r10d\nmov 0x4(%r8),%r11d\ncmp %r11d,%r10d\njle 1893 \nmov %r11d,(%r8)\nmov %r10d,0x4(%r8)\nadd $0x4,%r8\ncmp %r8,%rdx\njne 1880 \ntest %ecx,%ecx\njne 1870 \nadd $0x18,%r9\ncmp %r9,%rbp\njne 1858 \npop %rbx\nmov %r13,%rax\nmov %r12,%rdx\npop %rbp\npop %r12\npop %r13\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rdi\npush rbx\nmov rbx, rsi\ntest esi, esi\njle short loc_18B8\nmovsxd rax, esi\nlea r10, [rdi+8]\nlea rax, [rax+rax*2]\nlea r11, [r10+rax*8]\nnop\nloc_1860:\nmov edi, [r10+8]\nmov r8, [r10]\ncmp edi, 1\njle short loc_18AF\nlea r9, [r8+4]\nloc_1870:\ncmp edi, 1\njle short loc_18C8\nlea edx, [rdi-2]\nmov rax, r8\nlea rsi, [r9+rdx*4]\nnop\nloc_1880:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd edx, xmm0\nmovd ecx, xmm1\ncmp ecx, edx\njge short loc_189E\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_189E:\nadd rax, 4\ncmp rax, rsi\njnz short loc_1880\nsub edi, 1\ncmp edi, 1\njnz short loc_1870\nloc_18AF:\nadd r10, 18h\ncmp r10, r11\njnz short loc_1860\nloc_18B8:\nmov rax, rbp\nmov rdx, rbx\npop rbx\npop rbp\nretn\nloc_18C8:\nsub edi, 1\njmp short loc_1870", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v3; // r10\n __int64 v4; // r11\n int v5; // edi\n __m128i *v6; // r8\n __m128i *v7; // rax\n __m128i v8; // xmm0\n\n if ( a2 > 0 )\n {\n v3 = a1 + 8;\n v4 = a1 + 8 + 24LL * a2;\n do\n {\n v5 = *(_DWORD *)(v3 + 8);\n v6 = *(__m128i **)v3;\n if ( v5 > 1 )\n {\n do\n {\n while ( v5 <= 1 )\n --v5;\n v7 = v6;\n do\n {\n v8 = _mm_loadl_epi64(v7);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v8, 229)) < _mm_cvtsi128_si32(v8) )\n v7->m128i_i64[0] = _mm_shuffle_epi32(v8, 225).m128i_u64[0];\n v7 = (__m128i *)((char *)v7 + 4);\n }\n while ( v7 != (__m128i *)((char *)v6->m128i_i64 + 4 * (unsigned int)(v5 - 2) + 4) );\n --v5;\n }\n while ( v5 != 1 );\n }\n v3 += 24LL;\n }\n while ( v3 != v4 );\n }\n return a1;\n}", + "ida_strip_asm": "sub_1840:\nendbr64\npush rbp\nmov rbp, rdi\npush rbx\nmov rbx, rsi\ntest esi, esi\njle short loc_18B8\nmovsxd rax, esi\nlea r10, [rdi+8]\nlea rax, [rax+rax*2]\nlea r11, [r10+rax*8]\nnop\nloc_1860:\nmov edi, [r10+8]\nmov r8, [r10]\ncmp edi, 1\njle short loc_18AF\nlea r9, [r8+4]\nloc_1870:\ncmp edi, 1\njle short loc_18C8\nlea edx, [rdi-2]\nmov rax, r8\nlea rsi, [r9+rdx*4]\nnop\nloc_1880:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd edx, xmm0\nmovd ecx, xmm1\ncmp ecx, edx\njge short loc_189E\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_189E:\nadd rax, 4\ncmp rax, rsi\njnz short loc_1880\nsub edi, 1\ncmp edi, 1\njnz short loc_1870\nloc_18AF:\nadd r10, 18h\ncmp r10, r11\njnz short loc_1860\nloc_18B8:\nmov rax, rbp\nmov rdx, rbx\npop rbx\npop rbp\nretn\nloc_18C8:\nsub edi, 1\njmp short loc_1870", + "ida_strip_pseudo": "__int64 __fastcall sub_1840(__int64 a1, int a2)\n{\n __int64 v3; // r10\n __int64 v4; // r11\n int v5; // edi\n __m128i *v6; // r8\n __m128i *v7; // rax\n __m128i v8; // xmm0\n\n if ( a2 > 0 )\n {\n v3 = a1 + 8;\n v4 = a1 + 8 + 24LL * a2;\n do\n {\n v5 = *(_DWORD *)(v3 + 8);\n v6 = *(__m128i **)v3;\n if ( v5 > 1 )\n {\n do\n {\n while ( v5 <= 1 )\n --v5;\n v7 = v6;\n do\n {\n v8 = _mm_loadl_epi64(v7);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v8, 229)) < _mm_cvtsi128_si32(v8) )\n v7->m128i_i64[0] = _mm_shuffle_epi32(v8, 225).m128i_u64[0];\n v7 = (__m128i *)((char *)v7 + 4);\n }\n while ( v7 != (__m128i *)((char *)v6->m128i_i64 + 4 * (unsigned int)(v5 - 2) + 4) );\n --v5;\n }\n while ( v5 != 1 );\n }\n v3 += 24LL;\n }\n while ( v3 != v4 );\n }\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1840(long long a1, int a2) {\n long long v3;\n long long v4;\n int v5;\n __m128i *v6;\n __m128i *v7;\n __m128i v8;\n if (a2 > 0) {\n v3 = a1 + 8;\n v4 = a1 + 8 + 24LL * a2;\n do {\n v5 = *(uint32_t *)(v3 + 8);\n v6 = *(__m128i **)v3;\n if (v5 > 1) {\n do {\n while (v5 <= 1) --v5;\n v7 = v6;\n do {\n v8 = _mm_loadl_epi64(v7);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v8, 229)) <\n _mm_cvtsi128_si32(v8))\n v7->m128i_i64[0] = _mm_shuffle_epi32(v8, 225).m128i_u64[0];\n v7 = (__m128i *)((char *)v7 + 4);\n } while (v7 != (__m128i *)((char *)v6->m128i_i64 +\n 4 * (unsigned int)(v5 - 2) + 4));\n --v5;\n } while (v5 != 1);\n }\n v3 += 24LL;\n } while (v3 != v4);\n }\n return a1;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v3;\n long long v4;\n int v5;\n __m128i *v6;\n __m128i *v7;\n __m128i v8;\n if (a2 > 0) {\n v3 = a1 + 8;\n v4 = a1 + 8 + 24LL * a2;\n do {\n v5 = *(uint32_t *)(v3 + 8);\n v6 = *(__m128i **)v3;\n if (v5 > 1) {\n do {\n while (v5 <= 1) --v5;\n v7 = v6;\n do {\n v8 = _mm_loadl_epi64(v7);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v8, 229)) <\n _mm_cvtsi128_si32(v8))\n v7->m128i_i64[0] = _mm_shuffle_epi32(v8, 225).m128i_u64[0];\n v7 = (__m128i *)((char *)v7 + 4);\n } while (v7 != (__m128i *)((char *)v6->m128i_i64 +\n 4 * (unsigned int)(v5 - 2) + 4));\n --v5;\n } while (v5 != 1);\n }\n v3 += 24LL;\n } while (v3 != v4);\n }\n return a1;\n}" + }, + { + "index": 663, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n, int x, int y) {\n int ans = INT_MIN;\n for (int k = 0; k <= n; k++) {\n if (k % x == y) {\n if (ans < k) {\n ans = k;\n }\n }\n }\n return ((ans >= 0 && ans <= n) ? ans : -1);\n}", + "test": "int main() {\n\n assert(func0(15, 10, 5) == 15);\n\n assert(func0(187, 10, 5) == 185);\n\n assert(func0(16, 11, 1) == 12);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov %edx,-0x1c(%rbp)\nmovl $0x80000000,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 118a \nmov -0x4(%rbp),%eax\ncltd\nidivl -0x18(%rbp)\nmov %edx,%eax\ncmp %eax,-0x1c(%rbp)\njne 1186 \nmov -0x8(%rbp),%eax\ncmp -0x4(%rbp),%eax\njge 1186 \nmov -0x4(%rbp),%eax\nmov %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x14(%rbp),%eax\njle 116a \ncmpl $0x0,-0x8(%rbp)\njs 11a5 \nmov -0x8(%rbp),%eax\ncmp -0x14(%rbp),%eax\njg 11a5 \nmov -0x8(%rbp),%eax\njmp 11aa \nmov $0xffffffff,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov [rbp+var_8], 80000000h\nmov [rbp+var_4], 0\njmp short loc_118A\nloc_116A:\nmov eax, [rbp+var_4]\ncdq\nidiv [rbp+var_18]\nmov eax, edx\ncmp [rbp+var_1C], eax\njnz short loc_1186\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njge short loc_1186\nmov eax, [rbp+var_4]\nmov [rbp+var_8], eax\nloc_1186:\nadd [rbp+var_4], 1\nloc_118A:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_14]\njle short loc_116A\ncmp [rbp+var_8], 0\njs short loc_11A5\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_14]\njg short loc_11A5\nmov eax, [rbp+var_8]\njmp short loc_11AA\nloc_11A5:\nmov eax, 0FFFFFFFFh\nloc_11AA:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, int a3)\n{\n int v4; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v4 = 0x80000000;\n for ( i = 0; i <= a1; ++i )\n {\n if ( a3 == i % a2 && v4 < i )\n v4 = i;\n }\n if ( v4 < 0 || v4 > a1 )\n return 0xFFFFFFFFLL;\n else\n return (unsigned int)v4;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov [rbp+var_8], 80000000h\nmov [rbp+var_4], 0\njmp short loc_118A\nloc_116A:\nmov eax, [rbp+var_4]\ncdq\nidiv [rbp+var_18]\nmov eax, edx\ncmp [rbp+var_1C], eax\njnz short loc_1186\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njge short loc_1186\nmov eax, [rbp+var_4]\nmov [rbp+var_8], eax\nloc_1186:\nadd [rbp+var_4], 1\nloc_118A:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_14]\njle short loc_116A\ncmp [rbp+var_8], 0\njs short loc_11A5\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_14]\njg short loc_11A5\nmov eax, [rbp+var_8]\njmp short loc_11AA\nloc_11A5:\nmov eax, 0FFFFFFFFh\nloc_11AA:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2, int a3)\n{\n int v4; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v4 = 0x80000000;\n for ( i = 0; i <= a1; ++i )\n {\n if ( a3 == i % a2 && v4 < i )\n v4 = i;\n }\n if ( v4 < 0 || v4 > a1 )\n return 0xFFFFFFFFLL;\n else\n return (unsigned int)v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2, int a3) {\n int v4;\n int i;\n v4 = 2147483648;\n for (i = 0; i <= a1; ++i) {\n if (a3 == i % a2 && v4 < i) v4 = i;\n }\n if (v4 < 0 || v4 > a1)\n return 4294967295LL;\n else\n return (unsigned int)v4;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, int a3) {\n int v4;\n int i;\n v4 = 2147483648;\n for (i = 0; i <= a1; ++i) {\n if (a3 == i % a2 && v4 < i) v4 = i;\n }\n if (v4 < 0 || v4 > a1)\n return 4294967295LL;\n else\n return (unsigned int)v4;\n}" + }, + { + "index": 663, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n, int x, int y) {\n int ans = INT_MIN;\n for (int k = 0; k <= n; k++) {\n if (k % x == y) {\n if (ans < k) {\n ans = k;\n }\n }\n }\n return ((ans >= 0 && ans <= n) ? ans : -1);\n}", + "test": "int main() {\n\n assert(func0(15, 10, 5) == 15);\n\n assert(func0(187, 10, 5) == 185);\n\n assert(func0(16, 11, 1) == 12);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %edx,%r9d\ntest %edi,%edi\njs 118e \nlea 0x1(%rdi),%r10d\nmov $0x0,%ecx\nmov $0x80000000,%r8d\njmp 116d \nadd $0x1,%ecx\ncmp %ecx,%r10d\nje 1180 \nmov %ecx,%eax\ncltd\nidiv %esi\ncmp %r9d,%edx\njne 1165 \ncmp %ecx,%r8d\ncmovl %ecx,%r8d\njmp 1165 \ntest %r8d,%r8d\njs 1196 \ncmp %edi,%r8d\njg 1196 \nmov %r8d,%eax\nretq\nmov $0xffffffff,%r8d\njmp 118a \nmov $0xffffffff,%r8d\njmp 118a \n", + "ida_asm": "func0:\nendbr64\nmov r9d, edx\ntest edi, edi\njs short loc_118E\nlea r10d, [rdi+1]\nmov ecx, 0\nmov r8d, 80000000h\nloc_1163:\nmov eax, ecx\ncdq\nidiv esi\ncmp r8d, ecx\nmov eax, ecx\ncmovge eax, r8d\ncmp edx, r9d\ncmovz r8d, eax\nadd ecx, 1\ncmp r10d, ecx\njnz short loc_1163\ntest r8d, r8d\njs short loc_1196\ncmp r8d, edi\njg short loc_1196\nloc_118A:\nmov eax, r8d\nretn\nloc_118E:\nmov r8d, 0FFFFFFFFh\njmp short loc_118A\nloc_1196:\nmov r8d, 0FFFFFFFFh\njmp short loc_118A", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, int a3)\n{\n int v3; // ecx\n int v4; // r8d\n int v5; // eax\n\n if ( a1 < 0 )\n {\n return (unsigned int)-1;\n }\n else\n {\n v3 = 0;\n v4 = 0x80000000;\n do\n {\n v5 = v3;\n if ( v4 >= v3 )\n v5 = v4;\n if ( v3 % a2 == a3 )\n v4 = v5;\n ++v3;\n }\n while ( a1 + 1 != v3 );\n if ( v4 < 0 || v4 > a1 )\n return (unsigned int)-1;\n }\n return (unsigned int)v4;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmov r9d, edx\ntest edi, edi\njs short loc_118E\nlea r10d, [rdi+1]\nmov ecx, 0\nmov r8d, 80000000h\nloc_1163:\nmov eax, ecx\ncdq\nidiv esi\ncmp r8d, ecx\nmov eax, ecx\ncmovge eax, r8d\ncmp edx, r9d\ncmovz r8d, eax\nadd ecx, 1\ncmp r10d, ecx\njnz short loc_1163\ntest r8d, r8d\njs short loc_1196\ncmp r8d, edi\njg short loc_1196\nloc_118A:\nmov eax, r8d\nretn\nloc_118E:\nmov r8d, 0FFFFFFFFh\njmp short loc_118A\nloc_1196:\nmov r8d, 0FFFFFFFFh\njmp short loc_118A", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2, int a3)\n{\n int v3; // ecx\n int v4; // r8d\n int v5; // eax\n\n if ( a1 < 0 )\n {\n return (unsigned int)-1;\n }\n else\n {\n v3 = 0;\n v4 = 0x80000000;\n do\n {\n v5 = v3;\n if ( v4 >= v3 )\n v5 = v4;\n if ( v3 % a2 == a3 )\n v4 = v5;\n ++v3;\n }\n while ( a1 + 1 != v3 );\n if ( v4 < 0 || v4 > a1 )\n return (unsigned int)-1;\n }\n return (unsigned int)v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2, int a3) {\n int v3;\n int v4;\n int v5;\n if (a1 < 0) {\n return (unsigned int)-1;\n } else {\n v3 = 0;\n v4 = 2147483648;\n do {\n v5 = v3;\n if (v4 >= v3) v5 = v4;\n if (v3 % a2 == a3) v4 = v5;\n ++v3;\n } while (a1 + 1 != v3);\n if (v4 < 0 || v4 > a1) return (unsigned int)-1;\n }\n return (unsigned int)v4;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, int a3) {\n int v3;\n int v4;\n int v5;\n if (a1 < 0) {\n return (unsigned int)-1;\n } else {\n v3 = 0;\n v4 = 2147483648;\n do {\n v5 = v3;\n if (v4 >= v3) v5 = v4;\n if (v3 % a2 == a3) v4 = v5;\n ++v3;\n } while (a1 + 1 != v3);\n if (v4 < 0 || v4 > a1) return (unsigned int)-1;\n }\n return (unsigned int)v4;\n}" + }, + { + "index": 663, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n, int x, int y) {\n int ans = INT_MIN;\n for (int k = 0; k <= n; k++) {\n if (k % x == y) {\n if (ans < k) {\n ans = k;\n }\n }\n }\n return ((ans >= 0 && ans <= n) ? ans : -1);\n}", + "test": "int main() {\n\n assert(func0(15, 10, 5) == 15);\n\n assert(func0(187, 10, 5) == 185);\n\n assert(func0(16, 11, 1) == 12);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov %edx,%r9d\ntest %edi,%edi\njs 12c0 \nlea 0x1(%rdi),%r10d\nxor %ecx,%ecx\nmov $0x80000000,%r8d\nnopw 0x0(%rax,%rax,1)\nmov %ecx,%eax\ncltd\nidiv %esi\ncmp %r9d,%edx\njne 12a1 \ncmp %ecx,%r8d\ncmovl %ecx,%r8d\nadd $0x1,%ecx\ncmp %ecx,%r10d\njne 1290 \ntest %r8d,%r8d\njs 12c0 \ncmp %edi,%r8d\njg 12c0 \nmov %r8d,%eax\nretq\nnopw 0x0(%rax,%rax,1)\nmov $0xffffffff,%r8d\nmov %r8d,%eax\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmov r9d, edx\ntest edi, edi\njs short loc_1260\nlea r10d, [rdi+1]\nxor ecx, ecx\nmov r8d, 80000000h\nnop word ptr [rax+rax+00000000h]\nloc_1230:\nmov eax, ecx\ncdq\nidiv esi\ncmp r8d, ecx\nmov eax, ecx\ncmovge eax, r8d\ncmp r9d, edx\ncmovz r8d, eax\nadd ecx, 1\ncmp r10d, ecx\njnz short loc_1230\ntest r8d, r8d\njs short loc_1260\ncmp edi, r8d\njl short loc_1260\nmov eax, r8d\nretn\nloc_1260:\nmov r8d, 0FFFFFFFFh\nmov eax, r8d\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, int a3)\n{\n int v3; // ecx\n int v4; // r8d\n int v5; // eax\n\n if ( a1 < 0 )\n return 0xFFFFFFFFLL;\n v3 = 0;\n v4 = 0x80000000;\n do\n {\n v5 = v3;\n if ( v4 >= v3 )\n v5 = v4;\n if ( a3 == v3 % a2 )\n v4 = v5;\n ++v3;\n }\n while ( a1 + 1 != v3 );\n if ( v4 < 0 || a1 < v4 )\n return 0xFFFFFFFFLL;\n else\n return (unsigned int)v4;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\nmov r9d, edx\ntest edi, edi\njs short loc_1260\nlea r10d, [rdi+1]\nxor ecx, ecx\nmov r8d, 80000000h\nnop word ptr [rax+rax+00000000h]\nloc_1230:\nmov eax, ecx\ncdq\nidiv esi\ncmp r8d, ecx\nmov eax, ecx\ncmovge eax, r8d\ncmp r9d, edx\ncmovz r8d, eax\nadd ecx, 1\ncmp r10d, ecx\njnz short loc_1230\ntest r8d, r8d\njs short loc_1260\ncmp edi, r8d\njl short loc_1260\nmov eax, r8d\nretn\nloc_1260:\nmov r8d, 0FFFFFFFFh\nmov eax, r8d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(int a1, int a2, int a3)\n{\n int v3; // ecx\n int v4; // r8d\n int v5; // eax\n\n if ( a1 < 0 )\n return 0xFFFFFFFFLL;\n v3 = 0;\n v4 = 0x80000000;\n do\n {\n v5 = v3;\n if ( v4 >= v3 )\n v5 = v4;\n if ( a3 == v3 % a2 )\n v4 = v5;\n ++v3;\n }\n while ( a1 + 1 != v3 );\n if ( v4 < 0 || a1 < v4 )\n return 0xFFFFFFFFLL;\n else\n return (unsigned int)v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(int a1, int a2, int a3) {\n int v3;\n int v4;\n int v5;\n if (a1 < 0) return 4294967295LL;\n v3 = 0;\n v4 = 2147483648;\n do {\n v5 = v3;\n if (v4 >= v3) v5 = v4;\n if (a3 == v3 % a2) v4 = v5;\n ++v3;\n } while (a1 + 1 != v3);\n if (v4 < 0 || a1 < v4)\n return 4294967295LL;\n else\n return (unsigned int)v4;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, int a3) {\n int v3;\n int v4;\n int v5;\n if (a1 < 0) return 4294967295LL;\n v3 = 0;\n v4 = 2147483648;\n do {\n v5 = v3;\n if (v4 >= v3) v5 = v4;\n if (a3 == v3 % a2) v4 = v5;\n ++v3;\n } while (a1 + 1 != v3);\n if (v4 < 0 || a1 < v4)\n return 4294967295LL;\n else\n return (unsigned int)v4;\n}" + }, + { + "index": 664, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n % 2 != 0) {\n printf(\"Invalid Input\\n\");\n return -1;\n }\n int sm = 0, count = 0;\n while (n >= 2) {\n count += 1;\n sm += n;\n n -= 2;\n }\n return sm / count;\n}", + "test": "int main() {\n\n assert(func0(2) == 2);\n\n assert(func0(4) == 3);\n\n assert(func0(100) == 51);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %edi,-0x14(%rbp)\nmov -0x14(%rbp),%eax\nand $0x1,%eax\ntest %eax,%eax\nje 1195 \nlea 0xe7f(%rip),%rdi\ncallq 1060 \nmov $0xffffffff,%eax\njmp 11c0 \nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11b3 \naddl $0x1,-0x4(%rbp)\nmov -0x14(%rbp),%eax\nadd %eax,-0x8(%rbp)\nsubl $0x2,-0x14(%rbp)\ncmpl $0x1,-0x14(%rbp)\njg 11a5 \nmov -0x8(%rbp),%eax\ncltd\nidivl -0x4(%rbp)\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov eax, [rbp+var_14]\nand eax, 1\ntest eax, eax\njz short loc_1198\nlea rax, s; \"Invalid Input\"\nmov rdi, rax; s\ncall _puts\nmov eax, 0FFFFFFFFh\njmp short locret_11C3\nloc_1198:\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11B6\nloc_11A8:\nadd [rbp+var_4], 1\nmov eax, [rbp+var_14]\nadd [rbp+var_8], eax\nsub [rbp+var_14], 2\nloc_11B6:\ncmp [rbp+var_14], 1\njg short loc_11A8\nmov eax, [rbp+var_8]\ncdq\nidiv [rbp+var_4]\nlocret_11C3:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v2; // [rsp+Ch] [rbp-14h]\n int v3; // [rsp+18h] [rbp-8h]\n int v4; // [rsp+1Ch] [rbp-4h]\n\n v2 = a1;\n if ( (a1 & 1) != 0 )\n {\n puts(\"Invalid Input\");\n return 0xFFFFFFFFLL;\n }\n else\n {\n v3 = 0;\n v4 = 0;\n while ( v2 > 1 )\n {\n ++v4;\n v3 += v2;\n v2 -= 2;\n }\n return (unsigned int)(v3 / v4);\n }\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov eax, [rbp+var_14]\nand eax, 1\ntest eax, eax\njz short loc_1198\nlea rax, s; \"Invalid Input\"\nmov rdi, rax; s\ncall _puts\nmov eax, 0FFFFFFFFh\njmp short locret_11C3\nloc_1198:\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11B6\nloc_11A8:\nadd [rbp+var_4], 1\nmov eax, [rbp+var_14]\nadd [rbp+var_8], eax\nsub [rbp+var_14], 2\nloc_11B6:\ncmp [rbp+var_14], 1\njg short loc_11A8\nmov eax, [rbp+var_8]\ncdq\nidiv [rbp+var_4]\nlocret_11C3:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n int v2; // [rsp+Ch] [rbp-14h]\n int v3; // [rsp+18h] [rbp-8h]\n int v4; // [rsp+1Ch] [rbp-4h]\n\n v2 = a1;\n if ( (a1 & 1) != 0 )\n {\n puts(\"Invalid Input\");\n return 0xFFFFFFFFLL;\n }\n else\n {\n v3 = 0;\n v4 = 0;\n while ( v2 > 1 )\n {\n ++v4;\n v3 += v2;\n v2 -= 2;\n }\n return (unsigned int)(v3 / v4);\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n int v2;\n int v3;\n int v4;\n v2 = a1;\n if ((a1 & 1) != 0) {\n puts(\"Invalid Input\");\n return 4294967295LL;\n } else {\n v3 = 0;\n v4 = 0;\n while (v2 > 1) {\n ++v4;\n v3 += v2;\n v2 -= 2;\n }\n return (unsigned int)(v3 / v4);\n }\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v2;\n int v3;\n int v4;\n v2 = a1;\n if ((a1 & 1) != 0) {\n puts(\"Invalid Input\");\n return 4294967295LL;\n } else {\n v3 = 0;\n v4 = 0;\n while (v2 > 1) {\n ++v4;\n v3 += v2;\n v2 -= 2;\n }\n return (unsigned int)(v3 / v4);\n }\n}" + }, + { + "index": 664, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n % 2 != 0) {\n printf(\"Invalid Input\\n\");\n return -1;\n }\n int sm = 0, count = 0;\n while (n >= 2) {\n count += 1;\n sm += n;\n n -= 2;\n }\n return sm / count;\n}", + "test": "int main() {\n\n assert(func0(2) == 2);\n\n assert(func0(4) == 3);\n\n assert(func0(100) == 51);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest $0x1,%dil\njne 119c \nmov %edi,%ecx\nmov $0x0,%eax\ncmp $0x1,%edi\njle 1195 \nadd %edi,%eax\nsub $0x2,%edi\ncmp $0x1,%edi\njg 117f \nsub $0x2,%ecx\nshr %ecx\nadd $0x1,%ecx\ncltd\nidiv %ecx\nretq\nmov $0x0,%ecx\njmp 1191 \nsub $0x8,%rsp\nlea 0xe5d(%rip),%rdi\ncallq 1060 \nmov $0xffffffff,%eax\nadd $0x8,%rsp\nretq\n", + "ida_asm": "func0:\nendbr64\nmov eax, edi\nand eax, 1\njnz short loc_1195\nmov edx, edi\ncmp edi, 1\njle short loc_1191\nloc_117B:\nadd eax, edx\nsub edx, 2\ncmp edx, 1\njg short loc_117B\nsub edi, 2\nshr edi, 1\nadd edi, 1\nloc_118D:\ncdq\nidiv edi\nretn\nloc_1191:\nmov edi, eax\njmp short loc_118D\nloc_1195:\nsub rsp, 8\nlea rdi, s; \"Invalid Input\"\ncall _puts\nmov eax, 0FFFFFFFFh\nadd rsp, 8\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // eax\n int v2; // edx\n int v3; // edi\n\n v1 = a1 & 1;\n if ( (a1 & 1) != 0 )\n {\n puts(\"Invalid Input\");\n return 0xFFFFFFFFLL;\n }\n else\n {\n v2 = a1;\n if ( a1 <= 1 )\n {\n v3 = a1 & 1;\n }\n else\n {\n do\n {\n v1 += v2;\n v2 -= 2;\n }\n while ( v2 > 1 );\n v3 = ((unsigned int)(a1 - 2) >> 1) + 1;\n }\n return (unsigned int)(v1 / v3);\n }\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov eax, edi\nand eax, 1\njnz short loc_1195\nmov edx, edi\ncmp edi, 1\njle short loc_1191\nloc_117B:\nadd eax, edx\nsub edx, 2\ncmp edx, 1\njg short loc_117B\nsub edi, 2\nshr edi, 1\nadd edi, 1\nloc_118D:\ncdq\nidiv edi\nretn\nloc_1191:\nmov edi, eax\njmp short loc_118D\nloc_1195:\nsub rsp, 8\nlea rdi, s; \"Invalid Input\"\ncall _puts\nmov eax, 0FFFFFFFFh\nadd rsp, 8\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n int v1; // eax\n int v2; // edx\n int v3; // edi\n\n v1 = a1 & 1;\n if ( (a1 & 1) != 0 )\n {\n puts(\"Invalid Input\");\n return 0xFFFFFFFFLL;\n }\n else\n {\n v2 = a1;\n if ( a1 <= 1 )\n {\n v3 = a1 & 1;\n }\n else\n {\n do\n {\n v1 += v2;\n v2 -= 2;\n }\n while ( v2 > 1 );\n v3 = ((unsigned int)(a1 - 2) >> 1) + 1;\n }\n return (unsigned int)(v1 / v3);\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n int v1;\n int v2;\n int v3;\n v1 = a1 & 1;\n if ((a1 & 1) != 0) {\n puts(\"Invalid Input\");\n return 4294967295LL;\n } else {\n v2 = a1;\n if (a1 <= 1) {\n v3 = a1 & 1;\n } else {\n do {\n v1 += v2;\n v2 -= 2;\n } while (v2 > 1);\n v3 = ((unsigned int)(a1 - 2) >> 1) + 1;\n }\n return (unsigned int)(v1 / v3);\n }\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v2;\n int v3;\n v1 = a1 & 1;\n if ((a1 & 1) != 0) {\n puts(\"Invalid Input\");\n return 4294967295LL;\n } else {\n v2 = a1;\n if (a1 <= 1) {\n v3 = a1 & 1;\n } else {\n do {\n v1 += v2;\n v2 -= 2;\n } while (v2 > 1);\n v3 = ((unsigned int)(a1 - 2) >> 1) + 1;\n }\n return (unsigned int)(v1 / v3);\n }\n}" + }, + { + "index": 665, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int *num_list, int n, int *output) {\n int first_element = num_list[0];\n int count_first = 0;\n int output_index = 0;\n for (int i = 0; i < n; i++) {\n if (num_list[i] == first_element) {\n count_first++;\n }\n }\n for (int i = 0; i < n; i++) {\n if (num_list[i] != first_element) {\n output[output_index++] = num_list[i];\n }\n }\n for (int i = 0; i < count_first; i++) {\n output[output_index++] = first_element;\n }\n}", + "test": "int main() {\n\n int test1[] = {1, 2, 3, 4};\n\n int result1[4];\n\n func0(test1, 4, result1);\n\n assert(result1[0] == 2 && result1[1] == 3 && result1[2] == 4 && result1[3] == 1);\n\n\n\n int test2[] = {2, 3, 4, 1, 5, 0};\n\n int result2[6];\n\n func0(test2, 6, result2);\n\n assert(result2[0] == 3 && result2[1] == 4 && result2[2] == 1 && result2[3] == 5 && result2[4] == 0 && result2[5] == 2);\n\n\n\n int test3[] = {5, 4, 3, 2, 1};\n\n int result3[5];\n\n func0(test3, 5, result3);\n\n assert(result3[0] == 4 && result3[1] == 3 && result3[2] == 2 && result3[3] == 1 && result3[4] == 5);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmov %rdx,-0x38(%rbp)\nmov -0x28(%rbp),%rax\nmov (%rax),%eax\nmov %eax,-0x4(%rbp)\nmovl $0x0,-0x18(%rbp)\nmovl $0x0,-0x14(%rbp)\nmovl $0x0,-0x10(%rbp)\njmp 11bf \nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x4(%rbp)\njne 11bb \naddl $0x1,-0x18(%rbp)\naddl $0x1,-0x10(%rbp)\nmov -0x10(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 119c \nmovl $0x0,-0xc(%rbp)\njmp 1222 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x4(%rbp)\nje 121e \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x14(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x14(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x38(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 11d0 \nmovl $0x0,-0x8(%rbp)\njmp 1256 \nmov -0x14(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x14(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x38(%rbp),%rax\nadd %rax,%rdx\nmov -0x4(%rbp),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x18(%rbp),%eax\njl 1233 \npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmov rax, [rbp+var_28]\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\njmp short loc_11BF\nloc_119C:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_4], eax\njnz short loc_11BB\nadd [rbp+var_18], 1\nloc_11BB:\nadd [rbp+var_10], 1\nloc_11BF:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_2C]\njl short loc_119C\nmov [rbp+var_C], 0\njmp short loc_1222\nloc_11D0:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_4], eax\njz short loc_121E\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_14]\nlea edx, [rax+1]\nmov [rbp+var_14], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_121E:\nadd [rbp+var_C], 1\nloc_1222:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_2C]\njl short loc_11D0\nmov [rbp+var_8], 0\njmp short loc_1256\nloc_1233:\nmov eax, [rbp+var_14]\nlea edx, [rax+1]\nmov [rbp+var_14], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nadd [rbp+var_8], 1\nloc_1256:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_18]\njl short loc_1233\nnop\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2, __int64 a3)\n{\n int v3; // eax\n int v4; // eax\n __int64 result; // rax\n int v6; // [rsp+20h] [rbp-18h]\n int v7; // [rsp+24h] [rbp-14h]\n int i; // [rsp+28h] [rbp-10h]\n int j; // [rsp+2Ch] [rbp-Ch]\n unsigned int k; // [rsp+30h] [rbp-8h]\n int v11; // [rsp+34h] [rbp-4h]\n\n v11 = *a1;\n v6 = 0;\n v7 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( v11 == a1[i] )\n ++v6;\n }\n for ( j = 0; j < a2; ++j )\n {\n if ( v11 != a1[j] )\n {\n v3 = v7++;\n *(_DWORD *)(a3 + 4LL * v3) = a1[j];\n }\n }\n for ( k = 0; ; ++k )\n {\n result = k;\n if ( (int)k >= v6 )\n break;\n v4 = v7++;\n *(_DWORD *)(a3 + 4LL * v4) = v11;\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmov rax, [rbp+var_28]\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\njmp short loc_11BF\nloc_119C:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_4], eax\njnz short loc_11BB\nadd [rbp+var_18], 1\nloc_11BB:\nadd [rbp+var_10], 1\nloc_11BF:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_2C]\njl short loc_119C\nmov [rbp+var_C], 0\njmp short loc_1222\nloc_11D0:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_4], eax\njz short loc_121E\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_14]\nlea edx, [rax+1]\nmov [rbp+var_14], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_121E:\nadd [rbp+var_C], 1\nloc_1222:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_2C]\njl short loc_11D0\nmov [rbp+var_8], 0\njmp short loc_1256\nloc_1233:\nmov eax, [rbp+var_14]\nlea edx, [rax+1]\nmov [rbp+var_14], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nadd [rbp+var_8], 1\nloc_1256:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_18]\njl short loc_1233\nnop\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int *a1, int a2, __int64 a3)\n{\n int v3; // eax\n int v4; // eax\n __int64 result; // rax\n int v6; // [rsp+20h] [rbp-18h]\n int v7; // [rsp+24h] [rbp-14h]\n int i; // [rsp+28h] [rbp-10h]\n int j; // [rsp+2Ch] [rbp-Ch]\n unsigned int k; // [rsp+30h] [rbp-8h]\n int v11; // [rsp+34h] [rbp-4h]\n\n v11 = *a1;\n v6 = 0;\n v7 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( v11 == a1[i] )\n ++v6;\n }\n for ( j = 0; j < a2; ++j )\n {\n if ( v11 != a1[j] )\n {\n v3 = v7++;\n *(_DWORD *)(a3 + 4LL * v3) = a1[j];\n }\n }\n for ( k = 0; ; ++k )\n {\n result = k;\n if ( (int)k >= v6 )\n break;\n v4 = v7++;\n *(_DWORD *)(a3 + 4LL * v4) = v11;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int *a1, int a2, long long a3) {\n int v3;\n int v4;\n long long result;\n int v6;\n int v7;\n int i;\n int j;\n unsigned int k;\n int v11;\n v11 = *a1;\n v6 = 0;\n v7 = 0;\n for (i = 0; i < a2; ++i) {\n if (v11 == a1[i]) ++v6;\n }\n for (j = 0; j < a2; ++j) {\n if (v11 != a1[j]) {\n v3 = v7++;\n *(uint32_t *)(a3 + 4LL * v3) = a1[j];\n }\n }\n for (k = 0;; ++k) {\n result = k;\n if ((int)k >= v6) break;\n v4 = v7++;\n *(uint32_t *)(a3 + 4LL * v4) = v11;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2, long long a3) {\n int v3;\n int v4;\n long long result;\n int v6;\n int v7;\n int i;\n int j;\n unsigned int k;\n int v11;\n v11 = *a1;\n v6 = 0;\n v7 = 0;\n for (i = 0; i < a2; ++i) {\n if (v11 == a1[i]) ++v6;\n }\n for (j = 0; j < a2; ++j) {\n if (v11 != a1[j]) {\n v3 = v7++;\n *(uint32_t *)(a3 + 4LL * v3) = a1[j];\n }\n }\n for (k = 0;; ++k) {\n result = k;\n if ((int)k >= v6) break;\n v4 = v7++;\n *(uint32_t *)(a3 + 4LL * v4) = v11;\n }\n return result;\n}" + }, + { + "index": 665, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int *num_list, int n, int *output) {\n int first_element = num_list[0];\n int count_first = 0;\n int output_index = 0;\n for (int i = 0; i < n; i++) {\n if (num_list[i] == first_element) {\n count_first++;\n }\n }\n for (int i = 0; i < n; i++) {\n if (num_list[i] != first_element) {\n output[output_index++] = num_list[i];\n }\n }\n for (int i = 0; i < count_first; i++) {\n output[output_index++] = first_element;\n }\n}", + "test": "int main() {\n\n int test1[] = {1, 2, 3, 4};\n\n int result1[4];\n\n func0(test1, 4, result1);\n\n assert(result1[0] == 2 && result1[1] == 3 && result1[2] == 4 && result1[3] == 1);\n\n\n\n int test2[] = {2, 3, 4, 1, 5, 0};\n\n int result2[6];\n\n func0(test2, 6, result2);\n\n assert(result2[0] == 3 && result2[1] == 4 && result2[2] == 1 && result2[3] == 5 && result2[4] == 0 && result2[5] == 2);\n\n\n\n int test3[] = {5, 4, 3, 2, 1};\n\n int result3[5];\n\n func0(test3, 5, result3);\n\n assert(result3[0] == 4 && result3[1] == 3 && result3[2] == 2 && result3[3] == 1 && result3[4] == 5);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov (%rdi),%ecx\ntest %esi,%esi\njle 11df \nmov %rdi,%rax\nlea -0x1(%rsi),%esi\nlea 0x4(%rdi,%rsi,4),%r9\nmov $0x0,%r8d\ncmp %ecx,(%rdi)\nsete %sil\nmovzbl %sil,%esi\nadd %esi,%r8d\nadd $0x4,%rdi\ncmp %r9,%rdi\njne 1184 \nmov $0x0,%edi\njmp 11b4 \nmovslq %edi,%r10\nmov %esi,(%rdx,%r10,4)\nlea 0x1(%rdi),%edi\nadd $0x4,%rax\ncmp %r9,%rax\nje 11bc \nmov (%rax),%esi\ncmp %ecx,%esi\njne 11a1 \njmp 11ab \ntest %r8d,%r8d\njle 11df \nmovslq %edi,%rdi\nlea (%rdx,%rdi,4),%rax\nlea -0x1(%r8),%esi\nadd %rsi,%rdi\nlea 0x4(%rdx,%rdi,4),%rdx\nmov %ecx,(%rax)\nadd $0x4,%rax\ncmp %rdx,%rax\njne 11d4 \nretq\n", + "ida_asm": "func0:\nendbr64\nmov r10, rdx\nmov edx, [rdi]\ntest esi, esi\njle short locret_11DC\nmov rax, rdi\nmovsxd rsi, esi\nlea r8, [rdi+rsi*4]\nmov ecx, 0\nloc_1185:\ncmp [rdi], edx\nsetz sil\nmovzx esi, sil\nadd ecx, esi\nadd rdi, 4\ncmp rdi, r8\njnz short loc_1185\nmov edi, 0\njmp short loc_11AA\nloc_11A1:\nadd rax, 4\ncmp rax, r8\njz short loc_11BC\nloc_11AA:\nmov esi, [rax]\ncmp esi, edx\njz short loc_11A1\nmovsxd r9, edi\nmov [r10+r9*4], esi\nlea edi, [rdi+1]\njmp short loc_11A1\nloc_11BC:\ntest ecx, ecx\njle short locret_11DC\nmovsxd rdi, edi\nlea rax, [r10+rdi*4]\nmovsxd rcx, ecx\nadd rcx, rdi\nlea rcx, [r10+rcx*4]\nloc_11D1:\nmov [rax], edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_11D1\nlocret_11DC:\nretn", + "ida_pseudo": "void __fastcall func0(_DWORD *a1, int a2, __int64 a3)\n{\n int v4; // edx\n _DWORD *v5; // rax\n _DWORD *v6; // r8\n int v7; // ecx\n int v8; // edi\n _DWORD *v9; // rax\n _DWORD *v10; // rcx\n\n v4 = *a1;\n if ( a2 > 0 )\n {\n v5 = a1;\n v6 = &a1[a2];\n v7 = 0;\n do\n v7 += *a1++ == v4;\n while ( a1 != v6 );\n v8 = 0;\n do\n {\n if ( *v5 != v4 )\n *(_DWORD *)(a3 + 4LL * v8++) = *v5;\n ++v5;\n }\n while ( v5 != v6 );\n if ( v7 > 0 )\n {\n v9 = (_DWORD *)(a3 + 4LL * v8);\n v10 = (_DWORD *)(a3 + 4 * (v8 + (__int64)v7));\n do\n *v9++ = v4;\n while ( v9 != v10 );\n }\n }\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov r10, rdx\nmov edx, [rdi]\ntest esi, esi\njle short locret_11DC\nmov rax, rdi\nmovsxd rsi, esi\nlea r8, [rdi+rsi*4]\nmov ecx, 0\nloc_1185:\ncmp [rdi], edx\nsetz sil\nmovzx esi, sil\nadd ecx, esi\nadd rdi, 4\ncmp rdi, r8\njnz short loc_1185\nmov edi, 0\njmp short loc_11AA\nloc_11A1:\nadd rax, 4\ncmp rax, r8\njz short loc_11BC\nloc_11AA:\nmov esi, [rax]\ncmp esi, edx\njz short loc_11A1\nmovsxd r9, edi\nmov [r10+r9*4], esi\nlea edi, [rdi+1]\njmp short loc_11A1\nloc_11BC:\ntest ecx, ecx\njle short locret_11DC\nmovsxd rdi, edi\nlea rax, [r10+rdi*4]\nmovsxd rcx, ecx\nadd rcx, rdi\nlea rcx, [r10+rcx*4]\nloc_11D1:\nmov [rax], edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_11D1\nlocret_11DC:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1169(_DWORD *a1, int a2, __int64 a3)\n{\n int v4; // edx\n _DWORD *v5; // rax\n _DWORD *v6; // r8\n int v7; // ecx\n int v8; // edi\n _DWORD *v9; // rax\n _DWORD *v10; // rcx\n\n v4 = *a1;\n if ( a2 > 0 )\n {\n v5 = a1;\n v6 = &a1[a2];\n v7 = 0;\n do\n v7 += *a1++ == v4;\n while ( a1 != v6 );\n v8 = 0;\n do\n {\n if ( *v5 != v4 )\n *(_DWORD *)(a3 + 4LL * v8++) = *v5;\n ++v5;\n }\n while ( v5 != v6 );\n if ( v7 > 0 )\n {\n v9 = (_DWORD *)(a3 + 4LL * v8);\n v10 = (_DWORD *)(a3 + 4 * (v8 + (__int64)v7));\n do\n *v9++ = v4;\n while ( v9 != v10 );\n }\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1169(uint32_t *a1, int a2, long long a3) {\n int v4;\n uint32_t *v5;\n uint32_t *v6;\n int v7;\n int v8;\n uint32_t *v9;\n uint32_t *v10;\n v4 = *a1;\n if (a2 > 0) {\n v5 = a1;\n v6 = &a1[a2];\n v7 = 0;\n do\n v7 += *a1++ == v4;\n while (a1 != v6);\n v8 = 0;\n do {\n if (*v5 != v4) *(uint32_t *)(a3 + 4LL * v8++) = *v5;\n ++v5;\n } while (v5 != v6);\n if (v7 > 0) {\n v9 = (uint32_t *)(a3 + 4LL * v8);\n v10 = (uint32_t *)(a3 + 4 * (v8 + (long long)v7));\n do\n *v9++ = v4;\n while (v9 != v10);\n }\n }\n}", + "ida_pseudo_norm": "void func0(uint32_t *a1, int a2, long long a3) {\n int v4;\n uint32_t *v5;\n uint32_t *v6;\n int v7;\n int v8;\n uint32_t *v9;\n uint32_t *v10;\n v4 = *a1;\n if (a2 > 0) {\n v5 = a1;\n v6 = &a1[a2];\n v7 = 0;\n do\n v7 += *a1++ == v4;\n while (a1 != v6);\n v8 = 0;\n do {\n if (*v5 != v4) *(uint32_t *)(a3 + 4LL * v8++) = *v5;\n ++v5;\n } while (v5 != v6);\n if (v7 > 0) {\n v9 = (uint32_t *)(a3 + 4LL * v8);\n v10 = (uint32_t *)(a3 + 4 * (v8 + (long long)v7));\n do\n *v9++ = v4;\n while (v9 != v10);\n }\n }\n}" + }, + { + "index": 665, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int *num_list, int n, int *output) {\n int first_element = num_list[0];\n int count_first = 0;\n int output_index = 0;\n for (int i = 0; i < n; i++) {\n if (num_list[i] == first_element) {\n count_first++;\n }\n }\n for (int i = 0; i < n; i++) {\n if (num_list[i] != first_element) {\n output[output_index++] = num_list[i];\n }\n }\n for (int i = 0; i < count_first; i++) {\n output[output_index++] = first_element;\n }\n}", + "test": "int main() {\n\n int test1[] = {1, 2, 3, 4};\n\n int result1[4];\n\n func0(test1, 4, result1);\n\n assert(result1[0] == 2 && result1[1] == 3 && result1[2] == 4 && result1[3] == 1);\n\n\n\n int test2[] = {2, 3, 4, 1, 5, 0};\n\n int result2[6];\n\n func0(test2, 6, result2);\n\n assert(result2[0] == 3 && result2[1] == 4 && result2[2] == 1 && result2[3] == 5 && result2[4] == 0 && result2[5] == 2);\n\n\n\n int test3[] = {5, 4, 3, 2, 1};\n\n int result3[5];\n\n func0(test3, 5, result3);\n\n assert(result3[0] == 4 && result3[1] == 3 && result3[2] == 2 && result3[3] == 1 && result3[4] == 5);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov (%rdi),%ecx\ntest %esi,%esi\njle 13e3 \nlea -0x1(%rsi),%eax\nadd $0x4,%rdi\nmov %ecx,%esi\nxor %r9d,%r9d\nlea (%rdi,%rax,4),%r8\nmov %rdi,%rax\njmp 1386 \nmov (%rax),%esi\nadd $0x4,%rax\ncmp %ecx,%esi\nsete %sil\nmovzbl %sil,%esi\nadd %esi,%r9d\ncmp %r8,%rax\njne 1380 \nxor %esi,%esi\njmp 13b6 \nnopl 0x0(%rax)\nmov (%rdi),%r8d\ncmp %ecx,%r8d\nje 13b2 \nmovslq %esi,%r10\nadd $0x1,%esi\nmov %r8d,(%rdx,%r10,4)\nadd $0x4,%rdi\ncmp %rax,%rdi\njne 13a0 \ntest %r9d,%r9d\nje 13e3 \nmovslq %esi,%rsi\nlea -0x1(%r9),%edi\nlea (%rdx,%rsi,4),%rax\nadd %rdi,%rsi\nlea 0x4(%rdx,%rsi,4),%rdx\nnopl 0x0(%rax,%rax,1)\nmov %ecx,(%rax)\nadd $0x4,%rax\ncmp %rax,%rdx\njne 13d8 \nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\nmov r10, rdx\nmov edx, [rdi]\ntest esi, esi\njle locret_13AE\nmovsxd rsi, esi\nmov rax, rdi\nxor ecx, ecx\nlea r8, [rdi+rsi*4]\nnop dword ptr [rax]\nloc_1340:\nxor esi, esi\ncmp edx, [rax]\nsetz sil\nadd rax, 4\nadd ecx, esi\ncmp rax, r8\njnz short loc_1340\nxor esi, esi\nnop dword ptr [rax]\nloc_1358:\nmov eax, [rdi]\ncmp eax, edx\njz short loc_1368\nmovsxd r9, esi\nadd esi, 1\nmov [r10+r9*4], eax\nloc_1368:\nadd rdi, 4\ncmp rdi, r8\njnz short loc_1358\ntest ecx, ecx\njle short locret_13AE\nmovsxd rsi, esi\nmovsxd rcx, ecx\nadd rcx, rsi\nlea rax, [r10+rsi*4]\nlea rcx, [r10+rcx*4]\nmov rsi, rcx\nsub rsi, rax\nand esi, 4\njz short loc_13A0\nmov [rax], edx\nadd rax, 4\ncmp rcx, rax\njz short locret_13AF\nnop dword ptr [rax+00h]\nloc_13A0:\nmov [rax], edx\nadd rax, 8\nmov [rax-4], edx\ncmp rcx, rax\njnz short loc_13A0\nlocret_13AE:\nretn\nlocret_13AF:\nretn", + "ida_pseudo": "void __fastcall func0(_DWORD *a1, int a2, __int64 a3)\n{\n int v4; // edx\n _DWORD *v5; // rax\n int v6; // ecx\n _DWORD *v7; // r8\n int v8; // esi\n int v9; // esi\n __int64 v10; // r9\n _DWORD *v11; // rax\n _DWORD *v12; // rcx\n\n v4 = *a1;\n if ( a2 > 0 )\n {\n v5 = a1;\n v6 = 0;\n v7 = &a1[a2];\n do\n {\n v8 = v4 == *v5++;\n v6 += v8;\n }\n while ( v5 != v7 );\n v9 = 0;\n do\n {\n if ( *a1 != v4 )\n {\n v10 = v9++;\n *(_DWORD *)(a3 + 4 * v10) = *a1;\n }\n ++a1;\n }\n while ( a1 != v7 );\n if ( v6 > 0 )\n {\n v11 = (_DWORD *)(a3 + 4LL * v9);\n v12 = (_DWORD *)(a3 + 4 * (v9 + (__int64)v6));\n if ( (((_BYTE)v12 - (_BYTE)v11) & 4) == 0 || (*v11 = v4, ++v11, v12 != v11) )\n {\n do\n {\n *v11 = v4;\n v11 += 2;\n *(v11 - 1) = v4;\n }\n while ( v12 != v11 );\n }\n }\n }\n}", + "ida_strip_asm": "sub_1320:\nendbr64\nmov r10, rdx\nmov edx, [rdi]\ntest esi, esi\njle locret_13AE\nmovsxd rsi, esi\nmov rax, rdi\nxor ecx, ecx\nlea r8, [rdi+rsi*4]\nnop dword ptr [rax]\nloc_1340:\nxor esi, esi\ncmp edx, [rax]\nsetz sil\nadd rax, 4\nadd ecx, esi\ncmp rax, r8\njnz short loc_1340\nxor esi, esi\nnop dword ptr [rax]\nloc_1358:\nmov eax, [rdi]\ncmp eax, edx\njz short loc_1368\nmovsxd r9, esi\nadd esi, 1\nmov [r10+r9*4], eax\nloc_1368:\nadd rdi, 4\ncmp rdi, r8\njnz short loc_1358\ntest ecx, ecx\njle short locret_13AE\nmovsxd rsi, esi\nmovsxd rcx, ecx\nadd rcx, rsi\nlea rax, [r10+rsi*4]\nlea rcx, [r10+rcx*4]\nmov rsi, rcx\nsub rsi, rax\nand esi, 4\njz short loc_13A0\nmov [rax], edx\nadd rax, 4\ncmp rcx, rax\njz short locret_13AF\nnop dword ptr [rax+00h]\nloc_13A0:\nmov [rax], edx\nadd rax, 8\nmov [rax-4], edx\ncmp rcx, rax\njnz short loc_13A0\nlocret_13AE:\nretn\nlocret_13AF:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1320(_DWORD *a1, int a2, __int64 a3)\n{\n int v4; // edx\n _DWORD *v5; // rax\n int v6; // ecx\n _DWORD *v7; // r8\n int v8; // esi\n int v9; // esi\n __int64 v10; // r9\n _DWORD *v11; // rax\n _DWORD *v12; // rcx\n\n v4 = *a1;\n if ( a2 > 0 )\n {\n v5 = a1;\n v6 = 0;\n v7 = &a1[a2];\n do\n {\n v8 = v4 == *v5++;\n v6 += v8;\n }\n while ( v5 != v7 );\n v9 = 0;\n do\n {\n if ( *a1 != v4 )\n {\n v10 = v9++;\n *(_DWORD *)(a3 + 4 * v10) = *a1;\n }\n ++a1;\n }\n while ( a1 != v7 );\n if ( v6 > 0 )\n {\n v11 = (_DWORD *)(a3 + 4LL * v9);\n v12 = (_DWORD *)(a3 + 4 * (v9 + (__int64)v6));\n if ( (((_BYTE)v12 - (_BYTE)v11) & 4) == 0 || (*v11 = v4, ++v11, v12 != v11) )\n {\n do\n {\n *v11 = v4;\n v11 += 2;\n *(v11 - 1) = v4;\n }\n while ( v12 != v11 );\n }\n }\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1320(uint32_t *a1, int a2, long long a3) {\n int v4;\n uint32_t *v5;\n int v6;\n uint32_t *v7;\n int v8;\n int v9;\n long long v10;\n uint32_t *v11;\n uint32_t *v12;\n v4 = *a1;\n if (a2 > 0) {\n v5 = a1;\n v6 = 0;\n v7 = &a1[a2];\n do {\n v8 = v4 == *v5++;\n v6 += v8;\n } while (v5 != v7);\n v9 = 0;\n do {\n if (*a1 != v4) {\n v10 = v9++;\n *(uint32_t *)(a3 + 4 * v10) = *a1;\n }\n ++a1;\n } while (a1 != v7);\n if (v6 > 0) {\n v11 = (uint32_t *)(a3 + 4LL * v9);\n v12 = (uint32_t *)(a3 + 4 * (v9 + (long long)v6));\n if ((((uint8_t)v12 - (uint8_t)v11) & 4) == 0 ||\n (*v11 = v4, ++v11, v12 != v11)) {\n do {\n *v11 = v4;\n v11 += 2;\n *(v11 - 1) = v4;\n } while (v12 != v11);\n }\n }\n }\n}", + "ida_pseudo_norm": "void func0(uint32_t *a1, int a2, long long a3) {\n int v4;\n uint32_t *v5;\n int v6;\n uint32_t *v7;\n int v8;\n int v9;\n long long v10;\n uint32_t *v11;\n uint32_t *v12;\n v4 = *a1;\n if (a2 > 0) {\n v5 = a1;\n v6 = 0;\n v7 = &a1[a2];\n do {\n v8 = v4 == *v5++;\n v6 += v8;\n } while (v5 != v7);\n v9 = 0;\n do {\n if (*a1 != v4) {\n v10 = v9++;\n *(uint32_t *)(a3 + 4 * v10) = *a1;\n }\n ++a1;\n } while (a1 != v7);\n if (v6 > 0) {\n v11 = (uint32_t *)(a3 + 4LL * v9);\n v12 = (uint32_t *)(a3 + 4 * (v9 + (long long)v6));\n if ((((uint8_t)v12 - (uint8_t)v11) & 4) == 0 ||\n (*v11 = v4, ++v11, v12 != v11)) {\n do {\n *v11 = v4;\n v11 += 2;\n *(v11 - 1) = v4;\n } while (v12 != v11);\n }\n }\n }\n}" + }, + { + "index": 665, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int *num_list, int n, int *output) {\n int first_element = num_list[0];\n int count_first = 0;\n int output_index = 0;\n for (int i = 0; i < n; i++) {\n if (num_list[i] == first_element) {\n count_first++;\n }\n }\n for (int i = 0; i < n; i++) {\n if (num_list[i] != first_element) {\n output[output_index++] = num_list[i];\n }\n }\n for (int i = 0; i < count_first; i++) {\n output[output_index++] = first_element;\n }\n}", + "test": "int main() {\n\n int test1[] = {1, 2, 3, 4};\n\n int result1[4];\n\n func0(test1, 4, result1);\n\n assert(result1[0] == 2 && result1[1] == 3 && result1[2] == 4 && result1[3] == 1);\n\n\n\n int test2[] = {2, 3, 4, 1, 5, 0};\n\n int result2[6];\n\n func0(test2, 6, result2);\n\n assert(result2[0] == 3 && result2[1] == 4 && result2[2] == 1 && result2[3] == 5 && result2[4] == 0 && result2[5] == 2);\n\n\n\n int test3[] = {5, 4, 3, 2, 1};\n\n int result3[5];\n\n func0(test3, 5, result3);\n\n assert(result3[0] == 4 && result3[1] == 3 && result3[2] == 2 && result3[3] == 1 && result3[4] == 5);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nmov (%rdi),%r9d\ntest %esi,%esi\njle 1497 \nlea -0x1(%rsi),%eax\ncmp $0x3,%eax\njbe 14a9 \nmov %esi,%ecx\nmovd %r9d,%xmm3\npxor %xmm1,%xmm1\nmov %rdi,%rax\nshr $0x2,%ecx\npshufd $0x0,%xmm3,%xmm2\nshl $0x4,%rcx\nadd %rdi,%rcx\nnopl 0x0(%rax,%rax,1)\nmovdqu (%rax),%xmm0\nadd $0x10,%rax\npcmpeqd %xmm2,%xmm0\npsubd %xmm0,%xmm1\ncmp %rcx,%rax\njne 1360 \nmovdqa %xmm1,%xmm0\nmov %esi,%eax\npsrldq $0x8,%xmm0\nand $0xfffffffc,%eax\npaddd %xmm0,%xmm1\nmovdqa %xmm1,%xmm0\npsrldq $0x4,%xmm0\npaddd %xmm0,%xmm1\nmovd %xmm1,%r8d\ntest $0x3,%sil\nje 13eb \nmovslq %eax,%rcx\ncmp %r9d,(%rdi,%rcx,4)\nje 14ae \nlea 0x1(%rax),%ecx\ncmp %esi,%ecx\njge 14e9 \nmovslq %ecx,%rcx\ncmp %r9d,(%rdi,%rcx,4)\nje 14a0 \nlea 0x2(%rax),%ecx\ncmp %ecx,%esi\njle 13eb \nmovslq %ecx,%rcx\ncmp (%rdi,%rcx,4),%r9d\nje 14c8 \nadd $0x3,%eax\ncmp %eax,%esi\njle 13eb \ncltq\ncmp (%rdi,%rax,4),%r9d\nje 14e0 \nlea -0x2(%rsi),%ecx\nlea 0x4(%rdi),%rax\nlea 0x8(%rdi,%rcx,4),%r10\nxor %ecx,%ecx\nnopl 0x0(%rax)\nmov (%rax),%esi\ncmp %r9d,%esi\nje 1410 \nmovslq %ecx,%rdi\nadd $0x1,%ecx\nmov %esi,(%rdx,%rdi,4)\nadd $0x4,%rax\ncmp %r10,%rax\njne 1400 \ntest %r8d,%r8d\njle 1497 \nlea -0x1(%r8),%eax\ncmp $0x2,%eax\njbe 14f9 \nmov %r8d,%esi\nmovslq %ecx,%rax\nmovd %r9d,%xmm4\nshr $0x2,%esi\nlea (%rdx,%rax,4),%rax\npshufd $0x0,%xmm4,%xmm0\nshl $0x4,%rsi\nadd %rax,%rsi\nnopl 0x0(%rax)\nmovups %xmm0,(%rax)\nadd $0x10,%rax\ncmp %rsi,%rax\njne 1450 \nmov %r8d,%eax\nand $0xfffffffc,%eax\nadd %eax,%ecx\ncmp %eax,%r8d\nje 14c0 \nlea 0x1(%rcx),%esi\nmovslq %ecx,%rcx\nmov %r9d,(%rdx,%rcx,4)\nlea 0x1(%rax),%ecx\ncmp %r8d,%ecx\njge 1497 \nmovslq %esi,%rcx\nadd $0x2,%eax\nmov %r9d,(%rdx,%rcx,4)\nlea 0x0(,%rcx,4),%rsi\ncmp %r8d,%eax\njge 1497 \nmov %r9d,0x4(%rdx,%rsi,1)\nretq\nnopl 0x0(%rax,%rax,1)\nadd $0x1,%r8d\njmpq 13c4 \nxor %eax,%eax\nxor %r8d,%r8d\nadd $0x1,%r8d\njmpq 13ac \nnopw 0x0(%rax,%rax,1)\nretq\nnopl 0x0(%rax)\nadd $0x3,%eax\nadd $0x1,%r8d\ncmp %eax,%esi\njg 13df \njmpq 13eb \nnopl 0x0(%rax)\nadd $0x1,%r8d\njmpq 13eb \nxor %ecx,%ecx\ncmp $0x1,%esi\nje 1419 \njmpq 13eb \nxor %eax,%eax\njmpq 1469 \n", + "ida_asm": "func0:\nendbr64\nmov rax, rdi\nmov r8d, esi\nmov edi, [rdi]\nmov r9, rdx\ntest esi, esi\njle locret_1484\nlea edx, [rsi-1]\ncmp edx, 2\njbe loc_1490\nmov ecx, esi\nmovd xmm3, edi\npxor xmm1, xmm1\nmov rdx, rax\nshr ecx, 2\npshufd xmm2, xmm3, 0\nshl rcx, 4\nadd rcx, rax\nnop\nloc_1360:\nmovdqu xmm0, xmmword ptr [rdx]\nadd rdx, 10h\npcmpeqd xmm0, xmm2\npsubd xmm1, xmm0\ncmp rdx, rcx\njnz short loc_1360\nmovdqa xmm0, xmm1\nmov ecx, r8d\npsrldq xmm0, 8\nand ecx, 0FFFFFFFCh\npaddd xmm1, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm0, 4\npaddd xmm1, xmm0\nmovd esi, xmm1\ntest r8b, 3\njz short loc_13D9\nmovsxd r10, ecx\nlea rdx, ds:0[r10*4]\ncmp [rax+r10*4], edi\njz loc_1496\nloc_13B4:\nlea r10d, [rcx+1]\ncmp r8d, r10d\njle short loc_13D9\ncmp edi, [rax+rdx+4]\njz loc_1488\nloc_13C7:\nadd ecx, 2\ncmp r8d, ecx\njle short loc_13D9\ncmp edi, [rax+rdx+8]\njz loc_14A0\nloc_13D9:\nmovsxd rdx, r8d\nlea r10, [rax+rdx*4]\nxor edx, edx\nnop word ptr [rax+rax+00h]\nloc_13E8:\nmov ecx, [rax]\ncmp ecx, edi\njz short loc_13F8\nmovsxd r8, edx\nadd edx, 1\nmov [r9+r8*4], ecx\nloc_13F8:\nadd rax, 4\ncmp r10, rax\njnz short loc_13E8\ntest esi, esi\njle short locret_1484\nlea eax, [rsi-1]\ncmp eax, 2\njbe loc_14A8\nmov ecx, esi\nmovsxd rax, edx\nmovd xmm4, edi\nshr ecx, 2\nlea rax, [r9+rax*4]\npshufd xmm0, xmm4, 0\nshl rcx, 4\nlea r8, [rcx+rax]\nand ecx, 10h\njz short loc_1440\nmovups xmmword ptr [rax], xmm0\nadd rax, 10h\ncmp r8, rax\njz short loc_1450\nnop\nloc_1440:\nmovups xmmword ptr [rax], xmm0\nadd rax, 20h ; ' '\nmovups xmmword ptr [rax-10h], xmm0\ncmp r8, rax\njnz short loc_1440\nloc_1450:\nmov eax, esi\nand eax, 0FFFFFFFCh\nadd edx, eax\ntest sil, 3\njz short locret_1484\nloc_145D:\nmovsxd rdx, edx\nmov [r9+rdx*4], edi\nlea rcx, ds:0[rdx*4]\nlea edx, [rax+1]\ncmp edx, esi\njge short locret_1484\nadd eax, 2\nmov [r9+rcx+4], edi\ncmp eax, esi\njge short locret_1484\nmov [r9+rcx+8], edi\nlocret_1484:\nretn\nloc_1488:\nadd esi, 1\njmp loc_13C7\nloc_1490:\nxor ecx, ecx\nxor esi, esi\nxor edx, edx\nloc_1496:\nadd esi, 1\njmp loc_13B4\nloc_14A0:\nadd esi, 1\njmp loc_13D9\nloc_14A8:\nxor eax, eax\njmp short loc_145D", + "ida_pseudo": "const __m128i *__fastcall func0(unsigned int *a1, int a2, __int64 a3)\n{\n const __m128i *result; // rax\n unsigned int v5; // edi\n __m128i v7; // xmm1\n const __m128i *v8; // rdx\n __m128i v9; // xmm2\n __m128i v10; // xmm0\n signed int v11; // ecx\n __m128i v12; // xmm1\n int v13; // esi\n __int64 v14; // rdx\n const __m128i *v15; // r10\n int v16; // edx\n __int64 v17; // r8\n __m128i *v18; // rax\n __m128i v19; // xmm0\n __int64 v20; // rcx\n __m128i *v21; // r8\n __int64 v22; // rcx\n\n result = (const __m128i *)a1;\n v5 = *a1;\n if ( a2 <= 0 )\n return result;\n if ( (unsigned int)(a2 - 1) <= 2 )\n {\n v11 = 0;\n v13 = 0;\n v14 = 0LL;\nLABEL_28:\n ++v13;\n goto LABEL_7;\n }\n v7 = 0LL;\n v8 = result;\n v9 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v5), 0);\n do\n {\n v10 = _mm_loadu_si128(v8++);\n v7 = _mm_sub_epi32(v7, _mm_cmpeq_epi32(v10, v9));\n }\n while ( v8 != &result[(unsigned int)a2 >> 2] );\n v11 = a2 & 0xFFFFFFFC;\n v12 = _mm_add_epi32(v7, _mm_srli_si128(v7, 8));\n v13 = _mm_cvtsi128_si32(_mm_add_epi32(v12, _mm_srli_si128(v12, 4)));\n if ( (a2 & 3) == 0 )\n goto LABEL_13;\n v14 = v11;\n if ( result->m128i_i32[v14] == v5 )\n goto LABEL_28;\nLABEL_7:\n if ( a2 > v11 + 1 )\n {\n if ( v5 == result->m128i_i32[v14 + 1] )\n ++v13;\n if ( a2 > v11 + 2 && v5 == result->m128i_i32[v14 + 2] )\n ++v13;\n }\nLABEL_13:\n v15 = (const __m128i *)((char *)result + 4 * a2);\n v16 = 0;\n do\n {\n if ( result->m128i_i32[0] != v5 )\n {\n v17 = v16++;\n *(_DWORD *)(a3 + 4 * v17) = result->m128i_i32[0];\n }\n result = (const __m128i *)((char *)result + 4);\n }\n while ( v15 != result );\n if ( v13 > 0 )\n {\n if ( (unsigned int)(v13 - 1) <= 2 )\n {\n result = 0LL;\nLABEL_23:\n *(_DWORD *)(a3 + 4LL * v16) = v5;\n v22 = 4LL * v16;\n if ( (int)result + 1 < v13 )\n {\n result = (const __m128i *)(unsigned int)((_DWORD)result + 2);\n *(_DWORD *)(a3 + v22 + 4) = v5;\n if ( (int)result < v13 )\n *(_DWORD *)(a3 + v22 + 8) = v5;\n }\n return result;\n }\n v18 = (__m128i *)(a3 + 4LL * v16);\n v19 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v5), 0);\n v20 = (unsigned int)v13 >> 2;\n v21 = &v18[v20];\n if ( ((v20 * 16) & 0x10) == 0 || (*v18 = v19, ++v18, v21 != v18) )\n {\n do\n {\n *v18 = v19;\n v18 += 2;\n v18[-1] = v19;\n }\n while ( v21 != v18 );\n }\n result = (const __m128i *)(v13 & 0xFFFFFFFC);\n v16 += (int)result;\n if ( (v13 & 3) != 0 )\n goto LABEL_23;\n }\n return result;\n}", + "ida_strip_asm": "sub_1320:\nendbr64\nmov rax, rdi\nmov r8d, esi\nmov edi, [rdi]\nmov r9, rdx\ntest esi, esi\njle locret_1484\nlea edx, [rsi-1]\ncmp edx, 2\njbe loc_1490\nmov ecx, esi\nmovd xmm3, edi\npxor xmm1, xmm1\nmov rdx, rax\nshr ecx, 2\npshufd xmm2, xmm3, 0\nshl rcx, 4\nadd rcx, rax\nnop\nloc_1360:\nmovdqu xmm0, xmmword ptr [rdx]\nadd rdx, 10h\npcmpeqd xmm0, xmm2\npsubd xmm1, xmm0\ncmp rdx, rcx\njnz short loc_1360\nmovdqa xmm0, xmm1\nmov ecx, r8d\npsrldq xmm0, 8\nand ecx, 0FFFFFFFCh\npaddd xmm1, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm0, 4\npaddd xmm1, xmm0\nmovd esi, xmm1\ntest r8b, 3\njz short loc_13D9\nmovsxd r10, ecx\nlea rdx, ds:0[r10*4]\ncmp [rax+r10*4], edi\njz loc_1496\nloc_13B4:\nlea r10d, [rcx+1]\ncmp r8d, r10d\njle short loc_13D9\ncmp edi, [rax+rdx+4]\njz loc_1488\nloc_13C7:\nadd ecx, 2\ncmp r8d, ecx\njle short loc_13D9\ncmp edi, [rax+rdx+8]\njz loc_14A0\nloc_13D9:\nmovsxd rdx, r8d\nlea r10, [rax+rdx*4]\nxor edx, edx\nnop word ptr [rax+rax+00h]\nloc_13E8:\nmov ecx, [rax]\ncmp ecx, edi\njz short loc_13F8\nmovsxd r8, edx\nadd edx, 1\nmov [r9+r8*4], ecx\nloc_13F8:\nadd rax, 4\ncmp r10, rax\njnz short loc_13E8\ntest esi, esi\njle short locret_1484\nlea eax, [rsi-1]\ncmp eax, 2\njbe loc_14A8\nmov ecx, esi\nmovsxd rax, edx\nmovd xmm4, edi\nshr ecx, 2\nlea rax, [r9+rax*4]\npshufd xmm0, xmm4, 0\nshl rcx, 4\nlea r8, [rcx+rax]\nand ecx, 10h\njz short loc_1440\nmovups xmmword ptr [rax], xmm0\nadd rax, 10h\ncmp r8, rax\njz short loc_1450\nnop\nloc_1440:\nmovups xmmword ptr [rax], xmm0\nadd rax, 20h ; ' '\nmovups xmmword ptr [rax-10h], xmm0\ncmp r8, rax\njnz short loc_1440\nloc_1450:\nmov eax, esi\nand eax, 0FFFFFFFCh\nadd edx, eax\ntest sil, 3\njz short locret_1484\nloc_145D:\nmovsxd rdx, edx\nmov [r9+rdx*4], edi\nlea rcx, ds:0[rdx*4]\nlea edx, [rax+1]\ncmp edx, esi\njge short locret_1484\nadd eax, 2\nmov [r9+rcx+4], edi\ncmp eax, esi\njge short locret_1484\nmov [r9+rcx+8], edi\nlocret_1484:\nretn\nloc_1488:\nadd esi, 1\njmp loc_13C7\nloc_1490:\nxor ecx, ecx\nxor esi, esi\nxor edx, edx\nloc_1496:\nadd esi, 1\njmp loc_13B4\nloc_14A0:\nadd esi, 1\njmp loc_13D9\nloc_14A8:\nxor eax, eax\njmp short loc_145D", + "ida_strip_pseudo": "const __m128i *__fastcall sub_1320(unsigned int *a1, int a2, __int64 a3)\n{\n const __m128i *result; // rax\n unsigned int v5; // edi\n __m128i v7; // xmm1\n const __m128i *v8; // rdx\n __m128i v9; // xmm2\n __m128i v10; // xmm0\n signed int v11; // ecx\n __m128i v12; // xmm1\n int v13; // esi\n __int64 v14; // rdx\n const __m128i *v15; // r10\n int v16; // edx\n __int64 v17; // r8\n __m128i *v18; // rax\n __m128i v19; // xmm0\n __int64 v20; // rcx\n __m128i *v21; // r8\n __int64 v22; // rcx\n\n result = (const __m128i *)a1;\n v5 = *a1;\n if ( a2 <= 0 )\n return result;\n if ( (unsigned int)(a2 - 1) <= 2 )\n {\n v11 = 0;\n v13 = 0;\n v14 = 0LL;\nLABEL_28:\n ++v13;\n goto LABEL_7;\n }\n v7 = 0LL;\n v8 = result;\n v9 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v5), 0);\n do\n {\n v10 = _mm_loadu_si128(v8++);\n v7 = _mm_sub_epi32(v7, _mm_cmpeq_epi32(v10, v9));\n }\n while ( v8 != &result[(unsigned int)a2 >> 2] );\n v11 = a2 & 0xFFFFFFFC;\n v12 = _mm_add_epi32(v7, _mm_srli_si128(v7, 8));\n v13 = _mm_cvtsi128_si32(_mm_add_epi32(v12, _mm_srli_si128(v12, 4)));\n if ( (a2 & 3) == 0 )\n goto LABEL_13;\n v14 = v11;\n if ( result->m128i_i32[v14] == v5 )\n goto LABEL_28;\nLABEL_7:\n if ( a2 > v11 + 1 )\n {\n if ( v5 == result->m128i_i32[v14 + 1] )\n ++v13;\n if ( a2 > v11 + 2 && v5 == result->m128i_i32[v14 + 2] )\n ++v13;\n }\nLABEL_13:\n v15 = (const __m128i *)((char *)result + 4 * a2);\n v16 = 0;\n do\n {\n if ( result->m128i_i32[0] != v5 )\n {\n v17 = v16++;\n *(_DWORD *)(a3 + 4 * v17) = result->m128i_i32[0];\n }\n result = (const __m128i *)((char *)result + 4);\n }\n while ( v15 != result );\n if ( v13 > 0 )\n {\n if ( (unsigned int)(v13 - 1) <= 2 )\n {\n result = 0LL;\nLABEL_23:\n *(_DWORD *)(a3 + 4LL * v16) = v5;\n v22 = 4LL * v16;\n if ( (int)result + 1 < v13 )\n {\n result = (const __m128i *)(unsigned int)((_DWORD)result + 2);\n *(_DWORD *)(a3 + v22 + 4) = v5;\n if ( (int)result < v13 )\n *(_DWORD *)(a3 + v22 + 8) = v5;\n }\n return result;\n }\n v18 = (__m128i *)(a3 + 4LL * v16);\n v19 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v5), 0);\n v20 = (unsigned int)v13 >> 2;\n v21 = &v18[v20];\n if ( ((v20 * 16) & 0x10) == 0 || (*v18 = v19, ++v18, v21 != v18) )\n {\n do\n {\n *v18 = v19;\n v18 += 2;\n v18[-1] = v19;\n }\n while ( v21 != v18 );\n }\n result = (const __m128i *)(v13 & 0xFFFFFFFC);\n v16 += (int)result;\n if ( (v13 & 3) != 0 )\n goto LABEL_23;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const __m128i *sub_1320(unsigned int *a1, int a2, long long a3) {\n const __m128i *result;\n unsigned int v5;\n __m128i v7;\n const __m128i *v8;\n __m128i v9;\n __m128i v10;\n signed int v11;\n __m128i v12;\n int v13;\n long long v14;\n const __m128i *v15;\n int v16;\n long long v17;\n __m128i *v18;\n __m128i v19;\n long long v20;\n __m128i *v21;\n long long v22;\n result = (const __m128i *)a1;\n v5 = *a1;\n if (a2 <= 0) return result;\n if ((unsigned int)(a2 - 1) <= 2) {\n v11 = 0;\n v13 = 0;\n v14 = 0LL;\n LABEL_28:\n ++v13;\n goto LABEL_7;\n }\n v7 = 0LL;\n v8 = result;\n v9 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v5), 0);\n do {\n v10 = _mm_loadu_si128(v8++);\n v7 = _mm_sub_epi32(v7, _mm_cmpeq_epi32(v10, v9));\n } while (v8 != &result[(unsigned int)a2 >> 2]);\n v11 = a2 & 4294967292;\n v12 = _mm_add_epi32(v7, _mm_srli_si128(v7, 8));\n v13 = _mm_cvtsi128_si32(_mm_add_epi32(v12, _mm_srli_si128(v12, 4)));\n if ((a2 & 3) == 0) goto LABEL_13;\n v14 = v11;\n if (result->m128i_i32[v14] == v5) goto LABEL_28;\nLABEL_7:\n if (a2 > v11 + 1) {\n if (v5 == result->m128i_i32[v14 + 1]) ++v13;\n if (a2 > v11 + 2 && v5 == result->m128i_i32[v14 + 2]) ++v13;\n }\nLABEL_13:\n v15 = (const __m128i *)((char *)result + 4 * a2);\n v16 = 0;\n do {\n if (result->m128i_i32[0] != v5) {\n v17 = v16++;\n *(uint32_t *)(a3 + 4 * v17) = result->m128i_i32[0];\n }\n result = (const __m128i *)((char *)result + 4);\n } while (v15 != result);\n if (v13 > 0) {\n if ((unsigned int)(v13 - 1) <= 2) {\n result = 0LL;\n LABEL_23:\n *(uint32_t *)(a3 + 4LL * v16) = v5;\n v22 = 4LL * v16;\n if ((int)result + 1 < v13) {\n result = (const __m128i *)(unsigned int)((uint32_t)result + 2);\n *(uint32_t *)(a3 + v22 + 4) = v5;\n if ((int)result < v13) *(uint32_t *)(a3 + v22 + 8) = v5;\n }\n return result;\n }\n v18 = (__m128i *)(a3 + 4LL * v16);\n v19 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v5), 0);\n v20 = (unsigned int)v13 >> 2;\n v21 = &v18[v20];\n if (((v20 * 16) & 16) == 0 || (*v18 = v19, ++v18, v21 != v18)) {\n do {\n *v18 = v19;\n v18 += 2;\n v18[-1] = v19;\n } while (v21 != v18);\n }\n result = (const __m128i *)(v13 & 4294967292);\n v16 += (int)result;\n if ((v13 & 3) != 0) goto LABEL_23;\n }\n return result;\n}", + "ida_pseudo_norm": "const __m128i *func0(unsigned int *a1, int a2, long long a3) {\n const __m128i *result;\n unsigned int v5;\n __m128i v7;\n const __m128i *v8;\n __m128i v9;\n __m128i v10;\n signed int v11;\n __m128i v12;\n int v13;\n long long v14;\n const __m128i *v15;\n int v16;\n long long v17;\n __m128i *v18;\n __m128i v19;\n long long v20;\n __m128i *v21;\n long long v22;\n result = (const __m128i *)a1;\n v5 = *a1;\n if (a2 <= 0) return result;\n if ((unsigned int)(a2 - 1) <= 2) {\n v11 = 0;\n v13 = 0;\n v14 = 0LL;\n LABEL_28:\n ++v13;\n goto LABEL_7;\n }\n v7 = 0LL;\n v8 = result;\n v9 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v5), 0);\n do {\n v10 = _mm_loadu_si128(v8++);\n v7 = _mm_sub_epi32(v7, _mm_cmpeq_epi32(v10, v9));\n } while (v8 != &result[(unsigned int)a2 >> 2]);\n v11 = a2 & 4294967292;\n v12 = _mm_add_epi32(v7, _mm_srli_si128(v7, 8));\n v13 = _mm_cvtsi128_si32(_mm_add_epi32(v12, _mm_srli_si128(v12, 4)));\n if ((a2 & 3) == 0) goto LABEL_13;\n v14 = v11;\n if (result->m128i_i32[v14] == v5) goto LABEL_28;\nLABEL_7:\n if (a2 > v11 + 1) {\n if (v5 == result->m128i_i32[v14 + 1]) ++v13;\n if (a2 > v11 + 2 && v5 == result->m128i_i32[v14 + 2]) ++v13;\n }\nLABEL_13:\n v15 = (const __m128i *)((char *)result + 4 * a2);\n v16 = 0;\n do {\n if (result->m128i_i32[0] != v5) {\n v17 = v16++;\n *(uint32_t *)(a3 + 4 * v17) = result->m128i_i32[0];\n }\n result = (const __m128i *)((char *)result + 4);\n } while (v15 != result);\n if (v13 > 0) {\n if ((unsigned int)(v13 - 1) <= 2) {\n result = 0LL;\n LABEL_23:\n *(uint32_t *)(a3 + 4LL * v16) = v5;\n v22 = 4LL * v16;\n if ((int)result + 1 < v13) {\n result = (const __m128i *)(unsigned int)((uint32_t)result + 2);\n *(uint32_t *)(a3 + v22 + 4) = v5;\n if ((int)result < v13) *(uint32_t *)(a3 + v22 + 8) = v5;\n }\n return result;\n }\n v18 = (__m128i *)(a3 + 4LL * v16);\n v19 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v5), 0);\n v20 = (unsigned int)v13 >> 2;\n v21 = &v18[v20];\n if (((v20 * 16) & 16) == 0 || (*v18 = v19, ++v18, v21 != v18)) {\n do {\n *v18 = v19;\n v18 += 2;\n v18[-1] = v19;\n } while (v21 != v18);\n }\n result = (const __m128i *)(v13 & 4294967292);\n v16 += (int)result;\n if ((v13 & 3) != 0) goto LABEL_23;\n }\n return result;\n}" + }, + { + "index": 666, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *string, char c) {\n int count = 0;\n for (int i = 0; i < strlen(string); i++) {\n if (string[i] == c) {\n count++;\n }\n }\n return count;\n}", + "test": "int main() {\n\n assert(func0(\"Python\", 'o') == 1);\n\n assert(func0(\"little\", 't') == 2);\n\n assert(func0(\"assert\", 's') == 2);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x28,%rsp\nmov %rdi,-0x28(%rbp)\nmov %esi,%eax\nmov %al,-0x2c(%rbp)\nmovl $0x0,-0x18(%rbp)\nmovl $0x0,-0x14(%rbp)\njmp 11ac \nmov -0x14(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp %al,-0x2c(%rbp)\njne 11a8 \naddl $0x1,-0x18(%rbp)\naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\nmovslq %eax,%rbx\nmov -0x28(%rbp),%rax\nmov %rax,%rdi\ncallq 1060 \ncmp %rax,%rbx\njb 118f \nmov -0x18(%rbp),%eax\nadd $0x28,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+s], rdi\nmov eax, esi\nmov [rbp+var_2C], al\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp short loc_11AC\nloc_118F:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp [rbp+var_2C], al\njnz short loc_11A8\nadd [rbp+var_18], 1\nloc_11A8:\nadd [rbp+var_14], 1\nloc_11AC:\nmov eax, [rbp+var_14]\nmovsxd rbx, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rbx, rax\njb short loc_118F\nmov eax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, char a2)\n{\n unsigned int v3; // [rsp+18h] [rbp-18h]\n int i; // [rsp+1Ch] [rbp-14h]\n\n v3 = 0;\n for ( i = 0; i < strlen(a1); ++i )\n {\n if ( a2 == a1[i] )\n ++v3;\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+s], rdi\nmov eax, esi\nmov [rbp+var_2C], al\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp short loc_11AC\nloc_118F:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp [rbp+var_2C], al\njnz short loc_11A8\nadd [rbp+var_18], 1\nloc_11A8:\nadd [rbp+var_14], 1\nloc_11AC:\nmov eax, [rbp+var_14]\nmovsxd rbx, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rbx, rax\njb short loc_118F\nmov eax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1, char a2)\n{\n unsigned int v3; // [rsp+18h] [rbp-18h]\n int i; // [rsp+1Ch] [rbp-14h]\n\n v3 = 0;\n for ( i = 0; i < strlen(a1); ++i )\n {\n if ( a2 == a1[i] )\n ++v3;\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1, char a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < strlen(a1); ++i) {\n if (a2 == a1[i]) ++v3;\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, char a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < strlen(a1); ++i) {\n if (a2 == a1[i]) ++v3;\n }\n return v3;\n}" + }, + { + "index": 666, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *string, char c) {\n int count = 0;\n for (int i = 0; i < strlen(string); i++) {\n if (string[i] == c) {\n count++;\n }\n }\n return count;\n}", + "test": "int main() {\n\n assert(func0(\"Python\", 'o') == 1);\n\n assert(func0(\"little\", 't') == 2);\n\n assert(func0(\"assert\", 's') == 2);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%r8\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nmov %r8,%rdx\nlea -0x1(%r8,%rcx,1),%rdi\nmov $0x0,%eax\ncmp %rdi,%rdx\nje 1184 \ncmp %sil,(%rdx)\nsete %cl\nmovzbl %cl,%ecx\nadd %ecx,%eax\nadd $0x1,%rdx\njmp 116e \nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov ebp, esi\ncall _strlen\nmov rdi, rax\nmov rax, rbx\nadd rdi, rbx\nmov edx, 0\njmp short loc_119C\nloc_118D:\ncmp [rax], bpl\nsetz cl\nmovzx ecx, cl\nadd edx, ecx\nadd rax, 1\nloc_119C:\ncmp rax, rdi\njnz short loc_118D\nmov eax, edx\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, unsigned __int8 a2)\n{\n size_t v3; // rdi\n const char *v4; // rax\n const char *v5; // rdi\n unsigned int v6; // edx\n\n v3 = strlen(a1);\n v4 = a1;\n v5 = &a1[v3];\n v6 = 0;\n while ( v4 != v5 )\n v6 += *v4++ == a2;\n return v6;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov ebp, esi\ncall _strlen\nmov rdi, rax\nmov rax, rbx\nadd rdi, rbx\nmov edx, 0\njmp short loc_119C\nloc_118D:\ncmp [rax], bpl\nsetz cl\nmovzx ecx, cl\nadd edx, ecx\nadd rax, 1\nloc_119C:\ncmp rax, rdi\njnz short loc_118D\nmov eax, edx\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1, unsigned __int8 a2)\n{\n size_t v3; // rdi\n const char *v4; // rax\n const char *v5; // rdi\n unsigned int v6; // edx\n\n v3 = strlen(a1);\n v4 = a1;\n v5 = &a1[v3];\n v6 = 0;\n while ( v4 != v5 )\n v6 += *v4++ == a2;\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1, unsigned char a2) {\n unsigned int v3;\n const char *v4;\n const char *v5;\n unsigned int v6;\n v3 = strlen(a1);\n v4 = a1;\n v5 = &a1[v3];\n v6 = 0;\n while (v4 != v5) v6 += *v4++ == a2;\n return v6;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, unsigned char a2) {\n unsigned int v3;\n const char *v4;\n const char *v5;\n unsigned int v6;\n v3 = strlen(a1);\n v4 = a1;\n v5 = &a1[v3];\n v6 = 0;\n while (v4 != v5) v6 += *v4++ == a2;\n return v6;\n}" + }, + { + "index": 666, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *string, char c) {\n int count = 0;\n for (int i = 0; i < strlen(string); i++) {\n if (string[i] == c) {\n count++;\n }\n }\n return count;\n}", + "test": "int main() {\n\n assert(func0(\"Python\", 'o') == 1);\n\n assert(func0(\"little\", 't') == 2);\n\n assert(func0(\"assert\", 's') == 2);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %esi,%ebp\npush %rbx\nmov %rdi,%rbx\nsub $0x8,%rsp\ncallq 1060 \nmov %rbx,%rdi\nlea (%rbx,%rax,1),%rcx\nxor %eax,%eax\njmp 129e \nxor %edx,%edx\ncmp %bpl,(%rdi)\nsete %dl\nadd $0x1,%rdi\nadd %edx,%eax\ncmp %rcx,%rdi\njne 1290 \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov ebp, esi\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\ntest rax, rax\njz short loc_1268\nlea rcx, [rbx+rax]\nmov rdi, rbx\nxor eax, eax\nnop word ptr [rax+rax+00h]\nloc_1248:\nxor edx, edx\ncmp bpl, [rdi]\nsetz dl\nadd rdi, 1\nadd eax, edx\ncmp rcx, rdi\njnz short loc_1248\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1268:\nadd rsp, 8\nxor eax, eax\npop rbx\npop rbp\nretn", + "ida_pseudo": "size_t __fastcall func0(const char *a1, char a2)\n{\n size_t result; // rax\n const char *v3; // rcx\n _BOOL4 v4; // edx\n\n result = strlen(a1);\n if ( !result )\n return 0LL;\n v3 = &a1[result];\n LODWORD(result) = 0;\n do\n {\n v4 = a2 == *a1++;\n result = (unsigned int)(v4 + result);\n }\n while ( v3 != a1 );\n return result;\n}", + "ida_strip_asm": "sub_1220:\nendbr64\npush rbp\nmov ebp, esi\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\ntest rax, rax\njz short loc_1268\nlea rcx, [rbx+rax]\nmov rdi, rbx\nxor eax, eax\nnop word ptr [rax+rax+00h]\nloc_1248:\nxor edx, edx\ncmp bpl, [rdi]\nsetz dl\nadd rdi, 1\nadd eax, edx\ncmp rcx, rdi\njnz short loc_1248\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1268:\nadd rsp, 8\nxor eax, eax\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "size_t __fastcall sub_1220(const char *a1, char a2)\n{\n size_t result; // rax\n const char *v3; // rcx\n _BOOL4 v4; // edx\n\n result = strlen(a1);\n if ( !result )\n return 0LL;\n v3 = &a1[result];\n LODWORD(result) = 0;\n do\n {\n v4 = a2 == *a1++;\n result = (unsigned int)(v4 + result);\n }\n while ( v3 != a1 );\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned int sub_1220(const char *a1, char a2) {\n unsigned int result;\n const char *v3;\n int v4;\n result = strlen(a1);\n if (!result) return 0LL;\n v3 = &a1[result];\n LODWORD(result) = 0;\n do {\n v4 = a2 == *a1++;\n result = (unsigned int)(v4 + result);\n } while (v3 != a1);\n return result;\n}", + "ida_pseudo_norm": "unsigned int func0(const char *a1, char a2) {\n unsigned int result;\n const char *v3;\n int v4;\n result = strlen(a1);\n if (!result) return 0LL;\n v3 = &a1[result];\n LODWORD(result) = 0;\n do {\n v4 = a2 == *a1++;\n result = (unsigned int)(v4 + result);\n } while (v3 != a1);\n return result;\n}" + }, + { + "index": 666, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *string, char c) {\n int count = 0;\n for (int i = 0; i < strlen(string); i++) {\n if (string[i] == c) {\n count++;\n }\n }\n return count;\n}", + "test": "int main() {\n\n assert(func0(\"Python\", 'o') == 1);\n\n assert(func0(\"little\", 't') == 2);\n\n assert(func0(\"assert\", 's') == 2);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %esi,%ebp\npush %rbx\nmov %rdi,%rbx\nsub $0x8,%rsp\ncallq 1050 \ntest %rax,%rax\nje 13f0 \nmov %rax,%rcx\nlea -0x1(%rax),%rax\ncmp $0xe,%rax\njbe 13f9 \nmovd %ebp,%xmm4\nmov %rcx,%rax\npxor %xmm1,%xmm1\nmov %rbx,%rdx\npunpcklbw %xmm4,%xmm4\npxor %xmm6,%xmm6\npxor %xmm5,%xmm5\nand $0xfffffffffffffff0,%rax\npunpcklwd %xmm4,%xmm4\nmovdqa 0xe58(%rip),%xmm7\nadd %rbx,%rax\npshufd $0x0,%xmm4,%xmm4\nmovdqu (%rdx),%xmm0\nmovdqa %xmm6,%xmm3\nadd $0x10,%rdx\npcmpeqb %xmm4,%xmm0\npand %xmm7,%xmm0\npcmpgtb %xmm0,%xmm3\nmovdqa %xmm0,%xmm2\npunpcklbw %xmm3,%xmm2\npunpckhbw %xmm3,%xmm0\nmovdqa %xmm5,%xmm3\npcmpgtw %xmm2,%xmm3\nmovdqa %xmm2,%xmm8\npunpcklwd %xmm3,%xmm8\npunpckhwd %xmm3,%xmm2\nmovdqa %xmm0,%xmm3\npaddd %xmm8,%xmm1\npaddd %xmm2,%xmm1\nmovdqa %xmm5,%xmm2\npcmpgtw %xmm0,%xmm2\npunpcklwd %xmm2,%xmm3\npunpckhwd %xmm2,%xmm0\npaddd %xmm3,%xmm1\npaddd %xmm0,%xmm1\ncmp %rax,%rdx\njne 11c0 \nmovdqa %xmm1,%xmm0\nmov %rcx,%rsi\npsrldq $0x8,%xmm0\nand $0xfffffffffffffff0,%rsi\npaddd %xmm1,%xmm0\nmov %esi,%edx\nmovdqa %xmm0,%xmm1\npsrldq $0x4,%xmm1\npaddd %xmm1,%xmm0\nmovd %xmm0,%eax\ncmp %rsi,%rcx\nje 13e2 \ncmp %bpl,(%rbx,%rsi,1)\nsete %sil\nmovzbl %sil,%esi\nadd %esi,%eax\nlea 0x1(%rdx),%esi\nmovslq %esi,%rsi\ncmp %rsi,%rcx\njbe 13e2 \ncmp %bpl,(%rbx,%rsi,1)\nsete %sil\nmovzbl %sil,%esi\nadd %esi,%eax\nlea 0x2(%rdx),%esi\nmovslq %esi,%rsi\ncmp %rsi,%rcx\njbe 13e2 \ncmp %bpl,(%rbx,%rsi,1)\nsete %sil\nmovzbl %sil,%esi\nadd %esi,%eax\nlea 0x3(%rdx),%esi\nmovslq %esi,%rsi\ncmp %rsi,%rcx\njbe 13e2 \ncmp %bpl,(%rbx,%rsi,1)\nsete %sil\nmovzbl %sil,%esi\nadd %esi,%eax\nlea 0x4(%rdx),%esi\nmovslq %esi,%rsi\ncmp %rsi,%rcx\njbe 13e2 \ncmp %bpl,(%rbx,%rsi,1)\nsete %sil\nmovzbl %sil,%esi\nadd %esi,%eax\nlea 0x5(%rdx),%esi\nmovslq %esi,%rsi\ncmp %rsi,%rcx\njbe 13e2 \ncmp %bpl,(%rbx,%rsi,1)\nsete %sil\nmovzbl %sil,%esi\nadd %esi,%eax\nlea 0x6(%rdx),%esi\nmovslq %esi,%rsi\ncmp %rsi,%rcx\njbe 13e2 \ncmp %bpl,(%rbx,%rsi,1)\nsete %sil\nmovzbl %sil,%esi\nadd %esi,%eax\nlea 0x7(%rdx),%esi\nmovslq %esi,%rsi\ncmp %rsi,%rcx\njbe 13e2 \ncmp %bpl,(%rbx,%rsi,1)\nsete %sil\nmovzbl %sil,%esi\nadd %esi,%eax\nlea 0x8(%rdx),%esi\nmovslq %esi,%rsi\ncmp %rsi,%rcx\njbe 13e2 \ncmp %bpl,(%rbx,%rsi,1)\nsete %sil\nmovzbl %sil,%esi\nadd %esi,%eax\nlea 0x9(%rdx),%esi\nmovslq %esi,%rsi\ncmp %rsi,%rcx\njbe 13e2 \ncmp %bpl,(%rbx,%rsi,1)\nsete %sil\nmovzbl %sil,%esi\nadd %esi,%eax\nlea 0xa(%rdx),%esi\nmovslq %esi,%rsi\ncmp %rsi,%rcx\njbe 13e2 \ncmp %bpl,(%rbx,%rsi,1)\nsete %sil\nmovzbl %sil,%esi\nadd %esi,%eax\nlea 0xb(%rdx),%esi\nmovslq %esi,%rsi\ncmp %rsi,%rcx\njbe 13e2 \ncmp %bpl,(%rbx,%rsi,1)\nsete %sil\nmovzbl %sil,%esi\nadd %esi,%eax\nlea 0xc(%rdx),%esi\nmovslq %esi,%rsi\ncmp %rsi,%rcx\njbe 13e2 \ncmp %bpl,(%rbx,%rsi,1)\nsete %sil\nmovzbl %sil,%esi\nadd %esi,%eax\nlea 0xd(%rdx),%esi\nmovslq %esi,%rsi\ncmp %rsi,%rcx\njbe 13e2 \ncmp %bpl,(%rbx,%rsi,1)\nsete %sil\nadd $0xe,%edx\nmovzbl %sil,%esi\nmovslq %edx,%rdx\nadd %esi,%eax\ncmp %rdx,%rcx\njbe 13e2 \ncmp %bpl,(%rbx,%rdx,1)\nsete %dl\nmovzbl %dl,%edx\nadd %edx,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopl 0x0(%rax)\nadd $0x8,%rsp\nxor %eax,%eax\npop %rbx\npop %rbp\nretq\nxor %edx,%edx\nxor %eax,%eax\nxor %esi,%esi\njmpq 1254 \nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov ebp, esi\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\ntest rax, rax\njz loc_13D0\nmov rdx, rax\nlea rax, [rax-1]\ncmp rax, 0Eh\njbe loc_13D9\nmovd xmm4, ebp\nmov rcx, rdx\npxor xmm1, xmm1\nmov rax, rbx\npunpcklbw xmm4, xmm4\npxor xmm6, xmm6\npxor xmm5, xmm5\nand rcx, 0FFFFFFFFFFFFFFF0h\npunpcklwd xmm4, xmm4\nlea rsi, [rcx+rbx]\npshufd xmm4, xmm4, 0\nnop dword ptr [rax+00000000h]\nloc_11C0:\nmovdqu xmm0, xmmword ptr [rax]\nmovdqa xmm3, xmm6\nadd rax, 10h\npcmpeqb xmm0, xmm4\npcmpgtb xmm3, xmm0\nmovdqa xmm2, xmm0\npunpcklbw xmm2, xmm3\npunpckhbw xmm0, xmm3\nmovdqa xmm3, xmm5\npcmpgtw xmm3, xmm2\nmovdqa xmm7, xmm2\npunpcklwd xmm7, xmm3\npunpckhwd xmm2, xmm3\nmovdqa xmm3, xmm0\npsubd xmm1, xmm7\npsubd xmm1, xmm2\nmovdqa xmm2, xmm5\npcmpgtw xmm2, xmm0\npunpcklwd xmm3, xmm2\npunpckhwd xmm0, xmm2\npsubd xmm1, xmm3\npsubd xmm1, xmm0\ncmp rsi, rax\njnz short loc_11C0\nmovdqa xmm0, xmm1\nmov esi, ecx\npsrldq xmm0, 8\npaddd xmm0, xmm1\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\npaddd xmm0, xmm2\nmovd eax, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm1, 8\npaddd xmm0, xmm1\ncmp rdx, rcx\njz loc_136F\nloc_1253:\nmov rdi, rdx\nsub rdi, rcx\nlea r8, [rdi-1]\ncmp r8, 6\njbe loc_12FD\nmovzx eax, bpl\nmovq xmm1, qword ptr [rbx+rcx]\nmov ah, al\nmovd xmm6, eax\npshuflw xmm2, xmm6, 0\npcmpeqb xmm1, xmm2\npxor xmm2, xmm2\npcmpgtb xmm2, xmm1\nmovdqa xmm3, xmm1\npunpcklbw xmm3, xmm2\npunpcklbw xmm1, xmm2\npxor xmm2, xmm2\nmovdqa xmm4, xmm2\nmovdqa xmm5, xmm3\npshufd xmm1, xmm1, 4Eh ; 'N'\npcmpgtw xmm4, xmm3\npcmpgtw xmm2, xmm1\npunpcklwd xmm5, xmm4\npunpcklwd xmm3, xmm4\npsubd xmm0, xmm5\npshufd xmm3, xmm3, 4Eh ; 'N'\npsubd xmm0, xmm3\nmovdqa xmm3, xmm1\npunpcklwd xmm1, xmm2\npunpcklwd xmm3, xmm2\npshufd xmm1, xmm1, 4Eh ; 'N'\npsubd xmm0, xmm3\npsubd xmm0, xmm1\nmovd r8d, xmm0\npshufd xmm6, xmm0, 0E5h\nmovd eax, xmm6\nadd eax, r8d\nmov r8, rdi\nand r8, 0FFFFFFFFFFFFFFF8h\nadd rcx, r8\nadd esi, r8d\nand edi, 7\njz short loc_136F\nloc_12FD:\ncmp [rbx+rcx], bpl\njz short loc_1380\nloc_1303:\nlea ecx, [rsi+1]\nmovsxd rcx, ecx\ncmp rcx, rdx\njnb short loc_136F\ncmp bpl, [rbx+rcx]\njz short loc_1390\nloc_1314:\nlea ecx, [rsi+2]\nmovsxd rcx, ecx\ncmp rcx, rdx\njnb short loc_136F\ncmp bpl, [rbx+rcx]\njz short loc_13A0\nloc_1325:\nlea ecx, [rsi+3]\nmovsxd rcx, ecx\ncmp rcx, rdx\njnb short loc_136F\ncmp bpl, [rbx+rcx]\njz short loc_13A8\nlea ecx, [rsi+4]\nmovsxd rcx, ecx\ncmp rcx, rdx\njnb short loc_136F\nloc_1341:\ncmp bpl, [rbx+rcx]\njnz short loc_134A\nadd eax, 1\nloc_134A:\nlea ecx, [rsi+5]\nmovsxd rcx, ecx\ncmp rcx, rdx\njnb short loc_136F\ncmp bpl, [rbx+rcx]\njnz short loc_135E\nadd eax, 1\nloc_135E:\nadd esi, 6\nmovsxd rsi, esi\ncmp rsi, rdx\njnb short loc_136F\ncmp bpl, [rbx+rsi]\njz short loc_13C0\nloc_136F:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1380:\nadd eax, 1\njmp loc_1303\nloc_1390:\nadd eax, 1\njmp loc_1314\nloc_13A0:\nadd eax, 1\njmp short loc_1325\nloc_13A8:\nlea ecx, [rsi+4]\nadd eax, 1\nmovsxd rcx, ecx\ncmp rcx, rdx\njb short loc_1341\njmp short loc_136F\nloc_13C0:\nadd rsp, 8\nadd eax, 1\npop rbx\npop rbp\nretn\nloc_13D0:\nadd rsp, 8\nxor eax, eax\npop rbx\npop rbp\nretn\nloc_13D9:\npxor xmm0, xmm0\nxor esi, esi\nxor eax, eax\nxor ecx, ecx\njmp loc_1253", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, unsigned __int8 a2)\n{\n size_t v4; // rax\n size_t v5; // rdx\n __m128i v6; // xmm4\n __m128i v7; // xmm1\n const __m128i *v8; // rax\n __m128i v9; // xmm4\n unsigned __int64 v10; // rcx\n __m128i v11; // xmm4\n __m128i v12; // xmm0\n __m128i v13; // xmm0\n __m128i v14; // xmm3\n __m128i v15; // xmm2\n __m128i v16; // xmm0\n __m128i v17; // xmm3\n __m128i v18; // xmm1\n __m128i v19; // xmm2\n int v20; // esi\n __m128i v21; // xmm0\n __int64 result; // rax\n __m128i v23; // xmm0\n size_t v24; // rdi\n unsigned int v25; // eax\n __m128i v26; // xmm1\n __m128i v27; // xmm3\n __m128i v28; // xmm1\n __m128i v29; // xmm2\n __m128i v30; // xmm3\n __m128i v31; // xmm0\n size_t v32; // rcx\n size_t v33; // rcx\n size_t v34; // rcx\n size_t v35; // rcx\n size_t v36; // rcx\n size_t v37; // rsi\n\n v4 = strlen(a1);\n if ( !v4 )\n return 0LL;\n v5 = v4;\n if ( v4 - 1 <= 0xE )\n {\n v23 = 0LL;\n v20 = 0;\n result = 0LL;\n v10 = 0LL;\n }\n else\n {\n v6 = _mm_cvtsi32_si128(a2);\n v7 = 0LL;\n v8 = (const __m128i *)a1;\n v9 = _mm_unpacklo_epi8(v6, v6);\n v10 = v5 & 0xFFFFFFFFFFFFFFF0LL;\n v11 = _mm_shuffle_epi32(_mm_unpacklo_epi16(v9, v9), 0);\n do\n {\n v12 = _mm_loadu_si128(v8++);\n v13 = _mm_cmpeq_epi8(v12, v11);\n v14 = _mm_cmpgt_epi8((__m128i)0LL, v13);\n v15 = _mm_unpacklo_epi8(v13, v14);\n v16 = _mm_unpackhi_epi8(v13, v14);\n v17 = _mm_cmpgt_epi16((__m128i)0LL, v15);\n v18 = _mm_sub_epi32(_mm_sub_epi32(v7, _mm_unpacklo_epi16(v15, v17)), _mm_unpackhi_epi16(v15, v17));\n v19 = _mm_cmpgt_epi16((__m128i)0LL, v16);\n v7 = _mm_sub_epi32(_mm_sub_epi32(v18, _mm_unpacklo_epi16(v16, v19)), _mm_unpackhi_epi16(v16, v19));\n }\n while ( &a1[v5 & 0xFFFFFFFFFFFFFFF0LL] != (const char *)v8 );\n v20 = v5 & 0xFFFFFFF0;\n v21 = _mm_add_epi32(_mm_srli_si128(v7, 8), v7);\n result = (unsigned int)_mm_cvtsi128_si32(_mm_add_epi32(v21, _mm_srli_si128(v21, 4)));\n v23 = _mm_add_epi32(v7, _mm_srli_si128(v7, 8));\n if ( v5 == v10 )\n return result;\n }\n v24 = v5 - v10;\n if ( v5 - v10 - 1 <= 6 )\n goto LABEL_34;\n v25 = a2;\n BYTE1(v25) = a2;\n v26 = _mm_cmpeq_epi8(_mm_loadl_epi64((const __m128i *)&a1[v10]), _mm_shufflelo_epi16(_mm_cvtsi32_si128(v25), 0));\n v27 = _mm_unpacklo_epi8(v26, _mm_cmpgt_epi8((__m128i)0LL, v26));\n v28 = _mm_shuffle_epi32(v27, 78);\n v29 = _mm_cmpgt_epi16((__m128i)0LL, v28);\n v30 = _mm_unpacklo_epi16(v27, _mm_cmpgt_epi16((__m128i)0LL, v27));\n v31 = _mm_sub_epi32(\n _mm_sub_epi32(\n _mm_sub_epi32(_mm_sub_epi32(v23, v30), _mm_shuffle_epi32(v30, 78)),\n _mm_unpacklo_epi16(v28, v29)),\n _mm_shuffle_epi32(_mm_unpacklo_epi16(v28, v29), 78));\n result = (unsigned int)(_mm_cvtsi128_si32(v31) + _mm_cvtsi128_si32(_mm_shuffle_epi32(v31, 229)));\n v10 += v24 & 0xFFFFFFFFFFFFFFF8LL;\n v20 += v24 & 0xFFFFFFF8;\n if ( (v24 & 7) != 0 )\n {\nLABEL_34:\n if ( a1[v10] == a2 )\n result = (unsigned int)(result + 1);\n v32 = v20 + 1;\n if ( v32 < v5 )\n {\n if ( a2 == a1[v32] )\n result = (unsigned int)(result + 1);\n v33 = v20 + 2;\n if ( v33 < v5 )\n {\n if ( a2 == a1[v33] )\n result = (unsigned int)(result + 1);\n v34 = v20 + 3;\n if ( v34 < v5 )\n {\n if ( a2 == a1[v34] )\n {\n result = (unsigned int)(result + 1);\n v35 = v20 + 4;\n if ( v35 >= v5 )\n return result;\n }\n else\n {\n v35 = v20 + 4;\n if ( v35 >= v5 )\n return result;\n }\n if ( a2 == a1[v35] )\n result = (unsigned int)(result + 1);\n v36 = v20 + 5;\n if ( v36 < v5 )\n {\n if ( a2 == a1[v36] )\n result = (unsigned int)(result + 1);\n v37 = v20 + 6;\n if ( v37 < v5 && a2 == a1[v37] )\n return (unsigned int)(result + 1);\n }\n }\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1160:\nendbr64\npush rbp\nmov ebp, esi\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\ntest rax, rax\njz loc_13D0\nmov rdx, rax\nlea rax, [rax-1]\ncmp rax, 0Eh\njbe loc_13D9\nmovd xmm4, ebp\nmov rcx, rdx\npxor xmm1, xmm1\nmov rax, rbx\npunpcklbw xmm4, xmm4\npxor xmm6, xmm6\npxor xmm5, xmm5\nand rcx, 0FFFFFFFFFFFFFFF0h\npunpcklwd xmm4, xmm4\nlea rsi, [rcx+rbx]\npshufd xmm4, xmm4, 0\nnop dword ptr [rax+00000000h]\nloc_11C0:\nmovdqu xmm0, xmmword ptr [rax]\nmovdqa xmm3, xmm6\nadd rax, 10h\npcmpeqb xmm0, xmm4\npcmpgtb xmm3, xmm0\nmovdqa xmm2, xmm0\npunpcklbw xmm2, xmm3\npunpckhbw xmm0, xmm3\nmovdqa xmm3, xmm5\npcmpgtw xmm3, xmm2\nmovdqa xmm7, xmm2\npunpcklwd xmm7, xmm3\npunpckhwd xmm2, xmm3\nmovdqa xmm3, xmm0\npsubd xmm1, xmm7\npsubd xmm1, xmm2\nmovdqa xmm2, xmm5\npcmpgtw xmm2, xmm0\npunpcklwd xmm3, xmm2\npunpckhwd xmm0, xmm2\npsubd xmm1, xmm3\npsubd xmm1, xmm0\ncmp rsi, rax\njnz short loc_11C0\nmovdqa xmm0, xmm1\nmov esi, ecx\npsrldq xmm0, 8\npaddd xmm0, xmm1\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\npaddd xmm0, xmm2\nmovd eax, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm1, 8\npaddd xmm0, xmm1\ncmp rdx, rcx\njz loc_136F\nloc_1253:\nmov rdi, rdx\nsub rdi, rcx\nlea r8, [rdi-1]\ncmp r8, 6\njbe loc_12FD\nmovzx eax, bpl\nmovq xmm1, qword ptr [rbx+rcx]\nmov ah, al\nmovd xmm6, eax\npshuflw xmm2, xmm6, 0\npcmpeqb xmm1, xmm2\npxor xmm2, xmm2\npcmpgtb xmm2, xmm1\nmovdqa xmm3, xmm1\npunpcklbw xmm3, xmm2\npunpcklbw xmm1, xmm2\npxor xmm2, xmm2\nmovdqa xmm4, xmm2\nmovdqa xmm5, xmm3\npshufd xmm1, xmm1, 4Eh ; 'N'\npcmpgtw xmm4, xmm3\npcmpgtw xmm2, xmm1\npunpcklwd xmm5, xmm4\npunpcklwd xmm3, xmm4\npsubd xmm0, xmm5\npshufd xmm3, xmm3, 4Eh ; 'N'\npsubd xmm0, xmm3\nmovdqa xmm3, xmm1\npunpcklwd xmm1, xmm2\npunpcklwd xmm3, xmm2\npshufd xmm1, xmm1, 4Eh ; 'N'\npsubd xmm0, xmm3\npsubd xmm0, xmm1\nmovd r8d, xmm0\npshufd xmm6, xmm0, 0E5h\nmovd eax, xmm6\nadd eax, r8d\nmov r8, rdi\nand r8, 0FFFFFFFFFFFFFFF8h\nadd rcx, r8\nadd esi, r8d\nand edi, 7\njz short loc_136F\nloc_12FD:\ncmp [rbx+rcx], bpl\njz short loc_1380\nloc_1303:\nlea ecx, [rsi+1]\nmovsxd rcx, ecx\ncmp rcx, rdx\njnb short loc_136F\ncmp bpl, [rbx+rcx]\njz short loc_1390\nloc_1314:\nlea ecx, [rsi+2]\nmovsxd rcx, ecx\ncmp rcx, rdx\njnb short loc_136F\ncmp bpl, [rbx+rcx]\njz short loc_13A0\nloc_1325:\nlea ecx, [rsi+3]\nmovsxd rcx, ecx\ncmp rcx, rdx\njnb short loc_136F\ncmp bpl, [rbx+rcx]\njz short loc_13A8\nlea ecx, [rsi+4]\nmovsxd rcx, ecx\ncmp rcx, rdx\njnb short loc_136F\nloc_1341:\ncmp bpl, [rbx+rcx]\njnz short loc_134A\nadd eax, 1\nloc_134A:\nlea ecx, [rsi+5]\nmovsxd rcx, ecx\ncmp rcx, rdx\njnb short loc_136F\ncmp bpl, [rbx+rcx]\njnz short loc_135E\nadd eax, 1\nloc_135E:\nadd esi, 6\nmovsxd rsi, esi\ncmp rsi, rdx\njnb short loc_136F\ncmp bpl, [rbx+rsi]\njz short loc_13C0\nloc_136F:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1380:\nadd eax, 1\njmp loc_1303\nloc_1390:\nadd eax, 1\njmp loc_1314\nloc_13A0:\nadd eax, 1\njmp short loc_1325\nloc_13A8:\nlea ecx, [rsi+4]\nadd eax, 1\nmovsxd rcx, ecx\ncmp rcx, rdx\njb short loc_1341\njmp short loc_136F\nloc_13C0:\nadd rsp, 8\nadd eax, 1\npop rbx\npop rbp\nretn\nloc_13D0:\nadd rsp, 8\nxor eax, eax\npop rbx\npop rbp\nretn\nloc_13D9:\npxor xmm0, xmm0\nxor esi, esi\nxor eax, eax\nxor ecx, ecx\njmp loc_1253", + "ida_strip_pseudo": "__int64 __fastcall sub_1160(const char *a1, unsigned __int8 a2)\n{\n size_t v4; // rax\n size_t v5; // rdx\n __m128i v6; // xmm4\n __m128i v7; // xmm1\n const __m128i *v8; // rax\n __m128i v9; // xmm4\n unsigned __int64 v10; // rcx\n __m128i v11; // xmm4\n __m128i v12; // xmm0\n __m128i v13; // xmm0\n __m128i v14; // xmm3\n __m128i v15; // xmm2\n __m128i v16; // xmm0\n __m128i v17; // xmm3\n __m128i v18; // xmm1\n __m128i v19; // xmm2\n int v20; // esi\n __m128i v21; // xmm0\n __int64 result; // rax\n __m128i v23; // xmm0\n size_t v24; // rdi\n unsigned int v25; // eax\n __m128i v26; // xmm1\n __m128i v27; // xmm3\n __m128i v28; // xmm1\n __m128i v29; // xmm2\n __m128i v30; // xmm3\n __m128i v31; // xmm0\n size_t v32; // rcx\n size_t v33; // rcx\n size_t v34; // rcx\n size_t v35; // rcx\n size_t v36; // rcx\n size_t v37; // rsi\n\n v4 = strlen(a1);\n if ( !v4 )\n return 0LL;\n v5 = v4;\n if ( v4 - 1 <= 0xE )\n {\n v23 = 0LL;\n v20 = 0;\n result = 0LL;\n v10 = 0LL;\n }\n else\n {\n v6 = _mm_cvtsi32_si128(a2);\n v7 = 0LL;\n v8 = (const __m128i *)a1;\n v9 = _mm_unpacklo_epi8(v6, v6);\n v10 = v5 & 0xFFFFFFFFFFFFFFF0LL;\n v11 = _mm_shuffle_epi32(_mm_unpacklo_epi16(v9, v9), 0);\n do\n {\n v12 = _mm_loadu_si128(v8++);\n v13 = _mm_cmpeq_epi8(v12, v11);\n v14 = _mm_cmpgt_epi8((__m128i)0LL, v13);\n v15 = _mm_unpacklo_epi8(v13, v14);\n v16 = _mm_unpackhi_epi8(v13, v14);\n v17 = _mm_cmpgt_epi16((__m128i)0LL, v15);\n v18 = _mm_sub_epi32(_mm_sub_epi32(v7, _mm_unpacklo_epi16(v15, v17)), _mm_unpackhi_epi16(v15, v17));\n v19 = _mm_cmpgt_epi16((__m128i)0LL, v16);\n v7 = _mm_sub_epi32(_mm_sub_epi32(v18, _mm_unpacklo_epi16(v16, v19)), _mm_unpackhi_epi16(v16, v19));\n }\n while ( &a1[v5 & 0xFFFFFFFFFFFFFFF0LL] != (const char *)v8 );\n v20 = v5 & 0xFFFFFFF0;\n v21 = _mm_add_epi32(_mm_srli_si128(v7, 8), v7);\n result = (unsigned int)_mm_cvtsi128_si32(_mm_add_epi32(v21, _mm_srli_si128(v21, 4)));\n v23 = _mm_add_epi32(v7, _mm_srli_si128(v7, 8));\n if ( v5 == v10 )\n return result;\n }\n v24 = v5 - v10;\n if ( v5 - v10 - 1 <= 6 )\n goto LABEL_34;\n v25 = a2;\n BYTE1(v25) = a2;\n v26 = _mm_cmpeq_epi8(_mm_loadl_epi64((const __m128i *)&a1[v10]), _mm_shufflelo_epi16(_mm_cvtsi32_si128(v25), 0));\n v27 = _mm_unpacklo_epi8(v26, _mm_cmpgt_epi8((__m128i)0LL, v26));\n v28 = _mm_shuffle_epi32(v27, 78);\n v29 = _mm_cmpgt_epi16((__m128i)0LL, v28);\n v30 = _mm_unpacklo_epi16(v27, _mm_cmpgt_epi16((__m128i)0LL, v27));\n v31 = _mm_sub_epi32(\n _mm_sub_epi32(\n _mm_sub_epi32(_mm_sub_epi32(v23, v30), _mm_shuffle_epi32(v30, 78)),\n _mm_unpacklo_epi16(v28, v29)),\n _mm_shuffle_epi32(_mm_unpacklo_epi16(v28, v29), 78));\n result = (unsigned int)(_mm_cvtsi128_si32(v31) + _mm_cvtsi128_si32(_mm_shuffle_epi32(v31, 229)));\n v10 += v24 & 0xFFFFFFFFFFFFFFF8LL;\n v20 += v24 & 0xFFFFFFF8;\n if ( (v24 & 7) != 0 )\n {\nLABEL_34:\n if ( a1[v10] == a2 )\n result = (unsigned int)(result + 1);\n v32 = v20 + 1;\n if ( v32 < v5 )\n {\n if ( a2 == a1[v32] )\n result = (unsigned int)(result + 1);\n v33 = v20 + 2;\n if ( v33 < v5 )\n {\n if ( a2 == a1[v33] )\n result = (unsigned int)(result + 1);\n v34 = v20 + 3;\n if ( v34 < v5 )\n {\n if ( a2 == a1[v34] )\n {\n result = (unsigned int)(result + 1);\n v35 = v20 + 4;\n if ( v35 >= v5 )\n return result;\n }\n else\n {\n v35 = v20 + 4;\n if ( v35 >= v5 )\n return result;\n }\n if ( a2 == a1[v35] )\n result = (unsigned int)(result + 1);\n v36 = v20 + 5;\n if ( v36 < v5 )\n {\n if ( a2 == a1[v36] )\n result = (unsigned int)(result + 1);\n v37 = v20 + 6;\n if ( v37 < v5 && a2 == a1[v37] )\n return (unsigned int)(result + 1);\n }\n }\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1160(const char *a1, unsigned char a2) {\n unsigned int v4;\n unsigned int v5;\n __m128i v6;\n __m128i v7;\n const __m128i *v8;\n __m128i v9;\n unsigned long long v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n __m128i v15;\n __m128i v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n int v20;\n __m128i v21;\n long long result;\n __m128i v23;\n unsigned int v24;\n unsigned int v25;\n __m128i v26;\n __m128i v27;\n __m128i v28;\n __m128i v29;\n __m128i v30;\n __m128i v31;\n unsigned int v32;\n unsigned int v33;\n unsigned int v34;\n unsigned int v35;\n unsigned int v36;\n unsigned int v37;\n v4 = strlen(a1);\n if (!v4) return 0LL;\n v5 = v4;\n if (v4 - 1 <= 14) {\n v23 = 0LL;\n v20 = 0;\n result = 0LL;\n v10 = 0LL;\n } else {\n v6 = _mm_cvtsi32_si128(a2);\n v7 = 0LL;\n v8 = (const __m128i *)a1;\n v9 = _mm_unpacklo_epi8(v6, v6);\n v10 = v5 & 18446744073709551600LL;\n v11 = _mm_shuffle_epi32(_mm_unpacklo_epi16(v9, v9), 0);\n do {\n v12 = _mm_loadu_si128(v8++);\n v13 = _mm_cmpeq_epi8(v12, v11);\n v14 = _mm_cmpgt_epi8((__m128i)0LL, v13);\n v15 = _mm_unpacklo_epi8(v13, v14);\n v16 = _mm_unpackhi_epi8(v13, v14);\n v17 = _mm_cmpgt_epi16((__m128i)0LL, v15);\n v18 = _mm_sub_epi32(_mm_sub_epi32(v7, _mm_unpacklo_epi16(v15, v17)),\n _mm_unpackhi_epi16(v15, v17));\n v19 = _mm_cmpgt_epi16((__m128i)0LL, v16);\n v7 = _mm_sub_epi32(_mm_sub_epi32(v18, _mm_unpacklo_epi16(v16, v19)),\n _mm_unpackhi_epi16(v16, v19));\n } while (&a1[v5 & 18446744073709551600LL] != (const char *)v8);\n v20 = v5 & 4294967280;\n v21 = _mm_add_epi32(_mm_srli_si128(v7, 8), v7);\n result = (unsigned int)_mm_cvtsi128_si32(\n _mm_add_epi32(v21, _mm_srli_si128(v21, 4)));\n v23 = _mm_add_epi32(v7, _mm_srli_si128(v7, 8));\n if (v5 == v10) return result;\n }\n v24 = v5 - v10;\n if (v5 - v10 - 1 <= 6) goto LABEL_34;\n v25 = a2;\n BYTE1(v25) = a2;\n v26 = _mm_cmpeq_epi8(_mm_loadl_epi64((const __m128i *)&a1[v10]),\n _mm_shufflelo_epi16(_mm_cvtsi32_si128(v25), 0));\n v27 = _mm_unpacklo_epi8(v26, _mm_cmpgt_epi8((__m128i)0LL, v26));\n v28 = _mm_shuffle_epi32(v27, 78);\n v29 = _mm_cmpgt_epi16((__m128i)0LL, v28);\n v30 = _mm_unpacklo_epi16(v27, _mm_cmpgt_epi16((__m128i)0LL, v27));\n v31 = _mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(v23, v30),\n _mm_shuffle_epi32(v30, 78)),\n _mm_unpacklo_epi16(v28, v29)),\n _mm_shuffle_epi32(_mm_unpacklo_epi16(v28, v29), 78));\n result = (unsigned int)(_mm_cvtsi128_si32(v31) +\n _mm_cvtsi128_si32(_mm_shuffle_epi32(v31, 229)));\n v10 += v24 & 18446744073709551608LL;\n v20 += v24 & 4294967288;\n if ((v24 & 7) != 0) {\n LABEL_34:\n if (a1[v10] == a2) result = (unsigned int)(result + 1);\n v32 = v20 + 1;\n if (v32 < v5) {\n if (a2 == a1[v32]) result = (unsigned int)(result + 1);\n v33 = v20 + 2;\n if (v33 < v5) {\n if (a2 == a1[v33]) result = (unsigned int)(result + 1);\n v34 = v20 + 3;\n if (v34 < v5) {\n if (a2 == a1[v34]) {\n result = (unsigned int)(result + 1);\n v35 = v20 + 4;\n if (v35 >= v5) return result;\n } else {\n v35 = v20 + 4;\n if (v35 >= v5) return result;\n }\n if (a2 == a1[v35]) result = (unsigned int)(result + 1);\n v36 = v20 + 5;\n if (v36 < v5) {\n if (a2 == a1[v36]) result = (unsigned int)(result + 1);\n v37 = v20 + 6;\n if (v37 < v5 && a2 == a1[v37]) return (unsigned int)(result + 1);\n }\n }\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, unsigned char a2) {\n unsigned int v4;\n unsigned int v5;\n __m128i v6;\n __m128i v7;\n const __m128i *v8;\n __m128i v9;\n unsigned long long v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n __m128i v15;\n __m128i v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n int v20;\n __m128i v21;\n long long result;\n __m128i v23;\n unsigned int v24;\n unsigned int v25;\n __m128i v26;\n __m128i v27;\n __m128i v28;\n __m128i v29;\n __m128i v30;\n __m128i v31;\n unsigned int v32;\n unsigned int v33;\n unsigned int v34;\n unsigned int v35;\n unsigned int v36;\n unsigned int v37;\n v4 = strlen(a1);\n if (!v4) return 0LL;\n v5 = v4;\n if (v4 - 1 <= 14) {\n v23 = 0LL;\n v20 = 0;\n result = 0LL;\n v10 = 0LL;\n } else {\n v6 = _mm_cvtsi32_si128(a2);\n v7 = 0LL;\n v8 = (const __m128i *)a1;\n v9 = _mm_unpacklo_epi8(v6, v6);\n v10 = v5 & 18446744073709551600LL;\n v11 = _mm_shuffle_epi32(_mm_unpacklo_epi16(v9, v9), 0);\n do {\n v12 = _mm_loadu_si128(v8++);\n v13 = _mm_cmpeq_epi8(v12, v11);\n v14 = _mm_cmpgt_epi8((__m128i)0LL, v13);\n v15 = _mm_unpacklo_epi8(v13, v14);\n v16 = _mm_unpackhi_epi8(v13, v14);\n v17 = _mm_cmpgt_epi16((__m128i)0LL, v15);\n v18 = _mm_sub_epi32(_mm_sub_epi32(v7, _mm_unpacklo_epi16(v15, v17)),\n _mm_unpackhi_epi16(v15, v17));\n v19 = _mm_cmpgt_epi16((__m128i)0LL, v16);\n v7 = _mm_sub_epi32(_mm_sub_epi32(v18, _mm_unpacklo_epi16(v16, v19)),\n _mm_unpackhi_epi16(v16, v19));\n } while (&a1[v5 & 18446744073709551600LL] != (const char *)v8);\n v20 = v5 & 4294967280;\n v21 = _mm_add_epi32(_mm_srli_si128(v7, 8), v7);\n result = (unsigned int)_mm_cvtsi128_si32(\n _mm_add_epi32(v21, _mm_srli_si128(v21, 4)));\n v23 = _mm_add_epi32(v7, _mm_srli_si128(v7, 8));\n if (v5 == v10) return result;\n }\n v24 = v5 - v10;\n if (v5 - v10 - 1 <= 6) goto LABEL_34;\n v25 = a2;\n BYTE1(v25) = a2;\n v26 = _mm_cmpeq_epi8(_mm_loadl_epi64((const __m128i *)&a1[v10]),\n _mm_shufflelo_epi16(_mm_cvtsi32_si128(v25), 0));\n v27 = _mm_unpacklo_epi8(v26, _mm_cmpgt_epi8((__m128i)0LL, v26));\n v28 = _mm_shuffle_epi32(v27, 78);\n v29 = _mm_cmpgt_epi16((__m128i)0LL, v28);\n v30 = _mm_unpacklo_epi16(v27, _mm_cmpgt_epi16((__m128i)0LL, v27));\n v31 = _mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(v23, v30),\n _mm_shuffle_epi32(v30, 78)),\n _mm_unpacklo_epi16(v28, v29)),\n _mm_shuffle_epi32(_mm_unpacklo_epi16(v28, v29), 78));\n result = (unsigned int)(_mm_cvtsi128_si32(v31) +\n _mm_cvtsi128_si32(_mm_shuffle_epi32(v31, 229)));\n v10 += v24 & 18446744073709551608LL;\n v20 += v24 & 4294967288;\n if ((v24 & 7) != 0) {\n LABEL_34:\n if (a1[v10] == a2) result = (unsigned int)(result + 1);\n v32 = v20 + 1;\n if (v32 < v5) {\n if (a2 == a1[v32]) result = (unsigned int)(result + 1);\n v33 = v20 + 2;\n if (v33 < v5) {\n if (a2 == a1[v33]) result = (unsigned int)(result + 1);\n v34 = v20 + 3;\n if (v34 < v5) {\n if (a2 == a1[v34]) {\n result = (unsigned int)(result + 1);\n v35 = v20 + 4;\n if (v35 >= v5) return result;\n } else {\n v35 = v20 + 4;\n if (v35 >= v5) return result;\n }\n if (a2 == a1[v35]) result = (unsigned int)(result + 1);\n v36 = v20 + 5;\n if (v36 < v5) {\n if (a2 == a1[v36]) result = (unsigned int)(result + 1);\n v37 = v20 + 6;\n if (v37 < v5 && a2 == a1[v37]) return (unsigned int)(result + 1);\n }\n }\n }\n }\n }\n return result;\n}" + }, + { + "index": 667, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(const char *string, const char *vowels) {\n int count = 0;\n const char *s = string;\n const char *v;\n while (*s) {\n v = vowels;\n while (*v) {\n if (*s == *v) {\n count++;\n break;\n }\n v++;\n }\n s++;\n }\n return count;\n}", + "test": "int main() {\n\n assert(func0(\"corner\", \"AaEeIiOoUu\") == 2);\n\n assert(func0(\"valid\", \"AaEeIiOoUu\") == 2);\n\n assert(func0(\"true\", \"AaEeIiOoUu\") == 2);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x28(%rbp)\nmov %rsi,-0x30(%rbp)\nmovl $0x0,-0x14(%rbp)\nmov -0x28(%rbp),%rax\nmov %rax,-0x10(%rbp)\njmp 11a1 \nmov -0x30(%rbp),%rax\nmov %rax,-0x8(%rbp)\njmp 1191 \nmov -0x10(%rbp),%rax\nmovzbl (%rax),%edx\nmov -0x8(%rbp),%rax\nmovzbl (%rax),%eax\ncmp %al,%dl\njne 118c \naddl $0x1,-0x14(%rbp)\njmp 119c \naddq $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 1174 \naddq $0x1,-0x10(%rbp)\nmov -0x10(%rbp),%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 116a \nmov -0x14(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_30], rsi\nmov [rbp+var_14], 0\nmov rax, [rbp+var_28]\nmov [rbp+var_10], rax\njmp short loc_11A1\nloc_116A:\nmov rax, [rbp+var_30]\nmov [rbp+var_8], rax\njmp short loc_1191\nloc_1174:\nmov rax, [rbp+var_10]\nmovzx edx, byte ptr [rax]\nmov rax, [rbp+var_8]\nmovzx eax, byte ptr [rax]\ncmp dl, al\njnz short loc_118C\nadd [rbp+var_14], 1\njmp short loc_119C\nloc_118C:\nadd [rbp+var_8], 1\nloc_1191:\nmov rax, [rbp+var_8]\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1174\nloc_119C:\nadd [rbp+var_10], 1\nloc_11A1:\nmov rax, [rbp+var_10]\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_116A\nmov eax, [rbp+var_14]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(_BYTE *a1, _BYTE *a2)\n{\n unsigned int v3; // [rsp+1Ch] [rbp-14h]\n _BYTE *i; // [rsp+28h] [rbp-8h]\n\n v3 = 0;\n while ( *a1 )\n {\n for ( i = a2; *i; ++i )\n {\n if ( *a1 == *i )\n {\n ++v3;\n break;\n }\n }\n ++a1;\n }\n return v3;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_30], rsi\nmov [rbp+var_14], 0\nmov rax, [rbp+var_28]\nmov [rbp+var_10], rax\njmp short loc_11A1\nloc_116A:\nmov rax, [rbp+var_30]\nmov [rbp+var_8], rax\njmp short loc_1191\nloc_1174:\nmov rax, [rbp+var_10]\nmovzx edx, byte ptr [rax]\nmov rax, [rbp+var_8]\nmovzx eax, byte ptr [rax]\ncmp dl, al\njnz short loc_118C\nadd [rbp+var_14], 1\njmp short loc_119C\nloc_118C:\nadd [rbp+var_8], 1\nloc_1191:\nmov rax, [rbp+var_8]\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1174\nloc_119C:\nadd [rbp+var_10], 1\nloc_11A1:\nmov rax, [rbp+var_10]\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_116A\nmov eax, [rbp+var_14]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(_BYTE *a1, _BYTE *a2)\n{\n unsigned int v3; // [rsp+1Ch] [rbp-14h]\n _BYTE *i; // [rsp+28h] [rbp-8h]\n\n v3 = 0;\n while ( *a1 )\n {\n for ( i = a2; *i; ++i )\n {\n if ( *a1 == *i )\n {\n ++v3;\n break;\n }\n }\n ++a1;\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(uint8_t *a1, uint8_t *a2) {\n unsigned int v3;\n uint8_t *i;\n v3 = 0;\n while (*a1) {\n for (i = a2; *i; ++i) {\n if (*a1 == *i) {\n ++v3;\n break;\n }\n }\n ++a1;\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(uint8_t *a1, uint8_t *a2) {\n unsigned int v3;\n uint8_t *i;\n v3 = 0;\n while (*a1) {\n for (i = a2; *i; ++i) {\n if (*a1 == *i) {\n ++v3;\n break;\n }\n }\n ++a1;\n }\n return v3;\n}" + }, + { + "index": 667, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(const char *string, const char *vowels) {\n int count = 0;\n const char *s = string;\n const char *v;\n while (*s) {\n v = vowels;\n while (*v) {\n if (*s == *v) {\n count++;\n break;\n }\n v++;\n }\n s++;\n }\n return count;\n}", + "test": "int main() {\n\n assert(func0(\"corner\", \"AaEeIiOoUu\") == 2);\n\n assert(func0(\"valid\", \"AaEeIiOoUu\") == 2);\n\n assert(func0(\"true\", \"AaEeIiOoUu\") == 2);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmovzbl (%rdi),%ecx\ntest %cl,%cl\nje 118e \nmovzbl (%rsi),%r9d\nmov $0x0,%r8d\nmov %r9d,%r10d\njmp 1172 \nadd $0x1,%r8d\nadd $0x1,%rdi\nmovzbl (%rdi),%ecx\ntest %cl,%cl\nje 1194 \nmov %rsi,%rdx\nmov %r10d,%eax\ntest %r9b,%r9b\nje 1167 \ncmp %cl,%al\nje 1163 \nadd $0x1,%rdx\nmovzbl (%rdx),%eax\ntest %al,%al\njne 117d \njmp 1167 \nmov $0x0,%r8d\nmov %r8d,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmovzx ecx, byte ptr [rdi]\ntest cl, cl\njz short loc_118B\nmovzx r8d, byte ptr [rsi]\nmov r9d, 0\njmp short loc_116F\nloc_1160:\nadd r9d, 1\nloc_1164:\nadd rdi, 1\nmovzx ecx, byte ptr [rdi]\ntest cl, cl\njz short loc_1191\nloc_116F:\nmov rdx, rsi\nmov eax, r8d\ntest r8b, r8b\njz short loc_1164\nloc_117A:\ncmp al, cl\njz short loc_1160\nadd rdx, 1\nmovzx eax, byte ptr [rdx]\ntest al, al\njnz short loc_117A\njmp short loc_1164\nloc_118B:\nmov r9d, 0\nloc_1191:\nmov eax, r9d\nretn", + "ida_pseudo": "__int64 __fastcall func0(char *a1, _BYTE *a2)\n{\n char v2; // cl\n unsigned int v3; // r9d\n _BYTE *v4; // rdx\n char v5; // al\n\n v2 = *a1;\n if ( *a1 )\n {\n v3 = 0;\n do\n {\n v4 = a2;\n v5 = *a2;\n if ( *a2 )\n {\n while ( v5 != v2 )\n {\n v5 = *++v4;\n if ( !*v4 )\n goto LABEL_4;\n }\n ++v3;\n }\nLABEL_4:\n v2 = *++a1;\n }\n while ( *a1 );\n }\n else\n {\n return 0;\n }\n return v3;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmovzx ecx, byte ptr [rdi]\ntest cl, cl\njz short loc_118B\nmovzx r8d, byte ptr [rsi]\nmov r9d, 0\njmp short loc_116F\nloc_1160:\nadd r9d, 1\nloc_1164:\nadd rdi, 1\nmovzx ecx, byte ptr [rdi]\ntest cl, cl\njz short loc_1191\nloc_116F:\nmov rdx, rsi\nmov eax, r8d\ntest r8b, r8b\njz short loc_1164\nloc_117A:\ncmp al, cl\njz short loc_1160\nadd rdx, 1\nmovzx eax, byte ptr [rdx]\ntest al, al\njnz short loc_117A\njmp short loc_1164\nloc_118B:\nmov r9d, 0\nloc_1191:\nmov eax, r9d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(char *a1, _BYTE *a2)\n{\n char v2; // cl\n unsigned int v3; // r9d\n _BYTE *v4; // rdx\n char v5; // al\n\n v2 = *a1;\n if ( *a1 )\n {\n v3 = 0;\n do\n {\n v4 = a2;\n v5 = *a2;\n if ( *a2 )\n {\n while ( v5 != v2 )\n {\n v5 = *++v4;\n if ( !*v4 )\n goto LABEL_4;\n }\n ++v3;\n }\nLABEL_4:\n v2 = *++a1;\n }\n while ( *a1 );\n }\n else\n {\n return 0;\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(char *a1, uint8_t *a2) {\n char v2;\n unsigned int v3;\n uint8_t *v4;\n char v5;\n v2 = *a1;\n if (*a1) {\n v3 = 0;\n do {\n v4 = a2;\n v5 = *a2;\n if (*a2) {\n while (v5 != v2) {\n v5 = *++v4;\n if (!*v4) goto LABEL_4;\n }\n ++v3;\n }\n LABEL_4:\n v2 = *++a1;\n } while (*a1);\n } else {\n return 0;\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(char *a1, uint8_t *a2) {\n char v2;\n unsigned int v3;\n uint8_t *v4;\n char v5;\n v2 = *a1;\n if (*a1) {\n v3 = 0;\n do {\n v4 = a2;\n v5 = *a2;\n if (*a2) {\n while (v5 != v2) {\n v5 = *++v4;\n if (!*v4) goto LABEL_4;\n }\n ++v3;\n }\n LABEL_4:\n v2 = *++a1;\n } while (*a1);\n } else {\n return 0;\n }\n return v3;\n}" + }, + { + "index": 667, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(const char *string, const char *vowels) {\n int count = 0;\n const char *s = string;\n const char *v;\n while (*s) {\n v = vowels;\n while (*v) {\n if (*s == *v) {\n count++;\n break;\n }\n v++;\n }\n s++;\n }\n return count;\n}", + "test": "int main() {\n\n assert(func0(\"corner\", \"AaEeIiOoUu\") == 2);\n\n assert(func0(\"valid\", \"AaEeIiOoUu\") == 2);\n\n assert(func0(\"true\", \"AaEeIiOoUu\") == 2);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmovzbl (%rdi),%ecx\ntest %cl,%cl\nje 132c \nmovzbl (%rsi),%r8d\nxor %r9d,%r9d\nnopw 0x0(%rax,%rax,1)\nmov %rsi,%rdx\nmov %r8d,%eax\ntest %r8b,%r8b\njne 1314 \njmp 131c \nnopl (%rax)\nmovzbl 0x1(%rdx),%eax\nadd $0x1,%rdx\ntest %al,%al\nje 131c \ncmp %cl,%al\njne 1308 \nadd $0x1,%r9d\nmovzbl 0x1(%rdi),%ecx\nadd $0x1,%rdi\ntest %cl,%cl\njne 12f8 \nmov %r9d,%eax\nretq\nxor %r9d,%r9d\nmov %r9d,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\nmovzx ecx, byte ptr [rdi]\ntest cl, cl\njz short loc_124C\nmovzx r8d, byte ptr [rsi]\nxor r9d, r9d\nnop word ptr [rax+rax+00h]\nloc_1218:\nmov rdx, rsi\nmov eax, r8d\ntest r8b, r8b\njnz short loc_1234\njmp short loc_123C\nloc_1228:\nmovzx eax, byte ptr [rdx+1]\nadd rdx, 1\ntest al, al\njz short loc_123C\nloc_1234:\ncmp al, cl\njnz short loc_1228\nadd r9d, 1\nloc_123C:\nmovzx ecx, byte ptr [rdi+1]\nadd rdi, 1\ntest cl, cl\njnz short loc_1218\nmov eax, r9d\nretn\nloc_124C:\nxor r9d, r9d\nmov eax, r9d\nretn", + "ida_pseudo": "__int64 __fastcall func0(char *a1, _BYTE *a2)\n{\n char v2; // cl\n unsigned int v3; // r9d\n _BYTE *v4; // rdx\n char v5; // al\n\n v2 = *a1;\n if ( !*a1 )\n return 0LL;\n v3 = 0;\n do\n {\n v4 = a2;\n v5 = *a2;\n if ( *a2 )\n {\n while ( v5 != v2 )\n {\n v5 = *++v4;\n if ( !v5 )\n goto LABEL_8;\n }\n ++v3;\n }\nLABEL_8:\n v2 = *++a1;\n }\n while ( v2 );\n return v3;\n}", + "ida_strip_asm": "sub_1200:\nendbr64\nmovzx ecx, byte ptr [rdi]\ntest cl, cl\njz short loc_124C\nmovzx r8d, byte ptr [rsi]\nxor r9d, r9d\nnop word ptr [rax+rax+00h]\nloc_1218:\nmov rdx, rsi\nmov eax, r8d\ntest r8b, r8b\njnz short loc_1234\njmp short loc_123C\nloc_1228:\nmovzx eax, byte ptr [rdx+1]\nadd rdx, 1\ntest al, al\njz short loc_123C\nloc_1234:\ncmp al, cl\njnz short loc_1228\nadd r9d, 1\nloc_123C:\nmovzx ecx, byte ptr [rdi+1]\nadd rdi, 1\ntest cl, cl\njnz short loc_1218\nmov eax, r9d\nretn\nloc_124C:\nxor r9d, r9d\nmov eax, r9d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1200(char *a1, _BYTE *a2)\n{\n char v2; // cl\n unsigned int v3; // r9d\n _BYTE *v4; // rdx\n char v5; // al\n\n v2 = *a1;\n if ( !*a1 )\n return 0LL;\n v3 = 0;\n do\n {\n v4 = a2;\n v5 = *a2;\n if ( *a2 )\n {\n while ( v5 != v2 )\n {\n v5 = *++v4;\n if ( !v5 )\n goto LABEL_8;\n }\n ++v3;\n }\nLABEL_8:\n v2 = *++a1;\n }\n while ( v2 );\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1200(char *a1, uint8_t *a2) {\n char v2;\n unsigned int v3;\n uint8_t *v4;\n char v5;\n v2 = *a1;\n if (!*a1) return 0LL;\n v3 = 0;\n do {\n v4 = a2;\n v5 = *a2;\n if (*a2) {\n while (v5 != v2) {\n v5 = *++v4;\n if (!v5) goto LABEL_8;\n }\n ++v3;\n }\n LABEL_8:\n v2 = *++a1;\n } while (v2);\n return v3;\n}", + "ida_pseudo_norm": "long long func0(char *a1, uint8_t *a2) {\n char v2;\n unsigned int v3;\n uint8_t *v4;\n char v5;\n v2 = *a1;\n if (!*a1) return 0LL;\n v3 = 0;\n do {\n v4 = a2;\n v5 = *a2;\n if (*a2) {\n while (v5 != v2) {\n v5 = *++v4;\n if (!v5) goto LABEL_8;\n }\n ++v3;\n }\n LABEL_8:\n v2 = *++a1;\n } while (v2);\n return v3;\n}" + }, + { + "index": 668, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* string, const char* charToReplace) {\n regex_t regex;\n char pattern[10];\n sprintf(pattern, \"%s{2,}\", charToReplace);\n if (regcomp(®ex, pattern, REG_EXTENDED) != 0) {\n return NULL;\n }\n regmatch_t match;\n size_t offset = 0;\n char* result = strdup(string);\n while (regexec(®ex, result + offset, 1, &match, 0) == 0) {\n size_t pos = offset + match.rm_so;\n memmove(result + pos + 1, result + pos + match.rm_eo - match.rm_so,\n strlen(result) - pos - match.rm_eo + match.rm_so + 1);\n offset = pos + 1;\n }\n regfree(®ex);\n return result;\n}", + "test": "int main() {\n\n char* result;\n\n\n\n result = func0(\"peep\", \"e\");\n\n assert(strcmp(result, \"pep\") == 0);\n\n free(result);\n\n\n\n result = func0(\"Greek\", \"e\");\n\n assert(strcmp(result, \"Grek\") == 0);\n\n free(result);\n\n\n\n result = func0(\"Moon\", \"o\");\n\n assert(strcmp(result, \"Mon\") == 0);\n\n free(result);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x90,%rsp\nmov %rdi,-0x88(%rbp)\nmov %rsi,-0x90(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmov -0x90(%rbp),%rdx\nlea -0x12(%rbp),%rax\nlea 0xd41(%rip),%rsi\nmov %rax,%rdi\nmov $0x0,%eax\ncallq 1180 \nlea -0x12(%rbp),%rcx\nlea -0x60(%rbp),%rax\nmov $0x1,%edx\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 1140 \ntest %eax,%eax\nje 12fa \nmov $0x0,%eax\njmpq 13d3 \nmovq $0x0,-0x80(%rbp)\nmov -0x88(%rbp),%rax\nmov %rax,%rdi\ncallq 1190 \nmov %rax,-0x78(%rbp)\njmp 1391 \nmov -0x68(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x80(%rbp),%rax\nadd %rdx,%rax\nmov %rax,-0x70(%rbp)\nmov -0x78(%rbp),%rax\nmov %rax,%rdi\ncallq 1110 \nsub -0x70(%rbp),%rax\nmov %rax,%rdx\nmov -0x64(%rbp),%eax\ncltq\nsub %rax,%rdx\nmov -0x68(%rbp),%eax\ncltq\nadd %rdx,%rax\nlea 0x1(%rax),%rdx\nmov -0x64(%rbp),%eax\nmovslq %eax,%rcx\nmov -0x70(%rbp),%rax\nadd %rax,%rcx\nmov -0x68(%rbp),%eax\ncltq\nsub %rax,%rcx\nmov -0x78(%rbp),%rax\nadd %rax,%rcx\nmov -0x70(%rbp),%rax\nlea 0x1(%rax),%rsi\nmov -0x78(%rbp),%rax\nadd %rsi,%rax\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 1170 \nmov -0x70(%rbp),%rax\nadd $0x1,%rax\nmov %rax,-0x80(%rbp)\nmov -0x78(%rbp),%rdx\nmov -0x80(%rbp),%rax\nlea (%rdx,%rax,1),%rsi\nlea -0x68(%rbp),%rdx\nlea -0x60(%rbp),%rax\nmov $0x0,%r8d\nmov %rdx,%rcx\nmov $0x1,%edx\nmov %rax,%rdi\ncallq 1160 \ntest %eax,%eax\nje 1317 \nlea -0x60(%rbp),%rax\nmov %rax,%rdi\ncallq 1100 \nmov -0x78(%rbp),%rax\nmov -0x8(%rbp),%rdi\nxor %fs:0x28,%rdi\nje 13e7 \ncallq 1120 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 90h\nmov [rbp+var_88], rdi\nmov [rbp+var_90], rsi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rdx, [rbp+var_90]\nlea rax, [rbp+s]\nlea rcx, format; \"%s{2,}\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rcx, [rbp+s]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\ntest eax, eax\njz short loc_12FD\nmov eax, 0\njmp loc_13D6\nloc_12FD:\nmov [rbp+var_80], 0\nmov rax, [rbp+var_88]\nmov rdi, rax; s\ncall _strdup\nmov [rbp+var_78], rax\njmp short loc_1394\nloc_131A:\nmov eax, [rbp+pmatch.rm_so]\nmovsxd rdx, eax\nmov rax, [rbp+var_80]\nadd rax, rdx\nmov [rbp+var_70], rax\nmov rax, [rbp+var_78]\nmov rdi, rax; s\ncall _strlen\nsub rax, [rbp+var_70]\nmov rdx, rax\nmov eax, [rbp+pmatch.rm_eo]\ncdqe\nsub rdx, rax\nmov eax, [rbp+pmatch.rm_so]\ncdqe\nadd rax, rdx\nlea rdx, [rax+1]; n\nmov eax, [rbp+pmatch.rm_eo]\nmovsxd rcx, eax\nmov rax, [rbp+var_70]\nadd rcx, rax\nmov eax, [rbp+pmatch.rm_so]\ncdqe\nsub rcx, rax\nmov rax, [rbp+var_78]\nadd rcx, rax\nmov rax, [rbp+var_70]\nlea rsi, [rax+1]\nmov rax, [rbp+var_78]\nadd rax, rsi\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _memmove\nmov rax, [rbp+var_70]\nadd rax, 1\nmov [rbp+var_80], rax\nloc_1394:\nmov rdx, [rbp+var_78]\nmov rax, [rbp+var_80]\nlea rsi, [rdx+rax]; string\nlea rdx, [rbp+pmatch]\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov rcx, rdx; pmatch\nmov edx, 1; nmatch\nmov rdi, rax; preg\ncall _regexec\ntest eax, eax\njz loc_131A\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nmov rax, [rbp+var_78]\nloc_13D6:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_13EA\ncall ___stack_chk_fail\nlocret_13EA:\nleave\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1, const char *a2)\n{\n size_t v3; // rax\n __int64 v4; // [rsp+10h] [rbp-80h]\n const char *v5; // [rsp+18h] [rbp-78h]\n __int64 v6; // [rsp+20h] [rbp-70h]\n regmatch_t pmatch; // [rsp+28h] [rbp-68h] BYREF\n regex_t preg; // [rsp+30h] [rbp-60h] BYREF\n char s[10]; // [rsp+7Eh] [rbp-12h] BYREF\n unsigned __int64 v10; // [rsp+88h] [rbp-8h]\n\n v10 = __readfsqword(0x28u);\n sprintf(s, \"%s{2,}\", a2);\n if ( regcomp(&preg, s, 1) )\n return 0LL;\n v4 = 0LL;\n v5 = strdup(a1);\n while ( !regexec(&preg, &v5[v4], 1uLL, &pmatch, 0) )\n {\n v6 = pmatch.rm_so + v4;\n v3 = strlen(v5);\n memmove((void *)&v5[v6 + 1], &v5[v6 + pmatch.rm_eo - pmatch.rm_so], v3 - v6 - pmatch.rm_eo + pmatch.rm_so + 1);\n v4 = v6 + 1;\n }\n regfree(&preg);\n return v5;\n}", + "ida_strip_asm": "sub_1289:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 90h\nmov [rbp+var_88], rdi\nmov [rbp+var_90], rsi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rdx, [rbp+var_90]\nlea rax, [rbp+s]\nlea rcx, format; \"%s{2,}\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rcx, [rbp+s]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\ntest eax, eax\njz short loc_12FD\nmov eax, 0\njmp loc_13D6\nloc_12FD:\nmov [rbp+var_80], 0\nmov rax, [rbp+var_88]\nmov rdi, rax; s\ncall _strdup\nmov [rbp+var_78], rax\njmp short loc_1394\nloc_131A:\nmov eax, [rbp+pmatch.rm_so]\nmovsxd rdx, eax\nmov rax, [rbp+var_80]\nadd rax, rdx\nmov [rbp+var_70], rax\nmov rax, [rbp+var_78]\nmov rdi, rax; s\ncall _strlen\nsub rax, [rbp+var_70]\nmov rdx, rax\nmov eax, [rbp+pmatch.rm_eo]\ncdqe\nsub rdx, rax\nmov eax, [rbp+pmatch.rm_so]\ncdqe\nadd rax, rdx\nlea rdx, [rax+1]; n\nmov eax, [rbp+pmatch.rm_eo]\nmovsxd rcx, eax\nmov rax, [rbp+var_70]\nadd rcx, rax\nmov eax, [rbp+pmatch.rm_so]\ncdqe\nsub rcx, rax\nmov rax, [rbp+var_78]\nadd rcx, rax\nmov rax, [rbp+var_70]\nlea rsi, [rax+1]\nmov rax, [rbp+var_78]\nadd rax, rsi\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _memmove\nmov rax, [rbp+var_70]\nadd rax, 1\nmov [rbp+var_80], rax\nloc_1394:\nmov rdx, [rbp+var_78]\nmov rax, [rbp+var_80]\nlea rsi, [rdx+rax]; string\nlea rdx, [rbp+pmatch]\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov rcx, rdx; pmatch\nmov edx, 1; nmatch\nmov rdi, rax; preg\ncall _regexec\ntest eax, eax\njz loc_131A\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nmov rax, [rbp+var_78]\nloc_13D6:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_13EA\ncall ___stack_chk_fail\nlocret_13EA:\nleave\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1289(const char *a1, const char *a2)\n{\n size_t v3; // rax\n __int64 v4; // [rsp+10h] [rbp-80h]\n const char *v5; // [rsp+18h] [rbp-78h]\n __int64 v6; // [rsp+20h] [rbp-70h]\n regmatch_t pmatch; // [rsp+28h] [rbp-68h] BYREF\n regex_t preg; // [rsp+30h] [rbp-60h] BYREF\n char s[10]; // [rsp+7Eh] [rbp-12h] BYREF\n unsigned __int64 v10; // [rsp+88h] [rbp-8h]\n\n v10 = __readfsqword(0x28u);\n sprintf(s, \"%s{2,}\", a2);\n if ( regcomp(&preg, s, 1) )\n return 0LL;\n v4 = 0LL;\n v5 = strdup(a1);\n while ( !regexec(&preg, &v5[v4], 1uLL, &pmatch, 0) )\n {\n v6 = pmatch.rm_so + v4;\n v3 = strlen(v5);\n memmove((void *)&v5[v6 + 1], &v5[v6 + pmatch.rm_eo - pmatch.rm_so], v3 - v6 - pmatch.rm_eo + pmatch.rm_so + 1);\n v4 = v6 + 1;\n }\n regfree(&preg);\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1289(const char *a1, const char *a2) {\n unsigned int v3;\n long long v4;\n const char *v5;\n long long v6;\n regmatch_t pmatch;\n regex_t preg;\n char s[10];\n unsigned long long v10;\n v10 = __readfsqword(40u);\n sprintf(s, \"%s{2,}\", a2);\n if (regcomp(&preg, s, 1)) return 0LL;\n v4 = 0LL;\n v5 = strdup(a1);\n while (!regexec(&preg, &v5[v4], 1uLL, &pmatch, 0)) {\n v6 = pmatch.rm_so + v4;\n v3 = strlen(v5);\n memmove((void *)&v5[v6 + 1], &v5[v6 + pmatch.rm_eo - pmatch.rm_so],\n v3 - v6 - pmatch.rm_eo + pmatch.rm_so + 1);\n v4 = v6 + 1;\n }\n regfree(&preg);\n return v5;\n}", + "ida_pseudo_norm": "const char *func0(const char *a1, const char *a2) {\n unsigned int v3;\n long long v4;\n const char *v5;\n long long v6;\n regmatch_t pmatch;\n regex_t preg;\n char s[10];\n unsigned long long v10;\n v10 = __readfsqword(40u);\n sprintf(s, \"%s{2,}\", a2);\n if (regcomp(&preg, s, 1)) return 0LL;\n v4 = 0LL;\n v5 = strdup(a1);\n while (!regexec(&preg, &v5[v4], 1uLL, &pmatch, 0)) {\n v6 = pmatch.rm_so + v4;\n v3 = strlen(v5);\n memmove((void *)&v5[v6 + 1], &v5[v6 + pmatch.rm_eo - pmatch.rm_so],\n v3 - v6 - pmatch.rm_eo + pmatch.rm_so + 1);\n v4 = v6 + 1;\n }\n regfree(&preg);\n return v5;\n}" + }, + { + "index": 668, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* string, const char* charToReplace) {\n regex_t regex;\n char pattern[10];\n sprintf(pattern, \"%s{2,}\", charToReplace);\n if (regcomp(®ex, pattern, REG_EXTENDED) != 0) {\n return NULL;\n }\n regmatch_t match;\n size_t offset = 0;\n char* result = strdup(string);\n while (regexec(®ex, result + offset, 1, &match, 0) == 0) {\n size_t pos = offset + match.rm_so;\n memmove(result + pos + 1, result + pos + match.rm_eo - match.rm_so,\n strlen(result) - pos - match.rm_eo + match.rm_so + 1);\n offset = pos + 1;\n }\n regfree(®ex);\n return result;\n}", + "test": "int main() {\n\n char* result;\n\n\n\n result = func0(\"peep\", \"e\");\n\n assert(strcmp(result, \"pep\") == 0);\n\n free(result);\n\n\n\n result = func0(\"Greek\", \"e\");\n\n assert(strcmp(result, \"Grek\") == 0);\n\n free(result);\n\n\n\n result = func0(\"Moon\", \"o\");\n\n assert(strcmp(result, \"Mon\") == 0);\n\n free(result);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nsub $0x70,%rsp\nmov %rdi,%rbx\nmov %rsi,%r8\nmov %fs:0x28,%rax\nmov %rax,0x68(%rsp)\nxor %eax,%eax\nlea 0x5e(%rsp),%rbp\nlea 0xd8d(%rip),%rcx\nmov $0xa,%edx\nmov $0x1,%esi\nmov %rbp,%rdi\ncallq 1150 <__sprintf_chk@plt>\nlea 0x10(%rsp),%rdi\nmov $0x1,%edx\nmov %rbp,%rsi\ncallq 1110 \nmov $0x0,%ebp\ntest %eax,%eax\njne 1330 \nmov %rbx,%rdi\ncallq 1140 \nmov %rax,%rbp\nmov $0x0,%ebx\nlea 0x8(%rsp),%r12\nlea 0x0(%rbp,%rbx,1),%rsi\nlea 0x10(%rsp),%rdi\nmov $0x0,%r8d\nmov %r12,%rcx\nmov $0x1,%edx\ncallq 1120 \ntest %eax,%eax\njne 1326 \nmovslq 0x8(%rsp),%rdx\nlea (%rdx,%rbx,1),%r8\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nmov %rbp,%rdi\nrepnz scas %es:(%rdi),%al\nnot %rcx\nmovslq 0xc(%rsp),%rax\nlea (%rax,%rbx,1),%rsi\nadd %rbp,%rsi\nlea 0x1(%r8),%rbx\nadd $0x1,%rdx\nsub %rax,%rdx\nsub %r8,%rdx\nlea -0x1(%rcx,%rdx,1),%rdx\nlea 0x0(%rbp,%rbx,1),%rdi\ncallq 1130 \njmp 12bd \nlea 0x10(%rsp),%rdi\ncallq 10e0 \nmov 0x68(%rsp),%rax\nxor %fs:0x28,%rax\njne 134c \nmov %rbp,%rax\nadd $0x70,%rsp\npop %rbx\npop %rbp\npop %r12\nretq\ncallq 10f0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 78h\nmov rbx, rdi\nmov r8, rsi\nmov rax, fs:28h\nmov [rsp+0A8h+var_40], rax\nxor eax, eax\nlea rbp, [rsp+0A8h+pattern]\nlea rcx, aS2; \"%s{2,}\"\nmov edx, 0Ah\nmov esi, 2\nmov rdi, rbp\ncall ___sprintf_chk\nlea rdi, [rsp+0A8h+preg]; preg\nmov edx, 1; cflags\nmov rsi, rbp; pattern\ncall _regcomp\nmov r12d, 0\ntest eax, eax\njnz loc_1383\nmov rdi, rbx; s\ncall _strlen\nlea r13, [rax+1]\nmov rdi, rbx; s\ncall _strdup\nmov r12, rax\nmov ebp, 0\nlea r14, [rsp+0A8h+pmatch]\njmp short loc_1359\nloc_1312:\nmovsxd rbx, [rsp+0A8h+pmatch.rm_so]\nlea r15, [rbx+rbp]\nmov rdi, r12; s\ncall _strlen\nmov rdi, rax\nmovsxd rax, [rsp+0A8h+pmatch.rm_eo]\nlea rsi, [rax+rbp]\nadd rsi, r12\nlea rbp, [r15+1]\ncmp rbp, r13\nmov rcx, r13\ncmovnb rcx, rbp\nsub rcx, rbp\nlea rdx, [rbx+1]\nsub rdx, rax\nsub rdx, r15\nadd rdx, rdi\nlea rdi, [r12+rbp]\ncall ___memmove_chk\nloc_1359:\nlea rsi, [r12+rbp]; string\nlea rdi, [rsp+0A8h+preg]; preg\nmov r8d, 0; eflags\nmov rcx, r14; pmatch\nmov edx, 1; nmatch\ncall _regexec\ntest eax, eax\njz short loc_1312\nlea rdi, [rsp+0A8h+preg]; preg\ncall _regfree\nloc_1383:\nmov rax, [rsp+0A8h+var_40]\nsub rax, fs:28h\njnz short loc_13A5\nmov rax, r12\nadd rsp, 78h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_13A5:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(char *s, const char *a2)\n{\n char *v2; // r12\n size_t v3; // r13\n __int64 i; // rbp\n __int64 rm_so; // rbx\n __int64 v6; // r15\n size_t v7; // rdi\n char *v8; // rsi\n size_t v9; // rcx\n regmatch_t pmatch; // [rsp+8h] [rbp-A0h] BYREF\n regex_t preg; // [rsp+10h] [rbp-98h] BYREF\n char pattern[10]; // [rsp+5Eh] [rbp-4Ah] BYREF\n unsigned __int64 v14; // [rsp+68h] [rbp-40h]\n\n v14 = __readfsqword(0x28u);\n __sprintf_chk(pattern, 2LL, 10LL, \"%s{2,}\", a2);\n v2 = 0LL;\n if ( !regcomp(&preg, pattern, 1) )\n {\n v3 = strlen(s) + 1;\n v2 = strdup(s);\n for ( i = 0LL;\n !regexec(&preg, &v2[i], 1uLL, &pmatch, 0);\n __memmove_chk(&v2[i], v8, v7 + rm_so + 1 - pmatch.rm_eo - v6, v9 - i) )\n {\n rm_so = pmatch.rm_so;\n v6 = pmatch.rm_so + i;\n v7 = strlen(v2);\n v8 = &v2[pmatch.rm_eo + i];\n i = v6 + 1;\n v9 = v3;\n if ( v6 + 1 >= v3 )\n v9 = v6 + 1;\n }\n regfree(&preg);\n }\n return v2;\n}", + "ida_strip_asm": "sub_1289:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 78h\nmov rbx, rdi\nmov r8, rsi\nmov rax, fs:28h\nmov [rsp+0A8h+var_40], rax\nxor eax, eax\nlea rbp, [rsp+0A8h+pattern]\nlea rcx, aS2; \"%s{2,}\"\nmov edx, 0Ah\nmov esi, 2\nmov rdi, rbp\ncall ___sprintf_chk\nlea rdi, [rsp+0A8h+preg]; preg\nmov edx, 1; cflags\nmov rsi, rbp; pattern\ncall _regcomp\nmov r12d, 0\ntest eax, eax\njnz loc_1383\nmov rdi, rbx; s\ncall _strlen\nlea r13, [rax+1]\nmov rdi, rbx; s\ncall _strdup\nmov r12, rax\nmov ebp, 0\nlea r14, [rsp+0A8h+pmatch]\njmp short loc_1359\nloc_1312:\nmovsxd rbx, [rsp+0A8h+pmatch.rm_so]\nlea r15, [rbx+rbp]\nmov rdi, r12; s\ncall _strlen\nmov rdi, rax\nmovsxd rax, [rsp+0A8h+pmatch.rm_eo]\nlea rsi, [rax+rbp]\nadd rsi, r12\nlea rbp, [r15+1]\ncmp rbp, r13\nmov rcx, r13\ncmovnb rcx, rbp\nsub rcx, rbp\nlea rdx, [rbx+1]\nsub rdx, rax\nsub rdx, r15\nadd rdx, rdi\nlea rdi, [r12+rbp]\ncall ___memmove_chk\nloc_1359:\nlea rsi, [r12+rbp]; string\nlea rdi, [rsp+0A8h+preg]; preg\nmov r8d, 0; eflags\nmov rcx, r14; pmatch\nmov edx, 1; nmatch\ncall _regexec\ntest eax, eax\njz short loc_1312\nlea rdi, [rsp+0A8h+preg]; preg\ncall _regfree\nloc_1383:\nmov rax, [rsp+0A8h+var_40]\nsub rax, fs:28h\njnz short loc_13A5\nmov rax, r12\nadd rsp, 78h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_13A5:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_1289(char *s, const char *a2)\n{\n char *v2; // r12\n size_t v3; // r13\n __int64 i; // rbp\n __int64 rm_so; // rbx\n __int64 v6; // r15\n size_t v7; // rdi\n char *v8; // rsi\n size_t v9; // rcx\n regmatch_t pmatch; // [rsp+8h] [rbp-A0h] BYREF\n regex_t preg; // [rsp+10h] [rbp-98h] BYREF\n char pattern[10]; // [rsp+5Eh] [rbp-4Ah] BYREF\n unsigned __int64 v14; // [rsp+68h] [rbp-40h]\n\n v14 = __readfsqword(0x28u);\n __sprintf_chk(pattern, 2LL, 10LL, \"%s{2,}\", a2);\n v2 = 0LL;\n if ( !regcomp(&preg, pattern, 1) )\n {\n v3 = strlen(s) + 1;\n v2 = strdup(s);\n for ( i = 0LL;\n !regexec(&preg, &v2[i], 1uLL, &pmatch, 0);\n __memmove_chk(&v2[i], v8, v7 + rm_so + 1 - pmatch.rm_eo - v6, v9 - i) )\n {\n rm_so = pmatch.rm_so;\n v6 = pmatch.rm_so + i;\n v7 = strlen(v2);\n v8 = &v2[pmatch.rm_eo + i];\n i = v6 + 1;\n v9 = v3;\n if ( v6 + 1 >= v3 )\n v9 = v6 + 1;\n }\n regfree(&preg);\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1289(char *s, const char *a2) {\n char *v2;\n unsigned int v3;\n long long i;\n long long rm_so;\n long long v6;\n unsigned int v7;\n char *v8;\n unsigned int v9;\n regmatch_t pmatch;\n regex_t preg;\n char pattern[10];\n unsigned long long v14;\n v14 = __readfsqword(40u);\n __sprintf_chk(pattern, 2LL, 10LL, \"%s{2,}\", a2);\n v2 = 0LL;\n if (!regcomp(&preg, pattern, 1)) {\n v3 = strlen(s) + 1;\n v2 = strdup(s);\n for (i = 0LL; !regexec(&preg, &v2[i], 1uLL, &pmatch, 0); __memmove_chk(\n &v2[i], v8, v7 + rm_so + 1 - pmatch.rm_eo - v6, v9 - i)) {\n rm_so = pmatch.rm_so;\n v6 = pmatch.rm_so + i;\n v7 = strlen(v2);\n v8 = &v2[pmatch.rm_eo + i];\n i = v6 + 1;\n v9 = v3;\n if (v6 + 1 >= v3) v9 = v6 + 1;\n }\n regfree(&preg);\n }\n return v2;\n}", + "ida_pseudo_norm": "char *func0(char *s, const char *a2) {\n char *v2;\n unsigned int v3;\n long long i;\n long long rm_so;\n long long v6;\n unsigned int v7;\n char *v8;\n unsigned int v9;\n regmatch_t pmatch;\n regex_t preg;\n char pattern[10];\n unsigned long long v14;\n v14 = __readfsqword(40u);\n __sprintf_chk(pattern, 2LL, 10LL, \"%s{2,}\", a2);\n v2 = 0LL;\n if (!regcomp(&preg, pattern, 1)) {\n v3 = strlen(s) + 1;\n v2 = strdup(s);\n for (i = 0LL; !regexec(&preg, &v2[i], 1uLL, &pmatch, 0); __memmove_chk(\n &v2[i], v8, v7 + rm_so + 1 - pmatch.rm_eo - v6, v9 - i)) {\n rm_so = pmatch.rm_so;\n v6 = pmatch.rm_so + i;\n v7 = strlen(v2);\n v8 = &v2[pmatch.rm_eo + i];\n i = v6 + 1;\n v9 = v3;\n if (v6 + 1 >= v3) v9 = v6 + 1;\n }\n regfree(&preg);\n }\n return v2;\n}" + }, + { + "index": 668, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* string, const char* charToReplace) {\n regex_t regex;\n char pattern[10];\n sprintf(pattern, \"%s{2,}\", charToReplace);\n if (regcomp(®ex, pattern, REG_EXTENDED) != 0) {\n return NULL;\n }\n regmatch_t match;\n size_t offset = 0;\n char* result = strdup(string);\n while (regexec(®ex, result + offset, 1, &match, 0) == 0) {\n size_t pos = offset + match.rm_so;\n memmove(result + pos + 1, result + pos + match.rm_eo - match.rm_so,\n strlen(result) - pos - match.rm_eo + match.rm_so + 1);\n offset = pos + 1;\n }\n regfree(®ex);\n return result;\n}", + "test": "int main() {\n\n char* result;\n\n\n\n result = func0(\"peep\", \"e\");\n\n assert(strcmp(result, \"pep\") == 0);\n\n free(result);\n\n\n\n result = func0(\"Greek\", \"e\");\n\n assert(strcmp(result, \"Grek\") == 0);\n\n free(result);\n\n\n\n result = func0(\"Moon\", \"o\");\n\n assert(strcmp(result, \"Mon\") == 0);\n\n free(result);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov %rsi,%r8\nmov $0xa,%edx\nmov %rdi,%r13\npush %r12\nlea 0xc7a(%rip),%rcx\nmov $0x1,%esi\npush %rbp\npush %rbx\nsub $0x78,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x68(%rsp)\nxor %eax,%eax\nlea 0x5e(%rsp),%r12\nlea 0x10(%rsp),%rbp\nmov %r12,%rdi\ncallq 1150 <__sprintf_chk@plt>\nmov %r12,%rsi\nmov $0x1,%edx\nmov %rbp,%rdi\ncallq 1110 \nxor %r12d,%r12d\ntest %eax,%eax\njne 1486 \nmov %r13,%rdi\nxor %ebx,%ebx\nlea 0x8(%rsp),%r13\ncallq 1140 \nmov %rax,%r12\nmov %rax,%r9\njmp 1460 \nnopl 0x0(%rax)\nmovslq 0x8(%rsp),%rcx\nmov %r12,%rdx\nlea (%rcx,%rbx,1),%rdi\nmov (%rdx),%esi\nadd $0x4,%rdx\nlea -0x1010101(%rsi),%eax\nnot %esi\nand %esi,%eax\nand $0x80808080,%eax\nje 13fc \nmov %eax,%esi\nshr $0x10,%esi\ntest $0x8080,%eax\ncmove %esi,%eax\nlea 0x2(%rdx),%rsi\ncmove %rsi,%rdx\nmov %eax,%esi\nadd %al,%sil\nmovslq 0xc(%rsp),%rax\nsbb $0x3,%rdx\nadd $0x1,%rcx\nlea (%rax,%rbx,1),%rsi\nsub %rax,%rcx\nlea 0x1(%rdi),%rbx\nsub %r12,%rdx\nsub %rdi,%rcx\nlea (%r12,%rbx,1),%r9\nadd %r12,%rsi\nmov %r9,%rdi\nadd %rcx,%rdx\ncallq 1130 \nmov %rax,%r9\nxor %r8d,%r8d\nmov %r13,%rcx\nmov $0x1,%edx\nmov %r9,%rsi\nmov %rbp,%rdi\ncallq 1120 \ntest %eax,%eax\nje 13f0 \nmov %rbp,%rdi\ncallq 10e0 \nmov 0x68(%rsp),%rax\nxor %fs:0x28,%rax\njne 14a4 \nadd $0x78,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\ncallq 10f0 <__stack_chk_fail@plt>\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov r8, rsi\nmov edx, 0Ah\nlea rcx, aS2; \"%s{2,}\"\npush r14\nmov esi, 2\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 88h\nmov rax, fs:28h\nmov [rsp+0B8h+var_40], rax\nxor eax, eax\nlea rbp, [rsp+0B8h+pattern]\nlea r13, [rsp+0B8h+preg]\nmov rdi, rbp\ncall ___sprintf_chk\nmov rsi, rbp; pattern\nmov edx, 1; cflags\nmov rdi, r13; preg\ncall _regcomp\nxor ebp, ebp\ntest eax, eax\njnz loc_14A7\nmov rdi, rbx; s\nxor r15d, r15d\ncall _strlen\nmov rdi, rbx; s\nlea r12, [rax+1]\ncall _strdup\nmov rbp, rax\nmov rdi, rax\nlea rax, [rsp+0B8h+var_A0]\nmov [rsp+0B8h+pmatch], rax\njmp short loc_1483\nloc_1438:\nmov rdi, rbp; s\nmovsxd rbx, [rsp+0B8h+var_A0]\ncall _strlen\nmov rcx, r12\nmov rdi, rax\nmovsxd rax, [rsp+0B8h+var_9C]\nlea r14, [rbx+r15]\nlea rdx, [rbx+1]\nlea rsi, [rax+r15]\nlea r15, [r14+1]\nadd rsi, rbp\ncmp r15, r12\ncmovnb rcx, r15\nsub rdx, rax\nsub rdx, r14\nadd rdx, rdi\nsub rcx, r15\nlea rdi, [rbp+r15+0]\ncall ___memmove_chk\nmov rdi, rax\nloc_1483:\nmov rcx, [rsp+0B8h+pmatch]; pmatch\nxor r8d, r8d; eflags\nmov rsi, rdi; string\nmov edx, 1; nmatch\nmov rdi, r13; preg\ncall _regexec\ntest eax, eax\njz short loc_1438\nmov rdi, r13; preg\ncall _regfree\nloc_14A7:\nmov rax, [rsp+0B8h+var_40]\nsub rax, fs:28h\njnz short loc_14CC\nadd rsp, 88h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14CC:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(char *s, const char *a2)\n{\n char *v2; // rbp\n size_t v3; // r15\n size_t v4; // r12\n int i; // eax\n __int64 rm_so; // rbx\n size_t v7; // rax\n size_t v8; // rcx\n size_t v9; // r14\n size_t v10; // rsi\n char *v11; // rsi\n const char *v12; // rdi\n regmatch_t v14; // [rsp+18h] [rbp-A0h] BYREF\n regex_t preg; // [rsp+20h] [rbp-98h] BYREF\n char pattern[10]; // [rsp+6Eh] [rbp-4Ah] BYREF\n unsigned __int64 v17; // [rsp+78h] [rbp-40h]\n\n v17 = __readfsqword(0x28u);\n __sprintf_chk(pattern, 2LL, 10LL, \"%s{2,}\", a2);\n v2 = 0LL;\n if ( !regcomp(&preg, pattern, 1) )\n {\n v3 = 0LL;\n v4 = strlen(s) + 1;\n v2 = strdup(s);\n for ( i = regexec(&preg, v2, 1uLL, &v14, 0); !i; i = regexec(&preg, v12, 1uLL, &v14, 0) )\n {\n rm_so = v14.rm_so;\n v7 = strlen(v2);\n v8 = v4;\n v9 = rm_so + v3;\n v10 = v14.rm_eo + v3;\n v3 += rm_so + 1;\n v11 = &v2[v10];\n if ( v3 >= v4 )\n v8 = v3;\n v12 = (const char *)__memmove_chk(&v2[v3], v11, v7 + rm_so + 1 - v14.rm_eo - v9, v8 - v3);\n }\n regfree(&preg);\n }\n return v2;\n}", + "ida_strip_asm": "sub_13A0:\nendbr64\npush r15\nmov r8, rsi\nmov edx, 0Ah\nlea rcx, aS2; \"%s{2,}\"\npush r14\nmov esi, 2\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 88h\nmov rax, fs:28h\nmov [rsp+0B8h+var_40], rax\nxor eax, eax\nlea rbp, [rsp+0B8h+pattern]\nlea r13, [rsp+0B8h+preg]\nmov rdi, rbp\ncall ___sprintf_chk\nmov rsi, rbp; pattern\nmov edx, 1; cflags\nmov rdi, r13; preg\ncall _regcomp\nxor ebp, ebp\ntest eax, eax\njnz loc_14A7\nmov rdi, rbx; s\nxor r15d, r15d\ncall _strlen\nmov rdi, rbx; s\nlea r12, [rax+1]\ncall _strdup\nmov rbp, rax\nmov rdi, rax\nlea rax, [rsp+0B8h+var_A0]\nmov [rsp+0B8h+pmatch], rax\njmp short loc_1483\nloc_1438:\nmov rdi, rbp; s\nmovsxd rbx, [rsp+0B8h+var_A0]\ncall _strlen\nmov rcx, r12\nmov rdi, rax\nmovsxd rax, [rsp+0B8h+var_9C]\nlea r14, [rbx+r15]\nlea rdx, [rbx+1]\nlea rsi, [rax+r15]\nlea r15, [r14+1]\nadd rsi, rbp\ncmp r15, r12\ncmovnb rcx, r15\nsub rdx, rax\nsub rdx, r14\nadd rdx, rdi\nsub rcx, r15\nlea rdi, [rbp+r15+0]\ncall ___memmove_chk\nmov rdi, rax\nloc_1483:\nmov rcx, [rsp+0B8h+pmatch]; pmatch\nxor r8d, r8d; eflags\nmov rsi, rdi; string\nmov edx, 1; nmatch\nmov rdi, r13; preg\ncall _regexec\ntest eax, eax\njz short loc_1438\nmov rdi, r13; preg\ncall _regfree\nloc_14A7:\nmov rax, [rsp+0B8h+var_40]\nsub rax, fs:28h\njnz short loc_14CC\nadd rsp, 88h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14CC:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_13A0(char *s, const char *a2)\n{\n char *v2; // rbp\n size_t v3; // r15\n size_t v4; // r12\n int i; // eax\n __int64 rm_so; // rbx\n size_t v7; // rax\n size_t v8; // rcx\n size_t v9; // r14\n size_t v10; // rsi\n char *v11; // rsi\n const char *v12; // rdi\n regmatch_t v14; // [rsp+18h] [rbp-A0h] BYREF\n regex_t preg; // [rsp+20h] [rbp-98h] BYREF\n char pattern[10]; // [rsp+6Eh] [rbp-4Ah] BYREF\n unsigned __int64 v17; // [rsp+78h] [rbp-40h]\n\n v17 = __readfsqword(0x28u);\n __sprintf_chk(pattern, 2LL, 10LL, \"%s{2,}\", a2);\n v2 = 0LL;\n if ( !regcomp(&preg, pattern, 1) )\n {\n v3 = 0LL;\n v4 = strlen(s) + 1;\n v2 = strdup(s);\n for ( i = regexec(&preg, v2, 1uLL, &v14, 0); !i; i = regexec(&preg, v12, 1uLL, &v14, 0) )\n {\n rm_so = v14.rm_so;\n v7 = strlen(v2);\n v8 = v4;\n v9 = rm_so + v3;\n v10 = v14.rm_eo + v3;\n v3 += rm_so + 1;\n v11 = &v2[v10];\n if ( v3 >= v4 )\n v8 = v3;\n v12 = (const char *)__memmove_chk(&v2[v3], v11, v7 + rm_so + 1 - v14.rm_eo - v9, v8 - v3);\n }\n regfree(&preg);\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_13A0(char *s, const char *a2) {\n char *v2;\n unsigned int v3;\n unsigned int v4;\n int i;\n long long rm_so;\n unsigned int v7;\n unsigned int v8;\n unsigned int v9;\n unsigned int v10;\n char *v11;\n const char *v12;\n regmatch_t v14;\n regex_t preg;\n char pattern[10];\n unsigned long long v17;\n v17 = __readfsqword(40u);\n __sprintf_chk(pattern, 2LL, 10LL, \"%s{2,}\", a2);\n v2 = 0LL;\n if (!regcomp(&preg, pattern, 1)) {\n v3 = 0LL;\n v4 = strlen(s) + 1;\n v2 = strdup(s);\n for (i = regexec(&preg, v2, 1uLL, &v14, 0); !i;\n i = regexec(&preg, v12, 1uLL, &v14, 0)) {\n rm_so = v14.rm_so;\n v7 = strlen(v2);\n v8 = v4;\n v9 = rm_so + v3;\n v10 = v14.rm_eo + v3;\n v3 += rm_so + 1;\n v11 = &v2[v10];\n if (v3 >= v4) v8 = v3;\n v12 = (const char *)__memmove_chk(\n &v2[v3], v11, v7 + rm_so + 1 - v14.rm_eo - v9, v8 - v3);\n }\n regfree(&preg);\n }\n return v2;\n}", + "ida_pseudo_norm": "char *func0(char *s, const char *a2) {\n char *v2;\n unsigned int v3;\n unsigned int v4;\n int i;\n long long rm_so;\n unsigned int v7;\n unsigned int v8;\n unsigned int v9;\n unsigned int v10;\n char *v11;\n const char *v12;\n regmatch_t v14;\n regex_t preg;\n char pattern[10];\n unsigned long long v17;\n v17 = __readfsqword(40u);\n __sprintf_chk(pattern, 2LL, 10LL, \"%s{2,}\", a2);\n v2 = 0LL;\n if (!regcomp(&preg, pattern, 1)) {\n v3 = 0LL;\n v4 = strlen(s) + 1;\n v2 = strdup(s);\n for (i = regexec(&preg, v2, 1uLL, &v14, 0); !i;\n i = regexec(&preg, v12, 1uLL, &v14, 0)) {\n rm_so = v14.rm_so;\n v7 = strlen(v2);\n v8 = v4;\n v9 = rm_so + v3;\n v10 = v14.rm_eo + v3;\n v3 += rm_so + 1;\n v11 = &v2[v10];\n if (v3 >= v4) v8 = v3;\n v12 = (const char *)__memmove_chk(\n &v2[v3], v11, v7 + rm_so + 1 - v14.rm_eo - v9, v8 - v3);\n }\n regfree(&preg);\n }\n return v2;\n}" + }, + { + "index": 668, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* string, const char* charToReplace) {\n regex_t regex;\n char pattern[10];\n sprintf(pattern, \"%s{2,}\", charToReplace);\n if (regcomp(®ex, pattern, REG_EXTENDED) != 0) {\n return NULL;\n }\n regmatch_t match;\n size_t offset = 0;\n char* result = strdup(string);\n while (regexec(®ex, result + offset, 1, &match, 0) == 0) {\n size_t pos = offset + match.rm_so;\n memmove(result + pos + 1, result + pos + match.rm_eo - match.rm_so,\n strlen(result) - pos - match.rm_eo + match.rm_so + 1);\n offset = pos + 1;\n }\n regfree(®ex);\n return result;\n}", + "test": "int main() {\n\n char* result;\n\n\n\n result = func0(\"peep\", \"e\");\n\n assert(strcmp(result, \"pep\") == 0);\n\n free(result);\n\n\n\n result = func0(\"Greek\", \"e\");\n\n assert(strcmp(result, \"Grek\") == 0);\n\n free(result);\n\n\n\n result = func0(\"Moon\", \"o\");\n\n assert(strcmp(result, \"Mon\") == 0);\n\n free(result);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov %rsi,%r8\nmov $0xa,%edx\nmov %rdi,%r13\npush %r12\nlea 0xc7a(%rip),%rcx\nmov $0x1,%esi\npush %rbp\npush %rbx\nsub $0x78,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x68(%rsp)\nxor %eax,%eax\nlea 0x5e(%rsp),%r12\nlea 0x10(%rsp),%rbp\nmov %r12,%rdi\ncallq 1150 <__sprintf_chk@plt>\nmov %r12,%rsi\nmov $0x1,%edx\nmov %rbp,%rdi\ncallq 1110 \nxor %r12d,%r12d\ntest %eax,%eax\njne 1486 \nmov %r13,%rdi\nxor %ebx,%ebx\nlea 0x8(%rsp),%r13\ncallq 1140 \nmov %rax,%r12\nmov %rax,%r9\njmp 1460 \nnopl 0x0(%rax)\nmovslq 0x8(%rsp),%rcx\nmov %r12,%rdx\nlea (%rcx,%rbx,1),%rdi\nmov (%rdx),%esi\nadd $0x4,%rdx\nlea -0x1010101(%rsi),%eax\nnot %esi\nand %esi,%eax\nand $0x80808080,%eax\nje 13fc \nmov %eax,%esi\nshr $0x10,%esi\ntest $0x8080,%eax\ncmove %esi,%eax\nlea 0x2(%rdx),%rsi\ncmove %rsi,%rdx\nmov %eax,%esi\nadd %al,%sil\nmovslq 0xc(%rsp),%rax\nsbb $0x3,%rdx\nadd $0x1,%rcx\nlea (%rax,%rbx,1),%rsi\nsub %rax,%rcx\nlea 0x1(%rdi),%rbx\nsub %r12,%rdx\nsub %rdi,%rcx\nlea (%r12,%rbx,1),%r9\nadd %r12,%rsi\nmov %r9,%rdi\nadd %rcx,%rdx\ncallq 1130 \nmov %rax,%r9\nxor %r8d,%r8d\nmov %r13,%rcx\nmov $0x1,%edx\nmov %r9,%rsi\nmov %rbp,%rdi\ncallq 1120 \ntest %eax,%eax\nje 13f0 \nmov %rbp,%rdi\ncallq 10e0 \nmov 0x68(%rsp),%rax\nxor %fs:0x28,%rax\njne 14a4 \nadd $0x78,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\ncallq 10f0 <__stack_chk_fail@plt>\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov r8, rsi\nmov edx, 0Ah\nlea rcx, aS2; \"%s{2,}\"\npush r14\nmov esi, 2\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 88h\nmov rax, fs:28h\nmov [rsp+0B8h+var_40], rax\nxor eax, eax\nlea rbp, [rsp+0B8h+pattern]\nlea r13, [rsp+0B8h+preg]\nmov rdi, rbp\ncall ___sprintf_chk\nmov rsi, rbp; pattern\nmov edx, 1; cflags\nmov rdi, r13; preg\ncall _regcomp\nxor ebp, ebp\ntest eax, eax\njnz loc_14A7\nmov rdi, rbx; s\nxor r15d, r15d\ncall _strlen\nmov rdi, rbx; s\nlea r12, [rax+1]\ncall _strdup\nmov rbp, rax\nmov rdi, rax\nlea rax, [rsp+0B8h+var_A0]\nmov [rsp+0B8h+pmatch], rax\njmp short loc_1483\nloc_1438:\nmov rdi, rbp; s\nmovsxd rbx, [rsp+0B8h+var_A0]\ncall _strlen\nmov rcx, r12\nmov rdi, rax\nmovsxd rax, [rsp+0B8h+var_9C]\nlea r14, [rbx+r15]\nlea rdx, [rbx+1]\nlea rsi, [rax+r15]\nlea r15, [r14+1]\nadd rsi, rbp\ncmp r15, r12\ncmovnb rcx, r15\nsub rdx, rax\nsub rdx, r14\nadd rdx, rdi\nsub rcx, r15\nlea rdi, [rbp+r15+0]\ncall ___memmove_chk\nmov rdi, rax\nloc_1483:\nmov rcx, [rsp+0B8h+pmatch]; pmatch\nxor r8d, r8d; eflags\nmov rsi, rdi; string\nmov edx, 1; nmatch\nmov rdi, r13; preg\ncall _regexec\ntest eax, eax\njz short loc_1438\nmov rdi, r13; preg\ncall _regfree\nloc_14A7:\nmov rax, [rsp+0B8h+var_40]\nsub rax, fs:28h\njnz short loc_14CC\nadd rsp, 88h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14CC:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(char *s, const char *a2)\n{\n char *v2; // rbp\n size_t v3; // r15\n size_t v4; // r12\n int i; // eax\n __int64 rm_so; // rbx\n size_t v7; // rax\n size_t v8; // rcx\n size_t v9; // r14\n size_t v10; // rsi\n char *v11; // rsi\n const char *v12; // rdi\n regmatch_t v14; // [rsp+18h] [rbp-A0h] BYREF\n regex_t preg; // [rsp+20h] [rbp-98h] BYREF\n char pattern[10]; // [rsp+6Eh] [rbp-4Ah] BYREF\n unsigned __int64 v17; // [rsp+78h] [rbp-40h]\n\n v17 = __readfsqword(0x28u);\n __sprintf_chk(pattern, 2LL, 10LL, \"%s{2,}\", a2);\n v2 = 0LL;\n if ( !regcomp(&preg, pattern, 1) )\n {\n v3 = 0LL;\n v4 = strlen(s) + 1;\n v2 = strdup(s);\n for ( i = regexec(&preg, v2, 1uLL, &v14, 0); !i; i = regexec(&preg, v12, 1uLL, &v14, 0) )\n {\n rm_so = v14.rm_so;\n v7 = strlen(v2);\n v8 = v4;\n v9 = rm_so + v3;\n v10 = v14.rm_eo + v3;\n v3 += rm_so + 1;\n v11 = &v2[v10];\n if ( v3 >= v4 )\n v8 = v3;\n v12 = (const char *)__memmove_chk(&v2[v3], v11, v7 + rm_so + 1 - v14.rm_eo - v9, v8 - v3);\n }\n regfree(&preg);\n }\n return v2;\n}", + "ida_strip_asm": "sub_13A0:\nendbr64\npush r15\nmov r8, rsi\nmov edx, 0Ah\nlea rcx, aS2; \"%s{2,}\"\npush r14\nmov esi, 2\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 88h\nmov rax, fs:28h\nmov [rsp+0B8h+var_40], rax\nxor eax, eax\nlea rbp, [rsp+0B8h+pattern]\nlea r13, [rsp+0B8h+preg]\nmov rdi, rbp\ncall ___sprintf_chk\nmov rsi, rbp; pattern\nmov edx, 1; cflags\nmov rdi, r13; preg\ncall _regcomp\nxor ebp, ebp\ntest eax, eax\njnz loc_14A7\nmov rdi, rbx; s\nxor r15d, r15d\ncall _strlen\nmov rdi, rbx; s\nlea r12, [rax+1]\ncall _strdup\nmov rbp, rax\nmov rdi, rax\nlea rax, [rsp+0B8h+var_A0]\nmov [rsp+0B8h+pmatch], rax\njmp short loc_1483\nloc_1438:\nmov rdi, rbp; s\nmovsxd rbx, [rsp+0B8h+var_A0]\ncall _strlen\nmov rcx, r12\nmov rdi, rax\nmovsxd rax, [rsp+0B8h+var_9C]\nlea r14, [rbx+r15]\nlea rdx, [rbx+1]\nlea rsi, [rax+r15]\nlea r15, [r14+1]\nadd rsi, rbp\ncmp r15, r12\ncmovnb rcx, r15\nsub rdx, rax\nsub rdx, r14\nadd rdx, rdi\nsub rcx, r15\nlea rdi, [rbp+r15+0]\ncall ___memmove_chk\nmov rdi, rax\nloc_1483:\nmov rcx, [rsp+0B8h+pmatch]; pmatch\nxor r8d, r8d; eflags\nmov rsi, rdi; string\nmov edx, 1; nmatch\nmov rdi, r13; preg\ncall _regexec\ntest eax, eax\njz short loc_1438\nmov rdi, r13; preg\ncall _regfree\nloc_14A7:\nmov rax, [rsp+0B8h+var_40]\nsub rax, fs:28h\njnz short loc_14CC\nadd rsp, 88h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14CC:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_13A0(char *s, const char *a2)\n{\n char *v2; // rbp\n size_t v3; // r15\n size_t v4; // r12\n int i; // eax\n __int64 rm_so; // rbx\n size_t v7; // rax\n size_t v8; // rcx\n size_t v9; // r14\n size_t v10; // rsi\n char *v11; // rsi\n const char *v12; // rdi\n regmatch_t v14; // [rsp+18h] [rbp-A0h] BYREF\n regex_t preg; // [rsp+20h] [rbp-98h] BYREF\n char pattern[10]; // [rsp+6Eh] [rbp-4Ah] BYREF\n unsigned __int64 v17; // [rsp+78h] [rbp-40h]\n\n v17 = __readfsqword(0x28u);\n __sprintf_chk(pattern, 2LL, 10LL, \"%s{2,}\", a2);\n v2 = 0LL;\n if ( !regcomp(&preg, pattern, 1) )\n {\n v3 = 0LL;\n v4 = strlen(s) + 1;\n v2 = strdup(s);\n for ( i = regexec(&preg, v2, 1uLL, &v14, 0); !i; i = regexec(&preg, v12, 1uLL, &v14, 0) )\n {\n rm_so = v14.rm_so;\n v7 = strlen(v2);\n v8 = v4;\n v9 = rm_so + v3;\n v10 = v14.rm_eo + v3;\n v3 += rm_so + 1;\n v11 = &v2[v10];\n if ( v3 >= v4 )\n v8 = v3;\n v12 = (const char *)__memmove_chk(&v2[v3], v11, v7 + rm_so + 1 - v14.rm_eo - v9, v8 - v3);\n }\n regfree(&preg);\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_13A0(char *s, const char *a2) {\n char *v2;\n unsigned int v3;\n unsigned int v4;\n int i;\n long long rm_so;\n unsigned int v7;\n unsigned int v8;\n unsigned int v9;\n unsigned int v10;\n char *v11;\n const char *v12;\n regmatch_t v14;\n regex_t preg;\n char pattern[10];\n unsigned long long v17;\n v17 = __readfsqword(40u);\n __sprintf_chk(pattern, 2LL, 10LL, \"%s{2,}\", a2);\n v2 = 0LL;\n if (!regcomp(&preg, pattern, 1)) {\n v3 = 0LL;\n v4 = strlen(s) + 1;\n v2 = strdup(s);\n for (i = regexec(&preg, v2, 1uLL, &v14, 0); !i;\n i = regexec(&preg, v12, 1uLL, &v14, 0)) {\n rm_so = v14.rm_so;\n v7 = strlen(v2);\n v8 = v4;\n v9 = rm_so + v3;\n v10 = v14.rm_eo + v3;\n v3 += rm_so + 1;\n v11 = &v2[v10];\n if (v3 >= v4) v8 = v3;\n v12 = (const char *)__memmove_chk(\n &v2[v3], v11, v7 + rm_so + 1 - v14.rm_eo - v9, v8 - v3);\n }\n regfree(&preg);\n }\n return v2;\n}", + "ida_pseudo_norm": "char *func0(char *s, const char *a2) {\n char *v2;\n unsigned int v3;\n unsigned int v4;\n int i;\n long long rm_so;\n unsigned int v7;\n unsigned int v8;\n unsigned int v9;\n unsigned int v10;\n char *v11;\n const char *v12;\n regmatch_t v14;\n regex_t preg;\n char pattern[10];\n unsigned long long v17;\n v17 = __readfsqword(40u);\n __sprintf_chk(pattern, 2LL, 10LL, \"%s{2,}\", a2);\n v2 = 0LL;\n if (!regcomp(&preg, pattern, 1)) {\n v3 = 0LL;\n v4 = strlen(s) + 1;\n v2 = strdup(s);\n for (i = regexec(&preg, v2, 1uLL, &v14, 0); !i;\n i = regexec(&preg, v12, 1uLL, &v14, 0)) {\n rm_so = v14.rm_so;\n v7 = strlen(v2);\n v8 = v4;\n v9 = rm_so + v3;\n v10 = v14.rm_eo + v3;\n v3 += rm_so + 1;\n v11 = &v2[v10];\n if (v3 >= v4) v8 = v3;\n v12 = (const char *)__memmove_chk(\n &v2[v3], v11, v7 + rm_so + 1 - v14.rm_eo - v9, v8 - v3);\n }\n regfree(&preg);\n }\n return v2;\n}" + }, + { + "index": 669, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *Ip) {\n regex_t regex;\n int reti;\n char msgbuf[100];\n const char *pattern =\n \"^(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)\\\\.\"\n \"(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)\\\\.\"\n \"(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)\\\\.\"\n \"(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)$\";\n reti = regcomp(®ex, pattern, REG_EXTENDED);\n if (reti) {\n fprintf(stderr, \"Could not compile regex\\n\");\n return -1;\n }\n reti = regexec(®ex, Ip, 0, NULL, 0);\n if (!reti) {\n return 1;\n }\n else if (reti == REG_NOMATCH) {\n return 0;\n }\n else {\n regerror(reti, ®ex, msgbuf, sizeof(msgbuf));\n fprintf(stderr, \"Regex match failed: %s\\n\", msgbuf);\n return -1;\n }\n regfree(®ex);\n}", + "test": "int main() {\n\n assert(func0(\"192.168.0.1\") == 1); // Valid IP address\n\n assert(func0(\"110.234.52.124\") == 1); // Valid IP address\n\n assert(func0(\"366.1.2.2\") == 0); // Invalid IP address\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0xd0,%rsp\nmov %rdi,-0xc8(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0xdd3(%rip),%rax\nmov %rax,-0xb8(%rbp)\nmov -0xb8(%rbp),%rcx\nlea -0xb0(%rbp),%rax\nmov $0x1,%edx\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 10d0 \nmov %eax,-0xbc(%rbp)\ncmpl $0x0,-0xbc(%rbp)\nje 1293 \nmov 0x2db0(%rip),%rax\nmov %rax,%rcx\nmov $0x18,%edx\nmov $0x1,%esi\nlea 0xe29(%rip),%rdi\ncallq 1110 \nmov $0xffffffff,%eax\njmpq 1320 \nmov -0xc8(%rbp),%rsi\nlea -0xb0(%rbp),%rax\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rax,%rdi\ncallq 1100 \nmov %eax,-0xbc(%rbp)\ncmpl $0x0,-0xbc(%rbp)\njne 12cf \nmov $0x1,%eax\njmp 1320 \ncmpl $0x1,-0xbc(%rbp)\njne 12df \nmov $0x0,%eax\njmp 1320 \nlea -0x70(%rbp),%rdx\nlea -0xb0(%rbp),%rsi\nmov -0xbc(%rbp),%eax\nmov $0x64,%ecx\nmov %eax,%edi\ncallq 10f0 \nmov 0x2d1d(%rip),%rax\nlea -0x70(%rbp),%rdx\nlea 0xdb8(%rip),%rsi\nmov %rax,%rdi\nmov $0x0,%eax\ncallq 10e0 \nmov $0xffffffff,%eax\nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 1334 \ncallq 10b0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0D0h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, a25052040901090; \"^(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?\"...\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+errcode], eax\ncmp [rbp+errcode], 0\njz short loc_1296\nmov rax, cs:__bss_start\nmov rcx, rax; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rax, aCouldNotCompil; \"Could not compile regex\\n\"\nmov rdi, rax; ptr\ncall _fwrite\nmov eax, 0FFFFFFFFh\njmp loc_1326\nloc_1296:\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+errcode], eax\ncmp [rbp+errcode], 0\njnz short loc_12D2\nmov eax, 1\njmp short loc_1326\nloc_12D2:\ncmp [rbp+errcode], 1\njnz short loc_12E2\nmov eax, 0\njmp short loc_1326\nloc_12E2:\nlea rdx, [rbp+errbuf]; errbuf\nlea rsi, [rbp+preg]; preg\nmov eax, [rbp+errcode]\nmov ecx, 64h ; 'd'; errbuf_size\nmov edi, eax; errcode\ncall _regerror\nmov rax, cs:__bss_start\nlea rdx, [rbp+errbuf]\nlea rcx, format; \"Regex match failed: %s\\n\"\nmov rsi, rcx; format\nmov rdi, rax; stream\nmov eax, 0\ncall _fprintf\nmov eax, 0FFFFFFFFh\nloc_1326:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_133A\ncall ___stack_chk_fail\nlocret_133A:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int errcode; // [rsp+14h] [rbp-BCh]\n regex_t preg; // [rsp+20h] [rbp-B0h] BYREF\n char errbuf[104]; // [rsp+60h] [rbp-70h] BYREF\n unsigned __int64 v5; // [rsp+C8h] [rbp-8h]\n\n v5 = __readfsqword(0x28u);\n if ( regcomp(\n &preg,\n \"^(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|[0-1]\"\n \"?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)$\",\n 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n return 0xFFFFFFFFLL;\n }\n else\n {\n errcode = regexec(&preg, a1, 0LL, 0LL, 0);\n if ( errcode )\n {\n if ( errcode == 1 )\n {\n return 0LL;\n }\n else\n {\n regerror(errcode, &preg, errbuf, 0x64uLL);\n fprintf(_bss_start, \"Regex match failed: %s\\n\", errbuf);\n return 0xFFFFFFFFLL;\n }\n }\n else\n {\n return 1LL;\n }\n }\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0D0h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, a25052040901090; \"^(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?\"...\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+errcode], eax\ncmp [rbp+errcode], 0\njz short loc_1296\nmov rax, cs:stderr\nmov rcx, rax; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rax, aCouldNotCompil; \"Could not compile regex\\n\"\nmov rdi, rax; ptr\ncall _fwrite\nmov eax, 0FFFFFFFFh\njmp loc_1326\nloc_1296:\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+errcode], eax\ncmp [rbp+errcode], 0\njnz short loc_12D2\nmov eax, 1\njmp short loc_1326\nloc_12D2:\ncmp [rbp+errcode], 1\njnz short loc_12E2\nmov eax, 0\njmp short loc_1326\nloc_12E2:\nlea rdx, [rbp+errbuf]; errbuf\nlea rsi, [rbp+preg]; preg\nmov eax, [rbp+errcode]\nmov ecx, 64h ; 'd'; errbuf_size\nmov edi, eax; errcode\ncall _regerror\nmov rax, cs:stderr\nlea rdx, [rbp+errbuf]\nlea rcx, format; \"Regex match failed: %s\\n\"\nmov rsi, rcx; format\nmov rdi, rax; stream\nmov eax, 0\ncall _fprintf\nmov eax, 0FFFFFFFFh\nloc_1326:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_133A\ncall ___stack_chk_fail\nlocret_133A:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1209(const char *a1)\n{\n int errcode; // [rsp+14h] [rbp-BCh]\n regex_t preg; // [rsp+20h] [rbp-B0h] BYREF\n char errbuf[104]; // [rsp+60h] [rbp-70h] BYREF\n unsigned __int64 v5; // [rsp+C8h] [rbp-8h]\n\n v5 = __readfsqword(0x28u);\n if ( regcomp(\n &preg,\n \"^(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|[0-1]\"\n \"?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)$\",\n 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n return 0xFFFFFFFFLL;\n }\n else\n {\n errcode = regexec(&preg, a1, 0LL, 0LL, 0);\n if ( errcode )\n {\n if ( errcode == 1 )\n {\n return 0LL;\n }\n else\n {\n regerror(errcode, &preg, errbuf, 0x64uLL);\n fprintf(stderr, \"Regex match failed: %s\\n\", errbuf);\n return 0xFFFFFFFFLL;\n }\n }\n else\n {\n return 1LL;\n }\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1209(const char *a1) {\n int errcode;\n regex_t preg;\n char errbuf[104];\n unsigned long long v5;\n v5 = __readfsqword(40u);\n if (regcomp(&preg,\n \"^(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|\"\n \"[0-1]?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|[0-1]\"\n \"?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)$\",\n 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n return 4294967295LL;\n } else {\n errcode = regexec(&preg, a1, 0LL, 0LL, 0);\n if (errcode) {\n if (errcode == 1) {\n return 0LL;\n } else {\n regerror(errcode, &preg, errbuf, 100uLL);\n fprintf(stderr, \"Regex match failed: %s\\n\", errbuf);\n return 4294967295LL;\n }\n } else {\n return 1LL;\n }\n }\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int errcode;\n regex_t preg;\n char errbuf[104];\n unsigned long long v5;\n v5 = __readfsqword(40u);\n if (regcomp(&preg,\n \"^(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|\"\n \"[0-1]?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|[0-1]\"\n \"?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)$\",\n 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n return 4294967295LL;\n } else {\n errcode = regexec(&preg, a1, 0LL, 0LL, 0);\n if (errcode) {\n if (errcode == 1) {\n return 0LL;\n } else {\n regerror(errcode, &preg, errbuf, 100uLL);\n fprintf(_bss_start, \"Regex match failed: %s\\n\", errbuf);\n return 4294967295LL;\n }\n } else {\n return 1LL;\n }\n }\n}" + }, + { + "index": 669, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *Ip) {\n regex_t regex;\n int reti;\n char msgbuf[100];\n const char *pattern =\n \"^(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)\\\\.\"\n \"(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)\\\\.\"\n \"(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)\\\\.\"\n \"(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)$\";\n reti = regcomp(®ex, pattern, REG_EXTENDED);\n if (reti) {\n fprintf(stderr, \"Could not compile regex\\n\");\n return -1;\n }\n reti = regexec(®ex, Ip, 0, NULL, 0);\n if (!reti) {\n return 1;\n }\n else if (reti == REG_NOMATCH) {\n return 0;\n }\n else {\n regerror(reti, ®ex, msgbuf, sizeof(msgbuf));\n fprintf(stderr, \"Regex match failed: %s\\n\", msgbuf);\n return -1;\n }\n regfree(®ex);\n}", + "test": "int main() {\n\n assert(func0(\"192.168.0.1\") == 1); // Valid IP address\n\n assert(func0(\"110.234.52.124\") == 1); // Valid IP address\n\n assert(func0(\"366.1.2.2\") == 0); // Invalid IP address\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0xb8,%rsp\nmov %rdi,%rbp\nmov %fs:0x28,%rax\nmov %rax,0xa8(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nmov $0x1,%edx\nlea 0xdcd(%rip),%rsi\ncallq 10d0 \ntest %eax,%eax\njne 12ac \nmov %eax,%ebx\nmov %rsp,%rdi\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rbp,%rsi\ncallq 10f0 \ntest %eax,%eax\nje 12ed \ncmp $0x1,%eax\nje 12ce \nlea 0x40(%rsp),%rbx\nmov %rsp,%rsi\nmov $0x64,%ecx\nmov %rbx,%rdx\nmov %eax,%edi\ncallq 10e0 \nmov %rbx,%rcx\nlea 0xe76(%rip),%rdx\nmov $0x1,%esi\nmov 0x2d85(%rip),%rdi\nmov $0x0,%eax\ncallq 1110 <__fprintf_chk@plt>\nmov $0xffffffff,%ebx\njmp 12ce \nmov 0x2d6d(%rip),%rcx\nmov $0x18,%edx\nmov $0x1,%esi\nlea 0xe28(%rip),%rdi\ncallq 1100 \nmov $0xffffffff,%ebx\nmov 0xa8(%rsp),%rax\nxor %fs:0x28,%rax\njne 12f4 \nmov %ebx,%eax\nadd $0xb8,%rsp\npop %rbx\npop %rbp\nretq\nmov $0x1,%ebx\njmp 12ce \ncallq 10b0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 0B8h\nmov rbp, rdi\nmov rax, fs:28h\nmov [rsp+0C8h+var_20], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"^(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?\"...\ncall _regcomp\ntest eax, eax\njnz short loc_12AC\nmov ebx, eax\nmov rdi, rsp; preg\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbp; string\ncall _regexec\ntest eax, eax\njz loc_12ED\ncmp eax, 1\njz short loc_12CE\nlea rbx, [rsp+0C8h+errbuf]\nmov rsi, rsp; preg\nmov ecx, 64h ; 'd'; errbuf_size\nmov rdx, rbx; errbuf\nmov edi, eax; errcode\ncall _regerror\nmov rcx, rbx\nlea rdx, aRegexMatchFail; \"Regex match failed: %s\\n\"\nmov esi, 2\nmov rdi, cs:__bss_start\nmov eax, 0\ncall ___fprintf_chk\nmov ebx, 0FFFFFFFFh\njmp short loc_12CE\nloc_12AC:\nmov rcx, cs:__bss_start; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nmov ebx, 0FFFFFFFFh\nloc_12CE:\nmov rax, [rsp+0C8h+var_20]\nsub rax, fs:28h\njnz short loc_12F4\nmov eax, ebx\nadd rsp, 0B8h\npop rbx\npop rbp\nretn\nloc_12ED:\nmov ebx, 1\njmp short loc_12CE\nloc_12F4:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(char *string)\n{\n unsigned int v1; // ebx\n int v2; // eax\n regex_t v4; // [rsp+0h] [rbp-C8h] BYREF\n char errbuf[104]; // [rsp+40h] [rbp-88h] BYREF\n unsigned __int64 v6; // [rsp+A8h] [rbp-20h]\n\n v6 = __readfsqword(0x28u);\n if ( regcomp(\n &v4,\n \"^(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|[0-1]\"\n \"?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)$\",\n 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n return (unsigned int)-1;\n }\n else\n {\n v1 = 0;\n v2 = regexec(&v4, string, 0LL, 0LL, 0);\n if ( v2 )\n {\n if ( v2 != 1 )\n {\n regerror(v2, &v4, errbuf, 0x64uLL);\n __fprintf_chk(_bss_start, 2LL, \"Regex match failed: %s\\n\", errbuf);\n return (unsigned int)-1;\n }\n }\n else\n {\n return 1;\n }\n }\n return v1;\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush rbp\npush rbx\nsub rsp, 0B8h\nmov rbp, rdi\nmov rax, fs:28h\nmov [rsp+0C8h+var_20], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"^(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?\"...\ncall _regcomp\ntest eax, eax\njnz short loc_12AC\nmov ebx, eax\nmov rdi, rsp; preg\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbp; string\ncall _regexec\ntest eax, eax\njz loc_12ED\ncmp eax, 1\njz short loc_12CE\nlea rbx, [rsp+0C8h+errbuf]\nmov rsi, rsp; preg\nmov ecx, 64h ; 'd'; errbuf_size\nmov rdx, rbx; errbuf\nmov edi, eax; errcode\ncall _regerror\nmov rcx, rbx\nlea rdx, aRegexMatchFail; \"Regex match failed: %s\\n\"\nmov esi, 2\nmov rdi, cs:stderr\nmov eax, 0\ncall ___fprintf_chk\nmov ebx, 0FFFFFFFFh\njmp short loc_12CE\nloc_12AC:\nmov rcx, cs:stderr; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nmov ebx, 0FFFFFFFFh\nloc_12CE:\nmov rax, [rsp+0C8h+var_20]\nsub rax, fs:28h\njnz short loc_12F4\nmov eax, ebx\nadd rsp, 0B8h\npop rbx\npop rbp\nretn\nloc_12ED:\nmov ebx, 1\njmp short loc_12CE\nloc_12F4:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1209(char *string)\n{\n unsigned int v1; // ebx\n int v2; // eax\n regex_t v4; // [rsp+0h] [rbp-C8h] BYREF\n char errbuf[104]; // [rsp+40h] [rbp-88h] BYREF\n unsigned __int64 v6; // [rsp+A8h] [rbp-20h]\n\n v6 = __readfsqword(0x28u);\n if ( regcomp(\n &v4,\n \"^(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|[0-1]\"\n \"?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)$\",\n 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n return (unsigned int)-1;\n }\n else\n {\n v1 = 0;\n v2 = regexec(&v4, string, 0LL, 0LL, 0);\n if ( v2 )\n {\n if ( v2 != 1 )\n {\n regerror(v2, &v4, errbuf, 0x64uLL);\n __fprintf_chk(stderr, 2LL, \"Regex match failed: %s\\n\", errbuf);\n return (unsigned int)-1;\n }\n }\n else\n {\n return 1;\n }\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1209(char *string) {\n unsigned int v1;\n int v2;\n regex_t v4;\n char errbuf[104];\n unsigned long long v6;\n v6 = __readfsqword(40u);\n if (regcomp(&v4,\n \"^(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|\"\n \"[0-1]?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|[0-1]\"\n \"?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)$\",\n 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n return (unsigned int)-1;\n } else {\n v1 = 0;\n v2 = regexec(&v4, string, 0LL, 0LL, 0);\n if (v2) {\n if (v2 != 1) {\n regerror(v2, &v4, errbuf, 100uLL);\n __fprintf_chk(stderr, 2LL, \"Regex match failed: %s\\n\", errbuf);\n return (unsigned int)-1;\n }\n } else {\n return 1;\n }\n }\n return v1;\n}", + "ida_pseudo_norm": "long long func0(char *string) {\n unsigned int v1;\n int v2;\n regex_t v4;\n char errbuf[104];\n unsigned long long v6;\n v6 = __readfsqword(40u);\n if (regcomp(&v4,\n \"^(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|\"\n \"[0-1]?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|[0-1]\"\n \"?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)$\",\n 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n return (unsigned int)-1;\n } else {\n v1 = 0;\n v2 = regexec(&v4, string, 0LL, 0LL, 0);\n if (v2) {\n if (v2 != 1) {\n regerror(v2, &v4, errbuf, 100uLL);\n __fprintf_chk(_bss_start, 2LL, \"Regex match failed: %s\\n\", errbuf);\n return (unsigned int)-1;\n }\n } else {\n return 1;\n }\n }\n return v1;\n}" + }, + { + "index": 669, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *Ip) {\n regex_t regex;\n int reti;\n char msgbuf[100];\n const char *pattern =\n \"^(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)\\\\.\"\n \"(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)\\\\.\"\n \"(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)\\\\.\"\n \"(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)$\";\n reti = regcomp(®ex, pattern, REG_EXTENDED);\n if (reti) {\n fprintf(stderr, \"Could not compile regex\\n\");\n return -1;\n }\n reti = regexec(®ex, Ip, 0, NULL, 0);\n if (!reti) {\n return 1;\n }\n else if (reti == REG_NOMATCH) {\n return 0;\n }\n else {\n regerror(reti, ®ex, msgbuf, sizeof(msgbuf));\n fprintf(stderr, \"Regex match failed: %s\\n\", msgbuf);\n return -1;\n }\n regfree(®ex);\n}", + "test": "int main() {\n\n assert(func0(\"192.168.0.1\") == 1); // Valid IP address\n\n assert(func0(\"110.234.52.124\") == 1); // Valid IP address\n\n assert(func0(\"366.1.2.2\") == 0); // Invalid IP address\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov $0x1,%edx\nlea 0xd46(%rip),%rsi\npush %r12\npush %rbp\nmov %rdi,%rbp\nsub $0xb0,%rsp\nmov %fs:0x28,%rax\nmov %rax,0xa8(%rsp)\nxor %eax,%eax\nmov %rsp,%r13\nmov %r13,%rdi\ncallq 10d0 \ntest %eax,%eax\njne 1380 \nxor %r8d,%r8d\nxor %ecx,%ecx\nxor %edx,%edx\nmov %rbp,%rsi\nmov %r13,%rdi\nmov %eax,%r12d\ncallq 10f0 \ntest %eax,%eax\nje 1370 \ncmp $0x1,%eax\nje 134d \nlea 0x40(%rsp),%r12\nmov $0x64,%ecx\nmov %r13,%rsi\nmov %eax,%edi\nmov %r12,%rdx\ncallq 10e0 \nmov %r12,%rcx\nmov $0x1,%esi\nxor %eax,%eax\nmov 0x2ce5(%rip),%rdi\nlea 0xdc3(%rip),%rdx\nmov $0xffffffff,%r12d\ncallq 1110 <__fprintf_chk@plt>\nmov 0xa8(%rsp),%rax\nxor %fs:0x28,%rax\njne 13a5 \nadd $0xb0,%rsp\nmov %r12d,%eax\npop %rbp\npop %r12\npop %r13\nretq\nmov $0x1,%r12d\njmp 134d \nnopl 0x0(%rax,%rax,1)\nmov $0x18,%edx\nmov 0x2c94(%rip),%rcx\nmov $0x1,%esi\nlea 0xd54(%rip),%rdi\nmov $0xffffffff,%r12d\ncallq 1100 \njmp 134d \ncallq 10b0 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r12\nmov edx, 1; cflags\nlea rsi, pattern; \"^(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?\"...\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 0B0h\nmov rax, fs:28h\nmov [rsp+0C8h+var_20], rax\nxor eax, eax\nmov r12, rsp\nmov rdi, r12; preg\ncall _regcomp\ntest eax, eax\njnz loc_1380\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbp; string\nmov rdi, r12; preg\nmov ebx, eax\ncall _regexec\ntest eax, eax\njz short loc_1370\ncmp eax, 1\njz short loc_134A\nlea rbx, [rsp+0C8h+errbuf]\nmov ecx, 64h ; 'd'; errbuf_size\nmov rsi, r12; preg\nmov edi, eax; errcode\nmov rdx, rbx; errbuf\ncall _regerror\nmov rcx, rbx\nmov esi, 2\nxor eax, eax\nmov rdi, cs:__bss_start\nlea rdx, aRegexMatchFail; \"Regex match failed: %s\\n\"\ncall ___fprintf_chk\nloc_1345:\nmov ebx, 0FFFFFFFFh\nloc_134A:\nmov rax, [rsp+0C8h+var_20]\nsub rax, fs:28h\njnz short loc_139F\nadd rsp, 0B0h\nmov eax, ebx\npop rbx\npop rbp\npop r12\nretn\nloc_1370:\nmov ebx, 1\njmp short loc_134A\nloc_1380:\nmov rcx, cs:__bss_start; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\njmp short loc_1345\nloc_139F:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(char *string)\n{\n unsigned int v1; // ebx\n int v2; // eax\n regex_t v4; // [rsp+0h] [rbp-C8h] BYREF\n char errbuf[104]; // [rsp+40h] [rbp-88h] BYREF\n unsigned __int64 v6; // [rsp+A8h] [rbp-20h]\n\n v6 = __readfsqword(0x28u);\n if ( regcomp(\n &v4,\n \"^(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|[0-1]\"\n \"?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)$\",\n 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n return (unsigned int)-1;\n }\n v1 = 0;\n v2 = regexec(&v4, string, 0LL, 0LL, 0);\n if ( !v2 )\n return 1;\n if ( v2 != 1 )\n {\n regerror(v2, &v4, errbuf, 0x64uLL);\n __fprintf_chk(_bss_start, 2LL, \"Regex match failed: %s\\n\", errbuf);\n return (unsigned int)-1;\n }\n return v1;\n}", + "ida_strip_asm": "sub_12B0:\nendbr64\npush r12\nmov edx, 1; cflags\nlea rsi, pattern; \"^(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?\"...\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 0B0h\nmov rax, fs:28h\nmov [rsp+0C8h+var_20], rax\nxor eax, eax\nmov r12, rsp\nmov rdi, r12; preg\ncall _regcomp\ntest eax, eax\njnz loc_1380\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbp; string\nmov rdi, r12; preg\nmov ebx, eax\ncall _regexec\ntest eax, eax\njz short loc_1370\ncmp eax, 1\njz short loc_134A\nlea rbx, [rsp+0C8h+errbuf]\nmov ecx, 64h ; 'd'; errbuf_size\nmov rsi, r12; preg\nmov edi, eax; errcode\nmov rdx, rbx; errbuf\ncall _regerror\nmov rcx, rbx\nmov esi, 2\nxor eax, eax\nmov rdi, cs:stderr\nlea rdx, aRegexMatchFail; \"Regex match failed: %s\\n\"\ncall ___fprintf_chk\nloc_1345:\nmov ebx, 0FFFFFFFFh\nloc_134A:\nmov rax, [rsp+0C8h+var_20]\nsub rax, fs:28h\njnz short loc_139F\nadd rsp, 0B0h\nmov eax, ebx\npop rbx\npop rbp\npop r12\nretn\nloc_1370:\nmov ebx, 1\njmp short loc_134A\nloc_1380:\nmov rcx, cs:stderr; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\njmp short loc_1345\nloc_139F:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12B0(char *string)\n{\n unsigned int v1; // ebx\n int v2; // eax\n regex_t v4; // [rsp+0h] [rbp-C8h] BYREF\n char errbuf[104]; // [rsp+40h] [rbp-88h] BYREF\n unsigned __int64 v6; // [rsp+A8h] [rbp-20h]\n\n v6 = __readfsqword(0x28u);\n if ( regcomp(\n &v4,\n \"^(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|[0-1]\"\n \"?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)$\",\n 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n return (unsigned int)-1;\n }\n v1 = 0;\n v2 = regexec(&v4, string, 0LL, 0LL, 0);\n if ( !v2 )\n return 1;\n if ( v2 != 1 )\n {\n regerror(v2, &v4, errbuf, 0x64uLL);\n __fprintf_chk(stderr, 2LL, \"Regex match failed: %s\\n\", errbuf);\n return (unsigned int)-1;\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12B0(char *string) {\n unsigned int v1;\n int v2;\n regex_t v4;\n char errbuf[104];\n unsigned long long v6;\n v6 = __readfsqword(40u);\n if (regcomp(&v4,\n \"^(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|\"\n \"[0-1]?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|[0-1]\"\n \"?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)$\",\n 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n return (unsigned int)-1;\n }\n v1 = 0;\n v2 = regexec(&v4, string, 0LL, 0LL, 0);\n if (!v2) return 1;\n if (v2 != 1) {\n regerror(v2, &v4, errbuf, 100uLL);\n __fprintf_chk(stderr, 2LL, \"Regex match failed: %s\\n\", errbuf);\n return (unsigned int)-1;\n }\n return v1;\n}", + "ida_pseudo_norm": "long long func0(char *string) {\n unsigned int v1;\n int v2;\n regex_t v4;\n char errbuf[104];\n unsigned long long v6;\n v6 = __readfsqword(40u);\n if (regcomp(&v4,\n \"^(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|\"\n \"[0-1]?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|[0-1]\"\n \"?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)$\",\n 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n return (unsigned int)-1;\n }\n v1 = 0;\n v2 = regexec(&v4, string, 0LL, 0LL, 0);\n if (!v2) return 1;\n if (v2 != 1) {\n regerror(v2, &v4, errbuf, 100uLL);\n __fprintf_chk(_bss_start, 2LL, \"Regex match failed: %s\\n\", errbuf);\n return (unsigned int)-1;\n }\n return v1;\n}" + }, + { + "index": 669, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *Ip) {\n regex_t regex;\n int reti;\n char msgbuf[100];\n const char *pattern =\n \"^(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)\\\\.\"\n \"(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)\\\\.\"\n \"(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)\\\\.\"\n \"(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)$\";\n reti = regcomp(®ex, pattern, REG_EXTENDED);\n if (reti) {\n fprintf(stderr, \"Could not compile regex\\n\");\n return -1;\n }\n reti = regexec(®ex, Ip, 0, NULL, 0);\n if (!reti) {\n return 1;\n }\n else if (reti == REG_NOMATCH) {\n return 0;\n }\n else {\n regerror(reti, ®ex, msgbuf, sizeof(msgbuf));\n fprintf(stderr, \"Regex match failed: %s\\n\", msgbuf);\n return -1;\n }\n regfree(®ex);\n}", + "test": "int main() {\n\n assert(func0(\"192.168.0.1\") == 1); // Valid IP address\n\n assert(func0(\"110.234.52.124\") == 1); // Valid IP address\n\n assert(func0(\"366.1.2.2\") == 0); // Invalid IP address\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov $0x1,%edx\nlea 0xd46(%rip),%rsi\npush %r12\npush %rbp\nmov %rdi,%rbp\nsub $0xb0,%rsp\nmov %fs:0x28,%rax\nmov %rax,0xa8(%rsp)\nxor %eax,%eax\nmov %rsp,%r13\nmov %r13,%rdi\ncallq 10d0 \ntest %eax,%eax\njne 1380 \nxor %r8d,%r8d\nxor %ecx,%ecx\nxor %edx,%edx\nmov %rbp,%rsi\nmov %r13,%rdi\nmov %eax,%r12d\ncallq 10f0 \ntest %eax,%eax\nje 1370 \ncmp $0x1,%eax\nje 134d \nlea 0x40(%rsp),%r12\nmov $0x64,%ecx\nmov %r13,%rsi\nmov %eax,%edi\nmov %r12,%rdx\ncallq 10e0 \nmov %r12,%rcx\nmov $0x1,%esi\nxor %eax,%eax\nmov 0x2ce5(%rip),%rdi\nlea 0xdc3(%rip),%rdx\nmov $0xffffffff,%r12d\ncallq 1110 <__fprintf_chk@plt>\nmov 0xa8(%rsp),%rax\nxor %fs:0x28,%rax\njne 13a5 \nadd $0xb0,%rsp\nmov %r12d,%eax\npop %rbp\npop %r12\npop %r13\nretq\nmov $0x1,%r12d\njmp 134d \nnopl 0x0(%rax,%rax,1)\nmov $0x18,%edx\nmov 0x2c94(%rip),%rcx\nmov $0x1,%esi\nlea 0xd54(%rip),%rdi\nmov $0xffffffff,%r12d\ncallq 1100 \njmp 134d \ncallq 10b0 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r12\nmov edx, 1; cflags\nlea rsi, pattern; \"^(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?\"...\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 0B0h\nmov rax, fs:28h\nmov [rsp+0C8h+var_20], rax\nxor eax, eax\nmov r12, rsp\nmov rdi, r12; preg\ncall _regcomp\ntest eax, eax\njnz loc_1380\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbp; string\nmov rdi, r12; preg\nmov ebx, eax\ncall _regexec\ntest eax, eax\njz short loc_1370\ncmp eax, 1\njz short loc_134A\nlea rbx, [rsp+0C8h+errbuf]\nmov ecx, 64h ; 'd'; errbuf_size\nmov rsi, r12; preg\nmov edi, eax; errcode\nmov rdx, rbx; errbuf\ncall _regerror\nmov rcx, rbx\nmov esi, 2\nxor eax, eax\nmov rdi, cs:__bss_start\nlea rdx, aRegexMatchFail; \"Regex match failed: %s\\n\"\ncall ___fprintf_chk\nloc_1345:\nmov ebx, 0FFFFFFFFh\nloc_134A:\nmov rax, [rsp+0C8h+var_20]\nsub rax, fs:28h\njnz short loc_139F\nadd rsp, 0B0h\nmov eax, ebx\npop rbx\npop rbp\npop r12\nretn\nloc_1370:\nmov ebx, 1\njmp short loc_134A\nloc_1380:\nmov rcx, cs:__bss_start; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\njmp short loc_1345\nloc_139F:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(char *string)\n{\n unsigned int v1; // ebx\n int v2; // eax\n regex_t v4; // [rsp+0h] [rbp-C8h] BYREF\n char errbuf[104]; // [rsp+40h] [rbp-88h] BYREF\n unsigned __int64 v6; // [rsp+A8h] [rbp-20h]\n\n v6 = __readfsqword(0x28u);\n if ( regcomp(\n &v4,\n \"^(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|[0-1]\"\n \"?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)$\",\n 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n return (unsigned int)-1;\n }\n v1 = 0;\n v2 = regexec(&v4, string, 0LL, 0LL, 0);\n if ( !v2 )\n return 1;\n if ( v2 != 1 )\n {\n regerror(v2, &v4, errbuf, 0x64uLL);\n __fprintf_chk(_bss_start, 2LL, \"Regex match failed: %s\\n\", errbuf);\n return (unsigned int)-1;\n }\n return v1;\n}", + "ida_strip_asm": "sub_12B0:\nendbr64\npush r12\nmov edx, 1; cflags\nlea rsi, pattern; \"^(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?\"...\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 0B0h\nmov rax, fs:28h\nmov [rsp+0C8h+var_20], rax\nxor eax, eax\nmov r12, rsp\nmov rdi, r12; preg\ncall _regcomp\ntest eax, eax\njnz loc_1380\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbp; string\nmov rdi, r12; preg\nmov ebx, eax\ncall _regexec\ntest eax, eax\njz short loc_1370\ncmp eax, 1\njz short loc_134A\nlea rbx, [rsp+0C8h+errbuf]\nmov ecx, 64h ; 'd'; errbuf_size\nmov rsi, r12; preg\nmov edi, eax; errcode\nmov rdx, rbx; errbuf\ncall _regerror\nmov rcx, rbx\nmov esi, 2\nxor eax, eax\nmov rdi, cs:stderr\nlea rdx, aRegexMatchFail; \"Regex match failed: %s\\n\"\ncall ___fprintf_chk\nloc_1345:\nmov ebx, 0FFFFFFFFh\nloc_134A:\nmov rax, [rsp+0C8h+var_20]\nsub rax, fs:28h\njnz short loc_139F\nadd rsp, 0B0h\nmov eax, ebx\npop rbx\npop rbp\npop r12\nretn\nloc_1370:\nmov ebx, 1\njmp short loc_134A\nloc_1380:\nmov rcx, cs:stderr; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\njmp short loc_1345\nloc_139F:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12B0(char *string)\n{\n unsigned int v1; // ebx\n int v2; // eax\n regex_t v4; // [rsp+0h] [rbp-C8h] BYREF\n char errbuf[104]; // [rsp+40h] [rbp-88h] BYREF\n unsigned __int64 v6; // [rsp+A8h] [rbp-20h]\n\n v6 = __readfsqword(0x28u);\n if ( regcomp(\n &v4,\n \"^(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|[0-1]\"\n \"?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)$\",\n 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n return (unsigned int)-1;\n }\n v1 = 0;\n v2 = regexec(&v4, string, 0LL, 0LL, 0);\n if ( !v2 )\n return 1;\n if ( v2 != 1 )\n {\n regerror(v2, &v4, errbuf, 0x64uLL);\n __fprintf_chk(stderr, 2LL, \"Regex match failed: %s\\n\", errbuf);\n return (unsigned int)-1;\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12B0(char *string) {\n unsigned int v1;\n int v2;\n regex_t v4;\n char errbuf[104];\n unsigned long long v6;\n v6 = __readfsqword(40u);\n if (regcomp(&v4,\n \"^(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|\"\n \"[0-1]?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|[0-1]\"\n \"?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)$\",\n 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n return (unsigned int)-1;\n }\n v1 = 0;\n v2 = regexec(&v4, string, 0LL, 0LL, 0);\n if (!v2) return 1;\n if (v2 != 1) {\n regerror(v2, &v4, errbuf, 100uLL);\n __fprintf_chk(stderr, 2LL, \"Regex match failed: %s\\n\", errbuf);\n return (unsigned int)-1;\n }\n return v1;\n}", + "ida_pseudo_norm": "long long func0(char *string) {\n unsigned int v1;\n int v2;\n regex_t v4;\n char errbuf[104];\n unsigned long long v6;\n v6 = __readfsqword(40u);\n if (regcomp(&v4,\n \"^(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|\"\n \"[0-1]?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|[0-1]\"\n \"?[0-9][0-9]?)\\\\.(25[0-5]|2[0-4][0-9]|[0-1]?[0-9][0-9]?)$\",\n 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n return (unsigned int)-1;\n }\n v1 = 0;\n v2 = regexec(&v4, string, 0LL, 0LL, 0);\n if (!v2) return 1;\n if (v2 != 1) {\n regerror(v2, &v4, errbuf, 100uLL);\n __fprintf_chk(_bss_start, 2LL, \"Regex match failed: %s\\n\", errbuf);\n return (unsigned int)-1;\n }\n return v1;\n}" + }, + { + "index": 670, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int nums[], int size) {\n for (int i = 0; i < size - 1; i++) {\n if (nums[i] >= nums[i + 1]) return false;\n }\n return true;\n}", + "test": "int main() {\n\n int arr1[] = {-4, -3, -2, -1};\n\n int size1 = sizeof(arr1)/sizeof(arr1[0]);\n\n assert(func0(arr1, size1) == true);\n\n\n\n int arr2[] = {1, 2, 3};\n\n int size2 = sizeof(arr2)/sizeof(arr2[0]);\n\n assert(func0(arr2, size2) == true);\n\n\n\n int arr3[] = {3, 2, 1};\n\n int size3 = sizeof(arr3)/sizeof(arr3[0]);\n\n assert(func0(arr3, size3) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11c0 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njl 11bc \nmov $0x0,%eax\njmp 11d0 \naddl $0x1,-0x4(%rbp)\nmov -0x1c(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x4(%rbp)\njl 1181 \nmov $0x1,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 0\njmp short loc_11C0\nloc_1181:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njl short loc_11BC\nmov eax, 0\njmp short loc_11D0\nloc_11BC:\nadd [rbp+var_4], 1\nloc_11C0:\nmov eax, [rbp+var_1C]\nsub eax, 1\ncmp [rbp+var_4], eax\njl short loc_1181\nmov eax, 1\nloc_11D0:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i < a2 - 1; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) >= *(_DWORD *)(4 * (i + 1LL) + a1) )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 0\njmp short loc_11C0\nloc_1181:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njl short loc_11BC\nmov eax, 0\njmp short loc_11D0\nloc_11BC:\nadd [rbp+var_4], 1\nloc_11C0:\nmov eax, [rbp+var_1C]\nsub eax, 1\ncmp [rbp+var_4], eax\njl short loc_1181\nmov eax, 1\nloc_11D0:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i < a2 - 1; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) >= *(_DWORD *)(4 * (i + 1LL) + a1) )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int i;\n for (i = 0; i < a2 - 1; ++i) {\n if (*(uint32_t *)(4LL * i + a1) >= *(uint32_t *)(4 * (i + 1LL) + a1))\n return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int i;\n for (i = 0; i < a2 - 1; ++i) {\n if (*(uint32_t *)(4LL * i + a1) >= *(uint32_t *)(4 * (i + 1LL) + a1))\n return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": 670, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int nums[], int size) {\n for (int i = 0; i < size - 1; i++) {\n if (nums[i] >= nums[i + 1]) return false;\n }\n return true;\n}", + "test": "int main() {\n\n int arr1[] = {-4, -3, -2, -1};\n\n int size1 = sizeof(arr1)/sizeof(arr1[0]);\n\n assert(func0(arr1, size1) == true);\n\n\n\n int arr2[] = {1, 2, 3};\n\n int size2 = sizeof(arr2)/sizeof(arr2[0]);\n\n assert(func0(arr2, size2) == true);\n\n\n\n int arr3[] = {3, 2, 1};\n\n int size3 = sizeof(arr3)/sizeof(arr3[0]);\n\n assert(func0(arr3, size3) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%esi\njle 1193 \nmov %rdi,%rax\nlea -0x2(%rsi),%edx\nlea 0x4(%rdi,%rdx,4),%rdx\nmov 0x4(%rax),%ecx\ncmp %ecx,(%rax)\njge 1199 \nadd $0x4,%rax\ncmp %rdx,%rax\njne 117d \nmov $0x1,%eax\nretq\nmov $0x1,%eax\nretq\nmov $0x0,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ncmp esi, 1\njle short loc_1193\nmov rax, rdi\nlea edx, [rsi-2]\nlea rdx, [rdi+rdx*4+4]\nloc_117D:\nmov ecx, [rax+4]\ncmp [rax], ecx\njge short loc_1199\nadd rax, 4\ncmp rax, rdx\njnz short loc_117D\nmov eax, 1\nretn\nloc_1193:\nmov eax, 1\nretn\nloc_1199:\nmov eax, 0\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n\n if ( a2 <= 1 )\n return 1LL;\n v2 = a1;\n while ( *v2 < v2[1] )\n {\n if ( ++v2 == &a1[a2 - 2 + 1] )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ncmp esi, 1\njle short loc_1193\nmov rax, rdi\nlea edx, [rsi-2]\nlea rdx, [rdi+rdx*4+4]\nloc_117D:\nmov ecx, [rax+4]\ncmp [rax], ecx\njge short loc_1199\nadd rax, 4\ncmp rax, rdx\njnz short loc_117D\nmov eax, 1\nretn\nloc_1193:\nmov eax, 1\nretn\nloc_1199:\nmov eax, 0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n\n if ( a2 <= 1 )\n return 1LL;\n v2 = a1;\n while ( *v2 < v2[1] )\n {\n if ( ++v2 == &a1[a2 - 2 + 1] )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2) {\n uint32_t *v2;\n if (a2 <= 1) return 1LL;\n v2 = a1;\n while (*v2 < v2[1]) {\n if (++v2 == &a1[a2 - 2 + 1]) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n if (a2 <= 1) return 1LL;\n v2 = a1;\n while (*v2 < v2[1]) {\n if (++v2 == &a1[a2 - 2 + 1]) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 670, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int nums[], int size) {\n for (int i = 0; i < size - 1; i++) {\n if (nums[i] >= nums[i + 1]) return false;\n }\n return true;\n}", + "test": "int main() {\n\n int arr1[] = {-4, -3, -2, -1};\n\n int size1 = sizeof(arr1)/sizeof(arr1[0]);\n\n assert(func0(arr1, size1) == true);\n\n\n\n int arr2[] = {1, 2, 3};\n\n int size2 = sizeof(arr2)/sizeof(arr2[0]);\n\n assert(func0(arr2, size2) == true);\n\n\n\n int arr3[] = {3, 2, 1};\n\n int size3 = sizeof(arr3)/sizeof(arr3[0]);\n\n assert(func0(arr3, size3) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%esi\njle 1170 \nlea -0x2(%rsi),%eax\nlea 0x4(%rdi,%rax,4),%rax\njmp 1161 \nnopl 0x0(%rax,%rax,1)\nadd $0x4,%rdi\ncmp %rax,%rdi\nje 1170 \nmov 0x4(%rdi),%edx\ncmp %edx,(%rdi)\njl 1158 \nxor %eax,%eax\nretq\nnopl 0x0(%rax,%rax,1)\nmov $0x1,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ncmp esi, 1\njle short loc_12A8\nlea ecx, [rsi-2]\nmov edx, [rdi]\nlea rax, [rdi+4]\nlea rsi, [rdi+rcx*4+8]\njmp short loc_1299\nloc_1290:\nadd rax, 4\ncmp rax, rsi\njz short loc_12A8\nloc_1299:\nmov ecx, edx\nmov edx, [rax]\ncmp edx, ecx\njg short loc_1290\nxor eax, eax\nretn\nloc_12A8:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int v2; // edx\n int *v3; // rax\n __int64 v4; // rsi\n int v5; // ecx\n\n if ( a2 <= 1 )\n return 1LL;\n v2 = *a1;\n v3 = a1 + 1;\n v4 = (__int64)&a1[a2 - 2 + 2];\n while ( 1 )\n {\n v5 = v2;\n v2 = *v3;\n if ( *v3 <= v5 )\n break;\n if ( ++v3 == (int *)v4 )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1270:\nendbr64\ncmp esi, 1\njle short loc_12A8\nlea ecx, [rsi-2]\nmov edx, [rdi]\nlea rax, [rdi+4]\nlea rsi, [rdi+rcx*4+8]\njmp short loc_1299\nloc_1290:\nadd rax, 4\ncmp rax, rsi\njz short loc_12A8\nloc_1299:\nmov ecx, edx\nmov edx, [rax]\ncmp edx, ecx\njg short loc_1290\nxor eax, eax\nretn\nloc_12A8:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1270(int *a1, int a2)\n{\n int v2; // edx\n int *v3; // rax\n __int64 v4; // rsi\n int v5; // ecx\n\n if ( a2 <= 1 )\n return 1LL;\n v2 = *a1;\n v3 = a1 + 1;\n v4 = (__int64)&a1[a2 - 2 + 2];\n while ( 1 )\n {\n v5 = v2;\n v2 = *v3;\n if ( *v3 <= v5 )\n break;\n if ( ++v3 == (int *)v4 )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1270(int *a1, int a2) {\n int v2;\n int *v3;\n long long v4;\n int v5;\n if (a2 <= 1) return 1LL;\n v2 = *a1;\n v3 = a1 + 1;\n v4 = (long long)&a1[a2 - 2 + 2];\n while (1) {\n v5 = v2;\n v2 = *v3;\n if (*v3 <= v5) break;\n if (++v3 == (int *)v4) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int v2;\n int *v3;\n long long v4;\n int v5;\n if (a2 <= 1) return 1LL;\n v2 = *a1;\n v3 = a1 + 1;\n v4 = (long long)&a1[a2 - 2 + 2];\n while (1) {\n v5 = v2;\n v2 = *v3;\n if (*v3 <= v5) break;\n if (++v3 == (int *)v4) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 671, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n == 0) {\n return 1;\n }\n if ((n & (n + 1)) == 0) {\n return n;\n }\n int pos = (int)(log2((~n) & -(~n)) + 1);\n return ((1 << (pos - 1)) | n);\n}", + "test": "int main() {\n\n assert(func0(21) == 23);\n\n assert(func0(11) == 15);\n\n assert(func0(15) == 15);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %edi,-0x14(%rbp)\ncmpl $0x0,-0x14(%rbp)\njne 1185 \nmov $0x1,%eax\njmp 11d6 \nmov -0x14(%rbp),%eax\nadd $0x1,%eax\nand -0x14(%rbp),%eax\ntest %eax,%eax\njne 1197 \nmov -0x14(%rbp),%eax\njmp 11d6 \nmov -0x14(%rbp),%eax\nnot %eax\nmov %eax,%edx\nmov -0x14(%rbp),%eax\nadd $0x1,%eax\nand %edx,%eax\ncvtsi2sd %eax,%xmm0\ncallq 1060 \nmovsd 0xec9(%rip),%xmm1\naddsd %xmm1,%xmm0\ncvttsd2si %xmm0,%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nsub $0x1,%eax\nmov $0x1,%edx\nmov %eax,%ecx\nshl %cl,%edx\nmov %edx,%eax\nor -0x14(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\ncmp [rbp+var_14], 0\njnz short loc_1185\nmov eax, 1\njmp short locret_11E4\nloc_1185:\nmov eax, [rbp+var_14]\nadd eax, 1\nand eax, [rbp+var_14]\ntest eax, eax\njnz short loc_1197\nmov eax, [rbp+var_14]\njmp short locret_11E4\nloc_1197:\nmov eax, [rbp+var_14]\nnot eax\nmov edx, eax\nmov eax, [rbp+var_14]\nadd eax, 1\nand eax, edx\npxor xmm2, xmm2\ncvtsi2sd xmm2, eax\nmovq rax, xmm2\nmovq xmm0, rax; x\ncall _log2\nmovsd xmm1, cs:qword_2060\naddsd xmm0, xmm1\ncvttsd2si eax, xmm0\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\nsub eax, 1\nmov edx, 1\nmov ecx, eax\nshl edx, cl\nmov eax, edx\nor eax, [rbp+var_14]\nlocret_11E4:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1)\n{\n if ( !a1 )\n return 1LL;\n if ( (a1 & (a1 + 1)) != 0 )\n return a1 | (1 << ((int)(log2((double)(int)(~a1 & (a1 + 1))) + 1.0) - 1));\n return a1;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\ncmp [rbp+var_14], 0\njnz short loc_1185\nmov eax, 1\njmp short locret_11E4\nloc_1185:\nmov eax, [rbp+var_14]\nadd eax, 1\nand eax, [rbp+var_14]\ntest eax, eax\njnz short loc_1197\nmov eax, [rbp+var_14]\njmp short locret_11E4\nloc_1197:\nmov eax, [rbp+var_14]\nnot eax\nmov edx, eax\nmov eax, [rbp+var_14]\nadd eax, 1\nand eax, edx\npxor xmm2, xmm2\ncvtsi2sd xmm2, eax\nmovq rax, xmm2\nmovq xmm0, rax; x\ncall _log2\nmovsd xmm1, cs:qword_2060\naddsd xmm0, xmm1\ncvttsd2si eax, xmm0\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\nsub eax, 1\nmov edx, 1\nmov ecx, eax\nshl edx, cl\nmov eax, edx\nor eax, [rbp+var_14]\nlocret_11E4:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(unsigned int a1)\n{\n if ( !a1 )\n return 1LL;\n if ( (a1 & (a1 + 1)) != 0 )\n return a1 | (1 << ((int)(log2((double)(int)(~a1 & (a1 + 1))) + 1.0) - 1));\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(unsigned int a1) {\n if (!a1) return 1LL;\n if ((a1 & (a1 + 1)) != 0)\n return a1 | (1 << ((int)(log2((double)(int)(~a1 & (a1 + 1))) + 1.0) - 1));\n return a1;\n}", + "ida_pseudo_norm": "long long func0(unsigned int a1) {\n if (!a1) return 1LL;\n if ((a1 & (a1 + 1)) != 0)\n return a1 | (1 << ((int)(log2((double)(int)(~a1 & (a1 + 1))) + 1.0) - 1));\n return a1;\n}" + }, + { + "index": 671, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n == 0) {\n return 1;\n }\n if ((n & (n + 1)) == 0) {\n return n;\n }\n int pos = (int)(log2((~n) & -(~n)) + 1);\n return ((1 << (pos - 1)) | n);\n}", + "test": "int main() {\n\n assert(func0(21) == 23);\n\n assert(func0(11) == 15);\n\n assert(func0(15) == 15);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x1,%eax\ntest %edi,%edi\nje 11ab \npush %rbx\nmov %edi,%ebx\nlea 0x1(%rdi),%edx\nmov %edi,%eax\ntest %edi,%edx\njne 1184 \npop %rbx\nretq\nnot %eax\nand %edx,%eax\npxor %xmm0,%xmm0\ncvtsi2sd %eax,%xmm0\ncallq 1060 \naddsd 0xee3(%rip),%xmm0\ncvttsd2si %xmm0,%eax\nsub $0x1,%eax\nbts %eax,%ebx\nmov %ebx,%eax\njmp 1182 \nretq\n", + "ida_asm": "func0:\nendbr64\nmov eax, 1\ntest edi, edi\njz short locret_11AB\npush rbx\nmov ebx, edi\nlea edx, [rdi+1]\nmov eax, edi\ntest edx, edi\njnz short loc_1184\nloc_1182:\npop rbx\nretn\nloc_1184:\nnot eax\nand eax, edx\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax; x\ncall _log2\naddsd xmm0, cs:qword_2060\ncvttsd2si edx, xmm0\nsub edx, 1\nmov eax, ebx\nbts eax, edx\njmp short loc_1182\nlocret_11AB:\nretn", + "ida_pseudo": "int __fastcall func0(int a1)\n{\n int result; // eax\n double v2; // xmm0_8\n\n result = 1;\n if ( a1 )\n {\n result = a1;\n if ( (a1 & (a1 + 1)) != 0 )\n {\n v2 = log2((double)((a1 + 1) & ~a1));\n result = a1;\n _bittestandset(&result, (int)(v2 + 1.0) - 1);\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov eax, 1\ntest edi, edi\njz short locret_11AB\npush rbx\nmov ebx, edi\nlea edx, [rdi+1]\nmov eax, edi\ntest edx, edi\njnz short loc_1184\nloc_1182:\npop rbx\nretn\nloc_1184:\nnot eax\nand eax, edx\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax; x\ncall _log2\naddsd xmm0, cs:qword_2060\ncvttsd2si edx, xmm0\nsub edx, 1\nmov eax, ebx\nbts eax, edx\njmp short loc_1182\nlocret_11AB:\nretn", + "ida_strip_pseudo": "int __fastcall sub_1169(int a1)\n{\n int result; // eax\n double v2; // xmm0_8\n\n result = 1;\n if ( a1 )\n {\n result = a1;\n if ( (a1 & (a1 + 1)) != 0 )\n {\n v2 = log2((double)((a1 + 1) & ~a1));\n result = a1;\n _bittestandset(&result, (int)(v2 + 1.0) - 1);\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "int sub_1169(int a1) {\n int result;\n double v2;\n result = 1;\n if (a1) {\n result = a1;\n if ((a1 & (a1 + 1)) != 0) {\n v2 = log2((double)((a1 + 1) & ~a1));\n result = a1;\n _bittestandset(&result, (int)(v2 + 1.0) - 1);\n }\n }\n return result;\n}", + "ida_pseudo_norm": "int func0(int a1) {\n int result;\n double v2;\n result = 1;\n if (a1) {\n result = a1;\n if ((a1 & (a1 + 1)) != 0) {\n v2 = log2((double)((a1 + 1) & ~a1));\n result = a1;\n _bittestandset(&result, (int)(v2 + 1.0) - 1);\n }\n }\n return result;\n}" + }, + { + "index": 672, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int num1, int num2, int num3) {\n int lnum;\n if ((num1 >= num2) && (num1 >= num3)) {\n lnum = num1;\n } else if ((num2 >= num1) && (num2 >= num3)) {\n lnum = num2;\n } else {\n lnum = num3;\n }\n return lnum;\n}", + "test": "int main() {\n\n assert(func0(10, 20, 30) == 30);\n\n assert(func0(55, 47, 39) == 55);\n\n assert(func0(10, 49, 30) == 49);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov %edx,-0x1c(%rbp)\nmov -0x14(%rbp),%eax\ncmp -0x18(%rbp),%eax\njl 1172 \nmov -0x14(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1172 \nmov -0x14(%rbp),%eax\nmov %eax,-0x4(%rbp)\njmp 1190 \nmov -0x18(%rbp),%eax\ncmp -0x14(%rbp),%eax\njl 118a \nmov -0x18(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 118a \nmov -0x18(%rbp),%eax\nmov %eax,-0x4(%rbp)\njmp 1190 \nmov -0x1c(%rbp),%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_18]\njl short loc_1172\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_1C]\njl short loc_1172\nmov eax, [rbp+var_14]\nmov [rbp+var_4], eax\njmp short loc_1190\nloc_1172:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_14]\njl short loc_118A\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_1C]\njl short loc_118A\nmov eax, [rbp+var_18]\nmov [rbp+var_4], eax\njmp short loc_1190\nloc_118A:\nmov eax, [rbp+var_1C]\nmov [rbp+var_4], eax\nloc_1190:\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(signed int a1, signed int a2, signed int a3)\n{\n if ( a1 < a2 || a1 < a3 )\n {\n if ( a2 < a1 || a2 < a3 )\n return (unsigned int)a3;\n else\n return (unsigned int)a2;\n }\n else\n {\n return (unsigned int)a1;\n }\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_18]\njl short loc_1172\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_1C]\njl short loc_1172\nmov eax, [rbp+var_14]\nmov [rbp+var_4], eax\njmp short loc_1190\nloc_1172:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_14]\njl short loc_118A\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_1C]\njl short loc_118A\nmov eax, [rbp+var_18]\nmov [rbp+var_4], eax\njmp short loc_1190\nloc_118A:\nmov eax, [rbp+var_1C]\nmov [rbp+var_4], eax\nloc_1190:\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(signed int a1, signed int a2, signed int a3)\n{\n if ( a1 < a2 || a1 < a3 )\n {\n if ( a2 < a1 || a2 < a3 )\n return (unsigned int)a3;\n else\n return (unsigned int)a2;\n }\n else\n {\n return (unsigned int)a1;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(signed int a1, signed int a2, signed int a3) {\n if (a1 < a2 || a1 < a3) {\n if (a2 < a1 || a2 < a3)\n return (unsigned int)a3;\n else\n return (unsigned int)a2;\n } else {\n return (unsigned int)a1;\n }\n}", + "ida_pseudo_norm": "long long func0(signed int a1, signed int a2, signed int a3) {\n if (a1 < a2 || a1 < a3) {\n if (a2 < a1 || a2 < a3)\n return (unsigned int)a3;\n else\n return (unsigned int)a2;\n } else {\n return (unsigned int)a1;\n }\n}" + }, + { + "index": 673, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int list[], int size) {\n int res = 0;\n for (int i = 0; i < size; i++) {\n res = res * 10 + list[i];\n }\n return res;\n}", + "test": "int main() {\n\n int list1[] = {1, 2, 3};\n\n int size1 = sizeof(list1) / sizeof(list1[0]);\n\n assert(func0(list1, size1) == 123);\n\n \n\n int list2[] = {4, 5, 6};\n\n int size2 = sizeof(list2) / sizeof(list2[0]);\n\n assert(func0(list2, size2) == 456);\n\n \n\n int list3[] = {7, 8, 9};\n\n int size3 = sizeof(list3) / sizeof(list3[0]);\n\n assert(func0(list3, size3) == 789);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11b5 \nmov -0x8(%rbp),%edx\nmov %edx,%eax\nshl $0x2,%eax\nadd %edx,%eax\nadd %eax,%eax\nmov %eax,%ecx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nadd %ecx,%eax\nmov %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1188 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11B5\nloc_1188:\nmov edx, [rbp+var_8]\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nmov ecx, eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd eax, ecx\nmov [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_11B5:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n v3 = 10 * v3 + *(_DWORD *)(4LL * i + a1);\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11B5\nloc_1188:\nmov edx, [rbp+var_8]\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nmov ecx, eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd eax, ecx\nmov [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_11B5:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n v3 = 10 * v3 + *(_DWORD *)(4LL * i + a1);\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) v3 = 10 * v3 + *(uint32_t *)(4LL * i + a1);\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) v3 = 10 * v3 + *(uint32_t *)(4LL * i + a1);\n return v3;\n}" + }, + { + "index": 673, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int list[], int size) {\n int res = 0;\n for (int i = 0; i < size; i++) {\n res = res * 10 + list[i];\n }\n return res;\n}", + "test": "int main() {\n\n int list1[] = {1, 2, 3};\n\n int size1 = sizeof(list1) / sizeof(list1[0]);\n\n assert(func0(list1, size1) == 123);\n\n \n\n int list2[] = {4, 5, 6};\n\n int size2 = sizeof(list2) / sizeof(list2[0]);\n\n assert(func0(list2, size2) == 456);\n\n \n\n int list3[] = {7, 8, 9};\n\n int size3 = sizeof(list3) / sizeof(list3[0]);\n\n assert(func0(list3, size3) == 789);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1195 \nmov %rdi,%rax\nlea -0x1(%rsi),%edx\nlea 0x4(%rdi,%rdx,4),%rsi\nmov $0x0,%edx\nlea (%rdx,%rdx,4),%ecx\nmov (%rax),%edx\nlea (%rdx,%rcx,2),%edx\nadd $0x4,%rax\ncmp %rsi,%rax\njne 1181 \nmov %edx,%eax\nretq\nmov $0x0,%edx\njmp 1192 \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1194\nmov rax, rdi\nmovsxd rsi, esi\nlea rsi, [rdi+rsi*4]\nmov edx, 0\nloc_1180:\nlea ecx, [rdx+rdx*4]\nmov edx, [rax]\nlea edx, [rdx+rcx*2]\nadd rax, 4\ncmp rax, rsi\njnz short loc_1180\nloc_1191:\nmov eax, edx\nretn\nloc_1194:\nmov edx, 0\njmp short loc_1191", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n _DWORD *v3; // rsi\n unsigned int v4; // edx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n v4 = *v2++ + 10 * v4;\n while ( v2 != v3 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_1194\nmov rax, rdi\nmovsxd rsi, esi\nlea rsi, [rdi+rsi*4]\nmov edx, 0\nloc_1180:\nlea ecx, [rdx+rdx*4]\nmov edx, [rax]\nlea edx, [rdx+rcx*2]\nadd rax, 4\ncmp rax, rsi\njnz short loc_1180\nloc_1191:\nmov eax, edx\nretn\nloc_1194:\nmov edx, 0\njmp short loc_1191", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n _DWORD *v3; // rsi\n unsigned int v4; // edx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n v4 = *v2++ + 10 * v4;\n while ( v2 != v3 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2) {\n uint32_t *v2;\n uint32_t *v3;\n unsigned int v4;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n v4 = *v2++ + 10 * v4;\n while (v2 != v3);\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n uint32_t *v3;\n unsigned int v4;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n v4 = *v2++ + 10 * v4;\n while (v2 != v3);\n }\n return v4;\n}" + }, + { + "index": 674, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* string) {\n char* str = strdup(string);\n if (!str) return NULL;\n char* unique[100];\n int unique_count = 0;\n char* token = strtok(str, \" \");\n while (token != NULL) {\n int found = 0;\n for (int i = 0; i < unique_count; i++) {\n if (strcmp(token, unique[i]) == 0) {\n found = 1;\n break;\n }\n }\n if (!found) {\n unique[unique_count++] = token;\n }\n token = strtok(NULL, \" \");\n }\n int total_length = 0;\n for (int i = 0; i < unique_count; i++) {\n total_length += strlen(unique[i]) + 1;\n }\n char* result = malloc(total_length);\n if (!result) {\n free(str);\n return NULL;\n }\n result[0] = '\\0';\n for (int i = 0; i < unique_count; i++) {\n strcat(result, unique[i]);\n if (i < unique_count - 1) {\n strcat(result, \" \");\n }\n }\n free(str);\n return result;\n}", + "test": "int main(){\n\n assert(strcmp(func0(\"Python Exercises Practice Solution Exercises\"), \"Python Exercises Practice Solution\") == 0);\n\n assert(strcmp(func0(\"Python Exercises Practice Solution Python\"), \"Python Exercises Practice Solution\") == 0);\n\n assert(strcmp(func0(\"Python Exercises Practice Solution Practice\"), \"Python Exercises Practice Solution\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x370,%rsp\nmov %rdi,-0x368(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmov -0x368(%rbp),%rax\nmov %rax,%rdi\ncallq 1150 \nmov %rax,-0x340(%rbp)\ncmpq $0x0,-0x340(%rbp)\njne 1298 \nmov $0x0,%eax\njmpq 14a8 \nmovl $0x0,-0x360(%rbp)\nmov -0x340(%rbp),%rax\nlea 0xd58(%rip),%rsi\nmov %rax,%rdi\ncallq 1130 \nmov %rax,-0x348(%rbp)\njmpq 1362 \nmovl $0x0,-0x35c(%rbp)\nmovl $0x0,-0x358(%rbp)\njmp 1313 \nmov -0x358(%rbp),%eax\ncltq\nmov -0x330(%rbp,%rax,8),%rdx\nmov -0x348(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1110 \ntest %eax,%eax\njne 130c \nmovl $0x1,-0x35c(%rbp)\njmp 1321 \naddl $0x1,-0x358(%rbp)\nmov -0x358(%rbp),%eax\ncmp -0x360(%rbp),%eax\njl 12da \ncmpl $0x0,-0x35c(%rbp)\njne 134a \nmov -0x360(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x360(%rbp)\ncltq\nmov -0x348(%rbp),%rdx\nmov %rdx,-0x330(%rbp,%rax,8)\nlea 0xcb7(%rip),%rsi\nmov $0x0,%edi\ncallq 1130 \nmov %rax,-0x348(%rbp)\ncmpq $0x0,-0x348(%rbp)\njne 12c4 \nmovl $0x0,-0x354(%rbp)\nmovl $0x0,-0x350(%rbp)\njmp 13b8 \nmov -0x350(%rbp),%eax\ncltq\nmov -0x330(%rbp,%rax,8),%rax\nmov %rax,%rdi\ncallq 10e0 \nmov %eax,%edx\nmov -0x354(%rbp),%eax\nadd %edx,%eax\nadd $0x1,%eax\nmov %eax,-0x354(%rbp)\naddl $0x1,-0x350(%rbp)\nmov -0x350(%rbp),%eax\ncmp -0x360(%rbp),%eax\njl 1386 \nmov -0x354(%rbp),%eax\ncltq\nmov %rax,%rdi\ncallq 1120 \nmov %rax,-0x338(%rbp)\ncmpq $0x0,-0x338(%rbp)\njne 1400 \nmov -0x340(%rbp),%rax\nmov %rax,%rdi\ncallq 10d0 \nmov $0x0,%eax\njmpq 14a8 \nmov -0x338(%rbp),%rax\nmovb $0x0,(%rax)\nmovl $0x0,-0x34c(%rbp)\njmp 1484 \nmov -0x34c(%rbp),%eax\ncltq\nmov -0x330(%rbp,%rax,8),%rdx\nmov -0x338(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1140 \nmov -0x360(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x34c(%rbp)\njge 147d \nmov -0x338(%rbp),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nmov -0x338(%rbp),%rax\nadd %rdx,%rax\nmovw $0x20,(%rax)\naddl $0x1,-0x34c(%rbp)\nmov -0x34c(%rbp),%eax\ncmp -0x360(%rbp),%eax\njl 1416 \nmov -0x340(%rbp),%rax\nmov %rax,%rdi\ncallq 10d0 \nmov -0x338(%rbp),%rax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 14bc \ncallq 10f0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 370h\nmov [rbp+s], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strdup\nmov [rbp+var_340], rax\ncmp [rbp+var_340], 0\njnz short loc_1298\nmov eax, 0\njmp loc_149B\nloc_1298:\nmov [rbp+var_360], 0\nmov rax, [rbp+var_340]\nlea rdx, delim; \" \"\nmov rsi, rdx; delim\nmov rdi, rax; s\ncall _strtok\nmov [rbp+s1], rax\njmp loc_1368\nloc_12C7:\nmov [rbp+var_35C], 0\nmov [rbp+var_358], 0\njmp short loc_1316\nloc_12DD:\nmov eax, [rbp+var_358]\ncdqe\nmov rdx, [rbp+rax*8+s2]\nmov rax, [rbp+s1]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_130F\nmov [rbp+var_35C], 1\njmp short loc_1324\nloc_130F:\nadd [rbp+var_358], 1\nloc_1316:\nmov eax, [rbp+var_358]\ncmp eax, [rbp+var_360]\njl short loc_12DD\nloc_1324:\ncmp [rbp+var_35C], 0\njnz short loc_134D\nmov eax, [rbp+var_360]\nlea edx, [rax+1]\nmov [rbp+var_360], edx\ncdqe\nmov rdx, [rbp+s1]\nmov [rbp+rax*8+s2], rdx\nloc_134D:\nlea rax, delim; \" \"\nmov rsi, rax; delim\nmov edi, 0; s\ncall _strtok\nmov [rbp+s1], rax\nloc_1368:\ncmp [rbp+s1], 0\njnz loc_12C7\nmov [rbp+var_354], 0\nmov [rbp+var_350], 0\njmp short loc_13BE\nloc_138C:\nmov eax, [rbp+var_350]\ncdqe\nmov rax, [rbp+rax*8+s2]\nmov rdi, rax; s\ncall _strlen\nmov edx, eax\nmov eax, [rbp+var_354]\nadd eax, edx\nadd eax, 1\nmov [rbp+var_354], eax\nadd [rbp+var_350], 1\nloc_13BE:\nmov eax, [rbp+var_350]\ncmp eax, [rbp+var_360]\njl short loc_138C\nmov eax, [rbp+var_354]\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+dest], rax\ncmp [rbp+dest], 0\njnz short loc_1406\nmov rax, [rbp+var_340]\nmov rdi, rax; ptr\ncall _free\nmov eax, 0\njmp loc_149B\nloc_1406:\nmov rax, [rbp+dest]\nmov byte ptr [rax], 0\nmov [rbp+var_34C], 0\njmp short loc_1477\nloc_141C:\nmov eax, [rbp+var_34C]\ncdqe\nmov rdx, [rbp+rax*8+s2]\nmov rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\nmov eax, [rbp+var_360]\nsub eax, 1\ncmp [rbp+var_34C], eax\njge short loc_1470\nmov rax, [rbp+dest]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+dest]\nadd rax, rdx\nmov word ptr [rax], 20h ; ' '\nloc_1470:\nadd [rbp+var_34C], 1\nloc_1477:\nmov eax, [rbp+var_34C]\ncmp eax, [rbp+var_360]\njl short loc_141C\nmov rax, [rbp+var_340]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+dest]\nloc_149B:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_14AF\ncall ___stack_chk_fail\nlocret_14AF:\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(const char *a1)\n{\n int v2; // eax\n int v3; // [rsp+10h] [rbp-360h]\n int v4; // [rsp+14h] [rbp-35Ch]\n int i; // [rsp+18h] [rbp-358h]\n int v6; // [rsp+1Ch] [rbp-354h]\n int j; // [rsp+20h] [rbp-350h]\n int k; // [rsp+24h] [rbp-34Ch]\n const char *s1; // [rsp+28h] [rbp-348h]\n char *v10; // [rsp+30h] [rbp-340h]\n char *dest; // [rsp+38h] [rbp-338h]\n char *s2[102]; // [rsp+40h] [rbp-330h]\n\n s2[101] = (char *)__readfsqword(0x28u);\n v10 = strdup(a1);\n if ( !v10 )\n return 0LL;\n v3 = 0;\n for ( s1 = strtok(v10, \" \"); s1; s1 = strtok(0LL, \" \") )\n {\n v4 = 0;\n for ( i = 0; i < v3; ++i )\n {\n if ( !strcmp(s1, s2[i]) )\n {\n v4 = 1;\n break;\n }\n }\n if ( !v4 )\n {\n v2 = v3++;\n s2[v2] = (char *)s1;\n }\n }\n v6 = 0;\n for ( j = 0; j < v3; ++j )\n v6 += strlen(s2[j]) + 1;\n dest = (char *)malloc(v6);\n if ( dest )\n {\n *dest = 0;\n for ( k = 0; k < v3; ++k )\n {\n strcat(dest, s2[k]);\n if ( k < v3 - 1 )\n *(_WORD *)&dest[strlen(dest)] = 32;\n }\n free(v10);\n return dest;\n }\n else\n {\n free(v10);\n return 0LL;\n }\n}", + "ida_strip_asm": "sub_1249:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 370h\nmov [rbp+s], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strdup\nmov [rbp+var_340], rax\ncmp [rbp+var_340], 0\njnz short loc_1298\nmov eax, 0\njmp loc_149B\nloc_1298:\nmov [rbp+var_360], 0\nmov rax, [rbp+var_340]\nlea rdx, delim; \" \"\nmov rsi, rdx; delim\nmov rdi, rax; s\ncall _strtok\nmov [rbp+s1], rax\njmp loc_1368\nloc_12C7:\nmov [rbp+var_35C], 0\nmov [rbp+var_358], 0\njmp short loc_1316\nloc_12DD:\nmov eax, [rbp+var_358]\ncdqe\nmov rdx, [rbp+rax*8+s2]\nmov rax, [rbp+s1]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_130F\nmov [rbp+var_35C], 1\njmp short loc_1324\nloc_130F:\nadd [rbp+var_358], 1\nloc_1316:\nmov eax, [rbp+var_358]\ncmp eax, [rbp+var_360]\njl short loc_12DD\nloc_1324:\ncmp [rbp+var_35C], 0\njnz short loc_134D\nmov eax, [rbp+var_360]\nlea edx, [rax+1]\nmov [rbp+var_360], edx\ncdqe\nmov rdx, [rbp+s1]\nmov [rbp+rax*8+s2], rdx\nloc_134D:\nlea rax, delim; \" \"\nmov rsi, rax; delim\nmov edi, 0; s\ncall _strtok\nmov [rbp+s1], rax\nloc_1368:\ncmp [rbp+s1], 0\njnz loc_12C7\nmov [rbp+var_354], 0\nmov [rbp+var_350], 0\njmp short loc_13BE\nloc_138C:\nmov eax, [rbp+var_350]\ncdqe\nmov rax, [rbp+rax*8+s2]\nmov rdi, rax; s\ncall _strlen\nmov edx, eax\nmov eax, [rbp+var_354]\nadd eax, edx\nadd eax, 1\nmov [rbp+var_354], eax\nadd [rbp+var_350], 1\nloc_13BE:\nmov eax, [rbp+var_350]\ncmp eax, [rbp+var_360]\njl short loc_138C\nmov eax, [rbp+var_354]\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+dest], rax\ncmp [rbp+dest], 0\njnz short loc_1406\nmov rax, [rbp+var_340]\nmov rdi, rax; ptr\ncall _free\nmov eax, 0\njmp loc_149B\nloc_1406:\nmov rax, [rbp+dest]\nmov byte ptr [rax], 0\nmov [rbp+var_34C], 0\njmp short loc_1477\nloc_141C:\nmov eax, [rbp+var_34C]\ncdqe\nmov rdx, [rbp+rax*8+s2]\nmov rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\nmov eax, [rbp+var_360]\nsub eax, 1\ncmp [rbp+var_34C], eax\njge short loc_1470\nmov rax, [rbp+dest]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+dest]\nadd rax, rdx\nmov word ptr [rax], 20h ; ' '\nloc_1470:\nadd [rbp+var_34C], 1\nloc_1477:\nmov eax, [rbp+var_34C]\ncmp eax, [rbp+var_360]\njl short loc_141C\nmov rax, [rbp+var_340]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+dest]\nloc_149B:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_14AF\ncall ___stack_chk_fail\nlocret_14AF:\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1249(const char *a1)\n{\n int v2; // eax\n int v3; // [rsp+10h] [rbp-360h]\n int v4; // [rsp+14h] [rbp-35Ch]\n int i; // [rsp+18h] [rbp-358h]\n int v6; // [rsp+1Ch] [rbp-354h]\n int j; // [rsp+20h] [rbp-350h]\n int k; // [rsp+24h] [rbp-34Ch]\n const char *s1; // [rsp+28h] [rbp-348h]\n char *v10; // [rsp+30h] [rbp-340h]\n char *dest; // [rsp+38h] [rbp-338h]\n char *s2[102]; // [rsp+40h] [rbp-330h]\n\n s2[101] = (char *)__readfsqword(0x28u);\n v10 = strdup(a1);\n if ( !v10 )\n return 0LL;\n v3 = 0;\n for ( s1 = strtok(v10, \" \"); s1; s1 = strtok(0LL, \" \") )\n {\n v4 = 0;\n for ( i = 0; i < v3; ++i )\n {\n if ( !strcmp(s1, s2[i]) )\n {\n v4 = 1;\n break;\n }\n }\n if ( !v4 )\n {\n v2 = v3++;\n s2[v2] = (char *)s1;\n }\n }\n v6 = 0;\n for ( j = 0; j < v3; ++j )\n v6 += strlen(s2[j]) + 1;\n dest = (char *)malloc(v6);\n if ( dest )\n {\n *dest = 0;\n for ( k = 0; k < v3; ++k )\n {\n strcat(dest, s2[k]);\n if ( k < v3 - 1 )\n *(_WORD *)&dest[strlen(dest)] = 32;\n }\n free(v10);\n return dest;\n }\n else\n {\n free(v10);\n return 0LL;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1249(const char *a1) {\n int v2;\n int v3;\n int v4;\n int i;\n int v6;\n int j;\n int k;\n const char *s1;\n char *v10;\n char *dest;\n char *s2[102];\n s2[101] = (char *)__readfsqword(40u);\n v10 = strdup(a1);\n if (!v10) return 0LL;\n v3 = 0;\n for (s1 = strtok(v10, \" \"); s1; s1 = strtok(0LL, \" \")) {\n v4 = 0;\n for (i = 0; i < v3; ++i) {\n if (!strcmp(s1, s2[i])) {\n v4 = 1;\n break;\n }\n }\n if (!v4) {\n v2 = v3++;\n s2[v2] = (char *)s1;\n }\n }\n v6 = 0;\n for (j = 0; j < v3; ++j) v6 += strlen(s2[j]) + 1;\n dest = (char *)malloc(v6);\n if (dest) {\n *dest = 0;\n for (k = 0; k < v3; ++k) {\n strcat(dest, s2[k]);\n if (k < v3 - 1) *(unsigned short *)&dest[strlen(dest)] = 32;\n }\n free(v10);\n return dest;\n } else {\n free(v10);\n return 0LL;\n }\n}", + "ida_pseudo_norm": "char *func0(const char *a1) {\n int v2;\n int v3;\n int v4;\n int i;\n int v6;\n int j;\n int k;\n const char *s1;\n char *v10;\n char *dest;\n char *s2[102];\n s2[101] = (char *)__readfsqword(40u);\n v10 = strdup(a1);\n if (!v10) return 0LL;\n v3 = 0;\n for (s1 = strtok(v10, \" \"); s1; s1 = strtok(0LL, \" \")) {\n v4 = 0;\n for (i = 0; i < v3; ++i) {\n if (!strcmp(s1, s2[i])) {\n v4 = 1;\n break;\n }\n }\n if (!v4) {\n v2 = v3++;\n s2[v2] = (char *)s1;\n }\n }\n v6 = 0;\n for (j = 0; j < v3; ++j) v6 += strlen(s2[j]) + 1;\n dest = (char *)malloc(v6);\n if (dest) {\n *dest = 0;\n for (k = 0; k < v3; ++k) {\n strcat(dest, s2[k]);\n if (k < v3 - 1) *(unsigned short *)&dest[strlen(dest)] = 32;\n }\n free(v10);\n return dest;\n } else {\n free(v10);\n return 0LL;\n }\n}" + }, + { + "index": 674, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* string) {\n char* str = strdup(string);\n if (!str) return NULL;\n char* unique[100];\n int unique_count = 0;\n char* token = strtok(str, \" \");\n while (token != NULL) {\n int found = 0;\n for (int i = 0; i < unique_count; i++) {\n if (strcmp(token, unique[i]) == 0) {\n found = 1;\n break;\n }\n }\n if (!found) {\n unique[unique_count++] = token;\n }\n token = strtok(NULL, \" \");\n }\n int total_length = 0;\n for (int i = 0; i < unique_count; i++) {\n total_length += strlen(unique[i]) + 1;\n }\n char* result = malloc(total_length);\n if (!result) {\n free(str);\n return NULL;\n }\n result[0] = '\\0';\n for (int i = 0; i < unique_count; i++) {\n strcat(result, unique[i]);\n if (i < unique_count - 1) {\n strcat(result, \" \");\n }\n }\n free(str);\n return result;\n}", + "test": "int main(){\n\n assert(strcmp(func0(\"Python Exercises Practice Solution Exercises\"), \"Python Exercises Practice Solution\") == 0);\n\n assert(strcmp(func0(\"Python Exercises Practice Solution Python\"), \"Python Exercises Practice Solution\") == 0);\n\n assert(strcmp(func0(\"Python Exercises Practice Solution Practice\"), \"Python Exercises Practice Solution\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x338,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x328(%rsp)\nxor %eax,%eax\ncallq 1130 \nmov %rax,%r15\ntest %rax,%rax\nje 1382 \nlea 0xd9b(%rip),%rsi\nmov %rax,%rdi\ncallq 1110 \nmov %rax,%rbp\nmov $0x0,%r13d\nlea 0x8(%rsp),%r14\ntest %rax,%rax\njne 13b2 \nmov $0x0,%edi\ncallq 1100 \nmov %rax,%r12\ntest %rax,%rax\nje 1330 \nmovb $0x0,(%r12)\nmov %r15,%rdi\ncallq 10c0 \nmov 0x328(%rsp),%rax\nxor %fs:0x28,%rax\njne 13dc \nmov %r12,%rax\nadd $0x338,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\ntest %r13d,%r13d\njle 1288 \nmov %rsp,%rdx\nlea -0x1(%r13),%ebp\nlea 0x8(%rsp,%rbp,8),%r9\nmov $0x0,%esi\nmov $0xffffffffffffffff,%r8\nmov $0x0,%eax\nmov (%rdx),%rdi\nmov %r8,%rcx\nrepnz scas %es:(%rdi),%al\nnot %rcx\nlea (%rsi,%rcx,1),%esi\nadd $0x8,%rdx\ncmp %r9,%rdx\njne 12f9 \nmovslq %esi,%rdi\ncallq 1100 \nmov %rax,%r12\ntest %rax,%rax\nje 1330 \nmovb $0x0,(%r12)\nmov $0x0,%ebx\nsub $0x1,%r13d\njmp 1353 \nmov %r15,%rdi\ncallq 10c0 \nmov $0x0,%r12d\njmpq 12ab \nlea 0x1(%rbx),%rax\ncmp %rbx,%rbp\nje 12a3 \nmov %rax,%rbx\nmov (%rsp,%rbx,8),%rsi\nmov %r12,%rdi\ncallq 1120 \ncmp %ebx,%r13d\njle 1343 \nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nmov %r12,%rdi\nrepnz scas %es:(%rdi),%al\nnot %rcx\nmovw $0x20,-0x1(%r12,%rcx,1)\njmp 1343 \nmov %rax,%r12\njmpq 12ab \nmovslq %r13d,%rax\nmov %rbp,(%rsp,%rax,8)\nlea 0x1(%r13),%r13d\nlea 0xc68(%rip),%rsi\nmov $0x0,%edi\ncallq 1110 \nmov %rax,%rbp\ntest %rax,%rax\nje 12d7 \ntest %r13d,%r13d\njle 138a \nmov %rsp,%rbx\nlea -0x1(%r13),%eax\nlea (%r14,%rax,8),%r12\nmov (%rbx),%rsi\nmov %rbp,%rdi\ncallq 10f0 \ntest %eax,%eax\nje 1395 \nadd $0x8,%rbx\ncmp %r12,%rbx\njne 13c2 \njmp 138a \ncallq 10d0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 348h\nmov rax, fs:28h\nmov [rsp+378h+var_40], rax\nxor eax, eax\ncall _strdup\nmov [rsp+378h+ptr], rax\ntest rax, rax\njz loc_13E2\nmov rdi, rax; s\nlea rsi, delim; \" \"\ncall _strtok\nmov r12, rax\nmov ebp, 0\nlea r14, delim; \" \"\ntest rax, rax\njnz short loc_1318\nloc_12A7:\nmov edi, 0; size\ncall _malloc\nmov r13, rax\ntest rax, rax\njz loc_1399\nmov byte ptr [r13+0], 0\nloc_12C2:\nmov rdi, [rsp+378h+ptr]; ptr\ncall _free\nloc_12CC:\nmov rax, [rsp+378h+var_40]\nsub rax, fs:28h\njnz loc_13EC\nmov rax, r13\nadd rsp, 348h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_12F8:\nmovsxd rax, ebp\nmov [rsp+rax*8+378h+var_368], r12\nlea ebp, [rbp+1]\nloc_1303:\nmov rsi, r14; delim\nmov edi, 0; s\ncall _strtok\nmov r12, rax\ntest rax, rax\njz short loc_1342\nloc_1318:\ntest ebp, ebp\njle short loc_12F8\nlea rbx, [rsp+378h+var_368]\nmovsxd rax, ebp\nlea r13, [rbx+rax*8]\nloc_1328:\nmov rsi, [rbx]; s2\nmov rdi, r12; s1\ncall _strcmp\ntest eax, eax\njz short loc_1303\nadd rbx, 8\ncmp rbx, r13\njnz short loc_1328\njmp short loc_12F8\nloc_1342:\ntest ebp, ebp\njle loc_12A7\nlea rbx, [rsp+378h+var_368]\nmovsxd r14, ebp\nlea r15, [rbx+r14*8]\nmov r13d, 0\nloc_135C:\nmov rdi, [rbx]; s\ncall _strlen\nlea r12d, [r13+rax+1]\nmov r13d, r12d\nadd rbx, 8\ncmp rbx, r15\njnz short loc_135C\nmovsxd r12, r12d\nmov rdi, r12; size\ncall _malloc\nmov r13, rax\ntest rax, rax\njz short loc_1399\nmov byte ptr [rax], 0\nmov ebx, 0\nlea r15, delim; \" \"\njmp short loc_13BB\nloc_1399:\nmov rdi, [rsp+378h+ptr]; ptr\ncall _free\nmov r13d, 0\njmp loc_12CC\nloc_13AE:\nadd rbx, 1\ncmp rbx, r14\njz loc_12C2\nloc_13BB:\nmov rsi, [rsp+rbx*8+378h+var_368]\nmov rdx, r12\nmov rdi, r13\ncall ___strcat_chk\nlea eax, [rbp-1]\ncmp eax, ebx\njle short loc_13AE\nmov rdx, r12\nmov rsi, r15\nmov rdi, r13\ncall ___strcat_chk\njmp short loc_13AE\nloc_13E2:\nmov r13, [rsp+378h+ptr]\njmp loc_12CC\nloc_13EC:\ncall ___stack_chk_fail", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1)\n{\n char *v1; // rax\n char *v2; // r12\n int v3; // ebp\n _BYTE *v4; // rax\n _BYTE *v5; // r13\n const char **v7; // rbx\n const char **v8; // rbx\n int v9; // r13d\n int v10; // r12d\n _BYTE *v11; // rax\n __int64 i; // rbx\n char *ptr; // [rsp+8h] [rbp-370h]\n _QWORD v14[109]; // [rsp+10h] [rbp-368h] BYREF\n\n v14[101] = __readfsqword(0x28u);\n v1 = strdup(a1);\n ptr = v1;\n if ( !v1 )\n return 0LL;\n v2 = strtok(v1, \" \");\n v3 = 0;\n if ( v2 )\n {\n do\n {\n if ( v3 <= 0 )\n {\nLABEL_7:\n v14[v3++] = v2;\n }\n else\n {\n v7 = (const char **)v14;\n while ( strcmp(v2, *v7) )\n {\n if ( ++v7 == &v14[v3] )\n goto LABEL_7;\n }\n }\n v2 = strtok(0LL, \" \");\n }\n while ( v2 );\n if ( v3 > 0 )\n {\n v8 = (const char **)v14;\n v9 = 0;\n do\n {\n v10 = v9 + strlen(*v8) + 1;\n v9 = v10;\n ++v8;\n }\n while ( v8 != &v14[v3] );\n v11 = malloc(v10);\n v5 = v11;\n if ( v11 )\n {\n *v11 = 0;\n for ( i = 0LL; i != v3; ++i )\n {\n __strcat_chk(v5, v14[i], v10);\n if ( v3 - 1 > (int)i )\n __strcat_chk(v5, \" \", v10);\n }\n goto LABEL_5;\n }\nLABEL_19:\n free(ptr);\n return 0LL;\n }\n }\n v4 = malloc(0LL);\n v5 = v4;\n if ( !v4 )\n goto LABEL_19;\n *v4 = 0;\nLABEL_5:\n free(ptr);\n return v5;\n}", + "ida_strip_asm": "sub_1249:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 348h\nmov rax, fs:28h\nmov [rsp+378h+var_40], rax\nxor eax, eax\ncall _strdup\nmov [rsp+378h+ptr], rax\ntest rax, rax\njz loc_13E2\nmov rdi, rax; s\nlea rsi, delim; \" \"\ncall _strtok\nmov r12, rax\nmov ebp, 0\nlea r14, delim; \" \"\ntest rax, rax\njnz short loc_1318\nloc_12A7:\nmov edi, 0; size\ncall _malloc\nmov r13, rax\ntest rax, rax\njz loc_1399\nmov byte ptr [r13+0], 0\nloc_12C2:\nmov rdi, [rsp+378h+ptr]; ptr\ncall _free\nloc_12CC:\nmov rax, [rsp+378h+var_40]\nsub rax, fs:28h\njnz loc_13EC\nmov rax, r13\nadd rsp, 348h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_12F8:\nmovsxd rax, ebp\nmov [rsp+rax*8+378h+var_368], r12\nlea ebp, [rbp+1]\nloc_1303:\nmov rsi, r14; delim\nmov edi, 0; s\ncall _strtok\nmov r12, rax\ntest rax, rax\njz short loc_1342\nloc_1318:\ntest ebp, ebp\njle short loc_12F8\nlea rbx, [rsp+378h+var_368]\nmovsxd rax, ebp\nlea r13, [rbx+rax*8]\nloc_1328:\nmov rsi, [rbx]; s2\nmov rdi, r12; s1\ncall _strcmp\ntest eax, eax\njz short loc_1303\nadd rbx, 8\ncmp rbx, r13\njnz short loc_1328\njmp short loc_12F8\nloc_1342:\ntest ebp, ebp\njle loc_12A7\nlea rbx, [rsp+378h+var_368]\nmovsxd r14, ebp\nlea r15, [rbx+r14*8]\nmov r13d, 0\nloc_135C:\nmov rdi, [rbx]; s\ncall _strlen\nlea r12d, [r13+rax+1]\nmov r13d, r12d\nadd rbx, 8\ncmp rbx, r15\njnz short loc_135C\nmovsxd r12, r12d\nmov rdi, r12; size\ncall _malloc\nmov r13, rax\ntest rax, rax\njz short loc_1399\nmov byte ptr [rax], 0\nmov ebx, 0\nlea r15, delim; \" \"\njmp short loc_13BB\nloc_1399:\nmov rdi, [rsp+378h+ptr]; ptr\ncall _free\nmov r13d, 0\njmp loc_12CC\nloc_13AE:\nadd rbx, 1\ncmp rbx, r14\njz loc_12C2\nloc_13BB:\nmov rsi, [rsp+rbx*8+378h+var_368]\nmov rdx, r12\nmov rdi, r13\ncall ___strcat_chk\nlea eax, [rbp-1]\ncmp eax, ebx\njle short loc_13AE\nmov rdx, r12\nmov rsi, r15\nmov rdi, r13\ncall ___strcat_chk\njmp short loc_13AE\nloc_13E2:\nmov r13, [rsp+378h+ptr]\njmp loc_12CC\nloc_13EC:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1249(const char *a1)\n{\n char *v1; // rax\n char *v2; // r12\n int v3; // ebp\n _BYTE *v4; // rax\n _BYTE *v5; // r13\n const char **v7; // rbx\n const char **v8; // rbx\n int v9; // r13d\n int v10; // r12d\n _BYTE *v11; // rax\n __int64 i; // rbx\n char *ptr; // [rsp+8h] [rbp-370h]\n _QWORD v14[109]; // [rsp+10h] [rbp-368h] BYREF\n\n v14[101] = __readfsqword(0x28u);\n v1 = strdup(a1);\n ptr = v1;\n if ( !v1 )\n return 0LL;\n v2 = strtok(v1, \" \");\n v3 = 0;\n if ( v2 )\n {\n do\n {\n if ( v3 <= 0 )\n {\nLABEL_7:\n v14[v3++] = v2;\n }\n else\n {\n v7 = (const char **)v14;\n while ( strcmp(v2, *v7) )\n {\n if ( ++v7 == &v14[v3] )\n goto LABEL_7;\n }\n }\n v2 = strtok(0LL, \" \");\n }\n while ( v2 );\n if ( v3 > 0 )\n {\n v8 = (const char **)v14;\n v9 = 0;\n do\n {\n v10 = v9 + strlen(*v8) + 1;\n v9 = v10;\n ++v8;\n }\n while ( v8 != &v14[v3] );\n v11 = malloc(v10);\n v5 = v11;\n if ( v11 )\n {\n *v11 = 0;\n for ( i = 0LL; i != v3; ++i )\n {\n __strcat_chk(v5, v14[i], v10);\n if ( v3 - 1 > (int)i )\n __strcat_chk(v5, \" \", v10);\n }\n goto LABEL_5;\n }\nLABEL_19:\n free(ptr);\n return 0LL;\n }\n }\n v4 = malloc(0LL);\n v5 = v4;\n if ( !v4 )\n goto LABEL_19;\n *v4 = 0;\nLABEL_5:\n free(ptr);\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1249(const char *a1) {\n char *v1;\n char *v2;\n int v3;\n uint8_t *v4;\n uint8_t *v5;\n const char **v7;\n const char **v8;\n int v9;\n int v10;\n uint8_t *v11;\n long long i;\n char *ptr;\n uint64_t v14[109];\n v14[101] = __readfsqword(40u);\n v1 = strdup(a1);\n ptr = v1;\n if (!v1) return 0LL;\n v2 = strtok(v1, \" \");\n v3 = 0;\n if (v2) {\n do {\n if (v3 <= 0) {\n LABEL_7:\n v14[v3++] = v2;\n } else {\n v7 = (const char **)v14;\n while (strcmp(v2, *v7)) {\n if (++v7 == &v14[v3]) goto LABEL_7;\n }\n }\n v2 = strtok(0LL, \" \");\n } while (v2);\n if (v3 > 0) {\n v8 = (const char **)v14;\n v9 = 0;\n do {\n v10 = v9 + strlen(*v8) + 1;\n v9 = v10;\n ++v8;\n } while (v8 != &v14[v3]);\n v11 = malloc(v10);\n v5 = v11;\n if (v11) {\n *v11 = 0;\n for (i = 0LL; i != v3; ++i) {\n __strcat_chk(v5, v14[i], v10);\n if (v3 - 1 > (int)i) __strcat_chk(v5, \" \", v10);\n }\n goto LABEL_5;\n }\n LABEL_19:\n free(ptr);\n return 0LL;\n }\n }\n v4 = malloc(0LL);\n v5 = v4;\n if (!v4) goto LABEL_19;\n *v4 = 0;\nLABEL_5:\n free(ptr);\n return v5;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1) {\n char *v1;\n char *v2;\n int v3;\n uint8_t *v4;\n uint8_t *v5;\n const char **v7;\n const char **v8;\n int v9;\n int v10;\n uint8_t *v11;\n long long i;\n char *ptr;\n uint64_t v14[109];\n v14[101] = __readfsqword(40u);\n v1 = strdup(a1);\n ptr = v1;\n if (!v1) return 0LL;\n v2 = strtok(v1, \" \");\n v3 = 0;\n if (v2) {\n do {\n if (v3 <= 0) {\n LABEL_7:\n v14[v3++] = v2;\n } else {\n v7 = (const char **)v14;\n while (strcmp(v2, *v7)) {\n if (++v7 == &v14[v3]) goto LABEL_7;\n }\n }\n v2 = strtok(0LL, \" \");\n } while (v2);\n if (v3 > 0) {\n v8 = (const char **)v14;\n v9 = 0;\n do {\n v10 = v9 + strlen(*v8) + 1;\n v9 = v10;\n ++v8;\n } while (v8 != &v14[v3]);\n v11 = malloc(v10);\n v5 = v11;\n if (v11) {\n *v11 = 0;\n for (i = 0LL; i != v3; ++i) {\n __strcat_chk(v5, v14[i], v10);\n if (v3 - 1 > (int)i) __strcat_chk(v5, \" \", v10);\n }\n goto LABEL_5;\n }\n LABEL_19:\n free(ptr);\n return 0LL;\n }\n }\n v4 = malloc(0LL);\n v5 = v4;\n if (!v4) goto LABEL_19;\n *v4 = 0;\nLABEL_5:\n free(ptr);\n return v5;\n}" + }, + { + "index": 674, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* string) {\n char* str = strdup(string);\n if (!str) return NULL;\n char* unique[100];\n int unique_count = 0;\n char* token = strtok(str, \" \");\n while (token != NULL) {\n int found = 0;\n for (int i = 0; i < unique_count; i++) {\n if (strcmp(token, unique[i]) == 0) {\n found = 1;\n break;\n }\n }\n if (!found) {\n unique[unique_count++] = token;\n }\n token = strtok(NULL, \" \");\n }\n int total_length = 0;\n for (int i = 0; i < unique_count; i++) {\n total_length += strlen(unique[i]) + 1;\n }\n char* result = malloc(total_length);\n if (!result) {\n free(str);\n return NULL;\n }\n result[0] = '\\0';\n for (int i = 0; i < unique_count; i++) {\n strcat(result, unique[i]);\n if (i < unique_count - 1) {\n strcat(result, \" \");\n }\n }\n free(str);\n return result;\n}", + "test": "int main(){\n\n assert(strcmp(func0(\"Python Exercises Practice Solution Exercises\"), \"Python Exercises Practice Solution\") == 0);\n\n assert(strcmp(func0(\"Python Exercises Practice Solution Python\"), \"Python Exercises Practice Solution\") == 0);\n\n assert(strcmp(func0(\"Python Exercises Practice Solution Practice\"), \"Python Exercises Practice Solution\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x348,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x338(%rsp)\nxor %eax,%eax\ncallq 1150 \nmov %rax,0x8(%rsp)\ntest %rax,%rax\nje 1505 \nlea 0xc92(%rip),%rsi\nmov %rax,%rdi\nlea 0x10(%rsp),%r13\nxor %r12d,%r12d\ncallq 1140 \nlea 0xc7b(%rip),%r15\nmov %rax,%rbx\nlea 0x18(%rsp),%rax\nmov %rax,(%rsp)\ntest %rbx,%rbx\nje 14e1 \nxchg %ax,%ax\ntest %r12d,%r12d\nje 14d0 \nmov (%rsp),%rcx\nlea -0x1(%r12),%eax\nmov %r13,%r14\nlea (%rcx,%rax,8),%rbp\njmp 13cd \nnopl 0x0(%rax,%rax,1)\nadd $0x8,%r14\ncmp %rbp,%r14\nje 14d0 \nmov (%r14),%rsi\nmov %rbx,%rdi\ncallq 1120 \ntest %eax,%eax\njne 13c0 \nmov %r15,%rsi\nxor %edi,%edi\ncallq 1140 \nmov %rax,%rbx\ntest %rax,%rax\njne 13a0 \nmov (%rsp),%rax\nlea -0x1(%r12),%ebx\nmov %r13,%rbp\nxor %r15d,%r15d\nmov %rbx,%r12\nlea (%rax,%rbx,8),%r14\nnopl 0x0(%rax)\nmov 0x0(%rbp),%rdi\nadd $0x8,%rbp\ncallq 10f0 \nlea 0x1(%r15,%rax,1),%r15d\ncmp %rbp,%r14\njne 1408 \nmovslq %r15d,%rdi\ncallq 1130 \nmov %rax,%r14\ntest %rax,%rax\nje 14f6 \nmovb $0x0,(%r14)\nxor %ebp,%ebp\njmp 1443 \nnopl 0x0(%rax,%rax,1)\nmov %rax,%rbp\nmov %r14,%rdi\nmov (%rdi),%edx\nadd $0x4,%rdi\nlea -0x1010101(%rdx),%eax\nnot %edx\nand %edx,%eax\nand $0x80808080,%eax\nje 1446 \nmov %eax,%edx\nmov 0x0(%r13,%rbp,8),%rsi\nshr $0x10,%edx\ntest $0x8080,%eax\ncmove %edx,%eax\nlea 0x2(%rdi),%rdx\ncmove %rdx,%rdi\nmov %eax,%ecx\nadd %al,%cl\nsbb $0x3,%rdi\ncallq 10e0 \ncmp %ebp,%r12d\njle 1491 \nmov $0x20,%edx\nmov %dx,(%rax)\nlea 0x1(%rbp),%rax\ncmp %rbp,%rbx\njne 1440 \nmov 0x8(%rsp),%rdi\ncallq 10d0 \nmov 0x338(%rsp),%rax\nxor %fs:0x28,%rax\njne 150a \nadd $0x348,%rsp\nmov %r14,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\nmovslq %r12d,%rax\nadd $0x1,%r12d\nmov %rbx,0x10(%rsp,%rax,8)\njmpq 13dc \nxor %edi,%edi\ncallq 1130 \nmov %rax,%r14\ntest %rax,%rax\nje 14f6 \nmovb $0x0,(%r14)\njmp 149a \nmov 0x8(%rsp),%rdi\nxor %r14d,%r14d\ncallq 10d0 \njmp 14a4 \nxor %r14d,%r14d\njmp 14a4 \ncallq 1100 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 348h\nmov rax, fs:28h\nmov [rsp+378h+var_40], rax\nxor eax, eax\ncall _strdup\nmov [rsp+378h+ptr], rax\ntest rax, rax\njz loc_1501\nlea rsi, delim; \" \"\nmov rdi, rax; s\nlea r12, [rsp+378h+var_368]\nxor r15d, r15d\ncall _strtok\nmov rbx, rax\ntest rax, rax\njz loc_14E3\nxchg ax, ax\nloc_1390:\nmovsxd r14, r15d\nlea rbp, [r12+r14*8]\ntest r15d, r15d\njle loc_14B8\nloc_13A0:\nmov r13, r12\njmp short loc_13B5\nloc_13A8:\nadd r13, 8\ncmp r13, rbp\njz loc_14B8\nloc_13B5:\nmov rsi, [r13+0]; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_13A8\nlea rsi, delim; \" \"\nxor edi, edi; s\ncall _strtok\nmov rbx, rax\ntest rax, rax\njnz short loc_13A0\nmov ebp, r15d\nloc_13DE:\ntest ebp, ebp\njle loc_14E3\nlea r12, [rsp+378h+var_368]\nmovsxd r15, ebp\nxor r14d, r14d\nmov rbx, r12\nlea r13, [r12+r15*8]\nnop dword ptr [rax+rax+00000000h]\nloc_1400:\nmov rdi, [rbx]; s\nadd rbx, 8\ncall _strlen\nlea r14d, [r14+rax+1]\ncmp r13, rbx\njnz short loc_1400\nmovsxd rbx, r14d\nmov rdi, rbx; size\ncall _malloc\nmov r14, rax\ntest rax, rax\njz loc_14F7\nmov byte ptr [rax], 0\nlea r13d, [rbp-1]\nxor ebp, ebp\nnop word ptr [rax+rax+00000000h]\nloc_1440:\nmov rdi, r14; s\ncall _strlen\nmov rsi, [r12+rbp*8]\nmov rdx, rbx\nlea rdi, [r14+rax]\ncall ___stpcpy_chk\ncmp r13d, ebp\njle short loc_147A\nmov rcx, r14\nmov edx, 2\nlea rsi, delim; \" \"\nmov rdi, rax\nsub rcx, rax\nadd rcx, rbx\ncall ___memcpy_chk\nloc_147A:\nadd rbp, 1\ncmp r15, rbp\njnz short loc_1440\nloc_1483:\nmov rdi, [rsp+378h+ptr]; ptr\ncall _free\nloc_148D:\nmov rax, [rsp+378h+var_40]\nsub rax, fs:28h\njnz short loc_1506\nadd rsp, 348h\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14B8:\nlea rsi, delim; \" \"\nxor edi, edi; s\nmov [rsp+r14*8+378h+var_368], rbx\nlea ebp, [r15+1]\ncall _strtok\nmov rbx, rax\ntest rax, rax\njz loc_13DE\nmov r15d, ebp\njmp loc_1390\nloc_14E3:\nxor edi, edi; size\ncall _malloc\nmov r14, rax\ntest rax, rax\njz short loc_14F7\nmov byte ptr [rax], 0\njmp short loc_1483\nloc_14F7:\nmov rdi, [rsp+378h+ptr]; ptr\ncall _free\nloc_1501:\nxor r14d, r14d\njmp short loc_148D\nloc_1506:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n char *v1; // rax\n int v2; // r15d\n char *v3; // rbx\n const char **v4; // r13\n int v5; // ebp\n __int64 v6; // r15\n int v7; // r14d\n const char **v8; // rbx\n const char *v9; // rdi\n __int64 v10; // rbx\n const char *v11; // rax\n const char *v12; // r14\n int v13; // r13d\n __int64 i; // rbp\n size_t v15; // rax\n __int64 v16; // rax\n const char *v18; // rax\n char *ptr; // [rsp+8h] [rbp-370h]\n _QWORD v20[109]; // [rsp+10h] [rbp-368h] BYREF\n\n v20[101] = __readfsqword(0x28u);\n v1 = strdup(a1);\n ptr = v1;\n if ( !v1 )\n return 0LL;\n v2 = 0;\n v3 = strtok(v1, \" \");\n if ( v3 )\n {\n while ( v2 <= 0 )\n {\nLABEL_19:\n v20[v2] = v3;\n v5 = v2 + 1;\n v3 = strtok(0LL, \" \");\n if ( !v3 )\n goto LABEL_9;\n ++v2;\n }\n do\n {\n v4 = (const char **)v20;\n while ( strcmp(v3, *v4) )\n {\n if ( ++v4 == &v20[v2] )\n goto LABEL_19;\n }\n v3 = strtok(0LL, \" \");\n }\n while ( v3 );\n v5 = v2;\nLABEL_9:\n if ( v5 > 0 )\n {\n v6 = v5;\n v7 = 0;\n v8 = (const char **)v20;\n do\n {\n v9 = *v8++;\n v7 += strlen(v9) + 1;\n }\n while ( &v20[v5] != v8 );\n v10 = v7;\n v11 = (const char *)malloc(v7);\n v12 = v11;\n if ( v11 )\n {\n *v11 = 0;\n v13 = v5 - 1;\n for ( i = 0LL; i != v6; ++i )\n {\n v15 = strlen(v12);\n v16 = __stpcpy_chk(&v12[v15], v20[i], v10);\n if ( v13 > (int)i )\n __memcpy_chk(v16, \" \", 2LL, &v12[v10 - v16]);\n }\n goto LABEL_17;\n }\n goto LABEL_23;\n }\n }\n v18 = (const char *)malloc(0LL);\n v12 = v18;\n if ( !v18 )\n {\nLABEL_23:\n free(ptr);\n return 0LL;\n }\n *v18 = 0;\nLABEL_17:\n free(ptr);\n return v12;\n}", + "ida_strip_asm": "sub_1330:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 348h\nmov rax, fs:28h\nmov [rsp+378h+var_40], rax\nxor eax, eax\ncall _strdup\nmov [rsp+378h+ptr], rax\ntest rax, rax\njz loc_1501\nlea rsi, delim; \" \"\nmov rdi, rax; s\nlea r12, [rsp+378h+var_368]\nxor r15d, r15d\ncall _strtok\nmov rbx, rax\ntest rax, rax\njz loc_14E3\nxchg ax, ax\nloc_1390:\nmovsxd r14, r15d\nlea rbp, [r12+r14*8]\ntest r15d, r15d\njle loc_14B8\nloc_13A0:\nmov r13, r12\njmp short loc_13B5\nloc_13A8:\nadd r13, 8\ncmp r13, rbp\njz loc_14B8\nloc_13B5:\nmov rsi, [r13+0]; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_13A8\nlea rsi, delim; \" \"\nxor edi, edi; s\ncall _strtok\nmov rbx, rax\ntest rax, rax\njnz short loc_13A0\nmov ebp, r15d\nloc_13DE:\ntest ebp, ebp\njle loc_14E3\nlea r12, [rsp+378h+var_368]\nmovsxd r15, ebp\nxor r14d, r14d\nmov rbx, r12\nlea r13, [r12+r15*8]\nnop dword ptr [rax+rax+00000000h]\nloc_1400:\nmov rdi, [rbx]; s\nadd rbx, 8\ncall _strlen\nlea r14d, [r14+rax+1]\ncmp r13, rbx\njnz short loc_1400\nmovsxd rbx, r14d\nmov rdi, rbx; size\ncall _malloc\nmov r14, rax\ntest rax, rax\njz loc_14F7\nmov byte ptr [rax], 0\nlea r13d, [rbp-1]\nxor ebp, ebp\nnop word ptr [rax+rax+00000000h]\nloc_1440:\nmov rdi, r14; s\ncall _strlen\nmov rsi, [r12+rbp*8]\nmov rdx, rbx\nlea rdi, [r14+rax]\ncall ___stpcpy_chk\ncmp r13d, ebp\njle short loc_147A\nmov rcx, r14\nmov edx, 2\nlea rsi, delim; \" \"\nmov rdi, rax\nsub rcx, rax\nadd rcx, rbx\ncall ___memcpy_chk\nloc_147A:\nadd rbp, 1\ncmp r15, rbp\njnz short loc_1440\nloc_1483:\nmov rdi, [rsp+378h+ptr]; ptr\ncall _free\nloc_148D:\nmov rax, [rsp+378h+var_40]\nsub rax, fs:28h\njnz short loc_1506\nadd rsp, 348h\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14B8:\nlea rsi, delim; \" \"\nxor edi, edi; s\nmov [rsp+r14*8+378h+var_368], rbx\nlea ebp, [r15+1]\ncall _strtok\nmov rbx, rax\ntest rax, rax\njz loc_13DE\nmov r15d, ebp\njmp loc_1390\nloc_14E3:\nxor edi, edi; size\ncall _malloc\nmov r14, rax\ntest rax, rax\njz short loc_14F7\nmov byte ptr [rax], 0\njmp short loc_1483\nloc_14F7:\nmov rdi, [rsp+378h+ptr]; ptr\ncall _free\nloc_1501:\nxor r14d, r14d\njmp short loc_148D\nloc_1506:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_1330(const char *a1)\n{\n char *v1; // rax\n int v2; // r15d\n char *v3; // rbx\n const char **v4; // r13\n int v5; // ebp\n __int64 v6; // r15\n int v7; // r14d\n const char **v8; // rbx\n const char *v9; // rdi\n __int64 v10; // rbx\n const char *v11; // rax\n const char *v12; // r14\n int v13; // r13d\n __int64 i; // rbp\n size_t v15; // rax\n __int64 v16; // rax\n const char *v18; // rax\n char *ptr; // [rsp+8h] [rbp-370h]\n _QWORD v20[109]; // [rsp+10h] [rbp-368h] BYREF\n\n v20[101] = __readfsqword(0x28u);\n v1 = strdup(a1);\n ptr = v1;\n if ( !v1 )\n return 0LL;\n v2 = 0;\n v3 = strtok(v1, \" \");\n if ( v3 )\n {\n while ( v2 <= 0 )\n {\nLABEL_19:\n v20[v2] = v3;\n v5 = v2 + 1;\n v3 = strtok(0LL, \" \");\n if ( !v3 )\n goto LABEL_9;\n ++v2;\n }\n do\n {\n v4 = (const char **)v20;\n while ( strcmp(v3, *v4) )\n {\n if ( ++v4 == &v20[v2] )\n goto LABEL_19;\n }\n v3 = strtok(0LL, \" \");\n }\n while ( v3 );\n v5 = v2;\nLABEL_9:\n if ( v5 > 0 )\n {\n v6 = v5;\n v7 = 0;\n v8 = (const char **)v20;\n do\n {\n v9 = *v8++;\n v7 += strlen(v9) + 1;\n }\n while ( &v20[v5] != v8 );\n v10 = v7;\n v11 = (const char *)malloc(v7);\n v12 = v11;\n if ( v11 )\n {\n *v11 = 0;\n v13 = v5 - 1;\n for ( i = 0LL; i != v6; ++i )\n {\n v15 = strlen(v12);\n v16 = __stpcpy_chk(&v12[v15], v20[i], v10);\n if ( v13 > (int)i )\n __memcpy_chk(v16, \" \", 2LL, &v12[v10 - v16]);\n }\n goto LABEL_17;\n }\n goto LABEL_23;\n }\n }\n v18 = (const char *)malloc(0LL);\n v12 = v18;\n if ( !v18 )\n {\nLABEL_23:\n free(ptr);\n return 0LL;\n }\n *v18 = 0;\nLABEL_17:\n free(ptr);\n return v12;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1330(const char *a1) {\n char *v1;\n int v2;\n char *v3;\n const char **v4;\n int v5;\n long long v6;\n int v7;\n const char **v8;\n const char *v9;\n long long v10;\n const char *v11;\n const char *v12;\n int v13;\n long long i;\n unsigned int v15;\n long long v16;\n const char *v18;\n char *ptr;\n uint64_t v20[109];\n v20[101] = __readfsqword(40u);\n v1 = strdup(a1);\n ptr = v1;\n if (!v1) return 0LL;\n v2 = 0;\n v3 = strtok(v1, \" \");\n if (v3) {\n while (v2 <= 0) {\n LABEL_19:\n v20[v2] = v3;\n v5 = v2 + 1;\n v3 = strtok(0LL, \" \");\n if (!v3) goto LABEL_9;\n ++v2;\n }\n do {\n v4 = (const char **)v20;\n while (strcmp(v3, *v4)) {\n if (++v4 == &v20[v2]) goto LABEL_19;\n }\n v3 = strtok(0LL, \" \");\n } while (v3);\n v5 = v2;\n LABEL_9:\n if (v5 > 0) {\n v6 = v5;\n v7 = 0;\n v8 = (const char **)v20;\n do {\n v9 = *v8++;\n v7 += strlen(v9) + 1;\n } while (&v20[v5] != v8);\n v10 = v7;\n v11 = (const char *)malloc(v7);\n v12 = v11;\n if (v11) {\n *v11 = 0;\n v13 = v5 - 1;\n for (i = 0LL; i != v6; ++i) {\n v15 = strlen(v12);\n v16 = __stpcpy_chk(&v12[v15], v20[i], v10);\n if (v13 > (int)i) __memcpy_chk(v16, \" \", 2LL, &v12[v10 - v16]);\n }\n goto LABEL_17;\n }\n goto LABEL_23;\n }\n }\n v18 = (const char *)malloc(0LL);\n v12 = v18;\n if (!v18) {\n LABEL_23:\n free(ptr);\n return 0LL;\n }\n *v18 = 0;\nLABEL_17:\n free(ptr);\n return v12;\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n char *v1;\n int v2;\n char *v3;\n const char **v4;\n int v5;\n long long v6;\n int v7;\n const char **v8;\n const char *v9;\n long long v10;\n const char *v11;\n const char *v12;\n int v13;\n long long i;\n unsigned int v15;\n long long v16;\n const char *v18;\n char *ptr;\n uint64_t v20[109];\n v20[101] = __readfsqword(40u);\n v1 = strdup(a1);\n ptr = v1;\n if (!v1) return 0LL;\n v2 = 0;\n v3 = strtok(v1, \" \");\n if (v3) {\n while (v2 <= 0) {\n LABEL_19:\n v20[v2] = v3;\n v5 = v2 + 1;\n v3 = strtok(0LL, \" \");\n if (!v3) goto LABEL_9;\n ++v2;\n }\n do {\n v4 = (const char **)v20;\n while (strcmp(v3, *v4)) {\n if (++v4 == &v20[v2]) goto LABEL_19;\n }\n v3 = strtok(0LL, \" \");\n } while (v3);\n v5 = v2;\n LABEL_9:\n if (v5 > 0) {\n v6 = v5;\n v7 = 0;\n v8 = (const char **)v20;\n do {\n v9 = *v8++;\n v7 += strlen(v9) + 1;\n } while (&v20[v5] != v8);\n v10 = v7;\n v11 = (const char *)malloc(v7);\n v12 = v11;\n if (v11) {\n *v11 = 0;\n v13 = v5 - 1;\n for (i = 0LL; i != v6; ++i) {\n v15 = strlen(v12);\n v16 = __stpcpy_chk(&v12[v15], v20[i], v10);\n if (v13 > (int)i) __memcpy_chk(v16, \" \", 2LL, &v12[v10 - v16]);\n }\n goto LABEL_17;\n }\n goto LABEL_23;\n }\n }\n v18 = (const char *)malloc(0LL);\n v12 = v18;\n if (!v18) {\n LABEL_23:\n free(ptr);\n return 0LL;\n }\n *v18 = 0;\nLABEL_17:\n free(ptr);\n return v12;\n}" + }, + { + "index": 674, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* string) {\n char* str = strdup(string);\n if (!str) return NULL;\n char* unique[100];\n int unique_count = 0;\n char* token = strtok(str, \" \");\n while (token != NULL) {\n int found = 0;\n for (int i = 0; i < unique_count; i++) {\n if (strcmp(token, unique[i]) == 0) {\n found = 1;\n break;\n }\n }\n if (!found) {\n unique[unique_count++] = token;\n }\n token = strtok(NULL, \" \");\n }\n int total_length = 0;\n for (int i = 0; i < unique_count; i++) {\n total_length += strlen(unique[i]) + 1;\n }\n char* result = malloc(total_length);\n if (!result) {\n free(str);\n return NULL;\n }\n result[0] = '\\0';\n for (int i = 0; i < unique_count; i++) {\n strcat(result, unique[i]);\n if (i < unique_count - 1) {\n strcat(result, \" \");\n }\n }\n free(str);\n return result;\n}", + "test": "int main(){\n\n assert(strcmp(func0(\"Python Exercises Practice Solution Exercises\"), \"Python Exercises Practice Solution\") == 0);\n\n assert(strcmp(func0(\"Python Exercises Practice Solution Python\"), \"Python Exercises Practice Solution\") == 0);\n\n assert(strcmp(func0(\"Python Exercises Practice Solution Practice\"), \"Python Exercises Practice Solution\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x348,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x338(%rsp)\nxor %eax,%eax\ncallq 1170 \nmov %rax,0x8(%rsp)\ntest %rax,%rax\nje 155c \nlea 0xc72(%rip),%rsi\nmov %rax,%rdi\nlea 0x10(%rsp),%r13\nxor %r12d,%r12d\ncallq 1150 \nlea 0xc5b(%rip),%r15\nmov %rax,%rbx\nlea 0x18(%rsp),%rax\nmov %rax,(%rsp)\ntest %rbx,%rbx\nje 1532 \nxchg %ax,%ax\ntest %r12d,%r12d\nje 14b0 \nmov (%rsp),%rcx\nlea -0x1(%r12),%eax\nmov %r13,%r14\nlea (%rcx,%rax,8),%rbp\njmp 13ed \nnopl 0x0(%rax,%rax,1)\nadd $0x8,%r14\ncmp %rbp,%r14\nje 14b0 \nmov (%r14),%rsi\nmov %rbx,%rdi\ncallq 1130 \ntest %eax,%eax\njne 13e0 \nmov %r15,%rsi\nxor %edi,%edi\ncallq 1150 \nmov %rax,%rbx\ntest %rax,%rax\njne 13c0 \nmov (%rsp),%rcx\nlea -0x1(%r12),%eax\nmov %r13,%rbp\nxor %r15d,%r15d\nmov %rax,%rbx\nlea (%rcx,%rax,8),%r14\nnopl 0x0(%rax)\nmov 0x0(%rbp),%rdi\nadd $0x8,%rbp\ncallq 1100 \nlea 0x1(%r15,%rax,1),%r15d\ncmp %r14,%rbp\njne 1428 \nmovslq %r15d,%rdi\ncallq 1140 \nmov %rax,%r14\ntest %rax,%rax\nje 154a \nmovb $0x0,(%r14)\ntest %ebx,%ebx\njg 14c8 \nxor %eax,%eax\nmovslq %eax,%rbx\nmov 0x0(%r13,%rbx,8),%rsi\nmov %r14,%rdi\nadd $0x1,%rbx\ncallq 1160 \ncmp %ebx,%r12d\njg 1460 \nmov 0x8(%rsp),%rdi\ncallq 10e0 \nmov 0x338(%rsp),%rax\nxor %fs:0x28,%rax\njne 1564 \nadd $0x348,%rsp\nmov %r14,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\nmovslq %r12d,%rax\nadd $0x1,%r12d\nmov %rbx,0x10(%rsp,%rax,8)\njmpq 13fc \nnopl 0x0(%rax)\nxor %ebp,%ebp\nnopw 0x0(%rax,%rax,1)\nmov %r14,%rdi\nmov (%rdi),%edx\nadd $0x4,%rdi\nlea -0x1010101(%rdx),%eax\nnot %edx\nand %edx,%eax\nand $0x80808080,%eax\nje 14d3 \nmov %eax,%edx\nmov 0x0(%r13,%rbp,8),%rsi\nshr $0x10,%edx\ntest $0x8080,%eax\ncmove %edx,%eax\nlea 0x2(%rdi),%rdx\ncmove %rdx,%rdi\nmov %eax,%ecx\nadd %al,%cl\nsbb $0x3,%rdi\ncallq 10f0 \nmov $0x20,%edx\nmov %dx,(%rax)\nlea 0x1(%rbp),%eax\nadd $0x1,%rbp\ncmp %ebp,%ebx\njg 14d0 \ncmp %eax,%r12d\njg 145d \njmpq 1476 \nxor %edi,%edi\ncallq 1140 \nmov %rax,%r14\ntest %rax,%rax\nje 154a \nmovb $0x0,(%r14)\njmpq 1476 \nmov 0x8(%rsp),%rdi\nxor %r14d,%r14d\ncallq 10e0 \njmpq 1480 \nxor %r14d,%r14d\njmpq 1480 \ncallq 1110 <__stack_chk_fail@plt>\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 348h\nmov rax, fs:28h\nmov [rsp+378h+var_40], rax\nxor eax, eax\ncall _strdup\nmov [rsp+378h+ptr], rax\ntest rax, rax\njz loc_155B\nlea rsi, delim; \" \"\nmov rdi, rax; s\nlea r13, [rsp+378h+var_368]\nxor ebx, ebx\ncall _strtok\nmov rbp, rax\ntest rax, rax\njz loc_1535\nnop dword ptr [rax]\nloc_13B0:\nmovsxd r14, ebx\nlea r12, [r13+r14*8+0]\ntest ebx, ebx\njle loc_14B0\nloc_13C0:\nmov r15, r13\njmp short loc_13D5\nloc_13C8:\nadd r15, 8\ncmp r15, r12\njz loc_14B0\nloc_13D5:\nmov rsi, [r15]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njnz short loc_13C8\nlea rsi, delim; \" \"\nxor edi, edi; s\ncall _strtok\nmov rbp, rax\ntest rax, rax\njnz short loc_13C0\nloc_13FA:\ntest ebx, ebx\njle loc_1535\nlea r13, [rsp+378h+var_368]\nmovsxd rax, ebx\nxor ebp, ebp\nmov r12, r13\nlea r14, [r13+rax*8+0]\nnop dword ptr [rax+00h]\nloc_1418:\nmov rdi, [r12]; s\nadd r12, 8\ncall _strlen\nlea ebp, [rbp+rax+1]\ncmp r12, r14\njnz short loc_1418\nmovsxd rbp, ebp\nmov rdi, rbp; size\ncall _malloc\nmov r14, rax\ntest rax, rax\njz loc_1551\nmov byte ptr [rax], 0\nlea eax, [rbx-1]\nxor r12d, r12d\nmov r15d, eax\ntest eax, eax\njg loc_14D7\nloc_1459:\nmovsxd r12, r12d\nnop dword ptr [rax+00h]\nloc_1460:\nmov rsi, [r13+r12*8+0]\nmov rdx, rbp\nmov rdi, r14\nadd r12, 1\ncall ___strcat_chk\ncmp ebx, r12d\njg short loc_1460\nloc_1479:\nmov rdi, [rsp+378h+ptr]; ptr\ncall _free\nloc_1483:\nmov rax, [rsp+378h+var_40]\nsub rax, fs:28h\njnz loc_154C\nadd rsp, 348h\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14B0:\nlea rsi, delim; \" \"\nxor edi, edi; s\nmov [rsp+r14*8+378h+var_368], rbp\nadd ebx, 1\ncall _strtok\nmov rbp, rax\ntest rax, rax\njnz loc_13B0\njmp loc_13FA\nloc_14D7:\nxor r12d, r12d\nloc_14DA:\nmov rdi, r14; s\ncall _strlen\nmov rsi, [r13+r12*8+0]\nmov rdx, rbp\nlea rdi, [r14+rax]\ncall ___stpcpy_chk\nmov rcx, r14\nmov edx, 2\nlea rsi, delim; \" \"\nsub rcx, rax\nmov rdi, rax\nadd rcx, rbp\ncall ___memcpy_chk\nlea rax, [r12+1]\ncmp r15d, eax\njg short loc_1530\nadd r12d, 1\ncmp r12d, ebx\njl loc_1459\njmp loc_1479\nloc_1530:\nmov r12, rax\njmp short loc_14DA\nloc_1535:\nxor edi, edi; size\ncall _malloc\nmov r14, rax\ntest rax, rax\njz short loc_1551\nmov byte ptr [rax], 0\njmp loc_1479\nloc_154C:\ncall ___stack_chk_fail\nloc_1551:\nmov rdi, [rsp+378h+ptr]; ptr\ncall _free\nloc_155B:\nxor r14d, r14d\njmp loc_1483", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n char *v1; // rax\n int v2; // ebx\n char *v3; // rbp\n const char **v4; // r15\n int v5; // ebp\n const char **v6; // r12\n const char *v7; // rdi\n const char *v8; // rax\n const char *v9; // r14\n __int64 i; // r12\n __int64 v11; // rsi\n size_t v13; // rax\n __int64 v14; // rax\n const char *v15; // rax\n char *ptr; // [rsp+8h] [rbp-370h]\n _QWORD v17[109]; // [rsp+10h] [rbp-368h] BYREF\n\n v17[101] = __readfsqword(0x28u);\n v1 = strdup(a1);\n ptr = v1;\n if ( !v1 )\n return 0LL;\n v2 = 0;\n v3 = strtok(v1, \" \");\n if ( v3 )\n {\n while ( v2 <= 0 )\n {\nLABEL_17:\n v17[v2++] = v3;\n v3 = strtok(0LL, \" \");\n if ( !v3 )\n goto LABEL_8;\n }\n do\n {\n v4 = (const char **)v17;\n while ( strcmp(v3, *v4) )\n {\n if ( ++v4 == &v17[v2] )\n goto LABEL_17;\n }\n v3 = strtok(0LL, \" \");\n }\n while ( v3 );\nLABEL_8:\n if ( v2 > 0 )\n {\n v5 = 0;\n v6 = (const char **)v17;\n do\n {\n v7 = *v6++;\n v5 += strlen(v7) + 1;\n }\n while ( v6 != &v17[v2] );\n v8 = (const char *)malloc(v5);\n v9 = v8;\n if ( v8 )\n {\n *v8 = 0;\n LODWORD(i) = 0;\n if ( v2 - 1 <= 0 )\n goto LABEL_13;\n for ( i = 0LL; ; ++i )\n {\n v13 = strlen(v9);\n v14 = __stpcpy_chk(&v9[v13], v17[i], v5);\n __memcpy_chk(v14, \" \", 2LL, &v9[v5 - v14]);\n if ( v2 - 1 <= (int)i + 1 )\n break;\n }\n LODWORD(i) = i + 1;\n if ( (int)i < v2 )\n {\nLABEL_13:\n i = (int)i;\n do\n {\n v11 = v17[i++];\n __strcat_chk(v9, v11, v5);\n }\n while ( v2 > (int)i );\n }\n goto LABEL_15;\n }\n goto LABEL_26;\n }\n }\n v15 = (const char *)malloc(0LL);\n v9 = v15;\n if ( !v15 )\n {\nLABEL_26:\n free(ptr);\n return 0LL;\n }\n *v15 = 0;\nLABEL_15:\n free(ptr);\n return v9;\n}", + "ida_strip_asm": "sub_1350:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 348h\nmov rax, fs:28h\nmov [rsp+378h+var_40], rax\nxor eax, eax\ncall _strdup\nmov [rsp+378h+ptr], rax\ntest rax, rax\njz loc_155B\nlea rsi, delim; \" \"\nmov rdi, rax; s\nlea r13, [rsp+378h+var_368]\nxor ebx, ebx\ncall _strtok\nmov rbp, rax\ntest rax, rax\njz loc_1535\nnop dword ptr [rax]\nloc_13B0:\nmovsxd r14, ebx\nlea r12, [r13+r14*8+0]\ntest ebx, ebx\njle loc_14B0\nloc_13C0:\nmov r15, r13\njmp short loc_13D5\nloc_13C8:\nadd r15, 8\ncmp r15, r12\njz loc_14B0\nloc_13D5:\nmov rsi, [r15]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njnz short loc_13C8\nlea rsi, delim; \" \"\nxor edi, edi; s\ncall _strtok\nmov rbp, rax\ntest rax, rax\njnz short loc_13C0\nloc_13FA:\ntest ebx, ebx\njle loc_1535\nlea r13, [rsp+378h+var_368]\nmovsxd rax, ebx\nxor ebp, ebp\nmov r12, r13\nlea r14, [r13+rax*8+0]\nnop dword ptr [rax+00h]\nloc_1418:\nmov rdi, [r12]; s\nadd r12, 8\ncall _strlen\nlea ebp, [rbp+rax+1]\ncmp r12, r14\njnz short loc_1418\nmovsxd rbp, ebp\nmov rdi, rbp; size\ncall _malloc\nmov r14, rax\ntest rax, rax\njz loc_1551\nmov byte ptr [rax], 0\nlea eax, [rbx-1]\nxor r12d, r12d\nmov r15d, eax\ntest eax, eax\njg loc_14D7\nloc_1459:\nmovsxd r12, r12d\nnop dword ptr [rax+00h]\nloc_1460:\nmov rsi, [r13+r12*8+0]\nmov rdx, rbp\nmov rdi, r14\nadd r12, 1\ncall ___strcat_chk\ncmp ebx, r12d\njg short loc_1460\nloc_1479:\nmov rdi, [rsp+378h+ptr]; ptr\ncall _free\nloc_1483:\nmov rax, [rsp+378h+var_40]\nsub rax, fs:28h\njnz loc_154C\nadd rsp, 348h\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14B0:\nlea rsi, delim; \" \"\nxor edi, edi; s\nmov [rsp+r14*8+378h+var_368], rbp\nadd ebx, 1\ncall _strtok\nmov rbp, rax\ntest rax, rax\njnz loc_13B0\njmp loc_13FA\nloc_14D7:\nxor r12d, r12d\nloc_14DA:\nmov rdi, r14; s\ncall _strlen\nmov rsi, [r13+r12*8+0]\nmov rdx, rbp\nlea rdi, [r14+rax]\ncall ___stpcpy_chk\nmov rcx, r14\nmov edx, 2\nlea rsi, delim; \" \"\nsub rcx, rax\nmov rdi, rax\nadd rcx, rbp\ncall ___memcpy_chk\nlea rax, [r12+1]\ncmp r15d, eax\njg short loc_1530\nadd r12d, 1\ncmp r12d, ebx\njl loc_1459\njmp loc_1479\nloc_1530:\nmov r12, rax\njmp short loc_14DA\nloc_1535:\nxor edi, edi; size\ncall _malloc\nmov r14, rax\ntest rax, rax\njz short loc_1551\nmov byte ptr [rax], 0\njmp loc_1479\nloc_154C:\ncall ___stack_chk_fail\nloc_1551:\nmov rdi, [rsp+378h+ptr]; ptr\ncall _free\nloc_155B:\nxor r14d, r14d\njmp loc_1483", + "ida_strip_pseudo": "const char *__fastcall sub_1350(const char *a1)\n{\n char *v1; // rax\n int v2; // ebx\n char *v3; // rbp\n const char **v4; // r15\n int v5; // ebp\n const char **v6; // r12\n const char *v7; // rdi\n const char *v8; // rax\n const char *v9; // r14\n __int64 i; // r12\n __int64 v11; // rsi\n size_t v13; // rax\n __int64 v14; // rax\n const char *v15; // rax\n char *ptr; // [rsp+8h] [rbp-370h]\n _QWORD v17[109]; // [rsp+10h] [rbp-368h] BYREF\n\n v17[101] = __readfsqword(0x28u);\n v1 = strdup(a1);\n ptr = v1;\n if ( !v1 )\n return 0LL;\n v2 = 0;\n v3 = strtok(v1, \" \");\n if ( v3 )\n {\n while ( v2 <= 0 )\n {\nLABEL_17:\n v17[v2++] = v3;\n v3 = strtok(0LL, \" \");\n if ( !v3 )\n goto LABEL_8;\n }\n do\n {\n v4 = (const char **)v17;\n while ( strcmp(v3, *v4) )\n {\n if ( ++v4 == &v17[v2] )\n goto LABEL_17;\n }\n v3 = strtok(0LL, \" \");\n }\n while ( v3 );\nLABEL_8:\n if ( v2 > 0 )\n {\n v5 = 0;\n v6 = (const char **)v17;\n do\n {\n v7 = *v6++;\n v5 += strlen(v7) + 1;\n }\n while ( v6 != &v17[v2] );\n v8 = (const char *)malloc(v5);\n v9 = v8;\n if ( v8 )\n {\n *v8 = 0;\n LODWORD(i) = 0;\n if ( v2 - 1 <= 0 )\n goto LABEL_13;\n for ( i = 0LL; ; ++i )\n {\n v13 = strlen(v9);\n v14 = __stpcpy_chk(&v9[v13], v17[i], v5);\n __memcpy_chk(v14, \" \", 2LL, &v9[v5 - v14]);\n if ( v2 - 1 <= (int)i + 1 )\n break;\n }\n LODWORD(i) = i + 1;\n if ( (int)i < v2 )\n {\nLABEL_13:\n i = (int)i;\n do\n {\n v11 = v17[i++];\n __strcat_chk(v9, v11, v5);\n }\n while ( v2 > (int)i );\n }\n goto LABEL_15;\n }\n goto LABEL_26;\n }\n }\n v15 = (const char *)malloc(0LL);\n v9 = v15;\n if ( !v15 )\n {\nLABEL_26:\n free(ptr);\n return 0LL;\n }\n *v15 = 0;\nLABEL_15:\n free(ptr);\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1350(const char *a1) {\n char *v1;\n int v2;\n char *v3;\n const char **v4;\n int v5;\n const char **v6;\n const char *v7;\n const char *v8;\n const char *v9;\n long long i;\n long long v11;\n unsigned int v13;\n long long v14;\n const char *v15;\n char *ptr;\n uint64_t v17[109];\n v17[101] = __readfsqword(40u);\n v1 = strdup(a1);\n ptr = v1;\n if (!v1) return 0LL;\n v2 = 0;\n v3 = strtok(v1, \" \");\n if (v3) {\n while (v2 <= 0) {\n LABEL_17:\n v17[v2++] = v3;\n v3 = strtok(0LL, \" \");\n if (!v3) goto LABEL_8;\n }\n do {\n v4 = (const char **)v17;\n while (strcmp(v3, *v4)) {\n if (++v4 == &v17[v2]) goto LABEL_17;\n }\n v3 = strtok(0LL, \" \");\n } while (v3);\n LABEL_8:\n if (v2 > 0) {\n v5 = 0;\n v6 = (const char **)v17;\n do {\n v7 = *v6++;\n v5 += strlen(v7) + 1;\n } while (v6 != &v17[v2]);\n v8 = (const char *)malloc(v5);\n v9 = v8;\n if (v8) {\n *v8 = 0;\n LODWORD(i) = 0;\n if (v2 - 1 <= 0) goto LABEL_13;\n for (i = 0LL;; ++i) {\n v13 = strlen(v9);\n v14 = __stpcpy_chk(&v9[v13], v17[i], v5);\n __memcpy_chk(v14, \" \", 2LL, &v9[v5 - v14]);\n if (v2 - 1 <= (int)i + 1) break;\n }\n LODWORD(i) = i + 1;\n if ((int)i < v2) {\n LABEL_13:\n i = (int)i;\n do {\n v11 = v17[i++];\n __strcat_chk(v9, v11, v5);\n } while (v2 > (int)i);\n }\n goto LABEL_15;\n }\n goto LABEL_26;\n }\n }\n v15 = (const char *)malloc(0LL);\n v9 = v15;\n if (!v15) {\n LABEL_26:\n free(ptr);\n return 0LL;\n }\n *v15 = 0;\nLABEL_15:\n free(ptr);\n return v9;\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n char *v1;\n int v2;\n char *v3;\n const char **v4;\n int v5;\n const char **v6;\n const char *v7;\n const char *v8;\n const char *v9;\n long long i;\n long long v11;\n unsigned int v13;\n long long v14;\n const char *v15;\n char *ptr;\n uint64_t v17[109];\n v17[101] = __readfsqword(40u);\n v1 = strdup(a1);\n ptr = v1;\n if (!v1) return 0LL;\n v2 = 0;\n v3 = strtok(v1, \" \");\n if (v3) {\n while (v2 <= 0) {\n LABEL_17:\n v17[v2++] = v3;\n v3 = strtok(0LL, \" \");\n if (!v3) goto LABEL_8;\n }\n do {\n v4 = (const char **)v17;\n while (strcmp(v3, *v4)) {\n if (++v4 == &v17[v2]) goto LABEL_17;\n }\n v3 = strtok(0LL, \" \");\n } while (v3);\n LABEL_8:\n if (v2 > 0) {\n v5 = 0;\n v6 = (const char **)v17;\n do {\n v7 = *v6++;\n v5 += strlen(v7) + 1;\n } while (v6 != &v17[v2]);\n v8 = (const char *)malloc(v5);\n v9 = v8;\n if (v8) {\n *v8 = 0;\n LODWORD(i) = 0;\n if (v2 - 1 <= 0) goto LABEL_13;\n for (i = 0LL;; ++i) {\n v13 = strlen(v9);\n v14 = __stpcpy_chk(&v9[v13], v17[i], v5);\n __memcpy_chk(v14, \" \", 2LL, &v9[v5 - v14]);\n if (v2 - 1 <= (int)i + 1) break;\n }\n LODWORD(i) = i + 1;\n if ((int)i < v2) {\n LABEL_13:\n i = (int)i;\n do {\n v11 = v17[i++];\n __strcat_chk(v9, v11, v5);\n } while (v2 > (int)i);\n }\n goto LABEL_15;\n }\n goto LABEL_26;\n }\n }\n v15 = (const char *)malloc(0LL);\n v9 = v15;\n if (!v15) {\n LABEL_26:\n free(ptr);\n return 0LL;\n }\n *v15 = 0;\nLABEL_15:\n free(ptr);\n return v9;\n}" + }, + { + "index": 675, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int x, int y, int m, int n) {\n int sum_nums = x + y;\n if (sum_nums >= m && sum_nums <= n) {\n return 20;\n } else {\n return sum_nums;\n }\n}", + "test": "int main() {\n\n assert(func0(2, 10, 11, 20) == 20);\n\n assert(func0(15, 17, 1, 10) == 32);\n\n assert(func0(10, 15, 5, 30) == 20);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov %edx,-0x1c(%rbp)\nmov %ecx,-0x20(%rbp)\nmov -0x14(%rbp),%edx\nmov -0x18(%rbp),%eax\nadd %edx,%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 117f \nmov -0x4(%rbp),%eax\ncmp -0x20(%rbp),%eax\njg 117f \nmov $0x14,%eax\njmp 1182 \nmov -0x4(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov [rbp+var_20], ecx\nmov edx, [rbp+var_14]\nmov eax, [rbp+var_18]\nadd eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_117F\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_20]\njg short loc_117F\nmov eax, 14h\njmp short loc_1182\nloc_117F:\nmov eax, [rbp+var_4]\nloc_1182:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, int a3, int a4)\n{\n unsigned int v5; // [rsp+1Ch] [rbp-4h]\n\n v5 = a1 + a2;\n if ( a1 + a2 < a3 || (int)v5 > a4 )\n return v5;\n else\n return 20LL;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov [rbp+var_20], ecx\nmov edx, [rbp+var_14]\nmov eax, [rbp+var_18]\nadd eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_117F\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_20]\njg short loc_117F\nmov eax, 14h\njmp short loc_1182\nloc_117F:\nmov eax, [rbp+var_4]\nloc_1182:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2, int a3, int a4)\n{\n unsigned int v5; // [rsp+1Ch] [rbp-4h]\n\n v5 = a1 + a2;\n if ( a1 + a2 < a3 || (int)v5 > a4 )\n return v5;\n else\n return 20LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2, int a3, int a4) {\n unsigned int v5;\n v5 = a1 + a2;\n if (a1 + a2 < a3 || (int)v5 > a4)\n return v5;\n else\n return 20LL;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, int a3, int a4) {\n unsigned int v5;\n v5 = a1 + a2;\n if (a1 + a2 < a3 || (int)v5 > a4)\n return v5;\n else\n return 20LL;\n}" + }, + { + "index": 676, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text1) {\n size_t len = strlen(text1);\n char* result = (char*)malloc(len + 1);\n if (!result) return NULL;\n size_t j = 0;\n for (size_t i = 0; i < len; ++i) {\n if (isalnum((unsigned char)text1[i])) {\n result[j++] = text1[i];\n }\n }\n result[j] = '\\0';\n return result;\n}", + "test": "int main() {\n\n char* res1 = func0(\"**//Google Android// - 12. \");\n\n assert(res1 != NULL);\n\n assert(strcmp(res1, \"GoogleAndroid12\") == 0);\n\n free(res1);\n\n \n\n char* res2 = func0(\"****//Google Flutter//*** - 36. \");\n\n assert(res2 != NULL);\n\n assert(strcmp(res2, \"GoogleFlutter36\") == 0);\n\n free(res2);\n\n \n\n char* res3 = func0(\"**//Google Firebase// - 478. \");\n\n assert(res3 != NULL);\n\n assert(strcmp(res3, \"GoogleFirebase478\") == 0);\n\n free(res3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x28(%rbp)\nmov -0x28(%rbp),%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x10(%rbp)\nmov -0x10(%rbp),%rax\nadd $0x1,%rax\nmov %rax,%rdi\ncallq 10e0 \nmov %rax,-0x8(%rbp)\ncmpq $0x0,-0x8(%rbp)\njne 122e \nmov $0x0,%eax\njmpq 12b1 \nmovq $0x0,-0x20(%rbp)\nmovq $0x0,-0x18(%rbp)\njmp 1295 \ncallq 10f0 <__ctype_b_loc@plt>\nmov (%rax),%rax\nmov -0x28(%rbp),%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rdx),%edx\nmovzbl %dl,%edx\nadd %rdx,%rdx\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x8,%eax\ntest %eax,%eax\nje 1290 \nmov -0x28(%rbp),%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x20(%rbp),%rax\nlea 0x1(%rax),%rdx\nmov %rdx,-0x20(%rbp)\nmov -0x8(%rbp),%rdx\nadd %rax,%rdx\nmovzbl (%rcx),%eax\nmov %al,(%rdx)\naddq $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%rax\ncmp -0x10(%rbp),%rax\njb 1240 \nmov -0x8(%rbp),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmovb $0x0,(%rax)\nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_10], rax\nmov rax, [rbp+var_10]\nadd rax, 1\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\ncmp [rbp+var_8], 0\njnz short loc_122E\nmov eax, 0\njmp locret_12B1\nloc_122E:\nmov [rbp+var_20], 0\nmov [rbp+var_18], 0\njmp short loc_1295\nloc_1240:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov rcx, [rbp+s]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovzx edx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 8\ntest eax, eax\njz short loc_1290\nmov rdx, [rbp+s]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov rax, [rbp+var_20]\nlea rdx, [rax+1]\nmov [rbp+var_20], rdx\nmov rdx, [rbp+var_8]\nadd rdx, rax\nmovzx eax, byte ptr [rcx]\nmov [rdx], al\nloc_1290:\nadd [rbp+var_18], 1\nloc_1295:\nmov rax, [rbp+var_18]\ncmp rax, [rbp+var_10]\njb short loc_1240\nmov rdx, [rbp+var_8]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+var_8]\nlocret_12B1:\nleave\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1)\n{\n __int64 v2; // rax\n __int64 v3; // [rsp+10h] [rbp-20h]\n size_t i; // [rsp+18h] [rbp-18h]\n size_t v5; // [rsp+20h] [rbp-10h]\n _BYTE *v6; // [rsp+28h] [rbp-8h]\n\n v5 = strlen(a1);\n v6 = malloc(v5 + 1);\n if ( !v6 )\n return 0LL;\n v3 = 0LL;\n for ( i = 0LL; i < v5; ++i )\n {\n if ( ((*__ctype_b_loc())[(unsigned __int8)a1[i]] & 8) != 0 )\n {\n v2 = v3++;\n v6[v2] = a1[i];\n }\n }\n v6[v3] = 0;\n return v6;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_10], rax\nmov rax, [rbp+var_10]\nadd rax, 1\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\ncmp [rbp+var_8], 0\njnz short loc_122E\nmov eax, 0\njmp locret_12B1\nloc_122E:\nmov [rbp+var_20], 0\nmov [rbp+var_18], 0\njmp short loc_1295\nloc_1240:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov rcx, [rbp+s]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovzx edx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 8\ntest eax, eax\njz short loc_1290\nmov rdx, [rbp+s]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov rax, [rbp+var_20]\nlea rdx, [rax+1]\nmov [rbp+var_20], rdx\nmov rdx, [rbp+var_8]\nadd rdx, rax\nmovzx eax, byte ptr [rcx]\nmov [rdx], al\nloc_1290:\nadd [rbp+var_18], 1\nloc_1295:\nmov rax, [rbp+var_18]\ncmp rax, [rbp+var_10]\njb short loc_1240\nmov rdx, [rbp+var_8]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+var_8]\nlocret_12B1:\nleave\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_11E9(const char *a1)\n{\n __int64 v2; // rax\n __int64 v3; // [rsp+10h] [rbp-20h]\n size_t i; // [rsp+18h] [rbp-18h]\n size_t v5; // [rsp+20h] [rbp-10h]\n _BYTE *v6; // [rsp+28h] [rbp-8h]\n\n v5 = strlen(a1);\n v6 = malloc(v5 + 1);\n if ( !v6 )\n return 0LL;\n v3 = 0LL;\n for ( i = 0LL; i < v5; ++i )\n {\n if ( ((*__ctype_b_loc())[(unsigned __int8)a1[i]] & 8) != 0 )\n {\n v2 = v3++;\n v6[v2] = a1[i];\n }\n }\n v6[v3] = 0;\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_11E9(const char *a1) {\n long long v2;\n long long v3;\n unsigned int i;\n unsigned int v5;\n uint8_t *v6;\n v5 = strlen(a1);\n v6 = malloc(v5 + 1);\n if (!v6) return 0LL;\n v3 = 0LL;\n for (i = 0LL; i < v5; ++i) {\n if (((*__ctype_b_loc())[(unsigned char)a1[i]] & 8) != 0) {\n v2 = v3++;\n v6[v2] = a1[i];\n }\n }\n v6[v3] = 0;\n return v6;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1) {\n long long v2;\n long long v3;\n unsigned int i;\n unsigned int v5;\n uint8_t *v6;\n v5 = strlen(a1);\n v6 = malloc(v5 + 1);\n if (!v6) return 0LL;\n v3 = 0LL;\n for (i = 0LL; i < v5; ++i) {\n if (((*__ctype_b_loc())[(unsigned char)a1[i]] & 8) != 0) {\n v2 = v3++;\n v6[v2] = a1[i];\n }\n }\n v6[v3] = 0;\n return v6;\n}" + }, + { + "index": 676, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text1) {\n size_t len = strlen(text1);\n char* result = (char*)malloc(len + 1);\n if (!result) return NULL;\n size_t j = 0;\n for (size_t i = 0; i < len; ++i) {\n if (isalnum((unsigned char)text1[i])) {\n result[j++] = text1[i];\n }\n }\n result[j] = '\\0';\n return result;\n}", + "test": "int main() {\n\n char* res1 = func0(\"**//Google Android// - 12. \");\n\n assert(res1 != NULL);\n\n assert(strcmp(res1, \"GoogleAndroid12\") == 0);\n\n free(res1);\n\n \n\n char* res2 = func0(\"****//Google Flutter//*** - 36. \");\n\n assert(res2 != NULL);\n\n assert(strcmp(res2, \"GoogleFlutter36\") == 0);\n\n free(res2);\n\n \n\n char* res3 = func0(\"**//Google Firebase// - 478. \");\n\n assert(res3 != NULL);\n\n assert(strcmp(res3, \"GoogleFirebase478\") == 0);\n\n free(res3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%r12\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rdi\nnot %rdi\nlea -0x1(%rdi),%rbx\ncallq 10a0 \nmov %rax,%rbp\ntest %rax,%rax\nje 1218 \ntest %rbx,%rbx\nje 1213 \ncallq 10b0 <__ctype_b_loc@plt>\nmov (%rax),%rsi\nmov %r12,%rax\nlea (%r12,%rbx,1),%rdi\nmov $0x0,%ebx\njmp 11fd \nadd $0x1,%rax\ncmp %rdi,%rax\nje 1213 \nmovzbl (%rax),%edx\nmovzbl %dl,%ecx\ntestb $0x8,(%rsi,%rcx,2)\nje 11f4 \nmov %dl,0x0(%rbp,%rbx,1)\nlea 0x1(%rbx),%rbx\njmp 11f4 \nmovb $0x0,0x0(%rbp,%rbx,1)\nmov %rbp,%rax\npop %rbx\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12, rdi\ncall _strlen\nmov r13, rax\nmov rbx, rax\nlea rdi, [rax+1]; size\ncall _malloc\nmov rbp, rax\ntest rax, rax\njz short loc_1255\ntest r13, r13\njz short loc_1250\ncall ___ctype_b_loc\nmov rdi, [rax]\nmov rax, r12\nlea rsi, [r12+r13]\nmov ebx, 0\njmp short loc_123A\nloc_1231:\nadd rax, 1\ncmp rax, rsi\njz short loc_1250\nloc_123A:\nmovzx edx, byte ptr [rax]\nmovzx ecx, dl\ntest byte ptr [rdi+rcx*2], 8\njz short loc_1231\nmov [rbp+rbx+0], dl\nlea rbx, [rbx+1]\njmp short loc_1231\nloc_1250:\nmov byte ptr [rbp+rbx+0], 0\nloc_1255:\nmov rax, rbp\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1)\n{\n size_t v2; // r13\n size_t v3; // rbx\n _BYTE *v4; // rbp\n const unsigned __int16 *v5; // rdi\n const char *v6; // rax\n\n v2 = strlen(a1);\n v3 = v2;\n v4 = malloc(v2 + 1);\n if ( v4 )\n {\n if ( v2 )\n {\n v5 = *__ctype_b_loc();\n v6 = a1;\n v3 = 0LL;\n do\n {\n if ( (v5[*(unsigned __int8 *)v6] & 8) != 0 )\n v4[v3++] = *v6;\n ++v6;\n }\n while ( v6 != &a1[v2] );\n }\n v4[v3] = 0;\n }\n return v4;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12, rdi\ncall _strlen\nmov r13, rax\nmov rbx, rax\nlea rdi, [rax+1]; size\ncall _malloc\nmov rbp, rax\ntest rax, rax\njz short loc_1255\ntest r13, r13\njz short loc_1250\ncall ___ctype_b_loc\nmov rdi, [rax]\nmov rax, r12\nlea rsi, [r12+r13]\nmov ebx, 0\njmp short loc_123A\nloc_1231:\nadd rax, 1\ncmp rax, rsi\njz short loc_1250\nloc_123A:\nmovzx edx, byte ptr [rax]\nmovzx ecx, dl\ntest byte ptr [rdi+rcx*2], 8\njz short loc_1231\nmov [rbp+rbx+0], dl\nlea rbx, [rbx+1]\njmp short loc_1231\nloc_1250:\nmov byte ptr [rbp+rbx+0], 0\nloc_1255:\nmov rax, rbp\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_11E9(const char *a1)\n{\n size_t v2; // r13\n size_t v3; // rbx\n _BYTE *v4; // rbp\n const unsigned __int16 *v5; // rdi\n const char *v6; // rax\n\n v2 = strlen(a1);\n v3 = v2;\n v4 = malloc(v2 + 1);\n if ( v4 )\n {\n if ( v2 )\n {\n v5 = *__ctype_b_loc();\n v6 = a1;\n v3 = 0LL;\n do\n {\n if ( (v5[*(unsigned __int8 *)v6] & 8) != 0 )\n v4[v3++] = *v6;\n ++v6;\n }\n while ( v6 != &a1[v2] );\n }\n v4[v3] = 0;\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_11E9(const char *a1) {\n unsigned int v2;\n unsigned int v3;\n uint8_t *v4;\n const unsigned short *v5;\n const char *v6;\n v2 = strlen(a1);\n v3 = v2;\n v4 = malloc(v2 + 1);\n if (v4) {\n if (v2) {\n v5 = *__ctype_b_loc();\n v6 = a1;\n v3 = 0LL;\n do {\n if ((v5[*(unsigned char *)v6] & 8) != 0) v4[v3++] = *v6;\n ++v6;\n } while (v6 != &a1[v2]);\n }\n v4[v3] = 0;\n }\n return v4;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1) {\n unsigned int v2;\n unsigned int v3;\n uint8_t *v4;\n const unsigned short *v5;\n const char *v6;\n v2 = strlen(a1);\n v3 = v2;\n v4 = malloc(v2 + 1);\n if (v4) {\n if (v2) {\n v5 = *__ctype_b_loc();\n v6 = a1;\n v3 = 0LL;\n do {\n if ((v5[*(unsigned char *)v6] & 8) != 0) v4[v3++] = *v6;\n ++v6;\n } while (v6 != &a1[v2]);\n }\n v4[v3] = 0;\n }\n return v4;\n}" + }, + { + "index": 676, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text1) {\n size_t len = strlen(text1);\n char* result = (char*)malloc(len + 1);\n if (!result) return NULL;\n size_t j = 0;\n for (size_t i = 0; i < len; ++i) {\n if (isalnum((unsigned char)text1[i])) {\n result[j++] = text1[i];\n }\n }\n result[j] = '\\0';\n return result;\n}", + "test": "int main() {\n\n char* res1 = func0(\"**//Google Android// - 12. \");\n\n assert(res1 != NULL);\n\n assert(strcmp(res1, \"GoogleAndroid12\") == 0);\n\n free(res1);\n\n \n\n char* res2 = func0(\"****//Google Flutter//*** - 36. \");\n\n assert(res2 != NULL);\n\n assert(strcmp(res2, \"GoogleFlutter36\") == 0);\n\n free(res2);\n\n \n\n char* res3 = func0(\"**//Google Firebase// - 478. \");\n\n assert(res3 != NULL);\n\n assert(strcmp(res3, \"GoogleFirebase478\") == 0);\n\n free(res3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\ncallq 10a0 \nlea 0x1(%rax),%rdi\nmov %rax,%rbp\ncallq 10c0 \nmov %rax,%r12\ntest %rax,%rax\nje 13b6 \ntest %rbp,%rbp\nje 13c0 \ncallq 10d0 <__ctype_b_loc@plt>\nmov %rbx,%rdi\nlea (%rbx,%rbp,1),%r9\nxor %r8d,%r8d\nmov (%rax),%r10\nmov %r12,%rax\nxchg %ax,%ax\nmovzbl (%rdi),%ecx\nmov %rax,%rsi\ntestb $0x8,(%r10,%rcx,2)\nje 13aa \nadd $0x1,%r8\nmov %cl,(%rax)\nlea (%r12,%r8,1),%rax\nmov %rax,%rsi\nadd $0x1,%rdi\ncmp %rdi,%r9\njne 1390 \nmovb $0x0,(%rsi)\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\nretq\nxchg %ax,%ax\nmov %rax,%rsi\njmp 13b3 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbx, rdi\ncall _strlen\nlea rdi, [rax+1]; size\nmov rbp, rax\ncall _malloc\nmov r12, rax\ntest rax, rax\njz short loc_13B1\ntest rbp, rbp\njz short loc_13C0\ncall ___ctype_b_loc\nlea rdi, [rbx+rbp]\nxor esi, esi\nmov r8, [rax]\nmov rax, rbx\nnop word ptr [rax+rax+00h]\nloc_1390:\nmovzx ecx, byte ptr [rax]\ntest byte ptr [r8+rcx*2], 8\njz short loc_13A2\nmov [r12+rsi], cl\nadd rsi, 1\nloc_13A2:\nadd rax, 1\ncmp rdi, rax\njnz short loc_1390\nadd rsi, r12\nloc_13AE:\nmov byte ptr [rsi], 0\nloc_13B1:\nmov rax, r12\npop rbx\npop rbp\npop r12\nretn\nloc_13C0:\nmov rsi, rax\njmp short loc_13AE", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1)\n{\n size_t v2; // rbp\n _BYTE *v3; // rax\n _BYTE *v4; // r12\n unsigned __int8 *v5; // rdi\n __int64 v6; // rsi\n const unsigned __int16 *v7; // r8\n const char *v8; // rax\n __int64 v9; // rcx\n _BYTE *v10; // rsi\n\n v2 = strlen(a1);\n v3 = malloc(v2 + 1);\n v4 = v3;\n if ( v3 )\n {\n if ( v2 )\n {\n v5 = (unsigned __int8 *)&a1[v2];\n v6 = 0LL;\n v7 = *__ctype_b_loc();\n v8 = a1;\n do\n {\n v9 = *(unsigned __int8 *)v8;\n if ( (v7[v9] & 8) != 0 )\n v4[v6++] = v9;\n ++v8;\n }\n while ( v5 != (unsigned __int8 *)v8 );\n v10 = &v4[v6];\n }\n else\n {\n v10 = v3;\n }\n *v10 = 0;\n }\n return v4;\n}", + "ida_strip_asm": "sub_1350:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbx, rdi\ncall _strlen\nlea rdi, [rax+1]; size\nmov rbp, rax\ncall _malloc\nmov r12, rax\ntest rax, rax\njz short loc_13B1\ntest rbp, rbp\njz short loc_13C0\ncall ___ctype_b_loc\nlea rdi, [rbx+rbp]\nxor esi, esi\nmov r8, [rax]\nmov rax, rbx\nnop word ptr [rax+rax+00h]\nloc_1390:\nmovzx ecx, byte ptr [rax]\ntest byte ptr [r8+rcx*2], 8\njz short loc_13A2\nmov [r12+rsi], cl\nadd rsi, 1\nloc_13A2:\nadd rax, 1\ncmp rdi, rax\njnz short loc_1390\nadd rsi, r12\nloc_13AE:\nmov byte ptr [rsi], 0\nloc_13B1:\nmov rax, r12\npop rbx\npop rbp\npop r12\nretn\nloc_13C0:\nmov rsi, rax\njmp short loc_13AE", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1350(const char *a1)\n{\n size_t v2; // rbp\n _BYTE *v3; // rax\n _BYTE *v4; // r12\n unsigned __int8 *v5; // rdi\n __int64 v6; // rsi\n const unsigned __int16 *v7; // r8\n const char *v8; // rax\n __int64 v9; // rcx\n _BYTE *v10; // rsi\n\n v2 = strlen(a1);\n v3 = malloc(v2 + 1);\n v4 = v3;\n if ( v3 )\n {\n if ( v2 )\n {\n v5 = (unsigned __int8 *)&a1[v2];\n v6 = 0LL;\n v7 = *__ctype_b_loc();\n v8 = a1;\n do\n {\n v9 = *(unsigned __int8 *)v8;\n if ( (v7[v9] & 8) != 0 )\n v4[v6++] = v9;\n ++v8;\n }\n while ( v5 != (unsigned __int8 *)v8 );\n v10 = &v4[v6];\n }\n else\n {\n v10 = v3;\n }\n *v10 = 0;\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1350(const char *a1) {\n unsigned int v2;\n uint8_t *v3;\n uint8_t *v4;\n unsigned char *v5;\n long long v6;\n const unsigned short *v7;\n const char *v8;\n long long v9;\n uint8_t *v10;\n v2 = strlen(a1);\n v3 = malloc(v2 + 1);\n v4 = v3;\n if (v3) {\n if (v2) {\n v5 = (unsigned char *)&a1[v2];\n v6 = 0LL;\n v7 = *__ctype_b_loc();\n v8 = a1;\n do {\n v9 = *(unsigned char *)v8;\n if ((v7[v9] & 8) != 0) v4[v6++] = v9;\n ++v8;\n } while (v5 != (unsigned char *)v8);\n v10 = &v4[v6];\n } else {\n v10 = v3;\n }\n *v10 = 0;\n }\n return v4;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1) {\n unsigned int v2;\n uint8_t *v3;\n uint8_t *v4;\n unsigned char *v5;\n long long v6;\n const unsigned short *v7;\n const char *v8;\n long long v9;\n uint8_t *v10;\n v2 = strlen(a1);\n v3 = malloc(v2 + 1);\n v4 = v3;\n if (v3) {\n if (v2) {\n v5 = (unsigned char *)&a1[v2];\n v6 = 0LL;\n v7 = *__ctype_b_loc();\n v8 = a1;\n do {\n v9 = *(unsigned char *)v8;\n if ((v7[v9] & 8) != 0) v4[v6++] = v9;\n ++v8;\n } while (v5 != (unsigned char *)v8);\n v10 = &v4[v6];\n } else {\n v10 = v3;\n }\n *v10 = 0;\n }\n return v4;\n}" + }, + { + "index": 676, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text1) {\n size_t len = strlen(text1);\n char* result = (char*)malloc(len + 1);\n if (!result) return NULL;\n size_t j = 0;\n for (size_t i = 0; i < len; ++i) {\n if (isalnum((unsigned char)text1[i])) {\n result[j++] = text1[i];\n }\n }\n result[j] = '\\0';\n return result;\n}", + "test": "int main() {\n\n char* res1 = func0(\"**//Google Android// - 12. \");\n\n assert(res1 != NULL);\n\n assert(strcmp(res1, \"GoogleAndroid12\") == 0);\n\n free(res1);\n\n \n\n char* res2 = func0(\"****//Google Flutter//*** - 36. \");\n\n assert(res2 != NULL);\n\n assert(strcmp(res2, \"GoogleFlutter36\") == 0);\n\n free(res2);\n\n \n\n char* res3 = func0(\"**//Google Firebase// - 478. \");\n\n assert(res3 != NULL);\n\n assert(strcmp(res3, \"GoogleFirebase478\") == 0);\n\n free(res3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\ncallq 10a0 \nlea 0x1(%rax),%rdi\nmov %rax,%rbp\ncallq 10c0 \nmov %rax,%r12\ntest %rax,%rax\nje 13b6 \ntest %rbp,%rbp\nje 13c0 \ncallq 10d0 <__ctype_b_loc@plt>\nmov %rbx,%rdi\nlea (%rbx,%rbp,1),%r9\nxor %r8d,%r8d\nmov (%rax),%r10\nmov %r12,%rax\nxchg %ax,%ax\nmovzbl (%rdi),%ecx\nmov %rax,%rsi\ntestb $0x8,(%r10,%rcx,2)\nje 13aa \nadd $0x1,%r8\nmov %cl,(%rax)\nlea (%r12,%r8,1),%rax\nmov %rax,%rsi\nadd $0x1,%rdi\ncmp %rdi,%r9\njne 1390 \nmovb $0x0,(%rsi)\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\nretq\nxchg %ax,%ax\nmov %rax,%rsi\njmp 13b3 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbx, rdi\ncall _strlen\nlea rdi, [rax+1]; size\nmov rbp, rax\ncall _malloc\nmov r12, rax\ntest rax, rax\njz short loc_13B1\ntest rbp, rbp\njz short loc_13C0\ncall ___ctype_b_loc\nlea rdi, [rbx+rbp]\nxor esi, esi\nmov r8, [rax]\nmov rax, rbx\nnop word ptr [rax+rax+00h]\nloc_1390:\nmovzx ecx, byte ptr [rax]\ntest byte ptr [r8+rcx*2], 8\njz short loc_13A2\nmov [r12+rsi], cl\nadd rsi, 1\nloc_13A2:\nadd rax, 1\ncmp rdi, rax\njnz short loc_1390\nadd rsi, r12\nloc_13AE:\nmov byte ptr [rsi], 0\nloc_13B1:\nmov rax, r12\npop rbx\npop rbp\npop r12\nretn\nloc_13C0:\nmov rsi, rax\njmp short loc_13AE", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1)\n{\n size_t v2; // rbp\n _BYTE *v3; // rax\n _BYTE *v4; // r12\n unsigned __int8 *v5; // rdi\n __int64 v6; // rsi\n const unsigned __int16 *v7; // r8\n const char *v8; // rax\n __int64 v9; // rcx\n _BYTE *v10; // rsi\n\n v2 = strlen(a1);\n v3 = malloc(v2 + 1);\n v4 = v3;\n if ( v3 )\n {\n if ( v2 )\n {\n v5 = (unsigned __int8 *)&a1[v2];\n v6 = 0LL;\n v7 = *__ctype_b_loc();\n v8 = a1;\n do\n {\n v9 = *(unsigned __int8 *)v8;\n if ( (v7[v9] & 8) != 0 )\n v4[v6++] = v9;\n ++v8;\n }\n while ( v5 != (unsigned __int8 *)v8 );\n v10 = &v4[v6];\n }\n else\n {\n v10 = v3;\n }\n *v10 = 0;\n }\n return v4;\n}", + "ida_strip_asm": "sub_1350:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbx, rdi\ncall _strlen\nlea rdi, [rax+1]; size\nmov rbp, rax\ncall _malloc\nmov r12, rax\ntest rax, rax\njz short loc_13B1\ntest rbp, rbp\njz short loc_13C0\ncall ___ctype_b_loc\nlea rdi, [rbx+rbp]\nxor esi, esi\nmov r8, [rax]\nmov rax, rbx\nnop word ptr [rax+rax+00h]\nloc_1390:\nmovzx ecx, byte ptr [rax]\ntest byte ptr [r8+rcx*2], 8\njz short loc_13A2\nmov [r12+rsi], cl\nadd rsi, 1\nloc_13A2:\nadd rax, 1\ncmp rdi, rax\njnz short loc_1390\nadd rsi, r12\nloc_13AE:\nmov byte ptr [rsi], 0\nloc_13B1:\nmov rax, r12\npop rbx\npop rbp\npop r12\nretn\nloc_13C0:\nmov rsi, rax\njmp short loc_13AE", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1350(const char *a1)\n{\n size_t v2; // rbp\n _BYTE *v3; // rax\n _BYTE *v4; // r12\n unsigned __int8 *v5; // rdi\n __int64 v6; // rsi\n const unsigned __int16 *v7; // r8\n const char *v8; // rax\n __int64 v9; // rcx\n _BYTE *v10; // rsi\n\n v2 = strlen(a1);\n v3 = malloc(v2 + 1);\n v4 = v3;\n if ( v3 )\n {\n if ( v2 )\n {\n v5 = (unsigned __int8 *)&a1[v2];\n v6 = 0LL;\n v7 = *__ctype_b_loc();\n v8 = a1;\n do\n {\n v9 = *(unsigned __int8 *)v8;\n if ( (v7[v9] & 8) != 0 )\n v4[v6++] = v9;\n ++v8;\n }\n while ( v5 != (unsigned __int8 *)v8 );\n v10 = &v4[v6];\n }\n else\n {\n v10 = v3;\n }\n *v10 = 0;\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1350(const char *a1) {\n unsigned int v2;\n uint8_t *v3;\n uint8_t *v4;\n unsigned char *v5;\n long long v6;\n const unsigned short *v7;\n const char *v8;\n long long v9;\n uint8_t *v10;\n v2 = strlen(a1);\n v3 = malloc(v2 + 1);\n v4 = v3;\n if (v3) {\n if (v2) {\n v5 = (unsigned char *)&a1[v2];\n v6 = 0LL;\n v7 = *__ctype_b_loc();\n v8 = a1;\n do {\n v9 = *(unsigned char *)v8;\n if ((v7[v9] & 8) != 0) v4[v6++] = v9;\n ++v8;\n } while (v5 != (unsigned char *)v8);\n v10 = &v4[v6];\n } else {\n v10 = v3;\n }\n *v10 = 0;\n }\n return v4;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1) {\n unsigned int v2;\n uint8_t *v3;\n uint8_t *v4;\n unsigned char *v5;\n long long v6;\n const unsigned short *v7;\n const char *v8;\n long long v9;\n uint8_t *v10;\n v2 = strlen(a1);\n v3 = malloc(v2 + 1);\n v4 = v3;\n if (v3) {\n if (v2) {\n v5 = (unsigned char *)&a1[v2];\n v6 = 0LL;\n v7 = *__ctype_b_loc();\n v8 = a1;\n do {\n v9 = *(unsigned char *)v8;\n if ((v7[v9] & 8) != 0) v4[v6++] = v9;\n ++v8;\n } while (v5 != (unsigned char *)v8);\n v10 = &v4[v6];\n } else {\n v10 = v3;\n }\n *v10 = 0;\n }\n return v4;\n}" + }, + { + "index": 677, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "bool func0(int a, int b, int c) {\n int total = a + b + c;\n if (total == 180) {\n return true;\n } else {\n return false;\n }\n}", + "test": "int main() {\n\n assert(func0(60, 50, 90) == false);\n\n assert(func0(45, 75, 60) == true);\n\n assert(func0(30, 50, 100) == true);\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov %edx,-0x1c(%rbp)\nmov -0x14(%rbp),%edx\nmov -0x18(%rbp),%eax\nadd %eax,%edx\nmov -0x1c(%rbp),%eax\nadd %edx,%eax\nmov %eax,-0x4(%rbp)\ncmpl $0xb4,-0x4(%rbp)\njne 117a \nmov $0x1,%eax\njmp 117f \nmov $0x0,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov edx, [rbp+var_14]\nmov eax, [rbp+var_18]\nadd edx, eax\nmov eax, [rbp+var_1C]\nadd eax, edx\nmov [rbp+var_4], eax\ncmp [rbp+var_4], 0B4h\njnz short loc_117A\nmov eax, 1\njmp short loc_117F\nloc_117A:\nmov eax, 0\nloc_117F:\npop rbp\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(int a1, int a2, int a3)\n{\n return a2 + a1 + a3 == 180;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov edx, [rbp+var_14]\nmov eax, [rbp+var_18]\nadd edx, eax\nmov eax, [rbp+var_1C]\nadd eax, edx\nmov [rbp+var_4], eax\ncmp [rbp+var_4], 0B4h\njnz short loc_117A\nmov eax, 1\njmp short loc_117F\nloc_117A:\nmov eax, 0\nloc_117F:\npop rbp\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1149(int a1, int a2, int a3)\n{\n return a2 + a1 + a3 == 180;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1149(int a1, int a2, int a3) { return a2 + a1 + a3 == 180; }", + "ida_pseudo_norm": "uint8_t func0(int a1, int a2, int a3) { return a2 + a1 + a3 == 180; }" + }, + { + "index": 678, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* str1) {\n int i, j = 0;\n int len = strlen(str1);\n for (i = 0; i < len; i++) {\n if (str1[i] != ' ') {\n str1[j++] = str1[i];\n }\n }\n str1[j] = '\\0';\n return str1;\n}", + "test": "int main() {\n\n char str1[100] = \"a b c\";\n\n char str2[100] = \"1 2 3\";\n\n char str3[100] = \" b c\";\n\n\n\n assert(strcmp(func0(str1), \"abc\") == 0);\n\n assert(strcmp(func0(str2), \"123\") == 0);\n\n assert(strcmp(func0(str3), \"bc\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmovl $0x0,-0x8(%rbp)\nmov -0x18(%rbp),%rax\nmov %rax,%rdi\ncallq 1080 \nmov %eax,-0x4(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 1216 \nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x20,%al\nje 1212 \nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x8(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x8(%rbp)\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmovzbl (%rcx),%eax\nmov %al,(%rdx)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x4(%rbp),%eax\njl 11d8 \nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovb $0x0,(%rax)\nmov -0x18(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov [rbp+var_8], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_C], 0\njmp short loc_1216\nloc_11D8:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njz short loc_1212\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_8]\nlea edx, [rax+1]\nmov [rbp+var_8], edx\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rdx, rax\nmovzx eax, byte ptr [rcx]\nmov [rdx], al\nloc_1212:\nadd [rbp+var_C], 1\nloc_1216:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_4]\njl short loc_11D8\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+s]\nleave\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n int v1; // eax\n int i; // [rsp+14h] [rbp-Ch]\n int v4; // [rsp+18h] [rbp-8h]\n int v5; // [rsp+1Ch] [rbp-4h]\n\n v4 = 0;\n v5 = strlen(a1);\n for ( i = 0; i < v5; ++i )\n {\n if ( a1[i] != 32 )\n {\n v1 = v4++;\n a1[v1] = a1[i];\n }\n }\n a1[v4] = 0;\n return a1;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov [rbp+var_8], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_C], 0\njmp short loc_1216\nloc_11D8:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njz short loc_1212\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_8]\nlea edx, [rax+1]\nmov [rbp+var_8], edx\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rdx, rax\nmovzx eax, byte ptr [rcx]\nmov [rdx], al\nloc_1212:\nadd [rbp+var_C], 1\nloc_1216:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_4]\njl short loc_11D8\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+s]\nleave\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_11A9(const char *a1)\n{\n int v1; // eax\n int i; // [rsp+14h] [rbp-Ch]\n int v4; // [rsp+18h] [rbp-8h]\n int v5; // [rsp+1Ch] [rbp-4h]\n\n v4 = 0;\n v5 = strlen(a1);\n for ( i = 0; i < v5; ++i )\n {\n if ( a1[i] != 32 )\n {\n v1 = v4++;\n a1[v1] = a1[i];\n }\n }\n a1[v4] = 0;\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_11A9(const char *a1) {\n int v1;\n int i;\n int v4;\n int v5;\n v4 = 0;\n v5 = strlen(a1);\n for (i = 0; i < v5; ++i) {\n if (a1[i] != 32) {\n v1 = v4++;\n a1[v1] = a1[i];\n }\n }\n a1[v4] = 0;\n return a1;\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n int v1;\n int i;\n int v4;\n int v5;\n v4 = 0;\n v5 = strlen(a1);\n for (i = 0; i < v5; ++i) {\n if (a1[i] != 32) {\n v1 = v4++;\n a1[v1] = a1[i];\n }\n }\n a1[v4] = 0;\n return a1;\n}" + }, + { + "index": 678, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* str1) {\n int i, j = 0;\n int len = strlen(str1);\n for (i = 0; i < len; i++) {\n if (str1[i] != ' ') {\n str1[j++] = str1[i];\n }\n }\n str1[j] = '\\0';\n return str1;\n}", + "test": "int main() {\n\n char str1[100] = \"a b c\";\n\n char str2[100] = \"1 2 3\";\n\n char str3[100] = \" b c\";\n\n\n\n assert(strcmp(func0(str1), \"abc\") == 0);\n\n assert(strcmp(func0(str2), \"123\") == 0);\n\n assert(strcmp(func0(str3), \"bc\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%rsi\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nsub $0x1,%rcx\ntest %ecx,%ecx\njle 11b7 \nmov %rsi,%rax\nlea -0x1(%rcx),%edx\nlea 0x1(%rsi,%rdx,1),%r8\nmov $0x0,%ecx\njmp 11ad \nmovslq %ecx,%rdi\nmov %dl,(%rsi,%rdi,1)\nlea 0x1(%rcx),%ecx\nadd $0x1,%rax\ncmp %r8,%rax\nje 11bc \nmovzbl (%rax),%edx\ncmp $0x20,%dl\njne 119b \njmp 11a4 \nmov $0x0,%ecx\nmovslq %ecx,%rcx\nmovb $0x0,(%rsi,%rcx,1)\nmov %rsi,%rax\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest eax, eax\njle short loc_11E7\nmov rdx, rbx\nlea eax, [rax-1]\nlea rdi, [rbx+rax+1]\nmov ecx, 0\njmp short loc_11D5\nloc_11CC:\nadd rdx, 1\ncmp rdx, rdi\njz short loc_11EC\nloc_11D5:\nmovzx eax, byte ptr [rdx]\ncmp al, 20h ; ' '\njz short loc_11CC\nmovsxd rsi, ecx\nmov [rbx+rsi], al\nlea ecx, [rcx+1]\njmp short loc_11CC\nloc_11E7:\nmov ecx, 0\nloc_11EC:\nmovsxd rcx, ecx\nmov byte ptr [rbx+rcx], 0\nmov rax, rbx\npop rbx\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n int v2; // eax\n const char *v3; // rdx\n __int64 v4; // rdi\n int v5; // ecx\n\n v2 = strlen(a1);\n if ( v2 <= 0 )\n {\n v5 = 0;\n }\n else\n {\n v3 = a1;\n v4 = (__int64)&a1[v2 - 1 + 1];\n v5 = 0;\n do\n {\n if ( *v3 != 32 )\n a1[v5++] = *v3;\n ++v3;\n }\n while ( v3 != (const char *)v4 );\n }\n a1[v5] = 0;\n return a1;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest eax, eax\njle short loc_11E7\nmov rdx, rbx\nlea eax, [rax-1]\nlea rdi, [rbx+rax+1]\nmov ecx, 0\njmp short loc_11D5\nloc_11CC:\nadd rdx, 1\ncmp rdx, rdi\njz short loc_11EC\nloc_11D5:\nmovzx eax, byte ptr [rdx]\ncmp al, 20h ; ' '\njz short loc_11CC\nmovsxd rsi, ecx\nmov [rbx+rsi], al\nlea ecx, [rcx+1]\njmp short loc_11CC\nloc_11E7:\nmov ecx, 0\nloc_11EC:\nmovsxd rcx, ecx\nmov byte ptr [rbx+rcx], 0\nmov rax, rbx\npop rbx\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_11A9(const char *a1)\n{\n int v2; // eax\n const char *v3; // rdx\n __int64 v4; // rdi\n int v5; // ecx\n\n v2 = strlen(a1);\n if ( v2 <= 0 )\n {\n v5 = 0;\n }\n else\n {\n v3 = a1;\n v4 = (__int64)&a1[v2 - 1 + 1];\n v5 = 0;\n do\n {\n if ( *v3 != 32 )\n a1[v5++] = *v3;\n ++v3;\n }\n while ( v3 != (const char *)v4 );\n }\n a1[v5] = 0;\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_11A9(const char *a1) {\n int v2;\n const char *v3;\n long long v4;\n int v5;\n v2 = strlen(a1);\n if (v2 <= 0) {\n v5 = 0;\n } else {\n v3 = a1;\n v4 = (long long)&a1[v2 - 1 + 1];\n v5 = 0;\n do {\n if (*v3 != 32) a1[v5++] = *v3;\n ++v3;\n } while (v3 != (const char *)v4);\n }\n a1[v5] = 0;\n return a1;\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n int v2;\n const char *v3;\n long long v4;\n int v5;\n v2 = strlen(a1);\n if (v2 <= 0) {\n v5 = 0;\n } else {\n v3 = a1;\n v4 = (long long)&a1[v2 - 1 + 1];\n v5 = 0;\n do {\n if (*v3 != 32) a1[v5++] = *v3;\n ++v3;\n } while (v3 != (const char *)v4);\n }\n a1[v5] = 0;\n return a1;\n}" + }, + { + "index": 678, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* str1) {\n int i, j = 0;\n int len = strlen(str1);\n for (i = 0; i < len; i++) {\n if (str1[i] != ' ') {\n str1[j++] = str1[i];\n }\n }\n str1[j] = '\\0';\n return str1;\n}", + "test": "int main() {\n\n char str1[100] = \"a b c\";\n\n char str2[100] = \"1 2 3\";\n\n char str3[100] = \" b c\";\n\n\n\n assert(strcmp(func0(str1), \"abc\") == 0);\n\n assert(strcmp(func0(str2), \"123\") == 0);\n\n assert(strcmp(func0(str3), \"bc\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %rdi,%r12\ncallq 1070 \ntest %eax,%eax\njle 13c8 \nsub $0x1,%eax\nmov %r12,%rdx\nxor %edi,%edi\nxor %esi,%esi\nlea 0x1(%r12,%rax,1),%r8\nnopl 0x0(%rax)\nmovzbl (%rdx),%eax\nlea (%r12,%rsi,1),%rcx\ncmp $0x20,%al\nje 13af \nadd $0x1,%edi\nmov %al,(%rcx)\nmovslq %edi,%rsi\nlea (%r12,%rsi,1),%rcx\nadd $0x1,%rdx\ncmp %r8,%rdx\njne 1398 \nmov %r12,%rax\nmovb $0x0,(%rcx)\npop %r12\nretq\nnopl 0x0(%rax)\nmov %r12,%rcx\nmov %r12,%rax\nmovb $0x0,(%rcx)\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest eax, eax\njle short loc_13D0\nsub eax, 1\nmov rdx, rbx\nlea rdi, [rbx+rax+1]\nxor eax, eax\nxchg ax, ax\nloc_13A0:\nmovzx ecx, byte ptr [rdx]\ncmp cl, 20h ; ' '\njz short loc_13B1\nmovsxd rsi, eax\nadd eax, 1\nmov [rbx+rsi], cl\nloc_13B1:\nadd rdx, 1\ncmp rdx, rdi\njnz short loc_13A0\ncdqe\nadd rax, rbx\nmov byte ptr [rax], 0\nmov rax, rbx\npop rbx\nretn\nloc_13D0:\nmov rax, rbx\nmov byte ptr [rax], 0\nmov rax, rbx\npop rbx\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n int v2; // eax\n const char *v3; // rdx\n __int64 v4; // rdi\n int v5; // eax\n __int64 v6; // rsi\n\n v2 = strlen(a1);\n if ( v2 <= 0 )\n {\n *a1 = 0;\n return a1;\n }\n else\n {\n v3 = a1;\n v4 = (__int64)&a1[v2 - 1 + 1];\n v5 = 0;\n do\n {\n if ( *v3 != 32 )\n {\n v6 = v5++;\n a1[v6] = *v3;\n }\n ++v3;\n }\n while ( v3 != (const char *)v4 );\n a1[v5] = 0;\n return a1;\n }\n}", + "ida_strip_asm": "sub_1380:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest eax, eax\njle short loc_13D0\nsub eax, 1\nmov rdx, rbx\nlea rdi, [rbx+rax+1]\nxor eax, eax\nxchg ax, ax\nloc_13A0:\nmovzx ecx, byte ptr [rdx]\ncmp cl, 20h ; ' '\njz short loc_13B1\nmovsxd rsi, eax\nadd eax, 1\nmov [rbx+rsi], cl\nloc_13B1:\nadd rdx, 1\ncmp rdx, rdi\njnz short loc_13A0\ncdqe\nadd rax, rbx\nmov byte ptr [rax], 0\nmov rax, rbx\npop rbx\nretn\nloc_13D0:\nmov rax, rbx\nmov byte ptr [rax], 0\nmov rax, rbx\npop rbx\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1380(const char *a1)\n{\n int v2; // eax\n const char *v3; // rdx\n __int64 v4; // rdi\n int v5; // eax\n __int64 v6; // rsi\n\n v2 = strlen(a1);\n if ( v2 <= 0 )\n {\n *a1 = 0;\n return a1;\n }\n else\n {\n v3 = a1;\n v4 = (__int64)&a1[v2 - 1 + 1];\n v5 = 0;\n do\n {\n if ( *v3 != 32 )\n {\n v6 = v5++;\n a1[v6] = *v3;\n }\n ++v3;\n }\n while ( v3 != (const char *)v4 );\n a1[v5] = 0;\n return a1;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1380(const char *a1) {\n int v2;\n const char *v3;\n long long v4;\n int v5;\n long long v6;\n v2 = strlen(a1);\n if (v2 <= 0) {\n *a1 = 0;\n return a1;\n } else {\n v3 = a1;\n v4 = (long long)&a1[v2 - 1 + 1];\n v5 = 0;\n do {\n if (*v3 != 32) {\n v6 = v5++;\n a1[v6] = *v3;\n }\n ++v3;\n } while (v3 != (const char *)v4);\n a1[v5] = 0;\n return a1;\n }\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n int v2;\n const char *v3;\n long long v4;\n int v5;\n long long v6;\n v2 = strlen(a1);\n if (v2 <= 0) {\n *a1 = 0;\n return a1;\n } else {\n v3 = a1;\n v4 = (long long)&a1[v2 - 1 + 1];\n v5 = 0;\n do {\n if (*v3 != 32) {\n v6 = v5++;\n a1[v6] = *v3;\n }\n ++v3;\n } while (v3 != (const char *)v4);\n a1[v5] = 0;\n return a1;\n }\n}" + }, + { + "index": 678, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* str1) {\n int i, j = 0;\n int len = strlen(str1);\n for (i = 0; i < len; i++) {\n if (str1[i] != ' ') {\n str1[j++] = str1[i];\n }\n }\n str1[j] = '\\0';\n return str1;\n}", + "test": "int main() {\n\n char str1[100] = \"a b c\";\n\n char str2[100] = \"1 2 3\";\n\n char str3[100] = \" b c\";\n\n\n\n assert(strcmp(func0(str1), \"abc\") == 0);\n\n assert(strcmp(func0(str2), \"123\") == 0);\n\n assert(strcmp(func0(str3), \"bc\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %rdi,%r12\ncallq 1070 \ntest %eax,%eax\njle 13c8 \nsub $0x1,%eax\nmov %r12,%rdx\nxor %edi,%edi\nxor %esi,%esi\nlea 0x1(%r12,%rax,1),%r8\nnopl 0x0(%rax)\nmovzbl (%rdx),%eax\nlea (%r12,%rsi,1),%rcx\ncmp $0x20,%al\nje 13af \nadd $0x1,%edi\nmov %al,(%rcx)\nmovslq %edi,%rsi\nlea (%r12,%rsi,1),%rcx\nadd $0x1,%rdx\ncmp %rdx,%r8\njne 1398 \nmov %r12,%rax\nmovb $0x0,(%rcx)\npop %r12\nretq\nnopl 0x0(%rax)\nmov %r12,%rcx\nmov %r12,%rax\nmovb $0x0,(%rcx)\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest eax, eax\njle short loc_13D0\nsub eax, 1\nmov rdx, rbx\nlea rdi, [rbx+rax+1]\nxor eax, eax\nxchg ax, ax\nloc_13A0:\nmovzx ecx, byte ptr [rdx]\ncmp cl, 20h ; ' '\njz short loc_13B1\nmovsxd rsi, eax\nadd eax, 1\nmov [rbx+rsi], cl\nloc_13B1:\nadd rdx, 1\ncmp rdi, rdx\njnz short loc_13A0\ncdqe\nadd rax, rbx\nmov byte ptr [rax], 0\nmov rax, rbx\npop rbx\nretn\nloc_13D0:\nmov rax, rbx\nmov byte ptr [rax], 0\nmov rax, rbx\npop rbx\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n int v2; // eax\n const char *v3; // rdx\n __int64 v4; // rdi\n int v5; // eax\n __int64 v6; // rsi\n\n v2 = strlen(a1);\n if ( v2 <= 0 )\n {\n *a1 = 0;\n return a1;\n }\n else\n {\n v3 = a1;\n v4 = (__int64)&a1[v2 - 1 + 1];\n v5 = 0;\n do\n {\n if ( *v3 != 32 )\n {\n v6 = v5++;\n a1[v6] = *v3;\n }\n ++v3;\n }\n while ( (const char *)v4 != v3 );\n a1[v5] = 0;\n return a1;\n }\n}", + "ida_strip_asm": "sub_1380:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest eax, eax\njle short loc_13D0\nsub eax, 1\nmov rdx, rbx\nlea rdi, [rbx+rax+1]\nxor eax, eax\nxchg ax, ax\nloc_13A0:\nmovzx ecx, byte ptr [rdx]\ncmp cl, 20h ; ' '\njz short loc_13B1\nmovsxd rsi, eax\nadd eax, 1\nmov [rbx+rsi], cl\nloc_13B1:\nadd rdx, 1\ncmp rdi, rdx\njnz short loc_13A0\ncdqe\nadd rax, rbx\nmov byte ptr [rax], 0\nmov rax, rbx\npop rbx\nretn\nloc_13D0:\nmov rax, rbx\nmov byte ptr [rax], 0\nmov rax, rbx\npop rbx\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1380(const char *a1)\n{\n int v2; // eax\n const char *v3; // rdx\n __int64 v4; // rdi\n int v5; // eax\n __int64 v6; // rsi\n\n v2 = strlen(a1);\n if ( v2 <= 0 )\n {\n *a1 = 0;\n return a1;\n }\n else\n {\n v3 = a1;\n v4 = (__int64)&a1[v2 - 1 + 1];\n v5 = 0;\n do\n {\n if ( *v3 != 32 )\n {\n v6 = v5++;\n a1[v6] = *v3;\n }\n ++v3;\n }\n while ( (const char *)v4 != v3 );\n a1[v5] = 0;\n return a1;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1380(const char *a1) {\n int v2;\n const char *v3;\n long long v4;\n int v5;\n long long v6;\n v2 = strlen(a1);\n if (v2 <= 0) {\n *a1 = 0;\n return a1;\n } else {\n v3 = a1;\n v4 = (long long)&a1[v2 - 1 + 1];\n v5 = 0;\n do {\n if (*v3 != 32) {\n v6 = v5++;\n a1[v6] = *v3;\n }\n ++v3;\n } while ((const char *)v4 != v3);\n a1[v5] = 0;\n return a1;\n }\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n int v2;\n const char *v3;\n long long v4;\n int v5;\n long long v6;\n v2 = strlen(a1);\n if (v2 <= 0) {\n *a1 = 0;\n return a1;\n } else {\n v3 = a1;\n v4 = (long long)&a1[v2 - 1 + 1];\n v5 = 0;\n do {\n if (*v3 != 32) {\n v6 = v5++;\n a1[v6] = *v3;\n }\n ++v3;\n } while ((const char *)v4 != v3);\n a1[v5] = 0;\n return a1;\n }\n}" + }, + { + "index": 679, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char** keys, int index) { return keys[index]; }", + "test": "int main() {\n\n char* keys1[] = {\"physics\", \"math\", \"chemistry\"};\n\n assert(strcmp(func0(keys1, 0), \"physics\") == 0);\n\n \n\n char* keys2[] = {\"python\", \"java\", \"C++\"};\n\n assert(strcmp(func0(keys2, 2), \"C++\") == 0);\n\n\n\n char* keys3[] = {\"program\", \"computer\"};\n\n assert(strcmp(func0(keys3, 1), \"computer\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x8(%rbp)\nmov %esi,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_8], rdi\nmov [rbp+var_C], esi\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov rax, [rax]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n return *(_QWORD *)(8LL * a2 + a1);\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_8], rdi\nmov [rbp+var_C], esi\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov rax, [rax]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2)\n{\n return *(_QWORD *)(8LL * a2 + a1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2) {\n return *(uint64_t *)(8LL * a2 + a1);\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) { return *(uint64_t *)(8LL * a2 + a1); }" + }, + { + "index": 680, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int nums[], int size) {\n for (int i = 0; i < size - 1; i++) {\n if (nums[i] > nums[i + 1]) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n int array1[] = {1, 2, 3, 4};\n\n int array2[] = {4, 3, 2, 1};\n\n int array3[] = {0, 1, 4, 9};\n\n \n\n assert(func0(array1, 4) == true);\n\n assert(func0(array2, 4) == false);\n\n assert(func0(array3, 4) == true);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11c0 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njle 11bc \nmov $0x0,%eax\njmp 11d0 \naddl $0x1,-0x4(%rbp)\nmov -0x1c(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x4(%rbp)\njl 1181 \nmov $0x1,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 0\njmp short loc_11C0\nloc_1181:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_11BC\nmov eax, 0\njmp short loc_11D0\nloc_11BC:\nadd [rbp+var_4], 1\nloc_11C0:\nmov eax, [rbp+var_1C]\nsub eax, 1\ncmp [rbp+var_4], eax\njl short loc_1181\nmov eax, 1\nloc_11D0:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i < a2 - 1; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) > *(_DWORD *)(4 * (i + 1LL) + a1) )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 0\njmp short loc_11C0\nloc_1181:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_11BC\nmov eax, 0\njmp short loc_11D0\nloc_11BC:\nadd [rbp+var_4], 1\nloc_11C0:\nmov eax, [rbp+var_1C]\nsub eax, 1\ncmp [rbp+var_4], eax\njl short loc_1181\nmov eax, 1\nloc_11D0:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i < a2 - 1; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) > *(_DWORD *)(4 * (i + 1LL) + a1) )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int i;\n for (i = 0; i < a2 - 1; ++i) {\n if (*(uint32_t *)(4LL * i + a1) > *(uint32_t *)(4 * (i + 1LL) + a1))\n return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int i;\n for (i = 0; i < a2 - 1; ++i) {\n if (*(uint32_t *)(4LL * i + a1) > *(uint32_t *)(4 * (i + 1LL) + a1))\n return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": 680, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int nums[], int size) {\n for (int i = 0; i < size - 1; i++) {\n if (nums[i] > nums[i + 1]) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n int array1[] = {1, 2, 3, 4};\n\n int array2[] = {4, 3, 2, 1};\n\n int array3[] = {0, 1, 4, 9};\n\n \n\n assert(func0(array1, 4) == true);\n\n assert(func0(array2, 4) == false);\n\n assert(func0(array3, 4) == true);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%esi\njle 1193 \nmov %rdi,%rax\nlea -0x2(%rsi),%edx\nlea 0x4(%rdi,%rdx,4),%rdx\nmov 0x4(%rax),%ecx\ncmp %ecx,(%rax)\njg 1199 \nadd $0x4,%rax\ncmp %rdx,%rax\njne 117d \nmov $0x1,%eax\nretq\nmov $0x1,%eax\nretq\nmov $0x0,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ncmp esi, 1\njle short loc_1193\nmov rax, rdi\nlea edx, [rsi-2]\nlea rdx, [rdi+rdx*4+4]\nloc_117D:\nmov ecx, [rax+4]\ncmp [rax], ecx\njg short loc_1199\nadd rax, 4\ncmp rax, rdx\njnz short loc_117D\nmov eax, 1\nretn\nloc_1193:\nmov eax, 1\nretn\nloc_1199:\nmov eax, 0\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n\n if ( a2 <= 1 )\n return 1LL;\n v2 = a1;\n while ( *v2 <= v2[1] )\n {\n if ( ++v2 == &a1[a2 - 2 + 1] )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ncmp esi, 1\njle short loc_1193\nmov rax, rdi\nlea edx, [rsi-2]\nlea rdx, [rdi+rdx*4+4]\nloc_117D:\nmov ecx, [rax+4]\ncmp [rax], ecx\njg short loc_1199\nadd rax, 4\ncmp rax, rdx\njnz short loc_117D\nmov eax, 1\nretn\nloc_1193:\nmov eax, 1\nretn\nloc_1199:\nmov eax, 0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n\n if ( a2 <= 1 )\n return 1LL;\n v2 = a1;\n while ( *v2 <= v2[1] )\n {\n if ( ++v2 == &a1[a2 - 2 + 1] )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2) {\n uint32_t *v2;\n if (a2 <= 1) return 1LL;\n v2 = a1;\n while (*v2 <= v2[1]) {\n if (++v2 == &a1[a2 - 2 + 1]) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n if (a2 <= 1) return 1LL;\n v2 = a1;\n while (*v2 <= v2[1]) {\n if (++v2 == &a1[a2 - 2 + 1]) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 680, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int nums[], int size) {\n for (int i = 0; i < size - 1; i++) {\n if (nums[i] > nums[i + 1]) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n int array1[] = {1, 2, 3, 4};\n\n int array2[] = {4, 3, 2, 1};\n\n int array3[] = {0, 1, 4, 9};\n\n \n\n assert(func0(array1, 4) == true);\n\n assert(func0(array2, 4) == false);\n\n assert(func0(array3, 4) == true);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%esi\njle 1170 \nlea -0x2(%rsi),%eax\nlea 0x4(%rdi,%rax,4),%rax\njmp 1161 \nnopl 0x0(%rax,%rax,1)\nadd $0x4,%rdi\ncmp %rax,%rdi\nje 1170 \nmov 0x4(%rdi),%edx\ncmp %edx,(%rdi)\njle 1158 \nxor %eax,%eax\nretq\nnopl 0x0(%rax,%rax,1)\nmov $0x1,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ncmp esi, 1\njle short loc_1298\nlea ecx, [rsi-2]\nmov edx, [rdi]\nlea rax, [rdi+4]\nlea rsi, [rdi+rcx*4+8]\njmp short loc_1289\nloc_1280:\nadd rax, 4\ncmp rax, rsi\njz short loc_1298\nloc_1289:\nmov ecx, edx\nmov edx, [rax]\ncmp edx, ecx\njge short loc_1280\nxor eax, eax\nretn\nloc_1298:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int v2; // edx\n int *v3; // rax\n __int64 v4; // rsi\n int v5; // ecx\n\n if ( a2 <= 1 )\n return 1LL;\n v2 = *a1;\n v3 = a1 + 1;\n v4 = (__int64)&a1[a2 - 2 + 2];\n while ( 1 )\n {\n v5 = v2;\n v2 = *v3;\n if ( *v3 < v5 )\n break;\n if ( ++v3 == (int *)v4 )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1260:\nendbr64\ncmp esi, 1\njle short loc_1298\nlea ecx, [rsi-2]\nmov edx, [rdi]\nlea rax, [rdi+4]\nlea rsi, [rdi+rcx*4+8]\njmp short loc_1289\nloc_1280:\nadd rax, 4\ncmp rax, rsi\njz short loc_1298\nloc_1289:\nmov ecx, edx\nmov edx, [rax]\ncmp edx, ecx\njge short loc_1280\nxor eax, eax\nretn\nloc_1298:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1260(int *a1, int a2)\n{\n int v2; // edx\n int *v3; // rax\n __int64 v4; // rsi\n int v5; // ecx\n\n if ( a2 <= 1 )\n return 1LL;\n v2 = *a1;\n v3 = a1 + 1;\n v4 = (__int64)&a1[a2 - 2 + 2];\n while ( 1 )\n {\n v5 = v2;\n v2 = *v3;\n if ( *v3 < v5 )\n break;\n if ( ++v3 == (int *)v4 )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1260(int *a1, int a2) {\n int v2;\n int *v3;\n long long v4;\n int v5;\n if (a2 <= 1) return 1LL;\n v2 = *a1;\n v3 = a1 + 1;\n v4 = (long long)&a1[a2 - 2 + 2];\n while (1) {\n v5 = v2;\n v2 = *v3;\n if (*v3 < v5) break;\n if (++v3 == (int *)v4) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int v2;\n int *v3;\n long long v4;\n int v5;\n if (a2 <= 1) return 1LL;\n v2 = *a1;\n v3 = a1 + 1;\n v4 = (long long)&a1[a2 - 2 + 2];\n while (1) {\n v5 = v2;\n v2 = *v3;\n if (*v3 < v5) break;\n if (++v3 == (int *)v4) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 681, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n % 2 == 0) {\n return 2;\n }\n int i = 3;\n while (i * i <= n) {\n if (n % i == 0) {\n return i;\n }\n i += 2;\n }\n return n;\n}", + "test": "int main() {\n\n assert(func0(10) == 2);\n\n assert(func0(25) == 5);\n\n assert(func0(31) == 31);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov -0x14(%rbp),%eax\nand $0x1,%eax\ntest %eax,%eax\njne 1165 \nmov $0x2,%eax\njmp 1192 \nmovl $0x3,-0x4(%rbp)\njmp 1184 \nmov -0x14(%rbp),%eax\ncltd\nidivl -0x4(%rbp)\nmov %edx,%eax\ntest %eax,%eax\njne 1180 \nmov -0x4(%rbp),%eax\njmp 1192 \naddl $0x2,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nimul %eax,%eax\ncmp %eax,-0x14(%rbp)\njge 116e \nmov -0x14(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov eax, [rbp+var_14]\nand eax, 1\ntest eax, eax\njnz short loc_1165\nmov eax, 2\njmp short loc_1192\nloc_1165:\nmov [rbp+var_4], 3\njmp short loc_1184\nloc_116E:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njnz short loc_1180\nmov eax, [rbp+var_4]\njmp short loc_1192\nloc_1180:\nadd [rbp+var_4], 2\nloc_1184:\nmov eax, [rbp+var_4]\nimul eax, eax\ncmp [rbp+var_14], eax\njge short loc_116E\nmov eax, [rbp+var_14]\nloc_1192:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int i; // [rsp+10h] [rbp-4h]\n\n if ( (a1 & 1) == 0 )\n return 2LL;\n for ( i = 3; a1 >= i * i; i += 2 )\n {\n if ( !(a1 % i) )\n return (unsigned int)i;\n }\n return (unsigned int)a1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov eax, [rbp+var_14]\nand eax, 1\ntest eax, eax\njnz short loc_1165\nmov eax, 2\njmp short loc_1192\nloc_1165:\nmov [rbp+var_4], 3\njmp short loc_1184\nloc_116E:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njnz short loc_1180\nmov eax, [rbp+var_4]\njmp short loc_1192\nloc_1180:\nadd [rbp+var_4], 2\nloc_1184:\nmov eax, [rbp+var_4]\nimul eax, eax\ncmp [rbp+var_14], eax\njge short loc_116E\nmov eax, [rbp+var_14]\nloc_1192:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int i; // [rsp+10h] [rbp-4h]\n\n if ( (a1 & 1) == 0 )\n return 2LL;\n for ( i = 3; a1 >= i * i; i += 2 )\n {\n if ( !(a1 % i) )\n return (unsigned int)i;\n }\n return (unsigned int)a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int i;\n if ((a1 & 1) == 0) return 2LL;\n for (i = 3; a1 >= i * i; i += 2) {\n if (!(a1 % i)) return (unsigned int)i;\n }\n return (unsigned int)a1;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int i;\n if ((a1 & 1) == 0) return 2LL;\n for (i = 3; a1 >= i * i; i += 2) {\n if (!(a1 % i)) return (unsigned int)i;\n }\n return (unsigned int)a1;\n}" + }, + { + "index": 681, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n % 2 == 0) {\n return 2;\n }\n int i = 3;\n while (i * i <= n) {\n if (n % i == 0) {\n return i;\n }\n i += 2;\n }\n return n;\n}", + "test": "int main() {\n\n assert(func0(10) == 2);\n\n assert(func0(25) == 5);\n\n assert(func0(31) == 31);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x2,%ecx\ntest $0x1,%dil\nje 1197 \ncmp $0x8,%edi\njle 119a \nmovslq %edi,%rax\nimul $0x55555556,%rax,%rax\nshr $0x20,%rax\nmov %edi,%edx\nsar $0x1f,%edx\nsub %edx,%eax\nlea (%rax,%rax,2),%eax\ncmp %eax,%edi\nje 119e \nmov $0x3,%ecx\nadd $0x2,%ecx\nmov %ecx,%eax\nimul %ecx,%eax\ncmp %edi,%eax\njg 1195 \nmov %edi,%eax\ncltd\nidiv %ecx\ntest %edx,%edx\njne 117e \njmp 1197 \nmov %edi,%ecx\nmov %ecx,%eax\nretq\nmov %edi,%ecx\njmp 1197 \nmov $0x3,%ecx\njmp 1197 \n", + "ida_asm": "func0:\nendbr64\nmov ecx, 2\ntest dil, 1\njz short loc_1197\ncmp edi, 8\njle short loc_119A\nmovsxd rax, edi\nimul rax, 55555556h\nshr rax, 20h\nmov edx, edi\nsar edx, 1Fh\nsub eax, edx\nlea eax, [rax+rax*2]\ncmp edi, eax\njz short loc_119E\nmov ecx, 3\nloc_117E:\nadd ecx, 2\nmov eax, ecx\nimul eax, ecx\ncmp eax, edi\njg short loc_1195\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_117E\njmp short loc_1197\nloc_1195:\nmov ecx, edi\nloc_1197:\nmov eax, ecx\nretn\nloc_119A:\nmov ecx, edi\njmp short loc_1197\nloc_119E:\nmov ecx, 3\njmp short loc_1197", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v1; // ecx\n\n v1 = 2;\n if ( (a1 & 1) != 0 )\n {\n if ( a1 <= 8 )\n {\n return (unsigned int)a1;\n }\n else if ( a1 == 3 * (a1 / 3) )\n {\n return 3;\n }\n else\n {\n v1 = 3;\n while ( 1 )\n {\n v1 += 2;\n if ( (int)(v1 * v1) > a1 )\n break;\n if ( !(a1 % (int)v1) )\n return v1;\n }\n return (unsigned int)a1;\n }\n }\n return v1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmov ecx, 2\ntest dil, 1\njz short loc_1197\ncmp edi, 8\njle short loc_119A\nmovsxd rax, edi\nimul rax, 55555556h\nshr rax, 20h\nmov edx, edi\nsar edx, 1Fh\nsub eax, edx\nlea eax, [rax+rax*2]\ncmp edi, eax\njz short loc_119E\nmov ecx, 3\nloc_117E:\nadd ecx, 2\nmov eax, ecx\nimul eax, ecx\ncmp eax, edi\njg short loc_1195\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_117E\njmp short loc_1197\nloc_1195:\nmov ecx, edi\nloc_1197:\nmov eax, ecx\nretn\nloc_119A:\nmov ecx, edi\njmp short loc_1197\nloc_119E:\nmov ecx, 3\njmp short loc_1197", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n unsigned int v1; // ecx\n\n v1 = 2;\n if ( (a1 & 1) != 0 )\n {\n if ( a1 <= 8 )\n {\n return (unsigned int)a1;\n }\n else if ( a1 == 3 * (a1 / 3) )\n {\n return 3;\n }\n else\n {\n v1 = 3;\n while ( 1 )\n {\n v1 += 2;\n if ( (int)(v1 * v1) > a1 )\n break;\n if ( !(a1 % (int)v1) )\n return v1;\n }\n return (unsigned int)a1;\n }\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n unsigned int v1;\n v1 = 2;\n if ((a1 & 1) != 0) {\n if (a1 <= 8) {\n return (unsigned int)a1;\n } else if (a1 == 3 * (a1 / 3)) {\n return 3;\n } else {\n v1 = 3;\n while (1) {\n v1 += 2;\n if ((int)(v1 * v1) > a1) break;\n if (!(a1 % (int)v1)) return v1;\n }\n return (unsigned int)a1;\n }\n }\n return v1;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v1;\n v1 = 2;\n if ((a1 & 1) != 0) {\n if (a1 <= 8) {\n return (unsigned int)a1;\n } else if (a1 == 3 * (a1 / 3)) {\n return 3;\n } else {\n v1 = 3;\n while (1) {\n v1 += 2;\n if ((int)(v1 * v1) > a1) break;\n if (!(a1 % (int)v1)) return v1;\n }\n return (unsigned int)a1;\n }\n }\n return v1;\n}" + }, + { + "index": 682, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int* nums1, int* nums2, int n, int* result) {\n for (int i = 0; i < n; i++) {\n result[i] = nums1[i] * nums2[i];\n }\n return result;\n}", + "test": "int main() {\n\n int result1[3], result2[2], result3[2];\n\n int nums1a[] = {1, 2, 3};\n\n int nums2a[] = {4, 5, 6};\n\n int nums1b[] = {1, 2};\n\n int nums2b[] = {3, 4};\n\n int nums1c[] = {90, 120};\n\n int nums2c[] = {50, 70};\n\n\n\n func0(nums1a, nums2a, 3, result1);\n\n func0(nums1b, nums2b, 2, result2);\n\n func0(nums1c, nums2c, 2, result3);\n\n\n\n assert(result1[0] == 4 && result1[1] == 10 && result1[2] == 18);\n\n assert(result2[0] == 3 && result2[1] == 8);\n\n assert(result3[0] == 4500 && result3[1] == 8400);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %edx,-0x24(%rbp)\nmov %rcx,-0x30(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11d3 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%ecx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov -0x4(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rsi\nmov -0x30(%rbp),%rdx\nadd %rsi,%rdx\nimul %ecx,%eax\nmov %eax,(%rdx)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x24(%rbp),%eax\njl 1189 \nmov -0x30(%rbp),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_30], rcx\nmov [rbp+var_4], 0\njmp short loc_11D3\nloc_1189:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rcx\nmov eax, [rax]\nmov ecx, [rbp+var_4]\nmovsxd rcx, ecx\nlea rsi, ds:0[rcx*4]\nmov rcx, [rbp+var_30]\nadd rcx, rsi\nimul eax, edx\nmov [rcx], eax\nadd [rbp+var_4], 1\nloc_11D3:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_24]\njl short loc_1189\nmov rax, [rbp+var_30]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3, __int64 a4)\n{\n int i; // [rsp+2Ch] [rbp-4h]\n\n for ( i = 0; i < a3; ++i )\n *(_DWORD *)(4LL * i + a4) = *(_DWORD *)(4LL * i + a1) * *(_DWORD *)(4LL * i + a2);\n return a4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_30], rcx\nmov [rbp+var_4], 0\njmp short loc_11D3\nloc_1189:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rcx\nmov eax, [rax]\nmov ecx, [rbp+var_4]\nmovsxd rcx, ecx\nlea rsi, ds:0[rcx*4]\nmov rcx, [rbp+var_30]\nadd rcx, rsi\nimul eax, edx\nmov [rcx], eax\nadd [rbp+var_4], 1\nloc_11D3:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_24]\njl short loc_1189\nmov rax, [rbp+var_30]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, int a3, __int64 a4)\n{\n int i; // [rsp+2Ch] [rbp-4h]\n\n for ( i = 0; i < a3; ++i )\n *(_DWORD *)(4LL * i + a4) = *(_DWORD *)(4LL * i + a1) * *(_DWORD *)(4LL * i + a2);\n return a4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, int a3, long long a4) {\n int i;\n for (i = 0; i < a3; ++i)\n *(uint32_t *)(4LL * i + a4) =\n *(uint32_t *)(4LL * i + a1) * *(uint32_t *)(4LL * i + a2);\n return a4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3, long long a4) {\n int i;\n for (i = 0; i < a3; ++i)\n *(uint32_t *)(4LL * i + a4) =\n *(uint32_t *)(4LL * i + a1) * *(uint32_t *)(4LL * i + a2);\n return a4;\n}" + }, + { + "index": 682, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int* nums1, int* nums2, int n, int* result) {\n for (int i = 0; i < n; i++) {\n result[i] = nums1[i] * nums2[i];\n }\n return result;\n}", + "test": "int main() {\n\n int result1[3], result2[2], result3[2];\n\n int nums1a[] = {1, 2, 3};\n\n int nums2a[] = {4, 5, 6};\n\n int nums1b[] = {1, 2};\n\n int nums2b[] = {3, 4};\n\n int nums1c[] = {90, 120};\n\n int nums2c[] = {50, 70};\n\n\n\n func0(nums1a, nums2a, 3, result1);\n\n func0(nums1b, nums2b, 2, result2);\n\n func0(nums1c, nums2c, 2, result3);\n\n\n\n assert(result1[0] == 4 && result1[1] == 10 && result1[2] == 18);\n\n assert(result2[0] == 3 && result2[1] == 8);\n\n assert(result3[0] == 4500 && result3[1] == 8400);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rcx,%rax\ntest %edx,%edx\njle 1195 \nlea -0x1(%rdx),%ecx\nmov $0x0,%edx\nmov (%rdi,%rdx,4),%r8d\nimul (%rsi,%rdx,4),%r8d\nmov %r8d,(%rax,%rdx,4)\nmov %rdx,%r8\nadd $0x1,%rdx\ncmp %rcx,%r8\njne 117c \nretq\n", + "ida_asm": "func0:\nendbr64\nmov rax, rcx\ntest edx, edx\njle short locret_119A\nmovsxd rdx, edx\nlea r9, ds:0[rdx*4]\nmov edx, 0\nloc_1184:\nmov r8d, [rdi+rdx]\nimul r8d, [rsi+rdx]\nmov [rax+rdx], r8d\nadd rdx, 4\ncmp rdx, r9\njnz short loc_1184\nlocret_119A:\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3, __int64 a4)\n{\n __int64 result; // rax\n __int64 v5; // r9\n __int64 v6; // rdx\n\n result = a4;\n if ( a3 > 0 )\n {\n v5 = 4LL * a3;\n v6 = 0LL;\n do\n {\n *(_DWORD *)(a4 + v6) = *(_DWORD *)(a2 + v6) * *(_DWORD *)(a1 + v6);\n v6 += 4LL;\n }\n while ( v6 != v5 );\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov rax, rcx\ntest edx, edx\njle short locret_119A\nmovsxd rdx, edx\nlea r9, ds:0[rdx*4]\nmov edx, 0\nloc_1184:\nmov r8d, [rdi+rdx]\nimul r8d, [rsi+rdx]\nmov [rax+rdx], r8d\nadd rdx, 4\ncmp rdx, r9\njnz short loc_1184\nlocret_119A:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, int a3, __int64 a4)\n{\n __int64 result; // rax\n __int64 v5; // r9\n __int64 v6; // rdx\n\n result = a4;\n if ( a3 > 0 )\n {\n v5 = 4LL * a3;\n v6 = 0LL;\n do\n {\n *(_DWORD *)(a4 + v6) = *(_DWORD *)(a2 + v6) * *(_DWORD *)(a1 + v6);\n v6 += 4LL;\n }\n while ( v6 != v5 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, int a3, long long a4) {\n long long result;\n long long v5;\n long long v6;\n result = a4;\n if (a3 > 0) {\n v5 = 4LL * a3;\n v6 = 0LL;\n do {\n *(uint32_t *)(a4 + v6) = *(uint32_t *)(a2 + v6) * *(uint32_t *)(a1 + v6);\n v6 += 4LL;\n } while (v6 != v5);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3, long long a4) {\n long long result;\n long long v5;\n long long v6;\n result = a4;\n if (a3 > 0) {\n v5 = 4LL * a3;\n v6 = 0LL;\n do {\n *(uint32_t *)(a4 + v6) = *(uint32_t *)(a2 + v6) * *(uint32_t *)(a1 + v6);\n v6 += 4LL;\n } while (v6 != v5);\n }\n return result;\n}" + }, + { + "index": 683, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int n) {\n int i = 1;\n while (i * i <= n) {\n int j = 1;\n while (j * j <= n) {\n if ((i * i + j * j) == n) {\n return true;\n }\n j++;\n }\n i++;\n }\n return false;\n}", + "test": "int main() {\n\n assert(func0(25) == true);\n\n assert(func0(24) == false);\n\n assert(func0(17) == true);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmovl $0x1,-0x8(%rbp)\njmp 1195 \nmovl $0x1,-0x4(%rbp)\njmp 1186 \nmov -0x8(%rbp),%eax\nimul %eax,%eax\nmov %eax,%edx\nmov -0x4(%rbp),%eax\nimul %eax,%eax\nadd %edx,%eax\ncmp %eax,-0x14(%rbp)\njne 1182 \nmov $0x1,%eax\njmp 11a5 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nimul %eax,%eax\ncmp %eax,-0x14(%rbp)\njge 1166 \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\nimul %eax,%eax\ncmp %eax,-0x14(%rbp)\njge 115d \nmov $0x0,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_8], 1\njmp short loc_1195\nloc_115D:\nmov [rbp+var_4], 1\njmp short loc_1186\nloc_1166:\nmov eax, [rbp+var_8]\nimul eax, eax\nmov edx, eax\nmov eax, [rbp+var_4]\nimul eax, eax\nadd eax, edx\ncmp [rbp+var_14], eax\njnz short loc_1182\nmov eax, 1\njmp short loc_11A5\nloc_1182:\nadd [rbp+var_4], 1\nloc_1186:\nmov eax, [rbp+var_4]\nimul eax, eax\ncmp [rbp+var_14], eax\njge short loc_1166\nadd [rbp+var_8], 1\nloc_1195:\nmov eax, [rbp+var_8]\nimul eax, eax\ncmp [rbp+var_14], eax\njge short loc_115D\nmov eax, 0\nloc_11A5:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int i; // [rsp+Ch] [rbp-8h]\n int j; // [rsp+10h] [rbp-4h]\n\n for ( i = 1; a1 >= i * i; ++i )\n {\n for ( j = 1; a1 >= j * j; ++j )\n {\n if ( a1 == i * i + j * j )\n return 1LL;\n }\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_8], 1\njmp short loc_1195\nloc_115D:\nmov [rbp+var_4], 1\njmp short loc_1186\nloc_1166:\nmov eax, [rbp+var_8]\nimul eax, eax\nmov edx, eax\nmov eax, [rbp+var_4]\nimul eax, eax\nadd eax, edx\ncmp [rbp+var_14], eax\njnz short loc_1182\nmov eax, 1\njmp short loc_11A5\nloc_1182:\nadd [rbp+var_4], 1\nloc_1186:\nmov eax, [rbp+var_4]\nimul eax, eax\ncmp [rbp+var_14], eax\njge short loc_1166\nadd [rbp+var_8], 1\nloc_1195:\nmov eax, [rbp+var_8]\nimul eax, eax\ncmp [rbp+var_14], eax\njge short loc_115D\nmov eax, 0\nloc_11A5:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int i; // [rsp+Ch] [rbp-8h]\n int j; // [rsp+10h] [rbp-4h]\n\n for ( i = 1; a1 >= i * i; ++i )\n {\n for ( j = 1; a1 >= j * j; ++j )\n {\n if ( a1 == i * i + j * j )\n return 1LL;\n }\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int i;\n int j;\n for (i = 1; a1 >= i * i; ++i) {\n for (j = 1; a1 >= j * j; ++j) {\n if (a1 == i * i + j * j) return 1LL;\n }\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int i;\n int j;\n for (i = 1; a1 >= i * i; ++i) {\n for (j = 1; a1 >= j * j; ++j) {\n if (a1 == i * i + j * j) return 1LL;\n }\n }\n return 0LL;\n}" + }, + { + "index": 683, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int n) {\n int i = 1;\n while (i * i <= n) {\n int j = 1;\n while (j * j <= n) {\n if ((i * i + j * j) == n) {\n return true;\n }\n j++;\n }\n i++;\n }\n return false;\n}", + "test": "int main() {\n\n assert(func0(25) == true);\n\n assert(func0(24) == false);\n\n assert(func0(17) == true);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x1,%esi\nmov $0x1,%ecx\ntest %edi,%edi\njle 117f \nlea 0x1(%rcx),%eax\ncmp %eax,%edi\nje 1197 \nmov $0x1,%edx\nadd $0x1,%edx\nmov %edx,%eax\nimul %edx,%eax\ncmp %edi,%eax\njg 1185 \nadd %ecx,%eax\ncmp %edi,%eax\njne 1167 \nmov $0x1,%eax\nretq\nmov $0x0,%eax\nretq\nadd $0x1,%esi\nmov %esi,%ecx\nimul %esi,%ecx\ncmp %edi,%ecx\njle 115b \nmov $0x0,%eax\nretq\nmov $0x1,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov esi, 1\nmov ecx, 1\ntest edi, edi\njle short loc_117F\nloc_115B:\nlea eax, [rcx+1]\ncmp edi, eax\njz short loc_1197\nmov edx, 1\nloc_1167:\nadd edx, 1\nmov eax, edx\nimul eax, edx\ncmp eax, edi\njg short loc_1185\nadd eax, ecx\ncmp eax, edi\njnz short loc_1167\nmov eax, 1\nretn\nloc_117F:\nmov eax, 0\nretn\nloc_1185:\nadd esi, 1\nmov ecx, esi\nimul ecx, esi\ncmp ecx, edi\njle short loc_115B\nmov eax, 0\nretn\nloc_1197:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // esi\n int v2; // ecx\n int v3; // edx\n\n v1 = 1;\n v2 = 1;\n if ( a1 <= 0 )\n return 0LL;\n while ( a1 != v2 + 1 )\n {\n v3 = 1;\n while ( 1 )\n {\n ++v3;\n if ( v3 * v3 > a1 )\n break;\n if ( v2 + v3 * v3 == a1 )\n return 1LL;\n }\n ++v1;\n v2 = v1 * v1;\n if ( v1 * v1 > a1 )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmov esi, 1\nmov ecx, 1\ntest edi, edi\njle short loc_117F\nloc_115B:\nlea eax, [rcx+1]\ncmp edi, eax\njz short loc_1197\nmov edx, 1\nloc_1167:\nadd edx, 1\nmov eax, edx\nimul eax, edx\ncmp eax, edi\njg short loc_1185\nadd eax, ecx\ncmp eax, edi\njnz short loc_1167\nmov eax, 1\nretn\nloc_117F:\nmov eax, 0\nretn\nloc_1185:\nadd esi, 1\nmov ecx, esi\nimul ecx, esi\ncmp ecx, edi\njle short loc_115B\nmov eax, 0\nretn\nloc_1197:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v1; // esi\n int v2; // ecx\n int v3; // edx\n\n v1 = 1;\n v2 = 1;\n if ( a1 <= 0 )\n return 0LL;\n while ( a1 != v2 + 1 )\n {\n v3 = 1;\n while ( 1 )\n {\n ++v3;\n if ( v3 * v3 > a1 )\n break;\n if ( v2 + v3 * v3 == a1 )\n return 1LL;\n }\n ++v1;\n v2 = v1 * v1;\n if ( v1 * v1 > a1 )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v1;\n int v2;\n int v3;\n v1 = 1;\n v2 = 1;\n if (a1 <= 0) return 0LL;\n while (a1 != v2 + 1) {\n v3 = 1;\n while (1) {\n ++v3;\n if (v3 * v3 > a1) break;\n if (v2 + v3 * v3 == a1) return 1LL;\n }\n ++v1;\n v2 = v1 * v1;\n if (v1 * v1 > a1) return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v2;\n int v3;\n v1 = 1;\n v2 = 1;\n if (a1 <= 0) return 0LL;\n while (a1 != v2 + 1) {\n v3 = 1;\n while (1) {\n ++v3;\n if (v3 * v3 > a1) break;\n if (v2 + v3 * v3 == a1) return 1LL;\n }\n ++v1;\n v2 = v1 * v1;\n if (v1 * v1 > a1) return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": 683, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int n) {\n int i = 1;\n while (i * i <= n) {\n int j = 1;\n while (j * j <= n) {\n if ((i * i + j * j) == n) {\n return true;\n }\n j++;\n }\n i++;\n }\n return false;\n}", + "test": "int main() {\n\n assert(func0(25) == true);\n\n assert(func0(24) == false);\n\n assert(func0(17) == true);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x1,%esi\nmov $0x1,%ecx\ntest %edi,%edi\njle 12ce \nlea 0x1(%rcx),%eax\ncmp %eax,%edi\nje 12d8 \nmov $0x1,%edx\njmp 12b6 \nadd %ecx,%eax\ncmp %edi,%eax\nje 12d8 \nadd $0x1,%edx\nmov %edx,%eax\nimul %edx,%eax\ncmp %edi,%eax\njle 12b0 \nadd $0x1,%esi\nmov %esi,%ecx\nimul %esi,%ecx\ncmp %edi,%ecx\njle 12a2 \nxor %eax,%eax\nretq\nnopl 0x0(%rax)\nmov $0x1,%eax\nretq\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\nmov esi, 1\nmov ecx, 1\ntest edi, edi\njle short loc_122E\nloc_1202:\nlea eax, [rcx+1]\ncmp edi, eax\njz short loc_1238\nmov edx, 1\njmp short loc_1216\nloc_1210:\nadd eax, ecx\ncmp eax, edi\njz short loc_1238\nloc_1216:\nadd edx, 1\nmov eax, edx\nimul eax, edx\ncmp eax, edi\njle short loc_1210\nadd esi, 1\nmov ecx, esi\nimul ecx, esi\ncmp ecx, edi\njle short loc_1202\nloc_122E:\nxor eax, eax\nretn\nloc_1238:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // esi\n int v2; // ecx\n int v3; // edx\n\n v1 = 1;\n v2 = 1;\n if ( a1 <= 0 )\n return 0LL;\n while ( a1 != v2 + 1 )\n {\n v3 = 1;\n while ( 1 )\n {\n ++v3;\n if ( v3 * v3 > a1 )\n break;\n if ( v2 + v3 * v3 == a1 )\n return 1LL;\n }\n ++v1;\n v2 = v1 * v1;\n if ( v1 * v1 > a1 )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_11F0:\nendbr64\nmov esi, 1\nmov ecx, 1\ntest edi, edi\njle short loc_122E\nloc_1202:\nlea eax, [rcx+1]\ncmp edi, eax\njz short loc_1238\nmov edx, 1\njmp short loc_1216\nloc_1210:\nadd eax, ecx\ncmp eax, edi\njz short loc_1238\nloc_1216:\nadd edx, 1\nmov eax, edx\nimul eax, edx\ncmp eax, edi\njle short loc_1210\nadd esi, 1\nmov ecx, esi\nimul ecx, esi\ncmp ecx, edi\njle short loc_1202\nloc_122E:\nxor eax, eax\nretn\nloc_1238:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11F0(int a1)\n{\n int v1; // esi\n int v2; // ecx\n int v3; // edx\n\n v1 = 1;\n v2 = 1;\n if ( a1 <= 0 )\n return 0LL;\n while ( a1 != v2 + 1 )\n {\n v3 = 1;\n while ( 1 )\n {\n ++v3;\n if ( v3 * v3 > a1 )\n break;\n if ( v2 + v3 * v3 == a1 )\n return 1LL;\n }\n ++v1;\n v2 = v1 * v1;\n if ( v1 * v1 > a1 )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11F0(int a1) {\n int v1;\n int v2;\n int v3;\n v1 = 1;\n v2 = 1;\n if (a1 <= 0) return 0LL;\n while (a1 != v2 + 1) {\n v3 = 1;\n while (1) {\n ++v3;\n if (v3 * v3 > a1) break;\n if (v2 + v3 * v3 == a1) return 1LL;\n }\n ++v1;\n v2 = v1 * v1;\n if (v1 * v1 > a1) return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v2;\n int v3;\n v1 = 1;\n v2 = 1;\n if (a1 <= 0) return 0LL;\n while (a1 != v2 + 1) {\n v3 = 1;\n while (1) {\n ++v3;\n if (v3 * v3 > a1) break;\n if (v2 + v3 * v3 == a1) return 1LL;\n }\n ++v1;\n v2 = v1 * v1;\n if (v1 * v1 > a1) return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": 684, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *str, char x) {\n int count = 0;\n int str_len = strlen(str);\n for (int i = 0; i < str_len; i++) {\n if (str[i] == x) {\n count += 1;\n }\n }\n int n = 10;\n int repetitions = n / str_len;\n count = count * repetitions;\n int l = n % str_len;\n for (int i = 0; i < l; i++) {\n if (str[i] == x) {\n count += 1;\n }\n }\n return count;\n}", + "test": "int main() {\n\n assert(func0(\"abcac\", 'a') == 4);\n\n assert(func0(\"abca\", 'c') == 2);\n\n assert(func0(\"aba\", 'a') == 7);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x28(%rbp)\nmov %esi,%eax\nmov %al,-0x2c(%rbp)\nmovl $0x0,-0x1c(%rbp)\nmov -0x28(%rbp),%rax\nmov %rax,%rdi\ncallq 1060 \nmov %eax,-0x10(%rbp)\nmovl $0x0,-0x18(%rbp)\njmp 11ba \nmov -0x18(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp %al,-0x2c(%rbp)\njne 11b6 \naddl $0x1,-0x1c(%rbp)\naddl $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%eax\ncmp -0x10(%rbp),%eax\njl 119d \nmovl $0xa,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncltd\nidivl -0x10(%rbp)\nmov %eax,-0x8(%rbp)\nmov -0x1c(%rbp),%eax\nimul -0x8(%rbp),%eax\nmov %eax,-0x1c(%rbp)\nmov -0xc(%rbp),%eax\ncltd\nidivl -0x10(%rbp)\nmov %edx,-0x4(%rbp)\nmovl $0x0,-0x14(%rbp)\njmp 120d \nmov -0x14(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp %al,-0x2c(%rbp)\njne 1209 \naddl $0x1,-0x1c(%rbp)\naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\ncmp -0x4(%rbp),%eax\njl 11f0 \nmov -0x1c(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov eax, esi\nmov [rbp+var_2C], al\nmov [rbp+var_1C], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_10], eax\nmov [rbp+var_18], 0\njmp short loc_11BA\nloc_119D:\nmov eax, [rbp+var_18]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp [rbp+var_2C], al\njnz short loc_11B6\nadd [rbp+var_1C], 1\nloc_11B6:\nadd [rbp+var_18], 1\nloc_11BA:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_10]\njl short loc_119D\nmov [rbp+var_C], 0Ah\nmov eax, [rbp+var_C]\ncdq\nidiv [rbp+var_10]\nmov [rbp+var_8], eax\nmov eax, [rbp+var_1C]\nimul eax, [rbp+var_8]\nmov [rbp+var_1C], eax\nmov eax, [rbp+var_C]\ncdq\nidiv [rbp+var_10]\nmov [rbp+var_4], edx\nmov [rbp+var_14], 0\njmp short loc_120D\nloc_11F0:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp [rbp+var_2C], al\njnz short loc_1209\nadd [rbp+var_1C], 1\nloc_1209:\nadd [rbp+var_14], 1\nloc_120D:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_4]\njl short loc_11F0\nmov eax, [rbp+var_1C]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, char a2)\n{\n int v3; // [rsp+14h] [rbp-1Ch]\n unsigned int v4; // [rsp+14h] [rbp-1Ch]\n int i; // [rsp+18h] [rbp-18h]\n int j; // [rsp+1Ch] [rbp-14h]\n int v7; // [rsp+20h] [rbp-10h]\n\n v3 = 0;\n v7 = strlen(a1);\n for ( i = 0; i < v7; ++i )\n {\n if ( a2 == a1[i] )\n ++v3;\n }\n v4 = 10 / v7 * v3;\n for ( j = 0; j < 10 % v7; ++j )\n {\n if ( a2 == a1[j] )\n ++v4;\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov eax, esi\nmov [rbp+var_2C], al\nmov [rbp+var_1C], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_10], eax\nmov [rbp+var_18], 0\njmp short loc_11BA\nloc_119D:\nmov eax, [rbp+var_18]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp [rbp+var_2C], al\njnz short loc_11B6\nadd [rbp+var_1C], 1\nloc_11B6:\nadd [rbp+var_18], 1\nloc_11BA:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_10]\njl short loc_119D\nmov [rbp+var_C], 0Ah\nmov eax, [rbp+var_C]\ncdq\nidiv [rbp+var_10]\nmov [rbp+var_8], eax\nmov eax, [rbp+var_1C]\nimul eax, [rbp+var_8]\nmov [rbp+var_1C], eax\nmov eax, [rbp+var_C]\ncdq\nidiv [rbp+var_10]\nmov [rbp+var_4], edx\nmov [rbp+var_14], 0\njmp short loc_120D\nloc_11F0:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp [rbp+var_2C], al\njnz short loc_1209\nadd [rbp+var_1C], 1\nloc_1209:\nadd [rbp+var_14], 1\nloc_120D:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_4]\njl short loc_11F0\nmov eax, [rbp+var_1C]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1, char a2)\n{\n int v3; // [rsp+14h] [rbp-1Ch]\n unsigned int v4; // [rsp+14h] [rbp-1Ch]\n int i; // [rsp+18h] [rbp-18h]\n int j; // [rsp+1Ch] [rbp-14h]\n int v7; // [rsp+20h] [rbp-10h]\n\n v3 = 0;\n v7 = strlen(a1);\n for ( i = 0; i < v7; ++i )\n {\n if ( a2 == a1[i] )\n ++v3;\n }\n v4 = 10 / v7 * v3;\n for ( j = 0; j < 10 % v7; ++j )\n {\n if ( a2 == a1[j] )\n ++v4;\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1, char a2) {\n int v3;\n unsigned int v4;\n int i;\n int j;\n int v7;\n v3 = 0;\n v7 = strlen(a1);\n for (i = 0; i < v7; ++i) {\n if (a2 == a1[i]) ++v3;\n }\n v4 = 10 / v7 * v3;\n for (j = 0; j < 10 % v7; ++j) {\n if (a2 == a1[j]) ++v4;\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, char a2) {\n int v3;\n unsigned int v4;\n int i;\n int j;\n int v7;\n v3 = 0;\n v7 = strlen(a1);\n for (i = 0; i < v7; ++i) {\n if (a2 == a1[i]) ++v3;\n }\n v4 = 10 / v7 * v3;\n for (j = 0; j < 10 % v7; ++j) {\n if (a2 == a1[j]) ++v4;\n }\n return v4;\n}" + }, + { + "index": 684, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *str, char x) {\n int count = 0;\n int str_len = strlen(str);\n for (int i = 0; i < str_len; i++) {\n if (str[i] == x) {\n count += 1;\n }\n }\n int n = 10;\n int repetitions = n / str_len;\n count = count * repetitions;\n int l = n % str_len;\n for (int i = 0; i < l; i++) {\n if (str[i] == x) {\n count += 1;\n }\n }\n return count;\n}", + "test": "int main() {\n\n assert(func0(\"abcac\", 'a') == 4);\n\n assert(func0(\"abca\", 'c') == 2);\n\n assert(func0(\"aba\", 'a') == 7);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%r8\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nsub $0x1,%rcx\nmov %ecx,%r9d\ntest %ecx,%ecx\njle 11c0 \nmov %r8,%rax\nlea -0x1(%rcx),%edx\nlea 0x1(%r8,%rdx,1),%rdi\nmov $0x0,%ecx\ncmp %sil,(%rax)\nsete %dl\nmovzbl %dl,%edx\nadd %edx,%ecx\nadd $0x1,%rax\ncmp %rdi,%rax\njne 117c \nmov $0xa,%eax\ncltd\nidiv %r9d\nimul %ecx,%eax\ntest %edx,%edx\njle 11bf \nmov %r8,%rcx\nlea -0x1(%rdx),%edx\nlea 0x1(%r8,%rdx,1),%rdi\ncmp %sil,(%rcx)\nsete %dl\nmovzbl %dl,%edx\nadd %edx,%eax\nadd $0x1,%rcx\ncmp %rdi,%rcx\njne 11ab \nretq\nmov $0x0,%ecx\njmp 1190 \n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov ebx, esi\ncall _strlen\nmov edi, eax\ntest eax, eax\njle short loc_11DC\nmov rdx, rbp\nlea eax, [rax-1]\nlea rsi, [rbp+rax+1]\nmov ecx, 0\nloc_1193:\ncmp [rdx], bl\nsetz al\nmovzx eax, al\nadd ecx, eax\nadd rdx, 1\ncmp rdx, rsi\njnz short loc_1193\nloc_11A6:\nmov eax, 0Ah\nmov edx, 0\nidiv edi\nimul eax, ecx\ntest edx, edx\njle short loc_11D5\nmov rcx, rbp\nmovsxd rdx, edx\nadd rbp, rdx\nloc_11C2:\ncmp [rcx], bl\nsetz dl\nmovzx edx, dl\nadd eax, edx\nadd rcx, 1\ncmp rcx, rbp\njnz short loc_11C2\nloc_11D5:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_11DC:\nmov ecx, 0\njmp short loc_11A6", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, unsigned __int8 a2)\n{\n int v3; // eax\n int v4; // edi\n const char *v5; // rdx\n int v6; // ecx\n __int64 result; // rax\n const char *v8; // rcx\n const char *v9; // rbp\n\n v3 = strlen(a1);\n v4 = v3;\n if ( v3 <= 0 )\n {\n v6 = 0;\n }\n else\n {\n v5 = a1;\n v6 = 0;\n do\n v6 += *v5++ == a2;\n while ( v5 != &a1[v3 - 1 + 1] );\n }\n result = (unsigned int)(v6 * (10 / v3));\n if ( 10 % v4 > 0 )\n {\n v8 = a1;\n v9 = &a1[10 % v4];\n do\n result = (*v8++ == a2) + (unsigned int)result;\n while ( v8 != v9 );\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov ebx, esi\ncall _strlen\nmov edi, eax\ntest eax, eax\njle short loc_11DC\nmov rdx, rbp\nlea eax, [rax-1]\nlea rsi, [rbp+rax+1]\nmov ecx, 0\nloc_1193:\ncmp [rdx], bl\nsetz al\nmovzx eax, al\nadd ecx, eax\nadd rdx, 1\ncmp rdx, rsi\njnz short loc_1193\nloc_11A6:\nmov eax, 0Ah\nmov edx, 0\nidiv edi\nimul eax, ecx\ntest edx, edx\njle short loc_11D5\nmov rcx, rbp\nmovsxd rdx, edx\nadd rbp, rdx\nloc_11C2:\ncmp [rcx], bl\nsetz dl\nmovzx edx, dl\nadd eax, edx\nadd rcx, 1\ncmp rcx, rbp\njnz short loc_11C2\nloc_11D5:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_11DC:\nmov ecx, 0\njmp short loc_11A6", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1, unsigned __int8 a2)\n{\n int v3; // eax\n int v4; // edi\n const char *v5; // rdx\n int v6; // ecx\n __int64 result; // rax\n const char *v8; // rcx\n const char *v9; // rbp\n\n v3 = strlen(a1);\n v4 = v3;\n if ( v3 <= 0 )\n {\n v6 = 0;\n }\n else\n {\n v5 = a1;\n v6 = 0;\n do\n v6 += *v5++ == a2;\n while ( v5 != &a1[v3 - 1 + 1] );\n }\n result = (unsigned int)(v6 * (10 / v3));\n if ( 10 % v4 > 0 )\n {\n v8 = a1;\n v9 = &a1[10 % v4];\n do\n result = (*v8++ == a2) + (unsigned int)result;\n while ( v8 != v9 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1, unsigned char a2) {\n int v3;\n int v4;\n const char *v5;\n int v6;\n long long result;\n const char *v8;\n const char *v9;\n v3 = strlen(a1);\n v4 = v3;\n if (v3 <= 0) {\n v6 = 0;\n } else {\n v5 = a1;\n v6 = 0;\n do\n v6 += *v5++ == a2;\n while (v5 != &a1[v3 - 1 + 1]);\n }\n result = (unsigned int)(v6 * (10 / v3));\n if (10 % v4 > 0) {\n v8 = a1;\n v9 = &a1[10 % v4];\n do\n result = (*v8++ == a2) + (unsigned int)result;\n while (v8 != v9);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, unsigned char a2) {\n int v3;\n int v4;\n const char *v5;\n int v6;\n long long result;\n const char *v8;\n const char *v9;\n v3 = strlen(a1);\n v4 = v3;\n if (v3 <= 0) {\n v6 = 0;\n } else {\n v5 = a1;\n v6 = 0;\n do\n v6 += *v5++ == a2;\n while (v5 != &a1[v3 - 1 + 1]);\n }\n result = (unsigned int)(v6 * (10 / v3));\n if (10 % v4 > 0) {\n v8 = a1;\n v9 = &a1[10 % v4];\n do\n result = (*v8++ == a2) + (unsigned int)result;\n while (v8 != v9);\n }\n return result;\n}" + }, + { + "index": 684, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *str, char x) {\n int count = 0;\n int str_len = strlen(str);\n for (int i = 0; i < str_len; i++) {\n if (str[i] == x) {\n count += 1;\n }\n }\n int n = 10;\n int repetitions = n / str_len;\n count = count * repetitions;\n int l = n % str_len;\n for (int i = 0; i < l; i++) {\n if (str[i] == x) {\n count += 1;\n }\n }\n return count;\n}", + "test": "int main() {\n\n assert(func0(\"abcac\", 'a') == 4);\n\n assert(func0(\"abca\", 'c') == 2);\n\n assert(func0(\"aba\", 'a') == 7);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %esi,%ebp\npush %rbx\nmov %rdi,%rbx\nsub $0x8,%rsp\ncallq 1060 \nmov %eax,%esi\ntest %eax,%eax\njle 12b0 \nsub $0x1,%eax\nmov %rbx,%rdx\nxor %r8d,%r8d\nlea 0x1(%rbx,%rax,1),%rcx\nnopl 0x0(%rax,%rax,1)\nxor %eax,%eax\ncmp %bpl,(%rdx)\nsete %al\nadd $0x1,%rdx\nadd %eax,%r8d\ncmp %rcx,%rdx\njne 1250 \nmov $0xa,%eax\ncltd\nidiv %esi\nimul %eax,%r8d\nmov $0xa,%eax\ncltd\nidiv %esi\ntest %edx,%edx\nje 12a4 \nlea -0x1(%rdx),%eax\nmov %rbx,%rdi\nlea 0x1(%rbx,%rax,1),%rdx\nnopw 0x0(%rax,%rax,1)\nxor %eax,%eax\ncmp %bpl,(%rdi)\nsete %al\nadd $0x1,%rdi\nadd %eax,%r8d\ncmp %rdi,%rdx\njne 1290 \nadd $0x8,%rsp\nmov %r8d,%eax\npop %rbx\npop %rbp\nretq\nxchg %ax,%ax\nxor %r8d,%r8d\njmp 1270 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov ebp, esi\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\nxor edx, edx\nmov rcx, rax\nmov r8d, eax\nmov eax, 0Ah\nidiv ecx\ntest ecx, ecx\njle short loc_12B0\nsub ecx, 1\nmov rdx, rbx\nlea rdi, [rbx+rcx+1]\nxor ecx, ecx\nnop dword ptr [rax+00h]\nloc_1258:\nxor esi, esi\ncmp bpl, [rdx]\nsetz sil\nadd rdx, 1\nadd ecx, esi\ncmp rdx, rdi\njnz short loc_1258\nimul eax, ecx\nmov esi, eax\nloc_1271:\nmov eax, 0Ah\nxor edx, edx\nidiv r8d\ntest edx, edx\njz short loc_12A3\nmovsxd rdx, edx\nmov rcx, rbx\nadd rdx, rbx\nnop dword ptr [rax+rax+00000000h]\nloc_1290:\nxor eax, eax\ncmp [rcx], bpl\nsetz al\nadd rcx, 1\nadd esi, eax\ncmp rdx, rcx\njnz short loc_1290\nloc_12A3:\nadd rsp, 8\nmov eax, esi\npop rbx\npop rbp\nretn\nloc_12B0:\nxor esi, esi\njmp short loc_1271", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, unsigned __int8 a2)\n{\n int v4; // ecx\n int v5; // r8d\n int v6; // eax\n const char *v7; // rdx\n __int64 v8; // rdi\n int v9; // ecx\n int v10; // esi\n unsigned int v11; // esi\n const char *v12; // rcx\n int v13; // eax\n\n v4 = strlen(a1);\n v5 = v4;\n v6 = 10 / v4;\n if ( v4 <= 0 )\n {\n v11 = 0;\n }\n else\n {\n v7 = a1;\n v8 = (__int64)&a1[v4 - 1 + 1];\n v9 = 0;\n do\n {\n v10 = a2 == *v7++;\n v9 += v10;\n }\n while ( v7 != (const char *)v8 );\n v11 = v9 * v6;\n }\n if ( 10 % v5 )\n {\n v12 = a1;\n do\n {\n v13 = *v12++ == a2;\n v11 += v13;\n }\n while ( &a1[10 % v5] != v12 );\n }\n return v11;\n}", + "ida_strip_asm": "sub_1220:\nendbr64\npush rbp\nmov ebp, esi\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\nxor edx, edx\nmov rcx, rax\nmov r8d, eax\nmov eax, 0Ah\nidiv ecx\ntest ecx, ecx\njle short loc_12B0\nsub ecx, 1\nmov rdx, rbx\nlea rdi, [rbx+rcx+1]\nxor ecx, ecx\nnop dword ptr [rax+00h]\nloc_1258:\nxor esi, esi\ncmp bpl, [rdx]\nsetz sil\nadd rdx, 1\nadd ecx, esi\ncmp rdx, rdi\njnz short loc_1258\nimul eax, ecx\nmov esi, eax\nloc_1271:\nmov eax, 0Ah\nxor edx, edx\nidiv r8d\ntest edx, edx\njz short loc_12A3\nmovsxd rdx, edx\nmov rcx, rbx\nadd rdx, rbx\nnop dword ptr [rax+rax+00000000h]\nloc_1290:\nxor eax, eax\ncmp [rcx], bpl\nsetz al\nadd rcx, 1\nadd esi, eax\ncmp rdx, rcx\njnz short loc_1290\nloc_12A3:\nadd rsp, 8\nmov eax, esi\npop rbx\npop rbp\nretn\nloc_12B0:\nxor esi, esi\njmp short loc_1271", + "ida_strip_pseudo": "__int64 __fastcall sub_1220(const char *a1, unsigned __int8 a2)\n{\n int v4; // ecx\n int v5; // r8d\n int v6; // eax\n const char *v7; // rdx\n __int64 v8; // rdi\n int v9; // ecx\n int v10; // esi\n unsigned int v11; // esi\n const char *v12; // rcx\n int v13; // eax\n\n v4 = strlen(a1);\n v5 = v4;\n v6 = 10 / v4;\n if ( v4 <= 0 )\n {\n v11 = 0;\n }\n else\n {\n v7 = a1;\n v8 = (__int64)&a1[v4 - 1 + 1];\n v9 = 0;\n do\n {\n v10 = a2 == *v7++;\n v9 += v10;\n }\n while ( v7 != (const char *)v8 );\n v11 = v9 * v6;\n }\n if ( 10 % v5 )\n {\n v12 = a1;\n do\n {\n v13 = *v12++ == a2;\n v11 += v13;\n }\n while ( &a1[10 % v5] != v12 );\n }\n return v11;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1220(const char *a1, unsigned char a2) {\n int v4;\n int v5;\n int v6;\n const char *v7;\n long long v8;\n int v9;\n int v10;\n unsigned int v11;\n const char *v12;\n int v13;\n v4 = strlen(a1);\n v5 = v4;\n v6 = 10 / v4;\n if (v4 <= 0) {\n v11 = 0;\n } else {\n v7 = a1;\n v8 = (long long)&a1[v4 - 1 + 1];\n v9 = 0;\n do {\n v10 = a2 == *v7++;\n v9 += v10;\n } while (v7 != (const char *)v8);\n v11 = v9 * v6;\n }\n if (10 % v5) {\n v12 = a1;\n do {\n v13 = *v12++ == a2;\n v11 += v13;\n } while (&a1[10 % v5] != v12);\n }\n return v11;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, unsigned char a2) {\n int v4;\n int v5;\n int v6;\n const char *v7;\n long long v8;\n int v9;\n int v10;\n unsigned int v11;\n const char *v12;\n int v13;\n v4 = strlen(a1);\n v5 = v4;\n v6 = 10 / v4;\n if (v4 <= 0) {\n v11 = 0;\n } else {\n v7 = a1;\n v8 = (long long)&a1[v4 - 1 + 1];\n v9 = 0;\n do {\n v10 = a2 == *v7++;\n v9 += v10;\n } while (v7 != (const char *)v8);\n v11 = v9 * v6;\n }\n if (10 % v5) {\n v12 = a1;\n do {\n v13 = *v12++ == a2;\n v11 += v13;\n } while (&a1[10 % v5] != v12);\n }\n return v11;\n}" + }, + { + "index": 684, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *str, char x) {\n int count = 0;\n int str_len = strlen(str);\n for (int i = 0; i < str_len; i++) {\n if (str[i] == x) {\n count += 1;\n }\n }\n int n = 10;\n int repetitions = n / str_len;\n count = count * repetitions;\n int l = n % str_len;\n for (int i = 0; i < l; i++) {\n if (str[i] == x) {\n count += 1;\n }\n }\n return count;\n}", + "test": "int main() {\n\n assert(func0(\"abcac\", 'a') == 4);\n\n assert(func0(\"abca\", 'c') == 2);\n\n assert(func0(\"aba\", 'a') == 7);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %esi,%ebp\npush %rbx\nmov %rdi,%rbx\nsub $0x8,%rsp\ncallq 1060 \nmov %eax,%esi\ntest %eax,%eax\njle 1570 \nlea -0x1(%rax),%edx\ncmp $0xe,%edx\njbe 1578 \nmovd %ebp,%xmm4\nmov %eax,%ecx\nmovdqa 0xe58(%rip),%xmm7\nmov %rbx,%rdx\npunpcklbw %xmm4,%xmm4\nshr $0x4,%ecx\npxor %xmm1,%xmm1\npxor %xmm6,%xmm6\npunpcklwd %xmm4,%xmm4\nshl $0x4,%rcx\npxor %xmm5,%xmm5\npshufd $0x0,%xmm4,%xmm4\nadd %rbx,%rcx\nxchg %ax,%ax\nmovdqu (%rdx),%xmm0\nmovdqa %xmm6,%xmm3\nadd $0x10,%rdx\npcmpeqb %xmm4,%xmm0\npand %xmm7,%xmm0\npcmpgtb %xmm0,%xmm3\nmovdqa %xmm0,%xmm2\npunpcklbw %xmm3,%xmm2\npunpckhbw %xmm3,%xmm0\nmovdqa %xmm5,%xmm3\npcmpgtw %xmm2,%xmm3\nmovdqa %xmm2,%xmm8\npunpcklwd %xmm3,%xmm8\npunpckhwd %xmm3,%xmm2\nmovdqa %xmm0,%xmm3\npaddd %xmm8,%xmm1\npaddd %xmm2,%xmm1\nmovdqa %xmm5,%xmm2\npcmpgtw %xmm0,%xmm2\npunpcklwd %xmm2,%xmm3\npunpckhwd %xmm2,%xmm0\npaddd %xmm3,%xmm1\npaddd %xmm0,%xmm1\ncmp %rcx,%rdx\njne 1280 \nmovdqa %xmm1,%xmm0\nmov %eax,%edx\npsrldq $0x8,%xmm0\nand $0xfffffff0,%edx\npaddd %xmm1,%xmm0\nmovdqa %xmm0,%xmm1\npsrldq $0x4,%xmm1\npaddd %xmm1,%xmm0\nmovd %xmm0,%ecx\ntest $0xf,%al\nje 1498 \nmovslq %edx,%rdi\ncmp %bpl,(%rbx,%rdi,1)\nsete %dil\nmovzbl %dil,%edi\nadd %edi,%ecx\nlea 0x1(%rdx),%edi\ncmp %edi,%eax\njle 1498 \nmovslq %edi,%rdi\ncmp %bpl,(%rbx,%rdi,1)\nsete %dil\nmovzbl %dil,%edi\nadd %edi,%ecx\nlea 0x2(%rdx),%edi\ncmp %edi,%eax\njle 1498 \nmovslq %edi,%rdi\ncmp %bpl,(%rbx,%rdi,1)\nsete %dil\nmovzbl %dil,%edi\nadd %edi,%ecx\nlea 0x3(%rdx),%edi\ncmp %edi,%eax\njle 1498 \nmovslq %edi,%rdi\ncmp %bpl,(%rbx,%rdi,1)\nsete %dil\nmovzbl %dil,%edi\nadd %edi,%ecx\nlea 0x4(%rdx),%edi\ncmp %edi,%eax\njle 1498 \nmovslq %edi,%rdi\ncmp %bpl,(%rbx,%rdi,1)\nsete %dil\nmovzbl %dil,%edi\nadd %edi,%ecx\nlea 0x5(%rdx),%edi\ncmp %edi,%eax\njle 1498 \nmovslq %edi,%rdi\ncmp %bpl,(%rbx,%rdi,1)\nsete %dil\nmovzbl %dil,%edi\nadd %edi,%ecx\nlea 0x6(%rdx),%edi\ncmp %edi,%eax\njle 1498 \nmovslq %edi,%rdi\ncmp %bpl,(%rbx,%rdi,1)\nsete %dil\nmovzbl %dil,%edi\nadd %edi,%ecx\nlea 0x7(%rdx),%edi\ncmp %edi,%eax\njle 1498 \nmovslq %edi,%rdi\ncmp %bpl,(%rbx,%rdi,1)\nsete %dil\nmovzbl %dil,%edi\nadd %edi,%ecx\nlea 0x8(%rdx),%edi\ncmp %edi,%eax\njle 1498 \nmovslq %edi,%rdi\ncmp %bpl,(%rbx,%rdi,1)\nsete %dil\nmovzbl %dil,%edi\nadd %edi,%ecx\nlea 0x9(%rdx),%edi\ncmp %edi,%eax\njle 1498 \nmovslq %edi,%rdi\ncmp %bpl,(%rbx,%rdi,1)\nsete %dil\nmovzbl %dil,%edi\nadd %edi,%ecx\nlea 0xa(%rdx),%edi\ncmp %edi,%eax\njle 1498 \nmovslq %edi,%rdi\ncmp %bpl,(%rbx,%rdi,1)\nsete %dil\nmovzbl %dil,%edi\nadd %edi,%ecx\nlea 0xb(%rdx),%edi\ncmp %edi,%eax\njle 1498 \nmovslq %edi,%rdi\ncmp %bpl,(%rbx,%rdi,1)\nsete %dil\nmovzbl %dil,%edi\nadd %edi,%ecx\nlea 0xc(%rdx),%edi\ncmp %edi,%eax\njle 1498 \nmovslq %edi,%rdi\ncmp %bpl,(%rbx,%rdi,1)\nsete %dil\nmovzbl %dil,%edi\nadd %edi,%ecx\nlea 0xd(%rdx),%edi\ncmp %edi,%eax\njle 1498 \nmovslq %edi,%rdi\ncmp %bpl,(%rbx,%rdi,1)\nsete %dil\nadd $0xe,%edx\nmovzbl %dil,%edi\nadd %edi,%ecx\ncmp %edx,%eax\njle 1498 \nmovslq %edx,%rdx\nxor %eax,%eax\ncmp %bpl,(%rbx,%rdx,1)\nsete %al\nadd %eax,%ecx\nnopl 0x0(%rax)\nmov $0xa,%eax\ncltd\nidiv %esi\nimul %ecx,%eax\nmov %eax,%r8d\nmov $0xa,%eax\ncltd\nidiv %esi\ntest %edx,%edx\nje 1562 \nxor %eax,%eax\ncmp %bpl,(%rbx)\nsete %al\nadd %eax,%r8d\ncmp $0x1,%edx\nje 1562 \nxor %eax,%eax\ncmp %bpl,0x1(%rbx)\nsete %al\nadd %eax,%r8d\ncmp $0x2,%edx\nje 1562 \nxor %eax,%eax\ncmp %bpl,0x2(%rbx)\nsete %al\nadd %eax,%r8d\ncmp $0x3,%edx\nje 1562 \nxor %eax,%eax\ncmp %bpl,0x3(%rbx)\nsete %al\nadd %eax,%r8d\ncmp $0x4,%edx\nje 1562 \nxor %eax,%eax\ncmp %bpl,0x4(%rbx)\nsete %al\nadd %eax,%r8d\ncmp $0x5,%edx\nje 1562 \nxor %eax,%eax\ncmp %bpl,0x5(%rbx)\nsete %al\nadd %eax,%r8d\ncmp $0x6,%edx\nje 1562 \nxor %eax,%eax\ncmp %bpl,0x6(%rbx)\nsete %al\nadd %eax,%r8d\ncmp $0x7,%edx\nje 1562 \nxor %eax,%eax\ncmp %bpl,0x7(%rbx)\nsete %al\nadd %eax,%r8d\ncmp $0x8,%edx\nje 1562 \nxor %eax,%eax\ncmp %bpl,0x8(%rbx)\nsete %al\nadd %eax,%r8d\ncmp $0xa,%edx\njne 1562 \nxor %eax,%eax\ncmp %bpl,0x9(%rbx)\nsete %al\nadd %eax,%r8d\nadd $0x8,%rsp\nmov %r8d,%eax\npop %rbx\npop %rbp\nretq\nnopl 0x0(%rax)\nxor %r8d,%r8d\njmpq 14a6 \nxor %edx,%edx\nxor %ecx,%ecx\njmpq 130f \nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov ebp, esi\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\nxor edx, edx\nmov rdi, rax\nmov esi, eax\nmov eax, 0Ah\nidiv edi\ntest edi, edi\njle loc_15E0\nlea edx, [rdi-1]\ncmp edx, 0Eh\njbe loc_15E7\nmovd xmm4, ebp\nmov ecx, edi\npxor xmm1, xmm1\nmov rdx, rbx\npunpcklbw xmm4, xmm4\nshr ecx, 4\npxor xmm6, xmm6\npxor xmm5, xmm5\npunpcklwd xmm4, xmm4\nshl rcx, 4\npshufd xmm4, xmm4, 0\nadd rcx, rbx\nnop word ptr [rax+rax+00h]\nloc_1288:\nmovdqu xmm0, xmmword ptr [rdx]\nmovdqa xmm3, xmm6\nadd rdx, 10h\npcmpeqb xmm0, xmm4\npcmpgtb xmm3, xmm0\nmovdqa xmm2, xmm0\npunpcklbw xmm2, xmm3\npunpckhbw xmm0, xmm3\nmovdqa xmm3, xmm5\npcmpgtw xmm3, xmm2\nmovdqa xmm7, xmm2\npunpcklwd xmm7, xmm3\npunpckhwd xmm2, xmm3\nmovdqa xmm3, xmm0\npsubd xmm1, xmm7\npsubd xmm1, xmm2\nmovdqa xmm2, xmm5\npcmpgtw xmm2, xmm0\npunpcklwd xmm3, xmm2\npunpckhwd xmm0, xmm2\npsubd xmm1, xmm3\npsubd xmm1, xmm0\ncmp rcx, rdx\njnz short loc_1288\nmovdqa xmm0, xmm1\nmov edx, edi\npsrldq xmm0, 8\nand edx, 0FFFFFFF0h\npaddd xmm0, xmm1\nmov r8d, edx\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\npaddd xmm0, xmm2\nmovd ecx, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm1, 8\npaddd xmm0, xmm1\ntest dil, 0Fh\njz loc_1455\nloc_1322:\nmov r9d, edi\nsub r9d, edx\nlea r10d, [r9-1]\ncmp r10d, 6\njbe loc_13CB\nmovq xmm1, qword ptr [rbx+rdx]\nmovzx edx, bpl\nmov dh, dl\nmovd xmm6, edx\npshuflw xmm2, xmm6, 0\npcmpeqb xmm1, xmm2\npxor xmm2, xmm2\npcmpgtb xmm2, xmm1\nmovdqa xmm3, xmm1\npunpcklbw xmm3, xmm2\npunpcklbw xmm1, xmm2\npxor xmm2, xmm2\nmovdqa xmm4, xmm2\nmovdqa xmm5, xmm3\npshufd xmm1, xmm1, 4Eh ; 'N'\npcmpgtw xmm4, xmm3\npcmpgtw xmm2, xmm1\npunpcklwd xmm5, xmm4\npunpcklwd xmm3, xmm4\npsubd xmm0, xmm5\npshufd xmm3, xmm3, 4Eh ; 'N'\npsubd xmm0, xmm3\nmovdqa xmm3, xmm1\npunpcklwd xmm1, xmm2\npunpcklwd xmm3, xmm2\npshufd xmm1, xmm1, 4Eh ; 'N'\npsubd xmm0, xmm3\npsubd xmm0, xmm1\nmovd ecx, xmm0\npshufd xmm6, xmm0, 0E5h\nmovd edx, xmm6\nadd ecx, edx\nmov edx, r9d\nand edx, 0FFFFFFF8h\nadd r8d, edx\nand r9d, 7\njz loc_1455\nloc_13CB:\nmovsxd rdx, r8d\ncmp bpl, [rbx+rdx]\njz loc_1570\nloc_13D8:\nlea edx, [r8+1]\ncmp edi, edx\njle short loc_1455\nmovsxd rdx, edx\ncmp bpl, [rbx+rdx]\njz loc_1588\nloc_13ED:\nlea edx, [r8+2]\ncmp edi, edx\njle short loc_1455\nmovsxd rdx, edx\ncmp bpl, [rbx+rdx]\njz loc_1598\nloc_1402:\nlea edx, [r8+3]\ncmp edi, edx\njle short loc_1455\nmovsxd rdx, edx\ncmp bpl, [rbx+rdx]\njz loc_15B0\nlea edx, [r8+4]\ncmp edi, edx\njle short loc_1455\nloc_141F:\nmovsxd rdx, edx\ncmp bpl, [rbx+rdx]\njnz short loc_142B\nadd ecx, 1\nloc_142B:\nlea edx, [r8+5]\ncmp edi, edx\njle short loc_1455\nmovsxd rdx, edx\ncmp bpl, [rbx+rdx]\njnz short loc_143F\nadd ecx, 1\nloc_143F:\nadd r8d, 6\ncmp edi, r8d\njle short loc_1455\nmovsxd r8, r8d\ncmp bpl, [rbx+r8]\njz loc_15D8\nloc_1455:\nimul ecx, eax\nloc_1458:\nmov eax, 0Ah\nxor edx, edx\nidiv esi\ntest edx, edx\njz loc_1565\nlea eax, [rdx-1]\ncmp eax, 6\njbe loc_15F7\nmovzx eax, bpl\nmovq xmm1, qword ptr [rbx]\npxor xmm2, xmm2\nmov ah, al\nmovdqa xmm4, xmm2\nmovd xmm6, eax\npshuflw xmm0, xmm6, 0\npcmpeqb xmm1, xmm0\npxor xmm0, xmm0\npcmpgtb xmm0, xmm1\nmovdqa xmm3, xmm1\npunpcklbw xmm3, xmm0\npunpcklbw xmm1, xmm0\nmovq xmm0, cs:qword_2088\npcmpgtw xmm4, xmm3\nmovdqa xmm5, xmm3\npshufd xmm1, xmm1, 4Eh ; 'N'\npcmpgtw xmm2, xmm1\npunpcklwd xmm5, xmm4\npunpcklwd xmm3, xmm4\npshufd xmm3, xmm3, 4Eh ; 'N'\npand xmm0, xmm5\npsubd xmm0, xmm3\nmovdqa xmm3, xmm1\npunpcklwd xmm1, xmm2\npunpcklwd xmm3, xmm2\npshufd xmm1, xmm1, 4Eh ; 'N'\npsubd xmm0, xmm3\npsubd xmm0, xmm1\nmovd esi, xmm0\npshufd xmm6, xmm0, 0E5h\nmovd eax, xmm6\nadd eax, esi\nadd ecx, eax\nmov eax, 8\ncmp edx, 8\njz short loc_1565\nloc_150A:\nmovsxd rsi, eax\ncmp [rbx+rsi], bpl\njnz short loc_1516\nadd ecx, 1\nloc_1516:\nlea esi, [rax+1]\ncmp edx, esi\njle short loc_1565\nmovsxd rsi, esi\ncmp bpl, [rbx+rsi]\njz short loc_1580\nloc_1526:\nadd eax, 2\ncmp eax, edx\njge short loc_1565\ncmp bpl, [rbx+2]\njz short loc_1590\nloc_1533:\ncmp edx, 3\njz short loc_1565\ncmp bpl, [rbx+3]\njz short loc_15A0\ncmp edx, 4\njz short loc_1565\nloc_1543:\ncmp bpl, [rbx+4]\njnz short loc_154C\nadd ecx, 1\nloc_154C:\ncmp edx, 5\njz short loc_1565\ncmp bpl, [rbx+5]\njnz short loc_155A\nadd ecx, 1\nloc_155A:\ncmp edx, 6\njz short loc_1565\ncmp bpl, [rbx+6]\njz short loc_15C8\nloc_1565:\nadd rsp, 8\nmov eax, ecx\npop rbx\npop rbp\nretn\nloc_1570:\nadd ecx, 1\njmp loc_13D8\nloc_1580:\nadd ecx, 1\njmp short loc_1526\nloc_1588:\nadd ecx, 1\njmp loc_13ED\nloc_1590:\nadd ecx, 1\njmp short loc_1533\nloc_1598:\nadd ecx, 1\njmp loc_1402\nloc_15A0:\nadd ecx, 1\ncmp edx, 4\njnz short loc_1543\njmp short loc_1565\nloc_15B0:\nlea edx, [r8+4]\nadd ecx, 1\ncmp edi, edx\njg loc_141F\njmp loc_1455\nloc_15C8:\nadd rsp, 8\nadd ecx, 1\nmov eax, ecx\npop rbx\npop rbp\nretn\nloc_15D8:\nadd ecx, 1\njmp loc_1455\nloc_15E0:\nxor ecx, ecx\njmp loc_1458\nloc_15E7:\npxor xmm0, xmm0\nxor edx, edx\nxor r8d, r8d\nxor ecx, ecx\njmp loc_1322\nloc_15F7:\nxor eax, eax\njmp loc_150A", + "ida_pseudo": "__int64 __fastcall func0(const __m128i *a1, unsigned __int8 a2)\n{\n int v3; // edi\n __m128i v4; // xmm4\n __m128i v5; // xmm1\n const __m128i *v6; // rdx\n __m128i v7; // xmm4\n __m128i v8; // xmm4\n __m128i v9; // xmm0\n __m128i v10; // xmm0\n __m128i v11; // xmm3\n __m128i v12; // xmm2\n __m128i v13; // xmm0\n __m128i v14; // xmm3\n __m128i v15; // xmm1\n __m128i v16; // xmm2\n __int64 v17; // rdx\n __m128i v18; // xmm0\n signed int v19; // r8d\n int v20; // ecx\n __m128i v21; // xmm0\n int v22; // r9d\n __m128i v23; // xmm1\n unsigned int v24; // edx\n __m128i v25; // xmm1\n __m128i v26; // xmm3\n __m128i v27; // xmm1\n __m128i v28; // xmm2\n __m128i v29; // xmm3\n __m128i v30; // xmm0\n int v31; // edx\n int v32; // r8d\n unsigned int v33; // ecx\n int v34; // edx\n unsigned int v35; // eax\n __m128i v36; // xmm1\n __m128i v37; // xmm3\n __m128i v38; // xmm1\n __m128i v39; // xmm2\n __m128i v40; // xmm5\n __m128i v41; // xmm0\n int v42; // eax\n\n v3 = strlen(a1->m128i_i8);\n if ( v3 > 0 )\n {\n if ( (unsigned int)(v3 - 1) <= 0xE )\n {\n v21 = 0LL;\n v17 = 0LL;\n v19 = 0;\n v20 = 0;\n }\n else\n {\n v4 = _mm_cvtsi32_si128(a2);\n v5 = 0LL;\n v6 = a1;\n v7 = _mm_unpacklo_epi8(v4, v4);\n v8 = _mm_shuffle_epi32(_mm_unpacklo_epi16(v7, v7), 0);\n do\n {\n v9 = _mm_loadu_si128(v6++);\n v10 = _mm_cmpeq_epi8(v9, v8);\n v11 = _mm_cmpgt_epi8((__m128i)0LL, v10);\n v12 = _mm_unpacklo_epi8(v10, v11);\n v13 = _mm_unpackhi_epi8(v10, v11);\n v14 = _mm_cmpgt_epi16((__m128i)0LL, v12);\n v15 = _mm_sub_epi32(_mm_sub_epi32(v5, _mm_unpacklo_epi16(v12, v14)), _mm_unpackhi_epi16(v12, v14));\n v16 = _mm_cmpgt_epi16((__m128i)0LL, v13);\n v5 = _mm_sub_epi32(_mm_sub_epi32(v15, _mm_unpacklo_epi16(v13, v16)), _mm_unpackhi_epi16(v13, v16));\n }\n while ( &a1[(unsigned int)v3 >> 4] != v6 );\n v17 = v3 & 0xFFFFFFF0;\n v18 = _mm_add_epi32(_mm_srli_si128(v5, 8), v5);\n v19 = v3 & 0xFFFFFFF0;\n v20 = _mm_cvtsi128_si32(_mm_add_epi32(v18, _mm_srli_si128(v18, 4)));\n v21 = _mm_add_epi32(v5, _mm_srli_si128(v5, 8));\n if ( (v3 & 0xF) == 0 )\n goto LABEL_27;\n }\n v22 = v3 - v17;\n if ( (unsigned int)(v3 - v17 - 1) > 6 )\n {\n v23 = _mm_loadl_epi64((const __m128i *)((char *)a1 + v17));\n v24 = a2;\n BYTE1(v24) = a2;\n v25 = _mm_cmpeq_epi8(v23, _mm_shufflelo_epi16(_mm_cvtsi32_si128(v24), 0));\n v26 = _mm_unpacklo_epi8(v25, _mm_cmpgt_epi8((__m128i)0LL, v25));\n v27 = _mm_shuffle_epi32(v26, 78);\n v28 = _mm_cmpgt_epi16((__m128i)0LL, v27);\n v29 = _mm_unpacklo_epi16(v26, _mm_cmpgt_epi16((__m128i)0LL, v26));\n v30 = _mm_sub_epi32(\n _mm_sub_epi32(\n _mm_sub_epi32(_mm_sub_epi32(v21, v29), _mm_shuffle_epi32(v29, 78)),\n _mm_unpacklo_epi16(v27, v28)),\n _mm_shuffle_epi32(_mm_unpacklo_epi16(v27, v28), 78));\n v20 = _mm_cvtsi128_si32(_mm_shuffle_epi32(v30, 229)) + _mm_cvtsi128_si32(v30);\n v19 += v22 & 0xFFFFFFF8;\n if ( (v22 & 7) == 0 )\n goto LABEL_27;\n }\n if ( a2 == a1->m128i_i8[v19] )\n ++v20;\n if ( v3 <= v19 + 1 )\n goto LABEL_27;\n if ( a2 == a1->m128i_i8[v19 + 1] )\n ++v20;\n if ( v3 <= v19 + 2 )\n goto LABEL_27;\n if ( a2 == a1->m128i_i8[v19 + 2] )\n ++v20;\n if ( v3 <= v19 + 3 )\n goto LABEL_27;\n if ( a2 == a1->m128i_i8[v19 + 3] )\n {\n v31 = v19 + 4;\n ++v20;\n if ( v3 > v19 + 4 )\n goto LABEL_19;\n }\n else\n {\n v31 = v19 + 4;\n if ( v3 > v19 + 4 )\n {\nLABEL_19:\n if ( a2 == a1->m128i_i8[v31] )\n ++v20;\n if ( v3 > v19 + 5 )\n {\n if ( a2 == a1->m128i_i8[v19 + 5] )\n ++v20;\n v32 = v19 + 6;\n if ( v3 > v32 && a2 == a1->m128i_i8[v32] )\n ++v20;\n }\n }\n }\nLABEL_27:\n v33 = 10 / v3 * v20;\n goto LABEL_28;\n }\n v33 = 0;\nLABEL_28:\n v34 = 10 % v3;\n if ( !(10 % v3) )\n return v33;\n if ( (unsigned int)(v34 - 1) <= 6 )\n {\n v42 = 0;\n }\n else\n {\n v35 = a2;\n BYTE1(v35) = a2;\n v36 = _mm_cmpeq_epi8(_mm_loadl_epi64(a1), _mm_shufflelo_epi16(_mm_cvtsi32_si128(v35), 0));\n v37 = _mm_unpacklo_epi8(v36, _mm_cmpgt_epi8((__m128i)0LL, v36));\n v38 = _mm_shuffle_epi32(v37, 78);\n v39 = _mm_cmpgt_epi16((__m128i)0LL, v38);\n v40 = _mm_unpacklo_epi16(v37, _mm_cmpgt_epi16((__m128i)0LL, v37));\n v41 = _mm_sub_epi32(\n _mm_sub_epi32(\n _mm_sub_epi32(\n _mm_and_si128(_mm_loadl_epi64((const __m128i *)&qword_2088), v40),\n _mm_shuffle_epi32(v40, 78)),\n _mm_unpacklo_epi16(v38, v39)),\n _mm_shuffle_epi32(_mm_unpacklo_epi16(v38, v39), 78));\n v33 += _mm_cvtsi128_si32(v41) + _mm_cvtsi128_si32(_mm_shuffle_epi32(v41, 229));\n v42 = 8;\n if ( v34 == 8 )\n return v33;\n }\n if ( a1->m128i_i8[v42] == a2 )\n ++v33;\n if ( v34 <= v42 + 1 )\n return v33;\n if ( a2 == a1->m128i_i8[v42 + 1] )\n ++v33;\n if ( v42 + 2 >= v34 )\n return v33;\n if ( a2 == a1->m128i_i8[2] )\n ++v33;\n if ( v34 == 3 )\n return v33;\n if ( a2 != a1->m128i_i8[3] )\n {\n if ( v34 != 4 )\n goto LABEL_42;\n return v33;\n }\n ++v33;\n if ( v34 == 4 )\n return v33;\nLABEL_42:\n if ( a2 == a1->m128i_i8[4] )\n ++v33;\n if ( v34 == 5 )\n return v33;\n if ( a2 == a1->m128i_i8[5] )\n ++v33;\n if ( v34 == 6 || a2 != a1->m128i_i8[6] )\n return v33;\n return v33 + 1;\n}", + "ida_strip_asm": "sub_1220:\nendbr64\npush rbp\nmov ebp, esi\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\nxor edx, edx\nmov rdi, rax\nmov esi, eax\nmov eax, 0Ah\nidiv edi\ntest edi, edi\njle loc_15E0\nlea edx, [rdi-1]\ncmp edx, 0Eh\njbe loc_15E7\nmovd xmm4, ebp\nmov ecx, edi\npxor xmm1, xmm1\nmov rdx, rbx\npunpcklbw xmm4, xmm4\nshr ecx, 4\npxor xmm6, xmm6\npxor xmm5, xmm5\npunpcklwd xmm4, xmm4\nshl rcx, 4\npshufd xmm4, xmm4, 0\nadd rcx, rbx\nnop word ptr [rax+rax+00h]\nloc_1288:\nmovdqu xmm0, xmmword ptr [rdx]\nmovdqa xmm3, xmm6\nadd rdx, 10h\npcmpeqb xmm0, xmm4\npcmpgtb xmm3, xmm0\nmovdqa xmm2, xmm0\npunpcklbw xmm2, xmm3\npunpckhbw xmm0, xmm3\nmovdqa xmm3, xmm5\npcmpgtw xmm3, xmm2\nmovdqa xmm7, xmm2\npunpcklwd xmm7, xmm3\npunpckhwd xmm2, xmm3\nmovdqa xmm3, xmm0\npsubd xmm1, xmm7\npsubd xmm1, xmm2\nmovdqa xmm2, xmm5\npcmpgtw xmm2, xmm0\npunpcklwd xmm3, xmm2\npunpckhwd xmm0, xmm2\npsubd xmm1, xmm3\npsubd xmm1, xmm0\ncmp rcx, rdx\njnz short loc_1288\nmovdqa xmm0, xmm1\nmov edx, edi\npsrldq xmm0, 8\nand edx, 0FFFFFFF0h\npaddd xmm0, xmm1\nmov r8d, edx\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\npaddd xmm0, xmm2\nmovd ecx, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm1, 8\npaddd xmm0, xmm1\ntest dil, 0Fh\njz loc_1455\nloc_1322:\nmov r9d, edi\nsub r9d, edx\nlea r10d, [r9-1]\ncmp r10d, 6\njbe loc_13CB\nmovq xmm1, qword ptr [rbx+rdx]\nmovzx edx, bpl\nmov dh, dl\nmovd xmm6, edx\npshuflw xmm2, xmm6, 0\npcmpeqb xmm1, xmm2\npxor xmm2, xmm2\npcmpgtb xmm2, xmm1\nmovdqa xmm3, xmm1\npunpcklbw xmm3, xmm2\npunpcklbw xmm1, xmm2\npxor xmm2, xmm2\nmovdqa xmm4, xmm2\nmovdqa xmm5, xmm3\npshufd xmm1, xmm1, 4Eh ; 'N'\npcmpgtw xmm4, xmm3\npcmpgtw xmm2, xmm1\npunpcklwd xmm5, xmm4\npunpcklwd xmm3, xmm4\npsubd xmm0, xmm5\npshufd xmm3, xmm3, 4Eh ; 'N'\npsubd xmm0, xmm3\nmovdqa xmm3, xmm1\npunpcklwd xmm1, xmm2\npunpcklwd xmm3, xmm2\npshufd xmm1, xmm1, 4Eh ; 'N'\npsubd xmm0, xmm3\npsubd xmm0, xmm1\nmovd ecx, xmm0\npshufd xmm6, xmm0, 0E5h\nmovd edx, xmm6\nadd ecx, edx\nmov edx, r9d\nand edx, 0FFFFFFF8h\nadd r8d, edx\nand r9d, 7\njz loc_1455\nloc_13CB:\nmovsxd rdx, r8d\ncmp bpl, [rbx+rdx]\njz loc_1570\nloc_13D8:\nlea edx, [r8+1]\ncmp edi, edx\njle short loc_1455\nmovsxd rdx, edx\ncmp bpl, [rbx+rdx]\njz loc_1588\nloc_13ED:\nlea edx, [r8+2]\ncmp edi, edx\njle short loc_1455\nmovsxd rdx, edx\ncmp bpl, [rbx+rdx]\njz loc_1598\nloc_1402:\nlea edx, [r8+3]\ncmp edi, edx\njle short loc_1455\nmovsxd rdx, edx\ncmp bpl, [rbx+rdx]\njz loc_15B0\nlea edx, [r8+4]\ncmp edi, edx\njle short loc_1455\nloc_141F:\nmovsxd rdx, edx\ncmp bpl, [rbx+rdx]\njnz short loc_142B\nadd ecx, 1\nloc_142B:\nlea edx, [r8+5]\ncmp edi, edx\njle short loc_1455\nmovsxd rdx, edx\ncmp bpl, [rbx+rdx]\njnz short loc_143F\nadd ecx, 1\nloc_143F:\nadd r8d, 6\ncmp edi, r8d\njle short loc_1455\nmovsxd r8, r8d\ncmp bpl, [rbx+r8]\njz loc_15D8\nloc_1455:\nimul ecx, eax\nloc_1458:\nmov eax, 0Ah\nxor edx, edx\nidiv esi\ntest edx, edx\njz loc_1565\nlea eax, [rdx-1]\ncmp eax, 6\njbe loc_15F7\nmovzx eax, bpl\nmovq xmm1, qword ptr [rbx]\npxor xmm2, xmm2\nmov ah, al\nmovdqa xmm4, xmm2\nmovd xmm6, eax\npshuflw xmm0, xmm6, 0\npcmpeqb xmm1, xmm0\npxor xmm0, xmm0\npcmpgtb xmm0, xmm1\nmovdqa xmm3, xmm1\npunpcklbw xmm3, xmm0\npunpcklbw xmm1, xmm0\nmovq xmm0, cs:qword_2088\npcmpgtw xmm4, xmm3\nmovdqa xmm5, xmm3\npshufd xmm1, xmm1, 4Eh ; 'N'\npcmpgtw xmm2, xmm1\npunpcklwd xmm5, xmm4\npunpcklwd xmm3, xmm4\npshufd xmm3, xmm3, 4Eh ; 'N'\npand xmm0, xmm5\npsubd xmm0, xmm3\nmovdqa xmm3, xmm1\npunpcklwd xmm1, xmm2\npunpcklwd xmm3, xmm2\npshufd xmm1, xmm1, 4Eh ; 'N'\npsubd xmm0, xmm3\npsubd xmm0, xmm1\nmovd esi, xmm0\npshufd xmm6, xmm0, 0E5h\nmovd eax, xmm6\nadd eax, esi\nadd ecx, eax\nmov eax, 8\ncmp edx, 8\njz short loc_1565\nloc_150A:\nmovsxd rsi, eax\ncmp [rbx+rsi], bpl\njnz short loc_1516\nadd ecx, 1\nloc_1516:\nlea esi, [rax+1]\ncmp edx, esi\njle short loc_1565\nmovsxd rsi, esi\ncmp bpl, [rbx+rsi]\njz short loc_1580\nloc_1526:\nadd eax, 2\ncmp eax, edx\njge short loc_1565\ncmp bpl, [rbx+2]\njz short loc_1590\nloc_1533:\ncmp edx, 3\njz short loc_1565\ncmp bpl, [rbx+3]\njz short loc_15A0\ncmp edx, 4\njz short loc_1565\nloc_1543:\ncmp bpl, [rbx+4]\njnz short loc_154C\nadd ecx, 1\nloc_154C:\ncmp edx, 5\njz short loc_1565\ncmp bpl, [rbx+5]\njnz short loc_155A\nadd ecx, 1\nloc_155A:\ncmp edx, 6\njz short loc_1565\ncmp bpl, [rbx+6]\njz short loc_15C8\nloc_1565:\nadd rsp, 8\nmov eax, ecx\npop rbx\npop rbp\nretn\nloc_1570:\nadd ecx, 1\njmp loc_13D8\nloc_1580:\nadd ecx, 1\njmp short loc_1526\nloc_1588:\nadd ecx, 1\njmp loc_13ED\nloc_1590:\nadd ecx, 1\njmp short loc_1533\nloc_1598:\nadd ecx, 1\njmp loc_1402\nloc_15A0:\nadd ecx, 1\ncmp edx, 4\njnz short loc_1543\njmp short loc_1565\nloc_15B0:\nlea edx, [r8+4]\nadd ecx, 1\ncmp edi, edx\njg loc_141F\njmp loc_1455\nloc_15C8:\nadd rsp, 8\nadd ecx, 1\nmov eax, ecx\npop rbx\npop rbp\nretn\nloc_15D8:\nadd ecx, 1\njmp loc_1455\nloc_15E0:\nxor ecx, ecx\njmp loc_1458\nloc_15E7:\npxor xmm0, xmm0\nxor edx, edx\nxor r8d, r8d\nxor ecx, ecx\njmp loc_1322\nloc_15F7:\nxor eax, eax\njmp loc_150A", + "ida_strip_pseudo": "__int64 __fastcall sub_1220(const __m128i *a1, unsigned __int8 a2)\n{\n int v3; // edi\n __m128i v4; // xmm4\n __m128i v5; // xmm1\n const __m128i *v6; // rdx\n __m128i v7; // xmm4\n __m128i v8; // xmm4\n __m128i v9; // xmm0\n __m128i v10; // xmm0\n __m128i v11; // xmm3\n __m128i v12; // xmm2\n __m128i v13; // xmm0\n __m128i v14; // xmm3\n __m128i v15; // xmm1\n __m128i v16; // xmm2\n __int64 v17; // rdx\n __m128i v18; // xmm0\n signed int v19; // r8d\n int v20; // ecx\n __m128i v21; // xmm0\n int v22; // r9d\n __m128i v23; // xmm1\n unsigned int v24; // edx\n __m128i v25; // xmm1\n __m128i v26; // xmm3\n __m128i v27; // xmm1\n __m128i v28; // xmm2\n __m128i v29; // xmm3\n __m128i v30; // xmm0\n int v31; // edx\n int v32; // r8d\n unsigned int v33; // ecx\n int v34; // edx\n unsigned int v35; // eax\n __m128i v36; // xmm1\n __m128i v37; // xmm3\n __m128i v38; // xmm1\n __m128i v39; // xmm2\n __m128i v40; // xmm5\n __m128i v41; // xmm0\n int v42; // eax\n\n v3 = strlen(a1->m128i_i8);\n if ( v3 > 0 )\n {\n if ( (unsigned int)(v3 - 1) <= 0xE )\n {\n v21 = 0LL;\n v17 = 0LL;\n v19 = 0;\n v20 = 0;\n }\n else\n {\n v4 = _mm_cvtsi32_si128(a2);\n v5 = 0LL;\n v6 = a1;\n v7 = _mm_unpacklo_epi8(v4, v4);\n v8 = _mm_shuffle_epi32(_mm_unpacklo_epi16(v7, v7), 0);\n do\n {\n v9 = _mm_loadu_si128(v6++);\n v10 = _mm_cmpeq_epi8(v9, v8);\n v11 = _mm_cmpgt_epi8((__m128i)0LL, v10);\n v12 = _mm_unpacklo_epi8(v10, v11);\n v13 = _mm_unpackhi_epi8(v10, v11);\n v14 = _mm_cmpgt_epi16((__m128i)0LL, v12);\n v15 = _mm_sub_epi32(_mm_sub_epi32(v5, _mm_unpacklo_epi16(v12, v14)), _mm_unpackhi_epi16(v12, v14));\n v16 = _mm_cmpgt_epi16((__m128i)0LL, v13);\n v5 = _mm_sub_epi32(_mm_sub_epi32(v15, _mm_unpacklo_epi16(v13, v16)), _mm_unpackhi_epi16(v13, v16));\n }\n while ( &a1[(unsigned int)v3 >> 4] != v6 );\n v17 = v3 & 0xFFFFFFF0;\n v18 = _mm_add_epi32(_mm_srli_si128(v5, 8), v5);\n v19 = v3 & 0xFFFFFFF0;\n v20 = _mm_cvtsi128_si32(_mm_add_epi32(v18, _mm_srli_si128(v18, 4)));\n v21 = _mm_add_epi32(v5, _mm_srli_si128(v5, 8));\n if ( (v3 & 0xF) == 0 )\n goto LABEL_27;\n }\n v22 = v3 - v17;\n if ( (unsigned int)(v3 - v17 - 1) > 6 )\n {\n v23 = _mm_loadl_epi64((const __m128i *)((char *)a1 + v17));\n v24 = a2;\n BYTE1(v24) = a2;\n v25 = _mm_cmpeq_epi8(v23, _mm_shufflelo_epi16(_mm_cvtsi32_si128(v24), 0));\n v26 = _mm_unpacklo_epi8(v25, _mm_cmpgt_epi8((__m128i)0LL, v25));\n v27 = _mm_shuffle_epi32(v26, 78);\n v28 = _mm_cmpgt_epi16((__m128i)0LL, v27);\n v29 = _mm_unpacklo_epi16(v26, _mm_cmpgt_epi16((__m128i)0LL, v26));\n v30 = _mm_sub_epi32(\n _mm_sub_epi32(\n _mm_sub_epi32(_mm_sub_epi32(v21, v29), _mm_shuffle_epi32(v29, 78)),\n _mm_unpacklo_epi16(v27, v28)),\n _mm_shuffle_epi32(_mm_unpacklo_epi16(v27, v28), 78));\n v20 = _mm_cvtsi128_si32(_mm_shuffle_epi32(v30, 229)) + _mm_cvtsi128_si32(v30);\n v19 += v22 & 0xFFFFFFF8;\n if ( (v22 & 7) == 0 )\n goto LABEL_27;\n }\n if ( a2 == a1->m128i_i8[v19] )\n ++v20;\n if ( v3 <= v19 + 1 )\n goto LABEL_27;\n if ( a2 == a1->m128i_i8[v19 + 1] )\n ++v20;\n if ( v3 <= v19 + 2 )\n goto LABEL_27;\n if ( a2 == a1->m128i_i8[v19 + 2] )\n ++v20;\n if ( v3 <= v19 + 3 )\n goto LABEL_27;\n if ( a2 == a1->m128i_i8[v19 + 3] )\n {\n v31 = v19 + 4;\n ++v20;\n if ( v3 > v19 + 4 )\n goto LABEL_19;\n }\n else\n {\n v31 = v19 + 4;\n if ( v3 > v19 + 4 )\n {\nLABEL_19:\n if ( a2 == a1->m128i_i8[v31] )\n ++v20;\n if ( v3 > v19 + 5 )\n {\n if ( a2 == a1->m128i_i8[v19 + 5] )\n ++v20;\n v32 = v19 + 6;\n if ( v3 > v32 && a2 == a1->m128i_i8[v32] )\n ++v20;\n }\n }\n }\nLABEL_27:\n v33 = 10 / v3 * v20;\n goto LABEL_28;\n }\n v33 = 0;\nLABEL_28:\n v34 = 10 % v3;\n if ( !(10 % v3) )\n return v33;\n if ( (unsigned int)(v34 - 1) <= 6 )\n {\n v42 = 0;\n }\n else\n {\n v35 = a2;\n BYTE1(v35) = a2;\n v36 = _mm_cmpeq_epi8(_mm_loadl_epi64(a1), _mm_shufflelo_epi16(_mm_cvtsi32_si128(v35), 0));\n v37 = _mm_unpacklo_epi8(v36, _mm_cmpgt_epi8((__m128i)0LL, v36));\n v38 = _mm_shuffle_epi32(v37, 78);\n v39 = _mm_cmpgt_epi16((__m128i)0LL, v38);\n v40 = _mm_unpacklo_epi16(v37, _mm_cmpgt_epi16((__m128i)0LL, v37));\n v41 = _mm_sub_epi32(\n _mm_sub_epi32(\n _mm_sub_epi32(\n _mm_and_si128(_mm_loadl_epi64((const __m128i *)&qword_2088), v40),\n _mm_shuffle_epi32(v40, 78)),\n _mm_unpacklo_epi16(v38, v39)),\n _mm_shuffle_epi32(_mm_unpacklo_epi16(v38, v39), 78));\n v33 += _mm_cvtsi128_si32(v41) + _mm_cvtsi128_si32(_mm_shuffle_epi32(v41, 229));\n v42 = 8;\n if ( v34 == 8 )\n return v33;\n }\n if ( a1->m128i_i8[v42] == a2 )\n ++v33;\n if ( v34 <= v42 + 1 )\n return v33;\n if ( a2 == a1->m128i_i8[v42 + 1] )\n ++v33;\n if ( v42 + 2 >= v34 )\n return v33;\n if ( a2 == a1->m128i_i8[2] )\n ++v33;\n if ( v34 == 3 )\n return v33;\n if ( a2 != a1->m128i_i8[3] )\n {\n if ( v34 != 4 )\n goto LABEL_42;\n return v33;\n }\n ++v33;\n if ( v34 == 4 )\n return v33;\nLABEL_42:\n if ( a2 == a1->m128i_i8[4] )\n ++v33;\n if ( v34 == 5 )\n return v33;\n if ( a2 == a1->m128i_i8[5] )\n ++v33;\n if ( v34 == 6 || a2 != a1->m128i_i8[6] )\n return v33;\n return v33 + 1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1220(const __m128i *a1, unsigned char a2) {\n int v3;\n __m128i v4;\n __m128i v5;\n const __m128i *v6;\n __m128i v7;\n __m128i v8;\n __m128i v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n __m128i v15;\n __m128i v16;\n long long v17;\n __m128i v18;\n signed int v19;\n int v20;\n __m128i v21;\n int v22;\n __m128i v23;\n unsigned int v24;\n __m128i v25;\n __m128i v26;\n __m128i v27;\n __m128i v28;\n __m128i v29;\n __m128i v30;\n int v31;\n int v32;\n unsigned int v33;\n int v34;\n unsigned int v35;\n __m128i v36;\n __m128i v37;\n __m128i v38;\n __m128i v39;\n __m128i v40;\n __m128i v41;\n int v42;\n v3 = strlen(a1->m128i_i8);\n if (v3 > 0) {\n if ((unsigned int)(v3 - 1) <= 14) {\n v21 = 0LL;\n v17 = 0LL;\n v19 = 0;\n v20 = 0;\n } else {\n v4 = _mm_cvtsi32_si128(a2);\n v5 = 0LL;\n v6 = a1;\n v7 = _mm_unpacklo_epi8(v4, v4);\n v8 = _mm_shuffle_epi32(_mm_unpacklo_epi16(v7, v7), 0);\n do {\n v9 = _mm_loadu_si128(v6++);\n v10 = _mm_cmpeq_epi8(v9, v8);\n v11 = _mm_cmpgt_epi8((__m128i)0LL, v10);\n v12 = _mm_unpacklo_epi8(v10, v11);\n v13 = _mm_unpackhi_epi8(v10, v11);\n v14 = _mm_cmpgt_epi16((__m128i)0LL, v12);\n v15 = _mm_sub_epi32(_mm_sub_epi32(v5, _mm_unpacklo_epi16(v12, v14)),\n _mm_unpackhi_epi16(v12, v14));\n v16 = _mm_cmpgt_epi16((__m128i)0LL, v13);\n v5 = _mm_sub_epi32(_mm_sub_epi32(v15, _mm_unpacklo_epi16(v13, v16)),\n _mm_unpackhi_epi16(v13, v16));\n } while (&a1[(unsigned int)v3 >> 4] != v6);\n v17 = v3 & 4294967280;\n v18 = _mm_add_epi32(_mm_srli_si128(v5, 8), v5);\n v19 = v3 & 4294967280;\n v20 = _mm_cvtsi128_si32(_mm_add_epi32(v18, _mm_srli_si128(v18, 4)));\n v21 = _mm_add_epi32(v5, _mm_srli_si128(v5, 8));\n if ((v3 & 15) == 0) goto LABEL_27;\n }\n v22 = v3 - v17;\n if ((unsigned int)(v3 - v17 - 1) > 6) {\n v23 = _mm_loadl_epi64((const __m128i *)((char *)a1 + v17));\n v24 = a2;\n BYTE1(v24) = a2;\n v25 = _mm_cmpeq_epi8(v23, _mm_shufflelo_epi16(_mm_cvtsi32_si128(v24), 0));\n v26 = _mm_unpacklo_epi8(v25, _mm_cmpgt_epi8((__m128i)0LL, v25));\n v27 = _mm_shuffle_epi32(v26, 78);\n v28 = _mm_cmpgt_epi16((__m128i)0LL, v27);\n v29 = _mm_unpacklo_epi16(v26, _mm_cmpgt_epi16((__m128i)0LL, v26));\n v30 =\n _mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(v21, v29),\n _mm_shuffle_epi32(v29, 78)),\n _mm_unpacklo_epi16(v27, v28)),\n _mm_shuffle_epi32(_mm_unpacklo_epi16(v27, v28), 78));\n v20 = _mm_cvtsi128_si32(_mm_shuffle_epi32(v30, 229)) +\n _mm_cvtsi128_si32(v30);\n v19 += v22 & 4294967288;\n if ((v22 & 7) == 0) goto LABEL_27;\n }\n if (a2 == a1->m128i_i8[v19]) ++v20;\n if (v3 <= v19 + 1) goto LABEL_27;\n if (a2 == a1->m128i_i8[v19 + 1]) ++v20;\n if (v3 <= v19 + 2) goto LABEL_27;\n if (a2 == a1->m128i_i8[v19 + 2]) ++v20;\n if (v3 <= v19 + 3) goto LABEL_27;\n if (a2 == a1->m128i_i8[v19 + 3]) {\n v31 = v19 + 4;\n ++v20;\n if (v3 > v19 + 4) goto LABEL_19;\n } else {\n v31 = v19 + 4;\n if (v3 > v19 + 4) {\n LABEL_19:\n if (a2 == a1->m128i_i8[v31]) ++v20;\n if (v3 > v19 + 5) {\n if (a2 == a1->m128i_i8[v19 + 5]) ++v20;\n v32 = v19 + 6;\n if (v3 > v32 && a2 == a1->m128i_i8[v32]) ++v20;\n }\n }\n }\n LABEL_27:\n v33 = 10 / v3 * v20;\n goto LABEL_28;\n }\n v33 = 0;\nLABEL_28:\n v34 = 10 % v3;\n if (!(10 % v3)) return v33;\n if ((unsigned int)(v34 - 1) <= 6) {\n v42 = 0;\n } else {\n v35 = a2;\n BYTE1(v35) = a2;\n v36 = _mm_cmpeq_epi8(_mm_loadl_epi64(a1),\n _mm_shufflelo_epi16(_mm_cvtsi32_si128(v35), 0));\n v37 = _mm_unpacklo_epi8(v36, _mm_cmpgt_epi8((__m128i)0LL, v36));\n v38 = _mm_shuffle_epi32(v37, 78);\n v39 = _mm_cmpgt_epi16((__m128i)0LL, v38);\n v40 = _mm_unpacklo_epi16(v37, _mm_cmpgt_epi16((__m128i)0LL, v37));\n v41 = _mm_sub_epi32(\n _mm_sub_epi32(\n _mm_sub_epi32(\n _mm_and_si128(_mm_loadl_epi64((const __m128i *)&qword_2088),\n v40),\n _mm_shuffle_epi32(v40, 78)),\n _mm_unpacklo_epi16(v38, v39)),\n _mm_shuffle_epi32(_mm_unpacklo_epi16(v38, v39), 78));\n v33 +=\n _mm_cvtsi128_si32(v41) + _mm_cvtsi128_si32(_mm_shuffle_epi32(v41, 229));\n v42 = 8;\n if (v34 == 8) return v33;\n }\n if (a1->m128i_i8[v42] == a2) ++v33;\n if (v34 <= v42 + 1) return v33;\n if (a2 == a1->m128i_i8[v42 + 1]) ++v33;\n if (v42 + 2 >= v34) return v33;\n if (a2 == a1->m128i_i8[2]) ++v33;\n if (v34 == 3) return v33;\n if (a2 != a1->m128i_i8[3]) {\n if (v34 != 4) goto LABEL_42;\n return v33;\n }\n ++v33;\n if (v34 == 4) return v33;\nLABEL_42:\n if (a2 == a1->m128i_i8[4]) ++v33;\n if (v34 == 5) return v33;\n if (a2 == a1->m128i_i8[5]) ++v33;\n if (v34 == 6 || a2 != a1->m128i_i8[6]) return v33;\n return v33 + 1;\n}", + "ida_pseudo_norm": "long long func0(const __m128i *a1, unsigned char a2) {\n int v3;\n __m128i v4;\n __m128i v5;\n const __m128i *v6;\n __m128i v7;\n __m128i v8;\n __m128i v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n __m128i v15;\n __m128i v16;\n long long v17;\n __m128i v18;\n signed int v19;\n int v20;\n __m128i v21;\n int v22;\n __m128i v23;\n unsigned int v24;\n __m128i v25;\n __m128i v26;\n __m128i v27;\n __m128i v28;\n __m128i v29;\n __m128i v30;\n int v31;\n int v32;\n unsigned int v33;\n int v34;\n unsigned int v35;\n __m128i v36;\n __m128i v37;\n __m128i v38;\n __m128i v39;\n __m128i v40;\n __m128i v41;\n int v42;\n v3 = strlen(a1->m128i_i8);\n if (v3 > 0) {\n if ((unsigned int)(v3 - 1) <= 14) {\n v21 = 0LL;\n v17 = 0LL;\n v19 = 0;\n v20 = 0;\n } else {\n v4 = _mm_cvtsi32_si128(a2);\n v5 = 0LL;\n v6 = a1;\n v7 = _mm_unpacklo_epi8(v4, v4);\n v8 = _mm_shuffle_epi32(_mm_unpacklo_epi16(v7, v7), 0);\n do {\n v9 = _mm_loadu_si128(v6++);\n v10 = _mm_cmpeq_epi8(v9, v8);\n v11 = _mm_cmpgt_epi8((__m128i)0LL, v10);\n v12 = _mm_unpacklo_epi8(v10, v11);\n v13 = _mm_unpackhi_epi8(v10, v11);\n v14 = _mm_cmpgt_epi16((__m128i)0LL, v12);\n v15 = _mm_sub_epi32(_mm_sub_epi32(v5, _mm_unpacklo_epi16(v12, v14)),\n _mm_unpackhi_epi16(v12, v14));\n v16 = _mm_cmpgt_epi16((__m128i)0LL, v13);\n v5 = _mm_sub_epi32(_mm_sub_epi32(v15, _mm_unpacklo_epi16(v13, v16)),\n _mm_unpackhi_epi16(v13, v16));\n } while (&a1[(unsigned int)v3 >> 4] != v6);\n v17 = v3 & 4294967280;\n v18 = _mm_add_epi32(_mm_srli_si128(v5, 8), v5);\n v19 = v3 & 4294967280;\n v20 = _mm_cvtsi128_si32(_mm_add_epi32(v18, _mm_srli_si128(v18, 4)));\n v21 = _mm_add_epi32(v5, _mm_srli_si128(v5, 8));\n if ((v3 & 15) == 0) goto LABEL_27;\n }\n v22 = v3 - v17;\n if ((unsigned int)(v3 - v17 - 1) > 6) {\n v23 = _mm_loadl_epi64((const __m128i *)((char *)a1 + v17));\n v24 = a2;\n BYTE1(v24) = a2;\n v25 = _mm_cmpeq_epi8(v23, _mm_shufflelo_epi16(_mm_cvtsi32_si128(v24), 0));\n v26 = _mm_unpacklo_epi8(v25, _mm_cmpgt_epi8((__m128i)0LL, v25));\n v27 = _mm_shuffle_epi32(v26, 78);\n v28 = _mm_cmpgt_epi16((__m128i)0LL, v27);\n v29 = _mm_unpacklo_epi16(v26, _mm_cmpgt_epi16((__m128i)0LL, v26));\n v30 =\n _mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(v21, v29),\n _mm_shuffle_epi32(v29, 78)),\n _mm_unpacklo_epi16(v27, v28)),\n _mm_shuffle_epi32(_mm_unpacklo_epi16(v27, v28), 78));\n v20 = _mm_cvtsi128_si32(_mm_shuffle_epi32(v30, 229)) +\n _mm_cvtsi128_si32(v30);\n v19 += v22 & 4294967288;\n if ((v22 & 7) == 0) goto LABEL_27;\n }\n if (a2 == a1->m128i_i8[v19]) ++v20;\n if (v3 <= v19 + 1) goto LABEL_27;\n if (a2 == a1->m128i_i8[v19 + 1]) ++v20;\n if (v3 <= v19 + 2) goto LABEL_27;\n if (a2 == a1->m128i_i8[v19 + 2]) ++v20;\n if (v3 <= v19 + 3) goto LABEL_27;\n if (a2 == a1->m128i_i8[v19 + 3]) {\n v31 = v19 + 4;\n ++v20;\n if (v3 > v19 + 4) goto LABEL_19;\n } else {\n v31 = v19 + 4;\n if (v3 > v19 + 4) {\n LABEL_19:\n if (a2 == a1->m128i_i8[v31]) ++v20;\n if (v3 > v19 + 5) {\n if (a2 == a1->m128i_i8[v19 + 5]) ++v20;\n v32 = v19 + 6;\n if (v3 > v32 && a2 == a1->m128i_i8[v32]) ++v20;\n }\n }\n }\n LABEL_27:\n v33 = 10 / v3 * v20;\n goto LABEL_28;\n }\n v33 = 0;\nLABEL_28:\n v34 = 10 % v3;\n if (!(10 % v3)) return v33;\n if ((unsigned int)(v34 - 1) <= 6) {\n v42 = 0;\n } else {\n v35 = a2;\n BYTE1(v35) = a2;\n v36 = _mm_cmpeq_epi8(_mm_loadl_epi64(a1),\n _mm_shufflelo_epi16(_mm_cvtsi32_si128(v35), 0));\n v37 = _mm_unpacklo_epi8(v36, _mm_cmpgt_epi8((__m128i)0LL, v36));\n v38 = _mm_shuffle_epi32(v37, 78);\n v39 = _mm_cmpgt_epi16((__m128i)0LL, v38);\n v40 = _mm_unpacklo_epi16(v37, _mm_cmpgt_epi16((__m128i)0LL, v37));\n v41 = _mm_sub_epi32(\n _mm_sub_epi32(\n _mm_sub_epi32(\n _mm_and_si128(_mm_loadl_epi64((const __m128i *)&qword_2088),\n v40),\n _mm_shuffle_epi32(v40, 78)),\n _mm_unpacklo_epi16(v38, v39)),\n _mm_shuffle_epi32(_mm_unpacklo_epi16(v38, v39), 78));\n v33 +=\n _mm_cvtsi128_si32(v41) + _mm_cvtsi128_si32(_mm_shuffle_epi32(v41, 229));\n v42 = 8;\n if (v34 == 8) return v33;\n }\n if (a1->m128i_i8[v42] == a2) ++v33;\n if (v34 <= v42 + 1) return v33;\n if (a2 == a1->m128i_i8[v42 + 1]) ++v33;\n if (v42 + 2 >= v34) return v33;\n if (a2 == a1->m128i_i8[2]) ++v33;\n if (v34 == 3) return v33;\n if (a2 != a1->m128i_i8[3]) {\n if (v34 != 4) goto LABEL_42;\n return v33;\n }\n ++v33;\n if (v34 == 4) return v33;\nLABEL_42:\n if (a2 == a1->m128i_i8[4]) ++v33;\n if (v34 == 5) return v33;\n if (a2 == a1->m128i_i8[5]) ++v33;\n if (v34 == 6 || a2 != a1->m128i_i8[6]) return v33;\n return v33 + 1;\n}" + }, + { + "index": 685, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n bool prime[n + 1];\n for (int j = 0; j <= n; j++) {\n prime[j] = true;\n }\n int p = 2;\n while (p * p <= n) {\n if (prime[p] == true) {\n int i = p * 2;\n while (i <= n) {\n prime[i] = false;\n i += p;\n }\n }\n p += 1;\n }\n int sum = 0;\n for (int i = 2; i <= n; i++) {\n if (prime[i]) {\n sum += i;\n }\n }\n return sum;\n}", + "test": "int main() {\n\n assert(func0(10) == 17);\n\n assert(func0(20) == 77);\n\n assert(func0(5) == 10);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x40,%rsp\nmov %edi,-0x34(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmov %rsp,%rax\nmov %rax,%rcx\nmov -0x34(%rbp),%eax\nadd $0x1,%eax\nmovslq %eax,%rdx\nsub $0x1,%rdx\nmov %rdx,-0x18(%rbp)\nmovslq %eax,%rdx\nmov %rdx,%r10\nmov $0x0,%r11d\nmovslq %eax,%rdx\nmov %rdx,%r8\nmov $0x0,%r9d\ncltq\nmov $0x10,%edx\nsub $0x1,%rdx\nadd %rdx,%rax\nmov $0x10,%edi\nmov $0x0,%edx\ndiv %rdi\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rsi\nsub %rdx,%rsi\nmov %rsi,%rdx\ncmp %rdx,%rsp\nje 121f \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 1208 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 1249 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x0,%rax\nmov %rax,-0x10(%rbp)\nmovl $0x0,-0x20(%rbp)\njmp 126e \nmov -0x10(%rbp),%rdx\nmov -0x20(%rbp),%eax\ncltq\nmovb $0x1,(%rdx,%rax,1)\naddl $0x1,-0x20(%rbp)\nmov -0x20(%rbp),%eax\ncmp -0x34(%rbp),%eax\njle 125d \nmovl $0x2,-0x24(%rbp)\njmp 12b9 \nmov -0x10(%rbp),%rdx\nmov -0x24(%rbp),%eax\ncltq\nmovzbl (%rdx,%rax,1),%eax\ntest %al,%al\nje 12b5 \nmov -0x24(%rbp),%eax\nadd %eax,%eax\nmov %eax,-0x28(%rbp)\njmp 12ad \nmov -0x10(%rbp),%rdx\nmov -0x28(%rbp),%eax\ncltq\nmovb $0x0,(%rdx,%rax,1)\nmov -0x24(%rbp),%eax\nadd %eax,-0x28(%rbp)\nmov -0x28(%rbp),%eax\ncmp -0x34(%rbp),%eax\njle 129a \naddl $0x1,-0x24(%rbp)\nmov -0x24(%rbp),%eax\nimul %eax,%eax\ncmp %eax,-0x34(%rbp)\njge 127f \nmovl $0x0,-0x2c(%rbp)\nmovl $0x2,-0x1c(%rbp)\njmp 12ef \nmov -0x10(%rbp),%rdx\nmov -0x1c(%rbp),%eax\ncltq\nmovzbl (%rdx,%rax,1),%eax\ntest %al,%al\nje 12eb \nmov -0x1c(%rbp),%eax\nadd %eax,-0x2c(%rbp)\naddl $0x1,-0x1c(%rbp)\nmov -0x1c(%rbp),%eax\ncmp -0x34(%rbp),%eax\njle 12d4 \nmov -0x2c(%rbp),%eax\nmov %rcx,%rsp\nmov -0x8(%rbp),%rdi\nxor %fs:0x28,%rdi\nje 1311 \ncallq 1080 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_34], edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov eax, [rbp+var_34]\nadd eax, 1\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nmov edx, 10h\nsub rdx, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11ED:\ncmp rsp, rdx\njz short loc_1204\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_11ED\nloc_1204:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_122E\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_122E:\nmov rax, rsp\nadd rax, 0\nmov [rbp+var_10], rax\nmov [rbp+var_2C], 0\njmp short loc_1253\nloc_1242:\nmov rdx, [rbp+var_10]\nmov eax, [rbp+var_2C]\ncdqe\nmov byte ptr [rdx+rax], 1\nadd [rbp+var_2C], 1\nloc_1253:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_34]\njle short loc_1242\nmov [rbp+var_28], 2\njmp short loc_129E\nloc_1264:\nmov rdx, [rbp+var_10]\nmov eax, [rbp+var_28]\ncdqe\nmovzx eax, byte ptr [rdx+rax]\ntest al, al\njz short loc_129A\nmov eax, [rbp+var_28]\nadd eax, eax\nmov [rbp+var_24], eax\njmp short loc_1292\nloc_127F:\nmov rdx, [rbp+var_10]\nmov eax, [rbp+var_24]\ncdqe\nmov byte ptr [rdx+rax], 0\nmov eax, [rbp+var_28]\nadd [rbp+var_24], eax\nloc_1292:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_34]\njle short loc_127F\nloc_129A:\nadd [rbp+var_28], 1\nloc_129E:\nmov eax, [rbp+var_28]\nimul eax, eax\ncmp [rbp+var_34], eax\njge short loc_1264\nmov [rbp+var_20], 0\nmov [rbp+var_1C], 2\njmp short loc_12D4\nloc_12B9:\nmov rdx, [rbp+var_10]\nmov eax, [rbp+var_1C]\ncdqe\nmovzx eax, byte ptr [rdx+rax]\ntest al, al\njz short loc_12D0\nmov eax, [rbp+var_1C]\nadd [rbp+var_20], eax\nloc_12D0:\nadd [rbp+var_1C], 1\nloc_12D4:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_34]\njle short loc_12B9\nmov eax, [rbp+var_20]\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12F6\ncall ___stack_chk_fail\nlocret_12F6:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned __int64 v1; // rax\n void *v2; // rsp\n _BYTE v4[12]; // [rsp+8h] [rbp-40h] BYREF\n int v5; // [rsp+14h] [rbp-34h]\n int i; // [rsp+1Ch] [rbp-2Ch]\n int j; // [rsp+20h] [rbp-28h]\n int k; // [rsp+24h] [rbp-24h]\n unsigned int v9; // [rsp+28h] [rbp-20h]\n int m; // [rsp+2Ch] [rbp-1Ch]\n __int64 v11; // [rsp+30h] [rbp-18h]\n _BYTE *v12; // [rsp+38h] [rbp-10h]\n unsigned __int64 v13; // [rsp+40h] [rbp-8h]\n\n v5 = a1;\n v13 = __readfsqword(0x28u);\n v11 = a1 + 1 - 1LL;\n v1 = 16 * ((a1 + 1 + 15LL) / 0x10uLL);\n while ( v4 != &v4[-(v1 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v2 = alloca(v1 & 0xFFF);\n if ( (v1 & 0xFFF) != 0 )\n *(_QWORD *)&v4[(v1 & 0xFFF) - 8] = *(_QWORD *)&v4[(v1 & 0xFFF) - 8];\n v12 = v4;\n for ( i = 0; i <= v5; ++i )\n v12[i] = 1;\n for ( j = 2; v5 >= j * j; ++j )\n {\n if ( v12[j] )\n {\n for ( k = 2 * j; k <= v5; k += j )\n v12[k] = 0;\n }\n }\n v9 = 0;\n for ( m = 2; m <= v5; ++m )\n {\n if ( v12[m] )\n v9 += m;\n }\n return v9;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_34], edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov eax, [rbp+var_34]\nadd eax, 1\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nmov edx, 10h\nsub rdx, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11ED:\ncmp rsp, rdx\njz short loc_1204\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_11ED\nloc_1204:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_122E\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_122E:\nmov rax, rsp\nadd rax, 0\nmov [rbp+var_10], rax\nmov [rbp+var_2C], 0\njmp short loc_1253\nloc_1242:\nmov rdx, [rbp+var_10]\nmov eax, [rbp+var_2C]\ncdqe\nmov byte ptr [rdx+rax], 1\nadd [rbp+var_2C], 1\nloc_1253:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_34]\njle short loc_1242\nmov [rbp+var_28], 2\njmp short loc_129E\nloc_1264:\nmov rdx, [rbp+var_10]\nmov eax, [rbp+var_28]\ncdqe\nmovzx eax, byte ptr [rdx+rax]\ntest al, al\njz short loc_129A\nmov eax, [rbp+var_28]\nadd eax, eax\nmov [rbp+var_24], eax\njmp short loc_1292\nloc_127F:\nmov rdx, [rbp+var_10]\nmov eax, [rbp+var_24]\ncdqe\nmov byte ptr [rdx+rax], 0\nmov eax, [rbp+var_28]\nadd [rbp+var_24], eax\nloc_1292:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_34]\njle short loc_127F\nloc_129A:\nadd [rbp+var_28], 1\nloc_129E:\nmov eax, [rbp+var_28]\nimul eax, eax\ncmp [rbp+var_34], eax\njge short loc_1264\nmov [rbp+var_20], 0\nmov [rbp+var_1C], 2\njmp short loc_12D4\nloc_12B9:\nmov rdx, [rbp+var_10]\nmov eax, [rbp+var_1C]\ncdqe\nmovzx eax, byte ptr [rdx+rax]\ntest al, al\njz short loc_12D0\nmov eax, [rbp+var_1C]\nadd [rbp+var_20], eax\nloc_12D0:\nadd [rbp+var_1C], 1\nloc_12D4:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_34]\njle short loc_12B9\nmov eax, [rbp+var_20]\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12F6\ncall ___stack_chk_fail\nlocret_12F6:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(int a1)\n{\n unsigned __int64 v1; // rax\n void *v2; // rsp\n _BYTE v4[12]; // [rsp+8h] [rbp-40h] BYREF\n int v5; // [rsp+14h] [rbp-34h]\n int i; // [rsp+1Ch] [rbp-2Ch]\n int j; // [rsp+20h] [rbp-28h]\n int k; // [rsp+24h] [rbp-24h]\n unsigned int v9; // [rsp+28h] [rbp-20h]\n int m; // [rsp+2Ch] [rbp-1Ch]\n __int64 v11; // [rsp+30h] [rbp-18h]\n _BYTE *v12; // [rsp+38h] [rbp-10h]\n unsigned __int64 v13; // [rsp+40h] [rbp-8h]\n\n v5 = a1;\n v13 = __readfsqword(0x28u);\n v11 = a1 + 1 - 1LL;\n v1 = 16 * ((a1 + 1 + 15LL) / 0x10uLL);\n while ( v4 != &v4[-(v1 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v2 = alloca(v1 & 0xFFF);\n if ( (v1 & 0xFFF) != 0 )\n *(_QWORD *)&v4[(v1 & 0xFFF) - 8] = *(_QWORD *)&v4[(v1 & 0xFFF) - 8];\n v12 = v4;\n for ( i = 0; i <= v5; ++i )\n v12[i] = 1;\n for ( j = 2; v5 >= j * j; ++j )\n {\n if ( v12[j] )\n {\n for ( k = 2 * j; k <= v5; k += j )\n v12[k] = 0;\n }\n }\n v9 = 0;\n for ( m = 2; m <= v5; ++m )\n {\n if ( v12[m] )\n v9 += m;\n }\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(int a1) {\n unsigned long long v1;\n void *v2;\n uint8_t v4[12];\n int v5;\n int i;\n int j;\n int k;\n unsigned int v9;\n int m;\n long long v11;\n uint8_t *v12;\n unsigned long long v13;\n v5 = a1;\n v13 = __readfsqword(40u);\n v11 = a1 + 1 - 1LL;\n v1 = 16 * ((a1 + 1 + 15LL) / 16uLL);\n while (v4 != &v4[-(v1 & 18446744073709547520LL)])\n ;\n v2 = alloca(v1 & 4095);\n if ((v1 & 4095) != 0)\n *(uint64_t *)&v4[(v1 & 4095) - 8] = *(uint64_t *)&v4[(v1 & 4095) - 8];\n v12 = v4;\n for (i = 0; i <= v5; ++i) v12[i] = 1;\n for (j = 2; v5 >= j * j; ++j) {\n if (v12[j]) {\n for (k = 2 * j; k <= v5; k += j) v12[k] = 0;\n }\n }\n v9 = 0;\n for (m = 2; m <= v5; ++m) {\n if (v12[m]) v9 += m;\n }\n return v9;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned long long v1;\n void *v2;\n uint8_t v4[12];\n int v5;\n int i;\n int j;\n int k;\n unsigned int v9;\n int m;\n long long v11;\n uint8_t *v12;\n unsigned long long v13;\n v5 = a1;\n v13 = __readfsqword(40u);\n v11 = a1 + 1 - 1LL;\n v1 = 16 * ((a1 + 1 + 15LL) / 16uLL);\n while (v4 != &v4[-(v1 & 18446744073709547520LL)])\n ;\n v2 = alloca(v1 & 4095);\n if ((v1 & 4095) != 0)\n *(uint64_t *)&v4[(v1 & 4095) - 8] = *(uint64_t *)&v4[(v1 & 4095) - 8];\n v12 = v4;\n for (i = 0; i <= v5; ++i) v12[i] = 1;\n for (j = 2; v5 >= j * j; ++j) {\n if (v12[j]) {\n for (k = 2 * j; k <= v5; k += j) v12[k] = 0;\n }\n }\n v9 = 0;\n for (m = 2; m <= v5; ++m) {\n if (v12[m]) v9 += m;\n }\n return v9;\n}" + }, + { + "index": 685, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n bool prime[n + 1];\n for (int j = 0; j <= n; j++) {\n prime[j] = true;\n }\n int p = 2;\n while (p * p <= n) {\n if (prime[p] == true) {\n int i = p * 2;\n while (i <= n) {\n prime[i] = false;\n i += p;\n }\n }\n p += 1;\n }\n int sum = 0;\n for (int i = 2; i <= n; i++) {\n if (prime[i]) {\n sum += i;\n }\n }\n return sum;\n}", + "test": "int main() {\n\n assert(func0(10) == 17);\n\n assert(func0(20) == 77);\n\n assert(func0(5) == 10);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0x1(%rdi),%eax\ncltq\nadd $0xf,%rax\nmov %rax,%rdx\nand $0xfffffffffffffff0,%rdx\nand $0xfffffffffffff000,%rax\nmov %rsp,%rsi\nsub %rax,%rsi\nmov %rsi,%rax\ncmp %rax,%rsp\nje 11da \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11c3 \nmov %rdx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 11f0 \norq $0x0,-0x8(%rsp,%rax,1)\nmov %rsp,%rsi\ntest %edi,%edi\njs 120d \nmov %rsi,%rax\nmov %edi,%edx\nlea 0x1(%rsi,%rdx,1),%rdx\nmovb $0x1,(%rax)\nadd $0x1,%rax\ncmp %rdx,%rax\njne 1201 \ncmp $0x3,%edi\njle 1245 \nmov $0x2,%ecx\njmp 1227 \nlea 0x1(%rdx),%eax\nadd $0x1,%rcx\nimul %eax,%eax\ncmp %edi,%eax\njg 1262 \nmov %ecx,%edx\ncmpb $0x0,(%rsi,%rcx,1)\nje 1219 \nlea (%rcx,%rcx,1),%eax\ncmp %eax,%edi\njl 1219 \ncltq\nmovb $0x0,(%rsi,%rax,1)\nadd %rcx,%rax\ncmp %eax,%edi\njge 1238 \njmp 1219 \ncmp $0x1,%edi\njg 1262 \nmov $0x0,%edx\nmov -0x8(%rbp),%rax\nxor %fs:0x28,%rax\njne 1280 \nmov %edx,%eax\nleaveq\nretq\nmov $0x2,%eax\nmov $0x0,%edx\njmp 1276 \nadd $0x1,%rax\ncmp %eax,%edi\njl 124f \ncmpb $0x0,(%rsi,%rax,1)\nje 126e \nadd %eax,%edx\njmp 126e \ncallq 1080 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea eax, [rdi+1]\ncdqe\nadd rax, 0Fh\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11C0:\ncmp rsp, rdx\njz short loc_11D7\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11C0\nloc_11D7:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11ED\nor [rsp+rax+10h+var_18], 0\nloc_11ED:\nmov rsi, rsp\ntest edi, edi\njs loc_127A\nmov rax, rsi\nlea edx, [rdi+1]\nadd rdx, rsi\nloc_1201:\nmov byte ptr [rax], 1\nadd rax, 1\ncmp rax, rdx\njnz short loc_1201\ncmp edi, 3\njle short loc_124E\nmov r8d, 4\nmov ecx, 2\njmp short loc_1231\nloc_121F:\nlea eax, [rdx+1]\nadd rcx, 1\nadd r8d, 2\nimul eax, eax\ncmp eax, edi\njg short loc_1258\nloc_1231:\nmov edx, ecx\ncmp byte ptr [rsi+rcx], 0\njz short loc_121F\ncmp edi, r8d\njl short loc_121F\nmovsxd rax, r8d\nloc_1241:\nmov byte ptr [rsi+rax], 0\nadd rax, rcx\ncmp edi, eax\njge short loc_1241\njmp short loc_121F\nloc_124E:\nmov edx, 0\ncmp edi, 1\njle short loc_127F\nloc_1258:\nlea ecx, [rdi+1]\nmov eax, 2\nmov edx, 0\njmp short loc_1270\nloc_1267:\nadd rax, 1\ncmp rax, rcx\njz short loc_127F\nloc_1270:\ncmp byte ptr [rsi+rax], 0\njz short loc_1267\nadd edx, eax\njmp short loc_1267\nloc_127A:\nmov edx, 0\nloc_127F:\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njnz short loc_1292\nmov eax, edx\nleave\nretn\nloc_1292:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n signed __int64 v1; // rax\n void *v2; // rsp\n _BYTE *v3; // rax\n int v4; // r8d\n __int64 v5; // rcx\n int v6; // edx\n __int64 v7; // rax\n unsigned int v8; // edx\n __int64 v9; // rax\n _BYTE v12[8]; // [rsp+8h] [rbp-10h] BYREF\n unsigned __int64 v13; // [rsp+10h] [rbp-8h]\n\n v13 = __readfsqword(0x28u);\n while ( v12 != &v12[-((a1 + 1 + 15LL) & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v1 = ((_WORD)a1 + 16) & 0xFF0;\n v2 = alloca(v1);\n if ( (((_WORD)a1 + 16) & 0xFF0) != 0 )\n *(_QWORD *)&v12[v1 - 8] = *(_QWORD *)&v12[v1 - 8];\n if ( a1 < 0 )\n return 0;\n v3 = v12;\n do\n *v3++ = 1;\n while ( v3 != &v12[a1 + 1] );\n if ( a1 <= 3 )\n {\n v8 = 0;\n if ( a1 <= 1 )\n return v8;\n }\n else\n {\n v4 = 4;\n v5 = 2LL;\n do\n {\n v6 = v5;\n if ( v12[v5] && a1 >= v4 )\n {\n v7 = v4;\n do\n {\n v12[v7] = 0;\n v7 += v5;\n }\n while ( a1 >= (int)v7 );\n }\n ++v5;\n v4 += 2;\n }\n while ( (v6 + 1) * (v6 + 1) <= a1 );\n }\n v9 = 2LL;\n v8 = 0;\n do\n {\n if ( v12[v9] )\n v8 += v9;\n ++v9;\n }\n while ( v9 != a1 + 1 );\n return v8;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea eax, [rdi+1]\ncdqe\nadd rax, 0Fh\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11C0:\ncmp rsp, rdx\njz short loc_11D7\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11C0\nloc_11D7:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11ED\nor [rsp+rax+10h+var_18], 0\nloc_11ED:\nmov rsi, rsp\ntest edi, edi\njs loc_127A\nmov rax, rsi\nlea edx, [rdi+1]\nadd rdx, rsi\nloc_1201:\nmov byte ptr [rax], 1\nadd rax, 1\ncmp rax, rdx\njnz short loc_1201\ncmp edi, 3\njle short loc_124E\nmov r8d, 4\nmov ecx, 2\njmp short loc_1231\nloc_121F:\nlea eax, [rdx+1]\nadd rcx, 1\nadd r8d, 2\nimul eax, eax\ncmp eax, edi\njg short loc_1258\nloc_1231:\nmov edx, ecx\ncmp byte ptr [rsi+rcx], 0\njz short loc_121F\ncmp edi, r8d\njl short loc_121F\nmovsxd rax, r8d\nloc_1241:\nmov byte ptr [rsi+rax], 0\nadd rax, rcx\ncmp edi, eax\njge short loc_1241\njmp short loc_121F\nloc_124E:\nmov edx, 0\ncmp edi, 1\njle short loc_127F\nloc_1258:\nlea ecx, [rdi+1]\nmov eax, 2\nmov edx, 0\njmp short loc_1270\nloc_1267:\nadd rax, 1\ncmp rax, rcx\njz short loc_127F\nloc_1270:\ncmp byte ptr [rsi+rax], 0\njz short loc_1267\nadd edx, eax\njmp short loc_1267\nloc_127A:\nmov edx, 0\nloc_127F:\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njnz short loc_1292\nmov eax, edx\nleave\nretn\nloc_1292:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(int a1)\n{\n signed __int64 v1; // rax\n void *v2; // rsp\n _BYTE *v3; // rax\n int v4; // r8d\n __int64 v5; // rcx\n int v6; // edx\n __int64 v7; // rax\n unsigned int v8; // edx\n __int64 v9; // rax\n _BYTE v12[8]; // [rsp+8h] [rbp-10h] BYREF\n unsigned __int64 v13; // [rsp+10h] [rbp-8h]\n\n v13 = __readfsqword(0x28u);\n while ( v12 != &v12[-((a1 + 1 + 15LL) & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v1 = ((_WORD)a1 + 16) & 0xFF0;\n v2 = alloca(v1);\n if ( (((_WORD)a1 + 16) & 0xFF0) != 0 )\n *(_QWORD *)&v12[v1 - 8] = *(_QWORD *)&v12[v1 - 8];\n if ( a1 < 0 )\n return 0;\n v3 = v12;\n do\n *v3++ = 1;\n while ( v3 != &v12[a1 + 1] );\n if ( a1 <= 3 )\n {\n v8 = 0;\n if ( a1 <= 1 )\n return v8;\n }\n else\n {\n v4 = 4;\n v5 = 2LL;\n do\n {\n v6 = v5;\n if ( v12[v5] && a1 >= v4 )\n {\n v7 = v4;\n do\n {\n v12[v7] = 0;\n v7 += v5;\n }\n while ( a1 >= (int)v7 );\n }\n ++v5;\n v4 += 2;\n }\n while ( (v6 + 1) * (v6 + 1) <= a1 );\n }\n v9 = 2LL;\n v8 = 0;\n do\n {\n if ( v12[v9] )\n v8 += v9;\n ++v9;\n }\n while ( v9 != a1 + 1 );\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(int a1) {\n signed long long v1;\n void *v2;\n uint8_t *v3;\n int v4;\n long long v5;\n int v6;\n long long v7;\n unsigned int v8;\n long long v9;\n uint8_t v12[8];\n unsigned long long v13;\n v13 = __readfsqword(40u);\n while (v12 != &v12[-((a1 + 1 + 15LL) & 18446744073709547520LL)])\n ;\n v1 = ((unsigned short)a1 + 16) & 4080;\n v2 = alloca(v1);\n if ((((unsigned short)a1 + 16) & 4080) != 0)\n *(uint64_t *)&v12[v1 - 8] = *(uint64_t *)&v12[v1 - 8];\n if (a1 < 0) return 0;\n v3 = v12;\n do\n *v3++ = 1;\n while (v3 != &v12[a1 + 1]);\n if (a1 <= 3) {\n v8 = 0;\n if (a1 <= 1) return v8;\n } else {\n v4 = 4;\n v5 = 2LL;\n do {\n v6 = v5;\n if (v12[v5] && a1 >= v4) {\n v7 = v4;\n do {\n v12[v7] = 0;\n v7 += v5;\n } while (a1 >= (int)v7);\n }\n ++v5;\n v4 += 2;\n } while ((v6 + 1) * (v6 + 1) <= a1);\n }\n v9 = 2LL;\n v8 = 0;\n do {\n if (v12[v9]) v8 += v9;\n ++v9;\n } while (v9 != a1 + 1);\n return v8;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n signed long long v1;\n void *v2;\n uint8_t *v3;\n int v4;\n long long v5;\n int v6;\n long long v7;\n unsigned int v8;\n long long v9;\n uint8_t v12[8];\n unsigned long long v13;\n v13 = __readfsqword(40u);\n while (v12 != &v12[-((a1 + 1 + 15LL) & 18446744073709547520LL)])\n ;\n v1 = ((unsigned short)a1 + 16) & 4080;\n v2 = alloca(v1);\n if ((((unsigned short)a1 + 16) & 4080) != 0)\n *(uint64_t *)&v12[v1 - 8] = *(uint64_t *)&v12[v1 - 8];\n if (a1 < 0) return 0;\n v3 = v12;\n do\n *v3++ = 1;\n while (v3 != &v12[a1 + 1]);\n if (a1 <= 3) {\n v8 = 0;\n if (a1 <= 1) return v8;\n } else {\n v4 = 4;\n v5 = 2LL;\n do {\n v6 = v5;\n if (v12[v5] && a1 >= v4) {\n v7 = v4;\n do {\n v12[v7] = 0;\n v7 += v5;\n } while (a1 >= (int)v7);\n }\n ++v5;\n v4 += 2;\n } while ((v6 + 1) * (v6 + 1) <= a1);\n }\n v9 = 2LL;\n v8 = 0;\n do {\n if (v12[v9]) v8 += v9;\n ++v9;\n } while (v9 != a1 + 1);\n return v8;\n}" + }, + { + "index": 685, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n bool prime[n + 1];\n for (int j = 0; j <= n; j++) {\n prime[j] = true;\n }\n int p = 2;\n while (p * p <= n) {\n if (prime[p] == true) {\n int i = p * 2;\n while (i <= n) {\n prime[i] = false;\n i += p;\n }\n }\n p += 1;\n }\n int sum = 0;\n for (int i = 2; i <= n; i++) {\n if (prime[i]) {\n sum += i;\n }\n }\n return sum;\n}", + "test": "int main() {\n\n assert(func0(10) == 17);\n\n assert(func0(20) == 77);\n\n assert(func0(5) == 10);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0x1(%rdi),%eax\nmov %rsp,%rsi\ncltq\nadd $0xf,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rsi\nand $0xfffffffffffffff0,%rdx\nmov %rsi,%rax\ncmp %rax,%rsp\nje 1294 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 127f \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 134d \nmov %rsp,%rsi\ntest %edi,%edi\njs 1358 \nmovslq %edi,%rdx\nmov %rsp,%rax\nlea 0x1(%rsp,%rdx,1),%rdx\nnopl 0x0(%rax)\nmovb $0x1,(%rax)\nadd $0x1,%rax\ncmp %rdx,%rax\njne 12c0 \ncmp $0x3,%edi\njle 1358 \nmov $0x2,%ecx\njmp 12ee \nnopl 0x0(%rax)\nlea 0x1(%rdx),%eax\nadd $0x1,%rcx\nimul %eax,%eax\ncmp %edi,%eax\njg 1319 \ncmpb $0x0,(%rsi,%rcx,1)\nmov %ecx,%edx\nje 12e0 \nlea (%rcx,%rcx,1),%eax\ncmp %eax,%edi\njl 12e0 \ncltq\nmovb $0x0,(%rsi,%rax,1)\nadd %rcx,%rax\ncmp %eax,%edi\njge 1300 \nlea 0x1(%rdx),%eax\nadd $0x1,%rcx\nimul %eax,%eax\ncmp %edi,%eax\njle 12ee \nmov $0x2,%eax\nxor %r8d,%r8d\nnopl 0x0(%rax)\ncmpb $0x0,(%rsi,%rax,1)\nje 1331 \nadd %eax,%r8d\nadd $0x1,%rax\ncmp %eax,%edi\njge 1328 \nmov -0x8(%rbp),%rax\nxor %fs:0x28,%rax\njne 1362 \nleaveq\nmov %r8d,%eax\nretq\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 12a6 \ncmp $0x1,%edi\njg 1319 \nxor %r8d,%r8d\njmp 1339 \ncallq 1080 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r13\nlea r13d, [rdi+1]\npush r12\nmov r12d, edi\npush rbx\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nmovsxd rax, r13d\nmov rcx, rsp\nadd rax, 0Fh\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_12BB\nloc_12A6:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rcx\njnz short loc_12A6\nloc_12BB:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_137D\nloc_12CD:\nmov rbx, rsp\ntest r12d, r12d\njs loc_1388\nmovsxd rdx, r12d\nmov esi, 1; c\nmov rdi, rsp; s\nadd rdx, 1; n\ncall _memset\ncmp r12d, 3\njle short loc_1336\nmov esi, 4\nmov ecx, 2\njmp short loc_1312\nloc_1300:\nlea eax, [rdx+1]\nadd rcx, 1\nadd esi, 2\nimul eax, eax\ncmp eax, r12d\njg short loc_1340\nloc_1312:\ncmp byte ptr [rbx+rcx], 0\nmov edx, ecx\njz short loc_1300\ncmp r12d, esi\njl short loc_1300\nmov eax, esi\nnop dword ptr [rax+00000000h]\nloc_1328:\nmov byte ptr [rbx+rax], 0\nadd rax, rcx\ncmp r12d, eax\njge short loc_1328\njmp short loc_1300\nloc_1336:\ncmp r12d, 1\njle short loc_1388\nnop dword ptr [rax+00h]\nloc_1340:\nmov edx, r13d\nmov eax, 2\nxor ecx, ecx\nnop word ptr [rax+rax+00h]\nloc_1350:\ncmp byte ptr [rbx+rax], 0\njz short loc_1358\nadd ecx, eax\nloc_1358:\nadd rax, 1\ncmp rdx, rax\njnz short loc_1350\nloc_1361:\nmov rax, [rbp+var_28]\nsub rax, fs:28h\njnz short loc_138C\nlea rsp, [rbp-18h]\nmov eax, ecx\npop rbx\npop r12\npop r13\npop rbp\nretn\nloc_137D:\nor [rsp+rdx+1030h+var_1038], 0\njmp loc_12CD\nloc_1388:\nxor ecx, ecx\njmp short loc_1361\nloc_138C:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n _BYTE *v1; // rcx\n signed __int64 v2; // rdx\n void *v3; // rsp\n int v4; // esi\n __int64 v5; // rcx\n int v6; // edx\n __int64 v7; // rax\n __int64 v8; // rax\n unsigned int v9; // ecx\n _BYTE v12[4088]; // [rsp+8h] [rbp-1030h] BYREF\n _QWORD v13[6]; // [rsp+1008h] [rbp-30h] BYREF\n\n v13[1] = __readfsqword(0x28u);\n v1 = (char *)v13 - ((a1 + 1 + 15LL) & 0xFFFFFFFFFFFFF000LL);\n if ( v13 != (_QWORD *)v1 )\n {\n while ( v12 != v1 )\n ;\n }\n v2 = ((_WORD)a1 + 16) & 0xFF0;\n v3 = alloca(v2);\n if ( (((_WORD)a1 + 16) & 0xFF0) != 0 )\n *(_QWORD *)&v12[v2 - 8] = *(_QWORD *)&v12[v2 - 8];\n if ( a1 < 0 )\n return 0;\n memset(v12, 1, a1 + 1LL);\n if ( a1 > 3 )\n {\n v4 = 4;\n v5 = 2LL;\n do\n {\n v6 = v5;\n if ( v12[v5] && a1 >= v4 )\n {\n v7 = (unsigned int)v4;\n do\n {\n v12[v7] = 0;\n v7 += v5;\n }\n while ( a1 >= (int)v7 );\n }\n ++v5;\n v4 += 2;\n }\n while ( (v6 + 1) * (v6 + 1) <= a1 );\n goto LABEL_15;\n }\n if ( a1 <= 1 )\n return 0;\nLABEL_15:\n v8 = 2LL;\n v9 = 0;\n do\n {\n if ( v12[v8] )\n v9 += v8;\n ++v8;\n }\n while ( a1 + 1 != v8 );\n return v9;\n}", + "ida_strip_asm": "sub_1260:\nendbr64\npush rbp\nmov rbp, rsp\npush r13\nlea r13d, [rdi+1]\npush r12\nmov r12d, edi\npush rbx\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nmovsxd rax, r13d\nmov rcx, rsp\nadd rax, 0Fh\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_12BB\nloc_12A6:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rcx\njnz short loc_12A6\nloc_12BB:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_137D\nloc_12CD:\nmov rbx, rsp\ntest r12d, r12d\njs loc_1388\nmovsxd rdx, r12d\nmov esi, 1; c\nmov rdi, rsp; s\nadd rdx, 1; n\ncall _memset\ncmp r12d, 3\njle short loc_1336\nmov esi, 4\nmov ecx, 2\njmp short loc_1312\nloc_1300:\nlea eax, [rdx+1]\nadd rcx, 1\nadd esi, 2\nimul eax, eax\ncmp eax, r12d\njg short loc_1340\nloc_1312:\ncmp byte ptr [rbx+rcx], 0\nmov edx, ecx\njz short loc_1300\ncmp r12d, esi\njl short loc_1300\nmov eax, esi\nnop dword ptr [rax+00000000h]\nloc_1328:\nmov byte ptr [rbx+rax], 0\nadd rax, rcx\ncmp r12d, eax\njge short loc_1328\njmp short loc_1300\nloc_1336:\ncmp r12d, 1\njle short loc_1388\nnop dword ptr [rax+00h]\nloc_1340:\nmov edx, r13d\nmov eax, 2\nxor ecx, ecx\nnop word ptr [rax+rax+00h]\nloc_1350:\ncmp byte ptr [rbx+rax], 0\njz short loc_1358\nadd ecx, eax\nloc_1358:\nadd rax, 1\ncmp rdx, rax\njnz short loc_1350\nloc_1361:\nmov rax, [rbp+var_28]\nsub rax, fs:28h\njnz short loc_138C\nlea rsp, [rbp-18h]\nmov eax, ecx\npop rbx\npop r12\npop r13\npop rbp\nretn\nloc_137D:\nor [rsp+rdx+1030h+var_1038], 0\njmp loc_12CD\nloc_1388:\nxor ecx, ecx\njmp short loc_1361\nloc_138C:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1260(int a1)\n{\n _BYTE *v1; // rcx\n signed __int64 v2; // rdx\n void *v3; // rsp\n int v4; // esi\n __int64 v5; // rcx\n int v6; // edx\n __int64 v7; // rax\n __int64 v8; // rax\n unsigned int v9; // ecx\n _BYTE v12[4088]; // [rsp+8h] [rbp-1030h] BYREF\n _QWORD v13[6]; // [rsp+1008h] [rbp-30h] BYREF\n\n v13[1] = __readfsqword(0x28u);\n v1 = (char *)v13 - ((a1 + 1 + 15LL) & 0xFFFFFFFFFFFFF000LL);\n if ( v13 != (_QWORD *)v1 )\n {\n while ( v12 != v1 )\n ;\n }\n v2 = ((_WORD)a1 + 16) & 0xFF0;\n v3 = alloca(v2);\n if ( (((_WORD)a1 + 16) & 0xFF0) != 0 )\n *(_QWORD *)&v12[v2 - 8] = *(_QWORD *)&v12[v2 - 8];\n if ( a1 < 0 )\n return 0;\n memset(v12, 1, a1 + 1LL);\n if ( a1 > 3 )\n {\n v4 = 4;\n v5 = 2LL;\n do\n {\n v6 = v5;\n if ( v12[v5] && a1 >= v4 )\n {\n v7 = (unsigned int)v4;\n do\n {\n v12[v7] = 0;\n v7 += v5;\n }\n while ( a1 >= (int)v7 );\n }\n ++v5;\n v4 += 2;\n }\n while ( (v6 + 1) * (v6 + 1) <= a1 );\n goto LABEL_15;\n }\n if ( a1 <= 1 )\n return 0;\nLABEL_15:\n v8 = 2LL;\n v9 = 0;\n do\n {\n if ( v12[v8] )\n v9 += v8;\n ++v8;\n }\n while ( a1 + 1 != v8 );\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1260(int a1) {\n uint8_t *v1;\n signed long long v2;\n void *v3;\n int v4;\n long long v5;\n int v6;\n long long v7;\n long long v8;\n unsigned int v9;\n uint8_t v12[4088];\n uint64_t v13[6];\n v13[1] = __readfsqword(40u);\n v1 = (char *)v13 - ((a1 + 1 + 15LL) & 18446744073709547520LL);\n if (v13 != (uint64_t *)v1) {\n while (v12 != v1)\n ;\n }\n v2 = ((unsigned short)a1 + 16) & 4080;\n v3 = alloca(v2);\n if ((((unsigned short)a1 + 16) & 4080) != 0)\n *(uint64_t *)&v12[v2 - 8] = *(uint64_t *)&v12[v2 - 8];\n if (a1 < 0) return 0;\n memset(v12, 1, a1 + 1LL);\n if (a1 > 3) {\n v4 = 4;\n v5 = 2LL;\n do {\n v6 = v5;\n if (v12[v5] && a1 >= v4) {\n v7 = (unsigned int)v4;\n do {\n v12[v7] = 0;\n v7 += v5;\n } while (a1 >= (int)v7);\n }\n ++v5;\n v4 += 2;\n } while ((v6 + 1) * (v6 + 1) <= a1);\n goto LABEL_15;\n }\n if (a1 <= 1) return 0;\nLABEL_15:\n v8 = 2LL;\n v9 = 0;\n do {\n if (v12[v8]) v9 += v8;\n ++v8;\n } while (a1 + 1 != v8);\n return v9;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n uint8_t *v1;\n signed long long v2;\n void *v3;\n int v4;\n long long v5;\n int v6;\n long long v7;\n long long v8;\n unsigned int v9;\n uint8_t v12[4088];\n uint64_t v13[6];\n v13[1] = __readfsqword(40u);\n v1 = (char *)v13 - ((a1 + 1 + 15LL) & 18446744073709547520LL);\n if (v13 != (uint64_t *)v1) {\n while (v12 != v1)\n ;\n }\n v2 = ((unsigned short)a1 + 16) & 4080;\n v3 = alloca(v2);\n if ((((unsigned short)a1 + 16) & 4080) != 0)\n *(uint64_t *)&v12[v2 - 8] = *(uint64_t *)&v12[v2 - 8];\n if (a1 < 0) return 0;\n memset(v12, 1, a1 + 1LL);\n if (a1 > 3) {\n v4 = 4;\n v5 = 2LL;\n do {\n v6 = v5;\n if (v12[v5] && a1 >= v4) {\n v7 = (unsigned int)v4;\n do {\n v12[v7] = 0;\n v7 += v5;\n } while (a1 >= (int)v7);\n }\n ++v5;\n v4 += 2;\n } while ((v6 + 1) * (v6 + 1) <= a1);\n goto LABEL_15;\n }\n if (a1 <= 1) return 0;\nLABEL_15:\n v8 = 2LL;\n v9 = 0;\n do {\n if (v12[v8]) v9 += v8;\n ++v8;\n } while (a1 + 1 != v8);\n return v9;\n}" + }, + { + "index": 685, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n bool prime[n + 1];\n for (int j = 0; j <= n; j++) {\n prime[j] = true;\n }\n int p = 2;\n while (p * p <= n) {\n if (prime[p] == true) {\n int i = p * 2;\n while (i <= n) {\n prime[i] = false;\n i += p;\n }\n }\n p += 1;\n }\n int sum = 0;\n for (int i = 2; i <= n; i++) {\n if (prime[i]) {\n sum += i;\n }\n }\n return sum;\n}", + "test": "int main() {\n\n assert(func0(10) == 17);\n\n assert(func0(20) == 77);\n\n assert(func0(5) == 10);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r12\npush %rbx\nmov %edi,%ebx\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nlea 0x1(%rdi),%eax\nmov %rsp,%rsi\ncltq\nadd $0xf,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rsi\nand $0xfffffffffffffff0,%rdx\nmov %rsi,%rax\ncmp %rax,%rsp\nje 12b9 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 12a4 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 1375 \nmov %rsp,%r12\ntest %ebx,%ebx\njs 1380 \nmovslq %ebx,%rdx\nmov $0x1,%esi\nmov %rsp,%rdi\nadd $0x1,%rdx\ncallq 10b0 \ncmp $0x3,%ebx\njle 1380 \nmov $0x2,%ecx\njmp 130e \nnopw 0x0(%rax,%rax,1)\nlea 0x1(%rdx),%eax\nadd $0x1,%rcx\nimul %eax,%eax\ncmp %ebx,%eax\njg 133a \ncmpb $0x0,(%r12,%rcx,1)\nmov %ecx,%edx\nje 1300 \nlea (%rcx,%rcx,1),%eax\ncmp %eax,%ebx\njl 1300 \ncltq\nmovb $0x0,(%r12,%rax,1)\nadd %rcx,%rax\ncmp %eax,%ebx\njge 1320 \nlea 0x1(%rdx),%eax\nadd $0x1,%rcx\nimul %eax,%eax\ncmp %ebx,%eax\njle 130e \nmov $0x2,%eax\nxor %r8d,%r8d\nnopw 0x0(%rax,%rax,1)\ncmpb $0x0,(%r12,%rax,1)\nje 1352 \nadd %eax,%r8d\nadd $0x1,%rax\ncmp %eax,%ebx\njge 1348 \nmov -0x18(%rbp),%rax\nxor %fs:0x28,%rax\njne 138a \nlea -0x10(%rbp),%rsp\nmov %r8d,%eax\npop %rbx\npop %r12\npop %rbp\nretq\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 12cb \ncmp $0x1,%ebx\njg 133a \nxor %r8d,%r8d\njmp 135a \ncallq 1090 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r13\nlea r13d, [rdi+1]\npush r12\nmov r12d, edi\npush rbx\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nmovsxd rax, r13d\nmov rcx, rsp\nadd rax, 0Fh\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_12BB\nloc_12A6:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rcx\njnz short loc_12A6\nloc_12BB:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_137D\nloc_12CD:\nmov rbx, rsp\ntest r12d, r12d\njs loc_1388\nmovsxd rdx, r12d\nmov esi, 1; c\nmov rdi, rsp; s\nadd rdx, 1; n\ncall _memset\ncmp r12d, 3\njle short loc_1336\nmov esi, 4\nmov ecx, 2\njmp short loc_1312\nloc_1300:\nlea eax, [rdx+1]\nadd rcx, 1\nadd esi, 2\nimul eax, eax\ncmp eax, r12d\njg short loc_1340\nloc_1312:\ncmp byte ptr [rbx+rcx], 0\nmov edx, ecx\njz short loc_1300\ncmp r12d, esi\njl short loc_1300\nmov eax, esi\nnop dword ptr [rax+00000000h]\nloc_1328:\nmov byte ptr [rbx+rax], 0\nadd rax, rcx\ncmp r12d, eax\njge short loc_1328\njmp short loc_1300\nloc_1336:\ncmp r12d, 1\njle short loc_1388\nnop dword ptr [rax+00h]\nloc_1340:\nmov edx, r13d\nmov eax, 2\nxor ecx, ecx\nnop word ptr [rax+rax+00h]\nloc_1350:\ncmp byte ptr [rbx+rax], 0\njz short loc_1358\nadd ecx, eax\nloc_1358:\nadd rax, 1\ncmp rdx, rax\njnz short loc_1350\nloc_1361:\nmov rax, [rbp+var_28]\nsub rax, fs:28h\njnz short loc_138C\nlea rsp, [rbp-18h]\nmov eax, ecx\npop rbx\npop r12\npop r13\npop rbp\nretn\nloc_137D:\nor [rsp+rdx+1030h+var_1038], 0\njmp loc_12CD\nloc_1388:\nxor ecx, ecx\njmp short loc_1361\nloc_138C:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n _BYTE *v1; // rcx\n signed __int64 v2; // rdx\n void *v3; // rsp\n int v4; // esi\n __int64 v5; // rcx\n int v6; // edx\n __int64 v7; // rax\n __int64 v8; // rax\n unsigned int v9; // ecx\n _BYTE v12[4088]; // [rsp+8h] [rbp-1030h] BYREF\n _QWORD v13[6]; // [rsp+1008h] [rbp-30h] BYREF\n\n v13[1] = __readfsqword(0x28u);\n v1 = (char *)v13 - ((a1 + 1 + 15LL) & 0xFFFFFFFFFFFFF000LL);\n if ( v13 != (_QWORD *)v1 )\n {\n while ( v12 != v1 )\n ;\n }\n v2 = ((_WORD)a1 + 16) & 0xFF0;\n v3 = alloca(v2);\n if ( (((_WORD)a1 + 16) & 0xFF0) != 0 )\n *(_QWORD *)&v12[v2 - 8] = *(_QWORD *)&v12[v2 - 8];\n if ( a1 < 0 )\n return 0;\n memset(v12, 1, a1 + 1LL);\n if ( a1 > 3 )\n {\n v4 = 4;\n v5 = 2LL;\n do\n {\n v6 = v5;\n if ( v12[v5] && a1 >= v4 )\n {\n v7 = (unsigned int)v4;\n do\n {\n v12[v7] = 0;\n v7 += v5;\n }\n while ( a1 >= (int)v7 );\n }\n ++v5;\n v4 += 2;\n }\n while ( (v6 + 1) * (v6 + 1) <= a1 );\n goto LABEL_15;\n }\n if ( a1 <= 1 )\n return 0;\nLABEL_15:\n v8 = 2LL;\n v9 = 0;\n do\n {\n if ( v12[v8] )\n v9 += v8;\n ++v8;\n }\n while ( a1 + 1 != v8 );\n return v9;\n}", + "ida_strip_asm": "sub_1260:\nendbr64\npush rbp\nmov rbp, rsp\npush r13\nlea r13d, [rdi+1]\npush r12\nmov r12d, edi\npush rbx\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nmovsxd rax, r13d\nmov rcx, rsp\nadd rax, 0Fh\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_12BB\nloc_12A6:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rcx\njnz short loc_12A6\nloc_12BB:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_137D\nloc_12CD:\nmov rbx, rsp\ntest r12d, r12d\njs loc_1388\nmovsxd rdx, r12d\nmov esi, 1; c\nmov rdi, rsp; s\nadd rdx, 1; n\ncall _memset\ncmp r12d, 3\njle short loc_1336\nmov esi, 4\nmov ecx, 2\njmp short loc_1312\nloc_1300:\nlea eax, [rdx+1]\nadd rcx, 1\nadd esi, 2\nimul eax, eax\ncmp eax, r12d\njg short loc_1340\nloc_1312:\ncmp byte ptr [rbx+rcx], 0\nmov edx, ecx\njz short loc_1300\ncmp r12d, esi\njl short loc_1300\nmov eax, esi\nnop dword ptr [rax+00000000h]\nloc_1328:\nmov byte ptr [rbx+rax], 0\nadd rax, rcx\ncmp r12d, eax\njge short loc_1328\njmp short loc_1300\nloc_1336:\ncmp r12d, 1\njle short loc_1388\nnop dword ptr [rax+00h]\nloc_1340:\nmov edx, r13d\nmov eax, 2\nxor ecx, ecx\nnop word ptr [rax+rax+00h]\nloc_1350:\ncmp byte ptr [rbx+rax], 0\njz short loc_1358\nadd ecx, eax\nloc_1358:\nadd rax, 1\ncmp rdx, rax\njnz short loc_1350\nloc_1361:\nmov rax, [rbp+var_28]\nsub rax, fs:28h\njnz short loc_138C\nlea rsp, [rbp-18h]\nmov eax, ecx\npop rbx\npop r12\npop r13\npop rbp\nretn\nloc_137D:\nor [rsp+rdx+1030h+var_1038], 0\njmp loc_12CD\nloc_1388:\nxor ecx, ecx\njmp short loc_1361\nloc_138C:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1260(int a1)\n{\n _BYTE *v1; // rcx\n signed __int64 v2; // rdx\n void *v3; // rsp\n int v4; // esi\n __int64 v5; // rcx\n int v6; // edx\n __int64 v7; // rax\n __int64 v8; // rax\n unsigned int v9; // ecx\n _BYTE v12[4088]; // [rsp+8h] [rbp-1030h] BYREF\n _QWORD v13[6]; // [rsp+1008h] [rbp-30h] BYREF\n\n v13[1] = __readfsqword(0x28u);\n v1 = (char *)v13 - ((a1 + 1 + 15LL) & 0xFFFFFFFFFFFFF000LL);\n if ( v13 != (_QWORD *)v1 )\n {\n while ( v12 != v1 )\n ;\n }\n v2 = ((_WORD)a1 + 16) & 0xFF0;\n v3 = alloca(v2);\n if ( (((_WORD)a1 + 16) & 0xFF0) != 0 )\n *(_QWORD *)&v12[v2 - 8] = *(_QWORD *)&v12[v2 - 8];\n if ( a1 < 0 )\n return 0;\n memset(v12, 1, a1 + 1LL);\n if ( a1 > 3 )\n {\n v4 = 4;\n v5 = 2LL;\n do\n {\n v6 = v5;\n if ( v12[v5] && a1 >= v4 )\n {\n v7 = (unsigned int)v4;\n do\n {\n v12[v7] = 0;\n v7 += v5;\n }\n while ( a1 >= (int)v7 );\n }\n ++v5;\n v4 += 2;\n }\n while ( (v6 + 1) * (v6 + 1) <= a1 );\n goto LABEL_15;\n }\n if ( a1 <= 1 )\n return 0;\nLABEL_15:\n v8 = 2LL;\n v9 = 0;\n do\n {\n if ( v12[v8] )\n v9 += v8;\n ++v8;\n }\n while ( a1 + 1 != v8 );\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1260(int a1) {\n uint8_t *v1;\n signed long long v2;\n void *v3;\n int v4;\n long long v5;\n int v6;\n long long v7;\n long long v8;\n unsigned int v9;\n uint8_t v12[4088];\n uint64_t v13[6];\n v13[1] = __readfsqword(40u);\n v1 = (char *)v13 - ((a1 + 1 + 15LL) & 18446744073709547520LL);\n if (v13 != (uint64_t *)v1) {\n while (v12 != v1)\n ;\n }\n v2 = ((unsigned short)a1 + 16) & 4080;\n v3 = alloca(v2);\n if ((((unsigned short)a1 + 16) & 4080) != 0)\n *(uint64_t *)&v12[v2 - 8] = *(uint64_t *)&v12[v2 - 8];\n if (a1 < 0) return 0;\n memset(v12, 1, a1 + 1LL);\n if (a1 > 3) {\n v4 = 4;\n v5 = 2LL;\n do {\n v6 = v5;\n if (v12[v5] && a1 >= v4) {\n v7 = (unsigned int)v4;\n do {\n v12[v7] = 0;\n v7 += v5;\n } while (a1 >= (int)v7);\n }\n ++v5;\n v4 += 2;\n } while ((v6 + 1) * (v6 + 1) <= a1);\n goto LABEL_15;\n }\n if (a1 <= 1) return 0;\nLABEL_15:\n v8 = 2LL;\n v9 = 0;\n do {\n if (v12[v8]) v9 += v8;\n ++v8;\n } while (a1 + 1 != v8);\n return v9;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n uint8_t *v1;\n signed long long v2;\n void *v3;\n int v4;\n long long v5;\n int v6;\n long long v7;\n long long v8;\n unsigned int v9;\n uint8_t v12[4088];\n uint64_t v13[6];\n v13[1] = __readfsqword(40u);\n v1 = (char *)v13 - ((a1 + 1 + 15LL) & 18446744073709547520LL);\n if (v13 != (uint64_t *)v1) {\n while (v12 != v1)\n ;\n }\n v2 = ((unsigned short)a1 + 16) & 4080;\n v3 = alloca(v2);\n if ((((unsigned short)a1 + 16) & 4080) != 0)\n *(uint64_t *)&v12[v2 - 8] = *(uint64_t *)&v12[v2 - 8];\n if (a1 < 0) return 0;\n memset(v12, 1, a1 + 1LL);\n if (a1 > 3) {\n v4 = 4;\n v5 = 2LL;\n do {\n v6 = v5;\n if (v12[v5] && a1 >= v4) {\n v7 = (unsigned int)v4;\n do {\n v12[v7] = 0;\n v7 += v5;\n } while (a1 >= (int)v7);\n }\n ++v5;\n v4 += 2;\n } while ((v6 + 1) * (v6 + 1) <= a1);\n goto LABEL_15;\n }\n if (a1 <= 1) return 0;\nLABEL_15:\n v8 = 2LL;\n v9 = 0;\n do {\n if (v12[v8]) v9 += v8;\n ++v8;\n } while (a1 + 1 != v8);\n return v9;\n}" + }, + { + "index": 686, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\nstruct dict {\n\n int key;\n\n int value;\n\n};\n\n\n\n", + "func": "char *func0(int test_tup[], int size) {\n struct dict freq[100];\n int count = 0;\n for (int i = 0; i < size; i++) {\n int found = 0;\n for (int j = 0; j < count; j++) {\n if (freq[j].key == test_tup[i]) {\n freq[j].value++;\n found = 1;\n break;\n }\n }\n if (!found) {\n freq[count].key = test_tup[i];\n freq[count].value = 1;\n count++;\n }\n }\n char *result = (char *)malloc(1000 * sizeof(char));\n char buffer[50];\n result[0] = '\\0';\n strcat(result, \"{\");\n for (int i = 0; i < count; i++) {\n sprintf(buffer, \"%d: %d\", freq[i].key, freq[i].value);\n strcat(result, buffer);\n if (i < count - 1) strcat(result, \", \");\n }\n strcat(result, \"}\");\n return result;\n}", + "test": "int main() {\n\n int tuple1[] = {4, 5, 4, 5, 6, 6, 5, 5, 4};\n\n char *res1 = func0(tuple1, sizeof(tuple1)/sizeof(tuple1[0]));\n\n assert(strcmp(res1, \"{4: 3, 5: 4, 6: 2}\") == 0);\n\n free(res1);\n\n\n\n int tuple2[] = {7, 8, 8, 9, 4, 7, 6, 5, 4};\n\n char *res2 = func0(tuple2, sizeof(tuple2)/sizeof(tuple2[0]));\n\n assert(strcmp(res2, \"{7: 2, 8: 2, 9: 1, 4: 2, 6: 1, 5: 1}\") == 0);\n\n free(res2);\n\n\n\n int tuple3[] = {1, 4, 3, 1, 4, 5, 2, 6, 2, 7};\n\n char *res3 = func0(tuple3, sizeof(tuple3)/sizeof(tuple3[0]));\n\n assert(strcmp(res3, \"{1: 2, 4: 2, 3: 1, 5: 1, 2: 2, 6: 1, 7: 1}\") == 0);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x390,%rsp\nmov %rdi,-0x388(%rbp)\nmov %esi,-0x38c(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovl $0x0,-0x37c(%rbp)\nmovl $0x0,-0x378(%rbp)\njmpq 1329 \nmovl $0x0,-0x374(%rbp)\nmovl $0x0,-0x370(%rbp)\njmp 12c6 \nmov -0x370(%rbp),%eax\ncltq\nmov -0x360(%rbp,%rax,8),%edx\nmov -0x378(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x388(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 12bf \nmov -0x370(%rbp),%eax\ncltq\nmov -0x35c(%rbp,%rax,8),%eax\nlea 0x1(%rax),%edx\nmov -0x370(%rbp),%eax\ncltq\nmov %edx,-0x35c(%rbp,%rax,8)\nmovl $0x1,-0x374(%rbp)\njmp 12d4 \naddl $0x1,-0x370(%rbp)\nmov -0x370(%rbp),%eax\ncmp -0x37c(%rbp),%eax\njl 1263 \ncmpl $0x0,-0x374(%rbp)\njne 1322 \nmov -0x378(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x388(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x37c(%rbp),%eax\ncltq\nmov %edx,-0x360(%rbp,%rax,8)\nmov -0x37c(%rbp),%eax\ncltq\nmovl $0x1,-0x35c(%rbp,%rax,8)\naddl $0x1,-0x37c(%rbp)\naddl $0x1,-0x378(%rbp)\nmov -0x378(%rbp),%eax\ncmp -0x38c(%rbp),%eax\njl 124d \nmov $0x3e8,%edi\ncallq 10f0 \nmov %rax,-0x368(%rbp)\nmov -0x368(%rbp),%rax\nmovb $0x0,(%rax)\nmov -0x368(%rbp),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nmov -0x368(%rbp),%rax\nadd %rdx,%rax\nmovw $0x7b,(%rax)\nmovl $0x0,-0x36c(%rbp)\njmpq 1435 \nmov -0x36c(%rbp),%eax\ncltq\nmov -0x35c(%rbp,%rax,8),%ecx\nmov -0x36c(%rbp),%eax\ncltq\nmov -0x360(%rbp,%rax,8),%edx\nlea -0x40(%rbp),%rax\nlea 0xc46(%rip),%rsi\nmov %rax,%rdi\nmov $0x0,%eax\ncallq 1110 \nlea -0x40(%rbp),%rdx\nmov -0x368(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1100 \nmov -0x37c(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x36c(%rbp)\njge 142e \nmov -0x368(%rbp),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nmov -0x368(%rbp),%rax\nadd %rdx,%rax\nmovw $0x202c,(%rax)\nmovb $0x0,0x2(%rax)\naddl $0x1,-0x36c(%rbp)\nmov -0x36c(%rbp),%eax\ncmp -0x37c(%rbp),%eax\njl 1399 \nmov -0x368(%rbp),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nmov -0x368(%rbp),%rax\nadd %rdx,%rax\nmovw $0x7d,(%rax)\nmov -0x368(%rbp),%rax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 1496 \ncallq 10c0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 390h\nmov [rbp+var_388], rdi\nmov [rbp+var_38C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_37C], 0\nmov [rbp+var_378], 0\njmp loc_1349\nloc_126D:\nmov [rbp+var_374], 0\nmov [rbp+var_370], 0\njmp short loc_12E6\nloc_1283:\nmov eax, [rbp+var_370]\ncdqe\nmov edx, [rbp+rax*8+var_360]\nmov eax, [rbp+var_378]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_388]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_12DF\nmov eax, [rbp+var_370]\ncdqe\nmov eax, [rbp+rax*8+var_35C]\nlea edx, [rax+1]\nmov eax, [rbp+var_370]\ncdqe\nmov [rbp+rax*8+var_35C], edx\nmov [rbp+var_374], 1\njmp short loc_12F4\nloc_12DF:\nadd [rbp+var_370], 1\nloc_12E6:\nmov eax, [rbp+var_370]\ncmp eax, [rbp+var_37C]\njl short loc_1283\nloc_12F4:\ncmp [rbp+var_374], 0\njnz short loc_1342\nmov eax, [rbp+var_378]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_388]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_37C]\ncdqe\nmov [rbp+rax*8+var_360], edx\nmov eax, [rbp+var_37C]\ncdqe\nmov [rbp+rax*8+var_35C], 1\nadd [rbp+var_37C], 1\nloc_1342:\nadd [rbp+var_378], 1\nloc_1349:\nmov eax, [rbp+var_378]\ncmp eax, [rbp+var_38C]\njl loc_126D\nmov edi, 3E8h; size\ncall _malloc\nmov [rbp+s], rax\nmov rax, [rbp+s]\nmov byte ptr [rax], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+s]\nadd rax, rdx\nmov word ptr [rax], 7Bh ; '{'\nmov [rbp+var_36C], 0\njmp loc_142F\nloc_13A6:\nmov eax, [rbp+var_36C]\ncdqe\nmov ecx, [rbp+rax*8+var_35C]\nmov eax, [rbp+var_36C]\ncdqe\nmov edx, [rbp+rax*8+var_360]\nlea rax, [rbp+src]\nlea rsi, format; \"%d: %d\"\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rdx, [rbp+src]\nmov rax, [rbp+s]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\nmov eax, [rbp+var_37C]\nsub eax, 1\ncmp [rbp+var_36C], eax\njge short loc_1428\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+s]\nadd rax, rdx\nmov word ptr [rax], 202Ch\nmov byte ptr [rax+2], 0\nloc_1428:\nadd [rbp+var_36C], 1\nloc_142F:\nmov eax, [rbp+var_36C]\ncmp eax, [rbp+var_37C]\njl loc_13A6\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+s]\nadd rax, rdx\nmov word ptr [rax], 7Dh ; '}'\nmov rax, [rbp+s]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_147D\ncall ___stack_chk_fail\nlocret_147D:\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2)\n{\n int v3; // [rsp+14h] [rbp-37Ch]\n int i; // [rsp+18h] [rbp-378h]\n int v5; // [rsp+1Ch] [rbp-374h]\n int j; // [rsp+20h] [rbp-370h]\n int k; // [rsp+24h] [rbp-36Ch]\n char *s; // [rsp+28h] [rbp-368h]\n _DWORD v9[200]; // [rsp+30h] [rbp-360h]\n char src[56]; // [rsp+350h] [rbp-40h] BYREF\n unsigned __int64 v11; // [rsp+388h] [rbp-8h]\n\n v11 = __readfsqword(0x28u);\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v5 = 0;\n for ( j = 0; j < v3; ++j )\n {\n if ( v9[2 * j] == *(_DWORD *)(4LL * i + a1) )\n {\n ++v9[2 * j + 1];\n v5 = 1;\n break;\n }\n }\n if ( !v5 )\n {\n v9[2 * v3] = *(_DWORD *)(4LL * i + a1);\n v9[2 * v3++ + 1] = 1;\n }\n }\n s = (char *)malloc(0x3E8uLL);\n *s = 0;\n *(_WORD *)&s[strlen(s)] = 123;\n for ( k = 0; k < v3; ++k )\n {\n sprintf(src, \"%d: %d\", v9[2 * k], v9[2 * k + 1]);\n strcat(s, src);\n if ( k < v3 - 1 )\n strcpy(&s[strlen(s)], \", \");\n }\n *(_WORD *)&s[strlen(s)] = 125;\n return s;\n}", + "ida_strip_asm": "sub_1229:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 390h\nmov [rbp+var_388], rdi\nmov [rbp+var_38C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_37C], 0\nmov [rbp+var_378], 0\njmp loc_1349\nloc_126D:\nmov [rbp+var_374], 0\nmov [rbp+var_370], 0\njmp short loc_12E6\nloc_1283:\nmov eax, [rbp+var_370]\ncdqe\nmov edx, [rbp+rax*8+var_360]\nmov eax, [rbp+var_378]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_388]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_12DF\nmov eax, [rbp+var_370]\ncdqe\nmov eax, [rbp+rax*8+var_35C]\nlea edx, [rax+1]\nmov eax, [rbp+var_370]\ncdqe\nmov [rbp+rax*8+var_35C], edx\nmov [rbp+var_374], 1\njmp short loc_12F4\nloc_12DF:\nadd [rbp+var_370], 1\nloc_12E6:\nmov eax, [rbp+var_370]\ncmp eax, [rbp+var_37C]\njl short loc_1283\nloc_12F4:\ncmp [rbp+var_374], 0\njnz short loc_1342\nmov eax, [rbp+var_378]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_388]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_37C]\ncdqe\nmov [rbp+rax*8+var_360], edx\nmov eax, [rbp+var_37C]\ncdqe\nmov [rbp+rax*8+var_35C], 1\nadd [rbp+var_37C], 1\nloc_1342:\nadd [rbp+var_378], 1\nloc_1349:\nmov eax, [rbp+var_378]\ncmp eax, [rbp+var_38C]\njl loc_126D\nmov edi, 3E8h; size\ncall _malloc\nmov [rbp+s], rax\nmov rax, [rbp+s]\nmov byte ptr [rax], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+s]\nadd rax, rdx\nmov word ptr [rax], 7Bh ; '{'\nmov [rbp+var_36C], 0\njmp loc_142F\nloc_13A6:\nmov eax, [rbp+var_36C]\ncdqe\nmov ecx, [rbp+rax*8+var_35C]\nmov eax, [rbp+var_36C]\ncdqe\nmov edx, [rbp+rax*8+var_360]\nlea rax, [rbp+src]\nlea rsi, format; \"%d: %d\"\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rdx, [rbp+src]\nmov rax, [rbp+s]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\nmov eax, [rbp+var_37C]\nsub eax, 1\ncmp [rbp+var_36C], eax\njge short loc_1428\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+s]\nadd rax, rdx\nmov word ptr [rax], 202Ch\nmov byte ptr [rax+2], 0\nloc_1428:\nadd [rbp+var_36C], 1\nloc_142F:\nmov eax, [rbp+var_36C]\ncmp eax, [rbp+var_37C]\njl loc_13A6\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+s]\nadd rax, rdx\nmov word ptr [rax], 7Dh ; '}'\nmov rax, [rbp+s]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_147D\ncall ___stack_chk_fail\nlocret_147D:\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1229(__int64 a1, int a2)\n{\n int v3; // [rsp+14h] [rbp-37Ch]\n int i; // [rsp+18h] [rbp-378h]\n int v5; // [rsp+1Ch] [rbp-374h]\n int j; // [rsp+20h] [rbp-370h]\n int k; // [rsp+24h] [rbp-36Ch]\n char *s; // [rsp+28h] [rbp-368h]\n _DWORD v9[200]; // [rsp+30h] [rbp-360h]\n char src[56]; // [rsp+350h] [rbp-40h] BYREF\n unsigned __int64 v11; // [rsp+388h] [rbp-8h]\n\n v11 = __readfsqword(0x28u);\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v5 = 0;\n for ( j = 0; j < v3; ++j )\n {\n if ( v9[2 * j] == *(_DWORD *)(4LL * i + a1) )\n {\n ++v9[2 * j + 1];\n v5 = 1;\n break;\n }\n }\n if ( !v5 )\n {\n v9[2 * v3] = *(_DWORD *)(4LL * i + a1);\n v9[2 * v3++ + 1] = 1;\n }\n }\n s = (char *)malloc(0x3E8uLL);\n *s = 0;\n *(_WORD *)&s[strlen(s)] = 123;\n for ( k = 0; k < v3; ++k )\n {\n sprintf(src, \"%d: %d\", v9[2 * k], v9[2 * k + 1]);\n strcat(s, src);\n if ( k < v3 - 1 )\n strcpy(&s[strlen(s)], \", \");\n }\n *(_WORD *)&s[strlen(s)] = 125;\n return s;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1229(long long a1, int a2) {\n int v3;\n int i;\n int v5;\n int j;\n int k;\n char *s;\n uint32_t v9[200];\n char src[56];\n unsigned long long v11;\n v11 = __readfsqword(40u);\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n v5 = 0;\n for (j = 0; j < v3; ++j) {\n if (v9[2 * j] == *(uint32_t *)(4LL * i + a1)) {\n ++v9[2 * j + 1];\n v5 = 1;\n break;\n }\n }\n if (!v5) {\n v9[2 * v3] = *(uint32_t *)(4LL * i + a1);\n v9[2 * v3++ + 1] = 1;\n }\n }\n s = (char *)malloc(1000uLL);\n *s = 0;\n *(unsigned short *)&s[strlen(s)] = 123;\n for (k = 0; k < v3; ++k) {\n sprintf(src, \"%d: %d\", v9[2 * k], v9[2 * k + 1]);\n strcat(s, src);\n if (k < v3 - 1) strcpy(&s[strlen(s)], \", \");\n }\n *(unsigned short *)&s[strlen(s)] = 125;\n return s;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2) {\n int v3;\n int i;\n int v5;\n int j;\n int k;\n char *s;\n uint32_t v9[200];\n char src[56];\n unsigned long long v11;\n v11 = __readfsqword(40u);\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n v5 = 0;\n for (j = 0; j < v3; ++j) {\n if (v9[2 * j] == *(uint32_t *)(4LL * i + a1)) {\n ++v9[2 * j + 1];\n v5 = 1;\n break;\n }\n }\n if (!v5) {\n v9[2 * v3] = *(uint32_t *)(4LL * i + a1);\n v9[2 * v3++ + 1] = 1;\n }\n }\n s = (char *)malloc(1000uLL);\n *s = 0;\n *(unsigned short *)&s[strlen(s)] = 123;\n for (k = 0; k < v3; ++k) {\n sprintf(src, \"%d: %d\", v9[2 * k], v9[2 * k + 1]);\n strcat(s, src);\n if (k < v3 - 1) strcpy(&s[strlen(s)], \", \");\n }\n *(unsigned short *)&s[strlen(s)] = 125;\n return s;\n}" + }, + { + "index": 686, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\nstruct dict {\n\n int key;\n\n int value;\n\n};\n\n\n\n", + "func": "char *func0(int test_tup[], int size) {\n struct dict freq[100];\n int count = 0;\n for (int i = 0; i < size; i++) {\n int found = 0;\n for (int j = 0; j < count; j++) {\n if (freq[j].key == test_tup[i]) {\n freq[j].value++;\n found = 1;\n break;\n }\n }\n if (!found) {\n freq[count].key = test_tup[i];\n freq[count].value = 1;\n count++;\n }\n }\n char *result = (char *)malloc(1000 * sizeof(char));\n char buffer[50];\n result[0] = '\\0';\n strcat(result, \"{\");\n for (int i = 0; i < count; i++) {\n sprintf(buffer, \"%d: %d\", freq[i].key, freq[i].value);\n strcat(result, buffer);\n if (i < count - 1) strcat(result, \", \");\n }\n strcat(result, \"}\");\n return result;\n}", + "test": "int main() {\n\n int tuple1[] = {4, 5, 4, 5, 6, 6, 5, 5, 4};\n\n char *res1 = func0(tuple1, sizeof(tuple1)/sizeof(tuple1[0]));\n\n assert(strcmp(res1, \"{4: 3, 5: 4, 6: 2}\") == 0);\n\n free(res1);\n\n\n\n int tuple2[] = {7, 8, 8, 9, 4, 7, 6, 5, 4};\n\n char *res2 = func0(tuple2, sizeof(tuple2)/sizeof(tuple2[0]));\n\n assert(strcmp(res2, \"{7: 2, 8: 2, 9: 1, 4: 2, 6: 1, 5: 1}\") == 0);\n\n free(res2);\n\n\n\n int tuple3[] = {1, 4, 3, 1, 4, 5, 2, 6, 2, 7};\n\n char *res3 = func0(tuple3, sizeof(tuple3)/sizeof(tuple3[0]));\n\n assert(strcmp(res3, \"{1: 2, 4: 2, 3: 1, 5: 1, 2: 2, 6: 1, 7: 1}\") == 0);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x360,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x358(%rsp)\nxor %eax,%eax\ntest %esi,%esi\njle 1318 \nmov %rdi,%r8\nlea -0x1(%rsi),%eax\nlea 0x4(%rdi,%rax,4),%r9\nmov $0x0,%ebx\nmov $0x0,%r10d\nmov %rsp,%rdi\njmp 1260 \nmov %rdx,%rax\ncmp %ecx,(%rdi,%rax,8)\nje 126f \nlea 0x1(%rax),%rdx\ncmp %rsi,%rax\njne 1232 \nmovslq %ebx,%rax\nmov (%r8),%edx\nmov %edx,(%rsp,%rax,8)\nmovl $0x1,0x4(%rsp,%rax,8)\nadd $0x1,%ebx\nadd $0x4,%r8\ncmp %r9,%r8\nje 1279 \ntest %ebx,%ebx\njle 1243 \nmov (%r8),%ecx\nlea -0x1(%rbx),%esi\nmov %r10,%rax\njmp 1235 \nmovslq %eax,%rdx\naddl $0x1,0x4(%rsp,%rdx,8)\njmp 1257 \nmov $0x3e8,%edi\ncallq 10e0 \nmov %rax,%r12\nmovb $0x0,(%rax)\nmov $0x3e8,%edx\nlea 0xd6f(%rip),%rsi\nmov %rax,%rdi\ncallq 10a0 <__strcat_chk@plt>\ntest %ebx,%ebx\njle 133c \nlea -0x1(%rbx),%r14d\nmov $0x0,%ebp\nlea 0x320(%rsp),%r13\njmp 12c4 \nlea 0x1(%rbp),%rax\ncmp %r14,%rbp\nje 133c \nmov %rax,%rbp\nmov 0x4(%rsp,%rbp,8),%r9d\nmov (%rsp,%rbp,8),%r8d\nlea 0xd32(%rip),%rcx\nmov $0x32,%edx\nmov $0x1,%esi\nmov %r13,%rdi\nmov $0x0,%eax\ncallq 10f0 <__sprintf_chk@plt>\nmov $0x3e8,%edx\nmov %r13,%rsi\nmov %r12,%rdi\ncallq 10a0 <__strcat_chk@plt>\nlea -0x1(%rbx),%eax\ncmp %ebp,%eax\njle 12b8 \nmov $0x3e8,%edx\nlea 0xcff(%rip),%rsi\nmov %r12,%rdi\ncallq 10a0 <__strcat_chk@plt>\njmp 12b8 \nmov $0x3e8,%edi\ncallq 10e0 \nmov %rax,%r12\nmovb $0x0,(%rax)\nmov $0x3e8,%edx\nlea 0xcd0(%rip),%rsi\nmov %rax,%rdi\ncallq 10a0 <__strcat_chk@plt>\nmov $0x3e8,%edx\nlea 0xcd9(%rip),%rsi\nmov %r12,%rdi\ncallq 10a0 <__strcat_chk@plt>\nmov 0x358(%rsp),%rax\nxor %fs:0x28,%rax\njne 1376 \nmov %r12,%rax\nadd $0x360,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\ncallq 10c0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 368h\nmov rax, fs:28h\nmov [rsp+398h+var_40], rax\nxor eax, eax\ntest esi, esi\njle loc_1330\nmov r8, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*4]\nmov ebp, 0\nmov rsi, rsp\njmp short loc_1273\nloc_124D:\ncdqe\nadd [rsp+rax*8+398h+var_394], 1\njmp short loc_126A\nloc_1256:\nmovsxd rax, ebp\nmov edx, [r8]\nmov [rsp+rax*8+398h+var_398], edx\nmov [rsp+rax*8+398h+var_394], 1\nadd ebp, 1\nloc_126A:\nadd r8, 4\ncmp r8, rdi\njz short loc_1292\nloc_1273:\ntest ebp, ebp\njle short loc_1256\nmov edx, [r8]\nmovsxd rcx, ebp\nmov eax, 0\nloc_1282:\ncmp [rsi+rax*8], edx\njz short loc_124D\nadd rax, 1\ncmp rax, rcx\njnz short loc_1282\njmp short loc_1256\nloc_1292:\nmov edi, 3E8h; size\ncall _malloc\nmov r12, rax\nmov byte ptr [rax], 0\nmov edx, 3E8h\nlea rsi, unk_2004\nmov rdi, rax\ncall ___strcat_chk\ntest ebp, ebp\njle loc_1354\nmovsxd r15, ebp\nmov ebx, 0\nlea r13, [rsp+398h+var_78]\nlea r14, aDD; \"%d: %d\"\nsub ebp, 1\njmp short loc_12E3\nloc_12DA:\nadd rbx, 1\ncmp rbx, r15\njz short loc_1354\nloc_12E3:\nmov r9d, [rsp+rbx*8+398h+var_394]\nmov r8d, [rsp+rbx*8+398h+var_398]\nmov rcx, r14\nmov edx, 32h ; '2'\nmov esi, 2\nmov rdi, r13\nmov eax, 0\ncall ___sprintf_chk\nmov edx, 3E8h\nmov rsi, r13\nmov rdi, r12\ncall ___strcat_chk\ncmp ebp, ebx\njle short loc_12DA\nmov edx, 3E8h\nlea rsi, asc_200D; \", \"\nmov rdi, r12\ncall ___strcat_chk\njmp short loc_12DA\nloc_1330:\nmov edi, 3E8h; size\ncall _malloc\nmov r12, rax\nmov byte ptr [rax], 0\nmov edx, 3E8h\nlea rsi, unk_2004\nmov rdi, rax\ncall ___strcat_chk\nloc_1354:\nmov edx, 3E8h\nlea rsi, s2+11h; \"}\"\nmov rdi, r12\ncall ___strcat_chk\nmov rax, [rsp+398h+var_40]\nsub rax, fs:28h\njnz short loc_1390\nmov rax, r12\nadd rsp, 368h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1390:\ncall ___stack_chk_fail", + "ida_pseudo": "_BYTE *__fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // r8\n _DWORD *v3; // rdi\n int v4; // ebp\n __int64 v5; // rax\n _BYTE *v6; // r12\n __int64 v7; // r15\n __int64 v8; // rbx\n int v9; // ebp\n _DWORD v11[200]; // [rsp+0h] [rbp-398h]\n _BYTE v12[56]; // [rsp+320h] [rbp-78h] BYREF\n unsigned __int64 v13; // [rsp+358h] [rbp-40h]\n\n v13 = __readfsqword(0x28u);\n if ( a2 <= 0 )\n {\n v6 = malloc(0x3E8uLL);\n *v6 = 0;\n __strcat_chk(v6, &unk_2004, 1000LL);\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n {\n if ( v4 <= 0 )\n {\nLABEL_4:\n v11[2 * v4] = *v2;\n v11[2 * v4++ + 1] = 1;\n }\n else\n {\n v5 = 0LL;\n while ( v11[2 * v5] != *v2 )\n {\n if ( ++v5 == v4 )\n goto LABEL_4;\n }\n ++v11[2 * (int)v5 + 1];\n }\n ++v2;\n }\n while ( v2 != v3 );\n v6 = malloc(0x3E8uLL);\n *v6 = 0;\n __strcat_chk(v6, &unk_2004, 1000LL);\n if ( v4 > 0 )\n {\n v7 = v4;\n v8 = 0LL;\n v9 = v4 - 1;\n do\n {\n __sprintf_chk(v12, 2LL, 50LL, \"%d: %d\", v11[2 * v8], v11[2 * v8 + 1]);\n __strcat_chk(v6, v12, 1000LL);\n if ( v9 > (int)v8 )\n __strcat_chk(v6, \", \", 1000LL);\n ++v8;\n }\n while ( v8 != v7 );\n }\n }\n __strcat_chk(v6, \"}\", 1000LL);\n return v6;\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 368h\nmov rax, fs:28h\nmov [rsp+398h+var_40], rax\nxor eax, eax\ntest esi, esi\njle loc_1330\nmov r8, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*4]\nmov ebp, 0\nmov rsi, rsp\njmp short loc_1273\nloc_124D:\ncdqe\nadd [rsp+rax*8+398h+var_394], 1\njmp short loc_126A\nloc_1256:\nmovsxd rax, ebp\nmov edx, [r8]\nmov [rsp+rax*8+398h+var_398], edx\nmov [rsp+rax*8+398h+var_394], 1\nadd ebp, 1\nloc_126A:\nadd r8, 4\ncmp r8, rdi\njz short loc_1292\nloc_1273:\ntest ebp, ebp\njle short loc_1256\nmov edx, [r8]\nmovsxd rcx, ebp\nmov eax, 0\nloc_1282:\ncmp [rsi+rax*8], edx\njz short loc_124D\nadd rax, 1\ncmp rax, rcx\njnz short loc_1282\njmp short loc_1256\nloc_1292:\nmov edi, 3E8h; size\ncall _malloc\nmov r12, rax\nmov byte ptr [rax], 0\nmov edx, 3E8h\nlea rsi, unk_2004\nmov rdi, rax\ncall ___strcat_chk\ntest ebp, ebp\njle loc_1354\nmovsxd r15, ebp\nmov ebx, 0\nlea r13, [rsp+398h+var_78]\nlea r14, aDD; \"%d: %d\"\nsub ebp, 1\njmp short loc_12E3\nloc_12DA:\nadd rbx, 1\ncmp rbx, r15\njz short loc_1354\nloc_12E3:\nmov r9d, [rsp+rbx*8+398h+var_394]\nmov r8d, [rsp+rbx*8+398h+var_398]\nmov rcx, r14\nmov edx, 32h ; '2'\nmov esi, 2\nmov rdi, r13\nmov eax, 0\ncall ___sprintf_chk\nmov edx, 3E8h\nmov rsi, r13\nmov rdi, r12\ncall ___strcat_chk\ncmp ebp, ebx\njle short loc_12DA\nmov edx, 3E8h\nlea rsi, asc_200D; \", \"\nmov rdi, r12\ncall ___strcat_chk\njmp short loc_12DA\nloc_1330:\nmov edi, 3E8h; size\ncall _malloc\nmov r12, rax\nmov byte ptr [rax], 0\nmov edx, 3E8h\nlea rsi, unk_2004\nmov rdi, rax\ncall ___strcat_chk\nloc_1354:\nmov edx, 3E8h\nlea rsi, s2+11h; \"}\"\nmov rdi, r12\ncall ___strcat_chk\nmov rax, [rsp+398h+var_40]\nsub rax, fs:28h\njnz short loc_1390\nmov rax, r12\nadd rsp, 368h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1390:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1209(_DWORD *a1, int a2)\n{\n _DWORD *v2; // r8\n _DWORD *v3; // rdi\n int v4; // ebp\n __int64 v5; // rax\n _BYTE *v6; // r12\n __int64 v7; // r15\n __int64 v8; // rbx\n int v9; // ebp\n _DWORD v11[200]; // [rsp+0h] [rbp-398h]\n _BYTE v12[56]; // [rsp+320h] [rbp-78h] BYREF\n unsigned __int64 v13; // [rsp+358h] [rbp-40h]\n\n v13 = __readfsqword(0x28u);\n if ( a2 <= 0 )\n {\n v6 = malloc(0x3E8uLL);\n *v6 = 0;\n __strcat_chk(v6, &unk_2004, 1000LL);\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n {\n if ( v4 <= 0 )\n {\nLABEL_4:\n v11[2 * v4] = *v2;\n v11[2 * v4++ + 1] = 1;\n }\n else\n {\n v5 = 0LL;\n while ( v11[2 * v5] != *v2 )\n {\n if ( ++v5 == v4 )\n goto LABEL_4;\n }\n ++v11[2 * (int)v5 + 1];\n }\n ++v2;\n }\n while ( v2 != v3 );\n v6 = malloc(0x3E8uLL);\n *v6 = 0;\n __strcat_chk(v6, &unk_2004, 1000LL);\n if ( v4 > 0 )\n {\n v7 = v4;\n v8 = 0LL;\n v9 = v4 - 1;\n do\n {\n __sprintf_chk(v12, 2LL, 50LL, \"%d: %d\", v11[2 * v8], v11[2 * v8 + 1]);\n __strcat_chk(v6, v12, 1000LL);\n if ( v9 > (int)v8 )\n __strcat_chk(v6, \", \", 1000LL);\n ++v8;\n }\n while ( v8 != v7 );\n }\n }\n __strcat_chk(v6, \"}\", 1000LL);\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1209(uint32_t *a1, int a2) {\n uint32_t *v2;\n uint32_t *v3;\n int v4;\n long long v5;\n uint8_t *v6;\n long long v7;\n long long v8;\n int v9;\n uint32_t v11[200];\n uint8_t v12[56];\n unsigned long long v13;\n v13 = __readfsqword(40u);\n if (a2 <= 0) {\n v6 = malloc(1000uLL);\n *v6 = 0;\n __strcat_chk(v6, &unk_2004, 1000LL);\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do {\n if (v4 <= 0) {\n LABEL_4:\n v11[2 * v4] = *v2;\n v11[2 * v4++ + 1] = 1;\n } else {\n v5 = 0LL;\n while (v11[2 * v5] != *v2) {\n if (++v5 == v4) goto LABEL_4;\n }\n ++v11[2 * (int)v5 + 1];\n }\n ++v2;\n } while (v2 != v3);\n v6 = malloc(1000uLL);\n *v6 = 0;\n __strcat_chk(v6, &unk_2004, 1000LL);\n if (v4 > 0) {\n v7 = v4;\n v8 = 0LL;\n v9 = v4 - 1;\n do {\n __sprintf_chk(v12, 2LL, 50LL, \"%d: %d\", v11[2 * v8], v11[2 * v8 + 1]);\n __strcat_chk(v6, v12, 1000LL);\n if (v9 > (int)v8) __strcat_chk(v6, \", \", 1000LL);\n ++v8;\n } while (v8 != v7);\n }\n }\n __strcat_chk(v6, \"}\", 1000LL);\n return v6;\n}", + "ida_pseudo_norm": "uint8_t *func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n uint32_t *v3;\n int v4;\n long long v5;\n uint8_t *v6;\n long long v7;\n long long v8;\n int v9;\n uint32_t v11[200];\n uint8_t v12[56];\n unsigned long long v13;\n v13 = __readfsqword(40u);\n if (a2 <= 0) {\n v6 = malloc(1000uLL);\n *v6 = 0;\n __strcat_chk(v6, &unk_2004, 1000LL);\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do {\n if (v4 <= 0) {\n LABEL_4:\n v11[2 * v4] = *v2;\n v11[2 * v4++ + 1] = 1;\n } else {\n v5 = 0LL;\n while (v11[2 * v5] != *v2) {\n if (++v5 == v4) goto LABEL_4;\n }\n ++v11[2 * (int)v5 + 1];\n }\n ++v2;\n } while (v2 != v3);\n v6 = malloc(1000uLL);\n *v6 = 0;\n __strcat_chk(v6, &unk_2004, 1000LL);\n if (v4 > 0) {\n v7 = v4;\n v8 = 0LL;\n v9 = v4 - 1;\n do {\n __sprintf_chk(v12, 2LL, 50LL, \"%d: %d\", v11[2 * v8], v11[2 * v8 + 1]);\n __strcat_chk(v6, v12, 1000LL);\n if (v9 > (int)v8) __strcat_chk(v6, \", \", 1000LL);\n ++v8;\n } while (v8 != v7);\n }\n }\n __strcat_chk(v6, \"}\", 1000LL);\n return v6;\n}" + }, + { + "index": 686, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\nstruct dict {\n\n int key;\n\n int value;\n\n};\n\n\n\n", + "func": "char *func0(int test_tup[], int size) {\n struct dict freq[100];\n int count = 0;\n for (int i = 0; i < size; i++) {\n int found = 0;\n for (int j = 0; j < count; j++) {\n if (freq[j].key == test_tup[i]) {\n freq[j].value++;\n found = 1;\n break;\n }\n }\n if (!found) {\n freq[count].key = test_tup[i];\n freq[count].value = 1;\n count++;\n }\n }\n char *result = (char *)malloc(1000 * sizeof(char));\n char buffer[50];\n result[0] = '\\0';\n strcat(result, \"{\");\n for (int i = 0; i < count; i++) {\n sprintf(buffer, \"%d: %d\", freq[i].key, freq[i].value);\n strcat(result, buffer);\n if (i < count - 1) strcat(result, \", \");\n }\n strcat(result, \"}\");\n return result;\n}", + "test": "int main() {\n\n int tuple1[] = {4, 5, 4, 5, 6, 6, 5, 5, 4};\n\n char *res1 = func0(tuple1, sizeof(tuple1)/sizeof(tuple1[0]));\n\n assert(strcmp(res1, \"{4: 3, 5: 4, 6: 2}\") == 0);\n\n free(res1);\n\n\n\n int tuple2[] = {7, 8, 8, 9, 4, 7, 6, 5, 4};\n\n char *res2 = func0(tuple2, sizeof(tuple2)/sizeof(tuple2[0]));\n\n assert(strcmp(res2, \"{7: 2, 8: 2, 9: 1, 4: 2, 6: 1, 5: 1}\") == 0);\n\n free(res2);\n\n\n\n int tuple3[] = {1, 4, 3, 1, 4, 5, 2, 6, 2, 7};\n\n char *res3 = func0(tuple3, sizeof(tuple3)/sizeof(tuple3[0]));\n\n assert(strcmp(res3, \"{1: 2, 4: 2, 3: 1, 5: 1, 2: 2, 6: 1, 7: 1}\") == 0);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x378,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x368(%rsp)\nxor %eax,%eax\ntest %esi,%esi\njle 15e7 \nlea -0x1(%rsi),%eax\nxor %ebx,%ebx\nlea 0x10(%rsp),%r15\nlea 0x4(%rdi,%rax,4),%r8\nmov (%rdi),%ecx\nlea -0x1(%rbx),%esi\nxor %eax,%eax\ntest %ebx,%ebx\njne 14a0 \njmpq 15d0 \nlea 0x1(%rax),%rdx\ncmp %rax,%rsi\nje 15d0 \nmov %rdx,%rax\nmovslq %eax,%rdx\ncmp %ecx,(%r15,%rax,8)\njne 1490 \naddl $0x1,0x14(%rsp,%rdx,8)\nadd $0x4,%rdi\ncmp %r8,%rdi\njne 1480 \nmov $0x3e8,%edi\nxor %r14d,%r14d\nlea 0x330(%rsp),%rbp\ncallq 1120 \nmov $0x7b,%edx\nlea 0xb2c(%rip),%r13\nmov %dx,(%rax)\nmov %rax,%r12\nlea -0x1(%rbx),%eax\nmov %rax,0x8(%rsp)\nmov %rax,%rbx\njmp 14f3 \nnopl 0x0(%rax,%rax,1)\nmov %rax,%r14\nmov 0x4(%r15,%r14,8),%r9d\nmov (%r15,%r14,8),%r8d\nmov %rbp,%rdi\nmov %r13,%rcx\nmov $0x32,%edx\nmov $0x1,%esi\nxor %eax,%eax\ncallq 1130 <__sprintf_chk@plt>\nmov %r12,%rdi\nmov (%rdi),%edx\nadd $0x4,%rdi\nlea -0x1010101(%rdx),%eax\nnot %edx\nand %edx,%eax\nand $0x80808080,%eax\nje 1516 \nmov %eax,%edx\nshr $0x10,%edx\ntest $0x8080,%eax\ncmove %edx,%eax\nlea 0x2(%rdi),%rdx\ncmove %rdx,%rdi\nmov $0x3e8,%edx\nmov %eax,%esi\nadd %al,%sil\nmov %rbp,%rsi\nsbb $0x3,%rdi\ncallq 1110 <__stpcpy_chk@plt>\ncmp %r14d,%ebx\njle 157e \nmov %r12,%rcx\nmov $0x3,%edx\nlea 0xa9f(%rip),%rsi\nmov %rax,%rdi\nsub %rax,%rcx\nadd $0x3e8,%rcx\ncallq 1100 <__memcpy_chk@plt>\nlea 0x1(%r14),%rax\ncmp 0x8(%rsp),%r14\njne 14f0 \nmov $0x3e8,%edx\nlea 0xa86(%rip),%rsi\nmov %r12,%rdi\ncallq 10c0 <__strcat_chk@plt>\nmov 0x368(%rsp),%rax\nxor %fs:0x28,%rax\njne 1600 \nadd $0x378,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\nmovslq %ebx,%rax\nadd $0x1,%ebx\nmov %ecx,0x10(%rsp,%rax,8)\nmovl $0x1,0x14(%rsp,%rax,8)\njmpq 14ae \nmov $0x3e8,%edi\ncallq 1120 \nmov %rax,%r12\nmov $0x7b,%eax\nmov %ax,(%r12)\njmp 158d \ncallq 10e0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 368h\nmov rax, fs:28h\nmov [rsp+398h+var_40], rax\nxor eax, eax\ntest esi, esi\njle loc_1581\nmovsxd rsi, esi\nxor ebx, ebx\nmov r15, rsp\nlea rsi, [rdi+rsi*4]\nnop dword ptr [rax+00h]\nloc_1450:\nmov edx, [rdi]\nmovsxd rcx, ebx\ntest ebx, ebx\njle short loc_1488\nloc_1459:\nxor eax, eax\njmp short loc_1469\nloc_1460:\nadd rax, 1\ncmp rax, rcx\njz short loc_1488\nloc_1469:\ncmp [r15+rax*8], edx\njnz short loc_1460\ncdqe\nadd rdi, 4\nadd [rsp+rax*8+398h+var_394], 1\ncmp rdi, rsi\njz short loc_149F\nmov edx, [rdi]\njmp short loc_1459\nloc_1488:\nadd rdi, 4\nmov [rsp+rcx*8+398h+var_398], edx\nadd ebx, 1\nmov [rsp+rcx*8+398h+var_394], 1\ncmp rdi, rsi\njnz short loc_1450\nloc_149F:\nmov edi, 3E8h; size\ncall _malloc\nmov edx, 7Bh ; '{'\nmov [rax], dx\nmov rbp, rax\ntest ebx, ebx\njle loc_1545\nlea r14d, [rbx-1]\nxor r13d, r13d\nmovsxd rbx, ebx\nmov r15, rsp\nlea r12, [rsp+398h+var_78]\nnop dword ptr [rax+00000000h]\nloc_14D8:\nmov r9d, [r15+r13*8+4]\nmov r8d, [r15+r13*8]\nmov edx, 32h ; '2'\nxor eax, eax\nmov esi, 2\nlea rcx, aDD; \"%d: %d\"\nmov rdi, r12\ncall ___sprintf_chk\nmov rdi, rbp; s\ncall _strlen\nmov edx, 3E8h\nmov rsi, r12\nlea rdi, [rbp+rax+0]\ncall ___stpcpy_chk\ncmp r14d, r13d\njle short loc_153C\nmov rcx, rbp\nmov edx, 3\nlea rsi, asc_200B; \", \"\nmov rdi, rax\nsub rcx, rax\nadd rcx, 3E8h\ncall ___memcpy_chk\nloc_153C:\nadd r13, 1\ncmp r13, rbx\njnz short loc_14D8\nloc_1545:\nmov edx, 3E8h\nlea rsi, s2+11h; \"}\"\nmov rdi, rbp\ncall ___strcat_chk\nmov rax, [rsp+398h+var_40]\nsub rax, fs:28h\njnz short loc_1599\nadd rsp, 368h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1581:\nmov edi, 3E8h; size\ncall _malloc\nmov rbp, rax\nmov eax, 7Bh ; '{'\nmov [rbp+0], ax\njmp short loc_1545\nloc_1599:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(int *a1, int a2)\n{\n int v2; // ebx\n int *v3; // rsi\n int v4; // edx\n __int64 v5; // rcx\n __int64 v6; // rax\n char *v7; // rax\n char *v8; // rbp\n __int64 i; // r13\n size_t v10; // rax\n __int64 v11; // rax\n _DWORD v13[200]; // [rsp+0h] [rbp-398h] BYREF\n _BYTE v14[56]; // [rsp+320h] [rbp-78h] BYREF\n unsigned __int64 v15; // [rsp+358h] [rbp-40h]\n\n v15 = __readfsqword(0x28u);\n if ( a2 <= 0 )\n {\n v8 = (char *)malloc(0x3E8uLL);\n *(_WORD *)v8 = 123;\n }\n else\n {\n v2 = 0;\n v3 = &a1[a2];\n while ( 1 )\n {\n v4 = *a1;\n v5 = v2;\n if ( v2 > 0 )\n break;\nLABEL_9:\n ++a1;\n v13[2 * v2++] = v4;\n v13[2 * v5 + 1] = 1;\n if ( a1 == v3 )\n goto LABEL_10;\n }\n while ( 1 )\n {\n v6 = 0LL;\n while ( v13[2 * v6] != v4 )\n {\n if ( ++v6 == v2 )\n goto LABEL_9;\n }\n ++a1;\n ++v13[2 * (int)v6 + 1];\n if ( a1 == v3 )\n break;\n v4 = *a1;\n }\nLABEL_10:\n v7 = (char *)malloc(0x3E8uLL);\n *(_WORD *)v7 = 123;\n v8 = v7;\n if ( v2 > 0 )\n {\n for ( i = 0LL; i != v2; ++i )\n {\n __sprintf_chk(v14, 2LL, 50LL, \"%d: %d\", v13[2 * i], v13[2 * i + 1]);\n v10 = strlen(v8);\n v11 = __stpcpy_chk(&v8[v10], v14, 1000LL);\n if ( v2 - 1 > (int)i )\n __memcpy_chk(v11, \", \", 3LL, &v8[-v11 + 1000]);\n }\n }\n }\n __strcat_chk(v8, \"}\", 1000LL);\n return v8;\n}", + "ida_strip_asm": "sub_1410:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 368h\nmov rax, fs:28h\nmov [rsp+398h+var_40], rax\nxor eax, eax\ntest esi, esi\njle loc_1581\nmovsxd rsi, esi\nxor ebx, ebx\nmov r15, rsp\nlea rsi, [rdi+rsi*4]\nnop dword ptr [rax+00h]\nloc_1450:\nmov edx, [rdi]\nmovsxd rcx, ebx\ntest ebx, ebx\njle short loc_1488\nloc_1459:\nxor eax, eax\njmp short loc_1469\nloc_1460:\nadd rax, 1\ncmp rax, rcx\njz short loc_1488\nloc_1469:\ncmp [r15+rax*8], edx\njnz short loc_1460\ncdqe\nadd rdi, 4\nadd [rsp+rax*8+398h+var_394], 1\ncmp rdi, rsi\njz short loc_149F\nmov edx, [rdi]\njmp short loc_1459\nloc_1488:\nadd rdi, 4\nmov [rsp+rcx*8+398h+var_398], edx\nadd ebx, 1\nmov [rsp+rcx*8+398h+var_394], 1\ncmp rdi, rsi\njnz short loc_1450\nloc_149F:\nmov edi, 3E8h; size\ncall _malloc\nmov edx, 7Bh ; '{'\nmov [rax], dx\nmov rbp, rax\ntest ebx, ebx\njle loc_1545\nlea r14d, [rbx-1]\nxor r13d, r13d\nmovsxd rbx, ebx\nmov r15, rsp\nlea r12, [rsp+398h+var_78]\nnop dword ptr [rax+00000000h]\nloc_14D8:\nmov r9d, [r15+r13*8+4]\nmov r8d, [r15+r13*8]\nmov edx, 32h ; '2'\nxor eax, eax\nmov esi, 2\nlea rcx, aDD; \"%d: %d\"\nmov rdi, r12\ncall ___sprintf_chk\nmov rdi, rbp; s\ncall _strlen\nmov edx, 3E8h\nmov rsi, r12\nlea rdi, [rbp+rax+0]\ncall ___stpcpy_chk\ncmp r14d, r13d\njle short loc_153C\nmov rcx, rbp\nmov edx, 3\nlea rsi, asc_200B; \", \"\nmov rdi, rax\nsub rcx, rax\nadd rcx, 3E8h\ncall ___memcpy_chk\nloc_153C:\nadd r13, 1\ncmp r13, rbx\njnz short loc_14D8\nloc_1545:\nmov edx, 3E8h\nlea rsi, s2+11h; \"}\"\nmov rdi, rbp\ncall ___strcat_chk\nmov rax, [rsp+398h+var_40]\nsub rax, fs:28h\njnz short loc_1599\nadd rsp, 368h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1581:\nmov edi, 3E8h; size\ncall _malloc\nmov rbp, rax\nmov eax, 7Bh ; '{'\nmov [rbp+0], ax\njmp short loc_1545\nloc_1599:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_1410(int *a1, int a2)\n{\n int v2; // ebx\n int *v3; // rsi\n int v4; // edx\n __int64 v5; // rcx\n __int64 v6; // rax\n char *v7; // rax\n char *v8; // rbp\n __int64 i; // r13\n size_t v10; // rax\n __int64 v11; // rax\n _DWORD v13[200]; // [rsp+0h] [rbp-398h] BYREF\n _BYTE v14[56]; // [rsp+320h] [rbp-78h] BYREF\n unsigned __int64 v15; // [rsp+358h] [rbp-40h]\n\n v15 = __readfsqword(0x28u);\n if ( a2 <= 0 )\n {\n v8 = (char *)malloc(0x3E8uLL);\n *(_WORD *)v8 = 123;\n }\n else\n {\n v2 = 0;\n v3 = &a1[a2];\n while ( 1 )\n {\n v4 = *a1;\n v5 = v2;\n if ( v2 > 0 )\n break;\nLABEL_9:\n ++a1;\n v13[2 * v2++] = v4;\n v13[2 * v5 + 1] = 1;\n if ( a1 == v3 )\n goto LABEL_10;\n }\n while ( 1 )\n {\n v6 = 0LL;\n while ( v13[2 * v6] != v4 )\n {\n if ( ++v6 == v2 )\n goto LABEL_9;\n }\n ++a1;\n ++v13[2 * (int)v6 + 1];\n if ( a1 == v3 )\n break;\n v4 = *a1;\n }\nLABEL_10:\n v7 = (char *)malloc(0x3E8uLL);\n *(_WORD *)v7 = 123;\n v8 = v7;\n if ( v2 > 0 )\n {\n for ( i = 0LL; i != v2; ++i )\n {\n __sprintf_chk(v14, 2LL, 50LL, \"%d: %d\", v13[2 * i], v13[2 * i + 1]);\n v10 = strlen(v8);\n v11 = __stpcpy_chk(&v8[v10], v14, 1000LL);\n if ( v2 - 1 > (int)i )\n __memcpy_chk(v11, \", \", 3LL, &v8[-v11 + 1000]);\n }\n }\n }\n __strcat_chk(v8, \"}\", 1000LL);\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1410(int *a1, int a2) {\n int v2;\n int *v3;\n int v4;\n long long v5;\n long long v6;\n char *v7;\n char *v8;\n long long i;\n unsigned int v10;\n long long v11;\n uint32_t v13[200];\n uint8_t v14[56];\n unsigned long long v15;\n v15 = __readfsqword(40u);\n if (a2 <= 0) {\n v8 = (char *)malloc(1000uLL);\n *(unsigned short *)v8 = 123;\n } else {\n v2 = 0;\n v3 = &a1[a2];\n while (1) {\n v4 = *a1;\n v5 = v2;\n if (v2 > 0) break;\n LABEL_9:\n ++a1;\n v13[2 * v2++] = v4;\n v13[2 * v5 + 1] = 1;\n if (a1 == v3) goto LABEL_10;\n }\n while (1) {\n v6 = 0LL;\n while (v13[2 * v6] != v4) {\n if (++v6 == v2) goto LABEL_9;\n }\n ++a1;\n ++v13[2 * (int)v6 + 1];\n if (a1 == v3) break;\n v4 = *a1;\n }\n LABEL_10:\n v7 = (char *)malloc(1000uLL);\n *(unsigned short *)v7 = 123;\n v8 = v7;\n if (v2 > 0) {\n for (i = 0LL; i != v2; ++i) {\n __sprintf_chk(v14, 2LL, 50LL, \"%d: %d\", v13[2 * i], v13[2 * i + 1]);\n v10 = strlen(v8);\n v11 = __stpcpy_chk(&v8[v10], v14, 1000LL);\n if (v2 - 1 > (int)i) __memcpy_chk(v11, \", \", 3LL, &v8[-v11 + 1000]);\n }\n }\n }\n __strcat_chk(v8, \"}\", 1000LL);\n return v8;\n}", + "ida_pseudo_norm": "char *func0(int *a1, int a2) {\n int v2;\n int *v3;\n int v4;\n long long v5;\n long long v6;\n char *v7;\n char *v8;\n long long i;\n unsigned int v10;\n long long v11;\n uint32_t v13[200];\n uint8_t v14[56];\n unsigned long long v15;\n v15 = __readfsqword(40u);\n if (a2 <= 0) {\n v8 = (char *)malloc(1000uLL);\n *(unsigned short *)v8 = 123;\n } else {\n v2 = 0;\n v3 = &a1[a2];\n while (1) {\n v4 = *a1;\n v5 = v2;\n if (v2 > 0) break;\n LABEL_9:\n ++a1;\n v13[2 * v2++] = v4;\n v13[2 * v5 + 1] = 1;\n if (a1 == v3) goto LABEL_10;\n }\n while (1) {\n v6 = 0LL;\n while (v13[2 * v6] != v4) {\n if (++v6 == v2) goto LABEL_9;\n }\n ++a1;\n ++v13[2 * (int)v6 + 1];\n if (a1 == v3) break;\n v4 = *a1;\n }\n LABEL_10:\n v7 = (char *)malloc(1000uLL);\n *(unsigned short *)v7 = 123;\n v8 = v7;\n if (v2 > 0) {\n for (i = 0LL; i != v2; ++i) {\n __sprintf_chk(v14, 2LL, 50LL, \"%d: %d\", v13[2 * i], v13[2 * i + 1]);\n v10 = strlen(v8);\n v11 = __stpcpy_chk(&v8[v10], v14, 1000LL);\n if (v2 - 1 > (int)i) __memcpy_chk(v11, \", \", 3LL, &v8[-v11 + 1000]);\n }\n }\n }\n __strcat_chk(v8, \"}\", 1000LL);\n return v8;\n}" + }, + { + "index": 686, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\nstruct dict {\n\n int key;\n\n int value;\n\n};\n\n\n\n", + "func": "char *func0(int test_tup[], int size) {\n struct dict freq[100];\n int count = 0;\n for (int i = 0; i < size; i++) {\n int found = 0;\n for (int j = 0; j < count; j++) {\n if (freq[j].key == test_tup[i]) {\n freq[j].value++;\n found = 1;\n break;\n }\n }\n if (!found) {\n freq[count].key = test_tup[i];\n freq[count].value = 1;\n count++;\n }\n }\n char *result = (char *)malloc(1000 * sizeof(char));\n char buffer[50];\n result[0] = '\\0';\n strcat(result, \"{\");\n for (int i = 0; i < count; i++) {\n sprintf(buffer, \"%d: %d\", freq[i].key, freq[i].value);\n strcat(result, buffer);\n if (i < count - 1) strcat(result, \", \");\n }\n strcat(result, \"}\");\n return result;\n}", + "test": "int main() {\n\n int tuple1[] = {4, 5, 4, 5, 6, 6, 5, 5, 4};\n\n char *res1 = func0(tuple1, sizeof(tuple1)/sizeof(tuple1[0]));\n\n assert(strcmp(res1, \"{4: 3, 5: 4, 6: 2}\") == 0);\n\n free(res1);\n\n\n\n int tuple2[] = {7, 8, 8, 9, 4, 7, 6, 5, 4};\n\n char *res2 = func0(tuple2, sizeof(tuple2)/sizeof(tuple2[0]));\n\n assert(strcmp(res2, \"{7: 2, 8: 2, 9: 1, 4: 2, 6: 1, 5: 1}\") == 0);\n\n free(res2);\n\n\n\n int tuple3[] = {1, 4, 3, 1, 4, 5, 2, 6, 2, 7};\n\n char *res3 = func0(tuple3, sizeof(tuple3)/sizeof(tuple3[0]));\n\n assert(strcmp(res3, \"{1: 2, 4: 2, 3: 1, 5: 1, 2: 2, 6: 1, 7: 1}\") == 0);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x378,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x368(%rsp)\nxor %eax,%eax\ntest %esi,%esi\njle 15f8 \nlea -0x1(%rsi),%eax\nxor %r12d,%r12d\nlea 0x10(%rsp),%r15\nlea 0x4(%rdi,%rax,4),%r8\nmov (%rdi),%ecx\nlea -0x1(%r12),%esi\nxor %eax,%eax\ntest %r12d,%r12d\njne 1448 \njmpq 1520 \nnopl 0x0(%rax,%rax,1)\nlea 0x1(%rax),%rdx\ncmp %rsi,%rax\nje 1520 \nmov %rdx,%rax\nmovslq %eax,%rdx\ncmp %ecx,(%r15,%rax,8)\njne 1438 \naddl $0x1,0x14(%rsp,%rdx,8)\nadd $0x4,%rdi\ncmp %r8,%rdi\njne 1420 \nmov $0x3e8,%edi\ncallq 1120 \nmov $0x7b,%edx\nmov %dx,(%rax)\nmov %rax,%r14\nlea -0x1(%r12),%eax\nmov %eax,0xc(%rsp)\ntest %eax,%eax\njg 1540 \nxor %ebx,%ebx\nlea 0x330(%rsp),%r13\nmovslq %ebx,%rbx\nlea 0xb6b(%rip),%rbp\nnopl 0x0(%rax)\nmov 0x4(%r15,%rbx,8),%r9d\nmov (%r15,%rbx,8),%r8d\nmov %rbp,%rcx\nmov %r13,%rdi\nmov $0x32,%edx\nmov $0x1,%esi\nxor %eax,%eax\nadd $0x1,%rbx\ncallq 1130 <__sprintf_chk@plt>\nmov $0x3e8,%edx\nmov %r13,%rsi\nmov %r14,%rdi\ncallq 10c0 <__strcat_chk@plt>\ncmp %ebx,%r12d\njg 14a0 \nmov $0x3e8,%edx\nlea 0xb3a(%rip),%rsi\nmov %r14,%rdi\ncallq 10c0 <__strcat_chk@plt>\nmov 0x368(%rsp),%rax\nxor %fs:0x28,%rax\njne 1613 \nadd $0x378,%rsp\nmov %r14,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\nmovslq %r12d,%rax\nadd $0x1,%r12d\nmov %ecx,0x10(%rsp,%rax,8)\nmovl $0x1,0x14(%rsp,%rax,8)\njmpq 1456 \nnopl 0x0(%rax,%rax,1)\nmov %r15,%rbp\nxor %ebx,%ebx\nlea 0x330(%rsp),%r13\nnopl (%rax)\nmov 0x4(%rbp),%r9d\nmov 0x0(%rbp),%r8d\nmov %r13,%rdi\nmov $0x32,%edx\nlea 0xa9d(%rip),%rcx\nmov $0x1,%esi\nxor %eax,%eax\ncallq 1130 <__sprintf_chk@plt>\nmov %r14,%rdi\nmov (%rdi),%edx\nadd $0x4,%rdi\nlea -0x1010101(%rdx),%eax\nnot %edx\nand %edx,%eax\nand $0x80808080,%eax\nje 1576 \nmov %eax,%edx\nshr $0x10,%edx\ntest $0x8080,%eax\ncmove %edx,%eax\nlea 0x2(%rdi),%rdx\ncmove %rdx,%rdi\nmov $0x3e8,%edx\nmov %eax,%esi\nadd %al,%sil\nmov %r13,%rsi\nsbb $0x3,%rdi\nadd $0x1,%ebx\nadd $0x8,%rbp\ncallq 1110 <__stpcpy_chk@plt>\nmov %r14,%rcx\nmov $0x3,%edx\nlea 0xa3d(%rip),%rsi\nsub %rax,%rcx\nmov %rax,%rdi\nadd $0x3e8,%rcx\ncallq 1100 <__memcpy_chk@plt>\ncmp 0xc(%rsp),%ebx\njl 1550 \ncmp %ebx,%r12d\njg 148f \njmpq 14d9 \nmov $0x3e8,%edi\ncallq 1120 \nmov %rax,%r14\nmov $0x7b,%eax\nmov %ax,(%r14)\njmpq 14d9 \ncallq 10e0 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 378h\nmov rax, fs:28h\nmov [rsp+3A8h+var_40], rax\nxor eax, eax\ntest esi, esi\njle loc_1602\nmovsxd rsi, esi\nxor r15d, r15d\nlea rbx, [rsp+3A8h+var_398]\nlea r8, [rdi+rsi*4]\nnop\nloc_1450:\nmov edx, [rdi]\nmovsxd rcx, r15d\ntest r15d, r15d\njle short loc_1488\nloc_145A:\nxor eax, eax\njmp short loc_1469\nloc_1460:\nadd rax, 1\ncmp rax, rcx\njz short loc_1488\nloc_1469:\ncmp [rbx+rax*8], edx\njnz short loc_1460\ncdqe\nadd rdi, 4\nadd [rsp+rax*8+3A8h+var_394], 1\ncmp rdi, r8\njz short loc_14A1\nmov edx, [rdi]\njmp short loc_145A\nloc_1488:\nadd rdi, 4\nmov [rsp+rcx*8+3A8h+var_398], edx\nadd r15d, 1\nmov [rsp+rcx*8+3A8h+var_394], 1\ncmp rdi, r8\njnz short loc_1450\nloc_14A1:\nmov edi, 3E8h; size\ncall _malloc\nmov edx, 7Bh ; '{'\nmov [rax], dx\nmov r12, rax\ntest r15d, r15d\njle short loc_1519\nlea edx, [r15-1]\ntest edx, edx\njg loc_1559\nxor ebp, ebp\nlea rbx, [rsp+3A8h+var_398]\nlea r13, [rsp+3A8h+var_78]\nlea r14, aDD; \"%d: %d\"\nnop dword ptr [rax]\nloc_14E0:\nmov r9d, [rbx+rbp*8+4]\nmov r8d, [rbx+rbp*8]\nmov rcx, r14\nmov rdi, r13\nmov edx, 32h ; '2'\nmov esi, 2\nxor eax, eax\nadd rbp, 1\ncall ___sprintf_chk\nmov edx, 3E8h\nmov rsi, r13\nmov rdi, r12\ncall ___strcat_chk\ncmp r15d, ebp\njg short loc_14E0\nloc_1519:\nmov edx, 3E8h\nlea rsi, s2+11h; \"}\"\nmov rdi, r12\ncall ___strcat_chk\nmov rax, [rsp+3A8h+var_40]\nsub rax, fs:28h\njnz loc_161E\nadd rsp, 378h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1559:\nlea rbx, [rsp+3A8h+var_398]\nxor ebp, ebp\nmov [rsp+3A8h+var_3A4], r15d\nlea r13, [rsp+3A8h+var_78]\nmov [rsp+3A8h+var_3A0], rbx\nmov r15d, ebp\nlea r14, aDD; \"%d: %d\"\nmov rbp, rbx\nmov ebx, edx\nloc_1581:\nmov r9d, [rbp+4]\nmov r8d, [rbp+0]\nmov rcx, r14\nmov edx, 32h ; '2'\nmov esi, 2\nmov rdi, r13\nxor eax, eax\nadd r15d, 1\ncall ___sprintf_chk\nmov rdi, r12; s\nadd rbp, 8\ncall _strlen\nmov edx, 3E8h\nmov rsi, r13\nlea rdi, [r12+rax]\ncall ___stpcpy_chk\nmov rcx, r12\nmov edx, 3\nlea rsi, asc_200B; \", \"\nsub rcx, rax\nmov rdi, rax\nadd rcx, 3E8h\ncall ___memcpy_chk\ncmp r15d, ebx\njl short loc_1581\nmovsxd rbp, r15d\nmov r15d, [rsp+3A8h+var_3A4]\nmov rbx, [rsp+3A8h+var_3A0]\ncmp ebp, r15d\njl loc_14E0\njmp loc_1519\nloc_1602:\nmov edi, 3E8h; size\ncall _malloc\nmov r12, rax\nmov eax, 7Bh ; '{'\nmov [r12], ax\njmp loc_1519\nloc_161E:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(int *a1, int a2)\n{\n int v2; // r15d\n int *v3; // r8\n int v4; // edx\n __int64 v5; // rcx\n __int64 v6; // rax\n char *v7; // rax\n char *v8; // r12\n int v9; // edx\n __int64 v10; // rbp\n int v11; // r9d\n int v12; // r8d\n int v14; // r15d\n _DWORD *v15; // rbp\n int v16; // ebx\n size_t v17; // rax\n __int64 v18; // rax\n int v19; // [rsp+4h] [rbp-3A4h]\n _DWORD v20[200]; // [rsp+10h] [rbp-398h] BYREF\n _BYTE v21[56]; // [rsp+330h] [rbp-78h] BYREF\n unsigned __int64 v22; // [rsp+368h] [rbp-40h]\n\n v22 = __readfsqword(0x28u);\n if ( a2 <= 0 )\n {\n v8 = (char *)malloc(0x3E8uLL);\n *(_WORD *)v8 = 123;\n goto LABEL_14;\n }\n v2 = 0;\n v3 = &a1[a2];\n while ( 1 )\n {\n v4 = *a1;\n v5 = v2;\n if ( v2 > 0 )\n break;\nLABEL_9:\n ++a1;\n v20[2 * v2++] = v4;\n v20[2 * v5 + 1] = 1;\n if ( a1 == v3 )\n goto LABEL_10;\n }\n while ( 1 )\n {\n v6 = 0LL;\n while ( v20[2 * v6] != v4 )\n {\n if ( ++v6 == v2 )\n goto LABEL_9;\n }\n ++a1;\n ++v20[2 * (int)v6 + 1];\n if ( a1 == v3 )\n break;\n v4 = *a1;\n }\nLABEL_10:\n v7 = (char *)malloc(0x3E8uLL);\n *(_WORD *)v7 = 123;\n v8 = v7;\n if ( v2 > 0 )\n {\n v9 = v2 - 1;\n if ( v2 - 1 <= 0 )\n {\n v10 = 0LL;\n do\n {\nLABEL_13:\n v11 = v20[2 * v10 + 1];\n v12 = v20[2 * v10++];\n __sprintf_chk(v21, 2LL, 50LL, \"%d: %d\", v12, v11);\n __strcat_chk(v8, v21, 1000LL);\n }\n while ( v2 > (int)v10 );\n goto LABEL_14;\n }\n v19 = v2;\n v14 = 0;\n v15 = v20;\n v16 = v9;\n do\n {\n ++v14;\n __sprintf_chk(v21, 2LL, 50LL, \"%d: %d\", *v15, v15[1]);\n v15 += 2;\n v17 = strlen(v8);\n v18 = __stpcpy_chk(&v8[v17], v21, 1000LL);\n __memcpy_chk(v18, \", \", 3LL, &v8[-v18 + 1000]);\n }\n while ( v14 < v16 );\n v10 = v14;\n v2 = v19;\n if ( (int)v10 < v19 )\n goto LABEL_13;\n }\nLABEL_14:\n __strcat_chk(v8, \"}\", 1000LL);\n return v8;\n}", + "ida_strip_asm": "sub_1410:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 378h\nmov rax, fs:28h\nmov [rsp+3A8h+var_40], rax\nxor eax, eax\ntest esi, esi\njle loc_1602\nmovsxd rsi, esi\nxor r15d, r15d\nlea rbx, [rsp+3A8h+var_398]\nlea r8, [rdi+rsi*4]\nnop\nloc_1450:\nmov edx, [rdi]\nmovsxd rcx, r15d\ntest r15d, r15d\njle short loc_1488\nloc_145A:\nxor eax, eax\njmp short loc_1469\nloc_1460:\nadd rax, 1\ncmp rax, rcx\njz short loc_1488\nloc_1469:\ncmp [rbx+rax*8], edx\njnz short loc_1460\ncdqe\nadd rdi, 4\nadd [rsp+rax*8+3A8h+var_394], 1\ncmp rdi, r8\njz short loc_14A1\nmov edx, [rdi]\njmp short loc_145A\nloc_1488:\nadd rdi, 4\nmov [rsp+rcx*8+3A8h+var_398], edx\nadd r15d, 1\nmov [rsp+rcx*8+3A8h+var_394], 1\ncmp rdi, r8\njnz short loc_1450\nloc_14A1:\nmov edi, 3E8h; size\ncall _malloc\nmov edx, 7Bh ; '{'\nmov [rax], dx\nmov r12, rax\ntest r15d, r15d\njle short loc_1519\nlea edx, [r15-1]\ntest edx, edx\njg loc_1559\nxor ebp, ebp\nlea rbx, [rsp+3A8h+var_398]\nlea r13, [rsp+3A8h+var_78]\nlea r14, aDD; \"%d: %d\"\nnop dword ptr [rax]\nloc_14E0:\nmov r9d, [rbx+rbp*8+4]\nmov r8d, [rbx+rbp*8]\nmov rcx, r14\nmov rdi, r13\nmov edx, 32h ; '2'\nmov esi, 2\nxor eax, eax\nadd rbp, 1\ncall ___sprintf_chk\nmov edx, 3E8h\nmov rsi, r13\nmov rdi, r12\ncall ___strcat_chk\ncmp r15d, ebp\njg short loc_14E0\nloc_1519:\nmov edx, 3E8h\nlea rsi, s2+11h; \"}\"\nmov rdi, r12\ncall ___strcat_chk\nmov rax, [rsp+3A8h+var_40]\nsub rax, fs:28h\njnz loc_161E\nadd rsp, 378h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1559:\nlea rbx, [rsp+3A8h+var_398]\nxor ebp, ebp\nmov [rsp+3A8h+var_3A4], r15d\nlea r13, [rsp+3A8h+var_78]\nmov [rsp+3A8h+var_3A0], rbx\nmov r15d, ebp\nlea r14, aDD; \"%d: %d\"\nmov rbp, rbx\nmov ebx, edx\nloc_1581:\nmov r9d, [rbp+4]\nmov r8d, [rbp+0]\nmov rcx, r14\nmov edx, 32h ; '2'\nmov esi, 2\nmov rdi, r13\nxor eax, eax\nadd r15d, 1\ncall ___sprintf_chk\nmov rdi, r12; s\nadd rbp, 8\ncall _strlen\nmov edx, 3E8h\nmov rsi, r13\nlea rdi, [r12+rax]\ncall ___stpcpy_chk\nmov rcx, r12\nmov edx, 3\nlea rsi, asc_200B; \", \"\nsub rcx, rax\nmov rdi, rax\nadd rcx, 3E8h\ncall ___memcpy_chk\ncmp r15d, ebx\njl short loc_1581\nmovsxd rbp, r15d\nmov r15d, [rsp+3A8h+var_3A4]\nmov rbx, [rsp+3A8h+var_3A0]\ncmp ebp, r15d\njl loc_14E0\njmp loc_1519\nloc_1602:\nmov edi, 3E8h; size\ncall _malloc\nmov r12, rax\nmov eax, 7Bh ; '{'\nmov [r12], ax\njmp loc_1519\nloc_161E:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_1410(int *a1, int a2)\n{\n int v2; // r15d\n int *v3; // r8\n int v4; // edx\n __int64 v5; // rcx\n __int64 v6; // rax\n char *v7; // rax\n char *v8; // r12\n int v9; // edx\n __int64 v10; // rbp\n int v11; // r9d\n int v12; // r8d\n int v14; // r15d\n _DWORD *v15; // rbp\n int v16; // ebx\n size_t v17; // rax\n __int64 v18; // rax\n int v19; // [rsp+4h] [rbp-3A4h]\n _DWORD v20[200]; // [rsp+10h] [rbp-398h] BYREF\n _BYTE v21[56]; // [rsp+330h] [rbp-78h] BYREF\n unsigned __int64 v22; // [rsp+368h] [rbp-40h]\n\n v22 = __readfsqword(0x28u);\n if ( a2 <= 0 )\n {\n v8 = (char *)malloc(0x3E8uLL);\n *(_WORD *)v8 = 123;\n goto LABEL_14;\n }\n v2 = 0;\n v3 = &a1[a2];\n while ( 1 )\n {\n v4 = *a1;\n v5 = v2;\n if ( v2 > 0 )\n break;\nLABEL_9:\n ++a1;\n v20[2 * v2++] = v4;\n v20[2 * v5 + 1] = 1;\n if ( a1 == v3 )\n goto LABEL_10;\n }\n while ( 1 )\n {\n v6 = 0LL;\n while ( v20[2 * v6] != v4 )\n {\n if ( ++v6 == v2 )\n goto LABEL_9;\n }\n ++a1;\n ++v20[2 * (int)v6 + 1];\n if ( a1 == v3 )\n break;\n v4 = *a1;\n }\nLABEL_10:\n v7 = (char *)malloc(0x3E8uLL);\n *(_WORD *)v7 = 123;\n v8 = v7;\n if ( v2 > 0 )\n {\n v9 = v2 - 1;\n if ( v2 - 1 <= 0 )\n {\n v10 = 0LL;\n do\n {\nLABEL_13:\n v11 = v20[2 * v10 + 1];\n v12 = v20[2 * v10++];\n __sprintf_chk(v21, 2LL, 50LL, \"%d: %d\", v12, v11);\n __strcat_chk(v8, v21, 1000LL);\n }\n while ( v2 > (int)v10 );\n goto LABEL_14;\n }\n v19 = v2;\n v14 = 0;\n v15 = v20;\n v16 = v9;\n do\n {\n ++v14;\n __sprintf_chk(v21, 2LL, 50LL, \"%d: %d\", *v15, v15[1]);\n v15 += 2;\n v17 = strlen(v8);\n v18 = __stpcpy_chk(&v8[v17], v21, 1000LL);\n __memcpy_chk(v18, \", \", 3LL, &v8[-v18 + 1000]);\n }\n while ( v14 < v16 );\n v10 = v14;\n v2 = v19;\n if ( (int)v10 < v19 )\n goto LABEL_13;\n }\nLABEL_14:\n __strcat_chk(v8, \"}\", 1000LL);\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1410(int *a1, int a2) {\n int v2;\n int *v3;\n int v4;\n long long v5;\n long long v6;\n char *v7;\n char *v8;\n int v9;\n long long v10;\n int v11;\n int v12;\n int v14;\n uint32_t *v15;\n int v16;\n unsigned int v17;\n long long v18;\n int v19;\n uint32_t v20[200];\n uint8_t v21[56];\n unsigned long long v22;\n v22 = __readfsqword(40u);\n if (a2 <= 0) {\n v8 = (char *)malloc(1000uLL);\n *(unsigned short *)v8 = 123;\n goto LABEL_14;\n }\n v2 = 0;\n v3 = &a1[a2];\n while (1) {\n v4 = *a1;\n v5 = v2;\n if (v2 > 0) break;\n LABEL_9:\n ++a1;\n v20[2 * v2++] = v4;\n v20[2 * v5 + 1] = 1;\n if (a1 == v3) goto LABEL_10;\n }\n while (1) {\n v6 = 0LL;\n while (v20[2 * v6] != v4) {\n if (++v6 == v2) goto LABEL_9;\n }\n ++a1;\n ++v20[2 * (int)v6 + 1];\n if (a1 == v3) break;\n v4 = *a1;\n }\nLABEL_10:\n v7 = (char *)malloc(1000uLL);\n *(unsigned short *)v7 = 123;\n v8 = v7;\n if (v2 > 0) {\n v9 = v2 - 1;\n if (v2 - 1 <= 0) {\n v10 = 0LL;\n do {\n LABEL_13:\n v11 = v20[2 * v10 + 1];\n v12 = v20[2 * v10++];\n __sprintf_chk(v21, 2LL, 50LL, \"%d: %d\", v12, v11);\n __strcat_chk(v8, v21, 1000LL);\n } while (v2 > (int)v10);\n goto LABEL_14;\n }\n v19 = v2;\n v14 = 0;\n v15 = v20;\n v16 = v9;\n do {\n ++v14;\n __sprintf_chk(v21, 2LL, 50LL, \"%d: %d\", *v15, v15[1]);\n v15 += 2;\n v17 = strlen(v8);\n v18 = __stpcpy_chk(&v8[v17], v21, 1000LL);\n __memcpy_chk(v18, \", \", 3LL, &v8[-v18 + 1000]);\n } while (v14 < v16);\n v10 = v14;\n v2 = v19;\n if ((int)v10 < v19) goto LABEL_13;\n }\nLABEL_14:\n __strcat_chk(v8, \"}\", 1000LL);\n return v8;\n}", + "ida_pseudo_norm": "char *func0(int *a1, int a2) {\n int v2;\n int *v3;\n int v4;\n long long v5;\n long long v6;\n char *v7;\n char *v8;\n int v9;\n long long v10;\n int v11;\n int v12;\n int v14;\n uint32_t *v15;\n int v16;\n unsigned int v17;\n long long v18;\n int v19;\n uint32_t v20[200];\n uint8_t v21[56];\n unsigned long long v22;\n v22 = __readfsqword(40u);\n if (a2 <= 0) {\n v8 = (char *)malloc(1000uLL);\n *(unsigned short *)v8 = 123;\n goto LABEL_14;\n }\n v2 = 0;\n v3 = &a1[a2];\n while (1) {\n v4 = *a1;\n v5 = v2;\n if (v2 > 0) break;\n LABEL_9:\n ++a1;\n v20[2 * v2++] = v4;\n v20[2 * v5 + 1] = 1;\n if (a1 == v3) goto LABEL_10;\n }\n while (1) {\n v6 = 0LL;\n while (v20[2 * v6] != v4) {\n if (++v6 == v2) goto LABEL_9;\n }\n ++a1;\n ++v20[2 * (int)v6 + 1];\n if (a1 == v3) break;\n v4 = *a1;\n }\nLABEL_10:\n v7 = (char *)malloc(1000uLL);\n *(unsigned short *)v7 = 123;\n v8 = v7;\n if (v2 > 0) {\n v9 = v2 - 1;\n if (v2 - 1 <= 0) {\n v10 = 0LL;\n do {\n LABEL_13:\n v11 = v20[2 * v10 + 1];\n v12 = v20[2 * v10++];\n __sprintf_chk(v21, 2LL, 50LL, \"%d: %d\", v12, v11);\n __strcat_chk(v8, v21, 1000LL);\n } while (v2 > (int)v10);\n goto LABEL_14;\n }\n v19 = v2;\n v14 = 0;\n v15 = v20;\n v16 = v9;\n do {\n ++v14;\n __sprintf_chk(v21, 2LL, 50LL, \"%d: %d\", *v15, v15[1]);\n v15 += 2;\n v17 = strlen(v8);\n v18 = __stpcpy_chk(&v8[v17], v21, 1000LL);\n __memcpy_chk(v18, \", \", 3LL, &v8[-v18 + 1000]);\n } while (v14 < v16);\n v10 = v14;\n v2 = v19;\n if ((int)v10 < v19) goto LABEL_13;\n }\nLABEL_14:\n __strcat_chk(v8, \"}\", 1000LL);\n return v8;\n}" + }, + { + "index": 687, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int a, int b) {\n int low = a < b ? a : b;\n int high = a > b ? a : b;\n if (low == 0) {\n return high;\n } else if (low == 1) {\n return 1;\n } else {\n return func0(low, high % low);\n }\n}", + "test": "int main() {\n\n assert(func0(12, 14) == 2);\n\n assert(func0(13, 17) == 1);\n\n assert(func0(9, 3) == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov -0x14(%rbp),%eax\ncmp %eax,-0x18(%rbp)\ncmovle -0x18(%rbp),%eax\nmov %eax,-0x8(%rbp)\nmov -0x14(%rbp),%eax\ncmp %eax,-0x18(%rbp)\ncmovge -0x18(%rbp),%eax\nmov %eax,-0x4(%rbp)\ncmpl $0x0,-0x8(%rbp)\njne 1180 \nmov -0x4(%rbp),%eax\njmp 11a0 \ncmpl $0x1,-0x8(%rbp)\njne 118d \nmov $0x1,%eax\njmp 11a0 \nmov -0x4(%rbp),%eax\ncltd\nidivl -0x8(%rbp)\nmov -0x8(%rbp),%eax\nmov %edx,%esi\nmov %eax,%edi\ncallq 1149 \nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov edx, [rbp+var_18]\nmov eax, [rbp+var_14]\ncmp edx, eax\ncmovle eax, edx\nmov [rbp+var_8], eax\nmov edx, [rbp+var_18]\nmov eax, [rbp+var_14]\ncmp edx, eax\ncmovge eax, edx\nmov [rbp+var_4], eax\ncmp [rbp+var_8], 0\njnz short loc_1182\nmov eax, [rbp+var_4]\njmp short locret_11A2\nloc_1182:\ncmp [rbp+var_8], 1\njnz short loc_118F\nmov eax, 1\njmp short locret_11A2\nloc_118F:\nmov eax, [rbp+var_4]\ncdq\nidiv [rbp+var_8]\nmov eax, [rbp+var_8]\nmov esi, edx\nmov edi, eax\ncall func0\nlocret_11A2:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n unsigned int v2; // eax\n __int64 result; // rax\n unsigned int v4; // [rsp+18h] [rbp-8h]\n\n v2 = a1;\n if ( a2 <= a1 )\n v2 = a2;\n v4 = v2;\n LODWORD(result) = a1;\n if ( a2 >= a1 )\n LODWORD(result) = a2;\n if ( !v4 )\n return (unsigned int)result;\n if ( v4 == 1 )\n return 1LL;\n return func0(v4, (unsigned int)((int)result % (int)v4));\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov edx, [rbp+var_18]\nmov eax, [rbp+var_14]\ncmp edx, eax\ncmovle eax, edx\nmov [rbp+var_8], eax\nmov edx, [rbp+var_18]\nmov eax, [rbp+var_14]\ncmp edx, eax\ncmovge eax, edx\nmov [rbp+var_4], eax\ncmp [rbp+var_8], 0\njnz short loc_1182\nmov eax, [rbp+var_4]\njmp short locret_11A2\nloc_1182:\ncmp [rbp+var_8], 1\njnz short loc_118F\nmov eax, 1\njmp short locret_11A2\nloc_118F:\nmov eax, [rbp+var_4]\ncdq\nidiv [rbp+var_8]\nmov eax, [rbp+var_8]\nmov esi, edx\nmov edi, eax\ncall sub_1149\nlocret_11A2:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2)\n{\n unsigned int v2; // eax\n __int64 result; // rax\n unsigned int v4; // [rsp+18h] [rbp-8h]\n\n v2 = a1;\n if ( a2 <= a1 )\n v2 = a2;\n v4 = v2;\n LODWORD(result) = a1;\n if ( a2 >= a1 )\n LODWORD(result) = a2;\n if ( !v4 )\n return (unsigned int)result;\n if ( v4 == 1 )\n return 1LL;\n return sub_1149(v4, (unsigned int)((int)result % (int)v4));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2) {\n unsigned int v2;\n long long result;\n unsigned int v4;\n v2 = a1;\n if (a2 <= a1) v2 = a2;\n v4 = v2;\n LODWORD(result) = a1;\n if (a2 >= a1) LODWORD(result) = a2;\n if (!v4) return (unsigned int)result;\n if (v4 == 1) return 1LL;\n return sub_1149(v4, (unsigned int)((int)result % (int)v4));\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n unsigned int v2;\n long long result;\n unsigned int v4;\n v2 = a1;\n if (a2 <= a1) v2 = a2;\n v4 = v2;\n LODWORD(result) = a1;\n if (a2 >= a1) LODWORD(result) = a2;\n if (!v4) return (unsigned int)result;\n if (v4 == 1) return 1LL;\n return func0(v4, (unsigned int)((int)result % (int)v4));\n}" + }, + { + "index": 687, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int a, int b) {\n int low = a < b ? a : b;\n int high = a > b ? a : b;\n if (low == 0) {\n return high;\n } else if (low == 1) {\n return 1;\n } else {\n return func0(low, high % low);\n }\n}", + "test": "int main() {\n\n assert(func0(12, 14) == 2);\n\n assert(func0(13, 17) == 1);\n\n assert(func0(9, 3) == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %edi,%eax\ncmp %edi,%esi\ncmovle %esi,%edi\ncmovge %esi,%eax\ntest %edi,%edi\nje 1176 \ncmp $0x1,%edi\njne 1163 \nmov %edi,%eax\nretq\nsub $0x8,%rsp\ncltd\nidiv %edi\nmov %edx,%esi\ncallq 1149 \nadd $0x8,%rsp\nretq\nretq\n", + "ida_asm": "func0:\nendbr64\ncmp esi, edi\nmov ecx, edi\ncmovle ecx, esi\nmov eax, edi\ncmovge eax, esi\ntest ecx, ecx\njz short locret_117A\ncmp ecx, 1\njnz short loc_1165\nmov eax, ecx\nretn\nloc_1165:\nsub rsp, 8\ncdq\nidiv ecx\nmov esi, edx\nmov edi, ecx\ncall func0\nadd rsp, 8\nretn\nlocret_117A:\nretn", + "ida_pseudo": "__int64 __fastcall func0(signed int a1, signed int a2)\n{\n unsigned int v2; // ecx\n __int64 result; // rax\n\n v2 = a1;\n if ( a2 <= a1 )\n v2 = a2;\n result = (unsigned int)a1;\n if ( a2 >= a1 )\n result = (unsigned int)a2;\n if ( v2 )\n {\n if ( v2 == 1 )\n return 1LL;\n else\n return func0(v2, (unsigned int)((int)result % (int)v2));\n }\n return result;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ncmp esi, edi\nmov ecx, edi\ncmovle ecx, esi\nmov eax, edi\ncmovge eax, esi\ntest ecx, ecx\njz short locret_117A\ncmp ecx, 1\njnz short loc_1165\nmov eax, ecx\nretn\nloc_1165:\nsub rsp, 8\ncdq\nidiv ecx\nmov esi, edx\nmov edi, ecx\ncall sub_1149\nadd rsp, 8\nretn\nlocret_117A:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(signed int a1, signed int a2)\n{\n unsigned int v2; // ecx\n __int64 result; // rax\n\n v2 = a1;\n if ( a2 <= a1 )\n v2 = a2;\n result = (unsigned int)a1;\n if ( a2 >= a1 )\n result = (unsigned int)a2;\n if ( v2 )\n {\n if ( v2 == 1 )\n return 1LL;\n else\n return sub_1149(v2, (unsigned int)((int)result % (int)v2));\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(signed int a1, signed int a2) {\n unsigned int v2;\n long long result;\n v2 = a1;\n if (a2 <= a1) v2 = a2;\n result = (unsigned int)a1;\n if (a2 >= a1) result = (unsigned int)a2;\n if (v2) {\n if (v2 == 1)\n return 1LL;\n else\n return sub_1149(v2, (unsigned int)((int)result % (int)v2));\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(signed int a1, signed int a2) {\n unsigned int v2;\n long long result;\n v2 = a1;\n if (a2 <= a1) v2 = a2;\n result = (unsigned int)a1;\n if (a2 >= a1) result = (unsigned int)a2;\n if (v2) {\n if (v2 == 1)\n return 1LL;\n else\n return func0(v2, (unsigned int)((int)result % (int)v2));\n }\n return result;\n}" + }, + { + "index": 688, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "double func0(double a, double b) { return sqrt(a * a + b * b); }", + "test": "int main() {\n\n assert(func0(3, 4) == 5.0);\n\n assert(fabs(func0(9, 10) - 13.45362404707371) < 0.000001);\n\n assert(fabs(func0(7, 9) - 11.40175425099138) < 0.000001);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmovsd %xmm0,-0x8(%rbp)\nmovsd %xmm1,-0x10(%rbp)\nmovsd -0x8(%rbp),%xmm0\nmovapd %xmm0,%xmm1\nmulsd %xmm0,%xmm1\nmovsd -0x10(%rbp),%xmm0\nmulsd %xmm0,%xmm0\naddsd %xmm1,%xmm0\ncallq 1070 \nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmovsd [rbp+var_8], xmm0\nmovsd [rbp+var_10], xmm1\nmovsd xmm0, [rbp+var_8]\nmovapd xmm1, xmm0\nmulsd xmm1, xmm0\nmovsd xmm0, [rbp+var_10]\nmulsd xmm0, xmm0\naddsd xmm1, xmm0\nmovq rax, xmm1\nmovq xmm0, rax; x\ncall _sqrt\nleave\nretn", + "ida_pseudo": "double __fastcall func0(double a1, double a2)\n{\n return sqrt(a1 * a1 + a2 * a2);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmovsd [rbp+var_8], xmm0\nmovsd [rbp+var_10], xmm1\nmovsd xmm0, [rbp+var_8]\nmovapd xmm1, xmm0\nmulsd xmm1, xmm0\nmovsd xmm0, [rbp+var_10]\nmulsd xmm0, xmm0\naddsd xmm1, xmm0\nmovq rax, xmm1\nmovq xmm0, rax; x\ncall _sqrt\nleave\nretn", + "ida_strip_pseudo": "double __fastcall sub_1169(double a1, double a2)\n{\n return sqrt(a1 * a1 + a2 * a2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1169(double a1, double a2) { return sqrt(a1 * a1 + a2 * a2); }", + "ida_pseudo_norm": "double func0(double a1, double a2) { return sqrt(a1 * a1 + a2 * a2); }" + }, + { + "index": 689, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int jumps[n];\n if (n == 0 || arr[0] == 0) {\n return INT_MAX;\n }\n jumps[0] = 0;\n for (int i = 1; i < n; i++) {\n jumps[i] = INT_MAX;\n for (int j = 0; j < i; j++) {\n if (i <= j + arr[j] && jumps[j] != INT_MAX) {\n jumps[i] = (jumps[i] < jumps[j] + 1) ? jumps[i] : jumps[j] + 1;\n break;\n }\n }\n }\n return jumps[n - 1];\n}", + "test": "int main() {\n\n int arr1[] = {1, 3, 6, 1, 0, 9};\n\n int arr2[] = {1, 3, 5, 8, 9, 2, 6, 7, 6, 8, 9};\n\n int arr3[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1};\n\n\n\n assert(func0(arr1, 6) == 3);\n\n assert(func0(arr2, 11) == 3);\n\n assert(func0(arr3, 11) == 10);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x38,%rsp\nmov %rdi,-0x38(%rbp)\nmov %esi,-0x3c(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmov %rsp,%rax\nmov %rax,%rsi\nmov -0x3c(%rbp),%eax\nmovslq %eax,%rdx\nsub $0x1,%rdx\nmov %rdx,-0x28(%rbp)\nmovslq %eax,%rdx\nmov %rdx,%r8\nmov $0x0,%r9d\nmovslq %eax,%rdx\nmov %rdx,%rcx\nmov $0x0,%ebx\ncltq\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%edi\nmov $0x0,%edx\ndiv %rdi\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rbx\nsub %rdx,%rbx\nmov %rbx,%rdx\ncmp %rdx,%rsp\nje 1208 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11f1 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 1232 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x20(%rbp)\ncmpl $0x0,-0x3c(%rbp)\nje 1255 \nmov -0x38(%rbp),%rax\nmov (%rax),%eax\ntest %eax,%eax\njne 125f \nmov $0x7fffffff,%eax\njmpq 1342 \nmov -0x20(%rbp),%rax\nmovl $0x0,(%rax)\nmovl $0x1,-0x2c(%rbp)\njmpq 1326 \nmov -0x20(%rbp),%rax\nmov -0x2c(%rbp),%edx\nmovslq %edx,%rdx\nmovl $0x7fffffff,(%rax,%rdx,4)\nmovl $0x0,-0x30(%rbp)\njmpq 1316 \nmov -0x30(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x30(%rbp),%eax\nadd %edx,%eax\ncmp %eax,-0x2c(%rbp)\njg 1312 \nmov -0x20(%rbp),%rax\nmov -0x30(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\ncmp $0x7fffffff,%eax\nje 1312 \nmov -0x20(%rbp),%rax\nmov -0x30(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%ecx\nmov -0x20(%rbp),%rax\nmov -0x2c(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\ncmp %eax,%ecx\njl 12f3 \nmov -0x20(%rbp),%rax\nmov -0x2c(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\njmp 1303 \nmov -0x20(%rbp),%rax\nmov -0x30(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nadd $0x1,%eax\nmov -0x20(%rbp),%rdx\nmov -0x2c(%rbp),%ecx\nmovslq %ecx,%rcx\nmov %eax,(%rdx,%rcx,4)\njmp 1322 \naddl $0x1,-0x30(%rbp)\nmov -0x30(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 1292 \naddl $0x1,-0x2c(%rbp)\nmov -0x2c(%rbp),%eax\ncmp -0x3c(%rbp),%eax\njl 1275 \nmov -0x3c(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x20(%rbp),%rax\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nmov %rsi,%rsp\nmov -0x18(%rbp),%rdi\nxor %fs:0x28,%rdi\nje 1359 \ncallq 1060 <__stack_chk_fail@plt>\nmov -0x8(%rbp),%rbx\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov eax, [rbp+var_2C]\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11D6:\ncmp rsp, rdx\njz short loc_11ED\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\njmp short loc_11D6\nloc_11ED:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1217\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1217:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\ncmp [rbp+var_2C], 0\njz short loc_123A\nmov rax, [rbp+var_28]\nmov eax, [rax]\ntest eax, eax\njnz short loc_1244\nloc_123A:\nmov eax, 7FFFFFFFh\njmp loc_1327\nloc_1244:\nmov rax, [rbp+var_10]\nmov dword ptr [rax], 0\nmov [rbp+var_20], 1\njmp loc_130B\nloc_125A:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nmov dword ptr [rax+rdx*4], 7FFFFFFFh\nmov [rbp+var_1C], 0\njmp loc_12FB\nloc_1277:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_1C]\nadd eax, edx\ncmp [rbp+var_20], eax\njg short loc_12F7\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ncmp eax, 7FFFFFFFh\njz short loc_12F7\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ncmp ecx, eax\njl short loc_12D8\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\njmp short loc_12E8\nloc_12D8:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nadd eax, 1\nloc_12E8:\nmov rdx, [rbp+var_10]\nmov ecx, [rbp+var_20]\nmovsxd rcx, ecx\nmov [rdx+rcx*4], eax\njmp short loc_1307\nloc_12F7:\nadd [rbp+var_1C], 1\nloc_12FB:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_20]\njl loc_1277\nloc_1307:\nadd [rbp+var_20], 1\nloc_130B:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_2C]\njl loc_125A\nmov eax, [rbp+var_2C]\nlea edx, [rax-1]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nloc_1327:\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_133E\ncall ___stack_chk_fail\nlocret_133E:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n unsigned __int64 v2; // rax\n void *v3; // rsp\n int v5; // eax\n _BYTE v6[4]; // [rsp+8h] [rbp-30h] BYREF\n int v7; // [rsp+Ch] [rbp-2Ch]\n _DWORD *v8; // [rsp+10h] [rbp-28h]\n int i; // [rsp+18h] [rbp-20h]\n int j; // [rsp+1Ch] [rbp-1Ch]\n __int64 v11; // [rsp+20h] [rbp-18h]\n _DWORD *v12; // [rsp+28h] [rbp-10h]\n unsigned __int64 v13; // [rsp+30h] [rbp-8h]\n\n v8 = a1;\n v7 = a2;\n v13 = __readfsqword(0x28u);\n v11 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 0x10uLL);\n while ( v6 != &v6[-(v2 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = alloca(v2 & 0xFFF);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)&v6[(v2 & 0xFFF) - 8] = *(_QWORD *)&v6[(v2 & 0xFFF) - 8];\n v12 = v6;\n if ( !v7 || !*v8 )\n return 0x7FFFFFFFLL;\n *v12 = 0;\n for ( i = 1; i < v7; ++i )\n {\n v12[i] = 0x7FFFFFFF;\n for ( j = 0; j < i; ++j )\n {\n if ( i <= v8[j] + j && v12[j] != 0x7FFFFFFF )\n {\n if ( v12[j] < v12[i] )\n v5 = v12[j] + 1;\n else\n v5 = v12[i];\n v12[i] = v5;\n break;\n }\n }\n }\n return (unsigned int)v12[v7 - 1];\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov eax, [rbp+var_2C]\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11D6:\ncmp rsp, rdx\njz short loc_11ED\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\njmp short loc_11D6\nloc_11ED:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1217\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1217:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\ncmp [rbp+var_2C], 0\njz short loc_123A\nmov rax, [rbp+var_28]\nmov eax, [rax]\ntest eax, eax\njnz short loc_1244\nloc_123A:\nmov eax, 7FFFFFFFh\njmp loc_1327\nloc_1244:\nmov rax, [rbp+var_10]\nmov dword ptr [rax], 0\nmov [rbp+var_20], 1\njmp loc_130B\nloc_125A:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nmov dword ptr [rax+rdx*4], 7FFFFFFFh\nmov [rbp+var_1C], 0\njmp loc_12FB\nloc_1277:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_1C]\nadd eax, edx\ncmp [rbp+var_20], eax\njg short loc_12F7\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ncmp eax, 7FFFFFFFh\njz short loc_12F7\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ncmp ecx, eax\njl short loc_12D8\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\njmp short loc_12E8\nloc_12D8:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nadd eax, 1\nloc_12E8:\nmov rdx, [rbp+var_10]\nmov ecx, [rbp+var_20]\nmovsxd rcx, ecx\nmov [rdx+rcx*4], eax\njmp short loc_1307\nloc_12F7:\nadd [rbp+var_1C], 1\nloc_12FB:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_20]\njl loc_1277\nloc_1307:\nadd [rbp+var_20], 1\nloc_130B:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_2C]\njl loc_125A\nmov eax, [rbp+var_2C]\nlea edx, [rax-1]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nloc_1327:\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_133E\ncall ___stack_chk_fail\nlocret_133E:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2)\n{\n unsigned __int64 v2; // rax\n void *v3; // rsp\n int v5; // eax\n _BYTE v6[4]; // [rsp+8h] [rbp-30h] BYREF\n int v7; // [rsp+Ch] [rbp-2Ch]\n _DWORD *v8; // [rsp+10h] [rbp-28h]\n int i; // [rsp+18h] [rbp-20h]\n int j; // [rsp+1Ch] [rbp-1Ch]\n __int64 v11; // [rsp+20h] [rbp-18h]\n _DWORD *v12; // [rsp+28h] [rbp-10h]\n unsigned __int64 v13; // [rsp+30h] [rbp-8h]\n\n v8 = a1;\n v7 = a2;\n v13 = __readfsqword(0x28u);\n v11 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 0x10uLL);\n while ( v6 != &v6[-(v2 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = alloca(v2 & 0xFFF);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)&v6[(v2 & 0xFFF) - 8] = *(_QWORD *)&v6[(v2 & 0xFFF) - 8];\n v12 = v6;\n if ( !v7 || !*v8 )\n return 0x7FFFFFFFLL;\n *v12 = 0;\n for ( i = 1; i < v7; ++i )\n {\n v12[i] = 0x7FFFFFFF;\n for ( j = 0; j < i; ++j )\n {\n if ( i <= v8[j] + j && v12[j] != 0x7FFFFFFF )\n {\n if ( v12[j] < v12[i] )\n v5 = v12[j] + 1;\n else\n v5 = v12[i];\n v12[i] = v5;\n break;\n }\n }\n }\n return (unsigned int)v12[v7 - 1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2) {\n unsigned long long v2;\n void *v3;\n int v5;\n uint8_t v6[4];\n int v7;\n uint32_t *v8;\n int i;\n int j;\n long long v11;\n uint32_t *v12;\n unsigned long long v13;\n v8 = a1;\n v7 = a2;\n v13 = __readfsqword(40u);\n v11 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 16uLL);\n while (v6 != &v6[-(v2 & 18446744073709547520LL)])\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)&v6[(v2 & 4095) - 8] = *(uint64_t *)&v6[(v2 & 4095) - 8];\n v12 = v6;\n if (!v7 || !*v8) return 2147483647LL;\n *v12 = 0;\n for (i = 1; i < v7; ++i) {\n v12[i] = 2147483647;\n for (j = 0; j < i; ++j) {\n if (i <= v8[j] + j && v12[j] != 2147483647) {\n if (v12[j] < v12[i])\n v5 = v12[j] + 1;\n else\n v5 = v12[i];\n v12[i] = v5;\n break;\n }\n }\n }\n return (unsigned int)v12[v7 - 1];\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n unsigned long long v2;\n void *v3;\n int v5;\n uint8_t v6[4];\n int v7;\n uint32_t *v8;\n int i;\n int j;\n long long v11;\n uint32_t *v12;\n unsigned long long v13;\n v8 = a1;\n v7 = a2;\n v13 = __readfsqword(40u);\n v11 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 16uLL);\n while (v6 != &v6[-(v2 & 18446744073709547520LL)])\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)&v6[(v2 & 4095) - 8] = *(uint64_t *)&v6[(v2 & 4095) - 8];\n v12 = v6;\n if (!v7 || !*v8) return 2147483647LL;\n *v12 = 0;\n for (i = 1; i < v7; ++i) {\n v12[i] = 2147483647;\n for (j = 0; j < i; ++j) {\n if (i <= v8[j] + j && v12[j] != 2147483647) {\n if (v12[j] < v12[i])\n v5 = v12[j] + 1;\n else\n v5 = v12[i];\n v12[i] = v5;\n break;\n }\n }\n }\n return (unsigned int)v12[v7 - 1];\n}" + }, + { + "index": 689, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int jumps[n];\n if (n == 0 || arr[0] == 0) {\n return INT_MAX;\n }\n jumps[0] = 0;\n for (int i = 1; i < n; i++) {\n jumps[i] = INT_MAX;\n for (int j = 0; j < i; j++) {\n if (i <= j + arr[j] && jumps[j] != INT_MAX) {\n jumps[i] = (jumps[i] < jumps[j] + 1) ? jumps[i] : jumps[j] + 1;\n break;\n }\n }\n }\n return jumps[n - 1];\n}", + "test": "int main() {\n\n int arr1[] = {1, 3, 6, 1, 0, 9};\n\n int arr2[] = {1, 3, 5, 8, 9, 2, 6, 7, 6, 8, 9};\n\n int arr3[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1};\n\n\n\n assert(func0(arr1, 6) == 3);\n\n assert(func0(arr2, 11) == 3);\n\n assert(func0(arr3, 11) == 10);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovslq %esi,%rax\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffffff0,%rdx\nand $0xfffffffffffff000,%rax\nmov %rsp,%rcx\nsub %rax,%rcx\nmov %rcx,%rax\ncmp %rax,%rsp\nje 11bc \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11a5 \nmov %rdx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 11d2 \norq $0x0,-0x8(%rsp,%rax,1)\nlea 0x3(%rsp),%r11\nmov %r11,%rdx\nshr $0x2,%rdx\nand $0xfffffffffffffffc,%r11\nmov %r11,%r9\nmov $0x7fffffff,%eax\ntest %esi,%esi\nje 1260 \ncmpl $0x0,(%rdi)\nje 1260 \nmovl $0x0,0x0(,%rdx,4)\ncmp $0x1,%esi\njle 1257 \nlea -0x2(%rsi),%r10d\nadd $0x2,%r10\nmov $0x1,%ecx\njmp 1241 \nadd $0x1,%rax\ncmp %rcx,%rax\nje 1238 \nmov %eax,%edx\nadd (%rdi,%rax,4),%edx\ncmp %r8d,%edx\njl 1212 \nmov (%r9,%rax,4),%edx\ncmp $0x7fffffff,%edx\nje 1212 \nadd $0x1,%edx\nmov %edx,(%r9,%rcx,4)\nadd $0x1,%rcx\ncmp %r10,%rcx\nje 1257 \nmovl $0x7fffffff,(%r9,%rcx,4)\nmov %ecx,%r8d\ntest %ecx,%ecx\njle 1238 \nmov $0x0,%eax\njmp 121b \nlea -0x1(%rsi),%eax\ncltq\nmov (%r11,%rax,4),%eax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\njne 1271 \nleaveq\nretq\ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov r9d, esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmovsxd rax, esi\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11A5:\ncmp rsp, rdx\njz short loc_11BC\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11A5\nloc_11BC:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11D2\nor [rsp+rax+10h+var_18], 0\nloc_11D2:\nlea r8, [rsp+10h+var_D]\nmov rdx, r8\nshr rdx, 2\nand r8, 0FFFFFFFFFFFFFFFCh\nmov eax, 7FFFFFFFh\ntest r9d, r9d\njz short loc_1259\ncmp dword ptr [rdi], 0\njz short loc_1259\nmov ds:dword_0[rdx*4], 0\ncmp r9d, 1\njle short loc_124F\nmov r10d, r9d\nmov ecx, 1\njmp short loc_123A\nloc_120C:\nadd rax, 1\ncmp rax, rcx\njz short loc_1231\nloc_1215:\nmov edx, eax\nadd edx, [rdi+rax*4]\ncmp edx, esi\njl short loc_120C\nmov edx, [r8+rax*4]\ncmp edx, 7FFFFFFFh\njz short loc_120C\nadd edx, 1\nmov [r8+rcx*4], edx\nloc_1231:\nadd rcx, 1\ncmp rcx, r10\njz short loc_124F\nloc_123A:\nmov dword ptr [r8+rcx*4], 7FFFFFFFh\nmov esi, ecx\ntest ecx, ecx\njle short loc_126A\nmov eax, 0\njmp short loc_1215\nloc_124F:\nlea eax, [r9-1]\ncdqe\nmov eax, [r8+rax*4]\nloc_1259:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_1270\nleave\nretn\nloc_126A:\nadd rcx, 1\njmp short loc_123A\nloc_1270:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n signed __int64 v2; // rax\n void *v3; // rsp\n __int64 result; // rax\n __int64 i; // rcx\n __int64 v6; // rax\n int v7; // edx\n _DWORD v9[2]; // [rsp+8h] [rbp-10h] BYREF\n unsigned __int64 v10; // [rsp+10h] [rbp-8h]\n\n v10 = __readfsqword(0x28u);\n while ( v9 != (_DWORD *)((char *)v9 - ((4LL * a2 + 15) & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v2 = (4 * (_WORD)a2 + 15) & 0xFF0;\n v3 = alloca(v2);\n if ( ((4 * (_WORD)a2 + 15) & 0xFF0) != 0 )\n *(_QWORD *)((char *)&v9[-2] + v2) = *(_QWORD *)((char *)&v9[-2] + v2);\n result = 0x7FFFFFFFLL;\n if ( a2 && *a1 )\n {\n v9[0] = 0;\n if ( a2 > 1 )\n {\n for ( i = 1LL; i != a2; ++i )\n {\n while ( 1 )\n {\n v9[i] = 0x7FFFFFFF;\n if ( (int)i > 0 )\n break;\n ++i;\n }\n v6 = 0LL;\n while ( 1 )\n {\n if ( a1[v6] + (int)v6 >= (int)i )\n {\n v7 = v9[v6];\n if ( v7 != 0x7FFFFFFF )\n break;\n }\n if ( ++v6 == i )\n goto LABEL_13;\n }\n v9[i] = v7 + 1;\nLABEL_13:\n ;\n }\n }\n return (unsigned int)v9[a2 - 1];\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov r9d, esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmovsxd rax, esi\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11A5:\ncmp rsp, rdx\njz short loc_11BC\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11A5\nloc_11BC:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11D2\nor [rsp+rax+10h+var_18], 0\nloc_11D2:\nlea r8, [rsp+10h+var_D]\nmov rdx, r8\nshr rdx, 2\nand r8, 0FFFFFFFFFFFFFFFCh\nmov eax, 7FFFFFFFh\ntest r9d, r9d\njz short loc_1259\ncmp dword ptr [rdi], 0\njz short loc_1259\nmov ds:dword_0[rdx*4], 0\ncmp r9d, 1\njle short loc_124F\nmov r10d, r9d\nmov ecx, 1\njmp short loc_123A\nloc_120C:\nadd rax, 1\ncmp rax, rcx\njz short loc_1231\nloc_1215:\nmov edx, eax\nadd edx, [rdi+rax*4]\ncmp edx, esi\njl short loc_120C\nmov edx, [r8+rax*4]\ncmp edx, 7FFFFFFFh\njz short loc_120C\nadd edx, 1\nmov [r8+rcx*4], edx\nloc_1231:\nadd rcx, 1\ncmp rcx, r10\njz short loc_124F\nloc_123A:\nmov dword ptr [r8+rcx*4], 7FFFFFFFh\nmov esi, ecx\ntest ecx, ecx\njle short loc_126A\nmov eax, 0\njmp short loc_1215\nloc_124F:\nlea eax, [r9-1]\ncdqe\nmov eax, [r8+rax*4]\nloc_1259:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_1270\nleave\nretn\nloc_126A:\nadd rcx, 1\njmp short loc_123A\nloc_1270:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2)\n{\n signed __int64 v2; // rax\n void *v3; // rsp\n __int64 result; // rax\n __int64 i; // rcx\n __int64 v6; // rax\n int v7; // edx\n _DWORD v9[2]; // [rsp+8h] [rbp-10h] BYREF\n unsigned __int64 v10; // [rsp+10h] [rbp-8h]\n\n v10 = __readfsqword(0x28u);\n while ( v9 != (_DWORD *)((char *)v9 - ((4LL * a2 + 15) & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v2 = (4 * (_WORD)a2 + 15) & 0xFF0;\n v3 = alloca(v2);\n if ( ((4 * (_WORD)a2 + 15) & 0xFF0) != 0 )\n *(_QWORD *)((char *)&v9[-2] + v2) = *(_QWORD *)((char *)&v9[-2] + v2);\n result = 0x7FFFFFFFLL;\n if ( a2 && *a1 )\n {\n v9[0] = 0;\n if ( a2 > 1 )\n {\n for ( i = 1LL; i != a2; ++i )\n {\n while ( 1 )\n {\n v9[i] = 0x7FFFFFFF;\n if ( (int)i > 0 )\n break;\n ++i;\n }\n v6 = 0LL;\n while ( 1 )\n {\n if ( a1[v6] + (int)v6 >= (int)i )\n {\n v7 = v9[v6];\n if ( v7 != 0x7FFFFFFF )\n break;\n }\n if ( ++v6 == i )\n goto LABEL_13;\n }\n v9[i] = v7 + 1;\nLABEL_13:\n ;\n }\n }\n return (unsigned int)v9[a2 - 1];\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2) {\n signed long long v2;\n void *v3;\n long long result;\n long long i;\n long long v6;\n int v7;\n uint32_t v9[2];\n unsigned long long v10;\n v10 = __readfsqword(40u);\n while (v9 !=\n (uint32_t *)((char *)v9 - ((4LL * a2 + 15) & 18446744073709547520LL)))\n ;\n v2 = (4 * (unsigned short)a2 + 15) & 4080;\n v3 = alloca(v2);\n if (((4 * (unsigned short)a2 + 15) & 4080) != 0)\n *(uint64_t *)((char *)&v9[-2] + v2) = *(uint64_t *)((char *)&v9[-2] + v2);\n result = 2147483647LL;\n if (a2 && *a1) {\n v9[0] = 0;\n if (a2 > 1) {\n for (i = 1LL; i != a2; ++i) {\n while (1) {\n v9[i] = 2147483647;\n if ((int)i > 0) break;\n ++i;\n }\n v6 = 0LL;\n while (1) {\n if (a1[v6] + (int)v6 >= (int)i) {\n v7 = v9[v6];\n if (v7 != 2147483647) break;\n }\n if (++v6 == i) goto LABEL_13;\n }\n v9[i] = v7 + 1;\n LABEL_13:;\n }\n }\n return (unsigned int)v9[a2 - 1];\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n signed long long v2;\n void *v3;\n long long result;\n long long i;\n long long v6;\n int v7;\n uint32_t v9[2];\n unsigned long long v10;\n v10 = __readfsqword(40u);\n while (v9 !=\n (uint32_t *)((char *)v9 - ((4LL * a2 + 15) & 18446744073709547520LL)))\n ;\n v2 = (4 * (unsigned short)a2 + 15) & 4080;\n v3 = alloca(v2);\n if (((4 * (unsigned short)a2 + 15) & 4080) != 0)\n *(uint64_t *)((char *)&v9[-2] + v2) = *(uint64_t *)((char *)&v9[-2] + v2);\n result = 2147483647LL;\n if (a2 && *a1) {\n v9[0] = 0;\n if (a2 > 1) {\n for (i = 1LL; i != a2; ++i) {\n while (1) {\n v9[i] = 2147483647;\n if ((int)i > 0) break;\n ++i;\n }\n v6 = 0LL;\n while (1) {\n if (a1[v6] + (int)v6 >= (int)i) {\n v7 = v9[v6];\n if (v7 != 2147483647) break;\n }\n if (++v6 == i) goto LABEL_13;\n }\n v9[i] = v7 + 1;\n LABEL_13:;\n }\n }\n return (unsigned int)v9[a2 - 1];\n }\n return result;\n}" + }, + { + "index": 689, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int jumps[n];\n if (n == 0 || arr[0] == 0) {\n return INT_MAX;\n }\n jumps[0] = 0;\n for (int i = 1; i < n; i++) {\n jumps[i] = INT_MAX;\n for (int j = 0; j < i; j++) {\n if (i <= j + arr[j] && jumps[j] != INT_MAX) {\n jumps[i] = (jumps[i] < jumps[j] + 1) ? jumps[i] : jumps[j] + 1;\n break;\n }\n }\n }\n return jumps[n - 1];\n}", + "test": "int main() {\n\n int arr1[] = {1, 3, 6, 1, 0, 9};\n\n int arr2[] = {1, 3, 5, 8, 9, 2, 6, 7, 6, 8, 9};\n\n int arr3[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1};\n\n\n\n assert(func0(arr1, 6) == 3);\n\n assert(func0(arr2, 11) == 3);\n\n assert(func0(arr3, 11) == 10);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovslq %esi,%rax\nmov %rsp,%rcx\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rcx\nand $0xfffffffffffffff0,%rdx\nmov %rcx,%rax\ncmp %rax,%rsp\nje 1346 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 1331 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 140a \nlea 0x3(%rsp),%r8\nmov $0x7fffffff,%eax\nmov %r8,%rdx\nand $0xfffffffffffffffc,%r8\nshr $0x2,%rdx\ntest %esi,%esi\nje 13e0 \nmov (%rdi),%r10d\ntest %r10d,%r10d\nje 13e0 \nmovl $0x0,0x0(,%rdx,4)\ncmp $0x1,%esi\njle 13d7 \nlea -0x2(%rsi),%r9d\nmov $0x1,%ecx\nadd $0x2,%r9\nnopw %cs:0x0(%rax,%rax,1)\nmovl $0x7fffffff,(%r8,%rcx,4)\nmov %r10d,%edx\nxor %eax,%eax\njmp 13b3 \nmov (%rdi,%rax,4),%edx\nadd %eax,%edx\ncmp %ecx,%edx\njl 13c5 \nmov (%r8,%rax,4),%edx\ncmp $0x7fffffff,%edx\njne 13f8 \nadd $0x1,%rax\ncmp %rax,%rcx\njne 13b0 \nadd $0x1,%rcx\ncmp %r9,%rcx\njne 13a0 \nlea -0x1(%rsi),%eax\ncltq\nmov (%r8,%rax,4),%eax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\njne 1415 \nleaveq\nretq\nnopl 0x0(%rax)\nadd $0x1,%edx\nmov %edx,(%r8,%rcx,4)\nadd $0x1,%rcx\ncmp %r9,%rcx\njne 13a0 \njmp 13d7 \norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 1358 \ncallq 1060 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov r8d, esi\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmovsxd rax, esi\nmov rcx, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_1316\nloc_1301:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rcx\njnz short loc_1301\nloc_1316:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_13D1\nloc_1328:\nlea rsi, [rsp+1010h+var_100D]\nmov eax, 7FFFFFFFh\nmov rdx, rsi\nand rsi, 0FFFFFFFFFFFFFFFCh\nshr rdx, 2\ntest r8d, r8d\njz short loc_13A7\nmov ecx, [rdi]\ntest ecx, ecx\njz short loc_13A7\nmov ds:dword_0[rdx*4], 0\ncmp r8d, 1\njle short loc_139E\nmov r9d, r8d\nmov edx, 1\nnop dword ptr [rax+00000000h]\nloc_1368:\nmov dword ptr [rsi+rdx*4], 7FFFFFFFh\nxor eax, eax\nnop dword ptr [rax+00000000h]\nloc_1378:\nmov ecx, [rdi+rax*4]\nadd ecx, eax\ncmp ecx, edx\njl short loc_138C\nmov ecx, [rsi+rax*4]\ncmp ecx, 7FFFFFFFh\njnz short loc_13C0\nloc_138C:\nadd rax, 1\ncmp rax, rdx\njnz short loc_1378\nadd rdx, 1\ncmp rdx, r9\njnz short loc_1368\nloc_139E:\nlea eax, [r8-1]\ncdqe\nmov eax, [rsi+rax*4]\nloc_13A7:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_13DC\nleave\nretn\nloc_13C0:\nadd ecx, 1\nmov [rsi+rdx*4], ecx\nadd rdx, 1\ncmp rdx, r9\njnz short loc_1368\njmp short loc_139E\nloc_13D1:\nor [rsp+rdx+1010h+var_1018], 0\njmp loc_1328\nloc_13DC:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n __int64 v2; // rdx\n _DWORD *v3; // rcx\n __int16 v4; // dx\n signed __int64 v5; // rdx\n void *v6; // rsp\n __int64 result; // rax\n __int64 v8; // rdx\n __int64 v9; // rax\n int v10; // ecx\n _DWORD v12[1022]; // [rsp+8h] [rbp-1010h] BYREF\n _QWORD v13[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v13[1] = __readfsqword(0x28u);\n v2 = 4LL * a2 + 15;\n v3 = (_DWORD *)((char *)v13 - (v2 & 0xFFFFFFFFFFFFF000LL));\n v4 = v2 & 0xFFF0;\n if ( v13 != (_QWORD *)v3 )\n {\n while ( v12 != v3 )\n ;\n }\n v5 = v4 & 0xFFF;\n v6 = alloca(v5);\n if ( v5 )\n *(_QWORD *)((char *)&v12[-2] + v5) = *(_QWORD *)((char *)&v12[-2] + v5);\n result = 0x7FFFFFFFLL;\n if ( a2 && *a1 )\n {\n v12[0] = 0;\n if ( a2 > 1 )\n {\n v8 = 1LL;\nLABEL_9:\n while ( 2 )\n {\n v12[v8] = 0x7FFFFFFF;\n v9 = 0LL;\n while ( 1 )\n {\n if ( (int)v9 + a1[v9] >= (int)v8 )\n {\n v10 = v12[v9];\n if ( v10 != 0x7FFFFFFF )\n break;\n }\n if ( ++v9 == v8 )\n {\n if ( ++v8 != a2 )\n goto LABEL_9;\n return (unsigned int)v12[a2 - 1];\n }\n }\n v12[v8++] = v10 + 1;\n if ( v8 != a2 )\n continue;\n break;\n }\n }\n return (unsigned int)v12[a2 - 1];\n }\n return result;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\npush rbp\nmov r8d, esi\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmovsxd rax, esi\nmov rcx, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_1316\nloc_1301:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rcx\njnz short loc_1301\nloc_1316:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_13D1\nloc_1328:\nlea rsi, [rsp+1010h+var_100D]\nmov eax, 7FFFFFFFh\nmov rdx, rsi\nand rsi, 0FFFFFFFFFFFFFFFCh\nshr rdx, 2\ntest r8d, r8d\njz short loc_13A7\nmov ecx, [rdi]\ntest ecx, ecx\njz short loc_13A7\nmov ds:dword_0[rdx*4], 0\ncmp r8d, 1\njle short loc_139E\nmov r9d, r8d\nmov edx, 1\nnop dword ptr [rax+00000000h]\nloc_1368:\nmov dword ptr [rsi+rdx*4], 7FFFFFFFh\nxor eax, eax\nnop dword ptr [rax+00000000h]\nloc_1378:\nmov ecx, [rdi+rax*4]\nadd ecx, eax\ncmp ecx, edx\njl short loc_138C\nmov ecx, [rsi+rax*4]\ncmp ecx, 7FFFFFFFh\njnz short loc_13C0\nloc_138C:\nadd rax, 1\ncmp rax, rdx\njnz short loc_1378\nadd rdx, 1\ncmp rdx, r9\njnz short loc_1368\nloc_139E:\nlea eax, [r8-1]\ncdqe\nmov eax, [rsi+rax*4]\nloc_13A7:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_13DC\nleave\nretn\nloc_13C0:\nadd ecx, 1\nmov [rsi+rdx*4], ecx\nadd rdx, 1\ncmp rdx, r9\njnz short loc_1368\njmp short loc_139E\nloc_13D1:\nor [rsp+rdx+1010h+var_1018], 0\njmp loc_1328\nloc_13DC:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12C0(_DWORD *a1, int a2)\n{\n __int64 v2; // rdx\n _DWORD *v3; // rcx\n __int16 v4; // dx\n signed __int64 v5; // rdx\n void *v6; // rsp\n __int64 result; // rax\n __int64 v8; // rdx\n __int64 v9; // rax\n int v10; // ecx\n _DWORD v12[1022]; // [rsp+8h] [rbp-1010h] BYREF\n _QWORD v13[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v13[1] = __readfsqword(0x28u);\n v2 = 4LL * a2 + 15;\n v3 = (_DWORD *)((char *)v13 - (v2 & 0xFFFFFFFFFFFFF000LL));\n v4 = v2 & 0xFFF0;\n if ( v13 != (_QWORD *)v3 )\n {\n while ( v12 != v3 )\n ;\n }\n v5 = v4 & 0xFFF;\n v6 = alloca(v5);\n if ( v5 )\n *(_QWORD *)((char *)&v12[-2] + v5) = *(_QWORD *)((char *)&v12[-2] + v5);\n result = 0x7FFFFFFFLL;\n if ( a2 && *a1 )\n {\n v12[0] = 0;\n if ( a2 > 1 )\n {\n v8 = 1LL;\nLABEL_9:\n while ( 2 )\n {\n v12[v8] = 0x7FFFFFFF;\n v9 = 0LL;\n while ( 1 )\n {\n if ( (int)v9 + a1[v9] >= (int)v8 )\n {\n v10 = v12[v9];\n if ( v10 != 0x7FFFFFFF )\n break;\n }\n if ( ++v9 == v8 )\n {\n if ( ++v8 != a2 )\n goto LABEL_9;\n return (unsigned int)v12[a2 - 1];\n }\n }\n v12[v8++] = v10 + 1;\n if ( v8 != a2 )\n continue;\n break;\n }\n }\n return (unsigned int)v12[a2 - 1];\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12C0(uint32_t *a1, int a2) {\n long long v2;\n uint32_t *v3;\n short v4;\n signed long long v5;\n void *v6;\n long long result;\n long long v8;\n long long v9;\n int v10;\n uint32_t v12[1022];\n uint64_t v13[2];\n v13[1] = __readfsqword(40u);\n v2 = 4LL * a2 + 15;\n v3 = (uint32_t *)((char *)v13 - (v2 & 18446744073709547520LL));\n v4 = v2 & 65520;\n if (v13 != (uint64_t *)v3) {\n while (v12 != v3)\n ;\n }\n v5 = v4 & 4095;\n v6 = alloca(v5);\n if (v5)\n *(uint64_t *)((char *)&v12[-2] + v5) = *(uint64_t *)((char *)&v12[-2] + v5);\n result = 2147483647LL;\n if (a2 && *a1) {\n v12[0] = 0;\n if (a2 > 1) {\n v8 = 1LL;\n LABEL_9:\n while (2) {\n v12[v8] = 2147483647;\n v9 = 0LL;\n while (1) {\n if ((int)v9 + a1[v9] >= (int)v8) {\n v10 = v12[v9];\n if (v10 != 2147483647) break;\n }\n if (++v9 == v8) {\n if (++v8 != a2) goto LABEL_9;\n return (unsigned int)v12[a2 - 1];\n }\n }\n v12[v8++] = v10 + 1;\n if (v8 != a2) continue;\n break;\n }\n }\n return (unsigned int)v12[a2 - 1];\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n long long v2;\n uint32_t *v3;\n short v4;\n signed long long v5;\n void *v6;\n long long result;\n long long v8;\n long long v9;\n int v10;\n uint32_t v12[1022];\n uint64_t v13[2];\n v13[1] = __readfsqword(40u);\n v2 = 4LL * a2 + 15;\n v3 = (uint32_t *)((char *)v13 - (v2 & 18446744073709547520LL));\n v4 = v2 & 65520;\n if (v13 != (uint64_t *)v3) {\n while (v12 != v3)\n ;\n }\n v5 = v4 & 4095;\n v6 = alloca(v5);\n if (v5)\n *(uint64_t *)((char *)&v12[-2] + v5) = *(uint64_t *)((char *)&v12[-2] + v5);\n result = 2147483647LL;\n if (a2 && *a1) {\n v12[0] = 0;\n if (a2 > 1) {\n v8 = 1LL;\n LABEL_9:\n while (2) {\n v12[v8] = 2147483647;\n v9 = 0LL;\n while (1) {\n if ((int)v9 + a1[v9] >= (int)v8) {\n v10 = v12[v9];\n if (v10 != 2147483647) break;\n }\n if (++v9 == v8) {\n if (++v8 != a2) goto LABEL_9;\n return (unsigned int)v12[a2 - 1];\n }\n }\n v12[v8++] = v10 + 1;\n if (v8 != a2) continue;\n break;\n }\n }\n return (unsigned int)v12[a2 - 1];\n }\n return result;\n}" + }, + { + "index": 689, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int jumps[n];\n if (n == 0 || arr[0] == 0) {\n return INT_MAX;\n }\n jumps[0] = 0;\n for (int i = 1; i < n; i++) {\n jumps[i] = INT_MAX;\n for (int j = 0; j < i; j++) {\n if (i <= j + arr[j] && jumps[j] != INT_MAX) {\n jumps[i] = (jumps[i] < jumps[j] + 1) ? jumps[i] : jumps[j] + 1;\n break;\n }\n }\n }\n return jumps[n - 1];\n}", + "test": "int main() {\n\n int arr1[] = {1, 3, 6, 1, 0, 9};\n\n int arr2[] = {1, 3, 5, 8, 9, 2, 6, 7, 6, 8, 9};\n\n int arr3[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1};\n\n\n\n assert(func0(arr1, 6) == 3);\n\n assert(func0(arr2, 11) == 3);\n\n assert(func0(arr3, 11) == 10);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovslq %esi,%rax\nmov %rsp,%rcx\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rcx\nand $0xfffffffffffffff0,%rdx\nmov %rcx,%rax\ncmp %rax,%rsp\nje 1316 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 1301 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 13d2 \nlea 0x3(%rsp),%r8\nmov $0x7fffffff,%eax\nmov %r8,%rdx\nand $0xfffffffffffffffc,%r8\nshr $0x2,%rdx\ntest %esi,%esi\nje 13a8 \nmov (%rdi),%ecx\ntest %ecx,%ecx\nje 13a8 \nmovl $0x0,0x0(,%rdx,4)\ncmp $0x1,%esi\njle 139f \nlea -0x2(%rsi),%r9d\nmov $0x1,%edx\nadd $0x2,%r9\nnopl 0x0(%rax)\nmovl $0x7fffffff,(%r8,%rdx,4)\nxor %eax,%eax\nnopw 0x0(%rax,%rax,1)\nmov (%rdi,%rax,4),%ecx\nadd %eax,%ecx\ncmp %edx,%ecx\njl 138d \nmov (%r8,%rax,4),%ecx\ncmp $0x7fffffff,%ecx\njne 13c0 \nadd $0x1,%rax\ncmp %rdx,%rax\njne 1378 \nadd $0x1,%rdx\ncmp %r9,%rdx\njne 1368 \nlea -0x1(%rsi),%eax\ncltq\nmov (%r8,%rax,4),%eax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\njne 13dd \nleaveq\nretq\nnopl 0x0(%rax)\nadd $0x1,%ecx\nmov %ecx,(%r8,%rdx,4)\nadd $0x1,%rdx\ncmp %r9,%rdx\njne 1368 \njmp 139f \norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 1328 \ncallq 1060 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov r8d, esi\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmovsxd rax, esi\nmov rcx, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_1316\nloc_1301:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rcx\njnz short loc_1301\nloc_1316:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_13D1\nloc_1328:\nlea rsi, [rsp+1010h+var_100D]\nmov eax, 7FFFFFFFh\nmov rdx, rsi\nand rsi, 0FFFFFFFFFFFFFFFCh\nshr rdx, 2\ntest r8d, r8d\njz short loc_13A7\nmov ecx, [rdi]\ntest ecx, ecx\njz short loc_13A7\nmov ds:dword_0[rdx*4], 0\ncmp r8d, 1\njle short loc_139E\nmov r9d, r8d\nmov edx, 1\nnop dword ptr [rax+00000000h]\nloc_1368:\nmov dword ptr [rsi+rdx*4], 7FFFFFFFh\nxor eax, eax\nnop dword ptr [rax+00000000h]\nloc_1378:\nmov ecx, [rdi+rax*4]\nadd ecx, eax\ncmp ecx, edx\njl short loc_138C\nmov ecx, [rsi+rax*4]\ncmp ecx, 7FFFFFFFh\njnz short loc_13C0\nloc_138C:\nadd rax, 1\ncmp rax, rdx\njnz short loc_1378\nadd rdx, 1\ncmp rdx, r9\njnz short loc_1368\nloc_139E:\nlea eax, [r8-1]\ncdqe\nmov eax, [rsi+rax*4]\nloc_13A7:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_13DC\nleave\nretn\nloc_13C0:\nadd ecx, 1\nmov [rsi+rdx*4], ecx\nadd rdx, 1\ncmp rdx, r9\njnz short loc_1368\njmp short loc_139E\nloc_13D1:\nor [rsp+rdx+1010h+var_1018], 0\njmp loc_1328\nloc_13DC:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n __int64 v2; // rdx\n _DWORD *v3; // rcx\n __int16 v4; // dx\n signed __int64 v5; // rdx\n void *v6; // rsp\n __int64 result; // rax\n __int64 v8; // rdx\n __int64 v9; // rax\n int v10; // ecx\n _DWORD v12[1022]; // [rsp+8h] [rbp-1010h] BYREF\n _QWORD v13[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v13[1] = __readfsqword(0x28u);\n v2 = 4LL * a2 + 15;\n v3 = (_DWORD *)((char *)v13 - (v2 & 0xFFFFFFFFFFFFF000LL));\n v4 = v2 & 0xFFF0;\n if ( v13 != (_QWORD *)v3 )\n {\n while ( v12 != v3 )\n ;\n }\n v5 = v4 & 0xFFF;\n v6 = alloca(v5);\n if ( v5 )\n *(_QWORD *)((char *)&v12[-2] + v5) = *(_QWORD *)((char *)&v12[-2] + v5);\n result = 0x7FFFFFFFLL;\n if ( a2 && *a1 )\n {\n v12[0] = 0;\n if ( a2 > 1 )\n {\n v8 = 1LL;\nLABEL_9:\n while ( 2 )\n {\n v12[v8] = 0x7FFFFFFF;\n v9 = 0LL;\n while ( 1 )\n {\n if ( (int)v9 + a1[v9] >= (int)v8 )\n {\n v10 = v12[v9];\n if ( v10 != 0x7FFFFFFF )\n break;\n }\n if ( ++v9 == v8 )\n {\n if ( ++v8 != a2 )\n goto LABEL_9;\n return (unsigned int)v12[a2 - 1];\n }\n }\n v12[v8++] = v10 + 1;\n if ( v8 != a2 )\n continue;\n break;\n }\n }\n return (unsigned int)v12[a2 - 1];\n }\n return result;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\npush rbp\nmov r8d, esi\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmovsxd rax, esi\nmov rcx, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_1316\nloc_1301:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rcx\njnz short loc_1301\nloc_1316:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_13D1\nloc_1328:\nlea rsi, [rsp+1010h+var_100D]\nmov eax, 7FFFFFFFh\nmov rdx, rsi\nand rsi, 0FFFFFFFFFFFFFFFCh\nshr rdx, 2\ntest r8d, r8d\njz short loc_13A7\nmov ecx, [rdi]\ntest ecx, ecx\njz short loc_13A7\nmov ds:dword_0[rdx*4], 0\ncmp r8d, 1\njle short loc_139E\nmov r9d, r8d\nmov edx, 1\nnop dword ptr [rax+00000000h]\nloc_1368:\nmov dword ptr [rsi+rdx*4], 7FFFFFFFh\nxor eax, eax\nnop dword ptr [rax+00000000h]\nloc_1378:\nmov ecx, [rdi+rax*4]\nadd ecx, eax\ncmp ecx, edx\njl short loc_138C\nmov ecx, [rsi+rax*4]\ncmp ecx, 7FFFFFFFh\njnz short loc_13C0\nloc_138C:\nadd rax, 1\ncmp rax, rdx\njnz short loc_1378\nadd rdx, 1\ncmp rdx, r9\njnz short loc_1368\nloc_139E:\nlea eax, [r8-1]\ncdqe\nmov eax, [rsi+rax*4]\nloc_13A7:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_13DC\nleave\nretn\nloc_13C0:\nadd ecx, 1\nmov [rsi+rdx*4], ecx\nadd rdx, 1\ncmp rdx, r9\njnz short loc_1368\njmp short loc_139E\nloc_13D1:\nor [rsp+rdx+1010h+var_1018], 0\njmp loc_1328\nloc_13DC:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12C0(_DWORD *a1, int a2)\n{\n __int64 v2; // rdx\n _DWORD *v3; // rcx\n __int16 v4; // dx\n signed __int64 v5; // rdx\n void *v6; // rsp\n __int64 result; // rax\n __int64 v8; // rdx\n __int64 v9; // rax\n int v10; // ecx\n _DWORD v12[1022]; // [rsp+8h] [rbp-1010h] BYREF\n _QWORD v13[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v13[1] = __readfsqword(0x28u);\n v2 = 4LL * a2 + 15;\n v3 = (_DWORD *)((char *)v13 - (v2 & 0xFFFFFFFFFFFFF000LL));\n v4 = v2 & 0xFFF0;\n if ( v13 != (_QWORD *)v3 )\n {\n while ( v12 != v3 )\n ;\n }\n v5 = v4 & 0xFFF;\n v6 = alloca(v5);\n if ( v5 )\n *(_QWORD *)((char *)&v12[-2] + v5) = *(_QWORD *)((char *)&v12[-2] + v5);\n result = 0x7FFFFFFFLL;\n if ( a2 && *a1 )\n {\n v12[0] = 0;\n if ( a2 > 1 )\n {\n v8 = 1LL;\nLABEL_9:\n while ( 2 )\n {\n v12[v8] = 0x7FFFFFFF;\n v9 = 0LL;\n while ( 1 )\n {\n if ( (int)v9 + a1[v9] >= (int)v8 )\n {\n v10 = v12[v9];\n if ( v10 != 0x7FFFFFFF )\n break;\n }\n if ( ++v9 == v8 )\n {\n if ( ++v8 != a2 )\n goto LABEL_9;\n return (unsigned int)v12[a2 - 1];\n }\n }\n v12[v8++] = v10 + 1;\n if ( v8 != a2 )\n continue;\n break;\n }\n }\n return (unsigned int)v12[a2 - 1];\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12C0(uint32_t *a1, int a2) {\n long long v2;\n uint32_t *v3;\n short v4;\n signed long long v5;\n void *v6;\n long long result;\n long long v8;\n long long v9;\n int v10;\n uint32_t v12[1022];\n uint64_t v13[2];\n v13[1] = __readfsqword(40u);\n v2 = 4LL * a2 + 15;\n v3 = (uint32_t *)((char *)v13 - (v2 & 18446744073709547520LL));\n v4 = v2 & 65520;\n if (v13 != (uint64_t *)v3) {\n while (v12 != v3)\n ;\n }\n v5 = v4 & 4095;\n v6 = alloca(v5);\n if (v5)\n *(uint64_t *)((char *)&v12[-2] + v5) = *(uint64_t *)((char *)&v12[-2] + v5);\n result = 2147483647LL;\n if (a2 && *a1) {\n v12[0] = 0;\n if (a2 > 1) {\n v8 = 1LL;\n LABEL_9:\n while (2) {\n v12[v8] = 2147483647;\n v9 = 0LL;\n while (1) {\n if ((int)v9 + a1[v9] >= (int)v8) {\n v10 = v12[v9];\n if (v10 != 2147483647) break;\n }\n if (++v9 == v8) {\n if (++v8 != a2) goto LABEL_9;\n return (unsigned int)v12[a2 - 1];\n }\n }\n v12[v8++] = v10 + 1;\n if (v8 != a2) continue;\n break;\n }\n }\n return (unsigned int)v12[a2 - 1];\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n long long v2;\n uint32_t *v3;\n short v4;\n signed long long v5;\n void *v6;\n long long result;\n long long v8;\n long long v9;\n int v10;\n uint32_t v12[1022];\n uint64_t v13[2];\n v13[1] = __readfsqword(40u);\n v2 = 4LL * a2 + 15;\n v3 = (uint32_t *)((char *)v13 - (v2 & 18446744073709547520LL));\n v4 = v2 & 65520;\n if (v13 != (uint64_t *)v3) {\n while (v12 != v3)\n ;\n }\n v5 = v4 & 4095;\n v6 = alloca(v5);\n if (v5)\n *(uint64_t *)((char *)&v12[-2] + v5) = *(uint64_t *)((char *)&v12[-2] + v5);\n result = 2147483647LL;\n if (a2 && *a1) {\n v12[0] = 0;\n if (a2 > 1) {\n v8 = 1LL;\n LABEL_9:\n while (2) {\n v12[v8] = 2147483647;\n v9 = 0LL;\n while (1) {\n if ((int)v9 + a1[v9] >= (int)v8) {\n v10 = v12[v9];\n if (v10 != 2147483647) break;\n }\n if (++v9 == v8) {\n if (++v8 != a2) goto LABEL_9;\n return (unsigned int)v12[a2 - 1];\n }\n }\n v12[v8++] = v10 + 1;\n if (v8 != a2) continue;\n break;\n }\n }\n return (unsigned int)v12[a2 - 1];\n }\n return result;\n}" + }, + { + "index": 690, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int nums[], int length, int* result_length) {\n *result_length = length - 1;\n int* result = (int*)malloc((*result_length) * sizeof(int));\n for (int i = 0; i < *result_length; i++) {\n result[i] = nums[i] * nums[i + 1];\n }\n return result;\n}", + "test": "int main() {\n\n int result_length;\n\n\n\n int test1[] = {1, 1, 3, 4, 4, 5, 6, 7};\n\n int result1[] = {1, 3, 12, 16, 20, 30, 42};\n\n int* computed_result1 = func0(test1, sizeof(test1) / sizeof(test1[0]), &result_length);\n\n for (int i = 0; i < result_length; i++) {\n\n assert(computed_result1[i] == result1[i]);\n\n }\n\n free(computed_result1);\n\n \n\n int test2[] = {4, 5, 8, 9, 6, 10};\n\n int result2[] = {20, 40, 72, 54, 60};\n\n int* computed_result2 = func0(test2, sizeof(test2) / sizeof(test2[0]), &result_length);\n\n for (int i = 0; i < result_length; i++) {\n\n assert(computed_result2[i] == result2[i]);\n\n }\n\n free(computed_result2);\n\n\n\n int test3[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n int result3[] = {2, 6, 12, 20, 30, 42, 56, 72, 90};\n\n int* computed_result3 = func0(test3, sizeof(test3) / sizeof(test3[0]), &result_length);\n\n for (int i = 0; i < result_length; i++) {\n\n assert(computed_result3[i] == result3[i]);\n\n }\n\n free(computed_result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmov -0x1c(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x28(%rbp),%rax\nmov %edx,(%rax)\nmov -0x28(%rbp),%rax\nmov (%rax),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 123b \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%ecx\nmov -0xc(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov -0xc(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rsi\nmov -0x8(%rbp),%rdx\nadd %rsi,%rdx\nimul %ecx,%eax\nmov %eax,(%rdx)\naddl $0x1,-0xc(%rbp)\nmov -0x28(%rbp),%rax\nmov (%rax),%eax\ncmp %eax,-0xc(%rbp)\njl 11ed \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov eax, [rbp+var_1C]\nlea edx, [rax-1]\nmov rax, [rbp+var_28]\nmov [rax], edx\nmov rax, [rbp+var_28]\nmov eax, [rax]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp short loc_123B\nloc_11ED:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nmov ecx, [rbp+var_C]\nmovsxd rcx, ecx\nlea rsi, ds:0[rcx*4]\nmov rcx, [rbp+var_8]\nadd rcx, rsi\nimul eax, edx\nmov [rcx], eax\nadd [rbp+var_C], 1\nloc_123B:\nmov rax, [rbp+var_28]\nmov eax, [rax]\ncmp [rbp+var_C], eax\njl short loc_11ED\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, int *a3)\n{\n int i; // [rsp+24h] [rbp-Ch]\n _DWORD *v6; // [rsp+28h] [rbp-8h]\n\n *a3 = a2 - 1;\n v6 = malloc(4LL * *a3);\n for ( i = 0; i < *a3; ++i )\n v6[i] = *(_DWORD *)(4LL * i + a1) * *(_DWORD *)(4 * (i + 1LL) + a1);\n return v6;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov eax, [rbp+var_1C]\nlea edx, [rax-1]\nmov rax, [rbp+var_28]\nmov [rax], edx\nmov rax, [rbp+var_28]\nmov eax, [rax]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp short loc_123B\nloc_11ED:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nmov ecx, [rbp+var_C]\nmovsxd rcx, ecx\nlea rsi, ds:0[rcx*4]\nmov rcx, [rbp+var_8]\nadd rcx, rsi\nimul eax, edx\nmov [rcx], eax\nadd [rbp+var_C], 1\nloc_123B:\nmov rax, [rbp+var_28]\nmov eax, [rax]\ncmp [rbp+var_C], eax\njl short loc_11ED\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(__int64 a1, int a2, int *a3)\n{\n int i; // [rsp+24h] [rbp-Ch]\n _DWORD *v6; // [rsp+28h] [rbp-8h]\n\n *a3 = a2 - 1;\n v6 = malloc(4LL * *a3);\n for ( i = 0; i < *a3; ++i )\n v6[i] = *(_DWORD *)(4LL * i + a1) * *(_DWORD *)(4 * (i + 1LL) + a1);\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(long long a1, int a2, int *a3) {\n int i;\n uint32_t *v6;\n *a3 = a2 - 1;\n v6 = malloc(4LL * *a3);\n for (i = 0; i < *a3; ++i)\n v6[i] = *(uint32_t *)(4LL * i + a1) * *(uint32_t *)(4 * (i + 1LL) + a1);\n return v6;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, int *a3) {\n int i;\n uint32_t *v6;\n *a3 = a2 - 1;\n v6 = malloc(4LL * *a3);\n for (i = 0; i < *a3; ++i)\n v6[i] = *(uint32_t *)(4LL * i + a1) * *(uint32_t *)(4 * (i + 1LL) + a1);\n return v6;\n}" + }, + { + "index": 690, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int nums[], int length, int* result_length) {\n *result_length = length - 1;\n int* result = (int*)malloc((*result_length) * sizeof(int));\n for (int i = 0; i < *result_length; i++) {\n result[i] = nums[i] * nums[i + 1];\n }\n return result;\n}", + "test": "int main() {\n\n int result_length;\n\n\n\n int test1[] = {1, 1, 3, 4, 4, 5, 6, 7};\n\n int result1[] = {1, 3, 12, 16, 20, 30, 42};\n\n int* computed_result1 = func0(test1, sizeof(test1) / sizeof(test1[0]), &result_length);\n\n for (int i = 0; i < result_length; i++) {\n\n assert(computed_result1[i] == result1[i]);\n\n }\n\n free(computed_result1);\n\n \n\n int test2[] = {4, 5, 8, 9, 6, 10};\n\n int result2[] = {20, 40, 72, 54, 60};\n\n int* computed_result2 = func0(test2, sizeof(test2) / sizeof(test2[0]), &result_length);\n\n for (int i = 0; i < result_length; i++) {\n\n assert(computed_result2[i] == result2[i]);\n\n }\n\n free(computed_result2);\n\n\n\n int test3[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n int result3[] = {2, 6, 12, 20, 30, 42, 56, 72, 90};\n\n int* computed_result3 = func0(test3, sizeof(test3) / sizeof(test3[0]), &result_length);\n\n for (int i = 0; i < result_length; i++) {\n\n assert(computed_result3[i] == result3[i]);\n\n }\n\n free(computed_result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbx\nmov %rdx,%rbp\nsub $0x1,%esi\nmov %esi,(%rdx)\nmovslq %esi,%rsi\nlea 0x0(,%rsi,4),%rdi\ncallq 10b0 \nmov 0x0(%rbp),%edx\ntest %edx,%edx\njle 11f4 \nlea -0x1(%rdx),%esi\nmov $0x0,%edx\nmov (%rbx,%rdx,4),%ecx\nimul 0x4(%rbx,%rdx,4),%ecx\nmov %ecx,(%rax,%rdx,4)\nmov %rdx,%rcx\nadd $0x1,%rdx\ncmp %rsi,%rcx\njne 11dd \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov rbp, rdx\nsub esi, 1\nmov [rdx], esi\nmovsxd rsi, esi\nlea rdi, ds:0[rsi*4]; size\ncall _malloc\nmov esi, [rbp+0]\ntest esi, esi\njle short loc_11F5\nmovsxd rsi, esi\nshl rsi, 2\nmov edx, 0\nloc_11E1:\nmov ecx, [rbx+rdx]\nimul ecx, [rbx+rdx+4]\nmov [rax+rdx], ecx\nadd rdx, 4\ncmp rdx, rsi\njnz short loc_11E1\nloc_11F5:\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2, int *a3)\n{\n int v4; // esi\n char *result; // rax\n __int64 v6; // rsi\n __int64 v7; // rdx\n\n v4 = a2 - 1;\n *a3 = v4;\n result = (char *)malloc(4LL * v4);\n if ( *a3 > 0 )\n {\n v6 = 4LL * *a3;\n v7 = 0LL;\n do\n {\n *(_DWORD *)&result[v7] = *(_DWORD *)(a1 + v7 + 4) * *(_DWORD *)(a1 + v7);\n v7 += 4LL;\n }\n while ( v7 != v6 );\n }\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov rbp, rdx\nsub esi, 1\nmov [rdx], esi\nmovsxd rsi, esi\nlea rdi, ds:0[rsi*4]; size\ncall _malloc\nmov esi, [rbp+0]\ntest esi, esi\njle short loc_11F5\nmovsxd rsi, esi\nshl rsi, 2\nmov edx, 0\nloc_11E1:\nmov ecx, [rbx+rdx]\nimul ecx, [rbx+rdx+4]\nmov [rax+rdx], ecx\nadd rdx, 4\ncmp rdx, rsi\njnz short loc_11E1\nloc_11F5:\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11A9(__int64 a1, int a2, int *a3)\n{\n int v4; // esi\n char *result; // rax\n __int64 v6; // rsi\n __int64 v7; // rdx\n\n v4 = a2 - 1;\n *a3 = v4;\n result = (char *)malloc(4LL * v4);\n if ( *a3 > 0 )\n {\n v6 = 4LL * *a3;\n v7 = 0LL;\n do\n {\n *(_DWORD *)&result[v7] = *(_DWORD *)(a1 + v7 + 4) * *(_DWORD *)(a1 + v7);\n v7 += 4LL;\n }\n while ( v7 != v6 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11A9(long long a1, int a2, int *a3) {\n int v4;\n char *result;\n long long v6;\n long long v7;\n v4 = a2 - 1;\n *a3 = v4;\n result = (char *)malloc(4LL * v4);\n if (*a3 > 0) {\n v6 = 4LL * *a3;\n v7 = 0LL;\n do {\n *(uint32_t *)&result[v7] =\n *(uint32_t *)(a1 + v7 + 4) * *(uint32_t *)(a1 + v7);\n v7 += 4LL;\n } while (v7 != v6);\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2, int *a3) {\n int v4;\n char *result;\n long long v6;\n long long v7;\n v4 = a2 - 1;\n *a3 = v4;\n result = (char *)malloc(4LL * v4);\n if (*a3 > 0) {\n v6 = 4LL * *a3;\n v7 = 0LL;\n do {\n *(uint32_t *)&result[v7] =\n *(uint32_t *)(a1 + v7 + 4) * *(uint32_t *)(a1 + v7);\n v7 += 4LL;\n } while (v7 != v6);\n }\n return result;\n}" + }, + { + "index": 690, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int nums[], int length, int* result_length) {\n *result_length = length - 1;\n int* result = (int*)malloc((*result_length) * sizeof(int));\n for (int i = 0; i < *result_length; i++) {\n result[i] = nums[i] * nums[i + 1];\n }\n return result;\n}", + "test": "int main() {\n\n int result_length;\n\n\n\n int test1[] = {1, 1, 3, 4, 4, 5, 6, 7};\n\n int result1[] = {1, 3, 12, 16, 20, 30, 42};\n\n int* computed_result1 = func0(test1, sizeof(test1) / sizeof(test1[0]), &result_length);\n\n for (int i = 0; i < result_length; i++) {\n\n assert(computed_result1[i] == result1[i]);\n\n }\n\n free(computed_result1);\n\n \n\n int test2[] = {4, 5, 8, 9, 6, 10};\n\n int result2[] = {20, 40, 72, 54, 60};\n\n int* computed_result2 = func0(test2, sizeof(test2) / sizeof(test2[0]), &result_length);\n\n for (int i = 0; i < result_length; i++) {\n\n assert(computed_result2[i] == result2[i]);\n\n }\n\n free(computed_result2);\n\n\n\n int test3[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n int result3[] = {2, 6, 12, 20, 30, 42, 56, 72, 90};\n\n int* computed_result3 = func0(test3, sizeof(test3) / sizeof(test3[0]), &result_length);\n\n for (int i = 0; i < result_length; i++) {\n\n assert(computed_result3[i] == result3[i]);\n\n }\n\n free(computed_result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nsub $0x1,%esi\nmov %rdx,%rbp\npush %rbx\nmov %rdi,%rbx\nsub $0x8,%rsp\nmov %esi,(%rdx)\nmovslq %esi,%rsi\nlea 0x0(,%rsi,4),%rdi\ncallq 10b0 \nmov 0x0(%rbp),%edx\ntest %edx,%edx\njle 14df \nlea -0x1(%rdx),%esi\nxor %edx,%edx\nnopl 0x0(%rax)\nmov (%rbx,%rdx,4),%ecx\nimul 0x4(%rbx,%rdx,4),%ecx\nmov %ecx,(%rax,%rdx,4)\nmov %rdx,%rcx\nadd $0x1,%rdx\ncmp %rsi,%rcx\njne 14c8 \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nsub esi, 1\nmov rbp, rdx\npush rbx\nmov rbx, rdi\nsub rsp, 8\nmov [rdx], esi\nmovsxd rsi, esi\nlea rdi, ds:0[rsi*4]; size\ncall _malloc\nmovsxd rdi, dword ptr [rbp+0]\ntest edi, edi\njle short loc_143D\nmov esi, [rbx]\nshl rdi, 2\nxor edx, edx\nnop dword ptr [rax]\nloc_1428:\nmov ecx, esi\nmov esi, [rbx+rdx+4]\nimul ecx, esi\nmov [rax+rdx], ecx\nadd rdx, 4\ncmp rdi, rdx\njnz short loc_1428\nloc_143D:\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_pseudo": "char *__fastcall func0(int *a1, int a2, int *a3)\n{\n int v3; // esi\n char *result; // rax\n __int64 v7; // rdi\n int v8; // esi\n __int64 v9; // rdi\n unsigned __int64 v10; // rdx\n int v11; // ecx\n\n v3 = a2 - 1;\n *a3 = v3;\n result = (char *)malloc(4LL * v3);\n v7 = *a3;\n if ( (int)v7 > 0 )\n {\n v8 = *a1;\n v9 = 4 * v7;\n v10 = 0LL;\n do\n {\n v11 = v8;\n v8 = a1[v10 / 4 + 1];\n *(_DWORD *)&result[v10] = v8 * v11;\n v10 += 4LL;\n }\n while ( v9 != v10 );\n }\n return result;\n}", + "ida_strip_asm": "sub_13F0:\nendbr64\npush rbp\nsub esi, 1\nmov rbp, rdx\npush rbx\nmov rbx, rdi\nsub rsp, 8\nmov [rdx], esi\nmovsxd rsi, esi\nlea rdi, ds:0[rsi*4]; size\ncall _malloc\nmovsxd rdi, dword ptr [rbp+0]\ntest edi, edi\njle short loc_143D\nmov esi, [rbx]\nshl rdi, 2\nxor edx, edx\nnop dword ptr [rax]\nloc_1428:\nmov ecx, esi\nmov esi, [rbx+rdx+4]\nimul ecx, esi\nmov [rax+rdx], ecx\nadd rdx, 4\ncmp rdi, rdx\njnz short loc_1428\nloc_143D:\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "char *__fastcall sub_13F0(int *a1, int a2, int *a3)\n{\n int v3; // esi\n char *result; // rax\n __int64 v7; // rdi\n int v8; // esi\n __int64 v9; // rdi\n unsigned __int64 v10; // rdx\n int v11; // ecx\n\n v3 = a2 - 1;\n *a3 = v3;\n result = (char *)malloc(4LL * v3);\n v7 = *a3;\n if ( (int)v7 > 0 )\n {\n v8 = *a1;\n v9 = 4 * v7;\n v10 = 0LL;\n do\n {\n v11 = v8;\n v8 = a1[v10 / 4 + 1];\n *(_DWORD *)&result[v10] = v8 * v11;\n v10 += 4LL;\n }\n while ( v9 != v10 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_13F0(int *a1, int a2, int *a3) {\n int v3;\n char *result;\n long long v7;\n int v8;\n long long v9;\n unsigned long long v10;\n int v11;\n v3 = a2 - 1;\n *a3 = v3;\n result = (char *)malloc(4LL * v3);\n v7 = *a3;\n if ((int)v7 > 0) {\n v8 = *a1;\n v9 = 4 * v7;\n v10 = 0LL;\n do {\n v11 = v8;\n v8 = a1[v10 / 4 + 1];\n *(uint32_t *)&result[v10] = v8 * v11;\n v10 += 4LL;\n } while (v9 != v10);\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(int *a1, int a2, int *a3) {\n int v3;\n char *result;\n long long v7;\n int v8;\n long long v9;\n unsigned long long v10;\n int v11;\n v3 = a2 - 1;\n *a3 = v3;\n result = (char *)malloc(4LL * v3);\n v7 = *a3;\n if ((int)v7 > 0) {\n v8 = *a1;\n v9 = 4 * v7;\n v10 = 0LL;\n do {\n v11 = v8;\n v8 = a1[v10 / 4 + 1];\n *(uint32_t *)&result[v10] = v8 * v11;\n v10 += 4LL;\n } while (v9 != v10);\n }\n return result;\n}" + }, + { + "index": 690, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int nums[], int length, int* result_length) {\n *result_length = length - 1;\n int* result = (int*)malloc((*result_length) * sizeof(int));\n for (int i = 0; i < *result_length; i++) {\n result[i] = nums[i] * nums[i + 1];\n }\n return result;\n}", + "test": "int main() {\n\n int result_length;\n\n\n\n int test1[] = {1, 1, 3, 4, 4, 5, 6, 7};\n\n int result1[] = {1, 3, 12, 16, 20, 30, 42};\n\n int* computed_result1 = func0(test1, sizeof(test1) / sizeof(test1[0]), &result_length);\n\n for (int i = 0; i < result_length; i++) {\n\n assert(computed_result1[i] == result1[i]);\n\n }\n\n free(computed_result1);\n\n \n\n int test2[] = {4, 5, 8, 9, 6, 10};\n\n int result2[] = {20, 40, 72, 54, 60};\n\n int* computed_result2 = func0(test2, sizeof(test2) / sizeof(test2[0]), &result_length);\n\n for (int i = 0; i < result_length; i++) {\n\n assert(computed_result2[i] == result2[i]);\n\n }\n\n free(computed_result2);\n\n\n\n int test3[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n int result3[] = {2, 6, 12, 20, 30, 42, 56, 72, 90};\n\n int* computed_result3 = func0(test3, sizeof(test3) / sizeof(test3[0]), &result_length);\n\n for (int i = 0; i < result_length; i++) {\n\n assert(computed_result3[i] == result3[i]);\n\n }\n\n free(computed_result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nsub $0x1,%esi\nmov %rdx,%rbp\npush %rbx\nmov %rdi,%rbx\nsub $0x8,%rsp\nmov %esi,(%rdx)\nmovslq %esi,%rsi\nlea 0x0(,%rsi,4),%rdi\ncallq 10b0 \nmov 0x0(%rbp),%esi\ntest %esi,%esi\njle 15bb \nlea -0x1(%rsi),%edx\ncmp $0x2,%edx\njbe 15c2 \nmov %esi,%ecx\nxor %edx,%edx\nshr $0x2,%ecx\nshl $0x4,%rcx\nnopw 0x0(%rax,%rax,1)\nmovdqu (%rbx,%rdx,1),%xmm0\nmovdqu 0x4(%rbx,%rdx,1),%xmm2\nmovdqu (%rbx,%rdx,1),%xmm1\nmovdqu 0x4(%rbx,%rdx,1),%xmm3\npsrlq $0x20,%xmm0\npsrlq $0x20,%xmm2\npmuludq %xmm3,%xmm1\npmuludq %xmm2,%xmm0\npshufd $0x8,%xmm1,%xmm1\npshufd $0x8,%xmm0,%xmm0\npunpckldq %xmm0,%xmm1\nmovups %xmm1,(%rax,%rdx,1)\nadd $0x10,%rdx\ncmp %rcx,%rdx\njne 1530 \nmov %esi,%edx\nand $0xfffffffc,%edx\ntest $0x3,%sil\nje 15bb \nmovslq %edx,%rcx\nmov 0x4(%rbx,%rcx,4),%edi\nmov (%rbx,%rcx,4),%r8d\nimul %edi,%r8d\nmov %r8d,(%rax,%rcx,4)\nlea 0x1(%rdx),%ecx\ncmp %ecx,%esi\njle 15bb \nmovslq %ecx,%rcx\nadd $0x2,%edx\nmov 0x4(%rbx,%rcx,4),%r8d\nimul %r8d,%edi\nmov %edi,(%rax,%rcx,4)\ncmp %edx,%esi\njle 15bb \nmovslq %edx,%rdx\nimul 0x4(%rbx,%rdx,4),%r8d\nmov %r8d,(%rax,%rdx,4)\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nxor %edx,%edx\njmp 157e \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nsub esi, 1\nmov rbp, rdx\npush rbx\nmov rbx, rdi\nsub rsp, 8\nmov [rdx], esi\nmovsxd rsi, esi\nlea rdi, ds:0[rsi*4]; size\ncall _malloc\nmov esi, [rbp+0]\nmov rcx, rax\ntest esi, esi\njle loc_1501\nlea eax, [rsi-1]\ncmp eax, 2\njbe loc_150B\nmov edx, esi\nxor eax, eax\nshr edx, 2\nshl rdx, 4\nnop word ptr [rax+rax+00h]\nloc_1470:\nmovdqu xmm0, xmmword ptr [rbx+rax]\nmovdqu xmm2, xmmword ptr [rbx+rax+4]\nmovdqu xmm1, xmmword ptr [rbx+rax]\nmovdqu xmm3, xmmword ptr [rbx+rax+4]\npsrlq xmm0, 20h ; ' '\npsrlq xmm2, 20h ; ' '\npmuludq xmm1, xmm3\npmuludq xmm0, xmm2\npshufd xmm1, xmm1, 8\npshufd xmm0, xmm0, 8\npunpckldq xmm1, xmm0\nmovups xmmword ptr [rcx+rax], xmm1\nadd rax, 10h\ncmp rdx, rax\njnz short loc_1470\nmov eax, esi\nand eax, 0FFFFFFFCh\ntest sil, 3\njz short loc_1501\nloc_14BE:\nmovsxd r8, eax\nlea rdx, ds:0[r8*4]\nmov r9d, [rbx+r8*4]\nmov edi, [rbx+rdx+4]\nimul r9d, edi\nmov [rcx+r8*4], r9d\nlea r8d, [rax+1]\ncmp esi, r8d\njle short loc_1501\nmov r8d, [rbx+rdx+8]\nadd eax, 2\nimul edi, r8d\nmov [rcx+rdx+4], edi\ncmp esi, eax\njle short loc_1501\nimul r8d, [rbx+rdx+0Ch]\nmov [rcx+rdx+8], r8d\nloc_1501:\nadd rsp, 8\nmov rax, rcx\npop rbx\npop rbp\nretn\nloc_150B:\nxor eax, eax\njmp short loc_14BE", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2, int *a3)\n{\n int v3; // esi\n char *v6; // rax\n int v7; // esi\n char *v8; // rcx\n __int64 v9; // rax\n signed int v10; // eax\n __int64 v11; // rdx\n int v12; // edi\n int v13; // r8d\n\n v3 = a2 - 1;\n *a3 = v3;\n v6 = (char *)malloc(4LL * v3);\n v7 = *a3;\n v8 = v6;\n if ( *a3 > 0 )\n {\n if ( (unsigned int)(v7 - 1) <= 2 )\n {\n v10 = 0;\n }\n else\n {\n v9 = 0LL;\n do\n {\n *(__m128i *)&v8[v9] = _mm_unpacklo_epi32(\n _mm_shuffle_epi32(\n _mm_mul_epu32(\n _mm_loadu_si128((const __m128i *)(a1 + v9)),\n _mm_loadu_si128((const __m128i *)(a1 + v9 + 4))),\n 8),\n _mm_shuffle_epi32(\n _mm_mul_epu32(\n _mm_srli_epi64(_mm_loadu_si128((const __m128i *)(a1 + v9)), 0x20u),\n _mm_srli_epi64(_mm_loadu_si128((const __m128i *)(a1 + v9 + 4)), 0x20u)),\n 8));\n v9 += 16LL;\n }\n while ( 16LL * ((unsigned int)v7 >> 2) != v9 );\n v10 = v7 & 0xFFFFFFFC;\n if ( (v7 & 3) == 0 )\n return v8;\n }\n v11 = 4LL * v10;\n v12 = *(_DWORD *)(a1 + v11 + 4);\n *(_DWORD *)&v8[v11] = v12 * *(_DWORD *)(a1 + v11);\n if ( v7 > v10 + 1 )\n {\n v13 = *(_DWORD *)(a1 + v11 + 8);\n *(_DWORD *)&v8[v11 + 4] = v13 * v12;\n if ( v7 > v10 + 2 )\n *(_DWORD *)&v8[v11 + 8] = *(_DWORD *)(a1 + v11 + 12) * v13;\n }\n }\n return v8;\n}", + "ida_strip_asm": "sub_1420:\nendbr64\npush rbp\nsub esi, 1\nmov rbp, rdx\npush rbx\nmov rbx, rdi\nsub rsp, 8\nmov [rdx], esi\nmovsxd rsi, esi\nlea rdi, ds:0[rsi*4]; size\ncall _malloc\nmov esi, [rbp+0]\nmov rcx, rax\ntest esi, esi\njle loc_1501\nlea eax, [rsi-1]\ncmp eax, 2\njbe loc_150B\nmov edx, esi\nxor eax, eax\nshr edx, 2\nshl rdx, 4\nnop word ptr [rax+rax+00h]\nloc_1470:\nmovdqu xmm0, xmmword ptr [rbx+rax]\nmovdqu xmm2, xmmword ptr [rbx+rax+4]\nmovdqu xmm1, xmmword ptr [rbx+rax]\nmovdqu xmm3, xmmword ptr [rbx+rax+4]\npsrlq xmm0, 20h ; ' '\npsrlq xmm2, 20h ; ' '\npmuludq xmm1, xmm3\npmuludq xmm0, xmm2\npshufd xmm1, xmm1, 8\npshufd xmm0, xmm0, 8\npunpckldq xmm1, xmm0\nmovups xmmword ptr [rcx+rax], xmm1\nadd rax, 10h\ncmp rdx, rax\njnz short loc_1470\nmov eax, esi\nand eax, 0FFFFFFFCh\ntest sil, 3\njz short loc_1501\nloc_14BE:\nmovsxd r8, eax\nlea rdx, ds:0[r8*4]\nmov r9d, [rbx+r8*4]\nmov edi, [rbx+rdx+4]\nimul r9d, edi\nmov [rcx+r8*4], r9d\nlea r8d, [rax+1]\ncmp esi, r8d\njle short loc_1501\nmov r8d, [rbx+rdx+8]\nadd eax, 2\nimul edi, r8d\nmov [rcx+rdx+4], edi\ncmp esi, eax\njle short loc_1501\nimul r8d, [rbx+rdx+0Ch]\nmov [rcx+rdx+8], r8d\nloc_1501:\nadd rsp, 8\nmov rax, rcx\npop rbx\npop rbp\nretn\nloc_150B:\nxor eax, eax\njmp short loc_14BE", + "ida_strip_pseudo": "char *__fastcall sub_1420(__int64 a1, int a2, int *a3)\n{\n int v3; // esi\n char *v6; // rax\n int v7; // esi\n char *v8; // rcx\n __int64 v9; // rax\n signed int v10; // eax\n __int64 v11; // rdx\n int v12; // edi\n int v13; // r8d\n\n v3 = a2 - 1;\n *a3 = v3;\n v6 = (char *)malloc(4LL * v3);\n v7 = *a3;\n v8 = v6;\n if ( *a3 > 0 )\n {\n if ( (unsigned int)(v7 - 1) <= 2 )\n {\n v10 = 0;\n }\n else\n {\n v9 = 0LL;\n do\n {\n *(__m128i *)&v8[v9] = _mm_unpacklo_epi32(\n _mm_shuffle_epi32(\n _mm_mul_epu32(\n _mm_loadu_si128((const __m128i *)(a1 + v9)),\n _mm_loadu_si128((const __m128i *)(a1 + v9 + 4))),\n 8),\n _mm_shuffle_epi32(\n _mm_mul_epu32(\n _mm_srli_epi64(_mm_loadu_si128((const __m128i *)(a1 + v9)), 0x20u),\n _mm_srli_epi64(_mm_loadu_si128((const __m128i *)(a1 + v9 + 4)), 0x20u)),\n 8));\n v9 += 16LL;\n }\n while ( 16LL * ((unsigned int)v7 >> 2) != v9 );\n v10 = v7 & 0xFFFFFFFC;\n if ( (v7 & 3) == 0 )\n return v8;\n }\n v11 = 4LL * v10;\n v12 = *(_DWORD *)(a1 + v11 + 4);\n *(_DWORD *)&v8[v11] = v12 * *(_DWORD *)(a1 + v11);\n if ( v7 > v10 + 1 )\n {\n v13 = *(_DWORD *)(a1 + v11 + 8);\n *(_DWORD *)&v8[v11 + 4] = v13 * v12;\n if ( v7 > v10 + 2 )\n *(_DWORD *)&v8[v11 + 8] = *(_DWORD *)(a1 + v11 + 12) * v13;\n }\n }\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1420(long long a1, int a2, int *a3) {\n int v3;\n char *v6;\n int v7;\n char *v8;\n long long v9;\n signed int v10;\n long long v11;\n int v12;\n int v13;\n v3 = a2 - 1;\n *a3 = v3;\n v6 = (char *)malloc(4LL * v3);\n v7 = *a3;\n v8 = v6;\n if (*a3 > 0) {\n if ((unsigned int)(v7 - 1) <= 2) {\n v10 = 0;\n } else {\n v9 = 0LL;\n do {\n *(__m128i *)&v8[v9] = _mm_unpacklo_epi32(\n _mm_shuffle_epi32(\n _mm_mul_epu32(_mm_loadu_si128((const __m128i *)(a1 + v9)),\n _mm_loadu_si128((const __m128i *)(a1 + v9 + 4))),\n 8),\n _mm_shuffle_epi32(\n _mm_mul_epu32(\n _mm_srli_epi64(_mm_loadu_si128((const __m128i *)(a1 + v9)),\n 32u),\n _mm_srli_epi64(\n _mm_loadu_si128((const __m128i *)(a1 + v9 + 4)), 32u)),\n 8));\n v9 += 16LL;\n } while (16LL * ((unsigned int)v7 >> 2) != v9);\n v10 = v7 & 4294967292;\n if ((v7 & 3) == 0) return v8;\n }\n v11 = 4LL * v10;\n v12 = *(uint32_t *)(a1 + v11 + 4);\n *(uint32_t *)&v8[v11] = v12 * *(uint32_t *)(a1 + v11);\n if (v7 > v10 + 1) {\n v13 = *(uint32_t *)(a1 + v11 + 8);\n *(uint32_t *)&v8[v11 + 4] = v13 * v12;\n if (v7 > v10 + 2)\n *(uint32_t *)&v8[v11 + 8] = *(uint32_t *)(a1 + v11 + 12) * v13;\n }\n }\n return v8;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2, int *a3) {\n int v3;\n char *v6;\n int v7;\n char *v8;\n long long v9;\n signed int v10;\n long long v11;\n int v12;\n int v13;\n v3 = a2 - 1;\n *a3 = v3;\n v6 = (char *)malloc(4LL * v3);\n v7 = *a3;\n v8 = v6;\n if (*a3 > 0) {\n if ((unsigned int)(v7 - 1) <= 2) {\n v10 = 0;\n } else {\n v9 = 0LL;\n do {\n *(__m128i *)&v8[v9] = _mm_unpacklo_epi32(\n _mm_shuffle_epi32(\n _mm_mul_epu32(_mm_loadu_si128((const __m128i *)(a1 + v9)),\n _mm_loadu_si128((const __m128i *)(a1 + v9 + 4))),\n 8),\n _mm_shuffle_epi32(\n _mm_mul_epu32(\n _mm_srli_epi64(_mm_loadu_si128((const __m128i *)(a1 + v9)),\n 32u),\n _mm_srli_epi64(\n _mm_loadu_si128((const __m128i *)(a1 + v9 + 4)), 32u)),\n 8));\n v9 += 16LL;\n } while (16LL * ((unsigned int)v7 >> 2) != v9);\n v10 = v7 & 4294967292;\n if ((v7 & 3) == 0) return v8;\n }\n v11 = 4LL * v10;\n v12 = *(uint32_t *)(a1 + v11 + 4);\n *(uint32_t *)&v8[v11] = v12 * *(uint32_t *)(a1 + v11);\n if (v7 > v10 + 1) {\n v13 = *(uint32_t *)(a1 + v11 + 8);\n *(uint32_t *)&v8[v11 + 4] = v13 * v12;\n if (v7 > v10 + 2)\n *(uint32_t *)&v8[v11 + 8] = *(uint32_t *)(a1 + v11 + 12) * v13;\n }\n }\n return v8;\n}" + }, + { + "index": 691, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct Pair {\n\n int first;\n\n int second;\n\n} Pair;\n\n\n\ntypedef struct List {\n\n int value;\n\n struct List *next;\n\n} List;\n\n\n\ntypedef struct Map {\n\n int key;\n\n List *values;\n\n struct Map *next;\n\n} Map;\n\n\n\nint compare_pairs(const void *a, const void *b) {\n\n Pair *pa = (Pair *)a;\n\n Pair *pb = (Pair *)b;\n\n return pa->second - pb->second;\n\n}\n\n\n\nvoid add_to_map(Map **map, int key, int value) {\n\n Map *cursor = *map;\n\n Map *prev = NULL;\n\n List *newList = NULL;\n\n \n\n while (cursor) {\n\n if (cursor->key == key) {\n\n newList = (List *)malloc(sizeof(List));\n\n newList->value = value;\n\n newList->next = cursor->values;\n\n cursor->values = newList;\n\n return;\n\n }\n\n prev = cursor;\n\n cursor = cursor->next;\n\n }\n\n\n\n Map *newMap = (Map *)malloc(sizeof(Map));\n\n newMap->key = key;\n\n newMap->values = (List *)malloc(sizeof(List));\n\n newMap->values->value = value;\n\n newMap->values->next = NULL;\n\n newMap->next = NULL;\n\n\n\n if (prev) {\n\n prev->next = newMap;\n\n } else {\n\n *map = newMap;\n\n }\n\n}\n\n\n\nvoid free_map(Map *map) {\n\n while (map != NULL) {\n\n List *list = map->values;\n\n while (list != NULL) {\n\n List *tempList = list;\n\n list = list->next;\n\n free(tempList);\n\n }\n\n Map *tempMap = map;\n\n map = map->next;\n\n free(tempMap);\n\n }\n\n}\n\n\n\n", + "func": "Map *func0(Pair *test_list, int size) {\n qsort(test_list, size, sizeof(Pair), compare_pairs);\n Map *result = NULL;\n for (int i = 0; i < size; ++i) {\n add_to_map(&result, test_list[i].second, test_list[i].first);\n }\n return result;\n}", + "test": "int main() {\n\n Pair pairs1[] = {{6, 5}, {2, 7}, {2, 5}, {8, 7}, {9, 8}, {3, 7}};\n\n Pair pairs2[] = {{7, 6}, {3, 8}, {3, 6}, {9, 8}, {10, 9}, {4, 8}};\n\n Pair pairs3[] = {{8, 7}, {4, 9}, {4, 7}, {10, 9}, {11, 10}, {5, 9}};\n\n Map *map_result;\n\n\n\n map_result = func0(pairs1, 6);\n\n assert(map_result && map_result->key == 5 && map_result->next->key == 7 && map_result->next->next->key == 8);\n\n free_map(map_result);\n\n\n\n map_result = func0(pairs2, 6);\n\n assert(map_result && map_result->key == 6 && map_result->next->key == 8 && map_result->next->next->key == 9);\n\n free_map(map_result);\n\n\n\n map_result = func0(pairs3, 6);\n\n assert(map_result && map_result->key == 7 && map_result->next->key == 9 && map_result->next->next->key == 10);\n\n free_map(map_result);\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmov -0x2c(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x28(%rbp),%rax\nlea -0x1e1(%rip),%rcx\nmov $0x8,%edx\nmov %rax,%rdi\ncallq 10a0 \nmovq $0x0,-0x10(%rbp)\nmovl $0x0,-0x14(%rbp)\njmp 1407 \nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov 0x4(%rax),%ecx\nlea -0x10(%rbp),%rax\nmov %ecx,%esi\nmov %rax,%rdi\ncallq 11fd \naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 13c8 \nmov -0x10(%rbp),%rax\nmov -0x8(%rbp),%rdi\nxor %fs:0x28,%rdi\nje 1427 \ncallq 10b0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+base], rdi\nmov [rbp+var_2C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov eax, [rbp+var_2C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compare_pairs\nmov rcx, rdx; compar\nmov edx, 8; size\nmov rdi, rax; base\ncall _qsort\nmov [rbp+var_10], 0\nmov [rbp+var_14], 0\njmp short loc_140A\nloc_13CB:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_14]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rax, rcx\nmov ecx, [rax+4]\nlea rax, [rbp+var_10]\nmov esi, ecx\nmov rdi, rax\ncall add_to_map\nadd [rbp+var_14], 1\nloc_140A:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl short loc_13CB\nmov rax, [rbp+var_10]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_142A\ncall ___stack_chk_fail\nlocret_142A:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n int i; // [rsp+1Ch] [rbp-14h]\n _QWORD v4[2]; // [rsp+20h] [rbp-10h] BYREF\n\n v4[1] = __readfsqword(0x28u);\n qsort(a1, a2, 8uLL, compare_pairs);\n v4[0] = 0LL;\n for ( i = 0; i < a2; ++i )\n add_to_map(v4, a1[2 * i + 1], a1[2 * i]);\n return v4[0];\n}", + "ida_strip_asm": "sub_1377:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+base], rdi\nmov [rbp+var_2C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov eax, [rbp+var_2C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 8; size\nmov rdi, rax; base\ncall _qsort\nmov [rbp+var_10], 0\nmov [rbp+var_14], 0\njmp short loc_140A\nloc_13CB:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_14]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+base]\nadd rax, rcx\nmov ecx, [rax+4]\nlea rax, [rbp+var_10]\nmov esi, ecx\nmov rdi, rax\ncall sub_11FD\nadd [rbp+var_14], 1\nloc_140A:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl short loc_13CB\nmov rax, [rbp+var_10]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_142A\ncall ___stack_chk_fail\nlocret_142A:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1377(unsigned int *a1, int a2)\n{\n int i; // [rsp+1Ch] [rbp-14h]\n _QWORD v4[2]; // [rsp+20h] [rbp-10h] BYREF\n\n v4[1] = __readfsqword(0x28u);\n qsort(a1, a2, 8uLL, compar);\n v4[0] = 0LL;\n for ( i = 0; i < a2; ++i )\n sub_11FD(v4, a1[2 * i + 1], a1[2 * i]);\n return v4[0];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1377(unsigned int *a1, int a2) {\n int i;\n uint64_t v4[2];\n v4[1] = __readfsqword(40u);\n qsort(a1, a2, 8uLL, compar);\n v4[0] = 0LL;\n for (i = 0; i < a2; ++i) sub_11FD(v4, a1[2 * i + 1], a1[2 * i]);\n return v4[0];\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n int i;\n uint64_t v4[2];\n v4[1] = __readfsqword(40u);\n qsort(a1, a2, 8uLL, compare_pairs);\n v4[0] = 0LL;\n for (i = 0; i < a2; ++i) add_to_map(v4, a1[2 * i + 1], a1[2 * i]);\n return v4[0];\n}" + }, + { + "index": 691, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct Pair {\n\n int first;\n\n int second;\n\n} Pair;\n\n\n\ntypedef struct List {\n\n int value;\n\n struct List *next;\n\n} List;\n\n\n\ntypedef struct Map {\n\n int key;\n\n List *values;\n\n struct Map *next;\n\n} Map;\n\n\n\nint compare_pairs(const void *a, const void *b) {\n\n Pair *pa = (Pair *)a;\n\n Pair *pb = (Pair *)b;\n\n return pa->second - pb->second;\n\n}\n\n\n\nvoid add_to_map(Map **map, int key, int value) {\n\n Map *cursor = *map;\n\n Map *prev = NULL;\n\n List *newList = NULL;\n\n \n\n while (cursor) {\n\n if (cursor->key == key) {\n\n newList = (List *)malloc(sizeof(List));\n\n newList->value = value;\n\n newList->next = cursor->values;\n\n cursor->values = newList;\n\n return;\n\n }\n\n prev = cursor;\n\n cursor = cursor->next;\n\n }\n\n\n\n Map *newMap = (Map *)malloc(sizeof(Map));\n\n newMap->key = key;\n\n newMap->values = (List *)malloc(sizeof(List));\n\n newMap->values->value = value;\n\n newMap->values->next = NULL;\n\n newMap->next = NULL;\n\n\n\n if (prev) {\n\n prev->next = newMap;\n\n } else {\n\n *map = newMap;\n\n }\n\n}\n\n\n\nvoid free_map(Map *map) {\n\n while (map != NULL) {\n\n List *list = map->values;\n\n while (list != NULL) {\n\n List *tempList = list;\n\n list = list->next;\n\n free(tempList);\n\n }\n\n Map *tempMap = map;\n\n map = map->next;\n\n free(tempMap);\n\n }\n\n}\n\n\n\n", + "func": "Map *func0(Pair *test_list, int size) {\n qsort(test_list, size, sizeof(Pair), compare_pairs);\n Map *result = NULL;\n for (int i = 0; i < size; ++i) {\n add_to_map(&result, test_list[i].second, test_list[i].first);\n }\n return result;\n}", + "test": "int main() {\n\n Pair pairs1[] = {{6, 5}, {2, 7}, {2, 5}, {8, 7}, {9, 8}, {3, 7}};\n\n Pair pairs2[] = {{7, 6}, {3, 8}, {3, 6}, {9, 8}, {10, 9}, {4, 8}};\n\n Pair pairs3[] = {{8, 7}, {4, 9}, {4, 7}, {10, 9}, {11, 10}, {5, 9}};\n\n Map *map_result;\n\n\n\n map_result = func0(pairs1, 6);\n\n assert(map_result && map_result->key == 5 && map_result->next->key == 7 && map_result->next->next->key == 8);\n\n free_map(map_result);\n\n\n\n map_result = func0(pairs2, 6);\n\n assert(map_result && map_result->key == 6 && map_result->next->key == 8 && map_result->next->next->key == 9);\n\n free_map(map_result);\n\n\n\n map_result = func0(pairs3, 6);\n\n assert(map_result && map_result->key == 7 && map_result->next->key == 9 && map_result->next->next->key == 10);\n\n free_map(map_result);\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nsub $0x10,%rsp\nmov %rdi,%r12\nmov %esi,%ebp\nmov %fs:0x28,%rax\nmov %rax,0x8(%rsp)\nxor %eax,%eax\nmovslq %esi,%rsi\nlea -0x13f(%rip),%rcx\nmov $0x8,%edx\ncallq 10a0 \nmovq $0x0,(%rsp)\ntest %ebp,%ebp\njle 1342 \nmov %r12,%rbx\nlea -0x1(%rbp),%eax\nlea 0x8(%r12,%rax,8),%r12\nmov %rsp,%rbp\nmov 0x4(%rbx),%esi\nmov (%rbx),%edx\nmov %rbp,%rdi\ncallq 11d4 \nadd $0x8,%rbx\ncmp %r12,%rbx\njne 132c \nmov (%rsp),%rax\nmov 0x8(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 135f \nadd $0x10,%rsp\npop %rbx\npop %rbp\npop %r12\nretq\ncallq 10b0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 10h\nmov rbp, rdi\nmov ebx, esi\nmov rax, fs:28h\nmov [rsp+28h+var_20], rax\nxor eax, eax\nmovsxd r12, esi\nlea rcx, compare_pairs; compar\nmov edx, 8; size\nmov rsi, r12; nmemb\ncall _qsort\nmov [rsp+28h+var_28], 0\ntest ebx, ebx\njle short loc_1342\nmov rbx, rbp\nlea r12, [rbp+r12*8+0]\nmov rbp, rsp\nloc_132C:\nmov edx, [rbx]\nmov esi, [rbx+4]\nmov rdi, rbp\ncall add_to_map\nadd rbx, 8\ncmp rbx, r12\njnz short loc_132C\nloc_1342:\nmov rax, [rsp+28h+var_28]\nmov rdx, [rsp+28h+var_20]\nsub rdx, fs:28h\njnz short loc_135F\nadd rsp, 10h\npop rbx\npop rbp\npop r12\nretn\nloc_135F:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n unsigned int *v2; // rbx\n _QWORD v4[5]; // [rsp+0h] [rbp-28h] BYREF\n\n v4[1] = __readfsqword(0x28u);\n qsort(a1, a2, 8uLL, compare_pairs);\n v4[0] = 0LL;\n if ( a2 > 0 )\n {\n v2 = a1;\n do\n {\n add_to_map(v4, v2[1], *v2);\n v2 += 2;\n }\n while ( v2 != &a1[2 * a2] );\n }\n return v4[0];\n}", + "ida_strip_asm": "sub_12DD:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 10h\nmov rbp, rdi\nmov ebx, esi\nmov rax, fs:28h\nmov [rsp+28h+var_20], rax\nxor eax, eax\nmovsxd r12, esi\nlea rcx, compar; compar\nmov edx, 8; size\nmov rsi, r12; nmemb\ncall _qsort\nmov [rsp+28h+var_28], 0\ntest ebx, ebx\njle short loc_1342\nmov rbx, rbp\nlea r12, [rbp+r12*8+0]\nmov rbp, rsp\nloc_132C:\nmov edx, [rbx]\nmov esi, [rbx+4]\nmov rdi, rbp\ncall sub_11D4\nadd rbx, 8\ncmp rbx, r12\njnz short loc_132C\nloc_1342:\nmov rax, [rsp+28h+var_28]\nmov rdx, [rsp+28h+var_20]\nsub rdx, fs:28h\njnz short loc_135F\nadd rsp, 10h\npop rbx\npop rbp\npop r12\nretn\nloc_135F:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12DD(unsigned int *a1, int a2)\n{\n unsigned int *v2; // rbx\n _QWORD v4[5]; // [rsp+0h] [rbp-28h] BYREF\n\n v4[1] = __readfsqword(0x28u);\n qsort(a1, a2, 8uLL, compar);\n v4[0] = 0LL;\n if ( a2 > 0 )\n {\n v2 = a1;\n do\n {\n sub_11D4(v4, v2[1], *v2);\n v2 += 2;\n }\n while ( v2 != &a1[2 * a2] );\n }\n return v4[0];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12DD(unsigned int *a1, int a2) {\n unsigned int *v2;\n uint64_t v4[5];\n v4[1] = __readfsqword(40u);\n qsort(a1, a2, 8uLL, compar);\n v4[0] = 0LL;\n if (a2 > 0) {\n v2 = a1;\n do {\n sub_11D4(v4, v2[1], *v2);\n v2 += 2;\n } while (v2 != &a1[2 * a2]);\n }\n return v4[0];\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n unsigned int *v2;\n uint64_t v4[5];\n v4[1] = __readfsqword(40u);\n qsort(a1, a2, 8uLL, compare_pairs);\n v4[0] = 0LL;\n if (a2 > 0) {\n v2 = a1;\n do {\n add_to_map(v4, v2[1], *v2);\n v2 += 2;\n } while (v2 != &a1[2 * a2]);\n }\n return v4[0];\n}" + }, + { + "index": 691, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct Pair {\n\n int first;\n\n int second;\n\n} Pair;\n\n\n\ntypedef struct List {\n\n int value;\n\n struct List *next;\n\n} List;\n\n\n\ntypedef struct Map {\n\n int key;\n\n List *values;\n\n struct Map *next;\n\n} Map;\n\n\n\nint compare_pairs(const void *a, const void *b) {\n\n Pair *pa = (Pair *)a;\n\n Pair *pb = (Pair *)b;\n\n return pa->second - pb->second;\n\n}\n\n\n\nvoid add_to_map(Map **map, int key, int value) {\n\n Map *cursor = *map;\n\n Map *prev = NULL;\n\n List *newList = NULL;\n\n \n\n while (cursor) {\n\n if (cursor->key == key) {\n\n newList = (List *)malloc(sizeof(List));\n\n newList->value = value;\n\n newList->next = cursor->values;\n\n cursor->values = newList;\n\n return;\n\n }\n\n prev = cursor;\n\n cursor = cursor->next;\n\n }\n\n\n\n Map *newMap = (Map *)malloc(sizeof(Map));\n\n newMap->key = key;\n\n newMap->values = (List *)malloc(sizeof(List));\n\n newMap->values->value = value;\n\n newMap->values->next = NULL;\n\n newMap->next = NULL;\n\n\n\n if (prev) {\n\n prev->next = newMap;\n\n } else {\n\n *map = newMap;\n\n }\n\n}\n\n\n\nvoid free_map(Map *map) {\n\n while (map != NULL) {\n\n List *list = map->values;\n\n while (list != NULL) {\n\n List *tempList = list;\n\n list = list->next;\n\n free(tempList);\n\n }\n\n Map *tempMap = map;\n\n map = map->next;\n\n free(tempMap);\n\n }\n\n}\n\n\n\n", + "func": "Map *func0(Pair *test_list, int size) {\n qsort(test_list, size, sizeof(Pair), compare_pairs);\n Map *result = NULL;\n for (int i = 0; i < size; ++i) {\n add_to_map(&result, test_list[i].second, test_list[i].first);\n }\n return result;\n}", + "test": "int main() {\n\n Pair pairs1[] = {{6, 5}, {2, 7}, {2, 5}, {8, 7}, {9, 8}, {3, 7}};\n\n Pair pairs2[] = {{7, 6}, {3, 8}, {3, 6}, {9, 8}, {10, 9}, {4, 8}};\n\n Pair pairs3[] = {{8, 7}, {4, 9}, {4, 7}, {10, 9}, {11, 10}, {5, 9}};\n\n Map *map_result;\n\n\n\n map_result = func0(pairs1, 6);\n\n assert(map_result && map_result->key == 5 && map_result->next->key == 7 && map_result->next->next->key == 8);\n\n free_map(map_result);\n\n\n\n map_result = func0(pairs2, 6);\n\n assert(map_result && map_result->key == 6 && map_result->next->key == 8 && map_result->next->next->key == 9);\n\n free_map(map_result);\n\n\n\n map_result = func0(pairs3, 6);\n\n assert(map_result && map_result->key == 7 && map_result->next->key == 9 && map_result->next->next->key == 10);\n\n free_map(map_result);\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmovslq %esi,%rsi\nmov $0x8,%edx\nlea -0x165(%rip),%rcx\npush %rbp\nmov %rsi,%rbp\npush %rbx\nmov %rdi,%rbx\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x8(%rsp)\nxor %eax,%eax\ncallq 10a0 \nmovq $0x0,(%rsp)\ntest %ebp,%ebp\njle 15e8 \nlea -0x1(%rbp),%eax\nmov %rsp,%rbp\nlea 0x8(%rbx,%rax,8),%r12\nnopl (%rax)\nmov 0x4(%rbx),%esi\nmov (%rbx),%edx\nmov %rbp,%rdi\nadd $0x8,%rbx\ncallq 1420 \ncmp %r12,%rbx\njne 15b0 \nmov (%rsp),%rax\nmov 0x8(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 15ec \nadd $0x10,%rsp\npop %rbx\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax,%rax,1)\nxor %eax,%eax\njmp 15ca \ncallq 10b0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r12\nmovsxd r12, esi\nlea rcx, compare_pairs; compar\nmov edx, 8; size\npush rbp\nmov rsi, r12; nmemb\npush rbx\nmov rbx, rdi\nsub rsp, 10h\nmov rax, fs:28h\nmov [rsp+28h+var_20], rax\nxor eax, eax\ncall _qsort\nmov [rsp+28h+var_28], 0\ntest r12d, r12d\njle short loc_1578\nlea r12, [rbx+r12*8]\nmov rbp, rsp\nnop word ptr [rax+rax+00h]\nloc_1540:\nmov edx, [rbx]\nmov esi, [rbx+4]\nmov rdi, rbp\nadd rbx, 8\ncall add_to_map\ncmp rbx, r12\njnz short loc_1540\nmov rax, [rsp+28h+var_28]\nloc_155A:\nmov rdx, [rsp+28h+var_20]\nsub rdx, fs:28h\njnz short loc_157C\nadd rsp, 10h\npop rbx\npop rbp\npop r12\nretn\nloc_1578:\nxor eax, eax\njmp short loc_155A\nloc_157C:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n unsigned int *v2; // rbx\n unsigned int *v3; // r12\n __int64 v4; // rdx\n __int64 v5; // rsi\n _QWORD v7[5]; // [rsp+0h] [rbp-28h] BYREF\n\n v2 = a1;\n v7[1] = __readfsqword(0x28u);\n qsort(a1, a2, 8uLL, compare_pairs);\n v7[0] = 0LL;\n if ( a2 <= 0 )\n return 0LL;\n v3 = &a1[2 * a2];\n do\n {\n v4 = *v2;\n v5 = v2[1];\n v2 += 2;\n add_to_map(v7, v5, v4);\n }\n while ( v2 != v3 );\n return v7[0];\n}", + "ida_strip_asm": "sub_14F0:\nendbr64\npush r12\nmovsxd r12, esi\nlea rcx, compar; compar\nmov edx, 8; size\npush rbp\nmov rsi, r12; nmemb\npush rbx\nmov rbx, rdi\nsub rsp, 10h\nmov rax, fs:28h\nmov [rsp+28h+var_20], rax\nxor eax, eax\ncall _qsort\nmov [rsp+28h+var_28], 0\ntest r12d, r12d\njle short loc_1578\nlea r12, [rbx+r12*8]\nmov rbp, rsp\nnop word ptr [rax+rax+00h]\nloc_1540:\nmov edx, [rbx]\nmov esi, [rbx+4]\nmov rdi, rbp\nadd rbx, 8\ncall sub_13B0\ncmp rbx, r12\njnz short loc_1540\nmov rax, [rsp+28h+var_28]\nloc_155A:\nmov rdx, [rsp+28h+var_20]\nsub rdx, fs:28h\njnz short loc_157C\nadd rsp, 10h\npop rbx\npop rbp\npop r12\nretn\nloc_1578:\nxor eax, eax\njmp short loc_155A\nloc_157C:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_14F0(unsigned int *a1, int a2)\n{\n unsigned int *v2; // rbx\n unsigned int *v3; // r12\n __int64 v4; // rdx\n __int64 v5; // rsi\n _QWORD v7[5]; // [rsp+0h] [rbp-28h] BYREF\n\n v2 = a1;\n v7[1] = __readfsqword(0x28u);\n qsort(a1, a2, 8uLL, compar);\n v7[0] = 0LL;\n if ( a2 <= 0 )\n return 0LL;\n v3 = &a1[2 * a2];\n do\n {\n v4 = *v2;\n v5 = v2[1];\n v2 += 2;\n sub_13B0(v7, v5, v4);\n }\n while ( v2 != v3 );\n return v7[0];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_14F0(unsigned int *a1, int a2) {\n unsigned int *v2;\n unsigned int *v3;\n long long v4;\n long long v5;\n uint64_t v7[5];\n v2 = a1;\n v7[1] = __readfsqword(40u);\n qsort(a1, a2, 8uLL, compar);\n v7[0] = 0LL;\n if (a2 <= 0) return 0LL;\n v3 = &a1[2 * a2];\n do {\n v4 = *v2;\n v5 = v2[1];\n v2 += 2;\n sub_13B0(v7, v5, v4);\n } while (v2 != v3);\n return v7[0];\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n unsigned int *v2;\n unsigned int *v3;\n long long v4;\n long long v5;\n uint64_t v7[5];\n v2 = a1;\n v7[1] = __readfsqword(40u);\n qsort(a1, a2, 8uLL, compare_pairs);\n v7[0] = 0LL;\n if (a2 <= 0) return 0LL;\n v3 = &a1[2 * a2];\n do {\n v4 = *v2;\n v5 = v2[1];\n v2 += 2;\n add_to_map(v7, v5, v4);\n } while (v2 != v3);\n return v7[0];\n}" + }, + { + "index": 691, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct Pair {\n\n int first;\n\n int second;\n\n} Pair;\n\n\n\ntypedef struct List {\n\n int value;\n\n struct List *next;\n\n} List;\n\n\n\ntypedef struct Map {\n\n int key;\n\n List *values;\n\n struct Map *next;\n\n} Map;\n\n\n\nint compare_pairs(const void *a, const void *b) {\n\n Pair *pa = (Pair *)a;\n\n Pair *pb = (Pair *)b;\n\n return pa->second - pb->second;\n\n}\n\n\n\nvoid add_to_map(Map **map, int key, int value) {\n\n Map *cursor = *map;\n\n Map *prev = NULL;\n\n List *newList = NULL;\n\n \n\n while (cursor) {\n\n if (cursor->key == key) {\n\n newList = (List *)malloc(sizeof(List));\n\n newList->value = value;\n\n newList->next = cursor->values;\n\n cursor->values = newList;\n\n return;\n\n }\n\n prev = cursor;\n\n cursor = cursor->next;\n\n }\n\n\n\n Map *newMap = (Map *)malloc(sizeof(Map));\n\n newMap->key = key;\n\n newMap->values = (List *)malloc(sizeof(List));\n\n newMap->values->value = value;\n\n newMap->values->next = NULL;\n\n newMap->next = NULL;\n\n\n\n if (prev) {\n\n prev->next = newMap;\n\n } else {\n\n *map = newMap;\n\n }\n\n}\n\n\n\nvoid free_map(Map *map) {\n\n while (map != NULL) {\n\n List *list = map->values;\n\n while (list != NULL) {\n\n List *tempList = list;\n\n list = list->next;\n\n free(tempList);\n\n }\n\n Map *tempMap = map;\n\n map = map->next;\n\n free(tempMap);\n\n }\n\n}\n\n\n\n", + "func": "Map *func0(Pair *test_list, int size) {\n qsort(test_list, size, sizeof(Pair), compare_pairs);\n Map *result = NULL;\n for (int i = 0; i < size; ++i) {\n add_to_map(&result, test_list[i].second, test_list[i].first);\n }\n return result;\n}", + "test": "int main() {\n\n Pair pairs1[] = {{6, 5}, {2, 7}, {2, 5}, {8, 7}, {9, 8}, {3, 7}};\n\n Pair pairs2[] = {{7, 6}, {3, 8}, {3, 6}, {9, 8}, {10, 9}, {4, 8}};\n\n Pair pairs3[] = {{8, 7}, {4, 9}, {4, 7}, {10, 9}, {11, 10}, {5, 9}};\n\n Map *map_result;\n\n\n\n map_result = func0(pairs1, 6);\n\n assert(map_result && map_result->key == 5 && map_result->next->key == 7 && map_result->next->next->key == 8);\n\n free_map(map_result);\n\n\n\n map_result = func0(pairs2, 6);\n\n assert(map_result && map_result->key == 6 && map_result->next->key == 8 && map_result->next->next->key == 9);\n\n free_map(map_result);\n\n\n\n map_result = func0(pairs3, 6);\n\n assert(map_result && map_result->key == 7 && map_result->next->key == 9 && map_result->next->next->key == 10);\n\n free_map(map_result);\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmovslq %esi,%rsi\nmov $0x8,%edx\nlea -0x165(%rip),%rcx\npush %r14\npush %r13\npush %r12\npush %rbp\nmov %rsi,%rbp\npush %rbx\nmov %rdi,%rbx\nsub $0x18,%rsp\ncallq 10a0 \ntest %ebp,%ebp\njle 1620 \nlea -0x1(%rbp),%eax\nxor %r15d,%r15d\nlea 0x8(%rbx,%rax,8),%rax\nmov %rax,0x8(%rsp)\nnopl 0x0(%rax)\nmov (%rbx),%r12d\nmov 0x4(%rbx),%r13d\ntest %r15,%r15\nje 15e0 \nmov %r15,%rbp\njmp 155c \nnopl (%rax)\nmov 0x10(%rbp),%rax\ntest %rax,%rax\nje 15a0 \nmov %rax,%rbp\ncmp 0x0(%rbp),%r13d\njne 1550 \nmov $0x10,%edi\ncallq 10d0 \nmov 0x8(%rbp),%rdx\nmov %r12d,(%rax)\nmov %rdx,0x8(%rax)\nmov %rax,0x8(%rbp)\nadd $0x8,%rbx\ncmp 0x8(%rsp),%rbx\njne 1538 \nadd $0x18,%rsp\nmov %r15,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax,%rax,1)\nmov $0x18,%edi\ncallq 10d0 \nmov $0x10,%edi\nmov %r13d,(%rax)\nmov %rax,%r14\ncallq 10d0 \nmovq $0x0,0x10(%r14)\nmov %rax,0x8(%r14)\nmov %r12d,(%rax)\nmovq $0x0,0x8(%rax)\nmov %r14,0x10(%rbp)\njmp 157b \nnopw 0x0(%rax,%rax,1)\nmov $0x18,%edi\ncallq 10d0 \nmov $0x10,%edi\nmov %r13d,(%rax)\nmov %rax,%r15\ncallq 10d0 \nmovq $0x0,0x10(%r15)\nmov %rax,0x8(%r15)\nmov %r12d,(%rax)\nmovq $0x0,0x8(%rax)\njmpq 157b \nnopw %cs:0x0(%rax,%rax,1)\nxor %r15d,%r15d\njmpq 1586 \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\nlea rcx, compare_pairs; compar\nmov edx, 8; size\npush r14\npush r13\npush r12\nmovsxd r12, esi\npush rbp\nmov rsi, r12; nmemb\npush rbx\nmov rbx, rdi\nsub rsp, 18h\ncall _qsort\ntest r12d, r12d\njle loc_1624\nmov r14d, [rbx+4]\nmov edi, 18h; size\nmov ebp, [rbx]\nshl r12, 3\ncall _malloc\nmov edi, 10h; size\nmov [rax], r14d\nmov r13, rax\ncall _malloc\nmov qword ptr [r13+10h], 0\nmov [r13+8], rax\nmov [rax], ebp\nmov qword ptr [rax+8], 0\ncmp r12, 8\njz loc_1612\nlea rax, [rbx+r12]\nmov ebp, [rbx+0Ch]\nmov r12d, [rbx+8]\nlea r15, [rbx+8]\nmov [rsp+48h+var_40], rax\nnop dword ptr [rax]\nloc_1580:\nmov rbx, r13\njmp short loc_1594\nloc_1588:\nmov rax, [rbx+10h]\ntest rax, rax\njz short loc_15D0\nmov rbx, rax\nloc_1594:\ncmp [rbx], ebp\njnz short loc_1588\nmov edi, 10h; size\nadd r15, 8\ncall _malloc\nmov rdx, [rbx+8]\nmov [rax], r12d\nmov [rax+8], rdx\nmov [rbx+8], rax\nmov rax, [rsp+48h+var_40]\ncmp r15, rax\njz short loc_1612\nloc_15BF:\nmov r12d, [r15]\nmov ebp, [r15+4]\njmp short loc_1580\nloc_15D0:\nmov edi, 18h; size\nadd r15, 8\ncall _malloc\nmov edi, 10h; size\nmov [rax], ebp\nmov r14, rax\ncall _malloc\nmov qword ptr [r14+10h], 0\nmov [r14+8], rax\nmov [rax], r12d\nmov qword ptr [rax+8], 0\nmov rax, [rsp+48h+var_40]\nmov [rbx+10h], r14\ncmp r15, rax\njnz short loc_15BF\nloc_1612:\nadd rsp, 18h\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1624:\nxor r13d, r13d\njmp short loc_1612", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2)\n{\n int v2; // r14d\n int v3; // ebp\n __int64 v4; // r12\n _DWORD *v5; // rax\n _DWORD *v6; // r13\n _QWORD *v7; // rax\n int *v8; // rax\n int v9; // ebp\n int v10; // r12d\n int *v11; // r15\n _DWORD *i; // rbx\n _QWORD *v13; // rax\n __int64 v14; // rdx\n _DWORD *v15; // rax\n _DWORD *v16; // r14\n _QWORD *v17; // rax\n int *v19; // [rsp+8h] [rbp-40h]\n\n qsort(a1, a2, 8uLL, compare_pairs);\n if ( a2 <= 0 )\n return 0LL;\n v2 = a1[1];\n v3 = *a1;\n v4 = 2LL * a2;\n v5 = malloc(0x18uLL);\n *v5 = v2;\n v6 = v5;\n v7 = malloc(0x10uLL);\n *((_QWORD *)v6 + 2) = 0LL;\n *((_QWORD *)v6 + 1) = v7;\n *(_DWORD *)v7 = v3;\n v7[1] = 0LL;\n if ( v4 != 2 )\n {\n v8 = &a1[v4];\n v9 = a1[3];\n v10 = a1[2];\n v11 = a1 + 2;\n v19 = v8;\nLABEL_4:\n for ( i = v6; ; i = (_DWORD *)*((_QWORD *)i + 2) )\n {\n if ( *i == v9 )\n {\n v11 += 2;\n v13 = malloc(0x10uLL);\n v14 = *((_QWORD *)i + 1);\n *(_DWORD *)v13 = v10;\n v13[1] = v14;\n *((_QWORD *)i + 1) = v13;\n if ( v11 == v19 )\n return v6;\nLABEL_9:\n v10 = *v11;\n v9 = v11[1];\n goto LABEL_4;\n }\n if ( !*((_QWORD *)i + 2) )\n break;\n }\n v11 += 2;\n v15 = malloc(0x18uLL);\n *v15 = v9;\n v16 = v15;\n v17 = malloc(0x10uLL);\n *((_QWORD *)v16 + 2) = 0LL;\n *((_QWORD *)v16 + 1) = v17;\n *(_DWORD *)v17 = v10;\n v17[1] = 0LL;\n *((_QWORD *)i + 2) = v16;\n if ( v11 != v19 )\n goto LABEL_9;\n }\n return v6;\n}", + "ida_strip_asm": "sub_14F0:\nendbr64\npush r15\nlea rcx, compar; compar\nmov edx, 8; size\npush r14\npush r13\npush r12\nmovsxd r12, esi\npush rbp\nmov rsi, r12; nmemb\npush rbx\nmov rbx, rdi\nsub rsp, 18h\ncall _qsort\ntest r12d, r12d\njle loc_1624\nmov r14d, [rbx+4]\nmov edi, 18h; size\nmov ebp, [rbx]\nshl r12, 3\ncall _malloc\nmov edi, 10h; size\nmov [rax], r14d\nmov r13, rax\ncall _malloc\nmov qword ptr [r13+10h], 0\nmov [r13+8], rax\nmov [rax], ebp\nmov qword ptr [rax+8], 0\ncmp r12, 8\njz loc_1612\nlea rax, [rbx+r12]\nmov ebp, [rbx+0Ch]\nmov r12d, [rbx+8]\nlea r15, [rbx+8]\nmov [rsp+48h+var_40], rax\nnop dword ptr [rax]\nloc_1580:\nmov rbx, r13\njmp short loc_1594\nloc_1588:\nmov rax, [rbx+10h]\ntest rax, rax\njz short loc_15D0\nmov rbx, rax\nloc_1594:\ncmp [rbx], ebp\njnz short loc_1588\nmov edi, 10h; size\nadd r15, 8\ncall _malloc\nmov rdx, [rbx+8]\nmov [rax], r12d\nmov [rax+8], rdx\nmov [rbx+8], rax\nmov rax, [rsp+48h+var_40]\ncmp r15, rax\njz short loc_1612\nloc_15BF:\nmov r12d, [r15]\nmov ebp, [r15+4]\njmp short loc_1580\nloc_15D0:\nmov edi, 18h; size\nadd r15, 8\ncall _malloc\nmov edi, 10h; size\nmov [rax], ebp\nmov r14, rax\ncall _malloc\nmov qword ptr [r14+10h], 0\nmov [r14+8], rax\nmov [rax], r12d\nmov qword ptr [rax+8], 0\nmov rax, [rsp+48h+var_40]\nmov [rbx+10h], r14\ncmp r15, rax\njnz short loc_15BF\nloc_1612:\nadd rsp, 18h\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1624:\nxor r13d, r13d\njmp short loc_1612", + "ida_strip_pseudo": "_DWORD *__fastcall sub_14F0(int *a1, int a2)\n{\n int v2; // r14d\n int v3; // ebp\n __int64 v4; // r12\n _DWORD *v5; // rax\n _DWORD *v6; // r13\n _QWORD *v7; // rax\n int *v8; // rax\n int v9; // ebp\n int v10; // r12d\n int *v11; // r15\n _DWORD *i; // rbx\n _QWORD *v13; // rax\n __int64 v14; // rdx\n _DWORD *v15; // rax\n _DWORD *v16; // r14\n _QWORD *v17; // rax\n int *v19; // [rsp+8h] [rbp-40h]\n\n qsort(a1, a2, 8uLL, compar);\n if ( a2 <= 0 )\n return 0LL;\n v2 = a1[1];\n v3 = *a1;\n v4 = 2LL * a2;\n v5 = malloc(0x18uLL);\n *v5 = v2;\n v6 = v5;\n v7 = malloc(0x10uLL);\n *((_QWORD *)v6 + 2) = 0LL;\n *((_QWORD *)v6 + 1) = v7;\n *(_DWORD *)v7 = v3;\n v7[1] = 0LL;\n if ( v4 != 2 )\n {\n v8 = &a1[v4];\n v9 = a1[3];\n v10 = a1[2];\n v11 = a1 + 2;\n v19 = v8;\nLABEL_4:\n for ( i = v6; ; i = (_DWORD *)*((_QWORD *)i + 2) )\n {\n if ( *i == v9 )\n {\n v11 += 2;\n v13 = malloc(0x10uLL);\n v14 = *((_QWORD *)i + 1);\n *(_DWORD *)v13 = v10;\n v13[1] = v14;\n *((_QWORD *)i + 1) = v13;\n if ( v11 == v19 )\n return v6;\nLABEL_9:\n v10 = *v11;\n v9 = v11[1];\n goto LABEL_4;\n }\n if ( !*((_QWORD *)i + 2) )\n break;\n }\n v11 += 2;\n v15 = malloc(0x18uLL);\n *v15 = v9;\n v16 = v15;\n v17 = malloc(0x10uLL);\n *((_QWORD *)v16 + 2) = 0LL;\n *((_QWORD *)v16 + 1) = v17;\n *(_DWORD *)v17 = v10;\n v17[1] = 0LL;\n *((_QWORD *)i + 2) = v16;\n if ( v11 != v19 )\n goto LABEL_9;\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_14F0(int *a1, int a2) {\n int v2;\n int v3;\n long long v4;\n uint32_t *v5;\n uint32_t *v6;\n uint64_t *v7;\n int *v8;\n int v9;\n int v10;\n int *v11;\n uint32_t *i;\n uint64_t *v13;\n long long v14;\n uint32_t *v15;\n uint32_t *v16;\n uint64_t *v17;\n int *v19;\n qsort(a1, a2, 8uLL, compar);\n if (a2 <= 0) return 0LL;\n v2 = a1[1];\n v3 = *a1;\n v4 = 2LL * a2;\n v5 = malloc(24uLL);\n *v5 = v2;\n v6 = v5;\n v7 = malloc(16uLL);\n *((uint64_t *)v6 + 2) = 0LL;\n *((uint64_t *)v6 + 1) = v7;\n *(uint32_t *)v7 = v3;\n v7[1] = 0LL;\n if (v4 != 2) {\n v8 = &a1[v4];\n v9 = a1[3];\n v10 = a1[2];\n v11 = a1 + 2;\n v19 = v8;\n LABEL_4:\n for (i = v6;; i = (uint32_t *)*((uint64_t *)i + 2)) {\n if (*i == v9) {\n v11 += 2;\n v13 = malloc(16uLL);\n v14 = *((uint64_t *)i + 1);\n *(uint32_t *)v13 = v10;\n v13[1] = v14;\n *((uint64_t *)i + 1) = v13;\n if (v11 == v19) return v6;\n LABEL_9:\n v10 = *v11;\n v9 = v11[1];\n goto LABEL_4;\n }\n if (!*((uint64_t *)i + 2)) break;\n }\n v11 += 2;\n v15 = malloc(24uLL);\n *v15 = v9;\n v16 = v15;\n v17 = malloc(16uLL);\n *((uint64_t *)v16 + 2) = 0LL;\n *((uint64_t *)v16 + 1) = v17;\n *(uint32_t *)v17 = v10;\n v17[1] = 0LL;\n *((uint64_t *)i + 2) = v16;\n if (v11 != v19) goto LABEL_9;\n }\n return v6;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2) {\n int v2;\n int v3;\n long long v4;\n uint32_t *v5;\n uint32_t *v6;\n uint64_t *v7;\n int *v8;\n int v9;\n int v10;\n int *v11;\n uint32_t *i;\n uint64_t *v13;\n long long v14;\n uint32_t *v15;\n uint32_t *v16;\n uint64_t *v17;\n int *v19;\n qsort(a1, a2, 8uLL, compare_pairs);\n if (a2 <= 0) return 0LL;\n v2 = a1[1];\n v3 = *a1;\n v4 = 2LL * a2;\n v5 = malloc(24uLL);\n *v5 = v2;\n v6 = v5;\n v7 = malloc(16uLL);\n *((uint64_t *)v6 + 2) = 0LL;\n *((uint64_t *)v6 + 1) = v7;\n *(uint32_t *)v7 = v3;\n v7[1] = 0LL;\n if (v4 != 2) {\n v8 = &a1[v4];\n v9 = a1[3];\n v10 = a1[2];\n v11 = a1 + 2;\n v19 = v8;\n LABEL_4:\n for (i = v6;; i = (uint32_t *)*((uint64_t *)i + 2)) {\n if (*i == v9) {\n v11 += 2;\n v13 = malloc(16uLL);\n v14 = *((uint64_t *)i + 1);\n *(uint32_t *)v13 = v10;\n v13[1] = v14;\n *((uint64_t *)i + 1) = v13;\n if (v11 == v19) return v6;\n LABEL_9:\n v10 = *v11;\n v9 = v11[1];\n goto LABEL_4;\n }\n if (!*((uint64_t *)i + 2)) break;\n }\n v11 += 2;\n v15 = malloc(24uLL);\n *v15 = v9;\n v16 = v15;\n v17 = malloc(16uLL);\n *((uint64_t *)v16 + 2) = 0LL;\n *((uint64_t *)v16 + 1) = v17;\n *(uint32_t *)v17 = v10;\n v17[1] = 0LL;\n *((uint64_t *)i + 2) = v16;\n if (v11 != v19) goto LABEL_9;\n }\n return v6;\n}" + }, + { + "index": 692, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int N) {\n if (N >= 10) {\n return 0;\n }\n int fac = 1;\n for (int i = 1; i <= N; i++) {\n fac = (fac * i) % 100;\n }\n return fac;\n}", + "test": "int main() {\n\n assert(func0(7) == 40);\n\n assert(func0(5) == 20);\n\n assert(func0(2) == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\ncmpl $0x9,-0x14(%rbp)\njle 1161 \nmov $0x0,%eax\njmp 11ad \nmovl $0x1,-0x8(%rbp)\nmovl $0x1,-0x4(%rbp)\njmp 11a2 \nmov -0x8(%rbp),%eax\nimul -0x4(%rbp),%eax\nmovslq %eax,%rdx\nimul $0x51eb851f,%rdx,%rdx\nshr $0x20,%rdx\nmov %edx,%ecx\nsar $0x5,%ecx\ncltd\nsub %edx,%ecx\nmov %ecx,%edx\nmov %edx,-0x8(%rbp)\nmov -0x8(%rbp),%edx\nimul $0x64,%edx,%edx\nsub %edx,%eax\nmov %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x14(%rbp),%eax\njle 1171 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\ncmp [rbp+var_14], 9\njle short loc_1161\nmov eax, 0\njmp short loc_11AD\nloc_1161:\nmov [rbp+var_8], 1\nmov [rbp+var_4], 1\njmp short loc_11A2\nloc_1171:\nmov eax, [rbp+var_8]\nimul eax, [rbp+var_4]\nmovsxd rdx, eax\nimul rdx, 51EB851Fh\nshr rdx, 20h\nsar edx, 5\nmov ecx, eax\nsar ecx, 1Fh\nsub edx, ecx\nmov [rbp+var_8], edx\nmov edx, [rbp+var_8]\nimul edx, 64h ; 'd'\nsub eax, edx\nmov [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_11A2:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_14]\njle short loc_1171\nmov eax, [rbp+var_8]\nloc_11AD:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v2; // [rsp+Ch] [rbp-8h]\n int i; // [rsp+10h] [rbp-4h]\n\n if ( a1 > 9 )\n return 0LL;\n v2 = 1;\n for ( i = 1; i <= a1; ++i )\n v2 = (int)(i * v2) % 100;\n return v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\ncmp [rbp+var_14], 9\njle short loc_1161\nmov eax, 0\njmp short loc_11AD\nloc_1161:\nmov [rbp+var_8], 1\nmov [rbp+var_4], 1\njmp short loc_11A2\nloc_1171:\nmov eax, [rbp+var_8]\nimul eax, [rbp+var_4]\nmovsxd rdx, eax\nimul rdx, 51EB851Fh\nshr rdx, 20h\nsar edx, 5\nmov ecx, eax\nsar ecx, 1Fh\nsub edx, ecx\nmov [rbp+var_8], edx\nmov edx, [rbp+var_8]\nimul edx, 64h ; 'd'\nsub eax, edx\nmov [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_11A2:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_14]\njle short loc_1171\nmov eax, [rbp+var_8]\nloc_11AD:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n unsigned int v2; // [rsp+Ch] [rbp-8h]\n int i; // [rsp+10h] [rbp-4h]\n\n if ( a1 > 9 )\n return 0LL;\n v2 = 1;\n for ( i = 1; i <= a1; ++i )\n v2 = (int)(i * v2) % 100;\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n unsigned int v2;\n int i;\n if (a1 > 9) return 0LL;\n v2 = 1;\n for (i = 1; i <= a1; ++i) v2 = (int)(i * v2) % 100;\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v2;\n int i;\n if (a1 > 9) return 0LL;\n v2 = 1;\n for (i = 1; i <= a1; ++i) v2 = (int)(i * v2) % 100;\n return v2;\n}" + }, + { + "index": 692, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int N) {\n if (N >= 10) {\n return 0;\n }\n int fac = 1;\n for (int i = 1; i <= N; i++) {\n fac = (fac * i) % 100;\n }\n return fac;\n}", + "test": "int main() {\n\n assert(func0(7) == 40);\n\n assert(func0(5) == 20);\n\n assert(func0(2) == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x0,%eax\ncmp $0x9,%edi\njg 1195 \ntest %edi,%edi\njle 1190 \nadd $0x1,%edi\nmov $0x1,%edx\nmov $0x1,%eax\nimul %edx,%eax\nmov %eax,%ecx\ncltq\nimul $0x51eb851f,%rax,%rax\nsar $0x25,%rax\nmov %ecx,%esi\nsar $0x1f,%esi\nsub %esi,%eax\nimul $0x64,%eax,%eax\nsub %eax,%ecx\nmov %ecx,%eax\nadd $0x1,%edx\ncmp %edi,%edx\njne 1168 \nretq\nmov $0x1,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov eax, 0\ncmp edi, 9\njg short locret_1195\ntest edi, edi\njle short loc_1190\nadd edi, 1\nmov edx, 1\nmov eax, 1\nloc_1168:\nimul eax, edx\nmov ecx, eax\ncdqe\nimul rax, 51EB851Fh\nsar rax, 25h\nmov esi, ecx\nsar esi, 1Fh\nsub eax, esi\nimul esi, eax, 64h ; 'd'\nmov eax, ecx\nsub eax, esi\nadd edx, 1\ncmp edx, edi\njnz short loc_1168\nretn\nloc_1190:\nmov eax, 1\nlocret_1195:\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n __int64 result; // rax\n int v2; // edi\n int v3; // edx\n\n result = 0LL;\n if ( a1 <= 9 )\n {\n if ( a1 <= 0 )\n {\n return 1LL;\n }\n else\n {\n v2 = a1 + 1;\n v3 = 1;\n LODWORD(result) = 1;\n do\n {\n result = (unsigned int)(v3 * (int)result % 100);\n ++v3;\n }\n while ( v3 != v2 );\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmov eax, 0\ncmp edi, 9\njg short locret_1195\ntest edi, edi\njle short loc_1190\nadd edi, 1\nmov edx, 1\nmov eax, 1\nloc_1168:\nimul eax, edx\nmov ecx, eax\ncdqe\nimul rax, 51EB851Fh\nsar rax, 25h\nmov esi, ecx\nsar esi, 1Fh\nsub eax, esi\nimul esi, eax, 64h ; 'd'\nmov eax, ecx\nsub eax, esi\nadd edx, 1\ncmp edx, edi\njnz short loc_1168\nretn\nloc_1190:\nmov eax, 1\nlocret_1195:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n __int64 result; // rax\n int v2; // edi\n int v3; // edx\n\n result = 0LL;\n if ( a1 <= 9 )\n {\n if ( a1 <= 0 )\n {\n return 1LL;\n }\n else\n {\n v2 = a1 + 1;\n v3 = 1;\n LODWORD(result) = 1;\n do\n {\n result = (unsigned int)(v3 * (int)result % 100);\n ++v3;\n }\n while ( v3 != v2 );\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n long long result;\n int v2;\n int v3;\n result = 0LL;\n if (a1 <= 9) {\n if (a1 <= 0) {\n return 1LL;\n } else {\n v2 = a1 + 1;\n v3 = 1;\n LODWORD(result) = 1;\n do {\n result = (unsigned int)(v3 * (int)result % 100);\n ++v3;\n } while (v3 != v2);\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n long long result;\n int v2;\n int v3;\n result = 0LL;\n if (a1 <= 9) {\n if (a1 <= 0) {\n return 1LL;\n } else {\n v2 = a1 + 1;\n v3 = 1;\n LODWORD(result) = 1;\n do {\n result = (unsigned int)(v3 * (int)result % 100);\n ++v3;\n } while (v3 != v2);\n }\n }\n return result;\n}" + }, + { + "index": 693, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text1) {\n if (text1 == NULL) {\n return NULL;\n }\n size_t len = strlen(text1);\n char* result = malloc(len + 1);\n if (result == NULL) {\n return NULL;\n }\n size_t i = 0, j = 0;\n int space_found = 0;\n while (text1[i] != '\\0') {\n if (text1[i] != ' ') {\n result[j++] = text1[i];\n space_found = 0;\n } else {\n if (!space_found) {\n result[j++] = ' ';\n space_found = 1;\n }\n }\n i++;\n }\n result[j] = '\\0';\n return result;\n}", + "test": "int main() {\n\n char* result;\n\n\n\n result = func0(\"Google Assistant\");\n\n assert(result != NULL);\n\n assert(strcmp(result, \"Google Assistant\") == 0);\n\n free(result);\n\n\n\n result = func0(\"Quad Core\");\n\n assert(result != NULL);\n\n assert(strcmp(result, \"Quad Core\") == 0);\n\n free(result);\n\n\n\n result = func0(\"ChromeCast Built-in\");\n\n assert(result != NULL);\n\n assert(strcmp(result, \"ChromeCast Built-in\") == 0);\n\n free(result);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x40,%rsp\nmov %rdi,-0x38(%rbp)\ncmpq $0x0,-0x38(%rbp)\njne 11ea \nmov $0x0,%eax\njmpq 12c3 \nmov -0x38(%rbp),%rax\nmov %rax,%rdi\ncallq 10a0 \nmov %rax,-0x10(%rbp)\nmov -0x10(%rbp),%rax\nadd $0x1,%rax\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,-0x8(%rbp)\ncmpq $0x0,-0x8(%rbp)\njne 121f \nmov $0x0,%eax\njmpq 12c3 \nmovq $0x0,-0x20(%rbp)\nmovq $0x0,-0x18(%rbp)\nmovl $0x0,-0x24(%rbp)\njmp 129f \nmov -0x38(%rbp),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x20,%al\nje 1277 \nmov -0x38(%rbp),%rdx\nmov -0x20(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x18(%rbp),%rax\nlea 0x1(%rax),%rdx\nmov %rdx,-0x18(%rbp)\nmov -0x8(%rbp),%rdx\nadd %rax,%rdx\nmovzbl (%rcx),%eax\nmov %al,(%rdx)\nmovl $0x0,-0x24(%rbp)\njmp 129a \ncmpl $0x0,-0x24(%rbp)\njne 129a \nmov -0x18(%rbp),%rax\nlea 0x1(%rax),%rdx\nmov %rdx,-0x18(%rbp)\nmov -0x8(%rbp),%rdx\nadd %rdx,%rax\nmovb $0x20,(%rax)\nmovl $0x1,-0x24(%rbp)\naddq $0x1,-0x20(%rbp)\nmov -0x38(%rbp),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 1238 \nmov -0x8(%rbp),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovb $0x0,(%rax)\nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+s], rdi\ncmp [rbp+s], 0\njnz short loc_11EA\nmov eax, 0\njmp locret_12C3\nloc_11EA:\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_10], rax\nmov rax, [rbp+var_10]\nadd rax, 1\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\ncmp [rbp+var_8], 0\njnz short loc_121F\nmov eax, 0\njmp locret_12C3\nloc_121F:\nmov [rbp+var_20], 0\nmov [rbp+var_18], 0\nmov [rbp+var_24], 0\njmp short loc_129F\nloc_1238:\nmov rdx, [rbp+s]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njz short loc_1277\nmov rdx, [rbp+s]\nmov rax, [rbp+var_20]\nlea rcx, [rdx+rax]\nmov rax, [rbp+var_18]\nlea rdx, [rax+1]\nmov [rbp+var_18], rdx\nmov rdx, [rbp+var_8]\nadd rdx, rax\nmovzx eax, byte ptr [rcx]\nmov [rdx], al\nmov [rbp+var_24], 0\njmp short loc_129A\nloc_1277:\ncmp [rbp+var_24], 0\njnz short loc_129A\nmov rax, [rbp+var_18]\nlea rdx, [rax+1]\nmov [rbp+var_18], rdx\nmov rdx, [rbp+var_8]\nadd rax, rdx\nmov byte ptr [rax], 20h ; ' '\nmov [rbp+var_24], 1\nloc_129A:\nadd [rbp+var_20], 1\nloc_129F:\nmov rdx, [rbp+s]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1238\nmov rdx, [rbp+var_8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+var_8]\nlocret_12C3:\nleave\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1)\n{\n __int64 v2; // rax\n __int64 v3; // rax\n int v4; // [rsp+1Ch] [rbp-24h]\n __int64 v5; // [rsp+20h] [rbp-20h]\n __int64 v6; // [rsp+28h] [rbp-18h]\n size_t v7; // [rsp+30h] [rbp-10h]\n _BYTE *v8; // [rsp+38h] [rbp-8h]\n\n if ( !a1 )\n return 0LL;\n v7 = strlen(a1);\n v8 = malloc(v7 + 1);\n if ( !v8 )\n return 0LL;\n v5 = 0LL;\n v6 = 0LL;\n v4 = 0;\n while ( a1[v5] )\n {\n if ( a1[v5] == 32 )\n {\n if ( !v4 )\n {\n v3 = v6++;\n v8[v3] = 32;\n v4 = 1;\n }\n }\n else\n {\n v2 = v6++;\n v8[v2] = a1[v5];\n v4 = 0;\n }\n ++v5;\n }\n v8[v6] = 0;\n return v8;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+s], rdi\ncmp [rbp+s], 0\njnz short loc_11EA\nmov eax, 0\njmp locret_12C3\nloc_11EA:\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_10], rax\nmov rax, [rbp+var_10]\nadd rax, 1\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\ncmp [rbp+var_8], 0\njnz short loc_121F\nmov eax, 0\njmp locret_12C3\nloc_121F:\nmov [rbp+var_20], 0\nmov [rbp+var_18], 0\nmov [rbp+var_24], 0\njmp short loc_129F\nloc_1238:\nmov rdx, [rbp+s]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njz short loc_1277\nmov rdx, [rbp+s]\nmov rax, [rbp+var_20]\nlea rcx, [rdx+rax]\nmov rax, [rbp+var_18]\nlea rdx, [rax+1]\nmov [rbp+var_18], rdx\nmov rdx, [rbp+var_8]\nadd rdx, rax\nmovzx eax, byte ptr [rcx]\nmov [rdx], al\nmov [rbp+var_24], 0\njmp short loc_129A\nloc_1277:\ncmp [rbp+var_24], 0\njnz short loc_129A\nmov rax, [rbp+var_18]\nlea rdx, [rax+1]\nmov [rbp+var_18], rdx\nmov rdx, [rbp+var_8]\nadd rax, rdx\nmov byte ptr [rax], 20h ; ' '\nmov [rbp+var_24], 1\nloc_129A:\nadd [rbp+var_20], 1\nloc_129F:\nmov rdx, [rbp+s]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1238\nmov rdx, [rbp+var_8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+var_8]\nlocret_12C3:\nleave\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_11C9(const char *a1)\n{\n __int64 v2; // rax\n __int64 v3; // rax\n int v4; // [rsp+1Ch] [rbp-24h]\n __int64 v5; // [rsp+20h] [rbp-20h]\n __int64 v6; // [rsp+28h] [rbp-18h]\n size_t v7; // [rsp+30h] [rbp-10h]\n _BYTE *v8; // [rsp+38h] [rbp-8h]\n\n if ( !a1 )\n return 0LL;\n v7 = strlen(a1);\n v8 = malloc(v7 + 1);\n if ( !v8 )\n return 0LL;\n v5 = 0LL;\n v6 = 0LL;\n v4 = 0;\n while ( a1[v5] )\n {\n if ( a1[v5] == 32 )\n {\n if ( !v4 )\n {\n v3 = v6++;\n v8[v3] = 32;\n v4 = 1;\n }\n }\n else\n {\n v2 = v6++;\n v8[v2] = a1[v5];\n v4 = 0;\n }\n ++v5;\n }\n v8[v6] = 0;\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_11C9(const char *a1) {\n long long v2;\n long long v3;\n int v4;\n long long v5;\n long long v6;\n unsigned int v7;\n uint8_t *v8;\n if (!a1) return 0LL;\n v7 = strlen(a1);\n v8 = malloc(v7 + 1);\n if (!v8) return 0LL;\n v5 = 0LL;\n v6 = 0LL;\n v4 = 0;\n while (a1[v5]) {\n if (a1[v5] == 32) {\n if (!v4) {\n v3 = v6++;\n v8[v3] = 32;\n v4 = 1;\n }\n } else {\n v2 = v6++;\n v8[v2] = a1[v5];\n v4 = 0;\n }\n ++v5;\n }\n v8[v6] = 0;\n return v8;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1) {\n long long v2;\n long long v3;\n int v4;\n long long v5;\n long long v6;\n unsigned int v7;\n uint8_t *v8;\n if (!a1) return 0LL;\n v7 = strlen(a1);\n v8 = malloc(v7 + 1);\n if (!v8) return 0LL;\n v5 = 0LL;\n v6 = 0LL;\n v4 = 0;\n while (a1[v5]) {\n if (a1[v5] == 32) {\n if (!v4) {\n v3 = v6++;\n v8[v3] = 32;\n v4 = 1;\n }\n } else {\n v2 = v6++;\n v8[v2] = a1[v5];\n v4 = 0;\n }\n ++v5;\n }\n v8[v6] = 0;\n return v8;\n}" + }, + { + "index": 693, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text1) {\n if (text1 == NULL) {\n return NULL;\n }\n size_t len = strlen(text1);\n char* result = malloc(len + 1);\n if (result == NULL) {\n return NULL;\n }\n size_t i = 0, j = 0;\n int space_found = 0;\n while (text1[i] != '\\0') {\n if (text1[i] != ' ') {\n result[j++] = text1[i];\n space_found = 0;\n } else {\n if (!space_found) {\n result[j++] = ' ';\n space_found = 1;\n }\n }\n i++;\n }\n result[j] = '\\0';\n return result;\n}", + "test": "int main() {\n\n char* result;\n\n\n\n result = func0(\"Google Assistant\");\n\n assert(result != NULL);\n\n assert(strcmp(result, \"Google Assistant\") == 0);\n\n free(result);\n\n\n\n result = func0(\"Quad Core\");\n\n assert(result != NULL);\n\n assert(strcmp(result, \"Quad Core\") == 0);\n\n free(result);\n\n\n\n result = func0(\"ChromeCast Built-in\");\n\n assert(result != NULL);\n\n assert(strcmp(result, \"ChromeCast Built-in\") == 0);\n\n free(result);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\ntest %rdi,%rdi\nje 120e \nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nmov %rcx,%rdi\ncallq 1090 \ntest %rax,%rax\nje 120c \nmovzbl (%rbx),%edx\ntest %dl,%dl\nje 1203 \nlea 0x1(%rbx),%rdi\nmov $0x0,%esi\nmov $0x0,%ecx\nmov $0x1,%r9d\nmov $0x0,%r8d\njmp 11ed \nmov %dl,(%rax,%rcx,1)\nlea 0x1(%rcx),%rcx\nmov %r8d,%esi\nadd $0x1,%rdi\nmovzbl -0x1(%rdi),%edx\ntest %dl,%dl\nje 1208 \ncmp $0x20,%dl\njne 11d7 \ntest %esi,%esi\njne 11e1 \nmovb $0x20,(%rax,%rcx,1)\nlea 0x1(%rcx),%rcx\nmov %r9d,%esi\njmp 11e1 \nmov $0x0,%ecx\nmovb $0x0,(%rax,%rcx,1)\npop %rbx\nretq\nmov %rdi,%rax\njmp 120c \n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ntest rdi, rdi\njz short loc_1243\ncall _strlen\nlea rdi, [rax+1]; size\ncall _malloc\ntest rax, rax\njz short loc_1241\nmovzx edx, byte ptr [rbx]\ntest dl, dl\njz short loc_1238\nlea rdi, [rbx+1]\nmov esi, 0\nmov ecx, 0\nmov r9d, 1\nmov r8d, 0\njmp short loc_1227\nloc_120C:\ntest esi, esi\njnz short loc_121B\nmov byte ptr [rax+rcx], 20h ; ' '\nlea rcx, [rcx+1]\nmov esi, r9d\nloc_121B:\nadd rdi, 1\nmovzx edx, byte ptr [rdi-1]\ntest dl, dl\njz short loc_123D\nloc_1227:\ncmp dl, 20h ; ' '\njz short loc_120C\nmov [rax+rcx], dl\nlea rcx, [rcx+1]\nmov esi, r8d\njmp short loc_121B\nloc_1238:\nmov ecx, 0\nloc_123D:\nmov byte ptr [rax+rcx], 0\nloc_1241:\npop rbx\nretn\nloc_1243:\nmov rax, rdi\njmp short loc_1241", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1)\n{\n size_t v1; // rax\n _BYTE *result; // rax\n char v3; // dl\n char *v4; // rdi\n int v5; // esi\n __int64 v6; // rcx\n\n if ( !a1 )\n return 0LL;\n v1 = strlen(a1);\n result = malloc(v1 + 1);\n if ( result )\n {\n v3 = *a1;\n if ( *a1 )\n {\n v4 = (char *)(a1 + 1);\n v5 = 0;\n v6 = 0LL;\n do\n {\n if ( v3 == 32 )\n {\n if ( !v5 )\n {\n result[v6++] = 32;\n v5 = 1;\n }\n }\n else\n {\n result[v6++] = v3;\n v5 = 0;\n }\n v3 = *v4++;\n }\n while ( v3 );\n }\n else\n {\n v6 = 0LL;\n }\n result[v6] = 0;\n }\n return result;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbx\nmov rbx, rdi\ntest rdi, rdi\njz short loc_1243\ncall _strlen\nlea rdi, [rax+1]; size\ncall _malloc\ntest rax, rax\njz short loc_1241\nmovzx edx, byte ptr [rbx]\ntest dl, dl\njz short loc_1238\nlea rdi, [rbx+1]\nmov esi, 0\nmov ecx, 0\nmov r9d, 1\nmov r8d, 0\njmp short loc_1227\nloc_120C:\ntest esi, esi\njnz short loc_121B\nmov byte ptr [rax+rcx], 20h ; ' '\nlea rcx, [rcx+1]\nmov esi, r9d\nloc_121B:\nadd rdi, 1\nmovzx edx, byte ptr [rdi-1]\ntest dl, dl\njz short loc_123D\nloc_1227:\ncmp dl, 20h ; ' '\njz short loc_120C\nmov [rax+rcx], dl\nlea rcx, [rcx+1]\nmov esi, r8d\njmp short loc_121B\nloc_1238:\nmov ecx, 0\nloc_123D:\nmov byte ptr [rax+rcx], 0\nloc_1241:\npop rbx\nretn\nloc_1243:\nmov rax, rdi\njmp short loc_1241", + "ida_strip_pseudo": "_BYTE *__fastcall sub_11C9(const char *a1)\n{\n size_t v1; // rax\n _BYTE *result; // rax\n char v3; // dl\n char *v4; // rdi\n int v5; // esi\n __int64 v6; // rcx\n\n if ( !a1 )\n return 0LL;\n v1 = strlen(a1);\n result = malloc(v1 + 1);\n if ( result )\n {\n v3 = *a1;\n if ( *a1 )\n {\n v4 = (char *)(a1 + 1);\n v5 = 0;\n v6 = 0LL;\n do\n {\n if ( v3 == 32 )\n {\n if ( !v5 )\n {\n result[v6++] = 32;\n v5 = 1;\n }\n }\n else\n {\n result[v6++] = v3;\n v5 = 0;\n }\n v3 = *v4++;\n }\n while ( v3 );\n }\n else\n {\n v6 = 0LL;\n }\n result[v6] = 0;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_11C9(const char *a1) {\n unsigned int v1;\n uint8_t *result;\n char v3;\n char *v4;\n int v5;\n long long v6;\n if (!a1) return 0LL;\n v1 = strlen(a1);\n result = malloc(v1 + 1);\n if (result) {\n v3 = *a1;\n if (*a1) {\n v4 = (char *)(a1 + 1);\n v5 = 0;\n v6 = 0LL;\n do {\n if (v3 == 32) {\n if (!v5) {\n result[v6++] = 32;\n v5 = 1;\n }\n } else {\n result[v6++] = v3;\n v5 = 0;\n }\n v3 = *v4++;\n } while (v3);\n } else {\n v6 = 0LL;\n }\n result[v6] = 0;\n }\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1) {\n unsigned int v1;\n uint8_t *result;\n char v3;\n char *v4;\n int v5;\n long long v6;\n if (!a1) return 0LL;\n v1 = strlen(a1);\n result = malloc(v1 + 1);\n if (result) {\n v3 = *a1;\n if (*a1) {\n v4 = (char *)(a1 + 1);\n v5 = 0;\n v6 = 0LL;\n do {\n if (v3 == 32) {\n if (!v5) {\n result[v6++] = 32;\n v5 = 1;\n }\n } else {\n result[v6++] = v3;\n v5 = 0;\n }\n v3 = *v4++;\n } while (v3);\n } else {\n v6 = 0LL;\n }\n result[v6] = 0;\n }\n return result;\n}" + }, + { + "index": 693, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text1) {\n if (text1 == NULL) {\n return NULL;\n }\n size_t len = strlen(text1);\n char* result = malloc(len + 1);\n if (result == NULL) {\n return NULL;\n }\n size_t i = 0, j = 0;\n int space_found = 0;\n while (text1[i] != '\\0') {\n if (text1[i] != ' ') {\n result[j++] = text1[i];\n space_found = 0;\n } else {\n if (!space_found) {\n result[j++] = ' ';\n space_found = 1;\n }\n }\n i++;\n }\n result[j] = '\\0';\n return result;\n}", + "test": "int main() {\n\n char* result;\n\n\n\n result = func0(\"Google Assistant\");\n\n assert(result != NULL);\n\n assert(strcmp(result, \"Google Assistant\") == 0);\n\n free(result);\n\n\n\n result = func0(\"Quad Core\");\n\n assert(result != NULL);\n\n assert(strcmp(result, \"Quad Core\") == 0);\n\n free(result);\n\n\n\n result = func0(\"ChromeCast Built-in\");\n\n assert(result != NULL);\n\n assert(strcmp(result, \"ChromeCast Built-in\") == 0);\n\n free(result);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %rdi,%rdi\nje 13d0 \npush %rbx\nmov %rdi,%rbx\ncallq 1090 \nlea 0x1(%rax),%rdi\ncallq 10b0 \ntest %rax,%rax\nje 13bd \nmovzbl (%rbx),%edx\ntest %dl,%dl\nje 13c8 \nlea 0x1(%rbx),%rdi\nxor %r9d,%r9d\nxor %esi,%esi\nmov %rax,%rcx\njmp 138b \nnopl 0x0(%rax)\nadd $0x1,%rsi\nmov %dl,(%rcx)\nxor %r9d,%r9d\nlea (%rax,%rsi,1),%rcx\nmov %rcx,%r8\nmovzbl (%rdi),%edx\nadd $0x1,%rdi\ntest %dl,%dl\nje 13b7 \nmov %rcx,%r8\ncmp $0x20,%dl\njne 1370 \ntest %r9d,%r9d\njne 1380 \nadd $0x1,%rsi\nmovzbl (%rdi),%edx\nmovb $0x20,(%rcx)\nadd $0x1,%rdi\nlea (%rax,%rsi,1),%rcx\nmov $0x1,%r9d\nmov %rcx,%r8\ntest %dl,%dl\njne 138b \nmovb $0x0,(%r8)\npop %rbx\nretq\nxor %eax,%eax\npop %rbx\nretq\nnopl 0x0(%rax)\nmov %rax,%r8\njmp 13b7 \nnopl (%rax)\nxor %eax,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\ntest rdi, rdi\njz short loc_13B8\npush rbx\nmov rbx, rdi\ncall _strlen\nlea rdi, [rax+1]; size\ncall _malloc\ntest rax, rax\njz short loc_13AB\nmovzx edx, byte ptr [rbx]\ntest dl, dl\njz short loc_13B0\nlea rdi, [rbx+1]\nxor r8d, r8d\nxor ecx, ecx\nmov rsi, rax\njmp short loc_1380\nloc_1368:\nadd rcx, 1\nmov [rsi], dl\nxor r8d, r8d\nlea rsi, [rax+rcx]\nloc_1375:\nmovzx edx, byte ptr [rdi]\nadd rdi, 1\ntest dl, dl\njz short loc_13A6\nloc_1380:\ncmp dl, 20h ; ' '\njnz short loc_1368\ntest r8d, r8d\njnz short loc_1375\nmovzx edx, byte ptr [rdi]\nadd rcx, 1\nmov byte ptr [rsi], 20h ; ' '\nadd rdi, 1\nmov r8d, 1\nlea rsi, [rax+rcx]\ntest dl, dl\njnz short loc_1380\nloc_13A6:\nmov byte ptr [rsi], 0\npop rbx\nretn\nloc_13AB:\nxor eax, eax\npop rbx\nretn\nloc_13B0:\nmov rsi, rax\njmp short loc_13A6\nloc_13B8:\nxor eax, eax\nretn", + "ida_pseudo": "char *__fastcall func0(const char *a1)\n{\n size_t v1; // rax\n char *result; // rax\n char v3; // dl\n char *v4; // rdi\n int v5; // r8d\n __int64 v6; // rcx\n char *v7; // rsi\n\n if ( !a1 )\n return 0LL;\n v1 = strlen(a1);\n result = (char *)malloc(v1 + 1);\n if ( !result )\n return 0LL;\n v3 = *a1;\n if ( *a1 )\n {\n v4 = (char *)(a1 + 1);\n v5 = 0;\n v6 = 0LL;\n v7 = result;\n while ( 1 )\n {\n while ( v3 != 32 )\n {\n ++v6;\n *v7 = v3;\n v5 = 0;\n v7 = &result[v6];\nLABEL_6:\n v3 = *v4++;\n if ( !v3 )\n goto LABEL_10;\n }\n if ( v5 )\n goto LABEL_6;\n v3 = *v4;\n ++v6;\n *v7 = 32;\n ++v4;\n v5 = 1;\n v7 = &result[v6];\n if ( !v3 )\n goto LABEL_10;\n }\n }\n v7 = result;\nLABEL_10:\n *v7 = 0;\n return result;\n}", + "ida_strip_asm": "sub_1330:\nendbr64\ntest rdi, rdi\njz short loc_13B8\npush rbx\nmov rbx, rdi\ncall _strlen\nlea rdi, [rax+1]; size\ncall _malloc\ntest rax, rax\njz short loc_13AB\nmovzx edx, byte ptr [rbx]\ntest dl, dl\njz short loc_13B0\nlea rdi, [rbx+1]\nxor r8d, r8d\nxor ecx, ecx\nmov rsi, rax\njmp short loc_1380\nloc_1368:\nadd rcx, 1\nmov [rsi], dl\nxor r8d, r8d\nlea rsi, [rax+rcx]\nloc_1375:\nmovzx edx, byte ptr [rdi]\nadd rdi, 1\ntest dl, dl\njz short loc_13A6\nloc_1380:\ncmp dl, 20h ; ' '\njnz short loc_1368\ntest r8d, r8d\njnz short loc_1375\nmovzx edx, byte ptr [rdi]\nadd rcx, 1\nmov byte ptr [rsi], 20h ; ' '\nadd rdi, 1\nmov r8d, 1\nlea rsi, [rax+rcx]\ntest dl, dl\njnz short loc_1380\nloc_13A6:\nmov byte ptr [rsi], 0\npop rbx\nretn\nloc_13AB:\nxor eax, eax\npop rbx\nretn\nloc_13B0:\nmov rsi, rax\njmp short loc_13A6\nloc_13B8:\nxor eax, eax\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1330(const char *a1)\n{\n size_t v1; // rax\n char *result; // rax\n char v3; // dl\n char *v4; // rdi\n int v5; // r8d\n __int64 v6; // rcx\n char *v7; // rsi\n\n if ( !a1 )\n return 0LL;\n v1 = strlen(a1);\n result = (char *)malloc(v1 + 1);\n if ( !result )\n return 0LL;\n v3 = *a1;\n if ( *a1 )\n {\n v4 = (char *)(a1 + 1);\n v5 = 0;\n v6 = 0LL;\n v7 = result;\n while ( 1 )\n {\n while ( v3 != 32 )\n {\n ++v6;\n *v7 = v3;\n v5 = 0;\n v7 = &result[v6];\nLABEL_6:\n v3 = *v4++;\n if ( !v3 )\n goto LABEL_10;\n }\n if ( v5 )\n goto LABEL_6;\n v3 = *v4;\n ++v6;\n *v7 = 32;\n ++v4;\n v5 = 1;\n v7 = &result[v6];\n if ( !v3 )\n goto LABEL_10;\n }\n }\n v7 = result;\nLABEL_10:\n *v7 = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1330(const char *a1) {\n unsigned int v1;\n char *result;\n char v3;\n char *v4;\n int v5;\n long long v6;\n char *v7;\n if (!a1) return 0LL;\n v1 = strlen(a1);\n result = (char *)malloc(v1 + 1);\n if (!result) return 0LL;\n v3 = *a1;\n if (*a1) {\n v4 = (char *)(a1 + 1);\n v5 = 0;\n v6 = 0LL;\n v7 = result;\n while (1) {\n while (v3 != 32) {\n ++v6;\n *v7 = v3;\n v5 = 0;\n v7 = &result[v6];\n LABEL_6:\n v3 = *v4++;\n if (!v3) goto LABEL_10;\n }\n if (v5) goto LABEL_6;\n v3 = *v4;\n ++v6;\n *v7 = 32;\n ++v4;\n v5 = 1;\n v7 = &result[v6];\n if (!v3) goto LABEL_10;\n }\n }\n v7 = result;\nLABEL_10:\n *v7 = 0;\n return result;\n}", + "ida_pseudo_norm": "char *func0(const char *a1) {\n unsigned int v1;\n char *result;\n char v3;\n char *v4;\n int v5;\n long long v6;\n char *v7;\n if (!a1) return 0LL;\n v1 = strlen(a1);\n result = (char *)malloc(v1 + 1);\n if (!result) return 0LL;\n v3 = *a1;\n if (*a1) {\n v4 = (char *)(a1 + 1);\n v5 = 0;\n v6 = 0LL;\n v7 = result;\n while (1) {\n while (v3 != 32) {\n ++v6;\n *v7 = v3;\n v5 = 0;\n v7 = &result[v6];\n LABEL_6:\n v3 = *v4++;\n if (!v3) goto LABEL_10;\n }\n if (v5) goto LABEL_6;\n v3 = *v4;\n ++v6;\n *v7 = 32;\n ++v4;\n v5 = 1;\n v7 = &result[v6];\n if (!v3) goto LABEL_10;\n }\n }\n v7 = result;\nLABEL_10:\n *v7 = 0;\n return result;\n}" + }, + { + "index": 693, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text1) {\n if (text1 == NULL) {\n return NULL;\n }\n size_t len = strlen(text1);\n char* result = malloc(len + 1);\n if (result == NULL) {\n return NULL;\n }\n size_t i = 0, j = 0;\n int space_found = 0;\n while (text1[i] != '\\0') {\n if (text1[i] != ' ') {\n result[j++] = text1[i];\n space_found = 0;\n } else {\n if (!space_found) {\n result[j++] = ' ';\n space_found = 1;\n }\n }\n i++;\n }\n result[j] = '\\0';\n return result;\n}", + "test": "int main() {\n\n char* result;\n\n\n\n result = func0(\"Google Assistant\");\n\n assert(result != NULL);\n\n assert(strcmp(result, \"Google Assistant\") == 0);\n\n free(result);\n\n\n\n result = func0(\"Quad Core\");\n\n assert(result != NULL);\n\n assert(strcmp(result, \"Quad Core\") == 0);\n\n free(result);\n\n\n\n result = func0(\"ChromeCast Built-in\");\n\n assert(result != NULL);\n\n assert(strcmp(result, \"ChromeCast Built-in\") == 0);\n\n free(result);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ntest %rdi,%rdi\nje 13d0 \npush %rbx\nmov %rdi,%rbx\ncallq 1090 \nlea 0x1(%rax),%rdi\ncallq 10b0 \ntest %rax,%rax\nje 13bd \nmovzbl (%rbx),%edx\ntest %dl,%dl\nje 13c8 \nlea 0x1(%rbx),%rdi\nxor %r9d,%r9d\nxor %esi,%esi\nmov %rax,%rcx\njmp 138b \nnopl 0x0(%rax)\nadd $0x1,%rsi\nmov %dl,(%rcx)\nxor %r9d,%r9d\nlea (%rax,%rsi,1),%rcx\nmov %rcx,%r8\nmovzbl (%rdi),%edx\nadd $0x1,%rdi\ntest %dl,%dl\nje 13b7 \nmov %rcx,%r8\ncmp $0x20,%dl\njne 1370 \ntest %r9d,%r9d\njne 1380 \nadd $0x1,%rsi\nmovzbl (%rdi),%edx\nmovb $0x20,(%rcx)\nadd $0x1,%rdi\nlea (%rax,%rsi,1),%rcx\nmov $0x1,%r9d\nmov %rcx,%r8\ntest %dl,%dl\njne 138b \nmovb $0x0,(%r8)\npop %rbx\nretq\nxor %eax,%eax\npop %rbx\nretq\nnopl 0x0(%rax)\nmov %rax,%r8\njmp 13b7 \nnopl (%rax)\nxor %eax,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\ntest rdi, rdi\njz short loc_13B8\npush rbx\nmov rbx, rdi\ncall _strlen\nlea rdi, [rax+1]; size\ncall _malloc\ntest rax, rax\njz short loc_13AB\nmovzx edx, byte ptr [rbx]\ntest dl, dl\njz short loc_13B0\nlea rdi, [rbx+1]\nxor r8d, r8d\nxor ecx, ecx\nmov rsi, rax\njmp short loc_1380\nloc_1368:\nadd rcx, 1\nmov [rsi], dl\nxor r8d, r8d\nlea rsi, [rax+rcx]\nloc_1375:\nmovzx edx, byte ptr [rdi]\nadd rdi, 1\ntest dl, dl\njz short loc_13A6\nloc_1380:\ncmp dl, 20h ; ' '\njnz short loc_1368\ntest r8d, r8d\njnz short loc_1375\nmovzx edx, byte ptr [rdi]\nadd rcx, 1\nmov byte ptr [rsi], 20h ; ' '\nadd rdi, 1\nmov r8d, 1\nlea rsi, [rax+rcx]\ntest dl, dl\njnz short loc_1380\nloc_13A6:\nmov byte ptr [rsi], 0\npop rbx\nretn\nloc_13AB:\nxor eax, eax\npop rbx\nretn\nloc_13B0:\nmov rsi, rax\njmp short loc_13A6\nloc_13B8:\nxor eax, eax\nretn", + "ida_pseudo": "char *__fastcall func0(const char *a1)\n{\n size_t v1; // rax\n char *result; // rax\n char v3; // dl\n char *v4; // rdi\n int v5; // r8d\n __int64 v6; // rcx\n char *v7; // rsi\n\n if ( !a1 )\n return 0LL;\n v1 = strlen(a1);\n result = (char *)malloc(v1 + 1);\n if ( !result )\n return 0LL;\n v3 = *a1;\n if ( *a1 )\n {\n v4 = (char *)(a1 + 1);\n v5 = 0;\n v6 = 0LL;\n v7 = result;\n while ( 1 )\n {\n while ( v3 != 32 )\n {\n ++v6;\n *v7 = v3;\n v5 = 0;\n v7 = &result[v6];\nLABEL_6:\n v3 = *v4++;\n if ( !v3 )\n goto LABEL_10;\n }\n if ( v5 )\n goto LABEL_6;\n v3 = *v4;\n ++v6;\n *v7 = 32;\n ++v4;\n v5 = 1;\n v7 = &result[v6];\n if ( !v3 )\n goto LABEL_10;\n }\n }\n v7 = result;\nLABEL_10:\n *v7 = 0;\n return result;\n}", + "ida_strip_asm": "sub_1330:\nendbr64\ntest rdi, rdi\njz short loc_13B8\npush rbx\nmov rbx, rdi\ncall _strlen\nlea rdi, [rax+1]; size\ncall _malloc\ntest rax, rax\njz short loc_13AB\nmovzx edx, byte ptr [rbx]\ntest dl, dl\njz short loc_13B0\nlea rdi, [rbx+1]\nxor r8d, r8d\nxor ecx, ecx\nmov rsi, rax\njmp short loc_1380\nloc_1368:\nadd rcx, 1\nmov [rsi], dl\nxor r8d, r8d\nlea rsi, [rax+rcx]\nloc_1375:\nmovzx edx, byte ptr [rdi]\nadd rdi, 1\ntest dl, dl\njz short loc_13A6\nloc_1380:\ncmp dl, 20h ; ' '\njnz short loc_1368\ntest r8d, r8d\njnz short loc_1375\nmovzx edx, byte ptr [rdi]\nadd rcx, 1\nmov byte ptr [rsi], 20h ; ' '\nadd rdi, 1\nmov r8d, 1\nlea rsi, [rax+rcx]\ntest dl, dl\njnz short loc_1380\nloc_13A6:\nmov byte ptr [rsi], 0\npop rbx\nretn\nloc_13AB:\nxor eax, eax\npop rbx\nretn\nloc_13B0:\nmov rsi, rax\njmp short loc_13A6\nloc_13B8:\nxor eax, eax\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1330(const char *a1)\n{\n size_t v1; // rax\n char *result; // rax\n char v3; // dl\n char *v4; // rdi\n int v5; // r8d\n __int64 v6; // rcx\n char *v7; // rsi\n\n if ( !a1 )\n return 0LL;\n v1 = strlen(a1);\n result = (char *)malloc(v1 + 1);\n if ( !result )\n return 0LL;\n v3 = *a1;\n if ( *a1 )\n {\n v4 = (char *)(a1 + 1);\n v5 = 0;\n v6 = 0LL;\n v7 = result;\n while ( 1 )\n {\n while ( v3 != 32 )\n {\n ++v6;\n *v7 = v3;\n v5 = 0;\n v7 = &result[v6];\nLABEL_6:\n v3 = *v4++;\n if ( !v3 )\n goto LABEL_10;\n }\n if ( v5 )\n goto LABEL_6;\n v3 = *v4;\n ++v6;\n *v7 = 32;\n ++v4;\n v5 = 1;\n v7 = &result[v6];\n if ( !v3 )\n goto LABEL_10;\n }\n }\n v7 = result;\nLABEL_10:\n *v7 = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1330(const char *a1) {\n unsigned int v1;\n char *result;\n char v3;\n char *v4;\n int v5;\n long long v6;\n char *v7;\n if (!a1) return 0LL;\n v1 = strlen(a1);\n result = (char *)malloc(v1 + 1);\n if (!result) return 0LL;\n v3 = *a1;\n if (*a1) {\n v4 = (char *)(a1 + 1);\n v5 = 0;\n v6 = 0LL;\n v7 = result;\n while (1) {\n while (v3 != 32) {\n ++v6;\n *v7 = v3;\n v5 = 0;\n v7 = &result[v6];\n LABEL_6:\n v3 = *v4++;\n if (!v3) goto LABEL_10;\n }\n if (v5) goto LABEL_6;\n v3 = *v4;\n ++v6;\n *v7 = 32;\n ++v4;\n v5 = 1;\n v7 = &result[v6];\n if (!v3) goto LABEL_10;\n }\n }\n v7 = result;\nLABEL_10:\n *v7 = 0;\n return result;\n}", + "ida_pseudo_norm": "char *func0(const char *a1) {\n unsigned int v1;\n char *result;\n char v3;\n char *v4;\n int v5;\n long long v6;\n char *v7;\n if (!a1) return 0LL;\n v1 = strlen(a1);\n result = (char *)malloc(v1 + 1);\n if (!result) return 0LL;\n v3 = *a1;\n if (*a1) {\n v4 = (char *)(a1 + 1);\n v5 = 0;\n v6 = 0LL;\n v7 = result;\n while (1) {\n while (v3 != 32) {\n ++v6;\n *v7 = v3;\n v5 = 0;\n v7 = &result[v6];\n LABEL_6:\n v3 = *v4++;\n if (!v3) goto LABEL_10;\n }\n if (v5) goto LABEL_6;\n v3 = *v4;\n ++v6;\n *v7 = 32;\n ++v4;\n v5 = 1;\n v7 = &result[v6];\n if (!v3) goto LABEL_10;\n }\n }\n v7 = result;\nLABEL_10:\n *v7 = 0;\n return result;\n}" + }, + { + "index": 694, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint cmpfunc(const void* a, const void* b) {\n\n return (*(int*)a - *(int*)b);\n\n}\n\n\n\n", + "func": "int* func0(int** arrs, int sizes[], int n, int* res_size) {\n int max_elements = 0;\n for (int i = 0; i < n; ++i) {\n max_elements += sizes[i];\n }\n int* buf = (int*)malloc(max_elements * sizeof(int));\n int buf_len = 0;\n for (int i = 0; i < n; ++i) {\n for (int j = 0; j < sizes[i]; ++j) {\n int should_add = 1;\n for (int k = 0; k < buf_len; ++k) {\n if (buf[k] == arrs[i][j]) {\n should_add = 0;\n break;\n }\n }\n if (should_add) {\n buf[buf_len++] = arrs[i][j];\n }\n }\n }\n qsort(buf, buf_len, sizeof(int), cmpfunc);\n *res_size = buf_len;\n return buf;\n}", + "test": "int main() {\n\n int arr1_1[] = {5, 6, 7, 8};\n\n int arr1_2[] = {10, 11, 7, 5};\n\n int arr1_3[] = {6, 12, 10, 8};\n\n int arr1_4[] = {1, 2, 5};\n\n int* arrs1[] = {arr1_1, arr1_2, arr1_3, arr1_4};\n\n int sizes1[] = {4, 4, 4, 3};\n\n int res_size1;\n\n int* result1 = func0(arrs1, sizes1, 4, &res_size1);\n\n int expected1[] = {1, 2, 5, 6, 7, 8, 10, 11, 12};\n\n assert(res_size1 == 9);\n\n for (int i = 0; i < res_size1; ++i) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n free(result1);\n\n\n\n int arr2_1[] = {7, 1, 9, 4};\n\n int arr2_2[] = {11, 21, 36, 14, 9};\n\n int arr2_3[] = {4, 1, 21, 39, 47};\n\n int arr2_4[] = {1, 32, 38};\n\n int* arrs2[] = {arr2_1, arr2_2, arr2_3, arr2_4};\n\n int sizes2[] = {4, 5, 5, 3};\n\n int res_size2;\n\n int* result2 = func0(arrs2, sizes2, 4, &res_size2);\n\n int expected2[] = {1, 4, 7, 9, 11, 14, 21, 32, 36, 38, 39, 47};\n\n assert(res_size2 == 12);\n\n for (int i = 0; i < res_size2; ++i) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n free(result2);\n\n\n\n int arr3_1[] = {11, 13, 14, 17};\n\n int arr3_2[] = {12, 11, 15, 18};\n\n int arr3_3[] = {19, 21, 15, 36};\n\n int arr3_4[] = {37, 36, 35};\n\n int* arrs3[] = {arr3_1, arr3_2, arr3_3, arr3_4};\n\n int sizes3[] = {4, 4, 4, 3};\n\n int res_size3;\n\n int* result3 = func0(arrs3, sizes3, 4, &res_size3);\n\n int expected3[] = {11, 12, 13, 14, 15, 17, 18, 19, 21, 35, 36, 37};\n\n assert(res_size3 == 12);\n\n for (int i = 0; i < res_size3; ++i) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x50,%rsp\nmov %rdi,-0x38(%rbp)\nmov %rsi,-0x40(%rbp)\nmov %edx,-0x44(%rbp)\nmov %rcx,-0x50(%rbp)\nmovl $0x0,-0x24(%rbp)\nmovl $0x0,-0x20(%rbp)\njmp 1233 \nmov -0x20(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x40(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nadd %eax,-0x24(%rbp)\naddl $0x1,-0x20(%rbp)\nmov -0x20(%rbp),%eax\ncmp -0x44(%rbp),%eax\njl 1216 \nmov -0x24(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0x1c(%rbp)\nmovl $0x0,-0x18(%rbp)\njmpq 1344 \nmovl $0x0,-0x14(%rbp)\njmpq 1321 \nmovl $0x1,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 12cc \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x38(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%rax\nmov -0x14(%rbp),%ecx\nmovslq %ecx,%rcx\nshl $0x2,%rcx\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 12c8 \nmovl $0x0,-0x10(%rbp)\njmp 12d4 \naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 127f \ncmpl $0x0,-0x10(%rbp)\nje 131d \nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0x14(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x2,%rdx\nlea (%rax,%rdx,1),%rcx\nmov -0x1c(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x1c(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x14(%rbp)\nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x40(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x14(%rbp)\njl 126f \naddl $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%eax\ncmp -0x44(%rbp),%eax\njl 1263 \nmov -0x1c(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x8(%rbp),%rax\nlea -0x198(%rip),%rcx\nmov $0x4,%edx\nmov %rax,%rdi\ncallq 10a0 \nmov -0x50(%rbp),%rax\nmov -0x1c(%rbp),%edx\nmov %edx,(%rax)\nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+var_38], rdi\nmov [rbp+var_40], rsi\nmov [rbp+var_44], edx\nmov [rbp+var_50], rcx\nmov [rbp+var_24], 0\nmov [rbp+var_20], 0\njmp short loc_1233\nloc_1216:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_24], eax\nadd [rbp+var_20], 1\nloc_1233:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_44]\njl short loc_1216\nmov eax, [rbp+var_24]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+base], rax\nmov [rbp+var_1C], 0\nmov [rbp+var_18], 0\njmp loc_1344\nloc_1263:\nmov [rbp+var_14], 0\njmp loc_1321\nloc_126F:\nmov [rbp+var_10], 1\nmov [rbp+var_C], 0\njmp short loc_12CC\nloc_127F:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_18]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov rax, [rax]\nmov ecx, [rbp+var_14]\nmovsxd rcx, ecx\nshl rcx, 2\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_12C8\nmov [rbp+var_10], 0\njmp short loc_12D4\nloc_12C8:\nadd [rbp+var_C], 1\nloc_12CC:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_127F\nloc_12D4:\ncmp [rbp+var_10], 0\njz short loc_131D\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nshl rdx, 2\nlea rcx, [rax+rdx]\nmov eax, [rbp+var_1C]\nlea edx, [rax+1]\nmov [rbp+var_1C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_131D:\nadd [rbp+var_14], 1\nloc_1321:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_14], eax\njl loc_126F\nadd [rbp+var_18], 1\nloc_1344:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_44]\njl loc_1263\nmov eax, [rbp+var_1C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, cmpfunc\nmov rcx, rdx; compar\nmov edx, 4; size\nmov rdi, rax; base\ncall _qsort\nmov rax, [rbp+var_50]\nmov edx, [rbp+var_1C]\nmov [rax], edx\nmov rax, [rbp+base]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, __int64 a2, int a3, _DWORD *a4)\n{\n int v4; // eax\n int v8; // [rsp+2Ch] [rbp-24h]\n int i; // [rsp+30h] [rbp-20h]\n int v10; // [rsp+34h] [rbp-1Ch]\n int j; // [rsp+38h] [rbp-18h]\n int k; // [rsp+3Ch] [rbp-14h]\n int v13; // [rsp+40h] [rbp-10h]\n int m; // [rsp+44h] [rbp-Ch]\n _DWORD *base; // [rsp+48h] [rbp-8h]\n\n v8 = 0;\n for ( i = 0; i < a3; ++i )\n v8 += *(_DWORD *)(4LL * i + a2);\n base = malloc(4LL * v8);\n v10 = 0;\n for ( j = 0; j < a3; ++j )\n {\n for ( k = 0; k < *(_DWORD *)(4LL * j + a2); ++k )\n {\n v13 = 1;\n for ( m = 0; m < v10; ++m )\n {\n if ( base[m] == *(_DWORD *)(4LL * k + *(_QWORD *)(8LL * j + a1)) )\n {\n v13 = 0;\n break;\n }\n }\n if ( v13 )\n {\n v4 = v10++;\n base[v4] = *(_DWORD *)(*(_QWORD *)(8LL * j + a1) + 4LL * k);\n }\n }\n }\n qsort(base, v10, 4uLL, cmpfunc);\n *a4 = v10;\n return base;\n}", + "ida_strip_asm": "sub_11EB:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+var_38], rdi\nmov [rbp+var_40], rsi\nmov [rbp+var_44], edx\nmov [rbp+var_50], rcx\nmov [rbp+var_24], 0\nmov [rbp+var_20], 0\njmp short loc_1233\nloc_1216:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_24], eax\nadd [rbp+var_20], 1\nloc_1233:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_44]\njl short loc_1216\nmov eax, [rbp+var_24]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+base], rax\nmov [rbp+var_1C], 0\nmov [rbp+var_18], 0\njmp loc_1344\nloc_1263:\nmov [rbp+var_14], 0\njmp loc_1321\nloc_126F:\nmov [rbp+var_10], 1\nmov [rbp+var_C], 0\njmp short loc_12CC\nloc_127F:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_18]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov rax, [rax]\nmov ecx, [rbp+var_14]\nmovsxd rcx, ecx\nshl rcx, 2\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_12C8\nmov [rbp+var_10], 0\njmp short loc_12D4\nloc_12C8:\nadd [rbp+var_C], 1\nloc_12CC:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_127F\nloc_12D4:\ncmp [rbp+var_10], 0\njz short loc_131D\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nshl rdx, 2\nlea rcx, [rax+rdx]\nmov eax, [rbp+var_1C]\nlea edx, [rax+1]\nmov [rbp+var_1C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_131D:\nadd [rbp+var_14], 1\nloc_1321:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_14], eax\njl loc_126F\nadd [rbp+var_18], 1\nloc_1344:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_44]\njl loc_1263\nmov eax, [rbp+var_1C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 4; size\nmov rdi, rax; base\ncall _qsort\nmov rax, [rbp+var_50]\nmov edx, [rbp+var_1C]\nmov [rax], edx\nmov rax, [rbp+base]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11EB(__int64 a1, __int64 a2, int a3, _DWORD *a4)\n{\n int v4; // eax\n int v8; // [rsp+2Ch] [rbp-24h]\n int i; // [rsp+30h] [rbp-20h]\n int v10; // [rsp+34h] [rbp-1Ch]\n int j; // [rsp+38h] [rbp-18h]\n int k; // [rsp+3Ch] [rbp-14h]\n int v13; // [rsp+40h] [rbp-10h]\n int m; // [rsp+44h] [rbp-Ch]\n _DWORD *base; // [rsp+48h] [rbp-8h]\n\n v8 = 0;\n for ( i = 0; i < a3; ++i )\n v8 += *(_DWORD *)(4LL * i + a2);\n base = malloc(4LL * v8);\n v10 = 0;\n for ( j = 0; j < a3; ++j )\n {\n for ( k = 0; k < *(_DWORD *)(4LL * j + a2); ++k )\n {\n v13 = 1;\n for ( m = 0; m < v10; ++m )\n {\n if ( base[m] == *(_DWORD *)(4LL * k + *(_QWORD *)(8LL * j + a1)) )\n {\n v13 = 0;\n break;\n }\n }\n if ( v13 )\n {\n v4 = v10++;\n base[v4] = *(_DWORD *)(*(_QWORD *)(8LL * j + a1) + 4LL * k);\n }\n }\n }\n qsort(base, v10, 4uLL, compar);\n *a4 = v10;\n return base;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11EB(long long a1, long long a2, int a3, uint32_t *a4) {\n int v4;\n int v8;\n int i;\n int v10;\n int j;\n int k;\n int v13;\n int m;\n uint32_t *base;\n v8 = 0;\n for (i = 0; i < a3; ++i) v8 += *(uint32_t *)(4LL * i + a2);\n base = malloc(4LL * v8);\n v10 = 0;\n for (j = 0; j < a3; ++j) {\n for (k = 0; k < *(uint32_t *)(4LL * j + a2); ++k) {\n v13 = 1;\n for (m = 0; m < v10; ++m) {\n if (base[m] == *(uint32_t *)(4LL * k + *(uint64_t *)(8LL * j + a1))) {\n v13 = 0;\n break;\n }\n }\n if (v13) {\n v4 = v10++;\n base[v4] = *(uint32_t *)(*(uint64_t *)(8LL * j + a1) + 4LL * k);\n }\n }\n }\n qsort(base, v10, 4uLL, compar);\n *a4 = v10;\n return base;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, long long a2, int a3, uint32_t *a4) {\n int v4;\n int v8;\n int i;\n int v10;\n int j;\n int k;\n int v13;\n int m;\n uint32_t *base;\n v8 = 0;\n for (i = 0; i < a3; ++i) v8 += *(uint32_t *)(4LL * i + a2);\n base = malloc(4LL * v8);\n v10 = 0;\n for (j = 0; j < a3; ++j) {\n for (k = 0; k < *(uint32_t *)(4LL * j + a2); ++k) {\n v13 = 1;\n for (m = 0; m < v10; ++m) {\n if (base[m] == *(uint32_t *)(4LL * k + *(uint64_t *)(8LL * j + a1))) {\n v13 = 0;\n break;\n }\n }\n if (v13) {\n v4 = v10++;\n base[v4] = *(uint32_t *)(*(uint64_t *)(8LL * j + a1) + 4LL * k);\n }\n }\n }\n qsort(base, v10, 4uLL, cmpfunc);\n *a4 = v10;\n return base;\n}" + }, + { + "index": 694, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint cmpfunc(const void* a, const void* b) {\n\n return (*(int*)a - *(int*)b);\n\n}\n\n\n\n", + "func": "int* func0(int** arrs, int sizes[], int n, int* res_size) {\n int max_elements = 0;\n for (int i = 0; i < n; ++i) {\n max_elements += sizes[i];\n }\n int* buf = (int*)malloc(max_elements * sizeof(int));\n int buf_len = 0;\n for (int i = 0; i < n; ++i) {\n for (int j = 0; j < sizes[i]; ++j) {\n int should_add = 1;\n for (int k = 0; k < buf_len; ++k) {\n if (buf[k] == arrs[i][j]) {\n should_add = 0;\n break;\n }\n }\n if (should_add) {\n buf[buf_len++] = arrs[i][j];\n }\n }\n }\n qsort(buf, buf_len, sizeof(int), cmpfunc);\n *res_size = buf_len;\n return buf;\n}", + "test": "int main() {\n\n int arr1_1[] = {5, 6, 7, 8};\n\n int arr1_2[] = {10, 11, 7, 5};\n\n int arr1_3[] = {6, 12, 10, 8};\n\n int arr1_4[] = {1, 2, 5};\n\n int* arrs1[] = {arr1_1, arr1_2, arr1_3, arr1_4};\n\n int sizes1[] = {4, 4, 4, 3};\n\n int res_size1;\n\n int* result1 = func0(arrs1, sizes1, 4, &res_size1);\n\n int expected1[] = {1, 2, 5, 6, 7, 8, 10, 11, 12};\n\n assert(res_size1 == 9);\n\n for (int i = 0; i < res_size1; ++i) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n free(result1);\n\n\n\n int arr2_1[] = {7, 1, 9, 4};\n\n int arr2_2[] = {11, 21, 36, 14, 9};\n\n int arr2_3[] = {4, 1, 21, 39, 47};\n\n int arr2_4[] = {1, 32, 38};\n\n int* arrs2[] = {arr2_1, arr2_2, arr2_3, arr2_4};\n\n int sizes2[] = {4, 5, 5, 3};\n\n int res_size2;\n\n int* result2 = func0(arrs2, sizes2, 4, &res_size2);\n\n int expected2[] = {1, 4, 7, 9, 11, 14, 21, 32, 36, 38, 39, 47};\n\n assert(res_size2 == 12);\n\n for (int i = 0; i < res_size2; ++i) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n free(result2);\n\n\n\n int arr3_1[] = {11, 13, 14, 17};\n\n int arr3_2[] = {12, 11, 15, 18};\n\n int arr3_3[] = {19, 21, 15, 36};\n\n int arr3_4[] = {37, 36, 35};\n\n int* arrs3[] = {arr3_1, arr3_2, arr3_3, arr3_4};\n\n int sizes3[] = {4, 4, 4, 3};\n\n int res_size3;\n\n int* result3 = func0(arrs3, sizes3, 4, &res_size3);\n\n int expected3[] = {11, 12, 13, 14, 15, 17, 18, 19, 21, 35, 36, 37};\n\n assert(res_size3 == 12);\n\n for (int i = 0; i < res_size3; ++i) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %rcx,%r14\ntest %edx,%edx\njle 1294 \nmov %rdi,%rbx\nmov %rsi,%rax\nmov %rsi,%r12\nlea -0x1(%rdx),%r13d\nlea 0x4(%rsi,%r13,4),%rcx\nmov $0x0,%edx\nadd (%rax),%edx\nadd $0x4,%rax\ncmp %rcx,%rax\njne 1200 \nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rdi\ncallq 10d0 \nmov %rax,%rbp\nmov %rbx,%rdi\nlea 0x8(%rbx,%r13,8),%r10\nmov $0x0,%ebx\nlea 0x4(%rax),%r9\njmp 123e \nadd $0x4,%r12\nadd $0x8,%rdi\ncmp %r10,%rdi\nje 12a6 \nmov (%r12),%eax\ntest %eax,%eax\njle 1231 \nlea -0x1(%rax),%eax\nlea 0x4(,%rax,4),%r8\nmov $0x0,%esi\njmp 1271 \nmov (%rdi),%rax\nmov (%rax,%rsi,1),%edx\nmovslq %ebx,%rax\nmov %edx,0x0(%rbp,%rax,4)\nlea 0x1(%rbx),%ebx\nadd $0x4,%rsi\ncmp %r8,%rsi\nje 1231 \ntest %ebx,%ebx\njle 1258 \nmov (%rdi),%rax\nmov (%rax,%rsi,1),%edx\nmov %rbp,%rax\nlea -0x1(%rbx),%ecx\nlea (%r9,%rcx,4),%rcx\ncmp %edx,(%rax)\nje 1268 \nadd $0x4,%rax\ncmp %rax,%rcx\njne 1285 \njmp 1258 \nmov $0x0,%edi\ncallq 10d0 \nmov %rax,%rbp\nmov $0x0,%ebx\nmovslq %ebx,%rsi\nlea -0xe7(%rip),%rcx\nmov $0x4,%edx\nmov %rbp,%rdi\ncallq 10a0 \nmov %ebx,(%r14)\nmov %rbp,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r15, rcx\ntest edx, edx\njle loc_1293\nmov r12, rdi\nmov r14, rsi\nmov rax, rsi\nmovsxd r13, edx\nlea rsi, [rsi+r13*4]\nmov ecx, 0\nloc_1204:\nmov edx, ecx\nadd edx, [rax]\nmov ecx, edx\nadd rax, 4\ncmp rax, rsi\njnz short loc_1204\nmovsxd rdx, edx\nlea rdi, ds:0[rdx*4]; size\ncall _malloc\nmov rbp, rax\nmov edi, 0\nmov ebx, 0\njmp short loc_127A\nloc_1232:\nmov rax, [r12+rdi*8]\nmov edx, [rax+rsi]\nmovsxd rax, ebx\nmov [rbp+rax*4+0], edx\nlea ebx, [rbx+1]\nloc_1243:\nadd rsi, 4\ncmp rsi, r8\njz short loc_1271\nloc_124C:\ntest ebx, ebx\njle short loc_1232\nmov rax, [r12+rdi*8]\nmov edx, [rax+rsi]\nmov rax, rbp\nmovsxd rcx, ebx\nlea rcx, [rbp+rcx*4+0]\nloc_1262:\ncmp [rax], edx\njz short loc_1243\nadd rax, 4\ncmp rax, rcx\njnz short loc_1262\njmp short loc_1232\nloc_1271:\nadd rdi, 1\ncmp rdi, r13\njz short loc_12A5\nloc_127A:\nmov eax, [r14+rdi*4]\ntest eax, eax\njle short loc_1271\ncdqe\nlea r8, ds:0[rax*4]\nmov esi, 0\njmp short loc_124C\nloc_1293:\nmov edi, 0; size\ncall _malloc\nmov rbp, rax\nmov ebx, 0\nloc_12A5:\nmovsxd rsi, ebx; nmemb\nlea rcx, cmpfunc; compar\nmov edx, 4; size\nmov rdi, rbp; base\ncall _qsort\nmov [r15], ebx\nmov rax, rbp\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, _DWORD *a2, int a3, int *a4)\n{\n _DWORD *v7; // rax\n __int64 v8; // r13\n _DWORD *v9; // rsi\n int v10; // ecx\n int v11; // edx\n _DWORD *v12; // rbp\n __int64 v13; // rdi\n int v14; // ebx\n __int64 v15; // rsi\n _DWORD *v16; // rax\n int v17; // eax\n __int64 v18; // r8\n\n if ( a3 <= 0 )\n {\n v12 = malloc(0LL);\n v14 = 0;\n }\n else\n {\n v7 = a2;\n v8 = a3;\n v9 = &a2[a3];\n v10 = 0;\n do\n {\n v11 = *v7 + v10;\n v10 = v11;\n ++v7;\n }\n while ( v7 != v9 );\n v12 = malloc(4LL * v11);\n v13 = 0LL;\n v14 = 0;\n do\n {\n v17 = a2[v13];\n if ( v17 > 0 )\n {\n v18 = 4LL * v17;\n v15 = 0LL;\n do\n {\n if ( v14 <= 0 )\n {\nLABEL_5:\n v12[v14++] = *(_DWORD *)(*(_QWORD *)(a1 + 8 * v13) + v15);\n }\n else\n {\n v16 = v12;\n while ( *v16 != *(_DWORD *)(*(_QWORD *)(a1 + 8 * v13) + v15) )\n {\n if ( ++v16 == &v12[v14] )\n goto LABEL_5;\n }\n }\n v15 += 4LL;\n }\n while ( v15 != v18 );\n }\n ++v13;\n }\n while ( v13 != v8 );\n }\n qsort(v12, v14, 4uLL, cmpfunc);\n *a4 = v14;\n return v12;\n}", + "ida_strip_asm": "sub_11D2:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r15, rcx\ntest edx, edx\njle loc_1293\nmov r12, rdi\nmov r14, rsi\nmov rax, rsi\nmovsxd r13, edx\nlea rsi, [rsi+r13*4]\nmov ecx, 0\nloc_1204:\nmov edx, ecx\nadd edx, [rax]\nmov ecx, edx\nadd rax, 4\ncmp rax, rsi\njnz short loc_1204\nmovsxd rdx, edx\nlea rdi, ds:0[rdx*4]; size\ncall _malloc\nmov rbp, rax\nmov edi, 0\nmov ebx, 0\njmp short loc_127A\nloc_1232:\nmov rax, [r12+rdi*8]\nmov edx, [rax+rsi]\nmovsxd rax, ebx\nmov [rbp+rax*4+0], edx\nlea ebx, [rbx+1]\nloc_1243:\nadd rsi, 4\ncmp rsi, r8\njz short loc_1271\nloc_124C:\ntest ebx, ebx\njle short loc_1232\nmov rax, [r12+rdi*8]\nmov edx, [rax+rsi]\nmov rax, rbp\nmovsxd rcx, ebx\nlea rcx, [rbp+rcx*4+0]\nloc_1262:\ncmp [rax], edx\njz short loc_1243\nadd rax, 4\ncmp rax, rcx\njnz short loc_1262\njmp short loc_1232\nloc_1271:\nadd rdi, 1\ncmp rdi, r13\njz short loc_12A5\nloc_127A:\nmov eax, [r14+rdi*4]\ntest eax, eax\njle short loc_1271\ncdqe\nlea r8, ds:0[rax*4]\nmov esi, 0\njmp short loc_124C\nloc_1293:\nmov edi, 0; size\ncall _malloc\nmov rbp, rax\nmov ebx, 0\nloc_12A5:\nmovsxd rsi, ebx; nmemb\nlea rcx, compar; compar\nmov edx, 4; size\nmov rdi, rbp; base\ncall _qsort\nmov [r15], ebx\nmov rax, rbp\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11D2(__int64 a1, _DWORD *a2, int a3, int *a4)\n{\n _DWORD *v7; // rax\n __int64 v8; // r13\n _DWORD *v9; // rsi\n int v10; // ecx\n int v11; // edx\n _DWORD *v12; // rbp\n __int64 v13; // rdi\n int v14; // ebx\n __int64 v15; // rsi\n _DWORD *v16; // rax\n int v17; // eax\n __int64 v18; // r8\n\n if ( a3 <= 0 )\n {\n v12 = malloc(0LL);\n v14 = 0;\n }\n else\n {\n v7 = a2;\n v8 = a3;\n v9 = &a2[a3];\n v10 = 0;\n do\n {\n v11 = *v7 + v10;\n v10 = v11;\n ++v7;\n }\n while ( v7 != v9 );\n v12 = malloc(4LL * v11);\n v13 = 0LL;\n v14 = 0;\n do\n {\n v17 = a2[v13];\n if ( v17 > 0 )\n {\n v18 = 4LL * v17;\n v15 = 0LL;\n do\n {\n if ( v14 <= 0 )\n {\nLABEL_5:\n v12[v14++] = *(_DWORD *)(*(_QWORD *)(a1 + 8 * v13) + v15);\n }\n else\n {\n v16 = v12;\n while ( *v16 != *(_DWORD *)(*(_QWORD *)(a1 + 8 * v13) + v15) )\n {\n if ( ++v16 == &v12[v14] )\n goto LABEL_5;\n }\n }\n v15 += 4LL;\n }\n while ( v15 != v18 );\n }\n ++v13;\n }\n while ( v13 != v8 );\n }\n qsort(v12, v14, 4uLL, compar);\n *a4 = v14;\n return v12;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11D2(long long a1, uint32_t *a2, int a3, int *a4) {\n uint32_t *v7;\n long long v8;\n uint32_t *v9;\n int v10;\n int v11;\n uint32_t *v12;\n long long v13;\n int v14;\n long long v15;\n uint32_t *v16;\n int v17;\n long long v18;\n if (a3 <= 0) {\n v12 = malloc(0LL);\n v14 = 0;\n } else {\n v7 = a2;\n v8 = a3;\n v9 = &a2[a3];\n v10 = 0;\n do {\n v11 = *v7 + v10;\n v10 = v11;\n ++v7;\n } while (v7 != v9);\n v12 = malloc(4LL * v11);\n v13 = 0LL;\n v14 = 0;\n do {\n v17 = a2[v13];\n if (v17 > 0) {\n v18 = 4LL * v17;\n v15 = 0LL;\n do {\n if (v14 <= 0) {\n LABEL_5:\n v12[v14++] = *(uint32_t *)(*(uint64_t *)(a1 + 8 * v13) + v15);\n } else {\n v16 = v12;\n while (*v16 != *(uint32_t *)(*(uint64_t *)(a1 + 8 * v13) + v15)) {\n if (++v16 == &v12[v14]) goto LABEL_5;\n }\n }\n v15 += 4LL;\n } while (v15 != v18);\n }\n ++v13;\n } while (v13 != v8);\n }\n qsort(v12, v14, 4uLL, compar);\n *a4 = v14;\n return v12;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, uint32_t *a2, int a3, int *a4) {\n uint32_t *v7;\n long long v8;\n uint32_t *v9;\n int v10;\n int v11;\n uint32_t *v12;\n long long v13;\n int v14;\n long long v15;\n uint32_t *v16;\n int v17;\n long long v18;\n if (a3 <= 0) {\n v12 = malloc(0LL);\n v14 = 0;\n } else {\n v7 = a2;\n v8 = a3;\n v9 = &a2[a3];\n v10 = 0;\n do {\n v11 = *v7 + v10;\n v10 = v11;\n ++v7;\n } while (v7 != v9);\n v12 = malloc(4LL * v11);\n v13 = 0LL;\n v14 = 0;\n do {\n v17 = a2[v13];\n if (v17 > 0) {\n v18 = 4LL * v17;\n v15 = 0LL;\n do {\n if (v14 <= 0) {\n LABEL_5:\n v12[v14++] = *(uint32_t *)(*(uint64_t *)(a1 + 8 * v13) + v15);\n } else {\n v16 = v12;\n while (*v16 != *(uint32_t *)(*(uint64_t *)(a1 + 8 * v13) + v15)) {\n if (++v16 == &v12[v14]) goto LABEL_5;\n }\n }\n v15 += 4LL;\n } while (v15 != v18);\n }\n ++v13;\n } while (v13 != v8);\n }\n qsort(v12, v14, 4uLL, cmpfunc);\n *a4 = v14;\n return v12;\n}" + }, + { + "index": 694, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint cmpfunc(const void* a, const void* b) {\n\n return (*(int*)a - *(int*)b);\n\n}\n\n\n\n", + "func": "int* func0(int** arrs, int sizes[], int n, int* res_size) {\n int max_elements = 0;\n for (int i = 0; i < n; ++i) {\n max_elements += sizes[i];\n }\n int* buf = (int*)malloc(max_elements * sizeof(int));\n int buf_len = 0;\n for (int i = 0; i < n; ++i) {\n for (int j = 0; j < sizes[i]; ++j) {\n int should_add = 1;\n for (int k = 0; k < buf_len; ++k) {\n if (buf[k] == arrs[i][j]) {\n should_add = 0;\n break;\n }\n }\n if (should_add) {\n buf[buf_len++] = arrs[i][j];\n }\n }\n }\n qsort(buf, buf_len, sizeof(int), cmpfunc);\n *res_size = buf_len;\n return buf;\n}", + "test": "int main() {\n\n int arr1_1[] = {5, 6, 7, 8};\n\n int arr1_2[] = {10, 11, 7, 5};\n\n int arr1_3[] = {6, 12, 10, 8};\n\n int arr1_4[] = {1, 2, 5};\n\n int* arrs1[] = {arr1_1, arr1_2, arr1_3, arr1_4};\n\n int sizes1[] = {4, 4, 4, 3};\n\n int res_size1;\n\n int* result1 = func0(arrs1, sizes1, 4, &res_size1);\n\n int expected1[] = {1, 2, 5, 6, 7, 8, 10, 11, 12};\n\n assert(res_size1 == 9);\n\n for (int i = 0; i < res_size1; ++i) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n free(result1);\n\n\n\n int arr2_1[] = {7, 1, 9, 4};\n\n int arr2_2[] = {11, 21, 36, 14, 9};\n\n int arr2_3[] = {4, 1, 21, 39, 47};\n\n int arr2_4[] = {1, 32, 38};\n\n int* arrs2[] = {arr2_1, arr2_2, arr2_3, arr2_4};\n\n int sizes2[] = {4, 5, 5, 3};\n\n int res_size2;\n\n int* result2 = func0(arrs2, sizes2, 4, &res_size2);\n\n int expected2[] = {1, 4, 7, 9, 11, 14, 21, 32, 36, 38, 39, 47};\n\n assert(res_size2 == 12);\n\n for (int i = 0; i < res_size2; ++i) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n free(result2);\n\n\n\n int arr3_1[] = {11, 13, 14, 17};\n\n int arr3_2[] = {12, 11, 15, 18};\n\n int arr3_3[] = {19, 21, 15, 36};\n\n int arr3_4[] = {37, 36, 35};\n\n int* arrs3[] = {arr3_1, arr3_2, arr3_3, arr3_4};\n\n int sizes3[] = {4, 4, 4, 3};\n\n int res_size3;\n\n int* result3 = func0(arrs3, sizes3, 4, &res_size3);\n\n int expected3[] = {11, 12, 13, 14, 15, 17, 18, 19, 21, 35, 36, 37};\n\n assert(res_size3 == 12);\n\n for (int i = 0; i < res_size3; ++i) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\nmov %rcx,%rbp\npush %rbx\ntest %edx,%edx\njle 1890 \nmov %edx,%eax\nmov %rdi,%rbx\nmov %rsi,%r13\nxor %edx,%edx\nsub $0x1,%eax\nlea 0x4(%rsi,%rax,4),%r14\nmov %rsi,%rax\nnopl 0x0(%rax)\nadd (%rax),%edx\nadd $0x4,%rax\ncmp %r14,%rax\njne 17c0 \nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rdi\ncallq 10d0 \nmov %rbx,%r10\nxor %ebx,%ebx\nmov %rax,%r12\nlea 0x4(%rax),%r9\nnopw 0x0(%rax,%rax,1)\nmov 0x0(%r13),%eax\ntest %eax,%eax\njle 183e \nsub $0x1,%eax\nmov (%r10),%rdi\nxor %esi,%esi\nlea 0x4(,%rax,4),%r8\nnopl 0x0(%rax,%rax,1)\ntest %ebx,%ebx\nje 1878 \nlea -0x1(%rbx),%ecx\nmov (%rdi,%rsi,1),%edx\nmov %r12,%rax\nlea (%r9,%rcx,4),%rcx\njmp 1831 \nnopl 0x0(%rax,%rax,1)\nadd $0x4,%rax\ncmp %rax,%rcx\nje 1878 \ncmp %edx,(%rax)\njne 1828 \nadd $0x4,%rsi\ncmp %rsi,%r8\njne 1810 \nadd $0x4,%r13\nadd $0x8,%r10\ncmp %r14,%r13\njne 17f0 \nmovslq %ebx,%rsi\nmov %r12,%rdi\nlea -0xd8(%rip),%rcx\nmov $0x4,%edx\ncallq 10a0 \nmov %ebx,0x0(%rbp)\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopl 0x0(%rax)\nmov (%rdi,%rsi,1),%edx\nmovslq %ebx,%rax\nadd $0x4,%rsi\nadd $0x1,%ebx\nmov %edx,(%r12,%rax,4)\ncmp %rsi,%r8\njne 1810 \njmp 183e \nxor %edi,%edi\nxor %ebx,%ebx\ncallq 10d0 \nxor %esi,%esi\nmov %rax,%r12\njmp 184e \n", + "ida_asm": "func0:\nendbr64\npush r15\nmovsxd r15, edx\npush r14\npush r13\npush r12\npush rbp\nmov rbp, rcx\npush rbx\nsub rsp, 8\ntest r15d, r15d\njle loc_177C\nmov r13, rdi\nmov r14, rsi\nmov rax, rsi\nxor edx, edx\nlea rcx, [rsi+r15*4]\nloc_16B0:\nadd edx, [rax]\nadd rax, 4\ncmp rax, rcx\njnz short loc_16B0\nmovsxd rdx, edx\nxor ebx, ebx\nlea rdi, ds:0[rdx*4]; size\ncall _malloc\nxor r10d, r10d\nmov r12, rax\nnop dword ptr [rax+rax+00h]\nloc_16D8:\nmovsxd rax, dword ptr [r14+r10*4]\ntest eax, eax\njle short loc_1726\nmov r9, [r13+r10*8+0]\nlea r8, ds:0[rax*4]\nmovsxd rdi, ebx\nxor esi, esi\nnop word ptr [rax+rax+00h]\nloc_16F8:\nmovsxd rax, ebx\nlea rcx, [r12+rax*4]\ntest ebx, ebx\njle short loc_1760\nloc_1703:\nmov edx, [r9+rsi]\nmov rax, r12\njmp short loc_1719\nloc_1710:\nadd rax, 4\ncmp rcx, rax\njz short loc_1760\nloc_1719:\ncmp [rax], edx\njnz short loc_1710\nadd rsi, 4\ncmp r8, rsi\njnz short loc_1703\nloc_1726:\nadd r10, 1\ncmp r15, r10\njnz short loc_16D8\nmovsxd rsi, ebx; nmemb\nloc_1732:\nmov rdi, r12; base\nlea rcx, cmpfunc; compar\nmov edx, 4; size\ncall _qsort\nmov [rbp+0], ebx\nadd rsp, 8\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1760:\nmov eax, [r9+rsi]\nadd rsi, 4\nadd ebx, 1\nmov [r12+rdi*4], eax\ncmp r8, rsi\njz short loc_1726\nmovsxd rdi, ebx\njmp loc_16F8\nloc_177C:\nxor edi, edi; size\nxor ebx, ebx\ncall _malloc\nxor esi, esi\nmov r12, rax\njmp short loc_1732", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, _DWORD *a2, int a3, int *a4)\n{\n __int64 v4; // r15\n _DWORD *v8; // rax\n int v9; // edx\n int v10; // ebx\n _DWORD *v11; // rax\n __int64 v12; // r10\n _DWORD *v13; // r12\n __int64 v14; // rax\n __int64 v15; // r9\n __int64 v16; // r8\n __int64 v17; // rdi\n __int64 v18; // rsi\n _DWORD *v19; // rax\n size_t v20; // rsi\n int v22; // eax\n\n v4 = a3;\n if ( a3 <= 0 )\n {\n v10 = 0;\n v20 = 0LL;\n v13 = malloc(0LL);\n }\n else\n {\n v8 = a2;\n v9 = 0;\n do\n v9 += *v8++;\n while ( v8 != &a2[v4] );\n v10 = 0;\n v11 = malloc(4LL * v9);\n v12 = 0LL;\n v13 = v11;\n do\n {\n v14 = (int)a2[v12];\n if ( (int)v14 > 0 )\n {\n v15 = *(_QWORD *)(a1 + 8 * v12);\n v16 = 4 * v14;\n v17 = v10;\n v18 = 0LL;\n while ( v10 <= 0 )\n {\nLABEL_15:\n v22 = *(_DWORD *)(v15 + v18);\n v18 += 4LL;\n ++v10;\n v13[v17] = v22;\n if ( v16 == v18 )\n goto LABEL_12;\n v17 = v10;\n }\n do\n {\n v19 = v13;\n while ( *v19 != *(_DWORD *)(v15 + v18) )\n {\n if ( &v13[v10] == ++v19 )\n goto LABEL_15;\n }\n v18 += 4LL;\n }\n while ( v16 != v18 );\n }\nLABEL_12:\n ++v12;\n }\n while ( v4 != v12 );\n v20 = v10;\n }\n qsort(v13, v20, 4uLL, cmpfunc);\n *a4 = v10;\n return v13;\n}", + "ida_strip_asm": "sub_1680:\nendbr64\npush r15\nmovsxd r15, edx\npush r14\npush r13\npush r12\npush rbp\nmov rbp, rcx\npush rbx\nsub rsp, 8\ntest r15d, r15d\njle loc_177C\nmov r13, rdi\nmov r14, rsi\nmov rax, rsi\nxor edx, edx\nlea rcx, [rsi+r15*4]\nloc_16B0:\nadd edx, [rax]\nadd rax, 4\ncmp rax, rcx\njnz short loc_16B0\nmovsxd rdx, edx\nxor ebx, ebx\nlea rdi, ds:0[rdx*4]; size\ncall _malloc\nxor r10d, r10d\nmov r12, rax\nnop dword ptr [rax+rax+00h]\nloc_16D8:\nmovsxd rax, dword ptr [r14+r10*4]\ntest eax, eax\njle short loc_1726\nmov r9, [r13+r10*8+0]\nlea r8, ds:0[rax*4]\nmovsxd rdi, ebx\nxor esi, esi\nnop word ptr [rax+rax+00h]\nloc_16F8:\nmovsxd rax, ebx\nlea rcx, [r12+rax*4]\ntest ebx, ebx\njle short loc_1760\nloc_1703:\nmov edx, [r9+rsi]\nmov rax, r12\njmp short loc_1719\nloc_1710:\nadd rax, 4\ncmp rcx, rax\njz short loc_1760\nloc_1719:\ncmp [rax], edx\njnz short loc_1710\nadd rsi, 4\ncmp r8, rsi\njnz short loc_1703\nloc_1726:\nadd r10, 1\ncmp r15, r10\njnz short loc_16D8\nmovsxd rsi, ebx; nmemb\nloc_1732:\nmov rdi, r12; base\nlea rcx, compar; compar\nmov edx, 4; size\ncall _qsort\nmov [rbp+0], ebx\nadd rsp, 8\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1760:\nmov eax, [r9+rsi]\nadd rsi, 4\nadd ebx, 1\nmov [r12+rdi*4], eax\ncmp r8, rsi\njz short loc_1726\nmovsxd rdi, ebx\njmp loc_16F8\nloc_177C:\nxor edi, edi; size\nxor ebx, ebx\ncall _malloc\nxor esi, esi\nmov r12, rax\njmp short loc_1732", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1680(__int64 a1, _DWORD *a2, int a3, int *a4)\n{\n __int64 v4; // r15\n _DWORD *v8; // rax\n int v9; // edx\n int v10; // ebx\n _DWORD *v11; // rax\n __int64 v12; // r10\n _DWORD *v13; // r12\n __int64 v14; // rax\n __int64 v15; // r9\n __int64 v16; // r8\n __int64 v17; // rdi\n __int64 v18; // rsi\n _DWORD *v19; // rax\n size_t v20; // rsi\n int v22; // eax\n\n v4 = a3;\n if ( a3 <= 0 )\n {\n v10 = 0;\n v20 = 0LL;\n v13 = malloc(0LL);\n }\n else\n {\n v8 = a2;\n v9 = 0;\n do\n v9 += *v8++;\n while ( v8 != &a2[v4] );\n v10 = 0;\n v11 = malloc(4LL * v9);\n v12 = 0LL;\n v13 = v11;\n do\n {\n v14 = (int)a2[v12];\n if ( (int)v14 > 0 )\n {\n v15 = *(_QWORD *)(a1 + 8 * v12);\n v16 = 4 * v14;\n v17 = v10;\n v18 = 0LL;\n while ( v10 <= 0 )\n {\nLABEL_15:\n v22 = *(_DWORD *)(v15 + v18);\n v18 += 4LL;\n ++v10;\n v13[v17] = v22;\n if ( v16 == v18 )\n goto LABEL_12;\n v17 = v10;\n }\n do\n {\n v19 = v13;\n while ( *v19 != *(_DWORD *)(v15 + v18) )\n {\n if ( &v13[v10] == ++v19 )\n goto LABEL_15;\n }\n v18 += 4LL;\n }\n while ( v16 != v18 );\n }\nLABEL_12:\n ++v12;\n }\n while ( v4 != v12 );\n v20 = v10;\n }\n qsort(v13, v20, 4uLL, compar);\n *a4 = v10;\n return v13;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1680(long long a1, uint32_t *a2, int a3, int *a4) {\n long long v4;\n uint32_t *v8;\n int v9;\n int v10;\n uint32_t *v11;\n long long v12;\n uint32_t *v13;\n long long v14;\n long long v15;\n long long v16;\n long long v17;\n long long v18;\n uint32_t *v19;\n unsigned int v20;\n int v22;\n v4 = a3;\n if (a3 <= 0) {\n v10 = 0;\n v20 = 0LL;\n v13 = malloc(0LL);\n } else {\n v8 = a2;\n v9 = 0;\n do\n v9 += *v8++;\n while (v8 != &a2[v4]);\n v10 = 0;\n v11 = malloc(4LL * v9);\n v12 = 0LL;\n v13 = v11;\n do {\n v14 = (int)a2[v12];\n if ((int)v14 > 0) {\n v15 = *(uint64_t *)(a1 + 8 * v12);\n v16 = 4 * v14;\n v17 = v10;\n v18 = 0LL;\n while (v10 <= 0) {\n LABEL_15:\n v22 = *(uint32_t *)(v15 + v18);\n v18 += 4LL;\n ++v10;\n v13[v17] = v22;\n if (v16 == v18) goto LABEL_12;\n v17 = v10;\n }\n do {\n v19 = v13;\n while (*v19 != *(uint32_t *)(v15 + v18)) {\n if (&v13[v10] == ++v19) goto LABEL_15;\n }\n v18 += 4LL;\n } while (v16 != v18);\n }\n LABEL_12:\n ++v12;\n } while (v4 != v12);\n v20 = v10;\n }\n qsort(v13, v20, 4uLL, compar);\n *a4 = v10;\n return v13;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, uint32_t *a2, int a3, int *a4) {\n long long v4;\n uint32_t *v8;\n int v9;\n int v10;\n uint32_t *v11;\n long long v12;\n uint32_t *v13;\n long long v14;\n long long v15;\n long long v16;\n long long v17;\n long long v18;\n uint32_t *v19;\n unsigned int v20;\n int v22;\n v4 = a3;\n if (a3 <= 0) {\n v10 = 0;\n v20 = 0LL;\n v13 = malloc(0LL);\n } else {\n v8 = a2;\n v9 = 0;\n do\n v9 += *v8++;\n while (v8 != &a2[v4]);\n v10 = 0;\n v11 = malloc(4LL * v9);\n v12 = 0LL;\n v13 = v11;\n do {\n v14 = (int)a2[v12];\n if ((int)v14 > 0) {\n v15 = *(uint64_t *)(a1 + 8 * v12);\n v16 = 4 * v14;\n v17 = v10;\n v18 = 0LL;\n while (v10 <= 0) {\n LABEL_15:\n v22 = *(uint32_t *)(v15 + v18);\n v18 += 4LL;\n ++v10;\n v13[v17] = v22;\n if (v16 == v18) goto LABEL_12;\n v17 = v10;\n }\n do {\n v19 = v13;\n while (*v19 != *(uint32_t *)(v15 + v18)) {\n if (&v13[v10] == ++v19) goto LABEL_15;\n }\n v18 += 4LL;\n } while (v16 != v18);\n }\n LABEL_12:\n ++v12;\n } while (v4 != v12);\n v20 = v10;\n }\n qsort(v13, v20, 4uLL, cmpfunc);\n *a4 = v10;\n return v13;\n}" + }, + { + "index": 694, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint cmpfunc(const void* a, const void* b) {\n\n return (*(int*)a - *(int*)b);\n\n}\n\n\n\n", + "func": "int* func0(int** arrs, int sizes[], int n, int* res_size) {\n int max_elements = 0;\n for (int i = 0; i < n; ++i) {\n max_elements += sizes[i];\n }\n int* buf = (int*)malloc(max_elements * sizeof(int));\n int buf_len = 0;\n for (int i = 0; i < n; ++i) {\n for (int j = 0; j < sizes[i]; ++j) {\n int should_add = 1;\n for (int k = 0; k < buf_len; ++k) {\n if (buf[k] == arrs[i][j]) {\n should_add = 0;\n break;\n }\n }\n if (should_add) {\n buf[buf_len++] = arrs[i][j];\n }\n }\n }\n qsort(buf, buf_len, sizeof(int), cmpfunc);\n *res_size = buf_len;\n return buf;\n}", + "test": "int main() {\n\n int arr1_1[] = {5, 6, 7, 8};\n\n int arr1_2[] = {10, 11, 7, 5};\n\n int arr1_3[] = {6, 12, 10, 8};\n\n int arr1_4[] = {1, 2, 5};\n\n int* arrs1[] = {arr1_1, arr1_2, arr1_3, arr1_4};\n\n int sizes1[] = {4, 4, 4, 3};\n\n int res_size1;\n\n int* result1 = func0(arrs1, sizes1, 4, &res_size1);\n\n int expected1[] = {1, 2, 5, 6, 7, 8, 10, 11, 12};\n\n assert(res_size1 == 9);\n\n for (int i = 0; i < res_size1; ++i) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n free(result1);\n\n\n\n int arr2_1[] = {7, 1, 9, 4};\n\n int arr2_2[] = {11, 21, 36, 14, 9};\n\n int arr2_3[] = {4, 1, 21, 39, 47};\n\n int arr2_4[] = {1, 32, 38};\n\n int* arrs2[] = {arr2_1, arr2_2, arr2_3, arr2_4};\n\n int sizes2[] = {4, 5, 5, 3};\n\n int res_size2;\n\n int* result2 = func0(arrs2, sizes2, 4, &res_size2);\n\n int expected2[] = {1, 4, 7, 9, 11, 14, 21, 32, 36, 38, 39, 47};\n\n assert(res_size2 == 12);\n\n for (int i = 0; i < res_size2; ++i) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n free(result2);\n\n\n\n int arr3_1[] = {11, 13, 14, 17};\n\n int arr3_2[] = {12, 11, 15, 18};\n\n int arr3_3[] = {19, 21, 15, 36};\n\n int arr3_4[] = {37, 36, 35};\n\n int* arrs3[] = {arr3_1, arr3_2, arr3_3, arr3_4};\n\n int sizes3[] = {4, 4, 4, 3};\n\n int res_size3;\n\n int* result3 = func0(arrs3, sizes3, 4, &res_size3);\n\n int expected3[] = {11, 12, 13, 14, 15, 17, 18, 19, 21, 35, 36, 37};\n\n assert(res_size3 == 12);\n\n for (int i = 0; i < res_size3; ++i) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\nmov %rcx,%rbp\npush %rbx\ntest %edx,%edx\njle 1940 \nlea -0x1(%rdx),%r14d\nmov %rsi,%r13\nmov %rdi,%rbx\nmov %edx,%esi\ncmp $0x3,%r14d\njbe 1950 \nshr $0x2,%edx\nmov %r13,%rax\npxor %xmm0,%xmm0\nshl $0x4,%rdx\nadd %r13,%rdx\nmovdqu (%rax),%xmm2\nadd $0x10,%rax\npaddd %xmm2,%xmm0\ncmp %rdx,%rax\njne 180e \nmovdqa %xmm0,%xmm1\nmov %esi,%edx\npsrldq $0x8,%xmm1\nand $0xfffffffc,%edx\npaddd %xmm1,%xmm0\nmovdqa %xmm0,%xmm1\npsrldq $0x4,%xmm1\npaddd %xmm1,%xmm0\nmovd %xmm0,%eax\ntest $0x3,%sil\nje 187d \nmovslq %edx,%rcx\nadd 0x0(%r13,%rcx,4),%eax\nlea 0x1(%rdx),%ecx\ncmp %ecx,%esi\njle 187d \nmovslq %ecx,%rcx\nadd 0x0(%r13,%rcx,4),%eax\nlea 0x2(%rdx),%ecx\ncmp %esi,%ecx\njge 187d \nmovslq %ecx,%rcx\nadd $0x3,%edx\nadd 0x0(%r13,%rcx,4),%eax\ncmp %esi,%edx\njge 187d \nmovslq %edx,%rdx\nadd 0x0(%r13,%rdx,4),%eax\ncltq\nmov %r14d,%r14d\nlea 0x0(,%rax,4),%rdi\ncallq 10d0 \nmov %r13,%r10\nmov %rbx,%r11\nlea 0x4(%r13,%r14,4),%r13\nmov %rax,%r12\nxor %ebx,%ebx\nlea 0x4(%rax),%r9\nnopl 0x0(%rax,%rax,1)\nmov (%r10),%eax\ntest %eax,%eax\njle 18ee \nsub $0x1,%eax\nmov (%r11),%rdi\nxor %esi,%esi\nlea 0x4(,%rax,4),%r8\ntest %ebx,%ebx\nje 1928 \nlea -0x1(%rbx),%ecx\nmov (%rdi,%rsi,1),%edx\nmov %r12,%rax\nlea (%r9,%rcx,4),%rcx\njmp 18e1 \nnopl 0x0(%rax,%rax,1)\nadd $0x4,%rax\ncmp %rcx,%rax\nje 1928 \ncmp %edx,(%rax)\njne 18d8 \nadd $0x4,%rsi\ncmp %r8,%rsi\njne 18c0 \nadd $0x4,%r10\nadd $0x8,%r11\ncmp %r13,%r10\njne 18a8 \nmovslq %ebx,%rsi\nmov %r12,%rdi\nlea -0x148(%rip),%rcx\nmov $0x4,%edx\ncallq 10a0 \nmov %ebx,0x0(%rbp)\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopl 0x0(%rax)\nmov (%rdi,%rsi,1),%edx\nmovslq %ebx,%rax\nadd $0x4,%rsi\nadd $0x1,%ebx\nmov %edx,(%r12,%rax,4)\ncmp %r8,%rsi\njne 18c0 \njmp 18ee \nxor %edi,%edi\nxor %ebx,%ebx\ncallq 10d0 \nxor %esi,%esi\nmov %rax,%r12\njmp 18fe \nxor %edx,%edx\nxor %eax,%eax\njmpq 1848 \nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\nmov rbp, rcx\npush rbx\ntest edx, edx\njle loc_17FF\nlea eax, [rdx-1]\nmov r13, rdi\nmov r14, rsi\nmov ebx, edx\ncmp eax, 2\njbe loc_180F\nshr edx, 2\nmov rax, rsi\npxor xmm0, xmm0\nshl rdx, 4\nadd rdx, rsi\nloc_16EC:\nmovdqu xmm2, xmmword ptr [rax]\nadd rax, 10h\npaddd xmm0, xmm2\ncmp rax, rdx\njnz short loc_16EC\nmovdqa xmm1, xmm0\nmov edx, ebx\npsrldq xmm1, 8\nand edx, 0FFFFFFFCh\npaddd xmm0, xmm1\nmovdqa xmm1, xmm0\npsrldq xmm1, 4\npaddd xmm0, xmm1\nmovd eax, xmm0\ntest bl, 3\njz short loc_174C\nloc_1725:\nmovsxd rsi, edx\nlea rcx, ds:0[rsi*4]\nadd eax, [r14+rsi*4]\nlea esi, [rdx+1]\ncmp ebx, esi\njle short loc_174C\nadd edx, 2\nadd eax, [r14+rcx+4]\ncmp ebx, edx\njle short loc_174C\nadd eax, [r14+rcx+8]\nloc_174C:\ncdqe\nlea rdi, ds:0[rax*4]; size\ncall _malloc\nmovsxd r10, ebx\nxor r9d, r9d\nxor ebx, ebx\nmov r12, rax\nnop word ptr [rax+rax+00000000h]\nloc_1770:\nmovsxd rax, dword ptr [r14+r9*4]\ntest eax, eax\njle short loc_17B6\nmov rsi, [r13+r9*8+0]\nmovsxd rdi, ebx\nlea r8, [rsi+rax*4]\nnop dword ptr [rax+00h]\nloc_1788:\nmovsxd rax, ebx\nlea rcx, [r12+rax*4]\ntest ebx, ebx\njle short loc_17E8\nloc_1793:\nmov edx, [rsi]\nmov rax, r12\njmp short loc_17A9\nloc_17A0:\nadd rax, 4\ncmp rcx, rax\njz short loc_17E8\nloc_17A9:\ncmp [rax], edx\njnz short loc_17A0\nadd rsi, 4\ncmp rsi, r8\njnz short loc_1793\nloc_17B6:\nadd r9, 1\ncmp r9, r10\njnz short loc_1770\nmovsxd rsi, ebx; nmemb\nloc_17C2:\nmov rdi, r12; base\nlea rcx, cmpfunc; compar\nmov edx, 4; size\ncall _qsort\nmov [rbp+0], ebx\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_17E8:\nmov eax, [rsi]\nadd rsi, 4\nadd ebx, 1\nmov [r12+rdi*4], eax\ncmp rsi, r8\njz short loc_17B6\nmovsxd rdi, ebx\njmp short loc_1788\nloc_17FF:\nxor edi, edi; size\nxor ebx, ebx\ncall _malloc\nxor esi, esi\nmov r12, rax\njmp short loc_17C2\nloc_180F:\nxor edx, edx\nxor eax, eax\njmp loc_1725", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, const __m128i *a2, int a3, int *a4)\n{\n const __m128i *v8; // rax\n __m128i v9; // xmm0\n const __m128i *v10; // rdx\n __m128i v11; // xmm2\n int v12; // edx\n __m128i v13; // xmm0\n int v14; // eax\n __int64 v15; // rcx\n _DWORD *v16; // rax\n __int64 v17; // r10\n __int64 v18; // r9\n int v19; // ebx\n _DWORD *v20; // r12\n __int64 v21; // rax\n int *v22; // rsi\n __int64 v23; // rdi\n int *v24; // r8\n _DWORD *v25; // rax\n size_t v26; // rsi\n int v28; // eax\n\n if ( a3 <= 0 )\n {\n v19 = 0;\n v26 = 0LL;\n v20 = malloc(0LL);\n goto LABEL_19;\n }\n if ( (unsigned int)(a3 - 1) <= 2 )\n {\n v12 = 0;\n v14 = 0;\n }\n else\n {\n v8 = a2;\n v9 = 0LL;\n v10 = &a2[(unsigned int)a3 >> 2];\n do\n {\n v11 = _mm_loadu_si128(v8++);\n v9 = _mm_add_epi32(v9, v11);\n }\n while ( v8 != v10 );\n v12 = a3 & 0x7FFFFFFC;\n v13 = _mm_add_epi32(v9, _mm_srli_si128(v9, 8));\n v14 = _mm_cvtsi128_si32(_mm_add_epi32(v13, _mm_srli_si128(v13, 4)));\n if ( (a3 & 3) == 0 )\n goto LABEL_9;\n }\n v15 = v12;\n v14 += a2->m128i_i32[v15];\n if ( a3 > v12 + 1 )\n {\n v14 += a2->m128i_i32[v15 + 1];\n if ( a3 > v12 + 2 )\n v14 += a2->m128i_i32[v15 + 2];\n }\nLABEL_9:\n v16 = malloc(4LL * v14);\n v17 = a3;\n v18 = 0LL;\n v19 = 0;\n v20 = v16;\n do\n {\n v21 = a2->m128i_i32[v18];\n if ( (int)v21 > 0 )\n {\n v22 = *(int **)(a1 + 8 * v18);\n v23 = v19;\n v24 = &v22[v21];\n while ( v19 <= 0 )\n {\nLABEL_20:\n v28 = *v22++;\n ++v19;\n v20[v23] = v28;\n if ( v22 == v24 )\n goto LABEL_17;\n v23 = v19;\n }\n do\n {\n v25 = v20;\n while ( *v25 != *v22 )\n {\n if ( &v20[v19] == ++v25 )\n goto LABEL_20;\n }\n ++v22;\n }\n while ( v22 != v24 );\n }\nLABEL_17:\n ++v18;\n }\n while ( v18 != v17 );\n v26 = v19;\nLABEL_19:\n qsort(v20, v26, 4uLL, cmpfunc);\n *a4 = v19;\n return v20;\n}", + "ida_strip_asm": "sub_16B0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\nmov rbp, rcx\npush rbx\ntest edx, edx\njle loc_17FF\nlea eax, [rdx-1]\nmov r13, rdi\nmov r14, rsi\nmov ebx, edx\ncmp eax, 2\njbe loc_180F\nshr edx, 2\nmov rax, rsi\npxor xmm0, xmm0\nshl rdx, 4\nadd rdx, rsi\nloc_16EC:\nmovdqu xmm2, xmmword ptr [rax]\nadd rax, 10h\npaddd xmm0, xmm2\ncmp rax, rdx\njnz short loc_16EC\nmovdqa xmm1, xmm0\nmov edx, ebx\npsrldq xmm1, 8\nand edx, 0FFFFFFFCh\npaddd xmm0, xmm1\nmovdqa xmm1, xmm0\npsrldq xmm1, 4\npaddd xmm0, xmm1\nmovd eax, xmm0\ntest bl, 3\njz short loc_174C\nloc_1725:\nmovsxd rsi, edx\nlea rcx, ds:0[rsi*4]\nadd eax, [r14+rsi*4]\nlea esi, [rdx+1]\ncmp ebx, esi\njle short loc_174C\nadd edx, 2\nadd eax, [r14+rcx+4]\ncmp ebx, edx\njle short loc_174C\nadd eax, [r14+rcx+8]\nloc_174C:\ncdqe\nlea rdi, ds:0[rax*4]; size\ncall _malloc\nmovsxd r10, ebx\nxor r9d, r9d\nxor ebx, ebx\nmov r12, rax\nnop word ptr [rax+rax+00000000h]\nloc_1770:\nmovsxd rax, dword ptr [r14+r9*4]\ntest eax, eax\njle short loc_17B6\nmov rsi, [r13+r9*8+0]\nmovsxd rdi, ebx\nlea r8, [rsi+rax*4]\nnop dword ptr [rax+00h]\nloc_1788:\nmovsxd rax, ebx\nlea rcx, [r12+rax*4]\ntest ebx, ebx\njle short loc_17E8\nloc_1793:\nmov edx, [rsi]\nmov rax, r12\njmp short loc_17A9\nloc_17A0:\nadd rax, 4\ncmp rcx, rax\njz short loc_17E8\nloc_17A9:\ncmp [rax], edx\njnz short loc_17A0\nadd rsi, 4\ncmp rsi, r8\njnz short loc_1793\nloc_17B6:\nadd r9, 1\ncmp r9, r10\njnz short loc_1770\nmovsxd rsi, ebx; nmemb\nloc_17C2:\nmov rdi, r12; base\nlea rcx, compar; compar\nmov edx, 4; size\ncall _qsort\nmov [rbp+0], ebx\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_17E8:\nmov eax, [rsi]\nadd rsi, 4\nadd ebx, 1\nmov [r12+rdi*4], eax\ncmp rsi, r8\njz short loc_17B6\nmovsxd rdi, ebx\njmp short loc_1788\nloc_17FF:\nxor edi, edi; size\nxor ebx, ebx\ncall _malloc\nxor esi, esi\nmov r12, rax\njmp short loc_17C2\nloc_180F:\nxor edx, edx\nxor eax, eax\njmp loc_1725", + "ida_strip_pseudo": "_DWORD *__fastcall sub_16B0(__int64 a1, const __m128i *a2, int a3, int *a4)\n{\n const __m128i *v8; // rax\n __m128i v9; // xmm0\n const __m128i *v10; // rdx\n __m128i v11; // xmm2\n int v12; // edx\n __m128i v13; // xmm0\n int v14; // eax\n __int64 v15; // rcx\n _DWORD *v16; // rax\n __int64 v17; // r10\n __int64 v18; // r9\n int v19; // ebx\n _DWORD *v20; // r12\n __int64 v21; // rax\n int *v22; // rsi\n __int64 v23; // rdi\n int *v24; // r8\n _DWORD *v25; // rax\n size_t v26; // rsi\n int v28; // eax\n\n if ( a3 <= 0 )\n {\n v19 = 0;\n v26 = 0LL;\n v20 = malloc(0LL);\n goto LABEL_19;\n }\n if ( (unsigned int)(a3 - 1) <= 2 )\n {\n v12 = 0;\n v14 = 0;\n }\n else\n {\n v8 = a2;\n v9 = 0LL;\n v10 = &a2[(unsigned int)a3 >> 2];\n do\n {\n v11 = _mm_loadu_si128(v8++);\n v9 = _mm_add_epi32(v9, v11);\n }\n while ( v8 != v10 );\n v12 = a3 & 0x7FFFFFFC;\n v13 = _mm_add_epi32(v9, _mm_srli_si128(v9, 8));\n v14 = _mm_cvtsi128_si32(_mm_add_epi32(v13, _mm_srli_si128(v13, 4)));\n if ( (a3 & 3) == 0 )\n goto LABEL_9;\n }\n v15 = v12;\n v14 += a2->m128i_i32[v15];\n if ( a3 > v12 + 1 )\n {\n v14 += a2->m128i_i32[v15 + 1];\n if ( a3 > v12 + 2 )\n v14 += a2->m128i_i32[v15 + 2];\n }\nLABEL_9:\n v16 = malloc(4LL * v14);\n v17 = a3;\n v18 = 0LL;\n v19 = 0;\n v20 = v16;\n do\n {\n v21 = a2->m128i_i32[v18];\n if ( (int)v21 > 0 )\n {\n v22 = *(int **)(a1 + 8 * v18);\n v23 = v19;\n v24 = &v22[v21];\n while ( v19 <= 0 )\n {\nLABEL_20:\n v28 = *v22++;\n ++v19;\n v20[v23] = v28;\n if ( v22 == v24 )\n goto LABEL_17;\n v23 = v19;\n }\n do\n {\n v25 = v20;\n while ( *v25 != *v22 )\n {\n if ( &v20[v19] == ++v25 )\n goto LABEL_20;\n }\n ++v22;\n }\n while ( v22 != v24 );\n }\nLABEL_17:\n ++v18;\n }\n while ( v18 != v17 );\n v26 = v19;\nLABEL_19:\n qsort(v20, v26, 4uLL, compar);\n *a4 = v19;\n return v20;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_16B0(long long a1, const __m128i *a2, int a3, int *a4) {\n const __m128i *v8;\n __m128i v9;\n const __m128i *v10;\n __m128i v11;\n int v12;\n __m128i v13;\n int v14;\n long long v15;\n uint32_t *v16;\n long long v17;\n long long v18;\n int v19;\n uint32_t *v20;\n long long v21;\n int *v22;\n long long v23;\n int *v24;\n uint32_t *v25;\n unsigned int v26;\n int v28;\n if (a3 <= 0) {\n v19 = 0;\n v26 = 0LL;\n v20 = malloc(0LL);\n goto LABEL_19;\n }\n if ((unsigned int)(a3 - 1) <= 2) {\n v12 = 0;\n v14 = 0;\n } else {\n v8 = a2;\n v9 = 0LL;\n v10 = &a2[(unsigned int)a3 >> 2];\n do {\n v11 = _mm_loadu_si128(v8++);\n v9 = _mm_add_epi32(v9, v11);\n } while (v8 != v10);\n v12 = a3 & 2147483644;\n v13 = _mm_add_epi32(v9, _mm_srli_si128(v9, 8));\n v14 = _mm_cvtsi128_si32(_mm_add_epi32(v13, _mm_srli_si128(v13, 4)));\n if ((a3 & 3) == 0) goto LABEL_9;\n }\n v15 = v12;\n v14 += a2->m128i_i32[v15];\n if (a3 > v12 + 1) {\n v14 += a2->m128i_i32[v15 + 1];\n if (a3 > v12 + 2) v14 += a2->m128i_i32[v15 + 2];\n }\nLABEL_9:\n v16 = malloc(4LL * v14);\n v17 = a3;\n v18 = 0LL;\n v19 = 0;\n v20 = v16;\n do {\n v21 = a2->m128i_i32[v18];\n if ((int)v21 > 0) {\n v22 = *(int **)(a1 + 8 * v18);\n v23 = v19;\n v24 = &v22[v21];\n while (v19 <= 0) {\n LABEL_20:\n v28 = *v22++;\n ++v19;\n v20[v23] = v28;\n if (v22 == v24) goto LABEL_17;\n v23 = v19;\n }\n do {\n v25 = v20;\n while (*v25 != *v22) {\n if (&v20[v19] == ++v25) goto LABEL_20;\n }\n ++v22;\n } while (v22 != v24);\n }\n LABEL_17:\n ++v18;\n } while (v18 != v17);\n v26 = v19;\nLABEL_19:\n qsort(v20, v26, 4uLL, compar);\n *a4 = v19;\n return v20;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, const __m128i *a2, int a3, int *a4) {\n const __m128i *v8;\n __m128i v9;\n const __m128i *v10;\n __m128i v11;\n int v12;\n __m128i v13;\n int v14;\n long long v15;\n uint32_t *v16;\n long long v17;\n long long v18;\n int v19;\n uint32_t *v20;\n long long v21;\n int *v22;\n long long v23;\n int *v24;\n uint32_t *v25;\n unsigned int v26;\n int v28;\n if (a3 <= 0) {\n v19 = 0;\n v26 = 0LL;\n v20 = malloc(0LL);\n goto LABEL_19;\n }\n if ((unsigned int)(a3 - 1) <= 2) {\n v12 = 0;\n v14 = 0;\n } else {\n v8 = a2;\n v9 = 0LL;\n v10 = &a2[(unsigned int)a3 >> 2];\n do {\n v11 = _mm_loadu_si128(v8++);\n v9 = _mm_add_epi32(v9, v11);\n } while (v8 != v10);\n v12 = a3 & 2147483644;\n v13 = _mm_add_epi32(v9, _mm_srli_si128(v9, 8));\n v14 = _mm_cvtsi128_si32(_mm_add_epi32(v13, _mm_srli_si128(v13, 4)));\n if ((a3 & 3) == 0) goto LABEL_9;\n }\n v15 = v12;\n v14 += a2->m128i_i32[v15];\n if (a3 > v12 + 1) {\n v14 += a2->m128i_i32[v15 + 1];\n if (a3 > v12 + 2) v14 += a2->m128i_i32[v15 + 2];\n }\nLABEL_9:\n v16 = malloc(4LL * v14);\n v17 = a3;\n v18 = 0LL;\n v19 = 0;\n v20 = v16;\n do {\n v21 = a2->m128i_i32[v18];\n if ((int)v21 > 0) {\n v22 = *(int **)(a1 + 8 * v18);\n v23 = v19;\n v24 = &v22[v21];\n while (v19 <= 0) {\n LABEL_20:\n v28 = *v22++;\n ++v19;\n v20[v23] = v28;\n if (v22 == v24) goto LABEL_17;\n v23 = v19;\n }\n do {\n v25 = v20;\n while (*v25 != *v22) {\n if (&v20[v19] == ++v25) goto LABEL_20;\n }\n ++v22;\n } while (v22 != v24);\n }\n LABEL_17:\n ++v18;\n } while (v18 != v17);\n v26 = v19;\nLABEL_19:\n qsort(v20, v26, 4uLL, cmpfunc);\n *a4 = v19;\n return v20;\n}" + }, + { + "index": 695, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int test_tup1[], int test_tup2[], int length) {\n for (int i = 0; i < length; i++) {\n if (!(test_tup1[i] < test_tup2[i])) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n int tuple1_1[] = {10, 4, 5};\n\n int tuple2_1[] = {13, 5, 18};\n\n assert(func0(tuple1_1, tuple2_1, 3) == true);\n\n\n\n int tuple1_2[] = {1, 2, 3};\n\n int tuple2_2[] = {2, 1, 4};\n\n assert(func0(tuple1_2, tuple2_2, 3) == false);\n\n\n\n int tuple1_3[] = {4, 5, 6};\n\n int tuple2_3[] = {5, 6, 7};\n\n assert(func0(tuple1_3, tuple2_3, 3) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %edx,-0x24(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11c0 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x20(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njl 11bc \nmov $0x0,%eax\njmp 11cd \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x24(%rbp),%eax\njl 1185 \nmov $0x1,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_4], 0\njmp short loc_11C0\nloc_1185:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njl short loc_11BC\nmov eax, 0\njmp short loc_11CD\nloc_11BC:\nadd [rbp+var_4], 1\nloc_11C0:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_24]\njl short loc_1185\nmov eax, 1\nloc_11CD:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n int i; // [rsp+20h] [rbp-4h]\n\n for ( i = 0; i < a3; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) >= *(_DWORD *)(4LL * i + a2) )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_4], 0\njmp short loc_11C0\nloc_1185:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njl short loc_11BC\nmov eax, 0\njmp short loc_11CD\nloc_11BC:\nadd [rbp+var_4], 1\nloc_11C0:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_24]\njl short loc_1185\nmov eax, 1\nloc_11CD:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, int a3)\n{\n int i; // [rsp+20h] [rbp-4h]\n\n for ( i = 0; i < a3; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) >= *(_DWORD *)(4LL * i + a2) )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, int a3) {\n int i;\n for (i = 0; i < a3; ++i) {\n if (*(uint32_t *)(4LL * i + a1) >= *(uint32_t *)(4LL * i + a2)) return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3) {\n int i;\n for (i = 0; i < a3; ++i) {\n if (*(uint32_t *)(4LL * i + a1) >= *(uint32_t *)(4LL * i + a2)) return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": 695, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int test_tup1[], int test_tup2[], int length) {\n for (int i = 0; i < length; i++) {\n if (!(test_tup1[i] < test_tup2[i])) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n int tuple1_1[] = {10, 4, 5};\n\n int tuple2_1[] = {13, 5, 18};\n\n assert(func0(tuple1_1, tuple2_1, 3) == true);\n\n\n\n int tuple1_2[] = {1, 2, 3};\n\n int tuple2_2[] = {2, 1, 4};\n\n assert(func0(tuple1_2, tuple2_2, 3) == false);\n\n\n\n int tuple1_3[] = {4, 5, 6};\n\n int tuple2_3[] = {5, 6, 7};\n\n assert(func0(tuple1_3, tuple2_3, 3) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edx,%edx\njle 1195 \nlea -0x1(%rdx),%ecx\nmov $0x0,%eax\njmp 117e \nmov %rdx,%rax\nmov (%rsi,%rax,4),%edx\ncmp %edx,(%rdi,%rax,4)\njge 119b \nlea 0x1(%rax),%rdx\ncmp %rcx,%rax\njne 117b \nmov $0x1,%eax\nretq\nmov $0x1,%eax\nretq\nmov $0x0,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest edx, edx\njle short loc_1194\nmovsxd rdx, edx\nshl rdx, 2\nmov eax, 0\nloc_117D:\nmov ecx, [rsi+rax]\ncmp [rdi+rax], ecx\njge short loc_119A\nadd rax, 4\ncmp rax, rdx\njnz short loc_117D\nmov eax, 1\nretn\nloc_1194:\nmov eax, 1\nretn\nloc_119A:\nmov eax, 0\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n __int64 v3; // rdx\n __int64 v4; // rax\n\n if ( a3 <= 0 )\n return 1LL;\n v3 = 4LL * a3;\n v4 = 0LL;\n while ( *(_DWORD *)(a1 + v4) < *(_DWORD *)(a2 + v4) )\n {\n v4 += 4LL;\n if ( v4 == v3 )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest edx, edx\njle short loc_1194\nmovsxd rdx, edx\nshl rdx, 2\nmov eax, 0\nloc_117D:\nmov ecx, [rsi+rax]\ncmp [rdi+rax], ecx\njge short loc_119A\nadd rax, 4\ncmp rax, rdx\njnz short loc_117D\nmov eax, 1\nretn\nloc_1194:\nmov eax, 1\nretn\nloc_119A:\nmov eax, 0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, int a3)\n{\n __int64 v3; // rdx\n __int64 v4; // rax\n\n if ( a3 <= 0 )\n return 1LL;\n v3 = 4LL * a3;\n v4 = 0LL;\n while ( *(_DWORD *)(a1 + v4) < *(_DWORD *)(a2 + v4) )\n {\n v4 += 4LL;\n if ( v4 == v3 )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, int a3) {\n long long v3;\n long long v4;\n if (a3 <= 0) return 1LL;\n v3 = 4LL * a3;\n v4 = 0LL;\n while (*(uint32_t *)(a1 + v4) < *(uint32_t *)(a2 + v4)) {\n v4 += 4LL;\n if (v4 == v3) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3) {\n long long v3;\n long long v4;\n if (a3 <= 0) return 1LL;\n v3 = 4LL * a3;\n v4 = 0LL;\n while (*(uint32_t *)(a1 + v4) < *(uint32_t *)(a2 + v4)) {\n v4 += 4LL;\n if (v4 == v3) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 696, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n// Function to zip integer lists\n\nint** zip_list_int(int** list1, int* sizes1, int** list2, int* sizes2, int n) {\n\n int** result = malloc(n * sizeof(int*));\n\n for(int i = 0; i < n; i++) {\n\n int new_size = sizes1[i] + sizes2[i];\n\n result[i] = malloc(new_size * sizeof(int));\n\n memcpy(result[i], list1[i], sizes1[i] * sizeof(int));\n\n memcpy(result[i] + sizes1[i], list2[i], sizes2[i] * sizeof(int));\n\n }\n\n return result;\n\n}\n\n\n\n// Function to zip character lists\n\nchar** zip_list_char(char** list1, int* sizes1, char** list2, int* sizes2, int n) {\n\n char** result = malloc(n * sizeof(char*));\n\n for(int i = 0; i < n; i++) {\n\n int new_size = sizes1[i] + sizes2[i];\n\n result[i] = malloc((new_size + 1) * sizeof(char));\n\n memcpy(result[i], list1[i], sizes1[i] * sizeof(char));\n\n memcpy(result[i] + sizes1[i], list2[i], sizes2[i] * sizeof(char));\n\n result[i][new_size] = '\\0';\n\n }\n\n return result;\n\n}\n\n\n\n\n\n// Helper function to compare character lists\n\nint compare_char_lists(char** a, int* sizes_a, char** b, int* sizes_b, int n) {\n\n for(int i = 0; i < n; i++) {\n\n if(sizes_a[i] != sizes_b[i]) return 0;\n\n if(memcmp(a[i], b[i], sizes_a[i] * sizeof(char)) != 0) return 0;\n\n }\n\n return 1;\n\n}\n\n\n\n// Helper function to compare integer lists\n\n", + "func": "int func0(int** a, int* sizes_a, int** b, int* sizes_b, int n) {\n for (int i = 0; i < n; i++) {\n if (sizes_a[i] != sizes_b[i]) return 0;\n if (memcmp(a[i], b[i], sizes_a[i] * sizeof(int)) != 0) return 0;\n }\n return 1;\n}", + "test": "int main() {\n\n // First assert\n\n int n1 = 3;\n\n int sizes1_a[] = {2, 2, 2};\n\n int sizes1_b[] = {2, 2, 3};\n\n int row1_a1[] = {1, 3};\n\n int row1_a2[] = {5, 7};\n\n int row1_a3[] = {9, 11};\n\n int* list1_a[] = {row1_a1, row1_a2, row1_a3};\n\n int row1_b1[] = {2, 4};\n\n int row1_b2[] = {6, 8};\n\n int row1_b3[] = {10, 12, 14};\n\n int* list1_b[] = {row1_b1, row1_b2, row1_b3};\n\n int** expected1 = malloc(n1 * sizeof(int*));\n\n int expected_sizes1[] = {4, 4, 5};\n\n int row1_e1[] = {1, 3, 2, 4};\n\n int row1_e2[] = {5, 7, 6, 8};\n\n int row1_e3[] = {9, 11, 10, 12, 14};\n\n expected1[0] = row1_e1;\n\n expected1[1] = row1_e2;\n\n expected1[2] = row1_e3;\n\n int** result1 = zip_list_int(list1_a, sizes1_a, list1_b, sizes1_b, n1);\n\n assert(func0(result1, expected1 ? expected_sizes1 : NULL, expected1, expected_sizes1, n1));\n\n\n\n // Second assert\n\n int n2 = 3;\n\n int sizes2_a[] = {2, 2, 2};\n\n int sizes2_b2[] = {2, 2, 2};\n\n int row2_a1[] = {1, 2};\n\n int row2_a2[] = {3, 4};\n\n int row2_a3[] = {5, 6};\n\n int* list2_a[] = {row2_a1, row2_a2, row2_a3};\n\n int row2_b1[] = {7, 8};\n\n int row2_b2[] = {9, 10};\n\n int row2_b3[] = {11, 12};\n\n int* list2_b[] = {row2_b1, row2_b2, row2_b3};\n\n int** expected2 = malloc(n2 * sizeof(int*));\n\n int expected_sizes2[] = {4, 4, 4};\n\n int row2_e1[] = {1, 2, 7, 8};\n\n int row2_e2[] = {3, 4, 9, 10};\n\n int row2_e3[] = {5, 6, 11, 12};\n\n expected2[0] = row2_e1;\n\n expected2[1] = row2_e2;\n\n expected2[2] = row2_e3;\n\n int** result2 = zip_list_int(list2_a, sizes2_a, list2_b, sizes2_b2, n2);\n\n assert(func0(result2, expected2 ? expected_sizes2 : NULL, expected2, expected_sizes2, n2));\n\n\n\n // Third assert\n\n int n3 = 2;\n\n int sizes3_a[] = {2, 2};\n\n int sizes3_b3[] = {2, 2};\n\n char row3_a1[] = {'a', 'b'};\n\n char row3_a2[] = {'c', 'd'};\n\n char* list3_a[] = {row3_a1, row3_a2};\n\n char row3_b1[] = {'e', 'f'};\n\n char row3_b2[] = {'g', 'h'};\n\n char* list3_b[] = {row3_b1, row3_b2};\n\n char** expected3 = malloc(n3 * sizeof(char*));\n\n int expected_sizes3[] = {4, 4};\n\n char row3_e1[] = {'a', 'b', 'e', 'f'};\n\n char row3_e2[] = {'c', 'd', 'g', 'h'};\n\n expected3[0] = row3_e1;\n\n expected3[1] = row3_e2;\n\n char** result3 = zip_list_char(list3_a, sizes3_a, list3_b, sizes3_b3, n3);\n\n assert(compare_char_lists(result3, expected_sizes3, expected3, expected_sizes3, n3));\n\n\n\n printf(\"All assertions passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x40,%rsp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %rcx,-0x30(%rbp)\nmov %r8d,-0x34(%rbp)\nmovl $0x0,-0x4(%rbp)\njmpq 16b2 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x30(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\nje 164a \nmov $0x0,%eax\njmp 16c3 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%rcx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rsi\nmov -0x18(%rbp),%rax\nadd %rsi,%rax\nmov (%rax),%rax\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 10d0 \ntest %eax,%eax\nje 16ae \nmov $0x0,%eax\njmp 16c3 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x34(%rbp),%eax\njl 1613 \nmov $0x1,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_28], rdx\nmov [rbp+var_30], rcx\nmov [rbp+var_34], r8d\nmov [rbp+var_4], 0\njmp loc_16B0\nloc_1611:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_30]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_1648\nmov eax, 0\njmp short locret_16C1\nloc_1648:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]; n\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov rcx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rsi, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rsi\nmov rax, [rax]\nmov rsi, rcx; s2\nmov rdi, rax; s1\ncall _memcmp\ntest eax, eax\njz short loc_16AC\nmov eax, 0\njmp short locret_16C1\nloc_16AC:\nadd [rbp+var_4], 1\nloc_16B0:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_34]\njl loc_1611\nmov eax, 1\nlocret_16C1:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, __int64 a3, __int64 a4, int a5)\n{\n int i; // [rsp+3Ch] [rbp-4h]\n\n for ( i = 0; i < a5; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a2) != *(_DWORD *)(4LL * i + a4) )\n return 0LL;\n if ( memcmp(*(const void **)(8LL * i + a1), *(const void **)(8LL * i + a3), 4LL * *(int *)(4LL * i + a2)) )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_15E5:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_28], rdx\nmov [rbp+var_30], rcx\nmov [rbp+var_34], r8d\nmov [rbp+var_4], 0\njmp loc_16B0\nloc_1611:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_30]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_1648\nmov eax, 0\njmp short locret_16C1\nloc_1648:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]; n\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov rcx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rsi, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rsi\nmov rax, [rax]\nmov rsi, rcx; s2\nmov rdi, rax; s1\ncall _memcmp\ntest eax, eax\njz short loc_16AC\nmov eax, 0\njmp short locret_16C1\nloc_16AC:\nadd [rbp+var_4], 1\nloc_16B0:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_34]\njl loc_1611\nmov eax, 1\nlocret_16C1:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_15E5(__int64 a1, __int64 a2, __int64 a3, __int64 a4, int a5)\n{\n int i; // [rsp+3Ch] [rbp-4h]\n\n for ( i = 0; i < a5; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a2) != *(_DWORD *)(4LL * i + a4) )\n return 0LL;\n if ( memcmp(*(const void **)(8LL * i + a1), *(const void **)(8LL * i + a3), 4LL * *(int *)(4LL * i + a2)) )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_15E5(long long a1, long long a2, long long a3, long long a4,\n int a5) {\n int i;\n for (i = 0; i < a5; ++i) {\n if (*(uint32_t *)(4LL * i + a2) != *(uint32_t *)(4LL * i + a4)) return 0LL;\n if (memcmp(*(const void **)(8LL * i + a1), *(const void **)(8LL * i + a3),\n 4LL * *(int *)(4LL * i + a2)))\n return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, long long a3, long long a4,\n int a5) {\n int i;\n for (i = 0; i < a5; ++i) {\n if (*(uint32_t *)(4LL * i + a2) != *(uint32_t *)(4LL * i + a4)) return 0LL;\n if (memcmp(*(const void **)(8LL * i + a1), *(const void **)(8LL * i + a3),\n 4LL * *(int *)(4LL * i + a2)))\n return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": 696, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n// Function to zip integer lists\n\nint** zip_list_int(int** list1, int* sizes1, int** list2, int* sizes2, int n) {\n\n int** result = malloc(n * sizeof(int*));\n\n for(int i = 0; i < n; i++) {\n\n int new_size = sizes1[i] + sizes2[i];\n\n result[i] = malloc(new_size * sizeof(int));\n\n memcpy(result[i], list1[i], sizes1[i] * sizeof(int));\n\n memcpy(result[i] + sizes1[i], list2[i], sizes2[i] * sizeof(int));\n\n }\n\n return result;\n\n}\n\n\n\n// Function to zip character lists\n\nchar** zip_list_char(char** list1, int* sizes1, char** list2, int* sizes2, int n) {\n\n char** result = malloc(n * sizeof(char*));\n\n for(int i = 0; i < n; i++) {\n\n int new_size = sizes1[i] + sizes2[i];\n\n result[i] = malloc((new_size + 1) * sizeof(char));\n\n memcpy(result[i], list1[i], sizes1[i] * sizeof(char));\n\n memcpy(result[i] + sizes1[i], list2[i], sizes2[i] * sizeof(char));\n\n result[i][new_size] = '\\0';\n\n }\n\n return result;\n\n}\n\n\n\n\n\n// Helper function to compare character lists\n\nint compare_char_lists(char** a, int* sizes_a, char** b, int* sizes_b, int n) {\n\n for(int i = 0; i < n; i++) {\n\n if(sizes_a[i] != sizes_b[i]) return 0;\n\n if(memcmp(a[i], b[i], sizes_a[i] * sizeof(char)) != 0) return 0;\n\n }\n\n return 1;\n\n}\n\n\n\n// Helper function to compare integer lists\n\n", + "func": "int func0(int** a, int* sizes_a, int** b, int* sizes_b, int n) {\n for (int i = 0; i < n; i++) {\n if (sizes_a[i] != sizes_b[i]) return 0;\n if (memcmp(a[i], b[i], sizes_a[i] * sizeof(int)) != 0) return 0;\n }\n return 1;\n}", + "test": "int main() {\n\n // First assert\n\n int n1 = 3;\n\n int sizes1_a[] = {2, 2, 2};\n\n int sizes1_b[] = {2, 2, 3};\n\n int row1_a1[] = {1, 3};\n\n int row1_a2[] = {5, 7};\n\n int row1_a3[] = {9, 11};\n\n int* list1_a[] = {row1_a1, row1_a2, row1_a3};\n\n int row1_b1[] = {2, 4};\n\n int row1_b2[] = {6, 8};\n\n int row1_b3[] = {10, 12, 14};\n\n int* list1_b[] = {row1_b1, row1_b2, row1_b3};\n\n int** expected1 = malloc(n1 * sizeof(int*));\n\n int expected_sizes1[] = {4, 4, 5};\n\n int row1_e1[] = {1, 3, 2, 4};\n\n int row1_e2[] = {5, 7, 6, 8};\n\n int row1_e3[] = {9, 11, 10, 12, 14};\n\n expected1[0] = row1_e1;\n\n expected1[1] = row1_e2;\n\n expected1[2] = row1_e3;\n\n int** result1 = zip_list_int(list1_a, sizes1_a, list1_b, sizes1_b, n1);\n\n assert(func0(result1, expected1 ? expected_sizes1 : NULL, expected1, expected_sizes1, n1));\n\n\n\n // Second assert\n\n int n2 = 3;\n\n int sizes2_a[] = {2, 2, 2};\n\n int sizes2_b2[] = {2, 2, 2};\n\n int row2_a1[] = {1, 2};\n\n int row2_a2[] = {3, 4};\n\n int row2_a3[] = {5, 6};\n\n int* list2_a[] = {row2_a1, row2_a2, row2_a3};\n\n int row2_b1[] = {7, 8};\n\n int row2_b2[] = {9, 10};\n\n int row2_b3[] = {11, 12};\n\n int* list2_b[] = {row2_b1, row2_b2, row2_b3};\n\n int** expected2 = malloc(n2 * sizeof(int*));\n\n int expected_sizes2[] = {4, 4, 4};\n\n int row2_e1[] = {1, 2, 7, 8};\n\n int row2_e2[] = {3, 4, 9, 10};\n\n int row2_e3[] = {5, 6, 11, 12};\n\n expected2[0] = row2_e1;\n\n expected2[1] = row2_e2;\n\n expected2[2] = row2_e3;\n\n int** result2 = zip_list_int(list2_a, sizes2_a, list2_b, sizes2_b2, n2);\n\n assert(func0(result2, expected2 ? expected_sizes2 : NULL, expected2, expected_sizes2, n2));\n\n\n\n // Third assert\n\n int n3 = 2;\n\n int sizes3_a[] = {2, 2};\n\n int sizes3_b3[] = {2, 2};\n\n char row3_a1[] = {'a', 'b'};\n\n char row3_a2[] = {'c', 'd'};\n\n char* list3_a[] = {row3_a1, row3_a2};\n\n char row3_b1[] = {'e', 'f'};\n\n char row3_b2[] = {'g', 'h'};\n\n char* list3_b[] = {row3_b1, row3_b2};\n\n char** expected3 = malloc(n3 * sizeof(char*));\n\n int expected_sizes3[] = {4, 4};\n\n char row3_e1[] = {'a', 'b', 'e', 'f'};\n\n char row3_e2[] = {'c', 'd', 'g', 'h'};\n\n expected3[0] = row3_e1;\n\n expected3[1] = row3_e2;\n\n char** result3 = zip_list_char(list3_a, sizes3_a, list3_b, sizes3_b3, n3);\n\n assert(compare_char_lists(result3, expected_sizes3, expected3, expected_sizes3, n3));\n\n\n\n printf(\"All assertions passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %r8d,%r8d\njle 1455 \npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%r13\nmov %rsi,%rbp\nmov %rdx,%r14\nmov %rcx,%r12\nlea -0x1(%r8),%r15d\nmov $0x0,%ebx\njmp 1422 \nmov %rax,%rbx\nmov 0x0(%rbp,%rbx,4),%edx\ncmp (%r12,%rbx,4),%edx\njne 145b \nmovslq %edx,%rdx\nshl $0x2,%rdx\nmov (%r14,%rbx,8),%rsi\nmov 0x0(%r13,%rbx,8),%rdi\ncallq 10d0 \ntest %eax,%eax\njne 146f \nlea 0x1(%rbx),%rax\ncmp %r15,%rbx\njne 141f \nmov $0x1,%eax\njmp 1460 \nmov $0x1,%eax\nretq\nmov $0x0,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmov $0x0,%eax\njmp 1460 \n", + "ida_asm": "func0:\nendbr64\ntest r8d, r8d\njle short loc_14B0\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r14, rdi\nmov r12, rsi\nmov r15, rdx\nmov r13, rcx\nmovsxd r8, r8d\nlea rbp, ds:0[r8*4]\nmov ebx, 0\nloc_147D:\nmov edx, [r12+rbx]\ncmp edx, [r13+rbx+0]\njnz short loc_14B6\nmovsxd rdx, edx\nshl rdx, 2; n\nmov rsi, [r15+rbx*2]; s2\nmov rdi, [r14+rbx*2]; s1\ncall _memcmp\ntest eax, eax\njnz short loc_14CA\nadd rbx, 4\ncmp rbx, rbp\njnz short loc_147D\nmov eax, 1\njmp short loc_14BB\nloc_14B0:\nmov eax, 1\nretn\nloc_14B6:\nmov eax, 0\nloc_14BB:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14CA:\nmov eax, 0\njmp short loc_14BB", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, __int64 a3, __int64 a4, int a5)\n{\n __int64 v7; // rbp\n __int64 v8; // rbx\n int v9; // edx\n\n if ( a5 <= 0 )\n return 1LL;\n v7 = 4LL * a5;\n v8 = 0LL;\n while ( 1 )\n {\n v9 = *(_DWORD *)(a2 + v8);\n if ( v9 != *(_DWORD *)(a4 + v8) )\n return 0LL;\n if ( memcmp(*(const void **)(a1 + 2 * v8), *(const void **)(a3 + 2 * v8), 4LL * v9) )\n break;\n v8 += 4LL;\n if ( v8 == v7 )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_144A:\nendbr64\ntest r8d, r8d\njle short loc_14B0\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r14, rdi\nmov r12, rsi\nmov r15, rdx\nmov r13, rcx\nmovsxd r8, r8d\nlea rbp, ds:0[r8*4]\nmov ebx, 0\nloc_147D:\nmov edx, [r12+rbx]\ncmp edx, [r13+rbx+0]\njnz short loc_14B6\nmovsxd rdx, edx\nshl rdx, 2; n\nmov rsi, [r15+rbx*2]; s2\nmov rdi, [r14+rbx*2]; s1\ncall _memcmp\ntest eax, eax\njnz short loc_14CA\nadd rbx, 4\ncmp rbx, rbp\njnz short loc_147D\nmov eax, 1\njmp short loc_14BB\nloc_14B0:\nmov eax, 1\nretn\nloc_14B6:\nmov eax, 0\nloc_14BB:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14CA:\nmov eax, 0\njmp short loc_14BB", + "ida_strip_pseudo": "__int64 __fastcall sub_144A(__int64 a1, __int64 a2, __int64 a3, __int64 a4, int a5)\n{\n __int64 v7; // rbp\n __int64 v8; // rbx\n int v9; // edx\n\n if ( a5 <= 0 )\n return 1LL;\n v7 = 4LL * a5;\n v8 = 0LL;\n while ( 1 )\n {\n v9 = *(_DWORD *)(a2 + v8);\n if ( v9 != *(_DWORD *)(a4 + v8) )\n return 0LL;\n if ( memcmp(*(const void **)(a1 + 2 * v8), *(const void **)(a3 + 2 * v8), 4LL * v9) )\n break;\n v8 += 4LL;\n if ( v8 == v7 )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_144A(long long a1, long long a2, long long a3, long long a4,\n int a5) {\n long long v7;\n long long v8;\n int v9;\n if (a5 <= 0) return 1LL;\n v7 = 4LL * a5;\n v8 = 0LL;\n while (1) {\n v9 = *(uint32_t *)(a2 + v8);\n if (v9 != *(uint32_t *)(a4 + v8)) return 0LL;\n if (memcmp(*(const void **)(a1 + 2 * v8), *(const void **)(a3 + 2 * v8),\n 4LL * v9))\n break;\n v8 += 4LL;\n if (v8 == v7) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, long long a3, long long a4,\n int a5) {\n long long v7;\n long long v8;\n int v9;\n if (a5 <= 0) return 1LL;\n v7 = 4LL * a5;\n v8 = 0LL;\n while (1) {\n v9 = *(uint32_t *)(a2 + v8);\n if (v9 != *(uint32_t *)(a4 + v8)) return 0LL;\n if (memcmp(*(const void **)(a1 + 2 * v8), *(const void **)(a3 + 2 * v8),\n 4LL * v9))\n break;\n v8 += 4LL;\n if (v8 == v7) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 696, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n// Function to zip integer lists\n\nint** zip_list_int(int** list1, int* sizes1, int** list2, int* sizes2, int n) {\n\n int** result = malloc(n * sizeof(int*));\n\n for(int i = 0; i < n; i++) {\n\n int new_size = sizes1[i] + sizes2[i];\n\n result[i] = malloc(new_size * sizeof(int));\n\n memcpy(result[i], list1[i], sizes1[i] * sizeof(int));\n\n memcpy(result[i] + sizes1[i], list2[i], sizes2[i] * sizeof(int));\n\n }\n\n return result;\n\n}\n\n\n\n// Function to zip character lists\n\nchar** zip_list_char(char** list1, int* sizes1, char** list2, int* sizes2, int n) {\n\n char** result = malloc(n * sizeof(char*));\n\n for(int i = 0; i < n; i++) {\n\n int new_size = sizes1[i] + sizes2[i];\n\n result[i] = malloc((new_size + 1) * sizeof(char));\n\n memcpy(result[i], list1[i], sizes1[i] * sizeof(char));\n\n memcpy(result[i] + sizes1[i], list2[i], sizes2[i] * sizeof(char));\n\n result[i][new_size] = '\\0';\n\n }\n\n return result;\n\n}\n\n\n\n\n\n// Helper function to compare character lists\n\nint compare_char_lists(char** a, int* sizes_a, char** b, int* sizes_b, int n) {\n\n for(int i = 0; i < n; i++) {\n\n if(sizes_a[i] != sizes_b[i]) return 0;\n\n if(memcmp(a[i], b[i], sizes_a[i] * sizeof(char)) != 0) return 0;\n\n }\n\n return 1;\n\n}\n\n\n\n// Helper function to compare integer lists\n\n", + "func": "int func0(int** a, int* sizes_a, int** b, int* sizes_b, int n) {\n for (int i = 0; i < n; i++) {\n if (sizes_a[i] != sizes_b[i]) return 0;\n if (memcmp(a[i], b[i], sizes_a[i] * sizeof(int)) != 0) return 0;\n }\n return 1;\n}", + "test": "int main() {\n\n // First assert\n\n int n1 = 3;\n\n int sizes1_a[] = {2, 2, 2};\n\n int sizes1_b[] = {2, 2, 3};\n\n int row1_a1[] = {1, 3};\n\n int row1_a2[] = {5, 7};\n\n int row1_a3[] = {9, 11};\n\n int* list1_a[] = {row1_a1, row1_a2, row1_a3};\n\n int row1_b1[] = {2, 4};\n\n int row1_b2[] = {6, 8};\n\n int row1_b3[] = {10, 12, 14};\n\n int* list1_b[] = {row1_b1, row1_b2, row1_b3};\n\n int** expected1 = malloc(n1 * sizeof(int*));\n\n int expected_sizes1[] = {4, 4, 5};\n\n int row1_e1[] = {1, 3, 2, 4};\n\n int row1_e2[] = {5, 7, 6, 8};\n\n int row1_e3[] = {9, 11, 10, 12, 14};\n\n expected1[0] = row1_e1;\n\n expected1[1] = row1_e2;\n\n expected1[2] = row1_e3;\n\n int** result1 = zip_list_int(list1_a, sizes1_a, list1_b, sizes1_b, n1);\n\n assert(func0(result1, expected1 ? expected_sizes1 : NULL, expected1, expected_sizes1, n1));\n\n\n\n // Second assert\n\n int n2 = 3;\n\n int sizes2_a[] = {2, 2, 2};\n\n int sizes2_b2[] = {2, 2, 2};\n\n int row2_a1[] = {1, 2};\n\n int row2_a2[] = {3, 4};\n\n int row2_a3[] = {5, 6};\n\n int* list2_a[] = {row2_a1, row2_a2, row2_a3};\n\n int row2_b1[] = {7, 8};\n\n int row2_b2[] = {9, 10};\n\n int row2_b3[] = {11, 12};\n\n int* list2_b[] = {row2_b1, row2_b2, row2_b3};\n\n int** expected2 = malloc(n2 * sizeof(int*));\n\n int expected_sizes2[] = {4, 4, 4};\n\n int row2_e1[] = {1, 2, 7, 8};\n\n int row2_e2[] = {3, 4, 9, 10};\n\n int row2_e3[] = {5, 6, 11, 12};\n\n expected2[0] = row2_e1;\n\n expected2[1] = row2_e2;\n\n expected2[2] = row2_e3;\n\n int** result2 = zip_list_int(list2_a, sizes2_a, list2_b, sizes2_b2, n2);\n\n assert(func0(result2, expected2 ? expected_sizes2 : NULL, expected2, expected_sizes2, n2));\n\n\n\n // Third assert\n\n int n3 = 2;\n\n int sizes3_a[] = {2, 2};\n\n int sizes3_b3[] = {2, 2};\n\n char row3_a1[] = {'a', 'b'};\n\n char row3_a2[] = {'c', 'd'};\n\n char* list3_a[] = {row3_a1, row3_a2};\n\n char row3_b1[] = {'e', 'f'};\n\n char row3_b2[] = {'g', 'h'};\n\n char* list3_b[] = {row3_b1, row3_b2};\n\n char** expected3 = malloc(n3 * sizeof(char*));\n\n int expected_sizes3[] = {4, 4};\n\n char row3_e1[] = {'a', 'b', 'e', 'f'};\n\n char row3_e2[] = {'c', 'd', 'g', 'h'};\n\n expected3[0] = row3_e1;\n\n expected3[1] = row3_e2;\n\n char** result3 = zip_list_char(list3_a, sizes3_a, list3_b, sizes3_b3, n3);\n\n assert(compare_char_lists(result3, expected_sizes3, expected3, expected_sizes3, n3));\n\n\n\n printf(\"All assertions passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %r8d,%r8d\njle 19f4 \npush %r15\nmov %rdx,%r15\npush %r14\nmov %rdi,%r14\npush %r13\nxor %r13d,%r13d\npush %r12\nlea -0x1(%r8),%r12d\npush %rbp\nmov %rcx,%rbp\npush %rbx\nmov %rsi,%rbx\nsub $0x8,%rsp\njmp 19c1 \nnopl 0x0(%rax)\nmov (%r15,%r13,8),%rsi\nmov (%r14,%r13,8),%rdi\nshl $0x2,%rdx\ncallq 10d0 \ntest %eax,%eax\njne 19cc \nlea 0x1(%r13),%rax\ncmp %r12,%r13\nje 19e0 \nmov %rax,%r13\nmovslq (%rbx,%r13,4),%rdx\ncmp 0x0(%rbp,%r13,4),%edx\nje 19a0 \nadd $0x8,%rsp\nxor %eax,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl (%rax)\nadd $0x8,%rsp\nmov $0x1,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmov $0x1,%eax\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest r8d, r8d\njle loc_1AA4\npush r15\nmovsxd r8, r8d\nmov r15, rdx\npush r14\nmov r14, rdi\npush r13\nmov r13, rcx\npush r12\nmov r12, rsi\npush rbp\nlea rbp, ds:0[r8*4]\npush rbx\nxor ebx, ebx\nsub rsp, 8\njmp short loc_1A6E\nloc_1A50:\nmov rsi, [r15+rbx*2]; s2\nmov rdi, [r14+rbx*2]; s1\nshl rdx, 2; n\ncall _memcmp\ntest eax, eax\njnz short loc_1A79\nadd rbx, 4\ncmp rbp, rbx\njz short loc_1A90\nloc_1A6E:\nmovsxd rdx, dword ptr [r12+rbx]\ncmp edx, [r13+rbx+0]\njz short loc_1A50\nloc_1A79:\nadd rsp, 8\nxor eax, eax\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1A90:\nadd rsp, 8\nmov eax, 1\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1AA4:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, __int64 a3, __int64 a4, int a5)\n{\n __int64 v7; // rbp\n __int64 v8; // rbx\n __int64 v9; // rdx\n\n if ( a5 <= 0 )\n return 1LL;\n v7 = 4LL * a5;\n v8 = 0LL;\n do\n {\n v9 = *(int *)(a2 + v8);\n if ( (_DWORD)v9 != *(_DWORD *)(a4 + v8)\n || memcmp(*(const void **)(a1 + 2 * v8), *(const void **)(a3 + 2 * v8), 4 * v9) )\n {\n return 0LL;\n }\n v8 += 4LL;\n }\n while ( v7 != v8 );\n return 1LL;\n}", + "ida_strip_asm": "sub_1A10:\nendbr64\ntest r8d, r8d\njle loc_1AA4\npush r15\nmovsxd r8, r8d\nmov r15, rdx\npush r14\nmov r14, rdi\npush r13\nmov r13, rcx\npush r12\nmov r12, rsi\npush rbp\nlea rbp, ds:0[r8*4]\npush rbx\nxor ebx, ebx\nsub rsp, 8\njmp short loc_1A6E\nloc_1A50:\nmov rsi, [r15+rbx*2]; s2\nmov rdi, [r14+rbx*2]; s1\nshl rdx, 2; n\ncall _memcmp\ntest eax, eax\njnz short loc_1A79\nadd rbx, 4\ncmp rbp, rbx\njz short loc_1A90\nloc_1A6E:\nmovsxd rdx, dword ptr [r12+rbx]\ncmp edx, [r13+rbx+0]\njz short loc_1A50\nloc_1A79:\nadd rsp, 8\nxor eax, eax\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1A90:\nadd rsp, 8\nmov eax, 1\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1AA4:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1A10(__int64 a1, __int64 a2, __int64 a3, __int64 a4, int a5)\n{\n __int64 v7; // rbp\n __int64 v8; // rbx\n __int64 v9; // rdx\n\n if ( a5 <= 0 )\n return 1LL;\n v7 = 4LL * a5;\n v8 = 0LL;\n do\n {\n v9 = *(int *)(a2 + v8);\n if ( (_DWORD)v9 != *(_DWORD *)(a4 + v8)\n || memcmp(*(const void **)(a1 + 2 * v8), *(const void **)(a3 + 2 * v8), 4 * v9) )\n {\n return 0LL;\n }\n v8 += 4LL;\n }\n while ( v7 != v8 );\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1A10(long long a1, long long a2, long long a3, long long a4,\n int a5) {\n long long v7;\n long long v8;\n long long v9;\n if (a5 <= 0) return 1LL;\n v7 = 4LL * a5;\n v8 = 0LL;\n do {\n v9 = *(int *)(a2 + v8);\n if ((uint32_t)v9 != *(uint32_t *)(a4 + v8) ||\n memcmp(*(const void **)(a1 + 2 * v8), *(const void **)(a3 + 2 * v8),\n 4 * v9)) {\n return 0LL;\n }\n v8 += 4LL;\n } while (v7 != v8);\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, long long a3, long long a4,\n int a5) {\n long long v7;\n long long v8;\n long long v9;\n if (a5 <= 0) return 1LL;\n v7 = 4LL * a5;\n v8 = 0LL;\n do {\n v9 = *(int *)(a2 + v8);\n if ((uint32_t)v9 != *(uint32_t *)(a4 + v8) ||\n memcmp(*(const void **)(a1 + 2 * v8), *(const void **)(a3 + 2 * v8),\n 4 * v9)) {\n return 0LL;\n }\n v8 += 4LL;\n } while (v7 != v8);\n return 1LL;\n}" + }, + { + "index": 696, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n// Function to zip integer lists\n\nint** zip_list_int(int** list1, int* sizes1, int** list2, int* sizes2, int n) {\n\n int** result = malloc(n * sizeof(int*));\n\n for(int i = 0; i < n; i++) {\n\n int new_size = sizes1[i] + sizes2[i];\n\n result[i] = malloc(new_size * sizeof(int));\n\n memcpy(result[i], list1[i], sizes1[i] * sizeof(int));\n\n memcpy(result[i] + sizes1[i], list2[i], sizes2[i] * sizeof(int));\n\n }\n\n return result;\n\n}\n\n\n\n// Function to zip character lists\n\nchar** zip_list_char(char** list1, int* sizes1, char** list2, int* sizes2, int n) {\n\n char** result = malloc(n * sizeof(char*));\n\n for(int i = 0; i < n; i++) {\n\n int new_size = sizes1[i] + sizes2[i];\n\n result[i] = malloc((new_size + 1) * sizeof(char));\n\n memcpy(result[i], list1[i], sizes1[i] * sizeof(char));\n\n memcpy(result[i] + sizes1[i], list2[i], sizes2[i] * sizeof(char));\n\n result[i][new_size] = '\\0';\n\n }\n\n return result;\n\n}\n\n\n\n\n\n// Helper function to compare character lists\n\nint compare_char_lists(char** a, int* sizes_a, char** b, int* sizes_b, int n) {\n\n for(int i = 0; i < n; i++) {\n\n if(sizes_a[i] != sizes_b[i]) return 0;\n\n if(memcmp(a[i], b[i], sizes_a[i] * sizeof(char)) != 0) return 0;\n\n }\n\n return 1;\n\n}\n\n\n\n// Helper function to compare integer lists\n\n", + "func": "int func0(int** a, int* sizes_a, int** b, int* sizes_b, int n) {\n for (int i = 0; i < n; i++) {\n if (sizes_a[i] != sizes_b[i]) return 0;\n if (memcmp(a[i], b[i], sizes_a[i] * sizeof(int)) != 0) return 0;\n }\n return 1;\n}", + "test": "int main() {\n\n // First assert\n\n int n1 = 3;\n\n int sizes1_a[] = {2, 2, 2};\n\n int sizes1_b[] = {2, 2, 3};\n\n int row1_a1[] = {1, 3};\n\n int row1_a2[] = {5, 7};\n\n int row1_a3[] = {9, 11};\n\n int* list1_a[] = {row1_a1, row1_a2, row1_a3};\n\n int row1_b1[] = {2, 4};\n\n int row1_b2[] = {6, 8};\n\n int row1_b3[] = {10, 12, 14};\n\n int* list1_b[] = {row1_b1, row1_b2, row1_b3};\n\n int** expected1 = malloc(n1 * sizeof(int*));\n\n int expected_sizes1[] = {4, 4, 5};\n\n int row1_e1[] = {1, 3, 2, 4};\n\n int row1_e2[] = {5, 7, 6, 8};\n\n int row1_e3[] = {9, 11, 10, 12, 14};\n\n expected1[0] = row1_e1;\n\n expected1[1] = row1_e2;\n\n expected1[2] = row1_e3;\n\n int** result1 = zip_list_int(list1_a, sizes1_a, list1_b, sizes1_b, n1);\n\n assert(func0(result1, expected1 ? expected_sizes1 : NULL, expected1, expected_sizes1, n1));\n\n\n\n // Second assert\n\n int n2 = 3;\n\n int sizes2_a[] = {2, 2, 2};\n\n int sizes2_b2[] = {2, 2, 2};\n\n int row2_a1[] = {1, 2};\n\n int row2_a2[] = {3, 4};\n\n int row2_a3[] = {5, 6};\n\n int* list2_a[] = {row2_a1, row2_a2, row2_a3};\n\n int row2_b1[] = {7, 8};\n\n int row2_b2[] = {9, 10};\n\n int row2_b3[] = {11, 12};\n\n int* list2_b[] = {row2_b1, row2_b2, row2_b3};\n\n int** expected2 = malloc(n2 * sizeof(int*));\n\n int expected_sizes2[] = {4, 4, 4};\n\n int row2_e1[] = {1, 2, 7, 8};\n\n int row2_e2[] = {3, 4, 9, 10};\n\n int row2_e3[] = {5, 6, 11, 12};\n\n expected2[0] = row2_e1;\n\n expected2[1] = row2_e2;\n\n expected2[2] = row2_e3;\n\n int** result2 = zip_list_int(list2_a, sizes2_a, list2_b, sizes2_b2, n2);\n\n assert(func0(result2, expected2 ? expected_sizes2 : NULL, expected2, expected_sizes2, n2));\n\n\n\n // Third assert\n\n int n3 = 2;\n\n int sizes3_a[] = {2, 2};\n\n int sizes3_b3[] = {2, 2};\n\n char row3_a1[] = {'a', 'b'};\n\n char row3_a2[] = {'c', 'd'};\n\n char* list3_a[] = {row3_a1, row3_a2};\n\n char row3_b1[] = {'e', 'f'};\n\n char row3_b2[] = {'g', 'h'};\n\n char* list3_b[] = {row3_b1, row3_b2};\n\n char** expected3 = malloc(n3 * sizeof(char*));\n\n int expected_sizes3[] = {4, 4};\n\n char row3_e1[] = {'a', 'b', 'e', 'f'};\n\n char row3_e2[] = {'c', 'd', 'g', 'h'};\n\n expected3[0] = row3_e1;\n\n expected3[1] = row3_e2;\n\n char** result3 = zip_list_char(list3_a, sizes3_a, list3_b, sizes3_b3, n3);\n\n assert(compare_char_lists(result3, expected_sizes3, expected3, expected_sizes3, n3));\n\n\n\n printf(\"All assertions passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ntest %r8d,%r8d\njle 19f4 \npush %r15\nmov %rdx,%r15\npush %r14\nmov %rdi,%r14\npush %r13\nxor %r13d,%r13d\npush %r12\nlea -0x1(%r8),%r12d\npush %rbp\nmov %rcx,%rbp\npush %rbx\nmov %rsi,%rbx\nsub $0x8,%rsp\njmp 19c1 \nnopl 0x0(%rax)\nmov (%r15,%r13,8),%rsi\nmov (%r14,%r13,8),%rdi\nshl $0x2,%rdx\ncallq 10d0 \ntest %eax,%eax\njne 19cc \nlea 0x1(%r13),%rax\ncmp %r13,%r12\nje 19e0 \nmov %rax,%r13\nmovslq (%rbx,%r13,4),%rdx\ncmp 0x0(%rbp,%r13,4),%edx\nje 19a0 \nadd $0x8,%rsp\nxor %eax,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl (%rax)\nadd $0x8,%rsp\nmov $0x1,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmov $0x1,%eax\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest r8d, r8d\njle loc_1AA4\npush r15\nmovsxd r8, r8d\nmov r15, rdx\npush r14\nmov r14, rdi\npush r13\nmov r13, rcx\npush r12\nmov r12, rsi\npush rbp\nlea rbp, ds:0[r8*4]\npush rbx\nxor ebx, ebx\nsub rsp, 8\njmp short loc_1A6E\nloc_1A50:\nmov rsi, [r15+rbx*2]; s2\nmov rdi, [r14+rbx*2]; s1\nshl rdx, 2; n\ncall _memcmp\ntest eax, eax\njnz short loc_1A79\nadd rbx, 4\ncmp rbp, rbx\njz short loc_1A90\nloc_1A6E:\nmovsxd rdx, dword ptr [r12+rbx]\ncmp edx, [r13+rbx+0]\njz short loc_1A50\nloc_1A79:\nadd rsp, 8\nxor eax, eax\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1A90:\nadd rsp, 8\nmov eax, 1\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1AA4:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, __int64 a3, __int64 a4, int a5)\n{\n __int64 v7; // rbp\n __int64 v8; // rbx\n __int64 v9; // rdx\n\n if ( a5 <= 0 )\n return 1LL;\n v7 = 4LL * a5;\n v8 = 0LL;\n do\n {\n v9 = *(int *)(a2 + v8);\n if ( (_DWORD)v9 != *(_DWORD *)(a4 + v8)\n || memcmp(*(const void **)(a1 + 2 * v8), *(const void **)(a3 + 2 * v8), 4 * v9) )\n {\n return 0LL;\n }\n v8 += 4LL;\n }\n while ( v7 != v8 );\n return 1LL;\n}", + "ida_strip_asm": "sub_1A10:\nendbr64\ntest r8d, r8d\njle loc_1AA4\npush r15\nmovsxd r8, r8d\nmov r15, rdx\npush r14\nmov r14, rdi\npush r13\nmov r13, rcx\npush r12\nmov r12, rsi\npush rbp\nlea rbp, ds:0[r8*4]\npush rbx\nxor ebx, ebx\nsub rsp, 8\njmp short loc_1A6E\nloc_1A50:\nmov rsi, [r15+rbx*2]; s2\nmov rdi, [r14+rbx*2]; s1\nshl rdx, 2; n\ncall _memcmp\ntest eax, eax\njnz short loc_1A79\nadd rbx, 4\ncmp rbp, rbx\njz short loc_1A90\nloc_1A6E:\nmovsxd rdx, dword ptr [r12+rbx]\ncmp edx, [r13+rbx+0]\njz short loc_1A50\nloc_1A79:\nadd rsp, 8\nxor eax, eax\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1A90:\nadd rsp, 8\nmov eax, 1\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1AA4:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1A10(__int64 a1, __int64 a2, __int64 a3, __int64 a4, int a5)\n{\n __int64 v7; // rbp\n __int64 v8; // rbx\n __int64 v9; // rdx\n\n if ( a5 <= 0 )\n return 1LL;\n v7 = 4LL * a5;\n v8 = 0LL;\n do\n {\n v9 = *(int *)(a2 + v8);\n if ( (_DWORD)v9 != *(_DWORD *)(a4 + v8)\n || memcmp(*(const void **)(a1 + 2 * v8), *(const void **)(a3 + 2 * v8), 4 * v9) )\n {\n return 0LL;\n }\n v8 += 4LL;\n }\n while ( v7 != v8 );\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1A10(long long a1, long long a2, long long a3, long long a4,\n int a5) {\n long long v7;\n long long v8;\n long long v9;\n if (a5 <= 0) return 1LL;\n v7 = 4LL * a5;\n v8 = 0LL;\n do {\n v9 = *(int *)(a2 + v8);\n if ((uint32_t)v9 != *(uint32_t *)(a4 + v8) ||\n memcmp(*(const void **)(a1 + 2 * v8), *(const void **)(a3 + 2 * v8),\n 4 * v9)) {\n return 0LL;\n }\n v8 += 4LL;\n } while (v7 != v8);\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, long long a3, long long a4,\n int a5) {\n long long v7;\n long long v8;\n long long v9;\n if (a5 <= 0) return 1LL;\n v7 = 4LL * a5;\n v8 = 0LL;\n do {\n v9 = *(int *)(a2 + v8);\n if ((uint32_t)v9 != *(uint32_t *)(a4 + v8) ||\n memcmp(*(const void **)(a1 + 2 * v8), *(const void **)(a3 + 2 * v8),\n 4 * v9)) {\n return 0LL;\n }\n v8 += 4LL;\n } while (v7 != v8);\n return 1LL;\n}" + }, + { + "index": 697, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int array_nums[], int size) {\n int count_even = 0;\n for (int i = 0; i < size; i++) {\n if (array_nums[i] % 2 == 0) {\n count_even++;\n }\n }\n return count_even;\n}", + "test": "int main() {\n\n int array1[] = {1, 2, 3, 5, 7, 8, 9, 10};\n\n int size1 = sizeof(array1) / sizeof(array1[0]);\n\n assert(func0(array1, size1) == 3);\n\n \n\n int array2[] = {10, 15, 14, 13, -18, 12, -20};\n\n int size2 = sizeof(array2) / sizeof(array2[0]);\n\n assert(func0(array2, size2) == 5);\n\n \n\n int array3[] = {1, 2, 4, 8, 9};\n\n int size3 = sizeof(array3) / sizeof(array3[0]);\n\n assert(func0(array3, size3) == 3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11ad \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nand $0x1,%eax\ntest %eax,%eax\njne 11a9 \naddl $0x1,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1188 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11AD\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njnz short loc_11A9\nadd [rbp+var_8], 1\nloc_11A9:\nadd [rbp+var_4], 1\nloc_11AD:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( (*(_DWORD *)(4LL * i + a1) & 1) == 0 )\n ++v3;\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11AD\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njnz short loc_11A9\nadd [rbp+var_8], 1\nloc_11A9:\nadd [rbp+var_4], 1\nloc_11AD:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( (*(_DWORD *)(4LL * i + a1) & 1) == 0 )\n ++v3;\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n if ((*(uint32_t *)(4LL * i + a1) & 1) == 0) ++v3;\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n if ((*(uint32_t *)(4LL * i + a1) & 1) == 0) ++v3;\n }\n return v3;\n}" + }, + { + "index": 697, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int array_nums[], int size) {\n int count_even = 0;\n for (int i = 0; i < size; i++) {\n if (array_nums[i] % 2 == 0) {\n count_even++;\n }\n }\n return count_even;\n}", + "test": "int main() {\n\n int array1[] = {1, 2, 3, 5, 7, 8, 9, 10};\n\n int size1 = sizeof(array1) / sizeof(array1[0]);\n\n assert(func0(array1, size1) == 3);\n\n \n\n int array2[] = {10, 15, 14, 13, -18, 12, -20};\n\n int size2 = sizeof(array2) / sizeof(array2[0]);\n\n assert(func0(array2, size2) == 5);\n\n \n\n int array3[] = {1, 2, 4, 8, 9};\n\n int size3 = sizeof(array3) / sizeof(array3[0]);\n\n assert(func0(array3, size3) == 3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1198 \nmov %rdi,%rax\nlea -0x1(%rsi),%edx\nlea 0x4(%rdi,%rdx,4),%rsi\nmov $0x0,%ecx\nmov (%rax),%edx\nand $0x1,%edx\ncmp $0x1,%edx\nadc $0x0,%ecx\nadd $0x4,%rax\ncmp %rsi,%rax\njne 1181 \nmov %ecx,%eax\nretq\nmov $0x0,%ecx\njmp 1195 \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1197\nmov rax, rdi\nmovsxd rsi, esi\nlea rsi, [rdi+rsi*4]\nmov ecx, 0\nloc_1180:\nmov edx, [rax]\nand edx, 1\ncmp edx, 1\nadc ecx, 0\nadd rax, 4\ncmp rax, rsi\njnz short loc_1180\nloc_1194:\nmov eax, ecx\nretn\nloc_1197:\nmov ecx, 0\njmp short loc_1194", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n _DWORD *v3; // rsi\n unsigned int v4; // ecx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n v4 += (*v2++ & 1) == 0;\n while ( v2 != v3 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_1197\nmov rax, rdi\nmovsxd rsi, esi\nlea rsi, [rdi+rsi*4]\nmov ecx, 0\nloc_1180:\nmov edx, [rax]\nand edx, 1\ncmp edx, 1\nadc ecx, 0\nadd rax, 4\ncmp rax, rsi\njnz short loc_1180\nloc_1194:\nmov eax, ecx\nretn\nloc_1197:\nmov ecx, 0\njmp short loc_1194", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n _DWORD *v3; // rsi\n unsigned int v4; // ecx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n v4 += (*v2++ & 1) == 0;\n while ( v2 != v3 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2) {\n uint32_t *v2;\n uint32_t *v3;\n unsigned int v4;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n v4 += (*v2++ & 1) == 0;\n while (v2 != v3);\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n uint32_t *v3;\n unsigned int v4;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n v4 += (*v2++ & 1) == 0;\n while (v2 != v3);\n }\n return v4;\n}" + }, + { + "index": 698, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int key1;\n\n int key2;\n\n int value;\n\n} dictItem;\n\n\n\nint compare(const void *a, const void *b) {\n\n dictItem *itemA = (dictItem *)a;\n\n dictItem *itemB = (dictItem *)b;\n\n int mulA = itemA->key1 * itemA->key2;\n\n int mulB = itemB->key1 * itemB->key2;\n\n return mulA - mulB;\n\n}\n\n\n\n", + "func": "dictItem* func0(dictItem arr[], int size) {\n qsort(arr, size, sizeof(dictItem), compare);\n return arr;\n}", + "test": "int main() {\n\n dictItem arr1[] = {{5, 6, 3}, {2, 3, 9}, {8, 4, 10}, {6, 4, 12}};\n\n dictItem sorted1[] = {{2, 3, 9}, {6, 4, 12}, {5, 6, 3}, {8, 4, 10}};\n\n func0(arr1, 4);\n\n for (int i = 0; i < 4; i++) {\n\n assert(arr1[i].key1 == sorted1[i].key1 && arr1[i].key2 == sorted1[i].key2 && arr1[i].value == sorted1[i].value);\n\n }\n\n\n\n dictItem arr2[] = {{6, 7, 4}, {3, 4, 10}, {9, 5, 11}, {7, 5, 13}};\n\n dictItem sorted2[] = {{3, 4, 10}, {7, 5, 13}, {6, 7, 4}, {9, 5, 11}};\n\n func0(arr2, 4);\n\n for (int i = 0; i < 4; i++) {\n\n assert(arr2[i].key1 == sorted2[i].key1 && arr2[i].key2 == sorted2[i].key2 && arr2[i].value == sorted2[i].value);\n\n }\n\n \n\n dictItem arr3[] = {{7, 8, 5}, {4, 5, 11}, {10, 6, 12}, {8, 6, 14}};\n\n dictItem sorted3[] = {{4, 5, 11}, {8, 6, 14}, {7, 8, 5}, {10, 6, 12}};\n\n func0(arr3, 4);\n\n for (int i = 0; i < 4; i++) {\n\n assert(arr3[i].key1 == sorted3[i].key1 && arr3[i].key2 == sorted3[i].key2 && arr3[i].value == sorted3[i].value);\n\n }\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %rdi,-0x8(%rbp)\nmov %esi,-0xc(%rbp)\nmov -0xc(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x8(%rbp),%rax\nlea -0x72(%rip),%rcx\nmov $0xc,%edx\nmov %rax,%rdi\ncallq 1070 \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+base], rdi\nmov [rbp+var_C], esi\nmov eax, [rbp+var_C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compare\nmov rcx, rdx; compar\nmov edx, 0Ch; size\nmov rdi, rax; base\ncall _qsort\nmov rax, [rbp+base]\nleave\nretn", + "ida_pseudo": "void *__fastcall func0(void *a1, int a2)\n{\n qsort(a1, a2, 0xCuLL, compare);\n return a1;\n}", + "ida_strip_asm": "sub_11D7:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+base], rdi\nmov [rbp+var_C], esi\nmov eax, [rbp+var_C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 0Ch; size\nmov rdi, rax; base\ncall _qsort\nmov rax, [rbp+base]\nleave\nretn", + "ida_strip_pseudo": "void *__fastcall sub_11D7(void *a1, int a2)\n{\n qsort(a1, a2, 0xCuLL, compar);\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_11D7(void *a1, int a2) {\n qsort(a1, a2, 12uLL, compar);\n return a1;\n}", + "ida_pseudo_norm": "void *func0(void *a1, int a2) {\n qsort(a1, a2, 12uLL, compare);\n return a1;\n}" + }, + { + "index": 698, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int key1;\n\n int key2;\n\n int value;\n\n} dictItem;\n\n\n\nint compare(const void *a, const void *b) {\n\n dictItem *itemA = (dictItem *)a;\n\n dictItem *itemB = (dictItem *)b;\n\n int mulA = itemA->key1 * itemA->key2;\n\n int mulB = itemB->key1 * itemB->key2;\n\n return mulA - mulB;\n\n}\n\n\n\n", + "func": "dictItem* func0(dictItem arr[], int size) {\n qsort(arr, size, sizeof(dictItem), compare);\n return arr;\n}", + "test": "int main() {\n\n dictItem arr1[] = {{5, 6, 3}, {2, 3, 9}, {8, 4, 10}, {6, 4, 12}};\n\n dictItem sorted1[] = {{2, 3, 9}, {6, 4, 12}, {5, 6, 3}, {8, 4, 10}};\n\n func0(arr1, 4);\n\n for (int i = 0; i < 4; i++) {\n\n assert(arr1[i].key1 == sorted1[i].key1 && arr1[i].key2 == sorted1[i].key2 && arr1[i].value == sorted1[i].value);\n\n }\n\n\n\n dictItem arr2[] = {{6, 7, 4}, {3, 4, 10}, {9, 5, 11}, {7, 5, 13}};\n\n dictItem sorted2[] = {{3, 4, 10}, {7, 5, 13}, {6, 7, 4}, {9, 5, 11}};\n\n func0(arr2, 4);\n\n for (int i = 0; i < 4; i++) {\n\n assert(arr2[i].key1 == sorted2[i].key1 && arr2[i].key2 == sorted2[i].key2 && arr2[i].value == sorted2[i].value);\n\n }\n\n \n\n dictItem arr3[] = {{7, 8, 5}, {4, 5, 11}, {10, 6, 12}, {8, 6, 14}};\n\n dictItem sorted3[] = {{4, 5, 11}, {8, 6, 14}, {7, 8, 5}, {10, 6, 12}};\n\n func0(arr3, 4);\n\n for (int i = 0; i < 4; i++) {\n\n assert(arr3[i].key1 == sorted3[i].key1 && arr3[i].key2 == sorted3[i].key2 && arr3[i].value == sorted3[i].value);\n\n }\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\nmovslq %esi,%rsi\nlea -0x25(%rip),%rcx\nmov $0xc,%edx\ncallq 1070 \nmov %rbx,%rax\npop %rbx\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\nmovsxd rsi, esi; nmemb\nlea rcx, compare; compar\nmov edx, 0Ch; size\ncall _qsort\nmov rax, rbx\npop rbx\nretn", + "ida_pseudo": "void *__fastcall func0(void *a1, int a2)\n{\n qsort(a1, a2, 0xCuLL, compare);\n return a1;\n}", + "ida_strip_asm": "sub_119C:\nendbr64\npush rbx\nmov rbx, rdi\nmovsxd rsi, esi; nmemb\nlea rcx, compar; compar\nmov edx, 0Ch; size\ncall _qsort\nmov rax, rbx\npop rbx\nretn", + "ida_strip_pseudo": "void *__fastcall sub_119C(void *a1, int a2)\n{\n qsort(a1, a2, 0xCuLL, compar);\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_119C(void *a1, int a2) {\n qsort(a1, a2, 12uLL, compar);\n return a1;\n}", + "ida_pseudo_norm": "void *func0(void *a1, int a2) {\n qsort(a1, a2, 12uLL, compare);\n return a1;\n}" + }, + { + "index": 699, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(const char* str1, const char* str2) {\n int count = 0;\n int length = strlen(str1);\n for (int i = 0; i < length; i++) {\n if (str1[i] != str2[i]) {\n count++;\n }\n }\n if (count % 2 == 0) {\n return (count / 2);\n } else {\n return -1;\n }\n}", + "test": "int main() {\n\n assert(func0(\"1101\", \"1110\") == 1);\n\n assert(func0(\"1111\", \"0100\") == -1);\n\n assert(func0(\"1110000\", \"0001101\") == 3);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmovl $0x0,-0xc(%rbp)\nmov -0x18(%rbp),%rax\nmov %rax,%rdi\ncallq 1060 \nmov %eax,-0x4(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11c8 \nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%edx\nmov -0x8(%rbp),%eax\nmovslq %eax,%rcx\nmov -0x20(%rbp),%rax\nadd %rcx,%rax\nmovzbl (%rax),%eax\ncmp %al,%dl\nje 11c4 \naddl $0x1,-0xc(%rbp)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x4(%rbp),%eax\njl 119c \nmov -0xc(%rbp),%eax\nand $0x1,%eax\ntest %eax,%eax\njne 11e8 \nmov -0xc(%rbp),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\njmp 11ed \nmov $0xffffffff,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_C], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_8], 0\njmp short loc_11C8\nloc_119C:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_8]\nmovsxd rcx, eax\nmov rax, [rbp+var_20]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njz short loc_11C4\nadd [rbp+var_C], 1\nloc_11C4:\nadd [rbp+var_8], 1\nloc_11C8:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njl short loc_119C\nmov eax, [rbp+var_C]\nand eax, 1\ntest eax, eax\njnz short loc_11E8\nmov eax, [rbp+var_C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\njmp short locret_11ED\nloc_11E8:\nmov eax, 0FFFFFFFFh\nlocret_11ED:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, __int64 a2)\n{\n int v3; // [rsp+14h] [rbp-Ch]\n int i; // [rsp+18h] [rbp-8h]\n int v5; // [rsp+1Ch] [rbp-4h]\n\n v3 = 0;\n v5 = strlen(a1);\n for ( i = 0; i < v5; ++i )\n {\n if ( a1[i] != *(_BYTE *)(i + a2) )\n ++v3;\n }\n if ( (v3 & 1) != 0 )\n return 0xFFFFFFFFLL;\n else\n return (unsigned int)(v3 / 2);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_C], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_8], 0\njmp short loc_11C8\nloc_119C:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_8]\nmovsxd rcx, eax\nmov rax, [rbp+var_20]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njz short loc_11C4\nadd [rbp+var_C], 1\nloc_11C4:\nadd [rbp+var_8], 1\nloc_11C8:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njl short loc_119C\nmov eax, [rbp+var_C]\nand eax, 1\ntest eax, eax\njnz short loc_11E8\nmov eax, [rbp+var_C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\njmp short locret_11ED\nloc_11E8:\nmov eax, 0FFFFFFFFh\nlocret_11ED:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1, __int64 a2)\n{\n int v3; // [rsp+14h] [rbp-Ch]\n int i; // [rsp+18h] [rbp-8h]\n int v5; // [rsp+1Ch] [rbp-4h]\n\n v3 = 0;\n v5 = strlen(a1);\n for ( i = 0; i < v5; ++i )\n {\n if ( a1[i] != *(_BYTE *)(i + a2) )\n ++v3;\n }\n if ( (v3 & 1) != 0 )\n return 0xFFFFFFFFLL;\n else\n return (unsigned int)(v3 / 2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1, long long a2) {\n int v3;\n int i;\n int v5;\n v3 = 0;\n v5 = strlen(a1);\n for (i = 0; i < v5; ++i) {\n if (a1[i] != *(uint8_t *)(i + a2)) ++v3;\n }\n if ((v3 & 1) != 0)\n return 4294967295LL;\n else\n return (unsigned int)(v3 / 2);\n}", + "ida_pseudo_norm": "long long func0(const char *a1, long long a2) {\n int v3;\n int i;\n int v5;\n v3 = 0;\n v5 = strlen(a1);\n for (i = 0; i < v5; ++i) {\n if (a1[i] != *(uint8_t *)(i + a2)) ++v3;\n }\n if ((v3 & 1) != 0)\n return 4294967295LL;\n else\n return (unsigned int)(v3 / 2);\n}" + }, + { + "index": 699, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(const char* str1, const char* str2) {\n int count = 0;\n int length = strlen(str1);\n for (int i = 0; i < length; i++) {\n if (str1[i] != str2[i]) {\n count++;\n }\n }\n if (count % 2 == 0) {\n return (count / 2);\n } else {\n return -1;\n }\n}", + "test": "int main() {\n\n assert(func0(\"1101\", \"1110\") == 1);\n\n assert(func0(\"1111\", \"0100\") == -1);\n\n assert(func0(\"1110000\", \"0001101\") == 3);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%r8\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nsub $0x1,%rcx\ntest %ecx,%ecx\njle 11a3 \nlea -0x1(%rcx),%edi\nmov $0x0,%eax\nmov $0x0,%edx\njmp 117b \nmov %rcx,%rax\nmovzbl (%rsi,%rax,1),%ecx\ncmp %cl,(%r8,%rax,1)\nsetne %cl\nmovzbl %cl,%ecx\nadd %ecx,%edx\nlea 0x1(%rax),%rcx\ncmp %rdi,%rax\njne 1178 \ntest $0x1,%dl\njne 11aa \nmov %edx,%eax\nshr $0x1f,%eax\nadd %edx,%eax\nsar %eax\nretq\nmov $0x0,%edx\njmp 1199 \nmov $0xffffffff,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov rbp, rsi\ncall _strlen\ntest eax, eax\njle short loc_11C2\nlea esi, [rax-1]\nmov eax, 0\nmov ecx, 0\njmp short loc_119D\nloc_1191:\nlea rdx, [rax+1]\ncmp rax, rsi\njz short loc_11AD\nmov rax, rdx\nloc_119D:\nmovzx edi, byte ptr [rbp+rax+0]\ncmp [rbx+rax], dil\njz short loc_1191\nadd ecx, 1\njmp short loc_1191\nloc_11AD:\ntest cl, 1\njnz short loc_11C9\nloc_11B2:\nmov eax, ecx\nshr eax, 1Fh\nadd eax, ecx\nsar eax, 1\nloc_11BB:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_11C2:\nmov ecx, 0\njmp short loc_11B2\nloc_11C9:\nmov eax, 0FFFFFFFFh\njmp short loc_11BB", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, __int64 a2)\n{\n int v3; // eax\n __int64 v4; // rsi\n __int64 v5; // rax\n int v6; // ecx\n\n v3 = strlen(a1);\n if ( v3 <= 0 )\n {\n v6 = 0;\n return (unsigned int)(v6 / 2);\n }\n v4 = (unsigned int)(v3 - 1);\n v5 = 0LL;\n v6 = 0;\n while ( 1 )\n {\n if ( a1[v5] != *(_BYTE *)(a2 + v5) )\n ++v6;\n if ( v5 == v4 )\n break;\n ++v5;\n }\n if ( (v6 & 1) == 0 )\n return (unsigned int)(v6 / 2);\n return 0xFFFFFFFFLL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov rbp, rsi\ncall _strlen\ntest eax, eax\njle short loc_11C2\nlea esi, [rax-1]\nmov eax, 0\nmov ecx, 0\njmp short loc_119D\nloc_1191:\nlea rdx, [rax+1]\ncmp rax, rsi\njz short loc_11AD\nmov rax, rdx\nloc_119D:\nmovzx edi, byte ptr [rbp+rax+0]\ncmp [rbx+rax], dil\njz short loc_1191\nadd ecx, 1\njmp short loc_1191\nloc_11AD:\ntest cl, 1\njnz short loc_11C9\nloc_11B2:\nmov eax, ecx\nshr eax, 1Fh\nadd eax, ecx\nsar eax, 1\nloc_11BB:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_11C2:\nmov ecx, 0\njmp short loc_11B2\nloc_11C9:\nmov eax, 0FFFFFFFFh\njmp short loc_11BB", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1, __int64 a2)\n{\n int v3; // eax\n __int64 v4; // rsi\n __int64 v5; // rax\n int v6; // ecx\n\n v3 = strlen(a1);\n if ( v3 <= 0 )\n {\n v6 = 0;\n return (unsigned int)(v6 / 2);\n }\n v4 = (unsigned int)(v3 - 1);\n v5 = 0LL;\n v6 = 0;\n while ( 1 )\n {\n if ( a1[v5] != *(_BYTE *)(a2 + v5) )\n ++v6;\n if ( v5 == v4 )\n break;\n ++v5;\n }\n if ( (v6 & 1) == 0 )\n return (unsigned int)(v6 / 2);\n return 0xFFFFFFFFLL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1, long long a2) {\n int v3;\n long long v4;\n long long v5;\n int v6;\n v3 = strlen(a1);\n if (v3 <= 0) {\n v6 = 0;\n return (unsigned int)(v6 / 2);\n }\n v4 = (unsigned int)(v3 - 1);\n v5 = 0LL;\n v6 = 0;\n while (1) {\n if (a1[v5] != *(uint8_t *)(a2 + v5)) ++v6;\n if (v5 == v4) break;\n ++v5;\n }\n if ((v6 & 1) == 0) return (unsigned int)(v6 / 2);\n return 4294967295LL;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, long long a2) {\n int v3;\n long long v4;\n long long v5;\n int v6;\n v3 = strlen(a1);\n if (v3 <= 0) {\n v6 = 0;\n return (unsigned int)(v6 / 2);\n }\n v4 = (unsigned int)(v3 - 1);\n v5 = 0LL;\n v6 = 0;\n while (1) {\n if (a1[v5] != *(uint8_t *)(a2 + v5)) ++v6;\n if (v5 == v4) break;\n ++v5;\n }\n if ((v6 & 1) == 0) return (unsigned int)(v6 / 2);\n return 4294967295LL;\n}" + }, + { + "index": 699, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(const char* str1, const char* str2) {\n int count = 0;\n int length = strlen(str1);\n for (int i = 0; i < length; i++) {\n if (str1[i] != str2[i]) {\n count++;\n }\n }\n if (count % 2 == 0) {\n return (count / 2);\n } else {\n return -1;\n }\n}", + "test": "int main() {\n\n assert(func0(\"1101\", \"1110\") == 1);\n\n assert(func0(\"1111\", \"0100\") == -1);\n\n assert(func0(\"1110000\", \"0001101\") == 3);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsi,%rbp\npush %rbx\nmov %rdi,%rbx\nsub $0x8,%rsp\ncallq 1060 \ntest %eax,%eax\njle 1290 \nlea -0x1(%rax),%esi\nxor %edx,%edx\nxor %eax,%eax\njmp 125b \nnopw 0x0(%rax,%rax,1)\nmov %rcx,%rax\nxor %ecx,%ecx\nmovzbl 0x0(%rbp,%rax,1),%edi\ncmp %dil,(%rbx,%rax,1)\nsetne %cl\nadd %ecx,%edx\nlea 0x1(%rax),%rcx\ncmp %rax,%rsi\njne 1258 \nmov %edx,%eax\nsar %eax\nand $0x1,%edx\nmov $0xffffffff,%edx\ncmovne %edx,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopw 0x0(%rax,%rax,1)\nadd $0x8,%rsp\nxor %eax,%eax\npop %rbx\npop %rbp\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsi\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\ntest eax, eax\njle short loc_1290\nlea esi, [rax-1]\nxor ecx, ecx\nxor eax, eax\njmp short loc_125B\nloc_1258:\nmov rax, rdx\nloc_125B:\nmovzx edi, byte ptr [rbp+rax+0]\ncmp [rbx+rax], dil\njz short loc_1269\nadd ecx, 1\nloc_1269:\nlea rdx, [rax+1]\ncmp rsi, rax\njnz short loc_1258\ntest cl, 1\njnz short loc_1299\nmov eax, ecx\nshr eax, 1Fh\nadd eax, ecx\nsar eax, 1\nloc_1280:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1290:\nadd rsp, 8\nxor eax, eax\npop rbx\npop rbp\nretn\nloc_1299:\nmov eax, 0FFFFFFFFh\njmp short loc_1280", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, __int64 a2)\n{\n int v3; // eax\n __int64 v4; // rsi\n int v5; // ecx\n __int64 i; // rax\n\n v3 = strlen(a1);\n if ( v3 <= 0 )\n return 0LL;\n v4 = (unsigned int)(v3 - 1);\n v5 = 0;\n for ( i = 0LL; ; ++i )\n {\n if ( a1[i] != *(_BYTE *)(a2 + i) )\n ++v5;\n if ( v4 == i )\n break;\n }\n if ( (v5 & 1) != 0 )\n return 0xFFFFFFFFLL;\n else\n return (unsigned int)(v5 / 2);\n}", + "ida_strip_asm": "sub_1230:\nendbr64\npush rbp\nmov rbp, rsi\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\ntest eax, eax\njle short loc_1290\nlea esi, [rax-1]\nxor ecx, ecx\nxor eax, eax\njmp short loc_125B\nloc_1258:\nmov rax, rdx\nloc_125B:\nmovzx edi, byte ptr [rbp+rax+0]\ncmp [rbx+rax], dil\njz short loc_1269\nadd ecx, 1\nloc_1269:\nlea rdx, [rax+1]\ncmp rsi, rax\njnz short loc_1258\ntest cl, 1\njnz short loc_1299\nmov eax, ecx\nshr eax, 1Fh\nadd eax, ecx\nsar eax, 1\nloc_1280:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1290:\nadd rsp, 8\nxor eax, eax\npop rbx\npop rbp\nretn\nloc_1299:\nmov eax, 0FFFFFFFFh\njmp short loc_1280", + "ida_strip_pseudo": "__int64 __fastcall sub_1230(const char *a1, __int64 a2)\n{\n int v3; // eax\n __int64 v4; // rsi\n int v5; // ecx\n __int64 i; // rax\n\n v3 = strlen(a1);\n if ( v3 <= 0 )\n return 0LL;\n v4 = (unsigned int)(v3 - 1);\n v5 = 0;\n for ( i = 0LL; ; ++i )\n {\n if ( a1[i] != *(_BYTE *)(a2 + i) )\n ++v5;\n if ( v4 == i )\n break;\n }\n if ( (v5 & 1) != 0 )\n return 0xFFFFFFFFLL;\n else\n return (unsigned int)(v5 / 2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1230(const char *a1, long long a2) {\n int v3;\n long long v4;\n int v5;\n long long i;\n v3 = strlen(a1);\n if (v3 <= 0) return 0LL;\n v4 = (unsigned int)(v3 - 1);\n v5 = 0;\n for (i = 0LL;; ++i) {\n if (a1[i] != *(uint8_t *)(a2 + i)) ++v5;\n if (v4 == i) break;\n }\n if ((v5 & 1) != 0)\n return 4294967295LL;\n else\n return (unsigned int)(v5 / 2);\n}", + "ida_pseudo_norm": "long long func0(const char *a1, long long a2) {\n int v3;\n long long v4;\n int v5;\n long long i;\n v3 = strlen(a1);\n if (v3 <= 0) return 0LL;\n v4 = (unsigned int)(v3 - 1);\n v5 = 0;\n for (i = 0LL;; ++i) {\n if (a1[i] != *(uint8_t *)(a2 + i)) ++v5;\n if (v4 == i) break;\n }\n if ((v5 & 1) != 0)\n return 4294967295LL;\n else\n return (unsigned int)(v5 / 2);\n}" + }, + { + "index": 699, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(const char* str1, const char* str2) {\n int count = 0;\n int length = strlen(str1);\n for (int i = 0; i < length; i++) {\n if (str1[i] != str2[i]) {\n count++;\n }\n }\n if (count % 2 == 0) {\n return (count / 2);\n } else {\n return -1;\n }\n}", + "test": "int main() {\n\n assert(func0(\"1101\", \"1110\") == 1);\n\n assert(func0(\"1111\", \"0100\") == -1);\n\n assert(func0(\"1110000\", \"0001101\") == 3);\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsi,%rbp\npush %rbx\nmov %rdi,%rbx\nsub $0x8,%rsp\ncallq 1060 \ntest %eax,%eax\njle 1500 \nlea -0x1(%rax),%edx\ncmp $0xe,%edx\njbe 1509 \nmov %eax,%ecx\nmovdqa 0xe6d(%rip),%xmm6\nxor %edx,%edx\npxor %xmm1,%xmm1\nshr $0x4,%ecx\npxor %xmm5,%xmm5\npxor %xmm4,%xmm4\nshl $0x4,%rcx\nnopl 0x0(%rax,%rax,1)\nmovdqu 0x0(%rbp,%rdx,1),%xmm7\nmovdqu (%rbx,%rdx,1),%xmm0\nmovdqa %xmm5,%xmm3\nadd $0x10,%rdx\npcmpeqb %xmm7,%xmm0\npandn %xmm6,%xmm0\npcmpgtb %xmm0,%xmm3\nmovdqa %xmm0,%xmm2\npunpcklbw %xmm3,%xmm2\npunpckhbw %xmm3,%xmm0\nmovdqa %xmm4,%xmm3\npcmpgtw %xmm2,%xmm3\nmovdqa %xmm2,%xmm7\npunpcklwd %xmm3,%xmm7\npunpckhwd %xmm3,%xmm2\nmovdqa %xmm0,%xmm3\npaddd %xmm7,%xmm1\npaddd %xmm2,%xmm1\nmovdqa %xmm4,%xmm2\npcmpgtw %xmm0,%xmm2\npunpcklwd %xmm2,%xmm3\npunpckhwd %xmm2,%xmm0\npaddd %xmm3,%xmm1\npaddd %xmm0,%xmm1\ncmp %rcx,%rdx\njne 1280 \nmovdqa %xmm1,%xmm0\nmov %eax,%ecx\npsrldq $0x8,%xmm0\nand $0xfffffff0,%ecx\npaddd %xmm1,%xmm0\nmovdqa %xmm0,%xmm1\npsrldq $0x4,%xmm1\npaddd %xmm1,%xmm0\nmovd %xmm0,%edx\ntest $0xf,%al\nje 14e4 \nmovslq %ecx,%rsi\nmovzbl 0x0(%rbp,%rsi,1),%edi\ncmp %dil,(%rbx,%rsi,1)\nsetne %sil\nmovzbl %sil,%esi\nadd %esi,%edx\nlea 0x1(%rcx),%esi\ncmp %eax,%esi\njge 14e4 \nmovslq %esi,%rsi\nmovzbl (%rbx,%rsi,1),%edi\ncmp %dil,0x0(%rbp,%rsi,1)\nsetne %sil\nmovzbl %sil,%esi\nadd %esi,%edx\nlea 0x2(%rcx),%esi\ncmp %esi,%eax\njle 14e4 \nmovslq %esi,%rsi\nmovzbl 0x0(%rbp,%rsi,1),%edi\ncmp %dil,(%rbx,%rsi,1)\nsetne %sil\nmovzbl %sil,%esi\nadd %esi,%edx\nlea 0x3(%rcx),%esi\ncmp %esi,%eax\njle 14e4 \nmovslq %esi,%rsi\nmovzbl 0x0(%rbp,%rsi,1),%edi\ncmp %dil,(%rbx,%rsi,1)\nsetne %sil\nmovzbl %sil,%esi\nadd %esi,%edx\nlea 0x4(%rcx),%esi\ncmp %esi,%eax\njle 14e4 \nmovslq %esi,%rsi\nmovzbl 0x0(%rbp,%rsi,1),%edi\ncmp %dil,(%rbx,%rsi,1)\nsetne %sil\nmovzbl %sil,%esi\nadd %esi,%edx\nlea 0x5(%rcx),%esi\ncmp %esi,%eax\njle 14e4 \nmovslq %esi,%rsi\nmovzbl 0x0(%rbp,%rsi,1),%edi\ncmp %dil,(%rbx,%rsi,1)\nsetne %sil\nmovzbl %sil,%esi\nadd %esi,%edx\nlea 0x6(%rcx),%esi\ncmp %esi,%eax\njle 14e4 \nmovslq %esi,%rsi\nmovzbl 0x0(%rbp,%rsi,1),%edi\ncmp %dil,(%rbx,%rsi,1)\nsetne %sil\nmovzbl %sil,%esi\nadd %esi,%edx\nlea 0x7(%rcx),%esi\ncmp %esi,%eax\njle 14e4 \nmovslq %esi,%rsi\nmovzbl 0x0(%rbp,%rsi,1),%edi\ncmp %dil,(%rbx,%rsi,1)\nsetne %sil\nmovzbl %sil,%esi\nadd %esi,%edx\nlea 0x8(%rcx),%esi\ncmp %esi,%eax\njle 14e4 \nmovslq %esi,%rsi\nmovzbl 0x0(%rbp,%rsi,1),%edi\ncmp %dil,(%rbx,%rsi,1)\nsetne %sil\nmovzbl %sil,%esi\nadd %esi,%edx\nlea 0x9(%rcx),%esi\ncmp %esi,%eax\njle 14e4 \nmovslq %esi,%rsi\nmovzbl 0x0(%rbp,%rsi,1),%edi\ncmp %dil,(%rbx,%rsi,1)\nsetne %sil\nmovzbl %sil,%esi\nadd %esi,%edx\nlea 0xa(%rcx),%esi\ncmp %esi,%eax\njle 14e4 \nmovslq %esi,%rsi\nmovzbl 0x0(%rbp,%rsi,1),%edi\ncmp %dil,(%rbx,%rsi,1)\nsetne %sil\nmovzbl %sil,%esi\nadd %esi,%edx\nlea 0xb(%rcx),%esi\ncmp %esi,%eax\njle 14e4 \nmovslq %esi,%rsi\nmovzbl 0x0(%rbp,%rsi,1),%edi\ncmp %dil,(%rbx,%rsi,1)\nsetne %sil\nmovzbl %sil,%esi\nadd %esi,%edx\nlea 0xc(%rcx),%esi\ncmp %esi,%eax\njle 14e4 \nmovslq %esi,%rsi\nmovzbl 0x0(%rbp,%rsi,1),%edi\ncmp %dil,(%rbx,%rsi,1)\nsetne %sil\nmovzbl %sil,%esi\nadd %esi,%edx\nlea 0xd(%rcx),%esi\ncmp %esi,%eax\njle 14e4 \nmovslq %esi,%rsi\nmovzbl 0x0(%rbp,%rsi,1),%edi\ncmp %dil,(%rbx,%rsi,1)\nsetne %sil\nadd $0xe,%ecx\nmovzbl %sil,%esi\nadd %esi,%edx\ncmp %ecx,%eax\njle 14e4 \nmovslq %ecx,%rcx\nmovzbl 0x0(%rbp,%rcx,1),%eax\ncmp %al,(%rbx,%rcx,1)\nsetne %al\nmovzbl %al,%eax\nadd %eax,%edx\nmov %edx,%eax\nsar %eax\nand $0x1,%edx\nmov $0xffffffff,%edx\ncmovne %edx,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopw 0x0(%rax,%rax,1)\nadd $0x8,%rsp\nxor %eax,%eax\npop %rbx\npop %rbp\nretq\nxor %ecx,%ecx\nxor %edx,%edx\njmpq 1313 \nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsi\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\ntest eax, eax\njle loc_1470\nmov rdx, rax\nlea eax, [rax-1]\ncmp eax, 0Eh\njbe loc_1479\nmov ecx, edx\npxor xmm1, xmm1\npxor xmm5, xmm5\nxor eax, eax\nshr ecx, 4\npxor xmm4, xmm4\nshl rcx, 4\nnop dword ptr [rax+rax+00h]\nloc_1278:\nmovdqu xmm0, xmmword ptr [rbx+rax]\nmovdqu xmm7, xmmword ptr [rbp+rax+0]\nmovdqa xmm3, xmm5\nadd rax, 10h\npcmpeqb xmm0, xmm7\npcmpeqb xmm0, xmm5\npcmpgtb xmm3, xmm0\nmovdqa xmm2, xmm0\npunpcklbw xmm2, xmm3\npunpckhbw xmm0, xmm3\nmovdqa xmm3, xmm4\npcmpgtw xmm3, xmm2\nmovdqa xmm6, xmm2\npunpcklwd xmm6, xmm3\npunpckhwd xmm2, xmm3\nmovdqa xmm3, xmm0\npsubd xmm1, xmm6\npsubd xmm1, xmm2\nmovdqa xmm2, xmm4\npcmpgtw xmm2, xmm0\npunpcklwd xmm3, xmm2\npunpckhwd xmm0, xmm2\npsubd xmm1, xmm3\npsubd xmm1, xmm0\ncmp rax, rcx\njnz short loc_1278\nmovdqa xmm0, xmm1\nmov eax, edx\npsrldq xmm0, 8\nand eax, 0FFFFFFF0h\npaddd xmm0, xmm1\nmov ecx, eax\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\npaddd xmm0, xmm2\nmovd edi, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm1, 8\npaddd xmm1, xmm0\ntest dl, 0Fh\njz loc_1459\nloc_131B:\nmov esi, edx\nsub esi, eax\nlea r8d, [rsi-1]\ncmp r8d, 6\njbe loc_13BA\nmovq xmm2, qword ptr [rbp+rax+0]\nmovq xmm0, qword ptr [rbx+rax]\npcmpeqb xmm0, xmm2\npxor xmm2, xmm2\npcmpeqb xmm0, xmm2\npcmpgtb xmm2, xmm0\nmovdqa xmm3, xmm0\npunpcklbw xmm3, xmm2\npunpcklbw xmm0, xmm2\npxor xmm2, xmm2\nmovdqa xmm4, xmm2\nmovdqa xmm5, xmm3\npshufd xmm0, xmm0, 4Eh ; 'N'\npcmpgtw xmm4, xmm3\npcmpgtw xmm2, xmm0\npunpcklwd xmm5, xmm4\npunpcklwd xmm3, xmm4\npsubd xmm1, xmm5\npshufd xmm3, xmm3, 4Eh ; 'N'\npsubd xmm1, xmm3\nmovdqa xmm3, xmm0\npunpcklwd xmm0, xmm2\npunpcklwd xmm3, xmm2\npshufd xmm0, xmm0, 4Eh ; 'N'\npsubd xmm1, xmm3\npsubd xmm1, xmm0\nmovd edi, xmm1\npshufd xmm7, xmm1, 0E5h\nmovd eax, xmm7\nadd edi, eax\nmov eax, esi\nand eax, 0FFFFFFF8h\nadd ecx, eax\nand esi, 7\njz loc_1459\nloc_13BA:\nmovsxd rax, ecx\nmovzx esi, byte ptr [rbp+rax+0]\ncmp [rbx+rax], sil\njz short loc_13CB\nadd edi, 1\nloc_13CB:\nlea eax, [rcx+1]\ncmp edx, eax\njle loc_1459\ncdqe\nmovzx esi, byte ptr [rbp+rax+0]\ncmp [rbx+rax], sil\njz short loc_13E6\nadd edi, 1\nloc_13E6:\nlea eax, [rcx+2]\ncmp edx, eax\njle short loc_1459\ncdqe\nmovzx esi, byte ptr [rbx+rax]\ncmp [rbp+rax+0], sil\njz short loc_13FD\nadd edi, 1\nloc_13FD:\nlea eax, [rcx+3]\ncmp edx, eax\njle short loc_1459\ncdqe\nmovzx esi, byte ptr [rbp+rax+0]\ncmp [rbx+rax], sil\njz short loc_1414\nadd edi, 1\nloc_1414:\nlea eax, [rcx+4]\ncmp edx, eax\njle short loc_1459\ncdqe\nmovzx esi, byte ptr [rbx+rax]\ncmp [rbp+rax+0], sil\njz short loc_142B\nadd edi, 1\nloc_142B:\nlea eax, [rcx+5]\ncmp edx, eax\njle short loc_1459\ncdqe\nmovzx esi, byte ptr [rbp+rax+0]\ncmp [rbx+rax], sil\njz short loc_1442\nadd edi, 1\nloc_1442:\nadd ecx, 6\ncmp edx, ecx\njle short loc_1459\nmovsxd rcx, ecx\nmovzx eax, byte ptr [rbp+rcx+0]\ncmp [rbx+rcx], al\njz short loc_1459\nadd edi, 1\nloc_1459:\ntest dil, 1\njnz short loc_1488\nmov eax, edi\nshr eax, 1Fh\nadd eax, edi\nsar eax, 1\nloc_1468:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1470:\nadd rsp, 8\nxor eax, eax\npop rbx\npop rbp\nretn\nloc_1479:\npxor xmm1, xmm1\nxor eax, eax\nxor ecx, ecx\nxor edi, edi\njmp loc_131B\nloc_1488:\nmov eax, 0FFFFFFFFh\njmp short loc_1468", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, __int64 a2)\n{\n int v4; // eax\n int v5; // edx\n __m128i v6; // xmm1\n __int64 v7; // rax\n __m128i v8; // xmm0\n __m128i v9; // xmm7\n __m128i v10; // xmm0\n __m128i v11; // xmm3\n __m128i v12; // xmm2\n __m128i v13; // xmm0\n __m128i v14; // xmm3\n __m128i v15; // xmm1\n __m128i v16; // xmm2\n __int64 v17; // rax\n __m128i v18; // xmm0\n signed int v19; // ecx\n int v20; // edi\n __m128i v21; // xmm1\n int v22; // esi\n __m128i v23; // xmm0\n __m128i v24; // xmm3\n __m128i v25; // xmm0\n __m128i v26; // xmm2\n __m128i v27; // xmm3\n __m128i v28; // xmm1\n int v29; // ecx\n\n v4 = strlen(a1);\n if ( v4 <= 0 )\n return 0LL;\n v5 = v4;\n if ( (unsigned int)(v4 - 1) <= 0xE )\n {\n v21 = 0LL;\n v17 = 0LL;\n v19 = 0;\n v20 = 0;\n goto LABEL_6;\n }\n v6 = 0LL;\n v7 = 0LL;\n do\n {\n v8 = _mm_loadu_si128((const __m128i *)&a1[v7]);\n v9 = _mm_loadu_si128((const __m128i *)(a2 + v7));\n v7 += 16LL;\n v10 = _mm_cmpeq_epi8(_mm_cmpeq_epi8(v8, v9), (__m128i)0LL);\n v11 = _mm_cmpgt_epi8((__m128i)0LL, v10);\n v12 = _mm_unpacklo_epi8(v10, v11);\n v13 = _mm_unpackhi_epi8(v10, v11);\n v14 = _mm_cmpgt_epi16((__m128i)0LL, v12);\n v15 = _mm_sub_epi32(_mm_sub_epi32(v6, _mm_unpacklo_epi16(v12, v14)), _mm_unpackhi_epi16(v12, v14));\n v16 = _mm_cmpgt_epi16((__m128i)0LL, v13);\n v6 = _mm_sub_epi32(_mm_sub_epi32(v15, _mm_unpacklo_epi16(v13, v16)), _mm_unpackhi_epi16(v13, v16));\n }\n while ( v7 != 16LL * ((unsigned int)v5 >> 4) );\n v17 = v5 & 0xFFFFFFF0;\n v18 = _mm_add_epi32(_mm_srli_si128(v6, 8), v6);\n v19 = v5 & 0xFFFFFFF0;\n v20 = _mm_cvtsi128_si32(_mm_add_epi32(v18, _mm_srli_si128(v18, 4)));\n v21 = v18;\n if ( (v5 & 0xF) != 0 )\n {\nLABEL_6:\n v22 = v5 - v17;\n if ( (unsigned int)(v5 - v17 - 1) <= 6 )\n goto LABEL_8;\n v23 = _mm_cmpeq_epi8(\n _mm_cmpeq_epi8(_mm_loadl_epi64((const __m128i *)&a1[v17]), _mm_loadl_epi64((const __m128i *)(a2 + v17))),\n (__m128i)0LL);\n v24 = _mm_unpacklo_epi8(v23, _mm_cmpgt_epi8((__m128i)0LL, v23));\n v25 = _mm_shuffle_epi32(v24, 78);\n v26 = _mm_cmpgt_epi16((__m128i)0LL, v25);\n v27 = _mm_unpacklo_epi16(v24, _mm_cmpgt_epi16((__m128i)0LL, v24));\n v28 = _mm_sub_epi32(\n _mm_sub_epi32(\n _mm_sub_epi32(_mm_sub_epi32(v21, v27), _mm_shuffle_epi32(v27, 78)),\n _mm_unpacklo_epi16(v25, v26)),\n _mm_shuffle_epi32(_mm_unpacklo_epi16(v25, v26), 78));\n v20 = _mm_cvtsi128_si32(_mm_shuffle_epi32(v28, 229)) + _mm_cvtsi128_si32(v28);\n v19 += v22 & 0xFFFFFFF8;\n if ( (v22 & 7) != 0 )\n {\nLABEL_8:\n if ( a1[v19] != *(_BYTE *)(a2 + v19) )\n ++v20;\n if ( v5 > v19 + 1 )\n {\n if ( a1[v19 + 1] != *(_BYTE *)(a2 + v19 + 1) )\n ++v20;\n if ( v5 > v19 + 2 )\n {\n if ( *(_BYTE *)(a2 + v19 + 2) != a1[v19 + 2] )\n ++v20;\n if ( v5 > v19 + 3 )\n {\n if ( a1[v19 + 3] != *(_BYTE *)(a2 + v19 + 3) )\n ++v20;\n if ( v5 > v19 + 4 )\n {\n if ( *(_BYTE *)(a2 + v19 + 4) != a1[v19 + 4] )\n ++v20;\n if ( v5 > v19 + 5 )\n {\n if ( a1[v19 + 5] != *(_BYTE *)(a2 + v19 + 5) )\n ++v20;\n v29 = v19 + 6;\n if ( v5 > v29 && a1[v29] != *(_BYTE *)(a2 + v29) )\n ++v20;\n }\n }\n }\n }\n }\n }\n }\n if ( (v20 & 1) != 0 )\n return 0xFFFFFFFFLL;\n else\n return (unsigned int)(v20 / 2);\n}", + "ida_strip_asm": "sub_1230:\nendbr64\npush rbp\nmov rbp, rsi\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\ntest eax, eax\njle loc_1470\nmov rdx, rax\nlea eax, [rax-1]\ncmp eax, 0Eh\njbe loc_1479\nmov ecx, edx\npxor xmm1, xmm1\npxor xmm5, xmm5\nxor eax, eax\nshr ecx, 4\npxor xmm4, xmm4\nshl rcx, 4\nnop dword ptr [rax+rax+00h]\nloc_1278:\nmovdqu xmm0, xmmword ptr [rbx+rax]\nmovdqu xmm7, xmmword ptr [rbp+rax+0]\nmovdqa xmm3, xmm5\nadd rax, 10h\npcmpeqb xmm0, xmm7\npcmpeqb xmm0, xmm5\npcmpgtb xmm3, xmm0\nmovdqa xmm2, xmm0\npunpcklbw xmm2, xmm3\npunpckhbw xmm0, xmm3\nmovdqa xmm3, xmm4\npcmpgtw xmm3, xmm2\nmovdqa xmm6, xmm2\npunpcklwd xmm6, xmm3\npunpckhwd xmm2, xmm3\nmovdqa xmm3, xmm0\npsubd xmm1, xmm6\npsubd xmm1, xmm2\nmovdqa xmm2, xmm4\npcmpgtw xmm2, xmm0\npunpcklwd xmm3, xmm2\npunpckhwd xmm0, xmm2\npsubd xmm1, xmm3\npsubd xmm1, xmm0\ncmp rax, rcx\njnz short loc_1278\nmovdqa xmm0, xmm1\nmov eax, edx\npsrldq xmm0, 8\nand eax, 0FFFFFFF0h\npaddd xmm0, xmm1\nmov ecx, eax\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\npaddd xmm0, xmm2\nmovd edi, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm1, 8\npaddd xmm1, xmm0\ntest dl, 0Fh\njz loc_1459\nloc_131B:\nmov esi, edx\nsub esi, eax\nlea r8d, [rsi-1]\ncmp r8d, 6\njbe loc_13BA\nmovq xmm2, qword ptr [rbp+rax+0]\nmovq xmm0, qword ptr [rbx+rax]\npcmpeqb xmm0, xmm2\npxor xmm2, xmm2\npcmpeqb xmm0, xmm2\npcmpgtb xmm2, xmm0\nmovdqa xmm3, xmm0\npunpcklbw xmm3, xmm2\npunpcklbw xmm0, xmm2\npxor xmm2, xmm2\nmovdqa xmm4, xmm2\nmovdqa xmm5, xmm3\npshufd xmm0, xmm0, 4Eh ; 'N'\npcmpgtw xmm4, xmm3\npcmpgtw xmm2, xmm0\npunpcklwd xmm5, xmm4\npunpcklwd xmm3, xmm4\npsubd xmm1, xmm5\npshufd xmm3, xmm3, 4Eh ; 'N'\npsubd xmm1, xmm3\nmovdqa xmm3, xmm0\npunpcklwd xmm0, xmm2\npunpcklwd xmm3, xmm2\npshufd xmm0, xmm0, 4Eh ; 'N'\npsubd xmm1, xmm3\npsubd xmm1, xmm0\nmovd edi, xmm1\npshufd xmm7, xmm1, 0E5h\nmovd eax, xmm7\nadd edi, eax\nmov eax, esi\nand eax, 0FFFFFFF8h\nadd ecx, eax\nand esi, 7\njz loc_1459\nloc_13BA:\nmovsxd rax, ecx\nmovzx esi, byte ptr [rbp+rax+0]\ncmp [rbx+rax], sil\njz short loc_13CB\nadd edi, 1\nloc_13CB:\nlea eax, [rcx+1]\ncmp edx, eax\njle loc_1459\ncdqe\nmovzx esi, byte ptr [rbp+rax+0]\ncmp [rbx+rax], sil\njz short loc_13E6\nadd edi, 1\nloc_13E6:\nlea eax, [rcx+2]\ncmp edx, eax\njle short loc_1459\ncdqe\nmovzx esi, byte ptr [rbx+rax]\ncmp [rbp+rax+0], sil\njz short loc_13FD\nadd edi, 1\nloc_13FD:\nlea eax, [rcx+3]\ncmp edx, eax\njle short loc_1459\ncdqe\nmovzx esi, byte ptr [rbp+rax+0]\ncmp [rbx+rax], sil\njz short loc_1414\nadd edi, 1\nloc_1414:\nlea eax, [rcx+4]\ncmp edx, eax\njle short loc_1459\ncdqe\nmovzx esi, byte ptr [rbx+rax]\ncmp [rbp+rax+0], sil\njz short loc_142B\nadd edi, 1\nloc_142B:\nlea eax, [rcx+5]\ncmp edx, eax\njle short loc_1459\ncdqe\nmovzx esi, byte ptr [rbp+rax+0]\ncmp [rbx+rax], sil\njz short loc_1442\nadd edi, 1\nloc_1442:\nadd ecx, 6\ncmp edx, ecx\njle short loc_1459\nmovsxd rcx, ecx\nmovzx eax, byte ptr [rbp+rcx+0]\ncmp [rbx+rcx], al\njz short loc_1459\nadd edi, 1\nloc_1459:\ntest dil, 1\njnz short loc_1488\nmov eax, edi\nshr eax, 1Fh\nadd eax, edi\nsar eax, 1\nloc_1468:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1470:\nadd rsp, 8\nxor eax, eax\npop rbx\npop rbp\nretn\nloc_1479:\npxor xmm1, xmm1\nxor eax, eax\nxor ecx, ecx\nxor edi, edi\njmp loc_131B\nloc_1488:\nmov eax, 0FFFFFFFFh\njmp short loc_1468", + "ida_strip_pseudo": "__int64 __fastcall sub_1230(const char *a1, __int64 a2)\n{\n int v4; // eax\n int v5; // edx\n __m128i v6; // xmm1\n __int64 v7; // rax\n __m128i v8; // xmm0\n __m128i v9; // xmm7\n __m128i v10; // xmm0\n __m128i v11; // xmm3\n __m128i v12; // xmm2\n __m128i v13; // xmm0\n __m128i v14; // xmm3\n __m128i v15; // xmm1\n __m128i v16; // xmm2\n __int64 v17; // rax\n __m128i v18; // xmm0\n signed int v19; // ecx\n int v20; // edi\n __m128i v21; // xmm1\n int v22; // esi\n __m128i v23; // xmm0\n __m128i v24; // xmm3\n __m128i v25; // xmm0\n __m128i v26; // xmm2\n __m128i v27; // xmm3\n __m128i v28; // xmm1\n int v29; // ecx\n\n v4 = strlen(a1);\n if ( v4 <= 0 )\n return 0LL;\n v5 = v4;\n if ( (unsigned int)(v4 - 1) <= 0xE )\n {\n v21 = 0LL;\n v17 = 0LL;\n v19 = 0;\n v20 = 0;\n goto LABEL_6;\n }\n v6 = 0LL;\n v7 = 0LL;\n do\n {\n v8 = _mm_loadu_si128((const __m128i *)&a1[v7]);\n v9 = _mm_loadu_si128((const __m128i *)(a2 + v7));\n v7 += 16LL;\n v10 = _mm_cmpeq_epi8(_mm_cmpeq_epi8(v8, v9), (__m128i)0LL);\n v11 = _mm_cmpgt_epi8((__m128i)0LL, v10);\n v12 = _mm_unpacklo_epi8(v10, v11);\n v13 = _mm_unpackhi_epi8(v10, v11);\n v14 = _mm_cmpgt_epi16((__m128i)0LL, v12);\n v15 = _mm_sub_epi32(_mm_sub_epi32(v6, _mm_unpacklo_epi16(v12, v14)), _mm_unpackhi_epi16(v12, v14));\n v16 = _mm_cmpgt_epi16((__m128i)0LL, v13);\n v6 = _mm_sub_epi32(_mm_sub_epi32(v15, _mm_unpacklo_epi16(v13, v16)), _mm_unpackhi_epi16(v13, v16));\n }\n while ( v7 != 16LL * ((unsigned int)v5 >> 4) );\n v17 = v5 & 0xFFFFFFF0;\n v18 = _mm_add_epi32(_mm_srli_si128(v6, 8), v6);\n v19 = v5 & 0xFFFFFFF0;\n v20 = _mm_cvtsi128_si32(_mm_add_epi32(v18, _mm_srli_si128(v18, 4)));\n v21 = v18;\n if ( (v5 & 0xF) != 0 )\n {\nLABEL_6:\n v22 = v5 - v17;\n if ( (unsigned int)(v5 - v17 - 1) <= 6 )\n goto LABEL_8;\n v23 = _mm_cmpeq_epi8(\n _mm_cmpeq_epi8(_mm_loadl_epi64((const __m128i *)&a1[v17]), _mm_loadl_epi64((const __m128i *)(a2 + v17))),\n (__m128i)0LL);\n v24 = _mm_unpacklo_epi8(v23, _mm_cmpgt_epi8((__m128i)0LL, v23));\n v25 = _mm_shuffle_epi32(v24, 78);\n v26 = _mm_cmpgt_epi16((__m128i)0LL, v25);\n v27 = _mm_unpacklo_epi16(v24, _mm_cmpgt_epi16((__m128i)0LL, v24));\n v28 = _mm_sub_epi32(\n _mm_sub_epi32(\n _mm_sub_epi32(_mm_sub_epi32(v21, v27), _mm_shuffle_epi32(v27, 78)),\n _mm_unpacklo_epi16(v25, v26)),\n _mm_shuffle_epi32(_mm_unpacklo_epi16(v25, v26), 78));\n v20 = _mm_cvtsi128_si32(_mm_shuffle_epi32(v28, 229)) + _mm_cvtsi128_si32(v28);\n v19 += v22 & 0xFFFFFFF8;\n if ( (v22 & 7) != 0 )\n {\nLABEL_8:\n if ( a1[v19] != *(_BYTE *)(a2 + v19) )\n ++v20;\n if ( v5 > v19 + 1 )\n {\n if ( a1[v19 + 1] != *(_BYTE *)(a2 + v19 + 1) )\n ++v20;\n if ( v5 > v19 + 2 )\n {\n if ( *(_BYTE *)(a2 + v19 + 2) != a1[v19 + 2] )\n ++v20;\n if ( v5 > v19 + 3 )\n {\n if ( a1[v19 + 3] != *(_BYTE *)(a2 + v19 + 3) )\n ++v20;\n if ( v5 > v19 + 4 )\n {\n if ( *(_BYTE *)(a2 + v19 + 4) != a1[v19 + 4] )\n ++v20;\n if ( v5 > v19 + 5 )\n {\n if ( a1[v19 + 5] != *(_BYTE *)(a2 + v19 + 5) )\n ++v20;\n v29 = v19 + 6;\n if ( v5 > v29 && a1[v29] != *(_BYTE *)(a2 + v29) )\n ++v20;\n }\n }\n }\n }\n }\n }\n }\n if ( (v20 & 1) != 0 )\n return 0xFFFFFFFFLL;\n else\n return (unsigned int)(v20 / 2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1230(const char *a1, long long a2) {\n int v4;\n int v5;\n __m128i v6;\n long long v7;\n __m128i v8;\n __m128i v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n __m128i v15;\n __m128i v16;\n long long v17;\n __m128i v18;\n signed int v19;\n int v20;\n __m128i v21;\n int v22;\n __m128i v23;\n __m128i v24;\n __m128i v25;\n __m128i v26;\n __m128i v27;\n __m128i v28;\n int v29;\n v4 = strlen(a1);\n if (v4 <= 0) return 0LL;\n v5 = v4;\n if ((unsigned int)(v4 - 1) <= 14) {\n v21 = 0LL;\n v17 = 0LL;\n v19 = 0;\n v20 = 0;\n goto LABEL_6;\n }\n v6 = 0LL;\n v7 = 0LL;\n do {\n v8 = _mm_loadu_si128((const __m128i *)&a1[v7]);\n v9 = _mm_loadu_si128((const __m128i *)(a2 + v7));\n v7 += 16LL;\n v10 = _mm_cmpeq_epi8(_mm_cmpeq_epi8(v8, v9), (__m128i)0LL);\n v11 = _mm_cmpgt_epi8((__m128i)0LL, v10);\n v12 = _mm_unpacklo_epi8(v10, v11);\n v13 = _mm_unpackhi_epi8(v10, v11);\n v14 = _mm_cmpgt_epi16((__m128i)0LL, v12);\n v15 = _mm_sub_epi32(_mm_sub_epi32(v6, _mm_unpacklo_epi16(v12, v14)),\n _mm_unpackhi_epi16(v12, v14));\n v16 = _mm_cmpgt_epi16((__m128i)0LL, v13);\n v6 = _mm_sub_epi32(_mm_sub_epi32(v15, _mm_unpacklo_epi16(v13, v16)),\n _mm_unpackhi_epi16(v13, v16));\n } while (v7 != 16LL * ((unsigned int)v5 >> 4));\n v17 = v5 & 4294967280;\n v18 = _mm_add_epi32(_mm_srli_si128(v6, 8), v6);\n v19 = v5 & 4294967280;\n v20 = _mm_cvtsi128_si32(_mm_add_epi32(v18, _mm_srli_si128(v18, 4)));\n v21 = v18;\n if ((v5 & 15) != 0) {\n LABEL_6:\n v22 = v5 - v17;\n if ((unsigned int)(v5 - v17 - 1) <= 6) goto LABEL_8;\n v23 = _mm_cmpeq_epi8(\n _mm_cmpeq_epi8(_mm_loadl_epi64((const __m128i *)&a1[v17]),\n _mm_loadl_epi64((const __m128i *)(a2 + v17))),\n (__m128i)0LL);\n v24 = _mm_unpacklo_epi8(v23, _mm_cmpgt_epi8((__m128i)0LL, v23));\n v25 = _mm_shuffle_epi32(v24, 78);\n v26 = _mm_cmpgt_epi16((__m128i)0LL, v25);\n v27 = _mm_unpacklo_epi16(v24, _mm_cmpgt_epi16((__m128i)0LL, v24));\n v28 = _mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(v21, v27),\n _mm_shuffle_epi32(v27, 78)),\n _mm_unpacklo_epi16(v25, v26)),\n _mm_shuffle_epi32(_mm_unpacklo_epi16(v25, v26), 78));\n v20 =\n _mm_cvtsi128_si32(_mm_shuffle_epi32(v28, 229)) + _mm_cvtsi128_si32(v28);\n v19 += v22 & 4294967288;\n if ((v22 & 7) != 0) {\n LABEL_8:\n if (a1[v19] != *(uint8_t *)(a2 + v19)) ++v20;\n if (v5 > v19 + 1) {\n if (a1[v19 + 1] != *(uint8_t *)(a2 + v19 + 1)) ++v20;\n if (v5 > v19 + 2) {\n if (*(uint8_t *)(a2 + v19 + 2) != a1[v19 + 2]) ++v20;\n if (v5 > v19 + 3) {\n if (a1[v19 + 3] != *(uint8_t *)(a2 + v19 + 3)) ++v20;\n if (v5 > v19 + 4) {\n if (*(uint8_t *)(a2 + v19 + 4) != a1[v19 + 4]) ++v20;\n if (v5 > v19 + 5) {\n if (a1[v19 + 5] != *(uint8_t *)(a2 + v19 + 5)) ++v20;\n v29 = v19 + 6;\n if (v5 > v29 && a1[v29] != *(uint8_t *)(a2 + v29)) ++v20;\n }\n }\n }\n }\n }\n }\n }\n if ((v20 & 1) != 0)\n return 4294967295LL;\n else\n return (unsigned int)(v20 / 2);\n}", + "ida_pseudo_norm": "long long func0(const char *a1, long long a2) {\n int v4;\n int v5;\n __m128i v6;\n long long v7;\n __m128i v8;\n __m128i v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n __m128i v15;\n __m128i v16;\n long long v17;\n __m128i v18;\n signed int v19;\n int v20;\n __m128i v21;\n int v22;\n __m128i v23;\n __m128i v24;\n __m128i v25;\n __m128i v26;\n __m128i v27;\n __m128i v28;\n int v29;\n v4 = strlen(a1);\n if (v4 <= 0) return 0LL;\n v5 = v4;\n if ((unsigned int)(v4 - 1) <= 14) {\n v21 = 0LL;\n v17 = 0LL;\n v19 = 0;\n v20 = 0;\n goto LABEL_6;\n }\n v6 = 0LL;\n v7 = 0LL;\n do {\n v8 = _mm_loadu_si128((const __m128i *)&a1[v7]);\n v9 = _mm_loadu_si128((const __m128i *)(a2 + v7));\n v7 += 16LL;\n v10 = _mm_cmpeq_epi8(_mm_cmpeq_epi8(v8, v9), (__m128i)0LL);\n v11 = _mm_cmpgt_epi8((__m128i)0LL, v10);\n v12 = _mm_unpacklo_epi8(v10, v11);\n v13 = _mm_unpackhi_epi8(v10, v11);\n v14 = _mm_cmpgt_epi16((__m128i)0LL, v12);\n v15 = _mm_sub_epi32(_mm_sub_epi32(v6, _mm_unpacklo_epi16(v12, v14)),\n _mm_unpackhi_epi16(v12, v14));\n v16 = _mm_cmpgt_epi16((__m128i)0LL, v13);\n v6 = _mm_sub_epi32(_mm_sub_epi32(v15, _mm_unpacklo_epi16(v13, v16)),\n _mm_unpackhi_epi16(v13, v16));\n } while (v7 != 16LL * ((unsigned int)v5 >> 4));\n v17 = v5 & 4294967280;\n v18 = _mm_add_epi32(_mm_srli_si128(v6, 8), v6);\n v19 = v5 & 4294967280;\n v20 = _mm_cvtsi128_si32(_mm_add_epi32(v18, _mm_srli_si128(v18, 4)));\n v21 = v18;\n if ((v5 & 15) != 0) {\n LABEL_6:\n v22 = v5 - v17;\n if ((unsigned int)(v5 - v17 - 1) <= 6) goto LABEL_8;\n v23 = _mm_cmpeq_epi8(\n _mm_cmpeq_epi8(_mm_loadl_epi64((const __m128i *)&a1[v17]),\n _mm_loadl_epi64((const __m128i *)(a2 + v17))),\n (__m128i)0LL);\n v24 = _mm_unpacklo_epi8(v23, _mm_cmpgt_epi8((__m128i)0LL, v23));\n v25 = _mm_shuffle_epi32(v24, 78);\n v26 = _mm_cmpgt_epi16((__m128i)0LL, v25);\n v27 = _mm_unpacklo_epi16(v24, _mm_cmpgt_epi16((__m128i)0LL, v24));\n v28 = _mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(v21, v27),\n _mm_shuffle_epi32(v27, 78)),\n _mm_unpacklo_epi16(v25, v26)),\n _mm_shuffle_epi32(_mm_unpacklo_epi16(v25, v26), 78));\n v20 =\n _mm_cvtsi128_si32(_mm_shuffle_epi32(v28, 229)) + _mm_cvtsi128_si32(v28);\n v19 += v22 & 4294967288;\n if ((v22 & 7) != 0) {\n LABEL_8:\n if (a1[v19] != *(uint8_t *)(a2 + v19)) ++v20;\n if (v5 > v19 + 1) {\n if (a1[v19 + 1] != *(uint8_t *)(a2 + v19 + 1)) ++v20;\n if (v5 > v19 + 2) {\n if (*(uint8_t *)(a2 + v19 + 2) != a1[v19 + 2]) ++v20;\n if (v5 > v19 + 3) {\n if (a1[v19 + 3] != *(uint8_t *)(a2 + v19 + 3)) ++v20;\n if (v5 > v19 + 4) {\n if (*(uint8_t *)(a2 + v19 + 4) != a1[v19 + 4]) ++v20;\n if (v5 > v19 + 5) {\n if (a1[v19 + 5] != *(uint8_t *)(a2 + v19 + 5)) ++v20;\n v29 = v19 + 6;\n if (v5 > v29 && a1[v29] != *(uint8_t *)(a2 + v29)) ++v20;\n }\n }\n }\n }\n }\n }\n }\n if ((v20 & 1) != 0)\n return 4294967295LL;\n else\n return (unsigned int)(v20 / 2);\n}" + }, + { + "index": 700, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int li[], int size, int min, int max) {\n int ctr = 0;\n for (int i = 0; i < size; i++) {\n if (li[i] >= min && li[i] <= max) {\n ctr++;\n }\n }\n return ctr;\n}", + "test": "int main() {\n\n int list1[] = {10, 20, 30, 40, 40, 40, 70, 80, 99};\n\n int list1_size = sizeof(list1) / sizeof(list1[0]);\n\n assert(func0(list1, list1_size, 40, 100) == 6);\n\n \n\n int list3[] = {7, 8, 9, 15, 17, 19, 45};\n\n int list3_size = sizeof(list3) / sizeof(list3[0]);\n\n assert(func0(list3, list3_size, 15, 20) == 3);\n\n \n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmov %ecx,-0x24(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11cc \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x20(%rbp)\njg 11c8 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x24(%rbp)\njl 11c8 \naddl $0x1,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 118e \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_24], ecx\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11CC\nloc_118E:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njg short loc_11C8\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_24], eax\njl short loc_11C8\nadd [rbp+var_8], 1\nloc_11C8:\nadd [rbp+var_4], 1\nloc_11CC:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_118E\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3, int a4)\n{\n unsigned int v5; // [rsp+1Ch] [rbp-8h]\n int i; // [rsp+20h] [rbp-4h]\n\n v5 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( a3 <= *(_DWORD *)(4LL * i + a1) && a4 >= *(_DWORD *)(4LL * i + a1) )\n ++v5;\n }\n return v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_24], ecx\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11CC\nloc_118E:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njg short loc_11C8\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_24], eax\njl short loc_11C8\nadd [rbp+var_8], 1\nloc_11C8:\nadd [rbp+var_4], 1\nloc_11CC:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_118E\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3, int a4)\n{\n unsigned int v5; // [rsp+1Ch] [rbp-8h]\n int i; // [rsp+20h] [rbp-4h]\n\n v5 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( a3 <= *(_DWORD *)(4LL * i + a1) && a4 >= *(_DWORD *)(4LL * i + a1) )\n ++v5;\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3, int a4) {\n unsigned int v5;\n int i;\n v5 = 0;\n for (i = 0; i < a2; ++i) {\n if (a3 <= *(uint32_t *)(4LL * i + a1) && a4 >= *(uint32_t *)(4LL * i + a1))\n ++v5;\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3, int a4) {\n unsigned int v5;\n int i;\n v5 = 0;\n for (i = 0; i < a2; ++i) {\n if (a3 <= *(uint32_t *)(4LL * i + a1) && a4 >= *(uint32_t *)(4LL * i + a1))\n ++v5;\n }\n return v5;\n}" + }, + { + "index": 700, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int li[], int size, int min, int max) {\n int ctr = 0;\n for (int i = 0; i < size; i++) {\n if (li[i] >= min && li[i] <= max) {\n ctr++;\n }\n }\n return ctr;\n}", + "test": "int main() {\n\n int list1[] = {10, 20, 30, 40, 40, 40, 70, 80, 99};\n\n int list1_size = sizeof(list1) / sizeof(list1[0]);\n\n assert(func0(list1, list1_size, 40, 100) == 6);\n\n \n\n int list3[] = {7, 8, 9, 15, 17, 19, 45};\n\n int list3_size = sizeof(list3) / sizeof(list3[0]);\n\n assert(func0(list3, list3_size, 15, 20) == 3);\n\n \n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11a1 \nmov %rdi,%rax\nlea -0x1(%rsi),%esi\nlea 0x4(%rdi,%rsi,4),%r8\nmov $0x0,%edi\njmp 118c \nadd $0x4,%rax\ncmp %r8,%rax\nje 11a6 \nmov (%rax),%esi\ncmp %ecx,%esi\njg 1183 \ncmp %edx,%esi\nsetge %sil\ncmp $0x1,%sil\nsbb $0xffffffff,%edi\njmp 1183 \nmov $0x0,%edi\nmov %edi,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11A0\nmov rax, rdi\nmovsxd rsi, esi\nlea r8, [rdi+rsi*4]\nmov edi, 0\njmp short loc_118B\nloc_1182:\nadd rax, 4\ncmp rax, r8\njz short loc_11A5\nloc_118B:\nmov esi, [rax]\ncmp esi, ecx\njg short loc_1182\ncmp esi, edx\nsetnl sil\ncmp sil, 1\nsbb edi, 0FFFFFFFFh\njmp short loc_1182\nloc_11A0:\nmov edi, 0\nloc_11A5:\nmov eax, edi\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2, int a3, int a4)\n{\n _DWORD *v4; // rax\n _DWORD *v5; // r8\n unsigned int v6; // edi\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v4 = a1;\n v5 = &a1[a2];\n v6 = 0;\n do\n {\n if ( *v4 <= a4 )\n v6 -= (*v4 < a3) - 1;\n ++v4;\n }\n while ( v4 != v5 );\n }\n return v6;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11A0\nmov rax, rdi\nmovsxd rsi, esi\nlea r8, [rdi+rsi*4]\nmov edi, 0\njmp short loc_118B\nloc_1182:\nadd rax, 4\ncmp rax, r8\njz short loc_11A5\nloc_118B:\nmov esi, [rax]\ncmp esi, ecx\njg short loc_1182\ncmp esi, edx\nsetnl sil\ncmp sil, 1\nsbb edi, 0FFFFFFFFh\njmp short loc_1182\nloc_11A0:\nmov edi, 0\nloc_11A5:\nmov eax, edi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2, int a3, int a4)\n{\n _DWORD *v4; // rax\n _DWORD *v5; // r8\n unsigned int v6; // edi\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v4 = a1;\n v5 = &a1[a2];\n v6 = 0;\n do\n {\n if ( *v4 <= a4 )\n v6 -= (*v4 < a3) - 1;\n ++v4;\n }\n while ( v4 != v5 );\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2, int a3, int a4) {\n uint32_t *v4;\n uint32_t *v5;\n unsigned int v6;\n if (a2 <= 0) {\n return 0;\n } else {\n v4 = a1;\n v5 = &a1[a2];\n v6 = 0;\n do {\n if (*v4 <= a4) v6 -= (*v4 < a3) - 1;\n ++v4;\n } while (v4 != v5);\n }\n return v6;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2, int a3, int a4) {\n uint32_t *v4;\n uint32_t *v5;\n unsigned int v6;\n if (a2 <= 0) {\n return 0;\n } else {\n v4 = a1;\n v5 = &a1[a2];\n v6 = 0;\n do {\n if (*v4 <= a4) v6 -= (*v4 < a3) - 1;\n ++v4;\n } while (v4 != v5);\n }\n return v6;\n}" + }, + { + "index": 701, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int total_sum = 0;\n for (int i = 0; i < n; i++) {\n total_sum += arr[i];\n }\n int left_sum = 0;\n for (int i = 0; i < n; i++) {\n total_sum -= arr[i];\n if (left_sum == total_sum) {\n return i;\n }\n left_sum += arr[i];\n }\n return -1;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4, 1, 2, 3};\n\n int arr2[] = {-7, 1, 5, 2, -4, 3, 0};\n\n int arr3[] = {1, 2, 3};\n\n\n\n assert(func0(arr1, 7) == 3);\n\n assert(func0(arr2, 7) == 3);\n\n assert(func0(arr3, 3) == -1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 11a5 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nadd %eax,-0x10(%rbp)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1188 \nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 1200 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nsub %eax,-0x10(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x10(%rbp),%eax\njne 11e3 \nmov -0x4(%rbp),%eax\njmp 120d \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nadd %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11bd \nmov $0xffffffff,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp short loc_11A5\nloc_1188:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_10], eax\nadd [rbp+var_C], 1\nloc_11A5:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_1200\nloc_11BD:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nsub [rbp+var_10], eax\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_10]\njnz short loc_11E3\nmov eax, [rbp+var_4]\njmp short loc_120D\nloc_11E3:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_1200:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11BD\nmov eax, 0FFFFFFFFh\nloc_120D:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int v3; // [rsp+Ch] [rbp-10h]\n int i; // [rsp+10h] [rbp-Ch]\n int v5; // [rsp+14h] [rbp-8h]\n unsigned int j; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n v3 += *(_DWORD *)(4LL * i + a1);\n v5 = 0;\n for ( j = 0; (int)j < a2; ++j )\n {\n v3 -= *(_DWORD *)(4LL * (int)j + a1);\n if ( v5 == v3 )\n return j;\n v5 += *(_DWORD *)(4LL * (int)j + a1);\n }\n return 0xFFFFFFFFLL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp short loc_11A5\nloc_1188:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_10], eax\nadd [rbp+var_C], 1\nloc_11A5:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_1200\nloc_11BD:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nsub [rbp+var_10], eax\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_10]\njnz short loc_11E3\nmov eax, [rbp+var_4]\njmp short loc_120D\nloc_11E3:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_1200:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11BD\nmov eax, 0FFFFFFFFh\nloc_120D:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int v3; // [rsp+Ch] [rbp-10h]\n int i; // [rsp+10h] [rbp-Ch]\n int v5; // [rsp+14h] [rbp-8h]\n unsigned int j; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n v3 += *(_DWORD *)(4LL * i + a1);\n v5 = 0;\n for ( j = 0; (int)j < a2; ++j )\n {\n v3 -= *(_DWORD *)(4LL * (int)j + a1);\n if ( v5 == v3 )\n return j;\n v5 += *(_DWORD *)(4LL * (int)j + a1);\n }\n return 0xFFFFFFFFLL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int v3;\n int i;\n int v5;\n unsigned int j;\n v3 = 0;\n for (i = 0; i < a2; ++i) v3 += *(uint32_t *)(4LL * i + a1);\n v5 = 0;\n for (j = 0; (int)j < a2; ++j) {\n v3 -= *(uint32_t *)(4LL * (int)j + a1);\n if (v5 == v3) return j;\n v5 += *(uint32_t *)(4LL * (int)j + a1);\n }\n return 4294967295LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int v3;\n int i;\n int v5;\n unsigned int j;\n v3 = 0;\n for (i = 0; i < a2; ++i) v3 += *(uint32_t *)(4LL * i + a1);\n v5 = 0;\n for (j = 0; (int)j < a2; ++j) {\n v3 -= *(uint32_t *)(4LL * (int)j + a1);\n if (v5 == v3) return j;\n v5 += *(uint32_t *)(4LL * (int)j + a1);\n }\n return 4294967295LL;\n}" + }, + { + "index": 701, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int total_sum = 0;\n for (int i = 0; i < n; i++) {\n total_sum += arr[i];\n }\n int left_sum = 0;\n for (int i = 0; i < n; i++) {\n total_sum -= arr[i];\n if (left_sum == total_sum) {\n return i;\n }\n left_sum += arr[i];\n }\n return -1;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4, 1, 2, 3};\n\n int arr2[] = {-7, 1, 5, 2, -4, 3, 0};\n\n int arr3[] = {1, 2, 3};\n\n\n\n assert(func0(arr1, 7) == 3);\n\n assert(func0(arr2, 7) == 3);\n\n assert(func0(arr3, 3) == -1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11c4 \nmov %rdi,%rdx\nlea -0x1(%rsi),%r8d\nlea 0x4(%rdi,%r8,4),%rcx\nmov $0x0,%eax\nadd (%rdx),%eax\nadd $0x4,%rdx\ncmp %rcx,%rdx\njne 1182 \nmov (%rdi),%ecx\nsub %ecx,%eax\nje 11cc \nadd $0x1,%r8\nmov $0x1,%edx\nmov $0x0,%esi\nadd %ecx,%esi\nmov %edx,%r9d\ncmp %rdx,%r8\nje 11ba \nmov (%rdi,%rdx,4),%ecx\nsub %ecx,%eax\nadd $0x1,%rdx\ncmp %esi,%eax\njne 11a1 \njmp 11c0 \nmov $0xffffffff,%r9d\nmov %r9d,%eax\nretq\nmov $0xffffffff,%r9d\njmp 11c0 \nmov %eax,%r9d\njmp 11c0 \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11C6\nmov rdx, rdi\nmovsxd rax, esi\nlea r8, [rdi+rax*4]\nmov ecx, 0\nloc_1180:\nmov eax, ecx\nadd eax, [rdx]\nmov ecx, eax\nadd rdx, 4\ncmp rdx, r8\njnz short loc_1180\nmov ecx, [rdi]\nsub eax, ecx\njz short locret_11CB\nmov esi, esi\nmov edx, 1\nmov r8d, 0\nloc_11A2:\nadd r8d, ecx\ncmp rdx, rsi\njz short loc_11C0\nmov ecx, [rdi+rdx*4]\nsub eax, ecx\nlea r9, [rdx+1]\ncmp eax, r8d\njz short loc_11BD\nmov rdx, r9\njmp short loc_11A2\nloc_11BD:\nmov eax, edx\nretn\nloc_11C0:\nmov eax, 0FFFFFFFFh\nretn\nloc_11C6:\nmov eax, 0FFFFFFFFh\nlocret_11CB:\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rdx\n int v3; // ecx\n int v4; // eax\n int v5; // ecx\n __int64 result; // rax\n __int64 v7; // rdx\n int v8; // r8d\n\n if ( a2 <= 0 )\n return 0xFFFFFFFFLL;\n v2 = a1;\n v3 = 0;\n do\n {\n v4 = *v2 + v3;\n v3 = v4;\n ++v2;\n }\n while ( v2 != &a1[a2] );\n v5 = *a1;\n result = (unsigned int)(v4 - *a1);\n if ( (_DWORD)result )\n {\n v7 = 1LL;\n v8 = 0;\n while ( 1 )\n {\n v8 += v5;\n if ( v7 == a2 )\n break;\n v5 = a1[v7];\n LODWORD(result) = result - v5;\n if ( (_DWORD)result == v8 )\n return (unsigned int)v7;\n ++v7;\n }\n return 0xFFFFFFFFLL;\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11C6\nmov rdx, rdi\nmovsxd rax, esi\nlea r8, [rdi+rax*4]\nmov ecx, 0\nloc_1180:\nmov eax, ecx\nadd eax, [rdx]\nmov ecx, eax\nadd rdx, 4\ncmp rdx, r8\njnz short loc_1180\nmov ecx, [rdi]\nsub eax, ecx\njz short locret_11CB\nmov esi, esi\nmov edx, 1\nmov r8d, 0\nloc_11A2:\nadd r8d, ecx\ncmp rdx, rsi\njz short loc_11C0\nmov ecx, [rdi+rdx*4]\nsub eax, ecx\nlea r9, [rdx+1]\ncmp eax, r8d\njz short loc_11BD\nmov rdx, r9\njmp short loc_11A2\nloc_11BD:\nmov eax, edx\nretn\nloc_11C0:\nmov eax, 0FFFFFFFFh\nretn\nloc_11C6:\nmov eax, 0FFFFFFFFh\nlocret_11CB:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rdx\n int v3; // ecx\n int v4; // eax\n int v5; // ecx\n __int64 result; // rax\n __int64 v7; // rdx\n int v8; // r8d\n\n if ( a2 <= 0 )\n return 0xFFFFFFFFLL;\n v2 = a1;\n v3 = 0;\n do\n {\n v4 = *v2 + v3;\n v3 = v4;\n ++v2;\n }\n while ( v2 != &a1[a2] );\n v5 = *a1;\n result = (unsigned int)(v4 - *a1);\n if ( (_DWORD)result )\n {\n v7 = 1LL;\n v8 = 0;\n while ( 1 )\n {\n v8 += v5;\n if ( v7 == a2 )\n break;\n v5 = a1[v7];\n LODWORD(result) = result - v5;\n if ( (_DWORD)result == v8 )\n return (unsigned int)v7;\n ++v7;\n }\n return 0xFFFFFFFFLL;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2) {\n uint32_t *v2;\n int v3;\n int v4;\n int v5;\n long long result;\n long long v7;\n int v8;\n if (a2 <= 0) return 4294967295LL;\n v2 = a1;\n v3 = 0;\n do {\n v4 = *v2 + v3;\n v3 = v4;\n ++v2;\n } while (v2 != &a1[a2]);\n v5 = *a1;\n result = (unsigned int)(v4 - *a1);\n if ((uint32_t)result) {\n v7 = 1LL;\n v8 = 0;\n while (1) {\n v8 += v5;\n if (v7 == a2) break;\n v5 = a1[v7];\n LODWORD(result) = result - v5;\n if ((uint32_t)result == v8) return (unsigned int)v7;\n ++v7;\n }\n return 4294967295LL;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n int v3;\n int v4;\n int v5;\n long long result;\n long long v7;\n int v8;\n if (a2 <= 0) return 4294967295LL;\n v2 = a1;\n v3 = 0;\n do {\n v4 = *v2 + v3;\n v3 = v4;\n ++v2;\n } while (v2 != &a1[a2]);\n v5 = *a1;\n result = (unsigned int)(v4 - *a1);\n if ((uint32_t)result) {\n v7 = 1LL;\n v8 = 0;\n while (1) {\n v8 += v5;\n if (v7 == a2) break;\n v5 = a1[v7];\n LODWORD(result) = result - v5;\n if ((uint32_t)result == v8) return (unsigned int)v7;\n ++v7;\n }\n return 4294967295LL;\n }\n return result;\n}" + }, + { + "index": 701, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int total_sum = 0;\n for (int i = 0; i < n; i++) {\n total_sum += arr[i];\n }\n int left_sum = 0;\n for (int i = 0; i < n; i++) {\n total_sum -= arr[i];\n if (left_sum == total_sum) {\n return i;\n }\n left_sum += arr[i];\n }\n return -1;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4, 1, 2, 3};\n\n int arr2[] = {-7, 1, 5, 2, -4, 3, 0};\n\n int arr3[] = {1, 2, 3};\n\n\n\n assert(func0(arr1, 7) == 3);\n\n assert(func0(arr2, 7) == 3);\n\n assert(func0(arr3, 3) == -1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 12f7 \nlea -0x1(%rsi),%r8d\nmov %rdi,%rdx\nxor %eax,%eax\nlea 0x4(%rdi,%r8,4),%rcx\nnopw %cs:0x0(%rax,%rax,1)\nadd (%rdx),%eax\nadd $0x4,%rdx\ncmp %rcx,%rdx\njne 12c0 \nmov (%rdi),%ecx\nsub %ecx,%eax\nje 1301 \nadd $0x1,%r8\nmov $0x1,%edx\nxor %esi,%esi\njmp 12ed \nxchg %ax,%ax\nmov (%rdi,%rdx,4),%ecx\nadd $0x1,%rdx\nsub %ecx,%eax\ncmp %esi,%eax\nje 12fd \nadd %ecx,%esi\nmov %edx,%r9d\ncmp %r8,%rdx\njne 12e0 \nmov $0xffffffff,%r9d\nmov %r9d,%eax\nretq\nxor %r9d,%r9d\njmp 12fd \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_12E1\nmovsxd rax, esi\nmov rdx, rdi\nlea rcx, [rdi+rax*4]\nxor eax, eax\nnop dword ptr [rax+00h]\nloc_12A8:\nadd eax, [rdx]\nadd rdx, 4\ncmp rdx, rcx\njnz short loc_12A8\nmov ecx, [rdi]\nsub eax, ecx\njz short locret_12E6\nmov esi, esi\nmov edx, 1\nxor r8d, r8d\njmp short loc_12D9\nloc_12C8:\nmov ecx, [rdi+rdx*4]\nlea r9, [rdx+1]\nsub eax, ecx\ncmp eax, r8d\njz short loc_12F0\nmov rdx, r9\nloc_12D9:\nadd r8d, ecx\ncmp rdx, rsi\njnz short loc_12C8\nloc_12E1:\nmov eax, 0FFFFFFFFh\nlocret_12E6:\nretn\nloc_12F0:\nmov eax, edx\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rdx\n int v3; // eax\n int v4; // ecx\n __int64 result; // rax\n __int64 v6; // rdx\n int v7; // r8d\n\n if ( a2 <= 0 )\n return 0xFFFFFFFFLL;\n v2 = a1;\n v3 = 0;\n do\n v3 += *v2++;\n while ( v2 != &a1[a2] );\n v4 = *a1;\n result = (unsigned int)(v3 - *a1);\n if ( (_DWORD)result )\n {\n v6 = 1LL;\n v7 = 0;\n while ( 1 )\n {\n v7 += v4;\n if ( v6 == a2 )\n break;\n v4 = a1[v6];\n LODWORD(result) = result - v4;\n if ( (_DWORD)result == v7 )\n return (unsigned int)v6;\n ++v6;\n }\n return 0xFFFFFFFFLL;\n }\n return result;\n}", + "ida_strip_asm": "sub_1290:\nendbr64\ntest esi, esi\njle short loc_12E1\nmovsxd rax, esi\nmov rdx, rdi\nlea rcx, [rdi+rax*4]\nxor eax, eax\nnop dword ptr [rax+00h]\nloc_12A8:\nadd eax, [rdx]\nadd rdx, 4\ncmp rdx, rcx\njnz short loc_12A8\nmov ecx, [rdi]\nsub eax, ecx\njz short locret_12E6\nmov esi, esi\nmov edx, 1\nxor r8d, r8d\njmp short loc_12D9\nloc_12C8:\nmov ecx, [rdi+rdx*4]\nlea r9, [rdx+1]\nsub eax, ecx\ncmp eax, r8d\njz short loc_12F0\nmov rdx, r9\nloc_12D9:\nadd r8d, ecx\ncmp rdx, rsi\njnz short loc_12C8\nloc_12E1:\nmov eax, 0FFFFFFFFh\nlocret_12E6:\nretn\nloc_12F0:\nmov eax, edx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1290(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rdx\n int v3; // eax\n int v4; // ecx\n __int64 result; // rax\n __int64 v6; // rdx\n int v7; // r8d\n\n if ( a2 <= 0 )\n return 0xFFFFFFFFLL;\n v2 = a1;\n v3 = 0;\n do\n v3 += *v2++;\n while ( v2 != &a1[a2] );\n v4 = *a1;\n result = (unsigned int)(v3 - *a1);\n if ( (_DWORD)result )\n {\n v6 = 1LL;\n v7 = 0;\n while ( 1 )\n {\n v7 += v4;\n if ( v6 == a2 )\n break;\n v4 = a1[v6];\n LODWORD(result) = result - v4;\n if ( (_DWORD)result == v7 )\n return (unsigned int)v6;\n ++v6;\n }\n return 0xFFFFFFFFLL;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1290(uint32_t *a1, int a2) {\n uint32_t *v2;\n int v3;\n int v4;\n long long result;\n long long v6;\n int v7;\n if (a2 <= 0) return 4294967295LL;\n v2 = a1;\n v3 = 0;\n do\n v3 += *v2++;\n while (v2 != &a1[a2]);\n v4 = *a1;\n result = (unsigned int)(v3 - *a1);\n if ((uint32_t)result) {\n v6 = 1LL;\n v7 = 0;\n while (1) {\n v7 += v4;\n if (v6 == a2) break;\n v4 = a1[v6];\n LODWORD(result) = result - v4;\n if ((uint32_t)result == v7) return (unsigned int)v6;\n ++v6;\n }\n return 4294967295LL;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n int v3;\n int v4;\n long long result;\n long long v6;\n int v7;\n if (a2 <= 0) return 4294967295LL;\n v2 = a1;\n v3 = 0;\n do\n v3 += *v2++;\n while (v2 != &a1[a2]);\n v4 = *a1;\n result = (unsigned int)(v3 - *a1);\n if ((uint32_t)result) {\n v6 = 1LL;\n v7 = 0;\n while (1) {\n v7 += v4;\n if (v6 == a2) break;\n v4 = a1[v6];\n LODWORD(result) = result - v4;\n if ((uint32_t)result == v7) return (unsigned int)v6;\n ++v6;\n }\n return 4294967295LL;\n }\n return result;\n}" + }, + { + "index": 702, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\nint find_ind(int key, int i, int n, int k, int arr[]) {\n\n int ind = -1;\n\n int start = i + 1;\n\n int end = n - 1;\n\n while (start < end) {\n\n int mid = start + (end - start) / 2;\n\n if (arr[mid] - key <= k) {\n\n ind = mid;\n\n start = mid + 1;\n\n } else {\n\n end = mid;\n\n }\n\n }\n\n return ind;\n\n}\n\n\n\n", + "func": "int func0(int arr[], int n, int k) {\n int ans = n - 1;\n qsort(arr, n, sizeof(int), (int (*)(const void *, const void *))strcmp);\n for (int i = 0; i < n; i++) {\n int j = find_ind(arr[i], i, n, k, arr);\n if (j != -1) {\n ans = (ans < n - (j - i + 1) ? ans : n - (j - i + 1));\n }\n }\n return ans;\n}", + "test": "int main() {\n\n int arr1[] = {1, 3, 4, 9, 10, 11, 12, 17, 20};\n\n assert(func0(arr1, 9, 4) == 5);\n\n\n\n int arr2[] = {1, 5, 6, 2, 8};\n\n assert(func0(arr2, 5, 2) == 3);\n\n\n\n int arr3[] = {1, 2, 3, 4, 5, 6};\n\n assert(func0(arr3, 6, 3) == 2);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmov -0x1c(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0xc(%rbp)\nmov -0x1c(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x18(%rbp),%rax\nmov 0x2d99(%rip),%rdx\nmov %rdx,%rcx\nmov $0x4,%edx\nmov %rax,%rdi\ncallq 1070 \nmovl $0x0,-0x8(%rbp)\njmp 12b2 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov -0x18(%rbp),%rdi\nmov -0x20(%rbp),%ecx\nmov -0x1c(%rbp),%edx\nmov -0x8(%rbp),%esi\nmov %rdi,%r8\nmov %eax,%edi\ncallq 1189 \nmov %eax,-0x4(%rbp)\ncmpl $0xffffffff,-0x4(%rbp)\nje 12ae \nmov -0x4(%rbp),%eax\nsub -0x8(%rbp),%eax\nlea 0x1(%rax),%edx\nmov -0x1c(%rbp),%eax\nsub %edx,%eax\ncmp %eax,-0xc(%rbp)\ncmovle -0xc(%rbp),%eax\nmov %eax,-0xc(%rbp)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1260 \nmov -0xc(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+base], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov eax, [rbp+var_1C]\nsub eax, 1\nmov [rbp+var_C], eax\nmov eax, [rbp+var_1C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nmov rdx, cs:compar\nmov rcx, rdx; compar\nmov edx, 4; size\nmov rdi, rax; base\ncall _qsort\nmov [rbp+var_8], 0\njmp short loc_12B3\nloc_1260:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rdx\nmov eax, [rax]\nmov rdi, [rbp+base]\nmov ecx, [rbp+var_20]\nmov edx, [rbp+var_1C]\nmov esi, [rbp+var_8]\nmov r8, rdi\nmov edi, eax\ncall find_ind\nmov [rbp+var_4], eax\ncmp [rbp+var_4], 0FFFFFFFFh\njz short loc_12AF\nmov eax, [rbp+var_4]\nsub eax, [rbp+var_8]\nlea edx, [rax+1]\nmov eax, [rbp+var_1C]\nsub eax, edx\nmov edx, [rbp+var_C]\ncmp edx, eax\ncmovle eax, edx\nmov [rbp+var_C], eax\nloc_12AF:\nadd [rbp+var_8], 1\nloc_12B3:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_1260\nmov eax, [rbp+var_C]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, unsigned int a2, unsigned int a3)\n{\n int v3; // eax\n unsigned int v6; // [rsp+14h] [rbp-Ch]\n unsigned int i; // [rsp+18h] [rbp-8h]\n int ind; // [rsp+1Ch] [rbp-4h]\n\n v6 = a2 - 1;\n qsort(a1, (int)a2, 4uLL, (__compar_fn_t)&strcmp);\n for ( i = 0; (int)i < (int)a2; ++i )\n {\n ind = find_ind(a1[i], i, a2, a3, a1);\n if ( ind != -1 )\n {\n v3 = a2 - (ind - i + 1);\n if ( (int)v6 <= v3 )\n v3 = v6;\n v6 = v3;\n }\n }\n return v6;\n}", + "ida_strip_asm": "sub_1217:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+base], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov eax, [rbp+var_1C]\nsub eax, 1\nmov [rbp+var_C], eax\nmov eax, [rbp+var_1C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nmov rdx, cs:compar\nmov rcx, rdx; compar\nmov edx, 4; size\nmov rdi, rax; base\ncall _qsort\nmov [rbp+var_8], 0\njmp short loc_12B3\nloc_1260:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rdx\nmov eax, [rax]\nmov rdi, [rbp+base]\nmov ecx, [rbp+var_20]\nmov edx, [rbp+var_1C]\nmov esi, [rbp+var_8]\nmov r8, rdi\nmov edi, eax\ncall sub_1189\nmov [rbp+var_4], eax\ncmp [rbp+var_4], 0FFFFFFFFh\njz short loc_12AF\nmov eax, [rbp+var_4]\nsub eax, [rbp+var_8]\nlea edx, [rax+1]\nmov eax, [rbp+var_1C]\nsub eax, edx\nmov edx, [rbp+var_C]\ncmp edx, eax\ncmovle eax, edx\nmov [rbp+var_C], eax\nloc_12AF:\nadd [rbp+var_8], 1\nloc_12B3:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_1260\nmov eax, [rbp+var_C]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1217(unsigned int *a1, unsigned int a2, unsigned int a3)\n{\n int v3; // eax\n unsigned int v6; // [rsp+14h] [rbp-Ch]\n unsigned int i; // [rsp+18h] [rbp-8h]\n int v8; // [rsp+1Ch] [rbp-4h]\n\n v6 = a2 - 1;\n qsort(a1, (int)a2, 4uLL, (__compar_fn_t)&strcmp);\n for ( i = 0; (int)i < (int)a2; ++i )\n {\n v8 = sub_1189(a1[i], i, a2, a3, a1);\n if ( v8 != -1 )\n {\n v3 = a2 - (v8 - i + 1);\n if ( (int)v6 <= v3 )\n v3 = v6;\n v6 = v3;\n }\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1217(unsigned int *a1, unsigned int a2, unsigned int a3) {\n int v3;\n unsigned int v6;\n unsigned int i;\n int v8;\n v6 = a2 - 1;\n qsort(a1, (int)a2, 4uLL, (int (*)(const void *, const void *)) & strcmp);\n for (i = 0; (int)i < (int)a2; ++i) {\n v8 = sub_1189(a1[i], i, a2, a3, a1);\n if (v8 != -1) {\n v3 = a2 - (v8 - i + 1);\n if ((int)v6 <= v3) v3 = v6;\n v6 = v3;\n }\n }\n return v6;\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, unsigned int a2, unsigned int a3) {\n int v3;\n unsigned int v6;\n unsigned int i;\n int ind;\n v6 = a2 - 1;\n qsort(a1, (int)a2, 4uLL, (int (*)(const void *, const void *)) & strcmp);\n for (i = 0; (int)i < (int)a2; ++i) {\n ind = find_ind(a1[i], i, a2, a3, a1);\n if (ind != -1) {\n v3 = a2 - (ind - i + 1);\n if ((int)v6 <= v3) v3 = v6;\n v6 = v3;\n }\n }\n return v6;\n}" + }, + { + "index": 702, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\nint find_ind(int key, int i, int n, int k, int arr[]) {\n\n int ind = -1;\n\n int start = i + 1;\n\n int end = n - 1;\n\n while (start < end) {\n\n int mid = start + (end - start) / 2;\n\n if (arr[mid] - key <= k) {\n\n ind = mid;\n\n start = mid + 1;\n\n } else {\n\n end = mid;\n\n }\n\n }\n\n return ind;\n\n}\n\n\n\n", + "func": "int func0(int arr[], int n, int k) {\n int ans = n - 1;\n qsort(arr, n, sizeof(int), (int (*)(const void *, const void *))strcmp);\n for (int i = 0; i < n; i++) {\n int j = find_ind(arr[i], i, n, k, arr);\n if (j != -1) {\n ans = (ans < n - (j - i + 1) ? ans : n - (j - i + 1));\n }\n }\n return ans;\n}", + "test": "int main() {\n\n int arr1[] = {1, 3, 4, 9, 10, 11, 12, 17, 20};\n\n assert(func0(arr1, 9, 4) == 5);\n\n\n\n int arr2[] = {1, 5, 6, 2, 8};\n\n assert(func0(arr2, 5, 2) == 3);\n\n\n\n int arr3[] = {1, 2, 3, 4, 5, 6};\n\n assert(func0(arr3, 6, 3) == 2);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%r12\nmov %esi,%ebp\nmov %edx,%r14d\nlea -0x1(%rsi),%r13d\nmovslq %esi,%rsi\nmov 0x2deb(%rip),%rcx\nmov $0x4,%edx\ncallq 1070 \ntest %ebp,%ebp\njle 1244 \nlea -0x1(%rbp),%r15d\nmov $0x0,%ebx\njmp 122a \nsub %ebx,%eax\nadd $0x1,%eax\nmov %ebp,%ecx\nsub %eax,%ecx\ncmp %ecx,%r13d\ncmovg %ecx,%r13d\nlea 0x1(%rbx),%rax\ncmp %rbx,%r15\nje 1244 \nmov %rax,%rbx\nmov (%r12,%rbx,4),%edi\nmov %r12,%r8\nmov %r14d,%ecx\nmov %ebp,%edx\nmov %ebx,%esi\ncallq 1189 \ncmp $0xffffffff,%eax\njne 120e \njmp 121e \nmov %r13d,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov r12d, esi\nmov r14d, edx\nlea r13d, [rsi-1]\nmovsxd r15, esi\nmov rcx, cs:compar; compar\nmov edx, 4; size\nmov rsi, r15; nmemb\ncall _qsort\ntest r12d, r12d\njle short loc_1244\nmov ebx, 0\njmp short loc_1218\nloc_120F:\nadd rbx, 1\ncmp r15, rbx\njz short loc_1244\nloc_1218:\nmov esi, ebx\nmov edi, [rbp+rbx*4+0]\nmov r8, rbp\nmov ecx, r14d\nmov edx, r12d\ncall find_ind\ncmp eax, 0FFFFFFFFh\njz short loc_120F\nsub eax, ebx\nadd eax, 1\nmov edx, r12d\nsub edx, eax\ncmp r13d, edx\ncmovg r13d, edx\njmp short loc_120F\nloc_1244:\nmov eax, r13d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2, unsigned int a3)\n{\n int v4; // r13d\n __int64 i; // rbx\n int ind; // eax\n\n v4 = a2 - 1;\n qsort(a1, a2, 4uLL, (__compar_fn_t)&strcmp);\n if ( a2 > 0 )\n {\n for ( i = 0LL; i != a2; ++i )\n {\n ind = find_ind(a1[i], (unsigned int)i, (unsigned int)a2, a3, a1);\n if ( ind != -1 && v4 > a2 - (ind - (int)i + 1) )\n v4 = a2 - (ind - i + 1);\n }\n }\n return (unsigned int)v4;\n}", + "ida_strip_asm": "sub_11CD:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov r12d, esi\nmov r14d, edx\nlea r13d, [rsi-1]\nmovsxd r15, esi\nmov rcx, cs:compar; compar\nmov edx, 4; size\nmov rsi, r15; nmemb\ncall _qsort\ntest r12d, r12d\njle short loc_1244\nmov ebx, 0\njmp short loc_1218\nloc_120F:\nadd rbx, 1\ncmp r15, rbx\njz short loc_1244\nloc_1218:\nmov esi, ebx\nmov edi, [rbp+rbx*4+0]\nmov r8, rbp\nmov ecx, r14d\nmov edx, r12d\ncall sub_1189\ncmp eax, 0FFFFFFFFh\njz short loc_120F\nsub eax, ebx\nadd eax, 1\nmov edx, r12d\nsub edx, eax\ncmp r13d, edx\ncmovg r13d, edx\njmp short loc_120F\nloc_1244:\nmov eax, r13d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11CD(unsigned int *a1, int a2, unsigned int a3)\n{\n int v4; // r13d\n __int64 i; // rbx\n int v6; // eax\n\n v4 = a2 - 1;\n qsort(a1, a2, 4uLL, (__compar_fn_t)&strcmp);\n if ( a2 > 0 )\n {\n for ( i = 0LL; i != a2; ++i )\n {\n v6 = sub_1189(a1[i], (unsigned int)i, (unsigned int)a2, a3, a1);\n if ( v6 != -1 && v4 > a2 - (v6 - (int)i + 1) )\n v4 = a2 - (v6 - i + 1);\n }\n }\n return (unsigned int)v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11CD(unsigned int *a1, int a2, unsigned int a3) {\n int v4;\n long long i;\n int v6;\n v4 = a2 - 1;\n qsort(a1, a2, 4uLL, (int (*)(const void *, const void *)) & strcmp);\n if (a2 > 0) {\n for (i = 0LL; i != a2; ++i) {\n v6 = sub_1189(a1[i], (unsigned int)i, (unsigned int)a2, a3, a1);\n if (v6 != -1 && v4 > a2 - (v6 - (int)i + 1)) v4 = a2 - (v6 - i + 1);\n }\n }\n return (unsigned int)v4;\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2, unsigned int a3) {\n int v4;\n long long i;\n int ind;\n v4 = a2 - 1;\n qsort(a1, a2, 4uLL, (int (*)(const void *, const void *)) & strcmp);\n if (a2 > 0) {\n for (i = 0LL; i != a2; ++i) {\n ind = find_ind(a1[i], (unsigned int)i, (unsigned int)a2, a3, a1);\n if (ind != -1 && v4 > a2 - (ind - (int)i + 1)) v4 = a2 - (ind - i + 1);\n }\n }\n return (unsigned int)v4;\n}" + }, + { + "index": 702, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\nint find_ind(int key, int i, int n, int k, int arr[]) {\n\n int ind = -1;\n\n int start = i + 1;\n\n int end = n - 1;\n\n while (start < end) {\n\n int mid = start + (end - start) / 2;\n\n if (arr[mid] - key <= k) {\n\n ind = mid;\n\n start = mid + 1;\n\n } else {\n\n end = mid;\n\n }\n\n }\n\n return ind;\n\n}\n\n\n\n", + "func": "int func0(int arr[], int n, int k) {\n int ans = n - 1;\n qsort(arr, n, sizeof(int), (int (*)(const void *, const void *))strcmp);\n for (int i = 0; i < n; i++) {\n int j = find_ind(arr[i], i, n, k, arr);\n if (j != -1) {\n ans = (ans < n - (j - i + 1) ? ans : n - (j - i + 1));\n }\n }\n return ans;\n}", + "test": "int main() {\n\n int arr1[] = {1, 3, 4, 9, 10, 11, 12, 17, 20};\n\n assert(func0(arr1, 9, 4) == 5);\n\n\n\n int arr2[] = {1, 5, 6, 2, 8};\n\n assert(func0(arr2, 5, 2) == 3);\n\n\n\n int arr3[] = {1, 2, 3, 4, 5, 6};\n\n assert(func0(arr3, 6, 3) == 2);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\nmovslq %esi,%rsi\nmov 0x2c70(%rip),%rcx\npush %r13\nmov %rsi,%r13\npush %r12\nlea -0x1(%rsi),%r12d\npush %rbp\nmov %edx,%ebp\nmov $0x4,%edx\npush %rbx\nmov %rdi,%rbx\ncallq 1070 \ntest %r13d,%r13d\njle 1410 \nmov %r12d,%r14d\nmov %r12d,%r10d\nxor %r9d,%r9d\nnopw 0x0(%rax,%rax,1)\nmov (%rbx,%r9,4),%edi\nmov %r9d,%r11d\nlea 0x1(%r9),%ecx\nmov %r12d,%esi\nmov $0xffffffff,%r8d\njmp 13d6 \nnopw %cs:0x0(%rax,%rax,1)\nmov %esi,%eax\nsub %ecx,%eax\nsar %eax\nadd %ecx,%eax\nmovslq %eax,%rdx\nmov (%rbx,%rdx,4),%edx\nsub %edi,%edx\ncmp %edx,%ebp\njge 1408 \nmov %eax,%esi\ncmp %ecx,%esi\njg 13c0 \ncmp $0xffffffff,%r8d\nje 13f4 \nsub %r11d,%r8d\nmov %r13d,%eax\nadd $0x1,%r8d\nsub %r8d,%eax\ncmp %eax,%r10d\ncmovg %eax,%r10d\nlea 0x1(%r9),%rax\ncmp %r14,%r9\nje 1413 \nmov %rax,%r9\njmp 13a0 \nnopw 0x0(%rax,%rax,1)\nlea 0x1(%rax),%ecx\nmov %eax,%r8d\njmp 13d6 \nmov %r12d,%r10d\npop %rbx\nmov %r10d,%eax\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\n", + "ida_asm": "func0:\nendbr64\npush r14\nmov rcx, cs:compar; compar\nmovsxd r14, esi\npush r13\nmov rsi, r14; nmemb\nlea r13d, [r14-1]\npush r12\npush rbp\nmov ebp, edx\nmov edx, 4; size\npush rbx\nmov rbx, rdi\ncall _qsort\ntest r14d, r14d\njle short loc_13C0\nmov r12, r14\nmov r10d, r13d\nxor r9d, r9d\nnop word ptr [rax+rax+00h]\nloc_1350:\nmov edi, [rbx+r9*4]\nlea ecx, [r9+1]\nmov esi, r13d\nmov r8d, 0FFFFFFFFh\njmp short loc_137E\nloc_1368:\nmov eax, esi\nsub eax, ecx\nsar eax, 1\nadd eax, ecx\nmovsxd rdx, eax\nmov edx, [rbx+rdx*4]\nsub edx, edi\ncmp ebp, edx\njge short loc_13B8\nmov esi, eax\nloc_137E:\ncmp esi, ecx\njg short loc_1368\ncmp r8d, 0FFFFFFFFh\njz short loc_139C\nsub r8d, r9d\nmov eax, r12d\nadd r8d, 1\nsub eax, r8d\ncmp r10d, eax\ncmovg r10d, eax\nloc_139C:\nadd r9, 1\ncmp r14, r9\njnz short loc_1350\npop rbx\nmov eax, r10d\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_13B8:\nlea ecx, [rax+1]\nmov r8d, eax\njmp short loc_137E\nloc_13C0:\nmov r10d, r13d\npop rbx\npop rbp\nmov eax, r10d\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "__int64 __fastcall func0(void *a1, int a2, int a3)\n{\n __int64 v3; // r14\n unsigned int v4; // r13d\n int v6; // r10d\n __int64 v7; // r9\n int v8; // ecx\n signed int v9; // esi\n int v10; // r8d\n int v11; // eax\n\n v3 = a2;\n v4 = a2 - 1;\n qsort(a1, a2, 4uLL, (__compar_fn_t)&strcmp);\n if ( a2 <= 0 )\n return v4;\n v6 = a2 - 1;\n v7 = 0LL;\n do\n {\n v8 = v7 + 1;\n v9 = v4;\n v10 = -1;\n while ( v9 > v8 )\n {\n v11 = v8 + ((v9 - v8) >> 1);\n if ( a3 >= *((_DWORD *)a1 + v11) - *((_DWORD *)a1 + v7) )\n {\n v8 = v11 + 1;\n v10 = v11;\n }\n else\n {\n v9 = v8 + ((v9 - v8) >> 1);\n }\n }\n if ( v10 != -1 && v6 > (int)v3 - (v10 - (int)v7 + 1) )\n v6 = v3 - (v10 - v7 + 1);\n ++v7;\n }\n while ( v3 != v7 );\n return (unsigned int)v6;\n}", + "ida_strip_asm": "sub_1310:\nendbr64\npush r14\nmov rcx, cs:compar; compar\nmovsxd r14, esi\npush r13\nmov rsi, r14; nmemb\nlea r13d, [r14-1]\npush r12\npush rbp\nmov ebp, edx\nmov edx, 4; size\npush rbx\nmov rbx, rdi\ncall _qsort\ntest r14d, r14d\njle short loc_13C0\nmov r12, r14\nmov r10d, r13d\nxor r9d, r9d\nnop word ptr [rax+rax+00h]\nloc_1350:\nmov edi, [rbx+r9*4]\nlea ecx, [r9+1]\nmov esi, r13d\nmov r8d, 0FFFFFFFFh\njmp short loc_137E\nloc_1368:\nmov eax, esi\nsub eax, ecx\nsar eax, 1\nadd eax, ecx\nmovsxd rdx, eax\nmov edx, [rbx+rdx*4]\nsub edx, edi\ncmp ebp, edx\njge short loc_13B8\nmov esi, eax\nloc_137E:\ncmp esi, ecx\njg short loc_1368\ncmp r8d, 0FFFFFFFFh\njz short loc_139C\nsub r8d, r9d\nmov eax, r12d\nadd r8d, 1\nsub eax, r8d\ncmp r10d, eax\ncmovg r10d, eax\nloc_139C:\nadd r9, 1\ncmp r14, r9\njnz short loc_1350\npop rbx\nmov eax, r10d\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_13B8:\nlea ecx, [rax+1]\nmov r8d, eax\njmp short loc_137E\nloc_13C0:\nmov r10d, r13d\npop rbx\npop rbp\nmov eax, r10d\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1310(void *a1, int a2, int a3)\n{\n __int64 v3; // r14\n unsigned int v4; // r13d\n int v6; // r10d\n __int64 v7; // r9\n int v8; // ecx\n signed int v9; // esi\n int v10; // r8d\n int v11; // eax\n\n v3 = a2;\n v4 = a2 - 1;\n qsort(a1, a2, 4uLL, (__compar_fn_t)&strcmp);\n if ( a2 <= 0 )\n return v4;\n v6 = a2 - 1;\n v7 = 0LL;\n do\n {\n v8 = v7 + 1;\n v9 = v4;\n v10 = -1;\n while ( v9 > v8 )\n {\n v11 = v8 + ((v9 - v8) >> 1);\n if ( a3 >= *((_DWORD *)a1 + v11) - *((_DWORD *)a1 + v7) )\n {\n v8 = v11 + 1;\n v10 = v11;\n }\n else\n {\n v9 = v8 + ((v9 - v8) >> 1);\n }\n }\n if ( v10 != -1 && v6 > (int)v3 - (v10 - (int)v7 + 1) )\n v6 = v3 - (v10 - v7 + 1);\n ++v7;\n }\n while ( v3 != v7 );\n return (unsigned int)v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1310(void *a1, int a2, int a3) {\n long long v3;\n unsigned int v4;\n int v6;\n long long v7;\n int v8;\n signed int v9;\n int v10;\n int v11;\n v3 = a2;\n v4 = a2 - 1;\n qsort(a1, a2, 4uLL, (int (*)(const void *, const void *)) & strcmp);\n if (a2 <= 0) return v4;\n v6 = a2 - 1;\n v7 = 0LL;\n do {\n v8 = v7 + 1;\n v9 = v4;\n v10 = -1;\n while (v9 > v8) {\n v11 = v8 + ((v9 - v8) >> 1);\n if (a3 >= *((uint32_t *)a1 + v11) - *((uint32_t *)a1 + v7)) {\n v8 = v11 + 1;\n v10 = v11;\n } else {\n v9 = v8 + ((v9 - v8) >> 1);\n }\n }\n if (v10 != -1 && v6 > (int)v3 - (v10 - (int)v7 + 1))\n v6 = v3 - (v10 - v7 + 1);\n ++v7;\n } while (v3 != v7);\n return (unsigned int)v6;\n}", + "ida_pseudo_norm": "long long func0(void *a1, int a2, int a3) {\n long long v3;\n unsigned int v4;\n int v6;\n long long v7;\n int v8;\n signed int v9;\n int v10;\n int v11;\n v3 = a2;\n v4 = a2 - 1;\n qsort(a1, a2, 4uLL, (int (*)(const void *, const void *)) & strcmp);\n if (a2 <= 0) return v4;\n v6 = a2 - 1;\n v7 = 0LL;\n do {\n v8 = v7 + 1;\n v9 = v4;\n v10 = -1;\n while (v9 > v8) {\n v11 = v8 + ((v9 - v8) >> 1);\n if (a3 >= *((uint32_t *)a1 + v11) - *((uint32_t *)a1 + v7)) {\n v8 = v11 + 1;\n v10 = v11;\n } else {\n v9 = v8 + ((v9 - v8) >> 1);\n }\n }\n if (v10 != -1 && v6 > (int)v3 - (v10 - (int)v7 + 1))\n v6 = v3 - (v10 - v7 + 1);\n ++v7;\n } while (v3 != v7);\n return (unsigned int)v6;\n}" + }, + { + "index": 702, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\nint find_ind(int key, int i, int n, int k, int arr[]) {\n\n int ind = -1;\n\n int start = i + 1;\n\n int end = n - 1;\n\n while (start < end) {\n\n int mid = start + (end - start) / 2;\n\n if (arr[mid] - key <= k) {\n\n ind = mid;\n\n start = mid + 1;\n\n } else {\n\n end = mid;\n\n }\n\n }\n\n return ind;\n\n}\n\n\n\n", + "func": "int func0(int arr[], int n, int k) {\n int ans = n - 1;\n qsort(arr, n, sizeof(int), (int (*)(const void *, const void *))strcmp);\n for (int i = 0; i < n; i++) {\n int j = find_ind(arr[i], i, n, k, arr);\n if (j != -1) {\n ans = (ans < n - (j - i + 1) ? ans : n - (j - i + 1));\n }\n }\n return ans;\n}", + "test": "int main() {\n\n int arr1[] = {1, 3, 4, 9, 10, 11, 12, 17, 20};\n\n assert(func0(arr1, 9, 4) == 5);\n\n\n\n int arr2[] = {1, 5, 6, 2, 8};\n\n assert(func0(arr2, 5, 2) == 3);\n\n\n\n int arr3[] = {1, 2, 3, 4, 5, 6};\n\n assert(func0(arr3, 6, 3) == 2);\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\nmovslq %esi,%rsi\nmov 0x2cc0(%rip),%rcx\npush %r13\nmov %rsi,%r13\npush %r12\nlea -0x1(%rsi),%r12d\npush %rbp\nmov %edx,%ebp\nmov $0x4,%edx\npush %rbx\nmov %rdi,%rbx\ncallq 1070 \ntest %r13d,%r13d\njle 13c0 \nmov %r12d,%r14d\nmov %r12d,%r10d\nxor %r9d,%r9d\nnopw 0x0(%rax,%rax,1)\nmov (%rbx,%r9,4),%edi\nmov %r9d,%r11d\nlea 0x1(%r9),%ecx\nmov %r12d,%esi\nmov $0xffffffff,%r8d\njmp 1386 \nnopw %cs:0x0(%rax,%rax,1)\nmov %esi,%eax\nsub %ecx,%eax\nsar %eax\nadd %ecx,%eax\nmovslq %eax,%rdx\nmov (%rbx,%rdx,4),%edx\nsub %edi,%edx\ncmp %edx,%ebp\njge 13b8 \nmov %eax,%esi\ncmp %ecx,%esi\njg 1370 \ncmp $0xffffffff,%r8d\nje 13a4 \nsub %r11d,%r8d\nmov %r13d,%eax\nadd $0x1,%r8d\nsub %r8d,%eax\ncmp %eax,%r10d\ncmovg %eax,%r10d\nlea 0x1(%r9),%rax\ncmp %r9,%r14\nje 13c3 \nmov %rax,%r9\njmp 1350 \nnopw 0x0(%rax,%rax,1)\nlea 0x1(%rax),%ecx\nmov %eax,%r8d\njmp 1386 \nmov %r12d,%r10d\npop %rbx\nmov %r10d,%eax\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\n", + "ida_asm": "func0:\nendbr64\npush r14\nmov rcx, cs:compar; compar\nmovsxd r14, esi\npush r13\nmov rsi, r14; nmemb\nlea r13d, [r14-1]\npush r12\npush rbp\nmov ebp, edx\nmov edx, 4; size\npush rbx\nmov rbx, rdi\ncall _qsort\ntest r14d, r14d\njle short loc_13C0\nmov r12, r14\nmov r10d, r13d\nxor r9d, r9d\nnop word ptr [rax+rax+00h]\nloc_1350:\nmov edi, [rbx+r9*4]\nlea ecx, [r9+1]\nmov esi, r13d\nmov r8d, 0FFFFFFFFh\njmp short loc_137E\nloc_1368:\nmov eax, esi\nsub eax, ecx\nsar eax, 1\nadd eax, ecx\nmovsxd rdx, eax\nmov edx, [rbx+rdx*4]\nsub edx, edi\ncmp ebp, edx\njge short loc_13B8\nmov esi, eax\nloc_137E:\ncmp esi, ecx\njg short loc_1368\ncmp r8d, 0FFFFFFFFh\njz short loc_139C\nsub r8d, r9d\nmov eax, r12d\nadd r8d, 1\nsub eax, r8d\ncmp r10d, eax\ncmovg r10d, eax\nloc_139C:\nadd r9, 1\ncmp r14, r9\njnz short loc_1350\npop rbx\nmov eax, r10d\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_13B8:\nlea ecx, [rax+1]\nmov r8d, eax\njmp short loc_137E\nloc_13C0:\nmov r10d, r13d\npop rbx\npop rbp\nmov eax, r10d\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "__int64 __fastcall func0(void *a1, int a2, int a3)\n{\n __int64 v3; // r14\n unsigned int v4; // r13d\n int v6; // r10d\n __int64 v7; // r9\n int v8; // ecx\n signed int v9; // esi\n int v10; // r8d\n int v11; // eax\n\n v3 = a2;\n v4 = a2 - 1;\n qsort(a1, a2, 4uLL, (__compar_fn_t)&strcmp);\n if ( a2 <= 0 )\n return v4;\n v6 = a2 - 1;\n v7 = 0LL;\n do\n {\n v8 = v7 + 1;\n v9 = v4;\n v10 = -1;\n while ( v9 > v8 )\n {\n v11 = v8 + ((v9 - v8) >> 1);\n if ( a3 >= *((_DWORD *)a1 + v11) - *((_DWORD *)a1 + v7) )\n {\n v8 = v11 + 1;\n v10 = v11;\n }\n else\n {\n v9 = v8 + ((v9 - v8) >> 1);\n }\n }\n if ( v10 != -1 && v6 > (int)v3 - (v10 - (int)v7 + 1) )\n v6 = v3 - (v10 - v7 + 1);\n ++v7;\n }\n while ( v3 != v7 );\n return (unsigned int)v6;\n}", + "ida_strip_asm": "sub_1310:\nendbr64\npush r14\nmov rcx, cs:compar; compar\nmovsxd r14, esi\npush r13\nmov rsi, r14; nmemb\nlea r13d, [r14-1]\npush r12\npush rbp\nmov ebp, edx\nmov edx, 4; size\npush rbx\nmov rbx, rdi\ncall _qsort\ntest r14d, r14d\njle short loc_13C0\nmov r12, r14\nmov r10d, r13d\nxor r9d, r9d\nnop word ptr [rax+rax+00h]\nloc_1350:\nmov edi, [rbx+r9*4]\nlea ecx, [r9+1]\nmov esi, r13d\nmov r8d, 0FFFFFFFFh\njmp short loc_137E\nloc_1368:\nmov eax, esi\nsub eax, ecx\nsar eax, 1\nadd eax, ecx\nmovsxd rdx, eax\nmov edx, [rbx+rdx*4]\nsub edx, edi\ncmp ebp, edx\njge short loc_13B8\nmov esi, eax\nloc_137E:\ncmp esi, ecx\njg short loc_1368\ncmp r8d, 0FFFFFFFFh\njz short loc_139C\nsub r8d, r9d\nmov eax, r12d\nadd r8d, 1\nsub eax, r8d\ncmp r10d, eax\ncmovg r10d, eax\nloc_139C:\nadd r9, 1\ncmp r14, r9\njnz short loc_1350\npop rbx\nmov eax, r10d\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_13B8:\nlea ecx, [rax+1]\nmov r8d, eax\njmp short loc_137E\nloc_13C0:\nmov r10d, r13d\npop rbx\npop rbp\nmov eax, r10d\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1310(void *a1, int a2, int a3)\n{\n __int64 v3; // r14\n unsigned int v4; // r13d\n int v6; // r10d\n __int64 v7; // r9\n int v8; // ecx\n signed int v9; // esi\n int v10; // r8d\n int v11; // eax\n\n v3 = a2;\n v4 = a2 - 1;\n qsort(a1, a2, 4uLL, (__compar_fn_t)&strcmp);\n if ( a2 <= 0 )\n return v4;\n v6 = a2 - 1;\n v7 = 0LL;\n do\n {\n v8 = v7 + 1;\n v9 = v4;\n v10 = -1;\n while ( v9 > v8 )\n {\n v11 = v8 + ((v9 - v8) >> 1);\n if ( a3 >= *((_DWORD *)a1 + v11) - *((_DWORD *)a1 + v7) )\n {\n v8 = v11 + 1;\n v10 = v11;\n }\n else\n {\n v9 = v8 + ((v9 - v8) >> 1);\n }\n }\n if ( v10 != -1 && v6 > (int)v3 - (v10 - (int)v7 + 1) )\n v6 = v3 - (v10 - v7 + 1);\n ++v7;\n }\n while ( v3 != v7 );\n return (unsigned int)v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1310(void *a1, int a2, int a3) {\n long long v3;\n unsigned int v4;\n int v6;\n long long v7;\n int v8;\n signed int v9;\n int v10;\n int v11;\n v3 = a2;\n v4 = a2 - 1;\n qsort(a1, a2, 4uLL, (int (*)(const void *, const void *)) & strcmp);\n if (a2 <= 0) return v4;\n v6 = a2 - 1;\n v7 = 0LL;\n do {\n v8 = v7 + 1;\n v9 = v4;\n v10 = -1;\n while (v9 > v8) {\n v11 = v8 + ((v9 - v8) >> 1);\n if (a3 >= *((uint32_t *)a1 + v11) - *((uint32_t *)a1 + v7)) {\n v8 = v11 + 1;\n v10 = v11;\n } else {\n v9 = v8 + ((v9 - v8) >> 1);\n }\n }\n if (v10 != -1 && v6 > (int)v3 - (v10 - (int)v7 + 1))\n v6 = v3 - (v10 - v7 + 1);\n ++v7;\n } while (v3 != v7);\n return (unsigned int)v6;\n}", + "ida_pseudo_norm": "long long func0(void *a1, int a2, int a3) {\n long long v3;\n unsigned int v4;\n int v6;\n long long v7;\n int v8;\n signed int v9;\n int v10;\n int v11;\n v3 = a2;\n v4 = a2 - 1;\n qsort(a1, a2, 4uLL, (int (*)(const void *, const void *)) & strcmp);\n if (a2 <= 0) return v4;\n v6 = a2 - 1;\n v7 = 0LL;\n do {\n v8 = v7 + 1;\n v9 = v4;\n v10 = -1;\n while (v9 > v8) {\n v11 = v8 + ((v9 - v8) >> 1);\n if (a3 >= *((uint32_t *)a1 + v11) - *((uint32_t *)a1 + v7)) {\n v8 = v11 + 1;\n v10 = v11;\n } else {\n v9 = v8 + ((v9 - v8) >> 1);\n }\n }\n if (v10 != -1 && v6 > (int)v3 - (v10 - (int)v7 + 1))\n v6 = v3 - (v10 - v7 + 1);\n ++v7;\n } while (v3 != v7);\n return (unsigned int)v6;\n}" + }, + { + "index": 703, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int *keys, int *values, int size, int x) {\n for (int i = 0; i < size; i++) {\n if (keys[i] == x) {\n return true;\n }\n }\n return false;\n}", + "test": "int main() {\n\n int keys[] = {1, 2, 3, 4, 5, 6};\n\n int values[] = {10, 20, 30, 40, 50, 60};\n\n int size = 6;\n\n\n\n assert(func0(keys, values, size, 5) == true);\n\n assert(func0(keys, values, size, 6) == true);\n\n assert(func0(keys, values, size, 10) == false);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %edx,-0x24(%rbp)\nmov %ecx,-0x28(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11ae \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x28(%rbp)\njne 11aa \nmov $0x1,%eax\njmp 11bb \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x24(%rbp),%eax\njl 1188 \nmov $0x0,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_28], ecx\nmov [rbp+var_4], 0\njmp short loc_11AE\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_28], eax\njnz short loc_11AA\nmov eax, 1\njmp short loc_11BB\nloc_11AA:\nadd [rbp+var_4], 1\nloc_11AE:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_24]\njl short loc_1188\nmov eax, 0\nloc_11BB:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3, int a4)\n{\n int i; // [rsp+24h] [rbp-4h]\n\n for ( i = 0; i < a3; ++i )\n {\n if ( a4 == *(_DWORD *)(4LL * i + a1) )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_28], ecx\nmov [rbp+var_4], 0\njmp short loc_11AE\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_28], eax\njnz short loc_11AA\nmov eax, 1\njmp short loc_11BB\nloc_11AA:\nadd [rbp+var_4], 1\nloc_11AE:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_24]\njl short loc_1188\nmov eax, 0\nloc_11BB:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, int a3, int a4)\n{\n int i; // [rsp+24h] [rbp-4h]\n\n for ( i = 0; i < a3; ++i )\n {\n if ( a4 == *(_DWORD *)(4LL * i + a1) )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, int a3, int a4) {\n int i;\n for (i = 0; i < a3; ++i) {\n if (a4 == *(uint32_t *)(4LL * i + a1)) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3, int a4) {\n int i;\n for (i = 0; i < a3; ++i) {\n if (a4 == *(uint32_t *)(4LL * i + a1)) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 703, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int *keys, int *values, int size, int x) {\n for (int i = 0; i < size; i++) {\n if (keys[i] == x) {\n return true;\n }\n }\n return false;\n}", + "test": "int main() {\n\n int keys[] = {1, 2, 3, 4, 5, 6};\n\n int values[] = {10, 20, 30, 40, 50, 60};\n\n int size = 6;\n\n\n\n assert(func0(keys, values, size, 5) == true);\n\n assert(func0(keys, values, size, 6) == true);\n\n assert(func0(keys, values, size, 10) == false);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edx,%edx\njle 118f \nmov %rdi,%rax\nlea -0x1(%rdx),%edx\nlea 0x4(%rdi,%rdx,4),%rdx\ncmp %ecx,(%rax)\nje 1195 \nadd $0x4,%rax\ncmp %rdx,%rax\njne 117c \nmov $0x0,%eax\nretq\nmov $0x0,%eax\nretq\nmov $0x1,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest edx, edx\njle short loc_118E\nmov rax, rdi\nmovsxd rdx, edx\nlea rdx, [rdi+rdx*4]\nloc_117B:\ncmp [rax], ecx\njz short loc_1194\nadd rax, 4\ncmp rax, rdx\njnz short loc_117B\nmov eax, 0\nretn\nloc_118E:\nmov eax, 0\nretn\nloc_1194:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, __int64 a2, int a3, int a4)\n{\n _DWORD *v4; // rax\n _DWORD *v5; // rdx\n\n if ( a3 <= 0 )\n return 0LL;\n v4 = a1;\n v5 = &a1[a3];\n while ( *v4 != a4 )\n {\n if ( ++v4 == v5 )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest edx, edx\njle short loc_118E\nmov rax, rdi\nmovsxd rdx, edx\nlea rdx, [rdi+rdx*4]\nloc_117B:\ncmp [rax], ecx\njz short loc_1194\nadd rax, 4\ncmp rax, rdx\njnz short loc_117B\nmov eax, 0\nretn\nloc_118E:\nmov eax, 0\nretn\nloc_1194:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, __int64 a2, int a3, int a4)\n{\n _DWORD *v4; // rax\n _DWORD *v5; // rdx\n\n if ( a3 <= 0 )\n return 0LL;\n v4 = a1;\n v5 = &a1[a3];\n while ( *v4 != a4 )\n {\n if ( ++v4 == v5 )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, long long a2, int a3, int a4) {\n uint32_t *v4;\n uint32_t *v5;\n if (a3 <= 0) return 0LL;\n v4 = a1;\n v5 = &a1[a3];\n while (*v4 != a4) {\n if (++v4 == v5) return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, long long a2, int a3, int a4) {\n uint32_t *v4;\n uint32_t *v5;\n if (a3 <= 0) return 0LL;\n v4 = a1;\n v5 = &a1[a3];\n while (*v4 != a4) {\n if (++v4 == v5) return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": 704, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int n) {\n if (n < 2)\n return 1.0;\n else\n return 1.0 / n + func0(n - 1);\n}", + "test": "int main() {\n\n assert(func0(10) - 2.9289682539682538 < 1e-9);\n\n assert(func0(4) - 2.083333333333333 < 1e-9);\n\n assert(func0(7) - 2.5928571428571425 < 1e-9);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %edi,-0x4(%rbp)\ncmpl $0x1,-0x4(%rbp)\njg 1168 \nmovsd 0xf62(%rip),%xmm0\njmp 1190 \ncvtsi2sdl -0x4(%rbp),%xmm1\nmovsd 0xf53(%rip),%xmm0\ndivsd %xmm1,%xmm0\nmovsd %xmm0,-0x10(%rbp)\nmov -0x4(%rbp),%eax\nsub $0x1,%eax\nmov %eax,%edi\ncallq 1149 \naddsd -0x10(%rbp),%xmm0\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+var_4], edi\ncmp [rbp+var_4], 1\njg short loc_1168\nmovsd xmm0, cs:qword_20A8\njmp short locret_1194\nloc_1168:\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_4]\nmovsd xmm0, cs:qword_20A8\ndivsd xmm0, xmm1\nmovsd [rbp+var_10], xmm0\nmov eax, [rbp+var_4]\nsub eax, 1\nmov edi, eax\ncall func0\naddsd xmm0, [rbp+var_10]\nlocret_1194:\nleave\nretn", + "ida_pseudo": "double __fastcall func0(int a1)\n{\n if ( a1 > 1 )\n return func0((unsigned int)(a1 - 1)) + 1.0 / (double)a1;\n else\n return 1.0;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+var_4], edi\ncmp [rbp+var_4], 1\njg short loc_1168\nmovsd xmm0, cs:qword_20A8\njmp short locret_1194\nloc_1168:\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_4]\nmovsd xmm0, cs:qword_20A8\ndivsd xmm0, xmm1\nmovsd [rbp+var_10], xmm0\nmov eax, [rbp+var_4]\nsub eax, 1\nmov edi, eax\ncall sub_1149\naddsd xmm0, [rbp+var_10]\nlocret_1194:\nleave\nretn", + "ida_strip_pseudo": "double __fastcall sub_1149(int a1)\n{\n if ( a1 > 1 )\n return sub_1149((unsigned int)(a1 - 1)) + 1.0 / (double)a1;\n else\n return 1.0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1149(int a1) {\n if (a1 > 1)\n return sub_1149((unsigned int)(a1 - 1)) + 1.0 / (double)a1;\n else\n return 1.0;\n}", + "ida_pseudo_norm": "double func0(int a1) {\n if (a1 > 1)\n return func0((unsigned int)(a1 - 1)) + 1.0 / (double)a1;\n else\n return 1.0;\n}" + }, + { + "index": 704, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int n) {\n if (n < 2)\n return 1.0;\n else\n return 1.0 / n + func0(n - 1);\n}", + "test": "int main() {\n\n assert(func0(10) - 2.9289682539682538 < 1e-9);\n\n assert(func0(4) - 2.083333333333333 < 1e-9);\n\n assert(func0(7) - 2.5928571428571425 < 1e-9);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmovsd 0xf73(%rip),%xmm0\ncmp $0x1,%edi\njg 115b \nretq\npush %rbx\nmov %edi,%ebx\nlea -0x1(%rdi),%edi\ncallq 1149 \nmovapd %xmm0,%xmm2\npxor %xmm1,%xmm1\ncvtsi2sd %ebx,%xmm1\nmovsd 0xf4e(%rip),%xmm0\ndivsd %xmm1,%xmm0\naddsd %xmm2,%xmm0\npop %rbx\nretq\n", + "ida_asm": "func0:\nendbr64\nmovsd xmm0, cs:qword_20B0\ncmp edi, 1\njg short loc_115B\nretn\nloc_115B:\nsub rsp, 18h\npxor xmm0, xmm0\ncvtsi2sd xmm0, edi\nmovsd xmm1, cs:qword_20B0\ndivsd xmm1, xmm0\nmovsd [rsp+18h+var_10], xmm1\nsub edi, 1\ncall func0\naddsd xmm0, [rsp+18h+var_10]\nadd rsp, 18h\nretn", + "ida_pseudo": "double __fastcall func0(int a1)\n{\n double result; // xmm0_8\n\n result = 1.0;\n if ( a1 > 1 )\n return func0((unsigned int)(a1 - 1)) + 1.0 / (double)a1;\n return result;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmovsd xmm0, cs:qword_20B0\ncmp edi, 1\njg short loc_115B\nretn\nloc_115B:\nsub rsp, 18h\npxor xmm0, xmm0\ncvtsi2sd xmm0, edi\nmovsd xmm1, cs:qword_20B0\ndivsd xmm1, xmm0\nmovsd [rsp+18h+var_10], xmm1\nsub edi, 1\ncall sub_1149\naddsd xmm0, [rsp+18h+var_10]\nadd rsp, 18h\nretn", + "ida_strip_pseudo": "double __fastcall sub_1149(int a1)\n{\n double result; // xmm0_8\n\n result = 1.0;\n if ( a1 > 1 )\n return sub_1149((unsigned int)(a1 - 1)) + 1.0 / (double)a1;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1149(int a1) {\n double result;\n result = 1.0;\n if (a1 > 1) return sub_1149((unsigned int)(a1 - 1)) + 1.0 / (double)a1;\n return result;\n}", + "ida_pseudo_norm": "double func0(int a1) {\n double result;\n result = 1.0;\n if (a1 > 1) return func0((unsigned int)(a1 - 1)) + 1.0 / (double)a1;\n return result;\n}" + }, + { + "index": 704, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int n) {\n if (n < 2)\n return 1.0;\n else\n return 1.0 / n + func0(n - 1);\n}", + "test": "int main() {\n\n assert(func0(10) - 2.9289682539682538 < 1e-9);\n\n assert(func0(4) - 2.083333333333333 < 1e-9);\n\n assert(func0(7) - 2.5928571428571425 < 1e-9);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%edi\njg 1258 \nmovsd 0xe77(%rip),%xmm0\nretq\nnopw 0x0(%rax,%rax,1)\njmp 1260 \nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmovsd xmm0, cs:qword_20B0\ncmp edi, 1\njg short loc_1248\nretn\nloc_1248:\npxor xmm1, xmm1\nmovapd xmm2, xmm0\nlea eax, [rdi-1]\ncvtsi2sd xmm1, edi\ndivsd xmm2, xmm1\nmovapd xmm1, xmm0\ncmp edi, 2\njnz short loc_1270\naddsd xmm2, xmm1\nmovapd xmm0, xmm2\nretn\nloc_1270:\npxor xmm3, xmm3\ncvtsi2sd xmm3, eax\nlea eax, [rdi-2]\ndivsd xmm1, xmm3\ncmp edi, 3\njnz short loc_1298\naddsd xmm1, xmm0\naddsd xmm2, xmm1\nmovapd xmm0, xmm2\nretn\nloc_1298:\npxor xmm3, xmm3\nsub rsp, 28h\nsub edi, 3\ncvtsi2sd xmm3, eax\nmovsd [rsp+28h+var_10], xmm1\nmovsd [rsp+28h+var_18], xmm2\ndivsd xmm0, xmm3\nmovsd [rsp+28h+var_20], xmm0\ncall func0\naddsd xmm0, [rsp+28h+var_20]\nmovsd xmm1, [rsp+28h+var_10]\nmovsd xmm2, [rsp+28h+var_18]\nadd rsp, 28h\naddsd xmm1, xmm0\naddsd xmm2, xmm1\nmovapd xmm0, xmm2\nretn", + "ida_pseudo": "__int128 __usercall func0@(int a1@)\n{\n __int128 result; // xmm0\n __int128 v2; // xmm2\n int v3; // eax\n double v4; // xmm1_8\n\n result = 0x3FF0000000000000uLL;\n if ( a1 > 1 )\n {\n *((_QWORD *)&v2 + 1) = 0LL;\n *(double *)&v2 = 1.0 / (double)a1;\n if ( a1 == 2 )\n {\n *(double *)&v2 = *(double *)&v2 + 1.0;\n return v2;\n }\n else\n {\n v4 = 1.0 / (double)(a1 - 1);\n if ( a1 == 3 )\n {\n *(double *)&v2 = *(double *)&v2 + v4 + 1.0;\n }\n else\n {\n v2 = (unsigned __int64)v2;\n v3 = a1 - 2;\n *(double *)&v2 = *(double *)&v2 + v4 + func0((unsigned int)(a1 - 3)) + 1.0 / (double)v3;\n }\n return v2;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1230:\nendbr64\nmovsd xmm0, cs:qword_20B0\ncmp edi, 1\njg short loc_1248\nretn\nloc_1248:\npxor xmm1, xmm1\nmovapd xmm2, xmm0\nlea eax, [rdi-1]\ncvtsi2sd xmm1, edi\ndivsd xmm2, xmm1\nmovapd xmm1, xmm0\ncmp edi, 2\njnz short loc_1270\naddsd xmm2, xmm1\nmovapd xmm0, xmm2\nretn\nloc_1270:\npxor xmm3, xmm3\ncvtsi2sd xmm3, eax\nlea eax, [rdi-2]\ndivsd xmm1, xmm3\ncmp edi, 3\njnz short loc_1298\naddsd xmm1, xmm0\naddsd xmm2, xmm1\nmovapd xmm0, xmm2\nretn\nloc_1298:\npxor xmm3, xmm3\nsub rsp, 28h\nsub edi, 3\ncvtsi2sd xmm3, eax\nmovsd [rsp+28h+var_10], xmm1\nmovsd [rsp+28h+var_18], xmm2\ndivsd xmm0, xmm3\nmovsd [rsp+28h+var_20], xmm0\ncall sub_1230\naddsd xmm0, [rsp+28h+var_20]\nmovsd xmm1, [rsp+28h+var_10]\nmovsd xmm2, [rsp+28h+var_18]\nadd rsp, 28h\naddsd xmm1, xmm0\naddsd xmm2, xmm1\nmovapd xmm0, xmm2\nretn", + "ida_strip_pseudo": "__int128 __usercall sub_1230@(int a1@)\n{\n __int128 result; // xmm0\n __int128 v2; // xmm2\n int v3; // eax\n double v4; // xmm1_8\n\n result = 0x3FF0000000000000uLL;\n if ( a1 > 1 )\n {\n *((_QWORD *)&v2 + 1) = 0LL;\n *(double *)&v2 = 1.0 / (double)a1;\n if ( a1 == 2 )\n {\n *(double *)&v2 = *(double *)&v2 + 1.0;\n return v2;\n }\n else\n {\n v4 = 1.0 / (double)(a1 - 1);\n if ( a1 == 3 )\n {\n *(double *)&v2 = *(double *)&v2 + v4 + 1.0;\n }\n else\n {\n v2 = (unsigned __int64)v2;\n v3 = a1 - 2;\n *(double *)&v2 = *(double *)&v2 + v4 + sub_1230((unsigned int)(a1 - 3)) + 1.0 / (double)v3;\n }\n return v2;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__int128 __usercall sub_1230 @(int a1 @) {\n __int128 result;\n __int128 v2;\n int v3;\n double v4;\n result = 4607182418800017408uLL;\n if (a1 > 1) {\n *((uint64_t *)&v2 + 1) = 0LL;\n *(double *)&v2 = 1.0 / (double)a1;\n if (a1 == 2) {\n *(double *)&v2 = *(double *)&v2 + 1.0;\n return v2;\n } else {\n v4 = 1.0 / (double)(a1 - 1);\n if (a1 == 3) {\n *(double *)&v2 = *(double *)&v2 + v4 + 1.0;\n } else {\n v2 = (unsigned long long)v2;\n v3 = a1 - 2;\n *(double *)&v2 = *(double *)&v2 + v4 +\n sub_1230((unsigned int)(a1 - 3)) + 1.0 / (double)v3;\n }\n return v2;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "__int128 __usercall func0 @(int a1 @) {\n __int128 result;\n __int128 v2;\n int v3;\n double v4;\n result = 4607182418800017408uLL;\n if (a1 > 1) {\n *((uint64_t *)&v2 + 1) = 0LL;\n *(double *)&v2 = 1.0 / (double)a1;\n if (a1 == 2) {\n *(double *)&v2 = *(double *)&v2 + 1.0;\n return v2;\n } else {\n v4 = 1.0 / (double)(a1 - 1);\n if (a1 == 3) {\n *(double *)&v2 = *(double *)&v2 + v4 + 1.0;\n } else {\n v2 = (unsigned long long)v2;\n v3 = a1 - 2;\n *(double *)&v2 = *(double *)&v2 + v4 + func0((unsigned int)(a1 - 3)) +\n 1.0 / (double)v3;\n }\n return v2;\n }\n }\n return result;\n}" + }, + { + "index": 704, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int n) {\n if (n < 2)\n return 1.0;\n else\n return 1.0 / n + func0(n - 1);\n}", + "test": "int main() {\n\n assert(func0(10) - 2.9289682539682538 < 1e-9);\n\n assert(func0(4) - 2.083333333333333 < 1e-9);\n\n assert(func0(7) - 2.5928571428571425 < 1e-9);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nmovsd 0xe8c(%rip),%xmm1\ncmp $0x1,%edi\njg 1250 \nmovapd %xmm1,%xmm0\nretq\nnopw %cs:0x0(%rax,%rax,1)\npush %rbx\nmov %edi,%ebx\nlea -0x1(%rdi),%edi\nsub $0x10,%rsp\nmovsd %xmm1,0x8(%rsp)\ncallq 1230 \nmovsd 0x8(%rsp),%xmm1\nadd $0x10,%rsp\nmovapd %xmm0,%xmm2\npxor %xmm0,%xmm0\ncvtsi2sd %ebx,%xmm0\npop %rbx\ndivsd %xmm0,%xmm1\naddsd %xmm2,%xmm1\nmovapd %xmm1,%xmm0\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\nmovsd xmm0, cs:qword_20B0\ncmp edi, 1\njg short loc_1248\nretn\nloc_1248:\npxor xmm1, xmm1\nmovapd xmm2, xmm0\nlea eax, [rdi-1]\ncvtsi2sd xmm1, edi\ndivsd xmm2, xmm1\nmovapd xmm1, xmm0\ncmp edi, 2\njnz short loc_1270\naddsd xmm2, xmm1\nmovapd xmm0, xmm2\nretn\nloc_1270:\npxor xmm3, xmm3\ncvtsi2sd xmm3, eax\nlea eax, [rdi-2]\ndivsd xmm1, xmm3\ncmp edi, 3\njnz short loc_1298\naddsd xmm1, xmm0\naddsd xmm2, xmm1\nmovapd xmm0, xmm2\nretn\nloc_1298:\npxor xmm3, xmm3\nsub rsp, 28h\nsub edi, 3\ncvtsi2sd xmm3, eax\nmovsd [rsp+28h+var_10], xmm1\nmovsd [rsp+28h+var_18], xmm2\ndivsd xmm0, xmm3\nmovsd [rsp+28h+var_20], xmm0\ncall func0\naddsd xmm0, [rsp+28h+var_20]\nmovsd xmm1, [rsp+28h+var_10]\nmovsd xmm2, [rsp+28h+var_18]\nadd rsp, 28h\naddsd xmm1, xmm0\naddsd xmm2, xmm1\nmovapd xmm0, xmm2\nretn", + "ida_pseudo": "__int128 __usercall func0@(int a1@)\n{\n __int128 result; // xmm0\n __int128 v2; // xmm2\n int v3; // eax\n double v4; // xmm1_8\n\n result = 0x3FF0000000000000uLL;\n if ( a1 > 1 )\n {\n *((_QWORD *)&v2 + 1) = 0LL;\n *(double *)&v2 = 1.0 / (double)a1;\n if ( a1 == 2 )\n {\n *(double *)&v2 = *(double *)&v2 + 1.0;\n return v2;\n }\n else\n {\n v4 = 1.0 / (double)(a1 - 1);\n if ( a1 == 3 )\n {\n *(double *)&v2 = *(double *)&v2 + v4 + 1.0;\n }\n else\n {\n v2 = (unsigned __int64)v2;\n v3 = a1 - 2;\n *(double *)&v2 = *(double *)&v2 + v4 + func0((unsigned int)(a1 - 3)) + 1.0 / (double)v3;\n }\n return v2;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1230:\nendbr64\nmovsd xmm0, cs:qword_20B0\ncmp edi, 1\njg short loc_1248\nretn\nloc_1248:\npxor xmm1, xmm1\nmovapd xmm2, xmm0\nlea eax, [rdi-1]\ncvtsi2sd xmm1, edi\ndivsd xmm2, xmm1\nmovapd xmm1, xmm0\ncmp edi, 2\njnz short loc_1270\naddsd xmm2, xmm1\nmovapd xmm0, xmm2\nretn\nloc_1270:\npxor xmm3, xmm3\ncvtsi2sd xmm3, eax\nlea eax, [rdi-2]\ndivsd xmm1, xmm3\ncmp edi, 3\njnz short loc_1298\naddsd xmm1, xmm0\naddsd xmm2, xmm1\nmovapd xmm0, xmm2\nretn\nloc_1298:\npxor xmm3, xmm3\nsub rsp, 28h\nsub edi, 3\ncvtsi2sd xmm3, eax\nmovsd [rsp+28h+var_10], xmm1\nmovsd [rsp+28h+var_18], xmm2\ndivsd xmm0, xmm3\nmovsd [rsp+28h+var_20], xmm0\ncall sub_1230\naddsd xmm0, [rsp+28h+var_20]\nmovsd xmm1, [rsp+28h+var_10]\nmovsd xmm2, [rsp+28h+var_18]\nadd rsp, 28h\naddsd xmm1, xmm0\naddsd xmm2, xmm1\nmovapd xmm0, xmm2\nretn", + "ida_strip_pseudo": "__int128 __usercall sub_1230@(int a1@)\n{\n __int128 result; // xmm0\n __int128 v2; // xmm2\n int v3; // eax\n double v4; // xmm1_8\n\n result = 0x3FF0000000000000uLL;\n if ( a1 > 1 )\n {\n *((_QWORD *)&v2 + 1) = 0LL;\n *(double *)&v2 = 1.0 / (double)a1;\n if ( a1 == 2 )\n {\n *(double *)&v2 = *(double *)&v2 + 1.0;\n return v2;\n }\n else\n {\n v4 = 1.0 / (double)(a1 - 1);\n if ( a1 == 3 )\n {\n *(double *)&v2 = *(double *)&v2 + v4 + 1.0;\n }\n else\n {\n v2 = (unsigned __int64)v2;\n v3 = a1 - 2;\n *(double *)&v2 = *(double *)&v2 + v4 + sub_1230((unsigned int)(a1 - 3)) + 1.0 / (double)v3;\n }\n return v2;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__int128 __usercall sub_1230 @(int a1 @) {\n __int128 result;\n __int128 v2;\n int v3;\n double v4;\n result = 4607182418800017408uLL;\n if (a1 > 1) {\n *((uint64_t *)&v2 + 1) = 0LL;\n *(double *)&v2 = 1.0 / (double)a1;\n if (a1 == 2) {\n *(double *)&v2 = *(double *)&v2 + 1.0;\n return v2;\n } else {\n v4 = 1.0 / (double)(a1 - 1);\n if (a1 == 3) {\n *(double *)&v2 = *(double *)&v2 + v4 + 1.0;\n } else {\n v2 = (unsigned long long)v2;\n v3 = a1 - 2;\n *(double *)&v2 = *(double *)&v2 + v4 +\n sub_1230((unsigned int)(a1 - 3)) + 1.0 / (double)v3;\n }\n return v2;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "__int128 __usercall func0 @(int a1 @) {\n __int128 result;\n __int128 v2;\n int v3;\n double v4;\n result = 4607182418800017408uLL;\n if (a1 > 1) {\n *((uint64_t *)&v2 + 1) = 0LL;\n *(double *)&v2 = 1.0 / (double)a1;\n if (a1 == 2) {\n *(double *)&v2 = *(double *)&v2 + 1.0;\n return v2;\n } else {\n v4 = 1.0 / (double)(a1 - 1);\n if (a1 == 3) {\n *(double *)&v2 = *(double *)&v2 + v4 + 1.0;\n } else {\n v2 = (unsigned long long)v2;\n v3 = a1 - 2;\n *(double *)&v2 = *(double *)&v2 + v4 + func0((unsigned int)(a1 - 3)) +\n 1.0 / (double)v3;\n }\n return v2;\n }\n }\n return result;\n}" + }, + { + "index": 705, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int *array;\n\n size_t length;\n\n} IntList;\n\n\n\ntypedef struct {\n\n char **array;\n\n size_t length;\n\n} StrList;\n\n\n\n// Comparison function for integers\n\nint compare_ints(const void *a, const void *b) {\n\n IntList *listA = (IntList *)a;\n\n IntList *listB = (IntList *)b;\n\n if (listA->length != listB->length)\n\n return (listA->length > listB->length) - (listA->length < listB->length);\n\n for (size_t i = 0; i < listA->length; i++) {\n\n if (listA->array[i] != listB->array[i])\n\n return (listA->array[i] > listB->array[i]) - (listA->array[i] < listB->array[i]);\n\n }\n\n return 0;\n\n}\n\n\n\n// Comparison function for strings\n\nint compare_strings(const void *a, const void *b) {\n\n StrList *listA = (StrList *)a;\n\n StrList *listB = (StrList *)b;\n\n if (listA->length != listB->length)\n\n return (listA->length > listB->length) - (listA->length < listB->length);\n\n for (size_t i = 0; i < listA->length; i++) {\n\n int cmp = strcmp(listA->array[i], listB->array[i]);\n\n if (cmp != 0)\n\n return cmp;\n\n }\n\n return 0;\n\n}\n\n\n\nint compare_ints_only(const void *a, const void *b) {\n\n IntList *listA = (IntList *)a;\n\n IntList *listB = (IntList *)b;\n\n for (size_t i = 0; i < (listA->length < listB->length ? listA->length : listB->length); i++) {\n\n if (listA->array[i] != listB->array[i])\n\n return (listA->array[i] > listB->array[i]) - (listA->array[i] < listB->array[i]);\n\n }\n\n return 0;\n\n}\n\n\n\nvoid sort_sublists_str(StrList list[], size_t n) {\n\n qsort(list, n, sizeof(StrList), compare_strings);\n\n qsort(list, n, sizeof(StrList), compare_strings);\n\n}\n\n\n\n", + "func": "void func0(IntList list[], size_t n) {\n qsort(list, n, sizeof(IntList), compare_ints_only);\n qsort(list, n, sizeof(IntList), compare_ints);\n}", + "test": "int main() {\n\n // First assert\n\n IntList list1[] = {\n\n { (int[]){2}, 1 },\n\n { (int[]){0}, 1 },\n\n { (int[]){1, 3}, 2 },\n\n { (int[]){0, 7}, 2 },\n\n { (int[]){9, 11}, 2 },\n\n { (int[]){13, 15, 17}, 3 }\n\n };\n\n size_t n1 = sizeof(list1) / sizeof(list1[0]);\n\n func0(list1, n1);\n\n IntList expected1[] = {\n\n { (int[]){0}, 1 },\n\n { (int[]){2}, 1 },\n\n { (int[]){0, 7}, 2 },\n\n { (int[]){1, 3}, 2 },\n\n { (int[]){9, 11}, 2 },\n\n { (int[]){13, 15, 17}, 3 }\n\n };\n\n for (size_t i = 0; i < n1; i++) {\n\n assert(list1[i].length == expected1[i].length);\n\n for (size_t j = 0; j < list1[i].length; j++) {\n\n assert(list1[i].array[j] == expected1[i].array[j]);\n\n }\n\n }\n\n\n\n // Second assert\n\n IntList list2[] = {\n\n { (int[]){1}, 1 },\n\n { (int[]){2, 3}, 2 },\n\n { (int[]){4, 5, 6}, 3 },\n\n { (int[]){7}, 1 },\n\n { (int[]){10, 11}, 2 }\n\n };\n\n size_t n2 = sizeof(list2) / sizeof(list2[0]);\n\n func0(list2, n2);\n\n IntList expected2[] = {\n\n { (int[]){1}, 1 },\n\n { (int[]){7}, 1 },\n\n { (int[]){2, 3}, 2 },\n\n { (int[]){10, 11}, 2 },\n\n { (int[]){4, 5, 6}, 3 }\n\n };\n\n for (size_t i = 0; i < n2; i++) {\n\n assert(list2[i].length == expected2[i].length);\n\n for (size_t j = 0; j < list2[i].length; j++) {\n\n assert(list2[i].array[j] == expected2[i].array[j]);\n\n }\n\n }\n\n\n\n // Third assert\n\n StrList list3[] = {\n\n { (char*[]){\"python\"}, 1 },\n\n { (char*[]){\"java\", \"C\", \"C++\"}, 3 },\n\n { (char*[]){\"DBMS\"}, 1 },\n\n { (char*[]){\"SQL\", \"HTML\"}, 2 }\n\n };\n\n size_t n3 = sizeof(list3) / sizeof(list3[0]);\n\n sort_sublists_str(list3, n3);\n\n StrList expected3[] = {\n\n { (char*[]){\"DBMS\"}, 1 },\n\n { (char*[]){\"python\"}, 1 },\n\n { (char*[]){\"SQL\", \"HTML\"}, 2 },\n\n { (char*[]){\"java\", \"C\", \"C++\"}, 3 }\n\n };\n\n for (size_t i = 0; i < n3; i++) {\n\n assert(list3[i].length == expected3[i].length);\n\n for (size_t j = 0; j < list3[i].length; j++) {\n\n assert(strcmp(list3[i].array[j], expected3[i].array[j]) == 0);\n\n }\n\n }\n\n\n\n printf(\"All assertions passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %rdi,-0x8(%rbp)\nmov %rsi,-0x10(%rbp)\nmov -0x10(%rbp),%rsi\nmov -0x8(%rbp),%rax\nlea -0x15e(%rip),%rcx\nmov $0x10,%edx\nmov %rax,%rdi\ncallq 10a0 \nmov -0x10(%rbp),%rsi\nmov -0x8(%rbp),%rax\nlea -0x37f(%rip),%rcx\nmov $0x10,%edx\nmov %rax,%rdi\ncallq 10a0 \nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+base], rdi\nmov [rbp+nmemb], rsi\nmov rsi, [rbp+nmemb]; nmemb\nmov rax, [rbp+base]\nlea rdx, compare_ints_only\nmov rcx, rdx; compar\nmov edx, 10h; size\nmov rdi, rax; base\ncall _qsort\nmov rsi, [rbp+nmemb]; nmemb\nmov rax, [rbp+base]\nlea rdx, compare_ints\nmov rcx, rdx; compar\nmov edx, 10h; size\nmov rdi, rax; base\ncall _qsort\nnop\nleave\nretn", + "ida_pseudo": "void __fastcall func0(void *a1, size_t a2)\n{\n qsort(a1, a2, 0x10uLL, compare_ints_only);\n qsort(a1, a2, 0x10uLL, compare_ints);\n}", + "ida_strip_asm": "sub_150F:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+base], rdi\nmov [rbp+nmemb], rsi\nmov rsi, [rbp+nmemb]; nmemb\nmov rax, [rbp+base]\nlea rdx, sub_13CE\nmov rcx, rdx; compar\nmov edx, 10h; size\nmov rdi, rax; base\ncall _qsort\nmov rsi, [rbp+nmemb]; nmemb\nmov rax, [rbp+base]\nlea rdx, sub_11C9\nmov rcx, rdx; compar\nmov edx, 10h; size\nmov rdi, rax; base\ncall _qsort\nnop\nleave\nretn", + "ida_strip_pseudo": "void __fastcall sub_150F(void *a1, size_t a2)\n{\n qsort(a1, a2, 0x10uLL, sub_13CE);\n qsort(a1, a2, 0x10uLL, sub_11C9);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_150F(void *a1, unsigned int a2) {\n qsort(a1, a2, 16uLL, sub_13CE);\n qsort(a1, a2, 16uLL, sub_11C9);\n}", + "ida_pseudo_norm": "void func0(void *a1, unsigned int a2) {\n qsort(a1, a2, 16uLL, compare_ints_only);\n qsort(a1, a2, 16uLL, compare_ints);\n}" + }, + { + "index": 705, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int *array;\n\n size_t length;\n\n} IntList;\n\n\n\ntypedef struct {\n\n char **array;\n\n size_t length;\n\n} StrList;\n\n\n\n// Comparison function for integers\n\nint compare_ints(const void *a, const void *b) {\n\n IntList *listA = (IntList *)a;\n\n IntList *listB = (IntList *)b;\n\n if (listA->length != listB->length)\n\n return (listA->length > listB->length) - (listA->length < listB->length);\n\n for (size_t i = 0; i < listA->length; i++) {\n\n if (listA->array[i] != listB->array[i])\n\n return (listA->array[i] > listB->array[i]) - (listA->array[i] < listB->array[i]);\n\n }\n\n return 0;\n\n}\n\n\n\n// Comparison function for strings\n\nint compare_strings(const void *a, const void *b) {\n\n StrList *listA = (StrList *)a;\n\n StrList *listB = (StrList *)b;\n\n if (listA->length != listB->length)\n\n return (listA->length > listB->length) - (listA->length < listB->length);\n\n for (size_t i = 0; i < listA->length; i++) {\n\n int cmp = strcmp(listA->array[i], listB->array[i]);\n\n if (cmp != 0)\n\n return cmp;\n\n }\n\n return 0;\n\n}\n\n\n\nint compare_ints_only(const void *a, const void *b) {\n\n IntList *listA = (IntList *)a;\n\n IntList *listB = (IntList *)b;\n\n for (size_t i = 0; i < (listA->length < listB->length ? listA->length : listB->length); i++) {\n\n if (listA->array[i] != listB->array[i])\n\n return (listA->array[i] > listB->array[i]) - (listA->array[i] < listB->array[i]);\n\n }\n\n return 0;\n\n}\n\n\n\nvoid sort_sublists_str(StrList list[], size_t n) {\n\n qsort(list, n, sizeof(StrList), compare_strings);\n\n qsort(list, n, sizeof(StrList), compare_strings);\n\n}\n\n\n\n", + "func": "void func0(IntList list[], size_t n) {\n qsort(list, n, sizeof(IntList), compare_ints_only);\n qsort(list, n, sizeof(IntList), compare_ints);\n}", + "test": "int main() {\n\n // First assert\n\n IntList list1[] = {\n\n { (int[]){2}, 1 },\n\n { (int[]){0}, 1 },\n\n { (int[]){1, 3}, 2 },\n\n { (int[]){0, 7}, 2 },\n\n { (int[]){9, 11}, 2 },\n\n { (int[]){13, 15, 17}, 3 }\n\n };\n\n size_t n1 = sizeof(list1) / sizeof(list1[0]);\n\n func0(list1, n1);\n\n IntList expected1[] = {\n\n { (int[]){0}, 1 },\n\n { (int[]){2}, 1 },\n\n { (int[]){0, 7}, 2 },\n\n { (int[]){1, 3}, 2 },\n\n { (int[]){9, 11}, 2 },\n\n { (int[]){13, 15, 17}, 3 }\n\n };\n\n for (size_t i = 0; i < n1; i++) {\n\n assert(list1[i].length == expected1[i].length);\n\n for (size_t j = 0; j < list1[i].length; j++) {\n\n assert(list1[i].array[j] == expected1[i].array[j]);\n\n }\n\n }\n\n\n\n // Second assert\n\n IntList list2[] = {\n\n { (int[]){1}, 1 },\n\n { (int[]){2, 3}, 2 },\n\n { (int[]){4, 5, 6}, 3 },\n\n { (int[]){7}, 1 },\n\n { (int[]){10, 11}, 2 }\n\n };\n\n size_t n2 = sizeof(list2) / sizeof(list2[0]);\n\n func0(list2, n2);\n\n IntList expected2[] = {\n\n { (int[]){1}, 1 },\n\n { (int[]){7}, 1 },\n\n { (int[]){2, 3}, 2 },\n\n { (int[]){10, 11}, 2 },\n\n { (int[]){4, 5, 6}, 3 }\n\n };\n\n for (size_t i = 0; i < n2; i++) {\n\n assert(list2[i].length == expected2[i].length);\n\n for (size_t j = 0; j < list2[i].length; j++) {\n\n assert(list2[i].array[j] == expected2[i].array[j]);\n\n }\n\n }\n\n\n\n // Third assert\n\n StrList list3[] = {\n\n { (char*[]){\"python\"}, 1 },\n\n { (char*[]){\"java\", \"C\", \"C++\"}, 3 },\n\n { (char*[]){\"DBMS\"}, 1 },\n\n { (char*[]){\"SQL\", \"HTML\"}, 2 }\n\n };\n\n size_t n3 = sizeof(list3) / sizeof(list3[0]);\n\n sort_sublists_str(list3, n3);\n\n StrList expected3[] = {\n\n { (char*[]){\"DBMS\"}, 1 },\n\n { (char*[]){\"python\"}, 1 },\n\n { (char*[]){\"SQL\", \"HTML\"}, 2 },\n\n { (char*[]){\"java\", \"C\", \"C++\"}, 3 }\n\n };\n\n for (size_t i = 0; i < n3; i++) {\n\n assert(list3[i].length == expected3[i].length);\n\n for (size_t j = 0; j < list3[i].length; j++) {\n\n assert(strcmp(list3[i].array[j], expected3[i].array[j]) == 0);\n\n }\n\n }\n\n\n\n printf(\"All assertions passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbx\nmov %rsi,%rbp\nlea -0x106(%rip),%rcx\nmov $0x10,%edx\ncallq 10a0 \nlea -0x170(%rip),%rcx\nmov $0x10,%edx\nmov %rbp,%rsi\nmov %rbx,%rdi\ncallq 10a0 \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov rbp, rsi\nlea rcx, compare_ints_only; compar\nmov edx, 10h; size\ncall _qsort\nlea rcx, compare_ints; compar\nmov edx, 10h; size\nmov rsi, rbp; nmemb\nmov rdi, rbx; base\ncall _qsort\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_pseudo": "void __fastcall func0(void *base, size_t nmemb)\n{\n qsort(base, nmemb, 0x10uLL, compare_ints_only);\n qsort(base, nmemb, 0x10uLL, compare_ints);\n}", + "ida_strip_asm": "sub_131A:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov rbp, rsi\nlea rcx, sub_1228; compar\nmov edx, 10h; size\ncall _qsort\nlea rcx, sub_11C9; compar\nmov edx, 10h; size\nmov rsi, rbp; nmemb\nmov rdi, rbx; base\ncall _qsort\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "void __fastcall sub_131A(void *base, size_t nmemb)\n{\n qsort(base, nmemb, 0x10uLL, sub_1228);\n qsort(base, nmemb, 0x10uLL, sub_11C9);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_131A(void *base, unsigned int nmemb) {\n qsort(base, nmemb, 16uLL, sub_1228);\n qsort(base, nmemb, 16uLL, sub_11C9);\n}", + "ida_pseudo_norm": "void func0(void *base, unsigned int nmemb) {\n qsort(base, nmemb, 16uLL, compare_ints_only);\n qsort(base, nmemb, 16uLL, compare_ints);\n}" + }, + { + "index": 705, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int *array;\n\n size_t length;\n\n} IntList;\n\n\n\ntypedef struct {\n\n char **array;\n\n size_t length;\n\n} StrList;\n\n\n\n// Comparison function for integers\n\nint compare_ints(const void *a, const void *b) {\n\n IntList *listA = (IntList *)a;\n\n IntList *listB = (IntList *)b;\n\n if (listA->length != listB->length)\n\n return (listA->length > listB->length) - (listA->length < listB->length);\n\n for (size_t i = 0; i < listA->length; i++) {\n\n if (listA->array[i] != listB->array[i])\n\n return (listA->array[i] > listB->array[i]) - (listA->array[i] < listB->array[i]);\n\n }\n\n return 0;\n\n}\n\n\n\n// Comparison function for strings\n\nint compare_strings(const void *a, const void *b) {\n\n StrList *listA = (StrList *)a;\n\n StrList *listB = (StrList *)b;\n\n if (listA->length != listB->length)\n\n return (listA->length > listB->length) - (listA->length < listB->length);\n\n for (size_t i = 0; i < listA->length; i++) {\n\n int cmp = strcmp(listA->array[i], listB->array[i]);\n\n if (cmp != 0)\n\n return cmp;\n\n }\n\n return 0;\n\n}\n\n\n\nint compare_ints_only(const void *a, const void *b) {\n\n IntList *listA = (IntList *)a;\n\n IntList *listB = (IntList *)b;\n\n for (size_t i = 0; i < (listA->length < listB->length ? listA->length : listB->length); i++) {\n\n if (listA->array[i] != listB->array[i])\n\n return (listA->array[i] > listB->array[i]) - (listA->array[i] < listB->array[i]);\n\n }\n\n return 0;\n\n}\n\n\n\nvoid sort_sublists_str(StrList list[], size_t n) {\n\n qsort(list, n, sizeof(StrList), compare_strings);\n\n qsort(list, n, sizeof(StrList), compare_strings);\n\n}\n\n\n\n", + "func": "void func0(IntList list[], size_t n) {\n qsort(list, n, sizeof(IntList), compare_ints_only);\n qsort(list, n, sizeof(IntList), compare_ints);\n}", + "test": "int main() {\n\n // First assert\n\n IntList list1[] = {\n\n { (int[]){2}, 1 },\n\n { (int[]){0}, 1 },\n\n { (int[]){1, 3}, 2 },\n\n { (int[]){0, 7}, 2 },\n\n { (int[]){9, 11}, 2 },\n\n { (int[]){13, 15, 17}, 3 }\n\n };\n\n size_t n1 = sizeof(list1) / sizeof(list1[0]);\n\n func0(list1, n1);\n\n IntList expected1[] = {\n\n { (int[]){0}, 1 },\n\n { (int[]){2}, 1 },\n\n { (int[]){0, 7}, 2 },\n\n { (int[]){1, 3}, 2 },\n\n { (int[]){9, 11}, 2 },\n\n { (int[]){13, 15, 17}, 3 }\n\n };\n\n for (size_t i = 0; i < n1; i++) {\n\n assert(list1[i].length == expected1[i].length);\n\n for (size_t j = 0; j < list1[i].length; j++) {\n\n assert(list1[i].array[j] == expected1[i].array[j]);\n\n }\n\n }\n\n\n\n // Second assert\n\n IntList list2[] = {\n\n { (int[]){1}, 1 },\n\n { (int[]){2, 3}, 2 },\n\n { (int[]){4, 5, 6}, 3 },\n\n { (int[]){7}, 1 },\n\n { (int[]){10, 11}, 2 }\n\n };\n\n size_t n2 = sizeof(list2) / sizeof(list2[0]);\n\n func0(list2, n2);\n\n IntList expected2[] = {\n\n { (int[]){1}, 1 },\n\n { (int[]){7}, 1 },\n\n { (int[]){2, 3}, 2 },\n\n { (int[]){10, 11}, 2 },\n\n { (int[]){4, 5, 6}, 3 }\n\n };\n\n for (size_t i = 0; i < n2; i++) {\n\n assert(list2[i].length == expected2[i].length);\n\n for (size_t j = 0; j < list2[i].length; j++) {\n\n assert(list2[i].array[j] == expected2[i].array[j]);\n\n }\n\n }\n\n\n\n // Third assert\n\n StrList list3[] = {\n\n { (char*[]){\"python\"}, 1 },\n\n { (char*[]){\"java\", \"C\", \"C++\"}, 3 },\n\n { (char*[]){\"DBMS\"}, 1 },\n\n { (char*[]){\"SQL\", \"HTML\"}, 2 }\n\n };\n\n size_t n3 = sizeof(list3) / sizeof(list3[0]);\n\n sort_sublists_str(list3, n3);\n\n StrList expected3[] = {\n\n { (char*[]){\"DBMS\"}, 1 },\n\n { (char*[]){\"python\"}, 1 },\n\n { (char*[]){\"SQL\", \"HTML\"}, 2 },\n\n { (char*[]){\"java\", \"C\", \"C++\"}, 3 }\n\n };\n\n for (size_t i = 0; i < n3; i++) {\n\n assert(list3[i].length == expected3[i].length);\n\n for (size_t j = 0; j < list3[i].length; j++) {\n\n assert(strcmp(list3[i].array[j], expected3[i].array[j]) == 0);\n\n }\n\n }\n\n\n\n printf(\"All assertions passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nlea -0x11d(%rip),%rcx\nmov $0x10,%edx\nmov %rsi,%r12\npush %rbp\nmov %rdi,%rbp\nsub $0x8,%rsp\ncallq 10a0 \nadd $0x8,%rsp\nmov %r12,%rsi\nmov %rbp,%rdi\nlea -0x1a3(%rip),%rcx\npop %rbp\nmov $0x10,%edx\npop %r12\njmpq 10a0 \n", + "ida_asm": "func0:\nendbr64\npush rbp\nlea rcx, compare_ints_only; compar\nmov edx, 10h; size\nmov rbp, rsi\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _qsort\nadd rsp, 8\nmov rsi, rbp; nmemb\nmov rdi, rbx; base\nlea rcx, compare_ints; compar\npop rbx\nmov edx, 10h; size\npop rbp\njmp _qsort", + "ida_pseudo": "void __fastcall func0(void *base, size_t nmemb)\n{\n qsort(base, nmemb, 0x10uLL, compare_ints_only);\n qsort(base, nmemb, 0x10uLL, compare_ints);\n}", + "ida_strip_asm": "sub_1A80:\nendbr64\npush rbp\nlea rcx, sub_1960; compar\nmov edx, 10h; size\nmov rbp, rsi\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _qsort\nadd rsp, 8\nmov rsi, rbp; nmemb\nmov rdi, rbx; base\nlea rcx, sub_1900; compar\npop rbx\nmov edx, 10h; size\npop rbp\njmp _qsort", + "ida_strip_pseudo": "void __fastcall sub_1A80(void *base, size_t nmemb)\n{\n qsort(base, nmemb, 0x10uLL, sub_1960);\n qsort(base, nmemb, 0x10uLL, sub_1900);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1A80(void *base, unsigned int nmemb) {\n qsort(base, nmemb, 16uLL, sub_1960);\n qsort(base, nmemb, 16uLL, sub_1900);\n}", + "ida_pseudo_norm": "void func0(void *base, unsigned int nmemb) {\n qsort(base, nmemb, 16uLL, compare_ints_only);\n qsort(base, nmemb, 16uLL, compare_ints);\n}" + }, + { + "index": 705, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int *array;\n\n size_t length;\n\n} IntList;\n\n\n\ntypedef struct {\n\n char **array;\n\n size_t length;\n\n} StrList;\n\n\n\n// Comparison function for integers\n\nint compare_ints(const void *a, const void *b) {\n\n IntList *listA = (IntList *)a;\n\n IntList *listB = (IntList *)b;\n\n if (listA->length != listB->length)\n\n return (listA->length > listB->length) - (listA->length < listB->length);\n\n for (size_t i = 0; i < listA->length; i++) {\n\n if (listA->array[i] != listB->array[i])\n\n return (listA->array[i] > listB->array[i]) - (listA->array[i] < listB->array[i]);\n\n }\n\n return 0;\n\n}\n\n\n\n// Comparison function for strings\n\nint compare_strings(const void *a, const void *b) {\n\n StrList *listA = (StrList *)a;\n\n StrList *listB = (StrList *)b;\n\n if (listA->length != listB->length)\n\n return (listA->length > listB->length) - (listA->length < listB->length);\n\n for (size_t i = 0; i < listA->length; i++) {\n\n int cmp = strcmp(listA->array[i], listB->array[i]);\n\n if (cmp != 0)\n\n return cmp;\n\n }\n\n return 0;\n\n}\n\n\n\nint compare_ints_only(const void *a, const void *b) {\n\n IntList *listA = (IntList *)a;\n\n IntList *listB = (IntList *)b;\n\n for (size_t i = 0; i < (listA->length < listB->length ? listA->length : listB->length); i++) {\n\n if (listA->array[i] != listB->array[i])\n\n return (listA->array[i] > listB->array[i]) - (listA->array[i] < listB->array[i]);\n\n }\n\n return 0;\n\n}\n\n\n\nvoid sort_sublists_str(StrList list[], size_t n) {\n\n qsort(list, n, sizeof(StrList), compare_strings);\n\n qsort(list, n, sizeof(StrList), compare_strings);\n\n}\n\n\n\n", + "func": "void func0(IntList list[], size_t n) {\n qsort(list, n, sizeof(IntList), compare_ints_only);\n qsort(list, n, sizeof(IntList), compare_ints);\n}", + "test": "int main() {\n\n // First assert\n\n IntList list1[] = {\n\n { (int[]){2}, 1 },\n\n { (int[]){0}, 1 },\n\n { (int[]){1, 3}, 2 },\n\n { (int[]){0, 7}, 2 },\n\n { (int[]){9, 11}, 2 },\n\n { (int[]){13, 15, 17}, 3 }\n\n };\n\n size_t n1 = sizeof(list1) / sizeof(list1[0]);\n\n func0(list1, n1);\n\n IntList expected1[] = {\n\n { (int[]){0}, 1 },\n\n { (int[]){2}, 1 },\n\n { (int[]){0, 7}, 2 },\n\n { (int[]){1, 3}, 2 },\n\n { (int[]){9, 11}, 2 },\n\n { (int[]){13, 15, 17}, 3 }\n\n };\n\n for (size_t i = 0; i < n1; i++) {\n\n assert(list1[i].length == expected1[i].length);\n\n for (size_t j = 0; j < list1[i].length; j++) {\n\n assert(list1[i].array[j] == expected1[i].array[j]);\n\n }\n\n }\n\n\n\n // Second assert\n\n IntList list2[] = {\n\n { (int[]){1}, 1 },\n\n { (int[]){2, 3}, 2 },\n\n { (int[]){4, 5, 6}, 3 },\n\n { (int[]){7}, 1 },\n\n { (int[]){10, 11}, 2 }\n\n };\n\n size_t n2 = sizeof(list2) / sizeof(list2[0]);\n\n func0(list2, n2);\n\n IntList expected2[] = {\n\n { (int[]){1}, 1 },\n\n { (int[]){7}, 1 },\n\n { (int[]){2, 3}, 2 },\n\n { (int[]){10, 11}, 2 },\n\n { (int[]){4, 5, 6}, 3 }\n\n };\n\n for (size_t i = 0; i < n2; i++) {\n\n assert(list2[i].length == expected2[i].length);\n\n for (size_t j = 0; j < list2[i].length; j++) {\n\n assert(list2[i].array[j] == expected2[i].array[j]);\n\n }\n\n }\n\n\n\n // Third assert\n\n StrList list3[] = {\n\n { (char*[]){\"python\"}, 1 },\n\n { (char*[]){\"java\", \"C\", \"C++\"}, 3 },\n\n { (char*[]){\"DBMS\"}, 1 },\n\n { (char*[]){\"SQL\", \"HTML\"}, 2 }\n\n };\n\n size_t n3 = sizeof(list3) / sizeof(list3[0]);\n\n sort_sublists_str(list3, n3);\n\n StrList expected3[] = {\n\n { (char*[]){\"DBMS\"}, 1 },\n\n { (char*[]){\"python\"}, 1 },\n\n { (char*[]){\"SQL\", \"HTML\"}, 2 },\n\n { (char*[]){\"java\", \"C\", \"C++\"}, 3 }\n\n };\n\n for (size_t i = 0; i < n3; i++) {\n\n assert(list3[i].length == expected3[i].length);\n\n for (size_t j = 0; j < list3[i].length; j++) {\n\n assert(strcmp(list3[i].array[j], expected3[i].array[j]) == 0);\n\n }\n\n }\n\n\n\n printf(\"All assertions passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nlea -0x11d(%rip),%rcx\nmov $0x10,%edx\nmov %rsi,%r12\npush %rbp\nmov %rdi,%rbp\nsub $0x8,%rsp\ncallq 10a0 \nadd $0x8,%rsp\nmov %r12,%rsi\nmov %rbp,%rdi\nlea -0x1a3(%rip),%rcx\npop %rbp\nmov $0x10,%edx\npop %r12\njmpq 10a0 \n", + "ida_asm": "func0:\nendbr64\npush rbp\nlea rcx, compare_ints_only; compar\nmov edx, 10h; size\nmov rbp, rsi\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _qsort\nadd rsp, 8\nmov rsi, rbp; nmemb\nmov rdi, rbx; base\nlea rcx, compare_ints; compar\npop rbx\nmov edx, 10h; size\npop rbp\njmp _qsort", + "ida_pseudo": "void __fastcall func0(void *base, size_t nmemb)\n{\n qsort(base, nmemb, 0x10uLL, compare_ints_only);\n qsort(base, nmemb, 0x10uLL, compare_ints);\n}", + "ida_strip_asm": "sub_1A80:\nendbr64\npush rbp\nlea rcx, sub_1960; compar\nmov edx, 10h; size\nmov rbp, rsi\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _qsort\nadd rsp, 8\nmov rsi, rbp; nmemb\nmov rdi, rbx; base\nlea rcx, sub_1900; compar\npop rbx\nmov edx, 10h; size\npop rbp\njmp _qsort", + "ida_strip_pseudo": "void __fastcall sub_1A80(void *base, size_t nmemb)\n{\n qsort(base, nmemb, 0x10uLL, sub_1960);\n qsort(base, nmemb, 0x10uLL, sub_1900);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1A80(void *base, unsigned int nmemb) {\n qsort(base, nmemb, 16uLL, sub_1960);\n qsort(base, nmemb, 16uLL, sub_1900);\n}", + "ida_pseudo_norm": "void func0(void *base, unsigned int nmemb) {\n qsort(base, nmemb, 16uLL, compare_ints_only);\n qsort(base, nmemb, 16uLL, compare_ints);\n}" + }, + { + "index": 706, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int arr1[], int m, int arr2[], int n) {\n bool hashset[1000] = {false};\n for (int i = 0; i < m; i++) {\n hashset[arr1[i]] = true;\n }\n for (int i = 0; i < n; i++) {\n if (hashset[arr2[i]]) {\n continue;\n } else {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n int arr1[] = {11, 1, 13, 21, 3, 7};\n\n int arr2[] = {11, 3, 7, 1};\n\n assert(func0(arr1, 6, arr2, 4) == true);\n\n\n\n int arr3[] = {1, 2, 3, 4, 5, 6};\n\n int arr4[] = {1, 2, 4};\n\n assert(func0(arr3, 6, arr4, 3) == true);\n\n\n\n int arr5[] = {10, 5, 2, 23, 19};\n\n int arr6[] = {19, 5, 3};\n\n assert(func0(arr5, 5, arr6, 3) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x420,%rsp\nmov %rdi,-0x408(%rbp)\nmov %esi,-0x40c(%rbp)\nmov %rdx,-0x418(%rbp)\nmov %ecx,-0x410(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea -0x3f0(%rbp),%rdx\nmov $0x0,%eax\nmov $0x7d,%ecx\nmov %rdx,%rdi\nrep stos %rax,%es:(%rdi)\nmovl $0x0,-0x3f8(%rbp)\njmp 11f1 \nmov -0x3f8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x408(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncltq\nmovb $0x1,-0x3f0(%rbp,%rax,1)\naddl $0x1,-0x3f8(%rbp)\nmov -0x3f8(%rbp),%eax\ncmp -0x40c(%rbp),%eax\njl 11c4 \nmovl $0x0,-0x3f4(%rbp)\njmp 1245 \nmov -0x3f4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x418(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncltq\nmovzbl -0x3f0(%rbp,%rax,1),%eax\ntest %al,%al\nje 123e \naddl $0x1,-0x3f4(%rbp)\njmp 1245 \nmov $0x0,%eax\njmp 1258 \nmov -0x3f4(%rbp),%eax\ncmp -0x410(%rbp),%eax\njl 120b \nmov $0x1,%eax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 126c \ncallq 1060 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 420h\nmov [rbp+var_408], rdi\nmov [rbp+var_40C], esi\nmov [rbp+var_418], rdx\nmov [rbp+var_410], ecx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rdx, [rbp+var_3F0]\nmov eax, 0\nmov ecx, 7Dh ; '}'\nmov rdi, rdx\nrep stosq\nmov [rbp+var_3F8], 0\njmp short loc_11F1\nloc_11C4:\nmov eax, [rbp+var_3F8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_408]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nmov [rbp+rax+var_3F0], 1\nadd [rbp+var_3F8], 1\nloc_11F1:\nmov eax, [rbp+var_3F8]\ncmp eax, [rbp+var_40C]\njl short loc_11C4\nmov [rbp+var_3F4], 0\njmp short loc_1244\nloc_120B:\nmov eax, [rbp+var_3F4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_418]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nmovzx eax, [rbp+rax+var_3F0]\ntest al, al\njnz short loc_123C\nmov eax, 0\njmp short loc_1257\nloc_123C:\nnop\nadd [rbp+var_3F4], 1\nloc_1244:\nmov eax, [rbp+var_3F4]\ncmp eax, [rbp+var_410]\njl short loc_120B\nmov eax, 1\nloc_1257:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_126B\ncall ___stack_chk_fail\nlocret_126B:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3, int a4)\n{\n int i; // [rsp+28h] [rbp-3F8h]\n int j; // [rsp+2Ch] [rbp-3F4h]\n _BYTE v7[1000]; // [rsp+30h] [rbp-3F0h] BYREF\n unsigned __int64 v8; // [rsp+418h] [rbp-8h]\n\n v8 = __readfsqword(0x28u);\n memset(v7, 0, sizeof(v7));\n for ( i = 0; i < a2; ++i )\n v7[*(int *)(4LL * i + a1)] = 1;\n for ( j = 0; j < a4; ++j )\n {\n if ( !v7[*(int *)(4LL * j + a3)] )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 420h\nmov [rbp+var_408], rdi\nmov [rbp+var_40C], esi\nmov [rbp+var_418], rdx\nmov [rbp+var_410], ecx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rdx, [rbp+var_3F0]\nmov eax, 0\nmov ecx, 7Dh ; '}'\nmov rdi, rdx\nrep stosq\nmov [rbp+var_3F8], 0\njmp short loc_11F1\nloc_11C4:\nmov eax, [rbp+var_3F8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_408]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nmov [rbp+rax+var_3F0], 1\nadd [rbp+var_3F8], 1\nloc_11F1:\nmov eax, [rbp+var_3F8]\ncmp eax, [rbp+var_40C]\njl short loc_11C4\nmov [rbp+var_3F4], 0\njmp short loc_1244\nloc_120B:\nmov eax, [rbp+var_3F4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_418]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nmovzx eax, [rbp+rax+var_3F0]\ntest al, al\njnz short loc_123C\nmov eax, 0\njmp short loc_1257\nloc_123C:\nnop\nadd [rbp+var_3F4], 1\nloc_1244:\nmov eax, [rbp+var_3F4]\ncmp eax, [rbp+var_410]\njl short loc_120B\nmov eax, 1\nloc_1257:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_126B\ncall ___stack_chk_fail\nlocret_126B:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, __int64 a3, int a4)\n{\n int i; // [rsp+28h] [rbp-3F8h]\n int j; // [rsp+2Ch] [rbp-3F4h]\n _BYTE v7[1000]; // [rsp+30h] [rbp-3F0h] BYREF\n unsigned __int64 v8; // [rsp+418h] [rbp-8h]\n\n v8 = __readfsqword(0x28u);\n memset(v7, 0, sizeof(v7));\n for ( i = 0; i < a2; ++i )\n v7[*(int *)(4LL * i + a1)] = 1;\n for ( j = 0; j < a4; ++j )\n {\n if ( !v7[*(int *)(4LL * j + a3)] )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, long long a3, int a4) {\n int i;\n int j;\n uint8_t v7[1000];\n unsigned long long v8;\n v8 = __readfsqword(40u);\n memset(v7, 0, sizeof(v7));\n for (i = 0; i < a2; ++i) v7[*(int *)(4LL * i + a1)] = 1;\n for (j = 0; j < a4; ++j) {\n if (!v7[*(int *)(4LL * j + a3)]) return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3, int a4) {\n int i;\n int j;\n uint8_t v7[1000];\n unsigned long long v8;\n v8 = __readfsqword(40u);\n memset(v7, 0, sizeof(v7));\n for (i = 0; i < a2; ++i) v7[*(int *)(4LL * i + a1)] = 1;\n for (j = 0; j < a4; ++j) {\n if (!v7[*(int *)(4LL * j + a3)]) return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": 706, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int arr1[], int m, int arr2[], int n) {\n bool hashset[1000] = {false};\n for (int i = 0; i < m; i++) {\n hashset[arr1[i]] = true;\n }\n for (int i = 0; i < n; i++) {\n if (hashset[arr2[i]]) {\n continue;\n } else {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n int arr1[] = {11, 1, 13, 21, 3, 7};\n\n int arr2[] = {11, 3, 7, 1};\n\n assert(func0(arr1, 6, arr2, 4) == true);\n\n\n\n int arr3[] = {1, 2, 3, 4, 5, 6};\n\n int arr4[] = {1, 2, 4};\n\n assert(func0(arr3, 6, arr4, 3) == true);\n\n\n\n int arr5[] = {10, 5, 2, 23, 19};\n\n int arr6[] = {19, 5, 3};\n\n assert(func0(arr5, 5, arr6, 3) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x3f8,%rsp\nmov %rdi,%r9\nmov %ecx,%r8d\nmov %fs:0x28,%rax\nmov %rax,0x3e8(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nmov $0x7d,%ecx\nrep stos %rax,%es:(%rdi)\ntest %esi,%esi\njle 11b7 \nmov %r9,%rax\nlea -0x1(%rsi),%ecx\nlea 0x4(%r9,%rcx,4),%rsi\nmovslq (%rax),%rcx\nmovb $0x1,(%rsp,%rcx,1)\nadd $0x4,%rax\ncmp %rsi,%rax\njne 11a7 \ntest %r8d,%r8d\njle 11fb \nmov %rdx,%rax\nlea -0x1(%r8),%ecx\nlea 0x4(%rdx,%rcx,4),%rcx\nmovslq (%rax),%rdx\nmovzbl (%rsp,%rdx,1),%edx\ntest %dl,%dl\njne 11f0 \nmov 0x3e8(%rsp),%rax\nxor %fs:0x28,%rax\njne 1202 \nmov %edx,%eax\nadd $0x3f8,%rsp\nretq\nadd $0x4,%rax\ncmp %rcx,%rax\njne 11c8 \njmp 11d3 \nmov $0x1,%edx\njmp 11d3 \ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 3F8h\nmov r10, rdi\nmov r9, rdx\nmov r8d, ecx\nmov rax, fs:28h\nmov [rsp+3F8h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nmov ecx, 7Dh ; '}'\nrep stosq\ntest esi, esi\njle short loc_11B9\nmov rax, r10\nmovsxd rsi, esi\nlea rcx, [r10+rsi*4]\nloc_11A9:\nmovsxd rdx, dword ptr [rax]\nmov [rsp+rdx+3F8h+var_3F8], 1\nadd rax, 4\ncmp rax, rcx\njnz short loc_11A9\nloc_11B9:\ntest r8d, r8d\njle short loc_11FB\nmov rax, r9\nmovsxd r8, r8d\nlea rcx, [r9+r8*4]\nloc_11C8:\nmovsxd rdx, dword ptr [rax]\nmovzx edx, [rsp+rdx+3F8h+var_3F8]\ntest dl, dl\njnz short loc_11F0\nloc_11D3:\nmov rax, [rsp+3F8h+var_10]\nsub rax, fs:28h\njnz short loc_1202\nmov eax, edx\nadd rsp, 3F8h\nretn\nloc_11F0:\nadd rax, 4\ncmp rax, rcx\njnz short loc_11C8\njmp short loc_11D3\nloc_11FB:\nmov edx, 1\njmp short loc_11D3\nloc_1202:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2, int *a3, int a4)\n{\n int *v5; // rax\n int *v6; // rax\n unsigned int v7; // edx\n _BYTE v9[1000]; // [rsp+0h] [rbp-3F8h] BYREF\n unsigned __int64 v10; // [rsp+3E8h] [rbp-10h]\n\n v10 = __readfsqword(0x28u);\n memset(v9, 0, sizeof(v9));\n if ( a2 > 0 )\n {\n v5 = a1;\n do\n v9[*v5++] = 1;\n while ( v5 != &a1[a2] );\n }\n if ( a4 <= 0 )\n {\n return 1;\n }\n else\n {\n v6 = a3;\n do\n {\n v7 = (unsigned __int8)v9[*v6];\n if ( !(_BYTE)v7 )\n break;\n ++v6;\n }\n while ( v6 != &a3[a4] );\n }\n return v7;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nsub rsp, 3F8h\nmov r10, rdi\nmov r9, rdx\nmov r8d, ecx\nmov rax, fs:28h\nmov [rsp+3F8h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nmov ecx, 7Dh ; '}'\nrep stosq\ntest esi, esi\njle short loc_11B9\nmov rax, r10\nmovsxd rsi, esi\nlea rcx, [r10+rsi*4]\nloc_11A9:\nmovsxd rdx, dword ptr [rax]\nmov [rsp+rdx+3F8h+var_3F8], 1\nadd rax, 4\ncmp rax, rcx\njnz short loc_11A9\nloc_11B9:\ntest r8d, r8d\njle short loc_11FB\nmov rax, r9\nmovsxd r8, r8d\nlea rcx, [r9+r8*4]\nloc_11C8:\nmovsxd rdx, dword ptr [rax]\nmovzx edx, [rsp+rdx+3F8h+var_3F8]\ntest dl, dl\njnz short loc_11F0\nloc_11D3:\nmov rax, [rsp+3F8h+var_10]\nsub rax, fs:28h\njnz short loc_1202\nmov eax, edx\nadd rsp, 3F8h\nretn\nloc_11F0:\nadd rax, 4\ncmp rax, rcx\njnz short loc_11C8\njmp short loc_11D3\nloc_11FB:\nmov edx, 1\njmp short loc_11D3\nloc_1202:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int *a1, int a2, int *a3, int a4)\n{\n int *v5; // rax\n int *v6; // rax\n unsigned int v7; // edx\n _BYTE v9[1000]; // [rsp+0h] [rbp-3F8h] BYREF\n unsigned __int64 v10; // [rsp+3E8h] [rbp-10h]\n\n v10 = __readfsqword(0x28u);\n memset(v9, 0, sizeof(v9));\n if ( a2 > 0 )\n {\n v5 = a1;\n do\n v9[*v5++] = 1;\n while ( v5 != &a1[a2] );\n }\n if ( a4 <= 0 )\n {\n return 1;\n }\n else\n {\n v6 = a3;\n do\n {\n v7 = (unsigned __int8)v9[*v6];\n if ( !(_BYTE)v7 )\n break;\n ++v6;\n }\n while ( v6 != &a3[a4] );\n }\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int *a1, int a2, int *a3, int a4) {\n int *v5;\n int *v6;\n unsigned int v7;\n uint8_t v9[1000];\n unsigned long long v10;\n v10 = __readfsqword(40u);\n memset(v9, 0, sizeof(v9));\n if (a2 > 0) {\n v5 = a1;\n do\n v9[*v5++] = 1;\n while (v5 != &a1[a2]);\n }\n if (a4 <= 0) {\n return 1;\n } else {\n v6 = a3;\n do {\n v7 = (unsigned char)v9[*v6];\n if (!(uint8_t)v7) break;\n ++v6;\n } while (v6 != &a3[a4]);\n }\n return v7;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2, int *a3, int a4) {\n int *v5;\n int *v6;\n unsigned int v7;\n uint8_t v9[1000];\n unsigned long long v10;\n v10 = __readfsqword(40u);\n memset(v9, 0, sizeof(v9));\n if (a2 > 0) {\n v5 = a1;\n do\n v9[*v5++] = 1;\n while (v5 != &a1[a2]);\n }\n if (a4 <= 0) {\n return 1;\n } else {\n v6 = a3;\n do {\n v7 = (unsigned char)v9[*v6];\n if (!(uint8_t)v7) break;\n ++v6;\n } while (v6 != &a3[a4]);\n }\n return v7;\n}" + }, + { + "index": 706, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int arr1[], int m, int arr2[], int n) {\n bool hashset[1000] = {false};\n for (int i = 0; i < m; i++) {\n hashset[arr1[i]] = true;\n }\n for (int i = 0; i < n; i++) {\n if (hashset[arr2[i]]) {\n continue;\n } else {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n int arr1[] = {11, 1, 13, 21, 3, 7};\n\n int arr2[] = {11, 3, 7, 1};\n\n assert(func0(arr1, 6, arr2, 4) == true);\n\n\n\n int arr3[] = {1, 2, 3, 4, 5, 6};\n\n int arr4[] = {1, 2, 4};\n\n assert(func0(arr3, 6, arr4, 3) == true);\n\n\n\n int arr5[] = {10, 5, 2, 23, 19};\n\n int arr6[] = {19, 5, 3};\n\n assert(func0(arr5, 5, arr6, 3) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x3f8,%rsp\nmov %rdi,%r8\nmov %ecx,%r9d\nmov $0x7d,%ecx\nmov %fs:0x28,%rax\nmov %rax,0x3e8(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nrep stos %rax,%es:(%rdi)\ntest %esi,%esi\njle 11b0 \nlea -0x1(%rsi),%eax\nmov %r8,%rdi\nlea 0x4(%r8,%rax,4),%rcx\nxchg %ax,%ax\nmovslq (%rdi),%rax\nadd $0x4,%rdi\nmovb $0x1,(%rsp,%rax,1)\ncmp %rcx,%rdi\njne 11a0 \ntest %r9d,%r9d\njle 11f3 \nlea -0x1(%r9),%eax\nlea 0x4(%rdx,%rax,4),%rcx\nmovslq (%rdx),%rax\nmovzbl (%rsp,%rax,1),%eax\ntest %al,%al\nje 11d8 \nadd $0x4,%rdx\ncmp %rcx,%rdx\njne 11be \nnopw 0x0(%rax,%rax,1)\nmov 0x3e8(%rsp),%rsi\nxor %fs:0x28,%rsi\njne 11fa \nadd $0x3f8,%rsp\nretq\nmov $0x1,%eax\njmp 11d8 \ncallq 1050 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 3F8h\nmov r10, rdi\nmovsxd r8, ecx\nmov r9, rdx\nmov rax, fs:28h\nmov [rsp+3F8h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nmov ecx, 7Dh ; '}'\nrep stosq\ntest esi, esi\njle short loc_1340\nmovsxd rsi, esi\nmov rax, r10\nlea rcx, [r10+rsi*4]\nloc_1330:\nmovsxd rdx, dword ptr [rax]\nadd rax, 4\nmov [rsp+rdx+3F8h+var_3F8], 1\ncmp rax, rcx\njnz short loc_1330\nloc_1340:\ntest r8d, r8d\njle short loc_137D\nmov rax, r9\nlea rcx, [r9+r8*4]\nloc_134C:\nmovsxd rdx, dword ptr [rax]\nmovzx edx, [rsp+rdx+3F8h+var_3F8]\ntest dl, dl\njz short loc_1360\nadd rax, 4\ncmp rcx, rax\njnz short loc_134C\nloc_1360:\nmov rax, [rsp+3F8h+var_10]\nsub rax, fs:28h\njnz short loc_1384\nmov eax, edx\nadd rsp, 3F8h\nretn\nloc_137D:\nmov edx, 1\njmp short loc_1360\nloc_1384:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2, int *a3, int a4)\n{\n int *v5; // rax\n __int64 v6; // rdx\n int *v7; // rax\n unsigned int v8; // edx\n _BYTE v10[1000]; // [rsp+0h] [rbp-3F8h] BYREF\n unsigned __int64 v11; // [rsp+3E8h] [rbp-10h]\n\n v11 = __readfsqword(0x28u);\n memset(v10, 0, sizeof(v10));\n if ( a2 > 0 )\n {\n v5 = a1;\n do\n {\n v6 = *v5++;\n v10[v6] = 1;\n }\n while ( v5 != &a1[a2] );\n }\n if ( a4 <= 0 )\n {\n return 1;\n }\n else\n {\n v7 = a3;\n do\n {\n v8 = (unsigned __int8)v10[*v7];\n if ( !(_BYTE)v8 )\n break;\n ++v7;\n }\n while ( &a3[a4] != v7 );\n }\n return v8;\n}", + "ida_strip_asm": "sub_12F0:\nendbr64\nsub rsp, 3F8h\nmov r10, rdi\nmovsxd r8, ecx\nmov r9, rdx\nmov rax, fs:28h\nmov [rsp+3F8h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nmov ecx, 7Dh ; '}'\nrep stosq\ntest esi, esi\njle short loc_1340\nmovsxd rsi, esi\nmov rax, r10\nlea rcx, [r10+rsi*4]\nloc_1330:\nmovsxd rdx, dword ptr [rax]\nadd rax, 4\nmov [rsp+rdx+3F8h+var_3F8], 1\ncmp rax, rcx\njnz short loc_1330\nloc_1340:\ntest r8d, r8d\njle short loc_137D\nmov rax, r9\nlea rcx, [r9+r8*4]\nloc_134C:\nmovsxd rdx, dword ptr [rax]\nmovzx edx, [rsp+rdx+3F8h+var_3F8]\ntest dl, dl\njz short loc_1360\nadd rax, 4\ncmp rcx, rax\njnz short loc_134C\nloc_1360:\nmov rax, [rsp+3F8h+var_10]\nsub rax, fs:28h\njnz short loc_1384\nmov eax, edx\nadd rsp, 3F8h\nretn\nloc_137D:\nmov edx, 1\njmp short loc_1360\nloc_1384:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12F0(int *a1, int a2, int *a3, int a4)\n{\n int *v5; // rax\n __int64 v6; // rdx\n int *v7; // rax\n unsigned int v8; // edx\n _BYTE v10[1000]; // [rsp+0h] [rbp-3F8h] BYREF\n unsigned __int64 v11; // [rsp+3E8h] [rbp-10h]\n\n v11 = __readfsqword(0x28u);\n memset(v10, 0, sizeof(v10));\n if ( a2 > 0 )\n {\n v5 = a1;\n do\n {\n v6 = *v5++;\n v10[v6] = 1;\n }\n while ( v5 != &a1[a2] );\n }\n if ( a4 <= 0 )\n {\n return 1;\n }\n else\n {\n v7 = a3;\n do\n {\n v8 = (unsigned __int8)v10[*v7];\n if ( !(_BYTE)v8 )\n break;\n ++v7;\n }\n while ( &a3[a4] != v7 );\n }\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12F0(int *a1, int a2, int *a3, int a4) {\n int *v5;\n long long v6;\n int *v7;\n unsigned int v8;\n uint8_t v10[1000];\n unsigned long long v11;\n v11 = __readfsqword(40u);\n memset(v10, 0, sizeof(v10));\n if (a2 > 0) {\n v5 = a1;\n do {\n v6 = *v5++;\n v10[v6] = 1;\n } while (v5 != &a1[a2]);\n }\n if (a4 <= 0) {\n return 1;\n } else {\n v7 = a3;\n do {\n v8 = (unsigned char)v10[*v7];\n if (!(uint8_t)v8) break;\n ++v7;\n } while (&a3[a4] != v7);\n }\n return v8;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2, int *a3, int a4) {\n int *v5;\n long long v6;\n int *v7;\n unsigned int v8;\n uint8_t v10[1000];\n unsigned long long v11;\n v11 = __readfsqword(40u);\n memset(v10, 0, sizeof(v10));\n if (a2 > 0) {\n v5 = a1;\n do {\n v6 = *v5++;\n v10[v6] = 1;\n } while (v5 != &a1[a2]);\n }\n if (a4 <= 0) {\n return 1;\n } else {\n v7 = a3;\n do {\n v8 = (unsigned char)v10[*v7];\n if (!(uint8_t)v8) break;\n ++v7;\n } while (&a3[a4] != v7);\n }\n return v8;\n}" + }, + { + "index": 706, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int arr1[], int m, int arr2[], int n) {\n bool hashset[1000] = {false};\n for (int i = 0; i < m; i++) {\n hashset[arr1[i]] = true;\n }\n for (int i = 0; i < n; i++) {\n if (hashset[arr2[i]]) {\n continue;\n } else {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n int arr1[] = {11, 1, 13, 21, 3, 7};\n\n int arr2[] = {11, 3, 7, 1};\n\n assert(func0(arr1, 6, arr2, 4) == true);\n\n\n\n int arr3[] = {1, 2, 3, 4, 5, 6};\n\n int arr4[] = {1, 2, 4};\n\n assert(func0(arr3, 6, arr4, 3) == true);\n\n\n\n int arr5[] = {10, 5, 2, 23, 19};\n\n int arr6[] = {19, 5, 3};\n\n assert(func0(arr5, 5, arr6, 3) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x3f8,%rsp\nmov %rdi,%r8\nmov %ecx,%r9d\nmov $0x7d,%ecx\nmov %fs:0x28,%rax\nmov %rax,0x3e8(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nrep stos %rax,%es:(%rdi)\ntest %esi,%esi\njle 11b0 \nlea -0x1(%rsi),%eax\nmov %r8,%rdi\nlea 0x4(%r8,%rax,4),%rcx\nxchg %ax,%ax\nmovslq (%rdi),%rax\nadd $0x4,%rdi\nmovb $0x1,(%rsp,%rax,1)\ncmp %rcx,%rdi\njne 11a0 \ntest %r9d,%r9d\njle 11f3 \nlea -0x1(%r9),%eax\nlea 0x4(%rdx,%rax,4),%rcx\nmovslq (%rdx),%rax\nmovzbl (%rsp,%rax,1),%eax\ntest %al,%al\nje 11d8 \nadd $0x4,%rdx\ncmp %rdx,%rcx\njne 11be \nnopw 0x0(%rax,%rax,1)\nmov 0x3e8(%rsp),%rsi\nxor %fs:0x28,%rsi\njne 11fa \nadd $0x3f8,%rsp\nretq\nmov $0x1,%eax\njmp 11d8 \ncallq 1050 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 3F8h\nmov r10, rdi\nmovsxd r8, ecx\nmov r9, rdx\nmov rax, fs:28h\nmov [rsp+3F8h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nmov ecx, 7Dh ; '}'\nrep stosq\ntest esi, esi\njle short loc_1340\nmovsxd rsi, esi\nmov rax, r10\nlea rcx, [r10+rsi*4]\nloc_1330:\nmovsxd rdx, dword ptr [rax]\nadd rax, 4\nmov [rsp+rdx+3F8h+var_3F8], 1\ncmp rax, rcx\njnz short loc_1330\nloc_1340:\ntest r8d, r8d\njle short loc_137D\nmov rax, r9\nlea rcx, [r9+r8*4]\nloc_134C:\nmovsxd rdx, dword ptr [rax]\nmovzx edx, [rsp+rdx+3F8h+var_3F8]\ntest dl, dl\njz short loc_1360\nadd rax, 4\ncmp rcx, rax\njnz short loc_134C\nloc_1360:\nmov rax, [rsp+3F8h+var_10]\nsub rax, fs:28h\njnz short loc_1384\nmov eax, edx\nadd rsp, 3F8h\nretn\nloc_137D:\nmov edx, 1\njmp short loc_1360\nloc_1384:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2, int *a3, int a4)\n{\n int *v5; // rax\n __int64 v6; // rdx\n int *v7; // rax\n unsigned int v8; // edx\n _BYTE v10[1000]; // [rsp+0h] [rbp-3F8h] BYREF\n unsigned __int64 v11; // [rsp+3E8h] [rbp-10h]\n\n v11 = __readfsqword(0x28u);\n memset(v10, 0, sizeof(v10));\n if ( a2 > 0 )\n {\n v5 = a1;\n do\n {\n v6 = *v5++;\n v10[v6] = 1;\n }\n while ( v5 != &a1[a2] );\n }\n if ( a4 <= 0 )\n {\n return 1;\n }\n else\n {\n v7 = a3;\n do\n {\n v8 = (unsigned __int8)v10[*v7];\n if ( !(_BYTE)v8 )\n break;\n ++v7;\n }\n while ( &a3[a4] != v7 );\n }\n return v8;\n}", + "ida_strip_asm": "sub_12F0:\nendbr64\nsub rsp, 3F8h\nmov r10, rdi\nmovsxd r8, ecx\nmov r9, rdx\nmov rax, fs:28h\nmov [rsp+3F8h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nmov ecx, 7Dh ; '}'\nrep stosq\ntest esi, esi\njle short loc_1340\nmovsxd rsi, esi\nmov rax, r10\nlea rcx, [r10+rsi*4]\nloc_1330:\nmovsxd rdx, dword ptr [rax]\nadd rax, 4\nmov [rsp+rdx+3F8h+var_3F8], 1\ncmp rax, rcx\njnz short loc_1330\nloc_1340:\ntest r8d, r8d\njle short loc_137D\nmov rax, r9\nlea rcx, [r9+r8*4]\nloc_134C:\nmovsxd rdx, dword ptr [rax]\nmovzx edx, [rsp+rdx+3F8h+var_3F8]\ntest dl, dl\njz short loc_1360\nadd rax, 4\ncmp rcx, rax\njnz short loc_134C\nloc_1360:\nmov rax, [rsp+3F8h+var_10]\nsub rax, fs:28h\njnz short loc_1384\nmov eax, edx\nadd rsp, 3F8h\nretn\nloc_137D:\nmov edx, 1\njmp short loc_1360\nloc_1384:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12F0(int *a1, int a2, int *a3, int a4)\n{\n int *v5; // rax\n __int64 v6; // rdx\n int *v7; // rax\n unsigned int v8; // edx\n _BYTE v10[1000]; // [rsp+0h] [rbp-3F8h] BYREF\n unsigned __int64 v11; // [rsp+3E8h] [rbp-10h]\n\n v11 = __readfsqword(0x28u);\n memset(v10, 0, sizeof(v10));\n if ( a2 > 0 )\n {\n v5 = a1;\n do\n {\n v6 = *v5++;\n v10[v6] = 1;\n }\n while ( v5 != &a1[a2] );\n }\n if ( a4 <= 0 )\n {\n return 1;\n }\n else\n {\n v7 = a3;\n do\n {\n v8 = (unsigned __int8)v10[*v7];\n if ( !(_BYTE)v8 )\n break;\n ++v7;\n }\n while ( &a3[a4] != v7 );\n }\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12F0(int *a1, int a2, int *a3, int a4) {\n int *v5;\n long long v6;\n int *v7;\n unsigned int v8;\n uint8_t v10[1000];\n unsigned long long v11;\n v11 = __readfsqword(40u);\n memset(v10, 0, sizeof(v10));\n if (a2 > 0) {\n v5 = a1;\n do {\n v6 = *v5++;\n v10[v6] = 1;\n } while (v5 != &a1[a2]);\n }\n if (a4 <= 0) {\n return 1;\n } else {\n v7 = a3;\n do {\n v8 = (unsigned char)v10[*v7];\n if (!(uint8_t)v8) break;\n ++v7;\n } while (&a3[a4] != v7);\n }\n return v8;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2, int *a3, int a4) {\n int *v5;\n long long v6;\n int *v7;\n unsigned int v8;\n uint8_t v10[1000];\n unsigned long long v11;\n v11 = __readfsqword(40u);\n memset(v10, 0, sizeof(v10));\n if (a2 > 0) {\n v5 = a1;\n do {\n v6 = *v5++;\n v10[v6] = 1;\n } while (v5 != &a1[a2]);\n }\n if (a4 <= 0) {\n return 1;\n } else {\n v7 = a3;\n do {\n v8 = (unsigned char)v10[*v7];\n if (!(uint8_t)v8) break;\n ++v7;\n } while (&a3[a4] != v7);\n }\n return v8;\n}" + }, + { + "index": 707, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n n += 1;\n int powerOf2 = 2;\n int cnt = n / 2;\n while (powerOf2 <= n) {\n int totalPairs = n / powerOf2;\n cnt += (totalPairs / 2) * powerOf2;\n if (totalPairs & 1) {\n cnt += (n % powerOf2);\n }\n powerOf2 <<= 1;\n }\n return cnt;\n}", + "test": "int main() {\n\n assert(func0(16) == 33);\n\n assert(func0(2) == 2);\n\n assert(func0(14) == 28);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\naddl $0x1,-0x14(%rbp)\nmovl $0x2,-0xc(%rbp)\nmov -0x14(%rbp),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nmov %eax,-0x8(%rbp)\njmp 11a6 \nmov -0x14(%rbp),%eax\ncltd\nidivl -0xc(%rbp)\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nimul -0xc(%rbp),%eax\nadd %eax,-0x8(%rbp)\nmov -0x4(%rbp),%eax\nand $0x1,%eax\ntest %eax,%eax\nje 11a3 \nmov -0x14(%rbp),%eax\ncltd\nidivl -0xc(%rbp)\nmov %edx,%eax\nadd %eax,-0x8(%rbp)\nshll -0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x14(%rbp),%eax\njle 1170 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nadd [rbp+var_14], 1\nmov [rbp+var_C], 2\nmov eax, [rbp+var_14]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_8], eax\njmp short loc_11A6\nloc_1170:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_C]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nimul eax, [rbp+var_C]\nadd [rbp+var_8], eax\nmov eax, [rbp+var_4]\nand eax, 1\ntest eax, eax\njz short loc_11A3\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_C]\nmov eax, edx\nadd [rbp+var_8], eax\nloc_11A3:\nshl [rbp+var_C], 1\nloc_11A6:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_14]\njle short loc_1170\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v2; // [rsp+0h] [rbp-14h]\n int v3; // [rsp+8h] [rbp-Ch]\n unsigned int v4; // [rsp+Ch] [rbp-8h]\n\n v2 = a1 + 1;\n v3 = 2;\n v4 = (a1 + 1) / 2;\n while ( v3 <= v2 )\n {\n v4 += v3 * (v2 / v3 / 2);\n if ( ((v2 / v3) & 1) != 0 )\n v4 += v2 % v3;\n v3 *= 2;\n }\n return v4;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nadd [rbp+var_14], 1\nmov [rbp+var_C], 2\nmov eax, [rbp+var_14]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_8], eax\njmp short loc_11A6\nloc_1170:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_C]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nimul eax, [rbp+var_C]\nadd [rbp+var_8], eax\nmov eax, [rbp+var_4]\nand eax, 1\ntest eax, eax\njz short loc_11A3\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_C]\nmov eax, edx\nadd [rbp+var_8], eax\nloc_11A3:\nshl [rbp+var_C], 1\nloc_11A6:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_14]\njle short loc_1170\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v2; // [rsp+0h] [rbp-14h]\n int v3; // [rsp+8h] [rbp-Ch]\n unsigned int v4; // [rsp+Ch] [rbp-8h]\n\n v2 = a1 + 1;\n v3 = 2;\n v4 = (a1 + 1) / 2;\n while ( v3 <= v2 )\n {\n v4 += v3 * (v2 / v3 / 2);\n if ( ((v2 / v3) & 1) != 0 )\n v4 += v2 % v3;\n v3 *= 2;\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v2;\n int v3;\n unsigned int v4;\n v2 = a1 + 1;\n v3 = 2;\n v4 = (a1 + 1) / 2;\n while (v3 <= v2) {\n v4 += v3 * (v2 / v3 / 2);\n if (((v2 / v3) & 1) != 0) v4 += v2 % v3;\n v3 *= 2;\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v2;\n int v3;\n unsigned int v4;\n v2 = a1 + 1;\n v3 = 2;\n v4 = (a1 + 1) / 2;\n while (v3 <= v2) {\n v4 += v3 * (v2 / v3 / 2);\n if (((v2 / v3) & 1) != 0) v4 += v2 % v3;\n v3 *= 2;\n }\n return v4;\n}" + }, + { + "index": 707, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n n += 1;\n int powerOf2 = 2;\n int cnt = n / 2;\n while (powerOf2 <= n) {\n int totalPairs = n / powerOf2;\n cnt += (totalPairs / 2) * powerOf2;\n if (totalPairs & 1) {\n cnt += (n % powerOf2);\n }\n powerOf2 <<= 1;\n }\n return cnt;\n}", + "test": "int main() {\n\n assert(func0(16) == 33);\n\n assert(func0(2) == 2);\n\n assert(func0(14) == 28);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nadd $0x1,%edi\nmov %edi,%esi\nshr $0x1f,%esi\nadd %edi,%esi\nsar %esi\ncmp $0x1,%edi\njle 118b \nmov $0x2,%ecx\njmp 116b \nadd %ecx,%ecx\ncmp %ecx,%edi\njl 118b \nmov %edi,%eax\ncltd\nidiv %ecx\nmov %eax,%edx\nshr $0x1f,%edx\nadd %eax,%edx\nsar %edx\nimul %ecx,%edx\nadd %edx,%esi\ntest $0x1,%al\nje 1165 \nmov %edi,%eax\ncltd\nidiv %ecx\nadd %edx,%esi\njmp 1165 \nmov %esi,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nadd edi, 1\nmov esi, edi\nshr esi, 1Fh\nadd esi, edi\nsar esi, 1\ncmp edi, 1\njle short loc_118B\nmov ecx, 2\njmp short loc_116B\nloc_1165:\nadd ecx, ecx\ncmp edi, ecx\njl short loc_118B\nloc_116B:\nmov eax, edi\ncdq\nidiv ecx\nmov edx, eax\nshr edx, 1Fh\nadd edx, eax\nsar edx, 1\nimul edx, ecx\nadd esi, edx\ntest al, 1\njz short loc_1165\nmov eax, edi\ncdq\nidiv ecx\nadd esi, edx\njmp short loc_1165\nloc_118B:\nmov eax, esi\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // edi\n unsigned int v2; // esi\n int i; // ecx\n\n v1 = a1 + 1;\n v2 = v1 / 2;\n if ( v1 > 1 )\n {\n for ( i = 2; i <= v1; i *= 2 )\n {\n v2 += i * (v1 / i / 2);\n if ( ((v1 / i) & 1) != 0 )\n v2 += v1 % i;\n }\n }\n return v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nadd edi, 1\nmov esi, edi\nshr esi, 1Fh\nadd esi, edi\nsar esi, 1\ncmp edi, 1\njle short loc_118B\nmov ecx, 2\njmp short loc_116B\nloc_1165:\nadd ecx, ecx\ncmp edi, ecx\njl short loc_118B\nloc_116B:\nmov eax, edi\ncdq\nidiv ecx\nmov edx, eax\nshr edx, 1Fh\nadd edx, eax\nsar edx, 1\nimul edx, ecx\nadd esi, edx\ntest al, 1\njz short loc_1165\nmov eax, edi\ncdq\nidiv ecx\nadd esi, edx\njmp short loc_1165\nloc_118B:\nmov eax, esi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v1; // edi\n unsigned int v2; // esi\n int i; // ecx\n\n v1 = a1 + 1;\n v2 = v1 / 2;\n if ( v1 > 1 )\n {\n for ( i = 2; i <= v1; i *= 2 )\n {\n v2 += i * (v1 / i / 2);\n if ( ((v1 / i) & 1) != 0 )\n v2 += v1 % i;\n }\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v1;\n unsigned int v2;\n int i;\n v1 = a1 + 1;\n v2 = v1 / 2;\n if (v1 > 1) {\n for (i = 2; i <= v1; i *= 2) {\n v2 += i * (v1 / i / 2);\n if (((v1 / i) & 1) != 0) v2 += v1 % i;\n }\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n unsigned int v2;\n int i;\n v1 = a1 + 1;\n v2 = v1 / 2;\n if (v1 > 1) {\n for (i = 2; i <= v1; i *= 2) {\n v2 += i * (v1 / i / 2);\n if (((v1 / i) & 1) != 0) v2 += v1 % i;\n }\n }\n return v2;\n}" + }, + { + "index": 707, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n n += 1;\n int powerOf2 = 2;\n int cnt = n / 2;\n while (powerOf2 <= n) {\n int totalPairs = n / powerOf2;\n cnt += (totalPairs / 2) * powerOf2;\n if (totalPairs & 1) {\n cnt += (n % powerOf2);\n }\n powerOf2 <<= 1;\n }\n return cnt;\n}", + "test": "int main() {\n\n assert(func0(16) == 33);\n\n assert(func0(2) == 2);\n\n assert(func0(14) == 28);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nadd $0x1,%edi\nmov %edi,%r8d\nshr $0x1f,%r8d\nadd %edi,%r8d\nsar %r8d\ncmp $0x1,%edi\njle 1263 \nmov $0x2,%esi\nxchg %ax,%ax\nmov %edi,%eax\ncltd\nidiv %esi\nmov %eax,%ecx\nshr $0x1f,%ecx\nadd %eax,%ecx\nsar %ecx\nimul %esi,%ecx\nadd %ecx,%r8d\nadd %r8d,%edx\ntest $0x1,%al\ncmovne %edx,%r8d\nadd %esi,%esi\ncmp %esi,%edi\njge 1240 \nmov %r8d,%eax\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nadd edi, 1\nmov r8d, edi\nshr r8d, 1Fh\nadd r8d, edi\nsar r8d, 1\ncmp edi, 1\njle short loc_1233\nmov esi, 2\nxchg ax, ax\nloc_1210:\nmov eax, edi\ncdq\nidiv esi\nmov ecx, eax\nshr ecx, 1Fh\nadd ecx, eax\nsar ecx, 1\nimul ecx, esi\nadd r8d, ecx\nadd edx, r8d\ntest al, 1\ncmovnz r8d, edx\nadd esi, esi\ncmp edi, esi\njge short loc_1210\nloc_1233:\nmov eax, r8d\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // edi\n unsigned int v2; // r8d\n int i; // esi\n\n v1 = a1 + 1;\n v2 = v1 / 2;\n if ( v1 > 1 )\n {\n for ( i = 2; i <= v1; i *= 2 )\n {\n v2 += i * (v1 / i / 2);\n if ( ((v1 / i) & 1) != 0 )\n v2 += v1 % i;\n }\n }\n return v2;\n}", + "ida_strip_asm": "sub_11F0:\nendbr64\nadd edi, 1\nmov r8d, edi\nshr r8d, 1Fh\nadd r8d, edi\nsar r8d, 1\ncmp edi, 1\njle short loc_1233\nmov esi, 2\nxchg ax, ax\nloc_1210:\nmov eax, edi\ncdq\nidiv esi\nmov ecx, eax\nshr ecx, 1Fh\nadd ecx, eax\nsar ecx, 1\nimul ecx, esi\nadd r8d, ecx\nadd edx, r8d\ntest al, 1\ncmovnz r8d, edx\nadd esi, esi\ncmp edi, esi\njge short loc_1210\nloc_1233:\nmov eax, r8d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11F0(int a1)\n{\n int v1; // edi\n unsigned int v2; // r8d\n int i; // esi\n\n v1 = a1 + 1;\n v2 = v1 / 2;\n if ( v1 > 1 )\n {\n for ( i = 2; i <= v1; i *= 2 )\n {\n v2 += i * (v1 / i / 2);\n if ( ((v1 / i) & 1) != 0 )\n v2 += v1 % i;\n }\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11F0(int a1) {\n int v1;\n unsigned int v2;\n int i;\n v1 = a1 + 1;\n v2 = v1 / 2;\n if (v1 > 1) {\n for (i = 2; i <= v1; i *= 2) {\n v2 += i * (v1 / i / 2);\n if (((v1 / i) & 1) != 0) v2 += v1 % i;\n }\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n unsigned int v2;\n int i;\n v1 = a1 + 1;\n v2 = v1 / 2;\n if (v1 > 1) {\n for (i = 2; i <= v1; i *= 2) {\n v2 += i * (v1 / i / 2);\n if (((v1 / i) & 1) != 0) v2 += v1 % i;\n }\n }\n return v2;\n}" + }, + { + "index": 708, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(const char* string) {\n int count = 1;\n for (int i = 0; string[i] != '\\0'; i++) {\n if (string[i] == ' ') count++;\n }\n char** list = malloc(count * sizeof(char*));\n int start = 0, idx = 0;\n for (int i = 0; string[i] != '\\0'; i++) {\n if (string[i] == ' ') {\n int len = i - start;\n list[idx] = malloc(len + 1);\n strncpy(list[idx], string + start, len);\n list[idx][len] = '\\0';\n idx++;\n start = i + 1;\n }\n }\n int len = strlen(string) - start;\n list[idx] = malloc(len + 1);\n strncpy(list[idx], string + start, len);\n list[idx][len] = '\\0';\n return list;\n}", + "test": "int main(){\n\n char** res1 = func0(\"python program\");\n\n assert(strcmp(res1[0], \"python\") == 0);\n\n assert(strcmp(res1[1], \"program\") == 0);\n\n \n\n char** res2 = func0(\"Data Analysis\");\n\n assert(strcmp(res2[0], \"Data\") == 0);\n\n assert(strcmp(res2[1], \"Analysis\") == 0);\n\n \n\n char** res3 = func0(\"Hadoop Training\");\n\n assert(strcmp(res3[0], \"Hadoop\") == 0);\n\n assert(strcmp(res3[1], \"Training\") == 0);\n\n \n\n // Free allocated memory\n\n for(int i = 0; i < 2; i++) {\n\n free(res1[i]);\n\n free(res2[i]);\n\n free(res3[i]);\n\n }\n\n free(res1);\n\n free(res2);\n\n free(res3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x48,%rsp\nmov %rdi,-0x48(%rbp)\nmovl $0x1,-0x34(%rbp)\nmovl $0x0,-0x30(%rbp)\njmp 1226 \nmov -0x30(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x20,%al\njne 1222 \naddl $0x1,-0x34(%rbp)\naddl $0x1,-0x30(%rbp)\nmov -0x30(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 120a \nmov -0x34(%rbp),%eax\ncltq\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 10f0 \nmov %rax,-0x18(%rbp)\nmovl $0x0,-0x2c(%rbp)\nmovl $0x0,-0x28(%rbp)\nmovl $0x0,-0x24(%rbp)\njmpq 131b \nmov -0x24(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x20,%al\njne 1317 \nmov -0x24(%rbp),%eax\nsub -0x2c(%rbp),%eax\nmov %eax,-0x1c(%rbp)\nmov -0x1c(%rbp),%eax\nadd $0x1,%eax\ncltq\nmov -0x28(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x18(%rbp),%rdx\nlea (%rcx,%rdx,1),%rbx\nmov %rax,%rdi\ncallq 10f0 \nmov %rax,(%rbx)\nmov -0x1c(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x2c(%rbp),%eax\nmovslq %eax,%rcx\nmov -0x48(%rbp),%rax\nadd %rax,%rcx\nmov -0x28(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rsi\nmov -0x18(%rbp),%rax\nadd %rsi,%rax\nmov (%rax),%rax\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 10b0 \nmov -0x28(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rdx\nmov -0x1c(%rbp),%eax\ncltq\nadd %rdx,%rax\nmovb $0x0,(%rax)\naddl $0x1,-0x28(%rbp)\nmov -0x24(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x2c(%rbp)\naddl $0x1,-0x24(%rbp)\nmov -0x24(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 1269 \nmov -0x48(%rbp),%rax\nmov %rax,%rdi\ncallq 10c0 \nmov %eax,%edx\nmov -0x2c(%rbp),%eax\nsub %eax,%edx\nmov %edx,%eax\nmov %eax,-0x20(%rbp)\nmov -0x20(%rbp),%eax\nadd $0x1,%eax\ncltq\nmov -0x28(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x18(%rbp),%rdx\nlea (%rcx,%rdx,1),%rbx\nmov %rax,%rdi\ncallq 10f0 \nmov %rax,(%rbx)\nmov -0x20(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x2c(%rbp),%eax\nmovslq %eax,%rcx\nmov -0x48(%rbp),%rax\nadd %rax,%rcx\nmov -0x28(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rsi\nmov -0x18(%rbp),%rax\nadd %rsi,%rax\nmov (%rax),%rax\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 10b0 \nmov -0x28(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rdx\nmov -0x20(%rbp),%eax\ncltq\nadd %rdx,%rax\nmovb $0x0,(%rax)\nmov -0x18(%rbp),%rax\nadd $0x48,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 48h\nmov [rbp+s], rdi\nmov [rbp+var_34], 1\nmov [rbp+var_30], 0\njmp short loc_1226\nloc_120A:\nmov eax, [rbp+var_30]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njnz short loc_1222\nadd [rbp+var_34], 1\nloc_1222:\nadd [rbp+var_30], 1\nloc_1226:\nmov eax, [rbp+var_30]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_120A\nmov eax, [rbp+var_34]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_2C], 0\nmov [rbp+var_28], 0\nmov [rbp+var_24], 0\njmp loc_131B\nloc_1269:\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njnz loc_1317\nmov eax, [rbp+var_24]\nsub eax, [rbp+var_2C]\nmov [rbp+var_1C], eax\nmov eax, [rbp+var_1C]\nadd eax, 1\ncdqe\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nlea rbx, [rcx+rdx]\nmov rdi, rax; size\ncall _malloc\nmov [rbx], rax\nmov eax, [rbp+var_1C]\nmovsxd rdx, eax; n\nmov eax, [rbp+var_2C]\nmovsxd rcx, eax\nmov rax, [rbp+s]\nadd rcx, rax\nmov eax, [rbp+var_28]\ncdqe\nlea rsi, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rsi\nmov rax, [rax]\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strncpy\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_1C]\ncdqe\nadd rax, rdx\nmov byte ptr [rax], 0\nadd [rbp+var_28], 1\nmov eax, [rbp+var_24]\nadd eax, 1\nmov [rbp+var_2C], eax\nloc_1317:\nadd [rbp+var_24], 1\nloc_131B:\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_1269\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov edx, eax\nmov eax, [rbp+var_2C]\nsub edx, eax\nmov [rbp+var_20], edx\nmov eax, [rbp+var_20]\nadd eax, 1\ncdqe\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nlea rbx, [rcx+rdx]\nmov rdi, rax; size\ncall _malloc\nmov [rbx], rax\nmov eax, [rbp+var_20]\nmovsxd rdx, eax; n\nmov eax, [rbp+var_2C]\nmovsxd rcx, eax\nmov rax, [rbp+s]\nadd rcx, rax\nmov eax, [rbp+var_28]\ncdqe\nlea rsi, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rsi\nmov rax, [rax]\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strncpy\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_20]\ncdqe\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(const char *a1)\n{\n int v2; // [rsp+1Ch] [rbp-34h]\n int i; // [rsp+20h] [rbp-30h]\n int v4; // [rsp+24h] [rbp-2Ch]\n int v5; // [rsp+28h] [rbp-28h]\n int j; // [rsp+2Ch] [rbp-24h]\n int v7; // [rsp+30h] [rbp-20h]\n _QWORD *v8; // [rsp+38h] [rbp-18h]\n\n v2 = 1;\n for ( i = 0; a1[i]; ++i )\n {\n if ( a1[i] == 32 )\n ++v2;\n }\n v8 = malloc(8LL * v2);\n v4 = 0;\n v5 = 0;\n for ( j = 0; a1[j]; ++j )\n {\n if ( a1[j] == 32 )\n {\n v8[v5] = malloc(j - v4 + 1);\n strncpy((char *)v8[v5], &a1[v4], j - v4);\n *(_BYTE *)(v8[v5++] + j - v4) = 0;\n v4 = j + 1;\n }\n }\n v7 = strlen(a1) - v4;\n v8[v5] = malloc(v7 + 1);\n strncpy((char *)v8[v5], &a1[v4], v7);\n *(_BYTE *)(v8[v5] + v7) = 0;\n return v8;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 48h\nmov [rbp+s], rdi\nmov [rbp+var_34], 1\nmov [rbp+var_30], 0\njmp short loc_1226\nloc_120A:\nmov eax, [rbp+var_30]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njnz short loc_1222\nadd [rbp+var_34], 1\nloc_1222:\nadd [rbp+var_30], 1\nloc_1226:\nmov eax, [rbp+var_30]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_120A\nmov eax, [rbp+var_34]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_2C], 0\nmov [rbp+var_28], 0\nmov [rbp+var_24], 0\njmp loc_131B\nloc_1269:\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njnz loc_1317\nmov eax, [rbp+var_24]\nsub eax, [rbp+var_2C]\nmov [rbp+var_1C], eax\nmov eax, [rbp+var_1C]\nadd eax, 1\ncdqe\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nlea rbx, [rcx+rdx]\nmov rdi, rax; size\ncall _malloc\nmov [rbx], rax\nmov eax, [rbp+var_1C]\nmovsxd rdx, eax; n\nmov eax, [rbp+var_2C]\nmovsxd rcx, eax\nmov rax, [rbp+s]\nadd rcx, rax\nmov eax, [rbp+var_28]\ncdqe\nlea rsi, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rsi\nmov rax, [rax]\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strncpy\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_1C]\ncdqe\nadd rax, rdx\nmov byte ptr [rax], 0\nadd [rbp+var_28], 1\nmov eax, [rbp+var_24]\nadd eax, 1\nmov [rbp+var_2C], eax\nloc_1317:\nadd [rbp+var_24], 1\nloc_131B:\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_1269\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov edx, eax\nmov eax, [rbp+var_2C]\nsub edx, eax\nmov [rbp+var_20], edx\nmov eax, [rbp+var_20]\nadd eax, 1\ncdqe\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nlea rbx, [rcx+rdx]\nmov rdi, rax; size\ncall _malloc\nmov [rbx], rax\nmov eax, [rbp+var_20]\nmovsxd rdx, eax; n\nmov eax, [rbp+var_2C]\nmovsxd rcx, eax\nmov rax, [rbp+s]\nadd rcx, rax\nmov eax, [rbp+var_28]\ncdqe\nlea rsi, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rsi\nmov rax, [rax]\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strncpy\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_20]\ncdqe\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11E9(const char *a1)\n{\n int v2; // [rsp+1Ch] [rbp-34h]\n int i; // [rsp+20h] [rbp-30h]\n int v4; // [rsp+24h] [rbp-2Ch]\n int v5; // [rsp+28h] [rbp-28h]\n int j; // [rsp+2Ch] [rbp-24h]\n int v7; // [rsp+30h] [rbp-20h]\n _QWORD *v8; // [rsp+38h] [rbp-18h]\n\n v2 = 1;\n for ( i = 0; a1[i]; ++i )\n {\n if ( a1[i] == 32 )\n ++v2;\n }\n v8 = malloc(8LL * v2);\n v4 = 0;\n v5 = 0;\n for ( j = 0; a1[j]; ++j )\n {\n if ( a1[j] == 32 )\n {\n v8[v5] = malloc(j - v4 + 1);\n strncpy((char *)v8[v5], &a1[v4], j - v4);\n *(_BYTE *)(v8[v5++] + j - v4) = 0;\n v4 = j + 1;\n }\n }\n v7 = strlen(a1) - v4;\n v8[v5] = malloc(v7 + 1);\n strncpy((char *)v8[v5], &a1[v4], v7);\n *(_BYTE *)(v8[v5] + v7) = 0;\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11E9(const char *a1) {\n int v2;\n int i;\n int v4;\n int v5;\n int j;\n int v7;\n uint64_t *v8;\n v2 = 1;\n for (i = 0; a1[i]; ++i) {\n if (a1[i] == 32) ++v2;\n }\n v8 = malloc(8LL * v2);\n v4 = 0;\n v5 = 0;\n for (j = 0; a1[j]; ++j) {\n if (a1[j] == 32) {\n v8[v5] = malloc(j - v4 + 1);\n strncpy((char *)v8[v5], &a1[v4], j - v4);\n *(uint8_t *)(v8[v5++] + j - v4) = 0;\n v4 = j + 1;\n }\n }\n v7 = strlen(a1) - v4;\n v8[v5] = malloc(v7 + 1);\n strncpy((char *)v8[v5], &a1[v4], v7);\n *(uint8_t *)(v8[v5] + v7) = 0;\n return v8;\n}", + "ida_pseudo_norm": "uint64_t *func0(const char *a1) {\n int v2;\n int i;\n int v4;\n int v5;\n int j;\n int v7;\n uint64_t *v8;\n v2 = 1;\n for (i = 0; a1[i]; ++i) {\n if (a1[i] == 32) ++v2;\n }\n v8 = malloc(8LL * v2);\n v4 = 0;\n v5 = 0;\n for (j = 0; a1[j]; ++j) {\n if (a1[j] == 32) {\n v8[v5] = malloc(j - v4 + 1);\n strncpy((char *)v8[v5], &a1[v4], j - v4);\n *(uint8_t *)(v8[v5++] + j - v4) = 0;\n v4 = j + 1;\n }\n }\n v7 = strlen(a1) - v4;\n v8[v5] = malloc(v7 + 1);\n strncpy((char *)v8[v5], &a1[v4], v7);\n *(uint8_t *)(v8[v5] + v7) = 0;\n return v8;\n}" + }, + { + "index": 708, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(const char* string) {\n int count = 1;\n for (int i = 0; string[i] != '\\0'; i++) {\n if (string[i] == ' ') count++;\n }\n char** list = malloc(count * sizeof(char*));\n int start = 0, idx = 0;\n for (int i = 0; string[i] != '\\0'; i++) {\n if (string[i] == ' ') {\n int len = i - start;\n list[idx] = malloc(len + 1);\n strncpy(list[idx], string + start, len);\n list[idx][len] = '\\0';\n idx++;\n start = i + 1;\n }\n }\n int len = strlen(string) - start;\n list[idx] = malloc(len + 1);\n strncpy(list[idx], string + start, len);\n list[idx][len] = '\\0';\n return list;\n}", + "test": "int main(){\n\n char** res1 = func0(\"python program\");\n\n assert(strcmp(res1[0], \"python\") == 0);\n\n assert(strcmp(res1[1], \"program\") == 0);\n\n \n\n char** res2 = func0(\"Data Analysis\");\n\n assert(strcmp(res2[0], \"Data\") == 0);\n\n assert(strcmp(res2[1], \"Analysis\") == 0);\n\n \n\n char** res3 = func0(\"Hadoop Training\");\n\n assert(strcmp(res3[0], \"Hadoop\") == 0);\n\n assert(strcmp(res3[1], \"Training\") == 0);\n\n \n\n // Free allocated memory\n\n for(int i = 0; i < 2; i++) {\n\n free(res1[i]);\n\n free(res2[i]);\n\n free(res3[i]);\n\n }\n\n free(res1);\n\n free(res2);\n\n free(res3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov %rdi,%r12\nmovzbl (%rdi),%r13d\ntest %r13b,%r13b\nje 1267 \nlea 0x1(%rdi),%rdx\nmov %r13d,%eax\nmov $0x1,%edi\ncmp $0x20,%al\nsete %al\nmovzbl %al,%eax\nadd %eax,%edi\nadd $0x1,%rdx\nmovzbl -0x1(%rdx),%eax\ntest %al,%al\njne 11d7 \nmovslq %edi,%rdi\nshl $0x3,%rdi\ncallq 10b0 \nmov %rax,0x8(%rsp)\nmov $0x0,%ebx\nmov $0x0,%r15d\nmov $0x0,%ebp\njmp 125f \nmov %ebx,%r13d\nsub %ebp,%r13d\nlea 0x1(%r13),%edi\nmovslq %edi,%rdi\ncallq 10b0 \nmov %rax,%r14\nmovslq %r15d,%rax\nmov 0x8(%rsp),%rcx\nmov %r14,(%rcx,%rax,8)\nmovslq %r13d,%r13\nmovslq %ebp,%rsi\nadd %r12,%rsi\nmov %r13,%rdx\nmov %r14,%rdi\ncallq 1090 \nmovb $0x0,(%r14,%r13,1)\nadd $0x1,%r15d\nlea 0x1(%rbx),%ebp\nadd $0x1,%rbx\nmovzbl (%r12,%rbx,1),%r13d\ntest %r13b,%r13b\nje 1281 \ncmp $0x20,%r13b\njne 1251 \njmp 1210 \nmov $0x8,%edi\ncallq 10b0 \nmov %rax,0x8(%rsp)\nmov $0x0,%r15d\nmov $0x0,%ebp\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nmov %r12,%rdi\nrepnz scas %es:(%rdi),%al\nnot %rcx\nlea -0x1(%rcx),%rbx\nsub %ebp,%ebx\nlea 0x1(%rbx),%edi\nmovslq %edi,%rdi\ncallq 10b0 \nmov %rax,%r13\nmovslq %r15d,%r15\nmov 0x8(%rsp),%rax\nmov %r13,(%rax,%r15,8)\nmovslq %ebx,%rbx\nmovslq %ebp,%rsi\nadd %r12,%rsi\nmov %rbx,%rdx\nmov %r13,%rdi\ncallq 1090 \nmovb $0x0,0x0(%r13,%rbx,1)\nmov 0x8(%rsp),%rax\nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov r12, rdi\nmovzx r13d, byte ptr [rdi]\ntest r13b, r13b\njz loc_12B2\nlea rdx, [rdi+1]\nmov eax, r13d\nmov edi, 1\nloc_1217:\ncmp al, 20h ; ' '\nsetz al\nmovzx eax, al\nadd edi, eax\nadd rdx, 1\nmovzx eax, byte ptr [rdx-1]\ntest al, al\njnz short loc_1217\nmovsxd rdi, edi\nshl rdi, 3; size\ncall _malloc\nmov [rsp+48h+var_48], rax\nmov ebx, 1\nmov r15d, 0\nmov ebp, 0\njmp short loc_125E\nloc_124F:\nadd rbx, 1\nmovzx r13d, byte ptr [r12+rbx-1]\ntest r13b, r13b\njz short loc_12CB\nloc_125E:\ncmp r13b, 20h ; ' '\njnz short loc_124F\nlea r13d, [rbx-1]\nsub r13d, ebp\nlea eax, [r13+1]\ncdqe\nmov [rsp+48h+var_40], rax\nmov rdi, rax; size\ncall _malloc\nmov r14, rax\nmovsxd rax, r15d\nmov rsi, [rsp+48h+var_48]\nmov [rsi+rax*8], r14\nmovsxd r13, r13d\nmovsxd rsi, ebp\nadd rsi, r12\nmov rcx, [rsp+48h+var_40]\nmov rdx, r13\nmov rdi, r14\ncall ___strncpy_chk\nmov byte ptr [r14+r13], 0\nadd r15d, 1\nmov ebp, ebx\njmp short loc_124F\nloc_12B2:\nmov edi, 8; size\ncall _malloc\nmov [rsp+48h+var_48], rax\nmov r15d, 0\nmov ebp, 0\nloc_12CB:\nmov rdi, r12; s\ncall _strlen\nmov ebx, eax\nsub ebx, ebp\nlea eax, [rbx+1]\nmovsxd r14, eax\nmov rdi, r14; size\ncall _malloc\nmov r13, rax\nmovsxd r15, r15d\nmov rax, [rsp+48h+var_48]\nmov [rax+r15*8], r13\nmovsxd rbx, ebx\nmovsxd rsi, ebp\nadd rsi, r12\nmov rcx, r14\nmov rdx, rbx\nmov rdi, r13\ncall ___strncpy_chk\nmov byte ptr [r13+rbx+0], 0\nmov rax, [rsp+48h+var_48]\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(char *s)\n{\n char v2; // r13\n char *v3; // rdx\n char v4; // al\n int v5; // edi\n __int64 v6; // rbx\n int v7; // r15d\n int v8; // ebp\n _BYTE *v9; // r14\n int v10; // r13d\n int v11; // ebx\n _BYTE *v12; // r13\n _QWORD *v14; // [rsp+0h] [rbp-48h]\n\n v2 = *s;\n if ( *s )\n {\n v3 = s + 1;\n v4 = *s;\n v5 = 1;\n do\n {\n v5 += v4 == 32;\n v4 = *v3++;\n }\n while ( v4 );\n v14 = malloc(8LL * v5);\n v6 = 1LL;\n v7 = 0;\n v8 = 0;\n do\n {\n if ( v2 == 32 )\n {\n v9 = malloc((int)v6 - v8);\n v14[v7] = v9;\n v10 = v6 - 1 - v8;\n __strncpy_chk(v9, &s[v8], v10, (int)v6 - v8);\n v9[v10] = 0;\n ++v7;\n v8 = v6;\n }\n v2 = s[v6++];\n }\n while ( v2 );\n }\n else\n {\n v14 = malloc(8uLL);\n v7 = 0;\n v8 = 0;\n }\n v11 = strlen(s) - v8;\n v12 = malloc(v11 + 1);\n v14[v7] = v12;\n __strncpy_chk(v12, &s[v8], v11, v11 + 1);\n v12[v11] = 0;\n return v14;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov r12, rdi\nmovzx r13d, byte ptr [rdi]\ntest r13b, r13b\njz loc_12B2\nlea rdx, [rdi+1]\nmov eax, r13d\nmov edi, 1\nloc_1217:\ncmp al, 20h ; ' '\nsetz al\nmovzx eax, al\nadd edi, eax\nadd rdx, 1\nmovzx eax, byte ptr [rdx-1]\ntest al, al\njnz short loc_1217\nmovsxd rdi, edi\nshl rdi, 3; size\ncall _malloc\nmov [rsp+48h+var_48], rax\nmov ebx, 1\nmov r15d, 0\nmov ebp, 0\njmp short loc_125E\nloc_124F:\nadd rbx, 1\nmovzx r13d, byte ptr [r12+rbx-1]\ntest r13b, r13b\njz short loc_12CB\nloc_125E:\ncmp r13b, 20h ; ' '\njnz short loc_124F\nlea r13d, [rbx-1]\nsub r13d, ebp\nlea eax, [r13+1]\ncdqe\nmov [rsp+48h+var_40], rax\nmov rdi, rax; size\ncall _malloc\nmov r14, rax\nmovsxd rax, r15d\nmov rsi, [rsp+48h+var_48]\nmov [rsi+rax*8], r14\nmovsxd r13, r13d\nmovsxd rsi, ebp\nadd rsi, r12\nmov rcx, [rsp+48h+var_40]\nmov rdx, r13\nmov rdi, r14\ncall ___strncpy_chk\nmov byte ptr [r14+r13], 0\nadd r15d, 1\nmov ebp, ebx\njmp short loc_124F\nloc_12B2:\nmov edi, 8; size\ncall _malloc\nmov [rsp+48h+var_48], rax\nmov r15d, 0\nmov ebp, 0\nloc_12CB:\nmov rdi, r12; s\ncall _strlen\nmov ebx, eax\nsub ebx, ebp\nlea eax, [rbx+1]\nmovsxd r14, eax\nmov rdi, r14; size\ncall _malloc\nmov r13, rax\nmovsxd r15, r15d\nmov rax, [rsp+48h+var_48]\nmov [rax+r15*8], r13\nmovsxd rbx, ebx\nmovsxd rsi, ebp\nadd rsi, r12\nmov rcx, r14\nmov rdx, rbx\nmov rdi, r13\ncall ___strncpy_chk\nmov byte ptr [r13+rbx+0], 0\nmov rax, [rsp+48h+var_48]\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11E9(char *s)\n{\n char v2; // r13\n char *v3; // rdx\n char v4; // al\n int v5; // edi\n __int64 v6; // rbx\n int v7; // r15d\n int v8; // ebp\n _BYTE *v9; // r14\n int v10; // r13d\n int v11; // ebx\n _BYTE *v12; // r13\n _QWORD *v14; // [rsp+0h] [rbp-48h]\n\n v2 = *s;\n if ( *s )\n {\n v3 = s + 1;\n v4 = *s;\n v5 = 1;\n do\n {\n v5 += v4 == 32;\n v4 = *v3++;\n }\n while ( v4 );\n v14 = malloc(8LL * v5);\n v6 = 1LL;\n v7 = 0;\n v8 = 0;\n do\n {\n if ( v2 == 32 )\n {\n v9 = malloc((int)v6 - v8);\n v14[v7] = v9;\n v10 = v6 - 1 - v8;\n __strncpy_chk(v9, &s[v8], v10, (int)v6 - v8);\n v9[v10] = 0;\n ++v7;\n v8 = v6;\n }\n v2 = s[v6++];\n }\n while ( v2 );\n }\n else\n {\n v14 = malloc(8uLL);\n v7 = 0;\n v8 = 0;\n }\n v11 = strlen(s) - v8;\n v12 = malloc(v11 + 1);\n v14[v7] = v12;\n __strncpy_chk(v12, &s[v8], v11, v11 + 1);\n v12[v11] = 0;\n return v14;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11E9(char *s) {\n char v2;\n char *v3;\n char v4;\n int v5;\n long long v6;\n int v7;\n int v8;\n uint8_t *v9;\n int v10;\n int v11;\n uint8_t *v12;\n uint64_t *v14;\n v2 = *s;\n if (*s) {\n v3 = s + 1;\n v4 = *s;\n v5 = 1;\n do {\n v5 += v4 == 32;\n v4 = *v3++;\n } while (v4);\n v14 = malloc(8LL * v5);\n v6 = 1LL;\n v7 = 0;\n v8 = 0;\n do {\n if (v2 == 32) {\n v9 = malloc((int)v6 - v8);\n v14[v7] = v9;\n v10 = v6 - 1 - v8;\n __strncpy_chk(v9, &s[v8], v10, (int)v6 - v8);\n v9[v10] = 0;\n ++v7;\n v8 = v6;\n }\n v2 = s[v6++];\n } while (v2);\n } else {\n v14 = malloc(8uLL);\n v7 = 0;\n v8 = 0;\n }\n v11 = strlen(s) - v8;\n v12 = malloc(v11 + 1);\n v14[v7] = v12;\n __strncpy_chk(v12, &s[v8], v11, v11 + 1);\n v12[v11] = 0;\n return v14;\n}", + "ida_pseudo_norm": "uint64_t *func0(char *s) {\n char v2;\n char *v3;\n char v4;\n int v5;\n long long v6;\n int v7;\n int v8;\n uint8_t *v9;\n int v10;\n int v11;\n uint8_t *v12;\n uint64_t *v14;\n v2 = *s;\n if (*s) {\n v3 = s + 1;\n v4 = *s;\n v5 = 1;\n do {\n v5 += v4 == 32;\n v4 = *v3++;\n } while (v4);\n v14 = malloc(8LL * v5);\n v6 = 1LL;\n v7 = 0;\n v8 = 0;\n do {\n if (v2 == 32) {\n v9 = malloc((int)v6 - v8);\n v14[v7] = v9;\n v10 = v6 - 1 - v8;\n __strncpy_chk(v9, &s[v8], v10, (int)v6 - v8);\n v9[v10] = 0;\n ++v7;\n v8 = v6;\n }\n v2 = s[v6++];\n } while (v2);\n } else {\n v14 = malloc(8uLL);\n v7 = 0;\n v8 = 0;\n }\n v11 = strlen(s) - v8;\n v12 = malloc(v11 + 1);\n v14[v7] = v12;\n __strncpy_chk(v12, &s[v8], v11, v11 + 1);\n v12[v11] = 0;\n return v14;\n}" + }, + { + "index": 708, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(const char* string) {\n int count = 1;\n for (int i = 0; string[i] != '\\0'; i++) {\n if (string[i] == ' ') count++;\n }\n char** list = malloc(count * sizeof(char*));\n int start = 0, idx = 0;\n for (int i = 0; string[i] != '\\0'; i++) {\n if (string[i] == ' ') {\n int len = i - start;\n list[idx] = malloc(len + 1);\n strncpy(list[idx], string + start, len);\n list[idx][len] = '\\0';\n idx++;\n start = i + 1;\n }\n }\n int len = strlen(string) - start;\n list[idx] = malloc(len + 1);\n strncpy(list[idx], string + start, len);\n list[idx][len] = '\\0';\n return list;\n}", + "test": "int main(){\n\n char** res1 = func0(\"python program\");\n\n assert(strcmp(res1[0], \"python\") == 0);\n\n assert(strcmp(res1[1], \"program\") == 0);\n\n \n\n char** res2 = func0(\"Data Analysis\");\n\n assert(strcmp(res2[0], \"Data\") == 0);\n\n assert(strcmp(res2[1], \"Analysis\") == 0);\n\n \n\n char** res3 = func0(\"Hadoop Training\");\n\n assert(strcmp(res3[0], \"Hadoop\") == 0);\n\n assert(strcmp(res3[1], \"Training\") == 0);\n\n \n\n // Free allocated memory\n\n for(int i = 0; i < 2; i++) {\n\n free(res1[i]);\n\n free(res2[i]);\n\n free(res3[i]);\n\n }\n\n free(res1);\n\n free(res2);\n\n free(res3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\nmov %rdi,%r12\npush %rbp\npush %rbx\nsub $0x28,%rsp\nmovzbl (%rdi),%r13d\ntest %r13b,%r13b\nje 1510 \nlea 0x1(%rdi),%rdx\nmov %r13d,%eax\nmov $0x1,%edi\nxchg %ax,%ax\ncmp $0x20,%al\nsete %al\nadd $0x1,%rdx\nmovzbl %al,%eax\nadd %eax,%edi\nmovzbl -0x1(%rdx),%eax\ntest %al,%al\njne 1400 \nmovslq %edi,%rdi\nmov $0x1,%ebx\nshl $0x3,%rdi\ncallq 10d0 \nxor %ecx,%ecx\nxor %edx,%edx\nmov %rax,%r15\njmp 143f \nadd $0x1,%rbx\nmovzbl -0x1(%r12,%rbx,1),%r13d\ntest %r13b,%r13b\nje 14bd \nmovslq %ecx,%rbp\nlea -0x1(%rbx),%eax\nlea (%r12,%rbx,1),%r8\nmovslq %edx,%rsi\nshl $0x3,%rbp\nlea (%r12,%rsi,1),%r14\nlea (%r15,%rbp,1),%r9\ncmp $0x20,%r13b\njne 1430 \nsub %edx,%eax\nmov %r8,0x10(%rsp)\nmovslq %eax,%r13\nmov %ecx,0x8(%rsp)\nlea 0x1(%r13),%edi\nmov %r9,0x18(%rsp)\nmovslq %edi,%rdi\ncallq 10d0 \nmov 0x18(%rsp),%r9\nmov %r13,%rdx\nmov %r14,%rsi\nmov %rax,%rdi\nmov %rax,(%r9)\ncallq 10a0 \nmov %ebx,%edx\nadd $0x1,%rbx\nmov 0x8(%rsp),%ecx\nmovb $0x0,(%rax,%r13,1)\nmov 0x10(%rsp),%r8\nlea 0x8(%r15,%rbp,1),%r9\nmovzbl -0x1(%r12,%rbx,1),%r13d\nadd $0x1,%ecx\nmov %r8,%r14\ntest %r13b,%r13b\njne 143f \nmov %edx,%ebx\nmov %r12,%rdi\nmov %r9,0x8(%rsp)\ncallq 10b0 \nsub %ebx,%eax\nmovslq %eax,%rbx\nlea 0x1(%rbx),%edi\nmovslq %edi,%rdi\ncallq 10d0 \nmov 0x8(%rsp),%r9\nmov %rbx,%rdx\nmov %r14,%rsi\nmov %rax,%rdi\nmov %rax,(%r9)\ncallq 10a0 \nmovb $0x0,(%rax,%rbx,1)\nadd $0x28,%rsp\nmov %r15,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax,%rax,1)\nmov $0x8,%edi\nmov %r12,%r14\nxor %ebx,%ebx\ncallq 10d0 \nmov %rax,%r15\nmov %rax,%r9\njmp 14bf \nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 18h\nmovzx ebp, byte ptr [rdi]\ntest bpl, bpl\njz loc_14F0\nlea rdx, [rdi+1]\nmov eax, ebp\nmov edi, 1\nnop dword ptr [rax+00h]\nloc_13F0:\ncmp al, 20h ; ' '\nsetz al\nadd rdx, 1\nmovzx eax, al\nadd edi, eax\nmovzx eax, byte ptr [rdx-1]\ntest al, al\njnz short loc_13F0\nmovsxd rdi, edi\nmov ebx, 1\nxor r14d, r14d\nxor r13d, r13d\nshl rdi, 3; size\ncall _malloc\nmov r15, rax\njmp short loc_1437\nloc_1428:\nadd rbx, 1\nmovzx ebp, byte ptr [r12+rbx-1]\ntest bpl, bpl\njz short loc_1490\nloc_1437:\ncmp bpl, 20h ; ' '\njnz short loc_1428\nlea ebp, [rbx-1]\nsub ebp, r13d\nlea ecx, [rbp+1]\nmovsxd rbp, ebp\nmovsxd rcx, ecx\nmov rdi, rcx; size\nmov [rsp+48h+var_40], rcx\ncall _malloc\nmovsxd rsi, r13d\nmov rcx, [rsp+48h+var_40]\nmov rdx, rbp\nmov rdi, rax\nmovsxd rax, r14d\nadd rsi, r12\nmov r13d, ebx\nmov [r15+rax*8], rdi\nadd rbx, 1\nadd r14d, 1\ncall ___strncpy_chk\nmov byte ptr [rax+rbp], 0\nmovzx ebp, byte ptr [r12+rbx-1]\ntest bpl, bpl\njnz short loc_1437\nloc_1490:\nmovsxd r14, r14d\nmovsxd rbp, r13d\nlea r14, [r15+r14*8]\nadd rbp, r12\nloc_149D:\nmov rdi, r12; s\ncall _strlen\nmov ebx, eax\nsub ebx, r13d\nlea r12d, [rbx+1]\nmovsxd rbx, ebx\nmovsxd r12, r12d\nmov rdi, r12; size\ncall _malloc\nmov rcx, r12\nmov rdx, rbx\nmov rsi, rbp\nmov [r14], rax\nmov rdi, rax\ncall ___strncpy_chk\nmov byte ptr [rax+rbx], 0\nadd rsp, 18h\nmov rax, r15\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14F0:\nmov edi, 8; size\nmov rbp, r12\nxor r13d, r13d\ncall _malloc\nmov r15, rax\nmov r14, rax\njmp short loc_149D", + "ida_pseudo": "_QWORD *__fastcall func0(char *s)\n{\n char v2; // bp\n char *v3; // rdx\n char v4; // al\n int v5; // edi\n __int64 v6; // rbx\n int v7; // r14d\n int v8; // r13d\n _QWORD *v9; // r15\n __int64 v10; // rbp\n void *v11; // rax\n char *v12; // rsi\n _QWORD *v13; // r14\n char *v14; // rbp\n int v15; // eax\n __int64 v16; // rbx\n size_t v17; // r12\n void *v18; // rax\n size_t v20; // [rsp+8h] [rbp-40h]\n\n v2 = *s;\n if ( *s )\n {\n v3 = s + 1;\n v4 = *s;\n v5 = 1;\n do\n {\n ++v3;\n v5 += v4 == 32;\n v4 = *(v3 - 1);\n }\n while ( v4 );\n v6 = 1LL;\n v7 = 0;\n v8 = 0;\n v9 = malloc(8LL * v5);\n do\n {\n while ( v2 != 32 )\n {\n v2 = s[v6++];\n if ( !v2 )\n goto LABEL_8;\n }\n v10 = (int)v6 - 1 - v8;\n v20 = (int)v6 - v8;\n v11 = malloc(v20);\n v12 = &s[v8];\n v8 = v6;\n v9[v7] = v11;\n ++v6;\n ++v7;\n *(_BYTE *)(__strncpy_chk(v11, v12, v10, v20) + v10) = 0;\n v2 = s[v6 - 1];\n }\n while ( v2 );\nLABEL_8:\n v13 = &v9[v7];\n v14 = &s[v8];\n }\n else\n {\n v14 = s;\n v8 = 0;\n v9 = malloc(8uLL);\n v13 = v9;\n }\n v15 = strlen(s);\n v16 = v15 - v8;\n v17 = v15 - v8 + 1;\n v18 = malloc(v17);\n *v13 = v18;\n *(_BYTE *)(__strncpy_chk(v18, v14, v16, v17) + v16) = 0;\n return v9;\n}", + "ida_strip_asm": "sub_13C0:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 18h\nmovzx ebp, byte ptr [rdi]\ntest bpl, bpl\njz loc_14F0\nlea rdx, [rdi+1]\nmov eax, ebp\nmov edi, 1\nnop dword ptr [rax+00h]\nloc_13F0:\ncmp al, 20h ; ' '\nsetz al\nadd rdx, 1\nmovzx eax, al\nadd edi, eax\nmovzx eax, byte ptr [rdx-1]\ntest al, al\njnz short loc_13F0\nmovsxd rdi, edi\nmov ebx, 1\nxor r14d, r14d\nxor r13d, r13d\nshl rdi, 3; size\ncall _malloc\nmov r15, rax\njmp short loc_1437\nloc_1428:\nadd rbx, 1\nmovzx ebp, byte ptr [r12+rbx-1]\ntest bpl, bpl\njz short loc_1490\nloc_1437:\ncmp bpl, 20h ; ' '\njnz short loc_1428\nlea ebp, [rbx-1]\nsub ebp, r13d\nlea ecx, [rbp+1]\nmovsxd rbp, ebp\nmovsxd rcx, ecx\nmov rdi, rcx; size\nmov [rsp+48h+var_40], rcx\ncall _malloc\nmovsxd rsi, r13d\nmov rcx, [rsp+48h+var_40]\nmov rdx, rbp\nmov rdi, rax\nmovsxd rax, r14d\nadd rsi, r12\nmov r13d, ebx\nmov [r15+rax*8], rdi\nadd rbx, 1\nadd r14d, 1\ncall ___strncpy_chk\nmov byte ptr [rax+rbp], 0\nmovzx ebp, byte ptr [r12+rbx-1]\ntest bpl, bpl\njnz short loc_1437\nloc_1490:\nmovsxd r14, r14d\nmovsxd rbp, r13d\nlea r14, [r15+r14*8]\nadd rbp, r12\nloc_149D:\nmov rdi, r12; s\ncall _strlen\nmov ebx, eax\nsub ebx, r13d\nlea r12d, [rbx+1]\nmovsxd rbx, ebx\nmovsxd r12, r12d\nmov rdi, r12; size\ncall _malloc\nmov rcx, r12\nmov rdx, rbx\nmov rsi, rbp\nmov [r14], rax\nmov rdi, rax\ncall ___strncpy_chk\nmov byte ptr [rax+rbx], 0\nadd rsp, 18h\nmov rax, r15\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14F0:\nmov edi, 8; size\nmov rbp, r12\nxor r13d, r13d\ncall _malloc\nmov r15, rax\nmov r14, rax\njmp short loc_149D", + "ida_strip_pseudo": "_QWORD *__fastcall sub_13C0(char *s)\n{\n char v2; // bp\n char *v3; // rdx\n char v4; // al\n int v5; // edi\n __int64 v6; // rbx\n int v7; // r14d\n int v8; // r13d\n _QWORD *v9; // r15\n __int64 v10; // rbp\n void *v11; // rax\n char *v12; // rsi\n _QWORD *v13; // r14\n char *v14; // rbp\n int v15; // eax\n __int64 v16; // rbx\n size_t v17; // r12\n void *v18; // rax\n size_t v20; // [rsp+8h] [rbp-40h]\n\n v2 = *s;\n if ( *s )\n {\n v3 = s + 1;\n v4 = *s;\n v5 = 1;\n do\n {\n ++v3;\n v5 += v4 == 32;\n v4 = *(v3 - 1);\n }\n while ( v4 );\n v6 = 1LL;\n v7 = 0;\n v8 = 0;\n v9 = malloc(8LL * v5);\n do\n {\n while ( v2 != 32 )\n {\n v2 = s[v6++];\n if ( !v2 )\n goto LABEL_8;\n }\n v10 = (int)v6 - 1 - v8;\n v20 = (int)v6 - v8;\n v11 = malloc(v20);\n v12 = &s[v8];\n v8 = v6;\n v9[v7] = v11;\n ++v6;\n ++v7;\n *(_BYTE *)(__strncpy_chk(v11, v12, v10, v20) + v10) = 0;\n v2 = s[v6 - 1];\n }\n while ( v2 );\nLABEL_8:\n v13 = &v9[v7];\n v14 = &s[v8];\n }\n else\n {\n v14 = s;\n v8 = 0;\n v9 = malloc(8uLL);\n v13 = v9;\n }\n v15 = strlen(s);\n v16 = v15 - v8;\n v17 = v15 - v8 + 1;\n v18 = malloc(v17);\n *v13 = v18;\n *(_BYTE *)(__strncpy_chk(v18, v14, v16, v17) + v16) = 0;\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_13C0(char *s) {\n char v2;\n char *v3;\n char v4;\n int v5;\n long long v6;\n int v7;\n int v8;\n uint64_t *v9;\n long long v10;\n void *v11;\n char *v12;\n uint64_t *v13;\n char *v14;\n int v15;\n long long v16;\n unsigned int v17;\n void *v18;\n unsigned int v20;\n v2 = *s;\n if (*s) {\n v3 = s + 1;\n v4 = *s;\n v5 = 1;\n do {\n ++v3;\n v5 += v4 == 32;\n v4 = *(v3 - 1);\n } while (v4);\n v6 = 1LL;\n v7 = 0;\n v8 = 0;\n v9 = malloc(8LL * v5);\n do {\n while (v2 != 32) {\n v2 = s[v6++];\n if (!v2) goto LABEL_8;\n }\n v10 = (int)v6 - 1 - v8;\n v20 = (int)v6 - v8;\n v11 = malloc(v20);\n v12 = &s[v8];\n v8 = v6;\n v9[v7] = v11;\n ++v6;\n ++v7;\n *(uint8_t *)(__strncpy_chk(v11, v12, v10, v20) + v10) = 0;\n v2 = s[v6 - 1];\n } while (v2);\n LABEL_8:\n v13 = &v9[v7];\n v14 = &s[v8];\n } else {\n v14 = s;\n v8 = 0;\n v9 = malloc(8uLL);\n v13 = v9;\n }\n v15 = strlen(s);\n v16 = v15 - v8;\n v17 = v15 - v8 + 1;\n v18 = malloc(v17);\n *v13 = v18;\n *(uint8_t *)(__strncpy_chk(v18, v14, v16, v17) + v16) = 0;\n return v9;\n}", + "ida_pseudo_norm": "uint64_t *func0(char *s) {\n char v2;\n char *v3;\n char v4;\n int v5;\n long long v6;\n int v7;\n int v8;\n uint64_t *v9;\n long long v10;\n void *v11;\n char *v12;\n uint64_t *v13;\n char *v14;\n int v15;\n long long v16;\n unsigned int v17;\n void *v18;\n unsigned int v20;\n v2 = *s;\n if (*s) {\n v3 = s + 1;\n v4 = *s;\n v5 = 1;\n do {\n ++v3;\n v5 += v4 == 32;\n v4 = *(v3 - 1);\n } while (v4);\n v6 = 1LL;\n v7 = 0;\n v8 = 0;\n v9 = malloc(8LL * v5);\n do {\n while (v2 != 32) {\n v2 = s[v6++];\n if (!v2) goto LABEL_8;\n }\n v10 = (int)v6 - 1 - v8;\n v20 = (int)v6 - v8;\n v11 = malloc(v20);\n v12 = &s[v8];\n v8 = v6;\n v9[v7] = v11;\n ++v6;\n ++v7;\n *(uint8_t *)(__strncpy_chk(v11, v12, v10, v20) + v10) = 0;\n v2 = s[v6 - 1];\n } while (v2);\n LABEL_8:\n v13 = &v9[v7];\n v14 = &s[v8];\n } else {\n v14 = s;\n v8 = 0;\n v9 = malloc(8uLL);\n v13 = v9;\n }\n v15 = strlen(s);\n v16 = v15 - v8;\n v17 = v15 - v8 + 1;\n v18 = malloc(v17);\n *v13 = v18;\n *(uint8_t *)(__strncpy_chk(v18, v14, v16, v17) + v16) = 0;\n return v9;\n}" + }, + { + "index": 708, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(const char* string) {\n int count = 1;\n for (int i = 0; string[i] != '\\0'; i++) {\n if (string[i] == ' ') count++;\n }\n char** list = malloc(count * sizeof(char*));\n int start = 0, idx = 0;\n for (int i = 0; string[i] != '\\0'; i++) {\n if (string[i] == ' ') {\n int len = i - start;\n list[idx] = malloc(len + 1);\n strncpy(list[idx], string + start, len);\n list[idx][len] = '\\0';\n idx++;\n start = i + 1;\n }\n }\n int len = strlen(string) - start;\n list[idx] = malloc(len + 1);\n strncpy(list[idx], string + start, len);\n list[idx][len] = '\\0';\n return list;\n}", + "test": "int main(){\n\n char** res1 = func0(\"python program\");\n\n assert(strcmp(res1[0], \"python\") == 0);\n\n assert(strcmp(res1[1], \"program\") == 0);\n\n \n\n char** res2 = func0(\"Data Analysis\");\n\n assert(strcmp(res2[0], \"Data\") == 0);\n\n assert(strcmp(res2[1], \"Analysis\") == 0);\n\n \n\n char** res3 = func0(\"Hadoop Training\");\n\n assert(strcmp(res3[0], \"Hadoop\") == 0);\n\n assert(strcmp(res3[1], \"Training\") == 0);\n\n \n\n // Free allocated memory\n\n for(int i = 0; i < 2; i++) {\n\n free(res1[i]);\n\n free(res2[i]);\n\n free(res3[i]);\n\n }\n\n free(res1);\n\n free(res2);\n\n free(res3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\nmov %rdi,%rbp\npush %rbx\nsub $0x28,%rsp\nmovzbl (%rdi),%r12d\ntest %r12b,%r12b\nje 1548 \nlea 0x1(%rdi),%rdx\nmov %r12d,%eax\nmov $0x1,%edi\nxchg %ax,%ax\ncmp $0x20,%al\nsete %al\nadd $0x1,%rdx\nmovzbl %al,%eax\nadd %eax,%edi\nmovzbl -0x1(%rdx),%eax\ntest %al,%al\njne 1400 \nmovslq %edi,%rdi\nmov $0x1,%ebx\nshl $0x3,%rdi\ncallq 10d0 \nxor %r8d,%r8d\nxor %r10d,%r10d\nxor %edx,%edx\nmov %rax,%r14\nxor %eax,%eax\nnopl 0x0(%rax)\nlea 0x0(,%rdx,8),%r13\nlea -0x1(%rbx),%edi\nmov %ebx,%r15d\nlea (%r14,%r13,1),%r9\nlea 0x0(%rbp,%rax,1),%rsi\nlea 0x0(%rbp,%rbx,1),%rcx\ncmp $0x20,%r12b\nje 14c0 \nadd $0x1,%rbx\nmovzbl -0x1(%rbp,%rbx,1),%r12d\ntest %r12b,%r12b\njne 1438 \nmov %r10d,%ebx\nmov %rbp,%rdi\nmov %r9,0x8(%rsp)\nmov %rsi,(%rsp)\ncallq 10b0 \nsub %ebx,%eax\nmovslq %eax,%rbx\nlea 0x1(%rbx),%edi\nmovslq %edi,%rdi\ncallq 10d0 \nmov 0x8(%rsp),%r9\nmov (%rsp),%rsi\nmov %rbx,%rdx\nmov %rax,%rdi\nmov %rax,(%r9)\ncallq 10a0 \nmovb $0x0,(%rax,%rbx,1)\nadd $0x28,%rsp\nmov %r14,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw 0x0(%rax,%rax,1)\nsub %r10d,%edi\nmov %r8d,0x8(%rsp)\nadd $0x1,%rbx\nmovslq %edi,%r12\nmov %rcx,(%rsp)\nlea 0x1(%r12),%edi\nmov %r9,0x18(%rsp)\nmovslq %edi,%rdi\nmov %rsi,0x10(%rsp)\ncallq 10d0 \nmov 0x18(%rsp),%r9\nmov 0x10(%rsp),%rsi\nmov %r12,%rdx\nmov %rax,%rdi\nmov %rax,(%r9)\ncallq 10a0 \nmov 0x8(%rsp),%r8d\nmov (%rsp),%rcx\nlea 0x8(%r14,%r13,1),%r9\nmovb $0x0,(%rax,%r12,1)\nmovzbl -0x1(%rbp,%rbx,1),%r12d\nadd $0x1,%r8d\ntest %r12b,%r12b\nje 1538 \nmovslq %r15d,%rax\nmovslq %r8d,%rdx\nmov %rax,%r10\njmpq 1438 \nnopw 0x0(%rax,%rax,1)\nmov %rcx,%rsi\nmov %r15d,%r10d\njmpq 1469 \nnopl 0x0(%rax,%rax,1)\nmov $0x8,%edi\nxor %ebx,%ebx\ncallq 10d0 \nmov %rbp,%rsi\nmov %rax,%r14\nmov %rax,%r9\njmpq 146c \nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 18h\nmovzx ebp, byte ptr [rdi]\ntest bpl, bpl\njz loc_14F8\nlea rdx, [rdi+1]\nmov eax, ebp\nmov edi, 1\nnop dword ptr [rax+00h]\nloc_13F0:\ncmp al, 20h ; ' '\nsetz al\nadd rdx, 1\nmovzx eax, al\nadd edi, eax\nmovzx eax, byte ptr [rdx-1]\ntest al, al\njnz short loc_13F0\nmovsxd rdi, edi\nmov ebx, 1\nxor r13d, r13d\nxor r15d, r15d\nshl rdi, 3; size\ncall _malloc\nmov r14, rax\nloc_1420:\ncmp bpl, 20h ; ' '\njz short loc_1490\nadd rbx, 1\nmovzx ebp, byte ptr [r12+rbx-1]\ntest bpl, bpl\njnz short loc_1420\nloc_1435:\nmov ebx, r15d\nmovsxd r13, r13d\nlea r15, [r14+r13*8]\nmovsxd r13, ebx\nadd r13, r12\nloc_1445:\nmov rdi, r12; s\ncall _strlen\nmov ebp, eax\nsub ebp, ebx\nlea r12d, [rbp+1]\nmovsxd rbp, ebp\nmovsxd r12, r12d\nmov rdi, r12; size\ncall _malloc\nmov rcx, r12\nmov rdx, rbp\nmov rsi, r13\nmov [r15], rax\nmov rdi, rax\ncall ___strncpy_chk\nmov byte ptr [rax+rbp], 0\nadd rsp, 18h\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1490:\nlea ebp, [rbx-1]\nmov [rsp+48h+var_3C], ebx\nadd rbx, 1\nsub ebp, r15d\nlea ecx, [rbp+1]\nmovsxd rbp, ebp\nmovsxd rcx, ecx\nmov rdi, rcx; size\nmov [rsp+48h+var_48], rcx\ncall _malloc\nmovsxd rdx, r15d\nmov rcx, [rsp+48h+var_48]\nmov rdi, rax\nmovsxd rax, r13d\nlea rsi, [r12+rdx]\nmov rdx, rbp\nmov [r14+rax*8], rdi\nadd r13d, 1\ncall ___strncpy_chk\nmov r15d, [rsp+48h+var_3C]\nmov byte ptr [rax+rbp], 0\nmovzx ebp, byte ptr [r12+rbx-1]\ntest bpl, bpl\njnz loc_1420\njmp loc_1435\nloc_14F8:\nmov edi, 8; size\nmov r13, r12\nxor ebx, ebx\ncall _malloc\nmov r14, rax\nmov r15, rax\njmp loc_1445", + "ida_pseudo": "_QWORD *__fastcall func0(char *s)\n{\n char v2; // bp\n char *v3; // rdx\n char v4; // al\n int v5; // edi\n __int64 v6; // rbx\n int v7; // r13d\n int v8; // r15d\n _QWORD *v9; // r14\n int v10; // ebx\n _QWORD *v11; // r15\n char *v12; // r13\n int v13; // eax\n __int64 v14; // rbp\n size_t v15; // r12\n void *v16; // rax\n int v18; // ebp\n int v19; // ebp\n void *v20; // rax\n __int64 v21; // rax\n int v22; // [rsp+Ch] [rbp-3Ch]\n\n v2 = *s;\n if ( *s )\n {\n v3 = s + 1;\n v4 = *s;\n v5 = 1;\n do\n {\n ++v3;\n v5 += v4 == 32;\n v4 = *(v3 - 1);\n }\n while ( v4 );\n v6 = 1LL;\n v7 = 0;\n v8 = 0;\n v9 = malloc(8LL * v5);\n do\n {\n while ( v2 != 32 )\n {\n v2 = s[v6++];\n if ( !v2 )\n goto LABEL_7;\n }\n v18 = v6 - 1;\n v22 = v6++;\n v19 = v18 - v8;\n v20 = malloc(v19 + 1);\n v9[v7++] = v20;\n v21 = __strncpy_chk(v20, &s[v8], v19, v19 + 1);\n v8 = v22;\n *(_BYTE *)(v21 + v19) = 0;\n v2 = s[v6 - 1];\n }\n while ( v2 );\nLABEL_7:\n v10 = v8;\n v11 = &v9[v7];\n v12 = &s[v10];\n }\n else\n {\n v12 = s;\n v10 = 0;\n v9 = malloc(8uLL);\n v11 = v9;\n }\n v13 = strlen(s);\n v14 = v13 - v10;\n v15 = v13 - v10 + 1;\n v16 = malloc(v15);\n *v11 = v16;\n *(_BYTE *)(__strncpy_chk(v16, v12, v14, v15) + v14) = 0;\n return v9;\n}", + "ida_strip_asm": "sub_13C0:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 18h\nmovzx ebp, byte ptr [rdi]\ntest bpl, bpl\njz loc_14F8\nlea rdx, [rdi+1]\nmov eax, ebp\nmov edi, 1\nnop dword ptr [rax+00h]\nloc_13F0:\ncmp al, 20h ; ' '\nsetz al\nadd rdx, 1\nmovzx eax, al\nadd edi, eax\nmovzx eax, byte ptr [rdx-1]\ntest al, al\njnz short loc_13F0\nmovsxd rdi, edi\nmov ebx, 1\nxor r13d, r13d\nxor r15d, r15d\nshl rdi, 3; size\ncall _malloc\nmov r14, rax\nloc_1420:\ncmp bpl, 20h ; ' '\njz short loc_1490\nadd rbx, 1\nmovzx ebp, byte ptr [r12+rbx-1]\ntest bpl, bpl\njnz short loc_1420\nloc_1435:\nmov ebx, r15d\nmovsxd r13, r13d\nlea r15, [r14+r13*8]\nmovsxd r13, ebx\nadd r13, r12\nloc_1445:\nmov rdi, r12; s\ncall _strlen\nmov ebp, eax\nsub ebp, ebx\nlea r12d, [rbp+1]\nmovsxd rbp, ebp\nmovsxd r12, r12d\nmov rdi, r12; size\ncall _malloc\nmov rcx, r12\nmov rdx, rbp\nmov rsi, r13\nmov [r15], rax\nmov rdi, rax\ncall ___strncpy_chk\nmov byte ptr [rax+rbp], 0\nadd rsp, 18h\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1490:\nlea ebp, [rbx-1]\nmov [rsp+48h+var_3C], ebx\nadd rbx, 1\nsub ebp, r15d\nlea ecx, [rbp+1]\nmovsxd rbp, ebp\nmovsxd rcx, ecx\nmov rdi, rcx; size\nmov [rsp+48h+var_48], rcx\ncall _malloc\nmovsxd rdx, r15d\nmov rcx, [rsp+48h+var_48]\nmov rdi, rax\nmovsxd rax, r13d\nlea rsi, [r12+rdx]\nmov rdx, rbp\nmov [r14+rax*8], rdi\nadd r13d, 1\ncall ___strncpy_chk\nmov r15d, [rsp+48h+var_3C]\nmov byte ptr [rax+rbp], 0\nmovzx ebp, byte ptr [r12+rbx-1]\ntest bpl, bpl\njnz loc_1420\njmp loc_1435\nloc_14F8:\nmov edi, 8; size\nmov r13, r12\nxor ebx, ebx\ncall _malloc\nmov r14, rax\nmov r15, rax\njmp loc_1445", + "ida_strip_pseudo": "_QWORD *__fastcall sub_13C0(char *s)\n{\n char v2; // bp\n char *v3; // rdx\n char v4; // al\n int v5; // edi\n __int64 v6; // rbx\n int v7; // r13d\n int v8; // r15d\n _QWORD *v9; // r14\n int v10; // ebx\n _QWORD *v11; // r15\n char *v12; // r13\n int v13; // eax\n __int64 v14; // rbp\n size_t v15; // r12\n void *v16; // rax\n int v18; // ebp\n int v19; // ebp\n void *v20; // rax\n __int64 v21; // rax\n int v22; // [rsp+Ch] [rbp-3Ch]\n\n v2 = *s;\n if ( *s )\n {\n v3 = s + 1;\n v4 = *s;\n v5 = 1;\n do\n {\n ++v3;\n v5 += v4 == 32;\n v4 = *(v3 - 1);\n }\n while ( v4 );\n v6 = 1LL;\n v7 = 0;\n v8 = 0;\n v9 = malloc(8LL * v5);\n do\n {\n while ( v2 != 32 )\n {\n v2 = s[v6++];\n if ( !v2 )\n goto LABEL_7;\n }\n v18 = v6 - 1;\n v22 = v6++;\n v19 = v18 - v8;\n v20 = malloc(v19 + 1);\n v9[v7++] = v20;\n v21 = __strncpy_chk(v20, &s[v8], v19, v19 + 1);\n v8 = v22;\n *(_BYTE *)(v21 + v19) = 0;\n v2 = s[v6 - 1];\n }\n while ( v2 );\nLABEL_7:\n v10 = v8;\n v11 = &v9[v7];\n v12 = &s[v10];\n }\n else\n {\n v12 = s;\n v10 = 0;\n v9 = malloc(8uLL);\n v11 = v9;\n }\n v13 = strlen(s);\n v14 = v13 - v10;\n v15 = v13 - v10 + 1;\n v16 = malloc(v15);\n *v11 = v16;\n *(_BYTE *)(__strncpy_chk(v16, v12, v14, v15) + v14) = 0;\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_13C0(char *s) {\n char v2;\n char *v3;\n char v4;\n int v5;\n long long v6;\n int v7;\n int v8;\n uint64_t *v9;\n int v10;\n uint64_t *v11;\n char *v12;\n int v13;\n long long v14;\n unsigned int v15;\n void *v16;\n int v18;\n int v19;\n void *v20;\n long long v21;\n int v22;\n v2 = *s;\n if (*s) {\n v3 = s + 1;\n v4 = *s;\n v5 = 1;\n do {\n ++v3;\n v5 += v4 == 32;\n v4 = *(v3 - 1);\n } while (v4);\n v6 = 1LL;\n v7 = 0;\n v8 = 0;\n v9 = malloc(8LL * v5);\n do {\n while (v2 != 32) {\n v2 = s[v6++];\n if (!v2) goto LABEL_7;\n }\n v18 = v6 - 1;\n v22 = v6++;\n v19 = v18 - v8;\n v20 = malloc(v19 + 1);\n v9[v7++] = v20;\n v21 = __strncpy_chk(v20, &s[v8], v19, v19 + 1);\n v8 = v22;\n *(uint8_t *)(v21 + v19) = 0;\n v2 = s[v6 - 1];\n } while (v2);\n LABEL_7:\n v10 = v8;\n v11 = &v9[v7];\n v12 = &s[v10];\n } else {\n v12 = s;\n v10 = 0;\n v9 = malloc(8uLL);\n v11 = v9;\n }\n v13 = strlen(s);\n v14 = v13 - v10;\n v15 = v13 - v10 + 1;\n v16 = malloc(v15);\n *v11 = v16;\n *(uint8_t *)(__strncpy_chk(v16, v12, v14, v15) + v14) = 0;\n return v9;\n}", + "ida_pseudo_norm": "uint64_t *func0(char *s) {\n char v2;\n char *v3;\n char v4;\n int v5;\n long long v6;\n int v7;\n int v8;\n uint64_t *v9;\n int v10;\n uint64_t *v11;\n char *v12;\n int v13;\n long long v14;\n unsigned int v15;\n void *v16;\n int v18;\n int v19;\n void *v20;\n long long v21;\n int v22;\n v2 = *s;\n if (*s) {\n v3 = s + 1;\n v4 = *s;\n v5 = 1;\n do {\n ++v3;\n v5 += v4 == 32;\n v4 = *(v3 - 1);\n } while (v4);\n v6 = 1LL;\n v7 = 0;\n v8 = 0;\n v9 = malloc(8LL * v5);\n do {\n while (v2 != 32) {\n v2 = s[v6++];\n if (!v2) goto LABEL_7;\n }\n v18 = v6 - 1;\n v22 = v6++;\n v19 = v18 - v8;\n v20 = malloc(v19 + 1);\n v9[v7++] = v20;\n v21 = __strncpy_chk(v20, &s[v8], v19, v19 + 1);\n v8 = v22;\n *(uint8_t *)(v21 + v19) = 0;\n v2 = s[v6 - 1];\n } while (v2);\n LABEL_7:\n v10 = v8;\n v11 = &v9[v7];\n v12 = &s[v10];\n } else {\n v12 = s;\n v10 = 0;\n v9 = malloc(8uLL);\n v11 = v9;\n }\n v13 = strlen(s);\n v14 = v13 - v10;\n v15 = v13 - v10 + 1;\n v16 = malloc(v15);\n *v11 = v16;\n *(uint8_t *)(__strncpy_chk(v16, v12, v14, v15) + v14) = 0;\n return v9;\n}" + }, + { + "index": 709, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int key;\n\n int *values;\n\n int size;\n\n int capacity;\n\n} MapEntry;\n\n\n\ntypedef struct {\n\n MapEntry *entries;\n\n int size;\n\n int capacity;\n\n} Map;\n\n\n\nvoid init_map(Map *map) {\n\n map->entries = malloc(sizeof(MapEntry) * 10);\n\n map->size = 0;\n\n map->capacity = 10;\n\n}\n\n\n\nvoid add_to_map(Map *map, int key, int value) {\n\n for (int i = 0; i < map->size; i++) {\n\n if (map->entries[i].key == key) {\n\n for (int j = 0; j < map->entries[i].size; j++) {\n\n if (map->entries[i].values[j] == value)\n\n return;\n\n }\n\n if (map->entries[i].size == map->entries[i].capacity) {\n\n map->entries[i].capacity *= 2;\n\n map->entries[i].values = realloc(map->entries[i].values, sizeof(int) * map->entries[i].capacity);\n\n }\n\n map->entries[i].values[map->entries[i].size++] = value;\n\n return;\n\n }\n\n }\n\n if (map->size == map->capacity) {\n\n map->capacity *= 2;\n\n map->entries = realloc(map->entries, sizeof(MapEntry) * map->capacity);\n\n }\n\n map->entries[map->size].key = key;\n\n map->entries[map->size].values = malloc(sizeof(int) * 10);\n\n map->entries[map->size].values[0] = value;\n\n map->entries[map->size].size = 1;\n\n map->entries[map->size].capacity = 10;\n\n map->size++;\n\n}\n\n\n\n", + "func": "char *func0(int arr[][2], int len) {\n Map map;\n init_map(&map);\n for (int i = 0; i < len; i++) {\n add_to_map(&map, arr[i][1], arr[i][0]);\n }\n char *result = malloc(1024);\n strcpy(result, \"{\");\n for (int i = 0; i < map.size; i++) {\n char entry[32];\n sprintf(entry, \"%d: %d, \", map.entries[i].key, map.entries[i].size);\n strcat(result, entry);\n }\n int index = strlen(result) - 2;\n result[index] = '}';\n result[index + 1] = '\\0';\n for (int i = 0; i < map.size; i++) {\n free(map.entries[i].values);\n }\n free(map.entries);\n return result;\n}", + "test": "int main() {\n\n int test1[][2] = {{3, 4}, {1, 2}, {2, 4}, {8, 2}, {7, 2}, {8, 1}, {9, 1}, {8, 4}, {10, 4}};\n\n int test2[][2] = {{4, 5}, {2, 3}, {3, 5}, {9, 3}, {8, 3}, {9, 2}, {10, 2}, {9, 5}, {11, 5}};\n\n int test3[][2] = {{6, 5}, {3, 4}, {2, 6}, {11, 1}, {8, 22}, {8, 11}, {4, 3}, {14, 3}, {11, 6}};\n\n \n\n assert(strcmp(func0(test1, 9), \"{4: 4, 2: 3, 1: 2}\") == 0);\n\n assert(strcmp(func0(test2, 9), \"{5: 4, 3: 3, 2: 2}\") == 0);\n\n assert(strcmp(func0(test3, 9), \"{5: 1, 4: 1, 6: 2, 1: 1, 22: 1, 11: 1, 3: 2}\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x70,%rsp\nmov %rdi,-0x68(%rbp)\nmov %esi,-0x6c(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea -0x40(%rbp),%rax\nmov %rax,%rdi\ncallq 1249 \nmovl $0x0,-0x58(%rbp)\njmp 1664 \nmov -0x58(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x68(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x58(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x68(%rbp),%rax\nadd %rcx,%rax\nmov 0x4(%rax),%ecx\nlea -0x40(%rbp),%rax\nmov %ecx,%esi\nmov %rax,%rdi\ncallq 1286 \naddl $0x1,-0x58(%rbp)\nmov -0x58(%rbp),%eax\ncmp -0x6c(%rbp),%eax\njl 1625 \nmov $0x400,%edi\ncallq 1120 \nmov %rax,-0x48(%rbp)\nmov -0x48(%rbp),%rax\nmovw $0x7b,(%rax)\nmovl $0x0,-0x54(%rbp)\njmp 16f4 \nmov -0x40(%rbp),%rcx\nmov -0x54(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nadd %rcx,%rax\nmov 0x10(%rax),%ecx\nmov -0x40(%rbp),%rsi\nmov -0x54(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nadd %rsi,%rax\nmov (%rax),%edx\nlea -0x30(%rbp),%rax\nlea 0x938(%rip),%rsi\nmov %rax,%rdi\nmov $0x0,%eax\ncallq 1150 \nlea -0x30(%rbp),%rdx\nmov -0x48(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1140 \naddl $0x1,-0x54(%rbp)\nmov -0x38(%rbp),%eax\ncmp %eax,-0x54(%rbp)\njl 168c \nmov -0x48(%rbp),%rax\nmov %rax,%rdi\ncallq 10e0 \nsub $0x2,%eax\nmov %eax,-0x4c(%rbp)\nmov -0x4c(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmovb $0x7d,(%rax)\nmov -0x4c(%rbp),%eax\ncltq\nlea 0x1(%rax),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmovb $0x0,(%rax)\nmovl $0x0,-0x50(%rbp)\njmp 1764 \nmov -0x40(%rbp),%rcx\nmov -0x50(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nadd %rcx,%rax\nmov 0x8(%rax),%rax\nmov %rax,%rdi\ncallq 10d0 \naddl $0x1,-0x50(%rbp)\nmov -0x38(%rbp),%eax\ncmp %eax,-0x50(%rbp)\njl 173a \nmov -0x40(%rbp),%rax\nmov %rax,%rdi\ncallq 10d0 \nmov -0x48(%rbp),%rax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 1790 \ncallq 10f0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+var_68], rdi\nmov [rbp+var_6C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [rbp+ptr]\nmov rdi, rax\ncall init_map\nmov [rbp+var_58], 0\njmp short loc_1663\nloc_1624:\nmov eax, [rbp+var_58]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_68]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_58]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_68]\nadd rax, rcx\nmov ecx, [rax+4]\nlea rax, [rbp+ptr]\nmov esi, ecx\nmov rdi, rax\ncall add_to_map\nadd [rbp+var_58], 1\nloc_1663:\nmov eax, [rbp+var_58]\ncmp eax, [rbp+var_6C]\njl short loc_1624\nmov edi, 400h; size\ncall _malloc\nmov [rbp+dest], rax\nmov rax, [rbp+dest]\nmov word ptr [rax], 7Bh ; '{'\nmov [rbp+var_54], 0\njmp short loc_16F3\nloc_168B:\nmov rcx, [rbp+ptr]\nmov eax, [rbp+var_54]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nadd rax, rcx\nmov ecx, [rax+10h]\nmov rsi, [rbp+ptr]\nmov eax, [rbp+var_54]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nadd rax, rsi\nmov edx, [rax]\nlea rax, [rbp+s]\nlea rsi, format; \"%d: %d, \"\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rdx, [rbp+s]\nmov rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\nadd [rbp+var_54], 1\nloc_16F3:\nmov eax, [rbp+var_38]\ncmp [rbp+var_54], eax\njl short loc_168B\nmov rax, [rbp+dest]\nmov rdi, rax; s\ncall _strlen\nsub eax, 2\nmov [rbp+var_4C], eax\nmov eax, [rbp+var_4C]\nmovsxd rdx, eax\nmov rax, [rbp+dest]\nadd rax, rdx\nmov byte ptr [rax], 7Dh ; '}'\nmov eax, [rbp+var_4C]\ncdqe\nlea rdx, [rax+1]\nmov rax, [rbp+dest]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov [rbp+var_50], 0\njmp short loc_1763\nloc_1739:\nmov rcx, [rbp+ptr]\nmov eax, [rbp+var_50]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nadd rax, rcx\nmov rax, [rax+8]\nmov rdi, rax; ptr\ncall _free\nadd [rbp+var_50], 1\nloc_1763:\nmov eax, [rbp+var_38]\ncmp [rbp+var_50], eax\njl short loc_1739\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+dest]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_178F\ncall ___stack_chk_fail\nlocret_178F:\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-58h]\n int j; // [rsp+1Ch] [rbp-54h]\n int k; // [rsp+20h] [rbp-50h]\n int v6; // [rsp+24h] [rbp-4Ch]\n char *dest; // [rsp+28h] [rbp-48h]\n void *ptr; // [rsp+30h] [rbp-40h] BYREF\n int v9; // [rsp+38h] [rbp-38h]\n char s[40]; // [rsp+40h] [rbp-30h] BYREF\n unsigned __int64 v11; // [rsp+68h] [rbp-8h]\n\n v11 = __readfsqword(0x28u);\n init_map(&ptr);\n for ( i = 0; i < a2; ++i )\n add_to_map(&ptr, *(unsigned int *)(8LL * i + a1 + 4), *(unsigned int *)(8LL * i + a1));\n dest = (char *)malloc(0x400uLL);\n *(_WORD *)dest = 123;\n for ( j = 0; j < v9; ++j )\n {\n sprintf(s, \"%d: %d, \", *((_DWORD *)ptr + 6 * j), *((_DWORD *)ptr + 6 * j + 4));\n strcat(dest, s);\n }\n v6 = strlen(dest) - 2;\n dest[v6] = 125;\n dest[v6 + 1] = 0;\n for ( k = 0; k < v9; ++k )\n free(*((void **)ptr + 3 * k + 1));\n free(ptr);\n return dest;\n}", + "ida_strip_asm": "sub_15ED:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+var_68], rdi\nmov [rbp+var_6C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [rbp+ptr]\nmov rdi, rax\ncall sub_1249\nmov [rbp+var_58], 0\njmp short loc_1663\nloc_1624:\nmov eax, [rbp+var_58]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_68]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_58]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_68]\nadd rax, rcx\nmov ecx, [rax+4]\nlea rax, [rbp+ptr]\nmov esi, ecx\nmov rdi, rax\ncall sub_1286\nadd [rbp+var_58], 1\nloc_1663:\nmov eax, [rbp+var_58]\ncmp eax, [rbp+var_6C]\njl short loc_1624\nmov edi, 400h; size\ncall _malloc\nmov [rbp+dest], rax\nmov rax, [rbp+dest]\nmov word ptr [rax], 7Bh ; '{'\nmov [rbp+var_54], 0\njmp short loc_16F3\nloc_168B:\nmov rcx, [rbp+ptr]\nmov eax, [rbp+var_54]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nadd rax, rcx\nmov ecx, [rax+10h]\nmov rsi, [rbp+ptr]\nmov eax, [rbp+var_54]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nadd rax, rsi\nmov edx, [rax]\nlea rax, [rbp+s]\nlea rsi, format; \"%d: %d, \"\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rdx, [rbp+s]\nmov rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\nadd [rbp+var_54], 1\nloc_16F3:\nmov eax, [rbp+var_38]\ncmp [rbp+var_54], eax\njl short loc_168B\nmov rax, [rbp+dest]\nmov rdi, rax; s\ncall _strlen\nsub eax, 2\nmov [rbp+var_4C], eax\nmov eax, [rbp+var_4C]\nmovsxd rdx, eax\nmov rax, [rbp+dest]\nadd rax, rdx\nmov byte ptr [rax], 7Dh ; '}'\nmov eax, [rbp+var_4C]\ncdqe\nlea rdx, [rax+1]\nmov rax, [rbp+dest]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov [rbp+var_50], 0\njmp short loc_1763\nloc_1739:\nmov rcx, [rbp+ptr]\nmov eax, [rbp+var_50]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 3\nadd rax, rcx\nmov rax, [rax+8]\nmov rdi, rax; ptr\ncall _free\nadd [rbp+var_50], 1\nloc_1763:\nmov eax, [rbp+var_38]\ncmp [rbp+var_50], eax\njl short loc_1739\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+dest]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_178F\ncall ___stack_chk_fail\nlocret_178F:\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_15ED(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-58h]\n int j; // [rsp+1Ch] [rbp-54h]\n int k; // [rsp+20h] [rbp-50h]\n int v6; // [rsp+24h] [rbp-4Ch]\n char *dest; // [rsp+28h] [rbp-48h]\n void *ptr; // [rsp+30h] [rbp-40h] BYREF\n int v9; // [rsp+38h] [rbp-38h]\n char s[40]; // [rsp+40h] [rbp-30h] BYREF\n unsigned __int64 v11; // [rsp+68h] [rbp-8h]\n\n v11 = __readfsqword(0x28u);\n sub_1249(&ptr);\n for ( i = 0; i < a2; ++i )\n sub_1286(&ptr, *(unsigned int *)(8LL * i + a1 + 4), *(unsigned int *)(8LL * i + a1));\n dest = (char *)malloc(0x400uLL);\n *(_WORD *)dest = 123;\n for ( j = 0; j < v9; ++j )\n {\n sprintf(s, \"%d: %d, \", *((_DWORD *)ptr + 6 * j), *((_DWORD *)ptr + 6 * j + 4));\n strcat(dest, s);\n }\n v6 = strlen(dest) - 2;\n dest[v6] = 125;\n dest[v6 + 1] = 0;\n for ( k = 0; k < v9; ++k )\n free(*((void **)ptr + 3 * k + 1));\n free(ptr);\n return dest;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_15ED(long long a1, int a2) {\n int i;\n int j;\n int k;\n int v6;\n char *dest;\n void *ptr;\n int v9;\n char s[40];\n unsigned long long v11;\n v11 = __readfsqword(40u);\n sub_1249(&ptr);\n for (i = 0; i < a2; ++i)\n sub_1286(&ptr, *(unsigned int *)(8LL * i + a1 + 4),\n *(unsigned int *)(8LL * i + a1));\n dest = (char *)malloc(1024uLL);\n *(unsigned short *)dest = 123;\n for (j = 0; j < v9; ++j) {\n sprintf(s, \"%d: %d, \", *((uint32_t *)ptr + 6 * j),\n *((uint32_t *)ptr + 6 * j + 4));\n strcat(dest, s);\n }\n v6 = strlen(dest) - 2;\n dest[v6] = 125;\n dest[v6 + 1] = 0;\n for (k = 0; k < v9; ++k) free(*((void **)ptr + 3 * k + 1));\n free(ptr);\n return dest;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2) {\n int i;\n int j;\n int k;\n int v6;\n char *dest;\n void *ptr;\n int v9;\n char s[40];\n unsigned long long v11;\n v11 = __readfsqword(40u);\n init_map(&ptr);\n for (i = 0; i < a2; ++i)\n add_to_map(&ptr, *(unsigned int *)(8LL * i + a1 + 4),\n *(unsigned int *)(8LL * i + a1));\n dest = (char *)malloc(1024uLL);\n *(unsigned short *)dest = 123;\n for (j = 0; j < v9; ++j) {\n sprintf(s, \"%d: %d, \", *((uint32_t *)ptr + 6 * j),\n *((uint32_t *)ptr + 6 * j + 4));\n strcat(dest, s);\n }\n v6 = strlen(dest) - 2;\n dest[v6] = 125;\n dest[v6 + 1] = 0;\n for (k = 0; k < v9; ++k) free(*((void **)ptr + 3 * k + 1));\n free(ptr);\n return dest;\n}" + }, + { + "index": 709, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int key;\n\n int *values;\n\n int size;\n\n int capacity;\n\n} MapEntry;\n\n\n\ntypedef struct {\n\n MapEntry *entries;\n\n int size;\n\n int capacity;\n\n} Map;\n\n\n\nvoid init_map(Map *map) {\n\n map->entries = malloc(sizeof(MapEntry) * 10);\n\n map->size = 0;\n\n map->capacity = 10;\n\n}\n\n\n\nvoid add_to_map(Map *map, int key, int value) {\n\n for (int i = 0; i < map->size; i++) {\n\n if (map->entries[i].key == key) {\n\n for (int j = 0; j < map->entries[i].size; j++) {\n\n if (map->entries[i].values[j] == value)\n\n return;\n\n }\n\n if (map->entries[i].size == map->entries[i].capacity) {\n\n map->entries[i].capacity *= 2;\n\n map->entries[i].values = realloc(map->entries[i].values, sizeof(int) * map->entries[i].capacity);\n\n }\n\n map->entries[i].values[map->entries[i].size++] = value;\n\n return;\n\n }\n\n }\n\n if (map->size == map->capacity) {\n\n map->capacity *= 2;\n\n map->entries = realloc(map->entries, sizeof(MapEntry) * map->capacity);\n\n }\n\n map->entries[map->size].key = key;\n\n map->entries[map->size].values = malloc(sizeof(int) * 10);\n\n map->entries[map->size].values[0] = value;\n\n map->entries[map->size].size = 1;\n\n map->entries[map->size].capacity = 10;\n\n map->size++;\n\n}\n\n\n\n", + "func": "char *func0(int arr[][2], int len) {\n Map map;\n init_map(&map);\n for (int i = 0; i < len; i++) {\n add_to_map(&map, arr[i][1], arr[i][0]);\n }\n char *result = malloc(1024);\n strcpy(result, \"{\");\n for (int i = 0; i < map.size; i++) {\n char entry[32];\n sprintf(entry, \"%d: %d, \", map.entries[i].key, map.entries[i].size);\n strcat(result, entry);\n }\n int index = strlen(result) - 2;\n result[index] = '}';\n result[index + 1] = '\\0';\n for (int i = 0; i < map.size; i++) {\n free(map.entries[i].values);\n }\n free(map.entries);\n return result;\n}", + "test": "int main() {\n\n int test1[][2] = {{3, 4}, {1, 2}, {2, 4}, {8, 2}, {7, 2}, {8, 1}, {9, 1}, {8, 4}, {10, 4}};\n\n int test2[][2] = {{4, 5}, {2, 3}, {3, 5}, {9, 3}, {8, 3}, {9, 2}, {10, 2}, {9, 5}, {11, 5}};\n\n int test3[][2] = {{6, 5}, {3, 4}, {2, 6}, {11, 1}, {8, 22}, {8, 11}, {4, 3}, {14, 3}, {11, 6}};\n\n \n\n assert(strcmp(func0(test1, 9), \"{4: 4, 2: 3, 1: 2}\") == 0);\n\n assert(strcmp(func0(test2, 9), \"{5: 4, 3: 3, 2: 2}\") == 0);\n\n assert(strcmp(func0(test3, 9), \"{5: 1, 4: 1, 6: 2, 1: 1, 22: 1, 11: 1, 3: 2}\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nsub $0x40,%rsp\nmov %rdi,%r12\nmov %esi,%ebp\nmov %fs:0x28,%rax\nmov %rax,0x38(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\ncallq 1209 \ntest %ebp,%ebp\njle 13dd \nmov %r12,%rbx\nlea -0x1(%rbp),%eax\nlea 0x8(%r12,%rax,8),%r12\nmov %rsp,%rbp\nmov 0x4(%rbx),%esi\nmov (%rbx),%edx\nmov %rbp,%rdi\ncallq 122e \nadd $0x8,%rbx\ncmp %r12,%rbx\njne 13c7 \nmov $0x400,%edi\ncallq 10f0 \nmov %rax,%r12\nmovw $0x7b,(%rax)\ncmpl $0x0,0x8(%rsp)\njle 144b \nmov $0x0,%ebx\nlea 0x10(%rsp),%rbp\nlea (%rbx,%rbx,2),%rdx\nmov (%rsp),%rax\nlea (%rax,%rdx,8),%rax\nmov 0x10(%rax),%r9d\nmov (%rax),%r8d\nlea 0xbea(%rip),%rcx\nmov $0x20,%edx\nmov $0x1,%esi\nmov %rbp,%rdi\nmov $0x0,%eax\ncallq 1110 <__sprintf_chk@plt>\nmov $0x400,%edx\nmov %rbp,%rsi\nmov %r12,%rdi\ncallq 10b0 <__strcat_chk@plt>\nadd $0x1,%rbx\ncmp %ebx,0x8(%rsp)\njg 1400 \nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nmov %r12,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nsub $0x3,%eax\ncltq\nmovb $0x7d,(%r12,%rax,1)\nmovb $0x0,0x1(%r12,%rax,1)\ncmpl $0x0,0x8(%rsp)\njle 149e \nmov $0x0,%ebp\nmov $0x0,%ebx\nmov (%rsp),%rax\nmov 0x8(%rax,%rbp,1),%rdi\ncallq 10c0 \nadd $0x1,%ebx\nadd $0x18,%rbp\ncmp %ebx,0x8(%rsp)\njg 1483 \nmov (%rsp),%rdi\ncallq 10c0 \nmov 0x38(%rsp),%rax\nxor %fs:0x28,%rax\njne 14c3 \nmov %r12,%rax\nadd $0x40,%rsp\npop %rbx\npop %rbp\npop %r12\nretq\ncallq 10d0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 48h\nmov r12, rdi\nmov ebp, esi\nmov rax, fs:28h\nmov [rsp+78h+var_40], rax\nxor eax, eax\nmov rdi, rsp\ncall init_map\ntest ebp, ebp\njle short loc_1428\nmov rbx, r12\nmovsxd rbp, ebp\nlea r12, [r12+rbp*8]\nmov rbp, rsp\nloc_1412:\nmov edx, [rbx]\nmov esi, [rbx+4]\nmov rdi, rbp\ncall add_to_map\nadd rbx, 8\ncmp rbx, r12\njnz short loc_1412\nloc_1428:\nmov edi, 400h; size\ncall _malloc\nmov r14, rax\nmov word ptr [rax], 7Bh ; '{'\nmov eax, [rsp+78h+var_70]\ntest eax, eax\njle loc_14FF\ncdqe\nlea r13, [rax+rax*2]\nshl r13, 3\nmov ebx, 0\nlea r15, aDD; \"%d: %d, \"\nloc_145C:\nmov rbp, [rsp+78h+ptr]\nlea rax, [rbp+rbx+0]\nlea r12, [rsp+78h+var_68]\nmov r9d, [rax+10h]\nmov r8d, [rax]\nmov rcx, r15\nmov edx, 20h ; ' '\nmov esi, 2\nmov rdi, r12\nmov eax, 0\ncall ___sprintf_chk\nmov edx, 400h\nmov rsi, r12\nmov rdi, r14\ncall ___strcat_chk\nadd rbx, 18h\ncmp rbx, r13\njnz short loc_145C\nmov rdi, r14; s\ncall _strlen\nsub eax, 2\ncdqe\nmov byte ptr [r14+rax], 7Dh ; '}'\nmov byte ptr [r14+rax+1], 0\nmov ebx, 0\nloc_14C1:\nmov rdi, [rbp+rbx+8]; ptr\ncall _free\nadd rbx, 18h\ncmp rbx, r13\njnz short loc_14C1\nloc_14D4:\nmov rdi, [rsp+78h+ptr]; ptr\ncall _free\nmov rax, [rsp+78h+var_40]\nsub rax, fs:28h\njnz short loc_1519\nmov rax, r14\nadd rsp, 48h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14FF:\nmov rdi, r14; s\ncall _strlen\nsub eax, 2\ncdqe\nmov byte ptr [r14+rax], 7Dh ; '}'\nmov byte ptr [r14+rax+1], 0\njmp short loc_14D4\nloc_1519:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(unsigned int *a1, int a2)\n{\n unsigned int *v2; // rbx\n char *v3; // r14\n __int64 v4; // r13\n __int64 v5; // rbx\n char *v6; // rbp\n int v7; // eax\n __int64 v8; // rbx\n int v10; // eax\n void *ptr; // [rsp+0h] [rbp-78h] BYREF\n int v12; // [rsp+8h] [rbp-70h]\n _BYTE v13[40]; // [rsp+10h] [rbp-68h] BYREF\n unsigned __int64 v14; // [rsp+38h] [rbp-40h]\n\n v14 = __readfsqword(0x28u);\n init_map(&ptr);\n if ( a2 > 0 )\n {\n v2 = a1;\n do\n {\n add_to_map(&ptr, v2[1], *v2);\n v2 += 2;\n }\n while ( v2 != &a1[2 * a2] );\n }\n v3 = (char *)malloc(0x400uLL);\n *(_WORD *)v3 = 123;\n if ( v12 <= 0 )\n {\n v10 = strlen(v3) - 2;\n v3[v10] = 125;\n v3[v10 + 1] = 0;\n }\n else\n {\n v4 = 24LL * v12;\n v5 = 0LL;\n do\n {\n v6 = (char *)ptr;\n __sprintf_chk(v13, 2LL, 32LL, \"%d: %d, \", *(_DWORD *)((char *)ptr + v5), *(_DWORD *)((char *)ptr + v5 + 16));\n __strcat_chk(v3, v13, 1024LL);\n v5 += 24LL;\n }\n while ( v5 != v4 );\n v7 = strlen(v3) - 2;\n v3[v7] = 125;\n v3[v7 + 1] = 0;\n v8 = 0LL;\n do\n {\n free(*(void **)&v6[v8 + 8]);\n v8 += 24LL;\n }\n while ( v8 != v4 );\n }\n free(ptr);\n return v3;\n}", + "ida_strip_asm": "sub_13D2:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 48h\nmov r12, rdi\nmov ebp, esi\nmov rax, fs:28h\nmov [rsp+78h+var_40], rax\nxor eax, eax\nmov rdi, rsp\ncall sub_1249\ntest ebp, ebp\njle short loc_1428\nmov rbx, r12\nmovsxd rbp, ebp\nlea r12, [r12+rbp*8]\nmov rbp, rsp\nloc_1412:\nmov edx, [rbx]\nmov esi, [rbx+4]\nmov rdi, rbp\ncall sub_126E\nadd rbx, 8\ncmp rbx, r12\njnz short loc_1412\nloc_1428:\nmov edi, 400h; size\ncall _malloc\nmov r14, rax\nmov word ptr [rax], 7Bh ; '{'\nmov eax, [rsp+78h+var_70]\ntest eax, eax\njle loc_14FF\ncdqe\nlea r13, [rax+rax*2]\nshl r13, 3\nmov ebx, 0\nlea r15, aDD; \"%d: %d, \"\nloc_145C:\nmov rbp, [rsp+78h+ptr]\nlea rax, [rbp+rbx+0]\nlea r12, [rsp+78h+var_68]\nmov r9d, [rax+10h]\nmov r8d, [rax]\nmov rcx, r15\nmov edx, 20h ; ' '\nmov esi, 2\nmov rdi, r12\nmov eax, 0\ncall ___sprintf_chk\nmov edx, 400h\nmov rsi, r12\nmov rdi, r14\ncall ___strcat_chk\nadd rbx, 18h\ncmp rbx, r13\njnz short loc_145C\nmov rdi, r14; s\ncall _strlen\nsub eax, 2\ncdqe\nmov byte ptr [r14+rax], 7Dh ; '}'\nmov byte ptr [r14+rax+1], 0\nmov ebx, 0\nloc_14C1:\nmov rdi, [rbp+rbx+8]; ptr\ncall _free\nadd rbx, 18h\ncmp rbx, r13\njnz short loc_14C1\nloc_14D4:\nmov rdi, [rsp+78h+ptr]; ptr\ncall _free\nmov rax, [rsp+78h+var_40]\nsub rax, fs:28h\njnz short loc_1519\nmov rax, r14\nadd rsp, 48h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14FF:\nmov rdi, r14; s\ncall _strlen\nsub eax, 2\ncdqe\nmov byte ptr [r14+rax], 7Dh ; '}'\nmov byte ptr [r14+rax+1], 0\njmp short loc_14D4\nloc_1519:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_13D2(unsigned int *a1, int a2)\n{\n unsigned int *v2; // rbx\n char *v3; // r14\n __int64 v4; // r13\n __int64 v5; // rbx\n char *v6; // rbp\n int v7; // eax\n __int64 v8; // rbx\n int v10; // eax\n void *ptr; // [rsp+0h] [rbp-78h] BYREF\n int v12; // [rsp+8h] [rbp-70h]\n _BYTE v13[40]; // [rsp+10h] [rbp-68h] BYREF\n unsigned __int64 v14; // [rsp+38h] [rbp-40h]\n\n v14 = __readfsqword(0x28u);\n sub_1249(&ptr);\n if ( a2 > 0 )\n {\n v2 = a1;\n do\n {\n sub_126E(&ptr, v2[1], *v2);\n v2 += 2;\n }\n while ( v2 != &a1[2 * a2] );\n }\n v3 = (char *)malloc(0x400uLL);\n *(_WORD *)v3 = 123;\n if ( v12 <= 0 )\n {\n v10 = strlen(v3) - 2;\n v3[v10] = 125;\n v3[v10 + 1] = 0;\n }\n else\n {\n v4 = 24LL * v12;\n v5 = 0LL;\n do\n {\n v6 = (char *)ptr;\n __sprintf_chk(v13, 2LL, 32LL, \"%d: %d, \", *(_DWORD *)((char *)ptr + v5), *(_DWORD *)((char *)ptr + v5 + 16));\n __strcat_chk(v3, v13, 1024LL);\n v5 += 24LL;\n }\n while ( v5 != v4 );\n v7 = strlen(v3) - 2;\n v3[v7] = 125;\n v3[v7 + 1] = 0;\n v8 = 0LL;\n do\n {\n free(*(void **)&v6[v8 + 8]);\n v8 += 24LL;\n }\n while ( v8 != v4 );\n }\n free(ptr);\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_13D2(unsigned int *a1, int a2) {\n unsigned int *v2;\n char *v3;\n long long v4;\n long long v5;\n char *v6;\n int v7;\n long long v8;\n int v10;\n void *ptr;\n int v12;\n uint8_t v13[40];\n unsigned long long v14;\n v14 = __readfsqword(40u);\n sub_1249(&ptr);\n if (a2 > 0) {\n v2 = a1;\n do {\n sub_126E(&ptr, v2[1], *v2);\n v2 += 2;\n } while (v2 != &a1[2 * a2]);\n }\n v3 = (char *)malloc(1024uLL);\n *(unsigned short *)v3 = 123;\n if (v12 <= 0) {\n v10 = strlen(v3) - 2;\n v3[v10] = 125;\n v3[v10 + 1] = 0;\n } else {\n v4 = 24LL * v12;\n v5 = 0LL;\n do {\n v6 = (char *)ptr;\n __sprintf_chk(v13, 2LL, 32LL, \"%d: %d, \", *(uint32_t *)((char *)ptr + v5),\n *(uint32_t *)((char *)ptr + v5 + 16));\n __strcat_chk(v3, v13, 1024LL);\n v5 += 24LL;\n } while (v5 != v4);\n v7 = strlen(v3) - 2;\n v3[v7] = 125;\n v3[v7 + 1] = 0;\n v8 = 0LL;\n do {\n free(*(void **)&v6[v8 + 8]);\n v8 += 24LL;\n } while (v8 != v4);\n }\n free(ptr);\n return v3;\n}", + "ida_pseudo_norm": "char *func0(unsigned int *a1, int a2) {\n unsigned int *v2;\n char *v3;\n long long v4;\n long long v5;\n char *v6;\n int v7;\n long long v8;\n int v10;\n void *ptr;\n int v12;\n uint8_t v13[40];\n unsigned long long v14;\n v14 = __readfsqword(40u);\n init_map(&ptr);\n if (a2 > 0) {\n v2 = a1;\n do {\n add_to_map(&ptr, v2[1], *v2);\n v2 += 2;\n } while (v2 != &a1[2 * a2]);\n }\n v3 = (char *)malloc(1024uLL);\n *(unsigned short *)v3 = 123;\n if (v12 <= 0) {\n v10 = strlen(v3) - 2;\n v3[v10] = 125;\n v3[v10 + 1] = 0;\n } else {\n v4 = 24LL * v12;\n v5 = 0LL;\n do {\n v6 = (char *)ptr;\n __sprintf_chk(v13, 2LL, 32LL, \"%d: %d, \", *(uint32_t *)((char *)ptr + v5),\n *(uint32_t *)((char *)ptr + v5 + 16));\n __strcat_chk(v3, v13, 1024LL);\n v5 += 24LL;\n } while (v5 != v4);\n v7 = strlen(v3) - 2;\n v3[v7] = 125;\n v3[v7 + 1] = 0;\n v8 = 0LL;\n do {\n free(*(void **)&v6[v8 + 8]);\n v8 += 24LL;\n } while (v8 != v4);\n }\n free(ptr);\n return v3;\n}" + }, + { + "index": 709, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int key;\n\n int *values;\n\n int size;\n\n int capacity;\n\n} MapEntry;\n\n\n\ntypedef struct {\n\n MapEntry *entries;\n\n int size;\n\n int capacity;\n\n} Map;\n\n\n\nvoid init_map(Map *map) {\n\n map->entries = malloc(sizeof(MapEntry) * 10);\n\n map->size = 0;\n\n map->capacity = 10;\n\n}\n\n\n\nvoid add_to_map(Map *map, int key, int value) {\n\n for (int i = 0; i < map->size; i++) {\n\n if (map->entries[i].key == key) {\n\n for (int j = 0; j < map->entries[i].size; j++) {\n\n if (map->entries[i].values[j] == value)\n\n return;\n\n }\n\n if (map->entries[i].size == map->entries[i].capacity) {\n\n map->entries[i].capacity *= 2;\n\n map->entries[i].values = realloc(map->entries[i].values, sizeof(int) * map->entries[i].capacity);\n\n }\n\n map->entries[i].values[map->entries[i].size++] = value;\n\n return;\n\n }\n\n }\n\n if (map->size == map->capacity) {\n\n map->capacity *= 2;\n\n map->entries = realloc(map->entries, sizeof(MapEntry) * map->capacity);\n\n }\n\n map->entries[map->size].key = key;\n\n map->entries[map->size].values = malloc(sizeof(int) * 10);\n\n map->entries[map->size].values[0] = value;\n\n map->entries[map->size].size = 1;\n\n map->entries[map->size].capacity = 10;\n\n map->size++;\n\n}\n\n\n\n", + "func": "char *func0(int arr[][2], int len) {\n Map map;\n init_map(&map);\n for (int i = 0; i < len; i++) {\n add_to_map(&map, arr[i][1], arr[i][0]);\n }\n char *result = malloc(1024);\n strcpy(result, \"{\");\n for (int i = 0; i < map.size; i++) {\n char entry[32];\n sprintf(entry, \"%d: %d, \", map.entries[i].key, map.entries[i].size);\n strcat(result, entry);\n }\n int index = strlen(result) - 2;\n result[index] = '}';\n result[index + 1] = '\\0';\n for (int i = 0; i < map.size; i++) {\n free(map.entries[i].values);\n }\n free(map.entries);\n return result;\n}", + "test": "int main() {\n\n int test1[][2] = {{3, 4}, {1, 2}, {2, 4}, {8, 2}, {7, 2}, {8, 1}, {9, 1}, {8, 4}, {10, 4}};\n\n int test2[][2] = {{4, 5}, {2, 3}, {3, 5}, {9, 3}, {8, 3}, {9, 2}, {10, 2}, {9, 5}, {11, 5}};\n\n int test3[][2] = {{6, 5}, {3, 4}, {2, 6}, {11, 1}, {8, 22}, {8, 11}, {4, 3}, {14, 3}, {11, 6}};\n\n \n\n assert(strcmp(func0(test1, 9), \"{4: 4, 2: 3, 1: 2}\") == 0);\n\n assert(strcmp(func0(test2, 9), \"{5: 4, 3: 3, 2: 2}\") == 0);\n\n assert(strcmp(func0(test3, 9), \"{5: 1, 4: 1, 6: 2, 1: 1, 22: 1, 11: 1, 3: 2}\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\nmov %esi,%ebp\npush %rbx\nmov %rdi,%rbx\nmov $0xf0,%edi\nsub $0x40,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x38(%rsp)\nxor %eax,%eax\ncallq 10f0 \nmov %rax,(%rsp)\nmov %rax,%r14\nmovabs $0xa00000000,%rax\nmov %rax,0x8(%rsp)\ntest %ebp,%ebp\njle 17e0 \nlea -0x1(%rbp),%eax\nmov %rsp,%rbp\nlea 0x8(%rbx,%rax,8),%r12\nnopl 0x0(%rax,%rax,1)\nmov 0x4(%rbx),%esi\nmov (%rbx),%edx\nmov %rbp,%rdi\nadd $0x8,%rbx\ncallq 1500 \ncmp %rbx,%r12\njne 16b0 \nmov 0x8(%rsp),%ebx\nmov $0x400,%edi\nmov (%rsp),%r14\ncallq 10f0 \nmov $0x7b,%edx\nmov %dx,(%rax)\nmov %rax,%r12\ntest %ebx,%ebx\njle 17f7 \nxor %r13d,%r13d\nlea 0x10(%rsp),%rbx\nlea 0x90a(%rip),%rbp\nnopw 0x0(%rax,%rax,1)\nlea 0x0(%r13,%r13,2),%rax\nmov %rbx,%rdi\nmov %rbp,%rcx\nmov $0x20,%edx\nlea (%r14,%rax,8),%rax\nmov $0x1,%esi\nmov 0x10(%rax),%r9d\nmov (%rax),%r8d\nxor %eax,%eax\ncallq 1110 <__sprintf_chk@plt>\nmov %r12,%rdi\nmov (%rdi),%edx\nadd $0x4,%rdi\nlea -0x1010101(%rdx),%eax\nnot %edx\nand %edx,%eax\nand $0x80808080,%eax\nje 172a \nmov %eax,%edx\nmov %rbx,%rsi\nshr $0x10,%edx\ntest $0x8080,%eax\ncmove %edx,%eax\nlea 0x2(%rdi),%rdx\ncmove %rdx,%rdi\nmov $0x400,%edx\nmov %eax,%ecx\nadd %al,%cl\nsbb $0x3,%rdi\nadd $0x1,%r13\ncallq 10e0 <__stpcpy_chk@plt>\nmov 0x8(%rsp),%edx\nmov (%rsp),%r14\ncmp %r13d,%edx\njg 1700 \nsub %r12,%rax\nsub $0x2,%eax\ncltq\nmovb $0x7d,(%r12,%rax,1)\nmovb $0x0,0x1(%r12,%rax,1)\ntest %edx,%edx\njle 17b4 \nxor %ebx,%ebx\nnopl (%rax)\nlea (%rbx,%rbx,2),%rax\nadd $0x1,%rbx\nmov 0x8(%r14,%rax,8),%rdi\ncallq 10b0 \nmov (%rsp),%r14\ncmp %ebx,0x8(%rsp)\njg 1798 \nmov %r14,%rdi\ncallq 10b0 \nmov 0x38(%rsp),%rax\nxor %fs:0x28,%rax\njne 1848 \nadd $0x40,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopl 0x0(%rax)\nmov $0x400,%edi\ncallq 10f0 \nmov %rax,%r12\nmov $0x7b,%eax\nmov %ax,(%r12)\nmov %r12,%rax\nmov (%rax),%ecx\nadd $0x4,%rax\nlea -0x1010101(%rcx),%edx\nnot %ecx\nand %ecx,%edx\nand $0x80808080,%edx\nje 17fa \nmov %edx,%ecx\nshr $0x10,%ecx\ntest $0x8080,%edx\ncmove %ecx,%edx\nlea 0x2(%rax),%rcx\ncmove %rcx,%rax\nmov %edx,%ecx\nadd %dl,%cl\nsbb $0x3,%rax\nsub %r12,%rax\nsub $0x2,%eax\ncltq\nmovb $0x7d,(%r12,%rax,1)\nmovb $0x0,0x1(%r12,%rax,1)\njmpq 17b4 \ncallq 10c0 <__stack_chk_fail@plt>\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\nmovsxd rbp, esi\npush rbx\nmov rbx, rdi\nmov edi, 0F0h; size\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+88h+var_40], rax\nxor eax, eax\ncall _malloc\nmov [rsp+88h+ptr], rax\nmov r15, rax\nmov rax, cs:qword_2158\nmov [rsp+88h+var_70], rax\ntest ebp, ebp\njle loc_1700\nlea r12, [rbx+rbp*8]\nlea rbp, [rsp+88h+ptr]\nnop word ptr [rax+rax+00000000h]\nloc_15F0:\nmov edx, [rbx]\nmov esi, [rbx+4]\nmov rdi, rbp\nadd rbx, 8\ncall add_to_map\ncmp rbx, r12\njnz short loc_15F0\nmovsxd rbp, dword ptr [rsp+88h+var_70]\nmov edi, 400h; size\nmov r15, [rsp+88h+ptr]\ncall _malloc\nmov esi, 7Bh ; '{'\nmov [rax], si\nmov rbx, rax\ntest ebp, ebp\njle loc_1715\nlea r12, [rbp+rbp*2+0]\nlea r13, aDD; \"%d: %d, \"\nlea rax, ds:0[r12*8]\nlea rbp, [rsp+88h+var_68]\nmov r12, r15\nmov [rsp+88h+var_80], rax\nlea r14, [r15+rax]\nnop word ptr [rax+rax+00h]\nloc_1658:\nmov r9d, [r12+10h]\nmov r8d, [r12]\nmov rcx, r13\nmov rdi, rbp\nmov edx, 20h ; ' '\nmov esi, 2\nxor eax, eax\nadd r12, 18h\ncall ___sprintf_chk\nmov rdi, rbx; s\ncall _strlen\nmov edx, 400h\nmov rsi, rbp\nlea rdi, [rbx+rax]\ncall ___stpcpy_chk\ncmp r12, r14\njnz short loc_1658\nsub rax, rbx\nmov ecx, 7Dh ; '}'\nmov r12, [rsp+88h+var_80]\nlea rbp, [r15+8]\nsub eax, 2\ncdqe\nadd r12, rbp\nmov [rbx+rax], cx\nnop word ptr [rax+rax+00000000h]\nloc_16C0:\nmov rdi, [rbp+0]; ptr\nadd rbp, 18h\ncall _free\ncmp rbp, r12\njnz short loc_16C0\nloc_16D2:\nmov rdi, r15; ptr\ncall _free\nmov rax, [rsp+88h+var_40]\nsub rax, fs:28h\njnz short loc_172D\nadd rsp, 58h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1700:\nmov edi, 400h; size\ncall _malloc\nmov rbx, rax\nmov eax, 7Bh ; '{'\nmov [rbx], ax\nloc_1715:\nmov rdi, rbx; s\ncall _strlen\nmov edx, 7Dh ; '}'\nsub eax, 2\ncdqe\nmov [rbx+rax], dx\njmp short loc_16D2\nloc_172D:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(unsigned int *a1, int a2)\n{\n unsigned int *v2; // rbx\n char *v3; // r15\n unsigned int *v4; // r12\n __int64 v5; // rdx\n __int64 v6; // rsi\n __int64 v7; // rbp\n char *v8; // rax\n char *v9; // rbx\n char *v10; // r12\n int v11; // r9d\n int v12; // r8d\n size_t v13; // rax\n int v14; // eax\n void **v15; // rbp\n void *v16; // rdi\n __int64 v18; // [rsp+8h] [rbp-80h]\n void *ptr; // [rsp+10h] [rbp-78h] BYREF\n __int64 v20; // [rsp+18h] [rbp-70h]\n _BYTE v21[40]; // [rsp+20h] [rbp-68h] BYREF\n unsigned __int64 v22; // [rsp+48h] [rbp-40h]\n\n v2 = a1;\n v22 = __readfsqword(0x28u);\n ptr = malloc(0xF0uLL);\n v3 = (char *)ptr;\n v20 = 0xA00000000LL;\n if ( a2 <= 0 )\n {\n v9 = (char *)malloc(0x400uLL);\n *(_WORD *)v9 = 123;\nLABEL_11:\n *(_WORD *)&v9[(int)(strlen(v9) - 2)] = 125;\n goto LABEL_9;\n }\n v4 = &a1[2 * a2];\n do\n {\n v5 = *v2;\n v6 = v2[1];\n v2 += 2;\n add_to_map(&ptr, v6, v5);\n }\n while ( v2 != v4 );\n v7 = (int)v20;\n v3 = (char *)ptr;\n v8 = (char *)malloc(0x400uLL);\n *(_WORD *)v8 = 123;\n v9 = v8;\n if ( (int)v7 <= 0 )\n goto LABEL_11;\n v10 = v3;\n v18 = 24 * v7;\n do\n {\n v11 = *((_DWORD *)v10 + 4);\n v12 = *(_DWORD *)v10;\n v10 += 24;\n __sprintf_chk(v21, 2LL, 32LL, \"%d: %d, \", v12, v11);\n v13 = strlen(v9);\n v14 = __stpcpy_chk(&v9[v13], v21, 1024LL);\n }\n while ( v10 != &v3[24 * v7] );\n v15 = (void **)(v3 + 8);\n *(_WORD *)&v9[v14 - (int)v9 - 2] = 125;\n do\n {\n v16 = *v15;\n v15 += 3;\n free(v16);\n }\n while ( v15 != (void **)&v3[v18 + 8] );\nLABEL_9:\n free(v3);\n return v9;\n}", + "ida_strip_asm": "sub_1590:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\nmovsxd rbp, esi\npush rbx\nmov rbx, rdi\nmov edi, 0F0h; size\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+88h+var_40], rax\nxor eax, eax\ncall _malloc\nmov [rsp+88h+ptr], rax\nmov r15, rax\nmov rax, cs:qword_2158\nmov [rsp+88h+var_70], rax\ntest ebp, ebp\njle loc_1700\nlea r12, [rbx+rbp*8]\nlea rbp, [rsp+88h+ptr]\nnop word ptr [rax+rax+00000000h]\nloc_15F0:\nmov edx, [rbx]\nmov esi, [rbx+4]\nmov rdi, rbp\nadd rbx, 8\ncall sub_1460\ncmp rbx, r12\njnz short loc_15F0\nmovsxd rbp, dword ptr [rsp+88h+var_70]\nmov edi, 400h; size\nmov r15, [rsp+88h+ptr]\ncall _malloc\nmov esi, 7Bh ; '{'\nmov [rax], si\nmov rbx, rax\ntest ebp, ebp\njle loc_1715\nlea r12, [rbp+rbp*2+0]\nlea r13, aDD; \"%d: %d, \"\nlea rax, ds:0[r12*8]\nlea rbp, [rsp+88h+var_68]\nmov r12, r15\nmov [rsp+88h+var_80], rax\nlea r14, [r15+rax]\nnop word ptr [rax+rax+00h]\nloc_1658:\nmov r9d, [r12+10h]\nmov r8d, [r12]\nmov rcx, r13\nmov rdi, rbp\nmov edx, 20h ; ' '\nmov esi, 2\nxor eax, eax\nadd r12, 18h\ncall ___sprintf_chk\nmov rdi, rbx; s\ncall _strlen\nmov edx, 400h\nmov rsi, rbp\nlea rdi, [rbx+rax]\ncall ___stpcpy_chk\ncmp r12, r14\njnz short loc_1658\nsub rax, rbx\nmov ecx, 7Dh ; '}'\nmov r12, [rsp+88h+var_80]\nlea rbp, [r15+8]\nsub eax, 2\ncdqe\nadd r12, rbp\nmov [rbx+rax], cx\nnop word ptr [rax+rax+00000000h]\nloc_16C0:\nmov rdi, [rbp+0]; ptr\nadd rbp, 18h\ncall _free\ncmp rbp, r12\njnz short loc_16C0\nloc_16D2:\nmov rdi, r15; ptr\ncall _free\nmov rax, [rsp+88h+var_40]\nsub rax, fs:28h\njnz short loc_172D\nadd rsp, 58h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1700:\nmov edi, 400h; size\ncall _malloc\nmov rbx, rax\nmov eax, 7Bh ; '{'\nmov [rbx], ax\nloc_1715:\nmov rdi, rbx; s\ncall _strlen\nmov edx, 7Dh ; '}'\nsub eax, 2\ncdqe\nmov [rbx+rax], dx\njmp short loc_16D2\nloc_172D:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_1590(unsigned int *a1, int a2)\n{\n unsigned int *v2; // rbx\n char *v3; // r15\n unsigned int *v4; // r12\n __int64 v5; // rdx\n __int64 v6; // rsi\n __int64 v7; // rbp\n char *v8; // rax\n char *v9; // rbx\n char *v10; // r12\n int v11; // r9d\n int v12; // r8d\n size_t v13; // rax\n int v14; // eax\n void **v15; // rbp\n void *v16; // rdi\n __int64 v18; // [rsp+8h] [rbp-80h]\n void *ptr; // [rsp+10h] [rbp-78h] BYREF\n __int64 v20; // [rsp+18h] [rbp-70h]\n _BYTE v21[40]; // [rsp+20h] [rbp-68h] BYREF\n unsigned __int64 v22; // [rsp+48h] [rbp-40h]\n\n v2 = a1;\n v22 = __readfsqword(0x28u);\n ptr = malloc(0xF0uLL);\n v3 = (char *)ptr;\n v20 = 0xA00000000LL;\n if ( a2 <= 0 )\n {\n v9 = (char *)malloc(0x400uLL);\n *(_WORD *)v9 = 123;\nLABEL_11:\n *(_WORD *)&v9[(int)(strlen(v9) - 2)] = 125;\n goto LABEL_9;\n }\n v4 = &a1[2 * a2];\n do\n {\n v5 = *v2;\n v6 = v2[1];\n v2 += 2;\n sub_1460(&ptr, v6, v5);\n }\n while ( v2 != v4 );\n v7 = (int)v20;\n v3 = (char *)ptr;\n v8 = (char *)malloc(0x400uLL);\n *(_WORD *)v8 = 123;\n v9 = v8;\n if ( (int)v7 <= 0 )\n goto LABEL_11;\n v10 = v3;\n v18 = 24 * v7;\n do\n {\n v11 = *((_DWORD *)v10 + 4);\n v12 = *(_DWORD *)v10;\n v10 += 24;\n __sprintf_chk(v21, 2LL, 32LL, \"%d: %d, \", v12, v11);\n v13 = strlen(v9);\n v14 = __stpcpy_chk(&v9[v13], v21, 1024LL);\n }\n while ( v10 != &v3[24 * v7] );\n v15 = (void **)(v3 + 8);\n *(_WORD *)&v9[v14 - (int)v9 - 2] = 125;\n do\n {\n v16 = *v15;\n v15 += 3;\n free(v16);\n }\n while ( v15 != (void **)&v3[v18 + 8] );\nLABEL_9:\n free(v3);\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1590(unsigned int *a1, int a2) {\n unsigned int *v2;\n char *v3;\n unsigned int *v4;\n long long v5;\n long long v6;\n long long v7;\n char *v8;\n char *v9;\n char *v10;\n int v11;\n int v12;\n unsigned int v13;\n int v14;\n void **v15;\n void *v16;\n long long v18;\n void *ptr;\n long long v20;\n uint8_t v21[40];\n unsigned long long v22;\n v2 = a1;\n v22 = __readfsqword(40u);\n ptr = malloc(240uLL);\n v3 = (char *)ptr;\n v20 = 42949672960LL;\n if (a2 <= 0) {\n v9 = (char *)malloc(1024uLL);\n *(unsigned short *)v9 = 123;\n LABEL_11:\n *(unsigned short *)&v9[(int)(strlen(v9) - 2)] = 125;\n goto LABEL_9;\n }\n v4 = &a1[2 * a2];\n do {\n v5 = *v2;\n v6 = v2[1];\n v2 += 2;\n sub_1460(&ptr, v6, v5);\n } while (v2 != v4);\n v7 = (int)v20;\n v3 = (char *)ptr;\n v8 = (char *)malloc(1024uLL);\n *(unsigned short *)v8 = 123;\n v9 = v8;\n if ((int)v7 <= 0) goto LABEL_11;\n v10 = v3;\n v18 = 24 * v7;\n do {\n v11 = *((uint32_t *)v10 + 4);\n v12 = *(uint32_t *)v10;\n v10 += 24;\n __sprintf_chk(v21, 2LL, 32LL, \"%d: %d, \", v12, v11);\n v13 = strlen(v9);\n v14 = __stpcpy_chk(&v9[v13], v21, 1024LL);\n } while (v10 != &v3[24 * v7]);\n v15 = (void **)(v3 + 8);\n *(unsigned short *)&v9[v14 - (int)v9 - 2] = 125;\n do {\n v16 = *v15;\n v15 += 3;\n free(v16);\n } while (v15 != (void **)&v3[v18 + 8]);\nLABEL_9:\n free(v3);\n return v9;\n}", + "ida_pseudo_norm": "char *func0(unsigned int *a1, int a2) {\n unsigned int *v2;\n char *v3;\n unsigned int *v4;\n long long v5;\n long long v6;\n long long v7;\n char *v8;\n char *v9;\n char *v10;\n int v11;\n int v12;\n unsigned int v13;\n int v14;\n void **v15;\n void *v16;\n long long v18;\n void *ptr;\n long long v20;\n uint8_t v21[40];\n unsigned long long v22;\n v2 = a1;\n v22 = __readfsqword(40u);\n ptr = malloc(240uLL);\n v3 = (char *)ptr;\n v20 = 42949672960LL;\n if (a2 <= 0) {\n v9 = (char *)malloc(1024uLL);\n *(unsigned short *)v9 = 123;\n LABEL_11:\n *(unsigned short *)&v9[(int)(strlen(v9) - 2)] = 125;\n goto LABEL_9;\n }\n v4 = &a1[2 * a2];\n do {\n v5 = *v2;\n v6 = v2[1];\n v2 += 2;\n add_to_map(&ptr, v6, v5);\n } while (v2 != v4);\n v7 = (int)v20;\n v3 = (char *)ptr;\n v8 = (char *)malloc(1024uLL);\n *(unsigned short *)v8 = 123;\n v9 = v8;\n if ((int)v7 <= 0) goto LABEL_11;\n v10 = v3;\n v18 = 24 * v7;\n do {\n v11 = *((uint32_t *)v10 + 4);\n v12 = *(uint32_t *)v10;\n v10 += 24;\n __sprintf_chk(v21, 2LL, 32LL, \"%d: %d, \", v12, v11);\n v13 = strlen(v9);\n v14 = __stpcpy_chk(&v9[v13], v21, 1024LL);\n } while (v10 != &v3[24 * v7]);\n v15 = (void **)(v3 + 8);\n *(unsigned short *)&v9[v14 - (int)v9 - 2] = 125;\n do {\n v16 = *v15;\n v15 += 3;\n free(v16);\n } while (v15 != (void **)&v3[v18 + 8]);\nLABEL_9:\n free(v3);\n return v9;\n}" + }, + { + "index": 709, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int key;\n\n int *values;\n\n int size;\n\n int capacity;\n\n} MapEntry;\n\n\n\ntypedef struct {\n\n MapEntry *entries;\n\n int size;\n\n int capacity;\n\n} Map;\n\n\n\nvoid init_map(Map *map) {\n\n map->entries = malloc(sizeof(MapEntry) * 10);\n\n map->size = 0;\n\n map->capacity = 10;\n\n}\n\n\n\nvoid add_to_map(Map *map, int key, int value) {\n\n for (int i = 0; i < map->size; i++) {\n\n if (map->entries[i].key == key) {\n\n for (int j = 0; j < map->entries[i].size; j++) {\n\n if (map->entries[i].values[j] == value)\n\n return;\n\n }\n\n if (map->entries[i].size == map->entries[i].capacity) {\n\n map->entries[i].capacity *= 2;\n\n map->entries[i].values = realloc(map->entries[i].values, sizeof(int) * map->entries[i].capacity);\n\n }\n\n map->entries[i].values[map->entries[i].size++] = value;\n\n return;\n\n }\n\n }\n\n if (map->size == map->capacity) {\n\n map->capacity *= 2;\n\n map->entries = realloc(map->entries, sizeof(MapEntry) * map->capacity);\n\n }\n\n map->entries[map->size].key = key;\n\n map->entries[map->size].values = malloc(sizeof(int) * 10);\n\n map->entries[map->size].values[0] = value;\n\n map->entries[map->size].size = 1;\n\n map->entries[map->size].capacity = 10;\n\n map->size++;\n\n}\n\n\n\n", + "func": "char *func0(int arr[][2], int len) {\n Map map;\n init_map(&map);\n for (int i = 0; i < len; i++) {\n add_to_map(&map, arr[i][1], arr[i][0]);\n }\n char *result = malloc(1024);\n strcpy(result, \"{\");\n for (int i = 0; i < map.size; i++) {\n char entry[32];\n sprintf(entry, \"%d: %d, \", map.entries[i].key, map.entries[i].size);\n strcat(result, entry);\n }\n int index = strlen(result) - 2;\n result[index] = '}';\n result[index + 1] = '\\0';\n for (int i = 0; i < map.size; i++) {\n free(map.entries[i].values);\n }\n free(map.entries);\n return result;\n}", + "test": "int main() {\n\n int test1[][2] = {{3, 4}, {1, 2}, {2, 4}, {8, 2}, {7, 2}, {8, 1}, {9, 1}, {8, 4}, {10, 4}};\n\n int test2[][2] = {{4, 5}, {2, 3}, {3, 5}, {9, 3}, {8, 3}, {9, 2}, {10, 2}, {9, 5}, {11, 5}};\n\n int test3[][2] = {{6, 5}, {3, 4}, {2, 6}, {11, 1}, {8, 22}, {8, 11}, {4, 3}, {14, 3}, {11, 6}};\n\n \n\n assert(strcmp(func0(test1, 9), \"{4: 4, 2: 3, 1: 2}\") == 0);\n\n assert(strcmp(func0(test2, 9), \"{5: 4, 3: 3, 2: 2}\") == 0);\n\n assert(strcmp(func0(test3, 9), \"{5: 1, 4: 1, 6: 2, 1: 1, 22: 1, 11: 1, 3: 2}\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\nmov %esi,%ebp\npush %rbx\nmov %rdi,%rbx\nmov $0xf0,%edi\nsub $0x40,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x38(%rsp)\nxor %eax,%eax\ncallq 10f0 \nmov %rax,(%rsp)\nmov %rax,%r14\nmovabs $0xa00000000,%rax\nmov %rax,0x8(%rsp)\ntest %ebp,%ebp\njle 1720 \nlea -0x1(%rbp),%eax\nmov %rsp,%rbp\nlea 0x8(%rbx,%rax,8),%r12\nnopl 0x0(%rax,%rax,1)\nmov 0x4(%rbx),%esi\nmov (%rbx),%edx\nmov %rbp,%rdi\nadd $0x8,%rbx\ncallq 1440 \ncmp %rbx,%r12\njne 15f0 \nmov 0x8(%rsp),%ebx\nmov $0x400,%edi\nmov (%rsp),%r14\ncallq 10f0 \nmov $0x7b,%edx\nmov %dx,(%rax)\nmov %rax,%r12\ntest %ebx,%ebx\njle 1737 \nxor %r13d,%r13d\nlea 0x10(%rsp),%rbx\nlea 0x9ca(%rip),%rbp\nnopw 0x0(%rax,%rax,1)\nlea 0x0(%r13,%r13,2),%rax\nmov %rbx,%rdi\nmov %rbp,%rcx\nmov $0x20,%edx\nlea (%r14,%rax,8),%rax\nmov $0x1,%esi\nmov 0x10(%rax),%r9d\nmov (%rax),%r8d\nxor %eax,%eax\ncallq 1110 <__sprintf_chk@plt>\nmov %r12,%rdi\nmov (%rdi),%edx\nadd $0x4,%rdi\nlea -0x1010101(%rdx),%eax\nnot %edx\nand %edx,%eax\nand $0x80808080,%eax\nje 166a \nmov %eax,%edx\nmov %rbx,%rsi\nshr $0x10,%edx\ntest $0x8080,%eax\ncmove %edx,%eax\nlea 0x2(%rdi),%rdx\ncmove %rdx,%rdi\nmov $0x400,%edx\nmov %eax,%ecx\nadd %al,%cl\nsbb $0x3,%rdi\nadd $0x1,%r13\ncallq 10e0 <__stpcpy_chk@plt>\nmov 0x8(%rsp),%edx\nmov (%rsp),%r14\ncmp %r13d,%edx\njg 1640 \nsub %r12,%rax\nsub $0x2,%eax\ncltq\nmovb $0x7d,(%r12,%rax,1)\nmovb $0x0,0x1(%r12,%rax,1)\ntest %edx,%edx\njle 16f4 \nxor %ebx,%ebx\nnopl (%rax)\nlea (%rbx,%rbx,2),%rax\nadd $0x1,%rbx\nmov 0x8(%r14,%rax,8),%rdi\ncallq 10b0 \nmov (%rsp),%r14\ncmp %ebx,0x8(%rsp)\njg 16d8 \nmov %r14,%rdi\ncallq 10b0 \nmov 0x38(%rsp),%rax\nxor %fs:0x28,%rax\njne 1788 \nadd $0x40,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopl 0x0(%rax)\nmov $0x400,%edi\ncallq 10f0 \nmov %rax,%r12\nmov $0x7b,%eax\nmov %ax,(%r12)\nmov %r12,%rax\nmov (%rax),%ecx\nadd $0x4,%rax\nlea -0x1010101(%rcx),%edx\nnot %ecx\nand %ecx,%edx\nand $0x80808080,%edx\nje 173a \nmov %edx,%ecx\nshr $0x10,%ecx\ntest $0x8080,%edx\ncmove %ecx,%edx\nlea 0x2(%rax),%rcx\ncmove %rcx,%rax\nmov %edx,%ecx\nadd %dl,%cl\nsbb $0x3,%rax\nsub %r12,%rax\nsub $0x2,%eax\ncltq\nmovb $0x7d,(%r12,%rax,1)\nmovb $0x0,0x1(%r12,%rax,1)\njmpq 16f4 \ncallq 10c0 <__stack_chk_fail@plt>\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\nmovsxd rbp, esi\npush rbx\nmov rbx, rdi\nmov edi, 0F0h; size\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+88h+var_40], rax\nxor eax, eax\ncall _malloc\nmov [rsp+88h+ptr], rax\nmov r15, rax\nmov rax, cs:qword_2158\nmov [rsp+88h+var_70], rax\ntest ebp, ebp\njle loc_1700\nlea r12, [rbx+rbp*8]\nlea rbp, [rsp+88h+ptr]\nnop word ptr [rax+rax+00000000h]\nloc_15F0:\nmov edx, [rbx]\nmov esi, [rbx+4]\nmov rdi, rbp\nadd rbx, 8\ncall add_to_map\ncmp rbx, r12\njnz short loc_15F0\nmovsxd rbp, dword ptr [rsp+88h+var_70]\nmov edi, 400h; size\nmov r15, [rsp+88h+ptr]\ncall _malloc\nmov esi, 7Bh ; '{'\nmov [rax], si\nmov rbx, rax\ntest ebp, ebp\njle loc_1715\nlea r12, [rbp+rbp*2+0]\nlea r13, aDD; \"%d: %d, \"\nlea rax, ds:0[r12*8]\nlea rbp, [rsp+88h+var_68]\nmov r12, r15\nmov [rsp+88h+var_80], rax\nlea r14, [r15+rax]\nnop word ptr [rax+rax+00h]\nloc_1658:\nmov r9d, [r12+10h]\nmov r8d, [r12]\nmov rcx, r13\nmov rdi, rbp\nmov edx, 20h ; ' '\nmov esi, 2\nxor eax, eax\nadd r12, 18h\ncall ___sprintf_chk\nmov rdi, rbx; s\ncall _strlen\nmov edx, 400h\nmov rsi, rbp\nlea rdi, [rbx+rax]\ncall ___stpcpy_chk\ncmp r14, r12\njnz short loc_1658\nsub rax, rbx\nmov ecx, 7Dh ; '}'\nmov r12, [rsp+88h+var_80]\nlea rbp, [r15+8]\nsub eax, 2\ncdqe\nadd r12, rbp\nmov [rbx+rax], cx\nnop word ptr [rax+rax+00000000h]\nloc_16C0:\nmov rdi, [rbp+0]; ptr\nadd rbp, 18h\ncall _free\ncmp r12, rbp\njnz short loc_16C0\nloc_16D2:\nmov rdi, r15; ptr\ncall _free\nmov rax, [rsp+88h+var_40]\nsub rax, fs:28h\njnz short loc_172D\nadd rsp, 58h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1700:\nmov edi, 400h; size\ncall _malloc\nmov rbx, rax\nmov eax, 7Bh ; '{'\nmov [rbx], ax\nloc_1715:\nmov rdi, rbx; s\ncall _strlen\nmov edx, 7Dh ; '}'\nsub eax, 2\ncdqe\nmov [rbx+rax], dx\njmp short loc_16D2\nloc_172D:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(unsigned int *a1, int a2)\n{\n unsigned int *v2; // rbx\n char *v3; // r15\n unsigned int *v4; // r12\n __int64 v5; // rdx\n __int64 v6; // rsi\n __int64 v7; // rbp\n char *v8; // rax\n char *v9; // rbx\n char *v10; // r12\n int v11; // r9d\n int v12; // r8d\n size_t v13; // rax\n int v14; // eax\n void **v15; // rbp\n void *v16; // rdi\n __int64 v18; // [rsp+8h] [rbp-80h]\n void *ptr; // [rsp+10h] [rbp-78h] BYREF\n __int64 v20; // [rsp+18h] [rbp-70h]\n _BYTE v21[40]; // [rsp+20h] [rbp-68h] BYREF\n unsigned __int64 v22; // [rsp+48h] [rbp-40h]\n\n v2 = a1;\n v22 = __readfsqword(0x28u);\n ptr = malloc(0xF0uLL);\n v3 = (char *)ptr;\n v20 = 0xA00000000LL;\n if ( a2 <= 0 )\n {\n v9 = (char *)malloc(0x400uLL);\n *(_WORD *)v9 = 123;\nLABEL_11:\n *(_WORD *)&v9[(int)(strlen(v9) - 2)] = 125;\n goto LABEL_9;\n }\n v4 = &a1[2 * a2];\n do\n {\n v5 = *v2;\n v6 = v2[1];\n v2 += 2;\n add_to_map(&ptr, v6, v5);\n }\n while ( v2 != v4 );\n v7 = (int)v20;\n v3 = (char *)ptr;\n v8 = (char *)malloc(0x400uLL);\n *(_WORD *)v8 = 123;\n v9 = v8;\n if ( (int)v7 <= 0 )\n goto LABEL_11;\n v10 = v3;\n v18 = 24 * v7;\n do\n {\n v11 = *((_DWORD *)v10 + 4);\n v12 = *(_DWORD *)v10;\n v10 += 24;\n __sprintf_chk(v21, 2LL, 32LL, \"%d: %d, \", v12, v11);\n v13 = strlen(v9);\n v14 = __stpcpy_chk(&v9[v13], v21, 1024LL);\n }\n while ( &v3[24 * v7] != v10 );\n v15 = (void **)(v3 + 8);\n *(_WORD *)&v9[v14 - (int)v9 - 2] = 125;\n do\n {\n v16 = *v15;\n v15 += 3;\n free(v16);\n }\n while ( &v3[v18 + 8] != (char *)v15 );\nLABEL_9:\n free(v3);\n return v9;\n}", + "ida_strip_asm": "sub_1590:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\nmovsxd rbp, esi\npush rbx\nmov rbx, rdi\nmov edi, 0F0h; size\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+88h+var_40], rax\nxor eax, eax\ncall _malloc\nmov [rsp+88h+ptr], rax\nmov r15, rax\nmov rax, cs:qword_2158\nmov [rsp+88h+var_70], rax\ntest ebp, ebp\njle loc_1700\nlea r12, [rbx+rbp*8]\nlea rbp, [rsp+88h+ptr]\nnop word ptr [rax+rax+00000000h]\nloc_15F0:\nmov edx, [rbx]\nmov esi, [rbx+4]\nmov rdi, rbp\nadd rbx, 8\ncall sub_1460\ncmp rbx, r12\njnz short loc_15F0\nmovsxd rbp, dword ptr [rsp+88h+var_70]\nmov edi, 400h; size\nmov r15, [rsp+88h+ptr]\ncall _malloc\nmov esi, 7Bh ; '{'\nmov [rax], si\nmov rbx, rax\ntest ebp, ebp\njle loc_1715\nlea r12, [rbp+rbp*2+0]\nlea r13, aDD; \"%d: %d, \"\nlea rax, ds:0[r12*8]\nlea rbp, [rsp+88h+var_68]\nmov r12, r15\nmov [rsp+88h+var_80], rax\nlea r14, [r15+rax]\nnop word ptr [rax+rax+00h]\nloc_1658:\nmov r9d, [r12+10h]\nmov r8d, [r12]\nmov rcx, r13\nmov rdi, rbp\nmov edx, 20h ; ' '\nmov esi, 2\nxor eax, eax\nadd r12, 18h\ncall ___sprintf_chk\nmov rdi, rbx; s\ncall _strlen\nmov edx, 400h\nmov rsi, rbp\nlea rdi, [rbx+rax]\ncall ___stpcpy_chk\ncmp r14, r12\njnz short loc_1658\nsub rax, rbx\nmov ecx, 7Dh ; '}'\nmov r12, [rsp+88h+var_80]\nlea rbp, [r15+8]\nsub eax, 2\ncdqe\nadd r12, rbp\nmov [rbx+rax], cx\nnop word ptr [rax+rax+00000000h]\nloc_16C0:\nmov rdi, [rbp+0]; ptr\nadd rbp, 18h\ncall _free\ncmp r12, rbp\njnz short loc_16C0\nloc_16D2:\nmov rdi, r15; ptr\ncall _free\nmov rax, [rsp+88h+var_40]\nsub rax, fs:28h\njnz short loc_172D\nadd rsp, 58h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1700:\nmov edi, 400h; size\ncall _malloc\nmov rbx, rax\nmov eax, 7Bh ; '{'\nmov [rbx], ax\nloc_1715:\nmov rdi, rbx; s\ncall _strlen\nmov edx, 7Dh ; '}'\nsub eax, 2\ncdqe\nmov [rbx+rax], dx\njmp short loc_16D2\nloc_172D:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_1590(unsigned int *a1, int a2)\n{\n unsigned int *v2; // rbx\n char *v3; // r15\n unsigned int *v4; // r12\n __int64 v5; // rdx\n __int64 v6; // rsi\n __int64 v7; // rbp\n char *v8; // rax\n char *v9; // rbx\n char *v10; // r12\n int v11; // r9d\n int v12; // r8d\n size_t v13; // rax\n int v14; // eax\n void **v15; // rbp\n void *v16; // rdi\n __int64 v18; // [rsp+8h] [rbp-80h]\n void *ptr; // [rsp+10h] [rbp-78h] BYREF\n __int64 v20; // [rsp+18h] [rbp-70h]\n _BYTE v21[40]; // [rsp+20h] [rbp-68h] BYREF\n unsigned __int64 v22; // [rsp+48h] [rbp-40h]\n\n v2 = a1;\n v22 = __readfsqword(0x28u);\n ptr = malloc(0xF0uLL);\n v3 = (char *)ptr;\n v20 = 0xA00000000LL;\n if ( a2 <= 0 )\n {\n v9 = (char *)malloc(0x400uLL);\n *(_WORD *)v9 = 123;\nLABEL_11:\n *(_WORD *)&v9[(int)(strlen(v9) - 2)] = 125;\n goto LABEL_9;\n }\n v4 = &a1[2 * a2];\n do\n {\n v5 = *v2;\n v6 = v2[1];\n v2 += 2;\n sub_1460(&ptr, v6, v5);\n }\n while ( v2 != v4 );\n v7 = (int)v20;\n v3 = (char *)ptr;\n v8 = (char *)malloc(0x400uLL);\n *(_WORD *)v8 = 123;\n v9 = v8;\n if ( (int)v7 <= 0 )\n goto LABEL_11;\n v10 = v3;\n v18 = 24 * v7;\n do\n {\n v11 = *((_DWORD *)v10 + 4);\n v12 = *(_DWORD *)v10;\n v10 += 24;\n __sprintf_chk(v21, 2LL, 32LL, \"%d: %d, \", v12, v11);\n v13 = strlen(v9);\n v14 = __stpcpy_chk(&v9[v13], v21, 1024LL);\n }\n while ( &v3[24 * v7] != v10 );\n v15 = (void **)(v3 + 8);\n *(_WORD *)&v9[v14 - (int)v9 - 2] = 125;\n do\n {\n v16 = *v15;\n v15 += 3;\n free(v16);\n }\n while ( &v3[v18 + 8] != (char *)v15 );\nLABEL_9:\n free(v3);\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1590(unsigned int *a1, int a2) {\n unsigned int *v2;\n char *v3;\n unsigned int *v4;\n long long v5;\n long long v6;\n long long v7;\n char *v8;\n char *v9;\n char *v10;\n int v11;\n int v12;\n unsigned int v13;\n int v14;\n void **v15;\n void *v16;\n long long v18;\n void *ptr;\n long long v20;\n uint8_t v21[40];\n unsigned long long v22;\n v2 = a1;\n v22 = __readfsqword(40u);\n ptr = malloc(240uLL);\n v3 = (char *)ptr;\n v20 = 42949672960LL;\n if (a2 <= 0) {\n v9 = (char *)malloc(1024uLL);\n *(unsigned short *)v9 = 123;\n LABEL_11:\n *(unsigned short *)&v9[(int)(strlen(v9) - 2)] = 125;\n goto LABEL_9;\n }\n v4 = &a1[2 * a2];\n do {\n v5 = *v2;\n v6 = v2[1];\n v2 += 2;\n sub_1460(&ptr, v6, v5);\n } while (v2 != v4);\n v7 = (int)v20;\n v3 = (char *)ptr;\n v8 = (char *)malloc(1024uLL);\n *(unsigned short *)v8 = 123;\n v9 = v8;\n if ((int)v7 <= 0) goto LABEL_11;\n v10 = v3;\n v18 = 24 * v7;\n do {\n v11 = *((uint32_t *)v10 + 4);\n v12 = *(uint32_t *)v10;\n v10 += 24;\n __sprintf_chk(v21, 2LL, 32LL, \"%d: %d, \", v12, v11);\n v13 = strlen(v9);\n v14 = __stpcpy_chk(&v9[v13], v21, 1024LL);\n } while (&v3[24 * v7] != v10);\n v15 = (void **)(v3 + 8);\n *(unsigned short *)&v9[v14 - (int)v9 - 2] = 125;\n do {\n v16 = *v15;\n v15 += 3;\n free(v16);\n } while (&v3[v18 + 8] != (char *)v15);\nLABEL_9:\n free(v3);\n return v9;\n}", + "ida_pseudo_norm": "char *func0(unsigned int *a1, int a2) {\n unsigned int *v2;\n char *v3;\n unsigned int *v4;\n long long v5;\n long long v6;\n long long v7;\n char *v8;\n char *v9;\n char *v10;\n int v11;\n int v12;\n unsigned int v13;\n int v14;\n void **v15;\n void *v16;\n long long v18;\n void *ptr;\n long long v20;\n uint8_t v21[40];\n unsigned long long v22;\n v2 = a1;\n v22 = __readfsqword(40u);\n ptr = malloc(240uLL);\n v3 = (char *)ptr;\n v20 = 42949672960LL;\n if (a2 <= 0) {\n v9 = (char *)malloc(1024uLL);\n *(unsigned short *)v9 = 123;\n LABEL_11:\n *(unsigned short *)&v9[(int)(strlen(v9) - 2)] = 125;\n goto LABEL_9;\n }\n v4 = &a1[2 * a2];\n do {\n v5 = *v2;\n v6 = v2[1];\n v2 += 2;\n add_to_map(&ptr, v6, v5);\n } while (v2 != v4);\n v7 = (int)v20;\n v3 = (char *)ptr;\n v8 = (char *)malloc(1024uLL);\n *(unsigned short *)v8 = 123;\n v9 = v8;\n if ((int)v7 <= 0) goto LABEL_11;\n v10 = v3;\n v18 = 24 * v7;\n do {\n v11 = *((uint32_t *)v10 + 4);\n v12 = *(uint32_t *)v10;\n v10 += 24;\n __sprintf_chk(v21, 2LL, 32LL, \"%d: %d, \", v12, v11);\n v13 = strlen(v9);\n v14 = __stpcpy_chk(&v9[v13], v21, 1024LL);\n } while (&v3[24 * v7] != v10);\n v15 = (void **)(v3 + 8);\n *(unsigned short *)&v9[v14 - (int)v9 - 2] = 125;\n do {\n v16 = *v15;\n v15 += 3;\n free(v16);\n } while (&v3[v18 + 8] != (char *)v15);\nLABEL_9:\n free(v3);\n return v9;\n}" + }, + { + "index": 710, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\ntypedef struct tuple {\n\n int first;\n\n int last;\n\n} tuple;\n\n\n\n", + "func": "tuple func0(int arr[], int n) {\n tuple res;\n res.first = arr[0];\n res.last = arr[n - 1];\n return res;\n}", + "test": "int main() {\n\n int arr1[] = {10, 4, 5, 6, 7};\n\n tuple result1 = func0(arr1, 5);\n\n assert(result1.first == 10 && result1.last == 7);\n\n\n\n int arr2[] = {1, 2, 3, 4, 5};\n\n tuple result2 = func0(arr2, 5);\n\n assert(result2.first == 1 && result2.last == 5);\n\n \n\n int arr3[] = {6, 7, 8, 9, 10};\n\n tuple result3 = func0(arr3, 5);\n\n assert(result3.first == 6 && result3.last == 10);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov -0x18(%rbp),%rax\nmov (%rax),%eax\nmov %eax,-0x8(%rbp)\nmov -0x1c(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x4(%rbp)\nmov -0x8(%rbp),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov rax, [rbp+var_18]\nmov eax, [rax]\nmov dword ptr [rbp+var_8], eax\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov dword ptr [rbp+var_8+4], eax\nmov rax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n __int64 v3; // [rsp+14h] [rbp-8h]\n\n LODWORD(v3) = *a1;\n HIDWORD(v3) = a1[a2 - 1];\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov rax, [rbp+var_18]\nmov eax, [rax]\nmov dword ptr [rbp+var_8], eax\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov dword ptr [rbp+var_8+4], eax\nmov rax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2)\n{\n __int64 v3; // [rsp+14h] [rbp-8h]\n\n LODWORD(v3) = *a1;\n HIDWORD(v3) = a1[a2 - 1];\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2) {\n long long v3;\n LODWORD(v3) = *a1;\n HIDWORD(v3) = a1[a2 - 1];\n return v3;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n long long v3;\n LODWORD(v3) = *a1;\n HIDWORD(v3) = a1[a2 - 1];\n return v3;\n}" + }, + { + "index": 711, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int n) {\n if (n < 10) {\n return false;\n }\n int prodOdd = 1, prodEven = 1;\n while (n > 0) {\n int digit = n % 10;\n prodOdd *= digit;\n n = n / 10;\n if (n == 0) {\n break;\n }\n digit = n % 10;\n prodEven *= digit;\n n = n / 10;\n }\n if (prodOdd == prodEven) {\n return true;\n }\n return false;\n}", + "test": "int main() {\n\n assert(func0(2841) == true);\n\n assert(func0(1234) == false);\n\n assert(func0(1212) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\ncmpl $0x9,-0x14(%rbp)\njg 1164 \nmov $0x0,%eax\njmpq 1248 \nmovl $0x1,-0xc(%rbp)\nmovl $0x1,-0x8(%rbp)\njmpq 1227 \nmov -0x14(%rbp),%edx\nmovslq %edx,%rax\nimul $0x66666667,%rax,%rax\nshr $0x20,%rax\nmov %eax,%ecx\nsar $0x2,%ecx\nmov %edx,%eax\nsar $0x1f,%eax\nsub %eax,%ecx\nmov %ecx,%eax\nshl $0x2,%eax\nadd %ecx,%eax\nadd %eax,%eax\nsub %eax,%edx\nmov %edx,%eax\nmov %eax,-0x4(%rbp)\nmov -0xc(%rbp),%eax\nimul -0x4(%rbp),%eax\nmov %eax,-0xc(%rbp)\nmov -0x14(%rbp),%eax\nmovslq %eax,%rdx\nimul $0x66666667,%rdx,%rdx\nshr $0x20,%rdx\nsar $0x2,%edx\nsar $0x1f,%eax\nsub %eax,%edx\nmov %edx,%eax\nmov %eax,-0x14(%rbp)\ncmpl $0x0,-0x14(%rbp)\nje 1233 \nmov -0x14(%rbp),%edx\nmovslq %edx,%rax\nimul $0x66666667,%rax,%rax\nshr $0x20,%rax\nmov %eax,%ecx\nsar $0x2,%ecx\nmov %edx,%eax\nsar $0x1f,%eax\nsub %eax,%ecx\nmov %ecx,%eax\nshl $0x2,%eax\nadd %ecx,%eax\nadd %eax,%eax\nsub %eax,%edx\nmov %edx,%eax\nmov %eax,-0x4(%rbp)\nmov -0x8(%rbp),%eax\nimul -0x4(%rbp),%eax\nmov %eax,-0x8(%rbp)\nmov -0x14(%rbp),%eax\nmovslq %eax,%rdx\nimul $0x66666667,%rdx,%rdx\nshr $0x20,%rdx\nsar $0x2,%edx\nsar $0x1f,%eax\nsub %eax,%edx\nmov %edx,%eax\nmov %eax,-0x14(%rbp)\ncmpl $0x0,-0x14(%rbp)\njg 1177 \njmp 1234 \nmov -0xc(%rbp),%eax\ncmp -0x8(%rbp),%eax\njne 1243 \nmov $0x1,%eax\njmp 1248 \nmov $0x0,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\ncmp [rbp+var_14], 9\njg short loc_1164\nmov eax, 0\njmp loc_1244\nloc_1164:\nmov [rbp+var_C], 1\nmov [rbp+var_8], 1\njmp loc_1223\nloc_1177:\nmov edx, [rbp+var_14]\nmovsxd rax, edx\nimul rax, 66666667h\nshr rax, 20h\nmov ecx, eax\nsar ecx, 2\nmov eax, edx\nsar eax, 1Fh\nsub ecx, eax\nmov eax, ecx\nshl eax, 2\nadd eax, ecx\nadd eax, eax\nsub edx, eax\nmov [rbp+var_4], edx\nmov eax, [rbp+var_C]\nimul eax, [rbp+var_4]\nmov [rbp+var_C], eax\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_14], eax\ncmp [rbp+var_14], 0\njz short loc_122F\nmov edx, [rbp+var_14]\nmovsxd rax, edx\nimul rax, 66666667h\nshr rax, 20h\nmov ecx, eax\nsar ecx, 2\nmov eax, edx\nsar eax, 1Fh\nsub ecx, eax\nmov eax, ecx\nshl eax, 2\nadd eax, ecx\nadd eax, eax\nsub edx, eax\nmov [rbp+var_4], edx\nmov eax, [rbp+var_8]\nimul eax, [rbp+var_4]\nmov [rbp+var_8], eax\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_14], eax\nloc_1223:\ncmp [rbp+var_14], 0\njg loc_1177\njmp short loc_1230\nloc_122F:\nnop\nloc_1230:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_8]\njnz short loc_123F\nmov eax, 1\njmp short loc_1244\nloc_123F:\nmov eax, 0\nloc_1244:\npop rbp\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(int a1)\n{\n int v2; // [rsp+0h] [rbp-14h]\n int v3; // [rsp+0h] [rbp-14h]\n int v4; // [rsp+8h] [rbp-Ch]\n int v5; // [rsp+Ch] [rbp-8h]\n\n v2 = a1;\n if ( a1 <= 9 )\n return 0LL;\n v4 = 1;\n v5 = 1;\n while ( v2 > 0 )\n {\n v4 *= v2 % 10;\n v3 = v2 / 10;\n if ( !v3 )\n break;\n v5 *= v3 % 10;\n v2 = v3 / 10;\n }\n return v4 == v5;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\ncmp [rbp+var_14], 9\njg short loc_1164\nmov eax, 0\njmp loc_1244\nloc_1164:\nmov [rbp+var_C], 1\nmov [rbp+var_8], 1\njmp loc_1223\nloc_1177:\nmov edx, [rbp+var_14]\nmovsxd rax, edx\nimul rax, 66666667h\nshr rax, 20h\nmov ecx, eax\nsar ecx, 2\nmov eax, edx\nsar eax, 1Fh\nsub ecx, eax\nmov eax, ecx\nshl eax, 2\nadd eax, ecx\nadd eax, eax\nsub edx, eax\nmov [rbp+var_4], edx\nmov eax, [rbp+var_C]\nimul eax, [rbp+var_4]\nmov [rbp+var_C], eax\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_14], eax\ncmp [rbp+var_14], 0\njz short loc_122F\nmov edx, [rbp+var_14]\nmovsxd rax, edx\nimul rax, 66666667h\nshr rax, 20h\nmov ecx, eax\nsar ecx, 2\nmov eax, edx\nsar eax, 1Fh\nsub ecx, eax\nmov eax, ecx\nshl eax, 2\nadd eax, ecx\nadd eax, eax\nsub edx, eax\nmov [rbp+var_4], edx\nmov eax, [rbp+var_8]\nimul eax, [rbp+var_4]\nmov [rbp+var_8], eax\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_14], eax\nloc_1223:\ncmp [rbp+var_14], 0\njg loc_1177\njmp short loc_1230\nloc_122F:\nnop\nloc_1230:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_8]\njnz short loc_123F\nmov eax, 1\njmp short loc_1244\nloc_123F:\nmov eax, 0\nloc_1244:\npop rbp\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1149(int a1)\n{\n int v2; // [rsp+0h] [rbp-14h]\n int v3; // [rsp+0h] [rbp-14h]\n int v4; // [rsp+8h] [rbp-Ch]\n int v5; // [rsp+Ch] [rbp-8h]\n\n v2 = a1;\n if ( a1 <= 9 )\n return 0LL;\n v4 = 1;\n v5 = 1;\n while ( v2 > 0 )\n {\n v4 *= v2 % 10;\n v3 = v2 / 10;\n if ( !v3 )\n break;\n v5 *= v3 % 10;\n v2 = v3 / 10;\n }\n return v4 == v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1149(int a1) {\n int v2;\n int v3;\n int v4;\n int v5;\n v2 = a1;\n if (a1 <= 9) return 0LL;\n v4 = 1;\n v5 = 1;\n while (v2 > 0) {\n v4 *= v2 % 10;\n v3 = v2 / 10;\n if (!v3) break;\n v5 *= v3 % 10;\n v2 = v3 / 10;\n }\n return v4 == v5;\n}", + "ida_pseudo_norm": "uint8_t func0(int a1) {\n int v2;\n int v3;\n int v4;\n int v5;\n v2 = a1;\n if (a1 <= 9) return 0LL;\n v4 = 1;\n v5 = 1;\n while (v2 > 0) {\n v4 *= v2 % 10;\n v3 = v2 / 10;\n if (!v3) break;\n v5 *= v3 % 10;\n v2 = v3 / 10;\n }\n return v4 == v5;\n}" + }, + { + "index": 711, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int n) {\n if (n < 10) {\n return false;\n }\n int prodOdd = 1, prodEven = 1;\n while (n > 0) {\n int digit = n % 10;\n prodOdd *= digit;\n n = n / 10;\n if (n == 0) {\n break;\n }\n digit = n % 10;\n prodEven *= digit;\n n = n / 10;\n }\n if (prodOdd == prodEven) {\n return true;\n }\n return false;\n}", + "test": "int main() {\n\n assert(func0(2841) == true);\n\n assert(func0(1234) == false);\n\n assert(func0(1212) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x0,%eax\ncmp $0x9,%edi\njle 11cf \nmovslq %edi,%rsi\nimul $0x66666667,%rsi,%rsi\nsar $0x22,%rsi\nmov %edi,%eax\nsar $0x1f,%eax\nsub %eax,%esi\nmov %esi,%ecx\nlea (%rsi,%rsi,4),%eax\nadd %eax,%eax\nmov %edi,%esi\nsub %eax,%esi\nmov $0x1,%edi\nmovslq %ecx,%rax\nimul $0x66666667,%rax,%rax\nsar $0x22,%rax\nmov %ecx,%edx\nsar $0x1f,%edx\nsub %edx,%eax\nlea (%rax,%rax,4),%edx\nadd %edx,%edx\nmov %ecx,%r8d\nsub %edx,%r8d\nimul %r8d,%edi\ncmp $0x9,%ecx\njle 11ca \nmovslq %eax,%rdx\nimul $0x66666667,%rdx,%rdx\nsar $0x22,%rdx\nmov %eax,%ecx\nsar $0x1f,%ecx\nsub %ecx,%edx\nlea (%rdx,%rdx,4),%ecx\nadd %ecx,%ecx\nsub %ecx,%eax\nimul %eax,%esi\nmov %edx,%ecx\ntest %edx,%edx\njne 117c \ncmp %edi,%esi\nsete %al\nretq\n", + "ida_asm": "func0:\nendbr64\nmov eax, 0\ncmp edi, 9\njle short locret_11CF\nmovsxd rsi, edi\nimul rsi, 66666667h\nsar rsi, 22h\nmov eax, edi\nsar eax, 1Fh\nsub esi, eax\nmov ecx, esi\nlea eax, [rsi+rsi*4]\nadd eax, eax\nmov esi, edi\nsub esi, eax\nmov edi, 1\nloc_117C:\nmovsxd rax, ecx\nimul rax, 66666667h\nsar rax, 22h\nmov edx, ecx\nsar edx, 1Fh\nsub eax, edx\nlea edx, [rax+rax*4]\nadd edx, edx\nmov r8d, ecx\nsub r8d, edx\nimul edi, r8d\ncmp ecx, 9\njle short loc_11CA\nmovsxd rdx, eax\nimul rdx, 66666667h\nsar rdx, 22h\nmov ecx, eax\nsar ecx, 1Fh\nsub edx, ecx\nlea ecx, [rdx+rdx*4]\nadd ecx, ecx\nsub eax, ecx\nimul esi, eax\nmov ecx, edx\ntest edx, edx\njnz short loc_117C\nloc_11CA:\ncmp esi, edi\nsetz al\nlocret_11CF:\nretn", + "ida_pseudo": "bool __fastcall func0(int a1)\n{\n bool result; // al\n int v2; // ecx\n int v3; // esi\n int v4; // edi\n int v5; // eax\n\n result = 0;\n if ( a1 > 9 )\n {\n v2 = a1 / 10;\n v3 = a1 % 10;\n v4 = 1;\n do\n {\n v5 = v2 / 10;\n v4 *= v2 % 10;\n if ( v2 <= 9 )\n break;\n v3 *= v5 % 10;\n v2 = v5 / 10;\n }\n while ( v5 / 10 );\n return v3 == v4;\n }\n return result;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmov eax, 0\ncmp edi, 9\njle short locret_11CF\nmovsxd rsi, edi\nimul rsi, 66666667h\nsar rsi, 22h\nmov eax, edi\nsar eax, 1Fh\nsub esi, eax\nmov ecx, esi\nlea eax, [rsi+rsi*4]\nadd eax, eax\nmov esi, edi\nsub esi, eax\nmov edi, 1\nloc_117C:\nmovsxd rax, ecx\nimul rax, 66666667h\nsar rax, 22h\nmov edx, ecx\nsar edx, 1Fh\nsub eax, edx\nlea edx, [rax+rax*4]\nadd edx, edx\nmov r8d, ecx\nsub r8d, edx\nimul edi, r8d\ncmp ecx, 9\njle short loc_11CA\nmovsxd rdx, eax\nimul rdx, 66666667h\nsar rdx, 22h\nmov ecx, eax\nsar ecx, 1Fh\nsub edx, ecx\nlea ecx, [rdx+rdx*4]\nadd ecx, ecx\nsub eax, ecx\nimul esi, eax\nmov ecx, edx\ntest edx, edx\njnz short loc_117C\nloc_11CA:\ncmp esi, edi\nsetz al\nlocret_11CF:\nretn", + "ida_strip_pseudo": "bool __fastcall sub_1149(int a1)\n{\n bool result; // al\n int v2; // ecx\n int v3; // esi\n int v4; // edi\n int v5; // eax\n\n result = 0;\n if ( a1 > 9 )\n {\n v2 = a1 / 10;\n v3 = a1 % 10;\n v4 = 1;\n do\n {\n v5 = v2 / 10;\n v4 *= v2 % 10;\n if ( v2 <= 9 )\n break;\n v3 *= v5 % 10;\n v2 = v5 / 10;\n }\n while ( v5 / 10 );\n return v3 == v4;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_1149(int a1) {\n bool result;\n int v2;\n int v3;\n int v4;\n int v5;\n result = 0;\n if (a1 > 9) {\n v2 = a1 / 10;\n v3 = a1 % 10;\n v4 = 1;\n do {\n v5 = v2 / 10;\n v4 *= v2 % 10;\n if (v2 <= 9) break;\n v3 *= v5 % 10;\n v2 = v5 / 10;\n } while (v5 / 10);\n return v3 == v4;\n }\n return result;\n}", + "ida_pseudo_norm": "bool func0(int a1) {\n bool result;\n int v2;\n int v3;\n int v4;\n int v5;\n result = 0;\n if (a1 > 9) {\n v2 = a1 / 10;\n v3 = a1 % 10;\n v4 = 1;\n do {\n v5 = v2 / 10;\n v4 *= v2 % 10;\n if (v2 <= 9) break;\n v3 *= v5 % 10;\n v2 = v5 / 10;\n } while (v5 / 10);\n return v3 == v4;\n }\n return result;\n}" + }, + { + "index": 711, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int n) {\n if (n < 10) {\n return false;\n }\n int prodOdd = 1, prodEven = 1;\n while (n > 0) {\n int digit = n % 10;\n prodOdd *= digit;\n n = n / 10;\n if (n == 0) {\n break;\n }\n digit = n % 10;\n prodEven *= digit;\n n = n / 10;\n }\n if (prodOdd == prodEven) {\n return true;\n }\n return false;\n}", + "test": "int main() {\n\n assert(func0(2841) == true);\n\n assert(func0(1234) == false);\n\n assert(func0(1212) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x9,%edi\njle 1290 \njmpq 11f0 \nxchg %ax,%ax\nxor %eax,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0_part_0:\ntest edi, edi\njz short loc_1266\nmovsxd rsi, edi\nmov eax, edi\nmov r8d, 0CCCCCCCDh\nimul rsi, 66666667h\nsar eax, 1Fh\nsar rsi, 22h\nsub esi, eax\nlea edx, [rsi+rsi*4]\nmov eax, esi\nmov esi, edi\nmov edi, 1\nadd edx, edx\nsub esi, edx\ntest eax, eax\njnz short loc_1240\njmp short loc_126C\nloc_1228:\nmov eax, edx\nimul rax, r8\nshr rax, 23h\nlea ecx, [rax+rax*4]\nadd ecx, ecx\nsub edx, ecx\nimul esi, edx\ntest eax, eax\njz short loc_1260\nloc_1240:\nmov edx, eax\nimul rdx, r8\nshr rdx, 23h\nlea ecx, [rdx+rdx*4]\nadd ecx, ecx\nsub eax, ecx\nimul edi, eax\ntest edx, edx\njnz short loc_1228\ncmp edi, esi\nsetz al\nretn\nloc_1260:\ncmp esi, edi\nsetz al\nretn\nloc_1266:\nmov eax, 1\nretn\nloc_126C:\ncmp esi, 1\nsetz al\nretn", + "ida_pseudo": "bool __fastcall func0_part_0(int a1)\n{\n int v1; // edx\n unsigned int v2; // eax\n int v4; // edi\n int v5; // esi\n unsigned int v6; // edx\n int v7; // eax\n\n if ( a1 )\n {\n v1 = 5 * (a1 / 10);\n v2 = a1 / 10;\n v4 = 1;\n v5 = a1 - 2 * v1;\n if ( v2 )\n {\n do\n {\n v6 = v2 / 0xA;\n v4 *= v2 % 0xA;\n if ( !(v2 / 0xA) )\n {\n LOBYTE(v7) = v4 == v5;\n return v7;\n }\n v2 = v6 / 0xA;\n v5 *= v6 % 0xA;\n }\n while ( v6 / 0xA );\n LOBYTE(v7) = v5 == v4;\n }\n else\n {\n return v5 == 1;\n }\n }\n else\n {\n LOBYTE(v7) = 1;\n }\n return v7;\n}", + "ida_strip_asm": "sub_11F0:\ntest edi, edi\njz short loc_1266\nmovsxd rsi, edi\nmov eax, edi\nmov r8d, 0CCCCCCCDh\nimul rsi, 66666667h\nsar eax, 1Fh\nsar rsi, 22h\nsub esi, eax\nlea edx, [rsi+rsi*4]\nmov eax, esi\nmov esi, edi\nmov edi, 1\nadd edx, edx\nsub esi, edx\ntest eax, eax\njnz short loc_1240\njmp short loc_126C\nloc_1228:\nmov eax, edx\nimul rax, r8\nshr rax, 23h\nlea ecx, [rax+rax*4]\nadd ecx, ecx\nsub edx, ecx\nimul esi, edx\ntest eax, eax\njz short loc_1260\nloc_1240:\nmov edx, eax\nimul rdx, r8\nshr rdx, 23h\nlea ecx, [rdx+rdx*4]\nadd ecx, ecx\nsub eax, ecx\nimul edi, eax\ntest edx, edx\njnz short loc_1228\ncmp edi, esi\nsetz al\nretn\nloc_1260:\ncmp esi, edi\nsetz al\nretn\nloc_1266:\nmov eax, 1\nretn\nloc_126C:\ncmp esi, 1\nsetz al\nretn", + "ida_strip_pseudo": "bool __fastcall sub_11F0(int a1)\n{\n int v1; // edx\n unsigned int v2; // eax\n int v4; // edi\n int v5; // esi\n unsigned int v6; // edx\n int v7; // eax\n\n if ( a1 )\n {\n v1 = 5 * (a1 / 10);\n v2 = a1 / 10;\n v4 = 1;\n v5 = a1 - 2 * v1;\n if ( v2 )\n {\n do\n {\n v6 = v2 / 0xA;\n v4 *= v2 % 0xA;\n if ( !(v2 / 0xA) )\n {\n LOBYTE(v7) = v4 == v5;\n return v7;\n }\n v2 = v6 / 0xA;\n v5 *= v6 % 0xA;\n }\n while ( v6 / 0xA );\n LOBYTE(v7) = v5 == v4;\n }\n else\n {\n return v5 == 1;\n }\n }\n else\n {\n LOBYTE(v7) = 1;\n }\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_11F0(int a1) {\n int v1;\n unsigned int v2;\n int v4;\n int v5;\n unsigned int v6;\n int v7;\n if (a1) {\n v1 = 5 * (a1 / 10);\n v2 = a1 / 10;\n v4 = 1;\n v5 = a1 - 2 * v1;\n if (v2) {\n do {\n v6 = v2 / 10;\n v4 *= v2 % 10;\n if (!(v2 / 10)) {\n LOBYTE(v7) = v4 == v5;\n return v7;\n }\n v2 = v6 / 10;\n v5 *= v6 % 10;\n } while (v6 / 10);\n LOBYTE(v7) = v5 == v4;\n } else {\n return v5 == 1;\n }\n } else {\n LOBYTE(v7) = 1;\n }\n return v7;\n}", + "ida_pseudo_norm": "bool func0_part_0(int a1) {\n int v1;\n unsigned int v2;\n int v4;\n int v5;\n unsigned int v6;\n int v7;\n if (a1) {\n v1 = 5 * (a1 / 10);\n v2 = a1 / 10;\n v4 = 1;\n v5 = a1 - 2 * v1;\n if (v2) {\n do {\n v6 = v2 / 10;\n v4 *= v2 % 10;\n if (!(v2 / 10)) {\n LOBYTE(v7) = v4 == v5;\n return v7;\n }\n v2 = v6 / 10;\n v5 *= v6 % 10;\n } while (v6 / 10);\n LOBYTE(v7) = v5 == v4;\n } else {\n return v5 == 1;\n }\n } else {\n LOBYTE(v7) = 1;\n }\n return v7;\n}" + }, + { + "index": 711, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int n) {\n if (n < 10) {\n return false;\n }\n int prodOdd = 1, prodEven = 1;\n while (n > 0) {\n int digit = n % 10;\n prodOdd *= digit;\n n = n / 10;\n if (n == 0) {\n break;\n }\n digit = n % 10;\n prodEven *= digit;\n n = n / 10;\n }\n if (prodOdd == prodEven) {\n return true;\n }\n return false;\n}", + "test": "int main() {\n\n assert(func0(2841) == true);\n\n assert(func0(1234) == false);\n\n assert(func0(1212) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nxor %eax,%eax\ncmp $0x9,%edi\njle 1300 \nmovslq %edi,%rsi\nmov %edi,%eax\nmov $0xcccccccd,%r8d\nimul $0x66666667,%rsi,%rsi\nsar $0x1f,%eax\nsar $0x22,%rsi\nsub %eax,%esi\nlea (%rsi,%rsi,4),%edx\nmov %esi,%eax\nmov %edi,%esi\nmov $0x1,%edi\nadd %edx,%edx\nsub %edx,%esi\njmp 12d8 \nnopl 0x0(%rax,%rax,1)\nmov %edx,%eax\nimul %r8,%rax\nshr $0x23,%rax\nlea (%rax,%rax,4),%ecx\nadd %ecx,%ecx\nsub %ecx,%edx\nimul %edx,%esi\ntest %eax,%eax\nje 12f0 \nmov %eax,%edx\nimul %r8,%rdx\nshr $0x23,%rdx\nlea (%rdx,%rdx,4),%ecx\nadd %ecx,%ecx\nsub %ecx,%eax\nimul %eax,%edi\ntest %edx,%edx\njne 12c0 \ncmp %edi,%esi\nsete %al\nretq\nnopw %cs:0x0(%rax,%rax,1)\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0_part_0:\ntest edi, edi\njz short loc_1266\nmovsxd rsi, edi\nmov eax, edi\nmov r8d, 0CCCCCCCDh\nimul rsi, 66666667h\nsar eax, 1Fh\nsar rsi, 22h\nsub esi, eax\nlea edx, [rsi+rsi*4]\nmov eax, esi\nmov esi, edi\nmov edi, 1\nadd edx, edx\nsub esi, edx\ntest eax, eax\njnz short loc_1240\njmp short loc_126C\nloc_1228:\nmov eax, edx\nimul rax, r8\nshr rax, 23h\nlea ecx, [rax+rax*4]\nadd ecx, ecx\nsub edx, ecx\nimul esi, edx\ntest eax, eax\njz short loc_1260\nloc_1240:\nmov edx, eax\nimul rdx, r8\nshr rdx, 23h\nlea ecx, [rdx+rdx*4]\nadd ecx, ecx\nsub eax, ecx\nimul edi, eax\ntest edx, edx\njnz short loc_1228\ncmp edi, esi\nsetz al\nretn\nloc_1260:\ncmp esi, edi\nsetz al\nretn\nloc_1266:\nmov eax, 1\nretn\nloc_126C:\ncmp esi, 1\nsetz al\nretn", + "ida_pseudo": "bool __fastcall func0_part_0(int a1)\n{\n int v1; // edx\n unsigned int v2; // eax\n int v4; // edi\n int v5; // esi\n unsigned int v6; // edx\n int v7; // eax\n\n if ( a1 )\n {\n v1 = 5 * (a1 / 10);\n v2 = a1 / 10;\n v4 = 1;\n v5 = a1 - 2 * v1;\n if ( v2 )\n {\n do\n {\n v6 = v2 / 0xA;\n v4 *= v2 % 0xA;\n if ( !(v2 / 0xA) )\n {\n LOBYTE(v7) = v4 == v5;\n return v7;\n }\n v2 = v6 / 0xA;\n v5 *= v6 % 0xA;\n }\n while ( v6 / 0xA );\n LOBYTE(v7) = v5 == v4;\n }\n else\n {\n return v5 == 1;\n }\n }\n else\n {\n LOBYTE(v7) = 1;\n }\n return v7;\n}", + "ida_strip_asm": "sub_11F0:\ntest edi, edi\njz short loc_1266\nmovsxd rsi, edi\nmov eax, edi\nmov r8d, 0CCCCCCCDh\nimul rsi, 66666667h\nsar eax, 1Fh\nsar rsi, 22h\nsub esi, eax\nlea edx, [rsi+rsi*4]\nmov eax, esi\nmov esi, edi\nmov edi, 1\nadd edx, edx\nsub esi, edx\ntest eax, eax\njnz short loc_1240\njmp short loc_126C\nloc_1228:\nmov eax, edx\nimul rax, r8\nshr rax, 23h\nlea ecx, [rax+rax*4]\nadd ecx, ecx\nsub edx, ecx\nimul esi, edx\ntest eax, eax\njz short loc_1260\nloc_1240:\nmov edx, eax\nimul rdx, r8\nshr rdx, 23h\nlea ecx, [rdx+rdx*4]\nadd ecx, ecx\nsub eax, ecx\nimul edi, eax\ntest edx, edx\njnz short loc_1228\ncmp edi, esi\nsetz al\nretn\nloc_1260:\ncmp esi, edi\nsetz al\nretn\nloc_1266:\nmov eax, 1\nretn\nloc_126C:\ncmp esi, 1\nsetz al\nretn", + "ida_strip_pseudo": "bool __fastcall sub_11F0(int a1)\n{\n int v1; // edx\n unsigned int v2; // eax\n int v4; // edi\n int v5; // esi\n unsigned int v6; // edx\n int v7; // eax\n\n if ( a1 )\n {\n v1 = 5 * (a1 / 10);\n v2 = a1 / 10;\n v4 = 1;\n v5 = a1 - 2 * v1;\n if ( v2 )\n {\n do\n {\n v6 = v2 / 0xA;\n v4 *= v2 % 0xA;\n if ( !(v2 / 0xA) )\n {\n LOBYTE(v7) = v4 == v5;\n return v7;\n }\n v2 = v6 / 0xA;\n v5 *= v6 % 0xA;\n }\n while ( v6 / 0xA );\n LOBYTE(v7) = v5 == v4;\n }\n else\n {\n return v5 == 1;\n }\n }\n else\n {\n LOBYTE(v7) = 1;\n }\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_11F0(int a1) {\n int v1;\n unsigned int v2;\n int v4;\n int v5;\n unsigned int v6;\n int v7;\n if (a1) {\n v1 = 5 * (a1 / 10);\n v2 = a1 / 10;\n v4 = 1;\n v5 = a1 - 2 * v1;\n if (v2) {\n do {\n v6 = v2 / 10;\n v4 *= v2 % 10;\n if (!(v2 / 10)) {\n LOBYTE(v7) = v4 == v5;\n return v7;\n }\n v2 = v6 / 10;\n v5 *= v6 % 10;\n } while (v6 / 10);\n LOBYTE(v7) = v5 == v4;\n } else {\n return v5 == 1;\n }\n } else {\n LOBYTE(v7) = 1;\n }\n return v7;\n}", + "ida_pseudo_norm": "bool func0_part_0(int a1) {\n int v1;\n unsigned int v2;\n int v4;\n int v5;\n unsigned int v6;\n int v7;\n if (a1) {\n v1 = 5 * (a1 / 10);\n v2 = a1 / 10;\n v4 = 1;\n v5 = a1 - 2 * v1;\n if (v2) {\n do {\n v6 = v2 / 10;\n v4 *= v2 % 10;\n if (!(v2 / 10)) {\n LOBYTE(v7) = v4 == v5;\n return v7;\n }\n v2 = v6 / 10;\n v5 *= v6 % 10;\n } while (v6 / 10);\n LOBYTE(v7) = v5 == v4;\n } else {\n return v5 == 1;\n }\n } else {\n LOBYTE(v7) = 1;\n }\n return v7;\n}" + }, + { + "index": 712, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n// Function to compare integer arrays\n\nint compare_int_arrays(const void *a, const void *b) {\n\n int *arr1 = *(int **)a;\n\n int *arr2 = *(int **)b;\n\n size_t len1 = arr1[0];\n\n size_t len2 = arr2[0];\n\n if (len1 != len2) return len1 - len2;\n\n for (size_t i = 1; i <= len1; i++) {\n\n if (arr1[i] != arr2[i]) return arr1[i] - arr2[i];\n\n }\n\n return 0;\n\n}\n\n\n\n// Function to remove duplicates from list of integer arrays\n\nint** remove_duplicate_lists(int **list, size_t *new_size) {\n\n qsort(list, *new_size, sizeof(int*), compare_int_arrays);\n\n size_t unique = 0;\n\n for (size_t i = 1; i < *new_size; i++) {\n\n if (compare_int_arrays(&list[unique], &list[i]) != 0) {\n\n unique++;\n\n list[unique] = list[i];\n\n }\n\n }\n\n *new_size = unique + 1;\n\n return list;\n\n}\n\n\n\n// Function to compare strings\n\nint compare_strings(const void *a, const void *b) {\n\n char *const *sa = a;\n\n char *const *sb = b;\n\n return strcmp(*sa, *sb);\n\n}\n\n\n\n// Function to remove duplicates from strings\n\nchar** remove_duplicate_strings(char **list, size_t *new_size) {\n\n qsort(list, *new_size, sizeof(char*), compare_strings);\n\n size_t unique = 0;\n\n for (size_t i = 1; i < *new_size; i++) {\n\n if (strcmp(list[unique], list[i]) != 0) {\n\n unique++;\n\n list[unique] = list[i];\n\n }\n\n }\n\n *new_size = unique + 1;\n\n return list;\n\n}\n\n\n\n// Function to compare integers\n\nint compare_ints(const void *a, const void *b) {\n\n int ia = *(int*)a;\n\n int ib = *(int*)b;\n\n return ia - ib;\n\n}\n\n\n\n// Function to remove duplicates from integers\n\n", + "func": "int *func0(int *list, size_t *new_size) {\n qsort(list, *new_size, sizeof(int), compare_ints);\n size_t unique = 0;\n for (size_t i = 1; i < *new_size; i++) {\n if (list[unique] != list[i]) {\n unique++;\n list[unique] = list[i];\n }\n }\n *new_size = unique + 1;\n return list;\n}", + "test": "int main() {\n\n // Test case 1: List of integer arrays\n\n int list1_item1[] = {2, 10, 20};\n\n int list1_item2[] = {1, 40};\n\n int list1_item3[] = {3, 25, 30, 56};\n\n int list1_item4[] = {2, 10, 20};\n\n int list1_item5[] = {1, 33};\n\n int list1_item6[] = {1, 40};\n\n int* list1[] = {list1_item1, list1_item2, list1_item3, list1_item4, list1_item5, list1_item6};\n\n size_t size1 = 6;\n\n remove_duplicate_lists(list1, &size1);\n\n // Expected [[10, 20], [25, 30, 56], [33], [40]]\n\n // Skipping deep comparison for simplicity\n\n assert(size1 == 4);\n\n\n\n // Test case 2: List of strings\n\n char *list2[] = {\"a\", \"b\", \"a\", \"c\", \"c\"};\n\n size_t size2 = 5;\n\n remove_duplicate_strings(list2, &size2);\n\n assert(size2 == 3);\n\n assert(strcmp(list2[0], \"a\") == 0);\n\n assert(strcmp(list2[1], \"b\") == 0);\n\n assert(strcmp(list2[2], \"c\") == 0);\n\n\n\n // Test case 3: List of integers\n\n int list3[] = {1, 3, 5, 6, 3, 5, 6, 1};\n\n size_t size3 = 8;\n\n func0(list3, &size3);\n\n assert(size3 == 4);\n\n assert(list3[0] == 1);\n\n assert(list3[1] == 3);\n\n assert(list3[2] == 5);\n\n assert(list3[3] == 6);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov -0x20(%rbp),%rax\nmov (%rax),%rsi\nmov -0x18(%rbp),%rax\nlea -0x50(%rip),%rcx\nmov $0x4,%edx\nmov %rax,%rdi\ncallq 1080 \nmovq $0x0,-0x10(%rbp)\nmovq $0x1,-0x8(%rbp)\njmp 1539 \nmov -0x10(%rbp),%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x8(%rbp),%rax\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\nje 1534 \naddq $0x1,-0x10(%rbp)\nmov -0x8(%rbp),%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0x10(%rbp),%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddq $0x1,-0x8(%rbp)\nmov -0x20(%rbp),%rax\nmov (%rax),%rax\ncmp %rax,-0x8(%rbp)\njb 14d7 \nmov -0x10(%rbp),%rax\nlea 0x1(%rax),%rdx\nmov -0x20(%rbp),%rax\nmov %rdx,(%rax)\nmov -0x18(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+base], rdi\nmov [rbp+var_20], rsi\nmov rax, [rbp+var_20]\nmov rsi, [rax]; nmemb\nmov rax, [rbp+base]\nlea rdx, compare_ints\nmov rcx, rdx; compar\nmov edx, 4; size\nmov rdi, rax; base\ncall _qsort\nmov [rbp+var_10], 0\nmov [rbp+var_8], 1\njmp short loc_1542\nloc_14E0:\nmov rax, [rbp+var_10]\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_8]\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_153D\nadd [rbp+var_10], 1\nmov rax, [rbp+var_8]\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rdx\nmov rdx, [rbp+var_10]\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+base]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nloc_153D:\nadd [rbp+var_8], 1\nloc_1542:\nmov rax, [rbp+var_20]\nmov rax, [rax]\ncmp [rbp+var_8], rax\njb short loc_14E0\nmov rax, [rbp+var_10]\nlea rdx, [rax+1]\nmov rax, [rbp+var_20]\nmov [rax], rdx\nmov rax, [rbp+base]\nleave\nretn", + "ida_pseudo": "void *__fastcall func0(void *a1, size_t *a2)\n{\n __int64 v3; // [rsp+10h] [rbp-10h]\n unsigned __int64 i; // [rsp+18h] [rbp-8h]\n\n qsort(a1, *a2, 4uLL, compare_ints);\n v3 = 0LL;\n for ( i = 1LL; i < *a2; ++i )\n {\n if ( *((_DWORD *)a1 + v3) != *((_DWORD *)a1 + i) )\n {\n ++v3;\n *((_DWORD *)a1 + v3) = *((_DWORD *)a1 + i);\n }\n }\n *a2 = v3 + 1;\n return a1;\n}", + "ida_strip_asm": "sub_1498:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+base], rdi\nmov [rbp+var_20], rsi\nmov rax, [rbp+var_20]\nmov rsi, [rax]; nmemb\nmov rax, [rbp+base]\nlea rdx, sub_146E\nmov rcx, rdx; compar\nmov edx, 4; size\nmov rdi, rax; base\ncall _qsort\nmov [rbp+var_10], 0\nmov [rbp+var_8], 1\njmp short loc_1542\nloc_14E0:\nmov rax, [rbp+var_10]\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_8]\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_153D\nadd [rbp+var_10], 1\nmov rax, [rbp+var_8]\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rdx\nmov rdx, [rbp+var_10]\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+base]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nloc_153D:\nadd [rbp+var_8], 1\nloc_1542:\nmov rax, [rbp+var_20]\nmov rax, [rax]\ncmp [rbp+var_8], rax\njb short loc_14E0\nmov rax, [rbp+var_10]\nlea rdx, [rax+1]\nmov rax, [rbp+var_20]\nmov [rax], rdx\nmov rax, [rbp+base]\nleave\nretn", + "ida_strip_pseudo": "void *__fastcall sub_1498(void *a1, size_t *a2)\n{\n __int64 v3; // [rsp+10h] [rbp-10h]\n unsigned __int64 i; // [rsp+18h] [rbp-8h]\n\n qsort(a1, *a2, 4uLL, sub_146E);\n v3 = 0LL;\n for ( i = 1LL; i < *a2; ++i )\n {\n if ( *((_DWORD *)a1 + v3) != *((_DWORD *)a1 + i) )\n {\n ++v3;\n *((_DWORD *)a1 + v3) = *((_DWORD *)a1 + i);\n }\n }\n *a2 = v3 + 1;\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1498(void *a1, unsigned int *a2) {\n long long v3;\n unsigned long long i;\n qsort(a1, *a2, 4uLL, sub_146E);\n v3 = 0LL;\n for (i = 1LL; i < *a2; ++i) {\n if (*((uint32_t *)a1 + v3) != *((uint32_t *)a1 + i)) {\n ++v3;\n *((uint32_t *)a1 + v3) = *((uint32_t *)a1 + i);\n }\n }\n *a2 = v3 + 1;\n return a1;\n}", + "ida_pseudo_norm": "void *func0(void *a1, unsigned int *a2) {\n long long v3;\n unsigned long long i;\n qsort(a1, *a2, 4uLL, compare_ints);\n v3 = 0LL;\n for (i = 1LL; i < *a2; ++i) {\n if (*((uint32_t *)a1 + v3) != *((uint32_t *)a1 + i)) {\n ++v3;\n *((uint32_t *)a1 + v3) = *((uint32_t *)a1 + i);\n }\n }\n *a2 = v3 + 1;\n return a1;\n}" + }, + { + "index": 712, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n// Function to compare integer arrays\n\nint compare_int_arrays(const void *a, const void *b) {\n\n int *arr1 = *(int **)a;\n\n int *arr2 = *(int **)b;\n\n size_t len1 = arr1[0];\n\n size_t len2 = arr2[0];\n\n if (len1 != len2) return len1 - len2;\n\n for (size_t i = 1; i <= len1; i++) {\n\n if (arr1[i] != arr2[i]) return arr1[i] - arr2[i];\n\n }\n\n return 0;\n\n}\n\n\n\n// Function to remove duplicates from list of integer arrays\n\nint** remove_duplicate_lists(int **list, size_t *new_size) {\n\n qsort(list, *new_size, sizeof(int*), compare_int_arrays);\n\n size_t unique = 0;\n\n for (size_t i = 1; i < *new_size; i++) {\n\n if (compare_int_arrays(&list[unique], &list[i]) != 0) {\n\n unique++;\n\n list[unique] = list[i];\n\n }\n\n }\n\n *new_size = unique + 1;\n\n return list;\n\n}\n\n\n\n// Function to compare strings\n\nint compare_strings(const void *a, const void *b) {\n\n char *const *sa = a;\n\n char *const *sb = b;\n\n return strcmp(*sa, *sb);\n\n}\n\n\n\n// Function to remove duplicates from strings\n\nchar** remove_duplicate_strings(char **list, size_t *new_size) {\n\n qsort(list, *new_size, sizeof(char*), compare_strings);\n\n size_t unique = 0;\n\n for (size_t i = 1; i < *new_size; i++) {\n\n if (strcmp(list[unique], list[i]) != 0) {\n\n unique++;\n\n list[unique] = list[i];\n\n }\n\n }\n\n *new_size = unique + 1;\n\n return list;\n\n}\n\n\n\n// Function to compare integers\n\nint compare_ints(const void *a, const void *b) {\n\n int ia = *(int*)a;\n\n int ib = *(int*)b;\n\n return ia - ib;\n\n}\n\n\n\n// Function to remove duplicates from integers\n\n", + "func": "int *func0(int *list, size_t *new_size) {\n qsort(list, *new_size, sizeof(int), compare_ints);\n size_t unique = 0;\n for (size_t i = 1; i < *new_size; i++) {\n if (list[unique] != list[i]) {\n unique++;\n list[unique] = list[i];\n }\n }\n *new_size = unique + 1;\n return list;\n}", + "test": "int main() {\n\n // Test case 1: List of integer arrays\n\n int list1_item1[] = {2, 10, 20};\n\n int list1_item2[] = {1, 40};\n\n int list1_item3[] = {3, 25, 30, 56};\n\n int list1_item4[] = {2, 10, 20};\n\n int list1_item5[] = {1, 33};\n\n int list1_item6[] = {1, 40};\n\n int* list1[] = {list1_item1, list1_item2, list1_item3, list1_item4, list1_item5, list1_item6};\n\n size_t size1 = 6;\n\n remove_duplicate_lists(list1, &size1);\n\n // Expected [[10, 20], [25, 30, 56], [33], [40]]\n\n // Skipping deep comparison for simplicity\n\n assert(size1 == 4);\n\n\n\n // Test case 2: List of strings\n\n char *list2[] = {\"a\", \"b\", \"a\", \"c\", \"c\"};\n\n size_t size2 = 5;\n\n remove_duplicate_strings(list2, &size2);\n\n assert(size2 == 3);\n\n assert(strcmp(list2[0], \"a\") == 0);\n\n assert(strcmp(list2[1], \"b\") == 0);\n\n assert(strcmp(list2[2], \"c\") == 0);\n\n\n\n // Test case 3: List of integers\n\n int list3[] = {1, 3, 5, 6, 3, 5, 6, 1};\n\n size_t size3 = 8;\n\n func0(list3, &size3);\n\n assert(size3 == 4);\n\n assert(list3[0] == 1);\n\n assert(list3[1] == 3);\n\n assert(list3[2] == 5);\n\n assert(list3[3] == 6);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbx\nmov %rsi,%rbp\nlea -0x14a(%rip),%rcx\nmov $0x4,%edx\nmov (%rsi),%rsi\ncallq 1080 \ncmpq $0x1,0x0(%rbp)\njbe 1380 \nmov $0x1,%eax\nmov $0x0,%edx\njmp 136e \nadd $0x1,%rdx\nmov %ecx,0x4(%rbx,%rsi,1)\nadd $0x1,%rax\ncmp %rax,0x0(%rbp)\njbe 1385 \nlea 0x0(,%rdx,4),%rsi\nmov (%rbx,%rax,4),%ecx\ncmp %ecx,(%rbx,%rdx,4)\njne 135c \njmp 1364 \nmov $0x0,%edx\nadd $0x1,%rdx\nmov %rdx,0x0(%rbp)\nmov %rbx,%rax\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov rbp, rsi\nmov rsi, [rsi]; nmemb\nlea rcx, compare_ints; compar\nmov edx, 4; size\ncall _qsort\ncmp qword ptr [rbp+0], 1\njbe short loc_1380\nmov eax, 1\nmov edx, 0\njmp short loc_1366\nloc_135C:\nadd rax, 1\ncmp rax, [rbp+0]\njnb short loc_1385\nloc_1366:\nlea rsi, ds:0[rdx*4]\nmov ecx, [rbx+rax*4]\ncmp [rbx+rdx*4], ecx\njz short loc_135C\nadd rdx, 1\nmov [rbx+rsi+4], ecx\njmp short loc_135C\nloc_1380:\nmov edx, 0\nloc_1385:\nadd rdx, 1\nmov [rbp+0], rdx\nmov rax, rbx\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_pseudo": "char *__fastcall func0(char *a1, size_t *a2)\n{\n unsigned __int64 v3; // rax\n __int64 v4; // rdx\n __int64 v5; // rsi\n int v6; // ecx\n\n qsort(a1, *a2, 4uLL, compare_ints);\n if ( *a2 <= 1 )\n {\n v4 = 0LL;\n }\n else\n {\n v3 = 1LL;\n v4 = 0LL;\n do\n {\n v5 = 4 * v4;\n v6 = *(_DWORD *)&a1[4 * v3];\n if ( *(_DWORD *)&a1[4 * v4] != v6 )\n {\n ++v4;\n *(_DWORD *)&a1[v5 + 4] = v6;\n }\n ++v3;\n }\n while ( v3 < *a2 );\n }\n *a2 = v4 + 1;\n return a1;\n}", + "ida_strip_asm": "sub_1325:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov rbp, rsi\nmov rsi, [rsi]; nmemb\nlea rcx, sub_11F2; compar\nmov edx, 4; size\ncall _qsort\ncmp qword ptr [rbp+0], 1\njbe short loc_1380\nmov eax, 1\nmov edx, 0\njmp short loc_1366\nloc_135C:\nadd rax, 1\ncmp rax, [rbp+0]\njnb short loc_1385\nloc_1366:\nlea rsi, ds:0[rdx*4]\nmov ecx, [rbx+rax*4]\ncmp [rbx+rdx*4], ecx\njz short loc_135C\nadd rdx, 1\nmov [rbx+rsi+4], ecx\njmp short loc_135C\nloc_1380:\nmov edx, 0\nloc_1385:\nadd rdx, 1\nmov [rbp+0], rdx\nmov rax, rbx\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1325(char *a1, size_t *a2)\n{\n unsigned __int64 v3; // rax\n __int64 v4; // rdx\n __int64 v5; // rsi\n int v6; // ecx\n\n qsort(a1, *a2, 4uLL, sub_11F2);\n if ( *a2 <= 1 )\n {\n v4 = 0LL;\n }\n else\n {\n v3 = 1LL;\n v4 = 0LL;\n do\n {\n v5 = 4 * v4;\n v6 = *(_DWORD *)&a1[4 * v3];\n if ( *(_DWORD *)&a1[4 * v4] != v6 )\n {\n ++v4;\n *(_DWORD *)&a1[v5 + 4] = v6;\n }\n ++v3;\n }\n while ( v3 < *a2 );\n }\n *a2 = v4 + 1;\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1325(char *a1, unsigned int *a2) {\n unsigned long long v3;\n long long v4;\n long long v5;\n int v6;\n qsort(a1, *a2, 4uLL, sub_11F2);\n if (*a2 <= 1) {\n v4 = 0LL;\n } else {\n v3 = 1LL;\n v4 = 0LL;\n do {\n v5 = 4 * v4;\n v6 = *(uint32_t *)&a1[4 * v3];\n if (*(uint32_t *)&a1[4 * v4] != v6) {\n ++v4;\n *(uint32_t *)&a1[v5 + 4] = v6;\n }\n ++v3;\n } while (v3 < *a2);\n }\n *a2 = v4 + 1;\n return a1;\n}", + "ida_pseudo_norm": "char *func0(char *a1, unsigned int *a2) {\n unsigned long long v3;\n long long v4;\n long long v5;\n int v6;\n qsort(a1, *a2, 4uLL, compare_ints);\n if (*a2 <= 1) {\n v4 = 0LL;\n } else {\n v3 = 1LL;\n v4 = 0LL;\n do {\n v5 = 4 * v4;\n v6 = *(uint32_t *)&a1[4 * v3];\n if (*(uint32_t *)&a1[4 * v4] != v6) {\n ++v4;\n *(uint32_t *)&a1[v5 + 4] = v6;\n }\n ++v3;\n } while (v3 < *a2);\n }\n *a2 = v4 + 1;\n return a1;\n}" + }, + { + "index": 712, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n// Function to compare integer arrays\n\nint compare_int_arrays(const void *a, const void *b) {\n\n int *arr1 = *(int **)a;\n\n int *arr2 = *(int **)b;\n\n size_t len1 = arr1[0];\n\n size_t len2 = arr2[0];\n\n if (len1 != len2) return len1 - len2;\n\n for (size_t i = 1; i <= len1; i++) {\n\n if (arr1[i] != arr2[i]) return arr1[i] - arr2[i];\n\n }\n\n return 0;\n\n}\n\n\n\n// Function to remove duplicates from list of integer arrays\n\nint** remove_duplicate_lists(int **list, size_t *new_size) {\n\n qsort(list, *new_size, sizeof(int*), compare_int_arrays);\n\n size_t unique = 0;\n\n for (size_t i = 1; i < *new_size; i++) {\n\n if (compare_int_arrays(&list[unique], &list[i]) != 0) {\n\n unique++;\n\n list[unique] = list[i];\n\n }\n\n }\n\n *new_size = unique + 1;\n\n return list;\n\n}\n\n\n\n// Function to compare strings\n\nint compare_strings(const void *a, const void *b) {\n\n char *const *sa = a;\n\n char *const *sb = b;\n\n return strcmp(*sa, *sb);\n\n}\n\n\n\n// Function to remove duplicates from strings\n\nchar** remove_duplicate_strings(char **list, size_t *new_size) {\n\n qsort(list, *new_size, sizeof(char*), compare_strings);\n\n size_t unique = 0;\n\n for (size_t i = 1; i < *new_size; i++) {\n\n if (strcmp(list[unique], list[i]) != 0) {\n\n unique++;\n\n list[unique] = list[i];\n\n }\n\n }\n\n *new_size = unique + 1;\n\n return list;\n\n}\n\n\n\n// Function to compare integers\n\nint compare_ints(const void *a, const void *b) {\n\n int ia = *(int*)a;\n\n int ib = *(int*)b;\n\n return ia - ib;\n\n}\n\n\n\n// Function to remove duplicates from integers\n\n", + "func": "int *func0(int *list, size_t *new_size) {\n qsort(list, *new_size, sizeof(int), compare_ints);\n size_t unique = 0;\n for (size_t i = 1; i < *new_size; i++) {\n if (list[unique] != list[i]) {\n unique++;\n list[unique] = list[i];\n }\n }\n *new_size = unique + 1;\n return list;\n}", + "test": "int main() {\n\n // Test case 1: List of integer arrays\n\n int list1_item1[] = {2, 10, 20};\n\n int list1_item2[] = {1, 40};\n\n int list1_item3[] = {3, 25, 30, 56};\n\n int list1_item4[] = {2, 10, 20};\n\n int list1_item5[] = {1, 33};\n\n int list1_item6[] = {1, 40};\n\n int* list1[] = {list1_item1, list1_item2, list1_item3, list1_item4, list1_item5, list1_item6};\n\n size_t size1 = 6;\n\n remove_duplicate_lists(list1, &size1);\n\n // Expected [[10, 20], [25, 30, 56], [33], [40]]\n\n // Skipping deep comparison for simplicity\n\n assert(size1 == 4);\n\n\n\n // Test case 2: List of strings\n\n char *list2[] = {\"a\", \"b\", \"a\", \"c\", \"c\"};\n\n size_t size2 = 5;\n\n remove_duplicate_strings(list2, &size2);\n\n assert(size2 == 3);\n\n assert(strcmp(list2[0], \"a\") == 0);\n\n assert(strcmp(list2[1], \"b\") == 0);\n\n assert(strcmp(list2[2], \"c\") == 0);\n\n\n\n // Test case 3: List of integers\n\n int list3[] = {1, 3, 5, 6, 3, 5, 6, 1};\n\n size_t size3 = 8;\n\n func0(list3, &size3);\n\n assert(size3 == 4);\n\n assert(list3[0] == 1);\n\n assert(list3[1] == 3);\n\n assert(list3[2] == 5);\n\n assert(list3[3] == 6);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nlea -0x1ad(%rip),%rcx\nmov $0x4,%edx\nmov %rdi,%r12\npush %rbx\nmov %rsi,%rbx\nsub $0x8,%rsp\nmov (%rsi),%rsi\ncallq 1080 \nmov (%rbx),%rax\ncmp $0x1,%rax\njbe 17b0 \nlea 0x4(%r12),%rcx\nlea (%r12,%rax,4),%r8\nxor %edx,%edx\nnopl 0x0(%rax)\nmov (%rcx),%esi\nlea 0x0(,%rdx,4),%rdi\nlea 0x1(%rdx),%rax\ncmp %esi,(%r12,%rdx,4)\nje 1793 \nmov %esi,0x4(%r12,%rdi,1)\nlea 0x2(%rdx),%rsi\nmov %rax,%rdx\nmov %rsi,%rax\nadd $0x4,%rcx\ncmp %rcx,%r8\njne 1770 \nmov %rax,(%rbx)\nadd $0x8,%rsp\nmov %r12,%rax\npop %rbx\npop %r12\nretq\nnopw 0x0(%rax,%rax,1)\nmov $0x1,%eax\nmov %rax,(%rbx)\nadd $0x8,%rsp\nmov %r12,%rax\npop %rbx\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsi\nlea rcx, compare_ints; compar\nmov edx, 4; size\npush rbx\nmov rbx, rdi\nsub rsp, 8\nmov rsi, [rsi]; nmemb\ncall _qsort\nmov rax, [rbp+0]\ncmp rax, 1\njbe short loc_1798\nlea rdx, [rbx+4]\nlea rdi, [rbx+rax*4]\nxor ecx, ecx\nnop dword ptr [rax+rax+00000000h]\nloc_1760:\nmov esi, [rdx]\nlea rax, ds:0[rcx*4]\ncmp [rbx+rcx*4], esi\njz short loc_1777\nmov [rbx+rax+4], esi\nadd rcx, 1\nloc_1777:\nadd rdx, 4\ncmp rdx, rdi\njnz short loc_1760\nadd rcx, 1\nmov rax, rbx\nmov [rbp+0], rcx\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1798:\nmov ecx, 1\nmov rax, rbx\nmov [rbp+0], rcx\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(_DWORD *a1, size_t *a2)\n{\n _DWORD *v3; // rdx\n _DWORD *v4; // rdi\n __int64 v5; // rcx\n _DWORD *result; // rax\n\n qsort(a1, *a2, 4uLL, compare_ints);\n if ( *a2 <= 1 )\n {\n result = a1;\n *a2 = 1LL;\n }\n else\n {\n v3 = a1 + 1;\n v4 = &a1[*a2];\n v5 = 0LL;\n do\n {\n if ( a1[v5] != *v3 )\n a1[++v5] = *v3;\n ++v3;\n }\n while ( v3 != v4 );\n result = a1;\n *a2 = v5 + 1;\n }\n return result;\n}", + "ida_strip_asm": "sub_1720:\nendbr64\npush rbp\nmov rbp, rsi\nlea rcx, sub_1590; compar\nmov edx, 4; size\npush rbx\nmov rbx, rdi\nsub rsp, 8\nmov rsi, [rsi]; nmemb\ncall _qsort\nmov rax, [rbp+0]\ncmp rax, 1\njbe short loc_1798\nlea rdx, [rbx+4]\nlea rdi, [rbx+rax*4]\nxor ecx, ecx\nnop dword ptr [rax+rax+00000000h]\nloc_1760:\nmov esi, [rdx]\nlea rax, ds:0[rcx*4]\ncmp [rbx+rcx*4], esi\njz short loc_1777\nmov [rbx+rax+4], esi\nadd rcx, 1\nloc_1777:\nadd rdx, 4\ncmp rdx, rdi\njnz short loc_1760\nadd rcx, 1\nmov rax, rbx\nmov [rbp+0], rcx\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1798:\nmov ecx, 1\nmov rax, rbx\nmov [rbp+0], rcx\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1720(_DWORD *a1, size_t *a2)\n{\n _DWORD *v3; // rdx\n _DWORD *v4; // rdi\n __int64 v5; // rcx\n _DWORD *result; // rax\n\n qsort(a1, *a2, 4uLL, sub_1590);\n if ( *a2 <= 1 )\n {\n result = a1;\n *a2 = 1LL;\n }\n else\n {\n v3 = a1 + 1;\n v4 = &a1[*a2];\n v5 = 0LL;\n do\n {\n if ( a1[v5] != *v3 )\n a1[++v5] = *v3;\n ++v3;\n }\n while ( v3 != v4 );\n result = a1;\n *a2 = v5 + 1;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1720(uint32_t *a1, unsigned int *a2) {\n uint32_t *v3;\n uint32_t *v4;\n long long v5;\n uint32_t *result;\n qsort(a1, *a2, 4uLL, sub_1590);\n if (*a2 <= 1) {\n result = a1;\n *a2 = 1LL;\n } else {\n v3 = a1 + 1;\n v4 = &a1[*a2];\n v5 = 0LL;\n do {\n if (a1[v5] != *v3) a1[++v5] = *v3;\n ++v3;\n } while (v3 != v4);\n result = a1;\n *a2 = v5 + 1;\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(uint32_t *a1, unsigned int *a2) {\n uint32_t *v3;\n uint32_t *v4;\n long long v5;\n uint32_t *result;\n qsort(a1, *a2, 4uLL, compare_ints);\n if (*a2 <= 1) {\n result = a1;\n *a2 = 1LL;\n } else {\n v3 = a1 + 1;\n v4 = &a1[*a2];\n v5 = 0LL;\n do {\n if (a1[v5] != *v3) a1[++v5] = *v3;\n ++v3;\n } while (v3 != v4);\n result = a1;\n *a2 = v5 + 1;\n }\n return result;\n}" + }, + { + "index": 712, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n// Function to compare integer arrays\n\nint compare_int_arrays(const void *a, const void *b) {\n\n int *arr1 = *(int **)a;\n\n int *arr2 = *(int **)b;\n\n size_t len1 = arr1[0];\n\n size_t len2 = arr2[0];\n\n if (len1 != len2) return len1 - len2;\n\n for (size_t i = 1; i <= len1; i++) {\n\n if (arr1[i] != arr2[i]) return arr1[i] - arr2[i];\n\n }\n\n return 0;\n\n}\n\n\n\n// Function to remove duplicates from list of integer arrays\n\nint** remove_duplicate_lists(int **list, size_t *new_size) {\n\n qsort(list, *new_size, sizeof(int*), compare_int_arrays);\n\n size_t unique = 0;\n\n for (size_t i = 1; i < *new_size; i++) {\n\n if (compare_int_arrays(&list[unique], &list[i]) != 0) {\n\n unique++;\n\n list[unique] = list[i];\n\n }\n\n }\n\n *new_size = unique + 1;\n\n return list;\n\n}\n\n\n\n// Function to compare strings\n\nint compare_strings(const void *a, const void *b) {\n\n char *const *sa = a;\n\n char *const *sb = b;\n\n return strcmp(*sa, *sb);\n\n}\n\n\n\n// Function to remove duplicates from strings\n\nchar** remove_duplicate_strings(char **list, size_t *new_size) {\n\n qsort(list, *new_size, sizeof(char*), compare_strings);\n\n size_t unique = 0;\n\n for (size_t i = 1; i < *new_size; i++) {\n\n if (strcmp(list[unique], list[i]) != 0) {\n\n unique++;\n\n list[unique] = list[i];\n\n }\n\n }\n\n *new_size = unique + 1;\n\n return list;\n\n}\n\n\n\n// Function to compare integers\n\nint compare_ints(const void *a, const void *b) {\n\n int ia = *(int*)a;\n\n int ib = *(int*)b;\n\n return ia - ib;\n\n}\n\n\n\n// Function to remove duplicates from integers\n\n", + "func": "int *func0(int *list, size_t *new_size) {\n qsort(list, *new_size, sizeof(int), compare_ints);\n size_t unique = 0;\n for (size_t i = 1; i < *new_size; i++) {\n if (list[unique] != list[i]) {\n unique++;\n list[unique] = list[i];\n }\n }\n *new_size = unique + 1;\n return list;\n}", + "test": "int main() {\n\n // Test case 1: List of integer arrays\n\n int list1_item1[] = {2, 10, 20};\n\n int list1_item2[] = {1, 40};\n\n int list1_item3[] = {3, 25, 30, 56};\n\n int list1_item4[] = {2, 10, 20};\n\n int list1_item5[] = {1, 33};\n\n int list1_item6[] = {1, 40};\n\n int* list1[] = {list1_item1, list1_item2, list1_item3, list1_item4, list1_item5, list1_item6};\n\n size_t size1 = 6;\n\n remove_duplicate_lists(list1, &size1);\n\n // Expected [[10, 20], [25, 30, 56], [33], [40]]\n\n // Skipping deep comparison for simplicity\n\n assert(size1 == 4);\n\n\n\n // Test case 2: List of strings\n\n char *list2[] = {\"a\", \"b\", \"a\", \"c\", \"c\"};\n\n size_t size2 = 5;\n\n remove_duplicate_strings(list2, &size2);\n\n assert(size2 == 3);\n\n assert(strcmp(list2[0], \"a\") == 0);\n\n assert(strcmp(list2[1], \"b\") == 0);\n\n assert(strcmp(list2[2], \"c\") == 0);\n\n\n\n // Test case 3: List of integers\n\n int list3[] = {1, 3, 5, 6, 3, 5, 6, 1};\n\n size_t size3 = 8;\n\n func0(list3, &size3);\n\n assert(size3 == 4);\n\n assert(list3[0] == 1);\n\n assert(list3[1] == 3);\n\n assert(list3[2] == 5);\n\n assert(list3[3] == 6);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nlea -0x1ad(%rip),%rcx\nmov $0x4,%edx\nmov %rdi,%r12\npush %rbx\nmov %rsi,%rbx\nsub $0x8,%rsp\nmov (%rsi),%rsi\ncallq 1080 \nmov (%rbx),%rax\ncmp $0x1,%rax\njbe 17a0 \nmov (%r12),%r9d\nlea 0x4(%r12),%rdx\nlea (%r12,%rax,4),%rax\nxor %r8d,%r8d\nmov $0x1,%esi\nmov (%rdx),%ecx\ncmp %r9d,%ecx\nje 177c \nadd $0x4,%rdx\nmov %ecx,(%r12,%rsi,4)\nadd $0x2,%r8\ncmp %rax,%rdx\nje 1788 \nmov %ecx,%r9d\nmov (%rdx),%ecx\nmov %rsi,%r8\nadd $0x1,%rsi\ncmp %r9d,%ecx\njne 175a \nadd $0x4,%rdx\ncmp %rax,%rdx\njne 1753 \nmov %rsi,%r8\nmov %r8,(%rbx)\nadd $0x8,%rsp\nmov %r12,%rax\npop %rbx\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\nmov $0x1,%r8d\nmov %r12,%rax\nmov %r8,(%rbx)\nadd $0x8,%rsp\npop %rbx\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsi\nlea rcx, compare_ints; compar\nmov edx, 4; size\npush rbx\nmov rbx, rdi\nsub rsp, 8\nmov rsi, [rsi]; nmemb\ncall _qsort\nmov rax, [rbp+0]\ncmp rax, 1\njbe short loc_1798\nmov r8d, [rbx]\nlea rdx, [rbx+4]\nlea rax, [rbx+rax*4]\nxor esi, esi\njmp short loc_1773\nloc_1760:\nadd rsi, 1\nadd rdx, 4\nmov [rbx+rsi*4], ecx\ncmp rax, rdx\njz short loc_1783\nloc_1770:\nmov r8d, ecx\nloc_1773:\nmov ecx, [rdx]\ncmp ecx, r8d\njnz short loc_1760\nadd rdx, 4\ncmp rax, rdx\njnz short loc_1770\nloc_1783:\nadd rsi, 1\nmov rax, rbx\nmov [rbp+0], rsi\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1798:\nmov esi, 1\nmov rax, rbx\nmov [rbp+0], rsi\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_pseudo": "int *__fastcall func0(int *a1, size_t *a2)\n{\n int v3; // r8d\n int *v4; // rdx\n int *v5; // rax\n __int64 v6; // rsi\n int v7; // ecx\n int *result; // rax\n\n qsort(a1, *a2, 4uLL, compare_ints);\n if ( *a2 > 1 )\n {\n v3 = *a1;\n v4 = a1 + 1;\n v5 = &a1[*a2];\n v6 = 0LL;\n while ( 1 )\n {\n v7 = *v4;\n if ( *v4 == v3 )\n {\n if ( v5 == ++v4 )\n {\nLABEL_7:\n result = a1;\n *a2 = v6 + 1;\n return result;\n }\n }\n else\n {\n ++v6;\n ++v4;\n a1[v6] = v7;\n if ( v5 == v4 )\n goto LABEL_7;\n }\n v3 = v7;\n }\n }\n result = a1;\n *a2 = 1LL;\n return result;\n}", + "ida_strip_asm": "sub_1720:\nendbr64\npush rbp\nmov rbp, rsi\nlea rcx, sub_1590; compar\nmov edx, 4; size\npush rbx\nmov rbx, rdi\nsub rsp, 8\nmov rsi, [rsi]; nmemb\ncall _qsort\nmov rax, [rbp+0]\ncmp rax, 1\njbe short loc_1798\nmov r8d, [rbx]\nlea rdx, [rbx+4]\nlea rax, [rbx+rax*4]\nxor esi, esi\njmp short loc_1773\nloc_1760:\nadd rsi, 1\nadd rdx, 4\nmov [rbx+rsi*4], ecx\ncmp rax, rdx\njz short loc_1783\nloc_1770:\nmov r8d, ecx\nloc_1773:\nmov ecx, [rdx]\ncmp ecx, r8d\njnz short loc_1760\nadd rdx, 4\ncmp rax, rdx\njnz short loc_1770\nloc_1783:\nadd rsi, 1\nmov rax, rbx\nmov [rbp+0], rsi\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1798:\nmov esi, 1\nmov rax, rbx\nmov [rbp+0], rsi\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "int *__fastcall sub_1720(int *a1, size_t *a2)\n{\n int v3; // r8d\n int *v4; // rdx\n int *v5; // rax\n __int64 v6; // rsi\n int v7; // ecx\n int *result; // rax\n\n qsort(a1, *a2, 4uLL, sub_1590);\n if ( *a2 > 1 )\n {\n v3 = *a1;\n v4 = a1 + 1;\n v5 = &a1[*a2];\n v6 = 0LL;\n while ( 1 )\n {\n v7 = *v4;\n if ( *v4 == v3 )\n {\n if ( v5 == ++v4 )\n {\nLABEL_7:\n result = a1;\n *a2 = v6 + 1;\n return result;\n }\n }\n else\n {\n ++v6;\n ++v4;\n a1[v6] = v7;\n if ( v5 == v4 )\n goto LABEL_7;\n }\n v3 = v7;\n }\n }\n result = a1;\n *a2 = 1LL;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "int *sub_1720(int *a1, unsigned int *a2) {\n int v3;\n int *v4;\n int *v5;\n long long v6;\n int v7;\n int *result;\n qsort(a1, *a2, 4uLL, sub_1590);\n if (*a2 > 1) {\n v3 = *a1;\n v4 = a1 + 1;\n v5 = &a1[*a2];\n v6 = 0LL;\n while (1) {\n v7 = *v4;\n if (*v4 == v3) {\n if (v5 == ++v4) {\n LABEL_7:\n result = a1;\n *a2 = v6 + 1;\n return result;\n }\n } else {\n ++v6;\n ++v4;\n a1[v6] = v7;\n if (v5 == v4) goto LABEL_7;\n }\n v3 = v7;\n }\n }\n result = a1;\n *a2 = 1LL;\n return result;\n}", + "ida_pseudo_norm": "int *func0(int *a1, unsigned int *a2) {\n int v3;\n int *v4;\n int *v5;\n long long v6;\n int v7;\n int *result;\n qsort(a1, *a2, 4uLL, compare_ints);\n if (*a2 > 1) {\n v3 = *a1;\n v4 = a1 + 1;\n v5 = &a1[*a2];\n v6 = 0LL;\n while (1) {\n v7 = *v4;\n if (*v4 == v3) {\n if (v5 == ++v4) {\n LABEL_7:\n result = a1;\n *a2 = v6 + 1;\n return result;\n }\n } else {\n ++v6;\n ++v4;\n a1[v6] = v7;\n if (v5 == v4) goto LABEL_7;\n }\n v3 = v7;\n }\n }\n result = a1;\n *a2 = 1LL;\n return result;\n}" + }, + { + "index": 713, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(bool test_tup[], int size) {\n for (int i = 0; i < size; i++) {\n if (!test_tup[i]) return false;\n }\n return true;\n}", + "test": "int main() {\n\n bool arr1[] = {true, true, true, true};\n\n bool arr2[] = {true, false, true, true};\n\n bool arr3[] = {true, true, true, true};\n\n\n\n assert(func0(arr1, 4) == true);\n\n assert(func0(arr2, 4) == false);\n\n assert(func0(arr3, 4) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11a3 \nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nxor $0x1,%eax\ntest %al,%al\nje 119f \nmov $0x0,%eax\njmp 11b0 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1181 \nmov $0x1,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 0\njmp short loc_11A3\nloc_1181:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nxor eax, 1\ntest al, al\njz short loc_119F\nmov eax, 0\njmp short loc_11B0\nloc_119F:\nadd [rbp+var_4], 1\nloc_11A3:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1181\nmov eax, 1\nloc_11B0:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n if ( *(_BYTE *)(i + a1) != 1 )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 0\njmp short loc_11A3\nloc_1181:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nxor eax, 1\ntest al, al\njz short loc_119F\nmov eax, 0\njmp short loc_11B0\nloc_119F:\nadd [rbp+var_4], 1\nloc_11A3:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1181\nmov eax, 1\nloc_11B0:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n if ( *(_BYTE *)(i + a1) != 1 )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int i;\n for (i = 0; i < a2; ++i) {\n if (*(uint8_t *)(i + a1) != 1) return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int i;\n for (i = 0; i < a2; ++i) {\n if (*(uint8_t *)(i + a1) != 1) return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": 713, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(bool test_tup[], int size) {\n for (int i = 0; i < size; i++) {\n if (!test_tup[i]) return false;\n }\n return true;\n}", + "test": "int main() {\n\n bool arr1[] = {true, true, true, true};\n\n bool arr2[] = {true, false, true, true};\n\n bool arr3[] = {true, true, true, true};\n\n\n\n assert(func0(arr1, 4) == true);\n\n assert(func0(arr2, 4) == false);\n\n assert(func0(arr3, 4) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 118f \nmov %rdi,%rax\nlea -0x1(%rsi),%edx\nlea 0x1(%rdi,%rdx,1),%rcx\nmovzbl (%rax),%edx\ntest %dl,%dl\nje 118c \nadd $0x1,%rax\ncmp %rcx,%rax\njne 117c \nmov %edx,%eax\nretq\nmov $0x1,%edx\njmp 118c \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_118D\nmov rax, rdi\nmovsxd rsi, esi\nadd rdi, rsi\nloc_117A:\nmovzx edx, byte ptr [rax]\ntest dl, dl\njz short loc_118A\nadd rax, 1\ncmp rax, rdi\njnz short loc_117A\nloc_118A:\nmov eax, edx\nretn\nloc_118D:\nmov edx, 1\njmp short loc_118A", + "ida_pseudo": "__int64 __fastcall func0(unsigned __int8 *a1, int a2)\n{\n unsigned __int8 *v2; // rax\n unsigned __int8 *v3; // rdi\n unsigned int v4; // edx\n\n if ( a2 <= 0 )\n {\n return 1;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n do\n {\n v4 = *v2;\n if ( !(_BYTE)v4 )\n break;\n ++v2;\n }\n while ( v2 != v3 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_118D\nmov rax, rdi\nmovsxd rsi, esi\nadd rdi, rsi\nloc_117A:\nmovzx edx, byte ptr [rax]\ntest dl, dl\njz short loc_118A\nadd rax, 1\ncmp rax, rdi\njnz short loc_117A\nloc_118A:\nmov eax, edx\nretn\nloc_118D:\nmov edx, 1\njmp short loc_118A", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(unsigned __int8 *a1, int a2)\n{\n unsigned __int8 *v2; // rax\n unsigned __int8 *v3; // rdi\n unsigned int v4; // edx\n\n if ( a2 <= 0 )\n {\n return 1;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n do\n {\n v4 = *v2;\n if ( !(_BYTE)v4 )\n break;\n ++v2;\n }\n while ( v2 != v3 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(unsigned char *a1, int a2) {\n unsigned char *v2;\n unsigned char *v3;\n unsigned int v4;\n if (a2 <= 0) {\n return 1;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n do {\n v4 = *v2;\n if (!(uint8_t)v4) break;\n ++v2;\n } while (v2 != v3);\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(unsigned char *a1, int a2) {\n unsigned char *v2;\n unsigned char *v3;\n unsigned int v4;\n if (a2 <= 0) {\n return 1;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n do {\n v4 = *v2;\n if (!(uint8_t)v4) break;\n ++v2;\n } while (v2 != v3);\n }\n return v4;\n}" + }, + { + "index": 714, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int m = n;\n int count = 0;\n int i = 2;\n while ((i * i) <= m) {\n int total = 0;\n while (n % i == 0) {\n n /= i;\n total += 1;\n }\n int temp = 0;\n int j = 1;\n while ((temp + j) <= total) {\n temp += j;\n count += 1;\n j += 1;\n }\n i += 1;\n }\n if (n != 1) {\n count += 1;\n }\n return count;\n}", + "test": "int main() {\n\n assert(func0(24) == 3);\n\n assert(func0(12) == 2);\n\n assert(func0(4) == 1);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x24(%rbp)\nmov -0x24(%rbp),%eax\nmov %eax,-0x4(%rbp)\nmovl $0x0,-0x18(%rbp)\nmovl $0x2,-0x14(%rbp)\njmp 11bd \nmovl $0x0,-0x10(%rbp)\njmp 1181 \nmov -0x24(%rbp),%eax\ncltd\nidivl -0x14(%rbp)\nmov %eax,-0x24(%rbp)\naddl $0x1,-0x10(%rbp)\nmov -0x24(%rbp),%eax\ncltd\nidivl -0x14(%rbp)\nmov %edx,%eax\ntest %eax,%eax\nje 1173 \nmovl $0x0,-0xc(%rbp)\nmovl $0x1,-0x8(%rbp)\njmp 11ac \nmov -0x8(%rbp),%eax\nadd %eax,-0xc(%rbp)\naddl $0x1,-0x18(%rbp)\naddl $0x1,-0x8(%rbp)\nmov -0xc(%rbp),%edx\nmov -0x8(%rbp),%eax\nadd %edx,%eax\ncmp %eax,-0x10(%rbp)\njge 119e \naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\nimul %eax,%eax\ncmp %eax,-0x4(%rbp)\njge 116a \ncmpl $0x1,-0x24(%rbp)\nje 11d2 \naddl $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_24], edi\nmov eax, [rbp+var_24]\nmov [rbp+var_4], eax\nmov [rbp+var_18], 0\nmov [rbp+var_14], 2\njmp short loc_11BD\nloc_116A:\nmov [rbp+var_10], 0\njmp short loc_1181\nloc_1173:\nmov eax, [rbp+var_24]\ncdq\nidiv [rbp+var_14]\nmov [rbp+var_24], eax\nadd [rbp+var_10], 1\nloc_1181:\nmov eax, [rbp+var_24]\ncdq\nidiv [rbp+var_14]\nmov eax, edx\ntest eax, eax\njz short loc_1173\nmov [rbp+var_C], 0\nmov [rbp+var_8], 1\njmp short loc_11AC\nloc_119E:\nmov eax, [rbp+var_8]\nadd [rbp+var_C], eax\nadd [rbp+var_18], 1\nadd [rbp+var_8], 1\nloc_11AC:\nmov edx, [rbp+var_C]\nmov eax, [rbp+var_8]\nadd eax, edx\ncmp [rbp+var_10], eax\njge short loc_119E\nadd [rbp+var_14], 1\nloc_11BD:\nmov eax, [rbp+var_14]\nimul eax, eax\ncmp [rbp+var_4], eax\njge short loc_116A\ncmp [rbp+var_24], 1\njz short loc_11D2\nadd [rbp+var_18], 1\nloc_11D2:\nmov eax, [rbp+var_18]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v2; // [rsp+0h] [rbp-24h]\n unsigned int v3; // [rsp+Ch] [rbp-18h]\n int i; // [rsp+10h] [rbp-14h]\n int v5; // [rsp+14h] [rbp-10h]\n int v6; // [rsp+18h] [rbp-Ch]\n int j; // [rsp+1Ch] [rbp-8h]\n\n v2 = a1;\n v3 = 0;\n for ( i = 2; a1 >= i * i; ++i )\n {\n v5 = 0;\n while ( !(v2 % i) )\n {\n v2 /= i;\n ++v5;\n }\n v6 = 0;\n for ( j = 1; v5 >= v6 + j; ++j )\n {\n v6 += j;\n ++v3;\n }\n }\n if ( v2 != 1 )\n ++v3;\n return v3;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_24], edi\nmov eax, [rbp+var_24]\nmov [rbp+var_4], eax\nmov [rbp+var_18], 0\nmov [rbp+var_14], 2\njmp short loc_11BD\nloc_116A:\nmov [rbp+var_10], 0\njmp short loc_1181\nloc_1173:\nmov eax, [rbp+var_24]\ncdq\nidiv [rbp+var_14]\nmov [rbp+var_24], eax\nadd [rbp+var_10], 1\nloc_1181:\nmov eax, [rbp+var_24]\ncdq\nidiv [rbp+var_14]\nmov eax, edx\ntest eax, eax\njz short loc_1173\nmov [rbp+var_C], 0\nmov [rbp+var_8], 1\njmp short loc_11AC\nloc_119E:\nmov eax, [rbp+var_8]\nadd [rbp+var_C], eax\nadd [rbp+var_18], 1\nadd [rbp+var_8], 1\nloc_11AC:\nmov edx, [rbp+var_C]\nmov eax, [rbp+var_8]\nadd eax, edx\ncmp [rbp+var_10], eax\njge short loc_119E\nadd [rbp+var_14], 1\nloc_11BD:\nmov eax, [rbp+var_14]\nimul eax, eax\ncmp [rbp+var_4], eax\njge short loc_116A\ncmp [rbp+var_24], 1\njz short loc_11D2\nadd [rbp+var_18], 1\nloc_11D2:\nmov eax, [rbp+var_18]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v2; // [rsp+0h] [rbp-24h]\n unsigned int v3; // [rsp+Ch] [rbp-18h]\n int i; // [rsp+10h] [rbp-14h]\n int v5; // [rsp+14h] [rbp-10h]\n int v6; // [rsp+18h] [rbp-Ch]\n int j; // [rsp+1Ch] [rbp-8h]\n\n v2 = a1;\n v3 = 0;\n for ( i = 2; a1 >= i * i; ++i )\n {\n v5 = 0;\n while ( !(v2 % i) )\n {\n v2 /= i;\n ++v5;\n }\n v6 = 0;\n for ( j = 1; v5 >= v6 + j; ++j )\n {\n v6 += j;\n ++v3;\n }\n }\n if ( v2 != 1 )\n ++v3;\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v2;\n unsigned int v3;\n int i;\n int v5;\n int v6;\n int j;\n v2 = a1;\n v3 = 0;\n for (i = 2; a1 >= i * i; ++i) {\n v5 = 0;\n while (!(v2 % i)) {\n v2 /= i;\n ++v5;\n }\n v6 = 0;\n for (j = 1; v5 >= v6 + j; ++j) {\n v6 += j;\n ++v3;\n }\n }\n if (v2 != 1) ++v3;\n return v3;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v2;\n unsigned int v3;\n int i;\n int v5;\n int v6;\n int j;\n v2 = a1;\n v3 = 0;\n for (i = 2; a1 >= i * i; ++i) {\n v5 = 0;\n while (!(v2 % i)) {\n v2 /= i;\n ++v5;\n }\n v6 = 0;\n for (j = 1; v5 >= v6 + j; ++j) {\n v6 += j;\n ++v3;\n }\n }\n if (v2 != 1) ++v3;\n return v3;\n}" + }, + { + "index": 714, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int m = n;\n int count = 0;\n int i = 2;\n while ((i * i) <= m) {\n int total = 0;\n while (n % i == 0) {\n n /= i;\n total += 1;\n }\n int temp = 0;\n int j = 1;\n while ((temp + j) <= total) {\n temp += j;\n count += 1;\n j += 1;\n }\n i += 1;\n }\n if (n != 1) {\n count += 1;\n }\n return count;\n}", + "test": "int main() {\n\n assert(func0(24) == 3);\n\n assert(func0(12) == 2);\n\n assert(func0(4) == 1);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %edi,%ecx\nmov $0x2,%esi\nmov $0x0,%r10d\ncmp $0x3,%edi\njg 11b1 \ncmp $0x1,%ecx\nsetne %al\nmovzbl %al,%eax\nadd %eax,%r10d\nmov %r10d,%eax\nretq\nmov %ecx,%eax\ncltd\nidiv %esi\nmov %eax,%ecx\nadd $0x1,%r8d\ncltd\nidiv %esi\ntest %edx,%edx\nje 116f \ntest %r8d,%r8d\njle 11a5 \nmov %r10d,%edx\nmov $0x1,%r9d\nmov %edx,%eax\nadd $0x1,%edx\nadd $0x2,%eax\nsub %r10d,%eax\nadd %eax,%r9d\ncmp %r8d,%r9d\njle 118f \nmov %edx,%r10d\nadd $0x1,%esi\nmov %esi,%eax\nimul %esi,%eax\ncmp %edi,%eax\njg 115f \nmov %ecx,%eax\ncltd\nidiv %esi\nmov %edx,%r8d\ntest %edx,%edx\nje 116f \njmp 11a5 \n", + "ida_asm": "func0:\nendbr64\nmov r10d, edi\nmov ecx, edi\nmov esi, 2\nmov r8d, 0\nmov r11d, 1\ncmp edi, 3\njg short loc_11B9\nloc_1168:\ncmp ecx, 1\nsetnz al\nmovzx eax, al\nadd r8d, eax\nmov eax, r8d\nretn\nloc_1178:\nmov eax, ecx\ncdq\nidiv esi\nmov ecx, eax\nadd edi, 1\ncdq\nidiv esi\ntest edx, edx\njz short loc_1178\ntest edi, edi\njle short loc_11AC\nmov eax, r8d\nmov edx, 1\nmov r9d, r11d\nsub r9d, r8d\nloc_119B:\nadd eax, 1\nlea r8d, [r9+rax]\nadd edx, r8d\ncmp edx, edi\njle short loc_119B\nmov r8d, eax\nloc_11AC:\nadd esi, 1\nmov eax, esi\nimul eax, esi\ncmp eax, r10d\njg short loc_1168\nloc_11B9:\nmov eax, ecx\ncdq\nidiv esi\nmov edi, edx\ntest edx, edx\njz short loc_1178\njmp short loc_11AC", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v2; // ecx\n int v3; // esi\n int v4; // r8d\n int v6; // edi\n int v7; // eax\n int i; // edx\n\n v2 = a1;\n v3 = 2;\n v4 = 0;\n if ( a1 > 3 )\n {\n do\n {\n v6 = v2 % v3;\n if ( !(v2 % v3) )\n {\n do\n {\n v2 /= v3;\n ++v6;\n }\n while ( !(v2 % v3) );\n if ( v6 > 0 )\n {\n v7 = v4;\n for ( i = 1; i <= v6; i += 1 - v4 + v7 )\n ++v7;\n v4 = v7;\n }\n }\n ++v3;\n }\n while ( v3 * v3 <= a1 );\n }\n return (unsigned int)(v2 != 1) + v4;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmov r10d, edi\nmov ecx, edi\nmov esi, 2\nmov r8d, 0\nmov r11d, 1\ncmp edi, 3\njg short loc_11B9\nloc_1168:\ncmp ecx, 1\nsetnz al\nmovzx eax, al\nadd r8d, eax\nmov eax, r8d\nretn\nloc_1178:\nmov eax, ecx\ncdq\nidiv esi\nmov ecx, eax\nadd edi, 1\ncdq\nidiv esi\ntest edx, edx\njz short loc_1178\ntest edi, edi\njle short loc_11AC\nmov eax, r8d\nmov edx, 1\nmov r9d, r11d\nsub r9d, r8d\nloc_119B:\nadd eax, 1\nlea r8d, [r9+rax]\nadd edx, r8d\ncmp edx, edi\njle short loc_119B\nmov r8d, eax\nloc_11AC:\nadd esi, 1\nmov eax, esi\nimul eax, esi\ncmp eax, r10d\njg short loc_1168\nloc_11B9:\nmov eax, ecx\ncdq\nidiv esi\nmov edi, edx\ntest edx, edx\njz short loc_1178\njmp short loc_11AC", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v2; // ecx\n int v3; // esi\n int v4; // r8d\n int v6; // edi\n int v7; // eax\n int i; // edx\n\n v2 = a1;\n v3 = 2;\n v4 = 0;\n if ( a1 > 3 )\n {\n do\n {\n v6 = v2 % v3;\n if ( !(v2 % v3) )\n {\n do\n {\n v2 /= v3;\n ++v6;\n }\n while ( !(v2 % v3) );\n if ( v6 > 0 )\n {\n v7 = v4;\n for ( i = 1; i <= v6; i += 1 - v4 + v7 )\n ++v7;\n v4 = v7;\n }\n }\n ++v3;\n }\n while ( v3 * v3 <= a1 );\n }\n return (unsigned int)(v2 != 1) + v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v2;\n int v3;\n int v4;\n int v6;\n int v7;\n int i;\n v2 = a1;\n v3 = 2;\n v4 = 0;\n if (a1 > 3) {\n do {\n v6 = v2 % v3;\n if (!(v2 % v3)) {\n do {\n v2 /= v3;\n ++v6;\n } while (!(v2 % v3));\n if (v6 > 0) {\n v7 = v4;\n for (i = 1; i <= v6; i += 1 - v4 + v7) ++v7;\n v4 = v7;\n }\n }\n ++v3;\n } while (v3 * v3 <= a1);\n }\n return (unsigned int)(v2 != 1) + v4;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v2;\n int v3;\n int v4;\n int v6;\n int v7;\n int i;\n v2 = a1;\n v3 = 2;\n v4 = 0;\n if (a1 > 3) {\n do {\n v6 = v2 % v3;\n if (!(v2 % v3)) {\n do {\n v2 /= v3;\n ++v6;\n } while (!(v2 % v3));\n if (v6 > 0) {\n v7 = v4;\n for (i = 1; i <= v6; i += 1 - v4 + v7) ++v7;\n v4 = v7;\n }\n }\n ++v3;\n } while (v3 * v3 <= a1);\n }\n return (unsigned int)(v2 != 1) + v4;\n}" + }, + { + "index": 714, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int m = n;\n int count = 0;\n int i = 2;\n while ((i * i) <= m) {\n int total = 0;\n while (n % i == 0) {\n n /= i;\n total += 1;\n }\n int temp = 0;\n int j = 1;\n while ((temp + j) <= total) {\n temp += j;\n count += 1;\n j += 1;\n }\n i += 1;\n }\n if (n != 1) {\n count += 1;\n }\n return count;\n}", + "test": "int main() {\n\n assert(func0(24) == 3);\n\n assert(func0(12) == 2);\n\n assert(func0(4) == 1);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov %edi,%r10d\nmov $0x2,%ecx\nxor %r9d,%r9d\ncmp $0x3,%edi\njle 12fb \nnopl 0x0(%rax)\nmov %edi,%eax\ncltd\nidiv %ecx\nmov %edx,%esi\ntest %edx,%edx\njne 12ee \nnopl 0x0(%rax,%rax,1)\nmov %edi,%eax\nadd $0x1,%esi\ncltd\nidiv %ecx\ncltd\nmov %eax,%edi\nidiv %ecx\ntest %edx,%edx\nje 12b8 \nmov %r9d,%edx\nmov $0x1,%r8d\nnopw 0x0(%rax,%rax,1)\nmov %edx,%eax\nadd $0x1,%edx\nadd $0x2,%eax\nsub %r9d,%eax\nadd %eax,%r8d\ncmp %esi,%r8d\njle 12d8 \nmov %edx,%r9d\nadd $0x1,%ecx\nmov %ecx,%eax\nimul %ecx,%eax\ncmp %r10d,%eax\njle 12a8 \nxor %eax,%eax\ncmp $0x1,%edi\nsetne %al\nadd %eax,%r9d\nmov %r9d,%eax\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmov ecx, edi\nmov r10d, edi\nmov esi, 2\nxor edi, edi\nmov r11d, 1\ncmp ecx, 3\njle short loc_125D\nnop dword ptr [rax+rax+00h]\nloc_1210:\nmov eax, ecx\ncdq\nidiv esi\nmov r8d, edx\ntest edx, edx\njnz short loc_1250\nnop dword ptr [rax+00h]\nloc_1220:\nmov eax, ecx\nadd r8d, 1\ncdq\nidiv esi\ncdq\nmov ecx, eax\nidiv esi\ntest edx, edx\njz short loc_1220\nmov r9d, r11d\nmov eax, edi\nmov edx, 1\nsub r9d, edi\nnop\nloc_1240:\nadd eax, 1\nlea edi, [r9+rax]\nadd edx, edi\ncmp edx, r8d\njle short loc_1240\nmov edi, eax\nloc_1250:\nadd esi, 1\nmov eax, esi\nimul eax, esi\ncmp eax, r10d\njle short loc_1210\nloc_125D:\nxor eax, eax\ncmp ecx, 1\nsetnz al\nadd edi, eax\nmov eax, edi\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // ecx\n int v3; // esi\n int v4; // edi\n int v5; // r8d\n int v6; // edx\n int v7; // eax\n int v8; // edx\n\n v1 = a1;\n v3 = 2;\n v4 = 0;\n if ( v1 > 3 )\n {\n do\n {\n v5 = v1 % v3;\n if ( !(v1 % v3) )\n {\n do\n {\n ++v5;\n v6 = (v1 / v3) >> 31;\n v1 /= v3;\n }\n while ( !(unsigned int)(__SPAIR64__(v6, v1) % v3) );\n v7 = v4;\n v8 = 1;\n do\n {\n ++v7;\n v8 += 1 - v4 + v7;\n }\n while ( v8 <= v5 );\n v4 = v7;\n }\n ++v3;\n }\n while ( v3 * v3 <= a1 );\n }\n return (unsigned int)(v1 != 1) + v4;\n}", + "ida_strip_asm": "sub_11F0:\nendbr64\nmov ecx, edi\nmov r10d, edi\nmov esi, 2\nxor edi, edi\nmov r11d, 1\ncmp ecx, 3\njle short loc_125D\nnop dword ptr [rax+rax+00h]\nloc_1210:\nmov eax, ecx\ncdq\nidiv esi\nmov r8d, edx\ntest edx, edx\njnz short loc_1250\nnop dword ptr [rax+00h]\nloc_1220:\nmov eax, ecx\nadd r8d, 1\ncdq\nidiv esi\ncdq\nmov ecx, eax\nidiv esi\ntest edx, edx\njz short loc_1220\nmov r9d, r11d\nmov eax, edi\nmov edx, 1\nsub r9d, edi\nnop\nloc_1240:\nadd eax, 1\nlea edi, [r9+rax]\nadd edx, edi\ncmp edx, r8d\njle short loc_1240\nmov edi, eax\nloc_1250:\nadd esi, 1\nmov eax, esi\nimul eax, esi\ncmp eax, r10d\njle short loc_1210\nloc_125D:\nxor eax, eax\ncmp ecx, 1\nsetnz al\nadd edi, eax\nmov eax, edi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11F0(int a1)\n{\n int v1; // ecx\n int v3; // esi\n int v4; // edi\n int v5; // r8d\n int v6; // edx\n int v7; // eax\n int v8; // edx\n\n v1 = a1;\n v3 = 2;\n v4 = 0;\n if ( v1 > 3 )\n {\n do\n {\n v5 = v1 % v3;\n if ( !(v1 % v3) )\n {\n do\n {\n ++v5;\n v6 = (v1 / v3) >> 31;\n v1 /= v3;\n }\n while ( !(unsigned int)(__SPAIR64__(v6, v1) % v3) );\n v7 = v4;\n v8 = 1;\n do\n {\n ++v7;\n v8 += 1 - v4 + v7;\n }\n while ( v8 <= v5 );\n v4 = v7;\n }\n ++v3;\n }\n while ( v3 * v3 <= a1 );\n }\n return (unsigned int)(v1 != 1) + v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11F0(int a1) {\n int v1;\n int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n int v8;\n v1 = a1;\n v3 = 2;\n v4 = 0;\n if (v1 > 3) {\n do {\n v5 = v1 % v3;\n if (!(v1 % v3)) {\n do {\n ++v5;\n v6 = (v1 / v3) >> 31;\n v1 /= v3;\n } while (!(unsigned int)(__SPAIR64__(v6, v1) % v3));\n v7 = v4;\n v8 = 1;\n do {\n ++v7;\n v8 += 1 - v4 + v7;\n } while (v8 <= v5);\n v4 = v7;\n }\n ++v3;\n } while (v3 * v3 <= a1);\n }\n return (unsigned int)(v1 != 1) + v4;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n int v8;\n v1 = a1;\n v3 = 2;\n v4 = 0;\n if (v1 > 3) {\n do {\n v5 = v1 % v3;\n if (!(v1 % v3)) {\n do {\n ++v5;\n v6 = (v1 / v3) >> 31;\n v1 /= v3;\n } while (!(unsigned int)(__SPAIR64__(v6, v1) % v3));\n v7 = v4;\n v8 = 1;\n do {\n ++v7;\n v8 += 1 - v4 + v7;\n } while (v8 <= v5);\n v4 = v7;\n }\n ++v3;\n } while (v3 * v3 <= a1);\n }\n return (unsigned int)(v1 != 1) + v4;\n}" + }, + { + "index": 715, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int *data;\n\n int size;\n\n} str_to_tuple_result;\n\n\n\n", + "func": "str_to_tuple_result func0(const char *test_str) {\n str_to_tuple_result result;\n int count = 1;\n for (const char *p = test_str; *p; p++) {\n if (*p == ',') count++;\n }\n result.size = count;\n result.data = malloc(count * sizeof(int));\n if (!result.data) {\n perror(\"malloc failed\");\n exit(1);\n }\n char *copy = strdup(test_str);\n char *token = strtok(copy, \", \");\n int idx = 0;\n while (token != NULL && idx < count) {\n result.data[idx++] = atoi(token);\n token = strtok(NULL, \", \");\n }\n free(copy);\n return result;\n}", + "test": "int main() {\n\n // Test case 1\n\n str_to_tuple_result t1 = func0(\"1, -5, 4, 6, 7\");\n\n int expected1[] = {1, -5, 4, 6, 7};\n\n assert(t1.size == 5);\n\n for(int i = 0; i < 5; i++) {\n\n assert(t1.data[i] == expected1[i]);\n\n }\n\n free(t1.data);\n\n\n\n // Test case 2\n\n str_to_tuple_result t2 = func0(\"1, 2, 3, 4, 5\");\n\n int expected2[] = {1, 2, 3, 4, 5};\n\n assert(t2.size == 5);\n\n for(int i = 0; i < 5; i++) {\n\n assert(t2.data[i] == expected2[i]);\n\n }\n\n free(t2.data);\n\n\n\n // Test case 3\n\n str_to_tuple_result t3 = func0(\"4, 6, 9, 11, 13, 14\");\n\n int expected3[] = {4, 6, 9, 11, 13, 14};\n\n assert(t3.size == 6);\n\n for(int i = 0; i < 6; i++) {\n\n assert(t3.data[i] == expected3[i]);\n\n }\n\n free(t3.data);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x48,%rsp\nmov %rdi,-0x48(%rbp)\nmovl $0x1,-0x40(%rbp)\nmov -0x48(%rbp),%rax\nmov %rax,-0x38(%rbp)\njmp 127f \nmov -0x38(%rbp),%rax\nmovzbl (%rax),%eax\ncmp $0x2c,%al\njne 127a \naddl $0x1,-0x40(%rbp)\naddq $0x1,-0x38(%rbp)\nmov -0x38(%rbp),%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 126b \nmov -0x40(%rbp),%eax\nmov %eax,-0x18(%rbp)\nmov -0x40(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 1100 \nmov %rax,-0x20(%rbp)\nmov -0x20(%rbp),%rax\ntest %rax,%rax\njne 12c4 \nlea 0xd53(%rip),%rdi\ncallq 1110 \nmov $0x1,%edi\ncallq 1140 \nmov -0x48(%rbp),%rax\nmov %rax,%rdi\ncallq 1150 \nmov %rax,-0x28(%rbp)\nmov -0x28(%rbp),%rax\nlea 0xd37(%rip),%rsi\nmov %rax,%rdi\ncallq 1120 \nmov %rax,-0x30(%rbp)\nmovl $0x0,-0x3c(%rbp)\njmp 132e \nmov -0x20(%rbp),%rcx\nmov -0x3c(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x3c(%rbp)\ncltq\nshl $0x2,%rax\nlea (%rcx,%rax,1),%rbx\nmov -0x30(%rbp),%rax\nmov %rax,%rdi\ncallq 1130 \nmov %eax,(%rbx)\nlea 0xcf6(%rip),%rsi\nmov $0x0,%edi\ncallq 1120 \nmov %rax,-0x30(%rbp)\ncmpq $0x0,-0x30(%rbp)\nje 133d \nmov -0x3c(%rbp),%eax\ncmp -0x40(%rbp),%eax\njl 12f4 \nmov -0x28(%rbp),%rax\nmov %rax,%rdi\ncallq 10d0 \nmov -0x20(%rbp),%rax\nmov -0x18(%rbp),%rdx\nadd $0x48,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 48h\nmov [rbp+s], rdi\nmov [rbp+var_40], 1\nmov rax, [rbp+s]\nmov [rbp+var_38], rax\njmp short loc_127F\nloc_126B:\nmov rax, [rbp+var_38]\nmovzx eax, byte ptr [rax]\ncmp al, 2Ch ; ','\njnz short loc_127A\nadd [rbp+var_40], 1\nloc_127A:\nadd [rbp+var_38], 1\nloc_127F:\nmov rax, [rbp+var_38]\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_126B\nmov eax, [rbp+var_40]\nmov dword ptr [rbp+var_18], eax\nmov eax, [rbp+var_40]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_20], rax\nmov rax, [rbp+var_20]\ntest rax, rax\njnz short loc_12C7\nlea rax, s; \"malloc failed\"\nmov rdi, rax; s\ncall _perror\nmov edi, 1; status\ncall _exit\nloc_12C7:\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strdup\nmov [rbp+var_28], rax\nmov rax, [rbp+var_28]\nlea rdx, delim; \", \"\nmov rsi, rdx; delim\nmov rdi, rax; s\ncall _strtok\nmov [rbp+nptr], rax\nmov [rbp+var_3C], 0\njmp short loc_1337\nloc_12FA:\nmov rcx, [rbp+var_20]\nmov eax, [rbp+var_3C]\nlea edx, [rax+1]\nmov [rbp+var_3C], edx\ncdqe\nshl rax, 2\nlea rbx, [rcx+rax]\nmov rax, [rbp+nptr]\nmov rdi, rax; nptr\ncall _atoi\nmov [rbx], eax\nlea rax, delim; \", \"\nmov rsi, rax; delim\nmov edi, 0; s\ncall _strtok\nmov [rbp+nptr], rax\nloc_1337:\ncmp [rbp+nptr], 0\njz short loc_1346\nmov eax, [rbp+var_3C]\ncmp eax, [rbp+var_40]\njl short loc_12FA\nloc_1346:\nmov rax, [rbp+var_28]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_20]\nmov rdx, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(const char *a1)\n{\n int v1; // eax\n int v3; // [rsp+10h] [rbp-40h]\n int j; // [rsp+14h] [rbp-3Ch]\n const char *i; // [rsp+18h] [rbp-38h]\n const char *nptr; // [rsp+20h] [rbp-30h]\n char *v7; // [rsp+28h] [rbp-28h]\n _DWORD *v8; // [rsp+30h] [rbp-20h]\n\n v3 = 1;\n for ( i = a1; *i; ++i )\n {\n if ( *i == 44 )\n ++v3;\n }\n v8 = malloc(4LL * v3);\n if ( !v8 )\n {\n perror(\"malloc failed\");\n exit(1);\n }\n v7 = strdup(a1);\n nptr = strtok(v7, \", \");\n for ( j = 0; nptr && j < v3; ++j )\n {\n v1 = j;\n v8[v1] = atoi(nptr);\n nptr = strtok(0LL, \", \");\n }\n free(v7);\n return v8;\n}", + "ida_strip_asm": "sub_1249:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 48h\nmov [rbp+s], rdi\nmov [rbp+var_40], 1\nmov rax, [rbp+s]\nmov [rbp+var_38], rax\njmp short loc_127F\nloc_126B:\nmov rax, [rbp+var_38]\nmovzx eax, byte ptr [rax]\ncmp al, 2Ch ; ','\njnz short loc_127A\nadd [rbp+var_40], 1\nloc_127A:\nadd [rbp+var_38], 1\nloc_127F:\nmov rax, [rbp+var_38]\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_126B\nmov eax, [rbp+var_40]\nmov dword ptr [rbp+var_18], eax\nmov eax, [rbp+var_40]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_20], rax\nmov rax, [rbp+var_20]\ntest rax, rax\njnz short loc_12C7\nlea rax, s; \"malloc failed\"\nmov rdi, rax; s\ncall _perror\nmov edi, 1; status\ncall _exit\nloc_12C7:\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strdup\nmov [rbp+var_28], rax\nmov rax, [rbp+var_28]\nlea rdx, delim; \", \"\nmov rsi, rdx; delim\nmov rdi, rax; s\ncall _strtok\nmov [rbp+nptr], rax\nmov [rbp+var_3C], 0\njmp short loc_1337\nloc_12FA:\nmov rcx, [rbp+var_20]\nmov eax, [rbp+var_3C]\nlea edx, [rax+1]\nmov [rbp+var_3C], edx\ncdqe\nshl rax, 2\nlea rbx, [rcx+rax]\nmov rax, [rbp+nptr]\nmov rdi, rax; nptr\ncall _atoi\nmov [rbx], eax\nlea rax, delim; \", \"\nmov rsi, rax; delim\nmov edi, 0; s\ncall _strtok\nmov [rbp+nptr], rax\nloc_1337:\ncmp [rbp+nptr], 0\njz short loc_1346\nmov eax, [rbp+var_3C]\ncmp eax, [rbp+var_40]\njl short loc_12FA\nloc_1346:\nmov rax, [rbp+var_28]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_20]\nmov rdx, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1249(const char *a1)\n{\n int v1; // eax\n int v3; // [rsp+10h] [rbp-40h]\n int j; // [rsp+14h] [rbp-3Ch]\n const char *i; // [rsp+18h] [rbp-38h]\n const char *nptr; // [rsp+20h] [rbp-30h]\n char *v7; // [rsp+28h] [rbp-28h]\n _DWORD *v8; // [rsp+30h] [rbp-20h]\n\n v3 = 1;\n for ( i = a1; *i; ++i )\n {\n if ( *i == 44 )\n ++v3;\n }\n v8 = malloc(4LL * v3);\n if ( !v8 )\n {\n perror(\"malloc failed\");\n exit(1);\n }\n v7 = strdup(a1);\n nptr = strtok(v7, \", \");\n for ( j = 0; nptr && j < v3; ++j )\n {\n v1 = j;\n v8[v1] = atoi(nptr);\n nptr = strtok(0LL, \", \");\n }\n free(v7);\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1249(const char *a1) {\n int v1;\n int v3;\n int j;\n const char *i;\n const char *nptr;\n char *v7;\n uint32_t *v8;\n v3 = 1;\n for (i = a1; *i; ++i) {\n if (*i == 44) ++v3;\n }\n v8 = malloc(4LL * v3);\n if (!v8) {\n perror(\"malloc failed\");\n exit(1);\n }\n v7 = strdup(a1);\n nptr = strtok(v7, \", \");\n for (j = 0; nptr && j < v3; ++j) {\n v1 = j;\n v8[v1] = atoi(nptr);\n nptr = strtok(0LL, \", \");\n }\n free(v7);\n return v8;\n}", + "ida_pseudo_norm": "uint32_t *func0(const char *a1) {\n int v1;\n int v3;\n int j;\n const char *i;\n const char *nptr;\n char *v7;\n uint32_t *v8;\n v3 = 1;\n for (i = a1; *i; ++i) {\n if (*i == 44) ++v3;\n }\n v8 = malloc(4LL * v3);\n if (!v8) {\n perror(\"malloc failed\");\n exit(1);\n }\n v7 = strdup(a1);\n nptr = strtok(v7, \", \");\n for (j = 0; nptr && j < v3; ++j) {\n v1 = j;\n v8[v1] = atoi(nptr);\n nptr = strtok(0LL, \", \");\n }\n free(v7);\n return v8;\n}" + }, + { + "index": 715, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int *data;\n\n int size;\n\n} str_to_tuple_result;\n\n\n\n", + "func": "str_to_tuple_result func0(const char *test_str) {\n str_to_tuple_result result;\n int count = 1;\n for (const char *p = test_str; *p; p++) {\n if (*p == ',') count++;\n }\n result.size = count;\n result.data = malloc(count * sizeof(int));\n if (!result.data) {\n perror(\"malloc failed\");\n exit(1);\n }\n char *copy = strdup(test_str);\n char *token = strtok(copy, \", \");\n int idx = 0;\n while (token != NULL && idx < count) {\n result.data[idx++] = atoi(token);\n token = strtok(NULL, \", \");\n }\n free(copy);\n return result;\n}", + "test": "int main() {\n\n // Test case 1\n\n str_to_tuple_result t1 = func0(\"1, -5, 4, 6, 7\");\n\n int expected1[] = {1, -5, 4, 6, 7};\n\n assert(t1.size == 5);\n\n for(int i = 0; i < 5; i++) {\n\n assert(t1.data[i] == expected1[i]);\n\n }\n\n free(t1.data);\n\n\n\n // Test case 2\n\n str_to_tuple_result t2 = func0(\"1, 2, 3, 4, 5\");\n\n int expected2[] = {1, 2, 3, 4, 5};\n\n assert(t2.size == 5);\n\n for(int i = 0; i < 5; i++) {\n\n assert(t2.data[i] == expected2[i]);\n\n }\n\n free(t2.data);\n\n\n\n // Test case 3\n\n str_to_tuple_result t3 = func0(\"4, 6, 9, 11, 13, 14\");\n\n int expected3[] = {4, 6, 9, 11, 13, 14};\n\n assert(t3.size == 6);\n\n for(int i = 0; i < 6; i++) {\n\n assert(t3.data[i] == expected3[i]);\n\n }\n\n free(t3.data);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nmovzbl (%rdi),%eax\ntest %al,%al\nje 1317 \nmov %rdi,%rdx\nmov $0x1,%ebp\ncmp $0x2c,%al\nsete %al\nmovzbl %al,%eax\nadd %eax,%ebp\nadd $0x1,%rdx\nmovzbl (%rdx),%eax\ntest %al,%al\njne 126b \nmovslq %ebp,%rdi\nshl $0x2,%rdi\ncallq 1110 \nmov %rax,%r12\ntest %rax,%rax\nje 1321 \nmov %rbx,%rdi\ncallq 1150 \nmov %rax,%r14\nlea 0xd68(%rip),%rsi\nmov %rax,%rdi\ncallq 1130 \nmov %rax,%rdi\ntest %rax,%rax\nje 1301 \ntest %ebp,%ebp\njle 1301 \nmov $0x1,%ebx\nlea 0xd48(%rip),%r13\nmov $0xa,%edx\nmov $0x0,%esi\ncallq 1100 \nmov %eax,-0x4(%r12,%rbx,4)\nmov %r13,%rsi\nmov $0x0,%edi\ncallq 1130 \nmov %rax,%rdi\ntest %rax,%rax\nsetne %dl\ncmp %ebx,%ebp\nsetg %al\nadd $0x1,%rbx\ntest %al,%dl\njne 12ca \nmov %r14,%rdi\ncallq 10d0 \nmov %ebp,%edx\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nmov $0x1,%ebp\njmpq 1280 \nlea 0xcdc(%rip),%rdi\ncallq 1120 \nmov $0x1,%edi\ncallq 1140 \n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nmovzx eax, byte ptr [rdi]\ntest al, al\njz loc_1317\nmov rdx, rdi\nmov ebp, 1\nloc_126B:\ncmp al, 2Ch ; ','\nsetz al\nmovzx eax, al\nadd ebp, eax\nadd rdx, 1\nmovzx eax, byte ptr [rdx]\ntest al, al\njnz short loc_126B\nloc_1280:\nmovsxd rdi, ebp\nshl rdi, 2; size\ncall _malloc\nmov r12, rax\ntest rax, rax\njz loc_1321\nmov rdi, rbx; s\ncall _strdup\nmov r14, rax\nlea rsi, delim; \", \"\nmov rdi, rax; s\ncall _strtok\nmov rdi, rax; nptr\ntest rax, rax\njz short loc_1301\ntest ebp, ebp\njle short loc_1301\nmov ebx, 1\nlea r13, delim; \", \"\nloc_12CA:\nmov edx, 0Ah; base\nmov esi, 0; endptr\ncall _strtol\nmov [r12+rbx*4-4], eax\nmov rsi, r13; delim\nmov edi, 0; s\ncall _strtok\nmov rdi, rax\ntest rax, rax\nsetnz dl\ncmp ebp, ebx\nsetnle al\nadd rbx, 1\ntest dl, al\njnz short loc_12CA\nloc_1301:\nmov rdi, r14; ptr\ncall _free\nmov edx, ebp\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1317:\nmov ebp, 1\njmp loc_1280\nloc_1321:\nlea rdi, s; \"malloc failed\"\ncall _perror\nmov edi, 1; status\ncall _exit", + "ida_pseudo": "_DWORD *__fastcall func0(char *s)\n{\n char v1; // al\n char *v2; // rdx\n int v3; // ebp\n _DWORD *v4; // r12\n char *v5; // r14\n char *v6; // rdi\n __int64 v7; // rbx\n bool v8; // al\n\n v1 = *s;\n if ( *s )\n {\n v2 = s;\n v3 = 1;\n do\n {\n v3 += v1 == 44;\n v1 = *++v2;\n }\n while ( *v2 );\n }\n else\n {\n v3 = 1;\n }\n v4 = malloc(4LL * v3);\n if ( !v4 )\n {\n perror(\"malloc failed\");\n exit(1);\n }\n v5 = strdup(s);\n v6 = strtok(v5, \", \");\n if ( v6 && v3 > 0 )\n {\n v7 = 1LL;\n do\n {\n v4[v7 - 1] = strtol(v6, 0LL, 10);\n v6 = strtok(0LL, \", \");\n v8 = v3 > (int)v7++;\n }\n while ( v8 && v6 != 0LL );\n }\n free(v5);\n return v4;\n}", + "ida_strip_asm": "sub_1249:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nmovzx eax, byte ptr [rdi]\ntest al, al\njz loc_1317\nmov rdx, rdi\nmov ebp, 1\nloc_126B:\ncmp al, 2Ch ; ','\nsetz al\nmovzx eax, al\nadd ebp, eax\nadd rdx, 1\nmovzx eax, byte ptr [rdx]\ntest al, al\njnz short loc_126B\nloc_1280:\nmovsxd rdi, ebp\nshl rdi, 2; size\ncall _malloc\nmov r12, rax\ntest rax, rax\njz loc_1321\nmov rdi, rbx; s\ncall _strdup\nmov r14, rax\nlea rsi, delim; \", \"\nmov rdi, rax; s\ncall _strtok\nmov rdi, rax; nptr\ntest rax, rax\njz short loc_1301\ntest ebp, ebp\njle short loc_1301\nmov ebx, 1\nlea r13, delim; \", \"\nloc_12CA:\nmov edx, 0Ah; base\nmov esi, 0; endptr\ncall _strtol\nmov [r12+rbx*4-4], eax\nmov rsi, r13; delim\nmov edi, 0; s\ncall _strtok\nmov rdi, rax\ntest rax, rax\nsetnz dl\ncmp ebp, ebx\nsetnle al\nadd rbx, 1\ntest dl, al\njnz short loc_12CA\nloc_1301:\nmov rdi, r14; ptr\ncall _free\nmov edx, ebp\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1317:\nmov ebp, 1\njmp loc_1280\nloc_1321:\nlea rdi, s; \"malloc failed\"\ncall _perror\nmov edi, 1; status\ncall _exit", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1249(char *s)\n{\n char v1; // al\n char *v2; // rdx\n int v3; // ebp\n _DWORD *v4; // r12\n char *v5; // r14\n char *v6; // rdi\n __int64 v7; // rbx\n bool v8; // al\n\n v1 = *s;\n if ( *s )\n {\n v2 = s;\n v3 = 1;\n do\n {\n v3 += v1 == 44;\n v1 = *++v2;\n }\n while ( *v2 );\n }\n else\n {\n v3 = 1;\n }\n v4 = malloc(4LL * v3);\n if ( !v4 )\n {\n perror(\"malloc failed\");\n exit(1);\n }\n v5 = strdup(s);\n v6 = strtok(v5, \", \");\n if ( v6 && v3 > 0 )\n {\n v7 = 1LL;\n do\n {\n v4[v7 - 1] = strtol(v6, 0LL, 10);\n v6 = strtok(0LL, \", \");\n v8 = v3 > (int)v7++;\n }\n while ( v8 && v6 != 0LL );\n }\n free(v5);\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1249(char *s) {\n char v1;\n char *v2;\n int v3;\n uint32_t *v4;\n char *v5;\n char *v6;\n long long v7;\n bool v8;\n v1 = *s;\n if (*s) {\n v2 = s;\n v3 = 1;\n do {\n v3 += v1 == 44;\n v1 = *++v2;\n } while (*v2);\n } else {\n v3 = 1;\n }\n v4 = malloc(4LL * v3);\n if (!v4) {\n perror(\"malloc failed\");\n exit(1);\n }\n v5 = strdup(s);\n v6 = strtok(v5, \", \");\n if (v6 && v3 > 0) {\n v7 = 1LL;\n do {\n v4[v7 - 1] = strtol(v6, 0LL, 10);\n v6 = strtok(0LL, \", \");\n v8 = v3 > (int)v7++;\n } while (v8 && v6 != 0LL);\n }\n free(v5);\n return v4;\n}", + "ida_pseudo_norm": "uint32_t *func0(char *s) {\n char v1;\n char *v2;\n int v3;\n uint32_t *v4;\n char *v5;\n char *v6;\n long long v7;\n bool v8;\n v1 = *s;\n if (*s) {\n v2 = s;\n v3 = 1;\n do {\n v3 += v1 == 44;\n v1 = *++v2;\n } while (*v2);\n } else {\n v3 = 1;\n }\n v4 = malloc(4LL * v3);\n if (!v4) {\n perror(\"malloc failed\");\n exit(1);\n }\n v5 = strdup(s);\n v6 = strtok(v5, \", \");\n if (v6 && v3 > 0) {\n v7 = 1LL;\n do {\n v4[v7 - 1] = strtol(v6, 0LL, 10);\n v6 = strtok(0LL, \", \");\n v8 = v3 > (int)v7++;\n } while (v8 && v6 != 0LL);\n }\n free(v5);\n return v4;\n}" + }, + { + "index": 715, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int *data;\n\n int size;\n\n} str_to_tuple_result;\n\n\n\n", + "func": "str_to_tuple_result func0(const char *test_str) {\n str_to_tuple_result result;\n int count = 1;\n for (const char *p = test_str; *p; p++) {\n if (*p == ',') count++;\n }\n result.size = count;\n result.data = malloc(count * sizeof(int));\n if (!result.data) {\n perror(\"malloc failed\");\n exit(1);\n }\n char *copy = strdup(test_str);\n char *token = strtok(copy, \", \");\n int idx = 0;\n while (token != NULL && idx < count) {\n result.data[idx++] = atoi(token);\n token = strtok(NULL, \", \");\n }\n free(copy);\n return result;\n}", + "test": "int main() {\n\n // Test case 1\n\n str_to_tuple_result t1 = func0(\"1, -5, 4, 6, 7\");\n\n int expected1[] = {1, -5, 4, 6, 7};\n\n assert(t1.size == 5);\n\n for(int i = 0; i < 5; i++) {\n\n assert(t1.data[i] == expected1[i]);\n\n }\n\n free(t1.data);\n\n\n\n // Test case 2\n\n str_to_tuple_result t2 = func0(\"1, 2, 3, 4, 5\");\n\n int expected2[] = {1, 2, 3, 4, 5};\n\n assert(t2.size == 5);\n\n for(int i = 0; i < 5; i++) {\n\n assert(t2.data[i] == expected2[i]);\n\n }\n\n free(t2.data);\n\n\n\n // Test case 3\n\n str_to_tuple_result t3 = func0(\"4, 6, 9, 11, 13, 14\");\n\n int expected3[] = {4, 6, 9, 11, 13, 14};\n\n assert(t3.size == 6);\n\n for(int i = 0; i < 6; i++) {\n\n assert(t3.data[i] == expected3[i]);\n\n }\n\n free(t3.data);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\nmov %rdi,%rbp\npush %rbx\nmovzbl (%rdi),%eax\ntest %al,%al\nje 1548 \nmov %rdi,%rdx\nmov $0x1,%r14d\nnopl 0x0(%rax,%rax,1)\ncmp $0x2c,%al\nsete %al\nadd $0x1,%rdx\nmovzbl %al,%eax\nadd %eax,%r14d\nmovzbl (%rdx),%eax\ntest %al,%al\njne 1498 \nmovslq %r14d,%rdi\nshl $0x2,%rdi\ncallq 1110 \nmov %rax,%r12\ntest %rax,%rax\nje 1558 \nmov %rbp,%rdi\nmov $0x1,%ebx\nlea 0xb3d(%rip),%r13\ncallq 1150 \nlea 0xb31(%rip),%rsi\nmov %rax,%rdi\nmov %rax,%rbp\ncallq 1130 \nmov %rax,%rdi\ntest %rax,%rax\nje 152a \nnopl 0x0(%rax)\nmov $0xa,%edx\nxor %esi,%esi\ncallq 1100 \nxor %edi,%edi\nmov %r13,%rsi\nmov %eax,-0x4(%r12,%rbx,4)\ncallq 1130 \ntest %rax,%rax\nmov %rax,%rdi\nsetne %dl\ncmp %ebx,%r14d\nsetg %al\nadd $0x1,%rbx\ntest %al,%dl\njne 14f8 \nmov %rbp,%rdi\ncallq 10d0 \npop %rbx\nmov %r14d,%edx\npop %rbp\nmov %r12,%rax\npop %r12\npop %r13\npop %r14\nretq\nnopl 0x0(%rax)\nmov $0x4,%edi\nmov $0x1,%r14d\njmpq 14b5 \nlea 0xaa5(%rip),%rdi\ncallq 1120 \nmov $0x1,%edi\ncallq 1140 \nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nmovzx eax, byte ptr [rdi]\ntest al, al\njz loc_1540\nmov rdx, rdi\nmov r14d, 1\nnop dword ptr [rax+rax+00h]\nloc_1488:\ncmp al, 2Ch ; ','\nsetz al\nadd rdx, 1\nmovzx eax, al\nadd r14d, eax\nmovzx eax, byte ptr [rdx]\ntest al, al\njnz short loc_1488\nmovsxd rdi, r14d\nshl rdi, 2; size\nloc_14A5:\ncall _malloc\nmov rbx, rax\ntest rax, rax\njz func0_cold\nmov rdi, rbp; s\nlea rbp, delim; \", \"\ncall _strdup\nmov rsi, rbp; delim\nmov rdi, rax; s\nmov r12, rax\ncall _strtok\nmov rdi, rax; nptr\ntest rax, rax\njz short loc_1522\nmov r13d, 1\ntest r14d, r14d\njle short loc_1522\nnop word ptr [rax+rax+00000000h]\nloc_14F0:\nmov edx, 0Ah; base\nxor esi, esi; endptr\ncall _strtol\nxor edi, edi; s\nmov rsi, rbp; delim\nmov [rbx+r13*4-4], eax\ncall _strtok\ntest rax, rax\nmov rdi, rax\nsetnz dl\ncmp r14d, r13d\nsetnle al\nadd r13, 1\ntest dl, al\njnz short loc_14F0\nloc_1522:\nmov rdi, r12; ptr\ncall _free\nmov edx, r14d\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1540:\nmov edi, 4\nmov r14d, 1\njmp loc_14A5", + "ida_pseudo": "_DWORD *__fastcall func0(char *s)\n{\n char v2; // al\n char *v3; // rdx\n int v4; // r14d\n size_t v5; // rdi\n _DWORD *v6; // rbx\n char *v7; // r12\n char *v8; // rdi\n __int64 v9; // r13\n bool v10; // al\n\n v2 = *s;\n if ( *s )\n {\n v3 = s;\n v4 = 1;\n do\n {\n ++v3;\n v4 += v2 == 44;\n v2 = *v3;\n }\n while ( *v3 );\n v5 = 4LL * v4;\n }\n else\n {\n v5 = 4LL;\n v4 = 1;\n }\n v6 = malloc(v5);\n if ( !v6 )\n func0_cold();\n v7 = strdup(s);\n v8 = strtok(v7, \", \");\n if ( v8 )\n {\n v9 = 1LL;\n if ( v4 > 0 )\n {\n do\n {\n v6[v9 - 1] = strtol(v8, 0LL, 10);\n v8 = strtok(0LL, \", \");\n v10 = v4 > (int)v9++;\n }\n while ( v10 && v8 != 0LL );\n }\n }\n free(v7);\n return v6;\n}", + "ida_strip_asm": "sub_1460:\nendbr64\npush r14\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nmovzx eax, byte ptr [rdi]\ntest al, al\njz loc_1540\nmov rdx, rdi\nmov r14d, 1\nnop dword ptr [rax+rax+00h]\nloc_1488:\ncmp al, 2Ch ; ','\nsetz al\nadd rdx, 1\nmovzx eax, al\nadd r14d, eax\nmovzx eax, byte ptr [rdx]\ntest al, al\njnz short loc_1488\nmovsxd rdi, r14d\nshl rdi, 2; size\nloc_14A5:\ncall _malloc\nmov rbx, rax\ntest rax, rax\njz loc_1160\nmov rdi, rbp; s\nlea rbp, delim; \", \"\ncall _strdup\nmov rsi, rbp; delim\nmov rdi, rax; s\nmov r12, rax\ncall _strtok\nmov rdi, rax; nptr\ntest rax, rax\njz short loc_1522\nmov r13d, 1\ntest r14d, r14d\njle short loc_1522\nnop word ptr [rax+rax+00000000h]\nloc_14F0:\nmov edx, 0Ah; base\nxor esi, esi; endptr\ncall _strtol\nxor edi, edi; s\nmov rsi, rbp; delim\nmov [rbx+r13*4-4], eax\ncall _strtok\ntest rax, rax\nmov rdi, rax\nsetnz dl\ncmp r14d, r13d\nsetnle al\nadd r13, 1\ntest dl, al\njnz short loc_14F0\nloc_1522:\nmov rdi, r12; ptr\ncall _free\nmov edx, r14d\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1540:\nmov edi, 4\nmov r14d, 1\njmp loc_14A5", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1460(char *s)\n{\n char v2; // al\n char *v3; // rdx\n int v4; // r14d\n size_t v5; // rdi\n _DWORD *v6; // rbx\n char *v7; // r12\n char *v8; // rdi\n __int64 v9; // r13\n bool v10; // al\n\n v2 = *s;\n if ( *s )\n {\n v3 = s;\n v4 = 1;\n do\n {\n ++v3;\n v4 += v2 == 44;\n v2 = *v3;\n }\n while ( *v3 );\n v5 = 4LL * v4;\n }\n else\n {\n v5 = 4LL;\n v4 = 1;\n }\n v6 = malloc(v5);\n if ( !v6 )\n {\n perror(\"malloc failed\");\n exit(1);\n }\n v7 = strdup(s);\n v8 = strtok(v7, \", \");\n if ( v8 )\n {\n v9 = 1LL;\n if ( v4 > 0 )\n {\n do\n {\n v6[v9 - 1] = strtol(v8, 0LL, 10);\n v8 = strtok(0LL, \", \");\n v10 = v4 > (int)v9++;\n }\n while ( v10 && v8 != 0LL );\n }\n }\n free(v7);\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1460(char *s) {\n char v2;\n char *v3;\n int v4;\n unsigned int v5;\n uint32_t *v6;\n char *v7;\n char *v8;\n long long v9;\n bool v10;\n v2 = *s;\n if (*s) {\n v3 = s;\n v4 = 1;\n do {\n ++v3;\n v4 += v2 == 44;\n v2 = *v3;\n } while (*v3);\n v5 = 4LL * v4;\n } else {\n v5 = 4LL;\n v4 = 1;\n }\n v6 = malloc(v5);\n if (!v6) {\n perror(\"malloc failed\");\n exit(1);\n }\n v7 = strdup(s);\n v8 = strtok(v7, \", \");\n if (v8) {\n v9 = 1LL;\n if (v4 > 0) {\n do {\n v6[v9 - 1] = strtol(v8, 0LL, 10);\n v8 = strtok(0LL, \", \");\n v10 = v4 > (int)v9++;\n } while (v10 && v8 != 0LL);\n }\n }\n free(v7);\n return v6;\n}", + "ida_pseudo_norm": "uint32_t *func0(char *s) {\n char v2;\n char *v3;\n int v4;\n unsigned int v5;\n uint32_t *v6;\n char *v7;\n char *v8;\n long long v9;\n bool v10;\n v2 = *s;\n if (*s) {\n v3 = s;\n v4 = 1;\n do {\n ++v3;\n v4 += v2 == 44;\n v2 = *v3;\n } while (*v3);\n v5 = 4LL * v4;\n } else {\n v5 = 4LL;\n v4 = 1;\n }\n v6 = malloc(v5);\n if (!v6) func0_cold();\n v7 = strdup(s);\n v8 = strtok(v7, \", \");\n if (v8) {\n v9 = 1LL;\n if (v4 > 0) {\n do {\n v6[v9 - 1] = strtol(v8, 0LL, 10);\n v8 = strtok(0LL, \", \");\n v10 = v4 > (int)v9++;\n } while (v10 && v8 != 0LL);\n }\n }\n free(v7);\n return v6;\n}" + }, + { + "index": 715, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int *data;\n\n int size;\n\n} str_to_tuple_result;\n\n\n\n", + "func": "str_to_tuple_result func0(const char *test_str) {\n str_to_tuple_result result;\n int count = 1;\n for (const char *p = test_str; *p; p++) {\n if (*p == ',') count++;\n }\n result.size = count;\n result.data = malloc(count * sizeof(int));\n if (!result.data) {\n perror(\"malloc failed\");\n exit(1);\n }\n char *copy = strdup(test_str);\n char *token = strtok(copy, \", \");\n int idx = 0;\n while (token != NULL && idx < count) {\n result.data[idx++] = atoi(token);\n token = strtok(NULL, \", \");\n }\n free(copy);\n return result;\n}", + "test": "int main() {\n\n // Test case 1\n\n str_to_tuple_result t1 = func0(\"1, -5, 4, 6, 7\");\n\n int expected1[] = {1, -5, 4, 6, 7};\n\n assert(t1.size == 5);\n\n for(int i = 0; i < 5; i++) {\n\n assert(t1.data[i] == expected1[i]);\n\n }\n\n free(t1.data);\n\n\n\n // Test case 2\n\n str_to_tuple_result t2 = func0(\"1, 2, 3, 4, 5\");\n\n int expected2[] = {1, 2, 3, 4, 5};\n\n assert(t2.size == 5);\n\n for(int i = 0; i < 5; i++) {\n\n assert(t2.data[i] == expected2[i]);\n\n }\n\n free(t2.data);\n\n\n\n // Test case 3\n\n str_to_tuple_result t3 = func0(\"4, 6, 9, 11, 13, 14\");\n\n int expected3[] = {4, 6, 9, 11, 13, 14};\n\n assert(t3.size == 6);\n\n for(int i = 0; i < 6; i++) {\n\n assert(t3.data[i] == expected3[i]);\n\n }\n\n free(t3.data);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\nmov %rdi,%rbp\npush %rbx\nmovzbl (%rdi),%eax\ntest %al,%al\nje 1548 \nmov %rdi,%rdx\nmov $0x1,%r14d\nnopl 0x0(%rax,%rax,1)\ncmp $0x2c,%al\nsete %al\nadd $0x1,%rdx\nmovzbl %al,%eax\nadd %eax,%r14d\nmovzbl (%rdx),%eax\ntest %al,%al\njne 1498 \nmovslq %r14d,%rdi\nshl $0x2,%rdi\ncallq 1110 \nmov %rax,%r12\ntest %rax,%rax\nje 1558 \nmov %rbp,%rdi\nmov $0x1,%ebx\nlea 0xb3d(%rip),%r13\ncallq 1150 \nlea 0xb31(%rip),%rsi\nmov %rax,%rdi\nmov %rax,%rbp\ncallq 1130 \nmov %rax,%rdi\ntest %rax,%rax\nje 152a \nnopl 0x0(%rax)\nmov $0xa,%edx\nxor %esi,%esi\ncallq 1100 \nxor %edi,%edi\nmov %r13,%rsi\nmov %eax,-0x4(%r12,%rbx,4)\ncallq 1130 \ntest %rax,%rax\nmov %rax,%rdi\nsetne %dl\ncmp %ebx,%r14d\nsetg %al\nadd $0x1,%rbx\ntest %al,%dl\njne 14f8 \nmov %rbp,%rdi\ncallq 10d0 \npop %rbx\nmov %r14d,%edx\npop %rbp\nmov %r12,%rax\npop %r12\npop %r13\npop %r14\nretq\nnopl 0x0(%rax)\nmov $0x4,%edi\nmov $0x1,%r14d\njmpq 14b5 \nlea 0xaa5(%rip),%rdi\ncallq 1120 \nmov $0x1,%edi\ncallq 1140 \nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nmovzx eax, byte ptr [rdi]\ntest al, al\njz loc_14E0\nmov rdx, rdi\nmov r14d, 1\nnop dword ptr [rax+rax+00h]\nloc_1428:\ncmp al, 2Ch ; ','\nsetz al\nadd rdx, 1\nmovzx eax, al\nadd r14d, eax\nmovzx eax, byte ptr [rdx]\ntest al, al\njnz short loc_1428\nmovsxd rdi, r14d\nshl rdi, 2; size\nloc_1445:\ncall _malloc\nmov rbx, rax\ntest rax, rax\njz func0_cold\nmov rdi, rbp; s\nlea rbp, delim; \", \"\ncall _strdup\nmov rsi, rbp; delim\nmov rdi, rax; s\nmov r12, rax\ncall _strtok\nmov rdi, rax; nptr\ntest rax, rax\njz short loc_14C2\nmov r13d, 1\ntest r14d, r14d\njle short loc_14C2\nnop word ptr [rax+rax+00000000h]\nloc_1490:\nmov edx, 0Ah; base\nxor esi, esi; endptr\ncall _strtol\nxor edi, edi; s\nmov rsi, rbp; delim\nmov [rbx+r13*4-4], eax\ncall _strtok\ntest rax, rax\nmov rdi, rax\nsetnz dl\ncmp r14d, r13d\nsetnle al\nadd r13, 1\ntest dl, al\njnz short loc_1490\nloc_14C2:\nmov rdi, r12; ptr\ncall _free\nmov edx, r14d\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_14E0:\nmov edi, 4\nmov r14d, 1\njmp loc_1445", + "ida_pseudo": "_DWORD *__fastcall func0(char *s)\n{\n char v2; // al\n char *v3; // rdx\n int v4; // r14d\n size_t v5; // rdi\n _DWORD *v6; // rbx\n char *v7; // r12\n char *v8; // rdi\n __int64 v9; // r13\n bool v10; // al\n\n v2 = *s;\n if ( *s )\n {\n v3 = s;\n v4 = 1;\n do\n {\n ++v3;\n v4 += v2 == 44;\n v2 = *v3;\n }\n while ( *v3 );\n v5 = 4LL * v4;\n }\n else\n {\n v5 = 4LL;\n v4 = 1;\n }\n v6 = malloc(v5);\n if ( !v6 )\n func0_cold();\n v7 = strdup(s);\n v8 = strtok(v7, \", \");\n if ( v8 )\n {\n v9 = 1LL;\n if ( v4 > 0 )\n {\n do\n {\n v6[v9 - 1] = strtol(v8, 0LL, 10);\n v8 = strtok(0LL, \", \");\n v10 = v4 > (int)v9++;\n }\n while ( v10 && v8 != 0LL );\n }\n }\n free(v7);\n return v6;\n}", + "ida_strip_asm": "sub_1400:\nendbr64\npush r14\npush r13\npush r12\npush rbp\nmov rbp, rdi\npush rbx\nmovzx eax, byte ptr [rdi]\ntest al, al\njz loc_14E0\nmov rdx, rdi\nmov r14d, 1\nnop dword ptr [rax+rax+00h]\nloc_1428:\ncmp al, 2Ch ; ','\nsetz al\nadd rdx, 1\nmovzx eax, al\nadd r14d, eax\nmovzx eax, byte ptr [rdx]\ntest al, al\njnz short loc_1428\nmovsxd rdi, r14d\nshl rdi, 2; size\nloc_1445:\ncall _malloc\nmov rbx, rax\ntest rax, rax\njz loc_1140\nmov rdi, rbp; s\nlea rbp, delim; \", \"\ncall _strdup\nmov rsi, rbp; delim\nmov rdi, rax; s\nmov r12, rax\ncall _strtok\nmov rdi, rax; nptr\ntest rax, rax\njz short loc_14C2\nmov r13d, 1\ntest r14d, r14d\njle short loc_14C2\nnop word ptr [rax+rax+00000000h]\nloc_1490:\nmov edx, 0Ah; base\nxor esi, esi; endptr\ncall _strtol\nxor edi, edi; s\nmov rsi, rbp; delim\nmov [rbx+r13*4-4], eax\ncall _strtok\ntest rax, rax\nmov rdi, rax\nsetnz dl\ncmp r14d, r13d\nsetnle al\nadd r13, 1\ntest dl, al\njnz short loc_1490\nloc_14C2:\nmov rdi, r12; ptr\ncall _free\nmov edx, r14d\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_14E0:\nmov edi, 4\nmov r14d, 1\njmp loc_1445", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1400(char *s)\n{\n char v2; // al\n char *v3; // rdx\n int v4; // r14d\n size_t v5; // rdi\n _DWORD *v6; // rbx\n char *v7; // r12\n char *v8; // rdi\n __int64 v9; // r13\n bool v10; // al\n\n v2 = *s;\n if ( *s )\n {\n v3 = s;\n v4 = 1;\n do\n {\n ++v3;\n v4 += v2 == 44;\n v2 = *v3;\n }\n while ( *v3 );\n v5 = 4LL * v4;\n }\n else\n {\n v5 = 4LL;\n v4 = 1;\n }\n v6 = malloc(v5);\n if ( !v6 )\n {\n perror(\"malloc failed\");\n exit(1);\n }\n v7 = strdup(s);\n v8 = strtok(v7, \", \");\n if ( v8 )\n {\n v9 = 1LL;\n if ( v4 > 0 )\n {\n do\n {\n v6[v9 - 1] = strtol(v8, 0LL, 10);\n v8 = strtok(0LL, \", \");\n v10 = v4 > (int)v9++;\n }\n while ( v10 && v8 != 0LL );\n }\n }\n free(v7);\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1400(char *s) {\n char v2;\n char *v3;\n int v4;\n unsigned int v5;\n uint32_t *v6;\n char *v7;\n char *v8;\n long long v9;\n bool v10;\n v2 = *s;\n if (*s) {\n v3 = s;\n v4 = 1;\n do {\n ++v3;\n v4 += v2 == 44;\n v2 = *v3;\n } while (*v3);\n v5 = 4LL * v4;\n } else {\n v5 = 4LL;\n v4 = 1;\n }\n v6 = malloc(v5);\n if (!v6) {\n perror(\"malloc failed\");\n exit(1);\n }\n v7 = strdup(s);\n v8 = strtok(v7, \", \");\n if (v8) {\n v9 = 1LL;\n if (v4 > 0) {\n do {\n v6[v9 - 1] = strtol(v8, 0LL, 10);\n v8 = strtok(0LL, \", \");\n v10 = v4 > (int)v9++;\n } while (v10 && v8 != 0LL);\n }\n }\n free(v7);\n return v6;\n}", + "ida_pseudo_norm": "uint32_t *func0(char *s) {\n char v2;\n char *v3;\n int v4;\n unsigned int v5;\n uint32_t *v6;\n char *v7;\n char *v8;\n long long v9;\n bool v10;\n v2 = *s;\n if (*s) {\n v3 = s;\n v4 = 1;\n do {\n ++v3;\n v4 += v2 == 44;\n v2 = *v3;\n } while (*v3);\n v5 = 4LL * v4;\n } else {\n v5 = 4LL;\n v4 = 1;\n }\n v6 = malloc(v5);\n if (!v6) func0_cold();\n v7 = strdup(s);\n v8 = strtok(v7, \", \");\n if (v8) {\n v9 = 1LL;\n if (v4 > 0) {\n do {\n v6[v9 - 1] = strtol(v8, 0LL, 10);\n v8 = strtok(0LL, \", \");\n v10 = v4 > (int)v9++;\n } while (v10 && v8 != 0LL);\n }\n }\n free(v7);\n return v6;\n}" + }, + { + "index": 716, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int a) {\n int perimeter = 4 * a;\n return perimeter;\n}", + "test": "int main() {\n\n assert(func0(10) == 40);\n\n assert(func0(5) == 20);\n\n assert(func0(4) == 16);\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov -0x14(%rbp),%eax\nshl $0x2,%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov eax, [rbp+var_14]\nshl eax, 2\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n return (unsigned int)(4 * a1);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov eax, [rbp+var_14]\nshl eax, 2\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n return (unsigned int)(4 * a1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) { return (unsigned int)(4 * a1); }", + "ida_pseudo_norm": "long long func0(int a1) { return (unsigned int)(4 * a1); }" + }, + { + "index": 717, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\ndouble avg_calc(double *ls, int len) {\n\n double mean = 0.0;\n\n if (len <= 1) {\n\n return ls[0];\n\n }\n\n for (int i = 0; i < len; i++) {\n\n mean += ls[i];\n\n }\n\n mean /= len;\n\n return mean;\n\n}\n\n\n\n", + "func": "double func0(double *data, int len) {\n if (len <= 1) {\n return 0.0;\n }\n double mean = avg_calc(data, len);\n double sd = 0.0;\n for (int i = 0; i < len; i++) {\n sd += (data[i] - mean) * (data[i] - mean);\n }\n sd = sqrt(sd / (len - 1));\n return sd;\n}", + "test": "int main() {\n\n double data1[] = {4, 2, 5, 8, 6};\n\n double data2[] = {1, 2, 3, 4, 5, 6, 7};\n\n double data3[] = {5, 9, 10, 15, 6, 4};\n\n\n\n assert(fabs(func0(data1, 5) - 2.23606797749979) < 1e-9);\n\n assert(fabs(func0(data2, 7) - 2.160246899469287) < 1e-9);\n\n assert(fabs(func0(data3, 6) - 4.070217029430577) < 1e-9);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\ncmpl $0x1,-0x2c(%rbp)\njg 1228 \npxor %xmm0,%xmm0\njmpq 12d6 \nmov -0x2c(%rbp),%edx\nmov -0x28(%rbp),%rax\nmov %edx,%esi\nmov %rax,%rdi\ncallq 1189 \nmovq %xmm0,%rax\nmov %rax,-0x8(%rbp)\npxor %xmm0,%xmm0\nmovsd %xmm0,-0x10(%rbp)\nmovl $0x0,-0x14(%rbp)\njmp 12a8 \nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovsd (%rax),%xmm0\nmovapd %xmm0,%xmm1\nsubsd -0x8(%rbp),%xmm1\nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovsd (%rax),%xmm0\nsubsd -0x8(%rbp),%xmm0\nmulsd %xmm1,%xmm0\nmovsd -0x10(%rbp),%xmm1\naddsd %xmm1,%xmm0\nmovsd %xmm0,-0x10(%rbp)\naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 1254 \nmov -0x2c(%rbp),%eax\nsub $0x1,%eax\ncvtsi2sd %eax,%xmm1\nmovsd -0x10(%rbp),%xmm0\ndivsd %xmm1,%xmm0\ncallq 1090 \nmovq %xmm0,%rax\nmov %rax,-0x10(%rbp)\nmovsd -0x10(%rbp),%xmm0\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\ncmp [rbp+var_2C], 1\njg short loc_122C\npxor xmm0, xmm0\njmp locret_12E8\nloc_122C:\nmov edx, [rbp+var_2C]\nmov rax, [rbp+var_28]\nmov esi, edx\nmov rdi, rax\ncall avg_calc\nmovq rax, xmm0\nmov [rbp+var_8], rax\npxor xmm0, xmm0\nmovsd [rbp+var_10], xmm0\nmov [rbp+var_14], 0\njmp short loc_12AC\nloc_1258:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovsd xmm0, qword ptr [rax]\nmovapd xmm1, xmm0\nsubsd xmm1, [rbp+var_8]\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovsd xmm0, qword ptr [rax]\nsubsd xmm0, [rbp+var_8]\nmulsd xmm0, xmm1\nmovsd xmm1, [rbp+var_10]\naddsd xmm0, xmm1\nmovsd [rbp+var_10], xmm0\nadd [rbp+var_14], 1\nloc_12AC:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl short loc_1258\nmov eax, [rbp+var_2C]\nsub eax, 1\npxor xmm1, xmm1\ncvtsi2sd xmm1, eax\nmovsd xmm0, [rbp+var_10]\ndivsd xmm0, xmm1\nmovq rax, xmm0\nmovq xmm0, rax; x\ncall _sqrt\nmovq rax, xmm0\nmov [rbp+var_10], rax\nmovsd xmm0, [rbp+var_10]\nlocret_12E8:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 result; // rax\n int i; // [rsp+1Ch] [rbp-14h]\n double v4; // [rsp+20h] [rbp-10h]\n double v5; // [rsp+28h] [rbp-8h]\n\n if ( a2 > 1 )\n {\n v5 = avg_calc(a1, (unsigned int)a2);\n v4 = 0.0;\n for ( i = 0; i < a2; ++i )\n v4 = (*(double *)(8LL * i + a1) - v5) * (*(double *)(8LL * i + a1) - v5) + v4;\n return sqrt(v4 / (double)(a2 - 1));\n }\n return result;\n}", + "ida_strip_asm": "sub_120A:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\ncmp [rbp+var_2C], 1\njg short loc_122C\npxor xmm0, xmm0\njmp locret_12E8\nloc_122C:\nmov edx, [rbp+var_2C]\nmov rax, [rbp+var_28]\nmov esi, edx\nmov rdi, rax\ncall sub_1189\nmovq rax, xmm0\nmov [rbp+var_8], rax\npxor xmm0, xmm0\nmovsd [rbp+var_10], xmm0\nmov [rbp+var_14], 0\njmp short loc_12AC\nloc_1258:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovsd xmm0, qword ptr [rax]\nmovapd xmm1, xmm0\nsubsd xmm1, [rbp+var_8]\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmovsd xmm0, qword ptr [rax]\nsubsd xmm0, [rbp+var_8]\nmulsd xmm0, xmm1\nmovsd xmm1, [rbp+var_10]\naddsd xmm0, xmm1\nmovsd [rbp+var_10], xmm0\nadd [rbp+var_14], 1\nloc_12AC:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl short loc_1258\nmov eax, [rbp+var_2C]\nsub eax, 1\npxor xmm1, xmm1\ncvtsi2sd xmm1, eax\nmovsd xmm0, [rbp+var_10]\ndivsd xmm0, xmm1\nmovq rax, xmm0\nmovq xmm0, rax; x\ncall _sqrt\nmovq rax, xmm0\nmov [rbp+var_10], rax\nmovsd xmm0, [rbp+var_10]\nlocret_12E8:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_120A(__int64 a1, int a2)\n{\n __int64 result; // rax\n int i; // [rsp+1Ch] [rbp-14h]\n double v4; // [rsp+20h] [rbp-10h]\n double v5; // [rsp+28h] [rbp-8h]\n\n if ( a2 > 1 )\n {\n v5 = sub_1189(a1, (unsigned int)a2);\n v4 = 0.0;\n for ( i = 0; i < a2; ++i )\n v4 = (*(double *)(8LL * i + a1) - v5) * (*(double *)(8LL * i + a1) - v5) + v4;\n return sqrt(v4 / (double)(a2 - 1));\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_120A(long long a1, int a2) {\n long long result;\n int i;\n double v4;\n double v5;\n if (a2 > 1) {\n v5 = sub_1189(a1, (unsigned int)a2);\n v4 = 0.0;\n for (i = 0; i < a2; ++i)\n v4 = (*(double *)(8LL * i + a1) - v5) * (*(double *)(8LL * i + a1) - v5) +\n v4;\n return sqrt(v4 / (double)(a2 - 1));\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long result;\n int i;\n double v4;\n double v5;\n if (a2 > 1) {\n v5 = avg_calc(a1, (unsigned int)a2);\n v4 = 0.0;\n for (i = 0; i < a2; ++i)\n v4 = (*(double *)(8LL * i + a1) - v5) * (*(double *)(8LL * i + a1) - v5) +\n v4;\n return sqrt(v4 / (double)(a2 - 1));\n }\n return result;\n}" + }, + { + "index": 717, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\ndouble avg_calc(double *ls, int len) {\n\n double mean = 0.0;\n\n if (len <= 1) {\n\n return ls[0];\n\n }\n\n for (int i = 0; i < len; i++) {\n\n mean += ls[i];\n\n }\n\n mean /= len;\n\n return mean;\n\n}\n\n\n\n", + "func": "double func0(double *data, int len) {\n if (len <= 1) {\n return 0.0;\n }\n double mean = avg_calc(data, len);\n double sd = 0.0;\n for (int i = 0; i < len; i++) {\n sd += (data[i] - mean) * (data[i] - mean);\n }\n sd = sqrt(sd / (len - 1));\n return sd;\n}", + "test": "int main() {\n\n double data1[] = {4, 2, 5, 8, 6};\n\n double data2[] = {1, 2, 3, 4, 5, 6, 7};\n\n double data3[] = {5, 9, 10, 15, 6, 4};\n\n\n\n assert(fabs(func0(data1, 5) - 2.23606797749979) < 1e-9);\n\n assert(fabs(func0(data2, 7) - 2.160246899469287) < 1e-9);\n\n assert(fabs(func0(data3, 6) - 4.070217029430577) < 1e-9);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x18,%rsp\ncmp $0x1,%esi\njle 1240 \nmov %rdi,%rbp\nmov %esi,%ebx\ncallq 1189 \nmovapd %xmm0,%xmm2\nmov %rbp,%rax\nlea -0x1(%rbx),%edx\nlea 0x8(%rbp,%rdx,8),%rdx\npxor %xmm0,%xmm0\nmovsd (%rax),%xmm1\nsubsd %xmm2,%xmm1\nmulsd %xmm1,%xmm1\naddsd %xmm1,%xmm0\nadd $0x8,%rax\ncmp %rdx,%rax\njne 11ec \nsub $0x1,%ebx\npxor %xmm1,%xmm1\ncvtsi2sd %ebx,%xmm1\ndivsd %xmm1,%xmm0\nmovapd %xmm0,%xmm3\nsqrtsd %xmm3,%xmm3\nmovsd %xmm3,0x8(%rsp)\npxor %xmm1,%xmm1\nucomisd %xmm0,%xmm1\nja 1239 \nmovsd 0x8(%rsp),%xmm0\nadd $0x18,%rsp\npop %rbx\npop %rbp\nretq\ncallq 1090 \njmp 122c \npxor %xmm4,%xmm4\nmovsd %xmm4,0x8(%rsp)\njmp 122c \n", + "ida_asm": "func0:\nendbr64\npxor xmm0, xmm0\ncmp esi, 1\njle short locret_1233\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov ebx, esi\ncall avg_calc\nmovapd xmm2, xmm0\nmov rax, rbp\nmovsxd rdx, ebx\nlea rdx, [rbp+rdx*8+0]\npxor xmm0, xmm0\nloc_11EF:\nmovsd xmm1, qword ptr [rax]\nsubsd xmm1, xmm2\nmulsd xmm1, xmm1\naddsd xmm0, xmm1\nadd rax, 8\ncmp rax, rdx\njnz short loc_11EF\nsub ebx, 1\npxor xmm1, xmm1\ncvtsi2sd xmm1, ebx\ndivsd xmm0, xmm1; x\npxor xmm1, xmm1\nucomisd xmm1, xmm0\nja short loc_122C\nsqrtsd xmm0, xmm0\nloc_1225:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_122C:\ncall _sqrt\njmp short loc_1225\nlocret_1233:\nretn", + "ida_pseudo": "double __fastcall func0(double *a1, int a2)\n{\n double result; // xmm0_8\n double v3; // xmm2_8\n double *v4; // rax\n double v5; // xmm0_8\n double v6; // xmm0_8\n\n result = 0.0;\n if ( a2 > 1 )\n {\n v3 = avg_calc(0.0);\n v4 = a1;\n v5 = 0.0;\n do\n {\n v5 = v5 + (*v4 - v3) * (*v4 - v3);\n ++v4;\n }\n while ( v4 != &a1[a2] );\n v6 = v5 / (double)(a2 - 1);\n if ( v6 < 0.0 )\n return sqrt(v6);\n else\n return sqrt(v6);\n }\n return result;\n}", + "ida_strip_asm": "sub_11BF:\nendbr64\npxor xmm0, xmm0\ncmp esi, 1\njle short locret_1233\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov ebx, esi\ncall sub_1189\nmovapd xmm2, xmm0\nmov rax, rbp\nmovsxd rdx, ebx\nlea rdx, [rbp+rdx*8+0]\npxor xmm0, xmm0\nloc_11EF:\nmovsd xmm1, qword ptr [rax]\nsubsd xmm1, xmm2\nmulsd xmm1, xmm1\naddsd xmm0, xmm1\nadd rax, 8\ncmp rax, rdx\njnz short loc_11EF\nsub ebx, 1\npxor xmm1, xmm1\ncvtsi2sd xmm1, ebx\ndivsd xmm0, xmm1; x\npxor xmm1, xmm1\nucomisd xmm1, xmm0\nja short loc_122C\nsqrtsd xmm0, xmm0\nloc_1225:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_122C:\ncall _sqrt\njmp short loc_1225\nlocret_1233:\nretn", + "ida_strip_pseudo": "double __fastcall sub_11BF(double *a1, int a2)\n{\n double result; // xmm0_8\n double v3; // xmm2_8\n double *v4; // rax\n double v5; // xmm0_8\n double v6; // xmm0_8\n\n result = 0.0;\n if ( a2 > 1 )\n {\n v3 = sub_1189(0.0);\n v4 = a1;\n v5 = 0.0;\n do\n {\n v5 = v5 + (*v4 - v3) * (*v4 - v3);\n ++v4;\n }\n while ( v4 != &a1[a2] );\n v6 = v5 / (double)(a2 - 1);\n if ( v6 < 0.0 )\n return sqrt(v6);\n else\n return sqrt(v6);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_11BF(double *a1, int a2) {\n double result;\n double v3;\n double *v4;\n double v5;\n double v6;\n result = 0.0;\n if (a2 > 1) {\n v3 = sub_1189(0.0);\n v4 = a1;\n v5 = 0.0;\n do {\n v5 = v5 + (*v4 - v3) * (*v4 - v3);\n ++v4;\n } while (v4 != &a1[a2]);\n v6 = v5 / (double)(a2 - 1);\n if (v6 < 0.0)\n return sqrt(v6);\n else\n return sqrt(v6);\n }\n return result;\n}", + "ida_pseudo_norm": "double func0(double *a1, int a2) {\n double result;\n double v3;\n double *v4;\n double v5;\n double v6;\n result = 0.0;\n if (a2 > 1) {\n v3 = avg_calc(0.0);\n v4 = a1;\n v5 = 0.0;\n do {\n v5 = v5 + (*v4 - v3) * (*v4 - v3);\n ++v4;\n } while (v4 != &a1[a2]);\n v6 = v5 / (double)(a2 - 1);\n if (v6 < 0.0)\n return sqrt(v6);\n else\n return sqrt(v6);\n }\n return result;\n}" + }, + { + "index": 717, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\ndouble avg_calc(double *ls, int len) {\n\n double mean = 0.0;\n\n if (len <= 1) {\n\n return ls[0];\n\n }\n\n for (int i = 0; i < len; i++) {\n\n mean += ls[i];\n\n }\n\n mean /= len;\n\n return mean;\n\n}\n\n\n\n", + "func": "double func0(double *data, int len) {\n if (len <= 1) {\n return 0.0;\n }\n double mean = avg_calc(data, len);\n double sd = 0.0;\n for (int i = 0; i < len; i++) {\n sd += (data[i] - mean) * (data[i] - mean);\n }\n sd = sqrt(sd / (len - 1));\n return sd;\n}", + "test": "int main() {\n\n double data1[] = {4, 2, 5, 8, 6};\n\n double data2[] = {1, 2, 3, 4, 5, 6, 7};\n\n double data3[] = {5, 9, 10, 15, 6, 4};\n\n\n\n assert(fabs(func0(data1, 5) - 2.23606797749979) < 1e-9);\n\n assert(fabs(func0(data2, 7) - 2.160246899469287) < 1e-9);\n\n assert(fabs(func0(data3, 6) - 4.070217029430577) < 1e-9);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%esi\njle 1450 \nlea -0x1(%rsi),%eax\npxor %xmm3,%xmm3\nmov %rax,%rcx\nlea 0x8(%rdi,%rax,8),%rdx\nmovapd %xmm3,%xmm0\nmov %rdi,%rax\naddsd (%rax),%xmm0\nadd $0x8,%rax\ncmp %rax,%rdx\njne 13f0 \npxor %xmm1,%xmm1\nmovapd %xmm3,%xmm2\ncvtsi2sd %esi,%xmm1\ndivsd %xmm1,%xmm0\nnopl (%rax)\nmovsd (%rdi),%xmm1\nadd $0x8,%rdi\nsubsd %xmm0,%xmm1\nmulsd %xmm1,%xmm1\naddsd %xmm1,%xmm2\ncmp %rdi,%rdx\njne 1410 \npxor %xmm0,%xmm0\ncvtsi2sd %ecx,%xmm0\ndivsd %xmm0,%xmm2\nucomisd %xmm2,%xmm3\nmovapd %xmm2,%xmm1\nsqrtsd %xmm1,%xmm1\nja 1459 \nmovapd %xmm1,%xmm0\nretq\nnopl 0x0(%rax,%rax,1)\npxor %xmm1,%xmm1\nmovapd %xmm1,%xmm0\nretq\nsub $0x18,%rsp\nmovapd %xmm2,%xmm0\nmovsd %xmm1,0x8(%rsp)\ncallq 1090 \nmovsd 0x8(%rsp),%xmm1\nadd $0x18,%rsp\nmovapd %xmm1,%xmm0\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ncmp esi, 1\njle loc_1438\nmovsxd rcx, esi\nmov rax, rdi\npxor xmm0, xmm0\nlea rdx, [rdi+rcx*8]\nand ecx, 1\njz short loc_13D0\nlea rax, [rdi+8]\naddsd xmm0, qword ptr [rdi]\ncmp rdx, rax\njz short loc_13E2\nnop dword ptr [rax]\nloc_13D0:\naddsd xmm0, qword ptr [rax]\nadd rax, 10h\naddsd xmm0, qword ptr [rax-8]\ncmp rdx, rax\njnz short loc_13D0\nloc_13E2:\npxor xmm1, xmm1\npxor xmm2, xmm2\ncvtsi2sd xmm1, esi\ndivsd xmm0, xmm1\nnop word ptr [rax+rax+00h]\nloc_13F8:\nmovsd xmm1, qword ptr [rdi]\nadd rdi, 8\nsubsd xmm1, xmm0\nmulsd xmm1, xmm1\naddsd xmm2, xmm1\ncmp rdx, rdi\njnz short loc_13F8\nsub esi, 1\npxor xmm0, xmm0\ncvtsi2sd xmm0, esi\ndivsd xmm2, xmm0\npxor xmm0, xmm0\nucomisd xmm0, xmm2\nja short loc_143D\nsqrtsd xmm2, xmm2\nmovapd xmm0, xmm2\nretn\nloc_1438:\npxor xmm0, xmm0\nretn\nloc_143D:\nmovapd xmm0, xmm2; x\njmp _sqrt", + "ida_pseudo": "double __fastcall func0(double *a1, int a2)\n{\n double *v2; // rax\n double v3; // xmm0_8\n double *v4; // rdx\n double v5; // xmm0_8\n double v6; // xmm2_8\n double v7; // xmm0_8\n double v8; // xmm1_8\n double v9; // xmm2_8\n\n if ( a2 <= 1 )\n return 0.0;\n v2 = a1;\n v3 = 0.0;\n v4 = &a1[a2];\n if ( (a2 & 1) == 0 || (v2 = a1 + 1, v3 = *a1 + 0.0, v4 != a1 + 1) )\n {\n do\n {\n v5 = v3 + *v2;\n v2 += 2;\n v3 = v5 + *(v2 - 1);\n }\n while ( v4 != v2 );\n }\n v6 = 0.0;\n v7 = v3 / (double)a2;\n do\n {\n v8 = *a1++;\n v6 = v6 + (v8 - v7) * (v8 - v7);\n }\n while ( v4 != a1 );\n v9 = v6 / (double)(a2 - 1);\n if ( v9 < 0.0 )\n return sqrt(v9);\n else\n return sqrt(v9);\n}", + "ida_strip_asm": "sub_13A0:\nendbr64\ncmp esi, 1\njle loc_1438\nmovsxd rcx, esi\nmov rax, rdi\npxor xmm0, xmm0\nlea rdx, [rdi+rcx*8]\nand ecx, 1\njz short loc_13D0\nlea rax, [rdi+8]\naddsd xmm0, qword ptr [rdi]\ncmp rdx, rax\njz short loc_13E2\nnop dword ptr [rax]\nloc_13D0:\naddsd xmm0, qword ptr [rax]\nadd rax, 10h\naddsd xmm0, qword ptr [rax-8]\ncmp rdx, rax\njnz short loc_13D0\nloc_13E2:\npxor xmm1, xmm1\npxor xmm2, xmm2\ncvtsi2sd xmm1, esi\ndivsd xmm0, xmm1\nnop word ptr [rax+rax+00h]\nloc_13F8:\nmovsd xmm1, qword ptr [rdi]\nadd rdi, 8\nsubsd xmm1, xmm0\nmulsd xmm1, xmm1\naddsd xmm2, xmm1\ncmp rdx, rdi\njnz short loc_13F8\nsub esi, 1\npxor xmm0, xmm0\ncvtsi2sd xmm0, esi\ndivsd xmm2, xmm0\npxor xmm0, xmm0\nucomisd xmm0, xmm2\nja short loc_143D\nsqrtsd xmm2, xmm2\nmovapd xmm0, xmm2\nretn\nloc_1438:\npxor xmm0, xmm0\nretn\nloc_143D:\nmovapd xmm0, xmm2; x\njmp _sqrt", + "ida_strip_pseudo": "double __fastcall sub_13A0(double *a1, int a2)\n{\n double *v2; // rax\n double v3; // xmm0_8\n double *v4; // rdx\n double v5; // xmm0_8\n double v6; // xmm2_8\n double v7; // xmm0_8\n double v8; // xmm1_8\n double v9; // xmm2_8\n\n if ( a2 <= 1 )\n return 0.0;\n v2 = a1;\n v3 = 0.0;\n v4 = &a1[a2];\n if ( (a2 & 1) == 0 || (v2 = a1 + 1, v3 = *a1 + 0.0, v4 != a1 + 1) )\n {\n do\n {\n v5 = v3 + *v2;\n v2 += 2;\n v3 = v5 + *(v2 - 1);\n }\n while ( v4 != v2 );\n }\n v6 = 0.0;\n v7 = v3 / (double)a2;\n do\n {\n v8 = *a1++;\n v6 = v6 + (v8 - v7) * (v8 - v7);\n }\n while ( v4 != a1 );\n v9 = v6 / (double)(a2 - 1);\n if ( v9 < 0.0 )\n return sqrt(v9);\n else\n return sqrt(v9);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_13A0(double *a1, int a2) {\n double *v2;\n double v3;\n double *v4;\n double v5;\n double v6;\n double v7;\n double v8;\n double v9;\n if (a2 <= 1) return 0.0;\n v2 = a1;\n v3 = 0.0;\n v4 = &a1[a2];\n if ((a2 & 1) == 0 || (v2 = a1 + 1, v3 = *a1 + 0.0, v4 != a1 + 1)) {\n do {\n v5 = v3 + *v2;\n v2 += 2;\n v3 = v5 + *(v2 - 1);\n } while (v4 != v2);\n }\n v6 = 0.0;\n v7 = v3 / (double)a2;\n do {\n v8 = *a1++;\n v6 = v6 + (v8 - v7) * (v8 - v7);\n } while (v4 != a1);\n v9 = v6 / (double)(a2 - 1);\n if (v9 < 0.0)\n return sqrt(v9);\n else\n return sqrt(v9);\n}", + "ida_pseudo_norm": "double func0(double *a1, int a2) {\n double *v2;\n double v3;\n double *v4;\n double v5;\n double v6;\n double v7;\n double v8;\n double v9;\n if (a2 <= 1) return 0.0;\n v2 = a1;\n v3 = 0.0;\n v4 = &a1[a2];\n if ((a2 & 1) == 0 || (v2 = a1 + 1, v3 = *a1 + 0.0, v4 != a1 + 1)) {\n do {\n v5 = v3 + *v2;\n v2 += 2;\n v3 = v5 + *(v2 - 1);\n } while (v4 != v2);\n }\n v6 = 0.0;\n v7 = v3 / (double)a2;\n do {\n v8 = *a1++;\n v6 = v6 + (v8 - v7) * (v8 - v7);\n } while (v4 != a1);\n v9 = v6 / (double)(a2 - 1);\n if (v9 < 0.0)\n return sqrt(v9);\n else\n return sqrt(v9);\n}" + }, + { + "index": 717, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\ndouble avg_calc(double *ls, int len) {\n\n double mean = 0.0;\n\n if (len <= 1) {\n\n return ls[0];\n\n }\n\n for (int i = 0; i < len; i++) {\n\n mean += ls[i];\n\n }\n\n mean /= len;\n\n return mean;\n\n}\n\n\n\n", + "func": "double func0(double *data, int len) {\n if (len <= 1) {\n return 0.0;\n }\n double mean = avg_calc(data, len);\n double sd = 0.0;\n for (int i = 0; i < len; i++) {\n sd += (data[i] - mean) * (data[i] - mean);\n }\n sd = sqrt(sd / (len - 1));\n return sd;\n}", + "test": "int main() {\n\n double data1[] = {4, 2, 5, 8, 6};\n\n double data2[] = {1, 2, 3, 4, 5, 6, 7};\n\n double data3[] = {5, 9, 10, 15, 6, 4};\n\n\n\n assert(fabs(func0(data1, 5) - 2.23606797749979) < 1e-9);\n\n assert(fabs(func0(data2, 7) - 2.160246899469287) < 1e-9);\n\n assert(fabs(func0(data3, 6) - 4.070217029430577) < 1e-9);\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%esi\njle 1490 \nmov %esi,%edx\npxor %xmm4,%xmm4\nmov %rdi,%rax\nshr %edx\nmovapd %xmm4,%xmm0\nshl $0x4,%rdx\nadd %rdi,%rdx\nnopl 0x0(%rax,%rax,1)\nmovsd (%rax),%xmm1\nadd $0x10,%rax\naddsd %xmm1,%xmm0\nmovsd -0x8(%rax),%xmm1\naddsd %xmm1,%xmm0\ncmp %rax,%rdx\njne 13c8 \nmov %esi,%eax\nand $0xfffffffe,%eax\ntest $0x1,%sil\nje 13f2 \naddsd (%rdi,%rax,8),%xmm0\npxor %xmm1,%xmm1\nmovapd %xmm0,%xmm2\nmov %esi,%edx\nmov %rdi,%rax\ncvtsi2sd %esi,%xmm1\nshr %edx\nmovapd %xmm4,%xmm0\nshl $0x4,%rdx\nadd %rdi,%rdx\ndivsd %xmm1,%xmm2\nmovapd %xmm2,%xmm5\nunpcklpd %xmm5,%xmm5\nnopl 0x0(%rax)\nmovupd (%rax),%xmm1\nadd $0x10,%rax\nsubpd %xmm5,%xmm1\nmulpd %xmm1,%xmm1\nmovapd %xmm1,%xmm3\nunpckhpd %xmm1,%xmm1\naddsd %xmm0,%xmm3\nmovapd %xmm1,%xmm0\naddsd %xmm3,%xmm0\ncmp %rax,%rdx\njne 1420 \nmov %esi,%eax\nand $0xfffffffe,%eax\ntest $0x1,%sil\nje 1469 \nmovsd (%rdi,%rax,8),%xmm3\nsubsd %xmm2,%xmm3\nmovapd %xmm3,%xmm2\nmulsd %xmm3,%xmm2\naddsd %xmm2,%xmm0\nsub $0x1,%esi\npxor %xmm1,%xmm1\ncvtsi2sd %esi,%xmm1\ndivsd %xmm1,%xmm0\nucomisd %xmm0,%xmm4\nmovapd %xmm0,%xmm1\nsqrtsd %xmm1,%xmm1\nja 1499 \nmovapd %xmm1,%xmm0\nretq\nnopl 0x0(%rax,%rax,1)\npxor %xmm1,%xmm1\nmovapd %xmm1,%xmm0\nretq\nsub $0x18,%rsp\nmovsd %xmm1,0x8(%rsp)\ncallq 1090 \nmovsd 0x8(%rsp),%xmm1\nadd $0x18,%rsp\nmovapd %xmm1,%xmm0\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ncmp esi, 1\njle loc_1468\nmov ecx, esi\nmov rdx, rdi\npxor xmm0, xmm0\nmov rax, rdi\nshr ecx, 1\nshl rcx, 4\nadd rcx, rdi\nnop word ptr [rax+rax+00h]\nloc_13C8:\naddsd xmm0, qword ptr [rax]\nadd rax, 10h\naddsd xmm0, qword ptr [rax-8]\ncmp rcx, rax\njnz short loc_13C8\nmov eax, esi\nand eax, 0FFFFFFFEh\ntest sil, 1\njz short loc_13EE\nmov r8d, eax\naddsd xmm0, qword ptr [rdi+r8*8]\nloc_13EE:\npxor xmm1, xmm1\nmovapd xmm2, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm1, esi\ndivsd xmm2, xmm1\nmovapd xmm4, xmm2\nunpcklpd xmm4, xmm4\nnop word ptr [rax+rax+00h]\nloc_1410:\nmovupd xmm1, xmmword ptr [rdx]\nadd rdx, 10h\nsubpd xmm1, xmm4\nmulpd xmm1, xmm1\naddsd xmm0, xmm1\nunpckhpd xmm1, xmm1\naddsd xmm0, xmm1\ncmp rcx, rdx\njnz short loc_1410\ncmp esi, eax\njz short loc_1446\nmovsd xmm1, qword ptr [rdi+rax*8]\nsubsd xmm1, xmm2\nmulsd xmm1, xmm1\naddsd xmm0, xmm1\nloc_1446:\nsub esi, 1\npxor xmm1, xmm1\ncvtsi2sd xmm1, esi\ndivsd xmm0, xmm1; x\npxor xmm1, xmm1\nucomisd xmm1, xmm0\nja short loc_146D\nsqrtsd xmm0, xmm0\nretn\nloc_1468:\npxor xmm0, xmm0\nretn\nloc_146D:\njmp _sqrt", + "ida_pseudo": "double __fastcall func0(__m128d *a1, int a2)\n{\n __m128d *v2; // rdx\n __m128d v3; // xmm0\n double *v4; // rax\n double *m128d_f64; // rcx\n double v6; // xmm0_8\n __int64 v7; // rax\n double v8; // xmm0_8\n __m128d v9; // xmm2\n __m128d v10; // xmm4\n __m128d v11; // xmm1\n __m128d v12; // xmm1\n __m128d v13; // xmm1\n double v14; // xmm0_8\n\n if ( a2 <= 1 )\n return 0.0;\n v2 = a1;\n v3 = 0LL;\n v4 = (double *)a1;\n m128d_f64 = a1[(unsigned int)a2 >> 1].m128d_f64;\n do\n {\n v6 = v3.m128d_f64[0] + *v4;\n v4 += 2;\n v3.m128d_f64[0] = v6 + *(v4 - 1);\n }\n while ( m128d_f64 != v4 );\n v7 = a2 & 0xFFFFFFFE;\n if ( (a2 & 1) != 0 )\n v3.m128d_f64[0] = v3.m128d_f64[0] + a1->m128d_f64[(unsigned int)v7];\n v9 = v3;\n v8 = 0.0;\n v9.m128d_f64[0] = v9.m128d_f64[0] / (double)a2;\n v10 = _mm_unpacklo_pd(v9, v9);\n do\n {\n v11 = *v2++;\n v12 = _mm_sub_pd(v11, v10);\n v13 = _mm_mul_pd(v12, v12);\n v8 = v8 + v13.m128d_f64[0] + _mm_unpackhi_pd(v13, v13).m128d_f64[0];\n }\n while ( m128d_f64 != (double *)v2 );\n if ( a2 != (_DWORD)v7 )\n v8 = v8 + (a1->m128d_f64[v7] - v9.m128d_f64[0]) * (a1->m128d_f64[v7] - v9.m128d_f64[0]);\n v14 = v8 / (double)(a2 - 1);\n if ( v14 < 0.0 )\n return sqrt(v14);\n else\n return sqrt(v14);\n}", + "ida_strip_asm": "sub_13A0:\nendbr64\ncmp esi, 1\njle loc_1468\nmov ecx, esi\nmov rdx, rdi\npxor xmm0, xmm0\nmov rax, rdi\nshr ecx, 1\nshl rcx, 4\nadd rcx, rdi\nnop word ptr [rax+rax+00h]\nloc_13C8:\naddsd xmm0, qword ptr [rax]\nadd rax, 10h\naddsd xmm0, qword ptr [rax-8]\ncmp rcx, rax\njnz short loc_13C8\nmov eax, esi\nand eax, 0FFFFFFFEh\ntest sil, 1\njz short loc_13EE\nmov r8d, eax\naddsd xmm0, qword ptr [rdi+r8*8]\nloc_13EE:\npxor xmm1, xmm1\nmovapd xmm2, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm1, esi\ndivsd xmm2, xmm1\nmovapd xmm4, xmm2\nunpcklpd xmm4, xmm4\nnop word ptr [rax+rax+00h]\nloc_1410:\nmovupd xmm1, xmmword ptr [rdx]\nadd rdx, 10h\nsubpd xmm1, xmm4\nmulpd xmm1, xmm1\naddsd xmm0, xmm1\nunpckhpd xmm1, xmm1\naddsd xmm0, xmm1\ncmp rcx, rdx\njnz short loc_1410\ncmp esi, eax\njz short loc_1446\nmovsd xmm1, qword ptr [rdi+rax*8]\nsubsd xmm1, xmm2\nmulsd xmm1, xmm1\naddsd xmm0, xmm1\nloc_1446:\nsub esi, 1\npxor xmm1, xmm1\ncvtsi2sd xmm1, esi\ndivsd xmm0, xmm1; x\npxor xmm1, xmm1\nucomisd xmm1, xmm0\nja short loc_146D\nsqrtsd xmm0, xmm0\nretn\nloc_1468:\npxor xmm0, xmm0\nretn\nloc_146D:\njmp _sqrt", + "ida_strip_pseudo": "double __fastcall sub_13A0(__m128d *a1, int a2)\n{\n __m128d *v2; // rdx\n __m128d v3; // xmm0\n double *v4; // rax\n double *m128d_f64; // rcx\n double v6; // xmm0_8\n __int64 v7; // rax\n double v8; // xmm0_8\n __m128d v9; // xmm2\n __m128d v10; // xmm4\n __m128d v11; // xmm1\n __m128d v12; // xmm1\n __m128d v13; // xmm1\n double v14; // xmm0_8\n\n if ( a2 <= 1 )\n return 0.0;\n v2 = a1;\n v3 = 0LL;\n v4 = (double *)a1;\n m128d_f64 = a1[(unsigned int)a2 >> 1].m128d_f64;\n do\n {\n v6 = v3.m128d_f64[0] + *v4;\n v4 += 2;\n v3.m128d_f64[0] = v6 + *(v4 - 1);\n }\n while ( m128d_f64 != v4 );\n v7 = a2 & 0xFFFFFFFE;\n if ( (a2 & 1) != 0 )\n v3.m128d_f64[0] = v3.m128d_f64[0] + a1->m128d_f64[(unsigned int)v7];\n v9 = v3;\n v8 = 0.0;\n v9.m128d_f64[0] = v9.m128d_f64[0] / (double)a2;\n v10 = _mm_unpacklo_pd(v9, v9);\n do\n {\n v11 = *v2++;\n v12 = _mm_sub_pd(v11, v10);\n v13 = _mm_mul_pd(v12, v12);\n v8 = v8 + v13.m128d_f64[0] + _mm_unpackhi_pd(v13, v13).m128d_f64[0];\n }\n while ( m128d_f64 != (double *)v2 );\n if ( a2 != (_DWORD)v7 )\n v8 = v8 + (a1->m128d_f64[v7] - v9.m128d_f64[0]) * (a1->m128d_f64[v7] - v9.m128d_f64[0]);\n v14 = v8 / (double)(a2 - 1);\n if ( v14 < 0.0 )\n return sqrt(v14);\n else\n return sqrt(v14);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_13A0(__m128d *a1, int a2) {\n __m128d *v2;\n __m128d v3;\n double *v4;\n double *m128d_f64;\n double v6;\n long long v7;\n double v8;\n __m128d v9;\n __m128d v10;\n __m128d v11;\n __m128d v12;\n __m128d v13;\n double v14;\n if (a2 <= 1) return 0.0;\n v2 = a1;\n v3 = 0LL;\n v4 = (double *)a1;\n m128d_f64 = a1[(unsigned int)a2 >> 1].m128d_f64;\n do {\n v6 = v3.m128d_f64[0] + *v4;\n v4 += 2;\n v3.m128d_f64[0] = v6 + *(v4 - 1);\n } while (m128d_f64 != v4);\n v7 = a2 & 4294967294;\n if ((a2 & 1) != 0)\n v3.m128d_f64[0] = v3.m128d_f64[0] + a1->m128d_f64[(unsigned int)v7];\n v9 = v3;\n v8 = 0.0;\n v9.m128d_f64[0] = v9.m128d_f64[0] / (double)a2;\n v10 = _mm_unpacklo_pd(v9, v9);\n do {\n v11 = *v2++;\n v12 = _mm_sub_pd(v11, v10);\n v13 = _mm_mul_pd(v12, v12);\n v8 = v8 + v13.m128d_f64[0] + _mm_unpackhi_pd(v13, v13).m128d_f64[0];\n } while (m128d_f64 != (double *)v2);\n if (a2 != (uint32_t)v7)\n v8 = v8 + (a1->m128d_f64[v7] - v9.m128d_f64[0]) *\n (a1->m128d_f64[v7] - v9.m128d_f64[0]);\n v14 = v8 / (double)(a2 - 1);\n if (v14 < 0.0)\n return sqrt(v14);\n else\n return sqrt(v14);\n}", + "ida_pseudo_norm": "double func0(__m128d *a1, int a2) {\n __m128d *v2;\n __m128d v3;\n double *v4;\n double *m128d_f64;\n double v6;\n long long v7;\n double v8;\n __m128d v9;\n __m128d v10;\n __m128d v11;\n __m128d v12;\n __m128d v13;\n double v14;\n if (a2 <= 1) return 0.0;\n v2 = a1;\n v3 = 0LL;\n v4 = (double *)a1;\n m128d_f64 = a1[(unsigned int)a2 >> 1].m128d_f64;\n do {\n v6 = v3.m128d_f64[0] + *v4;\n v4 += 2;\n v3.m128d_f64[0] = v6 + *(v4 - 1);\n } while (m128d_f64 != v4);\n v7 = a2 & 4294967294;\n if ((a2 & 1) != 0)\n v3.m128d_f64[0] = v3.m128d_f64[0] + a1->m128d_f64[(unsigned int)v7];\n v9 = v3;\n v8 = 0.0;\n v9.m128d_f64[0] = v9.m128d_f64[0] / (double)a2;\n v10 = _mm_unpacklo_pd(v9, v9);\n do {\n v11 = *v2++;\n v12 = _mm_sub_pd(v11, v10);\n v13 = _mm_mul_pd(v12, v12);\n v8 = v8 + v13.m128d_f64[0] + _mm_unpackhi_pd(v13, v13).m128d_f64[0];\n } while (m128d_f64 != (double *)v2);\n if (a2 != (uint32_t)v7)\n v8 = v8 + (a1->m128d_f64[v7] - v9.m128d_f64[0]) *\n (a1->m128d_f64[v7] - v9.m128d_f64[0]);\n v14 = v8 / (double)(a2 - 1);\n if (v14 < 0.0)\n return sqrt(v14);\n else\n return sqrt(v14);\n}" + }, + { + "index": 718, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int* list1, int length, int* result_size) {\n *result_size = (length + 1) / 2;\n int* result = (int*)malloc(*result_size * sizeof(int));\n int j = 0;\n for (int i = 0; i < length; i += 2) {\n result[j++] = list1[i];\n }\n return result;\n}", + "test": "int main() {\n\n int list1[] = {2, 0, 3, 4, 0, 2, 8, 3, 4, 2};\n\n int list1_size = 10;\n\n int* result1;\n\n int result1_size;\n\n \n\n result1 = func0(list1, list1_size, &result1_size);\n\n int expected_result1[] = {2, 3, 0, 8, 4};\n\n \n\n assert(result1_size == 5);\n\n for (int i = 0; i < result1_size; i++) {\n\n assert(result1[i] == expected_result1[i]);\n\n }\n\n \n\n int list2[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n int list2_size = 10;\n\n int* result2;\n\n int result2_size;\n\n \n\n result2 = func0(list2, list2_size, &result2_size);\n\n int expected_result2[] = {1, 3, 5, 7, 9};\n\n \n\n assert(result2_size == 5);\n\n for (int i = 0; i < result2_size; i++) {\n\n assert(result2[i] == expected_result2[i]);\n\n }\n\n\n\n free(result1); // free allocated memory\n\n free(result2);\n\n \n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmov -0x1c(%rbp),%eax\nadd $0x1,%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nmov %eax,%edx\nmov -0x28(%rbp),%rax\nmov %edx,(%rax)\nmov -0x28(%rbp),%rax\nmov (%rax),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 1236 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x10(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x10(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\naddl $0x2,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11ff \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov eax, [rbp+var_1C]\nadd eax, 1\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov edx, eax\nmov rax, [rbp+var_28]\nmov [rax], edx\nmov rax, [rbp+var_28]\nmov eax, [rax]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp short loc_1236\nloc_11FF:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nadd [rbp+var_C], 2\nloc_1236:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_11FF\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, int *a3)\n{\n int v3; // eax\n int v5; // [rsp+20h] [rbp-10h]\n int i; // [rsp+24h] [rbp-Ch]\n _DWORD *v7; // [rsp+28h] [rbp-8h]\n\n *a3 = (a2 + 1) / 2;\n v7 = malloc(4LL * *a3);\n v5 = 0;\n for ( i = 0; i < a2; i += 2 )\n {\n v3 = v5++;\n v7[v3] = *(_DWORD *)(4LL * i + a1);\n }\n return v7;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov eax, [rbp+var_1C]\nadd eax, 1\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov edx, eax\nmov rax, [rbp+var_28]\nmov [rax], edx\nmov rax, [rbp+var_28]\nmov eax, [rax]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp short loc_1236\nloc_11FF:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nadd [rbp+var_C], 2\nloc_1236:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_11FF\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(__int64 a1, int a2, int *a3)\n{\n int v3; // eax\n int v5; // [rsp+20h] [rbp-10h]\n int i; // [rsp+24h] [rbp-Ch]\n _DWORD *v7; // [rsp+28h] [rbp-8h]\n\n *a3 = (a2 + 1) / 2;\n v7 = malloc(4LL * *a3);\n v5 = 0;\n for ( i = 0; i < a2; i += 2 )\n {\n v3 = v5++;\n v7[v3] = *(_DWORD *)(4LL * i + a1);\n }\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(long long a1, int a2, int *a3) {\n int v3;\n int v5;\n int i;\n uint32_t *v7;\n *a3 = (a2 + 1) / 2;\n v7 = malloc(4LL * *a3);\n v5 = 0;\n for (i = 0; i < a2; i += 2) {\n v3 = v5++;\n v7[v3] = *(uint32_t *)(4LL * i + a1);\n }\n return v7;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, int *a3) {\n int v3;\n int v5;\n int i;\n uint32_t *v7;\n *a3 = (a2 + 1) / 2;\n v7 = malloc(4LL * *a3);\n v5 = 0;\n for (i = 0; i < a2; i += 2) {\n v3 = v5++;\n v7[v3] = *(uint32_t *)(4LL * i + a1);\n }\n return v7;\n}" + }, + { + "index": 718, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int* list1, int length, int* result_size) {\n *result_size = (length + 1) / 2;\n int* result = (int*)malloc(*result_size * sizeof(int));\n int j = 0;\n for (int i = 0; i < length; i += 2) {\n result[j++] = list1[i];\n }\n return result;\n}", + "test": "int main() {\n\n int list1[] = {2, 0, 3, 4, 0, 2, 8, 3, 4, 2};\n\n int list1_size = 10;\n\n int* result1;\n\n int result1_size;\n\n \n\n result1 = func0(list1, list1_size, &result1_size);\n\n int expected_result1[] = {2, 3, 0, 8, 4};\n\n \n\n assert(result1_size == 5);\n\n for (int i = 0; i < result1_size; i++) {\n\n assert(result1[i] == expected_result1[i]);\n\n }\n\n \n\n int list2[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n int list2_size = 10;\n\n int* result2;\n\n int result2_size;\n\n \n\n result2 = func0(list2, list2_size, &result2_size);\n\n int expected_result2[] = {1, 3, 5, 7, 9};\n\n \n\n assert(result2_size == 5);\n\n for (int i = 0; i < result2_size; i++) {\n\n assert(result2[i] == expected_result2[i]);\n\n }\n\n\n\n free(result1); // free allocated memory\n\n free(result2);\n\n \n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbp\nmov %esi,%ebx\nlea 0x1(%rsi),%eax\nmov %eax,%edi\nshr $0x1f,%edi\nadd %eax,%edi\nsar %edi\nmov %edi,(%rdx)\nmovslq %edi,%rdi\nshl $0x2,%rdi\ncallq 10b0 \ntest %ebx,%ebx\njle 11ea \nmov $0x0,%edx\nmov 0x0(%rbp,%rdx,4),%ecx\nmov %ecx,(%rax,%rdx,2)\nadd $0x2,%rdx\ncmp %edx,%ebx\njg 11db \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov ebx, esi\nlea eax, [rsi+1]\nmov edi, eax\nshr edi, 1Fh\nadd edi, eax\nsar edi, 1\nmov [rdx], edi\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\ntest ebx, ebx\njle short loc_11EA\nmov edx, 0\nloc_11DB:\nmov ecx, [rbp+rdx*4+0]\nmov [rax+rdx*2], ecx\nadd rdx, 2\ncmp ebx, edx\njg short loc_11DB\nloc_11EA:\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2, int *a3)\n{\n int v4; // edi\n char *result; // rax\n __int64 v6; // rdx\n\n v4 = (a2 + 1) / 2;\n *a3 = v4;\n result = (char *)malloc(4LL * v4);\n if ( a2 > 0 )\n {\n v6 = 0LL;\n do\n {\n *(_DWORD *)&result[2 * v6] = *(_DWORD *)(a1 + 4 * v6);\n v6 += 2LL;\n }\n while ( a2 > (int)v6 );\n }\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov ebx, esi\nlea eax, [rsi+1]\nmov edi, eax\nshr edi, 1Fh\nadd edi, eax\nsar edi, 1\nmov [rdx], edi\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\ntest ebx, ebx\njle short loc_11EA\nmov edx, 0\nloc_11DB:\nmov ecx, [rbp+rdx*4+0]\nmov [rax+rdx*2], ecx\nadd rdx, 2\ncmp ebx, edx\njg short loc_11DB\nloc_11EA:\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11A9(__int64 a1, int a2, int *a3)\n{\n int v4; // edi\n char *result; // rax\n __int64 v6; // rdx\n\n v4 = (a2 + 1) / 2;\n *a3 = v4;\n result = (char *)malloc(4LL * v4);\n if ( a2 > 0 )\n {\n v6 = 0LL;\n do\n {\n *(_DWORD *)&result[2 * v6] = *(_DWORD *)(a1 + 4 * v6);\n v6 += 2LL;\n }\n while ( a2 > (int)v6 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11A9(long long a1, int a2, int *a3) {\n int v4;\n char *result;\n long long v6;\n v4 = (a2 + 1) / 2;\n *a3 = v4;\n result = (char *)malloc(4LL * v4);\n if (a2 > 0) {\n v6 = 0LL;\n do {\n *(uint32_t *)&result[2 * v6] = *(uint32_t *)(a1 + 4 * v6);\n v6 += 2LL;\n } while (a2 > (int)v6);\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2, int *a3) {\n int v4;\n char *result;\n long long v6;\n v4 = (a2 + 1) / 2;\n *a3 = v4;\n result = (char *)malloc(4LL * v4);\n if (a2 > 0) {\n v6 = 0LL;\n do {\n *(uint32_t *)&result[2 * v6] = *(uint32_t *)(a1 + 4 * v6);\n v6 += 2LL;\n } while (a2 > (int)v6);\n }\n return result;\n}" + }, + { + "index": 718, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int* list1, int length, int* result_size) {\n *result_size = (length + 1) / 2;\n int* result = (int*)malloc(*result_size * sizeof(int));\n int j = 0;\n for (int i = 0; i < length; i += 2) {\n result[j++] = list1[i];\n }\n return result;\n}", + "test": "int main() {\n\n int list1[] = {2, 0, 3, 4, 0, 2, 8, 3, 4, 2};\n\n int list1_size = 10;\n\n int* result1;\n\n int result1_size;\n\n \n\n result1 = func0(list1, list1_size, &result1_size);\n\n int expected_result1[] = {2, 3, 0, 8, 4};\n\n \n\n assert(result1_size == 5);\n\n for (int i = 0; i < result1_size; i++) {\n\n assert(result1[i] == expected_result1[i]);\n\n }\n\n \n\n int list2[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n int list2_size = 10;\n\n int* result2;\n\n int result2_size;\n\n \n\n result2 = func0(list2, list2_size, &result2_size);\n\n int expected_result2[] = {1, 3, 5, 7, 9};\n\n \n\n assert(result2_size == 5);\n\n for (int i = 0; i < result2_size; i++) {\n\n assert(result2[i] == expected_result2[i]);\n\n }\n\n\n\n free(result1); // free allocated memory\n\n free(result2);\n\n \n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nlea 0x1(%rsi),%eax\npush %rbp\nmov %rdi,%rbp\nmov %eax,%edi\npush %rbx\nmov %esi,%ebx\nshr $0x1f,%edi\nadd %eax,%edi\nsar %edi\nsub $0x8,%rsp\nmov %edi,(%rdx)\nmovslq %edi,%rdi\nshl $0x2,%rdi\ncallq 10b0 \ntest %ebx,%ebx\njle 142f \nxor %edx,%edx\nmov 0x0(%rbp,%rdx,4),%ecx\nmov %ecx,(%rax,%rdx,2)\nadd $0x2,%rdx\ncmp %edx,%ebx\njg 1420 \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nlea eax, [rsi+1]\npush rbp\nmov rbp, rdi\nmov edi, eax\npush rbx\nmov ebx, esi\nshr edi, 1Fh\nadd edi, eax\nsar edi, 1\nsub rsp, 8\nmov [rdx], edi\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\ntest ebx, ebx\njle short loc_13CF\nxor edx, edx\nnop\nloc_13C0:\nmov ecx, [rbp+rdx*4+0]\nmov [rax+rdx*2], ecx\nadd rdx, 2\ncmp ebx, edx\njg short loc_13C0\nloc_13CF:\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2, int *a3)\n{\n int v4; // edi\n char *result; // rax\n __int64 v6; // rdx\n\n v4 = (a2 + 1) / 2;\n *a3 = v4;\n result = (char *)malloc(4LL * v4);\n if ( a2 > 0 )\n {\n v6 = 0LL;\n do\n {\n *(_DWORD *)&result[2 * v6] = *(_DWORD *)(a1 + 4 * v6);\n v6 += 2LL;\n }\n while ( a2 > (int)v6 );\n }\n return result;\n}", + "ida_strip_asm": "sub_1390:\nendbr64\nlea eax, [rsi+1]\npush rbp\nmov rbp, rdi\nmov edi, eax\npush rbx\nmov ebx, esi\nshr edi, 1Fh\nadd edi, eax\nsar edi, 1\nsub rsp, 8\nmov [rdx], edi\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\ntest ebx, ebx\njle short loc_13CF\nxor edx, edx\nnop\nloc_13C0:\nmov ecx, [rbp+rdx*4+0]\nmov [rax+rdx*2], ecx\nadd rdx, 2\ncmp ebx, edx\njg short loc_13C0\nloc_13CF:\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1390(__int64 a1, int a2, int *a3)\n{\n int v4; // edi\n char *result; // rax\n __int64 v6; // rdx\n\n v4 = (a2 + 1) / 2;\n *a3 = v4;\n result = (char *)malloc(4LL * v4);\n if ( a2 > 0 )\n {\n v6 = 0LL;\n do\n {\n *(_DWORD *)&result[2 * v6] = *(_DWORD *)(a1 + 4 * v6);\n v6 += 2LL;\n }\n while ( a2 > (int)v6 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1390(long long a1, int a2, int *a3) {\n int v4;\n char *result;\n long long v6;\n v4 = (a2 + 1) / 2;\n *a3 = v4;\n result = (char *)malloc(4LL * v4);\n if (a2 > 0) {\n v6 = 0LL;\n do {\n *(uint32_t *)&result[2 * v6] = *(uint32_t *)(a1 + 4 * v6);\n v6 += 2LL;\n } while (a2 > (int)v6);\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2, int *a3) {\n int v4;\n char *result;\n long long v6;\n v4 = (a2 + 1) / 2;\n *a3 = v4;\n result = (char *)malloc(4LL * v4);\n if (a2 > 0) {\n v6 = 0LL;\n do {\n *(uint32_t *)&result[2 * v6] = *(uint32_t *)(a1 + 4 * v6);\n v6 += 2LL;\n } while (a2 > (int)v6);\n }\n return result;\n}" + }, + { + "index": 718, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int* list1, int length, int* result_size) {\n *result_size = (length + 1) / 2;\n int* result = (int*)malloc(*result_size * sizeof(int));\n int j = 0;\n for (int i = 0; i < length; i += 2) {\n result[j++] = list1[i];\n }\n return result;\n}", + "test": "int main() {\n\n int list1[] = {2, 0, 3, 4, 0, 2, 8, 3, 4, 2};\n\n int list1_size = 10;\n\n int* result1;\n\n int result1_size;\n\n \n\n result1 = func0(list1, list1_size, &result1_size);\n\n int expected_result1[] = {2, 3, 0, 8, 4};\n\n \n\n assert(result1_size == 5);\n\n for (int i = 0; i < result1_size; i++) {\n\n assert(result1[i] == expected_result1[i]);\n\n }\n\n \n\n int list2[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n int list2_size = 10;\n\n int* result2;\n\n int result2_size;\n\n \n\n result2 = func0(list2, list2_size, &result2_size);\n\n int expected_result2[] = {1, 3, 5, 7, 9};\n\n \n\n assert(result2_size == 5);\n\n for (int i = 0; i < result2_size; i++) {\n\n assert(result2[i] == expected_result2[i]);\n\n }\n\n\n\n free(result1); // free allocated memory\n\n free(result2);\n\n \n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nlea 0x1(%rsi),%eax\npush %rbp\nmov %esi,%ebp\npush %rbx\nmov %rdi,%rbx\nmov %eax,%edi\nshr $0x1f,%edi\nadd %eax,%edi\nsar %edi\nsub $0x8,%rsp\nmov %edi,(%rdx)\nmovslq %edi,%rdi\nshl $0x2,%rdi\ncallq 10b0 \ntest %ebp,%ebp\njle 148d \nlea -0x1(%rbp),%edx\ncmp $0x7,%edx\njbe 1494 \nmov %edx,%esi\nxor %edx,%edx\nshr $0x3,%esi\nmov %esi,%ecx\nshl $0x4,%rcx\nnopw 0x0(%rax,%rax,1)\nmovdqu (%rbx,%rdx,2),%xmm0\nmovdqu 0x10(%rbx,%rdx,2),%xmm1\nshufps $0x88,%xmm1,%xmm0\nmovups %xmm0,(%rax,%rdx,1)\nadd $0x10,%rdx\ncmp %rcx,%rdx\njne 1410 \nlea 0x0(,%rsi,4),%ecx\nlea 0x0(,%rsi,8),%edx\nmovslq %edx,%r8\nmovslq %ecx,%rsi\nlea 0x1(%rcx),%edi\nmov (%rbx,%r8,4),%r8d\nmov %r8d,(%rax,%rsi,4)\nlea 0x2(%rdx),%esi\ncmp %esi,%ebp\njle 148d \nmovslq %esi,%rsi\nmovslq %edi,%rdi\nadd $0x2,%ecx\nmov (%rbx,%rsi,4),%esi\nmov %esi,(%rax,%rdi,4)\nlea 0x4(%rdx),%esi\ncmp %esi,%ebp\njle 148d \nmovslq %esi,%rsi\nmovslq %ecx,%rcx\nadd $0x6,%edx\nmov (%rbx,%rsi,4),%esi\nlea 0x0(,%rcx,4),%rdi\nmov %esi,(%rax,%rcx,4)\ncmp %edx,%ebp\njle 148d \nmovslq %edx,%rdx\nmov (%rbx,%rdx,4),%edx\nmov %edx,0x4(%rax,%rdi,1)\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nxor %edx,%edx\nxor %ecx,%ecx\njmp 143a \nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nlea eax, [rsi+1]\npush rbp\nmov ebp, esi\npush rbx\nmov rbx, rdi\nmov edi, eax\nshr edi, 1Fh\nadd edi, eax\nsar edi, 1\nsub rsp, 8\nmov [rdx], edi\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov rdx, rax\ntest ebp, ebp\njle loc_1425\nlea eax, [rbp-1]\ncmp eax, 7\njbe loc_142F\nshr eax, 3\nmov esi, eax\nxor eax, eax\nmov rcx, rsi\nshl rsi, 4\nxchg ax, ax\nloc_13B0:\nmovdqu xmm0, xmmword ptr [rbx+rax*2]\nmovdqu xmm1, xmmword ptr [rbx+rax*2+10h]\nshufps xmm0, xmm1, 88h\nmovups xmmword ptr [rdx+rax], xmm0\nadd rax, 10h\ncmp rsi, rax\njnz short loc_13B0\nlea esi, ds:0[rcx*4]\nlea eax, ds:0[rcx*8]\nloc_13DA:\nmovsxd r8, eax\nmovsxd rcx, esi\nlea rdi, ds:0[r8*4]\nmov r8d, [rbx+r8*4]\nlea rsi, ds:0[rcx*4]\nmov [rdx+rcx*4], r8d\nlea ecx, [rax+2]\ncmp ebp, ecx\njle short loc_1425\nmov ecx, [rbx+rdi+8]\nmov [rdx+rsi+4], ecx\nlea ecx, [rax+4]\ncmp ebp, ecx\njle short loc_1425\nmov ecx, [rbx+rdi+10h]\nadd eax, 6\nmov [rdx+rsi+8], ecx\ncmp ebp, eax\njle short loc_1425\nmov eax, [rbx+rdi+18h]\nmov [rdx+rsi+0Ch], eax\nloc_1425:\nadd rsp, 8\nmov rax, rdx\npop rbx\npop rbp\nretn\nloc_142F:\nxor eax, eax\nxor esi, esi\njmp short loc_13DA", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2, int *a3)\n{\n int v5; // edi\n char *v6; // rdx\n __int64 v7; // rax\n unsigned int v8; // ecx\n int v9; // esi\n int v10; // eax\n __int64 v11; // rdi\n __int64 v12; // rsi\n\n v5 = (a2 + 1) / 2;\n *a3 = v5;\n v6 = (char *)malloc(4LL * v5);\n if ( a2 > 0 )\n {\n if ( (unsigned int)(a2 - 1) <= 7 )\n {\n v10 = 0;\n v9 = 0;\n }\n else\n {\n v7 = 0LL;\n v8 = (unsigned int)(a2 - 1) >> 3;\n do\n {\n *(__m128 *)&v6[v7] = _mm_shuffle_ps(\n (__m128)_mm_loadu_si128((const __m128i *)(a1 + 2 * v7)),\n (__m128)_mm_loadu_si128((const __m128i *)(a1 + 2 * v7 + 16)),\n 136);\n v7 += 16LL;\n }\n while ( 16LL * ((unsigned int)(a2 - 1) >> 3) != v7 );\n v9 = 4 * v8;\n v10 = 8 * v8;\n }\n v11 = 4LL * v10;\n v12 = 4LL * v9;\n *(_DWORD *)&v6[v12] = *(_DWORD *)(a1 + v11);\n if ( a2 > v10 + 2 )\n {\n *(_DWORD *)&v6[v12 + 4] = *(_DWORD *)(a1 + v11 + 8);\n if ( a2 > v10 + 4 )\n {\n *(_DWORD *)&v6[v12 + 8] = *(_DWORD *)(a1 + v11 + 16);\n if ( a2 > v10 + 6 )\n *(_DWORD *)&v6[v12 + 12] = *(_DWORD *)(a1 + v11 + 24);\n }\n }\n }\n return v6;\n}", + "ida_strip_asm": "sub_1360:\nendbr64\nlea eax, [rsi+1]\npush rbp\nmov ebp, esi\npush rbx\nmov rbx, rdi\nmov edi, eax\nshr edi, 1Fh\nadd edi, eax\nsar edi, 1\nsub rsp, 8\nmov [rdx], edi\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov rdx, rax\ntest ebp, ebp\njle loc_1425\nlea eax, [rbp-1]\ncmp eax, 7\njbe loc_142F\nshr eax, 3\nmov esi, eax\nxor eax, eax\nmov rcx, rsi\nshl rsi, 4\nxchg ax, ax\nloc_13B0:\nmovdqu xmm0, xmmword ptr [rbx+rax*2]\nmovdqu xmm1, xmmword ptr [rbx+rax*2+10h]\nshufps xmm0, xmm1, 88h\nmovups xmmword ptr [rdx+rax], xmm0\nadd rax, 10h\ncmp rsi, rax\njnz short loc_13B0\nlea esi, ds:0[rcx*4]\nlea eax, ds:0[rcx*8]\nloc_13DA:\nmovsxd r8, eax\nmovsxd rcx, esi\nlea rdi, ds:0[r8*4]\nmov r8d, [rbx+r8*4]\nlea rsi, ds:0[rcx*4]\nmov [rdx+rcx*4], r8d\nlea ecx, [rax+2]\ncmp ebp, ecx\njle short loc_1425\nmov ecx, [rbx+rdi+8]\nmov [rdx+rsi+4], ecx\nlea ecx, [rax+4]\ncmp ebp, ecx\njle short loc_1425\nmov ecx, [rbx+rdi+10h]\nadd eax, 6\nmov [rdx+rsi+8], ecx\ncmp ebp, eax\njle short loc_1425\nmov eax, [rbx+rdi+18h]\nmov [rdx+rsi+0Ch], eax\nloc_1425:\nadd rsp, 8\nmov rax, rdx\npop rbx\npop rbp\nretn\nloc_142F:\nxor eax, eax\nxor esi, esi\njmp short loc_13DA", + "ida_strip_pseudo": "char *__fastcall sub_1360(__int64 a1, int a2, int *a3)\n{\n int v5; // edi\n char *v6; // rdx\n __int64 v7; // rax\n unsigned int v8; // ecx\n int v9; // esi\n int v10; // eax\n __int64 v11; // rdi\n __int64 v12; // rsi\n\n v5 = (a2 + 1) / 2;\n *a3 = v5;\n v6 = (char *)malloc(4LL * v5);\n if ( a2 > 0 )\n {\n if ( (unsigned int)(a2 - 1) <= 7 )\n {\n v10 = 0;\n v9 = 0;\n }\n else\n {\n v7 = 0LL;\n v8 = (unsigned int)(a2 - 1) >> 3;\n do\n {\n *(__m128 *)&v6[v7] = _mm_shuffle_ps(\n (__m128)_mm_loadu_si128((const __m128i *)(a1 + 2 * v7)),\n (__m128)_mm_loadu_si128((const __m128i *)(a1 + 2 * v7 + 16)),\n 136);\n v7 += 16LL;\n }\n while ( 16LL * ((unsigned int)(a2 - 1) >> 3) != v7 );\n v9 = 4 * v8;\n v10 = 8 * v8;\n }\n v11 = 4LL * v10;\n v12 = 4LL * v9;\n *(_DWORD *)&v6[v12] = *(_DWORD *)(a1 + v11);\n if ( a2 > v10 + 2 )\n {\n *(_DWORD *)&v6[v12 + 4] = *(_DWORD *)(a1 + v11 + 8);\n if ( a2 > v10 + 4 )\n {\n *(_DWORD *)&v6[v12 + 8] = *(_DWORD *)(a1 + v11 + 16);\n if ( a2 > v10 + 6 )\n *(_DWORD *)&v6[v12 + 12] = *(_DWORD *)(a1 + v11 + 24);\n }\n }\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1360(long long a1, int a2, int *a3) {\n int v5;\n char *v6;\n long long v7;\n unsigned int v8;\n int v9;\n int v10;\n long long v11;\n long long v12;\n v5 = (a2 + 1) / 2;\n *a3 = v5;\n v6 = (char *)malloc(4LL * v5);\n if (a2 > 0) {\n if ((unsigned int)(a2 - 1) <= 7) {\n v10 = 0;\n v9 = 0;\n } else {\n v7 = 0LL;\n v8 = (unsigned int)(a2 - 1) >> 3;\n do {\n *(__m128 *)&v6[v7] = _mm_shuffle_ps(\n (__m128)_mm_loadu_si128((const __m128i *)(a1 + 2 * v7)),\n (__m128)_mm_loadu_si128((const __m128i *)(a1 + 2 * v7 + 16)), 136);\n v7 += 16LL;\n } while (16LL * ((unsigned int)(a2 - 1) >> 3) != v7);\n v9 = 4 * v8;\n v10 = 8 * v8;\n }\n v11 = 4LL * v10;\n v12 = 4LL * v9;\n *(uint32_t *)&v6[v12] = *(uint32_t *)(a1 + v11);\n if (a2 > v10 + 2) {\n *(uint32_t *)&v6[v12 + 4] = *(uint32_t *)(a1 + v11 + 8);\n if (a2 > v10 + 4) {\n *(uint32_t *)&v6[v12 + 8] = *(uint32_t *)(a1 + v11 + 16);\n if (a2 > v10 + 6)\n *(uint32_t *)&v6[v12 + 12] = *(uint32_t *)(a1 + v11 + 24);\n }\n }\n }\n return v6;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2, int *a3) {\n int v5;\n char *v6;\n long long v7;\n unsigned int v8;\n int v9;\n int v10;\n long long v11;\n long long v12;\n v5 = (a2 + 1) / 2;\n *a3 = v5;\n v6 = (char *)malloc(4LL * v5);\n if (a2 > 0) {\n if ((unsigned int)(a2 - 1) <= 7) {\n v10 = 0;\n v9 = 0;\n } else {\n v7 = 0LL;\n v8 = (unsigned int)(a2 - 1) >> 3;\n do {\n *(__m128 *)&v6[v7] = _mm_shuffle_ps(\n (__m128)_mm_loadu_si128((const __m128i *)(a1 + 2 * v7)),\n (__m128)_mm_loadu_si128((const __m128i *)(a1 + 2 * v7 + 16)), 136);\n v7 += 16LL;\n } while (16LL * ((unsigned int)(a2 - 1) >> 3) != v7);\n v9 = 4 * v8;\n v10 = 8 * v8;\n }\n v11 = 4LL * v10;\n v12 = 4LL * v9;\n *(uint32_t *)&v6[v12] = *(uint32_t *)(a1 + v11);\n if (a2 > v10 + 2) {\n *(uint32_t *)&v6[v12 + 4] = *(uint32_t *)(a1 + v11 + 8);\n if (a2 > v10 + 4) {\n *(uint32_t *)&v6[v12 + 8] = *(uint32_t *)(a1 + v11 + 16);\n if (a2 > v10 + 6)\n *(uint32_t *)&v6[v12 + 12] = *(uint32_t *)(a1 + v11 + 24);\n }\n }\n }\n return v6;\n}" + }, + { + "index": 719, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "const char* func0(const char* text) {\n regex_t regex;\n int ret;\n const char* patterns = \"ab*?\";\n ret = regcomp(®ex, patterns, REG_EXTENDED);\n if (ret) {\n return \"Regex compilation failed\";\n }\n ret = regexec(®ex, text, 0, NULL, 0);\n regfree(®ex);\n if (!ret) {\n return \"Found a match!\";\n } else {\n return \"Not matched!\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"ac\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\"dc\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"abba\"), \"Found a match!\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x70,%rsp\nmov %rdi,-0x68(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0xdf9(%rip),%rax\nmov %rax,-0x58(%rbp)\nmov -0x58(%rbp),%rcx\nlea -0x50(%rbp),%rax\nmov $0x1,%edx\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 10d0 \nmov %eax,-0x5c(%rbp)\ncmpl $0x0,-0x5c(%rbp)\nje 123d \nlea 0xdd2(%rip),%rax\njmp 1282 \nmov -0x68(%rbp),%rsi\nlea -0x50(%rbp),%rax\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rax,%rdi\ncallq 10f0 \nmov %eax,-0x5c(%rbp)\nlea -0x50(%rbp),%rax\nmov %rax,%rdi\ncallq 10a0 \ncmpl $0x0,-0x5c(%rbp)\njne 127b \nlea 0xdad(%rip),%rax\njmp 1282 \nlea 0xdb3(%rip),%rax\nmov -0x8(%rbp),%rdx\nxor %fs:0x28,%rdx\nje 1296 \ncallq 10b0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aAb; \"ab*?\"\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+var_5C], eax\ncmp [rbp+var_5C], 0\njz short loc_123D\nlea rax, aRegexCompilati; \"Regex compilation failed\"\njmp short loc_1282\nloc_123D:\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_5C], eax\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\ncmp [rbp+var_5C], 0\njnz short loc_127B\nlea rax, s2; \"Found a match!\"\njmp short loc_1282\nloc_127B:\nlea rax, aNotMatched; \"Not matched!\"\nloc_1282:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1296\ncall ___stack_chk_fail\nlocret_1296:\nleave\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n int v2; // [rsp+14h] [rbp-5Ch]\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n unsigned __int64 v4; // [rsp+68h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"ab*?\", 1) )\n return \"Regex compilation failed\";\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if ( v2 )\n return \"Not matched!\";\n else\n return \"Found a match!\";\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aAb; \"ab*?\"\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+var_5C], eax\ncmp [rbp+var_5C], 0\njz short loc_123D\nlea rax, aRegexCompilati; \"Regex compilation failed\"\njmp short loc_1282\nloc_123D:\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_5C], eax\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\ncmp [rbp+var_5C], 0\njnz short loc_127B\nlea rax, s2; \"Found a match!\"\njmp short loc_1282\nloc_127B:\nlea rax, aNotMatched; \"Not matched!\"\nloc_1282:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1296\ncall ___stack_chk_fail\nlocret_1296:\nleave\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_11E9(const char *a1)\n{\n int v2; // [rsp+14h] [rbp-5Ch]\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n unsigned __int64 v4; // [rsp+68h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"ab*?\", 1) )\n return \"Regex compilation failed\";\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if ( v2 )\n return \"Not matched!\";\n else\n return \"Found a match!\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_11E9(const char *a1) {\n int v2;\n regex_t preg;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n if (regcomp(&preg, \"ab*?\", 1)) return \"Regex compilation failed\";\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if (v2)\n return \"Not matched!\";\n else\n return \"Found a match!\";\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n int v2;\n regex_t preg;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n if (regcomp(&preg, \"ab*?\", 1)) return \"Regex compilation failed\";\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if (v2)\n return \"Not matched!\";\n else\n return \"Found a match!\";\n}" + }, + { + "index": 719, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "const char* func0(const char* text) {\n regex_t regex;\n int ret;\n const char* patterns = \"ab*?\";\n ret = regcomp(®ex, patterns, REG_EXTENDED);\n if (ret) {\n return \"Regex compilation failed\";\n }\n ret = regexec(®ex, text, 0, NULL, 0);\n regfree(®ex);\n if (!ret) {\n return \"Found a match!\";\n } else {\n return \"Not matched!\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"ac\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\"dc\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"abba\"), \"Found a match!\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x58,%rsp\nmov %rdi,%rbx\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nmov $0x1,%edx\nlea 0xe44(%rip),%rsi\ncallq 10c0 \nmov %eax,%edx\nlea 0xe01(%rip),%rax\ntest %edx,%edx\nje 121e \nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 125c \nadd $0x58,%rsp\npop %rbx\npop %rbp\nretq\nmov %rsp,%rbp\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rbx,%rsi\nmov %rbp,%rdi\ncallq 10d0 \nmov %eax,%ebx\nmov %rbp,%rdi\ncallq 1090 \ntest %ebx,%ebx\nlea 0xdce(%rip),%rax\nlea 0xdd6(%rip),%rdx\ncmovne %rdx,%rax\njmp 1207 \ncallq 10a0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+68h+var_20], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"ab*?\"\ncall _regcomp\nmov edx, eax\nlea rax, aRegexCompilati; \"Regex compilation failed\"\ntest edx, edx\njz short loc_123E\nloc_1227:\nmov rdx, [rsp+68h+var_20]\nsub rdx, fs:28h\njnz short loc_127C\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_123E:\nmov rbp, rsp\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov ebx, eax\nmov rdi, rbp; preg\ncall _regfree\ntest ebx, ebx\nlea rax, aNotMatched; \"Not matched!\"\nlea rdx, s2; \"Found a match!\"\ncmovz rax, rdx\njmp short loc_1227\nloc_127C:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // edx\n const char *result; // rax\n int v3; // ebx\n regex_t v4; // [rsp+0h] [rbp-68h] BYREF\n unsigned __int64 v5; // [rsp+48h] [rbp-20h]\n\n v5 = __readfsqword(0x28u);\n v1 = regcomp(&v4, \"ab*?\", 1);\n result = \"Regex compilation failed\";\n if ( !v1 )\n {\n v3 = regexec(&v4, string, 0LL, 0LL, 0);\n regfree(&v4);\n result = \"Not matched!\";\n if ( !v3 )\n return \"Found a match!\";\n }\n return result;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+68h+var_20], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"ab*?\"\ncall _regcomp\nmov edx, eax\nlea rax, aRegexCompilati; \"Regex compilation failed\"\ntest edx, edx\njz short loc_123E\nloc_1227:\nmov rdx, [rsp+68h+var_20]\nsub rdx, fs:28h\njnz short loc_127C\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_123E:\nmov rbp, rsp\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov ebx, eax\nmov rdi, rbp; preg\ncall _regfree\ntest ebx, ebx\nlea rax, aNotMatched; \"Not matched!\"\nlea rdx, s2; \"Found a match!\"\ncmovz rax, rdx\njmp short loc_1227\nloc_127C:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_11E9(char *string)\n{\n int v1; // edx\n const char *result; // rax\n int v3; // ebx\n regex_t v4; // [rsp+0h] [rbp-68h] BYREF\n unsigned __int64 v5; // [rsp+48h] [rbp-20h]\n\n v5 = __readfsqword(0x28u);\n v1 = regcomp(&v4, \"ab*?\", 1);\n result = \"Regex compilation failed\";\n if ( !v1 )\n {\n v3 = regexec(&v4, string, 0LL, 0LL, 0);\n regfree(&v4);\n result = \"Not matched!\";\n if ( !v3 )\n return \"Found a match!\";\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_11E9(char *string) {\n int v1;\n const char *result;\n int v3;\n regex_t v4;\n unsigned long long v5;\n v5 = __readfsqword(40u);\n v1 = regcomp(&v4, \"ab*?\", 1);\n result = \"Regex compilation failed\";\n if (!v1) {\n v3 = regexec(&v4, string, 0LL, 0LL, 0);\n regfree(&v4);\n result = \"Not matched!\";\n if (!v3) return \"Found a match!\";\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n const char *result;\n int v3;\n regex_t v4;\n unsigned long long v5;\n v5 = __readfsqword(40u);\n v1 = regcomp(&v4, \"ab*?\", 1);\n result = \"Regex compilation failed\";\n if (!v1) {\n v3 = regexec(&v4, string, 0LL, 0LL, 0);\n regfree(&v4);\n result = \"Not matched!\";\n if (!v3) return \"Found a match!\";\n }\n return result;\n}" + }, + { + "index": 719, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "const char* func0(const char* text) {\n regex_t regex;\n int ret;\n const char* patterns = \"ab*?\";\n ret = regcomp(®ex, patterns, REG_EXTENDED);\n if (ret) {\n return \"Regex compilation failed\";\n }\n ret = regexec(®ex, text, 0, NULL, 0);\n regfree(®ex);\n if (!ret) {\n return \"Found a match!\";\n } else {\n return \"Not matched!\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"ac\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\"dc\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"abba\"), \"Found a match!\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov $0x1,%edx\nlea 0xd77(%rip),%rsi\npush %rbp\nmov %rdi,%rbp\nsub $0x58,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%r12\nmov %r12,%rdi\ncallq 10c0 \nmov %eax,%r8d\nlea 0xd15(%rip),%rax\ntest %r8d,%r8d\njne 1321 \nxor %edx,%edx\nxor %ecx,%ecx\nmov %rbp,%rsi\nmov %r12,%rdi\ncallq 10d0 \nmov %r12,%rdi\nmov %eax,%ebp\ncallq 1090 \ntest %ebp,%ebp\nlea 0xd07(%rip),%rax\nlea 0xd0f(%rip),%rdx\ncmovne %rdx,%rax\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 1339 \nadd $0x58,%rsp\npop %rbp\npop %r12\nretq\ncallq 10a0 <__stack_chk_fail@plt>\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"ab*?\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nmov edx, eax\nlea rax, aRegexCompilati; \"Regex compilation failed\"\ntest edx, edx\njnz short loc_1331\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, aNotMatched; \"Not matched!\"\nlea rdx, s2; \"Found a match!\"\ncmovz rax, rdx\nloc_1331:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_1348\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1348:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // edx\n const char *result; // rax\n int v3; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n v1 = regcomp(&_0, \"ab*?\", 1);\n result = \"Regex compilation failed\";\n if ( !v1 )\n {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if ( !v3 )\n return \"Found a match!\";\n }\n return result;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"ab*?\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nmov edx, eax\nlea rax, aRegexCompilati; \"Regex compilation failed\"\ntest edx, edx\njnz short loc_1331\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, aNotMatched; \"Not matched!\"\nlea rdx, s2; \"Found a match!\"\ncmovz rax, rdx\nloc_1331:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_1348\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1348:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_12C0(char *string)\n{\n int v1; // edx\n const char *result; // rax\n int v3; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n v1 = regcomp(&_0, \"ab*?\", 1);\n result = \"Regex compilation failed\";\n if ( !v1 )\n {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if ( !v3 )\n return \"Found a match!\";\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_12C0(char *string) {\n int v1;\n const char *result;\n int v3;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n v1 = regcomp(&_0, \"ab*?\", 1);\n result = \"Regex compilation failed\";\n if (!v1) {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if (!v3) return \"Found a match!\";\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n const char *result;\n int v3;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n v1 = regcomp(&_0, \"ab*?\", 1);\n result = \"Regex compilation failed\";\n if (!v1) {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if (!v3) return \"Found a match!\";\n }\n return result;\n}" + }, + { + "index": 719, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "const char* func0(const char* text) {\n regex_t regex;\n int ret;\n const char* patterns = \"ab*?\";\n ret = regcomp(®ex, patterns, REG_EXTENDED);\n if (ret) {\n return \"Regex compilation failed\";\n }\n ret = regexec(®ex, text, 0, NULL, 0);\n regfree(®ex);\n if (!ret) {\n return \"Found a match!\";\n } else {\n return \"Not matched!\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"ac\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\"dc\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"abba\"), \"Found a match!\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov $0x1,%edx\nlea 0xd77(%rip),%rsi\npush %rbp\nmov %rdi,%rbp\nsub $0x58,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%r12\nmov %r12,%rdi\ncallq 10c0 \nmov %eax,%r8d\nlea 0xd15(%rip),%rax\ntest %r8d,%r8d\njne 1321 \nxor %edx,%edx\nxor %ecx,%ecx\nmov %rbp,%rsi\nmov %r12,%rdi\ncallq 10d0 \nmov %r12,%rdi\nmov %eax,%ebp\ncallq 1090 \ntest %ebp,%ebp\nlea 0xd07(%rip),%rax\nlea 0xd0f(%rip),%rdx\ncmovne %rdx,%rax\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 1339 \nadd $0x58,%rsp\npop %rbp\npop %r12\nretq\ncallq 10a0 <__stack_chk_fail@plt>\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"ab*?\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nmov edx, eax\nlea rax, aRegexCompilati; \"Regex compilation failed\"\ntest edx, edx\njnz short loc_1331\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, aNotMatched; \"Not matched!\"\nlea rdx, s2; \"Found a match!\"\ncmovz rax, rdx\nloc_1331:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_1348\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1348:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // edx\n const char *result; // rax\n int v3; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n v1 = regcomp(&_0, \"ab*?\", 1);\n result = \"Regex compilation failed\";\n if ( !v1 )\n {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if ( !v3 )\n return \"Found a match!\";\n }\n return result;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"ab*?\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nmov edx, eax\nlea rax, aRegexCompilati; \"Regex compilation failed\"\ntest edx, edx\njnz short loc_1331\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, aNotMatched; \"Not matched!\"\nlea rdx, s2; \"Found a match!\"\ncmovz rax, rdx\nloc_1331:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_1348\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1348:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_12C0(char *string)\n{\n int v1; // edx\n const char *result; // rax\n int v3; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n v1 = regcomp(&_0, \"ab*?\", 1);\n result = \"Regex compilation failed\";\n if ( !v1 )\n {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if ( !v3 )\n return \"Found a match!\";\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_12C0(char *string) {\n int v1;\n const char *result;\n int v3;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n v1 = regcomp(&_0, \"ab*?\", 1);\n result = \"Regex compilation failed\";\n if (!v1) {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if (!v3) return \"Found a match!\";\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n const char *result;\n int v3;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n v1 = regcomp(&_0, \"ab*?\", 1);\n result = \"Regex compilation failed\";\n if (!v1) {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if (!v3) return \"Found a match!\";\n }\n return result;\n}" + }, + { + "index": 720, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n const char* key;\n\n int value;\n\n} KeyValuePair;\n\n\n\ntypedef struct {\n\n KeyValuePair* pairs;\n\n int size;\n\n} Dictionary;\n\n\n\ntypedef struct {\n\n int* elements;\n\n int size;\n\n Dictionary* dict;\n\n} Tuple;\n\n\n\n", + "func": "Tuple* func0(Tuple* test_tup, Dictionary* test_dict) {\n int new_size = test_tup->size + 1;\n Tuple* new_tuple = malloc(sizeof(Tuple));\n new_tuple->elements = malloc(new_size * sizeof(int));\n for (int i = 0; i < test_tup->size; i++) {\n new_tuple->elements[i] = test_tup->elements[i];\n }\n new_tuple->elements[test_tup->size] = -1;\n new_tuple->size = new_size;\n new_tuple->dict = test_dict;\n return new_tuple;\n}", + "test": "int main() {\n\n int arr1[3] = {4, 5, 6};\n\n KeyValuePair pairs1[3] = {{\"MSAM\", 1}, {\"is\", 2}, {\"best\", 3}};\n\n Dictionary dict1 = {pairs1, 3};\n\n Tuple tup1 = {arr1, 3, NULL};\n\n Tuple* res_tup1 = func0(&tup1, &dict1);\n\n\n\n assert(res_tup1->size == 4);\n\n assert(res_tup1->elements[0] == 4);\n\n assert(res_tup1->elements[1] == 5);\n\n assert(res_tup1->elements[2] == 6);\n\n assert(res_tup1->elements[3] == -1);\n\n assert(res_tup1->dict->size == 3);\n\n\n\n int arr2[3] = {1, 2, 3};\n\n KeyValuePair pairs2[3] = {{\"UTS\", 2}, {\"is\", 3}, {\"Worst\", 4}};\n\n Dictionary dict2 = {pairs2, 3};\n\n Tuple tup2 = {arr2, 3, NULL};\n\n Tuple* res_tup2 = func0(&tup2, &dict2);\n\n\n\n assert(res_tup2->size == 4);\n\n assert(res_tup2->elements[0] == 1);\n\n assert(res_tup2->elements[1] == 2);\n\n assert(res_tup2->elements[2] == 3);\n\n assert(res_tup2->elements[3] == -1);\n\n assert(res_tup2->dict->size == 3);\n\n\n\n int arr3[3] = {8, 9, 10};\n\n KeyValuePair pairs3[3] = {{\"POS\", 3}, {\"is\", 4}, {\"Okay\", 5}};\n\n Dictionary dict3 = {pairs3, 3};\n\n Tuple tup3 = {arr3, 3, NULL};\n\n Tuple* res_tup3 = func0(&tup3, &dict3);\n\n\n\n assert(res_tup3->size == 4);\n\n assert(res_tup3->elements[0] == 8);\n\n assert(res_tup3->elements[1] == 9);\n\n assert(res_tup3->elements[2] == 10);\n\n assert(res_tup3->elements[3] == -1);\n\n assert(res_tup3->dict->size == 3);\n\n\n\n printf(\"All tests passed successfully!\\n\");\n\n\n\n free(res_tup1->elements);\n\n free(res_tup1);\n\n free(res_tup2->elements);\n\n free(res_tup2);\n\n free(res_tup3->elements);\n\n free(res_tup3);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov -0x18(%rbp),%rax\nmov 0x8(%rax),%eax\nadd $0x1,%eax\nmov %eax,-0xc(%rbp)\nmov $0x18,%edi\ncallq 10d0 \nmov %rax,-0x8(%rbp)\nmov -0xc(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,%rdx\nmov -0x8(%rbp),%rax\nmov %rdx,(%rax)\nmovl $0x0,-0x10(%rbp)\njmp 124d \nmov -0x18(%rbp),%rax\nmov (%rax),%rax\nmov -0x10(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x2,%rdx\nlea (%rax,%rdx,1),%rcx\nmov -0x8(%rbp),%rax\nmov (%rax),%rax\nmov -0x10(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x2,%rdx\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x10(%rbp)\nmov -0x18(%rbp),%rax\nmov 0x8(%rax),%eax\ncmp %eax,-0x10(%rbp)\njl 121c \nmov -0x8(%rbp),%rax\nmov (%rax),%rdx\nmov -0x18(%rbp),%rax\nmov 0x8(%rax),%eax\ncltq\nshl $0x2,%rax\nadd %rdx,%rax\nmovl $0xffffffff,(%rax)\nmov -0x8(%rbp),%rax\nmov -0xc(%rbp),%edx\nmov %edx,0x8(%rax)\nmov -0x8(%rbp),%rax\nmov -0x20(%rbp),%rdx\nmov %rdx,0x10(%rax)\nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov rax, [rbp+var_18]\nmov eax, [rax+8]\nadd eax, 1\nmov [rbp+var_C], eax\nmov edi, 18h; size\ncall _malloc\nmov [rbp+var_8], rax\nmov eax, [rbp+var_C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov rdx, rax\nmov rax, [rbp+var_8]\nmov [rax], rdx\nmov [rbp+var_10], 0\njmp short loc_124D\nloc_121C:\nmov rax, [rbp+var_18]\nmov rax, [rax]\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nshl rdx, 2\nlea rcx, [rax+rdx]\nmov rax, [rbp+var_8]\nmov rax, [rax]\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nshl rdx, 2\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nadd [rbp+var_10], 1\nloc_124D:\nmov rax, [rbp+var_18]\nmov eax, [rax+8]\ncmp [rbp+var_10], eax\njl short loc_121C\nmov rax, [rbp+var_8]\nmov rdx, [rax]\nmov rax, [rbp+var_18]\nmov eax, [rax+8]\ncdqe\nshl rax, 2\nadd rax, rdx\nmov dword ptr [rax], 0FFFFFFFFh\nmov rax, [rbp+var_8]\nmov edx, [rbp+var_C]\nmov [rax+8], edx\nmov rax, [rbp+var_8]\nmov rdx, [rbp+var_20]\nmov [rax+10h], rdx\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, __int64 a2)\n{\n int i; // [rsp+10h] [rbp-10h]\n int v4; // [rsp+14h] [rbp-Ch]\n _DWORD *v5; // [rsp+18h] [rbp-8h]\n\n v4 = *(_DWORD *)(a1 + 8) + 1;\n v5 = malloc(0x18uLL);\n *(_QWORD *)v5 = malloc(4LL * v4);\n for ( i = 0; i < *(_DWORD *)(a1 + 8); ++i )\n *(_DWORD *)(*(_QWORD *)v5 + 4LL * i) = *(_DWORD *)(*(_QWORD *)a1 + 4LL * i);\n *(_DWORD *)(*(_QWORD *)v5 + 4LL * *(int *)(a1 + 8)) = -1;\n v5[2] = v4;\n *((_QWORD *)v5 + 2) = a2;\n return v5;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov rax, [rbp+var_18]\nmov eax, [rax+8]\nadd eax, 1\nmov [rbp+var_C], eax\nmov edi, 18h; size\ncall _malloc\nmov [rbp+var_8], rax\nmov eax, [rbp+var_C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov rdx, rax\nmov rax, [rbp+var_8]\nmov [rax], rdx\nmov [rbp+var_10], 0\njmp short loc_124D\nloc_121C:\nmov rax, [rbp+var_18]\nmov rax, [rax]\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nshl rdx, 2\nlea rcx, [rax+rdx]\nmov rax, [rbp+var_8]\nmov rax, [rax]\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nshl rdx, 2\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nadd [rbp+var_10], 1\nloc_124D:\nmov rax, [rbp+var_18]\nmov eax, [rax+8]\ncmp [rbp+var_10], eax\njl short loc_121C\nmov rax, [rbp+var_8]\nmov rdx, [rax]\nmov rax, [rbp+var_18]\nmov eax, [rax+8]\ncdqe\nshl rax, 2\nadd rax, rdx\nmov dword ptr [rax], 0FFFFFFFFh\nmov rax, [rbp+var_8]\nmov edx, [rbp+var_C]\nmov [rax+8], edx\nmov rax, [rbp+var_8]\nmov rdx, [rbp+var_20]\nmov [rax+10h], rdx\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11C9(__int64 a1, __int64 a2)\n{\n int i; // [rsp+10h] [rbp-10h]\n int v4; // [rsp+14h] [rbp-Ch]\n _DWORD *v5; // [rsp+18h] [rbp-8h]\n\n v4 = *(_DWORD *)(a1 + 8) + 1;\n v5 = malloc(0x18uLL);\n *(_QWORD *)v5 = malloc(4LL * v4);\n for ( i = 0; i < *(_DWORD *)(a1 + 8); ++i )\n *(_DWORD *)(*(_QWORD *)v5 + 4LL * i) = *(_DWORD *)(*(_QWORD *)a1 + 4LL * i);\n *(_DWORD *)(*(_QWORD *)v5 + 4LL * *(int *)(a1 + 8)) = -1;\n v5[2] = v4;\n *((_QWORD *)v5 + 2) = a2;\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11C9(long long a1, long long a2) {\n int i;\n int v4;\n uint32_t *v5;\n v4 = *(uint32_t *)(a1 + 8) + 1;\n v5 = malloc(24uLL);\n *(uint64_t *)v5 = malloc(4LL * v4);\n for (i = 0; i < *(uint32_t *)(a1 + 8); ++i)\n *(uint32_t *)(*(uint64_t *)v5 + 4LL * i) =\n *(uint32_t *)(*(uint64_t *)a1 + 4LL * i);\n *(uint32_t *)(*(uint64_t *)v5 + 4LL * *(int *)(a1 + 8)) = -1;\n v5[2] = v4;\n *((uint64_t *)v5 + 2) = a2;\n return v5;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, long long a2) {\n int i;\n int v4;\n uint32_t *v5;\n v4 = *(uint32_t *)(a1 + 8) + 1;\n v5 = malloc(24uLL);\n *(uint64_t *)v5 = malloc(4LL * v4);\n for (i = 0; i < *(uint32_t *)(a1 + 8); ++i)\n *(uint32_t *)(*(uint64_t *)v5 + 4LL * i) =\n *(uint32_t *)(*(uint64_t *)a1 + 4LL * i);\n *(uint32_t *)(*(uint64_t *)v5 + 4LL * *(int *)(a1 + 8)) = -1;\n v5[2] = v4;\n *((uint64_t *)v5 + 2) = a2;\n return v5;\n}" + }, + { + "index": 720, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n const char* key;\n\n int value;\n\n} KeyValuePair;\n\n\n\ntypedef struct {\n\n KeyValuePair* pairs;\n\n int size;\n\n} Dictionary;\n\n\n\ntypedef struct {\n\n int* elements;\n\n int size;\n\n Dictionary* dict;\n\n} Tuple;\n\n\n\n", + "func": "Tuple* func0(Tuple* test_tup, Dictionary* test_dict) {\n int new_size = test_tup->size + 1;\n Tuple* new_tuple = malloc(sizeof(Tuple));\n new_tuple->elements = malloc(new_size * sizeof(int));\n for (int i = 0; i < test_tup->size; i++) {\n new_tuple->elements[i] = test_tup->elements[i];\n }\n new_tuple->elements[test_tup->size] = -1;\n new_tuple->size = new_size;\n new_tuple->dict = test_dict;\n return new_tuple;\n}", + "test": "int main() {\n\n int arr1[3] = {4, 5, 6};\n\n KeyValuePair pairs1[3] = {{\"MSAM\", 1}, {\"is\", 2}, {\"best\", 3}};\n\n Dictionary dict1 = {pairs1, 3};\n\n Tuple tup1 = {arr1, 3, NULL};\n\n Tuple* res_tup1 = func0(&tup1, &dict1);\n\n\n\n assert(res_tup1->size == 4);\n\n assert(res_tup1->elements[0] == 4);\n\n assert(res_tup1->elements[1] == 5);\n\n assert(res_tup1->elements[2] == 6);\n\n assert(res_tup1->elements[3] == -1);\n\n assert(res_tup1->dict->size == 3);\n\n\n\n int arr2[3] = {1, 2, 3};\n\n KeyValuePair pairs2[3] = {{\"UTS\", 2}, {\"is\", 3}, {\"Worst\", 4}};\n\n Dictionary dict2 = {pairs2, 3};\n\n Tuple tup2 = {arr2, 3, NULL};\n\n Tuple* res_tup2 = func0(&tup2, &dict2);\n\n\n\n assert(res_tup2->size == 4);\n\n assert(res_tup2->elements[0] == 1);\n\n assert(res_tup2->elements[1] == 2);\n\n assert(res_tup2->elements[2] == 3);\n\n assert(res_tup2->elements[3] == -1);\n\n assert(res_tup2->dict->size == 3);\n\n\n\n int arr3[3] = {8, 9, 10};\n\n KeyValuePair pairs3[3] = {{\"POS\", 3}, {\"is\", 4}, {\"Okay\", 5}};\n\n Dictionary dict3 = {pairs3, 3};\n\n Tuple tup3 = {arr3, 3, NULL};\n\n Tuple* res_tup3 = func0(&tup3, &dict3);\n\n\n\n assert(res_tup3->size == 4);\n\n assert(res_tup3->elements[0] == 8);\n\n assert(res_tup3->elements[1] == 9);\n\n assert(res_tup3->elements[2] == 10);\n\n assert(res_tup3->elements[3] == -1);\n\n assert(res_tup3->dict->size == 3);\n\n\n\n printf(\"All tests passed successfully!\\n\");\n\n\n\n free(res_tup1->elements);\n\n free(res_tup1);\n\n free(res_tup2->elements);\n\n free(res_tup2);\n\n free(res_tup3->elements);\n\n free(res_tup3);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%r14\nmov %rsi,%r12\nmov 0x8(%rdi),%ebx\nlea 0x1(%rbx),%r13d\nmov $0x18,%edi\ncallq 10d0 \nmov %rax,%rbp\nmovslq %r13d,%rdi\nshl $0x2,%rdi\ncallq 10d0 \nmov %rax,0x0(%rbp)\ntest %ebx,%ebx\njle 1221 \nmov $0x0,%eax\nmov (%r14),%rdx\nmov (%rdx,%rax,4),%ecx\nmov 0x0(%rbp),%rdx\nmov %ecx,(%rdx,%rax,4)\nmov 0x8(%r14),%ebx\nadd $0x1,%rax\ncmp %eax,%ebx\njg 1208 \nmovslq %ebx,%rbx\nmov 0x0(%rbp),%rax\nmovl $0xffffffff,(%rax,%rbx,4)\nmov %r13d,0x8(%rbp)\nmov %r12,0x10(%rbp)\nmov %rbp,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r14, rdi\nmov r12, rsi\nmov ebx, [rdi+8]\nlea r13d, [rbx+1]\nmov edi, 18h; size\ncall _malloc\nmov rbp, rax\nmovsxd rdi, r13d\nshl rdi, 2; size\ncall _malloc\nmov [rbp+0], rax\ntest ebx, ebx\njle short loc_1221\nmov eax, 0\nloc_1208:\nmov rdx, [r14]\nmov ecx, [rdx+rax*4]\nmov rdx, [rbp+0]\nmov [rdx+rax*4], ecx\nmov ebx, [r14+8]\nadd rax, 1\ncmp ebx, eax\njg short loc_1208\nloc_1221:\nmovsxd rbx, ebx\nmov rax, [rbp+0]\nmov dword ptr [rax+rbx*4], 0FFFFFFFFh\nmov [rbp+8], r13d\nmov [rbp+10h], r12\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, __int64 a2)\n{\n int v2; // ebx\n int v3; // r13d\n _DWORD *v4; // rbp\n __int64 v5; // rax\n\n v2 = *(_DWORD *)(a1 + 8);\n v3 = v2 + 1;\n v4 = malloc(0x18uLL);\n *(_QWORD *)v4 = malloc(4LL * (v2 + 1));\n if ( v2 > 0 )\n {\n v5 = 0LL;\n do\n {\n *(_DWORD *)(*(_QWORD *)v4 + 4 * v5) = *(_DWORD *)(*(_QWORD *)a1 + 4 * v5);\n v2 = *(_DWORD *)(a1 + 8);\n ++v5;\n }\n while ( v2 > (int)v5 );\n }\n *(_DWORD *)(*(_QWORD *)v4 + 4LL * v2) = -1;\n v4[2] = v3;\n *((_QWORD *)v4 + 2) = a2;\n return v4;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r14, rdi\nmov r12, rsi\nmov ebx, [rdi+8]\nlea r13d, [rbx+1]\nmov edi, 18h; size\ncall _malloc\nmov rbp, rax\nmovsxd rdi, r13d\nshl rdi, 2; size\ncall _malloc\nmov [rbp+0], rax\ntest ebx, ebx\njle short loc_1221\nmov eax, 0\nloc_1208:\nmov rdx, [r14]\nmov ecx, [rdx+rax*4]\nmov rdx, [rbp+0]\nmov [rdx+rax*4], ecx\nmov ebx, [r14+8]\nadd rax, 1\ncmp ebx, eax\njg short loc_1208\nloc_1221:\nmovsxd rbx, ebx\nmov rax, [rbp+0]\nmov dword ptr [rax+rbx*4], 0FFFFFFFFh\nmov [rbp+8], r13d\nmov [rbp+10h], r12\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11C9(__int64 a1, __int64 a2)\n{\n int v2; // ebx\n int v3; // r13d\n _DWORD *v4; // rbp\n __int64 v5; // rax\n\n v2 = *(_DWORD *)(a1 + 8);\n v3 = v2 + 1;\n v4 = malloc(0x18uLL);\n *(_QWORD *)v4 = malloc(4LL * (v2 + 1));\n if ( v2 > 0 )\n {\n v5 = 0LL;\n do\n {\n *(_DWORD *)(*(_QWORD *)v4 + 4 * v5) = *(_DWORD *)(*(_QWORD *)a1 + 4 * v5);\n v2 = *(_DWORD *)(a1 + 8);\n ++v5;\n }\n while ( v2 > (int)v5 );\n }\n *(_DWORD *)(*(_QWORD *)v4 + 4LL * v2) = -1;\n v4[2] = v3;\n *((_QWORD *)v4 + 2) = a2;\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11C9(long long a1, long long a2) {\n int v2;\n int v3;\n uint32_t *v4;\n long long v5;\n v2 = *(uint32_t *)(a1 + 8);\n v3 = v2 + 1;\n v4 = malloc(24uLL);\n *(uint64_t *)v4 = malloc(4LL * (v2 + 1));\n if (v2 > 0) {\n v5 = 0LL;\n do {\n *(uint32_t *)(*(uint64_t *)v4 + 4 * v5) =\n *(uint32_t *)(*(uint64_t *)a1 + 4 * v5);\n v2 = *(uint32_t *)(a1 + 8);\n ++v5;\n } while (v2 > (int)v5);\n }\n *(uint32_t *)(*(uint64_t *)v4 + 4LL * v2) = -1;\n v4[2] = v3;\n *((uint64_t *)v4 + 2) = a2;\n return v4;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, long long a2) {\n int v2;\n int v3;\n uint32_t *v4;\n long long v5;\n v2 = *(uint32_t *)(a1 + 8);\n v3 = v2 + 1;\n v4 = malloc(24uLL);\n *(uint64_t *)v4 = malloc(4LL * (v2 + 1));\n if (v2 > 0) {\n v5 = 0LL;\n do {\n *(uint32_t *)(*(uint64_t *)v4 + 4 * v5) =\n *(uint32_t *)(*(uint64_t *)a1 + 4 * v5);\n v2 = *(uint32_t *)(a1 + 8);\n ++v5;\n } while (v2 > (int)v5);\n }\n *(uint32_t *)(*(uint64_t *)v4 + 4LL * v2) = -1;\n v4[2] = v3;\n *((uint64_t *)v4 + 2) = a2;\n return v4;\n}" + }, + { + "index": 720, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n const char* key;\n\n int value;\n\n} KeyValuePair;\n\n\n\ntypedef struct {\n\n KeyValuePair* pairs;\n\n int size;\n\n} Dictionary;\n\n\n\ntypedef struct {\n\n int* elements;\n\n int size;\n\n Dictionary* dict;\n\n} Tuple;\n\n\n\n", + "func": "Tuple* func0(Tuple* test_tup, Dictionary* test_dict) {\n int new_size = test_tup->size + 1;\n Tuple* new_tuple = malloc(sizeof(Tuple));\n new_tuple->elements = malloc(new_size * sizeof(int));\n for (int i = 0; i < test_tup->size; i++) {\n new_tuple->elements[i] = test_tup->elements[i];\n }\n new_tuple->elements[test_tup->size] = -1;\n new_tuple->size = new_size;\n new_tuple->dict = test_dict;\n return new_tuple;\n}", + "test": "int main() {\n\n int arr1[3] = {4, 5, 6};\n\n KeyValuePair pairs1[3] = {{\"MSAM\", 1}, {\"is\", 2}, {\"best\", 3}};\n\n Dictionary dict1 = {pairs1, 3};\n\n Tuple tup1 = {arr1, 3, NULL};\n\n Tuple* res_tup1 = func0(&tup1, &dict1);\n\n\n\n assert(res_tup1->size == 4);\n\n assert(res_tup1->elements[0] == 4);\n\n assert(res_tup1->elements[1] == 5);\n\n assert(res_tup1->elements[2] == 6);\n\n assert(res_tup1->elements[3] == -1);\n\n assert(res_tup1->dict->size == 3);\n\n\n\n int arr2[3] = {1, 2, 3};\n\n KeyValuePair pairs2[3] = {{\"UTS\", 2}, {\"is\", 3}, {\"Worst\", 4}};\n\n Dictionary dict2 = {pairs2, 3};\n\n Tuple tup2 = {arr2, 3, NULL};\n\n Tuple* res_tup2 = func0(&tup2, &dict2);\n\n\n\n assert(res_tup2->size == 4);\n\n assert(res_tup2->elements[0] == 1);\n\n assert(res_tup2->elements[1] == 2);\n\n assert(res_tup2->elements[2] == 3);\n\n assert(res_tup2->elements[3] == -1);\n\n assert(res_tup2->dict->size == 3);\n\n\n\n int arr3[3] = {8, 9, 10};\n\n KeyValuePair pairs3[3] = {{\"POS\", 3}, {\"is\", 4}, {\"Okay\", 5}};\n\n Dictionary dict3 = {pairs3, 3};\n\n Tuple tup3 = {arr3, 3, NULL};\n\n Tuple* res_tup3 = func0(&tup3, &dict3);\n\n\n\n assert(res_tup3->size == 4);\n\n assert(res_tup3->elements[0] == 8);\n\n assert(res_tup3->elements[1] == 9);\n\n assert(res_tup3->elements[2] == 10);\n\n assert(res_tup3->elements[3] == -1);\n\n assert(res_tup3->dict->size == 3);\n\n\n\n printf(\"All tests passed successfully!\\n\");\n\n\n\n free(res_tup1->elements);\n\n free(res_tup1);\n\n free(res_tup2->elements);\n\n free(res_tup2);\n\n free(res_tup3->elements);\n\n free(res_tup3);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\nmov %rsi,%r14\npush %r13\nmov %rdi,%r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov 0x8(%rdi),%r15d\nmov $0x18,%edi\ncallq 10d0 \nlea 0x1(%r15),%ebx\nmov %rax,%r12\nmovslq %ebx,%rbp\nshl $0x2,%rbp\nmov %rbp,%rdi\ncallq 10d0 \nmov %rax,(%r12)\ntest %r15d,%r15d\njle 17b3 \nmov 0x0(%r13),%r8\nlea -0x1(%r15),%edi\nxor %edx,%edx\nmov (%r8,%rdx,4),%ecx\nmov %ecx,(%rax,%rdx,4)\nmov %rdx,%rcx\nadd $0x1,%rdx\ncmp %rdi,%rcx\njne 17a0 \nmovl $0xffffffff,-0x4(%rax,%rbp,1)\nmov %r12,%rax\nmov %ebx,0x8(%r12)\nmov %r14,0x10(%r12)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14, rsi\npush r13\nmov r13, rdi\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r15d, [rdi+8]\nmov edi, 18h; size\ncall _malloc\nlea ebx, [r15+1]\nmov rbp, rax\nmovsxd r12, ebx\nshl r12, 2\nmov rdi, r12; size\ncall _malloc\nmov [rbp+0], rax\ntest r15d, r15d\njle short loc_178F\nmov rdi, [r13+0]\nlea rsi, [r12-4]\nxor edx, edx\nloc_1780:\nmov ecx, [rdi+rdx]\nmov [rax+rdx], ecx\nadd rdx, 4\ncmp rdx, rsi\njnz short loc_1780\nloc_178F:\nmov dword ptr [rax+r12-4], 0FFFFFFFFh\nmov rax, rbp\nmov [rbp+8], ebx\nmov [rbp+10h], r14\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 *a1, __int64 a2)\n{\n int v2; // r15d\n _DWORD *v3; // rbp\n size_t v4; // r12\n char *v5; // rax\n __int64 v6; // rdi\n __int64 v7; // rdx\n _DWORD *result; // rax\n\n v2 = *((_DWORD *)a1 + 2);\n v3 = malloc(0x18uLL);\n v4 = 4LL * (v2 + 1);\n v5 = (char *)malloc(v4);\n *(_QWORD *)v3 = v5;\n if ( v2 > 0 )\n {\n v6 = *a1;\n v7 = 0LL;\n do\n {\n *(_DWORD *)&v5[v7] = *(_DWORD *)(v6 + v7);\n v7 += 4LL;\n }\n while ( v7 != v4 - 4 );\n }\n *(_DWORD *)&v5[v4 - 4] = -1;\n result = v3;\n v3[2] = v2 + 1;\n *((_QWORD *)v3 + 2) = a2;\n return result;\n}", + "ida_strip_asm": "sub_1730:\nendbr64\npush r15\npush r14\nmov r14, rsi\npush r13\nmov r13, rdi\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r15d, [rdi+8]\nmov edi, 18h; size\ncall _malloc\nlea ebx, [r15+1]\nmov rbp, rax\nmovsxd r12, ebx\nshl r12, 2\nmov rdi, r12; size\ncall _malloc\nmov [rbp+0], rax\ntest r15d, r15d\njle short loc_178F\nmov rdi, [r13+0]\nlea rsi, [r12-4]\nxor edx, edx\nloc_1780:\nmov ecx, [rdi+rdx]\nmov [rax+rdx], ecx\nadd rdx, 4\ncmp rdx, rsi\njnz short loc_1780\nloc_178F:\nmov dword ptr [rax+r12-4], 0FFFFFFFFh\nmov rax, rbp\nmov [rbp+8], ebx\nmov [rbp+10h], r14\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1730(__int64 *a1, __int64 a2)\n{\n int v2; // r15d\n _DWORD *v3; // rbp\n size_t v4; // r12\n char *v5; // rax\n __int64 v6; // rdi\n __int64 v7; // rdx\n _DWORD *result; // rax\n\n v2 = *((_DWORD *)a1 + 2);\n v3 = malloc(0x18uLL);\n v4 = 4LL * (v2 + 1);\n v5 = (char *)malloc(v4);\n *(_QWORD *)v3 = v5;\n if ( v2 > 0 )\n {\n v6 = *a1;\n v7 = 0LL;\n do\n {\n *(_DWORD *)&v5[v7] = *(_DWORD *)(v6 + v7);\n v7 += 4LL;\n }\n while ( v7 != v4 - 4 );\n }\n *(_DWORD *)&v5[v4 - 4] = -1;\n result = v3;\n v3[2] = v2 + 1;\n *((_QWORD *)v3 + 2) = a2;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1730(long long *a1, long long a2) {\n int v2;\n uint32_t *v3;\n unsigned int v4;\n char *v5;\n long long v6;\n long long v7;\n uint32_t *result;\n v2 = *((uint32_t *)a1 + 2);\n v3 = malloc(24uLL);\n v4 = 4LL * (v2 + 1);\n v5 = (char *)malloc(v4);\n *(uint64_t *)v3 = v5;\n if (v2 > 0) {\n v6 = *a1;\n v7 = 0LL;\n do {\n *(uint32_t *)&v5[v7] = *(uint32_t *)(v6 + v7);\n v7 += 4LL;\n } while (v7 != v4 - 4);\n }\n *(uint32_t *)&v5[v4 - 4] = -1;\n result = v3;\n v3[2] = v2 + 1;\n *((uint64_t *)v3 + 2) = a2;\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long *a1, long long a2) {\n int v2;\n uint32_t *v3;\n unsigned int v4;\n char *v5;\n long long v6;\n long long v7;\n uint32_t *result;\n v2 = *((uint32_t *)a1 + 2);\n v3 = malloc(24uLL);\n v4 = 4LL * (v2 + 1);\n v5 = (char *)malloc(v4);\n *(uint64_t *)v3 = v5;\n if (v2 > 0) {\n v6 = *a1;\n v7 = 0LL;\n do {\n *(uint32_t *)&v5[v7] = *(uint32_t *)(v6 + v7);\n v7 += 4LL;\n } while (v7 != v4 - 4);\n }\n *(uint32_t *)&v5[v4 - 4] = -1;\n result = v3;\n v3[2] = v2 + 1;\n *((uint64_t *)v3 + 2) = a2;\n return result;\n}" + }, + { + "index": 720, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n const char* key;\n\n int value;\n\n} KeyValuePair;\n\n\n\ntypedef struct {\n\n KeyValuePair* pairs;\n\n int size;\n\n} Dictionary;\n\n\n\ntypedef struct {\n\n int* elements;\n\n int size;\n\n Dictionary* dict;\n\n} Tuple;\n\n\n\n", + "func": "Tuple* func0(Tuple* test_tup, Dictionary* test_dict) {\n int new_size = test_tup->size + 1;\n Tuple* new_tuple = malloc(sizeof(Tuple));\n new_tuple->elements = malloc(new_size * sizeof(int));\n for (int i = 0; i < test_tup->size; i++) {\n new_tuple->elements[i] = test_tup->elements[i];\n }\n new_tuple->elements[test_tup->size] = -1;\n new_tuple->size = new_size;\n new_tuple->dict = test_dict;\n return new_tuple;\n}", + "test": "int main() {\n\n int arr1[3] = {4, 5, 6};\n\n KeyValuePair pairs1[3] = {{\"MSAM\", 1}, {\"is\", 2}, {\"best\", 3}};\n\n Dictionary dict1 = {pairs1, 3};\n\n Tuple tup1 = {arr1, 3, NULL};\n\n Tuple* res_tup1 = func0(&tup1, &dict1);\n\n\n\n assert(res_tup1->size == 4);\n\n assert(res_tup1->elements[0] == 4);\n\n assert(res_tup1->elements[1] == 5);\n\n assert(res_tup1->elements[2] == 6);\n\n assert(res_tup1->elements[3] == -1);\n\n assert(res_tup1->dict->size == 3);\n\n\n\n int arr2[3] = {1, 2, 3};\n\n KeyValuePair pairs2[3] = {{\"UTS\", 2}, {\"is\", 3}, {\"Worst\", 4}};\n\n Dictionary dict2 = {pairs2, 3};\n\n Tuple tup2 = {arr2, 3, NULL};\n\n Tuple* res_tup2 = func0(&tup2, &dict2);\n\n\n\n assert(res_tup2->size == 4);\n\n assert(res_tup2->elements[0] == 1);\n\n assert(res_tup2->elements[1] == 2);\n\n assert(res_tup2->elements[2] == 3);\n\n assert(res_tup2->elements[3] == -1);\n\n assert(res_tup2->dict->size == 3);\n\n\n\n int arr3[3] = {8, 9, 10};\n\n KeyValuePair pairs3[3] = {{\"POS\", 3}, {\"is\", 4}, {\"Okay\", 5}};\n\n Dictionary dict3 = {pairs3, 3};\n\n Tuple tup3 = {arr3, 3, NULL};\n\n Tuple* res_tup3 = func0(&tup3, &dict3);\n\n\n\n assert(res_tup3->size == 4);\n\n assert(res_tup3->elements[0] == 8);\n\n assert(res_tup3->elements[1] == 9);\n\n assert(res_tup3->elements[2] == 10);\n\n assert(res_tup3->elements[3] == -1);\n\n assert(res_tup3->dict->size == 3);\n\n\n\n printf(\"All tests passed successfully!\\n\");\n\n\n\n free(res_tup1->elements);\n\n free(res_tup1);\n\n free(res_tup2->elements);\n\n free(res_tup2);\n\n free(res_tup3->elements);\n\n free(res_tup3);\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmov %rsi,%r15\npush %r14\nmov %rdi,%r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov 0x8(%rdi),%ebp\nmov $0x18,%edi\ncallq 10d0 \nlea 0x1(%rbp),%ebx\nmov %rax,%r12\nmovslq %ebx,%r13\nshl $0x2,%r13\nmov %r13,%rdi\ncallq 10d0 \nmov %rax,(%r12)\ntest %ebp,%ebp\njle 1805 \nmov (%r14),%rcx\nlea 0xf(%rax),%rsi\nlea -0x1(%rbp),%edx\nsub %rcx,%rsi\ncmp $0x1e,%rsi\njbe 1830 \ncmp $0x3,%edx\njbe 1830 \nmov %ebp,%edi\nxor %edx,%edx\nshr $0x2,%edi\nshl $0x4,%rdi\nnopl (%rax)\nmovdqu (%rcx,%rdx,1),%xmm0\nmovups %xmm0,(%rax,%rdx,1)\nadd $0x10,%rdx\ncmp %rdi,%rdx\njne 17c0 \nmov %ebp,%edx\nand $0xfffffffc,%edx\ntest $0x3,%bpl\nje 1805 \nmov %edx,%esi\nmov (%rcx,%rsi,4),%edi\nmov %edi,(%rax,%rsi,4)\nlea 0x1(%rdx),%esi\ncmp %esi,%ebp\njle 1805 \nmovslq %esi,%rsi\nadd $0x2,%edx\nmov (%rcx,%rsi,4),%edi\nmov %edi,(%rax,%rsi,4)\ncmp %edx,%ebp\njle 1805 \nmovslq %edx,%rdx\nmov (%rcx,%rdx,4),%ecx\nmov %ecx,(%rax,%rdx,4)\nmovl $0xffffffff,-0x4(%rax,%r13,1)\nmov %r12,%rax\nmov %ebx,0x8(%r12)\nmov %r15,0x10(%r12)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw 0x0(%rax,%rax,1)\nmov %edx,%esi\nxor %edx,%edx\nnopl 0x0(%rax)\nmov (%rcx,%rdx,4),%edi\nmov %edi,(%rax,%rdx,4)\nmov %rdx,%rdi\nadd $0x1,%rdx\ncmp %rsi,%rdi\njne 1838 \njmp 1805 \nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14, rsi\npush r13\nmov r13, rdi\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r15d, [rdi+8]\nmov edi, 18h; size\ncall _malloc\nlea ebx, [r15+1]\nmov rbp, rax\nmovsxd r12, ebx\nshl r12, 2\nmov rdi, r12; size\ncall _malloc\nmov [rbp+0], rax\nmov rdx, rax\ntest r15d, r15d\njle short loc_17AF\nlea eax, [r15-1]\nmov rcx, [r13+0]\ncmp eax, 2\njbe short loc_1795\nlea rsi, [rcx+4]\nmov rax, rdx\nsub rax, rsi\ncmp rax, 8\nja short loc_17D8\nloc_1795:\nlea rdi, [r12-4]\nxor eax, eax\nnop dword ptr [rax+00h]\nloc_17A0:\nmov esi, [rcx+rax]\nmov [rdx+rax], esi\nadd rax, 4\ncmp rdi, rax\njnz short loc_17A0\nloc_17AF:\nmov dword ptr [rdx+r12-4], 0FFFFFFFFh\nmov rax, rbp\nmov [rbp+8], ebx\nmov [rbp+10h], r14\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_17D8:\nmov esi, r15d\nxor eax, eax\nshr esi, 2\nshl rsi, 4\nnop dword ptr [rax+00h]\nloc_17E8:\nmovdqu xmm0, xmmword ptr [rcx+rax]\nmovups xmmword ptr [rdx+rax], xmm0\nadd rax, 10h\ncmp rax, rsi\njnz short loc_17E8\nmov eax, r15d\nand eax, 0FFFFFFFCh\ntest r15b, 3\njz short loc_17AF\nmov edi, eax\nmov r8d, [rcx+rdi*4]\nlea rsi, ds:0[rdi*4]\nmov [rdx+rdi*4], r8d\nlea edi, [rax+1]\ncmp r15d, edi\njle short loc_17AF\nmov edi, [rcx+rsi+4]\nadd eax, 2\nmov [rdx+rsi+4], edi\ncmp r15d, eax\njle loc_17AF\nmov eax, [rcx+rsi+8]\nmov [rdx+rsi+8], eax\njmp loc_17AF", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 *a1, __int64 a2)\n{\n int v3; // r15d\n _DWORD *v4; // rbp\n size_t v5; // r12\n char *v6; // rax\n char *v7; // rdx\n __int64 v8; // rcx\n __int64 v9; // rax\n _DWORD *result; // rax\n __int64 v11; // rax\n unsigned int v12; // eax\n __int64 v13; // rsi\n\n v3 = *((_DWORD *)a1 + 2);\n v4 = malloc(0x18uLL);\n v5 = 4LL * (v3 + 1);\n v6 = (char *)malloc(v5);\n *(_QWORD *)v4 = v6;\n v7 = v6;\n if ( v3 > 0 )\n {\n v8 = *a1;\n if ( (unsigned int)(v3 - 1) > 2 && (unsigned __int64)&v6[-v8 - 4] > 8 )\n {\n v11 = 0LL;\n do\n {\n *(__m128i *)&v7[v11] = _mm_loadu_si128((const __m128i *)(v8 + v11));\n v11 += 16LL;\n }\n while ( v11 != 16LL * ((unsigned int)v3 >> 2) );\n v12 = v3 & 0x7FFFFFFC;\n if ( (v3 & 3) != 0 )\n {\n v13 = 4LL * v12;\n *(_DWORD *)&v7[v13] = *(_DWORD *)(v8 + v13);\n if ( v3 > (int)(v12 + 1) )\n {\n *(_DWORD *)&v7[v13 + 4] = *(_DWORD *)(v8 + v13 + 4);\n if ( v3 > (int)(v12 + 2) )\n *(_DWORD *)&v7[v13 + 8] = *(_DWORD *)(v8 + v13 + 8);\n }\n }\n }\n else\n {\n v9 = 0LL;\n do\n {\n *(_DWORD *)&v7[v9] = *(_DWORD *)(v8 + v9);\n v9 += 4LL;\n }\n while ( v5 - 4 != v9 );\n }\n }\n *(_DWORD *)&v7[v5 - 4] = -1;\n result = v4;\n v4[2] = v3 + 1;\n *((_QWORD *)v4 + 2) = a2;\n return result;\n}", + "ida_strip_asm": "sub_1730:\nendbr64\npush r15\npush r14\nmov r14, rsi\npush r13\nmov r13, rdi\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r15d, [rdi+8]\nmov edi, 18h; size\ncall _malloc\nlea ebx, [r15+1]\nmov rbp, rax\nmovsxd r12, ebx\nshl r12, 2\nmov rdi, r12; size\ncall _malloc\nmov [rbp+0], rax\nmov rdx, rax\ntest r15d, r15d\njle short loc_17AF\nlea eax, [r15-1]\nmov rcx, [r13+0]\ncmp eax, 2\njbe short loc_1795\nlea rsi, [rcx+4]\nmov rax, rdx\nsub rax, rsi\ncmp rax, 8\nja short loc_17D8\nloc_1795:\nlea rdi, [r12-4]\nxor eax, eax\nnop dword ptr [rax+00h]\nloc_17A0:\nmov esi, [rcx+rax]\nmov [rdx+rax], esi\nadd rax, 4\ncmp rdi, rax\njnz short loc_17A0\nloc_17AF:\nmov dword ptr [rdx+r12-4], 0FFFFFFFFh\nmov rax, rbp\nmov [rbp+8], ebx\nmov [rbp+10h], r14\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_17D8:\nmov esi, r15d\nxor eax, eax\nshr esi, 2\nshl rsi, 4\nnop dword ptr [rax+00h]\nloc_17E8:\nmovdqu xmm0, xmmword ptr [rcx+rax]\nmovups xmmword ptr [rdx+rax], xmm0\nadd rax, 10h\ncmp rax, rsi\njnz short loc_17E8\nmov eax, r15d\nand eax, 0FFFFFFFCh\ntest r15b, 3\njz short loc_17AF\nmov edi, eax\nmov r8d, [rcx+rdi*4]\nlea rsi, ds:0[rdi*4]\nmov [rdx+rdi*4], r8d\nlea edi, [rax+1]\ncmp r15d, edi\njle short loc_17AF\nmov edi, [rcx+rsi+4]\nadd eax, 2\nmov [rdx+rsi+4], edi\ncmp r15d, eax\njle loc_17AF\nmov eax, [rcx+rsi+8]\nmov [rdx+rsi+8], eax\njmp loc_17AF", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1730(__int64 *a1, __int64 a2)\n{\n int v3; // r15d\n _DWORD *v4; // rbp\n size_t v5; // r12\n char *v6; // rax\n char *v7; // rdx\n __int64 v8; // rcx\n __int64 v9; // rax\n _DWORD *result; // rax\n __int64 v11; // rax\n unsigned int v12; // eax\n __int64 v13; // rsi\n\n v3 = *((_DWORD *)a1 + 2);\n v4 = malloc(0x18uLL);\n v5 = 4LL * (v3 + 1);\n v6 = (char *)malloc(v5);\n *(_QWORD *)v4 = v6;\n v7 = v6;\n if ( v3 > 0 )\n {\n v8 = *a1;\n if ( (unsigned int)(v3 - 1) > 2 && (unsigned __int64)&v6[-v8 - 4] > 8 )\n {\n v11 = 0LL;\n do\n {\n *(__m128i *)&v7[v11] = _mm_loadu_si128((const __m128i *)(v8 + v11));\n v11 += 16LL;\n }\n while ( v11 != 16LL * ((unsigned int)v3 >> 2) );\n v12 = v3 & 0x7FFFFFFC;\n if ( (v3 & 3) != 0 )\n {\n v13 = 4LL * v12;\n *(_DWORD *)&v7[v13] = *(_DWORD *)(v8 + v13);\n if ( v3 > (int)(v12 + 1) )\n {\n *(_DWORD *)&v7[v13 + 4] = *(_DWORD *)(v8 + v13 + 4);\n if ( v3 > (int)(v12 + 2) )\n *(_DWORD *)&v7[v13 + 8] = *(_DWORD *)(v8 + v13 + 8);\n }\n }\n }\n else\n {\n v9 = 0LL;\n do\n {\n *(_DWORD *)&v7[v9] = *(_DWORD *)(v8 + v9);\n v9 += 4LL;\n }\n while ( v5 - 4 != v9 );\n }\n }\n *(_DWORD *)&v7[v5 - 4] = -1;\n result = v4;\n v4[2] = v3 + 1;\n *((_QWORD *)v4 + 2) = a2;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1730(long long *a1, long long a2) {\n int v3;\n uint32_t *v4;\n unsigned int v5;\n char *v6;\n char *v7;\n long long v8;\n long long v9;\n uint32_t *result;\n long long v11;\n unsigned int v12;\n long long v13;\n v3 = *((uint32_t *)a1 + 2);\n v4 = malloc(24uLL);\n v5 = 4LL * (v3 + 1);\n v6 = (char *)malloc(v5);\n *(uint64_t *)v4 = v6;\n v7 = v6;\n if (v3 > 0) {\n v8 = *a1;\n if ((unsigned int)(v3 - 1) > 2 && (unsigned long long)&v6[-v8 - 4] > 8) {\n v11 = 0LL;\n do {\n *(__m128i *)&v7[v11] = _mm_loadu_si128((const __m128i *)(v8 + v11));\n v11 += 16LL;\n } while (v11 != 16LL * ((unsigned int)v3 >> 2));\n v12 = v3 & 2147483644;\n if ((v3 & 3) != 0) {\n v13 = 4LL * v12;\n *(uint32_t *)&v7[v13] = *(uint32_t *)(v8 + v13);\n if (v3 > (int)(v12 + 1)) {\n *(uint32_t *)&v7[v13 + 4] = *(uint32_t *)(v8 + v13 + 4);\n if (v3 > (int)(v12 + 2))\n *(uint32_t *)&v7[v13 + 8] = *(uint32_t *)(v8 + v13 + 8);\n }\n }\n } else {\n v9 = 0LL;\n do {\n *(uint32_t *)&v7[v9] = *(uint32_t *)(v8 + v9);\n v9 += 4LL;\n } while (v5 - 4 != v9);\n }\n }\n *(uint32_t *)&v7[v5 - 4] = -1;\n result = v4;\n v4[2] = v3 + 1;\n *((uint64_t *)v4 + 2) = a2;\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long *a1, long long a2) {\n int v3;\n uint32_t *v4;\n unsigned int v5;\n char *v6;\n char *v7;\n long long v8;\n long long v9;\n uint32_t *result;\n long long v11;\n unsigned int v12;\n long long v13;\n v3 = *((uint32_t *)a1 + 2);\n v4 = malloc(24uLL);\n v5 = 4LL * (v3 + 1);\n v6 = (char *)malloc(v5);\n *(uint64_t *)v4 = v6;\n v7 = v6;\n if (v3 > 0) {\n v8 = *a1;\n if ((unsigned int)(v3 - 1) > 2 && (unsigned long long)&v6[-v8 - 4] > 8) {\n v11 = 0LL;\n do {\n *(__m128i *)&v7[v11] = _mm_loadu_si128((const __m128i *)(v8 + v11));\n v11 += 16LL;\n } while (v11 != 16LL * ((unsigned int)v3 >> 2));\n v12 = v3 & 2147483644;\n if ((v3 & 3) != 0) {\n v13 = 4LL * v12;\n *(uint32_t *)&v7[v13] = *(uint32_t *)(v8 + v13);\n if (v3 > (int)(v12 + 1)) {\n *(uint32_t *)&v7[v13 + 4] = *(uint32_t *)(v8 + v13 + 4);\n if (v3 > (int)(v12 + 2))\n *(uint32_t *)&v7[v13 + 8] = *(uint32_t *)(v8 + v13 + 8);\n }\n }\n } else {\n v9 = 0LL;\n do {\n *(uint32_t *)&v7[v9] = *(uint32_t *)(v8 + v9);\n v9 += 4LL;\n } while (v5 - 4 != v9);\n }\n }\n *(uint32_t *)&v7[v5 - 4] = -1;\n result = v4;\n v4[2] = v3 + 1;\n *((uint64_t *)v4 + 2) = a2;\n return result;\n}" + }, + { + "index": 721, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int cost[][100], int N) {\n int dp[100][100] = {0};\n dp[0][0] = cost[0][0];\n for (int i = 1; i < N; i++) {\n dp[i][0] = dp[i - 1][0] + cost[i][0];\n }\n for (int j = 1; j < N; j++) {\n dp[0][j] = dp[0][j - 1] + cost[0][j];\n }\n for (int i = 1; i < N; i++) {\n for (int j = 1; j < N; j++) {\n dp[i][j] = (dp[i - 1][j] > dp[i][j - 1] ? dp[i - 1][j] : dp[i][j - 1]) +\n cost[i][j];\n }\n }\n return (double)dp[N - 1][N - 1] / (2 * N - 1);\n}", + "test": "int main() {\n\n int cost1[3][100] = { {1, 2, 3}, {6, 5, 4}, {7, 3, 9} };\n\n assert(func0(cost1, 3) == 5.2);\n\n \n\n int cost2[3][100] = { {2, 3, 4}, {7, 6, 5}, {8, 4, 10} };\n\n assert(func0(cost2, 3) == 6.2);\n\n \n\n int cost3[3][100] = { {3, 4, 5}, {8, 7, 6}, {9, 5, 11} };\n\n assert(func0(cost3, 3) == 7.2);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nlea -0x9000(%rsp),%r11\nsub $0x1000,%rsp\norq $0x0,(%rsp)\ncmp %r11,%rsp\njne 1199 \nsub $0xc70,%rsp\nmov %rdi,-0x9c68(%rbp)\nmov %esi,-0x9c6c(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea -0x9c50(%rbp),%rax\nmov $0x9c40,%edx\nmov $0x0,%esi\nmov %rax,%rdi\ncallq 1090 \nmov -0x9c68(%rbp),%rax\nmov (%rax),%eax\nmov %eax,-0x9c50(%rbp)\nmovl $0x1,-0x9c60(%rbp)\njmpq 129b \nmov -0x9c60(%rbp),%eax\nsub $0x1,%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nshl $0x4,%rax\nadd %rbp,%rax\nsub $0x9c50,%rax\nmov (%rax),%ecx\nmov -0x9c60(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x9c68(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nadd %eax,%ecx\nmov -0x9c60(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nshl $0x4,%rax\nadd %rbp,%rax\nsub $0x9c50,%rax\nmov %ecx,(%rax)\naddl $0x1,-0x9c60(%rbp)\nmov -0x9c60(%rbp),%eax\ncmp -0x9c6c(%rbp),%eax\njl 1204 \nmovl $0x1,-0x9c5c(%rbp)\njmp 12f7 \nmov -0x9c5c(%rbp),%eax\nsub $0x1,%eax\ncltq\nmov -0x9c50(%rbp,%rax,4),%ecx\nmov -0x9c68(%rbp),%rax\nmov -0x9c5c(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nlea (%rcx,%rax,1),%edx\nmov -0x9c5c(%rbp),%eax\ncltq\nmov %edx,-0x9c50(%rbp,%rax,4)\naddl $0x1,-0x9c5c(%rbp)\nmov -0x9c5c(%rbp),%eax\ncmp -0x9c6c(%rbp),%eax\njl 12b9 \nmovl $0x1,-0x9c58(%rbp)\njmpq 142b \nmovl $0x1,-0x9c54(%rbp)\njmpq 1412 \nmov -0x9c54(%rbp),%eax\nsub $0x1,%eax\nmovslq %eax,%rcx\nmov -0x9c58(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rcx,%rax\nmov -0x9c50(%rbp,%rax,4),%edx\nmov -0x9c58(%rbp),%eax\nlea -0x1(%rax),%ecx\nmov -0x9c54(%rbp),%eax\nmovslq %eax,%rsi\nmovslq %ecx,%rcx\nmov %rcx,%rax\nshl $0x2,%rax\nadd %rcx,%rax\nlea 0x0(,%rax,4),%rcx\nadd %rcx,%rax\nshl $0x2,%rax\nadd %rsi,%rax\nmov -0x9c50(%rbp,%rax,4),%eax\ncmp %eax,%edx\ncmovge %edx,%eax\nmov %eax,%ecx\nmov -0x9c58(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x9c68(%rbp),%rax\nadd %rax,%rdx\nmov -0x9c54(%rbp),%eax\ncltq\nmov (%rdx,%rax,4),%eax\nadd %eax,%ecx\nmov -0x9c54(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x9c58(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rsi,%rax\nmov %ecx,-0x9c50(%rbp,%rax,4)\naddl $0x1,-0x9c54(%rbp)\nmov -0x9c54(%rbp),%eax\ncmp -0x9c6c(%rbp),%eax\njl 1323 \naddl $0x1,-0x9c58(%rbp)\nmov -0x9c58(%rbp),%eax\ncmp -0x9c6c(%rbp),%eax\njl 1314 \nmov -0x9c6c(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x9c6c(%rbp),%eax\nsub $0x1,%eax\nmovslq %eax,%rcx\nmovslq %edx,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rcx,%rax\nmov -0x9c50(%rbp,%rax,4),%eax\ncvtsi2sd %eax,%xmm0\nmov -0x9c6c(%rbp),%eax\nadd %eax,%eax\nsub $0x1,%eax\ncvtsi2sd %eax,%xmm1\ndivsd %xmm1,%xmm0\nmov -0x8(%rbp),%rax\nxor %fs:0x28,%rax\nje 14a3 \ncallq 1070 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nlea r11, [rsp+var_9000]\nloc_1199:\nsub rsp, 1000h\nor [rsp+1000h+var_1000], 0\ncmp rsp, r11\njnz short loc_1199\nsub rsp, 0C70h\nmov [rbp+var_9C68], rdi\nmov [rbp+var_9C6C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [rbp+s]\nmov edx, 9C40h; n\nmov esi, 0; c\nmov rdi, rax; s\ncall _memset\nmov rax, [rbp+var_9C68]\nmov eax, [rax]\nmov [rbp+s], eax\nmov [rbp+var_9C60], 1\njmp loc_129B\nloc_1204:\nmov eax, [rbp+var_9C60]\nsub eax, 1\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nadd rax, rbp\nsub rax, 9C50h\nmov ecx, [rax]\nmov eax, [rbp+var_9C60]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_9C68]\nadd rax, rdx\nmov eax, [rax]\nadd ecx, eax\nmov eax, [rbp+var_9C60]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nadd rax, rbp\nsub rax, 9C50h\nmov [rax], ecx\nadd [rbp+var_9C60], 1\nloc_129B:\nmov eax, [rbp+var_9C60]\ncmp eax, [rbp+var_9C6C]\njl loc_1204\nmov [rbp+var_9C5C], 1\njmp short loc_12F7\nloc_12B9:\nmov eax, [rbp+var_9C5C]\nsub eax, 1\ncdqe\nmov ecx, [rbp+rax*4+s]\nmov rax, [rbp+var_9C68]\nmov edx, [rbp+var_9C5C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nlea edx, [rcx+rax]\nmov eax, [rbp+var_9C5C]\ncdqe\nmov [rbp+rax*4+s], edx\nadd [rbp+var_9C5C], 1\nloc_12F7:\nmov eax, [rbp+var_9C5C]\ncmp eax, [rbp+var_9C6C]\njl short loc_12B9\nmov [rbp+var_9C58], 1\njmp loc_142B\nloc_1314:\nmov [rbp+var_9C54], 1\njmp loc_1412\nloc_1323:\nmov eax, [rbp+var_9C54]\nsub eax, 1\nmovsxd rcx, eax\nmov eax, [rbp+var_9C58]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 2\nadd rax, rcx\nmov edx, [rbp+rax*4+s]\nmov eax, [rbp+var_9C58]\nlea ecx, [rax-1]\nmov eax, [rbp+var_9C54]\nmovsxd rsi, eax\nmovsxd rcx, ecx\nmov rax, rcx\nshl rax, 2\nadd rax, rcx\nlea rcx, ds:0[rax*4]\nadd rax, rcx\nshl rax, 2\nadd rax, rsi\nmov eax, [rbp+rax*4+s]\ncmp edx, eax\ncmovge eax, edx\nmov ecx, eax\nmov eax, [rbp+var_9C58]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_9C68]\nadd rdx, rax\nmov eax, [rbp+var_9C54]\ncdqe\nmov eax, [rdx+rax*4]\nadd ecx, eax\nmov eax, [rbp+var_9C54]\nmovsxd rsi, eax\nmov eax, [rbp+var_9C58]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 2\nadd rax, rsi\nmov [rbp+rax*4+s], ecx\nadd [rbp+var_9C54], 1\nloc_1412:\nmov eax, [rbp+var_9C54]\ncmp eax, [rbp+var_9C6C]\njl loc_1323\nadd [rbp+var_9C58], 1\nloc_142B:\nmov eax, [rbp+var_9C58]\ncmp eax, [rbp+var_9C6C]\njl loc_1314\nmov eax, [rbp+var_9C6C]\nlea edx, [rax-1]\nmov eax, [rbp+var_9C6C]\nsub eax, 1\nmovsxd rcx, eax\nmovsxd rdx, edx\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 2\nadd rax, rcx\nmov eax, [rbp+rax*4+s]\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmov eax, [rbp+var_9C6C]\nadd eax, eax\nsub eax, 1\npxor xmm1, xmm1\ncvtsi2sd xmm1, eax\ndivsd xmm0, xmm1\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njz short locret_14AB\ncall ___stack_chk_fail\nlocret_14AB:\nleave\nretn", + "ida_pseudo": "// bad sp value at call has been detected, the output may be wrong!\nunsigned __int64 __fastcall func0(_DWORD *a1, int a2)\n{\n int v2; // eax\n int i; // [rsp+Ch] [rbp-9C60h]\n int j; // [rsp+10h] [rbp-9C5Ch]\n int k; // [rsp+14h] [rbp-9C58h]\n int m; // [rsp+18h] [rbp-9C54h]\n _DWORD s[788]; // [rsp+1Ch] [rbp-9C50h] BYREF\n char v9; // [rsp+C6Ch] [rbp-9000h] BYREF\n __int64 v10; // [rsp+8C6Ch] [rbp-1000h] BYREF\n unsigned __int64 v11; // [rsp+9C64h] [rbp-8h]\n\n while ( &v10 != (__int64 *)&v9 )\n ;\n v11 = __readfsqword(0x28u);\n memset(s, 0, 0x9C40uLL);\n s[0] = *a1;\n for ( i = 1; i < a2; ++i )\n s[100 * i] = a1[100 * i] + s[100 * i - 100];\n for ( j = 1; j < a2; ++j )\n s[j] = s[j - 1] + a1[j];\n for ( k = 1; k < a2; ++k )\n {\n for ( m = 1; m < a2; ++m )\n {\n v2 = s[100 * k - 100 + m];\n if ( s[100 * k - 1 + m] >= v2 )\n v2 = s[100 * k - 1 + m];\n s[100 * k + m] = a1[100 * k + m] + v2;\n }\n }\n return v11 - __readfsqword(0x28u);\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nlea r11, [rsp+var_9000]\nloc_1199:\nsub rsp, 1000h\nor [rsp+1000h+var_1000], 0\ncmp rsp, r11\njnz short loc_1199\nsub rsp, 0C70h\nmov [rbp+var_9C68], rdi\nmov [rbp+var_9C6C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [rbp+s]\nmov edx, 9C40h; n\nmov esi, 0; c\nmov rdi, rax; s\ncall _memset\nmov rax, [rbp+var_9C68]\nmov eax, [rax]\nmov [rbp+s], eax\nmov [rbp+var_9C60], 1\njmp loc_129B\nloc_1204:\nmov eax, [rbp+var_9C60]\nsub eax, 1\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nadd rax, rbp\nsub rax, 9C50h\nmov ecx, [rax]\nmov eax, [rbp+var_9C60]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_9C68]\nadd rax, rdx\nmov eax, [rax]\nadd ecx, eax\nmov eax, [rbp+var_9C60]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nadd rax, rbp\nsub rax, 9C50h\nmov [rax], ecx\nadd [rbp+var_9C60], 1\nloc_129B:\nmov eax, [rbp+var_9C60]\ncmp eax, [rbp+var_9C6C]\njl loc_1204\nmov [rbp+var_9C5C], 1\njmp short loc_12F7\nloc_12B9:\nmov eax, [rbp+var_9C5C]\nsub eax, 1\ncdqe\nmov ecx, [rbp+rax*4+s]\nmov rax, [rbp+var_9C68]\nmov edx, [rbp+var_9C5C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nlea edx, [rcx+rax]\nmov eax, [rbp+var_9C5C]\ncdqe\nmov [rbp+rax*4+s], edx\nadd [rbp+var_9C5C], 1\nloc_12F7:\nmov eax, [rbp+var_9C5C]\ncmp eax, [rbp+var_9C6C]\njl short loc_12B9\nmov [rbp+var_9C58], 1\njmp loc_142B\nloc_1314:\nmov [rbp+var_9C54], 1\njmp loc_1412\nloc_1323:\nmov eax, [rbp+var_9C54]\nsub eax, 1\nmovsxd rcx, eax\nmov eax, [rbp+var_9C58]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 2\nadd rax, rcx\nmov edx, [rbp+rax*4+s]\nmov eax, [rbp+var_9C58]\nlea ecx, [rax-1]\nmov eax, [rbp+var_9C54]\nmovsxd rsi, eax\nmovsxd rcx, ecx\nmov rax, rcx\nshl rax, 2\nadd rax, rcx\nlea rcx, ds:0[rax*4]\nadd rax, rcx\nshl rax, 2\nadd rax, rsi\nmov eax, [rbp+rax*4+s]\ncmp edx, eax\ncmovge eax, edx\nmov ecx, eax\nmov eax, [rbp+var_9C58]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_9C68]\nadd rdx, rax\nmov eax, [rbp+var_9C54]\ncdqe\nmov eax, [rdx+rax*4]\nadd ecx, eax\nmov eax, [rbp+var_9C54]\nmovsxd rsi, eax\nmov eax, [rbp+var_9C58]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 2\nadd rax, rsi\nmov [rbp+rax*4+s], ecx\nadd [rbp+var_9C54], 1\nloc_1412:\nmov eax, [rbp+var_9C54]\ncmp eax, [rbp+var_9C6C]\njl loc_1323\nadd [rbp+var_9C58], 1\nloc_142B:\nmov eax, [rbp+var_9C58]\ncmp eax, [rbp+var_9C6C]\njl loc_1314\nmov eax, [rbp+var_9C6C]\nlea edx, [rax-1]\nmov eax, [rbp+var_9C6C]\nsub eax, 1\nmovsxd rcx, eax\nmovsxd rdx, edx\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 2\nadd rax, rcx\nmov eax, [rbp+rax*4+s]\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmov eax, [rbp+var_9C6C]\nadd eax, eax\nsub eax, 1\npxor xmm1, xmm1\ncvtsi2sd xmm1, eax\ndivsd xmm0, xmm1\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njz short locret_14AB\ncall ___stack_chk_fail\nlocret_14AB:\nleave\nretn", + "ida_strip_pseudo": "// bad sp value at call has been detected, the output may be wrong!\nunsigned __int64 __fastcall sub_1189(_DWORD *a1, int a2)\n{\n int v2; // eax\n int i; // [rsp+Ch] [rbp-9C60h]\n int j; // [rsp+10h] [rbp-9C5Ch]\n int k; // [rsp+14h] [rbp-9C58h]\n int m; // [rsp+18h] [rbp-9C54h]\n _DWORD s[788]; // [rsp+1Ch] [rbp-9C50h] BYREF\n char v9; // [rsp+C6Ch] [rbp-9000h] BYREF\n __int64 v10; // [rsp+8C6Ch] [rbp-1000h] BYREF\n unsigned __int64 v11; // [rsp+9C64h] [rbp-8h]\n\n while ( &v10 != (__int64 *)&v9 )\n ;\n v11 = __readfsqword(0x28u);\n memset(s, 0, 0x9C40uLL);\n s[0] = *a1;\n for ( i = 1; i < a2; ++i )\n s[100 * i] = a1[100 * i] + s[100 * i - 100];\n for ( j = 1; j < a2; ++j )\n s[j] = s[j - 1] + a1[j];\n for ( k = 1; k < a2; ++k )\n {\n for ( m = 1; m < a2; ++m )\n {\n v2 = s[100 * k - 100 + m];\n if ( s[100 * k - 1 + m] >= v2 )\n v2 = s[100 * k - 1 + m];\n s[100 * k + m] = a1[100 * k + m] + v2;\n }\n }\n return v11 - __readfsqword(0x28u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_1189(uint32_t *a1, int a2) {\n int v2;\n int i;\n int j;\n int k;\n int m;\n uint32_t s[788];\n char v9;\n long long v10;\n unsigned long long v11;\n while (&v10 != (long long *)&v9)\n ;\n v11 = __readfsqword(40u);\n memset(s, 0, 40000uLL);\n s[0] = *a1;\n for (i = 1; i < a2; ++i) s[100 * i] = a1[100 * i] + s[100 * i - 100];\n for (j = 1; j < a2; ++j) s[j] = s[j - 1] + a1[j];\n for (k = 1; k < a2; ++k) {\n for (m = 1; m < a2; ++m) {\n v2 = s[100 * k - 100 + m];\n if (s[100 * k - 1 + m] >= v2) v2 = s[100 * k - 1 + m];\n s[100 * k + m] = a1[100 * k + m] + v2;\n }\n }\n return v11 - __readfsqword(40u);\n}", + "ida_pseudo_norm": "unsigned long long func0(uint32_t *a1, int a2) {\n int v2;\n int i;\n int j;\n int k;\n int m;\n uint32_t s[788];\n char v9;\n long long v10;\n unsigned long long v11;\n while (&v10 != (long long *)&v9)\n ;\n v11 = __readfsqword(40u);\n memset(s, 0, 40000uLL);\n s[0] = *a1;\n for (i = 1; i < a2; ++i) s[100 * i] = a1[100 * i] + s[100 * i - 100];\n for (j = 1; j < a2; ++j) s[j] = s[j - 1] + a1[j];\n for (k = 1; k < a2; ++k) {\n for (m = 1; m < a2; ++m) {\n v2 = s[100 * k - 100 + m];\n if (s[100 * k - 1 + m] >= v2) v2 = s[100 * k - 1 + m];\n s[100 * k + m] = a1[100 * k + m] + v2;\n }\n }\n return v11 - __readfsqword(40u);\n}" + }, + { + "index": 721, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int cost[][100], int N) {\n int dp[100][100] = {0};\n dp[0][0] = cost[0][0];\n for (int i = 1; i < N; i++) {\n dp[i][0] = dp[i - 1][0] + cost[i][0];\n }\n for (int j = 1; j < N; j++) {\n dp[0][j] = dp[0][j - 1] + cost[0][j];\n }\n for (int i = 1; i < N; i++) {\n for (int j = 1; j < N; j++) {\n dp[i][j] = (dp[i - 1][j] > dp[i][j - 1] ? dp[i - 1][j] : dp[i][j - 1]) +\n cost[i][j];\n }\n }\n return (double)dp[N - 1][N - 1] / (2 * N - 1);\n}", + "test": "int main() {\n\n int cost1[3][100] = { {1, 2, 3}, {6, 5, 4}, {7, 3, 9} };\n\n assert(func0(cost1, 3) == 5.2);\n\n \n\n int cost2[3][100] = { {2, 3, 4}, {7, 6, 5}, {8, 4, 10} };\n\n assert(func0(cost2, 3) == 6.2);\n\n \n\n int cost3[3][100] = { {3, 4, 5}, {8, 7, 6}, {9, 5, 11} };\n\n assert(func0(cost3, 3) == 7.2);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nlea -0x9000(%rsp),%r11\nsub $0x1000,%rsp\norq $0x0,(%rsp)\ncmp %r11,%rsp\njne 1197 \nsub $0xc58,%rsp\nmov %rdi,%rbp\nmov %esi,%ebx\nmov %fs:0x28,%rax\nmov %rax,0x9c48(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nmov $0x9c40,%edx\nmov $0x0,%esi\ncallq 1090 \nmov 0x0(%rbp),%eax\nmov %eax,(%rsp)\ncmp $0x1,%ebx\njle 12aa \nlea 0x190(%rbp),%rdx\nlea 0x190(%rsp),%rdi\nlea -0x2(%rbx),%r8d\nlea (%r8,%r8,4),%rax\nlea (%rax,%rax,4),%r9\nshl $0x4,%r9\nlea 0x320(%rbp,%r9,1),%rsi\nmov %rdi,%rax\nmov (%rdx),%ecx\nadd -0x190(%rax),%ecx\nmov %ecx,(%rax)\nadd $0x190,%rdx\nadd $0x190,%rax\ncmp %rsi,%rdx\njne 1212 \nlea 0x4(%rbp),%rdx\nlea 0x4(%rsp),%rax\nlea 0x0(,%r8,4),%r10\nlea 0x8(%rbp,%r10,1),%rsi\nmov (%rdx),%ecx\nadd -0x4(%rax),%ecx\nmov %ecx,(%rax)\nadd $0x4,%rdx\nadd $0x4,%rax\ncmp %rsi,%rdx\njne 1244 \nlea 0x198(%rbp,%r10,1),%rsi\nlea 0x320(%rsp,%r9,1),%r9\nnot %r8\nshl $0x2,%r8\njmp 1284 \nadd $0x190,%rdi\nadd $0x190,%rsi\ncmp %r9,%rdi\nje 12aa \nlea (%r8,%rsi,1),%rcx\nmov %rdi,%rdx\nmov -0x18c(%rdx),%eax\ncmp %eax,(%rdx)\ncmovge (%rdx),%eax\nadd (%rcx),%eax\nmov %eax,0x4(%rdx)\nadd $0x4,%rdx\nadd $0x4,%rcx\ncmp %rsi,%rcx\njne 128b \njmp 1271 \nlea -0x1(%rbx),%eax\ncltq\nimul $0x194,%rax,%rax\npxor %xmm0,%xmm0\ncvtsi2sdl (%rsp,%rax,1),%xmm0\nlea -0x1(%rbx,%rbx,1),%eax\npxor %xmm1,%xmm1\ncvtsi2sd %eax,%xmm1\ndivsd %xmm1,%xmm0\nmov 0x9c48(%rsp),%rax\nxor %fs:0x28,%rax\njne 12ec \nadd $0x9c58,%rsp\npop %rbx\npop %rbp\nretq\ncallq 1070 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nlea r11, [rsp+10h+var_9010]\nloc_1197:\nsub rsp, 1000h\nor [rsp+1010h+var_1010], 0\ncmp rsp, r11\njnz short loc_1197\nsub rsp, 0C58h\nmov rbp, rdi\nmov ebx, esi\nmov rax, fs:28h\nmov [rsp+1C68h+arg_7FD8], rax\nxor eax, eax\nmov rdi, rsp; s\nmov edx, 9C40h; n\nmov esi, 0; c\ncall _memset\nmov eax, [rbp+0]\nmov [rsp+1C68h+var_1C68], eax\ncmp ebx, 1\njle loc_12A8\nlea rdx, [rbp+190h]\nlea r8, [rsp+1C68h+var_1AD8]\nlea r9d, [rbx-2]\nlea rax, [r9+r9*4]\nlea r10, [rax+rax*4]\nshl r10, 4\nlea rsi, [rbp+r10+320h]\nmov rax, r8\nloc_1212:\nmov ecx, [rdx]\nadd ecx, [rax-190h]\nmov [rax], ecx\nadd rdx, 190h\nadd rax, 190h\ncmp rdx, rsi\njnz short loc_1212\nlea rdx, [rbp+4]\nlea rax, [rsp+1C68h+var_1C64]\nlea rdi, ds:0[r9*4]\nlea rsi, [rbp+rdi+8]\nloc_1244:\nmov ecx, [rdx]\nadd ecx, [rax-4]\nmov [rax], ecx\nadd rdx, 4\nadd rax, 4\ncmp rdx, rsi\njnz short loc_1244\nlea rdi, [rbp+rdi+198h]\nlea r10, [rsp+r10+1C68h+var_1948]\nnot r9\nshl r9, 2\nloc_126F:\nlea rcx, [r9+rdi]\nmov rdx, r8\nloc_1276:\nmov eax, [rdx]\nmov esi, [rdx-18Ch]\ncmp eax, esi\ncmovl eax, esi\nadd eax, [rcx]\nmov [rdx+4], eax\nadd rdx, 4\nadd rcx, 4\ncmp rcx, rdi\njnz short loc_1276\nadd r8, 190h\nadd rdi, 190h\ncmp r8, r10\njnz short loc_126F\nloc_12A8:\nlea eax, [rbx-1]\ncdqe\nimul rax, 194h\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rsp+rax+1C68h+var_1C68]\nlea eax, [rbx+rbx-1]\npxor xmm1, xmm1\ncvtsi2sd xmm1, eax\ndivsd xmm0, xmm1\nmov rax, [rsp+1C68h+arg_7FD8]\nsub rax, fs:28h\njnz short loc_12EA\nadd rsp, 9C58h\npop rbx\npop rbp\nretn\nloc_12EA:\ncall ___stack_chk_fail", + "ida_pseudo": "// positive sp value has been detected, the output may be wrong!\nunsigned __int64 __fastcall func0(int *a1, int a2)\n{\n int *v2; // rdx\n int *v3; // r8\n __int64 v4; // r9\n _DWORD *v5; // rax\n int *v6; // rdx\n int *v7; // rax\n __int64 v8; // rdi\n int *v9; // r10\n __int64 v10; // r9\n _DWORD *v11; // rcx\n int *v12; // rdx\n int v13; // eax\n int v15; // [rsp-C58h] [rbp-9C68h] BYREF\n int v16; // [rsp-C54h] [rbp-9C64h] BYREF\n _BYTE v17[2760]; // [rsp-AC8h] [rbp-9AD8h] BYREF\n char v18; // [rsp+0h] [rbp-9010h] BYREF\n __int64 v19; // [rsp+1000h] [rbp-8010h] BYREF\n unsigned __int64 v20; // [rsp+8FF0h] [rbp-20h]\n\n while ( &v18 != (char *)(&v19 - 4608) )\n ;\n v20 = __readfsqword(0x28u);\n memset(&v15, 0, 0x9C40uLL);\n v15 = *a1;\n if ( a2 > 1 )\n {\n v2 = a1 + 100;\n v3 = (int *)v17;\n v4 = (unsigned int)(a2 - 2);\n v5 = v17;\n do\n {\n *v5 = *(v5 - 100) + *v2;\n v2 += 100;\n v5 += 100;\n }\n while ( v2 != &a1[100 * v4 + 200] );\n v6 = a1 + 1;\n v7 = &v16;\n do\n {\n *v7 = *(v7 - 1) + *v6++;\n ++v7;\n }\n while ( v6 != &a1[v4 + 2] );\n v8 = (__int64)&a1[v4 + 102];\n v9 = (int *)&v17[400 * v4 + 400];\n v10 = 4 * ~v4;\n do\n {\n v11 = (_DWORD *)(v10 + v8);\n v12 = v3;\n do\n {\n v13 = *v12;\n if ( *v12 < *(v12 - 99) )\n v13 = *(v12 - 99);\n v12[1] = *v11 + v13;\n ++v12;\n ++v11;\n }\n while ( v11 != (_DWORD *)v8 );\n v3 += 100;\n v8 += 400LL;\n }\n while ( v3 != v9 );\n }\n return v20 - __readfsqword(0x28u);\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\npush rbx\nlea r11, [rsp+10h+var_9010]\nloc_1197:\nsub rsp, 1000h\nor [rsp+1010h+var_1010], 0\ncmp rsp, r11\njnz short loc_1197\nsub rsp, 0C58h\nmov rbp, rdi\nmov ebx, esi\nmov rax, fs:28h\nmov [rsp+1C68h+arg_7FD8], rax\nxor eax, eax\nmov rdi, rsp; s\nmov edx, 9C40h; n\nmov esi, 0; c\ncall _memset\nmov eax, [rbp+0]\nmov [rsp+1C68h+var_1C68], eax\ncmp ebx, 1\njle loc_12A8\nlea rdx, [rbp+190h]\nlea r8, [rsp+1C68h+var_1AD8]\nlea r9d, [rbx-2]\nlea rax, [r9+r9*4]\nlea r10, [rax+rax*4]\nshl r10, 4\nlea rsi, [rbp+r10+320h]\nmov rax, r8\nloc_1212:\nmov ecx, [rdx]\nadd ecx, [rax-190h]\nmov [rax], ecx\nadd rdx, 190h\nadd rax, 190h\ncmp rdx, rsi\njnz short loc_1212\nlea rdx, [rbp+4]\nlea rax, [rsp+1C68h+var_1C64]\nlea rdi, ds:0[r9*4]\nlea rsi, [rbp+rdi+8]\nloc_1244:\nmov ecx, [rdx]\nadd ecx, [rax-4]\nmov [rax], ecx\nadd rdx, 4\nadd rax, 4\ncmp rdx, rsi\njnz short loc_1244\nlea rdi, [rbp+rdi+198h]\nlea r10, [rsp+r10+1C68h+var_1948]\nnot r9\nshl r9, 2\nloc_126F:\nlea rcx, [r9+rdi]\nmov rdx, r8\nloc_1276:\nmov eax, [rdx]\nmov esi, [rdx-18Ch]\ncmp eax, esi\ncmovl eax, esi\nadd eax, [rcx]\nmov [rdx+4], eax\nadd rdx, 4\nadd rcx, 4\ncmp rcx, rdi\njnz short loc_1276\nadd r8, 190h\nadd rdi, 190h\ncmp r8, r10\njnz short loc_126F\nloc_12A8:\nlea eax, [rbx-1]\ncdqe\nimul rax, 194h\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rsp+rax+1C68h+var_1C68]\nlea eax, [rbx+rbx-1]\npxor xmm1, xmm1\ncvtsi2sd xmm1, eax\ndivsd xmm0, xmm1\nmov rax, [rsp+1C68h+arg_7FD8]\nsub rax, fs:28h\njnz short loc_12EA\nadd rsp, 9C58h\npop rbx\npop rbp\nretn\nloc_12EA:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "// positive sp value has been detected, the output may be wrong!\nunsigned __int64 __fastcall sub_1189(int *a1, int a2)\n{\n int *v2; // rdx\n int *v3; // r8\n __int64 v4; // r9\n _DWORD *v5; // rax\n int *v6; // rdx\n int *v7; // rax\n __int64 v8; // rdi\n int *v9; // r10\n __int64 v10; // r9\n _DWORD *v11; // rcx\n int *v12; // rdx\n int v13; // eax\n int v15; // [rsp-C58h] [rbp-9C68h] BYREF\n int v16; // [rsp-C54h] [rbp-9C64h] BYREF\n _BYTE v17[2760]; // [rsp-AC8h] [rbp-9AD8h] BYREF\n char v18; // [rsp+0h] [rbp-9010h] BYREF\n __int64 v19; // [rsp+1000h] [rbp-8010h] BYREF\n unsigned __int64 v20; // [rsp+8FF0h] [rbp-20h]\n\n while ( &v18 != (char *)(&v19 - 4608) )\n ;\n v20 = __readfsqword(0x28u);\n memset(&v15, 0, 0x9C40uLL);\n v15 = *a1;\n if ( a2 > 1 )\n {\n v2 = a1 + 100;\n v3 = (int *)v17;\n v4 = (unsigned int)(a2 - 2);\n v5 = v17;\n do\n {\n *v5 = *(v5 - 100) + *v2;\n v2 += 100;\n v5 += 100;\n }\n while ( v2 != &a1[100 * v4 + 200] );\n v6 = a1 + 1;\n v7 = &v16;\n do\n {\n *v7 = *(v7 - 1) + *v6++;\n ++v7;\n }\n while ( v6 != &a1[v4 + 2] );\n v8 = (__int64)&a1[v4 + 102];\n v9 = (int *)&v17[400 * v4 + 400];\n v10 = 4 * ~v4;\n do\n {\n v11 = (_DWORD *)(v10 + v8);\n v12 = v3;\n do\n {\n v13 = *v12;\n if ( *v12 < *(v12 - 99) )\n v13 = *(v12 - 99);\n v12[1] = *v11 + v13;\n ++v12;\n ++v11;\n }\n while ( v11 != (_DWORD *)v8 );\n v3 += 100;\n v8 += 400LL;\n }\n while ( v3 != v9 );\n }\n return v20 - __readfsqword(0x28u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_1189(int *a1, int a2) {\n int *v2;\n int *v3;\n long long v4;\n uint32_t *v5;\n int *v6;\n int *v7;\n long long v8;\n int *v9;\n long long v10;\n uint32_t *v11;\n int *v12;\n int v13;\n int v15;\n int v16;\n uint8_t v17[2760];\n char v18;\n long long v19;\n unsigned long long v20;\n while (&v18 != (char *)(&v19 - 4608))\n ;\n v20 = __readfsqword(40u);\n memset(&v15, 0, 40000uLL);\n v15 = *a1;\n if (a2 > 1) {\n v2 = a1 + 100;\n v3 = (int *)v17;\n v4 = (unsigned int)(a2 - 2);\n v5 = v17;\n do {\n *v5 = *(v5 - 100) + *v2;\n v2 += 100;\n v5 += 100;\n } while (v2 != &a1[100 * v4 + 200]);\n v6 = a1 + 1;\n v7 = &v16;\n do {\n *v7 = *(v7 - 1) + *v6++;\n ++v7;\n } while (v6 != &a1[v4 + 2]);\n v8 = (long long)&a1[v4 + 102];\n v9 = (int *)&v17[400 * v4 + 400];\n v10 = 4 * ~v4;\n do {\n v11 = (uint32_t *)(v10 + v8);\n v12 = v3;\n do {\n v13 = *v12;\n if (*v12 < *(v12 - 99)) v13 = *(v12 - 99);\n v12[1] = *v11 + v13;\n ++v12;\n ++v11;\n } while (v11 != (uint32_t *)v8);\n v3 += 100;\n v8 += 400LL;\n } while (v3 != v9);\n }\n return v20 - __readfsqword(40u);\n}", + "ida_pseudo_norm": "unsigned long long func0(int *a1, int a2) {\n int *v2;\n int *v3;\n long long v4;\n uint32_t *v5;\n int *v6;\n int *v7;\n long long v8;\n int *v9;\n long long v10;\n uint32_t *v11;\n int *v12;\n int v13;\n int v15;\n int v16;\n uint8_t v17[2760];\n char v18;\n long long v19;\n unsigned long long v20;\n while (&v18 != (char *)(&v19 - 4608))\n ;\n v20 = __readfsqword(40u);\n memset(&v15, 0, 40000uLL);\n v15 = *a1;\n if (a2 > 1) {\n v2 = a1 + 100;\n v3 = (int *)v17;\n v4 = (unsigned int)(a2 - 2);\n v5 = v17;\n do {\n *v5 = *(v5 - 100) + *v2;\n v2 += 100;\n v5 += 100;\n } while (v2 != &a1[100 * v4 + 200]);\n v6 = a1 + 1;\n v7 = &v16;\n do {\n *v7 = *(v7 - 1) + *v6++;\n ++v7;\n } while (v6 != &a1[v4 + 2]);\n v8 = (long long)&a1[v4 + 102];\n v9 = (int *)&v17[400 * v4 + 400];\n v10 = 4 * ~v4;\n do {\n v11 = (uint32_t *)(v10 + v8);\n v12 = v3;\n do {\n v13 = *v12;\n if (*v12 < *(v12 - 99)) v13 = *(v12 - 99);\n v12[1] = *v11 + v13;\n ++v12;\n ++v11;\n } while (v11 != (uint32_t *)v8);\n v3 += 100;\n v8 += 400LL;\n } while (v3 != v9);\n }\n return v20 - __readfsqword(40u);\n}" + }, + { + "index": 721, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int cost[][100], int N) {\n int dp[100][100] = {0};\n dp[0][0] = cost[0][0];\n for (int i = 1; i < N; i++) {\n dp[i][0] = dp[i - 1][0] + cost[i][0];\n }\n for (int j = 1; j < N; j++) {\n dp[0][j] = dp[0][j - 1] + cost[0][j];\n }\n for (int i = 1; i < N; i++) {\n for (int j = 1; j < N; j++) {\n dp[i][j] = (dp[i - 1][j] > dp[i][j - 1] ? dp[i - 1][j] : dp[i][j - 1]) +\n cost[i][j];\n }\n }\n return (double)dp[N - 1][N - 1] / (2 * N - 1);\n}", + "test": "int main() {\n\n int cost1[3][100] = { {1, 2, 3}, {6, 5, 4}, {7, 3, 9} };\n\n assert(func0(cost1, 3) == 5.2);\n\n \n\n int cost2[3][100] = { {2, 3, 4}, {7, 6, 5}, {8, 4, 10} };\n\n assert(func0(cost2, 3) == 6.2);\n\n \n\n int cost3[3][100] = { {3, 4, 5}, {8, 7, 6}, {9, 5, 11} };\n\n assert(func0(cost3, 3) == 7.2);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nlea -0x9000(%rsp),%r11\nsub $0x1000,%rsp\norq $0x0,(%rsp)\ncmp %r11,%rsp\njne 13de \nsub $0xc58,%rsp\nmov $0x9c40,%edx\nmov %fs:0x28,%rax\nmov %rax,0x9c48(%rsp)\nxor %eax,%eax\nmov %rdi,%rbp\nmov %esi,%ebx\nmov %rsp,%rdi\nxor %esi,%esi\ncallq 1090 \nmov 0x0(%rbp),%edx\nmov %edx,(%rsp)\ncmp $0x1,%ebx\njle 151b \nlea -0x2(%rbx),%edi\nlea 0x190(%rbp),%rax\nlea (%rdi,%rdi,4),%rcx\nlea 0x190(%rsp),%rsi\nlea (%rcx,%rcx,4),%rcx\nshl $0x4,%rcx\nlea 0x320(%rbp,%rcx,1),%r8\nmov %edx,%ecx\njmp 1467 \nnopw %cs:0x0(%rax,%rax,1)\nadd $0x190,%rsi\nadd (%rax),%ecx\nadd $0x190,%rax\nmov %ecx,(%rsi)\ncmp %r8,%rax\njne 1460 \nlea 0x4(%rbp),%r10\nlea 0x4(%rsp),%r11\nlea 0x0(,%rdi,4),%r8\nmov %r10,%rax\nmov %r11,%rcx\nlea 0x8(%rbp,%r8,1),%rsi\njmp 149c \nnopl 0x0(%rax)\nadd $0x4,%rcx\nadd (%rax),%edx\nadd $0x4,%rax\nmov %edx,(%rcx)\ncmp %rsi,%rax\njne 1498 \nimul $0xfffffffffffffe70,%rdi,%rdi\nlea 0x198(%rbp,%r8,1),%r9\nmov $0xfffffffffffffe70,%r8\nlea -0x320(%rdi),%rbp\nxor %edi,%edi\nnopl 0x0(%rax,%rax,1)\nmov %r10,%rcx\nmov %r11,%rdx\nsub %r8,%rcx\nsub %r8,%rdx\nnopl 0x0(%rax)\nlea (%r8,%rdx,1),%rsi\nmov -0x4(%rdx),%eax\ncmp %eax,(%rsi,%rdi,1)\ncmovge (%rsi,%rdi,1),%eax\nadd $0x4,%rcx\nadd $0x4,%rdx\nadd -0x4(%rcx),%eax\nmov %eax,-0x4(%rdx)\ncmp %r9,%rcx\njne 14e0 \nsub $0x190,%r8\nadd $0x190,%rdi\nadd $0x190,%r9\ncmp %rbp,%r8\njne 14d0 \nlea -0x1(%rbx),%eax\npxor %xmm0,%xmm0\npxor %xmm1,%xmm1\ncltq\nimul $0x194,%rax,%rax\ncvtsi2sdl (%rsp,%rax,1),%xmm0\nlea -0x1(%rbx,%rbx,1),%eax\ncvtsi2sd %eax,%xmm1\nmov 0x9c48(%rsp),%rax\nxor %fs:0x28,%rax\ndivsd %xmm1,%xmm0\njne 155d \nadd $0x9c58,%rsp\npop %rbx\npop %rbp\nretq\ncallq 1070 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nlea r11, [rsp+10h+var_9010]\nloc_13BE:\nsub rsp, 1000h\nor [rsp+1010h+var_1010], 0\ncmp rsp, r11\njnz short loc_13BE\nsub rsp, 0C58h\nmov edx, 9C40h; n\nmov rax, fs:28h\nmov [rsp+1C68h+arg_7FD8], rax\nxor eax, eax\nmov rbx, rdi\nmov ebp, esi\nmov rdi, rsp; s\nxor esi, esi; c\ncall _memset\nmov edx, [rbx]\nmov [rsp+1C68h+var_1C68], edx\ncmp ebp, 1\njle loc_14C2\nmov rdi, rax\nlea eax, [rbp-2]\nlea rax, [rax+rax*4]\nlea r10, [rax+rax*4]\nmov eax, 190h\nshl r10, 4\nlea rcx, [r10+320h]\nnop dword ptr [rax+00000000h]\nloc_1430:\nadd edx, [rbx+rax]\nmov [rdi+rax], edx\nadd rax, 190h\ncmp rax, rcx\njnz short loc_1430\nmov edx, [rsp+1C68h+var_1C68]\nmov r9d, ebp\nmov eax, 1\nnop dword ptr [rax+00h]\nloc_1450:\nadd edx, [rbx+rax*4]\nmov [rdi+rax*4], edx\nadd rax, 1\ncmp rax, r9\njnz short loc_1450\nlea r8, [rsp+1C68h+var_1AD8]\nlea rsi, [rbx+190h]\nlea r10, [rsp+r10+1C68h+var_1948]\nnop word ptr [rax+rax+00000000h]\nloc_1480:\nmov edx, [r8]\nmov eax, 1\nnop dword ptr [rax+rax+00000000h]\nloc_1490:\nmov ecx, [rdi+rax*4]\ncmp edx, ecx\ncmovl edx, ecx\nadd edx, [rsi+rax*4]\nmov [r8+rax*4], edx\nadd rax, 1\ncmp rax, r9\njnz short loc_1490\nadd r8, 190h\nadd rdi, 190h\nadd rsi, 190h\ncmp r10, r8\njnz short loc_1480\nloc_14C2:\nlea eax, [rbp-1]\npxor xmm0, xmm0\npxor xmm1, xmm1\ncdqe\nimul rax, 194h\ncvtsi2sd xmm0, [rsp+rax+1C68h+var_1C68]\nlea eax, [rbp+rbp-1]\ncvtsi2sd xmm1, eax\ndivsd xmm0, xmm1\nmov rax, [rsp+1C68h+arg_7FD8]\nsub rax, fs:28h\njnz short loc_1504\nadd rsp, 9C58h\npop rbx\npop rbp\nretn\nloc_1504:\ncall ___stack_chk_fail", + "ida_pseudo": "// positive sp value has been detected, the output may be wrong!\nunsigned __int64 __fastcall func0(int *a1, int a2)\n{\n _DWORD *v4; // rax\n int v5; // edx\n _DWORD *v6; // rdi\n __int64 v7; // rax\n __int64 v8; // r10\n int v9; // edx\n __int64 i; // rax\n int *v11; // r8\n _DWORD *v12; // rsi\n int *v13; // r10\n int v14; // edx\n __int64 v15; // rax\n int v17; // [rsp-C58h] [rbp-9C68h] BYREF\n _BYTE v18[2760]; // [rsp-AC8h] [rbp-9AD8h] BYREF\n char v19; // [rsp+0h] [rbp-9010h] BYREF\n __int64 v20; // [rsp+1000h] [rbp-8010h] BYREF\n unsigned __int64 v21; // [rsp+8FF0h] [rbp-20h]\n\n while ( &v19 != (char *)(&v20 - 4608) )\n ;\n v21 = __readfsqword(0x28u);\n v4 = memset(&v17, 0, 0x9C40uLL);\n v5 = *a1;\n v17 = *a1;\n if ( a2 > 1 )\n {\n v6 = v4;\n v7 = 400LL;\n v8 = 400LL * (unsigned int)(a2 - 2);\n do\n {\n v5 += a1[(unsigned __int64)v7 / 4];\n v6[(unsigned __int64)v7 / 4] = v5;\n v7 += 400LL;\n }\n while ( v7 != v8 + 800 );\n v9 = v17;\n for ( i = 1LL; i != a2; v6[i++] = v9 )\n v9 += a1[i];\n v11 = (int *)v18;\n v12 = a1 + 100;\n v13 = (int *)&v18[v8 + 400];\n do\n {\n v14 = *v11;\n v15 = 1LL;\n do\n {\n if ( v14 < v6[v15] )\n v14 = v6[v15];\n v14 += v12[v15];\n v11[v15++] = v14;\n }\n while ( v15 != a2 );\n v11 += 100;\n v6 += 100;\n v12 += 100;\n }\n while ( v13 != v11 );\n }\n return v21 - __readfsqword(0x28u);\n}", + "ida_strip_asm": "sub_13B0:\nendbr64\npush rbp\npush rbx\nlea r11, [rsp+10h+var_9010]\nloc_13BE:\nsub rsp, 1000h\nor [rsp+1010h+var_1010], 0\ncmp rsp, r11\njnz short loc_13BE\nsub rsp, 0C58h\nmov edx, 9C40h; n\nmov rax, fs:28h\nmov [rsp+1C68h+arg_7FD8], rax\nxor eax, eax\nmov rbx, rdi\nmov ebp, esi\nmov rdi, rsp; s\nxor esi, esi; c\ncall _memset\nmov edx, [rbx]\nmov [rsp+1C68h+var_1C68], edx\ncmp ebp, 1\njle loc_14C2\nmov rdi, rax\nlea eax, [rbp-2]\nlea rax, [rax+rax*4]\nlea r10, [rax+rax*4]\nmov eax, 190h\nshl r10, 4\nlea rcx, [r10+320h]\nnop dword ptr [rax+00000000h]\nloc_1430:\nadd edx, [rbx+rax]\nmov [rdi+rax], edx\nadd rax, 190h\ncmp rax, rcx\njnz short loc_1430\nmov edx, [rsp+1C68h+var_1C68]\nmov r9d, ebp\nmov eax, 1\nnop dword ptr [rax+00h]\nloc_1450:\nadd edx, [rbx+rax*4]\nmov [rdi+rax*4], edx\nadd rax, 1\ncmp rax, r9\njnz short loc_1450\nlea r8, [rsp+1C68h+var_1AD8]\nlea rsi, [rbx+190h]\nlea r10, [rsp+r10+1C68h+var_1948]\nnop word ptr [rax+rax+00000000h]\nloc_1480:\nmov edx, [r8]\nmov eax, 1\nnop dword ptr [rax+rax+00000000h]\nloc_1490:\nmov ecx, [rdi+rax*4]\ncmp edx, ecx\ncmovl edx, ecx\nadd edx, [rsi+rax*4]\nmov [r8+rax*4], edx\nadd rax, 1\ncmp rax, r9\njnz short loc_1490\nadd r8, 190h\nadd rdi, 190h\nadd rsi, 190h\ncmp r10, r8\njnz short loc_1480\nloc_14C2:\nlea eax, [rbp-1]\npxor xmm0, xmm0\npxor xmm1, xmm1\ncdqe\nimul rax, 194h\ncvtsi2sd xmm0, [rsp+rax+1C68h+var_1C68]\nlea eax, [rbp+rbp-1]\ncvtsi2sd xmm1, eax\ndivsd xmm0, xmm1\nmov rax, [rsp+1C68h+arg_7FD8]\nsub rax, fs:28h\njnz short loc_1504\nadd rsp, 9C58h\npop rbx\npop rbp\nretn\nloc_1504:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "// positive sp value has been detected, the output may be wrong!\nunsigned __int64 __fastcall sub_13B0(int *a1, int a2)\n{\n _DWORD *v4; // rax\n int v5; // edx\n _DWORD *v6; // rdi\n __int64 v7; // rax\n __int64 v8; // r10\n int v9; // edx\n __int64 i; // rax\n int *v11; // r8\n _DWORD *v12; // rsi\n int *v13; // r10\n int v14; // edx\n __int64 v15; // rax\n int v17; // [rsp-C58h] [rbp-9C68h] BYREF\n _BYTE v18[2760]; // [rsp-AC8h] [rbp-9AD8h] BYREF\n char v19; // [rsp+0h] [rbp-9010h] BYREF\n __int64 v20; // [rsp+1000h] [rbp-8010h] BYREF\n unsigned __int64 v21; // [rsp+8FF0h] [rbp-20h]\n\n while ( &v19 != (char *)(&v20 - 4608) )\n ;\n v21 = __readfsqword(0x28u);\n v4 = memset(&v17, 0, 0x9C40uLL);\n v5 = *a1;\n v17 = *a1;\n if ( a2 > 1 )\n {\n v6 = v4;\n v7 = 400LL;\n v8 = 400LL * (unsigned int)(a2 - 2);\n do\n {\n v5 += a1[(unsigned __int64)v7 / 4];\n v6[(unsigned __int64)v7 / 4] = v5;\n v7 += 400LL;\n }\n while ( v7 != v8 + 800 );\n v9 = v17;\n for ( i = 1LL; i != a2; v6[i++] = v9 )\n v9 += a1[i];\n v11 = (int *)v18;\n v12 = a1 + 100;\n v13 = (int *)&v18[v8 + 400];\n do\n {\n v14 = *v11;\n v15 = 1LL;\n do\n {\n if ( v14 < v6[v15] )\n v14 = v6[v15];\n v14 += v12[v15];\n v11[v15++] = v14;\n }\n while ( v15 != a2 );\n v11 += 100;\n v6 += 100;\n v12 += 100;\n }\n while ( v13 != v11 );\n }\n return v21 - __readfsqword(0x28u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_13B0(int *a1, int a2) {\n uint32_t *v4;\n int v5;\n uint32_t *v6;\n long long v7;\n long long v8;\n int v9;\n long long i;\n int *v11;\n uint32_t *v12;\n int *v13;\n int v14;\n long long v15;\n int v17;\n uint8_t v18[2760];\n char v19;\n long long v20;\n unsigned long long v21;\n while (&v19 != (char *)(&v20 - 4608))\n ;\n v21 = __readfsqword(40u);\n v4 = memset(&v17, 0, 40000uLL);\n v5 = *a1;\n v17 = *a1;\n if (a2 > 1) {\n v6 = v4;\n v7 = 400LL;\n v8 = 400LL * (unsigned int)(a2 - 2);\n do {\n v5 += a1[(unsigned long long)v7 / 4];\n v6[(unsigned long long)v7 / 4] = v5;\n v7 += 400LL;\n } while (v7 != v8 + 800);\n v9 = v17;\n for (i = 1LL; i != a2; v6[i++] = v9) v9 += a1[i];\n v11 = (int *)v18;\n v12 = a1 + 100;\n v13 = (int *)&v18[v8 + 400];\n do {\n v14 = *v11;\n v15 = 1LL;\n do {\n if (v14 < v6[v15]) v14 = v6[v15];\n v14 += v12[v15];\n v11[v15++] = v14;\n } while (v15 != a2);\n v11 += 100;\n v6 += 100;\n v12 += 100;\n } while (v13 != v11);\n }\n return v21 - __readfsqword(40u);\n}", + "ida_pseudo_norm": "unsigned long long func0(int *a1, int a2) {\n uint32_t *v4;\n int v5;\n uint32_t *v6;\n long long v7;\n long long v8;\n int v9;\n long long i;\n int *v11;\n uint32_t *v12;\n int *v13;\n int v14;\n long long v15;\n int v17;\n uint8_t v18[2760];\n char v19;\n long long v20;\n unsigned long long v21;\n while (&v19 != (char *)(&v20 - 4608))\n ;\n v21 = __readfsqword(40u);\n v4 = memset(&v17, 0, 40000uLL);\n v5 = *a1;\n v17 = *a1;\n if (a2 > 1) {\n v6 = v4;\n v7 = 400LL;\n v8 = 400LL * (unsigned int)(a2 - 2);\n do {\n v5 += a1[(unsigned long long)v7 / 4];\n v6[(unsigned long long)v7 / 4] = v5;\n v7 += 400LL;\n } while (v7 != v8 + 800);\n v9 = v17;\n for (i = 1LL; i != a2; v6[i++] = v9) v9 += a1[i];\n v11 = (int *)v18;\n v12 = a1 + 100;\n v13 = (int *)&v18[v8 + 400];\n do {\n v14 = *v11;\n v15 = 1LL;\n do {\n if (v14 < v6[v15]) v14 = v6[v15];\n v14 += v12[v15];\n v11[v15++] = v14;\n } while (v15 != a2);\n v11 += 100;\n v6 += 100;\n v12 += 100;\n } while (v13 != v11);\n }\n return v21 - __readfsqword(40u);\n}" + }, + { + "index": 721, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int cost[][100], int N) {\n int dp[100][100] = {0};\n dp[0][0] = cost[0][0];\n for (int i = 1; i < N; i++) {\n dp[i][0] = dp[i - 1][0] + cost[i][0];\n }\n for (int j = 1; j < N; j++) {\n dp[0][j] = dp[0][j - 1] + cost[0][j];\n }\n for (int i = 1; i < N; i++) {\n for (int j = 1; j < N; j++) {\n dp[i][j] = (dp[i - 1][j] > dp[i][j - 1] ? dp[i - 1][j] : dp[i][j - 1]) +\n cost[i][j];\n }\n }\n return (double)dp[N - 1][N - 1] / (2 * N - 1);\n}", + "test": "int main() {\n\n int cost1[3][100] = { {1, 2, 3}, {6, 5, 4}, {7, 3, 9} };\n\n assert(func0(cost1, 3) == 5.2);\n\n \n\n int cost2[3][100] = { {2, 3, 4}, {7, 6, 5}, {8, 4, 10} };\n\n assert(func0(cost2, 3) == 6.2);\n\n \n\n int cost3[3][100] = { {3, 4, 5}, {8, 7, 6}, {9, 5, 11} };\n\n assert(func0(cost3, 3) == 7.2);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nlea -0x9000(%rsp),%r11\nsub $0x1000,%rsp\norq $0x0,(%rsp)\ncmp %r11,%rsp\njne 13de \nsub $0xc58,%rsp\nmov $0x9c40,%edx\nmov %fs:0x28,%rax\nmov %rax,0x9c48(%rsp)\nxor %eax,%eax\nmov %rsp,%rcx\nmov %rdi,%rbx\nmov %esi,%ebp\nmov %rcx,%rdi\nxor %esi,%esi\ncallq 1090 \nmov (%rbx),%edx\nmov %edx,(%rsp)\ncmp $0x1,%ebp\njle 14e0 \nlea -0x2(%rbp),%r8d\nmov %rax,%rcx\nlea (%r8,%r8,4),%rax\nlea (%rax,%rax,4),%r9\nmov $0x190,%eax\nshl $0x4,%r9\nlea 0x320(%r9),%rsi\nnopl (%rax)\nadd (%rbx,%rax,1),%edx\nmov %edx,(%rcx,%rax,1)\nadd $0x190,%rax\ncmp %rax,%rsi\njne 1450 \nmov (%rsp),%edx\nadd $0x2,%r8\nmov $0x1,%eax\nnopl (%rax)\nadd (%rbx,%rax,4),%edx\nmov %edx,(%rcx,%rax,4)\nadd $0x1,%rax\ncmp %rax,%r8\njne 1470 \nlea 0x190(%rsp),%rdi\nlea 0x190(%rbx),%rsi\nlea 0x320(%rsp,%r9,1),%r9\nnopw %cs:0x0(%rax,%rax,1)\nmov (%rdi),%edx\nmov $0x1,%eax\nnopw 0x0(%rax,%rax,1)\ncmp %edx,(%rcx,%rax,4)\ncmovge (%rcx,%rax,4),%edx\nadd (%rsi,%rax,4),%edx\nmov %edx,(%rdi,%rax,4)\nadd $0x1,%rax\ncmp %r8,%rax\njne 14b0 \nadd $0x190,%rdi\nadd $0x190,%rcx\nadd $0x190,%rsi\ncmp %r9,%rdi\njne 14a0 \nlea -0x1(%rbp),%eax\npxor %xmm0,%xmm0\npxor %xmm1,%xmm1\ncltq\nimul $0x194,%rax,%rax\ncvtsi2sdl (%rsp,%rax,1),%xmm0\nlea -0x1(%rbp,%rbp,1),%eax\ncvtsi2sd %eax,%xmm1\nmov 0x9c48(%rsp),%rax\nxor %fs:0x28,%rax\ndivsd %xmm1,%xmm0\njne 1522 \nadd $0x9c58,%rsp\npop %rbx\npop %rbp\nretq\ncallq 1070 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nlea r11, [rsp+10h+var_9010]\nloc_13BE:\nsub rsp, 1000h\nor [rsp+1010h+var_1010], 0\ncmp rsp, r11\njnz short loc_13BE\nsub rsp, 0C58h\nmov edx, 9C40h; n\nmov rax, fs:28h\nmov [rsp+1C68h+arg_7FD8], rax\nxor eax, eax\nmov rbx, rdi\nmov ebp, esi\nmov rdi, rsp; s\nxor esi, esi; c\ncall _memset\nmov edx, [rbx]\nmov [rsp+1C68h+var_1C68], edx\ncmp ebp, 1\njle loc_14C2\nmov rdi, rax\nlea eax, [rbp-2]\nlea rax, [rax+rax*4]\nlea r10, [rax+rax*4]\nmov eax, 190h\nshl r10, 4\nlea rcx, [r10+320h]\nnop dword ptr [rax+00000000h]\nloc_1430:\nadd edx, [rbx+rax]\nmov [rdi+rax], edx\nadd rax, 190h\ncmp rax, rcx\njnz short loc_1430\nmov edx, [rsp+1C68h+var_1C68]\nmov r9d, ebp\nmov eax, 1\nnop dword ptr [rax+00h]\nloc_1450:\nadd edx, [rbx+rax*4]\nmov [rdi+rax*4], edx\nadd rax, 1\ncmp r9, rax\njnz short loc_1450\nlea r8, [rsp+1C68h+var_1AD8]\nlea rsi, [rbx+190h]\nlea r10, [rsp+r10+1C68h+var_1948]\nnop word ptr [rax+rax+00000000h]\nloc_1480:\nmov edx, [r8]\nmov eax, 1\nnop dword ptr [rax+rax+00000000h]\nloc_1490:\nmov ecx, [rdi+rax*4]\ncmp edx, ecx\ncmovl edx, ecx\nadd edx, [rsi+rax*4]\nmov [r8+rax*4], edx\nadd rax, 1\ncmp r9, rax\njnz short loc_1490\nadd r8, 190h\nadd rdi, 190h\nadd rsi, 190h\ncmp r8, r10\njnz short loc_1480\nloc_14C2:\nlea eax, [rbp-1]\npxor xmm0, xmm0\npxor xmm1, xmm1\ncdqe\nimul rax, 194h\ncvtsi2sd xmm0, [rsp+rax+1C68h+var_1C68]\nlea eax, [rbp+rbp-1]\ncvtsi2sd xmm1, eax\ndivsd xmm0, xmm1\nmov rax, [rsp+1C68h+arg_7FD8]\nsub rax, fs:28h\njnz short loc_1504\nadd rsp, 9C58h\npop rbx\npop rbp\nretn\nloc_1504:\ncall ___stack_chk_fail", + "ida_pseudo": "// positive sp value has been detected, the output may be wrong!\nunsigned __int64 __fastcall func0(int *a1, int a2)\n{\n _DWORD *v4; // rax\n int v5; // edx\n _DWORD *v6; // rdi\n __int64 v7; // rax\n __int64 v8; // r10\n int v9; // edx\n __int64 i; // rax\n int *v11; // r8\n _DWORD *v12; // rsi\n int *v13; // r10\n int v14; // edx\n __int64 v15; // rax\n int v17; // [rsp-C58h] [rbp-9C68h] BYREF\n _BYTE v18[2760]; // [rsp-AC8h] [rbp-9AD8h] BYREF\n char v19; // [rsp+0h] [rbp-9010h] BYREF\n __int64 v20; // [rsp+1000h] [rbp-8010h] BYREF\n unsigned __int64 v21; // [rsp+8FF0h] [rbp-20h]\n\n while ( &v19 != (char *)(&v20 - 4608) )\n ;\n v21 = __readfsqword(0x28u);\n v4 = memset(&v17, 0, 0x9C40uLL);\n v5 = *a1;\n v17 = *a1;\n if ( a2 > 1 )\n {\n v6 = v4;\n v7 = 400LL;\n v8 = 400LL * (unsigned int)(a2 - 2);\n do\n {\n v5 += a1[(unsigned __int64)v7 / 4];\n v6[(unsigned __int64)v7 / 4] = v5;\n v7 += 400LL;\n }\n while ( v7 != v8 + 800 );\n v9 = v17;\n for ( i = 1LL; i != a2; v6[i++] = v9 )\n v9 += a1[i];\n v11 = (int *)v18;\n v12 = a1 + 100;\n v13 = (int *)&v18[v8 + 400];\n do\n {\n v14 = *v11;\n v15 = 1LL;\n do\n {\n if ( v14 < v6[v15] )\n v14 = v6[v15];\n v14 += v12[v15];\n v11[v15++] = v14;\n }\n while ( a2 != v15 );\n v11 += 100;\n v6 += 100;\n v12 += 100;\n }\n while ( v11 != v13 );\n }\n return v21 - __readfsqword(0x28u);\n}", + "ida_strip_asm": "sub_13B0:\nendbr64\npush rbp\npush rbx\nlea r11, [rsp+10h+var_9010]\nloc_13BE:\nsub rsp, 1000h\nor [rsp+1010h+var_1010], 0\ncmp rsp, r11\njnz short loc_13BE\nsub rsp, 0C58h\nmov edx, 9C40h; n\nmov rax, fs:28h\nmov [rsp+1C68h+arg_7FD8], rax\nxor eax, eax\nmov rbx, rdi\nmov ebp, esi\nmov rdi, rsp; s\nxor esi, esi; c\ncall _memset\nmov edx, [rbx]\nmov [rsp+1C68h+var_1C68], edx\ncmp ebp, 1\njle loc_14C2\nmov rdi, rax\nlea eax, [rbp-2]\nlea rax, [rax+rax*4]\nlea r10, [rax+rax*4]\nmov eax, 190h\nshl r10, 4\nlea rcx, [r10+320h]\nnop dword ptr [rax+00000000h]\nloc_1430:\nadd edx, [rbx+rax]\nmov [rdi+rax], edx\nadd rax, 190h\ncmp rax, rcx\njnz short loc_1430\nmov edx, [rsp+1C68h+var_1C68]\nmov r9d, ebp\nmov eax, 1\nnop dword ptr [rax+00h]\nloc_1450:\nadd edx, [rbx+rax*4]\nmov [rdi+rax*4], edx\nadd rax, 1\ncmp r9, rax\njnz short loc_1450\nlea r8, [rsp+1C68h+var_1AD8]\nlea rsi, [rbx+190h]\nlea r10, [rsp+r10+1C68h+var_1948]\nnop word ptr [rax+rax+00000000h]\nloc_1480:\nmov edx, [r8]\nmov eax, 1\nnop dword ptr [rax+rax+00000000h]\nloc_1490:\nmov ecx, [rdi+rax*4]\ncmp edx, ecx\ncmovl edx, ecx\nadd edx, [rsi+rax*4]\nmov [r8+rax*4], edx\nadd rax, 1\ncmp r9, rax\njnz short loc_1490\nadd r8, 190h\nadd rdi, 190h\nadd rsi, 190h\ncmp r8, r10\njnz short loc_1480\nloc_14C2:\nlea eax, [rbp-1]\npxor xmm0, xmm0\npxor xmm1, xmm1\ncdqe\nimul rax, 194h\ncvtsi2sd xmm0, [rsp+rax+1C68h+var_1C68]\nlea eax, [rbp+rbp-1]\ncvtsi2sd xmm1, eax\ndivsd xmm0, xmm1\nmov rax, [rsp+1C68h+arg_7FD8]\nsub rax, fs:28h\njnz short loc_1504\nadd rsp, 9C58h\npop rbx\npop rbp\nretn\nloc_1504:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "// positive sp value has been detected, the output may be wrong!\nunsigned __int64 __fastcall sub_13B0(int *a1, int a2)\n{\n _DWORD *v4; // rax\n int v5; // edx\n _DWORD *v6; // rdi\n __int64 v7; // rax\n __int64 v8; // r10\n int v9; // edx\n __int64 i; // rax\n int *v11; // r8\n _DWORD *v12; // rsi\n int *v13; // r10\n int v14; // edx\n __int64 v15; // rax\n int v17; // [rsp-C58h] [rbp-9C68h] BYREF\n _BYTE v18[2760]; // [rsp-AC8h] [rbp-9AD8h] BYREF\n char v19; // [rsp+0h] [rbp-9010h] BYREF\n __int64 v20; // [rsp+1000h] [rbp-8010h] BYREF\n unsigned __int64 v21; // [rsp+8FF0h] [rbp-20h]\n\n while ( &v19 != (char *)(&v20 - 4608) )\n ;\n v21 = __readfsqword(0x28u);\n v4 = memset(&v17, 0, 0x9C40uLL);\n v5 = *a1;\n v17 = *a1;\n if ( a2 > 1 )\n {\n v6 = v4;\n v7 = 400LL;\n v8 = 400LL * (unsigned int)(a2 - 2);\n do\n {\n v5 += a1[(unsigned __int64)v7 / 4];\n v6[(unsigned __int64)v7 / 4] = v5;\n v7 += 400LL;\n }\n while ( v7 != v8 + 800 );\n v9 = v17;\n for ( i = 1LL; i != a2; v6[i++] = v9 )\n v9 += a1[i];\n v11 = (int *)v18;\n v12 = a1 + 100;\n v13 = (int *)&v18[v8 + 400];\n do\n {\n v14 = *v11;\n v15 = 1LL;\n do\n {\n if ( v14 < v6[v15] )\n v14 = v6[v15];\n v14 += v12[v15];\n v11[v15++] = v14;\n }\n while ( a2 != v15 );\n v11 += 100;\n v6 += 100;\n v12 += 100;\n }\n while ( v11 != v13 );\n }\n return v21 - __readfsqword(0x28u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_13B0(int *a1, int a2) {\n uint32_t *v4;\n int v5;\n uint32_t *v6;\n long long v7;\n long long v8;\n int v9;\n long long i;\n int *v11;\n uint32_t *v12;\n int *v13;\n int v14;\n long long v15;\n int v17;\n uint8_t v18[2760];\n char v19;\n long long v20;\n unsigned long long v21;\n while (&v19 != (char *)(&v20 - 4608))\n ;\n v21 = __readfsqword(40u);\n v4 = memset(&v17, 0, 40000uLL);\n v5 = *a1;\n v17 = *a1;\n if (a2 > 1) {\n v6 = v4;\n v7 = 400LL;\n v8 = 400LL * (unsigned int)(a2 - 2);\n do {\n v5 += a1[(unsigned long long)v7 / 4];\n v6[(unsigned long long)v7 / 4] = v5;\n v7 += 400LL;\n } while (v7 != v8 + 800);\n v9 = v17;\n for (i = 1LL; i != a2; v6[i++] = v9) v9 += a1[i];\n v11 = (int *)v18;\n v12 = a1 + 100;\n v13 = (int *)&v18[v8 + 400];\n do {\n v14 = *v11;\n v15 = 1LL;\n do {\n if (v14 < v6[v15]) v14 = v6[v15];\n v14 += v12[v15];\n v11[v15++] = v14;\n } while (a2 != v15);\n v11 += 100;\n v6 += 100;\n v12 += 100;\n } while (v11 != v13);\n }\n return v21 - __readfsqword(40u);\n}", + "ida_pseudo_norm": "unsigned long long func0(int *a1, int a2) {\n uint32_t *v4;\n int v5;\n uint32_t *v6;\n long long v7;\n long long v8;\n int v9;\n long long i;\n int *v11;\n uint32_t *v12;\n int *v13;\n int v14;\n long long v15;\n int v17;\n uint8_t v18[2760];\n char v19;\n long long v20;\n unsigned long long v21;\n while (&v19 != (char *)(&v20 - 4608))\n ;\n v21 = __readfsqword(40u);\n v4 = memset(&v17, 0, 40000uLL);\n v5 = *a1;\n v17 = *a1;\n if (a2 > 1) {\n v6 = v4;\n v7 = 400LL;\n v8 = 400LL * (unsigned int)(a2 - 2);\n do {\n v5 += a1[(unsigned long long)v7 / 4];\n v6[(unsigned long long)v7 / 4] = v5;\n v7 += 400LL;\n } while (v7 != v8 + 800);\n v9 = v17;\n for (i = 1LL; i != a2; v6[i++] = v9) v9 += a1[i];\n v11 = (int *)v18;\n v12 = a1 + 100;\n v13 = (int *)&v18[v8 + 400];\n do {\n v14 = *v11;\n v15 = 1LL;\n do {\n if (v14 < v6[v15]) v14 = v6[v15];\n v14 += v12[v15];\n v11[v15++] = v14;\n } while (a2 != v15);\n v11 += 100;\n v6 += 100;\n v12 += 100;\n } while (v11 != v13);\n }\n return v21 - __readfsqword(40u);\n}" + }, + { + "index": 722, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n double height;\n\n double weight;\n\n} StudentDetails;\n\n\n\ntypedef struct {\n\n char name[50];\n\n StudentDetails details;\n\n} Student;\n\n\n\n", + "func": "int func0(Student students[], int count, double h, double w, Student result[]) {\n int index = 0;\n for (int i = 0; i < count; i++) {\n if (students[i].details.height >= h && students[i].details.weight >= w) {\n result[index++] = students[i];\n }\n }\n return index;\n}", + "test": "int main() {\n\n Student students[] = {\n\n {\"Cierra Vega\", {6.2, 70}},\n\n {\"Alden Cantrell\", {5.9, 65}},\n\n {\"Kierra Gentry\", {6.0, 68}},\n\n {\"Pierre Cox\", {5.8, 66}}\n\n };\n\n\n\n Student result[4];\n\n int count;\n\n\n\n count = func0(students, 4, 6.0, 70, result);\n\n assert(count == 1 && strcmp(result[0].name, \"Cierra Vega\") == 0 && result[0].details.height == 6.2 && result[0].details.weight == 70);\n\n\n\n count = func0(students, 4, 5.9, 67, result);\n\n assert(count == 2 && strcmp(result[0].name, \"Cierra Vega\") == 0 && result[0].details.height == 6.2 && result[0].details.weight == 70\n\n && strcmp(result[1].name, \"Kierra Gentry\") == 0 && result[1].details.height == 6.0 && result[1].details.weight == 68);\n\n\n\n count = func0(students, 4, 5.7, 64, result);\n\n assert(count == 4 && strcmp(result[0].name, \"Cierra Vega\") == 0 && result[0].details.height == 6.2 && result[0].details.weight == 70\n\n && strcmp(result[1].name, \"Alden Cantrell\") == 0 && result[1].details.height == 5.9 && result[1].details.weight == 65\n\n && strcmp(result[2].name, \"Kierra Gentry\") == 0 && result[2].details.height == 6.0 && result[2].details.weight == 68\n\n && strcmp(result[3].name, \"Pierre Cox\") == 0 && result[3].details.height == 5.8 && result[3].details.weight == 66);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nmov %rdi,-0x20(%rbp)\nmov %esi,-0x24(%rbp)\nmovsd %xmm0,-0x30(%rbp)\nmovsd %xmm1,-0x38(%rbp)\nmov %rdx,-0x40(%rbp)\nmovl $0x0,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\njmpq 12a2 \nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x3,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmovsd 0x38(%rax),%xmm0\ncomisd -0x30(%rbp),%xmm0\njb 129e \nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x3,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmovsd 0x40(%rax),%xmm0\ncomisd -0x38(%rbp),%xmm0\njb 129e \nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x3,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nmov -0x20(%rbp),%rax\nadd %rax,%rdx\nmov -0x10(%rbp),%eax\nlea 0x1(%rax),%ecx\nmov %ecx,-0x10(%rbp)\nmovslq %eax,%rcx\nmov %rcx,%rax\nshl $0x3,%rax\nadd %rcx,%rax\nshl $0x3,%rax\nmov %rax,%rcx\nmov -0x40(%rbp),%rax\nadd %rcx,%rax\nmov (%rdx),%rcx\nmov 0x8(%rdx),%rbx\nmov %rcx,(%rax)\nmov %rbx,0x8(%rax)\nmov 0x10(%rdx),%rcx\nmov 0x18(%rdx),%rbx\nmov %rcx,0x10(%rax)\nmov %rbx,0x18(%rax)\nmov 0x20(%rdx),%rcx\nmov 0x28(%rdx),%rbx\nmov %rcx,0x20(%rax)\nmov %rbx,0x28(%rax)\nmov 0x30(%rdx),%rcx\nmov 0x38(%rdx),%rbx\nmov %rcx,0x30(%rax)\nmov %rbx,0x38(%rax)\nmov 0x40(%rdx),%rdx\nmov %rdx,0x40(%rax)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x24(%rbp),%eax\njl 11ba \nmov -0x10(%rbp),%eax\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nmov [rbp+var_20], rdi\nmov [rbp+var_24], esi\nmovsd [rbp+var_30], xmm0\nmovsd [rbp+var_38], xmm1\nmov [rbp+var_40], rdx\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp loc_12A2\nloc_11BA:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_20]\nadd rax, rdx\nmovsd xmm0, qword ptr [rax+38h]\ncomisd xmm0, [rbp+var_30]\njb loc_129E\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_20]\nadd rax, rdx\nmovsd xmm0, qword ptr [rax+40h]\ncomisd xmm0, [rbp+var_38]\njb loc_129E\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_20]\nadd rdx, rax\nmov eax, [rbp+var_10]\nlea ecx, [rax+1]\nmov [rbp+var_10], ecx\nmovsxd rcx, eax\nmov rax, rcx\nshl rax, 3\nadd rax, rcx\nshl rax, 3\nmov rcx, rax\nmov rax, [rbp+var_40]\nadd rax, rcx\nmov rcx, [rdx]\nmov rbx, [rdx+8]\nmov [rax], rcx\nmov [rax+8], rbx\nmov rcx, [rdx+10h]\nmov rbx, [rdx+18h]\nmov [rax+10h], rcx\nmov [rax+18h], rbx\nmov rcx, [rdx+20h]\nmov rbx, [rdx+28h]\nmov [rax+20h], rcx\nmov [rax+28h], rbx\nmov rcx, [rdx+30h]\nmov rbx, [rdx+38h]\nmov [rax+30h], rcx\nmov [rax+38h], rbx\nmov rdx, [rdx+40h]\nmov [rax+40h], rdx\nloc_129E:\nadd [rbp+var_C], 1\nloc_12A2:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_24]\njl loc_11BA\nmov eax, [rbp+var_10]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3, double a4, double a5)\n{\n _QWORD *v5; // rdx\n int v6; // eax\n _QWORD *v7; // rax\n __int64 v8; // rbx\n __int64 v9; // rbx\n __int64 v10; // rbx\n __int64 v11; // rbx\n unsigned int v14; // [rsp+30h] [rbp-10h]\n int i; // [rsp+34h] [rbp-Ch]\n\n v14 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(double *)(72LL * i + a1 + 56) >= a4 && *(double *)(72LL * i + a1 + 64) >= a5 )\n {\n v5 = (_QWORD *)(a1 + 72LL * i);\n v6 = v14++;\n v7 = (_QWORD *)(72LL * v6 + a3);\n v8 = v5[1];\n *v7 = *v5;\n v7[1] = v8;\n v9 = v5[3];\n v7[2] = v5[2];\n v7[3] = v9;\n v10 = v5[5];\n v7[4] = v5[4];\n v7[5] = v10;\n v11 = v5[7];\n v7[6] = v5[6];\n v7[7] = v11;\n v7[8] = v5[8];\n }\n }\n return v14;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nmov [rbp+var_20], rdi\nmov [rbp+var_24], esi\nmovsd [rbp+var_30], xmm0\nmovsd [rbp+var_38], xmm1\nmov [rbp+var_40], rdx\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp loc_12A2\nloc_11BA:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_20]\nadd rax, rdx\nmovsd xmm0, qword ptr [rax+38h]\ncomisd xmm0, [rbp+var_30]\njb loc_129E\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_20]\nadd rax, rdx\nmovsd xmm0, qword ptr [rax+40h]\ncomisd xmm0, [rbp+var_38]\njb loc_129E\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 3\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_20]\nadd rdx, rax\nmov eax, [rbp+var_10]\nlea ecx, [rax+1]\nmov [rbp+var_10], ecx\nmovsxd rcx, eax\nmov rax, rcx\nshl rax, 3\nadd rax, rcx\nshl rax, 3\nmov rcx, rax\nmov rax, [rbp+var_40]\nadd rax, rcx\nmov rcx, [rdx]\nmov rbx, [rdx+8]\nmov [rax], rcx\nmov [rax+8], rbx\nmov rcx, [rdx+10h]\nmov rbx, [rdx+18h]\nmov [rax+10h], rcx\nmov [rax+18h], rbx\nmov rcx, [rdx+20h]\nmov rbx, [rdx+28h]\nmov [rax+20h], rcx\nmov [rax+28h], rbx\nmov rcx, [rdx+30h]\nmov rbx, [rdx+38h]\nmov [rax+30h], rcx\nmov [rax+38h], rbx\nmov rdx, [rdx+40h]\nmov [rax+40h], rdx\nloc_129E:\nadd [rbp+var_C], 1\nloc_12A2:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_24]\njl loc_11BA\nmov eax, [rbp+var_10]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2, __int64 a3, double a4, double a5)\n{\n _QWORD *v5; // rdx\n int v6; // eax\n _QWORD *v7; // rax\n __int64 v8; // rbx\n __int64 v9; // rbx\n __int64 v10; // rbx\n __int64 v11; // rbx\n unsigned int v14; // [rsp+30h] [rbp-10h]\n int i; // [rsp+34h] [rbp-Ch]\n\n v14 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(double *)(72LL * i + a1 + 56) >= a4 && *(double *)(72LL * i + a1 + 64) >= a5 )\n {\n v5 = (_QWORD *)(a1 + 72LL * i);\n v6 = v14++;\n v7 = (_QWORD *)(72LL * v6 + a3);\n v8 = v5[1];\n *v7 = *v5;\n v7[1] = v8;\n v9 = v5[3];\n v7[2] = v5[2];\n v7[3] = v9;\n v10 = v5[5];\n v7[4] = v5[4];\n v7[5] = v10;\n v11 = v5[7];\n v7[6] = v5[6];\n v7[7] = v11;\n v7[8] = v5[8];\n }\n }\n return v14;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2, long long a3, double a4, double a5) {\n uint64_t *v5;\n int v6;\n uint64_t *v7;\n long long v8;\n long long v9;\n long long v10;\n long long v11;\n unsigned int v14;\n int i;\n v14 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(double *)(72LL * i + a1 + 56) >= a4 &&\n *(double *)(72LL * i + a1 + 64) >= a5) {\n v5 = (uint64_t *)(a1 + 72LL * i);\n v6 = v14++;\n v7 = (uint64_t *)(72LL * v6 + a3);\n v8 = v5[1];\n *v7 = *v5;\n v7[1] = v8;\n v9 = v5[3];\n v7[2] = v5[2];\n v7[3] = v9;\n v10 = v5[5];\n v7[4] = v5[4];\n v7[5] = v10;\n v11 = v5[7];\n v7[6] = v5[6];\n v7[7] = v11;\n v7[8] = v5[8];\n }\n }\n return v14;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3, double a4, double a5) {\n uint64_t *v5;\n int v6;\n uint64_t *v7;\n long long v8;\n long long v9;\n long long v10;\n long long v11;\n unsigned int v14;\n int i;\n v14 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(double *)(72LL * i + a1 + 56) >= a4 &&\n *(double *)(72LL * i + a1 + 64) >= a5) {\n v5 = (uint64_t *)(a1 + 72LL * i);\n v6 = v14++;\n v7 = (uint64_t *)(72LL * v6 + a3);\n v8 = v5[1];\n *v7 = *v5;\n v7[1] = v8;\n v9 = v5[3];\n v7[2] = v5[2];\n v7[3] = v9;\n v10 = v5[5];\n v7[4] = v5[4];\n v7[5] = v10;\n v11 = v5[7];\n v7[6] = v5[6];\n v7[7] = v11;\n v7[8] = v5[8];\n }\n }\n return v14;\n}" + }, + { + "index": 722, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n double height;\n\n double weight;\n\n} StudentDetails;\n\n\n\ntypedef struct {\n\n char name[50];\n\n StudentDetails details;\n\n} Student;\n\n\n\n", + "func": "int func0(Student students[], int count, double h, double w, Student result[]) {\n int index = 0;\n for (int i = 0; i < count; i++) {\n if (students[i].details.height >= h && students[i].details.weight >= w) {\n result[index++] = students[i];\n }\n }\n return index;\n}", + "test": "int main() {\n\n Student students[] = {\n\n {\"Cierra Vega\", {6.2, 70}},\n\n {\"Alden Cantrell\", {5.9, 65}},\n\n {\"Kierra Gentry\", {6.0, 68}},\n\n {\"Pierre Cox\", {5.8, 66}}\n\n };\n\n\n\n Student result[4];\n\n int count;\n\n\n\n count = func0(students, 4, 6.0, 70, result);\n\n assert(count == 1 && strcmp(result[0].name, \"Cierra Vega\") == 0 && result[0].details.height == 6.2 && result[0].details.weight == 70);\n\n\n\n count = func0(students, 4, 5.9, 67, result);\n\n assert(count == 2 && strcmp(result[0].name, \"Cierra Vega\") == 0 && result[0].details.height == 6.2 && result[0].details.weight == 70\n\n && strcmp(result[1].name, \"Kierra Gentry\") == 0 && result[1].details.height == 6.0 && result[1].details.weight == 68);\n\n\n\n count = func0(students, 4, 5.7, 64, result);\n\n assert(count == 4 && strcmp(result[0].name, \"Cierra Vega\") == 0 && result[0].details.height == 6.2 && result[0].details.weight == 70\n\n && strcmp(result[1].name, \"Alden Cantrell\") == 0 && result[1].details.height == 5.9 && result[1].details.weight == 65\n\n && strcmp(result[2].name, \"Kierra Gentry\") == 0 && result[2].details.height == 6.0 && result[2].details.weight == 68\n\n && strcmp(result[3].name, \"Pierre Cox\") == 0 && result[3].details.height == 5.8 && result[3].details.weight == 66);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11e2 \nmov %rdi,%rax\nlea -0x1(%rsi),%ecx\nlea (%rcx,%rcx,8),%rcx\nlea 0x48(%rdi,%rcx,8),%rdi\nmov $0x0,%r8d\njmp 1191 \nadd $0x48,%rax\ncmp %rdi,%rax\nje 11e8 \nmovsd 0x38(%rax),%xmm2\ncomisd %xmm0,%xmm2\njb 1188 \nmovsd 0x40(%rax),%xmm2\ncomisd %xmm1,%xmm2\njb 1188 \nmovslq %r8d,%rsi\nlea (%rsi,%rsi,8),%rsi\nlea (%rdx,%rsi,8),%rsi\nmovdqu (%rax),%xmm3\nmovups %xmm3,(%rsi)\nmovdqu 0x10(%rax),%xmm4\nmovups %xmm4,0x10(%rsi)\nmovdqu 0x20(%rax),%xmm5\nmovups %xmm5,0x20(%rsi)\nmovdqu 0x30(%rax),%xmm6\nmovups %xmm6,0x30(%rsi)\nmov 0x40(%rax),%rcx\nmov %rcx,0x40(%rsi)\nlea 0x1(%r8),%r8d\njmp 1188 \nmov $0x0,%r8d\nmov %r8d,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1201\nmov rax, rdi\nmovsxd rsi, esi\nlea rcx, [rsi+rsi*8]\nlea rdi, [rdi+rcx*8]\nmov r8d, 0\njmp short loc_11B0\nloc_11A7:\nadd rax, 48h ; 'H'\ncmp rax, rdi\njz short loc_1207\nloc_11B0:\nmovsd xmm2, qword ptr [rax+38h]\ncomisd xmm2, xmm0\njb short loc_11A7\nmovsd xmm2, qword ptr [rax+40h]\ncomisd xmm2, xmm1\njb short loc_11A7\nmovsxd rsi, r8d\nlea rsi, [rsi+rsi*8]\nlea rsi, [rdx+rsi*8]\nmovdqu xmm3, xmmword ptr [rax]\nmovups xmmword ptr [rsi], xmm3\nmovdqu xmm4, xmmword ptr [rax+10h]\nmovups xmmword ptr [rsi+10h], xmm4\nmovdqu xmm5, xmmword ptr [rax+20h]\nmovups xmmword ptr [rsi+20h], xmm5\nmovdqu xmm6, xmmword ptr [rax+30h]\nmovups xmmword ptr [rsi+30h], xmm6\nmov rcx, [rax+40h]\nmov [rsi+40h], rcx\nlea r8d, [r8+1]\njmp short loc_11A7\nloc_1201:\nmov r8d, 0\nloc_1207:\nmov eax, r8d\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3, double a4, double a5)\n{\n __int64 v5; // rax\n __int64 v6; // rdi\n unsigned int v7; // r8d\n __m128i *v8; // rsi\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v5 = a1;\n v6 = a1 + 72LL * a2;\n v7 = 0;\n do\n {\n if ( *(double *)(v5 + 56) >= a4 && *(double *)(v5 + 64) >= a5 )\n {\n v8 = (__m128i *)(a3 + 72LL * (int)v7);\n *v8 = _mm_loadu_si128((const __m128i *)v5);\n v8[1] = _mm_loadu_si128((const __m128i *)(v5 + 16));\n v8[2] = _mm_loadu_si128((const __m128i *)(v5 + 32));\n v8[3] = _mm_loadu_si128((const __m128i *)(v5 + 48));\n v8[4].m128i_i64[0] = *(_QWORD *)(v5 + 64);\n ++v7;\n }\n v5 += 72LL;\n }\n while ( v5 != v6 );\n }\n return v7;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\ntest esi, esi\njle short loc_1201\nmov rax, rdi\nmovsxd rsi, esi\nlea rcx, [rsi+rsi*8]\nlea rdi, [rdi+rcx*8]\nmov r8d, 0\njmp short loc_11B0\nloc_11A7:\nadd rax, 48h ; 'H'\ncmp rax, rdi\njz short loc_1207\nloc_11B0:\nmovsd xmm2, qword ptr [rax+38h]\ncomisd xmm2, xmm0\njb short loc_11A7\nmovsd xmm2, qword ptr [rax+40h]\ncomisd xmm2, xmm1\njb short loc_11A7\nmovsxd rsi, r8d\nlea rsi, [rsi+rsi*8]\nlea rsi, [rdx+rsi*8]\nmovdqu xmm3, xmmword ptr [rax]\nmovups xmmword ptr [rsi], xmm3\nmovdqu xmm4, xmmword ptr [rax+10h]\nmovups xmmword ptr [rsi+10h], xmm4\nmovdqu xmm5, xmmword ptr [rax+20h]\nmovups xmmword ptr [rsi+20h], xmm5\nmovdqu xmm6, xmmword ptr [rax+30h]\nmovups xmmword ptr [rsi+30h], xmm6\nmov rcx, [rax+40h]\nmov [rsi+40h], rcx\nlea r8d, [r8+1]\njmp short loc_11A7\nloc_1201:\nmov r8d, 0\nloc_1207:\nmov eax, r8d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2, __int64 a3, double a4, double a5)\n{\n __int64 v5; // rax\n __int64 v6; // rdi\n unsigned int v7; // r8d\n __m128i *v8; // rsi\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v5 = a1;\n v6 = a1 + 72LL * a2;\n v7 = 0;\n do\n {\n if ( *(double *)(v5 + 56) >= a4 && *(double *)(v5 + 64) >= a5 )\n {\n v8 = (__m128i *)(a3 + 72LL * (int)v7);\n *v8 = _mm_loadu_si128((const __m128i *)v5);\n v8[1] = _mm_loadu_si128((const __m128i *)(v5 + 16));\n v8[2] = _mm_loadu_si128((const __m128i *)(v5 + 32));\n v8[3] = _mm_loadu_si128((const __m128i *)(v5 + 48));\n v8[4].m128i_i64[0] = *(_QWORD *)(v5 + 64);\n ++v7;\n }\n v5 += 72LL;\n }\n while ( v5 != v6 );\n }\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2, long long a3, double a4, double a5) {\n long long v5;\n long long v6;\n unsigned int v7;\n __m128i *v8;\n if (a2 <= 0) {\n return 0;\n } else {\n v5 = a1;\n v6 = a1 + 72LL * a2;\n v7 = 0;\n do {\n if (*(double *)(v5 + 56) >= a4 && *(double *)(v5 + 64) >= a5) {\n v8 = (__m128i *)(a3 + 72LL * (int)v7);\n *v8 = _mm_loadu_si128((const __m128i *)v5);\n v8[1] = _mm_loadu_si128((const __m128i *)(v5 + 16));\n v8[2] = _mm_loadu_si128((const __m128i *)(v5 + 32));\n v8[3] = _mm_loadu_si128((const __m128i *)(v5 + 48));\n v8[4].m128i_i64[0] = *(uint64_t *)(v5 + 64);\n ++v7;\n }\n v5 += 72LL;\n } while (v5 != v6);\n }\n return v7;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3, double a4, double a5) {\n long long v5;\n long long v6;\n unsigned int v7;\n __m128i *v8;\n if (a2 <= 0) {\n return 0;\n } else {\n v5 = a1;\n v6 = a1 + 72LL * a2;\n v7 = 0;\n do {\n if (*(double *)(v5 + 56) >= a4 && *(double *)(v5 + 64) >= a5) {\n v8 = (__m128i *)(a3 + 72LL * (int)v7);\n *v8 = _mm_loadu_si128((const __m128i *)v5);\n v8[1] = _mm_loadu_si128((const __m128i *)(v5 + 16));\n v8[2] = _mm_loadu_si128((const __m128i *)(v5 + 32));\n v8[3] = _mm_loadu_si128((const __m128i *)(v5 + 48));\n v8[4].m128i_i64[0] = *(uint64_t *)(v5 + 64);\n ++v7;\n }\n v5 += 72LL;\n } while (v5 != v6);\n }\n return v7;\n}" + }, + { + "index": 722, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n double height;\n\n double weight;\n\n} StudentDetails;\n\n\n\ntypedef struct {\n\n char name[50];\n\n StudentDetails details;\n\n} Student;\n\n\n\n", + "func": "int func0(Student students[], int count, double h, double w, Student result[]) {\n int index = 0;\n for (int i = 0; i < count; i++) {\n if (students[i].details.height >= h && students[i].details.weight >= w) {\n result[index++] = students[i];\n }\n }\n return index;\n}", + "test": "int main() {\n\n Student students[] = {\n\n {\"Cierra Vega\", {6.2, 70}},\n\n {\"Alden Cantrell\", {5.9, 65}},\n\n {\"Kierra Gentry\", {6.0, 68}},\n\n {\"Pierre Cox\", {5.8, 66}}\n\n };\n\n\n\n Student result[4];\n\n int count;\n\n\n\n count = func0(students, 4, 6.0, 70, result);\n\n assert(count == 1 && strcmp(result[0].name, \"Cierra Vega\") == 0 && result[0].details.height == 6.2 && result[0].details.weight == 70);\n\n\n\n count = func0(students, 4, 5.9, 67, result);\n\n assert(count == 2 && strcmp(result[0].name, \"Cierra Vega\") == 0 && result[0].details.height == 6.2 && result[0].details.weight == 70\n\n && strcmp(result[1].name, \"Kierra Gentry\") == 0 && result[1].details.height == 6.0 && result[1].details.weight == 68);\n\n\n\n count = func0(students, 4, 5.7, 64, result);\n\n assert(count == 4 && strcmp(result[0].name, \"Cierra Vega\") == 0 && result[0].details.height == 6.2 && result[0].details.weight == 70\n\n && strcmp(result[1].name, \"Alden Cantrell\") == 0 && result[1].details.height == 5.9 && result[1].details.weight == 65\n\n && strcmp(result[2].name, \"Kierra Gentry\") == 0 && result[2].details.height == 6.0 && result[2].details.weight == 68\n\n && strcmp(result[3].name, \"Pierre Cox\") == 0 && result[3].details.height == 5.8 && result[3].details.weight == 66);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1580 \nlea -0x1(%rsi),%eax\nxor %r8d,%r8d\nlea (%rax,%rax,8),%rax\nlea 0x48(%rdi,%rax,8),%rcx\nnopw 0x0(%rax,%rax,1)\nmovsd 0x38(%rdi),%xmm2\ncomisd %xmm0,%xmm2\njb 156f \nmovsd 0x40(%rdi),%xmm2\ncomisd %xmm1,%xmm2\njb 156f \nmovslq %r8d,%rax\nmovdqu (%rdi),%xmm3\nadd $0x1,%r8d\nlea (%rax,%rax,8),%rax\nlea (%rdx,%rax,8),%rax\nmovups %xmm3,(%rax)\nmovdqu 0x10(%rdi),%xmm4\nmovups %xmm4,0x10(%rax)\nmovdqu 0x20(%rdi),%xmm5\nmovups %xmm5,0x20(%rax)\nmovdqu 0x30(%rdi),%xmm6\nmovups %xmm6,0x30(%rax)\nmov 0x40(%rdi),%rsi\nmov %rsi,0x40(%rax)\nadd $0x48,%rdi\ncmp %rcx,%rdi\njne 1520 \nmov %r8d,%eax\nretq\nnopl 0x0(%rax)\nxor %r8d,%r8d\nmov %r8d,%eax\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1558\nmovsxd rsi, esi\nlea rax, [rsi+rsi*8]\nxor esi, esi\nlea rcx, [rdi+rax*8]\nnop dword ptr [rax]\nloc_14F8:\nmovsd xmm2, qword ptr [rdi+38h]\ncomisd xmm2, xmm0\njb short loc_1546\nmovsd xmm2, qword ptr [rdi+40h]\ncomisd xmm2, xmm1\njb short loc_1546\nmovsxd rax, esi\nmovdqu xmm3, xmmword ptr [rdi]\nadd esi, 1\nlea rax, [rax+rax*8]\nlea rax, [rdx+rax*8]\nmovups xmmword ptr [rax], xmm3\nmovdqu xmm4, xmmword ptr [rdi+10h]\nmovups xmmword ptr [rax+10h], xmm4\nmovdqu xmm5, xmmword ptr [rdi+20h]\nmovups xmmword ptr [rax+20h], xmm5\nmovdqu xmm6, xmmword ptr [rdi+30h]\nmovups xmmword ptr [rax+30h], xmm6\nmov r8, [rdi+40h]\nmov [rax+40h], r8\nloc_1546:\nadd rdi, 48h ; 'H'\ncmp rdi, rcx\njnz short loc_14F8\nmov eax, esi\nretn\nloc_1558:\nxor esi, esi\nmov eax, esi\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3, double a4, double a5)\n{\n __int64 v5; // rax\n unsigned int v6; // esi\n __int64 v7; // rcx\n __int64 v8; // rax\n __m128i *v9; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v5 = 9LL * a2;\n v6 = 0;\n v7 = a1 + 8 * v5;\n do\n {\n if ( *(double *)(a1 + 56) >= a4 && *(double *)(a1 + 64) >= a5 )\n {\n v8 = (int)v6++;\n v9 = (__m128i *)(a3 + 72 * v8);\n *v9 = _mm_loadu_si128((const __m128i *)a1);\n v9[1] = _mm_loadu_si128((const __m128i *)(a1 + 16));\n v9[2] = _mm_loadu_si128((const __m128i *)(a1 + 32));\n v9[3] = _mm_loadu_si128((const __m128i *)(a1 + 48));\n v9[4].m128i_i64[0] = *(_QWORD *)(a1 + 64);\n }\n a1 += 72LL;\n }\n while ( a1 != v7 );\n return v6;\n}", + "ida_strip_asm": "sub_14E0:\nendbr64\ntest esi, esi\njle short loc_1558\nmovsxd rsi, esi\nlea rax, [rsi+rsi*8]\nxor esi, esi\nlea rcx, [rdi+rax*8]\nnop dword ptr [rax]\nloc_14F8:\nmovsd xmm2, qword ptr [rdi+38h]\ncomisd xmm2, xmm0\njb short loc_1546\nmovsd xmm2, qword ptr [rdi+40h]\ncomisd xmm2, xmm1\njb short loc_1546\nmovsxd rax, esi\nmovdqu xmm3, xmmword ptr [rdi]\nadd esi, 1\nlea rax, [rax+rax*8]\nlea rax, [rdx+rax*8]\nmovups xmmword ptr [rax], xmm3\nmovdqu xmm4, xmmword ptr [rdi+10h]\nmovups xmmword ptr [rax+10h], xmm4\nmovdqu xmm5, xmmword ptr [rdi+20h]\nmovups xmmword ptr [rax+20h], xmm5\nmovdqu xmm6, xmmword ptr [rdi+30h]\nmovups xmmword ptr [rax+30h], xmm6\nmov r8, [rdi+40h]\nmov [rax+40h], r8\nloc_1546:\nadd rdi, 48h ; 'H'\ncmp rdi, rcx\njnz short loc_14F8\nmov eax, esi\nretn\nloc_1558:\nxor esi, esi\nmov eax, esi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_14E0(__int64 a1, int a2, __int64 a3, double a4, double a5)\n{\n __int64 v5; // rax\n unsigned int v6; // esi\n __int64 v7; // rcx\n __int64 v8; // rax\n __m128i *v9; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v5 = 9LL * a2;\n v6 = 0;\n v7 = a1 + 8 * v5;\n do\n {\n if ( *(double *)(a1 + 56) >= a4 && *(double *)(a1 + 64) >= a5 )\n {\n v8 = (int)v6++;\n v9 = (__m128i *)(a3 + 72 * v8);\n *v9 = _mm_loadu_si128((const __m128i *)a1);\n v9[1] = _mm_loadu_si128((const __m128i *)(a1 + 16));\n v9[2] = _mm_loadu_si128((const __m128i *)(a1 + 32));\n v9[3] = _mm_loadu_si128((const __m128i *)(a1 + 48));\n v9[4].m128i_i64[0] = *(_QWORD *)(a1 + 64);\n }\n a1 += 72LL;\n }\n while ( a1 != v7 );\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_14E0(long long a1, int a2, long long a3, double a4, double a5) {\n long long v5;\n unsigned int v6;\n long long v7;\n long long v8;\n __m128i *v9;\n if (a2 <= 0) return 0LL;\n v5 = 9LL * a2;\n v6 = 0;\n v7 = a1 + 8 * v5;\n do {\n if (*(double *)(a1 + 56) >= a4 && *(double *)(a1 + 64) >= a5) {\n v8 = (int)v6++;\n v9 = (__m128i *)(a3 + 72 * v8);\n *v9 = _mm_loadu_si128((const __m128i *)a1);\n v9[1] = _mm_loadu_si128((const __m128i *)(a1 + 16));\n v9[2] = _mm_loadu_si128((const __m128i *)(a1 + 32));\n v9[3] = _mm_loadu_si128((const __m128i *)(a1 + 48));\n v9[4].m128i_i64[0] = *(uint64_t *)(a1 + 64);\n }\n a1 += 72LL;\n } while (a1 != v7);\n return v6;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3, double a4, double a5) {\n long long v5;\n unsigned int v6;\n long long v7;\n long long v8;\n __m128i *v9;\n if (a2 <= 0) return 0LL;\n v5 = 9LL * a2;\n v6 = 0;\n v7 = a1 + 8 * v5;\n do {\n if (*(double *)(a1 + 56) >= a4 && *(double *)(a1 + 64) >= a5) {\n v8 = (int)v6++;\n v9 = (__m128i *)(a3 + 72 * v8);\n *v9 = _mm_loadu_si128((const __m128i *)a1);\n v9[1] = _mm_loadu_si128((const __m128i *)(a1 + 16));\n v9[2] = _mm_loadu_si128((const __m128i *)(a1 + 32));\n v9[3] = _mm_loadu_si128((const __m128i *)(a1 + 48));\n v9[4].m128i_i64[0] = *(uint64_t *)(a1 + 64);\n }\n a1 += 72LL;\n } while (a1 != v7);\n return v6;\n}" + }, + { + "index": 722, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n double height;\n\n double weight;\n\n} StudentDetails;\n\n\n\ntypedef struct {\n\n char name[50];\n\n StudentDetails details;\n\n} Student;\n\n\n\n", + "func": "int func0(Student students[], int count, double h, double w, Student result[]) {\n int index = 0;\n for (int i = 0; i < count; i++) {\n if (students[i].details.height >= h && students[i].details.weight >= w) {\n result[index++] = students[i];\n }\n }\n return index;\n}", + "test": "int main() {\n\n Student students[] = {\n\n {\"Cierra Vega\", {6.2, 70}},\n\n {\"Alden Cantrell\", {5.9, 65}},\n\n {\"Kierra Gentry\", {6.0, 68}},\n\n {\"Pierre Cox\", {5.8, 66}}\n\n };\n\n\n\n Student result[4];\n\n int count;\n\n\n\n count = func0(students, 4, 6.0, 70, result);\n\n assert(count == 1 && strcmp(result[0].name, \"Cierra Vega\") == 0 && result[0].details.height == 6.2 && result[0].details.weight == 70);\n\n\n\n count = func0(students, 4, 5.9, 67, result);\n\n assert(count == 2 && strcmp(result[0].name, \"Cierra Vega\") == 0 && result[0].details.height == 6.2 && result[0].details.weight == 70\n\n && strcmp(result[1].name, \"Kierra Gentry\") == 0 && result[1].details.height == 6.0 && result[1].details.weight == 68);\n\n\n\n count = func0(students, 4, 5.7, 64, result);\n\n assert(count == 4 && strcmp(result[0].name, \"Cierra Vega\") == 0 && result[0].details.height == 6.2 && result[0].details.weight == 70\n\n && strcmp(result[1].name, \"Alden Cantrell\") == 0 && result[1].details.height == 5.9 && result[1].details.weight == 65\n\n && strcmp(result[2].name, \"Kierra Gentry\") == 0 && result[2].details.height == 6.0 && result[2].details.weight == 68\n\n && strcmp(result[3].name, \"Pierre Cox\") == 0 && result[3].details.height == 5.8 && result[3].details.weight == 66);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1580 \nlea -0x1(%rsi),%eax\nxor %r8d,%r8d\nlea (%rax,%rax,8),%rax\nlea 0x48(%rdi,%rax,8),%rcx\nnopw 0x0(%rax,%rax,1)\nmovsd 0x38(%rdi),%xmm2\ncomisd %xmm0,%xmm2\njb 156f \nmovsd 0x40(%rdi),%xmm2\ncomisd %xmm1,%xmm2\njb 156f \nmovslq %r8d,%rax\nmovdqu (%rdi),%xmm3\nadd $0x1,%r8d\nlea (%rax,%rax,8),%rax\nlea (%rdx,%rax,8),%rax\nmovups %xmm3,(%rax)\nmovdqu 0x10(%rdi),%xmm4\nmovups %xmm4,0x10(%rax)\nmovdqu 0x20(%rdi),%xmm5\nmovups %xmm5,0x20(%rax)\nmovdqu 0x30(%rdi),%xmm6\nmovups %xmm6,0x30(%rax)\nmov 0x40(%rdi),%rsi\nmov %rsi,0x40(%rax)\nadd $0x48,%rdi\ncmp %rcx,%rdi\njne 1520 \nmov %r8d,%eax\nretq\nnopl 0x0(%rax)\nxor %r8d,%r8d\nmov %r8d,%eax\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1558\nmovsxd rsi, esi\nlea rax, [rsi+rsi*8]\nxor esi, esi\nlea rcx, [rdi+rax*8]\nnop dword ptr [rax]\nloc_14F8:\nmovsd xmm2, qword ptr [rdi+38h]\ncomisd xmm2, xmm0\njb short loc_1546\nmovsd xmm2, qword ptr [rdi+40h]\ncomisd xmm2, xmm1\njb short loc_1546\nmovsxd rax, esi\nmovdqu xmm3, xmmword ptr [rdi]\nadd esi, 1\nlea rax, [rax+rax*8]\nlea rax, [rdx+rax*8]\nmovups xmmword ptr [rax], xmm3\nmovdqu xmm4, xmmword ptr [rdi+10h]\nmovups xmmword ptr [rax+10h], xmm4\nmovdqu xmm5, xmmword ptr [rdi+20h]\nmovups xmmword ptr [rax+20h], xmm5\nmovdqu xmm6, xmmword ptr [rdi+30h]\nmovups xmmword ptr [rax+30h], xmm6\nmov r8, [rdi+40h]\nmov [rax+40h], r8\nloc_1546:\nadd rdi, 48h ; 'H'\ncmp rdi, rcx\njnz short loc_14F8\nmov eax, esi\nretn\nloc_1558:\nxor esi, esi\nmov eax, esi\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3, double a4, double a5)\n{\n __int64 v5; // rax\n unsigned int v6; // esi\n __int64 v7; // rcx\n __int64 v8; // rax\n __m128i *v9; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v5 = 9LL * a2;\n v6 = 0;\n v7 = a1 + 8 * v5;\n do\n {\n if ( *(double *)(a1 + 56) >= a4 && *(double *)(a1 + 64) >= a5 )\n {\n v8 = (int)v6++;\n v9 = (__m128i *)(a3 + 72 * v8);\n *v9 = _mm_loadu_si128((const __m128i *)a1);\n v9[1] = _mm_loadu_si128((const __m128i *)(a1 + 16));\n v9[2] = _mm_loadu_si128((const __m128i *)(a1 + 32));\n v9[3] = _mm_loadu_si128((const __m128i *)(a1 + 48));\n v9[4].m128i_i64[0] = *(_QWORD *)(a1 + 64);\n }\n a1 += 72LL;\n }\n while ( a1 != v7 );\n return v6;\n}", + "ida_strip_asm": "sub_14E0:\nendbr64\ntest esi, esi\njle short loc_1558\nmovsxd rsi, esi\nlea rax, [rsi+rsi*8]\nxor esi, esi\nlea rcx, [rdi+rax*8]\nnop dword ptr [rax]\nloc_14F8:\nmovsd xmm2, qword ptr [rdi+38h]\ncomisd xmm2, xmm0\njb short loc_1546\nmovsd xmm2, qword ptr [rdi+40h]\ncomisd xmm2, xmm1\njb short loc_1546\nmovsxd rax, esi\nmovdqu xmm3, xmmword ptr [rdi]\nadd esi, 1\nlea rax, [rax+rax*8]\nlea rax, [rdx+rax*8]\nmovups xmmword ptr [rax], xmm3\nmovdqu xmm4, xmmword ptr [rdi+10h]\nmovups xmmword ptr [rax+10h], xmm4\nmovdqu xmm5, xmmword ptr [rdi+20h]\nmovups xmmword ptr [rax+20h], xmm5\nmovdqu xmm6, xmmword ptr [rdi+30h]\nmovups xmmword ptr [rax+30h], xmm6\nmov r8, [rdi+40h]\nmov [rax+40h], r8\nloc_1546:\nadd rdi, 48h ; 'H'\ncmp rdi, rcx\njnz short loc_14F8\nmov eax, esi\nretn\nloc_1558:\nxor esi, esi\nmov eax, esi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_14E0(__int64 a1, int a2, __int64 a3, double a4, double a5)\n{\n __int64 v5; // rax\n unsigned int v6; // esi\n __int64 v7; // rcx\n __int64 v8; // rax\n __m128i *v9; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v5 = 9LL * a2;\n v6 = 0;\n v7 = a1 + 8 * v5;\n do\n {\n if ( *(double *)(a1 + 56) >= a4 && *(double *)(a1 + 64) >= a5 )\n {\n v8 = (int)v6++;\n v9 = (__m128i *)(a3 + 72 * v8);\n *v9 = _mm_loadu_si128((const __m128i *)a1);\n v9[1] = _mm_loadu_si128((const __m128i *)(a1 + 16));\n v9[2] = _mm_loadu_si128((const __m128i *)(a1 + 32));\n v9[3] = _mm_loadu_si128((const __m128i *)(a1 + 48));\n v9[4].m128i_i64[0] = *(_QWORD *)(a1 + 64);\n }\n a1 += 72LL;\n }\n while ( a1 != v7 );\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_14E0(long long a1, int a2, long long a3, double a4, double a5) {\n long long v5;\n unsigned int v6;\n long long v7;\n long long v8;\n __m128i *v9;\n if (a2 <= 0) return 0LL;\n v5 = 9LL * a2;\n v6 = 0;\n v7 = a1 + 8 * v5;\n do {\n if (*(double *)(a1 + 56) >= a4 && *(double *)(a1 + 64) >= a5) {\n v8 = (int)v6++;\n v9 = (__m128i *)(a3 + 72 * v8);\n *v9 = _mm_loadu_si128((const __m128i *)a1);\n v9[1] = _mm_loadu_si128((const __m128i *)(a1 + 16));\n v9[2] = _mm_loadu_si128((const __m128i *)(a1 + 32));\n v9[3] = _mm_loadu_si128((const __m128i *)(a1 + 48));\n v9[4].m128i_i64[0] = *(uint64_t *)(a1 + 64);\n }\n a1 += 72LL;\n } while (a1 != v7);\n return v6;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3, double a4, double a5) {\n long long v5;\n unsigned int v6;\n long long v7;\n long long v8;\n __m128i *v9;\n if (a2 <= 0) return 0LL;\n v5 = 9LL * a2;\n v6 = 0;\n v7 = a1 + 8 * v5;\n do {\n if (*(double *)(a1 + 56) >= a4 && *(double *)(a1 + 64) >= a5) {\n v8 = (int)v6++;\n v9 = (__m128i *)(a3 + 72 * v8);\n *v9 = _mm_loadu_si128((const __m128i *)a1);\n v9[1] = _mm_loadu_si128((const __m128i *)(a1 + 16));\n v9[2] = _mm_loadu_si128((const __m128i *)(a1 + 32));\n v9[3] = _mm_loadu_si128((const __m128i *)(a1 + 48));\n v9[4].m128i_i64[0] = *(uint64_t *)(a1 + 64);\n }\n a1 += 72LL;\n } while (a1 != v7);\n return v6;\n}" + }, + { + "index": 723, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int* nums1, int* nums2, int size) {\n int result = 0;\n for (int i = 0; i < size; i++) {\n if (nums1[i] == nums2[i]) {\n result++;\n }\n }\n return result;\n}", + "test": "int main() {\n\n int arr1_1[] = {1, 2, 3, 4, 5, 6, 7, 8};\n\n int arr2_1[] = {2, 2, 3, 1, 2, 6, 7, 9};\n\n int size_1 = sizeof(arr1_1) / sizeof(arr1_1[0]);\n\n assert(func0(arr1_1, arr2_1, size_1) == 4);\n\n\n\n int arr1_2[] = {0, 1, 2, -1, -5, 6, 0, -3, -2, 3, 4, 6, 8};\n\n int arr2_2[] = {2, 1, 2, -1, -5, 6, 4, -3, -2, 3, 4, 6, 8};\n\n int size_2 = sizeof(arr1_2) / sizeof(arr1_2[0]);\n\n assert(func0(arr1_2, arr2_2, size_2) == 11);\n\n\n\n int arr1_3[] = {2, 4, -6, -9, 11, -12, 14, -5, 17};\n\n int arr2_3[] = {2, 1, 2, -1, -5, 6, 4, -3, -2, 3, 4, 6, 8};\n\n int size_3 = sizeof(arr1_3) / sizeof(arr1_3[0]);\n\n assert(func0(arr1_3, arr2_3, size_3) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %edx,-0x24(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11c4 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x20(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 11c0 \naddl $0x1,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x24(%rbp),%eax\njl 118c \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11C4\nloc_118C:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11C0\nadd [rbp+var_8], 1\nloc_11C0:\nadd [rbp+var_4], 1\nloc_11C4:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_24]\njl short loc_118C\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n unsigned int v4; // [rsp+1Ch] [rbp-8h]\n int i; // [rsp+20h] [rbp-4h]\n\n v4 = 0;\n for ( i = 0; i < a3; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4LL * i + a2) )\n ++v4;\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11C4\nloc_118C:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11C0\nadd [rbp+var_8], 1\nloc_11C0:\nadd [rbp+var_4], 1\nloc_11C4:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_24]\njl short loc_118C\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, int a3)\n{\n unsigned int v4; // [rsp+1Ch] [rbp-8h]\n int i; // [rsp+20h] [rbp-4h]\n\n v4 = 0;\n for ( i = 0; i < a3; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4LL * i + a2) )\n ++v4;\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, int a3) {\n unsigned int v4;\n int i;\n v4 = 0;\n for (i = 0; i < a3; ++i) {\n if (*(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4LL * i + a2)) ++v4;\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3) {\n unsigned int v4;\n int i;\n v4 = 0;\n for (i = 0; i < a3; ++i) {\n if (*(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4LL * i + a2)) ++v4;\n }\n return v4;\n}" + }, + { + "index": 723, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int* nums1, int* nums2, int size) {\n int result = 0;\n for (int i = 0; i < size; i++) {\n if (nums1[i] == nums2[i]) {\n result++;\n }\n }\n return result;\n}", + "test": "int main() {\n\n int arr1_1[] = {1, 2, 3, 4, 5, 6, 7, 8};\n\n int arr2_1[] = {2, 2, 3, 1, 2, 6, 7, 9};\n\n int size_1 = sizeof(arr1_1) / sizeof(arr1_1[0]);\n\n assert(func0(arr1_1, arr2_1, size_1) == 4);\n\n\n\n int arr1_2[] = {0, 1, 2, -1, -5, 6, 0, -3, -2, 3, 4, 6, 8};\n\n int arr2_2[] = {2, 1, 2, -1, -5, 6, 4, -3, -2, 3, 4, 6, 8};\n\n int size_2 = sizeof(arr1_2) / sizeof(arr1_2[0]);\n\n assert(func0(arr1_2, arr2_2, size_2) == 11);\n\n\n\n int arr1_3[] = {2, 4, -6, -9, 11, -12, 14, -5, 17};\n\n int arr2_3[] = {2, 1, 2, -1, -5, 6, 4, -3, -2, 3, 4, 6, 8};\n\n int size_3 = sizeof(arr1_3) / sizeof(arr1_3[0]);\n\n assert(func0(arr1_3, arr2_3, size_3) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edx,%edx\njle 119b \nlea -0x1(%rdx),%ecx\nmov $0x0,%eax\nmov $0x0,%r8d\njmp 118d \nlea 0x1(%rax),%rdx\ncmp %rcx,%rax\nje 11a1 \nmov %rdx,%rax\nmov (%rsi,%rax,4),%edx\ncmp %edx,(%rdi,%rax,4)\njne 1181 \nadd $0x1,%r8d\njmp 1181 \nmov $0x0,%r8d\nmov %r8d,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest edx, edx\njle short loc_119C\nmovsxd rdx, edx\nshl rdx, 2\nmov eax, 0\nmov ecx, 0\njmp short loc_118D\nloc_1184:\nadd rax, 4\ncmp rax, rdx\njz short loc_11A1\nloc_118D:\nmov r8d, [rsi+rax]\ncmp [rdi+rax], r8d\njnz short loc_1184\nadd ecx, 1\njmp short loc_1184\nloc_119C:\nmov ecx, 0\nloc_11A1:\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n __int64 v3; // rdx\n __int64 v4; // rax\n unsigned int v5; // ecx\n\n if ( a3 <= 0 )\n {\n return 0;\n }\n else\n {\n v3 = 4LL * a3;\n v4 = 0LL;\n v5 = 0;\n do\n {\n if ( *(_DWORD *)(a1 + v4) == *(_DWORD *)(a2 + v4) )\n ++v5;\n v4 += 4LL;\n }\n while ( v4 != v3 );\n }\n return v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest edx, edx\njle short loc_119C\nmovsxd rdx, edx\nshl rdx, 2\nmov eax, 0\nmov ecx, 0\njmp short loc_118D\nloc_1184:\nadd rax, 4\ncmp rax, rdx\njz short loc_11A1\nloc_118D:\nmov r8d, [rsi+rax]\ncmp [rdi+rax], r8d\njnz short loc_1184\nadd ecx, 1\njmp short loc_1184\nloc_119C:\nmov ecx, 0\nloc_11A1:\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, int a3)\n{\n __int64 v3; // rdx\n __int64 v4; // rax\n unsigned int v5; // ecx\n\n if ( a3 <= 0 )\n {\n return 0;\n }\n else\n {\n v3 = 4LL * a3;\n v4 = 0LL;\n v5 = 0;\n do\n {\n if ( *(_DWORD *)(a1 + v4) == *(_DWORD *)(a2 + v4) )\n ++v5;\n v4 += 4LL;\n }\n while ( v4 != v3 );\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, int a3) {\n long long v3;\n long long v4;\n unsigned int v5;\n if (a3 <= 0) {\n return 0;\n } else {\n v3 = 4LL * a3;\n v4 = 0LL;\n v5 = 0;\n do {\n if (*(uint32_t *)(a1 + v4) == *(uint32_t *)(a2 + v4)) ++v5;\n v4 += 4LL;\n } while (v4 != v3);\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3) {\n long long v3;\n long long v4;\n unsigned int v5;\n if (a3 <= 0) {\n return 0;\n } else {\n v3 = 4LL * a3;\n v4 = 0LL;\n v5 = 0;\n do {\n if (*(uint32_t *)(a1 + v4) == *(uint32_t *)(a2 + v4)) ++v5;\n v4 += 4LL;\n } while (v4 != v3);\n }\n return v5;\n}" + }, + { + "index": 724, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int base, int power) {\n int digits[1000];\n int size = 1;\n digits[0] = 1;\n for (int p = 0; p < power; p++) {\n int carry = 0;\n for (int i = 0; i < size; i++) {\n long temp = (long)digits[i] * base + carry;\n digits[i] = temp % 10;\n carry = temp / 10;\n }\n while (carry > 0) {\n digits[size] = carry % 10;\n carry /= 10;\n size++;\n }\n }\n int sum = 0;\n for (int i = 0; i < size; i++) {\n sum += digits[i];\n }\n return sum;\n}", + "test": "int main() {\n\n assert(func0(2, 100) == 115);\n\n assert(func0(8, 10) == 37);\n\n assert(func0(8, 15) == 62);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0xfe0,%rsp\nmov %edi,-0xfd4(%rbp)\nmov %esi,-0xfd8(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovl $0x1,-0xfd0(%rbp)\nmovl $0x1,-0xfb0(%rbp)\nmovl $0x0,-0xfcc(%rbp)\njmpq 1306 \nmovl $0x0,-0xfc8(%rbp)\nmovl $0x0,-0xfc4(%rbp)\njmpq 127b \nmov -0xfc4(%rbp),%eax\ncltq\nmov -0xfb0(%rbp,%rax,4),%eax\nmovslq %eax,%rdx\nmov -0xfd4(%rbp),%eax\ncltq\nimul %rax,%rdx\nmov -0xfc8(%rbp),%eax\ncltq\nadd %rdx,%rax\nmov %rax,-0xfb8(%rbp)\nmov -0xfb8(%rbp),%rcx\nmovabs $0x6666666666666667,%rdx\nmov %rcx,%rax\nimul %rdx\nsar $0x2,%rdx\nmov %rcx,%rax\nsar $0x3f,%rax\nsub %rax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nadd %rax,%rax\nsub %rax,%rcx\nmov %rcx,%rdx\nmov -0xfc4(%rbp),%eax\ncltq\nmov %edx,-0xfb0(%rbp,%rax,4)\nmov -0xfb8(%rbp),%rcx\nmovabs $0x6666666666666667,%rdx\nmov %rcx,%rax\nimul %rdx\nsar $0x2,%rdx\nmov %rcx,%rax\nsar $0x3f,%rax\nsub %rax,%rdx\nmov %rdx,%rax\nmov %eax,-0xfc8(%rbp)\naddl $0x1,-0xfc4(%rbp)\nmov -0xfc4(%rbp),%eax\ncmp -0xfd0(%rbp),%eax\njl 11cf \njmp 12f6 \nmov -0xfc8(%rbp),%ecx\nmovslq %ecx,%rax\nimul $0x66666667,%rax,%rax\nshr $0x20,%rax\nmov %eax,%edx\nsar $0x2,%edx\nmov %ecx,%eax\nsar $0x1f,%eax\nsub %eax,%edx\nmov %edx,%eax\nshl $0x2,%eax\nadd %edx,%eax\nadd %eax,%eax\nsub %eax,%ecx\nmov %ecx,%edx\nmov -0xfd0(%rbp),%eax\ncltq\nmov %edx,-0xfb0(%rbp,%rax,4)\nmov -0xfc8(%rbp),%eax\nmovslq %eax,%rdx\nimul $0x66666667,%rdx,%rdx\nshr $0x20,%rdx\nsar $0x2,%edx\nsar $0x1f,%eax\nsub %eax,%edx\nmov %edx,%eax\nmov %eax,-0xfc8(%rbp)\naddl $0x1,-0xfd0(%rbp)\ncmpl $0x0,-0xfc8(%rbp)\njg 128f \naddl $0x1,-0xfcc(%rbp)\nmov -0xfcc(%rbp),%eax\ncmp -0xfd8(%rbp),%eax\njl 11b6 \nmovl $0x0,-0xfc0(%rbp)\nmovl $0x0,-0xfbc(%rbp)\njmp 134a \nmov -0xfbc(%rbp),%eax\ncltq\nmov -0xfb0(%rbp,%rax,4),%eax\nadd %eax,-0xfc0(%rbp)\naddl $0x1,-0xfbc(%rbp)\nmov -0xfbc(%rbp),%eax\ncmp -0xfd0(%rbp),%eax\njl 132e \nmov -0xfc0(%rbp),%eax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 1372 \ncallq 1060 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0FE0h\nmov [rbp+var_FD4], edi\nmov [rbp+var_FD8], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_FD0], 1\nmov [rbp+var_FB0], 1\nmov [rbp+var_FCC], 0\njmp loc_1306\nloc_11B6:\nmov [rbp+var_FC8], 0\nmov [rbp+var_FC4], 0\njmp loc_127B\nloc_11CF:\nmov eax, [rbp+var_FC4]\ncdqe\nmov eax, [rbp+rax*4+var_FB0]\nmovsxd rdx, eax\nmov eax, [rbp+var_FD4]\ncdqe\nimul rdx, rax\nmov eax, [rbp+var_FC8]\ncdqe\nadd rax, rdx\nmov [rbp+var_FB8], rax\nmov rcx, [rbp+var_FB8]\nmov rdx, 6666666666666667h\nmov rax, rcx\nimul rdx\nsar rdx, 2\nmov rax, rcx\nsar rax, 3Fh\nsub rdx, rax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nadd rax, rax\nsub rcx, rax\nmov rdx, rcx\nmov eax, [rbp+var_FC4]\ncdqe\nmov [rbp+rax*4+var_FB0], edx\nmov rcx, [rbp+var_FB8]\nmov rdx, 6666666666666667h\nmov rax, rcx\nimul rdx\nmov rax, rdx\nsar rax, 2\nsar rcx, 3Fh\nmov rdx, rcx\nsub rax, rdx\nmov [rbp+var_FC8], eax\nadd [rbp+var_FC4], 1\nloc_127B:\nmov eax, [rbp+var_FC4]\ncmp eax, [rbp+var_FD0]\njl loc_11CF\njmp short loc_12F6\nloc_128F:\nmov ecx, [rbp+var_FC8]\nmovsxd rax, ecx\nimul rax, 66666667h\nshr rax, 20h\nmov edx, eax\nsar edx, 2\nmov eax, ecx\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nsub ecx, eax\nmov edx, ecx\nmov eax, [rbp+var_FD0]\ncdqe\nmov [rbp+rax*4+var_FB0], edx\nmov eax, [rbp+var_FC8]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_FC8], eax\nadd [rbp+var_FD0], 1\nloc_12F6:\ncmp [rbp+var_FC8], 0\njg short loc_128F\nadd [rbp+var_FCC], 1\nloc_1306:\nmov eax, [rbp+var_FCC]\ncmp eax, [rbp+var_FD8]\njl loc_11B6\nmov [rbp+var_FC0], 0\nmov [rbp+var_FBC], 0\njmp short loc_134A\nloc_132E:\nmov eax, [rbp+var_FBC]\ncdqe\nmov eax, [rbp+rax*4+var_FB0]\nadd [rbp+var_FC0], eax\nadd [rbp+var_FBC], 1\nloc_134A:\nmov eax, [rbp+var_FBC]\ncmp eax, [rbp+var_FD0]\njl short loc_132E\nmov eax, [rbp+var_FC0]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1372\ncall ___stack_chk_fail\nlocret_1372:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n int v3; // [rsp+10h] [rbp-FD0h]\n int i; // [rsp+14h] [rbp-FCCh]\n int v5; // [rsp+18h] [rbp-FC8h]\n int j; // [rsp+1Ch] [rbp-FC4h]\n unsigned int v7; // [rsp+20h] [rbp-FC0h]\n int k; // [rsp+24h] [rbp-FBCh]\n __int64 v9; // [rsp+28h] [rbp-FB8h]\n _DWORD v10[1002]; // [rsp+30h] [rbp-FB0h]\n unsigned __int64 v11; // [rsp+FD8h] [rbp-8h]\n\n v11 = __readfsqword(0x28u);\n v3 = 1;\n v10[0] = 1;\n for ( i = 0; i < a2; ++i )\n {\n v5 = 0;\n for ( j = 0; j < v3; ++j )\n {\n v9 = a1 * (__int64)(int)v10[j] + v5;\n v10[j] = (int)v9 % 10;\n v5 = v9 / 10;\n }\n while ( v5 > 0 )\n {\n v10[v3] = v5 % 10;\n v5 /= 10;\n ++v3;\n }\n }\n v7 = 0;\n for ( k = 0; k < v3; ++k )\n v7 += v10[k];\n return v7;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0FE0h\nmov [rbp+var_FD4], edi\nmov [rbp+var_FD8], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_FD0], 1\nmov [rbp+var_FB0], 1\nmov [rbp+var_FCC], 0\njmp loc_1306\nloc_11B6:\nmov [rbp+var_FC8], 0\nmov [rbp+var_FC4], 0\njmp loc_127B\nloc_11CF:\nmov eax, [rbp+var_FC4]\ncdqe\nmov eax, [rbp+rax*4+var_FB0]\nmovsxd rdx, eax\nmov eax, [rbp+var_FD4]\ncdqe\nimul rdx, rax\nmov eax, [rbp+var_FC8]\ncdqe\nadd rax, rdx\nmov [rbp+var_FB8], rax\nmov rcx, [rbp+var_FB8]\nmov rdx, 6666666666666667h\nmov rax, rcx\nimul rdx\nsar rdx, 2\nmov rax, rcx\nsar rax, 3Fh\nsub rdx, rax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nadd rax, rax\nsub rcx, rax\nmov rdx, rcx\nmov eax, [rbp+var_FC4]\ncdqe\nmov [rbp+rax*4+var_FB0], edx\nmov rcx, [rbp+var_FB8]\nmov rdx, 6666666666666667h\nmov rax, rcx\nimul rdx\nmov rax, rdx\nsar rax, 2\nsar rcx, 3Fh\nmov rdx, rcx\nsub rax, rdx\nmov [rbp+var_FC8], eax\nadd [rbp+var_FC4], 1\nloc_127B:\nmov eax, [rbp+var_FC4]\ncmp eax, [rbp+var_FD0]\njl loc_11CF\njmp short loc_12F6\nloc_128F:\nmov ecx, [rbp+var_FC8]\nmovsxd rax, ecx\nimul rax, 66666667h\nshr rax, 20h\nmov edx, eax\nsar edx, 2\nmov eax, ecx\nsar eax, 1Fh\nsub edx, eax\nmov eax, edx\nshl eax, 2\nadd eax, edx\nadd eax, eax\nsub ecx, eax\nmov edx, ecx\nmov eax, [rbp+var_FD0]\ncdqe\nmov [rbp+rax*4+var_FB0], edx\nmov eax, [rbp+var_FC8]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_FC8], eax\nadd [rbp+var_FD0], 1\nloc_12F6:\ncmp [rbp+var_FC8], 0\njg short loc_128F\nadd [rbp+var_FCC], 1\nloc_1306:\nmov eax, [rbp+var_FCC]\ncmp eax, [rbp+var_FD8]\njl loc_11B6\nmov [rbp+var_FC0], 0\nmov [rbp+var_FBC], 0\njmp short loc_134A\nloc_132E:\nmov eax, [rbp+var_FBC]\ncdqe\nmov eax, [rbp+rax*4+var_FB0]\nadd [rbp+var_FC0], eax\nadd [rbp+var_FBC], 1\nloc_134A:\nmov eax, [rbp+var_FBC]\ncmp eax, [rbp+var_FD0]\njl short loc_132E\nmov eax, [rbp+var_FC0]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1372\ncall ___stack_chk_fail\nlocret_1372:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1, int a2)\n{\n int v3; // [rsp+10h] [rbp-FD0h]\n int i; // [rsp+14h] [rbp-FCCh]\n int v5; // [rsp+18h] [rbp-FC8h]\n int j; // [rsp+1Ch] [rbp-FC4h]\n unsigned int v7; // [rsp+20h] [rbp-FC0h]\n int k; // [rsp+24h] [rbp-FBCh]\n __int64 v9; // [rsp+28h] [rbp-FB8h]\n _DWORD v10[1002]; // [rsp+30h] [rbp-FB0h]\n unsigned __int64 v11; // [rsp+FD8h] [rbp-8h]\n\n v11 = __readfsqword(0x28u);\n v3 = 1;\n v10[0] = 1;\n for ( i = 0; i < a2; ++i )\n {\n v5 = 0;\n for ( j = 0; j < v3; ++j )\n {\n v9 = a1 * (__int64)(int)v10[j] + v5;\n v10[j] = (int)v9 % 10;\n v5 = v9 / 10;\n }\n while ( v5 > 0 )\n {\n v10[v3] = v5 % 10;\n v5 /= 10;\n ++v3;\n }\n }\n v7 = 0;\n for ( k = 0; k < v3; ++k )\n v7 += v10[k];\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1, int a2) {\n int v3;\n int i;\n int v5;\n int j;\n unsigned int v7;\n int k;\n long long v9;\n uint32_t v10[1002];\n unsigned long long v11;\n v11 = __readfsqword(40u);\n v3 = 1;\n v10[0] = 1;\n for (i = 0; i < a2; ++i) {\n v5 = 0;\n for (j = 0; j < v3; ++j) {\n v9 = a1 * (long long)(int)v10[j] + v5;\n v10[j] = (int)v9 % 10;\n v5 = v9 / 10;\n }\n while (v5 > 0) {\n v10[v3] = v5 % 10;\n v5 /= 10;\n ++v3;\n }\n }\n v7 = 0;\n for (k = 0; k < v3; ++k) v7 += v10[k];\n return v7;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n int v3;\n int i;\n int v5;\n int j;\n unsigned int v7;\n int k;\n long long v9;\n uint32_t v10[1002];\n unsigned long long v11;\n v11 = __readfsqword(40u);\n v3 = 1;\n v10[0] = 1;\n for (i = 0; i < a2; ++i) {\n v5 = 0;\n for (j = 0; j < v3; ++j) {\n v9 = a1 * (long long)(int)v10[j] + v5;\n v10[j] = (int)v9 % 10;\n v5 = v9 / 10;\n }\n while (v5 > 0) {\n v10[v3] = v5 % 10;\n v5 /= 10;\n ++v3;\n }\n }\n v7 = 0;\n for (k = 0; k < v3; ++k) v7 += v10[k];\n return v7;\n}" + }, + { + "index": 724, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int base, int power) {\n int digits[1000];\n int size = 1;\n digits[0] = 1;\n for (int p = 0; p < power; p++) {\n int carry = 0;\n for (int i = 0; i < size; i++) {\n long temp = (long)digits[i] * base + carry;\n digits[i] = temp % 10;\n carry = temp / 10;\n }\n while (carry > 0) {\n digits[size] = carry % 10;\n carry /= 10;\n size++;\n }\n }\n int sum = 0;\n for (int i = 0; i < size; i++) {\n sum += digits[i];\n }\n return sum;\n}", + "test": "int main() {\n\n assert(func0(2, 100) == 115);\n\n assert(func0(8, 10) == 37);\n\n assert(func0(8, 15) == 62);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nsub $0xfb0,%rsp\nmov %fs:0x28,%rax\nmov %rax,0xfa8(%rsp)\nxor %eax,%eax\nmovl $0x1,(%rsp)\ntest %esi,%esi\njle 1294 \nmov $0x0,%r9d\nmov $0x1,%ebp\nlea 0x4(%rsp),%r11\nmov $0x0,%r10d\nmovslq %edi,%rdi\nmovabs $0x6666666666666667,%r8\njmpq 1249 \nmov %rsp,%rbx\nlea -0x1(%rbp),%eax\nlea (%r11,%rax,4),%r12\nmov %r10d,%edx\nmovslq (%rbx),%rcx\nimul %rdi,%rcx\nmovslq %edx,%rdx\nadd %rdx,%rcx\nmov %rcx,%rax\nimul %r8\nsar $0x2,%rdx\nmov %rcx,%rax\nsar $0x3f,%rax\nsub %rax,%rdx\nlea (%rdx,%rdx,4),%rax\nadd %rax,%rax\nsub %rax,%rcx\nmov %ecx,(%rbx)\nadd $0x4,%rbx\ncmp %r12,%rbx\njne 11cf \ntest %edx,%edx\njle 1240 \nadd $0x1,%ebp\nmovslq %ebp,%rcx\nmovslq %edx,%rax\nimul $0x66666667,%rax,%rax\nsar $0x22,%rax\nmov %edx,%ebx\nsar $0x1f,%ebx\nsub %ebx,%eax\nlea (%rax,%rax,4),%ebx\nadd %ebx,%ebx\nmov %edx,%ebp\nsub %ebx,%ebp\nmov %ebp,-0x4(%rsp,%rcx,4)\nmov %edx,%ebx\nmov %eax,%edx\nmov %ecx,%ebp\nadd $0x1,%rcx\ncmp $0x9,%ebx\njg 120f \nadd $0x1,%r9d\ncmp %r9d,%esi\nje 1253 \ntest %ebp,%ebp\njg 11c2 \njmp 1240 \ntest %ebp,%ebp\njle 128d \nmov $0x0,%eax\nmov $0x0,%edx\nadd (%rsp,%rax,4),%edx\nadd $0x1,%rax\ncmp %eax,%ebp\njg 1261 \nmov 0xfa8(%rsp),%rax\nxor %fs:0x28,%rax\njne 1299 \nmov %edx,%eax\nadd $0xfb0,%rsp\npop %rbx\npop %rbp\npop %r12\nretq\nmov $0x0,%edx\njmp 126c \nmov (%rsp),%edx\njmp 126c \ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 0FB8h\nmov r9d, esi\nmov rax, fs:28h\nmov [rsp+0FC8h+var_20], rax\nxor eax, eax\nmov [rsp+0FC8h+var_FC8], 1\nmov r8d, 0\nmov ebx, 1\nmov r10d, 0\nmovsxd rsi, edi\nmov rdi, 6666666666666667h\ntest r9d, r9d\njg loc_1251\njmp loc_125F\nloc_11BF:\nmov r11, rsp\nmovsxd rax, ebx\nlea rbp, [r11+rax*4]\nmov eax, r10d\nloc_11CC:\nmovsxd rcx, dword ptr [r11]\nimul rcx, rsi\ncdqe\nadd rcx, rax\nmov rax, rcx\nimul rdi\nsar rdx, 2\nmov rax, rcx\nsar rax, 3Fh\nsub rdx, rax\nlea rax, [rdx+rdx*4]\nadd rax, rax\nsub rcx, rax\nmov [r11], ecx\nmov eax, edx\nadd r11, 4\ncmp r11, rbp\njnz short loc_11CC\ntest edx, edx\njle short loc_1248\nlea ecx, [rbx+1]\nmovsxd rcx, ecx\nloc_120E:\nmovsxd rdx, eax\nimul rdx, 66666667h\nsar rdx, 22h\nmov r11d, eax\nsar r11d, 1Fh\nsub edx, r11d\nlea r11d, [rdx+rdx*4]\nadd r11d, r11d\nmov ebx, eax\nsub ebx, r11d\nmov [rsp+rcx*4+0FC8h+var_FCC], ebx\nmov r11d, eax\nmov eax, edx\nmov rbx, rcx\nadd rcx, 1\ncmp r11d, 9\njg short loc_120E\nloc_1248:\nadd r8d, 1\ncmp r9d, r8d\njz short loc_125B\nloc_1251:\ntest ebx, ebx\njg loc_11BF\njmp short loc_1248\nloc_125B:\ntest ebx, ebx\njle short loc_1298\nloc_125F:\nmov rax, rsp\nmovsxd rbx, ebx\nlea rcx, [rax+rbx*4]\nmov edx, 0\nloc_126E:\nadd edx, [rax]\nadd rax, 4\ncmp rcx, rax\njnz short loc_126E\nloc_1279:\nmov rax, [rsp+0FC8h+var_20]\nsub rax, fs:28h\njnz short loc_129F\nmov eax, edx\nadd rsp, 0FB8h\npop rbx\npop rbp\nretn\nloc_1298:\nmov edx, 0\njmp short loc_1279\nloc_129F:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n int v2; // r8d\n int v3; // ebx\n int *v4; // r11\n int v5; // eax\n __int64 v6; // rcx\n __int64 v7; // rcx\n int v8; // r11d\n _DWORD *v9; // rax\n unsigned int v10; // edx\n _DWORD v13[1002]; // [rsp+4h] [rbp-FC8h] BYREF\n unsigned __int64 v14; // [rsp+FACh] [rbp-20h]\n\n v14 = __readfsqword(0x28u);\n v13[0] = 1;\n v2 = 0;\n v3 = 1;\n if ( a2 <= 0 )\n goto LABEL_12;\n do\n {\n if ( v3 > 0 )\n {\n v4 = v13;\n v5 = 0;\n do\n {\n v6 = v5 + a1 * (__int64)*v4;\n *v4 = v6 % 10;\n v5 = v6 / 10;\n ++v4;\n }\n while ( v4 != &v13[v3] );\n if ( (int)(v6 / 10) > 0 )\n {\n v7 = v3 + 1;\n do\n {\n v13[v7 - 1] = v5 % 10;\n v8 = v5;\n v5 /= 10;\n v3 = v7++;\n }\n while ( v8 > 9 );\n }\n }\n ++v2;\n }\n while ( a2 != v2 );\n if ( v3 <= 0 )\n {\n return 0;\n }\n else\n {\nLABEL_12:\n v9 = v13;\n v10 = 0;\n do\n v10 += *v9++;\n while ( &v13[v3] != v9 );\n }\n return v10;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\npush rbx\nsub rsp, 0FB8h\nmov r9d, esi\nmov rax, fs:28h\nmov [rsp+0FC8h+var_20], rax\nxor eax, eax\nmov [rsp+0FC8h+var_FC8], 1\nmov r8d, 0\nmov ebx, 1\nmov r10d, 0\nmovsxd rsi, edi\nmov rdi, 6666666666666667h\ntest r9d, r9d\njg loc_1251\njmp loc_125F\nloc_11BF:\nmov r11, rsp\nmovsxd rax, ebx\nlea rbp, [r11+rax*4]\nmov eax, r10d\nloc_11CC:\nmovsxd rcx, dword ptr [r11]\nimul rcx, rsi\ncdqe\nadd rcx, rax\nmov rax, rcx\nimul rdi\nsar rdx, 2\nmov rax, rcx\nsar rax, 3Fh\nsub rdx, rax\nlea rax, [rdx+rdx*4]\nadd rax, rax\nsub rcx, rax\nmov [r11], ecx\nmov eax, edx\nadd r11, 4\ncmp r11, rbp\njnz short loc_11CC\ntest edx, edx\njle short loc_1248\nlea ecx, [rbx+1]\nmovsxd rcx, ecx\nloc_120E:\nmovsxd rdx, eax\nimul rdx, 66666667h\nsar rdx, 22h\nmov r11d, eax\nsar r11d, 1Fh\nsub edx, r11d\nlea r11d, [rdx+rdx*4]\nadd r11d, r11d\nmov ebx, eax\nsub ebx, r11d\nmov [rsp+rcx*4+0FC8h+var_FCC], ebx\nmov r11d, eax\nmov eax, edx\nmov rbx, rcx\nadd rcx, 1\ncmp r11d, 9\njg short loc_120E\nloc_1248:\nadd r8d, 1\ncmp r9d, r8d\njz short loc_125B\nloc_1251:\ntest ebx, ebx\njg loc_11BF\njmp short loc_1248\nloc_125B:\ntest ebx, ebx\njle short loc_1298\nloc_125F:\nmov rax, rsp\nmovsxd rbx, ebx\nlea rcx, [rax+rbx*4]\nmov edx, 0\nloc_126E:\nadd edx, [rax]\nadd rax, 4\ncmp rcx, rax\njnz short loc_126E\nloc_1279:\nmov rax, [rsp+0FC8h+var_20]\nsub rax, fs:28h\njnz short loc_129F\nmov eax, edx\nadd rsp, 0FB8h\npop rbx\npop rbp\nretn\nloc_1298:\nmov edx, 0\njmp short loc_1279\nloc_129F:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1, int a2)\n{\n int v2; // r8d\n int v3; // ebx\n int *v4; // r11\n int v5; // eax\n __int64 v6; // rcx\n __int64 v7; // rcx\n int v8; // r11d\n _DWORD *v9; // rax\n unsigned int v10; // edx\n _DWORD v13[1002]; // [rsp+4h] [rbp-FC8h] BYREF\n unsigned __int64 v14; // [rsp+FACh] [rbp-20h]\n\n v14 = __readfsqword(0x28u);\n v13[0] = 1;\n v2 = 0;\n v3 = 1;\n if ( a2 <= 0 )\n goto LABEL_12;\n do\n {\n if ( v3 > 0 )\n {\n v4 = v13;\n v5 = 0;\n do\n {\n v6 = v5 + a1 * (__int64)*v4;\n *v4 = v6 % 10;\n v5 = v6 / 10;\n ++v4;\n }\n while ( v4 != &v13[v3] );\n if ( (int)(v6 / 10) > 0 )\n {\n v7 = v3 + 1;\n do\n {\n v13[v7 - 1] = v5 % 10;\n v8 = v5;\n v5 /= 10;\n v3 = v7++;\n }\n while ( v8 > 9 );\n }\n }\n ++v2;\n }\n while ( a2 != v2 );\n if ( v3 <= 0 )\n {\n return 0;\n }\n else\n {\nLABEL_12:\n v9 = v13;\n v10 = 0;\n do\n v10 += *v9++;\n while ( &v13[v3] != v9 );\n }\n return v10;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1, int a2) {\n int v2;\n int v3;\n int *v4;\n int v5;\n long long v6;\n long long v7;\n int v8;\n uint32_t *v9;\n unsigned int v10;\n uint32_t v13[1002];\n unsigned long long v14;\n v14 = __readfsqword(40u);\n v13[0] = 1;\n v2 = 0;\n v3 = 1;\n if (a2 <= 0) goto LABEL_12;\n do {\n if (v3 > 0) {\n v4 = v13;\n v5 = 0;\n do {\n v6 = v5 + a1 * (long long)*v4;\n *v4 = v6 % 10;\n v5 = v6 / 10;\n ++v4;\n } while (v4 != &v13[v3]);\n if ((int)(v6 / 10) > 0) {\n v7 = v3 + 1;\n do {\n v13[v7 - 1] = v5 % 10;\n v8 = v5;\n v5 /= 10;\n v3 = v7++;\n } while (v8 > 9);\n }\n }\n ++v2;\n } while (a2 != v2);\n if (v3 <= 0) {\n return 0;\n } else {\n LABEL_12:\n v9 = v13;\n v10 = 0;\n do\n v10 += *v9++;\n while (&v13[v3] != v9);\n }\n return v10;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n int v2;\n int v3;\n int *v4;\n int v5;\n long long v6;\n long long v7;\n int v8;\n uint32_t *v9;\n unsigned int v10;\n uint32_t v13[1002];\n unsigned long long v14;\n v14 = __readfsqword(40u);\n v13[0] = 1;\n v2 = 0;\n v3 = 1;\n if (a2 <= 0) goto LABEL_12;\n do {\n if (v3 > 0) {\n v4 = v13;\n v5 = 0;\n do {\n v6 = v5 + a1 * (long long)*v4;\n *v4 = v6 % 10;\n v5 = v6 / 10;\n ++v4;\n } while (v4 != &v13[v3]);\n if ((int)(v6 / 10) > 0) {\n v7 = v3 + 1;\n do {\n v13[v7 - 1] = v5 % 10;\n v8 = v5;\n v5 /= 10;\n v3 = v7++;\n } while (v8 > 9);\n }\n }\n ++v2;\n } while (a2 != v2);\n if (v3 <= 0) {\n return 0;\n } else {\n LABEL_12:\n v9 = v13;\n v10 = 0;\n do\n v10 += *v9++;\n while (&v13[v3] != v9);\n }\n return v10;\n}" + }, + { + "index": 724, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int base, int power) {\n int digits[1000];\n int size = 1;\n digits[0] = 1;\n for (int p = 0; p < power; p++) {\n int carry = 0;\n for (int i = 0; i < size; i++) {\n long temp = (long)digits[i] * base + carry;\n digits[i] = temp % 10;\n carry = temp / 10;\n }\n while (carry > 0) {\n digits[size] = carry % 10;\n carry /= 10;\n size++;\n }\n }\n int sum = 0;\n for (int i = 0; i < size; i++) {\n sum += digits[i];\n }\n return sum;\n}", + "test": "int main() {\n\n assert(func0(2, 100) == 115);\n\n assert(func0(8, 10) == 37);\n\n assert(func0(8, 15) == 62);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0xfb0,%rsp\nmov %fs:0x28,%rax\nmov %rax,0xfa8(%rsp)\nxor %eax,%eax\nmovl $0x1,(%rsp)\ntest %esi,%esi\njle 1360 \nmov %esi,%ebp\nmovslq %edi,%r9\nmov $0x1,%ecx\nxor %ebx,%ebx\nmov $0x1,%r12d\nmov %rsp,%r8\nlea 0x4(%rsp),%rsi\nxor %r14d,%r14d\nmovabs $0x6666666666666667,%r11\nmov $0xcccccccd,%r10d\nnopw 0x0(%rax,%rax,1)\nmov %r14d,%eax\nmov %r8,%rdi\nxor %edx,%edx\nlea (%rsi,%rax,4),%r13\njmp 12a3 \nnopw %cs:0x0(%rax,%rax,1)\nmovslq (%rdi),%rcx\nimul %r9,%rcx\nmovslq %edx,%rdx\nadd $0x4,%rdi\nadd %rdx,%rcx\nmov %rcx,%rax\nimul %r11\nmov %rcx,%rax\nsar $0x3f,%rax\nsar $0x2,%rdx\nsub %rax,%rdx\nlea (%rdx,%rdx,4),%rax\nadd %rax,%rax\nsub %rax,%rcx\nmov %ecx,-0x4(%rdi)\ncmp %rdi,%r13\njne 12a0 \ntest %edx,%edx\njle 1317 \nadd $0x1,%r12d\nmovslq %r12d,%rdi\nnopw 0x0(%rax,%rax,1)\nmov %edx,%eax\nmov %edx,%r14d\nmov %edi,%r12d\nimul %r10,%rax\nshr $0x23,%rax\nlea (%rax,%rax,4),%ecx\nadd %ecx,%ecx\nsub %ecx,%r14d\nmov %edx,%ecx\nmov %eax,%edx\nmov %r14d,-0x4(%r8,%rdi,4)\nadd $0x1,%rdi\ncmp $0x9,%ecx\njg 12e8 \nlea -0x1(%r12),%r14d\nadd $0x1,%ebx\nmovslq (%rsp),%rcx\ncmp %ebx,%ebp\njne 1288 \nlea (%rsi,%r14,4),%rdx\nxor %eax,%eax\njmp 1336 \nxchg %ax,%ax\nmov (%rsi),%ecx\nadd $0x4,%rsi\nadd %ecx,%eax\ncmp %rsi,%rdx\njne 1330 \nmov 0xfa8(%rsp),%rbx\nxor %fs:0x28,%rbx\njne 1367 \nadd $0xfb0,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nmov $0x1,%eax\njmp 133d \ncallq 1060 <__stack_chk_fail@plt>\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 0FB8h\nmov rax, fs:28h\nmov [rsp+0FD8h+var_30], rax\nxor eax, eax\nmov [rsp+0FD8h+var_FD8], 1\ntest esi, esi\njle loc_134F\nmovsxd r8, edi\nmov ebx, esi\nxor r11d, r11d\nmov r12d, 1\nmov rdi, rsp\nmov r9d, 0CCCCCCCDh\nmov r10, 6666666666666667h\nnop dword ptr [rax+00h]\nloc_1278:\ntest r12d, r12d\njle loc_12FF\nmovsxd rax, r12d\nmov rbp, rdi\nxor esi, esi\nlea r13, [rdi+rax*4]\nnop dword ptr [rax]\nloc_1290:\nmovsxd rcx, dword ptr [rbp+0]\nadd rbp, 4\nimul rcx, r8\nadd rcx, rsi\nmov rax, rcx\nimul r10\nmov rax, rcx\nsar rax, 3Fh\nsar rdx, 2\nsub rdx, rax\nlea rax, [rdx+rdx*4]\nmovsxd rsi, edx\nadd rax, rax\nsub rcx, rax\nmov [rbp-4], ecx\ncmp rbp, r13\njnz short loc_1290\ntest edx, edx\njle short loc_12FF\nlea edx, [r12+1]\nmovsxd rdx, edx\nnop dword ptr [rax+00h]\nloc_12D8:\nmov eax, esi\nmov ebp, esi\nmov r12, rdx\nimul rax, r9\nshr rax, 23h\nlea ecx, [rax+rax*4]\nadd ecx, ecx\nsub ebp, ecx\nmov ecx, esi\nmov esi, eax\nmov [rdi+rdx*4-4], ebp\nadd rdx, 1\ncmp ecx, 9\njg short loc_12D8\nloc_12FF:\nadd r11d, 1\ncmp ebx, r11d\njnz loc_1278\ntest r12d, r12d\njle short loc_1356\nxor eax, eax\nxor edx, edx\nmov rcx, rsp\nnop dword ptr [rax+rax+00000000h]\nloc_1320:\nadd edx, [rcx+rax*4]\nadd rax, 1\ncmp r12d, eax\njg short loc_1320\nloc_132C:\nmov rax, [rsp+0FD8h+var_30]\nsub rax, fs:28h\njnz short loc_135A\nadd rsp, 0FB8h\nmov eax, edx\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_134F:\nmov edx, 1\njmp short loc_132C\nloc_1356:\nxor edx, edx\njmp short loc_132C\nloc_135A:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n int v3; // r11d\n int v4; // r12d\n _DWORD *v5; // rbp\n __int64 v6; // rsi\n __int64 v7; // rcx\n __int64 v8; // rcx\n __int64 v9; // rdx\n unsigned int v10; // ebp\n int v11; // ecx\n __int64 v12; // rax\n unsigned int v13; // edx\n _DWORD v15[1002]; // [rsp+0h] [rbp-FD8h] BYREF\n unsigned __int64 v16; // [rsp+FA8h] [rbp-30h]\n\n v16 = __readfsqword(0x28u);\n v15[0] = 1;\n if ( a2 <= 0 )\n {\n return 1;\n }\n else\n {\n v3 = 0;\n v4 = 1;\n do\n {\n if ( v4 > 0 )\n {\n v5 = v15;\n v6 = 0LL;\n do\n {\n v7 = (int)*v5++;\n v8 = v6 + a1 * v7;\n v6 = (int)(v8 / 10);\n *(v5 - 1) = v8 % 10;\n }\n while ( v5 != &v15[v4] );\n if ( (int)(v8 / 10) > 0 )\n {\n v9 = v4 + 1;\n do\n {\n v4 = v9;\n v10 = (unsigned int)v6 % 0xA;\n v11 = v6;\n LODWORD(v6) = (unsigned int)v6 / 0xA;\n v15[v9++ - 1] = v10;\n }\n while ( v11 > 9 );\n }\n }\n ++v3;\n }\n while ( a2 != v3 );\n if ( v4 <= 0 )\n {\n return 0;\n }\n else\n {\n v12 = 0LL;\n v13 = 0;\n do\n v13 += v15[v12++];\n while ( v4 > (int)v12 );\n }\n }\n return v13;\n}", + "ida_strip_asm": "sub_1220:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 0FB8h\nmov rax, fs:28h\nmov [rsp+0FD8h+var_30], rax\nxor eax, eax\nmov [rsp+0FD8h+var_FD8], 1\ntest esi, esi\njle loc_134F\nmovsxd r8, edi\nmov ebx, esi\nxor r11d, r11d\nmov r12d, 1\nmov rdi, rsp\nmov r9d, 0CCCCCCCDh\nmov r10, 6666666666666667h\nnop dword ptr [rax+00h]\nloc_1278:\ntest r12d, r12d\njle loc_12FF\nmovsxd rax, r12d\nmov rbp, rdi\nxor esi, esi\nlea r13, [rdi+rax*4]\nnop dword ptr [rax]\nloc_1290:\nmovsxd rcx, dword ptr [rbp+0]\nadd rbp, 4\nimul rcx, r8\nadd rcx, rsi\nmov rax, rcx\nimul r10\nmov rax, rcx\nsar rax, 3Fh\nsar rdx, 2\nsub rdx, rax\nlea rax, [rdx+rdx*4]\nmovsxd rsi, edx\nadd rax, rax\nsub rcx, rax\nmov [rbp-4], ecx\ncmp rbp, r13\njnz short loc_1290\ntest edx, edx\njle short loc_12FF\nlea edx, [r12+1]\nmovsxd rdx, edx\nnop dword ptr [rax+00h]\nloc_12D8:\nmov eax, esi\nmov ebp, esi\nmov r12, rdx\nimul rax, r9\nshr rax, 23h\nlea ecx, [rax+rax*4]\nadd ecx, ecx\nsub ebp, ecx\nmov ecx, esi\nmov esi, eax\nmov [rdi+rdx*4-4], ebp\nadd rdx, 1\ncmp ecx, 9\njg short loc_12D8\nloc_12FF:\nadd r11d, 1\ncmp ebx, r11d\njnz loc_1278\ntest r12d, r12d\njle short loc_1356\nxor eax, eax\nxor edx, edx\nmov rcx, rsp\nnop dword ptr [rax+rax+00000000h]\nloc_1320:\nadd edx, [rcx+rax*4]\nadd rax, 1\ncmp r12d, eax\njg short loc_1320\nloc_132C:\nmov rax, [rsp+0FD8h+var_30]\nsub rax, fs:28h\njnz short loc_135A\nadd rsp, 0FB8h\nmov eax, edx\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_134F:\nmov edx, 1\njmp short loc_132C\nloc_1356:\nxor edx, edx\njmp short loc_132C\nloc_135A:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1220(int a1, int a2)\n{\n int v3; // r11d\n int v4; // r12d\n _DWORD *v5; // rbp\n __int64 v6; // rsi\n __int64 v7; // rcx\n __int64 v8; // rcx\n __int64 v9; // rdx\n unsigned int v10; // ebp\n int v11; // ecx\n __int64 v12; // rax\n unsigned int v13; // edx\n _DWORD v15[1002]; // [rsp+0h] [rbp-FD8h] BYREF\n unsigned __int64 v16; // [rsp+FA8h] [rbp-30h]\n\n v16 = __readfsqword(0x28u);\n v15[0] = 1;\n if ( a2 <= 0 )\n {\n return 1;\n }\n else\n {\n v3 = 0;\n v4 = 1;\n do\n {\n if ( v4 > 0 )\n {\n v5 = v15;\n v6 = 0LL;\n do\n {\n v7 = (int)*v5++;\n v8 = v6 + a1 * v7;\n v6 = (int)(v8 / 10);\n *(v5 - 1) = v8 % 10;\n }\n while ( v5 != &v15[v4] );\n if ( (int)(v8 / 10) > 0 )\n {\n v9 = v4 + 1;\n do\n {\n v4 = v9;\n v10 = (unsigned int)v6 % 0xA;\n v11 = v6;\n LODWORD(v6) = (unsigned int)v6 / 0xA;\n v15[v9++ - 1] = v10;\n }\n while ( v11 > 9 );\n }\n }\n ++v3;\n }\n while ( a2 != v3 );\n if ( v4 <= 0 )\n {\n return 0;\n }\n else\n {\n v12 = 0LL;\n v13 = 0;\n do\n v13 += v15[v12++];\n while ( v4 > (int)v12 );\n }\n }\n return v13;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1220(int a1, int a2) {\n int v3;\n int v4;\n uint32_t *v5;\n long long v6;\n long long v7;\n long long v8;\n long long v9;\n unsigned int v10;\n int v11;\n long long v12;\n unsigned int v13;\n uint32_t v15[1002];\n unsigned long long v16;\n v16 = __readfsqword(40u);\n v15[0] = 1;\n if (a2 <= 0) {\n return 1;\n } else {\n v3 = 0;\n v4 = 1;\n do {\n if (v4 > 0) {\n v5 = v15;\n v6 = 0LL;\n do {\n v7 = (int)*v5++;\n v8 = v6 + a1 * v7;\n v6 = (int)(v8 / 10);\n *(v5 - 1) = v8 % 10;\n } while (v5 != &v15[v4]);\n if ((int)(v8 / 10) > 0) {\n v9 = v4 + 1;\n do {\n v4 = v9;\n v10 = (unsigned int)v6 % 10;\n v11 = v6;\n LODWORD(v6) = (unsigned int)v6 / 10;\n v15[v9++ - 1] = v10;\n } while (v11 > 9);\n }\n }\n ++v3;\n } while (a2 != v3);\n if (v4 <= 0) {\n return 0;\n } else {\n v12 = 0LL;\n v13 = 0;\n do\n v13 += v15[v12++];\n while (v4 > (int)v12);\n }\n }\n return v13;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n int v3;\n int v4;\n uint32_t *v5;\n long long v6;\n long long v7;\n long long v8;\n long long v9;\n unsigned int v10;\n int v11;\n long long v12;\n unsigned int v13;\n uint32_t v15[1002];\n unsigned long long v16;\n v16 = __readfsqword(40u);\n v15[0] = 1;\n if (a2 <= 0) {\n return 1;\n } else {\n v3 = 0;\n v4 = 1;\n do {\n if (v4 > 0) {\n v5 = v15;\n v6 = 0LL;\n do {\n v7 = (int)*v5++;\n v8 = v6 + a1 * v7;\n v6 = (int)(v8 / 10);\n *(v5 - 1) = v8 % 10;\n } while (v5 != &v15[v4]);\n if ((int)(v8 / 10) > 0) {\n v9 = v4 + 1;\n do {\n v4 = v9;\n v10 = (unsigned int)v6 % 10;\n v11 = v6;\n LODWORD(v6) = (unsigned int)v6 / 10;\n v15[v9++ - 1] = v10;\n } while (v11 > 9);\n }\n }\n ++v3;\n } while (a2 != v3);\n if (v4 <= 0) {\n return 0;\n } else {\n v12 = 0LL;\n v13 = 0;\n do\n v13 += v15[v12++];\n while (v4 > (int)v12);\n }\n }\n return v13;\n}" + }, + { + "index": 724, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int base, int power) {\n int digits[1000];\n int size = 1;\n digits[0] = 1;\n for (int p = 0; p < power; p++) {\n int carry = 0;\n for (int i = 0; i < size; i++) {\n long temp = (long)digits[i] * base + carry;\n digits[i] = temp % 10;\n carry = temp / 10;\n }\n while (carry > 0) {\n digits[size] = carry % 10;\n carry /= 10;\n size++;\n }\n }\n int sum = 0;\n for (int i = 0; i < size; i++) {\n sum += digits[i];\n }\n return sum;\n}", + "test": "int main() {\n\n assert(func0(2, 100) == 115);\n\n assert(func0(8, 10) == 37);\n\n assert(func0(8, 15) == 62);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0xfb8,%rsp\nmov %fs:0x28,%rax\nmov %rax,0xfa8(%rsp)\nxor %eax,%eax\nmovl $0x1,(%rsp)\ntest %esi,%esi\njle 13c4 \nmov %esi,%r13d\nmovslq %edi,%r10\nxor %ebp,%ebp\nmov $0x1,%r8d\nmov %rsp,%rdi\nxor %r12d,%r12d\nlea 0x4(%rsp),%r14\nmovabs $0x6666666666666667,%rsi\nmov $0xcccccccd,%r11d\nmov %r12d,%eax\nmov %rdi,%rbx\nmov %rdi,%rcx\nxor %edx,%edx\nlea (%r14,%rax,4),%r9\nmovslq (%rcx),%r15\nmovslq %edx,%rdx\nadd $0x4,%rcx\nimul %r10,%r15\nadd %rdx,%r15\nmov %r15,%rax\nimul %rsi\nmov %r15,%rax\nsar $0x3f,%rax\nsar $0x2,%rdx\nsub %rax,%rdx\nlea (%rdx,%rdx,4),%rax\nadd %rax,%rax\nsub %rax,%r15\nmov %r15d,-0x4(%rcx)\ncmp %r9,%rcx\njne 1290 \ntest %edx,%edx\njle 130a \nadd $0x1,%r8d\nmovslq %r8d,%rcx\nnopl 0x0(%rax,%rax,1)\nmov %edx,%eax\nmov %edx,%r9d\nimul %r11,%rax\nshr $0x23,%rax\nlea (%rax,%rax,4),%r8d\nadd %r8d,%r8d\nsub %r8d,%r9d\nmov %ecx,%r8d\nmov %r9d,-0x4(%rdi,%rcx,4)\nmov %edx,%r9d\nadd $0x1,%rcx\nmov %eax,%edx\ncmp $0x9,%r9d\njg 12d8 \nlea -0x1(%r8),%r12d\nadd $0x1,%ebp\ncmp %ebp,%r13d\njne 1280 \ncmp $0x3,%r12d\njbe 13cb \nmov %r8d,%eax\npxor %xmm0,%xmm0\nshr $0x2,%eax\nshl $0x4,%rax\nadd %rax,%rdi\nnopl 0x0(%rax)\npaddd (%rbx),%xmm0\nadd $0x10,%rbx\ncmp %rdi,%rbx\njne 1338 \nmovdqa %xmm0,%xmm1\nmov %r8d,%edx\npsrldq $0x8,%xmm1\nand $0xfffffffc,%edx\npaddd %xmm1,%xmm0\nmovdqa %xmm0,%xmm1\npsrldq $0x4,%xmm1\npaddd %xmm1,%xmm0\nmovd %xmm0,%eax\ntest $0x3,%r8b\nje 139f \nmovslq %edx,%rcx\nadd (%rsp,%rcx,4),%eax\nlea 0x1(%rdx),%ecx\ncmp %ecx,%r8d\njle 139f \nmovslq %ecx,%rcx\nadd (%rsp,%rcx,4),%eax\nlea 0x2(%rdx),%ecx\ncmp %ecx,%r8d\njle 139f \nmovslq %ecx,%rcx\nadd $0x3,%edx\nadd (%rsp,%rcx,4),%eax\ncmp %r8d,%edx\njge 139f \nmovslq %edx,%rdx\nadd (%rsp,%rdx,4),%eax\nmov 0xfa8(%rsp),%rbx\nxor %fs:0x28,%rbx\njne 13d1 \nadd $0xfb8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmov $0x1,%eax\njmp 139f \nxor %edx,%edx\nxor %eax,%eax\njmp 136f \ncallq 1060 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 0FB0h\nmov rax, fs:28h\nmov [rsp+0FD8h+var_30], rax\nxor eax, eax\nmov [rsp+0FD8h+var_FD8], 1\nmov eax, 1\ntest esi, esi\njle loc_13BB\nmovsxd r8, edi\nmov ebx, esi\nxor r11d, r11d\nmov ebp, 1\nmov rdi, rsp\nmov r13d, 1\nmov r10, 6666666666666667h\nmov r9d, 0CCCCCCCDh\nloc_1280:\nmov rsi, rdi\nlea r12, [rdi+r13*4]\nxor r14d, r14d\nnop word ptr [rax+rax+00h]\nloc_1290:\nmovsxd rcx, dword ptr [rsi]\nadd rsi, 4\nimul rcx, r8\nadd rcx, r14\nmov rax, rcx\nimul r10\nmov rax, rcx\nsar rax, 3Fh\nsar rdx, 2\nsub rdx, rax\nlea rax, [rdx+rdx*4]\nmovsxd r14, edx\nadd rax, rax\nsub rcx, rax\nmov [rsi-4], ecx\ncmp rsi, r12\njnz short loc_1290\ntest edx, edx\njle loc_13F2\nadd ebp, 1\nmovsxd rbp, ebp\nnop dword ptr [rax]\nloc_12D8:\nmov eax, r14d\nmov ecx, r14d\nimul rax, r9\nshr rax, 23h\nlea edx, [rax+rax*4]\nadd edx, edx\nsub ecx, edx\nmov edx, r14d\nmov r14d, eax\nmov rax, rbp\nmov [rdi+rbp*4-4], ecx\nadd rbp, 1\ncmp edx, 9\njg short loc_12D8\nlea edx, [r11+1]\nmov ebp, eax\ncmp ebx, edx\njz short loc_1330\ntest eax, eax\njle short loc_1320\nmovsxd r13, eax\nloc_1314:\nmov r11d, edx\njmp loc_1280\nloc_1320:\nadd r11d, 2\ncmp ebx, r11d\njz loc_1403\nnop dword ptr [rax]\nloc_1330:\ntest ebp, ebp\njle loc_1403\ncmp ebp, 3\njle loc_1407\nmov eax, ebp\npxor xmm0, xmm0\nshr eax, 2\nshl rax, 4\nlea rdx, [rdi+rax]\ntest al, 10h\njnz loc_13DE\nnop word ptr [rax+rax+00h]\nloc_1360:\npaddd xmm0, xmmword ptr [rdi]\nadd rdi, 20h ; ' '\npaddd xmm0, xmmword ptr [rdi-10h]\ncmp rdi, rdx\njnz short loc_1360\nloc_1372:\nmovdqa xmm1, xmm0\nmov edx, ebp\npsrldq xmm1, 8\nand edx, 0FFFFFFFCh\npaddd xmm0, xmm1\nmovdqa xmm1, xmm0\npsrldq xmm1, 4\npaddd xmm0, xmm1\nmovd eax, xmm0\ntest bpl, 3\njz short loc_13BB\nloc_139B:\nmovsxd rcx, edx\nadd eax, [rsp+rcx*4+0FD8h+var_FD8]\nlea ecx, [rdx+1]\ncmp ecx, ebp\njge short loc_13BB\nmovsxd rcx, ecx\nadd edx, 2\nadd eax, [rsp+rcx*4+0FD8h+var_FD8]\ncmp ebp, edx\njle short loc_13BB\nmovsxd rdx, edx\nadd eax, [rsp+rdx*4+0FD8h+var_FD8]\nloc_13BB:\nmov rdx, [rsp+0FD8h+var_30]\nsub rdx, fs:28h\njnz short loc_140D\nadd rsp, 0FB0h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_13DE:\nmovdqa xmm0, xmmword ptr [rdi]\nlea rdi, [rsp+0FD8h+var_FC8]\ncmp rdi, rdx\njnz loc_1360\njmp short loc_1372\nloc_13F2:\nlea edx, [r11+1]\ncmp ebx, edx\njnz loc_1314\njmp loc_1330\nloc_1403:\nxor eax, eax\njmp short loc_13BB\nloc_1407:\nxor edx, edx\nxor eax, eax\njmp short loc_139B\nloc_140D:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n __int64 result; // rax\n __int64 v3; // r8\n int v5; // r11d\n int v6; // ebp\n __m128i *v7; // rdi\n __int64 v8; // r13\n __m128i *v9; // rsi\n __int64 v10; // r14\n __int64 v11; // rcx\n __int64 v12; // rcx\n __int64 v13; // rbp\n unsigned int v14; // ecx\n int v15; // edx\n int v16; // eax\n int v17; // edx\n __m128i v18; // xmm0\n __int64 v19; // rax\n __m128i *v20; // rdx\n __m128i v21; // xmm0\n int v22; // edx\n __m128i v23; // xmm0\n int v24; // ecx\n int v25; // edx\n __m128i v26; // [rsp+0h] [rbp-FD8h] BYREF\n _BYTE v27[3992]; // [rsp+10h] [rbp-FC8h] BYREF\n unsigned __int64 v28; // [rsp+FA8h] [rbp-30h]\n\n v28 = __readfsqword(0x28u);\n v26.m128i_i32[0] = 1;\n result = 1LL;\n if ( a2 <= 0 )\n return result;\n v3 = a1;\n v5 = 0;\n v6 = 1;\n v7 = &v26;\n v8 = 1LL;\n while ( 1 )\n {\n v9 = &v26;\n v10 = 0LL;\n do\n {\n v11 = v9->m128i_i32[0];\n v9 = (__m128i *)((char *)v9 + 4);\n v12 = v10 + v3 * v11;\n v10 = (int)(v12 / 10);\n v9[-1].m128i_i32[3] = v12 % 10;\n }\n while ( v9 != (__m128i *)((char *)&v26 + 4 * v8) );\n if ( (int)(v12 / 10) > 0 )\n break;\n v17 = v5 + 1;\n if ( a2 == v5 + 1 )\n goto LABEL_13;\nLABEL_11:\n v5 = v17;\n }\n v13 = v6 + 1;\n do\n {\n v14 = (unsigned int)v10 % 0xA;\n v15 = v10;\n LODWORD(v10) = (unsigned int)v10 / 0xA;\n v16 = v13;\n v26.m128i_i32[v13++ - 1] = v14;\n }\n while ( v15 > 9 );\n v17 = v5 + 1;\n v6 = v16;\n if ( a2 == v5 + 1 )\n goto LABEL_13;\n if ( v16 > 0 )\n {\n v8 = v16;\n goto LABEL_11;\n }\n if ( a2 == v5 + 2 )\n return 0LL;\nLABEL_13:\n if ( v6 <= 0 )\n return 0LL;\n if ( v6 <= 3 )\n {\n v22 = 0;\n LODWORD(result) = 0;\n goto LABEL_18;\n }\n v18 = 0LL;\n v19 = 16LL * ((unsigned int)v6 >> 2);\n v20 = (__m128i *)((char *)&v26 + v19);\n if ( (v19 & 0x10) == 0 || (v18 = _mm_load_si128(&v26), v7 = (__m128i *)v27, v27 != (_BYTE *)v20) )\n {\n do\n {\n v21 = _mm_add_epi32(v18, *v7);\n v7 += 2;\n v18 = _mm_add_epi32(v21, v7[-1]);\n }\n while ( v7 != v20 );\n }\n v22 = v6 & 0x7FFFFFFC;\n v23 = _mm_add_epi32(v18, _mm_srli_si128(v18, 8));\n result = (unsigned int)_mm_cvtsi128_si32(_mm_add_epi32(v23, _mm_srli_si128(v23, 4)));\n if ( (v6 & 3) != 0 )\n {\nLABEL_18:\n result = (unsigned int)(v26.m128i_i32[v22] + result);\n v24 = v22 + 1;\n if ( v22 + 1 < v6 )\n {\n v25 = v22 + 2;\n result = (unsigned int)(v26.m128i_i32[v24] + result);\n if ( v6 > v25 )\n return (unsigned int)(v26.m128i_i32[v25] + result);\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1220:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 0FB0h\nmov rax, fs:28h\nmov [rsp+0FD8h+var_30], rax\nxor eax, eax\nmov [rsp+0FD8h+var_FD8], 1\nmov eax, 1\ntest esi, esi\njle loc_13BB\nmovsxd r8, edi\nmov ebx, esi\nxor r11d, r11d\nmov ebp, 1\nmov rdi, rsp\nmov r13d, 1\nmov r10, 6666666666666667h\nmov r9d, 0CCCCCCCDh\nloc_1280:\nmov rsi, rdi\nlea r12, [rdi+r13*4]\nxor r14d, r14d\nnop word ptr [rax+rax+00h]\nloc_1290:\nmovsxd rcx, dword ptr [rsi]\nadd rsi, 4\nimul rcx, r8\nadd rcx, r14\nmov rax, rcx\nimul r10\nmov rax, rcx\nsar rax, 3Fh\nsar rdx, 2\nsub rdx, rax\nlea rax, [rdx+rdx*4]\nmovsxd r14, edx\nadd rax, rax\nsub rcx, rax\nmov [rsi-4], ecx\ncmp rsi, r12\njnz short loc_1290\ntest edx, edx\njle loc_13F2\nadd ebp, 1\nmovsxd rbp, ebp\nnop dword ptr [rax]\nloc_12D8:\nmov eax, r14d\nmov ecx, r14d\nimul rax, r9\nshr rax, 23h\nlea edx, [rax+rax*4]\nadd edx, edx\nsub ecx, edx\nmov edx, r14d\nmov r14d, eax\nmov rax, rbp\nmov [rdi+rbp*4-4], ecx\nadd rbp, 1\ncmp edx, 9\njg short loc_12D8\nlea edx, [r11+1]\nmov ebp, eax\ncmp ebx, edx\njz short loc_1330\ntest eax, eax\njle short loc_1320\nmovsxd r13, eax\nloc_1314:\nmov r11d, edx\njmp loc_1280\nloc_1320:\nadd r11d, 2\ncmp ebx, r11d\njz loc_1403\nnop dword ptr [rax]\nloc_1330:\ntest ebp, ebp\njle loc_1403\ncmp ebp, 3\njle loc_1407\nmov eax, ebp\npxor xmm0, xmm0\nshr eax, 2\nshl rax, 4\nlea rdx, [rdi+rax]\ntest al, 10h\njnz loc_13DE\nnop word ptr [rax+rax+00h]\nloc_1360:\npaddd xmm0, xmmword ptr [rdi]\nadd rdi, 20h ; ' '\npaddd xmm0, xmmword ptr [rdi-10h]\ncmp rdi, rdx\njnz short loc_1360\nloc_1372:\nmovdqa xmm1, xmm0\nmov edx, ebp\npsrldq xmm1, 8\nand edx, 0FFFFFFFCh\npaddd xmm0, xmm1\nmovdqa xmm1, xmm0\npsrldq xmm1, 4\npaddd xmm0, xmm1\nmovd eax, xmm0\ntest bpl, 3\njz short loc_13BB\nloc_139B:\nmovsxd rcx, edx\nadd eax, [rsp+rcx*4+0FD8h+var_FD8]\nlea ecx, [rdx+1]\ncmp ecx, ebp\njge short loc_13BB\nmovsxd rcx, ecx\nadd edx, 2\nadd eax, [rsp+rcx*4+0FD8h+var_FD8]\ncmp ebp, edx\njle short loc_13BB\nmovsxd rdx, edx\nadd eax, [rsp+rdx*4+0FD8h+var_FD8]\nloc_13BB:\nmov rdx, [rsp+0FD8h+var_30]\nsub rdx, fs:28h\njnz short loc_140D\nadd rsp, 0FB0h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_13DE:\nmovdqa xmm0, xmmword ptr [rdi]\nlea rdi, [rsp+0FD8h+var_FC8]\ncmp rdi, rdx\njnz loc_1360\njmp short loc_1372\nloc_13F2:\nlea edx, [r11+1]\ncmp ebx, edx\njnz loc_1314\njmp loc_1330\nloc_1403:\nxor eax, eax\njmp short loc_13BB\nloc_1407:\nxor edx, edx\nxor eax, eax\njmp short loc_139B\nloc_140D:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1220(int a1, int a2)\n{\n __int64 result; // rax\n __int64 v3; // r8\n int v5; // r11d\n int v6; // ebp\n __m128i *v7; // rdi\n __int64 v8; // r13\n __m128i *v9; // rsi\n __int64 v10; // r14\n __int64 v11; // rcx\n __int64 v12; // rcx\n __int64 v13; // rbp\n unsigned int v14; // ecx\n int v15; // edx\n int v16; // eax\n int v17; // edx\n __m128i v18; // xmm0\n __int64 v19; // rax\n __m128i *v20; // rdx\n __m128i v21; // xmm0\n int v22; // edx\n __m128i v23; // xmm0\n int v24; // ecx\n int v25; // edx\n __m128i v26; // [rsp+0h] [rbp-FD8h] BYREF\n _BYTE v27[3992]; // [rsp+10h] [rbp-FC8h] BYREF\n unsigned __int64 v28; // [rsp+FA8h] [rbp-30h]\n\n v28 = __readfsqword(0x28u);\n v26.m128i_i32[0] = 1;\n result = 1LL;\n if ( a2 <= 0 )\n return result;\n v3 = a1;\n v5 = 0;\n v6 = 1;\n v7 = &v26;\n v8 = 1LL;\n while ( 1 )\n {\n v9 = &v26;\n v10 = 0LL;\n do\n {\n v11 = v9->m128i_i32[0];\n v9 = (__m128i *)((char *)v9 + 4);\n v12 = v10 + v3 * v11;\n v10 = (int)(v12 / 10);\n v9[-1].m128i_i32[3] = v12 % 10;\n }\n while ( v9 != (__m128i *)((char *)&v26 + 4 * v8) );\n if ( (int)(v12 / 10) > 0 )\n break;\n v17 = v5 + 1;\n if ( a2 == v5 + 1 )\n goto LABEL_13;\nLABEL_11:\n v5 = v17;\n }\n v13 = v6 + 1;\n do\n {\n v14 = (unsigned int)v10 % 0xA;\n v15 = v10;\n LODWORD(v10) = (unsigned int)v10 / 0xA;\n v16 = v13;\n v26.m128i_i32[v13++ - 1] = v14;\n }\n while ( v15 > 9 );\n v17 = v5 + 1;\n v6 = v16;\n if ( a2 == v5 + 1 )\n goto LABEL_13;\n if ( v16 > 0 )\n {\n v8 = v16;\n goto LABEL_11;\n }\n if ( a2 == v5 + 2 )\n return 0LL;\nLABEL_13:\n if ( v6 <= 0 )\n return 0LL;\n if ( v6 <= 3 )\n {\n v22 = 0;\n LODWORD(result) = 0;\n goto LABEL_18;\n }\n v18 = 0LL;\n v19 = 16LL * ((unsigned int)v6 >> 2);\n v20 = (__m128i *)((char *)&v26 + v19);\n if ( (v19 & 0x10) == 0 || (v18 = _mm_load_si128(&v26), v7 = (__m128i *)v27, v27 != (_BYTE *)v20) )\n {\n do\n {\n v21 = _mm_add_epi32(v18, *v7);\n v7 += 2;\n v18 = _mm_add_epi32(v21, v7[-1]);\n }\n while ( v7 != v20 );\n }\n v22 = v6 & 0x7FFFFFFC;\n v23 = _mm_add_epi32(v18, _mm_srli_si128(v18, 8));\n result = (unsigned int)_mm_cvtsi128_si32(_mm_add_epi32(v23, _mm_srli_si128(v23, 4)));\n if ( (v6 & 3) != 0 )\n {\nLABEL_18:\n result = (unsigned int)(v26.m128i_i32[v22] + result);\n v24 = v22 + 1;\n if ( v22 + 1 < v6 )\n {\n v25 = v22 + 2;\n result = (unsigned int)(v26.m128i_i32[v24] + result);\n if ( v6 > v25 )\n return (unsigned int)(v26.m128i_i32[v25] + result);\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1220(int a1, int a2) {\n long long result;\n long long v3;\n int v5;\n int v6;\n __m128i *v7;\n long long v8;\n __m128i *v9;\n long long v10;\n long long v11;\n long long v12;\n long long v13;\n unsigned int v14;\n int v15;\n int v16;\n int v17;\n __m128i v18;\n long long v19;\n __m128i *v20;\n __m128i v21;\n int v22;\n __m128i v23;\n int v24;\n int v25;\n __m128i v26;\n uint8_t v27[3992];\n unsigned long long v28;\n v28 = __readfsqword(40u);\n v26.m128i_i32[0] = 1;\n result = 1LL;\n if (a2 <= 0) return result;\n v3 = a1;\n v5 = 0;\n v6 = 1;\n v7 = &v26;\n v8 = 1LL;\n while (1) {\n v9 = &v26;\n v10 = 0LL;\n do {\n v11 = v9->m128i_i32[0];\n v9 = (__m128i *)((char *)v9 + 4);\n v12 = v10 + v3 * v11;\n v10 = (int)(v12 / 10);\n v9[-1].m128i_i32[3] = v12 % 10;\n } while (v9 != (__m128i *)((char *)&v26 + 4 * v8));\n if ((int)(v12 / 10) > 0) break;\n v17 = v5 + 1;\n if (a2 == v5 + 1) goto LABEL_13;\n LABEL_11:\n v5 = v17;\n }\n v13 = v6 + 1;\n do {\n v14 = (unsigned int)v10 % 10;\n v15 = v10;\n LODWORD(v10) = (unsigned int)v10 / 10;\n v16 = v13;\n v26.m128i_i32[v13++ - 1] = v14;\n } while (v15 > 9);\n v17 = v5 + 1;\n v6 = v16;\n if (a2 == v5 + 1) goto LABEL_13;\n if (v16 > 0) {\n v8 = v16;\n goto LABEL_11;\n }\n if (a2 == v5 + 2) return 0LL;\nLABEL_13:\n if (v6 <= 0) return 0LL;\n if (v6 <= 3) {\n v22 = 0;\n LODWORD(result) = 0;\n goto LABEL_18;\n }\n v18 = 0LL;\n v19 = 16LL * ((unsigned int)v6 >> 2);\n v20 = (__m128i *)((char *)&v26 + v19);\n if ((v19 & 16) == 0 || (v18 = _mm_load_si128(&v26), v7 = (__m128i *)v27,\n v27 != (uint8_t *)v20)) {\n do {\n v21 = _mm_add_epi32(v18, *v7);\n v7 += 2;\n v18 = _mm_add_epi32(v21, v7[-1]);\n } while (v7 != v20);\n }\n v22 = v6 & 2147483644;\n v23 = _mm_add_epi32(v18, _mm_srli_si128(v18, 8));\n result = (unsigned int)_mm_cvtsi128_si32(\n _mm_add_epi32(v23, _mm_srli_si128(v23, 4)));\n if ((v6 & 3) != 0) {\n LABEL_18:\n result = (unsigned int)(v26.m128i_i32[v22] + result);\n v24 = v22 + 1;\n if (v22 + 1 < v6) {\n v25 = v22 + 2;\n result = (unsigned int)(v26.m128i_i32[v24] + result);\n if (v6 > v25) return (unsigned int)(v26.m128i_i32[v25] + result);\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n long long result;\n long long v3;\n int v5;\n int v6;\n __m128i *v7;\n long long v8;\n __m128i *v9;\n long long v10;\n long long v11;\n long long v12;\n long long v13;\n unsigned int v14;\n int v15;\n int v16;\n int v17;\n __m128i v18;\n long long v19;\n __m128i *v20;\n __m128i v21;\n int v22;\n __m128i v23;\n int v24;\n int v25;\n __m128i v26;\n uint8_t v27[3992];\n unsigned long long v28;\n v28 = __readfsqword(40u);\n v26.m128i_i32[0] = 1;\n result = 1LL;\n if (a2 <= 0) return result;\n v3 = a1;\n v5 = 0;\n v6 = 1;\n v7 = &v26;\n v8 = 1LL;\n while (1) {\n v9 = &v26;\n v10 = 0LL;\n do {\n v11 = v9->m128i_i32[0];\n v9 = (__m128i *)((char *)v9 + 4);\n v12 = v10 + v3 * v11;\n v10 = (int)(v12 / 10);\n v9[-1].m128i_i32[3] = v12 % 10;\n } while (v9 != (__m128i *)((char *)&v26 + 4 * v8));\n if ((int)(v12 / 10) > 0) break;\n v17 = v5 + 1;\n if (a2 == v5 + 1) goto LABEL_13;\n LABEL_11:\n v5 = v17;\n }\n v13 = v6 + 1;\n do {\n v14 = (unsigned int)v10 % 10;\n v15 = v10;\n LODWORD(v10) = (unsigned int)v10 / 10;\n v16 = v13;\n v26.m128i_i32[v13++ - 1] = v14;\n } while (v15 > 9);\n v17 = v5 + 1;\n v6 = v16;\n if (a2 == v5 + 1) goto LABEL_13;\n if (v16 > 0) {\n v8 = v16;\n goto LABEL_11;\n }\n if (a2 == v5 + 2) return 0LL;\nLABEL_13:\n if (v6 <= 0) return 0LL;\n if (v6 <= 3) {\n v22 = 0;\n LODWORD(result) = 0;\n goto LABEL_18;\n }\n v18 = 0LL;\n v19 = 16LL * ((unsigned int)v6 >> 2);\n v20 = (__m128i *)((char *)&v26 + v19);\n if ((v19 & 16) == 0 || (v18 = _mm_load_si128(&v26), v7 = (__m128i *)v27,\n v27 != (uint8_t *)v20)) {\n do {\n v21 = _mm_add_epi32(v18, *v7);\n v7 += 2;\n v18 = _mm_add_epi32(v21, v7[-1]);\n } while (v7 != v20);\n }\n v22 = v6 & 2147483644;\n v23 = _mm_add_epi32(v18, _mm_srli_si128(v18, 8));\n result = (unsigned int)_mm_cvtsi128_si32(\n _mm_add_epi32(v23, _mm_srli_si128(v23, 4)));\n if ((v6 & 3) != 0) {\n LABEL_18:\n result = (unsigned int)(v26.m128i_i32[v22] + result);\n v24 = v22 + 1;\n if (v22 + 1 < v6) {\n v25 = v22 + 2;\n result = (unsigned int)(v26.m128i_i32[v24] + result);\n if (v6 > v25) return (unsigned int)(v26.m128i_i32[v25] + result);\n }\n }\n return result;\n}" + }, + { + "index": 725, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char **func0(const char *text1, int *count) {\n char **result = malloc(10 * sizeof(char *));\n *count = 0;\n int result_index = 0;\n const char *start = text1;\n const char *end = text1;\n while (*start) {\n if (*start == '\"') {\n end = ++start;\n while (*end && *end != '\"') ++end;\n int len = end - start;\n char *quoted_text = malloc((len + 1) * sizeof(char));\n strncpy(quoted_text, start, len);\n quoted_text[len] = '\\0';\n result[result_index++] = quoted_text;\n (*count)++;\n if (*end == '\"')\n start = end + 1;\n else\n break;\n }\n else {\n start++;\n }\n }\n return result;\n}", + "test": "int main() {\n\n int count;\n\n char **result;\n\n\n\n result = func0(\"Cortex \\\"A53\\\" Based \\\"multi\\\" tasking \\\"Processor\\\"\", &count);\n\n assert(count == 3);\n\n assert(strcmp(result[0], \"A53\") == 0);\n\n assert(strcmp(result[1], \"multi\") == 0);\n\n assert(strcmp(result[2], \"Processor\") == 0);\n\n\n\n result = func0(\"Cast your \\\"favorite\\\" entertainment \\\"apps\\\"\", &count);\n\n assert(count == 2);\n\n assert(strcmp(result[0], \"favorite\") == 0);\n\n assert(strcmp(result[1], \"apps\") == 0);\n\n\n\n result = func0(\"Watch content \\\"4k Ultra HD\\\" resolution with \\\"HDR 10\\\" Support\", &count);\n\n assert(count == 2);\n\n assert(strcmp(result[0], \"4k Ultra HD\") == 0);\n\n assert(strcmp(result[1], \"HDR 10\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x40,%rsp\nmov %rdi,-0x38(%rbp)\nmov %rsi,-0x40(%rbp)\nmov $0x50,%edi\ncallq 10d0 \nmov %rax,-0x10(%rbp)\nmov -0x40(%rbp),%rax\nmovl $0x0,(%rax)\nmovl $0x0,-0x28(%rbp)\nmov -0x38(%rbp),%rax\nmov %rax,-0x20(%rbp)\nmov -0x38(%rbp),%rax\nmov %rax,-0x18(%rbp)\njmpq 12e0 \nmov -0x20(%rbp),%rax\nmovzbl (%rax),%eax\ncmp $0x22,%al\njne 12db \naddq $0x1,-0x20(%rbp)\nmov -0x20(%rbp),%rax\nmov %rax,-0x18(%rbp)\njmp 1234 \naddq $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%rax\nmovzbl (%rax),%eax\ntest %al,%al\nje 124a \nmov -0x18(%rbp),%rax\nmovzbl (%rax),%eax\ncmp $0x22,%al\njne 122f \nmov -0x18(%rbp),%rax\nsub -0x20(%rbp),%rax\nmov %eax,-0x24(%rbp)\nmov -0x24(%rbp),%eax\nadd $0x1,%eax\ncltq\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,-0x8(%rbp)\nmov -0x24(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x20(%rbp),%rcx\nmov -0x8(%rbp),%rax\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 1090 \nmov -0x24(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmovb $0x0,(%rax)\nmov -0x28(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x28(%rbp)\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x10(%rbp),%rax\nadd %rax,%rdx\nmov -0x8(%rbp),%rax\nmov %rax,(%rdx)\nmov -0x40(%rbp),%rax\nmov (%rax),%eax\nlea 0x1(%rax),%edx\nmov -0x40(%rbp),%rax\nmov %edx,(%rax)\nmov -0x18(%rbp),%rax\nmovzbl (%rax),%eax\ncmp $0x22,%al\njne 12f1 \nmov -0x18(%rbp),%rax\nadd $0x1,%rax\nmov %rax,-0x20(%rbp)\njmp 12e0 \naddq $0x1,-0x20(%rbp)\nmov -0x20(%rbp),%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 1211 \njmp 12f2 \nmov -0x10(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_38], rdi\nmov [rbp+var_40], rsi\nmov edi, 50h ; 'P'; size\ncall _malloc\nmov [rbp+var_10], rax\nmov rax, [rbp+var_40]\nmov dword ptr [rax], 0\nmov [rbp+var_28], 0\nmov rax, [rbp+var_38]\nmov [rbp+src], rax\nmov rax, [rbp+var_38]\nmov [rbp+var_18], rax\njmp loc_12E0\nloc_1211:\nmov rax, [rbp+src]\nmovzx eax, byte ptr [rax]\ncmp al, 22h ; '\"'\njnz loc_12DB\nadd [rbp+src], 1\nmov rax, [rbp+src]\nmov [rbp+var_18], rax\njmp short loc_1234\nloc_122F:\nadd [rbp+var_18], 1\nloc_1234:\nmov rax, [rbp+var_18]\nmovzx eax, byte ptr [rax]\ntest al, al\njz short loc_124A\nmov rax, [rbp+var_18]\nmovzx eax, byte ptr [rax]\ncmp al, 22h ; '\"'\njnz short loc_122F\nloc_124A:\nmov rax, [rbp+var_18]\nsub rax, [rbp+src]\nmov [rbp+var_24], eax\nmov eax, [rbp+var_24]\nadd eax, 1\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+dest], rax\nmov eax, [rbp+var_24]\nmovsxd rdx, eax; n\nmov rcx, [rbp+src]\nmov rax, [rbp+dest]\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strncpy\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, [rbp+dest]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov eax, [rbp+var_28]\nlea edx, [rax+1]\nmov [rbp+var_28], edx\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_10]\nadd rdx, rax\nmov rax, [rbp+dest]\nmov [rdx], rax\nmov rax, [rbp+var_40]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_40]\nmov [rax], edx\nmov rax, [rbp+var_18]\nmovzx eax, byte ptr [rax]\ncmp al, 22h ; '\"'\njnz short loc_12F1\nmov rax, [rbp+var_18]\nadd rax, 1\nmov [rbp+src], rax\njmp short loc_12E0\nloc_12DB:\nadd [rbp+src], 1\nloc_12E0:\nmov rax, [rbp+src]\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_1211\njmp short loc_12F2\nloc_12F1:\nnop\nloc_12F2:\nmov rax, [rbp+var_10]\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(_BYTE *a1, _DWORD *a2)\n{\n int v2; // eax\n int v4; // [rsp+18h] [rbp-28h]\n char *srca; // [rsp+20h] [rbp-20h]\n char *i; // [rsp+28h] [rbp-18h]\n _QWORD *v8; // [rsp+30h] [rbp-10h]\n char *dest; // [rsp+38h] [rbp-8h]\n\n v8 = malloc(0x50uLL);\n *a2 = 0;\n v4 = 0;\n while ( *a1 )\n {\n if ( *a1 == 34 )\n {\n srca = a1 + 1;\n for ( i = srca; *i && *i != 34; ++i )\n ;\n dest = (char *)malloc((int)i - (int)srca + 1);\n strncpy(dest, srca, (int)i - (int)srca);\n dest[(int)i - (int)srca] = 0;\n v2 = v4++;\n v8[v2] = dest;\n ++*a2;\n if ( *i != 34 )\n return v8;\n a1 = i + 1;\n }\n else\n {\n ++a1;\n }\n }\n return v8;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_38], rdi\nmov [rbp+var_40], rsi\nmov edi, 50h ; 'P'; size\ncall _malloc\nmov [rbp+var_10], rax\nmov rax, [rbp+var_40]\nmov dword ptr [rax], 0\nmov [rbp+var_28], 0\nmov rax, [rbp+var_38]\nmov [rbp+src], rax\nmov rax, [rbp+var_38]\nmov [rbp+var_18], rax\njmp loc_12E0\nloc_1211:\nmov rax, [rbp+src]\nmovzx eax, byte ptr [rax]\ncmp al, 22h ; '\"'\njnz loc_12DB\nadd [rbp+src], 1\nmov rax, [rbp+src]\nmov [rbp+var_18], rax\njmp short loc_1234\nloc_122F:\nadd [rbp+var_18], 1\nloc_1234:\nmov rax, [rbp+var_18]\nmovzx eax, byte ptr [rax]\ntest al, al\njz short loc_124A\nmov rax, [rbp+var_18]\nmovzx eax, byte ptr [rax]\ncmp al, 22h ; '\"'\njnz short loc_122F\nloc_124A:\nmov rax, [rbp+var_18]\nsub rax, [rbp+src]\nmov [rbp+var_24], eax\nmov eax, [rbp+var_24]\nadd eax, 1\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+dest], rax\nmov eax, [rbp+var_24]\nmovsxd rdx, eax; n\nmov rcx, [rbp+src]\nmov rax, [rbp+dest]\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strncpy\nmov eax, [rbp+var_24]\nmovsxd rdx, eax\nmov rax, [rbp+dest]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov eax, [rbp+var_28]\nlea edx, [rax+1]\nmov [rbp+var_28], edx\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_10]\nadd rdx, rax\nmov rax, [rbp+dest]\nmov [rdx], rax\nmov rax, [rbp+var_40]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_40]\nmov [rax], edx\nmov rax, [rbp+var_18]\nmovzx eax, byte ptr [rax]\ncmp al, 22h ; '\"'\njnz short loc_12F1\nmov rax, [rbp+var_18]\nadd rax, 1\nmov [rbp+src], rax\njmp short loc_12E0\nloc_12DB:\nadd [rbp+src], 1\nloc_12E0:\nmov rax, [rbp+src]\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_1211\njmp short loc_12F2\nloc_12F1:\nnop\nloc_12F2:\nmov rax, [rbp+var_10]\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11C9(_BYTE *a1, _DWORD *a2)\n{\n int v2; // eax\n int v4; // [rsp+18h] [rbp-28h]\n char *srca; // [rsp+20h] [rbp-20h]\n char *i; // [rsp+28h] [rbp-18h]\n _QWORD *v8; // [rsp+30h] [rbp-10h]\n char *dest; // [rsp+38h] [rbp-8h]\n\n v8 = malloc(0x50uLL);\n *a2 = 0;\n v4 = 0;\n while ( *a1 )\n {\n if ( *a1 == 34 )\n {\n srca = a1 + 1;\n for ( i = srca; *i && *i != 34; ++i )\n ;\n dest = (char *)malloc((int)i - (int)srca + 1);\n strncpy(dest, srca, (int)i - (int)srca);\n dest[(int)i - (int)srca] = 0;\n v2 = v4++;\n v8[v2] = dest;\n ++*a2;\n if ( *i != 34 )\n return v8;\n a1 = i + 1;\n }\n else\n {\n ++a1;\n }\n }\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11C9(uint8_t *a1, uint32_t *a2) {\n int v2;\n int v4;\n char *srca;\n char *i;\n uint64_t *v8;\n char *dest;\n v8 = malloc(80uLL);\n *a2 = 0;\n v4 = 0;\n while (*a1) {\n if (*a1 == 34) {\n srca = a1 + 1;\n for (i = srca; *i && *i != 34; ++i)\n ;\n dest = (char *)malloc((int)i - (int)srca + 1);\n strncpy(dest, srca, (int)i - (int)srca);\n dest[(int)i - (int)srca] = 0;\n v2 = v4++;\n v8[v2] = dest;\n ++*a2;\n if (*i != 34) return v8;\n a1 = i + 1;\n } else {\n ++a1;\n }\n }\n return v8;\n}", + "ida_pseudo_norm": "uint64_t *func0(uint8_t *a1, uint32_t *a2) {\n int v2;\n int v4;\n char *srca;\n char *i;\n uint64_t *v8;\n char *dest;\n v8 = malloc(80uLL);\n *a2 = 0;\n v4 = 0;\n while (*a1) {\n if (*a1 == 34) {\n srca = a1 + 1;\n for (i = srca; *i && *i != 34; ++i)\n ;\n dest = (char *)malloc((int)i - (int)srca + 1);\n strncpy(dest, srca, (int)i - (int)srca);\n dest[(int)i - (int)srca] = 0;\n v2 = v4++;\n v8[v2] = dest;\n ++*a2;\n if (*i != 34) return v8;\n a1 = i + 1;\n } else {\n ++a1;\n }\n }\n return v8;\n}" + }, + { + "index": 725, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char **func0(const char *text1, int *count) {\n char **result = malloc(10 * sizeof(char *));\n *count = 0;\n int result_index = 0;\n const char *start = text1;\n const char *end = text1;\n while (*start) {\n if (*start == '\"') {\n end = ++start;\n while (*end && *end != '\"') ++end;\n int len = end - start;\n char *quoted_text = malloc((len + 1) * sizeof(char));\n strncpy(quoted_text, start, len);\n quoted_text[len] = '\\0';\n result[result_index++] = quoted_text;\n (*count)++;\n if (*end == '\"')\n start = end + 1;\n else\n break;\n }\n else {\n start++;\n }\n }\n return result;\n}", + "test": "int main() {\n\n int count;\n\n char **result;\n\n\n\n result = func0(\"Cortex \\\"A53\\\" Based \\\"multi\\\" tasking \\\"Processor\\\"\", &count);\n\n assert(count == 3);\n\n assert(strcmp(result[0], \"A53\") == 0);\n\n assert(strcmp(result[1], \"multi\") == 0);\n\n assert(strcmp(result[2], \"Processor\") == 0);\n\n\n\n result = func0(\"Cast your \\\"favorite\\\" entertainment \\\"apps\\\"\", &count);\n\n assert(count == 2);\n\n assert(strcmp(result[0], \"favorite\") == 0);\n\n assert(strcmp(result[1], \"apps\") == 0);\n\n\n\n result = func0(\"Watch content \\\"4k Ultra HD\\\" resolution with \\\"HDR 10\\\" Support\", &count);\n\n assert(count == 2);\n\n assert(strcmp(result[0], \"4k Ultra HD\") == 0);\n\n assert(strcmp(result[1], \"HDR 10\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov %rdi,%rbx\nmov %rsi,%r15\nmov $0x50,%edi\ncallq 10b0 \nmov %rax,0x8(%rsp)\nmovl $0x0,(%r15)\nmovzbl (%rbx),%eax\ntest %al,%al\nje 126f \nmov $0x0,%r13d\njmp 1260 \nlea 0x1(%rbx),%r14\nmovzbl 0x1(%rbx),%eax\ntest %al,%al\nje 126a \ncmp $0x22,%al\nje 126a \nmov %r14,%rbx\nadd $0x1,%rbx\nmovzbl (%rbx),%eax\ntest %al,%al\nje 120c \ncmp $0x22,%al\njne 11fd \nmov %rbx,%r12\nsub %r14,%r12\nlea 0x1(%r12),%edi\nmovslq %edi,%rdi\ncallq 10b0 \nmov %rax,%rbp\nmovslq %r12d,%r12\nmov %r12,%rdx\nmov %r14,%rsi\nmov %rax,%rdi\ncallq 1080 \nmovb $0x0,0x0(%rbp,%r12,1)\nlea 0x1(%r13),%eax\nmovslq %r13d,%r13\nmov 0x8(%rsp),%rcx\nmov %rbp,(%rcx,%r13,8)\naddl $0x1,(%r15)\ncmpb $0x22,(%rbx)\njne 126f \nadd $0x1,%rbx\nmov %eax,%r13d\nmovzbl (%rbx),%eax\ntest %al,%al\nje 126f \ncmp $0x22,%al\nje 11ea \nadd $0x1,%rbx\njmp 1259 \nmov %r14,%rbx\njmp 120c \nmov 0x8(%rsp),%rax\nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov rbx, rdi\nmov r15, rsi\nmov edi, 50h ; 'P'; size\ncall _malloc\nmov [rsp+48h+var_40], rax\nmov dword ptr [r15], 0\nmovzx eax, byte ptr [rbx]\ntest al, al\njz loc_12A1\nmov [rsp+48h+var_44], 0\njmp short loc_1220\nloc_120C:\nmov rbx, r14\njmp short loc_1246\nloc_1211:\nadd rbx, 1\nloc_1215:\nmovzx eax, byte ptr [rbx]\ntest al, al\njz loc_12A1\nloc_1220:\ncmp al, 22h ; '\"'\njnz short loc_1211\nlea r14, [rbx+1]\nmovzx eax, byte ptr [rbx+1]\ntest al, al\njz short loc_120C\ncmp al, 22h ; '\"'\njz short loc_120C\nmov rbx, r14\nloc_1237:\nadd rbx, 1\nmovzx eax, byte ptr [rbx]\ntest al, al\njz short loc_1246\ncmp al, 22h ; '\"'\njnz short loc_1237\nloc_1246:\nmov r12, rbx\nsub r12, r14\nlea r13d, [r12+1]\nmovsxd r13, r13d\nmov rdi, r13; size\ncall _malloc\nmov rbp, rax\nmovsxd r12, r12d\nmov rcx, r13\nmov rdx, r12\nmov rsi, r14\nmov rdi, rax\ncall ___strncpy_chk\nmov byte ptr [rbp+r12+0], 0\nmov eax, [rsp+48h+var_44]\nlea edx, [rax+1]\ncdqe\nmov rcx, [rsp+48h+var_40]\nmov [rcx+rax*8], rbp\nadd dword ptr [r15], 1\ncmp byte ptr [rbx], 22h ; '\"'\njnz short loc_12A1\nadd rbx, 1\nmov [rsp+48h+var_44], edx\njmp loc_1215\nloc_12A1:\nmov rax, [rsp+48h+var_40]\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(char *a1, _DWORD *a2)\n{\n char *v2; // rbx\n char v3; // al\n _BYTE *v4; // rbx\n _BYTE *v5; // r14\n char v6; // al\n _BYTE *v7; // rbp\n int v9; // [rsp+4h] [rbp-44h]\n _QWORD *v10; // [rsp+8h] [rbp-40h]\n\n v2 = a1;\n v10 = malloc(0x50uLL);\n *a2 = 0;\n v3 = *a1;\n if ( *a1 )\n {\n v9 = 0;\n do\n {\n if ( v3 == 34 )\n {\n v5 = v2 + 1;\n v6 = v2[1];\n if ( !v6 || v6 == 34 )\n {\n v4 = v2 + 1;\n }\n else\n {\n v4 = v2 + 1;\n do\n ++v4;\n while ( *v4 && *v4 != 34 );\n }\n v7 = malloc((int)v4 - (int)v5 + 1);\n __strncpy_chk(v7, v5, (int)v4 - (int)v5, (int)v4 - (int)v5 + 1);\n v7[(int)v4 - (int)v5] = 0;\n v10[v9] = v7;\n ++*a2;\n if ( *v4 != 34 )\n return v10;\n v2 = v4 + 1;\n ++v9;\n }\n else\n {\n ++v2;\n }\n v3 = *v2;\n }\n while ( *v2 );\n }\n return v10;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov rbx, rdi\nmov r15, rsi\nmov edi, 50h ; 'P'; size\ncall _malloc\nmov [rsp+48h+var_40], rax\nmov dword ptr [r15], 0\nmovzx eax, byte ptr [rbx]\ntest al, al\njz loc_12A1\nmov [rsp+48h+var_44], 0\njmp short loc_1220\nloc_120C:\nmov rbx, r14\njmp short loc_1246\nloc_1211:\nadd rbx, 1\nloc_1215:\nmovzx eax, byte ptr [rbx]\ntest al, al\njz loc_12A1\nloc_1220:\ncmp al, 22h ; '\"'\njnz short loc_1211\nlea r14, [rbx+1]\nmovzx eax, byte ptr [rbx+1]\ntest al, al\njz short loc_120C\ncmp al, 22h ; '\"'\njz short loc_120C\nmov rbx, r14\nloc_1237:\nadd rbx, 1\nmovzx eax, byte ptr [rbx]\ntest al, al\njz short loc_1246\ncmp al, 22h ; '\"'\njnz short loc_1237\nloc_1246:\nmov r12, rbx\nsub r12, r14\nlea r13d, [r12+1]\nmovsxd r13, r13d\nmov rdi, r13; size\ncall _malloc\nmov rbp, rax\nmovsxd r12, r12d\nmov rcx, r13\nmov rdx, r12\nmov rsi, r14\nmov rdi, rax\ncall ___strncpy_chk\nmov byte ptr [rbp+r12+0], 0\nmov eax, [rsp+48h+var_44]\nlea edx, [rax+1]\ncdqe\nmov rcx, [rsp+48h+var_40]\nmov [rcx+rax*8], rbp\nadd dword ptr [r15], 1\ncmp byte ptr [rbx], 22h ; '\"'\njnz short loc_12A1\nadd rbx, 1\nmov [rsp+48h+var_44], edx\njmp loc_1215\nloc_12A1:\nmov rax, [rsp+48h+var_40]\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11C9(char *a1, _DWORD *a2)\n{\n char *v2; // rbx\n char v3; // al\n _BYTE *v4; // rbx\n _BYTE *v5; // r14\n char v6; // al\n _BYTE *v7; // rbp\n int v9; // [rsp+4h] [rbp-44h]\n _QWORD *v10; // [rsp+8h] [rbp-40h]\n\n v2 = a1;\n v10 = malloc(0x50uLL);\n *a2 = 0;\n v3 = *a1;\n if ( *a1 )\n {\n v9 = 0;\n do\n {\n if ( v3 == 34 )\n {\n v5 = v2 + 1;\n v6 = v2[1];\n if ( !v6 || v6 == 34 )\n {\n v4 = v2 + 1;\n }\n else\n {\n v4 = v2 + 1;\n do\n ++v4;\n while ( *v4 && *v4 != 34 );\n }\n v7 = malloc((int)v4 - (int)v5 + 1);\n __strncpy_chk(v7, v5, (int)v4 - (int)v5, (int)v4 - (int)v5 + 1);\n v7[(int)v4 - (int)v5] = 0;\n v10[v9] = v7;\n ++*a2;\n if ( *v4 != 34 )\n return v10;\n v2 = v4 + 1;\n ++v9;\n }\n else\n {\n ++v2;\n }\n v3 = *v2;\n }\n while ( *v2 );\n }\n return v10;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11C9(char *a1, uint32_t *a2) {\n char *v2;\n char v3;\n uint8_t *v4;\n uint8_t *v5;\n char v6;\n uint8_t *v7;\n int v9;\n uint64_t *v10;\n v2 = a1;\n v10 = malloc(80uLL);\n *a2 = 0;\n v3 = *a1;\n if (*a1) {\n v9 = 0;\n do {\n if (v3 == 34) {\n v5 = v2 + 1;\n v6 = v2[1];\n if (!v6 || v6 == 34) {\n v4 = v2 + 1;\n } else {\n v4 = v2 + 1;\n do\n ++v4;\n while (*v4 && *v4 != 34);\n }\n v7 = malloc((int)v4 - (int)v5 + 1);\n __strncpy_chk(v7, v5, (int)v4 - (int)v5, (int)v4 - (int)v5 + 1);\n v7[(int)v4 - (int)v5] = 0;\n v10[v9] = v7;\n ++*a2;\n if (*v4 != 34) return v10;\n v2 = v4 + 1;\n ++v9;\n } else {\n ++v2;\n }\n v3 = *v2;\n } while (*v2);\n }\n return v10;\n}", + "ida_pseudo_norm": "uint64_t *func0(char *a1, uint32_t *a2) {\n char *v2;\n char v3;\n uint8_t *v4;\n uint8_t *v5;\n char v6;\n uint8_t *v7;\n int v9;\n uint64_t *v10;\n v2 = a1;\n v10 = malloc(80uLL);\n *a2 = 0;\n v3 = *a1;\n if (*a1) {\n v9 = 0;\n do {\n if (v3 == 34) {\n v5 = v2 + 1;\n v6 = v2[1];\n if (!v6 || v6 == 34) {\n v4 = v2 + 1;\n } else {\n v4 = v2 + 1;\n do\n ++v4;\n while (*v4 && *v4 != 34);\n }\n v7 = malloc((int)v4 - (int)v5 + 1);\n __strncpy_chk(v7, v5, (int)v4 - (int)v5, (int)v4 - (int)v5 + 1);\n v7[(int)v4 - (int)v5] = 0;\n v10[v9] = v7;\n ++*a2;\n if (*v4 != 34) return v10;\n v2 = v4 + 1;\n ++v9;\n } else {\n ++v2;\n }\n v3 = *v2;\n } while (*v2);\n }\n return v10;\n}" + }, + { + "index": 725, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char **func0(const char *text1, int *count) {\n char **result = malloc(10 * sizeof(char *));\n *count = 0;\n int result_index = 0;\n const char *start = text1;\n const char *end = text1;\n while (*start) {\n if (*start == '\"') {\n end = ++start;\n while (*end && *end != '\"') ++end;\n int len = end - start;\n char *quoted_text = malloc((len + 1) * sizeof(char));\n strncpy(quoted_text, start, len);\n quoted_text[len] = '\\0';\n result[result_index++] = quoted_text;\n (*count)++;\n if (*end == '\"')\n start = end + 1;\n else\n break;\n }\n else {\n start++;\n }\n }\n return result;\n}", + "test": "int main() {\n\n int count;\n\n char **result;\n\n\n\n result = func0(\"Cortex \\\"A53\\\" Based \\\"multi\\\" tasking \\\"Processor\\\"\", &count);\n\n assert(count == 3);\n\n assert(strcmp(result[0], \"A53\") == 0);\n\n assert(strcmp(result[1], \"multi\") == 0);\n\n assert(strcmp(result[2], \"Processor\") == 0);\n\n\n\n result = func0(\"Cast your \\\"favorite\\\" entertainment \\\"apps\\\"\", &count);\n\n assert(count == 2);\n\n assert(strcmp(result[0], \"favorite\") == 0);\n\n assert(strcmp(result[1], \"apps\") == 0);\n\n\n\n result = func0(\"Watch content \\\"4k Ultra HD\\\" resolution with \\\"HDR 10\\\" Support\", &count);\n\n assert(count == 2);\n\n assert(strcmp(result[0], \"4k Ultra HD\") == 0);\n\n assert(strcmp(result[1], \"HDR 10\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmov %rsi,%r15\npush %r14\npush %r13\npush %r12\npush %rbp\nmov %rdi,%rbp\nmov $0x50,%edi\npush %rbx\nsub $0x8,%rsp\ncallq 10b0 \nmovl $0x0,(%r15)\nmov %rax,%r14\nmovzbl 0x0(%rbp),%eax\ntest %al,%al\nje 150e \nxor %r13d,%r13d\njmp 1499 \nnopl (%rax)\nmov %edx,%eax\nmov %r12,%rbp\ntest %al,%al\nje 150e \nmovzbl 0x1(%rbp),%edx\nlea 0x1(%rbp),%r12\ncmp $0x22,%al\njne 1490 \nmov %r12,%rbx\ntest %dl,%dl\nje 1520 \ncmp $0x22,%dl\nje 1520 \nnopl 0x0(%rax)\nmovzbl 0x1(%rbx),%eax\nadd $0x1,%rbx\ntest %al,%al\nje 14c8 \ncmp $0x22,%al\njne 14b8 \nmov %rbx,%rbp\nsub %r12,%rbp\nlea 0x1(%rbp),%edi\nmovslq %ebp,%rbp\nmovslq %edi,%rdi\ncallq 10b0 \nmov %rbp,%rdx\nmov %r12,%rsi\nmov %rax,%rdi\ncallq 1080 \naddl $0x1,(%r15)\ncmpb $0x22,(%rbx)\nlea 0x1(%r13),%edx\nmovb $0x0,(%rax,%rbp,1)\nmov %rax,(%r14,%r13,8)\njne 150e \nmovzbl 0x1(%rbx),%eax\nlea 0x1(%rbx),%rbp\nmovslq %edx,%r13\ntest %al,%al\njne 1499 \nadd $0x8,%rsp\nmov %r14,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nxor %ebp,%ebp\nmov $0x1,%edi\njmp 14d7 \nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14, rsi\npush r13\npush r12\npush rbp\nmov rbp, rdi\nmov edi, 50h ; 'P'; size\npush rbx\nsub rsp, 18h\ncall _malloc\nmov dword ptr [r14], 0\nmov r12, rax\nmovzx eax, byte ptr [rbp+0]\ntest al, al\njz loc_151A\nxor r13d, r13d\njmp short loc_148F\nloc_1480:\nmov rbp, r15\nmovzx eax, byte ptr [rbp+0]\ntest al, al\njz loc_151A\nloc_148F:\nmovzx edx, byte ptr [rbp+1]\nlea r15, [rbp+1]\ncmp al, 22h ; '\"'\njnz short loc_1480\nmov rbx, r15\ntest dl, dl\njz loc_1530\ncmp dl, 22h ; '\"'\njz loc_1530\nnop\nloc_14B0:\nmov rdx, rbx\nmovzx eax, byte ptr [rbx+1]\nadd rbx, 1\ntest al, al\njz short loc_14C3\ncmp al, 22h ; '\"'\njnz short loc_14B0\nloc_14C3:\nsub rdx, rbp\nlea ecx, [rdx+1]\nmovsxd rbp, edx\nmovsxd rcx, ecx\nloc_14CF:\nmov rdi, rcx; size\nmov [rsp+48h+var_40], rcx\ncall _malloc\nmov rcx, [rsp+48h+var_40]\nmov rdx, rbp\nmov rsi, r15\nmov rdi, rax\ncall ___strncpy_chk\nadd dword ptr [r14], 1\ncmp byte ptr [rbx], 22h ; '\"'\nmov rdi, rax\nmov byte ptr [rax+rbp], 0\nlea eax, [r13+1]\nmov [r12+r13*8], rdi\njnz short loc_151A\nlea rbp, [rbx+1]\nmovsxd r13, eax\nmovzx eax, byte ptr [rbp+0]\ntest al, al\njnz loc_148F\nloc_151A:\nadd rsp, 18h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1530:\nxor ebp, ebp\nmov ecx, 1\njmp short loc_14CF", + "ida_pseudo": "_QWORD *__fastcall func0(_BYTE *a1, _DWORD *a2)\n{\n _BYTE *v2; // rbp\n _QWORD *v3; // rax\n _QWORD *v4; // r12\n char v5; // al\n __int64 v6; // r13\n char v7; // dl\n char *v8; // r15\n _BYTE *v9; // rbx\n int v10; // edx\n char v11; // al\n int v12; // edx\n __int64 v13; // rbp\n size_t v14; // rcx\n void *v15; // rax\n __int64 v16; // rax\n bool v17; // zf\n size_t v19; // [rsp+8h] [rbp-40h]\n\n v2 = a1;\n v3 = malloc(0x50uLL);\n *a2 = 0;\n v4 = v3;\n v5 = *a1;\n if ( *a1 )\n {\n v6 = 0LL;\n do\n {\n while ( 1 )\n {\n v7 = v2[1];\n v8 = v2 + 1;\n if ( v5 == 34 )\n break;\n ++v2;\n v5 = *v8;\n if ( !*v8 )\n return v4;\n }\n v9 = v2 + 1;\n if ( !v7 || v7 == 34 )\n {\n v13 = 0LL;\n v14 = 1LL;\n }\n else\n {\n do\n {\n v10 = (int)v9;\n v11 = *++v9;\n }\n while ( v11 && v11 != 34 );\n v12 = v10 - (_DWORD)v2;\n v13 = v12;\n v14 = v12 + 1;\n }\n v19 = v14;\n v15 = malloc(v14);\n v16 = __strncpy_chk(v15, v8, v13, v19);\n ++*a2;\n v17 = *v9 == 34;\n *(_BYTE *)(v16 + v13) = 0;\n v4[v6] = v16;\n if ( !v17 )\n break;\n v2 = v9 + 1;\n v6 = (int)v6 + 1;\n v5 = v9[1];\n }\n while ( v5 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_1440:\nendbr64\npush r15\npush r14\nmov r14, rsi\npush r13\npush r12\npush rbp\nmov rbp, rdi\nmov edi, 50h ; 'P'; size\npush rbx\nsub rsp, 18h\ncall _malloc\nmov dword ptr [r14], 0\nmov r12, rax\nmovzx eax, byte ptr [rbp+0]\ntest al, al\njz loc_151A\nxor r13d, r13d\njmp short loc_148F\nloc_1480:\nmov rbp, r15\nmovzx eax, byte ptr [rbp+0]\ntest al, al\njz loc_151A\nloc_148F:\nmovzx edx, byte ptr [rbp+1]\nlea r15, [rbp+1]\ncmp al, 22h ; '\"'\njnz short loc_1480\nmov rbx, r15\ntest dl, dl\njz loc_1530\ncmp dl, 22h ; '\"'\njz loc_1530\nnop\nloc_14B0:\nmov rdx, rbx\nmovzx eax, byte ptr [rbx+1]\nadd rbx, 1\ntest al, al\njz short loc_14C3\ncmp al, 22h ; '\"'\njnz short loc_14B0\nloc_14C3:\nsub rdx, rbp\nlea ecx, [rdx+1]\nmovsxd rbp, edx\nmovsxd rcx, ecx\nloc_14CF:\nmov rdi, rcx; size\nmov [rsp+48h+var_40], rcx\ncall _malloc\nmov rcx, [rsp+48h+var_40]\nmov rdx, rbp\nmov rsi, r15\nmov rdi, rax\ncall ___strncpy_chk\nadd dword ptr [r14], 1\ncmp byte ptr [rbx], 22h ; '\"'\nmov rdi, rax\nmov byte ptr [rax+rbp], 0\nlea eax, [r13+1]\nmov [r12+r13*8], rdi\njnz short loc_151A\nlea rbp, [rbx+1]\nmovsxd r13, eax\nmovzx eax, byte ptr [rbp+0]\ntest al, al\njnz loc_148F\nloc_151A:\nadd rsp, 18h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1530:\nxor ebp, ebp\nmov ecx, 1\njmp short loc_14CF", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1440(_BYTE *a1, _DWORD *a2)\n{\n _BYTE *v2; // rbp\n _QWORD *v3; // rax\n _QWORD *v4; // r12\n char v5; // al\n __int64 v6; // r13\n char v7; // dl\n char *v8; // r15\n _BYTE *v9; // rbx\n int v10; // edx\n char v11; // al\n int v12; // edx\n __int64 v13; // rbp\n size_t v14; // rcx\n void *v15; // rax\n __int64 v16; // rax\n bool v17; // zf\n size_t v19; // [rsp+8h] [rbp-40h]\n\n v2 = a1;\n v3 = malloc(0x50uLL);\n *a2 = 0;\n v4 = v3;\n v5 = *a1;\n if ( *a1 )\n {\n v6 = 0LL;\n do\n {\n while ( 1 )\n {\n v7 = v2[1];\n v8 = v2 + 1;\n if ( v5 == 34 )\n break;\n ++v2;\n v5 = *v8;\n if ( !*v8 )\n return v4;\n }\n v9 = v2 + 1;\n if ( !v7 || v7 == 34 )\n {\n v13 = 0LL;\n v14 = 1LL;\n }\n else\n {\n do\n {\n v10 = (int)v9;\n v11 = *++v9;\n }\n while ( v11 && v11 != 34 );\n v12 = v10 - (_DWORD)v2;\n v13 = v12;\n v14 = v12 + 1;\n }\n v19 = v14;\n v15 = malloc(v14);\n v16 = __strncpy_chk(v15, v8, v13, v19);\n ++*a2;\n v17 = *v9 == 34;\n *(_BYTE *)(v16 + v13) = 0;\n v4[v6] = v16;\n if ( !v17 )\n break;\n v2 = v9 + 1;\n v6 = (int)v6 + 1;\n v5 = v9[1];\n }\n while ( v5 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1440(uint8_t *a1, uint32_t *a2) {\n uint8_t *v2;\n uint64_t *v3;\n uint64_t *v4;\n char v5;\n long long v6;\n char v7;\n char *v8;\n uint8_t *v9;\n int v10;\n char v11;\n int v12;\n long long v13;\n unsigned int v14;\n void *v15;\n long long v16;\n bool v17;\n unsigned int v19;\n v2 = a1;\n v3 = malloc(80uLL);\n *a2 = 0;\n v4 = v3;\n v5 = *a1;\n if (*a1) {\n v6 = 0LL;\n do {\n while (1) {\n v7 = v2[1];\n v8 = v2 + 1;\n if (v5 == 34) break;\n ++v2;\n v5 = *v8;\n if (!*v8) return v4;\n }\n v9 = v2 + 1;\n if (!v7 || v7 == 34) {\n v13 = 0LL;\n v14 = 1LL;\n } else {\n do {\n v10 = (int)v9;\n v11 = *++v9;\n } while (v11 && v11 != 34);\n v12 = v10 - (uint32_t)v2;\n v13 = v12;\n v14 = v12 + 1;\n }\n v19 = v14;\n v15 = malloc(v14);\n v16 = __strncpy_chk(v15, v8, v13, v19);\n ++*a2;\n v17 = *v9 == 34;\n *(uint8_t *)(v16 + v13) = 0;\n v4[v6] = v16;\n if (!v17) break;\n v2 = v9 + 1;\n v6 = (int)v6 + 1;\n v5 = v9[1];\n } while (v5);\n }\n return v4;\n}", + "ida_pseudo_norm": "uint64_t *func0(uint8_t *a1, uint32_t *a2) {\n uint8_t *v2;\n uint64_t *v3;\n uint64_t *v4;\n char v5;\n long long v6;\n char v7;\n char *v8;\n uint8_t *v9;\n int v10;\n char v11;\n int v12;\n long long v13;\n unsigned int v14;\n void *v15;\n long long v16;\n bool v17;\n unsigned int v19;\n v2 = a1;\n v3 = malloc(80uLL);\n *a2 = 0;\n v4 = v3;\n v5 = *a1;\n if (*a1) {\n v6 = 0LL;\n do {\n while (1) {\n v7 = v2[1];\n v8 = v2 + 1;\n if (v5 == 34) break;\n ++v2;\n v5 = *v8;\n if (!*v8) return v4;\n }\n v9 = v2 + 1;\n if (!v7 || v7 == 34) {\n v13 = 0LL;\n v14 = 1LL;\n } else {\n do {\n v10 = (int)v9;\n v11 = *++v9;\n } while (v11 && v11 != 34);\n v12 = v10 - (uint32_t)v2;\n v13 = v12;\n v14 = v12 + 1;\n }\n v19 = v14;\n v15 = malloc(v14);\n v16 = __strncpy_chk(v15, v8, v13, v19);\n ++*a2;\n v17 = *v9 == 34;\n *(uint8_t *)(v16 + v13) = 0;\n v4[v6] = v16;\n if (!v17) break;\n v2 = v9 + 1;\n v6 = (int)v6 + 1;\n v5 = v9[1];\n } while (v5);\n }\n return v4;\n}" + }, + { + "index": 725, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char **func0(const char *text1, int *count) {\n char **result = malloc(10 * sizeof(char *));\n *count = 0;\n int result_index = 0;\n const char *start = text1;\n const char *end = text1;\n while (*start) {\n if (*start == '\"') {\n end = ++start;\n while (*end && *end != '\"') ++end;\n int len = end - start;\n char *quoted_text = malloc((len + 1) * sizeof(char));\n strncpy(quoted_text, start, len);\n quoted_text[len] = '\\0';\n result[result_index++] = quoted_text;\n (*count)++;\n if (*end == '\"')\n start = end + 1;\n else\n break;\n }\n else {\n start++;\n }\n }\n return result;\n}", + "test": "int main() {\n\n int count;\n\n char **result;\n\n\n\n result = func0(\"Cortex \\\"A53\\\" Based \\\"multi\\\" tasking \\\"Processor\\\"\", &count);\n\n assert(count == 3);\n\n assert(strcmp(result[0], \"A53\") == 0);\n\n assert(strcmp(result[1], \"multi\") == 0);\n\n assert(strcmp(result[2], \"Processor\") == 0);\n\n\n\n result = func0(\"Cast your \\\"favorite\\\" entertainment \\\"apps\\\"\", &count);\n\n assert(count == 2);\n\n assert(strcmp(result[0], \"favorite\") == 0);\n\n assert(strcmp(result[1], \"apps\") == 0);\n\n\n\n result = func0(\"Watch content \\\"4k Ultra HD\\\" resolution with \\\"HDR 10\\\" Support\", &count);\n\n assert(count == 2);\n\n assert(strcmp(result[0], \"4k Ultra HD\") == 0);\n\n assert(strcmp(result[1], \"HDR 10\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmov %rsi,%r15\npush %r14\npush %r13\npush %r12\npush %rbp\nmov %rdi,%rbp\nmov $0x50,%edi\npush %rbx\nsub $0x8,%rsp\ncallq 10b0 \nmovl $0x0,(%r15)\nmov %rax,%r14\nmovzbl 0x0(%rbp),%eax\ntest %al,%al\nje 150e \nxor %r13d,%r13d\njmp 1499 \nnopl (%rax)\nmov %edx,%eax\nmov %r12,%rbp\ntest %al,%al\nje 150e \nmovzbl 0x1(%rbp),%edx\nlea 0x1(%rbp),%r12\ncmp $0x22,%al\njne 1490 \nmov %r12,%rbx\ntest %dl,%dl\nje 1520 \ncmp $0x22,%dl\nje 1520 \nnopl 0x0(%rax)\nmovzbl 0x1(%rbx),%eax\nadd $0x1,%rbx\ntest %al,%al\nje 14c8 \ncmp $0x22,%al\njne 14b8 \nmov %rbx,%rbp\nsub %r12,%rbp\nlea 0x1(%rbp),%edi\nmovslq %ebp,%rbp\nmovslq %edi,%rdi\ncallq 10b0 \nmov %rbp,%rdx\nmov %r12,%rsi\nmov %rax,%rdi\ncallq 1080 \naddl $0x1,(%r15)\ncmpb $0x22,(%rbx)\nlea 0x1(%r13),%edx\nmovb $0x0,(%rax,%rbp,1)\nmov %rax,(%r14,%r13,8)\njne 150e \nmovzbl 0x1(%rbx),%eax\nlea 0x1(%rbx),%rbp\nmovslq %edx,%r13\ntest %al,%al\njne 1499 \nadd $0x8,%rsp\nmov %r14,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nxor %ebp,%ebp\nmov $0x1,%edi\njmp 14d7 \nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14, rsi\npush r13\npush r12\npush rbp\nmov rbp, rdi\nmov edi, 50h ; 'P'; size\npush rbx\nsub rsp, 18h\ncall _malloc\nmov dword ptr [r14], 0\nmov r12, rax\nmovzx eax, byte ptr [rbp+0]\ntest al, al\njz loc_151A\nxor r13d, r13d\njmp short loc_148F\nloc_1480:\nmov rbp, r15\nmovzx eax, byte ptr [rbp+0]\ntest al, al\njz loc_151A\nloc_148F:\nmovzx edx, byte ptr [rbp+1]\nlea r15, [rbp+1]\ncmp al, 22h ; '\"'\njnz short loc_1480\nmov rbx, r15\ntest dl, dl\njz loc_1530\ncmp dl, 22h ; '\"'\njz loc_1530\nnop\nloc_14B0:\nmov rdx, rbx\nmovzx eax, byte ptr [rbx+1]\nadd rbx, 1\ntest al, al\njz short loc_14C3\ncmp al, 22h ; '\"'\njnz short loc_14B0\nloc_14C3:\nsub rdx, rbp\nlea ecx, [rdx+1]\nmovsxd rbp, edx\nmovsxd rcx, ecx\nloc_14CF:\nmov rdi, rcx; size\nmov [rsp+48h+var_40], rcx\ncall _malloc\nmov rcx, [rsp+48h+var_40]\nmov rdx, rbp\nmov rsi, r15\nmov rdi, rax\ncall ___strncpy_chk\nadd dword ptr [r14], 1\ncmp byte ptr [rbx], 22h ; '\"'\nmov rdi, rax\nmov byte ptr [rax+rbp], 0\nlea eax, [r13+1]\nmov [r12+r13*8], rdi\njnz short loc_151A\nlea rbp, [rbx+1]\nmovsxd r13, eax\nmovzx eax, byte ptr [rbp+0]\ntest al, al\njnz loc_148F\nloc_151A:\nadd rsp, 18h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1530:\nxor ebp, ebp\nmov ecx, 1\njmp short loc_14CF", + "ida_pseudo": "_QWORD *__fastcall func0(_BYTE *a1, _DWORD *a2)\n{\n _BYTE *v2; // rbp\n _QWORD *v3; // rax\n _QWORD *v4; // r12\n char v5; // al\n __int64 v6; // r13\n char v7; // dl\n char *v8; // r15\n _BYTE *v9; // rbx\n int v10; // edx\n char v11; // al\n int v12; // edx\n __int64 v13; // rbp\n size_t v14; // rcx\n void *v15; // rax\n __int64 v16; // rax\n bool v17; // zf\n size_t v19; // [rsp+8h] [rbp-40h]\n\n v2 = a1;\n v3 = malloc(0x50uLL);\n *a2 = 0;\n v4 = v3;\n v5 = *a1;\n if ( *a1 )\n {\n v6 = 0LL;\n do\n {\n while ( 1 )\n {\n v7 = v2[1];\n v8 = v2 + 1;\n if ( v5 == 34 )\n break;\n ++v2;\n v5 = *v8;\n if ( !*v8 )\n return v4;\n }\n v9 = v2 + 1;\n if ( !v7 || v7 == 34 )\n {\n v13 = 0LL;\n v14 = 1LL;\n }\n else\n {\n do\n {\n v10 = (int)v9;\n v11 = *++v9;\n }\n while ( v11 && v11 != 34 );\n v12 = v10 - (_DWORD)v2;\n v13 = v12;\n v14 = v12 + 1;\n }\n v19 = v14;\n v15 = malloc(v14);\n v16 = __strncpy_chk(v15, v8, v13, v19);\n ++*a2;\n v17 = *v9 == 34;\n *(_BYTE *)(v16 + v13) = 0;\n v4[v6] = v16;\n if ( !v17 )\n break;\n v2 = v9 + 1;\n v6 = (int)v6 + 1;\n v5 = v9[1];\n }\n while ( v5 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_1440:\nendbr64\npush r15\npush r14\nmov r14, rsi\npush r13\npush r12\npush rbp\nmov rbp, rdi\nmov edi, 50h ; 'P'; size\npush rbx\nsub rsp, 18h\ncall _malloc\nmov dword ptr [r14], 0\nmov r12, rax\nmovzx eax, byte ptr [rbp+0]\ntest al, al\njz loc_151A\nxor r13d, r13d\njmp short loc_148F\nloc_1480:\nmov rbp, r15\nmovzx eax, byte ptr [rbp+0]\ntest al, al\njz loc_151A\nloc_148F:\nmovzx edx, byte ptr [rbp+1]\nlea r15, [rbp+1]\ncmp al, 22h ; '\"'\njnz short loc_1480\nmov rbx, r15\ntest dl, dl\njz loc_1530\ncmp dl, 22h ; '\"'\njz loc_1530\nnop\nloc_14B0:\nmov rdx, rbx\nmovzx eax, byte ptr [rbx+1]\nadd rbx, 1\ntest al, al\njz short loc_14C3\ncmp al, 22h ; '\"'\njnz short loc_14B0\nloc_14C3:\nsub rdx, rbp\nlea ecx, [rdx+1]\nmovsxd rbp, edx\nmovsxd rcx, ecx\nloc_14CF:\nmov rdi, rcx; size\nmov [rsp+48h+var_40], rcx\ncall _malloc\nmov rcx, [rsp+48h+var_40]\nmov rdx, rbp\nmov rsi, r15\nmov rdi, rax\ncall ___strncpy_chk\nadd dword ptr [r14], 1\ncmp byte ptr [rbx], 22h ; '\"'\nmov rdi, rax\nmov byte ptr [rax+rbp], 0\nlea eax, [r13+1]\nmov [r12+r13*8], rdi\njnz short loc_151A\nlea rbp, [rbx+1]\nmovsxd r13, eax\nmovzx eax, byte ptr [rbp+0]\ntest al, al\njnz loc_148F\nloc_151A:\nadd rsp, 18h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1530:\nxor ebp, ebp\nmov ecx, 1\njmp short loc_14CF", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1440(_BYTE *a1, _DWORD *a2)\n{\n _BYTE *v2; // rbp\n _QWORD *v3; // rax\n _QWORD *v4; // r12\n char v5; // al\n __int64 v6; // r13\n char v7; // dl\n char *v8; // r15\n _BYTE *v9; // rbx\n int v10; // edx\n char v11; // al\n int v12; // edx\n __int64 v13; // rbp\n size_t v14; // rcx\n void *v15; // rax\n __int64 v16; // rax\n bool v17; // zf\n size_t v19; // [rsp+8h] [rbp-40h]\n\n v2 = a1;\n v3 = malloc(0x50uLL);\n *a2 = 0;\n v4 = v3;\n v5 = *a1;\n if ( *a1 )\n {\n v6 = 0LL;\n do\n {\n while ( 1 )\n {\n v7 = v2[1];\n v8 = v2 + 1;\n if ( v5 == 34 )\n break;\n ++v2;\n v5 = *v8;\n if ( !*v8 )\n return v4;\n }\n v9 = v2 + 1;\n if ( !v7 || v7 == 34 )\n {\n v13 = 0LL;\n v14 = 1LL;\n }\n else\n {\n do\n {\n v10 = (int)v9;\n v11 = *++v9;\n }\n while ( v11 && v11 != 34 );\n v12 = v10 - (_DWORD)v2;\n v13 = v12;\n v14 = v12 + 1;\n }\n v19 = v14;\n v15 = malloc(v14);\n v16 = __strncpy_chk(v15, v8, v13, v19);\n ++*a2;\n v17 = *v9 == 34;\n *(_BYTE *)(v16 + v13) = 0;\n v4[v6] = v16;\n if ( !v17 )\n break;\n v2 = v9 + 1;\n v6 = (int)v6 + 1;\n v5 = v9[1];\n }\n while ( v5 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1440(uint8_t *a1, uint32_t *a2) {\n uint8_t *v2;\n uint64_t *v3;\n uint64_t *v4;\n char v5;\n long long v6;\n char v7;\n char *v8;\n uint8_t *v9;\n int v10;\n char v11;\n int v12;\n long long v13;\n unsigned int v14;\n void *v15;\n long long v16;\n bool v17;\n unsigned int v19;\n v2 = a1;\n v3 = malloc(80uLL);\n *a2 = 0;\n v4 = v3;\n v5 = *a1;\n if (*a1) {\n v6 = 0LL;\n do {\n while (1) {\n v7 = v2[1];\n v8 = v2 + 1;\n if (v5 == 34) break;\n ++v2;\n v5 = *v8;\n if (!*v8) return v4;\n }\n v9 = v2 + 1;\n if (!v7 || v7 == 34) {\n v13 = 0LL;\n v14 = 1LL;\n } else {\n do {\n v10 = (int)v9;\n v11 = *++v9;\n } while (v11 && v11 != 34);\n v12 = v10 - (uint32_t)v2;\n v13 = v12;\n v14 = v12 + 1;\n }\n v19 = v14;\n v15 = malloc(v14);\n v16 = __strncpy_chk(v15, v8, v13, v19);\n ++*a2;\n v17 = *v9 == 34;\n *(uint8_t *)(v16 + v13) = 0;\n v4[v6] = v16;\n if (!v17) break;\n v2 = v9 + 1;\n v6 = (int)v6 + 1;\n v5 = v9[1];\n } while (v5);\n }\n return v4;\n}", + "ida_pseudo_norm": "uint64_t *func0(uint8_t *a1, uint32_t *a2) {\n uint8_t *v2;\n uint64_t *v3;\n uint64_t *v4;\n char v5;\n long long v6;\n char v7;\n char *v8;\n uint8_t *v9;\n int v10;\n char v11;\n int v12;\n long long v13;\n unsigned int v14;\n void *v15;\n long long v16;\n bool v17;\n unsigned int v19;\n v2 = a1;\n v3 = malloc(80uLL);\n *a2 = 0;\n v4 = v3;\n v5 = *a1;\n if (*a1) {\n v6 = 0LL;\n do {\n while (1) {\n v7 = v2[1];\n v8 = v2 + 1;\n if (v5 == 34) break;\n ++v2;\n v5 = *v8;\n if (!*v8) return v4;\n }\n v9 = v2 + 1;\n if (!v7 || v7 == 34) {\n v13 = 0LL;\n v14 = 1LL;\n } else {\n do {\n v10 = (int)v9;\n v11 = *++v9;\n } while (v11 && v11 != 34);\n v12 = v10 - (uint32_t)v2;\n v13 = v12;\n v14 = v12 + 1;\n }\n v19 = v14;\n v15 = malloc(v14);\n v16 = __strncpy_chk(v15, v8, v13, v19);\n ++*a2;\n v17 = *v9 == 34;\n *(uint8_t *)(v16 + v13) = 0;\n v4[v6] = v16;\n if (!v17) break;\n v2 = v9 + 1;\n v6 = (int)v6 + 1;\n v5 = v9[1];\n } while (v5);\n }\n return v4;\n}" + }, + { + "index": 726, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int* func0(const int* test_tup, int size, int* result_size) {\n static int res[100];\n *result_size = size - 1;\n for (int i = 0; i < *result_size; i++) {\n res[i] = test_tup[i] * test_tup[i + 1];\n }\n return res;\n}", + "test": "int main() {\n\n int result_size;\n\n int* result;\n\n int expected1[] = {5, 35, 56, 80};\n\n int expected2[] = {8, 20, 30, 42};\n\n int expected3[] = {156, 182, 126, 135};\n\n\n\n int test1[] = {1, 5, 7, 8, 10};\n\n int test2[] = {2, 4, 5, 6, 7};\n\n int test3[] = {12, 13, 14, 9, 15};\n\n\n\n result = func0(test1, 5, &result_size);\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected1[i]);\n\n }\n\n\n\n result = func0(test2, 5, &result_size);\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected2[i]);\n\n }\n\n\n\n result = func0(test3, 5, &result_size);\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected3[i]);\n\n }\n\n\n\n printf(\"All tests passed.\\n\");\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmov -0x1c(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x28(%rbp),%rax\nmov %edx,(%rax)\nmovl $0x0,-0x4(%rbp)\njmp 1200 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\nimul %edx,%eax\nmov -0x4(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nlea 0x2e47(%rip),%rdx\nmov %eax,(%rcx,%rdx,1)\naddl $0x1,-0x4(%rbp)\nmov -0x28(%rbp),%rax\nmov (%rax),%eax\ncmp %eax,-0x4(%rbp)\njl 11b1 \nlea 0x2e2e(%rip),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov eax, [rbp+var_1C]\nlea edx, [rax-1]\nmov rax, [rbp+var_28]\nmov [rax], edx\nmov [rbp+var_4], 0\njmp short loc_1200\nloc_11B1:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nimul eax, edx\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nlea rdx, res_1\nmov [rcx+rdx], eax\nadd [rbp+var_4], 1\nloc_1200:\nmov rax, [rbp+var_28]\nmov eax, [rax]\ncmp [rbp+var_4], eax\njl short loc_11B1\nlea rax, res_1\npop rbp\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, _DWORD *a3)\n{\n int i; // [rsp+24h] [rbp-4h]\n\n *a3 = a2 - 1;\n for ( i = 0; i < *a3; ++i )\n res_1[i] = *(_DWORD *)(4LL * i + a1) * *(_DWORD *)(4 * (i + 1LL) + a1);\n return res_1;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov eax, [rbp+var_1C]\nlea edx, [rax-1]\nmov rax, [rbp+var_28]\nmov [rax], edx\nmov [rbp+var_4], 0\njmp short loc_1200\nloc_11B1:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nimul eax, edx\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nlea rdx, unk_4040\nmov [rcx+rdx], eax\nadd [rbp+var_4], 1\nloc_1200:\nmov rax, [rbp+var_28]\nmov eax, [rax]\ncmp [rbp+var_4], eax\njl short loc_11B1\nlea rax, unk_4040\npop rbp\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1189(__int64 a1, int a2, _DWORD *a3)\n{\n int i; // [rsp+24h] [rbp-4h]\n\n *a3 = a2 - 1;\n for ( i = 0; i < *a3; ++i )\n dword_4040[i] = *(_DWORD *)(4LL * i + a1) * *(_DWORD *)(4 * (i + 1LL) + a1);\n return dword_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1189(long long a1, int a2, uint32_t *a3) {\n int i;\n *a3 = a2 - 1;\n for (i = 0; i < *a3; ++i)\n dword_4040[i] =\n *(uint32_t *)(4LL * i + a1) * *(uint32_t *)(4 * (i + 1LL) + a1);\n return dword_4040;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, uint32_t *a3) {\n int i;\n *a3 = a2 - 1;\n for (i = 0; i < *a3; ++i)\n res_1[i] = *(uint32_t *)(4LL * i + a1) * *(uint32_t *)(4 * (i + 1LL) + a1);\n return res_1;\n}" + }, + { + "index": 726, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int* func0(const int* test_tup, int size, int* result_size) {\n static int res[100];\n *result_size = size - 1;\n for (int i = 0; i < *result_size; i++) {\n res[i] = test_tup[i] * test_tup[i + 1];\n }\n return res;\n}", + "test": "int main() {\n\n int result_size;\n\n int* result;\n\n int expected1[] = {5, 35, 56, 80};\n\n int expected2[] = {8, 20, 30, 42};\n\n int expected3[] = {156, 182, 126, 135};\n\n\n\n int test1[] = {1, 5, 7, 8, 10};\n\n int test2[] = {2, 4, 5, 6, 7};\n\n int test3[] = {12, 13, 14, 9, 15};\n\n\n\n result = func0(test1, 5, &result_size);\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected1[i]);\n\n }\n\n\n\n result = func0(test2, 5, &result_size);\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected2[i]);\n\n }\n\n\n\n result = func0(test3, 5, &result_size);\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected3[i]);\n\n }\n\n\n\n printf(\"All tests passed.\\n\");\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x1,%esi\nmov %esi,(%rdx)\ntest %esi,%esi\njle 11b5 \nmov $0x0,%eax\nlea 0x2e9e(%rip),%rsi\nmov (%rdi,%rax,4),%ecx\nimul 0x4(%rdi,%rax,4),%ecx\nmov %ecx,(%rsi,%rax,4)\nadd $0x1,%rax\ncmp %eax,(%rdx)\njg 11a2 \nlea 0x2e84(%rip),%rax\nretq\n", + "ida_asm": "func0:\nendbr64\nsub esi, 1\nmov [rdx], esi\ntest esi, esi\njle short loc_11B5\nmov eax, 0\nlea rsi, res_1\nloc_11A2:\nmov ecx, [rdi+rax*4]\nimul ecx, [rdi+rax*4+4]\nmov [rsi+rax*4], ecx\nadd rax, 1\ncmp [rdx], eax\njg short loc_11A2\nloc_11B5:\nlea rax, res_1\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, int *a3)\n{\n int v3; // esi\n __int64 v4; // rax\n\n v3 = a2 - 1;\n *a3 = v3;\n if ( v3 > 0 )\n {\n v4 = 0LL;\n do\n {\n res_1[v4] = *(_DWORD *)(a1 + 4 * v4 + 4) * *(_DWORD *)(a1 + 4 * v4);\n ++v4;\n }\n while ( *a3 > (int)v4 );\n }\n return res_1;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\nsub esi, 1\nmov [rdx], esi\ntest esi, esi\njle short loc_11B5\nmov eax, 0\nlea rsi, unk_4040\nloc_11A2:\nmov ecx, [rdi+rax*4]\nimul ecx, [rdi+rax*4+4]\nmov [rsi+rax*4], ecx\nadd rax, 1\ncmp [rdx], eax\njg short loc_11A2\nloc_11B5:\nlea rax, unk_4040\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1189(__int64 a1, int a2, int *a3)\n{\n int v3; // esi\n __int64 v4; // rax\n\n v3 = a2 - 1;\n *a3 = v3;\n if ( v3 > 0 )\n {\n v4 = 0LL;\n do\n {\n dword_4040[v4] = *(_DWORD *)(a1 + 4 * v4 + 4) * *(_DWORD *)(a1 + 4 * v4);\n ++v4;\n }\n while ( *a3 > (int)v4 );\n }\n return dword_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1189(long long a1, int a2, int *a3) {\n int v3;\n long long v4;\n v3 = a2 - 1;\n *a3 = v3;\n if (v3 > 0) {\n v4 = 0LL;\n do {\n dword_4040[v4] =\n *(uint32_t *)(a1 + 4 * v4 + 4) * *(uint32_t *)(a1 + 4 * v4);\n ++v4;\n } while (*a3 > (int)v4);\n }\n return dword_4040;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, int *a3) {\n int v3;\n long long v4;\n v3 = a2 - 1;\n *a3 = v3;\n if (v3 > 0) {\n v4 = 0LL;\n do {\n res_1[v4] = *(uint32_t *)(a1 + 4 * v4 + 4) * *(uint32_t *)(a1 + 4 * v4);\n ++v4;\n } while (*a3 > (int)v4);\n }\n return res_1;\n}" + }, + { + "index": 726, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int* func0(const int* test_tup, int size, int* result_size) {\n static int res[100];\n *result_size = size - 1;\n for (int i = 0; i < *result_size; i++) {\n res[i] = test_tup[i] * test_tup[i + 1];\n }\n return res;\n}", + "test": "int main() {\n\n int result_size;\n\n int* result;\n\n int expected1[] = {5, 35, 56, 80};\n\n int expected2[] = {8, 20, 30, 42};\n\n int expected3[] = {156, 182, 126, 135};\n\n\n\n int test1[] = {1, 5, 7, 8, 10};\n\n int test2[] = {2, 4, 5, 6, 7};\n\n int test3[] = {12, 13, 14, 9, 15};\n\n\n\n result = func0(test1, 5, &result_size);\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected1[i]);\n\n }\n\n\n\n result = func0(test2, 5, &result_size);\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected2[i]);\n\n }\n\n\n\n result = func0(test3, 5, &result_size);\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected3[i]);\n\n }\n\n\n\n printf(\"All tests passed.\\n\");\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x1,%esi\nmov %esi,(%rdx)\ntest %esi,%esi\njle 11c3 \nxor %eax,%eax\nlea 0x2e9a(%rip),%rsi\nnopw %cs:0x0(%rax,%rax,1)\nmov (%rdi,%rax,4),%ecx\nimul 0x4(%rdi,%rax,4),%ecx\nmov %ecx,(%rsi,%rax,4)\nadd $0x1,%rax\ncmp %eax,(%rdx)\njg 11b0 \nlea 0x2e76(%rip),%rax\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nsub esi, 1\nlea r8, res_1\nmov [rdx], esi\ntest esi, esi\njle short loc_1394\nxor eax, eax\nnop word ptr [rax+rax+00000000h]\nloc_1380:\nmov ecx, [rdi+rax*4]\nimul ecx, [rdi+rax*4+4]\nmov [r8+rax*4], ecx\nadd rax, 1\ncmp [rdx], eax\njg short loc_1380\nloc_1394:\nmov rax, r8\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, int *a3)\n{\n int v3; // esi\n __int64 v4; // rax\n\n v3 = a2 - 1;\n *a3 = v3;\n if ( v3 > 0 )\n {\n v4 = 0LL;\n do\n {\n res_1[v4] = *(_DWORD *)(a1 + 4 * v4 + 4) * *(_DWORD *)(a1 + 4 * v4);\n ++v4;\n }\n while ( *a3 > (int)v4 );\n }\n return res_1;\n}", + "ida_strip_asm": "sub_1360:\nendbr64\nsub esi, 1\nlea r8, unk_4040\nmov [rdx], esi\ntest esi, esi\njle short loc_1394\nxor eax, eax\nnop word ptr [rax+rax+00000000h]\nloc_1380:\nmov ecx, [rdi+rax*4]\nimul ecx, [rdi+rax*4+4]\nmov [r8+rax*4], ecx\nadd rax, 1\ncmp [rdx], eax\njg short loc_1380\nloc_1394:\nmov rax, r8\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1360(__int64 a1, int a2, int *a3)\n{\n int v3; // esi\n __int64 v4; // rax\n\n v3 = a2 - 1;\n *a3 = v3;\n if ( v3 > 0 )\n {\n v4 = 0LL;\n do\n {\n dword_4040[v4] = *(_DWORD *)(a1 + 4 * v4 + 4) * *(_DWORD *)(a1 + 4 * v4);\n ++v4;\n }\n while ( *a3 > (int)v4 );\n }\n return dword_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1360(long long a1, int a2, int *a3) {\n int v3;\n long long v4;\n v3 = a2 - 1;\n *a3 = v3;\n if (v3 > 0) {\n v4 = 0LL;\n do {\n dword_4040[v4] =\n *(uint32_t *)(a1 + 4 * v4 + 4) * *(uint32_t *)(a1 + 4 * v4);\n ++v4;\n } while (*a3 > (int)v4);\n }\n return dword_4040;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, int *a3) {\n int v3;\n long long v4;\n v3 = a2 - 1;\n *a3 = v3;\n if (v3 > 0) {\n v4 = 0LL;\n do {\n res_1[v4] = *(uint32_t *)(a1 + 4 * v4 + 4) * *(uint32_t *)(a1 + 4 * v4);\n ++v4;\n } while (*a3 > (int)v4);\n }\n return res_1;\n}" + }, + { + "index": 727, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* S) {\n static char result[100];\n int j = 0;\n for (int i = 0; i < strlen(S); i++) {\n if (isalnum(S[i])) {\n result[j++] = S[i];\n }\n }\n result[j] = '\\0';\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"123abcjw:, .@! eiw\"), \"123abcjweiw\") == 0);\n\n assert(strcmp(func0(\"Hello1234:, ! Howare33u\"), \"Hello1234Howare33u\") == 0);\n\n assert(strcmp(func0(\"Cool543Triks@:, Make@987Trips\"), \"Cool543TriksMake987Trips\") == 0);\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x28,%rsp\nmov %rdi,-0x28(%rbp)\nmovl $0x0,-0x18(%rbp)\nmovl $0x0,-0x14(%rbp)\njmp 1223 \ncallq 10b0 <__ctype_b_loc@plt>\nmov (%rax),%rax\nmov -0x14(%rbp),%edx\nmovslq %edx,%rcx\nmov -0x28(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rdx),%edx\nmovsbq %dl,%rdx\nadd %rdx,%rdx\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x8,%eax\ntest %eax,%eax\nje 121f \nmov -0x14(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x18(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x18(%rbp)\nmovzbl (%rcx),%edx\ncltq\nlea 0x2e24(%rip),%rcx\nmov %dl,(%rax,%rcx,1)\naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\nmovslq %eax,%rbx\nmov -0x28(%rbp),%rax\nmov %rax,%rdi\ncallq 1080 \ncmp %rax,%rbx\njb 11ca \nmov -0x18(%rbp),%eax\ncltq\nlea 0x2dfa(%rip),%rdx\nmovb $0x0,(%rax,%rdx,1)\nlea 0x2def(%rip),%rax\nadd $0x28,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+s], rdi\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp short loc_1223\nloc_11CA:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_14]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 8\ntest eax, eax\njz short loc_121F\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\nmovzx edx, byte ptr [rcx]\ncdqe\nlea rcx, result_1\nmov [rax+rcx], dl\nloc_121F:\nadd [rbp+var_14], 1\nloc_1223:\nmov eax, [rbp+var_14]\nmovsxd rbx, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rbx, rax\njb short loc_11CA\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, result_1\nmov byte ptr [rax+rdx], 0\nlea rax, result_1\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1)\n{\n int v1; // eax\n int v3; // [rsp+18h] [rbp-18h]\n int i; // [rsp+1Ch] [rbp-14h]\n\n v3 = 0;\n for ( i = 0; i < strlen(a1); ++i )\n {\n if ( ((*__ctype_b_loc())[a1[i]] & 8) != 0 )\n {\n v1 = v3++;\n result_1[v1] = a1[i];\n }\n }\n result_1[v3] = 0;\n return result_1;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+s], rdi\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp short loc_1223\nloc_11CA:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_14]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 8\ntest eax, eax\njz short loc_121F\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_18]\nlea edx, [rax+1]\nmov [rbp+var_18], edx\nmovzx edx, byte ptr [rcx]\ncdqe\nlea rcx, unk_4040\nmov [rax+rcx], dl\nloc_121F:\nadd [rbp+var_14], 1\nloc_1223:\nmov eax, [rbp+var_14]\nmovsxd rbx, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rbx, rax\njb short loc_11CA\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, unk_4040\nmov byte ptr [rax+rdx], 0\nlea rax, unk_4040\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_11A9(const char *a1)\n{\n int v1; // eax\n int v3; // [rsp+18h] [rbp-18h]\n int i; // [rsp+1Ch] [rbp-14h]\n\n v3 = 0;\n for ( i = 0; i < strlen(a1); ++i )\n {\n if ( ((*__ctype_b_loc())[a1[i]] & 8) != 0 )\n {\n v1 = v3++;\n byte_4040[v1] = a1[i];\n }\n }\n byte_4040[v3] = 0;\n return byte_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_11A9(const char *a1) {\n int v1;\n int v3;\n int i;\n v3 = 0;\n for (i = 0; i < strlen(a1); ++i) {\n if (((*__ctype_b_loc())[a1[i]] & 8) != 0) {\n v1 = v3++;\n byte_4040[v1] = a1[i];\n }\n }\n byte_4040[v3] = 0;\n return byte_4040;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1) {\n int v1;\n int v3;\n int i;\n v3 = 0;\n for (i = 0; i < strlen(a1); ++i) {\n if (((*__ctype_b_loc())[a1[i]] & 8) != 0) {\n v1 = v3++;\n result_1[v1] = a1[i];\n }\n }\n result_1[v3] = 0;\n return result_1;\n}" + }, + { + "index": 727, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* S) {\n static char result[100];\n int j = 0;\n for (int i = 0; i < strlen(S); i++) {\n if (isalnum(S[i])) {\n result[j++] = S[i];\n }\n }\n result[j] = '\\0';\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"123abcjw:, .@! eiw\"), \"123abcjweiw\") == 0);\n\n assert(strcmp(func0(\"Hello1234:, ! Howare33u\"), \"Hello1234Howare33u\") == 0);\n\n assert(strcmp(func0(\"Cool543Triks@:, Make@987Trips\"), \"Cool543TriksMake987Trips\") == 0);\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbp\nmov $0x0,%ebx\nmov $0x0,%r12d\nmov $0xffffffffffffffff,%r14\nmov $0x0,%r13d\nlea 0x2ea3(%rip),%r15\njmp 11a3 \nadd $0x1,%rbx\nmov %r14,%rcx\nmov %rbp,%rdi\nmov %r13d,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nsub $0x1,%rcx\ncmp %rbx,%rcx\njbe 11e2 \ncallq 1070 <__ctype_b_loc@plt>\nmov %rax,%rdx\nmovzbl 0x0(%rbp,%rbx,1),%eax\nmovsbq %al,%rcx\nmov (%rdx),%rdx\ntestb $0x8,(%rdx,%rcx,2)\nje 119f \nmovslq %r12d,%rdx\nmov %al,(%r15,%rdx,1)\nlea 0x1(%r12),%r12d\njmp 119f \nlea 0x2e57(%rip),%rax\nmovslq %r12d,%r12\nmovb $0x0,(%rax,%r12,1)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov ebx, 0\nmov r12d, 0\nlea r13, result_1\njmp short loc_11D2\nloc_11CE:\nadd rbx, 1\nloc_11D2:\nmov rdi, rbp; s\ncall _strlen\ncmp rbx, rax\njnb short loc_1208\ncall ___ctype_b_loc\nmov rdx, rax\nmovzx eax, byte ptr [rbp+rbx+0]\nmovsx rcx, al\nmov rdx, [rdx]\ntest byte ptr [rdx+rcx*2], 8\njz short loc_11CE\nmovsxd rdx, r12d\nmov [r13+rdx+0], al\nlea r12d, [r12+1]\njmp short loc_11CE\nloc_1208:\nlea rax, result_1\nmovsxd r12, r12d\nmov byte ptr [rax+r12], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(char *s)\n{\n size_t v1; // rbx\n int v2; // r12d\n const unsigned __int16 **v3; // rdx\n char v4; // al\n _BYTE *result; // rax\n\n v1 = 0LL;\n v2 = 0;\n while ( v1 < strlen(s) )\n {\n v3 = __ctype_b_loc();\n v4 = s[v1];\n if ( ((*v3)[v4] & 8) != 0 )\n result_1[v2++] = v4;\n ++v1;\n }\n result = result_1;\n result_1[v2] = 0;\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov ebx, 0\nmov r12d, 0\nlea r13, unk_4040\njmp short loc_11D2\nloc_11CE:\nadd rbx, 1\nloc_11D2:\nmov rdi, rbp; s\ncall _strlen\ncmp rbx, rax\njnb short loc_1208\ncall ___ctype_b_loc\nmov rdx, rax\nmovzx eax, byte ptr [rbp+rbx+0]\nmovsx rcx, al\nmov rdx, [rdx]\ntest byte ptr [rdx+rcx*2], 8\njz short loc_11CE\nmovsxd rdx, r12d\nmov [r13+rdx+0], al\nlea r12d, [r12+1]\njmp short loc_11CE\nloc_1208:\nlea rax, unk_4040\nmovsxd r12, r12d\nmov byte ptr [rax+r12], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_11A9(char *s)\n{\n size_t v1; // rbx\n int v2; // r12d\n const unsigned __int16 **v3; // rdx\n char v4; // al\n _BYTE *result; // rax\n\n v1 = 0LL;\n v2 = 0;\n while ( v1 < strlen(s) )\n {\n v3 = __ctype_b_loc();\n v4 = s[v1];\n if ( ((*v3)[v4] & 8) != 0 )\n byte_4040[v2++] = v4;\n ++v1;\n }\n result = byte_4040;\n byte_4040[v2] = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_11A9(char *s) {\n unsigned int v1;\n int v2;\n const unsigned short **v3;\n char v4;\n uint8_t *result;\n v1 = 0LL;\n v2 = 0;\n while (v1 < strlen(s)) {\n v3 = __ctype_b_loc();\n v4 = s[v1];\n if (((*v3)[v4] & 8) != 0) byte_4040[v2++] = v4;\n ++v1;\n }\n result = byte_4040;\n byte_4040[v2] = 0;\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(char *s) {\n unsigned int v1;\n int v2;\n const unsigned short **v3;\n char v4;\n uint8_t *result;\n v1 = 0LL;\n v2 = 0;\n while (v1 < strlen(s)) {\n v3 = __ctype_b_loc();\n v4 = s[v1];\n if (((*v3)[v4] & 8) != 0) result_1[v2++] = v4;\n ++v1;\n }\n result = result_1;\n result_1[v2] = 0;\n return result;\n}" + }, + { + "index": 727, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* S) {\n static char result[100];\n int j = 0;\n for (int i = 0; i < strlen(S); i++) {\n if (isalnum(S[i])) {\n result[j++] = S[i];\n }\n }\n result[j] = '\\0';\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"123abcjw:, .@! eiw\"), \"123abcjweiw\") == 0);\n\n assert(strcmp(func0(\"Hello1234:, ! Howare33u\"), \"Hello1234Howare33u\") == 0);\n\n assert(strcmp(func0(\"Cool543Triks@:, Make@987Trips\"), \"Cool543TriksMake987Trips\") == 0);\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nlea 0x2dc3(%rip),%r15\npush %r14\npush %r13\nmov %rdi,%r13\npush %r12\npush %rbp\nxor %ebp,%ebp\npush %rbx\nxor %ebx,%ebx\nsub $0x8,%rsp\ncallq 1070 \nmov %rax,%r12\njmp 12d1 \nnopw 0x0(%rax,%rax,1)\ncallq 1090 <__ctype_b_loc@plt>\nmovsbq 0x0(%r13,%rbx,1),%rcx\nmov %rax,%r8\nmov (%r8),%rdx\ntestb $0x8,(%rdx,%rcx,2)\nje 12cd \nmov %r13,%rdi\nmov %cl,(%r15,%rbp,1)\nlea 0x1(%rbp),%r14d\ncallq 1070 \nmovslq %r14d,%rbp\nmov %rax,%r12\nadd $0x1,%rbx\ncmp %r12,%rbx\njb 12a0 \nmovb $0x0,(%r15,%rbp,1)\nadd $0x8,%rsp\nlea 0x2d5a(%rip),%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r13\nlea r13, result_1\npush r12\nxor r12d, r12d\npush rbp\nmov rbp, rdi\npush rbx\nxor ebx, ebx\nsub rsp, 8\njmp short loc_12C7\nloc_12A0:\ncall ___ctype_b_loc\nmovsx rcx, byte ptr [rbp+rbx+0]\nmov rdx, rax\nmov rdx, [rdx]\ntest byte ptr [rdx+rcx*2], 8\njz short loc_12C3\nmovsxd rdx, r12d\nadd r12d, 1\nmov [r13+rdx+0], cl\nloc_12C3:\nadd rbx, 1\nloc_12C7:\nmov rdi, rbp; s\ncall _strlen\ncmp rbx, rax\njb short loc_12A0\nmovsxd r12, r12d\nmov rax, r13\nmov byte ptr [r13+r12+0], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(char *s)\n{\n int v1; // r12d\n size_t i; // rbx\n const unsigned __int16 **v3; // rax\n __int64 v4; // rcx\n __int64 v5; // rdx\n _BYTE *result; // rax\n\n v1 = 0;\n for ( i = 0LL; i < strlen(s); ++i )\n {\n v3 = __ctype_b_loc();\n v4 = s[i];\n if ( ((*v3)[v4] & 8) != 0 )\n {\n v5 = v1++;\n result_1[v5] = v4;\n }\n }\n result = result_1;\n result_1[v1] = 0;\n return result;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\npush r13\nlea r13, unk_4040\npush r12\nxor r12d, r12d\npush rbp\nmov rbp, rdi\npush rbx\nxor ebx, ebx\nsub rsp, 8\njmp short loc_12C7\nloc_12A0:\ncall ___ctype_b_loc\nmovsx rcx, byte ptr [rbp+rbx+0]\nmov rdx, rax\nmov rdx, [rdx]\ntest byte ptr [rdx+rcx*2], 8\njz short loc_12C3\nmovsxd rdx, r12d\nadd r12d, 1\nmov [r13+rdx+0], cl\nloc_12C3:\nadd rbx, 1\nloc_12C7:\nmov rdi, rbp; s\ncall _strlen\ncmp rbx, rax\njb short loc_12A0\nmovsxd r12, r12d\nmov rax, r13\nmov byte ptr [r13+r12+0], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1280(char *s)\n{\n int v1; // r12d\n size_t i; // rbx\n const unsigned __int16 **v3; // rax\n __int64 v4; // rcx\n __int64 v5; // rdx\n _BYTE *result; // rax\n\n v1 = 0;\n for ( i = 0LL; i < strlen(s); ++i )\n {\n v3 = __ctype_b_loc();\n v4 = s[i];\n if ( ((*v3)[v4] & 8) != 0 )\n {\n v5 = v1++;\n byte_4040[v5] = v4;\n }\n }\n result = byte_4040;\n byte_4040[v1] = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1280(char *s) {\n int v1;\n unsigned int i;\n const unsigned short **v3;\n long long v4;\n long long v5;\n uint8_t *result;\n v1 = 0;\n for (i = 0LL; i < strlen(s); ++i) {\n v3 = __ctype_b_loc();\n v4 = s[i];\n if (((*v3)[v4] & 8) != 0) {\n v5 = v1++;\n byte_4040[v5] = v4;\n }\n }\n result = byte_4040;\n byte_4040[v1] = 0;\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(char *s) {\n int v1;\n unsigned int i;\n const unsigned short **v3;\n long long v4;\n long long v5;\n uint8_t *result;\n v1 = 0;\n for (i = 0LL; i < strlen(s); ++i) {\n v3 = __ctype_b_loc();\n v4 = s[i];\n if (((*v3)[v4] & 8) != 0) {\n v5 = v1++;\n result_1[v5] = v4;\n }\n }\n result = result_1;\n result_1[v1] = 0;\n return result;\n}" + }, + { + "index": 727, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* S) {\n static char result[100];\n int j = 0;\n for (int i = 0; i < strlen(S); i++) {\n if (isalnum(S[i])) {\n result[j++] = S[i];\n }\n }\n result[j] = '\\0';\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"123abcjw:, .@! eiw\"), \"123abcjweiw\") == 0);\n\n assert(strcmp(func0(\"Hello1234:, ! Howare33u\"), \"Hello1234Howare33u\") == 0);\n\n assert(strcmp(func0(\"Cool543Triks@:, Make@987Trips\"), \"Cool543TriksMake987Trips\") == 0);\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\nmov %rdi,%r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\ncallq 1070 \ntest %rax,%rax\nje 1318 \nmov %rax,%rbp\nxor %ebx,%ebx\nlea 0x2da1(%rip),%r13\ncallq 1090 <__ctype_b_loc@plt>\nmov %rax,%r12\nxor %eax,%eax\nmov (%r12),%rsi\nnopl (%rax)\nmovsbq (%r14,%rbx,1),%rcx\ntestb $0x8,(%rsi,%rcx,2)\nje 12ea \nmov %r14,%rdi\nmov %cl,0x0(%r13,%rax,1)\nlea 0x1(%rax),%r15d\nadd $0x1,%rbx\ncallq 1070 \nmov %rax,%rbp\ncmp %rax,%rbx\njae 12f6 \nmov (%r12),%rsi\nmovsbq (%r14,%rbx,1),%rcx\nmovslq %r15d,%rax\ntestb $0x8,(%rsi,%rcx,2)\njne 12bb \nadd $0x1,%rbx\ncmp %rbp,%rbx\njb 12b0 \nmov %eax,%r15d\nmovslq %r15d,%r15\nlea 0x2d40(%rip),%rax\nmovb $0x0,0x0(%r13,%r15,1)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl (%rax)\nxor %r15d,%r15d\nlea 0x2d1e(%rip),%r13\njmp 12f6 \nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r13\nlea r13, result_1\npush r12\nxor r12d, r12d\npush rbp\nmov rbp, rdi\npush rbx\nxor ebx, ebx\nsub rsp, 8\njmp short loc_12C7\nloc_12A0:\ncall ___ctype_b_loc\nmovsx rcx, byte ptr [rbp+rbx+0]\nmov rdx, rax\nmov rdx, [rdx]\ntest byte ptr [rdx+rcx*2], 8\njz short loc_12C3\nmovsxd rdx, r12d\nadd r12d, 1\nmov [r13+rdx+0], cl\nloc_12C3:\nadd rbx, 1\nloc_12C7:\nmov rdi, rbp; s\ncall _strlen\ncmp rbx, rax\njb short loc_12A0\nmovsxd r12, r12d\nmov rax, r13\nmov byte ptr [r13+r12+0], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(char *s)\n{\n int v1; // r12d\n size_t i; // rbx\n const unsigned __int16 **v3; // rax\n __int64 v4; // rcx\n __int64 v5; // rdx\n _BYTE *result; // rax\n\n v1 = 0;\n for ( i = 0LL; i < strlen(s); ++i )\n {\n v3 = __ctype_b_loc();\n v4 = s[i];\n if ( ((*v3)[v4] & 8) != 0 )\n {\n v5 = v1++;\n result_1[v5] = v4;\n }\n }\n result = result_1;\n result_1[v1] = 0;\n return result;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\npush r13\nlea r13, unk_4040\npush r12\nxor r12d, r12d\npush rbp\nmov rbp, rdi\npush rbx\nxor ebx, ebx\nsub rsp, 8\njmp short loc_12C7\nloc_12A0:\ncall ___ctype_b_loc\nmovsx rcx, byte ptr [rbp+rbx+0]\nmov rdx, rax\nmov rdx, [rdx]\ntest byte ptr [rdx+rcx*2], 8\njz short loc_12C3\nmovsxd rdx, r12d\nadd r12d, 1\nmov [r13+rdx+0], cl\nloc_12C3:\nadd rbx, 1\nloc_12C7:\nmov rdi, rbp; s\ncall _strlen\ncmp rbx, rax\njb short loc_12A0\nmovsxd r12, r12d\nmov rax, r13\nmov byte ptr [r13+r12+0], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1280(char *s)\n{\n int v1; // r12d\n size_t i; // rbx\n const unsigned __int16 **v3; // rax\n __int64 v4; // rcx\n __int64 v5; // rdx\n _BYTE *result; // rax\n\n v1 = 0;\n for ( i = 0LL; i < strlen(s); ++i )\n {\n v3 = __ctype_b_loc();\n v4 = s[i];\n if ( ((*v3)[v4] & 8) != 0 )\n {\n v5 = v1++;\n byte_4040[v5] = v4;\n }\n }\n result = byte_4040;\n byte_4040[v1] = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1280(char *s) {\n int v1;\n unsigned int i;\n const unsigned short **v3;\n long long v4;\n long long v5;\n uint8_t *result;\n v1 = 0;\n for (i = 0LL; i < strlen(s); ++i) {\n v3 = __ctype_b_loc();\n v4 = s[i];\n if (((*v3)[v4] & 8) != 0) {\n v5 = v1++;\n byte_4040[v5] = v4;\n }\n }\n result = byte_4040;\n byte_4040[v1] = 0;\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(char *s) {\n int v1;\n unsigned int i;\n const unsigned short **v3;\n long long v4;\n long long v5;\n uint8_t *result;\n v1 = 0;\n for (i = 0LL; i < strlen(s); ++i) {\n v3 = __ctype_b_loc();\n v4 = s[i];\n if (((*v3)[v4] & 8) != 0) {\n v5 = v1++;\n result_1[v5] = v4;\n }\n }\n result = result_1;\n result_1[v1] = 0;\n return result;\n}" + }, + { + "index": 728, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "void func0(int *lst1, int *lst2, int *res_list, int size) {\n for (int i = 0; i < size; i++) {\n res_list[i] = lst1[i] + lst2[i];\n }\n}", + "test": "int main() {\n\n int lst1_1[] = {10, 20, 30};\n\n int lst2_1[] = {15, 25, 35};\n\n int res_list_1[3];\n\n func0(lst1_1, lst2_1, res_list_1, 3);\n\n assert(res_list_1[0] == 25);\n\n assert(res_list_1[1] == 45);\n\n assert(res_list_1[2] == 65);\n\n\n\n int lst1_2[] = {1, 2, 3};\n\n int lst2_2[] = {5, 6, 7};\n\n int res_list_2[3];\n\n func0(lst1_2, lst2_2, res_list_2, 3);\n\n assert(res_list_2[0] == 6);\n\n assert(res_list_2[1] == 8);\n\n assert(res_list_2[2] == 10);\n\n\n\n int lst1_3[] = {15, 20, 30};\n\n int lst2_3[] = {15, 45, 75};\n\n int res_list_3[3];\n\n func0(lst1_3, lst2_3, res_list_3, 3);\n\n assert(res_list_3[0] == 30);\n\n assert(res_list_3[1] == 65);\n\n assert(res_list_3[2] == 105);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %ecx,-0x2c(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11d1 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%ecx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rsi\nmov -0x28(%rbp),%rax\nadd %rsi,%rax\nadd %ecx,%edx\nmov %edx,(%rax)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 1189 \npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_28], rdx\nmov [rbp+var_2C], ecx\nmov [rbp+var_4], 0\njmp short loc_11D1\nloc_1189:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov ecx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rsi, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rsi\nadd edx, ecx\nmov [rax], edx\nadd [rbp+var_4], 1\nloc_11D1:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_2C]\njl short loc_1189\nnop\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+28h] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a4 )\n break;\n *(_DWORD *)(4LL * (int)i + a3) = *(_DWORD *)(4LL * (int)i + a1) + *(_DWORD *)(4LL * (int)i + a2);\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_28], rdx\nmov [rbp+var_2C], ecx\nmov [rbp+var_4], 0\njmp short loc_11D1\nloc_1189:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov ecx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rsi, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rsi\nadd edx, ecx\nmov [rax], edx\nadd [rbp+var_4], 1\nloc_11D1:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_2C]\njl short loc_1189\nnop\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+28h] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a4 )\n break;\n *(_DWORD *)(4LL * (int)i + a3) = *(_DWORD *)(4LL * (int)i + a1) + *(_DWORD *)(4LL * (int)i + a2);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, long long a3, int a4) {\n long long result;\n unsigned int i;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a4) break;\n *(uint32_t *)(4LL * (int)i + a3) =\n *(uint32_t *)(4LL * (int)i + a1) + *(uint32_t *)(4LL * (int)i + a2);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, long long a3, int a4) {\n long long result;\n unsigned int i;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a4) break;\n *(uint32_t *)(4LL * (int)i + a3) =\n *(uint32_t *)(4LL * (int)i + a1) + *(uint32_t *)(4LL * (int)i + a2);\n }\n return result;\n}" + }, + { + "index": 728, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "void func0(int *lst1, int *lst2, int *res_list, int size) {\n for (int i = 0; i < size; i++) {\n res_list[i] = lst1[i] + lst2[i];\n }\n}", + "test": "int main() {\n\n int lst1_1[] = {10, 20, 30};\n\n int lst2_1[] = {15, 25, 35};\n\n int res_list_1[3];\n\n func0(lst1_1, lst2_1, res_list_1, 3);\n\n assert(res_list_1[0] == 25);\n\n assert(res_list_1[1] == 45);\n\n assert(res_list_1[2] == 65);\n\n\n\n int lst1_2[] = {1, 2, 3};\n\n int lst2_2[] = {5, 6, 7};\n\n int res_list_2[3];\n\n func0(lst1_2, lst2_2, res_list_2, 3);\n\n assert(res_list_2[0] == 6);\n\n assert(res_list_2[1] == 8);\n\n assert(res_list_2[2] == 10);\n\n\n\n int lst1_3[] = {15, 20, 30};\n\n int lst2_3[] = {15, 45, 75};\n\n int res_list_3[3];\n\n func0(lst1_3, lst2_3, res_list_3, 3);\n\n assert(res_list_3[0] == 30);\n\n assert(res_list_3[1] == 65);\n\n assert(res_list_3[2] == 105);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %ecx,%ecx\njle 118f \nlea -0x1(%rcx),%r8d\nmov $0x0,%eax\nmov (%rsi,%rax,4),%ecx\nadd (%rdi,%rax,4),%ecx\nmov %ecx,(%rdx,%rax,4)\nmov %rax,%rcx\nadd $0x1,%rax\ncmp %r8,%rcx\njne 117a \nretq\n", + "ida_asm": "func0:\nendbr64\ntest ecx, ecx\njle short locret_1193\nmovsxd rcx, ecx\nlea r8, ds:0[rcx*4]\nmov eax, 0\nloc_1181:\nmov ecx, [rsi+rax]\nadd ecx, [rdi+rax]\nmov [rdx+rax], ecx\nadd rax, 4\ncmp rax, r8\njnz short loc_1181\nlocret_1193:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 v4; // rax\n\n if ( a4 > 0 )\n {\n v4 = 0LL;\n do\n {\n *(_DWORD *)(a3 + v4) = *(_DWORD *)(a1 + v4) + *(_DWORD *)(a2 + v4);\n v4 += 4LL;\n }\n while ( v4 != 4LL * a4 );\n }\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest ecx, ecx\njle short locret_1193\nmovsxd rcx, ecx\nlea r8, ds:0[rcx*4]\nmov eax, 0\nloc_1181:\nmov ecx, [rsi+rax]\nadd ecx, [rdi+rax]\nmov [rdx+rax], ecx\nadd rax, 4\ncmp rax, r8\njnz short loc_1181\nlocret_1193:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1169(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 v4; // rax\n\n if ( a4 > 0 )\n {\n v4 = 0LL;\n do\n {\n *(_DWORD *)(a3 + v4) = *(_DWORD *)(a1 + v4) + *(_DWORD *)(a2 + v4);\n v4 += 4LL;\n }\n while ( v4 != 4LL * a4 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1169(long long a1, long long a2, long long a3, int a4) {\n long long v4;\n if (a4 > 0) {\n v4 = 0LL;\n do {\n *(uint32_t *)(a3 + v4) = *(uint32_t *)(a1 + v4) + *(uint32_t *)(a2 + v4);\n v4 += 4LL;\n } while (v4 != 4LL * a4);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, long long a2, long long a3, int a4) {\n long long v4;\n if (a4 > 0) {\n v4 = 0LL;\n do {\n *(uint32_t *)(a3 + v4) = *(uint32_t *)(a1 + v4) + *(uint32_t *)(a2 + v4);\n v4 += 4LL;\n } while (v4 != 4LL * a4);\n }\n}" + }, + { + "index": 729, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int nums1[], int nums2[], int result[], int size) {\n for (int i = 0; i < size; i++) {\n result[i] = nums1[i] + nums2[i];\n }\n}", + "test": "int main() {\n\n int nums1_1[] = {1, 2, 3}, nums2_1[] = {4, 5, 6}, result_1[3], expected_1[] = {5, 7, 9};\n\n int nums1_2[] = {1, 2}, nums2_2[] = {3, 4}, result_2[2], expected_2[] = {4, 6};\n\n int nums1_3[] = {10, 20}, nums2_3[] = {50, 70}, result_3[2], expected_3[] = {60, 90};\n\n\n\n func0(nums1_1, nums2_1, result_1, 3);\n\n func0(nums1_2, nums2_2, result_2, 2);\n\n func0(nums1_3, nums2_3, result_3, 2);\n\n \n\n for (int i = 0; i < 3; i++) {\n\n assert(result_1[i] == expected_1[i]);\n\n }\n\n\n\n for (int i = 0; i < 2; i++) {\n\n assert(result_2[i] == expected_2[i]);\n\n }\n\n\n\n for (int i = 0; i < 2; i++) {\n\n assert(result_3[i] == expected_3[i]);\n\n }\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %ecx,-0x2c(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11d1 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%ecx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rsi\nmov -0x28(%rbp),%rax\nadd %rsi,%rax\nadd %ecx,%edx\nmov %edx,(%rax)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 1189 \npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_28], rdx\nmov [rbp+var_2C], ecx\nmov [rbp+var_4], 0\njmp short loc_11D1\nloc_1189:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov ecx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rsi, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rsi\nadd edx, ecx\nmov [rax], edx\nadd [rbp+var_4], 1\nloc_11D1:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_2C]\njl short loc_1189\nnop\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+28h] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a4 )\n break;\n *(_DWORD *)(4LL * (int)i + a3) = *(_DWORD *)(4LL * (int)i + a1) + *(_DWORD *)(4LL * (int)i + a2);\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_28], rdx\nmov [rbp+var_2C], ecx\nmov [rbp+var_4], 0\njmp short loc_11D1\nloc_1189:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov ecx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rsi, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rsi\nadd edx, ecx\nmov [rax], edx\nadd [rbp+var_4], 1\nloc_11D1:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_2C]\njl short loc_1189\nnop\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+28h] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a4 )\n break;\n *(_DWORD *)(4LL * (int)i + a3) = *(_DWORD *)(4LL * (int)i + a1) + *(_DWORD *)(4LL * (int)i + a2);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, long long a3, int a4) {\n long long result;\n unsigned int i;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a4) break;\n *(uint32_t *)(4LL * (int)i + a3) =\n *(uint32_t *)(4LL * (int)i + a1) + *(uint32_t *)(4LL * (int)i + a2);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, long long a3, int a4) {\n long long result;\n unsigned int i;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a4) break;\n *(uint32_t *)(4LL * (int)i + a3) =\n *(uint32_t *)(4LL * (int)i + a1) + *(uint32_t *)(4LL * (int)i + a2);\n }\n return result;\n}" + }, + { + "index": 729, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int nums1[], int nums2[], int result[], int size) {\n for (int i = 0; i < size; i++) {\n result[i] = nums1[i] + nums2[i];\n }\n}", + "test": "int main() {\n\n int nums1_1[] = {1, 2, 3}, nums2_1[] = {4, 5, 6}, result_1[3], expected_1[] = {5, 7, 9};\n\n int nums1_2[] = {1, 2}, nums2_2[] = {3, 4}, result_2[2], expected_2[] = {4, 6};\n\n int nums1_3[] = {10, 20}, nums2_3[] = {50, 70}, result_3[2], expected_3[] = {60, 90};\n\n\n\n func0(nums1_1, nums2_1, result_1, 3);\n\n func0(nums1_2, nums2_2, result_2, 2);\n\n func0(nums1_3, nums2_3, result_3, 2);\n\n \n\n for (int i = 0; i < 3; i++) {\n\n assert(result_1[i] == expected_1[i]);\n\n }\n\n\n\n for (int i = 0; i < 2; i++) {\n\n assert(result_2[i] == expected_2[i]);\n\n }\n\n\n\n for (int i = 0; i < 2; i++) {\n\n assert(result_3[i] == expected_3[i]);\n\n }\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %ecx,%ecx\njle 118f \nlea -0x1(%rcx),%r8d\nmov $0x0,%eax\nmov (%rsi,%rax,4),%ecx\nadd (%rdi,%rax,4),%ecx\nmov %ecx,(%rdx,%rax,4)\nmov %rax,%rcx\nadd $0x1,%rax\ncmp %r8,%rcx\njne 117a \nretq\n", + "ida_asm": "func0:\nendbr64\ntest ecx, ecx\njle short locret_1193\nmovsxd rcx, ecx\nlea r8, ds:0[rcx*4]\nmov eax, 0\nloc_1181:\nmov ecx, [rsi+rax]\nadd ecx, [rdi+rax]\nmov [rdx+rax], ecx\nadd rax, 4\ncmp rax, r8\njnz short loc_1181\nlocret_1193:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 v4; // rax\n\n if ( a4 > 0 )\n {\n v4 = 0LL;\n do\n {\n *(_DWORD *)(a3 + v4) = *(_DWORD *)(a1 + v4) + *(_DWORD *)(a2 + v4);\n v4 += 4LL;\n }\n while ( v4 != 4LL * a4 );\n }\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest ecx, ecx\njle short locret_1193\nmovsxd rcx, ecx\nlea r8, ds:0[rcx*4]\nmov eax, 0\nloc_1181:\nmov ecx, [rsi+rax]\nadd ecx, [rdi+rax]\nmov [rdx+rax], ecx\nadd rax, 4\ncmp rax, r8\njnz short loc_1181\nlocret_1193:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1169(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n __int64 v4; // rax\n\n if ( a4 > 0 )\n {\n v4 = 0LL;\n do\n {\n *(_DWORD *)(a3 + v4) = *(_DWORD *)(a1 + v4) + *(_DWORD *)(a2 + v4);\n v4 += 4LL;\n }\n while ( v4 != 4LL * a4 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1169(long long a1, long long a2, long long a3, int a4) {\n long long v4;\n if (a4 > 0) {\n v4 = 0LL;\n do {\n *(uint32_t *)(a3 + v4) = *(uint32_t *)(a1 + v4) + *(uint32_t *)(a2 + v4);\n v4 += 4LL;\n } while (v4 != 4LL * a4);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, long long a2, long long a3, int a4) {\n long long v4;\n if (a4 > 0) {\n v4 = 0LL;\n do {\n *(uint32_t *)(a3 + v4) = *(uint32_t *)(a1 + v4) + *(uint32_t *)(a2 + v4);\n v4 += 4LL;\n } while (v4 != 4LL * a4);\n }\n}" + }, + { + "index": 730, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int *func0(int nums[], int length, int *out_length) {\n int *result = malloc(sizeof(int) * length);\n int current_key = nums[0];\n result[0] = current_key;\n int j = 1;\n for (int i = 1; i < length; i++) {\n if (nums[i] != current_key) {\n current_key = nums[i];\n result[j++] = current_key;\n }\n }\n *out_length = j;\n return result;\n}", + "test": "int main() {\n\n int a1[] = {0, 0, 1, 2, 3, 4, 4, 5, 6, 6, 6, 7, 8, 9, 4, 4};\n\n int len1;\n\n int *result1 = func0(a1, 16, &len1);\n\n int expected1[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4};\n\n for (int i = 0; i < len1; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n\n\n int a2[] = {10, 10, 15, 19, 18, 18, 17, 26, 26, 17, 18, 10};\n\n int len2;\n\n int *result2 = func0(a2, 12, &len2);\n\n int expected2[] = {10, 15, 19, 18, 17, 26, 17, 18, 10};\n\n for (int i = 0; i < len2; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n\n\n int a3[] = {'a', 'a', 'b', 'c', 'd', 'd'};\n\n int len3;\n\n int *result3 = func0(a3, 6, &len3);\n\n int expected3[] = {'a', 'b', 'c', 'd'};\n\n for (int i = 0; i < len3; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x40,%rsp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmov %rdx,-0x38(%rbp)\nmov -0x2c(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,-0x8(%rbp)\nmov -0x28(%rbp),%rax\nmov (%rax),%eax\nmov %eax,-0x14(%rbp)\nmov -0x8(%rbp),%rax\nmov -0x14(%rbp),%edx\nmov %edx,(%rax)\nmovl $0x1,-0x10(%rbp)\nmovl $0x1,-0xc(%rbp)\njmp 126e \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x14(%rbp)\nje 126a \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x14(%rbp)\nmov -0x10(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x10(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov -0x14(%rbp),%eax\nmov %eax,(%rdx)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 1217 \nmov -0x38(%rbp),%rax\nmov -0x10(%rbp),%edx\nmov %edx,(%rax)\nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov rax, [rbp+var_28]\nmov eax, [rax]\nmov [rbp+var_14], eax\nmov rax, [rbp+var_8]\nmov edx, [rbp+var_14]\nmov [rax], edx\nmov [rbp+var_10], 1\nmov [rbp+var_C], 1\njmp short loc_126E\nloc_1217:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_14], eax\njz short loc_126A\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_14], eax\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_14]\nmov [rdx], eax\nloc_126A:\nadd [rbp+var_C], 1\nloc_126E:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_2C]\njl short loc_1217\nmov rax, [rbp+var_38]\nmov edx, [rbp+var_10]\nmov [rax], edx\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2, int *a3)\n{\n int v3; // eax\n int v6; // [rsp+2Ch] [rbp-14h]\n int v7; // [rsp+30h] [rbp-10h]\n int i; // [rsp+34h] [rbp-Ch]\n _DWORD *v9; // [rsp+38h] [rbp-8h]\n\n v9 = malloc(4LL * a2);\n v6 = *a1;\n *v9 = *a1;\n v7 = 1;\n for ( i = 1; i < a2; ++i )\n {\n if ( v6 != a1[i] )\n {\n v6 = a1[i];\n v3 = v7++;\n v9[v3] = v6;\n }\n }\n *a3 = v7;\n return v9;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov rax, [rbp+var_28]\nmov eax, [rax]\nmov [rbp+var_14], eax\nmov rax, [rbp+var_8]\nmov edx, [rbp+var_14]\nmov [rax], edx\nmov [rbp+var_10], 1\nmov [rbp+var_C], 1\njmp short loc_126E\nloc_1217:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_14], eax\njz short loc_126A\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_14], eax\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_14]\nmov [rdx], eax\nloc_126A:\nadd [rbp+var_C], 1\nloc_126E:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_2C]\njl short loc_1217\nmov rax, [rbp+var_38]\nmov edx, [rbp+var_10]\nmov [rax], edx\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11C9(int *a1, int a2, int *a3)\n{\n int v3; // eax\n int v6; // [rsp+2Ch] [rbp-14h]\n int v7; // [rsp+30h] [rbp-10h]\n int i; // [rsp+34h] [rbp-Ch]\n _DWORD *v9; // [rsp+38h] [rbp-8h]\n\n v9 = malloc(4LL * a2);\n v6 = *a1;\n *v9 = *a1;\n v7 = 1;\n for ( i = 1; i < a2; ++i )\n {\n if ( v6 != a1[i] )\n {\n v6 = a1[i];\n v3 = v7++;\n v9[v3] = v6;\n }\n }\n *a3 = v7;\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11C9(int *a1, int a2, int *a3) {\n int v3;\n int v6;\n int v7;\n int i;\n uint32_t *v9;\n v9 = malloc(4LL * a2);\n v6 = *a1;\n *v9 = *a1;\n v7 = 1;\n for (i = 1; i < a2; ++i) {\n if (v6 != a1[i]) {\n v6 = a1[i];\n v3 = v7++;\n v9[v3] = v6;\n }\n }\n *a3 = v7;\n return v9;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2, int *a3) {\n int v3;\n int v6;\n int v7;\n int i;\n uint32_t *v9;\n v9 = malloc(4LL * a2);\n v6 = *a1;\n *v9 = *a1;\n v7 = 1;\n for (i = 1; i < a2; ++i) {\n if (v6 != a1[i]) {\n v6 = a1[i];\n v3 = v7++;\n v9[v3] = v6;\n }\n }\n *a3 = v7;\n return v9;\n}" + }, + { + "index": 730, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int *func0(int nums[], int length, int *out_length) {\n int *result = malloc(sizeof(int) * length);\n int current_key = nums[0];\n result[0] = current_key;\n int j = 1;\n for (int i = 1; i < length; i++) {\n if (nums[i] != current_key) {\n current_key = nums[i];\n result[j++] = current_key;\n }\n }\n *out_length = j;\n return result;\n}", + "test": "int main() {\n\n int a1[] = {0, 0, 1, 2, 3, 4, 4, 5, 6, 6, 6, 7, 8, 9, 4, 4};\n\n int len1;\n\n int *result1 = func0(a1, 16, &len1);\n\n int expected1[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4};\n\n for (int i = 0; i < len1; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n\n\n int a2[] = {10, 10, 15, 19, 18, 18, 17, 26, 26, 17, 18, 10};\n\n int len2;\n\n int *result2 = func0(a2, 12, &len2);\n\n int expected2[] = {10, 15, 19, 18, 17, 26, 17, 18, 10};\n\n for (int i = 0; i < len2; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n\n\n int a3[] = {'a', 'a', 'b', 'c', 'd', 'd'};\n\n int len3;\n\n int *result3 = func0(a3, 6, &len3);\n\n int expected3[] = {'a', 'b', 'c', 'd'};\n\n for (int i = 0; i < len3; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%r12\nmov %esi,%ebp\nmov %rdx,%rbx\nmovslq %esi,%rdi\nshl $0x2,%rdi\ncallq 10d0 \nmov (%r12),%ecx\nmov %ecx,(%rax)\ncmp $0x1,%ebp\njle 1220 \nlea 0x4(%r12),%rdx\nlea -0x2(%rbp),%esi\nlea 0x8(%r12,%rsi,4),%r8\nmov $0x1,%esi\njmp 1216 \nmovslq %esi,%rdi\nmov %ecx,(%rax,%rdi,4)\nlea 0x1(%rsi),%esi\nadd $0x4,%rdx\ncmp %r8,%rdx\nje 1225 \nmov %ecx,%edi\nmov (%rdx),%ecx\ncmp %edi,%ecx\njne 1204 \njmp 120d \nmov $0x1,%esi\nmov %esi,(%rbx)\npop %rbx\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov r12, rdi\nmov ebp, esi\nmov rbx, rdx\nmovsxd rdi, esi\nshl rdi, 2; size\ncall _malloc\nmov ecx, [r12]\nmov [rax], ecx\ncmp ebp, 1\njle short loc_1220\nlea rdx, [r12+4]\nlea esi, [rbp-2]\nlea r8, [r12+rsi*4+8]\nmov esi, 1\njmp short loc_120D\nloc_1204:\nadd rdx, 4\ncmp rdx, r8\njz short loc_1225\nloc_120D:\nmov edi, ecx\nmov ecx, [rdx]\ncmp ecx, edi\njz short loc_1204\nmovsxd rdi, esi\nmov [rax+rdi*4], ecx\nlea esi, [rsi+1]\njmp short loc_1204\nloc_1220:\nmov esi, 1\nloc_1225:\nmov [rbx], esi\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2, int *a3)\n{\n _DWORD *result; // rax\n int v7; // ecx\n int *v8; // rdx\n int v9; // esi\n int v10; // edi\n\n result = malloc(4LL * a2);\n v7 = *a1;\n *result = *a1;\n if ( a2 <= 1 )\n {\n v9 = 1;\n }\n else\n {\n v8 = a1 + 1;\n v9 = 1;\n do\n {\n v10 = v7;\n v7 = *v8;\n if ( *v8 != v10 )\n result[v9++] = v7;\n ++v8;\n }\n while ( v8 != &a1[a2 - 2 + 2] );\n }\n *a3 = v9;\n return result;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r12\npush rbp\npush rbx\nmov r12, rdi\nmov ebp, esi\nmov rbx, rdx\nmovsxd rdi, esi\nshl rdi, 2; size\ncall _malloc\nmov ecx, [r12]\nmov [rax], ecx\ncmp ebp, 1\njle short loc_1220\nlea rdx, [r12+4]\nlea esi, [rbp-2]\nlea r8, [r12+rsi*4+8]\nmov esi, 1\njmp short loc_120D\nloc_1204:\nadd rdx, 4\ncmp rdx, r8\njz short loc_1225\nloc_120D:\nmov edi, ecx\nmov ecx, [rdx]\ncmp ecx, edi\njz short loc_1204\nmovsxd rdi, esi\nmov [rax+rdi*4], ecx\nlea esi, [rsi+1]\njmp short loc_1204\nloc_1220:\nmov esi, 1\nloc_1225:\nmov [rbx], esi\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11C9(int *a1, int a2, int *a3)\n{\n _DWORD *result; // rax\n int v7; // ecx\n int *v8; // rdx\n int v9; // esi\n int v10; // edi\n\n result = malloc(4LL * a2);\n v7 = *a1;\n *result = *a1;\n if ( a2 <= 1 )\n {\n v9 = 1;\n }\n else\n {\n v8 = a1 + 1;\n v9 = 1;\n do\n {\n v10 = v7;\n v7 = *v8;\n if ( *v8 != v10 )\n result[v9++] = v7;\n ++v8;\n }\n while ( v8 != &a1[a2 - 2 + 2] );\n }\n *a3 = v9;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11C9(int *a1, int a2, int *a3) {\n uint32_t *result;\n int v7;\n int *v8;\n int v9;\n int v10;\n result = malloc(4LL * a2);\n v7 = *a1;\n *result = *a1;\n if (a2 <= 1) {\n v9 = 1;\n } else {\n v8 = a1 + 1;\n v9 = 1;\n do {\n v10 = v7;\n v7 = *v8;\n if (*v8 != v10) result[v9++] = v7;\n ++v8;\n } while (v8 != &a1[a2 - 2 + 2]);\n }\n *a3 = v9;\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2, int *a3) {\n uint32_t *result;\n int v7;\n int *v8;\n int v9;\n int v10;\n result = malloc(4LL * a2);\n v7 = *a1;\n *result = *a1;\n if (a2 <= 1) {\n v9 = 1;\n } else {\n v8 = a1 + 1;\n v9 = 1;\n do {\n v10 = v7;\n v7 = *v8;\n if (*v8 != v10) result[v9++] = v7;\n ++v8;\n } while (v8 != &a1[a2 - 2 + 2]);\n }\n *a3 = v9;\n return result;\n}" + }, + { + "index": 730, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int *func0(int nums[], int length, int *out_length) {\n int *result = malloc(sizeof(int) * length);\n int current_key = nums[0];\n result[0] = current_key;\n int j = 1;\n for (int i = 1; i < length; i++) {\n if (nums[i] != current_key) {\n current_key = nums[i];\n result[j++] = current_key;\n }\n }\n *out_length = j;\n return result;\n}", + "test": "int main() {\n\n int a1[] = {0, 0, 1, 2, 3, 4, 4, 5, 6, 6, 6, 7, 8, 9, 4, 4};\n\n int len1;\n\n int *result1 = func0(a1, 16, &len1);\n\n int expected1[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4};\n\n for (int i = 0; i < len1; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n\n\n int a2[] = {10, 10, 15, 19, 18, 18, 17, 26, 26, 17, 18, 10};\n\n int len2;\n\n int *result2 = func0(a2, 12, &len2);\n\n int expected2[] = {10, 15, 19, 18, 17, 26, 17, 18, 10};\n\n for (int i = 0; i < len2; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n\n\n int a3[] = {'a', 'a', 'b', 'c', 'd', 'd'};\n\n int len3;\n\n int *result3 = func0(a3, 6, &len3);\n\n int expected3[] = {'a', 'b', 'c', 'd'};\n\n for (int i = 0; i < len3; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %rdx,%r12\npush %rbp\nmov %rdi,%rbp\nmovslq %esi,%rdi\npush %rbx\nmov %rdi,%rbx\nshl $0x2,%rdi\ncallq 10d0 \nmov 0x0(%rbp),%edi\nmov %edi,(%rax)\ncmp $0x1,%ebx\njle 1580 \nlea -0x2(%rbx),%edx\nlea 0x4(%rbp),%rcx\nmov $0x1,%esi\nlea 0x8(%rbp,%rdx,4),%r9\nnopl 0x0(%rax,%rax,1)\nmov %edi,%r8d\nmov (%rcx),%edi\ncmp %r8d,%edi\nje 1564 \nmovslq %esi,%r8\nadd $0x1,%esi\nmov %edi,(%rax,%r8,4)\nadd $0x4,%rcx\ncmp %r9,%rcx\njne 1550 \npop %rbx\npop %rbp\nmov %esi,(%r12)\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\nmov $0x1,%esi\npop %rbx\npop %rbp\nmov %esi,(%r12)\npop %r12\nretq\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r12\nmov r12, rdx\npush rbp\nmov rbp, rdi\nmovsxd rdi, esi\npush rbx\nmov rbx, rdi\nshl rdi, 2; size\ncall _malloc\nmov ecx, [rbp+0]\nmov [rax], ecx\ncmp ebx, 1\njle short loc_14C8\nlea esi, [rbx-2]\nlea rdx, [rbp+4]\nlea r8, [rbp+rsi*4+8]\nmov esi, 1\nnop dword ptr [rax+rax+00000000h]\nloc_14A0:\nmov edi, ecx\nmov ecx, [rdx]\ncmp ecx, edi\njz short loc_14B1\nmovsxd rdi, esi\nadd esi, 1\nmov [rax+rdi*4], ecx\nloc_14B1:\nadd rdx, 4\ncmp rdx, r8\njnz short loc_14A0\nmov [r12], esi\npop rbx\npop rbp\npop r12\nretn\nloc_14C8:\nmov esi, 1\nmov [r12], esi\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2, int *a3)\n{\n _DWORD *result; // rax\n int v7; // ecx\n int *v8; // rdx\n int v9; // esi\n int v10; // edi\n __int64 v11; // rdi\n\n result = malloc(4LL * a2);\n v7 = *a1;\n *result = *a1;\n if ( a2 <= 1 )\n {\n *a3 = 1;\n }\n else\n {\n v8 = a1 + 1;\n v9 = 1;\n do\n {\n v10 = v7;\n v7 = *v8;\n if ( *v8 != v10 )\n {\n v11 = v9++;\n result[v11] = v7;\n }\n ++v8;\n }\n while ( v8 != &a1[a2 - 2 + 2] );\n *a3 = v9;\n }\n return result;\n}", + "ida_strip_asm": "sub_1460:\nendbr64\npush r12\nmov r12, rdx\npush rbp\nmov rbp, rdi\nmovsxd rdi, esi\npush rbx\nmov rbx, rdi\nshl rdi, 2; size\ncall _malloc\nmov ecx, [rbp+0]\nmov [rax], ecx\ncmp ebx, 1\njle short loc_14C8\nlea esi, [rbx-2]\nlea rdx, [rbp+4]\nlea r8, [rbp+rsi*4+8]\nmov esi, 1\nnop dword ptr [rax+rax+00000000h]\nloc_14A0:\nmov edi, ecx\nmov ecx, [rdx]\ncmp ecx, edi\njz short loc_14B1\nmovsxd rdi, esi\nadd esi, 1\nmov [rax+rdi*4], ecx\nloc_14B1:\nadd rdx, 4\ncmp rdx, r8\njnz short loc_14A0\nmov [r12], esi\npop rbx\npop rbp\npop r12\nretn\nloc_14C8:\nmov esi, 1\nmov [r12], esi\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1460(int *a1, int a2, int *a3)\n{\n _DWORD *result; // rax\n int v7; // ecx\n int *v8; // rdx\n int v9; // esi\n int v10; // edi\n __int64 v11; // rdi\n\n result = malloc(4LL * a2);\n v7 = *a1;\n *result = *a1;\n if ( a2 <= 1 )\n {\n *a3 = 1;\n }\n else\n {\n v8 = a1 + 1;\n v9 = 1;\n do\n {\n v10 = v7;\n v7 = *v8;\n if ( *v8 != v10 )\n {\n v11 = v9++;\n result[v11] = v7;\n }\n ++v8;\n }\n while ( v8 != &a1[a2 - 2 + 2] );\n *a3 = v9;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1460(int *a1, int a2, int *a3) {\n uint32_t *result;\n int v7;\n int *v8;\n int v9;\n int v10;\n long long v11;\n result = malloc(4LL * a2);\n v7 = *a1;\n *result = *a1;\n if (a2 <= 1) {\n *a3 = 1;\n } else {\n v8 = a1 + 1;\n v9 = 1;\n do {\n v10 = v7;\n v7 = *v8;\n if (*v8 != v10) {\n v11 = v9++;\n result[v11] = v7;\n }\n ++v8;\n } while (v8 != &a1[a2 - 2 + 2]);\n *a3 = v9;\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2, int *a3) {\n uint32_t *result;\n int v7;\n int *v8;\n int v9;\n int v10;\n long long v11;\n result = malloc(4LL * a2);\n v7 = *a1;\n *result = *a1;\n if (a2 <= 1) {\n *a3 = 1;\n } else {\n v8 = a1 + 1;\n v9 = 1;\n do {\n v10 = v7;\n v7 = *v8;\n if (*v8 != v10) {\n v11 = v9++;\n result[v11] = v7;\n }\n ++v8;\n } while (v8 != &a1[a2 - 2 + 2]);\n *a3 = v9;\n }\n return result;\n}" + }, + { + "index": 730, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int *func0(int nums[], int length, int *out_length) {\n int *result = malloc(sizeof(int) * length);\n int current_key = nums[0];\n result[0] = current_key;\n int j = 1;\n for (int i = 1; i < length; i++) {\n if (nums[i] != current_key) {\n current_key = nums[i];\n result[j++] = current_key;\n }\n }\n *out_length = j;\n return result;\n}", + "test": "int main() {\n\n int a1[] = {0, 0, 1, 2, 3, 4, 4, 5, 6, 6, 6, 7, 8, 9, 4, 4};\n\n int len1;\n\n int *result1 = func0(a1, 16, &len1);\n\n int expected1[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4};\n\n for (int i = 0; i < len1; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n\n\n int a2[] = {10, 10, 15, 19, 18, 18, 17, 26, 26, 17, 18, 10};\n\n int len2;\n\n int *result2 = func0(a2, 12, &len2);\n\n int expected2[] = {10, 15, 19, 18, 17, 26, 17, 18, 10};\n\n for (int i = 0; i < len2; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n\n\n int a3[] = {'a', 'a', 'b', 'c', 'd', 'd'};\n\n int len3;\n\n int *result3 = func0(a3, 6, &len3);\n\n int expected3[] = {'a', 'b', 'c', 'd'};\n\n for (int i = 0; i < len3; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %rdx,%r12\npush %rbp\nmov %rdi,%rbp\nmovslq %esi,%rdi\npush %rbx\nmov %rdi,%rbx\nshl $0x2,%rdi\ncallq 10d0 \nmov 0x0(%rbp),%edi\nmov %edi,(%rax)\ncmp $0x1,%ebx\njle 1610 \nlea -0x2(%rbx),%edx\nlea 0x4(%rbp),%rcx\nmov $0x1,%esi\nlea 0x8(%rbp,%rdx,4),%r9\nnopl 0x0(%rax,%rax,1)\nmov %edi,%r8d\nmov (%rcx),%edi\ncmp %r8d,%edi\nje 15f4 \nmovslq %esi,%r8\nadd $0x1,%esi\nmov %edi,(%rax,%r8,4)\nadd $0x4,%rcx\ncmp %r9,%rcx\njne 15e0 \npop %rbx\npop %rbp\nmov %esi,(%r12)\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\nmov $0x1,%esi\npop %rbx\npop %rbp\nmov %esi,(%r12)\npop %r12\nretq\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r12\nmov r12, rdx\npush rbp\nmov rbp, rdi\nmovsxd rdi, esi\npush rbx\nmov rbx, rdi\nshl rdi, 2; size\ncall _malloc\nmov ecx, [rbp+0]\nmov [rax], ecx\ncmp ebx, 1\njle short loc_1548\nlea esi, [rbx-2]\nlea rdx, [rbp+4]\nlea r8, [rbp+rsi*4+8]\nmov esi, 1\nnop dword ptr [rax+rax+00000000h]\nloc_1520:\nmov edi, ecx\nmov ecx, [rdx]\ncmp ecx, edi\njz short loc_1531\nmovsxd rdi, esi\nadd esi, 1\nmov [rax+rdi*4], ecx\nloc_1531:\nadd rdx, 4\ncmp rdx, r8\njnz short loc_1520\nmov [r12], esi\npop rbx\npop rbp\npop r12\nretn\nloc_1548:\nmov esi, 1\nmov [r12], esi\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2, int *a3)\n{\n _DWORD *result; // rax\n int v7; // ecx\n int *v8; // rdx\n int v9; // esi\n int v10; // edi\n __int64 v11; // rdi\n\n result = malloc(4LL * a2);\n v7 = *a1;\n *result = *a1;\n if ( a2 <= 1 )\n {\n *a3 = 1;\n }\n else\n {\n v8 = a1 + 1;\n v9 = 1;\n do\n {\n v10 = v7;\n v7 = *v8;\n if ( *v8 != v10 )\n {\n v11 = v9++;\n result[v11] = v7;\n }\n ++v8;\n }\n while ( v8 != &a1[a2 - 2 + 2] );\n *a3 = v9;\n }\n return result;\n}", + "ida_strip_asm": "sub_14E0:\nendbr64\npush r12\nmov r12, rdx\npush rbp\nmov rbp, rdi\nmovsxd rdi, esi\npush rbx\nmov rbx, rdi\nshl rdi, 2; size\ncall _malloc\nmov ecx, [rbp+0]\nmov [rax], ecx\ncmp ebx, 1\njle short loc_1548\nlea esi, [rbx-2]\nlea rdx, [rbp+4]\nlea r8, [rbp+rsi*4+8]\nmov esi, 1\nnop dword ptr [rax+rax+00000000h]\nloc_1520:\nmov edi, ecx\nmov ecx, [rdx]\ncmp ecx, edi\njz short loc_1531\nmovsxd rdi, esi\nadd esi, 1\nmov [rax+rdi*4], ecx\nloc_1531:\nadd rdx, 4\ncmp rdx, r8\njnz short loc_1520\nmov [r12], esi\npop rbx\npop rbp\npop r12\nretn\nloc_1548:\nmov esi, 1\nmov [r12], esi\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_14E0(int *a1, int a2, int *a3)\n{\n _DWORD *result; // rax\n int v7; // ecx\n int *v8; // rdx\n int v9; // esi\n int v10; // edi\n __int64 v11; // rdi\n\n result = malloc(4LL * a2);\n v7 = *a1;\n *result = *a1;\n if ( a2 <= 1 )\n {\n *a3 = 1;\n }\n else\n {\n v8 = a1 + 1;\n v9 = 1;\n do\n {\n v10 = v7;\n v7 = *v8;\n if ( *v8 != v10 )\n {\n v11 = v9++;\n result[v11] = v7;\n }\n ++v8;\n }\n while ( v8 != &a1[a2 - 2 + 2] );\n *a3 = v9;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_14E0(int *a1, int a2, int *a3) {\n uint32_t *result;\n int v7;\n int *v8;\n int v9;\n int v10;\n long long v11;\n result = malloc(4LL * a2);\n v7 = *a1;\n *result = *a1;\n if (a2 <= 1) {\n *a3 = 1;\n } else {\n v8 = a1 + 1;\n v9 = 1;\n do {\n v10 = v7;\n v7 = *v8;\n if (*v8 != v10) {\n v11 = v9++;\n result[v11] = v7;\n }\n ++v8;\n } while (v8 != &a1[a2 - 2 + 2]);\n *a3 = v9;\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2, int *a3) {\n uint32_t *result;\n int v7;\n int *v8;\n int v9;\n int v10;\n long long v11;\n result = malloc(4LL * a2);\n v7 = *a1;\n *result = *a1;\n if (a2 <= 1) {\n *a3 = 1;\n } else {\n v8 = a1 + 1;\n v9 = 1;\n do {\n v10 = v7;\n v7 = *v8;\n if (*v8 != v10) {\n v11 = v9++;\n result[v11] = v7;\n }\n ++v8;\n } while (v8 != &a1[a2 - 2 + 2]);\n *a3 = v9;\n }\n return result;\n}" + }, + { + "index": 731, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "double func0(double r, double h) {\n double l = sqrt(r * r + h * h);\n double LSA = M_PI * r * l;\n return LSA;\n}", + "test": "int main() {\n\n assert(func0(5, 12) == 204.20352248333654);\n\n assert(func0(10, 15) == 566.3586699569488);\n\n assert(func0(19, 17) == 1521.8090132193388);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmovsd %xmm0,-0x18(%rbp)\nmovsd %xmm1,-0x20(%rbp)\nmovsd -0x18(%rbp),%xmm0\nmovapd %xmm0,%xmm1\nmulsd %xmm0,%xmm1\nmovsd -0x20(%rbp),%xmm0\nmulsd %xmm0,%xmm0\naddsd %xmm1,%xmm0\ncallq 1070 \nmovq %xmm0,%rax\nmov %rax,-0x10(%rbp)\nmovsd -0x18(%rbp),%xmm1\nmovsd 0xf14(%rip),%xmm0\nmulsd %xmm1,%xmm0\nmovsd -0x10(%rbp),%xmm1\nmulsd %xmm1,%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmovsd -0x8(%rbp),%xmm0\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmovsd [rbp+var_18], xmm0\nmovsd [rbp+var_20], xmm1\nmovsd xmm0, [rbp+var_18]\nmovapd xmm1, xmm0\nmulsd xmm1, xmm0\nmovsd xmm0, [rbp+var_20]\nmulsd xmm0, xmm0\naddsd xmm1, xmm0\nmovq rax, xmm1\nmovq xmm0, rax; x\ncall _sqrt\nmovq rax, xmm0\nmov [rbp+var_10], rax\nmovsd xmm1, [rbp+var_18]\nmovsd xmm0, cs:qword_20A8\nmulsd xmm0, xmm1\nmovsd xmm1, [rbp+var_10]\nmulsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "double __fastcall func0(double a1, double a2)\n{\n return 3.141592653589793 * a1 * sqrt(a1 * a1 + a2 * a2);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmovsd [rbp+var_18], xmm0\nmovsd [rbp+var_20], xmm1\nmovsd xmm0, [rbp+var_18]\nmovapd xmm1, xmm0\nmulsd xmm1, xmm0\nmovsd xmm0, [rbp+var_20]\nmulsd xmm0, xmm0\naddsd xmm1, xmm0\nmovq rax, xmm1\nmovq xmm0, rax; x\ncall _sqrt\nmovq rax, xmm0\nmov [rbp+var_10], rax\nmovsd xmm1, [rbp+var_18]\nmovsd xmm0, cs:qword_20A8\nmulsd xmm0, xmm1\nmovsd xmm1, [rbp+var_10]\nmulsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "double __fastcall sub_1169(double a1, double a2)\n{\n return 3.141592653589793 * a1 * sqrt(a1 * a1 + a2 * a2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1169(double a1, double a2) {\n return 3.141592653589793 * a1 * sqrt(a1 * a1 + a2 * a2);\n}", + "ida_pseudo_norm": "double func0(double a1, double a2) {\n return 3.141592653589793 * a1 * sqrt(a1 * a1 + a2 * a2);\n}" + }, + { + "index": 732, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char *func0(char *text) {\n for (int i = 0; text[i] != '\\0'; i++) {\n if (text[i] == ' ' || text[i] == ',' || text[i] == '.') {\n text[i] = ':';\n }\n }\n return text;\n}", + "test": "int main() {\n\n char text1[] = \"Python language, Programming language.\";\n\n char text2[] = \"a b c,d e f\";\n\n char text3[] = \"ram reshma,ram rahim\";\n\n\n\n assert(strcmp(func0(text1), \"Python:language::Programming:language:\") == 0);\n\n assert(strcmp(func0(text2), \"a:b:c:d:e:f\") == 0);\n\n assert(strcmp(func0(text3), \"ram:reshma:ram:rahim\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11ee \nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x20,%al\nje 11da \nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x2c,%al\nje 11da \nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x2e,%al\njne 11ea \nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovb $0x3a,(%rax)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 119e \nmov -0x18(%rbp),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_4], 0\njmp short loc_11EE\nloc_119E:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njz short loc_11DA\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 2Ch ; ','\njz short loc_11DA\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 2Eh ; '.'\njnz short loc_11EA\nloc_11DA:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov byte ptr [rax], 3Ah ; ':'\nloc_11EA:\nadd [rbp+var_4], 1\nloc_11EE:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_119E\nmov rax, [rbp+var_18]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1)\n{\n int i; // [rsp+14h] [rbp-4h]\n\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n {\n if ( *(_BYTE *)(i + a1) == 32 || *(_BYTE *)(i + a1) == 44 || *(_BYTE *)(i + a1) == 46 )\n *(_BYTE *)(i + a1) = 58;\n }\n return a1;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_4], 0\njmp short loc_11EE\nloc_119E:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njz short loc_11DA\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 2Ch ; ','\njz short loc_11DA\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 2Eh ; '.'\njnz short loc_11EA\nloc_11DA:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov byte ptr [rax], 3Ah ; ':'\nloc_11EA:\nadd [rbp+var_4], 1\nloc_11EE:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_119E\nmov rax, [rbp+var_18]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1)\n{\n int i; // [rsp+14h] [rbp-4h]\n\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n {\n if ( *(_BYTE *)(i + a1) == 32 || *(_BYTE *)(i + a1) == 44 || *(_BYTE *)(i + a1) == 46 )\n *(_BYTE *)(i + a1) = 58;\n }\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1) {\n int i;\n for (i = 0; *(uint8_t *)(i + a1); ++i) {\n if (*(uint8_t *)(i + a1) == 32 || *(uint8_t *)(i + a1) == 44 ||\n *(uint8_t *)(i + a1) == 46)\n *(uint8_t *)(i + a1) = 58;\n }\n return a1;\n}", + "ida_pseudo_norm": "long long func0(long long a1) {\n int i;\n for (i = 0; *(uint8_t *)(i + a1); ++i) {\n if (*(uint8_t *)(i + a1) == 32 || *(uint8_t *)(i + a1) == 44 ||\n *(uint8_t *)(i + a1) == 46)\n *(uint8_t *)(i + a1) = 58;\n }\n return a1;\n}" + }, + { + "index": 732, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char *func0(char *text) {\n for (int i = 0; text[i] != '\\0'; i++) {\n if (text[i] == ' ' || text[i] == ',' || text[i] == '.') {\n text[i] = ':';\n }\n }\n return text;\n}", + "test": "int main() {\n\n char text1[] = \"Python language, Programming language.\";\n\n char text2[] = \"a b c,d e f\";\n\n char text3[] = \"ram reshma,ram rahim\";\n\n\n\n assert(strcmp(func0(text1), \"Python:language::Programming:language:\") == 0);\n\n assert(strcmp(func0(text2), \"a:b:c:d:e:f\") == 0);\n\n assert(strcmp(func0(text3), \"ram:reshma:ram:rahim\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%rax\nmovzbl (%rdi),%edx\ntest %dl,%dl\nje 119c \nmov %rdi,%rcx\njmp 118a \nmovb $0x3a,(%rcx)\nadd $0x1,%rcx\nmovzbl (%rcx),%edx\ntest %dl,%dl\nje 119c \nmov %edx,%esi\nand $0xfffffffd,%esi\ncmp $0x2c,%sil\nje 117c \ncmp $0x20,%dl\nje 117c \njmp 117f \nretq\n", + "ida_asm": "func0:\nendbr64\nmov rax, rdi\nmovzx edx, byte ptr [rdi]\ntest dl, dl\njz short locret_11C1\nmov rcx, rdi\nmov rsi, 500100000000h\njmp short loc_11B4\nloc_11A6:\nmov byte ptr [rcx], 3Ah ; ':'\nloc_11A9:\nadd rcx, 1\nmovzx edx, byte ptr [rcx]\ntest dl, dl\njz short locret_11C1\nloc_11B4:\ncmp dl, 2Eh ; '.'\nja short loc_11A9\nbt rsi, rdx\njb short loc_11A6\njmp short loc_11A9\nlocret_11C1:\nretn", + "ida_pseudo": "unsigned __int8 *__fastcall func0(unsigned __int8 *a1)\n{\n unsigned __int8 *result; // rax\n unsigned __int64 v2; // rdx\n _BYTE *v3; // rcx\n __int64 v4; // rsi\n\n result = a1;\n v2 = *a1;\n if ( (_BYTE)v2 )\n {\n v3 = a1;\n v4 = 0x500100000000LL;\n do\n {\n if ( (unsigned __int8)v2 <= 0x2Eu )\n {\n if ( _bittest64(&v4, v2) )\n *v3 = 58;\n }\n v2 = (unsigned __int8)*++v3;\n }\n while ( (_BYTE)v2 );\n }\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\nmov rax, rdi\nmovzx edx, byte ptr [rdi]\ntest dl, dl\njz short locret_11C1\nmov rcx, rdi\nmov rsi, 500100000000h\njmp short loc_11B4\nloc_11A6:\nmov byte ptr [rcx], 3Ah ; ':'\nloc_11A9:\nadd rcx, 1\nmovzx edx, byte ptr [rcx]\ntest dl, dl\njz short locret_11C1\nloc_11B4:\ncmp dl, 2Eh ; '.'\nja short loc_11A9\nbt rsi, rdx\njb short loc_11A6\njmp short loc_11A9\nlocret_11C1:\nretn", + "ida_strip_pseudo": "unsigned __int8 *__fastcall sub_1189(unsigned __int8 *a1)\n{\n unsigned __int8 *result; // rax\n unsigned __int64 v2; // rdx\n _BYTE *v3; // rcx\n __int64 v4; // rsi\n\n result = a1;\n v2 = *a1;\n if ( (_BYTE)v2 )\n {\n v3 = a1;\n v4 = 0x500100000000LL;\n do\n {\n if ( (unsigned __int8)v2 <= 0x2Eu )\n {\n if ( _bittest64(&v4, v2) )\n *v3 = 58;\n }\n v2 = (unsigned __int8)*++v3;\n }\n while ( (_BYTE)v2 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned char *sub_1189(unsigned char *a1) {\n unsigned char *result;\n unsigned long long v2;\n uint8_t *v3;\n long long v4;\n result = a1;\n v2 = *a1;\n if ((uint8_t)v2) {\n v3 = a1;\n v4 = 87965225189376LL;\n do {\n if ((unsigned char)v2 <= 46u) {\n if (_bittest64(&v4, v2)) *v3 = 58;\n }\n v2 = (unsigned char)*++v3;\n } while ((uint8_t)v2);\n }\n return result;\n}", + "ida_pseudo_norm": "unsigned char *func0(unsigned char *a1) {\n unsigned char *result;\n unsigned long long v2;\n uint8_t *v3;\n long long v4;\n result = a1;\n v2 = *a1;\n if ((uint8_t)v2) {\n v3 = a1;\n v4 = 87965225189376LL;\n do {\n if ((unsigned char)v2 <= 46u) {\n if (_bittest64(&v4, v2)) *v3 = 58;\n }\n v2 = (unsigned char)*++v3;\n } while ((uint8_t)v2);\n }\n return result;\n}" + }, + { + "index": 732, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char *func0(char *text) {\n for (int i = 0; text[i] != '\\0'; i++) {\n if (text[i] == ' ' || text[i] == ',' || text[i] == '.') {\n text[i] = ':';\n }\n }\n return text;\n}", + "test": "int main() {\n\n char text1[] = \"Python language, Programming language.\";\n\n char text2[] = \"a b c,d e f\";\n\n char text3[] = \"ram reshma,ram rahim\";\n\n\n\n assert(strcmp(func0(text1), \"Python:language::Programming:language:\") == 0);\n\n assert(strcmp(func0(text2), \"a:b:c:d:e:f\") == 0);\n\n assert(strcmp(func0(text3), \"ram:reshma:ram:rahim\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmovzbl (%rdi),%edx\nmov %rdi,%rax\ntest %dl,%dl\nje 1387 \nmov %rdi,%rcx\nnopl 0x0(%rax)\nmov %edx,%esi\nand $0xfffffffd,%esi\ncmp $0x2c,%sil\nje 1378 \ncmp $0x20,%dl\njne 137b \nmovb $0x3a,(%rcx)\nmovzbl 0x1(%rcx),%edx\nadd $0x1,%rcx\ntest %dl,%dl\njne 1368 \nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmovzx edx, byte ptr [rdi]\nmov rax, rdi\ntest dl, dl\njz short locret_131A\nmov rsi, 500100000000h\nmov rcx, rdi\nnop dword ptr [rax+rax+00h]\nloc_1300:\ncmp dl, 2Eh ; '.'\nja short loc_130E\nbt rsi, rdx\njnb short loc_130E\nmov byte ptr [rcx], 3Ah ; ':'\nloc_130E:\nmovzx edx, byte ptr [rcx+1]\nadd rcx, 1\ntest dl, dl\njnz short loc_1300\nlocret_131A:\nretn", + "ida_pseudo": "unsigned __int8 *__fastcall func0(unsigned __int8 *a1)\n{\n unsigned __int64 v1; // rdx\n unsigned __int8 *result; // rax\n __int64 v3; // rsi\n _BYTE *v4; // rcx\n\n v1 = *a1;\n result = a1;\n if ( (_BYTE)v1 )\n {\n v3 = 0x500100000000LL;\n v4 = a1;\n do\n {\n if ( (unsigned __int8)v1 <= 0x2Eu )\n {\n if ( _bittest64(&v3, v1) )\n *v4 = 58;\n }\n v1 = (unsigned __int8)*++v4;\n }\n while ( (_BYTE)v1 );\n }\n return result;\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\nmovzx edx, byte ptr [rdi]\nmov rax, rdi\ntest dl, dl\njz short locret_131A\nmov rsi, 500100000000h\nmov rcx, rdi\nnop dword ptr [rax+rax+00h]\nloc_1300:\ncmp dl, 2Eh ; '.'\nja short loc_130E\nbt rsi, rdx\njnb short loc_130E\nmov byte ptr [rcx], 3Ah ; ':'\nloc_130E:\nmovzx edx, byte ptr [rcx+1]\nadd rcx, 1\ntest dl, dl\njnz short loc_1300\nlocret_131A:\nretn", + "ida_strip_pseudo": "unsigned __int8 *__fastcall sub_12E0(unsigned __int8 *a1)\n{\n unsigned __int64 v1; // rdx\n unsigned __int8 *result; // rax\n __int64 v3; // rsi\n _BYTE *v4; // rcx\n\n v1 = *a1;\n result = a1;\n if ( (_BYTE)v1 )\n {\n v3 = 0x500100000000LL;\n v4 = a1;\n do\n {\n if ( (unsigned __int8)v1 <= 0x2Eu )\n {\n if ( _bittest64(&v3, v1) )\n *v4 = 58;\n }\n v1 = (unsigned __int8)*++v4;\n }\n while ( (_BYTE)v1 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned char *sub_12E0(unsigned char *a1) {\n unsigned long long v1;\n unsigned char *result;\n long long v3;\n uint8_t *v4;\n v1 = *a1;\n result = a1;\n if ((uint8_t)v1) {\n v3 = 87965225189376LL;\n v4 = a1;\n do {\n if ((unsigned char)v1 <= 46u) {\n if (_bittest64(&v3, v1)) *v4 = 58;\n }\n v1 = (unsigned char)*++v4;\n } while ((uint8_t)v1);\n }\n return result;\n}", + "ida_pseudo_norm": "unsigned char *func0(unsigned char *a1) {\n unsigned long long v1;\n unsigned char *result;\n long long v3;\n uint8_t *v4;\n v1 = *a1;\n result = a1;\n if ((uint8_t)v1) {\n v3 = 87965225189376LL;\n v4 = a1;\n do {\n if ((unsigned char)v1 <= 46u) {\n if (_bittest64(&v3, v1)) *v4 = 58;\n }\n v1 = (unsigned char)*++v4;\n } while ((uint8_t)v1);\n }\n return result;\n}" + }, + { + "index": 733, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int A[], int n, int x) {\n int left = 0, right = n - 1;\n int result = -1;\n while (left <= right) {\n int mid = left + (right - left) / 2;\n if (x == A[mid]) {\n result = mid;\n right = mid - 1;\n } else if (x < A[mid]) {\n right = mid - 1;\n } else {\n left = mid + 1;\n }\n }\n return result;\n}", + "test": "int main() {\n\n int arr1[] = {2, 5, 5, 5, 6, 6, 8, 9, 9, 9};\n\n int arr2[] = {2, 3, 5, 5, 6, 6, 8, 9, 9, 9};\n\n int arr3[] = {2, 4, 1, 5, 6, 6, 8, 9, 9, 9};\n\n\n\n assert(func0(arr1, 10, 5) == 1);\n\n assert(func0(arr2, 10, 5) == 2);\n\n assert(func0(arr3, 10, 6) == 4);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmovl $0x0,-0x10(%rbp)\nmov -0x1c(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0xc(%rbp)\nmovl $0xffffffff,-0x8(%rbp)\njmp 1208 \nmov -0xc(%rbp),%eax\nsub -0x10(%rbp),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nmov %eax,%edx\nmov -0x10(%rbp),%eax\nadd %edx,%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x20(%rbp)\njne 11d9 \nmov -0x4(%rbp),%eax\nmov %eax,-0x8(%rbp)\nmov -0x4(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0xc(%rbp)\njmp 1208 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x20(%rbp)\njge 11ff \nmov -0x4(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0xc(%rbp)\njmp 1208 \nmov -0x4(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x10(%rbp)\nmov -0x10(%rbp),%eax\ncmp -0xc(%rbp),%eax\njle 1194 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_10], 0\nmov eax, [rbp+var_1C]\nsub eax, 1\nmov [rbp+var_C], eax\nmov [rbp+var_8], 0FFFFFFFFh\njmp short loc_1208\nloc_1194:\nmov eax, [rbp+var_C]\nsub eax, [rbp+var_10]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov edx, eax\nmov eax, [rbp+var_10]\nadd eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njnz short loc_11D9\nmov eax, [rbp+var_4]\nmov [rbp+var_8], eax\nmov eax, [rbp+var_4]\nsub eax, 1\nmov [rbp+var_C], eax\njmp short loc_1208\nloc_11D9:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njge short loc_11FF\nmov eax, [rbp+var_4]\nsub eax, 1\nmov [rbp+var_C], eax\njmp short loc_1208\nloc_11FF:\nmov eax, [rbp+var_4]\nadd eax, 1\nmov [rbp+var_10], eax\nloc_1208:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_C]\njle short loc_1194\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n int v4; // [rsp+10h] [rbp-10h]\n int v5; // [rsp+14h] [rbp-Ch]\n unsigned int v6; // [rsp+18h] [rbp-8h]\n int v7; // [rsp+1Ch] [rbp-4h]\n\n v4 = 0;\n v5 = a2 - 1;\n v6 = -1;\n while ( v4 <= v5 )\n {\n v7 = (v5 - v4) / 2 + v4;\n if ( a3 == *(_DWORD *)(4LL * v7 + a1) )\n {\n v6 = (v5 - v4) / 2 + v4;\n v5 = v7 - 1;\n }\n else if ( a3 >= *(_DWORD *)(4LL * v7 + a1) )\n {\n v4 = v7 + 1;\n }\n else\n {\n v5 = v7 - 1;\n }\n }\n return v6;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_10], 0\nmov eax, [rbp+var_1C]\nsub eax, 1\nmov [rbp+var_C], eax\nmov [rbp+var_8], 0FFFFFFFFh\njmp short loc_1208\nloc_1194:\nmov eax, [rbp+var_C]\nsub eax, [rbp+var_10]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov edx, eax\nmov eax, [rbp+var_10]\nadd eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njnz short loc_11D9\nmov eax, [rbp+var_4]\nmov [rbp+var_8], eax\nmov eax, [rbp+var_4]\nsub eax, 1\nmov [rbp+var_C], eax\njmp short loc_1208\nloc_11D9:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njge short loc_11FF\nmov eax, [rbp+var_4]\nsub eax, 1\nmov [rbp+var_C], eax\njmp short loc_1208\nloc_11FF:\nmov eax, [rbp+var_4]\nadd eax, 1\nmov [rbp+var_10], eax\nloc_1208:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_C]\njle short loc_1194\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n int v4; // [rsp+10h] [rbp-10h]\n int v5; // [rsp+14h] [rbp-Ch]\n unsigned int v6; // [rsp+18h] [rbp-8h]\n int v7; // [rsp+1Ch] [rbp-4h]\n\n v4 = 0;\n v5 = a2 - 1;\n v6 = -1;\n while ( v4 <= v5 )\n {\n v7 = (v5 - v4) / 2 + v4;\n if ( a3 == *(_DWORD *)(4LL * v7 + a1) )\n {\n v6 = (v5 - v4) / 2 + v4;\n v5 = v7 - 1;\n }\n else if ( a3 >= *(_DWORD *)(4LL * v7 + a1) )\n {\n v4 = v7 + 1;\n }\n else\n {\n v5 = v7 - 1;\n }\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n int v4;\n int v5;\n unsigned int v6;\n int v7;\n v4 = 0;\n v5 = a2 - 1;\n v6 = -1;\n while (v4 <= v5) {\n v7 = (v5 - v4) / 2 + v4;\n if (a3 == *(uint32_t *)(4LL * v7 + a1)) {\n v6 = (v5 - v4) / 2 + v4;\n v5 = v7 - 1;\n } else if (a3 >= *(uint32_t *)(4LL * v7 + a1)) {\n v4 = v7 + 1;\n } else {\n v5 = v7 - 1;\n }\n }\n return v6;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n int v4;\n int v5;\n unsigned int v6;\n int v7;\n v4 = 0;\n v5 = a2 - 1;\n v6 = -1;\n while (v4 <= v5) {\n v7 = (v5 - v4) / 2 + v4;\n if (a3 == *(uint32_t *)(4LL * v7 + a1)) {\n v6 = (v5 - v4) / 2 + v4;\n v5 = v7 - 1;\n } else if (a3 >= *(uint32_t *)(4LL * v7 + a1)) {\n v4 = v7 + 1;\n } else {\n v5 = v7 - 1;\n }\n }\n return v6;\n}" + }, + { + "index": 733, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int A[], int n, int x) {\n int left = 0, right = n - 1;\n int result = -1;\n while (left <= right) {\n int mid = left + (right - left) / 2;\n if (x == A[mid]) {\n result = mid;\n right = mid - 1;\n } else if (x < A[mid]) {\n right = mid - 1;\n } else {\n left = mid + 1;\n }\n }\n return result;\n}", + "test": "int main() {\n\n int arr1[] = {2, 5, 5, 5, 6, 6, 8, 9, 9, 9};\n\n int arr2[] = {2, 3, 5, 5, 6, 6, 8, 9, 9, 9};\n\n int arr3[] = {2, 4, 1, 5, 6, 6, 8, 9, 9, 9};\n\n\n\n assert(func0(arr1, 10, 5) == 1);\n\n assert(func0(arr2, 10, 5) == 2);\n\n assert(func0(arr3, 10, 6) == 4);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x1,%esi\njs 11b4 \nmov $0xffffffff,%r9d\nmov $0x0,%ecx\njmp 1189 \nlea -0x1(%rax),%esi\nmov %eax,%r9d\ncmp %esi,%ecx\njg 11ba \nmov %esi,%r8d\nsub %ecx,%r8d\nmov %r8d,%eax\nshr $0x1f,%eax\nadd %r8d,%eax\nsar %eax\nadd %ecx,%eax\nmovslq %eax,%r8\nmov (%rdi,%r8,4),%r8d\ncmp %edx,%r8d\nje 117f \njle 11af \nlea -0x1(%rax),%esi\njmp 1185 \nlea 0x1(%rax),%ecx\njmp 1185 \nmov $0xffffffff,%r9d\nmov %r9d,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov r8, rdi\nsub esi, 1\njs short loc_11B2\nmov r9d, 0FFFFFFFFh\nmov ecx, 0\njmp short loc_118C\nloc_1182:\nlea esi, [rax-1]\nmov r9d, eax\nloc_1188:\ncmp ecx, esi\njg short loc_11B8\nloc_118C:\nmov edi, esi\nsub edi, ecx\nmov eax, edi\nshr eax, 1Fh\nadd eax, edi\nsar eax, 1\nadd eax, ecx\nmovsxd rdi, eax\nmov edi, [r8+rdi*4]\ncmp edi, edx\njz short loc_1182\njle short loc_11AD\nlea esi, [rax-1]\njmp short loc_1188\nloc_11AD:\nlea ecx, [rax+1]\njmp short loc_1188\nloc_11B2:\nmov r9d, 0FFFFFFFFh\nloc_11B8:\nmov eax, r9d\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n int v4; // esi\n unsigned int v5; // r9d\n int v6; // ecx\n signed int v7; // eax\n int v8; // edi\n\n v4 = a2 - 1;\n if ( v4 < 0 )\n {\n return (unsigned int)-1;\n }\n else\n {\n v5 = -1;\n v6 = 0;\n do\n {\n v7 = v6 + (v4 - v6) / 2;\n v8 = *(_DWORD *)(a1 + 4LL * v7);\n if ( v8 == a3 )\n {\n v4 = v7 - 1;\n v5 = v7;\n }\n else if ( v8 <= a3 )\n {\n v6 = v7 + 1;\n }\n else\n {\n v4 = v7 - 1;\n }\n }\n while ( v6 <= v4 );\n }\n return v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov r8, rdi\nsub esi, 1\njs short loc_11B2\nmov r9d, 0FFFFFFFFh\nmov ecx, 0\njmp short loc_118C\nloc_1182:\nlea esi, [rax-1]\nmov r9d, eax\nloc_1188:\ncmp ecx, esi\njg short loc_11B8\nloc_118C:\nmov edi, esi\nsub edi, ecx\nmov eax, edi\nshr eax, 1Fh\nadd eax, edi\nsar eax, 1\nadd eax, ecx\nmovsxd rdi, eax\nmov edi, [r8+rdi*4]\ncmp edi, edx\njz short loc_1182\njle short loc_11AD\nlea esi, [rax-1]\njmp short loc_1188\nloc_11AD:\nlea ecx, [rax+1]\njmp short loc_1188\nloc_11B2:\nmov r9d, 0FFFFFFFFh\nloc_11B8:\nmov eax, r9d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n int v4; // esi\n unsigned int v5; // r9d\n int v6; // ecx\n signed int v7; // eax\n int v8; // edi\n\n v4 = a2 - 1;\n if ( v4 < 0 )\n {\n return (unsigned int)-1;\n }\n else\n {\n v5 = -1;\n v6 = 0;\n do\n {\n v7 = v6 + (v4 - v6) / 2;\n v8 = *(_DWORD *)(a1 + 4LL * v7);\n if ( v8 == a3 )\n {\n v4 = v7 - 1;\n v5 = v7;\n }\n else if ( v8 <= a3 )\n {\n v6 = v7 + 1;\n }\n else\n {\n v4 = v7 - 1;\n }\n }\n while ( v6 <= v4 );\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n int v4;\n unsigned int v5;\n int v6;\n signed int v7;\n int v8;\n v4 = a2 - 1;\n if (v4 < 0) {\n return (unsigned int)-1;\n } else {\n v5 = -1;\n v6 = 0;\n do {\n v7 = v6 + (v4 - v6) / 2;\n v8 = *(uint32_t *)(a1 + 4LL * v7);\n if (v8 == a3) {\n v4 = v7 - 1;\n v5 = v7;\n } else if (v8 <= a3) {\n v6 = v7 + 1;\n } else {\n v4 = v7 - 1;\n }\n } while (v6 <= v4);\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n int v4;\n unsigned int v5;\n int v6;\n signed int v7;\n int v8;\n v4 = a2 - 1;\n if (v4 < 0) {\n return (unsigned int)-1;\n } else {\n v5 = -1;\n v6 = 0;\n do {\n v7 = v6 + (v4 - v6) / 2;\n v8 = *(uint32_t *)(a1 + 4LL * v7);\n if (v8 == a3) {\n v4 = v7 - 1;\n v5 = v7;\n } else if (v8 <= a3) {\n v6 = v7 + 1;\n } else {\n v4 = v7 - 1;\n }\n } while (v6 <= v4);\n }\n return v5;\n}" + }, + { + "index": 733, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int A[], int n, int x) {\n int left = 0, right = n - 1;\n int result = -1;\n while (left <= right) {\n int mid = left + (right - left) / 2;\n if (x == A[mid]) {\n result = mid;\n right = mid - 1;\n } else if (x < A[mid]) {\n right = mid - 1;\n } else {\n left = mid + 1;\n }\n }\n return result;\n}", + "test": "int main() {\n\n int arr1[] = {2, 5, 5, 5, 6, 6, 8, 9, 9, 9};\n\n int arr2[] = {2, 3, 5, 5, 6, 6, 8, 9, 9, 9};\n\n int arr3[] = {2, 4, 1, 5, 6, 6, 8, 9, 9, 9};\n\n\n\n assert(func0(arr1, 10, 5) == 1);\n\n assert(func0(arr2, 10, 5) == 2);\n\n assert(func0(arr3, 10, 6) == 4);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov $0xffffffff,%r9d\nsub $0x1,%esi\njs 13dc \nxor %ecx,%ecx\njmp 13c1 \nnopl 0x0(%rax,%rax,1)\njle 13e0 \nlea -0x1(%rax),%esi\ncmp %ecx,%esi\njl 13dc \nmov %esi,%eax\nsub %ecx,%eax\nsar %eax\nadd %ecx,%eax\nmovslq %eax,%r8\ncmp %edx,(%rdi,%r8,4)\njne 13b8 \nlea -0x1(%rax),%esi\nmov %eax,%r9d\ncmp %ecx,%esi\njge 13c1 \nmov %r9d,%eax\nretq\nlea 0x1(%rax),%ecx\njmp 13bd \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmov r9d, 0FFFFFFFFh\nsub esi, 1\njs short loc_12EC\nxor ecx, ecx\njmp short loc_12D1\nloc_12C8:\njge short loc_12F0\nlea esi, [rax-1]\nloc_12CD:\ncmp ecx, esi\njg short loc_12EC\nloc_12D1:\nmov eax, esi\nsub eax, ecx\nsar eax, 1\nadd eax, ecx\nmovsxd r8, eax\ncmp edx, [rdi+r8*4]\njnz short loc_12C8\nlea esi, [rax-1]\nmov r9d, eax\ncmp ecx, esi\njle short loc_12D1\nloc_12EC:\nmov eax, r9d\nretn\nloc_12F0:\nlea ecx, [rax+1]\njmp short loc_12CD", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n unsigned int v3; // r9d\n int v4; // esi\n int v5; // ecx\n signed int v6; // eax\n\n v3 = -1;\n v4 = a2 - 1;\n if ( v4 >= 0 )\n {\n v5 = 0;\n do\n {\n while ( 1 )\n {\n v6 = v5 + ((v4 - v5) >> 1);\n if ( a3 != *(_DWORD *)(a1 + 4LL * v6) )\n break;\n v4 = v6 - 1;\n v3 = v6;\n if ( v5 > v6 - 1 )\n return v3;\n }\n if ( a3 >= *(_DWORD *)(a1 + 4LL * v6) )\n v5 = v6 + 1;\n else\n v4 = v6 - 1;\n }\n while ( v5 <= v4 );\n }\n return v3;\n}", + "ida_strip_asm": "sub_12B0:\nendbr64\nmov r9d, 0FFFFFFFFh\nsub esi, 1\njs short loc_12EC\nxor ecx, ecx\njmp short loc_12D1\nloc_12C8:\njge short loc_12F0\nlea esi, [rax-1]\nloc_12CD:\ncmp ecx, esi\njg short loc_12EC\nloc_12D1:\nmov eax, esi\nsub eax, ecx\nsar eax, 1\nadd eax, ecx\nmovsxd r8, eax\ncmp edx, [rdi+r8*4]\njnz short loc_12C8\nlea esi, [rax-1]\nmov r9d, eax\ncmp ecx, esi\njle short loc_12D1\nloc_12EC:\nmov eax, r9d\nretn\nloc_12F0:\nlea ecx, [rax+1]\njmp short loc_12CD", + "ida_strip_pseudo": "__int64 __fastcall sub_12B0(__int64 a1, int a2, int a3)\n{\n unsigned int v3; // r9d\n int v4; // esi\n int v5; // ecx\n signed int v6; // eax\n\n v3 = -1;\n v4 = a2 - 1;\n if ( v4 >= 0 )\n {\n v5 = 0;\n do\n {\n while ( 1 )\n {\n v6 = v5 + ((v4 - v5) >> 1);\n if ( a3 != *(_DWORD *)(a1 + 4LL * v6) )\n break;\n v4 = v6 - 1;\n v3 = v6;\n if ( v5 > v6 - 1 )\n return v3;\n }\n if ( a3 >= *(_DWORD *)(a1 + 4LL * v6) )\n v5 = v6 + 1;\n else\n v4 = v6 - 1;\n }\n while ( v5 <= v4 );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12B0(long long a1, int a2, int a3) {\n unsigned int v3;\n int v4;\n int v5;\n signed int v6;\n v3 = -1;\n v4 = a2 - 1;\n if (v4 >= 0) {\n v5 = 0;\n do {\n while (1) {\n v6 = v5 + ((v4 - v5) >> 1);\n if (a3 != *(uint32_t *)(a1 + 4LL * v6)) break;\n v4 = v6 - 1;\n v3 = v6;\n if (v5 > v6 - 1) return v3;\n }\n if (a3 >= *(uint32_t *)(a1 + 4LL * v6))\n v5 = v6 + 1;\n else\n v4 = v6 - 1;\n } while (v5 <= v4);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n unsigned int v3;\n int v4;\n int v5;\n signed int v6;\n v3 = -1;\n v4 = a2 - 1;\n if (v4 >= 0) {\n v5 = 0;\n do {\n while (1) {\n v6 = v5 + ((v4 - v5) >> 1);\n if (a3 != *(uint32_t *)(a1 + 4LL * v6)) break;\n v4 = v6 - 1;\n v3 = v6;\n if (v5 > v6 - 1) return v3;\n }\n if (a3 >= *(uint32_t *)(a1 + 4LL * v6))\n v5 = v6 + 1;\n else\n v4 = v6 - 1;\n } while (v5 <= v4);\n }\n return v3;\n}" + }, + { + "index": 734, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int ans = 0, res = 0;\n int i = n - 1;\n while (i >= 0) {\n int incr = arr[i] * (1 + res);\n ans += incr;\n res = incr;\n i--;\n }\n return ans;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3};\n\n int arr2[] = {1, 2};\n\n int arr3[] = {1, 2, 3, 4};\n\n assert(func0(arr1, 3) == 20);\n\n assert(func0(arr2, 2) == 5);\n\n assert(func0(arr3, 4) == 84);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\nmov -0x1c(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0x8(%rbp)\njmp 11c3 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov -0xc(%rbp),%edx\nadd $0x1,%edx\nimul %edx,%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nadd %eax,-0x10(%rbp)\nmov -0x4(%rbp),%eax\nmov %eax,-0xc(%rbp)\nsubl $0x1,-0x8(%rbp)\ncmpl $0x0,-0x8(%rbp)\njns 1191 \nmov -0x10(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\nmov eax, [rbp+var_1C]\nsub eax, 1\nmov [rbp+var_8], eax\njmp short loc_11C3\nloc_1191:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_C]\nadd edx, 1\nimul eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\nadd [rbp+var_10], eax\nmov eax, [rbp+var_4]\nmov [rbp+var_C], eax\nsub [rbp+var_8], 1\nloc_11C3:\ncmp [rbp+var_8], 0\njns short loc_1191\nmov eax, [rbp+var_10]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+Ch] [rbp-10h]\n int v4; // [rsp+10h] [rbp-Ch]\n int i; // [rsp+14h] [rbp-8h]\n\n v3 = 0;\n v4 = 0;\n for ( i = a2 - 1; i >= 0; --i )\n {\n v3 += (v4 + 1) * *(_DWORD *)(4LL * i + a1);\n v4 = (v4 + 1) * *(_DWORD *)(4LL * i + a1);\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\nmov eax, [rbp+var_1C]\nsub eax, 1\nmov [rbp+var_8], eax\njmp short loc_11C3\nloc_1191:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_C]\nadd edx, 1\nimul eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\nadd [rbp+var_10], eax\nmov eax, [rbp+var_4]\nmov [rbp+var_C], eax\nsub [rbp+var_8], 1\nloc_11C3:\ncmp [rbp+var_8], 0\njns short loc_1191\nmov eax, [rbp+var_10]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+Ch] [rbp-10h]\n int v4; // [rsp+10h] [rbp-Ch]\n int i; // [rsp+14h] [rbp-8h]\n\n v3 = 0;\n v4 = 0;\n for ( i = a2 - 1; i >= 0; --i )\n {\n v3 += (v4 + 1) * *(_DWORD *)(4LL * i + a1);\n v4 = (v4 + 1) * *(_DWORD *)(4LL * i + a1);\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n unsigned int v3;\n int v4;\n int i;\n v3 = 0;\n v4 = 0;\n for (i = a2 - 1; i >= 0; --i) {\n v3 += (v4 + 1) * *(uint32_t *)(4LL * i + a1);\n v4 = (v4 + 1) * *(uint32_t *)(4LL * i + a1);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int v4;\n int i;\n v3 = 0;\n v4 = 0;\n for (i = a2 - 1; i >= 0; --i) {\n v3 += (v4 + 1) * *(uint32_t *)(4LL * i + a1);\n v4 = (v4 + 1) * *(uint32_t *)(4LL * i + a1);\n }\n return v3;\n}" + }, + { + "index": 734, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int ans = 0, res = 0;\n int i = n - 1;\n while (i >= 0) {\n int incr = arr[i] * (1 + res);\n ans += incr;\n res = incr;\n i--;\n }\n return ans;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3};\n\n int arr2[] = {1, 2};\n\n int arr3[] = {1, 2, 3, 4};\n\n assert(func0(arr1, 3) == 20);\n\n assert(func0(arr2, 2) == 5);\n\n assert(func0(arr3, 4) == 84);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x1,%esi\njs 1193 \nmovslq %esi,%rsi\nmov $0x0,%eax\nmov $0x0,%edx\nadd $0x1,%eax\nimul (%rdi,%rsi,4),%eax\nadd %eax,%edx\nsub $0x1,%rsi\ntest %esi,%esi\njns 117f \nmov %edx,%eax\nretq\nmov $0x0,%edx\njmp 1190 \n", + "ida_asm": "func0:\nendbr64\nsub esi, 1\njs short loc_1193\nmovsxd rsi, esi\nmov eax, 0\nmov edx, 0\nloc_117F:\nadd eax, 1\nimul eax, [rdi+rsi*4]\nadd edx, eax\nsub rsi, 1\ntest esi, esi\njns short loc_117F\nloc_1190:\nmov eax, edx\nretn\nloc_1193:\nmov edx, 0\njmp short loc_1190", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // rsi\n int v3; // eax\n unsigned int v4; // edx\n\n LODWORD(v2) = a2 - 1;\n if ( (int)v2 < 0 )\n {\n return 0;\n }\n else\n {\n v2 = (int)v2;\n v3 = 0;\n v4 = 0;\n do\n {\n v3 = *(_DWORD *)(a1 + 4 * v2) * (v3 + 1);\n v4 += v3;\n --v2;\n }\n while ( (int)v2 >= 0 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nsub esi, 1\njs short loc_1193\nmovsxd rsi, esi\nmov eax, 0\nmov edx, 0\nloc_117F:\nadd eax, 1\nimul eax, [rdi+rsi*4]\nadd edx, eax\nsub rsi, 1\ntest esi, esi\njns short loc_117F\nloc_1190:\nmov eax, edx\nretn\nloc_1193:\nmov edx, 0\njmp short loc_1190", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n __int64 v2; // rsi\n int v3; // eax\n unsigned int v4; // edx\n\n LODWORD(v2) = a2 - 1;\n if ( (int)v2 < 0 )\n {\n return 0;\n }\n else\n {\n v2 = (int)v2;\n v3 = 0;\n v4 = 0;\n do\n {\n v3 = *(_DWORD *)(a1 + 4 * v2) * (v3 + 1);\n v4 += v3;\n --v2;\n }\n while ( (int)v2 >= 0 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n long long v2;\n int v3;\n unsigned int v4;\n LODWORD(v2) = a2 - 1;\n if ((int)v2 < 0) {\n return 0;\n } else {\n v2 = (int)v2;\n v3 = 0;\n v4 = 0;\n do {\n v3 = *(uint32_t *)(a1 + 4 * v2) * (v3 + 1);\n v4 += v3;\n --v2;\n } while ((int)v2 >= 0);\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n int v3;\n unsigned int v4;\n LODWORD(v2) = a2 - 1;\n if ((int)v2 < 0) {\n return 0;\n } else {\n v2 = (int)v2;\n v3 = 0;\n v4 = 0;\n do {\n v3 = *(uint32_t *)(a1 + 4 * v2) * (v3 + 1);\n v4 += v3;\n --v2;\n } while ((int)v2 >= 0);\n }\n return v4;\n}" + }, + { + "index": 735, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\nint set_middle_bits(int n) {\n\n n |= n >> 1;\n\n n |= n >> 2;\n\n n |= n >> 4;\n\n n |= n >> 8;\n\n n |= n >> 16;\n\n return (n >> 1) ^ 1;\n\n}\n\n\n\n", + "func": "int func0(int n) {\n if (n == 1) {\n return 1;\n }\n return n ^ set_middle_bits(n);\n}", + "test": "int main() {\n\n assert(func0(9) == 15);\n\n assert(func0(10) == 12);\n\n assert(func0(11) == 13);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x8,%rsp\nmov %edi,-0x4(%rbp)\ncmpl $0x1,-0x4(%rbp)\njne 11a6 \nmov $0x1,%eax\njmp 11b3 \nmov -0x4(%rbp),%eax\nmov %eax,%edi\ncallq 1149 \nxor -0x4(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 8\nmov [rbp+var_4], edi\ncmp [rbp+var_4], 1\njnz short loc_11A6\nmov eax, 1\njmp short locret_11B3\nloc_11A6:\nmov eax, [rbp+var_4]\nmov edi, eax\ncall set_middle_bits\nxor eax, [rbp+var_4]\nlocret_11B3:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1)\n{\n if ( a1 == 1 )\n return 1LL;\n else\n return a1 ^ (unsigned int)set_middle_bits(a1);\n}", + "ida_strip_asm": "sub_118A:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 8\nmov [rbp+var_4], edi\ncmp [rbp+var_4], 1\njnz short loc_11A6\nmov eax, 1\njmp short locret_11B3\nloc_11A6:\nmov eax, [rbp+var_4]\nmov edi, eax\ncall sub_1149\nxor eax, [rbp+var_4]\nlocret_11B3:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_118A(unsigned int a1)\n{\n if ( a1 == 1 )\n return 1LL;\n else\n return a1 ^ (unsigned int)sub_1149(a1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_118A(unsigned int a1) {\n if (a1 == 1)\n return 1LL;\n else\n return a1 ^ (unsigned int)sub_1149(a1);\n}", + "ida_pseudo_norm": "long long func0(unsigned int a1) {\n if (a1 == 1)\n return 1LL;\n else\n return a1 ^ (unsigned int)set_middle_bits(a1);\n}" + }, + { + "index": 736, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int a[], int n, int x) {\n int l = 0;\n int r = n;\n while (l < r) {\n int mid = (l + r) / 2;\n if (a[mid] < x)\n l = mid + 1;\n else\n r = mid;\n }\n return l;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 4, 5};\n\n assert(func0(arr1, 4, 6) == 4);\n\n assert(func0(arr1, 4, 3) == 2);\n\n int arr2[] = {1, 2, 4, 5};\n\n assert(func0(arr2, 4, 7) == 4);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmovl $0x0,-0xc(%rbp)\nmov -0x1c(%rbp),%eax\nmov %eax,-0x8(%rbp)\njmp 11ca \nmov -0xc(%rbp),%edx\nmov -0x8(%rbp),%eax\nadd %edx,%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x20(%rbp)\njle 11c4 \nmov -0x4(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0xc(%rbp)\njmp 11ca \nmov -0x4(%rbp),%eax\nmov %eax,-0x8(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x8(%rbp),%eax\njl 118a \nmov -0xc(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_C], 0\nmov eax, [rbp+var_1C]\nmov [rbp+var_8], eax\njmp short loc_11CA\nloc_118A:\nmov edx, [rbp+var_C]\nmov eax, [rbp+var_8]\nadd eax, edx\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njle short loc_11C4\nmov eax, [rbp+var_4]\nadd eax, 1\nmov [rbp+var_C], eax\njmp short loc_11CA\nloc_11C4:\nmov eax, [rbp+var_4]\nmov [rbp+var_8], eax\nloc_11CA:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_8]\njl short loc_118A\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n int v4; // [rsp+14h] [rbp-Ch]\n\n v4 = 0;\n while ( v4 < a2 )\n {\n if ( a3 <= *(_DWORD *)(4LL * ((v4 + a2) / 2) + a1) )\n a2 = (v4 + a2) / 2;\n else\n v4 = (v4 + a2) / 2 + 1;\n }\n return (unsigned int)v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_C], 0\nmov eax, [rbp+var_1C]\nmov [rbp+var_8], eax\njmp short loc_11CA\nloc_118A:\nmov edx, [rbp+var_C]\nmov eax, [rbp+var_8]\nadd eax, edx\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njle short loc_11C4\nmov eax, [rbp+var_4]\nadd eax, 1\nmov [rbp+var_C], eax\njmp short loc_11CA\nloc_11C4:\nmov eax, [rbp+var_4]\nmov [rbp+var_8], eax\nloc_11CA:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_8]\njl short loc_118A\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n int v4; // [rsp+14h] [rbp-Ch]\n\n v4 = 0;\n while ( v4 < a2 )\n {\n if ( a3 <= *(_DWORD *)(4LL * ((v4 + a2) / 2) + a1) )\n a2 = (v4 + a2) / 2;\n else\n v4 = (v4 + a2) / 2 + 1;\n }\n return (unsigned int)v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n int v4;\n v4 = 0;\n while (v4 < a2) {\n if (a3 <= *(uint32_t *)(4LL * ((v4 + a2) / 2) + a1))\n a2 = (v4 + a2) / 2;\n else\n v4 = (v4 + a2) / 2 + 1;\n }\n return (unsigned int)v4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n int v4;\n v4 = 0;\n while (v4 < a2) {\n if (a3 <= *(uint32_t *)(4LL * ((v4 + a2) / 2) + a1))\n a2 = (v4 + a2) / 2;\n else\n v4 = (v4 + a2) / 2 + 1;\n }\n return (unsigned int)v4;\n}" + }, + { + "index": 736, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int a[], int n, int x) {\n int l = 0;\n int r = n;\n while (l < r) {\n int mid = (l + r) / 2;\n if (a[mid] < x)\n l = mid + 1;\n else\n r = mid;\n }\n return l;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 4, 5};\n\n assert(func0(arr1, 4, 6) == 4);\n\n assert(func0(arr1, 4, 3) == 2);\n\n int arr2[] = {1, 2, 4, 5};\n\n assert(func0(arr2, 4, 7) == 4);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x0,%r8d\ncmp %r8d,%esi\njle 1197 \nlea (%rsi,%r8,1),%ecx\nmov %ecx,%eax\nshr $0x1f,%eax\nadd %ecx,%eax\nsar %eax\nmovslq %eax,%rcx\ncmp %edx,(%rdi,%rcx,4)\njl 1191 \nmov %eax,%esi\njmp 1173 \nlea 0x1(%rax),%r8d\njmp 1173 \nmov %r8d,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov r8d, 0\nloc_1173:\ncmp esi, r8d\njle short loc_1197\nlea ecx, [rsi+r8]\nmov eax, ecx\nshr eax, 1Fh\nadd eax, ecx\nsar eax, 1\nmovsxd rcx, eax\ncmp [rdi+rcx*4], edx\njl short loc_1191\nmov esi, eax\njmp short loc_1173\nloc_1191:\nlea r8d, [rax+1]\njmp short loc_1173\nloc_1197:\nmov eax, r8d\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n int v3; // r8d\n int v4; // eax\n\n v3 = 0;\n while ( a2 > v3 )\n {\n v4 = (a2 + v3) / 2;\n if ( *(_DWORD *)(a1 + 4LL * v4) < a3 )\n v3 = v4 + 1;\n else\n a2 = (a2 + v3) / 2;\n }\n return (unsigned int)v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov r8d, 0\nloc_1173:\ncmp esi, r8d\njle short loc_1197\nlea ecx, [rsi+r8]\nmov eax, ecx\nshr eax, 1Fh\nadd eax, ecx\nsar eax, 1\nmovsxd rcx, eax\ncmp [rdi+rcx*4], edx\njl short loc_1191\nmov esi, eax\njmp short loc_1173\nloc_1191:\nlea r8d, [rax+1]\njmp short loc_1173\nloc_1197:\nmov eax, r8d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n int v3; // r8d\n int v4; // eax\n\n v3 = 0;\n while ( a2 > v3 )\n {\n v4 = (a2 + v3) / 2;\n if ( *(_DWORD *)(a1 + 4LL * v4) < a3 )\n v3 = v4 + 1;\n else\n a2 = (a2 + v3) / 2;\n }\n return (unsigned int)v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n int v3;\n int v4;\n v3 = 0;\n while (a2 > v3) {\n v4 = (a2 + v3) / 2;\n if (*(uint32_t *)(a1 + 4LL * v4) < a3)\n v3 = v4 + 1;\n else\n a2 = (a2 + v3) / 2;\n }\n return (unsigned int)v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n int v3;\n int v4;\n v3 = 0;\n while (a2 > v3) {\n v4 = (a2 + v3) / 2;\n if (*(uint32_t *)(a1 + 4LL * v4) < a3)\n v3 = v4 + 1;\n else\n a2 = (a2 + v3) / 2;\n }\n return (unsigned int)v3;\n}" + }, + { + "index": 737, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* string) {\n regex_t regex;\n int result;\n char* pattern = \"^[aeiouAEIOU][A-Za-z0-9_]*\";\n regcomp(®ex, pattern, REG_EXTENDED | REG_NOSUB);\n result = regexec(®ex, string, 0, NULL, 0);\n regfree(®ex);\n if (result == 0) {\n return \"Valid\";\n } else {\n return \"Invalid\";\n }\n}", + "test": "int main() {\n\n assert(func0(\"annie\") == \"Valid\");\n\n assert(func0(\"dawood\") == \"Invalid\");\n\n assert(func0(\"Else\") == \"Valid\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x70,%rsp\nmov %rdi,-0x68(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0xe19(%rip),%rax\nmov %rax,-0x58(%rbp)\nmov -0x58(%rbp),%rcx\nlea -0x50(%rbp),%rax\nmov $0x9,%edx\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 10c0 \nmov -0x68(%rbp),%rsi\nlea -0x50(%rbp),%rax\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rax,%rdi\ncallq 10d0 \nmov %eax,-0x5c(%rbp)\nlea -0x50(%rbp),%rax\nmov %rax,%rdi\ncallq 1090 \ncmpl $0x0,-0x5c(%rbp)\njne 1249 \nlea 0xddc(%rip),%rax\njmp 1250 \nlea 0xdd9(%rip),%rax\nmov -0x8(%rbp),%rdx\nxor %fs:0x28,%rdx\nje 1264 \ncallq 10a0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aAeiouaeiouAZaZ; \"^[aeiouAEIOU][A-Za-z0-9_]*\"\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 9; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_5C], eax\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\ncmp [rbp+var_5C], 0\njnz short loc_1249\nlea rax, aValid; \"Valid\"\njmp short loc_1250\nloc_1249:\nlea rax, aInvalid; \"Invalid\"\nloc_1250:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1264\ncall ___stack_chk_fail\nlocret_1264:\nleave\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n int v2; // [rsp+14h] [rbp-5Ch]\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n unsigned __int64 v4; // [rsp+68h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n regcomp(&preg, \"^[aeiouAEIOU][A-Za-z0-9_]*\", 9);\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if ( v2 )\n return \"Invalid\";\n else\n return \"Valid\";\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aAeiouaeiouAZaZ; \"^[aeiouAEIOU][A-Za-z0-9_]*\"\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 9; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_5C], eax\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\ncmp [rbp+var_5C], 0\njnz short loc_1249\nlea rax, aValid; \"Valid\"\njmp short loc_1250\nloc_1249:\nlea rax, aInvalid; \"Invalid\"\nloc_1250:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1264\ncall ___stack_chk_fail\nlocret_1264:\nleave\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_11C9(const char *a1)\n{\n int v2; // [rsp+14h] [rbp-5Ch]\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n unsigned __int64 v4; // [rsp+68h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n regcomp(&preg, \"^[aeiouAEIOU][A-Za-z0-9_]*\", 9);\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if ( v2 )\n return \"Invalid\";\n else\n return \"Valid\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_11C9(const char *a1) {\n int v2;\n regex_t preg;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n regcomp(&preg, \"^[aeiouAEIOU][A-Za-z0-9_]*\", 9);\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if (v2)\n return \"Invalid\";\n else\n return \"Valid\";\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n int v2;\n regex_t preg;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n regcomp(&preg, \"^[aeiouAEIOU][A-Za-z0-9_]*\", 9);\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if (v2)\n return \"Invalid\";\n else\n return \"Valid\";\n}" + }, + { + "index": 737, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* string) {\n regex_t regex;\n int result;\n char* pattern = \"^[aeiouAEIOU][A-Za-z0-9_]*\";\n regcomp(®ex, pattern, REG_EXTENDED | REG_NOSUB);\n result = regexec(®ex, string, 0, NULL, 0);\n regfree(®ex);\n if (result == 0) {\n return \"Valid\";\n } else {\n return \"Invalid\";\n }\n}", + "test": "int main() {\n\n assert(func0(\"annie\") == \"Valid\");\n\n assert(func0(\"dawood\") == \"Invalid\");\n\n assert(func0(\"Else\") == \"Valid\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x58,%rsp\nmov %rdi,%rbx\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%rbp\nmov $0x9,%edx\nlea 0xe1d(%rip),%rsi\nmov %rbp,%rdi\ncallq 10c0 \nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rbx,%rsi\nmov %rbp,%rdi\ncallq 10d0 \nmov %eax,%ebx\nmov %rbp,%rdi\ncallq 1090 \ntest %ebx,%ebx\nlea 0xdd9(%rip),%rax\nlea 0xdd8(%rip),%rdx\ncmovne %rdx,%rax\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 124d \nadd $0x58,%rsp\npop %rbx\npop %rbp\nretq\ncallq 10a0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov edx, 9; cflags\nlea rsi, pattern; \"^[aeiouAEIOU][A-Za-z0-9_]*\"\nmov rdi, rbp; preg\ncall _regcomp\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov ebx, eax\nmov rdi, rbp; preg\ncall _regfree\ntest ebx, ebx\nlea rax, aInvalid; \"Invalid\"\nlea rdx, aValid; \"Valid\"\ncmovz rax, rdx\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_124D\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_124D:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // ebx\n const char *result; // rax\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \"^[aeiouAEIOU][A-Za-z0-9_]*\", 9);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Invalid\";\n if ( !v1 )\n return \"Valid\";\n return result;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov edx, 9; cflags\nlea rsi, pattern; \"^[aeiouAEIOU][A-Za-z0-9_]*\"\nmov rdi, rbp; preg\ncall _regcomp\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov ebx, eax\nmov rdi, rbp; preg\ncall _regfree\ntest ebx, ebx\nlea rax, aInvalid; \"Invalid\"\nlea rdx, aValid; \"Valid\"\ncmovz rax, rdx\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_124D\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_124D:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_11C9(char *string)\n{\n int v1; // ebx\n const char *result; // rax\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \"^[aeiouAEIOU][A-Za-z0-9_]*\", 9);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Invalid\";\n if ( !v1 )\n return \"Valid\";\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_11C9(char *string) {\n int v1;\n const char *result;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \"^[aeiouAEIOU][A-Za-z0-9_]*\", 9);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Invalid\";\n if (!v1) return \"Valid\";\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n const char *result;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \"^[aeiouAEIOU][A-Za-z0-9_]*\", 9);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Invalid\";\n if (!v1) return \"Valid\";\n return result;\n}" + }, + { + "index": 737, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* string) {\n regex_t regex;\n int result;\n char* pattern = \"^[aeiouAEIOU][A-Za-z0-9_]*\";\n regcomp(®ex, pattern, REG_EXTENDED | REG_NOSUB);\n result = regexec(®ex, string, 0, NULL, 0);\n regfree(®ex);\n if (result == 0) {\n return \"Valid\";\n } else {\n return \"Invalid\";\n }\n}", + "test": "int main() {\n\n assert(func0(\"annie\") == \"Valid\");\n\n assert(func0(\"dawood\") == \"Invalid\");\n\n assert(func0(\"Else\") == \"Valid\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov $0x9,%edx\nmov %rdi,%r12\nlea 0xd7d(%rip),%rsi\npush %rbp\npush %rbx\nsub $0x50,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%rbp\nmov %rbp,%rdi\ncallq 10c0 \nxor %ecx,%ecx\nxor %edx,%edx\nxor %r8d,%r8d\nmov %r12,%rsi\nmov %rbp,%rdi\ncallq 10d0 \nmov %rbp,%rdi\nmov %eax,%ebx\ncallq 1090 \ntest %ebx,%ebx\nlea 0xd29(%rip),%rax\nlea 0xd28(%rip),%rdx\ncmovne %rdx,%rax\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 12ff \nadd $0x50,%rsp\npop %rbx\npop %rbp\npop %r12\nretq\ncallq 10a0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov edx, 9; cflags\nlea rsi, pattern; \"^[aeiouAEIOU][A-Za-z0-9_]*\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, aInvalid; \"Invalid\"\nlea rdx, aValid; \"Valid\"\ncmovz rax, rdx\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_12FB\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_12FB:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // ebx\n const char *result; // rax\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \"^[aeiouAEIOU][A-Za-z0-9_]*\", 9);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Invalid\";\n if ( !v1 )\n return \"Valid\";\n return result;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\npush rbp\nmov edx, 9; cflags\nlea rsi, pattern; \"^[aeiouAEIOU][A-Za-z0-9_]*\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, aInvalid; \"Invalid\"\nlea rdx, aValid; \"Valid\"\ncmovz rax, rdx\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_12FB\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_12FB:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_1280(char *string)\n{\n int v1; // ebx\n const char *result; // rax\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \"^[aeiouAEIOU][A-Za-z0-9_]*\", 9);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Invalid\";\n if ( !v1 )\n return \"Valid\";\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1280(char *string) {\n int v1;\n const char *result;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \"^[aeiouAEIOU][A-Za-z0-9_]*\", 9);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Invalid\";\n if (!v1) return \"Valid\";\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n const char *result;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \"^[aeiouAEIOU][A-Za-z0-9_]*\", 9);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Invalid\";\n if (!v1) return \"Valid\";\n return result;\n}" + }, + { + "index": 737, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* string) {\n regex_t regex;\n int result;\n char* pattern = \"^[aeiouAEIOU][A-Za-z0-9_]*\";\n regcomp(®ex, pattern, REG_EXTENDED | REG_NOSUB);\n result = regexec(®ex, string, 0, NULL, 0);\n regfree(®ex);\n if (result == 0) {\n return \"Valid\";\n } else {\n return \"Invalid\";\n }\n}", + "test": "int main() {\n\n assert(func0(\"annie\") == \"Valid\");\n\n assert(func0(\"dawood\") == \"Invalid\");\n\n assert(func0(\"Else\") == \"Valid\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov $0x9,%edx\nmov %rdi,%r12\nlea 0xd7d(%rip),%rsi\npush %rbp\npush %rbx\nsub $0x50,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%rbp\nmov %rbp,%rdi\ncallq 10c0 \nxor %ecx,%ecx\nxor %edx,%edx\nxor %r8d,%r8d\nmov %r12,%rsi\nmov %rbp,%rdi\ncallq 10d0 \nmov %rbp,%rdi\nmov %eax,%ebx\ncallq 1090 \ntest %ebx,%ebx\nlea 0xd29(%rip),%rax\nlea 0xd28(%rip),%rdx\ncmovne %rdx,%rax\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 12ff \nadd $0x50,%rsp\npop %rbx\npop %rbp\npop %r12\nretq\ncallq 10a0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov edx, 9; cflags\nlea rsi, pattern; \"^[aeiouAEIOU][A-Za-z0-9_]*\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, aInvalid; \"Invalid\"\nlea rdx, aValid; \"Valid\"\ncmovz rax, rdx\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_12FB\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_12FB:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // ebx\n const char *result; // rax\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \"^[aeiouAEIOU][A-Za-z0-9_]*\", 9);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Invalid\";\n if ( !v1 )\n return \"Valid\";\n return result;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\npush rbp\nmov edx, 9; cflags\nlea rsi, pattern; \"^[aeiouAEIOU][A-Za-z0-9_]*\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, aInvalid; \"Invalid\"\nlea rdx, aValid; \"Valid\"\ncmovz rax, rdx\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_12FB\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_12FB:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_1280(char *string)\n{\n int v1; // ebx\n const char *result; // rax\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \"^[aeiouAEIOU][A-Za-z0-9_]*\", 9);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Invalid\";\n if ( !v1 )\n return \"Valid\";\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1280(char *string) {\n int v1;\n const char *result;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \"^[aeiouAEIOU][A-Za-z0-9_]*\", 9);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Invalid\";\n if (!v1) return \"Valid\";\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n const char *result;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \"^[aeiouAEIOU][A-Za-z0-9_]*\", 9);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Invalid\";\n if (!v1) return \"Valid\";\n return result;\n}" + }, + { + "index": 738, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int n) {\n if (n < 0) {\n return 0;\n } else {\n return 1 / pow(2, n) + func0(n - 1);\n }\n}", + "test": "int main() {\n\n assert(func0(7) == 1.9921875);\n\n assert(func0(4) == 1.9375);\n\n assert(func0(8) == 1.99609375);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %edi,-0x4(%rbp)\ncmpl $0x0,-0x4(%rbp)\njns 1184 \npxor %xmm0,%xmm0\njmp 11c1 \ncvtsi2sdl -0x4(%rbp),%xmm0\nmov 0xf00(%rip),%rax\nmovapd %xmm0,%xmm1\nmovq %rax,%xmm0\ncallq 1060 \nmovsd 0xef2(%rip),%xmm1\ndivsd %xmm0,%xmm1\nmovsd %xmm1,-0x10(%rbp)\nmov -0x4(%rbp),%eax\nsub $0x1,%eax\nmov %eax,%edi\ncallq 1169 \naddsd -0x10(%rbp),%xmm0\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+var_4], edi\ncmp [rbp+var_4], 0\njns short loc_1184\npxor xmm0, xmm0\njmp short locret_11C5\nloc_1184:\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_4]\nmov rax, cs:x\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\nmovsd xmm1, cs:qword_2078\ndivsd xmm1, xmm0\nmovsd [rbp+var_10], xmm1\nmov eax, [rbp+var_4]\nsub eax, 1\nmov edi, eax\ncall func0\naddsd xmm0, [rbp+var_10]\nlocret_11C5:\nleave\nretn", + "ida_pseudo": "double __fastcall func0(int a1)\n{\n double v2; // [rsp+0h] [rbp-10h]\n\n if ( a1 < 0 )\n return 0.0;\n v2 = 1.0 / pow(2.0, (double)a1);\n return func0((unsigned int)(a1 - 1)) + v2;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+var_4], edi\ncmp [rbp+var_4], 0\njns short loc_1184\npxor xmm0, xmm0\njmp short locret_11C5\nloc_1184:\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_4]\nmov rax, cs:x\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\nmovsd xmm1, cs:qword_2078\ndivsd xmm1, xmm0\nmovsd [rbp+var_10], xmm1\nmov eax, [rbp+var_4]\nsub eax, 1\nmov edi, eax\ncall sub_1169\naddsd xmm0, [rbp+var_10]\nlocret_11C5:\nleave\nretn", + "ida_strip_pseudo": "double __fastcall sub_1169(int a1)\n{\n double v2; // [rsp+0h] [rbp-10h]\n\n if ( a1 < 0 )\n return 0.0;\n v2 = 1.0 / pow(2.0, (double)a1);\n return sub_1169((unsigned int)(a1 - 1)) + v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1169(int a1) {\n double v2;\n if (a1 < 0) return 0.0;\n v2 = 1.0 / pow(2.0, (double)a1);\n return sub_1169((unsigned int)(a1 - 1)) + v2;\n}", + "ida_pseudo_norm": "double func0(int a1) {\n double v2;\n if (a1 < 0) return 0.0;\n v2 = 1.0 / pow(2.0, (double)a1);\n return func0((unsigned int)(a1 - 1)) + v2;\n}" + }, + { + "index": 738, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int n) {\n if (n < 0) {\n return 0;\n } else {\n return 1 / pow(2, n) + func0(n - 1);\n }\n}", + "test": "int main() {\n\n assert(func0(7) == 1.9921875);\n\n assert(func0(4) == 1.9375);\n\n assert(func0(8) == 1.99609375);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npxor %xmm0,%xmm0\ntest %edi,%edi\njns 1176 \nretq\npush %rbx\nsub $0x10,%rsp\nmov %edi,%ebx\npxor %xmm1,%xmm1\ncvtsi2sd %edi,%xmm1\nmovsd 0xf03(%rip),%xmm0\ncallq 1060 \nmovsd %xmm0,0x8(%rsp)\nlea -0x1(%rbx),%edi\ncallq 1169 \nmovapd %xmm0,%xmm1\nmovsd 0xeec(%rip),%xmm0\ndivsd 0x8(%rsp),%xmm0\naddsd %xmm1,%xmm0\nadd $0x10,%rsp\npop %rbx\nretq\n", + "ida_asm": "func0:\nendbr64\npxor xmm0, xmm0\ntest edi, edi\njns short loc_1176\nretn\nloc_1176:\npush rbx\nsub rsp, 10h\nmov ebx, edi\npxor xmm1, xmm1\ncvtsi2sd xmm1, edi; y\nmovsd xmm0, cs:x; x\ncall _pow\nmovsd xmm1, cs:qword_2078\ndivsd xmm1, xmm0\nmovsd [rsp+18h+var_10], xmm1\nlea edi, [rbx-1]\ncall func0\naddsd xmm0, [rsp+18h+var_10]\nadd rsp, 10h\npop rbx\nretn", + "ida_pseudo": "double __fastcall func0(int a1)\n{\n double result; // xmm0_8\n double v2; // [rsp+0h] [rbp-10h]\n\n result = 0.0;\n if ( a1 >= 0 )\n {\n v2 = 1.0 / pow(2.0, (double)a1);\n return func0((unsigned int)(a1 - 1)) + v2;\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npxor xmm0, xmm0\ntest edi, edi\njns short loc_1176\nretn\nloc_1176:\npush rbx\nsub rsp, 10h\nmov ebx, edi\npxor xmm1, xmm1\ncvtsi2sd xmm1, edi; y\nmovsd xmm0, cs:x; x\ncall _pow\nmovsd xmm1, cs:qword_2078\ndivsd xmm1, xmm0\nmovsd [rsp+18h+var_10], xmm1\nlea edi, [rbx-1]\ncall sub_1169\naddsd xmm0, [rsp+18h+var_10]\nadd rsp, 10h\npop rbx\nretn", + "ida_strip_pseudo": "double __fastcall sub_1169(int a1)\n{\n double result; // xmm0_8\n double v2; // [rsp+0h] [rbp-10h]\n\n result = 0.0;\n if ( a1 >= 0 )\n {\n v2 = 1.0 / pow(2.0, (double)a1);\n return sub_1169((unsigned int)(a1 - 1)) + v2;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1169(int a1) {\n double result;\n double v2;\n result = 0.0;\n if (a1 >= 0) {\n v2 = 1.0 / pow(2.0, (double)a1);\n return sub_1169((unsigned int)(a1 - 1)) + v2;\n }\n return result;\n}", + "ida_pseudo_norm": "double func0(int a1) {\n double result;\n double v2;\n result = 0.0;\n if (a1 >= 0) {\n v2 = 1.0 / pow(2.0, (double)a1);\n return func0((unsigned int)(a1 - 1)) + v2;\n }\n return result;\n}" + }, + { + "index": 738, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int n) {\n if (n < 0) {\n return 0;\n } else {\n return 1 / pow(2, n) + func0(n - 1);\n }\n}", + "test": "int main() {\n\n assert(func0(7) == 1.9921875);\n\n assert(func0(4) == 1.9375);\n\n assert(func0(8) == 1.99609375);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\njns 1230 \npxor %xmm0,%xmm0\nretq\nnopl (%rax)\njmp 1240 \ndata16 nopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0_part_0:\npush rbx\npxor xmm1, xmm1\nmov ebx, edi\ncvtsi2sd xmm1, edi; y\nsub rsp, 20h\nmovsd xmm0, cs:x; x\ncall _pow\nmovsd xmm2, cs:qword_2078\ndivsd xmm2, xmm0\npxor xmm0, xmm0\ntest ebx, ebx\njnz short loc_1260\nadd rsp, 20h\naddsd xmm0, xmm2\npop rbx\nretn\nloc_1260:\nlea eax, [rbx-1]\npxor xmm1, xmm1\nmovsd xmm0, cs:x; x\nmovsd [rsp+28h+var_20], xmm2\ncvtsi2sd xmm1, eax; y\ncall _pow\nmovsd xmm3, cs:qword_2078\ncmp ebx, 1\nlea eax, [rbx-2]\nmovsd xmm2, [rsp+28h+var_20]\ndivsd xmm3, xmm0\npxor xmm0, xmm0\njnz short loc_12B0\nloc_129C:\naddsd xmm0, xmm3\nadd rsp, 20h\npop rbx\naddsd xmm0, xmm2\nretn\nloc_12B0:\npxor xmm1, xmm1\nmovsd xmm0, cs:x; x\nmovsd [rsp+28h+var_18], xmm3\ncvtsi2sd xmm1, eax; y\ncall _pow\nmovsd xmm1, cs:qword_2078\ncmp ebx, 2\nmovsd xmm2, [rsp+28h+var_20]\nmovsd xmm3, [rsp+28h+var_18]\nlea edi, [rbx-3]\ndivsd xmm1, xmm0\npxor xmm0, xmm0\njz short loc_130C\nmovsd [rsp+28h+var_10], xmm1\ncall func0_part_0\nmovsd xmm1, [rsp+28h+var_10]\nmovsd xmm3, [rsp+28h+var_18]\nmovsd xmm2, [rsp+28h+var_20]\nloc_130C:\naddsd xmm0, xmm1\njmp short loc_129C", + "ida_pseudo": "double __fastcall func0_part_0(int a1)\n{\n double v1; // xmm2_8\n double v3; // xmm3_8\n double v4; // xmm0_8\n double v5; // xmm1_8\n\n v1 = 1.0 / pow(2.0, (double)a1);\n if ( !a1 )\n return v1 + 0.0;\n v3 = 1.0 / pow(2.0, (double)(a1 - 1));\n v4 = 0.0;\n if ( a1 != 1 )\n {\n v5 = 1.0 / pow(2.0, (double)(a1 - 2));\n if ( a1 != 2 )\n func0_part_0((unsigned int)(a1 - 3), 0.0, v5, v1, v3);\n v4 = v5 + 0.0;\n }\n return v4 + v3 + v1;\n}", + "ida_strip_asm": "sub_1220:\npush rbx\npxor xmm1, xmm1\nmov ebx, edi\ncvtsi2sd xmm1, edi; y\nsub rsp, 20h\nmovsd xmm0, cs:x; x\ncall _pow\nmovsd xmm2, cs:qword_2078\ndivsd xmm2, xmm0\npxor xmm0, xmm0\ntest ebx, ebx\njnz short loc_1260\nadd rsp, 20h\naddsd xmm0, xmm2\npop rbx\nretn\nloc_1260:\nlea eax, [rbx-1]\npxor xmm1, xmm1\nmovsd xmm0, cs:x; x\nmovsd [rsp+28h+var_20], xmm2\ncvtsi2sd xmm1, eax; y\ncall _pow\nmovsd xmm3, cs:qword_2078\ncmp ebx, 1\nlea eax, [rbx-2]\nmovsd xmm2, [rsp+28h+var_20]\ndivsd xmm3, xmm0\npxor xmm0, xmm0\njnz short loc_12B0\nloc_129C:\naddsd xmm0, xmm3\nadd rsp, 20h\npop rbx\naddsd xmm0, xmm2\nretn\nloc_12B0:\npxor xmm1, xmm1\nmovsd xmm0, cs:x; x\nmovsd [rsp+28h+var_18], xmm3\ncvtsi2sd xmm1, eax; y\ncall _pow\nmovsd xmm1, cs:qword_2078\ncmp ebx, 2\nmovsd xmm2, [rsp+28h+var_20]\nmovsd xmm3, [rsp+28h+var_18]\nlea edi, [rbx-3]\ndivsd xmm1, xmm0\npxor xmm0, xmm0\njz short loc_130C\nmovsd [rsp+28h+var_10], xmm1\ncall sub_1220\nmovsd xmm1, [rsp+28h+var_10]\nmovsd xmm3, [rsp+28h+var_18]\nmovsd xmm2, [rsp+28h+var_20]\nloc_130C:\naddsd xmm0, xmm1\njmp short loc_129C", + "ida_strip_pseudo": "double __fastcall sub_1220(int a1)\n{\n double v1; // xmm2_8\n double v3; // xmm3_8\n double v4; // xmm0_8\n double v5; // xmm1_8\n\n v1 = 1.0 / pow(2.0, (double)a1);\n if ( !a1 )\n return v1 + 0.0;\n v3 = 1.0 / pow(2.0, (double)(a1 - 1));\n v4 = 0.0;\n if ( a1 != 1 )\n {\n v5 = 1.0 / pow(2.0, (double)(a1 - 2));\n if ( a1 != 2 )\n sub_1220((unsigned int)(a1 - 3), 0.0, v5, v1, v3);\n v4 = v5 + 0.0;\n }\n return v4 + v3 + v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1220(int a1) {\n double v1;\n double v3;\n double v4;\n double v5;\n v1 = 1.0 / pow(2.0, (double)a1);\n if (!a1) return v1 + 0.0;\n v3 = 1.0 / pow(2.0, (double)(a1 - 1));\n v4 = 0.0;\n if (a1 != 1) {\n v5 = 1.0 / pow(2.0, (double)(a1 - 2));\n if (a1 != 2) sub_1220((unsigned int)(a1 - 3), 0.0, v5, v1, v3);\n v4 = v5 + 0.0;\n }\n return v4 + v3 + v1;\n}", + "ida_pseudo_norm": "double func0_part_0(int a1) {\n double v1;\n double v3;\n double v4;\n double v5;\n v1 = 1.0 / pow(2.0, (double)a1);\n if (!a1) return v1 + 0.0;\n v3 = 1.0 / pow(2.0, (double)(a1 - 1));\n v4 = 0.0;\n if (a1 != 1) {\n v5 = 1.0 / pow(2.0, (double)(a1 - 2));\n if (a1 != 2) func0_part_0((unsigned int)(a1 - 3), 0.0, v5, v1, v3);\n v4 = v5 + 0.0;\n }\n return v4 + v3 + v1;\n}" + }, + { + "index": 738, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int n) {\n if (n < 0) {\n return 0;\n } else {\n return 1 / pow(2, n) + func0(n - 1);\n }\n}", + "test": "int main() {\n\n assert(func0(7) == 1.9921875);\n\n assert(func0(4) == 1.9375);\n\n assert(func0(8) == 1.99609375);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npxor %xmm2,%xmm2\ntest %edi,%edi\njns 1288 \nmovapd %xmm2,%xmm0\nretq\nnopl 0x0(%rax)\npush %rbx\npxor %xmm1,%xmm1\nmov %edi,%ebx\ncvtsi2sd %edi,%xmm1\nsub $0x40,%rsp\nmov 0xdf2(%rip),%rax\nmovsd %xmm2,0x8(%rsp)\nmovq %rax,%xmm0\ncallq 1060 \nmovsd 0xde2(%rip),%xmm4\nmovsd 0x8(%rsp),%xmm2\nlea -0x1(%rbx),%eax\ndivsd %xmm0,%xmm4\nmovapd %xmm2,%xmm0\ntest %ebx,%ebx\njne 12e0 \naddsd %xmm0,%xmm4\nadd $0x40,%rsp\npop %rbx\nmovapd %xmm4,%xmm0\nretq\nnopl 0x0(%rax)\npxor %xmm1,%xmm1\nmovsd %xmm4,0x10(%rsp)\ncvtsi2sd %eax,%xmm1\nmov 0xd9b(%rip),%rax\nmovq %rax,%xmm0\ncallq 1060 \nmovsd 0xd91(%rip),%xmm3\ncmp $0x1,%ebx\nmovsd 0x8(%rsp),%xmm2\nmovsd 0x10(%rsp),%xmm4\nlea -0x2(%rbx),%eax\ndivsd %xmm0,%xmm3\nmovapd %xmm2,%xmm0\njne 1338 \naddsd %xmm3,%xmm0\nadd $0x40,%rsp\npop %rbx\naddsd %xmm0,%xmm4\nmovapd %xmm4,%xmm0\nretq\nnopl (%rax)\npxor %xmm1,%xmm1\nmovsd %xmm3,0x18(%rsp)\ncvtsi2sd %eax,%xmm1\nmov 0xd43(%rip),%rax\nmovq %rax,%xmm0\ncallq 1060 \nmovsd 0xd39(%rip),%xmm5\ncmp $0x2,%ebx\nmovsd 0x8(%rsp),%xmm2\nmovsd 0x10(%rsp),%xmm4\nmovsd 0x18(%rsp),%xmm3\nlea -0x3(%rbx),%eax\ndivsd %xmm0,%xmm5\nmovapd %xmm2,%xmm0\njne 1390 \naddsd %xmm5,%xmm0\njmp 1323 \nnopw 0x0(%rax,%rax,1)\npxor %xmm1,%xmm1\nmovsd %xmm5,0x20(%rsp)\ncvtsi2sd %eax,%xmm1\nmov 0xceb(%rip),%rax\nmovq %rax,%xmm0\ncallq 1060 \nmovsd 0xce1(%rip),%xmm6\ncmp $0x3,%ebx\nmovsd 0x8(%rsp),%xmm2\nmovsd 0x10(%rsp),%xmm4\nmovsd 0x18(%rsp),%xmm3\nlea -0x4(%rbx),%eax\ndivsd %xmm0,%xmm6\nmovsd 0x20(%rsp),%xmm5\nmovapd %xmm2,%xmm0\njne 13e8 \naddsd %xmm6,%xmm0\njmp 1381 \nnopl (%rax)\npxor %xmm1,%xmm1\nmovsd %xmm6,0x28(%rsp)\ncvtsi2sd %eax,%xmm1\nmov 0xc93(%rip),%rax\nmovq %rax,%xmm0\ncallq 1060 \nmovsd 0xc89(%rip),%xmm7\ncmp $0x4,%ebx\nmovsd 0x8(%rsp),%xmm2\nmovsd 0x10(%rsp),%xmm4\nmovsd 0x18(%rsp),%xmm3\nlea -0x5(%rbx),%eax\ndivsd %xmm0,%xmm7\nmovsd 0x20(%rsp),%xmm5\nmovsd 0x28(%rsp),%xmm6\nmovapd %xmm2,%xmm0\njne 1443 \naddsd %xmm7,%xmm0\njmp 13df \npxor %xmm1,%xmm1\nmovsd %xmm7,0x30(%rsp)\ncvtsi2sd %eax,%xmm1\nmov 0xc38(%rip),%rax\nmovq %rax,%xmm0\ncallq 1060 \nmovsd 0x8(%rsp),%xmm2\ncmp $0x5,%ebx\nmovsd 0xc24(%rip),%xmm8\nmovsd 0x10(%rsp),%xmm4\nmovsd 0x18(%rsp),%xmm3\nlea -0x6(%rbx),%eax\ndivsd %xmm0,%xmm8\nmovsd 0x20(%rsp),%xmm5\nmovsd 0x28(%rsp),%xmm6\nmovapd %xmm2,%xmm0\nmovsd 0x30(%rsp),%xmm7\njne 14a7 \naddsd %xmm8,%xmm0\njmp 143d \npxor %xmm1,%xmm1\nmovsd %xmm8,0x38(%rsp)\ncvtsi2sd %eax,%xmm1\nmov 0xbd3(%rip),%rax\nmovq %rax,%xmm0\ncallq 1060 \nmovsd 0xbc9(%rip),%xmm1\ncmp $0x6,%ebx\nmovsd 0x8(%rsp),%xmm2\nmovsd 0x10(%rsp),%xmm4\nmovsd 0x18(%rsp),%xmm3\nlea -0x7(%rbx),%edi\ndivsd %xmm0,%xmm1\nmovsd 0x20(%rsp),%xmm5\nmovsd 0x28(%rsp),%xmm6\nmovapd %xmm2,%xmm0\nmovsd 0x30(%rsp),%xmm7\nmovsd 0x38(%rsp),%xmm8\nje 1565 \nmovsd %xmm1,0x38(%rsp)\nmovsd %xmm8,0x30(%rsp)\nmovsd %xmm7,0x28(%rsp)\nmovsd %xmm6,0x20(%rsp)\nmovsd %xmm5,0x18(%rsp)\nmovsd %xmm3,0x10(%rsp)\nmovsd %xmm4,0x8(%rsp)\ncallq 1220 \nmovsd 0x38(%rsp),%xmm1\nmovsd 0x30(%rsp),%xmm8\nmovsd 0x28(%rsp),%xmm7\nmovsd 0x20(%rsp),%xmm6\nmovsd 0x18(%rsp),%xmm5\nmovsd 0x10(%rsp),%xmm3\nmovsd 0x8(%rsp),%xmm4\naddsd %xmm1,%xmm0\njmpq 14a0 \nxchg %ax,%ax\n", + "ida_asm": "func0_part_0:\npush rbx\npxor xmm1, xmm1\nmov ebx, edi\ncvtsi2sd xmm1, edi; y\nsub rsp, 20h\nmovsd xmm0, cs:x; x\ncall _pow\nmovsd xmm2, cs:qword_2078\ndivsd xmm2, xmm0\npxor xmm0, xmm0\ntest ebx, ebx\njnz short loc_1260\nadd rsp, 20h\naddsd xmm0, xmm2\npop rbx\nretn\nloc_1260:\nlea eax, [rbx-1]\npxor xmm1, xmm1\nmovsd xmm0, cs:x; x\nmovsd [rsp+28h+var_20], xmm2\ncvtsi2sd xmm1, eax; y\ncall _pow\nmovsd xmm3, cs:qword_2078\ncmp ebx, 1\nlea eax, [rbx-2]\nmovsd xmm2, [rsp+28h+var_20]\ndivsd xmm3, xmm0\npxor xmm0, xmm0\njnz short loc_12B0\nloc_129C:\naddsd xmm0, xmm3\nadd rsp, 20h\npop rbx\naddsd xmm0, xmm2\nretn\nloc_12B0:\npxor xmm1, xmm1\nmovsd xmm0, cs:x; x\nmovsd [rsp+28h+var_18], xmm3\ncvtsi2sd xmm1, eax; y\ncall _pow\nmovsd xmm1, cs:qword_2078\ncmp ebx, 2\nmovsd xmm2, [rsp+28h+var_20]\nmovsd xmm3, [rsp+28h+var_18]\nlea edi, [rbx-3]\ndivsd xmm1, xmm0\npxor xmm0, xmm0\njz short loc_130C\nmovsd [rsp+28h+var_10], xmm1\ncall func0_part_0\nmovsd xmm1, [rsp+28h+var_10]\nmovsd xmm3, [rsp+28h+var_18]\nmovsd xmm2, [rsp+28h+var_20]\nloc_130C:\naddsd xmm0, xmm1\njmp short loc_129C", + "ida_pseudo": "double __fastcall func0_part_0(int a1)\n{\n double v1; // xmm2_8\n double v3; // xmm3_8\n double v4; // xmm0_8\n double v5; // xmm1_8\n\n v1 = 1.0 / pow(2.0, (double)a1);\n if ( !a1 )\n return v1 + 0.0;\n v3 = 1.0 / pow(2.0, (double)(a1 - 1));\n v4 = 0.0;\n if ( a1 != 1 )\n {\n v5 = 1.0 / pow(2.0, (double)(a1 - 2));\n if ( a1 != 2 )\n func0_part_0((unsigned int)(a1 - 3), 0.0, v5, v1, v3);\n v4 = v5 + 0.0;\n }\n return v4 + v3 + v1;\n}", + "ida_strip_asm": "sub_1220:\npush rbx\npxor xmm1, xmm1\nmov ebx, edi\ncvtsi2sd xmm1, edi; y\nsub rsp, 20h\nmovsd xmm0, cs:x; x\ncall _pow\nmovsd xmm2, cs:qword_2078\ndivsd xmm2, xmm0\npxor xmm0, xmm0\ntest ebx, ebx\njnz short loc_1260\nadd rsp, 20h\naddsd xmm0, xmm2\npop rbx\nretn\nloc_1260:\nlea eax, [rbx-1]\npxor xmm1, xmm1\nmovsd xmm0, cs:x; x\nmovsd [rsp+28h+var_20], xmm2\ncvtsi2sd xmm1, eax; y\ncall _pow\nmovsd xmm3, cs:qword_2078\ncmp ebx, 1\nlea eax, [rbx-2]\nmovsd xmm2, [rsp+28h+var_20]\ndivsd xmm3, xmm0\npxor xmm0, xmm0\njnz short loc_12B0\nloc_129C:\naddsd xmm0, xmm3\nadd rsp, 20h\npop rbx\naddsd xmm0, xmm2\nretn\nloc_12B0:\npxor xmm1, xmm1\nmovsd xmm0, cs:x; x\nmovsd [rsp+28h+var_18], xmm3\ncvtsi2sd xmm1, eax; y\ncall _pow\nmovsd xmm1, cs:qword_2078\ncmp ebx, 2\nmovsd xmm2, [rsp+28h+var_20]\nmovsd xmm3, [rsp+28h+var_18]\nlea edi, [rbx-3]\ndivsd xmm1, xmm0\npxor xmm0, xmm0\njz short loc_130C\nmovsd [rsp+28h+var_10], xmm1\ncall sub_1220\nmovsd xmm1, [rsp+28h+var_10]\nmovsd xmm3, [rsp+28h+var_18]\nmovsd xmm2, [rsp+28h+var_20]\nloc_130C:\naddsd xmm0, xmm1\njmp short loc_129C", + "ida_strip_pseudo": "double __fastcall sub_1220(int a1)\n{\n double v1; // xmm2_8\n double v3; // xmm3_8\n double v4; // xmm0_8\n double v5; // xmm1_8\n\n v1 = 1.0 / pow(2.0, (double)a1);\n if ( !a1 )\n return v1 + 0.0;\n v3 = 1.0 / pow(2.0, (double)(a1 - 1));\n v4 = 0.0;\n if ( a1 != 1 )\n {\n v5 = 1.0 / pow(2.0, (double)(a1 - 2));\n if ( a1 != 2 )\n sub_1220((unsigned int)(a1 - 3), 0.0, v5, v1, v3);\n v4 = v5 + 0.0;\n }\n return v4 + v3 + v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1220(int a1) {\n double v1;\n double v3;\n double v4;\n double v5;\n v1 = 1.0 / pow(2.0, (double)a1);\n if (!a1) return v1 + 0.0;\n v3 = 1.0 / pow(2.0, (double)(a1 - 1));\n v4 = 0.0;\n if (a1 != 1) {\n v5 = 1.0 / pow(2.0, (double)(a1 - 2));\n if (a1 != 2) sub_1220((unsigned int)(a1 - 3), 0.0, v5, v1, v3);\n v4 = v5 + 0.0;\n }\n return v4 + v3 + v1;\n}", + "ida_pseudo_norm": "double func0_part_0(int a1) {\n double v1;\n double v3;\n double v4;\n double v5;\n v1 = 1.0 / pow(2.0, (double)a1);\n if (!a1) return v1 + 0.0;\n v3 = 1.0 / pow(2.0, (double)(a1 - 1));\n v4 = 0.0;\n if (a1 != 1) {\n v5 = 1.0 / pow(2.0, (double)(a1 - 2));\n if (a1 != 2) func0_part_0((unsigned int)(a1 - 3), 0.0, v5, v1, v3);\n v4 = v5 + 0.0;\n }\n return v4 + v3 + v1;\n}" + }, + { + "index": 739, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n double x = sqrt(2 * pow(10, (n - 1)));\n return (int)round(x);\n}", + "test": "int main() {\n\n assert(func0(2) == 4);\n\n assert(func0(3) == 14);\n\n assert(func0(4) == 45);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %edi,-0x14(%rbp)\nmov -0x14(%rbp),%eax\nsub $0x1,%eax\ncvtsi2sd %eax,%xmm0\nmov 0xeaf(%rip),%rax\nmovapd %xmm0,%xmm1\nmovq %rax,%xmm0\ncallq 1090 \naddsd %xmm0,%xmm0\ncallq 10b0 \nmovq %xmm0,%rax\nmov %rax,-0x8(%rbp)\nmov -0x8(%rbp),%rax\nmovq %rax,%xmm0\ncallq 1080 \ncvttsd2si %xmm0,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov eax, [rbp+var_14]\nsub eax, 1\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmov rax, cs:x\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\naddsd xmm0, xmm0\nmovq rax, xmm0\nmovq xmm0, rax; x\ncall _sqrt\nmovq rax, xmm0\nmov [rbp+x], rax\nmov rax, [rbp+x]\nmovq xmm0, rax; x\ncall _round\ncvttsd2si eax, xmm0\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n double v1; // xmm0_8\n double v2; // xmm0_8\n\n v1 = pow(10.0, (double)(a1 - 1));\n v2 = sqrt(v1 + v1);\n return (unsigned int)(int)round(v2);\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov eax, [rbp+var_14]\nsub eax, 1\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmov rax, cs:x\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\naddsd xmm0, xmm0\nmovq rax, xmm0\nmovq xmm0, rax; x\ncall _sqrt\nmovq rax, xmm0\nmov [rbp+x], rax\nmov rax, [rbp+x]\nmovq xmm0, rax; x\ncall _round\ncvttsd2si eax, xmm0\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(int a1)\n{\n double v1; // xmm0_8\n double v2; // xmm0_8\n\n v1 = pow(10.0, (double)(a1 - 1));\n v2 = sqrt(v1 + v1);\n return (unsigned int)(int)round(v2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(int a1) {\n double v1;\n double v2;\n v1 = pow(10.0, (double)(a1 - 1));\n v2 = sqrt(v1 + v1);\n return (unsigned int)(int)round(v2);\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n double v1;\n double v2;\n v1 = pow(10.0, (double)(a1 - 1));\n v2 = sqrt(v1 + v1);\n return (unsigned int)(int)round(v2);\n}" + }, + { + "index": 739, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n double x = sqrt(2 * pow(10, (n - 1)));\n return (int)round(x);\n}", + "test": "int main() {\n\n assert(func0(2) == 4);\n\n assert(func0(3) == 14);\n\n assert(func0(4) == 45);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x18,%rsp\nsub $0x1,%edi\npxor %xmm1,%xmm1\ncvtsi2sd %edi,%xmm1\nmovsd 0xeb4(%rip),%xmm0\ncallq 1090 \naddsd %xmm0,%xmm0\nmovapd %xmm0,%xmm2\nsqrtsd %xmm2,%xmm2\nmovsd %xmm2,0x8(%rsp)\npxor %xmm1,%xmm1\nucomisd %xmm0,%xmm1\nja 11f9 \nmovsd 0x8(%rsp),%xmm0\ncallq 1080 \ncvttsd2si %xmm0,%eax\nadd $0x18,%rsp\nretq\ncallq 10b0 \njmp 11e5 \n", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\nsub edi, 1\npxor xmm1, xmm1\ncvtsi2sd xmm1, edi; y\nmovsd xmm0, cs:x; x\ncall _pow\naddsd xmm0, xmm0\nsqrtsd xmm0, xmm0; x\ncall _round\ncvttsd2si eax, xmm0\nadd rsp, 8\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n double v1; // xmm0_8\n\n v1 = pow(10.0, (double)(a1 - 1));\n return (unsigned int)(int)round(sqrt(v1 + v1));\n}", + "ida_strip_asm": "sub_1189:\nendbr64\nsub rsp, 8\nsub edi, 1\npxor xmm1, xmm1\ncvtsi2sd xmm1, edi; y\nmovsd xmm0, cs:x; x\ncall _pow\naddsd xmm0, xmm0\nsqrtsd xmm0, xmm0; x\ncall _round\ncvttsd2si eax, xmm0\nadd rsp, 8\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(int a1)\n{\n double v1; // xmm0_8\n\n v1 = pow(10.0, (double)(a1 - 1));\n return (unsigned int)(int)round(sqrt(v1 + v1));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(int a1) {\n double v1;\n v1 = pow(10.0, (double)(a1 - 1));\n return (unsigned int)(int)round(sqrt(v1 + v1));\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n double v1;\n v1 = pow(10.0, (double)(a1 - 1));\n return (unsigned int)(int)round(sqrt(v1 + v1));\n}" + }, + { + "index": 739, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n double x = sqrt(2 * pow(10, (n - 1)));\n return (int)round(x);\n}", + "test": "int main() {\n\n assert(func0(2) == 4);\n\n assert(func0(3) == 14);\n\n assert(func0(4) == 45);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x1,%edi\npxor %xmm1,%xmm1\nsub $0x18,%rsp\nmovsd 0xe11(%rip),%xmm0\ncvtsi2sd %edi,%xmm1\ncallq 1090 \npxor %xmm2,%xmm2\naddsd %xmm0,%xmm0\nucomisd %xmm0,%xmm2\nmovapd %xmm0,%xmm1\nsqrtsd %xmm1,%xmm1\nja 1298 \nmovapd %xmm1,%xmm0\ncallq 1080 \nadd $0x18,%rsp\ncvttsd2si %xmm0,%eax\nretq\nmovsd %xmm1,0x8(%rsp)\ncallq 10b0 \nmovsd 0x8(%rsp),%xmm1\njmp 1286 \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nsub edi, 1\npxor xmm1, xmm1\nsub rsp, 8\nmovsd xmm0, cs:x; x\ncvtsi2sd xmm1, edi; y\ncall _pow\naddsd xmm0, xmm0\nsqrtsd xmm0, xmm0; x\ncall _round\nadd rsp, 8\ncvttsd2si eax, xmm0\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n double v1; // xmm0_8\n\n v1 = pow(10.0, (double)(a1 - 1));\n return (unsigned int)(int)round(sqrt(v1 + v1));\n}", + "ida_strip_asm": "sub_1230:\nendbr64\nsub edi, 1\npxor xmm1, xmm1\nsub rsp, 8\nmovsd xmm0, cs:x; x\ncvtsi2sd xmm1, edi; y\ncall _pow\naddsd xmm0, xmm0\nsqrtsd xmm0, xmm0; x\ncall _round\nadd rsp, 8\ncvttsd2si eax, xmm0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1230(int a1)\n{\n double v1; // xmm0_8\n\n v1 = pow(10.0, (double)(a1 - 1));\n return (unsigned int)(int)round(sqrt(v1 + v1));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1230(int a1) {\n double v1;\n v1 = pow(10.0, (double)(a1 - 1));\n return (unsigned int)(int)round(sqrt(v1 + v1));\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n double v1;\n v1 = pow(10.0, (double)(a1 - 1));\n return (unsigned int)(int)round(sqrt(v1 + v1));\n}" + }, + { + "index": 739, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n double x = sqrt(2 * pow(10, (n - 1)));\n return (int)round(x);\n}", + "test": "int main() {\n\n assert(func0(2) == 4);\n\n assert(func0(3) == 14);\n\n assert(func0(4) == 45);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x1,%edi\npxor %xmm1,%xmm1\nsub $0x18,%rsp\nmovsd 0xe11(%rip),%xmm0\ncvtsi2sd %edi,%xmm1\ncallq 1090 \npxor %xmm2,%xmm2\naddsd %xmm0,%xmm0\nucomisd %xmm0,%xmm2\nmovapd %xmm0,%xmm1\nsqrtsd %xmm1,%xmm1\nja 1298 \nmovapd %xmm1,%xmm0\ncallq 1080 \nadd $0x18,%rsp\ncvttsd2si %xmm0,%eax\nretq\nmovsd %xmm1,0x8(%rsp)\ncallq 10b0 \nmovsd 0x8(%rsp),%xmm1\njmp 1286 \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nsub edi, 1\npxor xmm1, xmm1\nsub rsp, 8\nmovsd xmm0, cs:x; x\ncvtsi2sd xmm1, edi; y\ncall _pow\naddsd xmm0, xmm0\nsqrtsd xmm0, xmm0; x\ncall _round\nadd rsp, 8\ncvttsd2si eax, xmm0\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n double v1; // xmm0_8\n\n v1 = pow(10.0, (double)(a1 - 1));\n return (unsigned int)(int)round(sqrt(v1 + v1));\n}", + "ida_strip_asm": "sub_1230:\nendbr64\nsub edi, 1\npxor xmm1, xmm1\nsub rsp, 8\nmovsd xmm0, cs:x; x\ncvtsi2sd xmm1, edi; y\ncall _pow\naddsd xmm0, xmm0\nsqrtsd xmm0, xmm0; x\ncall _round\nadd rsp, 8\ncvttsd2si eax, xmm0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1230(int a1)\n{\n double v1; // xmm0_8\n\n v1 = pow(10.0, (double)(a1 - 1));\n return (unsigned int)(int)round(sqrt(v1 + v1));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1230(int a1) {\n double v1;\n v1 = pow(10.0, (double)(a1 - 1));\n return (unsigned int)(int)round(sqrt(v1 + v1));\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n double v1;\n v1 = pow(10.0, (double)(a1 - 1));\n return (unsigned int)(int)round(sqrt(v1 + v1));\n}" + }, + { + "index": 740, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int key;\n\n int value;\n\n} Pair;\n\n\n\n", + "func": "Pair *func0(int *arr, int size) {\n Pair *dict = (Pair *)malloc((size / 2) * sizeof(Pair));\n for (int i = 0; i < size; i += 2) {\n dict[i / 2].key = arr[i];\n dict[i / 2].value = arr[i + 1];\n }\n return dict;\n}", + "test": "int main() {\n\n int test1[] = {1, 5, 7, 10, 13, 5};\n\n Pair *dict1 = func0(test1, 6);\n\n assert((dict1[0].key == 1 && dict1[0].value == 5) && (dict1[1].key == 7 && dict1[1].value == 10) && (dict1[2].key == 13 && dict1[2].value == 5));\n\n\n\n int test2[] = {1, 2, 3, 4, 5, 6};\n\n Pair *dict2 = func0(test2, 6);\n\n assert((dict2[0].key == 1 && dict2[0].value == 2) && (dict2[1].key == 3 && dict2[1].value == 4) && (dict2[2].key == 5 && dict2[2].value == 6));\n\n\n\n int test3[] = {7, 8, 9, 10, 11, 12};\n\n Pair *dict3 = func0(test3, 6);\n\n assert((dict3[0].key == 7 && dict3[0].value == 8) && (dict3[1].key == 9 && dict3[1].value == 10) && (dict3[2].key == 11 && dict3[2].value == 12));\n\n \n\n free(dict1);\n\n free(dict2);\n\n free(dict3);\n\n \n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov -0x1c(%rbp),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\ncltq\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 1258 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0xc(%rbp),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\nmov -0xc(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0xc(%rbp),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,0x4(%rdx)\naddl $0x2,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11e3 \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov eax, [rbp+var_1C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp short loc_1258\nloc_11E3:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nmov eax, [rbp+var_C]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx+4], eax\nadd [rbp+var_C], 2\nloc_1258:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_11E3\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+14h] [rbp-Ch]\n _DWORD *v4; // [rsp+18h] [rbp-8h]\n\n v4 = malloc(8LL * (a2 / 2));\n for ( i = 0; i < a2; i += 2 )\n {\n v4[2 * (i / 2)] = *(_DWORD *)(4LL * i + a1);\n v4[2 * (i / 2) + 1] = *(_DWORD *)(4 * (i + 1LL) + a1);\n }\n return v4;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov eax, [rbp+var_1C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp short loc_1258\nloc_11E3:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nmov eax, [rbp+var_C]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx+4], eax\nadd [rbp+var_C], 2\nloc_1258:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_11E3\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(__int64 a1, int a2)\n{\n int i; // [rsp+14h] [rbp-Ch]\n _DWORD *v4; // [rsp+18h] [rbp-8h]\n\n v4 = malloc(8LL * (a2 / 2));\n for ( i = 0; i < a2; i += 2 )\n {\n v4[2 * (i / 2)] = *(_DWORD *)(4LL * i + a1);\n v4[2 * (i / 2) + 1] = *(_DWORD *)(4 * (i + 1LL) + a1);\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(long long a1, int a2) {\n int i;\n uint32_t *v4;\n v4 = malloc(8LL * (a2 / 2));\n for (i = 0; i < a2; i += 2) {\n v4[2 * (i / 2)] = *(uint32_t *)(4LL * i + a1);\n v4[2 * (i / 2) + 1] = *(uint32_t *)(4 * (i + 1LL) + a1);\n }\n return v4;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2) {\n int i;\n uint32_t *v4;\n v4 = malloc(8LL * (a2 / 2));\n for (i = 0; i < a2; i += 2) {\n v4[2 * (i / 2)] = *(uint32_t *)(4LL * i + a1);\n v4[2 * (i / 2) + 1] = *(uint32_t *)(4 * (i + 1LL) + a1);\n }\n return v4;\n}" + }, + { + "index": 740, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int key;\n\n int value;\n\n} Pair;\n\n\n\n", + "func": "Pair *func0(int *arr, int size) {\n Pair *dict = (Pair *)malloc((size / 2) * sizeof(Pair));\n for (int i = 0; i < size; i += 2) {\n dict[i / 2].key = arr[i];\n dict[i / 2].value = arr[i + 1];\n }\n return dict;\n}", + "test": "int main() {\n\n int test1[] = {1, 5, 7, 10, 13, 5};\n\n Pair *dict1 = func0(test1, 6);\n\n assert((dict1[0].key == 1 && dict1[0].value == 5) && (dict1[1].key == 7 && dict1[1].value == 10) && (dict1[2].key == 13 && dict1[2].value == 5));\n\n\n\n int test2[] = {1, 2, 3, 4, 5, 6};\n\n Pair *dict2 = func0(test2, 6);\n\n assert((dict2[0].key == 1 && dict2[0].value == 2) && (dict2[1].key == 3 && dict2[1].value == 4) && (dict2[2].key == 5 && dict2[2].value == 6));\n\n\n\n int test3[] = {7, 8, 9, 10, 11, 12};\n\n Pair *dict3 = func0(test3, 6);\n\n assert((dict3[0].key == 7 && dict3[0].value == 8) && (dict3[1].key == 9 && dict3[1].value == 10) && (dict3[2].key == 11 && dict3[2].value == 12));\n\n \n\n free(dict1);\n\n free(dict2);\n\n free(dict3);\n\n \n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbx\nmov %esi,%ebp\nmov %esi,%edi\nshr $0x1f,%edi\nadd %esi,%edi\nsar %edi\nmovslq %edi,%rdi\nshl $0x3,%rdi\ncallq 10b0 \ntest %ebp,%ebp\njle 11fa \nmov $0x0,%ecx\nmov %ecx,%edx\nshr $0x1f,%edx\nadd %ecx,%edx\nsar %edx\nmovslq %edx,%rdx\nlea (%rax,%rdx,8),%rdx\nmov (%rbx,%rcx,4),%esi\nmov %esi,(%rdx)\nmov 0x4(%rbx,%rcx,4),%esi\nmov %esi,0x4(%rdx)\nadd $0x2,%rcx\ncmp %ecx,%ebp\njg 11d6 \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov ebp, esi\nmov edi, esi\nshr edi, 1Fh\nadd edi, esi\nsar edi, 1\nmovsxd rdi, edi\nshl rdi, 3; size\ncall _malloc\ntest ebp, ebp\njle short loc_11FA\nmov ecx, 0\nloc_11D6:\nmov edx, ecx\nshr edx, 1Fh\nadd edx, ecx\nsar edx, 1\nmovsxd rdx, edx\nlea rdx, [rax+rdx*8]\nmov esi, [rbx+rcx*4]\nmov [rdx], esi\nmov esi, [rbx+rcx*4+4]\nmov [rdx+4], esi\nadd rcx, 2\ncmp ebp, ecx\njg short loc_11D6\nloc_11FA:\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2)\n{\n char *result; // rax\n __int64 v3; // rcx\n char *v4; // rdx\n\n result = (char *)malloc(8LL * (a2 / 2));\n if ( a2 > 0 )\n {\n v3 = 0LL;\n do\n {\n v4 = &result[8 * ((int)v3 / 2)];\n *(_DWORD *)v4 = *(_DWORD *)(a1 + 4 * v3);\n *((_DWORD *)v4 + 1) = *(_DWORD *)(a1 + 4 * v3 + 4);\n v3 += 2LL;\n }\n while ( a2 > (int)v3 );\n }\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov ebp, esi\nmov edi, esi\nshr edi, 1Fh\nadd edi, esi\nsar edi, 1\nmovsxd rdi, edi\nshl rdi, 3; size\ncall _malloc\ntest ebp, ebp\njle short loc_11FA\nmov ecx, 0\nloc_11D6:\nmov edx, ecx\nshr edx, 1Fh\nadd edx, ecx\nsar edx, 1\nmovsxd rdx, edx\nlea rdx, [rax+rdx*8]\nmov esi, [rbx+rcx*4]\nmov [rdx], esi\nmov esi, [rbx+rcx*4+4]\nmov [rdx+4], esi\nadd rcx, 2\ncmp ebp, ecx\njg short loc_11D6\nloc_11FA:\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11A9(__int64 a1, int a2)\n{\n char *result; // rax\n __int64 v3; // rcx\n char *v4; // rdx\n\n result = (char *)malloc(8LL * (a2 / 2));\n if ( a2 > 0 )\n {\n v3 = 0LL;\n do\n {\n v4 = &result[8 * ((int)v3 / 2)];\n *(_DWORD *)v4 = *(_DWORD *)(a1 + 4 * v3);\n *((_DWORD *)v4 + 1) = *(_DWORD *)(a1 + 4 * v3 + 4);\n v3 += 2LL;\n }\n while ( a2 > (int)v3 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11A9(long long a1, int a2) {\n char *result;\n long long v3;\n char *v4;\n result = (char *)malloc(8LL * (a2 / 2));\n if (a2 > 0) {\n v3 = 0LL;\n do {\n v4 = &result[8 * ((int)v3 / 2)];\n *(uint32_t *)v4 = *(uint32_t *)(a1 + 4 * v3);\n *((uint32_t *)v4 + 1) = *(uint32_t *)(a1 + 4 * v3 + 4);\n v3 += 2LL;\n } while (a2 > (int)v3);\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2) {\n char *result;\n long long v3;\n char *v4;\n result = (char *)malloc(8LL * (a2 / 2));\n if (a2 > 0) {\n v3 = 0LL;\n do {\n v4 = &result[8 * ((int)v3 / 2)];\n *(uint32_t *)v4 = *(uint32_t *)(a1 + 4 * v3);\n *((uint32_t *)v4 + 1) = *(uint32_t *)(a1 + 4 * v3 + 4);\n v3 += 2LL;\n } while (a2 > (int)v3);\n }\n return result;\n}" + }, + { + "index": 740, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int key;\n\n int value;\n\n} Pair;\n\n\n\n", + "func": "Pair *func0(int *arr, int size) {\n Pair *dict = (Pair *)malloc((size / 2) * sizeof(Pair));\n for (int i = 0; i < size; i += 2) {\n dict[i / 2].key = arr[i];\n dict[i / 2].value = arr[i + 1];\n }\n return dict;\n}", + "test": "int main() {\n\n int test1[] = {1, 5, 7, 10, 13, 5};\n\n Pair *dict1 = func0(test1, 6);\n\n assert((dict1[0].key == 1 && dict1[0].value == 5) && (dict1[1].key == 7 && dict1[1].value == 10) && (dict1[2].key == 13 && dict1[2].value == 5));\n\n\n\n int test2[] = {1, 2, 3, 4, 5, 6};\n\n Pair *dict2 = func0(test2, 6);\n\n assert((dict2[0].key == 1 && dict2[0].value == 2) && (dict2[1].key == 3 && dict2[1].value == 4) && (dict2[2].key == 5 && dict2[2].value == 6));\n\n\n\n int test3[] = {7, 8, 9, 10, 11, 12};\n\n Pair *dict3 = func0(test3, 6);\n\n assert((dict3[0].key == 7 && dict3[0].value == 8) && (dict3[1].key == 9 && dict3[1].value == 10) && (dict3[2].key == 11 && dict3[2].value == 12));\n\n \n\n free(dict1);\n\n free(dict2);\n\n free(dict3);\n\n \n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %esi,%ebp\npush %rbx\nmov %rdi,%rbx\nmov %esi,%edi\nshr $0x1f,%edi\nadd %esi,%edi\nsar %edi\nsub $0x8,%rsp\nmovslq %edi,%rdi\nshl $0x3,%rdi\ncallq 10b0 \ntest %ebp,%ebp\njle 140f \nxor %edx,%edx\nnopw 0x0(%rax,%rax,1)\nmov %edx,%ecx\nmov (%rbx,%rdx,4),%edi\nsar %ecx\nmovslq %ecx,%rcx\nlea (%rax,%rcx,8),%rcx\nmov %edi,(%rcx)\nmov 0x4(%rbx,%rdx,4),%edi\nadd $0x2,%rdx\nmov %edi,0x4(%rcx)\ncmp %edx,%ebp\njg 13f0 \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rdi\nmov edi, esi\nshr edi, 1Fh\npush rbx\nmov ebx, esi\nadd edi, esi\nsar edi, 1\nmovsxd rdi, edi\nsub rsp, 8\nshl rdi, 3; size\ncall _malloc\ntest ebx, ebx\njle short loc_13C8\nxor edx, edx\nnop word ptr [rax+rax+00h]\nloc_13B0:\nmov ecx, edx\nmov rdi, [rbp+rdx*4+0]\nadd rdx, 2\nsar ecx, 1\nmovsxd rcx, ecx\nmov [rax+rcx*8], rdi\ncmp ebx, edx\njg short loc_13B0\nloc_13C8:\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, int a2)\n{\n _QWORD *result; // rax\n __int64 v4; // rdx\n int v5; // ecx\n __int64 v6; // rdi\n\n result = malloc(8LL * (a2 / 2));\n if ( a2 > 0 )\n {\n v4 = 0LL;\n do\n {\n v5 = v4;\n v6 = *(_QWORD *)(a1 + 4 * v4);\n v4 += 2LL;\n result[v5 >> 1] = v6;\n }\n while ( a2 > (int)v4 );\n }\n return result;\n}", + "ida_strip_asm": "sub_1380:\nendbr64\npush rbp\nmov rbp, rdi\nmov edi, esi\nshr edi, 1Fh\npush rbx\nmov ebx, esi\nadd edi, esi\nsar edi, 1\nmovsxd rdi, edi\nsub rsp, 8\nshl rdi, 3; size\ncall _malloc\ntest ebx, ebx\njle short loc_13C8\nxor edx, edx\nnop word ptr [rax+rax+00h]\nloc_13B0:\nmov ecx, edx\nmov rdi, [rbp+rdx*4+0]\nadd rdx, 2\nsar ecx, 1\nmovsxd rcx, ecx\nmov [rax+rcx*8], rdi\ncmp ebx, edx\njg short loc_13B0\nloc_13C8:\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1380(__int64 a1, int a2)\n{\n _QWORD *result; // rax\n __int64 v4; // rdx\n int v5; // ecx\n __int64 v6; // rdi\n\n result = malloc(8LL * (a2 / 2));\n if ( a2 > 0 )\n {\n v4 = 0LL;\n do\n {\n v5 = v4;\n v6 = *(_QWORD *)(a1 + 4 * v4);\n v4 += 2LL;\n result[v5 >> 1] = v6;\n }\n while ( a2 > (int)v4 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1380(long long a1, int a2) {\n uint64_t *result;\n long long v4;\n int v5;\n long long v6;\n result = malloc(8LL * (a2 / 2));\n if (a2 > 0) {\n v4 = 0LL;\n do {\n v5 = v4;\n v6 = *(uint64_t *)(a1 + 4 * v4);\n v4 += 2LL;\n result[v5 >> 1] = v6;\n } while (a2 > (int)v4);\n }\n return result;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, int a2) {\n uint64_t *result;\n long long v4;\n int v5;\n long long v6;\n result = malloc(8LL * (a2 / 2));\n if (a2 > 0) {\n v4 = 0LL;\n do {\n v5 = v4;\n v6 = *(uint64_t *)(a1 + 4 * v4);\n v4 += 2LL;\n result[v5 >> 1] = v6;\n } while (a2 > (int)v4);\n }\n return result;\n}" + }, + { + "index": 740, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int key;\n\n int value;\n\n} Pair;\n\n\n\n", + "func": "Pair *func0(int *arr, int size) {\n Pair *dict = (Pair *)malloc((size / 2) * sizeof(Pair));\n for (int i = 0; i < size; i += 2) {\n dict[i / 2].key = arr[i];\n dict[i / 2].value = arr[i + 1];\n }\n return dict;\n}", + "test": "int main() {\n\n int test1[] = {1, 5, 7, 10, 13, 5};\n\n Pair *dict1 = func0(test1, 6);\n\n assert((dict1[0].key == 1 && dict1[0].value == 5) && (dict1[1].key == 7 && dict1[1].value == 10) && (dict1[2].key == 13 && dict1[2].value == 5));\n\n\n\n int test2[] = {1, 2, 3, 4, 5, 6};\n\n Pair *dict2 = func0(test2, 6);\n\n assert((dict2[0].key == 1 && dict2[0].value == 2) && (dict2[1].key == 3 && dict2[1].value == 4) && (dict2[2].key == 5 && dict2[2].value == 6));\n\n\n\n int test3[] = {7, 8, 9, 10, 11, 12};\n\n Pair *dict3 = func0(test3, 6);\n\n assert((dict3[0].key == 7 && dict3[0].value == 8) && (dict3[1].key == 9 && dict3[1].value == 10) && (dict3[2].key == 11 && dict3[2].value == 12));\n\n \n\n free(dict1);\n\n free(dict2);\n\n free(dict3);\n\n \n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %esi,%ebp\npush %rbx\nmov %rdi,%rbx\nmov %esi,%edi\nshr $0x1f,%edi\nadd %esi,%edi\nsar %edi\nsub $0x8,%rsp\nmovslq %edi,%rdi\nshl $0x3,%rdi\ncallq 10b0 \ntest %ebp,%ebp\njle 13df \nxor %edx,%edx\nnopw 0x0(%rax,%rax,1)\nmov %edx,%ecx\nmov (%rbx,%rdx,4),%edi\nsar %ecx\nmovslq %ecx,%rcx\nlea (%rax,%rcx,8),%rcx\nmov %edi,(%rcx)\nmov 0x4(%rbx,%rdx,4),%edi\nadd $0x2,%rdx\nmov %edi,0x4(%rcx)\ncmp %edx,%ebp\njg 13c0 \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rdi\nmov edi, esi\nshr edi, 1Fh\npush rbx\nmov ebx, esi\nadd edi, esi\nsar edi, 1\nmovsxd rdi, edi\nsub rsp, 8\nshl rdi, 3; size\ncall _malloc\ntest ebx, ebx\njle short loc_13C8\nxor edx, edx\nnop word ptr [rax+rax+00h]\nloc_13B0:\nmov ecx, edx\nmov rdi, [rbp+rdx*4+0]\nadd rdx, 2\nsar ecx, 1\nmovsxd rcx, ecx\nmov [rax+rcx*8], rdi\ncmp ebx, edx\njg short loc_13B0\nloc_13C8:\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, int a2)\n{\n _QWORD *result; // rax\n __int64 v4; // rdx\n int v5; // ecx\n __int64 v6; // rdi\n\n result = malloc(8LL * (a2 / 2));\n if ( a2 > 0 )\n {\n v4 = 0LL;\n do\n {\n v5 = v4;\n v6 = *(_QWORD *)(a1 + 4 * v4);\n v4 += 2LL;\n result[v5 >> 1] = v6;\n }\n while ( a2 > (int)v4 );\n }\n return result;\n}", + "ida_strip_asm": "sub_1380:\nendbr64\npush rbp\nmov rbp, rdi\nmov edi, esi\nshr edi, 1Fh\npush rbx\nmov ebx, esi\nadd edi, esi\nsar edi, 1\nmovsxd rdi, edi\nsub rsp, 8\nshl rdi, 3; size\ncall _malloc\ntest ebx, ebx\njle short loc_13C8\nxor edx, edx\nnop word ptr [rax+rax+00h]\nloc_13B0:\nmov ecx, edx\nmov rdi, [rbp+rdx*4+0]\nadd rdx, 2\nsar ecx, 1\nmovsxd rcx, ecx\nmov [rax+rcx*8], rdi\ncmp ebx, edx\njg short loc_13B0\nloc_13C8:\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1380(__int64 a1, int a2)\n{\n _QWORD *result; // rax\n __int64 v4; // rdx\n int v5; // ecx\n __int64 v6; // rdi\n\n result = malloc(8LL * (a2 / 2));\n if ( a2 > 0 )\n {\n v4 = 0LL;\n do\n {\n v5 = v4;\n v6 = *(_QWORD *)(a1 + 4 * v4);\n v4 += 2LL;\n result[v5 >> 1] = v6;\n }\n while ( a2 > (int)v4 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1380(long long a1, int a2) {\n uint64_t *result;\n long long v4;\n int v5;\n long long v6;\n result = malloc(8LL * (a2 / 2));\n if (a2 > 0) {\n v4 = 0LL;\n do {\n v5 = v4;\n v6 = *(uint64_t *)(a1 + 4 * v4);\n v4 += 2LL;\n result[v5 >> 1] = v6;\n } while (a2 > (int)v4);\n }\n return result;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, int a2) {\n uint64_t *result;\n long long v4;\n int v5;\n long long v6;\n result = malloc(8LL * (a2 / 2));\n if (a2 > 0) {\n v4 = 0LL;\n do {\n v5 = v4;\n v6 = *(uint64_t *)(a1 + 4 * v4);\n v4 += 2LL;\n result[v5 >> 1] = v6;\n } while (a2 > (int)v4);\n }\n return result;\n}" + }, + { + "index": 741, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char *s) {\n int n = strlen(s);\n for (int i = 1; i < n; i++) {\n if (s[i] != s[0]) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n assert(func0(\"python\") == false);\n\n assert(func0(\"aaa\") == true);\n\n assert(func0(\"data\") == false);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov -0x18(%rbp),%rax\nmov %rax,%rdi\ncallq 1060 \nmov %eax,-0x4(%rbp)\nmovl $0x1,-0x8(%rbp)\njmp 11b7 \nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%edx\nmov -0x18(%rbp),%rax\nmovzbl (%rax),%eax\ncmp %al,%dl\nje 11b3 \nmov $0x0,%eax\njmp 11c4 \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x4(%rbp),%eax\njl 1191 \nmov $0x1,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_8], 1\njmp short loc_11B7\nloc_1191:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov rax, [rbp+s]\nmovzx eax, byte ptr [rax]\ncmp dl, al\njz short loc_11B3\nmov eax, 0\njmp short locret_11C4\nloc_11B3:\nadd [rbp+var_8], 1\nloc_11B7:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njl short loc_1191\nmov eax, 1\nlocret_11C4:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int i; // [rsp+18h] [rbp-8h]\n int v3; // [rsp+1Ch] [rbp-4h]\n\n v3 = strlen(a1);\n for ( i = 1; i < v3; ++i )\n {\n if ( a1[i] != *a1 )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_8], 1\njmp short loc_11B7\nloc_1191:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov rax, [rbp+s]\nmovzx eax, byte ptr [rax]\ncmp dl, al\njz short loc_11B3\nmov eax, 0\njmp short locret_11C4\nloc_11B3:\nadd [rbp+var_8], 1\nloc_11B7:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njl short loc_1191\nmov eax, 1\nlocret_11C4:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1)\n{\n int i; // [rsp+18h] [rbp-8h]\n int v3; // [rsp+1Ch] [rbp-4h]\n\n v3 = strlen(a1);\n for ( i = 1; i < v3; ++i )\n {\n if ( a1[i] != *a1 )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1) {\n int i;\n int v3;\n v3 = strlen(a1);\n for (i = 1; i < v3; ++i) {\n if (a1[i] != *a1) return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int i;\n int v3;\n v3 = strlen(a1);\n for (i = 1; i < v3; ++i) {\n if (a1[i] != *a1) return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": 741, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char *s) {\n int n = strlen(s);\n for (int i = 1; i < n; i++) {\n if (s[i] != s[0]) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n assert(func0(\"python\") == false);\n\n assert(func0(\"aaa\") == true);\n\n assert(func0(\"data\") == false);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%rsi\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nsub $0x1,%rcx\ncmp $0x1,%ecx\njle 118c \nmovzbl (%rsi),%edx\nlea 0x1(%rsi),%rax\nlea -0x2(%rcx),%ecx\nlea 0x2(%rsi,%rcx,1),%rcx\ncmp %dl,(%rax)\njne 1192 \nadd $0x1,%rax\ncmp %rcx,%rax\njne 1179 \nmov $0x1,%eax\nretq\nmov $0x1,%eax\nretq\nmov $0x0,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ncmp eax, 1\njle short loc_119E\nmovzx ecx, byte ptr [rbx]\nlea rdx, [rbx+1]\nlea eax, [rax-2]\nlea rax, [rbx+rax+2]\nloc_118A:\ncmp [rdx], cl\njnz short loc_11A5\nadd rdx, 1\ncmp rdx, rax\njnz short loc_118A\nmov eax, 1\njmp short loc_11AA\nloc_119E:\nmov eax, 1\njmp short loc_11AA\nloc_11A5:\nmov eax, 0\nloc_11AA:\npop rbx\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v1; // eax\n _BYTE *v2; // rdx\n __int64 v3; // rax\n\n v1 = strlen(a1);\n if ( v1 <= 1 )\n return 1LL;\n v2 = a1 + 1;\n v3 = (__int64)&a1[v1 - 2 + 2];\n while ( *v2 == *a1 )\n {\n if ( ++v2 == (_BYTE *)v3 )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ncmp eax, 1\njle short loc_119E\nmovzx ecx, byte ptr [rbx]\nlea rdx, [rbx+1]\nlea eax, [rax-2]\nlea rax, [rbx+rax+2]\nloc_118A:\ncmp [rdx], cl\njnz short loc_11A5\nadd rdx, 1\ncmp rdx, rax\njnz short loc_118A\nmov eax, 1\njmp short loc_11AA\nloc_119E:\nmov eax, 1\njmp short loc_11AA\nloc_11A5:\nmov eax, 0\nloc_11AA:\npop rbx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1)\n{\n int v1; // eax\n _BYTE *v2; // rdx\n __int64 v3; // rax\n\n v1 = strlen(a1);\n if ( v1 <= 1 )\n return 1LL;\n v2 = a1 + 1;\n v3 = (__int64)&a1[v1 - 2 + 2];\n while ( *v2 == *a1 )\n {\n if ( ++v2 == (_BYTE *)v3 )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1) {\n int v1;\n uint8_t *v2;\n long long v3;\n v1 = strlen(a1);\n if (v1 <= 1) return 1LL;\n v2 = a1 + 1;\n v3 = (long long)&a1[v1 - 2 + 2];\n while (*v2 == *a1) {\n if (++v2 == (uint8_t *)v3) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v1;\n uint8_t *v2;\n long long v3;\n v1 = strlen(a1);\n if (v1 <= 1) return 1LL;\n v2 = a1 + 1;\n v3 = (long long)&a1[v1 - 2 + 2];\n while (*v2 == *a1) {\n if (++v2 == (uint8_t *)v3) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 741, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char *s) {\n int n = strlen(s);\n for (int i = 1; i < n; i++) {\n if (s[i] != s[0]) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n assert(func0(\"python\") == false);\n\n assert(func0(\"aaa\") == true);\n\n assert(func0(\"data\") == false);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\ncallq 1060 \ncmp $0x1,%eax\njle 1250 \nsub $0x2,%eax\nmovzbl (%rbx),%ecx\nlea 0x1(%rbx),%rdx\nlea 0x2(%rbx,%rax,1),%rax\njmp 1241 \nnopl 0x0(%rax,%rax,1)\nadd $0x1,%rdx\ncmp %rax,%rdx\nje 1250 \ncmp %cl,(%rdx)\nje 1238 \nxor %eax,%eax\npop %rbx\nretq\nnopl 0x0(%rax)\nmov $0x1,%eax\npop %rbx\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ncmp eax, 1\njle short loc_1250\nsub eax, 2\nmovzx ecx, byte ptr [rbx]\nlea rdx, [rbx+1]\nlea rax, [rbx+rax+2]\njmp short loc_1241\nloc_1238:\nadd rdx, 1\ncmp rdx, rax\njz short loc_1250\nloc_1241:\ncmp [rdx], cl\njz short loc_1238\nxor eax, eax\npop rbx\nretn\nloc_1250:\nmov eax, 1\npop rbx\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v1; // eax\n _BYTE *v2; // rdx\n __int64 v3; // rax\n\n v1 = strlen(a1);\n if ( v1 <= 1 )\n return 1LL;\n v2 = a1 + 1;\n v3 = (__int64)&a1[v1 - 2 + 2];\n while ( *v2 == *a1 )\n {\n if ( ++v2 == (_BYTE *)v3 )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ncmp eax, 1\njle short loc_1250\nsub eax, 2\nmovzx ecx, byte ptr [rbx]\nlea rdx, [rbx+1]\nlea rax, [rbx+rax+2]\njmp short loc_1241\nloc_1238:\nadd rdx, 1\ncmp rdx, rax\njz short loc_1250\nloc_1241:\ncmp [rdx], cl\njz short loc_1238\nxor eax, eax\npop rbx\nretn\nloc_1250:\nmov eax, 1\npop rbx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(const char *a1)\n{\n int v1; // eax\n _BYTE *v2; // rdx\n __int64 v3; // rax\n\n v1 = strlen(a1);\n if ( v1 <= 1 )\n return 1LL;\n v2 = a1 + 1;\n v3 = (__int64)&a1[v1 - 2 + 2];\n while ( *v2 == *a1 )\n {\n if ( ++v2 == (_BYTE *)v3 )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(const char *a1) {\n int v1;\n uint8_t *v2;\n long long v3;\n v1 = strlen(a1);\n if (v1 <= 1) return 1LL;\n v2 = a1 + 1;\n v3 = (long long)&a1[v1 - 2 + 2];\n while (*v2 == *a1) {\n if (++v2 == (uint8_t *)v3) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v1;\n uint8_t *v2;\n long long v3;\n v1 = strlen(a1);\n if (v1 <= 1) return 1LL;\n v2 = a1 + 1;\n v3 = (long long)&a1[v1 - 2 + 2];\n while (*v2 == *a1) {\n if (++v2 == (uint8_t *)v3) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 741, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char *s) {\n int n = strlen(s);\n for (int i = 1; i < n; i++) {\n if (s[i] != s[0]) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n assert(func0(\"python\") == false);\n\n assert(func0(\"aaa\") == true);\n\n assert(func0(\"data\") == false);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\ncallq 1060 \ncmp $0x1,%eax\njle 1250 \nsub $0x2,%eax\nmovzbl (%rbx),%ecx\nlea 0x1(%rbx),%rdx\nlea 0x2(%rbx,%rax,1),%rax\njmp 1241 \nnopl 0x0(%rax,%rax,1)\nadd $0x1,%rdx\ncmp %rax,%rdx\nje 1250 \ncmp %cl,(%rdx)\nje 1238 \nxor %eax,%eax\npop %rbx\nretq\nnopl 0x0(%rax)\nmov $0x1,%eax\npop %rbx\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ncmp eax, 1\njle short loc_1250\nsub eax, 2\nmovzx ecx, byte ptr [rbx]\nlea rdx, [rbx+1]\nlea rax, [rbx+rax+2]\njmp short loc_1241\nloc_1238:\nadd rdx, 1\ncmp rdx, rax\njz short loc_1250\nloc_1241:\ncmp [rdx], cl\njz short loc_1238\nxor eax, eax\npop rbx\nretn\nloc_1250:\nmov eax, 1\npop rbx\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v1; // eax\n _BYTE *v2; // rdx\n __int64 v3; // rax\n\n v1 = strlen(a1);\n if ( v1 <= 1 )\n return 1LL;\n v2 = a1 + 1;\n v3 = (__int64)&a1[v1 - 2 + 2];\n while ( *v2 == *a1 )\n {\n if ( ++v2 == (_BYTE *)v3 )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ncmp eax, 1\njle short loc_1250\nsub eax, 2\nmovzx ecx, byte ptr [rbx]\nlea rdx, [rbx+1]\nlea rax, [rbx+rax+2]\njmp short loc_1241\nloc_1238:\nadd rdx, 1\ncmp rdx, rax\njz short loc_1250\nloc_1241:\ncmp [rdx], cl\njz short loc_1238\nxor eax, eax\npop rbx\nretn\nloc_1250:\nmov eax, 1\npop rbx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(const char *a1)\n{\n int v1; // eax\n _BYTE *v2; // rdx\n __int64 v3; // rax\n\n v1 = strlen(a1);\n if ( v1 <= 1 )\n return 1LL;\n v2 = a1 + 1;\n v3 = (__int64)&a1[v1 - 2 + 2];\n while ( *v2 == *a1 )\n {\n if ( ++v2 == (_BYTE *)v3 )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(const char *a1) {\n int v1;\n uint8_t *v2;\n long long v3;\n v1 = strlen(a1);\n if (v1 <= 1) return 1LL;\n v2 = a1 + 1;\n v3 = (long long)&a1[v1 - 2 + 2];\n while (*v2 == *a1) {\n if (++v2 == (uint8_t *)v3) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v1;\n uint8_t *v2;\n long long v3;\n v1 = strlen(a1);\n if (v1 <= 1) return 1LL;\n v2 = a1 + 1;\n v3 = (long long)&a1[v1 - 2 + 2];\n while (*v2 == *a1) {\n if (++v2 == (uint8_t *)v3) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 742, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(double side) {\n double area = sqrt(3) * (side * side);\n return area;\n}", + "test": "int main() {\n\n assert(func0(3) == 15.588457268119894);\n\n assert(func0(20) == 692.8203230275509);\n\n assert(func0(10) == 173.20508075688772);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmovsd %xmm0,-0x18(%rbp)\nmovsd -0x18(%rbp),%xmm0\nmovapd %xmm0,%xmm1\nmulsd %xmm0,%xmm1\nmovsd 0xf45(%rip),%xmm0\nmulsd %xmm1,%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmovsd -0x8(%rbp),%xmm0\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmovsd [rbp+var_18], xmm0\nmovsd xmm0, [rbp+var_18]\nmovapd xmm1, xmm0\nmulsd xmm1, xmm0\nmovsd xmm0, cs:qword_2090\nmulsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "double __fastcall func0(double a1)\n{\n return 1.732050807568877 * (a1 * a1);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmovsd [rbp+var_18], xmm0\nmovsd xmm0, [rbp+var_18]\nmovapd xmm1, xmm0\nmulsd xmm1, xmm0\nmovsd xmm0, cs:qword_2090\nmulsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "double __fastcall sub_1149(double a1)\n{\n return 1.732050807568877 * (a1 * a1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1149(double a1) { return 1.732050807568877 * (a1 * a1); }", + "ida_pseudo_norm": "double func0(double a1) { return 1.732050807568877 * (a1 * a1); }" + }, + { + "index": 743, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int list1[], int size, int m, int n) {\n int new_size = m + (size - n);\n int* result = (int*)malloc(new_size * sizeof(int));\n for (int i = 0; i < m; i++) {\n result[i] = list1[size - m + i];\n }\n for (int i = 0; i < (size - n); i++) {\n result[m + i] = list1[i];\n }\n return result;\n}", + "test": "int main() {\n\n int list1a[] = {1,2,3,4,5,6,7,8,9,10};\n\n int expected1[] = {8,9,10,1,2,3,4,5,6};\n\n int* result1 = func0(list1a, 10, 3, 4);\n\n assert(memcmp(result1, expected1, 9 * sizeof(int)) == 0);\n\n free(result1);\n\n \n\n int list1b[] = {1,2,3,4,5,6,7,8,9,10};\n\n int expected2[] = {9,10,1,2,3,4,5,6,7,8};\n\n int* result2 = func0(list1b, 10, 2, 2);\n\n assert(memcmp(result2, expected2, 10 * sizeof(int)) == 0);\n\n free(result2);\n\n \n\n int list1c[] = {1,2,3,4,5,6,7,8,9,10};\n\n int expected3[] = {6,7,8,9,10,1,2,3,4,5,6,7,8};\n\n int* result3 = func0(list1c, 10, 5, 2);\n\n assert(memcmp(result3, expected3, 13 * sizeof(int)) == 0);\n\n free(result3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x40,%rsp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmov %edx,-0x30(%rbp)\nmov %ecx,-0x34(%rbp)\nmov -0x2c(%rbp),%eax\nsub -0x34(%rbp),%eax\nmov %eax,%edx\nmov -0x30(%rbp),%eax\nadd %edx,%eax\nmov %eax,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0x14(%rbp)\njmp 124b \nmov -0x2c(%rbp),%eax\nsub -0x30(%rbp),%eax\nmov %eax,%edx\nmov -0x14(%rbp),%eax\nadd %edx,%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov -0x14(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\ncmp -0x30(%rbp),%eax\njl 1210 \nmovl $0x0,-0x10(%rbp)\njmp 1292 \nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov -0x30(%rbp),%ecx\nmov -0x10(%rbp),%edx\nadd %ecx,%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x10(%rbp)\nmov -0x2c(%rbp),%eax\nsub -0x34(%rbp),%eax\ncmp %eax,-0x10(%rbp)\njl 125c \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_30], edx\nmov [rbp+var_34], ecx\nmov eax, [rbp+var_2C]\nsub eax, [rbp+var_34]\nmov edx, eax\nmov eax, [rbp+var_30]\nadd eax, edx\nmov [rbp+var_C], eax\nmov eax, [rbp+var_C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_14], 0\njmp short loc_124B\nloc_1210:\nmov eax, [rbp+var_2C]\nsub eax, [rbp+var_30]\nmov edx, eax\nmov eax, [rbp+var_14]\nadd eax, edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_14], 1\nloc_124B:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_30]\njl short loc_1210\nmov [rbp+var_10], 0\njmp short loc_1292\nloc_125C:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov ecx, [rbp+var_30]\nmov edx, [rbp+var_10]\nadd edx, ecx\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_10], 1\nloc_1292:\nmov eax, [rbp+var_2C]\nsub eax, [rbp+var_34]\ncmp [rbp+var_10], eax\njl short loc_125C\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, int a3, int a4)\n{\n int i; // [rsp+2Ch] [rbp-14h]\n int j; // [rsp+30h] [rbp-10h]\n _DWORD *v9; // [rsp+38h] [rbp-8h]\n\n v9 = malloc(4LL * (a2 - a4 + a3));\n for ( i = 0; i < a3; ++i )\n v9[i] = *(_DWORD *)(4LL * (a2 - a3 + i) + a1);\n for ( j = 0; j < a2 - a4; ++j )\n v9[a3 + j] = *(_DWORD *)(4LL * j + a1);\n return v9;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_30], edx\nmov [rbp+var_34], ecx\nmov eax, [rbp+var_2C]\nsub eax, [rbp+var_34]\nmov edx, eax\nmov eax, [rbp+var_30]\nadd eax, edx\nmov [rbp+var_C], eax\nmov eax, [rbp+var_C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_14], 0\njmp short loc_124B\nloc_1210:\nmov eax, [rbp+var_2C]\nsub eax, [rbp+var_30]\nmov edx, eax\nmov eax, [rbp+var_14]\nadd eax, edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_14], 1\nloc_124B:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_30]\njl short loc_1210\nmov [rbp+var_10], 0\njmp short loc_1292\nloc_125C:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov ecx, [rbp+var_30]\nmov edx, [rbp+var_10]\nadd edx, ecx\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_10], 1\nloc_1292:\nmov eax, [rbp+var_2C]\nsub eax, [rbp+var_34]\ncmp [rbp+var_10], eax\njl short loc_125C\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11C9(__int64 a1, int a2, int a3, int a4)\n{\n int i; // [rsp+2Ch] [rbp-14h]\n int j; // [rsp+30h] [rbp-10h]\n _DWORD *v9; // [rsp+38h] [rbp-8h]\n\n v9 = malloc(4LL * (a2 - a4 + a3));\n for ( i = 0; i < a3; ++i )\n v9[i] = *(_DWORD *)(4LL * (a2 - a3 + i) + a1);\n for ( j = 0; j < a2 - a4; ++j )\n v9[a3 + j] = *(_DWORD *)(4LL * j + a1);\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11C9(long long a1, int a2, int a3, int a4) {\n int i;\n int j;\n uint32_t *v9;\n v9 = malloc(4LL * (a2 - a4 + a3));\n for (i = 0; i < a3; ++i) v9[i] = *(uint32_t *)(4LL * (a2 - a3 + i) + a1);\n for (j = 0; j < a2 - a4; ++j) v9[a3 + j] = *(uint32_t *)(4LL * j + a1);\n return v9;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, int a3, int a4) {\n int i;\n int j;\n uint32_t *v9;\n v9 = malloc(4LL * (a2 - a4 + a3));\n for (i = 0; i < a3; ++i) v9[i] = *(uint32_t *)(4LL * (a2 - a3 + i) + a1);\n for (j = 0; j < a2 - a4; ++j) v9[a3 + j] = *(uint32_t *)(4LL * j + a1);\n return v9;\n}" + }, + { + "index": 743, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int list1[], int size, int m, int n) {\n int new_size = m + (size - n);\n int* result = (int*)malloc(new_size * sizeof(int));\n for (int i = 0; i < m; i++) {\n result[i] = list1[size - m + i];\n }\n for (int i = 0; i < (size - n); i++) {\n result[m + i] = list1[i];\n }\n return result;\n}", + "test": "int main() {\n\n int list1a[] = {1,2,3,4,5,6,7,8,9,10};\n\n int expected1[] = {8,9,10,1,2,3,4,5,6};\n\n int* result1 = func0(list1a, 10, 3, 4);\n\n assert(memcmp(result1, expected1, 9 * sizeof(int)) == 0);\n\n free(result1);\n\n \n\n int list1b[] = {1,2,3,4,5,6,7,8,9,10};\n\n int expected2[] = {9,10,1,2,3,4,5,6,7,8};\n\n int* result2 = func0(list1b, 10, 2, 2);\n\n assert(memcmp(result2, expected2, 10 * sizeof(int)) == 0);\n\n free(result2);\n\n \n\n int list1c[] = {1,2,3,4,5,6,7,8,9,10};\n\n int expected3[] = {6,7,8,9,10,1,2,3,4,5,6,7,8};\n\n int* result3 = func0(list1c, 10, 5, 2);\n\n assert(memcmp(result3, expected3, 13 * sizeof(int)) == 0);\n\n free(result3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbx\nmov %esi,%r13d\nmov %edx,%ebp\nmov %esi,%r12d\nsub %ecx,%r12d\nlea (%r12,%rdx,1),%edi\nmovslq %edi,%rdi\nshl $0x2,%rdi\ncallq 10d0 \ntest %ebp,%ebp\njle 1220 \nlea -0x1(%rbp),%edi\nmovslq %ebp,%rdx\nmovslq %r13d,%r13\nsub %rdx,%r13\nlea (%rbx,%r13,4),%rsi\nmov $0x0,%edx\nmov (%rsi,%rdx,4),%ecx\nmov %ecx,(%rax,%rdx,4)\nmov %rdx,%rcx\nadd $0x1,%rdx\ncmp %rdi,%rcx\njne 120e \ntest %r12d,%r12d\njle 1248 \nlea -0x1(%r12),%edi\nmovslq %ebp,%rbp\nlea (%rax,%rbp,4),%rsi\nmov $0x0,%edx\nmov (%rbx,%rdx,4),%ecx\nmov %ecx,(%rsi,%rdx,4)\nmov %rdx,%rcx\nadd $0x1,%rdx\ncmp %rcx,%rdi\njne 1236 \nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov r13d, esi\nmov r12d, edx\nmov ebp, esi\nsub ebp, ecx\nlea edi, [rbp+rdx+0]\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov rsi, rax\ntest r12d, r12d\njle short loc_1225\nmovsxd rax, r12d\nlea rdi, ds:0[rax*4]\nmovsxd r13, r13d\nsub r13, rax\nlea rcx, [rbx+r13*4]\nmov eax, 0\nloc_1216:\nmov edx, [rcx+rax]\nmov [rsi+rax], edx\nadd rax, 4\ncmp rax, rdi\njnz short loc_1216\nloc_1225:\ntest ebp, ebp\njle short loc_124B\nmovsxd rcx, ebp\nshl rcx, 2\nmovsxd r12, r12d\nlea rdi, [rsi+r12*4]\nmov eax, 0\nloc_123C:\nmov edx, [rbx+rax]\nmov [rdi+rax], edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_123C\nloc_124B:\nmov rax, rsi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2, int a3, int a4)\n{\n int v6; // ebp\n char *v7; // rsi\n __int64 v8; // r13\n __int64 v9; // rax\n __int64 v10; // rax\n\n v6 = a2 - a4;\n v7 = (char *)malloc(4LL * (a2 - a4 + a3));\n if ( a3 > 0 )\n {\n v8 = a2 - (__int64)a3;\n v9 = 0LL;\n do\n {\n *(_DWORD *)&v7[v9] = *(_DWORD *)(a1 + 4 * v8 + v9);\n v9 += 4LL;\n }\n while ( v9 != 4LL * a3 );\n }\n if ( v6 > 0 )\n {\n v10 = 0LL;\n do\n {\n *(_DWORD *)&v7[4 * a3 + v10] = *(_DWORD *)(a1 + v10);\n v10 += 4LL;\n }\n while ( v10 != 4LL * v6 );\n }\n return v7;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov r13d, esi\nmov r12d, edx\nmov ebp, esi\nsub ebp, ecx\nlea edi, [rbp+rdx+0]\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov rsi, rax\ntest r12d, r12d\njle short loc_1225\nmovsxd rax, r12d\nlea rdi, ds:0[rax*4]\nmovsxd r13, r13d\nsub r13, rax\nlea rcx, [rbx+r13*4]\nmov eax, 0\nloc_1216:\nmov edx, [rcx+rax]\nmov [rsi+rax], edx\nadd rax, 4\ncmp rax, rdi\njnz short loc_1216\nloc_1225:\ntest ebp, ebp\njle short loc_124B\nmovsxd rcx, ebp\nshl rcx, 2\nmovsxd r12, r12d\nlea rdi, [rsi+r12*4]\nmov eax, 0\nloc_123C:\nmov edx, [rbx+rax]\nmov [rdi+rax], edx\nadd rax, 4\ncmp rax, rcx\njnz short loc_123C\nloc_124B:\nmov rax, rsi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11C9(__int64 a1, int a2, int a3, int a4)\n{\n int v6; // ebp\n char *v7; // rsi\n __int64 v8; // r13\n __int64 v9; // rax\n __int64 v10; // rax\n\n v6 = a2 - a4;\n v7 = (char *)malloc(4LL * (a2 - a4 + a3));\n if ( a3 > 0 )\n {\n v8 = a2 - (__int64)a3;\n v9 = 0LL;\n do\n {\n *(_DWORD *)&v7[v9] = *(_DWORD *)(a1 + 4 * v8 + v9);\n v9 += 4LL;\n }\n while ( v9 != 4LL * a3 );\n }\n if ( v6 > 0 )\n {\n v10 = 0LL;\n do\n {\n *(_DWORD *)&v7[4 * a3 + v10] = *(_DWORD *)(a1 + v10);\n v10 += 4LL;\n }\n while ( v10 != 4LL * v6 );\n }\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11C9(long long a1, int a2, int a3, int a4) {\n int v6;\n char *v7;\n long long v8;\n long long v9;\n long long v10;\n v6 = a2 - a4;\n v7 = (char *)malloc(4LL * (a2 - a4 + a3));\n if (a3 > 0) {\n v8 = a2 - (long long)a3;\n v9 = 0LL;\n do {\n *(uint32_t *)&v7[v9] = *(uint32_t *)(a1 + 4 * v8 + v9);\n v9 += 4LL;\n } while (v9 != 4LL * a3);\n }\n if (v6 > 0) {\n v10 = 0LL;\n do {\n *(uint32_t *)&v7[4 * a3 + v10] = *(uint32_t *)(a1 + v10);\n v10 += 4LL;\n } while (v10 != 4LL * v6);\n }\n return v7;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2, int a3, int a4) {\n int v6;\n char *v7;\n long long v8;\n long long v9;\n long long v10;\n v6 = a2 - a4;\n v7 = (char *)malloc(4LL * (a2 - a4 + a3));\n if (a3 > 0) {\n v8 = a2 - (long long)a3;\n v9 = 0LL;\n do {\n *(uint32_t *)&v7[v9] = *(uint32_t *)(a1 + 4 * v8 + v9);\n v9 += 4LL;\n } while (v9 != 4LL * a3);\n }\n if (v6 > 0) {\n v10 = 0LL;\n do {\n *(uint32_t *)&v7[4 * a3 + v10] = *(uint32_t *)(a1 + v10);\n v10 += 4LL;\n } while (v10 != 4LL * v6);\n }\n return v7;\n}" + }, + { + "index": 743, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int list1[], int size, int m, int n) {\n int new_size = m + (size - n);\n int* result = (int*)malloc(new_size * sizeof(int));\n for (int i = 0; i < m; i++) {\n result[i] = list1[size - m + i];\n }\n for (int i = 0; i < (size - n); i++) {\n result[m + i] = list1[i];\n }\n return result;\n}", + "test": "int main() {\n\n int list1a[] = {1,2,3,4,5,6,7,8,9,10};\n\n int expected1[] = {8,9,10,1,2,3,4,5,6};\n\n int* result1 = func0(list1a, 10, 3, 4);\n\n assert(memcmp(result1, expected1, 9 * sizeof(int)) == 0);\n\n free(result1);\n\n \n\n int list1b[] = {1,2,3,4,5,6,7,8,9,10};\n\n int expected2[] = {9,10,1,2,3,4,5,6,7,8};\n\n int* result2 = func0(list1b, 10, 2, 2);\n\n assert(memcmp(result2, expected2, 10 * sizeof(int)) == 0);\n\n free(result2);\n\n \n\n int list1c[] = {1,2,3,4,5,6,7,8,9,10};\n\n int expected3[] = {6,7,8,9,10,1,2,3,4,5,6,7,8};\n\n int* result3 = func0(list1c, 10, 5, 2);\n\n assert(memcmp(result3, expected3, 13 * sizeof(int)) == 0);\n\n free(result3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov %esi,%r13d\npush %r12\nsub %ecx,%r13d\nmov %esi,%r12d\npush %rbp\nmovslq %edx,%rbp\npush %rbx\nmov %rdi,%rbx\nlea 0x0(%r13,%rbp,1),%edi\nmovslq %edi,%rdi\nshl $0x2,%rdi\nsub $0x8,%rsp\ncallq 10b0 \ntest %ebp,%ebp\njle 156a \nsub %ebp,%r12d\nlea -0x1(%rbp),%edi\nxor %ecx,%ecx\nmovslq %r12d,%r12\nlea (%rbx,%r12,4),%rdx\nnopl 0x0(%rax)\nmov (%rdx,%rcx,4),%esi\nmov %esi,(%rax,%rcx,4)\nmov %rcx,%rsi\nadd $0x1,%rcx\ncmp %rsi,%rdi\njne 1558 \ntest %r13d,%r13d\njle 1592 \nlea -0x1(%r13),%edi\nlea (%rax,%rbp,4),%rsi\nxor %edx,%edx\nnopl 0x0(%rax)\nmov (%rbx,%rdx,4),%ecx\nmov %ecx,(%rsi,%rdx,4)\nmov %rdx,%rcx\nadd $0x1,%rdx\ncmp %rdi,%rcx\njne 1580 \nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r14\nmov r14d, esi\nsub r14d, ecx\npush r13\nmov r13, rdi\npush r12\nlea edi, [r14+rdx]\npush rbp\nmovsxd rdi, edi\nmov ebp, esi\npush rbx\nshl rdi, 2; size\nmov ebx, edx\ncall _malloc\nmov r12, rax\ntest ebx, ebx\njle short loc_1508\nsub ebp, ebx\nmov edx, ebx\nmov rdi, rax; dest\nmovsxd rbp, ebp\nshl rdx, 2; n\nlea rsi, [r13+rbp*4+0]; src\ncall _memcpy\nloc_1508:\ntest r14d, r14d\njle short loc_1523\nmovsxd rbx, ebx\nmov edx, r14d\nmov rsi, r13; src\nlea rdi, [r12+rbx*4]; dest\nshl rdx, 2; n\ncall _memcpy\nloc_1523:\npop rbx\nmov rax, r12\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "char *__fastcall func0(char *src, int a2, int a3, int a4)\n{\n int v4; // r14d\n char *v6; // rax\n char *v7; // r12\n\n v4 = a2 - a4;\n v6 = (char *)malloc(4LL * (a2 - a4 + a3));\n v7 = v6;\n if ( a3 > 0 )\n memcpy(v6, &src[4 * (a2 - a3)], 4LL * (unsigned int)a3);\n if ( v4 > 0 )\n memcpy(&v7[4 * a3], src, 4LL * (unsigned int)v4);\n return v7;\n}", + "ida_strip_asm": "sub_14C0:\nendbr64\npush r14\nmov r14d, esi\nsub r14d, ecx\npush r13\nmov r13, rdi\npush r12\nlea edi, [r14+rdx]\npush rbp\nmovsxd rdi, edi\nmov ebp, esi\npush rbx\nshl rdi, 2; size\nmov ebx, edx\ncall _malloc\nmov r12, rax\ntest ebx, ebx\njle short loc_1508\nsub ebp, ebx\nmov edx, ebx\nmov rdi, rax; dest\nmovsxd rbp, ebp\nshl rdx, 2; n\nlea rsi, [r13+rbp*4+0]; src\ncall _memcpy\nloc_1508:\ntest r14d, r14d\njle short loc_1523\nmovsxd rbx, ebx\nmov edx, r14d\nmov rsi, r13; src\nlea rdi, [r12+rbx*4]; dest\nshl rdx, 2; n\ncall _memcpy\nloc_1523:\npop rbx\nmov rax, r12\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "char *__fastcall sub_14C0(char *src, int a2, int a3, int a4)\n{\n int v4; // r14d\n char *v6; // rax\n char *v7; // r12\n\n v4 = a2 - a4;\n v6 = (char *)malloc(4LL * (a2 - a4 + a3));\n v7 = v6;\n if ( a3 > 0 )\n memcpy(v6, &src[4 * (a2 - a3)], 4LL * (unsigned int)a3);\n if ( v4 > 0 )\n memcpy(&v7[4 * a3], src, 4LL * (unsigned int)v4);\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_14C0(char *src, int a2, int a3, int a4) {\n int v4;\n char *v6;\n char *v7;\n v4 = a2 - a4;\n v6 = (char *)malloc(4LL * (a2 - a4 + a3));\n v7 = v6;\n if (a3 > 0) memcpy(v6, &src[4 * (a2 - a3)], 4LL * (unsigned int)a3);\n if (v4 > 0) memcpy(&v7[4 * a3], src, 4LL * (unsigned int)v4);\n return v7;\n}", + "ida_pseudo_norm": "char *func0(char *src, int a2, int a3, int a4) {\n int v4;\n char *v6;\n char *v7;\n v4 = a2 - a4;\n v6 = (char *)malloc(4LL * (a2 - a4 + a3));\n v7 = v6;\n if (a3 > 0) memcpy(v6, &src[4 * (a2 - a3)], 4LL * (unsigned int)a3);\n if (v4 > 0) memcpy(&v7[4 * a3], src, 4LL * (unsigned int)v4);\n return v7;\n}" + }, + { + "index": 743, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int list1[], int size, int m, int n) {\n int new_size = m + (size - n);\n int* result = (int*)malloc(new_size * sizeof(int));\n for (int i = 0; i < m; i++) {\n result[i] = list1[size - m + i];\n }\n for (int i = 0; i < (size - n); i++) {\n result[m + i] = list1[i];\n }\n return result;\n}", + "test": "int main() {\n\n int list1a[] = {1,2,3,4,5,6,7,8,9,10};\n\n int expected1[] = {8,9,10,1,2,3,4,5,6};\n\n int* result1 = func0(list1a, 10, 3, 4);\n\n assert(memcmp(result1, expected1, 9 * sizeof(int)) == 0);\n\n free(result1);\n\n \n\n int list1b[] = {1,2,3,4,5,6,7,8,9,10};\n\n int expected2[] = {9,10,1,2,3,4,5,6,7,8};\n\n int* result2 = func0(list1b, 10, 2, 2);\n\n assert(memcmp(result2, expected2, 10 * sizeof(int)) == 0);\n\n free(result2);\n\n \n\n int list1c[] = {1,2,3,4,5,6,7,8,9,10};\n\n int expected3[] = {6,7,8,9,10,1,2,3,4,5,6,7,8};\n\n int* result3 = func0(list1c, 10, 5, 2);\n\n assert(memcmp(result3, expected3, 13 * sizeof(int)) == 0);\n\n free(result3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\nmov %esi,%r13d\npush %r12\nsub %ecx,%r13d\nmov %rdi,%r12\npush %rbp\nmov %esi,%ebp\npush %rbx\nmovslq %edx,%rbx\nlea 0x0(%r13,%rbx,1),%edi\nmovslq %edi,%rdi\nshl $0x2,%rdi\ncallq 10d0 \nmov %rax,%r14\ntest %ebx,%ebx\njle 151e \nsub %ebx,%ebp\nlea -0x1(%rbx),%eax\nmov %r14,%rdi\nmovslq %ebp,%rbp\nlea 0x4(,%rax,4),%rdx\nlea (%r12,%rbp,4),%rsi\ncallq 10c0 \ntest %r13d,%r13d\njle 153b \nlea -0x1(%r13),%eax\nlea (%r14,%rbx,4),%rdi\nmov %r12,%rsi\nlea 0x4(,%rax,4),%rdx\ncallq 10c0 \npop %rbx\nmov %r14,%rax\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\nmov r14d, esi\nsub r14d, ecx\npush r13\nmov r13, rdi\npush r12\nlea edi, [r14+rdx]\npush rbp\nmovsxd rdi, edi\nmov ebp, esi\npush rbx\nshl rdi, 2; size\nmov ebx, edx\ncall _malloc\nmov r12, rax\ntest ebx, ebx\njle short loc_1508\nsub ebp, ebx\nmov edx, ebx\nmov rdi, rax; dest\nmovsxd rbp, ebp\nshl rdx, 2; n\nlea rsi, [r13+rbp*4+0]; src\ncall _memcpy\nloc_1508:\ntest r14d, r14d\njle short loc_1523\nmovsxd rbx, ebx\nmov edx, r14d\nmov rsi, r13; src\nlea rdi, [r12+rbx*4]; dest\nshl rdx, 2; n\ncall _memcpy\nloc_1523:\npop rbx\nmov rax, r12\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "char *__fastcall func0(char *src, int a2, int a3, int a4)\n{\n int v4; // r14d\n char *v6; // rax\n char *v7; // r12\n\n v4 = a2 - a4;\n v6 = (char *)malloc(4LL * (a2 - a4 + a3));\n v7 = v6;\n if ( a3 > 0 )\n memcpy(v6, &src[4 * (a2 - a3)], 4LL * (unsigned int)a3);\n if ( v4 > 0 )\n memcpy(&v7[4 * a3], src, 4LL * (unsigned int)v4);\n return v7;\n}", + "ida_strip_asm": "sub_14C0:\nendbr64\npush r14\nmov r14d, esi\nsub r14d, ecx\npush r13\nmov r13, rdi\npush r12\nlea edi, [r14+rdx]\npush rbp\nmovsxd rdi, edi\nmov ebp, esi\npush rbx\nshl rdi, 2; size\nmov ebx, edx\ncall _malloc\nmov r12, rax\ntest ebx, ebx\njle short loc_1508\nsub ebp, ebx\nmov edx, ebx\nmov rdi, rax; dest\nmovsxd rbp, ebp\nshl rdx, 2; n\nlea rsi, [r13+rbp*4+0]; src\ncall _memcpy\nloc_1508:\ntest r14d, r14d\njle short loc_1523\nmovsxd rbx, ebx\nmov edx, r14d\nmov rsi, r13; src\nlea rdi, [r12+rbx*4]; dest\nshl rdx, 2; n\ncall _memcpy\nloc_1523:\npop rbx\nmov rax, r12\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "char *__fastcall sub_14C0(char *src, int a2, int a3, int a4)\n{\n int v4; // r14d\n char *v6; // rax\n char *v7; // r12\n\n v4 = a2 - a4;\n v6 = (char *)malloc(4LL * (a2 - a4 + a3));\n v7 = v6;\n if ( a3 > 0 )\n memcpy(v6, &src[4 * (a2 - a3)], 4LL * (unsigned int)a3);\n if ( v4 > 0 )\n memcpy(&v7[4 * a3], src, 4LL * (unsigned int)v4);\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_14C0(char *src, int a2, int a3, int a4) {\n int v4;\n char *v6;\n char *v7;\n v4 = a2 - a4;\n v6 = (char *)malloc(4LL * (a2 - a4 + a3));\n v7 = v6;\n if (a3 > 0) memcpy(v6, &src[4 * (a2 - a3)], 4LL * (unsigned int)a3);\n if (v4 > 0) memcpy(&v7[4 * a3], src, 4LL * (unsigned int)v4);\n return v7;\n}", + "ida_pseudo_norm": "char *func0(char *src, int a2, int a3, int a4) {\n int v4;\n char *v6;\n char *v7;\n v4 = a2 - a4;\n v6 = (char *)malloc(4LL * (a2 - a4 + a3));\n v7 = v6;\n if (a3 > 0) memcpy(v6, &src[4 * (a2 - a3)], 4LL * (unsigned int)a3);\n if (v4 > 0) memcpy(&v7[4 * a3], src, 4LL * (unsigned int)v4);\n return v7;\n}" + }, + { + "index": 744, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int *test_tup, int size) {\n for (int i = 0; i < size; i++) {\n if (test_tup[i] == 0) {\n return true;\n }\n }\n return false;\n}", + "test": "int main() {\n\n int arr1[] = {10, 4, 5, 6, 0}; // 0 is used to represent None\n\n int arr2[] = {7, 8, 9, 11, 14};\n\n int arr3[] = {1, 2, 3, 4, 0}; // 0 is used to represent None\n\n\n\n assert(func0(arr1, 5) == true);\n\n assert(func0(arr2, 5) == false);\n\n assert(func0(arr3, 5) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11a6 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ntest %eax,%eax\njne 11a2 \nmov $0x1,%eax\njmp 11b3 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1181 \nmov $0x0,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 0\njmp short loc_11A6\nloc_1181:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njnz short loc_11A2\nmov eax, 1\njmp short loc_11B3\nloc_11A2:\nadd [rbp+var_4], 1\nloc_11A6:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1181\nmov eax, 0\nloc_11B3:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n if ( !*(_DWORD *)(4LL * i + a1) )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 0\njmp short loc_11A6\nloc_1181:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njnz short loc_11A2\nmov eax, 1\njmp short loc_11B3\nloc_11A2:\nadd [rbp+var_4], 1\nloc_11A6:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1181\nmov eax, 0\nloc_11B3:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n if ( !*(_DWORD *)(4LL * i + a1) )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int i;\n for (i = 0; i < a2; ++i) {\n if (!*(uint32_t *)(4LL * i + a1)) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int i;\n for (i = 0; i < a2; ++i) {\n if (!*(uint32_t *)(4LL * i + a1)) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 744, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int *test_tup, int size) {\n for (int i = 0; i < size; i++) {\n if (test_tup[i] == 0) {\n return true;\n }\n }\n return false;\n}", + "test": "int main() {\n\n int arr1[] = {10, 4, 5, 6, 0}; // 0 is used to represent None\n\n int arr2[] = {7, 8, 9, 11, 14};\n\n int arr3[] = {1, 2, 3, 4, 0}; // 0 is used to represent None\n\n\n\n assert(func0(arr1, 5) == true);\n\n assert(func0(arr2, 5) == false);\n\n assert(func0(arr3, 5) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1190 \nmov %rdi,%rax\nlea -0x1(%rsi),%edx\nlea 0x4(%rdi,%rdx,4),%rdx\ncmpl $0x0,(%rax)\nje 1196 \nadd $0x4,%rax\ncmp %rdx,%rax\njne 117c \nmov $0x0,%eax\nretq\nmov $0x0,%eax\nretq\nmov $0x1,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_118F\nmov rax, rdi\nmovsxd rsi, esi\nlea rdx, [rdi+rsi*4]\nloc_117B:\ncmp dword ptr [rax], 0\njz short loc_1195\nadd rax, 4\ncmp rax, rdx\njnz short loc_117B\nmov eax, 0\nretn\nloc_118F:\nmov eax, 0\nretn\nloc_1195:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = a1;\n while ( *v2 )\n {\n if ( ++v2 == &a1[a2] )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_118F\nmov rax, rdi\nmovsxd rsi, esi\nlea rdx, [rdi+rsi*4]\nloc_117B:\ncmp dword ptr [rax], 0\njz short loc_1195\nadd rax, 4\ncmp rax, rdx\njnz short loc_117B\nmov eax, 0\nretn\nloc_118F:\nmov eax, 0\nretn\nloc_1195:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = a1;\n while ( *v2 )\n {\n if ( ++v2 == &a1[a2] )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2) {\n uint32_t *v2;\n if (a2 <= 0) return 0LL;\n v2 = a1;\n while (*v2) {\n if (++v2 == &a1[a2]) return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n if (a2 <= 0) return 0LL;\n v2 = a1;\n while (*v2) {\n if (++v2 == &a1[a2]) return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": 745, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int startnum, int endnum, int result[], int *result_size) {\n *result_size = 0;\n for (int n = startnum; n <= endnum; ++n) {\n bool divisible = true;\n int temp = n;\n while (temp > 0) {\n int digit = temp % 10;\n if (digit == 0 || n % digit != 0) {\n divisible = false;\n break;\n }\n temp /= 10;\n }\n if (divisible) {\n result[*result_size] = n;\n (*result_size)++;\n }\n }\n}", + "test": "int main() {\n\n int result[100];\n\n int result_size;\n\n\n\n func0(1, 22, result, &result_size);\n\n int expected1[13] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 15, 22};\n\n assert(result_size == 13);\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected1[i]);\n\n }\n\n\n\n func0(1, 15, result, &result_size);\n\n int expected2[12] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 15};\n\n assert(result_size == 12);\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected2[i]);\n\n }\n\n\n\n func0(20, 25, result, &result_size);\n\n int expected3[2] = {22, 24};\n\n assert(result_size == 2);\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov %rdx,-0x20(%rbp)\nmov %rcx,-0x28(%rbp)\nmov -0x28(%rbp),%rax\nmovl $0x0,(%rax)\nmov -0x14(%rbp),%eax\nmov %eax,-0xc(%rbp)\njmpq 123f \nmovb $0x1,-0xd(%rbp)\nmov -0xc(%rbp),%eax\nmov %eax,-0x8(%rbp)\njmp 1204 \nmov -0x8(%rbp),%edx\nmovslq %edx,%rax\nimul $0x66666667,%rax,%rax\nshr $0x20,%rax\nmov %eax,%ecx\nsar $0x2,%ecx\nmov %edx,%eax\nsar $0x1f,%eax\nsub %eax,%ecx\nmov %ecx,%eax\nshl $0x2,%eax\nadd %ecx,%eax\nadd %eax,%eax\nsub %eax,%edx\nmov %edx,%eax\nmov %eax,-0x4(%rbp)\ncmpl $0x0,-0x4(%rbp)\nje 11e0 \nmov -0xc(%rbp),%eax\ncltd\nidivl -0x4(%rbp)\nmov %edx,%eax\ntest %eax,%eax\nje 11e6 \nmovb $0x0,-0xd(%rbp)\njmp 120a \nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nimul $0x66666667,%rdx,%rdx\nshr $0x20,%rdx\nsar $0x2,%edx\nsar $0x1f,%eax\nsub %eax,%edx\nmov %edx,%eax\nmov %eax,-0x8(%rbp)\ncmpl $0x0,-0x8(%rbp)\njg 11a0 \ncmpb $0x0,-0xd(%rbp)\nje 123b \nmov -0x28(%rbp),%rax\nmov (%rax),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x20(%rbp),%rax\nadd %rax,%rdx\nmov -0xc(%rbp),%eax\nmov %eax,(%rdx)\nmov -0x28(%rbp),%rax\nmov (%rax),%eax\nlea 0x1(%rax),%edx\nmov -0x28(%rbp),%rax\nmov %edx,(%rax)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x18(%rbp),%eax\njle 1194 \npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_20], rdx\nmov [rbp+var_28], rcx\nmov rax, [rbp+var_28]\nmov dword ptr [rax], 0\nmov eax, [rbp+var_14]\nmov [rbp+var_C], eax\njmp loc_123D\nloc_1194:\nmov [rbp+var_D], 1\nmov eax, [rbp+var_C]\nmov [rbp+var_8], eax\njmp short loc_1202\nloc_11A0:\nmov edx, [rbp+var_8]\nmovsxd rax, edx\nimul rax, 66666667h\nshr rax, 20h\nmov ecx, eax\nsar ecx, 2\nmov eax, edx\nsar eax, 1Fh\nsub ecx, eax\nmov eax, ecx\nshl eax, 2\nadd eax, ecx\nadd eax, eax\nsub edx, eax\nmov [rbp+var_4], edx\ncmp [rbp+var_4], 0\njz short loc_11DE\nmov eax, [rbp+var_C]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njz short loc_11E4\nloc_11DE:\nmov [rbp+var_D], 0\njmp short loc_1208\nloc_11E4:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_8], eax\nloc_1202:\ncmp [rbp+var_8], 0\njg short loc_11A0\nloc_1208:\ncmp [rbp+var_D], 0\njz short loc_1239\nmov rax, [rbp+var_28]\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rdx, rax\nmov eax, [rbp+var_C]\nmov [rdx], eax\nmov rax, [rbp+var_28]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_28]\nmov [rax], edx\nloc_1239:\nadd [rbp+var_C], 1\nloc_123D:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_18]\njle loc_1194\nnop\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, __int64 a3, _DWORD *a4)\n{\n __int64 result; // rax\n char v5; // [rsp+1Bh] [rbp-Dh]\n int i; // [rsp+20h] [rbp-8h]\n\n *a4 = 0;\n while ( 1 )\n {\n result = (unsigned int)a1;\n if ( a1 > a2 )\n return result;\n v5 = 1;\n for ( i = a1; i > 0; i /= 10 )\n {\n if ( !(i % 10) || a1 % (i % 10) )\n {\n v5 = 0;\n break;\n }\n }\n if ( v5 )\n *(_DWORD *)(a3 + 4LL * (int)(*a4)++) = a1;\n ++a1;\n }\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_20], rdx\nmov [rbp+var_28], rcx\nmov rax, [rbp+var_28]\nmov dword ptr [rax], 0\nmov eax, [rbp+var_14]\nmov [rbp+var_C], eax\njmp loc_123D\nloc_1194:\nmov [rbp+var_D], 1\nmov eax, [rbp+var_C]\nmov [rbp+var_8], eax\njmp short loc_1202\nloc_11A0:\nmov edx, [rbp+var_8]\nmovsxd rax, edx\nimul rax, 66666667h\nshr rax, 20h\nmov ecx, eax\nsar ecx, 2\nmov eax, edx\nsar eax, 1Fh\nsub ecx, eax\nmov eax, ecx\nshl eax, 2\nadd eax, ecx\nadd eax, eax\nsub edx, eax\nmov [rbp+var_4], edx\ncmp [rbp+var_4], 0\njz short loc_11DE\nmov eax, [rbp+var_C]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njz short loc_11E4\nloc_11DE:\nmov [rbp+var_D], 0\njmp short loc_1208\nloc_11E4:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_8], eax\nloc_1202:\ncmp [rbp+var_8], 0\njg short loc_11A0\nloc_1208:\ncmp [rbp+var_D], 0\njz short loc_1239\nmov rax, [rbp+var_28]\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rdx, rax\nmov eax, [rbp+var_C]\nmov [rdx], eax\nmov rax, [rbp+var_28]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_28]\nmov [rax], edx\nloc_1239:\nadd [rbp+var_C], 1\nloc_123D:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_18]\njle loc_1194\nnop\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1, int a2, __int64 a3, _DWORD *a4)\n{\n __int64 result; // rax\n char v5; // [rsp+1Bh] [rbp-Dh]\n int i; // [rsp+20h] [rbp-8h]\n\n *a4 = 0;\n while ( 1 )\n {\n result = (unsigned int)a1;\n if ( a1 > a2 )\n return result;\n v5 = 1;\n for ( i = a1; i > 0; i /= 10 )\n {\n if ( !(i % 10) || a1 % (i % 10) )\n {\n v5 = 0;\n break;\n }\n }\n if ( v5 )\n *(_DWORD *)(a3 + 4LL * (int)(*a4)++) = a1;\n ++a1;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1, int a2, long long a3, uint32_t *a4) {\n long long result;\n char v5;\n int i;\n *a4 = 0;\n while (1) {\n result = (unsigned int)a1;\n if (a1 > a2) return result;\n v5 = 1;\n for (i = a1; i > 0; i /= 10) {\n if (!(i % 10) || a1 % (i % 10)) {\n v5 = 0;\n break;\n }\n }\n if (v5) *(uint32_t *)(a3 + 4LL * (int)(*a4)++) = a1;\n ++a1;\n }\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, long long a3, uint32_t *a4) {\n long long result;\n char v5;\n int i;\n *a4 = 0;\n while (1) {\n result = (unsigned int)a1;\n if (a1 > a2) return result;\n v5 = 1;\n for (i = a1; i > 0; i /= 10) {\n if (!(i % 10) || a1 % (i % 10)) {\n v5 = 0;\n break;\n }\n }\n if (v5) *(uint32_t *)(a3 + 4LL * (int)(*a4)++) = a1;\n ++a1;\n }\n}" + }, + { + "index": 745, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int startnum, int endnum, int result[], int *result_size) {\n *result_size = 0;\n for (int n = startnum; n <= endnum; ++n) {\n bool divisible = true;\n int temp = n;\n while (temp > 0) {\n int digit = temp % 10;\n if (digit == 0 || n % digit != 0) {\n divisible = false;\n break;\n }\n temp /= 10;\n }\n if (divisible) {\n result[*result_size] = n;\n (*result_size)++;\n }\n }\n}", + "test": "int main() {\n\n int result[100];\n\n int result_size;\n\n\n\n func0(1, 22, result, &result_size);\n\n int expected1[13] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 15, 22};\n\n assert(result_size == 13);\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected1[i]);\n\n }\n\n\n\n func0(1, 15, result, &result_size);\n\n int expected2[12] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 15};\n\n assert(result_size == 12);\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected2[i]);\n\n }\n\n\n\n func0(20, 25, result, &result_size);\n\n int expected3[2] = {22, 24};\n\n assert(result_size == 2);\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdx,%r9\nmovl $0x0,(%rcx)\ncmp %esi,%edi\njg 120d \nlea 0x1(%rsi),%r10d\njmp 1196 \nmovslq (%rcx),%rax\nmov %edi,(%r9,%rax,4)\naddl $0x1,(%rcx)\nadd $0x1,%edi\ncmp %edi,%r10d\nje 120d \ntest %edi,%edi\njle 1184 \nmovslq %edi,%rsi\nimul $0x66666667,%rsi,%rsi\nsar $0x22,%rsi\nmov %edi,%eax\nsar $0x1f,%eax\nsub %eax,%esi\nlea (%rsi,%rsi,4),%eax\nadd %eax,%eax\nmov %edi,%esi\nsub %eax,%esi\nje 118e \nmov %edi,%eax\ncltd\nidiv %esi\ntest %edx,%edx\njne 118e \nmov %edi,%r8d\nmov %r8d,%edx\nmovslq %r8d,%rax\nimul $0x66666667,%rax,%rax\nsar $0x22,%rax\nsar $0x1f,%r8d\nsub %r8d,%eax\nmov %eax,%r8d\ncmp $0x9,%edx\njle 1184 \nmovslq %eax,%rsi\nimul $0x66666667,%rsi,%rsi\nsar $0x22,%rsi\ncltd\nsub %edx,%esi\nlea (%rsi,%rsi,4),%edx\nadd %edx,%edx\nsub %edx,%eax\nmov %eax,%esi\nje 118e \nmov %edi,%eax\ncltd\nidiv %esi\ntest %edx,%edx\nje 11c6 \njmp 118e \nretq\n", + "ida_asm": "func0:\nendbr64\nmov r9, rdx\nmov r8, rcx\nmov dword ptr [rcx], 0\ncmp edi, esi\njg locret_1210\nlea r10d, [rsi+1]\njmp short loc_119A\nloc_1187:\nmovsxd rax, dword ptr [r8]\nmov [r9+rax*4], edi\nadd dword ptr [r8], 1\nloc_1192:\nadd edi, 1\ncmp r10d, edi\njz short locret_1210\nloc_119A:\ntest edi, edi\njle short loc_1187\nmovsxd rcx, edi\nimul rcx, 66666667h\nsar rcx, 22h\nmov eax, edi\nsar eax, 1Fh\nsub ecx, eax\nlea eax, [rcx+rcx*4]\nadd eax, eax\nmov ecx, edi\nsub ecx, eax\njz short loc_1192\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_1192\nmov esi, edi\nloc_11C9:\nmov eax, esi\nmovsxd rdx, esi\nimul rdx, 66666667h\nsar rdx, 22h\nsar esi, 1Fh\nsub edx, esi\nmov esi, edx\ncmp eax, 9\njle short loc_1187\nmovsxd rcx, edx\nimul rcx, 66666667h\nsar rcx, 22h\nmov eax, edx\nsar eax, 1Fh\nsub ecx, eax\nlea eax, [rcx+rcx*4]\nadd eax, eax\nmov ecx, edx\nsub ecx, eax\njz short loc_1192\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njz short loc_11C9\njmp short loc_1192\nlocret_1210:\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, __int64 a3, int *a4)\n{\n int v6; // r10d\n __int64 result; // rax\n int v8; // ecx\n int v9; // esi\n int v10; // eax\n int v11; // edx\n int v12; // ecx\n\n *a4 = 0;\n if ( a1 <= a2 )\n {\n v6 = a2 + 1;\n do\n {\n if ( a1 > 0 )\n {\n result = (unsigned int)(10 * (a1 / 10));\n v8 = a1 % 10;\n if ( !(a1 % 10) )\n goto LABEL_4;\n result = (unsigned int)(a1 / v8);\n if ( a1 % v8 )\n goto LABEL_4;\n v9 = a1;\n while ( 1 )\n {\n v10 = v9;\n v11 = v9 / 10;\n v9 /= 10;\n if ( v10 <= 9 )\n break;\n result = (unsigned int)(10 * (v11 / 10));\n v12 = v11 % 10;\n if ( v11 % 10 )\n {\n result = (unsigned int)(a1 / v12);\n if ( !(a1 % v12) )\n continue;\n }\n goto LABEL_4;\n }\n }\n result = *a4;\n *(_DWORD *)(a3 + 4 * result) = a1;\n ++*a4;\nLABEL_4:\n ++a1;\n }\n while ( v6 != a1 );\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov r9, rdx\nmov r8, rcx\nmov dword ptr [rcx], 0\ncmp edi, esi\njg locret_1210\nlea r10d, [rsi+1]\njmp short loc_119A\nloc_1187:\nmovsxd rax, dword ptr [r8]\nmov [r9+rax*4], edi\nadd dword ptr [r8], 1\nloc_1192:\nadd edi, 1\ncmp r10d, edi\njz short locret_1210\nloc_119A:\ntest edi, edi\njle short loc_1187\nmovsxd rcx, edi\nimul rcx, 66666667h\nsar rcx, 22h\nmov eax, edi\nsar eax, 1Fh\nsub ecx, eax\nlea eax, [rcx+rcx*4]\nadd eax, eax\nmov ecx, edi\nsub ecx, eax\njz short loc_1192\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_1192\nmov esi, edi\nloc_11C9:\nmov eax, esi\nmovsxd rdx, esi\nimul rdx, 66666667h\nsar rdx, 22h\nsar esi, 1Fh\nsub edx, esi\nmov esi, edx\ncmp eax, 9\njle short loc_1187\nmovsxd rcx, edx\nimul rcx, 66666667h\nsar rcx, 22h\nmov eax, edx\nsar eax, 1Fh\nsub ecx, eax\nlea eax, [rcx+rcx*4]\nadd eax, eax\nmov ecx, edx\nsub ecx, eax\njz short loc_1192\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njz short loc_11C9\njmp short loc_1192\nlocret_1210:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1, int a2, __int64 a3, int *a4)\n{\n int v6; // r10d\n __int64 result; // rax\n int v8; // ecx\n int v9; // esi\n int v10; // eax\n int v11; // edx\n int v12; // ecx\n\n *a4 = 0;\n if ( a1 <= a2 )\n {\n v6 = a2 + 1;\n do\n {\n if ( a1 > 0 )\n {\n result = (unsigned int)(10 * (a1 / 10));\n v8 = a1 % 10;\n if ( !(a1 % 10) )\n goto LABEL_4;\n result = (unsigned int)(a1 / v8);\n if ( a1 % v8 )\n goto LABEL_4;\n v9 = a1;\n while ( 1 )\n {\n v10 = v9;\n v11 = v9 / 10;\n v9 /= 10;\n if ( v10 <= 9 )\n break;\n result = (unsigned int)(10 * (v11 / 10));\n v12 = v11 % 10;\n if ( v11 % 10 )\n {\n result = (unsigned int)(a1 / v12);\n if ( !(a1 % v12) )\n continue;\n }\n goto LABEL_4;\n }\n }\n result = *a4;\n *(_DWORD *)(a3 + 4 * result) = a1;\n ++*a4;\nLABEL_4:\n ++a1;\n }\n while ( v6 != a1 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1, int a2, long long a3, int *a4) {\n int v6;\n long long result;\n int v8;\n int v9;\n int v10;\n int v11;\n int v12;\n *a4 = 0;\n if (a1 <= a2) {\n v6 = a2 + 1;\n do {\n if (a1 > 0) {\n result = (unsigned int)(10 * (a1 / 10));\n v8 = a1 % 10;\n if (!(a1 % 10)) goto LABEL_4;\n result = (unsigned int)(a1 / v8);\n if (a1 % v8) goto LABEL_4;\n v9 = a1;\n while (1) {\n v10 = v9;\n v11 = v9 / 10;\n v9 /= 10;\n if (v10 <= 9) break;\n result = (unsigned int)(10 * (v11 / 10));\n v12 = v11 % 10;\n if (v11 % 10) {\n result = (unsigned int)(a1 / v12);\n if (!(a1 % v12)) continue;\n }\n goto LABEL_4;\n }\n }\n result = *a4;\n *(uint32_t *)(a3 + 4 * result) = a1;\n ++*a4;\n LABEL_4:\n ++a1;\n } while (v6 != a1);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, long long a3, int *a4) {\n int v6;\n long long result;\n int v8;\n int v9;\n int v10;\n int v11;\n int v12;\n *a4 = 0;\n if (a1 <= a2) {\n v6 = a2 + 1;\n do {\n if (a1 > 0) {\n result = (unsigned int)(10 * (a1 / 10));\n v8 = a1 % 10;\n if (!(a1 % 10)) goto LABEL_4;\n result = (unsigned int)(a1 / v8);\n if (a1 % v8) goto LABEL_4;\n v9 = a1;\n while (1) {\n v10 = v9;\n v11 = v9 / 10;\n v9 /= 10;\n if (v10 <= 9) break;\n result = (unsigned int)(10 * (v11 / 10));\n v12 = v11 % 10;\n if (v11 % 10) {\n result = (unsigned int)(a1 / v12);\n if (!(a1 % v12)) continue;\n }\n goto LABEL_4;\n }\n }\n result = *a4;\n *(uint32_t *)(a3 + 4 * result) = a1;\n ++*a4;\n LABEL_4:\n ++a1;\n } while (v6 != a1);\n }\n return result;\n}" + }, + { + "index": 745, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int startnum, int endnum, int result[], int *result_size) {\n *result_size = 0;\n for (int n = startnum; n <= endnum; ++n) {\n bool divisible = true;\n int temp = n;\n while (temp > 0) {\n int digit = temp % 10;\n if (digit == 0 || n % digit != 0) {\n divisible = false;\n break;\n }\n temp /= 10;\n }\n if (divisible) {\n result[*result_size] = n;\n (*result_size)++;\n }\n }\n}", + "test": "int main() {\n\n int result[100];\n\n int result_size;\n\n\n\n func0(1, 22, result, &result_size);\n\n int expected1[13] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 15, 22};\n\n assert(result_size == 13);\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected1[i]);\n\n }\n\n\n\n func0(1, 15, result, &result_size);\n\n int expected2[12] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 15};\n\n assert(result_size == 12);\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected2[i]);\n\n }\n\n\n\n func0(20, 25, result, &result_size);\n\n int expected3[2] = {22, 24};\n\n assert(result_size == 2);\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmovl $0x0,(%rcx)\nmov %rdx,%r10\ncmp %esi,%edi\njg 147d \nlea 0x1(%rsi),%r11d\nmov $0xcccccccd,%r9d\ntest %edi,%edi\njle 146b \nmovslq %edi,%rsi\nmov %edi,%eax\nimul $0x66666667,%rsi,%rsi\nsar $0x1f,%eax\nsar $0x22,%rsi\nsub %eax,%esi\nlea (%rsi,%rsi,4),%eax\nmov %edi,%esi\nadd %eax,%eax\nsub %eax,%esi\nje 1475 \nmov %edi,%eax\ncltd\nidiv %esi\ntest %edx,%edx\njne 1475 \nmov %edi,%r8d\njmp 1458 \nnopw 0x0(%rax,%rax,1)\nmov %r8d,%esi\nimul %r9,%rsi\nshr $0x23,%rsi\nlea (%rsi,%rsi,4),%eax\nmov %r8d,%esi\nadd %eax,%eax\nsub %eax,%esi\nje 1475 \nmov %edi,%eax\ncltd\nidiv %esi\ntest %edx,%edx\njne 1475 \nmov %r8d,%r8d\nmov %r8,%rax\nimul %r9,%r8\nshr $0x23,%r8\ncmp $0x9,%eax\njg 1438 \nmovslq (%rcx),%rax\nmov %edi,(%r10,%rax,4)\naddl $0x1,(%rcx)\nadd $0x1,%edi\ncmp %edi,%r11d\njne 1400 \nretq\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\nmov dword ptr [rcx], 0\nmov r10, rdx\nmov r9, rcx\ncmp edi, esi\njg locret_1423\nlea r11d, [rsi+1]\nmov r8d, 0CCCCCCCDh\nnop word ptr [rax+rax+00h]\nloc_13A8:\ntest edi, edi\njle short loc_1410\nmovsxd rcx, edi\nmov eax, edi\nimul rcx, 66666667h\nsar eax, 1Fh\nsar rcx, 22h\nsub ecx, eax\nlea eax, [rcx+rcx*4]\nmov ecx, edi\nadd eax, eax\nsub ecx, eax\njz short loc_141B\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_141B\nmov esi, edi\njmp short loc_13FE\nloc_13E0:\nmov ecx, esi\nimul rcx, r8\nshr rcx, 23h\nlea edx, [rcx+rcx*4]\nmov ecx, esi\nadd edx, edx\nsub ecx, edx\njz short loc_141B\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_141B\nloc_13FE:\nmov esi, esi\nmov rax, rsi\nimul rsi, r8\nshr rsi, 23h\ncmp eax, 9\njg short loc_13E0\nloc_1410:\nmovsxd rax, dword ptr [r9]\nmov [r10+rax*4], edi\nadd dword ptr [r9], 1\nloc_141B:\nadd edi, 1\ncmp r11d, edi\njnz short loc_13A8\nlocret_1423:\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, __int64 a3, int *a4)\n{\n int v5; // r11d\n __int64 result; // rax\n int v7; // ecx\n unsigned int v8; // esi\n signed int v9; // ecx\n\n *a4 = 0;\n if ( a1 <= a2 )\n {\n v5 = a2 + 1;\n do\n {\n if ( a1 > 0 )\n {\n result = (unsigned int)(10 * (a1 / 10));\n v7 = a1 % 10;\n if ( !(a1 % 10) )\n goto LABEL_11;\n result = (unsigned int)(a1 / v7);\n if ( a1 % v7 )\n goto LABEL_11;\n v8 = a1;\n while ( 1 )\n {\n result = v8;\n v8 /= 0xAu;\n if ( (int)result <= 9 )\n break;\n v9 = v8 % 0xA;\n if ( v8 != 10 * (v8 / 0xA) )\n {\n result = (unsigned int)(a1 / v9);\n if ( !(a1 % v9) )\n continue;\n }\n goto LABEL_11;\n }\n }\n result = *a4;\n *(_DWORD *)(a3 + 4 * result) = a1;\n ++*a4;\nLABEL_11:\n ++a1;\n }\n while ( v5 != a1 );\n }\n return result;\n}", + "ida_strip_asm": "sub_1380:\nendbr64\nmov dword ptr [rcx], 0\nmov r10, rdx\nmov r9, rcx\ncmp edi, esi\njg locret_1423\nlea r11d, [rsi+1]\nmov r8d, 0CCCCCCCDh\nnop word ptr [rax+rax+00h]\nloc_13A8:\ntest edi, edi\njle short loc_1410\nmovsxd rcx, edi\nmov eax, edi\nimul rcx, 66666667h\nsar eax, 1Fh\nsar rcx, 22h\nsub ecx, eax\nlea eax, [rcx+rcx*4]\nmov ecx, edi\nadd eax, eax\nsub ecx, eax\njz short loc_141B\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_141B\nmov esi, edi\njmp short loc_13FE\nloc_13E0:\nmov ecx, esi\nimul rcx, r8\nshr rcx, 23h\nlea edx, [rcx+rcx*4]\nmov ecx, esi\nadd edx, edx\nsub ecx, edx\njz short loc_141B\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_141B\nloc_13FE:\nmov esi, esi\nmov rax, rsi\nimul rsi, r8\nshr rsi, 23h\ncmp eax, 9\njg short loc_13E0\nloc_1410:\nmovsxd rax, dword ptr [r9]\nmov [r10+rax*4], edi\nadd dword ptr [r9], 1\nloc_141B:\nadd edi, 1\ncmp r11d, edi\njnz short loc_13A8\nlocret_1423:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1380(int a1, int a2, __int64 a3, int *a4)\n{\n int v5; // r11d\n __int64 result; // rax\n int v7; // ecx\n unsigned int v8; // esi\n signed int v9; // ecx\n\n *a4 = 0;\n if ( a1 <= a2 )\n {\n v5 = a2 + 1;\n do\n {\n if ( a1 > 0 )\n {\n result = (unsigned int)(10 * (a1 / 10));\n v7 = a1 % 10;\n if ( !(a1 % 10) )\n goto LABEL_11;\n result = (unsigned int)(a1 / v7);\n if ( a1 % v7 )\n goto LABEL_11;\n v8 = a1;\n while ( 1 )\n {\n result = v8;\n v8 /= 0xAu;\n if ( (int)result <= 9 )\n break;\n v9 = v8 % 0xA;\n if ( v8 != 10 * (v8 / 0xA) )\n {\n result = (unsigned int)(a1 / v9);\n if ( !(a1 % v9) )\n continue;\n }\n goto LABEL_11;\n }\n }\n result = *a4;\n *(_DWORD *)(a3 + 4 * result) = a1;\n ++*a4;\nLABEL_11:\n ++a1;\n }\n while ( v5 != a1 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1380(int a1, int a2, long long a3, int *a4) {\n int v5;\n long long result;\n int v7;\n unsigned int v8;\n signed int v9;\n *a4 = 0;\n if (a1 <= a2) {\n v5 = a2 + 1;\n do {\n if (a1 > 0) {\n result = (unsigned int)(10 * (a1 / 10));\n v7 = a1 % 10;\n if (!(a1 % 10)) goto LABEL_11;\n result = (unsigned int)(a1 / v7);\n if (a1 % v7) goto LABEL_11;\n v8 = a1;\n while (1) {\n result = v8;\n v8 /= 10u;\n if ((int)result <= 9) break;\n v9 = v8 % 10;\n if (v8 != 10 * (v8 / 10)) {\n result = (unsigned int)(a1 / v9);\n if (!(a1 % v9)) continue;\n }\n goto LABEL_11;\n }\n }\n result = *a4;\n *(uint32_t *)(a3 + 4 * result) = a1;\n ++*a4;\n LABEL_11:\n ++a1;\n } while (v5 != a1);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, long long a3, int *a4) {\n int v5;\n long long result;\n int v7;\n unsigned int v8;\n signed int v9;\n *a4 = 0;\n if (a1 <= a2) {\n v5 = a2 + 1;\n do {\n if (a1 > 0) {\n result = (unsigned int)(10 * (a1 / 10));\n v7 = a1 % 10;\n if (!(a1 % 10)) goto LABEL_11;\n result = (unsigned int)(a1 / v7);\n if (a1 % v7) goto LABEL_11;\n v8 = a1;\n while (1) {\n result = v8;\n v8 /= 10u;\n if ((int)result <= 9) break;\n v9 = v8 % 10;\n if (v8 != 10 * (v8 / 10)) {\n result = (unsigned int)(a1 / v9);\n if (!(a1 % v9)) continue;\n }\n goto LABEL_11;\n }\n }\n result = *a4;\n *(uint32_t *)(a3 + 4 * result) = a1;\n ++*a4;\n LABEL_11:\n ++a1;\n } while (v5 != a1);\n }\n return result;\n}" + }, + { + "index": 745, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int startnum, int endnum, int result[], int *result_size) {\n *result_size = 0;\n for (int n = startnum; n <= endnum; ++n) {\n bool divisible = true;\n int temp = n;\n while (temp > 0) {\n int digit = temp % 10;\n if (digit == 0 || n % digit != 0) {\n divisible = false;\n break;\n }\n temp /= 10;\n }\n if (divisible) {\n result[*result_size] = n;\n (*result_size)++;\n }\n }\n}", + "test": "int main() {\n\n int result[100];\n\n int result_size;\n\n\n\n func0(1, 22, result, &result_size);\n\n int expected1[13] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 15, 22};\n\n assert(result_size == 13);\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected1[i]);\n\n }\n\n\n\n func0(1, 15, result, &result_size);\n\n int expected2[12] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 15};\n\n assert(result_size == 12);\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected2[i]);\n\n }\n\n\n\n func0(20, 25, result, &result_size);\n\n int expected3[2] = {22, 24};\n\n assert(result_size == 2);\n\n for (int i = 0; i < result_size; i++) {\n\n assert(result[i] == expected3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nmovl $0x0,(%rcx)\nmov %rdx,%r11\ncmp %esi,%edi\njg 15b1 \ntest %edi,%edi\njle 1588 \nmov $0xcccccccd,%r10d\nnopl 0x0(%rax,%rax,1)\nmovslq %edi,%r8\nmov %edi,%eax\nimul $0x66666667,%r8,%r8\nsar $0x1f,%eax\nsar $0x22,%r8\nsub %eax,%r8d\nlea (%r8,%r8,4),%eax\nmov %edi,%r8d\nadd %eax,%eax\nsub %eax,%r8d\nje 1577 \nmov %edi,%eax\ncltd\nidiv %r8d\ntest %edx,%edx\njne 1577 \nmov %edi,%r8d\njmp 1553 \nnopl 0x0(%rax,%rax,1)\nmov %r8d,%r9d\nimul %r10,%r9\nshr $0x23,%r9\nlea (%r9,%r9,4),%eax\nmov %r8d,%r9d\nadd %eax,%eax\nsub %eax,%r9d\nje 1577 \nmov %edi,%eax\ncltd\nidiv %r9d\ntest %edx,%edx\njne 1577 \nmovslq %r8d,%r8\nmov %r8,%rax\nimul $0x66666667,%r8,%r8\ncltd\nsar $0x22,%r8\nsub %edx,%r8d\ncmp $0x9,%eax\njg 1530 \nmovslq (%rcx),%rax\nmov %edi,(%r11,%rax,4)\naddl $0x1,(%rcx)\nadd $0x1,%edi\ncmp %edi,%esi\njge 14f8 \nretq\nnopl 0x0(%rax,%rax,1)\ntest %esi,%esi\nmov $0x0,%edx\ncmovle %esi,%edx\nnopw 0x0(%rax,%rax,1)\nmovslq (%rcx),%rax\nmov %edi,(%r11,%rax,4)\nadd $0x1,%edi\naddl $0x1,(%rcx)\ncmp %edx,%edi\njle 1598 \ncmp %edi,%esi\njge 14ed \nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\nmov dword ptr [rcx], 0\nmov r10d, esi\nmov r9, rdx\ncmp edi, esi\njg locret_14C0\nxor edx, edx\ntest esi, esi\ncmovle edx, esi\ntest edi, edi\njg short loc_1432\nnop dword ptr [rax+rax+00h]\nloc_1418:\nmovsxd rax, dword ptr [rcx]\nmov [r9+rax*4], edi\nadd edi, 1\nadd dword ptr [rcx], 1\ncmp edi, edx\njle short loc_1418\ncmp r10d, edi\njl locret_14C1\nloc_1432:\nmov r11d, 0CCCCCCCDh\nloc_1438:\nmovsxd rsi, edi\nmov eax, edi\nimul rsi, 66666667h\nsar eax, 1Fh\nsar rsi, 22h\nsub esi, eax\nlea eax, [rsi+rsi*4]\nmov esi, edi\nadd eax, eax\nsub esi, eax\njz short loc_14AD\nmov eax, edi\ncdq\nidiv esi\ntest edx, edx\njnz short loc_14AD\nmov r8d, edi\njmp short loc_1490\nloc_1470:\nmov esi, r8d\nimul rsi, r11\nshr rsi, 23h\nlea eax, [rsi+rsi*4]\nmov esi, r8d\nadd eax, eax\nsub esi, eax\njz short loc_14AD\nmov eax, edi\ncdq\nidiv esi\ntest edx, edx\njnz short loc_14AD\nloc_1490:\nmov r8d, r8d\nmov rax, r8\nimul r8, r11\nshr r8, 23h\ncmp eax, 9\njg short loc_1470\nmovsxd rax, dword ptr [rcx]\nmov [r9+rax*4], edi\nadd dword ptr [rcx], 1\nloc_14AD:\nadd edi, 1\ncmp r10d, edi\njge short loc_1438\nretn\nlocret_14C0:\nretn\nlocret_14C1:\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, __int64 a3, int *a4)\n{\n int v6; // edx\n __int64 result; // rax\n int v8; // esi\n unsigned int v9; // r8d\n signed int v10; // esi\n int v11; // eax\n\n *a4 = 0;\n if ( a1 <= a2 )\n {\n v6 = 0;\n if ( a2 <= 0 )\n v6 = a2;\n if ( a1 > 0 )\n goto LABEL_17;\n do\n {\n result = *a4;\n *(_DWORD *)(a3 + 4 * result) = a1++;\n ++*a4;\n }\n while ( a1 <= v6 );\n if ( a2 >= a1 )\n {\nLABEL_17:\n do\n {\n result = (unsigned int)(10 * (a1 / 10));\n v8 = a1 % 10;\n if ( a1 % 10 )\n {\n result = (unsigned int)(a1 / v8);\n if ( !(a1 % v8) )\n {\n v9 = a1;\n while ( 1 )\n {\n v11 = v9;\n v9 /= 0xAu;\n if ( v11 <= 9 )\n break;\n result = 10 * (v9 / 0xA);\n v10 = v9 % 0xA;\n if ( v9 != (_DWORD)result )\n {\n result = (unsigned int)(a1 / v10);\n if ( !(a1 % v10) )\n continue;\n }\n goto LABEL_14;\n }\n result = *a4;\n *(_DWORD *)(a3 + 4 * result) = a1;\n ++*a4;\n }\n }\nLABEL_14:\n ++a1;\n }\n while ( a2 >= a1 );\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_13F0:\nendbr64\nmov dword ptr [rcx], 0\nmov r10d, esi\nmov r9, rdx\ncmp edi, esi\njg locret_14C0\nxor edx, edx\ntest esi, esi\ncmovle edx, esi\ntest edi, edi\njg short loc_1432\nnop dword ptr [rax+rax+00h]\nloc_1418:\nmovsxd rax, dword ptr [rcx]\nmov [r9+rax*4], edi\nadd edi, 1\nadd dword ptr [rcx], 1\ncmp edi, edx\njle short loc_1418\ncmp r10d, edi\njl locret_14C1\nloc_1432:\nmov r11d, 0CCCCCCCDh\nloc_1438:\nmovsxd rsi, edi\nmov eax, edi\nimul rsi, 66666667h\nsar eax, 1Fh\nsar rsi, 22h\nsub esi, eax\nlea eax, [rsi+rsi*4]\nmov esi, edi\nadd eax, eax\nsub esi, eax\njz short loc_14AD\nmov eax, edi\ncdq\nidiv esi\ntest edx, edx\njnz short loc_14AD\nmov r8d, edi\njmp short loc_1490\nloc_1470:\nmov esi, r8d\nimul rsi, r11\nshr rsi, 23h\nlea eax, [rsi+rsi*4]\nmov esi, r8d\nadd eax, eax\nsub esi, eax\njz short loc_14AD\nmov eax, edi\ncdq\nidiv esi\ntest edx, edx\njnz short loc_14AD\nloc_1490:\nmov r8d, r8d\nmov rax, r8\nimul r8, r11\nshr r8, 23h\ncmp eax, 9\njg short loc_1470\nmovsxd rax, dword ptr [rcx]\nmov [r9+rax*4], edi\nadd dword ptr [rcx], 1\nloc_14AD:\nadd edi, 1\ncmp r10d, edi\njge short loc_1438\nretn\nlocret_14C0:\nretn\nlocret_14C1:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_13F0(int a1, int a2, __int64 a3, int *a4)\n{\n int v6; // edx\n __int64 result; // rax\n int v8; // esi\n unsigned int v9; // r8d\n signed int v10; // esi\n int v11; // eax\n\n *a4 = 0;\n if ( a1 <= a2 )\n {\n v6 = 0;\n if ( a2 <= 0 )\n v6 = a2;\n if ( a1 > 0 )\n goto LABEL_17;\n do\n {\n result = *a4;\n *(_DWORD *)(a3 + 4 * result) = a1++;\n ++*a4;\n }\n while ( a1 <= v6 );\n if ( a2 >= a1 )\n {\nLABEL_17:\n do\n {\n result = (unsigned int)(10 * (a1 / 10));\n v8 = a1 % 10;\n if ( a1 % 10 )\n {\n result = (unsigned int)(a1 / v8);\n if ( !(a1 % v8) )\n {\n v9 = a1;\n while ( 1 )\n {\n v11 = v9;\n v9 /= 0xAu;\n if ( v11 <= 9 )\n break;\n result = 10 * (v9 / 0xA);\n v10 = v9 % 0xA;\n if ( v9 != (_DWORD)result )\n {\n result = (unsigned int)(a1 / v10);\n if ( !(a1 % v10) )\n continue;\n }\n goto LABEL_14;\n }\n result = *a4;\n *(_DWORD *)(a3 + 4 * result) = a1;\n ++*a4;\n }\n }\nLABEL_14:\n ++a1;\n }\n while ( a2 >= a1 );\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_13F0(int a1, int a2, long long a3, int *a4) {\n int v6;\n long long result;\n int v8;\n unsigned int v9;\n signed int v10;\n int v11;\n *a4 = 0;\n if (a1 <= a2) {\n v6 = 0;\n if (a2 <= 0) v6 = a2;\n if (a1 > 0) goto LABEL_17;\n do {\n result = *a4;\n *(uint32_t *)(a3 + 4 * result) = a1++;\n ++*a4;\n } while (a1 <= v6);\n if (a2 >= a1) {\n LABEL_17:\n do {\n result = (unsigned int)(10 * (a1 / 10));\n v8 = a1 % 10;\n if (a1 % 10) {\n result = (unsigned int)(a1 / v8);\n if (!(a1 % v8)) {\n v9 = a1;\n while (1) {\n v11 = v9;\n v9 /= 10u;\n if (v11 <= 9) break;\n result = 10 * (v9 / 10);\n v10 = v9 % 10;\n if (v9 != (uint32_t)result) {\n result = (unsigned int)(a1 / v10);\n if (!(a1 % v10)) continue;\n }\n goto LABEL_14;\n }\n result = *a4;\n *(uint32_t *)(a3 + 4 * result) = a1;\n ++*a4;\n }\n }\n LABEL_14:\n ++a1;\n } while (a2 >= a1);\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, long long a3, int *a4) {\n int v6;\n long long result;\n int v8;\n unsigned int v9;\n signed int v10;\n int v11;\n *a4 = 0;\n if (a1 <= a2) {\n v6 = 0;\n if (a2 <= 0) v6 = a2;\n if (a1 > 0) goto LABEL_17;\n do {\n result = *a4;\n *(uint32_t *)(a3 + 4 * result) = a1++;\n ++*a4;\n } while (a1 <= v6);\n if (a2 >= a1) {\n LABEL_17:\n do {\n result = (unsigned int)(10 * (a1 / 10));\n v8 = a1 % 10;\n if (a1 % 10) {\n result = (unsigned int)(a1 / v8);\n if (!(a1 % v8)) {\n v9 = a1;\n while (1) {\n v11 = v9;\n v9 /= 10u;\n if (v11 <= 9) break;\n result = 10 * (v9 / 10);\n v10 = v9 % 10;\n if (v9 != (uint32_t)result) {\n result = (unsigned int)(a1 / v10);\n if (!(a1 % v10)) continue;\n }\n goto LABEL_14;\n }\n result = *a4;\n *(uint32_t *)(a3 + 4 * result) = a1;\n ++*a4;\n }\n }\n LABEL_14:\n ++a1;\n } while (a2 >= a1);\n }\n }\n return result;\n}" + }, + { + "index": 746, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int r, int a) {\n double pi = 22.0 / 7.0;\n if (a >= 360) {\n return -1;\n }\n double sectorarea = (pi * r * r) * (a / 360.0);\n return sectorarea;\n}", + "test": "int main() {\n\n assert(func0(4, 45) == 6.285714285714286);\n\n assert(func0(9, 45) == 31.82142857142857);\n\n assert(func0(9, 360) == -1); // Using -1 to check for None\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmovsd 0xf51(%rip),%xmm0\nmovsd %xmm0,-0x10(%rbp)\ncmpl $0x167,-0x18(%rbp)\njle 1177 \nmovsd 0xf43(%rip),%xmm0\njmp 11ad \ncvtsi2sdl -0x14(%rbp),%xmm0\nmovapd %xmm0,%xmm1\nmulsd -0x10(%rbp),%xmm1\ncvtsi2sdl -0x14(%rbp),%xmm0\nmulsd %xmm0,%xmm1\ncvtsi2sdl -0x18(%rbp),%xmm0\nmovsd 0xf25(%rip),%xmm2\ndivsd %xmm2,%xmm0\nmulsd %xmm1,%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmovsd -0x8(%rbp),%xmm0\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmovsd xmm0, cs:qword_2090\nmovsd [rbp+var_10], xmm0\ncmp [rbp+var_18], 167h\njle short loc_1177\nmovsd xmm0, cs:qword_2098\njmp short loc_11B9\nloc_1177:\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_14]\nmovapd xmm1, xmm0\nmulsd xmm1, [rbp+var_10]\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_14]\nmulsd xmm1, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_18]\nmovsd xmm2, cs:qword_20A0\ndivsd xmm0, xmm2\nmulsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\nloc_11B9:\npop rbp\nretn", + "ida_pseudo": "double __fastcall func0(int a1, int a2)\n{\n if ( a2 <= 359 )\n return (double)a2 / 360.0 * ((double)a1 * 3.142857142857143 * (double)a1);\n else\n return -1.0;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmovsd xmm0, cs:qword_2090\nmovsd [rbp+var_10], xmm0\ncmp [rbp+var_18], 167h\njle short loc_1177\nmovsd xmm0, cs:qword_2098\njmp short loc_11B9\nloc_1177:\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_14]\nmovapd xmm1, xmm0\nmulsd xmm1, [rbp+var_10]\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_14]\nmulsd xmm1, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_18]\nmovsd xmm2, cs:qword_20A0\ndivsd xmm0, xmm2\nmulsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\nloc_11B9:\npop rbp\nretn", + "ida_strip_pseudo": "double __fastcall sub_1149(int a1, int a2)\n{\n if ( a2 <= 359 )\n return (double)a2 / 360.0 * ((double)a1 * 3.142857142857143 * (double)a1);\n else\n return -1.0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1149(int a1, int a2) {\n if (a2 <= 359)\n return (double)a2 / 360.0 * ((double)a1 * 3.142857142857143 * (double)a1);\n else\n return -1.0;\n}", + "ida_pseudo_norm": "double func0(int a1, int a2) {\n if (a2 <= 359)\n return (double)a2 / 360.0 * ((double)a1 * 3.142857142857143 * (double)a1);\n else\n return -1.0;\n}" + }, + { + "index": 747, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char* X, char* Y, char* Z, int m, int n, int o) {\n int L[m + 1][n + 1][o + 1];\n int i, j, k;\n for (i = 0; i <= m; i++) {\n for (j = 0; j <= n; j++) {\n for (k = 0; k <= o; k++) {\n if (i == 0 || j == 0 || k == 0) {\n L[i][j][k] = 0;\n } else if (X[i - 1] == Y[j - 1] && X[i - 1] == Z[k - 1]) {\n L[i][j][k] = L[i - 1][j - 1][k - 1] + 1;\n } else {\n int max1 =\n L[i - 1][j][k] > L[i][j - 1][k] ? L[i - 1][j][k] : L[i][j - 1][k];\n L[i][j][k] = max1 > L[i][j][k - 1] ? max1 : L[i][j][k - 1];\n }\n }\n }\n }\n return L[m][n][o];\n}", + "test": "int main() {\n\n\t// Testing the implementation with assertions\n\n\tassert(func0(\"AGGT12\", \"12TXAYB\", \"12XBA\", 6, 7, 5) == 2);\n\n\tassert(func0(\"Reels\", \"Reelsfor\", \"ReelsforReels\", 5, 8, 13) == 5);\n\n\tassert(func0(\"abcd1e2\", \"bc12ea\", \"bd1ea\", 7, 6, 5) == 3);\n\n\n\n\tprintf(\"All tests passed!\\n\");\n\n\treturn 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0xd8,%rsp\nmov %rdi,-0x78(%rbp)\nmov %rsi,-0x80(%rbp)\nmov %rdx,-0x88(%rbp)\nmov %ecx,-0x8c(%rbp)\nmov %r8d,-0x90(%rbp)\nmov %r9d,-0x94(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nmov %rsp,%rax\nmov %rax,-0xa0(%rbp)\nmov -0x94(%rbp),%eax\nlea 0x1(%rax),%edi\nmov -0x90(%rbp),%eax\nlea 0x1(%rax),%r8d\nmov -0x8c(%rbp),%eax\nlea 0x1(%rax),%r9d\nmovslq %edi,%rax\nsub $0x1,%rax\nmov %rax,-0x58(%rbp)\nmovslq %edi,%rax\nmov %rax,%r10\nmov $0x0,%r11d\nmovslq %edi,%rax\nlea 0x0(,%rax,4),%r11\nmovslq %r8d,%rax\nsub $0x1,%rax\nmov %rax,-0x50(%rbp)\nmovslq %edi,%rax\nmov %rax,%r14\nmov $0x0,%r15d\nmovslq %r8d,%rax\nmov %rax,%r12\nmov $0x0,%r13d\nmov %r15,%rdx\nimul %r12,%rdx\nmov %r13,%rax\nimul %r14,%rax\nlea (%rdx,%rax,1),%rcx\nmov %r14,%rax\nmul %r12\nadd %rdx,%rcx\nmov %rcx,%rdx\nmovslq %edi,%rdx\nmovslq %r8d,%rax\nimul %rdx,%rax\nlea 0x0(,%rax,4),%r10\nmovslq %r9d,%rax\nsub $0x1,%rax\nmov %rax,-0x48(%rbp)\nmovslq %edi,%rax\nmov %rax,-0xb0(%rbp)\nmovq $0x0,-0xa8(%rbp)\nmovslq %r8d,%rax\nmov %rax,-0xc0(%rbp)\nmovq $0x0,-0xb8(%rbp)\nmov -0xb0(%rbp),%rcx\nmov -0xa8(%rbp),%rbx\nmov %rbx,%rdx\nmov -0xc0(%rbp),%r14\nmov -0xb8(%rbp),%r15\nimul %r14,%rdx\nmov %r15,%rax\nimul %rcx,%rax\nlea (%rdx,%rax,1),%rsi\nmov %rcx,%rax\nmul %r14\nmov %rax,%rcx\nmov %rdx,%rbx\nlea (%rsi,%rbx,1),%rax\nmov %rax,%rbx\nmovslq %r9d,%rax\nmov %rax,-0xd0(%rbp)\nmovq $0x0,-0xc8(%rbp)\nmov -0xd0(%rbp),%r14\nmov -0xc8(%rbp),%r15\nmov %r14,%rdx\nimul %rbx,%rdx\nmov %r15,%rax\nimul %rcx,%rax\nlea (%rdx,%rax,1),%rsi\nmov %r14,%rax\nmul %rcx\nlea (%rsi,%rdx,1),%rcx\nmov %rcx,%rdx\nmovslq %edi,%rax\nmov %rax,-0xe0(%rbp)\nmovq $0x0,-0xd8(%rbp)\nmovslq %r8d,%rax\nmov %rax,-0xf0(%rbp)\nmovq $0x0,-0xe8(%rbp)\nmov -0xe0(%rbp),%rbx\nmov -0xd8(%rbp),%rsi\nmov %rsi,%rdx\nmov -0xf0(%rbp),%r14\nmov -0xe8(%rbp),%r15\nimul %r14,%rdx\nmov %r15,%rax\nimul %rbx,%rax\nlea (%rdx,%rax,1),%rcx\nmov %rbx,%rax\nmul %r14\nadd %rdx,%rcx\nmov %rcx,%rdx\nmovslq %r9d,%rcx\nmov %rcx,-0x100(%rbp)\nmovq $0x0,-0xf8(%rbp)\nmov -0x100(%rbp),%r14\nmov -0xf8(%rbp),%r15\nmov %r14,%rsi\nimul %rdx,%rsi\nmov %r15,%rcx\nimul %rax,%rcx\nadd %rsi,%rcx\nmul %r14\nadd %rdx,%rcx\nmov %rcx,%rdx\nmovslq %edi,%rdx\nmovslq %r8d,%rax\nimul %rax,%rdx\nmovslq %r9d,%rax\nimul %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%ebx\nmov $0x0,%edx\ndiv %rbx\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rbx\nsub %rdx,%rbx\nmov %rbx,%rdx\ncmp %rdx,%rsp\nje 1428 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 1411 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 1452 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x40(%rbp)\nmovl $0x0,-0x60(%rbp)\njmpq 16ca \nmovl $0x0,-0x64(%rbp)\njmpq 16b7 \nmovl $0x0,-0x68(%rbp)\njmpq 16a4 \ncmpl $0x0,-0x60(%rbp)\nje 149b \ncmpl $0x0,-0x64(%rbp)\nje 149b \ncmpl $0x0,-0x68(%rbp)\njne 14d9 \nmov %r10,%rcx\nshr $0x2,%rcx\nmov %r11,%rdi\nshr $0x2,%rdi\nmov -0x40(%rbp),%rax\nmov -0x68(%rbp),%edx\nmovslq %edx,%rsi\nmov -0x60(%rbp),%edx\nmovslq %edx,%rdx\nimul %rdx,%rcx\nmov -0x64(%rbp),%edx\nmovslq %edx,%rdx\nimul %rdi,%rdx\nadd %rsi,%rcx\nadd %rcx,%rdx\nmovl $0x0,(%rax,%rdx,4)\njmpq 16a0 \nmov -0x60(%rbp),%eax\ncltq\nlea -0x1(%rax),%rdx\nmov -0x78(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%edx\nmov -0x64(%rbp),%eax\ncltq\nlea -0x1(%rax),%rcx\nmov -0x80(%rbp),%rax\nadd %rcx,%rax\nmovzbl (%rax),%eax\ncmp %al,%dl\njne 15b0 \nmov -0x60(%rbp),%eax\ncltq\nlea -0x1(%rax),%rdx\nmov -0x78(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%edx\nmov -0x68(%rbp),%eax\ncltq\nlea -0x1(%rax),%rcx\nmov -0x88(%rbp),%rax\nadd %rcx,%rax\nmovzbl (%rax),%eax\ncmp %al,%dl\njne 15b0 \nmov %r10,%rcx\nshr $0x2,%rcx\nmov %r11,%rdi\nshr $0x2,%rdi\nmov -0x60(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x64(%rbp),%eax\nlea -0x1(%rax),%r8d\nmov -0x68(%rbp),%eax\nlea -0x1(%rax),%esi\nmov -0x40(%rbp),%rax\nmovslq %esi,%rsi\nmovslq %edx,%rdx\nimul %rdx,%rcx\nmovslq %r8d,%rdx\nimul %rdi,%rdx\nadd %rsi,%rcx\nadd %rcx,%rdx\nmov (%rax,%rdx,4),%eax\nmov %r10,%rsi\nshr $0x2,%rsi\nmov %r11,%r8\nshr $0x2,%r8\nlea 0x1(%rax),%ecx\nmov -0x40(%rbp),%rax\nmov -0x68(%rbp),%edx\nmovslq %edx,%rdi\nmov -0x60(%rbp),%edx\nmovslq %edx,%rdx\nimul %rdx,%rsi\nmov -0x64(%rbp),%edx\nmovslq %edx,%rdx\nimul %r8,%rdx\nadd %rdi,%rsi\nadd %rsi,%rdx\nmov %ecx,(%rax,%rdx,4)\njmpq 16a0 \nmov %r10,%rcx\nshr $0x2,%rcx\nmov %r11,%rdi\nshr $0x2,%rdi\nmov -0x64(%rbp),%eax\nlea -0x1(%rax),%r8d\nmov -0x40(%rbp),%rax\nmov -0x68(%rbp),%edx\nmovslq %edx,%rsi\nmov -0x60(%rbp),%edx\nmovslq %edx,%rdx\nimul %rdx,%rcx\nmovslq %r8d,%rdx\nimul %rdi,%rdx\nadd %rsi,%rcx\nadd %rcx,%rdx\nmov (%rax,%rdx,4),%edx\nmov %r10,%rsi\nshr $0x2,%rsi\nmov %r11,%r8\nshr $0x2,%r8\nmov -0x60(%rbp),%eax\nlea -0x1(%rax),%r9d\nmov -0x40(%rbp),%rax\nmov -0x68(%rbp),%ecx\nmovslq %ecx,%rdi\nmovslq %r9d,%rcx\nimul %rcx,%rsi\nmov -0x64(%rbp),%ecx\nmovslq %ecx,%rcx\nimul %r8,%rcx\nadd %rdi,%rsi\nadd %rsi,%rcx\nmov (%rax,%rcx,4),%eax\ncmp %eax,%edx\ncmovge %edx,%eax\nmov %eax,-0x5c(%rbp)\nmov %r10,%rcx\nshr $0x2,%rcx\nmov %r11,%rdi\nshr $0x2,%rdi\nmov -0x68(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x40(%rbp),%rax\nmovslq %edx,%rsi\nmov -0x60(%rbp),%edx\nmovslq %edx,%rdx\nimul %rdx,%rcx\nmov -0x64(%rbp),%edx\nmovslq %edx,%rdx\nimul %rdi,%rdx\nadd %rsi,%rcx\nadd %rcx,%rdx\nmov (%rax,%rdx,4),%eax\nmov %r10,%rsi\nshr $0x2,%rsi\nmov %r11,%r8\nshr $0x2,%r8\ncmp %eax,-0x5c(%rbp)\ncmovge -0x5c(%rbp),%eax\nmov %eax,%edx\nmov -0x40(%rbp),%rax\nmov -0x68(%rbp),%ecx\nmovslq %ecx,%rdi\nmov -0x60(%rbp),%ecx\nmovslq %ecx,%rcx\nimul %rcx,%rsi\nmov -0x64(%rbp),%ecx\nmovslq %ecx,%rcx\nimul %r8,%rcx\nadd %rdi,%rsi\nadd %rsi,%rcx\nmov %edx,(%rax,%rcx,4)\naddl $0x1,-0x68(%rbp)\nmov -0x68(%rbp),%eax\ncmp -0x94(%rbp),%eax\njle 1489 \naddl $0x1,-0x64(%rbp)\nmov -0x64(%rbp),%eax\ncmp -0x90(%rbp),%eax\njle 147d \naddl $0x1,-0x60(%rbp)\nmov -0x60(%rbp),%eax\ncmp -0x8c(%rbp),%eax\njle 1471 \nmov %r10,%rcx\nshr $0x2,%rcx\nmov %r11,%rdi\nshr $0x2,%rdi\nmov -0x40(%rbp),%rax\nmov -0x94(%rbp),%edx\nmovslq %edx,%rsi\nmov -0x8c(%rbp),%edx\nmovslq %edx,%rdx\nimul %rdx,%rcx\nmov -0x90(%rbp),%edx\nmovslq %edx,%rdx\nimul %rdi,%rdx\nadd %rsi,%rcx\nadd %rcx,%rdx\nmov (%rax,%rdx,4),%eax\nmov -0xa0(%rbp),%rsp\nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\nje 1732 \ncallq 1080 <__stack_chk_fail@plt>\nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r13\npush r12\npush rbx\nsub rsp, 78h\nmov [rbp+var_68], rdi\nmov [rbp+var_70], rsi\nmov [rbp+var_78], rdx\nmov [rbp+var_7C], ecx\nmov [rbp+var_80], r8d\nmov [rbp+var_84], r9d\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nmov rax, rsp\nmov r13, rax\nmov eax, [rbp+var_84]\nlea edi, [rax+1]\nmov eax, [rbp+var_80]\nlea r10d, [rax+1]\nmov eax, [rbp+var_7C]\nlea r11d, [rax+1]\nmovsxd rax, edi\nsub rax, 1\nmov [rbp+var_48], rax\nmovsxd rax, edi\nlea rcx, ds:0[rax*4]\nmovsxd rax, r10d\nsub rax, 1\nmov [rbp+var_40], rax\nmovsxd rax, edi\nmov r8, rax\nmov r9d, 0\nmovsxd rax, r10d\nmov rax, rax\nmov edx, 0\nmov rbx, r9\nimul rbx, rax\nmov rsi, rdx\nimul rsi, r8\nadd rsi, rbx\nmul r8\nadd rsi, rdx\nmov rdx, rsi\nmovsxd rdx, edi\nmovsxd rax, r10d\nimul rax, rdx\nlea rsi, ds:0[rax*4]\nmovsxd rax, r11d\nsub rax, 1\nmov [rbp+var_38], rax\nmovsxd rax, edi\nmov r8, rax\nmov r9d, 0\nmovsxd rax, r10d\nmov rax, rax\nmov edx, 0\nmov r12, r9\nimul r12, rax\nmov rbx, rdx\nimul rbx, r8\nadd rbx, r12\nmul r8\nlea r8, [rbx+rdx]\nmov rdx, r8\nmovsxd r8, r11d\nmov r8, r8\nmov r9d, 0\nmov r12, rdx\nimul r12, r8\nmov rbx, r9\nimul rbx, rax\nadd rbx, r12\nmul r8\nlea r8, [rbx+rdx]\nmov rdx, r8\nmovsxd rax, edi\nmov r8, rax\nmov r9d, 0\nmovsxd rax, r10d\nmov rax, rax\nmov edx, 0\nmov r12, r9\nimul r12, rax\nmov rbx, rdx\nimul rbx, r8\nadd rbx, r12\nmul r8\nlea r8, [rbx+rdx]\nmov rdx, r8\nmovsxd r8, r11d\nmov r8, r8\nmov r9d, 0\nmov r12, rdx\nimul r12, r8\nmov rbx, r9\nimul rbx, rax\nadd rbx, r12\nmul r8\nlea r8, [rbx+rdx]\nmov rdx, r8\nmovsxd rdx, edi\nmovsxd rax, r10d\nimul rdx, rax\nmovsxd rax, r11d\nimul rax, rdx\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov ebx, 10h\nmov edx, 0\ndiv rbx\nimul rax, 10h\nmov rdi, rax\nand rdi, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rdi\nloc_1347:\ncmp rsp, rdx\njz short loc_135E\nsub rsp, 1000h\nor [rsp+1090h+var_98], 0\njmp short loc_1347\nloc_135E:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1388\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1388:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_30], rax\nmov [rbp+var_58], 0\njmp loc_15FA\nloc_13A7:\nmov [rbp+var_54], 0\njmp loc_15EA\nloc_13B3:\nmov [rbp+var_50], 0\njmp loc_15D7\nloc_13BF:\ncmp [rbp+var_58], 0\njz short loc_13D1\ncmp [rbp+var_54], 0\njz short loc_13D1\ncmp [rbp+var_50], 0\njnz short loc_140F\nloc_13D1:\nmov rdi, rsi\nshr rdi, 2\nmov r9, rcx\nshr r9, 2\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_50]\nmovsxd r8, edx\nmov edx, [rbp+var_58]\nmovsxd rdx, edx\nimul rdi, rdx\nmov edx, [rbp+var_54]\nmovsxd rdx, edx\nimul rdx, r9\nadd rdi, r8\nadd rdx, rdi\nmov dword ptr [rax+rdx*4], 0\njmp loc_15D3\nloc_140F:\nmov eax, [rbp+var_58]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+var_68]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_54]\ncdqe\nlea rdi, [rax-1]\nmov rax, [rbp+var_70]\nadd rax, rdi\nmovzx eax, byte ptr [rax]\ncmp dl, al\njnz loc_14E4\nmov eax, [rbp+var_58]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+var_68]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_50]\ncdqe\nlea rdi, [rax-1]\nmov rax, [rbp+var_78]\nadd rax, rdi\nmovzx eax, byte ptr [rax]\ncmp dl, al\njnz short loc_14E4\nmov rdi, rsi\nshr rdi, 2\nmov eax, [rbp+var_58]\nlea edx, [rax-1]\nmov r9, rcx\nshr r9, 2\nmov eax, [rbp+var_54]\nlea r10d, [rax-1]\nmov eax, [rbp+var_50]\nlea r8d, [rax-1]\nmov rax, [rbp+var_30]\nmovsxd r8, r8d\nmovsxd rdx, edx\nimul rdi, rdx\nmovsxd rdx, r10d\nimul rdx, r9\nadd rdi, r8\nadd rdx, rdi\nmov eax, [rax+rdx*4]\nmov r8, rsi\nshr r8, 2\nmov r10, rcx\nshr r10, 2\nlea edi, [rax+1]\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_50]\nmovsxd r9, edx\nmov edx, [rbp+var_58]\nmovsxd rdx, edx\nimul r8, rdx\nmov edx, [rbp+var_54]\nmovsxd rdx, edx\nimul rdx, r10\nadd r8, r9\nadd rdx, r8\nmov [rax+rdx*4], edi\njmp loc_15D3\nloc_14E4:\nmov rdi, rsi\nshr rdi, 2\nmov r9, rcx\nshr r9, 2\nmov eax, [rbp+var_54]\nlea r10d, [rax-1]\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_50]\nmovsxd r8, edx\nmov edx, [rbp+var_58]\nmovsxd rdx, edx\nimul rdi, rdx\nmovsxd rdx, r10d\nimul rdx, r9\nadd rdi, r8\nadd rdx, rdi\nmov edx, [rax+rdx*4]\nmov r8, rsi\nshr r8, 2\nmov eax, [rbp+var_58]\nlea r11d, [rax-1]\nmov r10, rcx\nshr r10, 2\nmov rax, [rbp+var_30]\nmov edi, [rbp+var_50]\nmovsxd r9, edi\nmovsxd rdi, r11d\nimul r8, rdi\nmov edi, [rbp+var_54]\nmovsxd rdi, edi\nimul rdi, r10\nadd r8, r9\nadd rdi, r8\nmov eax, [rax+rdi*4]\ncmp edx, eax\ncmovge eax, edx\nmov [rbp+var_4C], eax\nmov rdi, rsi\nshr rdi, 2\nmov r9, rcx\nshr r9, 2\nmov eax, [rbp+var_50]\nlea edx, [rax-1]\nmov rax, [rbp+var_30]\nmovsxd r8, edx\nmov edx, [rbp+var_58]\nmovsxd rdx, edx\nimul rdi, rdx\nmov edx, [rbp+var_54]\nmovsxd rdx, edx\nimul rdx, r9\nadd rdi, r8\nadd rdx, rdi\nmov edx, [rax+rdx*4]\nmov r8, rsi\nshr r8, 2\nmov r10, rcx\nshr r10, 2\nmov eax, [rbp+var_4C]\ncmp edx, eax\ncmovl edx, eax\nmov rax, [rbp+var_30]\nmov edi, [rbp+var_50]\nmovsxd r9, edi\nmov edi, [rbp+var_58]\nmovsxd rdi, edi\nimul r8, rdi\nmov edi, [rbp+var_54]\nmovsxd rdi, edi\nimul rdi, r10\nadd r8, r9\nadd rdi, r8\nmov [rax+rdi*4], edx\nloc_15D3:\nadd [rbp+var_50], 1\nloc_15D7:\nmov eax, [rbp+var_50]\ncmp eax, [rbp+var_84]\njle loc_13BF\nadd [rbp+var_54], 1\nloc_15EA:\nmov eax, [rbp+var_54]\ncmp eax, [rbp+var_80]\njle loc_13B3\nadd [rbp+var_58], 1\nloc_15FA:\nmov eax, [rbp+var_58]\ncmp eax, [rbp+var_7C]\njle loc_13A7\nshr rsi, 2\nmov r8, rsi\nshr rcx, 2\nmov rdi, rcx\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_84]\nmovsxd rsi, edx\nmov edx, [rbp+var_7C]\nmovsxd rdx, edx\nmov rcx, rdx\nimul rcx, r8\nmov edx, [rbp+var_80]\nmovsxd rdx, edx\nimul rdx, rdi\nadd rcx, rsi\nadd rdx, rcx\nmov eax, [rax+rdx*4]\nmov rsp, r13\nmov rdx, [rbp+var_28]\nsub rdx, fs:28h\njz short loc_1658\ncall ___stack_chk_fail\nloc_1658:\nlea rsp, [rbp-18h]\npop rbx\npop r12\npop r13\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, __int64 a3, int a4, int a5, int a6)\n{\n int v6; // r11d\n unsigned __int64 v7; // rcx\n unsigned __int64 v8; // rsi\n unsigned __int64 v9; // rax\n void *v10; // rsp\n int v11; // eax\n int v12; // edx\n _BYTE v14[12]; // [rsp+8h] [rbp-90h] BYREF\n int v15; // [rsp+14h] [rbp-84h]\n int v16; // [rsp+18h] [rbp-80h]\n int v17; // [rsp+1Ch] [rbp-7Ch]\n __int64 v18; // [rsp+20h] [rbp-78h]\n __int64 v19; // [rsp+28h] [rbp-70h]\n __int64 v20; // [rsp+30h] [rbp-68h]\n int i; // [rsp+40h] [rbp-58h]\n int j; // [rsp+44h] [rbp-54h]\n int k; // [rsp+48h] [rbp-50h]\n int v24; // [rsp+4Ch] [rbp-4Ch]\n __int64 v25; // [rsp+50h] [rbp-48h]\n __int64 v26; // [rsp+58h] [rbp-40h]\n __int64 v27; // [rsp+60h] [rbp-38h]\n _BYTE *v28; // [rsp+68h] [rbp-30h]\n unsigned __int64 v29; // [rsp+70h] [rbp-28h]\n\n v20 = a1;\n v19 = a2;\n v18 = a3;\n v17 = a4;\n v16 = a5;\n v15 = a6;\n v29 = __readfsqword(0x28u);\n v6 = a4 + 1;\n v25 = a6 + 1 - 1LL;\n v7 = 4LL * (a6 + 1);\n v26 = a5 + 1 - 1LL;\n v8 = 4 * (a6 + 1) * (__int64)(a5 + 1);\n v27 = v6 - 1LL;\n v9 = 16 * ((4 * (a5 + 1) * (__int64)(a6 + 1) * v6 + 15) / 0x10uLL);\n while ( v14 != &v14[-(v9 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v10 = alloca(v9 & 0xFFF);\n if ( (v9 & 0xFFF) != 0 )\n *(_QWORD *)&v14[(v9 & 0xFFF) - 8] = *(_QWORD *)&v14[(v9 & 0xFFF) - 8];\n v28 = v14;\n for ( i = 0; i <= v17; ++i )\n {\n for ( j = 0; j <= v16; ++j )\n {\n for ( k = 0; k <= v15; ++k )\n {\n if ( i && j && k )\n {\n if ( *(_BYTE *)(i - 1LL + v20) == *(_BYTE *)(j - 1LL + v19)\n && *(_BYTE *)(i - 1LL + v20) == *(_BYTE *)(k - 1LL + v18) )\n {\n *(_DWORD *)&v28[4 * k + 4 * i * (v8 >> 2) + 4 * (v7 >> 2) * j] = *(_DWORD *)&v28[4 * k\n - 4\n + 4 * (i - 1) * (v8 >> 2)\n + 4 * (v7 >> 2) * (j - 1)]\n + 1;\n }\n else\n {\n v11 = *(_DWORD *)&v28[4 * k + 4 * (i - 1) * (v8 >> 2) + 4 * (v7 >> 2) * j];\n if ( *(_DWORD *)&v28[4 * k + 4 * i * (v8 >> 2) + 4 * (v7 >> 2) * (j - 1)] >= v11 )\n v11 = *(_DWORD *)&v28[4 * k + 4 * i * (v8 >> 2) + 4 * (v7 >> 2) * (j - 1)];\n v24 = v11;\n v12 = *(_DWORD *)&v28[4 * k - 4 + 4 * i * (v8 >> 2) + 4 * (v7 >> 2) * j];\n if ( v12 < v11 )\n v12 = v11;\n *(_DWORD *)&v28[4 * k + 4 * i * (v8 >> 2) + 4 * (v7 >> 2) * j] = v12;\n }\n }\n else\n {\n *(_DWORD *)&v28[4 * k + 4 * i * (v8 >> 2) + 4 * (v7 >> 2) * j] = 0;\n }\n }\n }\n }\n return *(unsigned int *)&v28[4 * v15 + 4 * (v8 >> 2) * v17 + 4 * (v7 >> 2) * v16];\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\npush r13\npush r12\npush rbx\nsub rsp, 78h\nmov [rbp+var_68], rdi\nmov [rbp+var_70], rsi\nmov [rbp+var_78], rdx\nmov [rbp+var_7C], ecx\nmov [rbp+var_80], r8d\nmov [rbp+var_84], r9d\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nmov rax, rsp\nmov r13, rax\nmov eax, [rbp+var_84]\nlea edi, [rax+1]\nmov eax, [rbp+var_80]\nlea r10d, [rax+1]\nmov eax, [rbp+var_7C]\nlea r11d, [rax+1]\nmovsxd rax, edi\nsub rax, 1\nmov [rbp+var_48], rax\nmovsxd rax, edi\nlea rcx, ds:0[rax*4]\nmovsxd rax, r10d\nsub rax, 1\nmov [rbp+var_40], rax\nmovsxd rax, edi\nmov r8, rax\nmov r9d, 0\nmovsxd rax, r10d\nmov rax, rax\nmov edx, 0\nmov rbx, r9\nimul rbx, rax\nmov rsi, rdx\nimul rsi, r8\nadd rsi, rbx\nmul r8\nadd rsi, rdx\nmov rdx, rsi\nmovsxd rdx, edi\nmovsxd rax, r10d\nimul rax, rdx\nlea rsi, ds:0[rax*4]\nmovsxd rax, r11d\nsub rax, 1\nmov [rbp+var_38], rax\nmovsxd rax, edi\nmov r8, rax\nmov r9d, 0\nmovsxd rax, r10d\nmov rax, rax\nmov edx, 0\nmov r12, r9\nimul r12, rax\nmov rbx, rdx\nimul rbx, r8\nadd rbx, r12\nmul r8\nlea r8, [rbx+rdx]\nmov rdx, r8\nmovsxd r8, r11d\nmov r8, r8\nmov r9d, 0\nmov r12, rdx\nimul r12, r8\nmov rbx, r9\nimul rbx, rax\nadd rbx, r12\nmul r8\nlea r8, [rbx+rdx]\nmov rdx, r8\nmovsxd rax, edi\nmov r8, rax\nmov r9d, 0\nmovsxd rax, r10d\nmov rax, rax\nmov edx, 0\nmov r12, r9\nimul r12, rax\nmov rbx, rdx\nimul rbx, r8\nadd rbx, r12\nmul r8\nlea r8, [rbx+rdx]\nmov rdx, r8\nmovsxd r8, r11d\nmov r8, r8\nmov r9d, 0\nmov r12, rdx\nimul r12, r8\nmov rbx, r9\nimul rbx, rax\nadd rbx, r12\nmul r8\nlea r8, [rbx+rdx]\nmov rdx, r8\nmovsxd rdx, edi\nmovsxd rax, r10d\nimul rdx, rax\nmovsxd rax, r11d\nimul rax, rdx\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov ebx, 10h\nmov edx, 0\ndiv rbx\nimul rax, 10h\nmov rdi, rax\nand rdi, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rdi\nloc_1347:\ncmp rsp, rdx\njz short loc_135E\nsub rsp, 1000h\nor [rsp+1090h+var_98], 0\njmp short loc_1347\nloc_135E:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1388\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1388:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_30], rax\nmov [rbp+var_58], 0\njmp loc_15FA\nloc_13A7:\nmov [rbp+var_54], 0\njmp loc_15EA\nloc_13B3:\nmov [rbp+var_50], 0\njmp loc_15D7\nloc_13BF:\ncmp [rbp+var_58], 0\njz short loc_13D1\ncmp [rbp+var_54], 0\njz short loc_13D1\ncmp [rbp+var_50], 0\njnz short loc_140F\nloc_13D1:\nmov rdi, rsi\nshr rdi, 2\nmov r9, rcx\nshr r9, 2\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_50]\nmovsxd r8, edx\nmov edx, [rbp+var_58]\nmovsxd rdx, edx\nimul rdi, rdx\nmov edx, [rbp+var_54]\nmovsxd rdx, edx\nimul rdx, r9\nadd rdi, r8\nadd rdx, rdi\nmov dword ptr [rax+rdx*4], 0\njmp loc_15D3\nloc_140F:\nmov eax, [rbp+var_58]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+var_68]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_54]\ncdqe\nlea rdi, [rax-1]\nmov rax, [rbp+var_70]\nadd rax, rdi\nmovzx eax, byte ptr [rax]\ncmp dl, al\njnz loc_14E4\nmov eax, [rbp+var_58]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+var_68]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_50]\ncdqe\nlea rdi, [rax-1]\nmov rax, [rbp+var_78]\nadd rax, rdi\nmovzx eax, byte ptr [rax]\ncmp dl, al\njnz short loc_14E4\nmov rdi, rsi\nshr rdi, 2\nmov eax, [rbp+var_58]\nlea edx, [rax-1]\nmov r9, rcx\nshr r9, 2\nmov eax, [rbp+var_54]\nlea r10d, [rax-1]\nmov eax, [rbp+var_50]\nlea r8d, [rax-1]\nmov rax, [rbp+var_30]\nmovsxd r8, r8d\nmovsxd rdx, edx\nimul rdi, rdx\nmovsxd rdx, r10d\nimul rdx, r9\nadd rdi, r8\nadd rdx, rdi\nmov eax, [rax+rdx*4]\nmov r8, rsi\nshr r8, 2\nmov r10, rcx\nshr r10, 2\nlea edi, [rax+1]\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_50]\nmovsxd r9, edx\nmov edx, [rbp+var_58]\nmovsxd rdx, edx\nimul r8, rdx\nmov edx, [rbp+var_54]\nmovsxd rdx, edx\nimul rdx, r10\nadd r8, r9\nadd rdx, r8\nmov [rax+rdx*4], edi\njmp loc_15D3\nloc_14E4:\nmov rdi, rsi\nshr rdi, 2\nmov r9, rcx\nshr r9, 2\nmov eax, [rbp+var_54]\nlea r10d, [rax-1]\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_50]\nmovsxd r8, edx\nmov edx, [rbp+var_58]\nmovsxd rdx, edx\nimul rdi, rdx\nmovsxd rdx, r10d\nimul rdx, r9\nadd rdi, r8\nadd rdx, rdi\nmov edx, [rax+rdx*4]\nmov r8, rsi\nshr r8, 2\nmov eax, [rbp+var_58]\nlea r11d, [rax-1]\nmov r10, rcx\nshr r10, 2\nmov rax, [rbp+var_30]\nmov edi, [rbp+var_50]\nmovsxd r9, edi\nmovsxd rdi, r11d\nimul r8, rdi\nmov edi, [rbp+var_54]\nmovsxd rdi, edi\nimul rdi, r10\nadd r8, r9\nadd rdi, r8\nmov eax, [rax+rdi*4]\ncmp edx, eax\ncmovge eax, edx\nmov [rbp+var_4C], eax\nmov rdi, rsi\nshr rdi, 2\nmov r9, rcx\nshr r9, 2\nmov eax, [rbp+var_50]\nlea edx, [rax-1]\nmov rax, [rbp+var_30]\nmovsxd r8, edx\nmov edx, [rbp+var_58]\nmovsxd rdx, edx\nimul rdi, rdx\nmov edx, [rbp+var_54]\nmovsxd rdx, edx\nimul rdx, r9\nadd rdi, r8\nadd rdx, rdi\nmov edx, [rax+rdx*4]\nmov r8, rsi\nshr r8, 2\nmov r10, rcx\nshr r10, 2\nmov eax, [rbp+var_4C]\ncmp edx, eax\ncmovl edx, eax\nmov rax, [rbp+var_30]\nmov edi, [rbp+var_50]\nmovsxd r9, edi\nmov edi, [rbp+var_58]\nmovsxd rdi, edi\nimul r8, rdi\nmov edi, [rbp+var_54]\nmovsxd rdi, edi\nimul rdi, r10\nadd r8, r9\nadd rdi, r8\nmov [rax+rdi*4], edx\nloc_15D3:\nadd [rbp+var_50], 1\nloc_15D7:\nmov eax, [rbp+var_50]\ncmp eax, [rbp+var_84]\njle loc_13BF\nadd [rbp+var_54], 1\nloc_15EA:\nmov eax, [rbp+var_54]\ncmp eax, [rbp+var_80]\njle loc_13B3\nadd [rbp+var_58], 1\nloc_15FA:\nmov eax, [rbp+var_58]\ncmp eax, [rbp+var_7C]\njle loc_13A7\nshr rsi, 2\nmov r8, rsi\nshr rcx, 2\nmov rdi, rcx\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_84]\nmovsxd rsi, edx\nmov edx, [rbp+var_7C]\nmovsxd rdx, edx\nmov rcx, rdx\nimul rcx, r8\nmov edx, [rbp+var_80]\nmovsxd rdx, edx\nimul rdx, rdi\nadd rcx, rsi\nadd rdx, rcx\nmov eax, [rax+rdx*4]\nmov rsp, r13\nmov rdx, [rbp+var_28]\nsub rdx, fs:28h\njz short loc_1658\ncall ___stack_chk_fail\nloc_1658:\nlea rsp, [rbp-18h]\npop rbx\npop r12\npop r13\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, __int64 a2, __int64 a3, int a4, int a5, int a6)\n{\n int v6; // r11d\n unsigned __int64 v7; // rcx\n unsigned __int64 v8; // rsi\n unsigned __int64 v9; // rax\n void *v10; // rsp\n int v11; // eax\n int v12; // edx\n _BYTE v14[12]; // [rsp+8h] [rbp-90h] BYREF\n int v15; // [rsp+14h] [rbp-84h]\n int v16; // [rsp+18h] [rbp-80h]\n int v17; // [rsp+1Ch] [rbp-7Ch]\n __int64 v18; // [rsp+20h] [rbp-78h]\n __int64 v19; // [rsp+28h] [rbp-70h]\n __int64 v20; // [rsp+30h] [rbp-68h]\n int i; // [rsp+40h] [rbp-58h]\n int j; // [rsp+44h] [rbp-54h]\n int k; // [rsp+48h] [rbp-50h]\n int v24; // [rsp+4Ch] [rbp-4Ch]\n __int64 v25; // [rsp+50h] [rbp-48h]\n __int64 v26; // [rsp+58h] [rbp-40h]\n __int64 v27; // [rsp+60h] [rbp-38h]\n _BYTE *v28; // [rsp+68h] [rbp-30h]\n unsigned __int64 v29; // [rsp+70h] [rbp-28h]\n\n v20 = a1;\n v19 = a2;\n v18 = a3;\n v17 = a4;\n v16 = a5;\n v15 = a6;\n v29 = __readfsqword(0x28u);\n v6 = a4 + 1;\n v25 = a6 + 1 - 1LL;\n v7 = 4LL * (a6 + 1);\n v26 = a5 + 1 - 1LL;\n v8 = 4 * (a6 + 1) * (__int64)(a5 + 1);\n v27 = v6 - 1LL;\n v9 = 16 * ((4 * (a5 + 1) * (__int64)(a6 + 1) * v6 + 15) / 0x10uLL);\n while ( v14 != &v14[-(v9 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v10 = alloca(v9 & 0xFFF);\n if ( (v9 & 0xFFF) != 0 )\n *(_QWORD *)&v14[(v9 & 0xFFF) - 8] = *(_QWORD *)&v14[(v9 & 0xFFF) - 8];\n v28 = v14;\n for ( i = 0; i <= v17; ++i )\n {\n for ( j = 0; j <= v16; ++j )\n {\n for ( k = 0; k <= v15; ++k )\n {\n if ( i && j && k )\n {\n if ( *(_BYTE *)(i - 1LL + v20) == *(_BYTE *)(j - 1LL + v19)\n && *(_BYTE *)(i - 1LL + v20) == *(_BYTE *)(k - 1LL + v18) )\n {\n *(_DWORD *)&v28[4 * k + 4 * i * (v8 >> 2) + 4 * (v7 >> 2) * j] = *(_DWORD *)&v28[4 * k\n - 4\n + 4 * (i - 1) * (v8 >> 2)\n + 4 * (v7 >> 2) * (j - 1)]\n + 1;\n }\n else\n {\n v11 = *(_DWORD *)&v28[4 * k + 4 * (i - 1) * (v8 >> 2) + 4 * (v7 >> 2) * j];\n if ( *(_DWORD *)&v28[4 * k + 4 * i * (v8 >> 2) + 4 * (v7 >> 2) * (j - 1)] >= v11 )\n v11 = *(_DWORD *)&v28[4 * k + 4 * i * (v8 >> 2) + 4 * (v7 >> 2) * (j - 1)];\n v24 = v11;\n v12 = *(_DWORD *)&v28[4 * k - 4 + 4 * i * (v8 >> 2) + 4 * (v7 >> 2) * j];\n if ( v12 < v11 )\n v12 = v11;\n *(_DWORD *)&v28[4 * k + 4 * i * (v8 >> 2) + 4 * (v7 >> 2) * j] = v12;\n }\n }\n else\n {\n *(_DWORD *)&v28[4 * k + 4 * i * (v8 >> 2) + 4 * (v7 >> 2) * j] = 0;\n }\n }\n }\n }\n return *(unsigned int *)&v28[4 * v15 + 4 * (v8 >> 2) * v17 + 4 * (v7 >> 2) * v16];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, long long a2, long long a3, int a4, int a5,\n int a6) {\n int v6;\n unsigned long long v7;\n unsigned long long v8;\n unsigned long long v9;\n void *v10;\n int v11;\n int v12;\n uint8_t v14[12];\n int v15;\n int v16;\n int v17;\n long long v18;\n long long v19;\n long long v20;\n int i;\n int j;\n int k;\n int v24;\n long long v25;\n long long v26;\n long long v27;\n uint8_t *v28;\n unsigned long long v29;\n v20 = a1;\n v19 = a2;\n v18 = a3;\n v17 = a4;\n v16 = a5;\n v15 = a6;\n v29 = __readfsqword(40u);\n v6 = a4 + 1;\n v25 = a6 + 1 - 1LL;\n v7 = 4LL * (a6 + 1);\n v26 = a5 + 1 - 1LL;\n v8 = 4 * (a6 + 1) * (long long)(a5 + 1);\n v27 = v6 - 1LL;\n v9 = 16 * ((4 * (a5 + 1) * (long long)(a6 + 1) * v6 + 15) / 16uLL);\n while (v14 != &v14[-(v9 & 18446744073709547520LL)])\n ;\n v10 = alloca(v9 & 4095);\n if ((v9 & 4095) != 0)\n *(uint64_t *)&v14[(v9 & 4095) - 8] = *(uint64_t *)&v14[(v9 & 4095) - 8];\n v28 = v14;\n for (i = 0; i <= v17; ++i) {\n for (j = 0; j <= v16; ++j) {\n for (k = 0; k <= v15; ++k) {\n if (i && j && k) {\n if (*(uint8_t *)(i - 1LL + v20) == *(uint8_t *)(j - 1LL + v19) &&\n *(uint8_t *)(i - 1LL + v20) == *(uint8_t *)(k - 1LL + v18)) {\n *(uint32_t *)&v28[4 * k + 4 * i * (v8 >> 2) + 4 * (v7 >> 2) * j] =\n *(uint32_t *)&v28[4 * k - 4 + 4 * (i - 1) * (v8 >> 2) +\n 4 * (v7 >> 2) * (j - 1)] +\n 1;\n } else {\n v11 = *(uint32_t *)&v28[4 * k + 4 * (i - 1) * (v8 >> 2) +\n 4 * (v7 >> 2) * j];\n if (*(uint32_t *)&v28[4 * k + 4 * i * (v8 >> 2) +\n 4 * (v7 >> 2) * (j - 1)] >= v11)\n v11 = *(uint32_t *)&v28[4 * k + 4 * i * (v8 >> 2) +\n 4 * (v7 >> 2) * (j - 1)];\n v24 = v11;\n v12 = *(uint32_t *)&v28[4 * k - 4 + 4 * i * (v8 >> 2) +\n 4 * (v7 >> 2) * j];\n if (v12 < v11) v12 = v11;\n *(uint32_t *)&v28[4 * k + 4 * i * (v8 >> 2) + 4 * (v7 >> 2) * j] =\n v12;\n }\n } else {\n *(uint32_t *)&v28[4 * k + 4 * i * (v8 >> 2) + 4 * (v7 >> 2) * j] = 0;\n }\n }\n }\n }\n return *(\n unsigned int *)&v28[4 * v15 + 4 * (v8 >> 2) * v17 + 4 * (v7 >> 2) * v16];\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, long long a3, int a4, int a5,\n int a6) {\n int v6;\n unsigned long long v7;\n unsigned long long v8;\n unsigned long long v9;\n void *v10;\n int v11;\n int v12;\n uint8_t v14[12];\n int v15;\n int v16;\n int v17;\n long long v18;\n long long v19;\n long long v20;\n int i;\n int j;\n int k;\n int v24;\n long long v25;\n long long v26;\n long long v27;\n uint8_t *v28;\n unsigned long long v29;\n v20 = a1;\n v19 = a2;\n v18 = a3;\n v17 = a4;\n v16 = a5;\n v15 = a6;\n v29 = __readfsqword(40u);\n v6 = a4 + 1;\n v25 = a6 + 1 - 1LL;\n v7 = 4LL * (a6 + 1);\n v26 = a5 + 1 - 1LL;\n v8 = 4 * (a6 + 1) * (long long)(a5 + 1);\n v27 = v6 - 1LL;\n v9 = 16 * ((4 * (a5 + 1) * (long long)(a6 + 1) * v6 + 15) / 16uLL);\n while (v14 != &v14[-(v9 & 18446744073709547520LL)])\n ;\n v10 = alloca(v9 & 4095);\n if ((v9 & 4095) != 0)\n *(uint64_t *)&v14[(v9 & 4095) - 8] = *(uint64_t *)&v14[(v9 & 4095) - 8];\n v28 = v14;\n for (i = 0; i <= v17; ++i) {\n for (j = 0; j <= v16; ++j) {\n for (k = 0; k <= v15; ++k) {\n if (i && j && k) {\n if (*(uint8_t *)(i - 1LL + v20) == *(uint8_t *)(j - 1LL + v19) &&\n *(uint8_t *)(i - 1LL + v20) == *(uint8_t *)(k - 1LL + v18)) {\n *(uint32_t *)&v28[4 * k + 4 * i * (v8 >> 2) + 4 * (v7 >> 2) * j] =\n *(uint32_t *)&v28[4 * k - 4 + 4 * (i - 1) * (v8 >> 2) +\n 4 * (v7 >> 2) * (j - 1)] +\n 1;\n } else {\n v11 = *(uint32_t *)&v28[4 * k + 4 * (i - 1) * (v8 >> 2) +\n 4 * (v7 >> 2) * j];\n if (*(uint32_t *)&v28[4 * k + 4 * i * (v8 >> 2) +\n 4 * (v7 >> 2) * (j - 1)] >= v11)\n v11 = *(uint32_t *)&v28[4 * k + 4 * i * (v8 >> 2) +\n 4 * (v7 >> 2) * (j - 1)];\n v24 = v11;\n v12 = *(uint32_t *)&v28[4 * k - 4 + 4 * i * (v8 >> 2) +\n 4 * (v7 >> 2) * j];\n if (v12 < v11) v12 = v11;\n *(uint32_t *)&v28[4 * k + 4 * i * (v8 >> 2) + 4 * (v7 >> 2) * j] =\n v12;\n }\n } else {\n *(uint32_t *)&v28[4 * k + 4 * i * (v8 >> 2) + 4 * (v7 >> 2) * j] = 0;\n }\n }\n }\n }\n return *(\n unsigned int *)&v28[4 * v15 + 4 * (v8 >> 2) * v17 + 4 * (v7 >> 2) * v16];\n}" + }, + { + "index": 747, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char* X, char* Y, char* Z, int m, int n, int o) {\n int L[m + 1][n + 1][o + 1];\n int i, j, k;\n for (i = 0; i <= m; i++) {\n for (j = 0; j <= n; j++) {\n for (k = 0; k <= o; k++) {\n if (i == 0 || j == 0 || k == 0) {\n L[i][j][k] = 0;\n } else if (X[i - 1] == Y[j - 1] && X[i - 1] == Z[k - 1]) {\n L[i][j][k] = L[i - 1][j - 1][k - 1] + 1;\n } else {\n int max1 =\n L[i - 1][j][k] > L[i][j - 1][k] ? L[i - 1][j][k] : L[i][j - 1][k];\n L[i][j][k] = max1 > L[i][j][k - 1] ? max1 : L[i][j][k - 1];\n }\n }\n }\n }\n return L[m][n][o];\n}", + "test": "int main() {\n\n\t// Testing the implementation with assertions\n\n\tassert(func0(\"AGGT12\", \"12TXAYB\", \"12XBA\", 6, 7, 5) == 2);\n\n\tassert(func0(\"Reels\", \"Reelsfor\", \"ReelsforReels\", 5, 8, 13) == 5);\n\n\tassert(func0(\"abcd1e2\", \"bc12ea\", \"bd1ea\", 7, 6, 5) == 3);\n\n\n\n\tprintf(\"All tests passed!\\n\");\n\n\treturn 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0xa8,%rsp\nmov %rdi,%r13\nmov %rsi,%r14\nmov %rdx,-0x70(%rbp)\nmov %ecx,-0xbc(%rbp)\nmov %r8d,-0x50(%rbp)\nmov %r9d,%eax\nmov %r9d,-0x4c(%rbp)\nmov %fs:0x28,%rbx\nmov %rbx,-0x38(%rbp)\nxor %ebx,%ebx\nadd $0x1,%eax\nmovslq %eax,%rdx\nlea 0x0(,%rdx,4),%r11\nlea 0x1(%r8),%eax\ncltq\nimul %rdx,%rax\nlea 0x0(,%rax,4),%rbx\nmov %rbx,-0xb8(%rbp)\nlea 0x1(%rcx),%edx\nmovslq %edx,%rdx\nimul %rdx,%rax\nlea 0xf(,%rax,4),%rdx\nmov %rdx,%rax\nand $0xfffffffffffffff0,%rax\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rbx\nsub %rdx,%rbx\nmov %rbx,%rdx\ncmp %rdx,%rsp\nje 1232 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 121b \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\nje 1249 \norq $0x0,-0x8(%rsp,%rdx,1)\nmov %rsp,%rsi\nmov %rsi,-0xc8(%rbp)\nmov -0xbc(%rbp),%ecx\ntest %ecx,%ecx\njs 1409 \nmov -0xb8(%rbp),%rbx\nshr $0x2,%rbx\nmov %rbx,-0x98(%rbp)\nmov %r11,%rax\nshr $0x2,%rax\nmov %rbx,%rdi\nneg %rdi\nmov %rdi,-0x80(%rbp)\nsub $0x1,%r13\nmov %ecx,%ecx\nmov %rcx,-0xa0(%rbp)\nmov %rsi,-0xa8(%rbp)\nsub %r11,%rsi\nmov %rsi,-0xb0(%rbp)\nmov %rdi,-0x90(%rbp)\nmovq $0x0,-0x88(%rbp)\nmovq $0x0,-0x78(%rbp)\nmov $0x0,%esi\nmov -0x50(%rbp),%edi\nmov %rdi,-0x58(%rbp)\nadd %rbx,%rax\nshl $0x2,%rax\nmov %rax,-0x60(%rbp)\nmov -0x4c(%rbp),%edi\nmovq $0x0,-0x68(%rbp)\njmpq 13ba \nmovl $0x0,(%r8,%rax,4)\nlea 0x1(%rax),%rdx\ncmp %rax,%rdi\nje 1352 \nmov %rdx,%rax\ntest %esi,%esi\nsete %r15b\ntest %ecx,%ecx\nsete %dl\nor %dl,%r15b\njne 12e3 \ntest %eax,%eax\nje 12e3 \nmovzbl 0x0(%r13),%edx\ncmp -0x1(%r14,%rcx,1),%dl\nje 1335 \nmov (%rbx,%rax,4),%edx\ncmp %edx,(%r10,%rax,4)\ncmovge (%r10,%rax,4),%edx\nmov -0x4(%r9,%rax,4),%r15d\ncmp %r15d,%edx\ncmovl %r15d,%edx\nmov %edx,(%r9,%rax,4)\njmp 12eb \nmov -0x70(%rbp),%r15\ncmp -0x1(%r15,%rax,1),%dl\njne 1317 \nmov -0x4(%r12,%rax,4),%edx\nadd $0x1,%edx\nmov -0x48(%rbp),%r15\nmov %edx,(%r15,%rax,4)\njmp 12eb \nlea 0x1(%rcx),%rax\nadd %r11,%r8\nadd %r11,%r12\nadd %r11,%r10\nadd %r11,%rbx\nadd %r11,%r9\ncmp -0x58(%rbp),%rcx\nje 1389 \nmov %rax,%rcx\nmov -0x60(%rbp),%rax\nadd %r12,%rax\nmov %rax,-0x48(%rbp)\nmov -0x68(%rbp),%rax\ncmpl $0x0,-0x4c(%rbp)\njns 12f7 \njmp 1352 \nlea 0x1(%rsi),%rax\nmov -0x98(%rbp),%rbx\nadd %rbx,-0x78(%rbp)\nadd %rbx,-0x80(%rbp)\nadd %rbx,-0x88(%rbp)\nadd %rbx,-0x90(%rbp)\nadd $0x1,%r13\ncmp -0xa0(%rbp),%rsi\nje 1409 \nmov %rax,%rsi\ncmpl $0x0,-0x50(%rbp)\njs 1389 \nmov -0xa8(%rbp),%rax\nmov -0x78(%rbp),%rbx\nlea (%rax,%rbx,4),%r8\nmov -0xb0(%rbp),%rbx\nmov -0x80(%rbp),%rcx\nlea (%rbx,%rcx,4),%r12\nmov -0x88(%rbp),%rcx\nlea 0x0(,%rcx,4),%r9\nlea (%rbx,%r9,1),%r10\nmov -0x90(%rbp),%rbx\nlea (%rax,%rbx,4),%rbx\nadd %rax,%r9\nmov $0x0,%ecx\njmpq 136e \nmovslq -0x4c(%rbp),%rax\nmovslq -0xbc(%rbp),%rcx\nmov -0xb8(%rbp),%rdx\nshr $0x2,%rdx\nimul %rdx,%rcx\nmovslq -0x50(%rbp),%rdx\nshr $0x2,%r11\nimul %rdx,%r11\nadd %rcx,%rax\nadd %r11,%rax\nmov -0xc8(%rbp),%rbx\nmov (%rbx,%rax,4),%eax\nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\njne 145d \nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\ncallq 1080 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 0A8h\nmov rax, rdi\nmov r13, rsi\nmov [rbp+var_60], rdx\nmov r14d, ecx\nmov [rbp+var_58], r8d\nmov ebx, r9d\nmov rcx, fs:28h\nmov [rbp+var_38], rcx\nxor ecx, ecx\nlea ecx, [r9+1]\nmovsxd rcx, ecx\nlea r11, ds:0[rcx*4]\nlea esi, [r8+1]\nmovsxd rsi, esi\nimul rsi, rcx\nlea rcx, ds:0[rsi*4]\nlea edi, [r14+1]\nmovsxd rdi, edi\nimul rsi, rdi\nlea rdi, ds:0Fh[rsi*4]\nmov rsi, rdi\nand rsi, 0FFFFFFFFFFFFFFF0h\nand rdi, 0FFFFFFFFFFFFF000h\nmov r8, rsp\nsub r8, rdi\nloc_120D:\ncmp rsp, r8\njz short loc_1224\nsub rsp, 1000h\nor [rsp+10D0h+var_D8], 0\njmp short loc_120D\nloc_1224:\nmov rdi, rsi\nand edi, 0FFFh\nsub rsp, rdi\ntest rdi, rdi\njz short loc_123B\nor [rsp+rdi+0D0h+var_D8], 0\nloc_123B:\nmov rdi, rsp\nmov [rbp+var_78], rdi\ntest r14d, r14d\njs loc_1465\nmov r10, rcx\nshr r10, 2\nmov rdx, r11\nshr rdx, 2\nmov [rbp+var_68], rdx\nlea rdx, [rax-1]\nlea eax, [r14+1]\nmov [rbp+var_B0], rax\nsub rdi, r11\nmov [rbp+var_B8], rdi\nmov [rbp+var_A0], 0FFFFFFFFFFFFFFFFh\nmov [rbp+var_98], 0\nmov [rbp+var_90], 0\nmov r12d, 0\nmov eax, [rbp+var_58]\nlea r15d, [rax+1]\nlea esi, [rbx+1]\nmov [rbp+var_C0], rcx\nmov [rbp+var_C4], r14d\nmov r14, r13\nmov r13d, ebx\nmov rbx, r15\njmp loc_13EC\nloc_12C3:\nmov dword ptr [rdi+rax*4], 0\nloc_12CA:\nadd rax, 1\nadd r10, 4\ncmp rax, rsi\njz loc_1380\nloc_12DB:\ntest r12d, r12d\nsetz bl\ntest ecx, ecx\nsetz r11b\nor r11b, bl\njnz short loc_12C3\ntest eax, eax\njz short loc_12C3\nmovzx r11d, byte ptr [rdx]\ncmp r11b, [r14+rcx-1]\njz short loc_131A\nloc_12FB:\nmov ebx, [r10+r9*4]\nmov r11d, [r10-4]\ncmp ebx, r11d\ncmovge r11d, ebx\nmov ebx, [r8+rax*4]\ncmp r11d, ebx\ncmovl r11d, ebx\nmov [r10], r11d\njmp short loc_12CA\nloc_131A:\nmov rbx, [rbp+var_60]\ncmp r11b, [rbx+rax-1]\njnz short loc_12FB\nmovsxd r11, eax\nmovsxd rbx, [rbp+var_50]\nmov r13, [rbp+var_68]\nimul rbx, r13\nmov r13, [rbp+var_80]\nadd r11, r13\nadd rbx, r11\nmov [rbp+var_70], rbx\nlea r11d, [rax-1]\nmovsxd r11, r11d\nmov ebx, [rbp+var_54]\nsub ebx, 1\nmovsxd rbx, ebx\nmov r13, [rbp+var_68]\nimul rbx, r13\nmov r13, [rbp+var_88]\nadd r11, r13\nadd r11, rbx\nmov rbx, [rbp+var_78]\nmov r11d, [rbx+r11*4]\nadd r11d, 1\nmov r13, [rbp+var_70]\nmov [rbx+r13*4], r11d\njmp loc_12CA\nloc_1380:\nmov r11, [rbp+var_48]\nmov r13d, [rbp+var_4C]\nloc_1388:\nadd rcx, 1\nadd rdi, r11\nadd r8, r11\ncmp rcx, r15\njz short loc_13B8\nloc_1397:\nmov [rbp+var_54], ecx\nmov [rbp+var_50], ecx\nlea r10, [r11+r8]\nmov eax, 0\ntest r13d, r13d\njs short loc_1388\nmov [rbp+var_48], r11\nmov [rbp+var_4C], r13d\njmp loc_12DB\nloc_13B8:\nmov r10, [rbp+var_A8]\nmov rbx, r15\nloc_13C2:\nadd r12, 1\nadd [rbp+var_90], r10\nadd [rbp+var_98], r10\nadd [rbp+var_A0], 1\nadd rdx, 1\nmov rax, [rbp+var_B0]\ncmp r12, rax\njz short loc_1454\nloc_13EC:\nmov eax, r12d\ncmp [rbp+var_58], 0\njs short loc_13C2\nmov rdi, [rbp+var_78]\nmov rcx, [rbp+var_90]\nlea rdi, [rdi+rcx*4]\nmov rcx, [rbp+var_B8]\nmov r9, [rbp+var_98]\nlea r8, [rcx+r9*4]\nmov r9, [rbp+var_A0]\nsub r9, r12\nimul r9, r10\nmov ecx, 0\ncdqe\nimul rax, r10\nmov [rbp+var_80], rax\nlea eax, [r12-1]\ncdqe\nimul rax, r10\nmov [rbp+var_88], rax\nmov [rbp+var_A8], r10\nmov r15, rbx\njmp loc_1397\nloc_1454:\nmov rcx, [rbp+var_C0]\nmov r14d, [rbp+var_C4]\nmov ebx, r13d\nloc_1465:\nmovsxd rax, ebx\nmovsxd rdx, r14d\nshr rcx, 2\nimul rcx, rdx\nmovsxd rdx, [rbp+var_58]\nshr r11, 2\nimul rdx, r11\nadd rax, rcx\nadd rax, rdx\nmov rdx, [rbp+var_78]\nmov eax, [rdx+rax*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_14AA\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_14AA:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, __int64 a3, int a4, int a5, int a6)\n{\n int v9; // ebx\n __int64 v10; // rcx\n unsigned __int64 v11; // r11\n __int64 v12; // rsi\n unsigned __int64 v13; // rcx\n __int64 v14; // rdi\n __int16 v15; // si\n signed __int64 v16; // rdi\n void *v17; // rsp\n unsigned __int64 v18; // r10\n _BYTE *v19; // rdx\n __int64 v20; // r12\n __int64 v21; // rsi\n __int64 v22; // r14\n int v23; // r13d\n __int64 v24; // rbx\n __int64 v25; // rax\n _DWORD *v26; // r10\n int v27; // r11d\n __int64 v28; // rcx\n _BYTE *v29; // rdi\n _BYTE *v30; // r8\n __int64 v31; // r9\n _BYTE v34[12]; // [rsp+8h] [rbp-D0h] BYREF\n int v35; // [rsp+14h] [rbp-C4h]\n unsigned __int64 v36; // [rsp+18h] [rbp-C0h]\n _BYTE *v37; // [rsp+20h] [rbp-B8h]\n __int64 v38; // [rsp+28h] [rbp-B0h]\n unsigned __int64 v39; // [rsp+30h] [rbp-A8h]\n __int64 v40; // [rsp+38h] [rbp-A0h]\n __int64 v41; // [rsp+40h] [rbp-98h]\n __int64 v42; // [rsp+48h] [rbp-90h]\n unsigned __int64 v43; // [rsp+50h] [rbp-88h]\n unsigned __int64 v44; // [rsp+58h] [rbp-80h]\n _BYTE *v45; // [rsp+60h] [rbp-78h]\n unsigned __int64 v46; // [rsp+68h] [rbp-70h]\n unsigned __int64 v47; // [rsp+70h] [rbp-68h]\n __int64 v48; // [rsp+78h] [rbp-60h]\n int v49; // [rsp+80h] [rbp-58h]\n int v50; // [rsp+84h] [rbp-54h]\n int v51; // [rsp+88h] [rbp-50h]\n int v52; // [rsp+8Ch] [rbp-4Ch]\n unsigned __int64 v53; // [rsp+90h] [rbp-48h]\n unsigned __int64 v54; // [rsp+A0h] [rbp-38h]\n\n v48 = a3;\n v49 = a5;\n v9 = a6;\n v54 = __readfsqword(0x28u);\n v10 = a6 + 1;\n v11 = 4 * v10;\n v12 = v10 * (a5 + 1);\n v13 = 4 * v12;\n v14 = 4 * (a4 + 1) * v12 + 15;\n v15 = (4 * (a4 + 1) * v12 + 15) & 0xFFF0;\n while ( v34 != &v34[-(v14 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v16 = v15 & 0xFFF;\n v17 = alloca(v16);\n if ( (v15 & 0xFFF) != 0 )\n *(_QWORD *)&v34[v16 - 8] = *(_QWORD *)&v34[v16 - 8];\n v45 = v34;\n if ( a4 >= 0 )\n {\n v18 = v13 >> 2;\n v47 = v11 >> 2;\n v19 = (_BYTE *)(a1 - 1);\n v38 = (unsigned int)(a4 + 1);\n v37 = &v34[-v11];\n v40 = -1LL;\n v41 = 0LL;\n v42 = 0LL;\n v20 = 0LL;\n v21 = (unsigned int)(a6 + 1);\n v36 = v13;\n v35 = a4;\n v22 = a2;\n v23 = a6;\n v24 = (unsigned int)(v49 + 1);\n do\n {\n if ( v49 >= 0 )\n {\n v29 = &v45[4 * v42];\n v30 = &v37[4 * v41];\n v31 = v18 * (v40 - v20);\n v28 = 0LL;\n v44 = v18 * (int)v20;\n v43 = v18 * ((int)v20 - 1);\n v39 = v18;\n do\n {\n v50 = v28;\n v51 = v28;\n v26 = &v30[v11];\n v25 = 0LL;\n if ( v23 >= 0 )\n {\n v53 = v11;\n v52 = v23;\n do\n {\n if ( (_DWORD)v20 == 0 || (_DWORD)v28 == 0 || !(_DWORD)v25 )\n {\n *(_DWORD *)&v29[4 * v25] = 0;\n }\n else if ( *v19 == *(_BYTE *)(v22 + v28 - 1) && *v19 == *(_BYTE *)(v48 + v25 - 1) )\n {\n v46 = v44 + (int)v25 + v47 * v51;\n *(_DWORD *)&v45[4 * v46] = *(_DWORD *)&v45[4 * v47 * (v50 - 1) - 4 + 4 * v43 + 4 * (int)v25] + 1;\n }\n else\n {\n v27 = *(v26 - 1);\n if ( v26[v31] >= v27 )\n v27 = v26[v31];\n if ( v27 < *(_DWORD *)&v30[4 * v25] )\n v27 = *(_DWORD *)&v30[4 * v25];\n *v26 = v27;\n }\n ++v25;\n ++v26;\n }\n while ( v25 != v21 );\n v11 = v53;\n v23 = v52;\n }\n ++v28;\n v29 += v11;\n v30 += v11;\n }\n while ( v28 != v24 );\n v18 = v39;\n }\n ++v20;\n v42 += v18;\n v41 += v18;\n ++v40;\n ++v19;\n }\n while ( v20 != v38 );\n v13 = v36;\n a4 = v35;\n v9 = v23;\n }\n return *(unsigned int *)&v45[4 * (v11 >> 2) * v49 + 4 * a4 * (v13 >> 2) + 4 * v9];\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 0A8h\nmov rax, rdi\nmov r13, rsi\nmov [rbp+var_60], rdx\nmov r14d, ecx\nmov [rbp+var_58], r8d\nmov ebx, r9d\nmov rcx, fs:28h\nmov [rbp+var_38], rcx\nxor ecx, ecx\nlea ecx, [r9+1]\nmovsxd rcx, ecx\nlea r11, ds:0[rcx*4]\nlea esi, [r8+1]\nmovsxd rsi, esi\nimul rsi, rcx\nlea rcx, ds:0[rsi*4]\nlea edi, [r14+1]\nmovsxd rdi, edi\nimul rsi, rdi\nlea rdi, ds:0Fh[rsi*4]\nmov rsi, rdi\nand rsi, 0FFFFFFFFFFFFFFF0h\nand rdi, 0FFFFFFFFFFFFF000h\nmov r8, rsp\nsub r8, rdi\nloc_120D:\ncmp rsp, r8\njz short loc_1224\nsub rsp, 1000h\nor [rsp+10D0h+var_D8], 0\njmp short loc_120D\nloc_1224:\nmov rdi, rsi\nand edi, 0FFFh\nsub rsp, rdi\ntest rdi, rdi\njz short loc_123B\nor [rsp+rdi+0D0h+var_D8], 0\nloc_123B:\nmov rdi, rsp\nmov [rbp+var_78], rdi\ntest r14d, r14d\njs loc_1465\nmov r10, rcx\nshr r10, 2\nmov rdx, r11\nshr rdx, 2\nmov [rbp+var_68], rdx\nlea rdx, [rax-1]\nlea eax, [r14+1]\nmov [rbp+var_B0], rax\nsub rdi, r11\nmov [rbp+var_B8], rdi\nmov [rbp+var_A0], 0FFFFFFFFFFFFFFFFh\nmov [rbp+var_98], 0\nmov [rbp+var_90], 0\nmov r12d, 0\nmov eax, [rbp+var_58]\nlea r15d, [rax+1]\nlea esi, [rbx+1]\nmov [rbp+var_C0], rcx\nmov [rbp+var_C4], r14d\nmov r14, r13\nmov r13d, ebx\nmov rbx, r15\njmp loc_13EC\nloc_12C3:\nmov dword ptr [rdi+rax*4], 0\nloc_12CA:\nadd rax, 1\nadd r10, 4\ncmp rax, rsi\njz loc_1380\nloc_12DB:\ntest r12d, r12d\nsetz bl\ntest ecx, ecx\nsetz r11b\nor r11b, bl\njnz short loc_12C3\ntest eax, eax\njz short loc_12C3\nmovzx r11d, byte ptr [rdx]\ncmp r11b, [r14+rcx-1]\njz short loc_131A\nloc_12FB:\nmov ebx, [r10+r9*4]\nmov r11d, [r10-4]\ncmp ebx, r11d\ncmovge r11d, ebx\nmov ebx, [r8+rax*4]\ncmp r11d, ebx\ncmovl r11d, ebx\nmov [r10], r11d\njmp short loc_12CA\nloc_131A:\nmov rbx, [rbp+var_60]\ncmp r11b, [rbx+rax-1]\njnz short loc_12FB\nmovsxd r11, eax\nmovsxd rbx, [rbp+var_50]\nmov r13, [rbp+var_68]\nimul rbx, r13\nmov r13, [rbp+var_80]\nadd r11, r13\nadd rbx, r11\nmov [rbp+var_70], rbx\nlea r11d, [rax-1]\nmovsxd r11, r11d\nmov ebx, [rbp+var_54]\nsub ebx, 1\nmovsxd rbx, ebx\nmov r13, [rbp+var_68]\nimul rbx, r13\nmov r13, [rbp+var_88]\nadd r11, r13\nadd r11, rbx\nmov rbx, [rbp+var_78]\nmov r11d, [rbx+r11*4]\nadd r11d, 1\nmov r13, [rbp+var_70]\nmov [rbx+r13*4], r11d\njmp loc_12CA\nloc_1380:\nmov r11, [rbp+var_48]\nmov r13d, [rbp+var_4C]\nloc_1388:\nadd rcx, 1\nadd rdi, r11\nadd r8, r11\ncmp rcx, r15\njz short loc_13B8\nloc_1397:\nmov [rbp+var_54], ecx\nmov [rbp+var_50], ecx\nlea r10, [r11+r8]\nmov eax, 0\ntest r13d, r13d\njs short loc_1388\nmov [rbp+var_48], r11\nmov [rbp+var_4C], r13d\njmp loc_12DB\nloc_13B8:\nmov r10, [rbp+var_A8]\nmov rbx, r15\nloc_13C2:\nadd r12, 1\nadd [rbp+var_90], r10\nadd [rbp+var_98], r10\nadd [rbp+var_A0], 1\nadd rdx, 1\nmov rax, [rbp+var_B0]\ncmp r12, rax\njz short loc_1454\nloc_13EC:\nmov eax, r12d\ncmp [rbp+var_58], 0\njs short loc_13C2\nmov rdi, [rbp+var_78]\nmov rcx, [rbp+var_90]\nlea rdi, [rdi+rcx*4]\nmov rcx, [rbp+var_B8]\nmov r9, [rbp+var_98]\nlea r8, [rcx+r9*4]\nmov r9, [rbp+var_A0]\nsub r9, r12\nimul r9, r10\nmov ecx, 0\ncdqe\nimul rax, r10\nmov [rbp+var_80], rax\nlea eax, [r12-1]\ncdqe\nimul rax, r10\nmov [rbp+var_88], rax\nmov [rbp+var_A8], r10\nmov r15, rbx\njmp loc_1397\nloc_1454:\nmov rcx, [rbp+var_C0]\nmov r14d, [rbp+var_C4]\nmov ebx, r13d\nloc_1465:\nmovsxd rax, ebx\nmovsxd rdx, r14d\nshr rcx, 2\nimul rcx, rdx\nmovsxd rdx, [rbp+var_58]\nshr r11, 2\nimul rdx, r11\nadd rax, rcx\nadd rax, rdx\nmov rdx, [rbp+var_78]\nmov eax, [rdx+rax*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_14AA\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_14AA:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, __int64 a2, __int64 a3, int a4, int a5, int a6)\n{\n int v9; // ebx\n __int64 v10; // rcx\n unsigned __int64 v11; // r11\n __int64 v12; // rsi\n unsigned __int64 v13; // rcx\n __int64 v14; // rdi\n __int16 v15; // si\n signed __int64 v16; // rdi\n void *v17; // rsp\n unsigned __int64 v18; // r10\n _BYTE *v19; // rdx\n __int64 v20; // r12\n __int64 v21; // rsi\n __int64 v22; // r14\n int v23; // r13d\n __int64 v24; // rbx\n __int64 v25; // rax\n _DWORD *v26; // r10\n int v27; // r11d\n __int64 v28; // rcx\n _BYTE *v29; // rdi\n _BYTE *v30; // r8\n __int64 v31; // r9\n _BYTE v34[12]; // [rsp+8h] [rbp-D0h] BYREF\n int v35; // [rsp+14h] [rbp-C4h]\n unsigned __int64 v36; // [rsp+18h] [rbp-C0h]\n _BYTE *v37; // [rsp+20h] [rbp-B8h]\n __int64 v38; // [rsp+28h] [rbp-B0h]\n unsigned __int64 v39; // [rsp+30h] [rbp-A8h]\n __int64 v40; // [rsp+38h] [rbp-A0h]\n __int64 v41; // [rsp+40h] [rbp-98h]\n __int64 v42; // [rsp+48h] [rbp-90h]\n unsigned __int64 v43; // [rsp+50h] [rbp-88h]\n unsigned __int64 v44; // [rsp+58h] [rbp-80h]\n _BYTE *v45; // [rsp+60h] [rbp-78h]\n unsigned __int64 v46; // [rsp+68h] [rbp-70h]\n unsigned __int64 v47; // [rsp+70h] [rbp-68h]\n __int64 v48; // [rsp+78h] [rbp-60h]\n int v49; // [rsp+80h] [rbp-58h]\n int v50; // [rsp+84h] [rbp-54h]\n int v51; // [rsp+88h] [rbp-50h]\n int v52; // [rsp+8Ch] [rbp-4Ch]\n unsigned __int64 v53; // [rsp+90h] [rbp-48h]\n unsigned __int64 v54; // [rsp+A0h] [rbp-38h]\n\n v48 = a3;\n v49 = a5;\n v9 = a6;\n v54 = __readfsqword(0x28u);\n v10 = a6 + 1;\n v11 = 4 * v10;\n v12 = v10 * (a5 + 1);\n v13 = 4 * v12;\n v14 = 4 * (a4 + 1) * v12 + 15;\n v15 = (4 * (a4 + 1) * v12 + 15) & 0xFFF0;\n while ( v34 != &v34[-(v14 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v16 = v15 & 0xFFF;\n v17 = alloca(v16);\n if ( (v15 & 0xFFF) != 0 )\n *(_QWORD *)&v34[v16 - 8] = *(_QWORD *)&v34[v16 - 8];\n v45 = v34;\n if ( a4 >= 0 )\n {\n v18 = v13 >> 2;\n v47 = v11 >> 2;\n v19 = (_BYTE *)(a1 - 1);\n v38 = (unsigned int)(a4 + 1);\n v37 = &v34[-v11];\n v40 = -1LL;\n v41 = 0LL;\n v42 = 0LL;\n v20 = 0LL;\n v21 = (unsigned int)(a6 + 1);\n v36 = v13;\n v35 = a4;\n v22 = a2;\n v23 = a6;\n v24 = (unsigned int)(v49 + 1);\n do\n {\n if ( v49 >= 0 )\n {\n v29 = &v45[4 * v42];\n v30 = &v37[4 * v41];\n v31 = v18 * (v40 - v20);\n v28 = 0LL;\n v44 = v18 * (int)v20;\n v43 = v18 * ((int)v20 - 1);\n v39 = v18;\n do\n {\n v50 = v28;\n v51 = v28;\n v26 = &v30[v11];\n v25 = 0LL;\n if ( v23 >= 0 )\n {\n v53 = v11;\n v52 = v23;\n do\n {\n if ( (_DWORD)v20 == 0 || (_DWORD)v28 == 0 || !(_DWORD)v25 )\n {\n *(_DWORD *)&v29[4 * v25] = 0;\n }\n else if ( *v19 == *(_BYTE *)(v22 + v28 - 1) && *v19 == *(_BYTE *)(v48 + v25 - 1) )\n {\n v46 = v44 + (int)v25 + v47 * v51;\n *(_DWORD *)&v45[4 * v46] = *(_DWORD *)&v45[4 * v47 * (v50 - 1) - 4 + 4 * v43 + 4 * (int)v25] + 1;\n }\n else\n {\n v27 = *(v26 - 1);\n if ( v26[v31] >= v27 )\n v27 = v26[v31];\n if ( v27 < *(_DWORD *)&v30[4 * v25] )\n v27 = *(_DWORD *)&v30[4 * v25];\n *v26 = v27;\n }\n ++v25;\n ++v26;\n }\n while ( v25 != v21 );\n v11 = v53;\n v23 = v52;\n }\n ++v28;\n v29 += v11;\n v30 += v11;\n }\n while ( v28 != v24 );\n v18 = v39;\n }\n ++v20;\n v42 += v18;\n v41 += v18;\n ++v40;\n ++v19;\n }\n while ( v20 != v38 );\n v13 = v36;\n a4 = v35;\n v9 = v23;\n }\n return *(unsigned int *)&v45[4 * (v11 >> 2) * v49 + 4 * a4 * (v13 >> 2) + 4 * v9];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, long long a2, long long a3, int a4, int a5,\n int a6) {\n int v9;\n long long v10;\n unsigned long long v11;\n long long v12;\n unsigned long long v13;\n long long v14;\n short v15;\n signed long long v16;\n void *v17;\n unsigned long long v18;\n uint8_t *v19;\n long long v20;\n long long v21;\n long long v22;\n int v23;\n long long v24;\n long long v25;\n uint32_t *v26;\n int v27;\n long long v28;\n uint8_t *v29;\n uint8_t *v30;\n long long v31;\n uint8_t v34[12];\n int v35;\n unsigned long long v36;\n uint8_t *v37;\n long long v38;\n unsigned long long v39;\n long long v40;\n long long v41;\n long long v42;\n unsigned long long v43;\n unsigned long long v44;\n uint8_t *v45;\n unsigned long long v46;\n unsigned long long v47;\n long long v48;\n int v49;\n int v50;\n int v51;\n int v52;\n unsigned long long v53;\n unsigned long long v54;\n v48 = a3;\n v49 = a5;\n v9 = a6;\n v54 = __readfsqword(40u);\n v10 = a6 + 1;\n v11 = 4 * v10;\n v12 = v10 * (a5 + 1);\n v13 = 4 * v12;\n v14 = 4 * (a4 + 1) * v12 + 15;\n v15 = (4 * (a4 + 1) * v12 + 15) & 65520;\n while (v34 != &v34[-(v14 & 18446744073709547520LL)])\n ;\n v16 = v15 & 4095;\n v17 = alloca(v16);\n if ((v15 & 4095) != 0)\n *(uint64_t *)&v34[v16 - 8] = *(uint64_t *)&v34[v16 - 8];\n v45 = v34;\n if (a4 >= 0) {\n v18 = v13 >> 2;\n v47 = v11 >> 2;\n v19 = (uint8_t *)(a1 - 1);\n v38 = (unsigned int)(a4 + 1);\n v37 = &v34[-v11];\n v40 = -1LL;\n v41 = 0LL;\n v42 = 0LL;\n v20 = 0LL;\n v21 = (unsigned int)(a6 + 1);\n v36 = v13;\n v35 = a4;\n v22 = a2;\n v23 = a6;\n v24 = (unsigned int)(v49 + 1);\n do {\n if (v49 >= 0) {\n v29 = &v45[4 * v42];\n v30 = &v37[4 * v41];\n v31 = v18 * (v40 - v20);\n v28 = 0LL;\n v44 = v18 * (int)v20;\n v43 = v18 * ((int)v20 - 1);\n v39 = v18;\n do {\n v50 = v28;\n v51 = v28;\n v26 = &v30[v11];\n v25 = 0LL;\n if (v23 >= 0) {\n v53 = v11;\n v52 = v23;\n do {\n if ((uint32_t)v20 == 0 || (uint32_t)v28 == 0 || !(uint32_t)v25) {\n *(uint32_t *)&v29[4 * v25] = 0;\n } else if (*v19 == *(uint8_t *)(v22 + v28 - 1) &&\n *v19 == *(uint8_t *)(v48 + v25 - 1)) {\n v46 = v44 + (int)v25 + v47 * v51;\n *(uint32_t *)&v45[4 * v46] =\n *(uint32_t *)&v45[4 * v47 * (v50 - 1) - 4 + 4 * v43 +\n 4 * (int)v25] +\n 1;\n } else {\n v27 = *(v26 - 1);\n if (v26[v31] >= v27) v27 = v26[v31];\n if (v27 < *(uint32_t *)&v30[4 * v25])\n v27 = *(uint32_t *)&v30[4 * v25];\n *v26 = v27;\n }\n ++v25;\n ++v26;\n } while (v25 != v21);\n v11 = v53;\n v23 = v52;\n }\n ++v28;\n v29 += v11;\n v30 += v11;\n } while (v28 != v24);\n v18 = v39;\n }\n ++v20;\n v42 += v18;\n v41 += v18;\n ++v40;\n ++v19;\n } while (v20 != v38);\n v13 = v36;\n a4 = v35;\n v9 = v23;\n }\n return *(\n unsigned int *)&v45[4 * (v11 >> 2) * v49 + 4 * a4 * (v13 >> 2) + 4 * v9];\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, long long a3, int a4, int a5,\n int a6) {\n int v9;\n long long v10;\n unsigned long long v11;\n long long v12;\n unsigned long long v13;\n long long v14;\n short v15;\n signed long long v16;\n void *v17;\n unsigned long long v18;\n uint8_t *v19;\n long long v20;\n long long v21;\n long long v22;\n int v23;\n long long v24;\n long long v25;\n uint32_t *v26;\n int v27;\n long long v28;\n uint8_t *v29;\n uint8_t *v30;\n long long v31;\n uint8_t v34[12];\n int v35;\n unsigned long long v36;\n uint8_t *v37;\n long long v38;\n unsigned long long v39;\n long long v40;\n long long v41;\n long long v42;\n unsigned long long v43;\n unsigned long long v44;\n uint8_t *v45;\n unsigned long long v46;\n unsigned long long v47;\n long long v48;\n int v49;\n int v50;\n int v51;\n int v52;\n unsigned long long v53;\n unsigned long long v54;\n v48 = a3;\n v49 = a5;\n v9 = a6;\n v54 = __readfsqword(40u);\n v10 = a6 + 1;\n v11 = 4 * v10;\n v12 = v10 * (a5 + 1);\n v13 = 4 * v12;\n v14 = 4 * (a4 + 1) * v12 + 15;\n v15 = (4 * (a4 + 1) * v12 + 15) & 65520;\n while (v34 != &v34[-(v14 & 18446744073709547520LL)])\n ;\n v16 = v15 & 4095;\n v17 = alloca(v16);\n if ((v15 & 4095) != 0)\n *(uint64_t *)&v34[v16 - 8] = *(uint64_t *)&v34[v16 - 8];\n v45 = v34;\n if (a4 >= 0) {\n v18 = v13 >> 2;\n v47 = v11 >> 2;\n v19 = (uint8_t *)(a1 - 1);\n v38 = (unsigned int)(a4 + 1);\n v37 = &v34[-v11];\n v40 = -1LL;\n v41 = 0LL;\n v42 = 0LL;\n v20 = 0LL;\n v21 = (unsigned int)(a6 + 1);\n v36 = v13;\n v35 = a4;\n v22 = a2;\n v23 = a6;\n v24 = (unsigned int)(v49 + 1);\n do {\n if (v49 >= 0) {\n v29 = &v45[4 * v42];\n v30 = &v37[4 * v41];\n v31 = v18 * (v40 - v20);\n v28 = 0LL;\n v44 = v18 * (int)v20;\n v43 = v18 * ((int)v20 - 1);\n v39 = v18;\n do {\n v50 = v28;\n v51 = v28;\n v26 = &v30[v11];\n v25 = 0LL;\n if (v23 >= 0) {\n v53 = v11;\n v52 = v23;\n do {\n if ((uint32_t)v20 == 0 || (uint32_t)v28 == 0 || !(uint32_t)v25) {\n *(uint32_t *)&v29[4 * v25] = 0;\n } else if (*v19 == *(uint8_t *)(v22 + v28 - 1) &&\n *v19 == *(uint8_t *)(v48 + v25 - 1)) {\n v46 = v44 + (int)v25 + v47 * v51;\n *(uint32_t *)&v45[4 * v46] =\n *(uint32_t *)&v45[4 * v47 * (v50 - 1) - 4 + 4 * v43 +\n 4 * (int)v25] +\n 1;\n } else {\n v27 = *(v26 - 1);\n if (v26[v31] >= v27) v27 = v26[v31];\n if (v27 < *(uint32_t *)&v30[4 * v25])\n v27 = *(uint32_t *)&v30[4 * v25];\n *v26 = v27;\n }\n ++v25;\n ++v26;\n } while (v25 != v21);\n v11 = v53;\n v23 = v52;\n }\n ++v28;\n v29 += v11;\n v30 += v11;\n } while (v28 != v24);\n v18 = v39;\n }\n ++v20;\n v42 += v18;\n v41 += v18;\n ++v40;\n ++v19;\n } while (v20 != v38);\n v13 = v36;\n a4 = v35;\n v9 = v23;\n }\n return *(\n unsigned int *)&v45[4 * (v11 >> 2) * v49 + 4 * a4 * (v13 >> 2) + 4 * v9];\n}" + }, + { + "index": 747, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char* X, char* Y, char* Z, int m, int n, int o) {\n int L[m + 1][n + 1][o + 1];\n int i, j, k;\n for (i = 0; i <= m; i++) {\n for (j = 0; j <= n; j++) {\n for (k = 0; k <= o; k++) {\n if (i == 0 || j == 0 || k == 0) {\n L[i][j][k] = 0;\n } else if (X[i - 1] == Y[j - 1] && X[i - 1] == Z[k - 1]) {\n L[i][j][k] = L[i - 1][j - 1][k - 1] + 1;\n } else {\n int max1 =\n L[i - 1][j][k] > L[i][j - 1][k] ? L[i - 1][j][k] : L[i][j - 1][k];\n L[i][j][k] = max1 > L[i][j][k - 1] ? max1 : L[i][j][k - 1];\n }\n }\n }\n }\n return L[m][n][o];\n}", + "test": "int main() {\n\n\t// Testing the implementation with assertions\n\n\tassert(func0(\"AGGT12\", \"12TXAYB\", \"12XBA\", 6, 7, 5) == 2);\n\n\tassert(func0(\"Reels\", \"Reelsfor\", \"ReelsforReels\", 5, 8, 13) == 5);\n\n\tassert(func0(\"abcd1e2\", \"bc12ea\", \"bd1ea\", 7, 6, 5) == 3);\n\n\n\n\tprintf(\"All tests passed!\\n\");\n\n\treturn 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\nmov %r9d,%r15d\npush %r14\npush %r13\nmov %rdi,%r13\npush %r12\npush %rbx\nmov %rsi,%rbx\nsub $0x78,%rsp\nmov %rdx,-0x60(%rbp)\nmov %ecx,%edx\nlea 0x1(%r8),%ecx\nmov %r8d,-0x7c(%rbp)\nmovslq %ecx,%rcx\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nlea 0x1(%r9),%eax\ncltq\nlea 0x0(,%rax,4),%rdi\nimul %rcx,%rax\nlea 0x1(%rdx),%ecx\nmov %rdi,-0x50(%rbp)\nmov %rsp,%rdi\nmovslq %ecx,%rcx\nimul %rax,%rcx\nlea 0xf(,%rcx,4),%rsi\nmov %rsi,%rcx\nand $0xfffffffffffff000,%rsi\nsub %rsi,%rdi\nand $0xfffffffffffffff0,%rcx\nmov %rdi,%rsi\ncmp %rsi,%rsp\nje 1337 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rsi,%rsp\njne 1322 \nand $0xfff,%ecx\nsub %rcx,%rsp\ntest %rcx,%rcx\njne 1521 \nshl $0x2,%rax\nmov %rsp,-0x90(%rbp)\nshr $0x2,%rax\nmov %rax,-0x68(%rbp)\nmov -0x50(%rbp),%rax\nshr $0x2,%rax\nmov %rax,-0x98(%rbp)\ntest %edx,%edx\njs 14c6 \nmovslq %edx,%rax\nsub $0x1,%r13\nxor %r14d,%r14d\nmovslq %r15d,%rdi\nmov %rax,-0x88(%rbp)\nmov -0x98(%rbp),%rax\nmovq $0x0,-0x78(%rbp)\nneg %rax\nmovq $0xffffffffffffffff,-0x70(%rbp)\nshl $0x2,%rax\nmov %rax,-0x58(%rbp)\nmovslq -0x7c(%rbp),%rax\nmov %rax,-0x48(%rbp)\nnopl 0x0(%rax)\nmov -0x7c(%rbp),%eax\ntest %eax,%eax\njs 14a0 \nmov -0x70(%rbp),%r12\nmov -0x90(%rbp),%rax\nxor %r10d,%r10d\nmov -0x78(%rbp),%rcx\nsub %r14,%r12\nimul -0x68(%rbp),%r12\nlea (%rax,%rcx,4),%r11\nnopl 0x0(%rax)\ntest %r15d,%r15d\njs 1460 \ntest %r14d,%r14d\nmov %r11,%rdx\nsete %r8b\ntest %r10d,%r10d\nsete %al\nor %eax,%r8d\nmov -0x58(%rbp),%rax\nlea (%r11,%rax,1),%rcx\nxor %eax,%eax\njmp 144b \nnopl 0x0(%rax)\ntest %r8b,%r8b\njne 144f \nmovzbl 0x0(%r13),%esi\ncmp -0x1(%rbx,%r10,1),%sil\nje 1480 \nmov (%rdx,%r12,4),%esi\nmov -0x4(%rdx),%r9d\ncmp %esi,(%rcx)\ncmovge (%rcx),%esi\ncmp %r9d,%esi\ncmovl %r9d,%esi\nmov %esi,(%rdx)\nlea 0x1(%rax),%rsi\nadd $0x4,%rdx\nadd $0x4,%rcx\ncmp %rax,%rdi\nje 1460 \nmov %rsi,%rax\ntest %eax,%eax\njne 1410 \nmovl $0x0,(%rdx)\njmp 1437 \nnopw 0x0(%rax,%rax,1)\nlea 0x1(%r10),%rax\nadd -0x50(%rbp),%r11\ncmp -0x48(%rbp),%r10\nje 14a0 \nmov %rax,%r10\njmpq 13e8 \nnopw %cs:0x0(%rax,%rax,1)\nmov -0x60(%rbp),%r9\ncmp -0x1(%r9,%rax,1),%sil\njne 1421 \nmov -0x4(%rcx,%r12,4),%esi\nadd $0x1,%esi\nmov %esi,(%rdx)\njmp 1437 \nnopw 0x0(%rax,%rax,1)\nmov -0x68(%rbp),%rdx\nlea 0x1(%r14),%rax\nadd %rdx,-0x78(%rbp)\nadd $0x1,%r13\naddq $0x1,-0x70(%rbp)\ncmp -0x88(%rbp),%r14\nje 14db \nmov %rax,%r14\njmpq 13b8 \nmovslq %edx,%rax\nmovslq %r15d,%rdi\nmov %rax,-0x88(%rbp)\nmovslq -0x7c(%rbp),%rax\nmov %rax,-0x48(%rbp)\nmov -0x88(%rbp),%rax\nimul -0x68(%rbp),%rax\nmov -0x48(%rbp),%rdx\nimul -0x98(%rbp),%rdx\nmov -0x90(%rbp),%rbx\nadd %rdi,%rax\nadd %rdx,%rax\nmov (%rbx,%rax,4),%eax\nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\njne 152c \nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\norq $0x0,-0x8(%rsp,%rcx,1)\njmpq 1349 \ncallq 1080 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov r11, rsi\nmov esi, r9d\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nmov rbx, rdi\nlea edi, [r9+1]\nmovsxd rdi, edi\nsub rsp, 68h\nmov [rbp+var_58], rdx\nlea rdx, ds:0[rdi*4]\nmov r10, rsp\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nlea eax, [r8+1]\ncdqe\nimul rax, rdi\nlea edi, [rcx+1]\nmovsxd rdi, edi\nimul rdi, rax\nlea r9, ds:0Fh[rdi*4]\nmov rdi, r9\nand r9, 0FFFFFFFFFFFFF000h\nsub r10, r9\nand rdi, 0FFFFFFFFFFFFFFF0h\ncmp rsp, r10\njz short loc_132A\nloc_1315:\nsub rsp, 1000h\nor [rsp+1090h+var_98], 0\ncmp rsp, r10\njnz short loc_1315\nloc_132A:\nand edi, 0FFFh\nsub rsp, rdi\ntest rdi, rdi\njnz loc_14F9\nloc_133C:\nshl rax, 2\nmov [rbp+var_80], rsp\nmovsxd r15, ecx\nmovsxd rdi, esi\nshr rax, 2\nmovsxd r14, r8d\nmov [rbp+var_78], rax\nmov rax, rdx\nshr rax, 2\ntest ecx, ecx\njs loc_14C1\nmovsxd r15, ecx\nmov rcx, rax\nmov r12, [rbp+var_78]\nsub rbx, 1\nneg rcx\nmov [rbp+var_88], rax\nxor r13d, r13d\nmovsxd r14, r8d\nlea rdi, ds:0[rcx*4]\nneg r12\nxor ecx, ecx\nmov [rbp+var_50], rdi\nmovsxd rdi, esi\nnop word ptr [rax+rax+00000000h]\nloc_13A0:\ntest r8d, r8d\njs loc_148A\nmov rax, [rbp+var_80]\nxor r9d, r9d\nlea r10, [rax+rcx*4]\nloc_13B4:\ntest esi, esi\njs loc_14A6\nmov [rbp+var_48], rdx\nmov [rbp+var_60], rcx\nmov [rbp+var_64], r8d\nmov [rbp+var_68], esi\nmov [rbp+var_70], r15\nnop\nloc_13D0:\ntest r9d, r9d\nmov rcx, r10\nsetz r8b\ntest r13d, r13d\nsetz al\nor r8d, eax\nmov rax, [rbp+var_50]\nlea rsi, [r10+rax]\nxor eax, eax\njmp short loc_142E\nloc_13F0:\ntest r8b, r8b\njnz short loc_1432\nmovzx edx, byte ptr [rbx]\ncmp dl, [r11+r9-1]\njz short loc_1460\nloc_13FF:\nmov r15d, [rsi]\nmov edx, [rcx+r12*4]\ncmp r15d, edx\ncmovge edx, r15d\nmov r15d, [rcx-4]\ncmp edx, r15d\ncmovl edx, r15d\nloc_1418:\nmov [rcx], edx\nadd rsi, 4\nlea rdx, [rax+1]\nadd rcx, 4\ncmp rax, rdi\njz short loc_1440\nmov rax, rdx\nloc_142E:\ntest eax, eax\njnz short loc_13F0\nloc_1432:\nxor edx, edx\njmp short loc_1418\nloc_1440:\nmov rsi, [rbp+var_48]\nlea rax, [r9+1]\nadd r10, rsi\ncmp r9, r14\njz short loc_1478\nmov r9, rax\njmp loc_13D0\nloc_1460:\nmov r15, [rbp+var_58]\ncmp dl, [r15+rax-1]\njnz short loc_13FF\nmov edx, [rsi+r12*4-4]\nadd edx, 1\njmp short loc_1418\nloc_1478:\nmov rdx, rsi\nmov rcx, [rbp+var_60]\nmov r8d, [rbp+var_64]\nmov esi, [rbp+var_68]\nmov r15, [rbp+var_70]\nloc_148A:\nmov r10, [rbp+var_78]\nlea rax, [r13+1]\nadd rbx, 1\nadd rcx, r10\ncmp r13, r15\njz short loc_14BA\nmov r13, rax\njmp loc_13A0\nloc_14A6:\nlea rax, [r9+1]\nadd r10, rdx\ncmp r9, r14\njz short loc_148A\nmov r9, rax\njmp loc_13B4\nloc_14BA:\nmov rax, [rbp+var_88]\nloc_14C1:\nmov rbx, [rbp+var_78]\nimul r14, rax\nimul r15, rbx\nmov rbx, [rbp+var_80]\nlea rax, [rdi+r15]\nadd rax, r14\nmov eax, [rbx+rax*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_1504\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_14F9:\nor [rsp+rdi+1090h+var_1098], 0\njmp loc_133C\nloc_1504:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, __int64 a3, int a4, int a5, int a6)\n{\n int v7; // esi\n __int64 v9; // rdi\n unsigned __int64 v10; // rdx\n __int64 v11; // rax\n __int64 v12; // rdi\n __int64 *v13; // r10\n __int16 v14; // di\n signed __int64 v15; // rdi\n void *v16; // rsp\n __int64 v17; // r15\n __int64 v18; // rdi\n __int64 v19; // r14\n unsigned __int64 v20; // rax\n _BYTE *v21; // rbx\n __int64 v22; // r13\n __int64 v23; // r12\n __int64 v24; // rcx\n __int64 v25; // r9\n int *v26; // r10\n int *v27; // rcx\n int *v28; // rsi\n __int64 i; // rax\n int v30; // edx\n _BYTE v33[4088]; // [rsp+8h] [rbp-1090h] BYREF\n __int64 v34; // [rsp+1008h] [rbp-90h] BYREF\n unsigned __int64 v35; // [rsp+1010h] [rbp-88h]\n _BYTE *v36; // [rsp+1018h] [rbp-80h]\n unsigned __int64 v37; // [rsp+1020h] [rbp-78h]\n __int64 v38; // [rsp+1028h] [rbp-70h]\n int v39; // [rsp+1030h] [rbp-68h]\n int v40; // [rsp+1034h] [rbp-64h]\n __int64 v41; // [rsp+1038h] [rbp-60h]\n __int64 v42; // [rsp+1040h] [rbp-58h]\n __int64 v43; // [rsp+1048h] [rbp-50h]\n unsigned __int64 v44; // [rsp+1050h] [rbp-48h]\n unsigned __int64 v45; // [rsp+1060h] [rbp-38h]\n\n v7 = a6;\n v9 = a6 + 1;\n v42 = a3;\n v10 = 4 * v9;\n v45 = __readfsqword(0x28u);\n v11 = v9 * (a5 + 1);\n v12 = 4 * v11 * (a4 + 1) + 15;\n v13 = (__int64 *)((char *)&v34 - (v12 & 0xFFFFFFFFFFFFF000LL));\n v14 = v12 & 0xFFF0;\n if ( &v34 != v13 )\n {\n while ( v33 != (_BYTE *)v13 )\n ;\n }\n v15 = v14 & 0xFFF;\n v16 = alloca(v15);\n if ( v15 )\n *(_QWORD *)&v33[v15 - 8] = *(_QWORD *)&v33[v15 - 8];\n v36 = v33;\n v17 = a4;\n v18 = a6;\n v19 = a5;\n v37 = (unsigned __int64)(4 * v11) >> 2;\n v20 = v10 >> 2;\n if ( a4 >= 0 )\n {\n v17 = a4;\n v21 = (_BYTE *)(a1 - 1);\n v35 = v10 >> 2;\n v22 = 0LL;\n v19 = a5;\n v23 = -(__int64)v37;\n v24 = 0LL;\n v43 = -4LL * v20;\n v18 = a6;\n while ( 1 )\n {\n if ( a5 >= 0 )\n {\n v25 = 0LL;\n v26 = (int *)&v36[4 * v24];\n while ( v7 < 0 )\n {\n v26 = (int *)((char *)v26 + v10);\n if ( v25 == v19 )\n goto LABEL_27;\n ++v25;\n }\n v44 = v10;\n v41 = v24;\n v40 = a5;\n v39 = v7;\n v38 = v17;\n while ( 1 )\n {\n v27 = v26;\n v28 = &v26[(unsigned __int64)v43 / 4];\n for ( i = 0LL; ; ++i )\n {\n if ( !(_DWORD)i || (_DWORD)v22 == 0 || (_DWORD)v25 == 0 )\n {\n v30 = 0;\n }\n else if ( *v21 == *(_BYTE *)(a2 + v25 - 1) && *v21 == *(_BYTE *)(v42 + i - 1) )\n {\n v30 = v28[v23 - 1] + 1;\n }\n else\n {\n v30 = v27[v23];\n if ( *v28 >= v30 )\n v30 = *v28;\n if ( v30 < *(v27 - 1) )\n v30 = *(v27 - 1);\n }\n *v27 = v30;\n ++v28;\n ++v27;\n if ( i == v18 )\n break;\n }\n v26 = (int *)((char *)v26 + v44);\n if ( v25 == v19 )\n break;\n ++v25;\n }\n v10 = v44;\n v24 = v41;\n a5 = v40;\n v7 = v39;\n v17 = v38;\n }\nLABEL_27:\n ++v21;\n v24 += v37;\n if ( v22 == v17 )\n break;\n ++v22;\n }\n v20 = v35;\n }\n return *(unsigned int *)&v36[4 * v20 * v19 + 4 * v18 + 4 * v37 * v17];\n}", + "ida_strip_asm": "sub_12A0:\nendbr64\npush rbp\nmov r11, rsi\nmov esi, r9d\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nmov rbx, rdi\nlea edi, [r9+1]\nmovsxd rdi, edi\nsub rsp, 68h\nmov [rbp+var_58], rdx\nlea rdx, ds:0[rdi*4]\nmov r10, rsp\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nlea eax, [r8+1]\ncdqe\nimul rax, rdi\nlea edi, [rcx+1]\nmovsxd rdi, edi\nimul rdi, rax\nlea r9, ds:0Fh[rdi*4]\nmov rdi, r9\nand r9, 0FFFFFFFFFFFFF000h\nsub r10, r9\nand rdi, 0FFFFFFFFFFFFFFF0h\ncmp rsp, r10\njz short loc_132A\nloc_1315:\nsub rsp, 1000h\nor [rsp+1090h+var_98], 0\ncmp rsp, r10\njnz short loc_1315\nloc_132A:\nand edi, 0FFFh\nsub rsp, rdi\ntest rdi, rdi\njnz loc_14F9\nloc_133C:\nshl rax, 2\nmov [rbp+var_80], rsp\nmovsxd r15, ecx\nmovsxd rdi, esi\nshr rax, 2\nmovsxd r14, r8d\nmov [rbp+var_78], rax\nmov rax, rdx\nshr rax, 2\ntest ecx, ecx\njs loc_14C1\nmovsxd r15, ecx\nmov rcx, rax\nmov r12, [rbp+var_78]\nsub rbx, 1\nneg rcx\nmov [rbp+var_88], rax\nxor r13d, r13d\nmovsxd r14, r8d\nlea rdi, ds:0[rcx*4]\nneg r12\nxor ecx, ecx\nmov [rbp+var_50], rdi\nmovsxd rdi, esi\nnop word ptr [rax+rax+00000000h]\nloc_13A0:\ntest r8d, r8d\njs loc_148A\nmov rax, [rbp+var_80]\nxor r9d, r9d\nlea r10, [rax+rcx*4]\nloc_13B4:\ntest esi, esi\njs loc_14A6\nmov [rbp+var_48], rdx\nmov [rbp+var_60], rcx\nmov [rbp+var_64], r8d\nmov [rbp+var_68], esi\nmov [rbp+var_70], r15\nnop\nloc_13D0:\ntest r9d, r9d\nmov rcx, r10\nsetz r8b\ntest r13d, r13d\nsetz al\nor r8d, eax\nmov rax, [rbp+var_50]\nlea rsi, [r10+rax]\nxor eax, eax\njmp short loc_142E\nloc_13F0:\ntest r8b, r8b\njnz short loc_1432\nmovzx edx, byte ptr [rbx]\ncmp dl, [r11+r9-1]\njz short loc_1460\nloc_13FF:\nmov r15d, [rsi]\nmov edx, [rcx+r12*4]\ncmp r15d, edx\ncmovge edx, r15d\nmov r15d, [rcx-4]\ncmp edx, r15d\ncmovl edx, r15d\nloc_1418:\nmov [rcx], edx\nadd rsi, 4\nlea rdx, [rax+1]\nadd rcx, 4\ncmp rax, rdi\njz short loc_1440\nmov rax, rdx\nloc_142E:\ntest eax, eax\njnz short loc_13F0\nloc_1432:\nxor edx, edx\njmp short loc_1418\nloc_1440:\nmov rsi, [rbp+var_48]\nlea rax, [r9+1]\nadd r10, rsi\ncmp r9, r14\njz short loc_1478\nmov r9, rax\njmp loc_13D0\nloc_1460:\nmov r15, [rbp+var_58]\ncmp dl, [r15+rax-1]\njnz short loc_13FF\nmov edx, [rsi+r12*4-4]\nadd edx, 1\njmp short loc_1418\nloc_1478:\nmov rdx, rsi\nmov rcx, [rbp+var_60]\nmov r8d, [rbp+var_64]\nmov esi, [rbp+var_68]\nmov r15, [rbp+var_70]\nloc_148A:\nmov r10, [rbp+var_78]\nlea rax, [r13+1]\nadd rbx, 1\nadd rcx, r10\ncmp r13, r15\njz short loc_14BA\nmov r13, rax\njmp loc_13A0\nloc_14A6:\nlea rax, [r9+1]\nadd r10, rdx\ncmp r9, r14\njz short loc_148A\nmov r9, rax\njmp loc_13B4\nloc_14BA:\nmov rax, [rbp+var_88]\nloc_14C1:\nmov rbx, [rbp+var_78]\nimul r14, rax\nimul r15, rbx\nmov rbx, [rbp+var_80]\nlea rax, [rdi+r15]\nadd rax, r14\nmov eax, [rbx+rax*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_1504\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_14F9:\nor [rsp+rdi+1090h+var_1098], 0\njmp loc_133C\nloc_1504:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12A0(__int64 a1, __int64 a2, __int64 a3, int a4, int a5, int a6)\n{\n int v7; // esi\n __int64 v9; // rdi\n unsigned __int64 v10; // rdx\n __int64 v11; // rax\n __int64 v12; // rdi\n __int64 *v13; // r10\n __int16 v14; // di\n signed __int64 v15; // rdi\n void *v16; // rsp\n __int64 v17; // r15\n __int64 v18; // rdi\n __int64 v19; // r14\n unsigned __int64 v20; // rax\n _BYTE *v21; // rbx\n __int64 v22; // r13\n __int64 v23; // r12\n __int64 v24; // rcx\n __int64 v25; // r9\n int *v26; // r10\n int *v27; // rcx\n int *v28; // rsi\n __int64 i; // rax\n int v30; // edx\n _BYTE v33[4088]; // [rsp+8h] [rbp-1090h] BYREF\n __int64 v34; // [rsp+1008h] [rbp-90h] BYREF\n unsigned __int64 v35; // [rsp+1010h] [rbp-88h]\n _BYTE *v36; // [rsp+1018h] [rbp-80h]\n unsigned __int64 v37; // [rsp+1020h] [rbp-78h]\n __int64 v38; // [rsp+1028h] [rbp-70h]\n int v39; // [rsp+1030h] [rbp-68h]\n int v40; // [rsp+1034h] [rbp-64h]\n __int64 v41; // [rsp+1038h] [rbp-60h]\n __int64 v42; // [rsp+1040h] [rbp-58h]\n __int64 v43; // [rsp+1048h] [rbp-50h]\n unsigned __int64 v44; // [rsp+1050h] [rbp-48h]\n unsigned __int64 v45; // [rsp+1060h] [rbp-38h]\n\n v7 = a6;\n v9 = a6 + 1;\n v42 = a3;\n v10 = 4 * v9;\n v45 = __readfsqword(0x28u);\n v11 = v9 * (a5 + 1);\n v12 = 4 * v11 * (a4 + 1) + 15;\n v13 = (__int64 *)((char *)&v34 - (v12 & 0xFFFFFFFFFFFFF000LL));\n v14 = v12 & 0xFFF0;\n if ( &v34 != v13 )\n {\n while ( v33 != (_BYTE *)v13 )\n ;\n }\n v15 = v14 & 0xFFF;\n v16 = alloca(v15);\n if ( v15 )\n *(_QWORD *)&v33[v15 - 8] = *(_QWORD *)&v33[v15 - 8];\n v36 = v33;\n v17 = a4;\n v18 = a6;\n v19 = a5;\n v37 = (unsigned __int64)(4 * v11) >> 2;\n v20 = v10 >> 2;\n if ( a4 >= 0 )\n {\n v17 = a4;\n v21 = (_BYTE *)(a1 - 1);\n v35 = v10 >> 2;\n v22 = 0LL;\n v19 = a5;\n v23 = -(__int64)v37;\n v24 = 0LL;\n v43 = -4LL * v20;\n v18 = a6;\n while ( 1 )\n {\n if ( a5 >= 0 )\n {\n v25 = 0LL;\n v26 = (int *)&v36[4 * v24];\n while ( v7 < 0 )\n {\n v26 = (int *)((char *)v26 + v10);\n if ( v25 == v19 )\n goto LABEL_27;\n ++v25;\n }\n v44 = v10;\n v41 = v24;\n v40 = a5;\n v39 = v7;\n v38 = v17;\n while ( 1 )\n {\n v27 = v26;\n v28 = &v26[(unsigned __int64)v43 / 4];\n for ( i = 0LL; ; ++i )\n {\n if ( !(_DWORD)i || (_DWORD)v22 == 0 || (_DWORD)v25 == 0 )\n {\n v30 = 0;\n }\n else if ( *v21 == *(_BYTE *)(a2 + v25 - 1) && *v21 == *(_BYTE *)(v42 + i - 1) )\n {\n v30 = v28[v23 - 1] + 1;\n }\n else\n {\n v30 = v27[v23];\n if ( *v28 >= v30 )\n v30 = *v28;\n if ( v30 < *(v27 - 1) )\n v30 = *(v27 - 1);\n }\n *v27 = v30;\n ++v28;\n ++v27;\n if ( i == v18 )\n break;\n }\n v26 = (int *)((char *)v26 + v44);\n if ( v25 == v19 )\n break;\n ++v25;\n }\n v10 = v44;\n v24 = v41;\n a5 = v40;\n v7 = v39;\n v17 = v38;\n }\nLABEL_27:\n ++v21;\n v24 += v37;\n if ( v22 == v17 )\n break;\n ++v22;\n }\n v20 = v35;\n }\n return *(unsigned int *)&v36[4 * v20 * v19 + 4 * v18 + 4 * v37 * v17];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12A0(long long a1, long long a2, long long a3, int a4, int a5,\n int a6) {\n int v7;\n long long v9;\n unsigned long long v10;\n long long v11;\n long long v12;\n long long *v13;\n short v14;\n signed long long v15;\n void *v16;\n long long v17;\n long long v18;\n long long v19;\n unsigned long long v20;\n uint8_t *v21;\n long long v22;\n long long v23;\n long long v24;\n long long v25;\n int *v26;\n int *v27;\n int *v28;\n long long i;\n int v30;\n uint8_t v33[4088];\n long long v34;\n unsigned long long v35;\n uint8_t *v36;\n unsigned long long v37;\n long long v38;\n int v39;\n int v40;\n long long v41;\n long long v42;\n long long v43;\n unsigned long long v44;\n unsigned long long v45;\n v7 = a6;\n v9 = a6 + 1;\n v42 = a3;\n v10 = 4 * v9;\n v45 = __readfsqword(40u);\n v11 = v9 * (a5 + 1);\n v12 = 4 * v11 * (a4 + 1) + 15;\n v13 = (long long *)((char *)&v34 - (v12 & 18446744073709547520LL));\n v14 = v12 & 65520;\n if (&v34 != v13) {\n while (v33 != (uint8_t *)v13)\n ;\n }\n v15 = v14 & 4095;\n v16 = alloca(v15);\n if (v15) *(uint64_t *)&v33[v15 - 8] = *(uint64_t *)&v33[v15 - 8];\n v36 = v33;\n v17 = a4;\n v18 = a6;\n v19 = a5;\n v37 = (unsigned long long)(4 * v11) >> 2;\n v20 = v10 >> 2;\n if (a4 >= 0) {\n v17 = a4;\n v21 = (uint8_t *)(a1 - 1);\n v35 = v10 >> 2;\n v22 = 0LL;\n v19 = a5;\n v23 = -(long long)v37;\n v24 = 0LL;\n v43 = -4LL * v20;\n v18 = a6;\n while (1) {\n if (a5 >= 0) {\n v25 = 0LL;\n v26 = (int *)&v36[4 * v24];\n while (v7 < 0) {\n v26 = (int *)((char *)v26 + v10);\n if (v25 == v19) goto LABEL_27;\n ++v25;\n }\n v44 = v10;\n v41 = v24;\n v40 = a5;\n v39 = v7;\n v38 = v17;\n while (1) {\n v27 = v26;\n v28 = &v26[(unsigned long long)v43 / 4];\n for (i = 0LL;; ++i) {\n if (!(uint32_t)i || (uint32_t)v22 == 0 || (uint32_t)v25 == 0) {\n v30 = 0;\n } else if (*v21 == *(uint8_t *)(a2 + v25 - 1) &&\n *v21 == *(uint8_t *)(v42 + i - 1)) {\n v30 = v28[v23 - 1] + 1;\n } else {\n v30 = v27[v23];\n if (*v28 >= v30) v30 = *v28;\n if (v30 < *(v27 - 1)) v30 = *(v27 - 1);\n }\n *v27 = v30;\n ++v28;\n ++v27;\n if (i == v18) break;\n }\n v26 = (int *)((char *)v26 + v44);\n if (v25 == v19) break;\n ++v25;\n }\n v10 = v44;\n v24 = v41;\n a5 = v40;\n v7 = v39;\n v17 = v38;\n }\n LABEL_27:\n ++v21;\n v24 += v37;\n if (v22 == v17) break;\n ++v22;\n }\n v20 = v35;\n }\n return *(unsigned int *)&v36[4 * v20 * v19 + 4 * v18 + 4 * v37 * v17];\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, long long a3, int a4, int a5,\n int a6) {\n int v7;\n long long v9;\n unsigned long long v10;\n long long v11;\n long long v12;\n long long *v13;\n short v14;\n signed long long v15;\n void *v16;\n long long v17;\n long long v18;\n long long v19;\n unsigned long long v20;\n uint8_t *v21;\n long long v22;\n long long v23;\n long long v24;\n long long v25;\n int *v26;\n int *v27;\n int *v28;\n long long i;\n int v30;\n uint8_t v33[4088];\n long long v34;\n unsigned long long v35;\n uint8_t *v36;\n unsigned long long v37;\n long long v38;\n int v39;\n int v40;\n long long v41;\n long long v42;\n long long v43;\n unsigned long long v44;\n unsigned long long v45;\n v7 = a6;\n v9 = a6 + 1;\n v42 = a3;\n v10 = 4 * v9;\n v45 = __readfsqword(40u);\n v11 = v9 * (a5 + 1);\n v12 = 4 * v11 * (a4 + 1) + 15;\n v13 = (long long *)((char *)&v34 - (v12 & 18446744073709547520LL));\n v14 = v12 & 65520;\n if (&v34 != v13) {\n while (v33 != (uint8_t *)v13)\n ;\n }\n v15 = v14 & 4095;\n v16 = alloca(v15);\n if (v15) *(uint64_t *)&v33[v15 - 8] = *(uint64_t *)&v33[v15 - 8];\n v36 = v33;\n v17 = a4;\n v18 = a6;\n v19 = a5;\n v37 = (unsigned long long)(4 * v11) >> 2;\n v20 = v10 >> 2;\n if (a4 >= 0) {\n v17 = a4;\n v21 = (uint8_t *)(a1 - 1);\n v35 = v10 >> 2;\n v22 = 0LL;\n v19 = a5;\n v23 = -(long long)v37;\n v24 = 0LL;\n v43 = -4LL * v20;\n v18 = a6;\n while (1) {\n if (a5 >= 0) {\n v25 = 0LL;\n v26 = (int *)&v36[4 * v24];\n while (v7 < 0) {\n v26 = (int *)((char *)v26 + v10);\n if (v25 == v19) goto LABEL_27;\n ++v25;\n }\n v44 = v10;\n v41 = v24;\n v40 = a5;\n v39 = v7;\n v38 = v17;\n while (1) {\n v27 = v26;\n v28 = &v26[(unsigned long long)v43 / 4];\n for (i = 0LL;; ++i) {\n if (!(uint32_t)i || (uint32_t)v22 == 0 || (uint32_t)v25 == 0) {\n v30 = 0;\n } else if (*v21 == *(uint8_t *)(a2 + v25 - 1) &&\n *v21 == *(uint8_t *)(v42 + i - 1)) {\n v30 = v28[v23 - 1] + 1;\n } else {\n v30 = v27[v23];\n if (*v28 >= v30) v30 = *v28;\n if (v30 < *(v27 - 1)) v30 = *(v27 - 1);\n }\n *v27 = v30;\n ++v28;\n ++v27;\n if (i == v18) break;\n }\n v26 = (int *)((char *)v26 + v44);\n if (v25 == v19) break;\n ++v25;\n }\n v10 = v44;\n v24 = v41;\n a5 = v40;\n v7 = v39;\n v17 = v38;\n }\n LABEL_27:\n ++v21;\n v24 += v37;\n if (v22 == v17) break;\n ++v22;\n }\n v20 = v35;\n }\n return *(unsigned int *)&v36[4 * v20 * v19 + 4 * v18 + 4 * v37 * v17];\n}" + }, + { + "index": 747, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char* X, char* Y, char* Z, int m, int n, int o) {\n int L[m + 1][n + 1][o + 1];\n int i, j, k;\n for (i = 0; i <= m; i++) {\n for (j = 0; j <= n; j++) {\n for (k = 0; k <= o; k++) {\n if (i == 0 || j == 0 || k == 0) {\n L[i][j][k] = 0;\n } else if (X[i - 1] == Y[j - 1] && X[i - 1] == Z[k - 1]) {\n L[i][j][k] = L[i - 1][j - 1][k - 1] + 1;\n } else {\n int max1 =\n L[i - 1][j][k] > L[i][j - 1][k] ? L[i - 1][j][k] : L[i][j - 1][k];\n L[i][j][k] = max1 > L[i][j][k - 1] ? max1 : L[i][j][k - 1];\n }\n }\n }\n }\n return L[m][n][o];\n}", + "test": "int main() {\n\n\t// Testing the implementation with assertions\n\n\tassert(func0(\"AGGT12\", \"12TXAYB\", \"12XBA\", 6, 7, 5) == 2);\n\n\tassert(func0(\"Reels\", \"Reelsfor\", \"ReelsforReels\", 5, 8, 13) == 5);\n\n\tassert(func0(\"abcd1e2\", \"bc12ea\", \"bd1ea\", 7, 6, 5) == 3);\n\n\n\n\tprintf(\"All tests passed!\\n\");\n\n\treturn 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmovslq %r8d,%rax\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\nmov %rdi,%r13\nmovslq %r9d,%rdi\npush %r12\npush %rbx\nmov %rsi,%rbx\nsub $0x68,%rsp\nmov %rdx,-0x58(%rbp)\nmov %ecx,%edx\nmov %rsp,%r15\nmov %fs:0x28,%rcx\nmov %rcx,-0x38(%rbp)\nxor %ecx,%ecx\nlea 0x1(%rdi),%ecx\nmovslq %ecx,%rcx\nlea 0x0(,%rcx,4),%rsi\nmov %rsi,-0x50(%rbp)\nlea 0x1(%rax),%esi\nmovslq %esi,%rsi\nimul %rsi,%rcx\nlea 0x1(%rdx),%esi\nmovslq %esi,%rsi\nimul %rcx,%rsi\nlea 0xf(,%rsi,4),%r8\nmov %r8,%rsi\nand $0xfffffffffffff000,%r8\nsub %r8,%r15\nand $0xfffffffffffffff0,%rsi\nmov %r15,%r8\ncmp %r8,%rsp\nje 1335 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %r8,%rsp\njne 1320 \nand $0xfff,%esi\nsub %rsi,%rsp\ntest %rsi,%rsi\njne 14ee \nshl $0x2,%rcx\nmov %rsp,-0x80(%rbp)\nshr $0x2,%rcx\nmov %rcx,-0x60(%rbp)\nmov -0x50(%rbp),%rcx\nshr $0x2,%rcx\nmov %rcx,-0x88(%rbp)\ntest %edx,%edx\njs 14a3 \ntest %eax,%eax\njs 14a3 \ntest %edi,%edi\njs 14a3 \nmov %rcx,%r15\nmovslq %edx,%rcx\nmov %rax,-0x48(%rbp)\nsub $0x1,%r13\nmov %rcx,-0x78(%rbp)\nneg %r15\nxor %r14d,%r14d\nmovq $0x0,-0x70(%rbp)\nshl $0x2,%r15\nmovq $0xffffffffffffffff,-0x68(%rbp)\nnopw 0x0(%rax,%rax,1)\nmov -0x68(%rbp),%r12\nmov -0x80(%rbp),%rax\nxor %r10d,%r10d\nmov -0x70(%rbp),%rcx\nsub %r14,%r12\nimul -0x60(%rbp),%r12\nlea (%rax,%rcx,4),%r11\nnopl 0x0(%rax,%rax,1)\ntest %r14d,%r14d\nlea (%r11,%r15,1),%rcx\nmov %r11,%rdx\nsete %r8b\ntest %r10d,%r10d\nsete %al\nor %eax,%r8d\nxor %eax,%eax\njmp 142b \nnopl 0x0(%rax,%rax,1)\ntest %r8b,%r8b\njne 142f \nmovzbl 0x0(%r13),%esi\ncmp -0x1(%rbx,%r10,1),%sil\nje 1460 \nmov (%rdx,%r12,4),%esi\nmov -0x4(%rdx),%r9d\ncmp %esi,(%rcx)\ncmovge (%rcx),%esi\ncmp %r9d,%esi\ncmovl %r9d,%esi\nmov %esi,(%rdx)\nlea 0x1(%rax),%rsi\nadd $0x4,%rdx\nadd $0x4,%rcx\ncmp %rax,%rdi\nje 1440 \nmov %rsi,%rax\ntest %eax,%eax\njne 13f0 \nmovl $0x0,(%rdx)\njmp 1417 \nnopw 0x0(%rax,%rax,1)\nlea 0x1(%r10),%rax\nadd -0x50(%rbp),%r11\ncmp -0x48(%rbp),%r10\nje 1480 \nmov %rax,%r10\njmpq 13d0 \nnopw %cs:0x0(%rax,%rax,1)\nmov -0x58(%rbp),%r9\ncmp -0x1(%r9,%rax,1),%sil\njne 1401 \nmov -0x4(%rcx,%r12,4),%esi\nadd $0x1,%esi\nmov %esi,(%rdx)\njmp 1417 \nnopw 0x0(%rax,%rax,1)\nmov -0x60(%rbp),%rdx\nlea 0x1(%r14),%rax\nadd %rdx,-0x70(%rbp)\nadd $0x1,%r13\naddq $0x1,-0x68(%rbp)\ncmp -0x78(%rbp),%r14\nje 14ae \nmov %rax,%r14\njmpq 13b0 \nmovslq %edx,%rbx\nmov %rax,-0x48(%rbp)\nmov %rbx,-0x78(%rbp)\nmov -0x78(%rbp),%rax\nimul -0x60(%rbp),%rax\nmov -0x48(%rbp),%rdx\nimul -0x88(%rbp),%rdx\nmov -0x80(%rbp),%rbx\nadd %rdi,%rax\nadd %rdx,%rax\nmov (%rbx,%rax,4),%eax\nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\njne 14f9 \nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\norq $0x0,-0x8(%rsp,%rsi,1)\njmpq 1347 \ncallq 1080 <__stack_chk_fail@plt>\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov r10d, ecx\nlea ecx, [r9+1]\nmov r11, rsi\nmovsxd rcx, ecx\nmov eax, r9d\nmov rbp, rsp\npush r15\npush r14\nlea r14, ds:0[rcx*4]\npush r13\npush r12\npush rbx\nmov rbx, rdi\nsub rsp, 68h\nmov [rbp+var_58], rdx\nmov [rbp+var_7C], r8d\nmov rdi, rsp\nmov rdx, fs:28h\nmov [rbp+var_38], rdx\nxor edx, edx\nlea edx, [r8+1]\nmovsxd rdx, edx\nimul rdx, rcx\nlea ecx, [r10+1]\nmovsxd rcx, ecx\nimul rcx, rdx\nlea rsi, ds:0Fh[rcx*4]\nmov rcx, rsi\nand rsi, 0FFFFFFFFFFFFF000h\nsub rdi, rsi\nand rcx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rdi\njz short loc_1333\nloc_131E:\nsub rsp, 1000h\nor [rsp+1090h+var_98], 0\ncmp rsp, rdi\njnz short loc_131E\nloc_1333:\nand ecx, 0FFFh\nsub rsp, rcx\ntest rcx, rcx\njnz loc_14EE\nloc_1345:\nshl rdx, 2\nmov r12d, [rbp+var_7C]\nmov r9, r14\nmov r8, rsp\nshr rdx, 2\nshr r9, 2\nmov rsi, rdx\nmov edx, r12d\nor edx, r10d\nor edx, eax\njs loc_14B5\nmov r15d, r10d\nmov rdx, r9\nmov [rbp+var_50], r14\nxor ecx, ecx\nmov [rbp+var_88], r9\nneg rdx\nsub rbx, 1\nmov edi, eax\nmov [rbp+var_78], r15\nshl rdx, 2\nxor r13d, r13d\nmov [rbp+var_80], r10d\nmov [rbp+var_8C], eax\nmov [rbp+var_70], r8\nmov [rbp+var_48], r12\nmov r12, rsi\nmov [rbp+var_68], rsi\nneg r12\nmov rsi, rcx\nnop word ptr [rax+rax+00h]\nloc_13B8:\nmov rax, [rbp+var_70]\nmov [rbp+var_60], rsi\nxor r10d, r10d\nlea r14, [rax+rsi*4]\nnop word ptr [rax+rax+00000000h]\nloc_13D0:\ntest r13d, r13d\nlea r8, [r14+rdx]\nmov rsi, r14\nsetz r9b\ntest r10d, r10d\nsetz al\nor r9d, eax\nxor eax, eax\njmp short loc_142E\nloc_13F0:\ntest r9b, r9b\njnz short loc_1432\nmovzx ecx, byte ptr [rbx]\ncmp cl, [r11+r10-1]\njz short loc_1460\nloc_13FF:\nmov r15d, [r8]\nmov ecx, [rsi+r12*4]\ncmp r15d, ecx\ncmovge ecx, r15d\nmov r15d, [rsi-4]\ncmp ecx, r15d\ncmovl ecx, r15d\nloc_1418:\nmov [rsi], ecx\nadd r8, 4\nlea rcx, [rax+1]\nadd rsi, 4\ncmp rdi, rax\njz short loc_1440\nmov rax, rcx\nloc_142E:\ntest eax, eax\njnz short loc_13F0\nloc_1432:\nxor ecx, ecx\njmp short loc_1418\nloc_1440:\nmov rsi, [rbp+var_50]\nlea rax, [r10+1]\nadd r14, rsi\nmov rsi, [rbp+var_48]\ncmp r10, rsi\njz short loc_1478\nmov r10, rax\njmp loc_13D0\nloc_1460:\nmov r15, [rbp+var_58]\ncmp cl, [r15+rax-1]\njnz short loc_13FF\nmov ecx, [r8+r12*4-4]\nadd ecx, 1\njmp short loc_1418\nloc_1478:\nmov rcx, [rbp+var_68]\nmov rsi, [rbp+var_60]\nlea rax, [r13+1]\nadd rbx, 1\nadd rsi, rcx\nmov rcx, [rbp+var_78]\ncmp r13, rcx\njz short loc_149C\nmov r13, rax\njmp loc_13B8\nloc_149C:\nmov rsi, [rbp+var_68]\nmov r9, [rbp+var_88]\nmov r10d, [rbp+var_80]\nmov eax, [rbp+var_8C]\nmov r8, [rbp+var_70]\nloc_14B5:\nmovsxd rdx, [rbp+var_7C]\nmovsxd rcx, r10d\ncdqe\nimul rcx, rsi\nimul rdx, r9\nadd rax, rcx\nadd rax, rdx\nmov eax, [r8+rax*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_14F9\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_14EE:\nor [rsp+rcx+1090h+var_1098], 0\njmp loc_1345\nloc_14F9:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, __int64 a3, unsigned int a4, unsigned int a5, unsigned int a6)\n{\n __int64 v8; // rcx\n unsigned int v9; // eax\n unsigned __int64 v10; // r14\n __int64 v12; // rdx\n __int64 v13; // rcx\n _BYTE *v14; // rdi\n __int16 v15; // cx\n signed __int64 v16; // rcx\n void *v17; // rsp\n _BYTE *v18; // r8\n unsigned __int64 v19; // r9\n unsigned __int64 v20; // rsi\n _BYTE *v21; // rbx\n __int64 v22; // rdi\n __int64 v23; // r13\n __int64 v24; // r12\n __int64 v25; // rsi\n __int64 v26; // r10\n int *v27; // r14\n int *v28; // r8\n int *v29; // rsi\n __int64 i; // rax\n int v31; // ecx\n _BYTE v34[4088]; // [rsp+8h] [rbp-1090h] BYREF\n _BYTE v35[4]; // [rsp+1008h] [rbp-90h] BYREF\n unsigned int v36; // [rsp+100Ch] [rbp-8Ch]\n unsigned __int64 v37; // [rsp+1010h] [rbp-88h]\n unsigned int v38; // [rsp+1018h] [rbp-80h]\n unsigned int v39; // [rsp+101Ch] [rbp-7Ch]\n __int64 v40; // [rsp+1020h] [rbp-78h]\n _BYTE *v41; // [rsp+1028h] [rbp-70h]\n unsigned __int64 v42; // [rsp+1030h] [rbp-68h]\n __int64 v43; // [rsp+1038h] [rbp-60h]\n __int64 v44; // [rsp+1040h] [rbp-58h]\n unsigned __int64 v45; // [rsp+1048h] [rbp-50h]\n __int64 v46; // [rsp+1050h] [rbp-48h]\n unsigned __int64 v47; // [rsp+1060h] [rbp-38h]\n\n v8 = (int)(a6 + 1);\n v9 = a6;\n v10 = 4 * v8;\n v44 = a3;\n v39 = a5;\n v47 = __readfsqword(0x28u);\n v12 = v8 * (int)(a5 + 1);\n v13 = 4 * v12 * (int)(a4 + 1) + 15;\n v14 = &v35[-(v13 & 0xFFFFFFFFFFFFF000LL)];\n v15 = v13 & 0xFFF0;\n if ( v35 != v14 )\n {\n while ( v34 != v14 )\n ;\n }\n v16 = v15 & 0xFFF;\n v17 = alloca(v16);\n if ( v16 )\n *(_QWORD *)&v34[v16 - 8] = *(_QWORD *)&v34[v16 - 8];\n v18 = v34;\n v19 = v10 >> 2;\n v20 = (unsigned __int64)(4 * v12) >> 2;\n if ( ((v9 | a4 | v39) & 0x80000000) == 0 )\n {\n v45 = v10;\n v37 = v10 >> 2;\n v21 = (_BYTE *)(a1 - 1);\n v22 = v9;\n v40 = a4;\n v23 = 0LL;\n v38 = a4;\n v36 = v9;\n v41 = v34;\n v46 = v39;\n v42 = (unsigned __int64)(4 * v12) >> 2;\n v24 = -(__int64)v20;\n v25 = 0LL;\n while ( 1 )\n {\n v43 = v25;\n v26 = 0LL;\n v27 = (int *)&v41[4 * v25];\n while ( 1 )\n {\n v28 = &v27[-v19];\n v29 = v27;\n for ( i = 0LL; ; ++i )\n {\n if ( !(_DWORD)i || (_DWORD)v26 == 0 || (_DWORD)v23 == 0 )\n {\n v31 = 0;\n }\n else if ( *v21 == *(_BYTE *)(a2 + v26 - 1) && *v21 == *(_BYTE *)(v44 + i - 1) )\n {\n v31 = v28[v24 - 1] + 1;\n }\n else\n {\n v31 = v29[v24];\n if ( *v28 >= v31 )\n v31 = *v28;\n if ( v31 < *(v29 - 1) )\n v31 = *(v29 - 1);\n }\n *v29 = v31;\n ++v28;\n ++v29;\n if ( v22 == i )\n break;\n }\n v27 = (int *)((char *)v27 + v45);\n if ( v26 == v46 )\n break;\n ++v26;\n }\n ++v21;\n v25 = v42 + v43;\n if ( v23 == v40 )\n break;\n ++v23;\n }\n v20 = v42;\n v19 = v37;\n a4 = v38;\n v9 = v36;\n v18 = v41;\n }\n return *(unsigned int *)&v18[4 * v19 * (int)v39 + 4 * v20 * (int)a4 + 4 * (int)v9];\n}", + "ida_strip_asm": "sub_12A0:\nendbr64\npush rbp\nmov r10d, ecx\nlea ecx, [r9+1]\nmov r11, rsi\nmovsxd rcx, ecx\nmov eax, r9d\nmov rbp, rsp\npush r15\npush r14\nlea r14, ds:0[rcx*4]\npush r13\npush r12\npush rbx\nmov rbx, rdi\nsub rsp, 68h\nmov [rbp+var_58], rdx\nmov [rbp+var_7C], r8d\nmov rdi, rsp\nmov rdx, fs:28h\nmov [rbp+var_38], rdx\nxor edx, edx\nlea edx, [r8+1]\nmovsxd rdx, edx\nimul rdx, rcx\nlea ecx, [r10+1]\nmovsxd rcx, ecx\nimul rcx, rdx\nlea rsi, ds:0Fh[rcx*4]\nmov rcx, rsi\nand rsi, 0FFFFFFFFFFFFF000h\nsub rdi, rsi\nand rcx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rdi\njz short loc_1333\nloc_131E:\nsub rsp, 1000h\nor [rsp+1090h+var_98], 0\ncmp rsp, rdi\njnz short loc_131E\nloc_1333:\nand ecx, 0FFFh\nsub rsp, rcx\ntest rcx, rcx\njnz loc_14EE\nloc_1345:\nshl rdx, 2\nmov r12d, [rbp+var_7C]\nmov r9, r14\nmov r8, rsp\nshr rdx, 2\nshr r9, 2\nmov rsi, rdx\nmov edx, r12d\nor edx, r10d\nor edx, eax\njs loc_14B5\nmov r15d, r10d\nmov rdx, r9\nmov [rbp+var_50], r14\nxor ecx, ecx\nmov [rbp+var_88], r9\nneg rdx\nsub rbx, 1\nmov edi, eax\nmov [rbp+var_78], r15\nshl rdx, 2\nxor r13d, r13d\nmov [rbp+var_80], r10d\nmov [rbp+var_8C], eax\nmov [rbp+var_70], r8\nmov [rbp+var_48], r12\nmov r12, rsi\nmov [rbp+var_68], rsi\nneg r12\nmov rsi, rcx\nnop word ptr [rax+rax+00h]\nloc_13B8:\nmov rax, [rbp+var_70]\nmov [rbp+var_60], rsi\nxor r10d, r10d\nlea r14, [rax+rsi*4]\nnop word ptr [rax+rax+00000000h]\nloc_13D0:\ntest r13d, r13d\nlea r8, [r14+rdx]\nmov rsi, r14\nsetz r9b\ntest r10d, r10d\nsetz al\nor r9d, eax\nxor eax, eax\njmp short loc_142E\nloc_13F0:\ntest r9b, r9b\njnz short loc_1432\nmovzx ecx, byte ptr [rbx]\ncmp cl, [r11+r10-1]\njz short loc_1460\nloc_13FF:\nmov r15d, [r8]\nmov ecx, [rsi+r12*4]\ncmp r15d, ecx\ncmovge ecx, r15d\nmov r15d, [rsi-4]\ncmp ecx, r15d\ncmovl ecx, r15d\nloc_1418:\nmov [rsi], ecx\nadd r8, 4\nlea rcx, [rax+1]\nadd rsi, 4\ncmp rdi, rax\njz short loc_1440\nmov rax, rcx\nloc_142E:\ntest eax, eax\njnz short loc_13F0\nloc_1432:\nxor ecx, ecx\njmp short loc_1418\nloc_1440:\nmov rsi, [rbp+var_50]\nlea rax, [r10+1]\nadd r14, rsi\nmov rsi, [rbp+var_48]\ncmp r10, rsi\njz short loc_1478\nmov r10, rax\njmp loc_13D0\nloc_1460:\nmov r15, [rbp+var_58]\ncmp cl, [r15+rax-1]\njnz short loc_13FF\nmov ecx, [r8+r12*4-4]\nadd ecx, 1\njmp short loc_1418\nloc_1478:\nmov rcx, [rbp+var_68]\nmov rsi, [rbp+var_60]\nlea rax, [r13+1]\nadd rbx, 1\nadd rsi, rcx\nmov rcx, [rbp+var_78]\ncmp r13, rcx\njz short loc_149C\nmov r13, rax\njmp loc_13B8\nloc_149C:\nmov rsi, [rbp+var_68]\nmov r9, [rbp+var_88]\nmov r10d, [rbp+var_80]\nmov eax, [rbp+var_8C]\nmov r8, [rbp+var_70]\nloc_14B5:\nmovsxd rdx, [rbp+var_7C]\nmovsxd rcx, r10d\ncdqe\nimul rcx, rsi\nimul rdx, r9\nadd rax, rcx\nadd rax, rdx\nmov eax, [r8+rax*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_14F9\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_14EE:\nor [rsp+rcx+1090h+var_1098], 0\njmp loc_1345\nloc_14F9:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12A0(__int64 a1, __int64 a2, __int64 a3, unsigned int a4, unsigned int a5, unsigned int a6)\n{\n __int64 v8; // rcx\n unsigned int v9; // eax\n unsigned __int64 v10; // r14\n __int64 v12; // rdx\n __int64 v13; // rcx\n _BYTE *v14; // rdi\n __int16 v15; // cx\n signed __int64 v16; // rcx\n void *v17; // rsp\n _BYTE *v18; // r8\n unsigned __int64 v19; // r9\n unsigned __int64 v20; // rsi\n _BYTE *v21; // rbx\n __int64 v22; // rdi\n __int64 v23; // r13\n __int64 v24; // r12\n __int64 v25; // rsi\n __int64 v26; // r10\n int *v27; // r14\n int *v28; // r8\n int *v29; // rsi\n __int64 i; // rax\n int v31; // ecx\n _BYTE v34[4088]; // [rsp+8h] [rbp-1090h] BYREF\n _BYTE v35[4]; // [rsp+1008h] [rbp-90h] BYREF\n unsigned int v36; // [rsp+100Ch] [rbp-8Ch]\n unsigned __int64 v37; // [rsp+1010h] [rbp-88h]\n unsigned int v38; // [rsp+1018h] [rbp-80h]\n unsigned int v39; // [rsp+101Ch] [rbp-7Ch]\n __int64 v40; // [rsp+1020h] [rbp-78h]\n _BYTE *v41; // [rsp+1028h] [rbp-70h]\n unsigned __int64 v42; // [rsp+1030h] [rbp-68h]\n __int64 v43; // [rsp+1038h] [rbp-60h]\n __int64 v44; // [rsp+1040h] [rbp-58h]\n unsigned __int64 v45; // [rsp+1048h] [rbp-50h]\n __int64 v46; // [rsp+1050h] [rbp-48h]\n unsigned __int64 v47; // [rsp+1060h] [rbp-38h]\n\n v8 = (int)(a6 + 1);\n v9 = a6;\n v10 = 4 * v8;\n v44 = a3;\n v39 = a5;\n v47 = __readfsqword(0x28u);\n v12 = v8 * (int)(a5 + 1);\n v13 = 4 * v12 * (int)(a4 + 1) + 15;\n v14 = &v35[-(v13 & 0xFFFFFFFFFFFFF000LL)];\n v15 = v13 & 0xFFF0;\n if ( v35 != v14 )\n {\n while ( v34 != v14 )\n ;\n }\n v16 = v15 & 0xFFF;\n v17 = alloca(v16);\n if ( v16 )\n *(_QWORD *)&v34[v16 - 8] = *(_QWORD *)&v34[v16 - 8];\n v18 = v34;\n v19 = v10 >> 2;\n v20 = (unsigned __int64)(4 * v12) >> 2;\n if ( ((v9 | a4 | v39) & 0x80000000) == 0 )\n {\n v45 = v10;\n v37 = v10 >> 2;\n v21 = (_BYTE *)(a1 - 1);\n v22 = v9;\n v40 = a4;\n v23 = 0LL;\n v38 = a4;\n v36 = v9;\n v41 = v34;\n v46 = v39;\n v42 = (unsigned __int64)(4 * v12) >> 2;\n v24 = -(__int64)v20;\n v25 = 0LL;\n while ( 1 )\n {\n v43 = v25;\n v26 = 0LL;\n v27 = (int *)&v41[4 * v25];\n while ( 1 )\n {\n v28 = &v27[-v19];\n v29 = v27;\n for ( i = 0LL; ; ++i )\n {\n if ( !(_DWORD)i || (_DWORD)v26 == 0 || (_DWORD)v23 == 0 )\n {\n v31 = 0;\n }\n else if ( *v21 == *(_BYTE *)(a2 + v26 - 1) && *v21 == *(_BYTE *)(v44 + i - 1) )\n {\n v31 = v28[v24 - 1] + 1;\n }\n else\n {\n v31 = v29[v24];\n if ( *v28 >= v31 )\n v31 = *v28;\n if ( v31 < *(v29 - 1) )\n v31 = *(v29 - 1);\n }\n *v29 = v31;\n ++v28;\n ++v29;\n if ( v22 == i )\n break;\n }\n v27 = (int *)((char *)v27 + v45);\n if ( v26 == v46 )\n break;\n ++v26;\n }\n ++v21;\n v25 = v42 + v43;\n if ( v23 == v40 )\n break;\n ++v23;\n }\n v20 = v42;\n v19 = v37;\n a4 = v38;\n v9 = v36;\n v18 = v41;\n }\n return *(unsigned int *)&v18[4 * v19 * (int)v39 + 4 * v20 * (int)a4 + 4 * (int)v9];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12A0(long long a1, long long a2, long long a3, unsigned int a4,\n unsigned int a5, unsigned int a6) {\n long long v8;\n unsigned int v9;\n unsigned long long v10;\n long long v12;\n long long v13;\n uint8_t *v14;\n short v15;\n signed long long v16;\n void *v17;\n uint8_t *v18;\n unsigned long long v19;\n unsigned long long v20;\n uint8_t *v21;\n long long v22;\n long long v23;\n long long v24;\n long long v25;\n long long v26;\n int *v27;\n int *v28;\n int *v29;\n long long i;\n int v31;\n uint8_t v34[4088];\n uint8_t v35[4];\n unsigned int v36;\n unsigned long long v37;\n unsigned int v38;\n unsigned int v39;\n long long v40;\n uint8_t *v41;\n unsigned long long v42;\n long long v43;\n long long v44;\n unsigned long long v45;\n long long v46;\n unsigned long long v47;\n v8 = (int)(a6 + 1);\n v9 = a6;\n v10 = 4 * v8;\n v44 = a3;\n v39 = a5;\n v47 = __readfsqword(40u);\n v12 = v8 * (int)(a5 + 1);\n v13 = 4 * v12 * (int)(a4 + 1) + 15;\n v14 = &v35[-(v13 & 18446744073709547520LL)];\n v15 = v13 & 65520;\n if (v35 != v14) {\n while (v34 != v14)\n ;\n }\n v16 = v15 & 4095;\n v17 = alloca(v16);\n if (v16) *(uint64_t *)&v34[v16 - 8] = *(uint64_t *)&v34[v16 - 8];\n v18 = v34;\n v19 = v10 >> 2;\n v20 = (unsigned long long)(4 * v12) >> 2;\n if (((v9 | a4 | v39) & 2147483648) == 0) {\n v45 = v10;\n v37 = v10 >> 2;\n v21 = (uint8_t *)(a1 - 1);\n v22 = v9;\n v40 = a4;\n v23 = 0LL;\n v38 = a4;\n v36 = v9;\n v41 = v34;\n v46 = v39;\n v42 = (unsigned long long)(4 * v12) >> 2;\n v24 = -(long long)v20;\n v25 = 0LL;\n while (1) {\n v43 = v25;\n v26 = 0LL;\n v27 = (int *)&v41[4 * v25];\n while (1) {\n v28 = &v27[-v19];\n v29 = v27;\n for (i = 0LL;; ++i) {\n if (!(uint32_t)i || (uint32_t)v26 == 0 || (uint32_t)v23 == 0) {\n v31 = 0;\n } else if (*v21 == *(uint8_t *)(a2 + v26 - 1) &&\n *v21 == *(uint8_t *)(v44 + i - 1)) {\n v31 = v28[v24 - 1] + 1;\n } else {\n v31 = v29[v24];\n if (*v28 >= v31) v31 = *v28;\n if (v31 < *(v29 - 1)) v31 = *(v29 - 1);\n }\n *v29 = v31;\n ++v28;\n ++v29;\n if (v22 == i) break;\n }\n v27 = (int *)((char *)v27 + v45);\n if (v26 == v46) break;\n ++v26;\n }\n ++v21;\n v25 = v42 + v43;\n if (v23 == v40) break;\n ++v23;\n }\n v20 = v42;\n v19 = v37;\n a4 = v38;\n v9 = v36;\n v18 = v41;\n }\n return *(\n unsigned int *)&v18[4 * v19 * (int)v39 + 4 * v20 * (int)a4 + 4 * (int)v9];\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, long long a3, unsigned int a4,\n unsigned int a5, unsigned int a6) {\n long long v8;\n unsigned int v9;\n unsigned long long v10;\n long long v12;\n long long v13;\n uint8_t *v14;\n short v15;\n signed long long v16;\n void *v17;\n uint8_t *v18;\n unsigned long long v19;\n unsigned long long v20;\n uint8_t *v21;\n long long v22;\n long long v23;\n long long v24;\n long long v25;\n long long v26;\n int *v27;\n int *v28;\n int *v29;\n long long i;\n int v31;\n uint8_t v34[4088];\n uint8_t v35[4];\n unsigned int v36;\n unsigned long long v37;\n unsigned int v38;\n unsigned int v39;\n long long v40;\n uint8_t *v41;\n unsigned long long v42;\n long long v43;\n long long v44;\n unsigned long long v45;\n long long v46;\n unsigned long long v47;\n v8 = (int)(a6 + 1);\n v9 = a6;\n v10 = 4 * v8;\n v44 = a3;\n v39 = a5;\n v47 = __readfsqword(40u);\n v12 = v8 * (int)(a5 + 1);\n v13 = 4 * v12 * (int)(a4 + 1) + 15;\n v14 = &v35[-(v13 & 18446744073709547520LL)];\n v15 = v13 & 65520;\n if (v35 != v14) {\n while (v34 != v14)\n ;\n }\n v16 = v15 & 4095;\n v17 = alloca(v16);\n if (v16) *(uint64_t *)&v34[v16 - 8] = *(uint64_t *)&v34[v16 - 8];\n v18 = v34;\n v19 = v10 >> 2;\n v20 = (unsigned long long)(4 * v12) >> 2;\n if (((v9 | a4 | v39) & 2147483648) == 0) {\n v45 = v10;\n v37 = v10 >> 2;\n v21 = (uint8_t *)(a1 - 1);\n v22 = v9;\n v40 = a4;\n v23 = 0LL;\n v38 = a4;\n v36 = v9;\n v41 = v34;\n v46 = v39;\n v42 = (unsigned long long)(4 * v12) >> 2;\n v24 = -(long long)v20;\n v25 = 0LL;\n while (1) {\n v43 = v25;\n v26 = 0LL;\n v27 = (int *)&v41[4 * v25];\n while (1) {\n v28 = &v27[-v19];\n v29 = v27;\n for (i = 0LL;; ++i) {\n if (!(uint32_t)i || (uint32_t)v26 == 0 || (uint32_t)v23 == 0) {\n v31 = 0;\n } else if (*v21 == *(uint8_t *)(a2 + v26 - 1) &&\n *v21 == *(uint8_t *)(v44 + i - 1)) {\n v31 = v28[v24 - 1] + 1;\n } else {\n v31 = v29[v24];\n if (*v28 >= v31) v31 = *v28;\n if (v31 < *(v29 - 1)) v31 = *(v29 - 1);\n }\n *v29 = v31;\n ++v28;\n ++v29;\n if (v22 == i) break;\n }\n v27 = (int *)((char *)v27 + v45);\n if (v26 == v46) break;\n ++v26;\n }\n ++v21;\n v25 = v42 + v43;\n if (v23 == v40) break;\n ++v23;\n }\n v20 = v42;\n v19 = v37;\n a4 = v38;\n v9 = v36;\n v18 = v41;\n }\n return *(\n unsigned int *)&v18[4 * v19 * (int)v39 + 4 * v20 * (int)a4 + 4 * (int)v9];\n}" + }, + { + "index": 748, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(const char *str1, char *result) {\n regex_t regex;\n regmatch_t matches[3];\n char buffer[1024];\n regcomp(®ex, \"([a-z])([A-Z])\", REG_EXTENDED);\n strcpy(buffer, str1);\n const char *cursor = buffer;\n result[0] = '\\0';\n while (regexec(®ex, cursor, 3, matches, 0) == 0) {\n strncat(result, cursor, matches[1].rm_eo);\n strcat(result, \" \");\n cursor += matches[2].rm_so;\n }\n strcat(result, cursor);\n regfree(®ex);\n}", + "test": "int main() {\n\n char result[1024];\n\n\n\n func0(\"Python\", result);\n\n assert(strcmp(result, \"Python\") == 0);\n\n\n\n func0(\"PythonProgrammingExamples\", result);\n\n assert(strcmp(result, \"Python Programming Examples\") == 0);\n\n\n\n func0(\"GetReadyToBeCodingFreak\", result);\n\n assert(strcmp(result, \"Get Ready To Be Coding Freak\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x490,%rsp\nmov %rdi,-0x488(%rbp)\nmov %rsi,-0x490(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea -0x470(%rbp),%rax\nmov $0x1,%edx\nlea 0xd80(%rip),%rsi\nmov %rax,%rdi\ncallq 1120 \nmov -0x488(%rbp),%rdx\nlea -0x410(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10d0 \nlea -0x410(%rbp),%rax\nmov %rax,-0x478(%rbp)\nmov -0x490(%rbp),%rax\nmovb $0x0,(%rax)\njmp 1328 \nmov -0x424(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x478(%rbp),%rcx\nmov -0x490(%rbp),%rax\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 1110 \nmov -0x490(%rbp),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nmov -0x490(%rbp),%rax\nadd %rdx,%rax\nmovw $0x20,(%rax)\nmov -0x420(%rbp),%eax\ncltq\nadd %rax,-0x478(%rbp)\nlea -0x430(%rbp),%rdx\nmov -0x478(%rbp),%rsi\nlea -0x470(%rbp),%rax\nmov $0x0,%r8d\nmov %rdx,%rcx\nmov $0x3,%edx\nmov %rax,%rdi\ncallq 1140 \ntest %eax,%eax\nje 12c3 \nmov -0x478(%rbp),%rdx\nmov -0x490(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1150 \nlea -0x470(%rbp),%rax\nmov %rax,%rdi\ncallq 10e0 \nmov -0x8(%rbp),%rax\nxor %fs:0x28,%rax\nje 1398 \ncallq 10f0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 490h\nmov [rbp+src], rdi\nmov [rbp+s], rsi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nlea rcx, pattern; \"([a-z])([A-Z])\"\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov rdx, [rbp+src]\nlea rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\nlea rax, [rbp+dest]\nmov [rbp+string], rax\nmov rax, [rbp+s]\nmov byte ptr [rax], 0\njmp short loc_1338\nloc_12E6:\nmov eax, [rbp+var_424]\nmovsxd rdx, eax; n\nmov rcx, [rbp+string]\nmov rax, [rbp+s]\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strncat\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+s]\nadd rax, rdx\nmov word ptr [rax], 20h ; ' '\nmov eax, [rbp+var_420]\ncdqe\nadd [rbp+string], rax\nloc_1338:\nlea rdx, [rbp+pmatch]\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov rcx, rdx; pmatch\nmov edx, 3; nmatch\nmov rdi, rax; preg\ncall _regexec\ntest eax, eax\njz loc_12E6\nmov rdx, [rbp+string]\nmov rax, [rbp+s]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nnop\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njz short locret_13A8\ncall ___stack_chk_fail\nlocret_13A8:\nleave\nretn", + "ida_pseudo": "unsigned __int64 __fastcall func0(const char *a1, char *a2)\n{\n int i; // eax\n const char *string; // [rsp+18h] [rbp-478h]\n regex_t preg; // [rsp+20h] [rbp-470h] BYREF\n regmatch_t pmatch; // [rsp+60h] [rbp-430h] BYREF\n int v7; // [rsp+6Ch] [rbp-424h]\n int v8; // [rsp+70h] [rbp-420h]\n char dest[1032]; // [rsp+80h] [rbp-410h] BYREF\n unsigned __int64 v10; // [rsp+488h] [rbp-8h]\n\n v10 = __readfsqword(0x28u);\n regcomp(&preg, \"([a-z])([A-Z])\", 1);\n strcpy(dest, a1);\n string = dest;\n *a2 = 0;\n for ( i = regexec(&preg, dest, 3uLL, &pmatch, 0); !i; i = regexec(&preg, string, 3uLL, &pmatch, 0) )\n {\n strncat(a2, string, v7);\n *(_WORD *)&a2[strlen(a2)] = 32;\n string += v8;\n }\n strcat(a2, string);\n regfree(&preg);\n return v10 - __readfsqword(0x28u);\n}", + "ida_strip_asm": "sub_1269:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 490h\nmov [rbp+src], rdi\nmov [rbp+s], rsi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nlea rcx, pattern; \"([a-z])([A-Z])\"\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov rdx, [rbp+src]\nlea rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\nlea rax, [rbp+dest]\nmov [rbp+string], rax\nmov rax, [rbp+s]\nmov byte ptr [rax], 0\njmp short loc_1338\nloc_12E6:\nmov eax, [rbp+var_424]\nmovsxd rdx, eax; n\nmov rcx, [rbp+string]\nmov rax, [rbp+s]\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strncat\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+s]\nadd rax, rdx\nmov word ptr [rax], 20h ; ' '\nmov eax, [rbp+var_420]\ncdqe\nadd [rbp+string], rax\nloc_1338:\nlea rdx, [rbp+pmatch]\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov rcx, rdx; pmatch\nmov edx, 3; nmatch\nmov rdi, rax; preg\ncall _regexec\ntest eax, eax\njz loc_12E6\nmov rdx, [rbp+string]\nmov rax, [rbp+s]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nnop\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njz short locret_13A8\ncall ___stack_chk_fail\nlocret_13A8:\nleave\nretn", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_1269(const char *a1, char *a2)\n{\n int i; // eax\n const char *string; // [rsp+18h] [rbp-478h]\n regex_t preg; // [rsp+20h] [rbp-470h] BYREF\n regmatch_t pmatch; // [rsp+60h] [rbp-430h] BYREF\n int v7; // [rsp+6Ch] [rbp-424h]\n int v8; // [rsp+70h] [rbp-420h]\n char dest[1032]; // [rsp+80h] [rbp-410h] BYREF\n unsigned __int64 v10; // [rsp+488h] [rbp-8h]\n\n v10 = __readfsqword(0x28u);\n regcomp(&preg, \"([a-z])([A-Z])\", 1);\n strcpy(dest, a1);\n string = dest;\n *a2 = 0;\n for ( i = regexec(&preg, dest, 3uLL, &pmatch, 0); !i; i = regexec(&preg, string, 3uLL, &pmatch, 0) )\n {\n strncat(a2, string, v7);\n *(_WORD *)&a2[strlen(a2)] = 32;\n string += v8;\n }\n strcat(a2, string);\n regfree(&preg);\n return v10 - __readfsqword(0x28u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_1269(const char *a1, char *a2) {\n int i;\n const char *string;\n regex_t preg;\n regmatch_t pmatch;\n int v7;\n int v8;\n char dest[1032];\n unsigned long long v10;\n v10 = __readfsqword(40u);\n regcomp(&preg, \"([a-z])([A-Z])\", 1);\n strcpy(dest, a1);\n string = dest;\n *a2 = 0;\n for (i = regexec(&preg, dest, 3uLL, &pmatch, 0); !i;\n i = regexec(&preg, string, 3uLL, &pmatch, 0)) {\n strncat(a2, string, v7);\n *(unsigned short *)&a2[strlen(a2)] = 32;\n string += v8;\n }\n strcat(a2, string);\n regfree(&preg);\n return v10 - __readfsqword(40u);\n}", + "ida_pseudo_norm": "unsigned long long func0(const char *a1, char *a2) {\n int i;\n const char *string;\n regex_t preg;\n regmatch_t pmatch;\n int v7;\n int v8;\n char dest[1032];\n unsigned long long v10;\n v10 = __readfsqword(40u);\n regcomp(&preg, \"([a-z])([A-Z])\", 1);\n strcpy(dest, a1);\n string = dest;\n *a2 = 0;\n for (i = regexec(&preg, dest, 3uLL, &pmatch, 0); !i;\n i = regexec(&preg, string, 3uLL, &pmatch, 0)) {\n strncat(a2, string, v7);\n *(unsigned short *)&a2[strlen(a2)] = 32;\n string += v8;\n }\n strcat(a2, string);\n regfree(&preg);\n return v10 - __readfsqword(40u);\n}" + }, + { + "index": 748, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(const char *str1, char *result) {\n regex_t regex;\n regmatch_t matches[3];\n char buffer[1024];\n regcomp(®ex, \"([a-z])([A-Z])\", REG_EXTENDED);\n strcpy(buffer, str1);\n const char *cursor = buffer;\n result[0] = '\\0';\n while (regexec(®ex, cursor, 3, matches, 0) == 0) {\n strncat(result, cursor, matches[1].rm_eo);\n strcat(result, \" \");\n cursor += matches[2].rm_so;\n }\n strcat(result, cursor);\n regfree(®ex);\n}", + "test": "int main() {\n\n char result[1024];\n\n\n\n func0(\"Python\", result);\n\n assert(strcmp(result, \"Python\") == 0);\n\n\n\n func0(\"PythonProgrammingExamples\", result);\n\n assert(strcmp(result, \"Python Programming Examples\") == 0);\n\n\n\n func0(\"GetReadyToBeCodingFreak\", result);\n\n assert(strcmp(result, \"Get Ready To Be Coding Freak\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nsub $0x470,%rsp\nmov %rdi,%r12\nmov %rsi,%rbp\nmov %fs:0x28,%rax\nmov %rax,0x468(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nmov $0x1,%edx\nlea 0xda4(%rip),%rsi\ncallq 1100 \nlea 0x60(%rsp),%rbx\nmov $0x400,%edx\nmov %r12,%rsi\nmov %rbx,%rdi\ncallq 1120 <__strcpy_chk@plt>\nmovb $0x0,0x0(%rbp)\nlea 0x40(%rsp),%r12\nmov %rsp,%rdi\nmov $0x0,%r8d\nmov %r12,%rcx\nmov $0x3,%edx\nmov %rbx,%rsi\ncallq 1110 \ntest %eax,%eax\njne 12d5 \nmovslq 0x4c(%rsp),%rdx\nmov %rbx,%rsi\nmov %rbp,%rdi\ncallq 10f0 \nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nmov %rbp,%rdi\nrepnz scas %es:(%rdi),%al\nnot %rcx\nmovw $0x20,-0x1(%rbp,%rcx,1)\nmovslq 0x50(%rsp),%rax\nadd %rax,%rbx\njmp 1283 \nmov %rbx,%rsi\nmov %rbp,%rdi\ncallq 1130 \nmov %rsp,%rdi\ncallq 10c0 \nmov 0x468(%rsp),%rax\nxor %fs:0x28,%rax\njne 1307 \nadd $0x470,%rsp\npop %rbx\npop %rbp\npop %r12\nretq\ncallq 10d0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 470h\nmov r12, rdi\nmov rbp, rsi\nmov rax, fs:28h\nmov [rsp+488h+var_20], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"([a-z])([A-Z])\"\ncall _regcomp\nlea rbx, [rsp+488h+src]\nmov edx, 400h\nmov rsi, r12\nmov rdi, rbx\ncall ___strcpy_chk\nmov byte ptr [rbp+0], 0\nlea r12, [rsp+488h+pmatch]\njmp short loc_12EC\nloc_12C5:\nmovsxd rdx, [rsp+488h+var_43C]; n\nmov rsi, rbx; src\nmov rdi, rbp; dest\ncall _strncat\nmov rdi, rbp; s\ncall _strlen\nmov word ptr [rbp+rax+0], 20h ; ' '\nmovsxd rax, [rsp+488h+var_438]\nadd rbx, rax\nloc_12EC:\nmov rdi, rsp; preg\nmov r8d, 0; eflags\nmov rcx, r12; pmatch\nmov edx, 3; nmatch\nmov rsi, rbx; string\ncall _regexec\ntest eax, eax\njz short loc_12C5\nmov rsi, rbx; src\nmov rdi, rbp; dest\ncall _strcat\nmov rdi, rsp; preg\ncall _regfree\nmov rax, [rsp+488h+var_20]\nsub rax, fs:28h\njnz short loc_133B\nadd rsp, 470h\npop rbx\npop rbp\npop r12\nretn\nloc_133B:\ncall ___stack_chk_fail", + "ida_pseudo": "unsigned __int64 __fastcall func0(__int64 a1, char *a2)\n{\n char *v2; // rbx\n regex_t v4; // [rsp+0h] [rbp-488h] BYREF\n regmatch_t pmatch; // [rsp+40h] [rbp-448h] BYREF\n int v6; // [rsp+4Ch] [rbp-43Ch]\n int v7; // [rsp+50h] [rbp-438h]\n char src[1032]; // [rsp+60h] [rbp-428h] BYREF\n unsigned __int64 v9; // [rsp+468h] [rbp-20h]\n\n v9 = __readfsqword(0x28u);\n regcomp(&v4, \"([a-z])([A-Z])\", 1);\n v2 = src;\n __strcpy_chk(src, a1, 1024LL);\n *a2 = 0;\n while ( !regexec(&v4, v2, 3uLL, &pmatch, 0) )\n {\n strncat(a2, v2, v6);\n *(_WORD *)&a2[strlen(a2)] = 32;\n v2 += v7;\n }\n strcat(a2, v2);\n regfree(&v4);\n return v9 - __readfsqword(0x28u);\n}", + "ida_strip_asm": "sub_1269:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 470h\nmov r12, rdi\nmov rbp, rsi\nmov rax, fs:28h\nmov [rsp+488h+var_20], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"([a-z])([A-Z])\"\ncall _regcomp\nlea rbx, [rsp+488h+src]\nmov edx, 400h\nmov rsi, r12\nmov rdi, rbx\ncall ___strcpy_chk\nmov byte ptr [rbp+0], 0\nlea r12, [rsp+488h+pmatch]\njmp short loc_12EC\nloc_12C5:\nmovsxd rdx, [rsp+488h+var_43C]; n\nmov rsi, rbx; src\nmov rdi, rbp; dest\ncall _strncat\nmov rdi, rbp; s\ncall _strlen\nmov word ptr [rbp+rax+0], 20h ; ' '\nmovsxd rax, [rsp+488h+var_438]\nadd rbx, rax\nloc_12EC:\nmov rdi, rsp; preg\nmov r8d, 0; eflags\nmov rcx, r12; pmatch\nmov edx, 3; nmatch\nmov rsi, rbx; string\ncall _regexec\ntest eax, eax\njz short loc_12C5\nmov rsi, rbx; src\nmov rdi, rbp; dest\ncall _strcat\nmov rdi, rsp; preg\ncall _regfree\nmov rax, [rsp+488h+var_20]\nsub rax, fs:28h\njnz short loc_133B\nadd rsp, 470h\npop rbx\npop rbp\npop r12\nretn\nloc_133B:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_1269(__int64 a1, char *a2)\n{\n char *v2; // rbx\n regex_t v4; // [rsp+0h] [rbp-488h] BYREF\n regmatch_t pmatch; // [rsp+40h] [rbp-448h] BYREF\n int v6; // [rsp+4Ch] [rbp-43Ch]\n int v7; // [rsp+50h] [rbp-438h]\n char src[1032]; // [rsp+60h] [rbp-428h] BYREF\n unsigned __int64 v9; // [rsp+468h] [rbp-20h]\n\n v9 = __readfsqword(0x28u);\n regcomp(&v4, \"([a-z])([A-Z])\", 1);\n v2 = src;\n __strcpy_chk(src, a1, 1024LL);\n *a2 = 0;\n while ( !regexec(&v4, v2, 3uLL, &pmatch, 0) )\n {\n strncat(a2, v2, v6);\n *(_WORD *)&a2[strlen(a2)] = 32;\n v2 += v7;\n }\n strcat(a2, v2);\n regfree(&v4);\n return v9 - __readfsqword(0x28u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_1269(long long a1, char *a2) {\n char *v2;\n regex_t v4;\n regmatch_t pmatch;\n int v6;\n int v7;\n char src[1032];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n regcomp(&v4, \"([a-z])([A-Z])\", 1);\n v2 = src;\n __strcpy_chk(src, a1, 1024LL);\n *a2 = 0;\n while (!regexec(&v4, v2, 3uLL, &pmatch, 0)) {\n strncat(a2, v2, v6);\n *(unsigned short *)&a2[strlen(a2)] = 32;\n v2 += v7;\n }\n strcat(a2, v2);\n regfree(&v4);\n return v9 - __readfsqword(40u);\n}", + "ida_pseudo_norm": "unsigned long long func0(long long a1, char *a2) {\n char *v2;\n regex_t v4;\n regmatch_t pmatch;\n int v6;\n int v7;\n char src[1032];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n regcomp(&v4, \"([a-z])([A-Z])\", 1);\n v2 = src;\n __strcpy_chk(src, a1, 1024LL);\n *a2 = 0;\n while (!regexec(&v4, v2, 3uLL, &pmatch, 0)) {\n strncat(a2, v2, v6);\n *(unsigned short *)&a2[strlen(a2)] = 32;\n v2 += v7;\n }\n strcat(a2, v2);\n regfree(&v4);\n return v9 - __readfsqword(40u);\n}" + }, + { + "index": 748, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(const char *str1, char *result) {\n regex_t regex;\n regmatch_t matches[3];\n char buffer[1024];\n regcomp(®ex, \"([a-z])([A-Z])\", REG_EXTENDED);\n strcpy(buffer, str1);\n const char *cursor = buffer;\n result[0] = '\\0';\n while (regexec(®ex, cursor, 3, matches, 0) == 0) {\n strncat(result, cursor, matches[1].rm_eo);\n strcat(result, \" \");\n cursor += matches[2].rm_so;\n }\n strcat(result, cursor);\n regfree(®ex);\n}", + "test": "int main() {\n\n char result[1024];\n\n\n\n func0(\"Python\", result);\n\n assert(strcmp(result, \"Python\") == 0);\n\n\n\n func0(\"PythonProgrammingExamples\", result);\n\n assert(strcmp(result, \"Python Programming Examples\") == 0);\n\n\n\n func0(\"GetReadyToBeCodingFreak\", result);\n\n assert(strcmp(result, \"Get Ready To Be Coding Freak\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\nmov $0x1,%edx\nmov %rdi,%r14\npush %r13\npush %r12\nmov %rsi,%r12\nlea 0xc18(%rip),%rsi\npush %rbp\npush %rbx\nsub $0x470,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x468(%rsp)\nxor %eax,%eax\nmov %rsp,%r13\nlea 0x60(%rsp),%rbp\nlea 0x40(%rsp),%rbx\nmov %r13,%rdi\ncallq 1120 \nmov $0x400,%edx\nmov %r14,%rsi\nmov %rbp,%rdi\ncallq 1140 <__strcpy_chk@plt>\nmovb $0x0,(%r12)\njmp 1462 \nnopl 0x0(%rax)\nmovslq 0x4c(%rsp),%rdx\nmov %rbp,%rsi\nmov %r12,%rdi\ncallq 1110 \nmov %r12,%rdi\ncallq 10e0 \nmov $0x20,%edx\nmov %dx,(%r12,%rax,1)\nmovslq 0x50(%rsp),%rax\nadd %rax,%rbp\nxor %r8d,%r8d\nmov %rbx,%rcx\nmov $0x3,%edx\nmov %rbp,%rsi\nmov %r13,%rdi\ncallq 1130 \ntest %eax,%eax\nje 1438 \nmov %rbp,%rsi\nmov %r12,%rdi\ncallq 1150 \nmov %r13,%rdi\ncallq 10d0 \nmov 0x468(%rsp),%rax\nxor %fs:0x28,%rax\njne 14b2 \nadd $0x470,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\ncallq 10f0 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r13\nmov edx, 1; cflags\nmov r13, rdi\npush r12\npush rbp\nmov rbp, rsi\nlea rsi, pattern; \"([a-z])([A-Z])\"\npush rbx\nsub rsp, 478h\nmov rax, fs:28h\nmov [rsp+498h+var_30], rax\nxor eax, eax\nmov r12, rsp\nlea rbx, [rsp+498h+src]\nmov rdi, r12; preg\ncall _regcomp\nmov rsi, r13\nmov edx, 400h\nmov rdi, rbx\ncall ___strcpy_chk\nlea r13, [rsp+498h+pmatch]\nmov byte ptr [rbp+0], 0\njmp short loc_1452\nloc_1428:\nmovsxd rdx, [rsp+498h+var_44C]; n\nmov rsi, rbx; src\nmov rdi, rbp; dest\ncall _strncat\nmov rdi, rbp; s\ncall _strlen\nmov edx, 20h ; ' '\nmov [rbp+rax+0], dx\nmovsxd rax, [rsp+498h+var_448]\nadd rbx, rax\nloc_1452:\nxor r8d, r8d; eflags\nmov rcx, r13; pmatch\nmov edx, 3; nmatch\nmov rsi, rbx; string\nmov rdi, r12; preg\ncall _regexec\ntest eax, eax\njz short loc_1428\nmov rdi, rbp; dest\nmov rsi, rbx; src\ncall _strcat\nmov rdi, r12; preg\ncall _regfree\nmov rax, [rsp+498h+var_30]\nsub rax, fs:28h\njnz short loc_14A0\nadd rsp, 478h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_14A0:\ncall ___stack_chk_fail", + "ida_pseudo": "unsigned __int64 __fastcall func0(__int64 a1, char *a2)\n{\n char *v2; // rbx\n regex_t v4; // [rsp+0h] [rbp-498h] BYREF\n regmatch_t pmatch; // [rsp+40h] [rbp-458h] BYREF\n int v6; // [rsp+4Ch] [rbp-44Ch]\n int v7; // [rsp+50h] [rbp-448h]\n char src[1032]; // [rsp+60h] [rbp-438h] BYREF\n unsigned __int64 v9; // [rsp+468h] [rbp-30h]\n\n v9 = __readfsqword(0x28u);\n v2 = src;\n regcomp(&v4, \"([a-z])([A-Z])\", 1);\n __strcpy_chk(src, a1, 1024LL);\n *a2 = 0;\n while ( !regexec(&v4, v2, 3uLL, &pmatch, 0) )\n {\n strncat(a2, v2, v6);\n *(_WORD *)&a2[strlen(a2)] = 32;\n v2 += v7;\n }\n strcat(a2, v2);\n regfree(&v4);\n return v9 - __readfsqword(0x28u);\n}", + "ida_strip_asm": "sub_13C0:\nendbr64\npush r13\nmov edx, 1; cflags\nmov r13, rdi\npush r12\npush rbp\nmov rbp, rsi\nlea rsi, pattern; \"([a-z])([A-Z])\"\npush rbx\nsub rsp, 478h\nmov rax, fs:28h\nmov [rsp+498h+var_30], rax\nxor eax, eax\nmov r12, rsp\nlea rbx, [rsp+498h+src]\nmov rdi, r12; preg\ncall _regcomp\nmov rsi, r13\nmov edx, 400h\nmov rdi, rbx\ncall ___strcpy_chk\nlea r13, [rsp+498h+pmatch]\nmov byte ptr [rbp+0], 0\njmp short loc_1452\nloc_1428:\nmovsxd rdx, [rsp+498h+var_44C]; n\nmov rsi, rbx; src\nmov rdi, rbp; dest\ncall _strncat\nmov rdi, rbp; s\ncall _strlen\nmov edx, 20h ; ' '\nmov [rbp+rax+0], dx\nmovsxd rax, [rsp+498h+var_448]\nadd rbx, rax\nloc_1452:\nxor r8d, r8d; eflags\nmov rcx, r13; pmatch\nmov edx, 3; nmatch\nmov rsi, rbx; string\nmov rdi, r12; preg\ncall _regexec\ntest eax, eax\njz short loc_1428\nmov rdi, rbp; dest\nmov rsi, rbx; src\ncall _strcat\nmov rdi, r12; preg\ncall _regfree\nmov rax, [rsp+498h+var_30]\nsub rax, fs:28h\njnz short loc_14A0\nadd rsp, 478h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_14A0:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_13C0(__int64 a1, char *a2)\n{\n char *v2; // rbx\n regex_t v4; // [rsp+0h] [rbp-498h] BYREF\n regmatch_t pmatch; // [rsp+40h] [rbp-458h] BYREF\n int v6; // [rsp+4Ch] [rbp-44Ch]\n int v7; // [rsp+50h] [rbp-448h]\n char src[1032]; // [rsp+60h] [rbp-438h] BYREF\n unsigned __int64 v9; // [rsp+468h] [rbp-30h]\n\n v9 = __readfsqword(0x28u);\n v2 = src;\n regcomp(&v4, \"([a-z])([A-Z])\", 1);\n __strcpy_chk(src, a1, 1024LL);\n *a2 = 0;\n while ( !regexec(&v4, v2, 3uLL, &pmatch, 0) )\n {\n strncat(a2, v2, v6);\n *(_WORD *)&a2[strlen(a2)] = 32;\n v2 += v7;\n }\n strcat(a2, v2);\n regfree(&v4);\n return v9 - __readfsqword(0x28u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_13C0(long long a1, char *a2) {\n char *v2;\n regex_t v4;\n regmatch_t pmatch;\n int v6;\n int v7;\n char src[1032];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n v2 = src;\n regcomp(&v4, \"([a-z])([A-Z])\", 1);\n __strcpy_chk(src, a1, 1024LL);\n *a2 = 0;\n while (!regexec(&v4, v2, 3uLL, &pmatch, 0)) {\n strncat(a2, v2, v6);\n *(unsigned short *)&a2[strlen(a2)] = 32;\n v2 += v7;\n }\n strcat(a2, v2);\n regfree(&v4);\n return v9 - __readfsqword(40u);\n}", + "ida_pseudo_norm": "unsigned long long func0(long long a1, char *a2) {\n char *v2;\n regex_t v4;\n regmatch_t pmatch;\n int v6;\n int v7;\n char src[1032];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n v2 = src;\n regcomp(&v4, \"([a-z])([A-Z])\", 1);\n __strcpy_chk(src, a1, 1024LL);\n *a2 = 0;\n while (!regexec(&v4, v2, 3uLL, &pmatch, 0)) {\n strncat(a2, v2, v6);\n *(unsigned short *)&a2[strlen(a2)] = 32;\n v2 += v7;\n }\n strcat(a2, v2);\n regfree(&v4);\n return v9 - __readfsqword(40u);\n}" + }, + { + "index": 748, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(const char *str1, char *result) {\n regex_t regex;\n regmatch_t matches[3];\n char buffer[1024];\n regcomp(®ex, \"([a-z])([A-Z])\", REG_EXTENDED);\n strcpy(buffer, str1);\n const char *cursor = buffer;\n result[0] = '\\0';\n while (regexec(®ex, cursor, 3, matches, 0) == 0) {\n strncat(result, cursor, matches[1].rm_eo);\n strcat(result, \" \");\n cursor += matches[2].rm_so;\n }\n strcat(result, cursor);\n regfree(®ex);\n}", + "test": "int main() {\n\n char result[1024];\n\n\n\n func0(\"Python\", result);\n\n assert(strcmp(result, \"Python\") == 0);\n\n\n\n func0(\"PythonProgrammingExamples\", result);\n\n assert(strcmp(result, \"Python Programming Examples\") == 0);\n\n\n\n func0(\"GetReadyToBeCodingFreak\", result);\n\n assert(strcmp(result, \"Get Ready To Be Coding Freak\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\nmov $0x1,%edx\nmov %rdi,%r14\npush %r13\npush %r12\nmov %rsi,%r12\nlea 0xc18(%rip),%rsi\npush %rbp\npush %rbx\nsub $0x470,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x468(%rsp)\nxor %eax,%eax\nmov %rsp,%r13\nlea 0x60(%rsp),%rbp\nlea 0x40(%rsp),%rbx\nmov %r13,%rdi\ncallq 1120 \nmov $0x400,%edx\nmov %r14,%rsi\nmov %rbp,%rdi\ncallq 1140 <__strcpy_chk@plt>\nmovb $0x0,(%r12)\njmp 1462 \nnopl 0x0(%rax)\nmovslq 0x4c(%rsp),%rdx\nmov %rbp,%rsi\nmov %r12,%rdi\ncallq 1110 \nmov %r12,%rdi\ncallq 10e0 \nmov $0x20,%edx\nmov %dx,(%r12,%rax,1)\nmovslq 0x50(%rsp),%rax\nadd %rax,%rbp\nxor %r8d,%r8d\nmov %rbx,%rcx\nmov $0x3,%edx\nmov %rbp,%rsi\nmov %r13,%rdi\ncallq 1130 \ntest %eax,%eax\nje 1438 \nmov %rbp,%rsi\nmov %r12,%rdi\ncallq 1150 \nmov %r13,%rdi\ncallq 10d0 \nmov 0x468(%rsp),%rax\nxor %fs:0x28,%rax\njne 14b2 \nadd $0x470,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\ncallq 10f0 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r13\nmov edx, 1; cflags\nmov r13, rdi\npush r12\npush rbp\nmov rbp, rsi\nlea rsi, pattern; \"([a-z])([A-Z])\"\npush rbx\nsub rsp, 478h\nmov rax, fs:28h\nmov [rsp+498h+var_30], rax\nxor eax, eax\nmov r12, rsp\nlea rbx, [rsp+498h+src]\nmov rdi, r12; preg\ncall _regcomp\nmov rsi, r13\nmov edx, 400h\nmov rdi, rbx\ncall ___strcpy_chk\nlea r13, [rsp+498h+pmatch]\nmov byte ptr [rbp+0], 0\njmp short loc_1452\nloc_1428:\nmovsxd rdx, [rsp+498h+var_44C]; n\nmov rsi, rbx; src\nmov rdi, rbp; dest\ncall _strncat\nmov rdi, rbp; s\ncall _strlen\nmov edx, 20h ; ' '\nmov [rbp+rax+0], dx\nmovsxd rax, [rsp+498h+var_448]\nadd rbx, rax\nloc_1452:\nxor r8d, r8d; eflags\nmov rcx, r13; pmatch\nmov edx, 3; nmatch\nmov rsi, rbx; string\nmov rdi, r12; preg\ncall _regexec\ntest eax, eax\njz short loc_1428\nmov rdi, rbp; dest\nmov rsi, rbx; src\ncall _strcat\nmov rdi, r12; preg\ncall _regfree\nmov rax, [rsp+498h+var_30]\nsub rax, fs:28h\njnz short loc_14A0\nadd rsp, 478h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_14A0:\ncall ___stack_chk_fail", + "ida_pseudo": "unsigned __int64 __fastcall func0(__int64 a1, char *a2)\n{\n char *v2; // rbx\n regex_t v4; // [rsp+0h] [rbp-498h] BYREF\n regmatch_t pmatch; // [rsp+40h] [rbp-458h] BYREF\n int v6; // [rsp+4Ch] [rbp-44Ch]\n int v7; // [rsp+50h] [rbp-448h]\n char src[1032]; // [rsp+60h] [rbp-438h] BYREF\n unsigned __int64 v9; // [rsp+468h] [rbp-30h]\n\n v9 = __readfsqword(0x28u);\n v2 = src;\n regcomp(&v4, \"([a-z])([A-Z])\", 1);\n __strcpy_chk(src, a1, 1024LL);\n *a2 = 0;\n while ( !regexec(&v4, v2, 3uLL, &pmatch, 0) )\n {\n strncat(a2, v2, v6);\n *(_WORD *)&a2[strlen(a2)] = 32;\n v2 += v7;\n }\n strcat(a2, v2);\n regfree(&v4);\n return v9 - __readfsqword(0x28u);\n}", + "ida_strip_asm": "sub_13C0:\nendbr64\npush r13\nmov edx, 1; cflags\nmov r13, rdi\npush r12\npush rbp\nmov rbp, rsi\nlea rsi, pattern; \"([a-z])([A-Z])\"\npush rbx\nsub rsp, 478h\nmov rax, fs:28h\nmov [rsp+498h+var_30], rax\nxor eax, eax\nmov r12, rsp\nlea rbx, [rsp+498h+src]\nmov rdi, r12; preg\ncall _regcomp\nmov rsi, r13\nmov edx, 400h\nmov rdi, rbx\ncall ___strcpy_chk\nlea r13, [rsp+498h+pmatch]\nmov byte ptr [rbp+0], 0\njmp short loc_1452\nloc_1428:\nmovsxd rdx, [rsp+498h+var_44C]; n\nmov rsi, rbx; src\nmov rdi, rbp; dest\ncall _strncat\nmov rdi, rbp; s\ncall _strlen\nmov edx, 20h ; ' '\nmov [rbp+rax+0], dx\nmovsxd rax, [rsp+498h+var_448]\nadd rbx, rax\nloc_1452:\nxor r8d, r8d; eflags\nmov rcx, r13; pmatch\nmov edx, 3; nmatch\nmov rsi, rbx; string\nmov rdi, r12; preg\ncall _regexec\ntest eax, eax\njz short loc_1428\nmov rdi, rbp; dest\nmov rsi, rbx; src\ncall _strcat\nmov rdi, r12; preg\ncall _regfree\nmov rax, [rsp+498h+var_30]\nsub rax, fs:28h\njnz short loc_14A0\nadd rsp, 478h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_14A0:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_13C0(__int64 a1, char *a2)\n{\n char *v2; // rbx\n regex_t v4; // [rsp+0h] [rbp-498h] BYREF\n regmatch_t pmatch; // [rsp+40h] [rbp-458h] BYREF\n int v6; // [rsp+4Ch] [rbp-44Ch]\n int v7; // [rsp+50h] [rbp-448h]\n char src[1032]; // [rsp+60h] [rbp-438h] BYREF\n unsigned __int64 v9; // [rsp+468h] [rbp-30h]\n\n v9 = __readfsqword(0x28u);\n v2 = src;\n regcomp(&v4, \"([a-z])([A-Z])\", 1);\n __strcpy_chk(src, a1, 1024LL);\n *a2 = 0;\n while ( !regexec(&v4, v2, 3uLL, &pmatch, 0) )\n {\n strncat(a2, v2, v6);\n *(_WORD *)&a2[strlen(a2)] = 32;\n v2 += v7;\n }\n strcat(a2, v2);\n regfree(&v4);\n return v9 - __readfsqword(0x28u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_13C0(long long a1, char *a2) {\n char *v2;\n regex_t v4;\n regmatch_t pmatch;\n int v6;\n int v7;\n char src[1032];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n v2 = src;\n regcomp(&v4, \"([a-z])([A-Z])\", 1);\n __strcpy_chk(src, a1, 1024LL);\n *a2 = 0;\n while (!regexec(&v4, v2, 3uLL, &pmatch, 0)) {\n strncat(a2, v2, v6);\n *(unsigned short *)&a2[strlen(a2)] = 32;\n v2 += v7;\n }\n strcat(a2, v2);\n regfree(&v4);\n return v9 - __readfsqword(40u);\n}", + "ida_pseudo_norm": "unsigned long long func0(long long a1, char *a2) {\n char *v2;\n regex_t v4;\n regmatch_t pmatch;\n int v6;\n int v7;\n char src[1032];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n v2 = src;\n regcomp(&v4, \"([a-z])([A-Z])\", 1);\n __strcpy_chk(src, a1, 1024LL);\n *a2 = 0;\n while (!regexec(&v4, v2, 3uLL, &pmatch, 0)) {\n strncat(a2, v2, v6);\n *(unsigned short *)&a2[strlen(a2)] = 32;\n v2 += v7;\n }\n strcat(a2, v2);\n regfree(&v4);\n return v9 - __readfsqword(40u);\n}" + }, + { + "index": 749, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint int_cmp(const void* a, const void* b) {\n\n int int_a = *((int*)a);\n\n int int_b = *((int*)b);\n\n return int_a - int_b;\n\n}\n\n\n\n", + "func": "int* func0(const char* nums_str[], int size) {\n int* result = malloc(size * sizeof(int));\n if (!result) {\n perror(\"Malloc failed\");\n exit(EXIT_FAILURE);\n }\n for (int i = 0; i < size; i++) {\n result[i] = atoi(nums_str[i]);\n }\n qsort(result, size, sizeof(int), int_cmp);\n return result;\n}", + "test": "int main() {\n\n const char* test1[] = {\"4\",\"12\",\"45\",\"7\",\"0\",\"100\",\"200\",\"-12\",\"-500\"};\n\n int expected1[] = {-500, -12, 0, 4, 7, 12, 45, 100, 200};\n\n int *sorted1 = func0(test1, 9);\n\n for (int i = 0; i < 9; i++) {\n\n assert(sorted1[i] == expected1[i]);\n\n }\n\n free(sorted1);\n\n\n\n const char* test2[] = {\"2\",\"3\",\"8\",\"4\",\"7\",\"9\",\"8\",\"2\",\"6\",\"5\",\"1\",\"6\",\"1\",\"2\",\"3\",\"4\",\"6\",\"9\",\"1\",\"2\"};\n\n int expected2[] = {1, 1, 1, 2, 2, 2, 2, 3, 3, 4, 4, 5, 6, 6, 6, 7, 8, 8, 9, 9};\n\n int *sorted2 = func0(test2, 20);\n\n for (int i = 0; i < 20; i++) {\n\n assert(sorted2[i] == expected2[i]);\n\n }\n\n free(sorted2);\n\n\n\n const char* test3[] = {\"1\",\"3\",\"5\",\"7\",\"1\", \"3\",\"13\", \"15\", \"17\",\"5\", \"7\",\"9\",\"1\", \"11\"};\n\n int expected3[] = {1, 1, 1, 3, 3, 5, 5, 7, 7, 9, 11, 13, 15, 17};\n\n int *sorted3 = func0(test3, 14);\n\n for (int i = 0; i < 14; i++) {\n\n assert(sorted3[i] == expected3[i]);\n\n }\n\n free(sorted3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x28,%rsp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmov -0x2c(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 1100 \nmov %rax,-0x18(%rbp)\ncmpq $0x0,-0x18(%rbp)\njne 1299 \nlea 0xd7e(%rip),%rdi\ncallq 1110 \nmov $0x1,%edi\ncallq 1130 \nmovl $0x0,-0x1c(%rbp)\njmp 12dd \nmov -0x1c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0x1c(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x18(%rbp),%rdx\nlea (%rcx,%rdx,1),%rbx\nmov %rax,%rdi\ncallq 1120 \nmov %eax,(%rbx)\naddl $0x1,-0x1c(%rbp)\nmov -0x1c(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 12a2 \nmov -0x2c(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x18(%rbp),%rax\nlea -0xcd(%rip),%rcx\nmov $0x4,%edx\nmov %rax,%rdi\ncallq 10d0 \nmov -0x18(%rbp),%rax\nadd $0x28,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+base], rax\ncmp [rbp+base], 0\njnz short loc_129C\nlea rax, s; \"Malloc failed\"\nmov rdi, rax; s\ncall _perror\nmov edi, 1; status\ncall _exit\nloc_129C:\nmov [rbp+var_1C], 0\njmp short loc_12E0\nloc_12A5:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+base]\nlea rbx, [rcx+rdx]\nmov rdi, rax; nptr\ncall _atoi\nmov [rbx], eax\nadd [rbp+var_1C], 1\nloc_12E0:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_2C]\njl short loc_12A5\nmov eax, [rbp+var_2C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, int_cmp\nmov rcx, rdx; compar\nmov edx, 4; size\nmov rdi, rax; base\ncall _qsort\nmov rax, [rbp+base]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+14h] [rbp-1Ch]\n _DWORD *base; // [rsp+18h] [rbp-18h]\n\n base = malloc(4LL * a2);\n if ( !base )\n {\n perror(\"Malloc failed\");\n exit(1);\n }\n for ( i = 0; i < a2; ++i )\n base[i] = atoi(*(const char **)(8LL * i + a1));\n qsort(base, a2, 4uLL, int_cmp);\n return base;\n}", + "ida_strip_asm": "sub_1253:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+base], rax\ncmp [rbp+base], 0\njnz short loc_129C\nlea rax, s; \"Malloc failed\"\nmov rdi, rax; s\ncall _perror\nmov edi, 1; status\ncall _exit\nloc_129C:\nmov [rbp+var_1C], 0\njmp short loc_12E0\nloc_12A5:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+base]\nlea rbx, [rcx+rdx]\nmov rdi, rax; nptr\ncall _atoi\nmov [rbx], eax\nadd [rbp+var_1C], 1\nloc_12E0:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_2C]\njl short loc_12A5\nmov eax, [rbp+var_2C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 4; size\nmov rdi, rax; base\ncall _qsort\nmov rax, [rbp+base]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1253(__int64 a1, int a2)\n{\n int i; // [rsp+14h] [rbp-1Ch]\n _DWORD *base; // [rsp+18h] [rbp-18h]\n\n base = malloc(4LL * a2);\n if ( !base )\n {\n perror(\"Malloc failed\");\n exit(1);\n }\n for ( i = 0; i < a2; ++i )\n base[i] = atoi(*(const char **)(8LL * i + a1));\n qsort(base, a2, 4uLL, compar);\n return base;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1253(long long a1, int a2) {\n int i;\n uint32_t *base;\n base = malloc(4LL * a2);\n if (!base) {\n perror(\"Malloc failed\");\n exit(1);\n }\n for (i = 0; i < a2; ++i) base[i] = atoi(*(const char **)(8LL * i + a1));\n qsort(base, a2, 4uLL, compar);\n return base;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2) {\n int i;\n uint32_t *base;\n base = malloc(4LL * a2);\n if (!base) {\n perror(\"Malloc failed\");\n exit(1);\n }\n for (i = 0; i < a2; ++i) base[i] = atoi(*(const char **)(8LL * i + a1));\n qsort(base, a2, 4uLL, int_cmp);\n return base;\n}" + }, + { + "index": 749, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint int_cmp(const void* a, const void* b) {\n\n int int_a = *((int*)a);\n\n int int_b = *((int*)b);\n\n return int_a - int_b;\n\n}\n\n\n\n", + "func": "int* func0(const char* nums_str[], int size) {\n int* result = malloc(size * sizeof(int));\n if (!result) {\n perror(\"Malloc failed\");\n exit(EXIT_FAILURE);\n }\n for (int i = 0; i < size; i++) {\n result[i] = atoi(nums_str[i]);\n }\n qsort(result, size, sizeof(int), int_cmp);\n return result;\n}", + "test": "int main() {\n\n const char* test1[] = {\"4\",\"12\",\"45\",\"7\",\"0\",\"100\",\"200\",\"-12\",\"-500\"};\n\n int expected1[] = {-500, -12, 0, 4, 7, 12, 45, 100, 200};\n\n int *sorted1 = func0(test1, 9);\n\n for (int i = 0; i < 9; i++) {\n\n assert(sorted1[i] == expected1[i]);\n\n }\n\n free(sorted1);\n\n\n\n const char* test2[] = {\"2\",\"3\",\"8\",\"4\",\"7\",\"9\",\"8\",\"2\",\"6\",\"5\",\"1\",\"6\",\"1\",\"2\",\"3\",\"4\",\"6\",\"9\",\"1\",\"2\"};\n\n int expected2[] = {1, 1, 1, 2, 2, 2, 2, 3, 3, 4, 4, 5, 6, 6, 6, 7, 8, 8, 9, 9};\n\n int *sorted2 = func0(test2, 20);\n\n for (int i = 0; i < 20; i++) {\n\n assert(sorted2[i] == expected2[i]);\n\n }\n\n free(sorted2);\n\n\n\n const char* test3[] = {\"1\",\"3\",\"5\",\"7\",\"1\", \"3\",\"13\", \"15\", \"17\",\"5\", \"7\",\"9\",\"1\", \"11\"};\n\n int expected3[] = {1, 1, 1, 3, 3, 5, 5, 7, 7, 9, 11, 13, 15, 17};\n\n int *sorted3 = func0(test3, 14);\n\n for (int i = 0; i < 14; i++) {\n\n assert(sorted3[i] == expected3[i]);\n\n }\n\n free(sorted3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%r12\nmov %esi,%r15d\nmovslq %esi,%r14\nlea 0x0(,%r14,4),%rdi\ncallq 1110 \ntest %rax,%rax\nje 12bc \nmov %rax,%rbp\nlea -0x1(%r15),%r13d\nmov $0x0,%ebx\ntest %r15d,%r15d\njle 1293 \nmov (%r12,%rbx,8),%rdi\nmov $0xa,%edx\nmov $0x0,%esi\ncallq 1100 \nmov %eax,0x0(%rbp,%rbx,4)\nmov %rbx,%rax\nadd $0x1,%rbx\ncmp %r13,%rax\njne 1270 \nlea -0x71(%rip),%rcx\nmov $0x4,%edx\nmov %r14,%rsi\nmov %rbp,%rdi\ncallq 10d0 \nmov %rbp,%rax\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nlea 0xd41(%rip),%rdi\ncallq 1120 \nmov $0x1,%edi\ncallq 1130 \n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r12, rdi\nmov ebx, esi\nmovsxd r14, esi\nlea rdi, ds:0[r14*4]; size\ncall _malloc\ntest rax, rax\njz short loc_12AE\nmov r13, rax\ntest ebx, ebx\njle short loc_128B\nmov rbx, r12\nmov rbp, rax\nlea r12, [r12+r14*8]\nloc_1269:\nmov rdi, [rbx]; nptr\nmov edx, 0Ah; base\nmov esi, 0; endptr\ncall _strtol\nmov [rbp+0], eax\nadd rbx, 8\nadd rbp, 4\ncmp rbx, r12\njnz short loc_1269\nloc_128B:\nlea rcx, int_cmp; compar\nmov edx, 4; size\nmov rsi, r14; nmemb\nmov rdi, r13; base\ncall _qsort\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_12AE:\nlea rdi, s; \"Malloc failed\"\ncall _perror\nmov edi, 1; status\ncall _exit", + "ida_pseudo": "void *__fastcall func0(const char **a1, int a2)\n{\n void *v2; // rax\n void *v3; // r13\n const char **v4; // rbx\n _DWORD *v5; // rbp\n\n v2 = malloc(4LL * a2);\n if ( !v2 )\n {\n perror(\"Malloc failed\");\n exit(1);\n }\n v3 = v2;\n if ( a2 > 0 )\n {\n v4 = a1;\n v5 = v2;\n do\n *v5++ = strtol(*v4++, 0LL, 10);\n while ( v4 != &a1[a2] );\n }\n qsort(v3, a2, 4uLL, int_cmp);\n return v3;\n}", + "ida_strip_asm": "sub_1232:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r12, rdi\nmov ebx, esi\nmovsxd r14, esi\nlea rdi, ds:0[r14*4]; size\ncall _malloc\ntest rax, rax\njz short loc_12AE\nmov r13, rax\ntest ebx, ebx\njle short loc_128B\nmov rbx, r12\nmov rbp, rax\nlea r12, [r12+r14*8]\nloc_1269:\nmov rdi, [rbx]; nptr\nmov edx, 0Ah; base\nmov esi, 0; endptr\ncall _strtol\nmov [rbp+0], eax\nadd rbx, 8\nadd rbp, 4\ncmp rbx, r12\njnz short loc_1269\nloc_128B:\nlea rcx, compar; compar\nmov edx, 4; size\nmov rsi, r14; nmemb\nmov rdi, r13; base\ncall _qsort\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_12AE:\nlea rdi, s; \"Malloc failed\"\ncall _perror\nmov edi, 1; status\ncall _exit", + "ida_strip_pseudo": "void *__fastcall sub_1232(const char **a1, int a2)\n{\n void *v2; // rax\n void *v3; // r13\n const char **v4; // rbx\n _DWORD *v5; // rbp\n\n v2 = malloc(4LL * a2);\n if ( !v2 )\n {\n perror(\"Malloc failed\");\n exit(1);\n }\n v3 = v2;\n if ( a2 > 0 )\n {\n v4 = a1;\n v5 = v2;\n do\n *v5++ = strtol(*v4++, 0LL, 10);\n while ( v4 != &a1[a2] );\n }\n qsort(v3, a2, 4uLL, compar);\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1232(const char **a1, int a2) {\n void *v2;\n void *v3;\n const char **v4;\n uint32_t *v5;\n v2 = malloc(4LL * a2);\n if (!v2) {\n perror(\"Malloc failed\");\n exit(1);\n }\n v3 = v2;\n if (a2 > 0) {\n v4 = a1;\n v5 = v2;\n do\n *v5++ = strtol(*v4++, 0LL, 10);\n while (v4 != &a1[a2]);\n }\n qsort(v3, a2, 4uLL, compar);\n return v3;\n}", + "ida_pseudo_norm": "void *func0(const char **a1, int a2) {\n void *v2;\n void *v3;\n const char **v4;\n uint32_t *v5;\n v2 = malloc(4LL * a2);\n if (!v2) {\n perror(\"Malloc failed\");\n exit(1);\n }\n v3 = v2;\n if (a2 > 0) {\n v4 = a1;\n v5 = v2;\n do\n *v5++ = strtol(*v4++, 0LL, 10);\n while (v4 != &a1[a2]);\n }\n qsort(v3, a2, 4uLL, int_cmp);\n return v3;\n}" + }, + { + "index": 749, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint int_cmp(const void* a, const void* b) {\n\n int int_a = *((int*)a);\n\n int int_b = *((int*)b);\n\n return int_a - int_b;\n\n}\n\n\n\n", + "func": "int* func0(const char* nums_str[], int size) {\n int* result = malloc(size * sizeof(int));\n if (!result) {\n perror(\"Malloc failed\");\n exit(EXIT_FAILURE);\n }\n for (int i = 0; i < size; i++) {\n result[i] = atoi(nums_str[i]);\n }\n qsort(result, size, sizeof(int), int_cmp);\n return result;\n}", + "test": "int main() {\n\n const char* test1[] = {\"4\",\"12\",\"45\",\"7\",\"0\",\"100\",\"200\",\"-12\",\"-500\"};\n\n int expected1[] = {-500, -12, 0, 4, 7, 12, 45, 100, 200};\n\n int *sorted1 = func0(test1, 9);\n\n for (int i = 0; i < 9; i++) {\n\n assert(sorted1[i] == expected1[i]);\n\n }\n\n free(sorted1);\n\n\n\n const char* test2[] = {\"2\",\"3\",\"8\",\"4\",\"7\",\"9\",\"8\",\"2\",\"6\",\"5\",\"1\",\"6\",\"1\",\"2\",\"3\",\"4\",\"6\",\"9\",\"1\",\"2\"};\n\n int expected2[] = {1, 1, 1, 2, 2, 2, 2, 3, 3, 4, 4, 5, 6, 6, 6, 7, 8, 8, 9, 9};\n\n int *sorted2 = func0(test2, 20);\n\n for (int i = 0; i < 20; i++) {\n\n assert(sorted2[i] == expected2[i]);\n\n }\n\n free(sorted2);\n\n\n\n const char* test3[] = {\"1\",\"3\",\"5\",\"7\",\"1\", \"3\",\"13\", \"15\", \"17\",\"5\", \"7\",\"9\",\"1\", \"11\"};\n\n int expected3[] = {1, 1, 1, 3, 3, 5, 5, 7, 7, 9, 11, 13, 15, 17};\n\n int *sorted3 = func0(test3, 14);\n\n for (int i = 0; i < 14; i++) {\n\n assert(sorted3[i] == expected3[i]);\n\n }\n\n free(sorted3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\nmovslq %esi,%r14\npush %r13\npush %r12\npush %rbp\nmov %rdi,%rbp\nlea 0x0(,%r14,4),%rdi\npush %rbx\nsub $0x8,%rsp\ncallq 1110 \ntest %rax,%rax\nje 175a \nmov %rax,%r12\nlea -0x1(%r14),%r13d\nxor %ebx,%ebx\ntest %r14d,%r14d\njle 1731 \nnopl 0x0(%rax,%rax,1)\nmov 0x0(%rbp,%rbx,8),%rdi\nmov $0xa,%edx\nxor %esi,%esi\ncallq 1100 \nmov %eax,(%r12,%rbx,4)\nmov %rbx,%rax\nadd $0x1,%rbx\ncmp %rax,%r13\njne 1710 \nmov %r14,%rsi\nmov %r12,%rdi\nmov $0x4,%edx\nlea -0x83(%rip),%rcx\ncallq 10d0 \nadd $0x8,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nlea 0x8a3(%rip),%rdi\ncallq 1120 \nmov $0x1,%edi\ncallq 1130 \n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\nmovsxd r13, esi\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nlea rdi, ds:0[r13*4]; size\ncall _malloc\ntest rax, rax\njz func0_cold\nmov r12, rax\ntest r13d, r13d\njle short loc_179F\nmov rbp, rax\nlea r14, [rbx+r13*8]\nnop word ptr [rax+rax+00000000h]\nloc_1780:\nmov rdi, [rbx]; nptr\nmov edx, 0Ah; base\nxor esi, esi; endptr\nadd rbx, 8\nadd rbp, 4\ncall _strtol\nmov [rbp-4], eax\ncmp rbx, r14\njnz short loc_1780\nloc_179F:\nmov rsi, r13; nmemb\nmov rdi, r12; base\nmov edx, 4; size\nlea rcx, int_cmp; compar\ncall _qsort\npop rbx\nmov rax, r12\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "void *__fastcall func0(const char **a1, int a2)\n{\n const char **v2; // rbx\n void *v3; // rax\n void *v4; // r12\n _DWORD *v5; // rbp\n const char **v6; // r14\n const char *v7; // rdi\n\n v2 = a1;\n v3 = malloc(4LL * a2);\n if ( !v3 )\n func0_cold();\n v4 = v3;\n if ( a2 > 0 )\n {\n v5 = v3;\n v6 = &a1[a2];\n do\n {\n v7 = *v2++;\n *v5++ = strtol(v7, 0LL, 10);\n }\n while ( v2 != v6 );\n }\n qsort(v4, a2, 4uLL, int_cmp);\n return v4;\n}", + "ida_strip_asm": "sub_1740:\nendbr64\npush r14\npush r13\nmovsxd r13, esi\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nlea rdi, ds:0[r13*4]; size\ncall _malloc\ntest rax, rax\njz loc_1140\nmov r12, rax\ntest r13d, r13d\njle short loc_179F\nmov rbp, rax\nlea r14, [rbx+r13*8]\nnop word ptr [rax+rax+00000000h]\nloc_1780:\nmov rdi, [rbx]; nptr\nmov edx, 0Ah; base\nxor esi, esi; endptr\nadd rbx, 8\nadd rbp, 4\ncall _strtol\nmov [rbp-4], eax\ncmp rbx, r14\njnz short loc_1780\nloc_179F:\nmov rsi, r13; nmemb\nmov rdi, r12; base\nmov edx, 4; size\nlea rcx, compar; compar\ncall _qsort\npop rbx\nmov rax, r12\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "void *__fastcall sub_1740(const char **a1, int a2)\n{\n const char **v2; // rbx\n void *v3; // rax\n void *v4; // r12\n _DWORD *v5; // rbp\n const char **v6; // r14\n const char *v7; // rdi\n\n v2 = a1;\n v3 = malloc(4LL * a2);\n if ( !v3 )\n {\n perror(\"Malloc failed\");\n exit(1);\n }\n v4 = v3;\n if ( a2 > 0 )\n {\n v5 = v3;\n v6 = &a1[a2];\n do\n {\n v7 = *v2++;\n *v5++ = strtol(v7, 0LL, 10);\n }\n while ( v2 != v6 );\n }\n qsort(v4, a2, 4uLL, compar);\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1740(const char **a1, int a2) {\n const char **v2;\n void *v3;\n void *v4;\n uint32_t *v5;\n const char **v6;\n const char *v7;\n v2 = a1;\n v3 = malloc(4LL * a2);\n if (!v3) {\n perror(\"Malloc failed\");\n exit(1);\n }\n v4 = v3;\n if (a2 > 0) {\n v5 = v3;\n v6 = &a1[a2];\n do {\n v7 = *v2++;\n *v5++ = strtol(v7, 0LL, 10);\n } while (v2 != v6);\n }\n qsort(v4, a2, 4uLL, compar);\n return v4;\n}", + "ida_pseudo_norm": "void *func0(const char **a1, int a2) {\n const char **v2;\n void *v3;\n void *v4;\n uint32_t *v5;\n const char **v6;\n const char *v7;\n v2 = a1;\n v3 = malloc(4LL * a2);\n if (!v3) func0_cold();\n v4 = v3;\n if (a2 > 0) {\n v5 = v3;\n v6 = &a1[a2];\n do {\n v7 = *v2++;\n *v5++ = strtol(v7, 0LL, 10);\n } while (v2 != v6);\n }\n qsort(v4, a2, 4uLL, int_cmp);\n return v4;\n}" + }, + { + "index": 749, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint int_cmp(const void* a, const void* b) {\n\n int int_a = *((int*)a);\n\n int int_b = *((int*)b);\n\n return int_a - int_b;\n\n}\n\n\n\n", + "func": "int* func0(const char* nums_str[], int size) {\n int* result = malloc(size * sizeof(int));\n if (!result) {\n perror(\"Malloc failed\");\n exit(EXIT_FAILURE);\n }\n for (int i = 0; i < size; i++) {\n result[i] = atoi(nums_str[i]);\n }\n qsort(result, size, sizeof(int), int_cmp);\n return result;\n}", + "test": "int main() {\n\n const char* test1[] = {\"4\",\"12\",\"45\",\"7\",\"0\",\"100\",\"200\",\"-12\",\"-500\"};\n\n int expected1[] = {-500, -12, 0, 4, 7, 12, 45, 100, 200};\n\n int *sorted1 = func0(test1, 9);\n\n for (int i = 0; i < 9; i++) {\n\n assert(sorted1[i] == expected1[i]);\n\n }\n\n free(sorted1);\n\n\n\n const char* test2[] = {\"2\",\"3\",\"8\",\"4\",\"7\",\"9\",\"8\",\"2\",\"6\",\"5\",\"1\",\"6\",\"1\",\"2\",\"3\",\"4\",\"6\",\"9\",\"1\",\"2\"};\n\n int expected2[] = {1, 1, 1, 2, 2, 2, 2, 3, 3, 4, 4, 5, 6, 6, 6, 7, 8, 8, 9, 9};\n\n int *sorted2 = func0(test2, 20);\n\n for (int i = 0; i < 20; i++) {\n\n assert(sorted2[i] == expected2[i]);\n\n }\n\n free(sorted2);\n\n\n\n const char* test3[] = {\"1\",\"3\",\"5\",\"7\",\"1\", \"3\",\"13\", \"15\", \"17\",\"5\", \"7\",\"9\",\"1\", \"11\"};\n\n int expected3[] = {1, 1, 1, 3, 3, 5, 5, 7, 7, 9, 11, 13, 15, 17};\n\n int *sorted3 = func0(test3, 14);\n\n for (int i = 0; i < 14; i++) {\n\n assert(sorted3[i] == expected3[i]);\n\n }\n\n free(sorted3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\nmovslq %esi,%r14\npush %r13\npush %r12\npush %rbp\nmov %rdi,%rbp\nlea 0x0(,%r14,4),%rdi\npush %rbx\nsub $0x8,%rsp\ncallq 1110 \ntest %rax,%rax\nje 17ca \nmov %rax,%r12\nlea -0x1(%r14),%r13d\nxor %ebx,%ebx\ntest %r14d,%r14d\njle 17a1 \nnopl 0x0(%rax,%rax,1)\nmov 0x0(%rbp,%rbx,8),%rdi\nmov $0xa,%edx\nxor %esi,%esi\ncallq 1100 \nmov %eax,(%r12,%rbx,4)\nmov %rbx,%rax\nadd $0x1,%rbx\ncmp %rax,%r13\njne 1780 \nmov %r14,%rsi\nmov %r12,%rdi\nmov $0x4,%edx\nlea -0x83(%rip),%rcx\ncallq 10d0 \nadd $0x8,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nlea 0x833(%rip),%rdi\ncallq 1120 \nmov $0x1,%edi\ncallq 1130 \n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\nmovsxd r13, esi\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nlea rdi, ds:0[r13*4]; size\ncall _malloc\ntest rax, rax\njz func0_cold\nmov r12, rax\ntest r13d, r13d\njle short loc_17AF\nmov rbp, rax\nlea r14, [rbx+r13*8]\nnop word ptr [rax+rax+00000000h]\nloc_1790:\nmov rdi, [rbx]; nptr\nmov edx, 0Ah; base\nxor esi, esi; endptr\nadd rbx, 8\nadd rbp, 4\ncall _strtol\nmov [rbp-4], eax\ncmp rbx, r14\njnz short loc_1790\nloc_17AF:\nmov rsi, r13; nmemb\nmov rdi, r12; base\nmov edx, 4; size\nlea rcx, int_cmp; compar\ncall _qsort\npop rbx\nmov rax, r12\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "void *__fastcall func0(const char **a1, int a2)\n{\n const char **v2; // rbx\n void *v3; // rax\n void *v4; // r12\n _DWORD *v5; // rbp\n const char **v6; // r14\n const char *v7; // rdi\n\n v2 = a1;\n v3 = malloc(4LL * a2);\n if ( !v3 )\n func0_cold();\n v4 = v3;\n if ( a2 > 0 )\n {\n v5 = v3;\n v6 = &a1[a2];\n do\n {\n v7 = *v2++;\n *v5++ = strtol(v7, 0LL, 10);\n }\n while ( v2 != v6 );\n }\n qsort(v4, a2, 4uLL, int_cmp);\n return v4;\n}", + "ida_strip_asm": "sub_1750:\nendbr64\npush r14\npush r13\nmovsxd r13, esi\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nlea rdi, ds:0[r13*4]; size\ncall _malloc\ntest rax, rax\njz loc_1140\nmov r12, rax\ntest r13d, r13d\njle short loc_17AF\nmov rbp, rax\nlea r14, [rbx+r13*8]\nnop word ptr [rax+rax+00000000h]\nloc_1790:\nmov rdi, [rbx]; nptr\nmov edx, 0Ah; base\nxor esi, esi; endptr\nadd rbx, 8\nadd rbp, 4\ncall _strtol\nmov [rbp-4], eax\ncmp rbx, r14\njnz short loc_1790\nloc_17AF:\nmov rsi, r13; nmemb\nmov rdi, r12; base\nmov edx, 4; size\nlea rcx, compar; compar\ncall _qsort\npop rbx\nmov rax, r12\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "void *__fastcall sub_1750(const char **a1, int a2)\n{\n const char **v2; // rbx\n void *v3; // rax\n void *v4; // r12\n _DWORD *v5; // rbp\n const char **v6; // r14\n const char *v7; // rdi\n\n v2 = a1;\n v3 = malloc(4LL * a2);\n if ( !v3 )\n {\n perror(\"Malloc failed\");\n exit(1);\n }\n v4 = v3;\n if ( a2 > 0 )\n {\n v5 = v3;\n v6 = &a1[a2];\n do\n {\n v7 = *v2++;\n *v5++ = strtol(v7, 0LL, 10);\n }\n while ( v2 != v6 );\n }\n qsort(v4, a2, 4uLL, compar);\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1750(const char **a1, int a2) {\n const char **v2;\n void *v3;\n void *v4;\n uint32_t *v5;\n const char **v6;\n const char *v7;\n v2 = a1;\n v3 = malloc(4LL * a2);\n if (!v3) {\n perror(\"Malloc failed\");\n exit(1);\n }\n v4 = v3;\n if (a2 > 0) {\n v5 = v3;\n v6 = &a1[a2];\n do {\n v7 = *v2++;\n *v5++ = strtol(v7, 0LL, 10);\n } while (v2 != v6);\n }\n qsort(v4, a2, 4uLL, compar);\n return v4;\n}", + "ida_pseudo_norm": "void *func0(const char **a1, int a2) {\n const char **v2;\n void *v3;\n void *v4;\n uint32_t *v5;\n const char **v6;\n const char *v7;\n v2 = a1;\n v3 = malloc(4LL * a2);\n if (!v3) func0_cold();\n v4 = v3;\n if (a2 > 0) {\n v5 = v3;\n v6 = &a1[a2];\n do {\n v7 = *v2++;\n *v5++ = strtol(v7, 0LL, 10);\n } while (v2 != v6);\n }\n qsort(v4, a2, 4uLL, int_cmp);\n return v4;\n}" + }, + { + "index": 750, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int* test_list, int list_size, int* test_tup, int tup_size,\n int* new_size) {\n *new_size = list_size + tup_size;\n int* result = malloc(*new_size * sizeof(int));\n for (int i = 0; i < list_size; i++) {\n result[i] = test_list[i];\n }\n for (int i = 0; i < tup_size; i++) {\n result[list_size + i] = test_tup[i];\n }\n return result;\n}", + "test": "int main() {\n\n int test_list1[] = {5, 6, 7};\n\n int test_tup1[] = {9, 10};\n\n int new_size1;\n\n int* result1 = func0(test_list1, 3, test_tup1, 2, &new_size1);\n\n assert(new_size1 == 5 && result1[0] == 5 && result1[1] == 6 && result1[2] == 7 && result1[3] == 9 && result1[4] == 10);\n\n free(result1);\n\n\n\n int test_list2[] = {6, 7, 8};\n\n int test_tup2[] = {10, 11};\n\n int new_size2;\n\n int* result2 = func0(test_list2, 3, test_tup2, 2, &new_size2);\n\n assert(new_size2 == 5 && result2[0] == 6 && result2[1] == 7 && result2[2] == 8 && result2[3] == 10 && result2[4] == 11);\n\n free(result2);\n\n\n\n int test_list3[] = {7, 8, 9};\n\n int test_tup3[] = {11, 12};\n\n int new_size3;\n\n int* result3 = func0(test_list3, 3, test_tup3, 2, &new_size3);\n\n assert(new_size3 == 5 && result3[0] == 7 && result3[1] == 8 && result3[2] == 9 && result3[3] == 11 && result3[4] == 12);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %ecx,-0x20(%rbp)\nmov %r8,-0x30(%rbp)\nmov -0x1c(%rbp),%edx\nmov -0x20(%rbp),%eax\nadd %eax,%edx\nmov -0x30(%rbp),%rax\nmov %edx,(%rax)\nmov -0x30(%rbp),%rax\nmov (%rax),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0x10(%rbp)\njmp 1227 \nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0x10(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x10(%rbp)\nmov -0x10(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11f6 \nmovl $0x0,-0xc(%rbp)\njmp 126e \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov -0x1c(%rbp),%ecx\nmov -0xc(%rbp),%edx\nadd %ecx,%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x20(%rbp),%eax\njl 1238 \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov [rbp+var_30], r8\nmov edx, [rbp+var_1C]\nmov eax, [rbp+var_20]\nadd edx, eax\nmov rax, [rbp+var_30]\nmov [rax], edx\nmov rax, [rbp+var_30]\nmov eax, [rax]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_10], 0\njmp short loc_1227\nloc_11F6:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_10], 1\nloc_1227:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_1C]\njl short loc_11F6\nmov [rbp+var_C], 0\njmp short loc_126E\nloc_1238:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov ecx, [rbp+var_1C]\nmov edx, [rbp+var_C]\nadd edx, ecx\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_C], 1\nloc_126E:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_20]\njl short loc_1238\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, __int64 a3, int a4, int *a5)\n{\n int i; // [rsp+20h] [rbp-10h]\n int j; // [rsp+24h] [rbp-Ch]\n _DWORD *v10; // [rsp+28h] [rbp-8h]\n\n *a5 = a4 + a2;\n v10 = malloc(4LL * *a5);\n for ( i = 0; i < a2; ++i )\n v10[i] = *(_DWORD *)(4LL * i + a1);\n for ( j = 0; j < a4; ++j )\n v10[a2 + j] = *(_DWORD *)(4LL * j + a3);\n return v10;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov [rbp+var_30], r8\nmov edx, [rbp+var_1C]\nmov eax, [rbp+var_20]\nadd edx, eax\nmov rax, [rbp+var_30]\nmov [rax], edx\nmov rax, [rbp+var_30]\nmov eax, [rax]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_10], 0\njmp short loc_1227\nloc_11F6:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_10], 1\nloc_1227:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_1C]\njl short loc_11F6\nmov [rbp+var_C], 0\njmp short loc_126E\nloc_1238:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov ecx, [rbp+var_1C]\nmov edx, [rbp+var_C]\nadd edx, ecx\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_C], 1\nloc_126E:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_20]\njl short loc_1238\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(__int64 a1, int a2, __int64 a3, int a4, int *a5)\n{\n int i; // [rsp+20h] [rbp-10h]\n int j; // [rsp+24h] [rbp-Ch]\n _DWORD *v10; // [rsp+28h] [rbp-8h]\n\n *a5 = a4 + a2;\n v10 = malloc(4LL * *a5);\n for ( i = 0; i < a2; ++i )\n v10[i] = *(_DWORD *)(4LL * i + a1);\n for ( j = 0; j < a4; ++j )\n v10[a2 + j] = *(_DWORD *)(4LL * j + a3);\n return v10;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(long long a1, int a2, long long a3, int a4, int *a5) {\n int i;\n int j;\n uint32_t *v10;\n *a5 = a4 + a2;\n v10 = malloc(4LL * *a5);\n for (i = 0; i < a2; ++i) v10[i] = *(uint32_t *)(4LL * i + a1);\n for (j = 0; j < a4; ++j) v10[a2 + j] = *(uint32_t *)(4LL * j + a3);\n return v10;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, long long a3, int a4, int *a5) {\n int i;\n int j;\n uint32_t *v10;\n *a5 = a4 + a2;\n v10 = malloc(4LL * *a5);\n for (i = 0; i < a2; ++i) v10[i] = *(uint32_t *)(4LL * i + a1);\n for (j = 0; j < a4; ++j) v10[a2 + j] = *(uint32_t *)(4LL * j + a3);\n return v10;\n}" + }, + { + "index": 750, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int* test_list, int list_size, int* test_tup, int tup_size,\n int* new_size) {\n *new_size = list_size + tup_size;\n int* result = malloc(*new_size * sizeof(int));\n for (int i = 0; i < list_size; i++) {\n result[i] = test_list[i];\n }\n for (int i = 0; i < tup_size; i++) {\n result[list_size + i] = test_tup[i];\n }\n return result;\n}", + "test": "int main() {\n\n int test_list1[] = {5, 6, 7};\n\n int test_tup1[] = {9, 10};\n\n int new_size1;\n\n int* result1 = func0(test_list1, 3, test_tup1, 2, &new_size1);\n\n assert(new_size1 == 5 && result1[0] == 5 && result1[1] == 6 && result1[2] == 7 && result1[3] == 9 && result1[4] == 10);\n\n free(result1);\n\n\n\n int test_list2[] = {6, 7, 8};\n\n int test_tup2[] = {10, 11};\n\n int new_size2;\n\n int* result2 = func0(test_list2, 3, test_tup2, 2, &new_size2);\n\n assert(new_size2 == 5 && result2[0] == 6 && result2[1] == 7 && result2[2] == 8 && result2[3] == 10 && result2[4] == 11);\n\n free(result2);\n\n\n\n int test_list3[] = {7, 8, 9};\n\n int test_tup3[] = {11, 12};\n\n int new_size3;\n\n int* result3 = func0(test_list3, 3, test_tup3, 2, &new_size3);\n\n assert(new_size3 == 5 && result3[0] == 7 && result3[1] == 8 && result3[2] == 9 && result3[3] == 11 && result3[4] == 12);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbp\nmov %esi,%r12d\nmov %rdx,%rbx\nmov %ecx,%r13d\nlea (%rsi,%rcx,1),%edi\nmov %edi,(%r8)\nmovslq %edi,%rdi\nshl $0x2,%rdi\ncallq 10b0 \ntest %r12d,%r12d\njle 11f7 \nlea -0x1(%r12),%esi\nmov $0x0,%edx\nmov 0x0(%rbp,%rdx,4),%ecx\nmov %ecx,(%rax,%rdx,4)\nmov %rdx,%rcx\nadd $0x1,%rdx\ncmp %rsi,%rcx\njne 11e4 \ntest %r13d,%r13d\njle 121e \nlea -0x1(%r13),%edi\nmovslq %r12d,%r12\nlea (%rax,%r12,4),%rsi\nmov $0x0,%edx\nmov (%rbx,%rdx,4),%ecx\nmov %ecx,(%rsi,%rdx,4)\nmov %rdx,%rcx\nadd $0x1,%rdx\ncmp %rcx,%rdi\njne 120c \nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r13, rdi\nmov r12d, esi\nmov rbx, rdx\nmov ebp, ecx\nlea edi, [rsi+rcx]\nmov [r8], edi\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\ntest r12d, r12d\njle short loc_11F6\nmovsxd rsi, r12d\nshl rsi, 2\nmov edx, 0\nloc_11E5:\nmov ecx, [r13+rdx+0]\nmov [rax+rdx], ecx\nadd rdx, 4\ncmp rdx, rsi\njnz short loc_11E5\nloc_11F6:\ntest ebp, ebp\njle short loc_121C\nmovsxd rsi, ebp\nshl rsi, 2\nmovsxd r12, r12d\nlea rdi, [rax+r12*4]\nmov edx, 0\nloc_120D:\nmov ecx, [rbx+rdx]\nmov [rdi+rdx], ecx\nadd rdx, 4\ncmp rdx, rsi\njnz short loc_120D\nloc_121C:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2, __int64 a3, int a4, _DWORD *a5)\n{\n char *result; // rax\n __int64 v8; // rdx\n __int64 v9; // rdx\n\n *a5 = a2 + a4;\n result = (char *)malloc(4LL * (a2 + a4));\n if ( a2 > 0 )\n {\n v8 = 0LL;\n do\n {\n *(_DWORD *)&result[v8] = *(_DWORD *)(a1 + v8);\n v8 += 4LL;\n }\n while ( v8 != 4LL * a2 );\n }\n if ( a4 > 0 )\n {\n v9 = 0LL;\n do\n {\n *(_DWORD *)&result[4 * a2 + v9] = *(_DWORD *)(a3 + v9);\n v9 += 4LL;\n }\n while ( v9 != 4LL * a4 );\n }\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r13, rdi\nmov r12d, esi\nmov rbx, rdx\nmov ebp, ecx\nlea edi, [rsi+rcx]\nmov [r8], edi\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\ntest r12d, r12d\njle short loc_11F6\nmovsxd rsi, r12d\nshl rsi, 2\nmov edx, 0\nloc_11E5:\nmov ecx, [r13+rdx+0]\nmov [rax+rdx], ecx\nadd rdx, 4\ncmp rdx, rsi\njnz short loc_11E5\nloc_11F6:\ntest ebp, ebp\njle short loc_121C\nmovsxd rsi, ebp\nshl rsi, 2\nmovsxd r12, r12d\nlea rdi, [rax+r12*4]\nmov edx, 0\nloc_120D:\nmov ecx, [rbx+rdx]\nmov [rdi+rdx], ecx\nadd rdx, 4\ncmp rdx, rsi\njnz short loc_120D\nloc_121C:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11A9(__int64 a1, int a2, __int64 a3, int a4, _DWORD *a5)\n{\n char *result; // rax\n __int64 v8; // rdx\n __int64 v9; // rdx\n\n *a5 = a2 + a4;\n result = (char *)malloc(4LL * (a2 + a4));\n if ( a2 > 0 )\n {\n v8 = 0LL;\n do\n {\n *(_DWORD *)&result[v8] = *(_DWORD *)(a1 + v8);\n v8 += 4LL;\n }\n while ( v8 != 4LL * a2 );\n }\n if ( a4 > 0 )\n {\n v9 = 0LL;\n do\n {\n *(_DWORD *)&result[4 * a2 + v9] = *(_DWORD *)(a3 + v9);\n v9 += 4LL;\n }\n while ( v9 != 4LL * a4 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11A9(long long a1, int a2, long long a3, int a4, uint32_t *a5) {\n char *result;\n long long v8;\n long long v9;\n *a5 = a2 + a4;\n result = (char *)malloc(4LL * (a2 + a4));\n if (a2 > 0) {\n v8 = 0LL;\n do {\n *(uint32_t *)&result[v8] = *(uint32_t *)(a1 + v8);\n v8 += 4LL;\n } while (v8 != 4LL * a2);\n }\n if (a4 > 0) {\n v9 = 0LL;\n do {\n *(uint32_t *)&result[4 * a2 + v9] = *(uint32_t *)(a3 + v9);\n v9 += 4LL;\n } while (v9 != 4LL * a4);\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2, long long a3, int a4, uint32_t *a5) {\n char *result;\n long long v8;\n long long v9;\n *a5 = a2 + a4;\n result = (char *)malloc(4LL * (a2 + a4));\n if (a2 > 0) {\n v8 = 0LL;\n do {\n *(uint32_t *)&result[v8] = *(uint32_t *)(a1 + v8);\n v8 += 4LL;\n } while (v8 != 4LL * a2);\n }\n if (a4 > 0) {\n v9 = 0LL;\n do {\n *(uint32_t *)&result[4 * a2 + v9] = *(uint32_t *)(a3 + v9);\n v9 += 4LL;\n } while (v9 != 4LL * a4);\n }\n return result;\n}" + }, + { + "index": 750, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int* test_list, int list_size, int* test_tup, int tup_size,\n int* new_size) {\n *new_size = list_size + tup_size;\n int* result = malloc(*new_size * sizeof(int));\n for (int i = 0; i < list_size; i++) {\n result[i] = test_list[i];\n }\n for (int i = 0; i < tup_size; i++) {\n result[list_size + i] = test_tup[i];\n }\n return result;\n}", + "test": "int main() {\n\n int test_list1[] = {5, 6, 7};\n\n int test_tup1[] = {9, 10};\n\n int new_size1;\n\n int* result1 = func0(test_list1, 3, test_tup1, 2, &new_size1);\n\n assert(new_size1 == 5 && result1[0] == 5 && result1[1] == 6 && result1[2] == 7 && result1[3] == 9 && result1[4] == 10);\n\n free(result1);\n\n\n\n int test_list2[] = {6, 7, 8};\n\n int test_tup2[] = {10, 11};\n\n int new_size2;\n\n int* result2 = func0(test_list2, 3, test_tup2, 2, &new_size2);\n\n assert(new_size2 == 5 && result2[0] == 6 && result2[1] == 7 && result2[2] == 8 && result2[3] == 10 && result2[4] == 11);\n\n free(result2);\n\n\n\n int test_list3[] = {7, 8, 9};\n\n int test_tup3[] = {11, 12};\n\n int new_size3;\n\n int* result3 = func0(test_list3, 3, test_tup3, 2, &new_size3);\n\n assert(new_size3 == 5 && result3[0] == 7 && result3[1] == 8 && result3[2] == 9 && result3[3] == 11 && result3[4] == 12);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov %ecx,%r13d\npush %r12\nmovslq %esi,%r12\npush %rbp\nmov %rdi,%rbp\nlea (%r12,%rcx,1),%edi\npush %rbx\nmov %rdx,%rbx\nsub $0x8,%rsp\nmov %edi,(%r8)\nmovslq %edi,%rdi\nshl $0x2,%rdi\ncallq 10b0 \ntest %r12d,%r12d\njle 1415 \nlea -0x1(%r12),%edx\nxor %edi,%edi\nnopl 0x0(%rax)\nmov 0x0(%rbp,%rdi,4),%r8d\nmov %r8d,(%rax,%rdi,4)\nmov %rdi,%r8\nadd $0x1,%rdi\ncmp %rdx,%r8\njne 1400 \ntest %r13d,%r13d\njle 143a \nlea -0x1(%r13),%edi\nlea (%rax,%r12,4),%rdx\nxor %ecx,%ecx\nnopl 0x0(%rax)\nmov (%rbx,%rcx,4),%esi\nmov %esi,(%rdx,%rcx,4)\nmov %rcx,%rsi\nadd $0x1,%rcx\ncmp %rsi,%rdi\njne 1428 \nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\nmov r14, rdi\nlea edi, [rsi+rcx]\npush r13\npush r12\nmov r12, rdx\npush rbp\nmov ebp, esi\npush rbx\nmov ebx, ecx\nmov [r8], edi\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov r13, rax\ntest ebp, ebp\njle short loc_1410\nmov edx, ebp\nmov rsi, r14; src\nmov rdi, rax; dest\nshl rdx, 2; n\ncall _memcpy\nloc_1410:\ntest ebx, ebx\njle short loc_142A\nmovsxd rbp, ebp\nmov edx, ebx\nmov rsi, r12; src\nlea rdi, [r13+rbp*4+0]; dest\nshl rdx, 2; n\ncall _memcpy\nloc_142A:\npop rbx\nmov rax, r13\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "char *__fastcall func0(void *src, int a2, const void *a3, int a4, _DWORD *a5)\n{\n char *v7; // rax\n char *v8; // r13\n\n *a5 = a2 + a4;\n v7 = (char *)malloc(4LL * (a2 + a4));\n v8 = v7;\n if ( a2 > 0 )\n memcpy(v7, src, 4LL * (unsigned int)a2);\n if ( a4 > 0 )\n memcpy(&v8[4 * a2], a3, 4LL * (unsigned int)a4);\n return v8;\n}", + "ida_strip_asm": "sub_13D0:\nendbr64\npush r14\nmov r14, rdi\nlea edi, [rsi+rcx]\npush r13\npush r12\nmov r12, rdx\npush rbp\nmov ebp, esi\npush rbx\nmov ebx, ecx\nmov [r8], edi\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov r13, rax\ntest ebp, ebp\njle short loc_1410\nmov edx, ebp\nmov rsi, r14; src\nmov rdi, rax; dest\nshl rdx, 2; n\ncall _memcpy\nloc_1410:\ntest ebx, ebx\njle short loc_142A\nmovsxd rbp, ebp\nmov edx, ebx\nmov rsi, r12; src\nlea rdi, [r13+rbp*4+0]; dest\nshl rdx, 2; n\ncall _memcpy\nloc_142A:\npop rbx\nmov rax, r13\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "char *__fastcall sub_13D0(void *src, int a2, const void *a3, int a4, _DWORD *a5)\n{\n char *v7; // rax\n char *v8; // r13\n\n *a5 = a2 + a4;\n v7 = (char *)malloc(4LL * (a2 + a4));\n v8 = v7;\n if ( a2 > 0 )\n memcpy(v7, src, 4LL * (unsigned int)a2);\n if ( a4 > 0 )\n memcpy(&v8[4 * a2], a3, 4LL * (unsigned int)a4);\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_13D0(void *src, int a2, const void *a3, int a4, uint32_t *a5) {\n char *v7;\n char *v8;\n *a5 = a2 + a4;\n v7 = (char *)malloc(4LL * (a2 + a4));\n v8 = v7;\n if (a2 > 0) memcpy(v7, src, 4LL * (unsigned int)a2);\n if (a4 > 0) memcpy(&v8[4 * a2], a3, 4LL * (unsigned int)a4);\n return v8;\n}", + "ida_pseudo_norm": "char *func0(void *src, int a2, const void *a3, int a4, uint32_t *a5) {\n char *v7;\n char *v8;\n *a5 = a2 + a4;\n v7 = (char *)malloc(4LL * (a2 + a4));\n v8 = v7;\n if (a2 > 0) memcpy(v7, src, 4LL * (unsigned int)a2);\n if (a4 > 0) memcpy(&v8[4 * a2], a3, 4LL * (unsigned int)a4);\n return v8;\n}" + }, + { + "index": 750, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int* test_list, int list_size, int* test_tup, int tup_size,\n int* new_size) {\n *new_size = list_size + tup_size;\n int* result = malloc(*new_size * sizeof(int));\n for (int i = 0; i < list_size; i++) {\n result[i] = test_list[i];\n }\n for (int i = 0; i < tup_size; i++) {\n result[list_size + i] = test_tup[i];\n }\n return result;\n}", + "test": "int main() {\n\n int test_list1[] = {5, 6, 7};\n\n int test_tup1[] = {9, 10};\n\n int new_size1;\n\n int* result1 = func0(test_list1, 3, test_tup1, 2, &new_size1);\n\n assert(new_size1 == 5 && result1[0] == 5 && result1[1] == 6 && result1[2] == 7 && result1[3] == 9 && result1[4] == 10);\n\n free(result1);\n\n\n\n int test_list2[] = {6, 7, 8};\n\n int test_tup2[] = {10, 11};\n\n int new_size2;\n\n int* result2 = func0(test_list2, 3, test_tup2, 2, &new_size2);\n\n assert(new_size2 == 5 && result2[0] == 6 && result2[1] == 7 && result2[2] == 8 && result2[3] == 10 && result2[4] == 11);\n\n free(result2);\n\n\n\n int test_list3[] = {7, 8, 9};\n\n int test_tup3[] = {11, 12};\n\n int new_size3;\n\n int* result3 = func0(test_list3, 3, test_tup3, 2, &new_size3);\n\n assert(new_size3 == 5 && result3[0] == 7 && result3[1] == 8 && result3[2] == 9 && result3[3] == 11 && result3[4] == 12);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\nmov %rdi,%r14\npush %r13\npush %r12\nmov %ecx,%r12d\npush %rbp\nmov %rdx,%rbp\npush %rbx\nmovslq %esi,%rbx\nlea (%rbx,%rcx,1),%edi\nmov %edi,(%r8)\nmovslq %edi,%rdi\nshl $0x2,%rdi\ncallq 10d0 \nmov %rax,%r13\ntest %ebx,%ebx\njle 1427 \nlea -0x1(%rbx),%eax\nmov %r14,%rsi\nmov %r13,%rdi\nlea 0x4(,%rax,4),%rdx\ncallq 10c0 \ntest %r12d,%r12d\njle 1446 \nlea -0x1(%r12),%eax\nlea 0x0(%r13,%rbx,4),%rdi\nmov %rbp,%rsi\nlea 0x4(,%rax,4),%rdx\ncallq 10c0 \npop %rbx\nmov %r13,%rax\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r14\nmov r14, rdi\nlea edi, [rsi+rcx]\npush r13\npush r12\nmov r12, rdx\npush rbp\nmov ebp, esi\npush rbx\nmov ebx, ecx\nmov [r8], edi\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov r13, rax\ntest ebp, ebp\njle short loc_1410\nmov edx, ebp\nmov rsi, r14; src\nmov rdi, rax; dest\nshl rdx, 2; n\ncall _memcpy\nloc_1410:\ntest ebx, ebx\njle short loc_142A\nmovsxd rbp, ebp\nmov edx, ebx\nmov rsi, r12; src\nlea rdi, [r13+rbp*4+0]; dest\nshl rdx, 2; n\ncall _memcpy\nloc_142A:\npop rbx\nmov rax, r13\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "char *__fastcall func0(void *src, int a2, const void *a3, int a4, _DWORD *a5)\n{\n char *v7; // rax\n char *v8; // r13\n\n *a5 = a2 + a4;\n v7 = (char *)malloc(4LL * (a2 + a4));\n v8 = v7;\n if ( a2 > 0 )\n memcpy(v7, src, 4LL * (unsigned int)a2);\n if ( a4 > 0 )\n memcpy(&v8[4 * a2], a3, 4LL * (unsigned int)a4);\n return v8;\n}", + "ida_strip_asm": "sub_13D0:\nendbr64\npush r14\nmov r14, rdi\nlea edi, [rsi+rcx]\npush r13\npush r12\nmov r12, rdx\npush rbp\nmov ebp, esi\npush rbx\nmov ebx, ecx\nmov [r8], edi\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov r13, rax\ntest ebp, ebp\njle short loc_1410\nmov edx, ebp\nmov rsi, r14; src\nmov rdi, rax; dest\nshl rdx, 2; n\ncall _memcpy\nloc_1410:\ntest ebx, ebx\njle short loc_142A\nmovsxd rbp, ebp\nmov edx, ebx\nmov rsi, r12; src\nlea rdi, [r13+rbp*4+0]; dest\nshl rdx, 2; n\ncall _memcpy\nloc_142A:\npop rbx\nmov rax, r13\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "char *__fastcall sub_13D0(void *src, int a2, const void *a3, int a4, _DWORD *a5)\n{\n char *v7; // rax\n char *v8; // r13\n\n *a5 = a2 + a4;\n v7 = (char *)malloc(4LL * (a2 + a4));\n v8 = v7;\n if ( a2 > 0 )\n memcpy(v7, src, 4LL * (unsigned int)a2);\n if ( a4 > 0 )\n memcpy(&v8[4 * a2], a3, 4LL * (unsigned int)a4);\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_13D0(void *src, int a2, const void *a3, int a4, uint32_t *a5) {\n char *v7;\n char *v8;\n *a5 = a2 + a4;\n v7 = (char *)malloc(4LL * (a2 + a4));\n v8 = v7;\n if (a2 > 0) memcpy(v7, src, 4LL * (unsigned int)a2);\n if (a4 > 0) memcpy(&v8[4 * a2], a3, 4LL * (unsigned int)a4);\n return v8;\n}", + "ida_pseudo_norm": "char *func0(void *src, int a2, const void *a3, int a4, uint32_t *a5) {\n char *v7;\n char *v8;\n *a5 = a2 + a4;\n v7 = (char *)malloc(4LL * (a2 + a4));\n v8 = v7;\n if (a2 > 0) memcpy(v7, src, 4LL * (unsigned int)a2);\n if (a4 > 0) memcpy(&v8[4 * a2], a3, 4LL * (unsigned int)a4);\n return v8;\n}" + }, + { + "index": 751, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int arr[], int n, int i) {\n if (2 * i + 2 > n) {\n return true;\n }\n bool left_child = (arr[i] <= arr[2 * i + 1]) && func0(arr, n, 2 * i + 1);\n bool right_child = (2 * i + 2 == n) || (arr[i] <= arr[2 * i + 2]\n && func0(arr, n, 2 * i + 2));\n return left_child && right_child;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4, 5, 6};\n\n int arr2[] = {2, 3, 4, 5, 10, 15};\n\n int arr3[] = {2, 10, 4, 5, 3, 15};\n\n\n\n assert(func0(arr1, 6, 0) == true);\n\n assert(func0(arr2, 6, 0) == true);\n\n assert(func0(arr3, 6, 0) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmov -0x20(%rbp),%eax\nadd $0x1,%eax\nadd %eax,%eax\ncmp %eax,-0x1c(%rbp)\njge 1196 \nmov $0x1,%eax\njmpq 128b \nmov -0x20(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x20(%rbp),%eax\nadd %eax,%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njg 11f0 \nmov -0x20(%rbp),%eax\nadd %eax,%eax\nlea 0x1(%rax),%edx\nmov -0x1c(%rbp),%ecx\nmov -0x18(%rbp),%rax\nmov %ecx,%esi\nmov %rax,%rdi\ncallq 1169 \ntest %al,%al\nje 11f0 \nmov $0x1,%eax\njmp 11f5 \nmov $0x0,%eax\nmov %al,-0x2(%rbp)\nandb $0x1,-0x2(%rbp)\nmov -0x20(%rbp),%eax\nadd $0x1,%eax\nadd %eax,%eax\ncmp %eax,-0x1c(%rbp)\nje 125d \nmov -0x20(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x20(%rbp),%eax\nadd %eax,%eax\ncltq\nadd $0x2,%rax\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njg 1264 \nmov -0x20(%rbp),%eax\nadd $0x1,%eax\nlea (%rax,%rax,1),%edx\nmov -0x1c(%rbp),%ecx\nmov -0x18(%rbp),%rax\nmov %ecx,%esi\nmov %rax,%rdi\ncallq 1169 \ntest %al,%al\nje 1264 \nmov $0x1,%eax\njmp 1269 \nmov $0x0,%eax\nmov %al,-0x1(%rbp)\nandb $0x1,-0x1(%rbp)\ncmpb $0x0,-0x2(%rbp)\nje 1283 \ncmpb $0x0,-0x1(%rbp)\nje 1283 \nmov $0x1,%eax\njmp 1288 \nmov $0x0,%eax\nand $0x1,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov eax, [rbp+var_20]\nadd eax, 1\nadd eax, eax\ncmp [rbp+var_1C], eax\njge short loc_1196\nmov eax, 1\njmp locret_128B\nloc_1196:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_20]\nadd eax, eax\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njg short loc_11F0\nmov eax, [rbp+var_20]\nadd eax, eax\nlea edx, [rax+1]\nmov ecx, [rbp+var_1C]\nmov rax, [rbp+var_18]\nmov esi, ecx\nmov rdi, rax\ncall func0\ntest al, al\njz short loc_11F0\nmov eax, 1\njmp short loc_11F5\nloc_11F0:\nmov eax, 0\nloc_11F5:\nmov [rbp+var_2], al\nand [rbp+var_2], 1\nmov eax, [rbp+var_20]\nadd eax, 1\nadd eax, eax\ncmp [rbp+var_1C], eax\njz short loc_125D\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_20]\nadd eax, eax\ncdqe\nadd rax, 2\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njg short loc_1264\nmov eax, [rbp+var_20]\nadd eax, 1\nlea edx, [rax+rax]\nmov ecx, [rbp+var_1C]\nmov rax, [rbp+var_18]\nmov esi, ecx\nmov rdi, rax\ncall func0\ntest al, al\njz short loc_1264\nloc_125D:\nmov eax, 1\njmp short loc_1269\nloc_1264:\nmov eax, 0\nloc_1269:\nmov [rbp+var_1], al\nand [rbp+var_1], 1\ncmp [rbp+var_2], 0\njz short loc_1283\ncmp [rbp+var_1], 0\njz short loc_1283\nmov eax, 1\njmp short loc_1288\nloc_1283:\nmov eax, 0\nloc_1288:\nand eax, 1\nlocret_128B:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, unsigned int a2, int a3)\n{\n bool v4; // al\n bool v5; // al\n bool v8; // [rsp+1Eh] [rbp-2h]\n\n if ( (int)a2 < 2 * (a3 + 1) )\n return 1LL;\n v4 = *(_DWORD *)(4LL * a3 + a1) <= *(_DWORD *)(4 * (2 * a3 + 1LL) + a1)\n && (unsigned __int8)func0(a1, a2, (unsigned int)(2 * a3 + 1));\n v8 = v4;\n v5 = a2 == 2 * (a3 + 1)\n || *(_DWORD *)(4LL * a3 + a1) <= *(_DWORD *)(4 * (2 * a3 + 2LL) + a1)\n && (unsigned __int8)func0(a1, a2, (unsigned int)(2 * (a3 + 1)));\n return v8 && v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov eax, [rbp+var_20]\nadd eax, 1\nadd eax, eax\ncmp [rbp+var_1C], eax\njge short loc_1196\nmov eax, 1\njmp locret_128B\nloc_1196:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_20]\nadd eax, eax\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njg short loc_11F0\nmov eax, [rbp+var_20]\nadd eax, eax\nlea edx, [rax+1]\nmov ecx, [rbp+var_1C]\nmov rax, [rbp+var_18]\nmov esi, ecx\nmov rdi, rax\ncall sub_1169\ntest al, al\njz short loc_11F0\nmov eax, 1\njmp short loc_11F5\nloc_11F0:\nmov eax, 0\nloc_11F5:\nmov [rbp+var_2], al\nand [rbp+var_2], 1\nmov eax, [rbp+var_20]\nadd eax, 1\nadd eax, eax\ncmp [rbp+var_1C], eax\njz short loc_125D\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_20]\nadd eax, eax\ncdqe\nadd rax, 2\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njg short loc_1264\nmov eax, [rbp+var_20]\nadd eax, 1\nlea edx, [rax+rax]\nmov ecx, [rbp+var_1C]\nmov rax, [rbp+var_18]\nmov esi, ecx\nmov rdi, rax\ncall sub_1169\ntest al, al\njz short loc_1264\nloc_125D:\nmov eax, 1\njmp short loc_1269\nloc_1264:\nmov eax, 0\nloc_1269:\nmov [rbp+var_1], al\nand [rbp+var_1], 1\ncmp [rbp+var_2], 0\njz short loc_1283\ncmp [rbp+var_1], 0\njz short loc_1283\nmov eax, 1\njmp short loc_1288\nloc_1283:\nmov eax, 0\nloc_1288:\nand eax, 1\nlocret_128B:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, unsigned int a2, int a3)\n{\n bool v4; // al\n bool v5; // al\n bool v8; // [rsp+1Eh] [rbp-2h]\n\n if ( (int)a2 < 2 * (a3 + 1) )\n return 1LL;\n v4 = *(_DWORD *)(4LL * a3 + a1) <= *(_DWORD *)(4 * (2 * a3 + 1LL) + a1)\n && (unsigned __int8)sub_1169(a1, a2, (unsigned int)(2 * a3 + 1));\n v8 = v4;\n v5 = a2 == 2 * (a3 + 1)\n || *(_DWORD *)(4LL * a3 + a1) <= *(_DWORD *)(4 * (2 * a3 + 2LL) + a1)\n && (unsigned __int8)sub_1169(a1, a2, (unsigned int)(2 * (a3 + 1)));\n return v8 && v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, unsigned int a2, int a3) {\n bool v4;\n bool v5;\n bool v8;\n if ((int)a2 < 2 * (a3 + 1)) return 1LL;\n v4 = *(uint32_t *)(4LL * a3 + a1) <= *(uint32_t *)(4 * (2 * a3 + 1LL) + a1) &&\n (unsigned char)sub_1169(a1, a2, (unsigned int)(2 * a3 + 1));\n v8 = v4;\n v5 = a2 == 2 * (a3 + 1) ||\n *(uint32_t *)(4LL * a3 + a1) <= *(uint32_t *)(4 * (2 * a3 + 2LL) + a1) &&\n (unsigned char)sub_1169(a1, a2, (unsigned int)(2 * (a3 + 1)));\n return v8 && v5;\n}", + "ida_pseudo_norm": "long long func0(long long a1, unsigned int a2, int a3) {\n bool v4;\n bool v5;\n bool v8;\n if ((int)a2 < 2 * (a3 + 1)) return 1LL;\n v4 = *(uint32_t *)(4LL * a3 + a1) <= *(uint32_t *)(4 * (2 * a3 + 1LL) + a1) &&\n (unsigned char)func0(a1, a2, (unsigned int)(2 * a3 + 1));\n v8 = v4;\n v5 = a2 == 2 * (a3 + 1) ||\n *(uint32_t *)(4LL * a3 + a1) <= *(uint32_t *)(4 * (2 * a3 + 2LL) + a1) &&\n (unsigned char)func0(a1, a2, (unsigned int)(2 * (a3 + 1)));\n return v8 && v5;\n}" + }, + { + "index": 751, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int arr[], int n, int i) {\n if (2 * i + 2 > n) {\n return true;\n }\n bool left_child = (arr[i] <= arr[2 * i + 1]) && func0(arr, n, 2 * i + 1);\n bool right_child = (2 * i + 2 == n) || (arr[i] <= arr[2 * i + 2]\n && func0(arr, n, 2 * i + 2));\n return left_child && right_child;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4, 5, 6};\n\n int arr2[] = {2, 3, 4, 5, 10, 15};\n\n int arr3[] = {2, 10, 4, 5, 3, 15};\n\n\n\n assert(func0(arr1, 6, 0) == true);\n\n assert(func0(arr2, 6, 0) == true);\n\n assert(func0(arr3, 6, 0) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nlea 0x2(%rdx,%rdx,1),%r12d\nmov $0x1,%eax\ncmp %esi,%r12d\njg 11c7 \nmov %rdi,%rbx\nmov %esi,%ebp\nmovslq %edx,%rdx\nmov (%rdi,%rdx,4),%r15d\nlea -0x2(%r12),%r14d\nmovslq %r14d,%r14\nmov $0x0,%r13d\ncmp 0x4(%rdi,%r14,4),%r15d\njle 11d6 \nmov $0x1,%eax\ncmp %ebp,%r12d\nje 11c1 \nmov $0x0,%eax\ncmp 0x8(%rbx,%r14,4),%r15d\njle 11e6 \nand %r13d,%eax\nand $0x1,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nlea -0x1(%r12),%edx\ncallq 1169 \nmovzbl %al,%r13d\njmp 11ab \nmov %r12d,%edx\nmov %ebp,%esi\nmov %rbx,%rdi\ncallq 1169 \nmovzbl %al,%eax\njmp 11c1 \n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nlea r12d, [rdx+rdx+2]\nmov eax, 1\ncmp r12d, esi\njg short loc_11C2\nmov rbx, rdi\nmov ebp, esi\nmovsxd rdx, edx\nmov r14d, [rdi+rdx*4]\nlea eax, [r12-2]\ncdqe\nmov r13d, 0\ncmp r14d, [rdi+rax*4+4]\njle short loc_11CB\nloc_11A4:\nmov eax, 1\ncmp r12d, ebp\njz short loc_11BC\nmovsxd rdx, r12d\nmov eax, 0\ncmp r14d, [rbx+rdx*4]\njle short loc_11DB\nloc_11BC:\nand eax, r13d\nand eax, 1\nloc_11C2:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_11CB:\nlea edx, [r12-1]\ncall func0\nmovzx r13d, al\njmp short loc_11A4\nloc_11DB:\nmov edx, r12d\nmov esi, ebp\nmov rdi, rbx\ncall func0\nmovzx eax, al\njmp short loc_11BC", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n int v3; // r12d\n __int64 result; // rax\n int v5; // r14d\n unsigned __int8 v6; // r13\n char v7; // al\n\n v3 = 2 * a3 + 2;\n result = 1LL;\n if ( v3 <= (int)a2 )\n {\n v5 = *(_DWORD *)(a1 + 4LL * a3);\n v6 = 0;\n if ( v5 <= *(_DWORD *)(a1 + 8LL * a3 + 4) )\n v6 = func0(a1, a2, (unsigned int)(2 * a3 + 1));\n v7 = 1;\n if ( v3 != (_DWORD)a2 )\n {\n v7 = 0;\n if ( v5 <= *(_DWORD *)(a1 + 4LL * v3) )\n v7 = func0(a1, (unsigned int)a2, (unsigned int)v3);\n }\n return v6 & (unsigned __int8)v7 & 1;\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nlea r12d, [rdx+rdx+2]\nmov eax, 1\ncmp r12d, esi\njg short loc_11C2\nmov rbx, rdi\nmov ebp, esi\nmovsxd rdx, edx\nmov r14d, [rdi+rdx*4]\nlea eax, [r12-2]\ncdqe\nmov r13d, 0\ncmp r14d, [rdi+rax*4+4]\njle short loc_11CB\nloc_11A4:\nmov eax, 1\ncmp r12d, ebp\njz short loc_11BC\nmovsxd rdx, r12d\nmov eax, 0\ncmp r14d, [rbx+rdx*4]\njle short loc_11DB\nloc_11BC:\nand eax, r13d\nand eax, 1\nloc_11C2:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_11CB:\nlea edx, [r12-1]\ncall sub_1169\nmovzx r13d, al\njmp short loc_11A4\nloc_11DB:\nmov edx, r12d\nmov esi, ebp\nmov rdi, rbx\ncall sub_1169\nmovzx eax, al\njmp short loc_11BC", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, int a3)\n{\n int v3; // r12d\n __int64 result; // rax\n int v5; // r14d\n unsigned __int8 v6; // r13\n char v7; // al\n\n v3 = 2 * a3 + 2;\n result = 1LL;\n if ( v3 <= (int)a2 )\n {\n v5 = *(_DWORD *)(a1 + 4LL * a3);\n v6 = 0;\n if ( v5 <= *(_DWORD *)(a1 + 8LL * a3 + 4) )\n v6 = sub_1169(a1, a2, (unsigned int)(2 * a3 + 1));\n v7 = 1;\n if ( v3 != (_DWORD)a2 )\n {\n v7 = 0;\n if ( v5 <= *(_DWORD *)(a1 + 4LL * v3) )\n v7 = sub_1169(a1, (unsigned int)a2, (unsigned int)v3);\n }\n return v6 & (unsigned __int8)v7 & 1;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, int a3) {\n int v3;\n long long result;\n int v5;\n unsigned char v6;\n char v7;\n v3 = 2 * a3 + 2;\n result = 1LL;\n if (v3 <= (int)a2) {\n v5 = *(uint32_t *)(a1 + 4LL * a3);\n v6 = 0;\n if (v5 <= *(uint32_t *)(a1 + 8LL * a3 + 4))\n v6 = sub_1169(a1, a2, (unsigned int)(2 * a3 + 1));\n v7 = 1;\n if (v3 != (uint32_t)a2) {\n v7 = 0;\n if (v5 <= *(uint32_t *)(a1 + 4LL * v3))\n v7 = sub_1169(a1, (unsigned int)a2, (unsigned int)v3);\n }\n return v6 & (unsigned char)v7 & 1;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3) {\n int v3;\n long long result;\n int v5;\n unsigned char v6;\n char v7;\n v3 = 2 * a3 + 2;\n result = 1LL;\n if (v3 <= (int)a2) {\n v5 = *(uint32_t *)(a1 + 4LL * a3);\n v6 = 0;\n if (v5 <= *(uint32_t *)(a1 + 8LL * a3 + 4))\n v6 = func0(a1, a2, (unsigned int)(2 * a3 + 1));\n v7 = 1;\n if (v3 != (uint32_t)a2) {\n v7 = 0;\n if (v5 <= *(uint32_t *)(a1 + 4LL * v3))\n v7 = func0(a1, (unsigned int)a2, (unsigned int)v3);\n }\n return v6 & (unsigned char)v7 & 1;\n }\n return result;\n}" + }, + { + "index": 751, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int arr[], int n, int i) {\n if (2 * i + 2 > n) {\n return true;\n }\n bool left_child = (arr[i] <= arr[2 * i + 1]) && func0(arr, n, 2 * i + 1);\n bool right_child = (2 * i + 2 == n) || (arr[i] <= arr[2 * i + 2]\n && func0(arr, n, 2 * i + 2));\n return left_child && right_child;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4, 5, 6};\n\n int arr2[] = {2, 3, 4, 5, 10, 15};\n\n int arr3[] = {2, 10, 4, 5, 3, 15};\n\n\n\n assert(func0(arr1, 6, 0) == true);\n\n assert(func0(arr2, 6, 0) == true);\n\n assert(func0(arr3, 6, 0) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmov $0x1,%eax\npush %r14\npush %r13\nlea 0x2(%rdx,%rdx,1),%r13d\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\ncmp %esi,%r13d\njg 1313 \nlea -0x2(%r13),%ebx\nmovslq %edx,%rdx\nmov %rdi,%rbp\nmov %esi,%r12d\nmovslq %ebx,%rbx\nmov (%rdi,%rdx,4),%r15d\nxor %r14d,%r14d\ncmp 0x4(%rdi,%rbx,4),%r15d\njle 1328 \nmov %r14d,%eax\nand $0x1,%eax\ncmp %r12d,%r13d\nje 1313 \nxor %eax,%eax\ncmp 0x8(%rbp,%rbx,4),%r15d\njle 1348 \nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw 0x0(%rax,%rax,1)\nlea -0x1(%r13),%edx\ncallq 12c0 \nmovzbl %al,%r14d\nmov %r14d,%eax\nand $0x1,%eax\ncmp %r12d,%r13d\njne 130a \njmp 1313 \nnopw 0x0(%rax,%rax,1)\nmov %r13d,%edx\nmov %r12d,%esi\nmov %rbp,%rdi\ncallq 12c0 \nadd $0x8,%rsp\nand %r14d,%eax\npop %rbx\npop %rbp\nand $0x1,%eax\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\nmov eax, 1\npush r13\npush r12\nlea r12d, [rdx+rdx+2]\npush rbp\npush rbx\ncmp r12d, esi\njg short loc_12D9\nmovsxd rdx, edx\nmov rbx, rdi\nmov ebp, esi\nxor r13d, r13d\nmov r14d, [rdi+rdx*4]\nlea edx, [r12-2]\nmovsxd rdx, edx\ncmp r14d, [rdi+rdx*4+4]\njle short loc_1310\ncmp r12d, ebp\njz short loc_12F8\nloc_12CE:\nmovsxd rdx, r12d\nxor eax, eax\ncmp r14d, [rbx+rdx*4]\njle short loc_12E8\nloc_12D9:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_12E8:\nmov edx, r12d\nmov esi, ebp\nmov rdi, rbx\ncall func0\nand r13d, eax\nloc_12F8:\nmov eax, r13d\npop rbx\npop rbp\nand eax, 1\npop r12\npop r13\npop r14\nretn\nloc_1310:\nlea edx, [r12-1]\ncall func0\nmovzx r13d, al\ncmp r12d, ebp\njnz short loc_12CE\njmp short loc_12F8", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n __int64 result; // rax\n int v4; // r12d\n char v5; // r13\n int v6; // r14d\n\n result = 1LL;\n v4 = 2 * a3 + 2;\n if ( v4 <= (int)a2 )\n {\n v5 = 0;\n v6 = *(_DWORD *)(a1 + 4LL * a3);\n if ( v6 <= *(_DWORD *)(a1 + 8LL * a3 + 4) )\n {\n v5 = func0(a1, a2, (unsigned int)(2 * a3 + 1));\n if ( v4 == (_DWORD)a2 )\n return v5 & 1;\n }\n else if ( v4 == (_DWORD)a2 )\n {\n return v5 & 1;\n }\n result = 0LL;\n if ( v6 > *(_DWORD *)(a1 + 4LL * v4) )\n return result;\n v5 &= func0(a1, (unsigned int)a2, (unsigned int)v4);\n return v5 & 1;\n }\n return result;\n}", + "ida_strip_asm": "sub_1290:\nendbr64\npush r14\nmov eax, 1\npush r13\npush r12\nlea r12d, [rdx+rdx+2]\npush rbp\npush rbx\ncmp r12d, esi\njg short loc_12D9\nmovsxd rdx, edx\nmov rbx, rdi\nmov ebp, esi\nxor r13d, r13d\nmov r14d, [rdi+rdx*4]\nlea edx, [r12-2]\nmovsxd rdx, edx\ncmp r14d, [rdi+rdx*4+4]\njle short loc_1310\ncmp r12d, ebp\njz short loc_12F8\nloc_12CE:\nmovsxd rdx, r12d\nxor eax, eax\ncmp r14d, [rbx+rdx*4]\njle short loc_12E8\nloc_12D9:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_12E8:\nmov edx, r12d\nmov esi, ebp\nmov rdi, rbx\ncall sub_1290\nand r13d, eax\nloc_12F8:\nmov eax, r13d\npop rbx\npop rbp\nand eax, 1\npop r12\npop r13\npop r14\nretn\nloc_1310:\nlea edx, [r12-1]\ncall sub_1290\nmovzx r13d, al\ncmp r12d, ebp\njnz short loc_12CE\njmp short loc_12F8", + "ida_strip_pseudo": "__int64 __fastcall sub_1290(__int64 a1, __int64 a2, int a3)\n{\n __int64 result; // rax\n int v4; // r12d\n char v5; // r13\n int v6; // r14d\n\n result = 1LL;\n v4 = 2 * a3 + 2;\n if ( v4 <= (int)a2 )\n {\n v5 = 0;\n v6 = *(_DWORD *)(a1 + 4LL * a3);\n if ( v6 <= *(_DWORD *)(a1 + 8LL * a3 + 4) )\n {\n v5 = sub_1290(a1, a2, (unsigned int)(2 * a3 + 1));\n if ( v4 == (_DWORD)a2 )\n return v5 & 1;\n }\n else if ( v4 == (_DWORD)a2 )\n {\n return v5 & 1;\n }\n result = 0LL;\n if ( v6 > *(_DWORD *)(a1 + 4LL * v4) )\n return result;\n v5 &= sub_1290(a1, (unsigned int)a2, (unsigned int)v4);\n return v5 & 1;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1290(long long a1, long long a2, int a3) {\n long long result;\n int v4;\n char v5;\n int v6;\n result = 1LL;\n v4 = 2 * a3 + 2;\n if (v4 <= (int)a2) {\n v5 = 0;\n v6 = *(uint32_t *)(a1 + 4LL * a3);\n if (v6 <= *(uint32_t *)(a1 + 8LL * a3 + 4)) {\n v5 = sub_1290(a1, a2, (unsigned int)(2 * a3 + 1));\n if (v4 == (uint32_t)a2) return v5 & 1;\n } else if (v4 == (uint32_t)a2) {\n return v5 & 1;\n }\n result = 0LL;\n if (v6 > *(uint32_t *)(a1 + 4LL * v4)) return result;\n v5 &= sub_1290(a1, (unsigned int)a2, (unsigned int)v4);\n return v5 & 1;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3) {\n long long result;\n int v4;\n char v5;\n int v6;\n result = 1LL;\n v4 = 2 * a3 + 2;\n if (v4 <= (int)a2) {\n v5 = 0;\n v6 = *(uint32_t *)(a1 + 4LL * a3);\n if (v6 <= *(uint32_t *)(a1 + 8LL * a3 + 4)) {\n v5 = func0(a1, a2, (unsigned int)(2 * a3 + 1));\n if (v4 == (uint32_t)a2) return v5 & 1;\n } else if (v4 == (uint32_t)a2) {\n return v5 & 1;\n }\n result = 0LL;\n if (v6 > *(uint32_t *)(a1 + 4LL * v4)) return result;\n v5 &= func0(a1, (unsigned int)a2, (unsigned int)v4);\n return v5 & 1;\n }\n return result;\n}" + }, + { + "index": 751, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int arr[], int n, int i) {\n if (2 * i + 2 > n) {\n return true;\n }\n bool left_child = (arr[i] <= arr[2 * i + 1]) && func0(arr, n, 2 * i + 1);\n bool right_child = (2 * i + 2 == n) || (arr[i] <= arr[2 * i + 2]\n && func0(arr, n, 2 * i + 2));\n return left_child && right_child;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4, 5, 6};\n\n int arr2[] = {2, 3, 4, 5, 10, 15};\n\n int arr3[] = {2, 10, 4, 5, 3, 15};\n\n\n\n assert(func0(arr1, 6, 0) == true);\n\n assert(func0(arr2, 6, 0) == true);\n\n assert(func0(arr3, 6, 0) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmov $0x1,%eax\npush %r14\npush %r13\nlea 0x2(%rdx,%rdx,1),%r13d\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\ncmp %esi,%r13d\njg 12df \nlea -0x2(%r13),%ebx\nmovslq %edx,%rdx\nmov %rdi,%rbp\nmov %esi,%r12d\nmovslq %ebx,%rbx\nmov (%rdi,%rdx,4),%r14d\nxor %eax,%eax\nxor %r15d,%r15d\ncmp 0x4(%rdi,%rbx,4),%r14d\njle 12f0 \ncmp %r12d,%r13d\nje 12df \nxor %eax,%eax\ncmp 0x8(%rbp,%rbx,4),%r14d\njle 1308 \nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nxchg %ax,%ax\nlea -0x1(%r13),%edx\ncallq 1290 \nmovzbl %al,%r15d\ncmp %r12d,%r13d\njne 12d6 \njmp 12df \nnopl 0x0(%rax)\nmov %r13d,%edx\nmov %r12d,%esi\nmov %rbp,%rdi\ncallq 1290 \nadd $0x8,%rsp\nand %r15d,%eax\npop %rbx\npop %rbp\nand $0x1,%eax\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\nmov eax, 1\npush r13\npush r12\nlea r12d, [rdx+rdx+2]\npush rbp\npush rbx\ncmp r12d, esi\njg short loc_12CB\nmovsxd rdx, edx\nmov rbx, rdi\nmov ebp, esi\nxor eax, eax\nmov r13d, [rdi+rdx*4]\nlea edx, [r12-2]\nxor r14d, r14d\nmovsxd rdx, edx\ncmp r13d, [rdi+rdx*4+4]\njle short loc_12D8\ncmp r12d, ebp\njz short loc_12CB\nloc_12C0:\nmovsxd rdx, r12d\nxor eax, eax\ncmp r13d, [rbx+rdx*4]\njle short loc_12F0\nloc_12CB:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_12D8:\nlea edx, [r12-1]\ncall func0\nmovzx r14d, al\ncmp r12d, ebp\njnz short loc_12C0\njmp short loc_12CB\nloc_12F0:\nmov edx, r12d\nmov esi, ebp\nmov rdi, rbx\ncall func0\npop rbx\npop rbp\nand r14d, eax\npop r12\npop r13\nmov eax, r14d\npop r14\nand eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n __int64 result; // rax\n int v4; // r12d\n int v5; // r13d\n unsigned __int8 v6; // r14\n\n result = 1LL;\n v4 = 2 * a3 + 2;\n if ( v4 <= (int)a2 )\n {\n result = 0LL;\n v5 = *(_DWORD *)(a1 + 4LL * a3);\n v6 = 0;\n if ( v5 <= *(_DWORD *)(a1 + 8LL * a3 + 4) )\n {\n result = func0(a1, a2, (unsigned int)(2 * a3 + 1));\n v6 = result;\n if ( v4 == (_DWORD)a2 )\n return result;\n }\n else if ( v4 == (_DWORD)a2 )\n {\n return result;\n }\n result = 0LL;\n if ( v5 <= *(_DWORD *)(a1 + 4LL * v4) )\n return (unsigned __int8)func0(a1, (unsigned int)a2, (unsigned int)v4) & v6 & 1;\n }\n return result;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\npush r14\nmov eax, 1\npush r13\npush r12\nlea r12d, [rdx+rdx+2]\npush rbp\npush rbx\ncmp r12d, esi\njg short loc_12CB\nmovsxd rdx, edx\nmov rbx, rdi\nmov ebp, esi\nxor eax, eax\nmov r13d, [rdi+rdx*4]\nlea edx, [r12-2]\nxor r14d, r14d\nmovsxd rdx, edx\ncmp r13d, [rdi+rdx*4+4]\njle short loc_12D8\ncmp r12d, ebp\njz short loc_12CB\nloc_12C0:\nmovsxd rdx, r12d\nxor eax, eax\ncmp r13d, [rbx+rdx*4]\njle short loc_12F0\nloc_12CB:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_12D8:\nlea edx, [r12-1]\ncall sub_1280\nmovzx r14d, al\ncmp r12d, ebp\njnz short loc_12C0\njmp short loc_12CB\nloc_12F0:\nmov edx, r12d\nmov esi, ebp\nmov rdi, rbx\ncall sub_1280\npop rbx\npop rbp\nand r14d, eax\npop r12\npop r13\nmov eax, r14d\npop r14\nand eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1280(__int64 a1, __int64 a2, int a3)\n{\n __int64 result; // rax\n int v4; // r12d\n int v5; // r13d\n unsigned __int8 v6; // r14\n\n result = 1LL;\n v4 = 2 * a3 + 2;\n if ( v4 <= (int)a2 )\n {\n result = 0LL;\n v5 = *(_DWORD *)(a1 + 4LL * a3);\n v6 = 0;\n if ( v5 <= *(_DWORD *)(a1 + 8LL * a3 + 4) )\n {\n result = sub_1280(a1, a2, (unsigned int)(2 * a3 + 1));\n v6 = result;\n if ( v4 == (_DWORD)a2 )\n return result;\n }\n else if ( v4 == (_DWORD)a2 )\n {\n return result;\n }\n result = 0LL;\n if ( v5 <= *(_DWORD *)(a1 + 4LL * v4) )\n return (unsigned __int8)sub_1280(a1, (unsigned int)a2, (unsigned int)v4) & v6 & 1;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1280(long long a1, long long a2, int a3) {\n long long result;\n int v4;\n int v5;\n unsigned char v6;\n result = 1LL;\n v4 = 2 * a3 + 2;\n if (v4 <= (int)a2) {\n result = 0LL;\n v5 = *(uint32_t *)(a1 + 4LL * a3);\n v6 = 0;\n if (v5 <= *(uint32_t *)(a1 + 8LL * a3 + 4)) {\n result = sub_1280(a1, a2, (unsigned int)(2 * a3 + 1));\n v6 = result;\n if (v4 == (uint32_t)a2) return result;\n } else if (v4 == (uint32_t)a2) {\n return result;\n }\n result = 0LL;\n if (v5 <= *(uint32_t *)(a1 + 4LL * v4))\n return (unsigned char)sub_1280(a1, (unsigned int)a2, (unsigned int)v4) &\n v6 & 1;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3) {\n long long result;\n int v4;\n int v5;\n unsigned char v6;\n result = 1LL;\n v4 = 2 * a3 + 2;\n if (v4 <= (int)a2) {\n result = 0LL;\n v5 = *(uint32_t *)(a1 + 4LL * a3);\n v6 = 0;\n if (v5 <= *(uint32_t *)(a1 + 8LL * a3 + 4)) {\n result = func0(a1, a2, (unsigned int)(2 * a3 + 1));\n v6 = result;\n if (v4 == (uint32_t)a2) return result;\n } else if (v4 == (uint32_t)a2) {\n return result;\n }\n result = 0LL;\n if (v5 <= *(uint32_t *)(a1 + 4LL * v4))\n return (unsigned char)func0(a1, (unsigned int)a2, (unsigned int)v4) & v6 &\n 1;\n }\n return result;\n}" + }, + { + "index": 752, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int dp[n + 1];\n dp[0] = 0;\n dp[1] = 1;\n for (int i = 2; i <= n; i++) {\n dp[i] = dp[i - 1] + 2 * dp[i - 2];\n }\n return dp[n];\n}", + "test": "int main() {\n\n assert(func0(5) == 11);\n\n assert(func0(2) == 1);\n\n assert(func0(4) == 5);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x38,%rsp\nmov %edi,-0x34(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmov %rsp,%rax\nmov %rax,%rsi\nmov -0x34(%rbp),%eax\nadd $0x1,%eax\nmovslq %eax,%rdx\nsub $0x1,%rdx\nmov %rdx,-0x28(%rbp)\nmovslq %eax,%rdx\nmov %rdx,%r8\nmov $0x0,%r9d\nmovslq %eax,%rdx\nmov %rdx,%rcx\nmov $0x0,%ebx\ncltq\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%edi\nmov $0x0,%edx\ndiv %rdi\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rbx\nsub %rdx,%rbx\nmov %rbx,%rdx\ncmp %rdx,%rsp\nje 1207 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11f0 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 1231 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x20(%rbp)\nmov -0x20(%rbp),%rax\nmovl $0x0,(%rax)\nmov -0x20(%rbp),%rax\nmovl $0x1,0x4(%rax)\nmovl $0x2,-0x2c(%rbp)\njmp 1297 \nmov -0x2c(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x20(%rbp),%rax\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%ecx\nmov -0x2c(%rbp),%eax\nlea -0x2(%rax),%edx\nmov -0x20(%rbp),%rax\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nadd %eax,%eax\nadd %eax,%ecx\nmov -0x20(%rbp),%rax\nmov -0x2c(%rbp),%edx\nmovslq %edx,%rdx\nmov %ecx,(%rax,%rdx,4)\naddl $0x1,-0x2c(%rbp)\nmov -0x2c(%rbp),%eax\ncmp -0x34(%rbp),%eax\njle 1262 \nmov -0x20(%rbp),%rax\nmov -0x34(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nmov %rsi,%rsp\nmov -0x18(%rbp),%rdi\nxor %fs:0x28,%rdi\nje 12c3 \ncallq 1060 <__stack_chk_fail@plt>\nmov -0x8(%rbp),%rbx\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_24], edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov eax, [rbp+var_24]\nadd eax, 1\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11D5:\ncmp rsp, rdx\njz short loc_11EC\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\njmp short loc_11D5\nloc_11EC:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1216\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1216:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov rax, [rbp+var_10]\nmov dword ptr [rax], 0\nmov rax, [rbp+var_10]\nmov dword ptr [rax+4], 1\nmov [rbp+var_1C], 2\njmp short loc_127C\nloc_1247:\nmov eax, [rbp+var_1C]\nlea edx, [rax-1]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov eax, [rbp+var_1C]\nlea edx, [rax-2]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nadd eax, eax\nadd ecx, eax\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nadd [rbp+var_1C], 1\nloc_127C:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_24]\njle short loc_1247\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12A8\ncall ___stack_chk_fail\nlocret_12A8:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned __int64 v1; // rax\n void *v2; // rsp\n _DWORD v4[3]; // [rsp+8h] [rbp-30h] BYREF\n int v5; // [rsp+14h] [rbp-24h]\n int i; // [rsp+1Ch] [rbp-1Ch]\n __int64 v7; // [rsp+20h] [rbp-18h]\n _DWORD *v8; // [rsp+28h] [rbp-10h]\n unsigned __int64 v9; // [rsp+30h] [rbp-8h]\n\n v5 = a1;\n v9 = __readfsqword(0x28u);\n v7 = a1 + 1 - 1LL;\n v1 = 16 * ((4LL * (a1 + 1) + 15) / 0x10uLL);\n while ( v4 != (_DWORD *)((char *)v4 - (v1 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v2 = alloca(v1 & 0xFFF);\n if ( (v1 & 0xFFF) != 0 )\n *(_QWORD *)((char *)&v4[-2] + (v1 & 0xFFF)) = *(_QWORD *)((char *)&v4[-2] + (v1 & 0xFFF));\n v8 = v4;\n v4[0] = 0;\n v4[1] = 1;\n for ( i = 2; i <= v5; ++i )\n v8[i] = 2 * v8[i - 2] + v8[i - 1];\n return (unsigned int)v8[v5];\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_24], edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov eax, [rbp+var_24]\nadd eax, 1\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11D5:\ncmp rsp, rdx\njz short loc_11EC\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\njmp short loc_11D5\nloc_11EC:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1216\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1216:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov rax, [rbp+var_10]\nmov dword ptr [rax], 0\nmov rax, [rbp+var_10]\nmov dword ptr [rax+4], 1\nmov [rbp+var_1C], 2\njmp short loc_127C\nloc_1247:\nmov eax, [rbp+var_1C]\nlea edx, [rax-1]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov eax, [rbp+var_1C]\nlea edx, [rax-2]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nadd eax, eax\nadd ecx, eax\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nadd [rbp+var_1C], 1\nloc_127C:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_24]\njle short loc_1247\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12A8\ncall ___stack_chk_fail\nlocret_12A8:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n unsigned __int64 v1; // rax\n void *v2; // rsp\n _DWORD v4[3]; // [rsp+8h] [rbp-30h] BYREF\n int v5; // [rsp+14h] [rbp-24h]\n int i; // [rsp+1Ch] [rbp-1Ch]\n __int64 v7; // [rsp+20h] [rbp-18h]\n _DWORD *v8; // [rsp+28h] [rbp-10h]\n unsigned __int64 v9; // [rsp+30h] [rbp-8h]\n\n v5 = a1;\n v9 = __readfsqword(0x28u);\n v7 = a1 + 1 - 1LL;\n v1 = 16 * ((4LL * (a1 + 1) + 15) / 0x10uLL);\n while ( v4 != (_DWORD *)((char *)v4 - (v1 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v2 = alloca(v1 & 0xFFF);\n if ( (v1 & 0xFFF) != 0 )\n *(_QWORD *)((char *)&v4[-2] + (v1 & 0xFFF)) = *(_QWORD *)((char *)&v4[-2] + (v1 & 0xFFF));\n v8 = v4;\n v4[0] = 0;\n v4[1] = 1;\n for ( i = 2; i <= v5; ++i )\n v8[i] = 2 * v8[i - 2] + v8[i - 1];\n return (unsigned int)v8[v5];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n unsigned long long v1;\n void *v2;\n uint32_t v4[3];\n int v5;\n int i;\n long long v7;\n uint32_t *v8;\n unsigned long long v9;\n v5 = a1;\n v9 = __readfsqword(40u);\n v7 = a1 + 1 - 1LL;\n v1 = 16 * ((4LL * (a1 + 1) + 15) / 16uLL);\n while (v4 != (uint32_t *)((char *)v4 - (v1 & 18446744073709547520LL)))\n ;\n v2 = alloca(v1 & 4095);\n if ((v1 & 4095) != 0)\n *(uint64_t *)((char *)&v4[-2] + (v1 & 4095)) =\n *(uint64_t *)((char *)&v4[-2] + (v1 & 4095));\n v8 = v4;\n v4[0] = 0;\n v4[1] = 1;\n for (i = 2; i <= v5; ++i) v8[i] = 2 * v8[i - 2] + v8[i - 1];\n return (unsigned int)v8[v5];\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned long long v1;\n void *v2;\n uint32_t v4[3];\n int v5;\n int i;\n long long v7;\n uint32_t *v8;\n unsigned long long v9;\n v5 = a1;\n v9 = __readfsqword(40u);\n v7 = a1 + 1 - 1LL;\n v1 = 16 * ((4LL * (a1 + 1) + 15) / 16uLL);\n while (v4 != (uint32_t *)((char *)v4 - (v1 & 18446744073709547520LL)))\n ;\n v2 = alloca(v1 & 4095);\n if ((v1 & 4095) != 0)\n *(uint64_t *)((char *)&v4[-2] + (v1 & 4095)) =\n *(uint64_t *)((char *)&v4[-2] + (v1 & 4095));\n v8 = v4;\n v4[0] = 0;\n v4[1] = 1;\n for (i = 2; i <= v5; ++i) v8[i] = 2 * v8[i - 2] + v8[i - 1];\n return (unsigned int)v8[v5];\n}" + }, + { + "index": 752, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int dp[n + 1];\n dp[0] = 0;\n dp[1] = 1;\n for (int i = 2; i <= n; i++) {\n dp[i] = dp[i - 1] + 2 * dp[i - 2];\n }\n return dp[n];\n}", + "test": "int main() {\n\n assert(func0(5) == 11);\n\n assert(func0(2) == 1);\n\n assert(func0(4) == 5);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0x1(%rdi),%eax\ncltq\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffffff0,%rdx\nand $0xfffffffffffff000,%rax\nmov %rsp,%rsi\nsub %rax,%rsi\nmov %rsi,%rax\ncmp %rax,%rsp\nje 11be \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11a7 \nmov %rdx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 11d4 \norq $0x0,-0x8(%rsp,%rax,1)\nlea 0x3(%rsp),%r8\nmov %r8,%rax\nshr $0x2,%rax\nand $0xfffffffffffffffc,%r8\nmovl $0x0,0x0(,%rax,4)\nmovl $0x1,0x4(,%rax,4)\ncmp $0x1,%edi\njle 121e \nmov %r8,%rax\nlea -0x2(%rdi),%edx\nlea 0x4(%r8,%rdx,4),%rsi\nmov (%rax),%ecx\nmov 0x4(%rax),%edx\nlea (%rdx,%rcx,2),%edx\nmov %edx,0x8(%rax)\nadd $0x4,%rax\ncmp %rsi,%rax\njne 120a \nmovslq %edi,%rdi\nmov (%r8,%rdi,4),%eax\nmov -0x8(%rbp),%rdi\nxor %fs:0x28,%rdi\njne 1236 \nleaveq\nretq\ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea eax, [rdi+1]\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11A4:\ncmp rsp, rdx\njz short loc_11BB\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11A4\nloc_11BB:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11D1\nor [rsp+rax+10h+var_18], 0\nloc_11D1:\nlea r8, [rsp+10h+var_D]\nmov rax, r8\nshr rax, 2\nand r8, 0FFFFFFFFFFFFFFFCh\nmov ds:dword_0[rax*4], 0\nmov dword ptr ds:byte_4[rax*4], 1\ncmp edi, 1\njle short loc_121A\nmov rax, r8\nlea edx, [rdi-1]\nlea rsi, [r8+rdx*4]\nloc_1206:\nmov ecx, [rax]\nmov edx, [rax+4]\nlea edx, [rdx+rcx*2]\nmov [rax+8], edx\nadd rax, 4\ncmp rax, rsi\njnz short loc_1206\nloc_121A:\nmovsxd rdi, edi\nmov eax, [r8+rdi*4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_1232\nleave\nretn\nloc_1232:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n signed __int64 v1; // rax\n void *v2; // rsp\n unsigned __int64 v3; // rax\n _BYTE *v4; // rax\n _BYTE v7[3]; // [rsp+8h] [rbp-10h] BYREF\n char v8; // [rsp+Bh] [rbp-Dh] BYREF\n unsigned __int64 v9; // [rsp+10h] [rbp-8h]\n\n v9 = __readfsqword(0x28u);\n while ( v7 != &v7[-((4LL * (a1 + 1) + 15) & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v1 = (4 * ((_WORD)a1 + 1) + 15) & 0xFF0;\n v2 = alloca(v1);\n if ( ((4 * ((_WORD)a1 + 1) + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v7[v1 - 8] = *(_QWORD *)&v7[v1 - 8];\n v3 = (unsigned __int64)&v8 >> 2;\n *(_DWORD *)(4 * v3) = 0;\n *(_DWORD *)&byte_4[4 * v3] = 1;\n if ( a1 > 1 )\n {\n v4 = v7;\n do\n {\n *((_DWORD *)v4 + 2) = *((_DWORD *)v4 + 1) + 2 * *(_DWORD *)v4;\n v4 += 4;\n }\n while ( v4 != &v7[4 * (a1 - 1)] );\n }\n return *(unsigned int *)&v7[4 * a1];\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea eax, [rdi+1]\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11A4:\ncmp rsp, rdx\njz short loc_11BB\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11A4\nloc_11BB:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11D1\nor [rsp+rax+10h+var_18], 0\nloc_11D1:\nlea r8, [rsp+10h+var_D]\nmov rax, r8\nshr rax, 2\nand r8, 0FFFFFFFFFFFFFFFCh\nmov ds:dword_0[rax*4], 0\nmov dword ptr ds:byte_4[rax*4], 1\ncmp edi, 1\njle short loc_121A\nmov rax, r8\nlea edx, [rdi-1]\nlea rsi, [r8+rdx*4]\nloc_1206:\nmov ecx, [rax]\nmov edx, [rax+4]\nlea edx, [rdx+rcx*2]\nmov [rax+8], edx\nadd rax, 4\ncmp rax, rsi\njnz short loc_1206\nloc_121A:\nmovsxd rdi, edi\nmov eax, [r8+rdi*4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_1232\nleave\nretn\nloc_1232:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n signed __int64 v1; // rax\n void *v2; // rsp\n unsigned __int64 v3; // rax\n _BYTE *v4; // rax\n _BYTE v7[3]; // [rsp+8h] [rbp-10h] BYREF\n char v8; // [rsp+Bh] [rbp-Dh] BYREF\n unsigned __int64 v9; // [rsp+10h] [rbp-8h]\n\n v9 = __readfsqword(0x28u);\n while ( v7 != &v7[-((4LL * (a1 + 1) + 15) & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v1 = (4 * ((_WORD)a1 + 1) + 15) & 0xFF0;\n v2 = alloca(v1);\n if ( ((4 * ((_WORD)a1 + 1) + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v7[v1 - 8] = *(_QWORD *)&v7[v1 - 8];\n v3 = (unsigned __int64)&v8 >> 2;\n *(_DWORD *)(4 * v3) = 0;\n *(_DWORD *)&byte_4[4 * v3] = 1;\n if ( a1 > 1 )\n {\n v4 = v7;\n do\n {\n *((_DWORD *)v4 + 2) = *((_DWORD *)v4 + 1) + 2 * *(_DWORD *)v4;\n v4 += 4;\n }\n while ( v4 != &v7[4 * (a1 - 1)] );\n }\n return *(unsigned int *)&v7[4 * a1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n signed long long v1;\n void *v2;\n unsigned long long v3;\n uint8_t *v4;\n uint8_t v7[3];\n char v8;\n unsigned long long v9;\n v9 = __readfsqword(40u);\n while (v7 != &v7[-((4LL * (a1 + 1) + 15) & 18446744073709547520LL)])\n ;\n v1 = (4 * ((unsigned short)a1 + 1) + 15) & 4080;\n v2 = alloca(v1);\n if (((4 * ((unsigned short)a1 + 1) + 15) & 4080) != 0)\n *(uint64_t *)&v7[v1 - 8] = *(uint64_t *)&v7[v1 - 8];\n v3 = (unsigned long long)&v8 >> 2;\n *(uint32_t *)(4 * v3) = 0;\n *(uint32_t *)&byte_4[4 * v3] = 1;\n if (a1 > 1) {\n v4 = v7;\n do {\n *((uint32_t *)v4 + 2) = *((uint32_t *)v4 + 1) + 2 * *(uint32_t *)v4;\n v4 += 4;\n } while (v4 != &v7[4 * (a1 - 1)]);\n }\n return *(unsigned int *)&v7[4 * a1];\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n signed long long v1;\n void *v2;\n unsigned long long v3;\n uint8_t *v4;\n uint8_t v7[3];\n char v8;\n unsigned long long v9;\n v9 = __readfsqword(40u);\n while (v7 != &v7[-((4LL * (a1 + 1) + 15) & 18446744073709547520LL)])\n ;\n v1 = (4 * ((unsigned short)a1 + 1) + 15) & 4080;\n v2 = alloca(v1);\n if (((4 * ((unsigned short)a1 + 1) + 15) & 4080) != 0)\n *(uint64_t *)&v7[v1 - 8] = *(uint64_t *)&v7[v1 - 8];\n v3 = (unsigned long long)&v8 >> 2;\n *(uint32_t *)(4 * v3) = 0;\n *(uint32_t *)&byte_4[4 * v3] = 1;\n if (a1 > 1) {\n v4 = v7;\n do {\n *((uint32_t *)v4 + 2) = *((uint32_t *)v4 + 1) + 2 * *(uint32_t *)v4;\n v4 += 4;\n } while (v4 != &v7[4 * (a1 - 1)]);\n }\n return *(unsigned int *)&v7[4 * a1];\n}" + }, + { + "index": 752, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int dp[n + 1];\n dp[0] = 0;\n dp[1] = 1;\n for (int i = 2; i <= n; i++) {\n dp[i] = dp[i - 1] + 2 * dp[i - 2];\n }\n return dp[n];\n}", + "test": "int main() {\n\n assert(func0(5) == 11);\n\n assert(func0(2) == 1);\n\n assert(func0(4) == 5);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0x1(%rdi),%eax\nmov %rsp,%rsi\ncltq\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rsi\nand $0xfffffffffffffff0,%rdx\nmov %rsi,%rax\ncmp %rax,%rsp\nje 1268 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 1253 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 12e8 \nmovabs $0x100000000,%rsi\nlea 0x3(%rsp),%r8\nmov %r8,%rax\nand $0xfffffffffffffffc,%r8\nshr $0x2,%rax\nmov %rsi,0x0(,%rax,4)\ncmp $0x1,%edi\njle 12c9 \nlea -0x2(%rdi),%edx\nlea 0x8(%r8),%rax\nxor %ecx,%ecx\nlea 0x8(%r8,%rdx,4),%rsi\nmov $0x1,%edx\njmp 12bf \nnopw 0x0(%rax,%rax,1)\nmov -0x4(%rax),%ecx\nadd $0x4,%rax\nlea (%rdx,%rcx,2),%edx\nmov %edx,(%rax)\ncmp %rsi,%rax\njne 12b8 \nmovslq %edi,%rdi\nmov (%r8,%rdi,4),%eax\nmov -0x8(%rbp),%rdi\nxor %fs:0x28,%rdi\njne 12f0 \nleaveq\nretq\nnopl 0x0(%rax)\norq $0x0,-0x8(%rsp,%rdx,1)\njmp 1276 \ncallq 1060 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmovsxd r8, edi\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea eax, [r8+1]\nmov rcx, rsp\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_1269\nloc_1254:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rcx\njnz short loc_1254\nloc_1269:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz short loc_12E0\nloc_1277:\nlea r9, [rsp+1010h+var_100D]\nmov rdx, cs:qword_2058\nmov rax, r9\nand r9, 0FFFFFFFFFFFFFFFCh\nshr rax, 2\nmov qword ptr ds:dword_0[rax*4], rdx\ncmp r8d, 1\njle short loc_12C3\nlea eax, [r8-2]\nlea rdx, [r9+8]\nxor ecx, ecx\nlea rdi, [r9+rax*4+0Ch]\nmov eax, 1\nloc_12B0:\nlea esi, [rcx+rcx]\nmov ecx, eax\nadd rdx, 4\nadd eax, esi\nmov [rdx-4], eax\ncmp rdi, rdx\njnz short loc_12B0\nloc_12C3:\nmov eax, [r9+r8*4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_12E8\nleave\nretn\nloc_12E0:\nor [rsp+rdx+1010h+var_1018], 0\njmp short loc_1277\nloc_12E8:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n __int64 v1; // rdx\n __int64 *v2; // rcx\n __int16 v3; // dx\n signed __int64 v4; // rdx\n void *v5; // rsp\n _BYTE *v6; // rdx\n int v7; // ecx\n int v8; // eax\n int v9; // esi\n __int64 v11; // [rsp+0h] [rbp-1018h]\n __int64 v12; // [rsp+8h] [rbp-1010h] BYREF\n _BYTE v13[4080]; // [rsp+10h] [rbp-1008h] BYREF\n _QWORD v14[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v14[1] = __readfsqword(0x28u);\n v1 = 4LL * (a1 + 1) + 15;\n v2 = (_QWORD *)((char *)v14 - (v1 & 0xFFFFFFFFFFFFF000LL));\n v3 = v1 & 0xFFF0;\n if ( v14 != v2 )\n {\n while ( &v12 != v2 )\n ;\n }\n v4 = v3 & 0xFFF;\n v5 = alloca(v4);\n if ( v4 )\n *(__int64 *)((char *)&v11 + v4) = *(__int64 *)((char *)&v11 + v4);\n v12 = 0x100000000LL;\n if ( a1 > 1 )\n {\n v6 = v13;\n v7 = 0;\n v8 = 1;\n do\n {\n v9 = 2 * v7;\n v7 = v8;\n v6 += 4;\n v8 += v9;\n *((_DWORD *)v6 - 1) = v8;\n }\n while ( &v13[4 * (a1 - 2) + 4] != v6 );\n }\n return *(unsigned int *)&v13[4 * a1 - 8];\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbp\nmovsxd r8, edi\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea eax, [r8+1]\nmov rcx, rsp\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_1269\nloc_1254:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rcx\njnz short loc_1254\nloc_1269:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz short loc_12E0\nloc_1277:\nlea r9, [rsp+1010h+var_100D]\nmov rdx, cs:qword_2058\nmov rax, r9\nand r9, 0FFFFFFFFFFFFFFFCh\nshr rax, 2\nmov qword ptr ds:dword_0[rax*4], rdx\ncmp r8d, 1\njle short loc_12C3\nlea eax, [r8-2]\nlea rdx, [r9+8]\nxor ecx, ecx\nlea rdi, [r9+rax*4+0Ch]\nmov eax, 1\nloc_12B0:\nlea esi, [rcx+rcx]\nmov ecx, eax\nadd rdx, 4\nadd eax, esi\nmov [rdx-4], eax\ncmp rdi, rdx\njnz short loc_12B0\nloc_12C3:\nmov eax, [r9+r8*4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_12E8\nleave\nretn\nloc_12E0:\nor [rsp+rdx+1010h+var_1018], 0\njmp short loc_1277\nloc_12E8:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(int a1)\n{\n __int64 v1; // rdx\n __int64 *v2; // rcx\n __int16 v3; // dx\n signed __int64 v4; // rdx\n void *v5; // rsp\n _BYTE *v6; // rdx\n int v7; // ecx\n int v8; // eax\n int v9; // esi\n __int64 v11; // [rsp+0h] [rbp-1018h]\n __int64 v12; // [rsp+8h] [rbp-1010h] BYREF\n _BYTE v13[4080]; // [rsp+10h] [rbp-1008h] BYREF\n _QWORD v14[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v14[1] = __readfsqword(0x28u);\n v1 = 4LL * (a1 + 1) + 15;\n v2 = (_QWORD *)((char *)v14 - (v1 & 0xFFFFFFFFFFFFF000LL));\n v3 = v1 & 0xFFF0;\n if ( v14 != v2 )\n {\n while ( &v12 != v2 )\n ;\n }\n v4 = v3 & 0xFFF;\n v5 = alloca(v4);\n if ( v4 )\n *(__int64 *)((char *)&v11 + v4) = *(__int64 *)((char *)&v11 + v4);\n v12 = 0x100000000LL;\n if ( a1 > 1 )\n {\n v6 = v13;\n v7 = 0;\n v8 = 1;\n do\n {\n v9 = 2 * v7;\n v7 = v8;\n v6 += 4;\n v8 += v9;\n *((_DWORD *)v6 - 1) = v8;\n }\n while ( &v13[4 * (a1 - 2) + 4] != v6 );\n }\n return *(unsigned int *)&v13[4 * a1 - 8];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(int a1) {\n long long v1;\n long long *v2;\n short v3;\n signed long long v4;\n void *v5;\n uint8_t *v6;\n int v7;\n int v8;\n int v9;\n long long v11;\n long long v12;\n uint8_t v13[4080];\n uint64_t v14[2];\n v14[1] = __readfsqword(40u);\n v1 = 4LL * (a1 + 1) + 15;\n v2 = (uint64_t *)((char *)v14 - (v1 & 18446744073709547520LL));\n v3 = v1 & 65520;\n if (v14 != v2) {\n while (&v12 != v2)\n ;\n }\n v4 = v3 & 4095;\n v5 = alloca(v4);\n if (v4) *(long long *)((char *)&v11 + v4) = *(long long *)((char *)&v11 + v4);\n v12 = 4294967296LL;\n if (a1 > 1) {\n v6 = v13;\n v7 = 0;\n v8 = 1;\n do {\n v9 = 2 * v7;\n v7 = v8;\n v6 += 4;\n v8 += v9;\n *((uint32_t *)v6 - 1) = v8;\n } while (&v13[4 * (a1 - 2) + 4] != v6);\n }\n return *(unsigned int *)&v13[4 * a1 - 8];\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n long long v1;\n long long *v2;\n short v3;\n signed long long v4;\n void *v5;\n uint8_t *v6;\n int v7;\n int v8;\n int v9;\n long long v11;\n long long v12;\n uint8_t v13[4080];\n uint64_t v14[2];\n v14[1] = __readfsqword(40u);\n v1 = 4LL * (a1 + 1) + 15;\n v2 = (uint64_t *)((char *)v14 - (v1 & 18446744073709547520LL));\n v3 = v1 & 65520;\n if (v14 != v2) {\n while (&v12 != v2)\n ;\n }\n v4 = v3 & 4095;\n v5 = alloca(v4);\n if (v4) *(long long *)((char *)&v11 + v4) = *(long long *)((char *)&v11 + v4);\n v12 = 4294967296LL;\n if (a1 > 1) {\n v6 = v13;\n v7 = 0;\n v8 = 1;\n do {\n v9 = 2 * v7;\n v7 = v8;\n v6 += 4;\n v8 += v9;\n *((uint32_t *)v6 - 1) = v8;\n } while (&v13[4 * (a1 - 2) + 4] != v6);\n }\n return *(unsigned int *)&v13[4 * a1 - 8];\n}" + }, + { + "index": 752, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int dp[n + 1];\n dp[0] = 0;\n dp[1] = 1;\n for (int i = 2; i <= n; i++) {\n dp[i] = dp[i - 1] + 2 * dp[i - 2];\n }\n return dp[n];\n}", + "test": "int main() {\n\n assert(func0(5) == 11);\n\n assert(func0(2) == 1);\n\n assert(func0(4) == 5);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0x1(%rdi),%eax\nmov %rsp,%rsi\ncltq\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rsi\nand $0xfffffffffffffff0,%rdx\nmov %rsi,%rax\ncmp %rax,%rsp\nje 11e8 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 11d3 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 1298 \nmovabs $0x100000000,%rsi\nlea 0x3(%rsp),%rdx\nmov %rdx,%rax\nand $0xfffffffffffffffc,%rdx\nshr $0x2,%rax\nmov %rsi,0x0(,%rax,4)\ncmp $0x1,%edi\njle 127e \ncmp $0x3,%edi\njle 12a3 \nmov 0x0(,%rax,4),%r8d\nmov 0x4(,%rax,4),%esi\nlea -0x4(%rdi),%eax\nmov $0x4,%ecx\nshr %eax\nlea 0x6(%rax,%rax,1),%r9\nlea (%rsi,%r8,2),%r8d\nmovslq %ecx,%rax\nlea (%r8,%rsi,2),%esi\nmov %r8d,-0x8(%rdx,%rcx,4)\nmov %esi,-0x4(%rdx,%rcx,4)\nadd $0x2,%rcx\ncmp %rcx,%r9\njne 1244 \nnopl 0x0(%rax)\nmov -0x8(%rdx,%rax,4),%esi\nmov -0x4(%rdx,%rax,4),%ecx\nlea (%rcx,%rsi,2),%ecx\nmov %ecx,(%rdx,%rax,4)\nadd $0x1,%rax\ncmp %eax,%edi\njge 1268 \nmovslq %edi,%rdi\nmov (%rdx,%rdi,4),%eax\nmov -0x8(%rbp),%rdi\nxor %fs:0x28,%rdi\njne 12aa \nleaveq\nretq\nnopl (%rax)\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 11fa \nmov $0x2,%eax\njmp 1268 \ncallq 1050 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmovsxd rcx, edi\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea eax, [rcx+1]\nmov rsi, rsp\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rsi, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rsi\njz short loc_11B8\nloc_11A3:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rsi\njnz short loc_11A3\nloc_11B8:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1260\nloc_11CA:\nlea rdx, [rsp+1010h+var_100D]\nmov rsi, cs:qword_2008\nmov rax, rdx\nand rdx, 0FFFFFFFFFFFFFFFCh\nshr rax, 2\nmov qword ptr ds:dword_0[rax*4], rsi\ncmp ecx, 1\njle short loc_1246\ncmp ecx, 3\njle short loc_126B\nlea eax, [rcx-4]\nmov esi, 4\nmov r8d, 1\nxor edi, edi\nshr eax, 1\nlea r9d, [rax+3]\nadd r9, r9\nloc_120C:\nlea edi, [r8+rdi*2]\nmov rax, rsi\nlea r8d, [rdi+r8*2]\nmov [rdx+rsi*4-8], edi\nmov [rdx+rsi*4-4], r8d\nadd rsi, 2\ncmp r9, rsi\njnz short loc_120C\nloc_1229:\ncdqe\nnop dword ptr [rax+rax+00h]\nloc_1230:\nmov edi, [rdx+rax*4-8]\nmov esi, [rdx+rax*4-4]\nlea esi, [rsi+rdi*2]\nmov [rdx+rax*4], esi\nadd rax, 1\ncmp ecx, eax\njge short loc_1230\nloc_1246:\nmov eax, [rdx+rcx*4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_1272\nleave\nretn\nloc_1260:\nor [rsp+rdx+1010h+var_1018], 0\njmp loc_11CA\nloc_126B:\nmov eax, 2\njmp short loc_1229\nloc_1272:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n __int64 v1; // rcx\n __int64 v2; // rdx\n _QWORD *v3; // rsi\n __int16 v4; // dx\n signed __int64 v5; // rdx\n void *v6; // rsp\n __int64 v7; // rsi\n int v8; // r8d\n int v9; // edi\n __int64 v10; // rax\n _QWORD v13[511]; // [rsp+8h] [rbp-1010h] BYREF\n _QWORD v14[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v1 = a1;\n v14[1] = __readfsqword(0x28u);\n v2 = 4LL * (a1 + 1) + 15;\n v3 = (_QWORD *)((char *)v14 - (v2 & 0xFFFFFFFFFFFFF000LL));\n v4 = v2 & 0xFFF0;\n if ( v14 != v3 )\n {\n while ( v13 != v3 )\n ;\n }\n v5 = v4 & 0xFFF;\n v6 = alloca(v5);\n if ( v5 )\n *(_QWORD *)((char *)&v13[-1] + v5) = *(_QWORD *)((char *)&v13[-1] + v5);\n v13[0] = 0x100000000LL;\n if ( a1 > 1 )\n {\n if ( a1 <= 3 )\n {\n LODWORD(v10) = 2;\n }\n else\n {\n v7 = 2LL;\n v8 = 1;\n v9 = 0;\n do\n {\n v9 = v8 + 2 * v9;\n LODWORD(v10) = v7 * 2;\n v8 = v9 + 2 * v8;\n LODWORD(v13[v7 - 1]) = v9;\n HIDWORD(v13[v7++ - 1]) = v8;\n }\n while ( ((unsigned int)(v1 - 4) >> 1) + 3 != v7 );\n }\n v10 = (int)v10;\n do\n {\n *((_DWORD *)v13 + v10) = *((_DWORD *)v13 + v10 - 1) + 2 * *((_DWORD *)&v13[-1] + v10);\n ++v10;\n }\n while ( (int)v1 >= (int)v10 );\n }\n return *((unsigned int *)v13 + v1);\n}", + "ida_strip_asm": "sub_1160:\nendbr64\npush rbp\nmovsxd rcx, edi\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea eax, [rcx+1]\nmov rsi, rsp\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rsi, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rsi\njz short loc_11B8\nloc_11A3:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rsi\njnz short loc_11A3\nloc_11B8:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1260\nloc_11CA:\nlea rdx, [rsp+1010h+var_100D]\nmov rsi, cs:qword_2008\nmov rax, rdx\nand rdx, 0FFFFFFFFFFFFFFFCh\nshr rax, 2\nmov qword ptr ds:dword_0[rax*4], rsi\ncmp ecx, 1\njle short loc_1246\ncmp ecx, 3\njle short loc_126B\nlea eax, [rcx-4]\nmov esi, 4\nmov r8d, 1\nxor edi, edi\nshr eax, 1\nlea r9d, [rax+3]\nadd r9, r9\nloc_120C:\nlea edi, [r8+rdi*2]\nmov rax, rsi\nlea r8d, [rdi+r8*2]\nmov [rdx+rsi*4-8], edi\nmov [rdx+rsi*4-4], r8d\nadd rsi, 2\ncmp r9, rsi\njnz short loc_120C\nloc_1229:\ncdqe\nnop dword ptr [rax+rax+00h]\nloc_1230:\nmov edi, [rdx+rax*4-8]\nmov esi, [rdx+rax*4-4]\nlea esi, [rsi+rdi*2]\nmov [rdx+rax*4], esi\nadd rax, 1\ncmp ecx, eax\njge short loc_1230\nloc_1246:\nmov eax, [rdx+rcx*4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_1272\nleave\nretn\nloc_1260:\nor [rsp+rdx+1010h+var_1018], 0\njmp loc_11CA\nloc_126B:\nmov eax, 2\njmp short loc_1229\nloc_1272:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1160(int a1)\n{\n __int64 v1; // rcx\n __int64 v2; // rdx\n _QWORD *v3; // rsi\n __int16 v4; // dx\n signed __int64 v5; // rdx\n void *v6; // rsp\n __int64 v7; // rsi\n int v8; // r8d\n int v9; // edi\n __int64 v10; // rax\n _QWORD v13[511]; // [rsp+8h] [rbp-1010h] BYREF\n _QWORD v14[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v1 = a1;\n v14[1] = __readfsqword(0x28u);\n v2 = 4LL * (a1 + 1) + 15;\n v3 = (_QWORD *)((char *)v14 - (v2 & 0xFFFFFFFFFFFFF000LL));\n v4 = v2 & 0xFFF0;\n if ( v14 != v3 )\n {\n while ( v13 != v3 )\n ;\n }\n v5 = v4 & 0xFFF;\n v6 = alloca(v5);\n if ( v5 )\n *(_QWORD *)((char *)&v13[-1] + v5) = *(_QWORD *)((char *)&v13[-1] + v5);\n v13[0] = 0x100000000LL;\n if ( a1 > 1 )\n {\n if ( a1 <= 3 )\n {\n LODWORD(v10) = 2;\n }\n else\n {\n v7 = 2LL;\n v8 = 1;\n v9 = 0;\n do\n {\n v9 = v8 + 2 * v9;\n LODWORD(v10) = v7 * 2;\n v8 = v9 + 2 * v8;\n LODWORD(v13[v7 - 1]) = v9;\n HIDWORD(v13[v7++ - 1]) = v8;\n }\n while ( ((unsigned int)(v1 - 4) >> 1) + 3 != v7 );\n }\n v10 = (int)v10;\n do\n {\n *((_DWORD *)v13 + v10) = *((_DWORD *)v13 + v10 - 1) + 2 * *((_DWORD *)&v13[-1] + v10);\n ++v10;\n }\n while ( (int)v1 >= (int)v10 );\n }\n return *((unsigned int *)v13 + v1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1160(int a1) {\n long long v1;\n long long v2;\n uint64_t *v3;\n short v4;\n signed long long v5;\n void *v6;\n long long v7;\n int v8;\n int v9;\n long long v10;\n uint64_t v13[511];\n uint64_t v14[2];\n v1 = a1;\n v14[1] = __readfsqword(40u);\n v2 = 4LL * (a1 + 1) + 15;\n v3 = (uint64_t *)((char *)v14 - (v2 & 18446744073709547520LL));\n v4 = v2 & 65520;\n if (v14 != v3) {\n while (v13 != v3)\n ;\n }\n v5 = v4 & 4095;\n v6 = alloca(v5);\n if (v5)\n *(uint64_t *)((char *)&v13[-1] + v5) = *(uint64_t *)((char *)&v13[-1] + v5);\n v13[0] = 4294967296LL;\n if (a1 > 1) {\n if (a1 <= 3) {\n LODWORD(v10) = 2;\n } else {\n v7 = 2LL;\n v8 = 1;\n v9 = 0;\n do {\n v9 = v8 + 2 * v9;\n LODWORD(v10) = v7 * 2;\n v8 = v9 + 2 * v8;\n LODWORD(v13[v7 - 1]) = v9;\n HIDWORD(v13[v7++ - 1]) = v8;\n } while (((unsigned int)(v1 - 4) >> 1) + 3 != v7);\n }\n v10 = (int)v10;\n do {\n *((uint32_t *)v13 + v10) =\n *((uint32_t *)v13 + v10 - 1) + 2 * *((uint32_t *)&v13[-1] + v10);\n ++v10;\n } while ((int)v1 >= (int)v10);\n }\n return *((unsigned int *)v13 + v1);\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n long long v1;\n long long v2;\n uint64_t *v3;\n short v4;\n signed long long v5;\n void *v6;\n long long v7;\n int v8;\n int v9;\n long long v10;\n uint64_t v13[511];\n uint64_t v14[2];\n v1 = a1;\n v14[1] = __readfsqword(40u);\n v2 = 4LL * (a1 + 1) + 15;\n v3 = (uint64_t *)((char *)v14 - (v2 & 18446744073709547520LL));\n v4 = v2 & 65520;\n if (v14 != v3) {\n while (v13 != v3)\n ;\n }\n v5 = v4 & 4095;\n v6 = alloca(v5);\n if (v5)\n *(uint64_t *)((char *)&v13[-1] + v5) = *(uint64_t *)((char *)&v13[-1] + v5);\n v13[0] = 4294967296LL;\n if (a1 > 1) {\n if (a1 <= 3) {\n LODWORD(v10) = 2;\n } else {\n v7 = 2LL;\n v8 = 1;\n v9 = 0;\n do {\n v9 = v8 + 2 * v9;\n LODWORD(v10) = v7 * 2;\n v8 = v9 + 2 * v8;\n LODWORD(v13[v7 - 1]) = v9;\n HIDWORD(v13[v7++ - 1]) = v8;\n } while (((unsigned int)(v1 - 4) >> 1) + 3 != v7);\n }\n v10 = (int)v10;\n do {\n *((uint32_t *)v13 + v10) =\n *((uint32_t *)v13 + v10 - 1) + 2 * *((uint32_t *)&v13[-1] + v10);\n ++v10;\n } while ((int)v1 >= (int)v10);\n }\n return *((unsigned int *)v13 + v1);\n}" + }, + { + "index": 753, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\ntypedef struct pair {\n\n char* name;\n\n int value;\n\n} Pair;\n\n\n\nint compare_pairs(const void *a, const void *b) {\n\n Pair *pa = (Pair *)a;\n\n Pair *pb = (Pair *)b;\n\n return (pa->value - pb->value);\n\n}\n\n\n\n", + "func": "Pair* func0(Pair arr[], int size, int K) {\n qsort(arr, size, sizeof(Pair), compare_pairs);\n Pair* res = malloc(K * sizeof(Pair));\n for (int i = 0; i < K; ++i) {\n res[i] = arr[i];\n }\n return res;\n}", + "test": "int main() {\n\n Pair list1[] = {{\"Manjeet\", 10}, {\"Akshat\", 4}, {\"Akash\", 2}, {\"Nikhil\", 8}};\n\n Pair list2[] = {{\"Sanjeev\", 11}, {\"Angat\", 5}, {\"Akash\", 3}, {\"Nepin\", 9}};\n\n Pair list3[] = {{\"tanmay\", 14}, {\"Amer\", 11}, {\"Ayesha\", 9}, {\"SKD\", 16}};\n\n\n\n Pair* result1 = func0(list1, 4, 2);\n\n assert(result1[0].value == 2 && result1[1].value == 4);\n\n assert(strcmp(result1[0].name, \"Akash\") == 0);\n\n assert(strcmp(result1[1].name, \"Akshat\") == 0);\n\n\n\n Pair* result2 = func0(list2, 4, 3);\n\n assert(result2[0].value == 3 && result2[1].value == 5 && result2[2].value == 9);\n\n assert(strcmp(result2[0].name, \"Akash\") == 0);\n\n assert(strcmp(result2[1].name, \"Angat\") == 0);\n\n assert(strcmp(result2[2].name, \"Nepin\") == 0);\n\n\n\n Pair* result3 = func0(list3, 4, 1);\n\n assert(result3[0].value == 9);\n\n assert(strcmp(result3[0].name, \"Ayesha\") == 0);\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmov -0x1c(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x18(%rbp),%rax\nlea -0x5b(%rip),%rcx\nmov $0x10,%edx\nmov %rax,%rdi\ncallq 10b0 \nmov -0x20(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdi\ncallq 10f0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 12a8 \nmov -0xc(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0xc(%rbp),%edx\nmovslq %edx,%rdx\nmov %rdx,%rcx\nshl $0x4,%rcx\nmov -0x8(%rbp),%rdx\nadd %rdx,%rcx\nmov 0x8(%rax),%rdx\nmov (%rax),%rax\nmov %rax,(%rcx)\nmov %rdx,0x8(%rcx)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x20(%rbp),%eax\njl 126f \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+base], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov eax, [rbp+var_1C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compare_pairs\nmov rcx, rdx; compar\nmov edx, 10h; size\nmov rdi, rax; base\ncall _qsort\nmov eax, [rbp+var_20]\ncdqe\nshl rax, 4\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp short loc_12AB\nloc_1272:\nmov eax, [rbp+var_C]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nmov rcx, rdx\nshl rcx, 4\nmov rdx, [rbp+var_8]\nadd rcx, rdx\nmov rdx, [rax+8]\nmov rax, [rax]\nmov [rcx], rax\nmov [rcx+8], rdx\nadd [rbp+var_C], 1\nloc_12AB:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_20]\njl short loc_1272\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(char *a1, int a2, int a3)\n{\n char *v3; // rax\n char *v4; // rcx\n __int64 v5; // rdx\n int i; // [rsp+14h] [rbp-Ch]\n char *v9; // [rsp+18h] [rbp-8h]\n\n qsort(a1, a2, 0x10uLL, compare_pairs);\n v9 = (char *)malloc(16LL * a3);\n for ( i = 0; i < a3; ++i )\n {\n v3 = &a1[16 * i];\n v4 = &v9[16 * i];\n v5 = *((_QWORD *)v3 + 1);\n *(_QWORD *)v4 = *(_QWORD *)v3;\n *((_QWORD *)v4 + 1) = v5;\n }\n return v9;\n}", + "ida_strip_asm": "sub_121D:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+base], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov eax, [rbp+var_1C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 10h; size\nmov rdi, rax; base\ncall _qsort\nmov eax, [rbp+var_20]\ncdqe\nshl rax, 4\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp short loc_12AB\nloc_1272:\nmov eax, [rbp+var_C]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nmov rcx, rdx\nshl rcx, 4\nmov rdx, [rbp+var_8]\nadd rcx, rdx\nmov rdx, [rax+8]\nmov rax, [rax]\nmov [rcx], rax\nmov [rcx+8], rdx\nadd [rbp+var_C], 1\nloc_12AB:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_20]\njl short loc_1272\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_121D(char *a1, int a2, int a3)\n{\n char *v3; // rax\n char *v4; // rcx\n __int64 v5; // rdx\n int i; // [rsp+14h] [rbp-Ch]\n char *v9; // [rsp+18h] [rbp-8h]\n\n qsort(a1, a2, 0x10uLL, compar);\n v9 = (char *)malloc(16LL * a3);\n for ( i = 0; i < a3; ++i )\n {\n v3 = &a1[16 * i];\n v4 = &v9[16 * i];\n v5 = *((_QWORD *)v3 + 1);\n *(_QWORD *)v4 = *(_QWORD *)v3;\n *((_QWORD *)v4 + 1) = v5;\n }\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_121D(char *a1, int a2, int a3) {\n char *v3;\n char *v4;\n long long v5;\n int i;\n char *v9;\n qsort(a1, a2, 16uLL, compar);\n v9 = (char *)malloc(16LL * a3);\n for (i = 0; i < a3; ++i) {\n v3 = &a1[16 * i];\n v4 = &v9[16 * i];\n v5 = *((uint64_t *)v3 + 1);\n *(uint64_t *)v4 = *(uint64_t *)v3;\n *((uint64_t *)v4 + 1) = v5;\n }\n return v9;\n}", + "ida_pseudo_norm": "char *func0(char *a1, int a2, int a3) {\n char *v3;\n char *v4;\n long long v5;\n int i;\n char *v9;\n qsort(a1, a2, 16uLL, compare_pairs);\n v9 = (char *)malloc(16LL * a3);\n for (i = 0; i < a3; ++i) {\n v3 = &a1[16 * i];\n v4 = &v9[16 * i];\n v5 = *((uint64_t *)v3 + 1);\n *(uint64_t *)v4 = *(uint64_t *)v3;\n *((uint64_t *)v4 + 1) = v5;\n }\n return v9;\n}" + }, + { + "index": 753, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\ntypedef struct pair {\n\n char* name;\n\n int value;\n\n} Pair;\n\n\n\nint compare_pairs(const void *a, const void *b) {\n\n Pair *pa = (Pair *)a;\n\n Pair *pb = (Pair *)b;\n\n return (pa->value - pb->value);\n\n}\n\n\n\n", + "func": "Pair* func0(Pair arr[], int size, int K) {\n qsort(arr, size, sizeof(Pair), compare_pairs);\n Pair* res = malloc(K * sizeof(Pair));\n for (int i = 0; i < K; ++i) {\n res[i] = arr[i];\n }\n return res;\n}", + "test": "int main() {\n\n Pair list1[] = {{\"Manjeet\", 10}, {\"Akshat\", 4}, {\"Akash\", 2}, {\"Nikhil\", 8}};\n\n Pair list2[] = {{\"Sanjeev\", 11}, {\"Angat\", 5}, {\"Akash\", 3}, {\"Nepin\", 9}};\n\n Pair list3[] = {{\"tanmay\", 14}, {\"Amer\", 11}, {\"Ayesha\", 9}, {\"SKD\", 16}};\n\n\n\n Pair* result1 = func0(list1, 4, 2);\n\n assert(result1[0].value == 2 && result1[1].value == 4);\n\n assert(strcmp(result1[0].name, \"Akash\") == 0);\n\n assert(strcmp(result1[1].name, \"Akshat\") == 0);\n\n\n\n Pair* result2 = func0(list2, 4, 3);\n\n assert(result2[0].value == 3 && result2[1].value == 5 && result2[2].value == 9);\n\n assert(strcmp(result2[0].name, \"Akash\") == 0);\n\n assert(strcmp(result2[1].name, \"Angat\") == 0);\n\n assert(strcmp(result2[2].name, \"Nepin\") == 0);\n\n\n\n Pair* result3 = func0(list3, 4, 1);\n\n assert(result3[0].value == 9);\n\n assert(strcmp(result3[0].name, \"Ayesha\") == 0);\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbx\nmov %edx,%ebp\nmovslq %esi,%rsi\nlea -0x24(%rip),%rcx\nmov $0x10,%edx\ncallq 10a0 \nmovslq %ebp,%rdi\nshl $0x4,%rdi\ncallq 10d0 \ntest %ebp,%ebp\njle 1229 \nlea -0x1(%rbp),%ecx\nadd $0x1,%rcx\nshl $0x4,%rcx\nmov $0x0,%edx\nmovdqu (%rbx,%rdx,1),%xmm0\nmovups %xmm0,(%rax,%rdx,1)\nadd $0x10,%rdx\ncmp %rcx,%rdx\njne 1217 \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbp, rdi\nmov r12d, edx\nmovsxd rsi, esi; nmemb\nlea rcx, compare_pairs; compar\nmov edx, 10h; size\ncall _qsort\nmovsxd rbx, r12d\nshl rbx, 4\nmov rdi, rbx; size\ncall _malloc\ntest r12d, r12d\njle short loc_1242\nmov edx, 0\nloc_122F:\nmovdqu xmm0, xmmword ptr [rbp+rdx+0]\nmovups xmmword ptr [rax+rdx], xmm0\nadd rdx, 10h\ncmp rbx, rdx\njnz short loc_122F\nloc_1242:\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "char *__fastcall func0(char *a1, int a2, int a3)\n{\n char *result; // rax\n __int64 v5; // rdx\n\n qsort(a1, a2, 0x10uLL, compare_pairs);\n result = (char *)malloc(16LL * a3);\n if ( a3 > 0 )\n {\n v5 = 0LL;\n do\n {\n *(__m128i *)&result[v5] = _mm_loadu_si128((const __m128i *)&a1[v5]);\n v5 += 16LL;\n }\n while ( 16LL * a3 != v5 );\n }\n return result;\n}", + "ida_strip_asm": "sub_11F4:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbp, rdi\nmov r12d, edx\nmovsxd rsi, esi; nmemb\nlea rcx, compar; compar\nmov edx, 10h; size\ncall _qsort\nmovsxd rbx, r12d\nshl rbx, 4\nmov rdi, rbx; size\ncall _malloc\ntest r12d, r12d\njle short loc_1242\nmov edx, 0\nloc_122F:\nmovdqu xmm0, xmmword ptr [rbp+rdx+0]\nmovups xmmword ptr [rax+rdx], xmm0\nadd rdx, 10h\ncmp rbx, rdx\njnz short loc_122F\nloc_1242:\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11F4(char *a1, int a2, int a3)\n{\n char *result; // rax\n __int64 v5; // rdx\n\n qsort(a1, a2, 0x10uLL, compar);\n result = (char *)malloc(16LL * a3);\n if ( a3 > 0 )\n {\n v5 = 0LL;\n do\n {\n *(__m128i *)&result[v5] = _mm_loadu_si128((const __m128i *)&a1[v5]);\n v5 += 16LL;\n }\n while ( 16LL * a3 != v5 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11F4(char *a1, int a2, int a3) {\n char *result;\n long long v5;\n qsort(a1, a2, 16uLL, compar);\n result = (char *)malloc(16LL * a3);\n if (a3 > 0) {\n v5 = 0LL;\n do {\n *(__m128i *)&result[v5] = _mm_loadu_si128((const __m128i *)&a1[v5]);\n v5 += 16LL;\n } while (16LL * a3 != v5);\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(char *a1, int a2, int a3) {\n char *result;\n long long v5;\n qsort(a1, a2, 16uLL, compare_pairs);\n result = (char *)malloc(16LL * a3);\n if (a3 > 0) {\n v5 = 0LL;\n do {\n *(__m128i *)&result[v5] = _mm_loadu_si128((const __m128i *)&a1[v5]);\n v5 += 16LL;\n } while (16LL * a3 != v5);\n }\n return result;\n}" + }, + { + "index": 753, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\ntypedef struct pair {\n\n char* name;\n\n int value;\n\n} Pair;\n\n\n\nint compare_pairs(const void *a, const void *b) {\n\n Pair *pa = (Pair *)a;\n\n Pair *pb = (Pair *)b;\n\n return (pa->value - pb->value);\n\n}\n\n\n\n", + "func": "Pair* func0(Pair arr[], int size, int K) {\n qsort(arr, size, sizeof(Pair), compare_pairs);\n Pair* res = malloc(K * sizeof(Pair));\n for (int i = 0; i < K; ++i) {\n res[i] = arr[i];\n }\n return res;\n}", + "test": "int main() {\n\n Pair list1[] = {{\"Manjeet\", 10}, {\"Akshat\", 4}, {\"Akash\", 2}, {\"Nikhil\", 8}};\n\n Pair list2[] = {{\"Sanjeev\", 11}, {\"Angat\", 5}, {\"Akash\", 3}, {\"Nepin\", 9}};\n\n Pair list3[] = {{\"tanmay\", 14}, {\"Amer\", 11}, {\"Ayesha\", 9}, {\"SKD\", 16}};\n\n\n\n Pair* result1 = func0(list1, 4, 2);\n\n assert(result1[0].value == 2 && result1[1].value == 4);\n\n assert(strcmp(result1[0].name, \"Akash\") == 0);\n\n assert(strcmp(result1[1].name, \"Akshat\") == 0);\n\n\n\n Pair* result2 = func0(list2, 4, 3);\n\n assert(result2[0].value == 3 && result2[1].value == 5 && result2[2].value == 9);\n\n assert(strcmp(result2[0].name, \"Akash\") == 0);\n\n assert(strcmp(result2[1].name, \"Angat\") == 0);\n\n assert(strcmp(result2[2].name, \"Nepin\") == 0);\n\n\n\n Pair* result3 = func0(list3, 4, 1);\n\n assert(result3[0].value == 9);\n\n assert(strcmp(result3[0].name, \"Ayesha\") == 0);\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmovslq %esi,%rsi\nmov %edx,%ebp\nlea -0x21(%rip),%rcx\npush %rbx\nmov $0x10,%edx\nmov %rdi,%rbx\nsub $0x8,%rsp\ncallq 10a0 \nmovslq %ebp,%rdi\nshl $0x4,%rdi\ncallq 10d0 \ntest %ebp,%ebp\njle 15e2 \nlea -0x1(%rbp),%ecx\nxor %edx,%edx\nadd $0x1,%rcx\nshl $0x4,%rcx\nmovdqu (%rbx,%rdx,1),%xmm0\nmovups %xmm0,(%rax,%rdx,1)\nadd $0x10,%rdx\ncmp %rcx,%rdx\njne 15d0 \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nlea rcx, compare_pairs; compar\nmovsxd rsi, esi; nmemb\nmov rbp, rdi\npush rbx\nmov ebx, edx\nmov edx, 10h; size\nsub rsp, 8\ncall _qsort\nmovsxd rdi, ebx\nshl rdi, 4; size\ncall _malloc\nmov rcx, rax\ntest ebx, ebx\njle short loc_15EA\nmov edx, ebx\nmov rsi, rbp; src\nmov rdi, rax; dest\nshl rdx, 4; n\ncall _memcpy\nmov rcx, rax\nloc_15EA:\nadd rsp, 8\nmov rax, rcx\npop rbx\npop rbp\nretn", + "ida_pseudo": "void *__fastcall func0(void *src, int a2, int a3)\n{\n void *v4; // rax\n void *v5; // rcx\n\n qsort(src, a2, 0x10uLL, compare_pairs);\n v4 = malloc(16LL * a3);\n v5 = v4;\n if ( a3 > 0 )\n return memcpy(v4, src, 16LL * (unsigned int)a3);\n return v5;\n}", + "ida_strip_asm": "sub_15A0:\nendbr64\npush rbp\nlea rcx, compar; compar\nmovsxd rsi, esi; nmemb\nmov rbp, rdi\npush rbx\nmov ebx, edx\nmov edx, 10h; size\nsub rsp, 8\ncall _qsort\nmovsxd rdi, ebx\nshl rdi, 4; size\ncall _malloc\nmov rcx, rax\ntest ebx, ebx\njle short loc_15EA\nmov edx, ebx\nmov rsi, rbp; src\nmov rdi, rax; dest\nshl rdx, 4; n\ncall _memcpy\nmov rcx, rax\nloc_15EA:\nadd rsp, 8\nmov rax, rcx\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "void *__fastcall sub_15A0(void *src, int a2, int a3)\n{\n void *v4; // rax\n void *v5; // rcx\n\n qsort(src, a2, 0x10uLL, compar);\n v4 = malloc(16LL * a3);\n v5 = v4;\n if ( a3 > 0 )\n return memcpy(v4, src, 16LL * (unsigned int)a3);\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_15A0(void *src, int a2, int a3) {\n void *v4;\n void *v5;\n qsort(src, a2, 16uLL, compar);\n v4 = malloc(16LL * a3);\n v5 = v4;\n if (a3 > 0) return memcpy(v4, src, 16LL * (unsigned int)a3);\n return v5;\n}", + "ida_pseudo_norm": "void *func0(void *src, int a2, int a3) {\n void *v4;\n void *v5;\n qsort(src, a2, 16uLL, compare_pairs);\n v4 = malloc(16LL * a3);\n v5 = v4;\n if (a3 > 0) return memcpy(v4, src, 16LL * (unsigned int)a3);\n return v5;\n}" + }, + { + "index": 753, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\ntypedef struct pair {\n\n char* name;\n\n int value;\n\n} Pair;\n\n\n\nint compare_pairs(const void *a, const void *b) {\n\n Pair *pa = (Pair *)a;\n\n Pair *pb = (Pair *)b;\n\n return (pa->value - pb->value);\n\n}\n\n\n\n", + "func": "Pair* func0(Pair arr[], int size, int K) {\n qsort(arr, size, sizeof(Pair), compare_pairs);\n Pair* res = malloc(K * sizeof(Pair));\n for (int i = 0; i < K; ++i) {\n res[i] = arr[i];\n }\n return res;\n}", + "test": "int main() {\n\n Pair list1[] = {{\"Manjeet\", 10}, {\"Akshat\", 4}, {\"Akash\", 2}, {\"Nikhil\", 8}};\n\n Pair list2[] = {{\"Sanjeev\", 11}, {\"Angat\", 5}, {\"Akash\", 3}, {\"Nepin\", 9}};\n\n Pair list3[] = {{\"tanmay\", 14}, {\"Amer\", 11}, {\"Ayesha\", 9}, {\"SKD\", 16}};\n\n\n\n Pair* result1 = func0(list1, 4, 2);\n\n assert(result1[0].value == 2 && result1[1].value == 4);\n\n assert(strcmp(result1[0].name, \"Akash\") == 0);\n\n assert(strcmp(result1[1].name, \"Akshat\") == 0);\n\n\n\n Pair* result2 = func0(list2, 4, 3);\n\n assert(result2[0].value == 3 && result2[1].value == 5 && result2[2].value == 9);\n\n assert(strcmp(result2[0].name, \"Akash\") == 0);\n\n assert(strcmp(result2[1].name, \"Angat\") == 0);\n\n assert(strcmp(result2[2].name, \"Nepin\") == 0);\n\n\n\n Pair* result3 = func0(list3, 4, 1);\n\n assert(result3[0].value == 9);\n\n assert(strcmp(result3[0].name, \"Ayesha\") == 0);\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmovslq %esi,%rsi\nlea -0x1f(%rip),%rcx\nmov %rdi,%rbp\npush %rbx\nmov %edx,%ebx\nmov $0x10,%edx\nsub $0x8,%rsp\ncallq 10b0 \nmovslq %ebx,%rdi\nshl $0x4,%rdi\ncallq 10f0 \nmov %rax,%r8\ntest %ebx,%ebx\njle 15ff \nlea -0x1(%rbx),%edx\nmov %rbp,%rsi\nmov %rax,%rdi\nadd $0x1,%rdx\nshl $0x4,%rdx\ncallq 10e0 \nmov %rax,%r8\nadd $0x8,%rsp\nmov %r8,%rax\npop %rbx\npop %rbp\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nlea rcx, compare_pairs; compar\nmovsxd rsi, esi; nmemb\nmov rbp, rdi\npush rbx\nmov ebx, edx\nmov edx, 10h; size\nsub rsp, 8\ncall _qsort\nmovsxd rdi, ebx\nshl rdi, 4; size\ncall _malloc\nmov rcx, rax\ntest ebx, ebx\njle short loc_15EA\nmov edx, ebx\nmov rsi, rbp; src\nmov rdi, rax; dest\nshl rdx, 4; n\ncall _memcpy\nmov rcx, rax\nloc_15EA:\nadd rsp, 8\nmov rax, rcx\npop rbx\npop rbp\nretn", + "ida_pseudo": "void *__fastcall func0(void *src, int a2, int a3)\n{\n void *v4; // rax\n void *v5; // rcx\n\n qsort(src, a2, 0x10uLL, compare_pairs);\n v4 = malloc(16LL * a3);\n v5 = v4;\n if ( a3 > 0 )\n return memcpy(v4, src, 16LL * (unsigned int)a3);\n return v5;\n}", + "ida_strip_asm": "sub_15A0:\nendbr64\npush rbp\nlea rcx, compar; compar\nmovsxd rsi, esi; nmemb\nmov rbp, rdi\npush rbx\nmov ebx, edx\nmov edx, 10h; size\nsub rsp, 8\ncall _qsort\nmovsxd rdi, ebx\nshl rdi, 4; size\ncall _malloc\nmov rcx, rax\ntest ebx, ebx\njle short loc_15EA\nmov edx, ebx\nmov rsi, rbp; src\nmov rdi, rax; dest\nshl rdx, 4; n\ncall _memcpy\nmov rcx, rax\nloc_15EA:\nadd rsp, 8\nmov rax, rcx\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "void *__fastcall sub_15A0(void *src, int a2, int a3)\n{\n void *v4; // rax\n void *v5; // rcx\n\n qsort(src, a2, 0x10uLL, compar);\n v4 = malloc(16LL * a3);\n v5 = v4;\n if ( a3 > 0 )\n return memcpy(v4, src, 16LL * (unsigned int)a3);\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_15A0(void *src, int a2, int a3) {\n void *v4;\n void *v5;\n qsort(src, a2, 16uLL, compar);\n v4 = malloc(16LL * a3);\n v5 = v4;\n if (a3 > 0) return memcpy(v4, src, 16LL * (unsigned int)a3);\n return v5;\n}", + "ida_pseudo_norm": "void *func0(void *src, int a2, int a3) {\n void *v4;\n void *v5;\n qsort(src, a2, 16uLL, compare_pairs);\n v4 = malloc(16LL * a3);\n v5 = v4;\n if (a3 > 0) return memcpy(v4, src, 16LL * (unsigned int)a3);\n return v5;\n}" + }, + { + "index": 754, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int l1[], int l2[], int l3[], int len, int* resultSize) {\n int* result = (int*)malloc(len * sizeof(int));\n *resultSize = 0;\n for (int i = 0; i < len; ++i) {\n if (l1[i] == l2[i] && l2[i] == l3[i]) {\n result[*resultSize] = l1[i];\n (*resultSize)++;\n }\n }\n return result;\n}", + "test": "int main() {\n\n int resultSize;\n\n\n\n // Test Case 1\n\n int l1a[] = {1, 1, 3, 4, 5, 6, 7};\n\n int l2a[] = {0, 1, 2, 3, 4, 5, 7};\n\n int l3a[] = {0, 1, 2, 3, 4, 5, 7};\n\n int* result1 = func0(l1a, l2a, l3a, 7, &resultSize);\n\n assert(resultSize == 2 && result1[0] == 1 && result1[1] == 7);\n\n free(result1);\n\n\n\n // Test Case 2\n\n int l1b[] = {1, 1, 3, 4, 5, 6, 7};\n\n int l2b[] = {0, 1, 2, 3, 4, 6, 5};\n\n int l3b[] = {0, 1, 2, 3, 4, 6, 7};\n\n int* result2 = func0(l1b, l2b, l3b, 7, &resultSize);\n\n assert(resultSize == 2 && result2[0] == 1 && result2[1] == 6);\n\n free(result2);\n\n\n\n // Test Case 3\n\n int l1c[] = {1, 1, 3, 4, 6, 5, 6};\n\n int l2c[] = {0, 1, 2, 3, 4, 5, 7};\n\n int l3c[] = {0, 1, 2, 3, 4, 5, 7};\n\n int* result3 = func0(l1c, l2c, l3c, 7, &resultSize);\n\n assert(resultSize == 2 && result3[0] == 1 && result3[1] == 5);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x40,%rsp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %ecx,-0x2c(%rbp)\nmov %r8,-0x38(%rbp)\nmov -0x2c(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\nmov -0x38(%rbp),%rax\nmovl $0x0,(%rax)\nmovl $0x0,-0xc(%rbp)\njmpq 1296 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x20(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 1292 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 1292 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x38(%rbp),%rax\nmov (%rax),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\nmov -0x38(%rbp),%rax\nmov (%rax),%eax\nlea 0x1(%rax),%edx\nmov -0x38(%rbp),%rax\nmov %edx,(%rax)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 11f3 \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_28], rdx\nmov [rbp+var_2C], ecx\nmov [rbp+var_38], r8\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov rax, [rbp+var_38]\nmov dword ptr [rax], 0\nmov [rbp+var_C], 0\njmp loc_1296\nloc_11F3:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_1292\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_1292\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov rax, [rbp+var_38]\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nmov rax, [rbp+var_38]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_38]\nmov [rax], edx\nloc_1292:\nadd [rbp+var_C], 1\nloc_1296:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_2C]\njl loc_11F3\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, __int64 a2, __int64 a3, int a4, _DWORD *a5)\n{\n int i; // [rsp+34h] [rbp-Ch]\n _DWORD *v10; // [rsp+38h] [rbp-8h]\n\n v10 = malloc(4LL * a4);\n *a5 = 0;\n for ( i = 0; i < a4; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4LL * i + a2)\n && *(_DWORD *)(4LL * i + a2) == *(_DWORD *)(4LL * i + a3) )\n {\n v10[(*a5)++] = *(_DWORD *)(4LL * i + a1);\n }\n }\n return v10;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_28], rdx\nmov [rbp+var_2C], ecx\nmov [rbp+var_38], r8\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov rax, [rbp+var_38]\nmov dword ptr [rax], 0\nmov [rbp+var_C], 0\njmp loc_1296\nloc_11F3:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_1292\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_1292\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov rax, [rbp+var_38]\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nmov rax, [rbp+var_38]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_38]\nmov [rax], edx\nloc_1292:\nadd [rbp+var_C], 1\nloc_1296:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_2C]\njl loc_11F3\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(__int64 a1, __int64 a2, __int64 a3, int a4, _DWORD *a5)\n{\n int i; // [rsp+34h] [rbp-Ch]\n _DWORD *v10; // [rsp+38h] [rbp-8h]\n\n v10 = malloc(4LL * a4);\n *a5 = 0;\n for ( i = 0; i < a4; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4LL * i + a2)\n && *(_DWORD *)(4LL * i + a2) == *(_DWORD *)(4LL * i + a3) )\n {\n v10[(*a5)++] = *(_DWORD *)(4LL * i + a1);\n }\n }\n return v10;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(long long a1, long long a2, long long a3, int a4,\n uint32_t *a5) {\n int i;\n uint32_t *v10;\n v10 = malloc(4LL * a4);\n *a5 = 0;\n for (i = 0; i < a4; ++i) {\n if (*(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4LL * i + a2) &&\n *(uint32_t *)(4LL * i + a2) == *(uint32_t *)(4LL * i + a3)) {\n v10[(*a5)++] = *(uint32_t *)(4LL * i + a1);\n }\n }\n return v10;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, long long a2, long long a3, int a4,\n uint32_t *a5) {\n int i;\n uint32_t *v10;\n v10 = malloc(4LL * a4);\n *a5 = 0;\n for (i = 0; i < a4; ++i) {\n if (*(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4LL * i + a2) &&\n *(uint32_t *)(4LL * i + a2) == *(uint32_t *)(4LL * i + a3)) {\n v10[(*a5)++] = *(uint32_t *)(4LL * i + a1);\n }\n }\n return v10;\n}" + }, + { + "index": 754, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int l1[], int l2[], int l3[], int len, int* resultSize) {\n int* result = (int*)malloc(len * sizeof(int));\n *resultSize = 0;\n for (int i = 0; i < len; ++i) {\n if (l1[i] == l2[i] && l2[i] == l3[i]) {\n result[*resultSize] = l1[i];\n (*resultSize)++;\n }\n }\n return result;\n}", + "test": "int main() {\n\n int resultSize;\n\n\n\n // Test Case 1\n\n int l1a[] = {1, 1, 3, 4, 5, 6, 7};\n\n int l2a[] = {0, 1, 2, 3, 4, 5, 7};\n\n int l3a[] = {0, 1, 2, 3, 4, 5, 7};\n\n int* result1 = func0(l1a, l2a, l3a, 7, &resultSize);\n\n assert(resultSize == 2 && result1[0] == 1 && result1[1] == 7);\n\n free(result1);\n\n\n\n // Test Case 2\n\n int l1b[] = {1, 1, 3, 4, 5, 6, 7};\n\n int l2b[] = {0, 1, 2, 3, 4, 6, 5};\n\n int l3b[] = {0, 1, 2, 3, 4, 6, 7};\n\n int* result2 = func0(l1b, l2b, l3b, 7, &resultSize);\n\n assert(resultSize == 2 && result2[0] == 1 && result2[1] == 6);\n\n free(result2);\n\n\n\n // Test Case 3\n\n int l1c[] = {1, 1, 3, 4, 6, 5, 6};\n\n int l2c[] = {0, 1, 2, 3, 4, 5, 7};\n\n int l3c[] = {0, 1, 2, 3, 4, 5, 7};\n\n int* result3 = func0(l1c, l2c, l3c, 7, &resultSize);\n\n assert(resultSize == 2 && result3[0] == 1 && result3[1] == 5);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nmov %rsi,%rbp\nmov %rdx,%r13\nmov %ecx,%r14d\nmov %r8,%r12\nmovslq %ecx,%rdi\nshl $0x2,%rdi\ncallq 10b0 \nmovl $0x0,(%r12)\ntest %r14d,%r14d\njle 121a \nlea -0x1(%r14),%edi\nmov $0x0,%edx\njmp 11f4 \nlea 0x1(%rdx),%rcx\ncmp %rdi,%rdx\nje 121a \nmov %rcx,%rdx\nmov (%rbx,%rdx,4),%esi\nmov 0x0(%rbp,%rdx,4),%ecx\ncmp %ecx,%esi\njne 11e8 \ncmp 0x0(%r13,%rdx,4),%ecx\njne 11e8 \nmov (%r12),%ecx\nmovslq %ecx,%r8\nmov %esi,(%rax,%r8,4)\nadd $0x1,%ecx\nmov %ecx,(%r12)\njmp 11e8 \npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov r12, rsi\nmov r14, rdx\nmov r15d, ecx\nmov r13, r8\nmovsxd rbx, ecx\nshl rbx, 2\nmov rdi, rbx; size\ncall _malloc\nmov dword ptr [r13+0], 0\ntest r15d, r15d\njle short loc_121B\nmov edx, 0\njmp short loc_11F6\nloc_11ED:\nadd rdx, 4\ncmp rbx, rdx\njz short loc_121B\nloc_11F6:\nmov esi, [rbp+rdx+0]\nmov ecx, [r12+rdx]\ncmp esi, ecx\njnz short loc_11ED\ncmp ecx, [r14+rdx]\njnz short loc_11ED\nmov ecx, [r13+0]\nmovsxd rdi, ecx\nmov [rax+rdi*4], esi\nadd ecx, 1\nmov [r13+0], ecx\njmp short loc_11ED\nloc_121B:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, __int64 a2, __int64 a3, int a4, int *a5)\n{\n size_t v9; // rbx\n _DWORD *result; // rax\n __int64 v11; // rdx\n int v12; // esi\n int v13; // ecx\n int v14; // ecx\n\n v9 = 4LL * a4;\n result = malloc(v9);\n *a5 = 0;\n if ( a4 > 0 )\n {\n v11 = 0LL;\n do\n {\n v12 = *(_DWORD *)(a1 + v11);\n v13 = *(_DWORD *)(a2 + v11);\n if ( v12 == v13 && v13 == *(_DWORD *)(a3 + v11) )\n {\n v14 = *a5;\n result[*a5] = v12;\n *a5 = v14 + 1;\n }\n v11 += 4LL;\n }\n while ( v9 != v11 );\n }\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov r12, rsi\nmov r14, rdx\nmov r15d, ecx\nmov r13, r8\nmovsxd rbx, ecx\nshl rbx, 2\nmov rdi, rbx; size\ncall _malloc\nmov dword ptr [r13+0], 0\ntest r15d, r15d\njle short loc_121B\nmov edx, 0\njmp short loc_11F6\nloc_11ED:\nadd rdx, 4\ncmp rbx, rdx\njz short loc_121B\nloc_11F6:\nmov esi, [rbp+rdx+0]\nmov ecx, [r12+rdx]\ncmp esi, ecx\njnz short loc_11ED\ncmp ecx, [r14+rdx]\njnz short loc_11ED\nmov ecx, [r13+0]\nmovsxd rdi, ecx\nmov [rax+rdi*4], esi\nadd ecx, 1\nmov [r13+0], ecx\njmp short loc_11ED\nloc_121B:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(__int64 a1, __int64 a2, __int64 a3, int a4, int *a5)\n{\n size_t v9; // rbx\n _DWORD *result; // rax\n __int64 v11; // rdx\n int v12; // esi\n int v13; // ecx\n int v14; // ecx\n\n v9 = 4LL * a4;\n result = malloc(v9);\n *a5 = 0;\n if ( a4 > 0 )\n {\n v11 = 0LL;\n do\n {\n v12 = *(_DWORD *)(a1 + v11);\n v13 = *(_DWORD *)(a2 + v11);\n if ( v12 == v13 && v13 == *(_DWORD *)(a3 + v11) )\n {\n v14 = *a5;\n result[*a5] = v12;\n *a5 = v14 + 1;\n }\n v11 += 4LL;\n }\n while ( v9 != v11 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(long long a1, long long a2, long long a3, int a4, int *a5) {\n unsigned int v9;\n uint32_t *result;\n long long v11;\n int v12;\n int v13;\n int v14;\n v9 = 4LL * a4;\n result = malloc(v9);\n *a5 = 0;\n if (a4 > 0) {\n v11 = 0LL;\n do {\n v12 = *(uint32_t *)(a1 + v11);\n v13 = *(uint32_t *)(a2 + v11);\n if (v12 == v13 && v13 == *(uint32_t *)(a3 + v11)) {\n v14 = *a5;\n result[*a5] = v12;\n *a5 = v14 + 1;\n }\n v11 += 4LL;\n } while (v9 != v11);\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, long long a2, long long a3, int a4, int *a5) {\n unsigned int v9;\n uint32_t *result;\n long long v11;\n int v12;\n int v13;\n int v14;\n v9 = 4LL * a4;\n result = malloc(v9);\n *a5 = 0;\n if (a4 > 0) {\n v11 = 0LL;\n do {\n v12 = *(uint32_t *)(a1 + v11);\n v13 = *(uint32_t *)(a2 + v11);\n if (v12 == v13 && v13 == *(uint32_t *)(a3 + v11)) {\n v14 = *a5;\n result[*a5] = v12;\n *a5 = v14 + 1;\n }\n v11 += 4LL;\n } while (v9 != v11);\n }\n return result;\n}" + }, + { + "index": 754, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int l1[], int l2[], int l3[], int len, int* resultSize) {\n int* result = (int*)malloc(len * sizeof(int));\n *resultSize = 0;\n for (int i = 0; i < len; ++i) {\n if (l1[i] == l2[i] && l2[i] == l3[i]) {\n result[*resultSize] = l1[i];\n (*resultSize)++;\n }\n }\n return result;\n}", + "test": "int main() {\n\n int resultSize;\n\n\n\n // Test Case 1\n\n int l1a[] = {1, 1, 3, 4, 5, 6, 7};\n\n int l2a[] = {0, 1, 2, 3, 4, 5, 7};\n\n int l3a[] = {0, 1, 2, 3, 4, 5, 7};\n\n int* result1 = func0(l1a, l2a, l3a, 7, &resultSize);\n\n assert(resultSize == 2 && result1[0] == 1 && result1[1] == 7);\n\n free(result1);\n\n\n\n // Test Case 2\n\n int l1b[] = {1, 1, 3, 4, 5, 6, 7};\n\n int l2b[] = {0, 1, 2, 3, 4, 6, 5};\n\n int l3b[] = {0, 1, 2, 3, 4, 6, 7};\n\n int* result2 = func0(l1b, l2b, l3b, 7, &resultSize);\n\n assert(resultSize == 2 && result2[0] == 1 && result2[1] == 6);\n\n free(result2);\n\n\n\n // Test Case 3\n\n int l1c[] = {1, 1, 3, 4, 6, 5, 6};\n\n int l2c[] = {0, 1, 2, 3, 4, 5, 7};\n\n int l3c[] = {0, 1, 2, 3, 4, 5, 7};\n\n int* result3 = func0(l1c, l2c, l3c, 7, &resultSize);\n\n assert(resultSize == 2 && result3[0] == 1 && result3[1] == 5);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\nmov %rdx,%r14\npush %r13\nmov %r8,%r13\npush %r12\npush %rbp\nmov %rsi,%rbp\npush %rbx\nmov %rdi,%rbx\nmovslq %ecx,%rdi\nmov %rdi,%r12\nshl $0x2,%rdi\ncallq 10b0 \nmovl $0x0,0x0(%r13)\ntest %r12d,%r12d\njle 1516 \nlea -0x1(%r12),%esi\nxor %ecx,%ecx\njmp 14ec \nnopl (%rax)\nlea 0x1(%rcx),%rdi\ncmp %rcx,%rsi\nje 1516 \nmov %rdi,%rcx\nmov (%rbx,%rcx,4),%edi\ncmp 0x0(%rbp,%rcx,4),%edi\njne 14e0 \ncmp (%r14,%rcx,4),%edi\njne 14e0 \nmovslq 0x0(%r13),%r8\nmov %r8,%rdx\nmov %edi,(%rax,%r8,4)\nlea 0x1(%rcx),%rdi\nadd $0x1,%edx\nmov %edx,0x0(%r13)\ncmp %rcx,%rsi\njne 14e9 \npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14, rdx\npush r13\nmov r13, r8\npush r12\nmov r12, rsi\npush rbp\nmov rbp, rdi\npush rbx\nmovsxd rbx, ecx\nmov r15, rbx\nshl rbx, 2\nmov rdi, rbx; size\nsub rsp, 8\ncall _malloc\nmov dword ptr [r13+0], 0\ntest r15d, r15d\njle short loc_14CB\nxor edx, edx\njmp short loc_14A1\nloc_1498:\nadd rdx, 4\ncmp rbx, rdx\njz short loc_14CB\nloc_14A1:\nmov ecx, [rbp+rdx+0]\ncmp ecx, [r12+rdx]\njnz short loc_1498\ncmp ecx, [r14+rdx]\njnz short loc_1498\nmovsxd rdi, dword ptr [r13+0]\nadd rdx, 4\nmov rsi, rdi\nmov [rax+rdi*4], ecx\nadd esi, 1\nmov [r13+0], esi\ncmp rbx, rdx\njnz short loc_14A1\nloc_14CB:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, __int64 a2, __int64 a3, int a4, int *a5)\n{\n size_t v9; // rbx\n _DWORD *result; // rax\n __int64 v11; // rdx\n int v12; // ecx\n int v13; // esi\n\n v9 = 4LL * a4;\n result = malloc(v9);\n *a5 = 0;\n if ( a4 > 0 )\n {\n v11 = 0LL;\n do\n {\n while ( 1 )\n {\n v12 = *(_DWORD *)(a1 + v11);\n if ( v12 == *(_DWORD *)(a2 + v11) && v12 == *(_DWORD *)(a3 + v11) )\n break;\n v11 += 4LL;\n if ( v9 == v11 )\n return result;\n }\n v11 += 4LL;\n v13 = *a5;\n result[*a5] = v12;\n *a5 = v13 + 1;\n }\n while ( v9 != v11 );\n }\n return result;\n}", + "ida_strip_asm": "sub_1450:\nendbr64\npush r15\npush r14\nmov r14, rdx\npush r13\nmov r13, r8\npush r12\nmov r12, rsi\npush rbp\nmov rbp, rdi\npush rbx\nmovsxd rbx, ecx\nmov r15, rbx\nshl rbx, 2\nmov rdi, rbx; size\nsub rsp, 8\ncall _malloc\nmov dword ptr [r13+0], 0\ntest r15d, r15d\njle short loc_14CB\nxor edx, edx\njmp short loc_14A1\nloc_1498:\nadd rdx, 4\ncmp rbx, rdx\njz short loc_14CB\nloc_14A1:\nmov ecx, [rbp+rdx+0]\ncmp ecx, [r12+rdx]\njnz short loc_1498\ncmp ecx, [r14+rdx]\njnz short loc_1498\nmovsxd rdi, dword ptr [r13+0]\nadd rdx, 4\nmov rsi, rdi\nmov [rax+rdi*4], ecx\nadd esi, 1\nmov [r13+0], esi\ncmp rbx, rdx\njnz short loc_14A1\nloc_14CB:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1450(__int64 a1, __int64 a2, __int64 a3, int a4, int *a5)\n{\n size_t v9; // rbx\n _DWORD *result; // rax\n __int64 v11; // rdx\n int v12; // ecx\n int v13; // esi\n\n v9 = 4LL * a4;\n result = malloc(v9);\n *a5 = 0;\n if ( a4 > 0 )\n {\n v11 = 0LL;\n do\n {\n while ( 1 )\n {\n v12 = *(_DWORD *)(a1 + v11);\n if ( v12 == *(_DWORD *)(a2 + v11) && v12 == *(_DWORD *)(a3 + v11) )\n break;\n v11 += 4LL;\n if ( v9 == v11 )\n return result;\n }\n v11 += 4LL;\n v13 = *a5;\n result[*a5] = v12;\n *a5 = v13 + 1;\n }\n while ( v9 != v11 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1450(long long a1, long long a2, long long a3, int a4, int *a5) {\n unsigned int v9;\n uint32_t *result;\n long long v11;\n int v12;\n int v13;\n v9 = 4LL * a4;\n result = malloc(v9);\n *a5 = 0;\n if (a4 > 0) {\n v11 = 0LL;\n do {\n while (1) {\n v12 = *(uint32_t *)(a1 + v11);\n if (v12 == *(uint32_t *)(a2 + v11) && v12 == *(uint32_t *)(a3 + v11))\n break;\n v11 += 4LL;\n if (v9 == v11) return result;\n }\n v11 += 4LL;\n v13 = *a5;\n result[*a5] = v12;\n *a5 = v13 + 1;\n } while (v9 != v11);\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, long long a2, long long a3, int a4, int *a5) {\n unsigned int v9;\n uint32_t *result;\n long long v11;\n int v12;\n int v13;\n v9 = 4LL * a4;\n result = malloc(v9);\n *a5 = 0;\n if (a4 > 0) {\n v11 = 0LL;\n do {\n while (1) {\n v12 = *(uint32_t *)(a1 + v11);\n if (v12 == *(uint32_t *)(a2 + v11) && v12 == *(uint32_t *)(a3 + v11))\n break;\n v11 += 4LL;\n if (v9 == v11) return result;\n }\n v11 += 4LL;\n v13 = *a5;\n result[*a5] = v12;\n *a5 = v13 + 1;\n } while (v9 != v11);\n }\n return result;\n}" + }, + { + "index": 754, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int l1[], int l2[], int l3[], int len, int* resultSize) {\n int* result = (int*)malloc(len * sizeof(int));\n *resultSize = 0;\n for (int i = 0; i < len; ++i) {\n if (l1[i] == l2[i] && l2[i] == l3[i]) {\n result[*resultSize] = l1[i];\n (*resultSize)++;\n }\n }\n return result;\n}", + "test": "int main() {\n\n int resultSize;\n\n\n\n // Test Case 1\n\n int l1a[] = {1, 1, 3, 4, 5, 6, 7};\n\n int l2a[] = {0, 1, 2, 3, 4, 5, 7};\n\n int l3a[] = {0, 1, 2, 3, 4, 5, 7};\n\n int* result1 = func0(l1a, l2a, l3a, 7, &resultSize);\n\n assert(resultSize == 2 && result1[0] == 1 && result1[1] == 7);\n\n free(result1);\n\n\n\n // Test Case 2\n\n int l1b[] = {1, 1, 3, 4, 5, 6, 7};\n\n int l2b[] = {0, 1, 2, 3, 4, 6, 5};\n\n int l3b[] = {0, 1, 2, 3, 4, 6, 7};\n\n int* result2 = func0(l1b, l2b, l3b, 7, &resultSize);\n\n assert(resultSize == 2 && result2[0] == 1 && result2[1] == 6);\n\n free(result2);\n\n\n\n // Test Case 3\n\n int l1c[] = {1, 1, 3, 4, 6, 5, 6};\n\n int l2c[] = {0, 1, 2, 3, 4, 5, 7};\n\n int l3c[] = {0, 1, 2, 3, 4, 5, 7};\n\n int* result3 = func0(l1c, l2c, l3c, 7, &resultSize);\n\n assert(resultSize == 2 && result3[0] == 1 && result3[1] == 5);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\nmov %rdx,%r14\npush %r13\nmov %r8,%r13\npush %r12\npush %rbp\nmov %rsi,%rbp\npush %rbx\nmov %rdi,%rbx\nmovslq %ecx,%rdi\nmov %rdi,%r12\nshl $0x2,%rdi\ncallq 10b0 \nmovl $0x0,0x0(%r13)\ntest %r12d,%r12d\njle 14c6 \nlea -0x1(%r12),%esi\nxor %ecx,%ecx\njmp 149c \nnopl (%rax)\nlea 0x1(%rcx),%rdi\ncmp %rsi,%rcx\nje 14c6 \nmov %rdi,%rcx\nmov (%rbx,%rcx,4),%edi\ncmp 0x0(%rbp,%rcx,4),%edi\njne 1490 \ncmp (%r14,%rcx,4),%edi\njne 1490 \nmovslq 0x0(%r13),%r8\nmov %r8,%rdx\nmov %edi,(%rax,%r8,4)\nlea 0x1(%rcx),%rdi\nadd $0x1,%edx\nmov %edx,0x0(%r13)\ncmp %rsi,%rcx\njne 1499 \npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14, rdx\npush r13\nmov r13, r8\npush r12\nmov r12, rsi\npush rbp\nmov rbp, rdi\npush rbx\nmovsxd rbx, ecx\nmov r15, rbx\nshl rbx, 2\nmov rdi, rbx; size\nsub rsp, 8\ncall _malloc\nmov dword ptr [r13+0], 0\ntest r15d, r15d\njle short loc_14CB\nxor edx, edx\njmp short loc_14A1\nloc_1498:\nadd rdx, 4\ncmp rbx, rdx\njz short loc_14CB\nloc_14A1:\nmov ecx, [rbp+rdx+0]\ncmp ecx, [r12+rdx]\njnz short loc_1498\ncmp ecx, [r14+rdx]\njnz short loc_1498\nmovsxd rdi, dword ptr [r13+0]\nadd rdx, 4\nmov rsi, rdi\nmov [rax+rdi*4], ecx\nadd esi, 1\nmov [r13+0], esi\ncmp rbx, rdx\njnz short loc_14A1\nloc_14CB:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, __int64 a2, __int64 a3, int a4, int *a5)\n{\n size_t v9; // rbx\n _DWORD *result; // rax\n __int64 v11; // rdx\n int v12; // ecx\n int v13; // esi\n\n v9 = 4LL * a4;\n result = malloc(v9);\n *a5 = 0;\n if ( a4 > 0 )\n {\n v11 = 0LL;\n do\n {\n while ( 1 )\n {\n v12 = *(_DWORD *)(a1 + v11);\n if ( v12 == *(_DWORD *)(a2 + v11) && v12 == *(_DWORD *)(a3 + v11) )\n break;\n v11 += 4LL;\n if ( v9 == v11 )\n return result;\n }\n v11 += 4LL;\n v13 = *a5;\n result[*a5] = v12;\n *a5 = v13 + 1;\n }\n while ( v9 != v11 );\n }\n return result;\n}", + "ida_strip_asm": "sub_1450:\nendbr64\npush r15\npush r14\nmov r14, rdx\npush r13\nmov r13, r8\npush r12\nmov r12, rsi\npush rbp\nmov rbp, rdi\npush rbx\nmovsxd rbx, ecx\nmov r15, rbx\nshl rbx, 2\nmov rdi, rbx; size\nsub rsp, 8\ncall _malloc\nmov dword ptr [r13+0], 0\ntest r15d, r15d\njle short loc_14CB\nxor edx, edx\njmp short loc_14A1\nloc_1498:\nadd rdx, 4\ncmp rbx, rdx\njz short loc_14CB\nloc_14A1:\nmov ecx, [rbp+rdx+0]\ncmp ecx, [r12+rdx]\njnz short loc_1498\ncmp ecx, [r14+rdx]\njnz short loc_1498\nmovsxd rdi, dword ptr [r13+0]\nadd rdx, 4\nmov rsi, rdi\nmov [rax+rdi*4], ecx\nadd esi, 1\nmov [r13+0], esi\ncmp rbx, rdx\njnz short loc_14A1\nloc_14CB:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1450(__int64 a1, __int64 a2, __int64 a3, int a4, int *a5)\n{\n size_t v9; // rbx\n _DWORD *result; // rax\n __int64 v11; // rdx\n int v12; // ecx\n int v13; // esi\n\n v9 = 4LL * a4;\n result = malloc(v9);\n *a5 = 0;\n if ( a4 > 0 )\n {\n v11 = 0LL;\n do\n {\n while ( 1 )\n {\n v12 = *(_DWORD *)(a1 + v11);\n if ( v12 == *(_DWORD *)(a2 + v11) && v12 == *(_DWORD *)(a3 + v11) )\n break;\n v11 += 4LL;\n if ( v9 == v11 )\n return result;\n }\n v11 += 4LL;\n v13 = *a5;\n result[*a5] = v12;\n *a5 = v13 + 1;\n }\n while ( v9 != v11 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1450(long long a1, long long a2, long long a3, int a4, int *a5) {\n unsigned int v9;\n uint32_t *result;\n long long v11;\n int v12;\n int v13;\n v9 = 4LL * a4;\n result = malloc(v9);\n *a5 = 0;\n if (a4 > 0) {\n v11 = 0LL;\n do {\n while (1) {\n v12 = *(uint32_t *)(a1 + v11);\n if (v12 == *(uint32_t *)(a2 + v11) && v12 == *(uint32_t *)(a3 + v11))\n break;\n v11 += 4LL;\n if (v9 == v11) return result;\n }\n v11 += 4LL;\n v13 = *a5;\n result[*a5] = v12;\n *a5 = v13 + 1;\n } while (v9 != v11);\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, long long a2, long long a3, int a4, int *a5) {\n unsigned int v9;\n uint32_t *result;\n long long v11;\n int v12;\n int v13;\n v9 = 4LL * a4;\n result = malloc(v9);\n *a5 = 0;\n if (a4 > 0) {\n v11 = 0LL;\n do {\n while (1) {\n v12 = *(uint32_t *)(a1 + v11);\n if (v12 == *(uint32_t *)(a2 + v11) && v12 == *(uint32_t *)(a3 + v11))\n break;\n v11 += 4LL;\n if (v9 == v11) return result;\n }\n v11 += 4LL;\n v13 = *a5;\n result[*a5] = v12;\n *a5 = v13 + 1;\n } while (v9 != v11);\n }\n return result;\n}" + }, + { + "index": 755, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "double func0(double* numbers, int length) {\n if (length < 2) {\n return -9999999;\n }\n int count = 0;\n for (int i = 0; i < length; i++) {\n for (int j = i + 1; j < length; j++) {\n if (numbers[j] == numbers[i]) {\n count += 1;\n break;\n }\n }\n }\n if (length == 2 && count == 1) {\n return -9999999;\n }\n double* uniq_items = malloc(length * sizeof(double));\n int uniq_length = 0;\n for (int i = 0; i < length; i++) {\n int found = 0;\n for (int j = 0; j < uniq_length; j++) {\n if (uniq_items[j] == numbers[i]) {\n found = 1;\n break;\n }\n }\n if (!found) {\n uniq_items[uniq_length++] = numbers[i];\n }\n }\n for (int i = 0; i < uniq_length; i++) {\n for (int j = i + 1; j < uniq_length; j++) {\n if (uniq_items[i] > uniq_items[j]) {\n double temp = uniq_items[i];\n uniq_items[i] = uniq_items[j];\n uniq_items[j] = temp;\n }\n }\n }\n double result = uniq_items[1];\n free(uniq_items);\n return result;\n}", + "test": "int main() {\n\n double arr1[] = {1, 2, -8, -2, 0, -2};\n\n double arr2[] = {1, 1, -0.5, 0, 2, -2, -2};\n\n double arr3[] = {2, 2};\n\n\n\n assert(func0(arr1, 6) == -2);\n\n assert(func0(arr2, 7) == -0.5);\n\n assert(func0(arr3, 2) == -9999999); // representing None\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x50,%rsp\nmov %rdi,-0x48(%rbp)\nmov %esi,-0x4c(%rbp)\ncmpl $0x1,-0x4c(%rbp)\njg 11cf \nmovsd 0xec6(%rip),%xmm0\njmpq 142c \nmovl $0x0,-0x3c(%rbp)\nmovl $0x0,-0x38(%rbp)\njmp 123c \nmov -0x38(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x34(%rbp)\njmp 1230 \nmov -0x34(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmovsd (%rax),%xmm0\nmov -0x38(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmovsd (%rax),%xmm1\nucomisd %xmm1,%xmm0\njp 122c \nucomisd %xmm1,%xmm0\njne 122c \naddl $0x1,-0x3c(%rbp)\njmp 1238 \naddl $0x1,-0x34(%rbp)\nmov -0x34(%rbp),%eax\ncmp -0x4c(%rbp),%eax\njl 11ea \naddl $0x1,-0x38(%rbp)\nmov -0x38(%rbp),%eax\ncmp -0x4c(%rbp),%eax\njl 11df \ncmpl $0x2,-0x4c(%rbp)\njne 125d \ncmpl $0x1,-0x3c(%rbp)\njne 125d \nmovsd 0xe38(%rip),%xmm0\njmpq 142c \nmov -0x4c(%rbp),%eax\ncltq\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x18(%rbp)\nmovl $0x0,-0x30(%rbp)\nmovl $0x0,-0x2c(%rbp)\njmpq 1327 \nmovl $0x0,-0x28(%rbp)\nmovl $0x0,-0x24(%rbp)\njmp 12de \nmov -0x24(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovsd (%rax),%xmm0\nmov -0x2c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmovsd (%rax),%xmm1\nucomisd %xmm1,%xmm0\njp 12da \nucomisd %xmm1,%xmm0\njne 12da \nmovl $0x1,-0x28(%rbp)\njmp 12e6 \naddl $0x1,-0x24(%rbp)\nmov -0x24(%rbp),%eax\ncmp -0x30(%rbp),%eax\njl 1295 \ncmpl $0x0,-0x28(%rbp)\njne 1323 \nmov -0x2c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x48(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x30(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x30(%rbp)\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovsd (%rcx),%xmm0\nmovsd %xmm0,(%rax)\naddl $0x1,-0x2c(%rbp)\nmov -0x2c(%rbp),%eax\ncmp -0x4c(%rbp),%eax\njl 1285 \nmovl $0x0,-0x20(%rbp)\njmpq 1401 \nmov -0x20(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x1c(%rbp)\njmpq 13f1 \nmov -0x20(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovsd (%rax),%xmm0\nmov -0x1c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovsd (%rax),%xmm1\ncomisd %xmm1,%xmm0\njbe 13ed \nmov -0x20(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovsd (%rax),%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmov -0x1c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0x20(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmovsd (%rdx),%xmm0\nmovsd %xmm0,(%rax)\nmov -0x1c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovsd -0x8(%rbp),%xmm0\nmovsd %xmm0,(%rax)\naddl $0x1,-0x1c(%rbp)\nmov -0x1c(%rbp),%eax\ncmp -0x30(%rbp),%eax\njl 134d \naddl $0x1,-0x20(%rbp)\nmov -0x20(%rbp),%eax\ncmp -0x30(%rbp),%eax\njl 133f \nmov -0x18(%rbp),%rax\nmovsd 0x8(%rax),%xmm0\nmovsd %xmm0,-0x10(%rbp)\nmov -0x18(%rbp),%rax\nmov %rax,%rdi\ncallq 1080 \nmovsd -0x10(%rbp),%xmm0\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+var_48], rdi\nmov [rbp+var_4C], esi\ncmp [rbp+var_4C], 1\njg short loc_11CF\nmovsd xmm0, cs:qword_2078\njmp locret_142C\nloc_11CF:\nmov [rbp+var_3C], 0\nmov [rbp+var_38], 0\njmp short loc_123C\nloc_11DF:\nmov eax, [rbp+var_38]\nadd eax, 1\nmov [rbp+var_34], eax\njmp short loc_1230\nloc_11EA:\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmovsd xmm0, qword ptr [rax]\nmov eax, [rbp+var_38]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmovsd xmm1, qword ptr [rax]\nucomisd xmm0, xmm1\njp short loc_122C\nucomisd xmm0, xmm1\njnz short loc_122C\nadd [rbp+var_3C], 1\njmp short loc_1238\nloc_122C:\nadd [rbp+var_34], 1\nloc_1230:\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_4C]\njl short loc_11EA\nloc_1238:\nadd [rbp+var_38], 1\nloc_123C:\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_4C]\njl short loc_11DF\ncmp [rbp+var_4C], 2\njnz short loc_125D\ncmp [rbp+var_3C], 1\njnz short loc_125D\nmovsd xmm0, cs:qword_2078\njmp locret_142C\nloc_125D:\nmov eax, [rbp+var_4C]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov [rbp+var_30], 0\nmov [rbp+var_2C], 0\njmp loc_1327\nloc_1285:\nmov [rbp+var_28], 0\nmov [rbp+var_24], 0\njmp short loc_12DE\nloc_1295:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmovsd xmm0, qword ptr [rax]\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmovsd xmm1, qword ptr [rax]\nucomisd xmm0, xmm1\njp short loc_12DA\nucomisd xmm0, xmm1\njnz short loc_12DA\nmov [rbp+var_28], 1\njmp short loc_12E6\nloc_12DA:\nadd [rbp+var_24], 1\nloc_12DE:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_30]\njl short loc_1295\nloc_12E6:\ncmp [rbp+var_28], 0\njnz short loc_1323\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_30]\nlea edx, [rax+1]\nmov [rbp+var_30], edx\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmovsd xmm0, qword ptr [rcx]\nmovsd qword ptr [rax], xmm0\nloc_1323:\nadd [rbp+var_2C], 1\nloc_1327:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_4C]\njl loc_1285\nmov [rbp+var_20], 0\njmp loc_1401\nloc_133F:\nmov eax, [rbp+var_20]\nadd eax, 1\nmov [rbp+var_1C], eax\njmp loc_13F1\nloc_134D:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmovsd xmm0, qword ptr [rax]\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmovsd xmm1, qword ptr [rax]\ncomisd xmm0, xmm1\njbe short loc_13ED\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmovsd xmm0, qword ptr [rax]\nmovsd [rbp+var_8], xmm0\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov eax, [rbp+var_20]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rcx\nmovsd xmm0, qword ptr [rdx]\nmovsd qword ptr [rax], xmm0\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmovsd xmm0, [rbp+var_8]\nmovsd qword ptr [rax], xmm0\nloc_13ED:\nadd [rbp+var_1C], 1\nloc_13F1:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_30]\njl loc_134D\nadd [rbp+var_20], 1\nloc_1401:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_30]\njl loc_133F\nmov rax, [rbp+ptr]\nmovsd xmm0, qword ptr [rax+8]\nmovsd [rbp+var_10], xmm0\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmovsd xmm0, [rbp+var_10]\nlocret_142C:\nleave\nretn", + "ida_pseudo": "double __fastcall func0(__int64 a1, int a2)\n{\n int v3; // eax\n int v4; // [rsp+14h] [rbp-3Ch]\n int i; // [rsp+18h] [rbp-38h]\n int j; // [rsp+1Ch] [rbp-34h]\n int v7; // [rsp+20h] [rbp-30h]\n int k; // [rsp+24h] [rbp-2Ch]\n int v9; // [rsp+28h] [rbp-28h]\n int m; // [rsp+2Ch] [rbp-24h]\n int n; // [rsp+30h] [rbp-20h]\n int ii; // [rsp+34h] [rbp-1Ch]\n double *ptr; // [rsp+38h] [rbp-18h]\n double v14; // [rsp+40h] [rbp-10h]\n double v15; // [rsp+48h] [rbp-8h]\n\n if ( a2 <= 1 )\n return -9999999.0;\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( *(double *)(8LL * j + a1) == *(double *)(8LL * i + a1) )\n {\n ++v4;\n break;\n }\n }\n }\n if ( a2 == 2 && v4 == 1 )\n return -9999999.0;\n ptr = (double *)malloc(8LL * a2);\n v7 = 0;\n for ( k = 0; k < a2; ++k )\n {\n v9 = 0;\n for ( m = 0; m < v7; ++m )\n {\n if ( ptr[m] == *(double *)(8LL * k + a1) )\n {\n v9 = 1;\n break;\n }\n }\n if ( !v9 )\n {\n v3 = v7++;\n ptr[v3] = *(double *)(8LL * k + a1);\n }\n }\n for ( n = 0; n < v7; ++n )\n {\n for ( ii = n + 1; ii < v7; ++ii )\n {\n if ( ptr[n] > ptr[ii] )\n {\n v15 = ptr[n];\n ptr[n] = ptr[ii];\n ptr[ii] = v15;\n }\n }\n }\n v14 = ptr[1];\n free(ptr);\n return v14;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+var_48], rdi\nmov [rbp+var_4C], esi\ncmp [rbp+var_4C], 1\njg short loc_11CF\nmovsd xmm0, cs:qword_2078\njmp locret_142C\nloc_11CF:\nmov [rbp+var_3C], 0\nmov [rbp+var_38], 0\njmp short loc_123C\nloc_11DF:\nmov eax, [rbp+var_38]\nadd eax, 1\nmov [rbp+var_34], eax\njmp short loc_1230\nloc_11EA:\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmovsd xmm0, qword ptr [rax]\nmov eax, [rbp+var_38]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmovsd xmm1, qword ptr [rax]\nucomisd xmm0, xmm1\njp short loc_122C\nucomisd xmm0, xmm1\njnz short loc_122C\nadd [rbp+var_3C], 1\njmp short loc_1238\nloc_122C:\nadd [rbp+var_34], 1\nloc_1230:\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_4C]\njl short loc_11EA\nloc_1238:\nadd [rbp+var_38], 1\nloc_123C:\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_4C]\njl short loc_11DF\ncmp [rbp+var_4C], 2\njnz short loc_125D\ncmp [rbp+var_3C], 1\njnz short loc_125D\nmovsd xmm0, cs:qword_2078\njmp locret_142C\nloc_125D:\nmov eax, [rbp+var_4C]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov [rbp+var_30], 0\nmov [rbp+var_2C], 0\njmp loc_1327\nloc_1285:\nmov [rbp+var_28], 0\nmov [rbp+var_24], 0\njmp short loc_12DE\nloc_1295:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmovsd xmm0, qword ptr [rax]\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmovsd xmm1, qword ptr [rax]\nucomisd xmm0, xmm1\njp short loc_12DA\nucomisd xmm0, xmm1\njnz short loc_12DA\nmov [rbp+var_28], 1\njmp short loc_12E6\nloc_12DA:\nadd [rbp+var_24], 1\nloc_12DE:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_30]\njl short loc_1295\nloc_12E6:\ncmp [rbp+var_28], 0\njnz short loc_1323\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_30]\nlea edx, [rax+1]\nmov [rbp+var_30], edx\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmovsd xmm0, qword ptr [rcx]\nmovsd qword ptr [rax], xmm0\nloc_1323:\nadd [rbp+var_2C], 1\nloc_1327:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_4C]\njl loc_1285\nmov [rbp+var_20], 0\njmp loc_1401\nloc_133F:\nmov eax, [rbp+var_20]\nadd eax, 1\nmov [rbp+var_1C], eax\njmp loc_13F1\nloc_134D:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmovsd xmm0, qword ptr [rax]\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmovsd xmm1, qword ptr [rax]\ncomisd xmm0, xmm1\njbe short loc_13ED\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmovsd xmm0, qword ptr [rax]\nmovsd [rbp+var_8], xmm0\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov eax, [rbp+var_20]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rcx\nmovsd xmm0, qword ptr [rdx]\nmovsd qword ptr [rax], xmm0\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmovsd xmm0, [rbp+var_8]\nmovsd qword ptr [rax], xmm0\nloc_13ED:\nadd [rbp+var_1C], 1\nloc_13F1:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_30]\njl loc_134D\nadd [rbp+var_20], 1\nloc_1401:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_30]\njl loc_133F\nmov rax, [rbp+ptr]\nmovsd xmm0, qword ptr [rax+8]\nmovsd [rbp+var_10], xmm0\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmovsd xmm0, [rbp+var_10]\nlocret_142C:\nleave\nretn", + "ida_strip_pseudo": "double __fastcall sub_11A9(__int64 a1, int a2)\n{\n int v3; // eax\n int v4; // [rsp+14h] [rbp-3Ch]\n int i; // [rsp+18h] [rbp-38h]\n int j; // [rsp+1Ch] [rbp-34h]\n int v7; // [rsp+20h] [rbp-30h]\n int k; // [rsp+24h] [rbp-2Ch]\n int v9; // [rsp+28h] [rbp-28h]\n int m; // [rsp+2Ch] [rbp-24h]\n int n; // [rsp+30h] [rbp-20h]\n int ii; // [rsp+34h] [rbp-1Ch]\n double *ptr; // [rsp+38h] [rbp-18h]\n double v14; // [rsp+40h] [rbp-10h]\n double v15; // [rsp+48h] [rbp-8h]\n\n if ( a2 <= 1 )\n return -9999999.0;\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( *(double *)(8LL * j + a1) == *(double *)(8LL * i + a1) )\n {\n ++v4;\n break;\n }\n }\n }\n if ( a2 == 2 && v4 == 1 )\n return -9999999.0;\n ptr = (double *)malloc(8LL * a2);\n v7 = 0;\n for ( k = 0; k < a2; ++k )\n {\n v9 = 0;\n for ( m = 0; m < v7; ++m )\n {\n if ( ptr[m] == *(double *)(8LL * k + a1) )\n {\n v9 = 1;\n break;\n }\n }\n if ( !v9 )\n {\n v3 = v7++;\n ptr[v3] = *(double *)(8LL * k + a1);\n }\n }\n for ( n = 0; n < v7; ++n )\n {\n for ( ii = n + 1; ii < v7; ++ii )\n {\n if ( ptr[n] > ptr[ii] )\n {\n v15 = ptr[n];\n ptr[n] = ptr[ii];\n ptr[ii] = v15;\n }\n }\n }\n v14 = ptr[1];\n free(ptr);\n return v14;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_11A9(long long a1, int a2) {\n int v3;\n int v4;\n int i;\n int j;\n int v7;\n int k;\n int v9;\n int m;\n int n;\n int ii;\n double *ptr;\n double v14;\n double v15;\n if (a2 <= 1) return -9999999.0;\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if (*(double *)(8LL * j + a1) == *(double *)(8LL * i + a1)) {\n ++v4;\n break;\n }\n }\n }\n if (a2 == 2 && v4 == 1) return -9999999.0;\n ptr = (double *)malloc(8LL * a2);\n v7 = 0;\n for (k = 0; k < a2; ++k) {\n v9 = 0;\n for (m = 0; m < v7; ++m) {\n if (ptr[m] == *(double *)(8LL * k + a1)) {\n v9 = 1;\n break;\n }\n }\n if (!v9) {\n v3 = v7++;\n ptr[v3] = *(double *)(8LL * k + a1);\n }\n }\n for (n = 0; n < v7; ++n) {\n for (ii = n + 1; ii < v7; ++ii) {\n if (ptr[n] > ptr[ii]) {\n v15 = ptr[n];\n ptr[n] = ptr[ii];\n ptr[ii] = v15;\n }\n }\n }\n v14 = ptr[1];\n free(ptr);\n return v14;\n}", + "ida_pseudo_norm": "double func0(long long a1, int a2) {\n int v3;\n int v4;\n int i;\n int j;\n int v7;\n int k;\n int v9;\n int m;\n int n;\n int ii;\n double *ptr;\n double v14;\n double v15;\n if (a2 <= 1) return -9999999.0;\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if (*(double *)(8LL * j + a1) == *(double *)(8LL * i + a1)) {\n ++v4;\n break;\n }\n }\n }\n if (a2 == 2 && v4 == 1) return -9999999.0;\n ptr = (double *)malloc(8LL * a2);\n v7 = 0;\n for (k = 0; k < a2; ++k) {\n v9 = 0;\n for (m = 0; m < v7; ++m) {\n if (ptr[m] == *(double *)(8LL * k + a1)) {\n v9 = 1;\n break;\n }\n }\n if (!v9) {\n v3 = v7++;\n ptr[v3] = *(double *)(8LL * k + a1);\n }\n }\n for (n = 0; n < v7; ++n) {\n for (ii = n + 1; ii < v7; ++ii) {\n if (ptr[n] > ptr[ii]) {\n v15 = ptr[n];\n ptr[n] = ptr[ii];\n ptr[ii] = v15;\n }\n }\n }\n v14 = ptr[1];\n free(ptr);\n return v14;\n}" + }, + { + "index": 755, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "double func0(double* numbers, int length) {\n if (length < 2) {\n return -9999999;\n }\n int count = 0;\n for (int i = 0; i < length; i++) {\n for (int j = i + 1; j < length; j++) {\n if (numbers[j] == numbers[i]) {\n count += 1;\n break;\n }\n }\n }\n if (length == 2 && count == 1) {\n return -9999999;\n }\n double* uniq_items = malloc(length * sizeof(double));\n int uniq_length = 0;\n for (int i = 0; i < length; i++) {\n int found = 0;\n for (int j = 0; j < uniq_length; j++) {\n if (uniq_items[j] == numbers[i]) {\n found = 1;\n break;\n }\n }\n if (!found) {\n uniq_items[uniq_length++] = numbers[i];\n }\n }\n for (int i = 0; i < uniq_length; i++) {\n for (int j = i + 1; j < uniq_length; j++) {\n if (uniq_items[i] > uniq_items[j]) {\n double temp = uniq_items[i];\n uniq_items[i] = uniq_items[j];\n uniq_items[j] = temp;\n }\n }\n }\n double result = uniq_items[1];\n free(uniq_items);\n return result;\n}", + "test": "int main() {\n\n double arr1[] = {1, 2, -8, -2, 0, -2};\n\n double arr2[] = {1, 1, -0.5, 0, 2, -2, -2};\n\n double arr3[] = {2, 2};\n\n\n\n assert(func0(arr1, 6) == -2);\n\n assert(func0(arr2, 7) == -0.5);\n\n assert(func0(arr3, 2) == -9999999); // representing None\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\ncmp $0x1,%esi\njle 1286 \nmov %rdi,%rbx\nmov %esi,%ebp\nmov $0x0,%esi\nmov $0x0,%r8d\nmov $0x1,%edi\nmov $0x1,%eax\njmp 11eb \njne 11fd \nadd $0x1,%r8d\nlea 0x1(%rdi),%eax\ncmp %eax,%ebp\njle 12d3 \nmov %edi,%esi\nmov %eax,%edi\nmovslq %eax,%rcx\nmovslq %esi,%rdx\nmovsd (%rbx,%rcx,8),%xmm0\nucomisd (%rbx,%rdx,8),%xmm0\njnp 11d6 \nadd $0x1,%eax\ncmp %eax,%ebp\njg 11eb \njmp 11dc \nje 129f \njmpq 12c8 \ntest %ecx,%ecx\njle 1270 \nlea 0x8(%r8),%rdx\nlea -0x1(%rcx),%esi\nmov %esi,%r9d\nadd $0x1,%r9\nmov $0x1,%edi\nlea 0x10(%r8),%r10\njmp 1259 \nadd $0x8,%rax\ncmp %rcx,%rax\nje 1251 \nmovsd -0x8(%rdx),%xmm0\nmovsd (%rax),%xmm1\ncomisd %xmm1,%xmm0\njbe 122e \nmovsd %xmm1,-0x8(%rdx)\nmovsd %xmm0,(%rax)\njmp 122e \nadd $0x1,%rdi\nadd $0x8,%rdx\ncmp %r9,%rdi\nje 1270 \nmov %esi,%eax\nsub %edi,%eax\nlea -0x1(%rdi,%rax,1),%rax\nlea (%r10,%rax,8),%rcx\nmov %rdx,%rax\njmp 1237 \nmov 0x8(%r8),%r12\nmov %r8,%rdi\ncallq 1080 \nmovq %r12,%xmm0\npop %rbx\npop %rbp\npop %r12\nretq\nmov 0xe03(%rip),%r12\njmp 127c \nmovslq %ecx,%rax\nmovsd (%rsi),%xmm0\nmovsd %xmm0,(%r8,%rax,8)\nlea 0x1(%rcx),%ecx\nadd $0x8,%rsi\ncmp %rdi,%rsi\nje 1211 \ntest %ecx,%ecx\njle 128f \nmovsd (%rsi),%xmm0\nmov %r8,%rax\nlea -0x1(%rcx),%edx\nlea (%r9,%rdx,8),%rdx\nucomisd (%rax),%xmm0\njnp 1206 \nadd $0x8,%rax\ncmp %rdx,%rax\njne 12be \njmp 128f \ncmp $0x2,%ebp\njne 12e5 \nmov 0xdb1(%rip),%r12\ncmp $0x1,%r8d\nje 127c \nmovslq %ebp,%rdi\nshl $0x3,%rdi\ncallq 10b0 \nmov %rax,%r8\nmov %rbx,%rsi\nlea -0x1(%rbp),%eax\nlea 0x8(%rbx,%rax,8),%rdi\nmov $0x0,%ecx\nlea 0x8(%r8),%r9\njmp 12ac \n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\ncmp esi, 1\njle loc_12F5\nmov rbx, rdi\nmov r8d, esi\nmovsxd rcx, esi\nmov edx, 1\nmov edi, 0\njmp short loc_11E0\nloc_11D1:\nadd edi, 1\nloc_11D4:\nlea rax, [rdx+1]\ncmp rdx, rcx\njz short loc_1201\nmov rdx, rax\nloc_11E0:\ncmp rdx, r8\njz short loc_1201\nmovsd xmm0, qword ptr [rbx+rdx*8-8]\nmov rax, rdx\nloc_11EE:\nucomisd xmm0, qword ptr [rbx+rax*8]\njp short loc_11F7\njz short loc_11D1\nloc_11F7:\nadd rax, 1\ncmp esi, eax\njg short loc_11EE\njmp short loc_11D4\nloc_1201:\ncmp esi, 2\njnz short loc_121E\nmov rbp, cs:qword_2078\ncmp edi, 1\njnz short loc_121E\nloc_1212:\nmovq xmm0, rbp\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_121E:\nlea rbp, ds:0[rcx*8]\nmov rdi, rbp; size\ncall _malloc\nmov r8, rax\nmov rsi, rbx\nadd rbx, rbp\nmov ecx, 0\njmp short loc_1257\nloc_123E:\nmovsxd rax, ecx\nmovsd xmm0, qword ptr [rsi]\nmovsd qword ptr [r8+rax*8], xmm0\nlea ecx, [rcx+1]\nloc_124E:\nadd rsi, 8\ncmp rsi, rbx\njz short loc_127C\nloc_1257:\ntest ecx, ecx\njle short loc_123E\nmovsd xmm0, qword ptr [rsi]\nmov rax, r8\nmovsxd rdx, ecx\nlea rdx, [r8+rdx*8]\nloc_1269:\nucomisd xmm0, qword ptr [rax]\njp short loc_1271\njz short loc_124E\nloc_1271:\nadd rax, 8\ncmp rax, rdx\njnz short loc_1269\njmp short loc_123E\nloc_127C:\ntest ecx, ecx\njle short loc_12E4\nlea rdx, [r8+8]\nlea r11d, [rcx-1]\nmov r9d, ecx\nmovsxd rdi, ecx\nmov esi, 1\nlea r10, [r8+10h]\njmp short loc_12CC\nloc_1299:\nadd rax, 8\ncmp rax, rcx\njz short loc_12BC\nloc_12A2:\nmovsd xmm0, qword ptr [rdx-8]\nmovsd xmm1, qword ptr [rax]\ncomisd xmm0, xmm1\njbe short loc_1299\nmovsd qword ptr [rdx-8], xmm1\nmovsd qword ptr [rax], xmm0\njmp short loc_1299\nloc_12BC:\nlea rax, [rsi+1]\nadd rdx, 8\ncmp rsi, rdi\njz short loc_12E4\nmov rsi, rax\nloc_12CC:\ncmp rsi, r9\njz short loc_12E4\nmov eax, r11d\nsub eax, esi\nlea rax, [rsi+rax-1]\nlea rcx, [r10+rax*8]\nmov rax, rdx\njmp short loc_12A2\nloc_12E4:\nmov rbp, [r8+8]\nmov rdi, r8; ptr\ncall _free\njmp loc_1212\nloc_12F5:\nmov rbp, cs:qword_2078\njmp loc_1212", + "ida_pseudo": "double __fastcall func0(double *a1, int a2)\n{\n __int64 v3; // rdx\n int v4; // edi\n __int64 v5; // rax\n double v6; // rbp\n size_t v8; // rbp\n double *v9; // r8\n double *v10; // rsi\n double *v11; // rbx\n int v12; // ecx\n double *v13; // rax\n double *v14; // rdx\n __int64 i; // rsi\n double *v16; // rax\n double v17; // xmm0_8\n\n if ( a2 <= 1 )\n return -9999999.0;\n v3 = 1LL;\n v4 = 0;\n while ( v3 != a2 )\n {\n v5 = v3;\n while ( a1[v3 - 1] != a1[v5] )\n {\n if ( a2 <= (int)++v5 )\n goto LABEL_4;\n }\n ++v4;\nLABEL_4:\n if ( v3 == a2 )\n break;\n ++v3;\n }\n if ( a2 != 2 || (v6 = -9999999.0, v4 != 1) )\n {\n v8 = a2;\n v9 = (double *)malloc(v8 * 8);\n v10 = a1;\n v11 = &a1[v8];\n v12 = 0;\n do\n {\n if ( v12 <= 0 )\n {\nLABEL_15:\n v9[v12++] = *v10;\n }\n else\n {\n v13 = v9;\n while ( *v10 != *v13 )\n {\n if ( ++v13 == &v9[v12] )\n goto LABEL_15;\n }\n }\n ++v10;\n }\n while ( v10 != v11 );\n if ( v12 > 0 )\n {\n v14 = v9 + 1;\n for ( i = 1LL; i != v12; ++i )\n {\n v16 = v14;\n do\n {\n v17 = *(v14 - 1);\n if ( v17 > *v16 )\n {\n *(v14 - 1) = *v16;\n *v16 = v17;\n }\n ++v16;\n }\n while ( v16 != &v9[i + 1 + (unsigned int)(v12 - 1 - i)] );\n ++v14;\n if ( i == v12 )\n break;\n }\n }\n v6 = v9[1];\n free(v9);\n }\n return v6;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\ncmp esi, 1\njle loc_12F5\nmov rbx, rdi\nmov r8d, esi\nmovsxd rcx, esi\nmov edx, 1\nmov edi, 0\njmp short loc_11E0\nloc_11D1:\nadd edi, 1\nloc_11D4:\nlea rax, [rdx+1]\ncmp rdx, rcx\njz short loc_1201\nmov rdx, rax\nloc_11E0:\ncmp rdx, r8\njz short loc_1201\nmovsd xmm0, qword ptr [rbx+rdx*8-8]\nmov rax, rdx\nloc_11EE:\nucomisd xmm0, qword ptr [rbx+rax*8]\njp short loc_11F7\njz short loc_11D1\nloc_11F7:\nadd rax, 1\ncmp esi, eax\njg short loc_11EE\njmp short loc_11D4\nloc_1201:\ncmp esi, 2\njnz short loc_121E\nmov rbp, cs:qword_2078\ncmp edi, 1\njnz short loc_121E\nloc_1212:\nmovq xmm0, rbp\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_121E:\nlea rbp, ds:0[rcx*8]\nmov rdi, rbp; size\ncall _malloc\nmov r8, rax\nmov rsi, rbx\nadd rbx, rbp\nmov ecx, 0\njmp short loc_1257\nloc_123E:\nmovsxd rax, ecx\nmovsd xmm0, qword ptr [rsi]\nmovsd qword ptr [r8+rax*8], xmm0\nlea ecx, [rcx+1]\nloc_124E:\nadd rsi, 8\ncmp rsi, rbx\njz short loc_127C\nloc_1257:\ntest ecx, ecx\njle short loc_123E\nmovsd xmm0, qword ptr [rsi]\nmov rax, r8\nmovsxd rdx, ecx\nlea rdx, [r8+rdx*8]\nloc_1269:\nucomisd xmm0, qword ptr [rax]\njp short loc_1271\njz short loc_124E\nloc_1271:\nadd rax, 8\ncmp rax, rdx\njnz short loc_1269\njmp short loc_123E\nloc_127C:\ntest ecx, ecx\njle short loc_12E4\nlea rdx, [r8+8]\nlea r11d, [rcx-1]\nmov r9d, ecx\nmovsxd rdi, ecx\nmov esi, 1\nlea r10, [r8+10h]\njmp short loc_12CC\nloc_1299:\nadd rax, 8\ncmp rax, rcx\njz short loc_12BC\nloc_12A2:\nmovsd xmm0, qword ptr [rdx-8]\nmovsd xmm1, qword ptr [rax]\ncomisd xmm0, xmm1\njbe short loc_1299\nmovsd qword ptr [rdx-8], xmm1\nmovsd qword ptr [rax], xmm0\njmp short loc_1299\nloc_12BC:\nlea rax, [rsi+1]\nadd rdx, 8\ncmp rsi, rdi\njz short loc_12E4\nmov rsi, rax\nloc_12CC:\ncmp rsi, r9\njz short loc_12E4\nmov eax, r11d\nsub eax, esi\nlea rax, [rsi+rax-1]\nlea rcx, [r10+rax*8]\nmov rax, rdx\njmp short loc_12A2\nloc_12E4:\nmov rbp, [r8+8]\nmov rdi, r8; ptr\ncall _free\njmp loc_1212\nloc_12F5:\nmov rbp, cs:qword_2078\njmp loc_1212", + "ida_strip_pseudo": "double __fastcall sub_11A9(double *a1, int a2)\n{\n __int64 v3; // rdx\n int v4; // edi\n __int64 v5; // rax\n double v6; // rbp\n size_t v8; // rbp\n double *v9; // r8\n double *v10; // rsi\n double *v11; // rbx\n int v12; // ecx\n double *v13; // rax\n double *v14; // rdx\n __int64 i; // rsi\n double *v16; // rax\n double v17; // xmm0_8\n\n if ( a2 <= 1 )\n return -9999999.0;\n v3 = 1LL;\n v4 = 0;\n while ( v3 != a2 )\n {\n v5 = v3;\n while ( a1[v3 - 1] != a1[v5] )\n {\n if ( a2 <= (int)++v5 )\n goto LABEL_4;\n }\n ++v4;\nLABEL_4:\n if ( v3 == a2 )\n break;\n ++v3;\n }\n if ( a2 != 2 || (v6 = -9999999.0, v4 != 1) )\n {\n v8 = a2;\n v9 = (double *)malloc(v8 * 8);\n v10 = a1;\n v11 = &a1[v8];\n v12 = 0;\n do\n {\n if ( v12 <= 0 )\n {\nLABEL_15:\n v9[v12++] = *v10;\n }\n else\n {\n v13 = v9;\n while ( *v10 != *v13 )\n {\n if ( ++v13 == &v9[v12] )\n goto LABEL_15;\n }\n }\n ++v10;\n }\n while ( v10 != v11 );\n if ( v12 > 0 )\n {\n v14 = v9 + 1;\n for ( i = 1LL; i != v12; ++i )\n {\n v16 = v14;\n do\n {\n v17 = *(v14 - 1);\n if ( v17 > *v16 )\n {\n *(v14 - 1) = *v16;\n *v16 = v17;\n }\n ++v16;\n }\n while ( v16 != &v9[i + 1 + (unsigned int)(v12 - 1 - i)] );\n ++v14;\n if ( i == v12 )\n break;\n }\n }\n v6 = v9[1];\n free(v9);\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_11A9(double *a1, int a2) {\n long long v3;\n int v4;\n long long v5;\n double v6;\n unsigned int v8;\n double *v9;\n double *v10;\n double *v11;\n int v12;\n double *v13;\n double *v14;\n long long i;\n double *v16;\n double v17;\n if (a2 <= 1) return -9999999.0;\n v3 = 1LL;\n v4 = 0;\n while (v3 != a2) {\n v5 = v3;\n while (a1[v3 - 1] != a1[v5]) {\n if (a2 <= (int)++v5) goto LABEL_4;\n }\n ++v4;\n LABEL_4:\n if (v3 == a2) break;\n ++v3;\n }\n if (a2 != 2 || (v6 = -9999999.0, v4 != 1)) {\n v8 = a2;\n v9 = (double *)malloc(v8 * 8);\n v10 = a1;\n v11 = &a1[v8];\n v12 = 0;\n do {\n if (v12 <= 0) {\n LABEL_15:\n v9[v12++] = *v10;\n } else {\n v13 = v9;\n while (*v10 != *v13) {\n if (++v13 == &v9[v12]) goto LABEL_15;\n }\n }\n ++v10;\n } while (v10 != v11);\n if (v12 > 0) {\n v14 = v9 + 1;\n for (i = 1LL; i != v12; ++i) {\n v16 = v14;\n do {\n v17 = *(v14 - 1);\n if (v17 > *v16) {\n *(v14 - 1) = *v16;\n *v16 = v17;\n }\n ++v16;\n } while (v16 != &v9[i + 1 + (unsigned int)(v12 - 1 - i)]);\n ++v14;\n if (i == v12) break;\n }\n }\n v6 = v9[1];\n free(v9);\n }\n return v6;\n}", + "ida_pseudo_norm": "double func0(double *a1, int a2) {\n long long v3;\n int v4;\n long long v5;\n double v6;\n unsigned int v8;\n double *v9;\n double *v10;\n double *v11;\n int v12;\n double *v13;\n double *v14;\n long long i;\n double *v16;\n double v17;\n if (a2 <= 1) return -9999999.0;\n v3 = 1LL;\n v4 = 0;\n while (v3 != a2) {\n v5 = v3;\n while (a1[v3 - 1] != a1[v5]) {\n if (a2 <= (int)++v5) goto LABEL_4;\n }\n ++v4;\n LABEL_4:\n if (v3 == a2) break;\n ++v3;\n }\n if (a2 != 2 || (v6 = -9999999.0, v4 != 1)) {\n v8 = a2;\n v9 = (double *)malloc(v8 * 8);\n v10 = a1;\n v11 = &a1[v8];\n v12 = 0;\n do {\n if (v12 <= 0) {\n LABEL_15:\n v9[v12++] = *v10;\n } else {\n v13 = v9;\n while (*v10 != *v13) {\n if (++v13 == &v9[v12]) goto LABEL_15;\n }\n }\n ++v10;\n } while (v10 != v11);\n if (v12 > 0) {\n v14 = v9 + 1;\n for (i = 1LL; i != v12; ++i) {\n v16 = v14;\n do {\n v17 = *(v14 - 1);\n if (v17 > *v16) {\n *(v14 - 1) = *v16;\n *v16 = v17;\n }\n ++v16;\n } while (v16 != &v9[i + 1 + (unsigned int)(v12 - 1 - i)]);\n ++v14;\n if (i == v12) break;\n }\n }\n v6 = v9[1];\n free(v9);\n }\n return v6;\n}" + }, + { + "index": 755, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "double func0(double* numbers, int length) {\n if (length < 2) {\n return -9999999;\n }\n int count = 0;\n for (int i = 0; i < length; i++) {\n for (int j = i + 1; j < length; j++) {\n if (numbers[j] == numbers[i]) {\n count += 1;\n break;\n }\n }\n }\n if (length == 2 && count == 1) {\n return -9999999;\n }\n double* uniq_items = malloc(length * sizeof(double));\n int uniq_length = 0;\n for (int i = 0; i < length; i++) {\n int found = 0;\n for (int j = 0; j < uniq_length; j++) {\n if (uniq_items[j] == numbers[i]) {\n found = 1;\n break;\n }\n }\n if (!found) {\n uniq_items[uniq_length++] = numbers[i];\n }\n }\n for (int i = 0; i < uniq_length; i++) {\n for (int j = i + 1; j < uniq_length; j++) {\n if (uniq_items[i] > uniq_items[j]) {\n double temp = uniq_items[i];\n uniq_items[i] = uniq_items[j];\n uniq_items[j] = temp;\n }\n }\n }\n double result = uniq_items[1];\n free(uniq_items);\n return result;\n}", + "test": "int main() {\n\n double arr1[] = {1, 2, -8, -2, 0, -2};\n\n double arr2[] = {1, 1, -0.5, 0, 2, -2, -2};\n\n double arr3[] = {2, 2};\n\n\n\n assert(func0(arr1, 6) == -2);\n\n assert(func0(arr2, 7) == -0.5);\n\n assert(func0(arr3, 2) == -9999999); // representing None\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%esi\njle 1491 \npush %rbp\nmov $0x1,%ecx\nmov %esi,%ebp\nmov $0x1,%eax\npush %rbx\nxor %esi,%esi\nmov %rdi,%rbx\nsub $0x18,%rsp\nmovsd (%rdi),%xmm0\njmp 1367 \nnopw 0x0(%rax,%rax,1)\nadd $0x1,%eax\ncmp %eax,%ebp\njle 1376 \nmovslq %eax,%rdx\nucomisd (%rbx,%rdx,8),%xmm0\njp 1360 \njne 1360 \nadd $0x1,%esi\nlea 0x1(%rcx),%eax\ncmp %eax,%ebp\njle 1387 \nmovsd (%rbx,%rcx,8),%xmm0\nmovslq %eax,%rcx\njmp 1367 \ncmp $0x2,%ebp\njne 13a0 \nmovsd 0xcfc(%rip),%xmm0\ncmp $0x1,%esi\njne 13a0 \nadd $0x18,%rsp\npop %rbx\npop %rbp\nretq\nmovslq %ebp,%rdi\nshl $0x3,%rdi\ncallq 10b0 \nxor %esi,%esi\nmov %rax,%r8\nlea -0x1(%rbp),%eax\nlea 0x8(%rbx,%rax,8),%rdi\nlea 0x8(%r8),%rdx\nnopl (%rax)\nmovsd (%rbx),%xmm0\ntest %esi,%esi\nje 1480 \nlea -0x1(%rsi),%ecx\nmov %r8,%rax\nlea (%rdx,%rcx,8),%rcx\njmp 13ed \nnopl 0x0(%rax,%rax,1)\nadd $0x8,%rax\ncmp %rax,%rcx\nje 1480 \nucomisd (%rax),%xmm0\njp 13e0 \njne 13e0 \nadd $0x8,%rbx\ncmp %rdi,%rbx\njne 13c0 \nlea -0x1(%rsi),%r9d\nmov $0x1,%edi\nlea 0x10(%r8),%r10\nmov %r9,%rsi\nadd $0x1,%r9\ncmp %rdi,%r9\nje 145e \nnopw 0x0(%rax,%rax,1)\nmov %esi,%eax\nsub %edi,%eax\nlea -0x1(%rdi,%rax,1),%rax\nlea (%r10,%rax,8),%rcx\nmov %rdx,%rax\nmovsd -0x8(%rdx),%xmm0\nmovsd (%rax),%xmm1\ncomisd %xmm1,%xmm0\njbe 1448 \nmovsd %xmm1,-0x8(%rdx)\nmovsd %xmm0,(%rax)\nadd $0x8,%rax\ncmp %rax,%rcx\njne 1430 \nadd $0x1,%rdi\nadd $0x8,%rdx\ncmp %rdi,%r9\njne 1420 \nmovsd 0x8(%r8),%xmm0\nmov %r8,%rdi\nmovsd %xmm0,0x8(%rsp)\ncallq 1080 \nmovsd 0x8(%rsp),%xmm0\nadd $0x18,%rsp\npop %rbx\npop %rbp\nretq\nmovslq %esi,%rax\nadd $0x1,%esi\nmovsd %xmm0,(%r8,%rax,8)\njmpq 13f5 \nmovsd 0xbf7(%rip),%xmm0\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0_part_0:\npush rbp\npush rbx\nsub rsp, 18h\ntest esi, esi\njle loc_1452\nmov rbx, rdi\ncmp esi, 1\njz short loc_1376\nmov edi, esi\nmov edx, 1\nxor ecx, ecx\nnop\nloc_1330:\nmovsd xmm0, qword ptr [rbx+rdx*8-8]\nmov rax, rdx\njmp short loc_1348\nloc_1340:\nadd rax, 1\ncmp esi, eax\njle short loc_1354\nloc_1348:\nucomisd xmm0, qword ptr [rbx+rax*8]\njp short loc_1340\njnz short loc_1340\nadd ecx, 1\nloc_1354:\nadd rdx, 1\ncmp rdx, rdi\njnz short loc_1330\ncmp esi, 2\njnz short loc_1376\nmovsd xmm0, cs:qword_2078\ncmp ecx, 1\njnz short loc_1376\nadd rsp, 18h\npop rbx\npop rbp\nretn\nloc_1376:\nmovsxd rdx, esi\nlea rbp, ds:0[rdx*8]\nmov rdi, rbp; size\ncall _malloc\nlea rdx, [rbx+rbp]\nxor ecx, ecx\nmov rdi, rax; ptr\nnop word ptr [rax+rax+00h]\nloc_1398:\nmovsxd r8, ecx\nmovsd xmm0, qword ptr [rbx]\nlea rsi, [rdi+r8*8]\ntest ecx, ecx\njle short loc_13D0\nloc_13A7:\nmov rax, rdi\njmp short loc_13B9\nloc_13B0:\nadd rax, 8\ncmp rax, rsi\njz short loc_13D0\nloc_13B9:\nucomisd xmm0, qword ptr [rax]\njp short loc_13B0\njnz short loc_13B0\nadd rbx, 8\ncmp rbx, rdx\njz short loc_13E2\nmovsd xmm0, qword ptr [rbx]\njmp short loc_13A7\nloc_13D0:\nadd rbx, 8\nadd ecx, 1\nmovsd qword ptr [rdi+r8*8], xmm0\ncmp rbx, rdx\njnz short loc_1398\nloc_13E2:\ntest ecx, ecx\njle short loc_1435\nmov rdx, rdi\nmov r8d, ecx\nmov esi, 1\ncmp ecx, 1\njz short loc_1435\nnop word ptr [rax+rax+00000000h]\nloc_1400:\nmov rax, rsi\nnop dword ptr [rax+rax+00h]\nloc_1408:\nmovsd xmm0, qword ptr [rdx]\nmovsd xmm1, qword ptr [rdi+rax*8]\ncomisd xmm0, xmm1\njbe short loc_1420\nmovsd qword ptr [rdx], xmm1\nmovsd qword ptr [rdi+rax*8], xmm0\nloc_1420:\nadd rax, 1\ncmp ecx, eax\njg short loc_1408\nadd rsi, 1\nadd rdx, 8\ncmp r8, rsi\njnz short loc_1400\nloc_1435:\nmovsd xmm0, qword ptr [rdi+8]\nmovsd [rsp+28h+var_20], xmm0\ncall _free\nmovsd xmm0, [rsp+28h+var_20]\nadd rsp, 18h\npop rbx\npop rbp\nretn\nloc_1452:\nmovsxd rsi, esi\nlea rdi, ds:0[rsi*8]; size\ncall _malloc\nmov rdi, rax\njmp short loc_1435", + "ida_pseudo": "double __fastcall func0_part_0(double *a1, int a2)\n{\n double *v2; // rbx\n __int64 v3; // rdx\n int v4; // ecx\n __int64 v5; // rax\n double result; // xmm0_8\n double *v7; // rax\n double *v8; // rdx\n int v9; // ecx\n double *v10; // rdi\n __int64 v11; // r8\n double v12; // xmm0_8\n double *v13; // rax\n double *v14; // rdx\n __int64 v15; // rsi\n __int64 v16; // rax\n double v17; // xmm0_8\n double v18; // xmm1_8\n double v19; // [rsp+8h] [rbp-20h]\n\n if ( a2 <= 0 )\n {\n v10 = (double *)malloc(8LL * a2);\nLABEL_26:\n v19 = v10[1];\n free(v10);\n return v19;\n }\n v2 = a1;\n if ( a2 == 1 )\n goto LABEL_11;\n v3 = 1LL;\n v4 = 0;\n do\n {\n v5 = v3;\n while ( a1[v3 - 1] != a1[v5] )\n {\n if ( a2 <= (int)++v5 )\n goto LABEL_8;\n }\n ++v4;\nLABEL_8:\n ++v3;\n }\n while ( v3 != a2 );\n if ( a2 != 2 || (result = -9999999.0, v4 != 1) )\n {\nLABEL_11:\n v7 = (double *)malloc(8LL * a2);\n v8 = &a1[a2];\n v9 = 0;\n v10 = v7;\n while ( 1 )\n {\n v11 = v9;\n v12 = *v2;\n if ( v9 > 0 )\n break;\nLABEL_18:\n ++v2;\n ++v9;\n v10[v11] = v12;\n if ( v2 == v8 )\n goto LABEL_19;\n }\n while ( 1 )\n {\n v13 = v10;\n while ( v12 != *v13 )\n {\n if ( ++v13 == &v10[v9] )\n goto LABEL_18;\n }\n if ( ++v2 == v8 )\n break;\n v12 = *v2;\n }\nLABEL_19:\n if ( v9 > 0 )\n {\n v14 = v10;\n v15 = 1LL;\n if ( v9 != 1 )\n {\n do\n {\n v16 = v15;\n do\n {\n v17 = *v14;\n v18 = v10[v16];\n if ( *v14 > v18 )\n {\n *v14 = v18;\n v10[v16] = v17;\n }\n ++v16;\n }\n while ( v9 > (int)v16 );\n ++v15;\n ++v14;\n }\n while ( v9 != v15 );\n }\n }\n goto LABEL_26;\n }\n return result;\n}", + "ida_strip_asm": "sub_1310:\npush rbp\npush rbx\nsub rsp, 18h\ntest esi, esi\njle loc_1452\nmov rbx, rdi\ncmp esi, 1\njz short loc_1376\nmov edi, esi\nmov edx, 1\nxor ecx, ecx\nnop\nloc_1330:\nmovsd xmm0, qword ptr [rbx+rdx*8-8]\nmov rax, rdx\njmp short loc_1348\nloc_1340:\nadd rax, 1\ncmp esi, eax\njle short loc_1354\nloc_1348:\nucomisd xmm0, qword ptr [rbx+rax*8]\njp short loc_1340\njnz short loc_1340\nadd ecx, 1\nloc_1354:\nadd rdx, 1\ncmp rdx, rdi\njnz short loc_1330\ncmp esi, 2\njnz short loc_1376\nmovsd xmm0, cs:qword_2078\ncmp ecx, 1\njnz short loc_1376\nadd rsp, 18h\npop rbx\npop rbp\nretn\nloc_1376:\nmovsxd rdx, esi\nlea rbp, ds:0[rdx*8]\nmov rdi, rbp; size\ncall _malloc\nlea rdx, [rbx+rbp]\nxor ecx, ecx\nmov rdi, rax; ptr\nnop word ptr [rax+rax+00h]\nloc_1398:\nmovsxd r8, ecx\nmovsd xmm0, qword ptr [rbx]\nlea rsi, [rdi+r8*8]\ntest ecx, ecx\njle short loc_13D0\nloc_13A7:\nmov rax, rdi\njmp short loc_13B9\nloc_13B0:\nadd rax, 8\ncmp rax, rsi\njz short loc_13D0\nloc_13B9:\nucomisd xmm0, qword ptr [rax]\njp short loc_13B0\njnz short loc_13B0\nadd rbx, 8\ncmp rbx, rdx\njz short loc_13E2\nmovsd xmm0, qword ptr [rbx]\njmp short loc_13A7\nloc_13D0:\nadd rbx, 8\nadd ecx, 1\nmovsd qword ptr [rdi+r8*8], xmm0\ncmp rbx, rdx\njnz short loc_1398\nloc_13E2:\ntest ecx, ecx\njle short loc_1435\nmov rdx, rdi\nmov r8d, ecx\nmov esi, 1\ncmp ecx, 1\njz short loc_1435\nnop word ptr [rax+rax+00000000h]\nloc_1400:\nmov rax, rsi\nnop dword ptr [rax+rax+00h]\nloc_1408:\nmovsd xmm0, qword ptr [rdx]\nmovsd xmm1, qword ptr [rdi+rax*8]\ncomisd xmm0, xmm1\njbe short loc_1420\nmovsd qword ptr [rdx], xmm1\nmovsd qword ptr [rdi+rax*8], xmm0\nloc_1420:\nadd rax, 1\ncmp ecx, eax\njg short loc_1408\nadd rsi, 1\nadd rdx, 8\ncmp r8, rsi\njnz short loc_1400\nloc_1435:\nmovsd xmm0, qword ptr [rdi+8]\nmovsd [rsp+28h+var_20], xmm0\ncall _free\nmovsd xmm0, [rsp+28h+var_20]\nadd rsp, 18h\npop rbx\npop rbp\nretn\nloc_1452:\nmovsxd rsi, esi\nlea rdi, ds:0[rsi*8]; size\ncall _malloc\nmov rdi, rax\njmp short loc_1435", + "ida_strip_pseudo": "double __fastcall sub_1310(double *a1, int a2)\n{\n double *v2; // rbx\n __int64 v3; // rdx\n int v4; // ecx\n __int64 v5; // rax\n double result; // xmm0_8\n double *v7; // rax\n double *v8; // rdx\n int v9; // ecx\n double *v10; // rdi\n __int64 v11; // r8\n double v12; // xmm0_8\n double *v13; // rax\n double *v14; // rdx\n __int64 v15; // rsi\n __int64 v16; // rax\n double v17; // xmm0_8\n double v18; // xmm1_8\n double v19; // [rsp+8h] [rbp-20h]\n\n if ( a2 <= 0 )\n {\n v10 = (double *)malloc(8LL * a2);\nLABEL_26:\n v19 = v10[1];\n free(v10);\n return v19;\n }\n v2 = a1;\n if ( a2 == 1 )\n goto LABEL_11;\n v3 = 1LL;\n v4 = 0;\n do\n {\n v5 = v3;\n while ( a1[v3 - 1] != a1[v5] )\n {\n if ( a2 <= (int)++v5 )\n goto LABEL_8;\n }\n ++v4;\nLABEL_8:\n ++v3;\n }\n while ( v3 != a2 );\n if ( a2 != 2 || (result = -9999999.0, v4 != 1) )\n {\nLABEL_11:\n v7 = (double *)malloc(8LL * a2);\n v8 = &a1[a2];\n v9 = 0;\n v10 = v7;\n while ( 1 )\n {\n v11 = v9;\n v12 = *v2;\n if ( v9 > 0 )\n break;\nLABEL_18:\n ++v2;\n ++v9;\n v10[v11] = v12;\n if ( v2 == v8 )\n goto LABEL_19;\n }\n while ( 1 )\n {\n v13 = v10;\n while ( v12 != *v13 )\n {\n if ( ++v13 == &v10[v9] )\n goto LABEL_18;\n }\n if ( ++v2 == v8 )\n break;\n v12 = *v2;\n }\nLABEL_19:\n if ( v9 > 0 )\n {\n v14 = v10;\n v15 = 1LL;\n if ( v9 != 1 )\n {\n do\n {\n v16 = v15;\n do\n {\n v17 = *v14;\n v18 = v10[v16];\n if ( *v14 > v18 )\n {\n *v14 = v18;\n v10[v16] = v17;\n }\n ++v16;\n }\n while ( v9 > (int)v16 );\n ++v15;\n ++v14;\n }\n while ( v9 != v15 );\n }\n }\n goto LABEL_26;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1310(double *a1, int a2) {\n double *v2;\n long long v3;\n int v4;\n long long v5;\n double result;\n double *v7;\n double *v8;\n int v9;\n double *v10;\n long long v11;\n double v12;\n double *v13;\n double *v14;\n long long v15;\n long long v16;\n double v17;\n double v18;\n double v19;\n if (a2 <= 0) {\n v10 = (double *)malloc(8LL * a2);\n LABEL_26:\n v19 = v10[1];\n free(v10);\n return v19;\n }\n v2 = a1;\n if (a2 == 1) goto LABEL_11;\n v3 = 1LL;\n v4 = 0;\n do {\n v5 = v3;\n while (a1[v3 - 1] != a1[v5]) {\n if (a2 <= (int)++v5) goto LABEL_8;\n }\n ++v4;\n LABEL_8:\n ++v3;\n } while (v3 != a2);\n if (a2 != 2 || (result = -9999999.0, v4 != 1)) {\n LABEL_11:\n v7 = (double *)malloc(8LL * a2);\n v8 = &a1[a2];\n v9 = 0;\n v10 = v7;\n while (1) {\n v11 = v9;\n v12 = *v2;\n if (v9 > 0) break;\n LABEL_18:\n ++v2;\n ++v9;\n v10[v11] = v12;\n if (v2 == v8) goto LABEL_19;\n }\n while (1) {\n v13 = v10;\n while (v12 != *v13) {\n if (++v13 == &v10[v9]) goto LABEL_18;\n }\n if (++v2 == v8) break;\n v12 = *v2;\n }\n LABEL_19:\n if (v9 > 0) {\n v14 = v10;\n v15 = 1LL;\n if (v9 != 1) {\n do {\n v16 = v15;\n do {\n v17 = *v14;\n v18 = v10[v16];\n if (*v14 > v18) {\n *v14 = v18;\n v10[v16] = v17;\n }\n ++v16;\n } while (v9 > (int)v16);\n ++v15;\n ++v14;\n } while (v9 != v15);\n }\n }\n goto LABEL_26;\n }\n return result;\n}", + "ida_pseudo_norm": "double func0_part_0(double *a1, int a2) {\n double *v2;\n long long v3;\n int v4;\n long long v5;\n double result;\n double *v7;\n double *v8;\n int v9;\n double *v10;\n long long v11;\n double v12;\n double *v13;\n double *v14;\n long long v15;\n long long v16;\n double v17;\n double v18;\n double v19;\n if (a2 <= 0) {\n v10 = (double *)malloc(8LL * a2);\n LABEL_26:\n v19 = v10[1];\n free(v10);\n return v19;\n }\n v2 = a1;\n if (a2 == 1) goto LABEL_11;\n v3 = 1LL;\n v4 = 0;\n do {\n v5 = v3;\n while (a1[v3 - 1] != a1[v5]) {\n if (a2 <= (int)++v5) goto LABEL_8;\n }\n ++v4;\n LABEL_8:\n ++v3;\n } while (v3 != a2);\n if (a2 != 2 || (result = -9999999.0, v4 != 1)) {\n LABEL_11:\n v7 = (double *)malloc(8LL * a2);\n v8 = &a1[a2];\n v9 = 0;\n v10 = v7;\n while (1) {\n v11 = v9;\n v12 = *v2;\n if (v9 > 0) break;\n LABEL_18:\n ++v2;\n ++v9;\n v10[v11] = v12;\n if (v2 == v8) goto LABEL_19;\n }\n while (1) {\n v13 = v10;\n while (v12 != *v13) {\n if (++v13 == &v10[v9]) goto LABEL_18;\n }\n if (++v2 == v8) break;\n v12 = *v2;\n }\n LABEL_19:\n if (v9 > 0) {\n v14 = v10;\n v15 = 1LL;\n if (v9 != 1) {\n do {\n v16 = v15;\n do {\n v17 = *v14;\n v18 = v10[v16];\n if (*v14 > v18) {\n *v14 = v18;\n v10[v16] = v17;\n }\n ++v16;\n } while (v9 > (int)v16);\n ++v15;\n ++v14;\n } while (v9 != v15);\n }\n }\n goto LABEL_26;\n }\n return result;\n}" + }, + { + "index": 755, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "double func0(double* numbers, int length) {\n if (length < 2) {\n return -9999999;\n }\n int count = 0;\n for (int i = 0; i < length; i++) {\n for (int j = i + 1; j < length; j++) {\n if (numbers[j] == numbers[i]) {\n count += 1;\n break;\n }\n }\n }\n if (length == 2 && count == 1) {\n return -9999999;\n }\n double* uniq_items = malloc(length * sizeof(double));\n int uniq_length = 0;\n for (int i = 0; i < length; i++) {\n int found = 0;\n for (int j = 0; j < uniq_length; j++) {\n if (uniq_items[j] == numbers[i]) {\n found = 1;\n break;\n }\n }\n if (!found) {\n uniq_items[uniq_length++] = numbers[i];\n }\n }\n for (int i = 0; i < uniq_length; i++) {\n for (int j = i + 1; j < uniq_length; j++) {\n if (uniq_items[i] > uniq_items[j]) {\n double temp = uniq_items[i];\n uniq_items[i] = uniq_items[j];\n uniq_items[j] = temp;\n }\n }\n }\n double result = uniq_items[1];\n free(uniq_items);\n return result;\n}", + "test": "int main() {\n\n double arr1[] = {1, 2, -8, -2, 0, -2};\n\n double arr2[] = {1, 1, -0.5, 0, 2, -2, -2};\n\n double arr3[] = {2, 2};\n\n\n\n assert(func0(arr1, 6) == -2);\n\n assert(func0(arr2, 7) == -0.5);\n\n assert(func0(arr3, 2) == -9999999); // representing None\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%esi\njle 1448 \npush %rbp\nmov $0x1,%ecx\nmov %esi,%ebp\nmov $0x1,%eax\npush %rbx\nxor %esi,%esi\nmov %rdi,%rbx\nsub $0x18,%rsp\nmovsd (%rdi),%xmm0\njmp 1337 \nnopw 0x0(%rax,%rax,1)\nadd $0x1,%eax\ncmp %eax,%ebp\njle 1346 \nmovslq %eax,%rdx\nucomisd (%rbx,%rdx,8),%xmm0\njp 1330 \njne 1330 \nadd $0x1,%esi\nlea 0x1(%rcx),%eax\ncmp %eax,%ebp\njle 1357 \nmovsd (%rbx,%rcx,8),%xmm0\nmovslq %eax,%rcx\njmp 1337 \ncmp $0x2,%ebp\njne 1370 \nmovsd 0xd2c(%rip),%xmm0\ncmp $0x1,%esi\njne 1370 \nadd $0x18,%rsp\npop %rbx\npop %rbp\nretq\nmovslq %ebp,%rdi\nshl $0x3,%rdi\ncallq 10b0 \nxor %ecx,%ecx\nmov %rax,%rdi\nlea -0x1(%rbp),%eax\nlea 0x8(%rbx,%rax,8),%rsi\nlea 0x8(%rdi),%r8\nnopl (%rax)\nmovsd (%rbx),%xmm0\ntest %ecx,%ecx\nje 1438 \nlea -0x1(%rcx),%edx\nmov %rdi,%rax\nlea (%r8,%rdx,8),%rdx\njmp 13b9 \nnopl 0x0(%rax,%rax,1)\nadd $0x8,%rax\ncmp %rax,%rdx\nje 1438 \nucomisd (%rax),%xmm0\njp 13b0 \njne 13b0 \nadd $0x8,%rbx\ncmp %rbx,%rsi\njne 1390 \ncmp $0x1,%ecx\njle 1415 \nlea -0x2(%rcx),%r8d\nmov %rdi,%rdx\nmov $0x1,%esi\nadd $0x2,%r8\nmov %rsi,%rax\nnopl 0x0(%rax,%rax,1)\nmovsd (%rdx),%xmm0\nmovsd (%rdi,%rax,8),%xmm1\ncomisd %xmm1,%xmm0\njbe 1400 \nmovsd %xmm1,(%rdx)\nmovsd %xmm0,(%rdi,%rax,8)\nadd $0x1,%rax\ncmp %eax,%ecx\njg 13e8 \nadd $0x1,%rsi\nadd $0x8,%rdx\ncmp %rsi,%r8\njne 13e0 \nmovsd 0x8(%rdi),%xmm0\nmovsd %xmm0,0x8(%rsp)\ncallq 1080 \nmovsd 0x8(%rsp),%xmm0\nadd $0x18,%rsp\npop %rbx\npop %rbp\nretq\nnopw 0x0(%rax,%rax,1)\nmovslq %ecx,%rax\nadd $0x1,%ecx\nmovsd %xmm0,(%rdi,%rax,8)\njmpq 13c1 \nmovsd 0xc40(%rip),%xmm0\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ncmp esi, 1\njle loc_1452\npush rbp\nmov edx, 1\nxor ecx, ecx\npush rbx\nmov rbx, rdi\nmov edi, esi\nsub rsp, 18h\nnop\nloc_1330:\nmovsd xmm0, qword ptr [rbx+rdx*8-8]\nmov rax, rdx\njmp short loc_1348\nloc_1340:\nadd rax, 1\ncmp esi, eax\njle short loc_1354\nloc_1348:\nucomisd xmm0, qword ptr [rbx+rax*8]\njp short loc_1340\njnz short loc_1340\nadd ecx, 1\nloc_1354:\nadd rdx, 1\ncmp rdx, rdi\njnz short loc_1330\ncmp esi, 2\njnz short loc_1376\nmovsd xmm0, cs:qword_2078\ncmp ecx, 1\njnz short loc_1376\nadd rsp, 18h\npop rbx\npop rbp\nretn\nloc_1376:\nmovsxd rdx, esi\nlea rbp, ds:0[rdx*8]\nmov rdi, rbp; size\ncall _malloc\nlea rdx, [rbx+rbp]\nxor ecx, ecx\nmov rdi, rax; ptr\nloc_1392:\nmovsxd r8, ecx\nmovsd xmm0, qword ptr [rbx]\nlea rsi, [rdi+r8*8]\ntest ecx, ecx\njle short loc_13D0\nloc_13A1:\nmov rax, rdi\njmp short loc_13B9\nloc_13B0:\nadd rax, 8\ncmp rsi, rax\njz short loc_13D0\nloc_13B9:\nucomisd xmm0, qword ptr [rax]\njp short loc_13B0\njnz short loc_13B0\nadd rbx, 8\ncmp rdx, rbx\njz short loc_13E2\nmovsd xmm0, qword ptr [rbx]\njmp short loc_13A1\nloc_13D0:\nadd rbx, 8\nadd ecx, 1\nmovsd qword ptr [rdi+r8*8], xmm0\ncmp rdx, rbx\njnz short loc_1392\nloc_13E2:\ntest ecx, ecx\njle short loc_1435\nmov rdx, rdi\nmov r8d, ecx\nmov esi, 1\ncmp ecx, 1\njz short loc_1435\nnop word ptr [rax+rax+00000000h]\nloc_1400:\nmov rax, rsi\nnop dword ptr [rax+rax+00h]\nloc_1408:\nmovsd xmm0, qword ptr [rdx]\nmovsd xmm1, qword ptr [rdi+rax*8]\ncomisd xmm0, xmm1\njbe short loc_1420\nmovsd qword ptr [rdx], xmm1\nmovsd qword ptr [rdi+rax*8], xmm0\nloc_1420:\nadd rax, 1\ncmp ecx, eax\njg short loc_1408\nadd rsi, 1\nadd rdx, 8\ncmp rsi, r8\njnz short loc_1400\nloc_1435:\nmovsd xmm0, qword ptr [rdi+8]\nmovsd [rsp+28h+var_20], xmm0\ncall _free\nmovsd xmm0, [rsp+28h+var_20]\nadd rsp, 18h\npop rbx\npop rbp\nretn\nloc_1452:\nmovsd xmm0, cs:qword_2078\nretn", + "ida_pseudo": "double __fastcall func0(double *a1, int a2)\n{\n __int64 v2; // rdx\n int v3; // ecx\n double *v4; // rbx\n __int64 v5; // rax\n double result; // xmm0_8\n double *v7; // rax\n double *v8; // rdx\n int v9; // ecx\n double *v10; // rdi\n __int64 v11; // r8\n double v12; // xmm0_8\n double *v13; // rax\n double *v14; // rdx\n __int64 v15; // rsi\n __int64 v16; // rax\n double v17; // xmm0_8\n double v18; // xmm1_8\n double v19; // [rsp+0h] [rbp-20h]\n\n if ( a2 <= 1 )\n return -9999999.0;\n v2 = 1LL;\n v3 = 0;\n v4 = a1;\n do\n {\n v5 = v2;\n while ( a1[v2 - 1] != a1[v5] )\n {\n if ( a2 <= (int)++v5 )\n goto LABEL_7;\n }\n ++v3;\nLABEL_7:\n ++v2;\n }\n while ( v2 != a2 );\n if ( a2 != 2 || (result = -9999999.0, v3 != 1) )\n {\n v7 = (double *)malloc(8LL * a2);\n v8 = &a1[a2];\n v9 = 0;\n v10 = v7;\n while ( 1 )\n {\n v11 = v9;\n v12 = *v4;\n if ( v9 > 0 )\n break;\nLABEL_17:\n ++v4;\n ++v9;\n v10[v11] = v12;\n if ( v8 == v4 )\n goto LABEL_18;\n }\n while ( 1 )\n {\n v13 = v10;\n while ( v12 != *v13 )\n {\n if ( &v10[v9] == ++v13 )\n goto LABEL_17;\n }\n if ( v8 == ++v4 )\n break;\n v12 = *v4;\n }\nLABEL_18:\n if ( v9 > 0 )\n {\n v14 = v10;\n v15 = 1LL;\n if ( v9 != 1 )\n {\n do\n {\n v16 = v15;\n do\n {\n v17 = *v14;\n v18 = v10[v16];\n if ( *v14 > v18 )\n {\n *v14 = v18;\n v10[v16] = v17;\n }\n ++v16;\n }\n while ( v9 > (int)v16 );\n ++v15;\n ++v14;\n }\n while ( v15 != v9 );\n }\n }\n v19 = v10[1];\n free(v10);\n return v19;\n }\n return result;\n}", + "ida_strip_asm": "sub_1310:\nendbr64\ncmp esi, 1\njle loc_1452\npush rbp\nmov edx, 1\nxor ecx, ecx\npush rbx\nmov rbx, rdi\nmov edi, esi\nsub rsp, 18h\nnop\nloc_1330:\nmovsd xmm0, qword ptr [rbx+rdx*8-8]\nmov rax, rdx\njmp short loc_1348\nloc_1340:\nadd rax, 1\ncmp esi, eax\njle short loc_1354\nloc_1348:\nucomisd xmm0, qword ptr [rbx+rax*8]\njp short loc_1340\njnz short loc_1340\nadd ecx, 1\nloc_1354:\nadd rdx, 1\ncmp rdx, rdi\njnz short loc_1330\ncmp esi, 2\njnz short loc_1376\nmovsd xmm0, cs:qword_2078\ncmp ecx, 1\njnz short loc_1376\nadd rsp, 18h\npop rbx\npop rbp\nretn\nloc_1376:\nmovsxd rdx, esi\nlea rbp, ds:0[rdx*8]\nmov rdi, rbp; size\ncall _malloc\nlea rdx, [rbx+rbp]\nxor ecx, ecx\nmov rdi, rax; ptr\nloc_1392:\nmovsxd r8, ecx\nmovsd xmm0, qword ptr [rbx]\nlea rsi, [rdi+r8*8]\ntest ecx, ecx\njle short loc_13D0\nloc_13A1:\nmov rax, rdi\njmp short loc_13B9\nloc_13B0:\nadd rax, 8\ncmp rsi, rax\njz short loc_13D0\nloc_13B9:\nucomisd xmm0, qword ptr [rax]\njp short loc_13B0\njnz short loc_13B0\nadd rbx, 8\ncmp rdx, rbx\njz short loc_13E2\nmovsd xmm0, qword ptr [rbx]\njmp short loc_13A1\nloc_13D0:\nadd rbx, 8\nadd ecx, 1\nmovsd qword ptr [rdi+r8*8], xmm0\ncmp rdx, rbx\njnz short loc_1392\nloc_13E2:\ntest ecx, ecx\njle short loc_1435\nmov rdx, rdi\nmov r8d, ecx\nmov esi, 1\ncmp ecx, 1\njz short loc_1435\nnop word ptr [rax+rax+00000000h]\nloc_1400:\nmov rax, rsi\nnop dword ptr [rax+rax+00h]\nloc_1408:\nmovsd xmm0, qword ptr [rdx]\nmovsd xmm1, qword ptr [rdi+rax*8]\ncomisd xmm0, xmm1\njbe short loc_1420\nmovsd qword ptr [rdx], xmm1\nmovsd qword ptr [rdi+rax*8], xmm0\nloc_1420:\nadd rax, 1\ncmp ecx, eax\njg short loc_1408\nadd rsi, 1\nadd rdx, 8\ncmp rsi, r8\njnz short loc_1400\nloc_1435:\nmovsd xmm0, qword ptr [rdi+8]\nmovsd [rsp+28h+var_20], xmm0\ncall _free\nmovsd xmm0, [rsp+28h+var_20]\nadd rsp, 18h\npop rbx\npop rbp\nretn\nloc_1452:\nmovsd xmm0, cs:qword_2078\nretn", + "ida_strip_pseudo": "double __fastcall sub_1310(double *a1, int a2)\n{\n __int64 v2; // rdx\n int v3; // ecx\n double *v4; // rbx\n __int64 v5; // rax\n double result; // xmm0_8\n double *v7; // rax\n double *v8; // rdx\n int v9; // ecx\n double *v10; // rdi\n __int64 v11; // r8\n double v12; // xmm0_8\n double *v13; // rax\n double *v14; // rdx\n __int64 v15; // rsi\n __int64 v16; // rax\n double v17; // xmm0_8\n double v18; // xmm1_8\n double v19; // [rsp+0h] [rbp-20h]\n\n if ( a2 <= 1 )\n return -9999999.0;\n v2 = 1LL;\n v3 = 0;\n v4 = a1;\n do\n {\n v5 = v2;\n while ( a1[v2 - 1] != a1[v5] )\n {\n if ( a2 <= (int)++v5 )\n goto LABEL_7;\n }\n ++v3;\nLABEL_7:\n ++v2;\n }\n while ( v2 != a2 );\n if ( a2 != 2 || (result = -9999999.0, v3 != 1) )\n {\n v7 = (double *)malloc(8LL * a2);\n v8 = &a1[a2];\n v9 = 0;\n v10 = v7;\n while ( 1 )\n {\n v11 = v9;\n v12 = *v4;\n if ( v9 > 0 )\n break;\nLABEL_17:\n ++v4;\n ++v9;\n v10[v11] = v12;\n if ( v8 == v4 )\n goto LABEL_18;\n }\n while ( 1 )\n {\n v13 = v10;\n while ( v12 != *v13 )\n {\n if ( &v10[v9] == ++v13 )\n goto LABEL_17;\n }\n if ( v8 == ++v4 )\n break;\n v12 = *v4;\n }\nLABEL_18:\n if ( v9 > 0 )\n {\n v14 = v10;\n v15 = 1LL;\n if ( v9 != 1 )\n {\n do\n {\n v16 = v15;\n do\n {\n v17 = *v14;\n v18 = v10[v16];\n if ( *v14 > v18 )\n {\n *v14 = v18;\n v10[v16] = v17;\n }\n ++v16;\n }\n while ( v9 > (int)v16 );\n ++v15;\n ++v14;\n }\n while ( v15 != v9 );\n }\n }\n v19 = v10[1];\n free(v10);\n return v19;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1310(double *a1, int a2) {\n long long v2;\n int v3;\n double *v4;\n long long v5;\n double result;\n double *v7;\n double *v8;\n int v9;\n double *v10;\n long long v11;\n double v12;\n double *v13;\n double *v14;\n long long v15;\n long long v16;\n double v17;\n double v18;\n double v19;\n if (a2 <= 1) return -9999999.0;\n v2 = 1LL;\n v3 = 0;\n v4 = a1;\n do {\n v5 = v2;\n while (a1[v2 - 1] != a1[v5]) {\n if (a2 <= (int)++v5) goto LABEL_7;\n }\n ++v3;\n LABEL_7:\n ++v2;\n } while (v2 != a2);\n if (a2 != 2 || (result = -9999999.0, v3 != 1)) {\n v7 = (double *)malloc(8LL * a2);\n v8 = &a1[a2];\n v9 = 0;\n v10 = v7;\n while (1) {\n v11 = v9;\n v12 = *v4;\n if (v9 > 0) break;\n LABEL_17:\n ++v4;\n ++v9;\n v10[v11] = v12;\n if (v8 == v4) goto LABEL_18;\n }\n while (1) {\n v13 = v10;\n while (v12 != *v13) {\n if (&v10[v9] == ++v13) goto LABEL_17;\n }\n if (v8 == ++v4) break;\n v12 = *v4;\n }\n LABEL_18:\n if (v9 > 0) {\n v14 = v10;\n v15 = 1LL;\n if (v9 != 1) {\n do {\n v16 = v15;\n do {\n v17 = *v14;\n v18 = v10[v16];\n if (*v14 > v18) {\n *v14 = v18;\n v10[v16] = v17;\n }\n ++v16;\n } while (v9 > (int)v16);\n ++v15;\n ++v14;\n } while (v15 != v9);\n }\n }\n v19 = v10[1];\n free(v10);\n return v19;\n }\n return result;\n}", + "ida_pseudo_norm": "double func0(double *a1, int a2) {\n long long v2;\n int v3;\n double *v4;\n long long v5;\n double result;\n double *v7;\n double *v8;\n int v9;\n double *v10;\n long long v11;\n double v12;\n double *v13;\n double *v14;\n long long v15;\n long long v16;\n double v17;\n double v18;\n double v19;\n if (a2 <= 1) return -9999999.0;\n v2 = 1LL;\n v3 = 0;\n v4 = a1;\n do {\n v5 = v2;\n while (a1[v2 - 1] != a1[v5]) {\n if (a2 <= (int)++v5) goto LABEL_7;\n }\n ++v3;\n LABEL_7:\n ++v2;\n } while (v2 != a2);\n if (a2 != 2 || (result = -9999999.0, v3 != 1)) {\n v7 = (double *)malloc(8LL * a2);\n v8 = &a1[a2];\n v9 = 0;\n v10 = v7;\n while (1) {\n v11 = v9;\n v12 = *v4;\n if (v9 > 0) break;\n LABEL_17:\n ++v4;\n ++v9;\n v10[v11] = v12;\n if (v8 == v4) goto LABEL_18;\n }\n while (1) {\n v13 = v10;\n while (v12 != *v13) {\n if (&v10[v9] == ++v13) goto LABEL_17;\n }\n if (v8 == ++v4) break;\n v12 = *v4;\n }\n LABEL_18:\n if (v9 > 0) {\n v14 = v10;\n v15 = 1LL;\n if (v9 != 1) {\n do {\n v16 = v15;\n do {\n v17 = *v14;\n v18 = v10[v16];\n if (*v14 > v18) {\n *v14 = v18;\n v10[v16] = v17;\n }\n ++v16;\n } while (v9 > (int)v16);\n ++v15;\n ++v14;\n } while (v15 != v9);\n }\n }\n v19 = v10[1];\n free(v10);\n return v19;\n }\n return result;\n}" + }, + { + "index": 756, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "const char* func0(const char* text) {\n regex_t regex;\n int ret;\n const char* result;\n ret = regcomp(®ex, \"ab?\", REG_EXTENDED);\n if (ret) {\n return \"Not matched!\";\n }\n ret = regexec(®ex, text, 0, NULL, 0);\n if (!ret) {\n result = \"Found a match!\";\n }\n else {\n result = \"Not matched!\";\n }\n regfree(®ex);\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"ac\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\"dc\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"abbbba\"), \"Found a match!\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x70,%rsp\nmov %rdi,-0x68(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea -0x50(%rbp),%rax\nmov $0x1,%edx\nlea 0xdf0(%rip),%rsi\nmov %rax,%rdi\ncallq 10d0 \nmov %eax,-0x5c(%rbp)\ncmpl $0x0,-0x5c(%rbp)\nje 1232 \nlea 0xddc(%rip),%rax\njmp 1283 \nmov -0x68(%rbp),%rsi\nlea -0x50(%rbp),%rax\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rax,%rdi\ncallq 10f0 \nmov %eax,-0x5c(%rbp)\ncmpl $0x0,-0x5c(%rbp)\njne 1268 \nlea 0xdb7(%rip),%rax\nmov %rax,-0x58(%rbp)\njmp 1273 \nlea 0xd9d(%rip),%rax\nmov %rax,-0x58(%rbp)\nlea -0x50(%rbp),%rax\nmov %rax,%rdi\ncallq 10a0 \nmov -0x58(%rbp),%rax\nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 1297 \ncallq 10b0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nlea rcx, pattern; \"ab?\"\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+var_5C], eax\ncmp [rbp+var_5C], 0\njz short loc_1235\nlea rax, aNotMatched; \"Not matched!\"\njmp short loc_1286\nloc_1235:\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_5C], eax\ncmp [rbp+var_5C], 0\njnz short loc_126B\nlea rax, s2; \"Found a match!\"\nmov [rbp+var_58], rax\njmp short loc_1276\nloc_126B:\nlea rax, aNotMatched; \"Not matched!\"\nmov [rbp+var_58], rax\nloc_1276:\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nmov rax, [rbp+var_58]\nloc_1286:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_129A\ncall ___stack_chk_fail\nlocret_129A:\nleave\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n const char *v2; // [rsp+18h] [rbp-58h]\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n unsigned __int64 v4; // [rsp+68h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"ab?\", 1) )\n return \"Not matched!\";\n if ( regexec(&preg, a1, 0LL, 0LL, 0) )\n v2 = \"Not matched!\";\n else\n v2 = \"Found a match!\";\n regfree(&preg);\n return v2;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nlea rcx, pattern; \"ab?\"\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+var_5C], eax\ncmp [rbp+var_5C], 0\njz short loc_1235\nlea rax, aNotMatched; \"Not matched!\"\njmp short loc_1286\nloc_1235:\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_5C], eax\ncmp [rbp+var_5C], 0\njnz short loc_126B\nlea rax, s2; \"Found a match!\"\nmov [rbp+var_58], rax\njmp short loc_1276\nloc_126B:\nlea rax, aNotMatched; \"Not matched!\"\nmov [rbp+var_58], rax\nloc_1276:\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nmov rax, [rbp+var_58]\nloc_1286:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_129A\ncall ___stack_chk_fail\nlocret_129A:\nleave\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_11E9(const char *a1)\n{\n const char *v2; // [rsp+18h] [rbp-58h]\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n unsigned __int64 v4; // [rsp+68h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"ab?\", 1) )\n return \"Not matched!\";\n if ( regexec(&preg, a1, 0LL, 0LL, 0) )\n v2 = \"Not matched!\";\n else\n v2 = \"Found a match!\";\n regfree(&preg);\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_11E9(const char *a1) {\n const char *v2;\n regex_t preg;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n if (regcomp(&preg, \"ab?\", 1)) return \"Not matched!\";\n if (regexec(&preg, a1, 0LL, 0LL, 0))\n v2 = \"Not matched!\";\n else\n v2 = \"Found a match!\";\n regfree(&preg);\n return v2;\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n const char *v2;\n regex_t preg;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n if (regcomp(&preg, \"ab?\", 1)) return \"Not matched!\";\n if (regexec(&preg, a1, 0LL, 0LL, 0))\n v2 = \"Not matched!\";\n else\n v2 = \"Found a match!\";\n regfree(&preg);\n return v2;\n}" + }, + { + "index": 756, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "const char* func0(const char* text) {\n regex_t regex;\n int ret;\n const char* result;\n ret = regcomp(®ex, \"ab?\", REG_EXTENDED);\n if (ret) {\n return \"Not matched!\";\n }\n ret = regexec(®ex, text, 0, NULL, 0);\n if (!ret) {\n result = \"Found a match!\";\n }\n else {\n result = \"Not matched!\";\n }\n regfree(®ex);\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"ac\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\"dc\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"abbbba\"), \"Found a match!\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x58,%rsp\nmov %rdi,%rbx\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nmov $0x1,%edx\nlea 0xe2b(%rip),%rsi\ncallq 10c0 \nlea 0xe12(%rip),%rbp\ntest %eax,%eax\nje 121f \nmov 0x48(%rsp),%rax\nxor %fs:0x28,%rax\njne 1258 \nmov %rbp,%rax\nadd $0x58,%rsp\npop %rbx\npop %rbp\nretq\nmov %rsp,%rdi\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rbx,%rsi\ncallq 10d0 \ntest %eax,%eax\nlea 0xdc1(%rip),%rbp\nlea 0xdc9(%rip),%rax\ncmovne %rax,%rbp\nmov %rsp,%rdi\ncallq 1090 \njmp 1205 \ncallq 10a0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rbp, rdi\nmov rax, fs:28h\nmov [rsp+68h+var_20], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"ab?\"\ncall _regcomp\nlea rbx, aNotMatched; \"Not matched!\"\ntest eax, eax\njz short loc_123F\nloc_1225:\nmov rax, [rsp+68h+var_20]\nsub rax, fs:28h\njnz short loc_1271\nmov rax, rbx\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_123F:\nmov rdi, rsp; preg\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbp; string\ncall _regexec\ntest eax, eax\nlea rax, s2; \"Found a match!\"\ncmovz rbx, rax\nmov rdi, rsp; preg\ncall _regfree\njmp short loc_1225\nloc_1271:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n const char *v1; // rbx\n regex_t v3; // [rsp+0h] [rbp-68h] BYREF\n unsigned __int64 v4; // [rsp+48h] [rbp-20h]\n\n v4 = __readfsqword(0x28u);\n v1 = \"Not matched!\";\n if ( !regcomp(&v3, \"ab?\", 1) )\n {\n if ( !regexec(&v3, string, 0LL, 0LL, 0) )\n v1 = \"Found a match!\";\n regfree(&v3);\n }\n return v1;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rbp, rdi\nmov rax, fs:28h\nmov [rsp+68h+var_20], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"ab?\"\ncall _regcomp\nlea rbx, aNotMatched; \"Not matched!\"\ntest eax, eax\njz short loc_123F\nloc_1225:\nmov rax, [rsp+68h+var_20]\nsub rax, fs:28h\njnz short loc_1271\nmov rax, rbx\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_123F:\nmov rdi, rsp; preg\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbp; string\ncall _regexec\ntest eax, eax\nlea rax, s2; \"Found a match!\"\ncmovz rbx, rax\nmov rdi, rsp; preg\ncall _regfree\njmp short loc_1225\nloc_1271:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_11E9(char *string)\n{\n const char *v1; // rbx\n regex_t v3; // [rsp+0h] [rbp-68h] BYREF\n unsigned __int64 v4; // [rsp+48h] [rbp-20h]\n\n v4 = __readfsqword(0x28u);\n v1 = \"Not matched!\";\n if ( !regcomp(&v3, \"ab?\", 1) )\n {\n if ( !regexec(&v3, string, 0LL, 0LL, 0) )\n v1 = \"Found a match!\";\n regfree(&v3);\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_11E9(char *string) {\n const char *v1;\n regex_t v3;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n v1 = \"Not matched!\";\n if (!regcomp(&v3, \"ab?\", 1)) {\n if (!regexec(&v3, string, 0LL, 0LL, 0)) v1 = \"Found a match!\";\n regfree(&v3);\n }\n return v1;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n const char *v1;\n regex_t v3;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n v1 = \"Not matched!\";\n if (!regcomp(&v3, \"ab?\", 1)) {\n if (!regexec(&v3, string, 0LL, 0LL, 0)) v1 = \"Found a match!\";\n regfree(&v3);\n }\n return v1;\n}" + }, + { + "index": 756, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "const char* func0(const char* text) {\n regex_t regex;\n int ret;\n const char* result;\n ret = regcomp(®ex, \"ab?\", REG_EXTENDED);\n if (ret) {\n return \"Not matched!\";\n }\n ret = regexec(®ex, text, 0, NULL, 0);\n if (!ret) {\n result = \"Found a match!\";\n }\n else {\n result = \"Not matched!\";\n }\n regfree(®ex);\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"ac\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\"dc\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"abbbba\"), \"Found a match!\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov $0x1,%edx\nlea 0xd5e(%rip),%rsi\nlea 0xd4a(%rip),%r13\npush %r12\npush %rbp\nmov %rdi,%rbp\nsub $0x50,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%r12\nmov %r12,%rdi\ncallq 10c0 \ntest %eax,%eax\njne 1319 \nxor %r8d,%r8d\nxor %ecx,%ecx\nxor %edx,%edx\nmov %r12,%rdi\nmov %rbp,%rsi\ncallq 10d0 \nmov %r12,%rdi\ntest %eax,%eax\nlea 0xcf4(%rip),%rax\ncmove %rax,%r13\ncallq 1090 \nmov 0x48(%rsp),%rax\nxor %fs:0x28,%rax\njne 1336 \nadd $0x50,%rsp\nmov %r13,%rax\npop %rbp\npop %r12\npop %r13\nretq\ncallq 10a0 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r12\nmov edx, 1; cflags\nlea rsi, pattern; \"ab?\"\nlea r12, aNotMatched; \"Not matched!\"\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 50h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njnz short loc_1328\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rdi, rbp; preg\nmov rsi, rbx; string\ncall _regexec\nmov rdi, rbp; preg\ntest eax, eax\nlea rax, s2; \"Found a match!\"\ncmovz r12, rax\ncall _regfree\nloc_1328:\nmov rax, [rsp+var_s48]\nsub rax, fs:28h\njnz short loc_1344\nadd rsp, 50h\nmov rax, r12\npop rbx\npop rbp\npop r12\nretn\nloc_1344:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n const char *v1; // r12\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n v1 = \"Not matched!\";\n vars48 = __readfsqword(0x28u);\n if ( !regcomp(&_0, \"ab?\", 1) )\n {\n if ( !regexec(&_0, string, 0LL, 0LL, 0) )\n v1 = \"Found a match!\";\n regfree(&_0);\n }\n return v1;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\npush r12\nmov edx, 1; cflags\nlea rsi, pattern; \"ab?\"\nlea r12, aNotMatched; \"Not matched!\"\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 50h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njnz short loc_1328\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rdi, rbp; preg\nmov rsi, rbx; string\ncall _regexec\nmov rdi, rbp; preg\ntest eax, eax\nlea rax, s2; \"Found a match!\"\ncmovz r12, rax\ncall _regfree\nloc_1328:\nmov rax, [rsp+var_s48]\nsub rax, fs:28h\njnz short loc_1344\nadd rsp, 50h\nmov rax, r12\npop rbx\npop rbp\npop r12\nretn\nloc_1344:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_12C0(char *string)\n{\n const char *v1; // r12\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n v1 = \"Not matched!\";\n vars48 = __readfsqword(0x28u);\n if ( !regcomp(&_0, \"ab?\", 1) )\n {\n if ( !regexec(&_0, string, 0LL, 0LL, 0) )\n v1 = \"Found a match!\";\n regfree(&_0);\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_12C0(char *string) {\n const char *v1;\n regex_t _0;\n unsigned long long vars48;\n v1 = \"Not matched!\";\n vars48 = __readfsqword(40u);\n if (!regcomp(&_0, \"ab?\", 1)) {\n if (!regexec(&_0, string, 0LL, 0LL, 0)) v1 = \"Found a match!\";\n regfree(&_0);\n }\n return v1;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n const char *v1;\n regex_t _0;\n unsigned long long vars48;\n v1 = \"Not matched!\";\n vars48 = __readfsqword(40u);\n if (!regcomp(&_0, \"ab?\", 1)) {\n if (!regexec(&_0, string, 0LL, 0LL, 0)) v1 = \"Found a match!\";\n regfree(&_0);\n }\n return v1;\n}" + }, + { + "index": 756, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "const char* func0(const char* text) {\n regex_t regex;\n int ret;\n const char* result;\n ret = regcomp(®ex, \"ab?\", REG_EXTENDED);\n if (ret) {\n return \"Not matched!\";\n }\n ret = regexec(®ex, text, 0, NULL, 0);\n if (!ret) {\n result = \"Found a match!\";\n }\n else {\n result = \"Not matched!\";\n }\n regfree(®ex);\n return result;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"ac\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\"dc\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"abbbba\"), \"Found a match!\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov $0x1,%edx\nlea 0xd5e(%rip),%rsi\nlea 0xd4a(%rip),%r13\npush %r12\npush %rbp\nmov %rdi,%rbp\nsub $0x50,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%r12\nmov %r12,%rdi\ncallq 10c0 \ntest %eax,%eax\njne 1319 \nxor %r8d,%r8d\nxor %ecx,%ecx\nxor %edx,%edx\nmov %r12,%rdi\nmov %rbp,%rsi\ncallq 10d0 \nmov %r12,%rdi\ntest %eax,%eax\nlea 0xcf4(%rip),%rax\ncmove %rax,%r13\ncallq 1090 \nmov 0x48(%rsp),%rax\nxor %fs:0x28,%rax\njne 1336 \nadd $0x50,%rsp\nmov %r13,%rax\npop %rbp\npop %r12\npop %r13\nretq\ncallq 10a0 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r12\nmov edx, 1; cflags\nlea rsi, pattern; \"ab?\"\nlea r12, aNotMatched; \"Not matched!\"\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 50h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njnz short loc_1328\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rdi, rbp; preg\nmov rsi, rbx; string\ncall _regexec\nmov rdi, rbp; preg\ntest eax, eax\nlea rax, s2; \"Found a match!\"\ncmovz r12, rax\ncall _regfree\nloc_1328:\nmov rax, [rsp+var_s48]\nsub rax, fs:28h\njnz short loc_1344\nadd rsp, 50h\nmov rax, r12\npop rbx\npop rbp\npop r12\nretn\nloc_1344:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n const char *v1; // r12\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n v1 = \"Not matched!\";\n vars48 = __readfsqword(0x28u);\n if ( !regcomp(&_0, \"ab?\", 1) )\n {\n if ( !regexec(&_0, string, 0LL, 0LL, 0) )\n v1 = \"Found a match!\";\n regfree(&_0);\n }\n return v1;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\npush r12\nmov edx, 1; cflags\nlea rsi, pattern; \"ab?\"\nlea r12, aNotMatched; \"Not matched!\"\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 50h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njnz short loc_1328\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rdi, rbp; preg\nmov rsi, rbx; string\ncall _regexec\nmov rdi, rbp; preg\ntest eax, eax\nlea rax, s2; \"Found a match!\"\ncmovz r12, rax\ncall _regfree\nloc_1328:\nmov rax, [rsp+var_s48]\nsub rax, fs:28h\njnz short loc_1344\nadd rsp, 50h\nmov rax, r12\npop rbx\npop rbp\npop r12\nretn\nloc_1344:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_12C0(char *string)\n{\n const char *v1; // r12\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n v1 = \"Not matched!\";\n vars48 = __readfsqword(0x28u);\n if ( !regcomp(&_0, \"ab?\", 1) )\n {\n if ( !regexec(&_0, string, 0LL, 0LL, 0) )\n v1 = \"Found a match!\";\n regfree(&_0);\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_12C0(char *string) {\n const char *v1;\n regex_t _0;\n unsigned long long vars48;\n v1 = \"Not matched!\";\n vars48 = __readfsqword(40u);\n if (!regcomp(&_0, \"ab?\", 1)) {\n if (!regexec(&_0, string, 0LL, 0LL, 0)) v1 = \"Found a match!\";\n regfree(&_0);\n }\n return v1;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n const char *v1;\n regex_t _0;\n unsigned long long vars48;\n v1 = \"Not matched!\";\n vars48 = __readfsqword(40u);\n if (!regcomp(&_0, \"ab?\", 1)) {\n if (!regexec(&_0, string, 0LL, 0LL, 0)) v1 = \"Found a match!\";\n regfree(&_0);\n }\n return v1;\n}" + }, + { + "index": 757, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* test_list[], int size) {\n int count = 0;\n for (int idx = 0; idx < size; idx++) {\n for (int idxn = idx; idxn < size; idxn++) {\n char reversed[100];\n int len = strlen(test_list[idx]);\n for (int i = 0; i < len; i++) {\n reversed[i] = test_list[idx][len - 1 - i];\n }\n reversed[len] = '\\0';\n if (strcmp(test_list[idxn], reversed) == 0) {\n count++;\n }\n }\n }\n static char result[12];\n sprintf(result, \"%d\", count);\n return result;\n}", + "test": "int main() {\n\n char* test1[] = {\"julia\", \"best\", \"tseb\", \"for\", \"ailuj\"};\n\n char* test2[] = {\"geeks\", \"best\", \"for\", \"skeeg\"};\n\n char* test3[] = {\"makes\", \"best\", \"sekam\", \"for\", \"rof\"};\n\n assert(strcmp(func0(test1, 5), \"2\") == 0);\n\n assert(strcmp(func0(test2, 4), \"1\") == 0);\n\n assert(strcmp(func0(test3, 5), \"2\") == 0);\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0xa0,%rsp\nmov %rdi,-0x98(%rbp)\nmov %esi,-0x9c(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovl $0x0,-0x84(%rbp)\nmovl $0x0,-0x80(%rbp)\njmpq 12d8 \nmov -0x80(%rbp),%eax\nmov %eax,-0x7c(%rbp)\njmpq 12c5 \nmov -0x80(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x98(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov %rax,%rdi\ncallq 1090 \nmov %eax,-0x74(%rbp)\nmovl $0x0,-0x78(%rbp)\njmp 127b \nmov -0x80(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x98(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rdx\nmov -0x74(%rbp),%eax\nsub $0x1,%eax\nsub -0x78(%rbp),%eax\ncltq\nadd %rdx,%rax\nmovzbl (%rax),%edx\nmov -0x78(%rbp),%eax\ncltq\nmov %dl,-0x70(%rbp,%rax,1)\naddl $0x1,-0x78(%rbp)\nmov -0x78(%rbp),%eax\ncmp -0x74(%rbp),%eax\njl 1243 \nmov -0x74(%rbp),%eax\ncltq\nmovb $0x0,-0x70(%rbp,%rax,1)\nmov -0x7c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x98(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nlea -0x70(%rbp),%rdx\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10c0 \ntest %eax,%eax\njne 12c1 \naddl $0x1,-0x84(%rbp)\naddl $0x1,-0x7c(%rbp)\nmov -0x7c(%rbp),%eax\ncmp -0x9c(%rbp),%eax\njl 1215 \naddl $0x1,-0x80(%rbp)\nmov -0x80(%rbp),%eax\ncmp -0x9c(%rbp),%eax\njl 120a \nmov -0x84(%rbp),%eax\nmov %eax,%edx\nlea 0xd12(%rip),%rsi\nlea 0x2d1b(%rip),%rdi\nmov $0x0,%eax\ncallq 10d0 \nlea 0x2d0a(%rip),%rax\nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 1322 \ncallq 10a0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0A0h\nmov [rbp+var_98], rdi\nmov [rbp+var_9C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_84], 0\nmov [rbp+var_80], 0\njmp loc_12D8\nloc_120A:\nmov eax, [rbp+var_80]\nmov [rbp+var_7C], eax\njmp loc_12C5\nloc_1215:\nmov eax, [rbp+var_80]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_98]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_74], eax\nmov [rbp+var_78], 0\njmp short loc_127B\nloc_1243:\nmov eax, [rbp+var_80]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_98]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_74]\nsub eax, 1\nsub eax, [rbp+var_78]\ncdqe\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_78]\ncdqe\nmov [rbp+rax+s2], dl\nadd [rbp+var_78], 1\nloc_127B:\nmov eax, [rbp+var_78]\ncmp eax, [rbp+var_74]\njl short loc_1243\nmov eax, [rbp+var_74]\ncdqe\nmov [rbp+rax+s2], 0\nmov eax, [rbp+var_7C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_98]\nadd rax, rdx\nmov rax, [rax]\nlea rdx, [rbp+s2]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_12C1\nadd [rbp+var_84], 1\nloc_12C1:\nadd [rbp+var_7C], 1\nloc_12C5:\nmov eax, [rbp+var_7C]\ncmp eax, [rbp+var_9C]\njl loc_1215\nadd [rbp+var_80], 1\nloc_12D8:\nmov eax, [rbp+var_80]\ncmp eax, [rbp+var_9C]\njl loc_120A\nmov eax, [rbp+var_84]\nmov edx, eax\nlea rax, format; \"%d\"\nmov rsi, rax; format\nlea rax, result_1\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rax, result_1\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1328\ncall ___stack_chk_fail\nlocret_1328:\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2)\n{\n int v3; // [rsp+1Ch] [rbp-84h]\n int i; // [rsp+20h] [rbp-80h]\n int j; // [rsp+24h] [rbp-7Ch]\n int k; // [rsp+28h] [rbp-78h]\n int v7; // [rsp+2Ch] [rbp-74h]\n char s2[104]; // [rsp+30h] [rbp-70h] BYREF\n unsigned __int64 v9; // [rsp+98h] [rbp-8h]\n\n v9 = __readfsqword(0x28u);\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i; j < a2; ++j )\n {\n v7 = strlen(*(const char **)(8LL * i + a1));\n for ( k = 0; k < v7; ++k )\n s2[k] = *(_BYTE *)(*(_QWORD *)(8LL * i + a1) + v7 - 1 - k);\n s2[v7] = 0;\n if ( !strcmp(*(const char **)(8LL * j + a1), s2) )\n ++v3;\n }\n }\n sprintf(result_1, \"%d\", v3);\n return result_1;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0A0h\nmov [rbp+var_98], rdi\nmov [rbp+var_9C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_84], 0\nmov [rbp+var_80], 0\njmp loc_12D8\nloc_120A:\nmov eax, [rbp+var_80]\nmov [rbp+var_7C], eax\njmp loc_12C5\nloc_1215:\nmov eax, [rbp+var_80]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_98]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_74], eax\nmov [rbp+var_78], 0\njmp short loc_127B\nloc_1243:\nmov eax, [rbp+var_80]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_98]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_74]\nsub eax, 1\nsub eax, [rbp+var_78]\ncdqe\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_78]\ncdqe\nmov [rbp+rax+s2], dl\nadd [rbp+var_78], 1\nloc_127B:\nmov eax, [rbp+var_78]\ncmp eax, [rbp+var_74]\njl short loc_1243\nmov eax, [rbp+var_74]\ncdqe\nmov [rbp+rax+s2], 0\nmov eax, [rbp+var_7C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_98]\nadd rax, rdx\nmov rax, [rax]\nlea rdx, [rbp+s2]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_12C1\nadd [rbp+var_84], 1\nloc_12C1:\nadd [rbp+var_7C], 1\nloc_12C5:\nmov eax, [rbp+var_7C]\ncmp eax, [rbp+var_9C]\njl loc_1215\nadd [rbp+var_80], 1\nloc_12D8:\nmov eax, [rbp+var_80]\ncmp eax, [rbp+var_9C]\njl loc_120A\nmov eax, [rbp+var_84]\nmov edx, eax\nlea rax, format; \"%d\"\nmov rsi, rax; format\nlea rax, s\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rax, s\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1328\ncall ___stack_chk_fail\nlocret_1328:\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11C9(__int64 a1, int a2)\n{\n int v3; // [rsp+1Ch] [rbp-84h]\n int i; // [rsp+20h] [rbp-80h]\n int j; // [rsp+24h] [rbp-7Ch]\n int k; // [rsp+28h] [rbp-78h]\n int v7; // [rsp+2Ch] [rbp-74h]\n char s2[104]; // [rsp+30h] [rbp-70h] BYREF\n unsigned __int64 v9; // [rsp+98h] [rbp-8h]\n\n v9 = __readfsqword(0x28u);\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i; j < a2; ++j )\n {\n v7 = strlen(*(const char **)(8LL * i + a1));\n for ( k = 0; k < v7; ++k )\n s2[k] = *(_BYTE *)(*(_QWORD *)(8LL * i + a1) + v7 - 1 - k);\n s2[v7] = 0;\n if ( !strcmp(*(const char **)(8LL * j + a1), s2) )\n ++v3;\n }\n }\n sprintf(s, \"%d\", v3);\n return s;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11C9(long long a1, int a2) {\n int v3;\n int i;\n int j;\n int k;\n int v7;\n char s2[104];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = i; j < a2; ++j) {\n v7 = strlen(*(const char **)(8LL * i + a1));\n for (k = 0; k < v7; ++k)\n s2[k] = *(uint8_t *)(*(uint64_t *)(8LL * i + a1) + v7 - 1 - k);\n s2[v7] = 0;\n if (!strcmp(*(const char **)(8LL * j + a1), s2)) ++v3;\n }\n }\n sprintf(s, \"%d\", v3);\n return s;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2) {\n int v3;\n int i;\n int j;\n int k;\n int v7;\n char s2[104];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = i; j < a2; ++j) {\n v7 = strlen(*(const char **)(8LL * i + a1));\n for (k = 0; k < v7; ++k)\n s2[k] = *(uint8_t *)(*(uint64_t *)(8LL * i + a1) + v7 - 1 - k);\n s2[v7] = 0;\n if (!strcmp(*(const char **)(8LL * j + a1), s2)) ++v3;\n }\n }\n sprintf(result_1, \"%d\", v3);\n return result_1;\n}" + }, + { + "index": 757, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* test_list[], int size) {\n int count = 0;\n for (int idx = 0; idx < size; idx++) {\n for (int idxn = idx; idxn < size; idxn++) {\n char reversed[100];\n int len = strlen(test_list[idx]);\n for (int i = 0; i < len; i++) {\n reversed[i] = test_list[idx][len - 1 - i];\n }\n reversed[len] = '\\0';\n if (strcmp(test_list[idxn], reversed) == 0) {\n count++;\n }\n }\n }\n static char result[12];\n sprintf(result, \"%d\", count);\n return result;\n}", + "test": "int main() {\n\n char* test1[] = {\"julia\", \"best\", \"tseb\", \"for\", \"ailuj\"};\n\n char* test2[] = {\"geeks\", \"best\", \"for\", \"skeeg\"};\n\n char* test3[] = {\"makes\", \"best\", \"sekam\", \"for\", \"rof\"};\n\n assert(strcmp(func0(test1, 5), \"2\") == 0);\n\n assert(strcmp(func0(test2, 4), \"1\") == 0);\n\n assert(strcmp(func0(test3, 5), \"2\") == 0);\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x98,%rsp\nmov %esi,%ebx\nmov %esi,0x10(%rsp)\nmov %fs:0x28,%rsi\nmov %rsi,0x88(%rsp)\nxor %esi,%esi\ntest %ebx,%ebx\njle 12c2 \nmov %rdi,%rax\nsub $0x1,%ebx\nmov %ebx,0x14(%rsp)\nmov %ebx,%ebx\nmov %rbx,0x8(%rsp)\nmov %rdi,%r12\nmovq $0x0,(%rsp)\nmov $0x0,%ebp\nadd $0x8,%rax\nmov %rax,0x18(%rsp)\nmov $0xffffffffffffffff,%r15\nlea 0x20(%rsp),%r14\njmpq 129b \nmovslq %esi,%rsi\nmovb $0x0,0x20(%rsp,%rsi,1)\nmov %r14,%rsi\nmov (%rbx),%rdi\ncallq 10a0 \ncmp $0x1,%eax\nadc $0x0,%ebp\nadd $0x8,%rbx\ncmp %r13,%rbx\nje 1284 \nmov (%r12),%r8\nmov %r15,%rcx\nmov %r8,%rdi\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nlea -0x1(%rcx),%rsi\ntest %esi,%esi\njle 121a \nmovslq %esi,%rcx\nlea -0x1(%r8,%rcx,1),%rax\nlea 0x20(%rsp),%rdx\nlea -0x2(%r8,%rcx,1),%rdi\nlea -0x1(%rsi),%ecx\nsub %rcx,%rdi\nmovzbl (%rax),%ecx\nmov %cl,(%rdx)\nsub $0x1,%rax\nadd $0x1,%rdx\ncmp %rdi,%rax\njne 1270 \njmp 121a \nmov (%rsp),%rbx\nlea 0x1(%rbx),%rax\nadd $0x8,%r12\ncmp 0x8(%rsp),%rbx\nje 12c7 \nmov %rax,(%rsp)\nmov (%rsp),%ebx\ncmp %ebx,0x10(%rsp)\njle 1284 \nmov 0x14(%rsp),%eax\nmov (%rsp),%rbx\nsub %ebx,%eax\nadd %rbx,%rax\nmov 0x18(%rsp),%rbx\nlea (%rbx,%rax,8),%r13\nmov %r12,%rbx\njmpq 123c \nmov $0x0,%ebp\nmov %ebp,%r8d\nlea 0xd33(%rip),%rcx\nmov $0xc,%edx\nmov $0x1,%esi\nlea 0x2d36(%rip),%rdi\nmov $0x0,%eax\ncallq 10b0 <__sprintf_chk@plt>\nmov 0x88(%rsp),%rax\nxor %fs:0x28,%rax\njne 1318 \nlea 0x2d12(%rip),%rax\nadd $0x98,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\ncallq 1080 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 98h\nmov [rsp+0C8h+var_B0], rdi\nmov [rsp+0C8h+var_BC], esi\nmov rax, fs:28h\nmov [rsp+0C8h+var_40], rax\nxor eax, eax\ntest esi, esi\njle loc_12B7\nmov eax, esi\ncdqe\nmov [rsp+0C8h+var_B8], rax\nmov r15d, 0\nmov r12d, 0\nlea rax, [rsp+0C8h+var_A8]\nmov [rsp+0C8h+s2], rax\njmp loc_12AA\nloc_1225:\nmov rcx, [rsp+0C8h+var_B0]\nmov rbp, [rcx+r15*8]\nlea rbx, [rcx+r15*8]\nmov eax, [rsp+0C8h+var_BC]\nsub eax, r15d\nadd rax, r15\nlea r13, [rcx+rax*8]\nlea r14, [rbp-2]\nloc_1244:\nmov rdi, rbp; s\ncall _strlen\ntest eax, eax\njle short loc_1279\nmovsxd rdi, eax\nlea rdx, [rbp+rdi-1]\nlea rcx, [rsp+0C8h+var_A8]\nadd rdi, r14\nlea esi, [rax-1]\nsub rdi, rsi\nloc_1266:\nmovzx esi, byte ptr [rdx]\nmov [rcx], sil\nsub rdx, 1\nadd rcx, 1\ncmp rdx, rdi\njnz short loc_1266\nloc_1279:\ncdqe\nmov [rsp+rax+0C8h+var_A8], 0\nmov rdi, [rbx]; s1\nmov rsi, [rsp+0C8h+s2]; s2\ncall _strcmp\ncmp eax, 1\nadc r12d, 0\nadd rbx, 8\ncmp rbx, r13\njnz short loc_1244\nloc_129C:\nadd r15, 1\nmov rax, [rsp+0C8h+var_B8]\ncmp r15, rax\njz short loc_12BD\nloc_12AA:\ncmp [rsp+0C8h+var_BC], r15d\njg loc_1225\njmp short loc_129C\nloc_12B7:\nmov r12d, 0\nloc_12BD:\nmov r8d, r12d\nlea rcx, unk_2004\nmov edx, 0Ch\nmov esi, 2\nlea rbx, result_1\nmov rdi, rbx\nmov eax, 0\ncall ___sprintf_chk\nmov rax, [rsp+0C8h+var_40]\nsub rax, fs:28h\njnz short loc_130D\nmov rax, rbx\nadd rsp, 98h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_130D:\ncall ___stack_chk_fail", + "ida_pseudo": "void *__fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // r15\n unsigned int v3; // r12d\n const char *v4; // rbp\n const char **v5; // rbx\n int v6; // eax\n const char *v7; // rdx\n char *v8; // rcx\n char v10[104]; // [rsp+20h] [rbp-A8h] BYREF\n unsigned __int64 v11; // [rsp+88h] [rbp-40h]\n\n v11 = __readfsqword(0x28u);\n if ( a2 <= 0 )\n {\n v3 = 0;\n }\n else\n {\n v2 = 0LL;\n v3 = 0;\n do\n {\n if ( a2 > (int)v2 )\n {\n v4 = *(const char **)(a1 + 8 * v2);\n v5 = (const char **)(a1 + 8 * v2);\n do\n {\n v6 = strlen(v4);\n if ( v6 > 0 )\n {\n v7 = &v4[v6 - 1];\n v8 = v10;\n do\n *v8++ = *v7--;\n while ( v7 != &v4[v6 - 2 - (v6 - 1)] );\n }\n v10[v6] = 0;\n v3 += strcmp(*v5++, v10) == 0;\n }\n while ( v5 != (const char **)(a1 + 8 * (v2 + (unsigned int)(a2 - v2))) );\n }\n ++v2;\n }\n while ( v2 != a2 );\n }\n __sprintf_chk(&result_1, 2LL, 12LL, &unk_2004, v3);\n return &result_1;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 98h\nmov [rsp+0C8h+var_B0], rdi\nmov [rsp+0C8h+var_BC], esi\nmov rax, fs:28h\nmov [rsp+0C8h+var_40], rax\nxor eax, eax\ntest esi, esi\njle loc_12B7\nmov eax, esi\ncdqe\nmov [rsp+0C8h+var_B8], rax\nmov r15d, 0\nmov r12d, 0\nlea rax, [rsp+0C8h+var_A8]\nmov [rsp+0C8h+s2], rax\njmp loc_12AA\nloc_1225:\nmov rcx, [rsp+0C8h+var_B0]\nmov rbp, [rcx+r15*8]\nlea rbx, [rcx+r15*8]\nmov eax, [rsp+0C8h+var_BC]\nsub eax, r15d\nadd rax, r15\nlea r13, [rcx+rax*8]\nlea r14, [rbp-2]\nloc_1244:\nmov rdi, rbp; s\ncall _strlen\ntest eax, eax\njle short loc_1279\nmovsxd rdi, eax\nlea rdx, [rbp+rdi-1]\nlea rcx, [rsp+0C8h+var_A8]\nadd rdi, r14\nlea esi, [rax-1]\nsub rdi, rsi\nloc_1266:\nmovzx esi, byte ptr [rdx]\nmov [rcx], sil\nsub rdx, 1\nadd rcx, 1\ncmp rdx, rdi\njnz short loc_1266\nloc_1279:\ncdqe\nmov [rsp+rax+0C8h+var_A8], 0\nmov rdi, [rbx]; s1\nmov rsi, [rsp+0C8h+s2]; s2\ncall _strcmp\ncmp eax, 1\nadc r12d, 0\nadd rbx, 8\ncmp rbx, r13\njnz short loc_1244\nloc_129C:\nadd r15, 1\nmov rax, [rsp+0C8h+var_B8]\ncmp r15, rax\njz short loc_12BD\nloc_12AA:\ncmp [rsp+0C8h+var_BC], r15d\njg loc_1225\njmp short loc_129C\nloc_12B7:\nmov r12d, 0\nloc_12BD:\nmov r8d, r12d\nlea rcx, unk_2004\nmov edx, 0Ch\nmov esi, 2\nlea rbx, unk_4018\nmov rdi, rbx\nmov eax, 0\ncall ___sprintf_chk\nmov rax, [rsp+0C8h+var_40]\nsub rax, fs:28h\njnz short loc_130D\nmov rax, rbx\nadd rsp, 98h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_130D:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "void *__fastcall sub_11C9(__int64 a1, int a2)\n{\n __int64 v2; // r15\n unsigned int v3; // r12d\n const char *v4; // rbp\n const char **v5; // rbx\n int v6; // eax\n const char *v7; // rdx\n char *v8; // rcx\n char v10[104]; // [rsp+20h] [rbp-A8h] BYREF\n unsigned __int64 v11; // [rsp+88h] [rbp-40h]\n\n v11 = __readfsqword(0x28u);\n if ( a2 <= 0 )\n {\n v3 = 0;\n }\n else\n {\n v2 = 0LL;\n v3 = 0;\n do\n {\n if ( a2 > (int)v2 )\n {\n v4 = *(const char **)(a1 + 8 * v2);\n v5 = (const char **)(a1 + 8 * v2);\n do\n {\n v6 = strlen(v4);\n if ( v6 > 0 )\n {\n v7 = &v4[v6 - 1];\n v8 = v10;\n do\n *v8++ = *v7--;\n while ( v7 != &v4[v6 - 2 - (v6 - 1)] );\n }\n v10[v6] = 0;\n v3 += strcmp(*v5++, v10) == 0;\n }\n while ( v5 != (const char **)(a1 + 8 * (v2 + (unsigned int)(a2 - v2))) );\n }\n ++v2;\n }\n while ( v2 != a2 );\n }\n __sprintf_chk(&unk_4018, 2LL, 12LL, &unk_2004, v3);\n return &unk_4018;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_11C9(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n const char *v4;\n const char **v5;\n int v6;\n const char *v7;\n char *v8;\n char v10[104];\n unsigned long long v11;\n v11 = __readfsqword(40u);\n if (a2 <= 0) {\n v3 = 0;\n } else {\n v2 = 0LL;\n v3 = 0;\n do {\n if (a2 > (int)v2) {\n v4 = *(const char **)(a1 + 8 * v2);\n v5 = (const char **)(a1 + 8 * v2);\n do {\n v6 = strlen(v4);\n if (v6 > 0) {\n v7 = &v4[v6 - 1];\n v8 = v10;\n do\n *v8++ = *v7--;\n while (v7 != &v4[v6 - 2 - (v6 - 1)]);\n }\n v10[v6] = 0;\n v3 += strcmp(*v5++, v10) == 0;\n } while (v5 !=\n (const char **)(a1 + 8 * (v2 + (unsigned int)(a2 - v2))));\n }\n ++v2;\n } while (v2 != a2);\n }\n __sprintf_chk(&unk_4018, 2LL, 12LL, &unk_2004, v3);\n return &unk_4018;\n}", + "ida_pseudo_norm": "void *func0(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n const char *v4;\n const char **v5;\n int v6;\n const char *v7;\n char *v8;\n char v10[104];\n unsigned long long v11;\n v11 = __readfsqword(40u);\n if (a2 <= 0) {\n v3 = 0;\n } else {\n v2 = 0LL;\n v3 = 0;\n do {\n if (a2 > (int)v2) {\n v4 = *(const char **)(a1 + 8 * v2);\n v5 = (const char **)(a1 + 8 * v2);\n do {\n v6 = strlen(v4);\n if (v6 > 0) {\n v7 = &v4[v6 - 1];\n v8 = v10;\n do\n *v8++ = *v7--;\n while (v7 != &v4[v6 - 2 - (v6 - 1)]);\n }\n v10[v6] = 0;\n v3 += strcmp(*v5++, v10) == 0;\n } while (v5 !=\n (const char **)(a1 + 8 * (v2 + (unsigned int)(a2 - v2))));\n }\n ++v2;\n } while (v2 != a2);\n }\n __sprintf_chk(&result_1, 2LL, 12LL, &unk_2004, v3);\n return &result_1;\n}" + }, + { + "index": 757, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* test_list[], int size) {\n int count = 0;\n for (int idx = 0; idx < size; idx++) {\n for (int idxn = idx; idxn < size; idxn++) {\n char reversed[100];\n int len = strlen(test_list[idx]);\n for (int i = 0; i < len; i++) {\n reversed[i] = test_list[idx][len - 1 - i];\n }\n reversed[len] = '\\0';\n if (strcmp(test_list[idxn], reversed) == 0) {\n count++;\n }\n }\n }\n static char result[12];\n sprintf(result, \"%d\", count);\n return result;\n}", + "test": "int main() {\n\n char* test1[] = {\"julia\", \"best\", \"tseb\", \"for\", \"ailuj\"};\n\n char* test2[] = {\"geeks\", \"best\", \"for\", \"skeeg\"};\n\n char* test3[] = {\"makes\", \"best\", \"sekam\", \"for\", \"rof\"};\n\n assert(strcmp(func0(test1, 5), \"2\") == 0);\n\n assert(strcmp(func0(test2, 4), \"1\") == 0);\n\n assert(strcmp(func0(test3, 5), \"2\") == 0);\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0xa8,%rsp\nmov %esi,0xc(%rsp)\nmov %fs:0x28,%rbx\nmov %rbx,0x98(%rsp)\nxor %ebx,%ebx\ntest %esi,%esi\njle 149e \nmov %esi,%eax\nmov %rdi,%r15\nlea 0x30(%rsp),%r13\nxor %r12d,%r12d\nmovq $0x0,0x18(%rsp)\nsub $0x1,%eax\nmov %rax,0x28(%rsp)\nnopw 0x0(%rax,%rax,1)\nmov 0x18(%rsp),%rax\nmov (%r15,%rax,8),%rbp\nmov %rax,0x20(%rsp)\nadd $0x1,%rax\nmov %rax,0x18(%rsp)\nmov %rax,%rbx\nmov %rbp,%rdi\nlea -0x2(%rbp),%rax\nmov %rbp,%r14\nmov %rax,0x10(%rsp)\ncallq 1090 \ntest %eax,%eax\njle 1434 \nnopw 0x0(%rax,%rax,1)\nlea -0x1(%rax),%r9d\nmovslq %eax,%rdi\nmov 0x10(%rsp),%rax\nmov %r13,%rcx\nmovslq %r9d,%rdx\nmov %r9d,%r9d\nlea (%rax,%rdi,1),%rsi\nadd %rbp,%rdx\nsub %r9,%rsi\nmovzbl (%rdx),%eax\nsub $0x1,%rdx\nadd $0x1,%rcx\nmov %al,-0x1(%rcx)\ncmp %rsi,%rdx\njne 13f0 \nmovb $0x0,0x30(%rsp,%rdi,1)\nmov %r13,%rsi\nmov %r14,%rdi\ncallq 10c0 \ncmp $0x1,%eax\nadc $0x0,%r12d\ncmp %ebx,0xc(%rsp)\njle 1440 \nmov %rbp,%rdi\nmov (%r15,%rbx,8),%r14\nadd $0x1,%rbx\ncallq 1090 \ntest %eax,%eax\njg 13d0 \nmovslq %eax,%rdi\njmp 1403 \nnopl 0x0(%rax)\nmov 0x28(%rsp),%rbx\ncmp %rbx,0x20(%rsp)\njne 1398 \nxor %eax,%eax\nmov %r12d,%r8d\nmov $0xc,%edx\nmov $0x1,%esi\nlea 0xb9e(%rip),%rcx\nlea 0x2bab(%rip),%rdi\ncallq 10d0 <__sprintf_chk@plt>\nmov 0x98(%rsp),%rax\nxor %fs:0x28,%rax\njne 14a3 \nadd $0xa8,%rsp\nlea 0x2b85(%rip),%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nxor %r12d,%r12d\njmp 1450 \ncallq 10a0 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 98h\nmov [rsp+0C8h+var_B0], rdi\nmov [rsp+0C8h+var_BC], esi\nmov rax, fs:28h\nmov [rsp+0C8h+var_40], rax\nxor eax, eax\nmovsxd rax, esi\ntest eax, eax\njle loc_14C7\nmov [rsp+0C8h+var_B8], rax\nxor ebp, ebp\nlea r12, [rsp+0C8h+s2]\nmov [rsp+0C8h+var_C8], 0\nloc_13C0:\nmov ebx, dword ptr [rsp+0C8h+var_C8]\ncmp [rsp+0C8h+var_BC], ebx\njle loc_1453\nmov rdi, [rsp+0C8h+var_C8]\nmov rcx, [rsp+0C8h+var_B0]\nmov eax, [rsp+0C8h+var_BC]\nmov rbx, [rcx+rdi*8]\nlea r15, [rcx+rdi*8]\nsub eax, edi\nadd rax, rdi\nlea r14, [rbx-2]\nlea r13, [rcx+rax*8]\nnop\nloc_13F0:\nmov rdi, rbx; s\ncall _strlen\ntest eax, eax\njle loc_14C0\nlea esi, [rax-1]\ncdqe\nmov rcx, r12\nmovsxd rdx, esi\nlea rdi, [r14+rax]\nmov esi, esi\nadd rdx, rbx\nsub rdi, rsi\nnop word ptr [rax+rax+00000000h]\nloc_1420:\nmovzx esi, byte ptr [rdx]\nsub rdx, 1\nadd rcx, 1\nmov [rcx-1], sil\ncmp rdx, rdi\njnz short loc_1420\nloc_1434:\nmov rdi, [r15]; s1\nmov rsi, r12; s2\nmov [rsp+rax+0C8h+s2], 0\ncall _strcmp\ncmp eax, 1\nadc ebp, 0\nadd r15, 8\ncmp r15, r13\njnz short loc_13F0\nloc_1453:\nadd [rsp+0C8h+var_C8], 1\nmov rbx, [rsp+0C8h+var_B8]\nmov rax, [rsp+0C8h+var_C8]\ncmp rax, rbx\njnz loc_13C0\nloc_146A:\nxor eax, eax\nmov r8d, ebp\nmov edx, 0Ch\nmov esi, 2\nlea rbx, result_1\nlea rcx, unk_2004\nmov rdi, rbx\ncall ___sprintf_chk\nmov rax, [rsp+0C8h+var_40]\nsub rax, fs:28h\njnz short loc_14CB\nadd rsp, 98h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14C0:\ncdqe\njmp loc_1434\nloc_14C7:\nxor ebp, ebp\njmp short loc_146A\nloc_14CB:\ncall ___stack_chk_fail", + "ida_pseudo": "void *__fastcall func0(__int64 a1, int a2)\n{\n unsigned int v2; // ebp\n const char *v3; // rbx\n const char **v4; // r15\n __int64 v5; // rax\n char *v6; // rcx\n const char *v7; // rdx\n char v8; // si\n const char *v9; // rdi\n __int64 i; // [rsp+0h] [rbp-C8h]\n __int64 v13; // [rsp+10h] [rbp-B8h]\n char s2[104]; // [rsp+20h] [rbp-A8h] BYREF\n unsigned __int64 v16; // [rsp+88h] [rbp-40h]\n\n v16 = __readfsqword(0x28u);\n if ( a2 <= 0 )\n {\n v2 = 0;\n }\n else\n {\n v13 = a2;\n v2 = 0;\n for ( i = 0LL; i != v13; ++i )\n {\n if ( a2 > (int)i )\n {\n v3 = *(const char **)(a1 + 8 * i);\n v4 = (const char **)(a1 + 8 * i);\n do\n {\n LODWORD(v5) = strlen(v3);\n if ( (int)v5 <= 0 )\n {\n v5 = (int)v5;\n }\n else\n {\n v5 = (int)v5;\n v6 = s2;\n v7 = &v3[(int)v5 - 1];\n do\n {\n v8 = *v7--;\n *v6++ = v8;\n }\n while ( v7 != &v3[(int)v5 - 2 - (unsigned int)(v5 - 1)] );\n }\n v9 = *v4;\n s2[v5] = 0;\n v2 += strcmp(v9, s2) == 0;\n ++v4;\n }\n while ( v4 != (const char **)(a1 + 8 * (i + (unsigned int)(a2 - i))) );\n }\n }\n }\n __sprintf_chk(&result_1, 2LL, 12LL, &unk_2004, v2);\n return &result_1;\n}", + "ida_strip_asm": "sub_1370:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 98h\nmov [rsp+0C8h+var_B0], rdi\nmov [rsp+0C8h+var_BC], esi\nmov rax, fs:28h\nmov [rsp+0C8h+var_40], rax\nxor eax, eax\nmovsxd rax, esi\ntest eax, eax\njle loc_14C7\nmov [rsp+0C8h+var_B8], rax\nxor ebp, ebp\nlea r12, [rsp+0C8h+s2]\nmov [rsp+0C8h+var_C8], 0\nloc_13C0:\nmov ebx, dword ptr [rsp+0C8h+var_C8]\ncmp [rsp+0C8h+var_BC], ebx\njle loc_1453\nmov rdi, [rsp+0C8h+var_C8]\nmov rcx, [rsp+0C8h+var_B0]\nmov eax, [rsp+0C8h+var_BC]\nmov rbx, [rcx+rdi*8]\nlea r15, [rcx+rdi*8]\nsub eax, edi\nadd rax, rdi\nlea r14, [rbx-2]\nlea r13, [rcx+rax*8]\nnop\nloc_13F0:\nmov rdi, rbx; s\ncall _strlen\ntest eax, eax\njle loc_14C0\nlea esi, [rax-1]\ncdqe\nmov rcx, r12\nmovsxd rdx, esi\nlea rdi, [r14+rax]\nmov esi, esi\nadd rdx, rbx\nsub rdi, rsi\nnop word ptr [rax+rax+00000000h]\nloc_1420:\nmovzx esi, byte ptr [rdx]\nsub rdx, 1\nadd rcx, 1\nmov [rcx-1], sil\ncmp rdx, rdi\njnz short loc_1420\nloc_1434:\nmov rdi, [r15]; s1\nmov rsi, r12; s2\nmov [rsp+rax+0C8h+s2], 0\ncall _strcmp\ncmp eax, 1\nadc ebp, 0\nadd r15, 8\ncmp r15, r13\njnz short loc_13F0\nloc_1453:\nadd [rsp+0C8h+var_C8], 1\nmov rbx, [rsp+0C8h+var_B8]\nmov rax, [rsp+0C8h+var_C8]\ncmp rax, rbx\njnz loc_13C0\nloc_146A:\nxor eax, eax\nmov r8d, ebp\nmov edx, 0Ch\nmov esi, 2\nlea rbx, unk_4018\nlea rcx, unk_2004\nmov rdi, rbx\ncall ___sprintf_chk\nmov rax, [rsp+0C8h+var_40]\nsub rax, fs:28h\njnz short loc_14CB\nadd rsp, 98h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14C0:\ncdqe\njmp loc_1434\nloc_14C7:\nxor ebp, ebp\njmp short loc_146A\nloc_14CB:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "void *__fastcall sub_1370(__int64 a1, int a2)\n{\n unsigned int v2; // ebp\n const char *v3; // rbx\n const char **v4; // r15\n __int64 v5; // rax\n char *v6; // rcx\n const char *v7; // rdx\n char v8; // si\n const char *v9; // rdi\n __int64 i; // [rsp+0h] [rbp-C8h]\n __int64 v13; // [rsp+10h] [rbp-B8h]\n char s2[104]; // [rsp+20h] [rbp-A8h] BYREF\n unsigned __int64 v16; // [rsp+88h] [rbp-40h]\n\n v16 = __readfsqword(0x28u);\n if ( a2 <= 0 )\n {\n v2 = 0;\n }\n else\n {\n v13 = a2;\n v2 = 0;\n for ( i = 0LL; i != v13; ++i )\n {\n if ( a2 > (int)i )\n {\n v3 = *(const char **)(a1 + 8 * i);\n v4 = (const char **)(a1 + 8 * i);\n do\n {\n LODWORD(v5) = strlen(v3);\n if ( (int)v5 <= 0 )\n {\n v5 = (int)v5;\n }\n else\n {\n v5 = (int)v5;\n v6 = s2;\n v7 = &v3[(int)v5 - 1];\n do\n {\n v8 = *v7--;\n *v6++ = v8;\n }\n while ( v7 != &v3[(int)v5 - 2 - (unsigned int)(v5 - 1)] );\n }\n v9 = *v4;\n s2[v5] = 0;\n v2 += strcmp(v9, s2) == 0;\n ++v4;\n }\n while ( v4 != (const char **)(a1 + 8 * (i + (unsigned int)(a2 - i))) );\n }\n }\n }\n __sprintf_chk(&unk_4018, 2LL, 12LL, &unk_2004, v2);\n return &unk_4018;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1370(long long a1, int a2) {\n unsigned int v2;\n const char *v3;\n const char **v4;\n long long v5;\n char *v6;\n const char *v7;\n char v8;\n const char *v9;\n long long i;\n long long v13;\n char s2[104];\n unsigned long long v16;\n v16 = __readfsqword(40u);\n if (a2 <= 0) {\n v2 = 0;\n } else {\n v13 = a2;\n v2 = 0;\n for (i = 0LL; i != v13; ++i) {\n if (a2 > (int)i) {\n v3 = *(const char **)(a1 + 8 * i);\n v4 = (const char **)(a1 + 8 * i);\n do {\n LODWORD(v5) = strlen(v3);\n if ((int)v5 <= 0) {\n v5 = (int)v5;\n } else {\n v5 = (int)v5;\n v6 = s2;\n v7 = &v3[(int)v5 - 1];\n do {\n v8 = *v7--;\n *v6++ = v8;\n } while (v7 != &v3[(int)v5 - 2 - (unsigned int)(v5 - 1)]);\n }\n v9 = *v4;\n s2[v5] = 0;\n v2 += strcmp(v9, s2) == 0;\n ++v4;\n } while (v4 != (const char **)(a1 + 8 * (i + (unsigned int)(a2 - i))));\n }\n }\n }\n __sprintf_chk(&unk_4018, 2LL, 12LL, &unk_2004, v2);\n return &unk_4018;\n}", + "ida_pseudo_norm": "void *func0(long long a1, int a2) {\n unsigned int v2;\n const char *v3;\n const char **v4;\n long long v5;\n char *v6;\n const char *v7;\n char v8;\n const char *v9;\n long long i;\n long long v13;\n char s2[104];\n unsigned long long v16;\n v16 = __readfsqword(40u);\n if (a2 <= 0) {\n v2 = 0;\n } else {\n v13 = a2;\n v2 = 0;\n for (i = 0LL; i != v13; ++i) {\n if (a2 > (int)i) {\n v3 = *(const char **)(a1 + 8 * i);\n v4 = (const char **)(a1 + 8 * i);\n do {\n LODWORD(v5) = strlen(v3);\n if ((int)v5 <= 0) {\n v5 = (int)v5;\n } else {\n v5 = (int)v5;\n v6 = s2;\n v7 = &v3[(int)v5 - 1];\n do {\n v8 = *v7--;\n *v6++ = v8;\n } while (v7 != &v3[(int)v5 - 2 - (unsigned int)(v5 - 1)]);\n }\n v9 = *v4;\n s2[v5] = 0;\n v2 += strcmp(v9, s2) == 0;\n ++v4;\n } while (v4 != (const char **)(a1 + 8 * (i + (unsigned int)(a2 - i))));\n }\n }\n }\n __sprintf_chk(&result_1, 2LL, 12LL, &unk_2004, v2);\n return &result_1;\n}" + }, + { + "index": 757, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* test_list[], int size) {\n int count = 0;\n for (int idx = 0; idx < size; idx++) {\n for (int idxn = idx; idxn < size; idxn++) {\n char reversed[100];\n int len = strlen(test_list[idx]);\n for (int i = 0; i < len; i++) {\n reversed[i] = test_list[idx][len - 1 - i];\n }\n reversed[len] = '\\0';\n if (strcmp(test_list[idxn], reversed) == 0) {\n count++;\n }\n }\n }\n static char result[12];\n sprintf(result, \"%d\", count);\n return result;\n}", + "test": "int main() {\n\n char* test1[] = {\"julia\", \"best\", \"tseb\", \"for\", \"ailuj\"};\n\n char* test2[] = {\"geeks\", \"best\", \"for\", \"skeeg\"};\n\n char* test3[] = {\"makes\", \"best\", \"sekam\", \"for\", \"rof\"};\n\n assert(strcmp(func0(test1, 5), \"2\") == 0);\n\n assert(strcmp(func0(test2, 4), \"1\") == 0);\n\n assert(strcmp(func0(test3, 5), \"2\") == 0);\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x98,%rsp\nmov %esi,0xc(%rsp)\nmov %fs:0x28,%rbx\nmov %rbx,0x88(%rsp)\nxor %ebx,%ebx\ntest %esi,%esi\njle 146d \nmov %esi,%eax\nmov %rdi,%r13\nlea 0x20(%rsp),%r12\nxor %ebp,%ebp\nmovq $0x0,0x10(%rsp)\nsub $0x1,%eax\nmov 0x10(%rsp),%r14\nmov %rax,0x18(%rsp)\nnopw %cs:0x0(%rax,%rax,1)\nmov 0x0(%r13,%r14,8),%rbx\nlea -0x2(%rbx),%r15\nnopl 0x0(%rax)\nmov %rbx,%rdi\ncallq 1090 \ntest %eax,%eax\njle 1468 \nlea -0x1(%rax),%r9d\nmovslq %eax,%rdi\nmov %r12,%rcx\nmovslq %r9d,%rdx\nlea (%r15,%rdi,1),%rsi\nmov %r9d,%r9d\nadd %rbx,%rdx\nsub %r9,%rsi\nnopw %cs:0x0(%rax,%rax,1)\nmovzbl (%rdx),%eax\nsub $0x1,%rdx\nadd $0x1,%rcx\nmov %al,-0x1(%rcx)\ncmp %rdx,%rsi\njne 1410 \nmovb $0x0,0x20(%rsp,%rdi,1)\nmov 0x0(%r13,%r14,8),%rdi\nmov %r12,%rsi\ncallq 10c0 \ncmp $0x1,%eax\nadc $0x0,%ebp\nadd $0x1,%r14\ncmp %r14d,0xc(%rsp)\njg 13e0 \nmov 0x10(%rsp),%rbx\nlea 0x1(%rbx),%rax\ncmp %rbx,0x18(%rsp)\nje 146f \nmov %rax,0x10(%rsp)\nmov %rax,%r14\njmpq 13d0 \nnopl 0x0(%rax,%rax,1)\nmovslq %eax,%rdi\njmp 1423 \nxor %ebp,%ebp\nxor %eax,%eax\nmov %ebp,%r8d\nmov $0xc,%edx\nmov $0x1,%esi\nlea 0xb7f(%rip),%rcx\nlea 0x2b8c(%rip),%rdi\ncallq 10d0 <__sprintf_chk@plt>\nmov 0x88(%rsp),%rax\nxor %fs:0x28,%rax\njne 14bd \nadd $0x98,%rsp\nlea 0x2b66(%rip),%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\ncallq 10a0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\nxor ebp, ebp\npush rbx\nsub rsp, 98h\nmov [rsp+0C8h+var_BC], esi\nmov rax, fs:28h\nmov [rsp+0C8h+var_40], rax\nxor eax, eax\ntest esi, esi\njle loc_145D\nmovsxd rax, [rsp+0C8h+var_BC]\nmov r13, rdi\nxor ebp, ebp\nlea r12, [rsp+0C8h+s2]\nmov [rsp+0C8h+var_B8], 0\nmov [rsp+0C8h+var_B0], rax\nnop dword ptr [rax+rax+00h]\nloc_13C8:\nmov r14, [rsp+0C8h+var_B8]\nmov rbx, [r13+r14*8+0]\nlea r15, [rbx-2]\nnop word ptr [rax+rax+00000000h]\nloc_13E0:\nmov rdi, rbx; s\ncall _strlen\ntest eax, eax\njle loc_14B0\nlea esi, [rax-1]\ncdqe\nmov rcx, r12\nmovsxd rdx, esi\nlea rdi, [r15+rax]\nmov esi, esi\nadd rdx, rbx\nsub rdi, rsi\nnop word ptr [rax+rax+00000000h]\nloc_1410:\nmovzx esi, byte ptr [rdx]\nsub rdx, 1\nadd rcx, 1\nmov [rcx-1], sil\ncmp rdi, rdx\njnz short loc_1410\nloc_1424:\nmov rdi, [r13+r14*8+0]; s1\nmov rsi, r12; s2\nmov [rsp+rax+0C8h+s2], 0\ncall _strcmp\ncmp eax, 1\nadc ebp, 0\nadd r14, 1\ncmp [rsp+0C8h+var_BC], r14d\njg short loc_13E0\nadd [rsp+0C8h+var_B8], 1\nmov rax, [rsp+0C8h+var_B8]\ncmp [rsp+0C8h+var_B0], rax\njnz loc_13C8\nloc_145D:\nxor eax, eax\nmov r8d, ebp\nmov edx, 0Ch\nmov esi, 2\nlea rbx, result_1\nlea rcx, unk_2004\nmov rdi, rbx\ncall ___sprintf_chk\nmov rax, [rsp+0C8h+var_40]\nsub rax, fs:28h\njnz short loc_14B7\nadd rsp, 98h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14B0:\ncdqe\njmp loc_1424\nloc_14B7:\ncall ___stack_chk_fail", + "ida_pseudo": "void *__fastcall func0(__int64 a1, int a2)\n{\n unsigned int v2; // ebp\n __int64 v4; // r14\n const char *v5; // rbx\n __int64 v6; // rax\n char *v7; // rcx\n const char *v8; // rdx\n char v9; // si\n const char *v10; // rdi\n __int64 i; // [rsp+10h] [rbp-B8h]\n char s2[104]; // [rsp+20h] [rbp-A8h] BYREF\n unsigned __int64 v15; // [rsp+88h] [rbp-40h]\n\n v2 = 0;\n v15 = __readfsqword(0x28u);\n if ( a2 > 0 )\n {\n v2 = 0;\n for ( i = 0LL; i != a2; ++i )\n {\n v4 = i;\n v5 = *(const char **)(a1 + 8 * i);\n do\n {\n LODWORD(v6) = strlen(v5);\n if ( (int)v6 <= 0 )\n {\n v6 = (int)v6;\n }\n else\n {\n v6 = (int)v6;\n v7 = s2;\n v8 = &v5[(int)v6 - 1];\n do\n {\n v9 = *v8--;\n *v7++ = v9;\n }\n while ( &v5[(int)v6 - 2 - (unsigned int)(v6 - 1)] != v8 );\n }\n v10 = *(const char **)(a1 + 8 * v4);\n s2[v6] = 0;\n v2 += strcmp(v10, s2) == 0;\n ++v4;\n }\n while ( a2 > (int)v4 );\n }\n }\n __sprintf_chk(&result_1, 2LL, 12LL, &unk_2004, v2);\n return &result_1;\n}", + "ida_strip_asm": "sub_1370:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\nxor ebp, ebp\npush rbx\nsub rsp, 98h\nmov [rsp+0C8h+var_BC], esi\nmov rax, fs:28h\nmov [rsp+0C8h+var_40], rax\nxor eax, eax\ntest esi, esi\njle loc_145D\nmovsxd rax, [rsp+0C8h+var_BC]\nmov r13, rdi\nxor ebp, ebp\nlea r12, [rsp+0C8h+s2]\nmov [rsp+0C8h+var_B8], 0\nmov [rsp+0C8h+var_B0], rax\nnop dword ptr [rax+rax+00h]\nloc_13C8:\nmov r14, [rsp+0C8h+var_B8]\nmov rbx, [r13+r14*8+0]\nlea r15, [rbx-2]\nnop word ptr [rax+rax+00000000h]\nloc_13E0:\nmov rdi, rbx; s\ncall _strlen\ntest eax, eax\njle loc_14B0\nlea esi, [rax-1]\ncdqe\nmov rcx, r12\nmovsxd rdx, esi\nlea rdi, [r15+rax]\nmov esi, esi\nadd rdx, rbx\nsub rdi, rsi\nnop word ptr [rax+rax+00000000h]\nloc_1410:\nmovzx esi, byte ptr [rdx]\nsub rdx, 1\nadd rcx, 1\nmov [rcx-1], sil\ncmp rdi, rdx\njnz short loc_1410\nloc_1424:\nmov rdi, [r13+r14*8+0]; s1\nmov rsi, r12; s2\nmov [rsp+rax+0C8h+s2], 0\ncall _strcmp\ncmp eax, 1\nadc ebp, 0\nadd r14, 1\ncmp [rsp+0C8h+var_BC], r14d\njg short loc_13E0\nadd [rsp+0C8h+var_B8], 1\nmov rax, [rsp+0C8h+var_B8]\ncmp [rsp+0C8h+var_B0], rax\njnz loc_13C8\nloc_145D:\nxor eax, eax\nmov r8d, ebp\nmov edx, 0Ch\nmov esi, 2\nlea rbx, unk_4018\nlea rcx, unk_2004\nmov rdi, rbx\ncall ___sprintf_chk\nmov rax, [rsp+0C8h+var_40]\nsub rax, fs:28h\njnz short loc_14B7\nadd rsp, 98h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14B0:\ncdqe\njmp loc_1424\nloc_14B7:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "void *__fastcall sub_1370(__int64 a1, int a2)\n{\n unsigned int v2; // ebp\n __int64 v4; // r14\n const char *v5; // rbx\n __int64 v6; // rax\n char *v7; // rcx\n const char *v8; // rdx\n char v9; // si\n const char *v10; // rdi\n __int64 i; // [rsp+10h] [rbp-B8h]\n char s2[104]; // [rsp+20h] [rbp-A8h] BYREF\n unsigned __int64 v15; // [rsp+88h] [rbp-40h]\n\n v2 = 0;\n v15 = __readfsqword(0x28u);\n if ( a2 > 0 )\n {\n v2 = 0;\n for ( i = 0LL; i != a2; ++i )\n {\n v4 = i;\n v5 = *(const char **)(a1 + 8 * i);\n do\n {\n LODWORD(v6) = strlen(v5);\n if ( (int)v6 <= 0 )\n {\n v6 = (int)v6;\n }\n else\n {\n v6 = (int)v6;\n v7 = s2;\n v8 = &v5[(int)v6 - 1];\n do\n {\n v9 = *v8--;\n *v7++ = v9;\n }\n while ( &v5[(int)v6 - 2 - (unsigned int)(v6 - 1)] != v8 );\n }\n v10 = *(const char **)(a1 + 8 * v4);\n s2[v6] = 0;\n v2 += strcmp(v10, s2) == 0;\n ++v4;\n }\n while ( a2 > (int)v4 );\n }\n }\n __sprintf_chk(&unk_4018, 2LL, 12LL, &unk_2004, v2);\n return &unk_4018;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1370(long long a1, int a2) {\n unsigned int v2;\n long long v4;\n const char *v5;\n long long v6;\n char *v7;\n const char *v8;\n char v9;\n const char *v10;\n long long i;\n char s2[104];\n unsigned long long v15;\n v2 = 0;\n v15 = __readfsqword(40u);\n if (a2 > 0) {\n v2 = 0;\n for (i = 0LL; i != a2; ++i) {\n v4 = i;\n v5 = *(const char **)(a1 + 8 * i);\n do {\n LODWORD(v6) = strlen(v5);\n if ((int)v6 <= 0) {\n v6 = (int)v6;\n } else {\n v6 = (int)v6;\n v7 = s2;\n v8 = &v5[(int)v6 - 1];\n do {\n v9 = *v8--;\n *v7++ = v9;\n } while (&v5[(int)v6 - 2 - (unsigned int)(v6 - 1)] != v8);\n }\n v10 = *(const char **)(a1 + 8 * v4);\n s2[v6] = 0;\n v2 += strcmp(v10, s2) == 0;\n ++v4;\n } while (a2 > (int)v4);\n }\n }\n __sprintf_chk(&unk_4018, 2LL, 12LL, &unk_2004, v2);\n return &unk_4018;\n}", + "ida_pseudo_norm": "void *func0(long long a1, int a2) {\n unsigned int v2;\n long long v4;\n const char *v5;\n long long v6;\n char *v7;\n const char *v8;\n char v9;\n const char *v10;\n long long i;\n char s2[104];\n unsigned long long v15;\n v2 = 0;\n v15 = __readfsqword(40u);\n if (a2 > 0) {\n v2 = 0;\n for (i = 0LL; i != a2; ++i) {\n v4 = i;\n v5 = *(const char **)(a1 + 8 * i);\n do {\n LODWORD(v6) = strlen(v5);\n if ((int)v6 <= 0) {\n v6 = (int)v6;\n } else {\n v6 = (int)v6;\n v7 = s2;\n v8 = &v5[(int)v6 - 1];\n do {\n v9 = *v8--;\n *v7++ = v9;\n } while (&v5[(int)v6 - 2 - (unsigned int)(v6 - 1)] != v8);\n }\n v10 = *(const char **)(a1 + 8 * v4);\n s2[v6] = 0;\n v2 += strcmp(v10, s2) == 0;\n ++v4;\n } while (a2 > (int)v4);\n }\n }\n __sprintf_chk(&result_1, 2LL, 12LL, &unk_2004, v2);\n return &result_1;\n}" + }, + { + "index": 758, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct hash{\n\n void* key;\n\n int value;\n\n size_t key_size;\n\n struct hash* next;\n\n} HashItem;\n\n\n\n\n\nint hash_function(void* key, size_t key_size, int buckets) {\n\n unsigned char* p = (unsigned char*) key;\n\n unsigned long hash = 5381;\n\n for (size_t i = 0; i < key_size; i++) {\n\n hash = ((hash << 5) + hash) + p[i];\n\n }\n\n return hash % buckets;\n\n}\n\n\n\nvoid insert_or_increment(HashItem** hashtable, int buckets, void* key, size_t key_size) {\n\n int bucket = hash_function(key, key_size, buckets);\n\n HashItem* item = hashtable[bucket];\n\n while (item) {\n\n if (item->key_size == key_size && memcmp(item->key, key, key_size) == 0) {\n\n item->value += 1;\n\n return;\n\n }\n\n item = item->next;\n\n }\n\n HashItem* new_item = malloc(sizeof(HashItem));\n\n new_item->key = malloc(key_size);\n\n memcpy(new_item->key, key, key_size);\n\n new_item->key_size = key_size;\n\n new_item->value = 1;\n\n new_item->next = hashtable[bucket];\n\n hashtable[bucket] = new_item;\n\n}\n\n\n\n\n\nvoid free_hashtable(HashItem** hashtable, int buckets) {\n\n for (int i = 0; i < buckets; i++) {\n\n HashItem* item = hashtable[i];\n\n while (item) {\n\n HashItem* next = item->next;\n\n free(item->key);\n\n free(item);\n\n item = next;\n\n }\n\n }\n\n free(hashtable);\n\n}\n\n\n\n", + "func": "HashItem** func0(int list1[][50], int lengths[], int list1_size) {\n const int buckets = 10;\n HashItem** hashtable = calloc(buckets, sizeof(HashItem*));\n for (int i = 0; i < list1_size; i++) {\n insert_or_increment(hashtable, buckets, list1[i], lengths[i] * sizeof(int));\n }\n return hashtable;\n}", + "test": "int main() {\n\n int list1[][50] = {{1, 3}, {5, 7}, {1, 3}, {13, 15, 17}, {5, 7}, {9, 11}};\n\n int lengths1[] = {2, 2, 2, 3, 2, 2};\n\n int list1_size = 6;\n\n HashItem** result1 = func0(list1, lengths1, list1_size);\n\n assert(result1[hash_function((int[]){1, 3}, sizeof(int)*2, 10)]->value == 2);\n\n assert(result1[hash_function((int[]){5, 7}, sizeof(int)*2, 10)]->value == 2);\n\n assert(result1[hash_function((int[]){13, 15, 17}, sizeof(int)*3, 10)]->value == 1);\n\n assert(result1[hash_function((int[]){9, 11}, sizeof(int)*2, 10)]->value == 1);\n\n free_hashtable(result1, 10);\n\n\n\n // Additional test cases for other lists like `list2`, `list3` can be written similarly...\n\n \n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %edx,-0x24(%rbp)\nmovl $0xa,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncltq\nmov $0x8,%esi\nmov %rax,%rdi\ncallq 10f0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0x10(%rbp)\njmp 14e1 \nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x10(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0xc(%rbp),%esi\nmov -0x8(%rbp),%rax\nmov %rax,%rdi\ncallq 1287 \naddl $0x1,-0x10(%rbp)\nmov -0x10(%rbp),%eax\ncmp -0x24(%rbp),%eax\njl 1485 \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_C], 0Ah\nmov eax, [rbp+var_C]\ncdqe\nmov esi, 8; size\nmov rdi, rax; nmemb\ncall _calloc\nmov [rbp+var_8], rax\nmov [rbp+var_10], 0\njmp short loc_14E4\nloc_1488:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rcx, ds:0[rax*4]\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov esi, [rbp+var_C]\nmov rax, [rbp+var_8]\nmov rdi, rax\ncall insert_or_increment\nadd [rbp+var_10], 1\nloc_14E4:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_24]\njl short loc_1488\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "void *__fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n int i; // [rsp+20h] [rbp-10h]\n void *v6; // [rsp+28h] [rbp-8h]\n\n v6 = calloc(0xAuLL, 8uLL);\n for ( i = 0; i < a3; ++i )\n insert_or_increment(v6, 10LL, a1 + 200LL * i, 4LL * *(int *)(4LL * i + a2));\n return v6;\n}", + "ida_strip_asm": "sub_144B:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_C], 0Ah\nmov eax, [rbp+var_C]\ncdqe\nmov esi, 8; size\nmov rdi, rax; nmemb\ncall _calloc\nmov [rbp+var_8], rax\nmov [rbp+var_10], 0\njmp short loc_14E4\nloc_1488:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rcx, ds:0[rax*4]\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov esi, [rbp+var_C]\nmov rax, [rbp+var_8]\nmov rdi, rax\ncall sub_128A\nadd [rbp+var_10], 1\nloc_14E4:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_24]\njl short loc_1488\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "void *__fastcall sub_144B(__int64 a1, __int64 a2, int a3)\n{\n int i; // [rsp+20h] [rbp-10h]\n void *v6; // [rsp+28h] [rbp-8h]\n\n v6 = calloc(0xAuLL, 8uLL);\n for ( i = 0; i < a3; ++i )\n sub_128A(v6, 10LL, a1 + 200LL * i, 4LL * *(int *)(4LL * i + a2));\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_144B(long long a1, long long a2, int a3) {\n int i;\n void *v6;\n v6 = calloc(10uLL, 8uLL);\n for (i = 0; i < a3; ++i)\n sub_128A(v6, 10LL, a1 + 200LL * i, 4LL * *(int *)(4LL * i + a2));\n return v6;\n}", + "ida_pseudo_norm": "void *func0(long long a1, long long a2, int a3) {\n int i;\n void *v6;\n v6 = calloc(10uLL, 8uLL);\n for (i = 0; i < a3; ++i)\n insert_or_increment(v6, 10LL, a1 + 200LL * i, 4LL * *(int *)(4LL * i + a2));\n return v6;\n}" + }, + { + "index": 758, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct hash{\n\n void* key;\n\n int value;\n\n size_t key_size;\n\n struct hash* next;\n\n} HashItem;\n\n\n\n\n\nint hash_function(void* key, size_t key_size, int buckets) {\n\n unsigned char* p = (unsigned char*) key;\n\n unsigned long hash = 5381;\n\n for (size_t i = 0; i < key_size; i++) {\n\n hash = ((hash << 5) + hash) + p[i];\n\n }\n\n return hash % buckets;\n\n}\n\n\n\nvoid insert_or_increment(HashItem** hashtable, int buckets, void* key, size_t key_size) {\n\n int bucket = hash_function(key, key_size, buckets);\n\n HashItem* item = hashtable[bucket];\n\n while (item) {\n\n if (item->key_size == key_size && memcmp(item->key, key, key_size) == 0) {\n\n item->value += 1;\n\n return;\n\n }\n\n item = item->next;\n\n }\n\n HashItem* new_item = malloc(sizeof(HashItem));\n\n new_item->key = malloc(key_size);\n\n memcpy(new_item->key, key, key_size);\n\n new_item->key_size = key_size;\n\n new_item->value = 1;\n\n new_item->next = hashtable[bucket];\n\n hashtable[bucket] = new_item;\n\n}\n\n\n\n\n\nvoid free_hashtable(HashItem** hashtable, int buckets) {\n\n for (int i = 0; i < buckets; i++) {\n\n HashItem* item = hashtable[i];\n\n while (item) {\n\n HashItem* next = item->next;\n\n free(item->key);\n\n free(item);\n\n item = next;\n\n }\n\n }\n\n free(hashtable);\n\n}\n\n\n\n", + "func": "HashItem** func0(int list1[][50], int lengths[], int list1_size) {\n const int buckets = 10;\n HashItem** hashtable = calloc(buckets, sizeof(HashItem*));\n for (int i = 0; i < list1_size; i++) {\n insert_or_increment(hashtable, buckets, list1[i], lengths[i] * sizeof(int));\n }\n return hashtable;\n}", + "test": "int main() {\n\n int list1[][50] = {{1, 3}, {5, 7}, {1, 3}, {13, 15, 17}, {5, 7}, {9, 11}};\n\n int lengths1[] = {2, 2, 2, 3, 2, 2};\n\n int list1_size = 6;\n\n HashItem** result1 = func0(list1, lengths1, list1_size);\n\n assert(result1[hash_function((int[]){1, 3}, sizeof(int)*2, 10)]->value == 2);\n\n assert(result1[hash_function((int[]){5, 7}, sizeof(int)*2, 10)]->value == 2);\n\n assert(result1[hash_function((int[]){13, 15, 17}, sizeof(int)*3, 10)]->value == 1);\n\n assert(result1[hash_function((int[]){9, 11}, sizeof(int)*2, 10)]->value == 1);\n\n free_hashtable(result1, 10);\n\n\n\n // Additional test cases for other lists like `list2`, `list3` can be written similarly...\n\n \n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbp\nmov %rsi,%r14\nmov %edx,%r13d\nmov $0x8,%esi\nmov $0xa,%edi\ncallq 10f0 \nmov %rax,%r12\ntest %r13d,%r13d\njle 13aa \nmov %r14,%rbx\nlea -0x1(%r13),%eax\nlea 0x4(%r14,%rax,4),%r13\nmovslq (%rbx),%rcx\nshl $0x2,%rcx\nmov %rbp,%rdx\nmov $0xa,%esi\nmov %r12,%rdi\ncallq 124c \nadd $0x4,%rbx\nadd $0xc8,%rbp\ncmp %r13,%rbx\njne 1383 \nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbp, rdi\nmov r14, rsi\nmov r13d, edx\nmov esi, 8; size\nmov edi, 0Ah; nmemb\ncall _calloc\nmov r12, rax\ntest r13d, r13d\njle short loc_13A5\nmov rbx, r14\nmovsxd r13, r13d\nlea r13, [r14+r13*4]\nloc_137E:\nmovsxd rcx, dword ptr [rbx]\nshl rcx, 2\nmov rdx, rbp\nmov esi, 0Ah\nmov rdi, r12\ncall insert_or_increment\nadd rbx, 4\nadd rbp, 0C8h\ncmp rbx, r13\njnz short loc_137E\nloc_13A5:\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "void *__fastcall func0(__int64 a1, int *a2, int a3)\n{\n void *v5; // r12\n int *v6; // rbx\n int *v7; // r13\n\n v5 = calloc(0xAuLL, 8uLL);\n if ( a3 > 0 )\n {\n v6 = a2;\n v7 = &a2[a3];\n do\n {\n insert_or_increment(v5, 10LL, a1, 4LL * *v6++);\n a1 += 200LL;\n }\n while ( v6 != v7 );\n }\n return v5;\n}", + "ida_strip_asm": "sub_1348:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbp, rdi\nmov r14, rsi\nmov r13d, edx\nmov esi, 8; size\nmov edi, 0Ah; nmemb\ncall _calloc\nmov r12, rax\ntest r13d, r13d\njle short loc_13A5\nmov rbx, r14\nmovsxd r13, r13d\nlea r13, [r14+r13*4]\nloc_137E:\nmovsxd rcx, dword ptr [rbx]\nshl rcx, 2\nmov rdx, rbp\nmov esi, 0Ah\nmov rdi, r12\ncall sub_124B\nadd rbx, 4\nadd rbp, 0C8h\ncmp rbx, r13\njnz short loc_137E\nloc_13A5:\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "void *__fastcall sub_1348(__int64 a1, int *a2, int a3)\n{\n void *v5; // r12\n int *v6; // rbx\n int *v7; // r13\n\n v5 = calloc(0xAuLL, 8uLL);\n if ( a3 > 0 )\n {\n v6 = a2;\n v7 = &a2[a3];\n do\n {\n sub_124B(v5, 10LL, a1, 4LL * *v6++);\n a1 += 200LL;\n }\n while ( v6 != v7 );\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1348(long long a1, int *a2, int a3) {\n void *v5;\n int *v6;\n int *v7;\n v5 = calloc(10uLL, 8uLL);\n if (a3 > 0) {\n v6 = a2;\n v7 = &a2[a3];\n do {\n sub_124B(v5, 10LL, a1, 4LL * *v6++);\n a1 += 200LL;\n } while (v6 != v7);\n }\n return v5;\n}", + "ida_pseudo_norm": "void *func0(long long a1, int *a2, int a3) {\n void *v5;\n int *v6;\n int *v7;\n v5 = calloc(10uLL, 8uLL);\n if (a3 > 0) {\n v6 = a2;\n v7 = &a2[a3];\n do {\n insert_or_increment(v5, 10LL, a1, 4LL * *v6++);\n a1 += 200LL;\n } while (v6 != v7);\n }\n return v5;\n}" + }, + { + "index": 758, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct hash{\n\n void* key;\n\n int value;\n\n size_t key_size;\n\n struct hash* next;\n\n} HashItem;\n\n\n\n\n\nint hash_function(void* key, size_t key_size, int buckets) {\n\n unsigned char* p = (unsigned char*) key;\n\n unsigned long hash = 5381;\n\n for (size_t i = 0; i < key_size; i++) {\n\n hash = ((hash << 5) + hash) + p[i];\n\n }\n\n return hash % buckets;\n\n}\n\n\n\nvoid insert_or_increment(HashItem** hashtable, int buckets, void* key, size_t key_size) {\n\n int bucket = hash_function(key, key_size, buckets);\n\n HashItem* item = hashtable[bucket];\n\n while (item) {\n\n if (item->key_size == key_size && memcmp(item->key, key, key_size) == 0) {\n\n item->value += 1;\n\n return;\n\n }\n\n item = item->next;\n\n }\n\n HashItem* new_item = malloc(sizeof(HashItem));\n\n new_item->key = malloc(key_size);\n\n memcpy(new_item->key, key, key_size);\n\n new_item->key_size = key_size;\n\n new_item->value = 1;\n\n new_item->next = hashtable[bucket];\n\n hashtable[bucket] = new_item;\n\n}\n\n\n\n\n\nvoid free_hashtable(HashItem** hashtable, int buckets) {\n\n for (int i = 0; i < buckets; i++) {\n\n HashItem* item = hashtable[i];\n\n while (item) {\n\n HashItem* next = item->next;\n\n free(item->key);\n\n free(item);\n\n item = next;\n\n }\n\n }\n\n free(hashtable);\n\n}\n\n\n\n", + "func": "HashItem** func0(int list1[][50], int lengths[], int list1_size) {\n const int buckets = 10;\n HashItem** hashtable = calloc(buckets, sizeof(HashItem*));\n for (int i = 0; i < list1_size; i++) {\n insert_or_increment(hashtable, buckets, list1[i], lengths[i] * sizeof(int));\n }\n return hashtable;\n}", + "test": "int main() {\n\n int list1[][50] = {{1, 3}, {5, 7}, {1, 3}, {13, 15, 17}, {5, 7}, {9, 11}};\n\n int lengths1[] = {2, 2, 2, 3, 2, 2};\n\n int list1_size = 6;\n\n HashItem** result1 = func0(list1, lengths1, list1_size);\n\n assert(result1[hash_function((int[]){1, 3}, sizeof(int)*2, 10)]->value == 2);\n\n assert(result1[hash_function((int[]){5, 7}, sizeof(int)*2, 10)]->value == 2);\n\n assert(result1[hash_function((int[]){13, 15, 17}, sizeof(int)*3, 10)]->value == 1);\n\n assert(result1[hash_function((int[]){9, 11}, sizeof(int)*2, 10)]->value == 1);\n\n free_hashtable(result1, 10);\n\n\n\n // Additional test cases for other lists like `list2`, `list3` can be written similarly...\n\n \n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov %edx,%r13d\npush %r12\npush %rbp\nmov %rdi,%rbp\nmov $0xa,%edi\npush %rbx\nmov %rsi,%rbx\nmov $0x8,%esi\nsub $0x8,%rsp\ncallq 10f0 \nmov %rax,%r12\ntest %r13d,%r13d\njle 1747 \nlea -0x1(%r13),%eax\nlea 0x4(%rbx,%rax,4),%r13\nnopw 0x0(%rax,%rax,1)\nmovslq (%rbx),%rcx\nmov %rbp,%rdx\nmov $0xa,%esi\nmov %r12,%rdi\nadd $0x4,%rbx\nadd $0xc8,%rbp\nshl $0x2,%rcx\ncallq 1580 \ncmp %r13,%rbx\njne 1720 \nadd $0x8,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r13\nmovsxd r13, edx\npush r12\npush rbp\nmov rbp, rdi\nmov edi, 0Ah; nmemb\npush rbx\nmov rbx, rsi\nmov esi, 8; size\nsub rsp, 8\ncall _calloc\nmov r12, rax\ntest r13d, r13d\njle short loc_16DF\nlea r13, [rbx+r13*4]\nnop word ptr [rax+rax+00h]\nloc_16B8:\nmovsxd rcx, dword ptr [rbx]\nmov rdx, rbp\nmov esi, 0Ah\nmov rdi, r12\nadd rbx, 4\nadd rbp, 0C8h\nshl rcx, 2\ncall insert_or_increment\ncmp rbx, r13\njnz short loc_16B8\nloc_16DF:\nadd rsp, 8\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "void *__fastcall func0(__int64 a1, int *a2, int a3)\n{\n __int64 v3; // r13\n int *v5; // rbx\n void *v6; // r12\n int *v7; // r13\n __int64 v8; // rcx\n __int64 v9; // rdx\n\n v3 = a3;\n v5 = a2;\n v6 = calloc(0xAuLL, 8uLL);\n if ( (int)v3 > 0 )\n {\n v7 = &a2[v3];\n do\n {\n v8 = *v5;\n v9 = a1;\n ++v5;\n a1 += 200LL;\n insert_or_increment(v6, 10LL, v9, 4 * v8);\n }\n while ( v5 != v7 );\n }\n return v6;\n}", + "ida_strip_asm": "sub_1680:\nendbr64\npush r13\nmovsxd r13, edx\npush r12\npush rbp\nmov rbp, rdi\nmov edi, 0Ah; nmemb\npush rbx\nmov rbx, rsi\nmov esi, 8; size\nsub rsp, 8\ncall _calloc\nmov r12, rax\ntest r13d, r13d\njle short loc_16DF\nlea r13, [rbx+r13*4]\nnop word ptr [rax+rax+00h]\nloc_16B8:\nmovsxd rcx, dword ptr [rbx]\nmov rdx, rbp\nmov esi, 0Ah\nmov rdi, r12\nadd rbx, 4\nadd rbp, 0C8h\nshl rcx, 2\ncall sub_1520\ncmp rbx, r13\njnz short loc_16B8\nloc_16DF:\nadd rsp, 8\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "void *__fastcall sub_1680(__int64 a1, int *a2, int a3)\n{\n __int64 v3; // r13\n int *v5; // rbx\n void *v6; // r12\n int *v7; // r13\n __int64 v8; // rcx\n __int64 v9; // rdx\n\n v3 = a3;\n v5 = a2;\n v6 = calloc(0xAuLL, 8uLL);\n if ( (int)v3 > 0 )\n {\n v7 = &a2[v3];\n do\n {\n v8 = *v5;\n v9 = a1;\n ++v5;\n a1 += 200LL;\n sub_1520(v6, 10LL, v9, 4 * v8);\n }\n while ( v5 != v7 );\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1680(long long a1, int *a2, int a3) {\n long long v3;\n int *v5;\n void *v6;\n int *v7;\n long long v8;\n long long v9;\n v3 = a3;\n v5 = a2;\n v6 = calloc(10uLL, 8uLL);\n if ((int)v3 > 0) {\n v7 = &a2[v3];\n do {\n v8 = *v5;\n v9 = a1;\n ++v5;\n a1 += 200LL;\n sub_1520(v6, 10LL, v9, 4 * v8);\n } while (v5 != v7);\n }\n return v6;\n}", + "ida_pseudo_norm": "void *func0(long long a1, int *a2, int a3) {\n long long v3;\n int *v5;\n void *v6;\n int *v7;\n long long v8;\n long long v9;\n v3 = a3;\n v5 = a2;\n v6 = calloc(10uLL, 8uLL);\n if ((int)v3 > 0) {\n v7 = &a2[v3];\n do {\n v8 = *v5;\n v9 = a1;\n ++v5;\n a1 += 200LL;\n insert_or_increment(v6, 10LL, v9, 4 * v8);\n } while (v5 != v7);\n }\n return v6;\n}" + }, + { + "index": 758, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct hash{\n\n void* key;\n\n int value;\n\n size_t key_size;\n\n struct hash* next;\n\n} HashItem;\n\n\n\n\n\nint hash_function(void* key, size_t key_size, int buckets) {\n\n unsigned char* p = (unsigned char*) key;\n\n unsigned long hash = 5381;\n\n for (size_t i = 0; i < key_size; i++) {\n\n hash = ((hash << 5) + hash) + p[i];\n\n }\n\n return hash % buckets;\n\n}\n\n\n\nvoid insert_or_increment(HashItem** hashtable, int buckets, void* key, size_t key_size) {\n\n int bucket = hash_function(key, key_size, buckets);\n\n HashItem* item = hashtable[bucket];\n\n while (item) {\n\n if (item->key_size == key_size && memcmp(item->key, key, key_size) == 0) {\n\n item->value += 1;\n\n return;\n\n }\n\n item = item->next;\n\n }\n\n HashItem* new_item = malloc(sizeof(HashItem));\n\n new_item->key = malloc(key_size);\n\n memcpy(new_item->key, key, key_size);\n\n new_item->key_size = key_size;\n\n new_item->value = 1;\n\n new_item->next = hashtable[bucket];\n\n hashtable[bucket] = new_item;\n\n}\n\n\n\n\n\nvoid free_hashtable(HashItem** hashtable, int buckets) {\n\n for (int i = 0; i < buckets; i++) {\n\n HashItem* item = hashtable[i];\n\n while (item) {\n\n HashItem* next = item->next;\n\n free(item->key);\n\n free(item);\n\n item = next;\n\n }\n\n }\n\n free(hashtable);\n\n}\n\n\n\n", + "func": "HashItem** func0(int list1[][50], int lengths[], int list1_size) {\n const int buckets = 10;\n HashItem** hashtable = calloc(buckets, sizeof(HashItem*));\n for (int i = 0; i < list1_size; i++) {\n insert_or_increment(hashtable, buckets, list1[i], lengths[i] * sizeof(int));\n }\n return hashtable;\n}", + "test": "int main() {\n\n int list1[][50] = {{1, 3}, {5, 7}, {1, 3}, {13, 15, 17}, {5, 7}, {9, 11}};\n\n int lengths1[] = {2, 2, 2, 3, 2, 2};\n\n int list1_size = 6;\n\n HashItem** result1 = func0(list1, lengths1, list1_size);\n\n assert(result1[hash_function((int[]){1, 3}, sizeof(int)*2, 10)]->value == 2);\n\n assert(result1[hash_function((int[]){5, 7}, sizeof(int)*2, 10)]->value == 2);\n\n assert(result1[hash_function((int[]){13, 15, 17}, sizeof(int)*3, 10)]->value == 1);\n\n assert(result1[hash_function((int[]){9, 11}, sizeof(int)*2, 10)]->value == 1);\n\n free_hashtable(result1, 10);\n\n\n\n // Additional test cases for other lists like `list2`, `list3` can be written similarly...\n\n \n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov %edx,%r13d\npush %r12\npush %rbp\nmov %rdi,%rbp\nmov $0xa,%edi\npush %rbx\nmov %rsi,%rbx\nmov $0x8,%esi\nsub $0x8,%rsp\ncallq 10f0 \nmov %rax,%r12\ntest %r13d,%r13d\njle 17d7 \nlea -0x1(%r13),%eax\nlea 0x4(%rbx,%rax,4),%r13\nnopw 0x0(%rax,%rax,1)\nmovslq (%rbx),%rcx\nmov %rbp,%rdx\nmov $0xa,%esi\nmov %r12,%rdi\nadd $0x4,%rbx\nadd $0xc8,%rbp\nshl $0x2,%rcx\ncallq 1610 \ncmp %rbx,%r13\njne 17b0 \nadd $0x8,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r13\nmovsxd r13, edx\npush r12\npush rbp\nmov rbp, rdi\nmov edi, 0Ah; nmemb\npush rbx\nmov rbx, rsi\nmov esi, 8; size\nsub rsp, 8\ncall _calloc\nmov r12, rax\ntest r13d, r13d\njle short loc_159F\nlea r13, [rbx+r13*4]\nnop word ptr [rax+rax+00h]\nloc_1578:\nmovsxd rcx, dword ptr [rbx]\nmov rdx, rbp\nmov esi, 0Ah\nmov rdi, r12\nadd rbx, 4\nadd rbp, 0C8h\nshl rcx, 2\ncall insert_or_increment\ncmp r13, rbx\njnz short loc_1578\nloc_159F:\nadd rsp, 8\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "void *__fastcall func0(__int64 a1, int *a2, int a3)\n{\n __int64 v3; // r13\n int *v5; // rbx\n void *v6; // r12\n int *v7; // r13\n __int64 v8; // rcx\n __int64 v9; // rdx\n\n v3 = a3;\n v5 = a2;\n v6 = calloc(0xAuLL, 8uLL);\n if ( (int)v3 > 0 )\n {\n v7 = &a2[v3];\n do\n {\n v8 = *v5;\n v9 = a1;\n ++v5;\n a1 += 200LL;\n insert_or_increment(v6, 10LL, v9, 4 * v8);\n }\n while ( v7 != v5 );\n }\n return v6;\n}", + "ida_strip_asm": "sub_1540:\nendbr64\npush r13\nmovsxd r13, edx\npush r12\npush rbp\nmov rbp, rdi\nmov edi, 0Ah; nmemb\npush rbx\nmov rbx, rsi\nmov esi, 8; size\nsub rsp, 8\ncall _calloc\nmov r12, rax\ntest r13d, r13d\njle short loc_159F\nlea r13, [rbx+r13*4]\nnop word ptr [rax+rax+00h]\nloc_1578:\nmovsxd rcx, dword ptr [rbx]\nmov rdx, rbp\nmov esi, 0Ah\nmov rdi, r12\nadd rbx, 4\nadd rbp, 0C8h\nshl rcx, 2\ncall sub_13E0\ncmp r13, rbx\njnz short loc_1578\nloc_159F:\nadd rsp, 8\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "void *__fastcall sub_1540(__int64 a1, int *a2, int a3)\n{\n __int64 v3; // r13\n int *v5; // rbx\n void *v6; // r12\n int *v7; // r13\n __int64 v8; // rcx\n __int64 v9; // rdx\n\n v3 = a3;\n v5 = a2;\n v6 = calloc(0xAuLL, 8uLL);\n if ( (int)v3 > 0 )\n {\n v7 = &a2[v3];\n do\n {\n v8 = *v5;\n v9 = a1;\n ++v5;\n a1 += 200LL;\n sub_13E0(v6, 10LL, v9, 4 * v8);\n }\n while ( v7 != v5 );\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1540(long long a1, int *a2, int a3) {\n long long v3;\n int *v5;\n void *v6;\n int *v7;\n long long v8;\n long long v9;\n v3 = a3;\n v5 = a2;\n v6 = calloc(10uLL, 8uLL);\n if ((int)v3 > 0) {\n v7 = &a2[v3];\n do {\n v8 = *v5;\n v9 = a1;\n ++v5;\n a1 += 200LL;\n sub_13E0(v6, 10LL, v9, 4 * v8);\n } while (v7 != v5);\n }\n return v6;\n}", + "ida_pseudo_norm": "void *func0(long long a1, int *a2, int a3) {\n long long v3;\n int *v5;\n void *v6;\n int *v7;\n long long v8;\n long long v9;\n v3 = a3;\n v5 = a2;\n v6 = calloc(10uLL, 8uLL);\n if ((int)v3 > 0) {\n v7 = &a2[v3];\n do {\n v8 = *v5;\n v9 = a1;\n ++v5;\n a1 += 200LL;\n insert_or_increment(v6, 10LL, v9, 4 * v8);\n } while (v7 != v5);\n }\n return v6;\n}" + }, + { + "index": 759, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char *num) {\n regex_t regex;\n int result;\n char *pattern = \"^[0-9]+(\\\\.[0-9]{1,2})?$\";\n if (regcomp(®ex, pattern, REG_EXTENDED) != 0) {\n return false;\n }\n result = regexec(®ex, num, 0, NULL, 0);\n regfree(®ex);\n return result == 0;\n}", + "test": "int main() {\n\n assert(func0(\"123.11\") == true);\n\n assert(func0(\"e666.86\") == false);\n\n assert(func0(\"3.124587\") == false);\n\n \n\n printf(\"All tests passed successfully.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x70,%rsp\nmov %rdi,-0x68(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0xdf9(%rip),%rax\nmov %rax,-0x58(%rbp)\nmov -0x58(%rbp),%rcx\nlea -0x50(%rbp),%rax\nmov $0x1,%edx\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 10e0 \ntest %eax,%eax\nje 1236 \nmov $0x0,%eax\njmp 126c \nmov -0x68(%rbp),%rsi\nlea -0x50(%rbp),%rax\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rax,%rdi\ncallq 10f0 \nmov %eax,-0x5c(%rbp)\nlea -0x50(%rbp),%rax\nmov %rax,%rdi\ncallq 10b0 \ncmpl $0x0,-0x5c(%rbp)\nsete %al\nmov -0x8(%rbp),%rdx\nxor %fs:0x28,%rdx\nje 1280 \ncallq 10c0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, a090912; \"^[0-9]+(\\\\.[0-9]{1,2})?$\"\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\ntest eax, eax\njz short loc_1236\nmov eax, 0\njmp short loc_126C\nloc_1236:\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_5C], eax\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\ncmp [rbp+var_5C], 0\nsetz al\nloc_126C:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1280\ncall ___stack_chk_fail\nlocret_1280:\nleave\nretn", + "ida_pseudo": "bool __fastcall func0(const char *a1)\n{\n int v2; // [rsp+14h] [rbp-5Ch]\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n unsigned __int64 v4; // [rsp+68h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"^[0-9]+(\\\\.[0-9]{1,2})?$\", 1) )\n return 0;\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n return v2 == 0;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, a090912; \"^[0-9]+(\\\\.[0-9]{1,2})?$\"\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\ntest eax, eax\njz short loc_1236\nmov eax, 0\njmp short loc_126C\nloc_1236:\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_5C], eax\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\ncmp [rbp+var_5C], 0\nsetz al\nloc_126C:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1280\ncall ___stack_chk_fail\nlocret_1280:\nleave\nretn", + "ida_strip_pseudo": "bool __fastcall sub_11E9(const char *a1)\n{\n int v2; // [rsp+14h] [rbp-5Ch]\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n unsigned __int64 v4; // [rsp+68h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"^[0-9]+(\\\\.[0-9]{1,2})?$\", 1) )\n return 0;\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n return v2 == 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_11E9(const char *a1) {\n int v2;\n regex_t preg;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n if (regcomp(&preg, \"^[0-9]+(\\\\.[0-9]{1,2})?$\", 1)) return 0;\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n return v2 == 0;\n}", + "ida_pseudo_norm": "bool func0(const char *a1) {\n int v2;\n regex_t preg;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n if (regcomp(&preg, \"^[0-9]+(\\\\.[0-9]{1,2})?$\", 1)) return 0;\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n return v2 == 0;\n}" + }, + { + "index": 759, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char *num) {\n regex_t regex;\n int result;\n char *pattern = \"^[0-9]+(\\\\.[0-9]{1,2})?$\";\n if (regcomp(®ex, pattern, REG_EXTENDED) != 0) {\n return false;\n }\n result = regexec(®ex, num, 0, NULL, 0);\n regfree(®ex);\n return result == 0;\n}", + "test": "int main() {\n\n assert(func0(\"123.11\") == true);\n\n assert(func0(\"e666.86\") == false);\n\n assert(func0(\"3.124587\") == false);\n\n \n\n printf(\"All tests passed successfully.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x58,%rsp\nmov %rdi,%rbx\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nmov $0x1,%edx\nlea 0xdef(%rip),%rsi\ncallq 10e0 \nmov %eax,%edx\nmov $0x0,%eax\ntest %edx,%edx\nje 123c \nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 126b \nadd $0x58,%rsp\npop %rbx\npop %rbp\nretq\nmov %rsp,%rbp\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rbx,%rsi\nmov %rbp,%rdi\ncallq 10f0 \nmov %eax,%ebx\nmov %rbp,%rdi\ncallq 10b0 \ntest %ebx,%ebx\nsete %al\njmp 1225 \ncallq 10c0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+68h+var_20], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"^[0-9]+(\\\\.[0-9]{1,2})?$\"\ncall _regcomp\nmov edx, eax\nmov eax, 0\ntest edx, edx\njz short loc_123C\nloc_1225:\nmov rdx, [rsp+68h+var_20]\nsub rdx, fs:28h\njnz short loc_126B\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_123C:\nmov rbp, rsp\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov ebx, eax\nmov rdi, rbp; preg\ncall _regfree\ntest ebx, ebx\nsetz al\njmp short loc_1225\nloc_126B:\ncall ___stack_chk_fail", + "ida_pseudo": "bool __fastcall func0(char *string)\n{\n int v1; // edx\n bool result; // al\n int v3; // ebx\n regex_t v4; // [rsp+0h] [rbp-68h] BYREF\n unsigned __int64 v5; // [rsp+48h] [rbp-20h]\n\n v5 = __readfsqword(0x28u);\n v1 = regcomp(&v4, \"^[0-9]+(\\\\.[0-9]{1,2})?$\", 1);\n result = 0;\n if ( !v1 )\n {\n v3 = regexec(&v4, string, 0LL, 0LL, 0);\n regfree(&v4);\n return v3 == 0;\n }\n return result;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+68h+var_20], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"^[0-9]+(\\\\.[0-9]{1,2})?$\"\ncall _regcomp\nmov edx, eax\nmov eax, 0\ntest edx, edx\njz short loc_123C\nloc_1225:\nmov rdx, [rsp+68h+var_20]\nsub rdx, fs:28h\njnz short loc_126B\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_123C:\nmov rbp, rsp\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov ebx, eax\nmov rdi, rbp; preg\ncall _regfree\ntest ebx, ebx\nsetz al\njmp short loc_1225\nloc_126B:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "bool __fastcall sub_11E9(char *string)\n{\n int v1; // edx\n bool result; // al\n int v3; // ebx\n regex_t v4; // [rsp+0h] [rbp-68h] BYREF\n unsigned __int64 v5; // [rsp+48h] [rbp-20h]\n\n v5 = __readfsqword(0x28u);\n v1 = regcomp(&v4, \"^[0-9]+(\\\\.[0-9]{1,2})?$\", 1);\n result = 0;\n if ( !v1 )\n {\n v3 = regexec(&v4, string, 0LL, 0LL, 0);\n regfree(&v4);\n return v3 == 0;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_11E9(char *string) {\n int v1;\n bool result;\n int v3;\n regex_t v4;\n unsigned long long v5;\n v5 = __readfsqword(40u);\n v1 = regcomp(&v4, \"^[0-9]+(\\\\.[0-9]{1,2})?$\", 1);\n result = 0;\n if (!v1) {\n v3 = regexec(&v4, string, 0LL, 0LL, 0);\n regfree(&v4);\n return v3 == 0;\n }\n return result;\n}", + "ida_pseudo_norm": "bool func0(char *string) {\n int v1;\n bool result;\n int v3;\n regex_t v4;\n unsigned long long v5;\n v5 = __readfsqword(40u);\n v1 = regcomp(&v4, \"^[0-9]+(\\\\.[0-9]{1,2})?$\", 1);\n result = 0;\n if (!v1) {\n v3 = regexec(&v4, string, 0LL, 0LL, 0);\n regfree(&v4);\n return v3 == 0;\n }\n return result;\n}" + }, + { + "index": 759, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char *num) {\n regex_t regex;\n int result;\n char *pattern = \"^[0-9]+(\\\\.[0-9]{1,2})?$\";\n if (regcomp(®ex, pattern, REG_EXTENDED) != 0) {\n return false;\n }\n result = regexec(®ex, num, 0, NULL, 0);\n regfree(®ex);\n return result == 0;\n}", + "test": "int main() {\n\n assert(func0(\"123.11\") == true);\n\n assert(func0(\"e666.86\") == false);\n\n assert(func0(\"3.124587\") == false);\n\n \n\n printf(\"All tests passed successfully.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov $0x1,%edx\nlea 0xd52(%rip),%rsi\npush %rbp\nmov %rdi,%rbp\nsub $0x58,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%r12\nmov %r12,%rdi\ncallq 10e0 \nmov %eax,%r8d\nxor %eax,%eax\ntest %r8d,%r8d\njne 12fd \nxor %ecx,%ecx\nxor %edx,%edx\nmov %rbp,%rsi\nmov %r12,%rdi\ncallq 10f0 \nmov %r12,%rdi\nmov %eax,%ebp\ncallq 10b0 \ntest %ebp,%ebp\nsete %al\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 1315 \nadd $0x58,%rsp\npop %rbp\npop %r12\nretq\ncallq 10c0 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"^[0-9]+(\\\\.[0-9]{1,2})?$\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nmov edx, eax\nxor eax, eax\ntest edx, edx\njnz short loc_12FD\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nsetz al\nloc_12FD:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_1314\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1314:\ncall ___stack_chk_fail", + "ida_pseudo": "bool __fastcall func0(char *string)\n{\n int v1; // edx\n bool result; // al\n int v3; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n v1 = regcomp(&_0, \"^[0-9]+(\\\\.[0-9]{1,2})?$\", 1);\n result = 0;\n if ( !v1 )\n {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v3 == 0;\n }\n return result;\n}", + "ida_strip_asm": "sub_12A0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"^[0-9]+(\\\\.[0-9]{1,2})?$\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nmov edx, eax\nxor eax, eax\ntest edx, edx\njnz short loc_12FD\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nsetz al\nloc_12FD:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_1314\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1314:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "bool __fastcall sub_12A0(char *string)\n{\n int v1; // edx\n bool result; // al\n int v3; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n v1 = regcomp(&_0, \"^[0-9]+(\\\\.[0-9]{1,2})?$\", 1);\n result = 0;\n if ( !v1 )\n {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v3 == 0;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_12A0(char *string) {\n int v1;\n bool result;\n int v3;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n v1 = regcomp(&_0, \"^[0-9]+(\\\\.[0-9]{1,2})?$\", 1);\n result = 0;\n if (!v1) {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v3 == 0;\n }\n return result;\n}", + "ida_pseudo_norm": "bool func0(char *string) {\n int v1;\n bool result;\n int v3;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n v1 = regcomp(&_0, \"^[0-9]+(\\\\.[0-9]{1,2})?$\", 1);\n result = 0;\n if (!v1) {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v3 == 0;\n }\n return result;\n}" + }, + { + "index": 759, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char *num) {\n regex_t regex;\n int result;\n char *pattern = \"^[0-9]+(\\\\.[0-9]{1,2})?$\";\n if (regcomp(®ex, pattern, REG_EXTENDED) != 0) {\n return false;\n }\n result = regexec(®ex, num, 0, NULL, 0);\n regfree(®ex);\n return result == 0;\n}", + "test": "int main() {\n\n assert(func0(\"123.11\") == true);\n\n assert(func0(\"e666.86\") == false);\n\n assert(func0(\"3.124587\") == false);\n\n \n\n printf(\"All tests passed successfully.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov $0x1,%edx\nlea 0xd52(%rip),%rsi\npush %rbp\nmov %rdi,%rbp\nsub $0x58,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%r12\nmov %r12,%rdi\ncallq 10e0 \nmov %eax,%r8d\nxor %eax,%eax\ntest %r8d,%r8d\njne 12fd \nxor %ecx,%ecx\nxor %edx,%edx\nmov %rbp,%rsi\nmov %r12,%rdi\ncallq 10f0 \nmov %r12,%rdi\nmov %eax,%ebp\ncallq 10b0 \ntest %ebp,%ebp\nsete %al\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 1315 \nadd $0x58,%rsp\npop %rbp\npop %r12\nretq\ncallq 10c0 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"^[0-9]+(\\\\.[0-9]{1,2})?$\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nmov edx, eax\nxor eax, eax\ntest edx, edx\njnz short loc_12FD\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nsetz al\nloc_12FD:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_1314\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1314:\ncall ___stack_chk_fail", + "ida_pseudo": "bool __fastcall func0(char *string)\n{\n int v1; // edx\n bool result; // al\n int v3; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n v1 = regcomp(&_0, \"^[0-9]+(\\\\.[0-9]{1,2})?$\", 1);\n result = 0;\n if ( !v1 )\n {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v3 == 0;\n }\n return result;\n}", + "ida_strip_asm": "sub_12A0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"^[0-9]+(\\\\.[0-9]{1,2})?$\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nmov edx, eax\nxor eax, eax\ntest edx, edx\njnz short loc_12FD\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nsetz al\nloc_12FD:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_1314\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1314:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "bool __fastcall sub_12A0(char *string)\n{\n int v1; // edx\n bool result; // al\n int v3; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n v1 = regcomp(&_0, \"^[0-9]+(\\\\.[0-9]{1,2})?$\", 1);\n result = 0;\n if ( !v1 )\n {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v3 == 0;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_12A0(char *string) {\n int v1;\n bool result;\n int v3;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n v1 = regcomp(&_0, \"^[0-9]+(\\\\.[0-9]{1,2})?$\", 1);\n result = 0;\n if (!v1) {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v3 == 0;\n }\n return result;\n}", + "ida_pseudo_norm": "bool func0(char *string) {\n int v1;\n bool result;\n int v3;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n v1 = regcomp(&_0, \"^[0-9]+(\\\\.[0-9]{1,2})?$\", 1);\n result = 0;\n if (!v1) {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v3 == 0;\n }\n return result;\n}" + }, + { + "index": 760, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "const char* func0(int arr[], int n) {\n for (int i = 1; i < n; i++) {\n if (arr[i] != arr[0]) {\n return \"NO\";\n }\n }\n return \"YES\";\n}", + "test": "int main() {\n\n int arr1[] = {1, 1, 1};\n\n assert(strcmp(func0(arr1, 3), \"YES\") == 0);\n\n\n\n int arr2[] = {1, 2, 1, 2};\n\n assert(strcmp(func0(arr2, 4), \"NO\") == 0);\n\n\n\n int arr3[] = {1, 2, 3, 4, 5};\n\n assert(strcmp(func0(arr3, 5), \"NO\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x1,-0x4(%rbp)\njmp 11ce \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x18(%rbp),%rax\nmov (%rax),%eax\ncmp %eax,%edx\nje 11ca \nlea 0xe40(%rip),%rax\njmp 11dd \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11a1 \nlea 0xe2e(%rip),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 1\njmp short loc_11CE\nloc_11A1:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_18]\nmov eax, [rax]\ncmp edx, eax\njz short loc_11CA\nlea rax, aNo; \"NO\"\njmp short loc_11DD\nloc_11CA:\nadd [rbp+var_4], 1\nloc_11CE:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11A1\nlea rax, s2; \"YES\"\nloc_11DD:\npop rbp\nretn", + "ida_pseudo": "const char *__fastcall func0(_DWORD *a1, int a2)\n{\n int i; // [rsp+18h] [rbp-4h]\n\n for ( i = 1; i < a2; ++i )\n {\n if ( a1[i] != *a1 )\n return \"NO\";\n }\n return \"YES\";\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 1\njmp short loc_11CE\nloc_11A1:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_18]\nmov eax, [rax]\ncmp edx, eax\njz short loc_11CA\nlea rax, aNo; \"NO\"\njmp short loc_11DD\nloc_11CA:\nadd [rbp+var_4], 1\nloc_11CE:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11A1\nlea rax, s2; \"YES\"\nloc_11DD:\npop rbp\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1189(_DWORD *a1, int a2)\n{\n int i; // [rsp+18h] [rbp-4h]\n\n for ( i = 1; i < a2; ++i )\n {\n if ( a1[i] != *a1 )\n return \"NO\";\n }\n return \"YES\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1189(uint32_t *a1, int a2) {\n int i;\n for (i = 1; i < a2; ++i) {\n if (a1[i] != *a1) return \"NO\";\n }\n return \"YES\";\n}", + "ida_pseudo_norm": "const char *func0(uint32_t *a1, int a2) {\n int i;\n for (i = 1; i < a2; ++i) {\n if (a1[i] != *a1) return \"NO\";\n }\n return \"YES\";\n}" + }, + { + "index": 760, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "const char* func0(int arr[], int n) {\n for (int i = 1; i < n; i++) {\n if (arr[i] != arr[0]) {\n return \"NO\";\n }\n }\n return \"YES\";\n}", + "test": "int main() {\n\n int arr1[] = {1, 1, 1};\n\n assert(strcmp(func0(arr1, 3), \"YES\") == 0);\n\n\n\n int arr2[] = {1, 2, 1, 2};\n\n assert(strcmp(func0(arr2, 4), \"NO\") == 0);\n\n\n\n int arr3[] = {1, 2, 3, 4, 5};\n\n assert(strcmp(func0(arr3, 5), \"NO\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nlea 0xe93(%rip),%rax\ncmp $0x1,%esi\njle 11a3 \nmov (%rdi),%edx\nlea 0x4(%rdi),%rax\nlea -0x2(%rsi),%ecx\nlea 0x8(%rdi,%rcx,4),%rcx\ncmp %edx,(%rax)\njne 119c \nadd $0x4,%rax\ncmp %rcx,%rax\njne 1187 \nlea 0xe6c(%rip),%rax\nretq\nlea 0xe61(%rip),%rax\nretq\n", + "ida_asm": "func0:\nendbr64\nlea rax, s2; \"YES\"\ncmp esi, 1\njle short locret_11C3\nmov edx, [rdi]\nlea rax, [rdi+4]\nlea ecx, [rsi-2]\nlea rcx, [rdi+rcx*4+8]\nloc_11A7:\ncmp [rax], edx\njnz short loc_11BC\nadd rax, 4\ncmp rax, rcx\njnz short loc_11A7\nlea rax, s2; \"YES\"\nretn\nloc_11BC:\nlea rax, aNo; \"NO\"\nlocret_11C3:\nretn", + "ida_pseudo": "const char *__fastcall func0(_DWORD *a1, int a2)\n{\n const char *result; // rax\n _DWORD *v3; // rax\n\n result = \"YES\";\n if ( a2 > 1 )\n {\n v3 = a1 + 1;\n while ( *v3 == *a1 )\n {\n if ( ++v3 == &a1[a2 - 2 + 2] )\n return \"YES\";\n }\n return \"NO\";\n }\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\nlea rax, s2; \"YES\"\ncmp esi, 1\njle short locret_11C3\nmov edx, [rdi]\nlea rax, [rdi+4]\nlea ecx, [rsi-2]\nlea rcx, [rdi+rcx*4+8]\nloc_11A7:\ncmp [rax], edx\njnz short loc_11BC\nadd rax, 4\ncmp rax, rcx\njnz short loc_11A7\nlea rax, s2; \"YES\"\nretn\nloc_11BC:\nlea rax, aNo; \"NO\"\nlocret_11C3:\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1189(_DWORD *a1, int a2)\n{\n const char *result; // rax\n _DWORD *v3; // rax\n\n result = \"YES\";\n if ( a2 > 1 )\n {\n v3 = a1 + 1;\n while ( *v3 == *a1 )\n {\n if ( ++v3 == &a1[a2 - 2 + 2] )\n return \"YES\";\n }\n return \"NO\";\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1189(uint32_t *a1, int a2) {\n const char *result;\n uint32_t *v3;\n result = \"YES\";\n if (a2 > 1) {\n v3 = a1 + 1;\n while (*v3 == *a1) {\n if (++v3 == &a1[a2 - 2 + 2]) return \"YES\";\n }\n return \"NO\";\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(uint32_t *a1, int a2) {\n const char *result;\n uint32_t *v3;\n result = \"YES\";\n if (a2 > 1) {\n v3 = a1 + 1;\n while (*v3 == *a1) {\n if (++v3 == &a1[a2 - 2 + 2]) return \"YES\";\n }\n return \"NO\";\n }\n return result;\n}" + }, + { + "index": 761, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(double d, double a) {\n double pi = 22.0 / 7.0;\n if (a >= 360) {\n return -1;\n }\n double arclength = (pi * d) * (a / 360);\n return arclength;\n}", + "test": "int main() {\n\n assert(func0(9, 45) - 3.5357142857142856 < 0.0001);\n\n assert(func0(9, 480) == -1); // Using -1 to represent None\n\n assert(func0(5, 270) - 11.785714285714285 < 0.0001);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmovsd %xmm0,-0x18(%rbp)\nmovsd %xmm1,-0x20(%rbp)\nmovsd 0xf5d(%rip),%xmm0\nmovsd %xmm0,-0x10(%rbp)\nmovsd -0x20(%rbp),%xmm0\ncomisd 0xf53(%rip),%xmm0\njb 1181 \nmovsd 0xf51(%rip),%xmm0\njmp 11ae \nmovsd -0x10(%rbp),%xmm0\nmovapd %xmm0,%xmm1\nmulsd -0x18(%rbp),%xmm1\nmovsd -0x20(%rbp),%xmm0\nmovsd 0xf2c(%rip),%xmm2\ndivsd %xmm2,%xmm0\nmulsd %xmm1,%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmovsd -0x8(%rbp),%xmm0\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmovsd [rbp+var_18], xmm0\nmovsd [rbp+var_20], xmm1\nmovsd xmm0, cs:qword_20A0\nmovsd [rbp+var_10], xmm0\nmovsd xmm0, [rbp+var_20]\ncomisd xmm0, cs:qword_20A8\njb short loc_1181\nmovsd xmm0, cs:qword_20B0\njmp short loc_11AE\nloc_1181:\nmovsd xmm0, [rbp+var_10]\nmovapd xmm1, xmm0\nmulsd xmm1, [rbp+var_18]\nmovsd xmm0, [rbp+var_20]\nmovsd xmm2, cs:qword_20A8\ndivsd xmm0, xmm2\nmulsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\nloc_11AE:\npop rbp\nretn", + "ida_pseudo": "double __fastcall func0(double a1, double a2)\n{\n if ( a2 < 360.0 )\n return a2 / 360.0 * (3.142857142857143 * a1);\n else\n return -1.0;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmovsd [rbp+var_18], xmm0\nmovsd [rbp+var_20], xmm1\nmovsd xmm0, cs:qword_20A0\nmovsd [rbp+var_10], xmm0\nmovsd xmm0, [rbp+var_20]\ncomisd xmm0, cs:qword_20A8\njb short loc_1181\nmovsd xmm0, cs:qword_20B0\njmp short loc_11AE\nloc_1181:\nmovsd xmm0, [rbp+var_10]\nmovapd xmm1, xmm0\nmulsd xmm1, [rbp+var_18]\nmovsd xmm0, [rbp+var_20]\nmovsd xmm2, cs:qword_20A8\ndivsd xmm0, xmm2\nmulsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\nloc_11AE:\npop rbp\nretn", + "ida_strip_pseudo": "double __fastcall sub_1149(double a1, double a2)\n{\n if ( a2 < 360.0 )\n return a2 / 360.0 * (3.142857142857143 * a1);\n else\n return -1.0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1149(double a1, double a2) {\n if (a2 < 360.0)\n return a2 / 360.0 * (3.142857142857143 * a1);\n else\n return -1.0;\n}", + "ida_pseudo_norm": "double func0(double a1, double a2) {\n if (a2 < 360.0)\n return a2 / 360.0 * (3.142857142857143 * a1);\n else\n return -1.0;\n}" + }, + { + "index": 762, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int monthnum3) {\n if (monthnum3 == 4 || monthnum3 == 6 || monthnum3 == 9 || monthnum3 == 11) {\n return 1;\n } else {\n return 0;\n }\n}", + "test": "int main() {\n\n assert(func0(6) == 1);\n\n assert(func0(2) == 0);\n\n assert(func0(12) == 0);\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\ncmpl $0x4,-0x4(%rbp)\nje 116c \ncmpl $0x6,-0x4(%rbp)\nje 116c \ncmpl $0x9,-0x4(%rbp)\nje 116c \ncmpl $0xb,-0x4(%rbp)\njne 1173 \nmov $0x1,%eax\njmp 1178 \nmov $0x0,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\ncmp [rbp+var_4], 4\njz short loc_116C\ncmp [rbp+var_4], 6\njz short loc_116C\ncmp [rbp+var_4], 9\njz short loc_116C\ncmp [rbp+var_4], 0Bh\njnz short loc_1173\nloc_116C:\nmov eax, 1\njmp short loc_1178\nloc_1173:\nmov eax, 0\nloc_1178:\npop rbp\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(int a1)\n{\n return a1 == 4 || a1 == 6 || a1 == 9 || a1 == 11;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\ncmp [rbp+var_4], 4\njz short loc_116C\ncmp [rbp+var_4], 6\njz short loc_116C\ncmp [rbp+var_4], 9\njz short loc_116C\ncmp [rbp+var_4], 0Bh\njnz short loc_1173\nloc_116C:\nmov eax, 1\njmp short loc_1178\nloc_1173:\nmov eax, 0\nloc_1178:\npop rbp\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1149(int a1)\n{\n return a1 == 4 || a1 == 6 || a1 == 9 || a1 == 11;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1149(int a1) { return a1 == 4 || a1 == 6 || a1 == 9 || a1 == 11; }", + "ida_pseudo_norm": "uint8_t func0(int a1) { return a1 == 4 || a1 == 6 || a1 == 9 || a1 == 11; }" + }, + { + "index": 763, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int i, j, temp;\n for (i = 0; i < n - 1; i++) {\n for (j = 0; j < n - i - 1; j++) {\n if (arr[j] > arr[j + 1]) {\n temp = arr[j];\n arr[j] = arr[j + 1];\n arr[j + 1] = temp;\n }\n }\n }\n int diff = __INT_MAX__;\n for (i = 0; i < n - 1; i++) {\n if (arr[i + 1] - arr[i] < diff) {\n diff = arr[i + 1] - arr[i];\n }\n }\n return diff;\n}", + "test": "int main() {\n\n int arr1[] = {1, 5, 3, 19, 18, 25};\n\n int arr2[] = {4, 3, 2, 6};\n\n int arr3[] = {30, 5, 20, 9};\n\n \n\n assert(func0(arr1, 6) == 1);\n\n assert(func0(arr2, 4) == 1);\n\n assert(func0(arr3, 4) == 4);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x10(%rbp)\njmpq 1245 \nmovl $0x0,-0xc(%rbp)\njmpq 122f \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0xc(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njle 122b \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x4(%rbp)\nmov -0xc(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0xc(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\nmov -0xc(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0x4(%rbp),%eax\nmov %eax,(%rdx)\naddl $0x1,-0xc(%rbp)\nmov -0x1c(%rbp),%eax\nsub -0x10(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0xc(%rbp)\njl 1190 \naddl $0x1,-0x10(%rbp)\nmov -0x1c(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x10(%rbp)\njl 1184 \nmovl $0x7fffffff,-0x8(%rbp)\nmovl $0x0,-0x10(%rbp)\njmp 12d8 \nmov -0x10(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\nsub %eax,%edx\nmov %edx,%eax\ncmp %eax,-0x8(%rbp)\njle 12d4 \nmov -0x10(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\nsub %eax,%edx\nmov %edx,%eax\nmov %eax,-0x8(%rbp)\naddl $0x1,-0x10(%rbp)\nmov -0x1c(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x10(%rbp)\njl 1264 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_10], 0\njmp loc_1245\nloc_1184:\nmov [rbp+var_C], 0\njmp loc_122F\nloc_1190:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_122B\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_C]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_C]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nloc_122B:\nadd [rbp+var_C], 1\nloc_122F:\nmov eax, [rbp+var_1C]\nsub eax, [rbp+var_10]\nsub eax, 1\ncmp [rbp+var_C], eax\njl loc_1190\nadd [rbp+var_10], 1\nloc_1245:\nmov eax, [rbp+var_1C]\nsub eax, 1\ncmp [rbp+var_10], eax\njl loc_1184\nmov [rbp+var_8], 7FFFFFFFh\nmov [rbp+var_10], 0\njmp short loc_12D4\nloc_1264:\nmov eax, [rbp+var_10]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nsub edx, eax\ncmp [rbp+var_8], edx\njle short loc_12D0\nmov eax, [rbp+var_10]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nsub edx, eax\nmov [rbp+var_8], edx\nloc_12D0:\nadd [rbp+var_10], 1\nloc_12D4:\nmov eax, [rbp+var_1C]\nsub eax, 1\ncmp [rbp+var_10], eax\njl short loc_1264\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+Ch] [rbp-10h]\n int k; // [rsp+Ch] [rbp-10h]\n int j; // [rsp+10h] [rbp-Ch]\n int v6; // [rsp+14h] [rbp-8h]\n int v7; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i < a2 - 1; ++i )\n {\n for ( j = 0; j < a2 - i - 1; ++j )\n {\n if ( *(_DWORD *)(4LL * j + a1) > *(_DWORD *)(4 * (j + 1LL) + a1) )\n {\n v7 = *(_DWORD *)(4LL * j + a1);\n *(_DWORD *)(4LL * j + a1) = *(_DWORD *)(4 * (j + 1LL) + a1);\n *(_DWORD *)(a1 + 4 * (j + 1LL)) = v7;\n }\n }\n }\n v6 = 0x7FFFFFFF;\n for ( k = 0; k < a2 - 1; ++k )\n {\n if ( v6 > *(_DWORD *)(4 * (k + 1LL) + a1) - *(_DWORD *)(4LL * k + a1) )\n v6 = *(_DWORD *)(4 * (k + 1LL) + a1) - *(_DWORD *)(4LL * k + a1);\n }\n return (unsigned int)v6;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_10], 0\njmp loc_1245\nloc_1184:\nmov [rbp+var_C], 0\njmp loc_122F\nloc_1190:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_122B\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_C]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_C]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nloc_122B:\nadd [rbp+var_C], 1\nloc_122F:\nmov eax, [rbp+var_1C]\nsub eax, [rbp+var_10]\nsub eax, 1\ncmp [rbp+var_C], eax\njl loc_1190\nadd [rbp+var_10], 1\nloc_1245:\nmov eax, [rbp+var_1C]\nsub eax, 1\ncmp [rbp+var_10], eax\njl loc_1184\nmov [rbp+var_8], 7FFFFFFFh\nmov [rbp+var_10], 0\njmp short loc_12D4\nloc_1264:\nmov eax, [rbp+var_10]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nsub edx, eax\ncmp [rbp+var_8], edx\njle short loc_12D0\nmov eax, [rbp+var_10]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nsub edx, eax\nmov [rbp+var_8], edx\nloc_12D0:\nadd [rbp+var_10], 1\nloc_12D4:\nmov eax, [rbp+var_1C]\nsub eax, 1\ncmp [rbp+var_10], eax\njl short loc_1264\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int i; // [rsp+Ch] [rbp-10h]\n int k; // [rsp+Ch] [rbp-10h]\n int j; // [rsp+10h] [rbp-Ch]\n int v6; // [rsp+14h] [rbp-8h]\n int v7; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i < a2 - 1; ++i )\n {\n for ( j = 0; j < a2 - i - 1; ++j )\n {\n if ( *(_DWORD *)(4LL * j + a1) > *(_DWORD *)(4 * (j + 1LL) + a1) )\n {\n v7 = *(_DWORD *)(4LL * j + a1);\n *(_DWORD *)(4LL * j + a1) = *(_DWORD *)(4 * (j + 1LL) + a1);\n *(_DWORD *)(a1 + 4 * (j + 1LL)) = v7;\n }\n }\n }\n v6 = 0x7FFFFFFF;\n for ( k = 0; k < a2 - 1; ++k )\n {\n if ( v6 > *(_DWORD *)(4 * (k + 1LL) + a1) - *(_DWORD *)(4LL * k + a1) )\n v6 = *(_DWORD *)(4 * (k + 1LL) + a1) - *(_DWORD *)(4LL * k + a1);\n }\n return (unsigned int)v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int i;\n int k;\n int j;\n int v6;\n int v7;\n for (i = 0; i < a2 - 1; ++i) {\n for (j = 0; j < a2 - i - 1; ++j) {\n if (*(uint32_t *)(4LL * j + a1) > *(uint32_t *)(4 * (j + 1LL) + a1)) {\n v7 = *(uint32_t *)(4LL * j + a1);\n *(uint32_t *)(4LL * j + a1) = *(uint32_t *)(4 * (j + 1LL) + a1);\n *(uint32_t *)(a1 + 4 * (j + 1LL)) = v7;\n }\n }\n }\n v6 = 2147483647;\n for (k = 0; k < a2 - 1; ++k) {\n if (v6 > *(uint32_t *)(4 * (k + 1LL) + a1) - *(uint32_t *)(4LL * k + a1))\n v6 = *(uint32_t *)(4 * (k + 1LL) + a1) - *(uint32_t *)(4LL * k + a1);\n }\n return (unsigned int)v6;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int i;\n int k;\n int j;\n int v6;\n int v7;\n for (i = 0; i < a2 - 1; ++i) {\n for (j = 0; j < a2 - i - 1; ++j) {\n if (*(uint32_t *)(4LL * j + a1) > *(uint32_t *)(4 * (j + 1LL) + a1)) {\n v7 = *(uint32_t *)(4LL * j + a1);\n *(uint32_t *)(4LL * j + a1) = *(uint32_t *)(4 * (j + 1LL) + a1);\n *(uint32_t *)(a1 + 4 * (j + 1LL)) = v7;\n }\n }\n }\n v6 = 2147483647;\n for (k = 0; k < a2 - 1; ++k) {\n if (v6 > *(uint32_t *)(4 * (k + 1LL) + a1) - *(uint32_t *)(4LL * k + a1))\n v6 = *(uint32_t *)(4 * (k + 1LL) + a1) - *(uint32_t *)(4LL * k + a1);\n }\n return (unsigned int)v6;\n}" + }, + { + "index": 763, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int i, j, temp;\n for (i = 0; i < n - 1; i++) {\n for (j = 0; j < n - i - 1; j++) {\n if (arr[j] > arr[j + 1]) {\n temp = arr[j];\n arr[j] = arr[j + 1];\n arr[j + 1] = temp;\n }\n }\n }\n int diff = __INT_MAX__;\n for (i = 0; i < n - 1; i++) {\n if (arr[i + 1] - arr[i] < diff) {\n diff = arr[i + 1] - arr[i];\n }\n }\n return diff;\n}", + "test": "int main() {\n\n int arr1[] = {1, 5, 3, 19, 18, 25};\n\n int arr2[] = {4, 3, 2, 6};\n\n int arr3[] = {30, 5, 20, 9};\n\n \n\n assert(func0(arr1, 6) == 1);\n\n assert(func0(arr2, 4) == 1);\n\n assert(func0(arr3, 4) == 4);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nlea -0x1(%rsi),%r9d\ntest %r9d,%r9d\njle 11d3 \nlea 0x4(%rdi),%r10\njmp 119b \nadd $0x4,%rax\ncmp %r8,%rax\nje 1195 \nmov (%rax),%edx\nmov 0x4(%rax),%ecx\ncmp %ecx,%edx\njle 117c \nmov %ecx,(%rax)\nmov %edx,0x4(%rax)\njmp 117c \nsub $0x1,%r9d\nje 11ad \ntest %r9d,%r9d\njle 1195 \nmov %rdi,%rax\nlea -0x1(%r9),%edx\nlea (%r10,%rdx,4),%r8\njmp 1185 \nmov %rdi,%rax\nlea -0x2(%rsi),%edx\nlea 0x4(%rdi,%rdx,4),%rsi\nmov $0x7fffffff,%ecx\nmov 0x4(%rax),%edx\nsub (%rax),%edx\ncmp %edx,%ecx\ncmovg %edx,%ecx\nadd $0x4,%rax\ncmp %rsi,%rax\njne 11bd \nmov %ecx,%eax\nretq\nmov $0x7fffffff,%ecx\njmp 11d0 \n", + "ida_asm": "func0:\nendbr64\ncmp esi, 1\njle short loc_11D7\nmov r9d, esi\nlea r10, [rdi+4]\njmp short loc_119E\nloc_117B:\nadd rax, 4\ncmp rax, r8\njz short loc_1194\nloc_1184:\nmov edx, [rax]\nmov ecx, [rax+4]\ncmp edx, ecx\njle short loc_117B\nmov [rax], ecx\nmov [rax+4], edx\njmp short loc_117B\nloc_1194:\nsub r9d, 1\ncmp r9d, 1\njz short loc_11B1\nloc_119E:\ncmp r9d, 1\njle short loc_11DE\nmov rax, rdi\nlea edx, [r9-2]\nlea r8, [r10+rdx*4]\njmp short loc_1184\nloc_11B1:\nmov rax, rdi\nlea edx, [rsi-2]\nlea rsi, [rdi+rdx*4+4]\nmov ecx, 7FFFFFFFh\nloc_11C1:\nmov edx, [rax+4]\nsub edx, [rax]\ncmp ecx, edx\ncmovg ecx, edx\nadd rax, 4\ncmp rax, rsi\njnz short loc_11C1\nloc_11D4:\nmov eax, ecx\nretn\nloc_11D7:\nmov ecx, 7FFFFFFFh\njmp short loc_11D4\nloc_11DE:\nsub r9d, 1\njmp short loc_119E", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int i; // r9d\n int *v3; // rax\n int v4; // edx\n int v5; // ecx\n int *v6; // rax\n __int64 v7; // rsi\n int v8; // ecx\n\n if ( a2 <= 1 )\n {\n return 0x7FFFFFFF;\n }\n else\n {\n for ( i = a2; i != 1; --i )\n {\n while ( i <= 1 )\n --i;\n v3 = a1;\n do\n {\n v4 = *v3;\n v5 = v3[1];\n if ( *v3 > v5 )\n {\n *v3 = v5;\n v3[1] = v4;\n }\n ++v3;\n }\n while ( v3 != &a1[i - 2 + 1] );\n }\n v6 = a1;\n v7 = (__int64)&a1[a2 - 2 + 1];\n v8 = 0x7FFFFFFF;\n do\n {\n if ( v8 > v6[1] - *v6 )\n v8 = v6[1] - *v6;\n ++v6;\n }\n while ( v6 != (int *)v7 );\n }\n return (unsigned int)v8;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ncmp esi, 1\njle short loc_11D7\nmov r9d, esi\nlea r10, [rdi+4]\njmp short loc_119E\nloc_117B:\nadd rax, 4\ncmp rax, r8\njz short loc_1194\nloc_1184:\nmov edx, [rax]\nmov ecx, [rax+4]\ncmp edx, ecx\njle short loc_117B\nmov [rax], ecx\nmov [rax+4], edx\njmp short loc_117B\nloc_1194:\nsub r9d, 1\ncmp r9d, 1\njz short loc_11B1\nloc_119E:\ncmp r9d, 1\njle short loc_11DE\nmov rax, rdi\nlea edx, [r9-2]\nlea r8, [r10+rdx*4]\njmp short loc_1184\nloc_11B1:\nmov rax, rdi\nlea edx, [rsi-2]\nlea rsi, [rdi+rdx*4+4]\nmov ecx, 7FFFFFFFh\nloc_11C1:\nmov edx, [rax+4]\nsub edx, [rax]\ncmp ecx, edx\ncmovg ecx, edx\nadd rax, 4\ncmp rax, rsi\njnz short loc_11C1\nloc_11D4:\nmov eax, ecx\nretn\nloc_11D7:\nmov ecx, 7FFFFFFFh\njmp short loc_11D4\nloc_11DE:\nsub r9d, 1\njmp short loc_119E", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int *a1, int a2)\n{\n int i; // r9d\n int *v3; // rax\n int v4; // edx\n int v5; // ecx\n int *v6; // rax\n __int64 v7; // rsi\n int v8; // ecx\n\n if ( a2 <= 1 )\n {\n return 0x7FFFFFFF;\n }\n else\n {\n for ( i = a2; i != 1; --i )\n {\n while ( i <= 1 )\n --i;\n v3 = a1;\n do\n {\n v4 = *v3;\n v5 = v3[1];\n if ( *v3 > v5 )\n {\n *v3 = v5;\n v3[1] = v4;\n }\n ++v3;\n }\n while ( v3 != &a1[i - 2 + 1] );\n }\n v6 = a1;\n v7 = (__int64)&a1[a2 - 2 + 1];\n v8 = 0x7FFFFFFF;\n do\n {\n if ( v8 > v6[1] - *v6 )\n v8 = v6[1] - *v6;\n ++v6;\n }\n while ( v6 != (int *)v7 );\n }\n return (unsigned int)v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int *a1, int a2) {\n int i;\n int *v3;\n int v4;\n int v5;\n int *v6;\n long long v7;\n int v8;\n if (a2 <= 1) {\n return 2147483647;\n } else {\n for (i = a2; i != 1; --i) {\n while (i <= 1) --i;\n v3 = a1;\n do {\n v4 = *v3;\n v5 = v3[1];\n if (*v3 > v5) {\n *v3 = v5;\n v3[1] = v4;\n }\n ++v3;\n } while (v3 != &a1[i - 2 + 1]);\n }\n v6 = a1;\n v7 = (long long)&a1[a2 - 2 + 1];\n v8 = 2147483647;\n do {\n if (v8 > v6[1] - *v6) v8 = v6[1] - *v6;\n ++v6;\n } while (v6 != (int *)v7);\n }\n return (unsigned int)v8;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int i;\n int *v3;\n int v4;\n int v5;\n int *v6;\n long long v7;\n int v8;\n if (a2 <= 1) {\n return 2147483647;\n } else {\n for (i = a2; i != 1; --i) {\n while (i <= 1) --i;\n v3 = a1;\n do {\n v4 = *v3;\n v5 = v3[1];\n if (*v3 > v5) {\n *v3 = v5;\n v3[1] = v4;\n }\n ++v3;\n } while (v3 != &a1[i - 2 + 1]);\n }\n v6 = a1;\n v7 = (long long)&a1[a2 - 2 + 1];\n v8 = 2147483647;\n do {\n if (v8 > v6[1] - *v6) v8 = v6[1] - *v6;\n ++v6;\n } while (v6 != (int *)v7);\n }\n return (unsigned int)v8;\n}" + }, + { + "index": 763, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int i, j, temp;\n for (i = 0; i < n - 1; i++) {\n for (j = 0; j < n - i - 1; j++) {\n if (arr[j] > arr[j + 1]) {\n temp = arr[j];\n arr[j] = arr[j + 1];\n arr[j + 1] = temp;\n }\n }\n }\n int diff = __INT_MAX__;\n for (i = 0; i < n - 1; i++) {\n if (arr[i + 1] - arr[i] < diff) {\n diff = arr[i + 1] - arr[i];\n }\n }\n return diff;\n}", + "test": "int main() {\n\n int arr1[] = {1, 5, 3, 19, 18, 25};\n\n int arr2[] = {4, 3, 2, 6};\n\n int arr3[] = {30, 5, 20, 9};\n\n \n\n assert(func0(arr1, 6) == 1);\n\n assert(func0(arr2, 4) == 1);\n\n assert(func0(arr3, 4) == 4);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nlea -0x1(%rsi),%edx\ntest %edx,%edx\njle 1319 \nlea 0x4(%rdi),%r10\nsub $0x1,%edx\nmov %rdi,%rax\nmov %rdx,%r9\nlea (%r10,%rdx,4),%r8\nnopl (%rax)\nmov (%rax),%edx\nmov 0x4(%rax),%ecx\ncmp %ecx,%edx\njle 12de \nmov %ecx,(%rax)\nmov %edx,0x4(%rax)\nadd $0x4,%rax\ncmp %rax,%r8\njne 12d0 \nmov %r9d,%edx\ntest %r9d,%r9d\njne 12c0 \nlea -0x2(%rsi),%eax\nmov $0x7fffffff,%r8d\nlea (%r10,%rax,4),%rdx\nnopl 0x0(%rax)\nmov 0x4(%rdi),%eax\nsub (%rdi),%eax\ncmp %eax,%r8d\ncmovg %eax,%r8d\nadd $0x4,%rdi\ncmp %rdi,%rdx\njne 1300 \nmov %r8d,%eax\nretq\nmov $0x7fffffff,%r8d\nmov %r8d,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\ncmp esi, 1\njle loc_1311\nmov r10d, esi\nlea r9, [rdi+4]\nnop dword ptr [rax+00h]\nloc_1288:\ncmp r10d, 1\njle short loc_1308\nlea eax, [r10-2]\nlea r8, [r9+rax*4]\nmov rax, rdi\nnop dword ptr [rax+00000000h]\nloc_12A0:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd edx, xmm0\nmovd ecx, xmm1\ncmp ecx, edx\njge short loc_12BE\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_12BE:\nadd rax, 4\ncmp rax, r8\njnz short loc_12A0\nsub r10d, 1\ncmp r10d, 1\njnz short loc_1288\nlea edx, [rsi-2]\nmov ecx, [rdi]\nmov rax, r9\nlea r8, [rdi+rdx*4+8]\nmov edx, 7FFFFFFFh\nnop dword ptr [rax+rax+00h]\nloc_12E8:\nmov edi, ecx\nmov ecx, [rax]\nmov esi, ecx\nsub esi, edi\ncmp edx, esi\ncmovg edx, esi\nadd rax, 4\ncmp r8, rax\njnz short loc_12E8\nmov eax, edx\nretn\nloc_1308:\nsub r10d, 1\njmp loc_1288\nloc_1311:\nmov edx, 7FFFFFFFh\nmov eax, edx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__m128i *a1, int a2)\n{\n int i; // r10d\n __m128i *v3; // rax\n __m128i v4; // xmm0\n __int32 v5; // ecx\n __int32 *v6; // rax\n __int64 v7; // r8\n int v8; // edx\n __int32 v9; // edi\n\n if ( a2 <= 1 )\n return 0x7FFFFFFFLL;\n for ( i = a2; i != 1; --i )\n {\n while ( i <= 1 )\n --i;\n v3 = a1;\n do\n {\n v4 = _mm_loadl_epi64(v3);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v4, 229)) < _mm_cvtsi128_si32(v4) )\n v3->m128i_i64[0] = _mm_shuffle_epi32(v4, 225).m128i_u64[0];\n v3 = (__m128i *)((char *)v3 + 4);\n }\n while ( v3 != (__m128i *)((char *)a1->m128i_i64 + 4 * (unsigned int)(i - 2) + 4) );\n }\n v5 = a1->m128i_i32[0];\n v6 = &a1->m128i_i32[1];\n v7 = (__int64)&a1->m128i_i64[1] + 4 * (unsigned int)(a2 - 2);\n v8 = 0x7FFFFFFF;\n do\n {\n v9 = v5;\n v5 = *v6;\n if ( v8 > *v6 - v9 )\n v8 = *v6 - v9;\n ++v6;\n }\n while ( (__int32 *)v7 != v6 );\n return (unsigned int)v8;\n}", + "ida_strip_asm": "sub_1270:\nendbr64\ncmp esi, 1\njle loc_1311\nmov r10d, esi\nlea r9, [rdi+4]\nnop dword ptr [rax+00h]\nloc_1288:\ncmp r10d, 1\njle short loc_1308\nlea eax, [r10-2]\nlea r8, [r9+rax*4]\nmov rax, rdi\nnop dword ptr [rax+00000000h]\nloc_12A0:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd edx, xmm0\nmovd ecx, xmm1\ncmp ecx, edx\njge short loc_12BE\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_12BE:\nadd rax, 4\ncmp rax, r8\njnz short loc_12A0\nsub r10d, 1\ncmp r10d, 1\njnz short loc_1288\nlea edx, [rsi-2]\nmov ecx, [rdi]\nmov rax, r9\nlea r8, [rdi+rdx*4+8]\nmov edx, 7FFFFFFFh\nnop dword ptr [rax+rax+00h]\nloc_12E8:\nmov edi, ecx\nmov ecx, [rax]\nmov esi, ecx\nsub esi, edi\ncmp edx, esi\ncmovg edx, esi\nadd rax, 4\ncmp r8, rax\njnz short loc_12E8\nmov eax, edx\nretn\nloc_1308:\nsub r10d, 1\njmp loc_1288\nloc_1311:\nmov edx, 7FFFFFFFh\nmov eax, edx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1270(__m128i *a1, int a2)\n{\n int i; // r10d\n __m128i *v3; // rax\n __m128i v4; // xmm0\n __int32 v5; // ecx\n __int32 *v6; // rax\n __int64 v7; // r8\n int v8; // edx\n __int32 v9; // edi\n\n if ( a2 <= 1 )\n return 0x7FFFFFFFLL;\n for ( i = a2; i != 1; --i )\n {\n while ( i <= 1 )\n --i;\n v3 = a1;\n do\n {\n v4 = _mm_loadl_epi64(v3);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v4, 229)) < _mm_cvtsi128_si32(v4) )\n v3->m128i_i64[0] = _mm_shuffle_epi32(v4, 225).m128i_u64[0];\n v3 = (__m128i *)((char *)v3 + 4);\n }\n while ( v3 != (__m128i *)((char *)a1->m128i_i64 + 4 * (unsigned int)(i - 2) + 4) );\n }\n v5 = a1->m128i_i32[0];\n v6 = &a1->m128i_i32[1];\n v7 = (__int64)&a1->m128i_i64[1] + 4 * (unsigned int)(a2 - 2);\n v8 = 0x7FFFFFFF;\n do\n {\n v9 = v5;\n v5 = *v6;\n if ( v8 > *v6 - v9 )\n v8 = *v6 - v9;\n ++v6;\n }\n while ( (__int32 *)v7 != v6 );\n return (unsigned int)v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1270(__m128i *a1, int a2) {\n int i;\n __m128i *v3;\n __m128i v4;\n int v5;\n int *v6;\n long long v7;\n int v8;\n int v9;\n if (a2 <= 1) return 2147483647LL;\n for (i = a2; i != 1; --i) {\n while (i <= 1) --i;\n v3 = a1;\n do {\n v4 = _mm_loadl_epi64(v3);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v4, 229)) < _mm_cvtsi128_si32(v4))\n v3->m128i_i64[0] = _mm_shuffle_epi32(v4, 225).m128i_u64[0];\n v3 = (__m128i *)((char *)v3 + 4);\n } while (v3 != (__m128i *)((char *)a1->m128i_i64 +\n 4 * (unsigned int)(i - 2) + 4));\n }\n v5 = a1->m128i_i32[0];\n v6 = &a1->m128i_i32[1];\n v7 = (long long)&a1->m128i_i64[1] + 4 * (unsigned int)(a2 - 2);\n v8 = 2147483647;\n do {\n v9 = v5;\n v5 = *v6;\n if (v8 > *v6 - v9) v8 = *v6 - v9;\n ++v6;\n } while ((int *)v7 != v6);\n return (unsigned int)v8;\n}", + "ida_pseudo_norm": "long long func0(__m128i *a1, int a2) {\n int i;\n __m128i *v3;\n __m128i v4;\n int v5;\n int *v6;\n long long v7;\n int v8;\n int v9;\n if (a2 <= 1) return 2147483647LL;\n for (i = a2; i != 1; --i) {\n while (i <= 1) --i;\n v3 = a1;\n do {\n v4 = _mm_loadl_epi64(v3);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v4, 229)) < _mm_cvtsi128_si32(v4))\n v3->m128i_i64[0] = _mm_shuffle_epi32(v4, 225).m128i_u64[0];\n v3 = (__m128i *)((char *)v3 + 4);\n } while (v3 != (__m128i *)((char *)a1->m128i_i64 +\n 4 * (unsigned int)(i - 2) + 4));\n }\n v5 = a1->m128i_i32[0];\n v6 = &a1->m128i_i32[1];\n v7 = (long long)&a1->m128i_i64[1] + 4 * (unsigned int)(a2 - 2);\n v8 = 2147483647;\n do {\n v9 = v5;\n v5 = *v6;\n if (v8 > *v6 - v9) v8 = *v6 - v9;\n ++v6;\n } while ((int *)v7 != v6);\n return (unsigned int)v8;\n}" + }, + { + "index": 763, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int i, j, temp;\n for (i = 0; i < n - 1; i++) {\n for (j = 0; j < n - i - 1; j++) {\n if (arr[j] > arr[j + 1]) {\n temp = arr[j];\n arr[j] = arr[j + 1];\n arr[j + 1] = temp;\n }\n }\n }\n int diff = __INT_MAX__;\n for (i = 0; i < n - 1; i++) {\n if (arr[i + 1] - arr[i] < diff) {\n diff = arr[i + 1] - arr[i];\n }\n }\n return diff;\n}", + "test": "int main() {\n\n int arr1[] = {1, 5, 3, 19, 18, 25};\n\n int arr2[] = {4, 3, 2, 6};\n\n int arr3[] = {30, 5, 20, 9};\n\n \n\n assert(func0(arr1, 6) == 1);\n\n assert(func0(arr2, 4) == 1);\n\n assert(func0(arr3, 4) == 4);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nlea -0x1(%rsi),%r10d\ntest %r10d,%r10d\njle 1448 \nmov %r10d,%edx\nlea 0x4(%rdi),%r11\nnopl 0x0(%rax,%rax,1)\nsub $0x1,%edx\nmov %rdi,%rax\nmov %rdx,%r9\nlea (%r11,%rdx,4),%r8\nnopl (%rax)\nmov (%rax),%edx\nmov 0x4(%rax),%ecx\ncmp %ecx,%edx\njle 12ae \nmov %ecx,(%rax)\nmov %edx,0x4(%rax)\nadd $0x4,%rax\ncmp %r8,%rax\njne 12a0 \nmov %r9d,%edx\ntest %r9d,%r9d\njne 1290 \nlea -0x2(%rsi),%r8d\ncmp $0x2,%r8d\njbe 144f \nmov %r10d,%edx\nmovdqa 0xdb8(%rip),%xmm0\nmov %rdi,%rax\nshr $0x2,%edx\nshl $0x4,%rdx\nadd %rdi,%rdx\nnopl (%rax)\nmovdqu 0x4(%rax),%xmm2\nmovdqu (%rax),%xmm3\nadd $0x10,%rax\npsubd %xmm3,%xmm2\nmovdqa %xmm2,%xmm1\npcmpgtd %xmm0,%xmm1\npand %xmm1,%xmm0\npandn %xmm2,%xmm1\npor %xmm1,%xmm0\ncmp %rdx,%rax\njne 12e8 \nmovdqa %xmm0,%xmm2\nmov %r10d,%ecx\npsrldq $0x8,%xmm2\nand $0xfffffffc,%ecx\nmovdqa %xmm2,%xmm1\npcmpgtd %xmm0,%xmm1\npand %xmm1,%xmm0\npandn %xmm2,%xmm1\npor %xmm1,%xmm0\nmovdqa %xmm0,%xmm2\npsrldq $0x4,%xmm2\nmovdqa %xmm2,%xmm1\npcmpgtd %xmm0,%xmm1\npand %xmm1,%xmm0\npandn %xmm2,%xmm1\npor %xmm1,%xmm0\nmovd %xmm0,%eax\ntest $0x3,%r10b\nje 144e \nmovslq %ecx,%rdx\nlea 0x1(%rcx),%r9d\nshl $0x2,%rdx\nlea (%rdi,%rdx,1),%r11\ncmp %r8d,%r9d\njge 145b \ncmp $0x80000001,%esi\nje 145b \nmov 0x4(%rdi,%rdx,1),%r9d\nmov %r9d,%esi\nsub (%r11),%esi\nmov 0x8(%rdi,%rdx,1),%r11d\ncmp %eax,%esi\ncmovle %esi,%eax\nmov %r11d,%esi\nsub %r9d,%esi\nlea 0x3(%rcx),%r9d\ncmp %eax,%esi\ncmovle %esi,%eax\nlea 0x2(%rcx),%esi\ncmp %r9d,%r8d\njg 13f8 \nmovslq %esi,%rdx\nadd $0x1,%rdx\nmov (%rdi,%rdx,4),%ecx\nsub -0x4(%rdi,%rdx,4),%ecx\nlea 0x0(,%rdx,4),%r8\ncmp %ecx,%eax\ncmovg %ecx,%eax\nlea 0x1(%rsi),%ecx\ncmp %ecx,%r10d\njle 144d \nmov 0x4(%rdi,%r8,1),%ecx\nsub (%rdi,%rdx,4),%ecx\ncmp %ecx,%eax\ncmovg %ecx,%eax\nadd $0x2,%esi\ncmp %esi,%r10d\njle 144d \nmov 0x8(%rdi,%r8,1),%edx\nsub 0x4(%rdi,%r8,1),%edx\ncmp %edx,%eax\ncmovg %edx,%eax\nretq\nmov 0xc(%rdi,%rdx,1),%r9d\nmov %r9d,%esi\nsub %r11d,%esi\nmov 0x10(%rdi,%rdx,1),%r11d\ncmp %eax,%esi\ncmovle %esi,%eax\nmov %r11d,%esi\nsub %r9d,%esi\nlea 0x5(%rcx),%r9d\ncmp %eax,%esi\ncmovle %esi,%eax\nlea 0x4(%rcx),%esi\ncmp %r9d,%r8d\njle 13b0 \nmov 0x14(%rdi,%rdx,1),%r8d\nmov 0x18(%rdi,%rdx,1),%edx\nmov %r8d,%esi\nsub %r11d,%esi\ncmp %eax,%esi\ncmovle %esi,%eax\nsub %r8d,%edx\nlea 0x6(%rcx),%esi\ncmp %eax,%edx\ncmovle %edx,%eax\njmpq 13b0 \nmov $0x7fffffff,%eax\nretq\nretq\nmov $0x7fffffff,%eax\nxor %ecx,%ecx\njmpq 1360 \nmov %ecx,%esi\njmpq 13b0 \nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\nlea r11d, [rsi-1]\ntest r11d, r11d\njle loc_146D\npush rbp\nmov r8d, esi\nmov r10, rdi\npush rbx\nmov ebx, esi\nlea rsi, [rdi+4]\nnop\nloc_1290:\ncmp r8d, 1\njle loc_1410\nlea eax, [r8-2]\nmov r9, r10\nlea rdi, [rsi+rax*4]\nmov rax, r10\nnop dword ptr [rax+rax+00000000h]\nloc_12B0:\nmovq xmm0, qword ptr [rax]\npshufd xmm3, xmm0, 0E5h\nmovd edx, xmm0\nmovd ecx, xmm3\ncmp ecx, edx\njge short loc_12CE\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_12CE:\nadd rax, 4\ncmp rax, rdi\njnz short loc_12B0\nsub r8d, 1\ncmp r8d, 1\njnz short loc_1290\nsub ebx, 2\ncmp ebx, 2\njbe loc_1473\nmov eax, r11d\nmovdqa xmm0, cs:xmmword_2070\nshr eax, 2\nshl rax, 4\nadd rax, r10\nnop word ptr [rax+rax+00h]\nloc_1308:\nmovdqu xmm2, xmmword ptr [r9+4]\nmovdqu xmm4, xmmword ptr [r9]\nadd r9, 10h\npsubd xmm2, xmm4\nmovdqa xmm1, xmm2\npcmpgtd xmm1, xmm0\npand xmm0, xmm1\npandn xmm1, xmm2\npor xmm0, xmm1\ncmp r9, rax\njnz short loc_1308\nmovdqa xmm2, xmm0\nmov edx, r11d\npsrldq xmm2, 8\nand edx, 0FFFFFFFCh\nmovdqa xmm1, xmm2\npcmpgtd xmm1, xmm0\npand xmm0, xmm1\npandn xmm1, xmm2\npor xmm0, xmm1\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\nmovdqa xmm1, xmm2\npcmpgtd xmm1, xmm0\npand xmm0, xmm1\npandn xmm1, xmm2\npor xmm1, xmm0\nmovd eax, xmm1\ntest r11b, 3\njz loc_1405\nloc_1382:\nmovsxd rcx, edx\nlea esi, [rdx+1]\nshl rcx, 2\nlea rdi, [r10+rcx]\ncmp esi, ebx\njge short loc_13C0\nmov r8d, [r10+rcx+4]\nmov r9d, [r10+rcx+8]\nmov esi, r8d\nsub esi, [rdi]\nmov edi, r9d\nsub edi, r8d\ncmp esi, edi\ncmovg esi, edi\ncmp eax, esi\ncmovg eax, esi\nlea esi, [rdx+3]\ncmp ebx, esi\njg short loc_1419\nadd edx, 2\nlea esi, [rdx+1]\nloc_13C0:\nmovsxd rcx, esi\nmov r8d, [r10+rcx*4]\nlea rdi, ds:0[rcx*4]\nmov ebx, r8d\nsub ebx, [r10+rcx*4-4]\ncmp eax, ebx\ncmovg eax, ebx\ncmp r11d, esi\njle short loc_1405\nmov ecx, [r10+rdi+4]\nsub ecx, r8d\ncmp eax, ecx\ncmovg eax, ecx\nadd edx, 2\ncmp r11d, edx\njle short loc_1405\nmov edx, [r10+rdi+8]\nsub edx, [r10+rdi+4]\ncmp eax, edx\ncmovg eax, edx\nloc_1405:\npop rbx\npop rbp\nretn\nloc_1410:\nsub r8d, 1\njmp loc_1290\nloc_1419:\nmov ebp, [r10+rcx+0Ch]\nmov r8d, [r10+rcx+10h]\nmov esi, ebp\nmov edi, r8d\nsub esi, r9d\nsub edi, ebp\ncmp esi, edi\ncmovg esi, edi\ncmp eax, esi\ncmovg eax, esi\nlea esi, [rdx+5]\ncmp ebx, esi\njle short loc_1462\nmov esi, [r10+rcx+14h]\nmov ecx, [r10+rcx+18h]\nsub ecx, esi\nsub esi, r8d\ncmp ecx, esi\ncmovg ecx, esi\ncmp eax, ecx\ncmovg eax, ecx\nadd edx, 6\nlea esi, [rdx+1]\njmp loc_13C0\nloc_1462:\nadd edx, 4\nlea esi, [rdx+1]\njmp loc_13C0\nloc_146D:\nmov eax, 7FFFFFFFh\nretn\nloc_1473:\nmov eax, 7FFFFFFFh\nxor edx, edx\njmp loc_1382", + "ida_pseudo": "__int64 __fastcall func0(__m128i *a1, int a2)\n{\n int v2; // r11d\n int v3; // r8d\n __m128i *v4; // r9\n __m128i *v5; // rax\n __m128i v6; // xmm0\n int v7; // ebx\n __m128i si128; // xmm0\n __m128i v9; // xmm2\n __m128i v10; // xmm4\n __m128i v11; // xmm2\n __m128i v12; // xmm1\n __m128i v13; // xmm2\n signed int v14; // edx\n __m128i v15; // xmm1\n __m128i v16; // xmm0\n __m128i v17; // xmm2\n __m128i v18; // xmm1\n __int64 result; // rax\n int v20; // esi\n __int64 v21; // rcx\n int v22; // esi\n int v23; // ebx\n int v24; // ecx\n int v25; // edx\n __int32 v26; // r8d\n int v27; // esi\n __int32 v28; // esi\n int v29; // ecx\n int v30; // esi\n\n v2 = a2 - 1;\n if ( a2 - 1 <= 0 )\n return 0x7FFFFFFFLL;\n v3 = a2;\n do\n {\n while ( v3 <= 1 )\n --v3;\n v4 = a1;\n v5 = a1;\n do\n {\n v6 = _mm_loadl_epi64(v5);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v6, 229)) < _mm_cvtsi128_si32(v6) )\n v5->m128i_i64[0] = _mm_shuffle_epi32(v6, 225).m128i_u64[0];\n v5 = (__m128i *)((char *)v5 + 4);\n }\n while ( v5 != (__m128i *)((char *)a1->m128i_i64 + 4 * (unsigned int)(v3 - 2) + 4) );\n --v3;\n }\n while ( v3 != 1 );\n v7 = a2 - 2;\n if ( (unsigned int)(a2 - 2) <= 2 )\n {\n result = 0x7FFFFFFFLL;\n v14 = 0;\n }\n else\n {\n si128 = _mm_load_si128((const __m128i *)&xmmword_2070);\n do\n {\n v9 = _mm_loadu_si128((const __m128i *)((char *)v4->m128i_i64 + 4));\n v10 = _mm_loadu_si128(v4++);\n v11 = _mm_sub_epi32(v9, v10);\n v12 = _mm_cmpgt_epi32(v11, si128);\n si128 = _mm_or_si128(_mm_and_si128(si128, v12), _mm_andnot_si128(v12, v11));\n }\n while ( v4 != &a1[(unsigned int)v2 >> 2] );\n v13 = _mm_srli_si128(si128, 8);\n v14 = v2 & 0xFFFFFFFC;\n v15 = _mm_cmpgt_epi32(v13, si128);\n v16 = _mm_or_si128(_mm_and_si128(si128, v15), _mm_andnot_si128(v15, v13));\n v17 = _mm_srli_si128(v16, 4);\n v18 = _mm_cmpgt_epi32(v17, v16);\n result = (unsigned int)_mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v18, v17), _mm_and_si128(v16, v18)));\n if ( (v2 & 3) == 0 )\n return result;\n }\n v20 = v14 + 1;\n v21 = v14;\n if ( v14 + 1 < v7 )\n {\n v22 = a1->m128i_i32[v14 + 1] - a1->m128i_i32[v14];\n if ( v22 > a1->m128i_i32[v21 + 2] - a1->m128i_i32[v21 + 1] )\n v22 = a1->m128i_i32[v21 + 2] - a1->m128i_i32[v21 + 1];\n if ( (int)result > v22 )\n result = (unsigned int)v22;\n if ( v7 > v14 + 3 )\n {\n v26 = a1[1].m128i_i32[v21];\n v27 = a1->m128i_i32[v21 + 3] - a1->m128i_i32[v21 + 2];\n if ( v27 > v26 - a1->m128i_i32[v21 + 3] )\n v27 = a1[1].m128i_i32[v21] - a1->m128i_i32[v21 + 3];\n if ( (int)result > v27 )\n result = (unsigned int)v27;\n if ( v7 <= v14 + 5 )\n {\n v14 += 4;\n v20 = v14 + 1;\n }\n else\n {\n v28 = a1[1].m128i_i32[v21 + 1];\n v29 = a1[1].m128i_i32[v21 + 2] - v28;\n v30 = v28 - v26;\n if ( v29 > v30 )\n v29 = v30;\n if ( (int)result > v29 )\n result = (unsigned int)v29;\n v14 += 6;\n v20 = v14 + 1;\n }\n }\n else\n {\n v14 += 2;\n v20 = v14 + 1;\n }\n }\n v23 = a1->m128i_i32[v20] - a1->m128i_i32[v20 - 1];\n if ( (int)result > v23 )\n result = (unsigned int)v23;\n if ( v2 > v20 )\n {\n v24 = a1->m128i_i32[v20 + 1] - a1->m128i_i32[v20];\n if ( (int)result > v24 )\n result = (unsigned int)v24;\n if ( v2 > v14 + 2 )\n {\n v25 = a1->m128i_i32[v20 + 2] - a1->m128i_i32[v20 + 1];\n if ( (int)result > v25 )\n return (unsigned int)v25;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1270:\nendbr64\nlea r11d, [rsi-1]\ntest r11d, r11d\njle loc_146D\npush rbp\nmov r8d, esi\nmov r10, rdi\npush rbx\nmov ebx, esi\nlea rsi, [rdi+4]\nnop\nloc_1290:\ncmp r8d, 1\njle loc_1410\nlea eax, [r8-2]\nmov r9, r10\nlea rdi, [rsi+rax*4]\nmov rax, r10\nnop dword ptr [rax+rax+00000000h]\nloc_12B0:\nmovq xmm0, qword ptr [rax]\npshufd xmm3, xmm0, 0E5h\nmovd edx, xmm0\nmovd ecx, xmm3\ncmp ecx, edx\njge short loc_12CE\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_12CE:\nadd rax, 4\ncmp rax, rdi\njnz short loc_12B0\nsub r8d, 1\ncmp r8d, 1\njnz short loc_1290\nsub ebx, 2\ncmp ebx, 2\njbe loc_1473\nmov eax, r11d\nmovdqa xmm0, cs:xmmword_2070\nshr eax, 2\nshl rax, 4\nadd rax, r10\nnop word ptr [rax+rax+00h]\nloc_1308:\nmovdqu xmm2, xmmword ptr [r9+4]\nmovdqu xmm4, xmmword ptr [r9]\nadd r9, 10h\npsubd xmm2, xmm4\nmovdqa xmm1, xmm2\npcmpgtd xmm1, xmm0\npand xmm0, xmm1\npandn xmm1, xmm2\npor xmm0, xmm1\ncmp r9, rax\njnz short loc_1308\nmovdqa xmm2, xmm0\nmov edx, r11d\npsrldq xmm2, 8\nand edx, 0FFFFFFFCh\nmovdqa xmm1, xmm2\npcmpgtd xmm1, xmm0\npand xmm0, xmm1\npandn xmm1, xmm2\npor xmm0, xmm1\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\nmovdqa xmm1, xmm2\npcmpgtd xmm1, xmm0\npand xmm0, xmm1\npandn xmm1, xmm2\npor xmm1, xmm0\nmovd eax, xmm1\ntest r11b, 3\njz loc_1405\nloc_1382:\nmovsxd rcx, edx\nlea esi, [rdx+1]\nshl rcx, 2\nlea rdi, [r10+rcx]\ncmp esi, ebx\njge short loc_13C0\nmov r8d, [r10+rcx+4]\nmov r9d, [r10+rcx+8]\nmov esi, r8d\nsub esi, [rdi]\nmov edi, r9d\nsub edi, r8d\ncmp esi, edi\ncmovg esi, edi\ncmp eax, esi\ncmovg eax, esi\nlea esi, [rdx+3]\ncmp ebx, esi\njg short loc_1419\nadd edx, 2\nlea esi, [rdx+1]\nloc_13C0:\nmovsxd rcx, esi\nmov r8d, [r10+rcx*4]\nlea rdi, ds:0[rcx*4]\nmov ebx, r8d\nsub ebx, [r10+rcx*4-4]\ncmp eax, ebx\ncmovg eax, ebx\ncmp r11d, esi\njle short loc_1405\nmov ecx, [r10+rdi+4]\nsub ecx, r8d\ncmp eax, ecx\ncmovg eax, ecx\nadd edx, 2\ncmp r11d, edx\njle short loc_1405\nmov edx, [r10+rdi+8]\nsub edx, [r10+rdi+4]\ncmp eax, edx\ncmovg eax, edx\nloc_1405:\npop rbx\npop rbp\nretn\nloc_1410:\nsub r8d, 1\njmp loc_1290\nloc_1419:\nmov ebp, [r10+rcx+0Ch]\nmov r8d, [r10+rcx+10h]\nmov esi, ebp\nmov edi, r8d\nsub esi, r9d\nsub edi, ebp\ncmp esi, edi\ncmovg esi, edi\ncmp eax, esi\ncmovg eax, esi\nlea esi, [rdx+5]\ncmp ebx, esi\njle short loc_1462\nmov esi, [r10+rcx+14h]\nmov ecx, [r10+rcx+18h]\nsub ecx, esi\nsub esi, r8d\ncmp ecx, esi\ncmovg ecx, esi\ncmp eax, ecx\ncmovg eax, ecx\nadd edx, 6\nlea esi, [rdx+1]\njmp loc_13C0\nloc_1462:\nadd edx, 4\nlea esi, [rdx+1]\njmp loc_13C0\nloc_146D:\nmov eax, 7FFFFFFFh\nretn\nloc_1473:\nmov eax, 7FFFFFFFh\nxor edx, edx\njmp loc_1382", + "ida_strip_pseudo": "__int64 __fastcall sub_1270(__m128i *a1, int a2)\n{\n int v2; // r11d\n int v3; // r8d\n __m128i *v4; // r9\n __m128i *v5; // rax\n __m128i v6; // xmm0\n int v7; // ebx\n __m128i si128; // xmm0\n __m128i v9; // xmm2\n __m128i v10; // xmm4\n __m128i v11; // xmm2\n __m128i v12; // xmm1\n __m128i v13; // xmm2\n signed int v14; // edx\n __m128i v15; // xmm1\n __m128i v16; // xmm0\n __m128i v17; // xmm2\n __m128i v18; // xmm1\n __int64 result; // rax\n int v20; // esi\n __int64 v21; // rcx\n int v22; // esi\n int v23; // ebx\n int v24; // ecx\n int v25; // edx\n __int32 v26; // r8d\n int v27; // esi\n __int32 v28; // esi\n int v29; // ecx\n int v30; // esi\n\n v2 = a2 - 1;\n if ( a2 - 1 <= 0 )\n return 0x7FFFFFFFLL;\n v3 = a2;\n do\n {\n while ( v3 <= 1 )\n --v3;\n v4 = a1;\n v5 = a1;\n do\n {\n v6 = _mm_loadl_epi64(v5);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v6, 229)) < _mm_cvtsi128_si32(v6) )\n v5->m128i_i64[0] = _mm_shuffle_epi32(v6, 225).m128i_u64[0];\n v5 = (__m128i *)((char *)v5 + 4);\n }\n while ( v5 != (__m128i *)((char *)a1->m128i_i64 + 4 * (unsigned int)(v3 - 2) + 4) );\n --v3;\n }\n while ( v3 != 1 );\n v7 = a2 - 2;\n if ( (unsigned int)(a2 - 2) <= 2 )\n {\n result = 0x7FFFFFFFLL;\n v14 = 0;\n }\n else\n {\n si128 = _mm_load_si128((const __m128i *)&xmmword_2070);\n do\n {\n v9 = _mm_loadu_si128((const __m128i *)((char *)v4->m128i_i64 + 4));\n v10 = _mm_loadu_si128(v4++);\n v11 = _mm_sub_epi32(v9, v10);\n v12 = _mm_cmpgt_epi32(v11, si128);\n si128 = _mm_or_si128(_mm_and_si128(si128, v12), _mm_andnot_si128(v12, v11));\n }\n while ( v4 != &a1[(unsigned int)v2 >> 2] );\n v13 = _mm_srli_si128(si128, 8);\n v14 = v2 & 0xFFFFFFFC;\n v15 = _mm_cmpgt_epi32(v13, si128);\n v16 = _mm_or_si128(_mm_and_si128(si128, v15), _mm_andnot_si128(v15, v13));\n v17 = _mm_srli_si128(v16, 4);\n v18 = _mm_cmpgt_epi32(v17, v16);\n result = (unsigned int)_mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v18, v17), _mm_and_si128(v16, v18)));\n if ( (v2 & 3) == 0 )\n return result;\n }\n v20 = v14 + 1;\n v21 = v14;\n if ( v14 + 1 < v7 )\n {\n v22 = a1->m128i_i32[v14 + 1] - a1->m128i_i32[v14];\n if ( v22 > a1->m128i_i32[v21 + 2] - a1->m128i_i32[v21 + 1] )\n v22 = a1->m128i_i32[v21 + 2] - a1->m128i_i32[v21 + 1];\n if ( (int)result > v22 )\n result = (unsigned int)v22;\n if ( v7 > v14 + 3 )\n {\n v26 = a1[1].m128i_i32[v21];\n v27 = a1->m128i_i32[v21 + 3] - a1->m128i_i32[v21 + 2];\n if ( v27 > v26 - a1->m128i_i32[v21 + 3] )\n v27 = a1[1].m128i_i32[v21] - a1->m128i_i32[v21 + 3];\n if ( (int)result > v27 )\n result = (unsigned int)v27;\n if ( v7 <= v14 + 5 )\n {\n v14 += 4;\n v20 = v14 + 1;\n }\n else\n {\n v28 = a1[1].m128i_i32[v21 + 1];\n v29 = a1[1].m128i_i32[v21 + 2] - v28;\n v30 = v28 - v26;\n if ( v29 > v30 )\n v29 = v30;\n if ( (int)result > v29 )\n result = (unsigned int)v29;\n v14 += 6;\n v20 = v14 + 1;\n }\n }\n else\n {\n v14 += 2;\n v20 = v14 + 1;\n }\n }\n v23 = a1->m128i_i32[v20] - a1->m128i_i32[v20 - 1];\n if ( (int)result > v23 )\n result = (unsigned int)v23;\n if ( v2 > v20 )\n {\n v24 = a1->m128i_i32[v20 + 1] - a1->m128i_i32[v20];\n if ( (int)result > v24 )\n result = (unsigned int)v24;\n if ( v2 > v14 + 2 )\n {\n v25 = a1->m128i_i32[v20 + 2] - a1->m128i_i32[v20 + 1];\n if ( (int)result > v25 )\n return (unsigned int)v25;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1270(__m128i *a1, int a2) {\n int v2;\n int v3;\n __m128i *v4;\n __m128i *v5;\n __m128i v6;\n int v7;\n __m128i si128;\n __m128i v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n signed int v14;\n __m128i v15;\n __m128i v16;\n __m128i v17;\n __m128i v18;\n long long result;\n int v20;\n long long v21;\n int v22;\n int v23;\n int v24;\n int v25;\n int v26;\n int v27;\n int v28;\n int v29;\n int v30;\n v2 = a2 - 1;\n if (a2 - 1 <= 0) return 2147483647LL;\n v3 = a2;\n do {\n while (v3 <= 1) --v3;\n v4 = a1;\n v5 = a1;\n do {\n v6 = _mm_loadl_epi64(v5);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v6, 229)) < _mm_cvtsi128_si32(v6))\n v5->m128i_i64[0] = _mm_shuffle_epi32(v6, 225).m128i_u64[0];\n v5 = (__m128i *)((char *)v5 + 4);\n } while (v5 != (__m128i *)((char *)a1->m128i_i64 +\n 4 * (unsigned int)(v3 - 2) + 4));\n --v3;\n } while (v3 != 1);\n v7 = a2 - 2;\n if ((unsigned int)(a2 - 2) <= 2) {\n result = 2147483647LL;\n v14 = 0;\n } else {\n si128 = _mm_load_si128((const __m128i *)&xmmword_2070);\n do {\n v9 = _mm_loadu_si128((const __m128i *)((char *)v4->m128i_i64 + 4));\n v10 = _mm_loadu_si128(v4++);\n v11 = _mm_sub_epi32(v9, v10);\n v12 = _mm_cmpgt_epi32(v11, si128);\n si128 =\n _mm_or_si128(_mm_and_si128(si128, v12), _mm_andnot_si128(v12, v11));\n } while (v4 != &a1[(unsigned int)v2 >> 2]);\n v13 = _mm_srli_si128(si128, 8);\n v14 = v2 & 4294967292;\n v15 = _mm_cmpgt_epi32(v13, si128);\n v16 = _mm_or_si128(_mm_and_si128(si128, v15), _mm_andnot_si128(v15, v13));\n v17 = _mm_srli_si128(v16, 4);\n v18 = _mm_cmpgt_epi32(v17, v16);\n result = (unsigned int)_mm_cvtsi128_si32(\n _mm_or_si128(_mm_andnot_si128(v18, v17), _mm_and_si128(v16, v18)));\n if ((v2 & 3) == 0) return result;\n }\n v20 = v14 + 1;\n v21 = v14;\n if (v14 + 1 < v7) {\n v22 = a1->m128i_i32[v14 + 1] - a1->m128i_i32[v14];\n if (v22 > a1->m128i_i32[v21 + 2] - a1->m128i_i32[v21 + 1])\n v22 = a1->m128i_i32[v21 + 2] - a1->m128i_i32[v21 + 1];\n if ((int)result > v22) result = (unsigned int)v22;\n if (v7 > v14 + 3) {\n v26 = a1[1].m128i_i32[v21];\n v27 = a1->m128i_i32[v21 + 3] - a1->m128i_i32[v21 + 2];\n if (v27 > v26 - a1->m128i_i32[v21 + 3])\n v27 = a1[1].m128i_i32[v21] - a1->m128i_i32[v21 + 3];\n if ((int)result > v27) result = (unsigned int)v27;\n if (v7 <= v14 + 5) {\n v14 += 4;\n v20 = v14 + 1;\n } else {\n v28 = a1[1].m128i_i32[v21 + 1];\n v29 = a1[1].m128i_i32[v21 + 2] - v28;\n v30 = v28 - v26;\n if (v29 > v30) v29 = v30;\n if ((int)result > v29) result = (unsigned int)v29;\n v14 += 6;\n v20 = v14 + 1;\n }\n } else {\n v14 += 2;\n v20 = v14 + 1;\n }\n }\n v23 = a1->m128i_i32[v20] - a1->m128i_i32[v20 - 1];\n if ((int)result > v23) result = (unsigned int)v23;\n if (v2 > v20) {\n v24 = a1->m128i_i32[v20 + 1] - a1->m128i_i32[v20];\n if ((int)result > v24) result = (unsigned int)v24;\n if (v2 > v14 + 2) {\n v25 = a1->m128i_i32[v20 + 2] - a1->m128i_i32[v20 + 1];\n if ((int)result > v25) return (unsigned int)v25;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(__m128i *a1, int a2) {\n int v2;\n int v3;\n __m128i *v4;\n __m128i *v5;\n __m128i v6;\n int v7;\n __m128i si128;\n __m128i v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n signed int v14;\n __m128i v15;\n __m128i v16;\n __m128i v17;\n __m128i v18;\n long long result;\n int v20;\n long long v21;\n int v22;\n int v23;\n int v24;\n int v25;\n int v26;\n int v27;\n int v28;\n int v29;\n int v30;\n v2 = a2 - 1;\n if (a2 - 1 <= 0) return 2147483647LL;\n v3 = a2;\n do {\n while (v3 <= 1) --v3;\n v4 = a1;\n v5 = a1;\n do {\n v6 = _mm_loadl_epi64(v5);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v6, 229)) < _mm_cvtsi128_si32(v6))\n v5->m128i_i64[0] = _mm_shuffle_epi32(v6, 225).m128i_u64[0];\n v5 = (__m128i *)((char *)v5 + 4);\n } while (v5 != (__m128i *)((char *)a1->m128i_i64 +\n 4 * (unsigned int)(v3 - 2) + 4));\n --v3;\n } while (v3 != 1);\n v7 = a2 - 2;\n if ((unsigned int)(a2 - 2) <= 2) {\n result = 2147483647LL;\n v14 = 0;\n } else {\n si128 = _mm_load_si128((const __m128i *)&xmmword_2070);\n do {\n v9 = _mm_loadu_si128((const __m128i *)((char *)v4->m128i_i64 + 4));\n v10 = _mm_loadu_si128(v4++);\n v11 = _mm_sub_epi32(v9, v10);\n v12 = _mm_cmpgt_epi32(v11, si128);\n si128 =\n _mm_or_si128(_mm_and_si128(si128, v12), _mm_andnot_si128(v12, v11));\n } while (v4 != &a1[(unsigned int)v2 >> 2]);\n v13 = _mm_srli_si128(si128, 8);\n v14 = v2 & 4294967292;\n v15 = _mm_cmpgt_epi32(v13, si128);\n v16 = _mm_or_si128(_mm_and_si128(si128, v15), _mm_andnot_si128(v15, v13));\n v17 = _mm_srli_si128(v16, 4);\n v18 = _mm_cmpgt_epi32(v17, v16);\n result = (unsigned int)_mm_cvtsi128_si32(\n _mm_or_si128(_mm_andnot_si128(v18, v17), _mm_and_si128(v16, v18)));\n if ((v2 & 3) == 0) return result;\n }\n v20 = v14 + 1;\n v21 = v14;\n if (v14 + 1 < v7) {\n v22 = a1->m128i_i32[v14 + 1] - a1->m128i_i32[v14];\n if (v22 > a1->m128i_i32[v21 + 2] - a1->m128i_i32[v21 + 1])\n v22 = a1->m128i_i32[v21 + 2] - a1->m128i_i32[v21 + 1];\n if ((int)result > v22) result = (unsigned int)v22;\n if (v7 > v14 + 3) {\n v26 = a1[1].m128i_i32[v21];\n v27 = a1->m128i_i32[v21 + 3] - a1->m128i_i32[v21 + 2];\n if (v27 > v26 - a1->m128i_i32[v21 + 3])\n v27 = a1[1].m128i_i32[v21] - a1->m128i_i32[v21 + 3];\n if ((int)result > v27) result = (unsigned int)v27;\n if (v7 <= v14 + 5) {\n v14 += 4;\n v20 = v14 + 1;\n } else {\n v28 = a1[1].m128i_i32[v21 + 1];\n v29 = a1[1].m128i_i32[v21 + 2] - v28;\n v30 = v28 - v26;\n if (v29 > v30) v29 = v30;\n if ((int)result > v29) result = (unsigned int)v29;\n v14 += 6;\n v20 = v14 + 1;\n }\n } else {\n v14 += 2;\n v20 = v14 + 1;\n }\n }\n v23 = a1->m128i_i32[v20] - a1->m128i_i32[v20 - 1];\n if ((int)result > v23) result = (unsigned int)v23;\n if (v2 > v20) {\n v24 = a1->m128i_i32[v20 + 1] - a1->m128i_i32[v20];\n if ((int)result > v24) result = (unsigned int)v24;\n if (v2 > v14 + 2) {\n v25 = a1->m128i_i32[v20 + 2] - a1->m128i_i32[v20 + 1];\n if ((int)result > v25) return (unsigned int)v25;\n }\n }\n return result;\n}" + }, + { + "index": 764, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char str[]) {\n int number_ctr = 0;\n for (int i = 0; i < strlen(str); i++) {\n if (str[i] >= '0' && str[i] <= '9') {\n number_ctr += 1;\n }\n }\n return number_ctr;\n}", + "test": "int main() {\n\n assert(func0(\"program2bedone\") == 1);\n\n assert(func0(\"3wonders\") == 1);\n\n assert(func0(\"123\") == 3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x28,%rsp\nmov %rdi,-0x28(%rbp)\nmovl $0x0,-0x18(%rbp)\nmovl $0x0,-0x14(%rbp)\njmp 11ba \nmov -0x14(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x2f,%al\njle 11b6 \nmov -0x14(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x39,%al\njg 11b6 \naddl $0x1,-0x18(%rbp)\naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\nmovslq %eax,%rbx\nmov -0x28(%rbp),%rax\nmov %rax,%rdi\ncallq 1060 \ncmp %rax,%rbx\njb 118a \nmov -0x18(%rbp),%eax\nadd $0x28,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+s], rdi\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp short loc_11BA\nloc_118A:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 2Fh ; '/'\njle short loc_11B6\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 39h ; '9'\njg short loc_11B6\nadd [rbp+var_18], 1\nloc_11B6:\nadd [rbp+var_14], 1\nloc_11BA:\nmov eax, [rbp+var_14]\nmovsxd rbx, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rbx, rax\njb short loc_118A\nmov eax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n unsigned int v2; // [rsp+18h] [rbp-18h]\n int i; // [rsp+1Ch] [rbp-14h]\n\n v2 = 0;\n for ( i = 0; i < strlen(a1); ++i )\n {\n if ( a1[i] > 47 && a1[i] <= 57 )\n ++v2;\n }\n return v2;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+s], rdi\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp short loc_11BA\nloc_118A:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 2Fh ; '/'\njle short loc_11B6\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 39h ; '9'\njg short loc_11B6\nadd [rbp+var_18], 1\nloc_11B6:\nadd [rbp+var_14], 1\nloc_11BA:\nmov eax, [rbp+var_14]\nmovsxd rbx, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rbx, rax\njb short loc_118A\nmov eax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1)\n{\n unsigned int v2; // [rsp+18h] [rbp-18h]\n int i; // [rsp+1Ch] [rbp-14h]\n\n v2 = 0;\n for ( i = 0; i < strlen(a1); ++i )\n {\n if ( a1[i] > 47 && a1[i] <= 57 )\n ++v2;\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1) {\n unsigned int v2;\n int i;\n v2 = 0;\n for (i = 0; i < strlen(a1); ++i) {\n if (a1[i] > 47 && a1[i] <= 57) ++v2;\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n unsigned int v2;\n int i;\n v2 = 0;\n for (i = 0; i < strlen(a1); ++i) {\n if (a1[i] > 47 && a1[i] <= 57) ++v2;\n }\n return v2;\n}" + }, + { + "index": 764, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char str[]) {\n int number_ctr = 0;\n for (int i = 0; i < strlen(str); i++) {\n if (str[i] >= '0' && str[i] <= '9') {\n number_ctr += 1;\n }\n }\n return number_ctr;\n}", + "test": "int main() {\n\n assert(func0(\"program2bedone\") == 1);\n\n assert(func0(\"3wonders\") == 1);\n\n assert(func0(\"123\") == 3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%rsi\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nmov %rsi,%rdx\nlea -0x1(%rsi,%rcx,1),%rsi\nmov $0x0,%ecx\ncmp %rsi,%rdx\nje 1184 \nmovzbl (%rdx),%eax\nsub $0x30,%eax\ncmp $0xa,%al\nadc $0x0,%ecx\nadd $0x1,%rdx\njmp 116e \nmov %ecx,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmov rdi, rax\nmov rax, rbx\nadd rdi, rbx\nmov ecx, 0\njmp short loc_1196\nloc_1186:\nmovzx esi, byte ptr [rax]\nlea edx, [rsi-30h]\ncmp dl, 0Ah\nadc ecx, 0\nadd rax, 1\nloc_1196:\ncmp rax, rdi\njnz short loc_1186\nmov eax, ecx\npop rbx\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n size_t v2; // rdi\n const char *v3; // rax\n const char *v4; // rdi\n unsigned int v5; // ecx\n\n v2 = strlen(a1);\n v3 = a1;\n v4 = &a1[v2];\n v5 = 0;\n while ( v3 != v4 )\n v5 += (unsigned __int8)(*v3++ - 48) < 0xAu;\n return v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmov rdi, rax\nmov rax, rbx\nadd rdi, rbx\nmov ecx, 0\njmp short loc_1196\nloc_1186:\nmovzx esi, byte ptr [rax]\nlea edx, [rsi-30h]\ncmp dl, 0Ah\nadc ecx, 0\nadd rax, 1\nloc_1196:\ncmp rax, rdi\njnz short loc_1186\nmov eax, ecx\npop rbx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1)\n{\n size_t v2; // rdi\n const char *v3; // rax\n const char *v4; // rdi\n unsigned int v5; // ecx\n\n v2 = strlen(a1);\n v3 = a1;\n v4 = &a1[v2];\n v5 = 0;\n while ( v3 != v4 )\n v5 += (unsigned __int8)(*v3++ - 48) < 0xAu;\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1) {\n unsigned int v2;\n const char *v3;\n const char *v4;\n unsigned int v5;\n v2 = strlen(a1);\n v3 = a1;\n v4 = &a1[v2];\n v5 = 0;\n while (v3 != v4) v5 += (unsigned char)(*v3++ - 48) < 10u;\n return v5;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n unsigned int v2;\n const char *v3;\n const char *v4;\n unsigned int v5;\n v2 = strlen(a1);\n v3 = a1;\n v4 = &a1[v2];\n v5 = 0;\n while (v3 != v4) v5 += (unsigned char)(*v3++ - 48) < 10u;\n return v5;\n}" + }, + { + "index": 764, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char str[]) {\n int number_ctr = 0;\n for (int i = 0; i < strlen(str); i++) {\n if (str[i] >= '0' && str[i] <= '9') {\n number_ctr += 1;\n }\n }\n return number_ctr;\n}", + "test": "int main() {\n\n assert(func0(\"program2bedone\") == 1);\n\n assert(func0(\"3wonders\") == 1);\n\n assert(func0(\"123\") == 3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\ncallq 1060 \nmov %rbx,%rdi\nlea (%rbx,%rax,1),%rcx\nxor %eax,%eax\njmp 1240 \nnopl 0x0(%rax,%rax,1)\nmovzbl (%rdi),%esi\nlea -0x30(%rsi),%edx\ncmp $0xa,%dl\nadc $0x0,%eax\nadd $0x1,%rdi\ncmp %rcx,%rdi\njne 1230 \npop %rbx\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest rax, rax\njz short loc_1250\nlea rcx, [rbx+rax]\nmov rdi, rbx\nxor eax, eax\nnop dword ptr [rax+rax+00h]\nloc_1230:\nmovzx esi, byte ptr [rdi]\nlea edx, [rsi-30h]\ncmp dl, 0Ah\nadc eax, 0\nadd rdi, 1\ncmp rcx, rdi\njnz short loc_1230\npop rbx\nretn\nloc_1250:\nxor eax, eax\npop rbx\nretn", + "ida_pseudo": "size_t __fastcall func0(const char *a1)\n{\n size_t result; // rax\n const char *v2; // rcx\n\n result = strlen(a1);\n if ( !result )\n return 0LL;\n v2 = &a1[result];\n LODWORD(result) = 0;\n do\n result = ((unsigned __int8)(*a1++ - 48) < 0xAu) + (unsigned int)result;\n while ( v2 != a1 );\n return result;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest rax, rax\njz short loc_1250\nlea rcx, [rbx+rax]\nmov rdi, rbx\nxor eax, eax\nnop dword ptr [rax+rax+00h]\nloc_1230:\nmovzx esi, byte ptr [rdi]\nlea edx, [rsi-30h]\ncmp dl, 0Ah\nadc eax, 0\nadd rdi, 1\ncmp rcx, rdi\njnz short loc_1230\npop rbx\nretn\nloc_1250:\nxor eax, eax\npop rbx\nretn", + "ida_strip_pseudo": "size_t __fastcall sub_1210(const char *a1)\n{\n size_t result; // rax\n const char *v2; // rcx\n\n result = strlen(a1);\n if ( !result )\n return 0LL;\n v2 = &a1[result];\n LODWORD(result) = 0;\n do\n result = ((unsigned __int8)(*a1++ - 48) < 0xAu) + (unsigned int)result;\n while ( v2 != a1 );\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned int sub_1210(const char *a1) {\n unsigned int result;\n const char *v2;\n result = strlen(a1);\n if (!result) return 0LL;\n v2 = &a1[result];\n LODWORD(result) = 0;\n do\n result = ((unsigned char)(*a1++ - 48) < 10u) + (unsigned int)result;\n while (v2 != a1);\n return result;\n}", + "ida_pseudo_norm": "unsigned int func0(const char *a1) {\n unsigned int result;\n const char *v2;\n result = strlen(a1);\n if (!result) return 0LL;\n v2 = &a1[result];\n LODWORD(result) = 0;\n do\n result = ((unsigned char)(*a1++ - 48) < 10u) + (unsigned int)result;\n while (v2 != a1);\n return result;\n}" + }, + { + "index": 764, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char str[]) {\n int number_ctr = 0;\n for (int i = 0; i < strlen(str); i++) {\n if (str[i] >= '0' && str[i] <= '9') {\n number_ctr += 1;\n }\n }\n return number_ctr;\n}", + "test": "int main() {\n\n assert(func0(\"program2bedone\") == 1);\n\n assert(func0(\"3wonders\") == 1);\n\n assert(func0(\"123\") == 3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\ncallq 1060 \ntest %rax,%rax\nje 14b0 \nmov %rax,%rcx\nlea -0x1(%rax),%rax\ncmp $0xe,%rax\njbe 14b4 \nmov %rcx,%rax\nmov %rbx,%rdx\npxor %xmm1,%xmm1\nmovdqa 0xe67(%rip),%xmm7\nand $0xfffffffffffffff0,%rax\nmovdqa 0xe6b(%rip),%xmm6\npxor %xmm4,%xmm4\npxor %xmm3,%xmm3\nmovdqa 0xe6b(%rip),%xmm5\nadd %rbx,%rax\nnopl 0x0(%rax,%rax,1)\nmovdqu (%rdx),%xmm0\nmovdqa %xmm4,%xmm8\nadd $0x10,%rdx\npaddb %xmm7,%xmm0\npsubusb %xmm6,%xmm0\npcmpeqb %xmm4,%xmm0\npand %xmm5,%xmm0\npcmpgtb %xmm0,%xmm8\nmovdqa %xmm0,%xmm2\npunpcklbw %xmm8,%xmm2\npunpckhbw %xmm8,%xmm0\nmovdqa %xmm3,%xmm8\npcmpgtw %xmm2,%xmm8\nmovdqa %xmm2,%xmm9\npunpcklwd %xmm8,%xmm9\npunpckhwd %xmm8,%xmm2\nmovdqa %xmm0,%xmm8\npaddd %xmm9,%xmm1\npaddd %xmm2,%xmm1\nmovdqa %xmm3,%xmm2\npcmpgtw %xmm0,%xmm2\npunpcklwd %xmm2,%xmm8\npunpckhwd %xmm2,%xmm0\npaddd %xmm8,%xmm1\npaddd %xmm0,%xmm1\ncmp %rax,%rdx\njne 1270 \nmovdqa %xmm1,%xmm0\nmov %rcx,%rsi\npsrldq $0x8,%xmm0\nand $0xfffffffffffffff0,%rsi\npaddd %xmm1,%xmm0\nmov %esi,%edx\nmovdqa %xmm0,%xmm1\npsrldq $0x4,%xmm1\npaddd %xmm1,%xmm0\nmovd %xmm0,%eax\ncmp %rsi,%rcx\nje 14a5 \nmovzbl (%rbx,%rsi,1),%esi\nsub $0x30,%esi\ncmp $0xa,%sil\nlea 0x1(%rdx),%esi\nmovslq %esi,%rsi\nadc $0x0,%eax\ncmp %rsi,%rcx\njbe 14a5 \nmovzbl (%rbx,%rsi,1),%esi\nsub $0x30,%esi\ncmp $0xa,%sil\nlea 0x2(%rdx),%esi\nmovslq %esi,%rsi\nadc $0x0,%eax\ncmp %rsi,%rcx\njbe 14a5 \nmovzbl (%rbx,%rsi,1),%esi\nsub $0x30,%esi\ncmp $0xa,%sil\nlea 0x3(%rdx),%esi\nmovslq %esi,%rsi\nadc $0x0,%eax\ncmp %rsi,%rcx\njbe 14a5 \nmovzbl (%rbx,%rsi,1),%esi\nsub $0x30,%esi\ncmp $0xa,%sil\nlea 0x4(%rdx),%esi\nmovslq %esi,%rsi\nadc $0x0,%eax\ncmp %rsi,%rcx\njbe 14a5 \nmovzbl (%rbx,%rsi,1),%esi\nsub $0x30,%esi\ncmp $0xa,%sil\nlea 0x5(%rdx),%esi\nmovslq %esi,%rsi\nadc $0x0,%eax\ncmp %rsi,%rcx\njbe 14a5 \nmovzbl (%rbx,%rsi,1),%esi\nsub $0x30,%esi\ncmp $0xa,%sil\nlea 0x6(%rdx),%esi\nmovslq %esi,%rsi\nadc $0x0,%eax\ncmp %rsi,%rcx\njbe 14a5 \nmovzbl (%rbx,%rsi,1),%esi\nsub $0x30,%esi\ncmp $0xa,%sil\nlea 0x7(%rdx),%esi\nmovslq %esi,%rsi\nadc $0x0,%eax\ncmp %rsi,%rcx\njbe 14a5 \nmovzbl (%rbx,%rsi,1),%esi\nsub $0x30,%esi\ncmp $0xa,%sil\nlea 0x8(%rdx),%esi\nmovslq %esi,%rsi\nadc $0x0,%eax\ncmp %rsi,%rcx\njbe 14a5 \nmovzbl (%rbx,%rsi,1),%esi\nsub $0x30,%esi\ncmp $0xa,%sil\nlea 0x9(%rdx),%esi\nmovslq %esi,%rsi\nadc $0x0,%eax\ncmp %rsi,%rcx\njbe 14a5 \nmovzbl (%rbx,%rsi,1),%esi\nsub $0x30,%esi\ncmp $0xa,%sil\nlea 0xa(%rdx),%esi\nmovslq %esi,%rsi\nadc $0x0,%eax\ncmp %rsi,%rcx\njbe 14a5 \nmovzbl (%rbx,%rsi,1),%esi\nsub $0x30,%esi\ncmp $0xa,%sil\nlea 0xb(%rdx),%esi\nmovslq %esi,%rsi\nadc $0x0,%eax\ncmp %rsi,%rcx\njbe 14a5 \nmovzbl (%rbx,%rsi,1),%esi\nsub $0x30,%esi\ncmp $0xa,%sil\nlea 0xc(%rdx),%esi\nmovslq %esi,%rsi\nadc $0x0,%eax\ncmp %rsi,%rcx\njbe 14a5 \nmovzbl (%rbx,%rsi,1),%esi\nsub $0x30,%esi\ncmp $0xa,%sil\nlea 0xd(%rdx),%esi\nmovslq %esi,%rsi\nadc $0x0,%eax\ncmp %rsi,%rcx\njbe 14a5 \nmovzbl (%rbx,%rsi,1),%esi\nsub $0x30,%esi\ncmp $0xa,%sil\nadc $0x0,%eax\nadd $0xe,%edx\nmovslq %edx,%rdx\ncmp %rdx,%rcx\njbe 14a5 \nmovzbl (%rbx,%rdx,1),%edx\nsub $0x30,%edx\ncmp $0xa,%dl\nadc $0x0,%eax\npop %rbx\nretq\nnopw 0x0(%rax,%rax,1)\nxor %eax,%eax\npop %rbx\nretq\nxor %edx,%edx\nxor %eax,%eax\nxor %esi,%esi\njmpq 1316 \n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest rax, rax\njz loc_1470\nmov rdx, rax\nlea rax, [rax-1]\ncmp rax, 0Eh\njbe loc_1474\nmov rcx, rdx\npxor xmm1, xmm1\npxor xmm3, xmm3\nmov rax, rbx\nand rcx, 0FFFFFFFFFFFFFFF0h\nmovdqa xmm6, cs:xmmword_2090\nmovdqa xmm5, cs:xmmword_20A0\npxor xmm4, xmm4\nlea rsi, [rcx+rbx]\nnop dword ptr [rax+00000000h]\nloc_1268:\nmovdqu xmm2, xmmword ptr [rax]\nmovdqa xmm0, xmm5\nmovdqa xmm7, xmm3\nadd rax, 10h\npaddb xmm2, xmm6\npsubusb xmm0, xmm2\npcmpeqb xmm0, xmm3\npcmpeqb xmm0, xmm3\npcmpgtb xmm7, xmm0\nmovdqa xmm2, xmm0\npunpcklbw xmm2, xmm7\npunpckhbw xmm0, xmm7\nmovdqa xmm7, xmm4\npcmpgtw xmm7, xmm2\nmovdqa xmm8, xmm2\npunpcklwd xmm8, xmm7\npunpckhwd xmm2, xmm7\nmovdqa xmm7, xmm0\npsubd xmm1, xmm8\npsubd xmm1, xmm2\nmovdqa xmm2, xmm4\npcmpgtw xmm2, xmm0\npunpcklwd xmm7, xmm2\npunpckhwd xmm0, xmm2\npsubd xmm1, xmm7\npsubd xmm1, xmm0\ncmp rsi, rax\njnz short loc_1268\nmovdqa xmm0, xmm1\nmov esi, ecx\npsrldq xmm0, 8\npaddd xmm0, xmm1\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\npaddd xmm0, xmm2\nmovd eax, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm1, 8\npaddd xmm1, xmm0\ncmp rdx, rcx\njz loc_1466\nloc_130E:\nmov rdi, rdx\nsub rdi, rcx\nlea r8, [rdi-1]\ncmp r8, 6\njbe loc_13C5\nmovq xmm2, qword ptr cs:xmmword_2090\nmovq xmm0, qword ptr [rbx+rcx]\npaddb xmm0, xmm2\nmovq xmm2, cs:qword_20B0\npminub xmm2, xmm0\npcmpeqb xmm0, xmm2\npxor xmm2, xmm2\npcmpgtb xmm2, xmm0\nmovdqa xmm3, xmm0\npunpcklbw xmm3, xmm2\npunpcklbw xmm0, xmm2\npxor xmm2, xmm2\nmovdqa xmm4, xmm2\nmovdqa xmm5, xmm3\npshufd xmm0, xmm0, 4Eh ; 'N'\npcmpgtw xmm4, xmm3\npcmpgtw xmm2, xmm0\npunpcklwd xmm5, xmm4\npunpcklwd xmm3, xmm4\npsubd xmm1, xmm5\npshufd xmm3, xmm3, 4Eh ; 'N'\npsubd xmm1, xmm3\nmovdqa xmm3, xmm0\npunpcklwd xmm0, xmm2\npunpcklwd xmm3, xmm2\npshufd xmm0, xmm0, 4Eh ; 'N'\npsubd xmm1, xmm3\npsubd xmm1, xmm0\nmovd r8d, xmm1\npshufd xmm6, xmm1, 0E5h\nmovd eax, xmm6\nadd eax, r8d\nmov r8, rdi\nand r8, 0FFFFFFFFFFFFFFF8h\nadd rcx, r8\nadd esi, r8d\nand edi, 7\njz loc_1466\nloc_13C5:\nmovzx ecx, byte ptr [rbx+rcx]\nsub ecx, 30h ; '0'\ncmp cl, 0Ah\nlea ecx, [rsi+1]\nmovsxd rcx, ecx\nadc eax, 0\ncmp rcx, rdx\njnb loc_1466\nmovzx ecx, byte ptr [rbx+rcx]\nsub ecx, 30h ; '0'\ncmp cl, 0Ah\nlea ecx, [rsi+2]\nmovsxd rcx, ecx\nadc eax, 0\ncmp rcx, rdx\njnb short loc_1466\nmovzx ecx, byte ptr [rbx+rcx]\nsub ecx, 30h ; '0'\ncmp cl, 0Ah\nlea ecx, [rsi+3]\nmovsxd rcx, ecx\nadc eax, 0\ncmp rcx, rdx\njnb short loc_1466\nmovzx ecx, byte ptr [rbx+rcx]\nsub ecx, 30h ; '0'\ncmp cl, 0Ah\nlea ecx, [rsi+4]\nmovsxd rcx, ecx\nadc eax, 0\ncmp rcx, rdx\njnb short loc_1466\nmovzx ecx, byte ptr [rbx+rcx]\nsub ecx, 30h ; '0'\ncmp cl, 0Ah\nlea ecx, [rsi+5]\nmovsxd rcx, ecx\nadc eax, 0\ncmp rcx, rdx\njnb short loc_1466\nmovzx ecx, byte ptr [rbx+rcx]\nsub ecx, 30h ; '0'\ncmp cl, 0Ah\nadc eax, 0\nadd esi, 6\nmovsxd rsi, esi\ncmp rsi, rdx\njnb short loc_1466\nmovzx edx, byte ptr [rbx+rsi]\nsub edx, 30h ; '0'\ncmp dl, 0Ah\nadc eax, 0\nloc_1466:\npop rbx\nretn\nloc_1470:\nxor eax, eax\npop rbx\nretn\nloc_1474:\npxor xmm1, xmm1\nxor esi, esi\nxor eax, eax\nxor ecx, ecx\njmp loc_130E", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n size_t v2; // rax\n size_t v3; // rdx\n __m128i v4; // xmm1\n const __m128i *v5; // rax\n unsigned __int64 v6; // rcx\n __m128i si128; // xmm6\n __m128i v8; // xmm5\n __m128i v9; // xmm2\n __m128i v10; // xmm0\n __m128i v11; // xmm7\n __m128i v12; // xmm2\n __m128i v13; // xmm0\n __m128i v14; // xmm7\n __m128i v15; // xmm1\n __m128i v16; // xmm2\n int v17; // esi\n __m128i v18; // xmm0\n __int64 result; // rax\n __m128i v20; // xmm1\n size_t v21; // rdi\n __m128i v22; // xmm0\n __m128i v23; // xmm0\n __m128i v24; // xmm3\n __m128i v25; // xmm0\n __m128i v26; // xmm2\n __m128i v27; // xmm3\n __m128i v28; // xmm1\n bool v29; // cf\n size_t v30; // rcx\n size_t v31; // rcx\n size_t v32; // rcx\n size_t v33; // rcx\n size_t v34; // rcx\n size_t v35; // rsi\n\n v2 = strlen(a1);\n if ( !v2 )\n return 0LL;\n v3 = v2;\n if ( v2 - 1 <= 0xE )\n {\n v20 = 0LL;\n v17 = 0;\n LODWORD(result) = 0;\n v6 = 0LL;\n }\n else\n {\n v4 = 0LL;\n v5 = (const __m128i *)a1;\n v6 = v3 & 0xFFFFFFFFFFFFFFF0LL;\n si128 = _mm_load_si128((const __m128i *)&xmmword_2090);\n v8 = _mm_load_si128((const __m128i *)&xmmword_20A0);\n do\n {\n v9 = _mm_loadu_si128(v5++);\n v10 = _mm_cmpeq_epi8(_mm_cmpeq_epi8(_mm_subs_epu8(v8, _mm_add_epi8(v9, si128)), (__m128i)0LL), (__m128i)0LL);\n v11 = _mm_cmpgt_epi8((__m128i)0LL, v10);\n v12 = _mm_unpacklo_epi8(v10, v11);\n v13 = _mm_unpackhi_epi8(v10, v11);\n v14 = _mm_cmpgt_epi16((__m128i)0LL, v12);\n v15 = _mm_sub_epi32(_mm_sub_epi32(v4, _mm_unpacklo_epi16(v12, v14)), _mm_unpackhi_epi16(v12, v14));\n v16 = _mm_cmpgt_epi16((__m128i)0LL, v13);\n v4 = _mm_sub_epi32(_mm_sub_epi32(v15, _mm_unpacklo_epi16(v13, v16)), _mm_unpackhi_epi16(v13, v16));\n }\n while ( &a1[v3 & 0xFFFFFFFFFFFFFFF0LL] != (const char *)v5 );\n v17 = v3 & 0xFFFFFFF0;\n v18 = _mm_add_epi32(_mm_srli_si128(v4, 8), v4);\n result = (unsigned int)_mm_cvtsi128_si32(_mm_add_epi32(v18, _mm_srli_si128(v18, 4)));\n v20 = v18;\n if ( v3 == v6 )\n return result;\n }\n v21 = v3 - v6;\n if ( v3 - v6 - 1 <= 6 )\n goto LABEL_8;\n v22 = _mm_add_epi8(_mm_loadl_epi64((const __m128i *)&a1[v6]), _mm_loadl_epi64((const __m128i *)&xmmword_2090));\n v23 = _mm_cmpeq_epi8(v22, _mm_min_epu8(_mm_loadl_epi64((const __m128i *)&qword_20B0), v22));\n v24 = _mm_unpacklo_epi8(v23, _mm_cmpgt_epi8((__m128i)0LL, v23));\n v25 = _mm_shuffle_epi32(v24, 78);\n v26 = _mm_cmpgt_epi16((__m128i)0LL, v25);\n v27 = _mm_unpacklo_epi16(v24, _mm_cmpgt_epi16((__m128i)0LL, v24));\n v28 = _mm_sub_epi32(\n _mm_sub_epi32(\n _mm_sub_epi32(_mm_sub_epi32(v20, v27), _mm_shuffle_epi32(v27, 78)),\n _mm_unpacklo_epi16(v25, v26)),\n _mm_shuffle_epi32(_mm_unpacklo_epi16(v25, v26), 78));\n result = (unsigned int)(_mm_cvtsi128_si32(v28) + _mm_cvtsi128_si32(_mm_shuffle_epi32(v28, 229)));\n v6 += v21 & 0xFFFFFFFFFFFFFFF8LL;\n v17 += v21 & 0xFFFFFFF8;\n if ( (v21 & 7) != 0 )\n {\nLABEL_8:\n v29 = (unsigned __int8)(a1[v6] - 48) < 0xAu;\n v30 = v17 + 1;\n result = v29 + (unsigned int)result;\n if ( v30 < v3 )\n {\n v29 = (unsigned __int8)(a1[v30] - 48) < 0xAu;\n v31 = v17 + 2;\n result = v29 + (unsigned int)result;\n if ( v31 < v3 )\n {\n v29 = (unsigned __int8)(a1[v31] - 48) < 0xAu;\n v32 = v17 + 3;\n result = v29 + (unsigned int)result;\n if ( v32 < v3 )\n {\n v29 = (unsigned __int8)(a1[v32] - 48) < 0xAu;\n v33 = v17 + 4;\n result = v29 + (unsigned int)result;\n if ( v33 < v3 )\n {\n v29 = (unsigned __int8)(a1[v33] - 48) < 0xAu;\n v34 = v17 + 5;\n result = v29 + (unsigned int)result;\n if ( v34 < v3 )\n {\n result = ((unsigned __int8)(a1[v34] - 48) < 0xAu) + (unsigned int)result;\n v35 = v17 + 6;\n if ( v35 < v3 )\n return ((unsigned __int8)(a1[v35] - 48) < 0xAu) + (unsigned int)result;\n }\n }\n }\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest rax, rax\njz loc_1470\nmov rdx, rax\nlea rax, [rax-1]\ncmp rax, 0Eh\njbe loc_1474\nmov rcx, rdx\npxor xmm1, xmm1\npxor xmm3, xmm3\nmov rax, rbx\nand rcx, 0FFFFFFFFFFFFFFF0h\nmovdqa xmm6, cs:xmmword_2090\nmovdqa xmm5, cs:xmmword_20A0\npxor xmm4, xmm4\nlea rsi, [rcx+rbx]\nnop dword ptr [rax+00000000h]\nloc_1268:\nmovdqu xmm2, xmmword ptr [rax]\nmovdqa xmm0, xmm5\nmovdqa xmm7, xmm3\nadd rax, 10h\npaddb xmm2, xmm6\npsubusb xmm0, xmm2\npcmpeqb xmm0, xmm3\npcmpeqb xmm0, xmm3\npcmpgtb xmm7, xmm0\nmovdqa xmm2, xmm0\npunpcklbw xmm2, xmm7\npunpckhbw xmm0, xmm7\nmovdqa xmm7, xmm4\npcmpgtw xmm7, xmm2\nmovdqa xmm8, xmm2\npunpcklwd xmm8, xmm7\npunpckhwd xmm2, xmm7\nmovdqa xmm7, xmm0\npsubd xmm1, xmm8\npsubd xmm1, xmm2\nmovdqa xmm2, xmm4\npcmpgtw xmm2, xmm0\npunpcklwd xmm7, xmm2\npunpckhwd xmm0, xmm2\npsubd xmm1, xmm7\npsubd xmm1, xmm0\ncmp rsi, rax\njnz short loc_1268\nmovdqa xmm0, xmm1\nmov esi, ecx\npsrldq xmm0, 8\npaddd xmm0, xmm1\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\npaddd xmm0, xmm2\nmovd eax, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm1, 8\npaddd xmm1, xmm0\ncmp rdx, rcx\njz loc_1466\nloc_130E:\nmov rdi, rdx\nsub rdi, rcx\nlea r8, [rdi-1]\ncmp r8, 6\njbe loc_13C5\nmovq xmm2, qword ptr cs:xmmword_2090\nmovq xmm0, qword ptr [rbx+rcx]\npaddb xmm0, xmm2\nmovq xmm2, cs:qword_20B0\npminub xmm2, xmm0\npcmpeqb xmm0, xmm2\npxor xmm2, xmm2\npcmpgtb xmm2, xmm0\nmovdqa xmm3, xmm0\npunpcklbw xmm3, xmm2\npunpcklbw xmm0, xmm2\npxor xmm2, xmm2\nmovdqa xmm4, xmm2\nmovdqa xmm5, xmm3\npshufd xmm0, xmm0, 4Eh ; 'N'\npcmpgtw xmm4, xmm3\npcmpgtw xmm2, xmm0\npunpcklwd xmm5, xmm4\npunpcklwd xmm3, xmm4\npsubd xmm1, xmm5\npshufd xmm3, xmm3, 4Eh ; 'N'\npsubd xmm1, xmm3\nmovdqa xmm3, xmm0\npunpcklwd xmm0, xmm2\npunpcklwd xmm3, xmm2\npshufd xmm0, xmm0, 4Eh ; 'N'\npsubd xmm1, xmm3\npsubd xmm1, xmm0\nmovd r8d, xmm1\npshufd xmm6, xmm1, 0E5h\nmovd eax, xmm6\nadd eax, r8d\nmov r8, rdi\nand r8, 0FFFFFFFFFFFFFFF8h\nadd rcx, r8\nadd esi, r8d\nand edi, 7\njz loc_1466\nloc_13C5:\nmovzx ecx, byte ptr [rbx+rcx]\nsub ecx, 30h ; '0'\ncmp cl, 0Ah\nlea ecx, [rsi+1]\nmovsxd rcx, ecx\nadc eax, 0\ncmp rcx, rdx\njnb loc_1466\nmovzx ecx, byte ptr [rbx+rcx]\nsub ecx, 30h ; '0'\ncmp cl, 0Ah\nlea ecx, [rsi+2]\nmovsxd rcx, ecx\nadc eax, 0\ncmp rcx, rdx\njnb short loc_1466\nmovzx ecx, byte ptr [rbx+rcx]\nsub ecx, 30h ; '0'\ncmp cl, 0Ah\nlea ecx, [rsi+3]\nmovsxd rcx, ecx\nadc eax, 0\ncmp rcx, rdx\njnb short loc_1466\nmovzx ecx, byte ptr [rbx+rcx]\nsub ecx, 30h ; '0'\ncmp cl, 0Ah\nlea ecx, [rsi+4]\nmovsxd rcx, ecx\nadc eax, 0\ncmp rcx, rdx\njnb short loc_1466\nmovzx ecx, byte ptr [rbx+rcx]\nsub ecx, 30h ; '0'\ncmp cl, 0Ah\nlea ecx, [rsi+5]\nmovsxd rcx, ecx\nadc eax, 0\ncmp rcx, rdx\njnb short loc_1466\nmovzx ecx, byte ptr [rbx+rcx]\nsub ecx, 30h ; '0'\ncmp cl, 0Ah\nadc eax, 0\nadd esi, 6\nmovsxd rsi, esi\ncmp rsi, rdx\njnb short loc_1466\nmovzx edx, byte ptr [rbx+rsi]\nsub edx, 30h ; '0'\ncmp dl, 0Ah\nadc eax, 0\nloc_1466:\npop rbx\nretn\nloc_1470:\nxor eax, eax\npop rbx\nretn\nloc_1474:\npxor xmm1, xmm1\nxor esi, esi\nxor eax, eax\nxor ecx, ecx\njmp loc_130E", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(const char *a1)\n{\n size_t v2; // rax\n size_t v3; // rdx\n __m128i v4; // xmm1\n const __m128i *v5; // rax\n unsigned __int64 v6; // rcx\n __m128i si128; // xmm6\n __m128i v8; // xmm5\n __m128i v9; // xmm2\n __m128i v10; // xmm0\n __m128i v11; // xmm7\n __m128i v12; // xmm2\n __m128i v13; // xmm0\n __m128i v14; // xmm7\n __m128i v15; // xmm1\n __m128i v16; // xmm2\n int v17; // esi\n __m128i v18; // xmm0\n __int64 result; // rax\n __m128i v20; // xmm1\n size_t v21; // rdi\n __m128i v22; // xmm0\n __m128i v23; // xmm0\n __m128i v24; // xmm3\n __m128i v25; // xmm0\n __m128i v26; // xmm2\n __m128i v27; // xmm3\n __m128i v28; // xmm1\n bool v29; // cf\n size_t v30; // rcx\n size_t v31; // rcx\n size_t v32; // rcx\n size_t v33; // rcx\n size_t v34; // rcx\n size_t v35; // rsi\n\n v2 = strlen(a1);\n if ( !v2 )\n return 0LL;\n v3 = v2;\n if ( v2 - 1 <= 0xE )\n {\n v20 = 0LL;\n v17 = 0;\n LODWORD(result) = 0;\n v6 = 0LL;\n }\n else\n {\n v4 = 0LL;\n v5 = (const __m128i *)a1;\n v6 = v3 & 0xFFFFFFFFFFFFFFF0LL;\n si128 = _mm_load_si128((const __m128i *)&xmmword_2090);\n v8 = _mm_load_si128((const __m128i *)&xmmword_20A0);\n do\n {\n v9 = _mm_loadu_si128(v5++);\n v10 = _mm_cmpeq_epi8(_mm_cmpeq_epi8(_mm_subs_epu8(v8, _mm_add_epi8(v9, si128)), (__m128i)0LL), (__m128i)0LL);\n v11 = _mm_cmpgt_epi8((__m128i)0LL, v10);\n v12 = _mm_unpacklo_epi8(v10, v11);\n v13 = _mm_unpackhi_epi8(v10, v11);\n v14 = _mm_cmpgt_epi16((__m128i)0LL, v12);\n v15 = _mm_sub_epi32(_mm_sub_epi32(v4, _mm_unpacklo_epi16(v12, v14)), _mm_unpackhi_epi16(v12, v14));\n v16 = _mm_cmpgt_epi16((__m128i)0LL, v13);\n v4 = _mm_sub_epi32(_mm_sub_epi32(v15, _mm_unpacklo_epi16(v13, v16)), _mm_unpackhi_epi16(v13, v16));\n }\n while ( &a1[v3 & 0xFFFFFFFFFFFFFFF0LL] != (const char *)v5 );\n v17 = v3 & 0xFFFFFFF0;\n v18 = _mm_add_epi32(_mm_srli_si128(v4, 8), v4);\n result = (unsigned int)_mm_cvtsi128_si32(_mm_add_epi32(v18, _mm_srli_si128(v18, 4)));\n v20 = v18;\n if ( v3 == v6 )\n return result;\n }\n v21 = v3 - v6;\n if ( v3 - v6 - 1 <= 6 )\n goto LABEL_8;\n v22 = _mm_add_epi8(_mm_loadl_epi64((const __m128i *)&a1[v6]), _mm_loadl_epi64((const __m128i *)&xmmword_2090));\n v23 = _mm_cmpeq_epi8(v22, _mm_min_epu8(_mm_loadl_epi64((const __m128i *)&qword_20B0), v22));\n v24 = _mm_unpacklo_epi8(v23, _mm_cmpgt_epi8((__m128i)0LL, v23));\n v25 = _mm_shuffle_epi32(v24, 78);\n v26 = _mm_cmpgt_epi16((__m128i)0LL, v25);\n v27 = _mm_unpacklo_epi16(v24, _mm_cmpgt_epi16((__m128i)0LL, v24));\n v28 = _mm_sub_epi32(\n _mm_sub_epi32(\n _mm_sub_epi32(_mm_sub_epi32(v20, v27), _mm_shuffle_epi32(v27, 78)),\n _mm_unpacklo_epi16(v25, v26)),\n _mm_shuffle_epi32(_mm_unpacklo_epi16(v25, v26), 78));\n result = (unsigned int)(_mm_cvtsi128_si32(v28) + _mm_cvtsi128_si32(_mm_shuffle_epi32(v28, 229)));\n v6 += v21 & 0xFFFFFFFFFFFFFFF8LL;\n v17 += v21 & 0xFFFFFFF8;\n if ( (v21 & 7) != 0 )\n {\nLABEL_8:\n v29 = (unsigned __int8)(a1[v6] - 48) < 0xAu;\n v30 = v17 + 1;\n result = v29 + (unsigned int)result;\n if ( v30 < v3 )\n {\n v29 = (unsigned __int8)(a1[v30] - 48) < 0xAu;\n v31 = v17 + 2;\n result = v29 + (unsigned int)result;\n if ( v31 < v3 )\n {\n v29 = (unsigned __int8)(a1[v31] - 48) < 0xAu;\n v32 = v17 + 3;\n result = v29 + (unsigned int)result;\n if ( v32 < v3 )\n {\n v29 = (unsigned __int8)(a1[v32] - 48) < 0xAu;\n v33 = v17 + 4;\n result = v29 + (unsigned int)result;\n if ( v33 < v3 )\n {\n v29 = (unsigned __int8)(a1[v33] - 48) < 0xAu;\n v34 = v17 + 5;\n result = v29 + (unsigned int)result;\n if ( v34 < v3 )\n {\n result = ((unsigned __int8)(a1[v34] - 48) < 0xAu) + (unsigned int)result;\n v35 = v17 + 6;\n if ( v35 < v3 )\n return ((unsigned __int8)(a1[v35] - 48) < 0xAu) + (unsigned int)result;\n }\n }\n }\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(const char *a1) {\n unsigned int v2;\n unsigned int v3;\n __m128i v4;\n const __m128i *v5;\n unsigned long long v6;\n __m128i si128;\n __m128i v8;\n __m128i v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n __m128i v15;\n __m128i v16;\n int v17;\n __m128i v18;\n long long result;\n __m128i v20;\n unsigned int v21;\n __m128i v22;\n __m128i v23;\n __m128i v24;\n __m128i v25;\n __m128i v26;\n __m128i v27;\n __m128i v28;\n bool v29;\n unsigned int v30;\n unsigned int v31;\n unsigned int v32;\n unsigned int v33;\n unsigned int v34;\n unsigned int v35;\n v2 = strlen(a1);\n if (!v2) return 0LL;\n v3 = v2;\n if (v2 - 1 <= 14) {\n v20 = 0LL;\n v17 = 0;\n LODWORD(result) = 0;\n v6 = 0LL;\n } else {\n v4 = 0LL;\n v5 = (const __m128i *)a1;\n v6 = v3 & 18446744073709551600LL;\n si128 = _mm_load_si128((const __m128i *)&xmmword_2090);\n v8 = _mm_load_si128((const __m128i *)&xmmword_20A0);\n do {\n v9 = _mm_loadu_si128(v5++);\n v10 = _mm_cmpeq_epi8(\n _mm_cmpeq_epi8(_mm_subs_epu8(v8, _mm_add_epi8(v9, si128)),\n (__m128i)0LL),\n (__m128i)0LL);\n v11 = _mm_cmpgt_epi8((__m128i)0LL, v10);\n v12 = _mm_unpacklo_epi8(v10, v11);\n v13 = _mm_unpackhi_epi8(v10, v11);\n v14 = _mm_cmpgt_epi16((__m128i)0LL, v12);\n v15 = _mm_sub_epi32(_mm_sub_epi32(v4, _mm_unpacklo_epi16(v12, v14)),\n _mm_unpackhi_epi16(v12, v14));\n v16 = _mm_cmpgt_epi16((__m128i)0LL, v13);\n v4 = _mm_sub_epi32(_mm_sub_epi32(v15, _mm_unpacklo_epi16(v13, v16)),\n _mm_unpackhi_epi16(v13, v16));\n } while (&a1[v3 & 18446744073709551600LL] != (const char *)v5);\n v17 = v3 & 4294967280;\n v18 = _mm_add_epi32(_mm_srli_si128(v4, 8), v4);\n result = (unsigned int)_mm_cvtsi128_si32(\n _mm_add_epi32(v18, _mm_srli_si128(v18, 4)));\n v20 = v18;\n if (v3 == v6) return result;\n }\n v21 = v3 - v6;\n if (v3 - v6 - 1 <= 6) goto LABEL_8;\n v22 = _mm_add_epi8(_mm_loadl_epi64((const __m128i *)&a1[v6]),\n _mm_loadl_epi64((const __m128i *)&xmmword_2090));\n v23 = _mm_cmpeq_epi8(\n v22, _mm_min_epu8(_mm_loadl_epi64((const __m128i *)&qword_20B0), v22));\n v24 = _mm_unpacklo_epi8(v23, _mm_cmpgt_epi8((__m128i)0LL, v23));\n v25 = _mm_shuffle_epi32(v24, 78);\n v26 = _mm_cmpgt_epi16((__m128i)0LL, v25);\n v27 = _mm_unpacklo_epi16(v24, _mm_cmpgt_epi16((__m128i)0LL, v24));\n v28 = _mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(v20, v27),\n _mm_shuffle_epi32(v27, 78)),\n _mm_unpacklo_epi16(v25, v26)),\n _mm_shuffle_epi32(_mm_unpacklo_epi16(v25, v26), 78));\n result = (unsigned int)(_mm_cvtsi128_si32(v28) +\n _mm_cvtsi128_si32(_mm_shuffle_epi32(v28, 229)));\n v6 += v21 & 18446744073709551608LL;\n v17 += v21 & 4294967288;\n if ((v21 & 7) != 0) {\n LABEL_8:\n v29 = (unsigned char)(a1[v6] - 48) < 10u;\n v30 = v17 + 1;\n result = v29 + (unsigned int)result;\n if (v30 < v3) {\n v29 = (unsigned char)(a1[v30] - 48) < 10u;\n v31 = v17 + 2;\n result = v29 + (unsigned int)result;\n if (v31 < v3) {\n v29 = (unsigned char)(a1[v31] - 48) < 10u;\n v32 = v17 + 3;\n result = v29 + (unsigned int)result;\n if (v32 < v3) {\n v29 = (unsigned char)(a1[v32] - 48) < 10u;\n v33 = v17 + 4;\n result = v29 + (unsigned int)result;\n if (v33 < v3) {\n v29 = (unsigned char)(a1[v33] - 48) < 10u;\n v34 = v17 + 5;\n result = v29 + (unsigned int)result;\n if (v34 < v3) {\n result =\n ((unsigned char)(a1[v34] - 48) < 10u) + (unsigned int)result;\n v35 = v17 + 6;\n if (v35 < v3)\n return ((unsigned char)(a1[v35] - 48) < 10u) +\n (unsigned int)result;\n }\n }\n }\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n unsigned int v2;\n unsigned int v3;\n __m128i v4;\n const __m128i *v5;\n unsigned long long v6;\n __m128i si128;\n __m128i v8;\n __m128i v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n __m128i v15;\n __m128i v16;\n int v17;\n __m128i v18;\n long long result;\n __m128i v20;\n unsigned int v21;\n __m128i v22;\n __m128i v23;\n __m128i v24;\n __m128i v25;\n __m128i v26;\n __m128i v27;\n __m128i v28;\n bool v29;\n unsigned int v30;\n unsigned int v31;\n unsigned int v32;\n unsigned int v33;\n unsigned int v34;\n unsigned int v35;\n v2 = strlen(a1);\n if (!v2) return 0LL;\n v3 = v2;\n if (v2 - 1 <= 14) {\n v20 = 0LL;\n v17 = 0;\n LODWORD(result) = 0;\n v6 = 0LL;\n } else {\n v4 = 0LL;\n v5 = (const __m128i *)a1;\n v6 = v3 & 18446744073709551600LL;\n si128 = _mm_load_si128((const __m128i *)&xmmword_2090);\n v8 = _mm_load_si128((const __m128i *)&xmmword_20A0);\n do {\n v9 = _mm_loadu_si128(v5++);\n v10 = _mm_cmpeq_epi8(\n _mm_cmpeq_epi8(_mm_subs_epu8(v8, _mm_add_epi8(v9, si128)),\n (__m128i)0LL),\n (__m128i)0LL);\n v11 = _mm_cmpgt_epi8((__m128i)0LL, v10);\n v12 = _mm_unpacklo_epi8(v10, v11);\n v13 = _mm_unpackhi_epi8(v10, v11);\n v14 = _mm_cmpgt_epi16((__m128i)0LL, v12);\n v15 = _mm_sub_epi32(_mm_sub_epi32(v4, _mm_unpacklo_epi16(v12, v14)),\n _mm_unpackhi_epi16(v12, v14));\n v16 = _mm_cmpgt_epi16((__m128i)0LL, v13);\n v4 = _mm_sub_epi32(_mm_sub_epi32(v15, _mm_unpacklo_epi16(v13, v16)),\n _mm_unpackhi_epi16(v13, v16));\n } while (&a1[v3 & 18446744073709551600LL] != (const char *)v5);\n v17 = v3 & 4294967280;\n v18 = _mm_add_epi32(_mm_srli_si128(v4, 8), v4);\n result = (unsigned int)_mm_cvtsi128_si32(\n _mm_add_epi32(v18, _mm_srli_si128(v18, 4)));\n v20 = v18;\n if (v3 == v6) return result;\n }\n v21 = v3 - v6;\n if (v3 - v6 - 1 <= 6) goto LABEL_8;\n v22 = _mm_add_epi8(_mm_loadl_epi64((const __m128i *)&a1[v6]),\n _mm_loadl_epi64((const __m128i *)&xmmword_2090));\n v23 = _mm_cmpeq_epi8(\n v22, _mm_min_epu8(_mm_loadl_epi64((const __m128i *)&qword_20B0), v22));\n v24 = _mm_unpacklo_epi8(v23, _mm_cmpgt_epi8((__m128i)0LL, v23));\n v25 = _mm_shuffle_epi32(v24, 78);\n v26 = _mm_cmpgt_epi16((__m128i)0LL, v25);\n v27 = _mm_unpacklo_epi16(v24, _mm_cmpgt_epi16((__m128i)0LL, v24));\n v28 = _mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(v20, v27),\n _mm_shuffle_epi32(v27, 78)),\n _mm_unpacklo_epi16(v25, v26)),\n _mm_shuffle_epi32(_mm_unpacklo_epi16(v25, v26), 78));\n result = (unsigned int)(_mm_cvtsi128_si32(v28) +\n _mm_cvtsi128_si32(_mm_shuffle_epi32(v28, 229)));\n v6 += v21 & 18446744073709551608LL;\n v17 += v21 & 4294967288;\n if ((v21 & 7) != 0) {\n LABEL_8:\n v29 = (unsigned char)(a1[v6] - 48) < 10u;\n v30 = v17 + 1;\n result = v29 + (unsigned int)result;\n if (v30 < v3) {\n v29 = (unsigned char)(a1[v30] - 48) < 10u;\n v31 = v17 + 2;\n result = v29 + (unsigned int)result;\n if (v31 < v3) {\n v29 = (unsigned char)(a1[v31] - 48) < 10u;\n v32 = v17 + 3;\n result = v29 + (unsigned int)result;\n if (v32 < v3) {\n v29 = (unsigned char)(a1[v32] - 48) < 10u;\n v33 = v17 + 4;\n result = v29 + (unsigned int)result;\n if (v33 < v3) {\n v29 = (unsigned char)(a1[v33] - 48) < 10u;\n v34 = v17 + 5;\n result = v29 + (unsigned int)result;\n if (v34 < v3) {\n result =\n ((unsigned char)(a1[v34] - 48) < 10u) + (unsigned int)result;\n v35 = v17 + 6;\n if (v35 < v3)\n return ((unsigned char)(a1[v35] - 48) < 10u) +\n (unsigned int)result;\n }\n }\n }\n }\n }\n }\n return result;\n}" + }, + { + "index": 765, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n n = n + 1;\n return n + (int)(log2(n + log2(n)));\n}", + "test": "int main() {\n\n assert(func0(7) == 11);\n\n assert(func0(4) == 7);\n\n assert(func0(9) == 13);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %edi,-0x4(%rbp)\naddl $0x1,-0x4(%rbp)\ncvtsi2sdl -0x4(%rbp),%xmm1\nmovsd %xmm1,-0x10(%rbp)\ncvtsi2sdl -0x4(%rbp),%xmm0\ncallq 1060 \naddsd -0x10(%rbp),%xmm0\ncallq 1060 \ncvttsd2si %xmm0,%edx\nmov -0x4(%rbp),%eax\nadd %edx,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+var_4], edi\nadd [rbp+var_4], 1\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_4]\nmovsd [rbp+var_10], xmm1\npxor xmm2, xmm2\ncvtsi2sd xmm2, [rbp+var_4]\nmovq rax, xmm2\nmovq xmm0, rax; x\ncall _log2\naddsd xmm0, [rbp+var_10]\nmovq rax, xmm0\nmovq xmm0, rax; x\ncall _log2\ncvttsd2si edx, xmm0\nmov eax, [rbp+var_4]\nadd eax, edx\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n double v1; // xmm0_8\n\n v1 = log2((double)(a1 + 1));\n return (unsigned int)((int)log2(v1 + (double)(a1 + 1)) + a1 + 1);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+var_4], edi\nadd [rbp+var_4], 1\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_4]\nmovsd [rbp+var_10], xmm1\npxor xmm2, xmm2\ncvtsi2sd xmm2, [rbp+var_4]\nmovq rax, xmm2\nmovq xmm0, rax; x\ncall _log2\naddsd xmm0, [rbp+var_10]\nmovq rax, xmm0\nmovq xmm0, rax; x\ncall _log2\ncvttsd2si edx, xmm0\nmov eax, [rbp+var_4]\nadd eax, edx\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n double v1; // xmm0_8\n\n v1 = log2((double)(a1 + 1));\n return (unsigned int)((int)log2(v1 + (double)(a1 + 1)) + a1 + 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n double v1;\n v1 = log2((double)(a1 + 1));\n return (unsigned int)((int)log2(v1 + (double)(a1 + 1)) + a1 + 1);\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n double v1;\n v1 = log2((double)(a1 + 1));\n return (unsigned int)((int)log2(v1 + (double)(a1 + 1)) + a1 + 1);\n}" + }, + { + "index": 765, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n n = n + 1;\n return n + (int)(log2(n + log2(n)));\n}", + "test": "int main() {\n\n assert(func0(7) == 11);\n\n assert(func0(4) == 7);\n\n assert(func0(9) == 13);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nsub $0x10,%rsp\nlea 0x1(%rdi),%ebx\npxor %xmm1,%xmm1\ncvtsi2sd %ebx,%xmm1\nmovsd %xmm1,0x8(%rsp)\nmovapd %xmm1,%xmm0\ncallq 1060 \naddsd 0x8(%rsp),%xmm0\ncallq 1060 \ncvttsd2si %xmm0,%eax\nadd %ebx,%eax\nadd $0x10,%rsp\npop %rbx\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbx\nsub rsp, 10h\nlea ebx, [rdi+1]\npxor xmm1, xmm1\ncvtsi2sd xmm1, ebx\nmovsd [rsp+18h+var_10], xmm1\nmovapd xmm0, xmm1; x\ncall _log2\naddsd xmm0, [rsp+18h+var_10]; x\ncall _log2\ncvttsd2si eax, xmm0\nadd eax, ebx\nadd rsp, 10h\npop rbx\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n double v1; // xmm0_8\n\n v1 = log2((double)(a1 + 1));\n return (unsigned int)(a1 + 1 + (int)log2(v1 + (double)(a1 + 1)));\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbx\nsub rsp, 10h\nlea ebx, [rdi+1]\npxor xmm1, xmm1\ncvtsi2sd xmm1, ebx\nmovsd [rsp+18h+var_10], xmm1\nmovapd xmm0, xmm1; x\ncall _log2\naddsd xmm0, [rsp+18h+var_10]; x\ncall _log2\ncvttsd2si eax, xmm0\nadd eax, ebx\nadd rsp, 10h\npop rbx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n double v1; // xmm0_8\n\n v1 = log2((double)(a1 + 1));\n return (unsigned int)(a1 + 1 + (int)log2(v1 + (double)(a1 + 1)));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n double v1;\n v1 = log2((double)(a1 + 1));\n return (unsigned int)(a1 + 1 + (int)log2(v1 + (double)(a1 + 1)));\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n double v1;\n v1 = log2((double)(a1 + 1));\n return (unsigned int)(a1 + 1 + (int)log2(v1 + (double)(a1 + 1)));\n}" + }, + { + "index": 765, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n n = n + 1;\n return n + (int)(log2(n + log2(n)));\n}", + "test": "int main() {\n\n assert(func0(7) == 11);\n\n assert(func0(4) == 7);\n\n assert(func0(9) == 13);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\npxor %xmm1,%xmm1\nlea 0x1(%rdi),%ebx\ncvtsi2sd %ebx,%xmm1\nsub $0x10,%rsp\nmovapd %xmm1,%xmm0\nmovsd %xmm1,0x8(%rsp)\ncallq 1060 \nmovsd 0x8(%rsp),%xmm1\naddsd %xmm1,%xmm0\ncallq 1060 \nadd $0x10,%rsp\ncvttsd2si %xmm0,%eax\nadd %ebx,%eax\npop %rbx\nretq\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbx\npxor xmm1, xmm1\nlea ebx, [rdi+1]\ncvtsi2sd xmm1, ebx\nsub rsp, 10h\nmovapd xmm0, xmm1; x\nmovsd [rsp+18h+var_10], xmm1\ncall _log2\nmovsd xmm1, [rsp+18h+var_10]\naddsd xmm0, xmm1; x\ncall _log2\nadd rsp, 10h\ncvttsd2si eax, xmm0\nadd eax, ebx\npop rbx\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n double v1; // xmm0_8\n\n v1 = log2((double)(a1 + 1));\n return (unsigned int)(a1 + 1 + (int)log2(v1 + (double)(a1 + 1)));\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbx\npxor xmm1, xmm1\nlea ebx, [rdi+1]\ncvtsi2sd xmm1, ebx\nsub rsp, 10h\nmovapd xmm0, xmm1; x\nmovsd [rsp+18h+var_10], xmm1\ncall _log2\nmovsd xmm1, [rsp+18h+var_10]\naddsd xmm0, xmm1; x\ncall _log2\nadd rsp, 10h\ncvttsd2si eax, xmm0\nadd eax, ebx\npop rbx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(int a1)\n{\n double v1; // xmm0_8\n\n v1 = log2((double)(a1 + 1));\n return (unsigned int)(a1 + 1 + (int)log2(v1 + (double)(a1 + 1)));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(int a1) {\n double v1;\n v1 = log2((double)(a1 + 1));\n return (unsigned int)(a1 + 1 + (int)log2(v1 + (double)(a1 + 1)));\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n double v1;\n v1 = log2((double)(a1 + 1));\n return (unsigned int)(a1 + 1 + (int)log2(v1 + (double)(a1 + 1)));\n}" + }, + { + "index": 765, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n n = n + 1;\n return n + (int)(log2(n + log2(n)));\n}", + "test": "int main() {\n\n assert(func0(7) == 11);\n\n assert(func0(4) == 7);\n\n assert(func0(9) == 13);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\npxor %xmm1,%xmm1\nlea 0x1(%rdi),%ebx\ncvtsi2sd %ebx,%xmm1\nsub $0x10,%rsp\nmovapd %xmm1,%xmm0\nmovsd %xmm1,0x8(%rsp)\ncallq 1060 \nmovsd 0x8(%rsp),%xmm1\naddsd %xmm1,%xmm0\ncallq 1060 \nadd $0x10,%rsp\ncvttsd2si %xmm0,%eax\nadd %ebx,%eax\npop %rbx\nretq\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbx\npxor xmm1, xmm1\nlea ebx, [rdi+1]\ncvtsi2sd xmm1, ebx\nsub rsp, 10h\nmovapd xmm0, xmm1; x\nmovsd [rsp+18h+var_10], xmm1\ncall _log2\nmovsd xmm1, [rsp+18h+var_10]\naddsd xmm0, xmm1; x\ncall _log2\nadd rsp, 10h\ncvttsd2si eax, xmm0\nadd eax, ebx\npop rbx\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n double v1; // xmm0_8\n\n v1 = log2((double)(a1 + 1));\n return (unsigned int)(a1 + 1 + (int)log2(v1 + (double)(a1 + 1)));\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbx\npxor xmm1, xmm1\nlea ebx, [rdi+1]\ncvtsi2sd xmm1, ebx\nsub rsp, 10h\nmovapd xmm0, xmm1; x\nmovsd [rsp+18h+var_10], xmm1\ncall _log2\nmovsd xmm1, [rsp+18h+var_10]\naddsd xmm0, xmm1; x\ncall _log2\nadd rsp, 10h\ncvttsd2si eax, xmm0\nadd eax, ebx\npop rbx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(int a1)\n{\n double v1; // xmm0_8\n\n v1 = log2((double)(a1 + 1));\n return (unsigned int)(a1 + 1 + (int)log2(v1 + (double)(a1 + 1)));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(int a1) {\n double v1;\n v1 = log2((double)(a1 + 1));\n return (unsigned int)(a1 + 1 + (int)log2(v1 + (double)(a1 + 1)));\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n double v1;\n v1 = log2((double)(a1 + 1));\n return (unsigned int)(a1 + 1 + (int)log2(v1 + (double)(a1 + 1)));\n}" + }, + { + "index": 766, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n} Pair;\n\n\n\n", + "func": "Pair* func0(int* arr, int size, int* out_size) {\n *out_size = size - 1;\n Pair* pairs = (Pair*)malloc(sizeof(Pair) * (*out_size));\n for (int i = 0; i < *out_size; i++) {\n pairs[i].first = arr[i];\n pairs[i].second = arr[i + 1];\n }\n return pairs;\n}", + "test": "int main() {\n\n int out_size;\n\n\n\n int arr1[] = {1, 1, 2, 3, 3, 4, 4, 5};\n\n Pair* result1 = func0(arr1, sizeof(arr1) / sizeof(arr1[0]), &out_size);\n\n Pair expected1[] = {{1, 1}, {1, 2}, {2, 3}, {3, 3}, {3, 4}, {4, 4}, {4, 5}};\n\n for (int i = 0; i < out_size; i++) {\n\n assert(result1[i].first == expected1[i].first && result1[i].second == expected1[i].second);\n\n }\n\n free(result1);\n\n\n\n int arr2[] = {1, 5, 7, 9, 10};\n\n Pair* result2 = func0(arr2, sizeof(arr2) / sizeof(arr2[0]), &out_size);\n\n Pair expected2[] = {{1, 5}, {5, 7}, {7, 9}, {9, 10}};\n\n for (int i = 0; i < out_size; i++) {\n\n assert(result2[i].first == expected2[i].first && result2[i].second == expected2[i].second);\n\n }\n\n free(result2);\n\n\n\n int arr3[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n Pair* result3 = func0(arr3, sizeof(arr3) / sizeof(arr3[0]), &out_size);\n\n Pair expected3[] = {{1, 2}, {2, 3}, {3, 4}, {4, 5}, {5, 6}, {6, 7}, {7, 8}, {8, 9}, {9, 10}};\n\n for (int i = 0; i < out_size; i++) {\n\n assert(result3[i].first == expected3[i].first && result3[i].second == expected3[i].second);\n\n }\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmov -0x1c(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x28(%rbp),%rax\nmov %edx,(%rax)\nmov -0x28(%rbp),%rax\nmov (%rax),%eax\ncltq\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 1250 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0xc(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\nmov -0xc(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0xc(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,0x4(%rdx)\naddl $0x1,-0xc(%rbp)\nmov -0x28(%rbp),%rax\nmov (%rax),%eax\ncmp %eax,-0xc(%rbp)\njl 11ed \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov eax, [rbp+var_1C]\nlea edx, [rax-1]\nmov rax, [rbp+var_28]\nmov [rax], edx\nmov rax, [rbp+var_28]\nmov eax, [rax]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp short loc_1250\nloc_11ED:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_C]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx+4], eax\nadd [rbp+var_C], 1\nloc_1250:\nmov rax, [rbp+var_28]\nmov eax, [rax]\ncmp [rbp+var_C], eax\njl short loc_11ED\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, int *a3)\n{\n int i; // [rsp+24h] [rbp-Ch]\n _DWORD *v6; // [rsp+28h] [rbp-8h]\n\n *a3 = a2 - 1;\n v6 = malloc(8LL * *a3);\n for ( i = 0; i < *a3; ++i )\n {\n v6[2 * i] = *(_DWORD *)(4LL * i + a1);\n v6[2 * i + 1] = *(_DWORD *)(4 * (i + 1LL) + a1);\n }\n return v6;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov eax, [rbp+var_1C]\nlea edx, [rax-1]\nmov rax, [rbp+var_28]\nmov [rax], edx\nmov rax, [rbp+var_28]\nmov eax, [rax]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp short loc_1250\nloc_11ED:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_C]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx+4], eax\nadd [rbp+var_C], 1\nloc_1250:\nmov rax, [rbp+var_28]\nmov eax, [rax]\ncmp [rbp+var_C], eax\njl short loc_11ED\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(__int64 a1, int a2, int *a3)\n{\n int i; // [rsp+24h] [rbp-Ch]\n _DWORD *v6; // [rsp+28h] [rbp-8h]\n\n *a3 = a2 - 1;\n v6 = malloc(8LL * *a3);\n for ( i = 0; i < *a3; ++i )\n {\n v6[2 * i] = *(_DWORD *)(4LL * i + a1);\n v6[2 * i + 1] = *(_DWORD *)(4 * (i + 1LL) + a1);\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(long long a1, int a2, int *a3) {\n int i;\n uint32_t *v6;\n *a3 = a2 - 1;\n v6 = malloc(8LL * *a3);\n for (i = 0; i < *a3; ++i) {\n v6[2 * i] = *(uint32_t *)(4LL * i + a1);\n v6[2 * i + 1] = *(uint32_t *)(4 * (i + 1LL) + a1);\n }\n return v6;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, int *a3) {\n int i;\n uint32_t *v6;\n *a3 = a2 - 1;\n v6 = malloc(8LL * *a3);\n for (i = 0; i < *a3; ++i) {\n v6[2 * i] = *(uint32_t *)(4LL * i + a1);\n v6[2 * i + 1] = *(uint32_t *)(4 * (i + 1LL) + a1);\n }\n return v6;\n}" + }, + { + "index": 766, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n} Pair;\n\n\n\n", + "func": "Pair* func0(int* arr, int size, int* out_size) {\n *out_size = size - 1;\n Pair* pairs = (Pair*)malloc(sizeof(Pair) * (*out_size));\n for (int i = 0; i < *out_size; i++) {\n pairs[i].first = arr[i];\n pairs[i].second = arr[i + 1];\n }\n return pairs;\n}", + "test": "int main() {\n\n int out_size;\n\n\n\n int arr1[] = {1, 1, 2, 3, 3, 4, 4, 5};\n\n Pair* result1 = func0(arr1, sizeof(arr1) / sizeof(arr1[0]), &out_size);\n\n Pair expected1[] = {{1, 1}, {1, 2}, {2, 3}, {3, 3}, {3, 4}, {4, 4}, {4, 5}};\n\n for (int i = 0; i < out_size; i++) {\n\n assert(result1[i].first == expected1[i].first && result1[i].second == expected1[i].second);\n\n }\n\n free(result1);\n\n\n\n int arr2[] = {1, 5, 7, 9, 10};\n\n Pair* result2 = func0(arr2, sizeof(arr2) / sizeof(arr2[0]), &out_size);\n\n Pair expected2[] = {{1, 5}, {5, 7}, {7, 9}, {9, 10}};\n\n for (int i = 0; i < out_size; i++) {\n\n assert(result2[i].first == expected2[i].first && result2[i].second == expected2[i].second);\n\n }\n\n free(result2);\n\n\n\n int arr3[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n Pair* result3 = func0(arr3, sizeof(arr3) / sizeof(arr3[0]), &out_size);\n\n Pair expected3[] = {{1, 2}, {2, 3}, {3, 4}, {4, 5}, {5, 6}, {6, 7}, {7, 8}, {8, 9}, {9, 10}};\n\n for (int i = 0; i < out_size; i++) {\n\n assert(result3[i].first == expected3[i].first && result3[i].second == expected3[i].second);\n\n }\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbx\nmov %rdx,%rbp\nsub $0x1,%esi\nmov %esi,(%rdx)\nmovslq %esi,%rsi\nlea 0x0(,%rsi,8),%rdi\ncallq 10b0 \nmov 0x0(%rbp),%edx\ntest %edx,%edx\njle 11f7 \nlea -0x1(%rdx),%esi\nmov $0x0,%edx\nmov (%rbx,%rdx,4),%ecx\nmov %ecx,(%rax,%rdx,8)\nmov 0x4(%rbx,%rdx,4),%ecx\nmov %ecx,0x4(%rax,%rdx,8)\nmov %rdx,%rcx\nadd $0x1,%rdx\ncmp %rsi,%rcx\njne 11dd \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov rbp, rdx\nsub esi, 1\nmov [rdx], esi\nmovsxd rsi, esi\nlea rdi, ds:0[rsi*8]; size\ncall _malloc\nmov esi, [rbp+0]\ntest esi, esi\njle short loc_11F8\nmovsxd rsi, esi\nshl rsi, 2\nmov edx, 0\nloc_11E1:\nmov ecx, [rbx+rdx]\nmov [rax+rdx*2], ecx\nmov ecx, [rbx+rdx+4]\nmov [rax+rdx*2+4], ecx\nadd rdx, 4\ncmp rdx, rsi\njnz short loc_11E1\nloc_11F8:\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2, int *a3)\n{\n int v4; // esi\n char *result; // rax\n __int64 v6; // rsi\n __int64 v7; // rdx\n\n v4 = a2 - 1;\n *a3 = v4;\n result = (char *)malloc(8LL * v4);\n if ( *a3 > 0 )\n {\n v6 = 4LL * *a3;\n v7 = 0LL;\n do\n {\n *(_DWORD *)&result[2 * v7] = *(_DWORD *)(a1 + v7);\n *(_DWORD *)&result[2 * v7 + 4] = *(_DWORD *)(a1 + v7 + 4);\n v7 += 4LL;\n }\n while ( v7 != v6 );\n }\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov rbp, rdx\nsub esi, 1\nmov [rdx], esi\nmovsxd rsi, esi\nlea rdi, ds:0[rsi*8]; size\ncall _malloc\nmov esi, [rbp+0]\ntest esi, esi\njle short loc_11F8\nmovsxd rsi, esi\nshl rsi, 2\nmov edx, 0\nloc_11E1:\nmov ecx, [rbx+rdx]\nmov [rax+rdx*2], ecx\nmov ecx, [rbx+rdx+4]\nmov [rax+rdx*2+4], ecx\nadd rdx, 4\ncmp rdx, rsi\njnz short loc_11E1\nloc_11F8:\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11A9(__int64 a1, int a2, int *a3)\n{\n int v4; // esi\n char *result; // rax\n __int64 v6; // rsi\n __int64 v7; // rdx\n\n v4 = a2 - 1;\n *a3 = v4;\n result = (char *)malloc(8LL * v4);\n if ( *a3 > 0 )\n {\n v6 = 4LL * *a3;\n v7 = 0LL;\n do\n {\n *(_DWORD *)&result[2 * v7] = *(_DWORD *)(a1 + v7);\n *(_DWORD *)&result[2 * v7 + 4] = *(_DWORD *)(a1 + v7 + 4);\n v7 += 4LL;\n }\n while ( v7 != v6 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11A9(long long a1, int a2, int *a3) {\n int v4;\n char *result;\n long long v6;\n long long v7;\n v4 = a2 - 1;\n *a3 = v4;\n result = (char *)malloc(8LL * v4);\n if (*a3 > 0) {\n v6 = 4LL * *a3;\n v7 = 0LL;\n do {\n *(uint32_t *)&result[2 * v7] = *(uint32_t *)(a1 + v7);\n *(uint32_t *)&result[2 * v7 + 4] = *(uint32_t *)(a1 + v7 + 4);\n v7 += 4LL;\n } while (v7 != v6);\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2, int *a3) {\n int v4;\n char *result;\n long long v6;\n long long v7;\n v4 = a2 - 1;\n *a3 = v4;\n result = (char *)malloc(8LL * v4);\n if (*a3 > 0) {\n v6 = 4LL * *a3;\n v7 = 0LL;\n do {\n *(uint32_t *)&result[2 * v7] = *(uint32_t *)(a1 + v7);\n *(uint32_t *)&result[2 * v7 + 4] = *(uint32_t *)(a1 + v7 + 4);\n v7 += 4LL;\n } while (v7 != v6);\n }\n return result;\n}" + }, + { + "index": 766, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n} Pair;\n\n\n\n", + "func": "Pair* func0(int* arr, int size, int* out_size) {\n *out_size = size - 1;\n Pair* pairs = (Pair*)malloc(sizeof(Pair) * (*out_size));\n for (int i = 0; i < *out_size; i++) {\n pairs[i].first = arr[i];\n pairs[i].second = arr[i + 1];\n }\n return pairs;\n}", + "test": "int main() {\n\n int out_size;\n\n\n\n int arr1[] = {1, 1, 2, 3, 3, 4, 4, 5};\n\n Pair* result1 = func0(arr1, sizeof(arr1) / sizeof(arr1[0]), &out_size);\n\n Pair expected1[] = {{1, 1}, {1, 2}, {2, 3}, {3, 3}, {3, 4}, {4, 4}, {4, 5}};\n\n for (int i = 0; i < out_size; i++) {\n\n assert(result1[i].first == expected1[i].first && result1[i].second == expected1[i].second);\n\n }\n\n free(result1);\n\n\n\n int arr2[] = {1, 5, 7, 9, 10};\n\n Pair* result2 = func0(arr2, sizeof(arr2) / sizeof(arr2[0]), &out_size);\n\n Pair expected2[] = {{1, 5}, {5, 7}, {7, 9}, {9, 10}};\n\n for (int i = 0; i < out_size; i++) {\n\n assert(result2[i].first == expected2[i].first && result2[i].second == expected2[i].second);\n\n }\n\n free(result2);\n\n\n\n int arr3[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n Pair* result3 = func0(arr3, sizeof(arr3) / sizeof(arr3[0]), &out_size);\n\n Pair expected3[] = {{1, 2}, {2, 3}, {3, 4}, {4, 5}, {5, 6}, {6, 7}, {7, 8}, {8, 9}, {9, 10}};\n\n for (int i = 0; i < out_size; i++) {\n\n assert(result3[i].first == expected3[i].first && result3[i].second == expected3[i].second);\n\n }\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nsub $0x1,%esi\nmov %rdx,%rbp\npush %rbx\nmov %rdi,%rbx\nsub $0x8,%rsp\nmov %esi,(%rdx)\nmovslq %esi,%rsi\nlea 0x0(,%rsi,8),%rdi\ncallq 10b0 \nmov 0x0(%rbp),%edx\ntest %edx,%edx\njle 1562 \nlea -0x1(%rdx),%esi\nxor %edx,%edx\nnopl 0x0(%rax)\nmov (%rbx,%rdx,4),%ecx\nmov %ecx,(%rax,%rdx,8)\nmov 0x4(%rbx,%rdx,4),%ecx\nmov %ecx,0x4(%rax,%rdx,8)\nmov %rdx,%rcx\nadd $0x1,%rdx\ncmp %rcx,%rsi\njne 1548 \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nsub esi, 1\nmov rbp, rdx\npush rbx\nmov rbx, rdi\nsub rsp, 8\nmov [rdx], esi\nmovsxd rsi, esi\nlea rdi, ds:0[rsi*8]; size\ncall _malloc\nmovsxd rcx, dword ptr [rbp+0]\ntest ecx, ecx\njle short loc_14BC\nmovd xmm1, dword ptr [rbx]\nshl rcx, 2\nxor edx, edx\nnop word ptr [rax+rax+00000000h]\nloc_14A0:\nmovdqa xmm0, xmm1\nmovd xmm1, dword ptr [rbx+rdx+4]\npunpckldq xmm0, xmm1\nmovq qword ptr [rax+rdx*2], xmm0\nadd rdx, 4\ncmp rdx, rcx\njnz short loc_14A0\nloc_14BC:\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_pseudo": "char *__fastcall func0(unsigned int *a1, int a2, int *a3)\n{\n int v3; // esi\n char *result; // rax\n __int64 v6; // rcx\n __m128i v7; // xmm1\n __int64 v8; // rcx\n unsigned __int64 v9; // rdx\n __m128i v10; // xmm0\n\n v3 = a2 - 1;\n *a3 = v3;\n result = (char *)malloc(8LL * v3);\n v6 = *a3;\n if ( (int)v6 > 0 )\n {\n v7 = _mm_cvtsi32_si128(*a1);\n v8 = 4 * v6;\n v9 = 0LL;\n do\n {\n v10 = v7;\n v7 = _mm_cvtsi32_si128(a1[v9 / 4 + 1]);\n *(_QWORD *)&result[2 * v9] = _mm_unpacklo_epi32(v10, v7).m128i_u64[0];\n v9 += 4LL;\n }\n while ( v9 != v8 );\n }\n return result;\n}", + "ida_strip_asm": "sub_1460:\nendbr64\npush rbp\nsub esi, 1\nmov rbp, rdx\npush rbx\nmov rbx, rdi\nsub rsp, 8\nmov [rdx], esi\nmovsxd rsi, esi\nlea rdi, ds:0[rsi*8]; size\ncall _malloc\nmovsxd rcx, dword ptr [rbp+0]\ntest ecx, ecx\njle short loc_14BC\nmovd xmm1, dword ptr [rbx]\nshl rcx, 2\nxor edx, edx\nnop word ptr [rax+rax+00000000h]\nloc_14A0:\nmovdqa xmm0, xmm1\nmovd xmm1, dword ptr [rbx+rdx+4]\npunpckldq xmm0, xmm1\nmovq qword ptr [rax+rdx*2], xmm0\nadd rdx, 4\ncmp rdx, rcx\njnz short loc_14A0\nloc_14BC:\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1460(unsigned int *a1, int a2, int *a3)\n{\n int v3; // esi\n char *result; // rax\n __int64 v6; // rcx\n __m128i v7; // xmm1\n __int64 v8; // rcx\n unsigned __int64 v9; // rdx\n __m128i v10; // xmm0\n\n v3 = a2 - 1;\n *a3 = v3;\n result = (char *)malloc(8LL * v3);\n v6 = *a3;\n if ( (int)v6 > 0 )\n {\n v7 = _mm_cvtsi32_si128(*a1);\n v8 = 4 * v6;\n v9 = 0LL;\n do\n {\n v10 = v7;\n v7 = _mm_cvtsi32_si128(a1[v9 / 4 + 1]);\n *(_QWORD *)&result[2 * v9] = _mm_unpacklo_epi32(v10, v7).m128i_u64[0];\n v9 += 4LL;\n }\n while ( v9 != v8 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1460(unsigned int *a1, int a2, int *a3) {\n int v3;\n char *result;\n long long v6;\n __m128i v7;\n long long v8;\n unsigned long long v9;\n __m128i v10;\n v3 = a2 - 1;\n *a3 = v3;\n result = (char *)malloc(8LL * v3);\n v6 = *a3;\n if ((int)v6 > 0) {\n v7 = _mm_cvtsi32_si128(*a1);\n v8 = 4 * v6;\n v9 = 0LL;\n do {\n v10 = v7;\n v7 = _mm_cvtsi32_si128(a1[v9 / 4 + 1]);\n *(uint64_t *)&result[2 * v9] = _mm_unpacklo_epi32(v10, v7).m128i_u64[0];\n v9 += 4LL;\n } while (v9 != v8);\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(unsigned int *a1, int a2, int *a3) {\n int v3;\n char *result;\n long long v6;\n __m128i v7;\n long long v8;\n unsigned long long v9;\n __m128i v10;\n v3 = a2 - 1;\n *a3 = v3;\n result = (char *)malloc(8LL * v3);\n v6 = *a3;\n if ((int)v6 > 0) {\n v7 = _mm_cvtsi32_si128(*a1);\n v8 = 4 * v6;\n v9 = 0LL;\n do {\n v10 = v7;\n v7 = _mm_cvtsi32_si128(a1[v9 / 4 + 1]);\n *(uint64_t *)&result[2 * v9] = _mm_unpacklo_epi32(v10, v7).m128i_u64[0];\n v9 += 4LL;\n } while (v9 != v8);\n }\n return result;\n}" + }, + { + "index": 766, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n} Pair;\n\n\n\n", + "func": "Pair* func0(int* arr, int size, int* out_size) {\n *out_size = size - 1;\n Pair* pairs = (Pair*)malloc(sizeof(Pair) * (*out_size));\n for (int i = 0; i < *out_size; i++) {\n pairs[i].first = arr[i];\n pairs[i].second = arr[i + 1];\n }\n return pairs;\n}", + "test": "int main() {\n\n int out_size;\n\n\n\n int arr1[] = {1, 1, 2, 3, 3, 4, 4, 5};\n\n Pair* result1 = func0(arr1, sizeof(arr1) / sizeof(arr1[0]), &out_size);\n\n Pair expected1[] = {{1, 1}, {1, 2}, {2, 3}, {3, 3}, {3, 4}, {4, 4}, {4, 5}};\n\n for (int i = 0; i < out_size; i++) {\n\n assert(result1[i].first == expected1[i].first && result1[i].second == expected1[i].second);\n\n }\n\n free(result1);\n\n\n\n int arr2[] = {1, 5, 7, 9, 10};\n\n Pair* result2 = func0(arr2, sizeof(arr2) / sizeof(arr2[0]), &out_size);\n\n Pair expected2[] = {{1, 5}, {5, 7}, {7, 9}, {9, 10}};\n\n for (int i = 0; i < out_size; i++) {\n\n assert(result2[i].first == expected2[i].first && result2[i].second == expected2[i].second);\n\n }\n\n free(result2);\n\n\n\n int arr3[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n Pair* result3 = func0(arr3, sizeof(arr3) / sizeof(arr3[0]), &out_size);\n\n Pair expected3[] = {{1, 2}, {2, 3}, {3, 4}, {4, 5}, {5, 6}, {6, 7}, {7, 8}, {8, 9}, {9, 10}};\n\n for (int i = 0; i < out_size; i++) {\n\n assert(result3[i].first == expected3[i].first && result3[i].second == expected3[i].second);\n\n }\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nsub $0x1,%esi\nmov %rdx,%rbp\npush %rbx\nmov %rdi,%rbx\nsub $0x8,%rsp\nmov %esi,(%rdx)\nmovslq %esi,%rsi\nlea 0x0(,%rsi,8),%rdi\ncallq 10b0 \nmov 0x0(%rbp),%esi\ntest %esi,%esi\njle 174a \nlea -0x1(%rsi),%edx\ncmp $0x2,%edx\njbe 1751 \nmov %esi,%ecx\nxor %edx,%edx\nshr $0x2,%ecx\nshl $0x4,%rcx\nnopw 0x0(%rax,%rax,1)\nmovdqu (%rbx,%rdx,1),%xmm0\nmovdqu 0x4(%rbx,%rdx,1),%xmm2\nmovdqa %xmm0,%xmm1\npunpckhdq %xmm2,%xmm0\npunpckldq %xmm2,%xmm1\nmovups %xmm0,0x10(%rax,%rdx,2)\nmovups %xmm1,(%rax,%rdx,2)\nadd $0x10,%rdx\ncmp %rdx,%rcx\njne 16d0 \nmov %esi,%edx\nand $0xfffffffc,%edx\ntest $0x3,%sil\nje 174a \nmovslq %edx,%rcx\nmov (%rbx,%rcx,4),%r8d\nlea (%rax,%rcx,8),%rdi\nmov %r8d,(%rdi)\nmov 0x4(%rbx,%rcx,4),%r8d\nlea 0x1(%rdx),%ecx\nmov %r8d,0x4(%rdi)\ncmp %ecx,%esi\njle 174a \nmovslq %ecx,%rcx\nadd $0x2,%edx\nlea (%rax,%rcx,8),%rdi\nmov 0x4(%rbx,%rcx,4),%ecx\nmov %r8d,(%rdi)\nmov %ecx,0x4(%rdi)\ncmp %edx,%esi\njle 174a \nmovslq %edx,%rdx\nlea (%rax,%rdx,8),%rsi\nmov 0x4(%rbx,%rdx,4),%edx\nmov %ecx,(%rsi)\nmov %edx,0x4(%rsi)\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nxor %edx,%edx\njmp 1704 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nsub esi, 1\nmov rbp, rdx\npush rbx\nmov rbx, rdi\nsub rsp, 8\nmov [rdx], esi\nmovsxd rsi, esi\nlea rdi, ds:0[rsi*8]; size\ncall _malloc\nmov edx, [rbp+0]\nmov rcx, rax\ntest edx, edx\njle loc_15B8\nlea eax, [rdx-1]\ncmp eax, 2\njbe loc_15C2\nmov esi, edx\nxor eax, eax\nshr esi, 2\nshl rsi, 4\nnop word ptr [rax+rax+00h]\nloc_1540:\nmovdqu xmm0, xmmword ptr [rbx+rax]\nmovdqu xmm3, xmmword ptr [rbx+rax+4]\nmovdqa xmm1, xmm0\npunpckhdq xmm0, xmm3\npunpckldq xmm1, xmm3\nmovups xmmword ptr [rcx+rax*2+10h], xmm0\nmovups xmmword ptr [rcx+rax*2], xmm1\nadd rax, 10h\ncmp rax, rsi\njnz short loc_1540\nmov eax, edx\nand eax, 0FFFFFFFCh\nmov esi, eax\ncmp edx, eax\njz short loc_15B8\nloc_1574:\nsub edx, esi\ncmp edx, 1\njz short loc_15AE\nmovq xmm0, qword ptr [rbx+rsi*4]\nmovq xmm1, qword ptr [rbx+rsi*4+4]\nlea rdi, [rcx+rsi*8]\nmovdqa xmm2, xmm0\npunpckldq xmm0, xmm1\npunpckldq xmm2, xmm1\npshufd xmm0, xmm0, 4Eh ; 'N'\nmovq qword ptr [rdi], xmm2\nmovq qword ptr [rdi+8], xmm0\ntest dl, 1\njz short loc_15B8\nand edx, 0FFFFFFFEh\nadd eax, edx\nloc_15AE:\ncdqe\nmov rdx, [rbx+rax*4]\nmov [rcx+rax*8], rdx\nloc_15B8:\nadd rsp, 8\nmov rax, rcx\npop rbx\npop rbp\nretn\nloc_15C2:\nxor esi, esi\nxor eax, eax\njmp short loc_1574", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, int a2, unsigned int *a3)\n{\n unsigned int v3; // esi\n _QWORD *v6; // rax\n unsigned int v7; // edx\n _QWORD *v8; // rcx\n __int64 v9; // rax\n __m128i v10; // xmm3\n __m128i v11; // xmm1\n signed int v12; // eax\n __int64 v13; // rsi\n int v14; // edx\n _QWORD *v15; // rdi\n __m128i v16; // xmm2\n\n v3 = a2 - 1;\n *a3 = v3;\n v6 = malloc(8LL * (int)v3);\n v7 = *a3;\n v8 = v6;\n if ( (int)*a3 > 0 )\n {\n if ( v7 - 1 <= 2 )\n {\n v13 = 0LL;\n v12 = 0;\n }\n else\n {\n v9 = 0LL;\n do\n {\n v10 = _mm_loadu_si128((const __m128i *)(a1 + v9 * 4 + 4));\n v11 = _mm_loadu_si128((const __m128i *)(a1 + v9 * 4));\n *(__m128i *)&v8[v9 + 2] = _mm_unpackhi_epi32(v11, v10);\n *(__m128i *)&v8[v9] = _mm_unpacklo_epi32(v11, v10);\n v9 += 4LL;\n }\n while ( v9 != 4LL * (v7 >> 2) );\n v12 = v7 & 0xFFFFFFFC;\n v13 = v7 & 0xFFFFFFFC;\n if ( v7 == (v7 & 0xFFFFFFFC) )\n return v8;\n }\n v14 = v7 - v13;\n if ( v14 == 1 )\n {\nLABEL_9:\n v8[v12] = *(_QWORD *)(a1 + 4LL * v12);\n return v8;\n }\n v15 = &v8[v13];\n v16 = _mm_unpacklo_epi32(\n _mm_loadl_epi64((const __m128i *)(a1 + 4 * v13)),\n _mm_loadl_epi64((const __m128i *)(a1 + 4 * v13 + 4)));\n *v15 = v16.m128i_i64[0];\n v15[1] = _mm_shuffle_epi32(v16, 78).m128i_u64[0];\n if ( (v14 & 1) != 0 )\n {\n v12 += v14 & 0xFFFFFFFE;\n goto LABEL_9;\n }\n }\n return v8;\n}", + "ida_strip_asm": "sub_14F0:\nendbr64\npush rbp\nsub esi, 1\nmov rbp, rdx\npush rbx\nmov rbx, rdi\nsub rsp, 8\nmov [rdx], esi\nmovsxd rsi, esi\nlea rdi, ds:0[rsi*8]; size\ncall _malloc\nmov edx, [rbp+0]\nmov rcx, rax\ntest edx, edx\njle loc_15B8\nlea eax, [rdx-1]\ncmp eax, 2\njbe loc_15C2\nmov esi, edx\nxor eax, eax\nshr esi, 2\nshl rsi, 4\nnop word ptr [rax+rax+00h]\nloc_1540:\nmovdqu xmm0, xmmword ptr [rbx+rax]\nmovdqu xmm3, xmmword ptr [rbx+rax+4]\nmovdqa xmm1, xmm0\npunpckhdq xmm0, xmm3\npunpckldq xmm1, xmm3\nmovups xmmword ptr [rcx+rax*2+10h], xmm0\nmovups xmmword ptr [rcx+rax*2], xmm1\nadd rax, 10h\ncmp rax, rsi\njnz short loc_1540\nmov eax, edx\nand eax, 0FFFFFFFCh\nmov esi, eax\ncmp edx, eax\njz short loc_15B8\nloc_1574:\nsub edx, esi\ncmp edx, 1\njz short loc_15AE\nmovq xmm0, qword ptr [rbx+rsi*4]\nmovq xmm1, qword ptr [rbx+rsi*4+4]\nlea rdi, [rcx+rsi*8]\nmovdqa xmm2, xmm0\npunpckldq xmm0, xmm1\npunpckldq xmm2, xmm1\npshufd xmm0, xmm0, 4Eh ; 'N'\nmovq qword ptr [rdi], xmm2\nmovq qword ptr [rdi+8], xmm0\ntest dl, 1\njz short loc_15B8\nand edx, 0FFFFFFFEh\nadd eax, edx\nloc_15AE:\ncdqe\nmov rdx, [rbx+rax*4]\nmov [rcx+rax*8], rdx\nloc_15B8:\nadd rsp, 8\nmov rax, rcx\npop rbx\npop rbp\nretn\nloc_15C2:\nxor esi, esi\nxor eax, eax\njmp short loc_1574", + "ida_strip_pseudo": "_QWORD *__fastcall sub_14F0(__int64 a1, int a2, unsigned int *a3)\n{\n unsigned int v3; // esi\n _QWORD *v6; // rax\n unsigned int v7; // edx\n _QWORD *v8; // rcx\n __int64 v9; // rax\n __m128i v10; // xmm3\n __m128i v11; // xmm1\n signed int v12; // eax\n __int64 v13; // rsi\n int v14; // edx\n _QWORD *v15; // rdi\n __m128i v16; // xmm2\n\n v3 = a2 - 1;\n *a3 = v3;\n v6 = malloc(8LL * (int)v3);\n v7 = *a3;\n v8 = v6;\n if ( (int)*a3 > 0 )\n {\n if ( v7 - 1 <= 2 )\n {\n v13 = 0LL;\n v12 = 0;\n }\n else\n {\n v9 = 0LL;\n do\n {\n v10 = _mm_loadu_si128((const __m128i *)(a1 + v9 * 4 + 4));\n v11 = _mm_loadu_si128((const __m128i *)(a1 + v9 * 4));\n *(__m128i *)&v8[v9 + 2] = _mm_unpackhi_epi32(v11, v10);\n *(__m128i *)&v8[v9] = _mm_unpacklo_epi32(v11, v10);\n v9 += 4LL;\n }\n while ( v9 != 4LL * (v7 >> 2) );\n v12 = v7 & 0xFFFFFFFC;\n v13 = v7 & 0xFFFFFFFC;\n if ( v7 == (v7 & 0xFFFFFFFC) )\n return v8;\n }\n v14 = v7 - v13;\n if ( v14 == 1 )\n {\nLABEL_9:\n v8[v12] = *(_QWORD *)(a1 + 4LL * v12);\n return v8;\n }\n v15 = &v8[v13];\n v16 = _mm_unpacklo_epi32(\n _mm_loadl_epi64((const __m128i *)(a1 + 4 * v13)),\n _mm_loadl_epi64((const __m128i *)(a1 + 4 * v13 + 4)));\n *v15 = v16.m128i_i64[0];\n v15[1] = _mm_shuffle_epi32(v16, 78).m128i_u64[0];\n if ( (v14 & 1) != 0 )\n {\n v12 += v14 & 0xFFFFFFFE;\n goto LABEL_9;\n }\n }\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_14F0(long long a1, int a2, unsigned int *a3) {\n unsigned int v3;\n uint64_t *v6;\n unsigned int v7;\n uint64_t *v8;\n long long v9;\n __m128i v10;\n __m128i v11;\n signed int v12;\n long long v13;\n int v14;\n uint64_t *v15;\n __m128i v16;\n v3 = a2 - 1;\n *a3 = v3;\n v6 = malloc(8LL * (int)v3);\n v7 = *a3;\n v8 = v6;\n if ((int)*a3 > 0) {\n if (v7 - 1 <= 2) {\n v13 = 0LL;\n v12 = 0;\n } else {\n v9 = 0LL;\n do {\n v10 = _mm_loadu_si128((const __m128i *)(a1 + v9 * 4 + 4));\n v11 = _mm_loadu_si128((const __m128i *)(a1 + v9 * 4));\n *(__m128i *)&v8[v9 + 2] = _mm_unpackhi_epi32(v11, v10);\n *(__m128i *)&v8[v9] = _mm_unpacklo_epi32(v11, v10);\n v9 += 4LL;\n } while (v9 != 4LL * (v7 >> 2));\n v12 = v7 & 4294967292;\n v13 = v7 & 4294967292;\n if (v7 == (v7 & 4294967292)) return v8;\n }\n v14 = v7 - v13;\n if (v14 == 1) {\n LABEL_9:\n v8[v12] = *(uint64_t *)(a1 + 4LL * v12);\n return v8;\n }\n v15 = &v8[v13];\n v16 = _mm_unpacklo_epi32(\n _mm_loadl_epi64((const __m128i *)(a1 + 4 * v13)),\n _mm_loadl_epi64((const __m128i *)(a1 + 4 * v13 + 4)));\n *v15 = v16.m128i_i64[0];\n v15[1] = _mm_shuffle_epi32(v16, 78).m128i_u64[0];\n if ((v14 & 1) != 0) {\n v12 += v14 & 4294967294;\n goto LABEL_9;\n }\n }\n return v8;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, int a2, unsigned int *a3) {\n unsigned int v3;\n uint64_t *v6;\n unsigned int v7;\n uint64_t *v8;\n long long v9;\n __m128i v10;\n __m128i v11;\n signed int v12;\n long long v13;\n int v14;\n uint64_t *v15;\n __m128i v16;\n v3 = a2 - 1;\n *a3 = v3;\n v6 = malloc(8LL * (int)v3);\n v7 = *a3;\n v8 = v6;\n if ((int)*a3 > 0) {\n if (v7 - 1 <= 2) {\n v13 = 0LL;\n v12 = 0;\n } else {\n v9 = 0LL;\n do {\n v10 = _mm_loadu_si128((const __m128i *)(a1 + v9 * 4 + 4));\n v11 = _mm_loadu_si128((const __m128i *)(a1 + v9 * 4));\n *(__m128i *)&v8[v9 + 2] = _mm_unpackhi_epi32(v11, v10);\n *(__m128i *)&v8[v9] = _mm_unpacklo_epi32(v11, v10);\n v9 += 4LL;\n } while (v9 != 4LL * (v7 >> 2));\n v12 = v7 & 4294967292;\n v13 = v7 & 4294967292;\n if (v7 == (v7 & 4294967292)) return v8;\n }\n v14 = v7 - v13;\n if (v14 == 1) {\n LABEL_9:\n v8[v12] = *(uint64_t *)(a1 + 4LL * v12);\n return v8;\n }\n v15 = &v8[v13];\n v16 = _mm_unpacklo_epi32(\n _mm_loadl_epi64((const __m128i *)(a1 + 4 * v13)),\n _mm_loadl_epi64((const __m128i *)(a1 + 4 * v13 + 4)));\n *v15 = v16.m128i_i64[0];\n v15[1] = _mm_shuffle_epi32(v16, 78).m128i_u64[0];\n if ((v14 & 1) != 0) {\n v12 += v14 & 4294967294;\n goto LABEL_9;\n }\n }\n return v8;\n}" + }, + { + "index": 767, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n, int sum) {\n int count = 0;\n for (int i = 0; i < n; i++) {\n for (int j = i + 1; j < n; j++) {\n if (arr[i] + arr[j] == sum) {\n count += 1;\n }\n }\n }\n return count;\n}", + "test": "int main() {\n\n int arr1[] = {1, 1, 1, 1};\n\n int arr2[] = {1, 5, 7, -1, 5};\n\n int arr3[] = {1, -2, 3};\n\n\n\n assert(func0(arr1, 4, 2) == 6);\n\n assert(func0(arr2, 5, 6) == 3);\n\n assert(func0(arr3, 3, 1) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11dd \nmov -0x8(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x4(%rbp)\njmp 11d1 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\nadd %edx,%eax\ncmp %eax,-0x20(%rbp)\njne 11cd \naddl $0x1,-0xc(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1196 \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 118b \nmov -0xc(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_11DD\nloc_118B:\nmov eax, [rbp+var_8]\nadd eax, 1\nmov [rbp+var_4], eax\njmp short loc_11D1\nloc_1196:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nadd eax, edx\ncmp [rbp+var_20], eax\njnz short loc_11CD\nadd [rbp+var_C], 1\nloc_11CD:\nadd [rbp+var_4], 1\nloc_11D1:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1196\nadd [rbp+var_8], 1\nloc_11DD:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_118B\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n unsigned int v4; // [rsp+14h] [rbp-Ch]\n int i; // [rsp+18h] [rbp-8h]\n int j; // [rsp+1Ch] [rbp-4h]\n\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( a3 == *(_DWORD *)(4LL * i + a1) + *(_DWORD *)(4LL * j + a1) )\n ++v4;\n }\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_11DD\nloc_118B:\nmov eax, [rbp+var_8]\nadd eax, 1\nmov [rbp+var_4], eax\njmp short loc_11D1\nloc_1196:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nadd eax, edx\ncmp [rbp+var_20], eax\njnz short loc_11CD\nadd [rbp+var_C], 1\nloc_11CD:\nadd [rbp+var_4], 1\nloc_11D1:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1196\nadd [rbp+var_8], 1\nloc_11DD:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_118B\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n unsigned int v4; // [rsp+14h] [rbp-Ch]\n int i; // [rsp+18h] [rbp-8h]\n int j; // [rsp+1Ch] [rbp-4h]\n\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( a3 == *(_DWORD *)(4LL * i + a1) + *(_DWORD *)(4LL * j + a1) )\n ++v4;\n }\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n unsigned int v4;\n int i;\n int j;\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if (a3 == *(uint32_t *)(4LL * i + a1) + *(uint32_t *)(4LL * j + a1)) ++v4;\n }\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n unsigned int v4;\n int i;\n int j;\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if (a3 == *(uint32_t *)(4LL * i + a1) + *(uint32_t *)(4LL * j + a1)) ++v4;\n }\n }\n return v4;\n}" + }, + { + "index": 767, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n, int sum) {\n int count = 0;\n for (int i = 0; i < n; i++) {\n for (int j = i + 1; j < n; j++) {\n if (arr[i] + arr[j] == sum) {\n count += 1;\n }\n }\n }\n return count;\n}", + "test": "int main() {\n\n int arr1[] = {1, 1, 1, 1};\n\n int arr2[] = {1, 5, 7, -1, 5};\n\n int arr3[] = {1, -2, 3};\n\n\n\n assert(func0(arr1, 4, 2) == 6);\n\n assert(func0(arr2, 5, 6) == 3);\n\n assert(func0(arr3, 3, 1) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11b4 \nlea -0x1(%rsi),%r11d\nadd $0x1,%r11\nmov $0x1,%r10d\nmov $0x0,%ecx\ncmp %r11,%r10\nje 11b9 \nmov -0x4(%rdi,%r10,4),%r9d\nmov %r10,%rax\nmov %r9d,%r8d\nadd (%rdi,%rax,4),%r8d\ncmp %edx,%r8d\nsete %r8b\nmovzbl %r8b,%r8d\nadd %r8d,%ecx\nadd $0x1,%rax\ncmp %eax,%esi\njg 1191 \nadd $0x1,%r10\njmp 1184 \nmov $0x0,%ecx\nmov %ecx,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11C0\npush rbx\nmov r8, rdi\nmov r11d, esi\nmovsxd rbx, esi\nmov r10d, 1\nmov ecx, 0\njmp short loc_118B\nloc_1188:\nmov r10, rax\nloc_118B:\ncmp r10, r11\njz short loc_11BC\nmov r9d, [r8+r10*4-4]\nmov rax, r10\nloc_1198:\nmov edi, r9d\nadd edi, [r8+rax*4]\ncmp edi, edx\nsetz dil\nmovzx edi, dil\nadd ecx, edi\nadd rax, 1\ncmp esi, eax\njg short loc_1198\nlea rax, [r10+1]\ncmp r10, rbx\njnz short loc_1188\nloc_11BC:\nmov eax, ecx\npop rbx\nretn\nloc_11C0:\nmov ecx, 0\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n __int64 v3; // r10\n unsigned int v4; // ecx\n __int64 v5; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v3 = 1LL;\n v4 = 0;\n while ( v3 != a2 )\n {\n v5 = v3;\n do\n v4 += *(_DWORD *)(a1 + 4 * v5++) + *(_DWORD *)(a1 + 4 * v3 - 4) == a3;\n while ( a2 > (int)v5 );\n if ( v3 == a2 )\n break;\n ++v3;\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11C0\npush rbx\nmov r8, rdi\nmov r11d, esi\nmovsxd rbx, esi\nmov r10d, 1\nmov ecx, 0\njmp short loc_118B\nloc_1188:\nmov r10, rax\nloc_118B:\ncmp r10, r11\njz short loc_11BC\nmov r9d, [r8+r10*4-4]\nmov rax, r10\nloc_1198:\nmov edi, r9d\nadd edi, [r8+rax*4]\ncmp edi, edx\nsetz dil\nmovzx edi, dil\nadd ecx, edi\nadd rax, 1\ncmp esi, eax\njg short loc_1198\nlea rax, [r10+1]\ncmp r10, rbx\njnz short loc_1188\nloc_11BC:\nmov eax, ecx\npop rbx\nretn\nloc_11C0:\nmov ecx, 0\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n __int64 v3; // r10\n unsigned int v4; // ecx\n __int64 v5; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v3 = 1LL;\n v4 = 0;\n while ( v3 != a2 )\n {\n v5 = v3;\n do\n v4 += *(_DWORD *)(a1 + 4 * v5++) + *(_DWORD *)(a1 + 4 * v3 - 4) == a3;\n while ( a2 > (int)v5 );\n if ( v3 == a2 )\n break;\n ++v3;\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n long long v3;\n unsigned int v4;\n long long v5;\n if (a2 <= 0) return 0LL;\n v3 = 1LL;\n v4 = 0;\n while (v3 != a2) {\n v5 = v3;\n do\n v4 += *(uint32_t *)(a1 + 4 * v5++) + *(uint32_t *)(a1 + 4 * v3 - 4) == a3;\n while (a2 > (int)v5);\n if (v3 == a2) break;\n ++v3;\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n long long v3;\n unsigned int v4;\n long long v5;\n if (a2 <= 0) return 0LL;\n v3 = 1LL;\n v4 = 0;\n while (v3 != a2) {\n v5 = v3;\n do\n v4 += *(uint32_t *)(a1 + 4 * v5++) + *(uint32_t *)(a1 + 4 * v3 - 4) == a3;\n while (a2 > (int)v5);\n if (v3 == a2) break;\n ++v3;\n }\n return v4;\n}" + }, + { + "index": 767, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n, int sum) {\n int count = 0;\n for (int i = 0; i < n; i++) {\n for (int j = i + 1; j < n; j++) {\n if (arr[i] + arr[j] == sum) {\n count += 1;\n }\n }\n }\n return count;\n}", + "test": "int main() {\n\n int arr1[] = {1, 1, 1, 1};\n\n int arr2[] = {1, 5, 7, -1, 5};\n\n int arr3[] = {1, -2, 3};\n\n\n\n assert(func0(arr1, 4, 2) == 6);\n\n assert(func0(arr2, 5, 6) == 3);\n\n assert(func0(arr3, 3, 1) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 13a6 \nlea -0x1(%rsi),%r11d\nmov $0x1,%r10d\nxor %r8d,%r8d\nadd $0x1,%r11\ncmp %r11,%r10\nje 13a2 \nxchg %ax,%ax\nmov -0x4(%rdi,%r10,4),%r9d\nmov %r10,%rax\nnopl 0x0(%rax,%rax,1)\nmov (%rdi,%rax,4),%ecx\nadd %r9d,%ecx\ncmp %edx,%ecx\nsete %cl\nadd $0x1,%rax\nmovzbl %cl,%ecx\nadd %ecx,%r8d\ncmp %eax,%esi\njg 1380 \nadd $0x1,%r10\ncmp %r11,%r10\njne 1370 \nmov %r8d,%eax\nretq\nxor %r8d,%r8d\nmov %r8d,%eax\nretq\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_12D9\nmov r11d, esi\nmov r10d, 1\nxor ecx, ecx\ncmp esi, 1\njz short loc_12D6\nnop dword ptr [rax+rax+00000000h]\nloc_12A0:\nmov r9d, [rdi+r10*4-4]\nmov rax, r10\nnop dword ptr [rax+rax+00000000h]\nloc_12B0:\nmov r8d, [rdi+rax*4]\nadd r8d, r9d\ncmp edx, r8d\nsetz r8b\nadd rax, 1\nmovzx r8d, r8b\nadd ecx, r8d\ncmp esi, eax\njg short loc_12B0\nadd r10, 1\ncmp r10, r11\njnz short loc_12A0\nloc_12D6:\nmov eax, ecx\nretn\nloc_12D9:\nxor ecx, ecx\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n __int64 v3; // r10\n unsigned int v4; // ecx\n __int64 v5; // rax\n bool v6; // r8\n\n if ( a2 <= 0 )\n return 0LL;\n v3 = 1LL;\n v4 = 0;\n if ( a2 != 1 )\n {\n do\n {\n v5 = v3;\n do\n {\n v6 = a3 == *(_DWORD *)(a1 + 4 * v3 - 4) + *(_DWORD *)(a1 + 4 * v5++);\n v4 += v6;\n }\n while ( a2 > (int)v5 );\n ++v3;\n }\n while ( v3 != a2 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\ntest esi, esi\njle short loc_12D9\nmov r11d, esi\nmov r10d, 1\nxor ecx, ecx\ncmp esi, 1\njz short loc_12D6\nnop dword ptr [rax+rax+00000000h]\nloc_12A0:\nmov r9d, [rdi+r10*4-4]\nmov rax, r10\nnop dword ptr [rax+rax+00000000h]\nloc_12B0:\nmov r8d, [rdi+rax*4]\nadd r8d, r9d\ncmp edx, r8d\nsetz r8b\nadd rax, 1\nmovzx r8d, r8b\nadd ecx, r8d\ncmp esi, eax\njg short loc_12B0\nadd r10, 1\ncmp r10, r11\njnz short loc_12A0\nloc_12D6:\nmov eax, ecx\nretn\nloc_12D9:\nxor ecx, ecx\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1280(__int64 a1, int a2, int a3)\n{\n __int64 v3; // r10\n unsigned int v4; // ecx\n __int64 v5; // rax\n bool v6; // r8\n\n if ( a2 <= 0 )\n return 0LL;\n v3 = 1LL;\n v4 = 0;\n if ( a2 != 1 )\n {\n do\n {\n v5 = v3;\n do\n {\n v6 = a3 == *(_DWORD *)(a1 + 4 * v3 - 4) + *(_DWORD *)(a1 + 4 * v5++);\n v4 += v6;\n }\n while ( a2 > (int)v5 );\n ++v3;\n }\n while ( v3 != a2 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1280(long long a1, int a2, int a3) {\n long long v3;\n unsigned int v4;\n long long v5;\n bool v6;\n if (a2 <= 0) return 0LL;\n v3 = 1LL;\n v4 = 0;\n if (a2 != 1) {\n do {\n v5 = v3;\n do {\n v6 =\n a3 == *(uint32_t *)(a1 + 4 * v3 - 4) + *(uint32_t *)(a1 + 4 * v5++);\n v4 += v6;\n } while (a2 > (int)v5);\n ++v3;\n } while (v3 != a2);\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n long long v3;\n unsigned int v4;\n long long v5;\n bool v6;\n if (a2 <= 0) return 0LL;\n v3 = 1LL;\n v4 = 0;\n if (a2 != 1) {\n do {\n v5 = v3;\n do {\n v6 =\n a3 == *(uint32_t *)(a1 + 4 * v3 - 4) + *(uint32_t *)(a1 + 4 * v5++);\n v4 += v6;\n } while (a2 > (int)v5);\n ++v3;\n } while (v3 != a2);\n }\n return v4;\n}" + }, + { + "index": 768, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int x) {\n int parity = 0;\n while (x != 0) {\n x = x & (x - 1);\n parity++;\n }\n return (parity % 2 == 1);\n}", + "test": "int main() {\n\n assert(func0(13) == 1);\n\n assert(func0(21) == 1);\n\n assert(func0(18) == 0);\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 116a \nmov -0x14(%rbp),%eax\nsub $0x1,%eax\nand %eax,-0x14(%rbp)\naddl $0x1,-0x4(%rbp)\ncmpl $0x0,-0x14(%rbp)\njne 115d \nmov -0x4(%rbp),%eax\ncltd\nshr $0x1f,%edx\nadd %edx,%eax\nand $0x1,%eax\nsub %edx,%eax\ncmp $0x1,%eax\nsete %al\nmovzbl %al,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_4], 0\njmp short loc_116A\nloc_115D:\nmov eax, [rbp+var_14]\nsub eax, 1\nand [rbp+var_14], eax\nadd [rbp+var_4], 1\nloc_116A:\ncmp [rbp+var_14], 0\njnz short loc_115D\nmov edx, [rbp+var_4]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\ncmp eax, 1\nsetz al\nmovzx eax, al\npop rbp\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(int a1)\n{\n int v3; // [rsp+10h] [rbp-4h]\n\n v3 = 0;\n while ( a1 )\n {\n a1 &= a1 - 1;\n ++v3;\n }\n return v3 % 2 == 1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_4], 0\njmp short loc_116A\nloc_115D:\nmov eax, [rbp+var_14]\nsub eax, 1\nand [rbp+var_14], eax\nadd [rbp+var_4], 1\nloc_116A:\ncmp [rbp+var_14], 0\njnz short loc_115D\nmov edx, [rbp+var_4]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\ncmp eax, 1\nsetz al\nmovzx eax, al\npop rbp\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1149(int a1)\n{\n int v3; // [rsp+10h] [rbp-4h]\n\n v3 = 0;\n while ( a1 )\n {\n a1 &= a1 - 1;\n ++v3;\n }\n return v3 % 2 == 1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1149(int a1) {\n int v3;\n v3 = 0;\n while (a1) {\n a1 &= a1 - 1;\n ++v3;\n }\n return v3 % 2 == 1;\n}", + "ida_pseudo_norm": "uint8_t func0(int a1) {\n int v3;\n v3 = 0;\n while (a1) {\n a1 &= a1 - 1;\n ++v3;\n }\n return v3 % 2 == 1;\n}" + }, + { + "index": 768, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int x) {\n int parity = 0;\n while (x != 0) {\n x = x & (x - 1);\n parity++;\n }\n return (parity % 2 == 1);\n}", + "test": "int main() {\n\n assert(func0(13) == 1);\n\n assert(func0(21) == 1);\n\n assert(func0(18) == 0);\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\nje 1176 \nmov $0x0,%eax\nlea -0x1(%rdi),%edx\nadd $0x1,%eax\nand %edx,%edi\njne 1156 \nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nand $0x1,%eax\nsub %edx,%eax\ncmp $0x1,%eax\nsete %al\nmovzbl %al,%eax\nretq\nmov %edi,%eax\njmp 1160 \n", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njz short loc_1176\nmov eax, 0\nloc_1156:\nlea edx, [rdi-1]\nadd eax, 1\nand edi, edx\njnz short loc_1156\nloc_1160:\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nand eax, 1\nsub eax, edx\ncmp eax, 1\nsetz al\nmovzx eax, al\nretn\nloc_1176:\nmov eax, edi\njmp short loc_1160", + "ida_pseudo": "_BOOL8 __fastcall func0(int a1)\n{\n int v1; // eax\n\n if ( a1 )\n {\n v1 = 0;\n do\n {\n ++v1;\n a1 &= a1 - 1;\n }\n while ( a1 );\n }\n else\n {\n v1 = 0;\n }\n return v1 % 2 == 1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ntest edi, edi\njz short loc_1176\nmov eax, 0\nloc_1156:\nlea edx, [rdi-1]\nadd eax, 1\nand edi, edx\njnz short loc_1156\nloc_1160:\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nand eax, 1\nsub eax, edx\ncmp eax, 1\nsetz al\nmovzx eax, al\nretn\nloc_1176:\nmov eax, edi\njmp short loc_1160", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1149(int a1)\n{\n int v1; // eax\n\n if ( a1 )\n {\n v1 = 0;\n do\n {\n ++v1;\n a1 &= a1 - 1;\n }\n while ( a1 );\n }\n else\n {\n v1 = 0;\n }\n return v1 % 2 == 1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1149(int a1) {\n int v1;\n if (a1) {\n v1 = 0;\n do {\n ++v1;\n a1 &= a1 - 1;\n } while (a1);\n } else {\n v1 = 0;\n }\n return v1 % 2 == 1;\n}", + "ida_pseudo_norm": "uint8_t func0(int a1) {\n int v1;\n if (a1) {\n v1 = 0;\n do {\n ++v1;\n a1 &= a1 - 1;\n } while (a1);\n } else {\n v1 = 0;\n }\n return v1 % 2 == 1;\n}" + }, + { + "index": 769, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\nint compare(const void *a, const void *b) {\n\n return (*(int*)a - *(int*)b);\n\n}\n\n\n\n", + "func": "int *func0(int *li1, int li1Size, int *li2, int li2Size, int *resultSize) {\n int *result = malloc((li1Size + li2Size) * sizeof(int));\n int i, j;\n int index = 0;\n int found;\n for (i = 0; i < li1Size; i++) {\n found = 0;\n for (j = 0; j < li2Size; j++) {\n if (li1[i] == li2[j]) {\n found = 1;\n break;\n }\n }\n if (!found) {\n result[index++] = li1[i];\n }\n }\n for (i = 0; i < li2Size; i++) {\n found = 0;\n for (j = 0; j < li1Size; j++) {\n if (li2[i] == li1[j]) {\n found = 1;\n break;\n }\n }\n if (!found) {\n result[index++] = li2[i];\n }\n }\n *resultSize = index;\n return result;\n}", + "test": "int main() {\n\n int resultSize;\n\n int *result;\n\n\n\n int li1[] = {10, 15, 20, 25, 30, 35, 40};\n\n int li2[] = {25, 40, 35};\n\n result = func0(li1, 7, li2, 3, &resultSize);\n\n qsort(result, resultSize, sizeof(int), compare);\n\n int expected1[] = {10, 15, 20, 30};\n\n assert(resultSize == 4 && memcmp(result, expected1, resultSize * sizeof(int)) == 0);\n\n free(result);\n\n\n\n int li3[] = {1, 2, 3, 4, 5};\n\n int li4[] = {6, 7, 1};\n\n result = func0(li3, 5, li4, 3, &resultSize);\n\n qsort(result, resultSize, sizeof(int), compare);\n\n int expected2[] = {2, 3, 4, 5, 6, 7};\n\n assert(resultSize == 6 && memcmp(result, expected2, resultSize * sizeof(int)) == 0);\n\n free(result);\n\n\n\n int li5[] = {1, 2, 3};\n\n int li6[] = {6, 7, 1};\n\n result = func0(li5, 3, li6, 3, &resultSize);\n\n qsort(result, resultSize, sizeof(int), compare);\n\n int expected3[] = {2, 3, 6, 7};\n\n assert(resultSize == 4 && memcmp(result, expected3, resultSize * sizeof(int)) == 0);\n\n free(result);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x40,%rsp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmov %rdx,-0x38(%rbp)\nmov %ecx,-0x30(%rbp)\nmov %r8,-0x40(%rbp)\nmov -0x2c(%rbp),%edx\nmov -0x30(%rbp),%eax\nadd %edx,%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10f0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0x10(%rbp)\nmovl $0x0,-0x18(%rbp)\njmpq 12e8 \nmovl $0x0,-0xc(%rbp)\nmovl $0x0,-0x14(%rbp)\njmp 12a3 \nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x38(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 129f \nmovl $0x1,-0xc(%rbp)\njmp 12ab \naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\ncmp -0x30(%rbp),%eax\njl 1266 \ncmpl $0x0,-0xc(%rbp)\njne 12e4 \nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x10(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x10(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 1256 \nmovl $0x0,-0x18(%rbp)\njmpq 1392 \nmovl $0x0,-0xc(%rbp)\nmovl $0x0,-0x14(%rbp)\njmp 134d \nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 1349 \nmovl $0x1,-0xc(%rbp)\njmp 1355 \naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 1310 \ncmpl $0x0,-0xc(%rbp)\njne 138e \nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x38(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x10(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x10(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%eax\ncmp -0x30(%rbp),%eax\njl 1300 \nmov -0x40(%rbp),%rax\nmov -0x10(%rbp),%edx\nmov %edx,(%rax)\nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmov [rbp+var_30], ecx\nmov [rbp+var_40], r8\nmov edx, [rbp+var_2C]\nmov eax, [rbp+var_30]\nadd eax, edx\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_10], 0\nmov [rbp+var_18], 0\njmp loc_12E8\nloc_1256:\nmov [rbp+var_C], 0\nmov [rbp+var_14], 0\njmp short loc_12A3\nloc_1266:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_14]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_129F\nmov [rbp+var_C], 1\njmp short loc_12AB\nloc_129F:\nadd [rbp+var_14], 1\nloc_12A3:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_30]\njl short loc_1266\nloc_12AB:\ncmp [rbp+var_C], 0\njnz short loc_12E4\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_12E4:\nadd [rbp+var_18], 1\nloc_12E8:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_2C]\njl loc_1256\nmov [rbp+var_18], 0\njmp loc_1392\nloc_1300:\nmov [rbp+var_C], 0\nmov [rbp+var_14], 0\njmp short loc_134D\nloc_1310:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_14]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_1349\nmov [rbp+var_C], 1\njmp short loc_1355\nloc_1349:\nadd [rbp+var_14], 1\nloc_134D:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl short loc_1310\nloc_1355:\ncmp [rbp+var_C], 0\njnz short loc_138E\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_138E:\nadd [rbp+var_18], 1\nloc_1392:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_30]\njl loc_1300\nmov rax, [rbp+var_40]\nmov edx, [rbp+var_10]\nmov [rax], edx\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, __int64 a3, int a4, _DWORD *a5)\n{\n int v5; // eax\n int v6; // eax\n int i; // [rsp+28h] [rbp-18h]\n int k; // [rsp+28h] [rbp-18h]\n int j; // [rsp+2Ch] [rbp-14h]\n int m; // [rsp+2Ch] [rbp-14h]\n int v15; // [rsp+30h] [rbp-10h]\n int v16; // [rsp+34h] [rbp-Ch]\n int v17; // [rsp+34h] [rbp-Ch]\n _DWORD *v18; // [rsp+38h] [rbp-8h]\n\n v18 = malloc(4LL * (a2 + a4));\n v15 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v16 = 0;\n for ( j = 0; j < a4; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4LL * j + a3) )\n {\n v16 = 1;\n break;\n }\n }\n if ( !v16 )\n {\n v5 = v15++;\n v18[v5] = *(_DWORD *)(4LL * i + a1);\n }\n }\n for ( k = 0; k < a4; ++k )\n {\n v17 = 0;\n for ( m = 0; m < a2; ++m )\n {\n if ( *(_DWORD *)(4LL * k + a3) == *(_DWORD *)(4LL * m + a1) )\n {\n v17 = 1;\n break;\n }\n }\n if ( !v17 )\n {\n v6 = v15++;\n v18[v6] = *(_DWORD *)(4LL * k + a3);\n }\n }\n *a5 = v15;\n return v18;\n}", + "ida_strip_asm": "sub_120B:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmov [rbp+var_30], ecx\nmov [rbp+var_40], r8\nmov edx, [rbp+var_2C]\nmov eax, [rbp+var_30]\nadd eax, edx\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_10], 0\nmov [rbp+var_18], 0\njmp loc_12E8\nloc_1256:\nmov [rbp+var_C], 0\nmov [rbp+var_14], 0\njmp short loc_12A3\nloc_1266:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_14]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_129F\nmov [rbp+var_C], 1\njmp short loc_12AB\nloc_129F:\nadd [rbp+var_14], 1\nloc_12A3:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_30]\njl short loc_1266\nloc_12AB:\ncmp [rbp+var_C], 0\njnz short loc_12E4\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_12E4:\nadd [rbp+var_18], 1\nloc_12E8:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_2C]\njl loc_1256\nmov [rbp+var_18], 0\njmp loc_1392\nloc_1300:\nmov [rbp+var_C], 0\nmov [rbp+var_14], 0\njmp short loc_134D\nloc_1310:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_14]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_1349\nmov [rbp+var_C], 1\njmp short loc_1355\nloc_1349:\nadd [rbp+var_14], 1\nloc_134D:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl short loc_1310\nloc_1355:\ncmp [rbp+var_C], 0\njnz short loc_138E\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_138E:\nadd [rbp+var_18], 1\nloc_1392:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_30]\njl loc_1300\nmov rax, [rbp+var_40]\nmov edx, [rbp+var_10]\nmov [rax], edx\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_120B(__int64 a1, int a2, __int64 a3, int a4, _DWORD *a5)\n{\n int v5; // eax\n int v6; // eax\n int i; // [rsp+28h] [rbp-18h]\n int k; // [rsp+28h] [rbp-18h]\n int j; // [rsp+2Ch] [rbp-14h]\n int m; // [rsp+2Ch] [rbp-14h]\n int v15; // [rsp+30h] [rbp-10h]\n int v16; // [rsp+34h] [rbp-Ch]\n int v17; // [rsp+34h] [rbp-Ch]\n _DWORD *v18; // [rsp+38h] [rbp-8h]\n\n v18 = malloc(4LL * (a2 + a4));\n v15 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v16 = 0;\n for ( j = 0; j < a4; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4LL * j + a3) )\n {\n v16 = 1;\n break;\n }\n }\n if ( !v16 )\n {\n v5 = v15++;\n v18[v5] = *(_DWORD *)(4LL * i + a1);\n }\n }\n for ( k = 0; k < a4; ++k )\n {\n v17 = 0;\n for ( m = 0; m < a2; ++m )\n {\n if ( *(_DWORD *)(4LL * k + a3) == *(_DWORD *)(4LL * m + a1) )\n {\n v17 = 1;\n break;\n }\n }\n if ( !v17 )\n {\n v6 = v15++;\n v18[v6] = *(_DWORD *)(4LL * k + a3);\n }\n }\n *a5 = v15;\n return v18;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_120B(long long a1, int a2, long long a3, int a4, uint32_t *a5) {\n int v5;\n int v6;\n int i;\n int k;\n int j;\n int m;\n int v15;\n int v16;\n int v17;\n uint32_t *v18;\n v18 = malloc(4LL * (a2 + a4));\n v15 = 0;\n for (i = 0; i < a2; ++i) {\n v16 = 0;\n for (j = 0; j < a4; ++j) {\n if (*(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4LL * j + a3)) {\n v16 = 1;\n break;\n }\n }\n if (!v16) {\n v5 = v15++;\n v18[v5] = *(uint32_t *)(4LL * i + a1);\n }\n }\n for (k = 0; k < a4; ++k) {\n v17 = 0;\n for (m = 0; m < a2; ++m) {\n if (*(uint32_t *)(4LL * k + a3) == *(uint32_t *)(4LL * m + a1)) {\n v17 = 1;\n break;\n }\n }\n if (!v17) {\n v6 = v15++;\n v18[v6] = *(uint32_t *)(4LL * k + a3);\n }\n }\n *a5 = v15;\n return v18;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, long long a3, int a4, uint32_t *a5) {\n int v5;\n int v6;\n int i;\n int k;\n int j;\n int m;\n int v15;\n int v16;\n int v17;\n uint32_t *v18;\n v18 = malloc(4LL * (a2 + a4));\n v15 = 0;\n for (i = 0; i < a2; ++i) {\n v16 = 0;\n for (j = 0; j < a4; ++j) {\n if (*(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4LL * j + a3)) {\n v16 = 1;\n break;\n }\n }\n if (!v16) {\n v5 = v15++;\n v18[v5] = *(uint32_t *)(4LL * i + a1);\n }\n }\n for (k = 0; k < a4; ++k) {\n v17 = 0;\n for (m = 0; m < a2; ++m) {\n if (*(uint32_t *)(4LL * k + a3) == *(uint32_t *)(4LL * m + a1)) {\n v17 = 1;\n break;\n }\n }\n if (!v17) {\n v6 = v15++;\n v18[v6] = *(uint32_t *)(4LL * k + a3);\n }\n }\n *a5 = v15;\n return v18;\n}" + }, + { + "index": 769, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\nint compare(const void *a, const void *b) {\n\n return (*(int*)a - *(int*)b);\n\n}\n\n\n\n", + "func": "int *func0(int *li1, int li1Size, int *li2, int li2Size, int *resultSize) {\n int *result = malloc((li1Size + li2Size) * sizeof(int));\n int i, j;\n int index = 0;\n int found;\n for (i = 0; i < li1Size; i++) {\n found = 0;\n for (j = 0; j < li2Size; j++) {\n if (li1[i] == li2[j]) {\n found = 1;\n break;\n }\n }\n if (!found) {\n result[index++] = li1[i];\n }\n }\n for (i = 0; i < li2Size; i++) {\n found = 0;\n for (j = 0; j < li1Size; j++) {\n if (li2[i] == li1[j]) {\n found = 1;\n break;\n }\n }\n if (!found) {\n result[index++] = li2[i];\n }\n }\n *resultSize = index;\n return result;\n}", + "test": "int main() {\n\n int resultSize;\n\n int *result;\n\n\n\n int li1[] = {10, 15, 20, 25, 30, 35, 40};\n\n int li2[] = {25, 40, 35};\n\n result = func0(li1, 7, li2, 3, &resultSize);\n\n qsort(result, resultSize, sizeof(int), compare);\n\n int expected1[] = {10, 15, 20, 30};\n\n assert(resultSize == 4 && memcmp(result, expected1, resultSize * sizeof(int)) == 0);\n\n free(result);\n\n\n\n int li3[] = {1, 2, 3, 4, 5};\n\n int li4[] = {6, 7, 1};\n\n result = func0(li3, 5, li4, 3, &resultSize);\n\n qsort(result, resultSize, sizeof(int), compare);\n\n int expected2[] = {2, 3, 4, 5, 6, 7};\n\n assert(resultSize == 6 && memcmp(result, expected2, resultSize * sizeof(int)) == 0);\n\n free(result);\n\n\n\n int li5[] = {1, 2, 3};\n\n int li6[] = {6, 7, 1};\n\n result = func0(li5, 3, li6, 3, &resultSize);\n\n qsort(result, resultSize, sizeof(int), compare);\n\n int expected3[] = {2, 3, 6, 7};\n\n assert(resultSize == 4 && memcmp(result, expected3, resultSize * sizeof(int)) == 0);\n\n free(result);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%r13\nmov %esi,%ebx\nmov %rdx,%r14\nmov %ecx,%ebp\nmov %r8,%r12\nlea (%rsi,%rcx,1),%edi\nmovslq %edi,%rdi\nshl $0x2,%rdi\ncallq 10f0 \ntest %ebx,%ebx\njle 123c \nmov %r13,%rdi\nlea -0x1(%rbx),%edx\nlea 0x4(%r13,%rdx,4),%r9\nmov %r14,%r10\nlea -0x1(%rbp),%edx\nlea 0x4(%r14,%rdx,4),%rsi\nmov $0x0,%r8d\njmp 12ad \nmov $0x0,%r8d\ntest %ebp,%ebp\njle 125e \nmov %r14,%rdi\nlea -0x1(%rbp),%edx\nlea 0x4(%r14,%rdx,4),%r9\nmov %r13,%r10\nlea -0x1(%rbx),%edx\nlea 0x4(%r13,%rdx,4),%rsi\njmp 1280 \nmov %r8d,(%r12)\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nmovslq %r8d,%rdx\nmov (%rdi),%ecx\nmov %ecx,(%rax,%rdx,4)\nlea 0x1(%r8),%r8d\nadd $0x4,%rdi\ncmp %r9,%rdi\nje 125e \ntest %ebx,%ebx\njle 126b \nmov (%rdi),%ecx\nmov %r10,%rdx\ncmp (%rdx),%ecx\nje 1277 \nadd $0x4,%rdx\ncmp %rsi,%rdx\njne 1289 \njmp 126b \nmovslq %r8d,%rdx\nmov (%rdi),%ecx\nmov %ecx,(%rax,%rdx,4)\nlea 0x1(%r8),%r8d\nadd $0x4,%rdi\ncmp %r9,%rdi\nje 1242 \ntest %ebp,%ebp\njle 1298 \nmov (%rdi),%ecx\nmov %r10,%rdx\ncmp (%rdx),%ecx\nje 12a4 \nadd $0x4,%rdx\ncmp %rsi,%rdx\njne 12b6 \njmp 1298 \n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbp, rdi\nmov ebx, esi\nmov r14, rdx\nmov r13d, ecx\nmov r12, r8\nlea edi, [rsi+rcx]\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov r8, rax\ntest ebx, ebx\njle short loc_1269\nmov rsi, rbp\nmovsxd rax, ebx\nlea r9, [rbp+rax*4+0]\nmovsxd rax, r13d\nlea rcx, [r14+rax*4]\nmov edi, 0\njmp short loc_1250\nloc_123B:\nmovsxd rax, edi\nmov edx, [rsi]\nmov [r8+rax*4], edx\nlea edi, [rdi+1]\nloc_1247:\nadd rsi, 4\ncmp rsi, r9\njz short loc_126E\nloc_1250:\ntest r13d, r13d\njle short loc_123B\nmov edx, [rsi]\nmov rax, r14\nloc_125A:\ncmp edx, [rax]\njz short loc_1247\nadd rax, 4\ncmp rax, rcx\njnz short loc_125A\njmp short loc_123B\nloc_1269:\nmov edi, 0\nloc_126E:\ntest r13d, r13d\njle short loc_12B4\nmov rsi, r14\nmovsxd r13, r13d\nlea r9, [r14+r13*4]\nmovsxd rax, ebx\nlea rcx, [rbp+rax*4+0]\njmp short loc_129C\nloc_1287:\nmovsxd rax, edi\nmov edx, [rsi]\nmov [r8+rax*4], edx\nlea edi, [rdi+1]\nloc_1293:\nadd rsi, 4\ncmp rsi, r9\njz short loc_12B4\nloc_129C:\ntest ebx, ebx\njle short loc_1287\nmov edx, [rsi]\nmov rax, rbp\nloc_12A5:\ncmp edx, [rax]\njz short loc_1293\nadd rax, 4\ncmp rax, rcx\njnz short loc_12A5\njmp short loc_1287\nloc_12B4:\nmov [r12], edi\nmov rax, r8\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(_DWORD *a1, int a2, _DWORD *a3, int a4, _DWORD *a5)\n{\n _DWORD *v10; // r8\n _DWORD *v11; // rsi\n int v12; // edi\n _DWORD *v13; // rax\n _DWORD *v14; // rsi\n _DWORD *v15; // rax\n\n v10 = malloc(4LL * (a2 + a4));\n if ( a2 <= 0 )\n {\n v12 = 0;\n }\n else\n {\n v11 = a1;\n v12 = 0;\n do\n {\n if ( a4 <= 0 )\n {\nLABEL_3:\n v10[v12++] = *v11;\n }\n else\n {\n v13 = a3;\n while ( *v11 != *v13 )\n {\n if ( ++v13 == &a3[a4] )\n goto LABEL_3;\n }\n }\n ++v11;\n }\n while ( v11 != &a1[a2] );\n }\n if ( a4 > 0 )\n {\n v14 = a3;\n do\n {\n if ( a2 <= 0 )\n {\nLABEL_13:\n v10[v12++] = *v14;\n }\n else\n {\n v15 = a1;\n while ( *v14 != *v15 )\n {\n if ( ++v15 == &a1[a2] )\n goto LABEL_13;\n }\n }\n ++v14;\n }\n while ( v14 != &a3[a4] );\n }\n *a5 = v12;\n return v10;\n}", + "ida_strip_asm": "sub_11F2:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbp, rdi\nmov ebx, esi\nmov r14, rdx\nmov r13d, ecx\nmov r12, r8\nlea edi, [rsi+rcx]\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov r8, rax\ntest ebx, ebx\njle short loc_1269\nmov rsi, rbp\nmovsxd rax, ebx\nlea r9, [rbp+rax*4+0]\nmovsxd rax, r13d\nlea rcx, [r14+rax*4]\nmov edi, 0\njmp short loc_1250\nloc_123B:\nmovsxd rax, edi\nmov edx, [rsi]\nmov [r8+rax*4], edx\nlea edi, [rdi+1]\nloc_1247:\nadd rsi, 4\ncmp rsi, r9\njz short loc_126E\nloc_1250:\ntest r13d, r13d\njle short loc_123B\nmov edx, [rsi]\nmov rax, r14\nloc_125A:\ncmp edx, [rax]\njz short loc_1247\nadd rax, 4\ncmp rax, rcx\njnz short loc_125A\njmp short loc_123B\nloc_1269:\nmov edi, 0\nloc_126E:\ntest r13d, r13d\njle short loc_12B4\nmov rsi, r14\nmovsxd r13, r13d\nlea r9, [r14+r13*4]\nmovsxd rax, ebx\nlea rcx, [rbp+rax*4+0]\njmp short loc_129C\nloc_1287:\nmovsxd rax, edi\nmov edx, [rsi]\nmov [r8+rax*4], edx\nlea edi, [rdi+1]\nloc_1293:\nadd rsi, 4\ncmp rsi, r9\njz short loc_12B4\nloc_129C:\ntest ebx, ebx\njle short loc_1287\nmov edx, [rsi]\nmov rax, rbp\nloc_12A5:\ncmp edx, [rax]\njz short loc_1293\nadd rax, 4\ncmp rax, rcx\njnz short loc_12A5\njmp short loc_1287\nloc_12B4:\nmov [r12], edi\nmov rax, r8\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11F2(_DWORD *a1, int a2, _DWORD *a3, int a4, _DWORD *a5)\n{\n _DWORD *v10; // r8\n _DWORD *v11; // rsi\n int v12; // edi\n _DWORD *v13; // rax\n _DWORD *v14; // rsi\n _DWORD *v15; // rax\n\n v10 = malloc(4LL * (a2 + a4));\n if ( a2 <= 0 )\n {\n v12 = 0;\n }\n else\n {\n v11 = a1;\n v12 = 0;\n do\n {\n if ( a4 <= 0 )\n {\nLABEL_3:\n v10[v12++] = *v11;\n }\n else\n {\n v13 = a3;\n while ( *v11 != *v13 )\n {\n if ( ++v13 == &a3[a4] )\n goto LABEL_3;\n }\n }\n ++v11;\n }\n while ( v11 != &a1[a2] );\n }\n if ( a4 > 0 )\n {\n v14 = a3;\n do\n {\n if ( a2 <= 0 )\n {\nLABEL_13:\n v10[v12++] = *v14;\n }\n else\n {\n v15 = a1;\n while ( *v14 != *v15 )\n {\n if ( ++v15 == &a1[a2] )\n goto LABEL_13;\n }\n }\n ++v14;\n }\n while ( v14 != &a3[a4] );\n }\n *a5 = v12;\n return v10;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11F2(uint32_t *a1, int a2, uint32_t *a3, int a4, uint32_t *a5) {\n uint32_t *v10;\n uint32_t *v11;\n int v12;\n uint32_t *v13;\n uint32_t *v14;\n uint32_t *v15;\n v10 = malloc(4LL * (a2 + a4));\n if (a2 <= 0) {\n v12 = 0;\n } else {\n v11 = a1;\n v12 = 0;\n do {\n if (a4 <= 0) {\n LABEL_3:\n v10[v12++] = *v11;\n } else {\n v13 = a3;\n while (*v11 != *v13) {\n if (++v13 == &a3[a4]) goto LABEL_3;\n }\n }\n ++v11;\n } while (v11 != &a1[a2]);\n }\n if (a4 > 0) {\n v14 = a3;\n do {\n if (a2 <= 0) {\n LABEL_13:\n v10[v12++] = *v14;\n } else {\n v15 = a1;\n while (*v14 != *v15) {\n if (++v15 == &a1[a2]) goto LABEL_13;\n }\n }\n ++v14;\n } while (v14 != &a3[a4]);\n }\n *a5 = v12;\n return v10;\n}", + "ida_pseudo_norm": "uint32_t *func0(uint32_t *a1, int a2, uint32_t *a3, int a4, uint32_t *a5) {\n uint32_t *v10;\n uint32_t *v11;\n int v12;\n uint32_t *v13;\n uint32_t *v14;\n uint32_t *v15;\n v10 = malloc(4LL * (a2 + a4));\n if (a2 <= 0) {\n v12 = 0;\n } else {\n v11 = a1;\n v12 = 0;\n do {\n if (a4 <= 0) {\n LABEL_3:\n v10[v12++] = *v11;\n } else {\n v13 = a3;\n while (*v11 != *v13) {\n if (++v13 == &a3[a4]) goto LABEL_3;\n }\n }\n ++v11;\n } while (v11 != &a1[a2]);\n }\n if (a4 > 0) {\n v14 = a3;\n do {\n if (a2 <= 0) {\n LABEL_13:\n v10[v12++] = *v14;\n } else {\n v15 = a1;\n while (*v14 != *v15) {\n if (++v15 == &a1[a2]) goto LABEL_13;\n }\n }\n ++v14;\n } while (v14 != &a3[a4]);\n }\n *a5 = v12;\n return v10;\n}" + }, + { + "index": 769, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\nint compare(const void *a, const void *b) {\n\n return (*(int*)a - *(int*)b);\n\n}\n\n\n\n", + "func": "int *func0(int *li1, int li1Size, int *li2, int li2Size, int *resultSize) {\n int *result = malloc((li1Size + li2Size) * sizeof(int));\n int i, j;\n int index = 0;\n int found;\n for (i = 0; i < li1Size; i++) {\n found = 0;\n for (j = 0; j < li2Size; j++) {\n if (li1[i] == li2[j]) {\n found = 1;\n break;\n }\n }\n if (!found) {\n result[index++] = li1[i];\n }\n }\n for (i = 0; i < li2Size; i++) {\n found = 0;\n for (j = 0; j < li1Size; j++) {\n if (li2[i] == li1[j]) {\n found = 1;\n break;\n }\n }\n if (!found) {\n result[index++] = li2[i];\n }\n }\n *resultSize = index;\n return result;\n}", + "test": "int main() {\n\n int resultSize;\n\n int *result;\n\n\n\n int li1[] = {10, 15, 20, 25, 30, 35, 40};\n\n int li2[] = {25, 40, 35};\n\n result = func0(li1, 7, li2, 3, &resultSize);\n\n qsort(result, resultSize, sizeof(int), compare);\n\n int expected1[] = {10, 15, 20, 30};\n\n assert(resultSize == 4 && memcmp(result, expected1, resultSize * sizeof(int)) == 0);\n\n free(result);\n\n\n\n int li3[] = {1, 2, 3, 4, 5};\n\n int li4[] = {6, 7, 1};\n\n result = func0(li3, 5, li4, 3, &resultSize);\n\n qsort(result, resultSize, sizeof(int), compare);\n\n int expected2[] = {2, 3, 4, 5, 6, 7};\n\n assert(resultSize == 6 && memcmp(result, expected2, resultSize * sizeof(int)) == 0);\n\n free(result);\n\n\n\n int li5[] = {1, 2, 3};\n\n int li6[] = {6, 7, 1};\n\n result = func0(li5, 3, li6, 3, &resultSize);\n\n qsort(result, resultSize, sizeof(int), compare);\n\n int expected3[] = {2, 3, 6, 7};\n\n assert(resultSize == 4 && memcmp(result, expected3, resultSize * sizeof(int)) == 0);\n\n free(result);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\nmov %ecx,%r14d\npush %r13\nmov %r8,%r13\npush %r12\nmov %esi,%r12d\npush %rbp\nmov %rdi,%rbp\nlea (%rsi,%rcx,1),%edi\npush %rbx\nmovslq %edi,%rdi\nmov %rdx,%rbx\nshl $0x2,%rdi\ncallq 10d0 \ntest %r12d,%r12d\njle 15d4 \nlea -0x1(%r14),%esi\nlea -0x1(%r12),%ecx\nmov %rbp,%rdx\nlea 0x4(%rbx,%rsi,4),%r10\nlea 0x4(%rbp,%rcx,4),%rcx\nxor %esi,%esi\nnopl 0x0(%rax,%rax,1)\nmov (%rdx),%r9d\nmov %rbx,%rdi\ntest %r14d,%r14d\njg 1539 \njmp 15a0 \nnopl (%rax)\nadd $0x4,%rdi\ncmp %rdi,%r10\nje 15a0 \ncmp %r9d,(%rdi)\njne 1530 \nadd $0x4,%rdx\ncmp %rcx,%rdx\njne 1520 \ntest %r14d,%r14d\njle 158e \nlea -0x1(%r14),%edx\nmov %rbx,%r9\nlea 0x4(%rbx,%rdx,4),%r8\nlea -0x1(%r12),%edx\nlea 0x4(%rbp,%rdx,4),%rdi\nnopw 0x0(%rax,%rax,1)\nmov (%r9),%ecx\nmov %rbp,%rdx\ntest %r12d,%r12d\njg 1581 \njmp 15c0 \nnopl (%rax)\nadd $0x4,%rdx\ncmp %rdi,%rdx\nje 15c0 \ncmp %ecx,(%rdx)\njne 1578 \nadd $0x4,%r9\ncmp %r9,%r8\njne 1568 \npop %rbx\npop %rbp\nmov %esi,0x0(%r13)\npop %r12\npop %r13\npop %r14\nretq\nnopl 0x0(%rax,%rax,1)\nmovslq %esi,%rdi\nadd $0x4,%rdx\nadd $0x1,%esi\nmov %r9d,(%rax,%rdi,4)\ncmp %rcx,%rdx\njne 1520 \njmp 1547 \nnopl 0x0(%rax)\nmovslq %esi,%rdx\nadd $0x4,%r9\nadd $0x1,%esi\nmov %ecx,(%rax,%rdx,4)\ncmp %r9,%r8\njne 1568 \njmp 158e \nxor %esi,%esi\njmpq 1547 \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\nmovsxd r14, ecx\npush r13\nmov r13, r8\npush r12\nmov r12d, esi\npush rbp\nmov rbp, rdi\nlea edi, [rsi+r14]\npush rbx\nmovsxd rdi, edi\nmov rbx, rdx\nshl rdi, 2; size\ncall _malloc\nmov r8, rax\ntest r12d, r12d\njle loc_1580\nmovsxd rax, r12d\nmov rsi, rbp\nxor r9d, r9d\nlea r10, [rbp+rax*4+0]\nmovsxd rax, r14d\nlea rcx, [rbx+rax*4]\nnop dword ptr [rax+00h]\nloc_14D0:\nmov edx, [rsi]\ntest r14d, r14d\njle short loc_1500\nloc_14D7:\nmov rax, rbx\njmp short loc_14E9\nloc_14E0:\nadd rax, 4\ncmp rcx, rax\njz short loc_1500\nloc_14E9:\ncmp [rax], edx\njnz short loc_14E0\nadd rsi, 4\ncmp r10, rsi\njz short loc_1516\nmov edx, [rsi]\njmp short loc_14D7\nloc_1500:\nadd rsi, 4\nmov [r8+r9*4], edx\nlea edi, [r9+1]\ncmp r10, rsi\njz short loc_1519\nmovsxd r9, edi\njmp short loc_14D0\nloc_1516:\nmov edi, r9d\nloc_1519:\ntest r14d, r14d\njle short loc_1570\nmovsxd rax, r12d\nmov rsi, rbx\nlea r10, [rbx+r14*4]\nlea rcx, [rbp+rax*4+0]\nnop dword ptr [rax]\nloc_1530:\nmov edx, [rsi]\nmovsxd r9, edi\ntest r12d, r12d\njle short loc_1560\nloc_153A:\nmov rax, rbp\njmp short loc_1549\nloc_1540:\nadd rax, 4\ncmp rcx, rax\njz short loc_1560\nloc_1549:\ncmp [rax], edx\njnz short loc_1540\nadd rsi, 4\ncmp r10, rsi\njz short loc_1570\nmov edx, [rsi]\njmp short loc_153A\nloc_1560:\nadd rsi, 4\nmov [r8+r9*4], edx\nadd edi, 1\ncmp r10, rsi\njnz short loc_1530\nloc_1570:\nmov [r13+0], edi\nmov rax, r8\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1580:\nxor edi, edi\njmp short loc_1519", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2, _DWORD *a3, int a4, _DWORD *a5)\n{\n __int64 v5; // r14\n _DWORD *v10; // r8\n int *v11; // rsi\n __int64 v12; // r9\n int *v13; // r10\n int v14; // edx\n _DWORD *v15; // rax\n int v16; // edi\n int *v17; // rsi\n int *v18; // r10\n int v19; // edx\n int *v20; // rax\n\n v5 = a4;\n v10 = malloc(4LL * (a2 + a4));\n if ( a2 <= 0 )\n {\n v16 = 0;\n }\n else\n {\n v11 = a1;\n v12 = 0LL;\n v13 = &a1[a2];\n while ( 1 )\n {\n v14 = *v11;\n if ( (int)v5 > 0 )\n break;\nLABEL_9:\n ++v11;\n v10[v12] = v14;\n v16 = v12 + 1;\n if ( v13 == v11 )\n goto LABEL_12;\n v12 = v16;\n }\n while ( 1 )\n {\n v15 = a3;\n while ( *v15 != v14 )\n {\n if ( &a3[(int)v5] == ++v15 )\n goto LABEL_9;\n }\n if ( v13 == ++v11 )\n break;\n v14 = *v11;\n }\n v16 = v12;\n }\nLABEL_12:\n if ( (int)v5 > 0 )\n {\n v17 = a3;\n v18 = &a3[v5];\n while ( 1 )\n {\n v19 = *v17;\n if ( a2 > 0 )\n break;\nLABEL_20:\n ++v17;\n v10[v16++] = v19;\n if ( v18 == v17 )\n goto LABEL_21;\n }\n while ( 1 )\n {\n v20 = a1;\n while ( *v20 != v19 )\n {\n if ( &a1[a2] == ++v20 )\n goto LABEL_20;\n }\n if ( v18 == ++v17 )\n break;\n v19 = *v17;\n }\n }\nLABEL_21:\n *a5 = v16;\n return v10;\n}", + "ida_strip_asm": "sub_1480:\nendbr64\npush r14\nmovsxd r14, ecx\npush r13\nmov r13, r8\npush r12\nmov r12d, esi\npush rbp\nmov rbp, rdi\nlea edi, [rsi+r14]\npush rbx\nmovsxd rdi, edi\nmov rbx, rdx\nshl rdi, 2; size\ncall _malloc\nmov r8, rax\ntest r12d, r12d\njle loc_1580\nmovsxd rax, r12d\nmov rsi, rbp\nxor r9d, r9d\nlea r10, [rbp+rax*4+0]\nmovsxd rax, r14d\nlea rcx, [rbx+rax*4]\nnop dword ptr [rax+00h]\nloc_14D0:\nmov edx, [rsi]\ntest r14d, r14d\njle short loc_1500\nloc_14D7:\nmov rax, rbx\njmp short loc_14E9\nloc_14E0:\nadd rax, 4\ncmp rcx, rax\njz short loc_1500\nloc_14E9:\ncmp [rax], edx\njnz short loc_14E0\nadd rsi, 4\ncmp r10, rsi\njz short loc_1516\nmov edx, [rsi]\njmp short loc_14D7\nloc_1500:\nadd rsi, 4\nmov [r8+r9*4], edx\nlea edi, [r9+1]\ncmp r10, rsi\njz short loc_1519\nmovsxd r9, edi\njmp short loc_14D0\nloc_1516:\nmov edi, r9d\nloc_1519:\ntest r14d, r14d\njle short loc_1570\nmovsxd rax, r12d\nmov rsi, rbx\nlea r10, [rbx+r14*4]\nlea rcx, [rbp+rax*4+0]\nnop dword ptr [rax]\nloc_1530:\nmov edx, [rsi]\nmovsxd r9, edi\ntest r12d, r12d\njle short loc_1560\nloc_153A:\nmov rax, rbp\njmp short loc_1549\nloc_1540:\nadd rax, 4\ncmp rcx, rax\njz short loc_1560\nloc_1549:\ncmp [rax], edx\njnz short loc_1540\nadd rsi, 4\ncmp r10, rsi\njz short loc_1570\nmov edx, [rsi]\njmp short loc_153A\nloc_1560:\nadd rsi, 4\nmov [r8+r9*4], edx\nadd edi, 1\ncmp r10, rsi\njnz short loc_1530\nloc_1570:\nmov [r13+0], edi\nmov rax, r8\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1580:\nxor edi, edi\njmp short loc_1519", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1480(int *a1, int a2, _DWORD *a3, int a4, _DWORD *a5)\n{\n __int64 v5; // r14\n _DWORD *v10; // r8\n int *v11; // rsi\n __int64 v12; // r9\n int *v13; // r10\n int v14; // edx\n _DWORD *v15; // rax\n int v16; // edi\n int *v17; // rsi\n int *v18; // r10\n int v19; // edx\n int *v20; // rax\n\n v5 = a4;\n v10 = malloc(4LL * (a2 + a4));\n if ( a2 <= 0 )\n {\n v16 = 0;\n }\n else\n {\n v11 = a1;\n v12 = 0LL;\n v13 = &a1[a2];\n while ( 1 )\n {\n v14 = *v11;\n if ( (int)v5 > 0 )\n break;\nLABEL_9:\n ++v11;\n v10[v12] = v14;\n v16 = v12 + 1;\n if ( v13 == v11 )\n goto LABEL_12;\n v12 = v16;\n }\n while ( 1 )\n {\n v15 = a3;\n while ( *v15 != v14 )\n {\n if ( &a3[(int)v5] == ++v15 )\n goto LABEL_9;\n }\n if ( v13 == ++v11 )\n break;\n v14 = *v11;\n }\n v16 = v12;\n }\nLABEL_12:\n if ( (int)v5 > 0 )\n {\n v17 = a3;\n v18 = &a3[v5];\n while ( 1 )\n {\n v19 = *v17;\n if ( a2 > 0 )\n break;\nLABEL_20:\n ++v17;\n v10[v16++] = v19;\n if ( v18 == v17 )\n goto LABEL_21;\n }\n while ( 1 )\n {\n v20 = a1;\n while ( *v20 != v19 )\n {\n if ( &a1[a2] == ++v20 )\n goto LABEL_20;\n }\n if ( v18 == ++v17 )\n break;\n v19 = *v17;\n }\n }\nLABEL_21:\n *a5 = v16;\n return v10;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1480(int *a1, int a2, uint32_t *a3, int a4, uint32_t *a5) {\n long long v5;\n uint32_t *v10;\n int *v11;\n long long v12;\n int *v13;\n int v14;\n uint32_t *v15;\n int v16;\n int *v17;\n int *v18;\n int v19;\n int *v20;\n v5 = a4;\n v10 = malloc(4LL * (a2 + a4));\n if (a2 <= 0) {\n v16 = 0;\n } else {\n v11 = a1;\n v12 = 0LL;\n v13 = &a1[a2];\n while (1) {\n v14 = *v11;\n if ((int)v5 > 0) break;\n LABEL_9:\n ++v11;\n v10[v12] = v14;\n v16 = v12 + 1;\n if (v13 == v11) goto LABEL_12;\n v12 = v16;\n }\n while (1) {\n v15 = a3;\n while (*v15 != v14) {\n if (&a3[(int)v5] == ++v15) goto LABEL_9;\n }\n if (v13 == ++v11) break;\n v14 = *v11;\n }\n v16 = v12;\n }\nLABEL_12:\n if ((int)v5 > 0) {\n v17 = a3;\n v18 = &a3[v5];\n while (1) {\n v19 = *v17;\n if (a2 > 0) break;\n LABEL_20:\n ++v17;\n v10[v16++] = v19;\n if (v18 == v17) goto LABEL_21;\n }\n while (1) {\n v20 = a1;\n while (*v20 != v19) {\n if (&a1[a2] == ++v20) goto LABEL_20;\n }\n if (v18 == ++v17) break;\n v19 = *v17;\n }\n }\nLABEL_21:\n *a5 = v16;\n return v10;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2, uint32_t *a3, int a4, uint32_t *a5) {\n long long v5;\n uint32_t *v10;\n int *v11;\n long long v12;\n int *v13;\n int v14;\n uint32_t *v15;\n int v16;\n int *v17;\n int *v18;\n int v19;\n int *v20;\n v5 = a4;\n v10 = malloc(4LL * (a2 + a4));\n if (a2 <= 0) {\n v16 = 0;\n } else {\n v11 = a1;\n v12 = 0LL;\n v13 = &a1[a2];\n while (1) {\n v14 = *v11;\n if ((int)v5 > 0) break;\n LABEL_9:\n ++v11;\n v10[v12] = v14;\n v16 = v12 + 1;\n if (v13 == v11) goto LABEL_12;\n v12 = v16;\n }\n while (1) {\n v15 = a3;\n while (*v15 != v14) {\n if (&a3[(int)v5] == ++v15) goto LABEL_9;\n }\n if (v13 == ++v11) break;\n v14 = *v11;\n }\n v16 = v12;\n }\nLABEL_12:\n if ((int)v5 > 0) {\n v17 = a3;\n v18 = &a3[v5];\n while (1) {\n v19 = *v17;\n if (a2 > 0) break;\n LABEL_20:\n ++v17;\n v10[v16++] = v19;\n if (v18 == v17) goto LABEL_21;\n }\n while (1) {\n v20 = a1;\n while (*v20 != v19) {\n if (&a1[a2] == ++v20) goto LABEL_20;\n }\n if (v18 == ++v17) break;\n v19 = *v17;\n }\n }\nLABEL_21:\n *a5 = v16;\n return v10;\n}" + }, + { + "index": 769, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\nint compare(const void *a, const void *b) {\n\n return (*(int*)a - *(int*)b);\n\n}\n\n\n\n", + "func": "int *func0(int *li1, int li1Size, int *li2, int li2Size, int *resultSize) {\n int *result = malloc((li1Size + li2Size) * sizeof(int));\n int i, j;\n int index = 0;\n int found;\n for (i = 0; i < li1Size; i++) {\n found = 0;\n for (j = 0; j < li2Size; j++) {\n if (li1[i] == li2[j]) {\n found = 1;\n break;\n }\n }\n if (!found) {\n result[index++] = li1[i];\n }\n }\n for (i = 0; i < li2Size; i++) {\n found = 0;\n for (j = 0; j < li1Size; j++) {\n if (li2[i] == li1[j]) {\n found = 1;\n break;\n }\n }\n if (!found) {\n result[index++] = li2[i];\n }\n }\n *resultSize = index;\n return result;\n}", + "test": "int main() {\n\n int resultSize;\n\n int *result;\n\n\n\n int li1[] = {10, 15, 20, 25, 30, 35, 40};\n\n int li2[] = {25, 40, 35};\n\n result = func0(li1, 7, li2, 3, &resultSize);\n\n qsort(result, resultSize, sizeof(int), compare);\n\n int expected1[] = {10, 15, 20, 30};\n\n assert(resultSize == 4 && memcmp(result, expected1, resultSize * sizeof(int)) == 0);\n\n free(result);\n\n\n\n int li3[] = {1, 2, 3, 4, 5};\n\n int li4[] = {6, 7, 1};\n\n result = func0(li3, 5, li4, 3, &resultSize);\n\n qsort(result, resultSize, sizeof(int), compare);\n\n int expected2[] = {2, 3, 4, 5, 6, 7};\n\n assert(resultSize == 6 && memcmp(result, expected2, resultSize * sizeof(int)) == 0);\n\n free(result);\n\n\n\n int li5[] = {1, 2, 3};\n\n int li6[] = {6, 7, 1};\n\n result = func0(li5, 3, li6, 3, &resultSize);\n\n qsort(result, resultSize, sizeof(int), compare);\n\n int expected3[] = {2, 3, 6, 7};\n\n assert(resultSize == 4 && memcmp(result, expected3, resultSize * sizeof(int)) == 0);\n\n free(result);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\nmov %ecx,%r14d\npush %r13\nmov %r8,%r13\npush %r12\nmov %esi,%r12d\npush %rbp\nmov %rdi,%rbp\nlea (%rsi,%rcx,1),%edi\npush %rbx\nmovslq %edi,%rdi\nmov %rdx,%rbx\nshl $0x2,%rdi\ncallq 10d0 \ntest %r12d,%r12d\njle 1594 \nlea -0x1(%r14),%esi\nlea -0x1(%r12),%ecx\nmov %rbp,%rdx\nlea 0x4(%rbx,%rsi,4),%r10\nlea 0x4(%rbp,%rcx,4),%rcx\nxor %esi,%esi\nnopl 0x0(%rax,%rax,1)\nmov (%rdx),%r9d\nmov %rbx,%rdi\ntest %r14d,%r14d\njg 14f9 \njmp 1560 \nnopl (%rax)\nadd $0x4,%rdi\ncmp %rdi,%r10\nje 1560 \ncmp %r9d,(%rdi)\njne 14f0 \nadd $0x4,%rdx\ncmp %rcx,%rdx\njne 14e0 \ntest %r14d,%r14d\njle 154e \nlea -0x1(%r14),%edx\nmov %rbx,%r9\nlea 0x4(%rbx,%rdx,4),%r8\nlea -0x1(%r12),%edx\nlea 0x4(%rbp,%rdx,4),%rdi\nnopw 0x0(%rax,%rax,1)\nmov (%r9),%ecx\nmov %rbp,%rdx\ntest %r12d,%r12d\njg 1541 \njmp 1580 \nnopl (%rax)\nadd $0x4,%rdx\ncmp %rdx,%rdi\nje 1580 \ncmp %ecx,(%rdx)\njne 1538 \nadd $0x4,%r9\ncmp %r8,%r9\njne 1528 \npop %rbx\npop %rbp\nmov %esi,0x0(%r13)\npop %r12\npop %r13\npop %r14\nretq\nnopl 0x0(%rax,%rax,1)\nmovslq %esi,%rdi\nadd $0x4,%rdx\nadd $0x1,%esi\nmov %r9d,(%rax,%rdi,4)\ncmp %rcx,%rdx\njne 14e0 \njmp 1507 \nnopl 0x0(%rax)\nmovslq %esi,%rdx\nadd $0x4,%r9\nadd $0x1,%esi\nmov %ecx,(%rax,%rdx,4)\ncmp %r8,%r9\njne 1528 \njmp 154e \nxor %esi,%esi\njmpq 1507 \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\nmovsxd r14, ecx\npush r13\nmov r13, r8\npush r12\nmov r12d, esi\npush rbp\nmov rbp, rdi\nlea edi, [rsi+r14]\npush rbx\nmovsxd rdi, edi\nmov rbx, rdx\nshl rdi, 2; size\ncall _malloc\nmov r8, rax\ntest r12d, r12d\njle loc_1580\nmovsxd rax, r12d\nmov rsi, rbp\nxor r9d, r9d\nlea r10, [rbp+rax*4+0]\nmovsxd rax, r14d\nlea rcx, [rbx+rax*4]\nnop dword ptr [rax+00h]\nloc_14D0:\nmov edx, [rsi]\ntest r14d, r14d\njle short loc_1500\nloc_14D7:\nmov rax, rbx\njmp short loc_14E9\nloc_14E0:\nadd rax, 4\ncmp rax, rcx\njz short loc_1500\nloc_14E9:\ncmp [rax], edx\njnz short loc_14E0\nadd rsi, 4\ncmp rsi, r10\njz short loc_1516\nmov edx, [rsi]\njmp short loc_14D7\nloc_1500:\nadd rsi, 4\nmov [r8+r9*4], edx\nlea edi, [r9+1]\ncmp rsi, r10\njz short loc_1519\nmovsxd r9, edi\njmp short loc_14D0\nloc_1516:\nmov edi, r9d\nloc_1519:\ntest r14d, r14d\njle short loc_1570\nmovsxd rax, r12d\nmov rsi, rbx\nlea r10, [rbx+r14*4]\nlea rcx, [rbp+rax*4+0]\nnop dword ptr [rax]\nloc_1530:\nmov edx, [rsi]\nmovsxd r9, edi\ntest r12d, r12d\njle short loc_1560\nloc_153A:\nmov rax, rbp\njmp short loc_1549\nloc_1540:\nadd rax, 4\ncmp rcx, rax\njz short loc_1560\nloc_1549:\ncmp edx, [rax]\njnz short loc_1540\nadd rsi, 4\ncmp rsi, r10\njz short loc_1570\nmov edx, [rsi]\njmp short loc_153A\nloc_1560:\nadd rsi, 4\nmov [r8+r9*4], edx\nadd edi, 1\ncmp rsi, r10\njnz short loc_1530\nloc_1570:\nmov [r13+0], edi\nmov rax, r8\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1580:\nxor edi, edi\njmp short loc_1519", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2, _DWORD *a3, int a4, _DWORD *a5)\n{\n __int64 v5; // r14\n _DWORD *v10; // r8\n int *v11; // rsi\n __int64 v12; // r9\n int *v13; // r10\n int v14; // edx\n _DWORD *v15; // rax\n int v16; // edi\n int *v17; // rsi\n int *v18; // r10\n int v19; // edx\n int *v20; // rax\n\n v5 = a4;\n v10 = malloc(4LL * (a2 + a4));\n if ( a2 <= 0 )\n {\n v16 = 0;\n }\n else\n {\n v11 = a1;\n v12 = 0LL;\n v13 = &a1[a2];\n while ( 1 )\n {\n v14 = *v11;\n if ( (int)v5 > 0 )\n break;\nLABEL_9:\n ++v11;\n v10[v12] = v14;\n v16 = v12 + 1;\n if ( v11 == v13 )\n goto LABEL_12;\n v12 = v16;\n }\n while ( 1 )\n {\n v15 = a3;\n while ( *v15 != v14 )\n {\n if ( ++v15 == &a3[(int)v5] )\n goto LABEL_9;\n }\n if ( ++v11 == v13 )\n break;\n v14 = *v11;\n }\n v16 = v12;\n }\nLABEL_12:\n if ( (int)v5 > 0 )\n {\n v17 = a3;\n v18 = &a3[v5];\n while ( 1 )\n {\n v19 = *v17;\n if ( a2 > 0 )\n break;\nLABEL_20:\n ++v17;\n v10[v16++] = v19;\n if ( v17 == v18 )\n goto LABEL_21;\n }\n while ( 1 )\n {\n v20 = a1;\n while ( v19 != *v20 )\n {\n if ( &a1[a2] == ++v20 )\n goto LABEL_20;\n }\n if ( ++v17 == v18 )\n break;\n v19 = *v17;\n }\n }\nLABEL_21:\n *a5 = v16;\n return v10;\n}", + "ida_strip_asm": "sub_1480:\nendbr64\npush r14\nmovsxd r14, ecx\npush r13\nmov r13, r8\npush r12\nmov r12d, esi\npush rbp\nmov rbp, rdi\nlea edi, [rsi+r14]\npush rbx\nmovsxd rdi, edi\nmov rbx, rdx\nshl rdi, 2; size\ncall _malloc\nmov r8, rax\ntest r12d, r12d\njle loc_1580\nmovsxd rax, r12d\nmov rsi, rbp\nxor r9d, r9d\nlea r10, [rbp+rax*4+0]\nmovsxd rax, r14d\nlea rcx, [rbx+rax*4]\nnop dword ptr [rax+00h]\nloc_14D0:\nmov edx, [rsi]\ntest r14d, r14d\njle short loc_1500\nloc_14D7:\nmov rax, rbx\njmp short loc_14E9\nloc_14E0:\nadd rax, 4\ncmp rax, rcx\njz short loc_1500\nloc_14E9:\ncmp [rax], edx\njnz short loc_14E0\nadd rsi, 4\ncmp rsi, r10\njz short loc_1516\nmov edx, [rsi]\njmp short loc_14D7\nloc_1500:\nadd rsi, 4\nmov [r8+r9*4], edx\nlea edi, [r9+1]\ncmp rsi, r10\njz short loc_1519\nmovsxd r9, edi\njmp short loc_14D0\nloc_1516:\nmov edi, r9d\nloc_1519:\ntest r14d, r14d\njle short loc_1570\nmovsxd rax, r12d\nmov rsi, rbx\nlea r10, [rbx+r14*4]\nlea rcx, [rbp+rax*4+0]\nnop dword ptr [rax]\nloc_1530:\nmov edx, [rsi]\nmovsxd r9, edi\ntest r12d, r12d\njle short loc_1560\nloc_153A:\nmov rax, rbp\njmp short loc_1549\nloc_1540:\nadd rax, 4\ncmp rcx, rax\njz short loc_1560\nloc_1549:\ncmp edx, [rax]\njnz short loc_1540\nadd rsi, 4\ncmp rsi, r10\njz short loc_1570\nmov edx, [rsi]\njmp short loc_153A\nloc_1560:\nadd rsi, 4\nmov [r8+r9*4], edx\nadd edi, 1\ncmp rsi, r10\njnz short loc_1530\nloc_1570:\nmov [r13+0], edi\nmov rax, r8\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1580:\nxor edi, edi\njmp short loc_1519", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1480(int *a1, int a2, _DWORD *a3, int a4, _DWORD *a5)\n{\n __int64 v5; // r14\n _DWORD *v10; // r8\n int *v11; // rsi\n __int64 v12; // r9\n int *v13; // r10\n int v14; // edx\n _DWORD *v15; // rax\n int v16; // edi\n int *v17; // rsi\n int *v18; // r10\n int v19; // edx\n int *v20; // rax\n\n v5 = a4;\n v10 = malloc(4LL * (a2 + a4));\n if ( a2 <= 0 )\n {\n v16 = 0;\n }\n else\n {\n v11 = a1;\n v12 = 0LL;\n v13 = &a1[a2];\n while ( 1 )\n {\n v14 = *v11;\n if ( (int)v5 > 0 )\n break;\nLABEL_9:\n ++v11;\n v10[v12] = v14;\n v16 = v12 + 1;\n if ( v11 == v13 )\n goto LABEL_12;\n v12 = v16;\n }\n while ( 1 )\n {\n v15 = a3;\n while ( *v15 != v14 )\n {\n if ( ++v15 == &a3[(int)v5] )\n goto LABEL_9;\n }\n if ( ++v11 == v13 )\n break;\n v14 = *v11;\n }\n v16 = v12;\n }\nLABEL_12:\n if ( (int)v5 > 0 )\n {\n v17 = a3;\n v18 = &a3[v5];\n while ( 1 )\n {\n v19 = *v17;\n if ( a2 > 0 )\n break;\nLABEL_20:\n ++v17;\n v10[v16++] = v19;\n if ( v17 == v18 )\n goto LABEL_21;\n }\n while ( 1 )\n {\n v20 = a1;\n while ( v19 != *v20 )\n {\n if ( &a1[a2] == ++v20 )\n goto LABEL_20;\n }\n if ( ++v17 == v18 )\n break;\n v19 = *v17;\n }\n }\nLABEL_21:\n *a5 = v16;\n return v10;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1480(int *a1, int a2, uint32_t *a3, int a4, uint32_t *a5) {\n long long v5;\n uint32_t *v10;\n int *v11;\n long long v12;\n int *v13;\n int v14;\n uint32_t *v15;\n int v16;\n int *v17;\n int *v18;\n int v19;\n int *v20;\n v5 = a4;\n v10 = malloc(4LL * (a2 + a4));\n if (a2 <= 0) {\n v16 = 0;\n } else {\n v11 = a1;\n v12 = 0LL;\n v13 = &a1[a2];\n while (1) {\n v14 = *v11;\n if ((int)v5 > 0) break;\n LABEL_9:\n ++v11;\n v10[v12] = v14;\n v16 = v12 + 1;\n if (v11 == v13) goto LABEL_12;\n v12 = v16;\n }\n while (1) {\n v15 = a3;\n while (*v15 != v14) {\n if (++v15 == &a3[(int)v5]) goto LABEL_9;\n }\n if (++v11 == v13) break;\n v14 = *v11;\n }\n v16 = v12;\n }\nLABEL_12:\n if ((int)v5 > 0) {\n v17 = a3;\n v18 = &a3[v5];\n while (1) {\n v19 = *v17;\n if (a2 > 0) break;\n LABEL_20:\n ++v17;\n v10[v16++] = v19;\n if (v17 == v18) goto LABEL_21;\n }\n while (1) {\n v20 = a1;\n while (v19 != *v20) {\n if (&a1[a2] == ++v20) goto LABEL_20;\n }\n if (++v17 == v18) break;\n v19 = *v17;\n }\n }\nLABEL_21:\n *a5 = v16;\n return v10;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2, uint32_t *a3, int a4, uint32_t *a5) {\n long long v5;\n uint32_t *v10;\n int *v11;\n long long v12;\n int *v13;\n int v14;\n uint32_t *v15;\n int v16;\n int *v17;\n int *v18;\n int v19;\n int *v20;\n v5 = a4;\n v10 = malloc(4LL * (a2 + a4));\n if (a2 <= 0) {\n v16 = 0;\n } else {\n v11 = a1;\n v12 = 0LL;\n v13 = &a1[a2];\n while (1) {\n v14 = *v11;\n if ((int)v5 > 0) break;\n LABEL_9:\n ++v11;\n v10[v12] = v14;\n v16 = v12 + 1;\n if (v11 == v13) goto LABEL_12;\n v12 = v16;\n }\n while (1) {\n v15 = a3;\n while (*v15 != v14) {\n if (++v15 == &a3[(int)v5]) goto LABEL_9;\n }\n if (++v11 == v13) break;\n v14 = *v11;\n }\n v16 = v12;\n }\nLABEL_12:\n if ((int)v5 > 0) {\n v17 = a3;\n v18 = &a3[v5];\n while (1) {\n v19 = *v17;\n if (a2 > 0) break;\n LABEL_20:\n ++v17;\n v10[v16++] = v19;\n if (v17 == v18) goto LABEL_21;\n }\n while (1) {\n v20 = a1;\n while (v19 != *v20) {\n if (&a1[a2] == ++v20) goto LABEL_20;\n }\n if (++v17 == v18) break;\n v19 = *v17;\n }\n }\nLABEL_21:\n *a5 = v16;\n return v10;\n}" + }, + { + "index": 770, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int n) {\n int j = 0;\n int sm = 0;\n for (int i = 1; i <= n; ++i) {\n j = (2 * i - 1);\n sm += (j * j * j * j);\n }\n return sm;\n}", + "test": "int main() {\n\n assert(func0(2) == 82);\n\n assert(func0(3) == 707);\n\n assert(func0(4) == 3108);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmovl $0x0,-0x4(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x1,-0x8(%rbp)\njmp 118b \nmov -0x8(%rbp),%eax\nadd %eax,%eax\nsub $0x1,%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nimul %eax,%eax\nimul -0x4(%rbp),%eax\nimul -0x4(%rbp),%eax\nadd %eax,-0xc(%rbp)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x14(%rbp),%eax\njle 116b \nmov -0xc(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_4], 0\nmov [rbp+var_C], 0\nmov [rbp+var_8], 1\njmp short loc_118B\nloc_116B:\nmov eax, [rbp+var_8]\nadd eax, eax\nsub eax, 1\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\nimul eax, eax\nimul eax, [rbp+var_4]\nimul eax, [rbp+var_4]\nadd [rbp+var_C], eax\nadd [rbp+var_8], 1\nloc_118B:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_14]\njle short loc_116B\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v2; // [rsp+8h] [rbp-Ch]\n int i; // [rsp+Ch] [rbp-8h]\n\n v2 = 0;\n for ( i = 1; i <= a1; ++i )\n v2 += (2 * i - 1) * (2 * i - 1) * (2 * i - 1) * (2 * i - 1);\n return v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_4], 0\nmov [rbp+var_C], 0\nmov [rbp+var_8], 1\njmp short loc_118B\nloc_116B:\nmov eax, [rbp+var_8]\nadd eax, eax\nsub eax, 1\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\nimul eax, eax\nimul eax, [rbp+var_4]\nimul eax, [rbp+var_4]\nadd [rbp+var_C], eax\nadd [rbp+var_8], 1\nloc_118B:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_14]\njle short loc_116B\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n unsigned int v2; // [rsp+8h] [rbp-Ch]\n int i; // [rsp+Ch] [rbp-8h]\n\n v2 = 0;\n for ( i = 1; i <= a1; ++i )\n v2 += (2 * i - 1) * (2 * i - 1) * (2 * i - 1) * (2 * i - 1);\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n unsigned int v2;\n int i;\n v2 = 0;\n for (i = 1; i <= a1; ++i)\n v2 += (2 * i - 1) * (2 * i - 1) * (2 * i - 1) * (2 * i - 1);\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v2;\n int i;\n v2 = 0;\n for (i = 1; i <= a1; ++i)\n v2 += (2 * i - 1) * (2 * i - 1) * (2 * i - 1) * (2 * i - 1);\n return v2;\n}" + }, + { + "index": 770, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int n) {\n int j = 0;\n int sm = 0;\n for (int i = 1; i <= n; ++i) {\n j = (2 * i - 1);\n sm += (j * j * j * j);\n }\n return sm;\n}", + "test": "int main() {\n\n assert(func0(2) == 82);\n\n assert(func0(3) == 707);\n\n assert(func0(4) == 3108);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\njle 1173 \nlea 0x1(%rdi,%rdi,1),%esi\nmov $0x1,%eax\nmov $0x0,%ecx\nmov %eax,%edx\nimul %eax,%edx\nimul %edx,%edx\nadd %edx,%ecx\nadd $0x2,%eax\ncmp %esi,%eax\njne 115f \nmov %ecx,%eax\nretq\nmov $0x0,%ecx\njmp 1170 \n", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njle short loc_1173\nlea esi, [rdi+rdi+1]\nmov eax, 1\nmov ecx, 0\nloc_115F:\nmov edx, eax\nimul edx, eax\nimul edx, edx\nadd ecx, edx\nadd eax, 2\ncmp eax, esi\njnz short loc_115F\nloc_1170:\nmov eax, ecx\nretn\nloc_1173:\nmov ecx, 0\njmp short loc_1170", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // eax\n unsigned int v2; // ecx\n\n if ( a1 <= 0 )\n {\n return 0;\n }\n else\n {\n v1 = 1;\n v2 = 0;\n do\n {\n v2 += v1 * v1 * v1 * v1;\n v1 += 2;\n }\n while ( v1 != 2 * a1 + 1 );\n }\n return v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ntest edi, edi\njle short loc_1173\nlea esi, [rdi+rdi+1]\nmov eax, 1\nmov ecx, 0\nloc_115F:\nmov edx, eax\nimul edx, eax\nimul edx, edx\nadd ecx, edx\nadd eax, 2\ncmp eax, esi\njnz short loc_115F\nloc_1170:\nmov eax, ecx\nretn\nloc_1173:\nmov ecx, 0\njmp short loc_1170", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v1; // eax\n unsigned int v2; // ecx\n\n if ( a1 <= 0 )\n {\n return 0;\n }\n else\n {\n v1 = 1;\n v2 = 0;\n do\n {\n v2 += v1 * v1 * v1 * v1;\n v1 += 2;\n }\n while ( v1 != 2 * a1 + 1 );\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v1;\n unsigned int v2;\n if (a1 <= 0) {\n return 0;\n } else {\n v1 = 1;\n v2 = 0;\n do {\n v2 += v1 * v1 * v1 * v1;\n v1 += 2;\n } while (v1 != 2 * a1 + 1);\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n unsigned int v2;\n if (a1 <= 0) {\n return 0;\n } else {\n v1 = 1;\n v2 = 0;\n do {\n v2 += v1 * v1 * v1 * v1;\n v1 += 2;\n } while (v1 != 2 * a1 + 1);\n }\n return v2;\n}" + }, + { + "index": 771, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char *exp) {\n int len = strlen(exp);\n if (len % 2 != 0) {\n return false;\n }\n char stack[100];\n int top = -1;\n for (int i = 0; i < len; i++) {\n char ch = exp[i];\n if (ch == '(' || ch == '{' || ch == '[') {\n stack[++top] = ch;\n } else if (ch == ')' || ch == '}' || ch == ']') {\n if (top == -1) {\n return false;\n }\n char last_open = stack[top--];\n if ((last_open == '(' && ch != ')') ||\n (last_open == '{' && ch != '}') ||\n (last_open == '[' && ch != ']')) {\n return false;\n }\n }\n }\n return top == -1;\n}", + "test": "int main() {\n\n assert(func0(\"{()}[{}]\") == true);\n\n assert(func0(\"{()}[{]\") == false);\n\n assert(func0(\"{()}[{}][]({})\") == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x90,%rsp\nmov %rdi,-0x88(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmov -0x88(%rbp),%rax\nmov %rax,%rdi\ncallq 1070 \nmov %eax,-0x74(%rbp)\nmov -0x74(%rbp),%eax\nand $0x1,%eax\ntest %eax,%eax\nje 11d4 \nmov $0x0,%eax\njmpq 1296 \nmovl $0xffffffff,-0x7c(%rbp)\nmovl $0x0,-0x78(%rbp)\njmpq 1283 \nmov -0x78(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x88(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmov %al,-0x7e(%rbp)\ncmpb $0x28,-0x7e(%rbp)\nje 120f \ncmpb $0x7b,-0x7e(%rbp)\nje 120f \ncmpb $0x5b,-0x7e(%rbp)\njne 1222 \naddl $0x1,-0x7c(%rbp)\nmov -0x7c(%rbp),%eax\ncltq\nmovzbl -0x7e(%rbp),%edx\nmov %dl,-0x70(%rbp,%rax,1)\njmp 127f \ncmpb $0x29,-0x7e(%rbp)\nje 1234 \ncmpb $0x7d,-0x7e(%rbp)\nje 1234 \ncmpb $0x5d,-0x7e(%rbp)\njne 127f \ncmpl $0xffffffff,-0x7c(%rbp)\njne 1241 \nmov $0x0,%eax\njmp 1296 \nmov -0x7c(%rbp),%eax\nlea -0x1(%rax),%edx\nmov %edx,-0x7c(%rbp)\ncltq\nmovzbl -0x70(%rbp,%rax,1),%eax\nmov %al,-0x7d(%rbp)\ncmpb $0x28,-0x7d(%rbp)\njne 1260 \ncmpb $0x29,-0x7e(%rbp)\njne 1278 \ncmpb $0x7b,-0x7d(%rbp)\njne 126c \ncmpb $0x7d,-0x7e(%rbp)\njne 1278 \ncmpb $0x5b,-0x7d(%rbp)\njne 127f \ncmpb $0x5d,-0x7e(%rbp)\nje 127f \nmov $0x0,%eax\njmp 1296 \naddl $0x1,-0x78(%rbp)\nmov -0x78(%rbp),%eax\ncmp -0x74(%rbp),%eax\njl 11e7 \ncmpl $0xffffffff,-0x7c(%rbp)\nsete %al\nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 12aa \ncallq 1080 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 90h\nmov [rbp+s], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_74], eax\nmov eax, [rbp+var_74]\nand eax, 1\ntest eax, eax\njz short loc_11D4\nmov eax, 0\njmp loc_1296\nloc_11D4:\nmov [rbp+var_7C], 0FFFFFFFFh\nmov [rbp+var_78], 0\njmp loc_1283\nloc_11E7:\nmov eax, [rbp+var_78]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_7E], al\ncmp [rbp+var_7E], 28h ; '('\njz short loc_120F\ncmp [rbp+var_7E], 7Bh ; '{'\njz short loc_120F\ncmp [rbp+var_7E], 5Bh ; '['\njnz short loc_1222\nloc_120F:\nadd [rbp+var_7C], 1\nmov eax, [rbp+var_7C]\ncdqe\nmovzx edx, [rbp+var_7E]\nmov [rbp+rax+var_70], dl\njmp short loc_127F\nloc_1222:\ncmp [rbp+var_7E], 29h ; ')'\njz short loc_1234\ncmp [rbp+var_7E], 7Dh ; '}'\njz short loc_1234\ncmp [rbp+var_7E], 5Dh ; ']'\njnz short loc_127F\nloc_1234:\ncmp [rbp+var_7C], 0FFFFFFFFh\njnz short loc_1241\nmov eax, 0\njmp short loc_1296\nloc_1241:\nmov eax, [rbp+var_7C]\nlea edx, [rax-1]\nmov [rbp+var_7C], edx\ncdqe\nmovzx eax, [rbp+rax+var_70]\nmov [rbp+var_7D], al\ncmp [rbp+var_7D], 28h ; '('\njnz short loc_1260\ncmp [rbp+var_7E], 29h ; ')'\njnz short loc_1278\nloc_1260:\ncmp [rbp+var_7D], 7Bh ; '{'\njnz short loc_126C\ncmp [rbp+var_7E], 7Dh ; '}'\njnz short loc_1278\nloc_126C:\ncmp [rbp+var_7D], 5Bh ; '['\njnz short loc_127F\ncmp [rbp+var_7E], 5Dh ; ']'\njz short loc_127F\nloc_1278:\nmov eax, 0\njmp short loc_1296\nloc_127F:\nadd [rbp+var_78], 1\nloc_1283:\nmov eax, [rbp+var_78]\ncmp eax, [rbp+var_74]\njl loc_11E7\ncmp [rbp+var_7C], 0FFFFFFFFh\nsetz al\nloc_1296:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12AA\ncall ___stack_chk_fail\nlocret_12AA:\nleave\nretn", + "ida_pseudo": "bool __fastcall func0(const char *a1)\n{\n int v2; // eax\n char v3; // [rsp+12h] [rbp-7Eh]\n char v4; // [rsp+13h] [rbp-7Dh]\n int v5; // [rsp+14h] [rbp-7Ch]\n int i; // [rsp+18h] [rbp-78h]\n int v7; // [rsp+1Ch] [rbp-74h]\n _BYTE v8[104]; // [rsp+20h] [rbp-70h]\n unsigned __int64 v9; // [rsp+88h] [rbp-8h]\n\n v9 = __readfsqword(0x28u);\n v7 = strlen(a1);\n if ( (v7 & 1) != 0 )\n return 0;\n v5 = -1;\n for ( i = 0; i < v7; ++i )\n {\n v3 = a1[i];\n if ( v3 == 40 || v3 == 123 || v3 == 91 )\n {\n v8[++v5] = v3;\n }\n else if ( v3 == 41 || v3 == 125 || v3 == 93 )\n {\n if ( v5 == -1 )\n return 0;\n v2 = v5--;\n v4 = v8[v2];\n if ( v4 == 40 && v3 != 41 )\n return 0;\n if ( v4 == 123 && v3 != 125 || v4 == 91 && v3 != 93 )\n return 0;\n }\n }\n return v5 == -1;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 90h\nmov [rbp+s], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_74], eax\nmov eax, [rbp+var_74]\nand eax, 1\ntest eax, eax\njz short loc_11D4\nmov eax, 0\njmp loc_1296\nloc_11D4:\nmov [rbp+var_7C], 0FFFFFFFFh\nmov [rbp+var_78], 0\njmp loc_1283\nloc_11E7:\nmov eax, [rbp+var_78]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_7E], al\ncmp [rbp+var_7E], 28h ; '('\njz short loc_120F\ncmp [rbp+var_7E], 7Bh ; '{'\njz short loc_120F\ncmp [rbp+var_7E], 5Bh ; '['\njnz short loc_1222\nloc_120F:\nadd [rbp+var_7C], 1\nmov eax, [rbp+var_7C]\ncdqe\nmovzx edx, [rbp+var_7E]\nmov [rbp+rax+var_70], dl\njmp short loc_127F\nloc_1222:\ncmp [rbp+var_7E], 29h ; ')'\njz short loc_1234\ncmp [rbp+var_7E], 7Dh ; '}'\njz short loc_1234\ncmp [rbp+var_7E], 5Dh ; ']'\njnz short loc_127F\nloc_1234:\ncmp [rbp+var_7C], 0FFFFFFFFh\njnz short loc_1241\nmov eax, 0\njmp short loc_1296\nloc_1241:\nmov eax, [rbp+var_7C]\nlea edx, [rax-1]\nmov [rbp+var_7C], edx\ncdqe\nmovzx eax, [rbp+rax+var_70]\nmov [rbp+var_7D], al\ncmp [rbp+var_7D], 28h ; '('\njnz short loc_1260\ncmp [rbp+var_7E], 29h ; ')'\njnz short loc_1278\nloc_1260:\ncmp [rbp+var_7D], 7Bh ; '{'\njnz short loc_126C\ncmp [rbp+var_7E], 7Dh ; '}'\njnz short loc_1278\nloc_126C:\ncmp [rbp+var_7D], 5Bh ; '['\njnz short loc_127F\ncmp [rbp+var_7E], 5Dh ; ']'\njz short loc_127F\nloc_1278:\nmov eax, 0\njmp short loc_1296\nloc_127F:\nadd [rbp+var_78], 1\nloc_1283:\nmov eax, [rbp+var_78]\ncmp eax, [rbp+var_74]\njl loc_11E7\ncmp [rbp+var_7C], 0FFFFFFFFh\nsetz al\nloc_1296:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12AA\ncall ___stack_chk_fail\nlocret_12AA:\nleave\nretn", + "ida_strip_pseudo": "bool __fastcall sub_1189(const char *a1)\n{\n int v2; // eax\n char v3; // [rsp+12h] [rbp-7Eh]\n char v4; // [rsp+13h] [rbp-7Dh]\n int v5; // [rsp+14h] [rbp-7Ch]\n int i; // [rsp+18h] [rbp-78h]\n int v7; // [rsp+1Ch] [rbp-74h]\n _BYTE v8[104]; // [rsp+20h] [rbp-70h]\n unsigned __int64 v9; // [rsp+88h] [rbp-8h]\n\n v9 = __readfsqword(0x28u);\n v7 = strlen(a1);\n if ( (v7 & 1) != 0 )\n return 0;\n v5 = -1;\n for ( i = 0; i < v7; ++i )\n {\n v3 = a1[i];\n if ( v3 == 40 || v3 == 123 || v3 == 91 )\n {\n v8[++v5] = v3;\n }\n else if ( v3 == 41 || v3 == 125 || v3 == 93 )\n {\n if ( v5 == -1 )\n return 0;\n v2 = v5--;\n v4 = v8[v2];\n if ( v4 == 40 && v3 != 41 )\n return 0;\n if ( v4 == 123 && v3 != 125 || v4 == 91 && v3 != 93 )\n return 0;\n }\n }\n return v5 == -1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_1189(const char *a1) {\n int v2;\n char v3;\n char v4;\n int v5;\n int i;\n int v7;\n uint8_t v8[104];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n v7 = strlen(a1);\n if ((v7 & 1) != 0) return 0;\n v5 = -1;\n for (i = 0; i < v7; ++i) {\n v3 = a1[i];\n if (v3 == 40 || v3 == 123 || v3 == 91) {\n v8[++v5] = v3;\n } else if (v3 == 41 || v3 == 125 || v3 == 93) {\n if (v5 == -1) return 0;\n v2 = v5--;\n v4 = v8[v2];\n if (v4 == 40 && v3 != 41) return 0;\n if (v4 == 123 && v3 != 125 || v4 == 91 && v3 != 93) return 0;\n }\n }\n return v5 == -1;\n}", + "ida_pseudo_norm": "bool func0(const char *a1) {\n int v2;\n char v3;\n char v4;\n int v5;\n int i;\n int v7;\n uint8_t v8[104];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n v7 = strlen(a1);\n if ((v7 & 1) != 0) return 0;\n v5 = -1;\n for (i = 0; i < v7; ++i) {\n v3 = a1[i];\n if (v3 == 40 || v3 == 123 || v3 == 91) {\n v8[++v5] = v3;\n } else if (v3 == 41 || v3 == 125 || v3 == 93) {\n if (v5 == -1) return 0;\n v2 = v5--;\n v4 = v8[v2];\n if (v4 == 40 && v3 != 41) return 0;\n if (v4 == 123 && v3 != 125 || v4 == 91 && v3 != 93) return 0;\n }\n }\n return v5 == -1;\n}" + }, + { + "index": 771, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char *exp) {\n int len = strlen(exp);\n if (len % 2 != 0) {\n return false;\n }\n char stack[100];\n int top = -1;\n for (int i = 0; i < len; i++) {\n char ch = exp[i];\n if (ch == '(' || ch == '{' || ch == '[') {\n stack[++top] = ch;\n } else if (ch == ')' || ch == '}' || ch == ']') {\n if (top == -1) {\n return false;\n }\n char last_open = stack[top--];\n if ((last_open == '(' && ch != ')') ||\n (last_open == '{' && ch != '}') ||\n (last_open == '[' && ch != ']')) {\n return false;\n }\n }\n }\n return top == -1;\n}", + "test": "int main() {\n\n assert(func0(\"{()}[{}]\") == true);\n\n assert(func0(\"{()}[{]\") == false);\n\n assert(func0(\"{()}[{}][]({})\") == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x78,%rsp\nmov %rdi,%rdx\nmov %fs:0x28,%rax\nmov %rax,0x68(%rsp)\nxor %eax,%eax\nmov $0xffffffffffffffff,%rcx\nrepnz scas %es:(%rdi),%al\nnot %rcx\ntest $0x1,%cl\nje 1243 \nlea -0x1(%rcx),%rsi\ntest %esi,%esi\njle 1238 \nmov %rdx,%rcx\nlea -0x1(%rsi),%eax\nlea 0x1(%rdx,%rax,1),%r9\nmov $0xffffffff,%esi\njmp 1210 \ncmp $0x29,%dl\nje 11c2 \ncmp $0x5d,%r8b\njne 1207 \ncmp $0xffffffff,%esi\nje 1243 \nlea -0x1(%rsi),%r10d\nmovslq %esi,%rsi\nmovzbl (%rsp,%rsi,1),%edi\ncmp $0x28,%dil\nsete %sil\ncmp $0x29,%dl\nsetne %r8b\nand %r8b,%sil\njne 1243 \ncmp $0x7b,%dil\nsete %al\ncmp $0x7d,%dl\nsetne %r8b\nand %r8b,%al\njne 1258 \ncmp $0x5b,%dil\njne 1204 \ncmp $0x5d,%dl\njne 1243 \nmov %r10d,%esi\nadd $0x1,%rcx\ncmp %r9,%rcx\nje 123d \nmovzbl (%rcx),%edx\nmov %edx,%r8d\nand $0xffffffdf,%r8d\ncmp $0x28,%dl\nsete %al\ncmp $0x5b,%r8b\nsete %dil\nor %dil,%al\nje 11b7 \nadd $0x1,%esi\nmovslq %esi,%rax\nmov %dl,(%rsp,%rax,1)\njmp 1207 \nmov $0xffffffff,%esi\ncmp $0xffffffff,%esi\nsete %al\nmov 0x68(%rsp),%rdi\nxor %fs:0x28,%rdi\njne 125c \nadd $0x78,%rsp\nretq\nmov %esi,%eax\njmp 1243 \ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbx\nsub rsp, 70h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+78h+var_10], rax\nxor eax, eax\ncall _strlen\nmov rdx, rax\nmov eax, 0\ntest dl, 1\njnz loc_1257\ntest edx, edx\njle loc_124C\nmov rcx, rbx\nlea eax, [rdx-1]\nlea r8, [rbx+rax+1]\nmov esi, 0FFFFFFFFh\njmp short loc_1231\nloc_11D5:\ncmp dl, 7Bh ; '{'\njz short loc_121F\ncmp dl, 7Dh ; '}'\njnz short loc_1228\nloc_11DF:\ncmp esi, 0FFFFFFFFh\njz loc_126D\nlea eax, [rsi-1]\nmovsxd rsi, esi\nmovzx edi, [rsp+rsi+78h+var_78]\ncmp dil, 28h ; '('\njnz short loc_11FD\ncmp dl, 29h ; ')'\njnz short loc_1274\nloc_11FD:\nmov esi, eax\nloc_11FF:\ncmp dil, 7Bh ; '{'\nsetz al\ncmp dl, 7Dh ; '}'\nsetnz r9b\nand al, r9b\njnz short loc_127B\ncmp dil, 5Bh ; '['\njnz short loc_1228\ncmp dl, 5Dh ; ']'\njz short loc_1228\njmp short loc_1257\nloc_121F:\nadd esi, 1\nmovsxd rax, esi\nmov [rsp+rax+78h+var_78], dl\nloc_1228:\nadd rcx, 1\ncmp rcx, r8\njz short loc_1251\nloc_1231:\nmovzx edx, byte ptr [rcx]\ncmp dl, 5Dh ; ']'\njz short loc_11DF\njg short loc_11D5\ncmp dl, 29h ; ')'\njz short loc_1289\ncmp dl, 5Bh ; '['\njz short loc_121F\ncmp dl, 28h ; '('\njnz short loc_1228\njmp short loc_121F\nloc_124C:\nmov esi, 0FFFFFFFFh\nloc_1251:\ncmp esi, 0FFFFFFFFh\nsetz al\nloc_1257:\nmov rdx, [rsp+78h+var_10]\nsub rdx, fs:28h\njnz short loc_129D\nadd rsp, 70h\npop rbx\nretn\nloc_126D:\nmov eax, 0\njmp short loc_1257\nloc_1274:\nmov eax, 0\njmp short loc_1257\nloc_127B:\nmov eax, 0\njmp short loc_1257\nloc_1282:\nmov eax, 0\njmp short loc_1257\nloc_1289:\ncmp esi, 0FFFFFFFFh\njz short loc_1282\nmovsxd rax, esi\nmovzx edi, [rsp+rax+78h+var_78]\nlea esi, [rsi-1]\njmp loc_11FF\nloc_129D:\ncall ___stack_chk_fail", + "ida_pseudo": "bool __fastcall func0(const char *a1)\n{\n int v1; // edx\n bool result; // al\n char *v3; // rcx\n __int64 v4; // r8\n int v5; // esi\n char v6; // di\n char v7; // dl\n _BYTE v8[104]; // [rsp+0h] [rbp-78h]\n unsigned __int64 v9; // [rsp+68h] [rbp-10h]\n\n v9 = __readfsqword(0x28u);\n v1 = strlen(a1);\n result = 0;\n if ( (v1 & 1) == 0 )\n {\n if ( v1 > 0 )\n {\n v3 = (char *)a1;\n v4 = (__int64)&a1[v1 - 1 + 1];\n v5 = -1;\n while ( 1 )\n {\n v7 = *v3;\n if ( *v3 == 93 )\n break;\n if ( v7 <= 93 )\n {\n if ( v7 != 41 )\n {\n if ( v7 != 91 && v7 != 40 )\n goto LABEL_15;\nLABEL_14:\n v8[++v5] = v7;\n goto LABEL_15;\n }\n if ( v5 == -1 )\n return 0;\n v6 = v8[v5--];\n goto LABEL_10;\n }\n if ( v7 == 123 )\n goto LABEL_14;\n if ( v7 == 125 )\n break;\nLABEL_15:\n if ( ++v3 == (char *)v4 )\n return v5 == -1;\n }\n if ( v5 == -1 )\n return 0;\n v6 = v8[v5];\n if ( v6 == 40 && v7 != 41 )\n return 0;\n --v5;\nLABEL_10:\n result = v7 != 125 && v6 == 123;\n if ( result )\n return 0;\n if ( v6 == 91 && v7 != 93 )\n return result;\n goto LABEL_15;\n }\n v5 = -1;\n return v5 == -1;\n }\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbx\nsub rsp, 70h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+78h+var_10], rax\nxor eax, eax\ncall _strlen\nmov rdx, rax\nmov eax, 0\ntest dl, 1\njnz loc_1257\ntest edx, edx\njle loc_124C\nmov rcx, rbx\nlea eax, [rdx-1]\nlea r8, [rbx+rax+1]\nmov esi, 0FFFFFFFFh\njmp short loc_1231\nloc_11D5:\ncmp dl, 7Bh ; '{'\njz short loc_121F\ncmp dl, 7Dh ; '}'\njnz short loc_1228\nloc_11DF:\ncmp esi, 0FFFFFFFFh\njz loc_126D\nlea eax, [rsi-1]\nmovsxd rsi, esi\nmovzx edi, [rsp+rsi+78h+var_78]\ncmp dil, 28h ; '('\njnz short loc_11FD\ncmp dl, 29h ; ')'\njnz short loc_1274\nloc_11FD:\nmov esi, eax\nloc_11FF:\ncmp dil, 7Bh ; '{'\nsetz al\ncmp dl, 7Dh ; '}'\nsetnz r9b\nand al, r9b\njnz short loc_127B\ncmp dil, 5Bh ; '['\njnz short loc_1228\ncmp dl, 5Dh ; ']'\njz short loc_1228\njmp short loc_1257\nloc_121F:\nadd esi, 1\nmovsxd rax, esi\nmov [rsp+rax+78h+var_78], dl\nloc_1228:\nadd rcx, 1\ncmp rcx, r8\njz short loc_1251\nloc_1231:\nmovzx edx, byte ptr [rcx]\ncmp dl, 5Dh ; ']'\njz short loc_11DF\njg short loc_11D5\ncmp dl, 29h ; ')'\njz short loc_1289\ncmp dl, 5Bh ; '['\njz short loc_121F\ncmp dl, 28h ; '('\njnz short loc_1228\njmp short loc_121F\nloc_124C:\nmov esi, 0FFFFFFFFh\nloc_1251:\ncmp esi, 0FFFFFFFFh\nsetz al\nloc_1257:\nmov rdx, [rsp+78h+var_10]\nsub rdx, fs:28h\njnz short loc_129D\nadd rsp, 70h\npop rbx\nretn\nloc_126D:\nmov eax, 0\njmp short loc_1257\nloc_1274:\nmov eax, 0\njmp short loc_1257\nloc_127B:\nmov eax, 0\njmp short loc_1257\nloc_1282:\nmov eax, 0\njmp short loc_1257\nloc_1289:\ncmp esi, 0FFFFFFFFh\njz short loc_1282\nmovsxd rax, esi\nmovzx edi, [rsp+rax+78h+var_78]\nlea esi, [rsi-1]\njmp loc_11FF\nloc_129D:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "bool __fastcall sub_1189(const char *a1)\n{\n int v1; // edx\n bool result; // al\n char *v3; // rcx\n __int64 v4; // r8\n int v5; // esi\n char v6; // di\n char v7; // dl\n _BYTE v8[104]; // [rsp+0h] [rbp-78h]\n unsigned __int64 v9; // [rsp+68h] [rbp-10h]\n\n v9 = __readfsqword(0x28u);\n v1 = strlen(a1);\n result = 0;\n if ( (v1 & 1) == 0 )\n {\n if ( v1 > 0 )\n {\n v3 = (char *)a1;\n v4 = (__int64)&a1[v1 - 1 + 1];\n v5 = -1;\n while ( 1 )\n {\n v7 = *v3;\n if ( *v3 == 93 )\n break;\n if ( v7 <= 93 )\n {\n if ( v7 != 41 )\n {\n if ( v7 != 91 && v7 != 40 )\n goto LABEL_15;\nLABEL_14:\n v8[++v5] = v7;\n goto LABEL_15;\n }\n if ( v5 == -1 )\n return 0;\n v6 = v8[v5--];\n goto LABEL_10;\n }\n if ( v7 == 123 )\n goto LABEL_14;\n if ( v7 == 125 )\n break;\nLABEL_15:\n if ( ++v3 == (char *)v4 )\n return v5 == -1;\n }\n if ( v5 == -1 )\n return 0;\n v6 = v8[v5];\n if ( v6 == 40 && v7 != 41 )\n return 0;\n --v5;\nLABEL_10:\n result = v7 != 125 && v6 == 123;\n if ( result )\n return 0;\n if ( v6 == 91 && v7 != 93 )\n return result;\n goto LABEL_15;\n }\n v5 = -1;\n return v5 == -1;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_1189(const char *a1) {\n int v1;\n bool result;\n char *v3;\n long long v4;\n int v5;\n char v6;\n char v7;\n uint8_t v8[104];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n v1 = strlen(a1);\n result = 0;\n if ((v1 & 1) == 0) {\n if (v1 > 0) {\n v3 = (char *)a1;\n v4 = (long long)&a1[v1 - 1 + 1];\n v5 = -1;\n while (1) {\n v7 = *v3;\n if (*v3 == 93) break;\n if (v7 <= 93) {\n if (v7 != 41) {\n if (v7 != 91 && v7 != 40) goto LABEL_15;\n LABEL_14:\n v8[++v5] = v7;\n goto LABEL_15;\n }\n if (v5 == -1) return 0;\n v6 = v8[v5--];\n goto LABEL_10;\n }\n if (v7 == 123) goto LABEL_14;\n if (v7 == 125) break;\n LABEL_15:\n if (++v3 == (char *)v4) return v5 == -1;\n }\n if (v5 == -1) return 0;\n v6 = v8[v5];\n if (v6 == 40 && v7 != 41) return 0;\n --v5;\n LABEL_10:\n result = v7 != 125 && v6 == 123;\n if (result) return 0;\n if (v6 == 91 && v7 != 93) return result;\n goto LABEL_15;\n }\n v5 = -1;\n return v5 == -1;\n }\n return result;\n}", + "ida_pseudo_norm": "bool func0(const char *a1) {\n int v1;\n bool result;\n char *v3;\n long long v4;\n int v5;\n char v6;\n char v7;\n uint8_t v8[104];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n v1 = strlen(a1);\n result = 0;\n if ((v1 & 1) == 0) {\n if (v1 > 0) {\n v3 = (char *)a1;\n v4 = (long long)&a1[v1 - 1 + 1];\n v5 = -1;\n while (1) {\n v7 = *v3;\n if (*v3 == 93) break;\n if (v7 <= 93) {\n if (v7 != 41) {\n if (v7 != 91 && v7 != 40) goto LABEL_15;\n LABEL_14:\n v8[++v5] = v7;\n goto LABEL_15;\n }\n if (v5 == -1) return 0;\n v6 = v8[v5--];\n goto LABEL_10;\n }\n if (v7 == 123) goto LABEL_14;\n if (v7 == 125) break;\n LABEL_15:\n if (++v3 == (char *)v4) return v5 == -1;\n }\n if (v5 == -1) return 0;\n v6 = v8[v5];\n if (v6 == 40 && v7 != 41) return 0;\n --v5;\n LABEL_10:\n result = v7 != 125 && v6 == 123;\n if (result) return 0;\n if (v6 == 91 && v7 != 93) return result;\n goto LABEL_15;\n }\n v5 = -1;\n return v5 == -1;\n }\n return result;\n}" + }, + { + "index": 771, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char *exp) {\n int len = strlen(exp);\n if (len % 2 != 0) {\n return false;\n }\n char stack[100];\n int top = -1;\n for (int i = 0; i < len; i++) {\n char ch = exp[i];\n if (ch == '(' || ch == '{' || ch == '[') {\n stack[++top] = ch;\n } else if (ch == ')' || ch == '}' || ch == ']') {\n if (top == -1) {\n return false;\n }\n char last_open = stack[top--];\n if ((last_open == '(' && ch != ')') ||\n (last_open == '{' && ch != '}') ||\n (last_open == '[' && ch != ']')) {\n return false;\n }\n }\n }\n return top == -1;\n}", + "test": "int main() {\n\n assert(func0(\"{()}[{}]\") == true);\n\n assert(func0(\"{()}[{]\") == false);\n\n assert(func0(\"{()}[{}][]({})\") == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\nsub $0x70,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x68(%rsp)\nxor %eax,%eax\ncallq 1070 \ntest $0x1,%al\njne 12d0 \ntest %eax,%eax\njle 12fb \nsub $0x1,%eax\nmov %rbx,%rdi\nmov $0xffffffff,%edx\nlea 0x1(%rbx,%rax,1),%rsi\nnopl (%rax)\nmovzbl (%rdi),%eax\nmov %eax,%ecx\nand $0xffffffdf,%ecx\ncmp $0x28,%al\nje 12f0 \ncmp $0x5b,%cl\nje 12f0 \ncmp $0x29,%al\nje 128a \ncmp $0x5d,%cl\njne 12b6 \ncmp $0xffffffff,%edx\nje 12d0 \nlea -0x1(%rdx),%ecx\nmovslq %edx,%rdx\nmovzbl (%rsp,%rdx,1),%edx\ncmp $0x28,%dl\njne 12a2 \ncmp $0x29,%al\njne 12d0 \ncmp $0x7b,%dl\njne 12ab \ncmp $0x7d,%al\njne 12d0 \ncmp $0x5b,%dl\njne 12b4 \ncmp $0x5d,%al\njne 12d0 \nmov %ecx,%edx\nadd $0x1,%rdi\ncmp %rdi,%rsi\njne 1270 \ncmp $0xffffffff,%edx\nsete %al\njmp 12d2 \nnopw 0x0(%rax,%rax,1)\nxor %eax,%eax\nmov 0x68(%rsp),%rbx\nxor %fs:0x28,%rbx\njne 1302 \nadd $0x70,%rsp\npop %rbx\nretq\nnopl 0x0(%rax,%rax,1)\nadd $0x1,%edx\nmovslq %edx,%rcx\nmov %al,(%rsp,%rcx,1)\njmp 12b6 \nmov $0x1,%eax\njmp 12d2 \ncallq 1080 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\nsub rsp, 70h\nmov rax, fs:28h\nmov [rsp+78h+var_10], rax\nxor eax, eax\ncall _strlen\ntest al, 1\njnz short loc_12C8\ntest eax, eax\njle loc_1311\nsub eax, 1\nmov rdi, rbx\nmov edx, 0FFFFFFFFh\nlea rsi, [rbx+rax+1]\njmp short loc_1289\nloc_1270:\ncmp al, 29h ; ')'\njz loc_1300\ncmp al, 5Bh ; '['\njz short loc_12E0\ncmp al, 28h ; '('\njz short loc_12E0\nloc_1280:\nadd rdi, 1\ncmp rdi, rsi\njz short loc_12F2\nloc_1289:\nmovzx eax, byte ptr [rdi]\ncmp al, 5Dh ; ']'\njz short loc_129A\njle short loc_1270\ncmp al, 7Bh ; '{'\njz short loc_12E0\ncmp al, 7Dh ; '}'\njnz short loc_1280\nloc_129A:\ncmp edx, 0FFFFFFFFh\njz short loc_12C8\nlea r8d, [rdx-1]\nmovsxd rdx, edx\nmovzx ecx, [rsp+rdx+78h+var_78]\ncmp cl, 28h ; '('\njz short loc_12C8\nmov edx, r8d\nloc_12B2:\ncmp cl, 7Bh ; '{'\njnz short loc_12BB\ncmp al, 7Dh ; '}'\njnz short loc_12C8\nloc_12BB:\ncmp cl, 5Bh ; '['\njnz short loc_1280\ncmp al, 5Dh ; ']'\njz short loc_1280\nnop dword ptr [rax+00h]\nloc_12C8:\nxor eax, eax\nloc_12CA:\nmov rdx, [rsp+78h+var_10]\nsub rdx, fs:28h\njnz short loc_1318\nadd rsp, 70h\npop rbx\nretn\nloc_12E0:\nadd edx, 1\nadd rdi, 1\nmovsxd rcx, edx\nmov [rsp+rcx+78h+var_78], al\ncmp rdi, rsi\njnz short loc_1289\nloc_12F2:\ncmp edx, 0FFFFFFFFh\nsetz al\njmp short loc_12CA\nloc_1300:\ncmp edx, 0FFFFFFFFh\njz short loc_12C8\nmovsxd rcx, edx\nsub edx, 1\nmovzx ecx, [rsp+rcx+78h+var_78]\njmp short loc_12B2\nloc_1311:\nmov eax, 1\njmp short loc_12CA\nloc_1318:\ncall ___stack_chk_fail", + "ida_pseudo": "char __fastcall func0(const char *a1)\n{\n int v1; // eax\n int v2; // edx\n __int64 v3; // rsi\n char v4; // al\n char v5; // cl\n __int64 v7; // rcx\n _BYTE v8[104]; // [rsp+0h] [rbp-78h]\n unsigned __int64 v9; // [rsp+68h] [rbp-10h]\n\n v9 = __readfsqword(0x28u);\n v1 = strlen(a1);\n if ( (v1 & 1) != 0 )\n return 0;\n if ( v1 > 0 )\n {\n v2 = -1;\n v3 = (__int64)&a1[v1 - 1 + 1];\n while ( 1 )\n {\n v4 = *a1;\n if ( *a1 == 93 )\n {\nLABEL_12:\n if ( v2 == -1 )\n return 0;\n v5 = v8[v2];\n if ( v5 == 40 )\n return 0;\n --v2;\nLABEL_15:\n if ( v5 == 123 && v4 != 125 || v5 == 91 && v4 != 93 )\n return 0;\n goto LABEL_7;\n }\n if ( v4 <= 93 )\n {\n if ( v4 == 41 )\n {\n if ( v2 == -1 )\n return 0;\n v7 = v2--;\n v5 = v8[v7];\n goto LABEL_15;\n }\n if ( v4 == 91 || v4 == 40 )\n goto LABEL_20;\nLABEL_7:\n if ( ++a1 == (const char *)v3 )\n return v2 == -1;\n }\n else\n {\n if ( v4 != 123 )\n {\n if ( v4 == 125 )\n goto LABEL_12;\n goto LABEL_7;\n }\nLABEL_20:\n ++v2;\n ++a1;\n v8[v2] = v4;\n if ( a1 == (const char *)v3 )\n return v2 == -1;\n }\n }\n }\n return 1;\n}", + "ida_strip_asm": "sub_1230:\nendbr64\npush rbx\nmov rbx, rdi\nsub rsp, 70h\nmov rax, fs:28h\nmov [rsp+78h+var_10], rax\nxor eax, eax\ncall _strlen\ntest al, 1\njnz short loc_12C8\ntest eax, eax\njle loc_1311\nsub eax, 1\nmov rdi, rbx\nmov edx, 0FFFFFFFFh\nlea rsi, [rbx+rax+1]\njmp short loc_1289\nloc_1270:\ncmp al, 29h ; ')'\njz loc_1300\ncmp al, 5Bh ; '['\njz short loc_12E0\ncmp al, 28h ; '('\njz short loc_12E0\nloc_1280:\nadd rdi, 1\ncmp rdi, rsi\njz short loc_12F2\nloc_1289:\nmovzx eax, byte ptr [rdi]\ncmp al, 5Dh ; ']'\njz short loc_129A\njle short loc_1270\ncmp al, 7Bh ; '{'\njz short loc_12E0\ncmp al, 7Dh ; '}'\njnz short loc_1280\nloc_129A:\ncmp edx, 0FFFFFFFFh\njz short loc_12C8\nlea r8d, [rdx-1]\nmovsxd rdx, edx\nmovzx ecx, [rsp+rdx+78h+var_78]\ncmp cl, 28h ; '('\njz short loc_12C8\nmov edx, r8d\nloc_12B2:\ncmp cl, 7Bh ; '{'\njnz short loc_12BB\ncmp al, 7Dh ; '}'\njnz short loc_12C8\nloc_12BB:\ncmp cl, 5Bh ; '['\njnz short loc_1280\ncmp al, 5Dh ; ']'\njz short loc_1280\nnop dword ptr [rax+00h]\nloc_12C8:\nxor eax, eax\nloc_12CA:\nmov rdx, [rsp+78h+var_10]\nsub rdx, fs:28h\njnz short loc_1318\nadd rsp, 70h\npop rbx\nretn\nloc_12E0:\nadd edx, 1\nadd rdi, 1\nmovsxd rcx, edx\nmov [rsp+rcx+78h+var_78], al\ncmp rdi, rsi\njnz short loc_1289\nloc_12F2:\ncmp edx, 0FFFFFFFFh\nsetz al\njmp short loc_12CA\nloc_1300:\ncmp edx, 0FFFFFFFFh\njz short loc_12C8\nmovsxd rcx, edx\nsub edx, 1\nmovzx ecx, [rsp+rcx+78h+var_78]\njmp short loc_12B2\nloc_1311:\nmov eax, 1\njmp short loc_12CA\nloc_1318:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char __fastcall sub_1230(const char *a1)\n{\n int v1; // eax\n int v2; // edx\n __int64 v3; // rsi\n char v4; // al\n char v5; // cl\n __int64 v7; // rcx\n _BYTE v8[104]; // [rsp+0h] [rbp-78h]\n unsigned __int64 v9; // [rsp+68h] [rbp-10h]\n\n v9 = __readfsqword(0x28u);\n v1 = strlen(a1);\n if ( (v1 & 1) != 0 )\n return 0;\n if ( v1 > 0 )\n {\n v2 = -1;\n v3 = (__int64)&a1[v1 - 1 + 1];\n while ( 1 )\n {\n v4 = *a1;\n if ( *a1 == 93 )\n {\nLABEL_12:\n if ( v2 == -1 )\n return 0;\n v5 = v8[v2];\n if ( v5 == 40 )\n return 0;\n --v2;\nLABEL_15:\n if ( v5 == 123 && v4 != 125 || v5 == 91 && v4 != 93 )\n return 0;\n goto LABEL_7;\n }\n if ( v4 <= 93 )\n {\n if ( v4 == 41 )\n {\n if ( v2 == -1 )\n return 0;\n v7 = v2--;\n v5 = v8[v7];\n goto LABEL_15;\n }\n if ( v4 == 91 || v4 == 40 )\n goto LABEL_20;\nLABEL_7:\n if ( ++a1 == (const char *)v3 )\n return v2 == -1;\n }\n else\n {\n if ( v4 != 123 )\n {\n if ( v4 == 125 )\n goto LABEL_12;\n goto LABEL_7;\n }\nLABEL_20:\n ++v2;\n ++a1;\n v8[v2] = v4;\n if ( a1 == (const char *)v3 )\n return v2 == -1;\n }\n }\n }\n return 1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char sub_1230(const char *a1) {\n int v1;\n int v2;\n long long v3;\n char v4;\n char v5;\n long long v7;\n uint8_t v8[104];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n v1 = strlen(a1);\n if ((v1 & 1) != 0) return 0;\n if (v1 > 0) {\n v2 = -1;\n v3 = (long long)&a1[v1 - 1 + 1];\n while (1) {\n v4 = *a1;\n if (*a1 == 93) {\n LABEL_12:\n if (v2 == -1) return 0;\n v5 = v8[v2];\n if (v5 == 40) return 0;\n --v2;\n LABEL_15:\n if (v5 == 123 && v4 != 125 || v5 == 91 && v4 != 93) return 0;\n goto LABEL_7;\n }\n if (v4 <= 93) {\n if (v4 == 41) {\n if (v2 == -1) return 0;\n v7 = v2--;\n v5 = v8[v7];\n goto LABEL_15;\n }\n if (v4 == 91 || v4 == 40) goto LABEL_20;\n LABEL_7:\n if (++a1 == (const char *)v3) return v2 == -1;\n } else {\n if (v4 != 123) {\n if (v4 == 125) goto LABEL_12;\n goto LABEL_7;\n }\n LABEL_20:\n ++v2;\n ++a1;\n v8[v2] = v4;\n if (a1 == (const char *)v3) return v2 == -1;\n }\n }\n }\n return 1;\n}", + "ida_pseudo_norm": "char func0(const char *a1) {\n int v1;\n int v2;\n long long v3;\n char v4;\n char v5;\n long long v7;\n uint8_t v8[104];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n v1 = strlen(a1);\n if ((v1 & 1) != 0) return 0;\n if (v1 > 0) {\n v2 = -1;\n v3 = (long long)&a1[v1 - 1 + 1];\n while (1) {\n v4 = *a1;\n if (*a1 == 93) {\n LABEL_12:\n if (v2 == -1) return 0;\n v5 = v8[v2];\n if (v5 == 40) return 0;\n --v2;\n LABEL_15:\n if (v5 == 123 && v4 != 125 || v5 == 91 && v4 != 93) return 0;\n goto LABEL_7;\n }\n if (v4 <= 93) {\n if (v4 == 41) {\n if (v2 == -1) return 0;\n v7 = v2--;\n v5 = v8[v7];\n goto LABEL_15;\n }\n if (v4 == 91 || v4 == 40) goto LABEL_20;\n LABEL_7:\n if (++a1 == (const char *)v3) return v2 == -1;\n } else {\n if (v4 != 123) {\n if (v4 == 125) goto LABEL_12;\n goto LABEL_7;\n }\n LABEL_20:\n ++v2;\n ++a1;\n v8[v2] = v4;\n if (a1 == (const char *)v3) return v2 == -1;\n }\n }\n }\n return 1;\n}" + }, + { + "index": 771, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char *exp) {\n int len = strlen(exp);\n if (len % 2 != 0) {\n return false;\n }\n char stack[100];\n int top = -1;\n for (int i = 0; i < len; i++) {\n char ch = exp[i];\n if (ch == '(' || ch == '{' || ch == '[') {\n stack[++top] = ch;\n } else if (ch == ')' || ch == '}' || ch == ']') {\n if (top == -1) {\n return false;\n }\n char last_open = stack[top--];\n if ((last_open == '(' && ch != ')') ||\n (last_open == '{' && ch != '}') ||\n (last_open == '[' && ch != ']')) {\n return false;\n }\n }\n }\n return top == -1;\n}", + "test": "int main() {\n\n assert(func0(\"{()}[{}]\") == true);\n\n assert(func0(\"{()}[{]\") == false);\n\n assert(func0(\"{()}[{}][]({})\") == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\nsub $0x70,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x68(%rsp)\nxor %eax,%eax\ncallq 1070 \ntest $0x1,%al\njne 12d0 \ntest %eax,%eax\njle 12fb \nsub $0x1,%eax\nmov %rbx,%rdi\nmov $0xffffffff,%edx\nlea 0x1(%rbx,%rax,1),%rsi\nnopl (%rax)\nmovzbl (%rdi),%eax\nmov %eax,%ecx\nand $0xffffffdf,%ecx\ncmp $0x28,%al\nje 12f0 \ncmp $0x5b,%cl\nje 12f0 \ncmp $0x29,%al\nje 128a \ncmp $0x5d,%cl\njne 12b6 \ncmp $0xffffffff,%edx\nje 12d0 \nlea -0x1(%rdx),%ecx\nmovslq %edx,%rdx\nmovzbl (%rsp,%rdx,1),%edx\ncmp $0x28,%dl\njne 12a2 \ncmp $0x29,%al\njne 12d0 \ncmp $0x7b,%dl\njne 12ab \ncmp $0x7d,%al\njne 12d0 \ncmp $0x5b,%dl\njne 12b4 \ncmp $0x5d,%al\njne 12d0 \nmov %ecx,%edx\nadd $0x1,%rdi\ncmp %rdi,%rsi\njne 1270 \ncmp $0xffffffff,%edx\nsete %al\njmp 12d2 \nnopw 0x0(%rax,%rax,1)\nxor %eax,%eax\nmov 0x68(%rsp),%rbx\nxor %fs:0x28,%rbx\njne 1302 \nadd $0x70,%rsp\npop %rbx\nretq\nnopl 0x0(%rax,%rax,1)\nadd $0x1,%edx\nmovslq %edx,%rcx\nmov %al,(%rsp,%rcx,1)\njmp 12b6 \nmov $0x1,%eax\njmp 12d2 \ncallq 1080 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\nsub rsp, 70h\nmov rax, fs:28h\nmov [rsp+78h+var_10], rax\nxor eax, eax\ncall _strlen\ntest al, 1\njnz short loc_12C8\ntest eax, eax\njle loc_1311\nsub eax, 1\nmov rdi, rbx\nmov edx, 0FFFFFFFFh\nlea rsi, [rbx+rax+1]\njmp short loc_1289\nloc_1270:\ncmp al, 29h ; ')'\njz loc_1300\ncmp al, 5Bh ; '['\njz short loc_12E0\ncmp al, 28h ; '('\njz short loc_12E0\nloc_1280:\nadd rdi, 1\ncmp rdi, rsi\njz short loc_12F2\nloc_1289:\nmovzx eax, byte ptr [rdi]\ncmp al, 5Dh ; ']'\njz short loc_129A\njle short loc_1270\ncmp al, 7Bh ; '{'\njz short loc_12E0\ncmp al, 7Dh ; '}'\njnz short loc_1280\nloc_129A:\ncmp edx, 0FFFFFFFFh\njz short loc_12C8\nlea r8d, [rdx-1]\nmovsxd rdx, edx\nmovzx ecx, [rsp+rdx+78h+var_78]\ncmp cl, 28h ; '('\njz short loc_12C8\nmov edx, r8d\nloc_12B2:\ncmp cl, 7Bh ; '{'\njnz short loc_12BB\ncmp al, 7Dh ; '}'\njnz short loc_12C8\nloc_12BB:\ncmp cl, 5Bh ; '['\njnz short loc_1280\ncmp al, 5Dh ; ']'\njz short loc_1280\nnop dword ptr [rax+00h]\nloc_12C8:\nxor eax, eax\nloc_12CA:\nmov rdx, [rsp+78h+var_10]\nsub rdx, fs:28h\njnz short loc_1318\nadd rsp, 70h\npop rbx\nretn\nloc_12E0:\nadd edx, 1\nadd rdi, 1\nmovsxd rcx, edx\nmov [rsp+rcx+78h+var_78], al\ncmp rdi, rsi\njnz short loc_1289\nloc_12F2:\ncmp edx, 0FFFFFFFFh\nsetz al\njmp short loc_12CA\nloc_1300:\ncmp edx, 0FFFFFFFFh\njz short loc_12C8\nmovsxd rcx, edx\nsub edx, 1\nmovzx ecx, [rsp+rcx+78h+var_78]\njmp short loc_12B2\nloc_1311:\nmov eax, 1\njmp short loc_12CA\nloc_1318:\ncall ___stack_chk_fail", + "ida_pseudo": "char __fastcall func0(const char *a1)\n{\n int v1; // eax\n int v2; // edx\n __int64 v3; // rsi\n char v4; // al\n char v5; // cl\n __int64 v7; // rcx\n _BYTE v8[104]; // [rsp+0h] [rbp-78h]\n unsigned __int64 v9; // [rsp+68h] [rbp-10h]\n\n v9 = __readfsqword(0x28u);\n v1 = strlen(a1);\n if ( (v1 & 1) != 0 )\n return 0;\n if ( v1 > 0 )\n {\n v2 = -1;\n v3 = (__int64)&a1[v1 - 1 + 1];\n while ( 1 )\n {\n v4 = *a1;\n if ( *a1 == 93 )\n {\nLABEL_12:\n if ( v2 == -1 )\n return 0;\n v5 = v8[v2];\n if ( v5 == 40 )\n return 0;\n --v2;\nLABEL_15:\n if ( v5 == 123 && v4 != 125 || v5 == 91 && v4 != 93 )\n return 0;\n goto LABEL_7;\n }\n if ( v4 <= 93 )\n {\n if ( v4 == 41 )\n {\n if ( v2 == -1 )\n return 0;\n v7 = v2--;\n v5 = v8[v7];\n goto LABEL_15;\n }\n if ( v4 == 91 || v4 == 40 )\n goto LABEL_20;\nLABEL_7:\n if ( ++a1 == (const char *)v3 )\n return v2 == -1;\n }\n else\n {\n if ( v4 != 123 )\n {\n if ( v4 == 125 )\n goto LABEL_12;\n goto LABEL_7;\n }\nLABEL_20:\n ++v2;\n ++a1;\n v8[v2] = v4;\n if ( a1 == (const char *)v3 )\n return v2 == -1;\n }\n }\n }\n return 1;\n}", + "ida_strip_asm": "sub_1230:\nendbr64\npush rbx\nmov rbx, rdi\nsub rsp, 70h\nmov rax, fs:28h\nmov [rsp+78h+var_10], rax\nxor eax, eax\ncall _strlen\ntest al, 1\njnz short loc_12C8\ntest eax, eax\njle loc_1311\nsub eax, 1\nmov rdi, rbx\nmov edx, 0FFFFFFFFh\nlea rsi, [rbx+rax+1]\njmp short loc_1289\nloc_1270:\ncmp al, 29h ; ')'\njz loc_1300\ncmp al, 5Bh ; '['\njz short loc_12E0\ncmp al, 28h ; '('\njz short loc_12E0\nloc_1280:\nadd rdi, 1\ncmp rdi, rsi\njz short loc_12F2\nloc_1289:\nmovzx eax, byte ptr [rdi]\ncmp al, 5Dh ; ']'\njz short loc_129A\njle short loc_1270\ncmp al, 7Bh ; '{'\njz short loc_12E0\ncmp al, 7Dh ; '}'\njnz short loc_1280\nloc_129A:\ncmp edx, 0FFFFFFFFh\njz short loc_12C8\nlea r8d, [rdx-1]\nmovsxd rdx, edx\nmovzx ecx, [rsp+rdx+78h+var_78]\ncmp cl, 28h ; '('\njz short loc_12C8\nmov edx, r8d\nloc_12B2:\ncmp cl, 7Bh ; '{'\njnz short loc_12BB\ncmp al, 7Dh ; '}'\njnz short loc_12C8\nloc_12BB:\ncmp cl, 5Bh ; '['\njnz short loc_1280\ncmp al, 5Dh ; ']'\njz short loc_1280\nnop dword ptr [rax+00h]\nloc_12C8:\nxor eax, eax\nloc_12CA:\nmov rdx, [rsp+78h+var_10]\nsub rdx, fs:28h\njnz short loc_1318\nadd rsp, 70h\npop rbx\nretn\nloc_12E0:\nadd edx, 1\nadd rdi, 1\nmovsxd rcx, edx\nmov [rsp+rcx+78h+var_78], al\ncmp rdi, rsi\njnz short loc_1289\nloc_12F2:\ncmp edx, 0FFFFFFFFh\nsetz al\njmp short loc_12CA\nloc_1300:\ncmp edx, 0FFFFFFFFh\njz short loc_12C8\nmovsxd rcx, edx\nsub edx, 1\nmovzx ecx, [rsp+rcx+78h+var_78]\njmp short loc_12B2\nloc_1311:\nmov eax, 1\njmp short loc_12CA\nloc_1318:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char __fastcall sub_1230(const char *a1)\n{\n int v1; // eax\n int v2; // edx\n __int64 v3; // rsi\n char v4; // al\n char v5; // cl\n __int64 v7; // rcx\n _BYTE v8[104]; // [rsp+0h] [rbp-78h]\n unsigned __int64 v9; // [rsp+68h] [rbp-10h]\n\n v9 = __readfsqword(0x28u);\n v1 = strlen(a1);\n if ( (v1 & 1) != 0 )\n return 0;\n if ( v1 > 0 )\n {\n v2 = -1;\n v3 = (__int64)&a1[v1 - 1 + 1];\n while ( 1 )\n {\n v4 = *a1;\n if ( *a1 == 93 )\n {\nLABEL_12:\n if ( v2 == -1 )\n return 0;\n v5 = v8[v2];\n if ( v5 == 40 )\n return 0;\n --v2;\nLABEL_15:\n if ( v5 == 123 && v4 != 125 || v5 == 91 && v4 != 93 )\n return 0;\n goto LABEL_7;\n }\n if ( v4 <= 93 )\n {\n if ( v4 == 41 )\n {\n if ( v2 == -1 )\n return 0;\n v7 = v2--;\n v5 = v8[v7];\n goto LABEL_15;\n }\n if ( v4 == 91 || v4 == 40 )\n goto LABEL_20;\nLABEL_7:\n if ( ++a1 == (const char *)v3 )\n return v2 == -1;\n }\n else\n {\n if ( v4 != 123 )\n {\n if ( v4 == 125 )\n goto LABEL_12;\n goto LABEL_7;\n }\nLABEL_20:\n ++v2;\n ++a1;\n v8[v2] = v4;\n if ( a1 == (const char *)v3 )\n return v2 == -1;\n }\n }\n }\n return 1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char sub_1230(const char *a1) {\n int v1;\n int v2;\n long long v3;\n char v4;\n char v5;\n long long v7;\n uint8_t v8[104];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n v1 = strlen(a1);\n if ((v1 & 1) != 0) return 0;\n if (v1 > 0) {\n v2 = -1;\n v3 = (long long)&a1[v1 - 1 + 1];\n while (1) {\n v4 = *a1;\n if (*a1 == 93) {\n LABEL_12:\n if (v2 == -1) return 0;\n v5 = v8[v2];\n if (v5 == 40) return 0;\n --v2;\n LABEL_15:\n if (v5 == 123 && v4 != 125 || v5 == 91 && v4 != 93) return 0;\n goto LABEL_7;\n }\n if (v4 <= 93) {\n if (v4 == 41) {\n if (v2 == -1) return 0;\n v7 = v2--;\n v5 = v8[v7];\n goto LABEL_15;\n }\n if (v4 == 91 || v4 == 40) goto LABEL_20;\n LABEL_7:\n if (++a1 == (const char *)v3) return v2 == -1;\n } else {\n if (v4 != 123) {\n if (v4 == 125) goto LABEL_12;\n goto LABEL_7;\n }\n LABEL_20:\n ++v2;\n ++a1;\n v8[v2] = v4;\n if (a1 == (const char *)v3) return v2 == -1;\n }\n }\n }\n return 1;\n}", + "ida_pseudo_norm": "char func0(const char *a1) {\n int v1;\n int v2;\n long long v3;\n char v4;\n char v5;\n long long v7;\n uint8_t v8[104];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n v1 = strlen(a1);\n if ((v1 & 1) != 0) return 0;\n if (v1 > 0) {\n v2 = -1;\n v3 = (long long)&a1[v1 - 1 + 1];\n while (1) {\n v4 = *a1;\n if (*a1 == 93) {\n LABEL_12:\n if (v2 == -1) return 0;\n v5 = v8[v2];\n if (v5 == 40) return 0;\n --v2;\n LABEL_15:\n if (v5 == 123 && v4 != 125 || v5 == 91 && v4 != 93) return 0;\n goto LABEL_7;\n }\n if (v4 <= 93) {\n if (v4 == 41) {\n if (v2 == -1) return 0;\n v7 = v2--;\n v5 = v8[v7];\n goto LABEL_15;\n }\n if (v4 == 91 || v4 == 40) goto LABEL_20;\n LABEL_7:\n if (++a1 == (const char *)v3) return v2 == -1;\n } else {\n if (v4 != 123) {\n if (v4 == 125) goto LABEL_12;\n goto LABEL_7;\n }\n LABEL_20:\n ++v2;\n ++a1;\n v8[v2] = v4;\n if (a1 == (const char *)v3) return v2 == -1;\n }\n }\n }\n return 1;\n}" + }, + { + "index": 772, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* test_str, int K) {\n char temp_copy[1000];\n strncpy(temp_copy, test_str, sizeof(temp_copy));\n temp_copy[sizeof(temp_copy) - 1] = '\\0';\n char* res = malloc(strlen(test_str) + 1);\n if (!res) {\n perror(\"malloc failed\");\n exit(EXIT_FAILURE);\n }\n res[0] = '\\0';\n char* token = strtok(temp_copy, \" \");\n while (token != NULL) {\n if ((int)strlen(token) != K) {\n strcat(res, token);\n strcat(res, \" \");\n }\n token = strtok(NULL, \" \");\n }\n size_t len = strlen(res);\n if (len > 0 && res[len - 1] == ' ') {\n res[len - 1] = '\\0';\n }\n return res;\n}", + "test": "int main() {\n\n char* result1 = func0(\"The person is most value tet\", 3);\n\n assert(strcmp(result1, \"person is most value\") == 0);\n\n free(result1);\n\n\n\n char* result2 = func0(\"If you told me about this ok\", 4);\n\n assert(strcmp(result2, \"If you me about ok\") == 0);\n\n free(result2);\n\n\n\n char* result3 = func0(\"Forces of darkeness is come into the play\", 4);\n\n assert(strcmp(result3, \"Forces of darkeness is the\") == 0);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x420,%rsp\nmov %rdi,-0x418(%rbp)\nmov %esi,-0x41c(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmov -0x418(%rbp),%rcx\nlea -0x3f0(%rbp),%rax\nmov $0x3e8,%edx\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 1100 \nmovb $0x0,-0x9(%rbp)\nmov -0x418(%rbp),%rax\nmov %rax,%rdi\ncallq 1110 \nadd $0x1,%rax\nmov %rax,%rdi\ncallq 1150 \nmov %rax,-0x400(%rbp)\ncmpq $0x0,-0x400(%rbp)\njne 1318 \nlea 0xcff(%rip),%rdi\ncallq 1160 \nmov $0x1,%edi\ncallq 1190 \nmov -0x400(%rbp),%rax\nmovb $0x0,(%rax)\nlea -0x3f0(%rbp),%rax\nlea 0xce6(%rip),%rsi\nmov %rax,%rdi\ncallq 1170 \nmov %rax,-0x408(%rbp)\njmp 13bd \nmov -0x408(%rbp),%rax\nmov %rax,%rdi\ncallq 1110 \ncmp %eax,-0x41c(%rbp)\nje 13a5 \nmov -0x408(%rbp),%rdx\nmov -0x400(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1180 \nmov -0x400(%rbp),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nmov -0x400(%rbp),%rax\nadd %rdx,%rax\nmovw $0x20,(%rax)\nlea 0xc6a(%rip),%rsi\nmov $0x0,%edi\ncallq 1170 \nmov %rax,-0x408(%rbp)\ncmpq $0x0,-0x408(%rbp)\njne 1341 \nmov -0x400(%rbp),%rax\nmov %rax,%rdi\ncallq 1110 \nmov %rax,-0x3f8(%rbp)\ncmpq $0x0,-0x3f8(%rbp)\nje 141f \nmov -0x3f8(%rbp),%rax\nlea -0x1(%rax),%rdx\nmov -0x400(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x20,%al\njne 141f \nmov -0x3f8(%rbp),%rax\nlea -0x1(%rax),%rdx\nmov -0x400(%rbp),%rax\nadd %rdx,%rax\nmovb $0x0,(%rax)\nmov -0x400(%rbp),%rax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 143a \ncallq 1120 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 420h\nmov [rbp+src], rdi\nmov [rbp+var_41C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rcx, [rbp+src]\nlea rax, [rbp+dest]\nmov edx, 3E8h; n\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strncpy\nmov [rbp+var_9], 0\nmov rax, [rbp+src]\nmov rdi, rax; s\ncall _strlen\nadd rax, 1\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_400], rax\ncmp [rbp+var_400], 0\njnz short loc_131B\nlea rax, s; \"malloc failed\"\nmov rdi, rax; s\ncall _perror\nmov edi, 1; status\ncall _exit\nloc_131B:\nmov rax, [rbp+var_400]\nmov byte ptr [rax], 0\nlea rax, [rbp+dest]\nlea rdx, delim; \" \"\nmov rsi, rdx; delim\nmov rdi, rax; s\ncall _strtok\nmov [rbp+s], rax\njmp short loc_13B3\nloc_1347:\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp [rbp+var_41C], eax\njz short loc_1398\nmov rdx, [rbp+s]\nmov rax, [rbp+var_400]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\nmov rax, [rbp+var_400]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+var_400]\nadd rax, rdx\nmov word ptr [rax], 20h ; ' '\nloc_1398:\nlea rax, delim; \" \"\nmov rsi, rax; delim\nmov edi, 0; s\ncall _strtok\nmov [rbp+s], rax\nloc_13B3:\ncmp [rbp+s], 0\njnz short loc_1347\nmov rax, [rbp+var_400]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_3F8], rax\ncmp [rbp+var_3F8], 0\njz short loc_1411\nmov rax, [rbp+var_3F8]\nlea rdx, [rax-1]\nmov rax, [rbp+var_400]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njnz short loc_1411\nmov rax, [rbp+var_3F8]\nlea rdx, [rax-1]\nmov rax, [rbp+var_400]\nadd rax, rdx\nmov byte ptr [rax], 0\nloc_1411:\nmov rax, [rbp+var_400]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_142C\ncall ___stack_chk_fail\nlocret_142C:\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(const char *a1, int a2)\n{\n size_t v2; // rax\n const char *s; // [rsp+18h] [rbp-408h]\n char *v5; // [rsp+20h] [rbp-400h]\n size_t v6; // [rsp+28h] [rbp-3F8h]\n char dest[1000]; // [rsp+30h] [rbp-3F0h] BYREF\n unsigned __int64 v8; // [rsp+418h] [rbp-8h]\n\n v8 = __readfsqword(0x28u);\n strncpy(dest, a1, 0x3E8uLL);\n dest[999] = 0;\n v2 = strlen(a1);\n v5 = (char *)malloc(v2 + 1);\n if ( !v5 )\n {\n perror(\"malloc failed\");\n exit(1);\n }\n *v5 = 0;\n for ( s = strtok(dest, \" \"); s; s = strtok(0LL, \" \") )\n {\n if ( a2 != (unsigned int)strlen(s) )\n {\n strcat(v5, s);\n *(_WORD *)&v5[strlen(v5)] = 32;\n }\n }\n v6 = strlen(v5);\n if ( v6 && v5[v6 - 1] == 32 )\n v5[v6 - 1] = 0;\n return v5;\n}", + "ida_strip_asm": "sub_1289:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 420h\nmov [rbp+src], rdi\nmov [rbp+var_41C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rcx, [rbp+src]\nlea rax, [rbp+dest]\nmov edx, 3E8h; n\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strncpy\nmov [rbp+var_9], 0\nmov rax, [rbp+src]\nmov rdi, rax; s\ncall _strlen\nadd rax, 1\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_400], rax\ncmp [rbp+var_400], 0\njnz short loc_131B\nlea rax, s; \"malloc failed\"\nmov rdi, rax; s\ncall _perror\nmov edi, 1; status\ncall _exit\nloc_131B:\nmov rax, [rbp+var_400]\nmov byte ptr [rax], 0\nlea rax, [rbp+dest]\nlea rdx, delim; \" \"\nmov rsi, rdx; delim\nmov rdi, rax; s\ncall _strtok\nmov [rbp+s], rax\njmp short loc_13B3\nloc_1347:\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp [rbp+var_41C], eax\njz short loc_1398\nmov rdx, [rbp+s]\nmov rax, [rbp+var_400]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\nmov rax, [rbp+var_400]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+var_400]\nadd rax, rdx\nmov word ptr [rax], 20h ; ' '\nloc_1398:\nlea rax, delim; \" \"\nmov rsi, rax; delim\nmov edi, 0; s\ncall _strtok\nmov [rbp+s], rax\nloc_13B3:\ncmp [rbp+s], 0\njnz short loc_1347\nmov rax, [rbp+var_400]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_3F8], rax\ncmp [rbp+var_3F8], 0\njz short loc_1411\nmov rax, [rbp+var_3F8]\nlea rdx, [rax-1]\nmov rax, [rbp+var_400]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njnz short loc_1411\nmov rax, [rbp+var_3F8]\nlea rdx, [rax-1]\nmov rax, [rbp+var_400]\nadd rax, rdx\nmov byte ptr [rax], 0\nloc_1411:\nmov rax, [rbp+var_400]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_142C\ncall ___stack_chk_fail\nlocret_142C:\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1289(const char *a1, int a2)\n{\n size_t v2; // rax\n const char *s; // [rsp+18h] [rbp-408h]\n char *v5; // [rsp+20h] [rbp-400h]\n size_t v6; // [rsp+28h] [rbp-3F8h]\n char dest[1000]; // [rsp+30h] [rbp-3F0h] BYREF\n unsigned __int64 v8; // [rsp+418h] [rbp-8h]\n\n v8 = __readfsqword(0x28u);\n strncpy(dest, a1, 0x3E8uLL);\n dest[999] = 0;\n v2 = strlen(a1);\n v5 = (char *)malloc(v2 + 1);\n if ( !v5 )\n {\n perror(\"malloc failed\");\n exit(1);\n }\n *v5 = 0;\n for ( s = strtok(dest, \" \"); s; s = strtok(0LL, \" \") )\n {\n if ( a2 != (unsigned int)strlen(s) )\n {\n strcat(v5, s);\n *(_WORD *)&v5[strlen(v5)] = 32;\n }\n }\n v6 = strlen(v5);\n if ( v6 && v5[v6 - 1] == 32 )\n v5[v6 - 1] = 0;\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1289(const char *a1, int a2) {\n unsigned int v2;\n const char *s;\n char *v5;\n unsigned int v6;\n char dest[1000];\n unsigned long long v8;\n v8 = __readfsqword(40u);\n strncpy(dest, a1, 1000uLL);\n dest[999] = 0;\n v2 = strlen(a1);\n v5 = (char *)malloc(v2 + 1);\n if (!v5) {\n perror(\"malloc failed\");\n exit(1);\n }\n *v5 = 0;\n for (s = strtok(dest, \" \"); s; s = strtok(0LL, \" \")) {\n if (a2 != (unsigned int)strlen(s)) {\n strcat(v5, s);\n *(unsigned short *)&v5[strlen(v5)] = 32;\n }\n }\n v6 = strlen(v5);\n if (v6 && v5[v6 - 1] == 32) v5[v6 - 1] = 0;\n return v5;\n}", + "ida_pseudo_norm": "char *func0(const char *a1, int a2) {\n unsigned int v2;\n const char *s;\n char *v5;\n unsigned int v6;\n char dest[1000];\n unsigned long long v8;\n v8 = __readfsqword(40u);\n strncpy(dest, a1, 1000uLL);\n dest[999] = 0;\n v2 = strlen(a1);\n v5 = (char *)malloc(v2 + 1);\n if (!v5) {\n perror(\"malloc failed\");\n exit(1);\n }\n *v5 = 0;\n for (s = strtok(dest, \" \"); s; s = strtok(0LL, \" \")) {\n if (a2 != (unsigned int)strlen(s)) {\n strcat(v5, s);\n *(unsigned short *)&v5[strlen(v5)] = 32;\n }\n }\n v6 = strlen(v5);\n if (v6 && v5[v6 - 1] == 32) v5[v6 - 1] = 0;\n return v5;\n}" + }, + { + "index": 772, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* test_str, int K) {\n char temp_copy[1000];\n strncpy(temp_copy, test_str, sizeof(temp_copy));\n temp_copy[sizeof(temp_copy) - 1] = '\\0';\n char* res = malloc(strlen(test_str) + 1);\n if (!res) {\n perror(\"malloc failed\");\n exit(EXIT_FAILURE);\n }\n res[0] = '\\0';\n char* token = strtok(temp_copy, \" \");\n while (token != NULL) {\n if ((int)strlen(token) != K) {\n strcat(res, token);\n strcat(res, \" \");\n }\n token = strtok(NULL, \" \");\n }\n size_t len = strlen(res);\n if (len > 0 && res[len - 1] == ' ') {\n res[len - 1] = '\\0';\n }\n return res;\n}", + "test": "int main() {\n\n char* result1 = func0(\"The person is most value tet\", 3);\n\n assert(strcmp(result1, \"person is most value\") == 0);\n\n free(result1);\n\n\n\n char* result2 = func0(\"If you told me about this ok\", 4);\n\n assert(strcmp(result2, \"If you me about ok\") == 0);\n\n free(result2);\n\n\n\n char* result3 = func0(\"Forces of darkeness is come into the play\", 4);\n\n assert(strcmp(result3, \"Forces of darkeness is the\") == 0);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nsub $0x3f0,%rsp\nmov %rdi,%rbx\nmov %esi,%r12d\nmov %fs:0x28,%rax\nmov %rax,0x3e8(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nmov $0x3e8,%edx\nmov %rbx,%rsi\ncallq 10e0 \nmovb $0x0,0x3e7(%rsp)\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nmov %rbx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rdi\nnot %rdi\ncallq 1110 \ntest %rax,%rax\nje 12d0 \nmov %rax,%rbx\nmovb $0x0,(%rax)\nmov %rsp,%rdi\nlea 0xd58(%rip),%rsi\ncallq 1130 \nmov %rax,%rsi\ntest %rax,%rax\nje 133f \nmov $0xffffffffffffffff,%rbp\njmp 1321 \nlea 0xd2d(%rip),%rdi\ncallq 1120 \nmov $0x1,%edi\ncallq 1150 \nmov %rbx,%rdi\ncallq 1140 \nmov $0x0,%eax\nmov %rbp,%rcx\nmov %rbx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nmovw $0x20,-0x1(%rbx,%rax,1)\nlea 0xd03(%rip),%rsi\nmov $0x0,%edi\ncallq 1130 \nmov %rax,%rsi\ntest %rax,%rax\nje 133f \nmov $0x0,%eax\nmov %rbp,%rcx\nmov %rsi,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nsub $0x1,%rax\ncmp %eax,%r12d\nje 1308 \njmp 12e6 \nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nmov %rbx,%rdi\nrepnz scas %es:(%rdi),%al\nnot %rcx\nsub $0x1,%rcx\nje 1363 \nlea -0x1(%rbx,%rcx,1),%rax\ncmpb $0x20,(%rax)\nje 1385 \nmov 0x3e8(%rsp),%rax\nxor %fs:0x28,%rax\njne 138a \nmov %rbx,%rax\nadd $0x3f0,%rsp\npop %rbx\npop %rbp\npop %r12\nretq\nmovb $0x0,(%rax)\njmp 1363 \ncallq 10f0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 3F0h\nmov rbx, rdi\nmov r13d, esi\nmov rax, fs:28h\nmov [rsp+418h+var_30], rax\nxor eax, eax\nmov rdi, rsp; dest\nmov edx, 3E8h; n\nmov rsi, rbx; src\ncall _strncpy\nmov [rsp+418h+var_31], 0\nmov rdi, rbx; s\ncall _strlen\nlea r12, [rax+1]\nmov rdi, r12; size\ncall _malloc\ntest rax, rax\njz short loc_130C\nmov rbp, rax\nmov byte ptr [rax], 0\nmov rdi, rsp; s\nlea rsi, delim; \" \"\ncall _strtok\nmov rbx, rax\ntest rax, rax\njz short loc_1362\nlea r14, delim; \" \"\njmp short loc_1337\nloc_130C:\nlea rdi, s; \"malloc failed\"\ncall _perror\nmov edi, 1; status\ncall _exit\nloc_1322:\nmov rsi, r14; delim\nmov edi, 0; s\ncall _strtok\nmov rbx, rax\ntest rax, rax\njz short loc_1362\nloc_1337:\nmov rdi, rbx; s\ncall _strlen\ncmp r13d, eax\njz short loc_1322\nmov rdx, r12\nmov rsi, rbx\nmov rdi, rbp\ncall ___strcat_chk\nmov rdx, r12\nmov rsi, r14\nmov rdi, rbp\ncall ___strcat_chk\njmp short loc_1322\nloc_1362:\nmov rdi, rbp; s\ncall _strlen\ntest rax, rax\njz short loc_1379\nlea rax, [rbp+rax-1]\ncmp byte ptr [rax], 20h ; ' '\njz short loc_139F\nloc_1379:\nmov rax, [rsp+418h+var_30]\nsub rax, fs:28h\njnz short loc_13A4\nmov rax, rbp\nadd rsp, 3F0h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_139F:\nmov byte ptr [rax], 0\njmp short loc_1379\nloc_13A4:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *s, int a2)\n{\n size_t v2; // r12\n const char *v3; // rax\n const char *v4; // rbp\n char *i; // rbx\n size_t v6; // rax\n const char *v7; // rax\n char v9[1000]; // [rsp+0h] [rbp-418h] BYREF\n unsigned __int64 v10; // [rsp+3E8h] [rbp-30h]\n\n v10 = __readfsqword(0x28u);\n strncpy(v9, s, 0x3E8uLL);\n v9[999] = 0;\n v2 = strlen(s) + 1;\n v3 = (const char *)malloc(v2);\n if ( !v3 )\n {\n perror(\"malloc failed\");\n exit(1);\n }\n v4 = v3;\n *v3 = 0;\n for ( i = strtok(v9, \" \"); i; i = strtok(0LL, \" \") )\n {\n if ( a2 != (unsigned int)strlen(i) )\n {\n __strcat_chk(v4, i, v2);\n __strcat_chk(v4, \" \", v2);\n }\n }\n v6 = strlen(v4);\n if ( v6 )\n {\n v7 = &v4[v6 - 1];\n if ( *v7 == 32 )\n *v7 = 0;\n }\n return v4;\n}", + "ida_strip_asm": "sub_1289:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 3F0h\nmov rbx, rdi\nmov r13d, esi\nmov rax, fs:28h\nmov [rsp+418h+var_30], rax\nxor eax, eax\nmov rdi, rsp; dest\nmov edx, 3E8h; n\nmov rsi, rbx; src\ncall _strncpy\nmov [rsp+418h+var_31], 0\nmov rdi, rbx; s\ncall _strlen\nlea r12, [rax+1]\nmov rdi, r12; size\ncall _malloc\ntest rax, rax\njz short loc_130C\nmov rbp, rax\nmov byte ptr [rax], 0\nmov rdi, rsp; s\nlea rsi, delim; \" \"\ncall _strtok\nmov rbx, rax\ntest rax, rax\njz short loc_1362\nlea r14, delim; \" \"\njmp short loc_1337\nloc_130C:\nlea rdi, s; \"malloc failed\"\ncall _perror\nmov edi, 1; status\ncall _exit\nloc_1322:\nmov rsi, r14; delim\nmov edi, 0; s\ncall _strtok\nmov rbx, rax\ntest rax, rax\njz short loc_1362\nloc_1337:\nmov rdi, rbx; s\ncall _strlen\ncmp r13d, eax\njz short loc_1322\nmov rdx, r12\nmov rsi, rbx\nmov rdi, rbp\ncall ___strcat_chk\nmov rdx, r12\nmov rsi, r14\nmov rdi, rbp\ncall ___strcat_chk\njmp short loc_1322\nloc_1362:\nmov rdi, rbp; s\ncall _strlen\ntest rax, rax\njz short loc_1379\nlea rax, [rbp+rax-1]\ncmp byte ptr [rax], 20h ; ' '\njz short loc_139F\nloc_1379:\nmov rax, [rsp+418h+var_30]\nsub rax, fs:28h\njnz short loc_13A4\nmov rax, rbp\nadd rsp, 3F0h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_139F:\nmov byte ptr [rax], 0\njmp short loc_1379\nloc_13A4:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_1289(char *s, int a2)\n{\n size_t v2; // r12\n const char *v3; // rax\n const char *v4; // rbp\n char *i; // rbx\n size_t v6; // rax\n const char *v7; // rax\n char v9[1000]; // [rsp+0h] [rbp-418h] BYREF\n unsigned __int64 v10; // [rsp+3E8h] [rbp-30h]\n\n v10 = __readfsqword(0x28u);\n strncpy(v9, s, 0x3E8uLL);\n v9[999] = 0;\n v2 = strlen(s) + 1;\n v3 = (const char *)malloc(v2);\n if ( !v3 )\n {\n perror(\"malloc failed\");\n exit(1);\n }\n v4 = v3;\n *v3 = 0;\n for ( i = strtok(v9, \" \"); i; i = strtok(0LL, \" \") )\n {\n if ( a2 != (unsigned int)strlen(i) )\n {\n __strcat_chk(v4, i, v2);\n __strcat_chk(v4, \" \", v2);\n }\n }\n v6 = strlen(v4);\n if ( v6 )\n {\n v7 = &v4[v6 - 1];\n if ( *v7 == 32 )\n *v7 = 0;\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1289(char *s, int a2) {\n unsigned int v2;\n const char *v3;\n const char *v4;\n char *i;\n unsigned int v6;\n const char *v7;\n char v9[1000];\n unsigned long long v10;\n v10 = __readfsqword(40u);\n strncpy(v9, s, 1000uLL);\n v9[999] = 0;\n v2 = strlen(s) + 1;\n v3 = (const char *)malloc(v2);\n if (!v3) {\n perror(\"malloc failed\");\n exit(1);\n }\n v4 = v3;\n *v3 = 0;\n for (i = strtok(v9, \" \"); i; i = strtok(0LL, \" \")) {\n if (a2 != (unsigned int)strlen(i)) {\n __strcat_chk(v4, i, v2);\n __strcat_chk(v4, \" \", v2);\n }\n }\n v6 = strlen(v4);\n if (v6) {\n v7 = &v4[v6 - 1];\n if (*v7 == 32) *v7 = 0;\n }\n return v4;\n}", + "ida_pseudo_norm": "const char *func0(char *s, int a2) {\n unsigned int v2;\n const char *v3;\n const char *v4;\n char *i;\n unsigned int v6;\n const char *v7;\n char v9[1000];\n unsigned long long v10;\n v10 = __readfsqword(40u);\n strncpy(v9, s, 1000uLL);\n v9[999] = 0;\n v2 = strlen(s) + 1;\n v3 = (const char *)malloc(v2);\n if (!v3) {\n perror(\"malloc failed\");\n exit(1);\n }\n v4 = v3;\n *v3 = 0;\n for (i = strtok(v9, \" \"); i; i = strtok(0LL, \" \")) {\n if (a2 != (unsigned int)strlen(i)) {\n __strcat_chk(v4, i, v2);\n __strcat_chk(v4, \" \", v2);\n }\n }\n v6 = strlen(v4);\n if (v6) {\n v7 = &v4[v6 - 1];\n if (*v7 == 32) *v7 = 0;\n }\n return v4;\n}" + }, + { + "index": 772, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* test_str, int K) {\n char temp_copy[1000];\n strncpy(temp_copy, test_str, sizeof(temp_copy));\n temp_copy[sizeof(temp_copy) - 1] = '\\0';\n char* res = malloc(strlen(test_str) + 1);\n if (!res) {\n perror(\"malloc failed\");\n exit(EXIT_FAILURE);\n }\n res[0] = '\\0';\n char* token = strtok(temp_copy, \" \");\n while (token != NULL) {\n if ((int)strlen(token) != K) {\n strcat(res, token);\n strcat(res, \" \");\n }\n token = strtok(NULL, \" \");\n }\n size_t len = strlen(res);\n if (len > 0 && res[len - 1] == ' ') {\n res[len - 1] = '\\0';\n }\n return res;\n}", + "test": "int main() {\n\n char* result1 = func0(\"The person is most value tet\", 3);\n\n assert(strcmp(result1, \"person is most value\") == 0);\n\n free(result1);\n\n\n\n char* result2 = func0(\"If you told me about this ok\", 4);\n\n assert(strcmp(result2, \"If you me about ok\") == 0);\n\n free(result2);\n\n\n\n char* result3 = func0(\"Forces of darkeness is come into the play\", 4);\n\n assert(strcmp(result3, \"Forces of darkeness is the\") == 0);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov $0x3e8,%edx\npush %r12\npush %rbp\nmov %rdi,%rbp\npush %rbx\nmov %esi,%ebx\nmov %rdi,%rsi\nsub $0x3f8,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x3e8(%rsp)\nxor %eax,%eax\nmov %rsp,%r13\nmov %r13,%rdi\ncallq 10f0 \nmov %rbp,%rdi\nmovb $0x0,0x3e7(%rsp)\ncallq 1110 \nlea 0x1(%rax),%rdi\ncallq 1140 \ntest %rax,%rax\nje 14fa \nmovb $0x0,(%rax)\nmov %r13,%rdi\nlea 0xc17(%rip),%rsi\nmov %rax,%r12\ncallq 1160 \nmov %rax,%r13\ntest %rax,%rax\nje 147f \nlea 0xc00(%rip),%rbp\nnopw 0x0(%rax,%rax,1)\nmov %r13,%rdi\ncallq 1110 \ncmp %eax,%ebx\nje 146d \nmov %r12,%rdi\nmov (%rdi),%eax\nadd $0x4,%rdi\nlea -0x1010101(%rax),%edx\nnot %eax\nand %eax,%edx\nand $0x80808080,%edx\nje 1427 \nmov %edx,%eax\nmov %r13,%rsi\nshr $0x10,%eax\ntest $0x8080,%edx\ncmove %eax,%edx\nlea 0x2(%rdi),%rax\ncmove %rax,%rdi\nmov %edx,%eax\nadd %dl,%al\nsbb $0x3,%rdi\ncallq 1100 \nmov $0x20,%edx\nmov %dx,(%rax)\nmov %rbp,%rsi\nxor %edi,%edi\ncallq 1160 \nmov %rax,%r13\ntest %rax,%rax\njne 1418 \nmov %r12,%rdx\nmov (%rdx),%ecx\nadd $0x4,%rdx\nlea -0x1010101(%rcx),%eax\nnot %ecx\nand %ecx,%eax\nand $0x80808080,%eax\nje 1482 \nmov %eax,%ecx\nshr $0x10,%ecx\ntest $0x8080,%eax\ncmove %ecx,%eax\nlea 0x2(%rdx),%rcx\ncmove %rcx,%rdx\nmov %eax,%ebx\nadd %al,%bl\nsbb $0x3,%rdx\nsub %r12,%rdx\nje 14c5 \nlea -0x1(%r12,%rdx,1),%rax\ncmpb $0x20,(%rax)\nje 14f0 \nmov 0x3e8(%rsp),%rax\nxor %fs:0x28,%rax\njne 14f5 \nadd $0x3f8,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax)\nmovb $0x0,(%rax)\njmp 14c5 \ncallq 1120 <__stack_chk_fail@plt>\nlea 0xb03(%rip),%rdi\ncallq 1150 \nmov $0x1,%edi\ncallq 1170 \n", + "ida_asm": "func0:\nendbr64\npush r15\nmov edx, 3E8h; n\npush r14\nmov r14d, esi\nmov rsi, rdi; src\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 3F8h\nmov rax, fs:28h\nmov [rsp+428h+var_40], rax\nxor eax, eax\nmov r15, rsp\nmov rdi, r15; dest\ncall _strncpy\nmov rdi, rbx; s\nmov [rsp+428h+var_41], 0\ncall _strlen\nlea r13, [rax+1]\nmov rdi, r13; size\ncall _malloc\ntest rax, rax\njz func0_cold\nmov byte ptr [rax], 0\nlea r12, delim; \" \"\nmov rdi, r15; s\nmov rbp, rax\nmov rsi, r12; delim\ncall _strtok\nmov rbx, rax\ntest rax, rax\njz short loc_14B0\nnop word ptr [rax+rax+00000000h]\nloc_1460:\nmov rdi, rbx; s\ncall _strlen\ncmp r14d, eax\njz short loc_149E\nmov rdi, rbp; s\ncall _strlen\nmov rdx, r13\nmov rsi, rbx\nlea rdi, [rbp+rax+0]\ncall ___stpcpy_chk\nmov rcx, rbp\nmov edx, 2\nmov rsi, r12\nsub rcx, rax\nmov rdi, rax\nadd rcx, r13\ncall ___memcpy_chk\nloc_149E:\nmov rsi, r12; delim\nxor edi, edi; s\ncall _strtok\nmov rbx, rax\ntest rax, rax\njnz short loc_1460\nloc_14B0:\nmov rdi, rbp; s\ncall _strlen\ntest rax, rax\njz short loc_14C7\nlea rax, [rbp+rax-1]\ncmp byte ptr [rax], 20h ; ' '\njz short loc_14F0\nloc_14C7:\nmov rax, [rsp+428h+var_40]\nsub rax, fs:28h\njnz short loc_14F5\nadd rsp, 3F8h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14F0:\nmov byte ptr [rax], 0\njmp short loc_14C7\nloc_14F5:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *s, int a2)\n{\n size_t v2; // r13\n const char *v3; // rax\n const char *v4; // rbp\n char *i; // rbx\n size_t v6; // rax\n __int64 v7; // rax\n size_t v8; // rax\n const char *v9; // rax\n char v11[1000]; // [rsp+0h] [rbp-428h] BYREF\n unsigned __int64 v12; // [rsp+3E8h] [rbp-40h]\n\n v12 = __readfsqword(0x28u);\n strncpy(v11, s, 0x3E8uLL);\n v11[999] = 0;\n v2 = strlen(s) + 1;\n v3 = (const char *)malloc(v2);\n if ( !v3 )\n func0_cold();\n *v3 = 0;\n v4 = v3;\n for ( i = strtok(v11, \" \"); i; i = strtok(0LL, \" \") )\n {\n if ( a2 != (unsigned int)strlen(i) )\n {\n v6 = strlen(v4);\n v7 = __stpcpy_chk(&v4[v6], i, v2);\n __memcpy_chk(v7, \" \", 2LL, &v4[v2 - v7]);\n }\n }\n v8 = strlen(v4);\n if ( v8 )\n {\n v9 = &v4[v8 - 1];\n if ( *v9 == 32 )\n *v9 = 0;\n }\n return v4;\n}", + "ida_strip_asm": "sub_13D0:\nendbr64\npush r15\nmov edx, 3E8h; n\npush r14\nmov r14d, esi\nmov rsi, rdi; src\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 3F8h\nmov rax, fs:28h\nmov [rsp+428h+var_40], rax\nxor eax, eax\nmov r15, rsp\nmov rdi, r15; dest\ncall _strncpy\nmov rdi, rbx; s\nmov [rsp+428h+var_41], 0\ncall _strlen\nlea r13, [rax+1]\nmov rdi, r13; size\ncall _malloc\ntest rax, rax\njz loc_11C0\nmov byte ptr [rax], 0\nlea r12, delim; \" \"\nmov rdi, r15; s\nmov rbp, rax\nmov rsi, r12; delim\ncall _strtok\nmov rbx, rax\ntest rax, rax\njz short loc_14B0\nnop word ptr [rax+rax+00000000h]\nloc_1460:\nmov rdi, rbx; s\ncall _strlen\ncmp r14d, eax\njz short loc_149E\nmov rdi, rbp; s\ncall _strlen\nmov rdx, r13\nmov rsi, rbx\nlea rdi, [rbp+rax+0]\ncall ___stpcpy_chk\nmov rcx, rbp\nmov edx, 2\nmov rsi, r12\nsub rcx, rax\nmov rdi, rax\nadd rcx, r13\ncall ___memcpy_chk\nloc_149E:\nmov rsi, r12; delim\nxor edi, edi; s\ncall _strtok\nmov rbx, rax\ntest rax, rax\njnz short loc_1460\nloc_14B0:\nmov rdi, rbp; s\ncall _strlen\ntest rax, rax\njz short loc_14C7\nlea rax, [rbp+rax-1]\ncmp byte ptr [rax], 20h ; ' '\njz short loc_14F0\nloc_14C7:\nmov rax, [rsp+428h+var_40]\nsub rax, fs:28h\njnz short loc_14F5\nadd rsp, 3F8h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14F0:\nmov byte ptr [rax], 0\njmp short loc_14C7\nloc_14F5:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_13D0(char *s, int a2)\n{\n size_t v2; // r13\n const char *v3; // rax\n const char *v4; // rbp\n char *i; // rbx\n size_t v6; // rax\n __int64 v7; // rax\n size_t v8; // rax\n const char *v9; // rax\n char v11[1000]; // [rsp+0h] [rbp-428h] BYREF\n unsigned __int64 v12; // [rsp+3E8h] [rbp-40h]\n\n v12 = __readfsqword(0x28u);\n strncpy(v11, s, 0x3E8uLL);\n v11[999] = 0;\n v2 = strlen(s) + 1;\n v3 = (const char *)malloc(v2);\n if ( !v3 )\n {\n perror(\"malloc failed\");\n exit(1);\n }\n *v3 = 0;\n v4 = v3;\n for ( i = strtok(v11, \" \"); i; i = strtok(0LL, \" \") )\n {\n if ( a2 != (unsigned int)strlen(i) )\n {\n v6 = strlen(v4);\n v7 = __stpcpy_chk(&v4[v6], i, v2);\n __memcpy_chk(v7, \" \", 2LL, &v4[v2 - v7]);\n }\n }\n v8 = strlen(v4);\n if ( v8 )\n {\n v9 = &v4[v8 - 1];\n if ( *v9 == 32 )\n *v9 = 0;\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_13D0(char *s, int a2) {\n unsigned int v2;\n const char *v3;\n const char *v4;\n char *i;\n unsigned int v6;\n long long v7;\n unsigned int v8;\n const char *v9;\n char v11[1000];\n unsigned long long v12;\n v12 = __readfsqword(40u);\n strncpy(v11, s, 1000uLL);\n v11[999] = 0;\n v2 = strlen(s) + 1;\n v3 = (const char *)malloc(v2);\n if (!v3) {\n perror(\"malloc failed\");\n exit(1);\n }\n *v3 = 0;\n v4 = v3;\n for (i = strtok(v11, \" \"); i; i = strtok(0LL, \" \")) {\n if (a2 != (unsigned int)strlen(i)) {\n v6 = strlen(v4);\n v7 = __stpcpy_chk(&v4[v6], i, v2);\n __memcpy_chk(v7, \" \", 2LL, &v4[v2 - v7]);\n }\n }\n v8 = strlen(v4);\n if (v8) {\n v9 = &v4[v8 - 1];\n if (*v9 == 32) *v9 = 0;\n }\n return v4;\n}", + "ida_pseudo_norm": "const char *func0(char *s, int a2) {\n unsigned int v2;\n const char *v3;\n const char *v4;\n char *i;\n unsigned int v6;\n long long v7;\n unsigned int v8;\n const char *v9;\n char v11[1000];\n unsigned long long v12;\n v12 = __readfsqword(40u);\n strncpy(v11, s, 1000uLL);\n v11[999] = 0;\n v2 = strlen(s) + 1;\n v3 = (const char *)malloc(v2);\n if (!v3) func0_cold();\n *v3 = 0;\n v4 = v3;\n for (i = strtok(v11, \" \"); i; i = strtok(0LL, \" \")) {\n if (a2 != (unsigned int)strlen(i)) {\n v6 = strlen(v4);\n v7 = __stpcpy_chk(&v4[v6], i, v2);\n __memcpy_chk(v7, \" \", 2LL, &v4[v2 - v7]);\n }\n }\n v8 = strlen(v4);\n if (v8) {\n v9 = &v4[v8 - 1];\n if (*v9 == 32) *v9 = 0;\n }\n return v4;\n}" + }, + { + "index": 772, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* test_str, int K) {\n char temp_copy[1000];\n strncpy(temp_copy, test_str, sizeof(temp_copy));\n temp_copy[sizeof(temp_copy) - 1] = '\\0';\n char* res = malloc(strlen(test_str) + 1);\n if (!res) {\n perror(\"malloc failed\");\n exit(EXIT_FAILURE);\n }\n res[0] = '\\0';\n char* token = strtok(temp_copy, \" \");\n while (token != NULL) {\n if ((int)strlen(token) != K) {\n strcat(res, token);\n strcat(res, \" \");\n }\n token = strtok(NULL, \" \");\n }\n size_t len = strlen(res);\n if (len > 0 && res[len - 1] == ' ') {\n res[len - 1] = '\\0';\n }\n return res;\n}", + "test": "int main() {\n\n char* result1 = func0(\"The person is most value tet\", 3);\n\n assert(strcmp(result1, \"person is most value\") == 0);\n\n free(result1);\n\n\n\n char* result2 = func0(\"If you told me about this ok\", 4);\n\n assert(strcmp(result2, \"If you me about ok\") == 0);\n\n free(result2);\n\n\n\n char* result3 = func0(\"Forces of darkeness is come into the play\", 4);\n\n assert(strcmp(result3, \"Forces of darkeness is the\") == 0);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov $0x3e8,%edx\npush %r12\npush %rbp\nmov %rdi,%rbp\npush %rbx\nmov %esi,%ebx\nmov %rdi,%rsi\nsub $0x3f8,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x3e8(%rsp)\nxor %eax,%eax\nmov %rsp,%r13\nmov %r13,%rdi\ncallq 10f0 \nmov %rbp,%rdi\nmovb $0x0,0x3e7(%rsp)\ncallq 1110 \nlea 0x1(%rax),%rdi\ncallq 1140 \ntest %rax,%rax\nje 14fa \nmovb $0x0,(%rax)\nmov %r13,%rdi\nlea 0xc17(%rip),%rsi\nmov %rax,%r12\ncallq 1160 \nmov %rax,%r13\ntest %rax,%rax\nje 147f \nlea 0xc00(%rip),%rbp\nnopw 0x0(%rax,%rax,1)\nmov %r13,%rdi\ncallq 1110 \ncmp %eax,%ebx\nje 146d \nmov %r12,%rdi\nmov (%rdi),%eax\nadd $0x4,%rdi\nlea -0x1010101(%rax),%edx\nnot %eax\nand %eax,%edx\nand $0x80808080,%edx\nje 1427 \nmov %edx,%eax\nmov %r13,%rsi\nshr $0x10,%eax\ntest $0x8080,%edx\ncmove %eax,%edx\nlea 0x2(%rdi),%rax\ncmove %rax,%rdi\nmov %edx,%eax\nadd %dl,%al\nsbb $0x3,%rdi\ncallq 1100 \nmov $0x20,%edx\nmov %dx,(%rax)\nmov %rbp,%rsi\nxor %edi,%edi\ncallq 1160 \nmov %rax,%r13\ntest %rax,%rax\njne 1418 \nmov %r12,%rdx\nmov (%rdx),%ecx\nadd $0x4,%rdx\nlea -0x1010101(%rcx),%eax\nnot %ecx\nand %ecx,%eax\nand $0x80808080,%eax\nje 1482 \nmov %eax,%ecx\nshr $0x10,%ecx\ntest $0x8080,%eax\ncmove %ecx,%eax\nlea 0x2(%rdx),%rcx\ncmove %rcx,%rdx\nmov %eax,%ebx\nadd %al,%bl\nsbb $0x3,%rdx\nsub %r12,%rdx\nje 14c5 \nlea -0x1(%r12,%rdx,1),%rax\ncmpb $0x20,(%rax)\nje 14f0 \nmov 0x3e8(%rsp),%rax\nxor %fs:0x28,%rax\njne 14f5 \nadd $0x3f8,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax)\nmovb $0x0,(%rax)\njmp 14c5 \ncallq 1120 <__stack_chk_fail@plt>\nlea 0xb03(%rip),%rdi\ncallq 1150 \nmov $0x1,%edi\ncallq 1170 \n", + "ida_asm": "func0:\nendbr64\npush r15\nmov edx, 3E8h; n\npush r14\nmov r14d, esi\nmov rsi, rdi; src\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 3F8h\nmov rax, fs:28h\nmov [rsp+428h+var_40], rax\nxor eax, eax\nmov r15, rsp\nmov rdi, r15; dest\ncall _strncpy\nmov rdi, rbx; s\nmov [rsp+428h+var_41], 0\ncall _strlen\nlea r13, [rax+1]\nmov rdi, r13; size\ncall _malloc\ntest rax, rax\njz func0_cold\nmov byte ptr [rax], 0\nlea r12, delim; \" \"\nmov rdi, r15; s\nmov rbp, rax\nmov rsi, r12; delim\ncall _strtok\nmov rbx, rax\ntest rax, rax\njz short loc_14B0\nnop word ptr [rax+rax+00000000h]\nloc_1460:\nmov rdi, rbx; s\ncall _strlen\ncmp r14d, eax\njz short loc_149E\nmov rdi, rbp; s\ncall _strlen\nmov rdx, r13\nmov rsi, rbx\nlea rdi, [rbp+rax+0]\ncall ___stpcpy_chk\nmov rcx, rbp\nmov edx, 2\nmov rsi, r12\nsub rcx, rax\nmov rdi, rax\nadd rcx, r13\ncall ___memcpy_chk\nloc_149E:\nmov rsi, r12; delim\nxor edi, edi; s\ncall _strtok\nmov rbx, rax\ntest rax, rax\njnz short loc_1460\nloc_14B0:\nmov rdi, rbp; s\ncall _strlen\ntest rax, rax\njz short loc_14C7\nlea rax, [rbp+rax-1]\ncmp byte ptr [rax], 20h ; ' '\njz short loc_14F0\nloc_14C7:\nmov rax, [rsp+428h+var_40]\nsub rax, fs:28h\njnz short loc_14F5\nadd rsp, 3F8h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14F0:\nmov byte ptr [rax], 0\njmp short loc_14C7\nloc_14F5:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *s, int a2)\n{\n size_t v2; // r13\n const char *v3; // rax\n const char *v4; // rbp\n char *i; // rbx\n size_t v6; // rax\n __int64 v7; // rax\n size_t v8; // rax\n const char *v9; // rax\n char v11[1000]; // [rsp+0h] [rbp-428h] BYREF\n unsigned __int64 v12; // [rsp+3E8h] [rbp-40h]\n\n v12 = __readfsqword(0x28u);\n strncpy(v11, s, 0x3E8uLL);\n v11[999] = 0;\n v2 = strlen(s) + 1;\n v3 = (const char *)malloc(v2);\n if ( !v3 )\n func0_cold();\n *v3 = 0;\n v4 = v3;\n for ( i = strtok(v11, \" \"); i; i = strtok(0LL, \" \") )\n {\n if ( a2 != (unsigned int)strlen(i) )\n {\n v6 = strlen(v4);\n v7 = __stpcpy_chk(&v4[v6], i, v2);\n __memcpy_chk(v7, \" \", 2LL, &v4[v2 - v7]);\n }\n }\n v8 = strlen(v4);\n if ( v8 )\n {\n v9 = &v4[v8 - 1];\n if ( *v9 == 32 )\n *v9 = 0;\n }\n return v4;\n}", + "ida_strip_asm": "sub_13D0:\nendbr64\npush r15\nmov edx, 3E8h; n\npush r14\nmov r14d, esi\nmov rsi, rdi; src\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 3F8h\nmov rax, fs:28h\nmov [rsp+428h+var_40], rax\nxor eax, eax\nmov r15, rsp\nmov rdi, r15; dest\ncall _strncpy\nmov rdi, rbx; s\nmov [rsp+428h+var_41], 0\ncall _strlen\nlea r13, [rax+1]\nmov rdi, r13; size\ncall _malloc\ntest rax, rax\njz loc_11C0\nmov byte ptr [rax], 0\nlea r12, delim; \" \"\nmov rdi, r15; s\nmov rbp, rax\nmov rsi, r12; delim\ncall _strtok\nmov rbx, rax\ntest rax, rax\njz short loc_14B0\nnop word ptr [rax+rax+00000000h]\nloc_1460:\nmov rdi, rbx; s\ncall _strlen\ncmp r14d, eax\njz short loc_149E\nmov rdi, rbp; s\ncall _strlen\nmov rdx, r13\nmov rsi, rbx\nlea rdi, [rbp+rax+0]\ncall ___stpcpy_chk\nmov rcx, rbp\nmov edx, 2\nmov rsi, r12\nsub rcx, rax\nmov rdi, rax\nadd rcx, r13\ncall ___memcpy_chk\nloc_149E:\nmov rsi, r12; delim\nxor edi, edi; s\ncall _strtok\nmov rbx, rax\ntest rax, rax\njnz short loc_1460\nloc_14B0:\nmov rdi, rbp; s\ncall _strlen\ntest rax, rax\njz short loc_14C7\nlea rax, [rbp+rax-1]\ncmp byte ptr [rax], 20h ; ' '\njz short loc_14F0\nloc_14C7:\nmov rax, [rsp+428h+var_40]\nsub rax, fs:28h\njnz short loc_14F5\nadd rsp, 3F8h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14F0:\nmov byte ptr [rax], 0\njmp short loc_14C7\nloc_14F5:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_13D0(char *s, int a2)\n{\n size_t v2; // r13\n const char *v3; // rax\n const char *v4; // rbp\n char *i; // rbx\n size_t v6; // rax\n __int64 v7; // rax\n size_t v8; // rax\n const char *v9; // rax\n char v11[1000]; // [rsp+0h] [rbp-428h] BYREF\n unsigned __int64 v12; // [rsp+3E8h] [rbp-40h]\n\n v12 = __readfsqword(0x28u);\n strncpy(v11, s, 0x3E8uLL);\n v11[999] = 0;\n v2 = strlen(s) + 1;\n v3 = (const char *)malloc(v2);\n if ( !v3 )\n {\n perror(\"malloc failed\");\n exit(1);\n }\n *v3 = 0;\n v4 = v3;\n for ( i = strtok(v11, \" \"); i; i = strtok(0LL, \" \") )\n {\n if ( a2 != (unsigned int)strlen(i) )\n {\n v6 = strlen(v4);\n v7 = __stpcpy_chk(&v4[v6], i, v2);\n __memcpy_chk(v7, \" \", 2LL, &v4[v2 - v7]);\n }\n }\n v8 = strlen(v4);\n if ( v8 )\n {\n v9 = &v4[v8 - 1];\n if ( *v9 == 32 )\n *v9 = 0;\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_13D0(char *s, int a2) {\n unsigned int v2;\n const char *v3;\n const char *v4;\n char *i;\n unsigned int v6;\n long long v7;\n unsigned int v8;\n const char *v9;\n char v11[1000];\n unsigned long long v12;\n v12 = __readfsqword(40u);\n strncpy(v11, s, 1000uLL);\n v11[999] = 0;\n v2 = strlen(s) + 1;\n v3 = (const char *)malloc(v2);\n if (!v3) {\n perror(\"malloc failed\");\n exit(1);\n }\n *v3 = 0;\n v4 = v3;\n for (i = strtok(v11, \" \"); i; i = strtok(0LL, \" \")) {\n if (a2 != (unsigned int)strlen(i)) {\n v6 = strlen(v4);\n v7 = __stpcpy_chk(&v4[v6], i, v2);\n __memcpy_chk(v7, \" \", 2LL, &v4[v2 - v7]);\n }\n }\n v8 = strlen(v4);\n if (v8) {\n v9 = &v4[v8 - 1];\n if (*v9 == 32) *v9 = 0;\n }\n return v4;\n}", + "ida_pseudo_norm": "const char *func0(char *s, int a2) {\n unsigned int v2;\n const char *v3;\n const char *v4;\n char *i;\n unsigned int v6;\n long long v7;\n unsigned int v8;\n const char *v9;\n char v11[1000];\n unsigned long long v12;\n v12 = __readfsqword(40u);\n strncpy(v11, s, 1000uLL);\n v11[999] = 0;\n v2 = strlen(s) + 1;\n v3 = (const char *)malloc(v2);\n if (!v3) func0_cold();\n *v3 = 0;\n v4 = v3;\n for (i = strtok(v11, \" \"); i; i = strtok(0LL, \" \")) {\n if (a2 != (unsigned int)strlen(i)) {\n v6 = strlen(v4);\n v7 = __stpcpy_chk(&v4[v6], i, v2);\n __memcpy_chk(v7, \" \", 2LL, &v4[v2 - v7]);\n }\n }\n v8 = strlen(v4);\n if (v8) {\n v9 = &v4[v8 - 1];\n if (*v9 == 32) *v9 = 0;\n }\n return v4;\n}" + }, + { + "index": 773, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char substring[100];\n\n int start;\n\n int end;\n\n} Occurrence;\n\n\n\n", + "func": "Occurrence func0(const char *text, const char *pattern) {\n Occurrence result;\n char *pos = strstr(text, pattern);\n if (pos) {\n result.start = pos - text;\n result.end = result.start + strlen(pattern);\n strncpy(result.substring, pos, strlen(pattern));\n result.substring[strlen(pattern)] = '\\0';\n } else {\n result.substring[0] = '\\0';\n result.start = -1;\n result.end = -1;\n }\n return result;\n}", + "test": "int main() {\n\n Occurrence res1 = func0(\"python programming, python language\", \"python\");\n\n assert(strcmp(res1.substring, \"python\") == 0);\n\n assert(res1.start == 0);\n\n assert(res1.end == 6);\n\n\n\n Occurrence res2 = func0(\"python programming,programming language\", \"programming\");\n\n assert(strcmp(res2.substring, \"programming\") == 0);\n\n assert(res2.start == 7);\n\n assert(res2.end == 18);\n\n\n\n Occurrence res3 = func0(\"python programming,programming language\", \"language\");\n\n assert(strcmp(res3.substring, \"language\") == 0);\n\n assert(res3.start == 31);\n\n assert(res3.end == 39);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0xb8,%rsp\nmov %rdi,-0xa8(%rbp)\nmov %rsi,-0xb0(%rbp)\nmov %rdx,-0xb8(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmov -0xb8(%rbp),%rdx\nmov -0xb0(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10f0 \nmov %rax,-0x98(%rbp)\ncmpq $0x0,-0x98(%rbp)\nje 12b5 \nmov -0x98(%rbp),%rax\nsub -0xb0(%rbp),%rax\nmov %eax,-0x2c(%rbp)\nmov -0x2c(%rbp),%eax\nmov %eax,%ebx\nmov -0xb8(%rbp),%rax\nmov %rax,%rdi\ncallq 10b0 \nadd %ebx,%eax\nmov %eax,-0x28(%rbp)\nmov -0xb8(%rbp),%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,%rdx\nmov -0x98(%rbp),%rcx\nlea -0x90(%rbp),%rax\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 10a0 \nmov -0xb8(%rbp),%rax\nmov %rax,%rdi\ncallq 10b0 \nmovb $0x0,-0x90(%rbp,%rax,1)\njmp 12ca \nmovb $0x0,-0x90(%rbp)\nmovl $0xffffffff,-0x2c(%rbp)\nmovl $0xffffffff,-0x28(%rbp)\nmov -0xa8(%rbp),%rax\nmov -0x90(%rbp),%rcx\nmov -0x88(%rbp),%rbx\nmov %rcx,(%rax)\nmov %rbx,0x8(%rax)\nmov -0x80(%rbp),%rcx\nmov -0x78(%rbp),%rbx\nmov %rcx,0x10(%rax)\nmov %rbx,0x18(%rax)\nmov -0x70(%rbp),%rcx\nmov -0x68(%rbp),%rbx\nmov %rcx,0x20(%rax)\nmov %rbx,0x28(%rax)\nmov -0x60(%rbp),%rcx\nmov -0x58(%rbp),%rbx\nmov %rcx,0x30(%rax)\nmov %rbx,0x38(%rax)\nmov -0x50(%rbp),%rcx\nmov -0x48(%rbp),%rbx\nmov %rcx,0x40(%rax)\nmov %rbx,0x48(%rax)\nmov -0x40(%rbp),%rcx\nmov -0x38(%rbp),%rbx\nmov %rcx,0x50(%rax)\nmov %rbx,0x58(%rax)\nmov -0x30(%rbp),%rdx\nmov %rdx,0x60(%rax)\nmov -0x28(%rbp),%edx\nmov %edx,0x68(%rax)\nmov -0x18(%rbp),%rax\nxor %fs:0x28,%rax\nje 1358 \ncallq 10c0 <__stack_chk_fail@plt>\nmov -0xa8(%rbp),%rax\nadd $0xb8,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 0B8h\nmov [rbp+var_A8], rdi\nmov [rbp+haystack], rsi\nmov [rbp+needle], rdx\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov rdx, [rbp+needle]\nmov rax, [rbp+haystack]\nmov rsi, rdx; needle\nmov rdi, rax; haystack\ncall _strstr\nmov [rbp+src], rax\ncmp [rbp+src], 0\njz short loc_12B5\nmov rax, [rbp+src]\nsub rax, [rbp+haystack]\nmov dword ptr [rbp+var_2C], eax\nmov eax, dword ptr [rbp+var_2C]\nmov ebx, eax\nmov rax, [rbp+needle]\nmov rdi, rax; s\ncall _strlen\nadd eax, ebx\nmov dword ptr [rbp+var_2C+4], eax\nmov rax, [rbp+needle]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax; n\nmov rcx, [rbp+src]\nlea rax, [rbp+dest]\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strncpy\nmov rax, [rbp+needle]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+rax+dest], 0\njmp short loc_12CA\nloc_12B5:\nmov [rbp+dest], 0\nmov dword ptr [rbp+var_2C], 0FFFFFFFFh\nmov dword ptr [rbp+var_2C+4], 0FFFFFFFFh\nloc_12CA:\nmov rax, [rbp+var_A8]\nmov rcx, qword ptr [rbp+dest]\nmov rbx, [rbp+var_88]\nmov [rax], rcx\nmov [rax+8], rbx\nmov rcx, [rbp+var_80]\nmov rbx, [rbp+var_78]\nmov [rax+10h], rcx\nmov [rax+18h], rbx\nmov rcx, [rbp+var_70]\nmov rbx, [rbp+var_68]\nmov [rax+20h], rcx\nmov [rax+28h], rbx\nmov rcx, [rbp+var_60]\nmov rbx, [rbp+var_58]\nmov [rax+30h], rcx\nmov [rax+38h], rbx\nmov rcx, [rbp+var_50]\nmov rbx, [rbp+var_48]\nmov [rax+40h], rcx\nmov [rax+48h], rbx\nmov rcx, [rbp+var_40]\nmov rbx, [rbp+var_38]\nmov [rax+50h], rcx\nmov [rax+58h], rbx\nmov rcx, [rbp+var_38+4]\nmov rbx, [rbp+var_2C]\nmov [rax+5Ch], rcx\nmov [rax+64h], rbx\nmov rax, [rbp+var_18]\nsub rax, fs:28h\njz short loc_135A\ncall ___stack_chk_fail\nloc_135A:\nmov rax, [rbp+var_A8]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(_QWORD *a1, const char *a2, const char *a3)\n{\n size_t v3; // rax\n __int64 v4; // rbx\n __int64 v5; // rbx\n __int64 v6; // rbx\n __int64 v7; // rbx\n __int64 v8; // rbx\n __int64 v9; // rbx\n __int64 v10; // rbx\n const char *src; // [rsp+28h] [rbp-98h]\n char dest[8]; // [rsp+30h] [rbp-90h] BYREF\n __int64 v15; // [rsp+38h] [rbp-88h]\n __int64 v16; // [rsp+40h] [rbp-80h]\n __int64 v17; // [rsp+48h] [rbp-78h]\n __int64 v18; // [rsp+50h] [rbp-70h]\n __int64 v19; // [rsp+58h] [rbp-68h]\n __int64 v20; // [rsp+60h] [rbp-60h]\n __int64 v21; // [rsp+68h] [rbp-58h]\n __int64 v22; // [rsp+70h] [rbp-50h]\n __int64 v23; // [rsp+78h] [rbp-48h]\n __int64 v24; // [rsp+80h] [rbp-40h]\n _BYTE v25[12]; // [rsp+88h] [rbp-38h]\n __int64 v26; // [rsp+94h] [rbp-2Ch]\n unsigned __int64 v27; // [rsp+A8h] [rbp-18h]\n\n v27 = __readfsqword(0x28u);\n src = strstr(a2, a3);\n if ( src )\n {\n LODWORD(v26) = (_DWORD)src - (_DWORD)a2;\n HIDWORD(v26) = (_DWORD)src - (_DWORD)a2 + strlen(a3);\n v3 = strlen(a3);\n strncpy(dest, src, v3);\n dest[strlen(a3)] = 0;\n }\n else\n {\n dest[0] = 0;\n v26 = -1LL;\n }\n v4 = v15;\n *a1 = *(_QWORD *)dest;\n a1[1] = v4;\n v5 = v17;\n a1[2] = v16;\n a1[3] = v5;\n v6 = v19;\n a1[4] = v18;\n a1[5] = v6;\n v7 = v21;\n a1[6] = v20;\n a1[7] = v7;\n v8 = v23;\n a1[8] = v22;\n a1[9] = v8;\n v9 = *(_QWORD *)v25;\n a1[10] = v24;\n a1[11] = v9;\n v10 = v26;\n *(_QWORD *)((char *)a1 + 92) = *(_QWORD *)&v25[4];\n *(_QWORD *)((char *)a1 + 100) = v10;\n return a1;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 0B8h\nmov [rbp+var_A8], rdi\nmov [rbp+haystack], rsi\nmov [rbp+needle], rdx\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov rdx, [rbp+needle]\nmov rax, [rbp+haystack]\nmov rsi, rdx; needle\nmov rdi, rax; haystack\ncall _strstr\nmov [rbp+src], rax\ncmp [rbp+src], 0\njz short loc_12B5\nmov rax, [rbp+src]\nsub rax, [rbp+haystack]\nmov dword ptr [rbp+var_2C], eax\nmov eax, dword ptr [rbp+var_2C]\nmov ebx, eax\nmov rax, [rbp+needle]\nmov rdi, rax; s\ncall _strlen\nadd eax, ebx\nmov dword ptr [rbp+var_2C+4], eax\nmov rax, [rbp+needle]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax; n\nmov rcx, [rbp+src]\nlea rax, [rbp+dest]\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strncpy\nmov rax, [rbp+needle]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+rax+dest], 0\njmp short loc_12CA\nloc_12B5:\nmov [rbp+dest], 0\nmov dword ptr [rbp+var_2C], 0FFFFFFFFh\nmov dword ptr [rbp+var_2C+4], 0FFFFFFFFh\nloc_12CA:\nmov rax, [rbp+var_A8]\nmov rcx, qword ptr [rbp+dest]\nmov rbx, [rbp+var_88]\nmov [rax], rcx\nmov [rax+8], rbx\nmov rcx, [rbp+var_80]\nmov rbx, [rbp+var_78]\nmov [rax+10h], rcx\nmov [rax+18h], rbx\nmov rcx, [rbp+var_70]\nmov rbx, [rbp+var_68]\nmov [rax+20h], rcx\nmov [rax+28h], rbx\nmov rcx, [rbp+var_60]\nmov rbx, [rbp+var_58]\nmov [rax+30h], rcx\nmov [rax+38h], rbx\nmov rcx, [rbp+var_50]\nmov rbx, [rbp+var_48]\nmov [rax+40h], rcx\nmov [rax+48h], rbx\nmov rcx, [rbp+var_40]\nmov rbx, [rbp+var_38]\nmov [rax+50h], rcx\nmov [rax+58h], rbx\nmov rcx, [rbp+var_38+4]\nmov rbx, [rbp+var_2C]\nmov [rax+5Ch], rcx\nmov [rax+64h], rbx\nmov rax, [rbp+var_18]\nsub rax, fs:28h\njz short loc_135A\ncall ___stack_chk_fail\nloc_135A:\nmov rax, [rbp+var_A8]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11E9(_QWORD *a1, const char *a2, const char *a3)\n{\n size_t v3; // rax\n __int64 v4; // rbx\n __int64 v5; // rbx\n __int64 v6; // rbx\n __int64 v7; // rbx\n __int64 v8; // rbx\n __int64 v9; // rbx\n __int64 v10; // rbx\n const char *src; // [rsp+28h] [rbp-98h]\n char dest[8]; // [rsp+30h] [rbp-90h] BYREF\n __int64 v15; // [rsp+38h] [rbp-88h]\n __int64 v16; // [rsp+40h] [rbp-80h]\n __int64 v17; // [rsp+48h] [rbp-78h]\n __int64 v18; // [rsp+50h] [rbp-70h]\n __int64 v19; // [rsp+58h] [rbp-68h]\n __int64 v20; // [rsp+60h] [rbp-60h]\n __int64 v21; // [rsp+68h] [rbp-58h]\n __int64 v22; // [rsp+70h] [rbp-50h]\n __int64 v23; // [rsp+78h] [rbp-48h]\n __int64 v24; // [rsp+80h] [rbp-40h]\n _BYTE v25[12]; // [rsp+88h] [rbp-38h]\n __int64 v26; // [rsp+94h] [rbp-2Ch]\n unsigned __int64 v27; // [rsp+A8h] [rbp-18h]\n\n v27 = __readfsqword(0x28u);\n src = strstr(a2, a3);\n if ( src )\n {\n LODWORD(v26) = (_DWORD)src - (_DWORD)a2;\n HIDWORD(v26) = (_DWORD)src - (_DWORD)a2 + strlen(a3);\n v3 = strlen(a3);\n strncpy(dest, src, v3);\n dest[strlen(a3)] = 0;\n }\n else\n {\n dest[0] = 0;\n v26 = -1LL;\n }\n v4 = v15;\n *a1 = *(_QWORD *)dest;\n a1[1] = v4;\n v5 = v17;\n a1[2] = v16;\n a1[3] = v5;\n v6 = v19;\n a1[4] = v18;\n a1[5] = v6;\n v7 = v21;\n a1[6] = v20;\n a1[7] = v7;\n v8 = v23;\n a1[8] = v22;\n a1[9] = v8;\n v9 = *(_QWORD *)v25;\n a1[10] = v24;\n a1[11] = v9;\n v10 = v26;\n *(_QWORD *)((char *)a1 + 92) = *(_QWORD *)&v25[4];\n *(_QWORD *)((char *)a1 + 100) = v10;\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11E9(uint64_t *a1, const char *a2, const char *a3) {\n unsigned int v3;\n long long v4;\n long long v5;\n long long v6;\n long long v7;\n long long v8;\n long long v9;\n long long v10;\n const char *src;\n char dest[8];\n long long v15;\n long long v16;\n long long v17;\n long long v18;\n long long v19;\n long long v20;\n long long v21;\n long long v22;\n long long v23;\n long long v24;\n uint8_t v25[12];\n long long v26;\n unsigned long long v27;\n v27 = __readfsqword(40u);\n src = strstr(a2, a3);\n if (src) {\n LODWORD(v26) = (uint32_t)src - (uint32_t)a2;\n HIDWORD(v26) = (uint32_t)src - (uint32_t)a2 + strlen(a3);\n v3 = strlen(a3);\n strncpy(dest, src, v3);\n dest[strlen(a3)] = 0;\n } else {\n dest[0] = 0;\n v26 = -1LL;\n }\n v4 = v15;\n *a1 = *(uint64_t *)dest;\n a1[1] = v4;\n v5 = v17;\n a1[2] = v16;\n a1[3] = v5;\n v6 = v19;\n a1[4] = v18;\n a1[5] = v6;\n v7 = v21;\n a1[6] = v20;\n a1[7] = v7;\n v8 = v23;\n a1[8] = v22;\n a1[9] = v8;\n v9 = *(uint64_t *)v25;\n a1[10] = v24;\n a1[11] = v9;\n v10 = v26;\n *(uint64_t *)((char *)a1 + 92) = *(uint64_t *)&v25[4];\n *(uint64_t *)((char *)a1 + 100) = v10;\n return a1;\n}", + "ida_pseudo_norm": "uint64_t *func0(uint64_t *a1, const char *a2, const char *a3) {\n unsigned int v3;\n long long v4;\n long long v5;\n long long v6;\n long long v7;\n long long v8;\n long long v9;\n long long v10;\n const char *src;\n char dest[8];\n long long v15;\n long long v16;\n long long v17;\n long long v18;\n long long v19;\n long long v20;\n long long v21;\n long long v22;\n long long v23;\n long long v24;\n uint8_t v25[12];\n long long v26;\n unsigned long long v27;\n v27 = __readfsqword(40u);\n src = strstr(a2, a3);\n if (src) {\n LODWORD(v26) = (uint32_t)src - (uint32_t)a2;\n HIDWORD(v26) = (uint32_t)src - (uint32_t)a2 + strlen(a3);\n v3 = strlen(a3);\n strncpy(dest, src, v3);\n dest[strlen(a3)] = 0;\n } else {\n dest[0] = 0;\n v26 = -1LL;\n }\n v4 = v15;\n *a1 = *(uint64_t *)dest;\n a1[1] = v4;\n v5 = v17;\n a1[2] = v16;\n a1[3] = v5;\n v6 = v19;\n a1[4] = v18;\n a1[5] = v6;\n v7 = v21;\n a1[6] = v20;\n a1[7] = v7;\n v8 = v23;\n a1[8] = v22;\n a1[9] = v8;\n v9 = *(uint64_t *)v25;\n a1[10] = v24;\n a1[11] = v9;\n v10 = v26;\n *(uint64_t *)((char *)a1 + 92) = *(uint64_t *)&v25[4];\n *(uint64_t *)((char *)a1 + 100) = v10;\n return a1;\n}" + }, + { + "index": 773, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char substring[100];\n\n int start;\n\n int end;\n\n} Occurrence;\n\n\n\n", + "func": "Occurrence func0(const char *text, const char *pattern) {\n Occurrence result;\n char *pos = strstr(text, pattern);\n if (pos) {\n result.start = pos - text;\n result.end = result.start + strlen(pattern);\n strncpy(result.substring, pos, strlen(pattern));\n result.substring[strlen(pattern)] = '\\0';\n } else {\n result.substring[0] = '\\0';\n result.start = -1;\n result.end = -1;\n }\n return result;\n}", + "test": "int main() {\n\n Occurrence res1 = func0(\"python programming, python language\", \"python\");\n\n assert(strcmp(res1.substring, \"python\") == 0);\n\n assert(res1.start == 0);\n\n assert(res1.end == 6);\n\n\n\n Occurrence res2 = func0(\"python programming,programming language\", \"programming\");\n\n assert(strcmp(res2.substring, \"programming\") == 0);\n\n assert(res2.start == 7);\n\n assert(res2.end == 18);\n\n\n\n Occurrence res3 = func0(\"python programming,programming language\", \"language\");\n\n assert(strcmp(res3.substring, \"language\") == 0);\n\n assert(res3.start == 31);\n\n assert(res3.end == 39);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x88,%rsp\nmov %rdi,%rbx\nmov %rsi,%r12\nmov %rdx,%rbp\nmov %fs:0x28,%rax\nmov %rax,0x78(%rsp)\nxor %eax,%eax\nmov %rdx,%rsi\nmov %r12,%rdi\ncallq 10b0 \ntest %rax,%rax\nje 12b7 \nmov %rax,%rsi\nmov %rax,%rdx\nsub %r12,%rdx\nmov %edx,0x64(%rsp)\nmov $0xffffffffffffffff,%r13\nmov $0x0,%r12d\nmov %r13,%rcx\nmov %rbp,%rdi\nmov %r12d,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nlea -0x1(%rcx,%rdx,1),%eax\nmov %eax,0x68(%rsp)\nmov %r13,%rcx\nmov %rbp,%rdi\nmov %r12d,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nlea -0x1(%rcx),%rdx\nmov %rsp,%rdi\nmov $0x64,%ecx\ncallq 10a0 <__strncpy_chk@plt>\nmov %r13,%rcx\nmov %rbp,%rdi\nmov %r12d,%eax\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rbp\nnot %rbp\nmovb $0x0,-0x1(%rsp,%rbp,1)\nmovdqa (%rsp),%xmm0\nmovups %xmm0,(%rbx)\nmovdqa 0x10(%rsp),%xmm1\nmovups %xmm1,0x10(%rbx)\nmovdqa 0x20(%rsp),%xmm2\nmovups %xmm2,0x20(%rbx)\nmovdqa 0x30(%rsp),%xmm3\nmovups %xmm3,0x30(%rbx)\nmovdqa 0x40(%rsp),%xmm4\nmovups %xmm4,0x40(%rbx)\nmovdqa 0x50(%rsp),%xmm5\nmovups %xmm5,0x50(%rbx)\nmov 0x60(%rsp),%rax\nmov %rax,0x60(%rbx)\nmov 0x68(%rsp),%eax\nmov %eax,0x68(%rbx)\nmov 0x78(%rsp),%rax\nxor %fs:0x28,%rax\njne 12d0 \nmov %rbx,%rax\nadd $0x88,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nmovb $0x0,(%rsp)\nmovl $0xffffffff,0x64(%rsp)\nmovl $0xffffffff,0x68(%rsp)\njmpq 124c \ncallq 1080 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nadd rsp, 0FFFFFFFFFFFFFF80h\nmov rbx, rdi\nmov r13, rsi\nmov rbp, rdx\nmov rax, fs:28h\nmov [rsp+0A8h+var_30], rax\nxor eax, eax\nmov rsi, rdx; needle\nmov rdi, r13; haystack\ncall _strstr\ntest rax, rax\njz loc_12CF\nmov r12, rax\nmov r14, rax\nsub r14, r13\nmov [rsp+0A8h+var_44], r14d\nmov rdi, rbp; s\ncall _strlen\nadd r14d, eax\nmov [rsp+0A8h+var_40], r14d\nmov rdi, rbp; s\ncall _strlen\nmov rdx, rax\nmov rdi, rsp\nmov ecx, 64h ; 'd'\nmov rsi, r12\ncall ___strncpy_chk\nmov rdi, rbp; s\ncall _strlen\nmov byte ptr [rsp+rax+0A8h+var_A8], 0\nloc_126B:\nmovdqa xmm0, [rsp+0A8h+var_A8]\nmovups xmmword ptr [rbx], xmm0\nmovdqa xmm1, [rsp+0A8h+var_98]\nmovups xmmword ptr [rbx+10h], xmm1\nmovdqa xmm2, [rsp+0A8h+var_88]\nmovups xmmword ptr [rbx+20h], xmm2\nmovdqa xmm3, [rsp+0A8h+var_78]\nmovups xmmword ptr [rbx+30h], xmm3\nmovdqa xmm4, [rsp+0A8h+var_68]\nmovups xmmword ptr [rbx+40h], xmm4\nmovdqa xmm5, [rsp+0A8h+var_58]\nmovups xmmword ptr [rbx+50h], xmm5\nmovdqu xmm6, [rsp+0A8h+var_58+0Ch]\nmovups xmmword ptr [rbx+5Ch], xmm6\nmov rax, [rsp+0A8h+var_30]\nsub rax, fs:28h\njnz short loc_12E5\nmov rax, rbx\nsub rsp, 0FFFFFFFFFFFFFF80h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_12CF:\nmov byte ptr [rsp+0A8h+var_A8], 0\nmov [rsp+0A8h+var_44], 0FFFFFFFFh\nmov [rsp+0A8h+var_40], 0FFFFFFFFh\njmp short loc_126B\nloc_12E5:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, const char *a2, const char *a3)\n{\n char *v4; // rax\n char *v5; // r12\n size_t v6; // rax\n __m128i v8; // [rsp+0h] [rbp-A8h] BYREF\n __m128i v9; // [rsp+10h] [rbp-98h] BYREF\n __m128i v10; // [rsp+20h] [rbp-88h] BYREF\n __m128i v11; // [rsp+30h] [rbp-78h] BYREF\n __m128i v12; // [rsp+40h] [rbp-68h] BYREF\n __m128i v13; // [rsp+50h] [rbp-58h] BYREF\n int v14; // [rsp+64h] [rbp-44h]\n int v15; // [rsp+68h] [rbp-40h]\n unsigned __int64 v16; // [rsp+78h] [rbp-30h]\n\n v16 = __readfsqword(0x28u);\n v4 = strstr(a2, a3);\n if ( v4 )\n {\n v5 = v4;\n v14 = (_DWORD)v4 - (_DWORD)a2;\n v15 = strlen(a3) + (_DWORD)v4 - (_DWORD)a2;\n v6 = strlen(a3);\n __strncpy_chk(&v8, v5, v6, 100LL);\n v8.m128i_i8[strlen(a3)] = 0;\n }\n else\n {\n v8.m128i_i8[0] = 0;\n v14 = -1;\n v15 = -1;\n }\n *(__m128i *)a1 = _mm_load_si128(&v8);\n *(__m128i *)(a1 + 16) = _mm_load_si128(&v9);\n *(__m128i *)(a1 + 32) = _mm_load_si128(&v10);\n *(__m128i *)(a1 + 48) = _mm_load_si128(&v11);\n *(__m128i *)(a1 + 64) = _mm_load_si128(&v12);\n *(__m128i *)(a1 + 80) = _mm_load_si128(&v13);\n *(__m128i *)(a1 + 92) = _mm_loadu_si128((const __m128i *)((char *)&v13.m128i_u64[1] + 4));\n return a1;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nadd rsp, 0FFFFFFFFFFFFFF80h\nmov rbx, rdi\nmov r13, rsi\nmov rbp, rdx\nmov rax, fs:28h\nmov [rsp+0A8h+var_30], rax\nxor eax, eax\nmov rsi, rdx; needle\nmov rdi, r13; haystack\ncall _strstr\ntest rax, rax\njz loc_12CF\nmov r12, rax\nmov r14, rax\nsub r14, r13\nmov [rsp+0A8h+var_44], r14d\nmov rdi, rbp; s\ncall _strlen\nadd r14d, eax\nmov [rsp+0A8h+var_40], r14d\nmov rdi, rbp; s\ncall _strlen\nmov rdx, rax\nmov rdi, rsp\nmov ecx, 64h ; 'd'\nmov rsi, r12\ncall ___strncpy_chk\nmov rdi, rbp; s\ncall _strlen\nmov byte ptr [rsp+rax+0A8h+var_A8], 0\nloc_126B:\nmovdqa xmm0, [rsp+0A8h+var_A8]\nmovups xmmword ptr [rbx], xmm0\nmovdqa xmm1, [rsp+0A8h+var_98]\nmovups xmmword ptr [rbx+10h], xmm1\nmovdqa xmm2, [rsp+0A8h+var_88]\nmovups xmmword ptr [rbx+20h], xmm2\nmovdqa xmm3, [rsp+0A8h+var_78]\nmovups xmmword ptr [rbx+30h], xmm3\nmovdqa xmm4, [rsp+0A8h+var_68]\nmovups xmmword ptr [rbx+40h], xmm4\nmovdqa xmm5, [rsp+0A8h+var_58]\nmovups xmmword ptr [rbx+50h], xmm5\nmovdqu xmm6, [rsp+0A8h+var_58+0Ch]\nmovups xmmword ptr [rbx+5Ch], xmm6\nmov rax, [rsp+0A8h+var_30]\nsub rax, fs:28h\njnz short loc_12E5\nmov rax, rbx\nsub rsp, 0FFFFFFFFFFFFFF80h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_12CF:\nmov byte ptr [rsp+0A8h+var_A8], 0\nmov [rsp+0A8h+var_44], 0FFFFFFFFh\nmov [rsp+0A8h+var_40], 0FFFFFFFFh\njmp short loc_126B\nloc_12E5:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_11E9(__int64 a1, const char *a2, const char *a3)\n{\n char *v4; // rax\n char *v5; // r12\n size_t v6; // rax\n __m128i v8; // [rsp+0h] [rbp-A8h] BYREF\n __m128i v9; // [rsp+10h] [rbp-98h] BYREF\n __m128i v10; // [rsp+20h] [rbp-88h] BYREF\n __m128i v11; // [rsp+30h] [rbp-78h] BYREF\n __m128i v12; // [rsp+40h] [rbp-68h] BYREF\n __m128i v13; // [rsp+50h] [rbp-58h] BYREF\n int v14; // [rsp+64h] [rbp-44h]\n int v15; // [rsp+68h] [rbp-40h]\n unsigned __int64 v16; // [rsp+78h] [rbp-30h]\n\n v16 = __readfsqword(0x28u);\n v4 = strstr(a2, a3);\n if ( v4 )\n {\n v5 = v4;\n v14 = (_DWORD)v4 - (_DWORD)a2;\n v15 = strlen(a3) + (_DWORD)v4 - (_DWORD)a2;\n v6 = strlen(a3);\n __strncpy_chk(&v8, v5, v6, 100LL);\n v8.m128i_i8[strlen(a3)] = 0;\n }\n else\n {\n v8.m128i_i8[0] = 0;\n v14 = -1;\n v15 = -1;\n }\n *(__m128i *)a1 = _mm_load_si128(&v8);\n *(__m128i *)(a1 + 16) = _mm_load_si128(&v9);\n *(__m128i *)(a1 + 32) = _mm_load_si128(&v10);\n *(__m128i *)(a1 + 48) = _mm_load_si128(&v11);\n *(__m128i *)(a1 + 64) = _mm_load_si128(&v12);\n *(__m128i *)(a1 + 80) = _mm_load_si128(&v13);\n *(__m128i *)(a1 + 92) = _mm_loadu_si128((const __m128i *)((char *)&v13.m128i_u64[1] + 4));\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11E9(long long a1, const char *a2, const char *a3) {\n char *v4;\n char *v5;\n unsigned int v6;\n __m128i v8;\n __m128i v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n int v14;\n int v15;\n unsigned long long v16;\n v16 = __readfsqword(40u);\n v4 = strstr(a2, a3);\n if (v4) {\n v5 = v4;\n v14 = (uint32_t)v4 - (uint32_t)a2;\n v15 = strlen(a3) + (uint32_t)v4 - (uint32_t)a2;\n v6 = strlen(a3);\n __strncpy_chk(&v8, v5, v6, 100LL);\n v8.m128i_i8[strlen(a3)] = 0;\n } else {\n v8.m128i_i8[0] = 0;\n v14 = -1;\n v15 = -1;\n }\n *(__m128i *)a1 = _mm_load_si128(&v8);\n *(__m128i *)(a1 + 16) = _mm_load_si128(&v9);\n *(__m128i *)(a1 + 32) = _mm_load_si128(&v10);\n *(__m128i *)(a1 + 48) = _mm_load_si128(&v11);\n *(__m128i *)(a1 + 64) = _mm_load_si128(&v12);\n *(__m128i *)(a1 + 80) = _mm_load_si128(&v13);\n *(__m128i *)(a1 + 92) =\n _mm_loadu_si128((const __m128i *)((char *)&v13.m128i_u64[1] + 4));\n return a1;\n}", + "ida_pseudo_norm": "long long func0(long long a1, const char *a2, const char *a3) {\n char *v4;\n char *v5;\n unsigned int v6;\n __m128i v8;\n __m128i v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n int v14;\n int v15;\n unsigned long long v16;\n v16 = __readfsqword(40u);\n v4 = strstr(a2, a3);\n if (v4) {\n v5 = v4;\n v14 = (uint32_t)v4 - (uint32_t)a2;\n v15 = strlen(a3) + (uint32_t)v4 - (uint32_t)a2;\n v6 = strlen(a3);\n __strncpy_chk(&v8, v5, v6, 100LL);\n v8.m128i_i8[strlen(a3)] = 0;\n } else {\n v8.m128i_i8[0] = 0;\n v14 = -1;\n v15 = -1;\n }\n *(__m128i *)a1 = _mm_load_si128(&v8);\n *(__m128i *)(a1 + 16) = _mm_load_si128(&v9);\n *(__m128i *)(a1 + 32) = _mm_load_si128(&v10);\n *(__m128i *)(a1 + 48) = _mm_load_si128(&v11);\n *(__m128i *)(a1 + 64) = _mm_load_si128(&v12);\n *(__m128i *)(a1 + 80) = _mm_load_si128(&v13);\n *(__m128i *)(a1 + 92) =\n _mm_loadu_si128((const __m128i *)((char *)&v13.m128i_u64[1] + 4));\n return a1;\n}" + }, + { + "index": 773, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char substring[100];\n\n int start;\n\n int end;\n\n} Occurrence;\n\n\n\n", + "func": "Occurrence func0(const char *text, const char *pattern) {\n Occurrence result;\n char *pos = strstr(text, pattern);\n if (pos) {\n result.start = pos - text;\n result.end = result.start + strlen(pattern);\n strncpy(result.substring, pos, strlen(pattern));\n result.substring[strlen(pattern)] = '\\0';\n } else {\n result.substring[0] = '\\0';\n result.start = -1;\n result.end = -1;\n }\n return result;\n}", + "test": "int main() {\n\n Occurrence res1 = func0(\"python programming, python language\", \"python\");\n\n assert(strcmp(res1.substring, \"python\") == 0);\n\n assert(res1.start == 0);\n\n assert(res1.end == 6);\n\n\n\n Occurrence res2 = func0(\"python programming,programming language\", \"programming\");\n\n assert(strcmp(res2.substring, \"programming\") == 0);\n\n assert(res2.start == 7);\n\n assert(res2.end == 18);\n\n\n\n Occurrence res3 = func0(\"python programming,programming language\", \"language\");\n\n assert(strcmp(res3.substring, \"language\") == 0);\n\n assert(res3.start == 31);\n\n assert(res3.end == 39);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\nmov %rdx,%r13\npush %r12\nmov %rdi,%r12\npush %rbp\npush %rbx\nmov %rsi,%rbx\nmov %rdx,%rsi\nmov %rbx,%rdi\nadd $0xffffffffffffff80,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x78(%rsp)\nxor %eax,%eax\ncallq 10d0 \ntest %rax,%rax\nje 1500 \nmov %rax,%r14\nmov %r13,%rdi\nmov %rax,%rbp\nsub %rbx,%r14\nmov %r14d,0x64(%rsp)\ncallq 1090 \nmov %rsp,%rdi\nmov $0x64,%ecx\nmov %rbp,%rsi\nmov %rax,%rbx\nadd %eax,%r14d\nmov %rax,%rdx\nmov %r14d,0x68(%rsp)\ncallq 10c0 <__strncpy_chk@plt>\nmovb $0x0,(%rsp,%rbx,1)\nmov 0x60(%rsp),%rax\nmovdqa (%rsp),%xmm0\nmovdqa 0x10(%rsp),%xmm1\nmovdqa 0x20(%rsp),%xmm2\nmov %rax,0x60(%r12)\nmov 0x68(%rsp),%eax\nmovdqa 0x30(%rsp),%xmm3\nmovdqa 0x40(%rsp),%xmm4\nmovups %xmm0,(%r12)\nmov %eax,0x68(%r12)\nmovdqa 0x50(%rsp),%xmm5\nmovups %xmm1,0x10(%r12)\nmovups %xmm2,0x20(%r12)\nmovups %xmm3,0x30(%r12)\nmovups %xmm4,0x40(%r12)\nmovups %xmm5,0x50(%r12)\nmov 0x78(%rsp),%rax\nxor %fs:0x28,%rax\njne 1512 \nsub $0xffffffffffffff80,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nxchg %ax,%ax\nmovb $0x0,(%rsp)\nmovq $0xffffffffffffffff,0x64(%rsp)\njmpq 1485 \ncallq 10a0 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\nmov r13, rsi\nmov rsi, rdx; needle\npush r12\nmov r12, rdx\npush rbp\npush rbx\nmov rbx, rdi\nmov rdi, r13; haystack\nadd rsp, 0FFFFFFFFFFFFFF80h\nmov rax, fs:28h\nmov [rsp+0A8h+var_30], rax\nxor eax, eax\ncall _strstr\ntest rax, rax\njz loc_14F0\nmov r14, rax\nmov rdi, r12; s\nmov rbp, rax\nsub r14, r13\nmov dword ptr [rsp+0A8h+var_44], r14d\ncall _strlen\nmov rdi, rsp\nmov ecx, 64h ; 'd'\nmov rsi, rbp\nmov r12, rax\nadd r14d, eax\nmov rdx, rax\nmov dword ptr [rsp+0A8h+var_44+4], r14d\ncall ___strncpy_chk\nmov byte ptr [rsp+r12+0A8h+var_A8], 0\nloc_1486:\nmovdqa xmm0, [rsp+0A8h+var_A8]\nmovdqa xmm1, [rsp+0A8h+var_98]\nmovdqa xmm2, [rsp+0A8h+var_88]\nmovdqa xmm3, [rsp+0A8h+var_78]\nmovdqa xmm4, [rsp+0A8h+var_68]\nmovdqa xmm5, [rsp+0A8h+var_58]\nmovups xmmword ptr [rbx], xmm0\nmovdqu xmm6, [rsp+0A8h+var_58+0Ch]\nmovups xmmword ptr [rbx+10h], xmm1\nmovups xmmword ptr [rbx+50h], xmm5\nmovups xmmword ptr [rbx+20h], xmm2\nmovups xmmword ptr [rbx+30h], xmm3\nmovups xmmword ptr [rbx+40h], xmm4\nmovups xmmword ptr [rbx+5Ch], xmm6\nmov rax, [rsp+0A8h+var_30]\nsub rax, fs:28h\njnz short loc_14FF\nsub rsp, 0FFFFFFFFFFFFFF80h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_14F0:\nmov byte ptr [rsp+0A8h+var_A8], 0\nmov [rsp+0A8h+var_44], 0FFFFFFFFFFFFFFFFh\njmp short loc_1486\nloc_14FF:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, const char *a2, const char *a3)\n{\n char *v4; // rax\n char *v5; // rbp\n int v6; // r14d\n size_t v7; // r12\n __m128i v8; // xmm1\n __m128i v9; // xmm2\n __m128i v10; // xmm3\n __m128i v11; // xmm4\n __m128i v12; // xmm5\n __m128i v13; // xmm6\n __m128i v15; // [rsp+0h] [rbp-A8h] BYREF\n __m128i v16; // [rsp+10h] [rbp-98h] BYREF\n __m128i v17; // [rsp+20h] [rbp-88h] BYREF\n __m128i v18; // [rsp+30h] [rbp-78h] BYREF\n __m128i v19; // [rsp+40h] [rbp-68h] BYREF\n __m128i v20; // [rsp+50h] [rbp-58h] BYREF\n __int64 v21; // [rsp+64h] [rbp-44h]\n unsigned __int64 v22; // [rsp+78h] [rbp-30h]\n\n v22 = __readfsqword(0x28u);\n v4 = strstr(a2, a3);\n if ( v4 )\n {\n v5 = v4;\n v6 = (_DWORD)v4 - (_DWORD)a2;\n LODWORD(v21) = (_DWORD)v4 - (_DWORD)a2;\n v7 = strlen(a3);\n HIDWORD(v21) = v7 + v6;\n __strncpy_chk(&v15, v5, v7, 100LL);\n v15.m128i_i8[v7] = 0;\n }\n else\n {\n v15.m128i_i8[0] = 0;\n v21 = -1LL;\n }\n v8 = _mm_load_si128(&v16);\n v9 = _mm_load_si128(&v17);\n v10 = _mm_load_si128(&v18);\n v11 = _mm_load_si128(&v19);\n v12 = _mm_load_si128(&v20);\n *(__m128i *)a1 = _mm_load_si128(&v15);\n v13 = _mm_loadu_si128((const __m128i *)((char *)&v20.m128i_u64[1] + 4));\n *(__m128i *)(a1 + 16) = v8;\n *(__m128i *)(a1 + 80) = v12;\n *(__m128i *)(a1 + 32) = v9;\n *(__m128i *)(a1 + 48) = v10;\n *(__m128i *)(a1 + 64) = v11;\n *(__m128i *)(a1 + 92) = v13;\n return a1;\n}", + "ida_strip_asm": "sub_1410:\nendbr64\npush r14\npush r13\nmov r13, rsi\nmov rsi, rdx; needle\npush r12\nmov r12, rdx\npush rbp\npush rbx\nmov rbx, rdi\nmov rdi, r13; haystack\nadd rsp, 0FFFFFFFFFFFFFF80h\nmov rax, fs:28h\nmov [rsp+0A8h+var_30], rax\nxor eax, eax\ncall _strstr\ntest rax, rax\njz loc_14F0\nmov r14, rax\nmov rdi, r12; s\nmov rbp, rax\nsub r14, r13\nmov dword ptr [rsp+0A8h+var_44], r14d\ncall _strlen\nmov rdi, rsp\nmov ecx, 64h ; 'd'\nmov rsi, rbp\nmov r12, rax\nadd r14d, eax\nmov rdx, rax\nmov dword ptr [rsp+0A8h+var_44+4], r14d\ncall ___strncpy_chk\nmov byte ptr [rsp+r12+0A8h+var_A8], 0\nloc_1486:\nmovdqa xmm0, [rsp+0A8h+var_A8]\nmovdqa xmm1, [rsp+0A8h+var_98]\nmovdqa xmm2, [rsp+0A8h+var_88]\nmovdqa xmm3, [rsp+0A8h+var_78]\nmovdqa xmm4, [rsp+0A8h+var_68]\nmovdqa xmm5, [rsp+0A8h+var_58]\nmovups xmmword ptr [rbx], xmm0\nmovdqu xmm6, [rsp+0A8h+var_58+0Ch]\nmovups xmmword ptr [rbx+10h], xmm1\nmovups xmmword ptr [rbx+50h], xmm5\nmovups xmmword ptr [rbx+20h], xmm2\nmovups xmmword ptr [rbx+30h], xmm3\nmovups xmmword ptr [rbx+40h], xmm4\nmovups xmmword ptr [rbx+5Ch], xmm6\nmov rax, [rsp+0A8h+var_30]\nsub rax, fs:28h\njnz short loc_14FF\nsub rsp, 0FFFFFFFFFFFFFF80h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_14F0:\nmov byte ptr [rsp+0A8h+var_A8], 0\nmov [rsp+0A8h+var_44], 0FFFFFFFFFFFFFFFFh\njmp short loc_1486\nloc_14FF:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1410(__int64 a1, const char *a2, const char *a3)\n{\n char *v4; // rax\n char *v5; // rbp\n int v6; // r14d\n size_t v7; // r12\n __m128i v8; // xmm1\n __m128i v9; // xmm2\n __m128i v10; // xmm3\n __m128i v11; // xmm4\n __m128i v12; // xmm5\n __m128i v13; // xmm6\n __m128i v15; // [rsp+0h] [rbp-A8h] BYREF\n __m128i v16; // [rsp+10h] [rbp-98h] BYREF\n __m128i v17; // [rsp+20h] [rbp-88h] BYREF\n __m128i v18; // [rsp+30h] [rbp-78h] BYREF\n __m128i v19; // [rsp+40h] [rbp-68h] BYREF\n __m128i v20; // [rsp+50h] [rbp-58h] BYREF\n __int64 v21; // [rsp+64h] [rbp-44h]\n unsigned __int64 v22; // [rsp+78h] [rbp-30h]\n\n v22 = __readfsqword(0x28u);\n v4 = strstr(a2, a3);\n if ( v4 )\n {\n v5 = v4;\n v6 = (_DWORD)v4 - (_DWORD)a2;\n LODWORD(v21) = (_DWORD)v4 - (_DWORD)a2;\n v7 = strlen(a3);\n HIDWORD(v21) = v7 + v6;\n __strncpy_chk(&v15, v5, v7, 100LL);\n v15.m128i_i8[v7] = 0;\n }\n else\n {\n v15.m128i_i8[0] = 0;\n v21 = -1LL;\n }\n v8 = _mm_load_si128(&v16);\n v9 = _mm_load_si128(&v17);\n v10 = _mm_load_si128(&v18);\n v11 = _mm_load_si128(&v19);\n v12 = _mm_load_si128(&v20);\n *(__m128i *)a1 = _mm_load_si128(&v15);\n v13 = _mm_loadu_si128((const __m128i *)((char *)&v20.m128i_u64[1] + 4));\n *(__m128i *)(a1 + 16) = v8;\n *(__m128i *)(a1 + 80) = v12;\n *(__m128i *)(a1 + 32) = v9;\n *(__m128i *)(a1 + 48) = v10;\n *(__m128i *)(a1 + 64) = v11;\n *(__m128i *)(a1 + 92) = v13;\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1410(long long a1, const char *a2, const char *a3) {\n char *v4;\n char *v5;\n int v6;\n unsigned int v7;\n __m128i v8;\n __m128i v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i v15;\n __m128i v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n __m128i v20;\n long long v21;\n unsigned long long v22;\n v22 = __readfsqword(40u);\n v4 = strstr(a2, a3);\n if (v4) {\n v5 = v4;\n v6 = (uint32_t)v4 - (uint32_t)a2;\n LODWORD(v21) = (uint32_t)v4 - (uint32_t)a2;\n v7 = strlen(a3);\n HIDWORD(v21) = v7 + v6;\n __strncpy_chk(&v15, v5, v7, 100LL);\n v15.m128i_i8[v7] = 0;\n } else {\n v15.m128i_i8[0] = 0;\n v21 = -1LL;\n }\n v8 = _mm_load_si128(&v16);\n v9 = _mm_load_si128(&v17);\n v10 = _mm_load_si128(&v18);\n v11 = _mm_load_si128(&v19);\n v12 = _mm_load_si128(&v20);\n *(__m128i *)a1 = _mm_load_si128(&v15);\n v13 = _mm_loadu_si128((const __m128i *)((char *)&v20.m128i_u64[1] + 4));\n *(__m128i *)(a1 + 16) = v8;\n *(__m128i *)(a1 + 80) = v12;\n *(__m128i *)(a1 + 32) = v9;\n *(__m128i *)(a1 + 48) = v10;\n *(__m128i *)(a1 + 64) = v11;\n *(__m128i *)(a1 + 92) = v13;\n return a1;\n}", + "ida_pseudo_norm": "long long func0(long long a1, const char *a2, const char *a3) {\n char *v4;\n char *v5;\n int v6;\n unsigned int v7;\n __m128i v8;\n __m128i v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i v15;\n __m128i v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n __m128i v20;\n long long v21;\n unsigned long long v22;\n v22 = __readfsqword(40u);\n v4 = strstr(a2, a3);\n if (v4) {\n v5 = v4;\n v6 = (uint32_t)v4 - (uint32_t)a2;\n LODWORD(v21) = (uint32_t)v4 - (uint32_t)a2;\n v7 = strlen(a3);\n HIDWORD(v21) = v7 + v6;\n __strncpy_chk(&v15, v5, v7, 100LL);\n v15.m128i_i8[v7] = 0;\n } else {\n v15.m128i_i8[0] = 0;\n v21 = -1LL;\n }\n v8 = _mm_load_si128(&v16);\n v9 = _mm_load_si128(&v17);\n v10 = _mm_load_si128(&v18);\n v11 = _mm_load_si128(&v19);\n v12 = _mm_load_si128(&v20);\n *(__m128i *)a1 = _mm_load_si128(&v15);\n v13 = _mm_loadu_si128((const __m128i *)((char *)&v20.m128i_u64[1] + 4));\n *(__m128i *)(a1 + 16) = v8;\n *(__m128i *)(a1 + 80) = v12;\n *(__m128i *)(a1 + 32) = v9;\n *(__m128i *)(a1 + 48) = v10;\n *(__m128i *)(a1 + 64) = v11;\n *(__m128i *)(a1 + 92) = v13;\n return a1;\n}" + }, + { + "index": 773, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char substring[100];\n\n int start;\n\n int end;\n\n} Occurrence;\n\n\n\n", + "func": "Occurrence func0(const char *text, const char *pattern) {\n Occurrence result;\n char *pos = strstr(text, pattern);\n if (pos) {\n result.start = pos - text;\n result.end = result.start + strlen(pattern);\n strncpy(result.substring, pos, strlen(pattern));\n result.substring[strlen(pattern)] = '\\0';\n } else {\n result.substring[0] = '\\0';\n result.start = -1;\n result.end = -1;\n }\n return result;\n}", + "test": "int main() {\n\n Occurrence res1 = func0(\"python programming, python language\", \"python\");\n\n assert(strcmp(res1.substring, \"python\") == 0);\n\n assert(res1.start == 0);\n\n assert(res1.end == 6);\n\n\n\n Occurrence res2 = func0(\"python programming,programming language\", \"programming\");\n\n assert(strcmp(res2.substring, \"programming\") == 0);\n\n assert(res2.start == 7);\n\n assert(res2.end == 18);\n\n\n\n Occurrence res3 = func0(\"python programming,programming language\", \"language\");\n\n assert(strcmp(res3.substring, \"language\") == 0);\n\n assert(res3.start == 31);\n\n assert(res3.end == 39);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\nmov %rdx,%r13\npush %r12\nmov %rdi,%r12\npush %rbp\npush %rbx\nmov %rsi,%rbx\nmov %rdx,%rsi\nmov %rbx,%rdi\nadd $0xffffffffffffff80,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x78(%rsp)\nxor %eax,%eax\ncallq 10d0 \ntest %rax,%rax\nje 1500 \nmov %rax,%r14\nmov %r13,%rdi\nmov %rax,%rbp\nsub %rbx,%r14\nmov %r14d,0x64(%rsp)\ncallq 1090 \nmov %rsp,%rdi\nmov $0x64,%ecx\nmov %rbp,%rsi\nmov %rax,%rbx\nadd %eax,%r14d\nmov %rax,%rdx\nmov %r14d,0x68(%rsp)\ncallq 10c0 <__strncpy_chk@plt>\nmovb $0x0,(%rsp,%rbx,1)\nmov 0x60(%rsp),%rax\nmovdqa (%rsp),%xmm0\nmovdqa 0x10(%rsp),%xmm1\nmovdqa 0x20(%rsp),%xmm2\nmov %rax,0x60(%r12)\nmov 0x68(%rsp),%eax\nmovdqa 0x30(%rsp),%xmm3\nmovdqa 0x40(%rsp),%xmm4\nmovups %xmm0,(%r12)\nmov %eax,0x68(%r12)\nmovdqa 0x50(%rsp),%xmm5\nmovups %xmm1,0x10(%r12)\nmovups %xmm2,0x20(%r12)\nmovups %xmm3,0x30(%r12)\nmovups %xmm4,0x40(%r12)\nmovups %xmm5,0x50(%r12)\nmov 0x78(%rsp),%rax\nxor %fs:0x28,%rax\njne 1512 \nsub $0xffffffffffffff80,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nxchg %ax,%ax\nmovb $0x0,(%rsp)\nmovq $0xffffffffffffffff,0x64(%rsp)\njmpq 1485 \ncallq 10a0 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\nmov r13, rsi\nmov rsi, rdx; needle\npush r12\nmov r12, rdx\npush rbp\npush rbx\nmov rbx, rdi\nmov rdi, r13; haystack\nadd rsp, 0FFFFFFFFFFFFFF80h\nmov rax, fs:28h\nmov [rsp+0A8h+var_30], rax\nxor eax, eax\ncall _strstr\ntest rax, rax\njz loc_14F0\nmov r14, rax\nmov rdi, r12; s\nmov rbp, rax\nsub r14, r13\nmov dword ptr [rsp+0A8h+var_44], r14d\ncall _strlen\nmov rdi, rsp\nmov ecx, 64h ; 'd'\nmov rsi, rbp\nmov r12, rax\nadd r14d, eax\nmov rdx, rax\nmov dword ptr [rsp+0A8h+var_44+4], r14d\ncall ___strncpy_chk\nmov byte ptr [rsp+r12+0A8h+var_A8], 0\nloc_1486:\nmovdqa xmm0, [rsp+0A8h+var_A8]\nmovdqa xmm1, [rsp+0A8h+var_98]\nmovdqa xmm2, [rsp+0A8h+var_88]\nmovdqa xmm3, [rsp+0A8h+var_78]\nmovdqa xmm4, [rsp+0A8h+var_68]\nmovdqa xmm5, [rsp+0A8h+var_58]\nmovups xmmword ptr [rbx], xmm0\nmovdqu xmm6, [rsp+0A8h+var_58+0Ch]\nmovups xmmword ptr [rbx+10h], xmm1\nmovups xmmword ptr [rbx+50h], xmm5\nmovups xmmword ptr [rbx+20h], xmm2\nmovups xmmword ptr [rbx+30h], xmm3\nmovups xmmword ptr [rbx+40h], xmm4\nmovups xmmword ptr [rbx+5Ch], xmm6\nmov rax, [rsp+0A8h+var_30]\nsub rax, fs:28h\njnz short loc_14FF\nsub rsp, 0FFFFFFFFFFFFFF80h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_14F0:\nmov byte ptr [rsp+0A8h+var_A8], 0\nmov [rsp+0A8h+var_44], 0FFFFFFFFFFFFFFFFh\njmp short loc_1486\nloc_14FF:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, const char *a2, const char *a3)\n{\n char *v4; // rax\n char *v5; // rbp\n int v6; // r14d\n size_t v7; // r12\n __m128i v8; // xmm1\n __m128i v9; // xmm2\n __m128i v10; // xmm3\n __m128i v11; // xmm4\n __m128i v12; // xmm5\n __m128i v13; // xmm6\n __m128i v15; // [rsp+0h] [rbp-A8h] BYREF\n __m128i v16; // [rsp+10h] [rbp-98h] BYREF\n __m128i v17; // [rsp+20h] [rbp-88h] BYREF\n __m128i v18; // [rsp+30h] [rbp-78h] BYREF\n __m128i v19; // [rsp+40h] [rbp-68h] BYREF\n __m128i v20; // [rsp+50h] [rbp-58h] BYREF\n __int64 v21; // [rsp+64h] [rbp-44h]\n unsigned __int64 v22; // [rsp+78h] [rbp-30h]\n\n v22 = __readfsqword(0x28u);\n v4 = strstr(a2, a3);\n if ( v4 )\n {\n v5 = v4;\n v6 = (_DWORD)v4 - (_DWORD)a2;\n LODWORD(v21) = (_DWORD)v4 - (_DWORD)a2;\n v7 = strlen(a3);\n HIDWORD(v21) = v7 + v6;\n __strncpy_chk(&v15, v5, v7, 100LL);\n v15.m128i_i8[v7] = 0;\n }\n else\n {\n v15.m128i_i8[0] = 0;\n v21 = -1LL;\n }\n v8 = _mm_load_si128(&v16);\n v9 = _mm_load_si128(&v17);\n v10 = _mm_load_si128(&v18);\n v11 = _mm_load_si128(&v19);\n v12 = _mm_load_si128(&v20);\n *(__m128i *)a1 = _mm_load_si128(&v15);\n v13 = _mm_loadu_si128((const __m128i *)((char *)&v20.m128i_u64[1] + 4));\n *(__m128i *)(a1 + 16) = v8;\n *(__m128i *)(a1 + 80) = v12;\n *(__m128i *)(a1 + 32) = v9;\n *(__m128i *)(a1 + 48) = v10;\n *(__m128i *)(a1 + 64) = v11;\n *(__m128i *)(a1 + 92) = v13;\n return a1;\n}", + "ida_strip_asm": "sub_1410:\nendbr64\npush r14\npush r13\nmov r13, rsi\nmov rsi, rdx; needle\npush r12\nmov r12, rdx\npush rbp\npush rbx\nmov rbx, rdi\nmov rdi, r13; haystack\nadd rsp, 0FFFFFFFFFFFFFF80h\nmov rax, fs:28h\nmov [rsp+0A8h+var_30], rax\nxor eax, eax\ncall _strstr\ntest rax, rax\njz loc_14F0\nmov r14, rax\nmov rdi, r12; s\nmov rbp, rax\nsub r14, r13\nmov dword ptr [rsp+0A8h+var_44], r14d\ncall _strlen\nmov rdi, rsp\nmov ecx, 64h ; 'd'\nmov rsi, rbp\nmov r12, rax\nadd r14d, eax\nmov rdx, rax\nmov dword ptr [rsp+0A8h+var_44+4], r14d\ncall ___strncpy_chk\nmov byte ptr [rsp+r12+0A8h+var_A8], 0\nloc_1486:\nmovdqa xmm0, [rsp+0A8h+var_A8]\nmovdqa xmm1, [rsp+0A8h+var_98]\nmovdqa xmm2, [rsp+0A8h+var_88]\nmovdqa xmm3, [rsp+0A8h+var_78]\nmovdqa xmm4, [rsp+0A8h+var_68]\nmovdqa xmm5, [rsp+0A8h+var_58]\nmovups xmmword ptr [rbx], xmm0\nmovdqu xmm6, [rsp+0A8h+var_58+0Ch]\nmovups xmmword ptr [rbx+10h], xmm1\nmovups xmmword ptr [rbx+50h], xmm5\nmovups xmmword ptr [rbx+20h], xmm2\nmovups xmmword ptr [rbx+30h], xmm3\nmovups xmmword ptr [rbx+40h], xmm4\nmovups xmmword ptr [rbx+5Ch], xmm6\nmov rax, [rsp+0A8h+var_30]\nsub rax, fs:28h\njnz short loc_14FF\nsub rsp, 0FFFFFFFFFFFFFF80h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_14F0:\nmov byte ptr [rsp+0A8h+var_A8], 0\nmov [rsp+0A8h+var_44], 0FFFFFFFFFFFFFFFFh\njmp short loc_1486\nloc_14FF:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1410(__int64 a1, const char *a2, const char *a3)\n{\n char *v4; // rax\n char *v5; // rbp\n int v6; // r14d\n size_t v7; // r12\n __m128i v8; // xmm1\n __m128i v9; // xmm2\n __m128i v10; // xmm3\n __m128i v11; // xmm4\n __m128i v12; // xmm5\n __m128i v13; // xmm6\n __m128i v15; // [rsp+0h] [rbp-A8h] BYREF\n __m128i v16; // [rsp+10h] [rbp-98h] BYREF\n __m128i v17; // [rsp+20h] [rbp-88h] BYREF\n __m128i v18; // [rsp+30h] [rbp-78h] BYREF\n __m128i v19; // [rsp+40h] [rbp-68h] BYREF\n __m128i v20; // [rsp+50h] [rbp-58h] BYREF\n __int64 v21; // [rsp+64h] [rbp-44h]\n unsigned __int64 v22; // [rsp+78h] [rbp-30h]\n\n v22 = __readfsqword(0x28u);\n v4 = strstr(a2, a3);\n if ( v4 )\n {\n v5 = v4;\n v6 = (_DWORD)v4 - (_DWORD)a2;\n LODWORD(v21) = (_DWORD)v4 - (_DWORD)a2;\n v7 = strlen(a3);\n HIDWORD(v21) = v7 + v6;\n __strncpy_chk(&v15, v5, v7, 100LL);\n v15.m128i_i8[v7] = 0;\n }\n else\n {\n v15.m128i_i8[0] = 0;\n v21 = -1LL;\n }\n v8 = _mm_load_si128(&v16);\n v9 = _mm_load_si128(&v17);\n v10 = _mm_load_si128(&v18);\n v11 = _mm_load_si128(&v19);\n v12 = _mm_load_si128(&v20);\n *(__m128i *)a1 = _mm_load_si128(&v15);\n v13 = _mm_loadu_si128((const __m128i *)((char *)&v20.m128i_u64[1] + 4));\n *(__m128i *)(a1 + 16) = v8;\n *(__m128i *)(a1 + 80) = v12;\n *(__m128i *)(a1 + 32) = v9;\n *(__m128i *)(a1 + 48) = v10;\n *(__m128i *)(a1 + 64) = v11;\n *(__m128i *)(a1 + 92) = v13;\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1410(long long a1, const char *a2, const char *a3) {\n char *v4;\n char *v5;\n int v6;\n unsigned int v7;\n __m128i v8;\n __m128i v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i v15;\n __m128i v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n __m128i v20;\n long long v21;\n unsigned long long v22;\n v22 = __readfsqword(40u);\n v4 = strstr(a2, a3);\n if (v4) {\n v5 = v4;\n v6 = (uint32_t)v4 - (uint32_t)a2;\n LODWORD(v21) = (uint32_t)v4 - (uint32_t)a2;\n v7 = strlen(a3);\n HIDWORD(v21) = v7 + v6;\n __strncpy_chk(&v15, v5, v7, 100LL);\n v15.m128i_i8[v7] = 0;\n } else {\n v15.m128i_i8[0] = 0;\n v21 = -1LL;\n }\n v8 = _mm_load_si128(&v16);\n v9 = _mm_load_si128(&v17);\n v10 = _mm_load_si128(&v18);\n v11 = _mm_load_si128(&v19);\n v12 = _mm_load_si128(&v20);\n *(__m128i *)a1 = _mm_load_si128(&v15);\n v13 = _mm_loadu_si128((const __m128i *)((char *)&v20.m128i_u64[1] + 4));\n *(__m128i *)(a1 + 16) = v8;\n *(__m128i *)(a1 + 80) = v12;\n *(__m128i *)(a1 + 32) = v9;\n *(__m128i *)(a1 + 48) = v10;\n *(__m128i *)(a1 + 64) = v11;\n *(__m128i *)(a1 + 92) = v13;\n return a1;\n}", + "ida_pseudo_norm": "long long func0(long long a1, const char *a2, const char *a3) {\n char *v4;\n char *v5;\n int v6;\n unsigned int v7;\n __m128i v8;\n __m128i v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i v15;\n __m128i v16;\n __m128i v17;\n __m128i v18;\n __m128i v19;\n __m128i v20;\n long long v21;\n unsigned long long v22;\n v22 = __readfsqword(40u);\n v4 = strstr(a2, a3);\n if (v4) {\n v5 = v4;\n v6 = (uint32_t)v4 - (uint32_t)a2;\n LODWORD(v21) = (uint32_t)v4 - (uint32_t)a2;\n v7 = strlen(a3);\n HIDWORD(v21) = v7 + v6;\n __strncpy_chk(&v15, v5, v7, 100LL);\n v15.m128i_i8[v7] = 0;\n } else {\n v15.m128i_i8[0] = 0;\n v21 = -1LL;\n }\n v8 = _mm_load_si128(&v16);\n v9 = _mm_load_si128(&v17);\n v10 = _mm_load_si128(&v18);\n v11 = _mm_load_si128(&v19);\n v12 = _mm_load_si128(&v20);\n *(__m128i *)a1 = _mm_load_si128(&v15);\n v13 = _mm_loadu_si128((const __m128i *)((char *)&v20.m128i_u64[1] + 4));\n *(__m128i *)(a1 + 16) = v8;\n *(__m128i *)(a1 + 80) = v12;\n *(__m128i *)(a1 + 32) = v9;\n *(__m128i *)(a1 + 48) = v10;\n *(__m128i *)(a1 + 64) = v11;\n *(__m128i *)(a1 + 92) = v13;\n return a1;\n}" + }, + { + "index": 774, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* email) {\n const char* regex_pattern = \"^[a-z0-9]+[\\\\._]?[a-z0-9]+[@]\\\\w+[.]\\\\w{2,3}$\";\n regex_t regex;\n int ret;\n ret = regcomp(®ex, regex_pattern, REG_EXTENDED | REG_NOSUB);\n if (ret) {\n return \"Invalid Email\";\n }\n ret = regexec(®ex, email, 0, NULL, 0);\n regfree(®ex);\n if (!ret) {\n return \"Valid Email\";\n } else {\n return \"Invalid Email\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"ankitrai326@gmail.com\"), \"Valid Email\") == 0);\n\n assert(strcmp(func0(\"my.ownsite@ourearth.org\"), \"Valid Email\") == 0);\n\n assert(strcmp(func0(\"ankitaoie326.com\"), \"Invalid Email\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x70,%rsp\nmov %rdi,-0x68(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0xdf9(%rip),%rax\nmov %rax,-0x58(%rbp)\nmov -0x58(%rbp),%rcx\nlea -0x50(%rbp),%rax\nmov $0x9,%edx\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 10d0 \nmov %eax,-0x5c(%rbp)\ncmpl $0x0,-0x5c(%rbp)\nje 123d \nlea 0xdf8(%rip),%rax\njmp 1282 \nmov -0x68(%rbp),%rsi\nlea -0x50(%rbp),%rax\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rax,%rdi\ncallq 10f0 \nmov %eax,-0x5c(%rbp)\nlea -0x50(%rbp),%rax\nmov %rax,%rdi\ncallq 10a0 \ncmpl $0x0,-0x5c(%rbp)\njne 127b \nlea 0xdc8(%rip),%rax\njmp 1282 \nlea 0xdb1(%rip),%rax\nmov -0x8(%rbp),%rdx\nxor %fs:0x28,%rdx\nje 1296 \ncallq 10b0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aAZ09AZ09WW23; \"^[a-z0-9]+[\\\\._]?[a-z0-9]+[@]\\\\w+[.]\\\\w\"...\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 9; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+var_5C], eax\ncmp [rbp+var_5C], 0\njz short loc_123D\nlea rax, aInvalidEmail; \"Invalid Email\"\njmp short loc_1282\nloc_123D:\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_5C], eax\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\ncmp [rbp+var_5C], 0\njnz short loc_127B\nlea rax, s2; \"Valid Email\"\njmp short loc_1282\nloc_127B:\nlea rax, aInvalidEmail; \"Invalid Email\"\nloc_1282:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1296\ncall ___stack_chk_fail\nlocret_1296:\nleave\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n int v2; // [rsp+14h] [rbp-5Ch]\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n unsigned __int64 v4; // [rsp+68h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"^[a-z0-9]+[\\\\._]?[a-z0-9]+[@]\\\\w+[.]\\\\w{2,3}$\", 9) )\n return \"Invalid Email\";\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if ( v2 )\n return \"Invalid Email\";\n else\n return \"Valid Email\";\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aAZ09AZ09WW23; \"^[a-z0-9]+[\\\\._]?[a-z0-9]+[@]\\\\w+[.]\\\\w\"...\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 9; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+var_5C], eax\ncmp [rbp+var_5C], 0\njz short loc_123D\nlea rax, aInvalidEmail; \"Invalid Email\"\njmp short loc_1282\nloc_123D:\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_5C], eax\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\ncmp [rbp+var_5C], 0\njnz short loc_127B\nlea rax, s2; \"Valid Email\"\njmp short loc_1282\nloc_127B:\nlea rax, aInvalidEmail; \"Invalid Email\"\nloc_1282:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1296\ncall ___stack_chk_fail\nlocret_1296:\nleave\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_11E9(const char *a1)\n{\n int v2; // [rsp+14h] [rbp-5Ch]\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n unsigned __int64 v4; // [rsp+68h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"^[a-z0-9]+[\\\\._]?[a-z0-9]+[@]\\\\w+[.]\\\\w{2,3}$\", 9) )\n return \"Invalid Email\";\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if ( v2 )\n return \"Invalid Email\";\n else\n return \"Valid Email\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_11E9(const char *a1) {\n int v2;\n regex_t preg;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n if (regcomp(&preg, \"^[a-z0-9]+[\\\\._]?[a-z0-9]+[@]\\\\w+[.]\\\\w{2,3}$\", 9))\n return \"Invalid Email\";\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if (v2)\n return \"Invalid Email\";\n else\n return \"Valid Email\";\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n int v2;\n regex_t preg;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n if (regcomp(&preg, \"^[a-z0-9]+[\\\\._]?[a-z0-9]+[@]\\\\w+[.]\\\\w{2,3}$\", 9))\n return \"Invalid Email\";\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if (v2)\n return \"Invalid Email\";\n else\n return \"Valid Email\";\n}" + }, + { + "index": 774, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* email) {\n const char* regex_pattern = \"^[a-z0-9]+[\\\\._]?[a-z0-9]+[@]\\\\w+[.]\\\\w{2,3}$\";\n regex_t regex;\n int ret;\n ret = regcomp(®ex, regex_pattern, REG_EXTENDED | REG_NOSUB);\n if (ret) {\n return \"Invalid Email\";\n }\n ret = regexec(®ex, email, 0, NULL, 0);\n regfree(®ex);\n if (!ret) {\n return \"Valid Email\";\n } else {\n return \"Invalid Email\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"ankitrai326@gmail.com\"), \"Valid Email\") == 0);\n\n assert(strcmp(func0(\"my.ownsite@ourearth.org\"), \"Valid Email\") == 0);\n\n assert(strcmp(func0(\"ankitaoie326.com\"), \"Invalid Email\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x58,%rsp\nmov %rdi,%rbx\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nmov $0x9,%edx\nlea 0xe6b(%rip),%rsi\ncallq 10c0 \nmov %eax,%edx\nlea 0xe01(%rip),%rax\ntest %edx,%edx\nje 121e \nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 125c \nadd $0x58,%rsp\npop %rbx\npop %rbp\nretq\nmov %rsp,%rbp\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rbx,%rsi\nmov %rbp,%rdi\ncallq 10d0 \nmov %eax,%ebx\nmov %rbp,%rdi\ncallq 1090 \ntest %ebx,%ebx\nlea 0xdc3(%rip),%rax\nlea 0xdae(%rip),%rdx\ncmovne %rdx,%rax\njmp 1207 \ncallq 10a0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+68h+var_20], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 9; cflags\nlea rsi, pattern; \"^[a-z0-9]+[\\\\._]?[a-z0-9]+[@]\\\\w+[.]\\\\w\"...\ncall _regcomp\nmov edx, eax\nlea rax, aInvalidEmail; \"Invalid Email\"\ntest edx, edx\njz short loc_123E\nloc_1227:\nmov rdx, [rsp+68h+var_20]\nsub rdx, fs:28h\njnz short loc_127C\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_123E:\nmov rbp, rsp\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov ebx, eax\nmov rdi, rbp; preg\ncall _regfree\ntest ebx, ebx\nlea rax, aInvalidEmail; \"Invalid Email\"\nlea rdx, s2; \"Valid Email\"\ncmovz rax, rdx\njmp short loc_1227\nloc_127C:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // edx\n const char *result; // rax\n int v3; // ebx\n regex_t v4; // [rsp+0h] [rbp-68h] BYREF\n unsigned __int64 v5; // [rsp+48h] [rbp-20h]\n\n v5 = __readfsqword(0x28u);\n v1 = regcomp(&v4, \"^[a-z0-9]+[\\\\._]?[a-z0-9]+[@]\\\\w+[.]\\\\w{2,3}$\", 9);\n result = \"Invalid Email\";\n if ( !v1 )\n {\n v3 = regexec(&v4, string, 0LL, 0LL, 0);\n regfree(&v4);\n result = \"Invalid Email\";\n if ( !v3 )\n return \"Valid Email\";\n }\n return result;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+68h+var_20], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 9; cflags\nlea rsi, pattern; \"^[a-z0-9]+[\\\\._]?[a-z0-9]+[@]\\\\w+[.]\\\\w\"...\ncall _regcomp\nmov edx, eax\nlea rax, aInvalidEmail; \"Invalid Email\"\ntest edx, edx\njz short loc_123E\nloc_1227:\nmov rdx, [rsp+68h+var_20]\nsub rdx, fs:28h\njnz short loc_127C\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_123E:\nmov rbp, rsp\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov ebx, eax\nmov rdi, rbp; preg\ncall _regfree\ntest ebx, ebx\nlea rax, aInvalidEmail; \"Invalid Email\"\nlea rdx, s2; \"Valid Email\"\ncmovz rax, rdx\njmp short loc_1227\nloc_127C:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_11E9(char *string)\n{\n int v1; // edx\n const char *result; // rax\n int v3; // ebx\n regex_t v4; // [rsp+0h] [rbp-68h] BYREF\n unsigned __int64 v5; // [rsp+48h] [rbp-20h]\n\n v5 = __readfsqword(0x28u);\n v1 = regcomp(&v4, \"^[a-z0-9]+[\\\\._]?[a-z0-9]+[@]\\\\w+[.]\\\\w{2,3}$\", 9);\n result = \"Invalid Email\";\n if ( !v1 )\n {\n v3 = regexec(&v4, string, 0LL, 0LL, 0);\n regfree(&v4);\n result = \"Invalid Email\";\n if ( !v3 )\n return \"Valid Email\";\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_11E9(char *string) {\n int v1;\n const char *result;\n int v3;\n regex_t v4;\n unsigned long long v5;\n v5 = __readfsqword(40u);\n v1 = regcomp(&v4, \"^[a-z0-9]+[\\\\._]?[a-z0-9]+[@]\\\\w+[.]\\\\w{2,3}$\", 9);\n result = \"Invalid Email\";\n if (!v1) {\n v3 = regexec(&v4, string, 0LL, 0LL, 0);\n regfree(&v4);\n result = \"Invalid Email\";\n if (!v3) return \"Valid Email\";\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n const char *result;\n int v3;\n regex_t v4;\n unsigned long long v5;\n v5 = __readfsqword(40u);\n v1 = regcomp(&v4, \"^[a-z0-9]+[\\\\._]?[a-z0-9]+[@]\\\\w+[.]\\\\w{2,3}$\", 9);\n result = \"Invalid Email\";\n if (!v1) {\n v3 = regexec(&v4, string, 0LL, 0LL, 0);\n regfree(&v4);\n result = \"Invalid Email\";\n if (!v3) return \"Valid Email\";\n }\n return result;\n}" + }, + { + "index": 774, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* email) {\n const char* regex_pattern = \"^[a-z0-9]+[\\\\._]?[a-z0-9]+[@]\\\\w+[.]\\\\w{2,3}$\";\n regex_t regex;\n int ret;\n ret = regcomp(®ex, regex_pattern, REG_EXTENDED | REG_NOSUB);\n if (ret) {\n return \"Invalid Email\";\n }\n ret = regexec(®ex, email, 0, NULL, 0);\n regfree(®ex);\n if (!ret) {\n return \"Valid Email\";\n } else {\n return \"Invalid Email\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"ankitrai326@gmail.com\"), \"Valid Email\") == 0);\n\n assert(strcmp(func0(\"my.ownsite@ourearth.org\"), \"Valid Email\") == 0);\n\n assert(strcmp(func0(\"ankitaoie326.com\"), \"Invalid Email\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov $0x9,%edx\nlea 0xd9e(%rip),%rsi\npush %rbp\nmov %rdi,%rbp\nsub $0x58,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%r12\nmov %r12,%rdi\ncallq 10c0 \ntest %eax,%eax\nje 1310 \nlea 0xd14(%rip),%rax\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 1339 \nadd $0x58,%rsp\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax,%rax,1)\nmov %rbp,%rsi\nxor %r8d,%r8d\nxor %ecx,%ecx\nxor %edx,%edx\nmov %r12,%rdi\ncallq 10d0 \nmov %r12,%rdi\nmov %eax,%ebp\ncallq 1090 \nlea 0xcdf(%rip),%rax\ntest %ebp,%ebp\nje 12f0 \njmp 12e9 \ncallq 10a0 <__stack_chk_fail@plt>\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov edx, 9; cflags\nlea rsi, pattern; \"^[a-z0-9]+[\\\\._]?[a-z0-9]+[@]\\\\w+[.]\\\\w\"...\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njz short loc_1320\nloc_12F8:\nlea rax, aInvalidEmail; \"Invalid Email\"\nloc_12FF:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_1349\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1320:\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\njnz short loc_12F8\nlea rax, s2; \"Valid Email\"\njmp short loc_12FF\nloc_1349:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v2; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n if ( regcomp(&_0, \"^[a-z0-9]+[\\\\._]?[a-z0-9]+[@]\\\\w+[.]\\\\w{2,3}$\", 9) )\n return \"Invalid Email\";\n v2 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n if ( v2 )\n return \"Invalid Email\";\n else\n return \"Valid Email\";\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\npush rbp\nmov edx, 9; cflags\nlea rsi, pattern; \"^[a-z0-9]+[\\\\._]?[a-z0-9]+[@]\\\\w+[.]\\\\w\"...\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njz short loc_1320\nloc_12F8:\nlea rax, aInvalidEmail; \"Invalid Email\"\nloc_12FF:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_1349\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1320:\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\njnz short loc_12F8\nlea rax, s2; \"Valid Email\"\njmp short loc_12FF\nloc_1349:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_12C0(char *string)\n{\n int v2; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n if ( regcomp(&_0, \"^[a-z0-9]+[\\\\._]?[a-z0-9]+[@]\\\\w+[.]\\\\w{2,3}$\", 9) )\n return \"Invalid Email\";\n v2 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n if ( v2 )\n return \"Invalid Email\";\n else\n return \"Valid Email\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_12C0(char *string) {\n int v2;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n if (regcomp(&_0, \"^[a-z0-9]+[\\\\._]?[a-z0-9]+[@]\\\\w+[.]\\\\w{2,3}$\", 9))\n return \"Invalid Email\";\n v2 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n if (v2)\n return \"Invalid Email\";\n else\n return \"Valid Email\";\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v2;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n if (regcomp(&_0, \"^[a-z0-9]+[\\\\._]?[a-z0-9]+[@]\\\\w+[.]\\\\w{2,3}$\", 9))\n return \"Invalid Email\";\n v2 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n if (v2)\n return \"Invalid Email\";\n else\n return \"Valid Email\";\n}" + }, + { + "index": 774, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* email) {\n const char* regex_pattern = \"^[a-z0-9]+[\\\\._]?[a-z0-9]+[@]\\\\w+[.]\\\\w{2,3}$\";\n regex_t regex;\n int ret;\n ret = regcomp(®ex, regex_pattern, REG_EXTENDED | REG_NOSUB);\n if (ret) {\n return \"Invalid Email\";\n }\n ret = regexec(®ex, email, 0, NULL, 0);\n regfree(®ex);\n if (!ret) {\n return \"Valid Email\";\n } else {\n return \"Invalid Email\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"ankitrai326@gmail.com\"), \"Valid Email\") == 0);\n\n assert(strcmp(func0(\"my.ownsite@ourearth.org\"), \"Valid Email\") == 0);\n\n assert(strcmp(func0(\"ankitaoie326.com\"), \"Invalid Email\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov $0x9,%edx\nlea 0xd9e(%rip),%rsi\npush %rbp\nmov %rdi,%rbp\nsub $0x58,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%r12\nmov %r12,%rdi\ncallq 10c0 \ntest %eax,%eax\nje 1310 \nlea 0xd14(%rip),%rax\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 1339 \nadd $0x58,%rsp\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax,%rax,1)\nmov %rbp,%rsi\nxor %r8d,%r8d\nxor %ecx,%ecx\nxor %edx,%edx\nmov %r12,%rdi\ncallq 10d0 \nmov %r12,%rdi\nmov %eax,%ebp\ncallq 1090 \nlea 0xcdf(%rip),%rax\ntest %ebp,%ebp\nje 12f0 \njmp 12e9 \ncallq 10a0 <__stack_chk_fail@plt>\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov edx, 9; cflags\nlea rsi, pattern; \"^[a-z0-9]+[\\\\._]?[a-z0-9]+[@]\\\\w+[.]\\\\w\"...\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njz short loc_1320\nloc_12F8:\nlea rax, aInvalidEmail; \"Invalid Email\"\nloc_12FF:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_1349\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1320:\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\njnz short loc_12F8\nlea rax, s2; \"Valid Email\"\njmp short loc_12FF\nloc_1349:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v2; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n if ( regcomp(&_0, \"^[a-z0-9]+[\\\\._]?[a-z0-9]+[@]\\\\w+[.]\\\\w{2,3}$\", 9) )\n return \"Invalid Email\";\n v2 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n if ( v2 )\n return \"Invalid Email\";\n else\n return \"Valid Email\";\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\npush rbp\nmov edx, 9; cflags\nlea rsi, pattern; \"^[a-z0-9]+[\\\\._]?[a-z0-9]+[@]\\\\w+[.]\\\\w\"...\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njz short loc_1320\nloc_12F8:\nlea rax, aInvalidEmail; \"Invalid Email\"\nloc_12FF:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_1349\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1320:\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\njnz short loc_12F8\nlea rax, s2; \"Valid Email\"\njmp short loc_12FF\nloc_1349:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_12C0(char *string)\n{\n int v2; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n if ( regcomp(&_0, \"^[a-z0-9]+[\\\\._]?[a-z0-9]+[@]\\\\w+[.]\\\\w{2,3}$\", 9) )\n return \"Invalid Email\";\n v2 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n if ( v2 )\n return \"Invalid Email\";\n else\n return \"Valid Email\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_12C0(char *string) {\n int v2;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n if (regcomp(&_0, \"^[a-z0-9]+[\\\\._]?[a-z0-9]+[@]\\\\w+[.]\\\\w{2,3}$\", 9))\n return \"Invalid Email\";\n v2 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n if (v2)\n return \"Invalid Email\";\n else\n return \"Valid Email\";\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v2;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n if (regcomp(&_0, \"^[a-z0-9]+[\\\\._]?[a-z0-9]+[@]\\\\w+[.]\\\\w{2,3}$\", 9))\n return \"Invalid Email\";\n v2 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n if (v2)\n return \"Invalid Email\";\n else\n return \"Valid Email\";\n}" + }, + { + "index": 775, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const int* nums, int size) {\n for (int i = 0; i < size; i++) {\n if (nums[i] % 2 != i % 2) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n int arr1[] = {2, 1, 4, 3, 6, 7, 6, 3};\n\n int arr2[] = {4, 1, 2};\n\n int arr3[] = {1, 2, 3};\n\n \n\n assert(func0(arr1, sizeof(arr1)/sizeof(arr1[0])));\n\n assert(func0(arr2, sizeof(arr2)/sizeof(arr2[0])));\n\n assert(!func0(arr3, sizeof(arr3)/sizeof(arr3[0])));\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11c1 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncltd\nshr $0x1f,%edx\nadd %edx,%eax\nand $0x1,%eax\nsub %edx,%eax\nmov %eax,%ecx\nmov -0x4(%rbp),%eax\ncltd\nshr $0x1f,%edx\nadd %edx,%eax\nand $0x1,%eax\nsub %edx,%eax\ncmp %eax,%ecx\nje 11bd \nmov $0x0,%eax\njmp 11ce \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1181 \nmov $0x1,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 0\njmp short loc_11CB\nloc_1181:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov ecx, edx\nmov edx, [rbp+var_4]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\ncmp ecx, eax\njz short loc_11C7\nmov eax, 0\njmp short loc_11D8\nloc_11C7:\nadd [rbp+var_4], 1\nloc_11CB:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1181\nmov eax, 1\nloc_11D8:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) % 2 != i % 2 )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 0\njmp short loc_11CB\nloc_1181:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov ecx, edx\nmov edx, [rbp+var_4]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\ncmp ecx, eax\njz short loc_11C7\nmov eax, 0\njmp short loc_11D8\nloc_11C7:\nadd [rbp+var_4], 1\nloc_11CB:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1181\nmov eax, 1\nloc_11D8:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) % 2 != i % 2 )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int i;\n for (i = 0; i < a2; ++i) {\n if (*(uint32_t *)(4LL * i + a1) % 2 != i % 2) return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int i;\n for (i = 0; i < a2; ++i) {\n if (*(uint32_t *)(4LL * i + a1) % 2 != i % 2) return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": 775, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const int* nums, int size) {\n for (int i = 0; i < size; i++) {\n if (nums[i] % 2 != i % 2) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n int arr1[] = {2, 1, 4, 3, 6, 7, 6, 3};\n\n int arr2[] = {4, 1, 2};\n\n int arr3[] = {1, 2, 3};\n\n \n\n assert(func0(arr1, sizeof(arr1)/sizeof(arr1[0])));\n\n assert(func0(arr2, sizeof(arr2)/sizeof(arr2[0])));\n\n assert(!func0(arr3, sizeof(arr3)/sizeof(arr3[0])));\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11ae \nlea -0x1(%rsi),%r8d\nmov $0x0,%ecx\njmp 117f \nmov %rax,%rcx\nmov (%rdi,%rcx,4),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nand $0x1,%eax\nsub %edx,%eax\nmov %ecx,%esi\nshr $0x1f,%esi\nlea (%rsi,%rcx,1),%edx\nand $0x1,%edx\nsub %esi,%edx\ncmp %edx,%eax\njne 11b4 \nlea 0x1(%rcx),%rax\ncmp %r8,%rcx\njne 117c \nmov $0x1,%eax\nretq\nmov $0x1,%eax\nretq\nmov $0x0,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11AC\nmovsxd rsi, esi\nmov ecx, 0\nloc_1179:\nmov eax, [rdi+rcx*4]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nand eax, 1\nsub eax, edx\nmov r8d, ecx\nshr r8d, 1Fh\nlea edx, [r8+rcx]\nand edx, 1\nsub edx, r8d\ncmp eax, edx\njnz short loc_11B2\nadd rcx, 1\ncmp rcx, rsi\njnz short loc_1179\nmov eax, 1\nretn\nloc_11AC:\nmov eax, 1\nretn\nloc_11B2:\nmov eax, 0\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // rcx\n\n if ( a2 <= 0 )\n return 1LL;\n v2 = 0LL;\n while ( *(_DWORD *)(a1 + 4 * v2) % 2 == (int)v2 % 2 )\n {\n if ( ++v2 == a2 )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11AC\nmovsxd rsi, esi\nmov ecx, 0\nloc_1179:\nmov eax, [rdi+rcx*4]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nand eax, 1\nsub eax, edx\nmov r8d, ecx\nshr r8d, 1Fh\nlea edx, [r8+rcx]\nand edx, 1\nsub edx, r8d\ncmp eax, edx\njnz short loc_11B2\nadd rcx, 1\ncmp rcx, rsi\njnz short loc_1179\nmov eax, 1\nretn\nloc_11AC:\nmov eax, 1\nretn\nloc_11B2:\nmov eax, 0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n __int64 v2; // rcx\n\n if ( a2 <= 0 )\n return 1LL;\n v2 = 0LL;\n while ( *(_DWORD *)(a1 + 4 * v2) % 2 == (int)v2 % 2 )\n {\n if ( ++v2 == a2 )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n long long v2;\n if (a2 <= 0) return 1LL;\n v2 = 0LL;\n while (*(uint32_t *)(a1 + 4 * v2) % 2 == (int)v2 % 2) {\n if (++v2 == a2) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n if (a2 <= 0) return 1LL;\n v2 = 0LL;\n while (*(uint32_t *)(a1 + 4 * v2) % 2 == (int)v2 % 2) {\n if (++v2 == a2) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 776, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *test_str) {\n int res = 0;\n const char *vow_list = \"aeiou\";\n int len = strlen(test_str);\n for (int idx = 1; idx < len - 1; idx++) {\n if (strchr(vow_list, test_str[idx]) == NULL &&\n (strchr(vow_list, test_str[idx - 1]) != NULL ||\n strchr(vow_list, test_str[idx + 1]) != NULL)) {\n res += 1;\n }\n }\n if (strchr(vow_list, test_str[0]) == NULL &&\n strchr(vow_list, test_str[1]) != NULL) {\n res += 1;\n }\n if (strchr(vow_list, test_str[len - 1]) == NULL &&\n strchr(vow_list, test_str[len - 2]) != NULL) {\n res += 1;\n }\n return res;\n}", + "test": "int main() {\n\n assert(func0(\"bestinstareels\") == 7);\n\n assert(func0(\"partofthejourneyistheend\") == 12);\n\n assert(func0(\"amazonprime\") == 5);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x28(%rbp)\nmovl $0x0,-0x14(%rbp)\nlea 0xe61(%rip),%rax\nmov %rax,-0x8(%rbp)\nmov -0x28(%rbp),%rax\nmov %rax,%rdi\ncallq 1070 \nmov %eax,-0xc(%rbp)\nmovl $0x1,-0x10(%rbp)\njmpq 1246 \nmov -0x10(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmovsbl %al,%edx\nmov -0x8(%rbp),%rax\nmov %edx,%esi\nmov %rax,%rdi\ncallq 1080 \ntest %rax,%rax\njne 1242 \nmov -0x10(%rbp),%eax\ncltq\nlea -0x1(%rax),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmovsbl %al,%edx\nmov -0x8(%rbp),%rax\nmov %edx,%esi\nmov %rax,%rdi\ncallq 1080 \ntest %rax,%rax\njne 123e \nmov -0x10(%rbp),%eax\ncltq\nlea 0x1(%rax),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmovsbl %al,%edx\nmov -0x8(%rbp),%rax\nmov %edx,%esi\nmov %rax,%rdi\ncallq 1080 \ntest %rax,%rax\nje 1242 \naddl $0x1,-0x14(%rbp)\naddl $0x1,-0x10(%rbp)\nmov -0xc(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x10(%rbp)\njl 11c6 \nmov -0x28(%rbp),%rax\nmovzbl (%rax),%eax\nmovsbl %al,%edx\nmov -0x8(%rbp),%rax\nmov %edx,%esi\nmov %rax,%rdi\ncallq 1080 \ntest %rax,%rax\njne 1297 \nmov -0x28(%rbp),%rax\nadd $0x1,%rax\nmovzbl (%rax),%eax\nmovsbl %al,%edx\nmov -0x8(%rbp),%rax\nmov %edx,%esi\nmov %rax,%rdi\ncallq 1080 \ntest %rax,%rax\nje 1297 \naddl $0x1,-0x14(%rbp)\nmov -0xc(%rbp),%eax\ncltq\nlea -0x1(%rax),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmovsbl %al,%edx\nmov -0x8(%rbp),%rax\nmov %edx,%esi\nmov %rax,%rdi\ncallq 1080 \ntest %rax,%rax\njne 12ed \nmov -0xc(%rbp),%eax\ncltq\nlea -0x2(%rax),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmovsbl %al,%edx\nmov -0x8(%rbp),%rax\nmov %edx,%esi\nmov %rax,%rdi\ncallq 1080 \ntest %rax,%rax\nje 12ed \naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov [rbp+var_14], 0\nlea rax, aAeiou; \"aeiou\"\nmov [rbp+var_8], rax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_C], eax\nmov [rbp+var_10], 1\njmp loc_1246\nloc_11C6:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx edx, al\nmov rax, [rbp+var_8]\nmov esi, edx; c\nmov rdi, rax; s\ncall _strchr\ntest rax, rax\njnz short loc_1242\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx edx, al\nmov rax, [rbp+var_8]\nmov esi, edx; c\nmov rdi, rax; s\ncall _strchr\ntest rax, rax\njnz short loc_123E\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, [rax+1]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx edx, al\nmov rax, [rbp+var_8]\nmov esi, edx; c\nmov rdi, rax; s\ncall _strchr\ntest rax, rax\njz short loc_1242\nloc_123E:\nadd [rbp+var_14], 1\nloc_1242:\nadd [rbp+var_10], 1\nloc_1246:\nmov eax, [rbp+var_C]\nsub eax, 1\ncmp [rbp+var_10], eax\njl loc_11C6\nmov rax, [rbp+s]\nmovzx eax, byte ptr [rax]\nmovsx edx, al\nmov rax, [rbp+var_8]\nmov esi, edx; c\nmov rdi, rax; s\ncall _strchr\ntest rax, rax\njnz short loc_1297\nmov rax, [rbp+s]\nadd rax, 1\nmovzx eax, byte ptr [rax]\nmovsx edx, al\nmov rax, [rbp+var_8]\nmov esi, edx; c\nmov rdi, rax; s\ncall _strchr\ntest rax, rax\njz short loc_1297\nadd [rbp+var_14], 1\nloc_1297:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx edx, al\nmov rax, [rbp+var_8]\nmov esi, edx; c\nmov rdi, rax; s\ncall _strchr\ntest rax, rax\njnz short loc_12ED\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, [rax-2]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx edx, al\nmov rax, [rbp+var_8]\nmov esi, edx; c\nmov rdi, rax; s\ncall _strchr\ntest rax, rax\njz short loc_12ED\nadd [rbp+var_14], 1\nloc_12ED:\nmov eax, [rbp+var_14]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n unsigned int v2; // [rsp+1Ch] [rbp-14h]\n int i; // [rsp+20h] [rbp-10h]\n int v4; // [rsp+24h] [rbp-Ch]\n\n v2 = 0;\n v4 = strlen(a1);\n for ( i = 1; i < v4 - 1; ++i )\n {\n if ( !strchr(\"aeiou\", a1[i]) && (strchr(\"aeiou\", a1[i - 1]) || strchr(\"aeiou\", a1[i + 1])) )\n ++v2;\n }\n if ( !strchr(\"aeiou\", *a1) && strchr(\"aeiou\", a1[1]) )\n ++v2;\n if ( !strchr(\"aeiou\", a1[v4 - 1]) && strchr(\"aeiou\", a1[v4 - 2]) )\n ++v2;\n return v2;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov [rbp+var_14], 0\nlea rax, aAeiou; \"aeiou\"\nmov [rbp+var_8], rax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_C], eax\nmov [rbp+var_10], 1\njmp loc_1246\nloc_11C6:\nmov eax, [rbp+var_10]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx edx, al\nmov rax, [rbp+var_8]\nmov esi, edx; c\nmov rdi, rax; s\ncall _strchr\ntest rax, rax\njnz short loc_1242\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx edx, al\nmov rax, [rbp+var_8]\nmov esi, edx; c\nmov rdi, rax; s\ncall _strchr\ntest rax, rax\njnz short loc_123E\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, [rax+1]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx edx, al\nmov rax, [rbp+var_8]\nmov esi, edx; c\nmov rdi, rax; s\ncall _strchr\ntest rax, rax\njz short loc_1242\nloc_123E:\nadd [rbp+var_14], 1\nloc_1242:\nadd [rbp+var_10], 1\nloc_1246:\nmov eax, [rbp+var_C]\nsub eax, 1\ncmp [rbp+var_10], eax\njl loc_11C6\nmov rax, [rbp+s]\nmovzx eax, byte ptr [rax]\nmovsx edx, al\nmov rax, [rbp+var_8]\nmov esi, edx; c\nmov rdi, rax; s\ncall _strchr\ntest rax, rax\njnz short loc_1297\nmov rax, [rbp+s]\nadd rax, 1\nmovzx eax, byte ptr [rax]\nmovsx edx, al\nmov rax, [rbp+var_8]\nmov esi, edx; c\nmov rdi, rax; s\ncall _strchr\ntest rax, rax\njz short loc_1297\nadd [rbp+var_14], 1\nloc_1297:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx edx, al\nmov rax, [rbp+var_8]\nmov esi, edx; c\nmov rdi, rax; s\ncall _strchr\ntest rax, rax\njnz short loc_12ED\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, [rax-2]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx edx, al\nmov rax, [rbp+var_8]\nmov esi, edx; c\nmov rdi, rax; s\ncall _strchr\ntest rax, rax\njz short loc_12ED\nadd [rbp+var_14], 1\nloc_12ED:\nmov eax, [rbp+var_14]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(const char *a1)\n{\n unsigned int v2; // [rsp+1Ch] [rbp-14h]\n int i; // [rsp+20h] [rbp-10h]\n int v4; // [rsp+24h] [rbp-Ch]\n\n v2 = 0;\n v4 = strlen(a1);\n for ( i = 1; i < v4 - 1; ++i )\n {\n if ( !strchr(\"aeiou\", a1[i]) && (strchr(\"aeiou\", a1[i - 1]) || strchr(\"aeiou\", a1[i + 1])) )\n ++v2;\n }\n if ( !strchr(\"aeiou\", *a1) && strchr(\"aeiou\", a1[1]) )\n ++v2;\n if ( !strchr(\"aeiou\", a1[v4 - 1]) && strchr(\"aeiou\", a1[v4 - 2]) )\n ++v2;\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(const char *a1) {\n unsigned int v2;\n int i;\n int v4;\n v2 = 0;\n v4 = strlen(a1);\n for (i = 1; i < v4 - 1; ++i) {\n if (!strchr(\"aeiou\", a1[i]) &&\n (strchr(\"aeiou\", a1[i - 1]) || strchr(\"aeiou\", a1[i + 1])))\n ++v2;\n }\n if (!strchr(\"aeiou\", *a1) && strchr(\"aeiou\", a1[1])) ++v2;\n if (!strchr(\"aeiou\", a1[v4 - 1]) && strchr(\"aeiou\", a1[v4 - 2])) ++v2;\n return v2;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n unsigned int v2;\n int i;\n int v4;\n v2 = 0;\n v4 = strlen(a1);\n for (i = 1; i < v4 - 1; ++i) {\n if (!strchr(\"aeiou\", a1[i]) &&\n (strchr(\"aeiou\", a1[i - 1]) || strchr(\"aeiou\", a1[i + 1])))\n ++v2;\n }\n if (!strchr(\"aeiou\", *a1) && strchr(\"aeiou\", a1[1])) ++v2;\n if (!strchr(\"aeiou\", a1[v4 - 1]) && strchr(\"aeiou\", a1[v4 - 2])) ++v2;\n return v2;\n}" + }, + { + "index": 776, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *test_str) {\n int res = 0;\n const char *vow_list = \"aeiou\";\n int len = strlen(test_str);\n for (int idx = 1; idx < len - 1; idx++) {\n if (strchr(vow_list, test_str[idx]) == NULL &&\n (strchr(vow_list, test_str[idx - 1]) != NULL ||\n strchr(vow_list, test_str[idx + 1]) != NULL)) {\n res += 1;\n }\n }\n if (strchr(vow_list, test_str[0]) == NULL &&\n strchr(vow_list, test_str[1]) != NULL) {\n res += 1;\n }\n if (strchr(vow_list, test_str[len - 1]) == NULL &&\n strchr(vow_list, test_str[len - 2]) != NULL) {\n res += 1;\n }\n return res;\n}", + "test": "int main() {\n\n assert(func0(\"bestinstareels\") == 7);\n\n assert(func0(\"partofthejourneyistheend\") == 12);\n\n assert(func0(\"amazonprime\") == 5);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov %rdi,%r14\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nlea -0x1(%rcx),%rbp\ncmp $0x2,%ebp\njle 11fd \nmov %r14,%rbx\nlea -0x3(%rbp),%eax\nlea 0x1(%r14,%rax,1),%r13\nmov $0x0,%r15d\nlea 0xe54(%rip),%r12\njmp 11bf \nadd $0x1,%r15d\nadd $0x1,%rbx\ncmp %r13,%rbx\nje 1203 \nmov %rbx,0x8(%rsp)\nmovsbl 0x1(%rbx),%esi\nmov %r12,%rdi\ncallq 1060 \ntest %rax,%rax\njne 11b6 \nmovsbl (%rbx),%esi\nmov %r12,%rdi\ncallq 1060 \ntest %rax,%rax\njne 11b2 \nmov 0x8(%rsp),%rax\nmovsbl 0x2(%rax),%esi\nmov %r12,%rdi\ncallq 1060 \ntest %rax,%rax\njne 11b2 \njmp 11b6 \nmov $0x0,%r15d\nmovsbl (%r14),%esi\nlea 0xdf6(%rip),%rdi\ncallq 1060 \ntest %rax,%rax\nje 1244 \nmovslq %ebp,%rbp\nmovsbl -0x1(%r14,%rbp,1),%esi\nlea 0xddc(%rip),%rdi\ncallq 1060 \ntest %rax,%rax\nje 125f \nmov %r15d,%eax\nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmovsbl 0x1(%r14),%esi\nlea 0xdb4(%rip),%rdi\ncallq 1060 \ncmp $0x1,%rax\nsbb $0xffffffff,%r15d\njmp 1218 \nmovsbl -0x2(%r14,%rbp,1),%esi\nlea 0xd98(%rip),%rdi\ncallq 1060 \ncmp $0x1,%rax\nsbb $0xffffffff,%r15d\njmp 1232 \n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov r13, rdi\ncall _strlen\nmov r14, rax\ncmp eax, 2\njle short loc_120F\nmov rbx, r13\nlea eax, [rax-3]\nlea r12, [r13+rax+1]\nmov r15d, 0\nlea rbp, s; \"aeiou\"\njmp short loc_11D2\nloc_11C5:\nadd r15d, 1\nloc_11C9:\nadd rbx, 1\ncmp rbx, r12\njz short loc_1215\nloc_11D2:\nmov [rsp+48h+var_40], rbx\nmovsx esi, byte ptr [rbx+1]; c\nmov rdi, rbp; s\ncall _strchr\ntest rax, rax\njnz short loc_11C9\nmovsx esi, byte ptr [rbx]; c\nmov rdi, rbp; s\ncall _strchr\ntest rax, rax\njnz short loc_11C5\nmovsx esi, byte ptr [rbx+2]; c\nlea rdi, s; \"aeiou\"\ncall _strchr\ntest rax, rax\njnz short loc_11C5\njmp short loc_11C9\nloc_120F:\nmov r15d, 0\nloc_1215:\nmovsx esi, byte ptr [r13+0]; c\nlea rdi, s; \"aeiou\"\ncall _strchr\ntest rax, rax\njz short loc_1257\nloc_122B:\nmovsxd r14, r14d\nmovsx esi, byte ptr [r13+r14-1]; c\nlea rdi, s; \"aeiou\"\ncall _strchr\ntest rax, rax\njz short loc_1272\nloc_1245:\nmov eax, r15d\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1257:\nmovsx esi, byte ptr [r13+1]; c\nlea rdi, s; \"aeiou\"\ncall _strchr\ncmp rax, 1\nsbb r15d, 0FFFFFFFFh\njmp short loc_122B\nloc_1272:\nmovsx esi, byte ptr [r13+r14-2]; c\nlea rdi, s; \"aeiou\"\ncall _strchr\ncmp rax, 1\nsbb r15d, 0FFFFFFFFh\njmp short loc_1245", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v1; // eax\n int v2; // r14d\n char *v3; // rbx\n __int64 v4; // r12\n unsigned int v5; // r15d\n\n v1 = strlen(a1);\n v2 = v1;\n if ( v1 <= 2 )\n {\n v5 = 0;\n }\n else\n {\n v3 = (char *)a1;\n v4 = (__int64)&a1[v1 - 3 + 1];\n v5 = 0;\n do\n {\n if ( !strchr(\"aeiou\", v3[1]) && (strchr(\"aeiou\", *v3) || strchr(\"aeiou\", v3[2])) )\n ++v5;\n ++v3;\n }\n while ( v3 != (char *)v4 );\n }\n if ( !strchr(\"aeiou\", *a1) )\n v5 -= (strchr(\"aeiou\", a1[1]) == 0LL) - 1;\n if ( !strchr(\"aeiou\", a1[v2 - 1]) )\n v5 -= (strchr(\"aeiou\", a1[v2 - 2]) == 0LL) - 1;\n return v5;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov r13, rdi\ncall _strlen\nmov r14, rax\ncmp eax, 2\njle short loc_120F\nmov rbx, r13\nlea eax, [rax-3]\nlea r12, [r13+rax+1]\nmov r15d, 0\nlea rbp, s; \"aeiou\"\njmp short loc_11D2\nloc_11C5:\nadd r15d, 1\nloc_11C9:\nadd rbx, 1\ncmp rbx, r12\njz short loc_1215\nloc_11D2:\nmov [rsp+48h+var_40], rbx\nmovsx esi, byte ptr [rbx+1]; c\nmov rdi, rbp; s\ncall _strchr\ntest rax, rax\njnz short loc_11C9\nmovsx esi, byte ptr [rbx]; c\nmov rdi, rbp; s\ncall _strchr\ntest rax, rax\njnz short loc_11C5\nmovsx esi, byte ptr [rbx+2]; c\nlea rdi, s; \"aeiou\"\ncall _strchr\ntest rax, rax\njnz short loc_11C5\njmp short loc_11C9\nloc_120F:\nmov r15d, 0\nloc_1215:\nmovsx esi, byte ptr [r13+0]; c\nlea rdi, s; \"aeiou\"\ncall _strchr\ntest rax, rax\njz short loc_1257\nloc_122B:\nmovsxd r14, r14d\nmovsx esi, byte ptr [r13+r14-1]; c\nlea rdi, s; \"aeiou\"\ncall _strchr\ntest rax, rax\njz short loc_1272\nloc_1245:\nmov eax, r15d\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1257:\nmovsx esi, byte ptr [r13+1]; c\nlea rdi, s; \"aeiou\"\ncall _strchr\ncmp rax, 1\nsbb r15d, 0FFFFFFFFh\njmp short loc_122B\nloc_1272:\nmovsx esi, byte ptr [r13+r14-2]; c\nlea rdi, s; \"aeiou\"\ncall _strchr\ncmp rax, 1\nsbb r15d, 0FFFFFFFFh\njmp short loc_1245", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(const char *a1)\n{\n int v1; // eax\n int v2; // r14d\n char *v3; // rbx\n __int64 v4; // r12\n unsigned int v5; // r15d\n\n v1 = strlen(a1);\n v2 = v1;\n if ( v1 <= 2 )\n {\n v5 = 0;\n }\n else\n {\n v3 = (char *)a1;\n v4 = (__int64)&a1[v1 - 3 + 1];\n v5 = 0;\n do\n {\n if ( !strchr(\"aeiou\", v3[1]) && (strchr(\"aeiou\", *v3) || strchr(\"aeiou\", v3[2])) )\n ++v5;\n ++v3;\n }\n while ( v3 != (char *)v4 );\n }\n if ( !strchr(\"aeiou\", *a1) )\n v5 -= (strchr(\"aeiou\", a1[1]) == 0LL) - 1;\n if ( !strchr(\"aeiou\", a1[v2 - 1]) )\n v5 -= (strchr(\"aeiou\", a1[v2 - 2]) == 0LL) - 1;\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(const char *a1) {\n int v1;\n int v2;\n char *v3;\n long long v4;\n unsigned int v5;\n v1 = strlen(a1);\n v2 = v1;\n if (v1 <= 2) {\n v5 = 0;\n } else {\n v3 = (char *)a1;\n v4 = (long long)&a1[v1 - 3 + 1];\n v5 = 0;\n do {\n if (!strchr(\"aeiou\", v3[1]) &&\n (strchr(\"aeiou\", *v3) || strchr(\"aeiou\", v3[2])))\n ++v5;\n ++v3;\n } while (v3 != (char *)v4);\n }\n if (!strchr(\"aeiou\", *a1)) v5 -= (strchr(\"aeiou\", a1[1]) == 0LL) - 1;\n if (!strchr(\"aeiou\", a1[v2 - 1]))\n v5 -= (strchr(\"aeiou\", a1[v2 - 2]) == 0LL) - 1;\n return v5;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v1;\n int v2;\n char *v3;\n long long v4;\n unsigned int v5;\n v1 = strlen(a1);\n v2 = v1;\n if (v1 <= 2) {\n v5 = 0;\n } else {\n v3 = (char *)a1;\n v4 = (long long)&a1[v1 - 3 + 1];\n v5 = 0;\n do {\n if (!strchr(\"aeiou\", v3[1]) &&\n (strchr(\"aeiou\", *v3) || strchr(\"aeiou\", v3[2])))\n ++v5;\n ++v3;\n } while (v3 != (char *)v4);\n }\n if (!strchr(\"aeiou\", *a1)) v5 -= (strchr(\"aeiou\", a1[1]) == 0LL) - 1;\n if (!strchr(\"aeiou\", a1[v2 - 1]))\n v5 -= (strchr(\"aeiou\", a1[v2 - 2]) == 0LL) - 1;\n return v5;\n}" + }, + { + "index": 776, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *test_str) {\n int res = 0;\n const char *vow_list = \"aeiou\";\n int len = strlen(test_str);\n for (int idx = 1; idx < len - 1; idx++) {\n if (strchr(vow_list, test_str[idx]) == NULL &&\n (strchr(vow_list, test_str[idx - 1]) != NULL ||\n strchr(vow_list, test_str[idx + 1]) != NULL)) {\n res += 1;\n }\n }\n if (strchr(vow_list, test_str[0]) == NULL &&\n strchr(vow_list, test_str[1]) != NULL) {\n res += 1;\n }\n if (strchr(vow_list, test_str[len - 1]) == NULL &&\n strchr(vow_list, test_str[len - 2]) != NULL) {\n res += 1;\n }\n return res;\n}", + "test": "int main() {\n\n assert(func0(\"bestinstareels\") == 7);\n\n assert(func0(\"partofthejourneyistheend\") == 12);\n\n assert(func0(\"amazonprime\") == 5);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\nmov %rdi,%r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\ncallq 1070 \nmov %rax,%r14\ncmp $0x2,%eax\njle 1350 \nlea -0x3(%rax),%eax\nmov %r13,%rbx\nlea 0xda1(%rip),%rbp\nxor %r15d,%r15d\nlea 0x1(%r13,%rax,1),%r12\njmp 1279 \nnopl (%rax)\nadd $0x1,%rbx\ncmp %r12,%rbx\nje 12a7 \nmovsbl 0x1(%rbx),%esi\nmov %rbp,%rdi\ncallq 1080 \ntest %rax,%rax\njne 1270 \nmovsbl (%rbx),%esi\nmov %rbp,%rdi\ncallq 1080 \ntest %rax,%rax\nje 12f0 \nadd $0x1,%rbx\nadd $0x1,%r15d\ncmp %r12,%rbx\njne 1279 \nmovsbl 0x0(%r13),%esi\nlea 0xd51(%rip),%rdi\ncallq 1080 \ntest %rax,%rax\nje 1310 \nmovslq %r14d,%r14\nlea 0xd3d(%rip),%rdi\nmovsbl -0x1(%r13,%r14,1),%esi\ncallq 1080 \ntest %rax,%rax\nje 1330 \nadd $0x8,%rsp\nmov %r15d,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\nmovsbl 0x2(%rbx),%esi\nmov %rbp,%rdi\ncallq 1080 \ntest %rax,%rax\njne 129a \njmpq 1270 \nnopw %cs:0x0(%rax,%rax,1)\nmovsbl 0x1(%r13),%esi\nlea 0xce8(%rip),%rdi\ncallq 1080 \ncmp $0x1,%rax\nsbb $0xffffffff,%r15d\njmp 12bd \nnopl 0x0(%rax,%rax,1)\nmovsbl -0x2(%r13,%r14,1),%esi\nlea 0xcc7(%rip),%rdi\ncallq 1080 \ncmp $0x1,%rax\nsbb $0xffffffff,%r15d\njmp 12d7 \nnopl 0x0(%rax)\nxor %r15d,%r15d\njmpq 12a7 \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\nmov r13, rdi\npush r12\npush rbp\npush rbx\nsub rsp, 8\ncall _strlen\nmov r14, rax\ncmp eax, 2\njle loc_1340\nlea eax, [rax-3]\nmov rbx, r13\nlea rbp, s; \"aeiou\"\nxor r15d, r15d\nlea r12, [r13+rax+1]\njmp short loc_1279\nloc_1270:\nadd rbx, 1\ncmp rbx, r12\njz short loc_12A7\nloc_1279:\nmovsx esi, byte ptr [rbx+1]; c\nmov rdi, rbp; s\ncall _strchr\ntest rax, rax\njnz short loc_1270\nmovsx esi, byte ptr [rbx]; c\nmov rdi, rbp; s\ncall _strchr\ntest rax, rax\njz short loc_12E8\nloc_129A:\nadd rbx, 1\nadd r15d, 1\ncmp rbx, r12\njnz short loc_1279\nloc_12A7:\nmovsx esi, byte ptr [r13+0]; c\nmov rdi, rbp; s\ncall _strchr\ntest rax, rax\njz short loc_1300\nloc_12B9:\nmovsxd r14, r14d\nmov rdi, rbp; s\nmovsx esi, byte ptr [r13+r14-1]; c\ncall _strchr\ntest rax, rax\njz short loc_1320\nloc_12CF:\nadd rsp, 8\nmov eax, r15d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_12E8:\nmovsx esi, byte ptr [rbx+2]; c\nmov rdi, rbp; s\ncall _strchr\ntest rax, rax\njnz short loc_129A\njmp loc_1270\nloc_1300:\nmovsx esi, byte ptr [r13+1]; c\nmov rdi, rbp; s\ncall _strchr\ncmp rax, 1\nsbb r15d, 0FFFFFFFFh\njmp short loc_12B9\nloc_1320:\nmovsx esi, byte ptr [r13+r14-2]; c\nmov rdi, rbp; s\ncall _strchr\ncmp rax, 1\nsbb r15d, 0FFFFFFFFh\njmp short loc_12CF\nloc_1340:\nxor r15d, r15d\nlea rbp, s; \"aeiou\"\njmp loc_12A7", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v1; // eax\n int v2; // r14d\n char *v3; // rbx\n unsigned int v4; // r15d\n __int64 v5; // r12\n\n v1 = strlen(a1);\n v2 = v1;\n if ( v1 <= 2 )\n {\n v4 = 0;\n }\n else\n {\n v3 = (char *)a1;\n v4 = 0;\n v5 = (__int64)&a1[v1 - 3 + 1];\n do\n {\n while ( strchr(\"aeiou\", v3[1]) || !strchr(\"aeiou\", *v3) && !strchr(\"aeiou\", v3[2]) )\n {\n if ( ++v3 == (char *)v5 )\n goto LABEL_7;\n }\n ++v3;\n ++v4;\n }\n while ( v3 != (char *)v5 );\n }\nLABEL_7:\n if ( !strchr(\"aeiou\", *a1) )\n v4 -= (strchr(\"aeiou\", a1[1]) == 0LL) - 1;\n if ( !strchr(\"aeiou\", a1[v2 - 1]) )\n v4 -= (strchr(\"aeiou\", a1[v2 - 2]) == 0LL) - 1;\n return v4;\n}", + "ida_strip_asm": "sub_1230:\nendbr64\npush r15\npush r14\npush r13\nmov r13, rdi\npush r12\npush rbp\npush rbx\nsub rsp, 8\ncall _strlen\nmov r14, rax\ncmp eax, 2\njle loc_1340\nlea eax, [rax-3]\nmov rbx, r13\nlea rbp, s; \"aeiou\"\nxor r15d, r15d\nlea r12, [r13+rax+1]\njmp short loc_1279\nloc_1270:\nadd rbx, 1\ncmp rbx, r12\njz short loc_12A7\nloc_1279:\nmovsx esi, byte ptr [rbx+1]; c\nmov rdi, rbp; s\ncall _strchr\ntest rax, rax\njnz short loc_1270\nmovsx esi, byte ptr [rbx]; c\nmov rdi, rbp; s\ncall _strchr\ntest rax, rax\njz short loc_12E8\nloc_129A:\nadd rbx, 1\nadd r15d, 1\ncmp rbx, r12\njnz short loc_1279\nloc_12A7:\nmovsx esi, byte ptr [r13+0]; c\nmov rdi, rbp; s\ncall _strchr\ntest rax, rax\njz short loc_1300\nloc_12B9:\nmovsxd r14, r14d\nmov rdi, rbp; s\nmovsx esi, byte ptr [r13+r14-1]; c\ncall _strchr\ntest rax, rax\njz short loc_1320\nloc_12CF:\nadd rsp, 8\nmov eax, r15d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_12E8:\nmovsx esi, byte ptr [rbx+2]; c\nmov rdi, rbp; s\ncall _strchr\ntest rax, rax\njnz short loc_129A\njmp loc_1270\nloc_1300:\nmovsx esi, byte ptr [r13+1]; c\nmov rdi, rbp; s\ncall _strchr\ncmp rax, 1\nsbb r15d, 0FFFFFFFFh\njmp short loc_12B9\nloc_1320:\nmovsx esi, byte ptr [r13+r14-2]; c\nmov rdi, rbp; s\ncall _strchr\ncmp rax, 1\nsbb r15d, 0FFFFFFFFh\njmp short loc_12CF\nloc_1340:\nxor r15d, r15d\nlea rbp, s; \"aeiou\"\njmp loc_12A7", + "ida_strip_pseudo": "__int64 __fastcall sub_1230(const char *a1)\n{\n int v1; // eax\n int v2; // r14d\n char *v3; // rbx\n unsigned int v4; // r15d\n __int64 v5; // r12\n\n v1 = strlen(a1);\n v2 = v1;\n if ( v1 <= 2 )\n {\n v4 = 0;\n }\n else\n {\n v3 = (char *)a1;\n v4 = 0;\n v5 = (__int64)&a1[v1 - 3 + 1];\n do\n {\n while ( strchr(\"aeiou\", v3[1]) || !strchr(\"aeiou\", *v3) && !strchr(\"aeiou\", v3[2]) )\n {\n if ( ++v3 == (char *)v5 )\n goto LABEL_7;\n }\n ++v3;\n ++v4;\n }\n while ( v3 != (char *)v5 );\n }\nLABEL_7:\n if ( !strchr(\"aeiou\", *a1) )\n v4 -= (strchr(\"aeiou\", a1[1]) == 0LL) - 1;\n if ( !strchr(\"aeiou\", a1[v2 - 1]) )\n v4 -= (strchr(\"aeiou\", a1[v2 - 2]) == 0LL) - 1;\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1230(const char *a1) {\n int v1;\n int v2;\n char *v3;\n unsigned int v4;\n long long v5;\n v1 = strlen(a1);\n v2 = v1;\n if (v1 <= 2) {\n v4 = 0;\n } else {\n v3 = (char *)a1;\n v4 = 0;\n v5 = (long long)&a1[v1 - 3 + 1];\n do {\n while (strchr(\"aeiou\", v3[1]) ||\n !strchr(\"aeiou\", *v3) && !strchr(\"aeiou\", v3[2])) {\n if (++v3 == (char *)v5) goto LABEL_7;\n }\n ++v3;\n ++v4;\n } while (v3 != (char *)v5);\n }\nLABEL_7:\n if (!strchr(\"aeiou\", *a1)) v4 -= (strchr(\"aeiou\", a1[1]) == 0LL) - 1;\n if (!strchr(\"aeiou\", a1[v2 - 1]))\n v4 -= (strchr(\"aeiou\", a1[v2 - 2]) == 0LL) - 1;\n return v4;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v1;\n int v2;\n char *v3;\n unsigned int v4;\n long long v5;\n v1 = strlen(a1);\n v2 = v1;\n if (v1 <= 2) {\n v4 = 0;\n } else {\n v3 = (char *)a1;\n v4 = 0;\n v5 = (long long)&a1[v1 - 3 + 1];\n do {\n while (strchr(\"aeiou\", v3[1]) ||\n !strchr(\"aeiou\", *v3) && !strchr(\"aeiou\", v3[2])) {\n if (++v3 == (char *)v5) goto LABEL_7;\n }\n ++v3;\n ++v4;\n } while (v3 != (char *)v5);\n }\nLABEL_7:\n if (!strchr(\"aeiou\", *a1)) v4 -= (strchr(\"aeiou\", a1[1]) == 0LL) - 1;\n if (!strchr(\"aeiou\", a1[v2 - 1]))\n v4 -= (strchr(\"aeiou\", a1[v2 - 2]) == 0LL) - 1;\n return v4;\n}" + }, + { + "index": 776, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *test_str) {\n int res = 0;\n const char *vow_list = \"aeiou\";\n int len = strlen(test_str);\n for (int idx = 1; idx < len - 1; idx++) {\n if (strchr(vow_list, test_str[idx]) == NULL &&\n (strchr(vow_list, test_str[idx - 1]) != NULL ||\n strchr(vow_list, test_str[idx + 1]) != NULL)) {\n res += 1;\n }\n }\n if (strchr(vow_list, test_str[0]) == NULL &&\n strchr(vow_list, test_str[1]) != NULL) {\n res += 1;\n }\n if (strchr(vow_list, test_str[len - 1]) == NULL &&\n strchr(vow_list, test_str[len - 2]) != NULL) {\n res += 1;\n }\n return res;\n}", + "test": "int main() {\n\n assert(func0(\"bestinstareels\") == 7);\n\n assert(func0(\"partofthejourneyistheend\") == 12);\n\n assert(func0(\"amazonprime\") == 5);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\nmov %rdi,%r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\ncallq 1070 \nmov %rax,%r14\ncmp $0x2,%eax\njle 1350 \nlea -0x3(%rax),%eax\nmov %r13,%rbx\nlea 0xda1(%rip),%rbp\nxor %r15d,%r15d\nlea 0x1(%r13,%rax,1),%r12\njmp 1279 \nnopl (%rax)\nadd $0x1,%rbx\ncmp %rbx,%r12\nje 12a7 \nmovsbl 0x1(%rbx),%esi\nmov %rbp,%rdi\ncallq 1080 \ntest %rax,%rax\njne 1270 \nmovsbl (%rbx),%esi\nmov %rbp,%rdi\ncallq 1080 \ntest %rax,%rax\nje 12f0 \nadd $0x1,%rbx\nadd $0x1,%r15d\ncmp %rbx,%r12\njne 1279 \nmovsbl 0x0(%r13),%esi\nlea 0xd51(%rip),%rdi\ncallq 1080 \ntest %rax,%rax\nje 1310 \nmovslq %r14d,%r14\nlea 0xd3d(%rip),%rdi\nmovsbl -0x1(%r13,%r14,1),%esi\ncallq 1080 \ntest %rax,%rax\nje 1330 \nadd $0x8,%rsp\nmov %r15d,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\nmovsbl 0x2(%rbx),%esi\nmov %rbp,%rdi\ncallq 1080 \ntest %rax,%rax\njne 129a \njmpq 1270 \nnopw %cs:0x0(%rax,%rax,1)\nmovsbl 0x1(%r13),%esi\nlea 0xce8(%rip),%rdi\ncallq 1080 \ncmp $0x1,%rax\nsbb $0xffffffff,%r15d\njmp 12bd \nnopl 0x0(%rax,%rax,1)\nmovsbl -0x2(%r13,%r14,1),%esi\nlea 0xcc7(%rip),%rdi\ncallq 1080 \ncmp $0x1,%rax\nsbb $0xffffffff,%r15d\njmp 12d7 \nnopl 0x0(%rax)\nxor %r15d,%r15d\njmpq 12a7 \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\nmov r13, rdi\npush r12\npush rbp\npush rbx\nsub rsp, 8\ncall _strlen\nmov r14, rax\ncmp eax, 2\njle loc_1340\nlea eax, [rax-3]\nmov rbx, r13\nlea rbp, s; \"aeiou\"\nxor r15d, r15d\nlea r12, [r13+rax+1]\njmp short loc_1279\nloc_1270:\nadd rbx, 1\ncmp r12, rbx\njz short loc_12A7\nloc_1279:\nmovsx esi, byte ptr [rbx+1]; c\nmov rdi, rbp; s\ncall _strchr\ntest rax, rax\njnz short loc_1270\nmovsx esi, byte ptr [rbx]; c\nmov rdi, rbp; s\ncall _strchr\ntest rax, rax\njz short loc_12E8\nloc_129A:\nadd rbx, 1\nadd r15d, 1\ncmp r12, rbx\njnz short loc_1279\nloc_12A7:\nmovsx esi, byte ptr [r13+0]; c\nmov rdi, rbp; s\ncall _strchr\ntest rax, rax\njz short loc_1300\nloc_12B9:\nmovsxd r14, r14d\nmov rdi, rbp; s\nmovsx esi, byte ptr [r13+r14-1]; c\ncall _strchr\ntest rax, rax\njz short loc_1320\nloc_12CF:\nadd rsp, 8\nmov eax, r15d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_12E8:\nmovsx esi, byte ptr [rbx+2]; c\nmov rdi, rbp; s\ncall _strchr\ntest rax, rax\njnz short loc_129A\njmp loc_1270\nloc_1300:\nmovsx esi, byte ptr [r13+1]; c\nmov rdi, rbp; s\ncall _strchr\ncmp rax, 1\nsbb r15d, 0FFFFFFFFh\njmp short loc_12B9\nloc_1320:\nmovsx esi, byte ptr [r13+r14-2]; c\nmov rdi, rbp; s\ncall _strchr\ncmp rax, 1\nsbb r15d, 0FFFFFFFFh\njmp short loc_12CF\nloc_1340:\nxor r15d, r15d\nlea rbp, s; \"aeiou\"\njmp loc_12A7", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v1; // eax\n int v2; // r14d\n char *v3; // rbx\n unsigned int v4; // r15d\n __int64 v5; // r12\n\n v1 = strlen(a1);\n v2 = v1;\n if ( v1 <= 2 )\n {\n v4 = 0;\n }\n else\n {\n v3 = (char *)a1;\n v4 = 0;\n v5 = (__int64)&a1[v1 - 3 + 1];\n do\n {\n while ( strchr(\"aeiou\", v3[1]) || !strchr(\"aeiou\", *v3) && !strchr(\"aeiou\", v3[2]) )\n {\n if ( (char *)v5 == ++v3 )\n goto LABEL_7;\n }\n ++v3;\n ++v4;\n }\n while ( (char *)v5 != v3 );\n }\nLABEL_7:\n if ( !strchr(\"aeiou\", *a1) )\n v4 -= (strchr(\"aeiou\", a1[1]) == 0LL) - 1;\n if ( !strchr(\"aeiou\", a1[v2 - 1]) )\n v4 -= (strchr(\"aeiou\", a1[v2 - 2]) == 0LL) - 1;\n return v4;\n}", + "ida_strip_asm": "sub_1230:\nendbr64\npush r15\npush r14\npush r13\nmov r13, rdi\npush r12\npush rbp\npush rbx\nsub rsp, 8\ncall _strlen\nmov r14, rax\ncmp eax, 2\njle loc_1340\nlea eax, [rax-3]\nmov rbx, r13\nlea rbp, s; \"aeiou\"\nxor r15d, r15d\nlea r12, [r13+rax+1]\njmp short loc_1279\nloc_1270:\nadd rbx, 1\ncmp r12, rbx\njz short loc_12A7\nloc_1279:\nmovsx esi, byte ptr [rbx+1]; c\nmov rdi, rbp; s\ncall _strchr\ntest rax, rax\njnz short loc_1270\nmovsx esi, byte ptr [rbx]; c\nmov rdi, rbp; s\ncall _strchr\ntest rax, rax\njz short loc_12E8\nloc_129A:\nadd rbx, 1\nadd r15d, 1\ncmp r12, rbx\njnz short loc_1279\nloc_12A7:\nmovsx esi, byte ptr [r13+0]; c\nmov rdi, rbp; s\ncall _strchr\ntest rax, rax\njz short loc_1300\nloc_12B9:\nmovsxd r14, r14d\nmov rdi, rbp; s\nmovsx esi, byte ptr [r13+r14-1]; c\ncall _strchr\ntest rax, rax\njz short loc_1320\nloc_12CF:\nadd rsp, 8\nmov eax, r15d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_12E8:\nmovsx esi, byte ptr [rbx+2]; c\nmov rdi, rbp; s\ncall _strchr\ntest rax, rax\njnz short loc_129A\njmp loc_1270\nloc_1300:\nmovsx esi, byte ptr [r13+1]; c\nmov rdi, rbp; s\ncall _strchr\ncmp rax, 1\nsbb r15d, 0FFFFFFFFh\njmp short loc_12B9\nloc_1320:\nmovsx esi, byte ptr [r13+r14-2]; c\nmov rdi, rbp; s\ncall _strchr\ncmp rax, 1\nsbb r15d, 0FFFFFFFFh\njmp short loc_12CF\nloc_1340:\nxor r15d, r15d\nlea rbp, s; \"aeiou\"\njmp loc_12A7", + "ida_strip_pseudo": "__int64 __fastcall sub_1230(const char *a1)\n{\n int v1; // eax\n int v2; // r14d\n char *v3; // rbx\n unsigned int v4; // r15d\n __int64 v5; // r12\n\n v1 = strlen(a1);\n v2 = v1;\n if ( v1 <= 2 )\n {\n v4 = 0;\n }\n else\n {\n v3 = (char *)a1;\n v4 = 0;\n v5 = (__int64)&a1[v1 - 3 + 1];\n do\n {\n while ( strchr(\"aeiou\", v3[1]) || !strchr(\"aeiou\", *v3) && !strchr(\"aeiou\", v3[2]) )\n {\n if ( (char *)v5 == ++v3 )\n goto LABEL_7;\n }\n ++v3;\n ++v4;\n }\n while ( (char *)v5 != v3 );\n }\nLABEL_7:\n if ( !strchr(\"aeiou\", *a1) )\n v4 -= (strchr(\"aeiou\", a1[1]) == 0LL) - 1;\n if ( !strchr(\"aeiou\", a1[v2 - 1]) )\n v4 -= (strchr(\"aeiou\", a1[v2 - 2]) == 0LL) - 1;\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1230(const char *a1) {\n int v1;\n int v2;\n char *v3;\n unsigned int v4;\n long long v5;\n v1 = strlen(a1);\n v2 = v1;\n if (v1 <= 2) {\n v4 = 0;\n } else {\n v3 = (char *)a1;\n v4 = 0;\n v5 = (long long)&a1[v1 - 3 + 1];\n do {\n while (strchr(\"aeiou\", v3[1]) ||\n !strchr(\"aeiou\", *v3) && !strchr(\"aeiou\", v3[2])) {\n if ((char *)v5 == ++v3) goto LABEL_7;\n }\n ++v3;\n ++v4;\n } while ((char *)v5 != v3);\n }\nLABEL_7:\n if (!strchr(\"aeiou\", *a1)) v4 -= (strchr(\"aeiou\", a1[1]) == 0LL) - 1;\n if (!strchr(\"aeiou\", a1[v2 - 1]))\n v4 -= (strchr(\"aeiou\", a1[v2 - 2]) == 0LL) - 1;\n return v4;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v1;\n int v2;\n char *v3;\n unsigned int v4;\n long long v5;\n v1 = strlen(a1);\n v2 = v1;\n if (v1 <= 2) {\n v4 = 0;\n } else {\n v3 = (char *)a1;\n v4 = 0;\n v5 = (long long)&a1[v1 - 3 + 1];\n do {\n while (strchr(\"aeiou\", v3[1]) ||\n !strchr(\"aeiou\", *v3) && !strchr(\"aeiou\", v3[2])) {\n if ((char *)v5 == ++v3) goto LABEL_7;\n }\n ++v3;\n ++v4;\n } while ((char *)v5 != v3);\n }\nLABEL_7:\n if (!strchr(\"aeiou\", *a1)) v4 -= (strchr(\"aeiou\", a1[1]) == 0LL) - 1;\n if (!strchr(\"aeiou\", a1[v2 - 1]))\n v4 -= (strchr(\"aeiou\", a1[v2 - 2]) == 0LL) - 1;\n return v4;\n}" + }, + { + "index": 777, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint compare(const void* a, const void* b) {\n\n return (*(int*)a - *(int*)b);\n\n}\n\n\n\n", + "func": "int func0(int* arr, int n) {\n qsort(arr, n, sizeof(int), compare);\n int sum = arr[0];\n for (int i = 0; i < n - 1; i++) {\n if (arr[i] != arr[i + 1]) {\n sum += arr[i + 1];\n }\n }\n return sum;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 1, 1, 4, 5, 6};\n\n int arr2[] = {1, 10, 9, 4, 2, 10, 10, 45, 4};\n\n int arr3[] = {12, 10, 9, 45, 2, 10, 10, 45, 10};\n\n assert(func0(arr1, 8) == 21);\n\n assert(func0(arr2, 9) == 71);\n\n assert(func0(arr3, 9) == 78);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov -0x1c(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x18(%rbp),%rax\nlea -0x46(%rip),%rcx\nmov $0x4,%edx\nmov %rax,%rdi\ncallq 1070 \nmov -0x18(%rbp),%rax\nmov (%rax),%eax\nmov %eax,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 1243 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\nje 123f \nmov -0x4(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nadd %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x1c(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x4(%rbp)\njl 11ee \nmov -0x8(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+base], rdi\nmov [rbp+var_1C], esi\nmov eax, [rbp+var_1C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compare\nmov rcx, rdx; compar\nmov edx, 4; size\nmov rdi, rax; base\ncall _qsort\nmov rax, [rbp+base]\nmov eax, [rax]\nmov [rbp+var_8], eax\nmov [rbp+var_4], 0\njmp short loc_1246\nloc_11F1:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_1242\nmov eax, [rbp+var_4]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nloc_1242:\nadd [rbp+var_4], 1\nloc_1246:\nmov eax, [rbp+var_1C]\nsub eax, 1\ncmp [rbp+var_4], eax\njl short loc_11F1\nmov eax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n unsigned int v3; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n qsort(a1, a2, 4uLL, compare);\n v3 = *a1;\n for ( i = 0; i < a2 - 1; ++i )\n {\n if ( a1[i] != a1[i + 1] )\n v3 += a1[i + 1];\n }\n return v3;\n}", + "ida_strip_asm": "sub_11AB:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+base], rdi\nmov [rbp+var_1C], esi\nmov eax, [rbp+var_1C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 4; size\nmov rdi, rax; base\ncall _qsort\nmov rax, [rbp+base]\nmov eax, [rax]\nmov [rbp+var_8], eax\nmov [rbp+var_4], 0\njmp short loc_1246\nloc_11F1:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_1242\nmov eax, [rbp+var_4]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nloc_1242:\nadd [rbp+var_4], 1\nloc_1246:\nmov eax, [rbp+var_1C]\nsub eax, 1\ncmp [rbp+var_4], eax\njl short loc_11F1\nmov eax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11AB(_DWORD *a1, int a2)\n{\n unsigned int v3; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n qsort(a1, a2, 4uLL, compar);\n v3 = *a1;\n for ( i = 0; i < a2 - 1; ++i )\n {\n if ( a1[i] != a1[i + 1] )\n v3 += a1[i + 1];\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11AB(uint32_t *a1, int a2) {\n unsigned int v3;\n int i;\n qsort(a1, a2, 4uLL, compar);\n v3 = *a1;\n for (i = 0; i < a2 - 1; ++i) {\n if (a1[i] != a1[i + 1]) v3 += a1[i + 1];\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n unsigned int v3;\n int i;\n qsort(a1, a2, 4uLL, compare);\n v3 = *a1;\n for (i = 0; i < a2 - 1; ++i) {\n if (a1[i] != a1[i + 1]) v3 += a1[i + 1];\n }\n return v3;\n}" + }, + { + "index": 777, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint compare(const void* a, const void* b) {\n\n return (*(int*)a - *(int*)b);\n\n}\n\n\n\n", + "func": "int func0(int* arr, int n) {\n qsort(arr, n, sizeof(int), compare);\n int sum = arr[0];\n for (int i = 0; i < n - 1; i++) {\n if (arr[i] != arr[i + 1]) {\n sum += arr[i + 1];\n }\n }\n return sum;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 1, 1, 4, 5, 6};\n\n int arr2[] = {1, 10, 9, 4, 2, 10, 10, 45, 4};\n\n int arr3[] = {12, 10, 9, 45, 2, 10, 10, 45, 10};\n\n assert(func0(arr1, 8) == 21);\n\n assert(func0(arr2, 9) == 71);\n\n assert(func0(arr3, 9) == 78);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbx\nmov %esi,%ebp\nmovslq %esi,%rsi\nlea -0x22(%rip),%rcx\nmov $0x4,%edx\ncallq 1070 \nmov (%rbx),%edx\ncmp $0x1,%ebp\njle 11db \nmov %rbx,%rax\nlea -0x2(%rbp),%ecx\nlea 0x4(%rbx,%rcx,4),%rdi\nmov 0x4(%rax),%ecx\nlea (%rdx,%rcx,1),%esi\ncmp %ecx,(%rax)\ncmovne %esi,%edx\nadd $0x4,%rax\ncmp %rdi,%rax\njne 11c7 \nmov %edx,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov ebp, esi\nmovsxd rsi, esi; nmemb\nlea rcx, compare; compar\nmov edx, 4; size\ncall _qsort\nmov ecx, [rbx]\ncmp ebp, 1\njle short loc_11DD\nmov rax, rbx\nlea edx, [rbp-2]\nlea rsi, [rbx+rdx*4+4]\njmp short loc_11D2\nloc_11C9:\nadd rax, 4\ncmp rax, rsi\njz short loc_11DD\nloc_11D2:\nmov edx, [rax+4]\ncmp [rax], edx\njz short loc_11C9\nadd ecx, edx\njmp short loc_11C9\nloc_11DD:\nmov eax, ecx\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n unsigned int v2; // ecx\n _DWORD *v3; // rax\n int v4; // edx\n\n qsort(a1, a2, 4uLL, compare);\n v2 = *a1;\n if ( a2 > 1 )\n {\n v3 = a1;\n do\n {\n v4 = v3[1];\n if ( *v3 != v4 )\n v2 += v4;\n ++v3;\n }\n while ( v3 != &a1[a2 - 2 + 1] );\n }\n return v2;\n}", + "ida_strip_asm": "sub_1192:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov ebp, esi\nmovsxd rsi, esi; nmemb\nlea rcx, compar; compar\nmov edx, 4; size\ncall _qsort\nmov ecx, [rbx]\ncmp ebp, 1\njle short loc_11DD\nmov rax, rbx\nlea edx, [rbp-2]\nlea rsi, [rbx+rdx*4+4]\njmp short loc_11D2\nloc_11C9:\nadd rax, 4\ncmp rax, rsi\njz short loc_11DD\nloc_11D2:\nmov edx, [rax+4]\ncmp [rax], edx\njz short loc_11C9\nadd ecx, edx\njmp short loc_11C9\nloc_11DD:\nmov eax, ecx\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1192(_DWORD *a1, int a2)\n{\n unsigned int v2; // ecx\n _DWORD *v3; // rax\n int v4; // edx\n\n qsort(a1, a2, 4uLL, compar);\n v2 = *a1;\n if ( a2 > 1 )\n {\n v3 = a1;\n do\n {\n v4 = v3[1];\n if ( *v3 != v4 )\n v2 += v4;\n ++v3;\n }\n while ( v3 != &a1[a2 - 2 + 1] );\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1192(uint32_t *a1, int a2) {\n unsigned int v2;\n uint32_t *v3;\n int v4;\n qsort(a1, a2, 4uLL, compar);\n v2 = *a1;\n if (a2 > 1) {\n v3 = a1;\n do {\n v4 = v3[1];\n if (*v3 != v4) v2 += v4;\n ++v3;\n } while (v3 != &a1[a2 - 2 + 1]);\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n unsigned int v2;\n uint32_t *v3;\n int v4;\n qsort(a1, a2, 4uLL, compare);\n v2 = *a1;\n if (a2 > 1) {\n v3 = a1;\n do {\n v4 = v3[1];\n if (*v3 != v4) v2 += v4;\n ++v3;\n } while (v3 != &a1[a2 - 2 + 1]);\n }\n return v2;\n}" + }, + { + "index": 777, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint compare(const void* a, const void* b) {\n\n return (*(int*)a - *(int*)b);\n\n}\n\n\n\n", + "func": "int func0(int* arr, int n) {\n qsort(arr, n, sizeof(int), compare);\n int sum = arr[0];\n for (int i = 0; i < n - 1; i++) {\n if (arr[i] != arr[i + 1]) {\n sum += arr[i + 1];\n }\n }\n return sum;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 1, 1, 4, 5, 6};\n\n int arr2[] = {1, 10, 9, 4, 2, 10, 10, 45, 4};\n\n int arr3[] = {12, 10, 9, 45, 2, 10, 10, 45, 10};\n\n assert(func0(arr1, 8) == 21);\n\n assert(func0(arr2, 9) == 71);\n\n assert(func0(arr3, 9) == 78);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmovslq %esi,%rsi\nlea -0x1f(%rip),%rcx\nmov $0x4,%edx\npush %rbx\nmov %rsi,%rbp\nmov %rdi,%rbx\nsub $0x8,%rsp\ncallq 1070 \nmov (%rbx),%r8d\ncmp $0x1,%ebp\njle 1377 \nlea 0x4(%rbx),%rdi\nlea -0x2(%rbp),%eax\nmov %r8d,%ecx\nlea (%rdi,%rax,4),%rsi\njmp 1366 \nnopl 0x0(%rax)\nadd $0x4,%rdi\nmov %eax,%ecx\nmov (%rdi),%eax\nlea (%r8,%rax,1),%edx\ncmp %ecx,%eax\ncmovne %edx,%r8d\ncmp %rsi,%rdi\njne 1360 \nadd $0x8,%rsp\nmov %r8d,%eax\npop %rbx\npop %rbp\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmovsxd rsi, esi; nmemb\nlea rcx, compare; compar\nmov edx, 4; size\npush rbx\nmov rbp, rsi\nmov rbx, rdi\nsub rsp, 8\ncall _qsort\nmov eax, [rbx]\ncmp ebp, 1\njle short loc_1330\nlea ecx, [rbp-2]\nlea rdx, [rbx+4]\nlea r8, [rbx+rcx*4+8]\nmov ecx, eax\nnop dword ptr [rax+00000000h]\nloc_1310:\nmov edi, eax\nmov eax, [rdx]\ncmp edi, eax\nlea esi, [rcx+rax]\ncmovnz ecx, esi\nadd rdx, 4\ncmp rdx, r8\njnz short loc_1310\nadd rsp, 8\nmov eax, ecx\npop rbx\npop rbp\nretn\nloc_1330:\nadd rsp, 8\nmov ecx, eax\nmov eax, ecx\npop rbx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n __int64 result; // rax\n _DWORD *v3; // rdx\n __int64 v4; // r8\n unsigned int v5; // ecx\n int v6; // edi\n\n qsort(a1, a2, 4uLL, compare);\n LODWORD(result) = *a1;\n if ( a2 <= 1 )\n return (unsigned int)result;\n v3 = a1 + 1;\n v4 = (__int64)&a1[a2 - 2 + 2];\n v5 = *a1;\n do\n {\n v6 = result;\n LODWORD(result) = *v3;\n if ( v6 != *v3 )\n v5 += *v3;\n ++v3;\n }\n while ( v3 != (_DWORD *)v4 );\n return v5;\n}", + "ida_strip_asm": "sub_12D0:\nendbr64\npush rbp\nmovsxd rsi, esi; nmemb\nlea rcx, compar; compar\nmov edx, 4; size\npush rbx\nmov rbp, rsi\nmov rbx, rdi\nsub rsp, 8\ncall _qsort\nmov eax, [rbx]\ncmp ebp, 1\njle short loc_1330\nlea ecx, [rbp-2]\nlea rdx, [rbx+4]\nlea r8, [rbx+rcx*4+8]\nmov ecx, eax\nnop dword ptr [rax+00000000h]\nloc_1310:\nmov edi, eax\nmov eax, [rdx]\ncmp edi, eax\nlea esi, [rcx+rax]\ncmovnz ecx, esi\nadd rdx, 4\ncmp rdx, r8\njnz short loc_1310\nadd rsp, 8\nmov eax, ecx\npop rbx\npop rbp\nretn\nloc_1330:\nadd rsp, 8\nmov ecx, eax\nmov eax, ecx\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12D0(_DWORD *a1, int a2)\n{\n __int64 result; // rax\n _DWORD *v3; // rdx\n __int64 v4; // r8\n unsigned int v5; // ecx\n int v6; // edi\n\n qsort(a1, a2, 4uLL, compar);\n LODWORD(result) = *a1;\n if ( a2 <= 1 )\n return (unsigned int)result;\n v3 = a1 + 1;\n v4 = (__int64)&a1[a2 - 2 + 2];\n v5 = *a1;\n do\n {\n v6 = result;\n LODWORD(result) = *v3;\n if ( v6 != *v3 )\n v5 += *v3;\n ++v3;\n }\n while ( v3 != (_DWORD *)v4 );\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12D0(uint32_t *a1, int a2) {\n long long result;\n uint32_t *v3;\n long long v4;\n unsigned int v5;\n int v6;\n qsort(a1, a2, 4uLL, compar);\n LODWORD(result) = *a1;\n if (a2 <= 1) return (unsigned int)result;\n v3 = a1 + 1;\n v4 = (long long)&a1[a2 - 2 + 2];\n v5 = *a1;\n do {\n v6 = result;\n LODWORD(result) = *v3;\n if (v6 != *v3) v5 += *v3;\n ++v3;\n } while (v3 != (uint32_t *)v4);\n return v5;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n long long result;\n uint32_t *v3;\n long long v4;\n unsigned int v5;\n int v6;\n qsort(a1, a2, 4uLL, compare);\n LODWORD(result) = *a1;\n if (a2 <= 1) return (unsigned int)result;\n v3 = a1 + 1;\n v4 = (long long)&a1[a2 - 2 + 2];\n v5 = *a1;\n do {\n v6 = result;\n LODWORD(result) = *v3;\n if (v6 != *v3) v5 += *v3;\n ++v3;\n } while (v3 != (uint32_t *)v4);\n return v5;\n}" + }, + { + "index": 777, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint compare(const void* a, const void* b) {\n\n return (*(int*)a - *(int*)b);\n\n}\n\n\n\n", + "func": "int func0(int* arr, int n) {\n qsort(arr, n, sizeof(int), compare);\n int sum = arr[0];\n for (int i = 0; i < n - 1; i++) {\n if (arr[i] != arr[i + 1]) {\n sum += arr[i + 1];\n }\n }\n return sum;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 1, 1, 4, 5, 6};\n\n int arr2[] = {1, 10, 9, 4, 2, 10, 10, 45, 4};\n\n int arr3[] = {12, 10, 9, 45, 2, 10, 10, 45, 10};\n\n assert(func0(arr1, 8) == 21);\n\n assert(func0(arr2, 9) == 71);\n\n assert(func0(arr3, 9) == 78);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmovslq %esi,%rsi\nlea -0x1f(%rip),%rcx\nmov $0x4,%edx\npush %rbx\nmov %rsi,%rbp\nmov %rdi,%rbx\nsub $0x8,%rsp\ncallq 1070 \nlea -0x1(%rbp),%ecx\nmov (%rbx),%r8d\ntest %ecx,%ecx\njle 13af \nsub $0x2,%ebp\ncmp $0x2,%ebp\njbe 13b9 \nmov %ecx,%edx\nmov %rbx,%rax\npxor %xmm1,%xmm1\nshr $0x2,%edx\nshl $0x4,%rdx\nadd %rbx,%rdx\nnopl 0x0(%rax)\nmovdqu 0x4(%rax),%xmm2\nmovdqu (%rax),%xmm0\nadd $0x10,%rax\npcmpeqd %xmm2,%xmm0\npandn %xmm2,%xmm0\npaddd %xmm0,%xmm1\ncmp %rdx,%rax\njne 1328 \nmovdqa %xmm1,%xmm0\npsrldq $0x8,%xmm0\npaddd %xmm0,%xmm1\nmovdqa %xmm1,%xmm0\npsrldq $0x4,%xmm0\npaddd %xmm0,%xmm1\nmovd %xmm1,%eax\nadd %eax,%r8d\nmov %ecx,%eax\nand $0xfffffffc,%eax\ntest $0x3,%cl\nje 13af \nmovslq %eax,%rdx\nmov 0x4(%rbx,%rdx,4),%esi\ncmp %esi,(%rbx,%rdx,4)\nje 1380 \nadd %esi,%r8d\nlea 0x1(%rax),%edx\ncmp %edx,%ecx\njle 13af \nmovslq %edx,%rdx\nmov 0x4(%rbx,%rdx,4),%edx\ncmp %esi,%edx\nlea (%r8,%rdx,1),%edi\ncmovne %edi,%r8d\nadd $0x2,%eax\ncmp %eax,%ecx\njle 13af \ncltq\nmov 0x4(%rbx,%rax,4),%eax\nlea (%r8,%rax,1),%ecx\ncmp %eax,%edx\ncmovne %ecx,%r8d\nadd $0x8,%rsp\nmov %r8d,%eax\npop %rbx\npop %rbp\nretq\nxor %eax,%eax\njmp 1371 \nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmovsxd rsi, esi; nmemb\nlea rcx, compare; compar\nmov edx, 4; size\npush rbx\nmov rbp, rsi\nmov rbx, rdi\nsub rsp, 8\ncall _qsort\nmov ecx, [rbx]\ncmp ebp, 1\njle loc_13B5\nlea esi, [rbp-1]\nsub ebp, 2\ncmp ebp, 2\njbe loc_13BE\nmov edx, esi\nmov rax, rbx\npxor xmm1, xmm1\nshr edx, 2\nshl rdx, 4\nadd rdx, rbx\nnop dword ptr [rax+00000000h]\nloc_1328:\nmovdqu xmm2, xmmword ptr [rax+4]\nmovdqu xmm0, xmmword ptr [rax]\nadd rax, 10h\npcmpeqd xmm0, xmm2\npandn xmm0, xmm2\npaddd xmm1, xmm0\ncmp rdx, rax\njnz short loc_1328\nmovdqa xmm0, xmm1\npsrldq xmm0, 8\npaddd xmm1, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm0, 4\npaddd xmm1, xmm0\nmovd eax, xmm1\nadd ecx, eax\nmov eax, esi\nand eax, 0FFFFFFFCh\ntest sil, 3\njz short loc_13B5\nloc_1371:\nmovsxd r8, eax\nlea rdx, ds:0[r8*4]\nmov edi, [rbx+rdx+4]\ncmp [rbx+r8*4], edi\njz short loc_1388\nadd ecx, edi\nloc_1388:\nlea r8d, [rax+1]\ncmp esi, r8d\njle short loc_13B5\nmov r8d, [rbx+rdx+8]\ncmp edi, r8d\nlea r9d, [rcx+r8]\ncmovnz ecx, r9d\nadd eax, 2\ncmp esi, eax\njle short loc_13B5\nmov eax, [rbx+rdx+0Ch]\nlea edx, [rcx+rax]\ncmp r8d, eax\ncmovnz ecx, edx\nloc_13B5:\nadd rsp, 8\nmov eax, ecx\npop rbx\npop rbp\nretn\nloc_13BE:\nxor eax, eax\njmp short loc_1371", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n unsigned int v4; // ecx\n int v5; // esi\n _DWORD *v6; // rax\n __m128i v7; // xmm1\n __m128i v8; // xmm2\n __m128i v9; // xmm0\n __m128i v10; // xmm1\n signed int v11; // eax\n __int64 v12; // rdx\n int v13; // edi\n int v14; // r8d\n int v15; // eax\n\n qsort(a1, a2, 4uLL, compare);\n v4 = *a1;\n if ( a2 > 1 )\n {\n v5 = a2 - 1;\n if ( (unsigned int)(a2 - 2) <= 2 )\n {\n v11 = 0;\n }\n else\n {\n v6 = a1;\n v7 = 0LL;\n do\n {\n v8 = _mm_loadu_si128((const __m128i *)(v6 + 1));\n v9 = _mm_loadu_si128((const __m128i *)v6);\n v6 += 4;\n v7 = _mm_add_epi32(v7, _mm_andnot_si128(_mm_cmpeq_epi32(v9, v8), v8));\n }\n while ( &a1[4 * ((unsigned int)v5 >> 2)] != v6 );\n v10 = _mm_add_epi32(v7, _mm_srli_si128(v7, 8));\n v4 += _mm_cvtsi128_si32(_mm_add_epi32(v10, _mm_srli_si128(v10, 4)));\n v11 = v5 & 0xFFFFFFFC;\n if ( (v5 & 3) == 0 )\n return v4;\n }\n v12 = v11;\n v13 = a1[v12 + 1];\n if ( a1[v12] != v13 )\n v4 += v13;\n if ( v5 > v11 + 1 )\n {\n v14 = a1[v12 + 2];\n if ( v13 != v14 )\n v4 += v14;\n if ( v5 > v11 + 2 )\n {\n v15 = a1[v12 + 3];\n if ( v14 != v15 )\n v4 += v15;\n }\n }\n }\n return v4;\n}", + "ida_strip_asm": "sub_12D0:\nendbr64\npush rbp\nmovsxd rsi, esi; nmemb\nlea rcx, compar; compar\nmov edx, 4; size\npush rbx\nmov rbp, rsi\nmov rbx, rdi\nsub rsp, 8\ncall _qsort\nmov ecx, [rbx]\ncmp ebp, 1\njle loc_13B5\nlea esi, [rbp-1]\nsub ebp, 2\ncmp ebp, 2\njbe loc_13BE\nmov edx, esi\nmov rax, rbx\npxor xmm1, xmm1\nshr edx, 2\nshl rdx, 4\nadd rdx, rbx\nnop dword ptr [rax+00000000h]\nloc_1328:\nmovdqu xmm2, xmmword ptr [rax+4]\nmovdqu xmm0, xmmword ptr [rax]\nadd rax, 10h\npcmpeqd xmm0, xmm2\npandn xmm0, xmm2\npaddd xmm1, xmm0\ncmp rdx, rax\njnz short loc_1328\nmovdqa xmm0, xmm1\npsrldq xmm0, 8\npaddd xmm1, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm0, 4\npaddd xmm1, xmm0\nmovd eax, xmm1\nadd ecx, eax\nmov eax, esi\nand eax, 0FFFFFFFCh\ntest sil, 3\njz short loc_13B5\nloc_1371:\nmovsxd r8, eax\nlea rdx, ds:0[r8*4]\nmov edi, [rbx+rdx+4]\ncmp [rbx+r8*4], edi\njz short loc_1388\nadd ecx, edi\nloc_1388:\nlea r8d, [rax+1]\ncmp esi, r8d\njle short loc_13B5\nmov r8d, [rbx+rdx+8]\ncmp edi, r8d\nlea r9d, [rcx+r8]\ncmovnz ecx, r9d\nadd eax, 2\ncmp esi, eax\njle short loc_13B5\nmov eax, [rbx+rdx+0Ch]\nlea edx, [rcx+rax]\ncmp r8d, eax\ncmovnz ecx, edx\nloc_13B5:\nadd rsp, 8\nmov eax, ecx\npop rbx\npop rbp\nretn\nloc_13BE:\nxor eax, eax\njmp short loc_1371", + "ida_strip_pseudo": "__int64 __fastcall sub_12D0(_DWORD *a1, int a2)\n{\n unsigned int v4; // ecx\n int v5; // esi\n _DWORD *v6; // rax\n __m128i v7; // xmm1\n __m128i v8; // xmm2\n __m128i v9; // xmm0\n __m128i v10; // xmm1\n signed int v11; // eax\n __int64 v12; // rdx\n int v13; // edi\n int v14; // r8d\n int v15; // eax\n\n qsort(a1, a2, 4uLL, compar);\n v4 = *a1;\n if ( a2 > 1 )\n {\n v5 = a2 - 1;\n if ( (unsigned int)(a2 - 2) <= 2 )\n {\n v11 = 0;\n }\n else\n {\n v6 = a1;\n v7 = 0LL;\n do\n {\n v8 = _mm_loadu_si128((const __m128i *)(v6 + 1));\n v9 = _mm_loadu_si128((const __m128i *)v6);\n v6 += 4;\n v7 = _mm_add_epi32(v7, _mm_andnot_si128(_mm_cmpeq_epi32(v9, v8), v8));\n }\n while ( &a1[4 * ((unsigned int)v5 >> 2)] != v6 );\n v10 = _mm_add_epi32(v7, _mm_srli_si128(v7, 8));\n v4 += _mm_cvtsi128_si32(_mm_add_epi32(v10, _mm_srli_si128(v10, 4)));\n v11 = v5 & 0xFFFFFFFC;\n if ( (v5 & 3) == 0 )\n return v4;\n }\n v12 = v11;\n v13 = a1[v12 + 1];\n if ( a1[v12] != v13 )\n v4 += v13;\n if ( v5 > v11 + 1 )\n {\n v14 = a1[v12 + 2];\n if ( v13 != v14 )\n v4 += v14;\n if ( v5 > v11 + 2 )\n {\n v15 = a1[v12 + 3];\n if ( v14 != v15 )\n v4 += v15;\n }\n }\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12D0(uint32_t *a1, int a2) {\n unsigned int v4;\n int v5;\n uint32_t *v6;\n __m128i v7;\n __m128i v8;\n __m128i v9;\n __m128i v10;\n signed int v11;\n long long v12;\n int v13;\n int v14;\n int v15;\n qsort(a1, a2, 4uLL, compar);\n v4 = *a1;\n if (a2 > 1) {\n v5 = a2 - 1;\n if ((unsigned int)(a2 - 2) <= 2) {\n v11 = 0;\n } else {\n v6 = a1;\n v7 = 0LL;\n do {\n v8 = _mm_loadu_si128((const __m128i *)(v6 + 1));\n v9 = _mm_loadu_si128((const __m128i *)v6);\n v6 += 4;\n v7 = _mm_add_epi32(v7, _mm_andnot_si128(_mm_cmpeq_epi32(v9, v8), v8));\n } while (&a1[4 * ((unsigned int)v5 >> 2)] != v6);\n v10 = _mm_add_epi32(v7, _mm_srli_si128(v7, 8));\n v4 += _mm_cvtsi128_si32(_mm_add_epi32(v10, _mm_srli_si128(v10, 4)));\n v11 = v5 & 4294967292;\n if ((v5 & 3) == 0) return v4;\n }\n v12 = v11;\n v13 = a1[v12 + 1];\n if (a1[v12] != v13) v4 += v13;\n if (v5 > v11 + 1) {\n v14 = a1[v12 + 2];\n if (v13 != v14) v4 += v14;\n if (v5 > v11 + 2) {\n v15 = a1[v12 + 3];\n if (v14 != v15) v4 += v15;\n }\n }\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n unsigned int v4;\n int v5;\n uint32_t *v6;\n __m128i v7;\n __m128i v8;\n __m128i v9;\n __m128i v10;\n signed int v11;\n long long v12;\n int v13;\n int v14;\n int v15;\n qsort(a1, a2, 4uLL, compare);\n v4 = *a1;\n if (a2 > 1) {\n v5 = a2 - 1;\n if ((unsigned int)(a2 - 2) <= 2) {\n v11 = 0;\n } else {\n v6 = a1;\n v7 = 0LL;\n do {\n v8 = _mm_loadu_si128((const __m128i *)(v6 + 1));\n v9 = _mm_loadu_si128((const __m128i *)v6);\n v6 += 4;\n v7 = _mm_add_epi32(v7, _mm_andnot_si128(_mm_cmpeq_epi32(v9, v8), v8));\n } while (&a1[4 * ((unsigned int)v5 >> 2)] != v6);\n v10 = _mm_add_epi32(v7, _mm_srli_si128(v7, 8));\n v4 += _mm_cvtsi128_si32(_mm_add_epi32(v10, _mm_srli_si128(v10, 4)));\n v11 = v5 & 4294967292;\n if ((v5 & 3) == 0) return v4;\n }\n v12 = v11;\n v13 = a1[v12 + 1];\n if (a1[v12] != v13) v4 += v13;\n if (v5 > v11 + 1) {\n v14 = a1[v12 + 2];\n if (v13 != v14) v4 += v14;\n if (v5 > v11 + 2) {\n v15 = a1[v12 + 3];\n if (v14 != v15) v4 += v15;\n }\n }\n }\n return v4;\n}" + }, + { + "index": 778, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int **group;\n\n int *groupSize;\n\n int numGroups;\n\n} PackResult;\n\n\n\nint compare_arrays(int a[], int b[], int a_size, int b_size) {\n\n if (a_size != b_size)\n\n return 0;\n\n\n\n for (int i = 0; i < a_size; i++) {\n\n if (a[i] != b[i]) {\n\n return 0;\n\n }\n\n }\n\n return 1;\n\n}\n\n\n\n", + "func": "PackResult* func0(int list1[], int size) {\n PackResult* result = malloc(sizeof(PackResult));\n result->group = malloc(sizeof(int*) * size);\n result->groupSize = malloc(sizeof(int) * size);\n result->numGroups = 0;\n if (size == 0) {\n return result;\n }\n int current_value = list1[0];\n int group_count = 0;\n result->group[result->numGroups] = malloc(sizeof(int) * size);\n result->group[result->numGroups][group_count++] = current_value;\n for (int i = 1; i < size; i++) {\n if (list1[i] == current_value) {\n result->group[result->numGroups][group_count++] = list1[i];\n } else {\n result->groupSize[result->numGroups] = group_count;\n result->numGroups++;\n current_value = list1[i];\n result->group[result->numGroups] = malloc(sizeof(int) * size);\n group_count = 0;\n result->group[result->numGroups][group_count++] = current_value;\n }\n }\n result->groupSize[result->numGroups] = group_count;\n result->numGroups++;\n return result;\n}", + "test": "int main() {\n\n // Test Case 1\n\n int input1[] = {0, 0, 1, 2, 3, 4, 4, 5, 6, 6, 6, 7, 8, 9, 4, 4};\n\n int size1 = sizeof(input1)/sizeof(input1[0]);\n\n PackResult* result1 = func0(input1, size1);\n\n assert(result1->numGroups == 11);\n\n assert(compare_arrays(result1->group[0], (int[]){0, 0}, result1->groupSize[0], 2));\n\n assert(compare_arrays(result1->group[1], (int[]){1}, result1->groupSize[1], 1));\n\n assert(compare_arrays(result1->group[4], (int[]){4, 4}, result1->groupSize[4], 2));\n\n assert(compare_arrays(result1->group[10], (int[]){4, 4}, result1->groupSize[10], 2));\n\n\n\n // Test Case 2\n\n int input2[] = {10, 10, 15, 19, 18, 18, 17, 26, 26, 17, 18, 10};\n\n int size2 = sizeof(input2)/sizeof(input2[0]);\n\n PackResult* result2 = func0(input2, size2);\n\n assert(result2->numGroups == 9);\n\n assert(compare_arrays(result2->group[0], (int[]){10, 10}, result2->groupSize[0], 2));\n\n assert(compare_arrays(result2->group[5], (int[]){26, 26}, result2->groupSize[5], 2));\n\n\n\n // Cleaning up memory\n\n for (int i = 0; i < result1->numGroups; i++) {\n\n free(result1->group[i]);\n\n }\n\n free(result1->group);\n\n free(result1->groupSize);\n\n free(result1);\n\n\n\n for (int i = 0; i < result2->numGroups; i++) {\n\n free(result2->group[i]);\n\n }\n\n free(result2->group);\n\n free(result2->groupSize);\n\n free(result2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x38,%rsp\nmov %rdi,-0x38(%rbp)\nmov %esi,-0x3c(%rbp)\nmov $0x18,%edi\ncallq 10b0 \nmov %rax,-0x18(%rbp)\nmov -0x3c(%rbp),%eax\ncltq\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nmov %rdx,(%rax)\nmov -0x3c(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nmov %rdx,0x8(%rax)\nmov -0x18(%rbp),%rax\nmovl $0x0,0x10(%rax)\ncmpl $0x0,-0x3c(%rbp)\njne 1294 \nmov -0x18(%rbp),%rax\njmpq 1464 \nmov -0x38(%rbp),%rax\nmov (%rax),%eax\nmov %eax,-0x24(%rbp)\nmovl $0x0,-0x20(%rbp)\nmov -0x3c(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov -0x18(%rbp),%rdx\nmov (%rdx),%rcx\nmov -0x18(%rbp),%rdx\nmov 0x10(%rdx),%edx\nmovslq %edx,%rdx\nshl $0x3,%rdx\nlea (%rcx,%rdx,1),%rbx\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,(%rbx)\nmov -0x18(%rbp),%rax\nmov (%rax),%rdx\nmov -0x18(%rbp),%rax\nmov 0x10(%rax),%eax\ncltq\nshl $0x3,%rax\nadd %rdx,%rax\nmov (%rax),%rcx\nmov -0x20(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x20(%rbp)\ncltq\nshl $0x2,%rax\nlea (%rcx,%rax,1),%rdx\nmov -0x24(%rbp),%eax\nmov %eax,(%rdx)\nmovl $0x1,-0x1c(%rbp)\njmpq 1426 \nmov -0x1c(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x24(%rbp)\njne 1375 \nmov -0x1c(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x38(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x18(%rbp),%rax\nmov (%rax),%rdx\nmov -0x18(%rbp),%rax\nmov 0x10(%rax),%eax\ncltq\nshl $0x3,%rax\nadd %rdx,%rax\nmov (%rax),%rsi\nmov -0x20(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x20(%rbp)\ncltq\nshl $0x2,%rax\nlea (%rsi,%rax,1),%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\njmpq 1422 \nmov -0x18(%rbp),%rax\nmov 0x8(%rax),%rdx\nmov -0x18(%rbp),%rax\nmov 0x10(%rax),%eax\ncltq\nshl $0x2,%rax\nadd %rax,%rdx\nmov -0x20(%rbp),%eax\nmov %eax,(%rdx)\nmov -0x18(%rbp),%rax\nmov 0x10(%rax),%eax\nlea 0x1(%rax),%edx\nmov -0x18(%rbp),%rax\nmov %edx,0x10(%rax)\nmov -0x1c(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x24(%rbp)\nmov -0x3c(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov -0x18(%rbp),%rdx\nmov (%rdx),%rcx\nmov -0x18(%rbp),%rdx\nmov 0x10(%rdx),%edx\nmovslq %edx,%rdx\nshl $0x3,%rdx\nlea (%rcx,%rdx,1),%rbx\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,(%rbx)\nmovl $0x0,-0x20(%rbp)\nmov -0x18(%rbp),%rax\nmov (%rax),%rdx\nmov -0x18(%rbp),%rax\nmov 0x10(%rax),%eax\ncltq\nshl $0x3,%rax\nadd %rdx,%rax\nmov (%rax),%rcx\nmov -0x20(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x20(%rbp)\ncltq\nshl $0x2,%rax\nlea (%rcx,%rax,1),%rdx\nmov -0x24(%rbp),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x1c(%rbp)\nmov -0x1c(%rbp),%eax\ncmp -0x3c(%rbp),%eax\njl 130f \nmov -0x18(%rbp),%rax\nmov 0x8(%rax),%rdx\nmov -0x18(%rbp),%rax\nmov 0x10(%rax),%eax\ncltq\nshl $0x2,%rax\nadd %rax,%rdx\nmov -0x20(%rbp),%eax\nmov %eax,(%rdx)\nmov -0x18(%rbp),%rax\nmov 0x10(%rax),%eax\nlea 0x1(%rax),%edx\nmov -0x18(%rbp),%rax\nmov %edx,0x10(%rax)\nmov -0x18(%rbp),%rax\nadd $0x38,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov edi, 18h; size\ncall _malloc\nmov [rbp+var_18], rax\nmov eax, [rbp+var_3C]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov rdx, rax\nmov rax, [rbp+var_18]\nmov [rax], rdx\nmov eax, [rbp+var_3C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov rdx, rax\nmov rax, [rbp+var_18]\nmov [rax+8], rdx\nmov rax, [rbp+var_18]\nmov dword ptr [rax+10h], 0\ncmp [rbp+var_3C], 0\njnz short loc_1294\nmov rax, [rbp+var_18]\njmp loc_1464\nloc_1294:\nmov rax, [rbp+var_38]\nmov eax, [rax]\nmov [rbp+var_24], eax\nmov [rbp+var_20], 0\nmov eax, [rbp+var_3C]\ncdqe\nshl rax, 2\nmov rdx, [rbp+var_18]\nmov rcx, [rdx]\nmov rdx, [rbp+var_18]\nmov edx, [rdx+10h]\nmovsxd rdx, edx\nshl rdx, 3\nlea rbx, [rcx+rdx]\nmov rdi, rax; size\ncall _malloc\nmov [rbx], rax\nmov rax, [rbp+var_18]\nmov rdx, [rax]\nmov rax, [rbp+var_18]\nmov eax, [rax+10h]\ncdqe\nshl rax, 3\nadd rax, rdx\nmov rcx, [rax]\nmov eax, [rbp+var_20]\nlea edx, [rax+1]\nmov [rbp+var_20], edx\ncdqe\nshl rax, 2\nlea rdx, [rcx+rax]\nmov eax, [rbp+var_24]\nmov [rdx], eax\nmov [rbp+var_1C], 1\njmp loc_1426\nloc_130F:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_24], eax\njnz short loc_1375\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nlea rcx, [rdx+rax]\nmov rax, [rbp+var_18]\nmov rdx, [rax]\nmov rax, [rbp+var_18]\nmov eax, [rax+10h]\ncdqe\nshl rax, 3\nadd rax, rdx\nmov rsi, [rax]\nmov eax, [rbp+var_20]\nlea edx, [rax+1]\nmov [rbp+var_20], edx\ncdqe\nshl rax, 2\nlea rdx, [rsi+rax]\nmov eax, [rcx]\nmov [rdx], eax\njmp loc_1422\nloc_1375:\nmov rax, [rbp+var_18]\nmov rdx, [rax+8]\nmov rax, [rbp+var_18]\nmov eax, [rax+10h]\ncdqe\nshl rax, 2\nadd rdx, rax\nmov eax, [rbp+var_20]\nmov [rdx], eax\nmov rax, [rbp+var_18]\nmov eax, [rax+10h]\nlea edx, [rax+1]\nmov rax, [rbp+var_18]\nmov [rax+10h], edx\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_24], eax\nmov eax, [rbp+var_3C]\ncdqe\nshl rax, 2\nmov rdx, [rbp+var_18]\nmov rcx, [rdx]\nmov rdx, [rbp+var_18]\nmov edx, [rdx+10h]\nmovsxd rdx, edx\nshl rdx, 3\nlea rbx, [rcx+rdx]\nmov rdi, rax; size\ncall _malloc\nmov [rbx], rax\nmov [rbp+var_20], 0\nmov rax, [rbp+var_18]\nmov rdx, [rax]\nmov rax, [rbp+var_18]\nmov eax, [rax+10h]\ncdqe\nshl rax, 3\nadd rax, rdx\nmov rcx, [rax]\nmov eax, [rbp+var_20]\nlea edx, [rax+1]\nmov [rbp+var_20], edx\ncdqe\nshl rax, 2\nlea rdx, [rcx+rax]\nmov eax, [rbp+var_24]\nmov [rdx], eax\nloc_1422:\nadd [rbp+var_1C], 1\nloc_1426:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_3C]\njl loc_130F\nmov rax, [rbp+var_18]\nmov rdx, [rax+8]\nmov rax, [rbp+var_18]\nmov eax, [rax+10h]\ncdqe\nshl rax, 2\nadd rdx, rax\nmov eax, [rbp+var_20]\nmov [rdx], eax\nmov rax, [rbp+var_18]\nmov eax, [rax+10h]\nlea edx, [rax+1]\nmov rax, [rbp+var_18]\nmov [rax+10h], edx\nmov rax, [rbp+var_18]\nloc_1464:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(int *a1, int a2)\n{\n void **v3; // rbx\n int v4; // eax\n void **v5; // rbx\n int v6; // [rsp+1Ch] [rbp-24h]\n int v7; // [rsp+20h] [rbp-20h]\n int i; // [rsp+24h] [rbp-1Ch]\n _QWORD *v9; // [rsp+28h] [rbp-18h]\n\n v9 = malloc(0x18uLL);\n *v9 = malloc(8LL * a2);\n v9[1] = malloc(4LL * a2);\n *((_DWORD *)v9 + 4) = 0;\n if ( !a2 )\n return v9;\n v6 = *a1;\n v3 = (void **)(*v9 + 8LL * *((int *)v9 + 4));\n *v3 = malloc(4LL * a2);\n v7 = 1;\n **(_DWORD **)(*v9 + 8LL * *((int *)v9 + 4)) = v6;\n for ( i = 1; i < a2; ++i )\n {\n if ( v6 == a1[i] )\n {\n v4 = v7++;\n *(_DWORD *)(*(_QWORD *)(*v9 + 8LL * *((int *)v9 + 4)) + 4LL * v4) = a1[i];\n }\n else\n {\n *(_DWORD *)(4LL * (int)(*((_DWORD *)v9 + 4))++ + v9[1]) = v7;\n v6 = a1[i];\n v5 = (void **)(*v9 + 8LL * *((int *)v9 + 4));\n *v5 = malloc(4LL * a2);\n v7 = 1;\n **(_DWORD **)(*v9 + 8LL * *((int *)v9 + 4)) = v6;\n }\n }\n *(_DWORD *)(4LL * (int)(*((_DWORD *)v9 + 4))++ + v9[1]) = v7;\n return v9;\n}", + "ida_strip_asm": "sub_1221:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov edi, 18h; size\ncall _malloc\nmov [rbp+var_18], rax\nmov eax, [rbp+var_3C]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov rdx, rax\nmov rax, [rbp+var_18]\nmov [rax], rdx\nmov eax, [rbp+var_3C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov rdx, rax\nmov rax, [rbp+var_18]\nmov [rax+8], rdx\nmov rax, [rbp+var_18]\nmov dword ptr [rax+10h], 0\ncmp [rbp+var_3C], 0\njnz short loc_1294\nmov rax, [rbp+var_18]\njmp loc_1464\nloc_1294:\nmov rax, [rbp+var_38]\nmov eax, [rax]\nmov [rbp+var_24], eax\nmov [rbp+var_20], 0\nmov eax, [rbp+var_3C]\ncdqe\nshl rax, 2\nmov rdx, [rbp+var_18]\nmov rcx, [rdx]\nmov rdx, [rbp+var_18]\nmov edx, [rdx+10h]\nmovsxd rdx, edx\nshl rdx, 3\nlea rbx, [rcx+rdx]\nmov rdi, rax; size\ncall _malloc\nmov [rbx], rax\nmov rax, [rbp+var_18]\nmov rdx, [rax]\nmov rax, [rbp+var_18]\nmov eax, [rax+10h]\ncdqe\nshl rax, 3\nadd rax, rdx\nmov rcx, [rax]\nmov eax, [rbp+var_20]\nlea edx, [rax+1]\nmov [rbp+var_20], edx\ncdqe\nshl rax, 2\nlea rdx, [rcx+rax]\nmov eax, [rbp+var_24]\nmov [rdx], eax\nmov [rbp+var_1C], 1\njmp loc_1426\nloc_130F:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_24], eax\njnz short loc_1375\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nlea rcx, [rdx+rax]\nmov rax, [rbp+var_18]\nmov rdx, [rax]\nmov rax, [rbp+var_18]\nmov eax, [rax+10h]\ncdqe\nshl rax, 3\nadd rax, rdx\nmov rsi, [rax]\nmov eax, [rbp+var_20]\nlea edx, [rax+1]\nmov [rbp+var_20], edx\ncdqe\nshl rax, 2\nlea rdx, [rsi+rax]\nmov eax, [rcx]\nmov [rdx], eax\njmp loc_1422\nloc_1375:\nmov rax, [rbp+var_18]\nmov rdx, [rax+8]\nmov rax, [rbp+var_18]\nmov eax, [rax+10h]\ncdqe\nshl rax, 2\nadd rdx, rax\nmov eax, [rbp+var_20]\nmov [rdx], eax\nmov rax, [rbp+var_18]\nmov eax, [rax+10h]\nlea edx, [rax+1]\nmov rax, [rbp+var_18]\nmov [rax+10h], edx\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_24], eax\nmov eax, [rbp+var_3C]\ncdqe\nshl rax, 2\nmov rdx, [rbp+var_18]\nmov rcx, [rdx]\nmov rdx, [rbp+var_18]\nmov edx, [rdx+10h]\nmovsxd rdx, edx\nshl rdx, 3\nlea rbx, [rcx+rdx]\nmov rdi, rax; size\ncall _malloc\nmov [rbx], rax\nmov [rbp+var_20], 0\nmov rax, [rbp+var_18]\nmov rdx, [rax]\nmov rax, [rbp+var_18]\nmov eax, [rax+10h]\ncdqe\nshl rax, 3\nadd rax, rdx\nmov rcx, [rax]\nmov eax, [rbp+var_20]\nlea edx, [rax+1]\nmov [rbp+var_20], edx\ncdqe\nshl rax, 2\nlea rdx, [rcx+rax]\nmov eax, [rbp+var_24]\nmov [rdx], eax\nloc_1422:\nadd [rbp+var_1C], 1\nloc_1426:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_3C]\njl loc_130F\nmov rax, [rbp+var_18]\nmov rdx, [rax+8]\nmov rax, [rbp+var_18]\nmov eax, [rax+10h]\ncdqe\nshl rax, 2\nadd rdx, rax\nmov eax, [rbp+var_20]\nmov [rdx], eax\nmov rax, [rbp+var_18]\nmov eax, [rax+10h]\nlea edx, [rax+1]\nmov rax, [rbp+var_18]\nmov [rax+10h], edx\nmov rax, [rbp+var_18]\nloc_1464:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1221(int *a1, int a2)\n{\n void **v3; // rbx\n int v4; // eax\n void **v5; // rbx\n int v6; // [rsp+1Ch] [rbp-24h]\n int v7; // [rsp+20h] [rbp-20h]\n int i; // [rsp+24h] [rbp-1Ch]\n _QWORD *v9; // [rsp+28h] [rbp-18h]\n\n v9 = malloc(0x18uLL);\n *v9 = malloc(8LL * a2);\n v9[1] = malloc(4LL * a2);\n *((_DWORD *)v9 + 4) = 0;\n if ( !a2 )\n return v9;\n v6 = *a1;\n v3 = (void **)(*v9 + 8LL * *((int *)v9 + 4));\n *v3 = malloc(4LL * a2);\n v7 = 1;\n **(_DWORD **)(*v9 + 8LL * *((int *)v9 + 4)) = v6;\n for ( i = 1; i < a2; ++i )\n {\n if ( v6 == a1[i] )\n {\n v4 = v7++;\n *(_DWORD *)(*(_QWORD *)(*v9 + 8LL * *((int *)v9 + 4)) + 4LL * v4) = a1[i];\n }\n else\n {\n *(_DWORD *)(4LL * (int)(*((_DWORD *)v9 + 4))++ + v9[1]) = v7;\n v6 = a1[i];\n v5 = (void **)(*v9 + 8LL * *((int *)v9 + 4));\n *v5 = malloc(4LL * a2);\n v7 = 1;\n **(_DWORD **)(*v9 + 8LL * *((int *)v9 + 4)) = v6;\n }\n }\n *(_DWORD *)(4LL * (int)(*((_DWORD *)v9 + 4))++ + v9[1]) = v7;\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1221(int *a1, int a2) {\n void **v3;\n int v4;\n void **v5;\n int v6;\n int v7;\n int i;\n uint64_t *v9;\n v9 = malloc(24uLL);\n *v9 = malloc(8LL * a2);\n v9[1] = malloc(4LL * a2);\n *((uint32_t *)v9 + 4) = 0;\n if (!a2) return v9;\n v6 = *a1;\n v3 = (void **)(*v9 + 8LL * *((int *)v9 + 4));\n *v3 = malloc(4LL * a2);\n v7 = 1;\n **(uint32_t **)(*v9 + 8LL * *((int *)v9 + 4)) = v6;\n for (i = 1; i < a2; ++i) {\n if (v6 == a1[i]) {\n v4 = v7++;\n *(uint32_t *)(*(uint64_t *)(*v9 + 8LL * *((int *)v9 + 4)) + 4LL * v4) =\n a1[i];\n } else {\n *(uint32_t *)(4LL * (int)(*((uint32_t *)v9 + 4))++ + v9[1]) = v7;\n v6 = a1[i];\n v5 = (void **)(*v9 + 8LL * *((int *)v9 + 4));\n *v5 = malloc(4LL * a2);\n v7 = 1;\n **(uint32_t **)(*v9 + 8LL * *((int *)v9 + 4)) = v6;\n }\n }\n *(uint32_t *)(4LL * (int)(*((uint32_t *)v9 + 4))++ + v9[1]) = v7;\n return v9;\n}", + "ida_pseudo_norm": "uint64_t *func0(int *a1, int a2) {\n void **v3;\n int v4;\n void **v5;\n int v6;\n int v7;\n int i;\n uint64_t *v9;\n v9 = malloc(24uLL);\n *v9 = malloc(8LL * a2);\n v9[1] = malloc(4LL * a2);\n *((uint32_t *)v9 + 4) = 0;\n if (!a2) return v9;\n v6 = *a1;\n v3 = (void **)(*v9 + 8LL * *((int *)v9 + 4));\n *v3 = malloc(4LL * a2);\n v7 = 1;\n **(uint32_t **)(*v9 + 8LL * *((int *)v9 + 4)) = v6;\n for (i = 1; i < a2; ++i) {\n if (v6 == a1[i]) {\n v4 = v7++;\n *(uint32_t *)(*(uint64_t *)(*v9 + 8LL * *((int *)v9 + 4)) + 4LL * v4) =\n a1[i];\n } else {\n *(uint32_t *)(4LL * (int)(*((uint32_t *)v9 + 4))++ + v9[1]) = v7;\n v6 = a1[i];\n v5 = (void **)(*v9 + 8LL * *((int *)v9 + 4));\n *v5 = malloc(4LL * a2);\n v7 = 1;\n **(uint32_t **)(*v9 + 8LL * *((int *)v9 + 4)) = v6;\n }\n }\n *(uint32_t *)(4LL * (int)(*((uint32_t *)v9 + 4))++ + v9[1]) = v7;\n return v9;\n}" + }, + { + "index": 778, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int **group;\n\n int *groupSize;\n\n int numGroups;\n\n} PackResult;\n\n\n\nint compare_arrays(int a[], int b[], int a_size, int b_size) {\n\n if (a_size != b_size)\n\n return 0;\n\n\n\n for (int i = 0; i < a_size; i++) {\n\n if (a[i] != b[i]) {\n\n return 0;\n\n }\n\n }\n\n return 1;\n\n}\n\n\n\n", + "func": "PackResult* func0(int list1[], int size) {\n PackResult* result = malloc(sizeof(PackResult));\n result->group = malloc(sizeof(int*) * size);\n result->groupSize = malloc(sizeof(int) * size);\n result->numGroups = 0;\n if (size == 0) {\n return result;\n }\n int current_value = list1[0];\n int group_count = 0;\n result->group[result->numGroups] = malloc(sizeof(int) * size);\n result->group[result->numGroups][group_count++] = current_value;\n for (int i = 1; i < size; i++) {\n if (list1[i] == current_value) {\n result->group[result->numGroups][group_count++] = list1[i];\n } else {\n result->groupSize[result->numGroups] = group_count;\n result->numGroups++;\n current_value = list1[i];\n result->group[result->numGroups] = malloc(sizeof(int) * size);\n group_count = 0;\n result->group[result->numGroups][group_count++] = current_value;\n }\n }\n result->groupSize[result->numGroups] = group_count;\n result->numGroups++;\n return result;\n}", + "test": "int main() {\n\n // Test Case 1\n\n int input1[] = {0, 0, 1, 2, 3, 4, 4, 5, 6, 6, 6, 7, 8, 9, 4, 4};\n\n int size1 = sizeof(input1)/sizeof(input1[0]);\n\n PackResult* result1 = func0(input1, size1);\n\n assert(result1->numGroups == 11);\n\n assert(compare_arrays(result1->group[0], (int[]){0, 0}, result1->groupSize[0], 2));\n\n assert(compare_arrays(result1->group[1], (int[]){1}, result1->groupSize[1], 1));\n\n assert(compare_arrays(result1->group[4], (int[]){4, 4}, result1->groupSize[4], 2));\n\n assert(compare_arrays(result1->group[10], (int[]){4, 4}, result1->groupSize[10], 2));\n\n\n\n // Test Case 2\n\n int input2[] = {10, 10, 15, 19, 18, 18, 17, 26, 26, 17, 18, 10};\n\n int size2 = sizeof(input2)/sizeof(input2[0]);\n\n PackResult* result2 = func0(input2, size2);\n\n assert(result2->numGroups == 9);\n\n assert(compare_arrays(result2->group[0], (int[]){10, 10}, result2->groupSize[0], 2));\n\n assert(compare_arrays(result2->group[5], (int[]){26, 26}, result2->groupSize[5], 2));\n\n\n\n // Cleaning up memory\n\n for (int i = 0; i < result1->numGroups; i++) {\n\n free(result1->group[i]);\n\n }\n\n free(result1->group);\n\n free(result1->groupSize);\n\n free(result1);\n\n\n\n for (int i = 0; i < result2->numGroups; i++) {\n\n free(result2->group[i]);\n\n }\n\n free(result2->group);\n\n free(result2->groupSize);\n\n free(result2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%r15\nmov %esi,%r14d\nmov $0x18,%edi\ncallq 10b0 \nmov %rax,%rbx\nmovslq %r14d,%r13\nlea 0x0(,%r13,8),%rdi\ncallq 10b0 \nmov %rax,%rbp\nmov %rax,(%rbx)\nshl $0x2,%r13\nmov %r13,%rdi\ncallq 10b0 \nmov %rax,0x8(%rbx)\nmovl $0x0,0x10(%rbx)\ntest %r14d,%r14d\njne 1253 \nmov %rbx,%rax\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmov (%r15),%r12d\nmov %r13,%rdi\ncallq 10b0 \nmov %rax,0x0(%rbp)\nmov %r12d,(%rax)\ncmp $0x1,%r14d\njle 12e4 \nlea 0x4(%r15),%rbp\nlea -0x2(%r14),%eax\nlea 0x8(%r15,%rax,4),%r14\nmov $0x1,%eax\njmp 12c7 \nmovslq 0x10(%rbx),%rcx\nmov 0x8(%rbx),%rdx\nmov %eax,(%rdx,%rcx,4)\nmov 0x10(%rbx),%eax\nadd $0x1,%eax\nmov %eax,0x10(%rbx)\nmov 0x0(%rbp),%r12d\ncltq\nmov (%rbx),%rdx\nlea (%rdx,%rax,8),%r15\nmov %r13,%rdi\ncallq 10b0 \nmov %rax,(%r15)\nmovslq 0x10(%rbx),%rdx\nmov (%rbx),%rax\nmov (%rax,%rdx,8),%rax\nmov %r12d,(%rax)\nmov $0x1,%eax\nadd $0x4,%rbp\ncmp %r14,%rbp\nje 12e9 \ncmp %r12d,0x0(%rbp)\njne 127f \nmovslq 0x10(%rbx),%rsi\nmov (%rbx),%rdx\nmovslq %eax,%rcx\nmov (%rdx,%rsi,8),%rdx\nmov %r12d,(%rdx,%rcx,4)\nlea 0x1(%rax),%eax\njmp 12be \nmov $0x1,%eax\nmovslq 0x10(%rbx),%rcx\nmov 0x8(%rbx),%rdx\nmov %eax,(%rdx,%rcx,4)\naddl $0x1,0x10(%rbx)\njmpq 1241 \n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r15, rdi\nmov r14d, esi\nmov edi, 18h; size\ncall _malloc\nmov rbx, rax\nmovsxd r13, r14d\nlea rdi, ds:0[r13*8]; size\ncall _malloc\nmov rbp, rax\nmov [rbx], rax\nshl r13, 2\nmov rdi, r13; size\ncall _malloc\nmov [rbx+8], rax\nmov dword ptr [rbx+10h], 0\ntest r14d, r14d\njnz short loc_1252\nloc_1240:\nmov rax, rbx\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1252:\nmov r12d, [r15]\nmov rdi, r13; size\ncall _malloc\nmov [rbp+0], rax\nmov [rax], r12d\ncmp r14d, 1\njle short loc_12D7\nlea rbp, [r15+4]\nlea eax, [r14-2]\nlea r14, [r15+rax*4+8]\nmov edx, 1\njmp short loc_12BA\nloc_127E:\nmov eax, [rbx+10h]\nmovsxd rsi, eax\nmov rcx, [rbx+8]\nmov [rcx+rsi*4], edx\nadd eax, 1\nmov [rbx+10h], eax\nmov r12d, [rbp+0]\ncdqe\nmov rdx, [rbx]\nlea r15, [rdx+rax*8]\nmov rdi, r13; size\ncall _malloc\nmov [r15], rax\nmov [rax], r12d\nmov edx, 1\nloc_12B1:\nadd rbp, 4\ncmp rbp, r14\njz short loc_12DC\nloc_12BA:\ncmp [rbp+0], r12d\njnz short loc_127E\nmovsxd rsi, dword ptr [rbx+10h]\nmov rax, [rbx]\nmovsxd rcx, edx\nmov rax, [rax+rsi*8]\nmov [rax+rcx*4], r12d\nlea edx, [rdx+1]\njmp short loc_12B1\nloc_12D7:\nmov edx, 1\nloc_12DC:\nmov eax, [rbx+10h]\nmovsxd rsi, eax\nmov rcx, [rbx+8]\nmov [rcx+rsi*4], edx\nadd eax, 1\nmov [rbx+10h], eax\njmp loc_1240", + "ida_pseudo": "_QWORD *__fastcall func0(int *a1, int a2)\n{\n _QWORD *v2; // rbx\n _QWORD *v3; // rbp\n size_t v4; // r13\n int v6; // r12d\n _DWORD *v7; // rax\n int *v8; // rbp\n int v9; // edx\n int v10; // eax\n _QWORD *v11; // r15\n _DWORD *v12; // rax\n int v13; // eax\n\n v2 = malloc(0x18uLL);\n v3 = malloc(8LL * a2);\n *v2 = v3;\n v4 = 4LL * a2;\n v2[1] = malloc(v4);\n *((_DWORD *)v2 + 4) = 0;\n if ( a2 )\n {\n v6 = *a1;\n v7 = malloc(v4);\n *v3 = v7;\n *v7 = v6;\n if ( a2 <= 1 )\n {\n v9 = 1;\n }\n else\n {\n v8 = a1 + 1;\n v9 = 1;\n do\n {\n if ( *v8 == v6 )\n {\n *(_DWORD *)(*(_QWORD *)(*v2 + 8LL * *((int *)v2 + 4)) + 4LL * v9++) = v6;\n }\n else\n {\n v10 = *((_DWORD *)v2 + 4);\n *(_DWORD *)(v2[1] + 4LL * v10++) = v9;\n *((_DWORD *)v2 + 4) = v10;\n v6 = *v8;\n v11 = (_QWORD *)(*v2 + 8LL * v10);\n v12 = malloc(v4);\n *v11 = v12;\n *v12 = v6;\n v9 = 1;\n }\n ++v8;\n }\n while ( v8 != &a1[a2 - 2 + 2] );\n }\n v13 = *((_DWORD *)v2 + 4);\n *(_DWORD *)(v2[1] + 4LL * v13) = v9;\n *((_DWORD *)v2 + 4) = v13 + 1;\n }\n return v2;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r15, rdi\nmov r14d, esi\nmov edi, 18h; size\ncall _malloc\nmov rbx, rax\nmovsxd r13, r14d\nlea rdi, ds:0[r13*8]; size\ncall _malloc\nmov rbp, rax\nmov [rbx], rax\nshl r13, 2\nmov rdi, r13; size\ncall _malloc\nmov [rbx+8], rax\nmov dword ptr [rbx+10h], 0\ntest r14d, r14d\njnz short loc_1252\nloc_1240:\nmov rax, rbx\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1252:\nmov r12d, [r15]\nmov rdi, r13; size\ncall _malloc\nmov [rbp+0], rax\nmov [rax], r12d\ncmp r14d, 1\njle short loc_12D7\nlea rbp, [r15+4]\nlea eax, [r14-2]\nlea r14, [r15+rax*4+8]\nmov edx, 1\njmp short loc_12BA\nloc_127E:\nmov eax, [rbx+10h]\nmovsxd rsi, eax\nmov rcx, [rbx+8]\nmov [rcx+rsi*4], edx\nadd eax, 1\nmov [rbx+10h], eax\nmov r12d, [rbp+0]\ncdqe\nmov rdx, [rbx]\nlea r15, [rdx+rax*8]\nmov rdi, r13; size\ncall _malloc\nmov [r15], rax\nmov [rax], r12d\nmov edx, 1\nloc_12B1:\nadd rbp, 4\ncmp rbp, r14\njz short loc_12DC\nloc_12BA:\ncmp [rbp+0], r12d\njnz short loc_127E\nmovsxd rsi, dword ptr [rbx+10h]\nmov rax, [rbx]\nmovsxd rcx, edx\nmov rax, [rax+rsi*8]\nmov [rax+rcx*4], r12d\nlea edx, [rdx+1]\njmp short loc_12B1\nloc_12D7:\nmov edx, 1\nloc_12DC:\nmov eax, [rbx+10h]\nmovsxd rsi, eax\nmov rcx, [rbx+8]\nmov [rcx+rsi*4], edx\nadd eax, 1\nmov [rbx+10h], eax\njmp loc_1240", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11E9(int *a1, int a2)\n{\n _QWORD *v2; // rbx\n _QWORD *v3; // rbp\n size_t v4; // r13\n int v6; // r12d\n _DWORD *v7; // rax\n int *v8; // rbp\n int v9; // edx\n int v10; // eax\n _QWORD *v11; // r15\n _DWORD *v12; // rax\n int v13; // eax\n\n v2 = malloc(0x18uLL);\n v3 = malloc(8LL * a2);\n *v2 = v3;\n v4 = 4LL * a2;\n v2[1] = malloc(v4);\n *((_DWORD *)v2 + 4) = 0;\n if ( a2 )\n {\n v6 = *a1;\n v7 = malloc(v4);\n *v3 = v7;\n *v7 = v6;\n if ( a2 <= 1 )\n {\n v9 = 1;\n }\n else\n {\n v8 = a1 + 1;\n v9 = 1;\n do\n {\n if ( *v8 == v6 )\n {\n *(_DWORD *)(*(_QWORD *)(*v2 + 8LL * *((int *)v2 + 4)) + 4LL * v9++) = v6;\n }\n else\n {\n v10 = *((_DWORD *)v2 + 4);\n *(_DWORD *)(v2[1] + 4LL * v10++) = v9;\n *((_DWORD *)v2 + 4) = v10;\n v6 = *v8;\n v11 = (_QWORD *)(*v2 + 8LL * v10);\n v12 = malloc(v4);\n *v11 = v12;\n *v12 = v6;\n v9 = 1;\n }\n ++v8;\n }\n while ( v8 != &a1[a2 - 2 + 2] );\n }\n v13 = *((_DWORD *)v2 + 4);\n *(_DWORD *)(v2[1] + 4LL * v13) = v9;\n *((_DWORD *)v2 + 4) = v13 + 1;\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11E9(int *a1, int a2) {\n uint64_t *v2;\n uint64_t *v3;\n unsigned int v4;\n int v6;\n uint32_t *v7;\n int *v8;\n int v9;\n int v10;\n uint64_t *v11;\n uint32_t *v12;\n int v13;\n v2 = malloc(24uLL);\n v3 = malloc(8LL * a2);\n *v2 = v3;\n v4 = 4LL * a2;\n v2[1] = malloc(v4);\n *((uint32_t *)v2 + 4) = 0;\n if (a2) {\n v6 = *a1;\n v7 = malloc(v4);\n *v3 = v7;\n *v7 = v6;\n if (a2 <= 1) {\n v9 = 1;\n } else {\n v8 = a1 + 1;\n v9 = 1;\n do {\n if (*v8 == v6) {\n *(uint32_t *)(*(uint64_t *)(*v2 + 8LL * *((int *)v2 + 4)) +\n 4LL * v9++) = v6;\n } else {\n v10 = *((uint32_t *)v2 + 4);\n *(uint32_t *)(v2[1] + 4LL * v10++) = v9;\n *((uint32_t *)v2 + 4) = v10;\n v6 = *v8;\n v11 = (uint64_t *)(*v2 + 8LL * v10);\n v12 = malloc(v4);\n *v11 = v12;\n *v12 = v6;\n v9 = 1;\n }\n ++v8;\n } while (v8 != &a1[a2 - 2 + 2]);\n }\n v13 = *((uint32_t *)v2 + 4);\n *(uint32_t *)(v2[1] + 4LL * v13) = v9;\n *((uint32_t *)v2 + 4) = v13 + 1;\n }\n return v2;\n}", + "ida_pseudo_norm": "uint64_t *func0(int *a1, int a2) {\n uint64_t *v2;\n uint64_t *v3;\n unsigned int v4;\n int v6;\n uint32_t *v7;\n int *v8;\n int v9;\n int v10;\n uint64_t *v11;\n uint32_t *v12;\n int v13;\n v2 = malloc(24uLL);\n v3 = malloc(8LL * a2);\n *v2 = v3;\n v4 = 4LL * a2;\n v2[1] = malloc(v4);\n *((uint32_t *)v2 + 4) = 0;\n if (a2) {\n v6 = *a1;\n v7 = malloc(v4);\n *v3 = v7;\n *v7 = v6;\n if (a2 <= 1) {\n v9 = 1;\n } else {\n v8 = a1 + 1;\n v9 = 1;\n do {\n if (*v8 == v6) {\n *(uint32_t *)(*(uint64_t *)(*v2 + 8LL * *((int *)v2 + 4)) +\n 4LL * v9++) = v6;\n } else {\n v10 = *((uint32_t *)v2 + 4);\n *(uint32_t *)(v2[1] + 4LL * v10++) = v9;\n *((uint32_t *)v2 + 4) = v10;\n v6 = *v8;\n v11 = (uint64_t *)(*v2 + 8LL * v10);\n v12 = malloc(v4);\n *v11 = v12;\n *v12 = v6;\n v9 = 1;\n }\n ++v8;\n } while (v8 != &a1[a2 - 2 + 2]);\n }\n v13 = *((uint32_t *)v2 + 4);\n *(uint32_t *)(v2[1] + 4LL * v13) = v9;\n *((uint32_t *)v2 + 4) = v13 + 1;\n }\n return v2;\n}" + }, + { + "index": 778, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int **group;\n\n int *groupSize;\n\n int numGroups;\n\n} PackResult;\n\n\n\nint compare_arrays(int a[], int b[], int a_size, int b_size) {\n\n if (a_size != b_size)\n\n return 0;\n\n\n\n for (int i = 0; i < a_size; i++) {\n\n if (a[i] != b[i]) {\n\n return 0;\n\n }\n\n }\n\n return 1;\n\n}\n\n\n\n", + "func": "PackResult* func0(int list1[], int size) {\n PackResult* result = malloc(sizeof(PackResult));\n result->group = malloc(sizeof(int*) * size);\n result->groupSize = malloc(sizeof(int) * size);\n result->numGroups = 0;\n if (size == 0) {\n return result;\n }\n int current_value = list1[0];\n int group_count = 0;\n result->group[result->numGroups] = malloc(sizeof(int) * size);\n result->group[result->numGroups][group_count++] = current_value;\n for (int i = 1; i < size; i++) {\n if (list1[i] == current_value) {\n result->group[result->numGroups][group_count++] = list1[i];\n } else {\n result->groupSize[result->numGroups] = group_count;\n result->numGroups++;\n current_value = list1[i];\n result->group[result->numGroups] = malloc(sizeof(int) * size);\n group_count = 0;\n result->group[result->numGroups][group_count++] = current_value;\n }\n }\n result->groupSize[result->numGroups] = group_count;\n result->numGroups++;\n return result;\n}", + "test": "int main() {\n\n // Test Case 1\n\n int input1[] = {0, 0, 1, 2, 3, 4, 4, 5, 6, 6, 6, 7, 8, 9, 4, 4};\n\n int size1 = sizeof(input1)/sizeof(input1[0]);\n\n PackResult* result1 = func0(input1, size1);\n\n assert(result1->numGroups == 11);\n\n assert(compare_arrays(result1->group[0], (int[]){0, 0}, result1->groupSize[0], 2));\n\n assert(compare_arrays(result1->group[1], (int[]){1}, result1->groupSize[1], 1));\n\n assert(compare_arrays(result1->group[4], (int[]){4, 4}, result1->groupSize[4], 2));\n\n assert(compare_arrays(result1->group[10], (int[]){4, 4}, result1->groupSize[10], 2));\n\n\n\n // Test Case 2\n\n int input2[] = {10, 10, 15, 19, 18, 18, 17, 26, 26, 17, 18, 10};\n\n int size2 = sizeof(input2)/sizeof(input2[0]);\n\n PackResult* result2 = func0(input2, size2);\n\n assert(result2->numGroups == 9);\n\n assert(compare_arrays(result2->group[0], (int[]){10, 10}, result2->groupSize[0], 2));\n\n assert(compare_arrays(result2->group[5], (int[]){26, 26}, result2->groupSize[5], 2));\n\n\n\n // Cleaning up memory\n\n for (int i = 0; i < result1->numGroups; i++) {\n\n free(result1->group[i]);\n\n }\n\n free(result1->group);\n\n free(result1->groupSize);\n\n free(result1);\n\n\n\n for (int i = 0; i < result2->numGroups; i++) {\n\n free(result2->group[i]);\n\n }\n\n free(result2->group);\n\n free(result2->groupSize);\n\n free(result2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\nmovslq %esi,%r14\npush %r13\npush %r12\nmov %rdi,%r12\nmov $0x18,%edi\npush %rbp\nmov %r14,%rbp\npush %rbx\nsub $0x28,%rsp\ncallq 10b0 \nlea 0x0(,%r14,8),%rdi\nshl $0x2,%r14\nmov %rax,%r15\ncallq 10b0 \nmov %r14,%rdi\nmov %rax,(%r15)\nmov %rax,%r13\ncallq 10b0 \nmovl $0x0,0x10(%r15)\nmov %rax,0x8(%r15)\nmov %rax,0x8(%rsp)\ntest %ebp,%ebp\njne 1650 \nadd $0x28,%rsp\nmov %r15,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nxchg %ax,%ax\nmov (%r12),%esi\nmov %r14,%rdi\nmov %esi,0x10(%rsp)\ncallq 10b0 \nmov 0x10(%rsp),%esi\ncmp $0x1,%ebp\nmov 0x8(%rsp),%rcx\nmov %rax,0x0(%r13)\nmov %esi,(%rax)\njle 1720 \nlea -0x2(%rbp),%eax\nlea 0x4(%r12),%rbx\nxor %ebp,%ebp\nxor %edx,%edx\nlea 0x8(%r12,%rax,4),%rax\nmov %rax,0x8(%rsp)\nmov $0x1,%eax\njmp 16b8 \nnopl (%rax)\nmov 0x0(%r13,%rdx,8),%rdx\nmovslq %eax,%rdi\nadd $0x4,%rbx\nadd $0x1,%eax\nmov %esi,(%rdx,%rdi,4)\nmovslq 0x10(%r15),%rdx\nmov %rdx,%rbp\ncmp 0x8(%rsp),%rbx\nje 1704 \nmov (%rbx),%r12d\ncmp %esi,%r12d\nje 1698 \nmov %eax,(%rcx,%rdx,4)\nadd $0x1,%ebp\nmov %r14,%rdi\nadd $0x4,%rbx\nmovslq %ebp,%rdx\nmov %rcx,0x18(%rsp)\nmov %rdx,0x10(%rsp)\nmov %ebp,0x10(%r15)\ncallq 10b0 \nmov 0x10(%rsp),%rdx\nmov 0x18(%rsp),%rcx\nmov %r12d,%esi\nmov %r12d,(%rax)\nmov %rax,0x0(%r13,%rdx,8)\nmov $0x1,%eax\ncmp 0x8(%rsp),%rbx\njne 16b8 \nlea (%rcx,%rdx,4),%rcx\nadd $0x1,%ebp\nmov %eax,(%rcx)\nmov %ebp,0x10(%r15)\njmpq 163c \nnopw %cs:0x0(%rax,%rax,1)\nmov $0x1,%ebp\nmov $0x1,%eax\njmp 170b \nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov r15, rdi\nmov edi, 18h; size\npush r14\npush r13\nmovsxd r13, esi\npush r12\nmov r14, r13\npush rbp\nlea rbp, ds:0[r13*4]\npush rbx\nsub rsp, 28h\ncall _malloc\nlea rdi, ds:0[r13*8]; size\nmov r12, rax\ncall _malloc\nmov rdi, rbp; size\nmov [rsp+58h+size], rbp\nmov [r12], rax\nmov [rsp+58h+var_50], rax\ncall _malloc\nmov dword ptr [r12+10h], 0\nmov [r12+8], rax\ntest r13d, r13d\njnz short loc_15F0\nloc_15D6:\nadd rsp, 28h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15F0:\nmov rdi, rbp; size\nmov ebx, [r15]\nmov r13, rax\ncall _malloc\nmov rcx, [rsp+58h+var_50]\nmov [rax], ebx\nmov [rcx], rax\ncmp r14d, 1\njle loc_16B0\nlea eax, [r14-2]\nlea rbp, [r15+4]\nxor r14d, r14d\nlea rax, [r15+rax*4+8]\nxor r15d, r15d\nmov [rsp+58h+var_50], rax\nmov eax, 1\njmp short loc_1651\nloc_1638:\nmov rdi, [rcx+r14*8]\nmovsxd r8, eax\nadd rbp, 4\nadd eax, 1\nmov [rdi+r8*4], ebx\ncmp [rsp+58h+var_50], rbp\njz short loc_1695\nloc_1651:\nmov edi, ebx\nmov ebx, [rbp+0]\ncmp ebx, edi\njz short loc_1638\nadd r15d, 1\nmov [r13+r14*4+0], eax\nmov rdi, [rsp+58h+size]; size\nadd rbp, 4\nmov [r12+10h], r15d\nmovsxd r14, r15d\nmov [rsp+58h+var_48], rcx\ncall _malloc\nmov rcx, [rsp+58h+var_48]\nmov [rax], ebx\nmov [rcx+r14*8], rax\nmov eax, 1\ncmp [rsp+58h+var_50], rbp\njnz short loc_1651\nloc_1695:\nlea r13, [r13+r14*4+0]\nadd r15d, 1\nloc_169E:\nmov [r13+0], eax\nmov [r12+10h], r15d\njmp loc_15D6\nloc_16B0:\nmov r15d, 1\nmov eax, 1\njmp short loc_169E", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2)\n{\n _DWORD *v2; // r12\n _QWORD *v3; // rax\n int *v4; // rax\n int v6; // ebx\n int *v7; // r13\n _DWORD *v8; // rax\n _QWORD *v9; // rcx\n int *v10; // rbp\n __int64 v11; // r14\n int v12; // r15d\n int v13; // eax\n __int64 v14; // r8\n int v15; // edi\n _DWORD *v16; // rax\n int v17; // r15d\n _QWORD *v18; // [rsp+8h] [rbp-50h]\n __int64 v19; // [rsp+8h] [rbp-50h]\n _QWORD *v20; // [rsp+10h] [rbp-48h]\n\n v2 = malloc(0x18uLL);\n v3 = malloc(8LL * a2);\n *(_QWORD *)v2 = v3;\n v18 = v3;\n v4 = (int *)malloc(4LL * a2);\n v2[4] = 0;\n *((_QWORD *)v2 + 1) = v4;\n if ( a2 )\n {\n v6 = *a1;\n v7 = v4;\n v8 = malloc(4LL * a2);\n v9 = v18;\n *v8 = v6;\n *v18 = v8;\n if ( a2 <= 1 )\n {\n v17 = 1;\n v13 = 1;\n }\n else\n {\n v10 = a1 + 1;\n v11 = 0LL;\n v12 = 0;\n v19 = (__int64)&a1[a2 - 2 + 2];\n v13 = 1;\n do\n {\n while ( 1 )\n {\n v15 = v6;\n v6 = *v10;\n if ( *v10 != v15 )\n break;\n v14 = v13;\n ++v10;\n ++v13;\n *(_DWORD *)(v9[v11] + 4 * v14) = v6;\n if ( (int *)v19 == v10 )\n goto LABEL_8;\n }\n ++v12;\n v7[v11] = v13;\n ++v10;\n v2[4] = v12;\n v11 = v12;\n v20 = v9;\n v16 = malloc(4LL * a2);\n v9 = v20;\n *v16 = v6;\n v20[v12] = v16;\n v13 = 1;\n }\n while ( (int *)v19 != v10 );\nLABEL_8:\n v7 += v11;\n v17 = v12 + 1;\n }\n *v7 = v13;\n v2[4] = v17;\n }\n return v2;\n}", + "ida_strip_asm": "sub_1570:\nendbr64\npush r15\nmov r15, rdi\nmov edi, 18h; size\npush r14\npush r13\nmovsxd r13, esi\npush r12\nmov r14, r13\npush rbp\nlea rbp, ds:0[r13*4]\npush rbx\nsub rsp, 28h\ncall _malloc\nlea rdi, ds:0[r13*8]; size\nmov r12, rax\ncall _malloc\nmov rdi, rbp; size\nmov [rsp+58h+size], rbp\nmov [r12], rax\nmov [rsp+58h+var_50], rax\ncall _malloc\nmov dword ptr [r12+10h], 0\nmov [r12+8], rax\ntest r13d, r13d\njnz short loc_15F0\nloc_15D6:\nadd rsp, 28h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15F0:\nmov rdi, rbp; size\nmov ebx, [r15]\nmov r13, rax\ncall _malloc\nmov rcx, [rsp+58h+var_50]\nmov [rax], ebx\nmov [rcx], rax\ncmp r14d, 1\njle loc_16B0\nlea eax, [r14-2]\nlea rbp, [r15+4]\nxor r14d, r14d\nlea rax, [r15+rax*4+8]\nxor r15d, r15d\nmov [rsp+58h+var_50], rax\nmov eax, 1\njmp short loc_1651\nloc_1638:\nmov rdi, [rcx+r14*8]\nmovsxd r8, eax\nadd rbp, 4\nadd eax, 1\nmov [rdi+r8*4], ebx\ncmp [rsp+58h+var_50], rbp\njz short loc_1695\nloc_1651:\nmov edi, ebx\nmov ebx, [rbp+0]\ncmp ebx, edi\njz short loc_1638\nadd r15d, 1\nmov [r13+r14*4+0], eax\nmov rdi, [rsp+58h+size]; size\nadd rbp, 4\nmov [r12+10h], r15d\nmovsxd r14, r15d\nmov [rsp+58h+var_48], rcx\ncall _malloc\nmov rcx, [rsp+58h+var_48]\nmov [rax], ebx\nmov [rcx+r14*8], rax\nmov eax, 1\ncmp [rsp+58h+var_50], rbp\njnz short loc_1651\nloc_1695:\nlea r13, [r13+r14*4+0]\nadd r15d, 1\nloc_169E:\nmov [r13+0], eax\nmov [r12+10h], r15d\njmp loc_15D6\nloc_16B0:\nmov r15d, 1\nmov eax, 1\njmp short loc_169E", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1570(int *a1, int a2)\n{\n _DWORD *v2; // r12\n _QWORD *v3; // rax\n int *v4; // rax\n int v6; // ebx\n int *v7; // r13\n _DWORD *v8; // rax\n _QWORD *v9; // rcx\n int *v10; // rbp\n __int64 v11; // r14\n int v12; // r15d\n int v13; // eax\n __int64 v14; // r8\n int v15; // edi\n _DWORD *v16; // rax\n int v17; // r15d\n _QWORD *v18; // [rsp+8h] [rbp-50h]\n __int64 v19; // [rsp+8h] [rbp-50h]\n _QWORD *v20; // [rsp+10h] [rbp-48h]\n\n v2 = malloc(0x18uLL);\n v3 = malloc(8LL * a2);\n *(_QWORD *)v2 = v3;\n v18 = v3;\n v4 = (int *)malloc(4LL * a2);\n v2[4] = 0;\n *((_QWORD *)v2 + 1) = v4;\n if ( a2 )\n {\n v6 = *a1;\n v7 = v4;\n v8 = malloc(4LL * a2);\n v9 = v18;\n *v8 = v6;\n *v18 = v8;\n if ( a2 <= 1 )\n {\n v17 = 1;\n v13 = 1;\n }\n else\n {\n v10 = a1 + 1;\n v11 = 0LL;\n v12 = 0;\n v19 = (__int64)&a1[a2 - 2 + 2];\n v13 = 1;\n do\n {\n while ( 1 )\n {\n v15 = v6;\n v6 = *v10;\n if ( *v10 != v15 )\n break;\n v14 = v13;\n ++v10;\n ++v13;\n *(_DWORD *)(v9[v11] + 4 * v14) = v6;\n if ( (int *)v19 == v10 )\n goto LABEL_8;\n }\n ++v12;\n v7[v11] = v13;\n ++v10;\n v2[4] = v12;\n v11 = v12;\n v20 = v9;\n v16 = malloc(4LL * a2);\n v9 = v20;\n *v16 = v6;\n v20[v12] = v16;\n v13 = 1;\n }\n while ( (int *)v19 != v10 );\nLABEL_8:\n v7 += v11;\n v17 = v12 + 1;\n }\n *v7 = v13;\n v2[4] = v17;\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1570(int *a1, int a2) {\n uint32_t *v2;\n uint64_t *v3;\n int *v4;\n int v6;\n int *v7;\n uint32_t *v8;\n uint64_t *v9;\n int *v10;\n long long v11;\n int v12;\n int v13;\n long long v14;\n int v15;\n uint32_t *v16;\n int v17;\n uint64_t *v18;\n long long v19;\n uint64_t *v20;\n v2 = malloc(24uLL);\n v3 = malloc(8LL * a2);\n *(uint64_t *)v2 = v3;\n v18 = v3;\n v4 = (int *)malloc(4LL * a2);\n v2[4] = 0;\n *((uint64_t *)v2 + 1) = v4;\n if (a2) {\n v6 = *a1;\n v7 = v4;\n v8 = malloc(4LL * a2);\n v9 = v18;\n *v8 = v6;\n *v18 = v8;\n if (a2 <= 1) {\n v17 = 1;\n v13 = 1;\n } else {\n v10 = a1 + 1;\n v11 = 0LL;\n v12 = 0;\n v19 = (long long)&a1[a2 - 2 + 2];\n v13 = 1;\n do {\n while (1) {\n v15 = v6;\n v6 = *v10;\n if (*v10 != v15) break;\n v14 = v13;\n ++v10;\n ++v13;\n *(uint32_t *)(v9[v11] + 4 * v14) = v6;\n if ((int *)v19 == v10) goto LABEL_8;\n }\n ++v12;\n v7[v11] = v13;\n ++v10;\n v2[4] = v12;\n v11 = v12;\n v20 = v9;\n v16 = malloc(4LL * a2);\n v9 = v20;\n *v16 = v6;\n v20[v12] = v16;\n v13 = 1;\n } while ((int *)v19 != v10);\n LABEL_8:\n v7 += v11;\n v17 = v12 + 1;\n }\n *v7 = v13;\n v2[4] = v17;\n }\n return v2;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2) {\n uint32_t *v2;\n uint64_t *v3;\n int *v4;\n int v6;\n int *v7;\n uint32_t *v8;\n uint64_t *v9;\n int *v10;\n long long v11;\n int v12;\n int v13;\n long long v14;\n int v15;\n uint32_t *v16;\n int v17;\n uint64_t *v18;\n long long v19;\n uint64_t *v20;\n v2 = malloc(24uLL);\n v3 = malloc(8LL * a2);\n *(uint64_t *)v2 = v3;\n v18 = v3;\n v4 = (int *)malloc(4LL * a2);\n v2[4] = 0;\n *((uint64_t *)v2 + 1) = v4;\n if (a2) {\n v6 = *a1;\n v7 = v4;\n v8 = malloc(4LL * a2);\n v9 = v18;\n *v8 = v6;\n *v18 = v8;\n if (a2 <= 1) {\n v17 = 1;\n v13 = 1;\n } else {\n v10 = a1 + 1;\n v11 = 0LL;\n v12 = 0;\n v19 = (long long)&a1[a2 - 2 + 2];\n v13 = 1;\n do {\n while (1) {\n v15 = v6;\n v6 = *v10;\n if (*v10 != v15) break;\n v14 = v13;\n ++v10;\n ++v13;\n *(uint32_t *)(v9[v11] + 4 * v14) = v6;\n if ((int *)v19 == v10) goto LABEL_8;\n }\n ++v12;\n v7[v11] = v13;\n ++v10;\n v2[4] = v12;\n v11 = v12;\n v20 = v9;\n v16 = malloc(4LL * a2);\n v9 = v20;\n *v16 = v6;\n v20[v12] = v16;\n v13 = 1;\n } while ((int *)v19 != v10);\n LABEL_8:\n v7 += v11;\n v17 = v12 + 1;\n }\n *v7 = v13;\n v2[4] = v17;\n }\n return v2;\n}" + }, + { + "index": 778, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int **group;\n\n int *groupSize;\n\n int numGroups;\n\n} PackResult;\n\n\n\nint compare_arrays(int a[], int b[], int a_size, int b_size) {\n\n if (a_size != b_size)\n\n return 0;\n\n\n\n for (int i = 0; i < a_size; i++) {\n\n if (a[i] != b[i]) {\n\n return 0;\n\n }\n\n }\n\n return 1;\n\n}\n\n\n\n", + "func": "PackResult* func0(int list1[], int size) {\n PackResult* result = malloc(sizeof(PackResult));\n result->group = malloc(sizeof(int*) * size);\n result->groupSize = malloc(sizeof(int) * size);\n result->numGroups = 0;\n if (size == 0) {\n return result;\n }\n int current_value = list1[0];\n int group_count = 0;\n result->group[result->numGroups] = malloc(sizeof(int) * size);\n result->group[result->numGroups][group_count++] = current_value;\n for (int i = 1; i < size; i++) {\n if (list1[i] == current_value) {\n result->group[result->numGroups][group_count++] = list1[i];\n } else {\n result->groupSize[result->numGroups] = group_count;\n result->numGroups++;\n current_value = list1[i];\n result->group[result->numGroups] = malloc(sizeof(int) * size);\n group_count = 0;\n result->group[result->numGroups][group_count++] = current_value;\n }\n }\n result->groupSize[result->numGroups] = group_count;\n result->numGroups++;\n return result;\n}", + "test": "int main() {\n\n // Test Case 1\n\n int input1[] = {0, 0, 1, 2, 3, 4, 4, 5, 6, 6, 6, 7, 8, 9, 4, 4};\n\n int size1 = sizeof(input1)/sizeof(input1[0]);\n\n PackResult* result1 = func0(input1, size1);\n\n assert(result1->numGroups == 11);\n\n assert(compare_arrays(result1->group[0], (int[]){0, 0}, result1->groupSize[0], 2));\n\n assert(compare_arrays(result1->group[1], (int[]){1}, result1->groupSize[1], 1));\n\n assert(compare_arrays(result1->group[4], (int[]){4, 4}, result1->groupSize[4], 2));\n\n assert(compare_arrays(result1->group[10], (int[]){4, 4}, result1->groupSize[10], 2));\n\n\n\n // Test Case 2\n\n int input2[] = {10, 10, 15, 19, 18, 18, 17, 26, 26, 17, 18, 10};\n\n int size2 = sizeof(input2)/sizeof(input2[0]);\n\n PackResult* result2 = func0(input2, size2);\n\n assert(result2->numGroups == 9);\n\n assert(compare_arrays(result2->group[0], (int[]){10, 10}, result2->groupSize[0], 2));\n\n assert(compare_arrays(result2->group[5], (int[]){26, 26}, result2->groupSize[5], 2));\n\n\n\n // Cleaning up memory\n\n for (int i = 0; i < result1->numGroups; i++) {\n\n free(result1->group[i]);\n\n }\n\n free(result1->group);\n\n free(result1->groupSize);\n\n free(result1);\n\n\n\n for (int i = 0; i < result2->numGroups; i++) {\n\n free(result2->group[i]);\n\n }\n\n free(result2->group);\n\n free(result2->groupSize);\n\n free(result2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\nmov %rdi,%r14\nmov $0x18,%edi\npush %r13\npush %r12\nmovslq %esi,%r12\npush %rbp\nmov %r12,%r13\npush %rbx\nsub $0x28,%rsp\ncallq 10b0 \nlea 0x0(,%r12,8),%rdi\nshl $0x2,%r12\nmov %rax,%rbp\ncallq 10b0 \nmov %r12,%rdi\nmov %rax,0x8(%rsp)\nmov %rax,%rbx\nmov %rax,0x0(%rbp)\ncallq 10b0 \nmovl $0x0,0x10(%rbp)\nmov %rax,0x8(%rbp)\nmov %rax,0x10(%rsp)\ntest %r13d,%r13d\njne 1608 \nadd $0x28,%rsp\nmov %rbp,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\nmov (%r14),%ecx\nmov %r12,%rdi\nmov %ecx,0x18(%rsp)\ncallq 10b0 \nmov 0x18(%rsp),%ecx\ncmp $0x1,%r13d\nmov 0x10(%rsp),%rdx\nmov %rax,(%rbx)\nmov %ecx,(%rax)\njle 16e0 \nlea -0x2(%r13),%eax\nlea 0x4(%r14),%rbx\nxor %r13d,%r13d\nlea 0x8(%r14,%rax,4),%rax\nxor %r14d,%r14d\nmov %rax,0x10(%rsp)\nmov $0x1,%eax\njmp 1674 \nxchg %ax,%ax\nmov 0x8(%rsp),%rsi\nlea 0x1(%rax),%edi\nadd $0x4,%rbx\nmov (%rsi,%r13,8),%rsi\nmov %ecx,(%rsi,%rax,4)\nmovslq 0x10(%rbp),%r13\nmov %r13,%r14\ncmp 0x10(%rsp),%rbx\nje 16c5 \nmovslq %edi,%rax\nmov (%rbx),%r15d\ncmp %ecx,%r15d\nje 1650 \nmov %eax,(%rdx,%r13,4)\nadd $0x1,%r14d\nmov %r12,%rdi\nadd $0x4,%rbx\nmov %rdx,0x18(%rsp)\nmovslq %r14d,%r13\nmov %r14d,0x10(%rbp)\ncallq 10b0 \nmov 0x8(%rsp),%rcx\ncmp %rbx,0x10(%rsp)\nmov %r15d,(%rax)\nmov 0x18(%rsp),%rdx\nmov %rax,(%rcx,%r13,8)\nje 16c0 \nmov %r15d,%ecx\nmov $0x1,%edi\njmp 1671 \nxchg %ax,%ax\nmov $0x1,%edi\nlea (%rdx,%r13,4),%rdx\nadd $0x1,%r14d\nmov %edi,(%rdx)\nmov %r14d,0x10(%rbp)\njmpq 15f2 \nnopl 0x0(%rax,%rax,1)\nmov $0x1,%r14d\nmov $0x1,%edi\njmp 16cd \nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov r15, rdi\nmov edi, 18h; size\npush r14\npush r13\nmovsxd r13, esi\npush r12\nmov r14, r13\npush rbp\nlea rbp, ds:0[r13*4]\npush rbx\nsub rsp, 28h\ncall _malloc\nlea rdi, ds:0[r13*8]; size\nmov r12, rax\ncall _malloc\nmov rdi, rbp; size\nmov [rsp+58h+size], rbp\nmov [r12], rax\nmov [rsp+58h+var_50], rax\ncall _malloc\nmov dword ptr [r12+10h], 0\nmov [r12+8], rax\ntest r13d, r13d\njnz short loc_15F0\nloc_15D6:\nadd rsp, 28h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15F0:\nmov rdi, rbp; size\nmov ebx, [r15]\nmov r13, rax\ncall _malloc\nmov rcx, [rsp+58h+var_50]\nmov [rax], ebx\nmov [rcx], rax\ncmp r14d, 1\njle loc_16B0\nlea eax, [r14-2]\nlea rbp, [r15+4]\nxor r14d, r14d\nlea rax, [r15+rax*4+8]\nxor r15d, r15d\nmov [rsp+58h+var_50], rax\nmov eax, 1\njmp short loc_1651\nloc_1638:\nmov rdi, [rcx+r14*8]\nmovsxd r8, eax\nadd rbp, 4\nadd eax, 1\nmov [rdi+r8*4], ebx\ncmp [rsp+58h+var_50], rbp\njz short loc_1695\nloc_1651:\nmov edi, ebx\nmov ebx, [rbp+0]\ncmp ebx, edi\njz short loc_1638\nadd r15d, 1\nmov [r13+r14*4+0], eax\nmov rdi, [rsp+58h+size]; size\nadd rbp, 4\nmov [r12+10h], r15d\nmovsxd r14, r15d\nmov [rsp+58h+var_48], rcx\ncall _malloc\nmov rcx, [rsp+58h+var_48]\nmov [rax], ebx\nmov [rcx+r14*8], rax\nmov eax, 1\ncmp [rsp+58h+var_50], rbp\njnz short loc_1651\nloc_1695:\nlea r13, [r13+r14*4+0]\nadd r15d, 1\nloc_169E:\nmov [r13+0], eax\nmov [r12+10h], r15d\njmp loc_15D6\nloc_16B0:\nmov r15d, 1\nmov eax, 1\njmp short loc_169E", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2)\n{\n _DWORD *v2; // r12\n _QWORD *v3; // rax\n int *v4; // rax\n int v6; // ebx\n int *v7; // r13\n _DWORD *v8; // rax\n _QWORD *v9; // rcx\n int *v10; // rbp\n __int64 v11; // r14\n int v12; // r15d\n int v13; // eax\n __int64 v14; // r8\n int v15; // edi\n _DWORD *v16; // rax\n int v17; // r15d\n _QWORD *v18; // [rsp+8h] [rbp-50h]\n __int64 v19; // [rsp+8h] [rbp-50h]\n _QWORD *v20; // [rsp+10h] [rbp-48h]\n\n v2 = malloc(0x18uLL);\n v3 = malloc(8LL * a2);\n *(_QWORD *)v2 = v3;\n v18 = v3;\n v4 = (int *)malloc(4LL * a2);\n v2[4] = 0;\n *((_QWORD *)v2 + 1) = v4;\n if ( a2 )\n {\n v6 = *a1;\n v7 = v4;\n v8 = malloc(4LL * a2);\n v9 = v18;\n *v8 = v6;\n *v18 = v8;\n if ( a2 <= 1 )\n {\n v17 = 1;\n v13 = 1;\n }\n else\n {\n v10 = a1 + 1;\n v11 = 0LL;\n v12 = 0;\n v19 = (__int64)&a1[a2 - 2 + 2];\n v13 = 1;\n do\n {\n while ( 1 )\n {\n v15 = v6;\n v6 = *v10;\n if ( *v10 != v15 )\n break;\n v14 = v13;\n ++v10;\n ++v13;\n *(_DWORD *)(v9[v11] + 4 * v14) = v6;\n if ( (int *)v19 == v10 )\n goto LABEL_8;\n }\n ++v12;\n v7[v11] = v13;\n ++v10;\n v2[4] = v12;\n v11 = v12;\n v20 = v9;\n v16 = malloc(4LL * a2);\n v9 = v20;\n *v16 = v6;\n v20[v12] = v16;\n v13 = 1;\n }\n while ( (int *)v19 != v10 );\nLABEL_8:\n v7 += v11;\n v17 = v12 + 1;\n }\n *v7 = v13;\n v2[4] = v17;\n }\n return v2;\n}", + "ida_strip_asm": "sub_1570:\nendbr64\npush r15\nmov r15, rdi\nmov edi, 18h; size\npush r14\npush r13\nmovsxd r13, esi\npush r12\nmov r14, r13\npush rbp\nlea rbp, ds:0[r13*4]\npush rbx\nsub rsp, 28h\ncall _malloc\nlea rdi, ds:0[r13*8]; size\nmov r12, rax\ncall _malloc\nmov rdi, rbp; size\nmov [rsp+58h+size], rbp\nmov [r12], rax\nmov [rsp+58h+var_50], rax\ncall _malloc\nmov dword ptr [r12+10h], 0\nmov [r12+8], rax\ntest r13d, r13d\njnz short loc_15F0\nloc_15D6:\nadd rsp, 28h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15F0:\nmov rdi, rbp; size\nmov ebx, [r15]\nmov r13, rax\ncall _malloc\nmov rcx, [rsp+58h+var_50]\nmov [rax], ebx\nmov [rcx], rax\ncmp r14d, 1\njle loc_16B0\nlea eax, [r14-2]\nlea rbp, [r15+4]\nxor r14d, r14d\nlea rax, [r15+rax*4+8]\nxor r15d, r15d\nmov [rsp+58h+var_50], rax\nmov eax, 1\njmp short loc_1651\nloc_1638:\nmov rdi, [rcx+r14*8]\nmovsxd r8, eax\nadd rbp, 4\nadd eax, 1\nmov [rdi+r8*4], ebx\ncmp [rsp+58h+var_50], rbp\njz short loc_1695\nloc_1651:\nmov edi, ebx\nmov ebx, [rbp+0]\ncmp ebx, edi\njz short loc_1638\nadd r15d, 1\nmov [r13+r14*4+0], eax\nmov rdi, [rsp+58h+size]; size\nadd rbp, 4\nmov [r12+10h], r15d\nmovsxd r14, r15d\nmov [rsp+58h+var_48], rcx\ncall _malloc\nmov rcx, [rsp+58h+var_48]\nmov [rax], ebx\nmov [rcx+r14*8], rax\nmov eax, 1\ncmp [rsp+58h+var_50], rbp\njnz short loc_1651\nloc_1695:\nlea r13, [r13+r14*4+0]\nadd r15d, 1\nloc_169E:\nmov [r13+0], eax\nmov [r12+10h], r15d\njmp loc_15D6\nloc_16B0:\nmov r15d, 1\nmov eax, 1\njmp short loc_169E", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1570(int *a1, int a2)\n{\n _DWORD *v2; // r12\n _QWORD *v3; // rax\n int *v4; // rax\n int v6; // ebx\n int *v7; // r13\n _DWORD *v8; // rax\n _QWORD *v9; // rcx\n int *v10; // rbp\n __int64 v11; // r14\n int v12; // r15d\n int v13; // eax\n __int64 v14; // r8\n int v15; // edi\n _DWORD *v16; // rax\n int v17; // r15d\n _QWORD *v18; // [rsp+8h] [rbp-50h]\n __int64 v19; // [rsp+8h] [rbp-50h]\n _QWORD *v20; // [rsp+10h] [rbp-48h]\n\n v2 = malloc(0x18uLL);\n v3 = malloc(8LL * a2);\n *(_QWORD *)v2 = v3;\n v18 = v3;\n v4 = (int *)malloc(4LL * a2);\n v2[4] = 0;\n *((_QWORD *)v2 + 1) = v4;\n if ( a2 )\n {\n v6 = *a1;\n v7 = v4;\n v8 = malloc(4LL * a2);\n v9 = v18;\n *v8 = v6;\n *v18 = v8;\n if ( a2 <= 1 )\n {\n v17 = 1;\n v13 = 1;\n }\n else\n {\n v10 = a1 + 1;\n v11 = 0LL;\n v12 = 0;\n v19 = (__int64)&a1[a2 - 2 + 2];\n v13 = 1;\n do\n {\n while ( 1 )\n {\n v15 = v6;\n v6 = *v10;\n if ( *v10 != v15 )\n break;\n v14 = v13;\n ++v10;\n ++v13;\n *(_DWORD *)(v9[v11] + 4 * v14) = v6;\n if ( (int *)v19 == v10 )\n goto LABEL_8;\n }\n ++v12;\n v7[v11] = v13;\n ++v10;\n v2[4] = v12;\n v11 = v12;\n v20 = v9;\n v16 = malloc(4LL * a2);\n v9 = v20;\n *v16 = v6;\n v20[v12] = v16;\n v13 = 1;\n }\n while ( (int *)v19 != v10 );\nLABEL_8:\n v7 += v11;\n v17 = v12 + 1;\n }\n *v7 = v13;\n v2[4] = v17;\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1570(int *a1, int a2) {\n uint32_t *v2;\n uint64_t *v3;\n int *v4;\n int v6;\n int *v7;\n uint32_t *v8;\n uint64_t *v9;\n int *v10;\n long long v11;\n int v12;\n int v13;\n long long v14;\n int v15;\n uint32_t *v16;\n int v17;\n uint64_t *v18;\n long long v19;\n uint64_t *v20;\n v2 = malloc(24uLL);\n v3 = malloc(8LL * a2);\n *(uint64_t *)v2 = v3;\n v18 = v3;\n v4 = (int *)malloc(4LL * a2);\n v2[4] = 0;\n *((uint64_t *)v2 + 1) = v4;\n if (a2) {\n v6 = *a1;\n v7 = v4;\n v8 = malloc(4LL * a2);\n v9 = v18;\n *v8 = v6;\n *v18 = v8;\n if (a2 <= 1) {\n v17 = 1;\n v13 = 1;\n } else {\n v10 = a1 + 1;\n v11 = 0LL;\n v12 = 0;\n v19 = (long long)&a1[a2 - 2 + 2];\n v13 = 1;\n do {\n while (1) {\n v15 = v6;\n v6 = *v10;\n if (*v10 != v15) break;\n v14 = v13;\n ++v10;\n ++v13;\n *(uint32_t *)(v9[v11] + 4 * v14) = v6;\n if ((int *)v19 == v10) goto LABEL_8;\n }\n ++v12;\n v7[v11] = v13;\n ++v10;\n v2[4] = v12;\n v11 = v12;\n v20 = v9;\n v16 = malloc(4LL * a2);\n v9 = v20;\n *v16 = v6;\n v20[v12] = v16;\n v13 = 1;\n } while ((int *)v19 != v10);\n LABEL_8:\n v7 += v11;\n v17 = v12 + 1;\n }\n *v7 = v13;\n v2[4] = v17;\n }\n return v2;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2) {\n uint32_t *v2;\n uint64_t *v3;\n int *v4;\n int v6;\n int *v7;\n uint32_t *v8;\n uint64_t *v9;\n int *v10;\n long long v11;\n int v12;\n int v13;\n long long v14;\n int v15;\n uint32_t *v16;\n int v17;\n uint64_t *v18;\n long long v19;\n uint64_t *v20;\n v2 = malloc(24uLL);\n v3 = malloc(8LL * a2);\n *(uint64_t *)v2 = v3;\n v18 = v3;\n v4 = (int *)malloc(4LL * a2);\n v2[4] = 0;\n *((uint64_t *)v2 + 1) = v4;\n if (a2) {\n v6 = *a1;\n v7 = v4;\n v8 = malloc(4LL * a2);\n v9 = v18;\n *v8 = v6;\n *v18 = v8;\n if (a2 <= 1) {\n v17 = 1;\n v13 = 1;\n } else {\n v10 = a1 + 1;\n v11 = 0LL;\n v12 = 0;\n v19 = (long long)&a1[a2 - 2 + 2];\n v13 = 1;\n do {\n while (1) {\n v15 = v6;\n v6 = *v10;\n if (*v10 != v15) break;\n v14 = v13;\n ++v10;\n ++v13;\n *(uint32_t *)(v9[v11] + 4 * v14) = v6;\n if ((int *)v19 == v10) goto LABEL_8;\n }\n ++v12;\n v7[v11] = v13;\n ++v10;\n v2[4] = v12;\n v11 = v12;\n v20 = v9;\n v16 = malloc(4LL * a2);\n v9 = v20;\n *v16 = v6;\n v20[v12] = v16;\n v13 = 1;\n } while ((int *)v19 != v10);\n LABEL_8:\n v7 += v11;\n v17 = v12 + 1;\n }\n *v7 = v13;\n v2[4] = v17;\n }\n return v2;\n}" + }, + { + "index": 779, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n// Structure to hold key-value pairs\n\ntypedef struct {\n\n char key[100];\n\n int count;\n\n} DictEntry;\n\n\n\n// Function to convert integer list to string key\n\nvoid int_list_to_key(int *list, int size, char *key) {\n\n strcpy(key, \"(\");\n\n for(int i = 0; i < size; i++) {\n\n char num[20];\n\n sprintf(num, \"%d\", list[i]);\n\n strcat(key, num);\n\n if(i < size - 1)\n\n strcat(key, \", \");\n\n }\n\n strcat(key, \")\");\n\n}\n\n\n\n// Function to convert string list to key\n\nvoid str_list_to_key(char **list, int size, char *key) {\n\n strcpy(key, \"(\");\n\n for(int i = 0; i < size; i++) {\n\n strcat(key, \"'\");\n\n strcat(key, list[i]);\n\n strcat(key, \"'\");\n\n if(i < size - 1)\n\n strcat(key, \", \");\n\n }\n\n strcat(key, \")\");\n\n}\n\n\n\n// Unique sublists for string lists\n\nDictEntry* unique_sublists_str(char ***list1, int *sizes, int n, int *unique_count) {\n\n DictEntry *result = malloc(n * sizeof(DictEntry));\n\n *unique_count = 0;\n\n for(int i = 0; i < n; i++) {\n\n char key[100];\n\n str_list_to_key(list1[i], sizes[i], key);\n\n int found = 0;\n\n for(int j = 0; j < *unique_count; j++) {\n\n if(strcmp(result[j].key, key) == 0) {\n\n result[j].count += 1;\n\n found = 1;\n\n break;\n\n }\n\n }\n\n if(!found) {\n\n strcpy(result[*unique_count].key, key);\n\n result[*unique_count].count = 1;\n\n (*unique_count)++;\n\n }\n\n }\n\n return result;\n\n}\n\n\n\n// Function to compare two DictEntry arrays\n\nint compare_dict(DictEntry *dict1, int count1, DictEntry *dict2, int count2) {\n\n if(count1 != count2)\n\n return 0;\n\n for(int i = 0; i < count1; i++) {\n\n int found = 0;\n\n for(int j = 0; j < count2; j++) {\n\n if(strcmp(dict1[i].key, dict2[j].key) == 0 && dict1[i].count == dict2[j].count) {\n\n found = 1;\n\n break;\n\n }\n\n }\n\n if(!found)\n\n return 0;\n\n }\n\n return 1;\n\n}\n\n\n\n// Unique sublists for integer lists\n\n", + "func": "DictEntry *func0(int **list1, int *sizes, int n, int *unique_count) {\n DictEntry *result = malloc(n * sizeof(DictEntry));\n *unique_count = 0;\n for (int i = 0; i < n; i++) {\n char key[100];\n int_list_to_key(list1[i], sizes[i], key);\n int found = 0;\n for (int j = 0; j < *unique_count; j++) {\n if (strcmp(result[j].key, key) == 0) {\n result[j].count += 1;\n found = 1;\n break;\n }\n }\n if (!found) {\n strcpy(result[*unique_count].key, key);\n result[*unique_count].count = 1;\n (*unique_count)++;\n }\n }\n return result;\n}", + "test": "int main() {\n\n // Test case 1\n\n int list1_case1_data[][3] = { {1, 3}, {5, 7}, {1, 3}, {13, 15, 17}, {5, 7}, {9, 11} };\n\n int sizes_case1[] = {2, 2, 2, 3, 2, 2};\n\n int *list1_case1[6];\n\n for(int i = 0; i < 6; i++) {\n\n list1_case1[i] = list1_case1_data[i];\n\n }\n\n int unique_count1;\n\n DictEntry *result1 = func0(list1_case1, sizes_case1, 6, &unique_count1);\n\n DictEntry expected1[] = { {\"(1, 3)\", 2}, {\"(5, 7)\", 2}, {\"(13, 15, 17)\", 1}, {\"(9, 11)\", 1} };\n\n assert(compare_dict(result1, unique_count1, expected1, 4));\n\n free(result1);\n\n\n\n // Test case 2\n\n char *list1_case2_data[][2] = { {\"green\", \"orange\"}, {\"black\"}, {\"green\", \"orange\"}, {\"white\"} };\n\n int sizes_case2[] = {2, 1, 2, 1};\n\n char **list1_case2[4];\n\n for(int i = 0; i < 4; i++) {\n\n list1_case2[i] = list1_case2_data[i];\n\n }\n\n int unique_count2;\n\n DictEntry *result2 = unique_sublists_str(list1_case2, sizes_case2, 4, &unique_count2);\n\n DictEntry expected2[] = { {\"('green', 'orange')\", 2}, {\"('black')\", 1}, {\"('white')\", 1} };\n\n assert(compare_dict(result2, unique_count2, expected2, 3));\n\n free(result2);\n\n\n\n // Test case 3\n\n int list1_case3_data[][2] = { {1, 2}, {3, 4}, {4, 5}, {6, 7} };\n\n int sizes_case3[] = {2, 2, 2, 2};\n\n int *list1_case3[4];\n\n for(int i = 0; i < 4; i++) {\n\n list1_case3[i] = list1_case3_data[i];\n\n }\n\n int unique_count3;\n\n DictEntry *result3 = func0(list1_case3, sizes_case3, 4, &unique_count3);\n\n DictEntry expected3[] = { {\"(1, 2)\", 1}, {\"(3, 4)\", 1}, {\"(4, 5)\", 1}, {\"(6, 7)\", 1} };\n\n assert(compare_dict(result3, unique_count3, expected3, 4));\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0xb0,%rsp\nmov %rdi,-0x98(%rbp)\nmov %rsi,-0xa0(%rbp)\nmov %edx,-0xa4(%rbp)\nmov %rcx,-0xb0(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmov -0xa4(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 1110 \nmov %rax,-0x78(%rbp)\nmov -0xb0(%rbp),%rax\nmovl $0x0,(%rax)\nmovl $0x0,-0x84(%rbp)\njmpq 19ed \nmov -0x84(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0xa0(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%ecx\nmov -0x84(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x98(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nlea -0x70(%rbp),%rdx\nmov %ecx,%esi\nmov %rax,%rdi\ncallq 1229 \nmovl $0x0,-0x80(%rbp)\nmovl $0x0,-0x7c(%rbp)\njmpq 1948 \nmov -0x7c(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nmov -0x78(%rbp),%rax\nadd %rdx,%rax\nmov %rax,%rdx\nlea -0x70(%rbp),%rax\nmov %rax,%rsi\nmov %rdx,%rdi\ncallq 1100 \ntest %eax,%eax\njne 1944 \nmov -0x7c(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nmov -0x78(%rbp),%rax\nadd %rdx,%rax\nmov 0x64(%rax),%ecx\nmov -0x7c(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nmov -0x78(%rbp),%rax\nadd %rdx,%rax\nlea 0x1(%rcx),%edx\nmov %edx,0x64(%rax)\nmovl $0x1,-0x80(%rbp)\njmp 195a \naddl $0x1,-0x7c(%rbp)\nmov -0xb0(%rbp),%rax\nmov (%rax),%eax\ncmp %eax,-0x7c(%rbp)\njl 18b0 \ncmpl $0x0,-0x80(%rbp)\njne 19e6 \nmov -0xb0(%rbp),%rax\nmov (%rax),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nmov -0x78(%rbp),%rax\nadd %rdx,%rax\nmov %rax,%rdx\nlea -0x70(%rbp),%rax\nmov %rax,%rsi\nmov %rdx,%rdi\ncallq 10d0 \nmov -0xb0(%rbp),%rax\nmov (%rax),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nshl $0x3,%rax\nmov %rax,%rdx\nmov -0x78(%rbp),%rax\nadd %rdx,%rax\nmovl $0x1,0x64(%rax)\nmov -0xb0(%rbp),%rax\nmov (%rax),%eax\nlea 0x1(%rax),%edx\nmov -0xb0(%rbp),%rax\nmov %edx,(%rax)\naddl $0x1,-0x84(%rbp)\nmov -0x84(%rbp),%eax\ncmp -0xa4(%rbp),%eax\njl 1856 \nmov -0x78(%rbp),%rax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 1a17 \ncallq 10e0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0B0h\nmov [rbp+var_98], rdi\nmov [rbp+var_A0], rsi\nmov [rbp+var_A4], edx\nmov [rbp+var_B0], rcx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov eax, [rbp+var_A4]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_78], rax\nmov rax, [rbp+var_B0]\nmov dword ptr [rax], 0\nmov [rbp+var_84], 0\njmp loc_1997\nloc_1800:\nmov eax, [rbp+var_84]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_A0]\nadd rax, rdx\nmov ecx, [rax]\nmov eax, [rbp+var_84]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_98]\nadd rax, rdx\nmov rax, [rax]\nlea rdx, [rbp+s2]\nmov esi, ecx\nmov rdi, rax\ncall int_list_to_key\nmov [rbp+var_80], 0\nmov [rbp+var_7C], 0\njmp loc_18F2\nloc_185A:\nmov eax, [rbp+var_7C]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_78]\nadd rax, rdx\nmov rdx, rax\nlea rax, [rbp+s2]\nmov rsi, rax; s2\nmov rdi, rdx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_18EE\nmov eax, [rbp+var_7C]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_78]\nadd rax, rdx\nmov ecx, [rax+64h]\nmov eax, [rbp+var_7C]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_78]\nadd rax, rdx\nlea edx, [rcx+1]\nmov [rax+64h], edx\nmov [rbp+var_80], 1\njmp short loc_1904\nloc_18EE:\nadd [rbp+var_7C], 1\nloc_18F2:\nmov rax, [rbp+var_B0]\nmov eax, [rax]\ncmp [rbp+var_7C], eax\njl loc_185A\nloc_1904:\ncmp [rbp+var_80], 0\njnz loc_1990\nmov rax, [rbp+var_B0]\nmov eax, [rax]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_78]\nadd rax, rdx\nmov rdx, rax\nlea rax, [rbp+s2]\nmov rsi, rax; src\nmov rdi, rdx; dest\ncall _strcpy\nmov rax, [rbp+var_B0]\nmov eax, [rax]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_78]\nadd rax, rdx\nmov dword ptr [rax+64h], 1\nmov rax, [rbp+var_B0]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_B0]\nmov [rax], edx\nloc_1990:\nadd [rbp+var_84], 1\nloc_1997:\nmov eax, [rbp+var_84]\ncmp eax, [rbp+var_A4]\njl loc_1800\nmov rax, [rbp+var_78]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_19C1\ncall ___stack_chk_fail\nlocret_19C1:\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, __int64 a2, int a3, int *a4)\n{\n int i; // [rsp+2Ch] [rbp-84h]\n int v8; // [rsp+30h] [rbp-80h]\n int j; // [rsp+34h] [rbp-7Ch]\n _DWORD *v10; // [rsp+38h] [rbp-78h]\n char s2[104]; // [rsp+40h] [rbp-70h] BYREF\n unsigned __int64 v12; // [rsp+A8h] [rbp-8h]\n\n v12 = __readfsqword(0x28u);\n v10 = malloc(104LL * a3);\n *a4 = 0;\n for ( i = 0; i < a3; ++i )\n {\n int_list_to_key(*(_QWORD *)(8LL * i + a1), *(unsigned int *)(4LL * i + a2), s2);\n v8 = 0;\n for ( j = 0; j < *a4; ++j )\n {\n if ( !strcmp((const char *)&v10[26 * j], s2) )\n {\n ++v10[26 * j + 25];\n v8 = 1;\n break;\n }\n }\n if ( !v8 )\n {\n strcpy((char *)&v10[26 * *a4], s2);\n v10[26 * (*a4)++ + 25] = 1;\n }\n }\n return v10;\n}", + "ida_strip_asm": "sub_1782:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0B0h\nmov [rbp+var_98], rdi\nmov [rbp+var_A0], rsi\nmov [rbp+var_A4], edx\nmov [rbp+var_B0], rcx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov eax, [rbp+var_A4]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_78], rax\nmov rax, [rbp+var_B0]\nmov dword ptr [rax], 0\nmov [rbp+var_84], 0\njmp loc_1997\nloc_1800:\nmov eax, [rbp+var_84]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_A0]\nadd rax, rdx\nmov ecx, [rax]\nmov eax, [rbp+var_84]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_98]\nadd rax, rdx\nmov rax, [rax]\nlea rdx, [rbp+s2]\nmov esi, ecx\nmov rdi, rax\ncall sub_1249\nmov [rbp+var_80], 0\nmov [rbp+var_7C], 0\njmp loc_18F2\nloc_185A:\nmov eax, [rbp+var_7C]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_78]\nadd rax, rdx\nmov rdx, rax\nlea rax, [rbp+s2]\nmov rsi, rax; s2\nmov rdi, rdx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_18EE\nmov eax, [rbp+var_7C]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_78]\nadd rax, rdx\nmov ecx, [rax+64h]\nmov eax, [rbp+var_7C]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_78]\nadd rax, rdx\nlea edx, [rcx+1]\nmov [rax+64h], edx\nmov [rbp+var_80], 1\njmp short loc_1904\nloc_18EE:\nadd [rbp+var_7C], 1\nloc_18F2:\nmov rax, [rbp+var_B0]\nmov eax, [rax]\ncmp [rbp+var_7C], eax\njl loc_185A\nloc_1904:\ncmp [rbp+var_80], 0\njnz loc_1990\nmov rax, [rbp+var_B0]\nmov eax, [rax]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_78]\nadd rax, rdx\nmov rdx, rax\nlea rax, [rbp+s2]\nmov rsi, rax; src\nmov rdi, rdx; dest\ncall _strcpy\nmov rax, [rbp+var_B0]\nmov eax, [rax]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rdx\nshl rax, 3\nmov rdx, rax\nmov rax, [rbp+var_78]\nadd rax, rdx\nmov dword ptr [rax+64h], 1\nmov rax, [rbp+var_B0]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_B0]\nmov [rax], edx\nloc_1990:\nadd [rbp+var_84], 1\nloc_1997:\nmov eax, [rbp+var_84]\ncmp eax, [rbp+var_A4]\njl loc_1800\nmov rax, [rbp+var_78]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_19C1\ncall ___stack_chk_fail\nlocret_19C1:\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1782(__int64 a1, __int64 a2, int a3, int *a4)\n{\n int i; // [rsp+2Ch] [rbp-84h]\n int v8; // [rsp+30h] [rbp-80h]\n int j; // [rsp+34h] [rbp-7Ch]\n _DWORD *v10; // [rsp+38h] [rbp-78h]\n char s2[104]; // [rsp+40h] [rbp-70h] BYREF\n unsigned __int64 v12; // [rsp+A8h] [rbp-8h]\n\n v12 = __readfsqword(0x28u);\n v10 = malloc(104LL * a3);\n *a4 = 0;\n for ( i = 0; i < a3; ++i )\n {\n sub_1249(*(_QWORD *)(8LL * i + a1), *(unsigned int *)(4LL * i + a2), s2);\n v8 = 0;\n for ( j = 0; j < *a4; ++j )\n {\n if ( !strcmp((const char *)&v10[26 * j], s2) )\n {\n ++v10[26 * j + 25];\n v8 = 1;\n break;\n }\n }\n if ( !v8 )\n {\n strcpy((char *)&v10[26 * *a4], s2);\n v10[26 * (*a4)++ + 25] = 1;\n }\n }\n return v10;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1782(long long a1, long long a2, int a3, int *a4) {\n int i;\n int v8;\n int j;\n uint32_t *v10;\n char s2[104];\n unsigned long long v12;\n v12 = __readfsqword(40u);\n v10 = malloc(104LL * a3);\n *a4 = 0;\n for (i = 0; i < a3; ++i) {\n sub_1249(*(uint64_t *)(8LL * i + a1), *(unsigned int *)(4LL * i + a2), s2);\n v8 = 0;\n for (j = 0; j < *a4; ++j) {\n if (!strcmp((const char *)&v10[26 * j], s2)) {\n ++v10[26 * j + 25];\n v8 = 1;\n break;\n }\n }\n if (!v8) {\n strcpy((char *)&v10[26 * *a4], s2);\n v10[26 * (*a4)++ + 25] = 1;\n }\n }\n return v10;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, long long a2, int a3, int *a4) {\n int i;\n int v8;\n int j;\n uint32_t *v10;\n char s2[104];\n unsigned long long v12;\n v12 = __readfsqword(40u);\n v10 = malloc(104LL * a3);\n *a4 = 0;\n for (i = 0; i < a3; ++i) {\n int_list_to_key(*(uint64_t *)(8LL * i + a1),\n *(unsigned int *)(4LL * i + a2), s2);\n v8 = 0;\n for (j = 0; j < *a4; ++j) {\n if (!strcmp((const char *)&v10[26 * j], s2)) {\n ++v10[26 * j + 25];\n v8 = 1;\n break;\n }\n }\n if (!v8) {\n strcpy((char *)&v10[26 * *a4], s2);\n v10[26 * (*a4)++ + 25] = 1;\n }\n }\n return v10;\n}" + }, + { + "index": 779, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n// Structure to hold key-value pairs\n\ntypedef struct {\n\n char key[100];\n\n int count;\n\n} DictEntry;\n\n\n\n// Function to convert integer list to string key\n\nvoid int_list_to_key(int *list, int size, char *key) {\n\n strcpy(key, \"(\");\n\n for(int i = 0; i < size; i++) {\n\n char num[20];\n\n sprintf(num, \"%d\", list[i]);\n\n strcat(key, num);\n\n if(i < size - 1)\n\n strcat(key, \", \");\n\n }\n\n strcat(key, \")\");\n\n}\n\n\n\n// Function to convert string list to key\n\nvoid str_list_to_key(char **list, int size, char *key) {\n\n strcpy(key, \"(\");\n\n for(int i = 0; i < size; i++) {\n\n strcat(key, \"'\");\n\n strcat(key, list[i]);\n\n strcat(key, \"'\");\n\n if(i < size - 1)\n\n strcat(key, \", \");\n\n }\n\n strcat(key, \")\");\n\n}\n\n\n\n// Unique sublists for string lists\n\nDictEntry* unique_sublists_str(char ***list1, int *sizes, int n, int *unique_count) {\n\n DictEntry *result = malloc(n * sizeof(DictEntry));\n\n *unique_count = 0;\n\n for(int i = 0; i < n; i++) {\n\n char key[100];\n\n str_list_to_key(list1[i], sizes[i], key);\n\n int found = 0;\n\n for(int j = 0; j < *unique_count; j++) {\n\n if(strcmp(result[j].key, key) == 0) {\n\n result[j].count += 1;\n\n found = 1;\n\n break;\n\n }\n\n }\n\n if(!found) {\n\n strcpy(result[*unique_count].key, key);\n\n result[*unique_count].count = 1;\n\n (*unique_count)++;\n\n }\n\n }\n\n return result;\n\n}\n\n\n\n// Function to compare two DictEntry arrays\n\nint compare_dict(DictEntry *dict1, int count1, DictEntry *dict2, int count2) {\n\n if(count1 != count2)\n\n return 0;\n\n for(int i = 0; i < count1; i++) {\n\n int found = 0;\n\n for(int j = 0; j < count2; j++) {\n\n if(strcmp(dict1[i].key, dict2[j].key) == 0 && dict1[i].count == dict2[j].count) {\n\n found = 1;\n\n break;\n\n }\n\n }\n\n if(!found)\n\n return 0;\n\n }\n\n return 1;\n\n}\n\n\n\n// Unique sublists for integer lists\n\n", + "func": "DictEntry *func0(int **list1, int *sizes, int n, int *unique_count) {\n DictEntry *result = malloc(n * sizeof(DictEntry));\n *unique_count = 0;\n for (int i = 0; i < n; i++) {\n char key[100];\n int_list_to_key(list1[i], sizes[i], key);\n int found = 0;\n for (int j = 0; j < *unique_count; j++) {\n if (strcmp(result[j].key, key) == 0) {\n result[j].count += 1;\n found = 1;\n break;\n }\n }\n if (!found) {\n strcpy(result[*unique_count].key, key);\n result[*unique_count].count = 1;\n (*unique_count)++;\n }\n }\n return result;\n}", + "test": "int main() {\n\n // Test case 1\n\n int list1_case1_data[][3] = { {1, 3}, {5, 7}, {1, 3}, {13, 15, 17}, {5, 7}, {9, 11} };\n\n int sizes_case1[] = {2, 2, 2, 3, 2, 2};\n\n int *list1_case1[6];\n\n for(int i = 0; i < 6; i++) {\n\n list1_case1[i] = list1_case1_data[i];\n\n }\n\n int unique_count1;\n\n DictEntry *result1 = func0(list1_case1, sizes_case1, 6, &unique_count1);\n\n DictEntry expected1[] = { {\"(1, 3)\", 2}, {\"(5, 7)\", 2}, {\"(13, 15, 17)\", 1}, {\"(9, 11)\", 1} };\n\n assert(compare_dict(result1, unique_count1, expected1, 4));\n\n free(result1);\n\n\n\n // Test case 2\n\n char *list1_case2_data[][2] = { {\"green\", \"orange\"}, {\"black\"}, {\"green\", \"orange\"}, {\"white\"} };\n\n int sizes_case2[] = {2, 1, 2, 1};\n\n char **list1_case2[4];\n\n for(int i = 0; i < 4; i++) {\n\n list1_case2[i] = list1_case2_data[i];\n\n }\n\n int unique_count2;\n\n DictEntry *result2 = unique_sublists_str(list1_case2, sizes_case2, 4, &unique_count2);\n\n DictEntry expected2[] = { {\"('green', 'orange')\", 2}, {\"('black')\", 1}, {\"('white')\", 1} };\n\n assert(compare_dict(result2, unique_count2, expected2, 3));\n\n free(result2);\n\n\n\n // Test case 3\n\n int list1_case3_data[][2] = { {1, 2}, {3, 4}, {4, 5}, {6, 7} };\n\n int sizes_case3[] = {2, 2, 2, 2};\n\n int *list1_case3[4];\n\n for(int i = 0; i < 4; i++) {\n\n list1_case3[i] = list1_case3_data[i];\n\n }\n\n int unique_count3;\n\n DictEntry *result3 = func0(list1_case3, sizes_case3, 4, &unique_count3);\n\n DictEntry expected3[] = { {\"(1, 2)\", 1}, {\"(3, 4)\", 1}, {\"(4, 5)\", 1}, {\"(6, 7)\", 1} };\n\n assert(compare_dict(result3, unique_count3, expected3, 4));\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0xa8,%rsp\nmov %rdi,0x18(%rsp)\nmov %rsi,0x20(%rsp)\nmov %edx,%ebx\nmov %rcx,%r15\nmov %rcx,0x10(%rsp)\nmov %fs:0x28,%rax\nmov %rax,0x98(%rsp)\nxor %eax,%eax\nmovslq %edx,%rax\nlea (%rax,%rax,2),%rdx\nlea (%rax,%rdx,4),%rdi\nshl $0x3,%rdi\ncallq 1100 \nmov %rax,0x8(%rsp)\nmovl $0x0,(%r15)\ntest %ebx,%ebx\njle 171c \nlea -0x1(%rbx),%eax\nmov %rax,0x28(%rsp)\nmov $0x0,%r15d\nlea 0x30(%rsp),%rbp\njmp 16b8 \naddl $0x1,0x64(%rbx)\njmp 16aa \nmovslq %r14d,%rax\nlea (%rax,%rax,2),%rdx\nlea (%rax,%rdx,4),%rax\nmov 0x8(%rsp),%rcx\nlea (%rcx,%rax,8),%rbx\nmov $0x64,%edx\nmov %rbp,%rsi\nmov %rbx,%rdi\ncallq 1110 <__strcpy_chk@plt>\nmovl $0x1,0x64(%rbx)\nadd $0x1,%r14d\nmov 0x10(%rsp),%rax\nmov %r14d,(%rax)\nlea 0x1(%r15),%rax\ncmp 0x28(%rsp),%r15\nje 171c \nmov %rax,%r15\nmov 0x20(%rsp),%rax\nmov (%rax,%r15,4),%esi\nmov 0x18(%rsp),%rax\nmov (%rax,%r15,8),%rdi\nmov %rbp,%rdx\ncallq 1229 \nmov 0x10(%rsp),%rax\nmov (%rax),%r14d\ntest %r14d,%r14d\njle 1673 \nmov 0x8(%rsp),%rcx\nmov %rcx,%rbx\nlea -0x1(%r14),%eax\nadd $0x1,%rax\nlea (%rax,%rax,2),%rdx\nlea (%rax,%rdx,4),%rax\nlea (%rcx,%rax,8),%r13\nmov %rbp,%rsi\nmov %rbx,%rdi\ncallq 10f0 \ntest %eax,%eax\nje 166d \nadd $0x68,%rbx\ncmp %r13,%rbx\njne 16fb \njmpq 1673 \nmov 0x98(%rsp),%rax\nxor %fs:0x28,%rax\njne 1746 \nmov 0x8(%rsp),%rax\nadd $0xa8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\ncallq 10d0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 98h\nmov r15, rdi\nmov rbp, rsi\nmov r12d, edx\nmov r14, rcx\nmov [rsp+0C8h+var_C0], rcx\nmov rax, fs:28h\nmov [rsp+0C8h+var_40], rax\nxor eax, eax\nmovsxd rbx, edx\nlea rax, [rbx+rbx*2]\nlea rax, [rbx+rax*4]\nshl rax, 3\nmov [rsp+0C8h+var_B0], rax\nmov rdi, rax; size\ncall _malloc\nmov [rsp+0C8h+s1], rax\nmov dword ptr [r14], 0\ntest r12d, r12d\njle loc_16DA\nmov r14, rbp\nlea rax, [rbp+rbx*4+0]\nmov [rsp+0C8h+var_B8], rax\nlea rbp, [rsp+0C8h+s2]\njmp short loc_1688\nloc_161D:\nadd dword ptr [rbx+64h], 1\njmp short loc_1676\nloc_1623:\nmovsxd rax, r13d\nlea rdx, [rax+rax*2]\nlea rax, [rax+rdx*4]\nshl rax, 3\nmov rcx, [rsp+0C8h+s1]\nlea rbx, [rcx+rax]\nmov rcx, [rsp+0C8h+var_B0]\ncmp rcx, rax\nmov rdx, rcx\ncmovb rdx, rax\nsub rdx, rax\nmov eax, 64h ; 'd'\ncmp rdx, rax\ncmova rdx, rax\nmov rsi, rbp\nmov rdi, rbx\ncall ___strcpy_chk\nmov dword ptr [rbx+64h], 1\nadd r13d, 1\nmov rax, [rsp+0C8h+var_C0]\nmov [rax], r13d\nloc_1676:\nadd r14, 4\nadd r15, 8\nmov rax, [rsp+0C8h+var_B8]\ncmp r14, rax\njz short loc_16DA\nloc_1688:\nmov esi, [r14]\nmov rdi, [r15]\nmov rdx, rbp\ncall int_list_to_key\nmov rax, [rsp+0C8h+var_C0]\nmov r13d, [rax]\ntest r13d, r13d\njle short loc_1623\nmov rcx, [rsp+0C8h+s1]\nmov rbx, rcx\nmovsxd rax, r13d\nlea rdx, [rax+rax*2]\nlea rax, [rax+rdx*4]\nlea r12, [rcx+rax*8]\nloc_16B9:\nmov rsi, rbp; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz loc_161D\nadd rbx, 68h ; 'h'\ncmp rbx, r12\njnz short loc_16B9\njmp loc_1623\nloc_16DA:\nmov rax, [rsp+0C8h+var_40]\nsub rax, fs:28h\njnz short loc_1703\nmov rax, [rsp+0C8h+s1]\nadd rsp, 98h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1703:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(_QWORD *a1, unsigned int *a2, int a3, int *a4)\n{\n __int64 v7; // rbx\n unsigned int *v8; // r14\n unsigned __int64 v9; // rax\n char *v10; // rbx\n __int64 v11; // rdx\n unsigned __int64 v12; // rdx\n int v13; // r13d\n char *v14; // rbx\n char *s1; // [rsp+0h] [rbp-C8h]\n unsigned int *v18; // [rsp+10h] [rbp-B8h]\n size_t v19; // [rsp+18h] [rbp-B0h]\n char s2[104]; // [rsp+20h] [rbp-A8h] BYREF\n unsigned __int64 v21; // [rsp+88h] [rbp-40h]\n\n v21 = __readfsqword(0x28u);\n v7 = a3;\n v19 = 104LL * a3;\n s1 = (char *)malloc(v19);\n *a4 = 0;\n if ( a3 > 0 )\n {\n v8 = a2;\n v18 = &a2[v7];\n do\n {\n int_list_to_key(*a1, *v8, s2);\n v13 = *a4;\n if ( *a4 <= 0 )\n {\nLABEL_4:\n v9 = 104LL * v13;\n v10 = &s1[v9];\n v11 = v19;\n if ( v19 < v9 )\n v11 = 104LL * v13;\n v12 = v11 - v9;\n if ( v12 > 0x64 )\n v12 = 100LL;\n __strcpy_chk(v10, s2, v12);\n *((_DWORD *)v10 + 25) = 1;\n *a4 = v13 + 1;\n }\n else\n {\n v14 = s1;\n while ( strcmp(v14, s2) )\n {\n v14 += 104;\n if ( v14 == &s1[104 * v13] )\n goto LABEL_4;\n }\n ++*((_DWORD *)v14 + 25);\n }\n ++v8;\n ++a1;\n }\n while ( v8 != v18 );\n }\n return s1;\n}", + "ida_strip_asm": "sub_15A0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 98h\nmov r15, rdi\nmov rbp, rsi\nmov r12d, edx\nmov r14, rcx\nmov [rsp+0C8h+var_C0], rcx\nmov rax, fs:28h\nmov [rsp+0C8h+var_40], rax\nxor eax, eax\nmovsxd rbx, edx\nlea rax, [rbx+rbx*2]\nlea rax, [rbx+rax*4]\nshl rax, 3\nmov [rsp+0C8h+var_B0], rax\nmov rdi, rax; size\ncall _malloc\nmov [rsp+0C8h+s1], rax\nmov dword ptr [r14], 0\ntest r12d, r12d\njle loc_16DA\nmov r14, rbp\nlea rax, [rbp+rbx*4+0]\nmov [rsp+0C8h+var_B8], rax\nlea rbp, [rsp+0C8h+s2]\njmp short loc_1688\nloc_161D:\nadd dword ptr [rbx+64h], 1\njmp short loc_1676\nloc_1623:\nmovsxd rax, r13d\nlea rdx, [rax+rax*2]\nlea rax, [rax+rdx*4]\nshl rax, 3\nmov rcx, [rsp+0C8h+s1]\nlea rbx, [rcx+rax]\nmov rcx, [rsp+0C8h+var_B0]\ncmp rcx, rax\nmov rdx, rcx\ncmovb rdx, rax\nsub rdx, rax\nmov eax, 64h ; 'd'\ncmp rdx, rax\ncmova rdx, rax\nmov rsi, rbp\nmov rdi, rbx\ncall ___strcpy_chk\nmov dword ptr [rbx+64h], 1\nadd r13d, 1\nmov rax, [rsp+0C8h+var_C0]\nmov [rax], r13d\nloc_1676:\nadd r14, 4\nadd r15, 8\nmov rax, [rsp+0C8h+var_B8]\ncmp r14, rax\njz short loc_16DA\nloc_1688:\nmov esi, [r14]\nmov rdi, [r15]\nmov rdx, rbp\ncall sub_1249\nmov rax, [rsp+0C8h+var_C0]\nmov r13d, [rax]\ntest r13d, r13d\njle short loc_1623\nmov rcx, [rsp+0C8h+s1]\nmov rbx, rcx\nmovsxd rax, r13d\nlea rdx, [rax+rax*2]\nlea rax, [rax+rdx*4]\nlea r12, [rcx+rax*8]\nloc_16B9:\nmov rsi, rbp; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz loc_161D\nadd rbx, 68h ; 'h'\ncmp rbx, r12\njnz short loc_16B9\njmp loc_1623\nloc_16DA:\nmov rax, [rsp+0C8h+var_40]\nsub rax, fs:28h\njnz short loc_1703\nmov rax, [rsp+0C8h+s1]\nadd rsp, 98h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1703:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_15A0(_QWORD *a1, unsigned int *a2, int a3, int *a4)\n{\n __int64 v7; // rbx\n unsigned int *v8; // r14\n unsigned __int64 v9; // rax\n char *v10; // rbx\n __int64 v11; // rdx\n unsigned __int64 v12; // rdx\n int v13; // r13d\n char *v14; // rbx\n char *s1; // [rsp+0h] [rbp-C8h]\n unsigned int *v18; // [rsp+10h] [rbp-B8h]\n size_t v19; // [rsp+18h] [rbp-B0h]\n char s2[104]; // [rsp+20h] [rbp-A8h] BYREF\n unsigned __int64 v21; // [rsp+88h] [rbp-40h]\n\n v21 = __readfsqword(0x28u);\n v7 = a3;\n v19 = 104LL * a3;\n s1 = (char *)malloc(v19);\n *a4 = 0;\n if ( a3 > 0 )\n {\n v8 = a2;\n v18 = &a2[v7];\n do\n {\n sub_1249(*a1, *v8, s2);\n v13 = *a4;\n if ( *a4 <= 0 )\n {\nLABEL_4:\n v9 = 104LL * v13;\n v10 = &s1[v9];\n v11 = v19;\n if ( v19 < v9 )\n v11 = 104LL * v13;\n v12 = v11 - v9;\n if ( v12 > 0x64 )\n v12 = 100LL;\n __strcpy_chk(v10, s2, v12);\n *((_DWORD *)v10 + 25) = 1;\n *a4 = v13 + 1;\n }\n else\n {\n v14 = s1;\n while ( strcmp(v14, s2) )\n {\n v14 += 104;\n if ( v14 == &s1[104 * v13] )\n goto LABEL_4;\n }\n ++*((_DWORD *)v14 + 25);\n }\n ++v8;\n ++a1;\n }\n while ( v8 != v18 );\n }\n return s1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_15A0(uint64_t *a1, unsigned int *a2, int a3, int *a4) {\n long long v7;\n unsigned int *v8;\n unsigned long long v9;\n char *v10;\n long long v11;\n unsigned long long v12;\n int v13;\n char *v14;\n char *s1;\n unsigned int *v18;\n unsigned int v19;\n char s2[104];\n unsigned long long v21;\n v21 = __readfsqword(40u);\n v7 = a3;\n v19 = 104LL * a3;\n s1 = (char *)malloc(v19);\n *a4 = 0;\n if (a3 > 0) {\n v8 = a2;\n v18 = &a2[v7];\n do {\n sub_1249(*a1, *v8, s2);\n v13 = *a4;\n if (*a4 <= 0) {\n LABEL_4:\n v9 = 104LL * v13;\n v10 = &s1[v9];\n v11 = v19;\n if (v19 < v9) v11 = 104LL * v13;\n v12 = v11 - v9;\n if (v12 > 100) v12 = 100LL;\n __strcpy_chk(v10, s2, v12);\n *((uint32_t *)v10 + 25) = 1;\n *a4 = v13 + 1;\n } else {\n v14 = s1;\n while (strcmp(v14, s2)) {\n v14 += 104;\n if (v14 == &s1[104 * v13]) goto LABEL_4;\n }\n ++*((uint32_t *)v14 + 25);\n }\n ++v8;\n ++a1;\n } while (v8 != v18);\n }\n return s1;\n}", + "ida_pseudo_norm": "char *func0(uint64_t *a1, unsigned int *a2, int a3, int *a4) {\n long long v7;\n unsigned int *v8;\n unsigned long long v9;\n char *v10;\n long long v11;\n unsigned long long v12;\n int v13;\n char *v14;\n char *s1;\n unsigned int *v18;\n unsigned int v19;\n char s2[104];\n unsigned long long v21;\n v21 = __readfsqword(40u);\n v7 = a3;\n v19 = 104LL * a3;\n s1 = (char *)malloc(v19);\n *a4 = 0;\n if (a3 > 0) {\n v8 = a2;\n v18 = &a2[v7];\n do {\n int_list_to_key(*a1, *v8, s2);\n v13 = *a4;\n if (*a4 <= 0) {\n LABEL_4:\n v9 = 104LL * v13;\n v10 = &s1[v9];\n v11 = v19;\n if (v19 < v9) v11 = 104LL * v13;\n v12 = v11 - v9;\n if (v12 > 100) v12 = 100LL;\n __strcpy_chk(v10, s2, v12);\n *((uint32_t *)v10 + 25) = 1;\n *a4 = v13 + 1;\n } else {\n v14 = s1;\n while (strcmp(v14, s2)) {\n v14 += 104;\n if (v14 == &s1[104 * v13]) goto LABEL_4;\n }\n ++*((uint32_t *)v14 + 25);\n }\n ++v8;\n ++a1;\n } while (v8 != v18);\n }\n return s1;\n}" + }, + { + "index": 779, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n// Structure to hold key-value pairs\n\ntypedef struct {\n\n char key[100];\n\n int count;\n\n} DictEntry;\n\n\n\n// Function to convert integer list to string key\n\nvoid int_list_to_key(int *list, int size, char *key) {\n\n strcpy(key, \"(\");\n\n for(int i = 0; i < size; i++) {\n\n char num[20];\n\n sprintf(num, \"%d\", list[i]);\n\n strcat(key, num);\n\n if(i < size - 1)\n\n strcat(key, \", \");\n\n }\n\n strcat(key, \")\");\n\n}\n\n\n\n// Function to convert string list to key\n\nvoid str_list_to_key(char **list, int size, char *key) {\n\n strcpy(key, \"(\");\n\n for(int i = 0; i < size; i++) {\n\n strcat(key, \"'\");\n\n strcat(key, list[i]);\n\n strcat(key, \"'\");\n\n if(i < size - 1)\n\n strcat(key, \", \");\n\n }\n\n strcat(key, \")\");\n\n}\n\n\n\n// Unique sublists for string lists\n\nDictEntry* unique_sublists_str(char ***list1, int *sizes, int n, int *unique_count) {\n\n DictEntry *result = malloc(n * sizeof(DictEntry));\n\n *unique_count = 0;\n\n for(int i = 0; i < n; i++) {\n\n char key[100];\n\n str_list_to_key(list1[i], sizes[i], key);\n\n int found = 0;\n\n for(int j = 0; j < *unique_count; j++) {\n\n if(strcmp(result[j].key, key) == 0) {\n\n result[j].count += 1;\n\n found = 1;\n\n break;\n\n }\n\n }\n\n if(!found) {\n\n strcpy(result[*unique_count].key, key);\n\n result[*unique_count].count = 1;\n\n (*unique_count)++;\n\n }\n\n }\n\n return result;\n\n}\n\n\n\n// Function to compare two DictEntry arrays\n\nint compare_dict(DictEntry *dict1, int count1, DictEntry *dict2, int count2) {\n\n if(count1 != count2)\n\n return 0;\n\n for(int i = 0; i < count1; i++) {\n\n int found = 0;\n\n for(int j = 0; j < count2; j++) {\n\n if(strcmp(dict1[i].key, dict2[j].key) == 0 && dict1[i].count == dict2[j].count) {\n\n found = 1;\n\n break;\n\n }\n\n }\n\n if(!found)\n\n return 0;\n\n }\n\n return 1;\n\n}\n\n\n\n// Unique sublists for integer lists\n\n", + "func": "DictEntry *func0(int **list1, int *sizes, int n, int *unique_count) {\n DictEntry *result = malloc(n * sizeof(DictEntry));\n *unique_count = 0;\n for (int i = 0; i < n; i++) {\n char key[100];\n int_list_to_key(list1[i], sizes[i], key);\n int found = 0;\n for (int j = 0; j < *unique_count; j++) {\n if (strcmp(result[j].key, key) == 0) {\n result[j].count += 1;\n found = 1;\n break;\n }\n }\n if (!found) {\n strcpy(result[*unique_count].key, key);\n result[*unique_count].count = 1;\n (*unique_count)++;\n }\n }\n return result;\n}", + "test": "int main() {\n\n // Test case 1\n\n int list1_case1_data[][3] = { {1, 3}, {5, 7}, {1, 3}, {13, 15, 17}, {5, 7}, {9, 11} };\n\n int sizes_case1[] = {2, 2, 2, 3, 2, 2};\n\n int *list1_case1[6];\n\n for(int i = 0; i < 6; i++) {\n\n list1_case1[i] = list1_case1_data[i];\n\n }\n\n int unique_count1;\n\n DictEntry *result1 = func0(list1_case1, sizes_case1, 6, &unique_count1);\n\n DictEntry expected1[] = { {\"(1, 3)\", 2}, {\"(5, 7)\", 2}, {\"(13, 15, 17)\", 1}, {\"(9, 11)\", 1} };\n\n assert(compare_dict(result1, unique_count1, expected1, 4));\n\n free(result1);\n\n\n\n // Test case 2\n\n char *list1_case2_data[][2] = { {\"green\", \"orange\"}, {\"black\"}, {\"green\", \"orange\"}, {\"white\"} };\n\n int sizes_case2[] = {2, 1, 2, 1};\n\n char **list1_case2[4];\n\n for(int i = 0; i < 4; i++) {\n\n list1_case2[i] = list1_case2_data[i];\n\n }\n\n int unique_count2;\n\n DictEntry *result2 = unique_sublists_str(list1_case2, sizes_case2, 4, &unique_count2);\n\n DictEntry expected2[] = { {\"('green', 'orange')\", 2}, {\"('black')\", 1}, {\"('white')\", 1} };\n\n assert(compare_dict(result2, unique_count2, expected2, 3));\n\n free(result2);\n\n\n\n // Test case 3\n\n int list1_case3_data[][2] = { {1, 2}, {3, 4}, {4, 5}, {6, 7} };\n\n int sizes_case3[] = {2, 2, 2, 2};\n\n int *list1_case3[4];\n\n for(int i = 0; i < 4; i++) {\n\n list1_case3[i] = list1_case3_data[i];\n\n }\n\n int unique_count3;\n\n DictEntry *result3 = func0(list1_case3, sizes_case3, 4, &unique_count3);\n\n DictEntry expected3[] = { {\"(1, 2)\", 1}, {\"(3, 4)\", 1}, {\"(4, 5)\", 1}, {\"(6, 7)\", 1} };\n\n assert(compare_dict(result3, unique_count3, expected3, 4));\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmov %rcx,%r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %edx,%ebx\nsub $0x98,%rsp\nmov %rdi,0x8(%rsp)\nmov %rsi,0x10(%rsp)\nmov %rcx,(%rsp)\nmov %fs:0x28,%rax\nmov %rax,0x88(%rsp)\nxor %eax,%eax\nmovslq %edx,%rax\nlea (%rax,%rax,2),%rdx\nlea (%rax,%rdx,4),%rdi\nshl $0x3,%rdi\ncallq 1130 \nmovl $0x0,(%r15)\nmov %rax,%r14\ntest %ebx,%ebx\njle 1b2c \nlea -0x1(%rbx),%eax\nxor %r13d,%r13d\nlea 0x20(%rsp),%rbx\nmov %rax,0x18(%rsp)\nnopl 0x0(%rax)\nmov 0x10(%rsp),%rax\nmov %rbx,%rdx\nmov (%rax,%r13,4),%esi\nmov 0x8(%rsp),%rax\nmov (%rax,%r13,8),%rdi\ncallq 1700 \nmov (%rsp),%rax\nmov (%rax),%r12d\ntest %r12d,%r12d\njle 1af0 \nlea -0x1(%r12),%eax\nmov %r14,%r15\nadd $0x1,%rax\nlea (%rax,%rax,2),%rcx\nlea (%rax,%rcx,4),%rax\nlea (%r14,%rax,8),%rbp\njmp 1ac9 \nnopl 0x0(%rax,%rax,1)\nadd $0x68,%r15\ncmp %r15,%rbp\nje 1af0 \nmov %rbx,%rsi\nmov %r15,%rdi\ncallq 1120 \ntest %eax,%eax\njne 1ac0 \naddl $0x1,0x64(%r15)\nlea 0x1(%r13),%rax\ncmp 0x18(%rsp),%r13\nje 1b2c \nmov %rax,%r13\njmp 1a78 \nnopl (%rax)\nmovslq %r12d,%rax\nmov %rbx,%rsi\nadd $0x1,%r12d\nlea (%rax,%rax,2),%rdx\nlea (%rax,%rdx,4),%rax\nmov $0x64,%edx\nlea (%r14,%rax,8),%rcx\nmov %rcx,%rdi\ncallq 1140 <__strcpy_chk@plt>\nmovl $0x1,0x64(%rax)\nmov (%rsp),%rax\nmov %r12d,(%rax)\nlea 0x1(%r13),%rax\ncmp 0x18(%rsp),%r13\njne 1ae8 \nmov 0x88(%rsp),%rax\nxor %fs:0x28,%rax\njne 1b54 \nadd $0x98,%rsp\nmov %r14,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\ncallq 1100 <__stack_chk_fail@plt>\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov r15, rdi\npush r14\nmov r14, rcx\npush r13\nmov r13, rsi\npush r12\npush rbp\nmovsxd rbp, edx\npush rbx\nsub rsp, 0A8h\nmov [rsp+0D8h+var_C0], rcx\nmov rax, fs:28h\nmov [rsp+0D8h+var_40], rax\nxor eax, eax\nlea rax, [rbp+rbp*2+0]\nlea rax, [rbp+rax*4+0]\nshl rax, 3\nmov rdi, rax; size\nmov [rsp+0D8h+var_B0], rax\ncall _malloc\nmov dword ptr [r14], 0\nmov [rsp+0D8h+s1], rax\ntest ebp, ebp\njle loc_1ACF\nlea rax, [r13+rbp*4+0]\nlea rbx, [rsp+0D8h+s2]\nmov [rsp+0D8h+var_B8], rax\nnop word ptr [rax+rax+00000000h]\nloc_1A60:\nmov esi, [r13+0]\nmov rdi, [r15]\nmov rdx, rbx\ncall int_list_to_key\nmov rax, [rsp+0D8h+var_C0]\nmov eax, [rax]\nmov [rsp+0D8h+var_CC], eax\nmovsxd r12, eax\ntest eax, eax\njle short loc_1B00\nmovsxd r12, [rsp+0D8h+var_CC]\nmov rcx, [rsp+0D8h+s1]\nlea rax, [r12+r12*2]\nmov r14, rcx\nlea rax, [r12+rax*4]\nlea rbp, [rcx+rax*8]\njmp short loc_1AA9\nloc_1AA0:\nadd r14, 68h ; 'h'\ncmp r14, rbp\njz short loc_1B00\nloc_1AA9:\nmov rsi, rbx; s2\nmov rdi, r14; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1AA0\nadd dword ptr [r14+64h], 1\nloc_1ABD:\nmov rax, [rsp+0D8h+var_B8]\nadd r13, 4\nadd r15, 8\ncmp r13, rax\njnz short loc_1A60\nloc_1ACF:\nmov rax, [rsp+0D8h+var_40]\nsub rax, fs:28h\njnz short loc_1B57\nmov rax, [rsp+0D8h+s1]\nadd rsp, 0A8h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1B00:\nlea rax, [r12+r12*2]\nmov rdx, [rsp+0D8h+var_B0]\nmov rcx, [rsp+0D8h+s1]\nmov rsi, rbx\nlea rax, [r12+rax*4]\nshl rax, 3\nadd rcx, rax\ncmp rdx, rax\ncmovb rdx, rax\nmov rdi, rcx\nsub rdx, rax\nmov eax, 64h ; 'd'\ncmp rdx, rax\ncmova rdx, rax\ncall ___strcpy_chk\nmov r14d, [rsp+0D8h+var_CC]\nmov dword ptr [rax+64h], 1\nmov rax, [rsp+0D8h+var_C0]\nadd r14d, 1\nmov [rax], r14d\njmp loc_1ABD\nloc_1B57:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(_QWORD *a1, unsigned int *a2, int a3, int *a4)\n{\n unsigned int *v6; // r13\n __int64 v7; // rbp\n char *v8; // rax\n __int64 v9; // r12\n char *v10; // r14\n __int64 v12; // rdx\n unsigned __int64 v13; // rdx\n int v14; // [rsp+Ch] [rbp-CCh]\n char *s1; // [rsp+10h] [rbp-C8h]\n size_t v17; // [rsp+28h] [rbp-B0h]\n char s2[104]; // [rsp+30h] [rbp-A8h] BYREF\n unsigned __int64 v19; // [rsp+98h] [rbp-40h]\n\n v6 = a2;\n v7 = a3;\n v19 = __readfsqword(0x28u);\n v17 = 104LL * a3;\n v8 = (char *)malloc(v17);\n *a4 = 0;\n s1 = v8;\n if ( (int)v7 > 0 )\n {\n do\n {\n int_list_to_key(*a1, *v6, s2);\n v14 = *a4;\n v9 = *a4;\n if ( *a4 <= 0 )\n {\nLABEL_9:\n v12 = v17;\n if ( v17 < 104 * v9 )\n v12 = 104 * v9;\n v13 = v12 - 104 * v9;\n if ( v13 > 0x64 )\n v13 = 100LL;\n *(_DWORD *)(__strcpy_chk(&s1[104 * v9], s2, v13, &s1[104 * v9]) + 100) = 1;\n *a4 = v14 + 1;\n }\n else\n {\n v9 = v14;\n v10 = s1;\n while ( strcmp(v10, s2) )\n {\n v10 += 104;\n if ( v10 == &s1[104 * v14] )\n goto LABEL_9;\n }\n ++*((_DWORD *)v10 + 25);\n }\n ++v6;\n ++a1;\n }\n while ( v6 != &a2[v7] );\n }\n return s1;\n}", + "ida_strip_asm": "sub_19E0:\nendbr64\npush r15\nmov r15, rdi\npush r14\nmov r14, rcx\npush r13\nmov r13, rsi\npush r12\npush rbp\nmovsxd rbp, edx\npush rbx\nsub rsp, 0A8h\nmov [rsp+0D8h+var_C0], rcx\nmov rax, fs:28h\nmov [rsp+0D8h+var_40], rax\nxor eax, eax\nlea rax, [rbp+rbp*2+0]\nlea rax, [rbp+rax*4+0]\nshl rax, 3\nmov rdi, rax; size\nmov [rsp+0D8h+var_B0], rax\ncall _malloc\nmov dword ptr [r14], 0\nmov [rsp+0D8h+s1], rax\ntest ebp, ebp\njle loc_1ACF\nlea rax, [r13+rbp*4+0]\nlea rbx, [rsp+0D8h+s2]\nmov [rsp+0D8h+var_B8], rax\nnop word ptr [rax+rax+00000000h]\nloc_1A60:\nmov esi, [r13+0]\nmov rdi, [r15]\nmov rdx, rbx\ncall sub_16E0\nmov rax, [rsp+0D8h+var_C0]\nmov eax, [rax]\nmov [rsp+0D8h+var_CC], eax\nmovsxd r12, eax\ntest eax, eax\njle short loc_1B00\nmovsxd r12, [rsp+0D8h+var_CC]\nmov rcx, [rsp+0D8h+s1]\nlea rax, [r12+r12*2]\nmov r14, rcx\nlea rax, [r12+rax*4]\nlea rbp, [rcx+rax*8]\njmp short loc_1AA9\nloc_1AA0:\nadd r14, 68h ; 'h'\ncmp r14, rbp\njz short loc_1B00\nloc_1AA9:\nmov rsi, rbx; s2\nmov rdi, r14; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1AA0\nadd dword ptr [r14+64h], 1\nloc_1ABD:\nmov rax, [rsp+0D8h+var_B8]\nadd r13, 4\nadd r15, 8\ncmp r13, rax\njnz short loc_1A60\nloc_1ACF:\nmov rax, [rsp+0D8h+var_40]\nsub rax, fs:28h\njnz short loc_1B57\nmov rax, [rsp+0D8h+s1]\nadd rsp, 0A8h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1B00:\nlea rax, [r12+r12*2]\nmov rdx, [rsp+0D8h+var_B0]\nmov rcx, [rsp+0D8h+s1]\nmov rsi, rbx\nlea rax, [r12+rax*4]\nshl rax, 3\nadd rcx, rax\ncmp rdx, rax\ncmovb rdx, rax\nmov rdi, rcx\nsub rdx, rax\nmov eax, 64h ; 'd'\ncmp rdx, rax\ncmova rdx, rax\ncall ___strcpy_chk\nmov r14d, [rsp+0D8h+var_CC]\nmov dword ptr [rax+64h], 1\nmov rax, [rsp+0D8h+var_C0]\nadd r14d, 1\nmov [rax], r14d\njmp loc_1ABD\nloc_1B57:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_19E0(_QWORD *a1, unsigned int *a2, int a3, int *a4)\n{\n unsigned int *v6; // r13\n __int64 v7; // rbp\n char *v8; // rax\n __int64 v9; // r12\n char *v10; // r14\n __int64 v12; // rdx\n unsigned __int64 v13; // rdx\n int v14; // [rsp+Ch] [rbp-CCh]\n char *s1; // [rsp+10h] [rbp-C8h]\n size_t v17; // [rsp+28h] [rbp-B0h]\n char s2[104]; // [rsp+30h] [rbp-A8h] BYREF\n unsigned __int64 v19; // [rsp+98h] [rbp-40h]\n\n v6 = a2;\n v7 = a3;\n v19 = __readfsqword(0x28u);\n v17 = 104LL * a3;\n v8 = (char *)malloc(v17);\n *a4 = 0;\n s1 = v8;\n if ( (int)v7 > 0 )\n {\n do\n {\n sub_16E0(*a1, *v6, s2);\n v14 = *a4;\n v9 = *a4;\n if ( *a4 <= 0 )\n {\nLABEL_9:\n v12 = v17;\n if ( v17 < 104 * v9 )\n v12 = 104 * v9;\n v13 = v12 - 104 * v9;\n if ( v13 > 0x64 )\n v13 = 100LL;\n *(_DWORD *)(__strcpy_chk(&s1[104 * v9], s2, v13, &s1[104 * v9]) + 100) = 1;\n *a4 = v14 + 1;\n }\n else\n {\n v9 = v14;\n v10 = s1;\n while ( strcmp(v10, s2) )\n {\n v10 += 104;\n if ( v10 == &s1[104 * v14] )\n goto LABEL_9;\n }\n ++*((_DWORD *)v10 + 25);\n }\n ++v6;\n ++a1;\n }\n while ( v6 != &a2[v7] );\n }\n return s1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_19E0(uint64_t *a1, unsigned int *a2, int a3, int *a4) {\n unsigned int *v6;\n long long v7;\n char *v8;\n long long v9;\n char *v10;\n long long v12;\n unsigned long long v13;\n int v14;\n char *s1;\n unsigned int v17;\n char s2[104];\n unsigned long long v19;\n v6 = a2;\n v7 = a3;\n v19 = __readfsqword(40u);\n v17 = 104LL * a3;\n v8 = (char *)malloc(v17);\n *a4 = 0;\n s1 = v8;\n if ((int)v7 > 0) {\n do {\n sub_16E0(*a1, *v6, s2);\n v14 = *a4;\n v9 = *a4;\n if (*a4 <= 0) {\n LABEL_9:\n v12 = v17;\n if (v17 < 104 * v9) v12 = 104 * v9;\n v13 = v12 - 104 * v9;\n if (v13 > 100) v13 = 100LL;\n *(uint32_t *)(__strcpy_chk(&s1[104 * v9], s2, v13, &s1[104 * v9]) +\n 100) = 1;\n *a4 = v14 + 1;\n } else {\n v9 = v14;\n v10 = s1;\n while (strcmp(v10, s2)) {\n v10 += 104;\n if (v10 == &s1[104 * v14]) goto LABEL_9;\n }\n ++*((uint32_t *)v10 + 25);\n }\n ++v6;\n ++a1;\n } while (v6 != &a2[v7]);\n }\n return s1;\n}", + "ida_pseudo_norm": "char *func0(uint64_t *a1, unsigned int *a2, int a3, int *a4) {\n unsigned int *v6;\n long long v7;\n char *v8;\n long long v9;\n char *v10;\n long long v12;\n unsigned long long v13;\n int v14;\n char *s1;\n unsigned int v17;\n char s2[104];\n unsigned long long v19;\n v6 = a2;\n v7 = a3;\n v19 = __readfsqword(40u);\n v17 = 104LL * a3;\n v8 = (char *)malloc(v17);\n *a4 = 0;\n s1 = v8;\n if ((int)v7 > 0) {\n do {\n int_list_to_key(*a1, *v6, s2);\n v14 = *a4;\n v9 = *a4;\n if (*a4 <= 0) {\n LABEL_9:\n v12 = v17;\n if (v17 < 104 * v9) v12 = 104 * v9;\n v13 = v12 - 104 * v9;\n if (v13 > 100) v13 = 100LL;\n *(uint32_t *)(__strcpy_chk(&s1[104 * v9], s2, v13, &s1[104 * v9]) +\n 100) = 1;\n *a4 = v14 + 1;\n } else {\n v9 = v14;\n v10 = s1;\n while (strcmp(v10, s2)) {\n v10 += 104;\n if (v10 == &s1[104 * v14]) goto LABEL_9;\n }\n ++*((uint32_t *)v10 + 25);\n }\n ++v6;\n ++a1;\n } while (v6 != &a2[v7]);\n }\n return s1;\n}" + }, + { + "index": 779, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n// Structure to hold key-value pairs\n\ntypedef struct {\n\n char key[100];\n\n int count;\n\n} DictEntry;\n\n\n\n// Function to convert integer list to string key\n\nvoid int_list_to_key(int *list, int size, char *key) {\n\n strcpy(key, \"(\");\n\n for(int i = 0; i < size; i++) {\n\n char num[20];\n\n sprintf(num, \"%d\", list[i]);\n\n strcat(key, num);\n\n if(i < size - 1)\n\n strcat(key, \", \");\n\n }\n\n strcat(key, \")\");\n\n}\n\n\n\n// Function to convert string list to key\n\nvoid str_list_to_key(char **list, int size, char *key) {\n\n strcpy(key, \"(\");\n\n for(int i = 0; i < size; i++) {\n\n strcat(key, \"'\");\n\n strcat(key, list[i]);\n\n strcat(key, \"'\");\n\n if(i < size - 1)\n\n strcat(key, \", \");\n\n }\n\n strcat(key, \")\");\n\n}\n\n\n\n// Unique sublists for string lists\n\nDictEntry* unique_sublists_str(char ***list1, int *sizes, int n, int *unique_count) {\n\n DictEntry *result = malloc(n * sizeof(DictEntry));\n\n *unique_count = 0;\n\n for(int i = 0; i < n; i++) {\n\n char key[100];\n\n str_list_to_key(list1[i], sizes[i], key);\n\n int found = 0;\n\n for(int j = 0; j < *unique_count; j++) {\n\n if(strcmp(result[j].key, key) == 0) {\n\n result[j].count += 1;\n\n found = 1;\n\n break;\n\n }\n\n }\n\n if(!found) {\n\n strcpy(result[*unique_count].key, key);\n\n result[*unique_count].count = 1;\n\n (*unique_count)++;\n\n }\n\n }\n\n return result;\n\n}\n\n\n\n// Function to compare two DictEntry arrays\n\nint compare_dict(DictEntry *dict1, int count1, DictEntry *dict2, int count2) {\n\n if(count1 != count2)\n\n return 0;\n\n for(int i = 0; i < count1; i++) {\n\n int found = 0;\n\n for(int j = 0; j < count2; j++) {\n\n if(strcmp(dict1[i].key, dict2[j].key) == 0 && dict1[i].count == dict2[j].count) {\n\n found = 1;\n\n break;\n\n }\n\n }\n\n if(!found)\n\n return 0;\n\n }\n\n return 1;\n\n}\n\n\n\n// Unique sublists for integer lists\n\n", + "func": "DictEntry *func0(int **list1, int *sizes, int n, int *unique_count) {\n DictEntry *result = malloc(n * sizeof(DictEntry));\n *unique_count = 0;\n for (int i = 0; i < n; i++) {\n char key[100];\n int_list_to_key(list1[i], sizes[i], key);\n int found = 0;\n for (int j = 0; j < *unique_count; j++) {\n if (strcmp(result[j].key, key) == 0) {\n result[j].count += 1;\n found = 1;\n break;\n }\n }\n if (!found) {\n strcpy(result[*unique_count].key, key);\n result[*unique_count].count = 1;\n (*unique_count)++;\n }\n }\n return result;\n}", + "test": "int main() {\n\n // Test case 1\n\n int list1_case1_data[][3] = { {1, 3}, {5, 7}, {1, 3}, {13, 15, 17}, {5, 7}, {9, 11} };\n\n int sizes_case1[] = {2, 2, 2, 3, 2, 2};\n\n int *list1_case1[6];\n\n for(int i = 0; i < 6; i++) {\n\n list1_case1[i] = list1_case1_data[i];\n\n }\n\n int unique_count1;\n\n DictEntry *result1 = func0(list1_case1, sizes_case1, 6, &unique_count1);\n\n DictEntry expected1[] = { {\"(1, 3)\", 2}, {\"(5, 7)\", 2}, {\"(13, 15, 17)\", 1}, {\"(9, 11)\", 1} };\n\n assert(compare_dict(result1, unique_count1, expected1, 4));\n\n free(result1);\n\n\n\n // Test case 2\n\n char *list1_case2_data[][2] = { {\"green\", \"orange\"}, {\"black\"}, {\"green\", \"orange\"}, {\"white\"} };\n\n int sizes_case2[] = {2, 1, 2, 1};\n\n char **list1_case2[4];\n\n for(int i = 0; i < 4; i++) {\n\n list1_case2[i] = list1_case2_data[i];\n\n }\n\n int unique_count2;\n\n DictEntry *result2 = unique_sublists_str(list1_case2, sizes_case2, 4, &unique_count2);\n\n DictEntry expected2[] = { {\"('green', 'orange')\", 2}, {\"('black')\", 1}, {\"('white')\", 1} };\n\n assert(compare_dict(result2, unique_count2, expected2, 3));\n\n free(result2);\n\n\n\n // Test case 3\n\n int list1_case3_data[][2] = { {1, 2}, {3, 4}, {4, 5}, {6, 7} };\n\n int sizes_case3[] = {2, 2, 2, 2};\n\n int *list1_case3[4];\n\n for(int i = 0; i < 4; i++) {\n\n list1_case3[i] = list1_case3_data[i];\n\n }\n\n int unique_count3;\n\n DictEntry *result3 = func0(list1_case3, sizes_case3, 4, &unique_count3);\n\n DictEntry expected3[] = { {\"(1, 2)\", 1}, {\"(3, 4)\", 1}, {\"(4, 5)\", 1}, {\"(6, 7)\", 1} };\n\n assert(compare_dict(result3, unique_count3, expected3, 4));\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\nmov %rcx,%r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %edx,%ebx\nsub $0xd8,%rsp\nmov %rdi,0x28(%rsp)\nmov %rsi,0x30(%rsp)\nmov %rcx,0x10(%rsp)\nmov %fs:0x28,%rax\nmov %rax,0xc8(%rsp)\nxor %eax,%eax\nmovslq %edx,%rax\nlea (%rax,%rax,2),%rdx\nlea (%rax,%rdx,4),%rdi\nshl $0x3,%rdi\ncallq 1190 \nmovl $0x0,(%r14)\nmov %rax,0x20(%rsp)\ntest %ebx,%ebx\njle 203a \nlea -0x1(%rbx),%eax\nmovq $0x0,(%rsp)\nlea 0x60(%rsp),%r15\nmov %rax,0x38(%rsp)\nmov (%rsp),%rax\nlea 0x1200(%rip),%r14\nnopl 0x0(%rax)\nmov 0x30(%rsp),%rsi\nmov $0x28,%edx\nmov %dx,(%r15)\nmov (%rsi,%rax,4),%r13d\nmov 0x28(%rsp),%rsi\nmov (%rsi,%rax,8),%rax\nmov %rax,0x8(%rsp)\ntest %r13d,%r13d\njle 1f34 \nlea -0x1(%r13),%eax\ntest %eax,%eax\njle 1fe0 \nmov 0x8(%rsp),%r12\nmov %r13d,0x1c(%rsp)\nxor %ebx,%ebx\nmov %eax,%r13d\nlea 0x40(%rsp),%rbp\nnopl 0x0(%rax)\nmov (%r12),%r8d\nmov %rbp,%rdi\nmov %r14,%rcx\nmov $0x14,%edx\nmov $0x1,%esi\nxor %eax,%eax\ncallq 11b0 <__sprintf_chk@plt>\nmov %r15,%rdi\nmov (%rdi),%edx\nadd $0x4,%rdi\nlea -0x1010101(%rdx),%eax\nnot %edx\nand %edx,%eax\nand $0x80808080,%eax\nje 1e76 \nmov %eax,%edx\nshr $0x10,%edx\ntest $0x8080,%eax\ncmove %edx,%eax\nlea 0x2(%rdi),%rdx\ncmove %rdx,%rdi\nmov $0x64,%edx\nmov %eax,%esi\nadd %al,%sil\nmov %rbp,%rsi\nsbb $0x3,%rdi\nadd $0x1,%ebx\nadd $0x4,%r12\ncallq 1180 <__stpcpy_chk@plt>\nmov %r15,%rcx\nmov $0x3,%edx\nlea 0x113b(%rip),%rsi\nsub %rax,%rcx\nmov %rax,%rdi\nadd $0x64,%rcx\ncallq 1170 <__memcpy_chk@plt>\ncmp %r13d,%ebx\njl 1e58 \nmov 0x1c(%rsp),%r13d\ncmp %ebx,%r13d\njle 1f34 \nmov 0x8(%rsp),%r12\nmovslq %ebx,%rbx\nnopl 0x0(%rax,%rax,1)\nmov (%r12,%rbx,4),%r8d\nmov %r14,%rcx\nmov $0x14,%edx\nmov %rbp,%rdi\nmov $0x1,%esi\nxor %eax,%eax\nadd $0x1,%rbx\ncallq 11b0 <__sprintf_chk@plt>\nmov $0x64,%edx\nmov %rbp,%rsi\nmov %r15,%rdi\ncallq 1100 <__strcat_chk@plt>\ncmp %ebx,%r13d\njg 1f00 \nmov %r15,%rbx\nmov (%rbx),%edx\nadd $0x4,%rbx\nlea -0x1010101(%rdx),%eax\nnot %edx\nand %edx,%eax\nand $0x80808080,%eax\nje 1f37 \nmov %eax,%edx\nshr $0x10,%edx\ntest $0x8080,%eax\ncmove %edx,%eax\nlea 0x2(%rbx),%rdx\ncmove %rdx,%rbx\nmov %eax,%esi\nadd %al,%sil\nmov $0x29,%eax\nsbb $0x3,%rbx\nmov %ax,(%rbx)\nmov 0x10(%rsp),%rax\nadd $0x1,%rbx\nmov (%rax),%r12d\ntest %r12d,%r12d\njle 1ff0 \nlea -0x1(%r12),%eax\nmov 0x20(%rsp),%rsi\nadd $0x1,%rax\nlea (%rax,%rax,2),%rdx\nmov %rsi,%r13\nlea (%rax,%rdx,4),%rax\nlea (%rsi,%rax,8),%rbp\njmp 1fb1 \nnopl 0x0(%rax)\nadd $0x68,%r13\ncmp %rbp,%r13\nje 1ff0 \nmov %r15,%rsi\nmov %r13,%rdi\ncallq 1160 \ntest %eax,%eax\njne 1fa8 \nmov (%rsp),%rsi\naddl $0x1,0x64(%r13)\nlea 0x1(%rsi),%rax\ncmp 0x38(%rsp),%rsi\nje 203a \nmov %rax,(%rsp)\njmpq 1e08 \nnopl (%rax)\nxor %ebx,%ebx\nlea 0x40(%rsp),%rbp\njmpq 1ef0 \nnopl 0x0(%rax)\nmovslq %r12d,%rax\nmov 0x20(%rsp),%rsi\nsub %r15,%rbx\nmov $0x64,%ecx\nlea (%rax,%rax,2),%rdx\nadd $0x1,%r12d\nlea (%rax,%rdx,4),%rax\nlea 0x1(%rbx),%rdx\nlea (%rsi,%rax,8),%rdi\nmov %r15,%rsi\ncallq 1170 <__memcpy_chk@plt>\nmov (%rsp),%rsi\nmovl $0x1,0x64(%rax)\nmov 0x10(%rsp),%rax\nmov %r12d,(%rax)\nlea 0x1(%rsi),%rax\ncmp 0x38(%rsp),%rsi\njne 1fd4 \nmov 0xc8(%rsp),%rax\nxor %fs:0x28,%rax\njne 2064 \nmov 0x20(%rsp),%rax\nadd $0xd8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\ncallq 1140 <__stack_chk_fail@plt>\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov r15, rdi\npush r14\nmov r14, rcx\npush r13\nmov r13, rsi\npush r12\npush rbp\nmovsxd rbp, edx\npush rbx\nsub rsp, 0A8h\nmov [rsp+0D8h+var_C0], rcx\nmov rax, fs:28h\nmov [rsp+0D8h+var_40], rax\nxor eax, eax\nlea rax, [rbp+rbp*2+0]\nlea rax, [rbp+rax*4+0]\nshl rax, 3\nmov rdi, rax; size\nmov [rsp+0D8h+var_B0], rax\ncall _malloc\nmov dword ptr [r14], 0\nmov [rsp+0D8h+s1], rax\ntest ebp, ebp\njle loc_1C3F\nlea rax, [r13+rbp*4+0]\nlea rbx, [rsp+0D8h+s2]\nmov [rsp+0D8h+var_B8], rax\nnop word ptr [rax+rax+00000000h]\nloc_1BD0:\nmov esi, [r13+0]\nmov rdi, [r15]\nmov rdx, rbx\ncall int_list_to_key\nmov rax, [rsp+0D8h+var_C0]\nmov eax, [rax]\nmov [rsp+0D8h+var_CC], eax\nmovsxd r12, eax\ntest eax, eax\njle short loc_1C70\nmovsxd r12, [rsp+0D8h+var_CC]\nmov rcx, [rsp+0D8h+s1]\nlea rax, [r12+r12*2]\nmov r14, rcx\nlea rax, [r12+rax*4]\nlea rbp, [rcx+rax*8]\njmp short loc_1C19\nloc_1C10:\nadd r14, 68h ; 'h'\ncmp r14, rbp\njz short loc_1C70\nloc_1C19:\nmov rsi, rbx; s2\nmov rdi, r14; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1C10\nadd dword ptr [r14+64h], 1\nloc_1C2D:\nmov rax, [rsp+0D8h+var_B8]\nadd r13, 4\nadd r15, 8\ncmp r13, rax\njnz short loc_1BD0\nloc_1C3F:\nmov rax, [rsp+0D8h+var_40]\nsub rax, fs:28h\njnz short loc_1CC7\nmov rax, [rsp+0D8h+s1]\nadd rsp, 0A8h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1C70:\nlea rax, [r12+r12*2]\nmov rdx, [rsp+0D8h+var_B0]\nmov rcx, [rsp+0D8h+s1]\nmov rsi, rbx\nlea rax, [r12+rax*4]\nshl rax, 3\nadd rcx, rax\ncmp rdx, rax\ncmovb rdx, rax\nmov rdi, rcx\nsub rdx, rax\nmov eax, 64h ; 'd'\ncmp rdx, rax\ncmova rdx, rax\ncall ___strcpy_chk\nmov r14d, [rsp+0D8h+var_CC]\nmov dword ptr [rax+64h], 1\nmov rax, [rsp+0D8h+var_C0]\nadd r14d, 1\nmov [rax], r14d\njmp loc_1C2D\nloc_1CC7:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(_QWORD *a1, unsigned int *a2, int a3, int *a4)\n{\n unsigned int *v6; // r13\n __int64 v7; // rbp\n char *v8; // rax\n __int64 v9; // r12\n char *v10; // r14\n __int64 v12; // rdx\n unsigned __int64 v13; // rdx\n int v14; // [rsp+Ch] [rbp-CCh]\n char *s1; // [rsp+10h] [rbp-C8h]\n size_t v17; // [rsp+28h] [rbp-B0h]\n char s2[104]; // [rsp+30h] [rbp-A8h] BYREF\n unsigned __int64 v19; // [rsp+98h] [rbp-40h]\n\n v6 = a2;\n v7 = a3;\n v19 = __readfsqword(0x28u);\n v17 = 104LL * a3;\n v8 = (char *)malloc(v17);\n *a4 = 0;\n s1 = v8;\n if ( (int)v7 > 0 )\n {\n do\n {\n int_list_to_key(*a1, *v6, s2);\n v14 = *a4;\n v9 = *a4;\n if ( *a4 <= 0 )\n {\nLABEL_9:\n v12 = v17;\n if ( v17 < 104 * v9 )\n v12 = 104 * v9;\n v13 = v12 - 104 * v9;\n if ( v13 > 0x64 )\n v13 = 100LL;\n *(_DWORD *)(__strcpy_chk(&s1[104 * v9], s2, v13, &s1[104 * v9]) + 100) = 1;\n *a4 = v14 + 1;\n }\n else\n {\n v9 = v14;\n v10 = s1;\n while ( strcmp(v10, s2) )\n {\n v10 += 104;\n if ( v10 == &s1[104 * v14] )\n goto LABEL_9;\n }\n ++*((_DWORD *)v10 + 25);\n }\n ++v6;\n ++a1;\n }\n while ( v6 != &a2[v7] );\n }\n return s1;\n}", + "ida_strip_asm": "sub_1B50:\nendbr64\npush r15\nmov r15, rdi\npush r14\nmov r14, rcx\npush r13\nmov r13, rsi\npush r12\npush rbp\nmovsxd rbp, edx\npush rbx\nsub rsp, 0A8h\nmov [rsp+0D8h+var_C0], rcx\nmov rax, fs:28h\nmov [rsp+0D8h+var_40], rax\nxor eax, eax\nlea rax, [rbp+rbp*2+0]\nlea rax, [rbp+rax*4+0]\nshl rax, 3\nmov rdi, rax; size\nmov [rsp+0D8h+var_B0], rax\ncall _malloc\nmov dword ptr [r14], 0\nmov [rsp+0D8h+s1], rax\ntest ebp, ebp\njle loc_1C3F\nlea rax, [r13+rbp*4+0]\nlea rbx, [rsp+0D8h+s2]\nmov [rsp+0D8h+var_B8], rax\nnop word ptr [rax+rax+00000000h]\nloc_1BD0:\nmov esi, [r13+0]\nmov rdi, [r15]\nmov rdx, rbx\ncall sub_1700\nmov rax, [rsp+0D8h+var_C0]\nmov eax, [rax]\nmov [rsp+0D8h+var_CC], eax\nmovsxd r12, eax\ntest eax, eax\njle short loc_1C70\nmovsxd r12, [rsp+0D8h+var_CC]\nmov rcx, [rsp+0D8h+s1]\nlea rax, [r12+r12*2]\nmov r14, rcx\nlea rax, [r12+rax*4]\nlea rbp, [rcx+rax*8]\njmp short loc_1C19\nloc_1C10:\nadd r14, 68h ; 'h'\ncmp r14, rbp\njz short loc_1C70\nloc_1C19:\nmov rsi, rbx; s2\nmov rdi, r14; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1C10\nadd dword ptr [r14+64h], 1\nloc_1C2D:\nmov rax, [rsp+0D8h+var_B8]\nadd r13, 4\nadd r15, 8\ncmp r13, rax\njnz short loc_1BD0\nloc_1C3F:\nmov rax, [rsp+0D8h+var_40]\nsub rax, fs:28h\njnz short loc_1CC7\nmov rax, [rsp+0D8h+s1]\nadd rsp, 0A8h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1C70:\nlea rax, [r12+r12*2]\nmov rdx, [rsp+0D8h+var_B0]\nmov rcx, [rsp+0D8h+s1]\nmov rsi, rbx\nlea rax, [r12+rax*4]\nshl rax, 3\nadd rcx, rax\ncmp rdx, rax\ncmovb rdx, rax\nmov rdi, rcx\nsub rdx, rax\nmov eax, 64h ; 'd'\ncmp rdx, rax\ncmova rdx, rax\ncall ___strcpy_chk\nmov r14d, [rsp+0D8h+var_CC]\nmov dword ptr [rax+64h], 1\nmov rax, [rsp+0D8h+var_C0]\nadd r14d, 1\nmov [rax], r14d\njmp loc_1C2D\nloc_1CC7:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_1B50(_QWORD *a1, unsigned int *a2, int a3, int *a4)\n{\n unsigned int *v6; // r13\n __int64 v7; // rbp\n char *v8; // rax\n __int64 v9; // r12\n char *v10; // r14\n __int64 v12; // rdx\n unsigned __int64 v13; // rdx\n int v14; // [rsp+Ch] [rbp-CCh]\n char *s1; // [rsp+10h] [rbp-C8h]\n size_t v17; // [rsp+28h] [rbp-B0h]\n char s2[104]; // [rsp+30h] [rbp-A8h] BYREF\n unsigned __int64 v19; // [rsp+98h] [rbp-40h]\n\n v6 = a2;\n v7 = a3;\n v19 = __readfsqword(0x28u);\n v17 = 104LL * a3;\n v8 = (char *)malloc(v17);\n *a4 = 0;\n s1 = v8;\n if ( (int)v7 > 0 )\n {\n do\n {\n sub_1700(*a1, *v6, s2);\n v14 = *a4;\n v9 = *a4;\n if ( *a4 <= 0 )\n {\nLABEL_9:\n v12 = v17;\n if ( v17 < 104 * v9 )\n v12 = 104 * v9;\n v13 = v12 - 104 * v9;\n if ( v13 > 0x64 )\n v13 = 100LL;\n *(_DWORD *)(__strcpy_chk(&s1[104 * v9], s2, v13, &s1[104 * v9]) + 100) = 1;\n *a4 = v14 + 1;\n }\n else\n {\n v9 = v14;\n v10 = s1;\n while ( strcmp(v10, s2) )\n {\n v10 += 104;\n if ( v10 == &s1[104 * v14] )\n goto LABEL_9;\n }\n ++*((_DWORD *)v10 + 25);\n }\n ++v6;\n ++a1;\n }\n while ( v6 != &a2[v7] );\n }\n return s1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1B50(uint64_t *a1, unsigned int *a2, int a3, int *a4) {\n unsigned int *v6;\n long long v7;\n char *v8;\n long long v9;\n char *v10;\n long long v12;\n unsigned long long v13;\n int v14;\n char *s1;\n unsigned int v17;\n char s2[104];\n unsigned long long v19;\n v6 = a2;\n v7 = a3;\n v19 = __readfsqword(40u);\n v17 = 104LL * a3;\n v8 = (char *)malloc(v17);\n *a4 = 0;\n s1 = v8;\n if ((int)v7 > 0) {\n do {\n sub_1700(*a1, *v6, s2);\n v14 = *a4;\n v9 = *a4;\n if (*a4 <= 0) {\n LABEL_9:\n v12 = v17;\n if (v17 < 104 * v9) v12 = 104 * v9;\n v13 = v12 - 104 * v9;\n if (v13 > 100) v13 = 100LL;\n *(uint32_t *)(__strcpy_chk(&s1[104 * v9], s2, v13, &s1[104 * v9]) +\n 100) = 1;\n *a4 = v14 + 1;\n } else {\n v9 = v14;\n v10 = s1;\n while (strcmp(v10, s2)) {\n v10 += 104;\n if (v10 == &s1[104 * v14]) goto LABEL_9;\n }\n ++*((uint32_t *)v10 + 25);\n }\n ++v6;\n ++a1;\n } while (v6 != &a2[v7]);\n }\n return s1;\n}", + "ida_pseudo_norm": "char *func0(uint64_t *a1, unsigned int *a2, int a3, int *a4) {\n unsigned int *v6;\n long long v7;\n char *v8;\n long long v9;\n char *v10;\n long long v12;\n unsigned long long v13;\n int v14;\n char *s1;\n unsigned int v17;\n char s2[104];\n unsigned long long v19;\n v6 = a2;\n v7 = a3;\n v19 = __readfsqword(40u);\n v17 = 104LL * a3;\n v8 = (char *)malloc(v17);\n *a4 = 0;\n s1 = v8;\n if ((int)v7 > 0) {\n do {\n int_list_to_key(*a1, *v6, s2);\n v14 = *a4;\n v9 = *a4;\n if (*a4 <= 0) {\n LABEL_9:\n v12 = v17;\n if (v17 < 104 * v9) v12 = 104 * v9;\n v13 = v12 - 104 * v9;\n if (v13 > 100) v13 = 100LL;\n *(uint32_t *)(__strcpy_chk(&s1[104 * v9], s2, v13, &s1[104 * v9]) +\n 100) = 1;\n *a4 = v14 + 1;\n } else {\n v9 = v14;\n v10 = s1;\n while (strcmp(v10, s2)) {\n v10 += 104;\n if (v10 == &s1[104 * v14]) goto LABEL_9;\n }\n ++*((uint32_t *)v10 + 25);\n }\n ++v6;\n ++a1;\n } while (v6 != &a2[v7]);\n }\n return s1;\n}" + }, + { + "index": 780, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n} Pair;\n\n\n\n", + "func": "Pair *func0(Pair test_list[], int size) {\n Pair *res = (Pair *)malloc(sizeof(Pair) * size * (size - 1) / 2);\n int index = 0;\n for (int i = 0; i < size; i++) {\n for (int j = i + 1; j < size; j++) {\n res[index].first = test_list[i].first + test_list[j].first;\n res[index].second = test_list[i].second + test_list[j].second;\n index++;\n }\n }\n return res;\n}", + "test": "int main() {\n\n Pair test1[] = {{2, 4}, {6, 7}, {5, 1}, {6, 10}};\n\n Pair test2[] = {{3, 5}, {7, 8}, {6, 2}, {7, 11}};\n\n Pair test3[] = {{4, 6}, {8, 9}, {7, 3}, {8, 12}};\n\n \n\n Pair *result1 = func0(test1, 4);\n\n Pair expected1[] = {{8, 11}, {7, 5}, {8, 14}, {11, 8}, {12, 17}, {11, 11}};\n\n for (int i = 0; i < 6; i++)\n\n assert(result1[i].first == expected1[i].first && result1[i].second == expected1[i].second);\n\n \n\n Pair *result2 = func0(test2, 4);\n\n Pair expected2[] = {{10, 13}, {9, 7}, {10, 16}, {13, 10}, {14, 19}, {13, 13}};\n\n for (int i = 0; i < 6; i++)\n\n assert(result2[i].first == expected2[i].first && result2[i].second == expected2[i].second);\n\n \n\n Pair *result3 = func0(test3, 4);\n\n Pair expected3[] = {{12, 15}, {11, 9}, {12, 18}, {15, 12}, {16, 21}, {15, 15}};\n\n for (int i = 0; i < 6; i++)\n\n assert(result3[i].first == expected3[i].first && result3[i].second == expected3[i].second);\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmov -0x2c(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x2c(%rbp),%eax\nsub $0x1,%eax\ncltq\nimul %rdx,%rax\nshl $0x3,%rax\nshr %rax\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0x14(%rbp)\nmovl $0x0,-0x10(%rbp)\njmpq 12c5 \nmov -0x10(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0xc(%rbp)\njmpq 12b5 \nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%ecx\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rsi\nmov -0x8(%rbp),%rax\nadd %rsi,%rax\nadd %ecx,%edx\nmov %edx,(%rax)\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov 0x4(%rax),%ecx\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov 0x4(%rax),%edx\nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rsi\nmov -0x8(%rbp),%rax\nadd %rsi,%rax\nadd %ecx,%edx\nmov %edx,0x4(%rax)\naddl $0x1,-0x14(%rbp)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 1222 \naddl $0x1,-0x10(%rbp)\nmov -0x10(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 1214 \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov eax, [rbp+var_2C]\nmovsxd rdx, eax\nmov eax, [rbp+var_2C]\nsub eax, 1\ncdqe\nimul rax, rdx\nshl rax, 3\nshr rax, 1\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\njmp loc_12C5\nloc_1214:\nmov eax, [rbp+var_10]\nadd eax, 1\nmov [rbp+var_C], eax\njmp loc_12B5\nloc_1222:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov ecx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_14]\ncdqe\nlea rsi, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rsi\nadd edx, ecx\nmov [rax], edx\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov ecx, [rax+4]\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax+4]\nmov eax, [rbp+var_14]\ncdqe\nlea rsi, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rsi\nadd edx, ecx\nmov [rax+4], edx\nadd [rbp+var_14], 1\nadd [rbp+var_C], 1\nloc_12B5:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_2C]\njl loc_1222\nadd [rbp+var_10], 1\nloc_12C5:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_2C]\njl loc_1214\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2)\n{\n int v3; // [rsp+1Ch] [rbp-14h]\n int i; // [rsp+20h] [rbp-10h]\n int j; // [rsp+24h] [rbp-Ch]\n _DWORD *v6; // [rsp+28h] [rbp-8h]\n\n v6 = malloc((unsigned __int64)(8 * a2 * (__int64)(a2 - 1)) >> 1);\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n v6[2 * v3] = *(_DWORD *)(8LL * i + a1) + *(_DWORD *)(8LL * j + a1);\n v6[2 * v3++ + 1] = *(_DWORD *)(8LL * i + a1 + 4) + *(_DWORD *)(8LL * j + a1 + 4);\n }\n }\n return v6;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov eax, [rbp+var_2C]\nmovsxd rdx, eax\nmov eax, [rbp+var_2C]\nsub eax, 1\ncdqe\nimul rax, rdx\nshl rax, 3\nshr rax, 1\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\njmp loc_12C5\nloc_1214:\nmov eax, [rbp+var_10]\nadd eax, 1\nmov [rbp+var_C], eax\njmp loc_12B5\nloc_1222:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov ecx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_14]\ncdqe\nlea rsi, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rsi\nadd edx, ecx\nmov [rax], edx\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov ecx, [rax+4]\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax+4]\nmov eax, [rbp+var_14]\ncdqe\nlea rsi, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rsi\nadd edx, ecx\nmov [rax+4], edx\nadd [rbp+var_14], 1\nadd [rbp+var_C], 1\nloc_12B5:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_2C]\njl loc_1222\nadd [rbp+var_10], 1\nloc_12C5:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_2C]\njl loc_1214\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11C9(__int64 a1, int a2)\n{\n int v3; // [rsp+1Ch] [rbp-14h]\n int i; // [rsp+20h] [rbp-10h]\n int j; // [rsp+24h] [rbp-Ch]\n _DWORD *v6; // [rsp+28h] [rbp-8h]\n\n v6 = malloc((unsigned __int64)(8 * a2 * (__int64)(a2 - 1)) >> 1);\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n v6[2 * v3] = *(_DWORD *)(8LL * i + a1) + *(_DWORD *)(8LL * j + a1);\n v6[2 * v3++ + 1] = *(_DWORD *)(8LL * i + a1 + 4) + *(_DWORD *)(8LL * j + a1 + 4);\n }\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11C9(long long a1, int a2) {\n int v3;\n int i;\n int j;\n uint32_t *v6;\n v6 = malloc((unsigned long long)(8 * a2 * (long long)(a2 - 1)) >> 1);\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n v6[2 * v3] = *(uint32_t *)(8LL * i + a1) + *(uint32_t *)(8LL * j + a1);\n v6[2 * v3++ + 1] =\n *(uint32_t *)(8LL * i + a1 + 4) + *(uint32_t *)(8LL * j + a1 + 4);\n }\n }\n return v6;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2) {\n int v3;\n int i;\n int j;\n uint32_t *v6;\n v6 = malloc((unsigned long long)(8 * a2 * (long long)(a2 - 1)) >> 1);\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n v6[2 * v3] = *(uint32_t *)(8LL * i + a1) + *(uint32_t *)(8LL * j + a1);\n v6[2 * v3++ + 1] =\n *(uint32_t *)(8LL * i + a1 + 4) + *(uint32_t *)(8LL * j + a1 + 4);\n }\n }\n return v6;\n}" + }, + { + "index": 780, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n} Pair;\n\n\n\n", + "func": "Pair *func0(Pair test_list[], int size) {\n Pair *res = (Pair *)malloc(sizeof(Pair) * size * (size - 1) / 2);\n int index = 0;\n for (int i = 0; i < size; i++) {\n for (int j = i + 1; j < size; j++) {\n res[index].first = test_list[i].first + test_list[j].first;\n res[index].second = test_list[i].second + test_list[j].second;\n index++;\n }\n }\n return res;\n}", + "test": "int main() {\n\n Pair test1[] = {{2, 4}, {6, 7}, {5, 1}, {6, 10}};\n\n Pair test2[] = {{3, 5}, {7, 8}, {6, 2}, {7, 11}};\n\n Pair test3[] = {{4, 6}, {8, 9}, {7, 3}, {8, 12}};\n\n \n\n Pair *result1 = func0(test1, 4);\n\n Pair expected1[] = {{8, 11}, {7, 5}, {8, 14}, {11, 8}, {12, 17}, {11, 11}};\n\n for (int i = 0; i < 6; i++)\n\n assert(result1[i].first == expected1[i].first && result1[i].second == expected1[i].second);\n\n \n\n Pair *result2 = func0(test2, 4);\n\n Pair expected2[] = {{10, 13}, {9, 7}, {10, 16}, {13, 10}, {14, 19}, {13, 13}};\n\n for (int i = 0; i < 6; i++)\n\n assert(result2[i].first == expected2[i].first && result2[i].second == expected2[i].second);\n\n \n\n Pair *result3 = func0(test3, 4);\n\n Pair expected3[] = {{12, 15}, {11, 9}, {12, 18}, {15, 12}, {16, 21}, {15, 15}};\n\n for (int i = 0; i < 6; i++)\n\n assert(result3[i].first == expected3[i].first && result3[i].second == expected3[i].second);\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbp\nmov %esi,%ebx\nlea -0x1(%rsi),%edi\nmovslq %edi,%rdi\nmovslq %esi,%rax\nimul %rax,%rdi\nshl $0x3,%rdi\nshr %rdi\ncallq 10d0 \nmov %rax,%r12\ntest %ebx,%ebx\njle 1272 \nmov %rbp,%r10\nmov $0x0,%r11d\nmov $0x0,%eax\nlea -0x1(%rbx),%r15d\nlea 0x8(%r12),%r14\nlea 0x1(%rbx),%r13d\nadd $0x1,%r11d\ncmp %r11d,%ebx\nje 1272 \nmov (%r10),%r9d\nmov 0x4(%r10),%r8d\nmovslq %eax,%rsi\nlea (%r12,%rsi,8),%rdx\nmov %r11d,%ebp\nmov %r15d,%ecx\nsub %r11d,%ecx\nadd %rsi,%rcx\nlea (%r14,%rcx,8),%rdi\nmov %r10,%rcx\nmov %r9d,%esi\nadd 0x8(%rcx),%esi\nmov %esi,(%rdx)\nmov %r8d,%esi\nadd 0xc(%rcx),%esi\nmov %esi,0x4(%rdx)\nadd $0x8,%rcx\nadd $0x8,%rdx\ncmp %rdi,%rdx\njne 1245 \nmov %r13d,%edx\nsub %ebp,%edx\nlea -0x1(%rax,%rdx,1),%eax\nadd $0x8,%r10\njmp 121b \nmov %r12,%rax\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbp, rdi\nmov ebx, esi\nlea edi, [rsi-1]\nmovsxd rdi, edi\nmovsxd rax, esi\nimul rdi, rax\nshl rdi, 3\nshr rdi, 1; size\ncall _malloc\nmov r12, rax\ntest ebx, ebx\njle short loc_1265\nmov r9, rbp\nmov r10d, 0\nmov r11d, 0\nlea r14d, [rbx-1]\nlea r13, [rax+8]\nloc_1211:\nadd r10d, 1\ncmp ebx, r10d\njz short loc_1265\nmov r8d, [r9]\nmov edi, [r9+4]\nmovsxd rcx, r11d\nlea rax, [r12+rcx*8]\nmov ebp, r10d\nmov edx, r14d\nsub edx, r10d\nadd rdx, rcx\nlea rsi, [r13+rdx*8+0]\nmov rdx, r9\nloc_123C:\nmov ecx, r8d\nadd ecx, [rdx+8]\nmov [rax], ecx\nmov ecx, edi\nadd ecx, [rdx+0Ch]\nmov [rax+4], ecx\nadd rdx, 8\nadd rax, 8\ncmp rax, rsi\njnz short loc_123C\nadd r11d, ebx\nsub r11d, ebp\nadd r9, 8\njmp short loc_1211\nloc_1265:\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "char *__fastcall func0(_DWORD *a1, int a2)\n{\n char *v2; // rax\n char *v3; // r12\n int v5; // r10d\n int v6; // r11d\n char *v7; // r13\n int v8; // r8d\n int v9; // edi\n char *v10; // rax\n _DWORD *v11; // rdx\n\n v2 = (char *)malloc((unsigned __int64)(8 * a2 * (__int64)(a2 - 1)) >> 1);\n v3 = v2;\n if ( a2 > 0 )\n {\n v5 = 0;\n v6 = 0;\n v7 = v2 + 8;\n while ( a2 != ++v5 )\n {\n v8 = *a1;\n v9 = a1[1];\n v10 = &v3[8 * v6];\n v11 = a1;\n do\n {\n *(_DWORD *)v10 = v11[2] + v8;\n *((_DWORD *)v10 + 1) = v11[3] + v9;\n v11 += 2;\n v10 += 8;\n }\n while ( v10 != &v7[8 * v6 + 8 * (unsigned __int64)(unsigned int)(a2 - 1 - v5)] );\n v6 = a2 + v6 - v5;\n a1 += 2;\n }\n }\n return v3;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbp, rdi\nmov ebx, esi\nlea edi, [rsi-1]\nmovsxd rdi, edi\nmovsxd rax, esi\nimul rdi, rax\nshl rdi, 3\nshr rdi, 1; size\ncall _malloc\nmov r12, rax\ntest ebx, ebx\njle short loc_1265\nmov r9, rbp\nmov r10d, 0\nmov r11d, 0\nlea r14d, [rbx-1]\nlea r13, [rax+8]\nloc_1211:\nadd r10d, 1\ncmp ebx, r10d\njz short loc_1265\nmov r8d, [r9]\nmov edi, [r9+4]\nmovsxd rcx, r11d\nlea rax, [r12+rcx*8]\nmov ebp, r10d\nmov edx, r14d\nsub edx, r10d\nadd rdx, rcx\nlea rsi, [r13+rdx*8+0]\nmov rdx, r9\nloc_123C:\nmov ecx, r8d\nadd ecx, [rdx+8]\nmov [rax], ecx\nmov ecx, edi\nadd ecx, [rdx+0Ch]\nmov [rax+4], ecx\nadd rdx, 8\nadd rax, 8\ncmp rax, rsi\njnz short loc_123C\nadd r11d, ebx\nsub r11d, ebp\nadd r9, 8\njmp short loc_1211\nloc_1265:\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11C9(_DWORD *a1, int a2)\n{\n char *v2; // rax\n char *v3; // r12\n int v5; // r10d\n int v6; // r11d\n char *v7; // r13\n int v8; // r8d\n int v9; // edi\n char *v10; // rax\n _DWORD *v11; // rdx\n\n v2 = (char *)malloc((unsigned __int64)(8 * a2 * (__int64)(a2 - 1)) >> 1);\n v3 = v2;\n if ( a2 > 0 )\n {\n v5 = 0;\n v6 = 0;\n v7 = v2 + 8;\n while ( a2 != ++v5 )\n {\n v8 = *a1;\n v9 = a1[1];\n v10 = &v3[8 * v6];\n v11 = a1;\n do\n {\n *(_DWORD *)v10 = v11[2] + v8;\n *((_DWORD *)v10 + 1) = v11[3] + v9;\n v11 += 2;\n v10 += 8;\n }\n while ( v10 != &v7[8 * v6 + 8 * (unsigned __int64)(unsigned int)(a2 - 1 - v5)] );\n v6 = a2 + v6 - v5;\n a1 += 2;\n }\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11C9(uint32_t *a1, int a2) {\n char *v2;\n char *v3;\n int v5;\n int v6;\n char *v7;\n int v8;\n int v9;\n char *v10;\n uint32_t *v11;\n v2 = (char *)malloc((unsigned long long)(8 * a2 * (long long)(a2 - 1)) >> 1);\n v3 = v2;\n if (a2 > 0) {\n v5 = 0;\n v6 = 0;\n v7 = v2 + 8;\n while (a2 != ++v5) {\n v8 = *a1;\n v9 = a1[1];\n v10 = &v3[8 * v6];\n v11 = a1;\n do {\n *(uint32_t *)v10 = v11[2] + v8;\n *((uint32_t *)v10 + 1) = v11[3] + v9;\n v11 += 2;\n v10 += 8;\n } while (\n v10 !=\n &v7[8 * v6 + 8 * (unsigned long long)(unsigned int)(a2 - 1 - v5)]);\n v6 = a2 + v6 - v5;\n a1 += 2;\n }\n }\n return v3;\n}", + "ida_pseudo_norm": "char *func0(uint32_t *a1, int a2) {\n char *v2;\n char *v3;\n int v5;\n int v6;\n char *v7;\n int v8;\n int v9;\n char *v10;\n uint32_t *v11;\n v2 = (char *)malloc((unsigned long long)(8 * a2 * (long long)(a2 - 1)) >> 1);\n v3 = v2;\n if (a2 > 0) {\n v5 = 0;\n v6 = 0;\n v7 = v2 + 8;\n while (a2 != ++v5) {\n v8 = *a1;\n v9 = a1[1];\n v10 = &v3[8 * v6];\n v11 = a1;\n do {\n *(uint32_t *)v10 = v11[2] + v8;\n *((uint32_t *)v10 + 1) = v11[3] + v9;\n v11 += 2;\n v10 += 8;\n } while (\n v10 !=\n &v7[8 * v6 + 8 * (unsigned long long)(unsigned int)(a2 - 1 - v5)]);\n v6 = a2 + v6 - v5;\n a1 += 2;\n }\n }\n return v3;\n}" + }, + { + "index": 780, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n} Pair;\n\n\n\n", + "func": "Pair *func0(Pair test_list[], int size) {\n Pair *res = (Pair *)malloc(sizeof(Pair) * size * (size - 1) / 2);\n int index = 0;\n for (int i = 0; i < size; i++) {\n for (int j = i + 1; j < size; j++) {\n res[index].first = test_list[i].first + test_list[j].first;\n res[index].second = test_list[i].second + test_list[j].second;\n index++;\n }\n }\n return res;\n}", + "test": "int main() {\n\n Pair test1[] = {{2, 4}, {6, 7}, {5, 1}, {6, 10}};\n\n Pair test2[] = {{3, 5}, {7, 8}, {6, 2}, {7, 11}};\n\n Pair test3[] = {{4, 6}, {8, 9}, {7, 3}, {8, 12}};\n\n \n\n Pair *result1 = func0(test1, 4);\n\n Pair expected1[] = {{8, 11}, {7, 5}, {8, 14}, {11, 8}, {12, 17}, {11, 11}};\n\n for (int i = 0; i < 6; i++)\n\n assert(result1[i].first == expected1[i].first && result1[i].second == expected1[i].second);\n\n \n\n Pair *result2 = func0(test2, 4);\n\n Pair expected2[] = {{10, 13}, {9, 7}, {10, 16}, {13, 10}, {14, 19}, {13, 13}};\n\n for (int i = 0; i < 6; i++)\n\n assert(result2[i].first == expected2[i].first && result2[i].second == expected2[i].second);\n\n \n\n Pair *result3 = func0(test3, 4);\n\n Pair expected3[] = {{12, 15}, {11, 9}, {12, 18}, {15, 12}, {16, 21}, {15, 15}};\n\n for (int i = 0; i < 6; i++)\n\n assert(result3[i].first == expected3[i].first && result3[i].second == expected3[i].second);\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmovslq %esi,%rax\npush %r14\npush %r13\nmov %rdi,%r13\npush %r12\npush %rbp\nlea -0x1(%rax),%ebp\nmovslq %ebp,%rdi\npush %rbx\nmov %rax,%rbx\nimul %rax,%rdi\nshl $0x3,%rdi\nshr %rdi\ncallq 10d0 \nmov %rax,%r12\ntest %ebx,%ebx\njle 1603 \nxor %eax,%eax\nmov %r13,%r11\nlea 0x8(%r12),%r14\nxor %esi,%esi\nadd $0x1,%eax\nlea 0x1(%rbx),%r13d\ncmp %eax,%ebx\nje 1603 \nnopl 0x0(%rax)\nmov %ebp,%ecx\nmovslq %esi,%rdi\nmov (%r11),%r10d\nmov 0x4(%r11),%r9d\nsub %eax,%ecx\nlea (%r12,%rdi,8),%rdx\nadd %rdi,%rcx\nlea (%r14,%rcx,8),%r8\nmov %r11,%rcx\nnopl 0x0(%rax)\nmov 0x8(%rcx),%edi\nadd $0x8,%rdx\nadd $0x8,%rcx\nadd %r10d,%edi\nmov %edi,-0x8(%rdx)\nmov 0x4(%rcx),%edi\nadd %r9d,%edi\nmov %edi,-0x4(%rdx)\ncmp %r8,%rdx\njne 15d0 \nmov %r13d,%edx\nadd $0x8,%r11\nsub %eax,%edx\nadd $0x1,%eax\nlea -0x1(%rsi,%rdx,1),%esi\ncmp %eax,%ebx\njne 15b0 \npop %rbx\nmov %r12,%rax\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\n", + "ida_asm": "func0:\nendbr64\nmovsxd rax, esi\npush rbp\npush rbx\nmov rbx, rdi\nlea edi, [rax-1]\nmov rbp, rax\nmovsxd rdi, edi\nimul rdi, rax\nsub rsp, 8\nshl rdi, 3\nshr rdi, 1; size\ncall _malloc\nmov r9, rax\ntest ebp, ebp\njle short loc_14E8\nlea rcx, [rbx+8]\nxor r8d, r8d\nmov edi, 1\nmov r10d, 1\ncmp ebp, 1\njz short loc_14E8\nnop word ptr [rax+rax+00000000h]\nloc_14A0:\nmov edx, ebp\nmovsxd rax, r8d\nmovq xmm1, qword ptr [rcx-8]\nsub edx, edi\ncmp edi, ebp\nlea rsi, [r9+rax*8]\ncmovge rdx, r10\nxor eax, eax\nshl rdx, 3\nnop dword ptr [rax+00h]\nloc_14C0:\nmovq xmm0, qword ptr [rcx+rax]\npaddd xmm0, xmm1\nmovq qword ptr [rsi+rax], xmm0\nadd rax, 8\ncmp rdx, rax\njnz short loc_14C0\nadd r8d, ebp\nadd rcx, 8\nsub r8d, edi\nadd edi, 1\ncmp ebp, edi\njnz short loc_14A0\nloc_14E8:\nadd rsp, 8\nmov rax, r9\npop rbx\npop rbp\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2)\n{\n char *v2; // r9\n __int64 v3; // rcx\n int v4; // r8d\n int i; // edi\n __m128i v6; // xmm1\n __int64 v7; // rdx\n __int64 v8; // rax\n __int64 v9; // rdx\n\n v2 = (char *)malloc((unsigned __int64)(8 * a2 * (__int64)(a2 - 1)) >> 1);\n if ( a2 > 0 )\n {\n v3 = a1 + 8;\n v4 = 0;\n for ( i = 1; a2 != i; ++i )\n {\n v6 = _mm_loadl_epi64((const __m128i *)(v3 - 8));\n v7 = (unsigned int)(a2 - i);\n if ( i >= a2 )\n v7 = 1LL;\n v8 = 0LL;\n v9 = 8 * v7;\n do\n {\n *(_QWORD *)&v2[8 * v4 + v8] = _mm_add_epi32(_mm_loadl_epi64((const __m128i *)(v3 + v8)), v6).m128i_u64[0];\n v8 += 8LL;\n }\n while ( v9 != v8 );\n v3 += 8LL;\n v4 = a2 + v4 - i;\n }\n }\n return v2;\n}", + "ida_strip_asm": "sub_1450:\nendbr64\nmovsxd rax, esi\npush rbp\npush rbx\nmov rbx, rdi\nlea edi, [rax-1]\nmov rbp, rax\nmovsxd rdi, edi\nimul rdi, rax\nsub rsp, 8\nshl rdi, 3\nshr rdi, 1; size\ncall _malloc\nmov r9, rax\ntest ebp, ebp\njle short loc_14E8\nlea rcx, [rbx+8]\nxor r8d, r8d\nmov edi, 1\nmov r10d, 1\ncmp ebp, 1\njz short loc_14E8\nnop word ptr [rax+rax+00000000h]\nloc_14A0:\nmov edx, ebp\nmovsxd rax, r8d\nmovq xmm1, qword ptr [rcx-8]\nsub edx, edi\ncmp edi, ebp\nlea rsi, [r9+rax*8]\ncmovge rdx, r10\nxor eax, eax\nshl rdx, 3\nnop dword ptr [rax+00h]\nloc_14C0:\nmovq xmm0, qword ptr [rcx+rax]\npaddd xmm0, xmm1\nmovq qword ptr [rsi+rax], xmm0\nadd rax, 8\ncmp rdx, rax\njnz short loc_14C0\nadd r8d, ebp\nadd rcx, 8\nsub r8d, edi\nadd edi, 1\ncmp ebp, edi\njnz short loc_14A0\nloc_14E8:\nadd rsp, 8\nmov rax, r9\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1450(__int64 a1, int a2)\n{\n char *v2; // r9\n __int64 v3; // rcx\n int v4; // r8d\n int i; // edi\n __m128i v6; // xmm1\n __int64 v7; // rdx\n __int64 v8; // rax\n __int64 v9; // rdx\n\n v2 = (char *)malloc((unsigned __int64)(8 * a2 * (__int64)(a2 - 1)) >> 1);\n if ( a2 > 0 )\n {\n v3 = a1 + 8;\n v4 = 0;\n for ( i = 1; a2 != i; ++i )\n {\n v6 = _mm_loadl_epi64((const __m128i *)(v3 - 8));\n v7 = (unsigned int)(a2 - i);\n if ( i >= a2 )\n v7 = 1LL;\n v8 = 0LL;\n v9 = 8 * v7;\n do\n {\n *(_QWORD *)&v2[8 * v4 + v8] = _mm_add_epi32(_mm_loadl_epi64((const __m128i *)(v3 + v8)), v6).m128i_u64[0];\n v8 += 8LL;\n }\n while ( v9 != v8 );\n v3 += 8LL;\n v4 = a2 + v4 - i;\n }\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1450(long long a1, int a2) {\n char *v2;\n long long v3;\n int v4;\n int i;\n __m128i v6;\n long long v7;\n long long v8;\n long long v9;\n v2 = (char *)malloc((unsigned long long)(8 * a2 * (long long)(a2 - 1)) >> 1);\n if (a2 > 0) {\n v3 = a1 + 8;\n v4 = 0;\n for (i = 1; a2 != i; ++i) {\n v6 = _mm_loadl_epi64((const __m128i *)(v3 - 8));\n v7 = (unsigned int)(a2 - i);\n if (i >= a2) v7 = 1LL;\n v8 = 0LL;\n v9 = 8 * v7;\n do {\n *(uint64_t *)&v2[8 * v4 + v8] =\n _mm_add_epi32(_mm_loadl_epi64((const __m128i *)(v3 + v8)), v6)\n .m128i_u64[0];\n v8 += 8LL;\n } while (v9 != v8);\n v3 += 8LL;\n v4 = a2 + v4 - i;\n }\n }\n return v2;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2) {\n char *v2;\n long long v3;\n int v4;\n int i;\n __m128i v6;\n long long v7;\n long long v8;\n long long v9;\n v2 = (char *)malloc((unsigned long long)(8 * a2 * (long long)(a2 - 1)) >> 1);\n if (a2 > 0) {\n v3 = a1 + 8;\n v4 = 0;\n for (i = 1; a2 != i; ++i) {\n v6 = _mm_loadl_epi64((const __m128i *)(v3 - 8));\n v7 = (unsigned int)(a2 - i);\n if (i >= a2) v7 = 1LL;\n v8 = 0LL;\n v9 = 8 * v7;\n do {\n *(uint64_t *)&v2[8 * v4 + v8] =\n _mm_add_epi32(_mm_loadl_epi64((const __m128i *)(v3 + v8)), v6)\n .m128i_u64[0];\n v8 += 8LL;\n } while (v9 != v8);\n v3 += 8LL;\n v4 = a2 + v4 - i;\n }\n }\n return v2;\n}" + }, + { + "index": 780, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n} Pair;\n\n\n\n", + "func": "Pair *func0(Pair test_list[], int size) {\n Pair *res = (Pair *)malloc(sizeof(Pair) * size * (size - 1) / 2);\n int index = 0;\n for (int i = 0; i < size; i++) {\n for (int j = i + 1; j < size; j++) {\n res[index].first = test_list[i].first + test_list[j].first;\n res[index].second = test_list[i].second + test_list[j].second;\n index++;\n }\n }\n return res;\n}", + "test": "int main() {\n\n Pair test1[] = {{2, 4}, {6, 7}, {5, 1}, {6, 10}};\n\n Pair test2[] = {{3, 5}, {7, 8}, {6, 2}, {7, 11}};\n\n Pair test3[] = {{4, 6}, {8, 9}, {7, 3}, {8, 12}};\n\n \n\n Pair *result1 = func0(test1, 4);\n\n Pair expected1[] = {{8, 11}, {7, 5}, {8, 14}, {11, 8}, {12, 17}, {11, 11}};\n\n for (int i = 0; i < 6; i++)\n\n assert(result1[i].first == expected1[i].first && result1[i].second == expected1[i].second);\n\n \n\n Pair *result2 = func0(test2, 4);\n\n Pair expected2[] = {{10, 13}, {9, 7}, {10, 16}, {13, 10}, {14, 19}, {13, 13}};\n\n for (int i = 0; i < 6; i++)\n\n assert(result2[i].first == expected2[i].first && result2[i].second == expected2[i].second);\n\n \n\n Pair *result3 = func0(test3, 4);\n\n Pair expected3[] = {{12, 15}, {11, 9}, {12, 18}, {15, 12}, {16, 21}, {15, 15}};\n\n for (int i = 0; i < 6; i++)\n\n assert(result3[i].first == expected3[i].first && result3[i].second == expected3[i].second);\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nmovslq %esi,%rax\npush %r14\npush %r13\npush %r12\nlea -0x1(%rax),%r12d\npush %rbp\nmov %rax,%rbp\npush %rbx\nmov %rdi,%rbx\nmovslq %r12d,%rdi\nimul %rax,%rdi\nshl $0x3,%rdi\nshr %rdi\ncallq 10d0 \ncmp $0x1,%ebp\njle 16cb \nmov %r12d,%r10d\nlea 0x8(%rbx),%r8\nxor %esi,%esi\nmov $0x1,%r9d\nmov $0x1,%r11d\nnopw 0x0(%rax,%rax,1)\ncmp %r9d,%ebp\nmov %r11d,%r13d\nmov -0x8(%r8),%edi\nmov -0x4(%r8),%ecx\ncmovg %r10d,%r13d\njle 16d4 \ncmp $0x1,%r10d\nje 16d4 \nmovd %edi,%xmm1\nmovd %ecx,%xmm2\nmov %r13d,%r12d\nmovslq %esi,%rdx\npunpckldq %xmm2,%xmm1\nshr %r12d\nlea (%rax,%rdx,8),%r14\nxor %edx,%edx\npunpcklqdq %xmm1,%xmm1\nshl $0x4,%r12\nnopl (%rax)\nmovdqu (%r8,%rdx,1),%xmm0\npaddd %xmm1,%xmm0\nmovups %xmm0,(%r14,%rdx,1)\nadd $0x10,%rdx\ncmp %rdx,%r12\njne 1668 \nmov %r13d,%r14d\nand $0xfffffffe,%r14d\nlea (%rsi,%r14,1),%edx\nlea (%r9,%r14,1),%r12d\ncmp %r14d,%r13d\nje 16b3 \nmovslq %r12d,%r12\nmovslq %edx,%rdx\nlea (%rbx,%r12,8),%r13\nlea (%rax,%rdx,8),%r12\nadd 0x0(%r13),%edi\nadd 0x4(%r13),%ecx\nmov %edi,(%r12)\nmov %ecx,0x4(%r12)\nadd $0x1,%r9d\nadd %r10d,%esi\nadd $0x8,%r8\nsub $0x1,%r10d\ncmp %r9d,%ebp\njne 1620 \npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nmov %r9d,%r12d\nmov %esi,%edx\njmp 1694 \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmovsxd rax, esi\npush r14\npush r13\nlea r13d, [rax-1]\npush r12\nmov r12, rax\npush rbp\nmov rbp, rdi\nmovsxd rdi, r13d\nimul rdi, rax\npush rbx\nshl rdi, 3\nshr rdi, 1; size\ncall _malloc\nmov rbx, rax\ntest r12d, r12d\njle loc_1539\ncmp r12d, 1\njz loc_1539\nmov r8d, r13d\nlea rcx, [rbp+8]\nmov r14d, r12d\nmov r9d, 1\nxor r11d, r11d\nmov r13d, 1\nnop dword ptr [rax+rax+00h]\nloc_14C0:\ncmp r12d, r9d\nmov esi, r13d\nmovq xmm2, qword ptr [rcx-8]\ncmovg esi, r8d\njle short loc_1545\ncmp r8d, 1\njz short loc_1545\nmov edx, esi\nmovdqa xmm1, xmm2\nmovsxd r10, r11d\nxor eax, eax\nshr edx, 1\npunpcklqdq xmm1, xmm2\nlea rdi, [rbx+r10*8]\nshl rdx, 4\nloc_14F0:\nmovdqu xmm0, xmmword ptr [rcx+rax]\npaddd xmm0, xmm1\nmovups xmmword ptr [rdi+rax], xmm0\nadd rax, 10h\ncmp rdx, rax\njnz short loc_14F0\ntest sil, 1\njz short loc_1525\nand esi, 0FFFFFFFEh\nloc_150F:\nadd r10, rsi\nadd rsi, r9\nmovq xmm0, qword ptr [rbp+rsi*8+0]\npaddd xmm0, xmm2\nmovq qword ptr [rbx+r10*8], xmm0\nloc_1525:\nadd r9, 1\nadd r11d, r8d\nadd rcx, 8\nsub r8d, 1\ncmp r14, r9\njnz short loc_14C0\nloc_1539:\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1545:\nxor esi, esi\nmovsxd r10, r11d\njmp short loc_150F", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, int a2)\n{\n _QWORD *v3; // rbx\n unsigned int v4; // r8d\n __int64 v5; // rcx\n __int64 v6; // r9\n int v7; // r11d\n __m128i v8; // xmm2\n __int64 v9; // r10\n __int64 v10; // rax\n __m128i v11; // xmm1\n __int64 v12; // rsi\n\n v3 = malloc((unsigned __int64)(8 * a2 * (__int64)(a2 - 1)) >> 1);\n if ( a2 >= 2 )\n {\n v4 = a2 - 1;\n v5 = a1 + 8;\n v6 = 1LL;\n v7 = 0;\n do\n {\n v8 = _mm_loadl_epi64((const __m128i *)(v5 - 8));\n if ( a2 <= (int)v6 || v4 == 1 )\n {\n v12 = 0LL;\n v9 = v7;\n }\n else\n {\n v9 = v7;\n v10 = 0LL;\n v11 = _mm_unpacklo_epi64(v8, v8);\n do\n {\n *(__m128i *)&v3[v7 + v10] = _mm_add_epi32(_mm_loadu_si128((const __m128i *)(v5 + v10 * 8)), v11);\n v10 += 2LL;\n }\n while ( 2LL * (v4 >> 1) != v10 );\n if ( (v4 & 1) == 0 )\n goto LABEL_10;\n v12 = v4 & 0xFFFFFFFE;\n }\n v3[v12 + v9] = _mm_add_epi32(_mm_loadl_epi64((const __m128i *)(a1 + 8 * (v6 + v12))), v8).m128i_u64[0];\nLABEL_10:\n ++v6;\n v7 += v4;\n v5 += 8LL;\n --v4;\n }\n while ( a2 != v6 );\n }\n return v3;\n}", + "ida_strip_asm": "sub_1460:\nendbr64\nmovsxd rax, esi\npush r14\npush r13\nlea r13d, [rax-1]\npush r12\nmov r12, rax\npush rbp\nmov rbp, rdi\nmovsxd rdi, r13d\nimul rdi, rax\npush rbx\nshl rdi, 3\nshr rdi, 1; size\ncall _malloc\nmov rbx, rax\ntest r12d, r12d\njle loc_1539\ncmp r12d, 1\njz loc_1539\nmov r8d, r13d\nlea rcx, [rbp+8]\nmov r14d, r12d\nmov r9d, 1\nxor r11d, r11d\nmov r13d, 1\nnop dword ptr [rax+rax+00h]\nloc_14C0:\ncmp r12d, r9d\nmov esi, r13d\nmovq xmm2, qword ptr [rcx-8]\ncmovg esi, r8d\njle short loc_1545\ncmp r8d, 1\njz short loc_1545\nmov edx, esi\nmovdqa xmm1, xmm2\nmovsxd r10, r11d\nxor eax, eax\nshr edx, 1\npunpcklqdq xmm1, xmm2\nlea rdi, [rbx+r10*8]\nshl rdx, 4\nloc_14F0:\nmovdqu xmm0, xmmword ptr [rcx+rax]\npaddd xmm0, xmm1\nmovups xmmword ptr [rdi+rax], xmm0\nadd rax, 10h\ncmp rdx, rax\njnz short loc_14F0\ntest sil, 1\njz short loc_1525\nand esi, 0FFFFFFFEh\nloc_150F:\nadd r10, rsi\nadd rsi, r9\nmovq xmm0, qword ptr [rbp+rsi*8+0]\npaddd xmm0, xmm2\nmovq qword ptr [rbx+r10*8], xmm0\nloc_1525:\nadd r9, 1\nadd r11d, r8d\nadd rcx, 8\nsub r8d, 1\ncmp r14, r9\njnz short loc_14C0\nloc_1539:\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1545:\nxor esi, esi\nmovsxd r10, r11d\njmp short loc_150F", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1460(__int64 a1, int a2)\n{\n _QWORD *v3; // rbx\n unsigned int v4; // r8d\n __int64 v5; // rcx\n __int64 v6; // r9\n int v7; // r11d\n __m128i v8; // xmm2\n __int64 v9; // r10\n __int64 v10; // rax\n __m128i v11; // xmm1\n __int64 v12; // rsi\n\n v3 = malloc((unsigned __int64)(8 * a2 * (__int64)(a2 - 1)) >> 1);\n if ( a2 >= 2 )\n {\n v4 = a2 - 1;\n v5 = a1 + 8;\n v6 = 1LL;\n v7 = 0;\n do\n {\n v8 = _mm_loadl_epi64((const __m128i *)(v5 - 8));\n if ( a2 <= (int)v6 || v4 == 1 )\n {\n v12 = 0LL;\n v9 = v7;\n }\n else\n {\n v9 = v7;\n v10 = 0LL;\n v11 = _mm_unpacklo_epi64(v8, v8);\n do\n {\n *(__m128i *)&v3[v7 + v10] = _mm_add_epi32(_mm_loadu_si128((const __m128i *)(v5 + v10 * 8)), v11);\n v10 += 2LL;\n }\n while ( 2LL * (v4 >> 1) != v10 );\n if ( (v4 & 1) == 0 )\n goto LABEL_10;\n v12 = v4 & 0xFFFFFFFE;\n }\n v3[v12 + v9] = _mm_add_epi32(_mm_loadl_epi64((const __m128i *)(a1 + 8 * (v6 + v12))), v8).m128i_u64[0];\nLABEL_10:\n ++v6;\n v7 += v4;\n v5 += 8LL;\n --v4;\n }\n while ( a2 != v6 );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1460(long long a1, int a2) {\n uint64_t *v3;\n unsigned int v4;\n long long v5;\n long long v6;\n int v7;\n __m128i v8;\n long long v9;\n long long v10;\n __m128i v11;\n long long v12;\n v3 = malloc((unsigned long long)(8 * a2 * (long long)(a2 - 1)) >> 1);\n if (a2 >= 2) {\n v4 = a2 - 1;\n v5 = a1 + 8;\n v6 = 1LL;\n v7 = 0;\n do {\n v8 = _mm_loadl_epi64((const __m128i *)(v5 - 8));\n if (a2 <= (int)v6 || v4 == 1) {\n v12 = 0LL;\n v9 = v7;\n } else {\n v9 = v7;\n v10 = 0LL;\n v11 = _mm_unpacklo_epi64(v8, v8);\n do {\n *(__m128i *)&v3[v7 + v10] = _mm_add_epi32(\n _mm_loadu_si128((const __m128i *)(v5 + v10 * 8)), v11);\n v10 += 2LL;\n } while (2LL * (v4 >> 1) != v10);\n if ((v4 & 1) == 0) goto LABEL_10;\n v12 = v4 & 4294967294;\n }\n v3[v12 + v9] =\n _mm_add_epi32(_mm_loadl_epi64((const __m128i *)(a1 + 8 * (v6 + v12))),\n v8)\n .m128i_u64[0];\n LABEL_10:\n ++v6;\n v7 += v4;\n v5 += 8LL;\n --v4;\n } while (a2 != v6);\n }\n return v3;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, int a2) {\n uint64_t *v3;\n unsigned int v4;\n long long v5;\n long long v6;\n int v7;\n __m128i v8;\n long long v9;\n long long v10;\n __m128i v11;\n long long v12;\n v3 = malloc((unsigned long long)(8 * a2 * (long long)(a2 - 1)) >> 1);\n if (a2 >= 2) {\n v4 = a2 - 1;\n v5 = a1 + 8;\n v6 = 1LL;\n v7 = 0;\n do {\n v8 = _mm_loadl_epi64((const __m128i *)(v5 - 8));\n if (a2 <= (int)v6 || v4 == 1) {\n v12 = 0LL;\n v9 = v7;\n } else {\n v9 = v7;\n v10 = 0LL;\n v11 = _mm_unpacklo_epi64(v8, v8);\n do {\n *(__m128i *)&v3[v7 + v10] = _mm_add_epi32(\n _mm_loadu_si128((const __m128i *)(v5 + v10 * 8)), v11);\n v10 += 2LL;\n } while (2LL * (v4 >> 1) != v10);\n if ((v4 & 1) == 0) goto LABEL_10;\n v12 = v4 & 4294967294;\n }\n v3[v12 + v9] =\n _mm_add_epi32(_mm_loadl_epi64((const __m128i *)(a1 + 8 * (v6 + v12))),\n v8)\n .m128i_u64[0];\n LABEL_10:\n ++v6;\n v7 += v4;\n v5 += 8LL;\n --v4;\n } while (a2 != v6);\n }\n return v3;\n}" + }, + { + "index": 781, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n", + "func": "char* func0(int n) {\n int count = 0;\n for (int i = 1; i < ((int)sqrt(n)) + 2; i++) {\n if (n % i == 0) {\n if (n / i == i) {\n count++;\n } else {\n count += 2;\n }\n }\n }\n if (count % 2 == 0) {\n return \"Even\";\n } else {\n return \"Odd\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(10), \"Even\") == 0);\n\n assert(strcmp(func0(100), \"Odd\") == 0);\n\n assert(strcmp(func0(125), \"Even\") == 0);\n\n\n\n printf(\"All test cases passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %edi,-0x14(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x1,-0x4(%rbp)\njmp 11ef \nmov -0x14(%rbp),%eax\ncltd\nidivl -0x4(%rbp)\nmov %edx,%eax\ntest %eax,%eax\njne 11eb \nmov -0x14(%rbp),%eax\ncltd\nidivl -0x4(%rbp)\ncmp %eax,-0x4(%rbp)\njne 11e7 \naddl $0x1,-0x8(%rbp)\njmp 11eb \naddl $0x2,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\ncvtsi2sdl -0x14(%rbp),%xmm0\ncallq 10b0 \ncvttsd2si %xmm0,%eax\nadd $0x1,%eax\ncmp %eax,-0x4(%rbp)\njle 11c8 \nmov -0x8(%rbp),%eax\nand $0x1,%eax\ntest %eax,%eax\njne 1218 \nlea 0xdf2(%rip),%rax\njmp 121f \nlea 0xdee(%rip),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 1\njmp short loc_11EF\nloc_11C8:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njnz short loc_11EB\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\ncmp [rbp+var_4], eax\njnz short loc_11E7\nadd [rbp+var_8], 1\njmp short loc_11EB\nloc_11E7:\nadd [rbp+var_8], 2\nloc_11EB:\nadd [rbp+var_4], 1\nloc_11EF:\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_14]\nmovq rax, xmm1\nmovq xmm0, rax; x\ncall _sqrt\ncvttsd2si eax, xmm0\nadd eax, 1\ncmp [rbp+var_4], eax\njle short loc_11C8\nmov eax, [rbp+var_8]\nand eax, 1\ntest eax, eax\njnz short loc_1226\nlea rax, s2; \"Even\"\njmp short locret_122D\nloc_1226:\nlea rax, aOdd; \"Odd\"\nlocret_122D:\nleave\nretn", + "ida_pseudo": "const char *__fastcall func0(int a1)\n{\n int v2; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v2 = 0;\n for ( i = 1; i <= (int)sqrt((double)a1) + 1; ++i )\n {\n if ( !(a1 % i) )\n {\n if ( i == a1 / i )\n ++v2;\n else\n v2 += 2;\n }\n }\n if ( (v2 & 1) != 0 )\n return \"Odd\";\n else\n return \"Even\";\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 1\njmp short loc_11EF\nloc_11C8:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njnz short loc_11EB\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\ncmp [rbp+var_4], eax\njnz short loc_11E7\nadd [rbp+var_8], 1\njmp short loc_11EB\nloc_11E7:\nadd [rbp+var_8], 2\nloc_11EB:\nadd [rbp+var_4], 1\nloc_11EF:\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_14]\nmovq rax, xmm1\nmovq xmm0, rax; x\ncall _sqrt\ncvttsd2si eax, xmm0\nadd eax, 1\ncmp [rbp+var_4], eax\njle short loc_11C8\nmov eax, [rbp+var_8]\nand eax, 1\ntest eax, eax\njnz short loc_1226\nlea rax, s2; \"Even\"\njmp short locret_122D\nloc_1226:\nlea rax, aOdd; \"Odd\"\nlocret_122D:\nleave\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_11A9(int a1)\n{\n int v2; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v2 = 0;\n for ( i = 1; i <= (int)sqrt((double)a1) + 1; ++i )\n {\n if ( !(a1 % i) )\n {\n if ( i == a1 / i )\n ++v2;\n else\n v2 += 2;\n }\n }\n if ( (v2 & 1) != 0 )\n return \"Odd\";\n else\n return \"Even\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char* sub_11A9(int a1) {\n int v2;\n int i;\n v2 = 0;\n for (i = 1; i <= (int)sqrt((double)a1) + 1; ++i) {\n if (!(a1 % i)) {\n if (i == a1 / i)\n ++v2;\n else\n v2 += 2;\n }\n }\n if ((v2 & 1) != 0)\n return \"Odd\";\n else\n return \"Even\";\n}", + "ida_pseudo_norm": "const char* func0(int a1) {\n int v2;\n int i;\n v2 = 0;\n for (i = 1; i <= (int)sqrt((double)a1) + 1; ++i) {\n if (!(a1 % i)) {\n if (i == a1 / i)\n ++v2;\n else\n v2 += 2;\n }\n }\n if ((v2 & 1) != 0)\n return \"Odd\";\n else\n return \"Even\";\n}" + }, + { + "index": 781, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n", + "func": "char* func0(int n) {\n int count = 0;\n for (int i = 1; i < ((int)sqrt(n)) + 2; i++) {\n if (n % i == 0) {\n if (n / i == i) {\n count++;\n } else {\n count += 2;\n }\n }\n }\n if (count % 2 == 0) {\n return \"Even\";\n } else {\n return \"Odd\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(10), \"Even\") == 0);\n\n assert(strcmp(func0(100), \"Odd\") == 0);\n\n assert(strcmp(func0(125), \"Even\") == 0);\n\n\n\n printf(\"All test cases passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov %edi,%ebp\npxor %xmm3,%xmm3\ncvtsi2sd %edi,%xmm3\nmovsd %xmm3,0x8(%rsp)\nmovapd %xmm3,%xmm0\nsqrtsd %xmm0,%xmm0\ncvttsd2si %xmm0,%r13d\nadd $0x1,%r13d\nmov $0x1,%ebx\nmov $0x0,%r12d\njmp 11c8 \nadd $0x1,%ebx\npxor %xmm1,%xmm1\nucomisd 0x8(%rsp),%xmm1\nja 11fb \ncmp %ebx,%r13d\njl 1208 \nmov %ebp,%eax\ncltd\nidiv %ebx\ntest %edx,%edx\njne 11c5 \nmov %ebp,%eax\ncltd\nidiv %ebx\nmov %r12d,%edx\ncmp %ebx,%eax\nsetne %r12b\nmovzbl %r12b,%r12d\nlea 0x1(%r12,%rdx,1),%r12d\njmp 11c5 \nmovsd 0x8(%rsp),%xmm0\ncallq 1090 \njmp 11d4 \ntest $0x1,%r12b\nlea 0xdf1(%rip),%rax\nlea 0xdef(%rip),%rdx\ncmovne %rdx,%rax\nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 10h\nmov ebp, edi\nmov ebx, 1\nmov r12d, 0\npxor xmm2, xmm2\ncvtsi2sd xmm2, edi\nmovsd [rsp+28h+x], xmm2\njmp short loc_11D5\nloc_11D2:\nadd ebx, 1\nloc_11D5:\npxor xmm0, xmm0\nmovsd xmm1, [rsp+28h+x]\nucomisd xmm0, xmm1\nja short loc_121A\nmovapd xmm0, xmm1\nsqrtsd xmm0, xmm0\nloc_11ED:\ncvttsd2si edx, xmm0\nadd edx, 1\ncmp edx, ebx\njl short loc_1227\nmov eax, ebp\ncdq\nidiv ebx\ntest edx, edx\njnz short loc_11D2\nmov eax, ebp\ncdq\nidiv ebx\nmov edx, r12d\ncmp eax, ebx\nsetnz r12b\nmovzx r12d, r12b\nlea r12d, [r12+rdx+1]\njmp short loc_11D2\nloc_121A:\nmovsd xmm0, [rsp+28h+x]; x\ncall _sqrt\njmp short loc_11ED\nloc_1227:\ntest r12b, 1\nlea rax, aOdd; \"Odd\"\nlea rdx, s2; \"Even\"\ncmovz rax, rdx\nadd rsp, 10h\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "const char *__fastcall func0(int a1)\n{\n int v1; // ebx\n char v2; // r12\n double v3; // xmm0_8\n const char *result; // rax\n double x; // [rsp+8h] [rbp-20h]\n\n v1 = 1;\n v2 = 0;\n x = (double)a1;\n while ( 1 )\n {\n v3 = x < 0.0 ? sqrt(x) : sqrt(x);\n if ( (int)v3 + 1 < v1 )\n break;\n if ( !(a1 % v1) )\n v2 += (a1 / v1 != v1) + 1;\n ++v1;\n }\n result = \"Odd\";\n if ( (v2 & 1) == 0 )\n return \"Even\";\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 10h\nmov ebp, edi\nmov ebx, 1\nmov r12d, 0\npxor xmm2, xmm2\ncvtsi2sd xmm2, edi\nmovsd [rsp+28h+x], xmm2\njmp short loc_11D5\nloc_11D2:\nadd ebx, 1\nloc_11D5:\npxor xmm0, xmm0\nmovsd xmm1, [rsp+28h+x]\nucomisd xmm0, xmm1\nja short loc_121A\nmovapd xmm0, xmm1\nsqrtsd xmm0, xmm0\nloc_11ED:\ncvttsd2si edx, xmm0\nadd edx, 1\ncmp edx, ebx\njl short loc_1227\nmov eax, ebp\ncdq\nidiv ebx\ntest edx, edx\njnz short loc_11D2\nmov eax, ebp\ncdq\nidiv ebx\nmov edx, r12d\ncmp eax, ebx\nsetnz r12b\nmovzx r12d, r12b\nlea r12d, [r12+rdx+1]\njmp short loc_11D2\nloc_121A:\nmovsd xmm0, [rsp+28h+x]; x\ncall _sqrt\njmp short loc_11ED\nloc_1227:\ntest r12b, 1\nlea rax, aOdd; \"Odd\"\nlea rdx, s2; \"Even\"\ncmovz rax, rdx\nadd rsp, 10h\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_11A9(int a1)\n{\n int v1; // ebx\n char v2; // r12\n double v3; // xmm0_8\n const char *result; // rax\n double x; // [rsp+8h] [rbp-20h]\n\n v1 = 1;\n v2 = 0;\n x = (double)a1;\n while ( 1 )\n {\n v3 = x < 0.0 ? sqrt(x) : sqrt(x);\n if ( (int)v3 + 1 < v1 )\n break;\n if ( !(a1 % v1) )\n v2 += (a1 / v1 != v1) + 1;\n ++v1;\n }\n result = \"Odd\";\n if ( (v2 & 1) == 0 )\n return \"Even\";\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_11A9(int a1) {\n int v1;\n char v2;\n double v3;\n const char *result;\n double x;\n v1 = 1;\n v2 = 0;\n x = (double)a1;\n while (1) {\n v3 = x < 0.0 ? sqrt(x) : sqrt(x);\n if ((int)v3 + 1 < v1) break;\n if (!(a1 % v1)) v2 += (a1 / v1 != v1) + 1;\n ++v1;\n }\n result = \"Odd\";\n if ((v2 & 1) == 0) return \"Even\";\n return result;\n}", + "ida_pseudo_norm": "const char *func0(int a1) {\n int v1;\n char v2;\n double v3;\n const char *result;\n double x;\n v1 = 1;\n v2 = 0;\n x = (double)a1;\n while (1) {\n v3 = x < 0.0 ? sqrt(x) : sqrt(x);\n if ((int)v3 + 1 < v1) break;\n if (!(a1 % v1)) v2 += (a1 / v1 != v1) + 1;\n ++v1;\n }\n result = \"Odd\";\n if ((v2 & 1) == 0) return \"Even\";\n return result;\n}" + }, + { + "index": 781, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n", + "func": "char* func0(int n) {\n int count = 0;\n for (int i = 1; i < ((int)sqrt(n)) + 2; i++) {\n if (n % i == 0) {\n if (n / i == i) {\n count++;\n } else {\n count += 2;\n }\n }\n }\n if (count % 2 == 0) {\n return \"Even\";\n } else {\n return \"Odd\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(10), \"Even\") == 0);\n\n assert(strcmp(func0(100), \"Odd\") == 0);\n\n assert(strcmp(func0(125), \"Even\") == 0);\n\n\n\n printf(\"All test cases passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npxor %xmm1,%xmm1\npush %r12\npxor %xmm2,%xmm2\ncvtsi2sd %edi,%xmm1\npush %rbp\nxor %ebp,%ebp\npush %rbx\nmov $0x1,%ebx\nmovapd %xmm1,%xmm0\nsub $0x10,%rsp\nsqrtsd %xmm0,%xmm0\ncvttsd2si %xmm0,%r12d\nadd $0x1,%r12d\njmp 12c2 \nnopw 0x0(%rax,%rax,1)\nmov %edi,%eax\ncltd\nidiv %ebx\ntest %edx,%edx\njne 12bf \nmov %ebp,%edx\nxor %ebp,%ebp\ncmp %ebx,%eax\nsetne %bpl\nlea 0x1(%rbp,%rdx,1),%ebp\nadd $0x1,%ebx\nucomisd %xmm1,%xmm2\nja 12eb \ncmp %ebx,%r12d\njge 12a8 \nand $0x1,%ebp\nlea 0xd2d(%rip),%rax\nlea 0xd2b(%rip),%rdx\ncmovne %rdx,%rax\nadd $0x10,%rsp\npop %rbx\npop %rbp\npop %r12\nretq\nmovapd %xmm1,%xmm0\nmov %edi,0xc(%rsp)\nmovsd %xmm1,(%rsp)\ncallq 1090 \nmov 0xc(%rsp),%edi\nmovsd (%rsp),%xmm1\npxor %xmm2,%xmm2\njmp 12c8 \nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\npxor xmm1, xmm1\nxor ebp, ebp\npxor xmm2, xmm2\npush rbx\ncvtsi2sd xmm1, edi\nmov ebx, 1\nsub rsp, 18h\njmp short loc_12BA\nloc_12A0:\nmov eax, edi\ncdq\nidiv ebx\ntest edx, edx\njnz short loc_12B7\nmov edx, ebp\nxor ebp, ebp\ncmp eax, ebx\nsetnz bpl\nlea ebp, [rbp+rdx+1]\nloc_12B7:\nadd ebx, 1\nloc_12BA:\nucomisd xmm2, xmm1\nja short loc_12EF\nmovapd xmm0, xmm1\nsqrtsd xmm0, xmm0\nloc_12C8:\ncvttsd2si edx, xmm0\nadd edx, 1\ncmp edx, ebx\njge short loc_12A0\nand ebp, 1\nlea rax, aOdd; \"Odd\"\nlea rdx, s2; \"Even\"\ncmovz rax, rdx\nadd rsp, 18h\npop rbx\npop rbp\nretn\nloc_12EF:\nmovapd xmm0, xmm1; x\nmov [rsp+28h+var_1C], edi\nmovsd [rsp+28h+var_28], xmm1\ncall _sqrt\nmov edi, [rsp+28h+var_1C]\nmovsd xmm1, [rsp+28h+var_28]\npxor xmm2, xmm2\njmp short loc_12C8", + "ida_pseudo": "const char *__fastcall func0(int a1)\n{\n char v1; // bp\n double v2; // xmm1_8\n int i; // ebx\n double v4; // xmm0_8\n const char *result; // rax\n\n v1 = 0;\n v2 = (double)a1;\n for ( i = 1; ; ++i )\n {\n v4 = v2 < 0.0 ? sqrt(v2) : sqrt(v2);\n if ( (int)v4 + 1 < i )\n break;\n if ( !(a1 % i) )\n v1 += (a1 / i != i) + 1;\n }\n result = \"Odd\";\n if ( (v1 & 1) == 0 )\n return \"Even\";\n return result;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\npush rbp\npxor xmm1, xmm1\nxor ebp, ebp\npxor xmm2, xmm2\npush rbx\ncvtsi2sd xmm1, edi\nmov ebx, 1\nsub rsp, 18h\njmp short loc_12BA\nloc_12A0:\nmov eax, edi\ncdq\nidiv ebx\ntest edx, edx\njnz short loc_12B7\nmov edx, ebp\nxor ebp, ebp\ncmp eax, ebx\nsetnz bpl\nlea ebp, [rbp+rdx+1]\nloc_12B7:\nadd ebx, 1\nloc_12BA:\nucomisd xmm2, xmm1\nja short loc_12EF\nmovapd xmm0, xmm1\nsqrtsd xmm0, xmm0\nloc_12C8:\ncvttsd2si edx, xmm0\nadd edx, 1\ncmp edx, ebx\njge short loc_12A0\nand ebp, 1\nlea rax, aOdd; \"Odd\"\nlea rdx, s2; \"Even\"\ncmovz rax, rdx\nadd rsp, 18h\npop rbx\npop rbp\nretn\nloc_12EF:\nmovapd xmm0, xmm1; x\nmov [rsp+28h+var_1C], edi\nmovsd [rsp+28h+var_28], xmm1\ncall _sqrt\nmov edi, [rsp+28h+var_1C]\nmovsd xmm1, [rsp+28h+var_28]\npxor xmm2, xmm2\njmp short loc_12C8", + "ida_strip_pseudo": "const char *__fastcall sub_1280(int a1)\n{\n char v1; // bp\n double v2; // xmm1_8\n int i; // ebx\n double v4; // xmm0_8\n const char *result; // rax\n\n v1 = 0;\n v2 = (double)a1;\n for ( i = 1; ; ++i )\n {\n v4 = v2 < 0.0 ? sqrt(v2) : sqrt(v2);\n if ( (int)v4 + 1 < i )\n break;\n if ( !(a1 % i) )\n v1 += (a1 / i != i) + 1;\n }\n result = \"Odd\";\n if ( (v1 & 1) == 0 )\n return \"Even\";\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1280(int a1) {\n char v1;\n double v2;\n int i;\n double v4;\n const char *result;\n v1 = 0;\n v2 = (double)a1;\n for (i = 1;; ++i) {\n v4 = v2 < 0.0 ? sqrt(v2) : sqrt(v2);\n if ((int)v4 + 1 < i) break;\n if (!(a1 % i)) v1 += (a1 / i != i) + 1;\n }\n result = \"Odd\";\n if ((v1 & 1) == 0) return \"Even\";\n return result;\n}", + "ida_pseudo_norm": "const char *func0(int a1) {\n char v1;\n double v2;\n int i;\n double v4;\n const char *result;\n v1 = 0;\n v2 = (double)a1;\n for (i = 1;; ++i) {\n v4 = v2 < 0.0 ? sqrt(v2) : sqrt(v2);\n if ((int)v4 + 1 < i) break;\n if (!(a1 % i)) v1 += (a1 / i != i) + 1;\n }\n result = \"Odd\";\n if ((v1 & 1) == 0) return \"Even\";\n return result;\n}" + }, + { + "index": 781, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n", + "func": "char* func0(int n) {\n int count = 0;\n for (int i = 1; i < ((int)sqrt(n)) + 2; i++) {\n if (n % i == 0) {\n if (n / i == i) {\n count++;\n } else {\n count += 2;\n }\n }\n }\n if (count % 2 == 0) {\n return \"Even\";\n } else {\n return \"Odd\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(10), \"Even\") == 0);\n\n assert(strcmp(func0(100), \"Odd\") == 0);\n\n assert(strcmp(func0(125), \"Even\") == 0);\n\n\n\n printf(\"All test cases passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npxor %xmm1,%xmm1\npush %r12\ncvtsi2sd %edi,%xmm1\npush %rbp\npush %rbx\nmovapd %xmm1,%xmm0\nsub $0x10,%rsp\nsqrtsd %xmm0,%xmm0\ncvttsd2si %xmm0,%esi\npxor %xmm0,%xmm0\nucomisd %xmm1,%xmm0\nlea 0x1(%rsi),%ebp\nja 12f3 \nadd $0x2,%esi\nmov $0x1,%ecx\nxor %ebx,%ebx\nlea 0xd56(%rip),%rax\ntest %ebp,%ebp\njle 12ea \nnopw 0x0(%rax,%rax,1)\nmov %edi,%eax\ncltd\nidiv %ecx\ntest %edx,%edx\njne 12ce \nmov %ebx,%edx\nxor %ebx,%ebx\ncmp %ecx,%eax\nsetne %bl\nlea 0x1(%rbx,%rdx,1),%ebx\nadd $0x1,%ecx\ncmp %esi,%ecx\njne 12b8 \nand $0x1,%ebx\nlea 0xd25(%rip),%rax\nlea 0xd23(%rip),%rdx\ncmovne %rdx,%rax\nadd $0x10,%rsp\npop %rbx\npop %rbp\npop %r12\nretq\nmov $0x1,%r12d\nxor %ebx,%ebx\njmp 1322 \nmov 0xc(%rsp),%edi\nmovsd (%rsp),%xmm1\nmov %edi,%eax\ncltd\nidiv %r12d\ntest %edx,%edx\njne 131e \nmov %ebx,%edx\nxor %ebx,%ebx\ncmp %eax,%r12d\nsetne %bl\nlea 0x1(%rbx,%rdx,1),%ebx\nadd $0x1,%r12d\nmovapd %xmm1,%xmm0\nmov %edi,0xc(%rsp)\nmovsd %xmm1,(%rsp)\ncallq 1090 \ncmp %r12d,%ebp\njge 12fd \njmp 12d5 \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npxor xmm1, xmm1\npush r12\npxor xmm0, xmm0\ncvtsi2sd xmm1, edi\npush rbp\nsub rsp, 18h\nucomisd xmm0, xmm1\nja short loc_12FF\nsqrtsd xmm1, xmm1\nmov ecx, 1\nxor ebp, ebp\ncvttsd2si esi, xmm1\ntest esi, esi\njns short loc_12BA\njmp short loc_12F0\nloc_12B8:\nmov ecx, eax\nloc_12BA:\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_12D1\nmov edx, ebp\nxor ebp, ebp\ncmp eax, ecx\nsetnz bpl\nlea ebp, [rbp+rdx+1]\nloc_12D1:\nlea eax, [rcx+1]\ncmp esi, ecx\njge short loc_12B8\nloc_12D8:\nand ebp, 1\nlea rax, aOdd; \"Odd\"\njz short loc_12F0\nadd rsp, 18h\npop rbp\npop r12\nretn\nloc_12F0:\nadd rsp, 18h\nlea rax, s2; \"Even\"\npop rbp\npop r12\nretn\nloc_12FF:\nmov r12d, 1\nxor ebp, ebp\njmp short loc_132F\nloc_1309:\nmov edi, [rsp+28h+var_1C]\nmovsd xmm1, [rsp+28h+var_28]\nmov eax, edi\ncdq\nidiv r12d\ntest edx, edx\njnz short loc_132B\nmov edx, ebp\nxor ebp, ebp\ncmp r12d, eax\nsetnz bpl\nlea ebp, [rbp+rdx+1]\nloc_132B:\nadd r12d, 1\nloc_132F:\nmovapd xmm0, xmm1; x\nmov [rsp+28h+var_1C], edi\nmovsd [rsp+28h+var_28], xmm1\ncall _sqrt\ncvttsd2si eax, xmm0\nadd eax, 1\ncmp r12d, eax\njle short loc_1309\njmp short loc_12D8", + "ida_pseudo": "const char *__fastcall func0(int a1)\n{\n double v1; // xmm1_8\n int v2; // ecx\n char v3; // bp\n int v4; // esi\n const char *result; // rax\n int v6; // r12d\n\n v1 = (double)a1;\n if ( (double)a1 < 0.0 )\n {\n v6 = 1;\n v3 = 0;\n while ( v6 <= (int)sqrt(v1) + 1 )\n {\n if ( !(a1 % v6) )\n v3 += (v6 != a1 / v6) + 1;\n ++v6;\n }\nLABEL_8:\n result = \"Odd\";\n if ( (v3 & 1) != 0 )\n return result;\n return \"Even\";\n }\n v2 = 1;\n v3 = 0;\n v4 = (int)sqrt(v1);\n if ( v4 >= 0 )\n {\n while ( 1 )\n {\n if ( !(a1 % v2) )\n v3 += (a1 / v2 != v2) + 1;\n if ( v4 < v2 )\n break;\n ++v2;\n }\n goto LABEL_8;\n }\n return \"Even\";\n}", + "ida_strip_asm": "sub_1280:\nendbr64\npxor xmm1, xmm1\npush r12\npxor xmm0, xmm0\ncvtsi2sd xmm1, edi\npush rbp\nsub rsp, 18h\nucomisd xmm0, xmm1\nja short loc_12FF\nsqrtsd xmm1, xmm1\nmov ecx, 1\nxor ebp, ebp\ncvttsd2si esi, xmm1\ntest esi, esi\njns short loc_12BA\njmp short loc_12F0\nloc_12B8:\nmov ecx, eax\nloc_12BA:\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_12D1\nmov edx, ebp\nxor ebp, ebp\ncmp eax, ecx\nsetnz bpl\nlea ebp, [rbp+rdx+1]\nloc_12D1:\nlea eax, [rcx+1]\ncmp esi, ecx\njge short loc_12B8\nloc_12D8:\nand ebp, 1\nlea rax, aOdd; \"Odd\"\njz short loc_12F0\nadd rsp, 18h\npop rbp\npop r12\nretn\nloc_12F0:\nadd rsp, 18h\nlea rax, s2; \"Even\"\npop rbp\npop r12\nretn\nloc_12FF:\nmov r12d, 1\nxor ebp, ebp\njmp short loc_132F\nloc_1309:\nmov edi, [rsp+28h+var_1C]\nmovsd xmm1, [rsp+28h+var_28]\nmov eax, edi\ncdq\nidiv r12d\ntest edx, edx\njnz short loc_132B\nmov edx, ebp\nxor ebp, ebp\ncmp r12d, eax\nsetnz bpl\nlea ebp, [rbp+rdx+1]\nloc_132B:\nadd r12d, 1\nloc_132F:\nmovapd xmm0, xmm1; x\nmov [rsp+28h+var_1C], edi\nmovsd [rsp+28h+var_28], xmm1\ncall _sqrt\ncvttsd2si eax, xmm0\nadd eax, 1\ncmp r12d, eax\njle short loc_1309\njmp short loc_12D8", + "ida_strip_pseudo": "const char *__fastcall sub_1280(int a1)\n{\n double v1; // xmm1_8\n int v2; // ecx\n char v3; // bp\n int v4; // esi\n const char *result; // rax\n int v6; // r12d\n\n v1 = (double)a1;\n if ( (double)a1 < 0.0 )\n {\n v6 = 1;\n v3 = 0;\n while ( v6 <= (int)sqrt(v1) + 1 )\n {\n if ( !(a1 % v6) )\n v3 += (v6 != a1 / v6) + 1;\n ++v6;\n }\nLABEL_8:\n result = \"Odd\";\n if ( (v3 & 1) != 0 )\n return result;\n return \"Even\";\n }\n v2 = 1;\n v3 = 0;\n v4 = (int)sqrt(v1);\n if ( v4 >= 0 )\n {\n while ( 1 )\n {\n if ( !(a1 % v2) )\n v3 += (a1 / v2 != v2) + 1;\n if ( v4 < v2 )\n break;\n ++v2;\n }\n goto LABEL_8;\n }\n return \"Even\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1280(int a1) {\n double v1;\n int v2;\n char v3;\n int v4;\n const char *result;\n int v6;\n v1 = (double)a1;\n if ((double)a1 < 0.0) {\n v6 = 1;\n v3 = 0;\n while (v6 <= (int)sqrt(v1) + 1) {\n if (!(a1 % v6)) v3 += (v6 != a1 / v6) + 1;\n ++v6;\n }\n LABEL_8:\n result = \"Odd\";\n if ((v3 & 1) != 0) return result;\n return \"Even\";\n }\n v2 = 1;\n v3 = 0;\n v4 = (int)sqrt(v1);\n if (v4 >= 0) {\n while (1) {\n if (!(a1 % v2)) v3 += (a1 / v2 != v2) + 1;\n if (v4 < v2) break;\n ++v2;\n }\n goto LABEL_8;\n }\n return \"Even\";\n}", + "ida_pseudo_norm": "const char *func0(int a1) {\n double v1;\n int v2;\n char v3;\n int v4;\n const char *result;\n int v6;\n v1 = (double)a1;\n if ((double)a1 < 0.0) {\n v6 = 1;\n v3 = 0;\n while (v6 <= (int)sqrt(v1) + 1) {\n if (!(a1 % v6)) v3 += (v6 != a1 / v6) + 1;\n ++v6;\n }\n LABEL_8:\n result = \"Odd\";\n if ((v3 & 1) != 0) return result;\n return \"Even\";\n }\n v2 = 1;\n v3 = 0;\n v4 = (int)sqrt(v1);\n if (v4 >= 0) {\n while (1) {\n if (!(a1 % v2)) v3 += (a1 / v2 != v2) + 1;\n if (v4 < v2) break;\n ++v2;\n }\n goto LABEL_8;\n }\n return \"Even\";\n}" + }, + { + "index": 782, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int l) {\n int Sum = 0;\n for (int i = 0; i < l; i++) {\n Sum += ((((i + 1) * (l - i) + 1) / 2) * arr[i]);\n }\n return Sum;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 4};\n\n int arr2[] = {1, 2, 1, 2};\n\n int arr3[] = {1, 7};\n\n assert(func0(arr1, 3) == 14);\n\n assert(func0(arr2, 4) == 15);\n\n assert(func0(arr3, 2) == 8);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11c5 \nmov -0x4(%rbp),%eax\nlea 0x1(%rax),%edx\nmov -0x1c(%rbp),%eax\nsub -0x4(%rbp),%eax\nimul %edx,%eax\nadd $0x1,%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nmov %eax,%ecx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nimul %ecx,%eax\nadd %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1188 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11C5\nloc_1188:\nmov eax, [rbp+var_4]\nlea edx, [rax+1]\nmov eax, [rbp+var_1C]\nsub eax, [rbp+var_4]\nimul eax, edx\nadd eax, 1\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov ecx, eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nimul eax, ecx\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_11C5:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n v3 += ((i + 1) * (a2 - i) + 1) / 2 * *(_DWORD *)(4LL * i + a1);\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11C5\nloc_1188:\nmov eax, [rbp+var_4]\nlea edx, [rax+1]\nmov eax, [rbp+var_1C]\nsub eax, [rbp+var_4]\nimul eax, edx\nadd eax, 1\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov ecx, eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nimul eax, ecx\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_11C5:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n v3 += ((i + 1) * (a2 - i) + 1) / 2 * *(_DWORD *)(4LL * i + a1);\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i)\n v3 += ((i + 1) * (a2 - i) + 1) / 2 * *(uint32_t *)(4LL * i + a1);\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i)\n v3 += ((i + 1) * (a2 - i) + 1) / 2 * *(uint32_t *)(4LL * i + a1);\n return v3;\n}" + }, + { + "index": 782, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int l) {\n int Sum = 0;\n for (int i = 0; i < l; i++) {\n Sum += ((((i + 1) * (l - i) + 1) / 2) * arr[i]);\n }\n return Sum;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 4};\n\n int arr2[] = {1, 2, 1, 2};\n\n int arr3[] = {1, 7};\n\n assert(func0(arr1, 3) == 14);\n\n assert(func0(arr2, 4) == 15);\n\n assert(func0(arr3, 2) == 8);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11af \nlea -0x1(%rsi),%r9d\nadd $0x2,%r9\nmov $0x1,%ecx\nmov $0x0,%r8d\nadd $0x1,%esi\nmov %esi,%eax\nsub %ecx,%eax\nimul %ecx,%eax\nlea 0x1(%rax),%edx\nmov %edx,%eax\nshr $0x1f,%eax\nadd %edx,%eax\nsar %eax\nimul -0x4(%rdi,%rcx,4),%eax\nadd %eax,%r8d\nadd $0x1,%rcx\ncmp %r9,%rcx\njne 1187 \nmov %r8d,%eax\nretq\nmov $0x0,%r8d\njmp 11ab \n", + "ida_asm": "func0:\nendbr64\nmov r8, rdi\ntest esi, esi\njle short loc_11AE\nmovsxd r9, esi\nmov ecx, 1\nmov edi, 0\nadd esi, 1\nloc_1184:\nmov edx, esi\nsub edx, ecx\nimul edx, ecx\nadd edx, 1\nmov eax, edx\nshr eax, 1Fh\nadd eax, edx\nsar eax, 1\nimul eax, [r8+rcx*4-4]\nadd edi, eax\nmov rax, rcx\nadd rcx, 1\ncmp rax, r9\njnz short loc_1184\nloc_11AB:\nmov eax, edi\nretn\nloc_11AE:\nmov edi, 0\njmp short loc_11AB", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v3; // r9\n __int64 v4; // rcx\n unsigned int v5; // edi\n int v6; // esi\n __int64 v7; // rax\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v3 = a2;\n v4 = 1LL;\n v5 = 0;\n v6 = a2 + 1;\n do\n {\n v5 += *(_DWORD *)(a1 + 4 * v4 - 4) * (((int)v4 * (v6 - (int)v4) + 1) / 2);\n v7 = v4++;\n }\n while ( v7 != v3 );\n }\n return v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov r8, rdi\ntest esi, esi\njle short loc_11AE\nmovsxd r9, esi\nmov ecx, 1\nmov edi, 0\nadd esi, 1\nloc_1184:\nmov edx, esi\nsub edx, ecx\nimul edx, ecx\nadd edx, 1\nmov eax, edx\nshr eax, 1Fh\nadd eax, edx\nsar eax, 1\nimul eax, [r8+rcx*4-4]\nadd edi, eax\nmov rax, rcx\nadd rcx, 1\ncmp rax, r9\njnz short loc_1184\nloc_11AB:\nmov eax, edi\nretn\nloc_11AE:\nmov edi, 0\njmp short loc_11AB", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n __int64 v3; // r9\n __int64 v4; // rcx\n unsigned int v5; // edi\n int v6; // esi\n __int64 v7; // rax\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v3 = a2;\n v4 = 1LL;\n v5 = 0;\n v6 = a2 + 1;\n do\n {\n v5 += *(_DWORD *)(a1 + 4 * v4 - 4) * (((int)v4 * (v6 - (int)v4) + 1) / 2);\n v7 = v4++;\n }\n while ( v7 != v3 );\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n long long v3;\n long long v4;\n unsigned int v5;\n int v6;\n long long v7;\n if (a2 <= 0) {\n return 0;\n } else {\n v3 = a2;\n v4 = 1LL;\n v5 = 0;\n v6 = a2 + 1;\n do {\n v5 +=\n *(uint32_t *)(a1 + 4 * v4 - 4) * (((int)v4 * (v6 - (int)v4) + 1) / 2);\n v7 = v4++;\n } while (v7 != v3);\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v3;\n long long v4;\n unsigned int v5;\n int v6;\n long long v7;\n if (a2 <= 0) {\n return 0;\n } else {\n v3 = a2;\n v4 = 1LL;\n v5 = 0;\n v6 = a2 + 1;\n do {\n v5 +=\n *(uint32_t *)(a1 + 4 * v4 - 4) * (((int)v4 * (v6 - (int)v4) + 1) / 2);\n v7 = v4++;\n } while (v7 != v3);\n }\n return v5;\n}" + }, + { + "index": 782, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int l) {\n int Sum = 0;\n for (int i = 0; i < l; i++) {\n Sum += ((((i + 1) * (l - i) + 1) / 2) * arr[i]);\n }\n return Sum;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 4};\n\n int arr2[] = {1, 2, 1, 2};\n\n int arr3[] = {1, 7};\n\n assert(func0(arr1, 3) == 14);\n\n assert(func0(arr2, 4) == 15);\n\n assert(func0(arr3, 2) == 8);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1188 \nlea -0x1(%rsi),%ecx\nmov $0x1,%edx\nxor %r8d,%r8d\nadd $0x1,%esi\nadd $0x2,%rcx\nnopw 0x0(%rax,%rax,1)\nmov %esi,%eax\nsub %edx,%eax\nimul %edx,%eax\nadd $0x1,%eax\nsar %eax\nimul -0x4(%rdi,%rdx,4),%eax\nadd $0x1,%rdx\nadd %eax,%r8d\ncmp %rdx,%rcx\njne 1160 \nmov %r8d,%eax\nretq\nnopl 0x0(%rax)\nxor %r8d,%r8d\nmov %r8d,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov r8, rdi\ntest esi, esi\njle short loc_12C0\nmovsxd r9, esi\nmov ecx, 1\nxor edi, edi\nadd esi, 1\nnop dword ptr [rax+rax+00000000h]\nloc_1290:\nmov edx, esi\nsub edx, ecx\nimul edx, ecx\nadd edx, 1\nmov eax, edx\nshr eax, 1Fh\nadd eax, edx\nsar eax, 1\nimul eax, [r8+rcx*4-4]\nadd edi, eax\nmov rax, rcx\nadd rcx, 1\ncmp rax, r9\njnz short loc_1290\nmov eax, edi\nretn\nloc_12C0:\nxor edi, edi\nmov eax, edi\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v3; // r9\n __int64 v4; // rcx\n unsigned int v5; // edi\n int v6; // esi\n __int64 v7; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v3 = a2;\n v4 = 1LL;\n v5 = 0;\n v6 = a2 + 1;\n do\n {\n v5 += *(_DWORD *)(a1 + 4 * v4 - 4) * (((int)v4 * (v6 - (int)v4) + 1) / 2);\n v7 = v4++;\n }\n while ( v7 != v3 );\n return v5;\n}", + "ida_strip_asm": "sub_1270:\nendbr64\nmov r8, rdi\ntest esi, esi\njle short loc_12C0\nmovsxd r9, esi\nmov ecx, 1\nxor edi, edi\nadd esi, 1\nnop dword ptr [rax+rax+00000000h]\nloc_1290:\nmov edx, esi\nsub edx, ecx\nimul edx, ecx\nadd edx, 1\nmov eax, edx\nshr eax, 1Fh\nadd eax, edx\nsar eax, 1\nimul eax, [r8+rcx*4-4]\nadd edi, eax\nmov rax, rcx\nadd rcx, 1\ncmp rax, r9\njnz short loc_1290\nmov eax, edi\nretn\nloc_12C0:\nxor edi, edi\nmov eax, edi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1270(__int64 a1, int a2)\n{\n __int64 v3; // r9\n __int64 v4; // rcx\n unsigned int v5; // edi\n int v6; // esi\n __int64 v7; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v3 = a2;\n v4 = 1LL;\n v5 = 0;\n v6 = a2 + 1;\n do\n {\n v5 += *(_DWORD *)(a1 + 4 * v4 - 4) * (((int)v4 * (v6 - (int)v4) + 1) / 2);\n v7 = v4++;\n }\n while ( v7 != v3 );\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1270(long long a1, int a2) {\n long long v3;\n long long v4;\n unsigned int v5;\n int v6;\n long long v7;\n if (a2 <= 0) return 0LL;\n v3 = a2;\n v4 = 1LL;\n v5 = 0;\n v6 = a2 + 1;\n do {\n v5 += *(uint32_t *)(a1 + 4 * v4 - 4) * (((int)v4 * (v6 - (int)v4) + 1) / 2);\n v7 = v4++;\n } while (v7 != v3);\n return v5;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v3;\n long long v4;\n unsigned int v5;\n int v6;\n long long v7;\n if (a2 <= 0) return 0LL;\n v3 = a2;\n v4 = 1LL;\n v5 = 0;\n v6 = a2 + 1;\n do {\n v5 += *(uint32_t *)(a1 + 4 * v4 - 4) * (((int)v4 * (v6 - (int)v4) + 1) / 2);\n v7 = v4++;\n } while (v7 != v3);\n return v5;\n}" + }, + { + "index": 783, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int r, int g, int b, double *h, double *s, double *v) {\n double rd = r / 255.0;\n double gd = g / 255.0;\n double bd = b / 255.0;\n double mx = fmax(rd, fmax(gd, bd));\n double mn = fmin(rd, fmin(gd, bd));\n double df = mx - mn;\n *h = 0;\n if (df > 0) {\n if (mx == rd) {\n *h = fmod((60.0 * ((gd - bd) / df) + 360.0), 360.0);\n } else if (mx == gd) {\n *h = fmod((60.0 * ((bd - rd) / df) + 120.0), 360.0);\n } else if (mx == bd) {\n *h = fmod((60.0 * ((rd - gd) / df) + 240.0), 360.0);\n }\n }\n if (mx == 0) {\n *s = 0;\n } else {\n *s = (df / mx) * 100.0;\n }\n *v = mx * 100.0;\n}", + "test": "int main() {\n\n double h, s, v;\n\n\n\n func0(255, 255, 255, &h, &s, &v);\n\n assert(h == 0 && s == 0.0 && v == 100.0);\n\n\n\n func0(0, 215, 0, &h, &s, &v);\n\n assert(h == 120.0 && s == 100.0 && v == 84.31372549019608);\n\n\n\n func0(10, 215, 110, &h, &s, &v);\n\n assert(h == 149.26829268292684 && s == 95.34883720930233 && v == 84.31372549019608);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x60,%rsp\nmov %edi,-0x34(%rbp)\nmov %esi,-0x38(%rbp)\nmov %edx,-0x3c(%rbp)\nmov %rcx,-0x48(%rbp)\nmov %r8,-0x50(%rbp)\nmov %r9,-0x58(%rbp)\ncvtsi2sdl -0x34(%rbp),%xmm0\nmovsd 0xf09(%rip),%xmm1\ndivsd %xmm1,%xmm0\nmovsd %xmm0,-0x30(%rbp)\ncvtsi2sdl -0x38(%rbp),%xmm0\nmovsd 0xef3(%rip),%xmm1\ndivsd %xmm1,%xmm0\nmovsd %xmm0,-0x28(%rbp)\ncvtsi2sdl -0x3c(%rbp),%xmm0\nmovsd 0xedd(%rip),%xmm1\ndivsd %xmm1,%xmm0\nmovsd %xmm0,-0x20(%rbp)\nmovsd -0x20(%rbp),%xmm0\nmov -0x28(%rbp),%rax\nmovapd %xmm0,%xmm1\nmovq %rax,%xmm0\ncallq 1090 \nmov -0x30(%rbp),%rax\nmovapd %xmm0,%xmm1\nmovq %rax,%xmm0\ncallq 1090 \nmovq %xmm0,%rax\nmov %rax,-0x18(%rbp)\nmovsd -0x20(%rbp),%xmm0\nmov -0x28(%rbp),%rax\nmovapd %xmm0,%xmm1\nmovq %rax,%xmm0\ncallq 10d0 \nmov -0x30(%rbp),%rax\nmovapd %xmm0,%xmm1\nmovq %rax,%xmm0\ncallq 10d0 \nmovq %xmm0,%rax\nmov %rax,-0x10(%rbp)\nmovsd -0x18(%rbp),%xmm0\nsubsd -0x10(%rbp),%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmov -0x48(%rbp),%rax\npxor %xmm0,%xmm0\nmovsd %xmm0,(%rax)\nmovsd -0x8(%rbp),%xmm0\npxor %xmm1,%xmm1\ncomisd %xmm1,%xmm0\njbe 13d9 \nmovsd -0x18(%rbp),%xmm0\nucomisd -0x30(%rbp),%xmm0\njp 131f \nmovsd -0x18(%rbp),%xmm0\nucomisd -0x30(%rbp),%xmm0\njne 131f \nmovsd -0x28(%rbp),%xmm0\nsubsd -0x20(%rbp),%xmm0\nmovapd %xmm0,%xmm1\ndivsd -0x8(%rbp),%xmm1\nmovsd 0xe17(%rip),%xmm0\nmulsd %xmm0,%xmm1\nmovsd 0xe13(%rip),%xmm0\naddsd %xmm1,%xmm0\nmovsd 0xe07(%rip),%xmm1\ncallq 10c0 \nmovq %xmm0,%rax\nmov -0x48(%rbp),%rdx\nmov %rax,(%rdx)\njmpq 13d9 \nmovsd -0x18(%rbp),%xmm0\nucomisd -0x28(%rbp),%xmm0\njp 137d \nmovsd -0x18(%rbp),%xmm0\nucomisd -0x28(%rbp),%xmm0\njne 137d \nmovsd -0x20(%rbp),%xmm0\nsubsd -0x30(%rbp),%xmm0\nmovapd %xmm0,%xmm1\ndivsd -0x8(%rbp),%xmm1\nmovsd 0xdb6(%rip),%xmm0\nmulsd %xmm0,%xmm1\nmovsd 0xdba(%rip),%xmm0\naddsd %xmm1,%xmm0\nmovsd 0xda6(%rip),%xmm1\ncallq 10c0 \nmovq %xmm0,%rax\nmov -0x48(%rbp),%rdx\nmov %rax,(%rdx)\njmp 13d9 \nmovsd -0x18(%rbp),%xmm0\nucomisd -0x20(%rbp),%xmm0\njp 13d9 \nmovsd -0x18(%rbp),%xmm0\nucomisd -0x20(%rbp),%xmm0\njne 13d9 \nmovsd -0x30(%rbp),%xmm0\nsubsd -0x28(%rbp),%xmm0\nmovapd %xmm0,%xmm1\ndivsd -0x8(%rbp),%xmm1\nmovsd 0xd58(%rip),%xmm0\nmulsd %xmm0,%xmm1\nmovsd 0xd64(%rip),%xmm0\naddsd %xmm1,%xmm0\nmovsd 0xd48(%rip),%xmm1\ncallq 10c0 \nmovq %xmm0,%rax\nmov -0x48(%rbp),%rdx\nmov %rax,(%rdx)\npxor %xmm0,%xmm0\nucomisd -0x18(%rbp),%xmm0\njp 13fd \npxor %xmm0,%xmm0\nucomisd -0x18(%rbp),%xmm0\njne 13fd \nmov -0x50(%rbp),%rax\npxor %xmm0,%xmm0\nmovsd %xmm0,(%rax)\njmp 141f \nmovsd -0x8(%rbp),%xmm0\nmovapd %xmm0,%xmm1\ndivsd -0x18(%rbp),%xmm1\nmovsd 0xd15(%rip),%xmm0\nmulsd %xmm1,%xmm0\nmov -0x50(%rbp),%rax\nmovsd %xmm0,(%rax)\nmovsd -0x18(%rbp),%xmm1\nmovsd 0xcfc(%rip),%xmm0\nmulsd %xmm1,%xmm0\nmov -0x58(%rbp),%rax\nmovsd %xmm0,(%rax)\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 60h\nmov [rbp+var_34], edi\nmov [rbp+var_38], esi\nmov [rbp+var_3C], edx\nmov [rbp+var_48], rcx\nmov [rbp+var_50], r8\nmov [rbp+var_58], r9\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_34]\nmovsd xmm1, cs:qword_20E0\ndivsd xmm0, xmm1\nmovsd [rbp+var_30], xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_38]\nmovsd xmm1, cs:qword_20E0\ndivsd xmm0, xmm1\nmovsd [rbp+x], xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_3C]\nmovsd xmm1, cs:qword_20E0\ndivsd xmm0, xmm1\nmovsd [rbp+y], xmm0\nmovsd xmm0, [rbp+y]\nmov rax, [rbp+x]\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _fmax\nmovq rdx, xmm0\nmov rax, [rbp+var_30]\nmovq xmm1, rdx; y\nmovq xmm0, rax; x\ncall _fmax\nmovq rax, xmm0\nmov [rbp+var_18], rax\nmovsd xmm0, [rbp+y]\nmov rax, [rbp+x]\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _fmin\nmovq rdx, xmm0\nmov rax, [rbp+var_30]\nmovq xmm1, rdx; y\nmovq xmm0, rax; x\ncall _fmin\nmovq rax, xmm0\nmov [rbp+var_10], rax\nmovsd xmm0, [rbp+var_18]\nsubsd xmm0, [rbp+var_10]\nmovsd [rbp+var_8], xmm0\nmov rax, [rbp+var_48]\npxor xmm0, xmm0\nmovsd qword ptr [rax], xmm0\nmovsd xmm0, [rbp+var_8]\npxor xmm1, xmm1\ncomisd xmm0, xmm1\njbe loc_141B\nmovsd xmm0, [rbp+var_18]\nucomisd xmm0, [rbp+var_30]\njp short loc_1345\nmovsd xmm0, [rbp+var_18]\nucomisd xmm0, [rbp+var_30]\njnz short loc_1345\nmovsd xmm0, [rbp+x]\nsubsd xmm0, [rbp+y]\nmovapd xmm1, xmm0\ndivsd xmm1, [rbp+var_8]\nmovsd xmm0, cs:qword_20E8\nmulsd xmm1, xmm0\nmovsd xmm0, cs:y\naddsd xmm1, xmm0\nmovq rax, xmm1\nmovsd xmm0, cs:y\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _fmod\nmovq rax, xmm0\nmov rdx, [rbp+var_48]\nmov [rdx], rax\njmp loc_141B\nloc_1345:\nmovsd xmm0, [rbp+var_18]\nucomisd xmm0, [rbp+x]\njp short loc_13B1\nmovsd xmm0, [rbp+var_18]\nucomisd xmm0, [rbp+x]\njnz short loc_13B1\nmovsd xmm0, [rbp+y]\nsubsd xmm0, [rbp+var_30]\nmovapd xmm1, xmm0\ndivsd xmm1, [rbp+var_8]\nmovsd xmm0, cs:qword_20E8\nmulsd xmm1, xmm0\nmovsd xmm0, cs:qword_20F8\naddsd xmm1, xmm0\nmovq rax, xmm1\nmovsd xmm0, cs:y\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _fmod\nmovq rax, xmm0\nmov rdx, [rbp+var_48]\nmov [rdx], rax\njmp short loc_141B\nloc_13B1:\nmovsd xmm0, [rbp+var_18]\nucomisd xmm0, [rbp+y]\njp short loc_141B\nmovsd xmm0, [rbp+var_18]\nucomisd xmm0, [rbp+y]\njnz short loc_141B\nmovsd xmm0, [rbp+var_30]\nsubsd xmm0, [rbp+x]\nmovapd xmm1, xmm0\ndivsd xmm1, [rbp+var_8]\nmovsd xmm0, cs:qword_20E8\nmulsd xmm1, xmm0\nmovsd xmm0, cs:qword_2100\naddsd xmm1, xmm0\nmovq rax, xmm1\nmovsd xmm0, cs:y\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _fmod\nmovq rax, xmm0\nmov rdx, [rbp+var_48]\nmov [rdx], rax\nloc_141B:\npxor xmm0, xmm0\nucomisd xmm0, [rbp+var_18]\njp short loc_143F\npxor xmm0, xmm0\nucomisd xmm0, [rbp+var_18]\njnz short loc_143F\nmov rax, [rbp+var_50]\npxor xmm0, xmm0\nmovsd qword ptr [rax], xmm0\njmp short loc_1461\nloc_143F:\nmovsd xmm0, [rbp+var_8]\nmovapd xmm1, xmm0\ndivsd xmm1, [rbp+var_18]\nmovsd xmm0, cs:qword_2108\nmulsd xmm0, xmm1\nmov rax, [rbp+var_50]\nmovsd qword ptr [rax], xmm0\nloc_1461:\nmovsd xmm1, [rbp+var_18]\nmovsd xmm0, cs:qword_2108\nmulsd xmm0, xmm1\nmov rax, [rbp+var_58]\nmovsd qword ptr [rax], xmm0\nnop\nleave\nretn", + "ida_pseudo": "double *__fastcall func0(int a1, int a2, int a3, double *a4, double *a5, double *a6)\n{\n double v6; // xmm0_8\n double v7; // xmm0_8\n double *result; // rax\n double v12; // [rsp+30h] [rbp-30h]\n double x; // [rsp+38h] [rbp-28h]\n double y; // [rsp+40h] [rbp-20h]\n double v15; // [rsp+48h] [rbp-18h]\n double v16; // [rsp+58h] [rbp-8h]\n\n v12 = (double)a1 / 255.0;\n x = (double)a2 / 255.0;\n y = (double)a3 / 255.0;\n v6 = fmax(x, y);\n v15 = fmax(v12, v6);\n v7 = fmin(x, y);\n v16 = v15 - fmin(v12, v7);\n *a4 = 0.0;\n if ( v16 > 0.0 )\n {\n if ( v15 == v12 )\n {\n *a4 = fmod((x - y) / v16 * 60.0 + 360.0, 360.0);\n }\n else if ( v15 == x )\n {\n *a4 = fmod((y - v12) / v16 * 60.0 + 120.0, 360.0);\n }\n else if ( v15 == y )\n {\n *a4 = fmod((v12 - x) / v16 * 60.0 + 240.0, 360.0);\n }\n }\n if ( v15 == 0.0 )\n *a5 = 0.0;\n else\n *a5 = 100.0 * (v16 / v15);\n result = a6;\n *a6 = 100.0 * v15;\n return result;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 60h\nmov [rbp+var_34], edi\nmov [rbp+var_38], esi\nmov [rbp+var_3C], edx\nmov [rbp+var_48], rcx\nmov [rbp+var_50], r8\nmov [rbp+var_58], r9\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_34]\nmovsd xmm1, cs:qword_20E0\ndivsd xmm0, xmm1\nmovsd [rbp+var_30], xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_38]\nmovsd xmm1, cs:qword_20E0\ndivsd xmm0, xmm1\nmovsd [rbp+x], xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_3C]\nmovsd xmm1, cs:qword_20E0\ndivsd xmm0, xmm1\nmovsd [rbp+y], xmm0\nmovsd xmm0, [rbp+y]\nmov rax, [rbp+x]\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _fmax\nmovq rdx, xmm0\nmov rax, [rbp+var_30]\nmovq xmm1, rdx; y\nmovq xmm0, rax; x\ncall _fmax\nmovq rax, xmm0\nmov [rbp+var_18], rax\nmovsd xmm0, [rbp+y]\nmov rax, [rbp+x]\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _fmin\nmovq rdx, xmm0\nmov rax, [rbp+var_30]\nmovq xmm1, rdx; y\nmovq xmm0, rax; x\ncall _fmin\nmovq rax, xmm0\nmov [rbp+var_10], rax\nmovsd xmm0, [rbp+var_18]\nsubsd xmm0, [rbp+var_10]\nmovsd [rbp+var_8], xmm0\nmov rax, [rbp+var_48]\npxor xmm0, xmm0\nmovsd qword ptr [rax], xmm0\nmovsd xmm0, [rbp+var_8]\npxor xmm1, xmm1\ncomisd xmm0, xmm1\njbe loc_141B\nmovsd xmm0, [rbp+var_18]\nucomisd xmm0, [rbp+var_30]\njp short loc_1345\nmovsd xmm0, [rbp+var_18]\nucomisd xmm0, [rbp+var_30]\njnz short loc_1345\nmovsd xmm0, [rbp+x]\nsubsd xmm0, [rbp+y]\nmovapd xmm1, xmm0\ndivsd xmm1, [rbp+var_8]\nmovsd xmm0, cs:qword_20E8\nmulsd xmm1, xmm0\nmovsd xmm0, cs:y\naddsd xmm1, xmm0\nmovq rax, xmm1\nmovsd xmm0, cs:y\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _fmod\nmovq rax, xmm0\nmov rdx, [rbp+var_48]\nmov [rdx], rax\njmp loc_141B\nloc_1345:\nmovsd xmm0, [rbp+var_18]\nucomisd xmm0, [rbp+x]\njp short loc_13B1\nmovsd xmm0, [rbp+var_18]\nucomisd xmm0, [rbp+x]\njnz short loc_13B1\nmovsd xmm0, [rbp+y]\nsubsd xmm0, [rbp+var_30]\nmovapd xmm1, xmm0\ndivsd xmm1, [rbp+var_8]\nmovsd xmm0, cs:qword_20E8\nmulsd xmm1, xmm0\nmovsd xmm0, cs:qword_20F8\naddsd xmm1, xmm0\nmovq rax, xmm1\nmovsd xmm0, cs:y\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _fmod\nmovq rax, xmm0\nmov rdx, [rbp+var_48]\nmov [rdx], rax\njmp short loc_141B\nloc_13B1:\nmovsd xmm0, [rbp+var_18]\nucomisd xmm0, [rbp+y]\njp short loc_141B\nmovsd xmm0, [rbp+var_18]\nucomisd xmm0, [rbp+y]\njnz short loc_141B\nmovsd xmm0, [rbp+var_30]\nsubsd xmm0, [rbp+x]\nmovapd xmm1, xmm0\ndivsd xmm1, [rbp+var_8]\nmovsd xmm0, cs:qword_20E8\nmulsd xmm1, xmm0\nmovsd xmm0, cs:qword_2100\naddsd xmm1, xmm0\nmovq rax, xmm1\nmovsd xmm0, cs:y\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _fmod\nmovq rax, xmm0\nmov rdx, [rbp+var_48]\nmov [rdx], rax\nloc_141B:\npxor xmm0, xmm0\nucomisd xmm0, [rbp+var_18]\njp short loc_143F\npxor xmm0, xmm0\nucomisd xmm0, [rbp+var_18]\njnz short loc_143F\nmov rax, [rbp+var_50]\npxor xmm0, xmm0\nmovsd qword ptr [rax], xmm0\njmp short loc_1461\nloc_143F:\nmovsd xmm0, [rbp+var_8]\nmovapd xmm1, xmm0\ndivsd xmm1, [rbp+var_18]\nmovsd xmm0, cs:qword_2108\nmulsd xmm0, xmm1\nmov rax, [rbp+var_50]\nmovsd qword ptr [rax], xmm0\nloc_1461:\nmovsd xmm1, [rbp+var_18]\nmovsd xmm0, cs:qword_2108\nmulsd xmm0, xmm1\nmov rax, [rbp+var_58]\nmovsd qword ptr [rax], xmm0\nnop\nleave\nretn", + "ida_strip_pseudo": "double *__fastcall sub_11C9(int a1, int a2, int a3, double *a4, double *a5, double *a6)\n{\n double v6; // xmm0_8\n double v7; // xmm0_8\n double *result; // rax\n double v12; // [rsp+30h] [rbp-30h]\n double x; // [rsp+38h] [rbp-28h]\n double y; // [rsp+40h] [rbp-20h]\n double v15; // [rsp+48h] [rbp-18h]\n double v16; // [rsp+58h] [rbp-8h]\n\n v12 = (double)a1 / 255.0;\n x = (double)a2 / 255.0;\n y = (double)a3 / 255.0;\n v6 = fmax(x, y);\n v15 = fmax(v12, v6);\n v7 = fmin(x, y);\n v16 = v15 - fmin(v12, v7);\n *a4 = 0.0;\n if ( v16 > 0.0 )\n {\n if ( v15 == v12 )\n {\n *a4 = fmod((x - y) / v16 * 60.0 + 360.0, 360.0);\n }\n else if ( v15 == x )\n {\n *a4 = fmod((y - v12) / v16 * 60.0 + 120.0, 360.0);\n }\n else if ( v15 == y )\n {\n *a4 = fmod((v12 - x) / v16 * 60.0 + 240.0, 360.0);\n }\n }\n if ( v15 == 0.0 )\n *a5 = 0.0;\n else\n *a5 = 100.0 * (v16 / v15);\n result = a6;\n *a6 = 100.0 * v15;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double *sub_11C9(int a1, int a2, int a3, double *a4, double *a5, double *a6) {\n double v6;\n double v7;\n double *result;\n double v12;\n double x;\n double y;\n double v15;\n double v16;\n v12 = (double)a1 / 255.0;\n x = (double)a2 / 255.0;\n y = (double)a3 / 255.0;\n v6 = fmax(x, y);\n v15 = fmax(v12, v6);\n v7 = fmin(x, y);\n v16 = v15 - fmin(v12, v7);\n *a4 = 0.0;\n if (v16 > 0.0) {\n if (v15 == v12) {\n *a4 = fmod((x - y) / v16 * 60.0 + 360.0, 360.0);\n } else if (v15 == x) {\n *a4 = fmod((y - v12) / v16 * 60.0 + 120.0, 360.0);\n } else if (v15 == y) {\n *a4 = fmod((v12 - x) / v16 * 60.0 + 240.0, 360.0);\n }\n }\n if (v15 == 0.0)\n *a5 = 0.0;\n else\n *a5 = 100.0 * (v16 / v15);\n result = a6;\n *a6 = 100.0 * v15;\n return result;\n}", + "ida_pseudo_norm": "double *func0(int a1, int a2, int a3, double *a4, double *a5, double *a6) {\n double v6;\n double v7;\n double *result;\n double v12;\n double x;\n double y;\n double v15;\n double v16;\n v12 = (double)a1 / 255.0;\n x = (double)a2 / 255.0;\n y = (double)a3 / 255.0;\n v6 = fmax(x, y);\n v15 = fmax(v12, v6);\n v7 = fmin(x, y);\n v16 = v15 - fmin(v12, v7);\n *a4 = 0.0;\n if (v16 > 0.0) {\n if (v15 == v12) {\n *a4 = fmod((x - y) / v16 * 60.0 + 360.0, 360.0);\n } else if (v15 == x) {\n *a4 = fmod((y - v12) / v16 * 60.0 + 120.0, 360.0);\n } else if (v15 == y) {\n *a4 = fmod((v12 - x) / v16 * 60.0 + 240.0, 360.0);\n }\n }\n if (v15 == 0.0)\n *a5 = 0.0;\n else\n *a5 = 100.0 * (v16 / v15);\n result = a6;\n *a6 = 100.0 * v15;\n return result;\n}" + }, + { + "index": 783, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int r, int g, int b, double *h, double *s, double *v) {\n double rd = r / 255.0;\n double gd = g / 255.0;\n double bd = b / 255.0;\n double mx = fmax(rd, fmax(gd, bd));\n double mn = fmin(rd, fmin(gd, bd));\n double df = mx - mn;\n *h = 0;\n if (df > 0) {\n if (mx == rd) {\n *h = fmod((60.0 * ((gd - bd) / df) + 360.0), 360.0);\n } else if (mx == gd) {\n *h = fmod((60.0 * ((bd - rd) / df) + 120.0), 360.0);\n } else if (mx == bd) {\n *h = fmod((60.0 * ((rd - gd) / df) + 240.0), 360.0);\n }\n }\n if (mx == 0) {\n *s = 0;\n } else {\n *s = (df / mx) * 100.0;\n }\n *v = mx * 100.0;\n}", + "test": "int main() {\n\n double h, s, v;\n\n\n\n func0(255, 255, 255, &h, &s, &v);\n\n assert(h == 0 && s == 0.0 && v == 100.0);\n\n\n\n func0(0, 215, 0, &h, &s, &v);\n\n assert(h == 120.0 && s == 100.0 && v == 84.31372549019608);\n\n\n\n func0(10, 215, 110, &h, &s, &v);\n\n assert(h == 149.26829268292684 && s == 95.34883720930233 && v == 84.31372549019608);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nsub $0x30,%rsp\nmov %rcx,%rbx\nmov %r8,%r12\nmov %r9,%rbp\npxor %xmm1,%xmm1\ncvtsi2sd %edi,%xmm1\nmovsd 0xf1a(%rip),%xmm0\ndivsd %xmm0,%xmm1\nmovsd %xmm1,0x10(%rsp)\npxor %xmm1,%xmm1\ncvtsi2sd %esi,%xmm1\nmovapd %xmm1,%xmm5\ndivsd %xmm0,%xmm5\npxor %xmm1,%xmm1\ncvtsi2sd %edx,%xmm1\nmovapd %xmm1,%xmm6\ndivsd %xmm0,%xmm6\nmovsd %xmm6,0x20(%rsp)\nmovapd %xmm6,%xmm1\nmovsd %xmm5,0x18(%rsp)\nmovapd %xmm5,%xmm0\ncallq 1090 \nmovapd %xmm0,%xmm1\nmovsd 0x10(%rsp),%xmm0\ncallq 1090 \nmovsd %xmm0,0x8(%rsp)\nmovsd 0x20(%rsp),%xmm1\nmovsd 0x18(%rsp),%xmm0\ncallq 10d0 \nmovapd %xmm0,%xmm1\nmovsd 0x10(%rsp),%xmm0\ncallq 10d0 \nmovsd 0x8(%rsp),%xmm3\nmovapd %xmm3,%xmm4\nsubsd %xmm0,%xmm4\nmovsd %xmm4,0x28(%rsp)\nmovq $0x0,(%rbx)\ncomisd 0xe77(%rip),%xmm4\njbe 1321 \nmovsd 0x10(%rsp),%xmm2\nucomisd %xmm3,%xmm2\njnp 12f2 \nmovsd 0x18(%rsp),%xmm2\nucomisd 0x8(%rsp),%xmm2\njnp 1339 \nmovsd 0x20(%rsp),%xmm2\nucomisd 0x8(%rsp),%xmm2\njp 1321 \njne 1321 \nmovsd 0x10(%rsp),%xmm0\nsubsd 0x18(%rsp),%xmm0\ndivsd 0x28(%rsp),%xmm0\nmulsd 0xe41(%rip),%xmm0\naddsd 0xe49(%rip),%xmm0\nmovsd 0xe29(%rip),%xmm1\ncallq 10c0 \nmovsd %xmm0,(%rbx)\njmp 1321 \njne 129b \nmovsd 0xe14(%rip),%xmm1\nmovsd 0x18(%rsp),%xmm0\nsubsd 0x20(%rsp),%xmm0\ndivsd %xmm4,%xmm0\nmulsd 0xe04(%rip),%xmm0\naddsd %xmm1,%xmm0\ncallq 10c0 \nmovsd %xmm0,(%rbx)\nmovsd 0x8(%rsp),%xmm7\nucomisd 0xdd1(%rip),%xmm7\njp 1374 \njne 1374 \npxor %xmm0,%xmm0\njmp 1388 \njne 12ad \nmovsd 0x20(%rsp),%xmm0\nsubsd 0x10(%rsp),%xmm0\ndivsd 0x28(%rsp),%xmm0\nmulsd 0xdbf(%rip),%xmm0\naddsd 0xdbf(%rip),%xmm0\nmovsd 0xda7(%rip),%xmm1\ncallq 10c0 \nmovsd %xmm0,(%rbx)\njmp 1321 \nmovsd 0x28(%rsp),%xmm0\ndivsd 0x8(%rsp),%xmm0\nmulsd 0xda8(%rip),%xmm0\nmovsd %xmm0,(%r12)\nmovsd 0x8(%rsp),%xmm0\nmulsd 0xd94(%rip),%xmm0\nmovsd %xmm0,0x0(%rbp)\nadd $0x30,%rsp\npop %rbx\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 30h\nmov rbx, rcx\nmov r12, r8\nmov rbp, r9\npxor xmm1, xmm1\ncvtsi2sd xmm1, edi\nmovsd xmm0, cs:qword_20E0\ndivsd xmm1, xmm0\nmovsd [rsp+48h+y], xmm1\npxor xmm1, xmm1\ncvtsi2sd xmm1, esi\nmovapd xmm5, xmm1\ndivsd xmm5, xmm0\npxor xmm1, xmm1\ncvtsi2sd xmm1, edx\nmovapd xmm6, xmm1\ndivsd xmm6, xmm0\nmovsd [rsp+48h+var_28], xmm6\nmovapd xmm1, xmm6; y\nmovsd [rsp+48h+x], xmm5\nmovapd xmm0, xmm5; x\ncall _fmax\nmovsd xmm1, [rsp+48h+y]; y\ncall _fmax\nmovsd [rsp+48h+var_40], xmm0\nmovsd xmm1, [rsp+48h+var_28]; y\nmovsd xmm0, [rsp+48h+x]; x\ncall _fmin\nmovsd xmm1, [rsp+48h+y]; y\ncall _fmin\nmovsd xmm3, [rsp+48h+var_40]\nmovapd xmm4, xmm3\nsubsd xmm4, xmm0\nmovsd [rsp+48h+var_20], xmm4\nmov qword ptr [rbx], 0\npxor xmm0, xmm0\ncomisd xmm4, xmm0\njbe loc_137F\nmovsd xmm2, [rsp+48h+y]\nucomisd xmm2, xmm3\njp short loc_1299\njz loc_132A\nloc_1299:\nmovsd xmm5, [rsp+48h+x]\nmovsd xmm6, [rsp+48h+var_40]\nucomisd xmm5, xmm6\njp short loc_12B1\njz loc_13D0\nloc_12B1:\nmovsd xmm7, [rsp+48h+var_28]\nmovsd xmm2, [rsp+48h+var_40]\nucomisd xmm7, xmm2\njp loc_137F\njnz loc_137F\nmovsd xmm0, [rsp+48h+y]\nsubsd xmm0, [rsp+48h+x]\ndivsd xmm0, [rsp+48h+var_20]\nmulsd xmm0, cs:qword_20E8\naddsd xmm0, cs:qword_2100\nmovsd [rsp+48h+x], xmm0\nfld cs:y\nfld [rsp+48h+x]\nloc_12FF:\nfprem\nfnstsw ax\ntest ah, 4\njnz short loc_12FF\nfstp st(1)\nfstp [rsp+48h+y]\nmovsd xmm4, [rsp+48h+y]\nucomisd xmm4, xmm4\njp loc_1441\nloc_131E:\nmovsd xmm6, [rsp+48h+y]\nmovsd qword ptr [rbx], xmm6\njmp short loc_137F\nloc_132A:\nmovsd xmm0, [rsp+48h+x]\nsubsd xmm0, [rsp+48h+var_28]\ndivsd xmm0, xmm4\nmulsd xmm0, cs:qword_20E8\naddsd xmm0, cs:y\nmovsd [rsp+48h+x], xmm0\nfld cs:y\nfld [rsp+48h+x]\nloc_135A:\nfprem\nfnstsw ax\ntest ah, 4\njnz short loc_135A\nfstp st(1)\nfstp [rsp+48h+y]\nmovsd xmm2, [rsp+48h+y]\nucomisd xmm2, xmm2\njp short loc_13BB\nloc_1375:\nmovsd xmm6, [rsp+48h+y]\nmovsd qword ptr [rbx], xmm6\nloc_137F:\npxor xmm0, xmm0\nmovsd xmm7, [rsp+48h+var_40]\nucomisd xmm7, xmm0\njp loc_1459\njnz loc_1459\nloc_1399:\nmovsd qword ptr [r12], xmm0\nmovsd xmm0, [rsp+48h+var_40]\nmulsd xmm0, cs:qword_2108\nmovsd qword ptr [rbp+0], xmm0\nadd rsp, 30h\npop rbx\npop rbp\npop r12\nretn\nloc_13BB:\nmovsd xmm1, cs:y; y\nmovsd xmm0, [rsp+48h+x]; x\ncall _fmod\njmp short loc_1375\nloc_13D0:\nmovsd xmm0, [rsp+48h+var_28]\nsubsd xmm0, [rsp+48h+y]\ndivsd xmm0, [rsp+48h+var_20]\nmulsd xmm0, cs:qword_20E8\naddsd xmm0, cs:qword_20F8\nmovsd [rsp+48h+x], xmm0\nfld cs:y\nfld [rsp+48h+x]\nloc_1402:\nfprem\nfnstsw ax\ntest ah, 4\njnz short loc_1402\nfstp st(1)\nfstp [rsp+48h+y]\nmovsd xmm3, [rsp+48h+y]\nucomisd xmm3, xmm3\njp short loc_142C\nloc_141D:\nmovsd xmm7, [rsp+48h+y]\nmovsd qword ptr [rbx], xmm7\njmp loc_137F\nloc_142C:\nmovsd xmm1, cs:y; y\nmovsd xmm0, [rsp+48h+x]; x\ncall _fmod\njmp short loc_141D\nloc_1441:\nmovsd xmm1, cs:y; y\nmovsd xmm0, [rsp+48h+x]; x\ncall _fmod\njmp loc_131E\nloc_1459:\nmovsd xmm0, [rsp+48h+var_20]\ndivsd xmm0, [rsp+48h+var_40]\nmulsd xmm0, cs:qword_2108\njmp loc_1399", + "ida_pseudo": "void __fastcall func0(int a1, int a2, int a3, double *a4, double *a5, double *a6)\n{\n double v9; // xmm0_8\n double v10; // xmm0_8\n double v11; // xmm4_8\n long double v12; // fst6\n char v14; // c2\n long double v15; // fst6\n char v17; // c2\n double v18; // xmm0_8\n long double v19; // fst6\n char v21; // c2\n double v22; // [rsp+8h] [rbp-40h]\n double y; // [rsp+10h] [rbp-38h]\n double x; // [rsp+18h] [rbp-30h]\n double v25; // [rsp+20h] [rbp-28h]\n\n y = (double)a1 / 255.0;\n v25 = (double)a3 / 255.0;\n x = (double)a2 / 255.0;\n v9 = fmax(x, v25);\n v22 = fmax(v9, y);\n v10 = fmin(x, v25);\n v11 = v22 - fmin(v10, y);\n *a4 = 0.0;\n if ( v11 > 0.0 )\n {\n if ( y == v22 )\n {\n v15 = (x - v25) / v11 * 60.0 + 360.0;\n do\n v15 = __FPREM__(v15, 360.0);\n while ( v17 );\n *a4 = v15;\n }\n else if ( x == v22 )\n {\n v19 = (v25 - y) / v11 * 60.0 + 120.0;\n do\n v19 = __FPREM__(v19, 360.0);\n while ( v21 );\n *a4 = v19;\n }\n else if ( v25 == v22 )\n {\n v12 = (y - x) / v11 * 60.0 + 240.0;\n do\n v12 = __FPREM__(v12, 360.0);\n while ( v14 );\n *a4 = v12;\n }\n }\n v18 = 0.0;\n if ( v22 != 0.0 )\n v18 = v11 / v22 * 100.0;\n *a5 = v18;\n *a6 = v22 * 100.0;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 30h\nmov rbx, rcx\nmov r12, r8\nmov rbp, r9\npxor xmm1, xmm1\ncvtsi2sd xmm1, edi\nmovsd xmm0, cs:qword_20E0\ndivsd xmm1, xmm0\nmovsd [rsp+48h+y], xmm1\npxor xmm1, xmm1\ncvtsi2sd xmm1, esi\nmovapd xmm5, xmm1\ndivsd xmm5, xmm0\npxor xmm1, xmm1\ncvtsi2sd xmm1, edx\nmovapd xmm6, xmm1\ndivsd xmm6, xmm0\nmovsd [rsp+48h+var_28], xmm6\nmovapd xmm1, xmm6; y\nmovsd [rsp+48h+x], xmm5\nmovapd xmm0, xmm5; x\ncall _fmax\nmovsd xmm1, [rsp+48h+y]; y\ncall _fmax\nmovsd [rsp+48h+var_40], xmm0\nmovsd xmm1, [rsp+48h+var_28]; y\nmovsd xmm0, [rsp+48h+x]; x\ncall _fmin\nmovsd xmm1, [rsp+48h+y]; y\ncall _fmin\nmovsd xmm3, [rsp+48h+var_40]\nmovapd xmm4, xmm3\nsubsd xmm4, xmm0\nmovsd [rsp+48h+var_20], xmm4\nmov qword ptr [rbx], 0\npxor xmm0, xmm0\ncomisd xmm4, xmm0\njbe loc_137F\nmovsd xmm2, [rsp+48h+y]\nucomisd xmm2, xmm3\njp short loc_1299\njz loc_132A\nloc_1299:\nmovsd xmm5, [rsp+48h+x]\nmovsd xmm6, [rsp+48h+var_40]\nucomisd xmm5, xmm6\njp short loc_12B1\njz loc_13D0\nloc_12B1:\nmovsd xmm7, [rsp+48h+var_28]\nmovsd xmm2, [rsp+48h+var_40]\nucomisd xmm7, xmm2\njp loc_137F\njnz loc_137F\nmovsd xmm0, [rsp+48h+y]\nsubsd xmm0, [rsp+48h+x]\ndivsd xmm0, [rsp+48h+var_20]\nmulsd xmm0, cs:qword_20E8\naddsd xmm0, cs:qword_2100\nmovsd [rsp+48h+x], xmm0\nfld cs:y\nfld [rsp+48h+x]\nloc_12FF:\nfprem\nfnstsw ax\ntest ah, 4\njnz short loc_12FF\nfstp st(1)\nfstp [rsp+48h+y]\nmovsd xmm4, [rsp+48h+y]\nucomisd xmm4, xmm4\njp loc_1441\nloc_131E:\nmovsd xmm6, [rsp+48h+y]\nmovsd qword ptr [rbx], xmm6\njmp short loc_137F\nloc_132A:\nmovsd xmm0, [rsp+48h+x]\nsubsd xmm0, [rsp+48h+var_28]\ndivsd xmm0, xmm4\nmulsd xmm0, cs:qword_20E8\naddsd xmm0, cs:y\nmovsd [rsp+48h+x], xmm0\nfld cs:y\nfld [rsp+48h+x]\nloc_135A:\nfprem\nfnstsw ax\ntest ah, 4\njnz short loc_135A\nfstp st(1)\nfstp [rsp+48h+y]\nmovsd xmm2, [rsp+48h+y]\nucomisd xmm2, xmm2\njp short loc_13BB\nloc_1375:\nmovsd xmm6, [rsp+48h+y]\nmovsd qword ptr [rbx], xmm6\nloc_137F:\npxor xmm0, xmm0\nmovsd xmm7, [rsp+48h+var_40]\nucomisd xmm7, xmm0\njp loc_1459\njnz loc_1459\nloc_1399:\nmovsd qword ptr [r12], xmm0\nmovsd xmm0, [rsp+48h+var_40]\nmulsd xmm0, cs:qword_2108\nmovsd qword ptr [rbp+0], xmm0\nadd rsp, 30h\npop rbx\npop rbp\npop r12\nretn\nloc_13BB:\nmovsd xmm1, cs:y; y\nmovsd xmm0, [rsp+48h+x]; x\ncall _fmod\njmp short loc_1375\nloc_13D0:\nmovsd xmm0, [rsp+48h+var_28]\nsubsd xmm0, [rsp+48h+y]\ndivsd xmm0, [rsp+48h+var_20]\nmulsd xmm0, cs:qword_20E8\naddsd xmm0, cs:qword_20F8\nmovsd [rsp+48h+x], xmm0\nfld cs:y\nfld [rsp+48h+x]\nloc_1402:\nfprem\nfnstsw ax\ntest ah, 4\njnz short loc_1402\nfstp st(1)\nfstp [rsp+48h+y]\nmovsd xmm3, [rsp+48h+y]\nucomisd xmm3, xmm3\njp short loc_142C\nloc_141D:\nmovsd xmm7, [rsp+48h+y]\nmovsd qword ptr [rbx], xmm7\njmp loc_137F\nloc_142C:\nmovsd xmm1, cs:y; y\nmovsd xmm0, [rsp+48h+x]; x\ncall _fmod\njmp short loc_141D\nloc_1441:\nmovsd xmm1, cs:y; y\nmovsd xmm0, [rsp+48h+x]; x\ncall _fmod\njmp loc_131E\nloc_1459:\nmovsd xmm0, [rsp+48h+var_20]\ndivsd xmm0, [rsp+48h+var_40]\nmulsd xmm0, cs:qword_2108\njmp loc_1399", + "ida_strip_pseudo": "void __fastcall sub_11C9(int a1, int a2, int a3, double *a4, double *a5, double *a6)\n{\n double v9; // xmm0_8\n double v10; // xmm0_8\n double v11; // xmm4_8\n long double v12; // fst6\n char v14; // c2\n long double v15; // fst6\n char v17; // c2\n double v18; // xmm0_8\n long double v19; // fst6\n char v21; // c2\n double v22; // [rsp+8h] [rbp-40h]\n double y; // [rsp+10h] [rbp-38h]\n double x; // [rsp+18h] [rbp-30h]\n double v25; // [rsp+20h] [rbp-28h]\n\n y = (double)a1 / 255.0;\n v25 = (double)a3 / 255.0;\n x = (double)a2 / 255.0;\n v9 = fmax(x, v25);\n v22 = fmax(v9, y);\n v10 = fmin(x, v25);\n v11 = v22 - fmin(v10, y);\n *a4 = 0.0;\n if ( v11 > 0.0 )\n {\n if ( y == v22 )\n {\n v15 = (x - v25) / v11 * 60.0 + 360.0;\n do\n v15 = __FPREM__(v15, 360.0);\n while ( v17 );\n *a4 = v15;\n }\n else if ( x == v22 )\n {\n v19 = (v25 - y) / v11 * 60.0 + 120.0;\n do\n v19 = __FPREM__(v19, 360.0);\n while ( v21 );\n *a4 = v19;\n }\n else if ( v25 == v22 )\n {\n v12 = (y - x) / v11 * 60.0 + 240.0;\n do\n v12 = __FPREM__(v12, 360.0);\n while ( v14 );\n *a4 = v12;\n }\n }\n v18 = 0.0;\n if ( v22 != 0.0 )\n v18 = v11 / v22 * 100.0;\n *a5 = v18;\n *a6 = v22 * 100.0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_11C9(int a1, int a2, int a3, double *a4, double *a5, double *a6) {\n double v9;\n double v10;\n double v11;\n long double v12;\n char v14;\n long double v15;\n char v17;\n double v18;\n long double v19;\n char v21;\n double v22;\n double y;\n double x;\n double v25;\n y = (double)a1 / 255.0;\n v25 = (double)a3 / 255.0;\n x = (double)a2 / 255.0;\n v9 = fmax(x, v25);\n v22 = fmax(v9, y);\n v10 = fmin(x, v25);\n v11 = v22 - fmin(v10, y);\n *a4 = 0.0;\n if (v11 > 0.0) {\n if (y == v22) {\n v15 = (x - v25) / v11 * 60.0 + 360.0;\n do\n v15 = __FPREM__(v15, 360.0);\n while (v17);\n *a4 = v15;\n } else if (x == v22) {\n v19 = (v25 - y) / v11 * 60.0 + 120.0;\n do\n v19 = __FPREM__(v19, 360.0);\n while (v21);\n *a4 = v19;\n } else if (v25 == v22) {\n v12 = (y - x) / v11 * 60.0 + 240.0;\n do\n v12 = __FPREM__(v12, 360.0);\n while (v14);\n *a4 = v12;\n }\n }\n v18 = 0.0;\n if (v22 != 0.0) v18 = v11 / v22 * 100.0;\n *a5 = v18;\n *a6 = v22 * 100.0;\n}", + "ida_pseudo_norm": "void func0(int a1, int a2, int a3, double *a4, double *a5, double *a6) {\n double v9;\n double v10;\n double v11;\n long double v12;\n char v14;\n long double v15;\n char v17;\n double v18;\n long double v19;\n char v21;\n double v22;\n double y;\n double x;\n double v25;\n y = (double)a1 / 255.0;\n v25 = (double)a3 / 255.0;\n x = (double)a2 / 255.0;\n v9 = fmax(x, v25);\n v22 = fmax(v9, y);\n v10 = fmin(x, v25);\n v11 = v22 - fmin(v10, y);\n *a4 = 0.0;\n if (v11 > 0.0) {\n if (y == v22) {\n v15 = (x - v25) / v11 * 60.0 + 360.0;\n do\n v15 = __FPREM__(v15, 360.0);\n while (v17);\n *a4 = v15;\n } else if (x == v22) {\n v19 = (v25 - y) / v11 * 60.0 + 120.0;\n do\n v19 = __FPREM__(v19, 360.0);\n while (v21);\n *a4 = v19;\n } else if (v25 == v22) {\n v12 = (y - x) / v11 * 60.0 + 240.0;\n do\n v12 = __FPREM__(v12, 360.0);\n while (v14);\n *a4 = v12;\n }\n }\n v18 = 0.0;\n if (v22 != 0.0) v18 = v11 / v22 * 100.0;\n *a5 = v18;\n *a6 = v22 * 100.0;\n}" + }, + { + "index": 783, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int r, int g, int b, double *h, double *s, double *v) {\n double rd = r / 255.0;\n double gd = g / 255.0;\n double bd = b / 255.0;\n double mx = fmax(rd, fmax(gd, bd));\n double mn = fmin(rd, fmin(gd, bd));\n double df = mx - mn;\n *h = 0;\n if (df > 0) {\n if (mx == rd) {\n *h = fmod((60.0 * ((gd - bd) / df) + 360.0), 360.0);\n } else if (mx == gd) {\n *h = fmod((60.0 * ((bd - rd) / df) + 120.0), 360.0);\n } else if (mx == bd) {\n *h = fmod((60.0 * ((rd - gd) / df) + 240.0), 360.0);\n }\n }\n if (mx == 0) {\n *s = 0;\n } else {\n *s = (df / mx) * 100.0;\n }\n *v = mx * 100.0;\n}", + "test": "int main() {\n\n double h, s, v;\n\n\n\n func0(255, 255, 255, &h, &s, &v);\n\n assert(h == 0 && s == 0.0 && v == 100.0);\n\n\n\n func0(0, 215, 0, &h, &s, &v);\n\n assert(h == 120.0 && s == 100.0 && v == 84.31372549019608);\n\n\n\n func0(10, 215, 110, &h, &s, &v);\n\n assert(h == 149.26829268292684 && s == 95.34883720930233 && v == 84.31372549019608);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npxor %xmm1,%xmm1\npxor %xmm3,%xmm3\npxor %xmm4,%xmm4\npush %rbp\ncvtsi2sd %edi,%xmm1\nmov %r8,%r12\nmov %r9,%rbp\npush %rbx\ncvtsi2sd %esi,%xmm3\nmov %rcx,%rbx\ncvtsi2sd %edx,%xmm4\nsub $0x20,%rsp\nmovsd 0xd3b(%rip),%xmm0\ndivsd %xmm0,%xmm4\ndivsd %xmm0,%xmm3\nmovsd %xmm4,0x18(%rsp)\ndivsd %xmm0,%xmm1\nmovapd %xmm3,%xmm0\nmovsd %xmm3,0x10(%rsp)\nmovsd %xmm1,(%rsp)\nmovapd %xmm4,%xmm1\ncallq 1090 \nmovapd %xmm0,%xmm1\nmovsd (%rsp),%xmm0\ncallq 1090 \nmovsd 0x18(%rsp),%xmm4\nmovsd 0x10(%rsp),%xmm3\nmovsd %xmm0,0x8(%rsp)\nmovapd %xmm4,%xmm1\nmovapd %xmm3,%xmm0\ncallq 10d0 \nmovapd %xmm0,%xmm1\nmovsd (%rsp),%xmm0\ncallq 10d0 \nmovsd 0x8(%rsp),%xmm2\npxor %xmm5,%xmm5\nmovq $0x0,(%rbx)\nmovapd %xmm2,%xmm6\nsubsd %xmm0,%xmm6\ncomisd %xmm5,%xmm6\njbe 1478 \nmovsd (%rsp),%xmm1\nmovsd 0x10(%rsp),%xmm3\nmovsd 0x18(%rsp),%xmm4\nucomisd %xmm2,%xmm1\njnp 14c0 \nucomisd %xmm2,%xmm3\njnp 1560 \nucomisd %xmm2,%xmm4\njnp 1508 \nnopl 0x0(%rax)\nucomisd %xmm5,%xmm2\njp 14a0 \njne 14a0 \nmovsd 0xca0(%rip),%xmm0\nmulsd %xmm0,%xmm2\nmovsd %xmm5,(%r12)\nmovsd %xmm2,0x0(%rbp)\nadd $0x20,%rsp\npop %rbx\npop %rbp\npop %r12\nretq\ndivsd %xmm2,%xmm6\nmovsd 0xc7c(%rip),%xmm0\nmovapd %xmm6,%xmm5\nmulsd %xmm0,%xmm5\njmp 1488 \nnopw %cs:0x0(%rax,%rax,1)\njne 1460 \nsubsd %xmm4,%xmm3\nmovsd 0xc3a(%rip),%xmm1\nmovsd %xmm6,(%rsp)\nmovapd %xmm3,%xmm0\ndivsd %xmm6,%xmm0\nmulsd 0xc2d(%rip),%xmm0\naddsd %xmm1,%xmm0\ncallq 10c0 \nmovsd (%rsp),%xmm6\nmovsd 0x8(%rsp),%xmm2\npxor %xmm5,%xmm5\nmovsd %xmm0,(%rbx)\njmpq 1478 \nnopl 0x0(%rax)\njne 1478 \nmovsd (%rsp),%xmm0\nmovsd 0xbed(%rip),%xmm1\nmovsd %xmm6,(%rsp)\nmovsd %xmm2,0x8(%rsp)\nsubsd %xmm3,%xmm0\ndivsd %xmm6,%xmm0\nmulsd 0xbda(%rip),%xmm0\naddsd 0xbe2(%rip),%xmm0\ncallq 10c0 \nmovsd 0x8(%rsp),%xmm2\nmovsd (%rsp),%xmm6\npxor %xmm5,%xmm5\nmovsd %xmm0,(%rbx)\njmpq 1478 \nnopl 0x0(%rax,%rax,1)\njne 146a \nsubsd (%rsp),%xmm4\nmovsd 0xb95(%rip),%xmm1\nmovsd %xmm6,(%rsp)\nmovsd %xmm2,0x8(%rsp)\nmovapd %xmm4,%xmm0\ndivsd %xmm6,%xmm0\nmulsd 0xb82(%rip),%xmm0\naddsd 0xb82(%rip),%xmm0\njmpq 14e7 \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r12\npxor xmm1, xmm1\nmov r12, rcx\npush rbp\ncvtsi2sd xmm1, edi\nmov rbp, r8\npush rbx\nmov rbx, r9\nsub rsp, 20h\nmovsd xmm0, cs:qword_20E0\ndivsd xmm1, xmm0\nmovsd [rsp+38h+y], xmm1\npxor xmm1, xmm1\ncvtsi2sd xmm1, esi\nmovapd xmm5, xmm1\npxor xmm1, xmm1\ncvtsi2sd xmm1, edx\ndivsd xmm5, xmm0\nmovapd xmm6, xmm1\ndivsd xmm6, xmm0\nmovapd xmm0, xmm5; x\nmovsd [rsp+38h+x], xmm5\nmovapd xmm1, xmm6; y\nmovsd [rsp+38h+var_28], xmm6\ncall _fmax\nmovsd xmm1, [rsp+38h+y]; y\ncall _fmax\nmovsd xmm1, [rsp+38h+var_28]; y\nmovsd [rsp+38h+var_20], xmm0\nmovsd xmm0, [rsp+38h+x]; x\ncall _fmin\nmovsd xmm1, [rsp+38h+y]; y\ncall _fmin\nmovsd xmm2, [rsp+38h+var_20]\nmov qword ptr [r12], 0\nmovapd xmm3, xmm2\nsubsd xmm3, xmm0\npxor xmm0, xmm0\ncomisd xmm3, xmm0\njbe short loc_1478\nmovsd xmm1, [rsp+38h+y]\nucomisd xmm1, xmm2\njp short loc_144F\njz short loc_14C8\nloc_144F:\nmovsd xmm7, [rsp+38h+x]\nucomisd xmm7, xmm2\njp short loc_1461\njz loc_1570\nloc_1461:\nmovsd xmm7, [rsp+38h+var_28]\nucomisd xmm7, xmm2\njp short loc_1478\njz loc_1530\nnop dword ptr [rax+rax+00h]\nloc_1478:\npxor xmm0, xmm0\nucomisd xmm2, xmm0\njp short loc_14B0\njnz short loc_14B0\nmovsd xmm0, cs:qword_2108\npxor xmm3, xmm3\nloc_1490:\nmulsd xmm2, xmm0\nmovsd qword ptr [rbp+0], xmm3\nmovsd qword ptr [rbx], xmm2\nadd rsp, 20h\npop rbx\npop rbp\npop r12\nretn\nloc_14B0:\ndivsd xmm3, xmm2\nmovsd xmm0, cs:qword_2108\nmulsd xmm3, xmm0\njmp short loc_1490\nloc_14C8:\nmovsd xmm0, [rsp+38h+x]\nsubsd xmm0, [rsp+38h+var_28]\nfld cs:y\ndivsd xmm0, xmm3\nmulsd xmm0, cs:qword_20E8\naddsd xmm0, cs:y\nmovsd [rsp+38h+x], xmm0\nfld [rsp+38h+x]\nloc_14F8:\nfprem\nfnstsw ax\ntest ah, 4\njnz short loc_14F8\nfstp st(1)\njmp short loc_1512\nloc_1508:\nfstp st(1)\njmp short loc_1512\nloc_1510:\nfstp st(1)\nloc_1512:\nfstp [rsp+38h+y]\nmovsd xmm4, [rsp+38h+y]\nucomisd xmm4, xmm4\njp loc_15AE\nloc_1524:\nmovsd qword ptr [r12], xmm4\njmp loc_1478\nloc_1530:\nmovsd xmm0, [rsp+38h+y]\nsubsd xmm0, [rsp+38h+x]\nfld cs:y\ndivsd xmm0, xmm3\nmulsd xmm0, cs:qword_20E8\naddsd xmm0, cs:qword_2100\nmovsd [rsp+38h+x], xmm0\nfld [rsp+38h+x]\nloc_155F:\nfprem\nfnstsw ax\ntest ah, 4\njz short loc_1508\njmp short loc_155F\nloc_1570:\nmovsd xmm0, [rsp+38h+var_28]\nsubsd xmm0, [rsp+38h+y]\nfld cs:y\ndivsd xmm0, xmm3\nmulsd xmm0, cs:qword_20E8\naddsd xmm0, cs:qword_20F8\nmovsd [rsp+38h+x], xmm0\nfld [rsp+38h+x]\nloc_159F:\nfprem\nfnstsw ax\ntest ah, 4\njz loc_1510\njmp short loc_159F\nloc_15AE:\nmovsd xmm1, cs:y; y\nmovsd xmm0, [rsp+38h+x]; x\nmovsd [rsp+38h+var_20], xmm3\nmovsd [rsp+38h+var_28], xmm2\ncall _fmod\nmovsd xmm3, [rsp+38h+var_20]\nmovsd xmm2, [rsp+38h+var_28]\nmovsd xmm4, [rsp+38h+y]\njmp loc_1524", + "ida_pseudo": "void __fastcall func0(int a1, int a2, int a3, double *a4, double *a5, double *a6)\n{\n double v9; // xmm0_8\n double v10; // xmm0_8\n double v11; // xmm0_8\n double v12; // xmm3_8\n double v13; // xmm3_8\n long double v14; // fst6\n char v16; // c2\n long double v17; // fst7\n long double v18; // fst6\n char v20; // c2\n long double v21; // fst6\n char v23; // c2\n double y; // [rsp+0h] [rbp-38h]\n double x; // [rsp+8h] [rbp-30h]\n double v26; // [rsp+10h] [rbp-28h]\n double v27; // [rsp+18h] [rbp-20h]\n\n y = (double)a1 / 255.0;\n x = (double)a2 / 255.0;\n v26 = (double)a3 / 255.0;\n v9 = fmax(x, v26);\n v27 = fmax(v9, y);\n v10 = fmin(x, v26);\n v11 = fmin(v10, y);\n *a4 = 0.0;\n v12 = v27 - v11;\n if ( v27 - v11 <= 0.0 )\n goto LABEL_5;\n if ( y == v27 )\n {\n v14 = (x - v26) / v12 * 60.0 + 360.0;\n do\n v14 = __FPREM__(v14, 360.0);\n while ( v16 );\n v17 = v14;\n }\n else if ( x == v27 )\n {\n v21 = (v26 - y) / v12 * 60.0 + 120.0;\n do\n v21 = __FPREM__(v21, 360.0);\n while ( v23 );\n v17 = v21;\n }\n else\n {\n if ( v26 != v27 )\n goto LABEL_5;\n v18 = (y - x) / v12 * 60.0 + 240.0;\n do\n v18 = __FPREM__(v18, 360.0);\n while ( v20 );\n v17 = v18;\n }\n *a4 = v17;\nLABEL_5:\n if ( v27 == 0.0 )\n v13 = 0.0;\n else\n v13 = v12 / v27 * 100.0;\n *a5 = v13;\n *a6 = v27 * 100.0;\n}", + "ida_strip_asm": "sub_1390:\nendbr64\npush r12\npxor xmm1, xmm1\nmov r12, rcx\npush rbp\ncvtsi2sd xmm1, edi\nmov rbp, r8\npush rbx\nmov rbx, r9\nsub rsp, 20h\nmovsd xmm0, cs:qword_20E0\ndivsd xmm1, xmm0\nmovsd [rsp+38h+y], xmm1\npxor xmm1, xmm1\ncvtsi2sd xmm1, esi\nmovapd xmm5, xmm1\npxor xmm1, xmm1\ncvtsi2sd xmm1, edx\ndivsd xmm5, xmm0\nmovapd xmm6, xmm1\ndivsd xmm6, xmm0\nmovapd xmm0, xmm5; x\nmovsd [rsp+38h+x], xmm5\nmovapd xmm1, xmm6; y\nmovsd [rsp+38h+var_28], xmm6\ncall _fmax\nmovsd xmm1, [rsp+38h+y]; y\ncall _fmax\nmovsd xmm1, [rsp+38h+var_28]; y\nmovsd [rsp+38h+var_20], xmm0\nmovsd xmm0, [rsp+38h+x]; x\ncall _fmin\nmovsd xmm1, [rsp+38h+y]; y\ncall _fmin\nmovsd xmm2, [rsp+38h+var_20]\nmov qword ptr [r12], 0\nmovapd xmm3, xmm2\nsubsd xmm3, xmm0\npxor xmm0, xmm0\ncomisd xmm3, xmm0\njbe short loc_1478\nmovsd xmm1, [rsp+38h+y]\nucomisd xmm1, xmm2\njp short loc_144F\njz short loc_14C8\nloc_144F:\nmovsd xmm7, [rsp+38h+x]\nucomisd xmm7, xmm2\njp short loc_1461\njz loc_1570\nloc_1461:\nmovsd xmm7, [rsp+38h+var_28]\nucomisd xmm7, xmm2\njp short loc_1478\njz loc_1530\nnop dword ptr [rax+rax+00h]\nloc_1478:\npxor xmm0, xmm0\nucomisd xmm2, xmm0\njp short loc_14B0\njnz short loc_14B0\nmovsd xmm0, cs:qword_2108\npxor xmm3, xmm3\nloc_1490:\nmulsd xmm2, xmm0\nmovsd qword ptr [rbp+0], xmm3\nmovsd qword ptr [rbx], xmm2\nadd rsp, 20h\npop rbx\npop rbp\npop r12\nretn\nloc_14B0:\ndivsd xmm3, xmm2\nmovsd xmm0, cs:qword_2108\nmulsd xmm3, xmm0\njmp short loc_1490\nloc_14C8:\nmovsd xmm0, [rsp+38h+x]\nsubsd xmm0, [rsp+38h+var_28]\nfld cs:y\ndivsd xmm0, xmm3\nmulsd xmm0, cs:qword_20E8\naddsd xmm0, cs:y\nmovsd [rsp+38h+x], xmm0\nfld [rsp+38h+x]\nloc_14F8:\nfprem\nfnstsw ax\ntest ah, 4\njnz short loc_14F8\nfstp st(1)\njmp short loc_1512\nloc_1508:\nfstp st(1)\njmp short loc_1512\nloc_1510:\nfstp st(1)\nloc_1512:\nfstp [rsp+38h+y]\nmovsd xmm4, [rsp+38h+y]\nucomisd xmm4, xmm4\njp loc_15AE\nloc_1524:\nmovsd qword ptr [r12], xmm4\njmp loc_1478\nloc_1530:\nmovsd xmm0, [rsp+38h+y]\nsubsd xmm0, [rsp+38h+x]\nfld cs:y\ndivsd xmm0, xmm3\nmulsd xmm0, cs:qword_20E8\naddsd xmm0, cs:qword_2100\nmovsd [rsp+38h+x], xmm0\nfld [rsp+38h+x]\nloc_155F:\nfprem\nfnstsw ax\ntest ah, 4\njz short loc_1508\njmp short loc_155F\nloc_1570:\nmovsd xmm0, [rsp+38h+var_28]\nsubsd xmm0, [rsp+38h+y]\nfld cs:y\ndivsd xmm0, xmm3\nmulsd xmm0, cs:qword_20E8\naddsd xmm0, cs:qword_20F8\nmovsd [rsp+38h+x], xmm0\nfld [rsp+38h+x]\nloc_159F:\nfprem\nfnstsw ax\ntest ah, 4\njz loc_1510\njmp short loc_159F\nloc_15AE:\nmovsd xmm1, cs:y; y\nmovsd xmm0, [rsp+38h+x]; x\nmovsd [rsp+38h+var_20], xmm3\nmovsd [rsp+38h+var_28], xmm2\ncall _fmod\nmovsd xmm3, [rsp+38h+var_20]\nmovsd xmm2, [rsp+38h+var_28]\nmovsd xmm4, [rsp+38h+y]\njmp loc_1524", + "ida_strip_pseudo": "void __fastcall sub_1390(int a1, int a2, int a3, double *a4, double *a5, double *a6)\n{\n double v9; // xmm0_8\n double v10; // xmm0_8\n double v11; // xmm0_8\n double v12; // xmm3_8\n double v13; // xmm3_8\n long double v14; // fst6\n char v16; // c2\n long double v17; // fst7\n long double v18; // fst6\n char v20; // c2\n long double v21; // fst6\n char v23; // c2\n double y; // [rsp+0h] [rbp-38h]\n double x; // [rsp+8h] [rbp-30h]\n double v26; // [rsp+10h] [rbp-28h]\n double v27; // [rsp+18h] [rbp-20h]\n\n y = (double)a1 / 255.0;\n x = (double)a2 / 255.0;\n v26 = (double)a3 / 255.0;\n v9 = fmax(x, v26);\n v27 = fmax(v9, y);\n v10 = fmin(x, v26);\n v11 = fmin(v10, y);\n *a4 = 0.0;\n v12 = v27 - v11;\n if ( v27 - v11 <= 0.0 )\n goto LABEL_5;\n if ( y == v27 )\n {\n v14 = (x - v26) / v12 * 60.0 + 360.0;\n do\n v14 = __FPREM__(v14, 360.0);\n while ( v16 );\n v17 = v14;\n }\n else if ( x == v27 )\n {\n v21 = (v26 - y) / v12 * 60.0 + 120.0;\n do\n v21 = __FPREM__(v21, 360.0);\n while ( v23 );\n v17 = v21;\n }\n else\n {\n if ( v26 != v27 )\n goto LABEL_5;\n v18 = (y - x) / v12 * 60.0 + 240.0;\n do\n v18 = __FPREM__(v18, 360.0);\n while ( v20 );\n v17 = v18;\n }\n *a4 = v17;\nLABEL_5:\n if ( v27 == 0.0 )\n v13 = 0.0;\n else\n v13 = v12 / v27 * 100.0;\n *a5 = v13;\n *a6 = v27 * 100.0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1390(int a1, int a2, int a3, double *a4, double *a5, double *a6) {\n double v9;\n double v10;\n double v11;\n double v12;\n double v13;\n long double v14;\n char v16;\n long double v17;\n long double v18;\n char v20;\n long double v21;\n char v23;\n double y;\n double x;\n double v26;\n double v27;\n y = (double)a1 / 255.0;\n x = (double)a2 / 255.0;\n v26 = (double)a3 / 255.0;\n v9 = fmax(x, v26);\n v27 = fmax(v9, y);\n v10 = fmin(x, v26);\n v11 = fmin(v10, y);\n *a4 = 0.0;\n v12 = v27 - v11;\n if (v27 - v11 <= 0.0) goto LABEL_5;\n if (y == v27) {\n v14 = (x - v26) / v12 * 60.0 + 360.0;\n do\n v14 = __FPREM__(v14, 360.0);\n while (v16);\n v17 = v14;\n } else if (x == v27) {\n v21 = (v26 - y) / v12 * 60.0 + 120.0;\n do\n v21 = __FPREM__(v21, 360.0);\n while (v23);\n v17 = v21;\n } else {\n if (v26 != v27) goto LABEL_5;\n v18 = (y - x) / v12 * 60.0 + 240.0;\n do\n v18 = __FPREM__(v18, 360.0);\n while (v20);\n v17 = v18;\n }\n *a4 = v17;\nLABEL_5:\n if (v27 == 0.0)\n v13 = 0.0;\n else\n v13 = v12 / v27 * 100.0;\n *a5 = v13;\n *a6 = v27 * 100.0;\n}", + "ida_pseudo_norm": "void func0(int a1, int a2, int a3, double *a4, double *a5, double *a6) {\n double v9;\n double v10;\n double v11;\n double v12;\n double v13;\n long double v14;\n char v16;\n long double v17;\n long double v18;\n char v20;\n long double v21;\n char v23;\n double y;\n double x;\n double v26;\n double v27;\n y = (double)a1 / 255.0;\n x = (double)a2 / 255.0;\n v26 = (double)a3 / 255.0;\n v9 = fmax(x, v26);\n v27 = fmax(v9, y);\n v10 = fmin(x, v26);\n v11 = fmin(v10, y);\n *a4 = 0.0;\n v12 = v27 - v11;\n if (v27 - v11 <= 0.0) goto LABEL_5;\n if (y == v27) {\n v14 = (x - v26) / v12 * 60.0 + 360.0;\n do\n v14 = __FPREM__(v14, 360.0);\n while (v16);\n v17 = v14;\n } else if (x == v27) {\n v21 = (v26 - y) / v12 * 60.0 + 120.0;\n do\n v21 = __FPREM__(v21, 360.0);\n while (v23);\n v17 = v21;\n } else {\n if (v26 != v27) goto LABEL_5;\n v18 = (y - x) / v12 * 60.0 + 240.0;\n do\n v18 = __FPREM__(v18, 360.0);\n while (v20);\n v17 = v18;\n }\n *a4 = v17;\nLABEL_5:\n if (v27 == 0.0)\n v13 = 0.0;\n else\n v13 = v12 / v27 * 100.0;\n *a5 = v13;\n *a6 = v27 * 100.0;\n}" + }, + { + "index": 783, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int r, int g, int b, double *h, double *s, double *v) {\n double rd = r / 255.0;\n double gd = g / 255.0;\n double bd = b / 255.0;\n double mx = fmax(rd, fmax(gd, bd));\n double mn = fmin(rd, fmin(gd, bd));\n double df = mx - mn;\n *h = 0;\n if (df > 0) {\n if (mx == rd) {\n *h = fmod((60.0 * ((gd - bd) / df) + 360.0), 360.0);\n } else if (mx == gd) {\n *h = fmod((60.0 * ((bd - rd) / df) + 120.0), 360.0);\n } else if (mx == bd) {\n *h = fmod((60.0 * ((rd - gd) / df) + 240.0), 360.0);\n }\n }\n if (mx == 0) {\n *s = 0;\n } else {\n *s = (df / mx) * 100.0;\n }\n *v = mx * 100.0;\n}", + "test": "int main() {\n\n double h, s, v;\n\n\n\n func0(255, 255, 255, &h, &s, &v);\n\n assert(h == 0 && s == 0.0 && v == 100.0);\n\n\n\n func0(0, 215, 0, &h, &s, &v);\n\n assert(h == 120.0 && s == 100.0 && v == 84.31372549019608);\n\n\n\n func0(10, 215, 110, &h, &s, &v);\n\n assert(h == 149.26829268292684 && s == 95.34883720930233 && v == 84.31372549019608);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npxor %xmm1,%xmm1\npxor %xmm3,%xmm3\npxor %xmm4,%xmm4\npush %rbp\ncvtsi2sd %edi,%xmm1\nmov %r8,%r12\nmov %r9,%rbp\npush %rbx\ncvtsi2sd %esi,%xmm3\nmov %rcx,%rbx\ncvtsi2sd %edx,%xmm4\nsub $0x20,%rsp\nmovsd 0xd3b(%rip),%xmm0\ndivsd %xmm0,%xmm4\ndivsd %xmm0,%xmm3\nmovsd %xmm4,0x18(%rsp)\ndivsd %xmm0,%xmm1\nmovapd %xmm3,%xmm0\nmovsd %xmm3,0x10(%rsp)\nmovsd %xmm1,(%rsp)\nmovapd %xmm4,%xmm1\ncallq 1090 \nmovapd %xmm0,%xmm1\nmovsd (%rsp),%xmm0\ncallq 1090 \nmovsd 0x18(%rsp),%xmm4\nmovsd 0x10(%rsp),%xmm3\nmovsd %xmm0,0x8(%rsp)\nmovapd %xmm4,%xmm1\nmovapd %xmm3,%xmm0\ncallq 10d0 \nmovapd %xmm0,%xmm1\nmovsd (%rsp),%xmm0\ncallq 10d0 \nmovsd 0x8(%rsp),%xmm2\npxor %xmm5,%xmm5\nmovq $0x0,(%rbx)\nmovapd %xmm2,%xmm6\nsubsd %xmm0,%xmm6\ncomisd %xmm5,%xmm6\njbe 1478 \nmovsd (%rsp),%xmm1\nmovsd 0x10(%rsp),%xmm3\nmovsd 0x18(%rsp),%xmm4\nucomisd %xmm2,%xmm1\njnp 14c0 \nucomisd %xmm2,%xmm3\njnp 1560 \nucomisd %xmm2,%xmm4\njnp 1508 \nnopl 0x0(%rax)\nucomisd %xmm5,%xmm2\njp 14a0 \njne 14a0 \nmovsd 0xca0(%rip),%xmm0\nmulsd %xmm0,%xmm2\nmovsd %xmm5,(%r12)\nmovsd %xmm2,0x0(%rbp)\nadd $0x20,%rsp\npop %rbx\npop %rbp\npop %r12\nretq\ndivsd %xmm2,%xmm6\nmovsd 0xc7c(%rip),%xmm0\nmovapd %xmm6,%xmm5\nmulsd %xmm0,%xmm5\njmp 1488 \nnopw %cs:0x0(%rax,%rax,1)\njne 1460 \nsubsd %xmm4,%xmm3\nmovsd 0xc3a(%rip),%xmm1\nmovsd %xmm6,(%rsp)\nmovapd %xmm3,%xmm0\ndivsd %xmm6,%xmm0\nmulsd 0xc2d(%rip),%xmm0\naddsd %xmm1,%xmm0\ncallq 10c0 \nmovsd (%rsp),%xmm6\nmovsd 0x8(%rsp),%xmm2\npxor %xmm5,%xmm5\nmovsd %xmm0,(%rbx)\njmpq 1478 \nnopl 0x0(%rax)\njne 1478 \nmovsd (%rsp),%xmm0\nmovsd 0xbed(%rip),%xmm1\nmovsd %xmm6,(%rsp)\nmovsd %xmm2,0x8(%rsp)\nsubsd %xmm3,%xmm0\ndivsd %xmm6,%xmm0\nmulsd 0xbda(%rip),%xmm0\naddsd 0xbe2(%rip),%xmm0\ncallq 10c0 \nmovsd 0x8(%rsp),%xmm2\nmovsd (%rsp),%xmm6\npxor %xmm5,%xmm5\nmovsd %xmm0,(%rbx)\njmpq 1478 \nnopl 0x0(%rax,%rax,1)\njne 146a \nsubsd (%rsp),%xmm4\nmovsd 0xb95(%rip),%xmm1\nmovsd %xmm6,(%rsp)\nmovsd %xmm2,0x8(%rsp)\nmovapd %xmm4,%xmm0\ndivsd %xmm6,%xmm0\nmulsd 0xb82(%rip),%xmm0\naddsd 0xb82(%rip),%xmm0\njmpq 14e7 \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r12\npxor xmm1, xmm1\nmov r12, rcx\npush rbp\ncvtsi2sd xmm1, edi\nmov rbp, r8\npush rbx\nmov rbx, r9\nsub rsp, 20h\nmovsd xmm0, cs:qword_20E0\ndivsd xmm1, xmm0\nmovsd [rsp+38h+y], xmm1\npxor xmm1, xmm1\ncvtsi2sd xmm1, esi\nmovapd xmm5, xmm1\npxor xmm1, xmm1\ncvtsi2sd xmm1, edx\ndivsd xmm5, xmm0\nmovapd xmm6, xmm1\ndivsd xmm6, xmm0\nmovapd xmm0, xmm5; x\nmovsd [rsp+38h+x], xmm5\nmovapd xmm1, xmm6; y\nmovsd [rsp+38h+var_28], xmm6\ncall _fmax\nmovsd xmm1, [rsp+38h+y]; y\ncall _fmax\nmovsd xmm1, [rsp+38h+var_28]; y\nmovsd [rsp+38h+var_20], xmm0\nmovsd xmm0, [rsp+38h+x]; x\ncall _fmin\nmovsd xmm1, [rsp+38h+y]; y\ncall _fmin\nmovsd xmm2, [rsp+38h+var_20]\nmov qword ptr [r12], 0\nmovapd xmm3, xmm2\nsubsd xmm3, xmm0\npxor xmm0, xmm0\ncomisd xmm3, xmm0\njbe short loc_1478\nmovsd xmm1, [rsp+38h+y]\nucomisd xmm1, xmm2\njp short loc_144F\njz short loc_14C8\nloc_144F:\nmovsd xmm7, [rsp+38h+x]\nucomisd xmm7, xmm2\njp short loc_1461\njz loc_1570\nloc_1461:\nmovsd xmm7, [rsp+38h+var_28]\nucomisd xmm7, xmm2\njp short loc_1478\njz loc_1530\nnop dword ptr [rax+rax+00h]\nloc_1478:\npxor xmm0, xmm0\nucomisd xmm2, xmm0\njp short loc_14B0\njnz short loc_14B0\nmovsd xmm0, cs:qword_2108\npxor xmm3, xmm3\nloc_1490:\nmulsd xmm2, xmm0\nmovsd qword ptr [rbp+0], xmm3\nmovsd qword ptr [rbx], xmm2\nadd rsp, 20h\npop rbx\npop rbp\npop r12\nretn\nloc_14B0:\ndivsd xmm3, xmm2\nmovsd xmm0, cs:qword_2108\nmulsd xmm3, xmm0\njmp short loc_1490\nloc_14C8:\nmovsd xmm0, [rsp+38h+x]\nsubsd xmm0, [rsp+38h+var_28]\nfld cs:y\ndivsd xmm0, xmm3\nmulsd xmm0, cs:qword_20E8\naddsd xmm0, cs:y\nmovsd [rsp+38h+x], xmm0\nfld [rsp+38h+x]\nloc_14F8:\nfprem\nfnstsw ax\ntest ah, 4\njnz short loc_14F8\nfstp st(1)\njmp short loc_1512\nloc_1508:\nfstp st(1)\njmp short loc_1512\nloc_1510:\nfstp st(1)\nloc_1512:\nfstp [rsp+38h+y]\nmovsd xmm4, [rsp+38h+y]\nucomisd xmm4, xmm4\njp loc_15AE\nloc_1524:\nmovsd qword ptr [r12], xmm4\njmp loc_1478\nloc_1530:\nmovsd xmm0, [rsp+38h+y]\nsubsd xmm0, [rsp+38h+x]\nfld cs:y\ndivsd xmm0, xmm3\nmulsd xmm0, cs:qword_20E8\naddsd xmm0, cs:qword_2100\nmovsd [rsp+38h+x], xmm0\nfld [rsp+38h+x]\nloc_155F:\nfprem\nfnstsw ax\ntest ah, 4\njz short loc_1508\njmp short loc_155F\nloc_1570:\nmovsd xmm0, [rsp+38h+var_28]\nsubsd xmm0, [rsp+38h+y]\nfld cs:y\ndivsd xmm0, xmm3\nmulsd xmm0, cs:qword_20E8\naddsd xmm0, cs:qword_20F8\nmovsd [rsp+38h+x], xmm0\nfld [rsp+38h+x]\nloc_159F:\nfprem\nfnstsw ax\ntest ah, 4\njz loc_1510\njmp short loc_159F\nloc_15AE:\nmovsd xmm1, cs:y; y\nmovsd xmm0, [rsp+38h+x]; x\nmovsd [rsp+38h+var_20], xmm3\nmovsd [rsp+38h+var_28], xmm2\ncall _fmod\nmovsd xmm3, [rsp+38h+var_20]\nmovsd xmm2, [rsp+38h+var_28]\nmovsd xmm4, [rsp+38h+y]\njmp loc_1524", + "ida_pseudo": "void __fastcall func0(int a1, int a2, int a3, double *a4, double *a5, double *a6)\n{\n double v9; // xmm0_8\n double v10; // xmm0_8\n double v11; // xmm0_8\n double v12; // xmm3_8\n double v13; // xmm3_8\n long double v14; // fst6\n char v16; // c2\n long double v17; // fst7\n long double v18; // fst6\n char v20; // c2\n long double v21; // fst6\n char v23; // c2\n double y; // [rsp+0h] [rbp-38h]\n double x; // [rsp+8h] [rbp-30h]\n double v26; // [rsp+10h] [rbp-28h]\n double v27; // [rsp+18h] [rbp-20h]\n\n y = (double)a1 / 255.0;\n x = (double)a2 / 255.0;\n v26 = (double)a3 / 255.0;\n v9 = fmax(x, v26);\n v27 = fmax(v9, y);\n v10 = fmin(x, v26);\n v11 = fmin(v10, y);\n *a4 = 0.0;\n v12 = v27 - v11;\n if ( v27 - v11 <= 0.0 )\n goto LABEL_5;\n if ( y == v27 )\n {\n v14 = (x - v26) / v12 * 60.0 + 360.0;\n do\n v14 = __FPREM__(v14, 360.0);\n while ( v16 );\n v17 = v14;\n }\n else if ( x == v27 )\n {\n v21 = (v26 - y) / v12 * 60.0 + 120.0;\n do\n v21 = __FPREM__(v21, 360.0);\n while ( v23 );\n v17 = v21;\n }\n else\n {\n if ( v26 != v27 )\n goto LABEL_5;\n v18 = (y - x) / v12 * 60.0 + 240.0;\n do\n v18 = __FPREM__(v18, 360.0);\n while ( v20 );\n v17 = v18;\n }\n *a4 = v17;\nLABEL_5:\n if ( v27 == 0.0 )\n v13 = 0.0;\n else\n v13 = v12 / v27 * 100.0;\n *a5 = v13;\n *a6 = v27 * 100.0;\n}", + "ida_strip_asm": "sub_1390:\nendbr64\npush r12\npxor xmm1, xmm1\nmov r12, rcx\npush rbp\ncvtsi2sd xmm1, edi\nmov rbp, r8\npush rbx\nmov rbx, r9\nsub rsp, 20h\nmovsd xmm0, cs:qword_20E0\ndivsd xmm1, xmm0\nmovsd [rsp+38h+y], xmm1\npxor xmm1, xmm1\ncvtsi2sd xmm1, esi\nmovapd xmm5, xmm1\npxor xmm1, xmm1\ncvtsi2sd xmm1, edx\ndivsd xmm5, xmm0\nmovapd xmm6, xmm1\ndivsd xmm6, xmm0\nmovapd xmm0, xmm5; x\nmovsd [rsp+38h+x], xmm5\nmovapd xmm1, xmm6; y\nmovsd [rsp+38h+var_28], xmm6\ncall _fmax\nmovsd xmm1, [rsp+38h+y]; y\ncall _fmax\nmovsd xmm1, [rsp+38h+var_28]; y\nmovsd [rsp+38h+var_20], xmm0\nmovsd xmm0, [rsp+38h+x]; x\ncall _fmin\nmovsd xmm1, [rsp+38h+y]; y\ncall _fmin\nmovsd xmm2, [rsp+38h+var_20]\nmov qword ptr [r12], 0\nmovapd xmm3, xmm2\nsubsd xmm3, xmm0\npxor xmm0, xmm0\ncomisd xmm3, xmm0\njbe short loc_1478\nmovsd xmm1, [rsp+38h+y]\nucomisd xmm1, xmm2\njp short loc_144F\njz short loc_14C8\nloc_144F:\nmovsd xmm7, [rsp+38h+x]\nucomisd xmm7, xmm2\njp short loc_1461\njz loc_1570\nloc_1461:\nmovsd xmm7, [rsp+38h+var_28]\nucomisd xmm7, xmm2\njp short loc_1478\njz loc_1530\nnop dword ptr [rax+rax+00h]\nloc_1478:\npxor xmm0, xmm0\nucomisd xmm2, xmm0\njp short loc_14B0\njnz short loc_14B0\nmovsd xmm0, cs:qword_2108\npxor xmm3, xmm3\nloc_1490:\nmulsd xmm2, xmm0\nmovsd qword ptr [rbp+0], xmm3\nmovsd qword ptr [rbx], xmm2\nadd rsp, 20h\npop rbx\npop rbp\npop r12\nretn\nloc_14B0:\ndivsd xmm3, xmm2\nmovsd xmm0, cs:qword_2108\nmulsd xmm3, xmm0\njmp short loc_1490\nloc_14C8:\nmovsd xmm0, [rsp+38h+x]\nsubsd xmm0, [rsp+38h+var_28]\nfld cs:y\ndivsd xmm0, xmm3\nmulsd xmm0, cs:qword_20E8\naddsd xmm0, cs:y\nmovsd [rsp+38h+x], xmm0\nfld [rsp+38h+x]\nloc_14F8:\nfprem\nfnstsw ax\ntest ah, 4\njnz short loc_14F8\nfstp st(1)\njmp short loc_1512\nloc_1508:\nfstp st(1)\njmp short loc_1512\nloc_1510:\nfstp st(1)\nloc_1512:\nfstp [rsp+38h+y]\nmovsd xmm4, [rsp+38h+y]\nucomisd xmm4, xmm4\njp loc_15AE\nloc_1524:\nmovsd qword ptr [r12], xmm4\njmp loc_1478\nloc_1530:\nmovsd xmm0, [rsp+38h+y]\nsubsd xmm0, [rsp+38h+x]\nfld cs:y\ndivsd xmm0, xmm3\nmulsd xmm0, cs:qword_20E8\naddsd xmm0, cs:qword_2100\nmovsd [rsp+38h+x], xmm0\nfld [rsp+38h+x]\nloc_155F:\nfprem\nfnstsw ax\ntest ah, 4\njz short loc_1508\njmp short loc_155F\nloc_1570:\nmovsd xmm0, [rsp+38h+var_28]\nsubsd xmm0, [rsp+38h+y]\nfld cs:y\ndivsd xmm0, xmm3\nmulsd xmm0, cs:qword_20E8\naddsd xmm0, cs:qword_20F8\nmovsd [rsp+38h+x], xmm0\nfld [rsp+38h+x]\nloc_159F:\nfprem\nfnstsw ax\ntest ah, 4\njz loc_1510\njmp short loc_159F\nloc_15AE:\nmovsd xmm1, cs:y; y\nmovsd xmm0, [rsp+38h+x]; x\nmovsd [rsp+38h+var_20], xmm3\nmovsd [rsp+38h+var_28], xmm2\ncall _fmod\nmovsd xmm3, [rsp+38h+var_20]\nmovsd xmm2, [rsp+38h+var_28]\nmovsd xmm4, [rsp+38h+y]\njmp loc_1524", + "ida_strip_pseudo": "void __fastcall sub_1390(int a1, int a2, int a3, double *a4, double *a5, double *a6)\n{\n double v9; // xmm0_8\n double v10; // xmm0_8\n double v11; // xmm0_8\n double v12; // xmm3_8\n double v13; // xmm3_8\n long double v14; // fst6\n char v16; // c2\n long double v17; // fst7\n long double v18; // fst6\n char v20; // c2\n long double v21; // fst6\n char v23; // c2\n double y; // [rsp+0h] [rbp-38h]\n double x; // [rsp+8h] [rbp-30h]\n double v26; // [rsp+10h] [rbp-28h]\n double v27; // [rsp+18h] [rbp-20h]\n\n y = (double)a1 / 255.0;\n x = (double)a2 / 255.0;\n v26 = (double)a3 / 255.0;\n v9 = fmax(x, v26);\n v27 = fmax(v9, y);\n v10 = fmin(x, v26);\n v11 = fmin(v10, y);\n *a4 = 0.0;\n v12 = v27 - v11;\n if ( v27 - v11 <= 0.0 )\n goto LABEL_5;\n if ( y == v27 )\n {\n v14 = (x - v26) / v12 * 60.0 + 360.0;\n do\n v14 = __FPREM__(v14, 360.0);\n while ( v16 );\n v17 = v14;\n }\n else if ( x == v27 )\n {\n v21 = (v26 - y) / v12 * 60.0 + 120.0;\n do\n v21 = __FPREM__(v21, 360.0);\n while ( v23 );\n v17 = v21;\n }\n else\n {\n if ( v26 != v27 )\n goto LABEL_5;\n v18 = (y - x) / v12 * 60.0 + 240.0;\n do\n v18 = __FPREM__(v18, 360.0);\n while ( v20 );\n v17 = v18;\n }\n *a4 = v17;\nLABEL_5:\n if ( v27 == 0.0 )\n v13 = 0.0;\n else\n v13 = v12 / v27 * 100.0;\n *a5 = v13;\n *a6 = v27 * 100.0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1390(int a1, int a2, int a3, double *a4, double *a5, double *a6) {\n double v9;\n double v10;\n double v11;\n double v12;\n double v13;\n long double v14;\n char v16;\n long double v17;\n long double v18;\n char v20;\n long double v21;\n char v23;\n double y;\n double x;\n double v26;\n double v27;\n y = (double)a1 / 255.0;\n x = (double)a2 / 255.0;\n v26 = (double)a3 / 255.0;\n v9 = fmax(x, v26);\n v27 = fmax(v9, y);\n v10 = fmin(x, v26);\n v11 = fmin(v10, y);\n *a4 = 0.0;\n v12 = v27 - v11;\n if (v27 - v11 <= 0.0) goto LABEL_5;\n if (y == v27) {\n v14 = (x - v26) / v12 * 60.0 + 360.0;\n do\n v14 = __FPREM__(v14, 360.0);\n while (v16);\n v17 = v14;\n } else if (x == v27) {\n v21 = (v26 - y) / v12 * 60.0 + 120.0;\n do\n v21 = __FPREM__(v21, 360.0);\n while (v23);\n v17 = v21;\n } else {\n if (v26 != v27) goto LABEL_5;\n v18 = (y - x) / v12 * 60.0 + 240.0;\n do\n v18 = __FPREM__(v18, 360.0);\n while (v20);\n v17 = v18;\n }\n *a4 = v17;\nLABEL_5:\n if (v27 == 0.0)\n v13 = 0.0;\n else\n v13 = v12 / v27 * 100.0;\n *a5 = v13;\n *a6 = v27 * 100.0;\n}", + "ida_pseudo_norm": "void func0(int a1, int a2, int a3, double *a4, double *a5, double *a6) {\n double v9;\n double v10;\n double v11;\n double v12;\n double v13;\n long double v14;\n char v16;\n long double v17;\n long double v18;\n char v20;\n long double v21;\n char v23;\n double y;\n double x;\n double v26;\n double v27;\n y = (double)a1 / 255.0;\n x = (double)a2 / 255.0;\n v26 = (double)a3 / 255.0;\n v9 = fmax(x, v26);\n v27 = fmax(v9, y);\n v10 = fmin(x, v26);\n v11 = fmin(v10, y);\n *a4 = 0.0;\n v12 = v27 - v11;\n if (v27 - v11 <= 0.0) goto LABEL_5;\n if (y == v27) {\n v14 = (x - v26) / v12 * 60.0 + 360.0;\n do\n v14 = __FPREM__(v14, 360.0);\n while (v16);\n v17 = v14;\n } else if (x == v27) {\n v21 = (v26 - y) / v12 * 60.0 + 120.0;\n do\n v21 = __FPREM__(v21, 360.0);\n while (v23);\n v17 = v21;\n } else {\n if (v26 != v27) goto LABEL_5;\n v18 = (y - x) / v12 * 60.0 + 240.0;\n do\n v18 = __FPREM__(v18, 360.0);\n while (v20);\n v17 = v18;\n }\n *a4 = v17;\nLABEL_5:\n if (v27 == 0.0)\n v13 = 0.0;\n else\n v13 = v12 / v27 * 100.0;\n *a5 = v13;\n *a6 = v27 * 100.0;\n}" + }, + { + "index": 784, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int list1[], int n) {\n int first_even = -1;\n int first_odd = -1;\n for (int i = 0; i < n; i++) {\n if (list1[i] % 2 == 0 && first_even == -1) {\n first_even = list1[i];\n }\n if (list1[i] % 2 != 0 && first_odd == -1) {\n first_odd = list1[i];\n }\n if (first_even != -1 && first_odd != -1) {\n break;\n }\n }\n return first_even * first_odd;\n}", + "test": "int main() {\n\n int list1[] = {1,3,5,7,4,1,6,8};\n\n int n1 = sizeof(list1) / sizeof(list1[0]);\n\n assert(func0(list1, n1) == 4);\n\n\n\n int list2[] = {1,2,3,4,5,6,7,8,9,10};\n\n int n2 = sizeof(list2) / sizeof(list2[0]);\n\n assert(func0(list2, n2) == 2);\n\n \n\n int list3[] = {1,5,7,9,10};\n\n int n3 = sizeof(list3) / sizeof(list3[0]);\n\n assert(func0(list3, n3) == 10);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0xffffffff,-0xc(%rbp)\nmovl $0xffffffff,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmpq 121a \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nand $0x1,%eax\ntest %eax,%eax\njne 11ce \ncmpl $0xffffffff,-0xc(%rbp)\njne 11ce \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0xc(%rbp)\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nand $0x1,%eax\ntest %eax,%eax\nje 120a \ncmpl $0xffffffff,-0x8(%rbp)\njne 120a \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x8(%rbp)\ncmpl $0xffffffff,-0xc(%rbp)\nje 1216 \ncmpl $0xffffffff,-0x8(%rbp)\njne 1228 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1192 \njmp 1229 \nmov -0xc(%rbp),%eax\nimul -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0FFFFFFFFh\nmov [rbp+var_8], 0FFFFFFFFh\nmov [rbp+var_4], 0\njmp loc_121A\nloc_1192:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njnz short loc_11CE\ncmp [rbp+var_C], 0FFFFFFFFh\njnz short loc_11CE\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nloc_11CE:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njz short loc_120A\ncmp [rbp+var_8], 0FFFFFFFFh\njnz short loc_120A\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_8], eax\nloc_120A:\ncmp [rbp+var_C], 0FFFFFFFFh\njz short loc_1216\ncmp [rbp+var_8], 0FFFFFFFFh\njnz short loc_1228\nloc_1216:\nadd [rbp+var_4], 1\nloc_121A:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl loc_1192\njmp short loc_1229\nloc_1228:\nnop\nloc_1229:\nmov eax, [rbp+var_C]\nimul eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int v3; // [rsp+10h] [rbp-Ch]\n int v4; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = -1;\n v4 = -1;\n for ( i = 0; i < a2; ++i )\n {\n if ( (*(_DWORD *)(4LL * i + a1) & 1) == 0 && v3 == -1 )\n v3 = *(_DWORD *)(4LL * i + a1);\n if ( (*(_DWORD *)(4LL * i + a1) & 1) != 0 && v4 == -1 )\n v4 = *(_DWORD *)(4LL * i + a1);\n if ( v3 != -1 && v4 != -1 )\n break;\n }\n return (unsigned int)(v4 * v3);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0FFFFFFFFh\nmov [rbp+var_8], 0FFFFFFFFh\nmov [rbp+var_4], 0\njmp loc_121A\nloc_1192:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njnz short loc_11CE\ncmp [rbp+var_C], 0FFFFFFFFh\njnz short loc_11CE\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nloc_11CE:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njz short loc_120A\ncmp [rbp+var_8], 0FFFFFFFFh\njnz short loc_120A\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_8], eax\nloc_120A:\ncmp [rbp+var_C], 0FFFFFFFFh\njz short loc_1216\ncmp [rbp+var_8], 0FFFFFFFFh\njnz short loc_1228\nloc_1216:\nadd [rbp+var_4], 1\nloc_121A:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl loc_1192\njmp short loc_1229\nloc_1228:\nnop\nloc_1229:\nmov eax, [rbp+var_C]\nimul eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int v3; // [rsp+10h] [rbp-Ch]\n int v4; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = -1;\n v4 = -1;\n for ( i = 0; i < a2; ++i )\n {\n if ( (*(_DWORD *)(4LL * i + a1) & 1) == 0 && v3 == -1 )\n v3 = *(_DWORD *)(4LL * i + a1);\n if ( (*(_DWORD *)(4LL * i + a1) & 1) != 0 && v4 == -1 )\n v4 = *(_DWORD *)(4LL * i + a1);\n if ( v3 != -1 && v4 != -1 )\n break;\n }\n return (unsigned int)(v4 * v3);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int v3;\n int v4;\n int i;\n v3 = -1;\n v4 = -1;\n for (i = 0; i < a2; ++i) {\n if ((*(uint32_t *)(4LL * i + a1) & 1) == 0 && v3 == -1)\n v3 = *(uint32_t *)(4LL * i + a1);\n if ((*(uint32_t *)(4LL * i + a1) & 1) != 0 && v4 == -1)\n v4 = *(uint32_t *)(4LL * i + a1);\n if (v3 != -1 && v4 != -1) break;\n }\n return (unsigned int)(v4 * v3);\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int v3;\n int v4;\n int i;\n v3 = -1;\n v4 = -1;\n for (i = 0; i < a2; ++i) {\n if ((*(uint32_t *)(4LL * i + a1) & 1) == 0 && v3 == -1)\n v3 = *(uint32_t *)(4LL * i + a1);\n if ((*(uint32_t *)(4LL * i + a1) & 1) != 0 && v4 == -1)\n v4 = *(uint32_t *)(4LL * i + a1);\n if (v3 != -1 && v4 != -1) break;\n }\n return (unsigned int)(v4 * v3);\n}" + }, + { + "index": 784, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int list1[], int n) {\n int first_even = -1;\n int first_odd = -1;\n for (int i = 0; i < n; i++) {\n if (list1[i] % 2 == 0 && first_even == -1) {\n first_even = list1[i];\n }\n if (list1[i] % 2 != 0 && first_odd == -1) {\n first_odd = list1[i];\n }\n if (first_even != -1 && first_odd != -1) {\n break;\n }\n }\n return first_even * first_odd;\n}", + "test": "int main() {\n\n int list1[] = {1,3,5,7,4,1,6,8};\n\n int n1 = sizeof(list1) / sizeof(list1[0]);\n\n assert(func0(list1, n1) == 4);\n\n\n\n int list2[] = {1,2,3,4,5,6,7,8,9,10};\n\n int n2 = sizeof(list2) / sizeof(list2[0]);\n\n assert(func0(list2, n2) == 2);\n\n \n\n int list3[] = {1,5,7,9,10};\n\n int n3 = sizeof(list3) / sizeof(list3[0]);\n\n assert(func0(list3, n3) == 10);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11b9 \nmov %rdi,%rdx\nlea -0x1(%rsi),%eax\nlea 0x4(%rdi,%rax,4),%r8\nmov $0xffffffff,%esi\nmov $0xffffffff,%eax\njmp 11a5 \ncmp $0xffffffff,%esi\njne 1192 \ntest %edi,%edi\ncmovne %ecx,%esi\ncmp $0xffffffff,%eax\nje 119c \ncmp $0xffffffff,%esi\njne 11c3 \nadd $0x4,%rdx\ncmp %r8,%rdx\nje 11c3 \nmov (%rdx),%ecx\nmov %ecx,%edi\nand $0x1,%edi\ncmp $0xffffffff,%eax\njne 1188 \ntest %edi,%edi\njne 1188 \nmov %ecx,%eax\njmp 1192 \nmov $0xffffffff,%esi\nmov $0xffffffff,%eax\nimul %esi,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11B8\nmov rdx, rdi\nmovsxd rsi, esi\nlea r8, [rdi+rsi*4]\nmov esi, 0FFFFFFFFh\nmov eax, 0FFFFFFFFh\njmp short loc_11A4\nloc_1187:\ncmp esi, 0FFFFFFFFh\njnz short loc_1191\ntest edi, edi\ncmovnz esi, ecx\nloc_1191:\ncmp eax, 0FFFFFFFFh\njz short loc_119B\ncmp esi, 0FFFFFFFFh\njnz short loc_11C2\nloc_119B:\nadd rdx, 4\ncmp rdx, r8\njz short loc_11C2\nloc_11A4:\nmov ecx, [rdx]\nmov edi, ecx\nand edi, 1\ncmp eax, 0FFFFFFFFh\njnz short loc_1187\ntest edi, edi\njnz short loc_1187\nmov eax, ecx\njmp short loc_1191\nloc_11B8:\nmov esi, 0FFFFFFFFh\nmov eax, 0FFFFFFFFh\nloc_11C2:\nimul eax, esi\nretn", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int *v2; // rdx\n int *v3; // r8\n int v4; // esi\n int v5; // eax\n int v6; // edi\n\n if ( a2 <= 0 )\n {\n v4 = -1;\n v5 = -1;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = -1;\n v5 = -1;\n do\n {\n v6 = *v2 & 1;\n if ( v5 != -1 || v6 )\n {\n if ( v4 == -1 && v6 )\n v4 = *v2;\n }\n else\n {\n v5 = *v2;\n }\n if ( v5 != -1 && v4 != -1 )\n break;\n ++v2;\n }\n while ( v2 != v3 );\n }\n return (unsigned int)(v4 * v5);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11B8\nmov rdx, rdi\nmovsxd rsi, esi\nlea r8, [rdi+rsi*4]\nmov esi, 0FFFFFFFFh\nmov eax, 0FFFFFFFFh\njmp short loc_11A4\nloc_1187:\ncmp esi, 0FFFFFFFFh\njnz short loc_1191\ntest edi, edi\ncmovnz esi, ecx\nloc_1191:\ncmp eax, 0FFFFFFFFh\njz short loc_119B\ncmp esi, 0FFFFFFFFh\njnz short loc_11C2\nloc_119B:\nadd rdx, 4\ncmp rdx, r8\njz short loc_11C2\nloc_11A4:\nmov ecx, [rdx]\nmov edi, ecx\nand edi, 1\ncmp eax, 0FFFFFFFFh\njnz short loc_1187\ntest edi, edi\njnz short loc_1187\nmov eax, ecx\njmp short loc_1191\nloc_11B8:\nmov esi, 0FFFFFFFFh\nmov eax, 0FFFFFFFFh\nloc_11C2:\nimul eax, esi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int *a1, int a2)\n{\n int *v2; // rdx\n int *v3; // r8\n int v4; // esi\n int v5; // eax\n int v6; // edi\n\n if ( a2 <= 0 )\n {\n v4 = -1;\n v5 = -1;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = -1;\n v5 = -1;\n do\n {\n v6 = *v2 & 1;\n if ( v5 != -1 || v6 )\n {\n if ( v4 == -1 && v6 )\n v4 = *v2;\n }\n else\n {\n v5 = *v2;\n }\n if ( v5 != -1 && v4 != -1 )\n break;\n ++v2;\n }\n while ( v2 != v3 );\n }\n return (unsigned int)(v4 * v5);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int *a1, int a2) {\n int *v2;\n int *v3;\n int v4;\n int v5;\n int v6;\n if (a2 <= 0) {\n v4 = -1;\n v5 = -1;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = -1;\n v5 = -1;\n do {\n v6 = *v2 & 1;\n if (v5 != -1 || v6) {\n if (v4 == -1 && v6) v4 = *v2;\n } else {\n v5 = *v2;\n }\n if (v5 != -1 && v4 != -1) break;\n ++v2;\n } while (v2 != v3);\n }\n return (unsigned int)(v4 * v5);\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int *v2;\n int *v3;\n int v4;\n int v5;\n int v6;\n if (a2 <= 0) {\n v4 = -1;\n v5 = -1;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = -1;\n v5 = -1;\n do {\n v6 = *v2 & 1;\n if (v5 != -1 || v6) {\n if (v4 == -1 && v6) v4 = *v2;\n } else {\n v5 = *v2;\n }\n if (v5 != -1 && v4 != -1) break;\n ++v2;\n } while (v2 != v3);\n }\n return (unsigned int)(v4 * v5);\n}" + }, + { + "index": 784, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int list1[], int n) {\n int first_even = -1;\n int first_odd = -1;\n for (int i = 0; i < n; i++) {\n if (list1[i] % 2 == 0 && first_even == -1) {\n first_even = list1[i];\n }\n if (list1[i] % 2 != 0 && first_odd == -1) {\n first_odd = list1[i];\n }\n if (first_even != -1 && first_odd != -1) {\n break;\n }\n }\n return first_even * first_odd;\n}", + "test": "int main() {\n\n int list1[] = {1,3,5,7,4,1,6,8};\n\n int n1 = sizeof(list1) / sizeof(list1[0]);\n\n assert(func0(list1, n1) == 4);\n\n\n\n int list2[] = {1,2,3,4,5,6,7,8,9,10};\n\n int n2 = sizeof(list2) / sizeof(list2[0]);\n\n assert(func0(list2, n2) == 2);\n\n \n\n int list3[] = {1,5,7,9,10};\n\n int n3 = sizeof(list3) / sizeof(list3[0]);\n\n assert(func0(list3, n3) == 10);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1344 \nlea -0x1(%rsi),%eax\nmov $0xffffffff,%ecx\nlea 0x4(%rdi,%rax,4),%rsi\nmov $0xffffffff,%eax\njmp 1329 \nnopl 0x0(%rax)\ncmp $0xffffffff,%eax\ncmove %edx,%eax\ncmp $0xffffffff,%eax\nje 1320 \ncmp $0xffffffff,%ecx\njne 1340 \nadd $0x4,%rdi\ncmp %rsi,%rdi\nje 1340 \nmov (%rdi),%edx\ntest $0x1,%dl\nje 1310 \ncmp $0xffffffff,%ecx\ncmove %edx,%ecx\njmp 1316 \nnopl 0x0(%rax,%rax,1)\nimul %ecx,%eax\nretq\nmov $0x1,%eax\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_12F4\nmovsxd rsi, esi\nmov eax, 0FFFFFFFFh\nmov ecx, 0FFFFFFFFh\nlea rsi, [rdi+rsi*4]\njmp short loc_12D9\nloc_12C0:\ncmp eax, 0FFFFFFFFh\ncmovz eax, edx\nloc_12C6:\ncmp ecx, 0FFFFFFFFh\njz short loc_12D0\ncmp eax, 0FFFFFFFFh\njnz short loc_12F0\nloc_12D0:\nadd rdi, 4\ncmp rdi, rsi\njz short loc_12F0\nloc_12D9:\nmov edx, [rdi]\ntest dl, 1\njnz short loc_12C0\ncmp ecx, 0FFFFFFFFh\ncmovz ecx, edx\njmp short loc_12C6\nloc_12F0:\nimul eax, ecx\nretn\nloc_12F4:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int v2; // eax\n int v3; // ecx\n int *v4; // rsi\n\n if ( a2 <= 0 )\n return 1LL;\n v2 = -1;\n v3 = -1;\n v4 = &a1[a2];\n do\n {\n if ( (*a1 & 1) != 0 )\n {\n if ( v2 == -1 )\n v2 = *a1;\n }\n else if ( v3 == -1 )\n {\n v3 = *a1;\n }\n if ( v3 != -1 && v2 != -1 )\n break;\n ++a1;\n }\n while ( a1 != v4 );\n return (unsigned int)(v3 * v2);\n}", + "ida_strip_asm": "sub_12A0:\nendbr64\ntest esi, esi\njle short loc_12F4\nmovsxd rsi, esi\nmov eax, 0FFFFFFFFh\nmov ecx, 0FFFFFFFFh\nlea rsi, [rdi+rsi*4]\njmp short loc_12D9\nloc_12C0:\ncmp eax, 0FFFFFFFFh\ncmovz eax, edx\nloc_12C6:\ncmp ecx, 0FFFFFFFFh\njz short loc_12D0\ncmp eax, 0FFFFFFFFh\njnz short loc_12F0\nloc_12D0:\nadd rdi, 4\ncmp rdi, rsi\njz short loc_12F0\nloc_12D9:\nmov edx, [rdi]\ntest dl, 1\njnz short loc_12C0\ncmp ecx, 0FFFFFFFFh\ncmovz ecx, edx\njmp short loc_12C6\nloc_12F0:\nimul eax, ecx\nretn\nloc_12F4:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12A0(int *a1, int a2)\n{\n int v2; // eax\n int v3; // ecx\n int *v4; // rsi\n\n if ( a2 <= 0 )\n return 1LL;\n v2 = -1;\n v3 = -1;\n v4 = &a1[a2];\n do\n {\n if ( (*a1 & 1) != 0 )\n {\n if ( v2 == -1 )\n v2 = *a1;\n }\n else if ( v3 == -1 )\n {\n v3 = *a1;\n }\n if ( v3 != -1 && v2 != -1 )\n break;\n ++a1;\n }\n while ( a1 != v4 );\n return (unsigned int)(v3 * v2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12A0(int *a1, int a2) {\n int v2;\n int v3;\n int *v4;\n if (a2 <= 0) return 1LL;\n v2 = -1;\n v3 = -1;\n v4 = &a1[a2];\n do {\n if ((*a1 & 1) != 0) {\n if (v2 == -1) v2 = *a1;\n } else if (v3 == -1) {\n v3 = *a1;\n }\n if (v3 != -1 && v2 != -1) break;\n ++a1;\n } while (a1 != v4);\n return (unsigned int)(v3 * v2);\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int v2;\n int v3;\n int *v4;\n if (a2 <= 0) return 1LL;\n v2 = -1;\n v3 = -1;\n v4 = &a1[a2];\n do {\n if ((*a1 & 1) != 0) {\n if (v2 == -1) v2 = *a1;\n } else if (v3 == -1) {\n v3 = *a1;\n }\n if (v3 != -1 && v2 != -1) break;\n ++a1;\n } while (a1 != v4);\n return (unsigned int)(v3 * v2);\n}" + }, + { + "index": 784, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int list1[], int n) {\n int first_even = -1;\n int first_odd = -1;\n for (int i = 0; i < n; i++) {\n if (list1[i] % 2 == 0 && first_even == -1) {\n first_even = list1[i];\n }\n if (list1[i] % 2 != 0 && first_odd == -1) {\n first_odd = list1[i];\n }\n if (first_even != -1 && first_odd != -1) {\n break;\n }\n }\n return first_even * first_odd;\n}", + "test": "int main() {\n\n int list1[] = {1,3,5,7,4,1,6,8};\n\n int n1 = sizeof(list1) / sizeof(list1[0]);\n\n assert(func0(list1, n1) == 4);\n\n\n\n int list2[] = {1,2,3,4,5,6,7,8,9,10};\n\n int n2 = sizeof(list2) / sizeof(list2[0]);\n\n assert(func0(list2, n2) == 2);\n\n \n\n int list3[] = {1,5,7,9,10};\n\n int n3 = sizeof(list3) / sizeof(list3[0]);\n\n assert(func0(list3, n3) == 10);\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 12f4 \nlea -0x1(%rsi),%eax\nmov $0xffffffff,%ecx\nlea 0x4(%rdi,%rax,4),%rsi\nmov $0xffffffff,%eax\njmp 12d9 \nnopl 0x0(%rax)\ncmp $0xffffffff,%eax\ncmove %edx,%eax\ncmp $0xffffffff,%eax\nje 12d0 \ncmp $0xffffffff,%ecx\njne 12f0 \nadd $0x4,%rdi\ncmp %rsi,%rdi\nje 12f0 \nmov (%rdi),%edx\ntest $0x1,%dl\nje 12c0 \ncmp $0xffffffff,%ecx\ncmove %edx,%ecx\njmp 12c6 \nnopl 0x0(%rax,%rax,1)\nimul %ecx,%eax\nretq\nmov $0x1,%eax\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_12F4\nmovsxd rsi, esi\nmov eax, 0FFFFFFFFh\nmov ecx, 0FFFFFFFFh\nlea rsi, [rdi+rsi*4]\njmp short loc_12D9\nloc_12C0:\ncmp eax, 0FFFFFFFFh\ncmovz eax, edx\nloc_12C6:\ncmp ecx, 0FFFFFFFFh\njz short loc_12D0\ncmp eax, 0FFFFFFFFh\njnz short loc_12F0\nloc_12D0:\nadd rdi, 4\ncmp rsi, rdi\njz short loc_12F0\nloc_12D9:\nmov edx, [rdi]\ntest dl, 1\njnz short loc_12C0\ncmp ecx, 0FFFFFFFFh\ncmovz ecx, edx\njmp short loc_12C6\nloc_12F0:\nimul eax, ecx\nretn\nloc_12F4:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int v2; // eax\n int v3; // ecx\n int *v4; // rsi\n\n if ( a2 <= 0 )\n return 1LL;\n v2 = -1;\n v3 = -1;\n v4 = &a1[a2];\n do\n {\n if ( (*a1 & 1) != 0 )\n {\n if ( v2 == -1 )\n v2 = *a1;\n }\n else if ( v3 == -1 )\n {\n v3 = *a1;\n }\n if ( v3 != -1 && v2 != -1 )\n break;\n ++a1;\n }\n while ( v4 != a1 );\n return (unsigned int)(v3 * v2);\n}", + "ida_strip_asm": "sub_12A0:\nendbr64\ntest esi, esi\njle short loc_12F4\nmovsxd rsi, esi\nmov eax, 0FFFFFFFFh\nmov ecx, 0FFFFFFFFh\nlea rsi, [rdi+rsi*4]\njmp short loc_12D9\nloc_12C0:\ncmp eax, 0FFFFFFFFh\ncmovz eax, edx\nloc_12C6:\ncmp ecx, 0FFFFFFFFh\njz short loc_12D0\ncmp eax, 0FFFFFFFFh\njnz short loc_12F0\nloc_12D0:\nadd rdi, 4\ncmp rsi, rdi\njz short loc_12F0\nloc_12D9:\nmov edx, [rdi]\ntest dl, 1\njnz short loc_12C0\ncmp ecx, 0FFFFFFFFh\ncmovz ecx, edx\njmp short loc_12C6\nloc_12F0:\nimul eax, ecx\nretn\nloc_12F4:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12A0(int *a1, int a2)\n{\n int v2; // eax\n int v3; // ecx\n int *v4; // rsi\n\n if ( a2 <= 0 )\n return 1LL;\n v2 = -1;\n v3 = -1;\n v4 = &a1[a2];\n do\n {\n if ( (*a1 & 1) != 0 )\n {\n if ( v2 == -1 )\n v2 = *a1;\n }\n else if ( v3 == -1 )\n {\n v3 = *a1;\n }\n if ( v3 != -1 && v2 != -1 )\n break;\n ++a1;\n }\n while ( v4 != a1 );\n return (unsigned int)(v3 * v2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12A0(int *a1, int a2) {\n int v2;\n int v3;\n int *v4;\n if (a2 <= 0) return 1LL;\n v2 = -1;\n v3 = -1;\n v4 = &a1[a2];\n do {\n if ((*a1 & 1) != 0) {\n if (v2 == -1) v2 = *a1;\n } else if (v3 == -1) {\n v3 = *a1;\n }\n if (v3 != -1 && v2 != -1) break;\n ++a1;\n } while (v4 != a1);\n return (unsigned int)(v3 * v2);\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int v2;\n int v3;\n int *v4;\n if (a2 <= 0) return 1LL;\n v2 = -1;\n v3 = -1;\n v4 = &a1[a2];\n do {\n if ((*a1 & 1) != 0) {\n if (v2 == -1) v2 = *a1;\n } else if (v3 == -1) {\n v3 = *a1;\n }\n if (v3 != -1 && v2 != -1) break;\n ++a1;\n } while (v4 != a1);\n return (unsigned int)(v3 * v2);\n}" + }, + { + "index": 785, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int *func0(const char *test_str, int *size) {\n char *str = strdup(test_str);\n str = strtok(str, \"(), \");\n int initial_size = 4, count = 0;\n int *res = malloc(initial_size * sizeof(int));\n while (str != NULL) {\n if (count == initial_size) {\n initial_size *= 2;\n res = realloc(res, initial_size * sizeof(int));\n }\n res[count++] = atoi(str);\n str = strtok(NULL, \"(), \");\n }\n free(str);\n *size = count;\n return res;\n}", + "test": "int main() {\n\n int size;\n\n int *result;\n\n\n\n result = func0(\"(7, 8, 9)\", &size);\n\n assert(size == 3 && result[0] == 7 && result[1] == 8 && result[2] == 9);\n\n free(result);\n\n \n\n result = func0(\"(1, 2, 3)\", &size);\n\n assert(size == 3 && result[0] == 1 && result[1] == 2 && result[2] == 3);\n\n free(result);\n\n \n\n result = func0(\"(4, 5, 6)\", &size);\n\n assert(size == 3 && result[0] == 4 && result[1] == 5 && result[2] == 6);\n\n free(result);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x38,%rsp\nmov %rdi,-0x38(%rbp)\nmov %rsi,-0x40(%rbp)\nmov -0x38(%rbp),%rax\nmov %rax,%rdi\ncallq 1130 \nmov %rax,-0x20(%rbp)\nmov -0x20(%rbp),%rax\nlea 0xdaf(%rip),%rsi\nmov %rax,%rdi\ncallq 1110 \nmov %rax,-0x20(%rbp)\nmovl $0x4,-0x28(%rbp)\nmovl $0x0,-0x24(%rbp)\nmov -0x28(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10f0 \nmov %rax,-0x18(%rbp)\njmp 12f3 \nmov -0x24(%rbp),%eax\ncmp -0x28(%rbp),%eax\njne 12b5 \nshll -0x28(%rbp)\nmov -0x28(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1100 \nmov %rax,-0x18(%rbp)\nmov -0x24(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x24(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rbx\nmov -0x20(%rbp),%rax\nmov %rax,%rdi\ncallq 1120 \nmov %eax,(%rbx)\nlea 0xd23(%rip),%rsi\nmov $0x0,%edi\ncallq 1110 \nmov %rax,-0x20(%rbp)\ncmpq $0x0,-0x20(%rbp)\njne 128a \nmov -0x20(%rbp),%rax\nmov %rax,%rdi\ncallq 10c0 \nmov -0x40(%rbp),%rax\nmov -0x24(%rbp),%edx\nmov %edx,(%rax)\nmov -0x18(%rbp),%rax\nadd $0x38,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+s], rdi\nmov [rbp+var_40], rsi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strdup\nmov [rbp+nptr], rax\nmov rax, [rbp+nptr]\nlea rdx, delim; \"(), \"\nmov rsi, rdx; delim\nmov rdi, rax; s\ncall _strtok\nmov [rbp+nptr], rax\nmov [rbp+var_28], 4\nmov [rbp+var_24], 0\nmov eax, [rbp+var_28]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\njmp short loc_12F9\nloc_128D:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_28]\njnz short loc_12B8\nshl [rbp+var_28], 1\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nmov rsi, rdx; size\nmov rdi, rax; ptr\ncall _realloc\nmov [rbp+ptr], rax\nloc_12B8:\nmov eax, [rbp+var_24]\nlea edx, [rax+1]\nmov [rbp+var_24], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nlea rbx, [rdx+rax]\nmov rax, [rbp+nptr]\nmov rdi, rax; nptr\ncall _atoi\nmov [rbx], eax\nlea rax, delim; \"(), \"\nmov rsi, rax; delim\nmov edi, 0; s\ncall _strtok\nmov [rbp+nptr], rax\nloc_12F9:\ncmp [rbp+nptr], 0\njnz short loc_128D\nmov rax, [rbp+nptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_40]\nmov edx, [rbp+var_24]\nmov [rax], edx\nmov rax, [rbp+ptr]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "void *__fastcall func0(const char *a1, _DWORD *a2)\n{\n char *v2; // rax\n int v3; // eax\n int v5; // [rsp+18h] [rbp-28h]\n int v6; // [rsp+1Ch] [rbp-24h]\n const char *nptr; // [rsp+20h] [rbp-20h]\n void *ptr; // [rsp+28h] [rbp-18h]\n\n v2 = strdup(a1);\n nptr = strtok(v2, \"(), \");\n v5 = 4;\n v6 = 0;\n ptr = malloc(0x10uLL);\n while ( nptr )\n {\n if ( v6 == v5 )\n {\n v5 *= 2;\n ptr = realloc(ptr, 4LL * v5);\n }\n v3 = v6++;\n *((_DWORD *)ptr + v3) = atoi(nptr);\n nptr = strtok(0LL, \"(), \");\n }\n free(0LL);\n *a2 = v6;\n return ptr;\n}", + "ida_strip_asm": "sub_1229:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+s], rdi\nmov [rbp+var_40], rsi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strdup\nmov [rbp+nptr], rax\nmov rax, [rbp+nptr]\nlea rdx, delim; \"(), \"\nmov rsi, rdx; delim\nmov rdi, rax; s\ncall _strtok\nmov [rbp+nptr], rax\nmov [rbp+var_28], 4\nmov [rbp+var_24], 0\nmov eax, [rbp+var_28]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\njmp short loc_12F9\nloc_128D:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_28]\njnz short loc_12B8\nshl [rbp+var_28], 1\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nmov rsi, rdx; size\nmov rdi, rax; ptr\ncall _realloc\nmov [rbp+ptr], rax\nloc_12B8:\nmov eax, [rbp+var_24]\nlea edx, [rax+1]\nmov [rbp+var_24], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nlea rbx, [rdx+rax]\nmov rax, [rbp+nptr]\nmov rdi, rax; nptr\ncall _atoi\nmov [rbx], eax\nlea rax, delim; \"(), \"\nmov rsi, rax; delim\nmov edi, 0; s\ncall _strtok\nmov [rbp+nptr], rax\nloc_12F9:\ncmp [rbp+nptr], 0\njnz short loc_128D\nmov rax, [rbp+nptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_40]\nmov edx, [rbp+var_24]\nmov [rax], edx\nmov rax, [rbp+ptr]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "void *__fastcall sub_1229(const char *a1, _DWORD *a2)\n{\n char *v2; // rax\n int v3; // eax\n int v5; // [rsp+18h] [rbp-28h]\n int v6; // [rsp+1Ch] [rbp-24h]\n const char *nptr; // [rsp+20h] [rbp-20h]\n void *ptr; // [rsp+28h] [rbp-18h]\n\n v2 = strdup(a1);\n nptr = strtok(v2, \"(), \");\n v5 = 4;\n v6 = 0;\n ptr = malloc(0x10uLL);\n while ( nptr )\n {\n if ( v6 == v5 )\n {\n v5 *= 2;\n ptr = realloc(ptr, 4LL * v5);\n }\n v3 = v6++;\n *((_DWORD *)ptr + v3) = atoi(nptr);\n nptr = strtok(0LL, \"(), \");\n }\n free(0LL);\n *a2 = v6;\n return ptr;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1229(const char *a1, uint32_t *a2) {\n char *v2;\n int v3;\n int v5;\n int v6;\n const char *nptr;\n void *ptr;\n v2 = strdup(a1);\n nptr = strtok(v2, \"(), \");\n v5 = 4;\n v6 = 0;\n ptr = malloc(16uLL);\n while (nptr) {\n if (v6 == v5) {\n v5 *= 2;\n ptr = realloc(ptr, 4LL * v5);\n }\n v3 = v6++;\n *((uint32_t *)ptr + v3) = atoi(nptr);\n nptr = strtok(0LL, \"(), \");\n }\n free(0LL);\n *a2 = v6;\n return ptr;\n}", + "ida_pseudo_norm": "void *func0(const char *a1, uint32_t *a2) {\n char *v2;\n int v3;\n int v5;\n int v6;\n const char *nptr;\n void *ptr;\n v2 = strdup(a1);\n nptr = strtok(v2, \"(), \");\n v5 = 4;\n v6 = 0;\n ptr = malloc(16uLL);\n while (nptr) {\n if (v6 == v5) {\n v5 *= 2;\n ptr = realloc(ptr, 4LL * v5);\n }\n v3 = v6++;\n *((uint32_t *)ptr + v3) = atoi(nptr);\n nptr = strtok(0LL, \"(), \");\n }\n free(0LL);\n *a2 = v6;\n return ptr;\n}" + }, + { + "index": 785, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int *func0(const char *test_str, int *size) {\n char *str = strdup(test_str);\n str = strtok(str, \"(), \");\n int initial_size = 4, count = 0;\n int *res = malloc(initial_size * sizeof(int));\n while (str != NULL) {\n if (count == initial_size) {\n initial_size *= 2;\n res = realloc(res, initial_size * sizeof(int));\n }\n res[count++] = atoi(str);\n str = strtok(NULL, \"(), \");\n }\n free(str);\n *size = count;\n return res;\n}", + "test": "int main() {\n\n int size;\n\n int *result;\n\n\n\n result = func0(\"(7, 8, 9)\", &size);\n\n assert(size == 3 && result[0] == 7 && result[1] == 8 && result[2] == 9);\n\n free(result);\n\n \n\n result = func0(\"(1, 2, 3)\", &size);\n\n assert(size == 3 && result[0] == 1 && result[1] == 2 && result[2] == 3);\n\n free(result);\n\n \n\n result = func0(\"(4, 5, 6)\", &size);\n\n assert(size == 3 && result[0] == 4 && result[1] == 5 && result[2] == 6);\n\n free(result);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov %rsi,0x8(%rsp)\ncallq 1130 \nmov %rax,%rdi\nlea 0xdb5(%rip),%rsi\ncallq 1120 \nmov %rax,%rbx\nmov $0x10,%edi\ncallq 1100 \nmov %rax,%r13\nmov $0x0,%r12d\nmov $0x4,%r15d\nmov $0x0,%r14d\ntest %rbx,%rbx\njne 12ae \nmov 0x8(%rsp),%rax\nmov %r14d,(%rax)\nmov %r13,%rax\nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nadd %r15d,%r15d\nmovslq %r15d,%rsi\nshl $0x2,%rsi\nmov %r13,%rdi\ncallq 1110 \nmov %rax,%r13\nadd $0x1,%r12\nlea 0x1(%r12),%r14d\nlea 0x0(%r13,%r12,4),%rbp\nmov $0xa,%edx\nmov $0x0,%esi\nmov %rbx,%rdi\ncallq 10f0 \nmov %eax,0x0(%rbp)\nlea 0xd30(%rip),%rsi\nmov $0x0,%edi\ncallq 1120 \nmov %rax,%rbx\ntest %rax,%rax\nje 127b \ncmp %r14d,%r15d\njne 12aa \njmp 1295 \n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rsi\ncall _strdup\nmov rdi, rax; s\nlea rsi, delim; \"(), \"\ncall _strtok\nmov rbx, rax\nmov edi, 10h; size\ncall _malloc\nmov r13, rax\ntest rbx, rbx\njz loc_12F0\nmov ebp, 0\nmov r14d, 4\nlea r15, delim; \"(), \"\njmp short loc_12B8\nloc_1281:\nlea r12, [r13+rbp*4+0]\nmov edx, 0Ah; base\nmov esi, 0; endptr\nmov rdi, rbx; nptr\ncall _strtol\nmov [r12], eax\nmov rsi, r15; delim\nmov edi, 0; s\ncall _strtok\nmov rbx, rax\nlea rax, [rbp+1]\ntest rbx, rbx\njz short loc_12D4\nmov rbp, rax\nloc_12B8:\ncmp r14d, ebp\njnz short loc_1281\nadd r14d, r14d\nmovsxd rsi, r14d\nshl rsi, 2; size\nmov rdi, r13; ptr\ncall _realloc\nmov r13, rax\njmp short loc_1281\nloc_12D4:\nadd ebp, 1\nloc_12D7:\nmov rax, [rsp+48h+var_40]\nmov [rax], ebp\nmov rax, r13\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_12F0:\nmov ebp, 0\njmp short loc_12D7", + "ida_pseudo": "void *__fastcall func0(const char *a1, _DWORD *a2)\n{\n char *v2; // rax\n char *v3; // rbx\n void *v4; // r13\n __int64 v5; // rbp\n int v6; // r14d\n int v7; // ebp\n\n v2 = strdup(a1);\n v3 = strtok(v2, \"(), \");\n v4 = malloc(0x10uLL);\n if ( v3 )\n {\n v5 = 0LL;\n v6 = 4;\n while ( 1 )\n {\n if ( v6 == (_DWORD)v5 )\n {\n v6 *= 2;\n v4 = realloc(v4, 4LL * v6);\n }\n *((_DWORD *)v4 + v5) = strtol(v3, 0LL, 10);\n v3 = strtok(0LL, \"(), \");\n if ( !v3 )\n break;\n ++v5;\n }\n v7 = v5 + 1;\n }\n else\n {\n v7 = 0;\n }\n *a2 = v7;\n return v4;\n}", + "ida_strip_asm": "sub_1229:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rsi\ncall _strdup\nmov rdi, rax; s\nlea rsi, delim; \"(), \"\ncall _strtok\nmov rbx, rax\nmov edi, 10h; size\ncall _malloc\nmov r13, rax\ntest rbx, rbx\njz loc_12F0\nmov ebp, 0\nmov r14d, 4\nlea r15, delim; \"(), \"\njmp short loc_12B8\nloc_1281:\nlea r12, [r13+rbp*4+0]\nmov edx, 0Ah; base\nmov esi, 0; endptr\nmov rdi, rbx; nptr\ncall _strtol\nmov [r12], eax\nmov rsi, r15; delim\nmov edi, 0; s\ncall _strtok\nmov rbx, rax\nlea rax, [rbp+1]\ntest rbx, rbx\njz short loc_12D4\nmov rbp, rax\nloc_12B8:\ncmp r14d, ebp\njnz short loc_1281\nadd r14d, r14d\nmovsxd rsi, r14d\nshl rsi, 2; size\nmov rdi, r13; ptr\ncall _realloc\nmov r13, rax\njmp short loc_1281\nloc_12D4:\nadd ebp, 1\nloc_12D7:\nmov rax, [rsp+48h+var_40]\nmov [rax], ebp\nmov rax, r13\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_12F0:\nmov ebp, 0\njmp short loc_12D7", + "ida_strip_pseudo": "void *__fastcall sub_1229(const char *a1, _DWORD *a2)\n{\n char *v2; // rax\n char *v3; // rbx\n void *v4; // r13\n __int64 v5; // rbp\n int v6; // r14d\n int v7; // ebp\n\n v2 = strdup(a1);\n v3 = strtok(v2, \"(), \");\n v4 = malloc(0x10uLL);\n if ( v3 )\n {\n v5 = 0LL;\n v6 = 4;\n while ( 1 )\n {\n if ( v6 == (_DWORD)v5 )\n {\n v6 *= 2;\n v4 = realloc(v4, 4LL * v6);\n }\n *((_DWORD *)v4 + v5) = strtol(v3, 0LL, 10);\n v3 = strtok(0LL, \"(), \");\n if ( !v3 )\n break;\n ++v5;\n }\n v7 = v5 + 1;\n }\n else\n {\n v7 = 0;\n }\n *a2 = v7;\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1229(const char *a1, uint32_t *a2) {\n char *v2;\n char *v3;\n void *v4;\n long long v5;\n int v6;\n int v7;\n v2 = strdup(a1);\n v3 = strtok(v2, \"(), \");\n v4 = malloc(16uLL);\n if (v3) {\n v5 = 0LL;\n v6 = 4;\n while (1) {\n if (v6 == (uint32_t)v5) {\n v6 *= 2;\n v4 = realloc(v4, 4LL * v6);\n }\n *((uint32_t *)v4 + v5) = strtol(v3, 0LL, 10);\n v3 = strtok(0LL, \"(), \");\n if (!v3) break;\n ++v5;\n }\n v7 = v5 + 1;\n } else {\n v7 = 0;\n }\n *a2 = v7;\n return v4;\n}", + "ida_pseudo_norm": "void *func0(const char *a1, uint32_t *a2) {\n char *v2;\n char *v3;\n void *v4;\n long long v5;\n int v6;\n int v7;\n v2 = strdup(a1);\n v3 = strtok(v2, \"(), \");\n v4 = malloc(16uLL);\n if (v3) {\n v5 = 0LL;\n v6 = 4;\n while (1) {\n if (v6 == (uint32_t)v5) {\n v6 *= 2;\n v4 = realloc(v4, 4LL * v6);\n }\n *((uint32_t *)v4 + v5) = strtol(v3, 0LL, 10);\n v3 = strtok(0LL, \"(), \");\n if (!v3) break;\n ++v5;\n }\n v7 = v5 + 1;\n } else {\n v7 = 0;\n }\n *a2 = v7;\n return v4;\n}" + }, + { + "index": 785, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int *func0(const char *test_str, int *size) {\n char *str = strdup(test_str);\n str = strtok(str, \"(), \");\n int initial_size = 4, count = 0;\n int *res = malloc(initial_size * sizeof(int));\n while (str != NULL) {\n if (count == initial_size) {\n initial_size *= 2;\n res = realloc(res, initial_size * sizeof(int));\n }\n res[count++] = atoi(str);\n str = strtok(NULL, \"(), \");\n }\n free(str);\n *size = count;\n return res;\n}", + "test": "int main() {\n\n int size;\n\n int *result;\n\n\n\n result = func0(\"(7, 8, 9)\", &size);\n\n assert(size == 3 && result[0] == 7 && result[1] == 8 && result[2] == 9);\n\n free(result);\n\n \n\n result = func0(\"(1, 2, 3)\", &size);\n\n assert(size == 3 && result[0] == 1 && result[1] == 2 && result[2] == 3);\n\n free(result);\n\n \n\n result = func0(\"(4, 5, 6)\", &size);\n\n assert(size == 3 && result[0] == 4 && result[1] == 5 && result[2] == 6);\n\n free(result);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\nxor %r12d,%r12d\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov %rsi,0x8(%rsp)\ncallq 1130 \nlea 0xc5e(%rip),%rsi\nmov %rax,%rdi\ncallq 1120 \nmov $0x10,%edi\nmov %rax,%r15\ncallq 1100 \nmovl $0x4,0x4(%rsp)\nmov %rax,%rbp\ntest %r15,%r15\nje 1438 \nxor %r13d,%r13d\nlea 0xc2f(%rip),%r14\njmp 13e4 \nnopw 0x0(%rax,%rax,1)\nadd $0x1,%r13\nmov %r15,%rdi\nmov $0xa,%edx\nlea 0x0(%rbp,%r13,4),%rbx\nxor %esi,%esi\ncallq 10f0 \nmov %r14,%rsi\nxor %edi,%edi\nlea 0x1(%r13),%r12d\nmov %eax,(%rbx)\ncallq 1120 \nmov %rax,%r15\ntest %rax,%rax\nje 1438 \ncmp %r12d,0x4(%rsp)\njne 13e0 \nshll 0x4(%rsp)\nmovslq 0x4(%rsp),%rsi\nmov %rbp,%rdi\nshl $0x2,%rsi\ncallq 1110 \nmov %rax,%rbp\njmp 13e0 \nnopl 0x0(%rax)\nmov 0x8(%rsp),%rax\nmov %r12d,(%rax)\nadd $0x18,%rsp\nmov %rbp,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nlea r14, delim; \"(), \"\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rsi\ncall _strdup\nmov rsi, r14; delim\nmov rdi, rax; s\ncall _strtok\nmov edi, 10h; size\nmov rbx, rax\ncall _malloc\nmov rbp, rax\ntest rbx, rbx\njz short loc_1440\nxor r13d, r13d\nmov r12d, 4\njmp short loc_1400\nloc_13D0:\nmov rdi, rbx; nptr\nmov edx, 0Ah; base\nlea r15, [rbp+r13*4+0]\nxor esi, esi; endptr\ncall _strtol\nmov rsi, r14; delim\nxor edi, edi; s\nmov [r15], eax\ncall _strtok\nmov rbx, rax\nlea rax, [r13+1]\ntest rbx, rbx\njz short loc_1420\nmov r13, rax\nloc_1400:\ncmp r12d, r13d\njnz short loc_13D0\nadd r12d, r12d\nmov rdi, rbp; ptr\nmovsxd rsi, r12d\nshl rsi, 2; size\ncall _realloc\nmov rbp, rax\njmp short loc_13D0\nloc_1420:\nlea eax, [r13+1]\nloc_1424:\nmov rcx, [rsp+48h+var_40]\nmov [rcx], eax\nadd rsp, 18h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1440:\nxor eax, eax\njmp short loc_1424", + "ida_pseudo": "void *__fastcall func0(const char *a1, _DWORD *a2)\n{\n char *v2; // rax\n char *v3; // rbx\n void *v4; // rbp\n __int64 v5; // r13\n int v6; // r12d\n int v7; // eax\n\n v2 = strdup(a1);\n v3 = strtok(v2, \"(), \");\n v4 = malloc(0x10uLL);\n if ( v3 )\n {\n v5 = 0LL;\n v6 = 4;\n while ( 1 )\n {\n if ( v6 == (_DWORD)v5 )\n {\n v6 *= 2;\n v4 = realloc(v4, 4LL * v6);\n }\n *((_DWORD *)v4 + v5) = strtol(v3, 0LL, 10);\n v3 = strtok(0LL, \"(), \");\n if ( !v3 )\n break;\n ++v5;\n }\n v7 = v5 + 1;\n }\n else\n {\n v7 = 0;\n }\n *a2 = v7;\n return v4;\n}", + "ida_strip_asm": "sub_1380:\nendbr64\npush r15\npush r14\nlea r14, delim; \"(), \"\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rsi\ncall _strdup\nmov rsi, r14; delim\nmov rdi, rax; s\ncall _strtok\nmov edi, 10h; size\nmov rbx, rax\ncall _malloc\nmov rbp, rax\ntest rbx, rbx\njz short loc_1440\nxor r13d, r13d\nmov r12d, 4\njmp short loc_1400\nloc_13D0:\nmov rdi, rbx; nptr\nmov edx, 0Ah; base\nlea r15, [rbp+r13*4+0]\nxor esi, esi; endptr\ncall _strtol\nmov rsi, r14; delim\nxor edi, edi; s\nmov [r15], eax\ncall _strtok\nmov rbx, rax\nlea rax, [r13+1]\ntest rbx, rbx\njz short loc_1420\nmov r13, rax\nloc_1400:\ncmp r12d, r13d\njnz short loc_13D0\nadd r12d, r12d\nmov rdi, rbp; ptr\nmovsxd rsi, r12d\nshl rsi, 2; size\ncall _realloc\nmov rbp, rax\njmp short loc_13D0\nloc_1420:\nlea eax, [r13+1]\nloc_1424:\nmov rcx, [rsp+48h+var_40]\nmov [rcx], eax\nadd rsp, 18h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1440:\nxor eax, eax\njmp short loc_1424", + "ida_strip_pseudo": "void *__fastcall sub_1380(const char *a1, _DWORD *a2)\n{\n char *v2; // rax\n char *v3; // rbx\n void *v4; // rbp\n __int64 v5; // r13\n int v6; // r12d\n int v7; // eax\n\n v2 = strdup(a1);\n v3 = strtok(v2, \"(), \");\n v4 = malloc(0x10uLL);\n if ( v3 )\n {\n v5 = 0LL;\n v6 = 4;\n while ( 1 )\n {\n if ( v6 == (_DWORD)v5 )\n {\n v6 *= 2;\n v4 = realloc(v4, 4LL * v6);\n }\n *((_DWORD *)v4 + v5) = strtol(v3, 0LL, 10);\n v3 = strtok(0LL, \"(), \");\n if ( !v3 )\n break;\n ++v5;\n }\n v7 = v5 + 1;\n }\n else\n {\n v7 = 0;\n }\n *a2 = v7;\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1380(const char *a1, uint32_t *a2) {\n char *v2;\n char *v3;\n void *v4;\n long long v5;\n int v6;\n int v7;\n v2 = strdup(a1);\n v3 = strtok(v2, \"(), \");\n v4 = malloc(16uLL);\n if (v3) {\n v5 = 0LL;\n v6 = 4;\n while (1) {\n if (v6 == (uint32_t)v5) {\n v6 *= 2;\n v4 = realloc(v4, 4LL * v6);\n }\n *((uint32_t *)v4 + v5) = strtol(v3, 0LL, 10);\n v3 = strtok(0LL, \"(), \");\n if (!v3) break;\n ++v5;\n }\n v7 = v5 + 1;\n } else {\n v7 = 0;\n }\n *a2 = v7;\n return v4;\n}", + "ida_pseudo_norm": "void *func0(const char *a1, uint32_t *a2) {\n char *v2;\n char *v3;\n void *v4;\n long long v5;\n int v6;\n int v7;\n v2 = strdup(a1);\n v3 = strtok(v2, \"(), \");\n v4 = malloc(16uLL);\n if (v3) {\n v5 = 0LL;\n v6 = 4;\n while (1) {\n if (v6 == (uint32_t)v5) {\n v6 *= 2;\n v4 = realloc(v4, 4LL * v6);\n }\n *((uint32_t *)v4 + v5) = strtol(v3, 0LL, 10);\n v3 = strtok(0LL, \"(), \");\n if (!v3) break;\n ++v5;\n }\n v7 = v5 + 1;\n } else {\n v7 = 0;\n }\n *a2 = v7;\n return v4;\n}" + }, + { + "index": 785, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int *func0(const char *test_str, int *size) {\n char *str = strdup(test_str);\n str = strtok(str, \"(), \");\n int initial_size = 4, count = 0;\n int *res = malloc(initial_size * sizeof(int));\n while (str != NULL) {\n if (count == initial_size) {\n initial_size *= 2;\n res = realloc(res, initial_size * sizeof(int));\n }\n res[count++] = atoi(str);\n str = strtok(NULL, \"(), \");\n }\n free(str);\n *size = count;\n return res;\n}", + "test": "int main() {\n\n int size;\n\n int *result;\n\n\n\n result = func0(\"(7, 8, 9)\", &size);\n\n assert(size == 3 && result[0] == 7 && result[1] == 8 && result[2] == 9);\n\n free(result);\n\n \n\n result = func0(\"(1, 2, 3)\", &size);\n\n assert(size == 3 && result[0] == 1 && result[1] == 2 && result[2] == 3);\n\n free(result);\n\n \n\n result = func0(\"(4, 5, 6)\", &size);\n\n assert(size == 3 && result[0] == 4 && result[1] == 5 && result[2] == 6);\n\n free(result);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\nxor %r12d,%r12d\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov %rsi,0x8(%rsp)\ncallq 1130 \nlea 0xc5e(%rip),%rsi\nmov %rax,%rdi\ncallq 1120 \nmov $0x10,%edi\nmov %rax,%r15\ncallq 1100 \nmovl $0x4,0x4(%rsp)\nmov %rax,%rbp\ntest %r15,%r15\nje 1438 \nxor %r13d,%r13d\nlea 0xc2f(%rip),%r14\njmp 13e4 \nnopw 0x0(%rax,%rax,1)\nadd $0x1,%r13\nmov %r15,%rdi\nmov $0xa,%edx\nlea 0x0(%rbp,%r13,4),%rbx\nxor %esi,%esi\ncallq 10f0 \nmov %r14,%rsi\nxor %edi,%edi\nlea 0x1(%r13),%r12d\nmov %eax,(%rbx)\ncallq 1120 \nmov %rax,%r15\ntest %rax,%rax\nje 1438 \ncmp %r12d,0x4(%rsp)\njne 13e0 \nshll 0x4(%rsp)\nmovslq 0x4(%rsp),%rsi\nmov %rbp,%rdi\nshl $0x2,%rsi\ncallq 1110 \nmov %rax,%rbp\njmp 13e0 \nnopl 0x0(%rax)\nmov 0x8(%rsp),%rax\nmov %r12d,(%rax)\nadd $0x18,%rsp\nmov %rbp,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nlea r14, delim; \"(), \"\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rsi\ncall _strdup\nmov rsi, r14; delim\nmov rdi, rax; s\ncall _strtok\nmov edi, 10h; size\nmov rbx, rax\ncall _malloc\nmov rbp, rax\ntest rbx, rbx\njz loc_1460\nxor r13d, r13d\nmov r12d, 4\njmp short loc_1408\nloc_13D8:\nmov edx, 0Ah; base\nxor esi, esi; endptr\nlea r15, [rbp+r13*4+0]\nmov rdi, rbx; nptr\ncall _strtol\nmov [r15], eax\nloc_13EF:\nmov rsi, r14; delim\nxor edi, edi; s\ncall _strtok\nmov rbx, rax\nlea rax, [r13+1]\ntest rbx, rbx\njz short loc_1440\nmov r13, rax\nloc_1408:\ncmp r12d, r13d\njnz short loc_13D8\nadd r12d, r12d\nmov rdi, rbp; ptr\nmovsxd rsi, r12d\nshl rsi, 2; size\ncall _realloc\nmov edx, 0Ah; base\nxor esi, esi; endptr\nmov rdi, rbx; nptr\nlea r15, [rax+r13*4]\nmov rbp, rax\ncall _strtol\nmov [r15], eax\njmp short loc_13EF\nloc_1440:\nlea eax, [r13+1]\nloc_1444:\nmov rcx, [rsp+48h+var_40]\nmov [rcx], eax\nadd rsp, 18h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1460:\nxor eax, eax\njmp short loc_1444", + "ida_pseudo": "void *__fastcall func0(const char *a1, _DWORD *a2)\n{\n char *v2; // rax\n char *v3; // rbx\n void *v4; // rbp\n __int64 v5; // r13\n int v6; // r12d\n int v7; // eax\n\n v2 = strdup(a1);\n v3 = strtok(v2, \"(), \");\n v4 = malloc(0x10uLL);\n if ( v3 )\n {\n v5 = 0LL;\n v6 = 4;\n while ( 1 )\n {\n if ( v6 == (_DWORD)v5 )\n {\n v6 *= 2;\n v4 = realloc(v4, 4LL * v6);\n }\n *((_DWORD *)v4 + v5) = strtol(v3, 0LL, 10);\n v3 = strtok(0LL, \"(), \");\n if ( !v3 )\n break;\n ++v5;\n }\n v7 = v5 + 1;\n }\n else\n {\n v7 = 0;\n }\n *a2 = v7;\n return v4;\n}", + "ida_strip_asm": "sub_1380:\nendbr64\npush r15\npush r14\nlea r14, delim; \"(), \"\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rsi\ncall _strdup\nmov rsi, r14; delim\nmov rdi, rax; s\ncall _strtok\nmov edi, 10h; size\nmov rbx, rax\ncall _malloc\nmov rbp, rax\ntest rbx, rbx\njz loc_1460\nxor r13d, r13d\nmov r12d, 4\njmp short loc_1408\nloc_13D8:\nmov edx, 0Ah; base\nxor esi, esi; endptr\nlea r15, [rbp+r13*4+0]\nmov rdi, rbx; nptr\ncall _strtol\nmov [r15], eax\nloc_13EF:\nmov rsi, r14; delim\nxor edi, edi; s\ncall _strtok\nmov rbx, rax\nlea rax, [r13+1]\ntest rbx, rbx\njz short loc_1440\nmov r13, rax\nloc_1408:\ncmp r12d, r13d\njnz short loc_13D8\nadd r12d, r12d\nmov rdi, rbp; ptr\nmovsxd rsi, r12d\nshl rsi, 2; size\ncall _realloc\nmov edx, 0Ah; base\nxor esi, esi; endptr\nmov rdi, rbx; nptr\nlea r15, [rax+r13*4]\nmov rbp, rax\ncall _strtol\nmov [r15], eax\njmp short loc_13EF\nloc_1440:\nlea eax, [r13+1]\nloc_1444:\nmov rcx, [rsp+48h+var_40]\nmov [rcx], eax\nadd rsp, 18h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1460:\nxor eax, eax\njmp short loc_1444", + "ida_strip_pseudo": "void *__fastcall sub_1380(const char *a1, _DWORD *a2)\n{\n char *v2; // rax\n char *v3; // rbx\n void *v4; // rbp\n __int64 v5; // r13\n int v6; // r12d\n int v7; // eax\n\n v2 = strdup(a1);\n v3 = strtok(v2, \"(), \");\n v4 = malloc(0x10uLL);\n if ( v3 )\n {\n v5 = 0LL;\n v6 = 4;\n while ( 1 )\n {\n if ( v6 == (_DWORD)v5 )\n {\n v6 *= 2;\n v4 = realloc(v4, 4LL * v6);\n }\n *((_DWORD *)v4 + v5) = strtol(v3, 0LL, 10);\n v3 = strtok(0LL, \"(), \");\n if ( !v3 )\n break;\n ++v5;\n }\n v7 = v5 + 1;\n }\n else\n {\n v7 = 0;\n }\n *a2 = v7;\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1380(const char *a1, uint32_t *a2) {\n char *v2;\n char *v3;\n void *v4;\n long long v5;\n int v6;\n int v7;\n v2 = strdup(a1);\n v3 = strtok(v2, \"(), \");\n v4 = malloc(16uLL);\n if (v3) {\n v5 = 0LL;\n v6 = 4;\n while (1) {\n if (v6 == (uint32_t)v5) {\n v6 *= 2;\n v4 = realloc(v4, 4LL * v6);\n }\n *((uint32_t *)v4 + v5) = strtol(v3, 0LL, 10);\n v3 = strtok(0LL, \"(), \");\n if (!v3) break;\n ++v5;\n }\n v7 = v5 + 1;\n } else {\n v7 = 0;\n }\n *a2 = v7;\n return v4;\n}", + "ida_pseudo_norm": "void *func0(const char *a1, uint32_t *a2) {\n char *v2;\n char *v3;\n void *v4;\n long long v5;\n int v6;\n int v7;\n v2 = strdup(a1);\n v3 = strtok(v2, \"(), \");\n v4 = malloc(16uLL);\n if (v3) {\n v5 = 0LL;\n v6 = 4;\n while (1) {\n if (v6 == (uint32_t)v5) {\n v6 *= 2;\n v4 = realloc(v4, 4LL * v6);\n }\n *((uint32_t *)v4 + v5) = strtol(v3, 0LL, 10);\n v3 = strtok(0LL, \"(), \");\n if (!v3) break;\n ++v5;\n }\n v7 = v5 + 1;\n } else {\n v7 = 0;\n }\n *a2 = v7;\n return v4;\n}" + }, + { + "index": 786, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int* a, int n, int x) {\n int i = 0;\n for (; i < n; i++) {\n if (a[i] > x) {\n break;\n }\n }\n return i;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 4, 5};\n\n int arr2[] = {1, 2, 4, 5};\n\n int arr3[] = {1, 2, 4, 5};\n\n\n\n assert(func0(arr1, 4, 6) == 4);\n\n assert(func0(arr2, 4, 3) == 2);\n\n assert(func0(arr3, 4, 7) == 4);\n\n\n\n return EXIT_SUCCESS;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11a3 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x20(%rbp)\njl 11ad \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1184 \njmp 11ae \nmov -0x4(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_4], 0\njmp short loc_11A3\nloc_1184:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njl short loc_11AD\nadd [rbp+var_4], 1\nloc_11A3:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1184\njmp short loc_11AE\nloc_11AD:\nnop\nloc_11AE:\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n unsigned int i; // [rsp+1Ch] [rbp-4h]\n\n for ( i = 0; (int)i < a2 && a3 >= *(_DWORD *)(4LL * (int)i + a1); ++i )\n ;\n return i;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_4], 0\njmp short loc_11A3\nloc_1184:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njl short loc_11AD\nadd [rbp+var_4], 1\nloc_11A3:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1184\njmp short loc_11AE\nloc_11AD:\nnop\nloc_11AE:\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n unsigned int i; // [rsp+1Ch] [rbp-4h]\n\n for ( i = 0; (int)i < a2 && a3 >= *(_DWORD *)(4LL * (int)i + a1); ++i )\n ;\n return i;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n unsigned int i;\n for (i = 0; (int)i < a2 && a3 >= *(uint32_t *)(4LL * (int)i + a1); ++i)\n ;\n return i;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n unsigned int i;\n for (i = 0; (int)i < a2 && a3 >= *(uint32_t *)(4LL * (int)i + a1); ++i)\n ;\n return i;\n}" + }, + { + "index": 786, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int* a, int n, int x) {\n int i = 0;\n for (; i < n; i++) {\n if (a[i] > x) {\n break;\n }\n }\n return i;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 4, 5};\n\n int arr2[] = {1, 2, 4, 5};\n\n int arr3[] = {1, 2, 4, 5};\n\n\n\n assert(func0(arr1, 4, 6) == 4);\n\n assert(func0(arr2, 4, 3) == 2);\n\n assert(func0(arr3, 4, 7) == 4);\n\n\n\n return EXIT_SUCCESS;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1195 \nlea -0x1(%rsi),%r8d\nmov $0x0,%eax\njmp 117f \nmov %rsi,%rax\nmov %eax,%ecx\ncmp %edx,(%rdi,%rax,4)\njg 1192 \nlea 0x1(%rax),%ecx\nlea 0x1(%rax),%rsi\ncmp %r8,%rax\njne 117c \nmov %ecx,%eax\nretq\nmov $0x0,%ecx\njmp 1192 \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1188\nmov eax, 0\nloc_1176:\ncmp [rdi], edx\njg short locret_118D\nadd eax, 1\nadd rdi, 4\ncmp esi, eax\njnz short loc_1176\nmov eax, esi\nretn\nloc_1188:\nmov eax, 0\nlocret_118D:\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2, int a3)\n{\n __int64 result; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n result = 0LL;\n while ( *a1 <= a3 )\n {\n result = (unsigned int)(result + 1);\n ++a1;\n if ( a2 == (_DWORD)result )\n return (unsigned int)a2;\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_1188\nmov eax, 0\nloc_1176:\ncmp [rdi], edx\njg short locret_118D\nadd eax, 1\nadd rdi, 4\ncmp esi, eax\njnz short loc_1176\nmov eax, esi\nretn\nloc_1188:\nmov eax, 0\nlocret_118D:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2, int a3)\n{\n __int64 result; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n result = 0LL;\n while ( *a1 <= a3 )\n {\n result = (unsigned int)(result + 1);\n ++a1;\n if ( a2 == (_DWORD)result )\n return (unsigned int)a2;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2, int a3) {\n long long result;\n if (a2 <= 0) return 0LL;\n result = 0LL;\n while (*a1 <= a3) {\n result = (unsigned int)(result + 1);\n ++a1;\n if (a2 == (uint32_t)result) return (unsigned int)a2;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2, int a3) {\n long long result;\n if (a2 <= 0) return 0LL;\n result = 0LL;\n while (*a1 <= a3) {\n result = (unsigned int)(result + 1);\n ++a1;\n if (a2 == (uint32_t)result) return (unsigned int)a2;\n }\n return result;\n}" + }, + { + "index": 787, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n regex_t regex;\n int reti;\n char* patterns = \"ab{3}\";\n reti = regcomp(®ex, patterns, REG_EXTENDED);\n if (reti) {\n fprintf(stderr, \"Could not compile regex\\n\");\n return \"Regex compilation error\";\n }\n reti = regexec(®ex, text, 0, NULL, 0);\n regfree(®ex);\n if (!reti)\n return \"Found a match!\";\n else\n return \"Not matched!\";\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"ac\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"dc\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"abbbba\"), \"Found a match!\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x70,%rsp\nmov %rdi,-0x68(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0xdd9(%rip),%rax\nmov %rax,-0x58(%rbp)\nmov -0x58(%rbp),%rcx\nlea -0x50(%rbp),%rax\nmov $0x1,%edx\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 10e0 \nmov %eax,-0x5c(%rbp)\ncmpl $0x0,-0x5c(%rbp)\nje 127d \nmov 0x2dc5(%rip),%rax\nmov %rax,%rcx\nmov $0x18,%edx\nmov $0x1,%esi\nlea 0xd9f(%rip),%rdi\ncallq 1110 \nlea 0xdac(%rip),%rax\njmp 12c2 \nmov -0x68(%rbp),%rsi\nlea -0x50(%rbp),%rax\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rax,%rdi\ncallq 1100 \nmov %eax,-0x5c(%rbp)\nlea -0x50(%rbp),%rax\nmov %rax,%rdi\ncallq 10b0 \ncmpl $0x0,-0x5c(%rbp)\njne 12bb \nlea 0xd86(%rip),%rax\njmp 12c2 \nlea 0xd8c(%rip),%rax\nmov -0x8(%rbp),%rdx\nxor %fs:0x28,%rdx\nje 12d6 \ncallq 10c0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aAb3; \"ab{3}\"\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+var_5C], eax\ncmp [rbp+var_5C], 0\njz short loc_1280\nmov rax, cs:__bss_start\nmov rcx, rax; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rax, aCouldNotCompil; \"Could not compile regex\\n\"\nmov rdi, rax; ptr\ncall _fwrite\nlea rax, aRegexCompilati; \"Regex compilation error\"\njmp short loc_12C5\nloc_1280:\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_5C], eax\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\ncmp [rbp+var_5C], 0\njnz short loc_12BE\nlea rax, aFoundAMatch; \"Found a match!\"\njmp short loc_12C5\nloc_12BE:\nlea rax, s2; \"Not matched!\"\nloc_12C5:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12D9\ncall ___stack_chk_fail\nlocret_12D9:\nleave\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n int v2; // [rsp+14h] [rbp-5Ch]\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n unsigned __int64 v4; // [rsp+68h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"ab{3}\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n return \"Regex compilation error\";\n }\n else\n {\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if ( v2 )\n return \"Not matched!\";\n else\n return \"Found a match!\";\n }\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aAb3; \"ab{3}\"\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+var_5C], eax\ncmp [rbp+var_5C], 0\njz short loc_1280\nmov rax, cs:stderr\nmov rcx, rax; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rax, aCouldNotCompil; \"Could not compile regex\\n\"\nmov rdi, rax; ptr\ncall _fwrite\nlea rax, aRegexCompilati; \"Regex compilation error\"\njmp short loc_12C5\nloc_1280:\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_5C], eax\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\ncmp [rbp+var_5C], 0\njnz short loc_12BE\nlea rax, aFoundAMatch; \"Found a match!\"\njmp short loc_12C5\nloc_12BE:\nlea rax, s2; \"Not matched!\"\nloc_12C5:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12D9\ncall ___stack_chk_fail\nlocret_12D9:\nleave\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1209(const char *a1)\n{\n int v2; // [rsp+14h] [rbp-5Ch]\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n unsigned __int64 v4; // [rsp+68h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"ab{3}\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n return \"Regex compilation error\";\n }\n else\n {\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if ( v2 )\n return \"Not matched!\";\n else\n return \"Found a match!\";\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1209(const char *a1) {\n int v2;\n regex_t preg;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n if (regcomp(&preg, \"ab{3}\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n return \"Regex compilation error\";\n } else {\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if (v2)\n return \"Not matched!\";\n else\n return \"Found a match!\";\n }\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n int v2;\n regex_t preg;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n if (regcomp(&preg, \"ab{3}\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n return \"Regex compilation error\";\n } else {\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if (v2)\n return \"Not matched!\";\n else\n return \"Found a match!\";\n }\n}" + }, + { + "index": 787, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n regex_t regex;\n int reti;\n char* patterns = \"ab{3}\";\n reti = regcomp(®ex, patterns, REG_EXTENDED);\n if (reti) {\n fprintf(stderr, \"Could not compile regex\\n\");\n return \"Regex compilation error\";\n }\n reti = regexec(®ex, text, 0, NULL, 0);\n regfree(®ex);\n if (!reti)\n return \"Found a match!\";\n else\n return \"Not matched!\";\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"ac\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"dc\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"abbbba\"), \"Found a match!\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x58,%rsp\nmov %rdi,%rbx\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nmov $0x1,%edx\nlea 0xe23(%rip),%rsi\ncallq 10d0 \ntest %eax,%eax\njne 1271 \nmov %rsp,%rbp\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rbx,%rsi\nmov %rbp,%rdi\ncallq 10e0 \nmov %eax,%ebx\nmov %rbp,%rdi\ncallq 10a0 \ntest %ebx,%ebx\nlea 0xdcd(%rip),%rax\nlea 0xdd5(%rip),%rdx\ncmovne %rdx,%rax\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 1297 \nadd $0x58,%rsp\npop %rbx\npop %rbp\nretq\nmov 0x2da8(%rip),%rcx\nmov $0x18,%edx\nmov $0x1,%esi\nlea 0xdb5(%rip),%rdi\ncallq 10f0 \nlea 0xd6f(%rip),%rax\njmp 125a \ncallq 10b0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+68h+var_20], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"ab{3}\"\ncall _regcomp\ntest eax, eax\njnz short loc_1291\nmov rbp, rsp\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov ebx, eax\nmov rdi, rbp; preg\ncall _regfree\ntest ebx, ebx\nlea rax, s2; \"Not matched!\"\nlea rdx, aFoundAMatch; \"Found a match!\"\ncmovz rax, rdx\nloc_127A:\nmov rdx, [rsp+68h+var_20]\nsub rdx, fs:28h\njnz short loc_12B7\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1291:\nmov rcx, cs:__bss_start; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nlea rax, aRegexCompilati; \"Regex compilation error\"\njmp short loc_127A\nloc_12B7:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // ebx\n const char *result; // rax\n regex_t v3; // [rsp+0h] [rbp-68h] BYREF\n unsigned __int64 v4; // [rsp+48h] [rbp-20h]\n\n v4 = __readfsqword(0x28u);\n if ( regcomp(&v3, \"ab{3}\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n return \"Regex compilation error\";\n }\n else\n {\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n regfree(&v3);\n result = \"Not matched!\";\n if ( !v1 )\n return \"Found a match!\";\n }\n return result;\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+68h+var_20], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"ab{3}\"\ncall _regcomp\ntest eax, eax\njnz short loc_1291\nmov rbp, rsp\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov ebx, eax\nmov rdi, rbp; preg\ncall _regfree\ntest ebx, ebx\nlea rax, s2; \"Not matched!\"\nlea rdx, aFoundAMatch; \"Found a match!\"\ncmovz rax, rdx\nloc_127A:\nmov rdx, [rsp+68h+var_20]\nsub rdx, fs:28h\njnz short loc_12B7\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1291:\nmov rcx, cs:stderr; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nlea rax, aRegexCompilati; \"Regex compilation error\"\njmp short loc_127A\nloc_12B7:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_1209(char *string)\n{\n int v1; // ebx\n const char *result; // rax\n regex_t v3; // [rsp+0h] [rbp-68h] BYREF\n unsigned __int64 v4; // [rsp+48h] [rbp-20h]\n\n v4 = __readfsqword(0x28u);\n if ( regcomp(&v3, \"ab{3}\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n return \"Regex compilation error\";\n }\n else\n {\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n regfree(&v3);\n result = \"Not matched!\";\n if ( !v1 )\n return \"Found a match!\";\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1209(char *string) {\n int v1;\n const char *result;\n regex_t v3;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n if (regcomp(&v3, \"ab{3}\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n return \"Regex compilation error\";\n } else {\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n regfree(&v3);\n result = \"Not matched!\";\n if (!v1) return \"Found a match!\";\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n const char *result;\n regex_t v3;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n if (regcomp(&v3, \"ab{3}\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n return \"Regex compilation error\";\n } else {\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n regfree(&v3);\n result = \"Not matched!\";\n if (!v1) return \"Found a match!\";\n }\n return result;\n}" + }, + { + "index": 787, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n regex_t regex;\n int reti;\n char* patterns = \"ab{3}\";\n reti = regcomp(®ex, patterns, REG_EXTENDED);\n if (reti) {\n fprintf(stderr, \"Could not compile regex\\n\");\n return \"Regex compilation error\";\n }\n reti = regexec(®ex, text, 0, NULL, 0);\n regfree(®ex);\n if (!reti)\n return \"Found a match!\";\n else\n return \"Not matched!\";\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"ac\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"dc\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"abbbba\"), \"Found a match!\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov $0x1,%edx\nlea 0xd56(%rip),%rsi\npush %rbp\nmov %rdi,%rbp\nsub $0x58,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%r12\nmov %r12,%rdi\ncallq 10d0 \ntest %eax,%eax\njne 1358 \nxor %edx,%edx\nxor %r8d,%r8d\nxor %ecx,%ecx\nmov %rbp,%rsi\nmov %r12,%rdi\ncallq 10e0 \nmov %r12,%rdi\nmov %eax,%ebp\ncallq 10a0 \ntest %ebp,%ebp\nlea 0xcee(%rip),%rax\nlea 0xcf6(%rip),%rdx\ncmovne %rdx,%rax\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 137e \nadd $0x58,%rsp\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax)\nmov 0x2cc1(%rip),%rcx\nmov $0x18,%edx\nmov $0x1,%esi\nlea 0xcce(%rip),%rdi\ncallq 10f0 \nlea 0xc88(%rip),%rax\njmp 1339 \ncallq 10b0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"ab{3}\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njnz short loc_1360\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, s2; \"Not matched!\"\nlea rdx, aFoundAMatch; \"Found a match!\"\ncmovz rax, rdx\nloc_1348:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_1386\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1360:\nmov rcx, cs:__bss_start; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nlea rax, aRegexCompilati; \"Regex compilation error\"\njmp short loc_1348\nloc_1386:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // ebx\n const char *result; // rax\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n if ( regcomp(&_0, \"ab{3}\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n return \"Regex compilation error\";\n }\n else\n {\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if ( !v1 )\n return \"Found a match!\";\n }\n return result;\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"ab{3}\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njnz short loc_1360\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, s2; \"Not matched!\"\nlea rdx, aFoundAMatch; \"Found a match!\"\ncmovz rax, rdx\nloc_1348:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_1386\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1360:\nmov rcx, cs:stderr; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nlea rax, aRegexCompilati; \"Regex compilation error\"\njmp short loc_1348\nloc_1386:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_12E0(char *string)\n{\n int v1; // ebx\n const char *result; // rax\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n if ( regcomp(&_0, \"ab{3}\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n return \"Regex compilation error\";\n }\n else\n {\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if ( !v1 )\n return \"Found a match!\";\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_12E0(char *string) {\n int v1;\n const char *result;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n if (regcomp(&_0, \"ab{3}\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n return \"Regex compilation error\";\n } else {\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if (!v1) return \"Found a match!\";\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n const char *result;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n if (regcomp(&_0, \"ab{3}\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n return \"Regex compilation error\";\n } else {\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if (!v1) return \"Found a match!\";\n }\n return result;\n}" + }, + { + "index": 787, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n regex_t regex;\n int reti;\n char* patterns = \"ab{3}\";\n reti = regcomp(®ex, patterns, REG_EXTENDED);\n if (reti) {\n fprintf(stderr, \"Could not compile regex\\n\");\n return \"Regex compilation error\";\n }\n reti = regexec(®ex, text, 0, NULL, 0);\n regfree(®ex);\n if (!reti)\n return \"Found a match!\";\n else\n return \"Not matched!\";\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"ac\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"dc\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"abbbba\"), \"Found a match!\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov $0x1,%edx\nlea 0xd56(%rip),%rsi\npush %rbp\nmov %rdi,%rbp\nsub $0x58,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%r12\nmov %r12,%rdi\ncallq 10d0 \ntest %eax,%eax\njne 1358 \nxor %edx,%edx\nxor %r8d,%r8d\nxor %ecx,%ecx\nmov %rbp,%rsi\nmov %r12,%rdi\ncallq 10e0 \nmov %r12,%rdi\nmov %eax,%ebp\ncallq 10a0 \ntest %ebp,%ebp\nlea 0xcee(%rip),%rax\nlea 0xcf6(%rip),%rdx\ncmovne %rdx,%rax\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 137e \nadd $0x58,%rsp\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax)\nmov 0x2cc1(%rip),%rcx\nmov $0x18,%edx\nmov $0x1,%esi\nlea 0xcce(%rip),%rdi\ncallq 10f0 \nlea 0xc88(%rip),%rax\njmp 1339 \ncallq 10b0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"ab{3}\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njnz short loc_1360\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, s2; \"Not matched!\"\nlea rdx, aFoundAMatch; \"Found a match!\"\ncmovz rax, rdx\nloc_1348:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_1386\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1360:\nmov rcx, cs:__bss_start; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nlea rax, aRegexCompilati; \"Regex compilation error\"\njmp short loc_1348\nloc_1386:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // ebx\n const char *result; // rax\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n if ( regcomp(&_0, \"ab{3}\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n return \"Regex compilation error\";\n }\n else\n {\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if ( !v1 )\n return \"Found a match!\";\n }\n return result;\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"ab{3}\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njnz short loc_1360\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, s2; \"Not matched!\"\nlea rdx, aFoundAMatch; \"Found a match!\"\ncmovz rax, rdx\nloc_1348:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_1386\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1360:\nmov rcx, cs:stderr; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nlea rax, aRegexCompilati; \"Regex compilation error\"\njmp short loc_1348\nloc_1386:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_12E0(char *string)\n{\n int v1; // ebx\n const char *result; // rax\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n if ( regcomp(&_0, \"ab{3}\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n return \"Regex compilation error\";\n }\n else\n {\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if ( !v1 )\n return \"Found a match!\";\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_12E0(char *string) {\n int v1;\n const char *result;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n if (regcomp(&_0, \"ab{3}\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n return \"Regex compilation error\";\n } else {\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if (!v1) return \"Found a match!\";\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n const char *result;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n if (regcomp(&_0, \"ab{3}\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n return \"Regex compilation error\";\n } else {\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if (!v1) return \"Found a match!\";\n }\n return result;\n}" + }, + { + "index": 788, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nstruct dynamicTuple {\n\n char elements[100];\n\n};\n\n\n\n", + "func": "struct dynamicTuple func0(char test_list[][100], int listSize,\n char test_str[]) {\n struct dynamicTuple result;\n strcpy(result.elements, \"\");\n for (int i = 0; i < listSize; i++) {\n strcat(result.elements, test_list[i]);\n strcat(result.elements, \", \");\n }\n strcat(result.elements, test_str);\n return result;\n}", + "test": "int main() {\n\n char list1[2][100] = {\"WEB\", \"is\"};\n\n char list2[2][100] = {\"We\", \"are\"};\n\n char list3[2][100] = {\"Part\", \"is\"};\n\n\n\n struct dynamicTuple result;\n\n\n\n result = func0(list1, 2, \"best\");\n\n assert(strcmp(result.elements, \"WEB, is, best\") == 0);\n\n\n\n result = func0(list2, 2, \"Developers\");\n\n assert(strcmp(result.elements, \"We, are, Developers\") == 0);\n\n\n\n result = func0(list3, 2, \"Wrong\");\n\n assert(strcmp(result.elements, \"Part, is, Wrong\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0xa8,%rsp\nmov %rdi,-0x98(%rbp)\nmov %rsi,-0xa0(%rbp)\nmov %edx,-0xa4(%rbp)\nmov %rcx,-0xb0(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmovb $0x0,-0x80(%rbp)\nmovl $0x0,-0x84(%rbp)\njmp 126a \nmov -0x84(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0xa0(%rbp),%rax\nadd %rax,%rdx\nlea -0x80(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10b0 \nlea -0x80(%rbp),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nlea -0x80(%rbp),%rax\nadd %rdx,%rax\nmovw $0x202c,(%rax)\nmovb $0x0,0x2(%rax)\naddl $0x1,-0x84(%rbp)\nmov -0x84(%rbp),%eax\ncmp -0xa4(%rbp),%eax\njl 11f3 \nmov -0xb0(%rbp),%rdx\nlea -0x80(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10b0 \nmov -0x98(%rbp),%rax\nmov -0x80(%rbp),%rcx\nmov -0x78(%rbp),%rbx\nmov %rcx,(%rax)\nmov %rbx,0x8(%rax)\nmov -0x70(%rbp),%rcx\nmov -0x68(%rbp),%rbx\nmov %rcx,0x10(%rax)\nmov %rbx,0x18(%rax)\nmov -0x60(%rbp),%rcx\nmov -0x58(%rbp),%rbx\nmov %rcx,0x20(%rax)\nmov %rbx,0x28(%rax)\nmov -0x50(%rbp),%rcx\nmov -0x48(%rbp),%rbx\nmov %rcx,0x30(%rax)\nmov %rbx,0x38(%rax)\nmov -0x40(%rbp),%rcx\nmov -0x38(%rbp),%rbx\nmov %rcx,0x40(%rax)\nmov %rbx,0x48(%rax)\nmov -0x30(%rbp),%rcx\nmov -0x28(%rbp),%rbx\nmov %rcx,0x50(%rax)\nmov %rbx,0x58(%rax)\nmov -0x20(%rbp),%edx\nmov %edx,0x60(%rax)\nmov -0x18(%rbp),%rax\nxor %fs:0x28,%rax\nje 1312 \ncallq 1080 <__stack_chk_fail@plt>\nmov -0x98(%rbp),%rax\nadd $0xa8,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 0A8h\nmov [rbp+var_98], rdi\nmov [rbp+var_A0], rsi\nmov [rbp+var_A4], edx\nmov [rbp+src], rcx\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov [rbp+dest], 0\nmov [rbp+var_84], 0\njmp short loc_1277\nloc_1213:\nmov eax, [rbp+var_84]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_A0]\nadd rdx, rax\nlea rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\nlea rax, [rbp+dest]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nlea rax, [rbp+dest]\nadd rax, rdx\nmov word ptr [rax], 202Ch\nmov byte ptr [rax+2], 0\nadd [rbp+var_84], 1\nloc_1277:\nmov eax, [rbp+var_84]\ncmp eax, [rbp+var_A4]\njl short loc_1213\nmov rdx, [rbp+src]\nlea rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\nmov rax, [rbp+var_98]\nmov rcx, qword ptr [rbp+dest]\nmov rbx, [rbp+var_78]\nmov [rax], rcx\nmov [rax+8], rbx\nmov rcx, [rbp+var_70]\nmov rbx, [rbp+var_68]\nmov [rax+10h], rcx\nmov [rax+18h], rbx\nmov rcx, [rbp+var_60]\nmov rbx, [rbp+var_58]\nmov [rax+20h], rcx\nmov [rax+28h], rbx\nmov rcx, [rbp+var_50]\nmov rbx, [rbp+var_48]\nmov [rax+30h], rcx\nmov [rax+38h], rbx\nmov rcx, [rbp+var_40]\nmov rbx, [rbp+var_38]\nmov [rax+40h], rcx\nmov [rax+48h], rbx\nmov rcx, [rbp+var_30]\nmov rbx, [rbp+var_28]\nmov [rax+50h], rcx\nmov [rax+58h], rbx\nmov edx, [rbp+var_20]\nmov [rax+60h], edx\nmov rax, [rbp+var_18]\nsub rax, fs:28h\njz short loc_131B\ncall ___stack_chk_fail\nloc_131B:\nmov rax, [rbp+var_98]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3, const char *a4)\n{\n __int64 v4; // rbx\n __int64 v5; // rbx\n __int64 v6; // rbx\n __int64 v7; // rbx\n __int64 v8; // rbx\n __int64 v9; // rbx\n int i; // [rsp+2Ch] [rbp-84h]\n char dest[8]; // [rsp+30h] [rbp-80h] BYREF\n __int64 v15; // [rsp+38h] [rbp-78h]\n __int64 v16; // [rsp+40h] [rbp-70h]\n __int64 v17; // [rsp+48h] [rbp-68h]\n __int64 v18; // [rsp+50h] [rbp-60h]\n __int64 v19; // [rsp+58h] [rbp-58h]\n __int64 v20; // [rsp+60h] [rbp-50h]\n __int64 v21; // [rsp+68h] [rbp-48h]\n __int64 v22; // [rsp+70h] [rbp-40h]\n __int64 v23; // [rsp+78h] [rbp-38h]\n __int64 v24; // [rsp+80h] [rbp-30h]\n __int64 v25; // [rsp+88h] [rbp-28h]\n int v26; // [rsp+90h] [rbp-20h]\n unsigned __int64 v27; // [rsp+98h] [rbp-18h]\n\n v27 = __readfsqword(0x28u);\n dest[0] = 0;\n for ( i = 0; i < a3; ++i )\n {\n strcat(dest, (const char *)(a2 + 100LL * i));\n strcpy(&dest[strlen(dest)], \", \");\n }\n strcat(dest, a4);\n v4 = v15;\n *(_QWORD *)a1 = *(_QWORD *)dest;\n *(_QWORD *)(a1 + 8) = v4;\n v5 = v17;\n *(_QWORD *)(a1 + 16) = v16;\n *(_QWORD *)(a1 + 24) = v5;\n v6 = v19;\n *(_QWORD *)(a1 + 32) = v18;\n *(_QWORD *)(a1 + 40) = v6;\n v7 = v21;\n *(_QWORD *)(a1 + 48) = v20;\n *(_QWORD *)(a1 + 56) = v7;\n v8 = v23;\n *(_QWORD *)(a1 + 64) = v22;\n *(_QWORD *)(a1 + 72) = v8;\n v9 = v25;\n *(_QWORD *)(a1 + 80) = v24;\n *(_QWORD *)(a1 + 88) = v9;\n *(_DWORD *)(a1 + 96) = v26;\n return a1;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 0A8h\nmov [rbp+var_98], rdi\nmov [rbp+var_A0], rsi\nmov [rbp+var_A4], edx\nmov [rbp+src], rcx\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov [rbp+dest], 0\nmov [rbp+var_84], 0\njmp short loc_1277\nloc_1213:\nmov eax, [rbp+var_84]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nlea rdx, ds:0[rax*4]\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_A0]\nadd rdx, rax\nlea rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\nlea rax, [rbp+dest]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nlea rax, [rbp+dest]\nadd rax, rdx\nmov word ptr [rax], 202Ch\nmov byte ptr [rax+2], 0\nadd [rbp+var_84], 1\nloc_1277:\nmov eax, [rbp+var_84]\ncmp eax, [rbp+var_A4]\njl short loc_1213\nmov rdx, [rbp+src]\nlea rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\nmov rax, [rbp+var_98]\nmov rcx, qword ptr [rbp+dest]\nmov rbx, [rbp+var_78]\nmov [rax], rcx\nmov [rax+8], rbx\nmov rcx, [rbp+var_70]\nmov rbx, [rbp+var_68]\nmov [rax+10h], rcx\nmov [rax+18h], rbx\nmov rcx, [rbp+var_60]\nmov rbx, [rbp+var_58]\nmov [rax+20h], rcx\nmov [rax+28h], rbx\nmov rcx, [rbp+var_50]\nmov rbx, [rbp+var_48]\nmov [rax+30h], rcx\nmov [rax+38h], rbx\nmov rcx, [rbp+var_40]\nmov rbx, [rbp+var_38]\nmov [rax+40h], rcx\nmov [rax+48h], rbx\nmov rcx, [rbp+var_30]\nmov rbx, [rbp+var_28]\nmov [rax+50h], rcx\nmov [rax+58h], rbx\nmov edx, [rbp+var_20]\nmov [rax+60h], edx\nmov rax, [rbp+var_18]\nsub rax, fs:28h\njz short loc_131B\ncall ___stack_chk_fail\nloc_131B:\nmov rax, [rbp+var_98]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11C9(__int64 a1, __int64 a2, int a3, const char *a4)\n{\n __int64 v4; // rbx\n __int64 v5; // rbx\n __int64 v6; // rbx\n __int64 v7; // rbx\n __int64 v8; // rbx\n __int64 v9; // rbx\n int i; // [rsp+2Ch] [rbp-84h]\n char dest[8]; // [rsp+30h] [rbp-80h] BYREF\n __int64 v15; // [rsp+38h] [rbp-78h]\n __int64 v16; // [rsp+40h] [rbp-70h]\n __int64 v17; // [rsp+48h] [rbp-68h]\n __int64 v18; // [rsp+50h] [rbp-60h]\n __int64 v19; // [rsp+58h] [rbp-58h]\n __int64 v20; // [rsp+60h] [rbp-50h]\n __int64 v21; // [rsp+68h] [rbp-48h]\n __int64 v22; // [rsp+70h] [rbp-40h]\n __int64 v23; // [rsp+78h] [rbp-38h]\n __int64 v24; // [rsp+80h] [rbp-30h]\n __int64 v25; // [rsp+88h] [rbp-28h]\n int v26; // [rsp+90h] [rbp-20h]\n unsigned __int64 v27; // [rsp+98h] [rbp-18h]\n\n v27 = __readfsqword(0x28u);\n dest[0] = 0;\n for ( i = 0; i < a3; ++i )\n {\n strcat(dest, (const char *)(a2 + 100LL * i));\n strcpy(&dest[strlen(dest)], \", \");\n }\n strcat(dest, a4);\n v4 = v15;\n *(_QWORD *)a1 = *(_QWORD *)dest;\n *(_QWORD *)(a1 + 8) = v4;\n v5 = v17;\n *(_QWORD *)(a1 + 16) = v16;\n *(_QWORD *)(a1 + 24) = v5;\n v6 = v19;\n *(_QWORD *)(a1 + 32) = v18;\n *(_QWORD *)(a1 + 40) = v6;\n v7 = v21;\n *(_QWORD *)(a1 + 48) = v20;\n *(_QWORD *)(a1 + 56) = v7;\n v8 = v23;\n *(_QWORD *)(a1 + 64) = v22;\n *(_QWORD *)(a1 + 72) = v8;\n v9 = v25;\n *(_QWORD *)(a1 + 80) = v24;\n *(_QWORD *)(a1 + 88) = v9;\n *(_DWORD *)(a1 + 96) = v26;\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11C9(long long a1, long long a2, int a3, const char *a4) {\n long long v4;\n long long v5;\n long long v6;\n long long v7;\n long long v8;\n long long v9;\n int i;\n char dest[8];\n long long v15;\n long long v16;\n long long v17;\n long long v18;\n long long v19;\n long long v20;\n long long v21;\n long long v22;\n long long v23;\n long long v24;\n long long v25;\n int v26;\n unsigned long long v27;\n v27 = __readfsqword(40u);\n dest[0] = 0;\n for (i = 0; i < a3; ++i) {\n strcat(dest, (const char *)(a2 + 100LL * i));\n strcpy(&dest[strlen(dest)], \", \");\n }\n strcat(dest, a4);\n v4 = v15;\n *(uint64_t *)a1 = *(uint64_t *)dest;\n *(uint64_t *)(a1 + 8) = v4;\n v5 = v17;\n *(uint64_t *)(a1 + 16) = v16;\n *(uint64_t *)(a1 + 24) = v5;\n v6 = v19;\n *(uint64_t *)(a1 + 32) = v18;\n *(uint64_t *)(a1 + 40) = v6;\n v7 = v21;\n *(uint64_t *)(a1 + 48) = v20;\n *(uint64_t *)(a1 + 56) = v7;\n v8 = v23;\n *(uint64_t *)(a1 + 64) = v22;\n *(uint64_t *)(a1 + 72) = v8;\n v9 = v25;\n *(uint64_t *)(a1 + 80) = v24;\n *(uint64_t *)(a1 + 88) = v9;\n *(uint32_t *)(a1 + 96) = v26;\n return a1;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3, const char *a4) {\n long long v4;\n long long v5;\n long long v6;\n long long v7;\n long long v8;\n long long v9;\n int i;\n char dest[8];\n long long v15;\n long long v16;\n long long v17;\n long long v18;\n long long v19;\n long long v20;\n long long v21;\n long long v22;\n long long v23;\n long long v24;\n long long v25;\n int v26;\n unsigned long long v27;\n v27 = __readfsqword(40u);\n dest[0] = 0;\n for (i = 0; i < a3; ++i) {\n strcat(dest, (const char *)(a2 + 100LL * i));\n strcpy(&dest[strlen(dest)], \", \");\n }\n strcat(dest, a4);\n v4 = v15;\n *(uint64_t *)a1 = *(uint64_t *)dest;\n *(uint64_t *)(a1 + 8) = v4;\n v5 = v17;\n *(uint64_t *)(a1 + 16) = v16;\n *(uint64_t *)(a1 + 24) = v5;\n v6 = v19;\n *(uint64_t *)(a1 + 32) = v18;\n *(uint64_t *)(a1 + 40) = v6;\n v7 = v21;\n *(uint64_t *)(a1 + 48) = v20;\n *(uint64_t *)(a1 + 56) = v7;\n v8 = v23;\n *(uint64_t *)(a1 + 64) = v22;\n *(uint64_t *)(a1 + 72) = v8;\n v9 = v25;\n *(uint64_t *)(a1 + 80) = v24;\n *(uint64_t *)(a1 + 88) = v9;\n *(uint32_t *)(a1 + 96) = v26;\n return a1;\n}" + }, + { + "index": 788, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nstruct dynamicTuple {\n\n char elements[100];\n\n};\n\n\n\n", + "func": "struct dynamicTuple func0(char test_list[][100], int listSize,\n char test_str[]) {\n struct dynamicTuple result;\n strcpy(result.elements, \"\");\n for (int i = 0; i < listSize; i++) {\n strcat(result.elements, test_list[i]);\n strcat(result.elements, \", \");\n }\n strcat(result.elements, test_str);\n return result;\n}", + "test": "int main() {\n\n char list1[2][100] = {\"WEB\", \"is\"};\n\n char list2[2][100] = {\"We\", \"are\"};\n\n char list3[2][100] = {\"Part\", \"is\"};\n\n\n\n struct dynamicTuple result;\n\n\n\n result = func0(list1, 2, \"best\");\n\n assert(strcmp(result.elements, \"WEB, is, best\") == 0);\n\n\n\n result = func0(list2, 2, \"Developers\");\n\n assert(strcmp(result.elements, \"We, are, Developers\") == 0);\n\n\n\n result = func0(list3, 2, \"Wrong\");\n\n assert(strcmp(result.elements, \"Part, is, Wrong\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x70,%rsp\nmov %rdi,%r12\nmov %rcx,%r14\nmov %fs:0x28,%rax\nmov %rax,0x68(%rsp)\nxor %eax,%eax\nmovb $0x0,(%rsp)\ntest %edx,%edx\njle 11fa \nmov %rsi,%rbx\nlea -0x1(%rdx),%eax\nlea (%rax,%rax,4),%rax\nlea (%rax,%rax,4),%rax\nlea 0x64(%rsi,%rax,4),%r13\nmov %rsp,%rbp\nmov $0x64,%edx\nmov %rbx,%rsi\nmov %rbp,%rdi\ncallq 1070 <__strcat_chk@plt>\nmov $0x64,%edx\nlea 0xe1b(%rip),%rsi\nmov %rbp,%rdi\ncallq 1070 <__strcat_chk@plt>\nadd $0x64,%rbx\ncmp %r13,%rbx\njne 11cd \nmov %rsp,%rdi\nmov $0x64,%edx\nmov %r14,%rsi\ncallq 1070 <__strcat_chk@plt>\nmovdqa (%rsp),%xmm0\nmovups %xmm0,(%r12)\nmovdqa 0x10(%rsp),%xmm1\nmovups %xmm1,0x10(%r12)\nmovdqa 0x20(%rsp),%xmm2\nmovups %xmm2,0x20(%r12)\nmovdqa 0x30(%rsp),%xmm3\nmovups %xmm3,0x30(%r12)\nmovdqa 0x40(%rsp),%xmm4\nmovups %xmm4,0x40(%r12)\nmovdqa 0x50(%rsp),%xmm5\nmovups %xmm5,0x50(%r12)\nmov 0x60(%rsp),%eax\nmov %eax,0x60(%r12)\nmov 0x68(%rsp),%rax\nxor %fs:0x28,%rax\njne 1279 \nmov %r12,%rax\nadd $0x70,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\ncallq 1080 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 78h\nmov r12, rdi\nmov r15, rcx\nmov rax, fs:28h\nmov [rsp+0A8h+var_40], rax\nxor eax, eax\nmov byte ptr [rsp+0A8h+var_A8], 0\ntest edx, edx\njle short loc_121E\nmov rbx, rsi\nmovsxd rdx, edx\nlea rax, [rdx+rdx*4]\nlea rax, [rax+rax*4]\nlea r14, [rsi+rax*4]\nlea r13, unk_2004\nloc_11F2:\nmov rbp, rsp\nmov edx, 64h ; 'd'\nmov rsi, rbx\nmov rdi, rbp\ncall ___strcat_chk\nmov edx, 64h ; 'd'\nmov rsi, r13\nmov rdi, rbp\ncall ___strcat_chk\nadd rbx, 64h ; 'd'\ncmp rbx, r14\njnz short loc_11F2\nloc_121E:\nmov rdi, rsp\nmov edx, 64h ; 'd'\nmov rsi, r15\ncall ___strcat_chk\nmovdqa xmm0, [rsp+0A8h+var_A8]\nmovups xmmword ptr [r12], xmm0\nmovdqa xmm1, [rsp+0A8h+var_98]\nmovups xmmword ptr [r12+10h], xmm1\nmovdqa xmm2, [rsp+0A8h+var_88]\nmovups xmmword ptr [r12+20h], xmm2\nmovdqa xmm3, [rsp+0A8h+var_78]\nmovups xmmword ptr [r12+30h], xmm3\nmovdqa xmm4, [rsp+0A8h+var_68]\nmovups xmmword ptr [r12+40h], xmm4\nmovdqa xmm5, [rsp+0A8h+var_58]\nmovups xmmword ptr [r12+50h], xmm5\nmov eax, [rsp+0A8h+var_48]\nmov [r12+60h], eax\nmov rax, [rsp+0A8h+var_40]\nsub rax, fs:28h\njnz short loc_129F\nmov rax, r12\nadd rsp, 78h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_129F:\ncall ___stack_chk_fail", + "ida_pseudo": "__m128i *__fastcall func0(__m128i *a1, __int64 a2, int a3, __int64 a4)\n{\n __int64 v5; // rbx\n __int64 v6; // r14\n __m128i v8; // [rsp+0h] [rbp-A8h] BYREF\n __m128i v9; // [rsp+10h] [rbp-98h] BYREF\n __m128i v10; // [rsp+20h] [rbp-88h] BYREF\n __m128i v11; // [rsp+30h] [rbp-78h] BYREF\n __m128i v12; // [rsp+40h] [rbp-68h] BYREF\n __m128i v13; // [rsp+50h] [rbp-58h] BYREF\n __int32 v14; // [rsp+60h] [rbp-48h]\n unsigned __int64 v15; // [rsp+68h] [rbp-40h]\n\n v15 = __readfsqword(0x28u);\n v8.m128i_i8[0] = 0;\n if ( a3 > 0 )\n {\n v5 = a2;\n v6 = a2 + 100LL * a3;\n do\n {\n __strcat_chk(&v8, v5, 100LL);\n __strcat_chk(&v8, &unk_2004, 100LL);\n v5 += 100LL;\n }\n while ( v5 != v6 );\n }\n __strcat_chk(&v8, a4, 100LL);\n *a1 = _mm_load_si128(&v8);\n a1[1] = _mm_load_si128(&v9);\n a1[2] = _mm_load_si128(&v10);\n a1[3] = _mm_load_si128(&v11);\n a1[4] = _mm_load_si128(&v12);\n a1[5] = _mm_load_si128(&v13);\n a1[6].m128i_i32[0] = v14;\n return a1;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 78h\nmov r12, rdi\nmov r15, rcx\nmov rax, fs:28h\nmov [rsp+0A8h+var_40], rax\nxor eax, eax\nmov byte ptr [rsp+0A8h+var_A8], 0\ntest edx, edx\njle short loc_121E\nmov rbx, rsi\nmovsxd rdx, edx\nlea rax, [rdx+rdx*4]\nlea rax, [rax+rax*4]\nlea r14, [rsi+rax*4]\nlea r13, unk_2004\nloc_11F2:\nmov rbp, rsp\nmov edx, 64h ; 'd'\nmov rsi, rbx\nmov rdi, rbp\ncall ___strcat_chk\nmov edx, 64h ; 'd'\nmov rsi, r13\nmov rdi, rbp\ncall ___strcat_chk\nadd rbx, 64h ; 'd'\ncmp rbx, r14\njnz short loc_11F2\nloc_121E:\nmov rdi, rsp\nmov edx, 64h ; 'd'\nmov rsi, r15\ncall ___strcat_chk\nmovdqa xmm0, [rsp+0A8h+var_A8]\nmovups xmmword ptr [r12], xmm0\nmovdqa xmm1, [rsp+0A8h+var_98]\nmovups xmmword ptr [r12+10h], xmm1\nmovdqa xmm2, [rsp+0A8h+var_88]\nmovups xmmword ptr [r12+20h], xmm2\nmovdqa xmm3, [rsp+0A8h+var_78]\nmovups xmmword ptr [r12+30h], xmm3\nmovdqa xmm4, [rsp+0A8h+var_68]\nmovups xmmword ptr [r12+40h], xmm4\nmovdqa xmm5, [rsp+0A8h+var_58]\nmovups xmmword ptr [r12+50h], xmm5\nmov eax, [rsp+0A8h+var_48]\nmov [r12+60h], eax\nmov rax, [rsp+0A8h+var_40]\nsub rax, fs:28h\njnz short loc_129F\nmov rax, r12\nadd rsp, 78h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_129F:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__m128i *__fastcall sub_11A9(__m128i *a1, __int64 a2, int a3, __int64 a4)\n{\n __int64 v5; // rbx\n __int64 v6; // r14\n __m128i v8; // [rsp+0h] [rbp-A8h] BYREF\n __m128i v9; // [rsp+10h] [rbp-98h] BYREF\n __m128i v10; // [rsp+20h] [rbp-88h] BYREF\n __m128i v11; // [rsp+30h] [rbp-78h] BYREF\n __m128i v12; // [rsp+40h] [rbp-68h] BYREF\n __m128i v13; // [rsp+50h] [rbp-58h] BYREF\n __int32 v14; // [rsp+60h] [rbp-48h]\n unsigned __int64 v15; // [rsp+68h] [rbp-40h]\n\n v15 = __readfsqword(0x28u);\n v8.m128i_i8[0] = 0;\n if ( a3 > 0 )\n {\n v5 = a2;\n v6 = a2 + 100LL * a3;\n do\n {\n __strcat_chk(&v8, v5, 100LL);\n __strcat_chk(&v8, &unk_2004, 100LL);\n v5 += 100LL;\n }\n while ( v5 != v6 );\n }\n __strcat_chk(&v8, a4, 100LL);\n *a1 = _mm_load_si128(&v8);\n a1[1] = _mm_load_si128(&v9);\n a1[2] = _mm_load_si128(&v10);\n a1[3] = _mm_load_si128(&v11);\n a1[4] = _mm_load_si128(&v12);\n a1[5] = _mm_load_si128(&v13);\n a1[6].m128i_i32[0] = v14;\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__m128i *sub_11A9(__m128i *a1, long long a2, int a3, long long a4) {\n long long v5;\n long long v6;\n __m128i v8;\n __m128i v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n int v14;\n unsigned long long v15;\n v15 = __readfsqword(40u);\n v8.m128i_i8[0] = 0;\n if (a3 > 0) {\n v5 = a2;\n v6 = a2 + 100LL * a3;\n do {\n __strcat_chk(&v8, v5, 100LL);\n __strcat_chk(&v8, &unk_2004, 100LL);\n v5 += 100LL;\n } while (v5 != v6);\n }\n __strcat_chk(&v8, a4, 100LL);\n *a1 = _mm_load_si128(&v8);\n a1[1] = _mm_load_si128(&v9);\n a1[2] = _mm_load_si128(&v10);\n a1[3] = _mm_load_si128(&v11);\n a1[4] = _mm_load_si128(&v12);\n a1[5] = _mm_load_si128(&v13);\n a1[6].m128i_i32[0] = v14;\n return a1;\n}", + "ida_pseudo_norm": "__m128i *func0(__m128i *a1, long long a2, int a3, long long a4) {\n long long v5;\n long long v6;\n __m128i v8;\n __m128i v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n int v14;\n unsigned long long v15;\n v15 = __readfsqword(40u);\n v8.m128i_i8[0] = 0;\n if (a3 > 0) {\n v5 = a2;\n v6 = a2 + 100LL * a3;\n do {\n __strcat_chk(&v8, v5, 100LL);\n __strcat_chk(&v8, &unk_2004, 100LL);\n v5 += 100LL;\n } while (v5 != v6);\n }\n __strcat_chk(&v8, a4, 100LL);\n *a1 = _mm_load_si128(&v8);\n a1[1] = _mm_load_si128(&v9);\n a1[2] = _mm_load_si128(&v10);\n a1[3] = _mm_load_si128(&v11);\n a1[4] = _mm_load_si128(&v12);\n a1[5] = _mm_load_si128(&v13);\n a1[6].m128i_i32[0] = v14;\n return a1;\n}" + }, + { + "index": 788, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nstruct dynamicTuple {\n\n char elements[100];\n\n};\n\n\n\n", + "func": "struct dynamicTuple func0(char test_list[][100], int listSize,\n char test_str[]) {\n struct dynamicTuple result;\n strcpy(result.elements, \"\");\n for (int i = 0; i < listSize; i++) {\n strcat(result.elements, test_list[i]);\n strcat(result.elements, \", \");\n }\n strcat(result.elements, test_str);\n return result;\n}", + "test": "int main() {\n\n char list1[2][100] = {\"WEB\", \"is\"};\n\n char list2[2][100] = {\"We\", \"are\"};\n\n char list3[2][100] = {\"Part\", \"is\"};\n\n\n\n struct dynamicTuple result;\n\n\n\n result = func0(list1, 2, \"best\");\n\n assert(strcmp(result.elements, \"WEB, is, best\") == 0);\n\n\n\n result = func0(list2, 2, \"Developers\");\n\n assert(strcmp(result.elements, \"We, are, Developers\") == 0);\n\n\n\n result = func0(list3, 2, \"Wrong\");\n\n assert(strcmp(result.elements, \"Part, is, Wrong\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\nmov %rcx,%r14\npush %r13\npush %r12\nmov %rdi,%r12\npush %rbp\npush %rbx\nsub $0x78,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x68(%rsp)\nxor %eax,%eax\nmov %rsp,%rbp\nmovb $0x0,(%rsp)\ntest %edx,%edx\njle 15c0 \nlea -0x1(%rdx),%eax\nmov %rsi,%r15\nlea 0xac0(%rip),%rbx\nmov %rsp,%rbp\nlea (%rax,%rax,4),%rax\nlea (%rax,%rax,4),%rax\nlea 0x64(%rsi,%rax,4),%r13\nnopl 0x0(%rax)\nmov %rbp,%rdi\nmov (%rdi),%edx\nadd $0x4,%rdi\nlea -0x1010101(%rdx),%eax\nnot %edx\nand %edx,%eax\nand $0x80808080,%eax\nje 155b \nmov %eax,%edx\nshr $0x10,%edx\ntest $0x8080,%eax\ncmove %edx,%eax\nlea 0x2(%rdi),%rdx\ncmove %rdx,%rdi\nmov $0x64,%edx\nmov %eax,%esi\nadd %al,%sil\nmov %r15,%rsi\nsbb $0x3,%rdi\nadd $0x64,%r15\ncallq 10d0 <__stpcpy_chk@plt>\nmov %rbp,%rcx\nmov $0x3,%edx\nmov %rbx,%rsi\nsub %rax,%rcx\nmov %rax,%rdi\nadd $0x64,%rcx\ncallq 10c0 <__memcpy_chk@plt>\ncmp %r13,%r15\njne 1558 \nmov $0x64,%edx\nmov %r14,%rsi\nmov %rbp,%rdi\ncallq 1090 <__strcat_chk@plt>\nmov 0x60(%rsp),%eax\nmovdqa (%rsp),%xmm0\nmovdqa 0x10(%rsp),%xmm1\nmovdqa 0x20(%rsp),%xmm2\nmov %eax,0x60(%r12)\nmovdqa 0x30(%rsp),%xmm3\nmovdqa 0x40(%rsp),%xmm4\nmovdqa 0x50(%rsp),%xmm5\nmovups %xmm0,(%r12)\nmovups %xmm1,0x10(%r12)\nmovups %xmm2,0x20(%r12)\nmovups %xmm3,0x30(%r12)\nmovups %xmm4,0x40(%r12)\nmovups %xmm5,0x50(%r12)\nmov 0x68(%rsp),%rax\nxor %fs:0x28,%rax\njne 1641 \nadd $0x78,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\ncallq 10a0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov r15, rcx\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 78h\nmov rax, fs:28h\nmov [rsp+var_s68], rax\nxor eax, eax\nmov rbp, rsp\nmov byte ptr [rsp+var_s0], 0\ntest edx, edx\njle short loc_15AD\nmovsxd rdx, edx\nmov rbx, rsi\nlea r13, unk_2004\nmov rbp, rsp\nlea rax, [rdx+rdx*4]\nlea rax, [rax+rax*4]\nlea r14, [rsi+rax*4]\nnop\nloc_1570:\nmov rdi, rbp; s\ncall _strlen\nmov rsi, rbx\nmov edx, 64h ; 'd'\nadd rbx, 64h ; 'd'\nlea rdi, [rbp+rax+var_s0]\ncall ___stpcpy_chk\nmov rcx, rbp\nmov edx, 3\nmov rsi, r13\nsub rcx, rax\nmov rdi, rax\nadd rcx, 64h ; 'd'\ncall ___memcpy_chk\ncmp rbx, r14\njnz short loc_1570\nloc_15AD:\nmov edx, 64h ; 'd'\nmov rsi, r15\nmov rdi, rbp\ncall ___strcat_chk\nmov eax, [rsp+var_s60]\nmovdqa xmm0, [rsp+var_s0]\nmovdqa xmm1, [rsp+var_s10]\nmovdqa xmm2, [rsp+var_s20]\nmovdqa xmm3, [rsp+var_s30]\nmovdqa xmm4, [rsp+var_s40]\nmov [r12+60h], eax\nmovdqa xmm5, [rsp+var_s50]\nmovups xmmword ptr [r12], xmm0\nmovups xmmword ptr [r12+10h], xmm1\nmovups xmmword ptr [r12+20h], xmm2\nmovups xmmword ptr [r12+30h], xmm3\nmovups xmmword ptr [r12+40h], xmm4\nmovups xmmword ptr [r12+50h], xmm5\nmov rax, [rsp+var_s68]\nsub rax, fs:28h\njnz short loc_162E\nadd rsp, 78h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_162E:\ncall ___stack_chk_fail", + "ida_pseudo": "__m128i *__fastcall func0(__m128i *a1, __int64 a2, int a3, __int64 a4)\n{\n __int64 v5; // rbx\n __int64 v6; // r14\n size_t v7; // rax\n __int64 v8; // rsi\n __int64 v9; // rax\n __m128i v10; // xmm0\n __m128i v11; // xmm1\n __m128i v12; // xmm2\n __m128i v13; // xmm3\n __m128i v14; // xmm4\n __m128i v15; // xmm5\n __m128i vars0; // [rsp+0h] [rbp+0h] BYREF\n __m128i vars10; // [rsp+10h] [rbp+10h] BYREF\n __m128i vars20; // [rsp+20h] [rbp+20h] BYREF\n __m128i vars30; // [rsp+30h] [rbp+30h] BYREF\n __m128i vars40; // [rsp+40h] [rbp+40h] BYREF\n __m128i vars50; // [rsp+50h] [rbp+50h] BYREF\n __int32 vars60; // [rsp+60h] [rbp+60h]\n unsigned __int64 vars68; // [rsp+68h] [rbp+68h]\n\n vars68 = __readfsqword(0x28u);\n vars0.m128i_i8[0] = 0;\n if ( a3 > 0 )\n {\n v5 = a2;\n v6 = a2 + 100LL * a3;\n do\n {\n v7 = strlen(vars0.m128i_i8);\n v8 = v5;\n v5 += 100LL;\n v9 = __stpcpy_chk(&vars0.m128i_i8[v7], v8, 100LL);\n __memcpy_chk(v9, &unk_2004, 3LL, (char *)&vars0 - v9 + 100);\n }\n while ( v5 != v6 );\n }\n __strcat_chk(&vars0, a4, 100LL);\n v10 = _mm_load_si128(&vars0);\n v11 = _mm_load_si128(&vars10);\n v12 = _mm_load_si128(&vars20);\n v13 = _mm_load_si128(&vars30);\n v14 = _mm_load_si128(&vars40);\n a1[6].m128i_i32[0] = vars60;\n v15 = _mm_load_si128(&vars50);\n *a1 = v10;\n a1[1] = v11;\n a1[2] = v12;\n a1[3] = v13;\n a1[4] = v14;\n a1[5] = v15;\n return a1;\n}", + "ida_strip_asm": "sub_1520:\nendbr64\npush r15\nmov r15, rcx\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 78h\nmov rax, fs:28h\nmov [rsp+var_s68], rax\nxor eax, eax\nmov rbp, rsp\nmov byte ptr [rsp+var_s0], 0\ntest edx, edx\njle short loc_15AD\nmovsxd rdx, edx\nmov rbx, rsi\nlea r13, unk_2004\nmov rbp, rsp\nlea rax, [rdx+rdx*4]\nlea rax, [rax+rax*4]\nlea r14, [rsi+rax*4]\nnop\nloc_1570:\nmov rdi, rbp; s\ncall _strlen\nmov rsi, rbx\nmov edx, 64h ; 'd'\nadd rbx, 64h ; 'd'\nlea rdi, [rbp+rax+var_s0]\ncall ___stpcpy_chk\nmov rcx, rbp\nmov edx, 3\nmov rsi, r13\nsub rcx, rax\nmov rdi, rax\nadd rcx, 64h ; 'd'\ncall ___memcpy_chk\ncmp rbx, r14\njnz short loc_1570\nloc_15AD:\nmov edx, 64h ; 'd'\nmov rsi, r15\nmov rdi, rbp\ncall ___strcat_chk\nmov eax, [rsp+var_s60]\nmovdqa xmm0, [rsp+var_s0]\nmovdqa xmm1, [rsp+var_s10]\nmovdqa xmm2, [rsp+var_s20]\nmovdqa xmm3, [rsp+var_s30]\nmovdqa xmm4, [rsp+var_s40]\nmov [r12+60h], eax\nmovdqa xmm5, [rsp+var_s50]\nmovups xmmword ptr [r12], xmm0\nmovups xmmword ptr [r12+10h], xmm1\nmovups xmmword ptr [r12+20h], xmm2\nmovups xmmword ptr [r12+30h], xmm3\nmovups xmmword ptr [r12+40h], xmm4\nmovups xmmword ptr [r12+50h], xmm5\nmov rax, [rsp+var_s68]\nsub rax, fs:28h\njnz short loc_162E\nadd rsp, 78h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_162E:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__m128i *__fastcall sub_1520(__m128i *a1, __int64 a2, int a3, __int64 a4)\n{\n __int64 v5; // rbx\n __int64 v6; // r14\n size_t v7; // rax\n __int64 v8; // rsi\n __int64 v9; // rax\n __m128i v10; // xmm0\n __m128i v11; // xmm1\n __m128i v12; // xmm2\n __m128i v13; // xmm3\n __m128i v14; // xmm4\n __m128i v15; // xmm5\n __m128i vars0; // [rsp+0h] [rbp+0h] BYREF\n __m128i vars10; // [rsp+10h] [rbp+10h] BYREF\n __m128i vars20; // [rsp+20h] [rbp+20h] BYREF\n __m128i vars30; // [rsp+30h] [rbp+30h] BYREF\n __m128i vars40; // [rsp+40h] [rbp+40h] BYREF\n __m128i vars50; // [rsp+50h] [rbp+50h] BYREF\n __int32 vars60; // [rsp+60h] [rbp+60h]\n unsigned __int64 vars68; // [rsp+68h] [rbp+68h]\n\n vars68 = __readfsqword(0x28u);\n vars0.m128i_i8[0] = 0;\n if ( a3 > 0 )\n {\n v5 = a2;\n v6 = a2 + 100LL * a3;\n do\n {\n v7 = strlen(vars0.m128i_i8);\n v8 = v5;\n v5 += 100LL;\n v9 = __stpcpy_chk(&vars0.m128i_i8[v7], v8, 100LL);\n __memcpy_chk(v9, &unk_2004, 3LL, (char *)&vars0 - v9 + 100);\n }\n while ( v5 != v6 );\n }\n __strcat_chk(&vars0, a4, 100LL);\n v10 = _mm_load_si128(&vars0);\n v11 = _mm_load_si128(&vars10);\n v12 = _mm_load_si128(&vars20);\n v13 = _mm_load_si128(&vars30);\n v14 = _mm_load_si128(&vars40);\n a1[6].m128i_i32[0] = vars60;\n v15 = _mm_load_si128(&vars50);\n *a1 = v10;\n a1[1] = v11;\n a1[2] = v12;\n a1[3] = v13;\n a1[4] = v14;\n a1[5] = v15;\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__m128i *sub_1520(__m128i *a1, long long a2, int a3, long long a4) {\n long long v5;\n long long v6;\n unsigned int v7;\n long long v8;\n long long v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n __m128i v15;\n __m128i vars0;\n __m128i vars10;\n __m128i vars20;\n __m128i vars30;\n __m128i vars40;\n __m128i vars50;\n int vars60;\n unsigned long long vars68;\n vars68 = __readfsqword(40u);\n vars0.m128i_i8[0] = 0;\n if (a3 > 0) {\n v5 = a2;\n v6 = a2 + 100LL * a3;\n do {\n v7 = strlen(vars0.m128i_i8);\n v8 = v5;\n v5 += 100LL;\n v9 = __stpcpy_chk(&vars0.m128i_i8[v7], v8, 100LL);\n __memcpy_chk(v9, &unk_2004, 3LL, (char *)&vars0 - v9 + 100);\n } while (v5 != v6);\n }\n __strcat_chk(&vars0, a4, 100LL);\n v10 = _mm_load_si128(&vars0);\n v11 = _mm_load_si128(&vars10);\n v12 = _mm_load_si128(&vars20);\n v13 = _mm_load_si128(&vars30);\n v14 = _mm_load_si128(&vars40);\n a1[6].m128i_i32[0] = vars60;\n v15 = _mm_load_si128(&vars50);\n *a1 = v10;\n a1[1] = v11;\n a1[2] = v12;\n a1[3] = v13;\n a1[4] = v14;\n a1[5] = v15;\n return a1;\n}", + "ida_pseudo_norm": "__m128i *func0(__m128i *a1, long long a2, int a3, long long a4) {\n long long v5;\n long long v6;\n unsigned int v7;\n long long v8;\n long long v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n __m128i v15;\n __m128i vars0;\n __m128i vars10;\n __m128i vars20;\n __m128i vars30;\n __m128i vars40;\n __m128i vars50;\n int vars60;\n unsigned long long vars68;\n vars68 = __readfsqword(40u);\n vars0.m128i_i8[0] = 0;\n if (a3 > 0) {\n v5 = a2;\n v6 = a2 + 100LL * a3;\n do {\n v7 = strlen(vars0.m128i_i8);\n v8 = v5;\n v5 += 100LL;\n v9 = __stpcpy_chk(&vars0.m128i_i8[v7], v8, 100LL);\n __memcpy_chk(v9, &unk_2004, 3LL, (char *)&vars0 - v9 + 100);\n } while (v5 != v6);\n }\n __strcat_chk(&vars0, a4, 100LL);\n v10 = _mm_load_si128(&vars0);\n v11 = _mm_load_si128(&vars10);\n v12 = _mm_load_si128(&vars20);\n v13 = _mm_load_si128(&vars30);\n v14 = _mm_load_si128(&vars40);\n a1[6].m128i_i32[0] = vars60;\n v15 = _mm_load_si128(&vars50);\n *a1 = v10;\n a1[1] = v11;\n a1[2] = v12;\n a1[3] = v13;\n a1[4] = v14;\n a1[5] = v15;\n return a1;\n}" + }, + { + "index": 788, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nstruct dynamicTuple {\n\n char elements[100];\n\n};\n\n\n\n", + "func": "struct dynamicTuple func0(char test_list[][100], int listSize,\n char test_str[]) {\n struct dynamicTuple result;\n strcpy(result.elements, \"\");\n for (int i = 0; i < listSize; i++) {\n strcat(result.elements, test_list[i]);\n strcat(result.elements, \", \");\n }\n strcat(result.elements, test_str);\n return result;\n}", + "test": "int main() {\n\n char list1[2][100] = {\"WEB\", \"is\"};\n\n char list2[2][100] = {\"We\", \"are\"};\n\n char list3[2][100] = {\"Part\", \"is\"};\n\n\n\n struct dynamicTuple result;\n\n\n\n result = func0(list1, 2, \"best\");\n\n assert(strcmp(result.elements, \"WEB, is, best\") == 0);\n\n\n\n result = func0(list2, 2, \"Developers\");\n\n assert(strcmp(result.elements, \"We, are, Developers\") == 0);\n\n\n\n result = func0(list3, 2, \"Wrong\");\n\n assert(strcmp(result.elements, \"Part, is, Wrong\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\nmov %rcx,%r14\npush %r13\npush %r12\nmov %rdi,%r12\npush %rbp\npush %rbx\nsub $0x78,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x68(%rsp)\nxor %eax,%eax\nmov %rsp,%rbp\nmovb $0x0,(%rsp)\ntest %edx,%edx\njle 15c0 \nlea -0x1(%rdx),%eax\nmov %rsi,%r15\nlea 0xac0(%rip),%rbx\nmov %rsp,%rbp\nlea (%rax,%rax,4),%rax\nlea (%rax,%rax,4),%rax\nlea 0x64(%rsi,%rax,4),%r13\nnopl 0x0(%rax)\nmov %rbp,%rdi\nmov (%rdi),%edx\nadd $0x4,%rdi\nlea -0x1010101(%rdx),%eax\nnot %edx\nand %edx,%eax\nand $0x80808080,%eax\nje 155b \nmov %eax,%edx\nshr $0x10,%edx\ntest $0x8080,%eax\ncmove %edx,%eax\nlea 0x2(%rdi),%rdx\ncmove %rdx,%rdi\nmov $0x64,%edx\nmov %eax,%esi\nadd %al,%sil\nmov %r15,%rsi\nsbb $0x3,%rdi\nadd $0x64,%r15\ncallq 10d0 <__stpcpy_chk@plt>\nmov %rbp,%rcx\nmov $0x3,%edx\nmov %rbx,%rsi\nsub %rax,%rcx\nmov %rax,%rdi\nadd $0x64,%rcx\ncallq 10c0 <__memcpy_chk@plt>\ncmp %r13,%r15\njne 1558 \nmov $0x64,%edx\nmov %r14,%rsi\nmov %rbp,%rdi\ncallq 1090 <__strcat_chk@plt>\nmov 0x60(%rsp),%eax\nmovdqa (%rsp),%xmm0\nmovdqa 0x10(%rsp),%xmm1\nmovdqa 0x20(%rsp),%xmm2\nmov %eax,0x60(%r12)\nmovdqa 0x30(%rsp),%xmm3\nmovdqa 0x40(%rsp),%xmm4\nmovdqa 0x50(%rsp),%xmm5\nmovups %xmm0,(%r12)\nmovups %xmm1,0x10(%r12)\nmovups %xmm2,0x20(%r12)\nmovups %xmm3,0x30(%r12)\nmovups %xmm4,0x40(%r12)\nmovups %xmm5,0x50(%r12)\nmov 0x68(%rsp),%rax\nxor %fs:0x28,%rax\njne 1641 \nadd $0x78,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\ncallq 10a0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov r15, rcx\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 78h\nmov rax, fs:28h\nmov [rsp+var_s68], rax\nxor eax, eax\nmov rbp, rsp\nmov byte ptr [rsp+var_s0], 0\ntest edx, edx\njle short loc_15AD\nmovsxd rdx, edx\nmov rbx, rsi\nlea r13, unk_2004\nmov rbp, rsp\nlea rax, [rdx+rdx*4]\nlea rax, [rax+rax*4]\nlea r14, [rsi+rax*4]\nnop\nloc_1570:\nmov rdi, rbp; s\ncall _strlen\nmov rsi, rbx\nmov edx, 64h ; 'd'\nadd rbx, 64h ; 'd'\nlea rdi, [rbp+rax+var_s0]\ncall ___stpcpy_chk\nmov rcx, rbp\nmov edx, 3\nmov rsi, r13\nsub rcx, rax\nmov rdi, rax\nadd rcx, 64h ; 'd'\ncall ___memcpy_chk\ncmp rbx, r14\njnz short loc_1570\nloc_15AD:\nmov edx, 64h ; 'd'\nmov rsi, r15\nmov rdi, rbp\ncall ___strcat_chk\nmov eax, [rsp+var_s60]\nmovdqa xmm0, [rsp+var_s0]\nmovdqa xmm1, [rsp+var_s10]\nmovdqa xmm2, [rsp+var_s20]\nmovdqa xmm3, [rsp+var_s30]\nmovdqa xmm4, [rsp+var_s40]\nmov [r12+60h], eax\nmovdqa xmm5, [rsp+var_s50]\nmovups xmmword ptr [r12], xmm0\nmovups xmmword ptr [r12+10h], xmm1\nmovups xmmword ptr [r12+20h], xmm2\nmovups xmmword ptr [r12+30h], xmm3\nmovups xmmword ptr [r12+40h], xmm4\nmovups xmmword ptr [r12+50h], xmm5\nmov rax, [rsp+var_s68]\nsub rax, fs:28h\njnz short loc_162E\nadd rsp, 78h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_162E:\ncall ___stack_chk_fail", + "ida_pseudo": "__m128i *__fastcall func0(__m128i *a1, __int64 a2, int a3, __int64 a4)\n{\n __int64 v5; // rbx\n __int64 v6; // r14\n size_t v7; // rax\n __int64 v8; // rsi\n __int64 v9; // rax\n __m128i v10; // xmm0\n __m128i v11; // xmm1\n __m128i v12; // xmm2\n __m128i v13; // xmm3\n __m128i v14; // xmm4\n __m128i v15; // xmm5\n __m128i vars0; // [rsp+0h] [rbp+0h] BYREF\n __m128i vars10; // [rsp+10h] [rbp+10h] BYREF\n __m128i vars20; // [rsp+20h] [rbp+20h] BYREF\n __m128i vars30; // [rsp+30h] [rbp+30h] BYREF\n __m128i vars40; // [rsp+40h] [rbp+40h] BYREF\n __m128i vars50; // [rsp+50h] [rbp+50h] BYREF\n __int32 vars60; // [rsp+60h] [rbp+60h]\n unsigned __int64 vars68; // [rsp+68h] [rbp+68h]\n\n vars68 = __readfsqword(0x28u);\n vars0.m128i_i8[0] = 0;\n if ( a3 > 0 )\n {\n v5 = a2;\n v6 = a2 + 100LL * a3;\n do\n {\n v7 = strlen(vars0.m128i_i8);\n v8 = v5;\n v5 += 100LL;\n v9 = __stpcpy_chk(&vars0.m128i_i8[v7], v8, 100LL);\n __memcpy_chk(v9, &unk_2004, 3LL, (char *)&vars0 - v9 + 100);\n }\n while ( v5 != v6 );\n }\n __strcat_chk(&vars0, a4, 100LL);\n v10 = _mm_load_si128(&vars0);\n v11 = _mm_load_si128(&vars10);\n v12 = _mm_load_si128(&vars20);\n v13 = _mm_load_si128(&vars30);\n v14 = _mm_load_si128(&vars40);\n a1[6].m128i_i32[0] = vars60;\n v15 = _mm_load_si128(&vars50);\n *a1 = v10;\n a1[1] = v11;\n a1[2] = v12;\n a1[3] = v13;\n a1[4] = v14;\n a1[5] = v15;\n return a1;\n}", + "ida_strip_asm": "sub_1520:\nendbr64\npush r15\nmov r15, rcx\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 78h\nmov rax, fs:28h\nmov [rsp+var_s68], rax\nxor eax, eax\nmov rbp, rsp\nmov byte ptr [rsp+var_s0], 0\ntest edx, edx\njle short loc_15AD\nmovsxd rdx, edx\nmov rbx, rsi\nlea r13, unk_2004\nmov rbp, rsp\nlea rax, [rdx+rdx*4]\nlea rax, [rax+rax*4]\nlea r14, [rsi+rax*4]\nnop\nloc_1570:\nmov rdi, rbp; s\ncall _strlen\nmov rsi, rbx\nmov edx, 64h ; 'd'\nadd rbx, 64h ; 'd'\nlea rdi, [rbp+rax+var_s0]\ncall ___stpcpy_chk\nmov rcx, rbp\nmov edx, 3\nmov rsi, r13\nsub rcx, rax\nmov rdi, rax\nadd rcx, 64h ; 'd'\ncall ___memcpy_chk\ncmp rbx, r14\njnz short loc_1570\nloc_15AD:\nmov edx, 64h ; 'd'\nmov rsi, r15\nmov rdi, rbp\ncall ___strcat_chk\nmov eax, [rsp+var_s60]\nmovdqa xmm0, [rsp+var_s0]\nmovdqa xmm1, [rsp+var_s10]\nmovdqa xmm2, [rsp+var_s20]\nmovdqa xmm3, [rsp+var_s30]\nmovdqa xmm4, [rsp+var_s40]\nmov [r12+60h], eax\nmovdqa xmm5, [rsp+var_s50]\nmovups xmmword ptr [r12], xmm0\nmovups xmmword ptr [r12+10h], xmm1\nmovups xmmword ptr [r12+20h], xmm2\nmovups xmmword ptr [r12+30h], xmm3\nmovups xmmword ptr [r12+40h], xmm4\nmovups xmmword ptr [r12+50h], xmm5\nmov rax, [rsp+var_s68]\nsub rax, fs:28h\njnz short loc_162E\nadd rsp, 78h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_162E:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__m128i *__fastcall sub_1520(__m128i *a1, __int64 a2, int a3, __int64 a4)\n{\n __int64 v5; // rbx\n __int64 v6; // r14\n size_t v7; // rax\n __int64 v8; // rsi\n __int64 v9; // rax\n __m128i v10; // xmm0\n __m128i v11; // xmm1\n __m128i v12; // xmm2\n __m128i v13; // xmm3\n __m128i v14; // xmm4\n __m128i v15; // xmm5\n __m128i vars0; // [rsp+0h] [rbp+0h] BYREF\n __m128i vars10; // [rsp+10h] [rbp+10h] BYREF\n __m128i vars20; // [rsp+20h] [rbp+20h] BYREF\n __m128i vars30; // [rsp+30h] [rbp+30h] BYREF\n __m128i vars40; // [rsp+40h] [rbp+40h] BYREF\n __m128i vars50; // [rsp+50h] [rbp+50h] BYREF\n __int32 vars60; // [rsp+60h] [rbp+60h]\n unsigned __int64 vars68; // [rsp+68h] [rbp+68h]\n\n vars68 = __readfsqword(0x28u);\n vars0.m128i_i8[0] = 0;\n if ( a3 > 0 )\n {\n v5 = a2;\n v6 = a2 + 100LL * a3;\n do\n {\n v7 = strlen(vars0.m128i_i8);\n v8 = v5;\n v5 += 100LL;\n v9 = __stpcpy_chk(&vars0.m128i_i8[v7], v8, 100LL);\n __memcpy_chk(v9, &unk_2004, 3LL, (char *)&vars0 - v9 + 100);\n }\n while ( v5 != v6 );\n }\n __strcat_chk(&vars0, a4, 100LL);\n v10 = _mm_load_si128(&vars0);\n v11 = _mm_load_si128(&vars10);\n v12 = _mm_load_si128(&vars20);\n v13 = _mm_load_si128(&vars30);\n v14 = _mm_load_si128(&vars40);\n a1[6].m128i_i32[0] = vars60;\n v15 = _mm_load_si128(&vars50);\n *a1 = v10;\n a1[1] = v11;\n a1[2] = v12;\n a1[3] = v13;\n a1[4] = v14;\n a1[5] = v15;\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__m128i *sub_1520(__m128i *a1, long long a2, int a3, long long a4) {\n long long v5;\n long long v6;\n unsigned int v7;\n long long v8;\n long long v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n __m128i v15;\n __m128i vars0;\n __m128i vars10;\n __m128i vars20;\n __m128i vars30;\n __m128i vars40;\n __m128i vars50;\n int vars60;\n unsigned long long vars68;\n vars68 = __readfsqword(40u);\n vars0.m128i_i8[0] = 0;\n if (a3 > 0) {\n v5 = a2;\n v6 = a2 + 100LL * a3;\n do {\n v7 = strlen(vars0.m128i_i8);\n v8 = v5;\n v5 += 100LL;\n v9 = __stpcpy_chk(&vars0.m128i_i8[v7], v8, 100LL);\n __memcpy_chk(v9, &unk_2004, 3LL, (char *)&vars0 - v9 + 100);\n } while (v5 != v6);\n }\n __strcat_chk(&vars0, a4, 100LL);\n v10 = _mm_load_si128(&vars0);\n v11 = _mm_load_si128(&vars10);\n v12 = _mm_load_si128(&vars20);\n v13 = _mm_load_si128(&vars30);\n v14 = _mm_load_si128(&vars40);\n a1[6].m128i_i32[0] = vars60;\n v15 = _mm_load_si128(&vars50);\n *a1 = v10;\n a1[1] = v11;\n a1[2] = v12;\n a1[3] = v13;\n a1[4] = v14;\n a1[5] = v15;\n return a1;\n}", + "ida_pseudo_norm": "__m128i *func0(__m128i *a1, long long a2, int a3, long long a4) {\n long long v5;\n long long v6;\n unsigned int v7;\n long long v8;\n long long v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n __m128i v15;\n __m128i vars0;\n __m128i vars10;\n __m128i vars20;\n __m128i vars30;\n __m128i vars40;\n __m128i vars50;\n int vars60;\n unsigned long long vars68;\n vars68 = __readfsqword(40u);\n vars0.m128i_i8[0] = 0;\n if (a3 > 0) {\n v5 = a2;\n v6 = a2 + 100LL * a3;\n do {\n v7 = strlen(vars0.m128i_i8);\n v8 = v5;\n v5 += 100LL;\n v9 = __stpcpy_chk(&vars0.m128i_i8[v7], v8, 100LL);\n __memcpy_chk(v9, &unk_2004, 3LL, (char *)&vars0 - v9 + 100);\n } while (v5 != v6);\n }\n __strcat_chk(&vars0, a4, 100LL);\n v10 = _mm_load_si128(&vars0);\n v11 = _mm_load_si128(&vars10);\n v12 = _mm_load_si128(&vars20);\n v13 = _mm_load_si128(&vars30);\n v14 = _mm_load_si128(&vars40);\n a1[6].m128i_i32[0] = vars60;\n v15 = _mm_load_si128(&vars50);\n *a1 = v10;\n a1[1] = v11;\n a1[2] = v12;\n a1[3] = v13;\n a1[4] = v14;\n a1[5] = v15;\n return a1;\n}" + }, + { + "index": 789, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "double func0(int s, int l) {\n double perimeter = s * l;\n return perimeter;\n}", + "test": "int main() {\n\n assert(func0(4, 20) == 80);\n\n assert(func0(10, 15) == 150);\n\n assert(func0(9, 7) == 63);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov -0x14(%rbp),%eax\nimul -0x18(%rbp),%eax\ncvtsi2sd %eax,%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmovsd -0x8(%rbp),%xmm0\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov eax, [rbp+var_14]\nimul eax, [rbp+var_18]\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "double __fastcall func0(int a1, int a2)\n{\n return (double)(a2 * a1);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov eax, [rbp+var_14]\nimul eax, [rbp+var_18]\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "double __fastcall sub_1149(int a1, int a2)\n{\n return (double)(a2 * a1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1149(int a1, int a2) { return (double)(a2 * a1); }", + "ida_pseudo_norm": "double func0(int a1, int a2) { return (double)(a2 * a1); }" + }, + { + "index": 790, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int nums[], int length) {\n for (int i = 0; i < length; i++) {\n if (nums[i] % 2 != i % 2) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n int arr1[] = {3, 2, 1};\n\n int arr2[] = {1, 2, 3};\n\n int arr3[] = {2, 1, 4};\n\n\n\n assert(func0(arr1, 3) == false);\n\n assert(func0(arr2, 3) == false);\n\n assert(func0(arr3, 3) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11c1 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncltd\nshr $0x1f,%edx\nadd %edx,%eax\nand $0x1,%eax\nsub %edx,%eax\nmov %eax,%ecx\nmov -0x4(%rbp),%eax\ncltd\nshr $0x1f,%edx\nadd %edx,%eax\nand $0x1,%eax\nsub %edx,%eax\ncmp %eax,%ecx\nje 11bd \nmov $0x0,%eax\njmp 11ce \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1181 \nmov $0x1,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 0\njmp short loc_11CB\nloc_1181:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov ecx, edx\nmov edx, [rbp+var_4]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\ncmp ecx, eax\njz short loc_11C7\nmov eax, 0\njmp short loc_11D8\nloc_11C7:\nadd [rbp+var_4], 1\nloc_11CB:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1181\nmov eax, 1\nloc_11D8:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) % 2 != i % 2 )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 0\njmp short loc_11CB\nloc_1181:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov ecx, edx\nmov edx, [rbp+var_4]\nmov eax, edx\nsar eax, 1Fh\nshr eax, 1Fh\nadd edx, eax\nand edx, 1\nsub edx, eax\nmov eax, edx\ncmp ecx, eax\njz short loc_11C7\nmov eax, 0\njmp short loc_11D8\nloc_11C7:\nadd [rbp+var_4], 1\nloc_11CB:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1181\nmov eax, 1\nloc_11D8:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) % 2 != i % 2 )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int i;\n for (i = 0; i < a2; ++i) {\n if (*(uint32_t *)(4LL * i + a1) % 2 != i % 2) return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int i;\n for (i = 0; i < a2; ++i) {\n if (*(uint32_t *)(4LL * i + a1) % 2 != i % 2) return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": 790, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int nums[], int length) {\n for (int i = 0; i < length; i++) {\n if (nums[i] % 2 != i % 2) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n int arr1[] = {3, 2, 1};\n\n int arr2[] = {1, 2, 3};\n\n int arr3[] = {2, 1, 4};\n\n\n\n assert(func0(arr1, 3) == false);\n\n assert(func0(arr2, 3) == false);\n\n assert(func0(arr3, 3) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11ae \nlea -0x1(%rsi),%r8d\nmov $0x0,%ecx\njmp 117f \nmov %rax,%rcx\nmov (%rdi,%rcx,4),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nand $0x1,%eax\nsub %edx,%eax\nmov %ecx,%esi\nshr $0x1f,%esi\nlea (%rsi,%rcx,1),%edx\nand $0x1,%edx\nsub %esi,%edx\ncmp %edx,%eax\njne 11b4 \nlea 0x1(%rcx),%rax\ncmp %r8,%rcx\njne 117c \nmov $0x1,%eax\nretq\nmov $0x1,%eax\nretq\nmov $0x0,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11AC\nmovsxd rsi, esi\nmov ecx, 0\nloc_1179:\nmov eax, [rdi+rcx*4]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nand eax, 1\nsub eax, edx\nmov r8d, ecx\nshr r8d, 1Fh\nlea edx, [r8+rcx]\nand edx, 1\nsub edx, r8d\ncmp eax, edx\njnz short loc_11B2\nadd rcx, 1\ncmp rcx, rsi\njnz short loc_1179\nmov eax, 1\nretn\nloc_11AC:\nmov eax, 1\nretn\nloc_11B2:\nmov eax, 0\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // rcx\n\n if ( a2 <= 0 )\n return 1LL;\n v2 = 0LL;\n while ( *(_DWORD *)(a1 + 4 * v2) % 2 == (int)v2 % 2 )\n {\n if ( ++v2 == a2 )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11AC\nmovsxd rsi, esi\nmov ecx, 0\nloc_1179:\nmov eax, [rdi+rcx*4]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nand eax, 1\nsub eax, edx\nmov r8d, ecx\nshr r8d, 1Fh\nlea edx, [r8+rcx]\nand edx, 1\nsub edx, r8d\ncmp eax, edx\njnz short loc_11B2\nadd rcx, 1\ncmp rcx, rsi\njnz short loc_1179\nmov eax, 1\nretn\nloc_11AC:\nmov eax, 1\nretn\nloc_11B2:\nmov eax, 0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n __int64 v2; // rcx\n\n if ( a2 <= 0 )\n return 1LL;\n v2 = 0LL;\n while ( *(_DWORD *)(a1 + 4 * v2) % 2 == (int)v2 % 2 )\n {\n if ( ++v2 == a2 )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n long long v2;\n if (a2 <= 0) return 1LL;\n v2 = 0LL;\n while (*(uint32_t *)(a1 + 4 * v2) % 2 == (int)v2 % 2) {\n if (++v2 == a2) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n if (a2 <= 0) return 1LL;\n v2 = 0LL;\n while (*(uint32_t *)(a1 + 4 * v2) % 2 == (int)v2 % 2) {\n if (++v2 == a2) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 791, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int *elements;\n\n int size;\n\n} Tuple;\n\n\n\n", + "func": "Tuple func0(Tuple test_tup) {\n Tuple res;\n int *elements = (int *)malloc(test_tup.size * sizeof(int));\n int count = 0;\n for (int i = 0; i < test_tup.size; i++) {\n elements[count] = test_tup.elements[i];\n count++;\n }\n res.elements = elements;\n res.size = count;\n return res;\n}", + "test": "int main() {\n\n Tuple test_tup1 = {(int[]){1, 5, 7, 10}, 4};\n\n Tuple test_tup2 = {(int[]){2, 6, 8, 11}, 4};\n\n Tuple test_tup3 = {(int[]){3, 7, 9, 12}, 4};\n\n\n\n Tuple result1 = func0(test_tup1);\n\n Tuple result2 = func0(test_tup2);\n\n Tuple result3 = func0(test_tup3);\n\n\n\n assert(result1.size == 4 && result1.elements[0] == 1 && result1.elements[1] == 5 && result1.elements[2] == 7 && result1.elements[3] == 10);\n\n assert(result2.size == 4 && result2.elements[0] == 2 && result2.elements[1] == 6 && result2.elements[2] == 8 && result2.elements[3] == 11);\n\n assert(result3.size == 4 && result3.elements[0] == 3 && result3.elements[1] == 7 && result3.elements[2] == 9 && result3.elements[3] == 12);\n\n\n\n printf(\"All tests passed!\\n\");\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,%rax\nmov %rsi,%rcx\nmov %rcx,%rdx\nmov %rax,-0x30(%rbp)\nmov %rdx,-0x28(%rbp)\nmov -0x28(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x18(%rbp)\nmovl $0x0,-0x20(%rbp)\nmovl $0x0,-0x1c(%rbp)\njmp 121d \nmov -0x30(%rbp),%rax\nmov -0x1c(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x2,%rdx\nadd %rdx,%rax\nmov -0x20(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x20(%rbp)\naddl $0x1,-0x1c(%rbp)\nmov -0x28(%rbp),%eax\ncmp %eax,-0x1c(%rbp)\njl 11eb \nmov -0x18(%rbp),%rax\nmov %rax,-0x10(%rbp)\nmov -0x20(%rbp),%eax\nmov %eax,-0x8(%rbp)\nmov -0x10(%rbp),%rax\nmov -0x8(%rbp),%rdx\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov rax, rdi\nmov rcx, rsi\nmov rdx, rcx\nmov [rbp+var_30], rax\nmov [rbp+var_28], rdx\nmov eax, dword ptr [rbp+var_28]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_20], 0\nmov [rbp+var_1C], 0\njmp short loc_121D\nloc_11EB:\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_20], 1\nadd [rbp+var_1C], 1\nloc_121D:\nmov eax, dword ptr [rbp+var_28]\ncmp [rbp+var_1C], eax\njl short loc_11EB\nmov rax, [rbp+var_18]\nmov [rbp+var_10], rax\nmov eax, [rbp+var_20]\nmov dword ptr [rbp+var_8], eax\nmov rax, [rbp+var_10]\nmov rdx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2)\n{\n int v3; // [rsp+10h] [rbp-20h]\n int i; // [rsp+14h] [rbp-1Ch]\n _DWORD *v5; // [rsp+18h] [rbp-18h]\n\n v5 = malloc(4LL * a2);\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n v5[v3++] = *(_DWORD *)(4LL * i + a1);\n return v5;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov rax, rdi\nmov rcx, rsi\nmov rdx, rcx\nmov [rbp+var_30], rax\nmov [rbp+var_28], rdx\nmov eax, dword ptr [rbp+var_28]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_20], 0\nmov [rbp+var_1C], 0\njmp short loc_121D\nloc_11EB:\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_20], 1\nadd [rbp+var_1C], 1\nloc_121D:\nmov eax, dword ptr [rbp+var_28]\ncmp [rbp+var_1C], eax\njl short loc_11EB\nmov rax, [rbp+var_18]\nmov [rbp+var_10], rax\nmov eax, [rbp+var_20]\nmov dword ptr [rbp+var_8], eax\nmov rax, [rbp+var_10]\nmov rdx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(__int64 a1, int a2)\n{\n int v3; // [rsp+10h] [rbp-20h]\n int i; // [rsp+14h] [rbp-1Ch]\n _DWORD *v5; // [rsp+18h] [rbp-18h]\n\n v5 = malloc(4LL * a2);\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n v5[v3++] = *(_DWORD *)(4LL * i + a1);\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(long long a1, int a2) {\n int v3;\n int i;\n uint32_t *v5;\n v5 = malloc(4LL * a2);\n v3 = 0;\n for (i = 0; i < a2; ++i) v5[v3++] = *(uint32_t *)(4LL * i + a1);\n return v5;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2) {\n int v3;\n int i;\n uint32_t *v5;\n v5 = malloc(4LL * a2);\n v3 = 0;\n for (i = 0; i < a2; ++i) v5[v3++] = *(uint32_t *)(4LL * i + a1);\n return v5;\n}" + }, + { + "index": 791, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int *elements;\n\n int size;\n\n} Tuple;\n\n\n\n", + "func": "Tuple func0(Tuple test_tup) {\n Tuple res;\n int *elements = (int *)malloc(test_tup.size * sizeof(int));\n int count = 0;\n for (int i = 0; i < test_tup.size; i++) {\n elements[count] = test_tup.elements[i];\n count++;\n }\n res.elements = elements;\n res.size = count;\n return res;\n}", + "test": "int main() {\n\n Tuple test_tup1 = {(int[]){1, 5, 7, 10}, 4};\n\n Tuple test_tup2 = {(int[]){2, 6, 8, 11}, 4};\n\n Tuple test_tup3 = {(int[]){3, 7, 9, 12}, 4};\n\n\n\n Tuple result1 = func0(test_tup1);\n\n Tuple result2 = func0(test_tup2);\n\n Tuple result3 = func0(test_tup3);\n\n\n\n assert(result1.size == 4 && result1.elements[0] == 1 && result1.elements[1] == 5 && result1.elements[2] == 7 && result1.elements[3] == 10);\n\n assert(result2.size == 4 && result2.elements[0] == 2 && result2.elements[1] == 6 && result2.elements[2] == 8 && result2.elements[3] == 11);\n\n assert(result3.size == 4 && result3.elements[0] == 3 && result3.elements[1] == 7 && result3.elements[2] == 9 && result3.elements[3] == 12);\n\n\n\n printf(\"All tests passed!\\n\");\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbp\nmov %rsi,%r12\nmov %esi,%ebx\nmovslq %esi,%rdi\nshl $0x2,%rdi\ncallq 10b0 \ntest %r12d,%r12d\njle 11f0 \nmov %rbp,%rdi\nlea -0x1(%r12),%esi\nmov $0x0,%edx\nmov (%rdi,%rdx,4),%ecx\nmov %ecx,(%rax,%rdx,4)\nmov %rdx,%rcx\nadd $0x1,%rdx\ncmp %rsi,%rcx\njne 11d7 \nmov %ebx,%edx\npop %rbx\npop %rbp\npop %r12\nretq\nmov $0x0,%ebx\njmp 11e9 \n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov r13, rsi\nmov r12d, esi\nmovsxd rbx, esi\nshl rbx, 2\nmov rdi, rbx; size\ncall _malloc\ntest r13d, r13d\njle short loc_11F7\nmov edx, 0\nloc_11D9:\nmov ecx, [rbp+rdx+0]\nmov [rax+rdx], ecx\nadd rdx, 4\ncmp rbx, rdx\njnz short loc_11D9\nloc_11E9:\nmov edx, r12d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_11F7:\nmov r12d, 0\njmp short loc_11E9", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2)\n{\n char *result; // rax\n __int64 v3; // rdx\n\n result = (char *)malloc(4LL * a2);\n if ( a2 > 0 )\n {\n v3 = 0LL;\n do\n {\n *(_DWORD *)&result[v3] = *(_DWORD *)(a1 + v3);\n v3 += 4LL;\n }\n while ( 4LL * a2 != v3 );\n }\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov r13, rsi\nmov r12d, esi\nmovsxd rbx, esi\nshl rbx, 2\nmov rdi, rbx; size\ncall _malloc\ntest r13d, r13d\njle short loc_11F7\nmov edx, 0\nloc_11D9:\nmov ecx, [rbp+rdx+0]\nmov [rax+rdx], ecx\nadd rdx, 4\ncmp rbx, rdx\njnz short loc_11D9\nloc_11E9:\nmov edx, r12d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_11F7:\nmov r12d, 0\njmp short loc_11E9", + "ida_strip_pseudo": "char *__fastcall sub_11A9(__int64 a1, int a2)\n{\n char *result; // rax\n __int64 v3; // rdx\n\n result = (char *)malloc(4LL * a2);\n if ( a2 > 0 )\n {\n v3 = 0LL;\n do\n {\n *(_DWORD *)&result[v3] = *(_DWORD *)(a1 + v3);\n v3 += 4LL;\n }\n while ( 4LL * a2 != v3 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11A9(long long a1, int a2) {\n char *result;\n long long v3;\n result = (char *)malloc(4LL * a2);\n if (a2 > 0) {\n v3 = 0LL;\n do {\n *(uint32_t *)&result[v3] = *(uint32_t *)(a1 + v3);\n v3 += 4LL;\n } while (4LL * a2 != v3);\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2) {\n char *result;\n long long v3;\n result = (char *)malloc(4LL * a2);\n if (a2 > 0) {\n v3 = 0LL;\n do {\n *(uint32_t *)&result[v3] = *(uint32_t *)(a1 + v3);\n v3 += 4LL;\n } while (4LL * a2 != v3);\n }\n return result;\n}" + }, + { + "index": 791, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int *elements;\n\n int size;\n\n} Tuple;\n\n\n\n", + "func": "Tuple func0(Tuple test_tup) {\n Tuple res;\n int *elements = (int *)malloc(test_tup.size * sizeof(int));\n int count = 0;\n for (int i = 0; i < test_tup.size; i++) {\n elements[count] = test_tup.elements[i];\n count++;\n }\n res.elements = elements;\n res.size = count;\n return res;\n}", + "test": "int main() {\n\n Tuple test_tup1 = {(int[]){1, 5, 7, 10}, 4};\n\n Tuple test_tup2 = {(int[]){2, 6, 8, 11}, 4};\n\n Tuple test_tup3 = {(int[]){3, 7, 9, 12}, 4};\n\n\n\n Tuple result1 = func0(test_tup1);\n\n Tuple result2 = func0(test_tup2);\n\n Tuple result3 = func0(test_tup3);\n\n\n\n assert(result1.size == 4 && result1.elements[0] == 1 && result1.elements[1] == 5 && result1.elements[2] == 7 && result1.elements[3] == 10);\n\n assert(result2.size == 4 && result2.elements[0] == 2 && result2.elements[1] == 6 && result2.elements[2] == 8 && result2.elements[3] == 11);\n\n assert(result3.size == 4 && result3.elements[0] == 3 && result3.elements[1] == 7 && result3.elements[2] == 9 && result3.elements[3] == 12);\n\n\n\n printf(\"All tests passed!\\n\");\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %rsi,%r12\npush %rbp\nmov %rdi,%rbp\nmovslq %esi,%rdi\npush %rbx\nshl $0x2,%rdi\nmov %esi,%ebx\ncallq 10b0 \ntest %r12d,%r12d\njle 13c0 \nlea -0x1(%r12),%esi\nxor %edx,%edx\nnopl 0x0(%rax,%rax,1)\nmov 0x0(%rbp,%rdx,4),%ecx\nmov %ecx,(%rax,%rdx,4)\nmov %rdx,%rcx\nadd $0x1,%rdx\ncmp %rcx,%rsi\njne 13a0 \nmov %ebx,%edx\npop %rbx\npop %rbp\npop %r12\nretq\nnopw 0x0(%rax,%rax,1)\nxor %ebx,%ebx\nmov %ebx,%edx\npop %rbx\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r12\nmov r12d, esi\npush rbp\nmov rbp, rdi\nmovsxd rdi, esi\npush rbx\nshl rdi, 2; size\nmov rbx, rsi\ncall _malloc\nmov rcx, rax\ntest ebx, ebx\njle short loc_13A8\nmov edx, ebx\nmov rsi, rbp; src\nmov rdi, rax; dest\nshl rdx, 2; n\ncall _memcpy\nmov edx, r12d\npop rbx\npop rbp\nmov rcx, rax\npop r12\nmov rax, rcx\nretn\nloc_13A8:\nxor r12d, r12d\npop rbx\nmov rax, rcx\npop rbp\nmov edx, r12d\npop r12\nretn", + "ida_pseudo": "void *__fastcall func0(void *src, int a2)\n{\n void *result; // rax\n\n result = malloc(4LL * a2);\n if ( a2 > 0 )\n return memcpy(result, src, 4LL * (unsigned int)a2);\n return result;\n}", + "ida_strip_asm": "sub_1360:\nendbr64\npush r12\nmov r12d, esi\npush rbp\nmov rbp, rdi\nmovsxd rdi, esi\npush rbx\nshl rdi, 2; size\nmov rbx, rsi\ncall _malloc\nmov rcx, rax\ntest ebx, ebx\njle short loc_13A8\nmov edx, ebx\nmov rsi, rbp; src\nmov rdi, rax; dest\nshl rdx, 2; n\ncall _memcpy\nmov edx, r12d\npop rbx\npop rbp\nmov rcx, rax\npop r12\nmov rax, rcx\nretn\nloc_13A8:\nxor r12d, r12d\npop rbx\nmov rax, rcx\npop rbp\nmov edx, r12d\npop r12\nretn", + "ida_strip_pseudo": "void *__fastcall sub_1360(void *src, int a2)\n{\n void *result; // rax\n\n result = malloc(4LL * a2);\n if ( a2 > 0 )\n return memcpy(result, src, 4LL * (unsigned int)a2);\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1360(void *src, int a2) {\n void *result;\n result = malloc(4LL * a2);\n if (a2 > 0) return memcpy(result, src, 4LL * (unsigned int)a2);\n return result;\n}", + "ida_pseudo_norm": "void *func0(void *src, int a2) {\n void *result;\n result = malloc(4LL * a2);\n if (a2 > 0) return memcpy(result, src, 4LL * (unsigned int)a2);\n return result;\n}" + }, + { + "index": 791, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int *elements;\n\n int size;\n\n} Tuple;\n\n\n\n", + "func": "Tuple func0(Tuple test_tup) {\n Tuple res;\n int *elements = (int *)malloc(test_tup.size * sizeof(int));\n int count = 0;\n for (int i = 0; i < test_tup.size; i++) {\n elements[count] = test_tup.elements[i];\n count++;\n }\n res.elements = elements;\n res.size = count;\n return res;\n}", + "test": "int main() {\n\n Tuple test_tup1 = {(int[]){1, 5, 7, 10}, 4};\n\n Tuple test_tup2 = {(int[]){2, 6, 8, 11}, 4};\n\n Tuple test_tup3 = {(int[]){3, 7, 9, 12}, 4};\n\n\n\n Tuple result1 = func0(test_tup1);\n\n Tuple result2 = func0(test_tup2);\n\n Tuple result3 = func0(test_tup3);\n\n\n\n assert(result1.size == 4 && result1.elements[0] == 1 && result1.elements[1] == 5 && result1.elements[2] == 7 && result1.elements[3] == 10);\n\n assert(result2.size == 4 && result2.elements[0] == 2 && result2.elements[1] == 6 && result2.elements[2] == 8 && result2.elements[3] == 11);\n\n assert(result3.size == 4 && result3.elements[0] == 3 && result3.elements[1] == 7 && result3.elements[2] == 9 && result3.elements[3] == 12);\n\n\n\n printf(\"All tests passed!\\n\");\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %rdi,%r12\nmovslq %esi,%rdi\npush %rbp\nshl $0x2,%rdi\nmov %esi,%ebp\npush %rbx\nmov %rsi,%rbx\ncallq 10d0 \nmov %rax,%r8\ntest %ebx,%ebx\njle 13b0 \nlea -0x1(%rbx),%eax\nmov %r12,%rsi\nmov %r8,%rdi\nlea 0x4(,%rax,4),%rdx\ncallq 10c0 \nmov %ebp,%edx\npop %rbx\npop %rbp\nmov %rax,%r8\npop %r12\nmov %r8,%rax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxor %ebp,%ebp\npop %rbx\nmov %r8,%rax\nmov %ebp,%edx\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r12\nmov r12d, esi\npush rbp\nmov rbp, rdi\nmovsxd rdi, esi\npush rbx\nshl rdi, 2; size\nmov rbx, rsi\ncall _malloc\nmov rcx, rax\ntest ebx, ebx\njle short loc_13A8\nmov edx, ebx\nmov rsi, rbp; src\nmov rdi, rax; dest\nshl rdx, 2; n\ncall _memcpy\nmov edx, r12d\npop rbx\npop rbp\nmov rcx, rax\npop r12\nmov rax, rcx\nretn\nloc_13A8:\nxor r12d, r12d\npop rbx\nmov rax, rcx\npop rbp\nmov edx, r12d\npop r12\nretn", + "ida_pseudo": "void *__fastcall func0(void *src, int a2)\n{\n void *result; // rax\n\n result = malloc(4LL * a2);\n if ( a2 > 0 )\n return memcpy(result, src, 4LL * (unsigned int)a2);\n return result;\n}", + "ida_strip_asm": "sub_1360:\nendbr64\npush r12\nmov r12d, esi\npush rbp\nmov rbp, rdi\nmovsxd rdi, esi\npush rbx\nshl rdi, 2; size\nmov rbx, rsi\ncall _malloc\nmov rcx, rax\ntest ebx, ebx\njle short loc_13A8\nmov edx, ebx\nmov rsi, rbp; src\nmov rdi, rax; dest\nshl rdx, 2; n\ncall _memcpy\nmov edx, r12d\npop rbx\npop rbp\nmov rcx, rax\npop r12\nmov rax, rcx\nretn\nloc_13A8:\nxor r12d, r12d\npop rbx\nmov rax, rcx\npop rbp\nmov edx, r12d\npop r12\nretn", + "ida_strip_pseudo": "void *__fastcall sub_1360(void *src, int a2)\n{\n void *result; // rax\n\n result = malloc(4LL * a2);\n if ( a2 > 0 )\n return memcpy(result, src, 4LL * (unsigned int)a2);\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1360(void *src, int a2) {\n void *result;\n result = malloc(4LL * a2);\n if (a2 > 0) return memcpy(result, src, 4LL * (unsigned int)a2);\n return result;\n}", + "ida_pseudo_norm": "void *func0(void *src, int a2) {\n void *result;\n result = malloc(4LL * a2);\n if (a2 > 0) return memcpy(result, src, 4LL * (unsigned int)a2);\n return result;\n}" + }, + { + "index": 792, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int input_list[][2], int size) { return size; }", + "test": "int main() {\n\n int list1[][2] = {{1, 3}, {5, 7}, {9, 11}, {13, 15}};\n\n int list2[][2] = {{1, 2}, {2, 3}, {4, 5}};\n\n int list3[][2] = {{1, 0}, {2, 0}};\n\n\n\n assert(func0(list1, 4) == 4);\n\n assert(func0(list2, 3) == 3);\n\n assert(func0(list3, 2) == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x8(%rbp)\nmov %esi,-0xc(%rbp)\nmov -0xc(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_8], rdi\nmov [rbp+var_C], esi\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, unsigned int a2)\n{\n return a2;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_8], rdi\nmov [rbp+var_C], esi\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, unsigned int a2)\n{\n return a2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, unsigned int a2) { return a2; }", + "ida_pseudo_norm": "long long func0(long long a1, unsigned int a2) { return a2; }" + }, + { + "index": 793, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int x, int n) {\n int low = 0;\n int high = n - 1;\n int res = -1;\n while (low <= high) {\n int mid = (low + high) / 2;\n if (arr[mid] > x) {\n high = mid - 1;\n } else if (arr[mid] < x) {\n low = mid + 1;\n } else {\n res = mid;\n low = mid + 1;\n }\n }\n return res;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3};\n\n assert(func0(arr1, 1, 3) == 0);\n\n \n\n int arr2[] = {1, 1, 1, 2, 3, 4};\n\n assert(func0(arr2, 1, 6) == 2);\n\n \n\n int arr3[] = {2, 3, 2, 3, 6, 8, 9};\n\n assert(func0(arr3, 3, 7) == 3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmovl $0x0,-0x10(%rbp)\nmov -0x20(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0xc(%rbp)\nmovl $0xffffffff,-0x8(%rbp)\njmp 1203 \nmov -0x10(%rbp),%edx\nmov -0xc(%rbp),%eax\nadd %edx,%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x1c(%rbp)\njge 11ce \nmov -0x4(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0xc(%rbp)\njmp 1203 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x1c(%rbp)\njle 11f4 \nmov -0x4(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x10(%rbp)\njmp 1203 \nmov -0x4(%rbp),%eax\nmov %eax,-0x8(%rbp)\nmov -0x4(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x10(%rbp)\nmov -0x10(%rbp),%eax\ncmp -0xc(%rbp),%eax\njle 1194 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_10], 0\nmov eax, [rbp+var_20]\nsub eax, 1\nmov [rbp+var_C], eax\nmov [rbp+var_8], 0FFFFFFFFh\njmp short loc_1203\nloc_1194:\nmov edx, [rbp+var_10]\nmov eax, [rbp+var_C]\nadd eax, edx\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_1C], eax\njge short loc_11CE\nmov eax, [rbp+var_4]\nsub eax, 1\nmov [rbp+var_C], eax\njmp short loc_1203\nloc_11CE:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_1C], eax\njle short loc_11F4\nmov eax, [rbp+var_4]\nadd eax, 1\nmov [rbp+var_10], eax\njmp short loc_1203\nloc_11F4:\nmov eax, [rbp+var_4]\nmov [rbp+var_8], eax\nmov eax, [rbp+var_4]\nadd eax, 1\nmov [rbp+var_10], eax\nloc_1203:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_C]\njle short loc_1194\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n int v4; // [rsp+10h] [rbp-10h]\n int v5; // [rsp+14h] [rbp-Ch]\n unsigned int v6; // [rsp+18h] [rbp-8h]\n int v7; // [rsp+1Ch] [rbp-4h]\n\n v4 = 0;\n v5 = a3 - 1;\n v6 = -1;\n while ( v4 <= v5 )\n {\n v7 = (v4 + v5) / 2;\n if ( a2 >= *(_DWORD *)(4LL * v7 + a1) )\n {\n if ( a2 <= *(_DWORD *)(4LL * v7 + a1) )\n v6 = (v4 + v5) / 2;\n v4 = v7 + 1;\n }\n else\n {\n v5 = v7 - 1;\n }\n }\n return v6;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_10], 0\nmov eax, [rbp+var_20]\nsub eax, 1\nmov [rbp+var_C], eax\nmov [rbp+var_8], 0FFFFFFFFh\njmp short loc_1203\nloc_1194:\nmov edx, [rbp+var_10]\nmov eax, [rbp+var_C]\nadd eax, edx\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_1C], eax\njge short loc_11CE\nmov eax, [rbp+var_4]\nsub eax, 1\nmov [rbp+var_C], eax\njmp short loc_1203\nloc_11CE:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_1C], eax\njle short loc_11F4\nmov eax, [rbp+var_4]\nadd eax, 1\nmov [rbp+var_10], eax\njmp short loc_1203\nloc_11F4:\nmov eax, [rbp+var_4]\nmov [rbp+var_8], eax\nmov eax, [rbp+var_4]\nadd eax, 1\nmov [rbp+var_10], eax\nloc_1203:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_C]\njle short loc_1194\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n int v4; // [rsp+10h] [rbp-10h]\n int v5; // [rsp+14h] [rbp-Ch]\n unsigned int v6; // [rsp+18h] [rbp-8h]\n int v7; // [rsp+1Ch] [rbp-4h]\n\n v4 = 0;\n v5 = a3 - 1;\n v6 = -1;\n while ( v4 <= v5 )\n {\n v7 = (v4 + v5) / 2;\n if ( a2 >= *(_DWORD *)(4LL * v7 + a1) )\n {\n if ( a2 <= *(_DWORD *)(4LL * v7 + a1) )\n v6 = (v4 + v5) / 2;\n v4 = v7 + 1;\n }\n else\n {\n v5 = v7 - 1;\n }\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n int v4;\n int v5;\n unsigned int v6;\n int v7;\n v4 = 0;\n v5 = a3 - 1;\n v6 = -1;\n while (v4 <= v5) {\n v7 = (v4 + v5) / 2;\n if (a2 >= *(uint32_t *)(4LL * v7 + a1)) {\n if (a2 <= *(uint32_t *)(4LL * v7 + a1)) v6 = (v4 + v5) / 2;\n v4 = v7 + 1;\n } else {\n v5 = v7 - 1;\n }\n }\n return v6;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n int v4;\n int v5;\n unsigned int v6;\n int v7;\n v4 = 0;\n v5 = a3 - 1;\n v6 = -1;\n while (v4 <= v5) {\n v7 = (v4 + v5) / 2;\n if (a2 >= *(uint32_t *)(4LL * v7 + a1)) {\n if (a2 <= *(uint32_t *)(4LL * v7 + a1)) v6 = (v4 + v5) / 2;\n v4 = v7 + 1;\n } else {\n v5 = v7 - 1;\n }\n }\n return v6;\n}" + }, + { + "index": 793, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int x, int n) {\n int low = 0;\n int high = n - 1;\n int res = -1;\n while (low <= high) {\n int mid = (low + high) / 2;\n if (arr[mid] > x) {\n high = mid - 1;\n } else if (arr[mid] < x) {\n low = mid + 1;\n } else {\n res = mid;\n low = mid + 1;\n }\n }\n return res;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3};\n\n assert(func0(arr1, 1, 3) == 0);\n\n \n\n int arr2[] = {1, 1, 1, 2, 3, 4};\n\n assert(func0(arr2, 1, 6) == 2);\n\n \n\n int arr3[] = {2, 3, 2, 3, 6, 8, 9};\n\n assert(func0(arr3, 3, 7) == 3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x1,%edx\njs 11ae \nmov $0xffffffff,%r9d\nmov $0x0,%r8d\njmp 1192 \nlea 0x1(%rax),%r8d\njl 118d \nlea 0x1(%rax),%r8d\nmov %eax,%r9d\ncmp %edx,%r8d\njg 11b4 \nlea (%r8,%rdx,1),%ecx\nmov %ecx,%eax\nshr $0x1f,%eax\nadd %ecx,%eax\nsar %eax\nmovslq %eax,%rcx\nmov (%rdi,%rcx,4),%ecx\ncmp %esi,%ecx\njle 1180 \nlea -0x1(%rax),%edx\njmp 118d \nmov $0xffffffff,%r9d\nmov %r9d,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nsub edx, 1\njs short loc_11AE\nmov r9d, 0FFFFFFFFh\nmov r8d, 0\njmp short loc_1192\nloc_1180:\nlea r8d, [rax+1]\njl short loc_118D\nlea r8d, [rax+1]\nmov r9d, eax\nloc_118D:\ncmp r8d, edx\njg short loc_11B4\nloc_1192:\nlea ecx, [r8+rdx]\nmov eax, ecx\nshr eax, 1Fh\nadd eax, ecx\nsar eax, 1\nmovsxd rcx, eax\nmov ecx, [rdi+rcx*4]\ncmp ecx, esi\njle short loc_1180\nlea edx, [rax-1]\njmp short loc_118D\nloc_11AE:\nmov r9d, 0FFFFFFFFh\nloc_11B4:\nmov eax, r9d\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n int v3; // edx\n unsigned int v4; // r9d\n int v5; // r8d\n int v6; // eax\n int v7; // ecx\n\n v3 = a3 - 1;\n if ( v3 < 0 )\n {\n return (unsigned int)-1;\n }\n else\n {\n v4 = -1;\n v5 = 0;\n do\n {\n v6 = (v5 + v3) / 2;\n v7 = *(_DWORD *)(a1 + 4LL * v6);\n if ( v7 <= a2 )\n {\n v5 = v6 + 1;\n if ( v7 >= a2 )\n {\n v5 = v6 + 1;\n v4 = v6;\n }\n }\n else\n {\n v3 = v6 - 1;\n }\n }\n while ( v5 <= v3 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nsub edx, 1\njs short loc_11AE\nmov r9d, 0FFFFFFFFh\nmov r8d, 0\njmp short loc_1192\nloc_1180:\nlea r8d, [rax+1]\njl short loc_118D\nlea r8d, [rax+1]\nmov r9d, eax\nloc_118D:\ncmp r8d, edx\njg short loc_11B4\nloc_1192:\nlea ecx, [r8+rdx]\nmov eax, ecx\nshr eax, 1Fh\nadd eax, ecx\nsar eax, 1\nmovsxd rcx, eax\nmov ecx, [rdi+rcx*4]\ncmp ecx, esi\njle short loc_1180\nlea edx, [rax-1]\njmp short loc_118D\nloc_11AE:\nmov r9d, 0FFFFFFFFh\nloc_11B4:\nmov eax, r9d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n int v3; // edx\n unsigned int v4; // r9d\n int v5; // r8d\n int v6; // eax\n int v7; // ecx\n\n v3 = a3 - 1;\n if ( v3 < 0 )\n {\n return (unsigned int)-1;\n }\n else\n {\n v4 = -1;\n v5 = 0;\n do\n {\n v6 = (v5 + v3) / 2;\n v7 = *(_DWORD *)(a1 + 4LL * v6);\n if ( v7 <= a2 )\n {\n v5 = v6 + 1;\n if ( v7 >= a2 )\n {\n v5 = v6 + 1;\n v4 = v6;\n }\n }\n else\n {\n v3 = v6 - 1;\n }\n }\n while ( v5 <= v3 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n int v3;\n unsigned int v4;\n int v5;\n int v6;\n int v7;\n v3 = a3 - 1;\n if (v3 < 0) {\n return (unsigned int)-1;\n } else {\n v4 = -1;\n v5 = 0;\n do {\n v6 = (v5 + v3) / 2;\n v7 = *(uint32_t *)(a1 + 4LL * v6);\n if (v7 <= a2) {\n v5 = v6 + 1;\n if (v7 >= a2) {\n v5 = v6 + 1;\n v4 = v6;\n }\n } else {\n v3 = v6 - 1;\n }\n } while (v5 <= v3);\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n int v3;\n unsigned int v4;\n int v5;\n int v6;\n int v7;\n v3 = a3 - 1;\n if (v3 < 0) {\n return (unsigned int)-1;\n } else {\n v4 = -1;\n v5 = 0;\n do {\n v6 = (v5 + v3) / 2;\n v7 = *(uint32_t *)(a1 + 4LL * v6);\n if (v7 <= a2) {\n v5 = v6 + 1;\n if (v7 >= a2) {\n v5 = v6 + 1;\n v4 = v6;\n }\n } else {\n v3 = v6 - 1;\n }\n } while (v5 <= v3);\n }\n return v4;\n}" + }, + { + "index": 793, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int x, int n) {\n int low = 0;\n int high = n - 1;\n int res = -1;\n while (low <= high) {\n int mid = (low + high) / 2;\n if (arr[mid] > x) {\n high = mid - 1;\n } else if (arr[mid] < x) {\n low = mid + 1;\n } else {\n res = mid;\n low = mid + 1;\n }\n }\n return res;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3};\n\n assert(func0(arr1, 1, 3) == 0);\n\n \n\n int arr2[] = {1, 1, 1, 2, 3, 4};\n\n assert(func0(arr2, 1, 6) == 2);\n\n \n\n int arr3[] = {2, 3, 2, 3, 6, 8, 9};\n\n assert(func0(arr3, 3, 7) == 3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov $0xffffffff,%r9d\nsub $0x1,%edx\njs 136b \nxor %ecx,%ecx\njmp 134f \nnopl 0x0(%rax,%rax,1)\nlea -0x1(%rax),%edx\ncmp %ecx,%edx\njl 136b \nlea (%rdx,%rcx,1),%eax\nsar %eax\nmovslq %eax,%r8\nmov (%rdi,%r8,4),%r8d\ncmp %esi,%r8d\njg 1348 \nlea 0x1(%rax),%ecx\ncmovge %eax,%r9d\ncmp %ecx,%edx\njge 134f \nmov %r9d,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov r9d, 0FFFFFFFFh\nsub edx, 1\njs short loc_12E4\nxor r8d, r8d\njmp short loc_12C0\nloc_12B8:\nlea edx, [rax-1]\ncmp r8d, edx\njg short loc_12E4\nloc_12C0:\nlea ecx, [r8+rdx]\nmov eax, ecx\nshr eax, 1Fh\nadd eax, ecx\nsar eax, 1\nmovsxd rcx, eax\nmov ecx, [rdi+rcx*4]\ncmp esi, ecx\njl short loc_12B8\nlea r8d, [rax+1]\ncmovle r9d, eax\ncmp r8d, edx\njle short loc_12C0\nloc_12E4:\nmov eax, r9d\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n unsigned int v3; // r9d\n int v4; // edx\n int v5; // r8d\n int v6; // eax\n int v7; // ecx\n\n v3 = -1;\n v4 = a3 - 1;\n if ( v4 >= 0 )\n {\n v5 = 0;\n do\n {\n while ( 1 )\n {\n v6 = (v5 + v4) / 2;\n v7 = *(_DWORD *)(a1 + 4LL * v6);\n if ( a2 >= v7 )\n break;\n v4 = v6 - 1;\n if ( v5 > v6 - 1 )\n return v3;\n }\n v5 = v6 + 1;\n if ( a2 <= v7 )\n v3 = v6;\n }\n while ( v5 <= v4 );\n }\n return v3;\n}", + "ida_strip_asm": "sub_12A0:\nendbr64\nmov r9d, 0FFFFFFFFh\nsub edx, 1\njs short loc_12E4\nxor r8d, r8d\njmp short loc_12C0\nloc_12B8:\nlea edx, [rax-1]\ncmp r8d, edx\njg short loc_12E4\nloc_12C0:\nlea ecx, [r8+rdx]\nmov eax, ecx\nshr eax, 1Fh\nadd eax, ecx\nsar eax, 1\nmovsxd rcx, eax\nmov ecx, [rdi+rcx*4]\ncmp esi, ecx\njl short loc_12B8\nlea r8d, [rax+1]\ncmovle r9d, eax\ncmp r8d, edx\njle short loc_12C0\nloc_12E4:\nmov eax, r9d\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12A0(__int64 a1, int a2, int a3)\n{\n unsigned int v3; // r9d\n int v4; // edx\n int v5; // r8d\n int v6; // eax\n int v7; // ecx\n\n v3 = -1;\n v4 = a3 - 1;\n if ( v4 >= 0 )\n {\n v5 = 0;\n do\n {\n while ( 1 )\n {\n v6 = (v5 + v4) / 2;\n v7 = *(_DWORD *)(a1 + 4LL * v6);\n if ( a2 >= v7 )\n break;\n v4 = v6 - 1;\n if ( v5 > v6 - 1 )\n return v3;\n }\n v5 = v6 + 1;\n if ( a2 <= v7 )\n v3 = v6;\n }\n while ( v5 <= v4 );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12A0(long long a1, int a2, int a3) {\n unsigned int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n v3 = -1;\n v4 = a3 - 1;\n if (v4 >= 0) {\n v5 = 0;\n do {\n while (1) {\n v6 = (v5 + v4) / 2;\n v7 = *(uint32_t *)(a1 + 4LL * v6);\n if (a2 >= v7) break;\n v4 = v6 - 1;\n if (v5 > v6 - 1) return v3;\n }\n v5 = v6 + 1;\n if (a2 <= v7) v3 = v6;\n } while (v5 <= v4);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n unsigned int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n v3 = -1;\n v4 = a3 - 1;\n if (v4 >= 0) {\n v5 = 0;\n do {\n while (1) {\n v6 = (v5 + v4) / 2;\n v7 = *(uint32_t *)(a1 + 4LL * v6);\n if (a2 >= v7) break;\n v4 = v6 - 1;\n if (v5 > v6 - 1) return v3;\n }\n v5 = v6 + 1;\n if (a2 <= v7) v3 = v6;\n } while (v5 <= v4);\n }\n return v3;\n}" + }, + { + "index": 794, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n regex_t regex;\n int result;\n char* pattern = \"a.*?b$\";\n result = regcomp(®ex, pattern, REG_EXTENDED);\n if (result) {\n fprintf(stderr, \"Could not compile regex\\n\");\n return \"Error\";\n }\n result = regexec(®ex, text, 0, NULL, 0);\n regfree(®ex);\n if (result == 0) {\n return \"Found a match!\";\n } else {\n return \"Not matched!\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"aabbbb\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\"aabAbbbc\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"accddbbjjj\"), \"Not matched!\") == 0);\n\n \n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x70,%rsp\nmov %rdi,-0x68(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0xdd9(%rip),%rax\nmov %rax,-0x58(%rbp)\nmov -0x58(%rbp),%rcx\nlea -0x50(%rbp),%rax\nmov $0x1,%edx\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 10e0 \nmov %eax,-0x5c(%rbp)\ncmpl $0x0,-0x5c(%rbp)\nje 127d \nmov 0x2dc5(%rip),%rax\nmov %rax,%rcx\nmov $0x18,%edx\nmov $0x1,%esi\nlea 0xda0(%rip),%rdi\ncallq 1110 \nlea 0xdad(%rip),%rax\njmp 12c2 \nmov -0x68(%rbp),%rsi\nlea -0x50(%rbp),%rax\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rax,%rdi\ncallq 1100 \nmov %eax,-0x5c(%rbp)\nlea -0x50(%rbp),%rax\nmov %rax,%rdi\ncallq 10b0 \ncmpl $0x0,-0x5c(%rbp)\njne 12bb \nlea 0xd75(%rip),%rax\njmp 12c2 \nlea 0xd7b(%rip),%rax\nmov -0x8(%rbp),%rdx\nxor %fs:0x28,%rdx\nje 12d6 \ncallq 10c0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aAB; \"a.*?b$\"\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+var_5C], eax\ncmp [rbp+var_5C], 0\njz short loc_1280\nmov rax, cs:__bss_start\nmov rcx, rax; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rax, aCouldNotCompil; \"Could not compile regex\\n\"\nmov rdi, rax; ptr\ncall _fwrite\nlea rax, aError; \"Error\"\njmp short loc_12C5\nloc_1280:\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_5C], eax\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\ncmp [rbp+var_5C], 0\njnz short loc_12BE\nlea rax, s2; \"Found a match!\"\njmp short loc_12C5\nloc_12BE:\nlea rax, aNotMatched; \"Not matched!\"\nloc_12C5:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12D9\ncall ___stack_chk_fail\nlocret_12D9:\nleave\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n int v2; // [rsp+14h] [rbp-5Ch]\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n unsigned __int64 v4; // [rsp+68h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"a.*?b$\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n return \"Error\";\n }\n else\n {\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if ( v2 )\n return \"Not matched!\";\n else\n return \"Found a match!\";\n }\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aAB; \"a.*?b$\"\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+var_5C], eax\ncmp [rbp+var_5C], 0\njz short loc_1280\nmov rax, cs:stderr\nmov rcx, rax; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rax, aCouldNotCompil; \"Could not compile regex\\n\"\nmov rdi, rax; ptr\ncall _fwrite\nlea rax, aError; \"Error\"\njmp short loc_12C5\nloc_1280:\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_5C], eax\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\ncmp [rbp+var_5C], 0\njnz short loc_12BE\nlea rax, s2; \"Found a match!\"\njmp short loc_12C5\nloc_12BE:\nlea rax, aNotMatched; \"Not matched!\"\nloc_12C5:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12D9\ncall ___stack_chk_fail\nlocret_12D9:\nleave\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1209(const char *a1)\n{\n int v2; // [rsp+14h] [rbp-5Ch]\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n unsigned __int64 v4; // [rsp+68h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"a.*?b$\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n return \"Error\";\n }\n else\n {\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if ( v2 )\n return \"Not matched!\";\n else\n return \"Found a match!\";\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1209(const char *a1) {\n int v2;\n regex_t preg;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n if (regcomp(&preg, \"a.*?b$\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n return \"Error\";\n } else {\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if (v2)\n return \"Not matched!\";\n else\n return \"Found a match!\";\n }\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n int v2;\n regex_t preg;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n if (regcomp(&preg, \"a.*?b$\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n return \"Error\";\n } else {\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if (v2)\n return \"Not matched!\";\n else\n return \"Found a match!\";\n }\n}" + }, + { + "index": 794, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n regex_t regex;\n int result;\n char* pattern = \"a.*?b$\";\n result = regcomp(®ex, pattern, REG_EXTENDED);\n if (result) {\n fprintf(stderr, \"Could not compile regex\\n\");\n return \"Error\";\n }\n result = regexec(®ex, text, 0, NULL, 0);\n regfree(®ex);\n if (result == 0) {\n return \"Found a match!\";\n } else {\n return \"Not matched!\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"aabbbb\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\"aabAbbbc\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"accddbbjjj\"), \"Not matched!\") == 0);\n\n \n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x58,%rsp\nmov %rdi,%rbx\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nmov $0x1,%edx\nlea 0xe11(%rip),%rsi\ncallq 10d0 \ntest %eax,%eax\njne 1271 \nmov %rsp,%rbp\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rbx,%rsi\nmov %rbp,%rdi\ncallq 10e0 \nmov %eax,%ebx\nmov %rbp,%rdi\ncallq 10a0 \ntest %ebx,%ebx\nlea 0xdbb(%rip),%rax\nlea 0xdc3(%rip),%rdx\ncmovne %rdx,%rax\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 1297 \nadd $0x58,%rsp\npop %rbx\npop %rbp\nretq\nmov 0x2da8(%rip),%rcx\nmov $0x18,%edx\nmov $0x1,%esi\nlea 0xda4(%rip),%rdi\ncallq 10f0 \nlea 0xd6f(%rip),%rax\njmp 125a \ncallq 10b0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+68h+var_20], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"a.*?b$\"\ncall _regcomp\ntest eax, eax\njnz short loc_1291\nmov rbp, rsp\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov ebx, eax\nmov rdi, rbp; preg\ncall _regfree\ntest ebx, ebx\nlea rax, aNotMatched; \"Not matched!\"\nlea rdx, s2; \"Found a match!\"\ncmovz rax, rdx\nloc_127A:\nmov rdx, [rsp+68h+var_20]\nsub rdx, fs:28h\njnz short loc_12B7\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1291:\nmov rcx, cs:__bss_start; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nlea rax, aError; \"Error\"\njmp short loc_127A\nloc_12B7:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // ebx\n const char *result; // rax\n regex_t v3; // [rsp+0h] [rbp-68h] BYREF\n unsigned __int64 v4; // [rsp+48h] [rbp-20h]\n\n v4 = __readfsqword(0x28u);\n if ( regcomp(&v3, \"a.*?b$\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n return \"Error\";\n }\n else\n {\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n regfree(&v3);\n result = \"Not matched!\";\n if ( !v1 )\n return \"Found a match!\";\n }\n return result;\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+68h+var_20], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"a.*?b$\"\ncall _regcomp\ntest eax, eax\njnz short loc_1291\nmov rbp, rsp\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov ebx, eax\nmov rdi, rbp; preg\ncall _regfree\ntest ebx, ebx\nlea rax, aNotMatched; \"Not matched!\"\nlea rdx, s2; \"Found a match!\"\ncmovz rax, rdx\nloc_127A:\nmov rdx, [rsp+68h+var_20]\nsub rdx, fs:28h\njnz short loc_12B7\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1291:\nmov rcx, cs:stderr; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nlea rax, aError; \"Error\"\njmp short loc_127A\nloc_12B7:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_1209(char *string)\n{\n int v1; // ebx\n const char *result; // rax\n regex_t v3; // [rsp+0h] [rbp-68h] BYREF\n unsigned __int64 v4; // [rsp+48h] [rbp-20h]\n\n v4 = __readfsqword(0x28u);\n if ( regcomp(&v3, \"a.*?b$\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n return \"Error\";\n }\n else\n {\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n regfree(&v3);\n result = \"Not matched!\";\n if ( !v1 )\n return \"Found a match!\";\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1209(char *string) {\n int v1;\n const char *result;\n regex_t v3;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n if (regcomp(&v3, \"a.*?b$\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n return \"Error\";\n } else {\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n regfree(&v3);\n result = \"Not matched!\";\n if (!v1) return \"Found a match!\";\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n const char *result;\n regex_t v3;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n if (regcomp(&v3, \"a.*?b$\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n return \"Error\";\n } else {\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n regfree(&v3);\n result = \"Not matched!\";\n if (!v1) return \"Found a match!\";\n }\n return result;\n}" + }, + { + "index": 794, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n regex_t regex;\n int result;\n char* pattern = \"a.*?b$\";\n result = regcomp(®ex, pattern, REG_EXTENDED);\n if (result) {\n fprintf(stderr, \"Could not compile regex\\n\");\n return \"Error\";\n }\n result = regexec(®ex, text, 0, NULL, 0);\n regfree(®ex);\n if (result == 0) {\n return \"Found a match!\";\n } else {\n return \"Not matched!\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"aabbbb\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\"aabAbbbc\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"accddbbjjj\"), \"Not matched!\") == 0);\n\n \n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov $0x1,%edx\nlea 0xd44(%rip),%rsi\npush %rbp\nmov %rdi,%rbp\nsub $0x58,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%r12\nmov %r12,%rdi\ncallq 10d0 \ntest %eax,%eax\njne 1358 \nxor %edx,%edx\nxor %r8d,%r8d\nxor %ecx,%ecx\nmov %rbp,%rsi\nmov %r12,%rdi\ncallq 10e0 \nmov %r12,%rdi\nmov %eax,%ebp\ncallq 10a0 \ntest %ebp,%ebp\nlea 0xcdc(%rip),%rax\nlea 0xce4(%rip),%rdx\ncmovne %rdx,%rax\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 137e \nadd $0x58,%rsp\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax)\nmov 0x2cc1(%rip),%rcx\nmov $0x18,%edx\nmov $0x1,%esi\nlea 0xcbd(%rip),%rdi\ncallq 10f0 \nlea 0xc88(%rip),%rax\njmp 1339 \ncallq 10b0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"a.*?b$\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njnz short loc_1360\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, aNotMatched; \"Not matched!\"\nlea rdx, s2; \"Found a match!\"\ncmovz rax, rdx\nloc_1348:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_1386\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1360:\nmov rcx, cs:__bss_start; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nlea rax, aError; \"Error\"\njmp short loc_1348\nloc_1386:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // ebx\n const char *result; // rax\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n if ( regcomp(&_0, \"a.*?b$\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n return \"Error\";\n }\n else\n {\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if ( !v1 )\n return \"Found a match!\";\n }\n return result;\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"a.*?b$\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njnz short loc_1360\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, aNotMatched; \"Not matched!\"\nlea rdx, s2; \"Found a match!\"\ncmovz rax, rdx\nloc_1348:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_1386\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1360:\nmov rcx, cs:stderr; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nlea rax, aError; \"Error\"\njmp short loc_1348\nloc_1386:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_12E0(char *string)\n{\n int v1; // ebx\n const char *result; // rax\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n if ( regcomp(&_0, \"a.*?b$\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n return \"Error\";\n }\n else\n {\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if ( !v1 )\n return \"Found a match!\";\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_12E0(char *string) {\n int v1;\n const char *result;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n if (regcomp(&_0, \"a.*?b$\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n return \"Error\";\n } else {\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if (!v1) return \"Found a match!\";\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n const char *result;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n if (regcomp(&_0, \"a.*?b$\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n return \"Error\";\n } else {\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if (!v1) return \"Found a match!\";\n }\n return result;\n}" + }, + { + "index": 794, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n regex_t regex;\n int result;\n char* pattern = \"a.*?b$\";\n result = regcomp(®ex, pattern, REG_EXTENDED);\n if (result) {\n fprintf(stderr, \"Could not compile regex\\n\");\n return \"Error\";\n }\n result = regexec(®ex, text, 0, NULL, 0);\n regfree(®ex);\n if (result == 0) {\n return \"Found a match!\";\n } else {\n return \"Not matched!\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"aabbbb\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\"aabAbbbc\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"accddbbjjj\"), \"Not matched!\") == 0);\n\n \n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov $0x1,%edx\nlea 0xd44(%rip),%rsi\npush %rbp\nmov %rdi,%rbp\nsub $0x58,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%r12\nmov %r12,%rdi\ncallq 10d0 \ntest %eax,%eax\njne 1358 \nxor %edx,%edx\nxor %r8d,%r8d\nxor %ecx,%ecx\nmov %rbp,%rsi\nmov %r12,%rdi\ncallq 10e0 \nmov %r12,%rdi\nmov %eax,%ebp\ncallq 10a0 \ntest %ebp,%ebp\nlea 0xcdc(%rip),%rax\nlea 0xce4(%rip),%rdx\ncmovne %rdx,%rax\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 137e \nadd $0x58,%rsp\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax)\nmov 0x2cc1(%rip),%rcx\nmov $0x18,%edx\nmov $0x1,%esi\nlea 0xcbd(%rip),%rdi\ncallq 10f0 \nlea 0xc88(%rip),%rax\njmp 1339 \ncallq 10b0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"a.*?b$\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njnz short loc_1360\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, aNotMatched; \"Not matched!\"\nlea rdx, s2; \"Found a match!\"\ncmovz rax, rdx\nloc_1348:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_1386\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1360:\nmov rcx, cs:__bss_start; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nlea rax, aError; \"Error\"\njmp short loc_1348\nloc_1386:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // ebx\n const char *result; // rax\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n if ( regcomp(&_0, \"a.*?b$\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n return \"Error\";\n }\n else\n {\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if ( !v1 )\n return \"Found a match!\";\n }\n return result;\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"a.*?b$\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njnz short loc_1360\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, aNotMatched; \"Not matched!\"\nlea rdx, s2; \"Found a match!\"\ncmovz rax, rdx\nloc_1348:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_1386\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1360:\nmov rcx, cs:stderr; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nlea rax, aError; \"Error\"\njmp short loc_1348\nloc_1386:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_12E0(char *string)\n{\n int v1; // ebx\n const char *result; // rax\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n if ( regcomp(&_0, \"a.*?b$\", 1) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n return \"Error\";\n }\n else\n {\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if ( !v1 )\n return \"Found a match!\";\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_12E0(char *string) {\n int v1;\n const char *result;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n if (regcomp(&_0, \"a.*?b$\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n return \"Error\";\n } else {\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if (!v1) return \"Found a match!\";\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n const char *result;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n if (regcomp(&_0, \"a.*?b$\", 1)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n return \"Error\";\n } else {\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Not matched!\";\n if (!v1) return \"Found a match!\";\n }\n return result;\n}" + }, + { + "index": 795, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char* name;\n\n double price;\n\n} Item;\n\n\n\nint compare(const void *a, const void *b) {\n\n Item *itemA = (Item *)a;\n\n Item *itemB = (Item *)b;\n\n if (itemA->price > itemB->price) return 1;\n\n if (itemA->price < itemB->price) return -1;\n\n return 0;\n\n}\n\n\n\n", + "func": "Item* func0(Item items[], int totalItems, int n) {\n qsort(items, totalItems, sizeof(Item), compare);\n Item* result = (Item*)malloc(n * sizeof(Item));\n for (int i = 0; i < n; i++) {\n result[i] = items[i];\n }\n return result;\n}", + "test": "int main() {\n\n Item items1[] = {{.name = \"Item-1\", .price = 101.1}, {.name = \"Item-2\", .price = 555.22}};\n\n Item* result1 = func0(items1, 2, 1);\n\n assert(result1[0].price == 101.1);\n\n\n\n Item items2[] = {{.name = \"Item-1\", .price = 101.1}, {.name = \"Item-2\", .price = 555.22}};\n\n Item* result2 = func0(items2, 2, 2);\n\n assert(result2[0].price == 101.1 && result2[1].price == 555.22);\n\n\n\n Item items3[] = {{.name = \"Item-1\", .price = 101.1}, {.name = \"Item-2\", .price = 555.22}, {.name = \"Item-3\", .price = 45.09}, {.name = \"Item-4\", .price = 22.75}};\n\n Item* result3 = func0(items3, 4, 1);\n\n assert(result3[0].price == 22.75);\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmov -0x1c(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x18(%rbp),%rax\nlea -0x8c(%rip),%rcx\nmov $0x10,%edx\nmov %rax,%rdi\ncallq 10a0 \nmov -0x20(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 12b9 \nmov -0xc(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0xc(%rbp),%edx\nmovslq %edx,%rdx\nmov %rdx,%rcx\nshl $0x4,%rcx\nmov -0x8(%rbp),%rdx\nadd %rdx,%rcx\nmov 0x8(%rax),%rdx\nmov (%rax),%rax\nmov %rax,(%rcx)\nmov %rdx,0x8(%rcx)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x20(%rbp),%eax\njl 1280 \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+base], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov eax, [rbp+var_1C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compare\nmov rcx, rdx; compar\nmov edx, 10h; size\nmov rdi, rax; base\ncall _qsort\nmov eax, [rbp+var_20]\ncdqe\nshl rax, 4\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp short loc_12BC\nloc_1283:\nmov eax, [rbp+var_C]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nmov rcx, rdx\nshl rcx, 4\nmov rdx, [rbp+var_8]\nadd rcx, rdx\nmov rdx, [rax+8]\nmov rax, [rax]\nmov [rcx], rax\nmov [rcx+8], rdx\nadd [rbp+var_C], 1\nloc_12BC:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_20]\njl short loc_1283\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(char *a1, int a2, int a3)\n{\n char *v3; // rax\n char *v4; // rcx\n __int64 v5; // rdx\n int i; // [rsp+14h] [rbp-Ch]\n char *v9; // [rsp+18h] [rbp-8h]\n\n qsort(a1, a2, 0x10uLL, compare);\n v9 = (char *)malloc(16LL * a3);\n for ( i = 0; i < a3; ++i )\n {\n v3 = &a1[16 * i];\n v4 = &v9[16 * i];\n v5 = *((_QWORD *)v3 + 1);\n *(_QWORD *)v4 = *(_QWORD *)v3;\n *((_QWORD *)v4 + 1) = v5;\n }\n return v9;\n}", + "ida_strip_asm": "sub_122E:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+base], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov eax, [rbp+var_1C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 10h; size\nmov rdi, rax; base\ncall _qsort\nmov eax, [rbp+var_20]\ncdqe\nshl rax, 4\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp short loc_12BC\nloc_1283:\nmov eax, [rbp+var_C]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nmov rcx, rdx\nshl rcx, 4\nmov rdx, [rbp+var_8]\nadd rcx, rdx\nmov rdx, [rax+8]\nmov rax, [rax]\nmov [rcx], rax\nmov [rcx+8], rdx\nadd [rbp+var_C], 1\nloc_12BC:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_20]\njl short loc_1283\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_122E(char *a1, int a2, int a3)\n{\n char *v3; // rax\n char *v4; // rcx\n __int64 v5; // rdx\n int i; // [rsp+14h] [rbp-Ch]\n char *v9; // [rsp+18h] [rbp-8h]\n\n qsort(a1, a2, 0x10uLL, compar);\n v9 = (char *)malloc(16LL * a3);\n for ( i = 0; i < a3; ++i )\n {\n v3 = &a1[16 * i];\n v4 = &v9[16 * i];\n v5 = *((_QWORD *)v3 + 1);\n *(_QWORD *)v4 = *(_QWORD *)v3;\n *((_QWORD *)v4 + 1) = v5;\n }\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_122E(char *a1, int a2, int a3) {\n char *v3;\n char *v4;\n long long v5;\n int i;\n char *v9;\n qsort(a1, a2, 16uLL, compar);\n v9 = (char *)malloc(16LL * a3);\n for (i = 0; i < a3; ++i) {\n v3 = &a1[16 * i];\n v4 = &v9[16 * i];\n v5 = *((uint64_t *)v3 + 1);\n *(uint64_t *)v4 = *(uint64_t *)v3;\n *((uint64_t *)v4 + 1) = v5;\n }\n return v9;\n}", + "ida_pseudo_norm": "char *func0(char *a1, int a2, int a3) {\n char *v3;\n char *v4;\n long long v5;\n int i;\n char *v9;\n qsort(a1, a2, 16uLL, compare);\n v9 = (char *)malloc(16LL * a3);\n for (i = 0; i < a3; ++i) {\n v3 = &a1[16 * i];\n v4 = &v9[16 * i];\n v5 = *((uint64_t *)v3 + 1);\n *(uint64_t *)v4 = *(uint64_t *)v3;\n *((uint64_t *)v4 + 1) = v5;\n }\n return v9;\n}" + }, + { + "index": 795, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char* name;\n\n double price;\n\n} Item;\n\n\n\nint compare(const void *a, const void *b) {\n\n Item *itemA = (Item *)a;\n\n Item *itemB = (Item *)b;\n\n if (itemA->price > itemB->price) return 1;\n\n if (itemA->price < itemB->price) return -1;\n\n return 0;\n\n}\n\n\n\n", + "func": "Item* func0(Item items[], int totalItems, int n) {\n qsort(items, totalItems, sizeof(Item), compare);\n Item* result = (Item*)malloc(n * sizeof(Item));\n for (int i = 0; i < n; i++) {\n result[i] = items[i];\n }\n return result;\n}", + "test": "int main() {\n\n Item items1[] = {{.name = \"Item-1\", .price = 101.1}, {.name = \"Item-2\", .price = 555.22}};\n\n Item* result1 = func0(items1, 2, 1);\n\n assert(result1[0].price == 101.1);\n\n\n\n Item items2[] = {{.name = \"Item-1\", .price = 101.1}, {.name = \"Item-2\", .price = 555.22}};\n\n Item* result2 = func0(items2, 2, 2);\n\n assert(result2[0].price == 101.1 && result2[1].price == 555.22);\n\n\n\n Item items3[] = {{.name = \"Item-1\", .price = 101.1}, {.name = \"Item-2\", .price = 555.22}, {.name = \"Item-3\", .price = 45.09}, {.name = \"Item-4\", .price = 22.75}};\n\n Item* result3 = func0(items3, 4, 1);\n\n assert(result3[0].price == 22.75);\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbx\nmov %edx,%ebp\nmovslq %esi,%rsi\nlea -0x3f(%rip),%rcx\nmov $0x10,%edx\ncallq 10a0 \nmovslq %ebp,%rdi\nshl $0x4,%rdi\ncallq 10d0 \ntest %ebp,%ebp\njle 1244 \nlea -0x1(%rbp),%ecx\nadd $0x1,%rcx\nshl $0x4,%rcx\nmov $0x0,%edx\nmovdqu (%rbx,%rdx,1),%xmm0\nmovups %xmm0,(%rax,%rdx,1)\nadd $0x10,%rdx\ncmp %rcx,%rdx\njne 1232 \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbp, rdi\nmov r12d, edx\nmovsxd rsi, esi; nmemb\nlea rcx, compare; compar\nmov edx, 10h; size\ncall _qsort\nmovsxd rbx, r12d\nshl rbx, 4\nmov rdi, rbx; size\ncall _malloc\ntest r12d, r12d\njle short loc_123D\nmov edx, 0\nloc_122A:\nmovdqu xmm0, xmmword ptr [rbp+rdx+0]\nmovups xmmword ptr [rax+rdx], xmm0\nadd rdx, 10h\ncmp rbx, rdx\njnz short loc_122A\nloc_123D:\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "char *__fastcall func0(char *a1, int a2, int a3)\n{\n char *result; // rax\n __int64 v5; // rdx\n\n qsort(a1, a2, 0x10uLL, compare);\n result = (char *)malloc(16LL * a3);\n if ( a3 > 0 )\n {\n v5 = 0LL;\n do\n {\n *(__m128i *)&result[v5] = _mm_loadu_si128((const __m128i *)&a1[v5]);\n v5 += 16LL;\n }\n while ( 16LL * a3 != v5 );\n }\n return result;\n}", + "ida_strip_asm": "sub_11EF:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbp, rdi\nmov r12d, edx\nmovsxd rsi, esi; nmemb\nlea rcx, compar; compar\nmov edx, 10h; size\ncall _qsort\nmovsxd rbx, r12d\nshl rbx, 4\nmov rdi, rbx; size\ncall _malloc\ntest r12d, r12d\njle short loc_123D\nmov edx, 0\nloc_122A:\nmovdqu xmm0, xmmword ptr [rbp+rdx+0]\nmovups xmmword ptr [rax+rdx], xmm0\nadd rdx, 10h\ncmp rbx, rdx\njnz short loc_122A\nloc_123D:\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11EF(char *a1, int a2, int a3)\n{\n char *result; // rax\n __int64 v5; // rdx\n\n qsort(a1, a2, 0x10uLL, compar);\n result = (char *)malloc(16LL * a3);\n if ( a3 > 0 )\n {\n v5 = 0LL;\n do\n {\n *(__m128i *)&result[v5] = _mm_loadu_si128((const __m128i *)&a1[v5]);\n v5 += 16LL;\n }\n while ( 16LL * a3 != v5 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11EF(char *a1, int a2, int a3) {\n char *result;\n long long v5;\n qsort(a1, a2, 16uLL, compar);\n result = (char *)malloc(16LL * a3);\n if (a3 > 0) {\n v5 = 0LL;\n do {\n *(__m128i *)&result[v5] = _mm_loadu_si128((const __m128i *)&a1[v5]);\n v5 += 16LL;\n } while (16LL * a3 != v5);\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(char *a1, int a2, int a3) {\n char *result;\n long long v5;\n qsort(a1, a2, 16uLL, compare);\n result = (char *)malloc(16LL * a3);\n if (a3 > 0) {\n v5 = 0LL;\n do {\n *(__m128i *)&result[v5] = _mm_loadu_si128((const __m128i *)&a1[v5]);\n v5 += 16LL;\n } while (16LL * a3 != v5);\n }\n return result;\n}" + }, + { + "index": 795, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char* name;\n\n double price;\n\n} Item;\n\n\n\nint compare(const void *a, const void *b) {\n\n Item *itemA = (Item *)a;\n\n Item *itemB = (Item *)b;\n\n if (itemA->price > itemB->price) return 1;\n\n if (itemA->price < itemB->price) return -1;\n\n return 0;\n\n}\n\n\n\n", + "func": "Item* func0(Item items[], int totalItems, int n) {\n qsort(items, totalItems, sizeof(Item), compare);\n Item* result = (Item*)malloc(n * sizeof(Item));\n for (int i = 0; i < n; i++) {\n result[i] = items[i];\n }\n return result;\n}", + "test": "int main() {\n\n Item items1[] = {{.name = \"Item-1\", .price = 101.1}, {.name = \"Item-2\", .price = 555.22}};\n\n Item* result1 = func0(items1, 2, 1);\n\n assert(result1[0].price == 101.1);\n\n\n\n Item items2[] = {{.name = \"Item-1\", .price = 101.1}, {.name = \"Item-2\", .price = 555.22}};\n\n Item* result2 = func0(items2, 2, 2);\n\n assert(result2[0].price == 101.1 && result2[1].price == 555.22);\n\n\n\n Item items3[] = {{.name = \"Item-1\", .price = 101.1}, {.name = \"Item-2\", .price = 555.22}, {.name = \"Item-3\", .price = 45.09}, {.name = \"Item-4\", .price = 22.75}};\n\n Item* result3 = func0(items3, 4, 1);\n\n assert(result3[0].price == 22.75);\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmovslq %esi,%rsi\nmov %edx,%ebp\nlea -0x41(%rip),%rcx\npush %rbx\nmov $0x10,%edx\nmov %rdi,%rbx\nsub $0x8,%rsp\ncallq 10a0 \nmovslq %ebp,%rdi\nshl $0x4,%rdi\ncallq 10d0 \ntest %ebp,%ebp\njle 1462 \nlea -0x1(%rbp),%ecx\nxor %edx,%edx\nadd $0x1,%rcx\nshl $0x4,%rcx\nmovdqu (%rbx,%rdx,1),%xmm0\nmovups %xmm0,(%rax,%rdx,1)\nadd $0x10,%rdx\ncmp %rcx,%rdx\njne 1450 \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nlea rcx, compare; compar\nmovsxd rsi, esi; nmemb\nmov rbp, rdi\npush rbx\nmov ebx, edx\nmov edx, 10h; size\nsub rsp, 8\ncall _qsort\nmovsxd rdi, ebx\nshl rdi, 4; size\ncall _malloc\nmov rcx, rax\ntest ebx, ebx\njle short loc_147A\nmov edx, ebx\nmov rsi, rbp; src\nmov rdi, rax; dest\nshl rdx, 4; n\ncall _memcpy\nmov rcx, rax\nloc_147A:\nadd rsp, 8\nmov rax, rcx\npop rbx\npop rbp\nretn", + "ida_pseudo": "void *__fastcall func0(void *src, int a2, int a3)\n{\n void *v4; // rax\n void *v5; // rcx\n\n qsort(src, a2, 0x10uLL, compare);\n v4 = malloc(16LL * a3);\n v5 = v4;\n if ( a3 > 0 )\n return memcpy(v4, src, 16LL * (unsigned int)a3);\n return v5;\n}", + "ida_strip_asm": "sub_1430:\nendbr64\npush rbp\nlea rcx, compar; compar\nmovsxd rsi, esi; nmemb\nmov rbp, rdi\npush rbx\nmov ebx, edx\nmov edx, 10h; size\nsub rsp, 8\ncall _qsort\nmovsxd rdi, ebx\nshl rdi, 4; size\ncall _malloc\nmov rcx, rax\ntest ebx, ebx\njle short loc_147A\nmov edx, ebx\nmov rsi, rbp; src\nmov rdi, rax; dest\nshl rdx, 4; n\ncall _memcpy\nmov rcx, rax\nloc_147A:\nadd rsp, 8\nmov rax, rcx\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "void *__fastcall sub_1430(void *src, int a2, int a3)\n{\n void *v4; // rax\n void *v5; // rcx\n\n qsort(src, a2, 0x10uLL, compar);\n v4 = malloc(16LL * a3);\n v5 = v4;\n if ( a3 > 0 )\n return memcpy(v4, src, 16LL * (unsigned int)a3);\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1430(void *src, int a2, int a3) {\n void *v4;\n void *v5;\n qsort(src, a2, 16uLL, compar);\n v4 = malloc(16LL * a3);\n v5 = v4;\n if (a3 > 0) return memcpy(v4, src, 16LL * (unsigned int)a3);\n return v5;\n}", + "ida_pseudo_norm": "void *func0(void *src, int a2, int a3) {\n void *v4;\n void *v5;\n qsort(src, a2, 16uLL, compare);\n v4 = malloc(16LL * a3);\n v5 = v4;\n if (a3 > 0) return memcpy(v4, src, 16LL * (unsigned int)a3);\n return v5;\n}" + }, + { + "index": 795, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char* name;\n\n double price;\n\n} Item;\n\n\n\nint compare(const void *a, const void *b) {\n\n Item *itemA = (Item *)a;\n\n Item *itemB = (Item *)b;\n\n if (itemA->price > itemB->price) return 1;\n\n if (itemA->price < itemB->price) return -1;\n\n return 0;\n\n}\n\n\n\n", + "func": "Item* func0(Item items[], int totalItems, int n) {\n qsort(items, totalItems, sizeof(Item), compare);\n Item* result = (Item*)malloc(n * sizeof(Item));\n for (int i = 0; i < n; i++) {\n result[i] = items[i];\n }\n return result;\n}", + "test": "int main() {\n\n Item items1[] = {{.name = \"Item-1\", .price = 101.1}, {.name = \"Item-2\", .price = 555.22}};\n\n Item* result1 = func0(items1, 2, 1);\n\n assert(result1[0].price == 101.1);\n\n\n\n Item items2[] = {{.name = \"Item-1\", .price = 101.1}, {.name = \"Item-2\", .price = 555.22}};\n\n Item* result2 = func0(items2, 2, 2);\n\n assert(result2[0].price == 101.1 && result2[1].price == 555.22);\n\n\n\n Item items3[] = {{.name = \"Item-1\", .price = 101.1}, {.name = \"Item-2\", .price = 555.22}, {.name = \"Item-3\", .price = 45.09}, {.name = \"Item-4\", .price = 22.75}};\n\n Item* result3 = func0(items3, 4, 1);\n\n assert(result3[0].price == 22.75);\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmovslq %esi,%rsi\nlea -0x3f(%rip),%rcx\nmov %rdi,%rbp\npush %rbx\nmov %edx,%ebx\nmov $0x10,%edx\nsub $0x8,%rsp\ncallq 10b0 \nmovslq %ebx,%rdi\nshl $0x4,%rdi\ncallq 10f0 \nmov %rax,%r8\ntest %ebx,%ebx\njle 146f \nlea -0x1(%rbx),%edx\nmov %rbp,%rsi\nmov %rax,%rdi\nadd $0x1,%rdx\nshl $0x4,%rdx\ncallq 10e0 \nmov %rax,%r8\nadd $0x8,%rsp\nmov %r8,%rax\npop %rbx\npop %rbp\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nlea rcx, compare; compar\nmovsxd rsi, esi; nmemb\nmov rbp, rdi\npush rbx\nmov ebx, edx\nmov edx, 10h; size\nsub rsp, 8\ncall _qsort\nmovsxd rdi, ebx\nshl rdi, 4; size\ncall _malloc\nmov rcx, rax\ntest ebx, ebx\njle short loc_146A\nmov edx, ebx\nmov rsi, rbp; src\nmov rdi, rax; dest\nshl rdx, 4; n\ncall _memcpy\nmov rcx, rax\nloc_146A:\nadd rsp, 8\nmov rax, rcx\npop rbx\npop rbp\nretn", + "ida_pseudo": "void *__fastcall func0(void *src, int a2, int a3)\n{\n void *v4; // rax\n void *v5; // rcx\n\n qsort(src, a2, 0x10uLL, compare);\n v4 = malloc(16LL * a3);\n v5 = v4;\n if ( a3 > 0 )\n return memcpy(v4, src, 16LL * (unsigned int)a3);\n return v5;\n}", + "ida_strip_asm": "sub_1420:\nendbr64\npush rbp\nlea rcx, compar; compar\nmovsxd rsi, esi; nmemb\nmov rbp, rdi\npush rbx\nmov ebx, edx\nmov edx, 10h; size\nsub rsp, 8\ncall _qsort\nmovsxd rdi, ebx\nshl rdi, 4; size\ncall _malloc\nmov rcx, rax\ntest ebx, ebx\njle short loc_146A\nmov edx, ebx\nmov rsi, rbp; src\nmov rdi, rax; dest\nshl rdx, 4; n\ncall _memcpy\nmov rcx, rax\nloc_146A:\nadd rsp, 8\nmov rax, rcx\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "void *__fastcall sub_1420(void *src, int a2, int a3)\n{\n void *v4; // rax\n void *v5; // rcx\n\n qsort(src, a2, 0x10uLL, compar);\n v4 = malloc(16LL * a3);\n v5 = v4;\n if ( a3 > 0 )\n return memcpy(v4, src, 16LL * (unsigned int)a3);\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1420(void *src, int a2, int a3) {\n void *v4;\n void *v5;\n qsort(src, a2, 16uLL, compar);\n v4 = malloc(16LL * a3);\n v5 = v4;\n if (a3 > 0) return memcpy(v4, src, 16LL * (unsigned int)a3);\n return v5;\n}", + "ida_pseudo_norm": "void *func0(void *src, int a2, int a3) {\n void *v4;\n void *v5;\n qsort(src, a2, 16uLL, compare);\n v4 = malloc(16LL * a3);\n v5 = v4;\n if (a3 > 0) return memcpy(v4, src, 16LL * (unsigned int)a3);\n return v5;\n}" + }, + { + "index": 796, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int dict[], int size) {\n int sum = 0;\n for (int i = 0; i < size; i++) {\n sum += dict[i];\n }\n return sum;\n}", + "test": "int main() {\n\n int dict1[] = {100, 200, 300};\n\n int dict2[] = {25, 18, 45};\n\n int dict3[] = {36, 39, 49};\n\n\n\n assert(func0(dict1, 3) == 600);\n\n assert(func0(dict2, 3) == 88);\n\n assert(func0(dict3, 3) == 124);\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11c5 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nadd %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11a8 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11C5\nloc_11A8:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_11C5:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11A8\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n v3 += *(_DWORD *)(4LL * i + a1);\n return v3;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11C5\nloc_11A8:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_11C5:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11A8\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n v3 += *(_DWORD *)(4LL * i + a1);\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) v3 += *(uint32_t *)(4LL * i + a1);\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) v3 += *(uint32_t *)(4LL * i + a1);\n return v3;\n}" + }, + { + "index": 796, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int dict[], int size) {\n int sum = 0;\n for (int i = 0; i < size; i++) {\n sum += dict[i];\n }\n return sum;\n}", + "test": "int main() {\n\n int dict1[] = {100, 200, 300};\n\n int dict2[] = {25, 18, 45};\n\n int dict3[] = {36, 39, 49};\n\n\n\n assert(func0(dict1, 3) == 600);\n\n assert(func0(dict2, 3) == 88);\n\n assert(func0(dict3, 3) == 124);\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11af \nmov %rdi,%rax\nlea -0x1(%rsi),%edx\nlea 0x4(%rdi,%rdx,4),%rcx\nmov $0x0,%edx\nadd (%rax),%edx\nadd $0x4,%rax\ncmp %rcx,%rax\njne 11a1 \nmov %edx,%eax\nretq\nmov $0x0,%edx\njmp 11ac \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11AE\nmov rax, rdi\nmovsxd rsi, esi\nlea rcx, [rdi+rsi*4]\nmov edx, 0\nloc_11A0:\nadd edx, [rax]\nadd rax, 4\ncmp rax, rcx\njnz short loc_11A0\nloc_11AB:\nmov eax, edx\nretn\nloc_11AE:\nmov edx, 0\njmp short loc_11AB", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n unsigned int v3; // edx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = 0;\n do\n v3 += *v2++;\n while ( v2 != &a1[a2] );\n }\n return v3;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\ntest esi, esi\njle short loc_11AE\nmov rax, rdi\nmovsxd rsi, esi\nlea rcx, [rdi+rsi*4]\nmov edx, 0\nloc_11A0:\nadd edx, [rax]\nadd rax, 4\ncmp rax, rcx\njnz short loc_11A0\nloc_11AB:\nmov eax, edx\nretn\nloc_11AE:\nmov edx, 0\njmp short loc_11AB", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n unsigned int v3; // edx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = 0;\n do\n v3 += *v2++;\n while ( v2 != &a1[a2] );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(uint32_t *a1, int a2) {\n uint32_t *v2;\n unsigned int v3;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = 0;\n do\n v3 += *v2++;\n while (v2 != &a1[a2]);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n unsigned int v3;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = 0;\n do\n v3 += *v2++;\n while (v2 != &a1[a2]);\n }\n return v3;\n}" + }, + { + "index": 797, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\nint sum_Odd(int n) {\n\n int terms = (n + 1) / 2;\n\n int sum1 = terms * terms;\n\n return sum1;\n\n}\n\n\n\n", + "func": "int func0(int l, int r) { return sum_Odd(r) - sum_Odd(l - 1); }", + "test": "int main() {\n\n assert(func0(2, 5) == 8);\n\n assert(func0(5, 7) == 12);\n\n assert(func0(7, 13) == 40);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x8,%rsp\nmov %edi,-0xc(%rbp)\nmov %esi,-0x10(%rbp)\nmov -0x10(%rbp),%eax\nmov %eax,%edi\ncallq 1149 \nmov %eax,%ebx\nmov -0xc(%rbp),%eax\nsub $0x1,%eax\nmov %eax,%edi\ncallq 1149 \nsub %eax,%ebx\nmov %ebx,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 8\nmov [rbp+var_C], edi\nmov [rbp+var_10], esi\nmov eax, [rbp+var_10]\nmov edi, eax\ncall sum_Odd\nmov ebx, eax\nmov eax, [rbp+var_C]\nsub eax, 1\nmov edi, eax\ncall sum_Odd\nmov edx, ebx\nsub edx, eax\nmov eax, edx\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, unsigned int a2)\n{\n int v2; // ebx\n\n v2 = sum_Odd(a2);\n return v2 - (unsigned int)sum_Odd((unsigned int)(a1 - 1));\n}", + "ida_strip_asm": "sub_1174:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 8\nmov [rbp+var_C], edi\nmov [rbp+var_10], esi\nmov eax, [rbp+var_10]\nmov edi, eax\ncall sub_1149\nmov ebx, eax\nmov eax, [rbp+var_C]\nsub eax, 1\nmov edi, eax\ncall sub_1149\nmov edx, ebx\nsub edx, eax\nmov eax, edx\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1174(int a1, unsigned int a2)\n{\n int v2; // ebx\n\n v2 = sub_1149(a2);\n return v2 - (unsigned int)sub_1149((unsigned int)(a1 - 1));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1174(int a1, unsigned int a2) {\n int v2;\n v2 = sub_1149(a2);\n return v2 - (unsigned int)sub_1149((unsigned int)(a1 - 1));\n}", + "ida_pseudo_norm": "long long func0(int a1, unsigned int a2) {\n int v2;\n v2 = sum_Odd(a2);\n return v2 - (unsigned int)sum_Odd((unsigned int)(a1 - 1));\n}" + }, + { + "index": 798, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int sum = 0;\n for (int i = 0; i < n; i++) {\n sum += arr[i];\n }\n return sum;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3};\n\n assert(func0(arr1, 3) == 6);\n\n \n\n int arr2[] = {15, 12, 13, 10};\n\n assert(func0(arr2, 4) == 50);\n\n \n\n int arr3[] = {0, 1, 2};\n\n assert(func0(arr3, 3) == 3);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11a5 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nadd %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1188 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11A5\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_11A5:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n v3 += *(_DWORD *)(4LL * i + a1);\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11A5\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_11A5:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n v3 += *(_DWORD *)(4LL * i + a1);\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) v3 += *(uint32_t *)(4LL * i + a1);\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) v3 += *(uint32_t *)(4LL * i + a1);\n return v3;\n}" + }, + { + "index": 798, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int sum = 0;\n for (int i = 0; i < n; i++) {\n sum += arr[i];\n }\n return sum;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3};\n\n assert(func0(arr1, 3) == 6);\n\n \n\n int arr2[] = {15, 12, 13, 10};\n\n assert(func0(arr2, 4) == 50);\n\n \n\n int arr3[] = {0, 1, 2};\n\n assert(func0(arr3, 3) == 3);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 118f \nmov %rdi,%rax\nlea -0x1(%rsi),%edx\nlea 0x4(%rdi,%rdx,4),%rcx\nmov $0x0,%edx\nadd (%rax),%edx\nadd $0x4,%rax\ncmp %rcx,%rax\njne 1181 \nmov %edx,%eax\nretq\nmov $0x0,%edx\njmp 118c \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_118E\nmov rax, rdi\nmovsxd rsi, esi\nlea rcx, [rdi+rsi*4]\nmov edx, 0\nloc_1180:\nadd edx, [rax]\nadd rax, 4\ncmp rax, rcx\njnz short loc_1180\nloc_118B:\nmov eax, edx\nretn\nloc_118E:\nmov edx, 0\njmp short loc_118B", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n unsigned int v3; // edx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = 0;\n do\n v3 += *v2++;\n while ( v2 != &a1[a2] );\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_118E\nmov rax, rdi\nmovsxd rsi, esi\nlea rcx, [rdi+rsi*4]\nmov edx, 0\nloc_1180:\nadd edx, [rax]\nadd rax, 4\ncmp rax, rcx\njnz short loc_1180\nloc_118B:\nmov eax, edx\nretn\nloc_118E:\nmov edx, 0\njmp short loc_118B", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n unsigned int v3; // edx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = 0;\n do\n v3 += *v2++;\n while ( v2 != &a1[a2] );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2) {\n uint32_t *v2;\n unsigned int v3;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = 0;\n do\n v3 += *v2++;\n while (v2 != &a1[a2]);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n unsigned int v3;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = 0;\n do\n v3 += *v2++;\n while (v2 != &a1[a2]);\n }\n return v3;\n}" + }, + { + "index": 799, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n#define INT_BITS 32\n\n\n\n", + "func": "int func0(int n, int d) { return (n << d) | (n >> (INT_BITS - d)); }", + "test": "int main() {\n\n assert(func0(16, 2) == 64);\n\n assert(func0(10, 2) == 40);\n\n assert(func0(99, 3) == 792);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov %esi,-0x8(%rbp)\nmov -0x8(%rbp),%eax\nmov -0x4(%rbp),%edx\nmov %edx,%esi\nmov %eax,%ecx\nshl %cl,%esi\nmov $0x20,%eax\nsub -0x8(%rbp),%eax\nmov -0x4(%rbp),%edx\nmov %eax,%ecx\nsar %cl,%edx\nmov %edx,%eax\nor %esi,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov eax, [rbp+var_8]\nmov edx, [rbp+var_4]\nmov esi, edx\nmov ecx, eax\nshl esi, cl\nmov eax, 20h ; ' '\nsub eax, [rbp+var_8]\nmov edx, [rbp+var_4]\nmov ecx, eax\nsar edx, cl\nmov eax, edx\nor eax, esi\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, char a2)\n{\n return (a1 << a2) | (unsigned int)(a1 >> (32 - a2));\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov eax, [rbp+var_8]\nmov edx, [rbp+var_4]\nmov esi, edx\nmov ecx, eax\nshl esi, cl\nmov eax, 20h ; ' '\nsub eax, [rbp+var_8]\nmov edx, [rbp+var_4]\nmov ecx, eax\nsar edx, cl\nmov eax, edx\nor eax, esi\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, char a2)\n{\n return (a1 << a2) | (unsigned int)(a1 >> (32 - a2));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, char a2) {\n return (a1 << a2) | (unsigned int)(a1 >> (32 - a2));\n}", + "ida_pseudo_norm": "long long func0(int a1, char a2) {\n return (a1 << a2) | (unsigned int)(a1 >> (32 - a2));\n}" + }, + { + "index": 800, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(char* text, char* result) {\n int i = 0, j = 0;\n while (text[i]) {\n if (!isspace((unsigned char)text[i])) {\n result[j++] = text[i];\n }\n i++;\n }\n result[j] = '\\0';\n}", + "test": "int main() {\n\n char result[100];\n\n\n\n func0(\"python program\", result);\n\n assert(strcmp(result, \"pythonprogram\") == 0);\n\n\n\n func0(\"python programming language\", result);\n\n assert(strcmp(result, \"pythonprogramminglanguage\") == 0);\n\n\n\n func0(\"python program\", result);\n\n assert(strcmp(result, \"pythonprogram\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 1227 \ncallq 10b0 <__ctype_b_loc@plt>\nmov (%rax),%rax\nmov -0x8(%rbp),%edx\nmovslq %edx,%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rdx),%edx\nmovzbl %dl,%edx\nadd %rdx,%rdx\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x2000,%eax\ntest %eax,%eax\njne 1223 \nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x4(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x4(%rbp)\nmovslq %eax,%rdx\nmov -0x20(%rbp),%rax\nadd %rax,%rdx\nmovzbl (%rcx),%eax\nmov %al,(%rdx)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 11cd \nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmovb $0x0,(%rax)\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_1227\nloc_11CD:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_8]\nmovsxd rcx, edx\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovzx edx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 2000h\ntest eax, eax\njnz short loc_1223\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_4]\nlea edx, [rax+1]\nmov [rbp+var_4], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_20]\nadd rdx, rax\nmovzx eax, byte ptr [rcx]\nmov [rdx], al\nloc_1223:\nadd [rbp+var_8], 1\nloc_1227:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_11CD\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov byte ptr [rax], 0\nnop\nleave\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(__int64 a1, __int64 a2)\n{\n int v2; // eax\n _BYTE *result; // rax\n int v4; // [rsp+18h] [rbp-8h]\n int v5; // [rsp+1Ch] [rbp-4h]\n\n v4 = 0;\n v5 = 0;\n while ( *(_BYTE *)(v4 + a1) )\n {\n if ( ((*__ctype_b_loc())[*(unsigned __int8 *)(v4 + a1)] & 0x2000) == 0 )\n {\n v2 = v5++;\n *(_BYTE *)(a2 + v2) = *(_BYTE *)(v4 + a1);\n }\n ++v4;\n }\n result = (_BYTE *)(v5 + a2);\n *result = 0;\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_1227\nloc_11CD:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_8]\nmovsxd rcx, edx\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovzx edx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 2000h\ntest eax, eax\njnz short loc_1223\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_4]\nlea edx, [rax+1]\nmov [rbp+var_4], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_20]\nadd rdx, rax\nmovzx eax, byte ptr [rcx]\nmov [rdx], al\nloc_1223:\nadd [rbp+var_8], 1\nloc_1227:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_11CD\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov byte ptr [rax], 0\nnop\nleave\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_11A9(__int64 a1, __int64 a2)\n{\n int v2; // eax\n _BYTE *result; // rax\n int v4; // [rsp+18h] [rbp-8h]\n int v5; // [rsp+1Ch] [rbp-4h]\n\n v4 = 0;\n v5 = 0;\n while ( *(_BYTE *)(v4 + a1) )\n {\n if ( ((*__ctype_b_loc())[*(unsigned __int8 *)(v4 + a1)] & 0x2000) == 0 )\n {\n v2 = v5++;\n *(_BYTE *)(a2 + v2) = *(_BYTE *)(v4 + a1);\n }\n ++v4;\n }\n result = (_BYTE *)(v5 + a2);\n *result = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_11A9(long long a1, long long a2) {\n int v2;\n uint8_t *result;\n int v4;\n int v5;\n v4 = 0;\n v5 = 0;\n while (*(uint8_t *)(v4 + a1)) {\n if (((*__ctype_b_loc())[*(unsigned char *)(v4 + a1)] & 8192) == 0) {\n v2 = v5++;\n *(uint8_t *)(a2 + v2) = *(uint8_t *)(v4 + a1);\n }\n ++v4;\n }\n result = (uint8_t *)(v5 + a2);\n *result = 0;\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(long long a1, long long a2) {\n int v2;\n uint8_t *result;\n int v4;\n int v5;\n v4 = 0;\n v5 = 0;\n while (*(uint8_t *)(v4 + a1)) {\n if (((*__ctype_b_loc())[*(unsigned char *)(v4 + a1)] & 8192) == 0) {\n v2 = v5++;\n *(uint8_t *)(a2 + v2) = *(uint8_t *)(v4 + a1);\n }\n ++v4;\n }\n result = (uint8_t *)(v5 + a2);\n *result = 0;\n return result;\n}" + }, + { + "index": 800, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(char* text, char* result) {\n int i = 0, j = 0;\n while (text[i]) {\n if (!isspace((unsigned char)text[i])) {\n result[j++] = text[i];\n }\n i++;\n }\n result[j] = '\\0';\n}", + "test": "int main() {\n\n char result[100];\n\n\n\n func0(\"python program\", result);\n\n assert(strcmp(result, \"pythonprogram\") == 0);\n\n\n\n func0(\"python programming language\", result);\n\n assert(strcmp(result, \"pythonprogramminglanguage\") == 0);\n\n\n\n func0(\"python program\", result);\n\n assert(strcmp(result, \"pythonprogram\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmov %rsi,%r12\nmovzbl (%rdi),%ebx\ntest %bl,%bl\nje 11d3 \nmov %rdi,%rbp\ncallq 1090 <__ctype_b_loc@plt>\nlea 0x1(%rbp),%rdi\nmov $0x0,%esi\njmp 11ba \nadd $0x1,%rdi\nmovzbl -0x1(%rdi),%ebx\ntest %bl,%bl\nje 11d8 \nmovzbl %bl,%edx\nmov (%rax),%rcx\ntestb $0x20,0x1(%rcx,%rdx,2)\njne 11ae \nmovslq %esi,%rdx\nmov %bl,(%r12,%rdx,1)\nlea 0x1(%rsi),%esi\njmp 11ae \nmov $0x0,%esi\nmovslq %esi,%rsi\nmovb $0x0,(%r12,%rsi,1)\npop %rbx\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov r12, rsi\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_11F3\nmov rbp, rdi\ncall ___ctype_b_loc\nlea rdi, [rbp+1]\nmov esi, 0\njmp short loc_11DA\nloc_11CE:\nadd rdi, 1\nmovzx ebx, byte ptr [rdi-1]\ntest bl, bl\njz short loc_11F8\nloc_11DA:\nmovzx edx, bl\nmov rcx, [rax]\ntest byte ptr [rcx+rdx*2+1], 20h\njnz short loc_11CE\nmovsxd rdx, esi\nmov [r12+rdx], bl\nlea esi, [rsi+1]\njmp short loc_11CE\nloc_11F3:\nmov esi, 0\nloc_11F8:\nmovsxd rsi, esi\nmov byte ptr [r12+rsi], 0\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "void __fastcall func0(unsigned __int8 *a1, __int64 a2)\n{\n unsigned __int8 v3; // bl\n const unsigned __int16 **v4; // rax\n unsigned __int8 *v5; // rdi\n int v6; // esi\n\n v3 = *a1;\n if ( *a1 )\n {\n v4 = __ctype_b_loc();\n v5 = a1 + 1;\n v6 = 0;\n do\n {\n if ( ((*v4)[v3] & 0x2000) == 0 )\n *(_BYTE *)(a2 + v6++) = v3;\n v3 = *v5++;\n }\n while ( v3 );\n }\n else\n {\n v6 = 0;\n }\n *(_BYTE *)(a2 + v6) = 0;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r12\npush rbp\npush rbx\nmov r12, rsi\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_11F3\nmov rbp, rdi\ncall ___ctype_b_loc\nlea rdi, [rbp+1]\nmov esi, 0\njmp short loc_11DA\nloc_11CE:\nadd rdi, 1\nmovzx ebx, byte ptr [rdi-1]\ntest bl, bl\njz short loc_11F8\nloc_11DA:\nmovzx edx, bl\nmov rcx, [rax]\ntest byte ptr [rcx+rdx*2+1], 20h\njnz short loc_11CE\nmovsxd rdx, esi\nmov [r12+rdx], bl\nlea esi, [rsi+1]\njmp short loc_11CE\nloc_11F3:\nmov esi, 0\nloc_11F8:\nmovsxd rsi, esi\nmov byte ptr [r12+rsi], 0\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "void __fastcall sub_11A9(unsigned __int8 *a1, __int64 a2)\n{\n unsigned __int8 v3; // bl\n const unsigned __int16 **v4; // rax\n unsigned __int8 *v5; // rdi\n int v6; // esi\n\n v3 = *a1;\n if ( *a1 )\n {\n v4 = __ctype_b_loc();\n v5 = a1 + 1;\n v6 = 0;\n do\n {\n if ( ((*v4)[v3] & 0x2000) == 0 )\n *(_BYTE *)(a2 + v6++) = v3;\n v3 = *v5++;\n }\n while ( v3 );\n }\n else\n {\n v6 = 0;\n }\n *(_BYTE *)(a2 + v6) = 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_11A9(unsigned char *a1, long long a2) {\n unsigned char v3;\n const unsigned short **v4;\n unsigned char *v5;\n int v6;\n v3 = *a1;\n if (*a1) {\n v4 = __ctype_b_loc();\n v5 = a1 + 1;\n v6 = 0;\n do {\n if (((*v4)[v3] & 8192) == 0) *(uint8_t *)(a2 + v6++) = v3;\n v3 = *v5++;\n } while (v3);\n } else {\n v6 = 0;\n }\n *(uint8_t *)(a2 + v6) = 0;\n}", + "ida_pseudo_norm": "void func0(unsigned char *a1, long long a2) {\n unsigned char v3;\n const unsigned short **v4;\n unsigned char *v5;\n int v6;\n v3 = *a1;\n if (*a1) {\n v4 = __ctype_b_loc();\n v5 = a1 + 1;\n v6 = 0;\n do {\n if (((*v4)[v3] & 8192) == 0) *(uint8_t *)(a2 + v6++) = v3;\n v3 = *v5++;\n } while (v3);\n } else {\n v6 = 0;\n }\n *(uint8_t *)(a2 + v6) = 0;\n}" + }, + { + "index": 800, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(char* text, char* result) {\n int i = 0, j = 0;\n while (text[i]) {\n if (!isspace((unsigned char)text[i])) {\n result[j++] = text[i];\n }\n i++;\n }\n result[j] = '\\0';\n}", + "test": "int main() {\n\n char result[100];\n\n\n\n func0(\"python program\", result);\n\n assert(strcmp(result, \"pythonprogram\") == 0);\n\n\n\n func0(\"python programming language\", result);\n\n assert(strcmp(result, \"pythonprogramminglanguage\") == 0);\n\n\n\n func0(\"python program\", result);\n\n assert(strcmp(result, \"pythonprogram\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %rsi,%r12\npush %rbp\npush %rbx\nmovzbl (%rdi),%ebx\ntest %bl,%bl\nje 1330 \nmov %rdi,%rbp\ncallq 1090 <__ctype_b_loc@plt>\nlea 0x1(%rbp),%rdi\nxor %esi,%esi\nxor %r8d,%r8d\nnopl 0x0(%rax,%rax,1)\nmov (%rax),%r9\nmovzbl %bl,%edx\nlea (%r12,%r8,1),%rcx\ntestb $0x20,0x1(%r9,%rdx,2)\njne 1316 \nadd $0x1,%esi\nmov %bl,(%rcx)\nmovslq %esi,%r8\nlea (%r12,%r8,1),%rcx\nmovzbl (%rdi),%ebx\nadd $0x1,%rdi\ntest %bl,%bl\njne 12f8 \nmovb $0x0,(%rcx)\npop %rbx\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax)\nmov %rsi,%rcx\nmovb $0x0,(%rcx)\npop %rbx\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r12\nmov r12, rsi\npush rbp\npush rbx\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_1321\nmov rbp, rdi\ncall ___ctype_b_loc\nlea rdi, [rbp+1]\nxor r8d, r8d\nnop dword ptr [rax+00000000h]\nloc_12F8:\nmov rcx, [rax]\nmovzx edx, bl\ntest byte ptr [rcx+rdx*2+1], 20h\njnz short loc_1310\nmovsxd rdx, r8d\nadd r8d, 1\nmov [r12+rdx], bl\nloc_1310:\nmovzx ebx, byte ptr [rdi]\nadd rdi, 1\ntest bl, bl\njnz short loc_12F8\nmovsxd r8, r8d\nadd r12, r8\nloc_1321:\nmov byte ptr [r12], 0\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "void __fastcall func0(unsigned __int8 *a1, _BYTE *a2)\n{\n _BYTE *v2; // r12\n unsigned __int8 v3; // bl\n const unsigned __int16 **v4; // rax\n unsigned __int8 *v5; // rdi\n int v6; // r8d\n __int64 v7; // rdx\n\n v2 = a2;\n v3 = *a1;\n if ( *a1 )\n {\n v4 = __ctype_b_loc();\n v5 = a1 + 1;\n v6 = 0;\n do\n {\n if ( ((*v4)[v3] & 0x2000) == 0 )\n {\n v7 = v6++;\n a2[v7] = v3;\n }\n v3 = *v5++;\n }\n while ( v3 );\n v2 = &a2[v6];\n }\n *v2 = 0;\n}", + "ida_strip_asm": "sub_12D0:\nendbr64\npush r12\nmov r12, rsi\npush rbp\npush rbx\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_1321\nmov rbp, rdi\ncall ___ctype_b_loc\nlea rdi, [rbp+1]\nxor r8d, r8d\nnop dword ptr [rax+00000000h]\nloc_12F8:\nmov rcx, [rax]\nmovzx edx, bl\ntest byte ptr [rcx+rdx*2+1], 20h\njnz short loc_1310\nmovsxd rdx, r8d\nadd r8d, 1\nmov [r12+rdx], bl\nloc_1310:\nmovzx ebx, byte ptr [rdi]\nadd rdi, 1\ntest bl, bl\njnz short loc_12F8\nmovsxd r8, r8d\nadd r12, r8\nloc_1321:\nmov byte ptr [r12], 0\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "void __fastcall sub_12D0(unsigned __int8 *a1, _BYTE *a2)\n{\n _BYTE *v2; // r12\n unsigned __int8 v3; // bl\n const unsigned __int16 **v4; // rax\n unsigned __int8 *v5; // rdi\n int v6; // r8d\n __int64 v7; // rdx\n\n v2 = a2;\n v3 = *a1;\n if ( *a1 )\n {\n v4 = __ctype_b_loc();\n v5 = a1 + 1;\n v6 = 0;\n do\n {\n if ( ((*v4)[v3] & 0x2000) == 0 )\n {\n v7 = v6++;\n a2[v7] = v3;\n }\n v3 = *v5++;\n }\n while ( v3 );\n v2 = &a2[v6];\n }\n *v2 = 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_12D0(unsigned char *a1, uint8_t *a2) {\n uint8_t *v2;\n unsigned char v3;\n const unsigned short **v4;\n unsigned char *v5;\n int v6;\n long long v7;\n v2 = a2;\n v3 = *a1;\n if (*a1) {\n v4 = __ctype_b_loc();\n v5 = a1 + 1;\n v6 = 0;\n do {\n if (((*v4)[v3] & 8192) == 0) {\n v7 = v6++;\n a2[v7] = v3;\n }\n v3 = *v5++;\n } while (v3);\n v2 = &a2[v6];\n }\n *v2 = 0;\n}", + "ida_pseudo_norm": "void func0(unsigned char *a1, uint8_t *a2) {\n uint8_t *v2;\n unsigned char v3;\n const unsigned short **v4;\n unsigned char *v5;\n int v6;\n long long v7;\n v2 = a2;\n v3 = *a1;\n if (*a1) {\n v4 = __ctype_b_loc();\n v5 = a1 + 1;\n v6 = 0;\n do {\n if (((*v4)[v3] & 8192) == 0) {\n v7 = v6++;\n a2[v7] = v3;\n }\n v3 = *v5++;\n } while (v3);\n v2 = &a2[v6];\n }\n *v2 = 0;\n}" + }, + { + "index": 800, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(char* text, char* result) {\n int i = 0, j = 0;\n while (text[i]) {\n if (!isspace((unsigned char)text[i])) {\n result[j++] = text[i];\n }\n i++;\n }\n result[j] = '\\0';\n}", + "test": "int main() {\n\n char result[100];\n\n\n\n func0(\"python program\", result);\n\n assert(strcmp(result, \"pythonprogram\") == 0);\n\n\n\n func0(\"python programming language\", result);\n\n assert(strcmp(result, \"pythonprogramminglanguage\") == 0);\n\n\n\n func0(\"python program\", result);\n\n assert(strcmp(result, \"pythonprogram\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %rsi,%r12\npush %rbp\npush %rbx\nmovzbl (%rdi),%ebx\ntest %bl,%bl\nje 1340 \nmov %rdi,%rbp\ncallq 1090 <__ctype_b_loc@plt>\nlea 0x1(%rbp),%rdi\nxor %esi,%esi\nxor %ecx,%ecx\njmp 1310 \nnopl 0x0(%rax)\nadd $0x1,%rdi\nmov %bl,(%rdx)\nadd $0x1,%esi\nmovzbl -0x1(%rdi),%ebx\nmovslq %esi,%rcx\nlea (%r12,%rcx,1),%rdx\ntest %bl,%bl\nje 132e \nmov (%rax),%r9\nmovzbl %bl,%r8d\nlea (%r12,%rcx,1),%rdx\ntestb $0x20,0x1(%r9,%r8,2)\nje 12f8 \nmovzbl (%rdi),%ebx\nadd $0x1,%rdi\ntest %bl,%bl\njne 1313 \nmovb $0x0,(%rdx)\npop %rbx\npop %rbp\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\nmov %rsi,%rdx\nmovb $0x0,(%rdx)\npop %rbx\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r12\nmov r12, rsi\npush rbp\npush rbx\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_132A\nmov rbp, rdi\ncall ___ctype_b_loc\nlea rdi, [rbp+1]\nxor edx, edx\njmp short loc_130E\nloc_12F8:\nadd rdi, 1\nmov [r12+rdx], bl\nlea ecx, [rdx+1]\nmovzx ebx, byte ptr [rdi-1]\nmovsxd rdx, ecx\ntest bl, bl\njz short loc_1327\nloc_130E:\nmov r8, [rax]\nloc_1311:\nmovzx ecx, bl\ntest byte ptr [r8+rcx*2+1], 20h\njz short loc_12F8\nmovzx ebx, byte ptr [rdi]\nadd rdi, 1\ntest bl, bl\njnz short loc_1311\nloc_1327:\nadd r12, rdx\nloc_132A:\nmov byte ptr [r12], 0\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "void __fastcall func0(unsigned __int8 *a1, _BYTE *a2)\n{\n _BYTE *v2; // r12\n unsigned __int8 v3; // bl\n const unsigned __int16 **v4; // rax\n unsigned __int8 *v5; // rdi\n __int64 v6; // rdx\n\n v2 = a2;\n v3 = *a1;\n if ( *a1 )\n {\n v4 = __ctype_b_loc();\n v5 = a1 + 1;\n v6 = 0LL;\n do\n {\n while ( ((*v4)[v3] & 0x2000) == 0 )\n {\n ++v5;\n a2[v6] = v3;\n v3 = *(v5 - 1);\n v6 = (int)v6 + 1;\n if ( !v3 )\n goto LABEL_6;\n }\n v3 = *v5++;\n }\n while ( v3 );\nLABEL_6:\n v2 = &a2[v6];\n }\n *v2 = 0;\n}", + "ida_strip_asm": "sub_12D0:\nendbr64\npush r12\nmov r12, rsi\npush rbp\npush rbx\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_132A\nmov rbp, rdi\ncall ___ctype_b_loc\nlea rdi, [rbp+1]\nxor edx, edx\njmp short loc_130E\nloc_12F8:\nadd rdi, 1\nmov [r12+rdx], bl\nlea ecx, [rdx+1]\nmovzx ebx, byte ptr [rdi-1]\nmovsxd rdx, ecx\ntest bl, bl\njz short loc_1327\nloc_130E:\nmov r8, [rax]\nloc_1311:\nmovzx ecx, bl\ntest byte ptr [r8+rcx*2+1], 20h\njz short loc_12F8\nmovzx ebx, byte ptr [rdi]\nadd rdi, 1\ntest bl, bl\njnz short loc_1311\nloc_1327:\nadd r12, rdx\nloc_132A:\nmov byte ptr [r12], 0\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "void __fastcall sub_12D0(unsigned __int8 *a1, _BYTE *a2)\n{\n _BYTE *v2; // r12\n unsigned __int8 v3; // bl\n const unsigned __int16 **v4; // rax\n unsigned __int8 *v5; // rdi\n __int64 v6; // rdx\n\n v2 = a2;\n v3 = *a1;\n if ( *a1 )\n {\n v4 = __ctype_b_loc();\n v5 = a1 + 1;\n v6 = 0LL;\n do\n {\n while ( ((*v4)[v3] & 0x2000) == 0 )\n {\n ++v5;\n a2[v6] = v3;\n v3 = *(v5 - 1);\n v6 = (int)v6 + 1;\n if ( !v3 )\n goto LABEL_6;\n }\n v3 = *v5++;\n }\n while ( v3 );\nLABEL_6:\n v2 = &a2[v6];\n }\n *v2 = 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_12D0(unsigned char *a1, uint8_t *a2) {\n uint8_t *v2;\n unsigned char v3;\n const unsigned short **v4;\n unsigned char *v5;\n long long v6;\n v2 = a2;\n v3 = *a1;\n if (*a1) {\n v4 = __ctype_b_loc();\n v5 = a1 + 1;\n v6 = 0LL;\n do {\n while (((*v4)[v3] & 8192) == 0) {\n ++v5;\n a2[v6] = v3;\n v3 = *(v5 - 1);\n v6 = (int)v6 + 1;\n if (!v3) goto LABEL_6;\n }\n v3 = *v5++;\n } while (v3);\n LABEL_6:\n v2 = &a2[v6];\n }\n *v2 = 0;\n}", + "ida_pseudo_norm": "void func0(unsigned char *a1, uint8_t *a2) {\n uint8_t *v2;\n unsigned char v3;\n const unsigned short **v4;\n unsigned char *v5;\n long long v6;\n v2 = a2;\n v3 = *a1;\n if (*a1) {\n v4 = __ctype_b_loc();\n v5 = a1 + 1;\n v6 = 0LL;\n do {\n while (((*v4)[v3] & 8192) == 0) {\n ++v5;\n a2[v6] = v3;\n v3 = *(v5 - 1);\n v6 = (int)v6 + 1;\n if (!v3) goto LABEL_6;\n }\n v3 = *v5++;\n } while (v3);\n LABEL_6:\n v2 = &a2[v6];\n }\n *v2 = 0;\n}" + }, + { + "index": 801, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int x, int y, int z) {\n int result[3] = {x, y, z};\n int unique_values = 0;\n int counts[3] = {0, 0, 0};\n for (int i = 0; i < 3; i++) {\n int found = 0;\n for (int j = 0; j < i; j++) {\n if (result[j] == result[i]) {\n found = 1;\n break;\n }\n }\n if (!found) {\n unique_values++;\n }\n }\n if (unique_values == 3) {\n return 0;\n } else {\n return (4 - unique_values);\n }\n}", + "test": "int main() {\n\n assert(func0(1, 1, 1) == 3);\n\n assert(func0(-1, -2, -3) == 0);\n\n assert(func0(1, 2, 2) == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x40,%rsp\nmov %edi,-0x34(%rbp)\nmov %esi,-0x38(%rbp)\nmov %edx,-0x3c(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmov -0x34(%rbp),%eax\nmov %eax,-0x20(%rbp)\nmov -0x38(%rbp),%eax\nmov %eax,-0x1c(%rbp)\nmov -0x3c(%rbp),%eax\nmov %eax,-0x18(%rbp)\nmovl $0x0,-0x30(%rbp)\nmovl $0x0,-0x14(%rbp)\nmovl $0x0,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x0,-0x2c(%rbp)\njmp 120d \nmovl $0x0,-0x28(%rbp)\nmovl $0x0,-0x24(%rbp)\njmp 11f7 \nmov -0x24(%rbp),%eax\ncltq\nmov -0x20(%rbp,%rax,4),%edx\nmov -0x2c(%rbp),%eax\ncltq\nmov -0x20(%rbp,%rax,4),%eax\ncmp %eax,%edx\njne 11f3 \nmovl $0x1,-0x28(%rbp)\njmp 11ff \naddl $0x1,-0x24(%rbp)\nmov -0x24(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 11d4 \ncmpl $0x0,-0x28(%rbp)\njne 1209 \naddl $0x1,-0x30(%rbp)\naddl $0x1,-0x2c(%rbp)\ncmpl $0x2,-0x2c(%rbp)\njle 11c4 \ncmpl $0x3,-0x30(%rbp)\njne 1220 \nmov $0x0,%eax\njmp 1228 \nmov $0x4,%eax\nsub -0x30(%rbp),%eax\nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 123c \ncallq 1060 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_34], edi\nmov [rbp+var_38], esi\nmov [rbp+var_3C], edx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov eax, [rbp+var_34]\nmov [rbp+var_20], eax\nmov eax, [rbp+var_38]\nmov [rbp+var_1C], eax\nmov eax, [rbp+var_3C]\nmov [rbp+var_18], eax\nmov [rbp+var_30], 0\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\nmov [rbp+var_2C], 0\njmp short loc_120D\nloc_11C4:\nmov [rbp+var_28], 0\nmov [rbp+var_24], 0\njmp short loc_11F7\nloc_11D4:\nmov eax, [rbp+var_24]\ncdqe\nmov edx, [rbp+rax*4+var_20]\nmov eax, [rbp+var_2C]\ncdqe\nmov eax, [rbp+rax*4+var_20]\ncmp edx, eax\njnz short loc_11F3\nmov [rbp+var_28], 1\njmp short loc_11FF\nloc_11F3:\nadd [rbp+var_24], 1\nloc_11F7:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_2C]\njl short loc_11D4\nloc_11FF:\ncmp [rbp+var_28], 0\njnz short loc_1209\nadd [rbp+var_30], 1\nloc_1209:\nadd [rbp+var_2C], 1\nloc_120D:\ncmp [rbp+var_2C], 2\njle short loc_11C4\ncmp [rbp+var_30], 3\njnz short loc_1220\nmov eax, 0\njmp short loc_1228\nloc_1220:\nmov eax, 4\nsub eax, [rbp+var_30]\nloc_1228:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_123C\ncall ___stack_chk_fail\nlocret_123C:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, int a3)\n{\n int v4; // [rsp+10h] [rbp-30h]\n int i; // [rsp+14h] [rbp-2Ch]\n int v6; // [rsp+18h] [rbp-28h]\n int j; // [rsp+1Ch] [rbp-24h]\n _DWORD v8[6]; // [rsp+20h] [rbp-20h]\n unsigned __int64 v9; // [rsp+38h] [rbp-8h]\n\n v9 = __readfsqword(0x28u);\n v8[0] = a1;\n v8[1] = a2;\n v8[2] = a3;\n v4 = 0;\n v8[3] = 0;\n v8[4] = 0;\n v8[5] = 0;\n for ( i = 0; i <= 2; ++i )\n {\n v6 = 0;\n for ( j = 0; j < i; ++j )\n {\n if ( v8[j] == v8[i] )\n {\n v6 = 1;\n break;\n }\n }\n if ( !v6 )\n ++v4;\n }\n if ( v4 == 3 )\n return 0LL;\n else\n return (unsigned int)(4 - v4);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_34], edi\nmov [rbp+var_38], esi\nmov [rbp+var_3C], edx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov eax, [rbp+var_34]\nmov [rbp+var_20], eax\nmov eax, [rbp+var_38]\nmov [rbp+var_1C], eax\nmov eax, [rbp+var_3C]\nmov [rbp+var_18], eax\nmov [rbp+var_30], 0\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\nmov [rbp+var_2C], 0\njmp short loc_120D\nloc_11C4:\nmov [rbp+var_28], 0\nmov [rbp+var_24], 0\njmp short loc_11F7\nloc_11D4:\nmov eax, [rbp+var_24]\ncdqe\nmov edx, [rbp+rax*4+var_20]\nmov eax, [rbp+var_2C]\ncdqe\nmov eax, [rbp+rax*4+var_20]\ncmp edx, eax\njnz short loc_11F3\nmov [rbp+var_28], 1\njmp short loc_11FF\nloc_11F3:\nadd [rbp+var_24], 1\nloc_11F7:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_2C]\njl short loc_11D4\nloc_11FF:\ncmp [rbp+var_28], 0\njnz short loc_1209\nadd [rbp+var_30], 1\nloc_1209:\nadd [rbp+var_2C], 1\nloc_120D:\ncmp [rbp+var_2C], 2\njle short loc_11C4\ncmp [rbp+var_30], 3\njnz short loc_1220\nmov eax, 0\njmp short loc_1228\nloc_1220:\nmov eax, 4\nsub eax, [rbp+var_30]\nloc_1228:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_123C\ncall ___stack_chk_fail\nlocret_123C:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1, int a2, int a3)\n{\n int v4; // [rsp+10h] [rbp-30h]\n int i; // [rsp+14h] [rbp-2Ch]\n int v6; // [rsp+18h] [rbp-28h]\n int j; // [rsp+1Ch] [rbp-24h]\n _DWORD v8[6]; // [rsp+20h] [rbp-20h]\n unsigned __int64 v9; // [rsp+38h] [rbp-8h]\n\n v9 = __readfsqword(0x28u);\n v8[0] = a1;\n v8[1] = a2;\n v8[2] = a3;\n v4 = 0;\n v8[3] = 0;\n v8[4] = 0;\n v8[5] = 0;\n for ( i = 0; i <= 2; ++i )\n {\n v6 = 0;\n for ( j = 0; j < i; ++j )\n {\n if ( v8[j] == v8[i] )\n {\n v6 = 1;\n break;\n }\n }\n if ( !v6 )\n ++v4;\n }\n if ( v4 == 3 )\n return 0LL;\n else\n return (unsigned int)(4 - v4);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1, int a2, int a3) {\n int v4;\n int i;\n int v6;\n int j;\n uint32_t v8[6];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n v8[0] = a1;\n v8[1] = a2;\n v8[2] = a3;\n v4 = 0;\n v8[3] = 0;\n v8[4] = 0;\n v8[5] = 0;\n for (i = 0; i <= 2; ++i) {\n v6 = 0;\n for (j = 0; j < i; ++j) {\n if (v8[j] == v8[i]) {\n v6 = 1;\n break;\n }\n }\n if (!v6) ++v4;\n }\n if (v4 == 3)\n return 0LL;\n else\n return (unsigned int)(4 - v4);\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, int a3) {\n int v4;\n int i;\n int v6;\n int j;\n uint32_t v8[6];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n v8[0] = a1;\n v8[1] = a2;\n v8[2] = a3;\n v4 = 0;\n v8[3] = 0;\n v8[4] = 0;\n v8[5] = 0;\n for (i = 0; i <= 2; ++i) {\n v6 = 0;\n for (j = 0; j < i; ++j) {\n if (v8[j] == v8[i]) {\n v6 = 1;\n break;\n }\n }\n if (!v6) ++v4;\n }\n if (v4 == 3)\n return 0LL;\n else\n return (unsigned int)(4 - v4);\n}" + }, + { + "index": 801, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int x, int y, int z) {\n int result[3] = {x, y, z};\n int unique_values = 0;\n int counts[3] = {0, 0, 0};\n for (int i = 0; i < 3; i++) {\n int found = 0;\n for (int j = 0; j < i; j++) {\n if (result[j] == result[i]) {\n found = 1;\n break;\n }\n }\n if (!found) {\n unique_values++;\n }\n }\n if (unique_values == 3) {\n return 0;\n } else {\n return (4 - unique_values);\n }\n}", + "test": "int main() {\n\n assert(func0(1, 1, 1) == 3);\n\n assert(func0(-1, -2, -3) == 0);\n\n assert(func0(1, 2, 2) == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x28,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x18(%rsp)\nxor %eax,%eax\nmov %edi,0xc(%rsp)\nmov %esi,0x10(%rsp)\nmov %edx,0x14(%rsp)\nmov $0x0,%edi\nmov $0x0,%r8d\njmp 11d1 \nmov $0x4,%eax\nsub %r8d,%eax\ncmp $0x3,%r8d\nmov $0x0,%edx\ncmove %edx,%eax\nmov 0x18(%rsp),%rdi\nxor %fs:0x28,%rdi\njne 11f4 \nadd $0x28,%rsp\nretq\nadd $0x1,%r8d\nadd $0x1,%rdi\ncmp $0x3,%rdi\nje 119a \nmov %edi,%esi\ntest %edi,%edi\njle 11c3 \nmov 0xc(%rsp,%rdi,4),%ecx\nmov $0x0,%eax\nlea 0xc(%rsp),%rdx\ncmp %ecx,(%rdx,%rax,4)\nje 11c7 \nadd $0x1,%rax\ncmp %eax,%esi\njg 11e5 \njmp 11c3 \ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 28h\nmov rax, fs:28h\nmov [rsp+28h+var_10], rax\nxor eax, eax\nmov [rsp+28h+var_1C], edi\nmov [rsp+28h+var_18], esi\nmov [rsp+28h+var_14], edx\nmov ecx, 0\njmp short loc_119E\nloc_1194:\nadd rax, 1\ncmp rax, 3\njz short loc_11BC\nloc_119E:\nmov r8d, eax\ntest eax, eax\njle short loc_11B7\nmov edx, [rsp+rax*4+28h+var_1C]\ncmp edx, edi\njz short loc_1194\ncmp r8d, 1\njle short loc_11B7\ncmp edx, esi\njz short loc_1194\nloc_11B7:\nadd ecx, 1\njmp short loc_1194\nloc_11BC:\nmov eax, 4\nsub eax, ecx\ncmp ecx, 3\nmov edx, 0\ncmovz eax, edx\nmov rdx, [rsp+28h+var_10]\nsub rdx, fs:28h\njnz short loc_11E3\nadd rsp, 28h\nretn\nloc_11E3:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, int a3)\n{\n __int64 v3; // rax\n int v4; // ecx\n int v5; // edx\n __int64 result; // rax\n _DWORD v7[3]; // [rsp+Ch] [rbp-1Ch]\n unsigned __int64 v8; // [rsp+18h] [rbp-10h]\n\n v8 = __readfsqword(0x28u);\n v3 = 0LL;\n v7[0] = a1;\n v7[1] = a2;\n v7[2] = a3;\n v4 = 0;\n do\n {\n if ( (int)v3 <= 0 || (v5 = v7[v3], v5 != a1) && ((int)v3 <= 1 || v5 != a2) )\n ++v4;\n ++v3;\n }\n while ( v3 != 3 );\n result = (unsigned int)(4 - v4);\n if ( v4 == 3 )\n return 0LL;\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nsub rsp, 28h\nmov rax, fs:28h\nmov [rsp+28h+var_10], rax\nxor eax, eax\nmov [rsp+28h+var_1C], edi\nmov [rsp+28h+var_18], esi\nmov [rsp+28h+var_14], edx\nmov ecx, 0\njmp short loc_119E\nloc_1194:\nadd rax, 1\ncmp rax, 3\njz short loc_11BC\nloc_119E:\nmov r8d, eax\ntest eax, eax\njle short loc_11B7\nmov edx, [rsp+rax*4+28h+var_1C]\ncmp edx, edi\njz short loc_1194\ncmp r8d, 1\njle short loc_11B7\ncmp edx, esi\njz short loc_1194\nloc_11B7:\nadd ecx, 1\njmp short loc_1194\nloc_11BC:\nmov eax, 4\nsub eax, ecx\ncmp ecx, 3\nmov edx, 0\ncmovz eax, edx\nmov rdx, [rsp+28h+var_10]\nsub rdx, fs:28h\njnz short loc_11E3\nadd rsp, 28h\nretn\nloc_11E3:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1, int a2, int a3)\n{\n __int64 v3; // rax\n int v4; // ecx\n int v5; // edx\n __int64 result; // rax\n _DWORD v7[3]; // [rsp+Ch] [rbp-1Ch]\n unsigned __int64 v8; // [rsp+18h] [rbp-10h]\n\n v8 = __readfsqword(0x28u);\n v3 = 0LL;\n v7[0] = a1;\n v7[1] = a2;\n v7[2] = a3;\n v4 = 0;\n do\n {\n if ( (int)v3 <= 0 || (v5 = v7[v3], v5 != a1) && ((int)v3 <= 1 || v5 != a2) )\n ++v4;\n ++v3;\n }\n while ( v3 != 3 );\n result = (unsigned int)(4 - v4);\n if ( v4 == 3 )\n return 0LL;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1, int a2, int a3) {\n long long v3;\n int v4;\n int v5;\n long long result;\n uint32_t v7[3];\n unsigned long long v8;\n v8 = __readfsqword(40u);\n v3 = 0LL;\n v7[0] = a1;\n v7[1] = a2;\n v7[2] = a3;\n v4 = 0;\n do {\n if ((int)v3 <= 0 || (v5 = v7[v3], v5 != a1) && ((int)v3 <= 1 || v5 != a2))\n ++v4;\n ++v3;\n } while (v3 != 3);\n result = (unsigned int)(4 - v4);\n if (v4 == 3) return 0LL;\n return result;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, int a3) {\n long long v3;\n int v4;\n int v5;\n long long result;\n uint32_t v7[3];\n unsigned long long v8;\n v8 = __readfsqword(40u);\n v3 = 0LL;\n v7[0] = a1;\n v7[1] = a2;\n v7[2] = a3;\n v4 = 0;\n do {\n if ((int)v3 <= 0 || (v5 = v7[v3], v5 != a1) && ((int)v3 <= 1 || v5 != a2))\n ++v4;\n ++v3;\n } while (v3 != 3);\n result = (unsigned int)(4 - v4);\n if (v4 == 3) return 0LL;\n return result;\n}" + }, + { + "index": 801, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int x, int y, int z) {\n int result[3] = {x, y, z};\n int unique_values = 0;\n int counts[3] = {0, 0, 0};\n for (int i = 0; i < 3; i++) {\n int found = 0;\n for (int j = 0; j < i; j++) {\n if (result[j] == result[i]) {\n found = 1;\n break;\n }\n }\n if (!found) {\n unique_values++;\n }\n }\n if (unique_values == 3) {\n return 0;\n } else {\n return (4 - unique_values);\n }\n}", + "test": "int main() {\n\n assert(func0(1, 1, 1) == 3);\n\n assert(func0(-1, -2, -3) == 0);\n\n assert(func0(1, 2, 2) == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x28,%rsp\nxor %r8d,%r8d\nxor %r10d,%r10d\nmov %fs:0x28,%rax\nmov %rax,0x18(%rsp)\nxor %eax,%eax\nmov %edi,0xc(%rsp)\nlea 0xc(%rsp),%r9\nmov %esi,0x10(%rsp)\nmov %edx,0x14(%rsp)\ntest %r8,%r8\nje 1458 \nlea -0x1(%r8),%edx\nmov (%r9,%r8,4),%ecx\nmov %r9,%rax\nlea (%r9,%rdx,4),%rsi\nmov %edi,%edx\njmp 141c \nnopw 0x0(%rax,%rax,1)\ncmp %rsi,%rax\nje 1458 \nmov 0x4(%rax),%edx\nadd $0x4,%rax\ncmp %edx,%ecx\njne 1410 \nadd $0x1,%r8\ncmp $0x3,%r8\njne 13ef \nmov $0x4,%eax\nmov $0x0,%edx\nsub %r10d,%eax\ncmp $0x3,%r10d\ncmove %edx,%eax\nmov 0x18(%rsp),%rdi\nxor %fs:0x28,%rdi\njne 1468 \nadd $0x28,%rsp\nretq\nnopl 0x0(%rax,%rax,1)\nadd $0x1,%r8\nadd $0x1,%r10d\ncmp $0x3,%r8\njne 13ef \njmp 142a \ncallq 1060 <__stack_chk_fail@plt>\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 28h\nmov rax, fs:28h\nmov [rsp+28h+var_10], rax\nxor eax, eax\nmov [rsp+28h+var_1C], edi\nlea r9, [rsp+28h+var_1C]\nmov [rsp+28h+var_18], esi\nmov [rsp+28h+var_14], edx\nxor edx, edx\nloc_125B:\nmov r8d, eax\ntest eax, eax\njz short loc_128C\nloc_1262:\nmov ecx, [r9+rax*4]\ncmp ecx, edi\njz short loc_127A\ncmp r8d, 2\njnz short loc_12C7\ncmp ecx, esi\nsetnz cl\nmovzx ecx, cl\nadd edx, ecx\nloc_127A:\ncmp rax, 2\njz short loc_12A0\nmov eax, 2\nmov r8d, eax\ntest eax, eax\njnz short loc_1262\nloc_128C:\nadd edx, 1\nmov eax, 1\njmp short loc_125B\nloc_12A0:\nmov eax, 4\nsub eax, edx\ncmp edx, 3\nmov edx, 0\ncmovz eax, edx\nmov rdx, [rsp+28h+var_10]\nsub rdx, fs:28h\njnz short loc_12D1\nadd rsp, 28h\nretn\nloc_12C7:\nadd edx, 1\nmov eax, 2\njmp short loc_125B\nloc_12D1:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, int a3)\n{\n __int64 v3; // rax\n int v4; // edx\n int v5; // r8d\n int v6; // ecx\n __int64 result; // rax\n _DWORD v8[3]; // [rsp+Ch] [rbp-1Ch]\n unsigned __int64 v9; // [rsp+18h] [rbp-10h]\n\n v9 = __readfsqword(0x28u);\n v3 = 0LL;\n v8[0] = a1;\n v8[1] = a2;\n v8[2] = a3;\n v4 = 0;\nLABEL_2:\n while ( 1 )\n {\n v5 = v3;\n if ( (_DWORD)v3 )\n break;\n ++v4;\n v3 = 1LL;\n }\n while ( 1 )\n {\n v6 = v8[v3];\n if ( v6 != a1 )\n {\n if ( v5 != 2 )\n {\n ++v4;\n v3 = 2LL;\n goto LABEL_2;\n }\n v4 += v6 != a2;\n }\n if ( v3 == 2 )\n break;\n v3 = 2LL;\n v5 = 2;\n }\n result = (unsigned int)(4 - v4);\n if ( v4 == 3 )\n return 0LL;\n return result;\n}", + "ida_strip_asm": "sub_1230:\nendbr64\nsub rsp, 28h\nmov rax, fs:28h\nmov [rsp+28h+var_10], rax\nxor eax, eax\nmov [rsp+28h+var_1C], edi\nlea r9, [rsp+28h+var_1C]\nmov [rsp+28h+var_18], esi\nmov [rsp+28h+var_14], edx\nxor edx, edx\nloc_125B:\nmov r8d, eax\ntest eax, eax\njz short loc_128C\nloc_1262:\nmov ecx, [r9+rax*4]\ncmp ecx, edi\njz short loc_127A\ncmp r8d, 2\njnz short loc_12C7\ncmp ecx, esi\nsetnz cl\nmovzx ecx, cl\nadd edx, ecx\nloc_127A:\ncmp rax, 2\njz short loc_12A0\nmov eax, 2\nmov r8d, eax\ntest eax, eax\njnz short loc_1262\nloc_128C:\nadd edx, 1\nmov eax, 1\njmp short loc_125B\nloc_12A0:\nmov eax, 4\nsub eax, edx\ncmp edx, 3\nmov edx, 0\ncmovz eax, edx\nmov rdx, [rsp+28h+var_10]\nsub rdx, fs:28h\njnz short loc_12D1\nadd rsp, 28h\nretn\nloc_12C7:\nadd edx, 1\nmov eax, 2\njmp short loc_125B\nloc_12D1:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1230(int a1, int a2, int a3)\n{\n __int64 v3; // rax\n int v4; // edx\n int v5; // r8d\n int v6; // ecx\n __int64 result; // rax\n _DWORD v8[3]; // [rsp+Ch] [rbp-1Ch]\n unsigned __int64 v9; // [rsp+18h] [rbp-10h]\n\n v9 = __readfsqword(0x28u);\n v3 = 0LL;\n v8[0] = a1;\n v8[1] = a2;\n v8[2] = a3;\n v4 = 0;\nLABEL_2:\n while ( 1 )\n {\n v5 = v3;\n if ( (_DWORD)v3 )\n break;\n ++v4;\n v3 = 1LL;\n }\n while ( 1 )\n {\n v6 = v8[v3];\n if ( v6 != a1 )\n {\n if ( v5 != 2 )\n {\n ++v4;\n v3 = 2LL;\n goto LABEL_2;\n }\n v4 += v6 != a2;\n }\n if ( v3 == 2 )\n break;\n v3 = 2LL;\n v5 = 2;\n }\n result = (unsigned int)(4 - v4);\n if ( v4 == 3 )\n return 0LL;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1230(int a1, int a2, int a3) {\n long long v3;\n int v4;\n int v5;\n int v6;\n long long result;\n uint32_t v8[3];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n v3 = 0LL;\n v8[0] = a1;\n v8[1] = a2;\n v8[2] = a3;\n v4 = 0;\nLABEL_2:\n while (1) {\n v5 = v3;\n if ((uint32_t)v3) break;\n ++v4;\n v3 = 1LL;\n }\n while (1) {\n v6 = v8[v3];\n if (v6 != a1) {\n if (v5 != 2) {\n ++v4;\n v3 = 2LL;\n goto LABEL_2;\n }\n v4 += v6 != a2;\n }\n if (v3 == 2) break;\n v3 = 2LL;\n v5 = 2;\n }\n result = (unsigned int)(4 - v4);\n if (v4 == 3) return 0LL;\n return result;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, int a3) {\n long long v3;\n int v4;\n int v5;\n int v6;\n long long result;\n uint32_t v8[3];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n v3 = 0LL;\n v8[0] = a1;\n v8[1] = a2;\n v8[2] = a3;\n v4 = 0;\nLABEL_2:\n while (1) {\n v5 = v3;\n if ((uint32_t)v3) break;\n ++v4;\n v3 = 1LL;\n }\n while (1) {\n v6 = v8[v3];\n if (v6 != a1) {\n if (v5 != 2) {\n ++v4;\n v3 = 2LL;\n goto LABEL_2;\n }\n v4 += v6 != a2;\n }\n if (v3 == 2) break;\n v3 = 2LL;\n v5 = 2;\n }\n result = (unsigned int)(4 - v4);\n if (v4 == 3) return 0LL;\n return result;\n}" + }, + { + "index": 801, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int x, int y, int z) {\n int result[3] = {x, y, z};\n int unique_values = 0;\n int counts[3] = {0, 0, 0};\n for (int i = 0; i < 3; i++) {\n int found = 0;\n for (int j = 0; j < i; j++) {\n if (result[j] == result[i]) {\n found = 1;\n break;\n }\n }\n if (!found) {\n unique_values++;\n }\n }\n if (unique_values == 3) {\n return 0;\n } else {\n return (4 - unique_values);\n }\n}", + "test": "int main() {\n\n assert(func0(1, 1, 1) == 3);\n\n assert(func0(-1, -2, -3) == 0);\n\n assert(func0(1, 2, 2) == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nxor %ecx,%ecx\ncmp %esi,%edi\nsetne %cl\nadd $0x1,%ecx\ncmp %edx,%edi\nje 1162 \ncmp %edx,%esi\nje 1162 \nxor %eax,%eax\ncmp $0x2,%ecx\nje 1170 \nmov $0x2,%ecx\nmov $0x4,%eax\nsub %ecx,%eax\nretq\nnopw 0x0(%rax,%rax,1)\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ncmp edi, esi\njz short loc_1230\ncmp edi, edx\njz short loc_1223\nxor eax, eax\ncmp esi, edx\njz short loc_1223\nretn\nloc_1223:\nmov edx, 2\nloc_1228:\nmov eax, 4\nsub eax, edx\nretn\nloc_1230:\ncmp edi, edx\nsetnz dl\nmovzx edx, dl\nadd edx, 1\njmp short loc_1228", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, int a3)\n{\n __int64 result; // rax\n int v4; // edx\n\n if ( a1 == a2 )\n {\n v4 = (a1 != a3) + 1;\n return (unsigned int)(4 - v4);\n }\n if ( a1 == a3 || (result = 0LL, a2 == a3) )\n {\n v4 = 2;\n return (unsigned int)(4 - v4);\n }\n return result;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\ncmp edi, esi\njz short loc_1230\ncmp edi, edx\njz short loc_1223\nxor eax, eax\ncmp esi, edx\njz short loc_1223\nretn\nloc_1223:\nmov edx, 2\nloc_1228:\nmov eax, 4\nsub eax, edx\nretn\nloc_1230:\ncmp edi, edx\nsetnz dl\nmovzx edx, dl\nadd edx, 1\njmp short loc_1228", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(int a1, int a2, int a3)\n{\n __int64 result; // rax\n int v4; // edx\n\n if ( a1 == a2 )\n {\n v4 = (a1 != a3) + 1;\n return (unsigned int)(4 - v4);\n }\n if ( a1 == a3 || (result = 0LL, a2 == a3) )\n {\n v4 = 2;\n return (unsigned int)(4 - v4);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(int a1, int a2, int a3) {\n long long result;\n int v4;\n if (a1 == a2) {\n v4 = (a1 != a3) + 1;\n return (unsigned int)(4 - v4);\n }\n if (a1 == a3 || (result = 0LL, a2 == a3)) {\n v4 = 2;\n return (unsigned int)(4 - v4);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, int a3) {\n long long result;\n int v4;\n if (a1 == a2) {\n v4 = (a1 != a3) + 1;\n return (unsigned int)(4 - v4);\n }\n if (a1 == a3 || (result = 0LL, a2 == a3)) {\n v4 = 2;\n return (unsigned int)(4 - v4);\n }\n return result;\n}" + }, + { + "index": 802, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n for (int i = 1; i < n; i++) {\n if (arr[i] < arr[i - 1]) {\n return i;\n }\n }\n return 0;\n}", + "test": "int main() {\n\n int arr1[] = {3, 2, 1};\n\n int arr2[] = {4, 5, 1, 2, 3};\n\n int arr3[] = {7, 8, 9, 1, 2, 3};\n\n \n\n assert(func0(arr1, 3) == 1);\n\n assert(func0(arr2, 5) == 2);\n\n assert(func0(arr3, 6) == 3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x1,-0x4(%rbp)\njmp 11ba \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njge 11b6 \nmov -0x4(%rbp),%eax\njmp 11c7 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1181 \nmov $0x0,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 1\njmp short loc_11BA\nloc_1181:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nshl rax, 2\nlea rcx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njge short loc_11B6\nmov eax, [rbp+var_4]\njmp short loc_11C7\nloc_11B6:\nadd [rbp+var_4], 1\nloc_11BA:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1181\nmov eax, 0\nloc_11C7:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-4h]\n\n for ( i = 1; i < a2; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) < *(_DWORD *)(4LL * i - 4 + a1) )\n return (unsigned int)i;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 1\njmp short loc_11BA\nloc_1181:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nshl rax, 2\nlea rcx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njge short loc_11B6\nmov eax, [rbp+var_4]\njmp short loc_11C7\nloc_11B6:\nadd [rbp+var_4], 1\nloc_11BA:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1181\nmov eax, 0\nloc_11C7:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-4h]\n\n for ( i = 1; i < a2; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) < *(_DWORD *)(4LL * i - 4 + a1) )\n return (unsigned int)i;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int i;\n for (i = 1; i < a2; ++i) {\n if (*(uint32_t *)(4LL * i + a1) < *(uint32_t *)(4LL * i - 4 + a1))\n return (unsigned int)i;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int i;\n for (i = 1; i < a2; ++i) {\n if (*(uint32_t *)(4LL * i + a1) < *(uint32_t *)(4LL * i - 4 + a1))\n return (unsigned int)i;\n }\n return 0LL;\n}" + }, + { + "index": 802, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n for (int i = 1; i < n; i++) {\n if (arr[i] < arr[i - 1]) {\n return i;\n }\n }\n return 0;\n}", + "test": "int main() {\n\n int arr1[] = {3, 2, 1};\n\n int arr2[] = {4, 5, 1, 2, 3};\n\n int arr3[] = {7, 8, 9, 1, 2, 3};\n\n \n\n assert(func0(arr1, 3) == 1);\n\n assert(func0(arr2, 5) == 2);\n\n assert(func0(arr3, 6) == 3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%esi\njle 119a \nlea -0x2(%rsi),%edx\nadd $0x2,%rdx\nmov $0x1,%eax\nmov %eax,%ecx\nmov -0x4(%rdi,%rax,4),%esi\ncmp %esi,(%rdi,%rax,4)\njl 1197 \nadd $0x1,%rax\ncmp %rdx,%rax\njne 117e \nmov $0x0,%ecx\nmov %ecx,%eax\nretq\nmov $0x0,%ecx\njmp 1197 \n", + "ida_asm": "func0:\nendbr64\ncmp esi, 1\njle short loc_1191\nmov esi, esi\nmov eax, 1\nloc_1179:\nmov edx, [rdi+rax*4-4]\ncmp [rdi+rax*4], edx\njl short locret_1196\nadd rax, 1\ncmp rax, rsi\njnz short loc_1179\nmov eax, 0\nretn\nloc_1191:\nmov eax, 0\nlocret_1196:\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 result; // rax\n\n if ( a2 <= 1 )\n return 0LL;\n result = 1LL;\n while ( *(_DWORD *)(a1 + 4 * result) >= *(_DWORD *)(a1 + 4 * result - 4) )\n {\n if ( ++result == a2 )\n return 0LL;\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ncmp esi, 1\njle short loc_1191\nmov esi, esi\nmov eax, 1\nloc_1179:\nmov edx, [rdi+rax*4-4]\ncmp [rdi+rax*4], edx\njl short locret_1196\nadd rax, 1\ncmp rax, rsi\njnz short loc_1179\nmov eax, 0\nretn\nloc_1191:\nmov eax, 0\nlocret_1196:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n __int64 result; // rax\n\n if ( a2 <= 1 )\n return 0LL;\n result = 1LL;\n while ( *(_DWORD *)(a1 + 4 * result) >= *(_DWORD *)(a1 + 4 * result - 4) )\n {\n if ( ++result == a2 )\n return 0LL;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n long long result;\n if (a2 <= 1) return 0LL;\n result = 1LL;\n while (*(uint32_t *)(a1 + 4 * result) >= *(uint32_t *)(a1 + 4 * result - 4)) {\n if (++result == a2) return 0LL;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long result;\n if (a2 <= 1) return 0LL;\n result = 1LL;\n while (*(uint32_t *)(a1 + 4 * result) >= *(uint32_t *)(a1 + 4 * result - 4)) {\n if (++result == a2) return 0LL;\n }\n return result;\n}" + }, + { + "index": 802, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n for (int i = 1; i < n; i++) {\n if (arr[i] < arr[i - 1]) {\n return i;\n }\n }\n return 0;\n}", + "test": "int main() {\n\n int arr1[] = {3, 2, 1};\n\n int arr2[] = {4, 5, 1, 2, 3};\n\n int arr3[] = {7, 8, 9, 1, 2, 3};\n\n \n\n assert(func0(arr1, 3) == 1);\n\n assert(func0(arr2, 5) == 2);\n\n assert(func0(arr3, 6) == 3);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%esi\njle 1180 \nlea -0x2(%rsi),%edx\nmov $0x1,%eax\nadd $0x2,%rdx\njmp 1169 \nnopw 0x0(%rax,%rax,1)\nadd $0x1,%rax\ncmp %rdx,%rax\nje 1180 \nmov -0x4(%rdi,%rax,4),%ecx\nmov %eax,%r8d\ncmp %ecx,(%rdi,%rax,4)\njge 1160 \nmov %r8d,%eax\nretq\nnopl 0x0(%rax)\nxor %r8d,%r8d\nmov %r8d,%eax\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ncmp esi, 1\njle short loc_12B0\nmov edx, [rdi]\nmov esi, esi\nmov eax, 1\njmp short loc_12A1\nloc_1298:\nadd rax, 1\ncmp rax, rsi\njz short loc_12B0\nloc_12A1:\nmov ecx, edx\nmov edx, [rdi+rax*4]\ncmp edx, ecx\njge short loc_1298\nretn\nloc_12B0:\nxor eax, eax\nretn", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int v2; // edx\n __int64 result; // rax\n int v4; // ecx\n\n if ( a2 <= 1 )\n return 0LL;\n v2 = *a1;\n result = 1LL;\n while ( 1 )\n {\n v4 = v2;\n v2 = a1[result];\n if ( v2 < v4 )\n break;\n if ( ++result == a2 )\n return 0LL;\n }\n return result;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\ncmp esi, 1\njle short loc_12B0\nmov edx, [rdi]\nmov esi, esi\nmov eax, 1\njmp short loc_12A1\nloc_1298:\nadd rax, 1\ncmp rax, rsi\njz short loc_12B0\nloc_12A1:\nmov ecx, edx\nmov edx, [rdi+rax*4]\ncmp edx, ecx\njge short loc_1298\nretn\nloc_12B0:\nxor eax, eax\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1280(int *a1, int a2)\n{\n int v2; // edx\n __int64 result; // rax\n int v4; // ecx\n\n if ( a2 <= 1 )\n return 0LL;\n v2 = *a1;\n result = 1LL;\n while ( 1 )\n {\n v4 = v2;\n v2 = a1[result];\n if ( v2 < v4 )\n break;\n if ( ++result == a2 )\n return 0LL;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1280(int *a1, int a2) {\n int v2;\n long long result;\n int v4;\n if (a2 <= 1) return 0LL;\n v2 = *a1;\n result = 1LL;\n while (1) {\n v4 = v2;\n v2 = a1[result];\n if (v2 < v4) break;\n if (++result == a2) return 0LL;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int v2;\n long long result;\n int v4;\n if (a2 <= 1) return 0LL;\n v2 = *a1;\n result = 1LL;\n while (1) {\n v4 = v2;\n v2 = a1[result];\n if (v2 < v4) break;\n if (++result == a2) return 0LL;\n }\n return result;\n}" + }, + { + "index": 803, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int n) {\n int i = 1;\n while (i * i <= n) {\n if ((n % i == 0) && (n / i == i)) {\n return true;\n }\n i = i + 1;\n }\n return false;\n}", + "test": "int main() {\n\n assert(func0(10) == false);\n\n assert(func0(36) == true);\n\n assert(func0(14) == false);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmovl $0x1,-0x4(%rbp)\njmp 1181 \nmov -0x14(%rbp),%eax\ncltd\nidivl -0x4(%rbp)\nmov %edx,%eax\ntest %eax,%eax\njne 117d \nmov -0x14(%rbp),%eax\ncltd\nidivl -0x4(%rbp)\ncmp %eax,-0x4(%rbp)\njne 117d \nmov $0x1,%eax\njmp 1191 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nimul %eax,%eax\ncmp %eax,-0x14(%rbp)\njge 115d \nmov $0x0,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_4], 1\njmp short loc_1181\nloc_115D:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njnz short loc_117D\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\ncmp [rbp+var_4], eax\njnz short loc_117D\nmov eax, 1\njmp short loc_1191\nloc_117D:\nadd [rbp+var_4], 1\nloc_1181:\nmov eax, [rbp+var_4]\nimul eax, eax\ncmp [rbp+var_14], eax\njge short loc_115D\nmov eax, 0\nloc_1191:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int i; // [rsp+10h] [rbp-4h]\n\n for ( i = 1; a1 >= i * i; ++i )\n {\n if ( !(a1 % i) && i == a1 / i )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_4], 1\njmp short loc_1181\nloc_115D:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njnz short loc_117D\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\ncmp [rbp+var_4], eax\njnz short loc_117D\nmov eax, 1\njmp short loc_1191\nloc_117D:\nadd [rbp+var_4], 1\nloc_1181:\nmov eax, [rbp+var_4]\nimul eax, eax\ncmp [rbp+var_14], eax\njge short loc_115D\nmov eax, 0\nloc_1191:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int i; // [rsp+10h] [rbp-4h]\n\n for ( i = 1; a1 >= i * i; ++i )\n {\n if ( !(a1 % i) && i == a1 / i )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int i;\n for (i = 1; a1 >= i * i; ++i) {\n if (!(a1 % i) && i == a1 / i) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int i;\n for (i = 1; a1 >= i * i; ++i) {\n if (!(a1 % i) && i == a1 / i) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 803, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int n) {\n int i = 1;\n while (i * i <= n) {\n if ((n % i == 0) && (n / i == i)) {\n return true;\n }\n i = i + 1;\n }\n return false;\n}", + "test": "int main() {\n\n assert(func0(10) == false);\n\n assert(func0(36) == true);\n\n assert(func0(14) == false);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\njle 1182 \nmov $0x1,%ecx\njmp 1164 \nadd $0x1,%ecx\nmov %ecx,%eax\nimul %ecx,%eax\ncmp %edi,%eax\njg 117c \nmov %edi,%eax\ncltd\nidiv %ecx\ntest %edx,%edx\njne 1158 \nmov %edi,%eax\ncltd\nidiv %ecx\ncmp %ecx,%eax\njne 1158 \nmov $0x1,%eax\nretq\nmov $0x0,%eax\nretq\nmov $0x0,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njle short loc_1182\nmov ecx, 1\njmp short loc_1164\nloc_1158:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, edi\njg short loc_117C\nloc_1164:\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_1158\nmov eax, edi\ncdq\nidiv ecx\ncmp eax, ecx\njnz short loc_1158\nmov eax, 1\nretn\nloc_117C:\nmov eax, 0\nretn\nloc_1182:\nmov eax, 0\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // ecx\n\n if ( a1 <= 0 )\n return 0LL;\n v1 = 1;\n do\n {\n if ( !(a1 % v1) && a1 / v1 == v1 )\n return 1LL;\n ++v1;\n }\n while ( v1 * v1 <= a1 );\n return 0LL;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ntest edi, edi\njle short loc_1182\nmov ecx, 1\njmp short loc_1164\nloc_1158:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, edi\njg short loc_117C\nloc_1164:\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_1158\nmov eax, edi\ncdq\nidiv ecx\ncmp eax, ecx\njnz short loc_1158\nmov eax, 1\nretn\nloc_117C:\nmov eax, 0\nretn\nloc_1182:\nmov eax, 0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v1; // ecx\n\n if ( a1 <= 0 )\n return 0LL;\n v1 = 1;\n do\n {\n if ( !(a1 % v1) && a1 / v1 == v1 )\n return 1LL;\n ++v1;\n }\n while ( v1 * v1 <= a1 );\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v1;\n if (a1 <= 0) return 0LL;\n v1 = 1;\n do {\n if (!(a1 % v1) && a1 / v1 == v1) return 1LL;\n ++v1;\n } while (v1 * v1 <= a1);\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n if (a1 <= 0) return 0LL;\n v1 = 1;\n do {\n if (!(a1 % v1) && a1 / v1 == v1) return 1LL;\n ++v1;\n } while (v1 * v1 <= a1);\n return 0LL;\n}" + }, + { + "index": 803, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int n) {\n int i = 1;\n while (i * i <= n) {\n if ((n % i == 0) && (n / i == i)) {\n return true;\n }\n i = i + 1;\n }\n return false;\n}", + "test": "int main() {\n\n assert(func0(10) == false);\n\n assert(func0(36) == true);\n\n assert(func0(14) == false);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\njle 1269 \nmov $0x1,%ecx\nnopl (%rax)\nmov %edi,%eax\ncltd\nidiv %ecx\ntest %edx,%edx\njne 125d \ncmp %ecx,%eax\nje 1270 \nadd $0x1,%ecx\nmov %ecx,%eax\nimul %ecx,%eax\ncmp %edi,%eax\njle 1250 \nxor %eax,%eax\nretq\nnopl 0x0(%rax)\nmov $0x1,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njle short loc_1219\nmov ecx, 1\nnop dword ptr [rax]\nloc_1200:\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_120D\ncmp eax, ecx\njz short loc_1220\nloc_120D:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, edi\njle short loc_1200\nloc_1219:\nxor eax, eax\nretn\nloc_1220:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // ecx\n\n if ( a1 <= 0 )\n return 0LL;\n v1 = 1;\n while ( a1 % v1 || a1 / v1 != v1 )\n {\n ++v1;\n if ( v1 * v1 > a1 )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_11F0:\nendbr64\ntest edi, edi\njle short loc_1219\nmov ecx, 1\nnop dword ptr [rax]\nloc_1200:\nmov eax, edi\ncdq\nidiv ecx\ntest edx, edx\njnz short loc_120D\ncmp eax, ecx\njz short loc_1220\nloc_120D:\nadd ecx, 1\nmov eax, ecx\nimul eax, ecx\ncmp eax, edi\njle short loc_1200\nloc_1219:\nxor eax, eax\nretn\nloc_1220:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11F0(int a1)\n{\n int v1; // ecx\n\n if ( a1 <= 0 )\n return 0LL;\n v1 = 1;\n while ( a1 % v1 || a1 / v1 != v1 )\n {\n ++v1;\n if ( v1 * v1 > a1 )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11F0(int a1) {\n int v1;\n if (a1 <= 0) return 0LL;\n v1 = 1;\n while (a1 % v1 || a1 / v1 != v1) {\n ++v1;\n if (v1 * v1 > a1) return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n if (a1 <= 0) return 0LL;\n v1 = 1;\n while (a1 % v1 || a1 / v1 != v1) {\n ++v1;\n if (v1 * v1 > a1) return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": 804, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "bool func0(int arr[], int n) {\n for (int i = 0; i < n; i++) {\n if ((arr[i] & 1) == 0) {\n return true;\n }\n }\n return false;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3};\n\n assert(func0(arr1, 3) == true);\n\n\n\n int arr2[] = {1, 2, 1, 4};\n\n assert(func0(arr2, 4) == true);\n\n\n\n int arr3[] = {1, 1};\n\n assert(func0(arr3, 2) == false);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11a9 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nand $0x1,%eax\ntest %eax,%eax\njne 11a5 \nmov $0x1,%eax\njmp 11b6 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1181 \nmov $0x0,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 0\njmp short loc_11A9\nloc_1181:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njnz short loc_11A5\nmov eax, 1\njmp short loc_11B6\nloc_11A5:\nadd [rbp+var_4], 1\nloc_11A9:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1181\nmov eax, 0\nloc_11B6:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n if ( (*(_DWORD *)(4LL * i + a1) & 1) == 0 )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 0\njmp short loc_11A9\nloc_1181:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njnz short loc_11A5\nmov eax, 1\njmp short loc_11B6\nloc_11A5:\nadd [rbp+var_4], 1\nloc_11A9:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1181\nmov eax, 0\nloc_11B6:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n if ( (*(_DWORD *)(4LL * i + a1) & 1) == 0 )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int i;\n for (i = 0; i < a2; ++i) {\n if ((*(uint32_t *)(4LL * i + a1) & 1) == 0) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int i;\n for (i = 0; i < a2; ++i) {\n if ((*(uint32_t *)(4LL * i + a1) & 1) == 0) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 804, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "bool func0(int arr[], int n) {\n for (int i = 0; i < n; i++) {\n if ((arr[i] & 1) == 0) {\n return true;\n }\n }\n return false;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3};\n\n assert(func0(arr1, 3) == true);\n\n\n\n int arr2[] = {1, 2, 1, 4};\n\n assert(func0(arr2, 4) == true);\n\n\n\n int arr3[] = {1, 1};\n\n assert(func0(arr3, 2) == false);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1190 \nmov %rdi,%rax\nlea -0x1(%rsi),%edx\nlea 0x4(%rdi,%rdx,4),%rdx\ntestb $0x1,(%rax)\nje 1196 \nadd $0x4,%rax\ncmp %rdx,%rax\njne 117c \nmov $0x0,%eax\nretq\nmov $0x0,%eax\nretq\nmov $0x1,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_118F\nmov rax, rdi\nmovsxd rsi, esi\nlea rdx, [rdi+rsi*4]\nloc_117B:\ntest byte ptr [rax], 1\njz short loc_1195\nadd rax, 4\ncmp rax, rdx\njnz short loc_117B\nmov eax, 0\nretn\nloc_118F:\nmov eax, 0\nretn\nloc_1195:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(_BYTE *a1, int a2)\n{\n _BYTE *v2; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = a1;\n while ( (*v2 & 1) != 0 )\n {\n v2 += 4;\n if ( v2 == &a1[4 * a2] )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_118F\nmov rax, rdi\nmovsxd rsi, esi\nlea rdx, [rdi+rsi*4]\nloc_117B:\ntest byte ptr [rax], 1\njz short loc_1195\nadd rax, 4\ncmp rax, rdx\njnz short loc_117B\nmov eax, 0\nretn\nloc_118F:\nmov eax, 0\nretn\nloc_1195:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_BYTE *a1, int a2)\n{\n _BYTE *v2; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = a1;\n while ( (*v2 & 1) != 0 )\n {\n v2 += 4;\n if ( v2 == &a1[4 * a2] )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint8_t *a1, int a2) {\n uint8_t *v2;\n if (a2 <= 0) return 0LL;\n v2 = a1;\n while ((*v2 & 1) != 0) {\n v2 += 4;\n if (v2 == &a1[4 * a2]) return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(uint8_t *a1, int a2) {\n uint8_t *v2;\n if (a2 <= 0) return 0LL;\n v2 = a1;\n while ((*v2 & 1) != 0) {\n v2 += 4;\n if (v2 == &a1[4 * a2]) return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": 805, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n", + "func": "int* func0(int lists[][3], int num_lists, int* length) {\n int max_sum = -1;\n int* max_list = NULL;\n for (int i = 0; i < num_lists; i++) {\n int current_sum = 0;\n for (int j = 0; j < 3; j++) {\n current_sum += lists[i][j];\n }\n if (current_sum > max_sum) {\n max_sum = current_sum;\n max_list = lists[i];\n *length = 3;\n }\n }\n return max_list;\n}", + "test": "int main() {\n\n int length;\n\n \n\n int list1[4][3] = {{1,2,3}, {4,5,6}, {10,11,12}, {7,8,9}};\n\n int* max_list1 = func0(list1, 4, &length);\n\n int expected1[3] = {10, 11, 12};\n\n assert(memcmp(max_list1, expected1, sizeof(expected1)) == 0);\n\n \n\n int list2[3][3] = {{3,2,1}, {6,5,4}, {12,11,10}};\n\n int* max_list2 = func0(list2, 3, &length);\n\n int expected2[3] = {12, 11, 10};\n\n assert(memcmp(max_list2, expected2, sizeof(expected2)) == 0);\n\n \n\n int list3[1][3] = {{2,3,1}};\n\n int* max_list3 = func0(list3, 1, &length);\n\n int expected3[3] = {2, 3, 1};\n\n assert(memcmp(max_list3, expected3, sizeof(expected3)) == 0);\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmov %rdx,-0x38(%rbp)\nmovl $0xffffffff,-0x18(%rbp)\nmovq $0x0,-0x8(%rbp)\nmovl $0x0,-0x14(%rbp)\njmp 1253 \nmovl $0x0,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 1210 \nmov -0x14(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x28(%rbp),%rax\nadd %rax,%rdx\nmov -0xc(%rbp),%eax\ncltq\nmov (%rdx,%rax,4),%eax\nadd %eax,-0x10(%rbp)\naddl $0x1,-0xc(%rbp)\ncmpl $0x2,-0xc(%rbp)\njle 11e4 \nmov -0x10(%rbp),%eax\ncmp -0x18(%rbp),%eax\njle 124f \nmov -0x10(%rbp),%eax\nmov %eax,-0x18(%rbp)\nmov -0x14(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov %rax,-0x8(%rbp)\nmov -0x38(%rbp),%rax\nmovl $0x3,(%rax)\naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 11d4 \nmov -0x8(%rbp),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmov [rbp+var_18], 0FFFFFFFFh\nmov [rbp+var_8], 0\nmov [rbp+var_14], 0\njmp short loc_1253\nloc_11D4:\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp short loc_1210\nloc_11E4:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov eax, [rbp+var_C]\ncdqe\nmov eax, [rdx+rax*4]\nadd [rbp+var_10], eax\nadd [rbp+var_C], 1\nloc_1210:\ncmp [rbp+var_C], 2\njle short loc_11E4\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_18]\njle short loc_124F\nmov eax, [rbp+var_10]\nmov [rbp+var_18], eax\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov [rbp+var_8], rax\nmov rax, [rbp+var_38]\nmov dword ptr [rax], 3\nloc_124F:\nadd [rbp+var_14], 1\nloc_1253:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl loc_11D4\nmov rax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, _DWORD *a3)\n{\n int v4; // [rsp+20h] [rbp-18h]\n int i; // [rsp+24h] [rbp-14h]\n int v6; // [rsp+28h] [rbp-10h]\n int j; // [rsp+2Ch] [rbp-Ch]\n __int64 v8; // [rsp+30h] [rbp-8h]\n\n v4 = -1;\n v8 = 0LL;\n for ( i = 0; i < a2; ++i )\n {\n v6 = 0;\n for ( j = 0; j <= 2; ++j )\n v6 += *(_DWORD *)(a1 + 12LL * i + 4LL * j);\n if ( v6 > v4 )\n {\n v4 = v6;\n v8 = 12LL * i + a1;\n *a3 = 3;\n }\n }\n return v8;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmov [rbp+var_18], 0FFFFFFFFh\nmov [rbp+var_8], 0\nmov [rbp+var_14], 0\njmp short loc_1253\nloc_11D4:\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp short loc_1210\nloc_11E4:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov eax, [rbp+var_C]\ncdqe\nmov eax, [rdx+rax*4]\nadd [rbp+var_10], eax\nadd [rbp+var_C], 1\nloc_1210:\ncmp [rbp+var_C], 2\njle short loc_11E4\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_18]\njle short loc_124F\nmov eax, [rbp+var_10]\nmov [rbp+var_18], eax\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov [rbp+var_8], rax\nmov rax, [rbp+var_38]\nmov dword ptr [rax], 3\nloc_124F:\nadd [rbp+var_14], 1\nloc_1253:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl loc_11D4\nmov rax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(__int64 a1, int a2, _DWORD *a3)\n{\n int v4; // [rsp+20h] [rbp-18h]\n int i; // [rsp+24h] [rbp-14h]\n int v6; // [rsp+28h] [rbp-10h]\n int j; // [rsp+2Ch] [rbp-Ch]\n __int64 v8; // [rsp+30h] [rbp-8h]\n\n v4 = -1;\n v8 = 0LL;\n for ( i = 0; i < a2; ++i )\n {\n v6 = 0;\n for ( j = 0; j <= 2; ++j )\n v6 += *(_DWORD *)(a1 + 12LL * i + 4LL * j);\n if ( v6 > v4 )\n {\n v4 = v6;\n v8 = 12LL * i + a1;\n *a3 = 3;\n }\n }\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(long long a1, int a2, uint32_t *a3) {\n int v4;\n int i;\n int v6;\n int j;\n long long v8;\n v4 = -1;\n v8 = 0LL;\n for (i = 0; i < a2; ++i) {\n v6 = 0;\n for (j = 0; j <= 2; ++j) v6 += *(uint32_t *)(a1 + 12LL * i + 4LL * j);\n if (v6 > v4) {\n v4 = v6;\n v8 = 12LL * i + a1;\n *a3 = 3;\n }\n }\n return v8;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, uint32_t *a3) {\n int v4;\n int i;\n int v6;\n int j;\n long long v8;\n v4 = -1;\n v8 = 0LL;\n for (i = 0; i < a2; ++i) {\n v6 = 0;\n for (j = 0; j <= 2; ++j) v6 += *(uint32_t *)(a1 + 12LL * i + 4LL * j);\n if (v6 > v4) {\n v4 = v6;\n v8 = 12LL * i + a1;\n *a3 = 3;\n }\n }\n return v8;\n}" + }, + { + "index": 805, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n", + "func": "int* func0(int lists[][3], int num_lists, int* length) {\n int max_sum = -1;\n int* max_list = NULL;\n for (int i = 0; i < num_lists; i++) {\n int current_sum = 0;\n for (int j = 0; j < 3; j++) {\n current_sum += lists[i][j];\n }\n if (current_sum > max_sum) {\n max_sum = current_sum;\n max_list = lists[i];\n *length = 3;\n }\n }\n return max_list;\n}", + "test": "int main() {\n\n int length;\n\n \n\n int list1[4][3] = {{1,2,3}, {4,5,6}, {10,11,12}, {7,8,9}};\n\n int* max_list1 = func0(list1, 4, &length);\n\n int expected1[3] = {10, 11, 12};\n\n assert(memcmp(max_list1, expected1, sizeof(expected1)) == 0);\n\n \n\n int list2[3][3] = {{3,2,1}, {6,5,4}, {12,11,10}};\n\n int* max_list2 = func0(list2, 3, &length);\n\n int expected2[3] = {12, 11, 10};\n\n assert(memcmp(max_list2, expected2, sizeof(expected2)) == 0);\n\n \n\n int list3[1][3] = {{2,3,1}};\n\n int* max_list3 = func0(list3, 1, &length);\n\n int expected3[3] = {2, 3, 1};\n\n assert(memcmp(max_list3, expected3, sizeof(expected3)) == 0);\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11ef \nmov %rdi,%rax\nlea -0x1(%rsi),%ecx\nlea (%rcx,%rcx,2),%rcx\nlea 0xc(%rdi,%rcx,4),%rdi\nmov $0x0,%r8d\nmov $0xffffffff,%esi\njmp 11d6 \nadd $0xc,%rax\ncmp %rdi,%rax\nje 11f5 \nmov 0x4(%rax),%ecx\nadd (%rax),%ecx\nadd 0x8(%rax),%ecx\ncmp %esi,%ecx\njle 11cd \nmovl $0x3,(%rdx)\nmov %rax,%r8\nmov %ecx,%esi\njmp 11cd \nmov $0x0,%r8d\nmov %r8,%rax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11EE\nmov rax, rdi\nmovsxd rsi, esi\nlea rcx, [rsi+rsi*2]\nlea rdi, [rdi+rcx*4]\nmov r8d, 0\nmov esi, 0FFFFFFFFh\njmp short loc_11D5\nloc_11CC:\nadd rax, 0Ch\ncmp rax, rdi\njz short loc_11F4\nloc_11D5:\nmov ecx, [rax+4]\nadd ecx, [rax]\nadd ecx, [rax+8]\ncmp ecx, esi\njle short loc_11CC\nmov dword ptr [rdx], 3\nmov r8, rax\nmov esi, ecx\njmp short loc_11CC\nloc_11EE:\nmov r8d, 0\nloc_11F4:\nmov rax, r8\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(_DWORD *a1, int a2, _DWORD *a3)\n{\n _DWORD *v3; // rax\n _DWORD *v4; // rdi\n _DWORD *v5; // r8\n int v6; // esi\n int v7; // ecx\n\n if ( a2 <= 0 )\n return 0LL;\n v3 = a1;\n v4 = &a1[3 * a2];\n v5 = 0LL;\n v6 = -1;\n do\n {\n v7 = v3[2] + *v3 + v3[1];\n if ( v7 > v6 )\n {\n *a3 = 3;\n v5 = v3;\n v6 = v7;\n }\n v3 += 3;\n }\n while ( v3 != v4 );\n return v5;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\ntest esi, esi\njle short loc_11EE\nmov rax, rdi\nmovsxd rsi, esi\nlea rcx, [rsi+rsi*2]\nlea rdi, [rdi+rcx*4]\nmov r8d, 0\nmov esi, 0FFFFFFFFh\njmp short loc_11D5\nloc_11CC:\nadd rax, 0Ch\ncmp rax, rdi\njz short loc_11F4\nloc_11D5:\nmov ecx, [rax+4]\nadd ecx, [rax]\nadd ecx, [rax+8]\ncmp ecx, esi\njle short loc_11CC\nmov dword ptr [rdx], 3\nmov r8, rax\nmov esi, ecx\njmp short loc_11CC\nloc_11EE:\nmov r8d, 0\nloc_11F4:\nmov rax, r8\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(_DWORD *a1, int a2, _DWORD *a3)\n{\n _DWORD *v3; // rax\n _DWORD *v4; // rdi\n _DWORD *v5; // r8\n int v6; // esi\n int v7; // ecx\n\n if ( a2 <= 0 )\n return 0LL;\n v3 = a1;\n v4 = &a1[3 * a2];\n v5 = 0LL;\n v6 = -1;\n do\n {\n v7 = v3[2] + *v3 + v3[1];\n if ( v7 > v6 )\n {\n *a3 = 3;\n v5 = v3;\n v6 = v7;\n }\n v3 += 3;\n }\n while ( v3 != v4 );\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(uint32_t *a1, int a2, uint32_t *a3) {\n uint32_t *v3;\n uint32_t *v4;\n uint32_t *v5;\n int v6;\n int v7;\n if (a2 <= 0) return 0LL;\n v3 = a1;\n v4 = &a1[3 * a2];\n v5 = 0LL;\n v6 = -1;\n do {\n v7 = v3[2] + *v3 + v3[1];\n if (v7 > v6) {\n *a3 = 3;\n v5 = v3;\n v6 = v7;\n }\n v3 += 3;\n } while (v3 != v4);\n return v5;\n}", + "ida_pseudo_norm": "uint32_t *func0(uint32_t *a1, int a2, uint32_t *a3) {\n uint32_t *v3;\n uint32_t *v4;\n uint32_t *v5;\n int v6;\n int v7;\n if (a2 <= 0) return 0LL;\n v3 = a1;\n v4 = &a1[3 * a2];\n v5 = 0LL;\n v6 = -1;\n do {\n v7 = v3[2] + *v3 + v3[1];\n if (v7 > v6) {\n *a3 = 3;\n v5 = v3;\n v6 = v7;\n }\n v3 += 3;\n } while (v3 != v4);\n return v5;\n}" + }, + { + "index": 805, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n", + "func": "int* func0(int lists[][3], int num_lists, int* length) {\n int max_sum = -1;\n int* max_list = NULL;\n for (int i = 0; i < num_lists; i++) {\n int current_sum = 0;\n for (int j = 0; j < 3; j++) {\n current_sum += lists[i][j];\n }\n if (current_sum > max_sum) {\n max_sum = current_sum;\n max_list = lists[i];\n *length = 3;\n }\n }\n return max_list;\n}", + "test": "int main() {\n\n int length;\n\n \n\n int list1[4][3] = {{1,2,3}, {4,5,6}, {10,11,12}, {7,8,9}};\n\n int* max_list1 = func0(list1, 4, &length);\n\n int expected1[3] = {10, 11, 12};\n\n assert(memcmp(max_list1, expected1, sizeof(expected1)) == 0);\n\n \n\n int list2[3][3] = {{3,2,1}, {6,5,4}, {12,11,10}};\n\n int* max_list2 = func0(list2, 3, &length);\n\n int expected2[3] = {12, 11, 10};\n\n assert(memcmp(max_list2, expected2, sizeof(expected2)) == 0);\n\n \n\n int list3[1][3] = {{2,3,1}};\n\n int* max_list3 = func0(list3, 1, &length);\n\n int expected3[3] = {2, 3, 1};\n\n assert(memcmp(max_list3, expected3, sizeof(expected3)) == 0);\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1374 \nlea -0x1(%rsi),%eax\nxor %r8d,%r8d\nmov $0xffffffff,%ecx\nlea (%rax,%rax,2),%rax\nlea 0xc(%rdi,%rax,4),%rsi\nnopl 0x0(%rax)\nmov 0x4(%rdi),%eax\nadd (%rdi),%eax\nadd 0x8(%rdi),%eax\ncmp %eax,%ecx\njge 1367 \nmovl $0x3,(%rdx)\nmov %rdi,%r8\nmov %eax,%ecx\nadd $0xc,%rdi\ncmp %rsi,%rdi\njne 1350 \nmov %r8,%rax\nretq\nxor %r8d,%r8d\nmov %r8,%rax\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1394\nmovsxd rsi, esi\nxor r8d, r8d\nmov ecx, 0FFFFFFFFh\nlea rax, [rsi+rsi*2]\nlea rsi, [rdi+rax*4]\nnop dword ptr [rax+rax+00h]\nloc_1370:\nmov eax, [rdi+4]\nadd eax, [rdi]\nadd eax, [rdi+8]\ncmp eax, ecx\njle short loc_1387\nmov dword ptr [rdx], 3\nmov r8, rdi\nmov ecx, eax\nloc_1387:\nadd rdi, 0Ch\ncmp rdi, rsi\njnz short loc_1370\nmov rax, r8\nretn\nloc_1394:\nxor r8d, r8d\nmov rax, r8\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(_DWORD *a1, int a2, _DWORD *a3)\n{\n _DWORD *v3; // r8\n int v4; // ecx\n _DWORD *v5; // rsi\n int v6; // eax\n\n if ( a2 <= 0 )\n return 0LL;\n v3 = 0LL;\n v4 = -1;\n v5 = &a1[3 * a2];\n do\n {\n v6 = a1[2] + *a1 + a1[1];\n if ( v6 > v4 )\n {\n *a3 = 3;\n v3 = a1;\n v4 = v6;\n }\n a1 += 3;\n }\n while ( a1 != v5 );\n return v3;\n}", + "ida_strip_asm": "sub_1350:\nendbr64\ntest esi, esi\njle short loc_1394\nmovsxd rsi, esi\nxor r8d, r8d\nmov ecx, 0FFFFFFFFh\nlea rax, [rsi+rsi*2]\nlea rsi, [rdi+rax*4]\nnop dword ptr [rax+rax+00h]\nloc_1370:\nmov eax, [rdi+4]\nadd eax, [rdi]\nadd eax, [rdi+8]\ncmp eax, ecx\njle short loc_1387\nmov dword ptr [rdx], 3\nmov r8, rdi\nmov ecx, eax\nloc_1387:\nadd rdi, 0Ch\ncmp rdi, rsi\njnz short loc_1370\nmov rax, r8\nretn\nloc_1394:\nxor r8d, r8d\nmov rax, r8\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1350(_DWORD *a1, int a2, _DWORD *a3)\n{\n _DWORD *v3; // r8\n int v4; // ecx\n _DWORD *v5; // rsi\n int v6; // eax\n\n if ( a2 <= 0 )\n return 0LL;\n v3 = 0LL;\n v4 = -1;\n v5 = &a1[3 * a2];\n do\n {\n v6 = a1[2] + *a1 + a1[1];\n if ( v6 > v4 )\n {\n *a3 = 3;\n v3 = a1;\n v4 = v6;\n }\n a1 += 3;\n }\n while ( a1 != v5 );\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1350(uint32_t *a1, int a2, uint32_t *a3) {\n uint32_t *v3;\n int v4;\n uint32_t *v5;\n int v6;\n if (a2 <= 0) return 0LL;\n v3 = 0LL;\n v4 = -1;\n v5 = &a1[3 * a2];\n do {\n v6 = a1[2] + *a1 + a1[1];\n if (v6 > v4) {\n *a3 = 3;\n v3 = a1;\n v4 = v6;\n }\n a1 += 3;\n } while (a1 != v5);\n return v3;\n}", + "ida_pseudo_norm": "uint32_t *func0(uint32_t *a1, int a2, uint32_t *a3) {\n uint32_t *v3;\n int v4;\n uint32_t *v5;\n int v6;\n if (a2 <= 0) return 0LL;\n v3 = 0LL;\n v4 = -1;\n v5 = &a1[3 * a2];\n do {\n v6 = a1[2] + *a1 + a1[1];\n if (v6 > v4) {\n *a3 = 3;\n v3 = a1;\n v4 = v6;\n }\n a1 += 3;\n } while (a1 != v5);\n return v3;\n}" + }, + { + "index": 806, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *test_str) {\n int cnt = 0;\n int res = 0;\n int length = strlen(test_str);\n for (int idx = 0; idx < length; idx++) {\n if (isupper(test_str[idx])) {\n cnt++;\n } else {\n if (cnt > res) {\n res = cnt;\n }\n cnt = 0;\n }\n }\n if (isupper(test_str[length - 1])) {\n if (cnt > res) {\n res = cnt;\n }\n }\n return res;\n}", + "test": "int main() {\n\n assert(func0(\"GeMKSForGERksISBESt\") == 5);\n\n assert(func0(\"PrECIOusMOVemENTSYT\") == 6);\n\n assert(func0(\"GooGLEFluTTER\") == 4);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmovl $0x0,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\nmov -0x18(%rbp),%rax\nmov %rax,%rdi\ncallq 1070 \nmov %eax,-0x4(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 120f \ncallq 1090 <__ctype_b_loc@plt>\nmov (%rax),%rax\nmov -0x8(%rbp),%edx\nmovslq %edx,%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rdx),%edx\nmovsbq %dl,%rdx\nadd %rdx,%rdx\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x100,%eax\ntest %eax,%eax\nje 11f6 \naddl $0x1,-0x10(%rbp)\njmp 120b \nmov -0x10(%rbp),%eax\ncmp -0xc(%rbp),%eax\njle 1204 \nmov -0x10(%rbp),%eax\nmov %eax,-0xc(%rbp)\nmovl $0x0,-0x10(%rbp)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x4(%rbp),%eax\njl 11bf \ncallq 1090 <__ctype_b_loc@plt>\nmov (%rax),%rax\nmov -0x4(%rbp),%edx\nmovslq %edx,%rdx\nlea -0x1(%rdx),%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rdx),%edx\nmovsbq %dl,%rdx\nadd %rdx,%rdx\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x100,%eax\ntest %eax,%eax\nje 125a \nmov -0x10(%rbp),%eax\ncmp -0xc(%rbp),%eax\njle 125a \nmov -0x10(%rbp),%eax\nmov %eax,-0xc(%rbp)\nmov -0xc(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_8], 0\njmp short loc_120F\nloc_11BF:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_8]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 100h\ntest eax, eax\njz short loc_11F6\nadd [rbp+var_10], 1\njmp short loc_120B\nloc_11F6:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_C]\njle short loc_1204\nmov eax, [rbp+var_10]\nmov [rbp+var_C], eax\nloc_1204:\nmov [rbp+var_10], 0\nloc_120B:\nadd [rbp+var_8], 1\nloc_120F:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njl short loc_11BF\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rcx, [rdx-1]\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 100h\ntest eax, eax\njz short loc_125A\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_C]\njle short loc_125A\nmov eax, [rbp+var_10]\nmov [rbp+var_C], eax\nloc_125A:\nmov eax, [rbp+var_C]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n signed int v2; // [rsp+10h] [rbp-10h]\n signed int v3; // [rsp+14h] [rbp-Ch]\n int i; // [rsp+18h] [rbp-8h]\n int v5; // [rsp+1Ch] [rbp-4h]\n\n v2 = 0;\n v3 = 0;\n v5 = strlen(a1);\n for ( i = 0; i < v5; ++i )\n {\n if ( ((*__ctype_b_loc())[a1[i]] & 0x100) != 0 )\n {\n ++v2;\n }\n else\n {\n if ( v2 > v3 )\n v3 = v2;\n v2 = 0;\n }\n }\n if ( ((*__ctype_b_loc())[a1[v5 - 1]] & 0x100) != 0 && v2 > v3 )\n return (unsigned int)v2;\n return (unsigned int)v3;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_8], 0\njmp short loc_120F\nloc_11BF:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_8]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 100h\ntest eax, eax\njz short loc_11F6\nadd [rbp+var_10], 1\njmp short loc_120B\nloc_11F6:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_C]\njle short loc_1204\nmov eax, [rbp+var_10]\nmov [rbp+var_C], eax\nloc_1204:\nmov [rbp+var_10], 0\nloc_120B:\nadd [rbp+var_8], 1\nloc_120F:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njl short loc_11BF\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rcx, [rdx-1]\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 100h\ntest eax, eax\njz short loc_125A\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_C]\njle short loc_125A\nmov eax, [rbp+var_10]\nmov [rbp+var_C], eax\nloc_125A:\nmov eax, [rbp+var_C]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(const char *a1)\n{\n signed int v2; // [rsp+10h] [rbp-10h]\n signed int v3; // [rsp+14h] [rbp-Ch]\n int i; // [rsp+18h] [rbp-8h]\n int v5; // [rsp+1Ch] [rbp-4h]\n\n v2 = 0;\n v3 = 0;\n v5 = strlen(a1);\n for ( i = 0; i < v5; ++i )\n {\n if ( ((*__ctype_b_loc())[a1[i]] & 0x100) != 0 )\n {\n ++v2;\n }\n else\n {\n if ( v2 > v3 )\n v3 = v2;\n v2 = 0;\n }\n }\n if ( ((*__ctype_b_loc())[a1[v5 - 1]] & 0x100) != 0 && v2 > v3 )\n return (unsigned int)v2;\n return (unsigned int)v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(const char *a1) {\n signed int v2;\n signed int v3;\n int i;\n int v5;\n v2 = 0;\n v3 = 0;\n v5 = strlen(a1);\n for (i = 0; i < v5; ++i) {\n if (((*__ctype_b_loc())[a1[i]] & 256) != 0) {\n ++v2;\n } else {\n if (v2 > v3) v3 = v2;\n v2 = 0;\n }\n }\n if (((*__ctype_b_loc())[a1[v5 - 1]] & 256) != 0 && v2 > v3)\n return (unsigned int)v2;\n return (unsigned int)v3;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n signed int v2;\n signed int v3;\n int i;\n int v5;\n v2 = 0;\n v3 = 0;\n v5 = strlen(a1);\n for (i = 0; i < v5; ++i) {\n if (((*__ctype_b_loc())[a1[i]] & 256) != 0) {\n ++v2;\n } else {\n if (v2 > v3) v3 = v2;\n v2 = 0;\n }\n }\n if (((*__ctype_b_loc())[a1[v5 - 1]] & 256) != 0 && v2 > v3)\n return (unsigned int)v2;\n return (unsigned int)v3;\n}" + }, + { + "index": 806, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *test_str) {\n int cnt = 0;\n int res = 0;\n int length = strlen(test_str);\n for (int idx = 0; idx < length; idx++) {\n if (isupper(test_str[idx])) {\n cnt++;\n } else {\n if (cnt > res) {\n res = cnt;\n }\n cnt = 0;\n }\n }\n if (isupper(test_str[length - 1])) {\n if (cnt > res) {\n res = cnt;\n }\n }\n return res;\n}", + "test": "int main() {\n\n assert(func0(\"GeMKSForGERksISBESt\") == 5);\n\n assert(func0(\"PrECIOusMOVemENTSYT\") == 6);\n\n assert(func0(\"GooGLEFluTTER\") == 4);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%r13\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nlea -0x1(%rcx),%r12\ntest %r12d,%r12d\njle 11d8 \ncallq 1070 <__ctype_b_loc@plt>\nmov (%rax),%rsi\nmov %r13,%rax\nlea -0x1(%r12),%edx\nlea 0x1(%r13,%rdx,1),%rcx\nmov $0x0,%ebp\nmov $0x0,%ebx\njmp 11c8 \ncmp %ebx,%ebp\ncmovl %ebx,%ebp\nmov $0x0,%ebx\nadd $0x1,%rax\ncmp %rcx,%rax\nje 11e2 \nmovsbq (%rax),%rdx\ntestb $0x1,0x1(%rsi,%rdx,2)\nje 11b5 \nadd $0x1,%ebx\njmp 11bf \nmov $0x0,%ebp\nmov $0x0,%ebx\ncallq 1070 <__ctype_b_loc@plt>\nmovslq %r12d,%r12\nmovsbq -0x1(%r13,%r12,1),%rdx\nmov (%rax),%rax\ntestb $0x1,0x1(%rax,%rdx,2)\nje 11ff \ncmp %ebx,%ebp\ncmovl %ebx,%ebp\nmov %ebp,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r13, rdi\ncall _strlen\nmov r12, rax\ntest eax, eax\njle short loc_11EA\ncall ___ctype_b_loc\nmov rsi, [rax]\nmov rax, r13\nlea edx, [r12-1]\nlea rcx, [r13+rdx+1]\nmov ebp, 0\nmov ebx, 0\njmp short loc_11DA\nloc_11C7:\ncmp ebp, ebx\ncmovl ebp, ebx\nmov ebx, 0\nloc_11D1:\nadd rax, 1\ncmp rax, rcx\njz short loc_11F4\nloc_11DA:\nmovsx rdx, byte ptr [rax]\ntest byte ptr [rsi+rdx*2+1], 1\njz short loc_11C7\nadd ebx, 1\njmp short loc_11D1\nloc_11EA:\nmov ebp, 0\nmov ebx, 0\nloc_11F4:\ncall ___ctype_b_loc\nmovsxd r12, r12d\nmovsx rdx, byte ptr [r13+r12-1]\nmov rax, [rax]\ncmp ebp, ebx\ncmovge ebx, ebp\ntest byte ptr [rax+rdx*2+1], 1\ncmovnz ebp, ebx\nmov eax, ebp\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v1; // r12d\n const unsigned __int16 *v2; // rsi\n const char *v3; // rax\n signed int v4; // ebp\n signed int v5; // ebx\n const unsigned __int16 *v6; // rax\n\n v1 = strlen(a1);\n if ( v1 <= 0 )\n {\n v4 = 0;\n v5 = 0;\n }\n else\n {\n v2 = *__ctype_b_loc();\n v3 = a1;\n v4 = 0;\n v5 = 0;\n do\n {\n if ( (v2[*v3] & 0x100) != 0 )\n {\n ++v5;\n }\n else\n {\n if ( v4 < v5 )\n v4 = v5;\n v5 = 0;\n }\n ++v3;\n }\n while ( v3 != &a1[v1 - 1 + 1] );\n }\n v6 = *__ctype_b_loc();\n if ( v4 >= v5 )\n v5 = v4;\n if ( (v6[a1[v1 - 1]] & 0x100) != 0 )\n return (unsigned int)v5;\n return (unsigned int)v4;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r13, rdi\ncall _strlen\nmov r12, rax\ntest eax, eax\njle short loc_11EA\ncall ___ctype_b_loc\nmov rsi, [rax]\nmov rax, r13\nlea edx, [r12-1]\nlea rcx, [r13+rdx+1]\nmov ebp, 0\nmov ebx, 0\njmp short loc_11DA\nloc_11C7:\ncmp ebp, ebx\ncmovl ebp, ebx\nmov ebx, 0\nloc_11D1:\nadd rax, 1\ncmp rax, rcx\njz short loc_11F4\nloc_11DA:\nmovsx rdx, byte ptr [rax]\ntest byte ptr [rsi+rdx*2+1], 1\njz short loc_11C7\nadd ebx, 1\njmp short loc_11D1\nloc_11EA:\nmov ebp, 0\nmov ebx, 0\nloc_11F4:\ncall ___ctype_b_loc\nmovsxd r12, r12d\nmovsx rdx, byte ptr [r13+r12-1]\nmov rax, [rax]\ncmp ebp, ebx\ncmovge ebx, ebp\ntest byte ptr [rax+rdx*2+1], 1\ncmovnz ebp, ebx\nmov eax, ebp\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(const char *a1)\n{\n int v1; // r12d\n const unsigned __int16 *v2; // rsi\n const char *v3; // rax\n signed int v4; // ebp\n signed int v5; // ebx\n const unsigned __int16 *v6; // rax\n\n v1 = strlen(a1);\n if ( v1 <= 0 )\n {\n v4 = 0;\n v5 = 0;\n }\n else\n {\n v2 = *__ctype_b_loc();\n v3 = a1;\n v4 = 0;\n v5 = 0;\n do\n {\n if ( (v2[*v3] & 0x100) != 0 )\n {\n ++v5;\n }\n else\n {\n if ( v4 < v5 )\n v4 = v5;\n v5 = 0;\n }\n ++v3;\n }\n while ( v3 != &a1[v1 - 1 + 1] );\n }\n v6 = *__ctype_b_loc();\n if ( v4 >= v5 )\n v5 = v4;\n if ( (v6[a1[v1 - 1]] & 0x100) != 0 )\n return (unsigned int)v5;\n return (unsigned int)v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(const char *a1) {\n int v1;\n const unsigned short *v2;\n const char *v3;\n signed int v4;\n signed int v5;\n const unsigned short *v6;\n v1 = strlen(a1);\n if (v1 <= 0) {\n v4 = 0;\n v5 = 0;\n } else {\n v2 = *__ctype_b_loc();\n v3 = a1;\n v4 = 0;\n v5 = 0;\n do {\n if ((v2[*v3] & 256) != 0) {\n ++v5;\n } else {\n if (v4 < v5) v4 = v5;\n v5 = 0;\n }\n ++v3;\n } while (v3 != &a1[v1 - 1 + 1]);\n }\n v6 = *__ctype_b_loc();\n if (v4 >= v5) v5 = v4;\n if ((v6[a1[v1 - 1]] & 256) != 0) return (unsigned int)v5;\n return (unsigned int)v4;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v1;\n const unsigned short *v2;\n const char *v3;\n signed int v4;\n signed int v5;\n const unsigned short *v6;\n v1 = strlen(a1);\n if (v1 <= 0) {\n v4 = 0;\n v5 = 0;\n } else {\n v2 = *__ctype_b_loc();\n v3 = a1;\n v4 = 0;\n v5 = 0;\n do {\n if ((v2[*v3] & 256) != 0) {\n ++v5;\n } else {\n if (v4 < v5) v4 = v5;\n v5 = 0;\n }\n ++v3;\n } while (v3 != &a1[v1 - 1 + 1]);\n }\n v6 = *__ctype_b_loc();\n if (v4 >= v5) v5 = v4;\n if ((v6[a1[v1 - 1]] & 256) != 0) return (unsigned int)v5;\n return (unsigned int)v4;\n}" + }, + { + "index": 806, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *test_str) {\n int cnt = 0;\n int res = 0;\n int length = strlen(test_str);\n for (int idx = 0; idx < length; idx++) {\n if (isupper(test_str[idx])) {\n cnt++;\n } else {\n if (cnt > res) {\n res = cnt;\n }\n cnt = 0;\n }\n }\n if (isupper(test_str[length - 1])) {\n if (cnt > res) {\n res = cnt;\n }\n }\n return res;\n}", + "test": "int main() {\n\n assert(func0(\"GeMKSForGERksISBESt\") == 5);\n\n assert(func0(\"PrECIOusMOVemENTSYT\") == 6);\n\n assert(func0(\"GooGLEFluTTER\") == 4);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rdi,%rbp\npush %rbx\nsub $0x8,%rsp\ncallq 1070 \nmov %rax,%rbx\ncallq 1090 <__ctype_b_loc@plt>\nmov (%rax),%rsi\ntest %ebx,%ebx\njle 12b8 \nlea -0x1(%rbx),%edx\nmov %rbp,%rax\nxor %r8d,%r8d\nlea 0x1(%rbp,%rdx,1),%r9\nxor %edx,%edx\njmp 1274 \nnopl 0x0(%rax,%rax,1)\nadd $0x1,%rax\nadd $0x1,%edx\ncmp %rax,%r9\nje 1291 \nmovsbq (%rax),%rcx\ntestb $0x1,0x1(%rsi,%rcx,2)\njne 1268 \ncmp %edx,%r8d\ncmovl %edx,%r8d\nadd $0x1,%rax\nxor %edx,%edx\ncmp %rax,%r9\njne 1274 \nmovslq %ebx,%rbx\nmovsbq -0x1(%rbp,%rbx,1),%rax\ntestb $0x1,0x1(%rsi,%rax,2)\nje 12a8 \ncmp %edx,%r8d\ncmovl %edx,%r8d\nadd $0x8,%rsp\nmov %r8d,%eax\npop %rbx\npop %rbp\nretq\nnopw 0x0(%rax,%rax,1)\nxor %r8d,%r8d\nxor %edx,%edx\njmp 1291 \n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 8\ncall _strlen\nmov rbx, rax\ncall ___ctype_b_loc\nmov r8, [rax]\ntest ebx, ebx\njle short loc_12B0\nlea edx, [rbx-1]\nmov rax, rbp\nxor ecx, ecx\nlea r9, [rbp+rdx+1]\nxor edx, edx\njmp short loc_1274\nloc_1268:\nadd rax, 1\nadd edx, 1\ncmp r9, rax\njz short loc_1290\nloc_1274:\nmovsx rsi, byte ptr [rax]\ntest byte ptr [r8+rsi*2+1], 1\njnz short loc_1268\ncmp ecx, edx\ncmovl ecx, edx\nadd rax, 1\nxor edx, edx\ncmp r9, rax\njnz short loc_1274\nloc_1290:\nmovsxd rbx, ebx\ncmp ecx, edx\nmovsx rax, byte ptr [rbp+rbx-1]\ncmovge edx, ecx\ntest byte ptr [r8+rax*2+1], 1\ncmovnz ecx, edx\nadd rsp, 8\npop rbx\npop rbp\nmov eax, ecx\nretn\nloc_12B0:\nxor ecx, ecx\nxor edx, edx\njmp short loc_1290", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v1; // ebx\n const unsigned __int16 *v2; // r8\n const char *v3; // rax\n signed int v4; // ecx\n __int64 v5; // r9\n signed int v6; // edx\n\n v1 = strlen(a1);\n v2 = *__ctype_b_loc();\n if ( v1 <= 0 )\n {\n v4 = 0;\n v6 = 0;\n }\n else\n {\n v3 = a1;\n v4 = 0;\n v5 = (__int64)&a1[v1 - 1 + 1];\n v6 = 0;\n do\n {\n while ( (v2[*v3] & 0x100) != 0 )\n {\n ++v3;\n ++v6;\n if ( (const char *)v5 == v3 )\n goto LABEL_8;\n }\n if ( v4 < v6 )\n v4 = v6;\n ++v3;\n v6 = 0;\n }\n while ( (const char *)v5 != v3 );\n }\nLABEL_8:\n if ( v4 >= v6 )\n v6 = v4;\n if ( (v2[a1[v1 - 1]] & 0x100) != 0 )\n return (unsigned int)v6;\n return (unsigned int)v4;\n}", + "ida_strip_asm": "sub_1230:\nendbr64\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 8\ncall _strlen\nmov rbx, rax\ncall ___ctype_b_loc\nmov r8, [rax]\ntest ebx, ebx\njle short loc_12B0\nlea edx, [rbx-1]\nmov rax, rbp\nxor ecx, ecx\nlea r9, [rbp+rdx+1]\nxor edx, edx\njmp short loc_1274\nloc_1268:\nadd rax, 1\nadd edx, 1\ncmp r9, rax\njz short loc_1290\nloc_1274:\nmovsx rsi, byte ptr [rax]\ntest byte ptr [r8+rsi*2+1], 1\njnz short loc_1268\ncmp ecx, edx\ncmovl ecx, edx\nadd rax, 1\nxor edx, edx\ncmp r9, rax\njnz short loc_1274\nloc_1290:\nmovsxd rbx, ebx\ncmp ecx, edx\nmovsx rax, byte ptr [rbp+rbx-1]\ncmovge edx, ecx\ntest byte ptr [r8+rax*2+1], 1\ncmovnz ecx, edx\nadd rsp, 8\npop rbx\npop rbp\nmov eax, ecx\nretn\nloc_12B0:\nxor ecx, ecx\nxor edx, edx\njmp short loc_1290", + "ida_strip_pseudo": "__int64 __fastcall sub_1230(const char *a1)\n{\n int v1; // ebx\n const unsigned __int16 *v2; // r8\n const char *v3; // rax\n signed int v4; // ecx\n __int64 v5; // r9\n signed int v6; // edx\n\n v1 = strlen(a1);\n v2 = *__ctype_b_loc();\n if ( v1 <= 0 )\n {\n v4 = 0;\n v6 = 0;\n }\n else\n {\n v3 = a1;\n v4 = 0;\n v5 = (__int64)&a1[v1 - 1 + 1];\n v6 = 0;\n do\n {\n while ( (v2[*v3] & 0x100) != 0 )\n {\n ++v3;\n ++v6;\n if ( (const char *)v5 == v3 )\n goto LABEL_8;\n }\n if ( v4 < v6 )\n v4 = v6;\n ++v3;\n v6 = 0;\n }\n while ( (const char *)v5 != v3 );\n }\nLABEL_8:\n if ( v4 >= v6 )\n v6 = v4;\n if ( (v2[a1[v1 - 1]] & 0x100) != 0 )\n return (unsigned int)v6;\n return (unsigned int)v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1230(const char *a1) {\n int v1;\n const unsigned short *v2;\n const char *v3;\n signed int v4;\n long long v5;\n signed int v6;\n v1 = strlen(a1);\n v2 = *__ctype_b_loc();\n if (v1 <= 0) {\n v4 = 0;\n v6 = 0;\n } else {\n v3 = a1;\n v4 = 0;\n v5 = (long long)&a1[v1 - 1 + 1];\n v6 = 0;\n do {\n while ((v2[*v3] & 256) != 0) {\n ++v3;\n ++v6;\n if ((const char *)v5 == v3) goto LABEL_8;\n }\n if (v4 < v6) v4 = v6;\n ++v3;\n v6 = 0;\n } while ((const char *)v5 != v3);\n }\nLABEL_8:\n if (v4 >= v6) v6 = v4;\n if ((v2[a1[v1 - 1]] & 256) != 0) return (unsigned int)v6;\n return (unsigned int)v4;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v1;\n const unsigned short *v2;\n const char *v3;\n signed int v4;\n long long v5;\n signed int v6;\n v1 = strlen(a1);\n v2 = *__ctype_b_loc();\n if (v1 <= 0) {\n v4 = 0;\n v6 = 0;\n } else {\n v3 = a1;\n v4 = 0;\n v5 = (long long)&a1[v1 - 1 + 1];\n v6 = 0;\n do {\n while ((v2[*v3] & 256) != 0) {\n ++v3;\n ++v6;\n if ((const char *)v5 == v3) goto LABEL_8;\n }\n if (v4 < v6) v4 = v6;\n ++v3;\n v6 = 0;\n } while ((const char *)v5 != v3);\n }\nLABEL_8:\n if (v4 >= v6) v6 = v4;\n if ((v2[a1[v1 - 1]] & 256) != 0) return (unsigned int)v6;\n return (unsigned int)v4;\n}" + }, + { + "index": 806, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *test_str) {\n int cnt = 0;\n int res = 0;\n int length = strlen(test_str);\n for (int idx = 0; idx < length; idx++) {\n if (isupper(test_str[idx])) {\n cnt++;\n } else {\n if (cnt > res) {\n res = cnt;\n }\n cnt = 0;\n }\n }\n if (isupper(test_str[length - 1])) {\n if (cnt > res) {\n res = cnt;\n }\n }\n return res;\n}", + "test": "int main() {\n\n assert(func0(\"GeMKSForGERksISBESt\") == 5);\n\n assert(func0(\"PrECIOusMOVemENTSYT\") == 6);\n\n assert(func0(\"GooGLEFluTTER\") == 4);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rdi,%rbp\npush %rbx\nsub $0x8,%rsp\ncallq 1070 \nmov %rax,%rbx\ncallq 1090 <__ctype_b_loc@plt>\nmov (%rax),%rsi\ntest %ebx,%ebx\njle 12b8 \nlea -0x1(%rbx),%edx\nmov %rbp,%rax\nxor %r8d,%r8d\nlea 0x1(%rbp,%rdx,1),%r9\nxor %edx,%edx\njmp 1274 \nnopl 0x0(%rax,%rax,1)\nadd $0x1,%rax\nadd $0x1,%edx\ncmp %rax,%r9\nje 1291 \nmovsbq (%rax),%rcx\ntestb $0x1,0x1(%rsi,%rcx,2)\njne 1268 \ncmp %edx,%r8d\ncmovl %edx,%r8d\nadd $0x1,%rax\nxor %edx,%edx\ncmp %rax,%r9\njne 1274 \nmovslq %ebx,%rbx\nmovsbq -0x1(%rbp,%rbx,1),%rax\ntestb $0x1,0x1(%rsi,%rax,2)\nje 12a8 \ncmp %edx,%r8d\ncmovl %edx,%r8d\nadd $0x8,%rsp\nmov %r8d,%eax\npop %rbx\npop %rbp\nretq\nnopw 0x0(%rax,%rax,1)\nxor %r8d,%r8d\nxor %edx,%edx\njmp 1291 \n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 8\ncall _strlen\nmov rbx, rax\ncall ___ctype_b_loc\nmov r8, [rax]\ntest ebx, ebx\njle short loc_12B0\nlea edx, [rbx-1]\nmov rax, rbp\nxor ecx, ecx\nlea r9, [rbp+rdx+1]\nxor edx, edx\njmp short loc_1274\nloc_1268:\nadd rax, 1\nadd edx, 1\ncmp r9, rax\njz short loc_1290\nloc_1274:\nmovsx rsi, byte ptr [rax]\ntest byte ptr [r8+rsi*2+1], 1\njnz short loc_1268\ncmp ecx, edx\ncmovl ecx, edx\nadd rax, 1\nxor edx, edx\ncmp r9, rax\njnz short loc_1274\nloc_1290:\nmovsxd rbx, ebx\ncmp ecx, edx\nmovsx rax, byte ptr [rbp+rbx-1]\ncmovge edx, ecx\ntest byte ptr [r8+rax*2+1], 1\ncmovnz ecx, edx\nadd rsp, 8\npop rbx\npop rbp\nmov eax, ecx\nretn\nloc_12B0:\nxor ecx, ecx\nxor edx, edx\njmp short loc_1290", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v1; // ebx\n const unsigned __int16 *v2; // r8\n const char *v3; // rax\n signed int v4; // ecx\n __int64 v5; // r9\n signed int v6; // edx\n\n v1 = strlen(a1);\n v2 = *__ctype_b_loc();\n if ( v1 <= 0 )\n {\n v4 = 0;\n v6 = 0;\n }\n else\n {\n v3 = a1;\n v4 = 0;\n v5 = (__int64)&a1[v1 - 1 + 1];\n v6 = 0;\n do\n {\n while ( (v2[*v3] & 0x100) != 0 )\n {\n ++v3;\n ++v6;\n if ( (const char *)v5 == v3 )\n goto LABEL_8;\n }\n if ( v4 < v6 )\n v4 = v6;\n ++v3;\n v6 = 0;\n }\n while ( (const char *)v5 != v3 );\n }\nLABEL_8:\n if ( v4 >= v6 )\n v6 = v4;\n if ( (v2[a1[v1 - 1]] & 0x100) != 0 )\n return (unsigned int)v6;\n return (unsigned int)v4;\n}", + "ida_strip_asm": "sub_1230:\nendbr64\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 8\ncall _strlen\nmov rbx, rax\ncall ___ctype_b_loc\nmov r8, [rax]\ntest ebx, ebx\njle short loc_12B0\nlea edx, [rbx-1]\nmov rax, rbp\nxor ecx, ecx\nlea r9, [rbp+rdx+1]\nxor edx, edx\njmp short loc_1274\nloc_1268:\nadd rax, 1\nadd edx, 1\ncmp r9, rax\njz short loc_1290\nloc_1274:\nmovsx rsi, byte ptr [rax]\ntest byte ptr [r8+rsi*2+1], 1\njnz short loc_1268\ncmp ecx, edx\ncmovl ecx, edx\nadd rax, 1\nxor edx, edx\ncmp r9, rax\njnz short loc_1274\nloc_1290:\nmovsxd rbx, ebx\ncmp ecx, edx\nmovsx rax, byte ptr [rbp+rbx-1]\ncmovge edx, ecx\ntest byte ptr [r8+rax*2+1], 1\ncmovnz ecx, edx\nadd rsp, 8\npop rbx\npop rbp\nmov eax, ecx\nretn\nloc_12B0:\nxor ecx, ecx\nxor edx, edx\njmp short loc_1290", + "ida_strip_pseudo": "__int64 __fastcall sub_1230(const char *a1)\n{\n int v1; // ebx\n const unsigned __int16 *v2; // r8\n const char *v3; // rax\n signed int v4; // ecx\n __int64 v5; // r9\n signed int v6; // edx\n\n v1 = strlen(a1);\n v2 = *__ctype_b_loc();\n if ( v1 <= 0 )\n {\n v4 = 0;\n v6 = 0;\n }\n else\n {\n v3 = a1;\n v4 = 0;\n v5 = (__int64)&a1[v1 - 1 + 1];\n v6 = 0;\n do\n {\n while ( (v2[*v3] & 0x100) != 0 )\n {\n ++v3;\n ++v6;\n if ( (const char *)v5 == v3 )\n goto LABEL_8;\n }\n if ( v4 < v6 )\n v4 = v6;\n ++v3;\n v6 = 0;\n }\n while ( (const char *)v5 != v3 );\n }\nLABEL_8:\n if ( v4 >= v6 )\n v6 = v4;\n if ( (v2[a1[v1 - 1]] & 0x100) != 0 )\n return (unsigned int)v6;\n return (unsigned int)v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1230(const char *a1) {\n int v1;\n const unsigned short *v2;\n const char *v3;\n signed int v4;\n long long v5;\n signed int v6;\n v1 = strlen(a1);\n v2 = *__ctype_b_loc();\n if (v1 <= 0) {\n v4 = 0;\n v6 = 0;\n } else {\n v3 = a1;\n v4 = 0;\n v5 = (long long)&a1[v1 - 1 + 1];\n v6 = 0;\n do {\n while ((v2[*v3] & 256) != 0) {\n ++v3;\n ++v6;\n if ((const char *)v5 == v3) goto LABEL_8;\n }\n if (v4 < v6) v4 = v6;\n ++v3;\n v6 = 0;\n } while ((const char *)v5 != v3);\n }\nLABEL_8:\n if (v4 >= v6) v6 = v4;\n if ((v2[a1[v1 - 1]] & 256) != 0) return (unsigned int)v6;\n return (unsigned int)v4;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v1;\n const unsigned short *v2;\n const char *v3;\n signed int v4;\n long long v5;\n signed int v6;\n v1 = strlen(a1);\n v2 = *__ctype_b_loc();\n if (v1 <= 0) {\n v4 = 0;\n v6 = 0;\n } else {\n v3 = a1;\n v4 = 0;\n v5 = (long long)&a1[v1 - 1 + 1];\n v6 = 0;\n do {\n while ((v2[*v3] & 256) != 0) {\n ++v3;\n ++v6;\n if ((const char *)v5 == v3) goto LABEL_8;\n }\n if (v4 < v6) v4 = v6;\n ++v3;\n v6 = 0;\n } while ((const char *)v5 != v3);\n }\nLABEL_8:\n if (v4 >= v6) v6 = v4;\n if ((v2[a1[v1 - 1]] & 256) != 0) return (unsigned int)v6;\n return (unsigned int)v4;\n}" + }, + { + "index": 807, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int nums[], int length) {\n for (int i = 0; i < length; i++) {\n if (nums[i] % 2 != 0) {\n return nums[i];\n }\n }\n return -1;\n}", + "test": "int main() {\n\n int nums1[] = {1, 3, 5};\n\n int nums2[] = {2, 4, 1, 3};\n\n int nums3[] = {8, 9, 1};\n\n\n\n assert(func0(nums1, 3) == 1);\n\n assert(func0(nums2, 4) == 1);\n\n assert(func0(nums3, 3) == 9);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11ba \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nand $0x1,%eax\ntest %eax,%eax\nje 11b6 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\njmp 11c7 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1181 \nmov $0xffffffff,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 0\njmp short loc_11BA\nloc_1181:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njz short loc_11B6\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\njmp short loc_11C7\nloc_11B6:\nadd [rbp+var_4], 1\nloc_11BA:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1181\nmov eax, 0FFFFFFFFh\nloc_11C7:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n if ( (*(_DWORD *)(4LL * i + a1) & 1) != 0 )\n return *(unsigned int *)(4LL * i + a1);\n }\n return 0xFFFFFFFFLL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 0\njmp short loc_11BA\nloc_1181:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njz short loc_11B6\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\njmp short loc_11C7\nloc_11B6:\nadd [rbp+var_4], 1\nloc_11BA:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1181\nmov eax, 0FFFFFFFFh\nloc_11C7:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int i; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n if ( (*(_DWORD *)(4LL * i + a1) & 1) != 0 )\n return *(unsigned int *)(4LL * i + a1);\n }\n return 0xFFFFFFFFLL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int i;\n for (i = 0; i < a2; ++i) {\n if ((*(uint32_t *)(4LL * i + a1) & 1) != 0)\n return *(unsigned int *)(4LL * i + a1);\n }\n return 4294967295LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int i;\n for (i = 0; i < a2; ++i) {\n if ((*(uint32_t *)(4LL * i + a1) & 1) != 0)\n return *(unsigned int *)(4LL * i + a1);\n }\n return 4294967295LL;\n}" + }, + { + "index": 807, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int nums[], int length) {\n for (int i = 0; i < length; i++) {\n if (nums[i] % 2 != 0) {\n return nums[i];\n }\n }\n return -1;\n}", + "test": "int main() {\n\n int nums1[] = {1, 3, 5};\n\n int nums2[] = {2, 4, 1, 3};\n\n int nums3[] = {8, 9, 1};\n\n\n\n assert(func0(nums1, 3) == 1);\n\n assert(func0(nums2, 4) == 1);\n\n assert(func0(nums3, 3) == 9);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1194 \nmov %rdi,%rax\nlea -0x1(%rsi),%edx\nlea 0x4(%rdi,%rdx,4),%rcx\nmov (%rax),%edx\ntest $0x1,%dl\njne 1191 \nadd $0x4,%rax\ncmp %rcx,%rax\njne 117c \nmov $0xffffffff,%edx\nmov %edx,%eax\nretq\nmov $0xffffffff,%edx\njmp 1191 \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1193\nmov rax, rdi\nmovsxd rsi, esi\nlea rcx, [rdi+rsi*4]\nloc_117B:\nmov edx, [rax]\ntest dl, 1\njnz short loc_1190\nadd rax, 4\ncmp rax, rcx\njnz short loc_117B\nmov edx, 0FFFFFFFFh\nloc_1190:\nmov eax, edx\nretn\nloc_1193:\nmov edx, 0FFFFFFFFh\njmp short loc_1190", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n unsigned int *v2; // rax\n unsigned int v3; // edx\n\n if ( a2 <= 0 )\n {\n return (unsigned int)-1;\n }\n else\n {\n v2 = a1;\n while ( 1 )\n {\n v3 = *v2;\n if ( (*v2 & 1) != 0 )\n break;\n if ( ++v2 == &a1[a2] )\n return (unsigned int)-1;\n }\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_1193\nmov rax, rdi\nmovsxd rsi, esi\nlea rcx, [rdi+rsi*4]\nloc_117B:\nmov edx, [rax]\ntest dl, 1\njnz short loc_1190\nadd rax, 4\ncmp rax, rcx\njnz short loc_117B\nmov edx, 0FFFFFFFFh\nloc_1190:\nmov eax, edx\nretn\nloc_1193:\nmov edx, 0FFFFFFFFh\njmp short loc_1190", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(unsigned int *a1, int a2)\n{\n unsigned int *v2; // rax\n unsigned int v3; // edx\n\n if ( a2 <= 0 )\n {\n return (unsigned int)-1;\n }\n else\n {\n v2 = a1;\n while ( 1 )\n {\n v3 = *v2;\n if ( (*v2 & 1) != 0 )\n break;\n if ( ++v2 == &a1[a2] )\n return (unsigned int)-1;\n }\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(unsigned int *a1, int a2) {\n unsigned int *v2;\n unsigned int v3;\n if (a2 <= 0) {\n return (unsigned int)-1;\n } else {\n v2 = a1;\n while (1) {\n v3 = *v2;\n if ((*v2 & 1) != 0) break;\n if (++v2 == &a1[a2]) return (unsigned int)-1;\n }\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n unsigned int *v2;\n unsigned int v3;\n if (a2 <= 0) {\n return (unsigned int)-1;\n } else {\n v2 = a1;\n while (1) {\n v3 = *v2;\n if ((*v2 & 1) != 0) break;\n if (++v2 == &a1[a2]) return (unsigned int)-1;\n }\n }\n return v3;\n}" + }, + { + "index": 808, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int test_tup[], int n, int K) {\n bool res = false;\n for (int i = 0; i < n; i++) {\n if (test_tup[i] == K) {\n res = true;\n break;\n }\n }\n return res;\n}", + "test": "int main() {\n\n int arr1[] = {10, 4, 5, 6, 8};\n\n assert(func0(arr1, 5, 6) == true);\n\n\n\n int arr2[] = {1, 2, 3, 4, 5, 6};\n\n assert(func0(arr2, 6, 7) == false);\n\n\n\n int arr3[] = {7, 8, 9, 44, 11, 12};\n\n assert(func0(arr3, 6, 11) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmovb $0x0,-0x5(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11ad \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x20(%rbp)\njne 11a9 \nmovb $0x1,-0x5(%rbp)\njmp 11b5 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1188 \nmovzbl -0x5(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_5], 0\nmov [rbp+var_4], 0\njmp short loc_11AD\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njnz short loc_11A9\nmov [rbp+var_5], 1\njmp short loc_11B5\nloc_11A9:\nadd [rbp+var_4], 1\nloc_11AD:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nloc_11B5:\nmovzx eax, [rbp+var_5]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n unsigned __int8 v4; // [rsp+1Bh] [rbp-5h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( a3 == *(_DWORD *)(4LL * i + a1) )\n return 1;\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_5], 0\nmov [rbp+var_4], 0\njmp short loc_11AD\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njnz short loc_11A9\nmov [rbp+var_5], 1\njmp short loc_11B5\nloc_11A9:\nadd [rbp+var_4], 1\nloc_11AD:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nloc_11B5:\nmovzx eax, [rbp+var_5]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n unsigned __int8 v4; // [rsp+1Bh] [rbp-5h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( a3 == *(_DWORD *)(4LL * i + a1) )\n return 1;\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n unsigned char v4;\n int i;\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n if (a3 == *(uint32_t *)(4LL * i + a1)) return 1;\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n unsigned char v4;\n int i;\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n if (a3 == *(uint32_t *)(4LL * i + a1)) return 1;\n }\n return v4;\n}" + }, + { + "index": 808, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int test_tup[], int n, int K) {\n bool res = false;\n for (int i = 0; i < n; i++) {\n if (test_tup[i] == K) {\n res = true;\n break;\n }\n }\n return res;\n}", + "test": "int main() {\n\n int arr1[] = {10, 4, 5, 6, 8};\n\n assert(func0(arr1, 5, 6) == true);\n\n\n\n int arr2[] = {1, 2, 3, 4, 5, 6};\n\n assert(func0(arr2, 6, 7) == false);\n\n\n\n int arr3[] = {7, 8, 9, 44, 11, 12};\n\n assert(func0(arr3, 6, 11) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 118f \nmov %rdi,%rax\nlea -0x1(%rsi),%ecx\nlea 0x4(%rdi,%rcx,4),%rcx\ncmp %edx,(%rax)\nje 1195 \nadd $0x4,%rax\ncmp %rcx,%rax\njne 117c \nmov $0x0,%eax\nretq\nmov $0x0,%eax\nretq\nmov $0x1,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_118E\nmov rax, rdi\nmovsxd rsi, esi\nlea rcx, [rdi+rsi*4]\nloc_117B:\ncmp [rax], edx\njz short loc_1194\nadd rax, 4\ncmp rax, rcx\njnz short loc_117B\nmov eax, 0\nretn\nloc_118E:\nmov eax, 0\nretn\nloc_1194:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2, int a3)\n{\n _DWORD *v3; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v3 = a1;\n while ( *v3 != a3 )\n {\n if ( ++v3 == &a1[a2] )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_118E\nmov rax, rdi\nmovsxd rsi, esi\nlea rcx, [rdi+rsi*4]\nloc_117B:\ncmp [rax], edx\njz short loc_1194\nadd rax, 4\ncmp rax, rcx\njnz short loc_117B\nmov eax, 0\nretn\nloc_118E:\nmov eax, 0\nretn\nloc_1194:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2, int a3)\n{\n _DWORD *v3; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v3 = a1;\n while ( *v3 != a3 )\n {\n if ( ++v3 == &a1[a2] )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2, int a3) {\n uint32_t *v3;\n if (a2 <= 0) return 0LL;\n v3 = a1;\n while (*v3 != a3) {\n if (++v3 == &a1[a2]) return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2, int a3) {\n uint32_t *v3;\n if (a2 <= 0) return 0LL;\n v3 = a1;\n while (*v3 != a3) {\n if (++v3 == &a1[a2]) return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": 809, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int test_tup1[], int test_tup2[], int size) {\n bool res = true;\n for (int i = 0; i < size; i++) {\n if (!(test_tup1[i] > test_tup2[i])) {\n res = false;\n break;\n }\n }\n return res;\n}", + "test": "int main() {\n\n int tup1_1[] = {1, 2, 3};\n\n int tup2_1[] = {2, 3, 4};\n\n assert(func0(tup1_1, tup2_1, 3) == false);\n\n\n\n int tup1_2[] = {4, 5, 6};\n\n int tup2_2[] = {3, 4, 5};\n\n assert(func0(tup1_2, tup2_2, 3) == true);\n\n\n\n int tup1_3[] = {11, 12, 13};\n\n int tup2_3[] = {10, 11, 12};\n\n assert(func0(tup1_3, tup2_3, 3) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %edx,-0x24(%rbp)\nmovb $0x1,-0x5(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11c3 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x20(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njg 11bf \nmovb $0x0,-0x5(%rbp)\njmp 11cb \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x24(%rbp),%eax\njl 1189 \nmovzbl -0x5(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_5], 1\nmov [rbp+var_4], 0\njmp short loc_11C3\nloc_1189:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njg short loc_11BF\nmov [rbp+var_5], 0\njmp short loc_11CB\nloc_11BF:\nadd [rbp+var_4], 1\nloc_11C3:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_24]\njl short loc_1189\nloc_11CB:\nmovzx eax, [rbp+var_5]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n unsigned __int8 v4; // [rsp+1Fh] [rbp-5h]\n int i; // [rsp+20h] [rbp-4h]\n\n v4 = 1;\n for ( i = 0; i < a3; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) <= *(_DWORD *)(4LL * i + a2) )\n return 0;\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_5], 1\nmov [rbp+var_4], 0\njmp short loc_11C3\nloc_1189:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njg short loc_11BF\nmov [rbp+var_5], 0\njmp short loc_11CB\nloc_11BF:\nadd [rbp+var_4], 1\nloc_11C3:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_24]\njl short loc_1189\nloc_11CB:\nmovzx eax, [rbp+var_5]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, int a3)\n{\n unsigned __int8 v4; // [rsp+1Fh] [rbp-5h]\n int i; // [rsp+20h] [rbp-4h]\n\n v4 = 1;\n for ( i = 0; i < a3; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) <= *(_DWORD *)(4LL * i + a2) )\n return 0;\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, int a3) {\n unsigned char v4;\n int i;\n v4 = 1;\n for (i = 0; i < a3; ++i) {\n if (*(uint32_t *)(4LL * i + a1) <= *(uint32_t *)(4LL * i + a2)) return 0;\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3) {\n unsigned char v4;\n int i;\n v4 = 1;\n for (i = 0; i < a3; ++i) {\n if (*(uint32_t *)(4LL * i + a1) <= *(uint32_t *)(4LL * i + a2)) return 0;\n }\n return v4;\n}" + }, + { + "index": 809, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int test_tup1[], int test_tup2[], int size) {\n bool res = true;\n for (int i = 0; i < size; i++) {\n if (!(test_tup1[i] > test_tup2[i])) {\n res = false;\n break;\n }\n }\n return res;\n}", + "test": "int main() {\n\n int tup1_1[] = {1, 2, 3};\n\n int tup2_1[] = {2, 3, 4};\n\n assert(func0(tup1_1, tup2_1, 3) == false);\n\n\n\n int tup1_2[] = {4, 5, 6};\n\n int tup2_2[] = {3, 4, 5};\n\n assert(func0(tup1_2, tup2_2, 3) == true);\n\n\n\n int tup1_3[] = {11, 12, 13};\n\n int tup2_3[] = {10, 11, 12};\n\n assert(func0(tup1_3, tup2_3, 3) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edx,%edx\njle 1195 \nlea -0x1(%rdx),%ecx\nmov $0x0,%eax\njmp 117e \nmov %rdx,%rax\nmov (%rsi,%rax,4),%edx\ncmp %edx,(%rdi,%rax,4)\njle 119b \nlea 0x1(%rax),%rdx\ncmp %rcx,%rax\njne 117b \nmov $0x1,%eax\nretq\nmov $0x1,%eax\nretq\nmov $0x0,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest edx, edx\njle short loc_1194\nmovsxd rdx, edx\nshl rdx, 2\nmov eax, 0\nloc_117D:\nmov ecx, [rsi+rax]\ncmp [rdi+rax], ecx\njle short loc_119A\nadd rax, 4\ncmp rax, rdx\njnz short loc_117D\nmov eax, 1\nretn\nloc_1194:\nmov eax, 1\nretn\nloc_119A:\nmov eax, 0\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n __int64 v3; // rdx\n __int64 v4; // rax\n\n if ( a3 <= 0 )\n return 1LL;\n v3 = 4LL * a3;\n v4 = 0LL;\n while ( *(_DWORD *)(a1 + v4) > *(_DWORD *)(a2 + v4) )\n {\n v4 += 4LL;\n if ( v4 == v3 )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest edx, edx\njle short loc_1194\nmovsxd rdx, edx\nshl rdx, 2\nmov eax, 0\nloc_117D:\nmov ecx, [rsi+rax]\ncmp [rdi+rax], ecx\njle short loc_119A\nadd rax, 4\ncmp rax, rdx\njnz short loc_117D\nmov eax, 1\nretn\nloc_1194:\nmov eax, 1\nretn\nloc_119A:\nmov eax, 0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, int a3)\n{\n __int64 v3; // rdx\n __int64 v4; // rax\n\n if ( a3 <= 0 )\n return 1LL;\n v3 = 4LL * a3;\n v4 = 0LL;\n while ( *(_DWORD *)(a1 + v4) > *(_DWORD *)(a2 + v4) )\n {\n v4 += 4LL;\n if ( v4 == v3 )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, int a3) {\n long long v3;\n long long v4;\n if (a3 <= 0) return 1LL;\n v3 = 4LL * a3;\n v4 = 0LL;\n while (*(uint32_t *)(a1 + v4) > *(uint32_t *)(a2 + v4)) {\n v4 += 4LL;\n if (v4 == v3) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3) {\n long long v3;\n long long v4;\n if (a3 <= 0) return 1LL;\n v3 = 4LL * a3;\n v4 = 0LL;\n while (*(uint32_t *)(a1 + v4) > *(uint32_t *)(a2 + v4)) {\n v4 += 4LL;\n if (v4 == v3) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 810, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(int a, int b, int c, int d) {\n int total = 0;\n if (a > 0) total += a;\n if (b > 0) total += b;\n if (c > 0) total += c;\n if (d > 0) total += d;\n char* result = malloc((total + 1) * sizeof(char));\n if (!result) {\n perror(\"Failed to allocate memory\");\n exit(EXIT_FAILURE);\n }\n int index = 0;\n for (int i = 0; i < a; i++) {\n result[index++] = 'p';\n }\n for (int i = 0; i < b; i++) {\n result[index++] = 'q';\n }\n for (int i = 0; i < c; i++) {\n result[index++] = 'r';\n }\n for (int i = 0; i < d; i++) {\n result[index++] = 's';\n }\n result[index] = '\\0';\n return result;\n}", + "test": "int main() {\n\n char* res1 = func0(4, 2, 0, -2);\n\n assert(strcmp(res1, \"ppppqq\") == 0);\n\n free(res1);\n\n\n\n char* res2 = func0(0, 1, 2, 3);\n\n assert(strcmp(res2, \"qrrsss\") == 0);\n\n free(res2);\n\n\n\n char* res3 = func0(11, 15, 12, 23);\n\n char expected3[11 + 15 + 12 + 23 + 1];\n\n int idx = 0;\n\n for(int i = 0; i < 11; i++) expected3[idx++] = 'p';\n\n for(int i = 0; i < 15; i++) expected3[idx++] = 'q';\n\n for(int i = 0; i < 12; i++) expected3[idx++] = 'r';\n\n for(int i = 0; i < 23; i++) expected3[idx++] = 's';\n\n expected3[idx] = '\\0';\n\n assert(strcmp(res3, expected3) == 0);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %edi,-0x24(%rbp)\nmov %esi,-0x28(%rbp)\nmov %edx,-0x2c(%rbp)\nmov %ecx,-0x30(%rbp)\nmovl $0x0,-0x20(%rbp)\ncmpl $0x0,-0x24(%rbp)\njle 1234 \nmov -0x24(%rbp),%eax\nadd %eax,-0x20(%rbp)\ncmpl $0x0,-0x28(%rbp)\njle 1240 \nmov -0x28(%rbp),%eax\nadd %eax,-0x20(%rbp)\ncmpl $0x0,-0x2c(%rbp)\njle 124c \nmov -0x2c(%rbp),%eax\nadd %eax,-0x20(%rbp)\ncmpl $0x0,-0x30(%rbp)\njle 1258 \nmov -0x30(%rbp),%eax\nadd %eax,-0x20(%rbp)\nmov -0x20(%rbp),%eax\nadd $0x1,%eax\ncltq\nmov %rax,%rdi\ncallq 10f0 \nmov %rax,-0x8(%rbp)\ncmpq $0x0,-0x8(%rbp)\njne 1289 \nlea 0xd8e(%rip),%rdi\ncallq 1100 \nmov $0x1,%edi\ncallq 1110 \nmovl $0x0,-0x1c(%rbp)\nmovl $0x0,-0x18(%rbp)\njmp 12b3 \nmov -0x1c(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x1c(%rbp)\nmovslq %eax,%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmovb $0x70,(%rax)\naddl $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%eax\ncmp -0x24(%rbp),%eax\njl 1299 \nmovl $0x0,-0x14(%rbp)\njmp 12de \nmov -0x1c(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x1c(%rbp)\nmovslq %eax,%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmovb $0x71,(%rax)\naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\ncmp -0x28(%rbp),%eax\njl 12c4 \nmovl $0x0,-0x10(%rbp)\njmp 1309 \nmov -0x1c(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x1c(%rbp)\nmovslq %eax,%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmovb $0x72,(%rax)\naddl $0x1,-0x10(%rbp)\nmov -0x10(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 12ef \nmovl $0x0,-0xc(%rbp)\njmp 1334 \nmov -0x1c(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x1c(%rbp)\nmovslq %eax,%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmovb $0x73,(%rax)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x30(%rbp),%eax\njl 131a \nmov -0x1c(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmovb $0x0,(%rax)\nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_24], edi\nmov [rbp+var_28], esi\nmov [rbp+var_2C], edx\nmov [rbp+var_30], ecx\nmov [rbp+var_20], 0\ncmp [rbp+var_24], 0\njle short loc_1234\nmov eax, [rbp+var_24]\nadd [rbp+var_20], eax\nloc_1234:\ncmp [rbp+var_28], 0\njle short loc_1240\nmov eax, [rbp+var_28]\nadd [rbp+var_20], eax\nloc_1240:\ncmp [rbp+var_2C], 0\njle short loc_124C\nmov eax, [rbp+var_2C]\nadd [rbp+var_20], eax\nloc_124C:\ncmp [rbp+var_30], 0\njle short loc_1258\nmov eax, [rbp+var_30]\nadd [rbp+var_20], eax\nloc_1258:\nmov eax, [rbp+var_20]\nadd eax, 1\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\ncmp [rbp+var_8], 0\njnz short loc_128C\nlea rax, s; \"Failed to allocate memory\"\nmov rdi, rax; s\ncall _perror\nmov edi, 1; status\ncall _exit\nloc_128C:\nmov [rbp+var_1C], 0\nmov [rbp+var_18], 0\njmp short loc_12B6\nloc_129C:\nmov eax, [rbp+var_1C]\nlea edx, [rax+1]\nmov [rbp+var_1C], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov byte ptr [rax], 70h ; 'p'\nadd [rbp+var_18], 1\nloc_12B6:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_24]\njl short loc_129C\nmov [rbp+var_14], 0\njmp short loc_12E1\nloc_12C7:\nmov eax, [rbp+var_1C]\nlea edx, [rax+1]\nmov [rbp+var_1C], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov byte ptr [rax], 71h ; 'q'\nadd [rbp+var_14], 1\nloc_12E1:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_28]\njl short loc_12C7\nmov [rbp+var_10], 0\njmp short loc_130C\nloc_12F2:\nmov eax, [rbp+var_1C]\nlea edx, [rax+1]\nmov [rbp+var_1C], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov byte ptr [rax], 72h ; 'r'\nadd [rbp+var_10], 1\nloc_130C:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_2C]\njl short loc_12F2\nmov [rbp+var_C], 0\njmp short loc_1337\nloc_131D:\nmov eax, [rbp+var_1C]\nlea edx, [rax+1]\nmov [rbp+var_1C], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov byte ptr [rax], 73h ; 's'\nadd [rbp+var_C], 1\nloc_1337:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_30]\njl short loc_131D\nmov eax, [rbp+var_1C]\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(int a1, int a2, int a3, int a4)\n{\n int v4; // eax\n int v5; // eax\n int v6; // eax\n int v7; // eax\n int v11; // [rsp+10h] [rbp-20h]\n int v12; // [rsp+14h] [rbp-1Ch]\n int i; // [rsp+18h] [rbp-18h]\n int j; // [rsp+1Ch] [rbp-14h]\n int k; // [rsp+20h] [rbp-10h]\n int m; // [rsp+24h] [rbp-Ch]\n _BYTE *v17; // [rsp+28h] [rbp-8h]\n\n v11 = 0;\n if ( a1 > 0 )\n v11 = a1;\n if ( a2 > 0 )\n v11 += a2;\n if ( a3 > 0 )\n v11 += a3;\n if ( a4 > 0 )\n v11 += a4;\n v17 = malloc(v11 + 1);\n if ( !v17 )\n {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v12 = 0;\n for ( i = 0; i < a1; ++i )\n {\n v4 = v12++;\n v17[v4] = 112;\n }\n for ( j = 0; j < a2; ++j )\n {\n v5 = v12++;\n v17[v5] = 113;\n }\n for ( k = 0; k < a3; ++k )\n {\n v6 = v12++;\n v17[v6] = 114;\n }\n for ( m = 0; m < a4; ++m )\n {\n v7 = v12++;\n v17[v7] = 115;\n }\n v17[v12] = 0;\n return v17;\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_24], edi\nmov [rbp+var_28], esi\nmov [rbp+var_2C], edx\nmov [rbp+var_30], ecx\nmov [rbp+var_20], 0\ncmp [rbp+var_24], 0\njle short loc_1234\nmov eax, [rbp+var_24]\nadd [rbp+var_20], eax\nloc_1234:\ncmp [rbp+var_28], 0\njle short loc_1240\nmov eax, [rbp+var_28]\nadd [rbp+var_20], eax\nloc_1240:\ncmp [rbp+var_2C], 0\njle short loc_124C\nmov eax, [rbp+var_2C]\nadd [rbp+var_20], eax\nloc_124C:\ncmp [rbp+var_30], 0\njle short loc_1258\nmov eax, [rbp+var_30]\nadd [rbp+var_20], eax\nloc_1258:\nmov eax, [rbp+var_20]\nadd eax, 1\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\ncmp [rbp+var_8], 0\njnz short loc_128C\nlea rax, s; \"Failed to allocate memory\"\nmov rdi, rax; s\ncall _perror\nmov edi, 1; status\ncall _exit\nloc_128C:\nmov [rbp+var_1C], 0\nmov [rbp+var_18], 0\njmp short loc_12B6\nloc_129C:\nmov eax, [rbp+var_1C]\nlea edx, [rax+1]\nmov [rbp+var_1C], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov byte ptr [rax], 70h ; 'p'\nadd [rbp+var_18], 1\nloc_12B6:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_24]\njl short loc_129C\nmov [rbp+var_14], 0\njmp short loc_12E1\nloc_12C7:\nmov eax, [rbp+var_1C]\nlea edx, [rax+1]\nmov [rbp+var_1C], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov byte ptr [rax], 71h ; 'q'\nadd [rbp+var_14], 1\nloc_12E1:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_28]\njl short loc_12C7\nmov [rbp+var_10], 0\njmp short loc_130C\nloc_12F2:\nmov eax, [rbp+var_1C]\nlea edx, [rax+1]\nmov [rbp+var_1C], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov byte ptr [rax], 72h ; 'r'\nadd [rbp+var_10], 1\nloc_130C:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_2C]\njl short loc_12F2\nmov [rbp+var_C], 0\njmp short loc_1337\nloc_131D:\nmov eax, [rbp+var_1C]\nlea edx, [rax+1]\nmov [rbp+var_1C], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov byte ptr [rax], 73h ; 's'\nadd [rbp+var_C], 1\nloc_1337:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_30]\njl short loc_131D\nmov eax, [rbp+var_1C]\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1209(int a1, int a2, int a3, int a4)\n{\n int v4; // eax\n int v5; // eax\n int v6; // eax\n int v7; // eax\n int v11; // [rsp+10h] [rbp-20h]\n int v12; // [rsp+14h] [rbp-1Ch]\n int i; // [rsp+18h] [rbp-18h]\n int j; // [rsp+1Ch] [rbp-14h]\n int k; // [rsp+20h] [rbp-10h]\n int m; // [rsp+24h] [rbp-Ch]\n _BYTE *v17; // [rsp+28h] [rbp-8h]\n\n v11 = 0;\n if ( a1 > 0 )\n v11 = a1;\n if ( a2 > 0 )\n v11 += a2;\n if ( a3 > 0 )\n v11 += a3;\n if ( a4 > 0 )\n v11 += a4;\n v17 = malloc(v11 + 1);\n if ( !v17 )\n {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v12 = 0;\n for ( i = 0; i < a1; ++i )\n {\n v4 = v12++;\n v17[v4] = 112;\n }\n for ( j = 0; j < a2; ++j )\n {\n v5 = v12++;\n v17[v5] = 113;\n }\n for ( k = 0; k < a3; ++k )\n {\n v6 = v12++;\n v17[v6] = 114;\n }\n for ( m = 0; m < a4; ++m )\n {\n v7 = v12++;\n v17[v7] = 115;\n }\n v17[v12] = 0;\n return v17;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1209(int a1, int a2, int a3, int a4) {\n int v4;\n int v5;\n int v6;\n int v7;\n int v11;\n int v12;\n int i;\n int j;\n int k;\n int m;\n uint8_t *v17;\n v11 = 0;\n if (a1 > 0) v11 = a1;\n if (a2 > 0) v11 += a2;\n if (a3 > 0) v11 += a3;\n if (a4 > 0) v11 += a4;\n v17 = malloc(v11 + 1);\n if (!v17) {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v12 = 0;\n for (i = 0; i < a1; ++i) {\n v4 = v12++;\n v17[v4] = 112;\n }\n for (j = 0; j < a2; ++j) {\n v5 = v12++;\n v17[v5] = 113;\n }\n for (k = 0; k < a3; ++k) {\n v6 = v12++;\n v17[v6] = 114;\n }\n for (m = 0; m < a4; ++m) {\n v7 = v12++;\n v17[v7] = 115;\n }\n v17[v12] = 0;\n return v17;\n}", + "ida_pseudo_norm": "uint8_t *func0(int a1, int a2, int a3, int a4) {\n int v4;\n int v5;\n int v6;\n int v7;\n int v11;\n int v12;\n int i;\n int j;\n int k;\n int m;\n uint8_t *v17;\n v11 = 0;\n if (a1 > 0) v11 = a1;\n if (a2 > 0) v11 += a2;\n if (a3 > 0) v11 += a3;\n if (a4 > 0) v11 += a4;\n v17 = malloc(v11 + 1);\n if (!v17) {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v12 = 0;\n for (i = 0; i < a1; ++i) {\n v4 = v12++;\n v17[v4] = 112;\n }\n for (j = 0; j < a2; ++j) {\n v5 = v12++;\n v17[v5] = 113;\n }\n for (k = 0; k < a3; ++k) {\n v6 = v12++;\n v17[v6] = 114;\n }\n for (m = 0; m < a4; ++m) {\n v7 = v12++;\n v17[v7] = 115;\n }\n v17[v12] = 0;\n return v17;\n}" + }, + { + "index": 810, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(int a, int b, int c, int d) {\n int total = 0;\n if (a > 0) total += a;\n if (b > 0) total += b;\n if (c > 0) total += c;\n if (d > 0) total += d;\n char* result = malloc((total + 1) * sizeof(char));\n if (!result) {\n perror(\"Failed to allocate memory\");\n exit(EXIT_FAILURE);\n }\n int index = 0;\n for (int i = 0; i < a; i++) {\n result[index++] = 'p';\n }\n for (int i = 0; i < b; i++) {\n result[index++] = 'q';\n }\n for (int i = 0; i < c; i++) {\n result[index++] = 'r';\n }\n for (int i = 0; i < d; i++) {\n result[index++] = 's';\n }\n result[index] = '\\0';\n return result;\n}", + "test": "int main() {\n\n char* res1 = func0(4, 2, 0, -2);\n\n assert(strcmp(res1, \"ppppqq\") == 0);\n\n free(res1);\n\n\n\n char* res2 = func0(0, 1, 2, 3);\n\n assert(strcmp(res2, \"qrrsss\") == 0);\n\n free(res2);\n\n\n\n char* res3 = func0(11, 15, 12, 23);\n\n char expected3[11 + 15 + 12 + 23 + 1];\n\n int idx = 0;\n\n for(int i = 0; i < 11; i++) expected3[idx++] = 'p';\n\n for(int i = 0; i < 15; i++) expected3[idx++] = 'q';\n\n for(int i = 0; i < 12; i++) expected3[idx++] = 'r';\n\n for(int i = 0; i < 23; i++) expected3[idx++] = 's';\n\n expected3[idx] = '\\0';\n\n assert(strcmp(res3, expected3) == 0);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %edi,%ebx\nmov %esi,%r13d\nmov %edx,%r12d\nmov %ecx,%ebp\ntest %edi,%edi\nmov $0x0,%edi\ncmovns %ebx,%edi\nlea (%rdi,%rsi,1),%eax\ntest %esi,%esi\ncmovg %eax,%edi\nlea (%rdi,%rdx,1),%eax\ntest %edx,%edx\ncmovg %eax,%edi\nlea (%rdi,%rcx,1),%eax\ntest %ecx,%ecx\ncmovg %eax,%edi\nadd $0x1,%edi\nmovslq %edi,%rdi\ncallq 10f0 \ntest %rax,%rax\nje 1305 \ntest %ebx,%ebx\njle 12fb \nmov %rax,%rdx\nlea -0x1(%rbx),%ecx\nlea 0x1(%rax,%rcx,1),%rcx\nmovb $0x70,(%rdx)\nadd $0x1,%rdx\ncmp %rcx,%rdx\njne 126a \ntest %r13d,%r13d\njle 129d \nmovslq %ebx,%rsi\nlea (%rax,%rsi,1),%rdx\nlea -0x1(%r13),%ecx\nlea 0x1(%rax,%rcx,1),%rcx\nadd %rsi,%rcx\nmovb $0x71,(%rdx)\nadd $0x1,%rdx\ncmp %rcx,%rdx\njne 128e \nadd %r13d,%ebx\ntest %r12d,%r12d\njle 12c5 \nmovslq %ebx,%rsi\nlea (%rax,%rsi,1),%rdx\nlea -0x1(%r12),%ecx\nlea 0x1(%rax,%rcx,1),%rcx\nadd %rsi,%rcx\nmovb $0x72,(%rdx)\nadd $0x1,%rdx\ncmp %rcx,%rdx\njne 12b6 \nadd %r12d,%ebx\ntest %ebp,%ebp\njle 12e9 \nmovslq %ebx,%rsi\nlea (%rax,%rsi,1),%rdx\nlea -0x1(%rbp),%ecx\nlea 0x1(%rax,%rcx,1),%rcx\nadd %rsi,%rcx\nmovb $0x73,(%rdx)\nadd $0x1,%rdx\ncmp %rcx,%rdx\njne 12db \nadd %ebp,%ebx\nmovslq %ebx,%rbx\nmovb $0x0,(%rax,%rbx,1)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nmov $0x0,%ebx\njmpq 1276 \nlea 0xcf8(%rip),%rdi\ncallq 1100 \nmov $0x1,%edi\ncallq 1110 \n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov ebx, edi\nmov r13d, esi\nmov r12d, edx\nmov ebp, ecx\ntest edi, edi\nmov edi, 0\ncmovns edi, ebx\nlea eax, [rdi+rsi]\ntest esi, esi\ncmovg edi, eax\nlea eax, [rdi+rdx]\ntest edx, edx\ncmovg edi, eax\nlea eax, [rdi+rcx]\ntest ecx, ecx\ncmovg edi, eax\nadd edi, 1\nmovsxd rdi, edi; size\ncall _malloc\ntest rax, rax\njz loc_12FD\nmov rdx, rax\nmovsxd rcx, ebx\nadd rcx, rax\ntest ebx, ebx\njle loc_12F3\nloc_1268:\nmov byte ptr [rax], 70h ; 'p'\nadd rax, 1\ncmp rax, rcx\njnz short loc_1268\nloc_1274:\ntest r13d, r13d\njle short loc_1298\nmovsxd rsi, ebx\nlea rax, [rdx+rsi]\nmovsxd rcx, r13d\nadd rcx, rdx\nadd rcx, rsi\nloc_1289:\nmov byte ptr [rax], 71h ; 'q'\nadd rax, 1\ncmp rax, rcx\njnz short loc_1289\nadd ebx, r13d\nloc_1298:\ntest r12d, r12d\njle short loc_12BC\nmovsxd rsi, ebx\nlea rax, [rdx+rsi]\nmovsxd rcx, r12d\nadd rcx, rdx\nadd rcx, rsi\nloc_12AD:\nmov byte ptr [rax], 72h ; 'r'\nadd rax, 1\ncmp rax, rcx\njnz short loc_12AD\nadd ebx, r12d\nloc_12BC:\ntest ebp, ebp\njle short loc_12DE\nmovsxd rsi, ebx\nlea rax, [rdx+rsi]\nmovsxd rcx, ebp\nadd rcx, rdx\nadd rcx, rsi\nloc_12D0:\nmov byte ptr [rax], 73h ; 's'\nadd rax, 1\ncmp rax, rcx\njnz short loc_12D0\nadd ebx, ebp\nloc_12DE:\nmovsxd rbx, ebx\nmov byte ptr [rdx+rbx], 0\nmov rax, rdx\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_12F3:\nmov ebx, 0\njmp loc_1274\nloc_12FD:\nlea rdi, s; \"Failed to allocate memory\"\ncall _perror\nmov edi, 1; status\ncall _exit", + "ida_pseudo": "_BYTE *__fastcall func0(int a1, int a2, int a3, int a4)\n{\n int v4; // ebx\n bool v7; // sf\n int v8; // edi\n _BYTE *v9; // rax\n _BYTE *v10; // rdx\n _BYTE *v11; // rcx\n _BYTE *v12; // rax\n _BYTE *v13; // rax\n _BYTE *v14; // rax\n\n v4 = a1;\n v7 = a1 < 0;\n v8 = 0;\n if ( !v7 )\n v8 = v4;\n if ( a2 > 0 )\n v8 += a2;\n if ( a3 > 0 )\n v8 += a3;\n if ( a4 > 0 )\n v8 += a4;\n v9 = malloc(v8 + 1);\n if ( !v9 )\n {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v10 = v9;\n v11 = &v9[v4];\n if ( v4 <= 0 )\n {\n v4 = 0;\n }\n else\n {\n do\n *v9++ = 112;\n while ( v9 != v11 );\n }\n if ( a2 > 0 )\n {\n v12 = &v10[v4];\n do\n *v12++ = 113;\n while ( v12 != &v10[a2 + v4] );\n v4 += a2;\n }\n if ( a3 > 0 )\n {\n v13 = &v10[v4];\n do\n *v13++ = 114;\n while ( v13 != &v10[a3 + v4] );\n v4 += a3;\n }\n if ( a4 > 0 )\n {\n v14 = &v10[v4];\n do\n *v14++ = 115;\n while ( v14 != &v10[a4 + v4] );\n v4 += a4;\n }\n v10[v4] = 0;\n return v10;\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov ebx, edi\nmov r13d, esi\nmov r12d, edx\nmov ebp, ecx\ntest edi, edi\nmov edi, 0\ncmovns edi, ebx\nlea eax, [rdi+rsi]\ntest esi, esi\ncmovg edi, eax\nlea eax, [rdi+rdx]\ntest edx, edx\ncmovg edi, eax\nlea eax, [rdi+rcx]\ntest ecx, ecx\ncmovg edi, eax\nadd edi, 1\nmovsxd rdi, edi; size\ncall _malloc\ntest rax, rax\njz loc_12FD\nmov rdx, rax\nmovsxd rcx, ebx\nadd rcx, rax\ntest ebx, ebx\njle loc_12F3\nloc_1268:\nmov byte ptr [rax], 70h ; 'p'\nadd rax, 1\ncmp rax, rcx\njnz short loc_1268\nloc_1274:\ntest r13d, r13d\njle short loc_1298\nmovsxd rsi, ebx\nlea rax, [rdx+rsi]\nmovsxd rcx, r13d\nadd rcx, rdx\nadd rcx, rsi\nloc_1289:\nmov byte ptr [rax], 71h ; 'q'\nadd rax, 1\ncmp rax, rcx\njnz short loc_1289\nadd ebx, r13d\nloc_1298:\ntest r12d, r12d\njle short loc_12BC\nmovsxd rsi, ebx\nlea rax, [rdx+rsi]\nmovsxd rcx, r12d\nadd rcx, rdx\nadd rcx, rsi\nloc_12AD:\nmov byte ptr [rax], 72h ; 'r'\nadd rax, 1\ncmp rax, rcx\njnz short loc_12AD\nadd ebx, r12d\nloc_12BC:\ntest ebp, ebp\njle short loc_12DE\nmovsxd rsi, ebx\nlea rax, [rdx+rsi]\nmovsxd rcx, ebp\nadd rcx, rdx\nadd rcx, rsi\nloc_12D0:\nmov byte ptr [rax], 73h ; 's'\nadd rax, 1\ncmp rax, rcx\njnz short loc_12D0\nadd ebx, ebp\nloc_12DE:\nmovsxd rbx, ebx\nmov byte ptr [rdx+rbx], 0\nmov rax, rdx\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_12F3:\nmov ebx, 0\njmp loc_1274\nloc_12FD:\nlea rdi, s; \"Failed to allocate memory\"\ncall _perror\nmov edi, 1; status\ncall _exit", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1209(int a1, int a2, int a3, int a4)\n{\n int v4; // ebx\n bool v7; // sf\n int v8; // edi\n _BYTE *v9; // rax\n _BYTE *v10; // rdx\n _BYTE *v11; // rcx\n _BYTE *v12; // rax\n _BYTE *v13; // rax\n _BYTE *v14; // rax\n\n v4 = a1;\n v7 = a1 < 0;\n v8 = 0;\n if ( !v7 )\n v8 = v4;\n if ( a2 > 0 )\n v8 += a2;\n if ( a3 > 0 )\n v8 += a3;\n if ( a4 > 0 )\n v8 += a4;\n v9 = malloc(v8 + 1);\n if ( !v9 )\n {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v10 = v9;\n v11 = &v9[v4];\n if ( v4 <= 0 )\n {\n v4 = 0;\n }\n else\n {\n do\n *v9++ = 112;\n while ( v9 != v11 );\n }\n if ( a2 > 0 )\n {\n v12 = &v10[v4];\n do\n *v12++ = 113;\n while ( v12 != &v10[a2 + v4] );\n v4 += a2;\n }\n if ( a3 > 0 )\n {\n v13 = &v10[v4];\n do\n *v13++ = 114;\n while ( v13 != &v10[a3 + v4] );\n v4 += a3;\n }\n if ( a4 > 0 )\n {\n v14 = &v10[v4];\n do\n *v14++ = 115;\n while ( v14 != &v10[a4 + v4] );\n v4 += a4;\n }\n v10[v4] = 0;\n return v10;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1209(int a1, int a2, int a3, int a4) {\n int v4;\n bool v7;\n int v8;\n uint8_t *v9;\n uint8_t *v10;\n uint8_t *v11;\n uint8_t *v12;\n uint8_t *v13;\n uint8_t *v14;\n v4 = a1;\n v7 = a1 < 0;\n v8 = 0;\n if (!v7) v8 = v4;\n if (a2 > 0) v8 += a2;\n if (a3 > 0) v8 += a3;\n if (a4 > 0) v8 += a4;\n v9 = malloc(v8 + 1);\n if (!v9) {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v10 = v9;\n v11 = &v9[v4];\n if (v4 <= 0) {\n v4 = 0;\n } else {\n do\n *v9++ = 112;\n while (v9 != v11);\n }\n if (a2 > 0) {\n v12 = &v10[v4];\n do\n *v12++ = 113;\n while (v12 != &v10[a2 + v4]);\n v4 += a2;\n }\n if (a3 > 0) {\n v13 = &v10[v4];\n do\n *v13++ = 114;\n while (v13 != &v10[a3 + v4]);\n v4 += a3;\n }\n if (a4 > 0) {\n v14 = &v10[v4];\n do\n *v14++ = 115;\n while (v14 != &v10[a4 + v4]);\n v4 += a4;\n }\n v10[v4] = 0;\n return v10;\n}", + "ida_pseudo_norm": "uint8_t *func0(int a1, int a2, int a3, int a4) {\n int v4;\n bool v7;\n int v8;\n uint8_t *v9;\n uint8_t *v10;\n uint8_t *v11;\n uint8_t *v12;\n uint8_t *v13;\n uint8_t *v14;\n v4 = a1;\n v7 = a1 < 0;\n v8 = 0;\n if (!v7) v8 = v4;\n if (a2 > 0) v8 += a2;\n if (a3 > 0) v8 += a3;\n if (a4 > 0) v8 += a4;\n v9 = malloc(v8 + 1);\n if (!v9) {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v10 = v9;\n v11 = &v9[v4];\n if (v4 <= 0) {\n v4 = 0;\n } else {\n do\n *v9++ = 112;\n while (v9 != v11);\n }\n if (a2 > 0) {\n v12 = &v10[v4];\n do\n *v12++ = 113;\n while (v12 != &v10[a2 + v4]);\n v4 += a2;\n }\n if (a3 > 0) {\n v13 = &v10[v4];\n do\n *v13++ = 114;\n while (v13 != &v10[a3 + v4]);\n v4 += a3;\n }\n if (a4 > 0) {\n v14 = &v10[v4];\n do\n *v14++ = 115;\n while (v14 != &v10[a4 + v4]);\n v4 += a4;\n }\n v10[v4] = 0;\n return v10;\n}" + }, + { + "index": 810, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(int a, int b, int c, int d) {\n int total = 0;\n if (a > 0) total += a;\n if (b > 0) total += b;\n if (c > 0) total += c;\n if (d > 0) total += d;\n char* result = malloc((total + 1) * sizeof(char));\n if (!result) {\n perror(\"Failed to allocate memory\");\n exit(EXIT_FAILURE);\n }\n int index = 0;\n for (int i = 0; i < a; i++) {\n result[index++] = 'p';\n }\n for (int i = 0; i < b; i++) {\n result[index++] = 'q';\n }\n for (int i = 0; i < c; i++) {\n result[index++] = 'r';\n }\n for (int i = 0; i < d; i++) {\n result[index++] = 's';\n }\n result[index] = '\\0';\n return result;\n}", + "test": "int main() {\n\n char* res1 = func0(4, 2, 0, -2);\n\n assert(strcmp(res1, \"ppppqq\") == 0);\n\n free(res1);\n\n\n\n char* res2 = func0(0, 1, 2, 3);\n\n assert(strcmp(res2, \"qrrsss\") == 0);\n\n free(res2);\n\n\n\n char* res3 = func0(11, 15, 12, 23);\n\n char expected3[11 + 15 + 12 + 23 + 1];\n\n int idx = 0;\n\n for(int i = 0; i < 11; i++) expected3[idx++] = 'p';\n\n for(int i = 0; i < 15; i++) expected3[idx++] = 'q';\n\n for(int i = 0; i < 12; i++) expected3[idx++] = 'r';\n\n for(int i = 0; i < 23; i++) expected3[idx++] = 's';\n\n expected3[idx] = '\\0';\n\n assert(strcmp(res3, expected3) == 0);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov %esi,%r13d\npush %r12\nmov %edx,%r12d\npush %rbp\nmov %ecx,%ebp\npush %rbx\nmov %edi,%ebx\nsub $0x8,%rsp\ntest %edi,%edi\nmov $0x0,%edi\ncmovns %ebx,%edi\ntest %esi,%esi\nlea (%rdi,%rsi,1),%eax\ncmovg %eax,%edi\ntest %edx,%edx\nlea (%rdi,%rdx,1),%eax\ncmovg %eax,%edi\ntest %ecx,%ecx\nlea (%rdi,%rcx,1),%eax\ncmovg %eax,%edi\nadd $0x1,%edi\nmovslq %edi,%rdi\ncallq 10f0 \ntest %rax,%rax\nje 14e2 \ntest %ebx,%ebx\njle 14d8 \nlea -0x1(%rbx),%edx\nmov %rax,%rdi\nlea 0x1(%rax,%rdx,1),%rdx\nnopl 0x0(%rax)\nmovb $0x70,(%rdi)\nadd $0x1,%rdi\ncmp %rdx,%rdi\njne 1418 \nmovslq %ebx,%rdx\nadd %rax,%rdx\ntest %r13d,%r13d\njle 145d \nlea -0x1(%r13),%edx\nmovslq %ebx,%rcx\nlea 0x1(%rax,%rdx,1),%rdx\nlea (%rax,%rcx,1),%rdi\nadd %rcx,%rdx\nnopw 0x0(%rax,%rax,1)\nmovb $0x71,(%rdi)\nadd $0x1,%rdi\ncmp %rdx,%rdi\njne 1448 \nadd %r13d,%ebx\nmovslq %ebx,%rdx\nadd %rax,%rdx\ntest %r12d,%r12d\njle 1495 \nlea -0x1(%r12),%ecx\nmovslq %ebx,%rdx\nlea 0x1(%rax,%rcx,1),%rcx\nlea (%rax,%rdx,1),%rsi\nadd %rdx,%rcx\nnopw %cs:0x0(%rax,%rax,1)\nmovb $0x72,(%rsi)\nadd $0x1,%rsi\ncmp %rsi,%rcx\njne 1480 \nadd %r12d,%ebx\nmovslq %ebx,%rdx\nadd %rax,%rdx\ntest %ebp,%ebp\njle 14c5 \nlea -0x1(%rbp),%esi\nmovslq %ebx,%rcx\nlea 0x1(%rax,%rsi,1),%rsi\nlea (%rax,%rcx,1),%rdx\nadd %rcx,%rsi\nnopl 0x0(%rax,%rax,1)\nmovb $0x73,(%rdx)\nadd $0x1,%rdx\ncmp %rsi,%rdx\njne 14b0 \nadd %ebp,%ebx\nmovslq %ebx,%rbx\nlea (%rax,%rbx,1),%rdx\nmovb $0x0,(%rdx)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax,%rax,1)\nmov %rax,%rdx\nxor %ebx,%ebx\njmpq 142a \nlea 0xb1b(%rip),%rdi\ncallq 1100 \nmov $0x1,%edi\ncallq 1110 \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\ntest edi, edi\npush r13\nmov r13d, esi\npush r12\nmov r12d, edx\npush rbp\nmov ebp, ecx\npush rbx\nmov ebx, edi\nmov edi, 0\ncmovns edi, ebx\ntest esi, esi\nlea eax, [rdi+rsi]\ncmovg edi, eax\ntest edx, edx\nlea eax, [rdi+rdx]\ncmovg edi, eax\ntest ecx, ecx\nlea eax, [rdi+rcx]\ncmovg edi, eax\nadd edi, 1\nmovsxd rdi, edi; size\ncall _malloc\ntest rax, rax\njz func0_cold\nmov r14, rax\ntest ebx, ebx\njle loc_14D0\nmov edx, ebx; n\nmov esi, 70h ; 'p'; c\nmov rdi, rax; s\ncall _memset\nmovsxd rax, ebx\nadd rax, r14\nloc_145C:\ntest r13d, r13d\njle short loc_147D\nmovsxd rdi, ebx\nmov edx, r13d; n\nmov esi, 71h ; 'q'; c\nadd ebx, r13d\nadd rdi, r14; s\ncall _memset\nmovsxd rax, ebx\nadd rax, r14\nloc_147D:\ntest r12d, r12d\njle short loc_149E\nmovsxd rdi, ebx\nmov edx, r12d; n\nmov esi, 72h ; 'r'; c\nadd ebx, r12d\nadd rdi, r14; s\ncall _memset\nmovsxd rax, ebx\nadd rax, r14\nloc_149E:\ntest ebp, ebp\njle short loc_14BD\nmovsxd rdi, ebx\nadd ebx, ebp\nmov edx, ebp; n\nmov esi, 73h ; 's'; c\nadd rdi, r14; s\nmovsxd rbx, ebx\ncall _memset\nlea rax, [r14+rbx]\nloc_14BD:\nmov byte ptr [rax], 0\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_14D0:\nxor ebx, ebx\njmp short loc_145C", + "ida_pseudo": "_BYTE *__fastcall func0(size_t n, int a2, int a3, int a4)\n{\n bool v4; // sf\n int v7; // ebx\n int v8; // edi\n _BYTE *v9; // rax\n _BYTE *v10; // r14\n __int64 v11; // rdi\n __int64 v12; // rdi\n\n v4 = (n & 0x80000000) != 0LL;\n v7 = n;\n v8 = 0;\n if ( !v4 )\n v8 = v7;\n if ( a2 > 0 )\n v8 += a2;\n if ( a3 > 0 )\n v8 += a3;\n if ( a4 > 0 )\n v8 += a4;\n v9 = malloc(v8 + 1);\n if ( !v9 )\n func0_cold();\n v10 = v9;\n if ( v7 <= 0 )\n {\n v7 = 0;\n }\n else\n {\n memset(v9, 112, (unsigned int)v7);\n v9 = &v10[v7];\n }\n if ( a2 > 0 )\n {\n v11 = v7;\n v7 += a2;\n memset(&v10[v11], 113, (unsigned int)a2);\n v9 = &v10[v7];\n }\n if ( a3 > 0 )\n {\n v12 = v7;\n v7 += a3;\n memset(&v10[v12], 114, (unsigned int)a3);\n v9 = &v10[v7];\n }\n if ( a4 > 0 )\n {\n memset(&v10[v7], 115, (unsigned int)a4);\n v9 = &v10[a4 + v7];\n }\n *v9 = 0;\n return v10;\n}", + "ida_strip_asm": "sub_13F0:\nendbr64\npush r14\ntest edi, edi\npush r13\nmov r13d, esi\npush r12\nmov r12d, edx\npush rbp\nmov ebp, ecx\npush rbx\nmov ebx, edi\nmov edi, 0\ncmovns edi, ebx\ntest esi, esi\nlea eax, [rdi+rsi]\ncmovg edi, eax\ntest edx, edx\nlea eax, [rdi+rdx]\ncmovg edi, eax\ntest ecx, ecx\nlea eax, [rdi+rcx]\ncmovg edi, eax\nadd edi, 1\nmovsxd rdi, edi; size\ncall _malloc\ntest rax, rax\njz loc_1140\nmov r14, rax\ntest ebx, ebx\njle loc_14D0\nmov edx, ebx; n\nmov esi, 70h ; 'p'; c\nmov rdi, rax; s\ncall _memset\nmovsxd rax, ebx\nadd rax, r14\nloc_145C:\ntest r13d, r13d\njle short loc_147D\nmovsxd rdi, ebx\nmov edx, r13d; n\nmov esi, 71h ; 'q'; c\nadd ebx, r13d\nadd rdi, r14; s\ncall _memset\nmovsxd rax, ebx\nadd rax, r14\nloc_147D:\ntest r12d, r12d\njle short loc_149E\nmovsxd rdi, ebx\nmov edx, r12d; n\nmov esi, 72h ; 'r'; c\nadd ebx, r12d\nadd rdi, r14; s\ncall _memset\nmovsxd rax, ebx\nadd rax, r14\nloc_149E:\ntest ebp, ebp\njle short loc_14BD\nmovsxd rdi, ebx\nadd ebx, ebp\nmov edx, ebp; n\nmov esi, 73h ; 's'; c\nadd rdi, r14; s\nmovsxd rbx, ebx\ncall _memset\nlea rax, [r14+rbx]\nloc_14BD:\nmov byte ptr [rax], 0\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_14D0:\nxor ebx, ebx\njmp short loc_145C", + "ida_strip_pseudo": "_BYTE *__fastcall sub_13F0(size_t n, int a2, int a3, int a4)\n{\n bool v4; // sf\n int v7; // ebx\n int v8; // edi\n _BYTE *v9; // rax\n _BYTE *v10; // r14\n __int64 v11; // rdi\n __int64 v12; // rdi\n\n v4 = (n & 0x80000000) != 0LL;\n v7 = n;\n v8 = 0;\n if ( !v4 )\n v8 = v7;\n if ( a2 > 0 )\n v8 += a2;\n if ( a3 > 0 )\n v8 += a3;\n if ( a4 > 0 )\n v8 += a4;\n v9 = malloc(v8 + 1);\n if ( !v9 )\n {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v10 = v9;\n if ( v7 <= 0 )\n {\n v7 = 0;\n }\n else\n {\n memset(v9, 112, (unsigned int)v7);\n v9 = &v10[v7];\n }\n if ( a2 > 0 )\n {\n v11 = v7;\n v7 += a2;\n memset(&v10[v11], 113, (unsigned int)a2);\n v9 = &v10[v7];\n }\n if ( a3 > 0 )\n {\n v12 = v7;\n v7 += a3;\n memset(&v10[v12], 114, (unsigned int)a3);\n v9 = &v10[v7];\n }\n if ( a4 > 0 )\n {\n memset(&v10[v7], 115, (unsigned int)a4);\n v9 = &v10[a4 + v7];\n }\n *v9 = 0;\n return v10;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_13F0(unsigned int n, int a2, int a3, int a4) {\n bool v4;\n int v7;\n int v8;\n uint8_t *v9;\n uint8_t *v10;\n long long v11;\n long long v12;\n v4 = (n & 2147483648) != 0LL;\n v7 = n;\n v8 = 0;\n if (!v4) v8 = v7;\n if (a2 > 0) v8 += a2;\n if (a3 > 0) v8 += a3;\n if (a4 > 0) v8 += a4;\n v9 = malloc(v8 + 1);\n if (!v9) {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v10 = v9;\n if (v7 <= 0) {\n v7 = 0;\n } else {\n memset(v9, 112, (unsigned int)v7);\n v9 = &v10[v7];\n }\n if (a2 > 0) {\n v11 = v7;\n v7 += a2;\n memset(&v10[v11], 113, (unsigned int)a2);\n v9 = &v10[v7];\n }\n if (a3 > 0) {\n v12 = v7;\n v7 += a3;\n memset(&v10[v12], 114, (unsigned int)a3);\n v9 = &v10[v7];\n }\n if (a4 > 0) {\n memset(&v10[v7], 115, (unsigned int)a4);\n v9 = &v10[a4 + v7];\n }\n *v9 = 0;\n return v10;\n}", + "ida_pseudo_norm": "uint8_t *func0(unsigned int n, int a2, int a3, int a4) {\n bool v4;\n int v7;\n int v8;\n uint8_t *v9;\n uint8_t *v10;\n long long v11;\n long long v12;\n v4 = (n & 2147483648) != 0LL;\n v7 = n;\n v8 = 0;\n if (!v4) v8 = v7;\n if (a2 > 0) v8 += a2;\n if (a3 > 0) v8 += a3;\n if (a4 > 0) v8 += a4;\n v9 = malloc(v8 + 1);\n if (!v9) func0_cold();\n v10 = v9;\n if (v7 <= 0) {\n v7 = 0;\n } else {\n memset(v9, 112, (unsigned int)v7);\n v9 = &v10[v7];\n }\n if (a2 > 0) {\n v11 = v7;\n v7 += a2;\n memset(&v10[v11], 113, (unsigned int)a2);\n v9 = &v10[v7];\n }\n if (a3 > 0) {\n v12 = v7;\n v7 += a3;\n memset(&v10[v12], 114, (unsigned int)a3);\n v9 = &v10[v7];\n }\n if (a4 > 0) {\n memset(&v10[v7], 115, (unsigned int)a4);\n v9 = &v10[a4 + v7];\n }\n *v9 = 0;\n return v10;\n}" + }, + { + "index": 810, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(int a, int b, int c, int d) {\n int total = 0;\n if (a > 0) total += a;\n if (b > 0) total += b;\n if (c > 0) total += c;\n if (d > 0) total += d;\n char* result = malloc((total + 1) * sizeof(char));\n if (!result) {\n perror(\"Failed to allocate memory\");\n exit(EXIT_FAILURE);\n }\n int index = 0;\n for (int i = 0; i < a; i++) {\n result[index++] = 'p';\n }\n for (int i = 0; i < b; i++) {\n result[index++] = 'q';\n }\n for (int i = 0; i < c; i++) {\n result[index++] = 'r';\n }\n for (int i = 0; i < d; i++) {\n result[index++] = 's';\n }\n result[index] = '\\0';\n return result;\n}", + "test": "int main() {\n\n char* res1 = func0(4, 2, 0, -2);\n\n assert(strcmp(res1, \"ppppqq\") == 0);\n\n free(res1);\n\n\n\n char* res2 = func0(0, 1, 2, 3);\n\n assert(strcmp(res2, \"qrrsss\") == 0);\n\n free(res2);\n\n\n\n char* res3 = func0(11, 15, 12, 23);\n\n char expected3[11 + 15 + 12 + 23 + 1];\n\n int idx = 0;\n\n for(int i = 0; i < 11; i++) expected3[idx++] = 'p';\n\n for(int i = 0; i < 15; i++) expected3[idx++] = 'q';\n\n for(int i = 0; i < 12; i++) expected3[idx++] = 'r';\n\n for(int i = 0; i < 23; i++) expected3[idx++] = 's';\n\n expected3[idx] = '\\0';\n\n assert(strcmp(res3, expected3) == 0);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\ntest %edi,%edi\nmov %esi,%r14d\npush %r13\npush %r12\nmov %edx,%r12d\npush %rbp\nmov %ecx,%ebp\npush %rbx\nmov %edi,%ebx\nmov $0x0,%edi\ncmovns %ebx,%edi\ntest %esi,%esi\nlea (%rdi,%rsi,1),%eax\ncmovg %eax,%edi\ntest %edx,%edx\nlea (%rdi,%rdx,1),%eax\ncmovg %eax,%edi\ntest %ecx,%ecx\nlea (%rdi,%rcx,1),%eax\ncmovg %eax,%edi\nadd $0x1,%edi\nmovslq %edi,%rdi\ncallq 1110 \ntest %rax,%rax\nje 14ff \nmov %rax,%r13\ntest %ebx,%ebx\njle 14f8 \nlea -0x1(%rbx),%edx\nmov $0x70,%esi\nmov %rax,%rdi\nadd $0x1,%rdx\ncallq 10f0 \nmovslq %ebx,%rax\nadd %r13,%rax\ntest %r14d,%r14d\njle 1497 \nmovslq %ebx,%rdi\nlea -0x1(%r14),%edx\nmov $0x71,%esi\nadd %r14d,%ebx\nadd $0x1,%rdx\nadd %r13,%rdi\ncallq 10f0 \nmovslq %ebx,%rax\nadd %r13,%rax\ntest %r12d,%r12d\njle 14be \nmovslq %ebx,%rdi\nlea -0x1(%r12),%edx\nmov $0x72,%esi\nadd %r12d,%ebx\nadd $0x1,%rdx\nadd %r13,%rdi\ncallq 10f0 \nmovslq %ebx,%rax\nadd %r13,%rax\ntest %ebp,%ebp\njle 14e3 \nmovslq %ebx,%rdi\nlea -0x1(%rbp),%edx\nadd %ebp,%ebx\nmov $0x73,%esi\nadd $0x1,%rdx\nadd %r13,%rdi\nmovslq %ebx,%rbx\ncallq 10f0 \nlea 0x0(%r13,%rbx,1),%rax\nmovb $0x0,(%rax)\nmov %r13,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopw 0x0(%rax,%rax,1)\nxor %ebx,%ebx\njmpq 1471 \nlea 0xafe(%rip),%rdi\ncallq 1120 \nmov $0x1,%edi\ncallq 1130 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\ntest edi, edi\npush r13\nmov r13d, esi\npush r12\nmov r12d, edx\npush rbp\nmov ebp, ecx\npush rbx\nmov ebx, edi\nmov edi, 0\ncmovns edi, ebx\ntest esi, esi\nlea eax, [rdi+rsi]\ncmovg edi, eax\ntest edx, edx\nlea eax, [rdi+rdx]\ncmovg edi, eax\ntest ecx, ecx\nlea eax, [rdi+rcx]\ncmovg edi, eax\nadd edi, 1\nmovsxd rdi, edi; size\ncall _malloc\ntest rax, rax\njz func0_cold\nmov r14, rax\ntest ebx, ebx\njle loc_14D0\nmov edx, ebx; n\nmov esi, 70h ; 'p'; c\nmov rdi, rax; s\ncall _memset\nmovsxd rax, ebx\nadd rax, r14\nloc_145C:\ntest r13d, r13d\njle short loc_147D\nmovsxd rdi, ebx\nmov edx, r13d; n\nmov esi, 71h ; 'q'; c\nadd ebx, r13d\nadd rdi, r14; s\ncall _memset\nmovsxd rax, ebx\nadd rax, r14\nloc_147D:\ntest r12d, r12d\njle short loc_149E\nmovsxd rdi, ebx\nmov edx, r12d; n\nmov esi, 72h ; 'r'; c\nadd ebx, r12d\nadd rdi, r14; s\ncall _memset\nmovsxd rax, ebx\nadd rax, r14\nloc_149E:\ntest ebp, ebp\njle short loc_14BD\nmovsxd rdi, ebx\nadd ebx, ebp\nmov edx, ebp; n\nmov esi, 73h ; 's'; c\nadd rdi, r14; s\nmovsxd rbx, ebx\ncall _memset\nlea rax, [r14+rbx]\nloc_14BD:\nmov byte ptr [rax], 0\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_14D0:\nxor ebx, ebx\njmp short loc_145C", + "ida_pseudo": "_BYTE *__fastcall func0(size_t n, int a2, int a3, int a4)\n{\n bool v4; // sf\n int v7; // ebx\n int v8; // edi\n _BYTE *v9; // rax\n _BYTE *v10; // r14\n __int64 v11; // rdi\n __int64 v12; // rdi\n\n v4 = (n & 0x80000000) != 0LL;\n v7 = n;\n v8 = 0;\n if ( !v4 )\n v8 = v7;\n if ( a2 > 0 )\n v8 += a2;\n if ( a3 > 0 )\n v8 += a3;\n if ( a4 > 0 )\n v8 += a4;\n v9 = malloc(v8 + 1);\n if ( !v9 )\n func0_cold();\n v10 = v9;\n if ( v7 <= 0 )\n {\n v7 = 0;\n }\n else\n {\n memset(v9, 112, (unsigned int)v7);\n v9 = &v10[v7];\n }\n if ( a2 > 0 )\n {\n v11 = v7;\n v7 += a2;\n memset(&v10[v11], 113, (unsigned int)a2);\n v9 = &v10[v7];\n }\n if ( a3 > 0 )\n {\n v12 = v7;\n v7 += a3;\n memset(&v10[v12], 114, (unsigned int)a3);\n v9 = &v10[v7];\n }\n if ( a4 > 0 )\n {\n memset(&v10[v7], 115, (unsigned int)a4);\n v9 = &v10[a4 + v7];\n }\n *v9 = 0;\n return v10;\n}", + "ida_strip_asm": "sub_13F0:\nendbr64\npush r14\ntest edi, edi\npush r13\nmov r13d, esi\npush r12\nmov r12d, edx\npush rbp\nmov ebp, ecx\npush rbx\nmov ebx, edi\nmov edi, 0\ncmovns edi, ebx\ntest esi, esi\nlea eax, [rdi+rsi]\ncmovg edi, eax\ntest edx, edx\nlea eax, [rdi+rdx]\ncmovg edi, eax\ntest ecx, ecx\nlea eax, [rdi+rcx]\ncmovg edi, eax\nadd edi, 1\nmovsxd rdi, edi; size\ncall _malloc\ntest rax, rax\njz loc_1140\nmov r14, rax\ntest ebx, ebx\njle loc_14D0\nmov edx, ebx; n\nmov esi, 70h ; 'p'; c\nmov rdi, rax; s\ncall _memset\nmovsxd rax, ebx\nadd rax, r14\nloc_145C:\ntest r13d, r13d\njle short loc_147D\nmovsxd rdi, ebx\nmov edx, r13d; n\nmov esi, 71h ; 'q'; c\nadd ebx, r13d\nadd rdi, r14; s\ncall _memset\nmovsxd rax, ebx\nadd rax, r14\nloc_147D:\ntest r12d, r12d\njle short loc_149E\nmovsxd rdi, ebx\nmov edx, r12d; n\nmov esi, 72h ; 'r'; c\nadd ebx, r12d\nadd rdi, r14; s\ncall _memset\nmovsxd rax, ebx\nadd rax, r14\nloc_149E:\ntest ebp, ebp\njle short loc_14BD\nmovsxd rdi, ebx\nadd ebx, ebp\nmov edx, ebp; n\nmov esi, 73h ; 's'; c\nadd rdi, r14; s\nmovsxd rbx, ebx\ncall _memset\nlea rax, [r14+rbx]\nloc_14BD:\nmov byte ptr [rax], 0\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_14D0:\nxor ebx, ebx\njmp short loc_145C", + "ida_strip_pseudo": "_BYTE *__fastcall sub_13F0(size_t n, int a2, int a3, int a4)\n{\n bool v4; // sf\n int v7; // ebx\n int v8; // edi\n _BYTE *v9; // rax\n _BYTE *v10; // r14\n __int64 v11; // rdi\n __int64 v12; // rdi\n\n v4 = (n & 0x80000000) != 0LL;\n v7 = n;\n v8 = 0;\n if ( !v4 )\n v8 = v7;\n if ( a2 > 0 )\n v8 += a2;\n if ( a3 > 0 )\n v8 += a3;\n if ( a4 > 0 )\n v8 += a4;\n v9 = malloc(v8 + 1);\n if ( !v9 )\n {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v10 = v9;\n if ( v7 <= 0 )\n {\n v7 = 0;\n }\n else\n {\n memset(v9, 112, (unsigned int)v7);\n v9 = &v10[v7];\n }\n if ( a2 > 0 )\n {\n v11 = v7;\n v7 += a2;\n memset(&v10[v11], 113, (unsigned int)a2);\n v9 = &v10[v7];\n }\n if ( a3 > 0 )\n {\n v12 = v7;\n v7 += a3;\n memset(&v10[v12], 114, (unsigned int)a3);\n v9 = &v10[v7];\n }\n if ( a4 > 0 )\n {\n memset(&v10[v7], 115, (unsigned int)a4);\n v9 = &v10[a4 + v7];\n }\n *v9 = 0;\n return v10;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_13F0(unsigned int n, int a2, int a3, int a4) {\n bool v4;\n int v7;\n int v8;\n uint8_t *v9;\n uint8_t *v10;\n long long v11;\n long long v12;\n v4 = (n & 2147483648) != 0LL;\n v7 = n;\n v8 = 0;\n if (!v4) v8 = v7;\n if (a2 > 0) v8 += a2;\n if (a3 > 0) v8 += a3;\n if (a4 > 0) v8 += a4;\n v9 = malloc(v8 + 1);\n if (!v9) {\n perror(\"Failed to allocate memory\");\n exit(1);\n }\n v10 = v9;\n if (v7 <= 0) {\n v7 = 0;\n } else {\n memset(v9, 112, (unsigned int)v7);\n v9 = &v10[v7];\n }\n if (a2 > 0) {\n v11 = v7;\n v7 += a2;\n memset(&v10[v11], 113, (unsigned int)a2);\n v9 = &v10[v7];\n }\n if (a3 > 0) {\n v12 = v7;\n v7 += a3;\n memset(&v10[v12], 114, (unsigned int)a3);\n v9 = &v10[v7];\n }\n if (a4 > 0) {\n memset(&v10[v7], 115, (unsigned int)a4);\n v9 = &v10[a4 + v7];\n }\n *v9 = 0;\n return v10;\n}", + "ida_pseudo_norm": "uint8_t *func0(unsigned int n, int a2, int a3, int a4) {\n bool v4;\n int v7;\n int v8;\n uint8_t *v9;\n uint8_t *v10;\n long long v11;\n long long v12;\n v4 = (n & 2147483648) != 0LL;\n v7 = n;\n v8 = 0;\n if (!v4) v8 = v7;\n if (a2 > 0) v8 += a2;\n if (a3 > 0) v8 += a3;\n if (a4 > 0) v8 += a4;\n v9 = malloc(v8 + 1);\n if (!v9) func0_cold();\n v10 = v9;\n if (v7 <= 0) {\n v7 = 0;\n } else {\n memset(v9, 112, (unsigned int)v7);\n v9 = &v10[v7];\n }\n if (a2 > 0) {\n v11 = v7;\n v7 += a2;\n memset(&v10[v11], 113, (unsigned int)a2);\n v9 = &v10[v7];\n }\n if (a3 > 0) {\n v12 = v7;\n v7 += a3;\n memset(&v10[v12], 114, (unsigned int)a3);\n v9 = &v10[v7];\n }\n if (a4 > 0) {\n memset(&v10[v7], 115, (unsigned int)a4);\n v9 = &v10[a4 + v7];\n }\n *v9 = 0;\n return v10;\n}" + }, + { + "index": 811, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int test_list1[][2], int size1, int test_list2[][2], int size2) {\n if (size1 != size2) {\n return false;\n }\n for (int i = 0; i < size1; i++) {\n if (test_list1[i][0] != test_list2[i][0] ||\n test_list1[i][1] != test_list2[i][1]) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n int list1[][2] = {{10, 4}, {2, 5}};\n\n int list2[][2] = {{10, 4}, {2, 5}};\n\n int list3[][2] = {{1, 2}, {3, 7}};\n\n int list4[][2] = {{12, 14}, {12, 45}};\n\n int list5[][2] = {{2, 14}, {12, 25}};\n\n int list6[][2] = {{2, 14}, {12, 25}};\n\n\n\n assert(func0(list1, 2, list2, 2) == true);\n\n assert(func0(list3, 2, list4, 2) == false);\n\n assert(func0(list5, 2, list6, 2) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %ecx,-0x20(%rbp)\nmov -0x1c(%rbp),%eax\ncmp -0x20(%rbp),%eax\nje 1191 \nmov $0x0,%eax\njmpq 1214 \nmovl $0x0,-0x4(%rbp)\njmp 1207 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 11fc \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov 0x4(%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov 0x4(%rax),%eax\ncmp %eax,%edx\nje 1203 \nmov $0x0,%eax\njmp 1214 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 119a \nmov $0x1,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_20]\njz short loc_1191\nmov eax, 0\njmp loc_1214\nloc_1191:\nmov [rbp+var_4], 0\njmp short loc_1207\nloc_119A:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11FC\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax+4]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax+4]\ncmp edx, eax\njz short loc_1203\nloc_11FC:\nmov eax, 0\njmp short loc_1214\nloc_1203:\nadd [rbp+var_4], 1\nloc_1207:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_119A\nmov eax, 1\nloc_1214:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3, int a4)\n{\n int i; // [rsp+24h] [rbp-4h]\n\n if ( a2 != a4 )\n return 0LL;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(_DWORD *)(8LL * i + a1) != *(_DWORD *)(8LL * i + a3)\n || *(_DWORD *)(8LL * i + a1 + 4) != *(_DWORD *)(8LL * i + a3 + 4) )\n {\n return 0LL;\n }\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_20]\njz short loc_1191\nmov eax, 0\njmp loc_1214\nloc_1191:\nmov [rbp+var_4], 0\njmp short loc_1207\nloc_119A:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11FC\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax+4]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax+4]\ncmp edx, eax\njz short loc_1203\nloc_11FC:\nmov eax, 0\njmp short loc_1214\nloc_1203:\nadd [rbp+var_4], 1\nloc_1207:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_119A\nmov eax, 1\nloc_1214:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, __int64 a3, int a4)\n{\n int i; // [rsp+24h] [rbp-4h]\n\n if ( a2 != a4 )\n return 0LL;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(_DWORD *)(8LL * i + a1) != *(_DWORD *)(8LL * i + a3)\n || *(_DWORD *)(8LL * i + a1 + 4) != *(_DWORD *)(8LL * i + a3 + 4) )\n {\n return 0LL;\n }\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, long long a3, int a4) {\n int i;\n if (a2 != a4) return 0LL;\n for (i = 0; i < a2; ++i) {\n if (*(uint32_t *)(8LL * i + a1) != *(uint32_t *)(8LL * i + a3) ||\n *(uint32_t *)(8LL * i + a1 + 4) != *(uint32_t *)(8LL * i + a3 + 4)) {\n return 0LL;\n }\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3, int a4) {\n int i;\n if (a2 != a4) return 0LL;\n for (i = 0; i < a2; ++i) {\n if (*(uint32_t *)(8LL * i + a1) != *(uint32_t *)(8LL * i + a3) ||\n *(uint32_t *)(8LL * i + a1 + 4) != *(uint32_t *)(8LL * i + a3 + 4)) {\n return 0LL;\n }\n }\n return 1LL;\n}" + }, + { + "index": 811, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int test_list1[][2], int size1, int test_list2[][2], int size2) {\n if (size1 != size2) {\n return false;\n }\n for (int i = 0; i < size1; i++) {\n if (test_list1[i][0] != test_list2[i][0] ||\n test_list1[i][1] != test_list2[i][1]) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n int list1[][2] = {{10, 4}, {2, 5}};\n\n int list2[][2] = {{10, 4}, {2, 5}};\n\n int list3[][2] = {{1, 2}, {3, 7}};\n\n int list4[][2] = {{12, 14}, {12, 45}};\n\n int list5[][2] = {{2, 14}, {12, 25}};\n\n int list6[][2] = {{2, 14}, {12, 25}};\n\n\n\n assert(func0(list1, 2, list2, 2) == true);\n\n assert(func0(list3, 2, list4, 2) == false);\n\n assert(func0(list5, 2, list6, 2) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x0,%eax\ncmp %ecx,%esi\njne 11b9 \ntest %esi,%esi\njle 11a8 \nlea -0x1(%rsi),%esi\nmov $0x0,%eax\njmp 1187 \nmov %rcx,%rax\nmov (%rdx,%rax,8),%ecx\ncmp %ecx,(%rdi,%rax,8)\njne 11ae \nmov 0x4(%rdx,%rax,8),%ecx\ncmp %ecx,0x4(%rdi,%rax,8)\njne 11b4 \nlea 0x1(%rax),%rcx\ncmp %rsi,%rax\njne 1184 \nmov $0x1,%eax\nretq\nmov $0x1,%eax\nretq\nmov $0x0,%eax\nretq\nmov $0x0,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov eax, 0\ncmp esi, ecx\njnz short locret_11BC\ntest esi, esi\njle short loc_11AB\nmovsxd rsi, esi\nlea rcx, ds:0[rsi*8]\nmov eax, 0\nloc_118A:\nmov esi, [rdx+rax]\ncmp [rdi+rax], esi\njnz short loc_11B1\nmov esi, [rdx+rax+4]\ncmp [rdi+rax+4], esi\njnz short loc_11B7\nadd rax, 8\ncmp rax, rcx\njnz short loc_118A\nmov eax, 1\nretn\nloc_11AB:\nmov eax, 1\nretn\nloc_11B1:\nmov eax, 0\nretn\nloc_11B7:\nmov eax, 0\nlocret_11BC:\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3, int a4)\n{\n __int64 result; // rax\n __int64 v5; // rax\n\n result = 0LL;\n if ( a2 == a4 )\n {\n if ( a2 <= 0 )\n {\n return 1LL;\n }\n else\n {\n v5 = 0LL;\n while ( 1 )\n {\n if ( *(_DWORD *)(a1 + v5) != *(_DWORD *)(a3 + v5) )\n return 0LL;\n if ( *(_DWORD *)(a1 + v5 + 4) != *(_DWORD *)(a3 + v5 + 4) )\n break;\n v5 += 8LL;\n if ( v5 == 8LL * a2 )\n return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov eax, 0\ncmp esi, ecx\njnz short locret_11BC\ntest esi, esi\njle short loc_11AB\nmovsxd rsi, esi\nlea rcx, ds:0[rsi*8]\nmov eax, 0\nloc_118A:\nmov esi, [rdx+rax]\ncmp [rdi+rax], esi\njnz short loc_11B1\nmov esi, [rdx+rax+4]\ncmp [rdi+rax+4], esi\njnz short loc_11B7\nadd rax, 8\ncmp rax, rcx\njnz short loc_118A\nmov eax, 1\nretn\nloc_11AB:\nmov eax, 1\nretn\nloc_11B1:\nmov eax, 0\nretn\nloc_11B7:\nmov eax, 0\nlocret_11BC:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, __int64 a3, int a4)\n{\n __int64 result; // rax\n __int64 v5; // rax\n\n result = 0LL;\n if ( a2 == a4 )\n {\n if ( a2 <= 0 )\n {\n return 1LL;\n }\n else\n {\n v5 = 0LL;\n while ( 1 )\n {\n if ( *(_DWORD *)(a1 + v5) != *(_DWORD *)(a3 + v5) )\n return 0LL;\n if ( *(_DWORD *)(a1 + v5 + 4) != *(_DWORD *)(a3 + v5 + 4) )\n break;\n v5 += 8LL;\n if ( v5 == 8LL * a2 )\n return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, long long a3, int a4) {\n long long result;\n long long v5;\n result = 0LL;\n if (a2 == a4) {\n if (a2 <= 0) {\n return 1LL;\n } else {\n v5 = 0LL;\n while (1) {\n if (*(uint32_t *)(a1 + v5) != *(uint32_t *)(a3 + v5)) return 0LL;\n if (*(uint32_t *)(a1 + v5 + 4) != *(uint32_t *)(a3 + v5 + 4)) break;\n v5 += 8LL;\n if (v5 == 8LL * a2) return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3, int a4) {\n long long result;\n long long v5;\n result = 0LL;\n if (a2 == a4) {\n if (a2 <= 0) {\n return 1LL;\n } else {\n v5 = 0LL;\n while (1) {\n if (*(uint32_t *)(a1 + v5) != *(uint32_t *)(a3 + v5)) return 0LL;\n if (*(uint32_t *)(a1 + v5 + 4) != *(uint32_t *)(a3 + v5 + 4)) break;\n v5 += 8LL;\n if (v5 == 8LL * a2) return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}" + }, + { + "index": 811, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int test_list1[][2], int size1, int test_list2[][2], int size2) {\n if (size1 != size2) {\n return false;\n }\n for (int i = 0; i < size1; i++) {\n if (test_list1[i][0] != test_list2[i][0] ||\n test_list1[i][1] != test_list2[i][1]) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n int list1[][2] = {{10, 4}, {2, 5}};\n\n int list2[][2] = {{10, 4}, {2, 5}};\n\n int list3[][2] = {{1, 2}, {3, 7}};\n\n int list4[][2] = {{12, 14}, {12, 45}};\n\n int list5[][2] = {{2, 14}, {12, 25}};\n\n int list6[][2] = {{2, 14}, {12, 25}};\n\n\n\n assert(func0(list1, 2, list2, 2) == true);\n\n assert(func0(list3, 2, list4, 2) == false);\n\n assert(func0(list5, 2, list6, 2) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ncmp %ecx,%esi\njne 1330 \njmp 12e0 \nnopw 0x0(%rax,%rax,1)\nxor %eax,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0_part_0:\ntest esi, esi\njle short loc_12D0\nmovsxd rsi, esi\nxor eax, eax\nlea rcx, ds:0[rsi*8]\njmp short loc_12BB\nloc_12A8:\nmov esi, [rdx+rax+4]\ncmp [rdi+rax+4], esi\njnz short loc_12C3\nadd rax, 8\ncmp rcx, rax\njz short loc_12D0\nloc_12BB:\nmov esi, [rdx+rax]\ncmp [rdi+rax], esi\njz short loc_12A8\nloc_12C3:\nxor eax, eax\nretn\nloc_12D0:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0_part_0(__int64 a1, int a2, __int64 a3)\n{\n __int64 v3; // rax\n\n if ( a2 <= 0 )\n return 1LL;\n v3 = 0LL;\n while ( *(_DWORD *)(a1 + v3) == *(_DWORD *)(a3 + v3) && *(_DWORD *)(a1 + v3 + 4) == *(_DWORD *)(a3 + v3 + 4) )\n {\n v3 += 8LL;\n if ( 8LL * a2 == v3 )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1290:\ntest esi, esi\njle short loc_12D0\nmovsxd rsi, esi\nxor eax, eax\nlea rcx, ds:0[rsi*8]\njmp short loc_12BB\nloc_12A8:\nmov esi, [rdx+rax+4]\ncmp [rdi+rax+4], esi\njnz short loc_12C3\nadd rax, 8\ncmp rcx, rax\njz short loc_12D0\nloc_12BB:\nmov esi, [rdx+rax]\ncmp [rdi+rax], esi\njz short loc_12A8\nloc_12C3:\nxor eax, eax\nretn\nloc_12D0:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1290(__int64 a1, int a2, __int64 a3)\n{\n __int64 v3; // rax\n\n if ( a2 <= 0 )\n return 1LL;\n v3 = 0LL;\n while ( *(_DWORD *)(a1 + v3) == *(_DWORD *)(a3 + v3) && *(_DWORD *)(a1 + v3 + 4) == *(_DWORD *)(a3 + v3 + 4) )\n {\n v3 += 8LL;\n if ( 8LL * a2 == v3 )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1290(long long a1, int a2, long long a3) {\n long long v3;\n if (a2 <= 0) return 1LL;\n v3 = 0LL;\n while (*(uint32_t *)(a1 + v3) == *(uint32_t *)(a3 + v3) &&\n *(uint32_t *)(a1 + v3 + 4) == *(uint32_t *)(a3 + v3 + 4)) {\n v3 += 8LL;\n if (8LL * a2 == v3) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0_part_0(long long a1, int a2, long long a3) {\n long long v3;\n if (a2 <= 0) return 1LL;\n v3 = 0LL;\n while (*(uint32_t *)(a1 + v3) == *(uint32_t *)(a3 + v3) &&\n *(uint32_t *)(a1 + v3 + 4) == *(uint32_t *)(a3 + v3 + 4)) {\n v3 += 8LL;\n if (8LL * a2 == v3) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 811, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int test_list1[][2], int size1, int test_list2[][2], int size2) {\n if (size1 != size2) {\n return false;\n }\n for (int i = 0; i < size1; i++) {\n if (test_list1[i][0] != test_list2[i][0] ||\n test_list1[i][1] != test_list2[i][1]) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n int list1[][2] = {{10, 4}, {2, 5}};\n\n int list2[][2] = {{10, 4}, {2, 5}};\n\n int list3[][2] = {{1, 2}, {3, 7}};\n\n int list4[][2] = {{12, 14}, {12, 45}};\n\n int list5[][2] = {{2, 14}, {12, 25}};\n\n int list6[][2] = {{2, 14}, {12, 25}};\n\n\n\n assert(func0(list1, 2, list2, 2) == true);\n\n assert(func0(list3, 2, list4, 2) == false);\n\n assert(func0(list5, 2, list6, 2) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nxor %eax,%eax\ncmp %ecx,%esi\njne 1308 \ntest %esi,%esi\njle 1310 \nsub $0x1,%esi\nxor %eax,%eax\njmp 12fe \nnopl (%rax)\nmov 0x4(%rdx,%rax,8),%ecx\ncmp %ecx,0x4(%rdi,%rax,8)\njne 1306 \nlea 0x1(%rax),%rcx\ncmp %rsi,%rax\nje 1310 \nmov %rcx,%rax\nmov (%rdx,%rax,8),%ecx\ncmp %ecx,(%rdi,%rax,8)\nje 12e8 \nxor %eax,%eax\nretq\nnopl 0x0(%rax)\nmov $0x1,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0_part_0:\ntest esi, esi\njle short loc_12D0\nmovsxd rsi, esi\nxor eax, eax\nlea rcx, ds:0[rsi*8]\njmp short loc_12BB\nloc_12A8:\nmov esi, [rdx+rax+4]\ncmp [rdi+rax+4], esi\njnz short loc_12C3\nadd rax, 8\ncmp rcx, rax\njz short loc_12D0\nloc_12BB:\nmov esi, [rdx+rax]\ncmp [rdi+rax], esi\njz short loc_12A8\nloc_12C3:\nxor eax, eax\nretn\nloc_12D0:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0_part_0(__int64 a1, int a2, __int64 a3)\n{\n __int64 v3; // rax\n\n if ( a2 <= 0 )\n return 1LL;\n v3 = 0LL;\n while ( *(_DWORD *)(a1 + v3) == *(_DWORD *)(a3 + v3) && *(_DWORD *)(a1 + v3 + 4) == *(_DWORD *)(a3 + v3 + 4) )\n {\n v3 += 8LL;\n if ( 8LL * a2 == v3 )\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1290:\ntest esi, esi\njle short loc_12D0\nmovsxd rsi, esi\nxor eax, eax\nlea rcx, ds:0[rsi*8]\njmp short loc_12BB\nloc_12A8:\nmov esi, [rdx+rax+4]\ncmp [rdi+rax+4], esi\njnz short loc_12C3\nadd rax, 8\ncmp rcx, rax\njz short loc_12D0\nloc_12BB:\nmov esi, [rdx+rax]\ncmp [rdi+rax], esi\njz short loc_12A8\nloc_12C3:\nxor eax, eax\nretn\nloc_12D0:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1290(__int64 a1, int a2, __int64 a3)\n{\n __int64 v3; // rax\n\n if ( a2 <= 0 )\n return 1LL;\n v3 = 0LL;\n while ( *(_DWORD *)(a1 + v3) == *(_DWORD *)(a3 + v3) && *(_DWORD *)(a1 + v3 + 4) == *(_DWORD *)(a3 + v3 + 4) )\n {\n v3 += 8LL;\n if ( 8LL * a2 == v3 )\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1290(long long a1, int a2, long long a3) {\n long long v3;\n if (a2 <= 0) return 1LL;\n v3 = 0LL;\n while (*(uint32_t *)(a1 + v3) == *(uint32_t *)(a3 + v3) &&\n *(uint32_t *)(a1 + v3 + 4) == *(uint32_t *)(a3 + v3 + 4)) {\n v3 += 8LL;\n if (8LL * a2 == v3) return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0_part_0(long long a1, int a2, long long a3) {\n long long v3;\n if (a2 <= 0) return 1LL;\n v3 = 0LL;\n while (*(uint32_t *)(a1 + v3) == *(uint32_t *)(a3 + v3) &&\n *(uint32_t *)(a1 + v3 + 4) == *(uint32_t *)(a3 + v3 + 4)) {\n v3 += 8LL;\n if (8LL * a2 == v3) return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 812, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* street) {\n int length = strlen(street);\n if (length > 4 && strcmp(&street[length - 4], \"Road\") == 0) {\n street[length - 4] = '\\0';\n strcat(street, \"Rd.\");\n }\n return street;\n}", + "test": "int main() {\n\n char street1[] = \"ravipadu Road\";\n\n char street2[] = \"palnadu Road\";\n\n char street3[] = \"eshwar enclave Road\";\n\n \n\n assert(strcmp(func0(street1), \"ravipadu Rd.\") == 0);\n\n assert(strcmp(func0(street2), \"palnadu Rd.\") == 0);\n\n assert(strcmp(func0(street3), \"eshwar enclave Rd.\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov -0x18(%rbp),%rax\nmov %rax,%rdi\ncallq 1080 \nmov %eax,-0x4(%rbp)\ncmpl $0x4,-0x4(%rbp)\njle 1233 \nmov -0x4(%rbp),%eax\ncltq\nlea -0x4(%rax),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nlea 0xe23(%rip),%rsi\nmov %rax,%rdi\ncallq 10b0 \ntest %eax,%eax\njne 1233 \nmov -0x4(%rbp),%eax\ncltq\nlea -0x4(%rax),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovb $0x0,(%rax)\nmov -0x18(%rbp),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovl $0x2e6452,(%rax)\nmov -0x18(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\ncmp [rbp+var_4], 4\njle short loc_1223\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, [rax-4]\nmov rax, [rbp+s]\nadd rax, rdx\nlea rdx, s2; \"Road\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1223\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, [rax-4]\nmov rax, [rbp+s]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+s]\nadd rax, rdx\nmov dword ptr [rax], 2E6452h\nloc_1223:\nmov rax, [rbp+s]\nleave\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n int v2; // [rsp+1Ch] [rbp-4h]\n\n v2 = strlen(a1);\n if ( v2 > 4 && !strcmp(&a1[v2 - 4], \"Road\") )\n {\n a1[v2 - 4] = 0;\n *(_DWORD *)&a1[strlen(a1)] = 3040338;\n }\n return a1;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\ncmp [rbp+var_4], 4\njle short loc_1223\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, [rax-4]\nmov rax, [rbp+s]\nadd rax, rdx\nlea rdx, s2; \"Road\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1223\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, [rax-4]\nmov rax, [rbp+s]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+s]\nadd rax, rdx\nmov dword ptr [rax], 2E6452h\nloc_1223:\nmov rax, [rbp+s]\nleave\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_11A9(const char *a1)\n{\n int v2; // [rsp+1Ch] [rbp-4h]\n\n v2 = strlen(a1);\n if ( v2 > 4 && !strcmp(&a1[v2 - 4], \"Road\") )\n {\n a1[v2 - 4] = 0;\n *(_DWORD *)&a1[strlen(a1)] = 3040338;\n }\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_11A9(const char *a1) {\n int v2;\n v2 = strlen(a1);\n if (v2 > 4 && !strcmp(&a1[v2 - 4], \"Road\")) {\n a1[v2 - 4] = 0;\n *(uint32_t *)&a1[strlen(a1)] = 3040338;\n }\n return a1;\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n int v2;\n v2 = strlen(a1);\n if (v2 > 4 && !strcmp(&a1[v2 - 4], \"Road\")) {\n a1[v2 - 4] = 0;\n *(uint32_t *)&a1[strlen(a1)] = 3040338;\n }\n return a1;\n}" + }, + { + "index": 812, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* street) {\n int length = strlen(street);\n if (length > 4 && strcmp(&street[length - 4], \"Road\") == 0) {\n street[length - 4] = '\\0';\n strcat(street, \"Rd.\");\n }\n return street;\n}", + "test": "int main() {\n\n char street1[] = \"ravipadu Road\";\n\n char street2[] = \"palnadu Road\";\n\n char street3[] = \"eshwar enclave Road\";\n\n \n\n assert(strcmp(func0(street1), \"ravipadu Rd.\") == 0);\n\n assert(strcmp(func0(street2), \"palnadu Rd.\") == 0);\n\n assert(strcmp(func0(street3), \"eshwar enclave Rd.\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%rdx\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nsub $0x1,%rcx\ncmp $0x4,%ecx\njle 11ac \nmovslq %ecx,%rcx\nlea -0x4(%rdx,%rcx,1),%r8\nmov $0x5,%ecx\nlea 0xe66(%rip),%rdi\nmov %r8,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %al\nsbb $0x0,%al\ntest %al,%al\nje 11b0 \nmov %rdx,%rax\nretq\nmovb $0x0,(%r8)\nmov $0xffffffffffffffff,%rcx\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nnot %rcx\nmovl $0x2e6452,-0x1(%rdx,%rcx,1)\njmp 11ac \n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\ncall _strlen\ncmp eax, 4\njle short loc_11DA\ncdqe\nlea rbp, [rbx+rax-4]\nlea rsi, s2; \"Road\"\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njz short loc_11E4\nloc_11DA:\nmov rax, rbx\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_11E4:\nmov byte ptr [rbp+0], 0\nmov rdi, rbx; s\ncall _strlen\nmov dword ptr [rbx+rax], 2E6452h\njmp short loc_11DA", + "ida_pseudo": "char *__fastcall func0(char *s)\n{\n int v1; // eax\n char *v2; // rbp\n\n v1 = strlen(s);\n if ( v1 > 4 )\n {\n v2 = &s[v1 - 4];\n if ( !strcmp(v2, \"Road\") )\n {\n *v2 = 0;\n *(_DWORD *)&s[strlen(s)] = 3040338;\n }\n }\n return s;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\ncall _strlen\ncmp eax, 4\njle short loc_11DA\ncdqe\nlea rbp, [rbx+rax-4]\nlea rsi, s2; \"Road\"\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njz short loc_11E4\nloc_11DA:\nmov rax, rbx\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_11E4:\nmov byte ptr [rbp+0], 0\nmov rdi, rbx; s\ncall _strlen\nmov dword ptr [rbx+rax], 2E6452h\njmp short loc_11DA", + "ida_strip_pseudo": "char *__fastcall sub_11A9(char *s)\n{\n int v1; // eax\n char *v2; // rbp\n\n v1 = strlen(s);\n if ( v1 > 4 )\n {\n v2 = &s[v1 - 4];\n if ( !strcmp(v2, \"Road\") )\n {\n *v2 = 0;\n *(_DWORD *)&s[strlen(s)] = 3040338;\n }\n }\n return s;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11A9(char *s) {\n int v1;\n char *v2;\n v1 = strlen(s);\n if (v1 > 4) {\n v2 = &s[v1 - 4];\n if (!strcmp(v2, \"Road\")) {\n *v2 = 0;\n *(uint32_t *)&s[strlen(s)] = 3040338;\n }\n }\n return s;\n}", + "ida_pseudo_norm": "char *func0(char *s) {\n int v1;\n char *v2;\n v1 = strlen(s);\n if (v1 > 4) {\n v2 = &s[v1 - 4];\n if (!strcmp(v2, \"Road\")) {\n *v2 = 0;\n *(uint32_t *)&s[strlen(s)] = 3040338;\n }\n }\n return s;\n}" + }, + { + "index": 812, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* street) {\n int length = strlen(street);\n if (length > 4 && strcmp(&street[length - 4], \"Road\") == 0) {\n street[length - 4] = '\\0';\n strcat(street, \"Rd.\");\n }\n return street;\n}", + "test": "int main() {\n\n char street1[] = \"ravipadu Road\";\n\n char street2[] = \"palnadu Road\";\n\n char street3[] = \"eshwar enclave Road\";\n\n \n\n assert(strcmp(func0(street1), \"ravipadu Rd.\") == 0);\n\n assert(strcmp(func0(street2), \"palnadu Rd.\") == 0);\n\n assert(strcmp(func0(street3), \"eshwar enclave Rd.\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %rdi,%r12\ncallq 1070 \ncmp $0x4,%eax\njle 1314 \ncltq\nmov $0x5,%ecx\nlea 0xd03(%rip),%rdi\nlea -0x4(%r12,%rax,1),%rdx\nmov %rdx,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %al\nsbb $0x0,%al\ntest %al,%al\nje 1320 \nmov %r12,%rax\npop %r12\nretq\nnopw 0x0(%rax,%rax,1)\nmovb $0x0,(%rdx)\nmov %r12,%rdi\ncallq 1070 \nmovl $0x2e6452,(%r12,%rax,1)\nmov %r12,%rax\npop %r12\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\ncmp eax, 4\njle short loc_1311\ncdqe\nlea rsi, aRoad; \"Road\"\nlea rbp, [rbx+rax-4]\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njz short loc_1320\nloc_1311:\nadd rsp, 8\nmov rax, rbx\npop rbx\npop rbp\nretn\nloc_1320:\nmov byte ptr [rbp+0], 0\nmov rdi, rbx; s\ncall _strlen\nmov dword ptr [rbx+rax], 2E6452h\nadd rsp, 8\nmov rax, rbx\npop rbx\npop rbp\nretn", + "ida_pseudo": "char *__fastcall func0(char *s)\n{\n int v1; // eax\n const char *v2; // rbp\n\n v1 = strlen(s);\n if ( v1 <= 4 )\n return s;\n v2 = &s[v1 - 4];\n if ( strcmp(v2, \"Road\") )\n return s;\n *v2 = 0;\n *(_DWORD *)&s[strlen(s)] = 3040338;\n return s;\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\ncmp eax, 4\njle short loc_1311\ncdqe\nlea rsi, aRoad; \"Road\"\nlea rbp, [rbx+rax-4]\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njz short loc_1320\nloc_1311:\nadd rsp, 8\nmov rax, rbx\npop rbx\npop rbp\nretn\nloc_1320:\nmov byte ptr [rbp+0], 0\nmov rdi, rbx; s\ncall _strlen\nmov dword ptr [rbx+rax], 2E6452h\nadd rsp, 8\nmov rax, rbx\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "char *__fastcall sub_12E0(char *s)\n{\n int v1; // eax\n const char *v2; // rbp\n\n v1 = strlen(s);\n if ( v1 <= 4 )\n return s;\n v2 = &s[v1 - 4];\n if ( strcmp(v2, \"Road\") )\n return s;\n *v2 = 0;\n *(_DWORD *)&s[strlen(s)] = 3040338;\n return s;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_12E0(char *s) {\n int v1;\n const char *v2;\n v1 = strlen(s);\n if (v1 <= 4) return s;\n v2 = &s[v1 - 4];\n if (strcmp(v2, \"Road\")) return s;\n *v2 = 0;\n *(uint32_t *)&s[strlen(s)] = 3040338;\n return s;\n}", + "ida_pseudo_norm": "char *func0(char *s) {\n int v1;\n const char *v2;\n v1 = strlen(s);\n if (v1 <= 4) return s;\n v2 = &s[v1 - 4];\n if (strcmp(v2, \"Road\")) return s;\n *v2 = 0;\n *(uint32_t *)&s[strlen(s)] = 3040338;\n return s;\n}" + }, + { + "index": 812, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* street) {\n int length = strlen(street);\n if (length > 4 && strcmp(&street[length - 4], \"Road\") == 0) {\n street[length - 4] = '\\0';\n strcat(street, \"Rd.\");\n }\n return street;\n}", + "test": "int main() {\n\n char street1[] = \"ravipadu Road\";\n\n char street2[] = \"palnadu Road\";\n\n char street3[] = \"eshwar enclave Road\";\n\n \n\n assert(strcmp(func0(street1), \"ravipadu Rd.\") == 0);\n\n assert(strcmp(func0(street2), \"palnadu Rd.\") == 0);\n\n assert(strcmp(func0(street3), \"eshwar enclave Rd.\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %rdi,%r12\ncallq 1070 \ncmp $0x4,%eax\njle 1314 \ncltq\nmov $0x5,%ecx\nlea 0xd03(%rip),%rdi\nlea -0x4(%r12,%rax,1),%rdx\nmov %rdx,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %al\nsbb $0x0,%al\ntest %al,%al\nje 1320 \nmov %r12,%rax\npop %r12\nretq\nnopw 0x0(%rax,%rax,1)\nmovb $0x0,(%rdx)\nmov %r12,%rdi\ncallq 1070 \nmovl $0x2e6452,(%r12,%rax,1)\nmov %r12,%rax\npop %r12\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\ncmp eax, 4\njle short loc_1311\ncdqe\nlea rsi, aRoad; \"Road\"\nlea rbp, [rbx+rax-4]\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njz short loc_1320\nloc_1311:\nadd rsp, 8\nmov rax, rbx\npop rbx\npop rbp\nretn\nloc_1320:\nmov byte ptr [rbp+0], 0\nmov rdi, rbx; s\ncall _strlen\nmov dword ptr [rbx+rax], 2E6452h\nadd rsp, 8\nmov rax, rbx\npop rbx\npop rbp\nretn", + "ida_pseudo": "char *__fastcall func0(char *s)\n{\n int v1; // eax\n const char *v2; // rbp\n\n v1 = strlen(s);\n if ( v1 <= 4 )\n return s;\n v2 = &s[v1 - 4];\n if ( strcmp(v2, \"Road\") )\n return s;\n *v2 = 0;\n *(_DWORD *)&s[strlen(s)] = 3040338;\n return s;\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\ncmp eax, 4\njle short loc_1311\ncdqe\nlea rsi, aRoad; \"Road\"\nlea rbp, [rbx+rax-4]\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njz short loc_1320\nloc_1311:\nadd rsp, 8\nmov rax, rbx\npop rbx\npop rbp\nretn\nloc_1320:\nmov byte ptr [rbp+0], 0\nmov rdi, rbx; s\ncall _strlen\nmov dword ptr [rbx+rax], 2E6452h\nadd rsp, 8\nmov rax, rbx\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "char *__fastcall sub_12E0(char *s)\n{\n int v1; // eax\n const char *v2; // rbp\n\n v1 = strlen(s);\n if ( v1 <= 4 )\n return s;\n v2 = &s[v1 - 4];\n if ( strcmp(v2, \"Road\") )\n return s;\n *v2 = 0;\n *(_DWORD *)&s[strlen(s)] = 3040338;\n return s;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_12E0(char *s) {\n int v1;\n const char *v2;\n v1 = strlen(s);\n if (v1 <= 4) return s;\n v2 = &s[v1 - 4];\n if (strcmp(v2, \"Road\")) return s;\n *v2 = 0;\n *(uint32_t *)&s[strlen(s)] = 3040338;\n return s;\n}", + "ida_pseudo_norm": "char *func0(char *s) {\n int v1;\n const char *v2;\n v1 = strlen(s);\n if (v1 <= 4) return s;\n v2 = &s[v1 - 4];\n if (strcmp(v2, \"Road\")) return s;\n *v2 = 0;\n *(uint32_t *)&s[strlen(s)] = 3040338;\n return s;\n}" + }, + { + "index": 813, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(const char *str1) {\n int count = 0;\n while (*str1 != '\\0') {\n count++;\n str1++;\n }\n return count;\n}", + "test": "int main() {\n\n assert(func0(\"python\") == 6);\n\n assert(func0(\"program\") == 7);\n\n assert(func0(\"language\") == 8);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 1167 \naddl $0x1,-0x4(%rbp)\naddq $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 115e \nmov -0x4(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_4], 0\njmp short loc_1167\nloc_115E:\nadd [rbp+var_4], 1\nadd [rbp+var_18], 1\nloc_1167:\nmov rax, [rbp+var_18]\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_115E\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(_BYTE *a1)\n{\n unsigned int v3; // [rsp+14h] [rbp-4h]\n\n v3 = 0;\n while ( *a1 )\n {\n ++v3;\n ++a1;\n }\n return v3;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_4], 0\njmp short loc_1167\nloc_115E:\nadd [rbp+var_4], 1\nadd [rbp+var_18], 1\nloc_1167:\nmov rax, [rbp+var_18]\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_115E\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(_BYTE *a1)\n{\n unsigned int v3; // [rsp+14h] [rbp-4h]\n\n v3 = 0;\n while ( *a1 )\n {\n ++v3;\n ++a1;\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(uint8_t *a1) {\n unsigned int v3;\n v3 = 0;\n while (*a1) {\n ++v3;\n ++a1;\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(uint8_t *a1) {\n unsigned int v3;\n v3 = 0;\n while (*a1) {\n ++v3;\n ++a1;\n }\n return v3;\n}" + }, + { + "index": 813, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(const char *str1) {\n int count = 0;\n while (*str1 != '\\0') {\n count++;\n str1++;\n }\n return count;\n}", + "test": "int main() {\n\n assert(func0(\"python\") == 6);\n\n assert(func0(\"program\") == 7);\n\n assert(func0(\"language\") == 8);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ncmpb $0x0,(%rdi)\nje 116b \nmov %rdi,%rax\nmov $0x1,%edx\nsub %edi,%edx\nlea (%rdx,%rax,1),%ecx\nadd $0x1,%rax\ncmpb $0x0,(%rax)\njne 115c \nmov %ecx,%eax\nretq\nmov $0x0,%ecx\njmp 1168 \n", + "ida_asm": "func0:\nendbr64\ncmp byte ptr [rdi], 0\njz short loc_1167\nmov rax, rdi\nloc_1155:\nmov rdx, rax\nadd rax, 1\ncmp byte ptr [rax], 0\njnz short loc_1155\nsub edx, edi\nlea eax, [rdx+1]\nretn\nloc_1167:\nmov eax, 0\nretn", + "ida_pseudo": "__int64 __fastcall func0(_BYTE *a1)\n{\n _BYTE *v1; // rax\n int v2; // edx\n\n if ( !*a1 )\n return 0LL;\n v1 = a1;\n do\n v2 = (int)v1++;\n while ( *v1 );\n return (unsigned int)(v2 - (_DWORD)a1 + 1);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ncmp byte ptr [rdi], 0\njz short loc_1167\nmov rax, rdi\nloc_1155:\nmov rdx, rax\nadd rax, 1\ncmp byte ptr [rax], 0\njnz short loc_1155\nsub edx, edi\nlea eax, [rdx+1]\nretn\nloc_1167:\nmov eax, 0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(_BYTE *a1)\n{\n _BYTE *v1; // rax\n int v2; // edx\n\n if ( !*a1 )\n return 0LL;\n v1 = a1;\n do\n v2 = (int)v1++;\n while ( *v1 );\n return (unsigned int)(v2 - (_DWORD)a1 + 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(uint8_t *a1) {\n uint8_t *v1;\n int v2;\n if (!*a1) return 0LL;\n v1 = a1;\n do\n v2 = (int)v1++;\n while (*v1);\n return (unsigned int)(v2 - (uint32_t)a1 + 1);\n}", + "ida_pseudo_norm": "long long func0(uint8_t *a1) {\n uint8_t *v1;\n int v2;\n if (!*a1) return 0LL;\n v1 = a1;\n do\n v2 = (int)v1++;\n while (*v1);\n return (unsigned int)(v2 - (uint32_t)a1 + 1);\n}" + }, + { + "index": 814, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "double func0(double p, double q) {\n double area = (p * q) / 2;\n return area;\n}", + "test": "int main() {\n\n assert(func0(10, 20) == 100);\n\n assert(func0(10, 5) == 25);\n\n assert(func0(4, 2) == 4);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmovsd %xmm0,-0x18(%rbp)\nmovsd %xmm1,-0x20(%rbp)\nmovsd -0x18(%rbp),%xmm0\nmulsd -0x20(%rbp),%xmm0\nmovsd 0xf1b(%rip),%xmm1\ndivsd %xmm1,%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmovsd -0x8(%rbp),%xmm0\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmovsd [rbp+var_18], xmm0\nmovsd [rbp+var_20], xmm1\nmovsd xmm0, [rbp+var_18]\nmulsd xmm0, [rbp+var_20]\nmovsd xmm1, cs:qword_2068\ndivsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "double __fastcall func0(double a1, double a2)\n{\n return a1 * a2 / 2.0;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmovsd [rbp+var_18], xmm0\nmovsd [rbp+var_20], xmm1\nmovsd xmm0, [rbp+var_18]\nmulsd xmm0, [rbp+var_20]\nmovsd xmm1, cs:qword_2068\ndivsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "double __fastcall sub_1149(double a1, double a2)\n{\n return a1 * a2 / 2.0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1149(double a1, double a2) { return a1 * a2 / 2.0; }", + "ida_pseudo_norm": "double func0(double a1, double a2) { return a1 * a2 / 2.0; }" + }, + { + "index": 815, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "void func0(int arr[], int n) {\n int low = 0;\n int mid = 0;\n int high = n - 1;\n while (mid <= high) {\n if (arr[mid] == 0) {\n int temp = arr[low];\n arr[low] = arr[mid];\n arr[mid] = temp;\n low++;\n mid++;\n } else if (arr[mid] == 1) {\n mid++;\n } else {\n int temp = arr[mid];\n arr[mid] = arr[high];\n arr[high] = temp;\n high--;\n }\n }\n}", + "test": "int main() {\n\n int arr1[9] = {1,2,0,1,0,1,2,1,1};\n\n func0(arr1, 9);\n\n int expected_arr1[9] = {0, 0, 1, 1, 1, 1, 1, 2, 2};\n\n for (int i = 0; i < 9; i++)\n\n assert(arr1[i] == expected_arr1[i]);\n\n\n\n int arr2[10] = {1,0,0,1,2,1,2,2,1,0};\n\n func0(arr2, 10);\n\n int expected_arr2[10] = {0, 0, 0, 1, 1, 1, 1, 2, 2, 2};\n\n for (int i = 0; i < 10; i++)\n\n assert(arr2[i] == expected_arr2[i]);\n\n\n\n int arr3[10] = {2,2,1,0,0,0,1,1,2,1};\n\n func0(arr3, 10);\n\n int expected_arr3[10] = {0, 0, 0, 1, 1, 1, 1, 2, 2, 2};\n\n for (int i = 0; i < 10; i++)\n\n assert(arr3[i] == expected_arr3[i]);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmovl $0x0,-0x14(%rbp)\nmovl $0x0,-0x10(%rbp)\nmov -0x2c(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0xc(%rbp)\njmpq 129e \nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ntest %eax,%eax\njne 121a \nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x4(%rbp)\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov -0x14(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x28(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rax,%rdx\nmov -0x4(%rbp),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x14(%rbp)\naddl $0x1,-0x10(%rbp)\njmpq 129e \nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp $0x1,%eax\njne 123b \naddl $0x1,-0x10(%rbp)\njmp 129e \nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x8(%rbp)\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov -0x10(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x28(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rax,%rdx\nmov -0x8(%rbp),%eax\nmov %eax,(%rdx)\nsubl $0x1,-0xc(%rbp)\nmov -0x10(%rbp),%eax\ncmp -0xc(%rbp),%eax\njle 1194 \npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\nmov eax, [rbp+var_2C]\nsub eax, 1\nmov [rbp+var_C], eax\njmp loc_129E\nloc_1194:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njnz short loc_121A\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nadd [rbp+var_14], 1\nadd [rbp+var_10], 1\njmp loc_129E\nloc_121A:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\ncmp eax, 1\njnz short loc_123B\nadd [rbp+var_10], 1\njmp short loc_129E\nloc_123B:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_8], eax\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov eax, [rbp+var_8]\nmov [rdx], eax\nsub [rbp+var_C], 1\nloc_129E:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_C]\njle loc_1194\nnop\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 result; // rax\n int v3; // [rsp+18h] [rbp-14h]\n unsigned int v4; // [rsp+1Ch] [rbp-10h]\n int v5; // [rsp+20h] [rbp-Ch]\n int v6; // [rsp+24h] [rbp-8h]\n int v7; // [rsp+28h] [rbp-4h]\n\n v3 = 0;\n v4 = 0;\n v5 = a2 - 1;\n while ( 1 )\n {\n result = v4;\n if ( (int)v4 > v5 )\n break;\n if ( *(_DWORD *)(4LL * (int)v4 + a1) )\n {\n if ( *(_DWORD *)(4LL * (int)v4 + a1) == 1 )\n {\n ++v4;\n }\n else\n {\n v6 = *(_DWORD *)(4LL * (int)v4 + a1);\n *(_DWORD *)(4LL * (int)v4 + a1) = *(_DWORD *)(4LL * v5 + a1);\n *(_DWORD *)(a1 + 4LL * v5--) = v6;\n }\n }\n else\n {\n v7 = *(_DWORD *)(4LL * v3 + a1);\n *(_DWORD *)(4LL * v3 + a1) = *(_DWORD *)(4LL * (int)v4 + a1);\n *(_DWORD *)(a1 + 4LL * (int)v4) = v7;\n ++v3;\n ++v4;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\nmov eax, [rbp+var_2C]\nsub eax, 1\nmov [rbp+var_C], eax\njmp loc_129E\nloc_1194:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njnz short loc_121A\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nadd [rbp+var_14], 1\nadd [rbp+var_10], 1\njmp loc_129E\nloc_121A:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\ncmp eax, 1\njnz short loc_123B\nadd [rbp+var_10], 1\njmp short loc_129E\nloc_123B:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_8], eax\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov eax, [rbp+var_8]\nmov [rdx], eax\nsub [rbp+var_C], 1\nloc_129E:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_C]\njle loc_1194\nnop\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n __int64 result; // rax\n int v3; // [rsp+18h] [rbp-14h]\n unsigned int v4; // [rsp+1Ch] [rbp-10h]\n int v5; // [rsp+20h] [rbp-Ch]\n int v6; // [rsp+24h] [rbp-8h]\n int v7; // [rsp+28h] [rbp-4h]\n\n v3 = 0;\n v4 = 0;\n v5 = a2 - 1;\n while ( 1 )\n {\n result = v4;\n if ( (int)v4 > v5 )\n break;\n if ( *(_DWORD *)(4LL * (int)v4 + a1) )\n {\n if ( *(_DWORD *)(4LL * (int)v4 + a1) == 1 )\n {\n ++v4;\n }\n else\n {\n v6 = *(_DWORD *)(4LL * (int)v4 + a1);\n *(_DWORD *)(4LL * (int)v4 + a1) = *(_DWORD *)(4LL * v5 + a1);\n *(_DWORD *)(a1 + 4LL * v5--) = v6;\n }\n }\n else\n {\n v7 = *(_DWORD *)(4LL * v3 + a1);\n *(_DWORD *)(4LL * v3 + a1) = *(_DWORD *)(4LL * (int)v4 + a1);\n *(_DWORD *)(a1 + 4LL * (int)v4) = v7;\n ++v3;\n ++v4;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n long long result;\n int v3;\n unsigned int v4;\n int v5;\n int v6;\n int v7;\n v3 = 0;\n v4 = 0;\n v5 = a2 - 1;\n while (1) {\n result = v4;\n if ((int)v4 > v5) break;\n if (*(uint32_t *)(4LL * (int)v4 + a1)) {\n if (*(uint32_t *)(4LL * (int)v4 + a1) == 1) {\n ++v4;\n } else {\n v6 = *(uint32_t *)(4LL * (int)v4 + a1);\n *(uint32_t *)(4LL * (int)v4 + a1) = *(uint32_t *)(4LL * v5 + a1);\n *(uint32_t *)(a1 + 4LL * v5--) = v6;\n }\n } else {\n v7 = *(uint32_t *)(4LL * v3 + a1);\n *(uint32_t *)(4LL * v3 + a1) = *(uint32_t *)(4LL * (int)v4 + a1);\n *(uint32_t *)(a1 + 4LL * (int)v4) = v7;\n ++v3;\n ++v4;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long result;\n int v3;\n unsigned int v4;\n int v5;\n int v6;\n int v7;\n v3 = 0;\n v4 = 0;\n v5 = a2 - 1;\n while (1) {\n result = v4;\n if ((int)v4 > v5) break;\n if (*(uint32_t *)(4LL * (int)v4 + a1)) {\n if (*(uint32_t *)(4LL * (int)v4 + a1) == 1) {\n ++v4;\n } else {\n v6 = *(uint32_t *)(4LL * (int)v4 + a1);\n *(uint32_t *)(4LL * (int)v4 + a1) = *(uint32_t *)(4LL * v5 + a1);\n *(uint32_t *)(a1 + 4LL * v5--) = v6;\n }\n } else {\n v7 = *(uint32_t *)(4LL * v3 + a1);\n *(uint32_t *)(4LL * v3 + a1) = *(uint32_t *)(4LL * (int)v4 + a1);\n *(uint32_t *)(a1 + 4LL * (int)v4) = v7;\n ++v3;\n ++v4;\n }\n }\n return result;\n}" + }, + { + "index": 815, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "void func0(int arr[], int n) {\n int low = 0;\n int mid = 0;\n int high = n - 1;\n while (mid <= high) {\n if (arr[mid] == 0) {\n int temp = arr[low];\n arr[low] = arr[mid];\n arr[mid] = temp;\n low++;\n mid++;\n } else if (arr[mid] == 1) {\n mid++;\n } else {\n int temp = arr[mid];\n arr[mid] = arr[high];\n arr[high] = temp;\n high--;\n }\n }\n}", + "test": "int main() {\n\n int arr1[9] = {1,2,0,1,0,1,2,1,1};\n\n func0(arr1, 9);\n\n int expected_arr1[9] = {0, 0, 1, 1, 1, 1, 1, 2, 2};\n\n for (int i = 0; i < 9; i++)\n\n assert(arr1[i] == expected_arr1[i]);\n\n\n\n int arr2[10] = {1,0,0,1,2,1,2,2,1,0};\n\n func0(arr2, 10);\n\n int expected_arr2[10] = {0, 0, 0, 1, 1, 1, 1, 2, 2, 2};\n\n for (int i = 0; i < 10; i++)\n\n assert(arr2[i] == expected_arr2[i]);\n\n\n\n int arr3[10] = {2,2,1,0,0,0,1,1,2,1};\n\n func0(arr3, 10);\n\n int expected_arr3[10] = {0, 0, 0, 1, 1, 1, 1, 2, 2, 2};\n\n for (int i = 0; i < 10; i++)\n\n assert(arr3[i] == expected_arr3[i]);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x1,%esi\njs 11c9 \nmov $0x0,%eax\nmov $0x0,%r8d\njmp 119b \ncmp $0x1,%edx\nje 11c4 \nmovslq %esi,%r9\nlea (%rdi,%r9,4),%r9\nmov (%r9),%r10d\nmov %r10d,(%rcx)\nmov %edx,(%r9)\nsub $0x1,%esi\ncmp %esi,%eax\njg 11c9 \nmovslq %eax,%rdx\nlea (%rdi,%rdx,4),%rcx\nmov (%rcx),%edx\ntest %edx,%edx\njne 117f \nmovslq %r8d,%rdx\nlea (%rdi,%rdx,4),%rdx\nmov (%rdx),%r9d\nmovl $0x0,(%rdx)\nmov %r9d,(%rcx)\nadd $0x1,%r8d\nadd $0x1,%eax\njmp 1197 \nadd $0x1,%eax\njmp 1197 \nretq\n", + "ida_asm": "func0:\nendbr64\nsub esi, 1\njs short locret_11C9\nmov eax, 0\nmov r8d, 0\njmp short loc_119B\nloc_117F:\ncmp edx, 1\njz short loc_11C4\nmovsxd r9, esi\nlea r9, [rdi+r9*4]\nmov r10d, [r9]\nmov [rcx], r10d\nmov [r9], edx\nsub esi, 1\nloc_1197:\ncmp eax, esi\njg short locret_11C9\nloc_119B:\nmovsxd rdx, eax\nlea rcx, [rdi+rdx*4]\nmov edx, [rcx]\ntest edx, edx\njnz short loc_117F\nmovsxd rdx, r8d\nlea rdx, [rdi+rdx*4]\nmov r9d, [rdx]\nmov dword ptr [rdx], 0\nmov [rcx], r9d\nadd r8d, 1\nadd eax, 1\njmp short loc_1197\nloc_11C4:\nadd eax, 1\njmp short loc_1197\nlocret_11C9:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2)\n{\n int v2; // esi\n int v3; // eax\n int v4; // r8d\n int *v5; // r9\n int *v6; // rcx\n int v7; // edx\n int *v8; // rdx\n int v9; // r9d\n\n v2 = a2 - 1;\n if ( v2 >= 0 )\n {\n v3 = 0;\n v4 = 0;\n do\n {\n v6 = (int *)(a1 + 4LL * v3);\n v7 = *v6;\n if ( *v6 )\n {\n if ( v7 == 1 )\n {\n ++v3;\n }\n else\n {\n v5 = (int *)(a1 + 4LL * v2);\n *v6 = *v5;\n *v5 = v7;\n --v2;\n }\n }\n else\n {\n v8 = (int *)(a1 + 4LL * v4);\n v9 = *v8;\n *v8 = 0;\n *v6 = v9;\n ++v4;\n ++v3;\n }\n }\n while ( v3 <= v2 );\n }\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nsub esi, 1\njs short locret_11C9\nmov eax, 0\nmov r8d, 0\njmp short loc_119B\nloc_117F:\ncmp edx, 1\njz short loc_11C4\nmovsxd r9, esi\nlea r9, [rdi+r9*4]\nmov r10d, [r9]\nmov [rcx], r10d\nmov [r9], edx\nsub esi, 1\nloc_1197:\ncmp eax, esi\njg short locret_11C9\nloc_119B:\nmovsxd rdx, eax\nlea rcx, [rdi+rdx*4]\nmov edx, [rcx]\ntest edx, edx\njnz short loc_117F\nmovsxd rdx, r8d\nlea rdx, [rdi+rdx*4]\nmov r9d, [rdx]\nmov dword ptr [rdx], 0\nmov [rcx], r9d\nadd r8d, 1\nadd eax, 1\njmp short loc_1197\nloc_11C4:\nadd eax, 1\njmp short loc_1197\nlocret_11C9:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1169(__int64 a1, int a2)\n{\n int v2; // esi\n int v3; // eax\n int v4; // r8d\n int *v5; // r9\n int *v6; // rcx\n int v7; // edx\n int *v8; // rdx\n int v9; // r9d\n\n v2 = a2 - 1;\n if ( v2 >= 0 )\n {\n v3 = 0;\n v4 = 0;\n do\n {\n v6 = (int *)(a1 + 4LL * v3);\n v7 = *v6;\n if ( *v6 )\n {\n if ( v7 == 1 )\n {\n ++v3;\n }\n else\n {\n v5 = (int *)(a1 + 4LL * v2);\n *v6 = *v5;\n *v5 = v7;\n --v2;\n }\n }\n else\n {\n v8 = (int *)(a1 + 4LL * v4);\n v9 = *v8;\n *v8 = 0;\n *v6 = v9;\n ++v4;\n ++v3;\n }\n }\n while ( v3 <= v2 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1169(long long a1, int a2) {\n int v2;\n int v3;\n int v4;\n int *v5;\n int *v6;\n int v7;\n int *v8;\n int v9;\n v2 = a2 - 1;\n if (v2 >= 0) {\n v3 = 0;\n v4 = 0;\n do {\n v6 = (int *)(a1 + 4LL * v3);\n v7 = *v6;\n if (*v6) {\n if (v7 == 1) {\n ++v3;\n } else {\n v5 = (int *)(a1 + 4LL * v2);\n *v6 = *v5;\n *v5 = v7;\n --v2;\n }\n } else {\n v8 = (int *)(a1 + 4LL * v4);\n v9 = *v8;\n *v8 = 0;\n *v6 = v9;\n ++v4;\n ++v3;\n }\n } while (v3 <= v2);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2) {\n int v2;\n int v3;\n int v4;\n int *v5;\n int *v6;\n int v7;\n int *v8;\n int v9;\n v2 = a2 - 1;\n if (v2 >= 0) {\n v3 = 0;\n v4 = 0;\n do {\n v6 = (int *)(a1 + 4LL * v3);\n v7 = *v6;\n if (*v6) {\n if (v7 == 1) {\n ++v3;\n } else {\n v5 = (int *)(a1 + 4LL * v2);\n *v6 = *v5;\n *v5 = v7;\n --v2;\n }\n } else {\n v8 = (int *)(a1 + 4LL * v4);\n v9 = *v8;\n *v8 = 0;\n *v6 = v9;\n ++v4;\n ++v3;\n }\n } while (v3 <= v2);\n }\n}" + }, + { + "index": 815, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "void func0(int arr[], int n) {\n int low = 0;\n int mid = 0;\n int high = n - 1;\n while (mid <= high) {\n if (arr[mid] == 0) {\n int temp = arr[low];\n arr[low] = arr[mid];\n arr[mid] = temp;\n low++;\n mid++;\n } else if (arr[mid] == 1) {\n mid++;\n } else {\n int temp = arr[mid];\n arr[mid] = arr[high];\n arr[high] = temp;\n high--;\n }\n }\n}", + "test": "int main() {\n\n int arr1[9] = {1,2,0,1,0,1,2,1,1};\n\n func0(arr1, 9);\n\n int expected_arr1[9] = {0, 0, 1, 1, 1, 1, 1, 2, 2};\n\n for (int i = 0; i < 9; i++)\n\n assert(arr1[i] == expected_arr1[i]);\n\n\n\n int arr2[10] = {1,0,0,1,2,1,2,2,1,0};\n\n func0(arr2, 10);\n\n int expected_arr2[10] = {0, 0, 0, 1, 1, 1, 1, 2, 2, 2};\n\n for (int i = 0; i < 10; i++)\n\n assert(arr2[i] == expected_arr2[i]);\n\n\n\n int arr3[10] = {2,2,1,0,0,0,1,1,2,1};\n\n func0(arr3, 10);\n\n int expected_arr3[10] = {0, 0, 0, 1, 1, 1, 1, 2, 2, 2};\n\n for (int i = 0; i < 10; i++)\n\n assert(arr3[i] == expected_arr3[i]);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x1,%esi\njs 1477 \nxor %eax,%eax\nxor %r8d,%r8d\njmp 144e \nmovslq %r8d,%rdx\nadd $0x1,%eax\nadd $0x1,%r8d\nlea (%rdi,%rdx,4),%rdx\nmov (%rdx),%r9d\nmovl $0x0,(%rdx)\nmov %r9d,(%rcx)\ncmp %eax,%esi\njl 1477 \nmovslq %eax,%rdx\nlea (%rdi,%rdx,4),%rcx\nmov (%rcx),%edx\ntest %edx,%edx\nje 1430 \ncmp $0x1,%edx\nje 1480 \nmovslq %esi,%r9\nsub $0x1,%esi\nlea (%rdi,%r9,4),%r9\nmov (%r9),%r10d\nmov %r10d,(%rcx)\nmov %edx,(%r9)\ncmp %eax,%esi\njge 144e \nretq\nnopl 0x0(%rax,%rax,1)\nadd $0x1,%eax\njmp 144a \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nsub esi, 1\njs short locret_13D7\nxor eax, eax\nxor r8d, r8d\njmp short loc_13AE\nloc_1390:\nmovsxd rdx, r8d\nadd eax, 1\nadd r8d, 1\nlea rdx, [rdi+rdx*4]\nmov r9d, [rdx]\nmov dword ptr [rdx], 0\nmov [rcx], r9d\nloc_13AA:\ncmp esi, eax\njl short locret_13D7\nloc_13AE:\nmovsxd rdx, eax\nlea rcx, [rdi+rdx*4]\nmov edx, [rcx]\ntest edx, edx\njz short loc_1390\ncmp edx, 1\njz short loc_13E0\nmovsxd r9, esi\nsub esi, 1\nlea r9, [rdi+r9*4]\nmov r10d, [r9]\nmov [rcx], r10d\nmov [r9], edx\ncmp esi, eax\njge short loc_13AE\nlocret_13D7:\nretn\nloc_13E0:\nadd eax, 1\njmp short loc_13AA", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2)\n{\n int v2; // esi\n int v3; // eax\n int v4; // r8d\n __int64 v5; // rdx\n int *v6; // rdx\n int v7; // r9d\n int *v8; // rcx\n int v9; // edx\n __int64 v10; // r9\n int *v11; // r9\n\n v2 = a2 - 1;\n if ( v2 >= 0 )\n {\n v3 = 0;\n v4 = 0;\n do\n {\n while ( 1 )\n {\n v8 = (int *)(a1 + 4LL * v3);\n v9 = *v8;\n if ( *v8 )\n break;\n v5 = v4;\n ++v3;\n ++v4;\n v6 = (int *)(a1 + 4 * v5);\n v7 = *v6;\n *v6 = 0;\n *v8 = v7;\nLABEL_4:\n if ( v2 < v3 )\n return;\n }\n if ( v9 == 1 )\n {\n ++v3;\n goto LABEL_4;\n }\n v10 = v2--;\n v11 = (int *)(a1 + 4 * v10);\n *v8 = *v11;\n *v11 = v9;\n }\n while ( v2 >= v3 );\n }\n}", + "ida_strip_asm": "sub_1380:\nendbr64\nsub esi, 1\njs short locret_13D7\nxor eax, eax\nxor r8d, r8d\njmp short loc_13AE\nloc_1390:\nmovsxd rdx, r8d\nadd eax, 1\nadd r8d, 1\nlea rdx, [rdi+rdx*4]\nmov r9d, [rdx]\nmov dword ptr [rdx], 0\nmov [rcx], r9d\nloc_13AA:\ncmp esi, eax\njl short locret_13D7\nloc_13AE:\nmovsxd rdx, eax\nlea rcx, [rdi+rdx*4]\nmov edx, [rcx]\ntest edx, edx\njz short loc_1390\ncmp edx, 1\njz short loc_13E0\nmovsxd r9, esi\nsub esi, 1\nlea r9, [rdi+r9*4]\nmov r10d, [r9]\nmov [rcx], r10d\nmov [r9], edx\ncmp esi, eax\njge short loc_13AE\nlocret_13D7:\nretn\nloc_13E0:\nadd eax, 1\njmp short loc_13AA", + "ida_strip_pseudo": "void __fastcall sub_1380(__int64 a1, int a2)\n{\n int v2; // esi\n int v3; // eax\n int v4; // r8d\n __int64 v5; // rdx\n int *v6; // rdx\n int v7; // r9d\n int *v8; // rcx\n int v9; // edx\n __int64 v10; // r9\n int *v11; // r9\n\n v2 = a2 - 1;\n if ( v2 >= 0 )\n {\n v3 = 0;\n v4 = 0;\n do\n {\n while ( 1 )\n {\n v8 = (int *)(a1 + 4LL * v3);\n v9 = *v8;\n if ( *v8 )\n break;\n v5 = v4;\n ++v3;\n ++v4;\n v6 = (int *)(a1 + 4 * v5);\n v7 = *v6;\n *v6 = 0;\n *v8 = v7;\nLABEL_4:\n if ( v2 < v3 )\n return;\n }\n if ( v9 == 1 )\n {\n ++v3;\n goto LABEL_4;\n }\n v10 = v2--;\n v11 = (int *)(a1 + 4 * v10);\n *v8 = *v11;\n *v11 = v9;\n }\n while ( v2 >= v3 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1380(long long a1, int a2) {\n int v2;\n int v3;\n int v4;\n long long v5;\n int *v6;\n int v7;\n int *v8;\n int v9;\n long long v10;\n int *v11;\n v2 = a2 - 1;\n if (v2 >= 0) {\n v3 = 0;\n v4 = 0;\n do {\n while (1) {\n v8 = (int *)(a1 + 4LL * v3);\n v9 = *v8;\n if (*v8) break;\n v5 = v4;\n ++v3;\n ++v4;\n v6 = (int *)(a1 + 4 * v5);\n v7 = *v6;\n *v6 = 0;\n *v8 = v7;\n LABEL_4:\n if (v2 < v3) return;\n }\n if (v9 == 1) {\n ++v3;\n goto LABEL_4;\n }\n v10 = v2--;\n v11 = (int *)(a1 + 4 * v10);\n *v8 = *v11;\n *v11 = v9;\n } while (v2 >= v3);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2) {\n int v2;\n int v3;\n int v4;\n long long v5;\n int *v6;\n int v7;\n int *v8;\n int v9;\n long long v10;\n int *v11;\n v2 = a2 - 1;\n if (v2 >= 0) {\n v3 = 0;\n v4 = 0;\n do {\n while (1) {\n v8 = (int *)(a1 + 4LL * v3);\n v9 = *v8;\n if (*v8) break;\n v5 = v4;\n ++v3;\n ++v4;\n v6 = (int *)(a1 + 4 * v5);\n v7 = *v6;\n *v6 = 0;\n *v8 = v7;\n LABEL_4:\n if (v2 < v3) return;\n }\n if (v9 == 1) {\n ++v3;\n goto LABEL_4;\n }\n v10 = v2--;\n v11 = (int *)(a1 + 4 * v10);\n *v8 = *v11;\n *v11 = v9;\n } while (v2 >= v3);\n }\n}" + }, + { + "index": 815, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "void func0(int arr[], int n) {\n int low = 0;\n int mid = 0;\n int high = n - 1;\n while (mid <= high) {\n if (arr[mid] == 0) {\n int temp = arr[low];\n arr[low] = arr[mid];\n arr[mid] = temp;\n low++;\n mid++;\n } else if (arr[mid] == 1) {\n mid++;\n } else {\n int temp = arr[mid];\n arr[mid] = arr[high];\n arr[high] = temp;\n high--;\n }\n }\n}", + "test": "int main() {\n\n int arr1[9] = {1,2,0,1,0,1,2,1,1};\n\n func0(arr1, 9);\n\n int expected_arr1[9] = {0, 0, 1, 1, 1, 1, 1, 2, 2};\n\n for (int i = 0; i < 9; i++)\n\n assert(arr1[i] == expected_arr1[i]);\n\n\n\n int arr2[10] = {1,0,0,1,2,1,2,2,1,0};\n\n func0(arr2, 10);\n\n int expected_arr2[10] = {0, 0, 0, 1, 1, 1, 1, 2, 2, 2};\n\n for (int i = 0; i < 10; i++)\n\n assert(arr2[i] == expected_arr2[i]);\n\n\n\n int arr3[10] = {2,2,1,0,0,0,1,1,2,1};\n\n func0(arr3, 10);\n\n int expected_arr3[10] = {0, 0, 0, 1, 1, 1, 1, 2, 2, 2};\n\n for (int i = 0; i < 10; i++)\n\n assert(arr3[i] == expected_arr3[i]);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x1,%esi\njs 1537 \nxor %eax,%eax\nxor %r8d,%r8d\njmp 150e \nmovslq %r8d,%rdx\nadd $0x1,%eax\nadd $0x1,%r8d\nlea (%rdi,%rdx,4),%rdx\nmov (%rdx),%r9d\nmovl $0x0,(%rdx)\nmov %r9d,(%rcx)\ncmp %eax,%esi\njl 1537 \nmovslq %eax,%rdx\nlea (%rdi,%rdx,4),%rcx\nmov (%rcx),%edx\ntest %edx,%edx\nje 14f0 \ncmp $0x1,%edx\nje 1540 \nmovslq %esi,%r9\nsub $0x1,%esi\nlea (%rdi,%r9,4),%r9\nmov (%r9),%r10d\nmov %r10d,(%rcx)\nmov %edx,(%r9)\ncmp %eax,%esi\njge 150e \nretq\nnopl 0x0(%rax,%rax,1)\nadd $0x1,%eax\njmp 150a \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nsub esi, 1\njs short locret_1407\nxor eax, eax\nxor r8d, r8d\njmp short loc_13DE\nloc_13C0:\nmovsxd rdx, r8d\nadd eax, 1\nadd r8d, 1\nlea rdx, [rdi+rdx*4]\nmov r9d, [rdx]\nmov dword ptr [rdx], 0\nmov [rcx], r9d\nloc_13DA:\ncmp esi, eax\njl short locret_1407\nloc_13DE:\nmovsxd rdx, eax\nlea rcx, [rdi+rdx*4]\nmov edx, [rcx]\ntest edx, edx\njz short loc_13C0\ncmp edx, 1\njz short loc_1410\nmovsxd r9, esi\nsub esi, 1\nlea r9, [rdi+r9*4]\nmov r10d, [r9]\nmov [rcx], r10d\nmov [r9], edx\ncmp esi, eax\njge short loc_13DE\nlocret_1407:\nretn\nloc_1410:\nadd eax, 1\njmp short loc_13DA", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2)\n{\n int v2; // esi\n int v3; // eax\n int v4; // r8d\n __int64 v5; // rdx\n int *v6; // rdx\n int v7; // r9d\n int *v8; // rcx\n int v9; // edx\n __int64 v10; // r9\n int *v11; // r9\n\n v2 = a2 - 1;\n if ( v2 >= 0 )\n {\n v3 = 0;\n v4 = 0;\n do\n {\n while ( 1 )\n {\n v8 = (int *)(a1 + 4LL * v3);\n v9 = *v8;\n if ( *v8 )\n break;\n v5 = v4;\n ++v3;\n ++v4;\n v6 = (int *)(a1 + 4 * v5);\n v7 = *v6;\n *v6 = 0;\n *v8 = v7;\nLABEL_4:\n if ( v2 < v3 )\n return;\n }\n if ( v9 == 1 )\n {\n ++v3;\n goto LABEL_4;\n }\n v10 = v2--;\n v11 = (int *)(a1 + 4 * v10);\n *v8 = *v11;\n *v11 = v9;\n }\n while ( v2 >= v3 );\n }\n}", + "ida_strip_asm": "sub_13B0:\nendbr64\nsub esi, 1\njs short locret_1407\nxor eax, eax\nxor r8d, r8d\njmp short loc_13DE\nloc_13C0:\nmovsxd rdx, r8d\nadd eax, 1\nadd r8d, 1\nlea rdx, [rdi+rdx*4]\nmov r9d, [rdx]\nmov dword ptr [rdx], 0\nmov [rcx], r9d\nloc_13DA:\ncmp esi, eax\njl short locret_1407\nloc_13DE:\nmovsxd rdx, eax\nlea rcx, [rdi+rdx*4]\nmov edx, [rcx]\ntest edx, edx\njz short loc_13C0\ncmp edx, 1\njz short loc_1410\nmovsxd r9, esi\nsub esi, 1\nlea r9, [rdi+r9*4]\nmov r10d, [r9]\nmov [rcx], r10d\nmov [r9], edx\ncmp esi, eax\njge short loc_13DE\nlocret_1407:\nretn\nloc_1410:\nadd eax, 1\njmp short loc_13DA", + "ida_strip_pseudo": "void __fastcall sub_13B0(__int64 a1, int a2)\n{\n int v2; // esi\n int v3; // eax\n int v4; // r8d\n __int64 v5; // rdx\n int *v6; // rdx\n int v7; // r9d\n int *v8; // rcx\n int v9; // edx\n __int64 v10; // r9\n int *v11; // r9\n\n v2 = a2 - 1;\n if ( v2 >= 0 )\n {\n v3 = 0;\n v4 = 0;\n do\n {\n while ( 1 )\n {\n v8 = (int *)(a1 + 4LL * v3);\n v9 = *v8;\n if ( *v8 )\n break;\n v5 = v4;\n ++v3;\n ++v4;\n v6 = (int *)(a1 + 4 * v5);\n v7 = *v6;\n *v6 = 0;\n *v8 = v7;\nLABEL_4:\n if ( v2 < v3 )\n return;\n }\n if ( v9 == 1 )\n {\n ++v3;\n goto LABEL_4;\n }\n v10 = v2--;\n v11 = (int *)(a1 + 4 * v10);\n *v8 = *v11;\n *v11 = v9;\n }\n while ( v2 >= v3 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_13B0(long long a1, int a2) {\n int v2;\n int v3;\n int v4;\n long long v5;\n int *v6;\n int v7;\n int *v8;\n int v9;\n long long v10;\n int *v11;\n v2 = a2 - 1;\n if (v2 >= 0) {\n v3 = 0;\n v4 = 0;\n do {\n while (1) {\n v8 = (int *)(a1 + 4LL * v3);\n v9 = *v8;\n if (*v8) break;\n v5 = v4;\n ++v3;\n ++v4;\n v6 = (int *)(a1 + 4 * v5);\n v7 = *v6;\n *v6 = 0;\n *v8 = v7;\n LABEL_4:\n if (v2 < v3) return;\n }\n if (v9 == 1) {\n ++v3;\n goto LABEL_4;\n }\n v10 = v2--;\n v11 = (int *)(a1 + 4 * v10);\n *v8 = *v11;\n *v11 = v9;\n } while (v2 >= v3);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2) {\n int v2;\n int v3;\n int v4;\n long long v5;\n int *v6;\n int v7;\n int *v8;\n int v9;\n long long v10;\n int *v11;\n v2 = a2 - 1;\n if (v2 >= 0) {\n v3 = 0;\n v4 = 0;\n do {\n while (1) {\n v8 = (int *)(a1 + 4LL * v3);\n v9 = *v8;\n if (*v8) break;\n v5 = v4;\n ++v3;\n ++v4;\n v6 = (int *)(a1 + 4 * v5);\n v7 = *v6;\n *v6 = 0;\n *v8 = v7;\n LABEL_4:\n if (v2 < v3) return;\n }\n if (v9 == 1) {\n ++v3;\n goto LABEL_4;\n }\n v10 = v2--;\n v11 = (int *)(a1 + 4 * v10);\n *v8 = *v11;\n *v11 = v9;\n } while (v2 >= v3);\n }\n}" + }, + { + "index": 816, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int *elements;\n\n size_t size;\n\n} tuple;\n\n\n\n", + "func": "tuple func0(tuple test_tup) {\n tuple new_tup;\n new_tup.elements = NULL;\n new_tup.size = 0;\n return new_tup;\n}", + "test": "int main() {\n\n tuple result;\n\n\n\n result = func0((tuple){ (int[]){1, 5, 3, 6, 8}, 5 });\n\n assert(result.size == 0);\n\n\n\n result = func0((tuple){ (int[]){2, 1, 4, 5, 6}, 5 });\n\n assert(result.size == 0);\n\n\n\n result = func0((tuple){ (int[]){3, 2, 5, 6, 8}, 5 });\n\n assert(result.size == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,%rax\nmov %rsi,%rcx\nmov %rcx,%rdx\nmov %rax,-0x20(%rbp)\nmov %rdx,-0x18(%rbp)\nmovq $0x0,-0x10(%rbp)\nmovq $0x0,-0x8(%rbp)\nmov -0x10(%rbp),%rax\nmov -0x8(%rbp),%rdx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov rax, rdi\nmov rcx, rsi\nmov rdx, rcx\nmov [rbp+var_20], rax\nmov [rbp+var_18], rdx\nmov [rbp+var_10], 0\nmov [rbp+var_8], 0\nmov rax, [rbp+var_10]\nmov rdx, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 func0()\n{\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov rax, rdi\nmov rcx, rsi\nmov rdx, rcx\nmov [rbp+var_20], rax\nmov [rbp+var_18], rdx\nmov [rbp+var_10], 0\nmov [rbp+var_8], 0\nmov rax, [rbp+var_10]\nmov rdx, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 sub_1169()\n{\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169() { return 0LL; }", + "ida_pseudo_norm": "long long func0() { return 0LL; }" + }, + { + "index": 817, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int nums[], int size, int m, int n, int* result_size) {\n int* result = (int*)malloc(size * sizeof(int));\n int count = 0;\n for (int i = 0; i < size; i++) {\n if (nums[i] % m == 0 || nums[i] % n == 0) {\n result[count++] = nums[i];\n }\n }\n *result_size = count;\n return result;\n}", + "test": "int main() {\n\n int nums1[] = {19, 65, 57, 39, 152, 639, 121, 44, 90, 190};\n\n int nums2[] = {1, 2, 3, 5, 7, 8, 10};\n\n int nums3[] = {10, 15, 14, 13, 18, 12, 20};\n\n int expected1[] = {19, 65, 57, 39, 152, 190};\n\n int expected2[] = {2, 5, 8, 10};\n\n int expected3[] = {10, 15, 20};\n\n int result_size1, result_size2, result_size3;\n\n\n\n int* result1 = func0(nums1, 10, 19, 13, &result_size1);\n\n int* result2 = func0(nums2, 7, 2, 5, &result_size2);\n\n int* result3 = func0(nums3, 7, 10, 5, &result_size3);\n\n\n\n assert(result_size1 == 6);\n\n for (int i = 0; i < result_size1; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n\n\n assert(result_size2 == 4);\n\n for (int i = 0; i < result_size2; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n\n\n assert(result_size3 == 3);\n\n for (int i = 0; i < result_size3; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmov %ecx,-0x24(%rbp)\nmov %r8,-0x30(%rbp)\nmov -0x1c(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 1262 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncltd\nidivl -0x20(%rbp)\nmov %edx,%eax\ntest %eax,%eax\nje 122b \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncltd\nidivl -0x24(%rbp)\nmov %edx,%eax\ntest %eax,%eax\njne 125e \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x10(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x10(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11eb \nmov -0x30(%rbp),%rax\nmov -0x10(%rbp),%edx\nmov %edx,(%rax)\nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_24], ecx\nmov [rbp+var_30], r8\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp short loc_1262\nloc_11EB:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncdq\nidiv [rbp+var_20]\nmov eax, edx\ntest eax, eax\njz short loc_122B\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncdq\nidiv [rbp+var_24]\nmov eax, edx\ntest eax, eax\njnz short loc_125E\nloc_122B:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_125E:\nadd [rbp+var_C], 1\nloc_1262:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_11EB\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_10]\nmov [rax], edx\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, int a3, int a4, _DWORD *a5)\n{\n int v5; // eax\n int v10; // [rsp+20h] [rbp-10h]\n int i; // [rsp+24h] [rbp-Ch]\n _DWORD *v12; // [rsp+28h] [rbp-8h]\n\n v12 = malloc(4LL * a2);\n v10 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( !(*(_DWORD *)(4LL * i + a1) % a3) || !(*(_DWORD *)(4LL * i + a1) % a4) )\n {\n v5 = v10++;\n v12[v5] = *(_DWORD *)(4LL * i + a1);\n }\n }\n *a5 = v10;\n return v12;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_24], ecx\nmov [rbp+var_30], r8\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp short loc_1262\nloc_11EB:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncdq\nidiv [rbp+var_20]\nmov eax, edx\ntest eax, eax\njz short loc_122B\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncdq\nidiv [rbp+var_24]\nmov eax, edx\ntest eax, eax\njnz short loc_125E\nloc_122B:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_125E:\nadd [rbp+var_C], 1\nloc_1262:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_11EB\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_10]\nmov [rax], edx\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(__int64 a1, int a2, int a3, int a4, _DWORD *a5)\n{\n int v5; // eax\n int v10; // [rsp+20h] [rbp-10h]\n int i; // [rsp+24h] [rbp-Ch]\n _DWORD *v12; // [rsp+28h] [rbp-8h]\n\n v12 = malloc(4LL * a2);\n v10 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( !(*(_DWORD *)(4LL * i + a1) % a3) || !(*(_DWORD *)(4LL * i + a1) % a4) )\n {\n v5 = v10++;\n v12[v5] = *(_DWORD *)(4LL * i + a1);\n }\n }\n *a5 = v10;\n return v12;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(long long a1, int a2, int a3, int a4, uint32_t *a5) {\n int v5;\n int v10;\n int i;\n uint32_t *v12;\n v12 = malloc(4LL * a2);\n v10 = 0;\n for (i = 0; i < a2; ++i) {\n if (!(*(uint32_t *)(4LL * i + a1) % a3) ||\n !(*(uint32_t *)(4LL * i + a1) % a4)) {\n v5 = v10++;\n v12[v5] = *(uint32_t *)(4LL * i + a1);\n }\n }\n *a5 = v10;\n return v12;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, int a3, int a4, uint32_t *a5) {\n int v5;\n int v10;\n int i;\n uint32_t *v12;\n v12 = malloc(4LL * a2);\n v10 = 0;\n for (i = 0; i < a2; ++i) {\n if (!(*(uint32_t *)(4LL * i + a1) % a3) ||\n !(*(uint32_t *)(4LL * i + a1) % a4)) {\n v5 = v10++;\n v12[v5] = *(uint32_t *)(4LL * i + a1);\n }\n }\n *a5 = v10;\n return v12;\n}" + }, + { + "index": 817, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int nums[], int size, int m, int n, int* result_size) {\n int* result = (int*)malloc(size * sizeof(int));\n int count = 0;\n for (int i = 0; i < size; i++) {\n if (nums[i] % m == 0 || nums[i] % n == 0) {\n result[count++] = nums[i];\n }\n }\n *result_size = count;\n return result;\n}", + "test": "int main() {\n\n int nums1[] = {19, 65, 57, 39, 152, 639, 121, 44, 90, 190};\n\n int nums2[] = {1, 2, 3, 5, 7, 8, 10};\n\n int nums3[] = {10, 15, 14, 13, 18, 12, 20};\n\n int expected1[] = {19, 65, 57, 39, 152, 190};\n\n int expected2[] = {2, 5, 8, 10};\n\n int expected3[] = {10, 15, 20};\n\n int result_size1, result_size2, result_size3;\n\n\n\n int* result1 = func0(nums1, 10, 19, 13, &result_size1);\n\n int* result2 = func0(nums2, 7, 2, 5, &result_size2);\n\n int* result3 = func0(nums3, 7, 10, 5, &result_size3);\n\n\n\n assert(result_size1 == 6);\n\n for (int i = 0; i < result_size1; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n\n\n assert(result_size2 == 4);\n\n for (int i = 0; i < result_size2; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n\n\n assert(result_size3 == 3);\n\n for (int i = 0; i < result_size3; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%r14\nmov %esi,%r13d\nmov %edx,%ebx\nmov %ecx,%ebp\nmov %r8,%r12\nmovslq %esi,%rdi\nshl $0x2,%rdi\ncallq 10b0 \nmov %rax,%r8\ntest %r13d,%r13d\njle 1212 \nmov %r14,%rsi\nlea -0x1(%r13),%eax\nlea 0x4(%r14,%rax,4),%r9\nmov $0x0,%edi\njmp 11fc \nmovslq %edi,%rax\nmov %ecx,(%r8,%rax,4)\nlea 0x1(%rdi),%edi\nadd $0x4,%rsi\ncmp %r9,%rsi\nje 1217 \nmov (%rsi),%ecx\nmov %ecx,%eax\ncltd\nidiv %ebx\ntest %edx,%edx\nje 11e9 \nmov %ecx,%eax\ncltd\nidiv %ebp\ntest %edx,%edx\njne 11f3 \njmp 11e9 \nmov $0x0,%edi\nmov %edi,(%r12)\nmov %r8,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r13, rdi\nmov r15d, esi\nmov ebx, edx\nmov ebp, ecx\nmov r12, r8\nmovsxd r14, esi\nshl r14, 2\nmov rdi, r14; size\ncall _malloc\nmov r9, rax\ntest r15d, r15d\njle short loc_1217\nmov rsi, r13\nlea r8, [r13+r14+0]\nmov edi, 0\njmp short loc_1201\nloc_11EE:\nmovsxd rax, edi\nmov [r9+rax*4], ecx\nlea edi, [rdi+1]\nloc_11F8:\nadd rsi, 4\ncmp rsi, r8\njz short loc_121C\nloc_1201:\nmov ecx, [rsi]\nmov eax, ecx\ncdq\nidiv ebx\ntest edx, edx\njz short loc_11EE\nmov eax, ecx\ncdq\nidiv ebp\ntest edx, edx\njnz short loc_11F8\njmp short loc_11EE\nloc_1217:\nmov edi, 0\nloc_121C:\nmov [r12], edi\nmov rax, r9\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2, int a3, int a4, _DWORD *a5)\n{\n size_t v8; // r14\n _DWORD *v9; // r9\n int *v10; // rsi\n int *v11; // r8\n int v12; // edi\n int v13; // ecx\n\n v8 = a2;\n v9 = malloc(v8 * 4);\n if ( a2 <= 0 )\n {\n v12 = 0;\n }\n else\n {\n v10 = a1;\n v11 = &a1[v8];\n v12 = 0;\n do\n {\n v13 = *v10;\n if ( !(*v10 % a3) || !(v13 % a4) )\n v9[v12++] = v13;\n ++v10;\n }\n while ( v10 != v11 );\n }\n *a5 = v12;\n return v9;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r13, rdi\nmov r15d, esi\nmov ebx, edx\nmov ebp, ecx\nmov r12, r8\nmovsxd r14, esi\nshl r14, 2\nmov rdi, r14; size\ncall _malloc\nmov r9, rax\ntest r15d, r15d\njle short loc_1217\nmov rsi, r13\nlea r8, [r13+r14+0]\nmov edi, 0\njmp short loc_1201\nloc_11EE:\nmovsxd rax, edi\nmov [r9+rax*4], ecx\nlea edi, [rdi+1]\nloc_11F8:\nadd rsi, 4\ncmp rsi, r8\njz short loc_121C\nloc_1201:\nmov ecx, [rsi]\nmov eax, ecx\ncdq\nidiv ebx\ntest edx, edx\njz short loc_11EE\nmov eax, ecx\ncdq\nidiv ebp\ntest edx, edx\njnz short loc_11F8\njmp short loc_11EE\nloc_1217:\nmov edi, 0\nloc_121C:\nmov [r12], edi\nmov rax, r9\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(int *a1, int a2, int a3, int a4, _DWORD *a5)\n{\n size_t v8; // r14\n _DWORD *v9; // r9\n int *v10; // rsi\n int *v11; // r8\n int v12; // edi\n int v13; // ecx\n\n v8 = a2;\n v9 = malloc(v8 * 4);\n if ( a2 <= 0 )\n {\n v12 = 0;\n }\n else\n {\n v10 = a1;\n v11 = &a1[v8];\n v12 = 0;\n do\n {\n v13 = *v10;\n if ( !(*v10 % a3) || !(v13 % a4) )\n v9[v12++] = v13;\n ++v10;\n }\n while ( v10 != v11 );\n }\n *a5 = v12;\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(int *a1, int a2, int a3, int a4, uint32_t *a5) {\n unsigned int v8;\n uint32_t *v9;\n int *v10;\n int *v11;\n int v12;\n int v13;\n v8 = a2;\n v9 = malloc(v8 * 4);\n if (a2 <= 0) {\n v12 = 0;\n } else {\n v10 = a1;\n v11 = &a1[v8];\n v12 = 0;\n do {\n v13 = *v10;\n if (!(*v10 % a3) || !(v13 % a4)) v9[v12++] = v13;\n ++v10;\n } while (v10 != v11);\n }\n *a5 = v12;\n return v9;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2, int a3, int a4, uint32_t *a5) {\n unsigned int v8;\n uint32_t *v9;\n int *v10;\n int *v11;\n int v12;\n int v13;\n v8 = a2;\n v9 = malloc(v8 * 4);\n if (a2 <= 0) {\n v12 = 0;\n } else {\n v10 = a1;\n v11 = &a1[v8];\n v12 = 0;\n do {\n v13 = *v10;\n if (!(*v10 % a3) || !(v13 % a4)) v9[v12++] = v13;\n ++v10;\n } while (v10 != v11);\n }\n *a5 = v12;\n return v9;\n}" + }, + { + "index": 817, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int nums[], int size, int m, int n, int* result_size) {\n int* result = (int*)malloc(size * sizeof(int));\n int count = 0;\n for (int i = 0; i < size; i++) {\n if (nums[i] % m == 0 || nums[i] % n == 0) {\n result[count++] = nums[i];\n }\n }\n *result_size = count;\n return result;\n}", + "test": "int main() {\n\n int nums1[] = {19, 65, 57, 39, 152, 639, 121, 44, 90, 190};\n\n int nums2[] = {1, 2, 3, 5, 7, 8, 10};\n\n int nums3[] = {10, 15, 14, 13, 18, 12, 20};\n\n int expected1[] = {19, 65, 57, 39, 152, 190};\n\n int expected2[] = {2, 5, 8, 10};\n\n int expected3[] = {10, 15, 20};\n\n int result_size1, result_size2, result_size3;\n\n\n\n int* result1 = func0(nums1, 10, 19, 13, &result_size1);\n\n int* result2 = func0(nums2, 7, 2, 5, &result_size2);\n\n int* result3 = func0(nums3, 7, 10, 5, &result_size3);\n\n\n\n assert(result_size1 == 6);\n\n for (int i = 0; i < result_size1; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n\n\n assert(result_size2 == 4);\n\n for (int i = 0; i < result_size2; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n\n\n assert(result_size3 == 3);\n\n for (int i = 0; i < result_size3; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\nmov %rdi,%r14\nmovslq %esi,%rdi\npush %r13\nmov %rdi,%r13\nshl $0x2,%rdi\npush %r12\nmov %r8,%r12\npush %rbp\nmov %ecx,%ebp\npush %rbx\nmov %edx,%ebx\ncallq 10b0 \nmov %rax,%r10\ntest %r13d,%r13d\njle 1530 \nlea -0x1(%r13),%eax\nmov %r14,%rdi\nxor %r9d,%r9d\nlea 0x4(%r14,%rax,4),%rcx\nnopl 0x0(%rax)\nmov (%rdi),%esi\nmov %esi,%eax\ncltd\nidiv %ebx\ntest %edx,%edx\nje 1504 \nmov %esi,%eax\ncltd\nidiv %ebp\ntest %edx,%edx\njne 150f \nmovslq %r9d,%rax\nadd $0x1,%r9d\nmov %esi,(%r10,%rax,4)\nadd $0x4,%rdi\ncmp %rcx,%rdi\njne 14f0 \npop %rbx\nmov %r10,%rax\npop %rbp\nmov %r9d,(%r12)\npop %r12\npop %r13\npop %r14\nretq\nnopl 0x0(%rax,%rax,1)\nxor %r9d,%r9d\npop %rbx\nmov %r10,%rax\npop %rbp\nmov %r9d,(%r12)\npop %r12\npop %r13\npop %r14\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmovsxd r9, esi\npush r14\nmov r15, r9\nmov r14, r8\npush r13\nmov r13d, ecx\npush r12\nlea r12, ds:0[r9*4]\npush rbp\nmov ebp, edx\npush rbx\nmov rbx, rdi\nmov rdi, r12; size\nsub rsp, 8\ncall _malloc\nmov r8, rax\ntest r15d, r15d\njle short loc_14C8\nmov rsi, rbx\nlea r9, [rbx+r12]\nxor edi, edi\nnop dword ptr [rax+00h]\nloc_1488:\nmov ecx, [rsi]\nmov eax, ecx\ncdq\nidiv ebp\ntest edx, edx\njz short loc_149D\nmov eax, ecx\ncdq\nidiv r13d\ntest edx, edx\njnz short loc_14A7\nloc_149D:\nmovsxd rax, edi\nadd edi, 1\nmov [r8+rax*4], ecx\nloc_14A7:\nadd rsi, 4\ncmp r9, rsi\njnz short loc_1488\nloc_14B0:\nmov [r14], edi\nadd rsp, 8\nmov rax, r8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14C8:\nxor edi, edi\njmp short loc_14B0", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2, int a3, int a4, _DWORD *a5)\n{\n size_t v7; // r12\n _DWORD *v10; // r8\n int *v11; // rsi\n int v12; // edi\n int v13; // ecx\n __int64 v14; // rax\n\n v7 = a2;\n v10 = malloc(v7 * 4);\n if ( a2 <= 0 )\n {\n v12 = 0;\n }\n else\n {\n v11 = a1;\n v12 = 0;\n do\n {\n v13 = *v11;\n if ( !(*v11 % a3) || !(v13 % a4) )\n {\n v14 = v12++;\n v10[v14] = v13;\n }\n ++v11;\n }\n while ( &a1[v7] != v11 );\n }\n *a5 = v12;\n return v10;\n}", + "ida_strip_asm": "sub_1440:\nendbr64\npush r15\nmovsxd r9, esi\npush r14\nmov r15, r9\nmov r14, r8\npush r13\nmov r13d, ecx\npush r12\nlea r12, ds:0[r9*4]\npush rbp\nmov ebp, edx\npush rbx\nmov rbx, rdi\nmov rdi, r12; size\nsub rsp, 8\ncall _malloc\nmov r8, rax\ntest r15d, r15d\njle short loc_14C8\nmov rsi, rbx\nlea r9, [rbx+r12]\nxor edi, edi\nnop dword ptr [rax+00h]\nloc_1488:\nmov ecx, [rsi]\nmov eax, ecx\ncdq\nidiv ebp\ntest edx, edx\njz short loc_149D\nmov eax, ecx\ncdq\nidiv r13d\ntest edx, edx\njnz short loc_14A7\nloc_149D:\nmovsxd rax, edi\nadd edi, 1\nmov [r8+rax*4], ecx\nloc_14A7:\nadd rsi, 4\ncmp r9, rsi\njnz short loc_1488\nloc_14B0:\nmov [r14], edi\nadd rsp, 8\nmov rax, r8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14C8:\nxor edi, edi\njmp short loc_14B0", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1440(int *a1, int a2, int a3, int a4, _DWORD *a5)\n{\n size_t v7; // r12\n _DWORD *v10; // r8\n int *v11; // rsi\n int v12; // edi\n int v13; // ecx\n __int64 v14; // rax\n\n v7 = a2;\n v10 = malloc(v7 * 4);\n if ( a2 <= 0 )\n {\n v12 = 0;\n }\n else\n {\n v11 = a1;\n v12 = 0;\n do\n {\n v13 = *v11;\n if ( !(*v11 % a3) || !(v13 % a4) )\n {\n v14 = v12++;\n v10[v14] = v13;\n }\n ++v11;\n }\n while ( &a1[v7] != v11 );\n }\n *a5 = v12;\n return v10;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1440(int *a1, int a2, int a3, int a4, uint32_t *a5) {\n unsigned int v7;\n uint32_t *v10;\n int *v11;\n int v12;\n int v13;\n long long v14;\n v7 = a2;\n v10 = malloc(v7 * 4);\n if (a2 <= 0) {\n v12 = 0;\n } else {\n v11 = a1;\n v12 = 0;\n do {\n v13 = *v11;\n if (!(*v11 % a3) || !(v13 % a4)) {\n v14 = v12++;\n v10[v14] = v13;\n }\n ++v11;\n } while (&a1[v7] != v11);\n }\n *a5 = v12;\n return v10;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2, int a3, int a4, uint32_t *a5) {\n unsigned int v7;\n uint32_t *v10;\n int *v11;\n int v12;\n int v13;\n long long v14;\n v7 = a2;\n v10 = malloc(v7 * 4);\n if (a2 <= 0) {\n v12 = 0;\n } else {\n v11 = a1;\n v12 = 0;\n do {\n v13 = *v11;\n if (!(*v11 % a3) || !(v13 % a4)) {\n v14 = v12++;\n v10[v14] = v13;\n }\n ++v11;\n } while (&a1[v7] != v11);\n }\n *a5 = v12;\n return v10;\n}" + }, + { + "index": 817, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int nums[], int size, int m, int n, int* result_size) {\n int* result = (int*)malloc(size * sizeof(int));\n int count = 0;\n for (int i = 0; i < size; i++) {\n if (nums[i] % m == 0 || nums[i] % n == 0) {\n result[count++] = nums[i];\n }\n }\n *result_size = count;\n return result;\n}", + "test": "int main() {\n\n int nums1[] = {19, 65, 57, 39, 152, 639, 121, 44, 90, 190};\n\n int nums2[] = {1, 2, 3, 5, 7, 8, 10};\n\n int nums3[] = {10, 15, 14, 13, 18, 12, 20};\n\n int expected1[] = {19, 65, 57, 39, 152, 190};\n\n int expected2[] = {2, 5, 8, 10};\n\n int expected3[] = {10, 15, 20};\n\n int result_size1, result_size2, result_size3;\n\n\n\n int* result1 = func0(nums1, 10, 19, 13, &result_size1);\n\n int* result2 = func0(nums2, 7, 2, 5, &result_size2);\n\n int* result3 = func0(nums3, 7, 10, 5, &result_size3);\n\n\n\n assert(result_size1 == 6);\n\n for (int i = 0; i < result_size1; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n\n\n assert(result_size2 == 4);\n\n for (int i = 0; i < result_size2; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n\n\n assert(result_size3 == 3);\n\n for (int i = 0; i < result_size3; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\nmov %rdi,%r14\nmovslq %esi,%rdi\npush %r13\nmov %rdi,%r13\nshl $0x2,%rdi\npush %r12\nmov %r8,%r12\npush %rbp\nmov %ecx,%ebp\npush %rbx\nmov %edx,%ebx\ncallq 10b0 \nmov %rax,%r10\ntest %r13d,%r13d\njle 14f0 \nlea -0x1(%r13),%eax\nmov %r14,%rdi\nxor %r9d,%r9d\nlea 0x4(%r14,%rax,4),%rcx\nnopl 0x0(%rax)\nmov (%rdi),%esi\nmov %esi,%eax\ncltd\nidiv %ebx\ntest %edx,%edx\nje 14c4 \nmov %esi,%eax\ncltd\nidiv %ebp\ntest %edx,%edx\njne 14cf \nmovslq %r9d,%rax\nadd $0x1,%r9d\nmov %esi,(%r10,%rax,4)\nadd $0x4,%rdi\ncmp %rcx,%rdi\njne 14b0 \npop %rbx\nmov %r10,%rax\npop %rbp\nmov %r9d,(%r12)\npop %r12\npop %r13\npop %r14\nretq\nnopl 0x0(%rax,%rax,1)\nxor %r9d,%r9d\npop %rbx\nmov %r10,%rax\npop %rbp\nmov %r9d,(%r12)\npop %r12\npop %r13\npop %r14\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmovsxd r9, esi\npush r14\nmov r15, r9\nmov r14, r8\npush r13\nmov r13d, ecx\npush r12\nlea r12, ds:0[r9*4]\npush rbp\nmov ebp, edx\npush rbx\nmov rbx, rdi\nmov rdi, r12; size\nsub rsp, 8\ncall _malloc\nmov r8, rax\ntest r15d, r15d\njle short loc_14B8\nmov rsi, rbx\nlea r9, [rbx+r12]\nxor edi, edi\nnop dword ptr [rax+00h]\nloc_1478:\nmov ecx, [rsi]\nmov eax, ecx\ncdq\nidiv ebp\ntest edx, edx\njz short loc_148D\nmov eax, ecx\ncdq\nidiv r13d\ntest edx, edx\njnz short loc_1497\nloc_148D:\nmovsxd rax, edi\nadd edi, 1\nmov [r8+rax*4], ecx\nloc_1497:\nadd rsi, 4\ncmp r9, rsi\njnz short loc_1478\nloc_14A0:\nmov [r14], edi\nadd rsp, 8\nmov rax, r8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14B8:\nxor edi, edi\njmp short loc_14A0", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2, int a3, int a4, _DWORD *a5)\n{\n size_t v7; // r12\n _DWORD *v10; // r8\n int *v11; // rsi\n int v12; // edi\n int v13; // ecx\n __int64 v14; // rax\n\n v7 = a2;\n v10 = malloc(v7 * 4);\n if ( a2 <= 0 )\n {\n v12 = 0;\n }\n else\n {\n v11 = a1;\n v12 = 0;\n do\n {\n v13 = *v11;\n if ( !(*v11 % a3) || !(v13 % a4) )\n {\n v14 = v12++;\n v10[v14] = v13;\n }\n ++v11;\n }\n while ( &a1[v7] != v11 );\n }\n *a5 = v12;\n return v10;\n}", + "ida_strip_asm": "sub_1430:\nendbr64\npush r15\nmovsxd r9, esi\npush r14\nmov r15, r9\nmov r14, r8\npush r13\nmov r13d, ecx\npush r12\nlea r12, ds:0[r9*4]\npush rbp\nmov ebp, edx\npush rbx\nmov rbx, rdi\nmov rdi, r12; size\nsub rsp, 8\ncall _malloc\nmov r8, rax\ntest r15d, r15d\njle short loc_14B8\nmov rsi, rbx\nlea r9, [rbx+r12]\nxor edi, edi\nnop dword ptr [rax+00h]\nloc_1478:\nmov ecx, [rsi]\nmov eax, ecx\ncdq\nidiv ebp\ntest edx, edx\njz short loc_148D\nmov eax, ecx\ncdq\nidiv r13d\ntest edx, edx\njnz short loc_1497\nloc_148D:\nmovsxd rax, edi\nadd edi, 1\nmov [r8+rax*4], ecx\nloc_1497:\nadd rsi, 4\ncmp r9, rsi\njnz short loc_1478\nloc_14A0:\nmov [r14], edi\nadd rsp, 8\nmov rax, r8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14B8:\nxor edi, edi\njmp short loc_14A0", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1430(int *a1, int a2, int a3, int a4, _DWORD *a5)\n{\n size_t v7; // r12\n _DWORD *v10; // r8\n int *v11; // rsi\n int v12; // edi\n int v13; // ecx\n __int64 v14; // rax\n\n v7 = a2;\n v10 = malloc(v7 * 4);\n if ( a2 <= 0 )\n {\n v12 = 0;\n }\n else\n {\n v11 = a1;\n v12 = 0;\n do\n {\n v13 = *v11;\n if ( !(*v11 % a3) || !(v13 % a4) )\n {\n v14 = v12++;\n v10[v14] = v13;\n }\n ++v11;\n }\n while ( &a1[v7] != v11 );\n }\n *a5 = v12;\n return v10;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1430(int *a1, int a2, int a3, int a4, uint32_t *a5) {\n unsigned int v7;\n uint32_t *v10;\n int *v11;\n int v12;\n int v13;\n long long v14;\n v7 = a2;\n v10 = malloc(v7 * 4);\n if (a2 <= 0) {\n v12 = 0;\n } else {\n v11 = a1;\n v12 = 0;\n do {\n v13 = *v11;\n if (!(*v11 % a3) || !(v13 % a4)) {\n v14 = v12++;\n v10[v14] = v13;\n }\n ++v11;\n } while (&a1[v7] != v11);\n }\n *a5 = v12;\n return v10;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2, int a3, int a4, uint32_t *a5) {\n unsigned int v7;\n uint32_t *v10;\n int *v11;\n int v12;\n int v13;\n long long v14;\n v7 = a2;\n v10 = malloc(v7 * 4);\n if (a2 <= 0) {\n v12 = 0;\n } else {\n v11 = a1;\n v12 = 0;\n do {\n v13 = *v11;\n if (!(*v11 % a3) || !(v13 % a4)) {\n v14 = v12++;\n v10[v14] = v13;\n }\n ++v11;\n } while (&a1[v7] != v11);\n }\n *a5 = v12;\n return v10;\n}" + }, + { + "index": 818, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *str) {\n int lower_ctr = 0;\n for (int i = 0; i < strlen(str); i++) {\n if (str[i] >= 'a' && str[i] <= 'z') {\n lower_ctr++;\n }\n }\n return lower_ctr;\n}", + "test": "int main() {\n\n assert(func0(\"abc\") == 3);\n\n assert(func0(\"string\") == 6);\n\n assert(func0(\"Python\") == 5);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x28,%rsp\nmov %rdi,-0x28(%rbp)\nmovl $0x0,-0x18(%rbp)\nmovl $0x0,-0x14(%rbp)\njmp 11ba \nmov -0x14(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x60,%al\njle 11b6 \nmov -0x14(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x7a,%al\njg 11b6 \naddl $0x1,-0x18(%rbp)\naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\nmovslq %eax,%rbx\nmov -0x28(%rbp),%rax\nmov %rax,%rdi\ncallq 1060 \ncmp %rax,%rbx\njb 118a \nmov -0x18(%rbp),%eax\nadd $0x28,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+s], rdi\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp short loc_11BA\nloc_118A:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 60h ; '`'\njle short loc_11B6\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 7Ah ; 'z'\njg short loc_11B6\nadd [rbp+var_18], 1\nloc_11B6:\nadd [rbp+var_14], 1\nloc_11BA:\nmov eax, [rbp+var_14]\nmovsxd rbx, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rbx, rax\njb short loc_118A\nmov eax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n unsigned int v2; // [rsp+18h] [rbp-18h]\n int i; // [rsp+1Ch] [rbp-14h]\n\n v2 = 0;\n for ( i = 0; i < strlen(a1); ++i )\n {\n if ( a1[i] > 96 && a1[i] <= 122 )\n ++v2;\n }\n return v2;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+s], rdi\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\njmp short loc_11BA\nloc_118A:\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 60h ; '`'\njle short loc_11B6\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 7Ah ; 'z'\njg short loc_11B6\nadd [rbp+var_18], 1\nloc_11B6:\nadd [rbp+var_14], 1\nloc_11BA:\nmov eax, [rbp+var_14]\nmovsxd rbx, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rbx, rax\njb short loc_118A\nmov eax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1)\n{\n unsigned int v2; // [rsp+18h] [rbp-18h]\n int i; // [rsp+1Ch] [rbp-14h]\n\n v2 = 0;\n for ( i = 0; i < strlen(a1); ++i )\n {\n if ( a1[i] > 96 && a1[i] <= 122 )\n ++v2;\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1) {\n unsigned int v2;\n int i;\n v2 = 0;\n for (i = 0; i < strlen(a1); ++i) {\n if (a1[i] > 96 && a1[i] <= 122) ++v2;\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n unsigned int v2;\n int i;\n v2 = 0;\n for (i = 0; i < strlen(a1); ++i) {\n if (a1[i] > 96 && a1[i] <= 122) ++v2;\n }\n return v2;\n}" + }, + { + "index": 818, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *str) {\n int lower_ctr = 0;\n for (int i = 0; i < strlen(str); i++) {\n if (str[i] >= 'a' && str[i] <= 'z') {\n lower_ctr++;\n }\n }\n return lower_ctr;\n}", + "test": "int main() {\n\n assert(func0(\"abc\") == 3);\n\n assert(func0(\"string\") == 6);\n\n assert(func0(\"Python\") == 5);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%rsi\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nmov %rsi,%rdx\nlea -0x1(%rsi,%rcx,1),%rsi\nmov $0x0,%ecx\ncmp %rsi,%rdx\nje 1184 \nmovzbl (%rdx),%eax\nsub $0x61,%eax\ncmp $0x1a,%al\nadc $0x0,%ecx\nadd $0x1,%rdx\njmp 116e \nmov %ecx,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmov rdi, rax\nmov rax, rbx\nadd rdi, rbx\nmov ecx, 0\njmp short loc_1196\nloc_1186:\nmovzx esi, byte ptr [rax]\nlea edx, [rsi-61h]\ncmp dl, 1Ah\nadc ecx, 0\nadd rax, 1\nloc_1196:\ncmp rax, rdi\njnz short loc_1186\nmov eax, ecx\npop rbx\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n size_t v2; // rdi\n const char *v3; // rax\n const char *v4; // rdi\n unsigned int v5; // ecx\n\n v2 = strlen(a1);\n v3 = a1;\n v4 = &a1[v2];\n v5 = 0;\n while ( v3 != v4 )\n v5 += (unsigned __int8)(*v3++ - 97) < 0x1Au;\n return v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmov rdi, rax\nmov rax, rbx\nadd rdi, rbx\nmov ecx, 0\njmp short loc_1196\nloc_1186:\nmovzx esi, byte ptr [rax]\nlea edx, [rsi-61h]\ncmp dl, 1Ah\nadc ecx, 0\nadd rax, 1\nloc_1196:\ncmp rax, rdi\njnz short loc_1186\nmov eax, ecx\npop rbx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1)\n{\n size_t v2; // rdi\n const char *v3; // rax\n const char *v4; // rdi\n unsigned int v5; // ecx\n\n v2 = strlen(a1);\n v3 = a1;\n v4 = &a1[v2];\n v5 = 0;\n while ( v3 != v4 )\n v5 += (unsigned __int8)(*v3++ - 97) < 0x1Au;\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1) {\n unsigned int v2;\n const char *v3;\n const char *v4;\n unsigned int v5;\n v2 = strlen(a1);\n v3 = a1;\n v4 = &a1[v2];\n v5 = 0;\n while (v3 != v4) v5 += (unsigned char)(*v3++ - 97) < 26u;\n return v5;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n unsigned int v2;\n const char *v3;\n const char *v4;\n unsigned int v5;\n v2 = strlen(a1);\n v3 = a1;\n v4 = &a1[v2];\n v5 = 0;\n while (v3 != v4) v5 += (unsigned char)(*v3++ - 97) < 26u;\n return v5;\n}" + }, + { + "index": 818, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *str) {\n int lower_ctr = 0;\n for (int i = 0; i < strlen(str); i++) {\n if (str[i] >= 'a' && str[i] <= 'z') {\n lower_ctr++;\n }\n }\n return lower_ctr;\n}", + "test": "int main() {\n\n assert(func0(\"abc\") == 3);\n\n assert(func0(\"string\") == 6);\n\n assert(func0(\"Python\") == 5);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\ncallq 1060 \nmov %rbx,%rdi\nlea (%rbx,%rax,1),%rcx\nxor %eax,%eax\njmp 1240 \nnopl 0x0(%rax,%rax,1)\nmovzbl (%rdi),%esi\nlea -0x61(%rsi),%edx\ncmp $0x1a,%dl\nadc $0x0,%eax\nadd $0x1,%rdi\ncmp %rcx,%rdi\njne 1230 \npop %rbx\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest rax, rax\njz short loc_1250\nlea rcx, [rbx+rax]\nmov rdi, rbx\nxor eax, eax\nnop dword ptr [rax+rax+00h]\nloc_1230:\nmovzx esi, byte ptr [rdi]\nlea edx, [rsi-61h]\ncmp dl, 1Ah\nadc eax, 0\nadd rdi, 1\ncmp rcx, rdi\njnz short loc_1230\npop rbx\nretn\nloc_1250:\nxor eax, eax\npop rbx\nretn", + "ida_pseudo": "size_t __fastcall func0(const char *a1)\n{\n size_t result; // rax\n const char *v2; // rcx\n\n result = strlen(a1);\n if ( !result )\n return 0LL;\n v2 = &a1[result];\n LODWORD(result) = 0;\n do\n result = ((unsigned __int8)(*a1++ - 97) < 0x1Au) + (unsigned int)result;\n while ( v2 != a1 );\n return result;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest rax, rax\njz short loc_1250\nlea rcx, [rbx+rax]\nmov rdi, rbx\nxor eax, eax\nnop dword ptr [rax+rax+00h]\nloc_1230:\nmovzx esi, byte ptr [rdi]\nlea edx, [rsi-61h]\ncmp dl, 1Ah\nadc eax, 0\nadd rdi, 1\ncmp rcx, rdi\njnz short loc_1230\npop rbx\nretn\nloc_1250:\nxor eax, eax\npop rbx\nretn", + "ida_strip_pseudo": "size_t __fastcall sub_1210(const char *a1)\n{\n size_t result; // rax\n const char *v2; // rcx\n\n result = strlen(a1);\n if ( !result )\n return 0LL;\n v2 = &a1[result];\n LODWORD(result) = 0;\n do\n result = ((unsigned __int8)(*a1++ - 97) < 0x1Au) + (unsigned int)result;\n while ( v2 != a1 );\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned int sub_1210(const char *a1) {\n unsigned int result;\n const char *v2;\n result = strlen(a1);\n if (!result) return 0LL;\n v2 = &a1[result];\n LODWORD(result) = 0;\n do\n result = ((unsigned char)(*a1++ - 97) < 26u) + (unsigned int)result;\n while (v2 != a1);\n return result;\n}", + "ida_pseudo_norm": "unsigned int func0(const char *a1) {\n unsigned int result;\n const char *v2;\n result = strlen(a1);\n if (!result) return 0LL;\n v2 = &a1[result];\n LODWORD(result) = 0;\n do\n result = ((unsigned char)(*a1++ - 97) < 26u) + (unsigned int)result;\n while (v2 != a1);\n return result;\n}" + }, + { + "index": 818, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *str) {\n int lower_ctr = 0;\n for (int i = 0; i < strlen(str); i++) {\n if (str[i] >= 'a' && str[i] <= 'z') {\n lower_ctr++;\n }\n }\n return lower_ctr;\n}", + "test": "int main() {\n\n assert(func0(\"abc\") == 3);\n\n assert(func0(\"string\") == 6);\n\n assert(func0(\"Python\") == 5);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\ncallq 1060 \ntest %rax,%rax\nje 14b0 \nmov %rax,%rcx\nlea -0x1(%rax),%rax\ncmp $0xe,%rax\njbe 14b4 \nmov %rcx,%rax\nmov %rbx,%rdx\npxor %xmm1,%xmm1\nmovdqa 0xe57(%rip),%xmm7\nand $0xfffffffffffffff0,%rax\nmovdqa 0xe5b(%rip),%xmm6\npxor %xmm4,%xmm4\npxor %xmm3,%xmm3\nmovdqa 0xe5b(%rip),%xmm5\nadd %rbx,%rax\nnopl 0x0(%rax,%rax,1)\nmovdqu (%rdx),%xmm0\nmovdqa %xmm4,%xmm8\nadd $0x10,%rdx\npaddb %xmm7,%xmm0\npsubusb %xmm6,%xmm0\npcmpeqb %xmm4,%xmm0\npand %xmm5,%xmm0\npcmpgtb %xmm0,%xmm8\nmovdqa %xmm0,%xmm2\npunpcklbw %xmm8,%xmm2\npunpckhbw %xmm8,%xmm0\nmovdqa %xmm3,%xmm8\npcmpgtw %xmm2,%xmm8\nmovdqa %xmm2,%xmm9\npunpcklwd %xmm8,%xmm9\npunpckhwd %xmm8,%xmm2\nmovdqa %xmm0,%xmm8\npaddd %xmm9,%xmm1\npaddd %xmm2,%xmm1\nmovdqa %xmm3,%xmm2\npcmpgtw %xmm0,%xmm2\npunpcklwd %xmm2,%xmm8\npunpckhwd %xmm2,%xmm0\npaddd %xmm8,%xmm1\npaddd %xmm0,%xmm1\ncmp %rax,%rdx\njne 1270 \nmovdqa %xmm1,%xmm0\nmov %rcx,%rsi\npsrldq $0x8,%xmm0\nand $0xfffffffffffffff0,%rsi\npaddd %xmm1,%xmm0\nmov %esi,%edx\nmovdqa %xmm0,%xmm1\npsrldq $0x4,%xmm1\npaddd %xmm1,%xmm0\nmovd %xmm0,%eax\ncmp %rsi,%rcx\nje 14a5 \nmovzbl (%rbx,%rsi,1),%esi\nsub $0x61,%esi\ncmp $0x1a,%sil\nlea 0x1(%rdx),%esi\nmovslq %esi,%rsi\nadc $0x0,%eax\ncmp %rsi,%rcx\njbe 14a5 \nmovzbl (%rbx,%rsi,1),%esi\nsub $0x61,%esi\ncmp $0x1a,%sil\nlea 0x2(%rdx),%esi\nmovslq %esi,%rsi\nadc $0x0,%eax\ncmp %rsi,%rcx\njbe 14a5 \nmovzbl (%rbx,%rsi,1),%esi\nsub $0x61,%esi\ncmp $0x1a,%sil\nlea 0x3(%rdx),%esi\nmovslq %esi,%rsi\nadc $0x0,%eax\ncmp %rsi,%rcx\njbe 14a5 \nmovzbl (%rbx,%rsi,1),%esi\nsub $0x61,%esi\ncmp $0x1a,%sil\nlea 0x4(%rdx),%esi\nmovslq %esi,%rsi\nadc $0x0,%eax\ncmp %rsi,%rcx\njbe 14a5 \nmovzbl (%rbx,%rsi,1),%esi\nsub $0x61,%esi\ncmp $0x1a,%sil\nlea 0x5(%rdx),%esi\nmovslq %esi,%rsi\nadc $0x0,%eax\ncmp %rsi,%rcx\njbe 14a5 \nmovzbl (%rbx,%rsi,1),%esi\nsub $0x61,%esi\ncmp $0x1a,%sil\nlea 0x6(%rdx),%esi\nmovslq %esi,%rsi\nadc $0x0,%eax\ncmp %rsi,%rcx\njbe 14a5 \nmovzbl (%rbx,%rsi,1),%esi\nsub $0x61,%esi\ncmp $0x1a,%sil\nlea 0x7(%rdx),%esi\nmovslq %esi,%rsi\nadc $0x0,%eax\ncmp %rsi,%rcx\njbe 14a5 \nmovzbl (%rbx,%rsi,1),%esi\nsub $0x61,%esi\ncmp $0x1a,%sil\nlea 0x8(%rdx),%esi\nmovslq %esi,%rsi\nadc $0x0,%eax\ncmp %rsi,%rcx\njbe 14a5 \nmovzbl (%rbx,%rsi,1),%esi\nsub $0x61,%esi\ncmp $0x1a,%sil\nlea 0x9(%rdx),%esi\nmovslq %esi,%rsi\nadc $0x0,%eax\ncmp %rsi,%rcx\njbe 14a5 \nmovzbl (%rbx,%rsi,1),%esi\nsub $0x61,%esi\ncmp $0x1a,%sil\nlea 0xa(%rdx),%esi\nmovslq %esi,%rsi\nadc $0x0,%eax\ncmp %rsi,%rcx\njbe 14a5 \nmovzbl (%rbx,%rsi,1),%esi\nsub $0x61,%esi\ncmp $0x1a,%sil\nlea 0xb(%rdx),%esi\nmovslq %esi,%rsi\nadc $0x0,%eax\ncmp %rsi,%rcx\njbe 14a5 \nmovzbl (%rbx,%rsi,1),%esi\nsub $0x61,%esi\ncmp $0x1a,%sil\nlea 0xc(%rdx),%esi\nmovslq %esi,%rsi\nadc $0x0,%eax\ncmp %rsi,%rcx\njbe 14a5 \nmovzbl (%rbx,%rsi,1),%esi\nsub $0x61,%esi\ncmp $0x1a,%sil\nlea 0xd(%rdx),%esi\nmovslq %esi,%rsi\nadc $0x0,%eax\ncmp %rsi,%rcx\njbe 14a5 \nmovzbl (%rbx,%rsi,1),%esi\nsub $0x61,%esi\ncmp $0x1a,%sil\nadc $0x0,%eax\nadd $0xe,%edx\nmovslq %edx,%rdx\ncmp %rdx,%rcx\njbe 14a5 \nmovzbl (%rbx,%rdx,1),%edx\nsub $0x61,%edx\ncmp $0x1a,%dl\nadc $0x0,%eax\npop %rbx\nretq\nnopw 0x0(%rax,%rax,1)\nxor %eax,%eax\npop %rbx\nretq\nxor %edx,%edx\nxor %eax,%eax\nxor %esi,%esi\njmpq 1316 \n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest rax, rax\njz loc_1470\nmov rdx, rax\nlea rax, [rax-1]\ncmp rax, 0Eh\njbe loc_1474\nmov rcx, rdx\npxor xmm1, xmm1\npxor xmm3, xmm3\nmov rax, rbx\nand rcx, 0FFFFFFFFFFFFFFF0h\nmovdqa xmm6, cs:xmmword_2080\nmovdqa xmm5, cs:xmmword_2090\npxor xmm4, xmm4\nlea rsi, [rcx+rbx]\nnop dword ptr [rax+00000000h]\nloc_1268:\nmovdqu xmm2, xmmword ptr [rax]\nmovdqa xmm0, xmm5\nmovdqa xmm7, xmm3\nadd rax, 10h\npaddb xmm2, xmm6\npsubusb xmm0, xmm2\npcmpeqb xmm0, xmm3\npcmpeqb xmm0, xmm3\npcmpgtb xmm7, xmm0\nmovdqa xmm2, xmm0\npunpcklbw xmm2, xmm7\npunpckhbw xmm0, xmm7\nmovdqa xmm7, xmm4\npcmpgtw xmm7, xmm2\nmovdqa xmm8, xmm2\npunpcklwd xmm8, xmm7\npunpckhwd xmm2, xmm7\nmovdqa xmm7, xmm0\npsubd xmm1, xmm8\npsubd xmm1, xmm2\nmovdqa xmm2, xmm4\npcmpgtw xmm2, xmm0\npunpcklwd xmm7, xmm2\npunpckhwd xmm0, xmm2\npsubd xmm1, xmm7\npsubd xmm1, xmm0\ncmp rsi, rax\njnz short loc_1268\nmovdqa xmm0, xmm1\nmov esi, ecx\npsrldq xmm0, 8\npaddd xmm0, xmm1\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\npaddd xmm0, xmm2\nmovd eax, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm1, 8\npaddd xmm1, xmm0\ncmp rdx, rcx\njz loc_1466\nloc_130E:\nmov rdi, rdx\nsub rdi, rcx\nlea r8, [rdi-1]\ncmp r8, 6\njbe loc_13C5\nmovq xmm2, qword ptr cs:xmmword_2080\nmovq xmm0, qword ptr [rbx+rcx]\npaddb xmm0, xmm2\nmovq xmm2, cs:qword_20A0\npminub xmm2, xmm0\npcmpeqb xmm0, xmm2\npxor xmm2, xmm2\npcmpgtb xmm2, xmm0\nmovdqa xmm3, xmm0\npunpcklbw xmm3, xmm2\npunpcklbw xmm0, xmm2\npxor xmm2, xmm2\nmovdqa xmm4, xmm2\nmovdqa xmm5, xmm3\npshufd xmm0, xmm0, 4Eh ; 'N'\npcmpgtw xmm4, xmm3\npcmpgtw xmm2, xmm0\npunpcklwd xmm5, xmm4\npunpcklwd xmm3, xmm4\npsubd xmm1, xmm5\npshufd xmm3, xmm3, 4Eh ; 'N'\npsubd xmm1, xmm3\nmovdqa xmm3, xmm0\npunpcklwd xmm0, xmm2\npunpcklwd xmm3, xmm2\npshufd xmm0, xmm0, 4Eh ; 'N'\npsubd xmm1, xmm3\npsubd xmm1, xmm0\nmovd r8d, xmm1\npshufd xmm6, xmm1, 0E5h\nmovd eax, xmm6\nadd eax, r8d\nmov r8, rdi\nand r8, 0FFFFFFFFFFFFFFF8h\nadd rcx, r8\nadd esi, r8d\nand edi, 7\njz loc_1466\nloc_13C5:\nmovzx ecx, byte ptr [rbx+rcx]\nsub ecx, 61h ; 'a'\ncmp cl, 1Ah\nlea ecx, [rsi+1]\nmovsxd rcx, ecx\nadc eax, 0\ncmp rcx, rdx\njnb loc_1466\nmovzx ecx, byte ptr [rbx+rcx]\nsub ecx, 61h ; 'a'\ncmp cl, 1Ah\nlea ecx, [rsi+2]\nmovsxd rcx, ecx\nadc eax, 0\ncmp rcx, rdx\njnb short loc_1466\nmovzx ecx, byte ptr [rbx+rcx]\nsub ecx, 61h ; 'a'\ncmp cl, 1Ah\nlea ecx, [rsi+3]\nmovsxd rcx, ecx\nadc eax, 0\ncmp rcx, rdx\njnb short loc_1466\nmovzx ecx, byte ptr [rbx+rcx]\nsub ecx, 61h ; 'a'\ncmp cl, 1Ah\nlea ecx, [rsi+4]\nmovsxd rcx, ecx\nadc eax, 0\ncmp rcx, rdx\njnb short loc_1466\nmovzx ecx, byte ptr [rbx+rcx]\nsub ecx, 61h ; 'a'\ncmp cl, 1Ah\nlea ecx, [rsi+5]\nmovsxd rcx, ecx\nadc eax, 0\ncmp rcx, rdx\njnb short loc_1466\nmovzx ecx, byte ptr [rbx+rcx]\nsub ecx, 61h ; 'a'\ncmp cl, 1Ah\nadc eax, 0\nadd esi, 6\nmovsxd rsi, esi\ncmp rsi, rdx\njnb short loc_1466\nmovzx edx, byte ptr [rbx+rsi]\nsub edx, 61h ; 'a'\ncmp dl, 1Ah\nadc eax, 0\nloc_1466:\npop rbx\nretn\nloc_1470:\nxor eax, eax\npop rbx\nretn\nloc_1474:\npxor xmm1, xmm1\nxor esi, esi\nxor eax, eax\nxor ecx, ecx\njmp loc_130E", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n size_t v2; // rax\n size_t v3; // rdx\n __m128i v4; // xmm1\n const __m128i *v5; // rax\n unsigned __int64 v6; // rcx\n __m128i si128; // xmm6\n __m128i v8; // xmm5\n __m128i v9; // xmm2\n __m128i v10; // xmm0\n __m128i v11; // xmm7\n __m128i v12; // xmm2\n __m128i v13; // xmm0\n __m128i v14; // xmm7\n __m128i v15; // xmm1\n __m128i v16; // xmm2\n int v17; // esi\n __m128i v18; // xmm0\n __int64 result; // rax\n __m128i v20; // xmm1\n size_t v21; // rdi\n __m128i v22; // xmm0\n __m128i v23; // xmm0\n __m128i v24; // xmm3\n __m128i v25; // xmm0\n __m128i v26; // xmm2\n __m128i v27; // xmm3\n __m128i v28; // xmm1\n bool v29; // cf\n size_t v30; // rcx\n size_t v31; // rcx\n size_t v32; // rcx\n size_t v33; // rcx\n size_t v34; // rcx\n size_t v35; // rsi\n\n v2 = strlen(a1);\n if ( !v2 )\n return 0LL;\n v3 = v2;\n if ( v2 - 1 <= 0xE )\n {\n v20 = 0LL;\n v17 = 0;\n LODWORD(result) = 0;\n v6 = 0LL;\n }\n else\n {\n v4 = 0LL;\n v5 = (const __m128i *)a1;\n v6 = v3 & 0xFFFFFFFFFFFFFFF0LL;\n si128 = _mm_load_si128((const __m128i *)&xmmword_2080);\n v8 = _mm_load_si128((const __m128i *)&xmmword_2090);\n do\n {\n v9 = _mm_loadu_si128(v5++);\n v10 = _mm_cmpeq_epi8(_mm_cmpeq_epi8(_mm_subs_epu8(v8, _mm_add_epi8(v9, si128)), (__m128i)0LL), (__m128i)0LL);\n v11 = _mm_cmpgt_epi8((__m128i)0LL, v10);\n v12 = _mm_unpacklo_epi8(v10, v11);\n v13 = _mm_unpackhi_epi8(v10, v11);\n v14 = _mm_cmpgt_epi16((__m128i)0LL, v12);\n v15 = _mm_sub_epi32(_mm_sub_epi32(v4, _mm_unpacklo_epi16(v12, v14)), _mm_unpackhi_epi16(v12, v14));\n v16 = _mm_cmpgt_epi16((__m128i)0LL, v13);\n v4 = _mm_sub_epi32(_mm_sub_epi32(v15, _mm_unpacklo_epi16(v13, v16)), _mm_unpackhi_epi16(v13, v16));\n }\n while ( &a1[v3 & 0xFFFFFFFFFFFFFFF0LL] != (const char *)v5 );\n v17 = v3 & 0xFFFFFFF0;\n v18 = _mm_add_epi32(_mm_srli_si128(v4, 8), v4);\n result = (unsigned int)_mm_cvtsi128_si32(_mm_add_epi32(v18, _mm_srli_si128(v18, 4)));\n v20 = v18;\n if ( v3 == v6 )\n return result;\n }\n v21 = v3 - v6;\n if ( v3 - v6 - 1 <= 6 )\n goto LABEL_8;\n v22 = _mm_add_epi8(_mm_loadl_epi64((const __m128i *)&a1[v6]), _mm_loadl_epi64((const __m128i *)&xmmword_2080));\n v23 = _mm_cmpeq_epi8(v22, _mm_min_epu8(_mm_loadl_epi64((const __m128i *)&qword_20A0), v22));\n v24 = _mm_unpacklo_epi8(v23, _mm_cmpgt_epi8((__m128i)0LL, v23));\n v25 = _mm_shuffle_epi32(v24, 78);\n v26 = _mm_cmpgt_epi16((__m128i)0LL, v25);\n v27 = _mm_unpacklo_epi16(v24, _mm_cmpgt_epi16((__m128i)0LL, v24));\n v28 = _mm_sub_epi32(\n _mm_sub_epi32(\n _mm_sub_epi32(_mm_sub_epi32(v20, v27), _mm_shuffle_epi32(v27, 78)),\n _mm_unpacklo_epi16(v25, v26)),\n _mm_shuffle_epi32(_mm_unpacklo_epi16(v25, v26), 78));\n result = (unsigned int)(_mm_cvtsi128_si32(v28) + _mm_cvtsi128_si32(_mm_shuffle_epi32(v28, 229)));\n v6 += v21 & 0xFFFFFFFFFFFFFFF8LL;\n v17 += v21 & 0xFFFFFFF8;\n if ( (v21 & 7) != 0 )\n {\nLABEL_8:\n v29 = (unsigned __int8)(a1[v6] - 97) < 0x1Au;\n v30 = v17 + 1;\n result = v29 + (unsigned int)result;\n if ( v30 < v3 )\n {\n v29 = (unsigned __int8)(a1[v30] - 97) < 0x1Au;\n v31 = v17 + 2;\n result = v29 + (unsigned int)result;\n if ( v31 < v3 )\n {\n v29 = (unsigned __int8)(a1[v31] - 97) < 0x1Au;\n v32 = v17 + 3;\n result = v29 + (unsigned int)result;\n if ( v32 < v3 )\n {\n v29 = (unsigned __int8)(a1[v32] - 97) < 0x1Au;\n v33 = v17 + 4;\n result = v29 + (unsigned int)result;\n if ( v33 < v3 )\n {\n v29 = (unsigned __int8)(a1[v33] - 97) < 0x1Au;\n v34 = v17 + 5;\n result = v29 + (unsigned int)result;\n if ( v34 < v3 )\n {\n result = ((unsigned __int8)(a1[v34] - 97) < 0x1Au) + (unsigned int)result;\n v35 = v17 + 6;\n if ( v35 < v3 )\n return ((unsigned __int8)(a1[v35] - 97) < 0x1Au) + (unsigned int)result;\n }\n }\n }\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ntest rax, rax\njz loc_1470\nmov rdx, rax\nlea rax, [rax-1]\ncmp rax, 0Eh\njbe loc_1474\nmov rcx, rdx\npxor xmm1, xmm1\npxor xmm3, xmm3\nmov rax, rbx\nand rcx, 0FFFFFFFFFFFFFFF0h\nmovdqa xmm6, cs:xmmword_2080\nmovdqa xmm5, cs:xmmword_2090\npxor xmm4, xmm4\nlea rsi, [rcx+rbx]\nnop dword ptr [rax+00000000h]\nloc_1268:\nmovdqu xmm2, xmmword ptr [rax]\nmovdqa xmm0, xmm5\nmovdqa xmm7, xmm3\nadd rax, 10h\npaddb xmm2, xmm6\npsubusb xmm0, xmm2\npcmpeqb xmm0, xmm3\npcmpeqb xmm0, xmm3\npcmpgtb xmm7, xmm0\nmovdqa xmm2, xmm0\npunpcklbw xmm2, xmm7\npunpckhbw xmm0, xmm7\nmovdqa xmm7, xmm4\npcmpgtw xmm7, xmm2\nmovdqa xmm8, xmm2\npunpcklwd xmm8, xmm7\npunpckhwd xmm2, xmm7\nmovdqa xmm7, xmm0\npsubd xmm1, xmm8\npsubd xmm1, xmm2\nmovdqa xmm2, xmm4\npcmpgtw xmm2, xmm0\npunpcklwd xmm7, xmm2\npunpckhwd xmm0, xmm2\npsubd xmm1, xmm7\npsubd xmm1, xmm0\ncmp rsi, rax\njnz short loc_1268\nmovdqa xmm0, xmm1\nmov esi, ecx\npsrldq xmm0, 8\npaddd xmm0, xmm1\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\npaddd xmm0, xmm2\nmovd eax, xmm0\nmovdqa xmm0, xmm1\npsrldq xmm1, 8\npaddd xmm1, xmm0\ncmp rdx, rcx\njz loc_1466\nloc_130E:\nmov rdi, rdx\nsub rdi, rcx\nlea r8, [rdi-1]\ncmp r8, 6\njbe loc_13C5\nmovq xmm2, qword ptr cs:xmmword_2080\nmovq xmm0, qword ptr [rbx+rcx]\npaddb xmm0, xmm2\nmovq xmm2, cs:qword_20A0\npminub xmm2, xmm0\npcmpeqb xmm0, xmm2\npxor xmm2, xmm2\npcmpgtb xmm2, xmm0\nmovdqa xmm3, xmm0\npunpcklbw xmm3, xmm2\npunpcklbw xmm0, xmm2\npxor xmm2, xmm2\nmovdqa xmm4, xmm2\nmovdqa xmm5, xmm3\npshufd xmm0, xmm0, 4Eh ; 'N'\npcmpgtw xmm4, xmm3\npcmpgtw xmm2, xmm0\npunpcklwd xmm5, xmm4\npunpcklwd xmm3, xmm4\npsubd xmm1, xmm5\npshufd xmm3, xmm3, 4Eh ; 'N'\npsubd xmm1, xmm3\nmovdqa xmm3, xmm0\npunpcklwd xmm0, xmm2\npunpcklwd xmm3, xmm2\npshufd xmm0, xmm0, 4Eh ; 'N'\npsubd xmm1, xmm3\npsubd xmm1, xmm0\nmovd r8d, xmm1\npshufd xmm6, xmm1, 0E5h\nmovd eax, xmm6\nadd eax, r8d\nmov r8, rdi\nand r8, 0FFFFFFFFFFFFFFF8h\nadd rcx, r8\nadd esi, r8d\nand edi, 7\njz loc_1466\nloc_13C5:\nmovzx ecx, byte ptr [rbx+rcx]\nsub ecx, 61h ; 'a'\ncmp cl, 1Ah\nlea ecx, [rsi+1]\nmovsxd rcx, ecx\nadc eax, 0\ncmp rcx, rdx\njnb loc_1466\nmovzx ecx, byte ptr [rbx+rcx]\nsub ecx, 61h ; 'a'\ncmp cl, 1Ah\nlea ecx, [rsi+2]\nmovsxd rcx, ecx\nadc eax, 0\ncmp rcx, rdx\njnb short loc_1466\nmovzx ecx, byte ptr [rbx+rcx]\nsub ecx, 61h ; 'a'\ncmp cl, 1Ah\nlea ecx, [rsi+3]\nmovsxd rcx, ecx\nadc eax, 0\ncmp rcx, rdx\njnb short loc_1466\nmovzx ecx, byte ptr [rbx+rcx]\nsub ecx, 61h ; 'a'\ncmp cl, 1Ah\nlea ecx, [rsi+4]\nmovsxd rcx, ecx\nadc eax, 0\ncmp rcx, rdx\njnb short loc_1466\nmovzx ecx, byte ptr [rbx+rcx]\nsub ecx, 61h ; 'a'\ncmp cl, 1Ah\nlea ecx, [rsi+5]\nmovsxd rcx, ecx\nadc eax, 0\ncmp rcx, rdx\njnb short loc_1466\nmovzx ecx, byte ptr [rbx+rcx]\nsub ecx, 61h ; 'a'\ncmp cl, 1Ah\nadc eax, 0\nadd esi, 6\nmovsxd rsi, esi\ncmp rsi, rdx\njnb short loc_1466\nmovzx edx, byte ptr [rbx+rsi]\nsub edx, 61h ; 'a'\ncmp dl, 1Ah\nadc eax, 0\nloc_1466:\npop rbx\nretn\nloc_1470:\nxor eax, eax\npop rbx\nretn\nloc_1474:\npxor xmm1, xmm1\nxor esi, esi\nxor eax, eax\nxor ecx, ecx\njmp loc_130E", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(const char *a1)\n{\n size_t v2; // rax\n size_t v3; // rdx\n __m128i v4; // xmm1\n const __m128i *v5; // rax\n unsigned __int64 v6; // rcx\n __m128i si128; // xmm6\n __m128i v8; // xmm5\n __m128i v9; // xmm2\n __m128i v10; // xmm0\n __m128i v11; // xmm7\n __m128i v12; // xmm2\n __m128i v13; // xmm0\n __m128i v14; // xmm7\n __m128i v15; // xmm1\n __m128i v16; // xmm2\n int v17; // esi\n __m128i v18; // xmm0\n __int64 result; // rax\n __m128i v20; // xmm1\n size_t v21; // rdi\n __m128i v22; // xmm0\n __m128i v23; // xmm0\n __m128i v24; // xmm3\n __m128i v25; // xmm0\n __m128i v26; // xmm2\n __m128i v27; // xmm3\n __m128i v28; // xmm1\n bool v29; // cf\n size_t v30; // rcx\n size_t v31; // rcx\n size_t v32; // rcx\n size_t v33; // rcx\n size_t v34; // rcx\n size_t v35; // rsi\n\n v2 = strlen(a1);\n if ( !v2 )\n return 0LL;\n v3 = v2;\n if ( v2 - 1 <= 0xE )\n {\n v20 = 0LL;\n v17 = 0;\n LODWORD(result) = 0;\n v6 = 0LL;\n }\n else\n {\n v4 = 0LL;\n v5 = (const __m128i *)a1;\n v6 = v3 & 0xFFFFFFFFFFFFFFF0LL;\n si128 = _mm_load_si128((const __m128i *)&xmmword_2080);\n v8 = _mm_load_si128((const __m128i *)&xmmword_2090);\n do\n {\n v9 = _mm_loadu_si128(v5++);\n v10 = _mm_cmpeq_epi8(_mm_cmpeq_epi8(_mm_subs_epu8(v8, _mm_add_epi8(v9, si128)), (__m128i)0LL), (__m128i)0LL);\n v11 = _mm_cmpgt_epi8((__m128i)0LL, v10);\n v12 = _mm_unpacklo_epi8(v10, v11);\n v13 = _mm_unpackhi_epi8(v10, v11);\n v14 = _mm_cmpgt_epi16((__m128i)0LL, v12);\n v15 = _mm_sub_epi32(_mm_sub_epi32(v4, _mm_unpacklo_epi16(v12, v14)), _mm_unpackhi_epi16(v12, v14));\n v16 = _mm_cmpgt_epi16((__m128i)0LL, v13);\n v4 = _mm_sub_epi32(_mm_sub_epi32(v15, _mm_unpacklo_epi16(v13, v16)), _mm_unpackhi_epi16(v13, v16));\n }\n while ( &a1[v3 & 0xFFFFFFFFFFFFFFF0LL] != (const char *)v5 );\n v17 = v3 & 0xFFFFFFF0;\n v18 = _mm_add_epi32(_mm_srli_si128(v4, 8), v4);\n result = (unsigned int)_mm_cvtsi128_si32(_mm_add_epi32(v18, _mm_srli_si128(v18, 4)));\n v20 = v18;\n if ( v3 == v6 )\n return result;\n }\n v21 = v3 - v6;\n if ( v3 - v6 - 1 <= 6 )\n goto LABEL_8;\n v22 = _mm_add_epi8(_mm_loadl_epi64((const __m128i *)&a1[v6]), _mm_loadl_epi64((const __m128i *)&xmmword_2080));\n v23 = _mm_cmpeq_epi8(v22, _mm_min_epu8(_mm_loadl_epi64((const __m128i *)&qword_20A0), v22));\n v24 = _mm_unpacklo_epi8(v23, _mm_cmpgt_epi8((__m128i)0LL, v23));\n v25 = _mm_shuffle_epi32(v24, 78);\n v26 = _mm_cmpgt_epi16((__m128i)0LL, v25);\n v27 = _mm_unpacklo_epi16(v24, _mm_cmpgt_epi16((__m128i)0LL, v24));\n v28 = _mm_sub_epi32(\n _mm_sub_epi32(\n _mm_sub_epi32(_mm_sub_epi32(v20, v27), _mm_shuffle_epi32(v27, 78)),\n _mm_unpacklo_epi16(v25, v26)),\n _mm_shuffle_epi32(_mm_unpacklo_epi16(v25, v26), 78));\n result = (unsigned int)(_mm_cvtsi128_si32(v28) + _mm_cvtsi128_si32(_mm_shuffle_epi32(v28, 229)));\n v6 += v21 & 0xFFFFFFFFFFFFFFF8LL;\n v17 += v21 & 0xFFFFFFF8;\n if ( (v21 & 7) != 0 )\n {\nLABEL_8:\n v29 = (unsigned __int8)(a1[v6] - 97) < 0x1Au;\n v30 = v17 + 1;\n result = v29 + (unsigned int)result;\n if ( v30 < v3 )\n {\n v29 = (unsigned __int8)(a1[v30] - 97) < 0x1Au;\n v31 = v17 + 2;\n result = v29 + (unsigned int)result;\n if ( v31 < v3 )\n {\n v29 = (unsigned __int8)(a1[v31] - 97) < 0x1Au;\n v32 = v17 + 3;\n result = v29 + (unsigned int)result;\n if ( v32 < v3 )\n {\n v29 = (unsigned __int8)(a1[v32] - 97) < 0x1Au;\n v33 = v17 + 4;\n result = v29 + (unsigned int)result;\n if ( v33 < v3 )\n {\n v29 = (unsigned __int8)(a1[v33] - 97) < 0x1Au;\n v34 = v17 + 5;\n result = v29 + (unsigned int)result;\n if ( v34 < v3 )\n {\n result = ((unsigned __int8)(a1[v34] - 97) < 0x1Au) + (unsigned int)result;\n v35 = v17 + 6;\n if ( v35 < v3 )\n return ((unsigned __int8)(a1[v35] - 97) < 0x1Au) + (unsigned int)result;\n }\n }\n }\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(const char *a1) {\n unsigned int v2;\n unsigned int v3;\n __m128i v4;\n const __m128i *v5;\n unsigned long long v6;\n __m128i si128;\n __m128i v8;\n __m128i v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n __m128i v15;\n __m128i v16;\n int v17;\n __m128i v18;\n long long result;\n __m128i v20;\n unsigned int v21;\n __m128i v22;\n __m128i v23;\n __m128i v24;\n __m128i v25;\n __m128i v26;\n __m128i v27;\n __m128i v28;\n bool v29;\n unsigned int v30;\n unsigned int v31;\n unsigned int v32;\n unsigned int v33;\n unsigned int v34;\n unsigned int v35;\n v2 = strlen(a1);\n if (!v2) return 0LL;\n v3 = v2;\n if (v2 - 1 <= 14) {\n v20 = 0LL;\n v17 = 0;\n LODWORD(result) = 0;\n v6 = 0LL;\n } else {\n v4 = 0LL;\n v5 = (const __m128i *)a1;\n v6 = v3 & 18446744073709551600LL;\n si128 = _mm_load_si128((const __m128i *)&xmmword_2080);\n v8 = _mm_load_si128((const __m128i *)&xmmword_2090);\n do {\n v9 = _mm_loadu_si128(v5++);\n v10 = _mm_cmpeq_epi8(\n _mm_cmpeq_epi8(_mm_subs_epu8(v8, _mm_add_epi8(v9, si128)),\n (__m128i)0LL),\n (__m128i)0LL);\n v11 = _mm_cmpgt_epi8((__m128i)0LL, v10);\n v12 = _mm_unpacklo_epi8(v10, v11);\n v13 = _mm_unpackhi_epi8(v10, v11);\n v14 = _mm_cmpgt_epi16((__m128i)0LL, v12);\n v15 = _mm_sub_epi32(_mm_sub_epi32(v4, _mm_unpacklo_epi16(v12, v14)),\n _mm_unpackhi_epi16(v12, v14));\n v16 = _mm_cmpgt_epi16((__m128i)0LL, v13);\n v4 = _mm_sub_epi32(_mm_sub_epi32(v15, _mm_unpacklo_epi16(v13, v16)),\n _mm_unpackhi_epi16(v13, v16));\n } while (&a1[v3 & 18446744073709551600LL] != (const char *)v5);\n v17 = v3 & 4294967280;\n v18 = _mm_add_epi32(_mm_srli_si128(v4, 8), v4);\n result = (unsigned int)_mm_cvtsi128_si32(\n _mm_add_epi32(v18, _mm_srli_si128(v18, 4)));\n v20 = v18;\n if (v3 == v6) return result;\n }\n v21 = v3 - v6;\n if (v3 - v6 - 1 <= 6) goto LABEL_8;\n v22 = _mm_add_epi8(_mm_loadl_epi64((const __m128i *)&a1[v6]),\n _mm_loadl_epi64((const __m128i *)&xmmword_2080));\n v23 = _mm_cmpeq_epi8(\n v22, _mm_min_epu8(_mm_loadl_epi64((const __m128i *)&qword_20A0), v22));\n v24 = _mm_unpacklo_epi8(v23, _mm_cmpgt_epi8((__m128i)0LL, v23));\n v25 = _mm_shuffle_epi32(v24, 78);\n v26 = _mm_cmpgt_epi16((__m128i)0LL, v25);\n v27 = _mm_unpacklo_epi16(v24, _mm_cmpgt_epi16((__m128i)0LL, v24));\n v28 = _mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(v20, v27),\n _mm_shuffle_epi32(v27, 78)),\n _mm_unpacklo_epi16(v25, v26)),\n _mm_shuffle_epi32(_mm_unpacklo_epi16(v25, v26), 78));\n result = (unsigned int)(_mm_cvtsi128_si32(v28) +\n _mm_cvtsi128_si32(_mm_shuffle_epi32(v28, 229)));\n v6 += v21 & 18446744073709551608LL;\n v17 += v21 & 4294967288;\n if ((v21 & 7) != 0) {\n LABEL_8:\n v29 = (unsigned char)(a1[v6] - 97) < 26u;\n v30 = v17 + 1;\n result = v29 + (unsigned int)result;\n if (v30 < v3) {\n v29 = (unsigned char)(a1[v30] - 97) < 26u;\n v31 = v17 + 2;\n result = v29 + (unsigned int)result;\n if (v31 < v3) {\n v29 = (unsigned char)(a1[v31] - 97) < 26u;\n v32 = v17 + 3;\n result = v29 + (unsigned int)result;\n if (v32 < v3) {\n v29 = (unsigned char)(a1[v32] - 97) < 26u;\n v33 = v17 + 4;\n result = v29 + (unsigned int)result;\n if (v33 < v3) {\n v29 = (unsigned char)(a1[v33] - 97) < 26u;\n v34 = v17 + 5;\n result = v29 + (unsigned int)result;\n if (v34 < v3) {\n result =\n ((unsigned char)(a1[v34] - 97) < 26u) + (unsigned int)result;\n v35 = v17 + 6;\n if (v35 < v3)\n return ((unsigned char)(a1[v35] - 97) < 26u) +\n (unsigned int)result;\n }\n }\n }\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n unsigned int v2;\n unsigned int v3;\n __m128i v4;\n const __m128i *v5;\n unsigned long long v6;\n __m128i si128;\n __m128i v8;\n __m128i v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n __m128i v13;\n __m128i v14;\n __m128i v15;\n __m128i v16;\n int v17;\n __m128i v18;\n long long result;\n __m128i v20;\n unsigned int v21;\n __m128i v22;\n __m128i v23;\n __m128i v24;\n __m128i v25;\n __m128i v26;\n __m128i v27;\n __m128i v28;\n bool v29;\n unsigned int v30;\n unsigned int v31;\n unsigned int v32;\n unsigned int v33;\n unsigned int v34;\n unsigned int v35;\n v2 = strlen(a1);\n if (!v2) return 0LL;\n v3 = v2;\n if (v2 - 1 <= 14) {\n v20 = 0LL;\n v17 = 0;\n LODWORD(result) = 0;\n v6 = 0LL;\n } else {\n v4 = 0LL;\n v5 = (const __m128i *)a1;\n v6 = v3 & 18446744073709551600LL;\n si128 = _mm_load_si128((const __m128i *)&xmmword_2080);\n v8 = _mm_load_si128((const __m128i *)&xmmword_2090);\n do {\n v9 = _mm_loadu_si128(v5++);\n v10 = _mm_cmpeq_epi8(\n _mm_cmpeq_epi8(_mm_subs_epu8(v8, _mm_add_epi8(v9, si128)),\n (__m128i)0LL),\n (__m128i)0LL);\n v11 = _mm_cmpgt_epi8((__m128i)0LL, v10);\n v12 = _mm_unpacklo_epi8(v10, v11);\n v13 = _mm_unpackhi_epi8(v10, v11);\n v14 = _mm_cmpgt_epi16((__m128i)0LL, v12);\n v15 = _mm_sub_epi32(_mm_sub_epi32(v4, _mm_unpacklo_epi16(v12, v14)),\n _mm_unpackhi_epi16(v12, v14));\n v16 = _mm_cmpgt_epi16((__m128i)0LL, v13);\n v4 = _mm_sub_epi32(_mm_sub_epi32(v15, _mm_unpacklo_epi16(v13, v16)),\n _mm_unpackhi_epi16(v13, v16));\n } while (&a1[v3 & 18446744073709551600LL] != (const char *)v5);\n v17 = v3 & 4294967280;\n v18 = _mm_add_epi32(_mm_srli_si128(v4, 8), v4);\n result = (unsigned int)_mm_cvtsi128_si32(\n _mm_add_epi32(v18, _mm_srli_si128(v18, 4)));\n v20 = v18;\n if (v3 == v6) return result;\n }\n v21 = v3 - v6;\n if (v3 - v6 - 1 <= 6) goto LABEL_8;\n v22 = _mm_add_epi8(_mm_loadl_epi64((const __m128i *)&a1[v6]),\n _mm_loadl_epi64((const __m128i *)&xmmword_2080));\n v23 = _mm_cmpeq_epi8(\n v22, _mm_min_epu8(_mm_loadl_epi64((const __m128i *)&qword_20A0), v22));\n v24 = _mm_unpacklo_epi8(v23, _mm_cmpgt_epi8((__m128i)0LL, v23));\n v25 = _mm_shuffle_epi32(v24, 78);\n v26 = _mm_cmpgt_epi16((__m128i)0LL, v25);\n v27 = _mm_unpacklo_epi16(v24, _mm_cmpgt_epi16((__m128i)0LL, v24));\n v28 = _mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(_mm_sub_epi32(v20, v27),\n _mm_shuffle_epi32(v27, 78)),\n _mm_unpacklo_epi16(v25, v26)),\n _mm_shuffle_epi32(_mm_unpacklo_epi16(v25, v26), 78));\n result = (unsigned int)(_mm_cvtsi128_si32(v28) +\n _mm_cvtsi128_si32(_mm_shuffle_epi32(v28, 229)));\n v6 += v21 & 18446744073709551608LL;\n v17 += v21 & 4294967288;\n if ((v21 & 7) != 0) {\n LABEL_8:\n v29 = (unsigned char)(a1[v6] - 97) < 26u;\n v30 = v17 + 1;\n result = v29 + (unsigned int)result;\n if (v30 < v3) {\n v29 = (unsigned char)(a1[v30] - 97) < 26u;\n v31 = v17 + 2;\n result = v29 + (unsigned int)result;\n if (v31 < v3) {\n v29 = (unsigned char)(a1[v31] - 97) < 26u;\n v32 = v17 + 3;\n result = v29 + (unsigned int)result;\n if (v32 < v3) {\n v29 = (unsigned char)(a1[v32] - 97) < 26u;\n v33 = v17 + 4;\n result = v29 + (unsigned int)result;\n if (v33 < v3) {\n v29 = (unsigned char)(a1[v33] - 97) < 26u;\n v34 = v17 + 5;\n result = v29 + (unsigned int)result;\n if (v34 < v3) {\n result =\n ((unsigned char)(a1[v34] - 97) < 26u) + (unsigned int)result;\n v35 = v17 + 6;\n if (v35 < v3)\n return ((unsigned char)(a1[v35] - 97) < 26u) +\n (unsigned int)result;\n }\n }\n }\n }\n }\n }\n return result;\n}" + }, + { + "index": 819, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int* lists, int list_size, int** elements, int** frequencies,\n int* return_size) {\n *elements = (int*)malloc(sizeof(int) * list_size);\n *frequencies = (int*)malloc(sizeof(int) * list_size);\n int element_count = 0;\n if (list_size == 0) {\n *return_size = 0;\n return;\n }\n int running_count = 1;\n int i;\n for (i = 0; i < list_size - 1; ++i) {\n if (lists[i] == lists[i + 1]) {\n running_count++;\n } else {\n (*frequencies)[element_count] = running_count;\n (*elements)[element_count] = lists[i];\n element_count++;\n running_count = 1;\n }\n }\n (*frequencies)[element_count] = running_count;\n (*elements)[element_count] = lists[i];\n element_count++;\n *return_size = element_count;\n}", + "test": "int main() {\n\n int list1[] = {1,2,2,2,4,4,4,5,5,5,5};\n\n int list2[] = {2,2,3,1,2,6,7,9};\n\n int list3[] = {2,1,5,6,8,3,4,9,10,11,8,12};\n\n\n\n int *elements, *frequencies, size;\n\n\n\n func0(list1, sizeof(list1)/sizeof(list1[0]), &elements, &frequencies, &size);\n\n assert(size == 4);\n\n assert(elements[0] == 1 && frequencies[0] == 1);\n\n assert(elements[1] == 2 && frequencies[1] == 3);\n\n assert(elements[2] == 4 && frequencies[2] == 3);\n\n assert(elements[3] == 5 && frequencies[3] == 4);\n\n free(elements);\n\n free(frequencies);\n\n\n\n func0(list2, sizeof(list2)/sizeof(list2[0]), &elements, &frequencies, &size);\n\n assert(size == 7);\n\n assert(elements[0] == 2 && frequencies[0] == 2);\n\n assert(elements[1] == 3 && frequencies[1] == 1);\n\n free(elements);\n\n free(frequencies);\n\n\n\n func0(list3, sizeof(list3)/sizeof(list3[0]), &elements, &frequencies, &size);\n\n assert(size == 12);\n\n for (int i = 0; i < size; i++) {\n\n assert(frequencies[i] == 1);\n\n }\n\n free(elements);\n\n free(frequencies);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x40,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %rcx,-0x30(%rbp)\nmov %r8,-0x38(%rbp)\nmov -0x1c(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,%rdx\nmov -0x28(%rbp),%rax\nmov %rdx,(%rax)\nmov -0x1c(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,%rdx\nmov -0x30(%rbp),%rax\nmov %rdx,(%rax)\nmovl $0x0,-0xc(%rbp)\ncmpl $0x0,-0x1c(%rbp)\njne 121a \nmov -0x38(%rbp),%rax\nmovl $0x0,(%rax)\njmpq 131e \nmovl $0x1,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmpq 12bc \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 1267 \naddl $0x1,-0x8(%rbp)\njmp 12b8 \nmov -0x30(%rbp),%rax\nmov (%rax),%rax\nmov -0xc(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x2,%rdx\nadd %rax,%rdx\nmov -0x8(%rbp),%eax\nmov %eax,(%rdx)\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x28(%rbp),%rax\nmov (%rax),%rax\nmov -0xc(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x2,%rdx\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\naddl $0x1,-0xc(%rbp)\nmovl $0x1,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x1c(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x4(%rbp)\njl 122d \nmov -0x30(%rbp),%rax\nmov (%rax),%rax\nmov -0xc(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x2,%rdx\nadd %rax,%rdx\nmov -0x8(%rbp),%eax\nmov %eax,(%rdx)\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x28(%rbp),%rax\nmov (%rax),%rax\nmov -0xc(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x2,%rdx\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\naddl $0x1,-0xc(%rbp)\nmov -0x38(%rbp),%rax\nmov -0xc(%rbp),%edx\nmov %edx,(%rax)\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_30], rcx\nmov [rbp+var_38], r8\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov rdx, rax\nmov rax, [rbp+var_28]\nmov [rax], rdx\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov rdx, rax\nmov rax, [rbp+var_30]\nmov [rax], rdx\nmov [rbp+var_C], 0\ncmp [rbp+var_1C], 0\njnz short loc_121A\nmov rax, [rbp+var_38]\nmov dword ptr [rax], 0\njmp locret_131E\nloc_121A:\nmov [rbp+var_8], 1\nmov [rbp+var_4], 0\njmp loc_12BC\nloc_122D:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_1267\nadd [rbp+var_8], 1\njmp short loc_12B8\nloc_1267:\nmov rax, [rbp+var_30]\nmov rax, [rax]\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nshl rdx, 2\nadd rdx, rax\nmov eax, [rbp+var_8]\nmov [rdx], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov rax, [rbp+var_28]\nmov rax, [rax]\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nshl rdx, 2\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nadd [rbp+var_C], 1\nmov [rbp+var_8], 1\nloc_12B8:\nadd [rbp+var_4], 1\nloc_12BC:\nmov eax, [rbp+var_1C]\nsub eax, 1\ncmp [rbp+var_4], eax\njl loc_122D\nmov rax, [rbp+var_30]\nmov rax, [rax]\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nshl rdx, 2\nadd rdx, rax\nmov eax, [rbp+var_8]\nmov [rdx], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov rax, [rbp+var_28]\nmov rax, [rax]\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nshl rdx, 2\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nadd [rbp+var_C], 1\nmov rax, [rbp+var_38]\nmov edx, [rbp+var_C]\nmov [rax], edx\nlocret_131E:\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, void **a3, void **a4, _DWORD *a5)\n{\n _DWORD *result; // rax\n int v9; // [rsp+34h] [rbp-Ch]\n int v10; // [rsp+38h] [rbp-8h]\n int i; // [rsp+3Ch] [rbp-4h]\n\n *a3 = malloc(4LL * a2);\n *a4 = malloc(4LL * a2);\n v9 = 0;\n if ( a2 )\n {\n v10 = 1;\n for ( i = 0; i < a2 - 1; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4 * (i + 1LL) + a1) )\n {\n ++v10;\n }\n else\n {\n *((_DWORD *)*a4 + v9) = v10;\n *((_DWORD *)*a3 + v9++) = *(_DWORD *)(4LL * i + a1);\n v10 = 1;\n }\n }\n *((_DWORD *)*a4 + v9) = v10;\n *((_DWORD *)*a3 + v9) = *(_DWORD *)(4LL * i + a1);\n result = a5;\n *a5 = v9 + 1;\n }\n else\n {\n result = a5;\n *a5 = 0;\n }\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_30], rcx\nmov [rbp+var_38], r8\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov rdx, rax\nmov rax, [rbp+var_28]\nmov [rax], rdx\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov rdx, rax\nmov rax, [rbp+var_30]\nmov [rax], rdx\nmov [rbp+var_C], 0\ncmp [rbp+var_1C], 0\njnz short loc_121A\nmov rax, [rbp+var_38]\nmov dword ptr [rax], 0\njmp locret_131E\nloc_121A:\nmov [rbp+var_8], 1\nmov [rbp+var_4], 0\njmp loc_12BC\nloc_122D:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_1267\nadd [rbp+var_8], 1\njmp short loc_12B8\nloc_1267:\nmov rax, [rbp+var_30]\nmov rax, [rax]\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nshl rdx, 2\nadd rdx, rax\nmov eax, [rbp+var_8]\nmov [rdx], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov rax, [rbp+var_28]\nmov rax, [rax]\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nshl rdx, 2\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nadd [rbp+var_C], 1\nmov [rbp+var_8], 1\nloc_12B8:\nadd [rbp+var_4], 1\nloc_12BC:\nmov eax, [rbp+var_1C]\nsub eax, 1\ncmp [rbp+var_4], eax\njl loc_122D\nmov rax, [rbp+var_30]\nmov rax, [rax]\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nshl rdx, 2\nadd rdx, rax\nmov eax, [rbp+var_8]\nmov [rdx], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov rax, [rbp+var_28]\nmov rax, [rax]\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nshl rdx, 2\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nadd [rbp+var_C], 1\nmov rax, [rbp+var_38]\nmov edx, [rbp+var_C]\nmov [rax], edx\nlocret_131E:\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(__int64 a1, int a2, void **a3, void **a4, _DWORD *a5)\n{\n _DWORD *result; // rax\n int v9; // [rsp+34h] [rbp-Ch]\n int v10; // [rsp+38h] [rbp-8h]\n int i; // [rsp+3Ch] [rbp-4h]\n\n *a3 = malloc(4LL * a2);\n *a4 = malloc(4LL * a2);\n v9 = 0;\n if ( a2 )\n {\n v10 = 1;\n for ( i = 0; i < a2 - 1; ++i )\n {\n if ( *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4 * (i + 1LL) + a1) )\n {\n ++v10;\n }\n else\n {\n *((_DWORD *)*a4 + v9) = v10;\n *((_DWORD *)*a3 + v9++) = *(_DWORD *)(4LL * i + a1);\n v10 = 1;\n }\n }\n *((_DWORD *)*a4 + v9) = v10;\n *((_DWORD *)*a3 + v9) = *(_DWORD *)(4LL * i + a1);\n result = a5;\n *a5 = v9 + 1;\n }\n else\n {\n result = a5;\n *a5 = 0;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(long long a1, int a2, void **a3, void **a4, uint32_t *a5) {\n uint32_t *result;\n int v9;\n int v10;\n int i;\n *a3 = malloc(4LL * a2);\n *a4 = malloc(4LL * a2);\n v9 = 0;\n if (a2) {\n v10 = 1;\n for (i = 0; i < a2 - 1; ++i) {\n if (*(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4 * (i + 1LL) + a1)) {\n ++v10;\n } else {\n *((uint32_t *)*a4 + v9) = v10;\n *((uint32_t *)*a3 + v9++) = *(uint32_t *)(4LL * i + a1);\n v10 = 1;\n }\n }\n *((uint32_t *)*a4 + v9) = v10;\n *((uint32_t *)*a3 + v9) = *(uint32_t *)(4LL * i + a1);\n result = a5;\n *a5 = v9 + 1;\n } else {\n result = a5;\n *a5 = 0;\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, void **a3, void **a4, uint32_t *a5) {\n uint32_t *result;\n int v9;\n int v10;\n int i;\n *a3 = malloc(4LL * a2);\n *a4 = malloc(4LL * a2);\n v9 = 0;\n if (a2) {\n v10 = 1;\n for (i = 0; i < a2 - 1; ++i) {\n if (*(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4 * (i + 1LL) + a1)) {\n ++v10;\n } else {\n *((uint32_t *)*a4 + v9) = v10;\n *((uint32_t *)*a3 + v9++) = *(uint32_t *)(4LL * i + a1);\n v10 = 1;\n }\n }\n *((uint32_t *)*a4 + v9) = v10;\n *((uint32_t *)*a3 + v9) = *(uint32_t *)(4LL * i + a1);\n result = a5;\n *a5 = v9 + 1;\n } else {\n result = a5;\n *a5 = 0;\n }\n return result;\n}" + }, + { + "index": 819, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int* lists, int list_size, int** elements, int** frequencies,\n int* return_size) {\n *elements = (int*)malloc(sizeof(int) * list_size);\n *frequencies = (int*)malloc(sizeof(int) * list_size);\n int element_count = 0;\n if (list_size == 0) {\n *return_size = 0;\n return;\n }\n int running_count = 1;\n int i;\n for (i = 0; i < list_size - 1; ++i) {\n if (lists[i] == lists[i + 1]) {\n running_count++;\n } else {\n (*frequencies)[element_count] = running_count;\n (*elements)[element_count] = lists[i];\n element_count++;\n running_count = 1;\n }\n }\n (*frequencies)[element_count] = running_count;\n (*elements)[element_count] = lists[i];\n element_count++;\n *return_size = element_count;\n}", + "test": "int main() {\n\n int list1[] = {1,2,2,2,4,4,4,5,5,5,5};\n\n int list2[] = {2,2,3,1,2,6,7,9};\n\n int list3[] = {2,1,5,6,8,3,4,9,10,11,8,12};\n\n\n\n int *elements, *frequencies, size;\n\n\n\n func0(list1, sizeof(list1)/sizeof(list1[0]), &elements, &frequencies, &size);\n\n assert(size == 4);\n\n assert(elements[0] == 1 && frequencies[0] == 1);\n\n assert(elements[1] == 2 && frequencies[1] == 3);\n\n assert(elements[2] == 4 && frequencies[2] == 3);\n\n assert(elements[3] == 5 && frequencies[3] == 4);\n\n free(elements);\n\n free(frequencies);\n\n\n\n func0(list2, sizeof(list2)/sizeof(list2[0]), &elements, &frequencies, &size);\n\n assert(size == 7);\n\n assert(elements[0] == 2 && frequencies[0] == 2);\n\n assert(elements[1] == 3 && frequencies[1] == 1);\n\n free(elements);\n\n free(frequencies);\n\n\n\n func0(list3, sizeof(list3)/sizeof(list3[0]), &elements, &frequencies, &size);\n\n assert(size == 12);\n\n for (int i = 0; i < size; i++) {\n\n assert(frequencies[i] == 1);\n\n }\n\n free(elements);\n\n free(frequencies);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%r13\nmov %esi,%ebx\nmov %rdx,%rbp\nmov %rcx,%r12\nmov %r8,%r14\nmovslq %esi,%r15\nshl $0x2,%r15\nmov %r15,%rdi\ncallq 10b0 \nmov %rax,0x0(%rbp)\nmov %r15,%rdi\ncallq 10b0 \nmov %rax,(%r12)\ntest %ebx,%ebx\nje 1219 \ncmp $0x1,%ebx\njle 1208 \nmov %r13,%rax\nlea -0x2(%rbx),%edx\nlea 0x4(%r13,%rdx,4),%r8\nmov $0x1,%ecx\nmov $0x0,%edx\njmp 1246 \nmov $0x0,%ebx\nmov $0x1,%ecx\nmov $0x0,%edx\njmp 1255 \nmovl $0x0,(%r14)\njmp 1274 \nmovslq %edx,%rsi\nmov (%r12),%rdi\nmov %ecx,(%rdi,%rsi,4)\nmov (%rax),%edi\nmov 0x0(%rbp),%rcx\nmov %edi,(%rcx,%rsi,4)\nadd $0x1,%edx\nmov $0x1,%ecx\nadd $0x4,%rax\ncmp %r8,%rax\nje 1252 \nmov 0x4(%rax),%esi\ncmp %esi,(%rax)\njne 1222 \nadd $0x1,%ecx\njmp 123d \nsub $0x1,%ebx\nmovslq %edx,%rax\nmov (%r12),%rsi\nmov %ecx,(%rsi,%rax,4)\nmovslq %ebx,%rbx\nmov 0x0(%r13,%rbx,4),%esi\nmov 0x0(%rbp),%rcx\nmov %esi,(%rcx,%rax,4)\nadd $0x1,%edx\nmov %edx,(%r14)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12, rdi\nmov r14d, esi\nmov rbx, rdx\nmov rbp, rcx\nmov r13, r8\nmovsxd r15, esi\nshl r15, 2\nmov rdi, r15; size\ncall _malloc\nmov [rbx], rax\nmov rdi, r15; size\ncall _malloc\nmov [rbp+0], rax\ntest r14d, r14d\njz short loc_125B\ncmp r14d, 1\njle short loc_126E\nmov rax, r12\nmov r9d, r14d\nlea edx, [r14-2]\nlea r8, [r12+rdx*4+4]\nmov ecx, 1\nmov edx, 0\njmp short loc_1231\nloc_120E:\nmovsxd rsi, edx\nmov rdi, [rbp+0]\nmov [rdi+rsi*4], ecx\nmov edi, [rax]\nmov rcx, [rbx]\nmov [rcx+rsi*4], edi\nadd edx, 1\nmov ecx, 1\nloc_1228:\nadd rax, 4\ncmp rax, r8\njz short loc_123D\nloc_1231:\nmov esi, [rax+4]\ncmp [rax], esi\njnz short loc_120E\nadd ecx, 1\njmp short loc_1228\nloc_123D:\nlea eax, [r9-1]\nloc_1241:\nmovsxd rsi, edx\nmov rdi, [rbp+0]\nmov [rdi+rsi*4], ecx\ncdqe\nmov ecx, [r12+rax*4]\nmov rax, [rbx]\nmov [rax+rsi*4], ecx\nlea r14d, [rdx+1]\nloc_125B:\nmov [r13+0], r14d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_126E:\nmov eax, 0\nmov ecx, 1\nmov edx, 0\njmp short loc_1241", + "ida_pseudo": "void *__fastcall func0(_DWORD *a1, int a2, void **a3, _QWORD *a4, int *a5)\n{\n int v5; // r14d\n void *result; // rax\n _DWORD *v10; // rax\n int v11; // ecx\n int v12; // edx\n int v13; // eax\n int v14; // ecx\n\n v5 = a2;\n *a3 = malloc(4LL * a2);\n result = malloc(4LL * a2);\n *a4 = result;\n if ( a2 )\n {\n if ( a2 <= 1 )\n {\n v13 = 0;\n v11 = 1;\n v12 = 0;\n }\n else\n {\n v10 = a1;\n v11 = 1;\n v12 = 0;\n do\n {\n if ( *v10 == v10[1] )\n {\n ++v11;\n }\n else\n {\n *(_DWORD *)(*a4 + 4LL * v12) = v11;\n *((_DWORD *)*a3 + v12++) = *v10;\n v11 = 1;\n }\n ++v10;\n }\n while ( v10 != &a1[a2 - 2 + 1] );\n v13 = a2 - 1;\n }\n *(_DWORD *)(*a4 + 4LL * v12) = v11;\n v14 = a1[v13];\n result = *a3;\n *((_DWORD *)*a3 + v12) = v14;\n v5 = v12 + 1;\n }\n *a5 = v5;\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12, rdi\nmov r14d, esi\nmov rbx, rdx\nmov rbp, rcx\nmov r13, r8\nmovsxd r15, esi\nshl r15, 2\nmov rdi, r15; size\ncall _malloc\nmov [rbx], rax\nmov rdi, r15; size\ncall _malloc\nmov [rbp+0], rax\ntest r14d, r14d\njz short loc_125B\ncmp r14d, 1\njle short loc_126E\nmov rax, r12\nmov r9d, r14d\nlea edx, [r14-2]\nlea r8, [r12+rdx*4+4]\nmov ecx, 1\nmov edx, 0\njmp short loc_1231\nloc_120E:\nmovsxd rsi, edx\nmov rdi, [rbp+0]\nmov [rdi+rsi*4], ecx\nmov edi, [rax]\nmov rcx, [rbx]\nmov [rcx+rsi*4], edi\nadd edx, 1\nmov ecx, 1\nloc_1228:\nadd rax, 4\ncmp rax, r8\njz short loc_123D\nloc_1231:\nmov esi, [rax+4]\ncmp [rax], esi\njnz short loc_120E\nadd ecx, 1\njmp short loc_1228\nloc_123D:\nlea eax, [r9-1]\nloc_1241:\nmovsxd rsi, edx\nmov rdi, [rbp+0]\nmov [rdi+rsi*4], ecx\ncdqe\nmov ecx, [r12+rax*4]\nmov rax, [rbx]\nmov [rax+rsi*4], ecx\nlea r14d, [rdx+1]\nloc_125B:\nmov [r13+0], r14d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_126E:\nmov eax, 0\nmov ecx, 1\nmov edx, 0\njmp short loc_1241", + "ida_strip_pseudo": "void *__fastcall sub_11A9(_DWORD *a1, int a2, void **a3, _QWORD *a4, int *a5)\n{\n int v5; // r14d\n void *result; // rax\n _DWORD *v10; // rax\n int v11; // ecx\n int v12; // edx\n int v13; // eax\n int v14; // ecx\n\n v5 = a2;\n *a3 = malloc(4LL * a2);\n result = malloc(4LL * a2);\n *a4 = result;\n if ( a2 )\n {\n if ( a2 <= 1 )\n {\n v13 = 0;\n v11 = 1;\n v12 = 0;\n }\n else\n {\n v10 = a1;\n v11 = 1;\n v12 = 0;\n do\n {\n if ( *v10 == v10[1] )\n {\n ++v11;\n }\n else\n {\n *(_DWORD *)(*a4 + 4LL * v12) = v11;\n *((_DWORD *)*a3 + v12++) = *v10;\n v11 = 1;\n }\n ++v10;\n }\n while ( v10 != &a1[a2 - 2 + 1] );\n v13 = a2 - 1;\n }\n *(_DWORD *)(*a4 + 4LL * v12) = v11;\n v14 = a1[v13];\n result = *a3;\n *((_DWORD *)*a3 + v12) = v14;\n v5 = v12 + 1;\n }\n *a5 = v5;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_11A9(uint32_t *a1, int a2, void **a3, uint64_t *a4, int *a5) {\n int v5;\n void *result;\n uint32_t *v10;\n int v11;\n int v12;\n int v13;\n int v14;\n v5 = a2;\n *a3 = malloc(4LL * a2);\n result = malloc(4LL * a2);\n *a4 = result;\n if (a2) {\n if (a2 <= 1) {\n v13 = 0;\n v11 = 1;\n v12 = 0;\n } else {\n v10 = a1;\n v11 = 1;\n v12 = 0;\n do {\n if (*v10 == v10[1]) {\n ++v11;\n } else {\n *(uint32_t *)(*a4 + 4LL * v12) = v11;\n *((uint32_t *)*a3 + v12++) = *v10;\n v11 = 1;\n }\n ++v10;\n } while (v10 != &a1[a2 - 2 + 1]);\n v13 = a2 - 1;\n }\n *(uint32_t *)(*a4 + 4LL * v12) = v11;\n v14 = a1[v13];\n result = *a3;\n *((uint32_t *)*a3 + v12) = v14;\n v5 = v12 + 1;\n }\n *a5 = v5;\n return result;\n}", + "ida_pseudo_norm": "void *func0(uint32_t *a1, int a2, void **a3, uint64_t *a4, int *a5) {\n int v5;\n void *result;\n uint32_t *v10;\n int v11;\n int v12;\n int v13;\n int v14;\n v5 = a2;\n *a3 = malloc(4LL * a2);\n result = malloc(4LL * a2);\n *a4 = result;\n if (a2) {\n if (a2 <= 1) {\n v13 = 0;\n v11 = 1;\n v12 = 0;\n } else {\n v10 = a1;\n v11 = 1;\n v12 = 0;\n do {\n if (*v10 == v10[1]) {\n ++v11;\n } else {\n *(uint32_t *)(*a4 + 4LL * v12) = v11;\n *((uint32_t *)*a3 + v12++) = *v10;\n v11 = 1;\n }\n ++v10;\n } while (v10 != &a1[a2 - 2 + 1]);\n v13 = a2 - 1;\n }\n *(uint32_t *)(*a4 + 4LL * v12) = v11;\n v14 = a1[v13];\n result = *a3;\n *((uint32_t *)*a3 + v12) = v14;\n v5 = v12 + 1;\n }\n *a5 = v5;\n return result;\n}" + }, + { + "index": 819, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int* lists, int list_size, int** elements, int** frequencies,\n int* return_size) {\n *elements = (int*)malloc(sizeof(int) * list_size);\n *frequencies = (int*)malloc(sizeof(int) * list_size);\n int element_count = 0;\n if (list_size == 0) {\n *return_size = 0;\n return;\n }\n int running_count = 1;\n int i;\n for (i = 0; i < list_size - 1; ++i) {\n if (lists[i] == lists[i + 1]) {\n running_count++;\n } else {\n (*frequencies)[element_count] = running_count;\n (*elements)[element_count] = lists[i];\n element_count++;\n running_count = 1;\n }\n }\n (*frequencies)[element_count] = running_count;\n (*elements)[element_count] = lists[i];\n element_count++;\n *return_size = element_count;\n}", + "test": "int main() {\n\n int list1[] = {1,2,2,2,4,4,4,5,5,5,5};\n\n int list2[] = {2,2,3,1,2,6,7,9};\n\n int list3[] = {2,1,5,6,8,3,4,9,10,11,8,12};\n\n\n\n int *elements, *frequencies, size;\n\n\n\n func0(list1, sizeof(list1)/sizeof(list1[0]), &elements, &frequencies, &size);\n\n assert(size == 4);\n\n assert(elements[0] == 1 && frequencies[0] == 1);\n\n assert(elements[1] == 2 && frequencies[1] == 3);\n\n assert(elements[2] == 4 && frequencies[2] == 3);\n\n assert(elements[3] == 5 && frequencies[3] == 4);\n\n free(elements);\n\n free(frequencies);\n\n\n\n func0(list2, sizeof(list2)/sizeof(list2[0]), &elements, &frequencies, &size);\n\n assert(size == 7);\n\n assert(elements[0] == 2 && frequencies[0] == 2);\n\n assert(elements[1] == 3 && frequencies[1] == 1);\n\n free(elements);\n\n free(frequencies);\n\n\n\n func0(list3, sizeof(list3)/sizeof(list3[0]), &elements, &frequencies, &size);\n\n assert(size == 12);\n\n for (int i = 0; i < size; i++) {\n\n assert(frequencies[i] == 1);\n\n }\n\n free(elements);\n\n free(frequencies);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmov %rcx,%r15\npush %r14\nmov %rdx,%r14\npush %r13\nmovslq %esi,%r13\npush %r12\nmov %r8,%r12\npush %rbp\nmov %r13,%rbp\nshl $0x2,%r13\npush %rbx\nmov %rdi,%rbx\nmov %r13,%rdi\nsub $0x8,%rsp\ncallq 10b0 \nmov %r13,%rdi\nmov %rax,(%r14)\ncallq 10b0 \nmov %rax,(%r15)\ntest %ebp,%ebp\nje 1660 \nmov (%r14),%r8\ncmp $0x1,%ebp\njle 1680 \nlea -0x2(%rbp),%edx\nmov %rbx,%rcx\nmov $0x1,%esi\nxor %edi,%edi\nlea 0x4(%rbx,%rdx,4),%r13\njmp 1606 \nnopw %cs:0x0(%rax,%rax,1)\nadd $0x4,%rdx\nadd $0x4,%rcx\nmov %esi,(%r11)\nmov $0x1,%esi\nmov %r9d,(%r10)\nlea (%rax,%rdx,1),%r11\nlea (%r8,%rdx,1),%r10\nlea 0x2(%rdi),%edx\nmov %r14d,%edi\ncmp %rcx,%r13\nje 1631 \nmovslq %edi,%rdx\nmov (%rcx),%r9d\nlea 0x1(%rdi),%r14d\nshl $0x2,%rdx\nlea (%rax,%rdx,1),%r11\nlea (%r8,%rdx,1),%r10\ncmp 0x4(%rcx),%r9d\njne 15e0 \nadd $0x4,%rcx\nadd $0x1,%esi\nmov %r14d,%edx\ncmp %rcx,%r13\njne 1606 \nsub $0x1,%ebp\nmovslq %ebp,%rbp\nlea (%rbx,%rbp,4),%rbx\nmov (%rbx),%eax\nmov %esi,(%r11)\nmov %eax,(%r10)\nmov %edx,(%r12)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw %cs:0x0(%rax,%rax,1)\nmovl $0x0,(%r12)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw 0x0(%rax,%rax,1)\nmov %r8,%r10\nmov %rax,%r11\nmov $0x1,%edx\nmov $0x1,%esi\njmp 163b \nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov r15, rcx\npush r14\nmov r14, r8\npush r13\nmov r13, rdx\npush r12\nmovsxd r12, esi\npush rbp\nmov rbp, rdi\npush rbx\nmov rbx, r12\nshl r12, 2\nmov rdi, r12; size\nsub rsp, 8\ncall _malloc\nmov rdi, r12; size\nmov [r13+0], rax\ncall _malloc\nmov [r15], rax\ntest ebx, ebx\njz short loc_15C0\nmov r10, [r13+0]\nmov r9, rax\ncmp ebx, 1\njle loc_15D8\nlea edx, [rbx-2]\nmov rax, rbp\nmov esi, 1\nxor ecx, ecx\nlea r11, [rbp+rdx*4+4]\njmp short loc_158C\nloc_1570:\nmovsxd rdi, ecx\nadd rax, 4\nadd ecx, 1\nmov [r9+rdi*4], esi\nmov esi, 1\nmov [r10+rdi*4], edx\ncmp r11, rax\njz short loc_159F\nloc_158C:\nmov edx, [rax]\ncmp edx, [rax+4]\njnz short loc_1570\nadd rax, 4\nadd esi, 1\ncmp r11, rax\njnz short loc_158C\nloc_159F:\nmovsxd rax, ecx\nlea edx, [rbx-1]\nlea ebx, [rcx+1]\nshl rax, 2\nlea rbp, [rbp+rdx*4+0]\nadd r9, rax\nadd r10, rax\nloc_15B7:\nmov eax, [rbp+0]\nmov [r9], esi\nmov [r10], eax\nloc_15C0:\nmov [r14], ebx\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15D8:\nmov ebx, 1\nmov esi, 1\njmp short loc_15B7", + "ida_pseudo": "int *__fastcall func0(unsigned int *a1, int a2, void **a3, int **a4, int *a5)\n{\n unsigned int *v8; // rbp\n int v9; // ebx\n int *result; // rax\n _DWORD *v11; // r10\n int *v12; // r9\n unsigned int *v13; // rax\n int v14; // esi\n int v15; // ecx\n __int64 v16; // r11\n __int64 v17; // rdi\n unsigned int v18; // edx\n __int64 v19; // rdx\n __int64 v20; // rax\n\n v8 = a1;\n v9 = a2;\n *a3 = malloc(4LL * a2);\n result = (int *)malloc(4LL * a2);\n *a4 = result;\n if ( a2 )\n {\n v11 = *a3;\n v12 = result;\n if ( a2 <= 1 )\n {\n v9 = 1;\n v14 = 1;\n }\n else\n {\n v13 = a1;\n v14 = 1;\n v15 = 0;\n v16 = (__int64)&a1[v9 - 2 + 1];\n do\n {\n while ( 1 )\n {\n v18 = *v13;\n if ( *v13 == v13[1] )\n break;\n v17 = v15;\n ++v13;\n ++v15;\n v12[v17] = v14;\n v14 = 1;\n v11[v17] = v18;\n if ( (unsigned int *)v16 == v13 )\n goto LABEL_7;\n }\n ++v13;\n ++v14;\n }\n while ( (unsigned int *)v16 != v13 );\nLABEL_7:\n v19 = (unsigned int)(v9 - 1);\n v9 = v15 + 1;\n v20 = 4LL * v15;\n v8 += v19;\n v12 = (int *)((char *)v12 + v20);\n v11 = (_DWORD *)((char *)v11 + v20);\n }\n result = (int *)*v8;\n *v12 = v14;\n *v11 = (_DWORD)result;\n }\n *a5 = v9;\n return result;\n}", + "ida_strip_asm": "sub_1500:\nendbr64\npush r15\nmov r15, rcx\npush r14\nmov r14, r8\npush r13\nmov r13, rdx\npush r12\nmovsxd r12, esi\npush rbp\nmov rbp, rdi\npush rbx\nmov rbx, r12\nshl r12, 2\nmov rdi, r12; size\nsub rsp, 8\ncall _malloc\nmov rdi, r12; size\nmov [r13+0], rax\ncall _malloc\nmov [r15], rax\ntest ebx, ebx\njz short loc_15C0\nmov r10, [r13+0]\nmov r9, rax\ncmp ebx, 1\njle loc_15D8\nlea edx, [rbx-2]\nmov rax, rbp\nmov esi, 1\nxor ecx, ecx\nlea r11, [rbp+rdx*4+4]\njmp short loc_158C\nloc_1570:\nmovsxd rdi, ecx\nadd rax, 4\nadd ecx, 1\nmov [r9+rdi*4], esi\nmov esi, 1\nmov [r10+rdi*4], edx\ncmp r11, rax\njz short loc_159F\nloc_158C:\nmov edx, [rax]\ncmp edx, [rax+4]\njnz short loc_1570\nadd rax, 4\nadd esi, 1\ncmp r11, rax\njnz short loc_158C\nloc_159F:\nmovsxd rax, ecx\nlea edx, [rbx-1]\nlea ebx, [rcx+1]\nshl rax, 2\nlea rbp, [rbp+rdx*4+0]\nadd r9, rax\nadd r10, rax\nloc_15B7:\nmov eax, [rbp+0]\nmov [r9], esi\nmov [r10], eax\nloc_15C0:\nmov [r14], ebx\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15D8:\nmov ebx, 1\nmov esi, 1\njmp short loc_15B7", + "ida_strip_pseudo": "int *__fastcall sub_1500(unsigned int *a1, int a2, void **a3, int **a4, int *a5)\n{\n unsigned int *v8; // rbp\n int v9; // ebx\n int *result; // rax\n _DWORD *v11; // r10\n int *v12; // r9\n unsigned int *v13; // rax\n int v14; // esi\n int v15; // ecx\n __int64 v16; // r11\n __int64 v17; // rdi\n unsigned int v18; // edx\n __int64 v19; // rdx\n __int64 v20; // rax\n\n v8 = a1;\n v9 = a2;\n *a3 = malloc(4LL * a2);\n result = (int *)malloc(4LL * a2);\n *a4 = result;\n if ( a2 )\n {\n v11 = *a3;\n v12 = result;\n if ( a2 <= 1 )\n {\n v9 = 1;\n v14 = 1;\n }\n else\n {\n v13 = a1;\n v14 = 1;\n v15 = 0;\n v16 = (__int64)&a1[v9 - 2 + 1];\n do\n {\n while ( 1 )\n {\n v18 = *v13;\n if ( *v13 == v13[1] )\n break;\n v17 = v15;\n ++v13;\n ++v15;\n v12[v17] = v14;\n v14 = 1;\n v11[v17] = v18;\n if ( (unsigned int *)v16 == v13 )\n goto LABEL_7;\n }\n ++v13;\n ++v14;\n }\n while ( (unsigned int *)v16 != v13 );\nLABEL_7:\n v19 = (unsigned int)(v9 - 1);\n v9 = v15 + 1;\n v20 = 4LL * v15;\n v8 += v19;\n v12 = (int *)((char *)v12 + v20);\n v11 = (_DWORD *)((char *)v11 + v20);\n }\n result = (int *)*v8;\n *v12 = v14;\n *v11 = (_DWORD)result;\n }\n *a5 = v9;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "int *sub_1500(unsigned int *a1, int a2, void **a3, int **a4, int *a5) {\n unsigned int *v8;\n int v9;\n int *result;\n uint32_t *v11;\n int *v12;\n unsigned int *v13;\n int v14;\n int v15;\n long long v16;\n long long v17;\n unsigned int v18;\n long long v19;\n long long v20;\n v8 = a1;\n v9 = a2;\n *a3 = malloc(4LL * a2);\n result = (int *)malloc(4LL * a2);\n *a4 = result;\n if (a2) {\n v11 = *a3;\n v12 = result;\n if (a2 <= 1) {\n v9 = 1;\n v14 = 1;\n } else {\n v13 = a1;\n v14 = 1;\n v15 = 0;\n v16 = (long long)&a1[v9 - 2 + 1];\n do {\n while (1) {\n v18 = *v13;\n if (*v13 == v13[1]) break;\n v17 = v15;\n ++v13;\n ++v15;\n v12[v17] = v14;\n v14 = 1;\n v11[v17] = v18;\n if ((unsigned int *)v16 == v13) goto LABEL_7;\n }\n ++v13;\n ++v14;\n } while ((unsigned int *)v16 != v13);\n LABEL_7:\n v19 = (unsigned int)(v9 - 1);\n v9 = v15 + 1;\n v20 = 4LL * v15;\n v8 += v19;\n v12 = (int *)((char *)v12 + v20);\n v11 = (uint32_t *)((char *)v11 + v20);\n }\n result = (int *)*v8;\n *v12 = v14;\n *v11 = (uint32_t)result;\n }\n *a5 = v9;\n return result;\n}", + "ida_pseudo_norm": "int *func0(unsigned int *a1, int a2, void **a3, int **a4, int *a5) {\n unsigned int *v8;\n int v9;\n int *result;\n uint32_t *v11;\n int *v12;\n unsigned int *v13;\n int v14;\n int v15;\n long long v16;\n long long v17;\n unsigned int v18;\n long long v19;\n long long v20;\n v8 = a1;\n v9 = a2;\n *a3 = malloc(4LL * a2);\n result = (int *)malloc(4LL * a2);\n *a4 = result;\n if (a2) {\n v11 = *a3;\n v12 = result;\n if (a2 <= 1) {\n v9 = 1;\n v14 = 1;\n } else {\n v13 = a1;\n v14 = 1;\n v15 = 0;\n v16 = (long long)&a1[v9 - 2 + 1];\n do {\n while (1) {\n v18 = *v13;\n if (*v13 == v13[1]) break;\n v17 = v15;\n ++v13;\n ++v15;\n v12[v17] = v14;\n v14 = 1;\n v11[v17] = v18;\n if ((unsigned int *)v16 == v13) goto LABEL_7;\n }\n ++v13;\n ++v14;\n } while ((unsigned int *)v16 != v13);\n LABEL_7:\n v19 = (unsigned int)(v9 - 1);\n v9 = v15 + 1;\n v20 = 4LL * v15;\n v8 += v19;\n v12 = (int *)((char *)v12 + v20);\n v11 = (uint32_t *)((char *)v11 + v20);\n }\n result = (int *)*v8;\n *v12 = v14;\n *v11 = (uint32_t)result;\n }\n *a5 = v9;\n return result;\n}" + }, + { + "index": 819, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int* lists, int list_size, int** elements, int** frequencies,\n int* return_size) {\n *elements = (int*)malloc(sizeof(int) * list_size);\n *frequencies = (int*)malloc(sizeof(int) * list_size);\n int element_count = 0;\n if (list_size == 0) {\n *return_size = 0;\n return;\n }\n int running_count = 1;\n int i;\n for (i = 0; i < list_size - 1; ++i) {\n if (lists[i] == lists[i + 1]) {\n running_count++;\n } else {\n (*frequencies)[element_count] = running_count;\n (*elements)[element_count] = lists[i];\n element_count++;\n running_count = 1;\n }\n }\n (*frequencies)[element_count] = running_count;\n (*elements)[element_count] = lists[i];\n element_count++;\n *return_size = element_count;\n}", + "test": "int main() {\n\n int list1[] = {1,2,2,2,4,4,4,5,5,5,5};\n\n int list2[] = {2,2,3,1,2,6,7,9};\n\n int list3[] = {2,1,5,6,8,3,4,9,10,11,8,12};\n\n\n\n int *elements, *frequencies, size;\n\n\n\n func0(list1, sizeof(list1)/sizeof(list1[0]), &elements, &frequencies, &size);\n\n assert(size == 4);\n\n assert(elements[0] == 1 && frequencies[0] == 1);\n\n assert(elements[1] == 2 && frequencies[1] == 3);\n\n assert(elements[2] == 4 && frequencies[2] == 3);\n\n assert(elements[3] == 5 && frequencies[3] == 4);\n\n free(elements);\n\n free(frequencies);\n\n\n\n func0(list2, sizeof(list2)/sizeof(list2[0]), &elements, &frequencies, &size);\n\n assert(size == 7);\n\n assert(elements[0] == 2 && frequencies[0] == 2);\n\n assert(elements[1] == 3 && frequencies[1] == 1);\n\n free(elements);\n\n free(frequencies);\n\n\n\n func0(list3, sizeof(list3)/sizeof(list3[0]), &elements, &frequencies, &size);\n\n assert(size == 12);\n\n for (int i = 0; i < size; i++) {\n\n assert(frequencies[i] == 1);\n\n }\n\n free(elements);\n\n free(frequencies);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmov %rcx,%r15\npush %r14\nmov %rdx,%r14\npush %r13\nmovslq %esi,%r13\npush %r12\nmov %r8,%r12\npush %rbp\nmov %r13,%rbp\nshl $0x2,%r13\npush %rbx\nmov %rdi,%rbx\nmov %r13,%rdi\nsub $0x8,%rsp\ncallq 10b0 \nmov %r13,%rdi\nmov %rax,(%r14)\ncallq 10b0 \nmov %rax,(%r15)\ntest %ebp,%ebp\nje 1620 \nmov (%r14),%r8\ncmp $0x1,%ebp\njle 1640 \nlea -0x2(%rbp),%edx\nmov %rbx,%rcx\nmov $0x1,%esi\nxor %edi,%edi\nlea 0x4(%rbx,%rdx,4),%r13\njmp 15c6 \nnopw %cs:0x0(%rax,%rax,1)\nadd $0x4,%rdx\nadd $0x4,%rcx\nmov %esi,(%r11)\nmov $0x1,%esi\nmov %r9d,(%r10)\nlea (%rax,%rdx,1),%r11\nlea (%r8,%rdx,1),%r10\nlea 0x2(%rdi),%edx\nmov %r14d,%edi\ncmp %rcx,%r13\nje 15f1 \nmovslq %edi,%rdx\nmov (%rcx),%r9d\nlea 0x1(%rdi),%r14d\nshl $0x2,%rdx\nlea (%rax,%rdx,1),%r11\nlea (%r8,%rdx,1),%r10\ncmp 0x4(%rcx),%r9d\njne 15a0 \nadd $0x4,%rcx\nadd $0x1,%esi\nmov %r14d,%edx\ncmp %rcx,%r13\njne 15c6 \nsub $0x1,%ebp\nmovslq %ebp,%rbp\nlea (%rbx,%rbp,4),%rbx\nmov (%rbx),%eax\nmov %esi,(%r11)\nmov %eax,(%r10)\nmov %edx,(%r12)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw %cs:0x0(%rax,%rax,1)\nmovl $0x0,(%r12)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw 0x0(%rax,%rax,1)\nmov %r8,%r10\nmov %rax,%r11\nmov $0x1,%edx\nmov $0x1,%esi\njmp 15fb \nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov r15, rcx\npush r14\nmov r14, r8\npush r13\nmov r13, rdx\npush r12\nmovsxd r12, esi\npush rbp\nmov rbp, rdi\npush rbx\nmov rbx, r12\nshl r12, 2\nmov rdi, r12; size\nsub rsp, 8\ncall _malloc\nmov rdi, r12; size\nmov [r13+0], rax\ncall _malloc\nmov [r15], rax\ntest ebx, ebx\njz short loc_15F0\nmov r10, [r13+0]\nmov r9, rax\ncmp ebx, 1\njle loc_1608\nlea edx, [rbx-2]\nmov rax, rbp\nmov esi, 1\nxor ecx, ecx\nlea r11, [rbp+rdx*4+4]\njmp short loc_15BC\nloc_15A0:\nmovsxd rdi, ecx\nadd rax, 4\nadd ecx, 1\nmov [r9+rdi*4], esi\nmov esi, 1\nmov [r10+rdi*4], edx\ncmp r11, rax\njz short loc_15CF\nloc_15BC:\nmov edx, [rax]\ncmp edx, [rax+4]\njnz short loc_15A0\nadd rax, 4\nadd esi, 1\ncmp r11, rax\njnz short loc_15BC\nloc_15CF:\nmovsxd rax, ecx\nlea edx, [rbx-1]\nlea ebx, [rcx+1]\nshl rax, 2\nlea rbp, [rbp+rdx*4+0]\nadd r9, rax\nadd r10, rax\nloc_15E7:\nmov eax, [rbp+0]\nmov [r9], esi\nmov [r10], eax\nloc_15F0:\nmov [r14], ebx\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1608:\nmov ebx, 1\nmov esi, 1\njmp short loc_15E7", + "ida_pseudo": "int *__fastcall func0(unsigned int *a1, int a2, void **a3, int **a4, int *a5)\n{\n unsigned int *v8; // rbp\n int v9; // ebx\n int *result; // rax\n _DWORD *v11; // r10\n int *v12; // r9\n unsigned int *v13; // rax\n int v14; // esi\n int v15; // ecx\n __int64 v16; // r11\n __int64 v17; // rdi\n unsigned int v18; // edx\n __int64 v19; // rdx\n __int64 v20; // rax\n\n v8 = a1;\n v9 = a2;\n *a3 = malloc(4LL * a2);\n result = (int *)malloc(4LL * a2);\n *a4 = result;\n if ( a2 )\n {\n v11 = *a3;\n v12 = result;\n if ( a2 <= 1 )\n {\n v9 = 1;\n v14 = 1;\n }\n else\n {\n v13 = a1;\n v14 = 1;\n v15 = 0;\n v16 = (__int64)&a1[v9 - 2 + 1];\n do\n {\n while ( 1 )\n {\n v18 = *v13;\n if ( *v13 == v13[1] )\n break;\n v17 = v15;\n ++v13;\n ++v15;\n v12[v17] = v14;\n v14 = 1;\n v11[v17] = v18;\n if ( (unsigned int *)v16 == v13 )\n goto LABEL_7;\n }\n ++v13;\n ++v14;\n }\n while ( (unsigned int *)v16 != v13 );\nLABEL_7:\n v19 = (unsigned int)(v9 - 1);\n v9 = v15 + 1;\n v20 = 4LL * v15;\n v8 += v19;\n v12 = (int *)((char *)v12 + v20);\n v11 = (_DWORD *)((char *)v11 + v20);\n }\n result = (int *)*v8;\n *v12 = v14;\n *v11 = (_DWORD)result;\n }\n *a5 = v9;\n return result;\n}", + "ida_strip_asm": "sub_1530:\nendbr64\npush r15\nmov r15, rcx\npush r14\nmov r14, r8\npush r13\nmov r13, rdx\npush r12\nmovsxd r12, esi\npush rbp\nmov rbp, rdi\npush rbx\nmov rbx, r12\nshl r12, 2\nmov rdi, r12; size\nsub rsp, 8\ncall _malloc\nmov rdi, r12; size\nmov [r13+0], rax\ncall _malloc\nmov [r15], rax\ntest ebx, ebx\njz short loc_15F0\nmov r10, [r13+0]\nmov r9, rax\ncmp ebx, 1\njle loc_1608\nlea edx, [rbx-2]\nmov rax, rbp\nmov esi, 1\nxor ecx, ecx\nlea r11, [rbp+rdx*4+4]\njmp short loc_15BC\nloc_15A0:\nmovsxd rdi, ecx\nadd rax, 4\nadd ecx, 1\nmov [r9+rdi*4], esi\nmov esi, 1\nmov [r10+rdi*4], edx\ncmp r11, rax\njz short loc_15CF\nloc_15BC:\nmov edx, [rax]\ncmp edx, [rax+4]\njnz short loc_15A0\nadd rax, 4\nadd esi, 1\ncmp r11, rax\njnz short loc_15BC\nloc_15CF:\nmovsxd rax, ecx\nlea edx, [rbx-1]\nlea ebx, [rcx+1]\nshl rax, 2\nlea rbp, [rbp+rdx*4+0]\nadd r9, rax\nadd r10, rax\nloc_15E7:\nmov eax, [rbp+0]\nmov [r9], esi\nmov [r10], eax\nloc_15F0:\nmov [r14], ebx\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1608:\nmov ebx, 1\nmov esi, 1\njmp short loc_15E7", + "ida_strip_pseudo": "int *__fastcall sub_1530(unsigned int *a1, int a2, void **a3, int **a4, int *a5)\n{\n unsigned int *v8; // rbp\n int v9; // ebx\n int *result; // rax\n _DWORD *v11; // r10\n int *v12; // r9\n unsigned int *v13; // rax\n int v14; // esi\n int v15; // ecx\n __int64 v16; // r11\n __int64 v17; // rdi\n unsigned int v18; // edx\n __int64 v19; // rdx\n __int64 v20; // rax\n\n v8 = a1;\n v9 = a2;\n *a3 = malloc(4LL * a2);\n result = (int *)malloc(4LL * a2);\n *a4 = result;\n if ( a2 )\n {\n v11 = *a3;\n v12 = result;\n if ( a2 <= 1 )\n {\n v9 = 1;\n v14 = 1;\n }\n else\n {\n v13 = a1;\n v14 = 1;\n v15 = 0;\n v16 = (__int64)&a1[v9 - 2 + 1];\n do\n {\n while ( 1 )\n {\n v18 = *v13;\n if ( *v13 == v13[1] )\n break;\n v17 = v15;\n ++v13;\n ++v15;\n v12[v17] = v14;\n v14 = 1;\n v11[v17] = v18;\n if ( (unsigned int *)v16 == v13 )\n goto LABEL_7;\n }\n ++v13;\n ++v14;\n }\n while ( (unsigned int *)v16 != v13 );\nLABEL_7:\n v19 = (unsigned int)(v9 - 1);\n v9 = v15 + 1;\n v20 = 4LL * v15;\n v8 += v19;\n v12 = (int *)((char *)v12 + v20);\n v11 = (_DWORD *)((char *)v11 + v20);\n }\n result = (int *)*v8;\n *v12 = v14;\n *v11 = (_DWORD)result;\n }\n *a5 = v9;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "int *sub_1530(unsigned int *a1, int a2, void **a3, int **a4, int *a5) {\n unsigned int *v8;\n int v9;\n int *result;\n uint32_t *v11;\n int *v12;\n unsigned int *v13;\n int v14;\n int v15;\n long long v16;\n long long v17;\n unsigned int v18;\n long long v19;\n long long v20;\n v8 = a1;\n v9 = a2;\n *a3 = malloc(4LL * a2);\n result = (int *)malloc(4LL * a2);\n *a4 = result;\n if (a2) {\n v11 = *a3;\n v12 = result;\n if (a2 <= 1) {\n v9 = 1;\n v14 = 1;\n } else {\n v13 = a1;\n v14 = 1;\n v15 = 0;\n v16 = (long long)&a1[v9 - 2 + 1];\n do {\n while (1) {\n v18 = *v13;\n if (*v13 == v13[1]) break;\n v17 = v15;\n ++v13;\n ++v15;\n v12[v17] = v14;\n v14 = 1;\n v11[v17] = v18;\n if ((unsigned int *)v16 == v13) goto LABEL_7;\n }\n ++v13;\n ++v14;\n } while ((unsigned int *)v16 != v13);\n LABEL_7:\n v19 = (unsigned int)(v9 - 1);\n v9 = v15 + 1;\n v20 = 4LL * v15;\n v8 += v19;\n v12 = (int *)((char *)v12 + v20);\n v11 = (uint32_t *)((char *)v11 + v20);\n }\n result = (int *)*v8;\n *v12 = v14;\n *v11 = (uint32_t)result;\n }\n *a5 = v9;\n return result;\n}", + "ida_pseudo_norm": "int *func0(unsigned int *a1, int a2, void **a3, int **a4, int *a5) {\n unsigned int *v8;\n int v9;\n int *result;\n uint32_t *v11;\n int *v12;\n unsigned int *v13;\n int v14;\n int v15;\n long long v16;\n long long v17;\n unsigned int v18;\n long long v19;\n long long v20;\n v8 = a1;\n v9 = a2;\n *a3 = malloc(4LL * a2);\n result = (int *)malloc(4LL * a2);\n *a4 = result;\n if (a2) {\n v11 = *a3;\n v12 = result;\n if (a2 <= 1) {\n v9 = 1;\n v14 = 1;\n } else {\n v13 = a1;\n v14 = 1;\n v15 = 0;\n v16 = (long long)&a1[v9 - 2 + 1];\n do {\n while (1) {\n v18 = *v13;\n if (*v13 == v13[1]) break;\n v17 = v15;\n ++v13;\n ++v15;\n v12[v17] = v14;\n v14 = 1;\n v11[v17] = v18;\n if ((unsigned int *)v16 == v13) goto LABEL_7;\n }\n ++v13;\n ++v14;\n } while ((unsigned int *)v16 != v13);\n LABEL_7:\n v19 = (unsigned int)(v9 - 1);\n v9 = v15 + 1;\n v20 = 4LL * v15;\n v8 += v19;\n v12 = (int *)((char *)v12 + v20);\n v11 = (uint32_t *)((char *)v11 + v20);\n }\n result = (int *)*v8;\n *v12 = v14;\n *v11 = (uint32_t)result;\n }\n *a5 = v9;\n return result;\n}" + }, + { + "index": 820, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int monthnum1) {\n if (monthnum1 == 2) {\n return true;\n } else {\n return false;\n }\n}", + "test": "int main() {\n\n assert(func0(2) == true);\n\n assert(func0(1) == false);\n\n assert(func0(3) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\ncmpl $0x2,-0x4(%rbp)\njne 1161 \nmov $0x1,%eax\njmp 1166 \nmov $0x0,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\ncmp [rbp+var_4], 2\njnz short loc_1161\nmov eax, 1\njmp short loc_1166\nloc_1161:\nmov eax, 0\nloc_1166:\npop rbp\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(int a1)\n{\n return a1 == 2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\ncmp [rbp+var_4], 2\njnz short loc_1161\nmov eax, 1\njmp short loc_1166\nloc_1161:\nmov eax, 0\nloc_1166:\npop rbp\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1149(int a1)\n{\n return a1 == 2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1149(int a1) { return a1 == 2; }", + "ida_pseudo_norm": "uint8_t func0(int a1) { return a1 == 2; }" + }, + { + "index": 821, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char key;\n\n char value[10];\n\n} DictItem;\n\n\n\ntypedef struct {\n\n DictItem *items;\n\n int size;\n\n} Dictionary;\n\n\n\n", + "func": "Dictionary func0(Dictionary dict1, Dictionary dict2) {\n Dictionary merged_dict;\n merged_dict.size = dict1.size + dict2.size;\n merged_dict.items = malloc(merged_dict.size * sizeof(DictItem));\n int k = 0;\n for (int i = 0; i < dict1.size; i++) {\n int found = 0;\n for (int j = 0; j < dict2.size; j++) {\n if (dict1.items[i].key == dict2.items[j].key) {\n found = 1;\n break;\n }\n }\n if (!found) {\n merged_dict.items[k++] = dict1.items[i];\n }\n }\n for (int i = 0; i < dict2.size; i++) {\n merged_dict.items[k++] = dict2.items[i];\n }\n merged_dict.size = k;\n return merged_dict;\n}", + "test": "int main() {\n\n DictItem items1[] = {{'R', \"Red\"}, {'B', \"Black\"}, {'P', \"Pink\"}};\n\n Dictionary dict1 = { items1, 3 };\n\n \n\n DictItem items2[] = {{'G', \"Green\"}, {'W', \"White\"}};\n\n Dictionary dict2 = { items2, 2 };\n\n \n\n Dictionary result1 = func0(dict1, dict2);\n\n\n\n assert(result1.size == 5);\n\n // More assertions could be added for individual dictionary items if needed.\n\n\n\n DictItem items3[] = {{'O', \"Orange\"}, {'W', \"White\"}, {'B', \"Black\"}};\n\n Dictionary dict3 = { items3, 3 };\n\n \n\n Dictionary result2 = func0(dict1, dict3);\n\n\n\n assert(result2.size == 5);\n\n // More assertions could be added for individual dictionary items if needed.\n\n\n\n Dictionary result3 = func0(dict2, dict3);\n\n\n\n assert(result3.size == 4);\n\n // More assertions could be added for individual dictionary items if needed.\n\n\n\n free(result1.items);\n\n free(result2.items);\n\n free(result3.items);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x50,%rsp\nmov %rsi,%rax\nmov %rdi,%r8\nmov %r8,%rsi\nmov %r9,%rdi\nmov %rax,%rdi\nmov %rsi,-0x40(%rbp)\nmov %rdi,-0x38(%rbp)\nmov %rdx,-0x50(%rbp)\nmov %rcx,-0x48(%rbp)\nmov -0x38(%rbp),%edx\nmov -0x48(%rbp),%eax\nadd %edx,%eax\nmov %eax,-0x8(%rbp)\nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x10(%rbp)\nmovl $0x0,-0x24(%rbp)\nmovl $0x0,-0x20(%rbp)\njmpq 12dd \nmovl $0x0,-0x1c(%rbp)\nmovl $0x0,-0x18(%rbp)\njmp 1275 \nmov -0x40(%rbp),%rcx\nmov -0x20(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nadd %rcx,%rax\nmovzbl (%rax),%ecx\nmov -0x50(%rbp),%rsi\nmov -0x18(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nadd %rsi,%rax\nmovzbl (%rax),%eax\ncmp %al,%cl\njne 1271 \nmovl $0x1,-0x1c(%rbp)\njmp 127d \naddl $0x1,-0x18(%rbp)\nmov -0x48(%rbp),%eax\ncmp %eax,-0x18(%rbp)\njl 1224 \ncmpl $0x0,-0x1c(%rbp)\njne 12d9 \nmov -0x40(%rbp),%rcx\nmov -0x20(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nlea (%rcx,%rax,1),%rdx\nmov -0x10(%rbp),%rsi\nmov -0x24(%rbp),%eax\nlea 0x1(%rax),%ecx\nmov %ecx,-0x24(%rbp)\nmovslq %eax,%rcx\nmov %rcx,%rax\nshl $0x2,%rax\nadd %rcx,%rax\nadd %rax,%rax\nadd %rcx,%rax\nadd %rsi,%rax\nmov (%rdx),%rcx\nmov %rcx,(%rax)\nmovzwl 0x8(%rdx),%ecx\nmov %cx,0x8(%rax)\nmovzbl 0xa(%rdx),%edx\nmov %dl,0xa(%rax)\naddl $0x1,-0x20(%rbp)\nmov -0x38(%rbp),%eax\ncmp %eax,-0x20(%rbp)\njl 1214 \nmovl $0x0,-0x14(%rbp)\njmp 134c \nmov -0x50(%rbp),%rcx\nmov -0x14(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nlea (%rcx,%rax,1),%rdx\nmov -0x10(%rbp),%rsi\nmov -0x24(%rbp),%eax\nlea 0x1(%rax),%ecx\nmov %ecx,-0x24(%rbp)\nmovslq %eax,%rcx\nmov %rcx,%rax\nshl $0x2,%rax\nadd %rcx,%rax\nadd %rax,%rax\nadd %rcx,%rax\nadd %rsi,%rax\nmov (%rdx),%rcx\nmov %rcx,(%rax)\nmovzwl 0x8(%rdx),%ecx\nmov %cx,0x8(%rax)\nmovzbl 0xa(%rdx),%edx\nmov %dl,0xa(%rax)\naddl $0x1,-0x14(%rbp)\nmov -0x48(%rbp),%eax\ncmp %eax,-0x14(%rbp)\njl 12f2 \nmov -0x24(%rbp),%eax\nmov %eax,-0x8(%rbp)\nmov -0x10(%rbp),%rax\nmov -0x8(%rbp),%rdx\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov rax, rdi\nmov r8, rsi\nmov rsi, rax\nmov rdi, rdx\nmov rdi, r8\nmov [rbp+var_40], rsi\nmov [rbp+var_38], rdi\nmov [rbp+var_50], rdx\nmov [rbp+var_48], rcx\nmov edx, dword ptr [rbp+var_38]\nmov eax, dword ptr [rbp+var_48]\nadd eax, edx\nmov dword ptr [rbp+var_8], eax\nmov eax, dword ptr [rbp+var_8]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nadd rax, rax\nadd rax, rdx\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_10], rax\nmov [rbp+var_24], 0\nmov [rbp+var_20], 0\njmp loc_12D3\nloc_1214:\nmov [rbp+var_1C], 0\nmov [rbp+var_18], 0\njmp short loc_1275\nloc_1224:\nmov rcx, [rbp+var_40]\nmov eax, [rbp+var_20]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nadd rax, rax\nadd rax, rdx\nadd rax, rcx\nmovzx ecx, byte ptr [rax]\nmov rsi, [rbp+var_50]\nmov eax, [rbp+var_18]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nadd rax, rax\nadd rax, rdx\nadd rax, rsi\nmovzx eax, byte ptr [rax]\ncmp cl, al\njnz short loc_1271\nmov [rbp+var_1C], 1\njmp short loc_127D\nloc_1271:\nadd [rbp+var_18], 1\nloc_1275:\nmov eax, dword ptr [rbp+var_48]\ncmp [rbp+var_18], eax\njl short loc_1224\nloc_127D:\ncmp [rbp+var_1C], 0\njnz short loc_12CF\nmov rcx, [rbp+var_40]\nmov eax, [rbp+var_20]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nadd rax, rax\nadd rax, rdx\nadd rcx, rax\nmov rsi, [rbp+var_10]\nmov eax, [rbp+var_24]\nlea edx, [rax+1]\nmov [rbp+var_24], edx\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nadd rax, rax\nadd rax, rdx\nadd rax, rsi\nmov rdx, [rcx]\nmov [rax], rdx\nmov edx, [rcx+7]\nmov [rax+7], edx\nloc_12CF:\nadd [rbp+var_20], 1\nloc_12D3:\nmov eax, dword ptr [rbp+var_38]\ncmp [rbp+var_20], eax\njl loc_1214\nmov [rbp+var_14], 0\njmp short loc_1338\nloc_12E8:\nmov rcx, [rbp+var_50]\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nadd rax, rax\nadd rax, rdx\nadd rcx, rax\nmov rsi, [rbp+var_10]\nmov eax, [rbp+var_24]\nlea edx, [rax+1]\nmov [rbp+var_24], edx\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nadd rax, rax\nadd rax, rdx\nadd rax, rsi\nmov rdx, [rcx]\nmov [rax], rdx\nmov edx, [rcx+7]\nmov [rax+7], edx\nadd [rbp+var_14], 1\nloc_1338:\nmov eax, dword ptr [rbp+var_48]\ncmp [rbp+var_14], eax\njl short loc_12E8\nmov eax, [rbp+var_24]\nmov dword ptr [rbp+var_8], eax\nmov rax, [rbp+var_10]\nmov rdx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2, __int64 a3, int a4)\n{\n __int64 v4; // rcx\n int v5; // eax\n char *v6; // rax\n __int64 v7; // rcx\n int v8; // eax\n char *v9; // rax\n int v13; // [rsp+2Ch] [rbp-24h]\n int i; // [rsp+30h] [rbp-20h]\n int v15; // [rsp+34h] [rbp-1Ch]\n int j; // [rsp+38h] [rbp-18h]\n int k; // [rsp+3Ch] [rbp-14h]\n char *v18; // [rsp+40h] [rbp-10h]\n\n v18 = (char *)malloc(11LL * (a2 + a4));\n v13 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v15 = 0;\n for ( j = 0; j < a4; ++j )\n {\n if ( *(_BYTE *)(a1 + 11LL * i) == *(_BYTE *)(a3 + 11LL * j) )\n {\n v15 = 1;\n break;\n }\n }\n if ( !v15 )\n {\n v4 = 11LL * i + a1;\n v5 = v13++;\n v6 = &v18[11 * v5];\n *(_QWORD *)v6 = *(_QWORD *)v4;\n *(_DWORD *)(v6 + 7) = *(_DWORD *)(v4 + 7);\n }\n }\n for ( k = 0; k < a4; ++k )\n {\n v7 = 11LL * k + a3;\n v8 = v13++;\n v9 = &v18[11 * v8];\n *(_QWORD *)v9 = *(_QWORD *)v7;\n *(_DWORD *)(v9 + 7) = *(_DWORD *)(v7 + 7);\n }\n return v18;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov rax, rdi\nmov r8, rsi\nmov rsi, rax\nmov rdi, rdx\nmov rdi, r8\nmov [rbp+var_40], rsi\nmov [rbp+var_38], rdi\nmov [rbp+var_50], rdx\nmov [rbp+var_48], rcx\nmov edx, dword ptr [rbp+var_38]\nmov eax, dword ptr [rbp+var_48]\nadd eax, edx\nmov dword ptr [rbp+var_8], eax\nmov eax, dword ptr [rbp+var_8]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nadd rax, rax\nadd rax, rdx\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_10], rax\nmov [rbp+var_24], 0\nmov [rbp+var_20], 0\njmp loc_12D3\nloc_1214:\nmov [rbp+var_1C], 0\nmov [rbp+var_18], 0\njmp short loc_1275\nloc_1224:\nmov rcx, [rbp+var_40]\nmov eax, [rbp+var_20]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nadd rax, rax\nadd rax, rdx\nadd rax, rcx\nmovzx ecx, byte ptr [rax]\nmov rsi, [rbp+var_50]\nmov eax, [rbp+var_18]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nadd rax, rax\nadd rax, rdx\nadd rax, rsi\nmovzx eax, byte ptr [rax]\ncmp cl, al\njnz short loc_1271\nmov [rbp+var_1C], 1\njmp short loc_127D\nloc_1271:\nadd [rbp+var_18], 1\nloc_1275:\nmov eax, dword ptr [rbp+var_48]\ncmp [rbp+var_18], eax\njl short loc_1224\nloc_127D:\ncmp [rbp+var_1C], 0\njnz short loc_12CF\nmov rcx, [rbp+var_40]\nmov eax, [rbp+var_20]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nadd rax, rax\nadd rax, rdx\nadd rcx, rax\nmov rsi, [rbp+var_10]\nmov eax, [rbp+var_24]\nlea edx, [rax+1]\nmov [rbp+var_24], edx\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nadd rax, rax\nadd rax, rdx\nadd rax, rsi\nmov rdx, [rcx]\nmov [rax], rdx\nmov edx, [rcx+7]\nmov [rax+7], edx\nloc_12CF:\nadd [rbp+var_20], 1\nloc_12D3:\nmov eax, dword ptr [rbp+var_38]\ncmp [rbp+var_20], eax\njl loc_1214\nmov [rbp+var_14], 0\njmp short loc_1338\nloc_12E8:\nmov rcx, [rbp+var_50]\nmov eax, [rbp+var_14]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nadd rax, rax\nadd rax, rdx\nadd rcx, rax\nmov rsi, [rbp+var_10]\nmov eax, [rbp+var_24]\nlea edx, [rax+1]\nmov [rbp+var_24], edx\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nadd rax, rax\nadd rax, rdx\nadd rax, rsi\nmov rdx, [rcx]\nmov [rax], rdx\nmov edx, [rcx+7]\nmov [rax+7], edx\nadd [rbp+var_14], 1\nloc_1338:\nmov eax, dword ptr [rbp+var_48]\ncmp [rbp+var_14], eax\njl short loc_12E8\nmov eax, [rbp+var_24]\nmov dword ptr [rbp+var_8], eax\nmov rax, [rbp+var_10]\nmov rdx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11A9(__int64 a1, int a2, __int64 a3, int a4)\n{\n __int64 v4; // rcx\n int v5; // eax\n char *v6; // rax\n __int64 v7; // rcx\n int v8; // eax\n char *v9; // rax\n int v13; // [rsp+2Ch] [rbp-24h]\n int i; // [rsp+30h] [rbp-20h]\n int v15; // [rsp+34h] [rbp-1Ch]\n int j; // [rsp+38h] [rbp-18h]\n int k; // [rsp+3Ch] [rbp-14h]\n char *v18; // [rsp+40h] [rbp-10h]\n\n v18 = (char *)malloc(11LL * (a2 + a4));\n v13 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v15 = 0;\n for ( j = 0; j < a4; ++j )\n {\n if ( *(_BYTE *)(a1 + 11LL * i) == *(_BYTE *)(a3 + 11LL * j) )\n {\n v15 = 1;\n break;\n }\n }\n if ( !v15 )\n {\n v4 = 11LL * i + a1;\n v5 = v13++;\n v6 = &v18[11 * v5];\n *(_QWORD *)v6 = *(_QWORD *)v4;\n *(_DWORD *)(v6 + 7) = *(_DWORD *)(v4 + 7);\n }\n }\n for ( k = 0; k < a4; ++k )\n {\n v7 = 11LL * k + a3;\n v8 = v13++;\n v9 = &v18[11 * v8];\n *(_QWORD *)v9 = *(_QWORD *)v7;\n *(_DWORD *)(v9 + 7) = *(_DWORD *)(v7 + 7);\n }\n return v18;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11A9(long long a1, int a2, long long a3, int a4) {\n long long v4;\n int v5;\n char *v6;\n long long v7;\n int v8;\n char *v9;\n int v13;\n int i;\n int v15;\n int j;\n int k;\n char *v18;\n v18 = (char *)malloc(11LL * (a2 + a4));\n v13 = 0;\n for (i = 0; i < a2; ++i) {\n v15 = 0;\n for (j = 0; j < a4; ++j) {\n if (*(uint8_t *)(a1 + 11LL * i) == *(uint8_t *)(a3 + 11LL * j)) {\n v15 = 1;\n break;\n }\n }\n if (!v15) {\n v4 = 11LL * i + a1;\n v5 = v13++;\n v6 = &v18[11 * v5];\n *(uint64_t *)v6 = *(uint64_t *)v4;\n *(uint32_t *)(v6 + 7) = *(uint32_t *)(v4 + 7);\n }\n }\n for (k = 0; k < a4; ++k) {\n v7 = 11LL * k + a3;\n v8 = v13++;\n v9 = &v18[11 * v8];\n *(uint64_t *)v9 = *(uint64_t *)v7;\n *(uint32_t *)(v9 + 7) = *(uint32_t *)(v7 + 7);\n }\n return v18;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2, long long a3, int a4) {\n long long v4;\n int v5;\n char *v6;\n long long v7;\n int v8;\n char *v9;\n int v13;\n int i;\n int v15;\n int j;\n int k;\n char *v18;\n v18 = (char *)malloc(11LL * (a2 + a4));\n v13 = 0;\n for (i = 0; i < a2; ++i) {\n v15 = 0;\n for (j = 0; j < a4; ++j) {\n if (*(uint8_t *)(a1 + 11LL * i) == *(uint8_t *)(a3 + 11LL * j)) {\n v15 = 1;\n break;\n }\n }\n if (!v15) {\n v4 = 11LL * i + a1;\n v5 = v13++;\n v6 = &v18[11 * v5];\n *(uint64_t *)v6 = *(uint64_t *)v4;\n *(uint32_t *)(v6 + 7) = *(uint32_t *)(v4 + 7);\n }\n }\n for (k = 0; k < a4; ++k) {\n v7 = 11LL * k + a3;\n v8 = v13++;\n v9 = &v18[11 * v8];\n *(uint64_t *)v9 = *(uint64_t *)v7;\n *(uint32_t *)(v9 + 7) = *(uint32_t *)(v7 + 7);\n }\n return v18;\n}" + }, + { + "index": 821, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char key;\n\n char value[10];\n\n} DictItem;\n\n\n\ntypedef struct {\n\n DictItem *items;\n\n int size;\n\n} Dictionary;\n\n\n\n", + "func": "Dictionary func0(Dictionary dict1, Dictionary dict2) {\n Dictionary merged_dict;\n merged_dict.size = dict1.size + dict2.size;\n merged_dict.items = malloc(merged_dict.size * sizeof(DictItem));\n int k = 0;\n for (int i = 0; i < dict1.size; i++) {\n int found = 0;\n for (int j = 0; j < dict2.size; j++) {\n if (dict1.items[i].key == dict2.items[j].key) {\n found = 1;\n break;\n }\n }\n if (!found) {\n merged_dict.items[k++] = dict1.items[i];\n }\n }\n for (int i = 0; i < dict2.size; i++) {\n merged_dict.items[k++] = dict2.items[i];\n }\n merged_dict.size = k;\n return merged_dict;\n}", + "test": "int main() {\n\n DictItem items1[] = {{'R', \"Red\"}, {'B', \"Black\"}, {'P', \"Pink\"}};\n\n Dictionary dict1 = { items1, 3 };\n\n \n\n DictItem items2[] = {{'G', \"Green\"}, {'W', \"White\"}};\n\n Dictionary dict2 = { items2, 2 };\n\n \n\n Dictionary result1 = func0(dict1, dict2);\n\n\n\n assert(result1.size == 5);\n\n // More assertions could be added for individual dictionary items if needed.\n\n\n\n DictItem items3[] = {{'O', \"Orange\"}, {'W', \"White\"}, {'B', \"Black\"}};\n\n Dictionary dict3 = { items3, 3 };\n\n \n\n Dictionary result2 = func0(dict1, dict3);\n\n\n\n assert(result2.size == 5);\n\n // More assertions could be added for individual dictionary items if needed.\n\n\n\n Dictionary result3 = func0(dict2, dict3);\n\n\n\n assert(result3.size == 4);\n\n // More assertions could be added for individual dictionary items if needed.\n\n\n\n free(result1.items);\n\n free(result2.items);\n\n free(result3.items);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%r15\nmov %rsi,%r13\nmov %rdx,%r14\nmov %rcx,%rbp\nmov %rdx,%rbx\nmov %ecx,%r12d\nlea (%rcx,%rsi,1),%eax\ncltq\nlea (%rax,%rax,4),%rdx\nlea (%rax,%rdx,2),%rdi\ncallq 10b0 \ntest %r13d,%r13d\njle 1216 \nmov %r15,%rdi\nlea -0x1(%r13),%edx\nlea (%rdx,%rdx,4),%rcx\nlea (%rdx,%rcx,2),%rdx\nlea 0xb(%r15,%rdx,1),%r9\nmov %r14,%r10\nlea -0x1(%rbp),%edx\nlea (%rdx,%rdx,4),%rcx\nlea (%rdx,%rcx,2),%rdx\nlea 0xb(%rdx,%r14,1),%rsi\nmov $0x0,%r8d\njmpq 12b0 \nmov $0x0,%r8d\ntest %ebp,%ebp\njle 126a \nlea -0x1(%rbp),%edx\nadd $0x1,%rdx\nlea (%rdx,%rdx,4),%rcx\nlea (%rdx,%rcx,2),%rdi\nmovslq %r8d,%rdx\nlea (%rdx,%rdx,4),%rcx\nlea (%rdx,%rcx,2),%rcx\nadd %rax,%rcx\nmov $0x0,%edx\nmov (%rbx,%rdx,1),%rsi\nmov %rsi,(%rcx,%rdx,1)\nmovzwl 0x8(%rbx,%rdx,1),%esi\nmov %si,0x8(%rcx,%rdx,1)\nmovzbl 0xa(%rbx,%rdx,1),%esi\nmov %sil,0xa(%rcx,%rdx,1)\nadd $0xb,%rdx\ncmp %rdi,%rdx\njne 1242 \nadd %ebp,%r8d\nmov %r8d,%edx\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmovslq %r8d,%rdx\nlea (%rdx,%rdx,4),%rcx\nlea (%rdx,%rcx,2),%rdx\nadd %rax,%rdx\nmov (%rdi),%rcx\nmov %rcx,(%rdx)\nmovzwl 0x8(%rdi),%ecx\nmov %cx,0x8(%rdx)\nmovzbl 0xa(%rdi),%ecx\nmov %cl,0xa(%rdx)\nlea 0x1(%r8),%r8d\nadd $0xb,%rdi\ncmp %r9,%rdi\nje 121c \ntest %r12d,%r12d\njle 127c \nmovzbl (%rdi),%ecx\nmov %r10,%rdx\ncmp (%rdx),%cl\nje 12a3 \nadd $0xb,%rdx\ncmp %rsi,%rdx\njne 12bb \njmp 127c \n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r14, rdi\nmov r13, rsi\nmov rbx, rdx\nmov rbp, rcx\nmov r12d, ecx\nlea eax, [rsi+rcx]\ncdqe\nlea rdx, [rax+rax*4]\nlea rdi, [rax+rdx*2]; size\ncall _malloc\nmov rdi, rax\ntest r13d, r13d\njle short loc_1248\nmov rsi, r14\nmovsxd r13, r13d\nlea rax, [r13+r13*4+0]\nlea r9, [r13+rax*2+0]\nadd r9, r14\nmovsxd rax, ebp\nlea rdx, [rax+rax*4]\nlea rcx, [rax+rdx*2]\nadd rcx, rbx\nmov r8d, 0\njmp short loc_122E\nloc_1207:\nmovsxd rax, r8d\nlea rdx, [rax+rax*4]\nlea rax, [rax+rdx*2]\nadd rax, rdi\nmov rdx, [rsi]\nmov [rax], rdx\nmov edx, [rsi+7]\nmov [rax+7], edx\nlea r8d, [r8+1]\nloc_1225:\nadd rsi, 0Bh\ncmp rsi, r9\njz short loc_124E\nloc_122E:\ntest r12d, r12d\njle short loc_1207\nmovzx edx, byte ptr [rsi]\nmov rax, rbx\nloc_1239:\ncmp dl, [rax]\njz short loc_1225\nadd rax, 0Bh\ncmp rax, rcx\njnz short loc_1239\njmp short loc_1207\nloc_1248:\nmov r8d, 0\nloc_124E:\ntest ebp, ebp\njle short loc_128C\nmovsxd rax, ebp\nlea rdx, [rax+rax*4]\nlea rsi, [rax+rdx*2]\nmovsxd rax, r8d\nlea rdx, [rax+rax*4]\nlea rdx, [rax+rdx*2]\nadd rdx, rdi\nmov eax, 0\nloc_1270:\nmov rcx, [rbx+rax]\nmov [rdx+rax], rcx\nmov ecx, [rax+rbx+7]\nmov [rdx+rax+7], ecx\nadd rax, 0Bh\ncmp rax, rsi\njnz short loc_1270\nadd r8d, ebp\nloc_128C:\nmov edx, r8d\nmov rax, rdi\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2, _BYTE *a3, int a4)\n{\n char *v9; // rdi\n __int64 v10; // rsi\n int v11; // r8d\n char *v12; // rax\n _BYTE *v13; // rax\n char *v14; // rdx\n __int64 v15; // rax\n\n v9 = (char *)malloc(11LL * (a2 + a4));\n if ( a2 <= 0 )\n {\n v11 = 0;\n }\n else\n {\n v10 = a1;\n v11 = 0;\n do\n {\n if ( a4 <= 0 )\n {\nLABEL_3:\n v12 = &v9[11 * v11];\n *(_QWORD *)v12 = *(_QWORD *)v10;\n *(_DWORD *)(v12 + 7) = *(_DWORD *)(v10 + 7);\n ++v11;\n }\n else\n {\n v13 = a3;\n while ( *(_BYTE *)v10 != *v13 )\n {\n v13 += 11;\n if ( v13 == &a3[11 * a4] )\n goto LABEL_3;\n }\n }\n v10 += 11LL;\n }\n while ( v10 != a1 + 11LL * a2 );\n }\n if ( a4 > 0 )\n {\n v14 = &v9[11 * v11];\n v15 = 0LL;\n do\n {\n *(_QWORD *)&v14[v15] = *(_QWORD *)&a3[v15];\n *(_DWORD *)&v14[v15 + 7] = *(_DWORD *)&a3[v15 + 7];\n v15 += 11LL;\n }\n while ( v15 != 11LL * a4 );\n }\n return v9;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r14, rdi\nmov r13, rsi\nmov rbx, rdx\nmov rbp, rcx\nmov r12d, ecx\nlea eax, [rsi+rcx]\ncdqe\nlea rdx, [rax+rax*4]\nlea rdi, [rax+rdx*2]; size\ncall _malloc\nmov rdi, rax\ntest r13d, r13d\njle short loc_1248\nmov rsi, r14\nmovsxd r13, r13d\nlea rax, [r13+r13*4+0]\nlea r9, [r13+rax*2+0]\nadd r9, r14\nmovsxd rax, ebp\nlea rdx, [rax+rax*4]\nlea rcx, [rax+rdx*2]\nadd rcx, rbx\nmov r8d, 0\njmp short loc_122E\nloc_1207:\nmovsxd rax, r8d\nlea rdx, [rax+rax*4]\nlea rax, [rax+rdx*2]\nadd rax, rdi\nmov rdx, [rsi]\nmov [rax], rdx\nmov edx, [rsi+7]\nmov [rax+7], edx\nlea r8d, [r8+1]\nloc_1225:\nadd rsi, 0Bh\ncmp rsi, r9\njz short loc_124E\nloc_122E:\ntest r12d, r12d\njle short loc_1207\nmovzx edx, byte ptr [rsi]\nmov rax, rbx\nloc_1239:\ncmp dl, [rax]\njz short loc_1225\nadd rax, 0Bh\ncmp rax, rcx\njnz short loc_1239\njmp short loc_1207\nloc_1248:\nmov r8d, 0\nloc_124E:\ntest ebp, ebp\njle short loc_128C\nmovsxd rax, ebp\nlea rdx, [rax+rax*4]\nlea rsi, [rax+rdx*2]\nmovsxd rax, r8d\nlea rdx, [rax+rax*4]\nlea rdx, [rax+rdx*2]\nadd rdx, rdi\nmov eax, 0\nloc_1270:\nmov rcx, [rbx+rax]\nmov [rdx+rax], rcx\nmov ecx, [rax+rbx+7]\nmov [rdx+rax+7], ecx\nadd rax, 0Bh\ncmp rax, rsi\njnz short loc_1270\nadd r8d, ebp\nloc_128C:\nmov edx, r8d\nmov rax, rdi\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11A9(__int64 a1, int a2, _BYTE *a3, int a4)\n{\n char *v9; // rdi\n __int64 v10; // rsi\n int v11; // r8d\n char *v12; // rax\n _BYTE *v13; // rax\n char *v14; // rdx\n __int64 v15; // rax\n\n v9 = (char *)malloc(11LL * (a2 + a4));\n if ( a2 <= 0 )\n {\n v11 = 0;\n }\n else\n {\n v10 = a1;\n v11 = 0;\n do\n {\n if ( a4 <= 0 )\n {\nLABEL_3:\n v12 = &v9[11 * v11];\n *(_QWORD *)v12 = *(_QWORD *)v10;\n *(_DWORD *)(v12 + 7) = *(_DWORD *)(v10 + 7);\n ++v11;\n }\n else\n {\n v13 = a3;\n while ( *(_BYTE *)v10 != *v13 )\n {\n v13 += 11;\n if ( v13 == &a3[11 * a4] )\n goto LABEL_3;\n }\n }\n v10 += 11LL;\n }\n while ( v10 != a1 + 11LL * a2 );\n }\n if ( a4 > 0 )\n {\n v14 = &v9[11 * v11];\n v15 = 0LL;\n do\n {\n *(_QWORD *)&v14[v15] = *(_QWORD *)&a3[v15];\n *(_DWORD *)&v14[v15 + 7] = *(_DWORD *)&a3[v15 + 7];\n v15 += 11LL;\n }\n while ( v15 != 11LL * a4 );\n }\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11A9(long long a1, int a2, uint8_t *a3, int a4) {\n char *v9;\n long long v10;\n int v11;\n char *v12;\n uint8_t *v13;\n char *v14;\n long long v15;\n v9 = (char *)malloc(11LL * (a2 + a4));\n if (a2 <= 0) {\n v11 = 0;\n } else {\n v10 = a1;\n v11 = 0;\n do {\n if (a4 <= 0) {\n LABEL_3:\n v12 = &v9[11 * v11];\n *(uint64_t *)v12 = *(uint64_t *)v10;\n *(uint32_t *)(v12 + 7) = *(uint32_t *)(v10 + 7);\n ++v11;\n } else {\n v13 = a3;\n while (*(uint8_t *)v10 != *v13) {\n v13 += 11;\n if (v13 == &a3[11 * a4]) goto LABEL_3;\n }\n }\n v10 += 11LL;\n } while (v10 != a1 + 11LL * a2);\n }\n if (a4 > 0) {\n v14 = &v9[11 * v11];\n v15 = 0LL;\n do {\n *(uint64_t *)&v14[v15] = *(uint64_t *)&a3[v15];\n *(uint32_t *)&v14[v15 + 7] = *(uint32_t *)&a3[v15 + 7];\n v15 += 11LL;\n } while (v15 != 11LL * a4);\n }\n return v9;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2, uint8_t *a3, int a4) {\n char *v9;\n long long v10;\n int v11;\n char *v12;\n uint8_t *v13;\n char *v14;\n long long v15;\n v9 = (char *)malloc(11LL * (a2 + a4));\n if (a2 <= 0) {\n v11 = 0;\n } else {\n v10 = a1;\n v11 = 0;\n do {\n if (a4 <= 0) {\n LABEL_3:\n v12 = &v9[11 * v11];\n *(uint64_t *)v12 = *(uint64_t *)v10;\n *(uint32_t *)(v12 + 7) = *(uint32_t *)(v10 + 7);\n ++v11;\n } else {\n v13 = a3;\n while (*(uint8_t *)v10 != *v13) {\n v13 += 11;\n if (v13 == &a3[11 * a4]) goto LABEL_3;\n }\n }\n v10 += 11LL;\n } while (v10 != a1 + 11LL * a2);\n }\n if (a4 > 0) {\n v14 = &v9[11 * v11];\n v15 = 0LL;\n do {\n *(uint64_t *)&v14[v15] = *(uint64_t *)&a3[v15];\n *(uint32_t *)&v14[v15 + 7] = *(uint32_t *)&a3[v15 + 7];\n v15 += 11LL;\n } while (v15 != 11LL * a4);\n }\n return v9;\n}" + }, + { + "index": 821, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char key;\n\n char value[10];\n\n} DictItem;\n\n\n\ntypedef struct {\n\n DictItem *items;\n\n int size;\n\n} Dictionary;\n\n\n\n", + "func": "Dictionary func0(Dictionary dict1, Dictionary dict2) {\n Dictionary merged_dict;\n merged_dict.size = dict1.size + dict2.size;\n merged_dict.items = malloc(merged_dict.size * sizeof(DictItem));\n int k = 0;\n for (int i = 0; i < dict1.size; i++) {\n int found = 0;\n for (int j = 0; j < dict2.size; j++) {\n if (dict1.items[i].key == dict2.items[j].key) {\n found = 1;\n break;\n }\n }\n if (!found) {\n merged_dict.items[k++] = dict1.items[i];\n }\n }\n for (int i = 0; i < dict2.size; i++) {\n merged_dict.items[k++] = dict2.items[i];\n }\n merged_dict.size = k;\n return merged_dict;\n}", + "test": "int main() {\n\n DictItem items1[] = {{'R', \"Red\"}, {'B', \"Black\"}, {'P', \"Pink\"}};\n\n Dictionary dict1 = { items1, 3 };\n\n \n\n DictItem items2[] = {{'G', \"Green\"}, {'W', \"White\"}};\n\n Dictionary dict2 = { items2, 2 };\n\n \n\n Dictionary result1 = func0(dict1, dict2);\n\n\n\n assert(result1.size == 5);\n\n // More assertions could be added for individual dictionary items if needed.\n\n\n\n DictItem items3[] = {{'O', \"Orange\"}, {'W', \"White\"}, {'B', \"Black\"}};\n\n Dictionary dict3 = { items3, 3 };\n\n \n\n Dictionary result2 = func0(dict1, dict3);\n\n\n\n assert(result2.size == 5);\n\n // More assertions could be added for individual dictionary items if needed.\n\n\n\n Dictionary result3 = func0(dict2, dict3);\n\n\n\n assert(result3.size == 4);\n\n // More assertions could be added for individual dictionary items if needed.\n\n\n\n free(result1.items);\n\n free(result2.items);\n\n free(result3.items);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nlea (%rcx,%rsi,1),%eax\npush %r14\nmov %rsi,%r14\npush %r13\ncltq\nmov %rdi,%r13\npush %r12\nmov %ecx,%r12d\npush %rbp\nmov %rcx,%rbp\npush %rbx\nmov %rdx,%rbx\nlea (%rax,%rax,4),%rdx\nlea (%rax,%rdx,2),%rdi\ncallq 10b0 \ntest %r14d,%r14d\njle 14ed \nlea -0x1(%r14),%edx\nmov %r13,%r9\nxor %r10d,%r10d\nlea (%rdx,%rdx,4),%rcx\nlea (%rdx,%rcx,2),%rdx\nlea 0xb(%r13,%rdx,1),%rcx\nlea -0x1(%rbp),%edx\nlea (%rdx,%rdx,4),%rsi\nlea (%rdx,%rsi,2),%rdx\nlea 0xb(%rdx,%rbx,1),%r8\nnopl (%rax)\ntest %r12d,%r12d\njle 14b0 \nmovzbl (%r9),%edi\nmov %rbx,%rsi\njmp 1441 \nnopw 0x0(%rax,%rax,1)\nadd $0xb,%rsi\ncmp %rsi,%r8\nje 14b0 \ncmp (%rsi),%dil\njne 1438 \nadd $0xb,%r9\ncmp %rcx,%r9\njne 1420 \ntest %ebp,%ebp\njle 14a0 \nlea -0x1(%rbp),%edx\nxor %esi,%esi\nadd $0x1,%rdx\nlea (%rdx,%rdx,4),%rcx\nlea (%rdx,%rcx,2),%r8\nmovslq %r10d,%rdx\nlea (%rdx,%rdx,4),%rcx\nlea (%rdx,%rcx,2),%rdx\nadd %rax,%rdx\nnopw 0x0(%rax,%rax,1)\nmov (%rbx,%rsi,1),%rcx\nmovzbl 0xa(%rbx,%rsi,1),%edi\nmov %rcx,(%rdx,%rsi,1)\nmovzwl 0x8(%rbx,%rsi,1),%ecx\nmov %dil,0xa(%rdx,%rsi,1)\nmov %cx,0x8(%rdx,%rsi,1)\nadd $0xb,%rsi\ncmp %r8,%rsi\njne 1478 \nadd %ebp,%r10d\npop %rbx\nmov %r10d,%edx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopl 0x0(%rax)\nmovslq %r10d,%rdx\nadd $0xb,%r9\nadd $0x1,%r10d\nlea (%rdx,%rdx,4),%rsi\nlea (%rdx,%rsi,2),%rdx\nmov -0xb(%r9),%rsi\nadd %rax,%rdx\nmov %rsi,(%rdx)\nmovzwl -0x3(%r9),%esi\nmov %si,0x8(%rdx)\nmovzbl -0x1(%r9),%esi\nmov %sil,0xa(%rdx)\ncmp %rcx,%r9\njne 1420 \njmpq 144f \nxor %r10d,%r10d\njmpq 144f \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\nlea eax, [rsi+rcx]\nmov r15, rdi\npush r14\ncdqe\nmov r14d, ecx\npush r13\nmov r13, rsi\npush r12\nmov r12, rcx\npush rbp\npush rbx\nmov rbx, rdx\nlea rdx, [rax+rax*4]\nlea rdi, [rax+rdx*2]; size\nsub rsp, 8\ncall _malloc\nmov rbp, rax\ntest r13d, r13d\njle loc_1470\nmovsxd r13, r13d\nmov rsi, r15\nxor edi, edi\nlea rax, [r13+r13*4+0]\nlea r8, [r13+rax*2+0]\nmovsxd rax, r12d\nlea rdx, [rax+rax*4]\nadd r8, r15\nlea rcx, [rax+rdx*2]\nadd rcx, rbx\nnop word ptr [rax+rax+00h]\nloc_13D8:\ntest r14d, r14d\njle short loc_1440\nloc_13DD:\nmovzx edx, byte ptr [rsi]\nmov rax, rbx\njmp short loc_13F1\nloc_13E8:\nadd rax, 0Bh\ncmp rax, rcx\njz short loc_1440\nloc_13F1:\ncmp dl, [rax]\njnz short loc_13E8\nadd rsi, 0Bh\ncmp r8, rsi\njnz short loc_13DD\nmov r13d, edi\nloc_1401:\ntest r12d, r12d\njle short loc_142A\nmovsxd rax, r13d\nmov rsi, rbx; src\nadd r13d, r12d\nlea rdx, [rax+rax*4]\nlea rdi, [rax+rdx*2]\nmov eax, r12d\nlea rdx, [rax+rax*4]\nadd rdi, rbp; dest\nlea rdx, [rax+rdx*2]; n\ncall _memcpy\nloc_142A:\nadd rsp, 8\nmov edx, r13d\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1440:\nmovsxd rax, edi\nadd rsi, 0Bh\nlea r13d, [rdi+1]\nlea rdx, [rax+rax*4]\nlea rax, [rax+rdx*2]\nmov rdx, [rsi-0Bh]\nadd rax, rbp\nmov [rax], rdx\nmov edx, [rsi-4]\nmov [rax+7], edx\ncmp rsi, r8\njz short loc_1401\nmov edi, r13d\njmp loc_13D8\nloc_1470:\nxor r13d, r13d\njmp short loc_1401", + "ida_pseudo": "char *__fastcall func0(_BYTE *a1, int a2, _BYTE *a3, int a4)\n{\n char *v8; // rbp\n _BYTE *v10; // rsi\n int v11; // edi\n _BYTE *v12; // r8\n _BYTE *v13; // rax\n int v14; // r13d\n char *v16; // rax\n\n v8 = (char *)malloc(11LL * (a2 + a4));\n if ( a2 <= 0 )\n {\n v14 = 0;\n }\n else\n {\n v10 = a1;\n v11 = 0;\n v12 = &a1[11 * a2];\n while ( a4 <= 0 )\n {\nLABEL_12:\n v10 += 11;\n v14 = v11 + 1;\n v16 = &v8[11 * v11];\n *(_QWORD *)v16 = *(_QWORD *)(v10 - 11);\n *(_DWORD *)(v16 + 7) = *((_DWORD *)v10 - 1);\n if ( v10 == v12 )\n goto LABEL_9;\n ++v11;\n }\n do\n {\n v13 = a3;\n while ( *v10 != *v13 )\n {\n v13 += 11;\n if ( v13 == &a3[11 * a4] )\n goto LABEL_12;\n }\n v10 += 11;\n }\n while ( v12 != v10 );\n v14 = v11;\n }\nLABEL_9:\n if ( a4 > 0 )\n memcpy(&v8[11 * v14], a3, 11LL * (unsigned int)a4);\n return v8;\n}", + "ida_strip_asm": "sub_1370:\nendbr64\npush r15\nlea eax, [rsi+rcx]\nmov r15, rdi\npush r14\ncdqe\nmov r14d, ecx\npush r13\nmov r13, rsi\npush r12\nmov r12, rcx\npush rbp\npush rbx\nmov rbx, rdx\nlea rdx, [rax+rax*4]\nlea rdi, [rax+rdx*2]; size\nsub rsp, 8\ncall _malloc\nmov rbp, rax\ntest r13d, r13d\njle loc_1470\nmovsxd r13, r13d\nmov rsi, r15\nxor edi, edi\nlea rax, [r13+r13*4+0]\nlea r8, [r13+rax*2+0]\nmovsxd rax, r12d\nlea rdx, [rax+rax*4]\nadd r8, r15\nlea rcx, [rax+rdx*2]\nadd rcx, rbx\nnop word ptr [rax+rax+00h]\nloc_13D8:\ntest r14d, r14d\njle short loc_1440\nloc_13DD:\nmovzx edx, byte ptr [rsi]\nmov rax, rbx\njmp short loc_13F1\nloc_13E8:\nadd rax, 0Bh\ncmp rax, rcx\njz short loc_1440\nloc_13F1:\ncmp dl, [rax]\njnz short loc_13E8\nadd rsi, 0Bh\ncmp r8, rsi\njnz short loc_13DD\nmov r13d, edi\nloc_1401:\ntest r12d, r12d\njle short loc_142A\nmovsxd rax, r13d\nmov rsi, rbx; src\nadd r13d, r12d\nlea rdx, [rax+rax*4]\nlea rdi, [rax+rdx*2]\nmov eax, r12d\nlea rdx, [rax+rax*4]\nadd rdi, rbp; dest\nlea rdx, [rax+rdx*2]; n\ncall _memcpy\nloc_142A:\nadd rsp, 8\nmov edx, r13d\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1440:\nmovsxd rax, edi\nadd rsi, 0Bh\nlea r13d, [rdi+1]\nlea rdx, [rax+rax*4]\nlea rax, [rax+rdx*2]\nmov rdx, [rsi-0Bh]\nadd rax, rbp\nmov [rax], rdx\nmov edx, [rsi-4]\nmov [rax+7], edx\ncmp rsi, r8\njz short loc_1401\nmov edi, r13d\njmp loc_13D8\nloc_1470:\nxor r13d, r13d\njmp short loc_1401", + "ida_strip_pseudo": "char *__fastcall sub_1370(_BYTE *a1, int a2, _BYTE *a3, int a4)\n{\n char *v8; // rbp\n _BYTE *v10; // rsi\n int v11; // edi\n _BYTE *v12; // r8\n _BYTE *v13; // rax\n int v14; // r13d\n char *v16; // rax\n\n v8 = (char *)malloc(11LL * (a2 + a4));\n if ( a2 <= 0 )\n {\n v14 = 0;\n }\n else\n {\n v10 = a1;\n v11 = 0;\n v12 = &a1[11 * a2];\n while ( a4 <= 0 )\n {\nLABEL_12:\n v10 += 11;\n v14 = v11 + 1;\n v16 = &v8[11 * v11];\n *(_QWORD *)v16 = *(_QWORD *)(v10 - 11);\n *(_DWORD *)(v16 + 7) = *((_DWORD *)v10 - 1);\n if ( v10 == v12 )\n goto LABEL_9;\n ++v11;\n }\n do\n {\n v13 = a3;\n while ( *v10 != *v13 )\n {\n v13 += 11;\n if ( v13 == &a3[11 * a4] )\n goto LABEL_12;\n }\n v10 += 11;\n }\n while ( v12 != v10 );\n v14 = v11;\n }\nLABEL_9:\n if ( a4 > 0 )\n memcpy(&v8[11 * v14], a3, 11LL * (unsigned int)a4);\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1370(uint8_t *a1, int a2, uint8_t *a3, int a4) {\n char *v8;\n uint8_t *v10;\n int v11;\n uint8_t *v12;\n uint8_t *v13;\n int v14;\n char *v16;\n v8 = (char *)malloc(11LL * (a2 + a4));\n if (a2 <= 0) {\n v14 = 0;\n } else {\n v10 = a1;\n v11 = 0;\n v12 = &a1[11 * a2];\n while (a4 <= 0) {\n LABEL_12:\n v10 += 11;\n v14 = v11 + 1;\n v16 = &v8[11 * v11];\n *(uint64_t *)v16 = *(uint64_t *)(v10 - 11);\n *(uint32_t *)(v16 + 7) = *((uint32_t *)v10 - 1);\n if (v10 == v12) goto LABEL_9;\n ++v11;\n }\n do {\n v13 = a3;\n while (*v10 != *v13) {\n v13 += 11;\n if (v13 == &a3[11 * a4]) goto LABEL_12;\n }\n v10 += 11;\n } while (v12 != v10);\n v14 = v11;\n }\nLABEL_9:\n if (a4 > 0) memcpy(&v8[11 * v14], a3, 11LL * (unsigned int)a4);\n return v8;\n}", + "ida_pseudo_norm": "char *func0(uint8_t *a1, int a2, uint8_t *a3, int a4) {\n char *v8;\n uint8_t *v10;\n int v11;\n uint8_t *v12;\n uint8_t *v13;\n int v14;\n char *v16;\n v8 = (char *)malloc(11LL * (a2 + a4));\n if (a2 <= 0) {\n v14 = 0;\n } else {\n v10 = a1;\n v11 = 0;\n v12 = &a1[11 * a2];\n while (a4 <= 0) {\n LABEL_12:\n v10 += 11;\n v14 = v11 + 1;\n v16 = &v8[11 * v11];\n *(uint64_t *)v16 = *(uint64_t *)(v10 - 11);\n *(uint32_t *)(v16 + 7) = *((uint32_t *)v10 - 1);\n if (v10 == v12) goto LABEL_9;\n ++v11;\n }\n do {\n v13 = a3;\n while (*v10 != *v13) {\n v13 += 11;\n if (v13 == &a3[11 * a4]) goto LABEL_12;\n }\n v10 += 11;\n } while (v12 != v10);\n v14 = v11;\n }\nLABEL_9:\n if (a4 > 0) memcpy(&v8[11 * v14], a3, 11LL * (unsigned int)a4);\n return v8;\n}" + }, + { + "index": 821, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char key;\n\n char value[10];\n\n} DictItem;\n\n\n\ntypedef struct {\n\n DictItem *items;\n\n int size;\n\n} Dictionary;\n\n\n\n", + "func": "Dictionary func0(Dictionary dict1, Dictionary dict2) {\n Dictionary merged_dict;\n merged_dict.size = dict1.size + dict2.size;\n merged_dict.items = malloc(merged_dict.size * sizeof(DictItem));\n int k = 0;\n for (int i = 0; i < dict1.size; i++) {\n int found = 0;\n for (int j = 0; j < dict2.size; j++) {\n if (dict1.items[i].key == dict2.items[j].key) {\n found = 1;\n break;\n }\n }\n if (!found) {\n merged_dict.items[k++] = dict1.items[i];\n }\n }\n for (int i = 0; i < dict2.size; i++) {\n merged_dict.items[k++] = dict2.items[i];\n }\n merged_dict.size = k;\n return merged_dict;\n}", + "test": "int main() {\n\n DictItem items1[] = {{'R', \"Red\"}, {'B', \"Black\"}, {'P', \"Pink\"}};\n\n Dictionary dict1 = { items1, 3 };\n\n \n\n DictItem items2[] = {{'G', \"Green\"}, {'W', \"White\"}};\n\n Dictionary dict2 = { items2, 2 };\n\n \n\n Dictionary result1 = func0(dict1, dict2);\n\n\n\n assert(result1.size == 5);\n\n // More assertions could be added for individual dictionary items if needed.\n\n\n\n DictItem items3[] = {{'O', \"Orange\"}, {'W', \"White\"}, {'B', \"Black\"}};\n\n Dictionary dict3 = { items3, 3 };\n\n \n\n Dictionary result2 = func0(dict1, dict3);\n\n\n\n assert(result2.size == 5);\n\n // More assertions could be added for individual dictionary items if needed.\n\n\n\n Dictionary result3 = func0(dict2, dict3);\n\n\n\n assert(result3.size == 4);\n\n // More assertions could be added for individual dictionary items if needed.\n\n\n\n free(result1.items);\n\n free(result2.items);\n\n free(result3.items);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nlea (%rcx,%rsi,1),%eax\nmov %rsi,%r15\npush %r14\ncltq\nmov %ecx,%r14d\npush %r13\nmov %rcx,%r13\npush %r12\npush %rbp\nmov %rdx,%rbp\nlea (%rax,%rax,4),%rdx\npush %rbx\nmov %rdi,%rbx\nlea (%rax,%rdx,2),%rdi\nsub $0x8,%rsp\ncallq 10d0 \nmov %rax,%r12\ntest %r15d,%r15d\njle 14f6 \nlea -0x1(%r15),%eax\nmov %rbx,%rdi\nlea (%rax,%rax,4),%rdx\nlea (%rax,%rdx,2),%rax\nlea 0xb(%rbx,%rax,1),%rcx\nlea -0x1(%r13),%eax\nxor %ebx,%ebx\nlea (%rax,%rax,4),%rdx\nlea (%rax,%rdx,2),%rax\nlea 0xb(%rax,%rbp,1),%rsi\nnopw %cs:0x0(%rax,%rax,1)\ntest %r14d,%r14d\njle 14c0 \nmovzbl (%rdi),%edx\nmov %rbp,%rax\njmp 1469 \nnopl (%rax)\nadd $0xb,%rax\ncmp %rax,%rsi\nje 14c0 \ncmp (%rax),%dl\njne 1460 \nadd $0xb,%rdi\ncmp %rcx,%rdi\njne 1450 \ntest %r13d,%r13d\njle 14a4 \nmovslq %ebx,%rax\nmov %rbp,%rsi\nadd %r13d,%ebx\nlea (%rax,%rax,4),%rdx\nlea (%rax,%rdx,2),%rdi\nlea -0x1(%r13),%eax\nadd $0x1,%rax\nadd %r12,%rdi\nlea (%rax,%rax,4),%rdx\nlea (%rax,%rdx,2),%rdx\ncallq 10c0 \nadd $0x8,%rsp\nmov %ebx,%edx\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax,%rax,1)\nmovslq %ebx,%rax\nadd $0xb,%rdi\nadd $0x1,%ebx\nlea (%rax,%rax,4),%rdx\nlea (%rax,%rdx,2),%rax\nmov -0xb(%rdi),%rdx\nadd %r12,%rax\nmov %rdx,(%rax)\nmovzwl -0x3(%rdi),%edx\nmov %dx,0x8(%rax)\nmovzbl -0x1(%rdi),%edx\nmov %dl,0xa(%rax)\ncmp %rcx,%rdi\njne 1450 \njmp 1476 \nxor %ebx,%ebx\njmpq 1476 \nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\nlea eax, [rsi+rcx]\nmov r15, rdi\npush r14\ncdqe\nmov r14d, ecx\npush r13\nmov r13, rsi\npush r12\nmov r12, rcx\npush rbp\npush rbx\nmov rbx, rdx\nlea rdx, [rax+rax*4]\nlea rdi, [rax+rdx*2]; size\nsub rsp, 8\ncall _malloc\nmov rbp, rax\ntest r13d, r13d\njle loc_1470\nmovsxd r13, r13d\nmov rsi, r15\nxor edi, edi\nlea rax, [r13+r13*4+0]\nlea r8, [r13+rax*2+0]\nmovsxd rax, r12d\nlea rdx, [rax+rax*4]\nadd r8, r15\nlea rcx, [rax+rdx*2]\nadd rcx, rbx\nnop word ptr [rax+rax+00h]\nloc_13D8:\ntest r14d, r14d\njle short loc_1440\nloc_13DD:\nmovzx edx, byte ptr [rsi]\nmov rax, rbx\njmp short loc_13F1\nloc_13E8:\nadd rax, 0Bh\ncmp rax, rcx\njz short loc_1440\nloc_13F1:\ncmp dl, [rax]\njnz short loc_13E8\nadd rsi, 0Bh\ncmp r8, rsi\njnz short loc_13DD\nmov r13d, edi\nloc_1401:\ntest r12d, r12d\njle short loc_142A\nmovsxd rax, r13d\nmov rsi, rbx; src\nadd r13d, r12d\nlea rdx, [rax+rax*4]\nlea rdi, [rax+rdx*2]\nmov eax, r12d\nlea rdx, [rax+rax*4]\nadd rdi, rbp; dest\nlea rdx, [rax+rdx*2]; n\ncall _memcpy\nloc_142A:\nadd rsp, 8\nmov edx, r13d\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1440:\nmovsxd rax, edi\nadd rsi, 0Bh\nlea r13d, [rdi+1]\nlea rdx, [rax+rax*4]\nlea rax, [rax+rdx*2]\nmov rdx, [rsi-0Bh]\nadd rax, rbp\nmov [rax], rdx\nmov edx, [rsi-4]\nmov [rax+7], edx\ncmp r8, rsi\njz short loc_1401\nmov edi, r13d\njmp loc_13D8\nloc_1470:\nxor r13d, r13d\njmp short loc_1401", + "ida_pseudo": "char *__fastcall func0(_BYTE *a1, int a2, _BYTE *a3, int a4)\n{\n char *v8; // rbp\n _BYTE *v10; // rsi\n int v11; // edi\n _BYTE *v12; // r8\n _BYTE *v13; // rax\n int v14; // r13d\n char *v16; // rax\n\n v8 = (char *)malloc(11LL * (a2 + a4));\n if ( a2 <= 0 )\n {\n v14 = 0;\n }\n else\n {\n v10 = a1;\n v11 = 0;\n v12 = &a1[11 * a2];\n while ( a4 <= 0 )\n {\nLABEL_12:\n v10 += 11;\n v14 = v11 + 1;\n v16 = &v8[11 * v11];\n *(_QWORD *)v16 = *(_QWORD *)(v10 - 11);\n *(_DWORD *)(v16 + 7) = *((_DWORD *)v10 - 1);\n if ( v12 == v10 )\n goto LABEL_9;\n ++v11;\n }\n do\n {\n v13 = a3;\n while ( *v10 != *v13 )\n {\n v13 += 11;\n if ( v13 == &a3[11 * a4] )\n goto LABEL_12;\n }\n v10 += 11;\n }\n while ( v12 != v10 );\n v14 = v11;\n }\nLABEL_9:\n if ( a4 > 0 )\n memcpy(&v8[11 * v14], a3, 11LL * (unsigned int)a4);\n return v8;\n}", + "ida_strip_asm": "sub_1370:\nendbr64\npush r15\nlea eax, [rsi+rcx]\nmov r15, rdi\npush r14\ncdqe\nmov r14d, ecx\npush r13\nmov r13, rsi\npush r12\nmov r12, rcx\npush rbp\npush rbx\nmov rbx, rdx\nlea rdx, [rax+rax*4]\nlea rdi, [rax+rdx*2]; size\nsub rsp, 8\ncall _malloc\nmov rbp, rax\ntest r13d, r13d\njle loc_1470\nmovsxd r13, r13d\nmov rsi, r15\nxor edi, edi\nlea rax, [r13+r13*4+0]\nlea r8, [r13+rax*2+0]\nmovsxd rax, r12d\nlea rdx, [rax+rax*4]\nadd r8, r15\nlea rcx, [rax+rdx*2]\nadd rcx, rbx\nnop word ptr [rax+rax+00h]\nloc_13D8:\ntest r14d, r14d\njle short loc_1440\nloc_13DD:\nmovzx edx, byte ptr [rsi]\nmov rax, rbx\njmp short loc_13F1\nloc_13E8:\nadd rax, 0Bh\ncmp rax, rcx\njz short loc_1440\nloc_13F1:\ncmp dl, [rax]\njnz short loc_13E8\nadd rsi, 0Bh\ncmp r8, rsi\njnz short loc_13DD\nmov r13d, edi\nloc_1401:\ntest r12d, r12d\njle short loc_142A\nmovsxd rax, r13d\nmov rsi, rbx; src\nadd r13d, r12d\nlea rdx, [rax+rax*4]\nlea rdi, [rax+rdx*2]\nmov eax, r12d\nlea rdx, [rax+rax*4]\nadd rdi, rbp; dest\nlea rdx, [rax+rdx*2]; n\ncall _memcpy\nloc_142A:\nadd rsp, 8\nmov edx, r13d\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1440:\nmovsxd rax, edi\nadd rsi, 0Bh\nlea r13d, [rdi+1]\nlea rdx, [rax+rax*4]\nlea rax, [rax+rdx*2]\nmov rdx, [rsi-0Bh]\nadd rax, rbp\nmov [rax], rdx\nmov edx, [rsi-4]\nmov [rax+7], edx\ncmp r8, rsi\njz short loc_1401\nmov edi, r13d\njmp loc_13D8\nloc_1470:\nxor r13d, r13d\njmp short loc_1401", + "ida_strip_pseudo": "char *__fastcall sub_1370(_BYTE *a1, int a2, _BYTE *a3, int a4)\n{\n char *v8; // rbp\n _BYTE *v10; // rsi\n int v11; // edi\n _BYTE *v12; // r8\n _BYTE *v13; // rax\n int v14; // r13d\n char *v16; // rax\n\n v8 = (char *)malloc(11LL * (a2 + a4));\n if ( a2 <= 0 )\n {\n v14 = 0;\n }\n else\n {\n v10 = a1;\n v11 = 0;\n v12 = &a1[11 * a2];\n while ( a4 <= 0 )\n {\nLABEL_12:\n v10 += 11;\n v14 = v11 + 1;\n v16 = &v8[11 * v11];\n *(_QWORD *)v16 = *(_QWORD *)(v10 - 11);\n *(_DWORD *)(v16 + 7) = *((_DWORD *)v10 - 1);\n if ( v12 == v10 )\n goto LABEL_9;\n ++v11;\n }\n do\n {\n v13 = a3;\n while ( *v10 != *v13 )\n {\n v13 += 11;\n if ( v13 == &a3[11 * a4] )\n goto LABEL_12;\n }\n v10 += 11;\n }\n while ( v12 != v10 );\n v14 = v11;\n }\nLABEL_9:\n if ( a4 > 0 )\n memcpy(&v8[11 * v14], a3, 11LL * (unsigned int)a4);\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1370(uint8_t *a1, int a2, uint8_t *a3, int a4) {\n char *v8;\n uint8_t *v10;\n int v11;\n uint8_t *v12;\n uint8_t *v13;\n int v14;\n char *v16;\n v8 = (char *)malloc(11LL * (a2 + a4));\n if (a2 <= 0) {\n v14 = 0;\n } else {\n v10 = a1;\n v11 = 0;\n v12 = &a1[11 * a2];\n while (a4 <= 0) {\n LABEL_12:\n v10 += 11;\n v14 = v11 + 1;\n v16 = &v8[11 * v11];\n *(uint64_t *)v16 = *(uint64_t *)(v10 - 11);\n *(uint32_t *)(v16 + 7) = *((uint32_t *)v10 - 1);\n if (v12 == v10) goto LABEL_9;\n ++v11;\n }\n do {\n v13 = a3;\n while (*v10 != *v13) {\n v13 += 11;\n if (v13 == &a3[11 * a4]) goto LABEL_12;\n }\n v10 += 11;\n } while (v12 != v10);\n v14 = v11;\n }\nLABEL_9:\n if (a4 > 0) memcpy(&v8[11 * v14], a3, 11LL * (unsigned int)a4);\n return v8;\n}", + "ida_pseudo_norm": "char *func0(uint8_t *a1, int a2, uint8_t *a3, int a4) {\n char *v8;\n uint8_t *v10;\n int v11;\n uint8_t *v12;\n uint8_t *v13;\n int v14;\n char *v16;\n v8 = (char *)malloc(11LL * (a2 + a4));\n if (a2 <= 0) {\n v14 = 0;\n } else {\n v10 = a1;\n v11 = 0;\n v12 = &a1[11 * a2];\n while (a4 <= 0) {\n LABEL_12:\n v10 += 11;\n v14 = v11 + 1;\n v16 = &v8[11 * v11];\n *(uint64_t *)v16 = *(uint64_t *)(v10 - 11);\n *(uint32_t *)(v16 + 7) = *((uint32_t *)v10 - 1);\n if (v12 == v10) goto LABEL_9;\n ++v11;\n }\n do {\n v13 = a3;\n while (*v10 != *v13) {\n v13 += 11;\n if (v13 == &a3[11 * a4]) goto LABEL_12;\n }\n v10 += 11;\n } while (v12 != v10);\n v14 = v11;\n }\nLABEL_9:\n if (a4 > 0) memcpy(&v8[11 * v14], a3, 11LL * (unsigned int)a4);\n return v8;\n}" + }, + { + "index": 822, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char *p) {\n int len = strlen(p);\n bool hasLower = false;\n bool hasUpper = false;\n bool hasDigit = false;\n bool hasSpecial = false;\n if (len < 6 || len > 12) {\n return false;\n }\n for (int i = 0; i < len; i++) {\n if (islower(p[i])) {\n hasLower = true;\n } else if (isupper(p[i])) {\n hasUpper = true;\n } else if (isdigit(p[i])) {\n hasDigit = true;\n } else if (p[i] == '$' || p[i] == '#' || p[i] == '@') {\n hasSpecial = true;\n } else if (isspace(p[i])) {\n return false;\n }\n }\n return hasLower && hasUpper && hasDigit && hasSpecial;\n}", + "test": "int main() {\n\n assert(func0(\"password\") == false);\n\n assert(func0(\"Password@10\") == true);\n\n assert(func0(\"password@10\") == false);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov -0x18(%rbp),%rax\nmov %rax,%rdi\ncallq 1070 \nmov %eax,-0x4(%rbp)\nmovb $0x0,-0xc(%rbp)\nmovb $0x0,-0xb(%rbp)\nmovb $0x0,-0xa(%rbp)\nmovb $0x0,-0x9(%rbp)\ncmpl $0x5,-0x4(%rbp)\njle 11c4 \ncmpl $0xc,-0x4(%rbp)\njle 11ce \nmov $0x0,%eax\njmpq 1336 \nmovl $0x0,-0x8(%rbp)\njmpq 1303 \ncallq 1090 <__ctype_b_loc@plt>\nmov (%rax),%rax\nmov -0x8(%rbp),%edx\nmovslq %edx,%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rdx),%edx\nmovsbq %dl,%rdx\nadd %rdx,%rdx\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x200,%eax\ntest %eax,%eax\nje 1214 \nmovb $0x1,-0xc(%rbp)\njmpq 12ff \ncallq 1090 <__ctype_b_loc@plt>\nmov (%rax),%rax\nmov -0x8(%rbp),%edx\nmovslq %edx,%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rdx),%edx\nmovsbq %dl,%rdx\nadd %rdx,%rdx\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x100,%eax\ntest %eax,%eax\nje 124e \nmovb $0x1,-0xb(%rbp)\njmpq 12ff \ncallq 1090 <__ctype_b_loc@plt>\nmov (%rax),%rax\nmov -0x8(%rbp),%edx\nmovslq %edx,%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rdx),%edx\nmovsbq %dl,%rdx\nadd %rdx,%rdx\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x800,%eax\ntest %eax,%eax\nje 1285 \nmovb $0x1,-0xa(%rbp)\njmp 12ff \nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x24,%al\nje 12c1 \nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x23,%al\nje 12c1 \nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x40,%al\njne 12c7 \nmovb $0x1,-0x9(%rbp)\njmp 12ff \ncallq 1090 <__ctype_b_loc@plt>\nmov (%rax),%rax\nmov -0x8(%rbp),%edx\nmovslq %edx,%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rdx),%edx\nmovsbq %dl,%rdx\nadd %rdx,%rdx\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x2000,%eax\ntest %eax,%eax\nje 12ff \nmov $0x0,%eax\njmp 1336 \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x4(%rbp),%eax\njl 11da \ncmpb $0x0,-0xc(%rbp)\nje 132e \ncmpb $0x0,-0xb(%rbp)\nje 132e \ncmpb $0x0,-0xa(%rbp)\nje 132e \ncmpb $0x0,-0x9(%rbp)\nje 132e \nmov $0x1,%eax\njmp 1333 \nmov $0x0,%eax\nand $0x1,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_C], 0\nmov [rbp+var_B], 0\nmov [rbp+var_A], 0\nmov [rbp+var_9], 0\ncmp [rbp+var_4], 5\njle short loc_11C4\ncmp [rbp+var_4], 0Ch\njle short loc_11CE\nloc_11C4:\nmov eax, 0\njmp locret_1336\nloc_11CE:\nmov [rbp+var_8], 0\njmp loc_1303\nloc_11DA:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_8]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 200h\ntest eax, eax\njz short loc_1214\nmov [rbp+var_C], 1\njmp loc_12FF\nloc_1214:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_8]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 100h\ntest eax, eax\njz short loc_124E\nmov [rbp+var_B], 1\njmp loc_12FF\nloc_124E:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_8]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 800h\ntest eax, eax\njz short loc_1285\nmov [rbp+var_A], 1\njmp short loc_12FF\nloc_1285:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 24h ; '$'\njz short loc_12C1\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 23h ; '#'\njz short loc_12C1\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 40h ; '@'\njnz short loc_12C7\nloc_12C1:\nmov [rbp+var_9], 1\njmp short loc_12FF\nloc_12C7:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_8]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 2000h\ntest eax, eax\njz short loc_12FF\nmov eax, 0\njmp short locret_1336\nloc_12FF:\nadd [rbp+var_8], 1\nloc_1303:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njl loc_11DA\ncmp [rbp+var_C], 0\njz short loc_132E\ncmp [rbp+var_B], 0\njz short loc_132E\ncmp [rbp+var_A], 0\njz short loc_132E\ncmp [rbp+var_9], 0\njz short loc_132E\nmov eax, 1\njmp short loc_1333\nloc_132E:\nmov eax, 0\nloc_1333:\nand eax, 1\nlocret_1336:\nleave\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(const char *a1)\n{\n char v3; // [rsp+14h] [rbp-Ch]\n char v4; // [rsp+15h] [rbp-Bh]\n char v5; // [rsp+16h] [rbp-Ah]\n char v6; // [rsp+17h] [rbp-9h]\n int i; // [rsp+18h] [rbp-8h]\n int v8; // [rsp+1Ch] [rbp-4h]\n\n v8 = strlen(a1);\n v3 = 0;\n v4 = 0;\n v5 = 0;\n v6 = 0;\n if ( v8 <= 5 || v8 > 12 )\n return 0LL;\n for ( i = 0; i < v8; ++i )\n {\n if ( ((*__ctype_b_loc())[a1[i]] & 0x200) != 0 )\n {\n v3 = 1;\n }\n else if ( ((*__ctype_b_loc())[a1[i]] & 0x100) != 0 )\n {\n v4 = 1;\n }\n else if ( ((*__ctype_b_loc())[a1[i]] & 0x800) != 0 )\n {\n v5 = 1;\n }\n else if ( a1[i] == 36 || a1[i] == 35 || a1[i] == 64 )\n {\n v6 = 1;\n }\n else if ( ((*__ctype_b_loc())[a1[i]] & 0x2000) != 0 )\n {\n return 0LL;\n }\n }\n return v3 && v4 && v5 && v6;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_C], 0\nmov [rbp+var_B], 0\nmov [rbp+var_A], 0\nmov [rbp+var_9], 0\ncmp [rbp+var_4], 5\njle short loc_11C4\ncmp [rbp+var_4], 0Ch\njle short loc_11CE\nloc_11C4:\nmov eax, 0\njmp locret_1336\nloc_11CE:\nmov [rbp+var_8], 0\njmp loc_1303\nloc_11DA:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_8]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 200h\ntest eax, eax\njz short loc_1214\nmov [rbp+var_C], 1\njmp loc_12FF\nloc_1214:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_8]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 100h\ntest eax, eax\njz short loc_124E\nmov [rbp+var_B], 1\njmp loc_12FF\nloc_124E:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_8]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 800h\ntest eax, eax\njz short loc_1285\nmov [rbp+var_A], 1\njmp short loc_12FF\nloc_1285:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 24h ; '$'\njz short loc_12C1\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 23h ; '#'\njz short loc_12C1\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 40h ; '@'\njnz short loc_12C7\nloc_12C1:\nmov [rbp+var_9], 1\njmp short loc_12FF\nloc_12C7:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_8]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 2000h\ntest eax, eax\njz short loc_12FF\nmov eax, 0\njmp short locret_1336\nloc_12FF:\nadd [rbp+var_8], 1\nloc_1303:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njl loc_11DA\ncmp [rbp+var_C], 0\njz short loc_132E\ncmp [rbp+var_B], 0\njz short loc_132E\ncmp [rbp+var_A], 0\njz short loc_132E\ncmp [rbp+var_9], 0\njz short loc_132E\nmov eax, 1\njmp short loc_1333\nloc_132E:\nmov eax, 0\nloc_1333:\nand eax, 1\nlocret_1336:\nleave\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1189(const char *a1)\n{\n char v3; // [rsp+14h] [rbp-Ch]\n char v4; // [rsp+15h] [rbp-Bh]\n char v5; // [rsp+16h] [rbp-Ah]\n char v6; // [rsp+17h] [rbp-9h]\n int i; // [rsp+18h] [rbp-8h]\n int v8; // [rsp+1Ch] [rbp-4h]\n\n v8 = strlen(a1);\n v3 = 0;\n v4 = 0;\n v5 = 0;\n v6 = 0;\n if ( v8 <= 5 || v8 > 12 )\n return 0LL;\n for ( i = 0; i < v8; ++i )\n {\n if ( ((*__ctype_b_loc())[a1[i]] & 0x200) != 0 )\n {\n v3 = 1;\n }\n else if ( ((*__ctype_b_loc())[a1[i]] & 0x100) != 0 )\n {\n v4 = 1;\n }\n else if ( ((*__ctype_b_loc())[a1[i]] & 0x800) != 0 )\n {\n v5 = 1;\n }\n else if ( a1[i] == 36 || a1[i] == 35 || a1[i] == 64 )\n {\n v6 = 1;\n }\n else if ( ((*__ctype_b_loc())[a1[i]] & 0x2000) != 0 )\n {\n return 0LL;\n }\n }\n return v3 && v4 && v5 && v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1189(const char *a1) {\n char v3;\n char v4;\n char v5;\n char v6;\n int i;\n int v8;\n v8 = strlen(a1);\n v3 = 0;\n v4 = 0;\n v5 = 0;\n v6 = 0;\n if (v8 <= 5 || v8 > 12) return 0LL;\n for (i = 0; i < v8; ++i) {\n if (((*__ctype_b_loc())[a1[i]] & 512) != 0) {\n v3 = 1;\n } else if (((*__ctype_b_loc())[a1[i]] & 256) != 0) {\n v4 = 1;\n } else if (((*__ctype_b_loc())[a1[i]] & 2048) != 0) {\n v5 = 1;\n } else if (a1[i] == 36 || a1[i] == 35 || a1[i] == 64) {\n v6 = 1;\n } else if (((*__ctype_b_loc())[a1[i]] & 8192) != 0) {\n return 0LL;\n }\n }\n return v3 && v4 && v5 && v6;\n}", + "ida_pseudo_norm": "uint8_t func0(const char *a1) {\n char v3;\n char v4;\n char v5;\n char v6;\n int i;\n int v8;\n v8 = strlen(a1);\n v3 = 0;\n v4 = 0;\n v5 = 0;\n v6 = 0;\n if (v8 <= 5 || v8 > 12) return 0LL;\n for (i = 0; i < v8; ++i) {\n if (((*__ctype_b_loc())[a1[i]] & 512) != 0) {\n v3 = 1;\n } else if (((*__ctype_b_loc())[a1[i]] & 256) != 0) {\n v4 = 1;\n } else if (((*__ctype_b_loc())[a1[i]] & 2048) != 0) {\n v5 = 1;\n } else if (a1[i] == 36 || a1[i] == 35 || a1[i] == 64) {\n v6 = 1;\n } else if (((*__ctype_b_loc())[a1[i]] & 8192) != 0) {\n return 0LL;\n }\n }\n return v3 && v4 && v5 && v6;\n}" + }, + { + "index": 822, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char *p) {\n int len = strlen(p);\n bool hasLower = false;\n bool hasUpper = false;\n bool hasDigit = false;\n bool hasSpecial = false;\n if (len < 6 || len > 12) {\n return false;\n }\n for (int i = 0; i < len; i++) {\n if (islower(p[i])) {\n hasLower = true;\n } else if (isupper(p[i])) {\n hasUpper = true;\n } else if (isdigit(p[i])) {\n hasDigit = true;\n } else if (p[i] == '$' || p[i] == '#' || p[i] == '@') {\n hasSpecial = true;\n } else if (isspace(p[i])) {\n return false;\n }\n }\n return hasLower && hasUpper && hasDigit && hasSpecial;\n}", + "test": "int main() {\n\n assert(func0(\"password\") == false);\n\n assert(func0(\"Password@10\") == true);\n\n assert(func0(\"password@10\") == false);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nlea -0x7(%rcx),%edx\ncmp $0x6,%edx\nja 1235 \nlea -0x1(%rcx),%rbp\ntest %ebp,%ebp\njle 123a \ncallq 1070 <__ctype_b_loc@plt>\nmov (%rax),%rdi\nmov %rbx,%rdx\nlea -0x1(%rbp),%eax\nlea 0x1(%rbx,%rax,1),%r8\nmov $0x0,%r12d\nmov $0x0,%ebx\nmov $0x0,%r11d\nmov $0x0,%r10d\nmov $0x1,%r9d\njmp 11db \nmov %r9d,%r10d\nadd $0x1,%rdx\ncmp %rdx,%r8\nje 1222 \nmovzbl (%rdx),%esi\nmovsbq %sil,%rax\nmovzwl (%rdi,%rax,2),%ecx\ntest $0x2,%ch\njne 11cf \ntest $0x1,%ch\njne 1213 \ntest $0x8,%ch\njne 1218 \nlea -0x23(%rsi),%ebp\ncmp $0x1,%bpl\nsetbe %al\ncmp $0x40,%sil\nsete %sil\nor %sil,%al\njne 121d \ntest $0x20,%ch\nje 11d2 \njmp 1235 \nmov %r9d,%r11d\njmp 11d2 \nmov %r9d,%ebx\njmp 11d2 \nmov %eax,%r12d\njmp 11d2 \ntest %r10b,%r10b\nje 1241 \ntest %r11b,%r11b\nje 1241 \nand %r12d,%ebx\nmovzbl %bl,%eax\nand $0x1,%eax\npop %rbx\npop %rbp\npop %r12\nretq\nmov $0x0,%eax\njmp 1232 \nmov $0x0,%eax\njmp 1232 \n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbp, rdi\ncall _strlen\nmov rbx, rax\nlea edx, [rax-6]\nmov eax, 0\ncmp edx, 6\nja loc_1240\ncall ___ctype_b_loc\nmov rdi, [rax]\nmov edx, 0\nmov r12d, 0\nmov r11d, 0\nmov r10d, 0\nmov r9d, 0\nmov r8d, 1\njmp short loc_11E5\nloc_11DA:\nmov r9d, r8d\nloc_11DD:\nadd rdx, 1\ncmp ebx, edx\njle short loc_122C\nloc_11E5:\nmovzx esi, byte ptr [rbp+rdx+0]\nmovsx rcx, sil\nmovzx ecx, word ptr [rdi+rcx*2]\ntest ch, 2\njnz short loc_11DA\ntest ch, 1\njnz short loc_121D\ntest ch, 8\njnz short loc_1222\nlea eax, [rsi-23h]\ncmp al, 1\nsetbe al\ncmp sil, 40h ; '@'\nsetz sil\nor al, sil\njnz short loc_1227\ntest ch, 20h\njz short loc_11DD\njmp short loc_1240\nloc_121D:\nmov r10d, r8d\njmp short loc_11DD\nloc_1222:\nmov r11d, r8d\njmp short loc_11DD\nloc_1227:\nmov r12d, eax\njmp short loc_11DD\nloc_122C:\ntest r9b, r9b\njz short loc_1245\ntest r10b, r10b\njz short loc_1245\nand r11d, r12d\nmovzx eax, r11b\nloc_123D:\nand eax, 1\nloc_1240:\npop rbx\npop rbp\npop r12\nretn\nloc_1245:\nmov eax, 0\njmp short loc_123D", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n int v2; // ebx\n __int64 result; // rax\n const unsigned __int16 *v4; // rdi\n __int64 v5; // rdx\n bool v6; // r12\n char v7; // r11\n char v8; // r10\n char v9; // r9\n int v10; // esi\n unsigned __int16 v11; // cx\n char v12; // al\n\n v2 = strlen(a1);\n result = 0LL;\n if ( (unsigned int)(v2 - 6) <= 6 )\n {\n v4 = *__ctype_b_loc();\n v5 = 0LL;\n v6 = 0;\n v7 = 0;\n v8 = 0;\n v9 = 0;\n do\n {\n v10 = (unsigned __int8)a1[v5];\n v11 = v4[(char)v10];\n if ( (v11 & 0x200) != 0 )\n {\n v9 = 1;\n }\n else if ( (v11 & 0x100) != 0 )\n {\n v8 = 1;\n }\n else if ( (v11 & 0x800) != 0 )\n {\n v7 = 1;\n }\n else\n {\n result = (unsigned int)(v10 - 35);\n LOBYTE(result) = (_BYTE)v10 == 64 || (unsigned __int8)(v10 - 35) <= 1u;\n if ( (_BYTE)result )\n {\n v6 = (_BYTE)v10 == 64 || (unsigned __int8)(v10 - 35) <= 1u;\n }\n else if ( (v11 & 0x2000) != 0 )\n {\n return result;\n }\n }\n ++v5;\n }\n while ( v2 > (int)v5 );\n if ( v9 && v8 )\n v12 = v6 & v7;\n else\n v12 = 0;\n return v12 & 1;\n }\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbp, rdi\ncall _strlen\nmov rbx, rax\nlea edx, [rax-6]\nmov eax, 0\ncmp edx, 6\nja loc_1240\ncall ___ctype_b_loc\nmov rdi, [rax]\nmov edx, 0\nmov r12d, 0\nmov r11d, 0\nmov r10d, 0\nmov r9d, 0\nmov r8d, 1\njmp short loc_11E5\nloc_11DA:\nmov r9d, r8d\nloc_11DD:\nadd rdx, 1\ncmp ebx, edx\njle short loc_122C\nloc_11E5:\nmovzx esi, byte ptr [rbp+rdx+0]\nmovsx rcx, sil\nmovzx ecx, word ptr [rdi+rcx*2]\ntest ch, 2\njnz short loc_11DA\ntest ch, 1\njnz short loc_121D\ntest ch, 8\njnz short loc_1222\nlea eax, [rsi-23h]\ncmp al, 1\nsetbe al\ncmp sil, 40h ; '@'\nsetz sil\nor al, sil\njnz short loc_1227\ntest ch, 20h\njz short loc_11DD\njmp short loc_1240\nloc_121D:\nmov r10d, r8d\njmp short loc_11DD\nloc_1222:\nmov r11d, r8d\njmp short loc_11DD\nloc_1227:\nmov r12d, eax\njmp short loc_11DD\nloc_122C:\ntest r9b, r9b\njz short loc_1245\ntest r10b, r10b\njz short loc_1245\nand r11d, r12d\nmovzx eax, r11b\nloc_123D:\nand eax, 1\nloc_1240:\npop rbx\npop rbp\npop r12\nretn\nloc_1245:\nmov eax, 0\njmp short loc_123D", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(const char *a1)\n{\n int v2; // ebx\n __int64 result; // rax\n const unsigned __int16 *v4; // rdi\n __int64 v5; // rdx\n bool v6; // r12\n char v7; // r11\n char v8; // r10\n char v9; // r9\n int v10; // esi\n unsigned __int16 v11; // cx\n char v12; // al\n\n v2 = strlen(a1);\n result = 0LL;\n if ( (unsigned int)(v2 - 6) <= 6 )\n {\n v4 = *__ctype_b_loc();\n v5 = 0LL;\n v6 = 0;\n v7 = 0;\n v8 = 0;\n v9 = 0;\n do\n {\n v10 = (unsigned __int8)a1[v5];\n v11 = v4[(char)v10];\n if ( (v11 & 0x200) != 0 )\n {\n v9 = 1;\n }\n else if ( (v11 & 0x100) != 0 )\n {\n v8 = 1;\n }\n else if ( (v11 & 0x800) != 0 )\n {\n v7 = 1;\n }\n else\n {\n result = (unsigned int)(v10 - 35);\n LOBYTE(result) = (_BYTE)v10 == 64 || (unsigned __int8)(v10 - 35) <= 1u;\n if ( (_BYTE)result )\n {\n v6 = (_BYTE)v10 == 64 || (unsigned __int8)(v10 - 35) <= 1u;\n }\n else if ( (v11 & 0x2000) != 0 )\n {\n return result;\n }\n }\n ++v5;\n }\n while ( v2 > (int)v5 );\n if ( v9 && v8 )\n v12 = v6 & v7;\n else\n v12 = 0;\n return v12 & 1;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(const char *a1) {\n int v2;\n long long result;\n const unsigned short *v4;\n long long v5;\n bool v6;\n char v7;\n char v8;\n char v9;\n int v10;\n unsigned short v11;\n char v12;\n v2 = strlen(a1);\n result = 0LL;\n if ((unsigned int)(v2 - 6) <= 6) {\n v4 = *__ctype_b_loc();\n v5 = 0LL;\n v6 = 0;\n v7 = 0;\n v8 = 0;\n v9 = 0;\n do {\n v10 = (unsigned char)a1[v5];\n v11 = v4[(char)v10];\n if ((v11 & 512) != 0) {\n v9 = 1;\n } else if ((v11 & 256) != 0) {\n v8 = 1;\n } else if ((v11 & 2048) != 0) {\n v7 = 1;\n } else {\n result = (unsigned int)(v10 - 35);\n LOBYTE(result) = (uint8_t)v10 == 64 || (unsigned char)(v10 - 35) <= 1u;\n if ((uint8_t)result) {\n v6 = (uint8_t)v10 == 64 || (unsigned char)(v10 - 35) <= 1u;\n } else if ((v11 & 8192) != 0) {\n return result;\n }\n }\n ++v5;\n } while (v2 > (int)v5);\n if (v9 && v8)\n v12 = v6 & v7;\n else\n v12 = 0;\n return v12 & 1;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n int v2;\n long long result;\n const unsigned short *v4;\n long long v5;\n bool v6;\n char v7;\n char v8;\n char v9;\n int v10;\n unsigned short v11;\n char v12;\n v2 = strlen(a1);\n result = 0LL;\n if ((unsigned int)(v2 - 6) <= 6) {\n v4 = *__ctype_b_loc();\n v5 = 0LL;\n v6 = 0;\n v7 = 0;\n v8 = 0;\n v9 = 0;\n do {\n v10 = (unsigned char)a1[v5];\n v11 = v4[(char)v10];\n if ((v11 & 512) != 0) {\n v9 = 1;\n } else if ((v11 & 256) != 0) {\n v8 = 1;\n } else if ((v11 & 2048) != 0) {\n v7 = 1;\n } else {\n result = (unsigned int)(v10 - 35);\n LOBYTE(result) = (uint8_t)v10 == 64 || (unsigned char)(v10 - 35) <= 1u;\n if ((uint8_t)result) {\n v6 = (uint8_t)v10 == 64 || (unsigned char)(v10 - 35) <= 1u;\n } else if ((v11 & 8192) != 0) {\n return result;\n }\n }\n ++v5;\n } while (v2 > (int)v5);\n if (v9 && v8)\n v12 = v6 & v7;\n else\n v12 = 0;\n return v12 & 1;\n }\n return result;\n}" + }, + { + "index": 822, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char *p) {\n int len = strlen(p);\n bool hasLower = false;\n bool hasUpper = false;\n bool hasDigit = false;\n bool hasSpecial = false;\n if (len < 6 || len > 12) {\n return false;\n }\n for (int i = 0; i < len; i++) {\n if (islower(p[i])) {\n hasLower = true;\n } else if (isupper(p[i])) {\n hasUpper = true;\n } else if (isdigit(p[i])) {\n hasDigit = true;\n } else if (p[i] == '$' || p[i] == '#' || p[i] == '@') {\n hasSpecial = true;\n } else if (isspace(p[i])) {\n return false;\n }\n }\n return hasLower && hasUpper && hasDigit && hasSpecial;\n}", + "test": "int main() {\n\n assert(func0(\"password\") == false);\n\n assert(func0(\"Password@10\") == true);\n\n assert(func0(\"password@10\") == false);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rdi,%rbp\npush %rbx\nsub $0x8,%rsp\ncallq 1070 \nlea -0x6(%rax),%edx\nmov %rax,%rbx\nxor %eax,%eax\ncmp $0x6,%edx\nja 12de \ntest %ebx,%ebx\njle 12de \ncallq 1090 <__ctype_b_loc@plt>\nmov %rbp,%rdi\nxor %r10d,%r10d\nxor %r9d,%r9d\nmov (%rax),%r11\nlea -0x1(%rbx),%eax\nxor %r8d,%r8d\nxor %ebx,%ebx\nlea 0x1(%rbp,%rax,1),%rsi\njmp 12b1 \nnopl 0x0(%rax,%rax,1)\ntest $0x1,%dh\njne 12e8 \ntest $0x8,%dh\njne 12f0 \nlea -0x23(%rax),%eax\ncmp $0x1,%al\nsetbe %al\ncmp $0x40,%cl\nsete %cl\nor %cl,%al\njne 1300 \nand $0x20,%dh\njne 12de \nnopl 0x0(%rax)\nadd $0x1,%rdi\ncmp %rdi,%rsi\nje 12d1 \nmovsbq (%rdi),%rax\nmovzwl (%r11,%rax,2),%edx\nmov %rax,%rcx\ntest $0x2,%dh\nje 1280 \nadd $0x1,%rdi\nmov $0x1,%r8d\ncmp %rdi,%rsi\njne 12b1 \nmov %r8d,%eax\nand %ebx,%r10d\nand %r9b,%al\ncmovne %r10d,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopl (%rax)\nmov $0x1,%r9d\njmp 12a8 \nmov $0x1,%r10d\njmp 12a8 \nnopl 0x0(%rax,%rax,1)\nmov %eax,%ebx\njmp 12a8 \nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 8\ncall _strlen\nlea edx, [rax-6]\nmov rbx, rax\nxor eax, eax\ncmp edx, 6\nja short loc_12CD\ncall ___ctype_b_loc\nxor edx, edx\nxor r11d, r11d\nxor r10d, r10d\nmov rdi, [rax]\nxor r9d, r9d\nxor r8d, r8d\njmp short loc_12A0\nloc_1270:\ntest ch, 1\njnz short loc_12D8\ntest ch, 8\njnz short loc_12E0\nlea eax, [rsi-23h]\ncmp al, 1\nsetbe al\ncmp sil, 40h ; '@'\nsetz sil\nor al, sil\njnz short loc_12F0\nand ch, 20h\njnz short loc_12CD\nnop dword ptr [rax+00h]\nloc_1298:\nadd rdx, 1\ncmp ebx, edx\njle short loc_12C0\nloc_12A0:\nmovsx rcx, byte ptr [rbp+rdx+0]\nmov rsi, rcx\nmovzx ecx, word ptr [rdi+rcx*2]\ntest ch, 2\njz short loc_1270\nadd rdx, 1\nmov r8d, 1\ncmp ebx, edx\njg short loc_12A0\nloc_12C0:\nmov eax, r8d\nand r10d, r11d\nand al, r9b\ncmovnz eax, r10d\nloc_12CD:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_12D8:\nmov r9d, 1\njmp short loc_1298\nloc_12E0:\nmov r10d, 1\njmp short loc_1298\nloc_12F0:\nmov r11d, eax\njmp short loc_1298", + "ida_pseudo": "char __fastcall func0(const char *a1)\n{\n int v2; // eax\n unsigned int v3; // edx\n int v4; // ebx\n char result; // al\n const unsigned __int16 **v6; // rax\n __int64 v7; // rdx\n bool v8; // r11\n char v9; // r10\n const unsigned __int16 *v10; // rdi\n char v11; // r9\n char v12; // r8\n __int64 v13; // rsi\n unsigned __int16 v14; // cx\n char v15; // r10\n\n v2 = strlen(a1);\n v3 = v2 - 6;\n v4 = v2;\n result = 0;\n if ( v3 <= 6 )\n {\n v6 = __ctype_b_loc();\n v7 = 0LL;\n v8 = 0;\n v9 = 0;\n v10 = *v6;\n v11 = 0;\n v12 = 0;\n do\n {\n while ( 1 )\n {\n v13 = a1[v7];\n v14 = v10[v13];\n if ( (v14 & 0x200) == 0 )\n break;\n ++v7;\n v12 = 1;\n if ( v4 <= (int)v7 )\n goto LABEL_10;\n }\n if ( (v14 & 0x100) != 0 )\n {\n v11 = 1;\n }\n else if ( (v14 & 0x800) != 0 )\n {\n v9 = 1;\n }\n else\n {\n result = (_BYTE)v13 == 64 || (unsigned __int8)(v13 - 35) <= 1u;\n if ( result )\n {\n v8 = (_BYTE)v13 == 64 || (unsigned __int8)(v13 - 35) <= 1u;\n }\n else if ( (v14 & 0x2000) != 0 )\n {\n return result;\n }\n }\n ++v7;\n }\n while ( v4 > (int)v7 );\nLABEL_10:\n v15 = v8 & v9;\n result = v11 & v12;\n if ( ((unsigned __int8)v11 & (unsigned __int8)v12) != 0 )\n return v15;\n }\n return result;\n}", + "ida_strip_asm": "sub_1230:\nendbr64\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 8\ncall _strlen\nlea edx, [rax-6]\nmov rbx, rax\nxor eax, eax\ncmp edx, 6\nja short loc_12CD\ncall ___ctype_b_loc\nxor edx, edx\nxor r11d, r11d\nxor r10d, r10d\nmov rdi, [rax]\nxor r9d, r9d\nxor r8d, r8d\njmp short loc_12A0\nloc_1270:\ntest ch, 1\njnz short loc_12D8\ntest ch, 8\njnz short loc_12E0\nlea eax, [rsi-23h]\ncmp al, 1\nsetbe al\ncmp sil, 40h ; '@'\nsetz sil\nor al, sil\njnz short loc_12F0\nand ch, 20h\njnz short loc_12CD\nnop dword ptr [rax+00h]\nloc_1298:\nadd rdx, 1\ncmp ebx, edx\njle short loc_12C0\nloc_12A0:\nmovsx rcx, byte ptr [rbp+rdx+0]\nmov rsi, rcx\nmovzx ecx, word ptr [rdi+rcx*2]\ntest ch, 2\njz short loc_1270\nadd rdx, 1\nmov r8d, 1\ncmp ebx, edx\njg short loc_12A0\nloc_12C0:\nmov eax, r8d\nand r10d, r11d\nand al, r9b\ncmovnz eax, r10d\nloc_12CD:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_12D8:\nmov r9d, 1\njmp short loc_1298\nloc_12E0:\nmov r10d, 1\njmp short loc_1298\nloc_12F0:\nmov r11d, eax\njmp short loc_1298", + "ida_strip_pseudo": "char __fastcall sub_1230(const char *a1)\n{\n int v2; // eax\n unsigned int v3; // edx\n int v4; // ebx\n char result; // al\n const unsigned __int16 **v6; // rax\n __int64 v7; // rdx\n bool v8; // r11\n char v9; // r10\n const unsigned __int16 *v10; // rdi\n char v11; // r9\n char v12; // r8\n __int64 v13; // rsi\n unsigned __int16 v14; // cx\n char v15; // r10\n\n v2 = strlen(a1);\n v3 = v2 - 6;\n v4 = v2;\n result = 0;\n if ( v3 <= 6 )\n {\n v6 = __ctype_b_loc();\n v7 = 0LL;\n v8 = 0;\n v9 = 0;\n v10 = *v6;\n v11 = 0;\n v12 = 0;\n do\n {\n while ( 1 )\n {\n v13 = a1[v7];\n v14 = v10[v13];\n if ( (v14 & 0x200) == 0 )\n break;\n ++v7;\n v12 = 1;\n if ( v4 <= (int)v7 )\n goto LABEL_10;\n }\n if ( (v14 & 0x100) != 0 )\n {\n v11 = 1;\n }\n else if ( (v14 & 0x800) != 0 )\n {\n v9 = 1;\n }\n else\n {\n result = (_BYTE)v13 == 64 || (unsigned __int8)(v13 - 35) <= 1u;\n if ( result )\n {\n v8 = (_BYTE)v13 == 64 || (unsigned __int8)(v13 - 35) <= 1u;\n }\n else if ( (v14 & 0x2000) != 0 )\n {\n return result;\n }\n }\n ++v7;\n }\n while ( v4 > (int)v7 );\nLABEL_10:\n v15 = v8 & v9;\n result = v11 & v12;\n if ( ((unsigned __int8)v11 & (unsigned __int8)v12) != 0 )\n return v15;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char sub_1230(const char *a1) {\n int v2;\n unsigned int v3;\n int v4;\n char result;\n const unsigned short **v6;\n long long v7;\n bool v8;\n char v9;\n const unsigned short *v10;\n char v11;\n char v12;\n long long v13;\n unsigned short v14;\n char v15;\n v2 = strlen(a1);\n v3 = v2 - 6;\n v4 = v2;\n result = 0;\n if (v3 <= 6) {\n v6 = __ctype_b_loc();\n v7 = 0LL;\n v8 = 0;\n v9 = 0;\n v10 = *v6;\n v11 = 0;\n v12 = 0;\n do {\n while (1) {\n v13 = a1[v7];\n v14 = v10[v13];\n if ((v14 & 512) == 0) break;\n ++v7;\n v12 = 1;\n if (v4 <= (int)v7) goto LABEL_10;\n }\n if ((v14 & 256) != 0) {\n v11 = 1;\n } else if ((v14 & 2048) != 0) {\n v9 = 1;\n } else {\n result = (uint8_t)v13 == 64 || (unsigned char)(v13 - 35) <= 1u;\n if (result) {\n v8 = (uint8_t)v13 == 64 || (unsigned char)(v13 - 35) <= 1u;\n } else if ((v14 & 8192) != 0) {\n return result;\n }\n }\n ++v7;\n } while (v4 > (int)v7);\n LABEL_10:\n v15 = v8 & v9;\n result = v11 & v12;\n if (((unsigned char)v11 & (unsigned char)v12) != 0) return v15;\n }\n return result;\n}", + "ida_pseudo_norm": "char func0(const char *a1) {\n int v2;\n unsigned int v3;\n int v4;\n char result;\n const unsigned short **v6;\n long long v7;\n bool v8;\n char v9;\n const unsigned short *v10;\n char v11;\n char v12;\n long long v13;\n unsigned short v14;\n char v15;\n v2 = strlen(a1);\n v3 = v2 - 6;\n v4 = v2;\n result = 0;\n if (v3 <= 6) {\n v6 = __ctype_b_loc();\n v7 = 0LL;\n v8 = 0;\n v9 = 0;\n v10 = *v6;\n v11 = 0;\n v12 = 0;\n do {\n while (1) {\n v13 = a1[v7];\n v14 = v10[v13];\n if ((v14 & 512) == 0) break;\n ++v7;\n v12 = 1;\n if (v4 <= (int)v7) goto LABEL_10;\n }\n if ((v14 & 256) != 0) {\n v11 = 1;\n } else if ((v14 & 2048) != 0) {\n v9 = 1;\n } else {\n result = (uint8_t)v13 == 64 || (unsigned char)(v13 - 35) <= 1u;\n if (result) {\n v8 = (uint8_t)v13 == 64 || (unsigned char)(v13 - 35) <= 1u;\n } else if ((v14 & 8192) != 0) {\n return result;\n }\n }\n ++v7;\n } while (v4 > (int)v7);\n LABEL_10:\n v15 = v8 & v9;\n result = v11 & v12;\n if (((unsigned char)v11 & (unsigned char)v12) != 0) return v15;\n }\n return result;\n}" + }, + { + "index": 822, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char *p) {\n int len = strlen(p);\n bool hasLower = false;\n bool hasUpper = false;\n bool hasDigit = false;\n bool hasSpecial = false;\n if (len < 6 || len > 12) {\n return false;\n }\n for (int i = 0; i < len; i++) {\n if (islower(p[i])) {\n hasLower = true;\n } else if (isupper(p[i])) {\n hasUpper = true;\n } else if (isdigit(p[i])) {\n hasDigit = true;\n } else if (p[i] == '$' || p[i] == '#' || p[i] == '@') {\n hasSpecial = true;\n } else if (isspace(p[i])) {\n return false;\n }\n }\n return hasLower && hasUpper && hasDigit && hasSpecial;\n}", + "test": "int main() {\n\n assert(func0(\"password\") == false);\n\n assert(func0(\"Password@10\") == true);\n\n assert(func0(\"password@10\") == false);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rdi,%rbp\npush %rbx\nsub $0x8,%rsp\ncallq 1070 \nlea -0x6(%rax),%edx\nmov %rax,%rbx\nxor %eax,%eax\ncmp $0x6,%edx\nja 12de \ntest %ebx,%ebx\njle 12de \ncallq 1090 <__ctype_b_loc@plt>\nmov %rbp,%rdi\nxor %r10d,%r10d\nxor %r9d,%r9d\nmov (%rax),%r11\nlea -0x1(%rbx),%eax\nxor %r8d,%r8d\nxor %ebx,%ebx\nlea 0x1(%rbp,%rax,1),%rsi\njmp 12b1 \nnopl 0x0(%rax,%rax,1)\ntest $0x1,%dh\njne 12e8 \ntest $0x8,%dh\njne 12f0 \nlea -0x23(%rax),%eax\ncmp $0x1,%al\nsetbe %al\ncmp $0x40,%cl\nsete %cl\nor %cl,%al\njne 1300 \nand $0x20,%dh\njne 12de \nnopl 0x0(%rax)\nadd $0x1,%rdi\ncmp %rdi,%rsi\nje 12d1 \nmovsbq (%rdi),%rax\nmovzwl (%r11,%rax,2),%edx\nmov %rax,%rcx\ntest $0x2,%dh\nje 1280 \nadd $0x1,%rdi\nmov $0x1,%r8d\ncmp %rdi,%rsi\njne 12b1 \nmov %r8d,%eax\nand %ebx,%r10d\nand %r9b,%al\ncmovne %r10d,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopl (%rax)\nmov $0x1,%r9d\njmp 12a8 \nmov $0x1,%r10d\njmp 12a8 \nnopl 0x0(%rax,%rax,1)\nmov %eax,%ebx\njmp 12a8 \nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 8\ncall _strlen\nlea edx, [rax-6]\nmov rbx, rax\nxor eax, eax\ncmp edx, 6\nja short loc_12CD\ncall ___ctype_b_loc\nxor edx, edx\nxor r11d, r11d\nxor r10d, r10d\nmov rdi, [rax]\nxor r9d, r9d\nxor r8d, r8d\njmp short loc_12A0\nloc_1270:\ntest ch, 1\njnz short loc_12D8\ntest ch, 8\njnz short loc_12E0\nlea eax, [rsi-23h]\ncmp al, 1\nsetbe al\ncmp sil, 40h ; '@'\nsetz sil\nor al, sil\njnz short loc_12F0\nand ch, 20h\njnz short loc_12CD\nnop dword ptr [rax+00h]\nloc_1298:\nadd rdx, 1\ncmp ebx, edx\njle short loc_12C0\nloc_12A0:\nmovsx rcx, byte ptr [rbp+rdx+0]\nmov rsi, rcx\nmovzx ecx, word ptr [rdi+rcx*2]\ntest ch, 2\njz short loc_1270\nadd rdx, 1\nmov r8d, 1\ncmp ebx, edx\njg short loc_12A0\nloc_12C0:\nmov eax, r8d\nand r10d, r11d\nand al, r9b\ncmovnz eax, r10d\nloc_12CD:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_12D8:\nmov r9d, 1\njmp short loc_1298\nloc_12E0:\nmov r10d, 1\njmp short loc_1298\nloc_12F0:\nmov r11d, eax\njmp short loc_1298", + "ida_pseudo": "char __fastcall func0(const char *a1)\n{\n int v2; // eax\n unsigned int v3; // edx\n int v4; // ebx\n char result; // al\n const unsigned __int16 **v6; // rax\n __int64 v7; // rdx\n bool v8; // r11\n char v9; // r10\n const unsigned __int16 *v10; // rdi\n char v11; // r9\n char v12; // r8\n __int64 v13; // rsi\n unsigned __int16 v14; // cx\n char v15; // r10\n\n v2 = strlen(a1);\n v3 = v2 - 6;\n v4 = v2;\n result = 0;\n if ( v3 <= 6 )\n {\n v6 = __ctype_b_loc();\n v7 = 0LL;\n v8 = 0;\n v9 = 0;\n v10 = *v6;\n v11 = 0;\n v12 = 0;\n do\n {\n while ( 1 )\n {\n v13 = a1[v7];\n v14 = v10[v13];\n if ( (v14 & 0x200) == 0 )\n break;\n ++v7;\n v12 = 1;\n if ( v4 <= (int)v7 )\n goto LABEL_10;\n }\n if ( (v14 & 0x100) != 0 )\n {\n v11 = 1;\n }\n else if ( (v14 & 0x800) != 0 )\n {\n v9 = 1;\n }\n else\n {\n result = (_BYTE)v13 == 64 || (unsigned __int8)(v13 - 35) <= 1u;\n if ( result )\n {\n v8 = (_BYTE)v13 == 64 || (unsigned __int8)(v13 - 35) <= 1u;\n }\n else if ( (v14 & 0x2000) != 0 )\n {\n return result;\n }\n }\n ++v7;\n }\n while ( v4 > (int)v7 );\nLABEL_10:\n v15 = v8 & v9;\n result = v11 & v12;\n if ( ((unsigned __int8)v11 & (unsigned __int8)v12) != 0 )\n return v15;\n }\n return result;\n}", + "ida_strip_asm": "sub_1230:\nendbr64\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 8\ncall _strlen\nlea edx, [rax-6]\nmov rbx, rax\nxor eax, eax\ncmp edx, 6\nja short loc_12CD\ncall ___ctype_b_loc\nxor edx, edx\nxor r11d, r11d\nxor r10d, r10d\nmov rdi, [rax]\nxor r9d, r9d\nxor r8d, r8d\njmp short loc_12A0\nloc_1270:\ntest ch, 1\njnz short loc_12D8\ntest ch, 8\njnz short loc_12E0\nlea eax, [rsi-23h]\ncmp al, 1\nsetbe al\ncmp sil, 40h ; '@'\nsetz sil\nor al, sil\njnz short loc_12F0\nand ch, 20h\njnz short loc_12CD\nnop dword ptr [rax+00h]\nloc_1298:\nadd rdx, 1\ncmp ebx, edx\njle short loc_12C0\nloc_12A0:\nmovsx rcx, byte ptr [rbp+rdx+0]\nmov rsi, rcx\nmovzx ecx, word ptr [rdi+rcx*2]\ntest ch, 2\njz short loc_1270\nadd rdx, 1\nmov r8d, 1\ncmp ebx, edx\njg short loc_12A0\nloc_12C0:\nmov eax, r8d\nand r10d, r11d\nand al, r9b\ncmovnz eax, r10d\nloc_12CD:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_12D8:\nmov r9d, 1\njmp short loc_1298\nloc_12E0:\nmov r10d, 1\njmp short loc_1298\nloc_12F0:\nmov r11d, eax\njmp short loc_1298", + "ida_strip_pseudo": "char __fastcall sub_1230(const char *a1)\n{\n int v2; // eax\n unsigned int v3; // edx\n int v4; // ebx\n char result; // al\n const unsigned __int16 **v6; // rax\n __int64 v7; // rdx\n bool v8; // r11\n char v9; // r10\n const unsigned __int16 *v10; // rdi\n char v11; // r9\n char v12; // r8\n __int64 v13; // rsi\n unsigned __int16 v14; // cx\n char v15; // r10\n\n v2 = strlen(a1);\n v3 = v2 - 6;\n v4 = v2;\n result = 0;\n if ( v3 <= 6 )\n {\n v6 = __ctype_b_loc();\n v7 = 0LL;\n v8 = 0;\n v9 = 0;\n v10 = *v6;\n v11 = 0;\n v12 = 0;\n do\n {\n while ( 1 )\n {\n v13 = a1[v7];\n v14 = v10[v13];\n if ( (v14 & 0x200) == 0 )\n break;\n ++v7;\n v12 = 1;\n if ( v4 <= (int)v7 )\n goto LABEL_10;\n }\n if ( (v14 & 0x100) != 0 )\n {\n v11 = 1;\n }\n else if ( (v14 & 0x800) != 0 )\n {\n v9 = 1;\n }\n else\n {\n result = (_BYTE)v13 == 64 || (unsigned __int8)(v13 - 35) <= 1u;\n if ( result )\n {\n v8 = (_BYTE)v13 == 64 || (unsigned __int8)(v13 - 35) <= 1u;\n }\n else if ( (v14 & 0x2000) != 0 )\n {\n return result;\n }\n }\n ++v7;\n }\n while ( v4 > (int)v7 );\nLABEL_10:\n v15 = v8 & v9;\n result = v11 & v12;\n if ( ((unsigned __int8)v11 & (unsigned __int8)v12) != 0 )\n return v15;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char sub_1230(const char *a1) {\n int v2;\n unsigned int v3;\n int v4;\n char result;\n const unsigned short **v6;\n long long v7;\n bool v8;\n char v9;\n const unsigned short *v10;\n char v11;\n char v12;\n long long v13;\n unsigned short v14;\n char v15;\n v2 = strlen(a1);\n v3 = v2 - 6;\n v4 = v2;\n result = 0;\n if (v3 <= 6) {\n v6 = __ctype_b_loc();\n v7 = 0LL;\n v8 = 0;\n v9 = 0;\n v10 = *v6;\n v11 = 0;\n v12 = 0;\n do {\n while (1) {\n v13 = a1[v7];\n v14 = v10[v13];\n if ((v14 & 512) == 0) break;\n ++v7;\n v12 = 1;\n if (v4 <= (int)v7) goto LABEL_10;\n }\n if ((v14 & 256) != 0) {\n v11 = 1;\n } else if ((v14 & 2048) != 0) {\n v9 = 1;\n } else {\n result = (uint8_t)v13 == 64 || (unsigned char)(v13 - 35) <= 1u;\n if (result) {\n v8 = (uint8_t)v13 == 64 || (unsigned char)(v13 - 35) <= 1u;\n } else if ((v14 & 8192) != 0) {\n return result;\n }\n }\n ++v7;\n } while (v4 > (int)v7);\n LABEL_10:\n v15 = v8 & v9;\n result = v11 & v12;\n if (((unsigned char)v11 & (unsigned char)v12) != 0) return v15;\n }\n return result;\n}", + "ida_pseudo_norm": "char func0(const char *a1) {\n int v2;\n unsigned int v3;\n int v4;\n char result;\n const unsigned short **v6;\n long long v7;\n bool v8;\n char v9;\n const unsigned short *v10;\n char v11;\n char v12;\n long long v13;\n unsigned short v14;\n char v15;\n v2 = strlen(a1);\n v3 = v2 - 6;\n v4 = v2;\n result = 0;\n if (v3 <= 6) {\n v6 = __ctype_b_loc();\n v7 = 0LL;\n v8 = 0;\n v9 = 0;\n v10 = *v6;\n v11 = 0;\n v12 = 0;\n do {\n while (1) {\n v13 = a1[v7];\n v14 = v10[v13];\n if ((v14 & 512) == 0) break;\n ++v7;\n v12 = 1;\n if (v4 <= (int)v7) goto LABEL_10;\n }\n if ((v14 & 256) != 0) {\n v11 = 1;\n } else if ((v14 & 2048) != 0) {\n v9 = 1;\n } else {\n result = (uint8_t)v13 == 64 || (unsigned char)(v13 - 35) <= 1u;\n if (result) {\n v8 = (uint8_t)v13 == 64 || (unsigned char)(v13 - 35) <= 1u;\n } else if ((v14 & 8192) != 0) {\n return result;\n }\n }\n ++v7;\n } while (v4 > (int)v7);\n LABEL_10:\n v15 = v8 & v9;\n result = v11 & v12;\n if (((unsigned char)v11 & (unsigned char)v12) != 0) return v15;\n }\n return result;\n}" + }, + { + "index": 823, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* string, const char* sample) {\n if (strstr(string, sample) != NULL) {\n regex_t regex;\n int result;\n char pattern[100] = \"^\";\n strcat(pattern, sample);\n regcomp(®ex, pattern, 0);\n result = regexec(®ex, string, 0, NULL, 0);\n regfree(®ex);\n if (result == 0) {\n return \"string starts with the given substring\";\n } else {\n return \"string doesnt start with the given substring\";\n }\n } else {\n return \"entered string isnt a substring\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"dreams for dreams makes life fun\", \"makes\"), \"string doesnt start with the given substring\") == 0);\n\n assert(strcmp(func0(\"Hi there how are you Hi alex\", \"Hi\"), \"string starts with the given substring\") == 0);\n\n assert(strcmp(func0(\"Its been a long day\", \"been\"), \"string doesnt start with the given substring\") == 0);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0xd0,%rsp\nmov %rdi,-0xc8(%rbp)\nmov %rsi,-0xd0(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmov -0xd0(%rbp),%rdx\nmov -0xc8(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1130 \ntest %rax,%rax\nje 1365 \nmovq $0x5e,-0x70(%rbp)\nmovq $0x0,-0x68(%rbp)\nmovq $0x0,-0x60(%rbp)\nmovq $0x0,-0x58(%rbp)\nmovq $0x0,-0x50(%rbp)\nmovq $0x0,-0x48(%rbp)\nmovq $0x0,-0x40(%rbp)\nmovq $0x0,-0x38(%rbp)\nmovq $0x0,-0x30(%rbp)\nmovq $0x0,-0x28(%rbp)\nmovq $0x0,-0x20(%rbp)\nmovq $0x0,-0x18(%rbp)\nmovl $0x0,-0x10(%rbp)\nmov -0xd0(%rbp),%rdx\nlea -0x70(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1120 \nlea -0x70(%rbp),%rcx\nlea -0xb0(%rbp),%rax\nmov $0x0,%edx\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 10f0 \nmov -0xc8(%rbp),%rsi\nlea -0xb0(%rbp),%rax\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rax,%rdi\ncallq 1110 \nmov %eax,-0xb4(%rbp)\nlea -0xb0(%rbp),%rax\nmov %rax,%rdi\ncallq 10c0 \ncmpl $0x0,-0xb4(%rbp)\njne 135c \nlea 0xcae(%rip),%rax\njmp 136c \nlea 0xccd(%rip),%rax\njmp 136c \nlea 0xcf4(%rip),%rax\nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 1380 \ncallq 10d0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0D0h\nmov [rbp+haystack], rdi\nmov [rbp+needle], rsi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rdx, [rbp+needle]\nmov rax, [rbp+haystack]\nmov rsi, rdx; needle\nmov rdi, rax; haystack\ncall _strstr\ntest rax, rax\njz loc_1365\nmov qword ptr [rbp+dest], 5Eh ; '^'\nmov [rbp+var_68], 0\nmov [rbp+var_60], 0\nmov [rbp+var_58], 0\nmov [rbp+var_50], 0\nmov [rbp+var_48], 0\nmov [rbp+var_40], 0\nmov [rbp+var_38], 0\nmov [rbp+var_30], 0\nmov [rbp+var_28], 0\nmov [rbp+var_20], 0\nmov [rbp+var_18], 0\nmov [rbp+var_10], 0\nmov rdx, [rbp+needle]\nlea rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\nlea rcx, [rbp+dest]\nlea rax, [rbp+preg]\nmov edx, 0; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov rsi, [rbp+haystack]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_B4], eax\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\ncmp [rbp+var_B4], 0\njnz short loc_135C\nlea rax, aStringStartsWi; \"string starts with the given substring\"\njmp short loc_136C\nloc_135C:\nlea rax, s2; \"string doesnt start with the given subs\"...\njmp short loc_136C\nloc_1365:\nlea rax, aEnteredStringI; \"entered string isnt a substring\"\nloc_136C:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1380\ncall ___stack_chk_fail\nlocret_1380:\nleave\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1, const char *a2)\n{\n int v3; // [rsp+1Ch] [rbp-B4h]\n regex_t preg; // [rsp+20h] [rbp-B0h] BYREF\n char dest[8]; // [rsp+60h] [rbp-70h] BYREF\n __int64 v6; // [rsp+68h] [rbp-68h]\n __int64 v7; // [rsp+70h] [rbp-60h]\n __int64 v8; // [rsp+78h] [rbp-58h]\n __int64 v9; // [rsp+80h] [rbp-50h]\n __int64 v10; // [rsp+88h] [rbp-48h]\n __int64 v11; // [rsp+90h] [rbp-40h]\n __int64 v12; // [rsp+98h] [rbp-38h]\n __int64 v13; // [rsp+A0h] [rbp-30h]\n __int64 v14; // [rsp+A8h] [rbp-28h]\n __int64 v15; // [rsp+B0h] [rbp-20h]\n __int64 v16; // [rsp+B8h] [rbp-18h]\n int v17; // [rsp+C0h] [rbp-10h]\n unsigned __int64 v18; // [rsp+C8h] [rbp-8h]\n\n v18 = __readfsqword(0x28u);\n if ( !strstr(a1, a2) )\n return \"entered string isnt a substring\";\n *(_QWORD *)dest = 94LL;\n v6 = 0LL;\n v7 = 0LL;\n v8 = 0LL;\n v9 = 0LL;\n v10 = 0LL;\n v11 = 0LL;\n v12 = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0;\n strcat(dest, a2);\n regcomp(&preg, dest, 0);\n v3 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if ( v3 )\n return \"string doesnt start with the given substring\";\n else\n return \"string starts with the given substring\";\n}", + "ida_strip_asm": "sub_1229:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0D0h\nmov [rbp+haystack], rdi\nmov [rbp+needle], rsi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rdx, [rbp+needle]\nmov rax, [rbp+haystack]\nmov rsi, rdx; needle\nmov rdi, rax; haystack\ncall _strstr\ntest rax, rax\njz loc_1365\nmov qword ptr [rbp+dest], 5Eh ; '^'\nmov [rbp+var_68], 0\nmov [rbp+var_60], 0\nmov [rbp+var_58], 0\nmov [rbp+var_50], 0\nmov [rbp+var_48], 0\nmov [rbp+var_40], 0\nmov [rbp+var_38], 0\nmov [rbp+var_30], 0\nmov [rbp+var_28], 0\nmov [rbp+var_20], 0\nmov [rbp+var_18], 0\nmov [rbp+var_10], 0\nmov rdx, [rbp+needle]\nlea rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\nlea rcx, [rbp+dest]\nlea rax, [rbp+preg]\nmov edx, 0; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov rsi, [rbp+haystack]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_B4], eax\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\ncmp [rbp+var_B4], 0\njnz short loc_135C\nlea rax, aStringStartsWi; \"string starts with the given substring\"\njmp short loc_136C\nloc_135C:\nlea rax, s2; \"string doesnt start with the given subs\"...\njmp short loc_136C\nloc_1365:\nlea rax, aEnteredStringI; \"entered string isnt a substring\"\nloc_136C:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1380\ncall ___stack_chk_fail\nlocret_1380:\nleave\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1229(const char *a1, const char *a2)\n{\n int v3; // [rsp+1Ch] [rbp-B4h]\n regex_t preg; // [rsp+20h] [rbp-B0h] BYREF\n char dest[8]; // [rsp+60h] [rbp-70h] BYREF\n __int64 v6; // [rsp+68h] [rbp-68h]\n __int64 v7; // [rsp+70h] [rbp-60h]\n __int64 v8; // [rsp+78h] [rbp-58h]\n __int64 v9; // [rsp+80h] [rbp-50h]\n __int64 v10; // [rsp+88h] [rbp-48h]\n __int64 v11; // [rsp+90h] [rbp-40h]\n __int64 v12; // [rsp+98h] [rbp-38h]\n __int64 v13; // [rsp+A0h] [rbp-30h]\n __int64 v14; // [rsp+A8h] [rbp-28h]\n __int64 v15; // [rsp+B0h] [rbp-20h]\n __int64 v16; // [rsp+B8h] [rbp-18h]\n int v17; // [rsp+C0h] [rbp-10h]\n unsigned __int64 v18; // [rsp+C8h] [rbp-8h]\n\n v18 = __readfsqword(0x28u);\n if ( !strstr(a1, a2) )\n return \"entered string isnt a substring\";\n *(_QWORD *)dest = 94LL;\n v6 = 0LL;\n v7 = 0LL;\n v8 = 0LL;\n v9 = 0LL;\n v10 = 0LL;\n v11 = 0LL;\n v12 = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0;\n strcat(dest, a2);\n regcomp(&preg, dest, 0);\n v3 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if ( v3 )\n return \"string doesnt start with the given substring\";\n else\n return \"string starts with the given substring\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1229(const char *a1, const char *a2) {\n int v3;\n regex_t preg;\n char dest[8];\n long long v6;\n long long v7;\n long long v8;\n long long v9;\n long long v10;\n long long v11;\n long long v12;\n long long v13;\n long long v14;\n long long v15;\n long long v16;\n int v17;\n unsigned long long v18;\n v18 = __readfsqword(40u);\n if (!strstr(a1, a2)) return \"entered string isnt a substring\";\n *(uint64_t *)dest = 94LL;\n v6 = 0LL;\n v7 = 0LL;\n v8 = 0LL;\n v9 = 0LL;\n v10 = 0LL;\n v11 = 0LL;\n v12 = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0;\n strcat(dest, a2);\n regcomp(&preg, dest, 0);\n v3 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if (v3)\n return \"string doesnt start with the given substring\";\n else\n return \"string starts with the given substring\";\n}", + "ida_pseudo_norm": "const char *func0(const char *a1, const char *a2) {\n int v3;\n regex_t preg;\n char dest[8];\n long long v6;\n long long v7;\n long long v8;\n long long v9;\n long long v10;\n long long v11;\n long long v12;\n long long v13;\n long long v14;\n long long v15;\n long long v16;\n int v17;\n unsigned long long v18;\n v18 = __readfsqword(40u);\n if (!strstr(a1, a2)) return \"entered string isnt a substring\";\n *(uint64_t *)dest = 94LL;\n v6 = 0LL;\n v7 = 0LL;\n v8 = 0LL;\n v9 = 0LL;\n v10 = 0LL;\n v11 = 0LL;\n v12 = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0;\n strcat(dest, a2);\n regcomp(&preg, dest, 0);\n v3 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if (v3)\n return \"string doesnt start with the given substring\";\n else\n return \"string starts with the given substring\";\n}" + }, + { + "index": 823, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* string, const char* sample) {\n if (strstr(string, sample) != NULL) {\n regex_t regex;\n int result;\n char pattern[100] = \"^\";\n strcat(pattern, sample);\n regcomp(®ex, pattern, 0);\n result = regexec(®ex, string, 0, NULL, 0);\n regfree(®ex);\n if (result == 0) {\n return \"string starts with the given substring\";\n } else {\n return \"string doesnt start with the given substring\";\n }\n } else {\n return \"entered string isnt a substring\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"dreams for dreams makes life fun\", \"makes\"), \"string doesnt start with the given substring\") == 0);\n\n assert(strcmp(func0(\"Hi there how are you Hi alex\", \"Hi\"), \"string starts with the given substring\") == 0);\n\n assert(strcmp(func0(\"Its been a long day\", \"been\"), \"string doesnt start with the given substring\") == 0);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nsub $0xb0,%rsp\nmov %rdi,%rbx\nmov %rsi,%rbp\nmov %fs:0x28,%rax\nmov %rax,0xa8(%rsp)\nxor %eax,%eax\ncallq 1110 \nmov %rax,%rdx\nlea 0xe20(%rip),%rax\ntest %rdx,%rdx\nje 132d \nmovq $0x5e,0x40(%rsp)\nmovq $0x0,0x48(%rsp)\nmovq $0x0,0x50(%rsp)\nmovq $0x0,0x58(%rsp)\nmovq $0x0,0x60(%rsp)\nmovq $0x0,0x68(%rsp)\nmovq $0x0,0x70(%rsp)\nmovq $0x0,0x78(%rsp)\nmovq $0x0,0x80(%rsp)\nmovq $0x0,0x88(%rsp)\nmovq $0x0,0x90(%rsp)\nmovq $0x0,0x98(%rsp)\nmovl $0x0,0xa0(%rsp)\nlea 0x40(%rsp),%r12\nmov $0x64,%edx\nmov %rbp,%rsi\nmov %r12,%rdi\ncallq 10b0 <__strcat_chk@plt>\nmov %rsp,%rbp\nmov $0x0,%edx\nmov %r12,%rsi\nmov %rbp,%rdi\ncallq 10f0 \nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rbx,%rsi\nmov %rbp,%rdi\ncallq 1100 \nmov %eax,%ebx\nmov %rbp,%rdi\ncallq 10c0 \ntest %ebx,%ebx\nlea 0xce6(%rip),%rax\nlea 0xd07(%rip),%rdx\ncmovne %rdx,%rax\nmov 0xa8(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 134c \nadd $0xb0,%rsp\npop %rbx\npop %rbp\npop %r12\nretq\ncallq 10d0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 0B0h\nmov rbx, rdi\nmov rbp, rsi\nmov rax, fs:28h\nmov [rsp+0C8h+var_20], rax\nxor eax, eax\ncall _strstr\nmov rdx, rax\nlea rax, aEnteredStringI; \"entered string isnt a substring\"\ntest rdx, rdx\njz loc_134D\nmov qword ptr [rsp+0C8h+pattern], 5Eh ; '^'\nmov [rsp+0C8h+var_80], 0\nmov [rsp+0C8h+var_78], 0\nmov [rsp+0C8h+var_70], 0\nmov [rsp+0C8h+var_68], 0\nmov [rsp+0C8h+var_60], 0\nmov [rsp+0C8h+var_58], 0\nmov [rsp+0C8h+var_50], 0\nmov [rsp+0C8h+var_48], 0\nmov [rsp+0C8h+var_40], 0\nmov [rsp+0C8h+var_38], 0\nmov [rsp+0C8h+var_30], 0\nmov [rsp+0C8h+var_28], 0\nlea r12, [rsp+0C8h+pattern]\nmov edx, 64h ; 'd'\nmov rsi, rbp\nmov rdi, r12\ncall ___strcat_chk\nmov rbp, rsp\nmov edx, 0; cflags\nmov rsi, r12; pattern\nmov rdi, rbp; preg\ncall _regcomp\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov ebx, eax\nmov rdi, rbp; preg\ncall _regfree\ntest ebx, ebx\nlea rax, s2; \"string doesnt start with the given subs\"...\nlea rdx, aStringStartsWi; \"string starts with the given substring\"\ncmovz rax, rdx\nloc_134D:\nmov rdx, [rsp+0C8h+var_20]\nsub rdx, fs:28h\njnz short loc_136C\nadd rsp, 0B0h\npop rbx\npop rbp\npop r12\nretn\nloc_136C:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string, const char *a2)\n{\n char *v2; // rdx\n const char *result; // rax\n int v4; // ebx\n regex_t v5; // [rsp+0h] [rbp-C8h] BYREF\n char pattern[8]; // [rsp+40h] [rbp-88h] BYREF\n __int64 v7; // [rsp+48h] [rbp-80h]\n __int64 v8; // [rsp+50h] [rbp-78h]\n __int64 v9; // [rsp+58h] [rbp-70h]\n __int64 v10; // [rsp+60h] [rbp-68h]\n __int64 v11; // [rsp+68h] [rbp-60h]\n __int64 v12; // [rsp+70h] [rbp-58h]\n __int64 v13; // [rsp+78h] [rbp-50h]\n __int64 v14; // [rsp+80h] [rbp-48h]\n __int64 v15; // [rsp+88h] [rbp-40h]\n __int64 v16; // [rsp+90h] [rbp-38h]\n __int64 v17; // [rsp+98h] [rbp-30h]\n int v18; // [rsp+A0h] [rbp-28h]\n unsigned __int64 v19; // [rsp+A8h] [rbp-20h]\n\n v19 = __readfsqword(0x28u);\n v2 = strstr(string, a2);\n result = \"entered string isnt a substring\";\n if ( v2 )\n {\n *(_QWORD *)pattern = 94LL;\n v7 = 0LL;\n v8 = 0LL;\n v9 = 0LL;\n v10 = 0LL;\n v11 = 0LL;\n v12 = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0LL;\n v18 = 0;\n __strcat_chk(pattern, a2, 100LL);\n regcomp(&v5, pattern, 0);\n v4 = regexec(&v5, string, 0LL, 0LL, 0);\n regfree(&v5);\n result = \"string doesnt start with the given substring\";\n if ( !v4 )\n return \"string starts with the given substring\";\n }\n return result;\n}", + "ida_strip_asm": "sub_1229:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 0B0h\nmov rbx, rdi\nmov rbp, rsi\nmov rax, fs:28h\nmov [rsp+0C8h+var_20], rax\nxor eax, eax\ncall _strstr\nmov rdx, rax\nlea rax, aEnteredStringI; \"entered string isnt a substring\"\ntest rdx, rdx\njz loc_134D\nmov qword ptr [rsp+0C8h+pattern], 5Eh ; '^'\nmov [rsp+0C8h+var_80], 0\nmov [rsp+0C8h+var_78], 0\nmov [rsp+0C8h+var_70], 0\nmov [rsp+0C8h+var_68], 0\nmov [rsp+0C8h+var_60], 0\nmov [rsp+0C8h+var_58], 0\nmov [rsp+0C8h+var_50], 0\nmov [rsp+0C8h+var_48], 0\nmov [rsp+0C8h+var_40], 0\nmov [rsp+0C8h+var_38], 0\nmov [rsp+0C8h+var_30], 0\nmov [rsp+0C8h+var_28], 0\nlea r12, [rsp+0C8h+pattern]\nmov edx, 64h ; 'd'\nmov rsi, rbp\nmov rdi, r12\ncall ___strcat_chk\nmov rbp, rsp\nmov edx, 0; cflags\nmov rsi, r12; pattern\nmov rdi, rbp; preg\ncall _regcomp\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov ebx, eax\nmov rdi, rbp; preg\ncall _regfree\ntest ebx, ebx\nlea rax, s2; \"string doesnt start with the given subs\"...\nlea rdx, aStringStartsWi; \"string starts with the given substring\"\ncmovz rax, rdx\nloc_134D:\nmov rdx, [rsp+0C8h+var_20]\nsub rdx, fs:28h\njnz short loc_136C\nadd rsp, 0B0h\npop rbx\npop rbp\npop r12\nretn\nloc_136C:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_1229(char *string, const char *a2)\n{\n char *v2; // rdx\n const char *result; // rax\n int v4; // ebx\n regex_t v5; // [rsp+0h] [rbp-C8h] BYREF\n char pattern[8]; // [rsp+40h] [rbp-88h] BYREF\n __int64 v7; // [rsp+48h] [rbp-80h]\n __int64 v8; // [rsp+50h] [rbp-78h]\n __int64 v9; // [rsp+58h] [rbp-70h]\n __int64 v10; // [rsp+60h] [rbp-68h]\n __int64 v11; // [rsp+68h] [rbp-60h]\n __int64 v12; // [rsp+70h] [rbp-58h]\n __int64 v13; // [rsp+78h] [rbp-50h]\n __int64 v14; // [rsp+80h] [rbp-48h]\n __int64 v15; // [rsp+88h] [rbp-40h]\n __int64 v16; // [rsp+90h] [rbp-38h]\n __int64 v17; // [rsp+98h] [rbp-30h]\n int v18; // [rsp+A0h] [rbp-28h]\n unsigned __int64 v19; // [rsp+A8h] [rbp-20h]\n\n v19 = __readfsqword(0x28u);\n v2 = strstr(string, a2);\n result = \"entered string isnt a substring\";\n if ( v2 )\n {\n *(_QWORD *)pattern = 94LL;\n v7 = 0LL;\n v8 = 0LL;\n v9 = 0LL;\n v10 = 0LL;\n v11 = 0LL;\n v12 = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0LL;\n v18 = 0;\n __strcat_chk(pattern, a2, 100LL);\n regcomp(&v5, pattern, 0);\n v4 = regexec(&v5, string, 0LL, 0LL, 0);\n regfree(&v5);\n result = \"string doesnt start with the given substring\";\n if ( !v4 )\n return \"string starts with the given substring\";\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1229(char *string, const char *a2) {\n char *v2;\n const char *result;\n int v4;\n regex_t v5;\n char pattern[8];\n long long v7;\n long long v8;\n long long v9;\n long long v10;\n long long v11;\n long long v12;\n long long v13;\n long long v14;\n long long v15;\n long long v16;\n long long v17;\n int v18;\n unsigned long long v19;\n v19 = __readfsqword(40u);\n v2 = strstr(string, a2);\n result = \"entered string isnt a substring\";\n if (v2) {\n *(uint64_t *)pattern = 94LL;\n v7 = 0LL;\n v8 = 0LL;\n v9 = 0LL;\n v10 = 0LL;\n v11 = 0LL;\n v12 = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0LL;\n v18 = 0;\n __strcat_chk(pattern, a2, 100LL);\n regcomp(&v5, pattern, 0);\n v4 = regexec(&v5, string, 0LL, 0LL, 0);\n regfree(&v5);\n result = \"string doesnt start with the given substring\";\n if (!v4) return \"string starts with the given substring\";\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string, const char *a2) {\n char *v2;\n const char *result;\n int v4;\n regex_t v5;\n char pattern[8];\n long long v7;\n long long v8;\n long long v9;\n long long v10;\n long long v11;\n long long v12;\n long long v13;\n long long v14;\n long long v15;\n long long v16;\n long long v17;\n int v18;\n unsigned long long v19;\n v19 = __readfsqword(40u);\n v2 = strstr(string, a2);\n result = \"entered string isnt a substring\";\n if (v2) {\n *(uint64_t *)pattern = 94LL;\n v7 = 0LL;\n v8 = 0LL;\n v9 = 0LL;\n v10 = 0LL;\n v11 = 0LL;\n v12 = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v16 = 0LL;\n v17 = 0LL;\n v18 = 0;\n __strcat_chk(pattern, a2, 100LL);\n regcomp(&v5, pattern, 0);\n v4 = regexec(&v5, string, 0LL, 0LL, 0);\n regfree(&v5);\n result = \"string doesnt start with the given substring\";\n if (!v4) return \"string starts with the given substring\";\n }\n return result;\n}" + }, + { + "index": 823, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* string, const char* sample) {\n if (strstr(string, sample) != NULL) {\n regex_t regex;\n int result;\n char pattern[100] = \"^\";\n strcat(pattern, sample);\n regcomp(®ex, pattern, 0);\n result = regexec(®ex, string, 0, NULL, 0);\n regfree(®ex);\n if (result == 0) {\n return \"string starts with the given substring\";\n } else {\n return \"string doesnt start with the given substring\";\n }\n } else {\n return \"entered string isnt a substring\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"dreams for dreams makes life fun\", \"makes\"), \"string doesnt start with the given substring\") == 0);\n\n assert(strcmp(func0(\"Hi there how are you Hi alex\", \"Hi\"), \"string starts with the given substring\") == 0);\n\n assert(strcmp(func0(\"Its been a long day\", \"been\"), \"string doesnt start with the given substring\") == 0);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\nmov %rsi,%r12\npush %rbp\nmov %rdi,%rbp\nsub $0xb0,%rsp\nmov %fs:0x28,%rax\nmov %rax,0xa8(%rsp)\nxor %eax,%eax\ncallq 1110 \nmov %rax,%r8\nlea 0xd28(%rip),%rax\ntest %r8,%r8\nje 13d8 \npxor %xmm0,%xmm0\nmov %r12,%rsi\nlea 0x41(%rsp),%rdi\nmov %rsp,%r12\nmov $0x63,%edx\nlea 0x40(%rsp),%r13\nmovaps %xmm0,0x50(%rsp)\nmovaps %xmm0,0x60(%rsp)\nmovaps %xmm0,0x70(%rsp)\nmovaps %xmm0,0x80(%rsp)\nmovaps %xmm0,0x90(%rsp)\nmovq $0x5e,0x40(%rsp)\nmovq $0x0,0x48(%rsp)\nmovl $0x0,0xa0(%rsp)\ncallq 1100 <__strcpy_chk@plt>\nxor %edx,%edx\nmov %r13,%rsi\nmov %r12,%rdi\ncallq 10e0 \nxor %edx,%edx\nxor %r8d,%r8d\nxor %ecx,%ecx\nmov %rbp,%rsi\nmov %r12,%rdi\ncallq 10f0 \nmov %r12,%rdi\nmov %eax,%ebp\ncallq 10b0 \ntest %ebp,%ebp\nlea 0xc3b(%rip),%rax\nlea 0xc5c(%rip),%rdx\ncmovne %rdx,%rax\nmov 0xa8(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 13f8 \nadd $0xb0,%rsp\npop %rbp\npop %r12\npop %r13\nretq\ncallq 10c0 <__stack_chk_fail@plt>\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\nmov rbp, rsi\npush rbx\nmov rbx, rdi\nsub rsp, 0B0h\nmov rax, fs:28h\nmov [rsp+0C8h+var_20], rax\nxor eax, eax\ncall _strstr\nmov rdx, rax\nlea rax, aEnteredStringI; \"entered string isnt a substring\"\ntest rdx, rdx\njz loc_13E7\npxor xmm0, xmm0\nmov rsi, rbp\nlea rdi, [rsp+0C8h+pattern+1]\nmov rbp, rsp\nmov edx, 63h ; 'c'\nlea r12, [rsp+0C8h+pattern]\nmovaps [rsp+0C8h+var_78], xmm0\nmovaps [rsp+0C8h+var_68], xmm0\nmovaps [rsp+0C8h+var_58], xmm0\nmovaps [rsp+0C8h+var_48], xmm0\nmovaps [rsp+0C8h+var_38], xmm0\nmov qword ptr [rsp+0C8h+pattern], 5Eh ; '^'\nmov [rsp+0C8h+var_80], 0\nmov [rsp+0C8h+var_28], 0\ncall ___strcpy_chk\nxor edx, edx; cflags\nmov rsi, r12; pattern\nmov rdi, rbp; preg\ncall _regcomp\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, s2; \"string doesnt start with the given subs\"...\nlea rdx, aStringStartsWi; \"string starts with the given substring\"\ncmovz rax, rdx\nloc_13E7:\nmov rdx, [rsp+0C8h+var_20]\nsub rdx, fs:28h\njnz short loc_1406\nadd rsp, 0B0h\npop rbx\npop rbp\npop r12\nretn\nloc_1406:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string, const char *a2)\n{\n char *v2; // rdx\n const char *result; // rax\n int v4; // ebx\n regex_t v5; // [rsp+0h] [rbp-C8h] BYREF\n char pattern[8]; // [rsp+40h] [rbp-88h] BYREF\n __int64 v7; // [rsp+48h] [rbp-80h]\n __int128 v8; // [rsp+50h] [rbp-78h]\n __int128 v9; // [rsp+60h] [rbp-68h]\n __int128 v10; // [rsp+70h] [rbp-58h]\n __int128 v11; // [rsp+80h] [rbp-48h]\n __int128 v12; // [rsp+90h] [rbp-38h]\n int v13; // [rsp+A0h] [rbp-28h]\n unsigned __int64 v14; // [rsp+A8h] [rbp-20h]\n\n v14 = __readfsqword(0x28u);\n v2 = strstr(string, a2);\n result = \"entered string isnt a substring\";\n if ( v2 )\n {\n v8 = 0LL;\n v9 = 0LL;\n v10 = 0LL;\n v11 = 0LL;\n v12 = 0LL;\n *(_QWORD *)pattern = 94LL;\n v7 = 0LL;\n v13 = 0;\n __strcpy_chk(&pattern[1], a2, 99LL);\n regcomp(&v5, pattern, 0);\n v4 = regexec(&v5, string, 0LL, 0LL, 0);\n regfree(&v5);\n result = \"string doesnt start with the given substring\";\n if ( !v4 )\n return \"string starts with the given substring\";\n }\n return result;\n}", + "ida_strip_asm": "sub_1310:\nendbr64\npush r12\npush rbp\nmov rbp, rsi\npush rbx\nmov rbx, rdi\nsub rsp, 0B0h\nmov rax, fs:28h\nmov [rsp+0C8h+var_20], rax\nxor eax, eax\ncall _strstr\nmov rdx, rax\nlea rax, aEnteredStringI; \"entered string isnt a substring\"\ntest rdx, rdx\njz loc_13E7\npxor xmm0, xmm0\nmov rsi, rbp\nlea rdi, [rsp+0C8h+pattern+1]\nmov rbp, rsp\nmov edx, 63h ; 'c'\nlea r12, [rsp+0C8h+pattern]\nmovaps [rsp+0C8h+var_78], xmm0\nmovaps [rsp+0C8h+var_68], xmm0\nmovaps [rsp+0C8h+var_58], xmm0\nmovaps [rsp+0C8h+var_48], xmm0\nmovaps [rsp+0C8h+var_38], xmm0\nmov qword ptr [rsp+0C8h+pattern], 5Eh ; '^'\nmov [rsp+0C8h+var_80], 0\nmov [rsp+0C8h+var_28], 0\ncall ___strcpy_chk\nxor edx, edx; cflags\nmov rsi, r12; pattern\nmov rdi, rbp; preg\ncall _regcomp\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, s2; \"string doesnt start with the given subs\"...\nlea rdx, aStringStartsWi; \"string starts with the given substring\"\ncmovz rax, rdx\nloc_13E7:\nmov rdx, [rsp+0C8h+var_20]\nsub rdx, fs:28h\njnz short loc_1406\nadd rsp, 0B0h\npop rbx\npop rbp\npop r12\nretn\nloc_1406:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_1310(char *string, const char *a2)\n{\n char *v2; // rdx\n const char *result; // rax\n int v4; // ebx\n regex_t v5; // [rsp+0h] [rbp-C8h] BYREF\n char pattern[8]; // [rsp+40h] [rbp-88h] BYREF\n __int64 v7; // [rsp+48h] [rbp-80h]\n __int128 v8; // [rsp+50h] [rbp-78h]\n __int128 v9; // [rsp+60h] [rbp-68h]\n __int128 v10; // [rsp+70h] [rbp-58h]\n __int128 v11; // [rsp+80h] [rbp-48h]\n __int128 v12; // [rsp+90h] [rbp-38h]\n int v13; // [rsp+A0h] [rbp-28h]\n unsigned __int64 v14; // [rsp+A8h] [rbp-20h]\n\n v14 = __readfsqword(0x28u);\n v2 = strstr(string, a2);\n result = \"entered string isnt a substring\";\n if ( v2 )\n {\n v8 = 0LL;\n v9 = 0LL;\n v10 = 0LL;\n v11 = 0LL;\n v12 = 0LL;\n *(_QWORD *)pattern = 94LL;\n v7 = 0LL;\n v13 = 0;\n __strcpy_chk(&pattern[1], a2, 99LL);\n regcomp(&v5, pattern, 0);\n v4 = regexec(&v5, string, 0LL, 0LL, 0);\n regfree(&v5);\n result = \"string doesnt start with the given substring\";\n if ( !v4 )\n return \"string starts with the given substring\";\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1310(char *string, const char *a2) {\n char *v2;\n const char *result;\n int v4;\n regex_t v5;\n char pattern[8];\n long long v7;\n __int128 v8;\n __int128 v9;\n __int128 v10;\n __int128 v11;\n __int128 v12;\n int v13;\n unsigned long long v14;\n v14 = __readfsqword(40u);\n v2 = strstr(string, a2);\n result = \"entered string isnt a substring\";\n if (v2) {\n v8 = 0LL;\n v9 = 0LL;\n v10 = 0LL;\n v11 = 0LL;\n v12 = 0LL;\n *(uint64_t *)pattern = 94LL;\n v7 = 0LL;\n v13 = 0;\n __strcpy_chk(&pattern[1], a2, 99LL);\n regcomp(&v5, pattern, 0);\n v4 = regexec(&v5, string, 0LL, 0LL, 0);\n regfree(&v5);\n result = \"string doesnt start with the given substring\";\n if (!v4) return \"string starts with the given substring\";\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string, const char *a2) {\n char *v2;\n const char *result;\n int v4;\n regex_t v5;\n char pattern[8];\n long long v7;\n __int128 v8;\n __int128 v9;\n __int128 v10;\n __int128 v11;\n __int128 v12;\n int v13;\n unsigned long long v14;\n v14 = __readfsqword(40u);\n v2 = strstr(string, a2);\n result = \"entered string isnt a substring\";\n if (v2) {\n v8 = 0LL;\n v9 = 0LL;\n v10 = 0LL;\n v11 = 0LL;\n v12 = 0LL;\n *(uint64_t *)pattern = 94LL;\n v7 = 0LL;\n v13 = 0;\n __strcpy_chk(&pattern[1], a2, 99LL);\n regcomp(&v5, pattern, 0);\n v4 = regexec(&v5, string, 0LL, 0LL, 0);\n regfree(&v5);\n result = \"string doesnt start with the given substring\";\n if (!v4) return \"string starts with the given substring\";\n }\n return result;\n}" + }, + { + "index": 823, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* string, const char* sample) {\n if (strstr(string, sample) != NULL) {\n regex_t regex;\n int result;\n char pattern[100] = \"^\";\n strcat(pattern, sample);\n regcomp(®ex, pattern, 0);\n result = regexec(®ex, string, 0, NULL, 0);\n regfree(®ex);\n if (result == 0) {\n return \"string starts with the given substring\";\n } else {\n return \"string doesnt start with the given substring\";\n }\n } else {\n return \"entered string isnt a substring\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"dreams for dreams makes life fun\", \"makes\"), \"string doesnt start with the given substring\") == 0);\n\n assert(strcmp(func0(\"Hi there how are you Hi alex\", \"Hi\"), \"string starts with the given substring\") == 0);\n\n assert(strcmp(func0(\"Its been a long day\", \"been\"), \"string doesnt start with the given substring\") == 0);\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\nmov %rsi,%r12\npush %rbp\nmov %rdi,%rbp\nsub $0xb0,%rsp\nmov %fs:0x28,%rax\nmov %rax,0xa8(%rsp)\nxor %eax,%eax\ncallq 1110 \nmov %rax,%r8\nlea 0xd28(%rip),%rax\ntest %r8,%r8\nje 13d8 \npxor %xmm0,%xmm0\nmov %r12,%rsi\nlea 0x41(%rsp),%rdi\nmov %rsp,%r12\nmov $0x63,%edx\nlea 0x40(%rsp),%r13\nmovaps %xmm0,0x50(%rsp)\nmovaps %xmm0,0x60(%rsp)\nmovaps %xmm0,0x70(%rsp)\nmovaps %xmm0,0x80(%rsp)\nmovaps %xmm0,0x90(%rsp)\nmovq $0x5e,0x40(%rsp)\nmovq $0x0,0x48(%rsp)\nmovl $0x0,0xa0(%rsp)\ncallq 1100 <__strcpy_chk@plt>\nxor %edx,%edx\nmov %r13,%rsi\nmov %r12,%rdi\ncallq 10e0 \nxor %edx,%edx\nxor %r8d,%r8d\nxor %ecx,%ecx\nmov %rbp,%rsi\nmov %r12,%rdi\ncallq 10f0 \nmov %r12,%rdi\nmov %eax,%ebp\ncallq 10b0 \ntest %ebp,%ebp\nlea 0xc3b(%rip),%rax\nlea 0xc5c(%rip),%rdx\ncmovne %rdx,%rax\nmov 0xa8(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 13f8 \nadd $0xb0,%rsp\npop %rbp\npop %r12\npop %r13\nretq\ncallq 10c0 <__stack_chk_fail@plt>\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\nmov rbp, rsi\npush rbx\nmov rbx, rdi\nsub rsp, 0B0h\nmov rax, fs:28h\nmov [rsp+0C8h+var_20], rax\nxor eax, eax\ncall _strstr\nmov rdx, rax\nlea rax, aEnteredStringI; \"entered string isnt a substring\"\ntest rdx, rdx\njz loc_13E7\npxor xmm0, xmm0\nmov rsi, rbp\nlea rdi, [rsp+0C8h+pattern+1]\nmov rbp, rsp\nmov edx, 63h ; 'c'\nlea r12, [rsp+0C8h+pattern]\nmovaps [rsp+0C8h+var_78], xmm0\nmovaps [rsp+0C8h+var_68], xmm0\nmovaps [rsp+0C8h+var_58], xmm0\nmovaps [rsp+0C8h+var_48], xmm0\nmovaps [rsp+0C8h+var_38], xmm0\nmov qword ptr [rsp+0C8h+pattern], 5Eh ; '^'\nmov [rsp+0C8h+var_80], 0\nmov [rsp+0C8h+var_28], 0\ncall ___strcpy_chk\nxor edx, edx; cflags\nmov rsi, r12; pattern\nmov rdi, rbp; preg\ncall _regcomp\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, s2; \"string doesnt start with the given subs\"...\nlea rdx, aStringStartsWi; \"string starts with the given substring\"\ncmovz rax, rdx\nloc_13E7:\nmov rdx, [rsp+0C8h+var_20]\nsub rdx, fs:28h\njnz short loc_1406\nadd rsp, 0B0h\npop rbx\npop rbp\npop r12\nretn\nloc_1406:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string, const char *a2)\n{\n char *v2; // rdx\n const char *result; // rax\n int v4; // ebx\n regex_t v5; // [rsp+0h] [rbp-C8h] BYREF\n char pattern[8]; // [rsp+40h] [rbp-88h] BYREF\n __int64 v7; // [rsp+48h] [rbp-80h]\n __int128 v8; // [rsp+50h] [rbp-78h]\n __int128 v9; // [rsp+60h] [rbp-68h]\n __int128 v10; // [rsp+70h] [rbp-58h]\n __int128 v11; // [rsp+80h] [rbp-48h]\n __int128 v12; // [rsp+90h] [rbp-38h]\n int v13; // [rsp+A0h] [rbp-28h]\n unsigned __int64 v14; // [rsp+A8h] [rbp-20h]\n\n v14 = __readfsqword(0x28u);\n v2 = strstr(string, a2);\n result = \"entered string isnt a substring\";\n if ( v2 )\n {\n v8 = 0LL;\n v9 = 0LL;\n v10 = 0LL;\n v11 = 0LL;\n v12 = 0LL;\n *(_QWORD *)pattern = 94LL;\n v7 = 0LL;\n v13 = 0;\n __strcpy_chk(&pattern[1], a2, 99LL);\n regcomp(&v5, pattern, 0);\n v4 = regexec(&v5, string, 0LL, 0LL, 0);\n regfree(&v5);\n result = \"string doesnt start with the given substring\";\n if ( !v4 )\n return \"string starts with the given substring\";\n }\n return result;\n}", + "ida_strip_asm": "sub_1310:\nendbr64\npush r12\npush rbp\nmov rbp, rsi\npush rbx\nmov rbx, rdi\nsub rsp, 0B0h\nmov rax, fs:28h\nmov [rsp+0C8h+var_20], rax\nxor eax, eax\ncall _strstr\nmov rdx, rax\nlea rax, aEnteredStringI; \"entered string isnt a substring\"\ntest rdx, rdx\njz loc_13E7\npxor xmm0, xmm0\nmov rsi, rbp\nlea rdi, [rsp+0C8h+pattern+1]\nmov rbp, rsp\nmov edx, 63h ; 'c'\nlea r12, [rsp+0C8h+pattern]\nmovaps [rsp+0C8h+var_78], xmm0\nmovaps [rsp+0C8h+var_68], xmm0\nmovaps [rsp+0C8h+var_58], xmm0\nmovaps [rsp+0C8h+var_48], xmm0\nmovaps [rsp+0C8h+var_38], xmm0\nmov qword ptr [rsp+0C8h+pattern], 5Eh ; '^'\nmov [rsp+0C8h+var_80], 0\nmov [rsp+0C8h+var_28], 0\ncall ___strcpy_chk\nxor edx, edx; cflags\nmov rsi, r12; pattern\nmov rdi, rbp; preg\ncall _regcomp\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, s2; \"string doesnt start with the given subs\"...\nlea rdx, aStringStartsWi; \"string starts with the given substring\"\ncmovz rax, rdx\nloc_13E7:\nmov rdx, [rsp+0C8h+var_20]\nsub rdx, fs:28h\njnz short loc_1406\nadd rsp, 0B0h\npop rbx\npop rbp\npop r12\nretn\nloc_1406:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_1310(char *string, const char *a2)\n{\n char *v2; // rdx\n const char *result; // rax\n int v4; // ebx\n regex_t v5; // [rsp+0h] [rbp-C8h] BYREF\n char pattern[8]; // [rsp+40h] [rbp-88h] BYREF\n __int64 v7; // [rsp+48h] [rbp-80h]\n __int128 v8; // [rsp+50h] [rbp-78h]\n __int128 v9; // [rsp+60h] [rbp-68h]\n __int128 v10; // [rsp+70h] [rbp-58h]\n __int128 v11; // [rsp+80h] [rbp-48h]\n __int128 v12; // [rsp+90h] [rbp-38h]\n int v13; // [rsp+A0h] [rbp-28h]\n unsigned __int64 v14; // [rsp+A8h] [rbp-20h]\n\n v14 = __readfsqword(0x28u);\n v2 = strstr(string, a2);\n result = \"entered string isnt a substring\";\n if ( v2 )\n {\n v8 = 0LL;\n v9 = 0LL;\n v10 = 0LL;\n v11 = 0LL;\n v12 = 0LL;\n *(_QWORD *)pattern = 94LL;\n v7 = 0LL;\n v13 = 0;\n __strcpy_chk(&pattern[1], a2, 99LL);\n regcomp(&v5, pattern, 0);\n v4 = regexec(&v5, string, 0LL, 0LL, 0);\n regfree(&v5);\n result = \"string doesnt start with the given substring\";\n if ( !v4 )\n return \"string starts with the given substring\";\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1310(char *string, const char *a2) {\n char *v2;\n const char *result;\n int v4;\n regex_t v5;\n char pattern[8];\n long long v7;\n __int128 v8;\n __int128 v9;\n __int128 v10;\n __int128 v11;\n __int128 v12;\n int v13;\n unsigned long long v14;\n v14 = __readfsqword(40u);\n v2 = strstr(string, a2);\n result = \"entered string isnt a substring\";\n if (v2) {\n v8 = 0LL;\n v9 = 0LL;\n v10 = 0LL;\n v11 = 0LL;\n v12 = 0LL;\n *(uint64_t *)pattern = 94LL;\n v7 = 0LL;\n v13 = 0;\n __strcpy_chk(&pattern[1], a2, 99LL);\n regcomp(&v5, pattern, 0);\n v4 = regexec(&v5, string, 0LL, 0LL, 0);\n regfree(&v5);\n result = \"string doesnt start with the given substring\";\n if (!v4) return \"string starts with the given substring\";\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string, const char *a2) {\n char *v2;\n const char *result;\n int v4;\n regex_t v5;\n char pattern[8];\n long long v7;\n __int128 v8;\n __int128 v9;\n __int128 v10;\n __int128 v11;\n __int128 v12;\n int v13;\n unsigned long long v14;\n v14 = __readfsqword(40u);\n v2 = strstr(string, a2);\n result = \"entered string isnt a substring\";\n if (v2) {\n v8 = 0LL;\n v9 = 0LL;\n v10 = 0LL;\n v11 = 0LL;\n v12 = 0LL;\n *(uint64_t *)pattern = 94LL;\n v7 = 0LL;\n v13 = 0;\n __strcpy_chk(&pattern[1], a2, 99LL);\n regcomp(&v5, pattern, 0);\n v4 = regexec(&v5, string, 0LL, 0LL, 0);\n regfree(&v5);\n result = \"string doesnt start with the given substring\";\n if (!v4) return \"string starts with the given substring\";\n }\n return result;\n}" + }, + { + "index": 824, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int *l, int len, int **out, int *out_len) {\n int i, j = 0;\n *out = (int *)malloc(len * sizeof(int));\n for (i = 0; i < len; i++) {\n if (l[i] % 2 != 0) {\n (*out)[j++] = l[i];\n }\n }\n *out_len = j;\n}", + "test": "int main() {\n\n int arr1[] = {1,3,5,2}, arr2[] = {5,6,7}, arr3[] = {1,2,3,4};\n\n int *res;\n\n int res_len;\n\n\n\n func0(arr1, 4, &res, &res_len);\n\n assert(res_len == 3 && res[0] == 1 && res[1] == 3 && res[2] == 5);\n\n free(res);\n\n\n\n func0(arr2, 3, &res, &res_len);\n\n assert(res_len == 2 && res[0] == 5 && res[1] == 7);\n\n free(res);\n\n\n\n func0(arr3, 4, &res, &res_len);\n\n assert(res_len == 2 && res[0] == 1 && res[1] == 3);\n\n free(res);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %rcx,-0x30(%rbp)\nmovl $0x0,-0x4(%rbp)\nmov -0x1c(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,%rdx\nmov -0x28(%rbp),%rax\nmov %rdx,(%rax)\nmovl $0x0,-0x8(%rbp)\njmp 1243 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nand $0x1,%eax\ntest %eax,%eax\nje 123f \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x28(%rbp),%rax\nmov (%rax),%rsi\nmov -0x4(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x4(%rbp)\ncltq\nshl $0x2,%rax\nlea (%rsi,%rax,1),%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11ef \nmov -0x30(%rbp),%rax\nmov -0x4(%rbp),%edx\nmov %edx,(%rax)\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_30], rcx\nmov [rbp+var_4], 0\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov rdx, rax\nmov rax, [rbp+var_28]\nmov [rax], rdx\nmov [rbp+var_8], 0\njmp short loc_1243\nloc_11EF:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njz short loc_123F\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov rax, [rbp+var_28]\nmov rsi, [rax]\nmov eax, [rbp+var_4]\nlea edx, [rax+1]\nmov [rbp+var_4], edx\ncdqe\nshl rax, 2\nlea rdx, [rsi+rax]\nmov eax, [rcx]\nmov [rdx], eax\nloc_123F:\nadd [rbp+var_8], 1\nloc_1243:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_11EF\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_4]\nmov [rax], edx\nnop\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, void **a3, _DWORD *a4)\n{\n int v4; // eax\n _DWORD *result; // rax\n int i; // [rsp+28h] [rbp-8h]\n int v9; // [rsp+2Ch] [rbp-4h]\n\n v9 = 0;\n *a3 = malloc(4LL * a2);\n for ( i = 0; i < a2; ++i )\n {\n if ( (*(_DWORD *)(4LL * i + a1) & 1) != 0 )\n {\n v4 = v9++;\n *((_DWORD *)*a3 + v4) = *(_DWORD *)(4LL * i + a1);\n }\n }\n result = a4;\n *a4 = v9;\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_30], rcx\nmov [rbp+var_4], 0\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov rdx, rax\nmov rax, [rbp+var_28]\nmov [rax], rdx\nmov [rbp+var_8], 0\njmp short loc_1243\nloc_11EF:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njz short loc_123F\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov rax, [rbp+var_28]\nmov rsi, [rax]\nmov eax, [rbp+var_4]\nlea edx, [rax+1]\nmov [rbp+var_4], edx\ncdqe\nshl rax, 2\nlea rdx, [rsi+rax]\nmov eax, [rcx]\nmov [rdx], eax\nloc_123F:\nadd [rbp+var_8], 1\nloc_1243:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_11EF\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_4]\nmov [rax], edx\nnop\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(__int64 a1, int a2, void **a3, _DWORD *a4)\n{\n int v4; // eax\n _DWORD *result; // rax\n int i; // [rsp+28h] [rbp-8h]\n int v9; // [rsp+2Ch] [rbp-4h]\n\n v9 = 0;\n *a3 = malloc(4LL * a2);\n for ( i = 0; i < a2; ++i )\n {\n if ( (*(_DWORD *)(4LL * i + a1) & 1) != 0 )\n {\n v4 = v9++;\n *((_DWORD *)*a3 + v4) = *(_DWORD *)(4LL * i + a1);\n }\n }\n result = a4;\n *a4 = v9;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(long long a1, int a2, void **a3, uint32_t *a4) {\n int v4;\n uint32_t *result;\n int i;\n int v9;\n v9 = 0;\n *a3 = malloc(4LL * a2);\n for (i = 0; i < a2; ++i) {\n if ((*(uint32_t *)(4LL * i + a1) & 1) != 0) {\n v4 = v9++;\n *((uint32_t *)*a3 + v4) = *(uint32_t *)(4LL * i + a1);\n }\n }\n result = a4;\n *a4 = v9;\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, void **a3, uint32_t *a4) {\n int v4;\n uint32_t *result;\n int i;\n int v9;\n v9 = 0;\n *a3 = malloc(4LL * a2);\n for (i = 0; i < a2; ++i) {\n if ((*(uint32_t *)(4LL * i + a1) & 1) != 0) {\n v4 = v9++;\n *((uint32_t *)*a3 + v4) = *(uint32_t *)(4LL * i + a1);\n }\n }\n result = a4;\n *a4 = v9;\n return result;\n}" + }, + { + "index": 824, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int *l, int len, int **out, int *out_len) {\n int i, j = 0;\n *out = (int *)malloc(len * sizeof(int));\n for (i = 0; i < len; i++) {\n if (l[i] % 2 != 0) {\n (*out)[j++] = l[i];\n }\n }\n *out_len = j;\n}", + "test": "int main() {\n\n int arr1[] = {1,3,5,2}, arr2[] = {5,6,7}, arr3[] = {1,2,3,4};\n\n int *res;\n\n int res_len;\n\n\n\n func0(arr1, 4, &res, &res_len);\n\n assert(res_len == 3 && res[0] == 1 && res[1] == 3 && res[2] == 5);\n\n free(res);\n\n\n\n func0(arr2, 3, &res, &res_len);\n\n assert(res_len == 2 && res[0] == 5 && res[1] == 7);\n\n free(res);\n\n\n\n func0(arr3, 4, &res, &res_len);\n\n assert(res_len == 2 && res[0] == 1 && res[1] == 3);\n\n free(res);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%r13\nmov %esi,%r12d\nmov %rdx,%rbx\nmov %rcx,%rbp\nmovslq %esi,%rdi\nshl $0x2,%rdi\ncallq 10b0 \nmov %rax,(%rbx)\ntest %r12d,%r12d\njle 120a \nmov %r13,%rax\nlea -0x1(%r12),%edx\nlea 0x4(%r13,%rdx,4),%rsi\nmov $0x0,%ecx\njmp 11f4 \nadd $0x4,%rax\ncmp %rsi,%rax\nje 120f \nmov (%rax),%edx\ntest $0x1,%dl\nje 11eb \nmovslq %ecx,%r8\nmov (%rbx),%rdi\nmov %edx,(%rdi,%r8,4)\nlea 0x1(%rcx),%ecx\njmp 11eb \nmov $0x0,%ecx\nmov %ecx,0x0(%rbp)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r12, rdi\nmov r13d, esi\nmov rbx, rdx\nmov rbp, rcx\nmovsxd r14, esi\nshl r14, 2\nmov rdi, r14; size\ncall _malloc\nmov [rbx], rax\ntest r13d, r13d\njle short loc_1205\nmov rax, r12\nlea rsi, [r12+r14]\nmov ecx, 0\njmp short loc_11EF\nloc_11E6:\nadd rax, 4\ncmp rax, rsi\njz short loc_120A\nloc_11EF:\nmov edx, [rax]\ntest dl, 1\njz short loc_11E6\nmovsxd r8, ecx\nmov rdi, [rbx]\nmov [rdi+r8*4], edx\nlea ecx, [rcx+1]\njmp short loc_11E6\nloc_1205:\nmov ecx, 0\nloc_120A:\nmov [rbp+0], ecx\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(_DWORD *a1, int a2, _QWORD *a3, _DWORD *a4)\n{\n _DWORD *result; // rax\n int v7; // ecx\n\n result = malloc(4LL * a2);\n *a3 = result;\n if ( a2 <= 0 )\n {\n v7 = 0;\n }\n else\n {\n result = a1;\n v7 = 0;\n do\n {\n if ( (*result & 1) != 0 )\n *(_DWORD *)(*a3 + 4LL * v7++) = *result;\n ++result;\n }\n while ( result != &a1[a2] );\n }\n *a4 = v7;\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r12, rdi\nmov r13d, esi\nmov rbx, rdx\nmov rbp, rcx\nmovsxd r14, esi\nshl r14, 2\nmov rdi, r14; size\ncall _malloc\nmov [rbx], rax\ntest r13d, r13d\njle short loc_1205\nmov rax, r12\nlea rsi, [r12+r14]\nmov ecx, 0\njmp short loc_11EF\nloc_11E6:\nadd rax, 4\ncmp rax, rsi\njz short loc_120A\nloc_11EF:\nmov edx, [rax]\ntest dl, 1\njz short loc_11E6\nmovsxd r8, ecx\nmov rdi, [rbx]\nmov [rdi+r8*4], edx\nlea ecx, [rcx+1]\njmp short loc_11E6\nloc_1205:\nmov ecx, 0\nloc_120A:\nmov [rbp+0], ecx\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(_DWORD *a1, int a2, _QWORD *a3, _DWORD *a4)\n{\n _DWORD *result; // rax\n int v7; // ecx\n\n result = malloc(4LL * a2);\n *a3 = result;\n if ( a2 <= 0 )\n {\n v7 = 0;\n }\n else\n {\n result = a1;\n v7 = 0;\n do\n {\n if ( (*result & 1) != 0 )\n *(_DWORD *)(*a3 + 4LL * v7++) = *result;\n ++result;\n }\n while ( result != &a1[a2] );\n }\n *a4 = v7;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(uint32_t *a1, int a2, uint64_t *a3, uint32_t *a4) {\n uint32_t *result;\n int v7;\n result = malloc(4LL * a2);\n *a3 = result;\n if (a2 <= 0) {\n v7 = 0;\n } else {\n result = a1;\n v7 = 0;\n do {\n if ((*result & 1) != 0) *(uint32_t *)(*a3 + 4LL * v7++) = *result;\n ++result;\n } while (result != &a1[a2]);\n }\n *a4 = v7;\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(uint32_t *a1, int a2, uint64_t *a3, uint32_t *a4) {\n uint32_t *result;\n int v7;\n result = malloc(4LL * a2);\n *a3 = result;\n if (a2 <= 0) {\n v7 = 0;\n } else {\n result = a1;\n v7 = 0;\n do {\n if ((*result & 1) != 0) *(uint32_t *)(*a3 + 4LL * v7++) = *result;\n ++result;\n } while (result != &a1[a2]);\n }\n *a4 = v7;\n return result;\n}" + }, + { + "index": 824, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int *l, int len, int **out, int *out_len) {\n int i, j = 0;\n *out = (int *)malloc(len * sizeof(int));\n for (i = 0; i < len; i++) {\n if (l[i] % 2 != 0) {\n (*out)[j++] = l[i];\n }\n }\n *out_len = j;\n}", + "test": "int main() {\n\n int arr1[] = {1,3,5,2}, arr2[] = {5,6,7}, arr3[] = {1,2,3,4};\n\n int *res;\n\n int res_len;\n\n\n\n func0(arr1, 4, &res, &res_len);\n\n assert(res_len == 3 && res[0] == 1 && res[1] == 3 && res[2] == 5);\n\n free(res);\n\n\n\n func0(arr2, 3, &res, &res_len);\n\n assert(res_len == 2 && res[0] == 5 && res[1] == 7);\n\n free(res);\n\n\n\n func0(arr3, 4, &res, &res_len);\n\n assert(res_len == 2 && res[0] == 1 && res[1] == 3);\n\n free(res);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov %rdx,%r13\npush %r12\nmov %rcx,%r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nmovslq %esi,%rdi\nmov %rdi,%rbp\nshl $0x2,%rdi\nsub $0x8,%rsp\ncallq 10b0 \nmov %rax,0x0(%r13)\ntest %ebp,%ebp\njle 13d0 \nlea -0x1(%rbp),%edx\nmov %rbx,%rdi\nxor %esi,%esi\nlea 0x4(%rbx,%rdx,4),%r8\nnopl 0x0(%rax,%rax,1)\nmov (%rdi),%edx\ntest $0x1,%dl\nje 13b1 \nmovslq %esi,%r9\nadd $0x1,%esi\nmov %edx,(%rax,%r9,4)\nadd $0x4,%rdi\ncmp %r8,%rdi\njne 13a0 \nmov %esi,(%r12)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax)\nxor %esi,%esi\nmov %esi,(%r12)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\nmovsxd r8, esi\nmov r14, rdx\npush r13\nmov r13, rcx\npush r12\nmov r12, r8\npush rbp\nlea rbp, ds:0[r8*4]\npush rbx\nmov rbx, rdi\nmov rdi, rbp; size\ncall _malloc\nmov [r14], rax\ntest r12d, r12d\njle short loc_13B0\nmov rdx, rbx\nlea r8, [rbx+rbp]\nxor edi, edi\nnop dword ptr [rax+00h]\nloc_1380:\nmov esi, [rdx]\ntest sil, 1\njz short loc_1392\nmovsxd r9, edi\nadd edi, 1\nmov [rax+r9*4], esi\nloc_1392:\nadd rdx, 4\ncmp rdx, r8\njnz short loc_1380\nmov [r13+0], edi\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_13B0:\nxor edi, edi\nmov [r13+0], edi\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(_DWORD *a1, int a2, _QWORD *a3, _DWORD *a4)\n{\n _DWORD *result; // rax\n _DWORD *v8; // rdx\n int v9; // edi\n __int64 v10; // r9\n\n result = malloc(4LL * a2);\n *a3 = result;\n if ( a2 <= 0 )\n {\n *a4 = 0;\n }\n else\n {\n v8 = a1;\n v9 = 0;\n do\n {\n if ( (*v8 & 1) != 0 )\n {\n v10 = v9++;\n result[v10] = *v8;\n }\n ++v8;\n }\n while ( v8 != &a1[a2] );\n *a4 = v9;\n }\n return result;\n}", + "ida_strip_asm": "sub_1340:\nendbr64\npush r14\nmovsxd r8, esi\nmov r14, rdx\npush r13\nmov r13, rcx\npush r12\nmov r12, r8\npush rbp\nlea rbp, ds:0[r8*4]\npush rbx\nmov rbx, rdi\nmov rdi, rbp; size\ncall _malloc\nmov [r14], rax\ntest r12d, r12d\njle short loc_13B0\nmov rdx, rbx\nlea r8, [rbx+rbp]\nxor edi, edi\nnop dword ptr [rax+00h]\nloc_1380:\nmov esi, [rdx]\ntest sil, 1\njz short loc_1392\nmovsxd r9, edi\nadd edi, 1\nmov [rax+r9*4], esi\nloc_1392:\nadd rdx, 4\ncmp rdx, r8\njnz short loc_1380\nmov [r13+0], edi\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_13B0:\nxor edi, edi\nmov [r13+0], edi\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1340(_DWORD *a1, int a2, _QWORD *a3, _DWORD *a4)\n{\n _DWORD *result; // rax\n _DWORD *v8; // rdx\n int v9; // edi\n __int64 v10; // r9\n\n result = malloc(4LL * a2);\n *a3 = result;\n if ( a2 <= 0 )\n {\n *a4 = 0;\n }\n else\n {\n v8 = a1;\n v9 = 0;\n do\n {\n if ( (*v8 & 1) != 0 )\n {\n v10 = v9++;\n result[v10] = *v8;\n }\n ++v8;\n }\n while ( v8 != &a1[a2] );\n *a4 = v9;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1340(uint32_t *a1, int a2, uint64_t *a3, uint32_t *a4) {\n uint32_t *result;\n uint32_t *v8;\n int v9;\n long long v10;\n result = malloc(4LL * a2);\n *a3 = result;\n if (a2 <= 0) {\n *a4 = 0;\n } else {\n v8 = a1;\n v9 = 0;\n do {\n if ((*v8 & 1) != 0) {\n v10 = v9++;\n result[v10] = *v8;\n }\n ++v8;\n } while (v8 != &a1[a2]);\n *a4 = v9;\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(uint32_t *a1, int a2, uint64_t *a3, uint32_t *a4) {\n uint32_t *result;\n uint32_t *v8;\n int v9;\n long long v10;\n result = malloc(4LL * a2);\n *a3 = result;\n if (a2 <= 0) {\n *a4 = 0;\n } else {\n v8 = a1;\n v9 = 0;\n do {\n if ((*v8 & 1) != 0) {\n v10 = v9++;\n result[v10] = *v8;\n }\n ++v8;\n } while (v8 != &a1[a2]);\n *a4 = v9;\n }\n return result;\n}" + }, + { + "index": 824, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int *l, int len, int **out, int *out_len) {\n int i, j = 0;\n *out = (int *)malloc(len * sizeof(int));\n for (i = 0; i < len; i++) {\n if (l[i] % 2 != 0) {\n (*out)[j++] = l[i];\n }\n }\n *out_len = j;\n}", + "test": "int main() {\n\n int arr1[] = {1,3,5,2}, arr2[] = {5,6,7}, arr3[] = {1,2,3,4};\n\n int *res;\n\n int res_len;\n\n\n\n func0(arr1, 4, &res, &res_len);\n\n assert(res_len == 3 && res[0] == 1 && res[1] == 3 && res[2] == 5);\n\n free(res);\n\n\n\n func0(arr2, 3, &res, &res_len);\n\n assert(res_len == 2 && res[0] == 5 && res[1] == 7);\n\n free(res);\n\n\n\n func0(arr3, 4, &res, &res_len);\n\n assert(res_len == 2 && res[0] == 1 && res[1] == 3);\n\n free(res);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov %rdx,%r13\npush %r12\nmov %rcx,%r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nmovslq %esi,%rdi\nmov %rdi,%rbp\nshl $0x2,%rdi\nsub $0x8,%rsp\ncallq 10b0 \nmov %rax,0x0(%r13)\ntest %ebp,%ebp\njle 13b0 \nlea -0x1(%rbp),%edx\nmov %rbx,%rdi\nxor %esi,%esi\nlea 0x4(%rbx,%rdx,4),%r8\nnopl 0x0(%rax,%rax,1)\nmov (%rdi),%edx\ntest $0x1,%dl\nje 1391 \nmovslq %esi,%r9\nadd $0x1,%esi\nmov %edx,(%rax,%r9,4)\nadd $0x4,%rdi\ncmp %r8,%rdi\njne 1380 \nmov %esi,(%r12)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax)\nxor %esi,%esi\nmov %esi,(%r12)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\nmovsxd r8, esi\nmov r14, rdx\npush r13\nmov r13, rcx\npush r12\nmov r12, r8\npush rbp\nlea rbp, ds:0[r8*4]\npush rbx\nmov rbx, rdi\nmov rdi, rbp; size\ncall _malloc\nmov [r14], rax\ntest r12d, r12d\njle short loc_13B0\nmov rdx, rbx\nlea r8, [rbx+rbp]\nxor edi, edi\nnop dword ptr [rax+00h]\nloc_1380:\nmov esi, [rdx]\ntest sil, 1\njz short loc_1392\nmovsxd r9, edi\nadd edi, 1\nmov [rax+r9*4], esi\nloc_1392:\nadd rdx, 4\ncmp rdx, r8\njnz short loc_1380\nmov [r13+0], edi\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_13B0:\nxor edi, edi\nmov [r13+0], edi\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(_DWORD *a1, int a2, _QWORD *a3, _DWORD *a4)\n{\n _DWORD *result; // rax\n _DWORD *v8; // rdx\n int v9; // edi\n __int64 v10; // r9\n\n result = malloc(4LL * a2);\n *a3 = result;\n if ( a2 <= 0 )\n {\n *a4 = 0;\n }\n else\n {\n v8 = a1;\n v9 = 0;\n do\n {\n if ( (*v8 & 1) != 0 )\n {\n v10 = v9++;\n result[v10] = *v8;\n }\n ++v8;\n }\n while ( v8 != &a1[a2] );\n *a4 = v9;\n }\n return result;\n}", + "ida_strip_asm": "sub_1340:\nendbr64\npush r14\nmovsxd r8, esi\nmov r14, rdx\npush r13\nmov r13, rcx\npush r12\nmov r12, r8\npush rbp\nlea rbp, ds:0[r8*4]\npush rbx\nmov rbx, rdi\nmov rdi, rbp; size\ncall _malloc\nmov [r14], rax\ntest r12d, r12d\njle short loc_13B0\nmov rdx, rbx\nlea r8, [rbx+rbp]\nxor edi, edi\nnop dword ptr [rax+00h]\nloc_1380:\nmov esi, [rdx]\ntest sil, 1\njz short loc_1392\nmovsxd r9, edi\nadd edi, 1\nmov [rax+r9*4], esi\nloc_1392:\nadd rdx, 4\ncmp rdx, r8\njnz short loc_1380\nmov [r13+0], edi\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_13B0:\nxor edi, edi\nmov [r13+0], edi\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1340(_DWORD *a1, int a2, _QWORD *a3, _DWORD *a4)\n{\n _DWORD *result; // rax\n _DWORD *v8; // rdx\n int v9; // edi\n __int64 v10; // r9\n\n result = malloc(4LL * a2);\n *a3 = result;\n if ( a2 <= 0 )\n {\n *a4 = 0;\n }\n else\n {\n v8 = a1;\n v9 = 0;\n do\n {\n if ( (*v8 & 1) != 0 )\n {\n v10 = v9++;\n result[v10] = *v8;\n }\n ++v8;\n }\n while ( v8 != &a1[a2] );\n *a4 = v9;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1340(uint32_t *a1, int a2, uint64_t *a3, uint32_t *a4) {\n uint32_t *result;\n uint32_t *v8;\n int v9;\n long long v10;\n result = malloc(4LL * a2);\n *a3 = result;\n if (a2 <= 0) {\n *a4 = 0;\n } else {\n v8 = a1;\n v9 = 0;\n do {\n if ((*v8 & 1) != 0) {\n v10 = v9++;\n result[v10] = *v8;\n }\n ++v8;\n } while (v8 != &a1[a2]);\n *a4 = v9;\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(uint32_t *a1, int a2, uint64_t *a3, uint32_t *a4) {\n uint32_t *result;\n uint32_t *v8;\n int v9;\n long long v10;\n result = malloc(4LL * a2);\n *a3 = result;\n if (a2 <= 0) {\n *a4 = 0;\n } else {\n v8 = a1;\n v9 = 0;\n do {\n if ((*v8 & 1) != 0) {\n v10 = v9++;\n result[v10] = *v8;\n }\n ++v8;\n } while (v8 != &a1[a2]);\n *a4 = v9;\n }\n return result;\n}" + }, + { + "index": 825, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int nums[], int num_size, int list_index[], int index_size,\n int* result_size) {\n static int result[100];\n for (int i = 0; i < index_size; i++) {\n result[i] = nums[list_index[i]];\n }\n *result_size = index_size;\n return result;\n}", + "test": "int main() {\n\n int result_size;\n\n int *result;\n\n\n\n result = func0((int[]){2,3,8,4,7,9}, 6, (int[]){0,3,5}, 3, &result_size);\n\n assert(result_size == 3 && result[0] == 2 && result[1] == 4 && result[2] == 9);\n\n\n\n result = func0((int[]){1, 2, 3, 4, 5}, 5, (int[]){1, 2}, 2, &result_size);\n\n assert(result_size == 2 && result[0] == 2 && result[1] == 3);\n\n \n\n result = func0((int[]){1,0,2,3}, 4, (int[]){0, 1}, 2, &result_size);\n\n assert(result_size == 2 && result[0] == 1 && result[1] == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %ecx,-0x20(%rbp)\nmov %r8,-0x30(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11d1 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov -0x4(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nlea 0x2e76(%rip),%rdx\nmov %eax,(%rcx,%rdx,1)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x20(%rbp),%eax\njl 118c \nmov -0x30(%rbp),%rax\nmov -0x20(%rbp),%edx\nmov %edx,(%rax)\nlea 0x2e57(%rip),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov [rbp+var_30], r8\nmov [rbp+var_4], 0\njmp short loc_11D1\nloc_118C:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nlea rdx, result_1\nmov [rcx+rdx], eax\nadd [rbp+var_4], 1\nloc_11D1:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_20]\njl short loc_118C\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_20]\nmov [rax], edx\nlea rax, result_1\npop rbp\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, __int64 a2, __int64 a3, int a4, _DWORD *a5)\n{\n int i; // [rsp+2Ch] [rbp-4h]\n\n for ( i = 0; i < a4; ++i )\n result_1[i] = *(_DWORD *)(4LL * *(int *)(4LL * i + a3) + a1);\n *a5 = a4;\n return result_1;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov [rbp+var_30], r8\nmov [rbp+var_4], 0\njmp short loc_11D1\nloc_118C:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nlea rdx, unk_4040\nmov [rcx+rdx], eax\nadd [rbp+var_4], 1\nloc_11D1:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_20]\njl short loc_118C\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_20]\nmov [rax], edx\nlea rax, unk_4040\npop rbp\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1169(__int64 a1, __int64 a2, __int64 a3, int a4, _DWORD *a5)\n{\n int i; // [rsp+2Ch] [rbp-4h]\n\n for ( i = 0; i < a4; ++i )\n dword_4040[i] = *(_DWORD *)(4LL * *(int *)(4LL * i + a3) + a1);\n *a5 = a4;\n return dword_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1169(long long a1, long long a2, long long a3, int a4,\n uint32_t *a5) {\n int i;\n for (i = 0; i < a4; ++i)\n dword_4040[i] = *(uint32_t *)(4LL * *(int *)(4LL * i + a3) + a1);\n *a5 = a4;\n return dword_4040;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, long long a2, long long a3, int a4,\n uint32_t *a5) {\n int i;\n for (i = 0; i < a4; ++i)\n result_1[i] = *(uint32_t *)(4LL * *(int *)(4LL * i + a3) + a1);\n *a5 = a4;\n return result_1;\n}" + }, + { + "index": 825, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int nums[], int num_size, int list_index[], int index_size,\n int* result_size) {\n static int result[100];\n for (int i = 0; i < index_size; i++) {\n result[i] = nums[list_index[i]];\n }\n *result_size = index_size;\n return result;\n}", + "test": "int main() {\n\n int result_size;\n\n int *result;\n\n\n\n result = func0((int[]){2,3,8,4,7,9}, 6, (int[]){0,3,5}, 3, &result_size);\n\n assert(result_size == 3 && result[0] == 2 && result[1] == 4 && result[2] == 9);\n\n\n\n result = func0((int[]){1, 2, 3, 4, 5}, 5, (int[]){1, 2}, 2, &result_size);\n\n assert(result_size == 2 && result[0] == 2 && result[1] == 3);\n\n \n\n result = func0((int[]){1,0,2,3}, 4, (int[]){0, 1}, 2, &result_size);\n\n assert(result_size == 2 && result[0] == 1 && result[1] == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %ecx,%ecx\njle 1198 \nlea -0x1(%rcx),%r10d\nmov $0x0,%eax\nlea 0x2ebf(%rip),%r9\nmovslq (%rdx,%rax,4),%rsi\nmov (%rdi,%rsi,4),%esi\nmov %esi,(%r9,%rax,4)\nmov %rax,%rsi\nadd $0x1,%rax\ncmp %r10,%rsi\njne 1181 \nmov %ecx,(%r8)\nlea 0x2e9e(%rip),%rax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest ecx, ecx\njle short loc_1198\nmovsxd r9, ecx\nshl r9, 2\nmov eax, 0\nlea r10, result_1\nloc_1184:\nmovsxd rsi, dword ptr [rdx+rax]\nmov esi, [rdi+rsi*4]\nmov [r10+rax], esi\nadd rax, 4\ncmp rax, r9\njnz short loc_1184\nloc_1198:\nmov [r8], ecx\nlea rax, result_1\nretn", + "ida_pseudo": "void *__fastcall func0(__int64 a1, __int64 a2, __int64 a3, int a4, int *a5)\n{\n __int64 v5; // rax\n\n if ( a4 > 0 )\n {\n v5 = 0LL;\n do\n {\n *(_DWORD *)((char *)&result_1 + v5) = *(_DWORD *)(a1 + 4LL * *(int *)(a3 + v5));\n v5 += 4LL;\n }\n while ( v5 != 4LL * a4 );\n }\n *a5 = a4;\n return &result_1;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest ecx, ecx\njle short loc_1198\nmovsxd r9, ecx\nshl r9, 2\nmov eax, 0\nlea r10, unk_4040\nloc_1184:\nmovsxd rsi, dword ptr [rdx+rax]\nmov esi, [rdi+rsi*4]\nmov [r10+rax], esi\nadd rax, 4\ncmp rax, r9\njnz short loc_1184\nloc_1198:\nmov [r8], ecx\nlea rax, unk_4040\nretn", + "ida_strip_pseudo": "void *__fastcall sub_1169(__int64 a1, __int64 a2, __int64 a3, int a4, int *a5)\n{\n __int64 v5; // rax\n\n if ( a4 > 0 )\n {\n v5 = 0LL;\n do\n {\n *(_DWORD *)((char *)&unk_4040 + v5) = *(_DWORD *)(a1 + 4LL * *(int *)(a3 + v5));\n v5 += 4LL;\n }\n while ( v5 != 4LL * a4 );\n }\n *a5 = a4;\n return &unk_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1169(long long a1, long long a2, long long a3, int a4, int *a5) {\n long long v5;\n if (a4 > 0) {\n v5 = 0LL;\n do {\n *(uint32_t *)((char *)&unk_4040 + v5) =\n *(uint32_t *)(a1 + 4LL * *(int *)(a3 + v5));\n v5 += 4LL;\n } while (v5 != 4LL * a4);\n }\n *a5 = a4;\n return &unk_4040;\n}", + "ida_pseudo_norm": "void *func0(long long a1, long long a2, long long a3, int a4, int *a5) {\n long long v5;\n if (a4 > 0) {\n v5 = 0LL;\n do {\n *(uint32_t *)((char *)&result_1 + v5) =\n *(uint32_t *)(a1 + 4LL * *(int *)(a3 + v5));\n v5 += 4LL;\n } while (v5 != 4LL * a4);\n }\n *a5 = a4;\n return &result_1;\n}" + }, + { + "index": 826, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(int a, int b, int c) {\n int sqa = pow(a, 2);\n int sqb = pow(b, 2);\n int sqc = pow(c, 2);\n if (sqa == sqb + sqc || sqb == sqa + sqc || sqc == sqa + sqb) {\n return \"Right-angled Triangle\";\n } else if (sqa > sqc + sqb || sqb > sqa + sqc || sqc > sqa + sqb) {\n return \"Obtuse-angled Triangle\";\n } else {\n return \"Acute-angled Triangle\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(1, 2, 3), \"Obtuse-angled Triangle\") == 0);\n\n assert(strcmp(func0(2, 2, 2), \"Acute-angled Triangle\") == 0);\n\n assert(strcmp(func0(1, 0, 1), \"Right-angled Triangle\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov %edx,-0x1c(%rbp)\ncvtsi2sdl -0x14(%rbp),%xmm0\nmovsd 0xf95(%rip),%xmm1\ncallq 1070 \ncvttsd2si %xmm0,%eax\nmov %eax,-0xc(%rbp)\ncvtsi2sdl -0x18(%rbp),%xmm0\nmovsd 0xf7c(%rip),%xmm1\ncallq 1070 \ncvttsd2si %xmm0,%eax\nmov %eax,-0x8(%rbp)\ncvtsi2sdl -0x1c(%rbp),%xmm0\nmovsd 0xf63(%rip),%xmm1\ncallq 1070 \ncvttsd2si %xmm0,%eax\nmov %eax,-0x4(%rbp)\nmov -0x8(%rbp),%edx\nmov -0x4(%rbp),%eax\nadd %edx,%eax\ncmp %eax,-0xc(%rbp)\nje 1210 \nmov -0xc(%rbp),%edx\nmov -0x4(%rbp),%eax\nadd %edx,%eax\ncmp %eax,-0x8(%rbp)\nje 1210 \nmov -0xc(%rbp),%edx\nmov -0x8(%rbp),%eax\nadd %edx,%eax\ncmp %eax,-0x4(%rbp)\njne 1219 \nlea 0xdf1(%rip),%rax\njmp 1250 \nmov -0x4(%rbp),%edx\nmov -0x8(%rbp),%eax\nadd %edx,%eax\ncmp %eax,-0xc(%rbp)\njg 1240 \nmov -0xc(%rbp),%edx\nmov -0x4(%rbp),%eax\nadd %edx,%eax\ncmp %eax,-0x8(%rbp)\njg 1240 \nmov -0xc(%rbp),%edx\nmov -0x8(%rbp),%eax\nadd %edx,%eax\ncmp %eax,-0x4(%rbp)\njle 1249 \nlea 0xdd7(%rip),%rax\njmp 1250 \nlea 0xde5(%rip),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\npxor xmm2, xmm2\ncvtsi2sd xmm2, [rbp+var_14]\nmovq rax, xmm2\nmovsd xmm0, cs:y\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\ncvttsd2si eax, xmm0\nmov [rbp+var_C], eax\npxor xmm3, xmm3\ncvtsi2sd xmm3, [rbp+var_18]\nmovq rax, xmm3\nmovsd xmm0, cs:y\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\ncvttsd2si eax, xmm0\nmov [rbp+var_8], eax\npxor xmm4, xmm4\ncvtsi2sd xmm4, [rbp+var_1C]\nmovq rax, xmm4\nmovsd xmm0, cs:y\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\ncvttsd2si eax, xmm0\nmov [rbp+var_4], eax\nmov edx, [rbp+var_8]\nmov eax, [rbp+var_4]\nadd eax, edx\ncmp [rbp+var_C], eax\njz short loc_1246\nmov edx, [rbp+var_C]\nmov eax, [rbp+var_4]\nadd eax, edx\ncmp [rbp+var_8], eax\njz short loc_1246\nmov edx, [rbp+var_C]\nmov eax, [rbp+var_8]\nadd eax, edx\ncmp [rbp+var_4], eax\njnz short loc_124F\nloc_1246:\nlea rax, aRightAngledTri; \"Right-angled Triangle\"\njmp short locret_1286\nloc_124F:\nmov edx, [rbp+var_4]\nmov eax, [rbp+var_8]\nadd eax, edx\ncmp [rbp+var_C], eax\njg short loc_1276\nmov edx, [rbp+var_C]\nmov eax, [rbp+var_4]\nadd eax, edx\ncmp [rbp+var_8], eax\njg short loc_1276\nmov edx, [rbp+var_C]\nmov eax, [rbp+var_8]\nadd eax, edx\ncmp [rbp+var_4], eax\njle short loc_127F\nloc_1276:\nlea rax, s2; \"Obtuse-angled Triangle\"\njmp short locret_1286\nloc_127F:\nlea rax, aAcuteAngledTri; \"Acute-angled Triangle\"\nlocret_1286:\nleave\nretn", + "ida_pseudo": "const char *__fastcall func0(int a1, int a2, int a3)\n{\n int v5; // [rsp+14h] [rbp-Ch]\n int v6; // [rsp+18h] [rbp-8h]\n int v7; // [rsp+1Ch] [rbp-4h]\n\n v5 = (int)pow((double)a1, 2.0);\n v6 = (int)pow((double)a2, 2.0);\n v7 = (int)pow((double)a3, 2.0);\n if ( v5 == v6 + v7 || v6 == v5 + v7 || v7 == v5 + v6 )\n return \"Right-angled Triangle\";\n if ( v5 <= v7 + v6 && v6 <= v5 + v7 && v7 <= v5 + v6 )\n return \"Acute-angled Triangle\";\n return \"Obtuse-angled Triangle\";\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\npxor xmm2, xmm2\ncvtsi2sd xmm2, [rbp+var_14]\nmovq rax, xmm2\nmovsd xmm0, cs:y\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\ncvttsd2si eax, xmm0\nmov [rbp+var_C], eax\npxor xmm3, xmm3\ncvtsi2sd xmm3, [rbp+var_18]\nmovq rax, xmm3\nmovsd xmm0, cs:y\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\ncvttsd2si eax, xmm0\nmov [rbp+var_8], eax\npxor xmm4, xmm4\ncvtsi2sd xmm4, [rbp+var_1C]\nmovq rax, xmm4\nmovsd xmm0, cs:y\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\ncvttsd2si eax, xmm0\nmov [rbp+var_4], eax\nmov edx, [rbp+var_8]\nmov eax, [rbp+var_4]\nadd eax, edx\ncmp [rbp+var_C], eax\njz short loc_1246\nmov edx, [rbp+var_C]\nmov eax, [rbp+var_4]\nadd eax, edx\ncmp [rbp+var_8], eax\njz short loc_1246\nmov edx, [rbp+var_C]\nmov eax, [rbp+var_8]\nadd eax, edx\ncmp [rbp+var_4], eax\njnz short loc_124F\nloc_1246:\nlea rax, aRightAngledTri; \"Right-angled Triangle\"\njmp short locret_1286\nloc_124F:\nmov edx, [rbp+var_4]\nmov eax, [rbp+var_8]\nadd eax, edx\ncmp [rbp+var_C], eax\njg short loc_1276\nmov edx, [rbp+var_C]\nmov eax, [rbp+var_4]\nadd eax, edx\ncmp [rbp+var_8], eax\njg short loc_1276\nmov edx, [rbp+var_C]\nmov eax, [rbp+var_8]\nadd eax, edx\ncmp [rbp+var_4], eax\njle short loc_127F\nloc_1276:\nlea rax, s2; \"Obtuse-angled Triangle\"\njmp short locret_1286\nloc_127F:\nlea rax, aAcuteAngledTri; \"Acute-angled Triangle\"\nlocret_1286:\nleave\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1189(int a1, int a2, int a3)\n{\n int v5; // [rsp+14h] [rbp-Ch]\n int v6; // [rsp+18h] [rbp-8h]\n int v7; // [rsp+1Ch] [rbp-4h]\n\n v5 = (int)pow((double)a1, 2.0);\n v6 = (int)pow((double)a2, 2.0);\n v7 = (int)pow((double)a3, 2.0);\n if ( v5 == v6 + v7 || v6 == v5 + v7 || v7 == v5 + v6 )\n return \"Right-angled Triangle\";\n if ( v5 <= v7 + v6 && v6 <= v5 + v7 && v7 <= v5 + v6 )\n return \"Acute-angled Triangle\";\n return \"Obtuse-angled Triangle\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char* sub_1189(int a1, int a2, int a3) {\n int v5;\n int v6;\n int v7;\n v5 = (int)pow((double)a1, 2.0);\n v6 = (int)pow((double)a2, 2.0);\n v7 = (int)pow((double)a3, 2.0);\n if (v5 == v6 + v7 || v6 == v5 + v7 || v7 == v5 + v6)\n return \"Right-angled Triangle\";\n if (v5 <= v7 + v6 && v6 <= v5 + v7 && v7 <= v5 + v6)\n return \"Acute-angled Triangle\";\n return \"Obtuse-angled Triangle\";\n}", + "ida_pseudo_norm": "const char* func0(int a1, int a2, int a3) {\n int v5;\n int v6;\n int v7;\n v5 = (int)pow((double)a1, 2.0);\n v6 = (int)pow((double)a2, 2.0);\n v7 = (int)pow((double)a3, 2.0);\n if (v5 == v6 + v7 || v6 == v5 + v7 || v7 == v5 + v6)\n return \"Right-angled Triangle\";\n if (v5 <= v7 + v6 && v6 <= v5 + v7 && v7 <= v5 + v6)\n return \"Acute-angled Triangle\";\n return \"Obtuse-angled Triangle\";\n}" + }, + { + "index": 826, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(int a, int b, int c) {\n int sqa = pow(a, 2);\n int sqb = pow(b, 2);\n int sqc = pow(c, 2);\n if (sqa == sqb + sqc || sqb == sqa + sqc || sqc == sqa + sqb) {\n return \"Right-angled Triangle\";\n } else if (sqa > sqc + sqb || sqb > sqa + sqc || sqc > sqa + sqb) {\n return \"Obtuse-angled Triangle\";\n } else {\n return \"Acute-angled Triangle\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(1, 2, 3), \"Obtuse-angled Triangle\") == 0);\n\n assert(strcmp(func0(2, 2, 2), \"Acute-angled Triangle\") == 0);\n\n assert(strcmp(func0(1, 0, 1), \"Right-angled Triangle\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npxor %xmm0,%xmm0\ncvtsi2sd %edi,%xmm0\nmulsd %xmm0,%xmm0\ncvttsd2si %xmm0,%edi\npxor %xmm0,%xmm0\ncvtsi2sd %esi,%xmm0\nmulsd %xmm0,%xmm0\ncvttsd2si %xmm0,%ecx\npxor %xmm0,%xmm0\ncvtsi2sd %edx,%xmm0\nmulsd %xmm0,%xmm0\ncvttsd2si %xmm0,%eax\nlea (%rcx,%rax,1),%esi\nlea 0xe94(%rip),%rdx\ncmp %edi,%esi\nje 11bf \nlea (%rdi,%rax,1),%r8d\ncmp %ecx,%r8d\nje 11bf \nlea (%rdi,%rcx,1),%r9d\ncmp %eax,%r9d\nje 11bf \ncmp %ecx,%r8d\nsetl %dl\ncmp %eax,%r9d\nsetl %al\nor %al,%dl\njne 11b8 \nlea 0xe7d(%rip),%rdx\ncmp %edi,%esi\njge 11bf \nlea 0xe45(%rip),%rdx\nmov %rdx,%rax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov eax, esi\npxor xmm0, xmm0\ncvtsi2sd xmm0, edi\nmulsd xmm0, xmm0\ncvttsd2si esi, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmulsd xmm0, xmm0\ncvttsd2si ecx, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, edx\nmulsd xmm0, xmm0\ncvttsd2si edx, xmm0\nlea edi, [rcx+rdx]\nlea rax, aRightAngledTri; \"Right-angled Triangle\"\ncmp edi, esi\njz short locret_11E1\nlea r8d, [rsi+rdx]\ncmp r8d, ecx\njz short locret_11E1\nlea r9d, [rsi+rcx]\ncmp r9d, edx\njz short locret_11E1\ncmp r8d, ecx\nsetl al\ncmp r9d, edx\nsetl dl\nor al, dl\njnz short loc_11DA\nlea rax, aAcuteAngledTri; \"Acute-angled Triangle\"\ncmp edi, esi\njge short locret_11E1\nloc_11DA:\nlea rax, s2; \"Obtuse-angled Triangle\"\nlocret_11E1:\nretn", + "ida_pseudo": "const char *__fastcall func0(int a1, int a2, int a3)\n{\n int v4; // esi\n int v5; // ecx\n int v6; // edx\n const char *result; // rax\n\n v4 = (int)((double)a1 * (double)a1);\n v5 = (int)((double)a2 * (double)a2);\n v6 = (int)((double)a3 * (double)a3);\n result = \"Right-angled Triangle\";\n if ( v5 + v6 != v4 && v4 + v6 != v5 && v4 + v5 != v6 )\n {\n if ( v4 + v5 < v6 || v4 + v6 < v5 )\n return \"Obtuse-angled Triangle\";\n result = \"Acute-angled Triangle\";\n if ( v5 + v6 < v4 )\n return \"Obtuse-angled Triangle\";\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov eax, esi\npxor xmm0, xmm0\ncvtsi2sd xmm0, edi\nmulsd xmm0, xmm0\ncvttsd2si esi, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmulsd xmm0, xmm0\ncvttsd2si ecx, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, edx\nmulsd xmm0, xmm0\ncvttsd2si edx, xmm0\nlea edi, [rcx+rdx]\nlea rax, aRightAngledTri; \"Right-angled Triangle\"\ncmp edi, esi\njz short locret_11E1\nlea r8d, [rsi+rdx]\ncmp r8d, ecx\njz short locret_11E1\nlea r9d, [rsi+rcx]\ncmp r9d, edx\njz short locret_11E1\ncmp r8d, ecx\nsetl al\ncmp r9d, edx\nsetl dl\nor al, dl\njnz short loc_11DA\nlea rax, aAcuteAngledTri; \"Acute-angled Triangle\"\ncmp edi, esi\njge short locret_11E1\nloc_11DA:\nlea rax, s2; \"Obtuse-angled Triangle\"\nlocret_11E1:\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1169(int a1, int a2, int a3)\n{\n int v4; // esi\n int v5; // ecx\n int v6; // edx\n const char *result; // rax\n\n v4 = (int)((double)a1 * (double)a1);\n v5 = (int)((double)a2 * (double)a2);\n v6 = (int)((double)a3 * (double)a3);\n result = \"Right-angled Triangle\";\n if ( v5 + v6 != v4 && v4 + v6 != v5 && v4 + v5 != v6 )\n {\n if ( v4 + v5 < v6 || v4 + v6 < v5 )\n return \"Obtuse-angled Triangle\";\n result = \"Acute-angled Triangle\";\n if ( v5 + v6 < v4 )\n return \"Obtuse-angled Triangle\";\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1169(int a1, int a2, int a3) {\n int v4;\n int v5;\n int v6;\n const char *result;\n v4 = (int)((double)a1 * (double)a1);\n v5 = (int)((double)a2 * (double)a2);\n v6 = (int)((double)a3 * (double)a3);\n result = \"Right-angled Triangle\";\n if (v5 + v6 != v4 && v4 + v6 != v5 && v4 + v5 != v6) {\n if (v4 + v5 < v6 || v4 + v6 < v5) return \"Obtuse-angled Triangle\";\n result = \"Acute-angled Triangle\";\n if (v5 + v6 < v4) return \"Obtuse-angled Triangle\";\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(int a1, int a2, int a3) {\n int v4;\n int v5;\n int v6;\n const char *result;\n v4 = (int)((double)a1 * (double)a1);\n v5 = (int)((double)a2 * (double)a2);\n v6 = (int)((double)a3 * (double)a3);\n result = \"Right-angled Triangle\";\n if (v5 + v6 != v4 && v4 + v6 != v5 && v4 + v5 != v6) {\n if (v4 + v5 < v6 || v4 + v6 < v5) return \"Obtuse-angled Triangle\";\n result = \"Acute-angled Triangle\";\n if (v5 + v6 < v4) return \"Obtuse-angled Triangle\";\n }\n return result;\n}" + }, + { + "index": 826, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(int a, int b, int c) {\n int sqa = pow(a, 2);\n int sqb = pow(b, 2);\n int sqc = pow(c, 2);\n if (sqa == sqb + sqc || sqb == sqa + sqc || sqc == sqa + sqb) {\n return \"Right-angled Triangle\";\n } else if (sqa > sqc + sqb || sqb > sqa + sqc || sqc > sqa + sqb) {\n return \"Obtuse-angled Triangle\";\n } else {\n return \"Acute-angled Triangle\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(1, 2, 3), \"Obtuse-angled Triangle\") == 0);\n\n assert(strcmp(func0(2, 2, 2), \"Acute-angled Triangle\") == 0);\n\n assert(strcmp(func0(1, 0, 1), \"Right-angled Triangle\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npxor %xmm0,%xmm0\nmov %edx,%r8d\ncvtsi2sd %edi,%xmm0\nmulsd %xmm0,%xmm0\ncvttsd2si %xmm0,%edx\npxor %xmm0,%xmm0\ncvtsi2sd %esi,%xmm0\nmulsd %xmm0,%xmm0\ncvttsd2si %xmm0,%eax\npxor %xmm0,%xmm0\ncvtsi2sd %r8d,%xmm0\nlea 0xd7d(%rip),%r8\nmulsd %xmm0,%xmm0\ncvttsd2si %xmm0,%ecx\nlea (%rax,%rcx,1),%esi\ncmp %edx,%esi\nje 12c4 \nlea (%rdx,%rcx,1),%edi\ncmp %eax,%edi\nje 12c4 \nlea (%rdx,%rax,1),%r9d\ncmp %ecx,%r9d\nje 12c4 \nsetl %cl\ncmp %eax,%edi\nsetl %al\nor %al,%cl\njne 12bd \nlea 0xd78(%rip),%r8\ncmp %edx,%esi\njge 12c4 \nlea 0xd56(%rip),%r8\nmov %r8,%rax\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npxor xmm0, xmm0\nmov eax, edx\ncvtsi2sd xmm0, edi\nmulsd xmm0, xmm0\ncvttsd2si ecx, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, esi\nlea rsi, aRightAngledTri; \"Right-angled Triangle\"\nmulsd xmm0, xmm0\ncvttsd2si edx, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmulsd xmm0, xmm0\ncvttsd2si eax, xmm0\nlea edi, [rdx+rax]\ncmp edi, ecx\njz short loc_12C8\nlea r8d, [rcx+rax]\ncmp r8d, edx\njz short loc_12C8\nlea r9d, [rcx+rdx]\ncmp r9d, eax\njz short loc_12C8\ncmp r8d, edx\nsetl dl\ncmp r9d, eax\nsetl al\nor dl, al\njnz short loc_12C1\nlea rsi, aAcuteAngledTri; \"Acute-angled Triangle\"\ncmp edi, ecx\njge short loc_12C8\nloc_12C1:\nlea rsi, s2; \"Obtuse-angled Triangle\"\nloc_12C8:\nmov rax, rsi\nretn", + "ida_pseudo": "const char *__fastcall func0(int a1, int a2, int a3)\n{\n int v4; // ecx\n double v5; // xmm0_8\n const char *v6; // rsi\n int v7; // edx\n int v8; // eax\n\n v4 = (int)((double)a1 * (double)a1);\n v5 = (double)a2;\n v6 = \"Right-angled Triangle\";\n v7 = (int)(v5 * v5);\n v8 = (int)((double)a3 * (double)a3);\n if ( v7 + v8 != v4 && v4 + v8 != v7 && v4 + v7 != v8 )\n {\n if ( v4 + v7 < v8 || v4 + v8 < v7 )\n return \"Obtuse-angled Triangle\";\n v6 = \"Acute-angled Triangle\";\n if ( v7 + v8 < v4 )\n return \"Obtuse-angled Triangle\";\n }\n return v6;\n}", + "ida_strip_asm": "sub_1250:\nendbr64\npxor xmm0, xmm0\nmov eax, edx\ncvtsi2sd xmm0, edi\nmulsd xmm0, xmm0\ncvttsd2si ecx, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, esi\nlea rsi, aRightAngledTri; \"Right-angled Triangle\"\nmulsd xmm0, xmm0\ncvttsd2si edx, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmulsd xmm0, xmm0\ncvttsd2si eax, xmm0\nlea edi, [rdx+rax]\ncmp edi, ecx\njz short loc_12C8\nlea r8d, [rcx+rax]\ncmp r8d, edx\njz short loc_12C8\nlea r9d, [rcx+rdx]\ncmp r9d, eax\njz short loc_12C8\ncmp r8d, edx\nsetl dl\ncmp r9d, eax\nsetl al\nor dl, al\njnz short loc_12C1\nlea rsi, aAcuteAngledTri; \"Acute-angled Triangle\"\ncmp edi, ecx\njge short loc_12C8\nloc_12C1:\nlea rsi, s2; \"Obtuse-angled Triangle\"\nloc_12C8:\nmov rax, rsi\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1250(int a1, int a2, int a3)\n{\n int v4; // ecx\n double v5; // xmm0_8\n const char *v6; // rsi\n int v7; // edx\n int v8; // eax\n\n v4 = (int)((double)a1 * (double)a1);\n v5 = (double)a2;\n v6 = \"Right-angled Triangle\";\n v7 = (int)(v5 * v5);\n v8 = (int)((double)a3 * (double)a3);\n if ( v7 + v8 != v4 && v4 + v8 != v7 && v4 + v7 != v8 )\n {\n if ( v4 + v7 < v8 || v4 + v8 < v7 )\n return \"Obtuse-angled Triangle\";\n v6 = \"Acute-angled Triangle\";\n if ( v7 + v8 < v4 )\n return \"Obtuse-angled Triangle\";\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1250(int a1, int a2, int a3) {\n int v4;\n double v5;\n const char *v6;\n int v7;\n int v8;\n v4 = (int)((double)a1 * (double)a1);\n v5 = (double)a2;\n v6 = \"Right-angled Triangle\";\n v7 = (int)(v5 * v5);\n v8 = (int)((double)a3 * (double)a3);\n if (v7 + v8 != v4 && v4 + v8 != v7 && v4 + v7 != v8) {\n if (v4 + v7 < v8 || v4 + v8 < v7) return \"Obtuse-angled Triangle\";\n v6 = \"Acute-angled Triangle\";\n if (v7 + v8 < v4) return \"Obtuse-angled Triangle\";\n }\n return v6;\n}", + "ida_pseudo_norm": "const char *func0(int a1, int a2, int a3) {\n int v4;\n double v5;\n const char *v6;\n int v7;\n int v8;\n v4 = (int)((double)a1 * (double)a1);\n v5 = (double)a2;\n v6 = \"Right-angled Triangle\";\n v7 = (int)(v5 * v5);\n v8 = (int)((double)a3 * (double)a3);\n if (v7 + v8 != v4 && v4 + v8 != v7 && v4 + v7 != v8) {\n if (v4 + v7 < v8 || v4 + v8 < v7) return \"Obtuse-angled Triangle\";\n v6 = \"Acute-angled Triangle\";\n if (v7 + v8 < v4) return \"Obtuse-angled Triangle\";\n }\n return v6;\n}" + }, + { + "index": 826, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(int a, int b, int c) {\n int sqa = pow(a, 2);\n int sqb = pow(b, 2);\n int sqc = pow(c, 2);\n if (sqa == sqb + sqc || sqb == sqa + sqc || sqc == sqa + sqb) {\n return \"Right-angled Triangle\";\n } else if (sqa > sqc + sqb || sqb > sqa + sqc || sqc > sqa + sqb) {\n return \"Obtuse-angled Triangle\";\n } else {\n return \"Acute-angled Triangle\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(1, 2, 3), \"Obtuse-angled Triangle\") == 0);\n\n assert(strcmp(func0(2, 2, 2), \"Acute-angled Triangle\") == 0);\n\n assert(strcmp(func0(1, 0, 1), \"Right-angled Triangle\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npxor %xmm0,%xmm0\nmov %edx,%r8d\ncvtsi2sd %edi,%xmm0\nmulsd %xmm0,%xmm0\ncvttsd2si %xmm0,%edx\npxor %xmm0,%xmm0\ncvtsi2sd %esi,%xmm0\nmulsd %xmm0,%xmm0\ncvttsd2si %xmm0,%eax\npxor %xmm0,%xmm0\ncvtsi2sd %r8d,%xmm0\nlea 0xd7d(%rip),%r8\nmulsd %xmm0,%xmm0\ncvttsd2si %xmm0,%ecx\nlea (%rax,%rcx,1),%esi\ncmp %edx,%esi\nje 12c4 \nlea (%rdx,%rcx,1),%edi\ncmp %eax,%edi\nje 12c4 \nlea (%rdx,%rax,1),%r9d\ncmp %ecx,%r9d\nje 12c4 \nsetl %cl\ncmp %eax,%edi\nsetl %al\nor %al,%cl\njne 12bd \nlea 0xd78(%rip),%r8\ncmp %edx,%esi\njge 12c4 \nlea 0xd56(%rip),%r8\nmov %r8,%rax\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npxor xmm0, xmm0\nmov eax, edx\ncvtsi2sd xmm0, edi\nmulsd xmm0, xmm0\ncvttsd2si ecx, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, esi\nlea rsi, aRightAngledTri; \"Right-angled Triangle\"\nmulsd xmm0, xmm0\ncvttsd2si edx, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmulsd xmm0, xmm0\ncvttsd2si eax, xmm0\nlea edi, [rdx+rax]\ncmp edi, ecx\njz short loc_12C8\nlea r8d, [rcx+rax]\ncmp r8d, edx\njz short loc_12C8\nlea r9d, [rcx+rdx]\ncmp r9d, eax\njz short loc_12C8\ncmp r8d, edx\nsetl dl\ncmp r9d, eax\nsetl al\nor dl, al\njnz short loc_12C1\nlea rsi, aAcuteAngledTri; \"Acute-angled Triangle\"\ncmp edi, ecx\njge short loc_12C8\nloc_12C1:\nlea rsi, s2; \"Obtuse-angled Triangle\"\nloc_12C8:\nmov rax, rsi\nretn", + "ida_pseudo": "const char *__fastcall func0(int a1, int a2, int a3)\n{\n int v4; // ecx\n double v5; // xmm0_8\n const char *v6; // rsi\n int v7; // edx\n int v8; // eax\n\n v4 = (int)((double)a1 * (double)a1);\n v5 = (double)a2;\n v6 = \"Right-angled Triangle\";\n v7 = (int)(v5 * v5);\n v8 = (int)((double)a3 * (double)a3);\n if ( v7 + v8 != v4 && v4 + v8 != v7 && v4 + v7 != v8 )\n {\n if ( v4 + v7 < v8 || v4 + v8 < v7 )\n return \"Obtuse-angled Triangle\";\n v6 = \"Acute-angled Triangle\";\n if ( v7 + v8 < v4 )\n return \"Obtuse-angled Triangle\";\n }\n return v6;\n}", + "ida_strip_asm": "sub_1250:\nendbr64\npxor xmm0, xmm0\nmov eax, edx\ncvtsi2sd xmm0, edi\nmulsd xmm0, xmm0\ncvttsd2si ecx, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, esi\nlea rsi, aRightAngledTri; \"Right-angled Triangle\"\nmulsd xmm0, xmm0\ncvttsd2si edx, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmulsd xmm0, xmm0\ncvttsd2si eax, xmm0\nlea edi, [rdx+rax]\ncmp edi, ecx\njz short loc_12C8\nlea r8d, [rcx+rax]\ncmp r8d, edx\njz short loc_12C8\nlea r9d, [rcx+rdx]\ncmp r9d, eax\njz short loc_12C8\ncmp r8d, edx\nsetl dl\ncmp r9d, eax\nsetl al\nor dl, al\njnz short loc_12C1\nlea rsi, aAcuteAngledTri; \"Acute-angled Triangle\"\ncmp edi, ecx\njge short loc_12C8\nloc_12C1:\nlea rsi, s2; \"Obtuse-angled Triangle\"\nloc_12C8:\nmov rax, rsi\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1250(int a1, int a2, int a3)\n{\n int v4; // ecx\n double v5; // xmm0_8\n const char *v6; // rsi\n int v7; // edx\n int v8; // eax\n\n v4 = (int)((double)a1 * (double)a1);\n v5 = (double)a2;\n v6 = \"Right-angled Triangle\";\n v7 = (int)(v5 * v5);\n v8 = (int)((double)a3 * (double)a3);\n if ( v7 + v8 != v4 && v4 + v8 != v7 && v4 + v7 != v8 )\n {\n if ( v4 + v7 < v8 || v4 + v8 < v7 )\n return \"Obtuse-angled Triangle\";\n v6 = \"Acute-angled Triangle\";\n if ( v7 + v8 < v4 )\n return \"Obtuse-angled Triangle\";\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1250(int a1, int a2, int a3) {\n int v4;\n double v5;\n const char *v6;\n int v7;\n int v8;\n v4 = (int)((double)a1 * (double)a1);\n v5 = (double)a2;\n v6 = \"Right-angled Triangle\";\n v7 = (int)(v5 * v5);\n v8 = (int)((double)a3 * (double)a3);\n if (v7 + v8 != v4 && v4 + v8 != v7 && v4 + v7 != v8) {\n if (v4 + v7 < v8 || v4 + v8 < v7) return \"Obtuse-angled Triangle\";\n v6 = \"Acute-angled Triangle\";\n if (v7 + v8 < v4) return \"Obtuse-angled Triangle\";\n }\n return v6;\n}", + "ida_pseudo_norm": "const char *func0(int a1, int a2, int a3) {\n int v4;\n double v5;\n const char *v6;\n int v7;\n int v8;\n v4 = (int)((double)a1 * (double)a1);\n v5 = (double)a2;\n v6 = \"Right-angled Triangle\";\n v7 = (int)(v5 * v5);\n v8 = (int)((double)a3 * (double)a3);\n if (v7 + v8 != v4 && v4 + v8 != v7 && v4 + v7 != v8) {\n if (v4 + v7 < v8 || v4 + v8 < v7) return \"Obtuse-angled Triangle\";\n v6 = \"Acute-angled Triangle\";\n if (v7 + v8 < v4) return \"Obtuse-angled Triangle\";\n }\n return v6;\n}" + }, + { + "index": 827, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int list1[][4], int rows, int C) {\n int result = 0;\n for (int i = 0; i < rows; i++) {\n result += list1[i][C];\n }\n return result;\n}", + "test": "int main() {\n\n int array1[3][4] = {{1,2,3,2},{4,5,6,2},{7,8,9,5}};\n\n \n\n assert(func0(array1, 3, 0) == 12);\n\n assert(func0(array1, 3, 1) == 15);\n\n assert(func0(array1, 3, 3) == 9);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11ad \nmov -0x4(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0x20(%rbp),%eax\ncltq\nmov (%rdx,%rax,4),%eax\nadd %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 118b \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11AD\nloc_118B:\nmov eax, [rbp+var_4]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_20]\ncdqe\nmov eax, [rdx+rax*4]\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_11AD:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_118B\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n unsigned int v4; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n v4 += *(_DWORD *)(a1 + 16LL * i + 4LL * a3);\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11AD\nloc_118B:\nmov eax, [rbp+var_4]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_20]\ncdqe\nmov eax, [rdx+rax*4]\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_11AD:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_118B\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n unsigned int v4; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n v4 += *(_DWORD *)(a1 + 16LL * i + 4LL * a3);\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n unsigned int v4;\n int i;\n v4 = 0;\n for (i = 0; i < a2; ++i) v4 += *(uint32_t *)(a1 + 16LL * i + 4LL * a3);\n return v4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n unsigned int v4;\n int i;\n v4 = 0;\n for (i = 0; i < a2; ++i) v4 += *(uint32_t *)(a1 + 16LL * i + 4LL * a3);\n return v4;\n}" + }, + { + "index": 827, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int list1[][4], int rows, int C) {\n int result = 0;\n for (int i = 0; i < rows; i++) {\n result += list1[i][C];\n }\n return result;\n}", + "test": "int main() {\n\n int array1[3][4] = {{1,2,3,2},{4,5,6,2},{7,8,9,5}};\n\n \n\n assert(func0(array1, 3, 0) == 12);\n\n assert(func0(array1, 3, 1) == 15);\n\n assert(func0(array1, 3, 3) == 9);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1197 \nmovslq %edx,%rdx\nlea (%rdi,%rdx,4),%rax\nlea -0x1(%rsi),%ecx\nlea (%rdx,%rcx,4),%rdx\nlea 0x10(%rdi,%rdx,4),%rcx\nmov $0x0,%edx\nadd (%rax),%edx\nadd $0x10,%rax\ncmp %rcx,%rax\njne 1189 \nmov %edx,%eax\nretq\nmov $0x0,%edx\njmp 1194 \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1196\nmovsxd rdx, edx\nlea rax, [rdi+rdx*4]\nmovsxd rsi, esi\nlea rdx, [rdx+rsi*4]\nlea rcx, [rdi+rdx*4]\nmov edx, 0\nloc_1188:\nadd edx, [rax]\nadd rax, 10h\ncmp rax, rcx\njnz short loc_1188\nloc_1193:\nmov eax, edx\nretn\nloc_1196:\nmov edx, 0\njmp short loc_1193", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n _DWORD *v3; // rax\n _DWORD *v4; // rcx\n unsigned int v5; // edx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v3 = (_DWORD *)(a1 + 4LL * a3);\n v4 = (_DWORD *)(a1 + 4 * (a3 + 4LL * a2));\n v5 = 0;\n do\n {\n v5 += *v3;\n v3 += 4;\n }\n while ( v3 != v4 );\n }\n return v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_1196\nmovsxd rdx, edx\nlea rax, [rdi+rdx*4]\nmovsxd rsi, esi\nlea rdx, [rdx+rsi*4]\nlea rcx, [rdi+rdx*4]\nmov edx, 0\nloc_1188:\nadd edx, [rax]\nadd rax, 10h\ncmp rax, rcx\njnz short loc_1188\nloc_1193:\nmov eax, edx\nretn\nloc_1196:\nmov edx, 0\njmp short loc_1193", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n _DWORD *v3; // rax\n _DWORD *v4; // rcx\n unsigned int v5; // edx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v3 = (_DWORD *)(a1 + 4LL * a3);\n v4 = (_DWORD *)(a1 + 4 * (a3 + 4LL * a2));\n v5 = 0;\n do\n {\n v5 += *v3;\n v3 += 4;\n }\n while ( v3 != v4 );\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n uint32_t *v3;\n uint32_t *v4;\n unsigned int v5;\n if (a2 <= 0) {\n return 0;\n } else {\n v3 = (uint32_t *)(a1 + 4LL * a3);\n v4 = (uint32_t *)(a1 + 4 * (a3 + 4LL * a2));\n v5 = 0;\n do {\n v5 += *v3;\n v3 += 4;\n } while (v3 != v4);\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n uint32_t *v3;\n uint32_t *v4;\n unsigned int v5;\n if (a2 <= 0) {\n return 0;\n } else {\n v3 = (uint32_t *)(a1 + 4LL * a3);\n v4 = (uint32_t *)(a1 + 4 * (a3 + 4LL * a2));\n v5 = 0;\n do {\n v5 += *v3;\n v3 += 4;\n } while (v3 != v4);\n }\n return v5;\n}" + }, + { + "index": 828, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "void func0(const char* string, int* alphabets, int* digits, int* special) {\n *alphabets = *digits = *special = 0;\n for (int i = 0; string[i] != '\\0'; i++) {\n if (isalpha(string[i]))\n (*alphabets)++;\n else if (isdigit(string[i]))\n (*digits)++;\n else\n (*special)++;\n }\n}", + "test": "int main() {\n\n int alphabets, digits, special;\n\n\n\n func0(\"abc!@#123\", &alphabets, &digits, &special);\n\n assert(alphabets == 3 && digits == 3 && special == 3);\n\n\n\n func0(\"dgsuy@#$%&1255\", &alphabets, &digits, &special);\n\n assert(alphabets == 5 && digits == 4 && special == 5);\n\n\n\n func0(\"fjdsif627348#%$^&\", &alphabets, &digits, &special);\n\n assert(alphabets == 6 && digits == 6 && special == 5);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %rcx,-0x30(%rbp)\nmov -0x30(%rbp),%rax\nmovl $0x0,(%rax)\nmov -0x30(%rbp),%rax\nmov (%rax),%edx\nmov -0x28(%rbp),%rax\nmov %edx,(%rax)\nmov -0x28(%rbp),%rax\nmov (%rax),%edx\nmov -0x20(%rbp),%rax\nmov %edx,(%rax)\nmovl $0x0,-0x4(%rbp)\njmpq 126a \ncallq 1090 <__ctype_b_loc@plt>\nmov (%rax),%rax\nmov -0x4(%rbp),%edx\nmovslq %edx,%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rdx),%edx\nmovsbq %dl,%rdx\nadd %rdx,%rdx\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x400,%eax\ntest %eax,%eax\nje 1215 \nmov -0x20(%rbp),%rax\nmov (%rax),%eax\nlea 0x1(%rax),%edx\nmov -0x20(%rbp),%rax\nmov %edx,(%rax)\njmp 1266 \ncallq 1090 <__ctype_b_loc@plt>\nmov (%rax),%rax\nmov -0x4(%rbp),%edx\nmovslq %edx,%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rdx),%edx\nmovsbq %dl,%rdx\nadd %rdx,%rdx\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x800,%eax\ntest %eax,%eax\nje 1257 \nmov -0x28(%rbp),%rax\nmov (%rax),%eax\nlea 0x1(%rax),%edx\nmov -0x28(%rbp),%rax\nmov %edx,(%rax)\njmp 1266 \nmov -0x30(%rbp),%rax\nmov (%rax),%eax\nlea 0x1(%rax),%edx\nmov -0x30(%rbp),%rax\nmov %edx,(%rax)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 11d3 \nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_28], rdx\nmov [rbp+var_30], rcx\nmov rax, [rbp+var_30]\nmov dword ptr [rax], 0\nmov rax, [rbp+var_30]\nmov edx, [rax]\nmov rax, [rbp+var_28]\nmov [rax], edx\nmov rax, [rbp+var_28]\nmov edx, [rax]\nmov rax, [rbp+var_20]\nmov [rax], edx\nmov [rbp+var_4], 0\njmp loc_126A\nloc_11D3:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_4]\nmovsxd rcx, edx\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 400h\ntest eax, eax\njz short loc_1215\nmov rax, [rbp+var_20]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_20]\nmov [rax], edx\njmp short loc_1266\nloc_1215:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_4]\nmovsxd rcx, edx\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 800h\ntest eax, eax\njz short loc_1257\nmov rax, [rbp+var_28]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_28]\nmov [rax], edx\njmp short loc_1266\nloc_1257:\nmov rax, [rbp+var_30]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_30]\nmov [rax], edx\nloc_1266:\nadd [rbp+var_4], 1\nloc_126A:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_11D3\nnop\nnop\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, _DWORD *a2, _DWORD *a3, _DWORD *a4)\n{\n __int64 result; // rax\n int i; // [rsp+2Ch] [rbp-4h]\n\n *a4 = 0;\n *a3 = *a4;\n *a2 = *a3;\n for ( i = 0; ; ++i )\n {\n result = *(unsigned __int8 *)(i + a1);\n if ( !(_BYTE)result )\n break;\n if ( ((*__ctype_b_loc())[*(char *)(i + a1)] & 0x400) != 0 )\n {\n ++*a2;\n }\n else if ( ((*__ctype_b_loc())[*(char *)(i + a1)] & 0x800) != 0 )\n {\n ++*a3;\n }\n else\n {\n ++*a4;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_28], rdx\nmov [rbp+var_30], rcx\nmov rax, [rbp+var_30]\nmov dword ptr [rax], 0\nmov rax, [rbp+var_30]\nmov edx, [rax]\nmov rax, [rbp+var_28]\nmov [rax], edx\nmov rax, [rbp+var_28]\nmov edx, [rax]\nmov rax, [rbp+var_20]\nmov [rax], edx\nmov [rbp+var_4], 0\njmp loc_126A\nloc_11D3:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_4]\nmovsxd rcx, edx\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 400h\ntest eax, eax\njz short loc_1215\nmov rax, [rbp+var_20]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_20]\nmov [rax], edx\njmp short loc_1266\nloc_1215:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_4]\nmovsxd rcx, edx\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 800h\ntest eax, eax\njz short loc_1257\nmov rax, [rbp+var_28]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_28]\nmov [rax], edx\njmp short loc_1266\nloc_1257:\nmov rax, [rbp+var_30]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_30]\nmov [rax], edx\nloc_1266:\nadd [rbp+var_4], 1\nloc_126A:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_11D3\nnop\nnop\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, _DWORD *a2, _DWORD *a3, _DWORD *a4)\n{\n __int64 result; // rax\n int i; // [rsp+2Ch] [rbp-4h]\n\n *a4 = 0;\n *a3 = *a4;\n *a2 = *a3;\n for ( i = 0; ; ++i )\n {\n result = *(unsigned __int8 *)(i + a1);\n if ( !(_BYTE)result )\n break;\n if ( ((*__ctype_b_loc())[*(char *)(i + a1)] & 0x400) != 0 )\n {\n ++*a2;\n }\n else if ( ((*__ctype_b_loc())[*(char *)(i + a1)] & 0x800) != 0 )\n {\n ++*a3;\n }\n else\n {\n ++*a4;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, uint32_t *a2, uint32_t *a3, uint32_t *a4) {\n long long result;\n int i;\n *a4 = 0;\n *a3 = *a4;\n *a2 = *a3;\n for (i = 0;; ++i) {\n result = *(unsigned char *)(i + a1);\n if (!(uint8_t)result) break;\n if (((*__ctype_b_loc())[*(char *)(i + a1)] & 1024) != 0) {\n ++*a2;\n } else if (((*__ctype_b_loc())[*(char *)(i + a1)] & 2048) != 0) {\n ++*a3;\n } else {\n ++*a4;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, uint32_t *a2, uint32_t *a3, uint32_t *a4) {\n long long result;\n int i;\n *a4 = 0;\n *a3 = *a4;\n *a2 = *a3;\n for (i = 0;; ++i) {\n result = *(unsigned char *)(i + a1);\n if (!(uint8_t)result) break;\n if (((*__ctype_b_loc())[*(char *)(i + a1)] & 1024) != 0) {\n ++*a2;\n } else if (((*__ctype_b_loc())[*(char *)(i + a1)] & 2048) != 0) {\n ++*a3;\n } else {\n ++*a4;\n }\n }\n return result;\n}" + }, + { + "index": 828, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "void func0(const char* string, int* alphabets, int* digits, int* special) {\n *alphabets = *digits = *special = 0;\n for (int i = 0; string[i] != '\\0'; i++) {\n if (isalpha(string[i]))\n (*alphabets)++;\n else if (isdigit(string[i]))\n (*digits)++;\n else\n (*special)++;\n }\n}", + "test": "int main() {\n\n int alphabets, digits, special;\n\n\n\n func0(\"abc!@#123\", &alphabets, &digits, &special);\n\n assert(alphabets == 3 && digits == 3 && special == 3);\n\n\n\n func0(\"dgsuy@#$%&1255\", &alphabets, &digits, &special);\n\n assert(alphabets == 5 && digits == 4 && special == 5);\n\n\n\n func0(\"fjdsif627348#%$^&\", &alphabets, &digits, &special);\n\n assert(alphabets == 6 && digits == 6 && special == 5);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nmovl $0x0,(%rcx)\nmovl $0x0,(%rdx)\nmovl $0x0,(%rsi)\nmovzbl (%rdi),%ebx\ntest %bl,%bl\nje 11f8 \nmov %rdi,%rbp\nmov %rsi,%r12\nmov %rdx,%r13\nmov %rcx,%r14\ncallq 1090 <__ctype_b_loc@plt>\nlea 0x1(%rbp),%rdi\njmp 11db \ntest $0x8,%dh\nje 11f2 \naddl $0x1,0x0(%r13)\nadd $0x1,%rdi\nmovzbl -0x1(%rdi),%ebx\ntest %bl,%bl\nje 11f8 \nmovsbq %bl,%rbx\nmov (%rax),%rdx\nmovzwl (%rdx,%rbx,2),%edx\ntest $0x4,%dh\nje 11c5 \naddl $0x1,(%r12)\njmp 11cf \naddl $0x1,(%r14)\njmp 11cf \npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov dword ptr [rcx], 0\nmov dword ptr [rdx], 0\nmov dword ptr [rsi], 0\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_11F8\nmov rbp, rdi\nmov r12, rsi\nmov r13, rdx\nmov r14, rcx\ncall ___ctype_b_loc\nlea rdx, [rbp+1]\njmp short loc_11DB\nloc_11C5:\ntest ch, 8\njz short loc_11F2\nadd dword ptr [r13+0], 1\nloc_11CF:\nadd rdx, 1\nmovzx ebx, byte ptr [rdx-1]\ntest bl, bl\njz short loc_11F8\nloc_11DB:\nmovsx rbx, bl\nmov rcx, [rax]\nmovzx ecx, word ptr [rcx+rbx*2]\ntest ch, 4\njz short loc_11C5\nadd dword ptr [r12], 1\njmp short loc_11CF\nloc_11F2:\nadd dword ptr [r14], 1\njmp short loc_11CF\nloc_11F8:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "void __fastcall func0(char *a1, _DWORD *a2, _DWORD *a3, _DWORD *a4)\n{\n char v4; // bl\n const unsigned __int16 **v7; // rax\n char *v8; // rdx\n unsigned __int16 v9; // cx\n\n *a4 = 0;\n *a3 = 0;\n *a2 = 0;\n v4 = *a1;\n if ( *a1 )\n {\n v7 = __ctype_b_loc();\n v8 = a1 + 1;\n do\n {\n v9 = (*v7)[v4];\n if ( (v9 & 0x400) != 0 )\n {\n ++*a2;\n }\n else if ( (v9 & 0x800) != 0 )\n {\n ++*a3;\n }\n else\n {\n ++*a4;\n }\n v4 = *v8++;\n }\n while ( v4 );\n }\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov dword ptr [rcx], 0\nmov dword ptr [rdx], 0\nmov dword ptr [rsi], 0\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_11F8\nmov rbp, rdi\nmov r12, rsi\nmov r13, rdx\nmov r14, rcx\ncall ___ctype_b_loc\nlea rdx, [rbp+1]\njmp short loc_11DB\nloc_11C5:\ntest ch, 8\njz short loc_11F2\nadd dword ptr [r13+0], 1\nloc_11CF:\nadd rdx, 1\nmovzx ebx, byte ptr [rdx-1]\ntest bl, bl\njz short loc_11F8\nloc_11DB:\nmovsx rbx, bl\nmov rcx, [rax]\nmovzx ecx, word ptr [rcx+rbx*2]\ntest ch, 4\njz short loc_11C5\nadd dword ptr [r12], 1\njmp short loc_11CF\nloc_11F2:\nadd dword ptr [r14], 1\njmp short loc_11CF\nloc_11F8:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "void __fastcall sub_1189(char *a1, _DWORD *a2, _DWORD *a3, _DWORD *a4)\n{\n char v4; // bl\n const unsigned __int16 **v7; // rax\n char *v8; // rdx\n unsigned __int16 v9; // cx\n\n *a4 = 0;\n *a3 = 0;\n *a2 = 0;\n v4 = *a1;\n if ( *a1 )\n {\n v7 = __ctype_b_loc();\n v8 = a1 + 1;\n do\n {\n v9 = (*v7)[v4];\n if ( (v9 & 0x400) != 0 )\n {\n ++*a2;\n }\n else if ( (v9 & 0x800) != 0 )\n {\n ++*a3;\n }\n else\n {\n ++*a4;\n }\n v4 = *v8++;\n }\n while ( v4 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1189(char *a1, uint32_t *a2, uint32_t *a3, uint32_t *a4) {\n char v4;\n const unsigned short **v7;\n char *v8;\n unsigned short v9;\n *a4 = 0;\n *a3 = 0;\n *a2 = 0;\n v4 = *a1;\n if (*a1) {\n v7 = __ctype_b_loc();\n v8 = a1 + 1;\n do {\n v9 = (*v7)[v4];\n if ((v9 & 1024) != 0) {\n ++*a2;\n } else if ((v9 & 2048) != 0) {\n ++*a3;\n } else {\n ++*a4;\n }\n v4 = *v8++;\n } while (v4);\n }\n}", + "ida_pseudo_norm": "void func0(char *a1, uint32_t *a2, uint32_t *a3, uint32_t *a4) {\n char v4;\n const unsigned short **v7;\n char *v8;\n unsigned short v9;\n *a4 = 0;\n *a3 = 0;\n *a2 = 0;\n v4 = *a1;\n if (*a1) {\n v7 = __ctype_b_loc();\n v8 = a1 + 1;\n do {\n v9 = (*v7)[v4];\n if ((v9 & 1024) != 0) {\n ++*a2;\n } else if ((v9 & 2048) != 0) {\n ++*a3;\n } else {\n ++*a4;\n }\n v4 = *v8++;\n } while (v4);\n }\n}" + }, + { + "index": 828, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "void func0(const char* string, int* alphabets, int* digits, int* special) {\n *alphabets = *digits = *special = 0;\n for (int i = 0; string[i] != '\\0'; i++) {\n if (isalpha(string[i]))\n (*alphabets)++;\n else if (isdigit(string[i]))\n (*digits)++;\n else\n (*special)++;\n }\n}", + "test": "int main() {\n\n int alphabets, digits, special;\n\n\n\n func0(\"abc!@#123\", &alphabets, &digits, &special);\n\n assert(alphabets == 3 && digits == 3 && special == 3);\n\n\n\n func0(\"dgsuy@#$%&1255\", &alphabets, &digits, &special);\n\n assert(alphabets == 5 && digits == 4 && special == 5);\n\n\n\n func0(\"fjdsif627348#%$^&\", &alphabets, &digits, &special);\n\n assert(alphabets == 6 && digits == 6 && special == 5);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\nmovl $0x0,(%rcx)\npush %r13\nmovl $0x0,(%rdx)\npush %r12\npush %rbp\npush %rbx\nmovl $0x0,(%rsi)\nmovsbq (%rdi),%rbx\ntest %bl,%bl\nje 1341 \nmov %rdi,%rbp\nmov %rsi,%r12\nmov %rdx,%r13\nmov %rcx,%r14\ncallq 1090 <__ctype_b_loc@plt>\nlea 0x1(%rbp),%rdi\nmov (%rax),%rsi\njmp 1321 \naddl $0x1,(%r12)\nmovsbq (%rdi),%rbx\nadd $0x1,%rdi\ntest %bl,%bl\nje 1341 \nmovzwl (%rsi,%rbx,2),%eax\ntest $0x4,%ah\njne 1310 \ntest $0x8,%ah\nje 1350 \nadd $0x1,%rdi\naddl $0x1,0x0(%r13)\nmovsbq -0x1(%rdi),%rbx\ntest %bl,%bl\njne 1321 \npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopw 0x0(%rax,%rax,1)\naddl $0x1,(%r14)\njmp 1315 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov dword ptr [rcx], 0\nmov dword ptr [rdx], 0\nmov dword ptr [rsi], 0\nmovsx rbx, byte ptr [rdi]\ntest bl, bl\njz short loc_1341\nmov rbp, rdi\nmov r12, rsi\nmov r13, rdx\nmov r14, rcx\ncall ___ctype_b_loc\nlea rdi, [rbp+1]\nmov rsi, [rax]\njmp short loc_1321\nloc_1310:\nadd dword ptr [r12], 1\nloc_1315:\nmovsx rbx, byte ptr [rdi]\nadd rdi, 1\ntest bl, bl\njz short loc_1341\nloc_1321:\nmovzx eax, word ptr [rsi+rbx*2]\ntest ah, 4\njnz short loc_1310\ntest ah, 8\njz short loc_1350\nadd rdi, 1\nadd dword ptr [r13+0], 1\nmovsx rbx, byte ptr [rdi-1]\ntest bl, bl\njnz short loc_1321\nloc_1341:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1350:\nadd dword ptr [r14], 1\njmp short loc_1315", + "ida_pseudo": "void __fastcall func0(char *a1, _DWORD *a2, _DWORD *a3, _DWORD *a4)\n{\n __int64 v4; // rbx\n char *v8; // rdi\n const unsigned __int16 *v9; // rsi\n unsigned __int16 v10; // ax\n\n *a4 = 0;\n *a3 = 0;\n *a2 = 0;\n v4 = *a1;\n if ( (_BYTE)v4 )\n {\n v8 = a1 + 1;\n v9 = *__ctype_b_loc();\n do\n {\n while ( 1 )\n {\n v10 = v9[v4];\n if ( (v10 & 0x400) == 0 )\n break;\n ++*a2;\nLABEL_4:\n v4 = *v8++;\n if ( !(_BYTE)v4 )\n return;\n }\n if ( (v10 & 0x800) == 0 )\n {\n ++*a4;\n goto LABEL_4;\n }\n ++v8;\n ++*a3;\n v4 = *(v8 - 1);\n }\n while ( (_BYTE)v4 );\n }\n}", + "ida_strip_asm": "sub_12D0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov dword ptr [rcx], 0\nmov dword ptr [rdx], 0\nmov dword ptr [rsi], 0\nmovsx rbx, byte ptr [rdi]\ntest bl, bl\njz short loc_1341\nmov rbp, rdi\nmov r12, rsi\nmov r13, rdx\nmov r14, rcx\ncall ___ctype_b_loc\nlea rdi, [rbp+1]\nmov rsi, [rax]\njmp short loc_1321\nloc_1310:\nadd dword ptr [r12], 1\nloc_1315:\nmovsx rbx, byte ptr [rdi]\nadd rdi, 1\ntest bl, bl\njz short loc_1341\nloc_1321:\nmovzx eax, word ptr [rsi+rbx*2]\ntest ah, 4\njnz short loc_1310\ntest ah, 8\njz short loc_1350\nadd rdi, 1\nadd dword ptr [r13+0], 1\nmovsx rbx, byte ptr [rdi-1]\ntest bl, bl\njnz short loc_1321\nloc_1341:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1350:\nadd dword ptr [r14], 1\njmp short loc_1315", + "ida_strip_pseudo": "void __fastcall sub_12D0(char *a1, _DWORD *a2, _DWORD *a3, _DWORD *a4)\n{\n __int64 v4; // rbx\n char *v8; // rdi\n const unsigned __int16 *v9; // rsi\n unsigned __int16 v10; // ax\n\n *a4 = 0;\n *a3 = 0;\n *a2 = 0;\n v4 = *a1;\n if ( (_BYTE)v4 )\n {\n v8 = a1 + 1;\n v9 = *__ctype_b_loc();\n do\n {\n while ( 1 )\n {\n v10 = v9[v4];\n if ( (v10 & 0x400) == 0 )\n break;\n ++*a2;\nLABEL_4:\n v4 = *v8++;\n if ( !(_BYTE)v4 )\n return;\n }\n if ( (v10 & 0x800) == 0 )\n {\n ++*a4;\n goto LABEL_4;\n }\n ++v8;\n ++*a3;\n v4 = *(v8 - 1);\n }\n while ( (_BYTE)v4 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_12D0(char *a1, uint32_t *a2, uint32_t *a3, uint32_t *a4) {\n long long v4;\n char *v8;\n const unsigned short *v9;\n unsigned short v10;\n *a4 = 0;\n *a3 = 0;\n *a2 = 0;\n v4 = *a1;\n if ((uint8_t)v4) {\n v8 = a1 + 1;\n v9 = *__ctype_b_loc();\n do {\n while (1) {\n v10 = v9[v4];\n if ((v10 & 1024) == 0) break;\n ++*a2;\n LABEL_4:\n v4 = *v8++;\n if (!(uint8_t)v4) return;\n }\n if ((v10 & 2048) == 0) {\n ++*a4;\n goto LABEL_4;\n }\n ++v8;\n ++*a3;\n v4 = *(v8 - 1);\n } while ((uint8_t)v4);\n }\n}", + "ida_pseudo_norm": "void func0(char *a1, uint32_t *a2, uint32_t *a3, uint32_t *a4) {\n long long v4;\n char *v8;\n const unsigned short *v9;\n unsigned short v10;\n *a4 = 0;\n *a3 = 0;\n *a2 = 0;\n v4 = *a1;\n if ((uint8_t)v4) {\n v8 = a1 + 1;\n v9 = *__ctype_b_loc();\n do {\n while (1) {\n v10 = v9[v4];\n if ((v10 & 1024) == 0) break;\n ++*a2;\n LABEL_4:\n v4 = *v8++;\n if (!(uint8_t)v4) return;\n }\n if ((v10 & 2048) == 0) {\n ++*a4;\n goto LABEL_4;\n }\n ++v8;\n ++*a3;\n v4 = *(v8 - 1);\n } while ((uint8_t)v4);\n }\n}" + }, + { + "index": 828, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "void func0(const char* string, int* alphabets, int* digits, int* special) {\n *alphabets = *digits = *special = 0;\n for (int i = 0; string[i] != '\\0'; i++) {\n if (isalpha(string[i]))\n (*alphabets)++;\n else if (isdigit(string[i]))\n (*digits)++;\n else\n (*special)++;\n }\n}", + "test": "int main() {\n\n int alphabets, digits, special;\n\n\n\n func0(\"abc!@#123\", &alphabets, &digits, &special);\n\n assert(alphabets == 3 && digits == 3 && special == 3);\n\n\n\n func0(\"dgsuy@#$%&1255\", &alphabets, &digits, &special);\n\n assert(alphabets == 5 && digits == 4 && special == 5);\n\n\n\n func0(\"fjdsif627348#%$^&\", &alphabets, &digits, &special);\n\n assert(alphabets == 6 && digits == 6 && special == 5);\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\nmovl $0x0,(%rcx)\npush %r13\nmovl $0x0,(%rdx)\npush %r12\npush %rbp\npush %rbx\nmovl $0x0,(%rsi)\nmovsbq (%rdi),%rbx\ntest %bl,%bl\nje 1341 \nmov %rdi,%rbp\nmov %rsi,%r12\nmov %rdx,%r13\nmov %rcx,%r14\ncallq 1090 <__ctype_b_loc@plt>\nlea 0x1(%rbp),%rdi\nmov (%rax),%rsi\njmp 1321 \naddl $0x1,(%r12)\nmovsbq (%rdi),%rbx\nadd $0x1,%rdi\ntest %bl,%bl\nje 1341 \nmovzwl (%rsi,%rbx,2),%eax\ntest $0x4,%ah\njne 1310 \ntest $0x8,%ah\nje 1350 \nadd $0x1,%rdi\naddl $0x1,0x0(%r13)\nmovsbq -0x1(%rdi),%rbx\ntest %bl,%bl\njne 1321 \npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopw 0x0(%rax,%rax,1)\naddl $0x1,(%r14)\njmp 1315 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov dword ptr [rcx], 0\nmov dword ptr [rdx], 0\nmov dword ptr [rsi], 0\nmovsx rbx, byte ptr [rdi]\ntest bl, bl\njz short loc_1341\nmov rbp, rdi\nmov r12, rsi\nmov r13, rdx\nmov r14, rcx\ncall ___ctype_b_loc\nlea rdi, [rbp+1]\nmov rsi, [rax]\njmp short loc_1321\nloc_1310:\nadd dword ptr [r12], 1\nloc_1315:\nmovsx rbx, byte ptr [rdi]\nadd rdi, 1\ntest bl, bl\njz short loc_1341\nloc_1321:\nmovzx eax, word ptr [rsi+rbx*2]\ntest ah, 4\njnz short loc_1310\ntest ah, 8\njz short loc_1350\nadd rdi, 1\nadd dword ptr [r13+0], 1\nmovsx rbx, byte ptr [rdi-1]\ntest bl, bl\njnz short loc_1321\nloc_1341:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1350:\nadd dword ptr [r14], 1\njmp short loc_1315", + "ida_pseudo": "void __fastcall func0(char *a1, _DWORD *a2, _DWORD *a3, _DWORD *a4)\n{\n __int64 v4; // rbx\n char *v8; // rdi\n const unsigned __int16 *v9; // rsi\n unsigned __int16 v10; // ax\n\n *a4 = 0;\n *a3 = 0;\n *a2 = 0;\n v4 = *a1;\n if ( (_BYTE)v4 )\n {\n v8 = a1 + 1;\n v9 = *__ctype_b_loc();\n do\n {\n while ( 1 )\n {\n v10 = v9[v4];\n if ( (v10 & 0x400) == 0 )\n break;\n ++*a2;\nLABEL_4:\n v4 = *v8++;\n if ( !(_BYTE)v4 )\n return;\n }\n if ( (v10 & 0x800) == 0 )\n {\n ++*a4;\n goto LABEL_4;\n }\n ++v8;\n ++*a3;\n v4 = *(v8 - 1);\n }\n while ( (_BYTE)v4 );\n }\n}", + "ida_strip_asm": "sub_12D0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov dword ptr [rcx], 0\nmov dword ptr [rdx], 0\nmov dword ptr [rsi], 0\nmovsx rbx, byte ptr [rdi]\ntest bl, bl\njz short loc_1341\nmov rbp, rdi\nmov r12, rsi\nmov r13, rdx\nmov r14, rcx\ncall ___ctype_b_loc\nlea rdi, [rbp+1]\nmov rsi, [rax]\njmp short loc_1321\nloc_1310:\nadd dword ptr [r12], 1\nloc_1315:\nmovsx rbx, byte ptr [rdi]\nadd rdi, 1\ntest bl, bl\njz short loc_1341\nloc_1321:\nmovzx eax, word ptr [rsi+rbx*2]\ntest ah, 4\njnz short loc_1310\ntest ah, 8\njz short loc_1350\nadd rdi, 1\nadd dword ptr [r13+0], 1\nmovsx rbx, byte ptr [rdi-1]\ntest bl, bl\njnz short loc_1321\nloc_1341:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1350:\nadd dword ptr [r14], 1\njmp short loc_1315", + "ida_strip_pseudo": "void __fastcall sub_12D0(char *a1, _DWORD *a2, _DWORD *a3, _DWORD *a4)\n{\n __int64 v4; // rbx\n char *v8; // rdi\n const unsigned __int16 *v9; // rsi\n unsigned __int16 v10; // ax\n\n *a4 = 0;\n *a3 = 0;\n *a2 = 0;\n v4 = *a1;\n if ( (_BYTE)v4 )\n {\n v8 = a1 + 1;\n v9 = *__ctype_b_loc();\n do\n {\n while ( 1 )\n {\n v10 = v9[v4];\n if ( (v10 & 0x400) == 0 )\n break;\n ++*a2;\nLABEL_4:\n v4 = *v8++;\n if ( !(_BYTE)v4 )\n return;\n }\n if ( (v10 & 0x800) == 0 )\n {\n ++*a4;\n goto LABEL_4;\n }\n ++v8;\n ++*a3;\n v4 = *(v8 - 1);\n }\n while ( (_BYTE)v4 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_12D0(char *a1, uint32_t *a2, uint32_t *a3, uint32_t *a4) {\n long long v4;\n char *v8;\n const unsigned short *v9;\n unsigned short v10;\n *a4 = 0;\n *a3 = 0;\n *a2 = 0;\n v4 = *a1;\n if ((uint8_t)v4) {\n v8 = a1 + 1;\n v9 = *__ctype_b_loc();\n do {\n while (1) {\n v10 = v9[v4];\n if ((v10 & 1024) == 0) break;\n ++*a2;\n LABEL_4:\n v4 = *v8++;\n if (!(uint8_t)v4) return;\n }\n if ((v10 & 2048) == 0) {\n ++*a4;\n goto LABEL_4;\n }\n ++v8;\n ++*a3;\n v4 = *(v8 - 1);\n } while ((uint8_t)v4);\n }\n}", + "ida_pseudo_norm": "void func0(char *a1, uint32_t *a2, uint32_t *a3, uint32_t *a4) {\n long long v4;\n char *v8;\n const unsigned short *v9;\n unsigned short v10;\n *a4 = 0;\n *a3 = 0;\n *a2 = 0;\n v4 = *a1;\n if ((uint8_t)v4) {\n v8 = a1 + 1;\n v9 = *__ctype_b_loc();\n do {\n while (1) {\n v10 = v9[v4];\n if ((v10 & 1024) == 0) break;\n ++*a2;\n LABEL_4:\n v4 = *v8++;\n if (!(uint8_t)v4) return;\n }\n if ((v10 & 2048) == 0) {\n ++*a4;\n goto LABEL_4;\n }\n ++v8;\n ++*a3;\n v4 = *(v8 - 1);\n } while ((uint8_t)v4);\n }\n}" + }, + { + "index": 829, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* input[], int size) {\n int count[100] = {0};\n char* unique[100];\n int unique_count = 0;\n for (int i = 0; i < size; i++) {\n int found = 0;\n for (int j = 0; j < unique_count; j++) {\n if (strcmp(input[i], unique[j]) == 0) {\n count[j]++;\n found = 1;\n break;\n }\n }\n if (!found) {\n unique[unique_count] = input[i];\n count[unique_count] = 1;\n unique_count++;\n }\n }\n int first = 0, second = 0;\n for (int i = 0; i < unique_count; i++) {\n if (count[i] > first) {\n second = first;\n first = count[i];\n }\n else if (count[i] > second && count[i] < first) {\n second = count[i];\n }\n }\n for (int i = 0; i < unique_count; i++) {\n if (count[i] == second) {\n return unique[i];\n }\n }\n return NULL;\n}", + "test": "int main() {\n\n char* arr1[] = {\"aaa\",\"bbb\",\"ccc\",\"bbb\",\"aaa\",\"aaa\"};\n\n assert(strcmp(func0(arr1, 6), \"bbb\") == 0);\n\n\n\n char* arr2[] = {\"abc\",\"bcd\",\"abc\",\"bcd\",\"bcd\",\"bcd\"};\n\n assert(strcmp(func0(arr2, 6), \"abc\") == 0);\n\n\n\n char* arr3[] = {\"cdma\",\"gsm\",\"hspa\",\"gsm\",\"cdma\",\"cdma\"};\n\n assert(strcmp(func0(arr3, 6), \"gsm\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x4f0,%rsp\nmov %rdi,-0x4e8(%rbp)\nmov %esi,-0x4ec(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea -0x4c0(%rbp),%rdx\nmov $0x0,%eax\nmov $0x32,%ecx\nmov %rdx,%rdi\nrep stos %rax,%es:(%rdi)\nmovl $0x0,-0x4e0(%rbp)\nmovl $0x0,-0x4dc(%rbp)\njmpq 12cf \nmovl $0x0,-0x4d8(%rbp)\nmovl $0x0,-0x4d4(%rbp)\njmp 126a \nmov -0x4d4(%rbp),%eax\ncltq\nmov -0x330(%rbp,%rax,8),%rdx\nmov -0x4dc(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x4e8(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1090 \ntest %eax,%eax\njne 1263 \nmov -0x4d4(%rbp),%eax\ncltq\nmov -0x4c0(%rbp,%rax,4),%eax\nlea 0x1(%rax),%edx\nmov -0x4d4(%rbp),%eax\ncltq\nmov %edx,-0x4c0(%rbp,%rax,4)\nmovl $0x1,-0x4d8(%rbp)\njmp 1278 \naddl $0x1,-0x4d4(%rbp)\nmov -0x4d4(%rbp),%eax\ncmp -0x4e0(%rbp),%eax\njl 11fa \ncmpl $0x0,-0x4d8(%rbp)\njne 12c8 \nmov -0x4dc(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x4e8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rdx\nmov -0x4e0(%rbp),%eax\ncltq\nmov %rdx,-0x330(%rbp,%rax,8)\nmov -0x4e0(%rbp),%eax\ncltq\nmovl $0x1,-0x4c0(%rbp,%rax,4)\naddl $0x1,-0x4e0(%rbp)\naddl $0x1,-0x4dc(%rbp)\nmov -0x4dc(%rbp),%eax\ncmp -0x4ec(%rbp),%eax\njl 11e4 \nmovl $0x0,-0x4d0(%rbp)\nmovl $0x0,-0x4cc(%rbp)\nmovl $0x0,-0x4c8(%rbp)\njmpq 1388 \nmov -0x4c8(%rbp),%eax\ncltq\nmov -0x4c0(%rbp,%rax,4),%eax\ncmp %eax,-0x4d0(%rbp)\njge 133e \nmov -0x4d0(%rbp),%eax\nmov %eax,-0x4cc(%rbp)\nmov -0x4c8(%rbp),%eax\ncltq\nmov -0x4c0(%rbp,%rax,4),%eax\nmov %eax,-0x4d0(%rbp)\njmp 1381 \nmov -0x4c8(%rbp),%eax\ncltq\nmov -0x4c0(%rbp,%rax,4),%eax\ncmp %eax,-0x4cc(%rbp)\njge 1381 \nmov -0x4c8(%rbp),%eax\ncltq\nmov -0x4c0(%rbp,%rax,4),%eax\ncmp %eax,-0x4d0(%rbp)\njle 1381 \nmov -0x4c8(%rbp),%eax\ncltq\nmov -0x4c0(%rbp,%rax,4),%eax\nmov %eax,-0x4cc(%rbp)\naddl $0x1,-0x4c8(%rbp)\nmov -0x4c8(%rbp),%eax\ncmp -0x4e0(%rbp),%eax\njl 1304 \nmovl $0x0,-0x4c4(%rbp)\njmp 13d6 \nmov -0x4c4(%rbp),%eax\ncltq\nmov -0x4c0(%rbp,%rax,4),%eax\ncmp %eax,-0x4cc(%rbp)\njne 13cf \nmov -0x4c4(%rbp),%eax\ncltq\nmov -0x330(%rbp,%rax,8),%rax\njmp 13e9 \naddl $0x1,-0x4c4(%rbp)\nmov -0x4c4(%rbp),%eax\ncmp -0x4e0(%rbp),%eax\njl 13a6 \nmov $0x0,%eax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 13fd \ncallq 1070 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 4F0h\nmov [rbp+var_4E8], rdi\nmov [rbp+var_4EC], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rdx, [rbp+var_4C0]\nmov eax, 0\nmov ecx, 32h ; '2'\nmov rdi, rdx\nrep stosq\nmov [rbp+var_4E0], 0\nmov [rbp+var_4DC], 0\njmp loc_12CF\nloc_11E4:\nmov [rbp+var_4D8], 0\nmov [rbp+var_4D4], 0\njmp short loc_126A\nloc_11FA:\nmov eax, [rbp+var_4D4]\ncdqe\nmov rdx, [rbp+rax*8+s2]\nmov eax, [rbp+var_4DC]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_4E8]\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1263\nmov eax, [rbp+var_4D4]\ncdqe\nmov eax, [rbp+rax*4+var_4C0]\nlea edx, [rax+1]\nmov eax, [rbp+var_4D4]\ncdqe\nmov [rbp+rax*4+var_4C0], edx\nmov [rbp+var_4D8], 1\njmp short loc_1278\nloc_1263:\nadd [rbp+var_4D4], 1\nloc_126A:\nmov eax, [rbp+var_4D4]\ncmp eax, [rbp+var_4E0]\njl short loc_11FA\nloc_1278:\ncmp [rbp+var_4D8], 0\njnz short loc_12C8\nmov eax, [rbp+var_4DC]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_4E8]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_4E0]\ncdqe\nmov [rbp+rax*8+s2], rdx\nmov eax, [rbp+var_4E0]\ncdqe\nmov [rbp+rax*4+var_4C0], 1\nadd [rbp+var_4E0], 1\nloc_12C8:\nadd [rbp+var_4DC], 1\nloc_12CF:\nmov eax, [rbp+var_4DC]\ncmp eax, [rbp+var_4EC]\njl loc_11E4\nmov [rbp+var_4D0], 0\nmov [rbp+var_4CC], 0\nmov [rbp+var_4C8], 0\njmp loc_1388\nloc_1304:\nmov eax, [rbp+var_4C8]\ncdqe\nmov eax, [rbp+rax*4+var_4C0]\ncmp [rbp+var_4D0], eax\njge short loc_133E\nmov eax, [rbp+var_4D0]\nmov [rbp+var_4CC], eax\nmov eax, [rbp+var_4C8]\ncdqe\nmov eax, [rbp+rax*4+var_4C0]\nmov [rbp+var_4D0], eax\njmp short loc_1381\nloc_133E:\nmov eax, [rbp+var_4C8]\ncdqe\nmov eax, [rbp+rax*4+var_4C0]\ncmp [rbp+var_4CC], eax\njge short loc_1381\nmov eax, [rbp+var_4C8]\ncdqe\nmov eax, [rbp+rax*4+var_4C0]\ncmp [rbp+var_4D0], eax\njle short loc_1381\nmov eax, [rbp+var_4C8]\ncdqe\nmov eax, [rbp+rax*4+var_4C0]\nmov [rbp+var_4CC], eax\nloc_1381:\nadd [rbp+var_4C8], 1\nloc_1388:\nmov eax, [rbp+var_4C8]\ncmp eax, [rbp+var_4E0]\njl loc_1304\nmov [rbp+var_4C4], 0\njmp short loc_13D6\nloc_13A6:\nmov eax, [rbp+var_4C4]\ncdqe\nmov eax, [rbp+rax*4+var_4C0]\ncmp [rbp+var_4CC], eax\njnz short loc_13CF\nmov eax, [rbp+var_4C4]\ncdqe\nmov rax, [rbp+rax*8+s2]\njmp short loc_13E9\nloc_13CF:\nadd [rbp+var_4C4], 1\nloc_13D6:\nmov eax, [rbp+var_4C4]\ncmp eax, [rbp+var_4E0]\njl short loc_13A6\nmov eax, 0\nloc_13E9:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_13FD\ncall ___stack_chk_fail\nlocret_13FD:\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2)\n{\n int v3; // [rsp+10h] [rbp-4E0h]\n int i; // [rsp+14h] [rbp-4DCh]\n int v5; // [rsp+18h] [rbp-4D8h]\n int j; // [rsp+1Ch] [rbp-4D4h]\n int v7; // [rsp+20h] [rbp-4D0h]\n int v8; // [rsp+24h] [rbp-4CCh]\n int k; // [rsp+28h] [rbp-4C8h]\n int m; // [rsp+2Ch] [rbp-4C4h]\n _DWORD v11[100]; // [rsp+30h] [rbp-4C0h] BYREF\n char *s2[102]; // [rsp+1C0h] [rbp-330h]\n\n s2[101] = (char *)__readfsqword(0x28u);\n memset(v11, 0, sizeof(v11));\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v5 = 0;\n for ( j = 0; j < v3; ++j )\n {\n if ( !strcmp(*(const char **)(8LL * i + a1), s2[j]) )\n {\n ++v11[j];\n v5 = 1;\n break;\n }\n }\n if ( !v5 )\n {\n s2[v3] = *(char **)(8LL * i + a1);\n v11[v3++] = 1;\n }\n }\n v7 = 0;\n v8 = 0;\n for ( k = 0; k < v3; ++k )\n {\n if ( v7 >= v11[k] )\n {\n if ( v8 < v11[k] && v7 > v11[k] )\n v8 = v11[k];\n }\n else\n {\n v8 = v7;\n v7 = v11[k];\n }\n }\n for ( m = 0; m < v3; ++m )\n {\n if ( v8 == v11[m] )\n return s2[m];\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 4F0h\nmov [rbp+var_4E8], rdi\nmov [rbp+var_4EC], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rdx, [rbp+var_4C0]\nmov eax, 0\nmov ecx, 32h ; '2'\nmov rdi, rdx\nrep stosq\nmov [rbp+var_4E0], 0\nmov [rbp+var_4DC], 0\njmp loc_12CF\nloc_11E4:\nmov [rbp+var_4D8], 0\nmov [rbp+var_4D4], 0\njmp short loc_126A\nloc_11FA:\nmov eax, [rbp+var_4D4]\ncdqe\nmov rdx, [rbp+rax*8+s2]\nmov eax, [rbp+var_4DC]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_4E8]\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1263\nmov eax, [rbp+var_4D4]\ncdqe\nmov eax, [rbp+rax*4+var_4C0]\nlea edx, [rax+1]\nmov eax, [rbp+var_4D4]\ncdqe\nmov [rbp+rax*4+var_4C0], edx\nmov [rbp+var_4D8], 1\njmp short loc_1278\nloc_1263:\nadd [rbp+var_4D4], 1\nloc_126A:\nmov eax, [rbp+var_4D4]\ncmp eax, [rbp+var_4E0]\njl short loc_11FA\nloc_1278:\ncmp [rbp+var_4D8], 0\njnz short loc_12C8\nmov eax, [rbp+var_4DC]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_4E8]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_4E0]\ncdqe\nmov [rbp+rax*8+s2], rdx\nmov eax, [rbp+var_4E0]\ncdqe\nmov [rbp+rax*4+var_4C0], 1\nadd [rbp+var_4E0], 1\nloc_12C8:\nadd [rbp+var_4DC], 1\nloc_12CF:\nmov eax, [rbp+var_4DC]\ncmp eax, [rbp+var_4EC]\njl loc_11E4\nmov [rbp+var_4D0], 0\nmov [rbp+var_4CC], 0\nmov [rbp+var_4C8], 0\njmp loc_1388\nloc_1304:\nmov eax, [rbp+var_4C8]\ncdqe\nmov eax, [rbp+rax*4+var_4C0]\ncmp [rbp+var_4D0], eax\njge short loc_133E\nmov eax, [rbp+var_4D0]\nmov [rbp+var_4CC], eax\nmov eax, [rbp+var_4C8]\ncdqe\nmov eax, [rbp+rax*4+var_4C0]\nmov [rbp+var_4D0], eax\njmp short loc_1381\nloc_133E:\nmov eax, [rbp+var_4C8]\ncdqe\nmov eax, [rbp+rax*4+var_4C0]\ncmp [rbp+var_4CC], eax\njge short loc_1381\nmov eax, [rbp+var_4C8]\ncdqe\nmov eax, [rbp+rax*4+var_4C0]\ncmp [rbp+var_4D0], eax\njle short loc_1381\nmov eax, [rbp+var_4C8]\ncdqe\nmov eax, [rbp+rax*4+var_4C0]\nmov [rbp+var_4CC], eax\nloc_1381:\nadd [rbp+var_4C8], 1\nloc_1388:\nmov eax, [rbp+var_4C8]\ncmp eax, [rbp+var_4E0]\njl loc_1304\nmov [rbp+var_4C4], 0\njmp short loc_13D6\nloc_13A6:\nmov eax, [rbp+var_4C4]\ncdqe\nmov eax, [rbp+rax*4+var_4C0]\ncmp [rbp+var_4CC], eax\njnz short loc_13CF\nmov eax, [rbp+var_4C4]\ncdqe\nmov rax, [rbp+rax*8+s2]\njmp short loc_13E9\nloc_13CF:\nadd [rbp+var_4C4], 1\nloc_13D6:\nmov eax, [rbp+var_4C4]\ncmp eax, [rbp+var_4E0]\njl short loc_13A6\nmov eax, 0\nloc_13E9:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_13FD\ncall ___stack_chk_fail\nlocret_13FD:\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1189(__int64 a1, int a2)\n{\n int v3; // [rsp+10h] [rbp-4E0h]\n int i; // [rsp+14h] [rbp-4DCh]\n int v5; // [rsp+18h] [rbp-4D8h]\n int j; // [rsp+1Ch] [rbp-4D4h]\n int v7; // [rsp+20h] [rbp-4D0h]\n int v8; // [rsp+24h] [rbp-4CCh]\n int k; // [rsp+28h] [rbp-4C8h]\n int m; // [rsp+2Ch] [rbp-4C4h]\n _DWORD v11[100]; // [rsp+30h] [rbp-4C0h] BYREF\n char *s2[102]; // [rsp+1C0h] [rbp-330h]\n\n s2[101] = (char *)__readfsqword(0x28u);\n memset(v11, 0, sizeof(v11));\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v5 = 0;\n for ( j = 0; j < v3; ++j )\n {\n if ( !strcmp(*(const char **)(8LL * i + a1), s2[j]) )\n {\n ++v11[j];\n v5 = 1;\n break;\n }\n }\n if ( !v5 )\n {\n s2[v3] = *(char **)(8LL * i + a1);\n v11[v3++] = 1;\n }\n }\n v7 = 0;\n v8 = 0;\n for ( k = 0; k < v3; ++k )\n {\n if ( v7 >= v11[k] )\n {\n if ( v8 < v11[k] && v7 > v11[k] )\n v8 = v11[k];\n }\n else\n {\n v8 = v7;\n v7 = v11[k];\n }\n }\n for ( m = 0; m < v3; ++m )\n {\n if ( v8 == v11[m] )\n return s2[m];\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1189(long long a1, int a2) {\n int v3;\n int i;\n int v5;\n int j;\n int v7;\n int v8;\n int k;\n int m;\n uint32_t v11[100];\n char *s2[102];\n s2[101] = (char *)__readfsqword(40u);\n memset(v11, 0, sizeof(v11));\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n v5 = 0;\n for (j = 0; j < v3; ++j) {\n if (!strcmp(*(const char **)(8LL * i + a1), s2[j])) {\n ++v11[j];\n v5 = 1;\n break;\n }\n }\n if (!v5) {\n s2[v3] = *(char **)(8LL * i + a1);\n v11[v3++] = 1;\n }\n }\n v7 = 0;\n v8 = 0;\n for (k = 0; k < v3; ++k) {\n if (v7 >= v11[k]) {\n if (v8 < v11[k] && v7 > v11[k]) v8 = v11[k];\n } else {\n v8 = v7;\n v7 = v11[k];\n }\n }\n for (m = 0; m < v3; ++m) {\n if (v8 == v11[m]) return s2[m];\n }\n return 0LL;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2) {\n int v3;\n int i;\n int v5;\n int j;\n int v7;\n int v8;\n int k;\n int m;\n uint32_t v11[100];\n char *s2[102];\n s2[101] = (char *)__readfsqword(40u);\n memset(v11, 0, sizeof(v11));\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n v5 = 0;\n for (j = 0; j < v3; ++j) {\n if (!strcmp(*(const char **)(8LL * i + a1), s2[j])) {\n ++v11[j];\n v5 = 1;\n break;\n }\n }\n if (!v5) {\n s2[v3] = *(char **)(8LL * i + a1);\n v11[v3++] = 1;\n }\n }\n v7 = 0;\n v8 = 0;\n for (k = 0; k < v3; ++k) {\n if (v7 >= v11[k]) {\n if (v8 < v11[k] && v7 > v11[k]) v8 = v11[k];\n } else {\n v8 = v7;\n v7 = v11[k];\n }\n }\n for (m = 0; m < v3; ++m) {\n if (v8 == v11[m]) return s2[m];\n }\n return 0LL;\n}" + }, + { + "index": 829, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* input[], int size) {\n int count[100] = {0};\n char* unique[100];\n int unique_count = 0;\n for (int i = 0; i < size; i++) {\n int found = 0;\n for (int j = 0; j < unique_count; j++) {\n if (strcmp(input[i], unique[j]) == 0) {\n count[j]++;\n found = 1;\n break;\n }\n }\n if (!found) {\n unique[unique_count] = input[i];\n count[unique_count] = 1;\n unique_count++;\n }\n }\n int first = 0, second = 0;\n for (int i = 0; i < unique_count; i++) {\n if (count[i] > first) {\n second = first;\n first = count[i];\n }\n else if (count[i] > second && count[i] < first) {\n second = count[i];\n }\n }\n for (int i = 0; i < unique_count; i++) {\n if (count[i] == second) {\n return unique[i];\n }\n }\n return NULL;\n}", + "test": "int main() {\n\n char* arr1[] = {\"aaa\",\"bbb\",\"ccc\",\"bbb\",\"aaa\",\"aaa\"};\n\n assert(strcmp(func0(arr1, 6), \"bbb\") == 0);\n\n\n\n char* arr2[] = {\"abc\",\"bcd\",\"abc\",\"bcd\",\"bcd\",\"bcd\"};\n\n assert(strcmp(func0(arr2, 6), \"abc\") == 0);\n\n\n\n char* arr3[] = {\"cdma\",\"gsm\",\"hspa\",\"gsm\",\"cdma\",\"cdma\"};\n\n assert(strcmp(func0(arr3, 6), \"gsm\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x4d8,%rsp\nmov %rdi,%rdx\nmov %fs:0x28,%rax\nmov %rax,0x4c8(%rsp)\nxor %eax,%eax\nlea 0x10(%rsp),%rdi\nmov $0x32,%ecx\nrep stos %rax,%es:(%rdi)\ntest %esi,%esi\njle 12d6 \nmov %rdx,%r14\nlea -0x1(%rsi),%eax\nlea 0x8(%rdx,%rax,8),%rax\nmov %rax,0x8(%rsp)\nmov $0x0,%r15d\njmp 1226 \nmov %rax,%rbx\nmov 0x1a0(%rsp,%rbx,8),%rsi\nmov %r12,%rdi\ncallq 1090 \ntest %eax,%eax\nje 1239 \nlea 0x1(%rbx),%rax\ncmp %r13,%rbx\njne 11e1 \nmovslq %r15d,%rax\nmov (%r14),%rdx\nmov %rdx,0x1a0(%rsp,%rax,8)\nmovl $0x1,0x10(%rsp,%rax,4)\nadd $0x1,%r15d\nadd $0x8,%r14\ncmp 0x8(%rsp),%r14\nje 1243 \ntest %r15d,%r15d\njle 1201 \nmov (%r14),%r12\nlea -0x1(%r15),%r13d\nmov $0x0,%ebx\njmp 11e4 \nmovslq %ebx,%rbp\naddl $0x1,0x10(%rsp,%rbp,4)\njmp 121b \ntest %r15d,%r15d\njle 12d6 \nlea 0x10(%rsp),%rax\nlea -0x1(%r15),%edi\nlea 0x14(%rsp,%rdi,4),%r8\nmov $0x0,%ecx\nmov $0x0,%esi\njmp 1273 \nmov %esi,%ecx\nmov %edx,%esi\nadd $0x4,%rax\ncmp %r8,%rax\nje 1282 \nmov (%rax),%edx\ncmp %esi,%edx\njg 1266 \njge 126a \ncmp %ecx,%edx\ncmovg %edx,%ecx\njmp 126a \nmov $0x0,%eax\nlea 0x10(%rsp),%rsi\njmp 1291 \nmov %rdx,%rax\ncmp %ecx,(%rsi,%rax,4)\nje 12a6 \nlea 0x1(%rax),%rdx\ncmp %rdi,%rax\njne 128e \nmov $0x0,%eax\njmp 12b1 \nmovslq %eax,%rdx\nmov 0x1a0(%rsp,%rdx,8),%rax\nmov 0x4c8(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 12dd \nadd $0x4d8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmov $0x0,%eax\njmp 12b1 \ncallq 1070 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 4C8h\nmov rdx, rdi\nmov rax, fs:28h\nmov [rsp+4F8h+var_40], rax\nxor eax, eax\nmov rdi, rsp\nmov ecx, 32h ; '2'\nrep stosq\ntest esi, esi\njle loc_12C4\nmov r13, rdx\nmovsxd rsi, esi\nlea r14, [rdx+rsi*8]\nmov r12d, 0\njmp short loc_1205\nloc_11D9:\nmovsxd rbx, ebx\nadd [rsp+rbx*4+4F8h+var_4F8], 1\njmp short loc_11FC\nloc_11E2:\nmovsxd rax, r12d\nmov rdx, [r13+0]\nmov [rsp+rax*8+4F8h+s2], rdx\nmov [rsp+rax*4+4F8h+var_4F8], 1\nadd r12d, 1\nloc_11FC:\nadd r13, 8\ncmp r13, r14\njz short loc_1235\nloc_1205:\ntest r12d, r12d\njle short loc_11E2\nmov rbp, [r13+0]\nmovsxd r15, r12d\nmov ebx, 0\nloc_1216:\nmov rsi, [rsp+rbx*8+4F8h+s2]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njz short loc_11D9\nadd rbx, 1\ncmp rbx, r15\njnz short loc_1216\njmp short loc_11E2\nloc_1235:\ntest r12d, r12d\njle loc_12C4\nmov rcx, rsp\nmovsxd r12, r12d\nlea rdi, [rcx+r12*4]\nmov eax, 0\nmov esi, 0\njmp short loc_1261\nloc_1254:\nmov eax, esi\nmov esi, edx\nloc_1258:\nadd rcx, 4\ncmp rdi, rcx\njz short loc_1277\nloc_1261:\nmov edx, [rcx]\ncmp edx, esi\njg short loc_1254\nmov r8d, eax\ncmp edx, eax\ncmovge eax, edx\ncmp edx, esi\ncmovge eax, r8d\njmp short loc_1258\nloc_1277:\nmov edx, 0\nmov rcx, rsp\nloc_127F:\ncmp [rcx+rdx*4], eax\njz short loc_1294\nadd rdx, 1\ncmp rdx, r12\njnz short loc_127F\nmov eax, 0\njmp short loc_129F\nloc_1294:\nmovsxd rdx, edx\nmov rax, [rsp+rdx*8+4F8h+s2]\nloc_129F:\nmov rdx, [rsp+4F8h+var_40]\nsub rdx, fs:28h\njnz short loc_12CB\nadd rsp, 4C8h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_12C4:\nmov eax, 0\njmp short loc_129F\nloc_12CB:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(char **a1, int a2)\n{\n char **v2; // r13\n int v3; // r12d\n const char *v4; // rbp\n __int64 v5; // rbx\n int *v6; // rcx\n int v7; // eax\n int v8; // esi\n int v9; // edx\n int v10; // r8d\n __int64 v11; // rdx\n _DWORD v13[100]; // [rsp+0h] [rbp-4F8h] BYREF\n char *s2[109]; // [rsp+190h] [rbp-368h]\n\n s2[101] = (char *)__readfsqword(0x28u);\n memset(v13, 0, sizeof(v13));\n if ( a2 <= 0 )\n return 0LL;\n v2 = a1;\n v3 = 0;\n do\n {\n if ( v3 <= 0 )\n {\nLABEL_4:\n s2[v3] = *v2;\n v13[v3++] = 1;\n }\n else\n {\n v4 = *v2;\n v5 = 0LL;\n while ( strcmp(v4, s2[v5]) )\n {\n if ( ++v5 == v3 )\n goto LABEL_4;\n }\n ++v13[(int)v5];\n }\n ++v2;\n }\n while ( v2 != &a1[a2] );\n if ( v3 <= 0 )\n return 0LL;\n v6 = v13;\n v7 = 0;\n v8 = 0;\n do\n {\n v9 = *v6;\n if ( *v6 > v8 )\n {\n v7 = v8;\n v8 = *v6;\n }\n else\n {\n v10 = v7;\n if ( v9 >= v7 )\n v7 = *v6;\n if ( v9 >= v8 )\n v7 = v10;\n }\n ++v6;\n }\n while ( &v13[v3] != v6 );\n v11 = 0LL;\n while ( v13[v11] != v7 )\n {\n if ( ++v11 == v3 )\n return 0LL;\n }\n return s2[(int)v11];\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 4C8h\nmov rdx, rdi\nmov rax, fs:28h\nmov [rsp+4F8h+var_40], rax\nxor eax, eax\nmov rdi, rsp\nmov ecx, 32h ; '2'\nrep stosq\ntest esi, esi\njle loc_12C4\nmov r13, rdx\nmovsxd rsi, esi\nlea r14, [rdx+rsi*8]\nmov r12d, 0\njmp short loc_1205\nloc_11D9:\nmovsxd rbx, ebx\nadd [rsp+rbx*4+4F8h+var_4F8], 1\njmp short loc_11FC\nloc_11E2:\nmovsxd rax, r12d\nmov rdx, [r13+0]\nmov [rsp+rax*8+4F8h+s2], rdx\nmov [rsp+rax*4+4F8h+var_4F8], 1\nadd r12d, 1\nloc_11FC:\nadd r13, 8\ncmp r13, r14\njz short loc_1235\nloc_1205:\ntest r12d, r12d\njle short loc_11E2\nmov rbp, [r13+0]\nmovsxd r15, r12d\nmov ebx, 0\nloc_1216:\nmov rsi, [rsp+rbx*8+4F8h+s2]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njz short loc_11D9\nadd rbx, 1\ncmp rbx, r15\njnz short loc_1216\njmp short loc_11E2\nloc_1235:\ntest r12d, r12d\njle loc_12C4\nmov rcx, rsp\nmovsxd r12, r12d\nlea rdi, [rcx+r12*4]\nmov eax, 0\nmov esi, 0\njmp short loc_1261\nloc_1254:\nmov eax, esi\nmov esi, edx\nloc_1258:\nadd rcx, 4\ncmp rdi, rcx\njz short loc_1277\nloc_1261:\nmov edx, [rcx]\ncmp edx, esi\njg short loc_1254\nmov r8d, eax\ncmp edx, eax\ncmovge eax, edx\ncmp edx, esi\ncmovge eax, r8d\njmp short loc_1258\nloc_1277:\nmov edx, 0\nmov rcx, rsp\nloc_127F:\ncmp [rcx+rdx*4], eax\njz short loc_1294\nadd rdx, 1\ncmp rdx, r12\njnz short loc_127F\nmov eax, 0\njmp short loc_129F\nloc_1294:\nmovsxd rdx, edx\nmov rax, [rsp+rdx*8+4F8h+s2]\nloc_129F:\nmov rdx, [rsp+4F8h+var_40]\nsub rdx, fs:28h\njnz short loc_12CB\nadd rsp, 4C8h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_12C4:\nmov eax, 0\njmp short loc_129F\nloc_12CB:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_1189(char **a1, int a2)\n{\n char **v2; // r13\n int v3; // r12d\n const char *v4; // rbp\n __int64 v5; // rbx\n int *v6; // rcx\n int v7; // eax\n int v8; // esi\n int v9; // edx\n int v10; // r8d\n __int64 v11; // rdx\n _DWORD v13[100]; // [rsp+0h] [rbp-4F8h] BYREF\n char *s2[109]; // [rsp+190h] [rbp-368h]\n\n s2[101] = (char *)__readfsqword(0x28u);\n memset(v13, 0, sizeof(v13));\n if ( a2 <= 0 )\n return 0LL;\n v2 = a1;\n v3 = 0;\n do\n {\n if ( v3 <= 0 )\n {\nLABEL_4:\n s2[v3] = *v2;\n v13[v3++] = 1;\n }\n else\n {\n v4 = *v2;\n v5 = 0LL;\n while ( strcmp(v4, s2[v5]) )\n {\n if ( ++v5 == v3 )\n goto LABEL_4;\n }\n ++v13[(int)v5];\n }\n ++v2;\n }\n while ( v2 != &a1[a2] );\n if ( v3 <= 0 )\n return 0LL;\n v6 = v13;\n v7 = 0;\n v8 = 0;\n do\n {\n v9 = *v6;\n if ( *v6 > v8 )\n {\n v7 = v8;\n v8 = *v6;\n }\n else\n {\n v10 = v7;\n if ( v9 >= v7 )\n v7 = *v6;\n if ( v9 >= v8 )\n v7 = v10;\n }\n ++v6;\n }\n while ( &v13[v3] != v6 );\n v11 = 0LL;\n while ( v13[v11] != v7 )\n {\n if ( ++v11 == v3 )\n return 0LL;\n }\n return s2[(int)v11];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1189(char **a1, int a2) {\n char **v2;\n int v3;\n const char *v4;\n long long v5;\n int *v6;\n int v7;\n int v8;\n int v9;\n int v10;\n long long v11;\n uint32_t v13[100];\n char *s2[109];\n s2[101] = (char *)__readfsqword(40u);\n memset(v13, 0, sizeof(v13));\n if (a2 <= 0) return 0LL;\n v2 = a1;\n v3 = 0;\n do {\n if (v3 <= 0) {\n LABEL_4:\n s2[v3] = *v2;\n v13[v3++] = 1;\n } else {\n v4 = *v2;\n v5 = 0LL;\n while (strcmp(v4, s2[v5])) {\n if (++v5 == v3) goto LABEL_4;\n }\n ++v13[(int)v5];\n }\n ++v2;\n } while (v2 != &a1[a2]);\n if (v3 <= 0) return 0LL;\n v6 = v13;\n v7 = 0;\n v8 = 0;\n do {\n v9 = *v6;\n if (*v6 > v8) {\n v7 = v8;\n v8 = *v6;\n } else {\n v10 = v7;\n if (v9 >= v7) v7 = *v6;\n if (v9 >= v8) v7 = v10;\n }\n ++v6;\n } while (&v13[v3] != v6);\n v11 = 0LL;\n while (v13[v11] != v7) {\n if (++v11 == v3) return 0LL;\n }\n return s2[(int)v11];\n}", + "ida_pseudo_norm": "char *func0(char **a1, int a2) {\n char **v2;\n int v3;\n const char *v4;\n long long v5;\n int *v6;\n int v7;\n int v8;\n int v9;\n int v10;\n long long v11;\n uint32_t v13[100];\n char *s2[109];\n s2[101] = (char *)__readfsqword(40u);\n memset(v13, 0, sizeof(v13));\n if (a2 <= 0) return 0LL;\n v2 = a1;\n v3 = 0;\n do {\n if (v3 <= 0) {\n LABEL_4:\n s2[v3] = *v2;\n v13[v3++] = 1;\n } else {\n v4 = *v2;\n v5 = 0LL;\n while (strcmp(v4, s2[v5])) {\n if (++v5 == v3) goto LABEL_4;\n }\n ++v13[(int)v5];\n }\n ++v2;\n } while (v2 != &a1[a2]);\n if (v3 <= 0) return 0LL;\n v6 = v13;\n v7 = 0;\n v8 = 0;\n do {\n v9 = *v6;\n if (*v6 > v8) {\n v7 = v8;\n v8 = *v6;\n } else {\n v10 = v7;\n if (v9 >= v7) v7 = *v6;\n if (v9 >= v8) v7 = v10;\n }\n ++v6;\n } while (&v13[v3] != v6);\n v11 = 0LL;\n while (v13[v11] != v7) {\n if (++v11 == v3) return 0LL;\n }\n return s2[(int)v11];\n}" + }, + { + "index": 829, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* input[], int size) {\n int count[100] = {0};\n char* unique[100];\n int unique_count = 0;\n for (int i = 0; i < size; i++) {\n int found = 0;\n for (int j = 0; j < unique_count; j++) {\n if (strcmp(input[i], unique[j]) == 0) {\n count[j]++;\n found = 1;\n break;\n }\n }\n if (!found) {\n unique[unique_count] = input[i];\n count[unique_count] = 1;\n unique_count++;\n }\n }\n int first = 0, second = 0;\n for (int i = 0; i < unique_count; i++) {\n if (count[i] > first) {\n second = first;\n first = count[i];\n }\n else if (count[i] > second && count[i] < first) {\n second = count[i];\n }\n }\n for (int i = 0; i < unique_count; i++) {\n if (count[i] == second) {\n return unique[i];\n }\n }\n return NULL;\n}", + "test": "int main() {\n\n char* arr1[] = {\"aaa\",\"bbb\",\"ccc\",\"bbb\",\"aaa\",\"aaa\"};\n\n assert(strcmp(func0(arr1, 6), \"bbb\") == 0);\n\n\n\n char* arr2[] = {\"abc\",\"bcd\",\"abc\",\"bcd\",\"bcd\",\"bcd\"};\n\n assert(strcmp(func0(arr2, 6), \"abc\") == 0);\n\n\n\n char* arr3[] = {\"cdma\",\"gsm\",\"hspa\",\"gsm\",\"cdma\",\"cdma\"};\n\n assert(strcmp(func0(arr3, 6), \"gsm\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmov $0x32,%ecx\npush %r14\npush %r13\nmov %rdi,%r13\npush %r12\npush %rbp\npush %rbx\nsub $0x4e8,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x4d8(%rsp)\nxor %eax,%eax\nlea 0x20(%rsp),%rdi\nmov %rdi,0x10(%rsp)\nrep stos %rax,%es:(%rdi)\ntest %esi,%esi\njle 148c \nlea -0x1(%rsi),%eax\nmovl $0x0,0xc(%rsp)\nlea 0x8(%r13,%rax,8),%rax\nmov %rax,0x18(%rsp)\nnopw 0x0(%rax,%rax,1)\nmov 0xc(%rsp),%eax\nmov 0x0(%r13),%rbp\ntest %eax,%eax\nje 1468 \nmov 0xc(%rsp),%eax\nxor %r14d,%r14d\nlea 0x1b0(%rsp),%r15\nlea -0x1(%rax),%r12d\njmp 13d8 \nnopl (%rax)\nlea 0x1(%r14),%rax\ncmp %r12,%r14\nje 1468 \nmov %rax,%r14\nmov (%r15,%r14,8),%rsi\nmov %rbp,%rdi\nmovslq %r14d,%rbx\ncallq 1090 \ntest %eax,%eax\njne 13c8 \naddl $0x1,0x20(%rsp,%rbx,4)\nadd $0x8,%r13\ncmp 0x18(%rsp),%r13\njne 13a0 \nmov 0xc(%rsp),%edx\nmov 0x10(%rsp),%rax\nxor %ecx,%ecx\nxor %esi,%esi\nlea -0x1(%rdx),%edi\nlea 0x24(%rsp,%rdi,4),%r8\njmp 1428 \nnopw 0x0(%rax,%rax,1)\njge 141f \ncmp %ecx,%edx\ncmovg %edx,%ecx\nadd $0x4,%rax\ncmp %r8,%rax\nje 143b \nmov (%rax),%edx\ncmp %esi,%edx\njle 1418 \nadd $0x4,%rax\nmov %esi,%ecx\nmov %edx,%esi\ncmp %r8,%rax\njne 1428 \nxor %eax,%eax\njmp 144c \nlea 0x1(%rax),%rdx\ncmp %rax,%rdi\nje 148c \nmov %rdx,%rax\nmov 0x10(%rsp),%rbx\nmovslq %eax,%rdx\ncmp %ecx,(%rbx,%rax,4)\njne 1440 \nmov 0x1b0(%rsp,%rdx,8),%rax\njmp 148e \nnopl 0x0(%rax,%rax,1)\nmovslq 0xc(%rsp),%rax\nmov %rax,%rcx\nmov %rbp,0x1b0(%rsp,%rax,8)\nadd $0x1,%ecx\nmovl $0x1,0x20(%rsp,%rax,4)\nmov %ecx,0xc(%rsp)\njmpq 13f0 \nxor %eax,%eax\nmov 0x4d8(%rsp),%rdx\nxor %fs:0x28,%rdx\njne 14b3 \nadd $0x4e8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\ncallq 1070 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov ecx, 32h ; '2'\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 4D8h\nmov rax, fs:28h\nmov [rsp+508h+var_40], rax\nxor eax, eax\nlea rdi, [rsp+508h+var_4F8]\nmov [rsp+508h+var_508], rdi\nrep stosq\ntest esi, esi\njle loc_14DE\nmovsxd rsi, esi\nxor r13d, r13d\nlea rax, [r12+rsi*8]\nmov [rsp+508h+var_500], rax\nnop dword ptr [rax+rax+00h]\nloc_13F8:\nmov rbx, [r12]\nmovsxd rbp, r13d\nlea r15, [rsp+508h+var_368]\ntest r13d, r13d\njle short loc_1450\nloc_140C:\nxor r14d, r14d\njmp short loc_1421\nloc_1418:\nadd r14, 1\ncmp rbp, r14\njz short loc_1450\nloc_1421:\nmov rsi, [r15+r14*8]; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1418\nmov rax, [rsp+508h+var_500]\nmovsxd rdx, r14d\nadd r12, 8\nadd [rsp+rdx*4+508h+var_4F8], 1\ncmp r12, rax\njz short loc_1472\nmov rbx, [r12]\njmp short loc_140C\nloc_1450:\nmov rax, [rsp+508h+var_500]\nadd r12, 8\nadd r13d, 1\nmov [rsp+rbp*8+508h+var_368], rbx\nmov [rsp+rbp*4+508h+var_4F8], 1\ncmp r12, rax\njnz short loc_13F8\nloc_1472:\ntest r13d, r13d\njle short loc_14DE\nmov rcx, [rsp+508h+var_508]\nmovsxd r13, r13d\nxor esi, esi\nmov rax, rcx\nlea rdi, [rcx+r13*4]\nxor ecx, ecx\njmp short loc_14A0\nloc_1490:\njle short loc_1497\ncmp edx, ecx\ncmovge ecx, edx\nloc_1497:\nadd rax, 4\ncmp rdi, rax\njz short loc_14B3\nloc_14A0:\nmov edx, [rax]\ncmp esi, edx\njge short loc_1490\nadd rax, 4\nmov ecx, esi\nmov esi, edx\ncmp rdi, rax\njnz short loc_14A0\nloc_14B3:\nxor eax, eax\njmp short loc_14C9\nloc_14C0:\nadd rax, 1\ncmp rax, r13\njz short loc_14DE\nloc_14C9:\nmov rdx, [rsp+508h+var_508]\ncmp [rdx+rax*4], ecx\njnz short loc_14C0\ncdqe\nmov rax, [rsp+rax*8+508h+var_368]\njmp short loc_14E0\nloc_14DE:\nxor eax, eax\nloc_14E0:\nmov rdx, [rsp+508h+var_40]\nsub rdx, fs:28h\njnz short loc_1505\nadd rsp, 4D8h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1505:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(const char **a1, int a2)\n{\n const char **v2; // r12\n int v3; // r13d\n const char *v4; // rbx\n __int64 v5; // rbp\n __int64 v6; // r14\n int v7; // esi\n int *v8; // rax\n int *v9; // rdi\n int v10; // ecx\n int v11; // edx\n __int64 v12; // rax\n const char **v14; // [rsp+8h] [rbp-500h]\n _DWORD v15[302]; // [rsp+10h] [rbp-4F8h] BYREF\n unsigned __int64 v16; // [rsp+4C8h] [rbp-40h]\n\n v2 = a1;\n v16 = __readfsqword(0x28u);\n memset(v15, 0, 0x190uLL);\n if ( a2 <= 0 )\n return 0LL;\n v3 = 0;\n v14 = &a1[a2];\n while ( 1 )\n {\n v4 = *v2;\n v5 = v3;\n if ( v3 > 0 )\n break;\nLABEL_9:\n ++v2;\n ++v3;\n *(_QWORD *)&v15[2 * v5 + 100] = v4;\n v15[v5] = 1;\n if ( v2 == v14 )\n goto LABEL_10;\n }\n while ( 1 )\n {\n v6 = 0LL;\n while ( strcmp(v4, *(const char **)&v15[2 * v6 + 100]) )\n {\n if ( v3 == ++v6 )\n goto LABEL_9;\n }\n ++v2;\n ++v15[(int)v6];\n if ( v2 == v14 )\n break;\n v4 = *v2;\n }\nLABEL_10:\n if ( v3 <= 0 )\n return 0LL;\n v7 = 0;\n v8 = v15;\n v9 = &v15[v3];\n v10 = 0;\n do\n {\n while ( 1 )\n {\n v11 = *v8;\n if ( v7 >= *v8 )\n break;\n ++v8;\n v10 = v7;\n v7 = v11;\n if ( v9 == v8 )\n goto LABEL_18;\n }\n if ( v7 > v11 && v11 >= v10 )\n v10 = *v8;\n ++v8;\n }\n while ( v9 != v8 );\nLABEL_18:\n v12 = 0LL;\n while ( v15[v12] != v10 )\n {\n if ( ++v12 == v3 )\n return 0LL;\n }\n return *(_QWORD *)&v15[2 * (int)v12 + 100];\n}", + "ida_strip_asm": "sub_13A0:\nendbr64\npush r15\nmov ecx, 32h ; '2'\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 4D8h\nmov rax, fs:28h\nmov [rsp+508h+var_40], rax\nxor eax, eax\nlea rdi, [rsp+508h+var_4F8]\nmov [rsp+508h+var_508], rdi\nrep stosq\ntest esi, esi\njle loc_14DE\nmovsxd rsi, esi\nxor r13d, r13d\nlea rax, [r12+rsi*8]\nmov [rsp+508h+var_500], rax\nnop dword ptr [rax+rax+00h]\nloc_13F8:\nmov rbx, [r12]\nmovsxd rbp, r13d\nlea r15, [rsp+508h+var_368]\ntest r13d, r13d\njle short loc_1450\nloc_140C:\nxor r14d, r14d\njmp short loc_1421\nloc_1418:\nadd r14, 1\ncmp rbp, r14\njz short loc_1450\nloc_1421:\nmov rsi, [r15+r14*8]; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1418\nmov rax, [rsp+508h+var_500]\nmovsxd rdx, r14d\nadd r12, 8\nadd [rsp+rdx*4+508h+var_4F8], 1\ncmp r12, rax\njz short loc_1472\nmov rbx, [r12]\njmp short loc_140C\nloc_1450:\nmov rax, [rsp+508h+var_500]\nadd r12, 8\nadd r13d, 1\nmov [rsp+rbp*8+508h+var_368], rbx\nmov [rsp+rbp*4+508h+var_4F8], 1\ncmp r12, rax\njnz short loc_13F8\nloc_1472:\ntest r13d, r13d\njle short loc_14DE\nmov rcx, [rsp+508h+var_508]\nmovsxd r13, r13d\nxor esi, esi\nmov rax, rcx\nlea rdi, [rcx+r13*4]\nxor ecx, ecx\njmp short loc_14A0\nloc_1490:\njle short loc_1497\ncmp edx, ecx\ncmovge ecx, edx\nloc_1497:\nadd rax, 4\ncmp rdi, rax\njz short loc_14B3\nloc_14A0:\nmov edx, [rax]\ncmp esi, edx\njge short loc_1490\nadd rax, 4\nmov ecx, esi\nmov esi, edx\ncmp rdi, rax\njnz short loc_14A0\nloc_14B3:\nxor eax, eax\njmp short loc_14C9\nloc_14C0:\nadd rax, 1\ncmp rax, r13\njz short loc_14DE\nloc_14C9:\nmov rdx, [rsp+508h+var_508]\ncmp [rdx+rax*4], ecx\njnz short loc_14C0\ncdqe\nmov rax, [rsp+rax*8+508h+var_368]\njmp short loc_14E0\nloc_14DE:\nxor eax, eax\nloc_14E0:\nmov rdx, [rsp+508h+var_40]\nsub rdx, fs:28h\njnz short loc_1505\nadd rsp, 4D8h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1505:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_13A0(const char **a1, int a2)\n{\n const char **v2; // r12\n int v3; // r13d\n const char *v4; // rbx\n __int64 v5; // rbp\n __int64 v6; // r14\n int v7; // esi\n int *v8; // rax\n int *v9; // rdi\n int v10; // ecx\n int v11; // edx\n __int64 v12; // rax\n const char **v14; // [rsp+8h] [rbp-500h]\n _DWORD v15[302]; // [rsp+10h] [rbp-4F8h] BYREF\n unsigned __int64 v16; // [rsp+4C8h] [rbp-40h]\n\n v2 = a1;\n v16 = __readfsqword(0x28u);\n memset(v15, 0, 0x190uLL);\n if ( a2 <= 0 )\n return 0LL;\n v3 = 0;\n v14 = &a1[a2];\n while ( 1 )\n {\n v4 = *v2;\n v5 = v3;\n if ( v3 > 0 )\n break;\nLABEL_9:\n ++v2;\n ++v3;\n *(_QWORD *)&v15[2 * v5 + 100] = v4;\n v15[v5] = 1;\n if ( v2 == v14 )\n goto LABEL_10;\n }\n while ( 1 )\n {\n v6 = 0LL;\n while ( strcmp(v4, *(const char **)&v15[2 * v6 + 100]) )\n {\n if ( v3 == ++v6 )\n goto LABEL_9;\n }\n ++v2;\n ++v15[(int)v6];\n if ( v2 == v14 )\n break;\n v4 = *v2;\n }\nLABEL_10:\n if ( v3 <= 0 )\n return 0LL;\n v7 = 0;\n v8 = v15;\n v9 = &v15[v3];\n v10 = 0;\n do\n {\n while ( 1 )\n {\n v11 = *v8;\n if ( v7 >= *v8 )\n break;\n ++v8;\n v10 = v7;\n v7 = v11;\n if ( v9 == v8 )\n goto LABEL_18;\n }\n if ( v7 > v11 && v11 >= v10 )\n v10 = *v8;\n ++v8;\n }\n while ( v9 != v8 );\nLABEL_18:\n v12 = 0LL;\n while ( v15[v12] != v10 )\n {\n if ( ++v12 == v3 )\n return 0LL;\n }\n return *(_QWORD *)&v15[2 * (int)v12 + 100];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_13A0(const char **a1, int a2) {\n const char **v2;\n int v3;\n const char *v4;\n long long v5;\n long long v6;\n int v7;\n int *v8;\n int *v9;\n int v10;\n int v11;\n long long v12;\n const char **v14;\n uint32_t v15[302];\n unsigned long long v16;\n v2 = a1;\n v16 = __readfsqword(40u);\n memset(v15, 0, 400uLL);\n if (a2 <= 0) return 0LL;\n v3 = 0;\n v14 = &a1[a2];\n while (1) {\n v4 = *v2;\n v5 = v3;\n if (v3 > 0) break;\n LABEL_9:\n ++v2;\n ++v3;\n *(uint64_t *)&v15[2 * v5 + 100] = v4;\n v15[v5] = 1;\n if (v2 == v14) goto LABEL_10;\n }\n while (1) {\n v6 = 0LL;\n while (strcmp(v4, *(const char **)&v15[2 * v6 + 100])) {\n if (v3 == ++v6) goto LABEL_9;\n }\n ++v2;\n ++v15[(int)v6];\n if (v2 == v14) break;\n v4 = *v2;\n }\nLABEL_10:\n if (v3 <= 0) return 0LL;\n v7 = 0;\n v8 = v15;\n v9 = &v15[v3];\n v10 = 0;\n do {\n while (1) {\n v11 = *v8;\n if (v7 >= *v8) break;\n ++v8;\n v10 = v7;\n v7 = v11;\n if (v9 == v8) goto LABEL_18;\n }\n if (v7 > v11 && v11 >= v10) v10 = *v8;\n ++v8;\n } while (v9 != v8);\nLABEL_18:\n v12 = 0LL;\n while (v15[v12] != v10) {\n if (++v12 == v3) return 0LL;\n }\n return *(uint64_t *)&v15[2 * (int)v12 + 100];\n}", + "ida_pseudo_norm": "long long func0(const char **a1, int a2) {\n const char **v2;\n int v3;\n const char *v4;\n long long v5;\n long long v6;\n int v7;\n int *v8;\n int *v9;\n int v10;\n int v11;\n long long v12;\n const char **v14;\n uint32_t v15[302];\n unsigned long long v16;\n v2 = a1;\n v16 = __readfsqword(40u);\n memset(v15, 0, 400uLL);\n if (a2 <= 0) return 0LL;\n v3 = 0;\n v14 = &a1[a2];\n while (1) {\n v4 = *v2;\n v5 = v3;\n if (v3 > 0) break;\n LABEL_9:\n ++v2;\n ++v3;\n *(uint64_t *)&v15[2 * v5 + 100] = v4;\n v15[v5] = 1;\n if (v2 == v14) goto LABEL_10;\n }\n while (1) {\n v6 = 0LL;\n while (strcmp(v4, *(const char **)&v15[2 * v6 + 100])) {\n if (v3 == ++v6) goto LABEL_9;\n }\n ++v2;\n ++v15[(int)v6];\n if (v2 == v14) break;\n v4 = *v2;\n }\nLABEL_10:\n if (v3 <= 0) return 0LL;\n v7 = 0;\n v8 = v15;\n v9 = &v15[v3];\n v10 = 0;\n do {\n while (1) {\n v11 = *v8;\n if (v7 >= *v8) break;\n ++v8;\n v10 = v7;\n v7 = v11;\n if (v9 == v8) goto LABEL_18;\n }\n if (v7 > v11 && v11 >= v10) v10 = *v8;\n ++v8;\n } while (v9 != v8);\nLABEL_18:\n v12 = 0LL;\n while (v15[v12] != v10) {\n if (++v12 == v3) return 0LL;\n }\n return *(uint64_t *)&v15[2 * (int)v12 + 100];\n}" + }, + { + "index": 829, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* input[], int size) {\n int count[100] = {0};\n char* unique[100];\n int unique_count = 0;\n for (int i = 0; i < size; i++) {\n int found = 0;\n for (int j = 0; j < unique_count; j++) {\n if (strcmp(input[i], unique[j]) == 0) {\n count[j]++;\n found = 1;\n break;\n }\n }\n if (!found) {\n unique[unique_count] = input[i];\n count[unique_count] = 1;\n unique_count++;\n }\n }\n int first = 0, second = 0;\n for (int i = 0; i < unique_count; i++) {\n if (count[i] > first) {\n second = first;\n first = count[i];\n }\n else if (count[i] > second && count[i] < first) {\n second = count[i];\n }\n }\n for (int i = 0; i < unique_count; i++) {\n if (count[i] == second) {\n return unique[i];\n }\n }\n return NULL;\n}", + "test": "int main() {\n\n char* arr1[] = {\"aaa\",\"bbb\",\"ccc\",\"bbb\",\"aaa\",\"aaa\"};\n\n assert(strcmp(func0(arr1, 6), \"bbb\") == 0);\n\n\n\n char* arr2[] = {\"abc\",\"bcd\",\"abc\",\"bcd\",\"bcd\",\"bcd\"};\n\n assert(strcmp(func0(arr2, 6), \"abc\") == 0);\n\n\n\n char* arr3[] = {\"cdma\",\"gsm\",\"hspa\",\"gsm\",\"cdma\",\"cdma\"};\n\n assert(strcmp(func0(arr3, 6), \"gsm\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmov $0x32,%ecx\npush %r14\npush %r13\nmov %rdi,%r13\npush %r12\npush %rbp\npush %rbx\nsub $0x4e8,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x4d8(%rsp)\nxor %eax,%eax\nlea 0x20(%rsp),%rdi\nmov %rdi,0x10(%rsp)\nrep stos %rax,%es:(%rdi)\ntest %esi,%esi\njle 14b4 \nlea -0x1(%rsi),%eax\nmovl $0x0,0xc(%rsp)\nlea 0x8(%r13,%rax,8),%rax\nmov %rax,0x18(%rsp)\nnopw 0x0(%rax,%rax,1)\nmov 0xc(%rsp),%eax\nmov 0x0(%r13),%rbp\ntest %eax,%eax\nje 1490 \nmov 0xc(%rsp),%eax\nxor %r14d,%r14d\nlea 0x1b0(%rsp),%r15\nlea -0x1(%rax),%r12d\njmp 13f8 \nnopl (%rax)\nlea 0x1(%r14),%rax\ncmp %r12,%r14\nje 1490 \nmov %rax,%r14\nmov (%r15,%r14,8),%rsi\nmov %rbp,%rdi\nmovslq %r14d,%rbx\ncallq 1090 \ntest %eax,%eax\njne 13e8 \naddl $0x1,0x20(%rsp,%rbx,4)\nadd $0x8,%r13\ncmp 0x18(%rsp),%r13\njne 13c0 \nmov 0xc(%rsp),%edx\nmov 0x10(%rsp),%rax\nxor %ecx,%ecx\nxor %esi,%esi\nlea -0x1(%rdx),%edi\nlea 0x24(%rsp,%rdi,4),%r8\njmp 1448 \nnopw 0x0(%rax,%rax,1)\njge 143f \ncmp %ecx,%edx\ncmovg %edx,%ecx\nadd $0x4,%rax\ncmp %rax,%r8\nje 145b \nmov (%rax),%edx\ncmp %esi,%edx\njle 1438 \nadd $0x4,%rax\nmov %esi,%ecx\nmov %edx,%esi\ncmp %rax,%r8\njne 1448 \nmov 0x10(%rsp),%rbx\nxor %eax,%eax\njmp 1474 \nnopl 0x0(%rax)\nlea 0x1(%rax),%rdx\ncmp %rdi,%rax\nje 14b4 \nmov %rdx,%rax\nmovslq %eax,%rdx\ncmp (%rbx,%rax,4),%ecx\njne 1468 \nmov 0x1b0(%rsp,%rdx,8),%rax\njmp 14b6 \nnopw %cs:0x0(%rax,%rax,1)\nmovslq 0xc(%rsp),%rax\nmov %rax,%rcx\nmov %rbp,0x1b0(%rsp,%rax,8)\nadd $0x1,%ecx\nmovl $0x1,0x20(%rsp,%rax,4)\nmov %ecx,0xc(%rsp)\njmpq 1410 \nxor %eax,%eax\nmov 0x4d8(%rsp),%rdx\nxor %fs:0x28,%rdx\njne 14db \nadd $0x4e8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\ncallq 1070 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov ecx, 32h ; '2'\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 4D8h\nmov rax, fs:28h\nmov [rsp+508h+var_40], rax\nxor eax, eax\nlea rdi, [rsp+508h+var_4F8]\nmov [rsp+508h+var_508], rdi\nrep stosq\ntest esi, esi\njle loc_14DE\nmovsxd rsi, esi\nxor r13d, r13d\nlea rax, [r12+rsi*8]\nmov [rsp+508h+var_500], rax\nnop dword ptr [rax+rax+00h]\nloc_13F8:\nmov rbx, [r12]\nmovsxd rbp, r13d\nlea r15, [rsp+508h+var_368]\ntest r13d, r13d\njle short loc_1450\nloc_140C:\nxor r14d, r14d\njmp short loc_1421\nloc_1418:\nadd r14, 1\ncmp r14, rbp\njz short loc_1450\nloc_1421:\nmov rsi, [r15+r14*8]; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1418\nmov rax, [rsp+508h+var_500]\nmovsxd rdx, r14d\nadd r12, 8\nadd [rsp+rdx*4+508h+var_4F8], 1\ncmp r12, rax\njz short loc_1472\nmov rbx, [r12]\njmp short loc_140C\nloc_1450:\nmov rax, [rsp+508h+var_500]\nadd r12, 8\nadd r13d, 1\nmov [rsp+rbp*8+508h+var_368], rbx\nmov [rsp+rbp*4+508h+var_4F8], 1\ncmp r12, rax\njnz short loc_13F8\nloc_1472:\ntest r13d, r13d\njle short loc_14DE\nmov rcx, [rsp+508h+var_508]\nmovsxd r13, r13d\nxor esi, esi\nmov rax, rcx\nlea rdi, [rcx+r13*4]\nxor ecx, ecx\njmp short loc_14A0\nloc_1490:\njge short loc_1497\ncmp edx, ecx\ncmovge ecx, edx\nloc_1497:\nadd rax, 4\ncmp rdi, rax\njz short loc_14B3\nloc_14A0:\nmov edx, [rax]\ncmp edx, esi\njle short loc_1490\nadd rax, 4\nmov ecx, esi\nmov esi, edx\ncmp rdi, rax\njnz short loc_14A0\nloc_14B3:\nxor eax, eax\njmp short loc_14C9\nloc_14C0:\nadd rax, 1\ncmp r13, rax\njz short loc_14DE\nloc_14C9:\nmov rdx, [rsp+508h+var_508]\ncmp [rdx+rax*4], ecx\njnz short loc_14C0\ncdqe\nmov rax, [rsp+rax*8+508h+var_368]\njmp short loc_14E0\nloc_14DE:\nxor eax, eax\nloc_14E0:\nmov rdx, [rsp+508h+var_40]\nsub rdx, fs:28h\njnz short loc_1505\nadd rsp, 4D8h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1505:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(const char **a1, int a2)\n{\n const char **v2; // r12\n int v3; // r13d\n const char *v4; // rbx\n __int64 v5; // rbp\n __int64 v6; // r14\n int v7; // esi\n int *v8; // rax\n int *v9; // rdi\n int v10; // ecx\n int v11; // edx\n __int64 v12; // rax\n const char **v14; // [rsp+8h] [rbp-500h]\n _DWORD v15[302]; // [rsp+10h] [rbp-4F8h] BYREF\n unsigned __int64 v16; // [rsp+4C8h] [rbp-40h]\n\n v2 = a1;\n v16 = __readfsqword(0x28u);\n memset(v15, 0, 0x190uLL);\n if ( a2 <= 0 )\n return 0LL;\n v3 = 0;\n v14 = &a1[a2];\n while ( 1 )\n {\n v4 = *v2;\n v5 = v3;\n if ( v3 > 0 )\n break;\nLABEL_9:\n ++v2;\n ++v3;\n *(_QWORD *)&v15[2 * v5 + 100] = v4;\n v15[v5] = 1;\n if ( v2 == v14 )\n goto LABEL_10;\n }\n while ( 1 )\n {\n v6 = 0LL;\n while ( strcmp(v4, *(const char **)&v15[2 * v6 + 100]) )\n {\n if ( ++v6 == v3 )\n goto LABEL_9;\n }\n ++v2;\n ++v15[(int)v6];\n if ( v2 == v14 )\n break;\n v4 = *v2;\n }\nLABEL_10:\n if ( v3 <= 0 )\n return 0LL;\n v7 = 0;\n v8 = v15;\n v9 = &v15[v3];\n v10 = 0;\n do\n {\n while ( 1 )\n {\n v11 = *v8;\n if ( *v8 <= v7 )\n break;\n ++v8;\n v10 = v7;\n v7 = v11;\n if ( v9 == v8 )\n goto LABEL_18;\n }\n if ( v11 < v7 && v11 >= v10 )\n v10 = *v8;\n ++v8;\n }\n while ( v9 != v8 );\nLABEL_18:\n v12 = 0LL;\n while ( v15[v12] != v10 )\n {\n if ( v3 == ++v12 )\n return 0LL;\n }\n return *(_QWORD *)&v15[2 * (int)v12 + 100];\n}", + "ida_strip_asm": "sub_13A0:\nendbr64\npush r15\nmov ecx, 32h ; '2'\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 4D8h\nmov rax, fs:28h\nmov [rsp+508h+var_40], rax\nxor eax, eax\nlea rdi, [rsp+508h+var_4F8]\nmov [rsp+508h+var_508], rdi\nrep stosq\ntest esi, esi\njle loc_14DE\nmovsxd rsi, esi\nxor r13d, r13d\nlea rax, [r12+rsi*8]\nmov [rsp+508h+var_500], rax\nnop dword ptr [rax+rax+00h]\nloc_13F8:\nmov rbx, [r12]\nmovsxd rbp, r13d\nlea r15, [rsp+508h+var_368]\ntest r13d, r13d\njle short loc_1450\nloc_140C:\nxor r14d, r14d\njmp short loc_1421\nloc_1418:\nadd r14, 1\ncmp r14, rbp\njz short loc_1450\nloc_1421:\nmov rsi, [r15+r14*8]; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1418\nmov rax, [rsp+508h+var_500]\nmovsxd rdx, r14d\nadd r12, 8\nadd [rsp+rdx*4+508h+var_4F8], 1\ncmp r12, rax\njz short loc_1472\nmov rbx, [r12]\njmp short loc_140C\nloc_1450:\nmov rax, [rsp+508h+var_500]\nadd r12, 8\nadd r13d, 1\nmov [rsp+rbp*8+508h+var_368], rbx\nmov [rsp+rbp*4+508h+var_4F8], 1\ncmp r12, rax\njnz short loc_13F8\nloc_1472:\ntest r13d, r13d\njle short loc_14DE\nmov rcx, [rsp+508h+var_508]\nmovsxd r13, r13d\nxor esi, esi\nmov rax, rcx\nlea rdi, [rcx+r13*4]\nxor ecx, ecx\njmp short loc_14A0\nloc_1490:\njge short loc_1497\ncmp edx, ecx\ncmovge ecx, edx\nloc_1497:\nadd rax, 4\ncmp rdi, rax\njz short loc_14B3\nloc_14A0:\nmov edx, [rax]\ncmp edx, esi\njle short loc_1490\nadd rax, 4\nmov ecx, esi\nmov esi, edx\ncmp rdi, rax\njnz short loc_14A0\nloc_14B3:\nxor eax, eax\njmp short loc_14C9\nloc_14C0:\nadd rax, 1\ncmp r13, rax\njz short loc_14DE\nloc_14C9:\nmov rdx, [rsp+508h+var_508]\ncmp [rdx+rax*4], ecx\njnz short loc_14C0\ncdqe\nmov rax, [rsp+rax*8+508h+var_368]\njmp short loc_14E0\nloc_14DE:\nxor eax, eax\nloc_14E0:\nmov rdx, [rsp+508h+var_40]\nsub rdx, fs:28h\njnz short loc_1505\nadd rsp, 4D8h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1505:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_13A0(const char **a1, int a2)\n{\n const char **v2; // r12\n int v3; // r13d\n const char *v4; // rbx\n __int64 v5; // rbp\n __int64 v6; // r14\n int v7; // esi\n int *v8; // rax\n int *v9; // rdi\n int v10; // ecx\n int v11; // edx\n __int64 v12; // rax\n const char **v14; // [rsp+8h] [rbp-500h]\n _DWORD v15[302]; // [rsp+10h] [rbp-4F8h] BYREF\n unsigned __int64 v16; // [rsp+4C8h] [rbp-40h]\n\n v2 = a1;\n v16 = __readfsqword(0x28u);\n memset(v15, 0, 0x190uLL);\n if ( a2 <= 0 )\n return 0LL;\n v3 = 0;\n v14 = &a1[a2];\n while ( 1 )\n {\n v4 = *v2;\n v5 = v3;\n if ( v3 > 0 )\n break;\nLABEL_9:\n ++v2;\n ++v3;\n *(_QWORD *)&v15[2 * v5 + 100] = v4;\n v15[v5] = 1;\n if ( v2 == v14 )\n goto LABEL_10;\n }\n while ( 1 )\n {\n v6 = 0LL;\n while ( strcmp(v4, *(const char **)&v15[2 * v6 + 100]) )\n {\n if ( ++v6 == v3 )\n goto LABEL_9;\n }\n ++v2;\n ++v15[(int)v6];\n if ( v2 == v14 )\n break;\n v4 = *v2;\n }\nLABEL_10:\n if ( v3 <= 0 )\n return 0LL;\n v7 = 0;\n v8 = v15;\n v9 = &v15[v3];\n v10 = 0;\n do\n {\n while ( 1 )\n {\n v11 = *v8;\n if ( *v8 <= v7 )\n break;\n ++v8;\n v10 = v7;\n v7 = v11;\n if ( v9 == v8 )\n goto LABEL_18;\n }\n if ( v11 < v7 && v11 >= v10 )\n v10 = *v8;\n ++v8;\n }\n while ( v9 != v8 );\nLABEL_18:\n v12 = 0LL;\n while ( v15[v12] != v10 )\n {\n if ( v3 == ++v12 )\n return 0LL;\n }\n return *(_QWORD *)&v15[2 * (int)v12 + 100];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_13A0(const char **a1, int a2) {\n const char **v2;\n int v3;\n const char *v4;\n long long v5;\n long long v6;\n int v7;\n int *v8;\n int *v9;\n int v10;\n int v11;\n long long v12;\n const char **v14;\n uint32_t v15[302];\n unsigned long long v16;\n v2 = a1;\n v16 = __readfsqword(40u);\n memset(v15, 0, 400uLL);\n if (a2 <= 0) return 0LL;\n v3 = 0;\n v14 = &a1[a2];\n while (1) {\n v4 = *v2;\n v5 = v3;\n if (v3 > 0) break;\n LABEL_9:\n ++v2;\n ++v3;\n *(uint64_t *)&v15[2 * v5 + 100] = v4;\n v15[v5] = 1;\n if (v2 == v14) goto LABEL_10;\n }\n while (1) {\n v6 = 0LL;\n while (strcmp(v4, *(const char **)&v15[2 * v6 + 100])) {\n if (++v6 == v3) goto LABEL_9;\n }\n ++v2;\n ++v15[(int)v6];\n if (v2 == v14) break;\n v4 = *v2;\n }\nLABEL_10:\n if (v3 <= 0) return 0LL;\n v7 = 0;\n v8 = v15;\n v9 = &v15[v3];\n v10 = 0;\n do {\n while (1) {\n v11 = *v8;\n if (*v8 <= v7) break;\n ++v8;\n v10 = v7;\n v7 = v11;\n if (v9 == v8) goto LABEL_18;\n }\n if (v11 < v7 && v11 >= v10) v10 = *v8;\n ++v8;\n } while (v9 != v8);\nLABEL_18:\n v12 = 0LL;\n while (v15[v12] != v10) {\n if (v3 == ++v12) return 0LL;\n }\n return *(uint64_t *)&v15[2 * (int)v12 + 100];\n}", + "ida_pseudo_norm": "long long func0(const char **a1, int a2) {\n const char **v2;\n int v3;\n const char *v4;\n long long v5;\n long long v6;\n int v7;\n int *v8;\n int *v9;\n int v10;\n int v11;\n long long v12;\n const char **v14;\n uint32_t v15[302];\n unsigned long long v16;\n v2 = a1;\n v16 = __readfsqword(40u);\n memset(v15, 0, 400uLL);\n if (a2 <= 0) return 0LL;\n v3 = 0;\n v14 = &a1[a2];\n while (1) {\n v4 = *v2;\n v5 = v3;\n if (v3 > 0) break;\n LABEL_9:\n ++v2;\n ++v3;\n *(uint64_t *)&v15[2 * v5 + 100] = v4;\n v15[v5] = 1;\n if (v2 == v14) goto LABEL_10;\n }\n while (1) {\n v6 = 0LL;\n while (strcmp(v4, *(const char **)&v15[2 * v6 + 100])) {\n if (++v6 == v3) goto LABEL_9;\n }\n ++v2;\n ++v15[(int)v6];\n if (v2 == v14) break;\n v4 = *v2;\n }\nLABEL_10:\n if (v3 <= 0) return 0LL;\n v7 = 0;\n v8 = v15;\n v9 = &v15[v3];\n v10 = 0;\n do {\n while (1) {\n v11 = *v8;\n if (*v8 <= v7) break;\n ++v8;\n v10 = v7;\n v7 = v11;\n if (v9 == v8) goto LABEL_18;\n }\n if (v11 < v7 && v11 >= v10) v10 = *v8;\n ++v8;\n } while (v9 != v8);\nLABEL_18:\n v12 = 0LL;\n while (v15[v12] != v10) {\n if (v3 == ++v12) return 0LL;\n }\n return *(uint64_t *)&v15[2 * (int)v12 + 100];\n}" + }, + { + "index": 830, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(double a, int digits) {\n double n = pow(10, -digits);\n return round(ceil(a / n) * n * pow(10, digits)) / pow(10, digits);\n}", + "test": "int main() {\n\n assert(func0(123.01247,0) == 124);\n\n assert(func0(123.01247,1) == 123.1);\n\n assert(func0(123.01247,2) == 123.02);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmovsd %xmm0,-0x18(%rbp)\nmov %edi,-0x1c(%rbp)\nmov -0x1c(%rbp),%eax\nneg %eax\ncvtsi2sd %eax,%xmm0\nmov 0xed3(%rip),%rax\nmovapd %xmm0,%xmm1\nmovq %rax,%xmm0\ncallq 1090 \nmovq %xmm0,%rax\nmov %rax,-0x8(%rbp)\nmovsd -0x18(%rbp),%xmm0\ndivsd -0x8(%rbp),%xmm0\ncallq 10b0 \nmulsd -0x8(%rbp),%xmm0\nmovsd %xmm0,-0x28(%rbp)\ncvtsi2sdl -0x1c(%rbp),%xmm0\nmov 0xe97(%rip),%rax\nmovapd %xmm0,%xmm1\nmovq %rax,%xmm0\ncallq 1090 \nmulsd -0x28(%rbp),%xmm0\ncallq 1080 \nmovsd %xmm0,-0x28(%rbp)\ncvtsi2sdl -0x1c(%rbp),%xmm0\nmov 0xe6e(%rip),%rax\nmovapd %xmm0,%xmm1\nmovq %rax,%xmm0\ncallq 1090 \nmovsd -0x28(%rbp),%xmm3\ndivsd %xmm0,%xmm3\nmovapd %xmm3,%xmm0\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmovsd [rbp+var_28], xmm0\nmov [rbp+var_2C], edi\nmov eax, [rbp+var_2C]\nneg eax\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmov rax, cs:x\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\nmovq rax, xmm0\nmov [rbp+var_18], rax\nmovsd xmm0, [rbp+var_28]\ndivsd xmm0, [rbp+var_18]\nmovq rax, xmm0\nmovq xmm0, rax; x\ncall _ceil\nmovq rax, xmm0\nmovq xmm2, rax\nmulsd xmm2, [rbp+var_18]\nmovsd [rbp+var_38], xmm2\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_2C]\nmov rax, cs:x\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\nmulsd xmm0, [rbp+var_38]\nmovq rax, xmm0\nmovq xmm0, rax; x\ncall _round\nmovq rbx, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_2C]\nmov rax, cs:x\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\nmovq xmm1, rbx\ndivsd xmm1, xmm0\nmovapd xmm0, xmm1\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int128 __usercall func0@(int a1@, double a2@)\n{\n double v2; // xmm0_8\n double v3; // rbx\n __int128 v4; // xmm1\n double v6; // [rsp+8h] [rbp-38h]\n double v8; // [rsp+28h] [rbp-18h]\n\n v8 = pow(10.0, (double)-a1);\n v6 = ceil(a2 / v8) * v8;\n v2 = pow(10.0, (double)a1);\n v3 = round(v2 * v6);\n v4 = *(unsigned __int64 *)&v3;\n *(double *)&v4 = v3 / pow(10.0, (double)a1);\n return v4;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmovsd [rbp+var_28], xmm0\nmov [rbp+var_2C], edi\nmov eax, [rbp+var_2C]\nneg eax\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmov rax, cs:x\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\nmovq rax, xmm0\nmov [rbp+var_18], rax\nmovsd xmm0, [rbp+var_28]\ndivsd xmm0, [rbp+var_18]\nmovq rax, xmm0\nmovq xmm0, rax; x\ncall _ceil\nmovq rax, xmm0\nmovq xmm2, rax\nmulsd xmm2, [rbp+var_18]\nmovsd [rbp+var_38], xmm2\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_2C]\nmov rax, cs:x\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\nmulsd xmm0, [rbp+var_38]\nmovq rax, xmm0\nmovq xmm0, rax; x\ncall _round\nmovq rbx, xmm0\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_2C]\nmov rax, cs:x\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\nmovq xmm1, rbx\ndivsd xmm1, xmm0\nmovapd xmm0, xmm1\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int128 __usercall sub_11A9@(int a1@, double a2@)\n{\n double v2; // xmm0_8\n double v3; // rbx\n __int128 v4; // xmm1\n double v6; // [rsp+8h] [rbp-38h]\n double v8; // [rsp+28h] [rbp-18h]\n\n v8 = pow(10.0, (double)-a1);\n v6 = ceil(a2 / v8) * v8;\n v2 = pow(10.0, (double)a1);\n v3 = round(v2 * v6);\n v4 = *(unsigned __int64 *)&v3;\n *(double *)&v4 = v3 / pow(10.0, (double)a1);\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__int128 __usercall sub_11A9 @(int a1 @, double a2 @) {\n double v2;\n double v3;\n __int128 v4;\n double v6;\n double v8;\n v8 = pow(10.0, (double)-a1);\n v6 = ceil(a2 / v8) * v8;\n v2 = pow(10.0, (double)a1);\n v3 = round(v2 * v6);\n v4 = *(unsigned long long *)&v3;\n *(double *)&v4 = v3 / pow(10.0, (double)a1);\n return v4;\n}", + "ida_pseudo_norm": "__int128 __usercall func0 @(int a1 @, double a2 @) {\n double v2;\n double v3;\n __int128 v4;\n double v6;\n double v8;\n v8 = pow(10.0, (double)-a1);\n v6 = ceil(a2 / v8) * v8;\n v2 = pow(10.0, (double)a1);\n v3 = round(v2 * v6);\n v4 = *(unsigned long long *)&v3;\n *(double *)&v4 = v3 / pow(10.0, (double)a1);\n return v4;\n}" + }, + { + "index": 830, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(double a, int digits) {\n double n = pow(10, -digits);\n return round(ceil(a / n) * n * pow(10, digits)) / pow(10, digits);\n}", + "test": "int main() {\n\n assert(func0(123.01247,0) == 124);\n\n assert(func0(123.01247,1) == 123.1);\n\n assert(func0(123.01247,2) == 123.02);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nsub $0x20,%rsp\nmovsd %xmm0,0x8(%rsp)\nmov %edi,%ebx\nmov %edi,%eax\nneg %eax\npxor %xmm1,%xmm1\ncvtsi2sd %eax,%xmm1\nmovsd 0xef2(%rip),%xmm0\ncallq 1080 \nmovsd %xmm0,0x18(%rsp)\nmovsd 0x8(%rsp),%xmm1\ndivsd %xmm0,%xmm1\nmovsd %xmm1,0x8(%rsp)\nmovsd 0xf0f(%rip),%xmm0\nmovapd %xmm1,%xmm2\nandpd %xmm0,%xmm2\nmovsd 0xec7(%rip),%xmm3\nucomisd %xmm2,%xmm3\njbe 121c \ncvttsd2si %xmm1,%rax\npxor %xmm2,%xmm2\ncvtsi2sd %rax,%xmm2\nmovapd %xmm1,%xmm3\ncmpnlesd %xmm2,%xmm3\nmovsd 0xeaa(%rip),%xmm4\nandpd %xmm4,%xmm3\naddsd %xmm3,%xmm2\nandnpd %xmm1,%xmm0\norpd %xmm0,%xmm2\nmovsd %xmm2,0x8(%rsp)\npxor %xmm6,%xmm6\ncvtsi2sd %ebx,%xmm6\nmovsd %xmm6,0x10(%rsp)\nmovapd %xmm6,%xmm1\nmov 0xe6b(%rip),%rax\nmovq %rax,%xmm0\ncallq 1080 \nmovapd %xmm0,%xmm1\nmovsd 0x8(%rsp),%xmm0\nmulsd 0x18(%rsp),%xmm0\nmulsd %xmm1,%xmm0\ncallq 1070 \nmovsd %xmm0,0x8(%rsp)\nmovsd 0x10(%rsp),%xmm1\nmov 0xe35(%rip),%rax\nmovq %rax,%xmm0\ncallq 1080 \nmovsd 0x8(%rsp),%xmm7\ndivsd %xmm0,%xmm7\nmovapd %xmm7,%xmm0\nadd $0x20,%rsp\npop %rbx\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbx\nsub rsp, 10h\nmovsd [rsp+18h+var_18], xmm0\nmov ebx, edi\nmov eax, edi\nneg eax\npxor xmm1, xmm1\ncvtsi2sd xmm1, eax; y\nmovsd xmm0, cs:x; x\ncall _pow\nmovsd [rsp+18h+var_10], xmm0\nmovsd xmm5, [rsp+18h+var_18]\ndivsd xmm5, xmm0\nmovsd [rsp+18h+var_18], xmm5\nmovsd xmm2, cs:qword_2098\nmovapd xmm1, xmm5\nandpd xmm1, xmm2\nmovsd xmm3, cs:qword_2088\nucomisd xmm3, xmm1\njbe short loc_1218\ncvttsd2si rax, xmm5\npxor xmm1, xmm1\ncvtsi2sd xmm1, rax\nmovapd xmm3, xmm5\ncmpnlesd xmm3, xmm1\nmovsd xmm4, cs:qword_2090\nandpd xmm3, xmm4\naddsd xmm1, xmm3\nandnpd xmm2, xmm5\norpd xmm1, xmm2\nmovsd [rsp+18h+var_18], xmm1\nloc_1218:\npxor xmm7, xmm7\ncvtsi2sd xmm7, ebx\nmovq rbx, xmm7\nmovapd xmm1, xmm7; y\nmovsd xmm0, cs:x; x\ncall _pow\nmovapd xmm1, xmm0\nmovsd xmm0, [rsp+18h+var_18]\nmulsd xmm0, [rsp+18h+var_10]\nmulsd xmm0, xmm1; x\ncall _round\nmovsd [rsp+18h+var_18], xmm0\nmovq xmm1, rbx; y\nmovsd xmm0, cs:x; x\ncall _pow\nmovapd xmm1, xmm0\nmovsd xmm0, [rsp+18h+var_18]\ndivsd xmm0, xmm1\nadd rsp, 10h\npop rbx\nretn", + "ida_pseudo": "double __fastcall func0(int a1, double a2)\n{\n __m128d v2; // xmm5\n __m128d v3; // xmm1\n double v4; // xmm0_8\n double v7; // [rsp+0h] [rbp-18h]\n double v8; // [rsp+0h] [rbp-18h]\n double v9; // [rsp+8h] [rbp-10h]\n\n v9 = pow(10.0, (double)-a1);\n v2 = (__m128d)*(unsigned __int64 *)&a2;\n v7 = a2 / v9;\n v2.m128d_f64[0] = v7;\n if ( fabs(v7) < 4.503599627370496e15 )\n {\n v3.m128d_f64[0] = (double)(int)v7;\n *(_QWORD *)&v7 = COERCE_UNSIGNED_INT64(v3.m128d_f64[0] + COERCE_DOUBLE(*(_OWORD *)&_mm_cmpgt_sd(v2, v3) & 0x3FF0000000000000LL)) | *(_QWORD *)&v7 & 0x8000000000000000LL;\n }\n v4 = pow(10.0, (double)a1);\n v8 = round(v7 * v9 * v4);\n return v8 / pow(10.0, (double)a1);\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbx\nsub rsp, 10h\nmovsd [rsp+18h+var_18], xmm0\nmov ebx, edi\nmov eax, edi\nneg eax\npxor xmm1, xmm1\ncvtsi2sd xmm1, eax; y\nmovsd xmm0, cs:x; x\ncall _pow\nmovsd [rsp+18h+var_10], xmm0\nmovsd xmm5, [rsp+18h+var_18]\ndivsd xmm5, xmm0\nmovsd [rsp+18h+var_18], xmm5\nmovsd xmm2, cs:qword_2098\nmovapd xmm1, xmm5\nandpd xmm1, xmm2\nmovsd xmm3, cs:qword_2088\nucomisd xmm3, xmm1\njbe short loc_1218\ncvttsd2si rax, xmm5\npxor xmm1, xmm1\ncvtsi2sd xmm1, rax\nmovapd xmm3, xmm5\ncmpnlesd xmm3, xmm1\nmovsd xmm4, cs:qword_2090\nandpd xmm3, xmm4\naddsd xmm1, xmm3\nandnpd xmm2, xmm5\norpd xmm1, xmm2\nmovsd [rsp+18h+var_18], xmm1\nloc_1218:\npxor xmm7, xmm7\ncvtsi2sd xmm7, ebx\nmovq rbx, xmm7\nmovapd xmm1, xmm7; y\nmovsd xmm0, cs:x; x\ncall _pow\nmovapd xmm1, xmm0\nmovsd xmm0, [rsp+18h+var_18]\nmulsd xmm0, [rsp+18h+var_10]\nmulsd xmm0, xmm1; x\ncall _round\nmovsd [rsp+18h+var_18], xmm0\nmovq xmm1, rbx; y\nmovsd xmm0, cs:x; x\ncall _pow\nmovapd xmm1, xmm0\nmovsd xmm0, [rsp+18h+var_18]\ndivsd xmm0, xmm1\nadd rsp, 10h\npop rbx\nretn", + "ida_strip_pseudo": "double __fastcall sub_1189(int a1, double a2)\n{\n __m128d v2; // xmm5\n __m128d v3; // xmm1\n double v4; // xmm0_8\n double v7; // [rsp+0h] [rbp-18h]\n double v8; // [rsp+0h] [rbp-18h]\n double v9; // [rsp+8h] [rbp-10h]\n\n v9 = pow(10.0, (double)-a1);\n v2 = (__m128d)*(unsigned __int64 *)&a2;\n v7 = a2 / v9;\n v2.m128d_f64[0] = v7;\n if ( fabs(v7) < 4.503599627370496e15 )\n {\n v3.m128d_f64[0] = (double)(int)v7;\n *(_QWORD *)&v7 = COERCE_UNSIGNED_INT64(v3.m128d_f64[0] + COERCE_DOUBLE(*(_OWORD *)&_mm_cmpgt_sd(v2, v3) & 0x3FF0000000000000LL)) | *(_QWORD *)&v7 & 0x8000000000000000LL;\n }\n v4 = pow(10.0, (double)a1);\n v8 = round(v7 * v9 * v4);\n return v8 / pow(10.0, (double)a1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1189(int a1, double a2) {\n __m128d v2;\n __m128d v3;\n double v4;\n double v7;\n double v8;\n double v9;\n v9 = pow(10.0, (double)-a1);\n v2 = (__m128d) * (unsigned long long *)&a2;\n v7 = a2 / v9;\n v2.m128d_f64[0] = v7;\n if (fabs(v7) < 4.503599627370496e15) {\n v3.m128d_f64[0] = (double)(int)v7;\n *(uint64_t *)&v7 = COERCE_UNSIGNED_INT64(\n v3.m128d_f64[0] +\n COERCE_DOUBLE(*(long double *)&_mm_cmpgt_sd(v2, v3) &\n 4607182418800017408LL)) |\n *(uint64_t *)&v7 & 9223372036854775808LL;\n }\n v4 = pow(10.0, (double)a1);\n v8 = round(v7 * v9 * v4);\n return v8 / pow(10.0, (double)a1);\n}", + "ida_pseudo_norm": "double func0(int a1, double a2) {\n __m128d v2;\n __m128d v3;\n double v4;\n double v7;\n double v8;\n double v9;\n v9 = pow(10.0, (double)-a1);\n v2 = (__m128d) * (unsigned long long *)&a2;\n v7 = a2 / v9;\n v2.m128d_f64[0] = v7;\n if (fabs(v7) < 4.503599627370496e15) {\n v3.m128d_f64[0] = (double)(int)v7;\n *(uint64_t *)&v7 = COERCE_UNSIGNED_INT64(\n v3.m128d_f64[0] +\n COERCE_DOUBLE(*(long double *)&_mm_cmpgt_sd(v2, v3) &\n 4607182418800017408LL)) |\n *(uint64_t *)&v7 & 9223372036854775808LL;\n }\n v4 = pow(10.0, (double)a1);\n v8 = round(v7 * v9 * v4);\n return v8 / pow(10.0, (double)a1);\n}" + }, + { + "index": 830, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(double a, int digits) {\n double n = pow(10, -digits);\n return round(ceil(a / n) * n * pow(10, digits)) / pow(10, digits);\n}", + "test": "int main() {\n\n assert(func0(123.01247,0) == 124);\n\n assert(func0(123.01247,1) == 123.1);\n\n assert(func0(123.01247,2) == 123.02);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %edi,%eax\npxor %xmm1,%xmm1\nmov %edi,%ebx\nneg %eax\ncvtsi2sd %eax,%xmm1\nsub $0x20,%rsp\nmovsd 0xe21(%rip),%xmm4\nmovsd %xmm0,0x8(%rsp)\nmovapd %xmm4,%xmm0\ncallq 1080 \nmovsd 0x8(%rsp),%xmm2\nmovsd 0xe0c(%rip),%xmm5\nmovapd %xmm0,%xmm3\nmov 0xdf9(%rip),%rax\ndivsd %xmm0,%xmm2\nmovsd 0xe2d(%rip),%xmm0\nmovq %rax,%xmm4\nmovapd %xmm2,%xmm1\nandpd %xmm0,%xmm1\nucomisd %xmm1,%xmm5\njbe 12f9 \ncvttsd2si %xmm2,%rax\npxor %xmm1,%xmm1\nmovapd %xmm2,%xmm5\nmovsd 0xdd5(%rip),%xmm6\nandnpd %xmm2,%xmm0\nmovapd %xmm0,%xmm2\ncvtsi2sd %rax,%xmm1\ncmpnlesd %xmm1,%xmm5\nandpd %xmm6,%xmm5\naddsd %xmm5,%xmm1\norpd %xmm1,%xmm2\npxor %xmm1,%xmm1\nmovapd %xmm4,%xmm0\nmovsd %xmm2,0x18(%rsp)\ncvtsi2sd %ebx,%xmm1\nmovsd %xmm3,0x8(%rsp)\nmovsd %xmm1,0x10(%rsp)\ncallq 1080 \nmovsd 0x8(%rsp),%xmm3\nmovsd 0x18(%rsp),%xmm2\nmulsd %xmm3,%xmm2\nmulsd %xmm2,%xmm0\ncallq 1070 \nmov 0xd64(%rip),%rax\nmovsd 0x10(%rsp),%xmm1\nmovsd %xmm0,0x8(%rsp)\nmovq %rax,%xmm0\ncallq 1080 \nmovsd 0x8(%rsp),%xmm2\nadd $0x20,%rsp\npop %rbx\ndivsd %xmm0,%xmm2\nmovapd %xmm2,%xmm0\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov eax, edi\npxor xmm1, xmm1\nmov ebx, edi\nneg eax\ncvtsi2sd xmm1, eax; y\nsub rsp, 20h\nmovsd [rsp+28h+var_20], xmm0\nmovsd xmm0, cs:x; x\ncall _pow\nmovsd xmm2, [rsp+28h+var_20]\nmovsd xmm1, cs:qword_2098\nmovsd xmm4, cs:qword_2088\nmovapd xmm3, xmm0\ndivsd xmm2, xmm0\nmovapd xmm0, xmm2\nandpd xmm0, xmm1\nucomisd xmm4, xmm0\njbe short loc_12E9\ncvttsd2si rax, xmm2\npxor xmm0, xmm0\nmovapd xmm4, xmm2\nmovsd xmm5, cs:qword_2090\nandnpd xmm1, xmm2\ncvtsi2sd xmm0, rax\ncmpnlesd xmm4, xmm0\nandpd xmm4, xmm5\naddsd xmm0, xmm4\nmovapd xmm2, xmm0\norpd xmm2, xmm1\nloc_12E9:\npxor xmm1, xmm1\nmovsd xmm0, cs:x; x\nmovsd [rsp+28h+var_10], xmm2\ncvtsi2sd xmm1, ebx; y\nmovsd [rsp+28h+var_20], xmm3\nmovsd [rsp+28h+y], xmm1\ncall _pow\nmovsd xmm3, [rsp+28h+var_20]\nmovsd xmm2, [rsp+28h+var_10]\nmulsd xmm2, xmm3\nmulsd xmm0, xmm2; x\ncall _round\nmovsd xmm1, [rsp+28h+y]; y\nmovsd [rsp+28h+var_20], xmm0\nmovsd xmm0, cs:x; x\ncall _pow\nmovsd xmm2, [rsp+28h+var_20]\nadd rsp, 20h\npop rbx\ndivsd xmm2, xmm0\nmovapd xmm0, xmm2\nretn", + "ida_pseudo": "__int128 __usercall func0@(int a1@, double a2@)\n{\n double v2; // xmm3_8\n __m128d v3; // xmm2\n __m128d v4; // xmm0\n double v5; // xmm0_8\n __int128 v6; // xmm2\n double v9; // [rsp+0h] [rbp-20h]\n\n v3 = (__m128d)*(unsigned __int64 *)&a2;\n v2 = pow(10.0, (double)-a1);\n v3.m128d_f64[0] = a2 / v2;\n if ( fabs(a2 / v2) < 4.503599627370496e15 )\n {\n v4.m128d_f64[0] = (double)(int)v3.m128d_f64[0];\n *(_QWORD *)&v3.m128d_f64[0] = COERCE_UNSIGNED_INT64(\n v4.m128d_f64[0]\n + COERCE_DOUBLE(*(_OWORD *)&_mm_cmpgt_sd(v3, v4) & 0x3FF0000000000000LL)) | *(_QWORD *)&v3.m128d_f64[0] & 0x8000000000000000LL;\n }\n v5 = pow(10.0, (double)a1);\n v9 = round(v5 * (v3.m128d_f64[0] * v2));\n v6 = *(unsigned __int64 *)&v9;\n *(double *)&v6 = v9 / pow(10.0, (double)a1);\n return v6;\n}", + "ida_strip_asm": "sub_1260:\nendbr64\npush rbx\nmov eax, edi\npxor xmm1, xmm1\nmov ebx, edi\nneg eax\ncvtsi2sd xmm1, eax; y\nsub rsp, 20h\nmovsd [rsp+28h+var_20], xmm0\nmovsd xmm0, cs:x; x\ncall _pow\nmovsd xmm2, [rsp+28h+var_20]\nmovsd xmm1, cs:qword_2098\nmovsd xmm4, cs:qword_2088\nmovapd xmm3, xmm0\ndivsd xmm2, xmm0\nmovapd xmm0, xmm2\nandpd xmm0, xmm1\nucomisd xmm4, xmm0\njbe short loc_12E9\ncvttsd2si rax, xmm2\npxor xmm0, xmm0\nmovapd xmm4, xmm2\nmovsd xmm5, cs:qword_2090\nandnpd xmm1, xmm2\ncvtsi2sd xmm0, rax\ncmpnlesd xmm4, xmm0\nandpd xmm4, xmm5\naddsd xmm0, xmm4\nmovapd xmm2, xmm0\norpd xmm2, xmm1\nloc_12E9:\npxor xmm1, xmm1\nmovsd xmm0, cs:x; x\nmovsd [rsp+28h+var_10], xmm2\ncvtsi2sd xmm1, ebx; y\nmovsd [rsp+28h+var_20], xmm3\nmovsd [rsp+28h+y], xmm1\ncall _pow\nmovsd xmm3, [rsp+28h+var_20]\nmovsd xmm2, [rsp+28h+var_10]\nmulsd xmm2, xmm3\nmulsd xmm0, xmm2; x\ncall _round\nmovsd xmm1, [rsp+28h+y]; y\nmovsd [rsp+28h+var_20], xmm0\nmovsd xmm0, cs:x; x\ncall _pow\nmovsd xmm2, [rsp+28h+var_20]\nadd rsp, 20h\npop rbx\ndivsd xmm2, xmm0\nmovapd xmm0, xmm2\nretn", + "ida_strip_pseudo": "__int128 __usercall sub_1260@(int a1@, double a2@)\n{\n double v2; // xmm3_8\n __m128d v3; // xmm2\n __m128d v4; // xmm0\n double v5; // xmm0_8\n __int128 v6; // xmm2\n double v9; // [rsp+0h] [rbp-20h]\n\n v3 = (__m128d)*(unsigned __int64 *)&a2;\n v2 = pow(10.0, (double)-a1);\n v3.m128d_f64[0] = a2 / v2;\n if ( fabs(a2 / v2) < 4.503599627370496e15 )\n {\n v4.m128d_f64[0] = (double)(int)v3.m128d_f64[0];\n *(_QWORD *)&v3.m128d_f64[0] = COERCE_UNSIGNED_INT64(\n v4.m128d_f64[0]\n + COERCE_DOUBLE(*(_OWORD *)&_mm_cmpgt_sd(v3, v4) & 0x3FF0000000000000LL)) | *(_QWORD *)&v3.m128d_f64[0] & 0x8000000000000000LL;\n }\n v5 = pow(10.0, (double)a1);\n v9 = round(v5 * (v3.m128d_f64[0] * v2));\n v6 = *(unsigned __int64 *)&v9;\n *(double *)&v6 = v9 / pow(10.0, (double)a1);\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__int128 __usercall sub_1260 @(int a1 @, double a2 @) {\n double v2;\n __m128d v3;\n __m128d v4;\n double v5;\n __int128 v6;\n double v9;\n v3 = (__m128d) * (unsigned long long *)&a2;\n v2 = pow(10.0, (double)-a1);\n v3.m128d_f64[0] = a2 / v2;\n if (fabs(a2 / v2) < 4.503599627370496e15) {\n v4.m128d_f64[0] = (double)(int)v3.m128d_f64[0];\n *(uint64_t *)&v3.m128d_f64[0] =\n COERCE_UNSIGNED_INT64(\n v4.m128d_f64[0] +\n COERCE_DOUBLE(*(long double *)&_mm_cmpgt_sd(v3, v4) &\n 4607182418800017408LL)) |\n *(uint64_t *)&v3.m128d_f64[0] & 9223372036854775808LL;\n }\n v5 = pow(10.0, (double)a1);\n v9 = round(v5 * (v3.m128d_f64[0] * v2));\n v6 = *(unsigned long long *)&v9;\n *(double *)&v6 = v9 / pow(10.0, (double)a1);\n return v6;\n}", + "ida_pseudo_norm": "__int128 __usercall func0 @(int a1 @, double a2 @) {\n double v2;\n __m128d v3;\n __m128d v4;\n double v5;\n __int128 v6;\n double v9;\n v3 = (__m128d) * (unsigned long long *)&a2;\n v2 = pow(10.0, (double)-a1);\n v3.m128d_f64[0] = a2 / v2;\n if (fabs(a2 / v2) < 4.503599627370496e15) {\n v4.m128d_f64[0] = (double)(int)v3.m128d_f64[0];\n *(uint64_t *)&v3.m128d_f64[0] =\n COERCE_UNSIGNED_INT64(\n v4.m128d_f64[0] +\n COERCE_DOUBLE(*(long double *)&_mm_cmpgt_sd(v3, v4) &\n 4607182418800017408LL)) |\n *(uint64_t *)&v3.m128d_f64[0] & 9223372036854775808LL;\n }\n v5 = pow(10.0, (double)a1);\n v9 = round(v5 * (v3.m128d_f64[0] * v2));\n v6 = *(unsigned long long *)&v9;\n *(double *)&v6 = v9 / pow(10.0, (double)a1);\n return v6;\n}" + }, + { + "index": 830, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(double a, int digits) {\n double n = pow(10, -digits);\n return round(ceil(a / n) * n * pow(10, digits)) / pow(10, digits);\n}", + "test": "int main() {\n\n assert(func0(123.01247,0) == 124);\n\n assert(func0(123.01247,1) == 123.1);\n\n assert(func0(123.01247,2) == 123.02);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %edi,%eax\npxor %xmm1,%xmm1\nmov %edi,%ebx\nneg %eax\ncvtsi2sd %eax,%xmm1\nsub $0x20,%rsp\nmovsd 0xe21(%rip),%xmm4\nmovsd %xmm0,0x8(%rsp)\nmovapd %xmm4,%xmm0\ncallq 1080 \nmovsd 0x8(%rsp),%xmm2\nmovsd 0xe0c(%rip),%xmm5\nmovapd %xmm0,%xmm3\nmov 0xdf9(%rip),%rax\ndivsd %xmm0,%xmm2\nmovsd 0xe2d(%rip),%xmm0\nmovq %rax,%xmm4\nmovapd %xmm2,%xmm1\nandpd %xmm0,%xmm1\nucomisd %xmm1,%xmm5\njbe 12f9 \ncvttsd2si %xmm2,%rax\npxor %xmm1,%xmm1\nmovapd %xmm2,%xmm5\nmovsd 0xdd5(%rip),%xmm6\nandnpd %xmm2,%xmm0\nmovapd %xmm0,%xmm2\ncvtsi2sd %rax,%xmm1\ncmpnlesd %xmm1,%xmm5\nandpd %xmm6,%xmm5\naddsd %xmm5,%xmm1\norpd %xmm1,%xmm2\npxor %xmm1,%xmm1\nmovapd %xmm4,%xmm0\nmovsd %xmm2,0x18(%rsp)\ncvtsi2sd %ebx,%xmm1\nmovsd %xmm3,0x8(%rsp)\nmovsd %xmm1,0x10(%rsp)\ncallq 1080 \nmovsd 0x8(%rsp),%xmm3\nmovsd 0x18(%rsp),%xmm2\nmulsd %xmm3,%xmm2\nmulsd %xmm2,%xmm0\ncallq 1070 \nmov 0xd64(%rip),%rax\nmovsd 0x10(%rsp),%xmm1\nmovsd %xmm0,0x8(%rsp)\nmovq %rax,%xmm0\ncallq 1080 \nmovsd 0x8(%rsp),%xmm2\nadd $0x20,%rsp\npop %rbx\ndivsd %xmm0,%xmm2\nmovapd %xmm2,%xmm0\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov eax, edi\npxor xmm1, xmm1\nmov ebx, edi\nneg eax\ncvtsi2sd xmm1, eax; y\nsub rsp, 20h\nmovsd [rsp+28h+var_20], xmm0\nmovsd xmm0, cs:x; x\ncall _pow\nmovsd xmm2, [rsp+28h+var_20]\nmovsd xmm1, cs:qword_2098\nmovsd xmm4, cs:qword_2088\nmovapd xmm3, xmm0\ndivsd xmm2, xmm0\nmovapd xmm0, xmm2\nandpd xmm0, xmm1\nucomisd xmm4, xmm0\njbe short loc_12E9\ncvttsd2si rax, xmm2\npxor xmm0, xmm0\nmovapd xmm4, xmm2\nmovsd xmm5, cs:qword_2090\nandnpd xmm1, xmm2\ncvtsi2sd xmm0, rax\ncmpnlesd xmm4, xmm0\nandpd xmm4, xmm5\naddsd xmm0, xmm4\nmovapd xmm2, xmm0\norpd xmm2, xmm1\nloc_12E9:\npxor xmm1, xmm1\nmovsd xmm0, cs:x; x\nmovsd [rsp+28h+var_10], xmm2\ncvtsi2sd xmm1, ebx; y\nmovsd [rsp+28h+var_20], xmm3\nmovsd [rsp+28h+y], xmm1\ncall _pow\nmovsd xmm3, [rsp+28h+var_20]\nmovsd xmm2, [rsp+28h+var_10]\nmulsd xmm2, xmm3\nmulsd xmm0, xmm2; x\ncall _round\nmovsd xmm1, [rsp+28h+y]; y\nmovsd [rsp+28h+var_20], xmm0\nmovsd xmm0, cs:x; x\ncall _pow\nmovsd xmm2, [rsp+28h+var_20]\nadd rsp, 20h\npop rbx\ndivsd xmm2, xmm0\nmovapd xmm0, xmm2\nretn", + "ida_pseudo": "__int128 __usercall func0@(int a1@, double a2@)\n{\n double v2; // xmm3_8\n __m128d v3; // xmm2\n __m128d v4; // xmm0\n double v5; // xmm0_8\n __int128 v6; // xmm2\n double v9; // [rsp+0h] [rbp-20h]\n\n v3 = (__m128d)*(unsigned __int64 *)&a2;\n v2 = pow(10.0, (double)-a1);\n v3.m128d_f64[0] = a2 / v2;\n if ( fabs(a2 / v2) < 4.503599627370496e15 )\n {\n v4.m128d_f64[0] = (double)(int)v3.m128d_f64[0];\n *(_QWORD *)&v3.m128d_f64[0] = COERCE_UNSIGNED_INT64(\n v4.m128d_f64[0]\n + COERCE_DOUBLE(*(_OWORD *)&_mm_cmpgt_sd(v3, v4) & 0x3FF0000000000000LL)) | *(_QWORD *)&v3.m128d_f64[0] & 0x8000000000000000LL;\n }\n v5 = pow(10.0, (double)a1);\n v9 = round(v5 * (v3.m128d_f64[0] * v2));\n v6 = *(unsigned __int64 *)&v9;\n *(double *)&v6 = v9 / pow(10.0, (double)a1);\n return v6;\n}", + "ida_strip_asm": "sub_1260:\nendbr64\npush rbx\nmov eax, edi\npxor xmm1, xmm1\nmov ebx, edi\nneg eax\ncvtsi2sd xmm1, eax; y\nsub rsp, 20h\nmovsd [rsp+28h+var_20], xmm0\nmovsd xmm0, cs:x; x\ncall _pow\nmovsd xmm2, [rsp+28h+var_20]\nmovsd xmm1, cs:qword_2098\nmovsd xmm4, cs:qword_2088\nmovapd xmm3, xmm0\ndivsd xmm2, xmm0\nmovapd xmm0, xmm2\nandpd xmm0, xmm1\nucomisd xmm4, xmm0\njbe short loc_12E9\ncvttsd2si rax, xmm2\npxor xmm0, xmm0\nmovapd xmm4, xmm2\nmovsd xmm5, cs:qword_2090\nandnpd xmm1, xmm2\ncvtsi2sd xmm0, rax\ncmpnlesd xmm4, xmm0\nandpd xmm4, xmm5\naddsd xmm0, xmm4\nmovapd xmm2, xmm0\norpd xmm2, xmm1\nloc_12E9:\npxor xmm1, xmm1\nmovsd xmm0, cs:x; x\nmovsd [rsp+28h+var_10], xmm2\ncvtsi2sd xmm1, ebx; y\nmovsd [rsp+28h+var_20], xmm3\nmovsd [rsp+28h+y], xmm1\ncall _pow\nmovsd xmm3, [rsp+28h+var_20]\nmovsd xmm2, [rsp+28h+var_10]\nmulsd xmm2, xmm3\nmulsd xmm0, xmm2; x\ncall _round\nmovsd xmm1, [rsp+28h+y]; y\nmovsd [rsp+28h+var_20], xmm0\nmovsd xmm0, cs:x; x\ncall _pow\nmovsd xmm2, [rsp+28h+var_20]\nadd rsp, 20h\npop rbx\ndivsd xmm2, xmm0\nmovapd xmm0, xmm2\nretn", + "ida_strip_pseudo": "__int128 __usercall sub_1260@(int a1@, double a2@)\n{\n double v2; // xmm3_8\n __m128d v3; // xmm2\n __m128d v4; // xmm0\n double v5; // xmm0_8\n __int128 v6; // xmm2\n double v9; // [rsp+0h] [rbp-20h]\n\n v3 = (__m128d)*(unsigned __int64 *)&a2;\n v2 = pow(10.0, (double)-a1);\n v3.m128d_f64[0] = a2 / v2;\n if ( fabs(a2 / v2) < 4.503599627370496e15 )\n {\n v4.m128d_f64[0] = (double)(int)v3.m128d_f64[0];\n *(_QWORD *)&v3.m128d_f64[0] = COERCE_UNSIGNED_INT64(\n v4.m128d_f64[0]\n + COERCE_DOUBLE(*(_OWORD *)&_mm_cmpgt_sd(v3, v4) & 0x3FF0000000000000LL)) | *(_QWORD *)&v3.m128d_f64[0] & 0x8000000000000000LL;\n }\n v5 = pow(10.0, (double)a1);\n v9 = round(v5 * (v3.m128d_f64[0] * v2));\n v6 = *(unsigned __int64 *)&v9;\n *(double *)&v6 = v9 / pow(10.0, (double)a1);\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__int128 __usercall sub_1260 @(int a1 @, double a2 @) {\n double v2;\n __m128d v3;\n __m128d v4;\n double v5;\n __int128 v6;\n double v9;\n v3 = (__m128d) * (unsigned long long *)&a2;\n v2 = pow(10.0, (double)-a1);\n v3.m128d_f64[0] = a2 / v2;\n if (fabs(a2 / v2) < 4.503599627370496e15) {\n v4.m128d_f64[0] = (double)(int)v3.m128d_f64[0];\n *(uint64_t *)&v3.m128d_f64[0] =\n COERCE_UNSIGNED_INT64(\n v4.m128d_f64[0] +\n COERCE_DOUBLE(*(long double *)&_mm_cmpgt_sd(v3, v4) &\n 4607182418800017408LL)) |\n *(uint64_t *)&v3.m128d_f64[0] & 9223372036854775808LL;\n }\n v5 = pow(10.0, (double)a1);\n v9 = round(v5 * (v3.m128d_f64[0] * v2));\n v6 = *(unsigned long long *)&v9;\n *(double *)&v6 = v9 / pow(10.0, (double)a1);\n return v6;\n}", + "ida_pseudo_norm": "__int128 __usercall func0 @(int a1 @, double a2 @) {\n double v2;\n __m128d v3;\n __m128d v4;\n double v5;\n __int128 v6;\n double v9;\n v3 = (__m128d) * (unsigned long long *)&a2;\n v2 = pow(10.0, (double)-a1);\n v3.m128d_f64[0] = a2 / v2;\n if (fabs(a2 / v2) < 4.503599627370496e15) {\n v4.m128d_f64[0] = (double)(int)v3.m128d_f64[0];\n *(uint64_t *)&v3.m128d_f64[0] =\n COERCE_UNSIGNED_INT64(\n v4.m128d_f64[0] +\n COERCE_DOUBLE(*(long double *)&_mm_cmpgt_sd(v3, v4) &\n 4607182418800017408LL)) |\n *(uint64_t *)&v3.m128d_f64[0] & 9223372036854775808LL;\n }\n v5 = pow(10.0, (double)a1);\n v9 = round(v5 * (v3.m128d_f64[0] * v2));\n v6 = *(unsigned long long *)&v9;\n *(double *)&v6 = v9 / pow(10.0, (double)a1);\n return v6;\n}" + }, + { + "index": 831, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int cnt = 0;\n for (int i = 0; i < n; i++) {\n for (int j = i + 1; j < n; j++) {\n if (arr[i] == arr[j]) {\n cnt++;\n }\n }\n }\n return cnt;\n}", + "test": "int main() {\n\n int arr1[] = {1, 1, 1, 1};\n\n int arr2[] = {1, 5, 1};\n\n int arr3[] = {3, 2, 1, 7, 8, 9};\n\n\n\n assert(func0(arr1, 4) == 6);\n\n assert(func0(arr2, 3) == 1);\n\n assert(func0(arr3, 6) == 0);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11d7 \nmov -0x8(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x4(%rbp)\njmp 11cb \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 11c7 \naddl $0x1,-0xc(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1193 \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1188 \nmov -0xc(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_11D7\nloc_1188:\nmov eax, [rbp+var_8]\nadd eax, 1\nmov [rbp+var_4], eax\njmp short loc_11CB\nloc_1193:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11C7\nadd [rbp+var_C], 1\nloc_11C7:\nadd [rbp+var_4], 1\nloc_11CB:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1193\nadd [rbp+var_8], 1\nloc_11D7:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+10h] [rbp-Ch]\n int i; // [rsp+14h] [rbp-8h]\n int j; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4LL * j + a1) )\n ++v3;\n }\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_11D7\nloc_1188:\nmov eax, [rbp+var_8]\nadd eax, 1\nmov [rbp+var_4], eax\njmp short loc_11CB\nloc_1193:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11C7\nadd [rbp+var_C], 1\nloc_11C7:\nadd [rbp+var_4], 1\nloc_11CB:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1193\nadd [rbp+var_8], 1\nloc_11D7:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+10h] [rbp-Ch]\n int i; // [rsp+14h] [rbp-8h]\n int j; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4LL * j + a1) )\n ++v3;\n }\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n unsigned int v3;\n int i;\n int j;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if (*(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4LL * j + a1)) ++v3;\n }\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n int j;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if (*(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4LL * j + a1)) ++v3;\n }\n }\n return v3;\n}" + }, + { + "index": 831, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int cnt = 0;\n for (int i = 0; i < n; i++) {\n for (int j = i + 1; j < n; j++) {\n if (arr[i] == arr[j]) {\n cnt++;\n }\n }\n }\n return cnt;\n}", + "test": "int main() {\n\n int arr1[] = {1, 1, 1, 1};\n\n int arr2[] = {1, 5, 1};\n\n int arr3[] = {3, 2, 1, 7, 8, 9};\n\n\n\n assert(func0(arr1, 4) == 6);\n\n assert(func0(arr2, 3) == 1);\n\n assert(func0(arr3, 6) == 0);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11ab \nlea -0x1(%rsi),%r9d\nadd $0x1,%r9\nmov $0x1,%r8d\nmov $0x0,%ecx\njmp 119c \nadd $0x1,%rax\ncmp %eax,%esi\njle 1198 \ncmp (%rdi,%rax,4),%edx\njne 1186 \nadd $0x1,%ecx\njmp 1186 \nadd $0x1,%r8\ncmp %r9,%r8\nje 11b0 \nmov -0x4(%rdi,%r8,4),%edx\nmov %r8,%rax\njmp 118e \nmov $0x0,%ecx\nmov %ecx,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11B1\nmov r9d, esi\nmovsxd r10, esi\nmov r8d, 1\nmov ecx, 0\njmp short loc_11A2\nloc_1184:\nadd rax, 1\ncmp esi, eax\njle short loc_1196\nloc_118C:\ncmp edx, [rdi+rax*4]\njnz short loc_1184\nadd ecx, 1\njmp short loc_1184\nloc_1196:\nlea rax, [r8+1]\ncmp r8, r10\njz short loc_11B6\nmov r8, rax\nloc_11A2:\ncmp r8, r9\njz short loc_11B6\nmov edx, [rdi+r8*4-4]\nmov rax, r8\njmp short loc_118C\nloc_11B1:\nmov ecx, 0\nloc_11B6:\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // r8\n unsigned int v3; // ecx\n __int64 v4; // rax\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = 1LL;\n v3 = 0;\n while ( v2 != a2 )\n {\n v4 = v2;\n do\n {\n if ( *(_DWORD *)(a1 + 4 * v2 - 4) == *(_DWORD *)(a1 + 4 * v4) )\n ++v3;\n ++v4;\n }\n while ( a2 > (int)v4 );\n if ( v2 == a2 )\n break;\n ++v2;\n }\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11B1\nmov r9d, esi\nmovsxd r10, esi\nmov r8d, 1\nmov ecx, 0\njmp short loc_11A2\nloc_1184:\nadd rax, 1\ncmp esi, eax\njle short loc_1196\nloc_118C:\ncmp edx, [rdi+rax*4]\njnz short loc_1184\nadd ecx, 1\njmp short loc_1184\nloc_1196:\nlea rax, [r8+1]\ncmp r8, r10\njz short loc_11B6\nmov r8, rax\nloc_11A2:\ncmp r8, r9\njz short loc_11B6\nmov edx, [rdi+r8*4-4]\nmov rax, r8\njmp short loc_118C\nloc_11B1:\nmov ecx, 0\nloc_11B6:\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n __int64 v2; // r8\n unsigned int v3; // ecx\n __int64 v4; // rax\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = 1LL;\n v3 = 0;\n while ( v2 != a2 )\n {\n v4 = v2;\n do\n {\n if ( *(_DWORD *)(a1 + 4 * v2 - 4) == *(_DWORD *)(a1 + 4 * v4) )\n ++v3;\n ++v4;\n }\n while ( a2 > (int)v4 );\n if ( v2 == a2 )\n break;\n ++v2;\n }\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n long long v4;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = 1LL;\n v3 = 0;\n while (v2 != a2) {\n v4 = v2;\n do {\n if (*(uint32_t *)(a1 + 4 * v2 - 4) == *(uint32_t *)(a1 + 4 * v4)) ++v3;\n ++v4;\n } while (a2 > (int)v4);\n if (v2 == a2) break;\n ++v2;\n }\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n long long v4;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = 1LL;\n v3 = 0;\n while (v2 != a2) {\n v4 = v2;\n do {\n if (*(uint32_t *)(a1 + 4 * v2 - 4) == *(uint32_t *)(a1 + 4 * v4)) ++v3;\n ++v4;\n } while (a2 > (int)v4);\n if (v2 == a2) break;\n ++v2;\n }\n }\n return v3;\n}" + }, + { + "index": 831, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int cnt = 0;\n for (int i = 0; i < n; i++) {\n for (int j = i + 1; j < n; j++) {\n if (arr[i] == arr[j]) {\n cnt++;\n }\n }\n }\n return cnt;\n}", + "test": "int main() {\n\n int arr1[] = {1, 1, 1, 1};\n\n int arr2[] = {1, 5, 1};\n\n int arr3[] = {3, 2, 1, 7, 8, 9};\n\n\n\n assert(func0(arr1, 4) == 6);\n\n assert(func0(arr2, 3) == 1);\n\n assert(func0(arr3, 6) == 0);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 137e \nlea -0x1(%rsi),%r9d\nmov $0x1,%ecx\nxor %r8d,%r8d\nadd $0x1,%r9\ncmp %r9,%rcx\nje 137a \nnopl (%rax)\nmov -0x4(%rdi,%rcx,4),%edx\nmov %rcx,%rax\nnopw 0x0(%rax,%rax,1)\ncmp (%rdi,%rax,4),%edx\njne 1369 \nadd $0x1,%r8d\nadd $0x1,%rax\ncmp %eax,%esi\njg 1360 \nadd $0x1,%rcx\ncmp %r9,%rcx\njne 1350 \nmov %r8d,%eax\nretq\nxor %r8d,%r8d\nmov %r8d,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_12CC\nmov r9d, esi\nmov r8d, 1\nxor ecx, ecx\ncmp esi, 1\njz short loc_12C9\nnop dword ptr [rax+rax+00000000h]\nloc_12A0:\nmov edx, [rdi+r8*4-4]\nmov rax, r8\nnop dword ptr [rax+rax+00000000h]\nloc_12B0:\ncmp edx, [rdi+rax*4]\njnz short loc_12B8\nadd ecx, 1\nloc_12B8:\nadd rax, 1\ncmp esi, eax\njg short loc_12B0\nadd r8, 1\ncmp r8, r9\njnz short loc_12A0\nloc_12C9:\nmov eax, ecx\nretn\nloc_12CC:\nxor ecx, ecx\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // r8\n unsigned int v3; // ecx\n __int64 v4; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 1LL;\n v3 = 0;\n if ( a2 != 1 )\n {\n do\n {\n v4 = v2;\n do\n {\n if ( *(_DWORD *)(a1 + 4 * v2 - 4) == *(_DWORD *)(a1 + 4 * v4) )\n ++v3;\n ++v4;\n }\n while ( a2 > (int)v4 );\n ++v2;\n }\n while ( v2 != a2 );\n }\n return v3;\n}", + "ida_strip_asm": "sub_1280:\nendbr64\ntest esi, esi\njle short loc_12CC\nmov r9d, esi\nmov r8d, 1\nxor ecx, ecx\ncmp esi, 1\njz short loc_12C9\nnop dword ptr [rax+rax+00000000h]\nloc_12A0:\nmov edx, [rdi+r8*4-4]\nmov rax, r8\nnop dword ptr [rax+rax+00000000h]\nloc_12B0:\ncmp edx, [rdi+rax*4]\njnz short loc_12B8\nadd ecx, 1\nloc_12B8:\nadd rax, 1\ncmp esi, eax\njg short loc_12B0\nadd r8, 1\ncmp r8, r9\njnz short loc_12A0\nloc_12C9:\nmov eax, ecx\nretn\nloc_12CC:\nxor ecx, ecx\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1280(__int64 a1, int a2)\n{\n __int64 v2; // r8\n unsigned int v3; // ecx\n __int64 v4; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 1LL;\n v3 = 0;\n if ( a2 != 1 )\n {\n do\n {\n v4 = v2;\n do\n {\n if ( *(_DWORD *)(a1 + 4 * v2 - 4) == *(_DWORD *)(a1 + 4 * v4) )\n ++v3;\n ++v4;\n }\n while ( a2 > (int)v4 );\n ++v2;\n }\n while ( v2 != a2 );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1280(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n long long v4;\n if (a2 <= 0) return 0LL;\n v2 = 1LL;\n v3 = 0;\n if (a2 != 1) {\n do {\n v4 = v2;\n do {\n if (*(uint32_t *)(a1 + 4 * v2 - 4) == *(uint32_t *)(a1 + 4 * v4)) ++v3;\n ++v4;\n } while (a2 > (int)v4);\n ++v2;\n } while (v2 != a2);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n long long v4;\n if (a2 <= 0) return 0LL;\n v2 = 1LL;\n v3 = 0;\n if (a2 != 1) {\n do {\n v4 = v2;\n do {\n if (*(uint32_t *)(a1 + 4 * v2 - 4) == *(uint32_t *)(a1 + 4 * v4)) ++v3;\n ++v4;\n } while (a2 > (int)v4);\n ++v2;\n } while (v2 != a2);\n }\n return v3;\n}" + }, + { + "index": 832, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *input) {\n int max = 0;\n char temp[256];\n int index = 0;\n for (int i = 0; input[i] != '\\0'; i++) {\n if (input[i] >= '0' && input[i] <= '9') {\n temp[index++] = input[i];\n } else {\n if (index != 0) {\n temp[index] = '\\0';\n int number = atoi(temp);\n if (number > max) max = number;\n index = 0;\n }\n }\n }\n if (index != 0) {\n temp[index] = '\\0';\n int number = atoi(temp);\n if (number > max) max = number;\n }\n return max;\n}", + "test": "int main() {\n\n assert(func0(\"100klh564abc365bg\") == 564);\n\n assert(func0(\"hello300how546mer231\") == 546);\n\n assert(func0(\"its233beenalong343journey234\") == 343);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x140,%rsp\nmov %rdi,-0x138(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovl $0x0,-0x124(%rbp)\nmovl $0x0,-0x120(%rbp)\nmovl $0x0,-0x11c(%rbp)\njmpq 128f \nmov -0x11c(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x138(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x2f,%al\njle 1236 \nmov -0x11c(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x138(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x39,%al\njg 1236 \nmov -0x11c(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x138(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x120(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x120(%rbp)\nmovzbl (%rcx),%edx\ncltq\nmov %dl,-0x110(%rbp,%rax,1)\njmp 1288 \ncmpl $0x0,-0x120(%rbp)\nje 1288 \nmov -0x120(%rbp),%eax\ncltq\nmovb $0x0,-0x110(%rbp,%rax,1)\nlea -0x110(%rbp),%rax\nmov %rax,%rdi\ncallq 1090 \nmov %eax,-0x114(%rbp)\nmov -0x114(%rbp),%eax\ncmp -0x124(%rbp),%eax\njle 127e \nmov -0x114(%rbp),%eax\nmov %eax,-0x124(%rbp)\nmovl $0x0,-0x120(%rbp)\naddl $0x1,-0x11c(%rbp)\nmov -0x11c(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x138(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 11d1 \ncmpl $0x0,-0x120(%rbp)\nje 12f5 \nmov -0x120(%rbp),%eax\ncltq\nmovb $0x0,-0x110(%rbp,%rax,1)\nlea -0x110(%rbp),%rax\nmov %rax,%rdi\ncallq 1090 \nmov %eax,-0x118(%rbp)\nmov -0x118(%rbp),%eax\ncmp -0x124(%rbp),%eax\njle 12f5 \nmov -0x118(%rbp),%eax\nmov %eax,-0x124(%rbp)\nmov -0x124(%rbp),%eax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 130f \ncallq 1070 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 140h\nmov [rbp+var_138], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_124], 0\nmov [rbp+var_120], 0\nmov [rbp+var_11C], 0\njmp loc_128F\nloc_11D1:\nmov eax, [rbp+var_11C]\nmovsxd rdx, eax\nmov rax, [rbp+var_138]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 2Fh ; '/'\njle short loc_1236\nmov eax, [rbp+var_11C]\nmovsxd rdx, eax\nmov rax, [rbp+var_138]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 39h ; '9'\njg short loc_1236\nmov eax, [rbp+var_11C]\nmovsxd rdx, eax\nmov rax, [rbp+var_138]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_120]\nlea edx, [rax+1]\nmov [rbp+var_120], edx\nmovzx edx, byte ptr [rcx]\ncdqe\nmov [rbp+rax+nptr], dl\njmp short loc_1288\nloc_1236:\ncmp [rbp+var_120], 0\njz short loc_1288\nmov eax, [rbp+var_120]\ncdqe\nmov [rbp+rax+nptr], 0\nlea rax, [rbp+nptr]\nmov rdi, rax; nptr\ncall _atoi\nmov [rbp+var_114], eax\nmov eax, [rbp+var_114]\ncmp eax, [rbp+var_124]\njle short loc_127E\nmov eax, [rbp+var_114]\nmov [rbp+var_124], eax\nloc_127E:\nmov [rbp+var_120], 0\nloc_1288:\nadd [rbp+var_11C], 1\nloc_128F:\nmov eax, [rbp+var_11C]\nmovsxd rdx, eax\nmov rax, [rbp+var_138]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_11D1\ncmp [rbp+var_120], 0\njz short loc_12F5\nmov eax, [rbp+var_120]\ncdqe\nmov [rbp+rax+nptr], 0\nlea rax, [rbp+nptr]\nmov rdi, rax; nptr\ncall _atoi\nmov [rbp+var_118], eax\nmov eax, [rbp+var_118]\ncmp eax, [rbp+var_124]\njle short loc_12F5\nmov eax, [rbp+var_118]\nmov [rbp+var_124], eax\nloc_12F5:\nmov eax, [rbp+var_124]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_130F\ncall ___stack_chk_fail\nlocret_130F:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1)\n{\n int v1; // eax\n int v3; // [rsp+1Ch] [rbp-124h]\n int v4; // [rsp+20h] [rbp-120h]\n int i; // [rsp+24h] [rbp-11Ch]\n int v6; // [rsp+28h] [rbp-118h]\n int v7; // [rsp+2Ch] [rbp-114h]\n char nptr[264]; // [rsp+30h] [rbp-110h] BYREF\n unsigned __int64 v9; // [rsp+138h] [rbp-8h]\n\n v9 = __readfsqword(0x28u);\n v3 = 0;\n v4 = 0;\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n {\n if ( *(char *)(i + a1) <= 47 || *(char *)(i + a1) > 57 )\n {\n if ( v4 )\n {\n nptr[v4] = 0;\n v7 = atoi(nptr);\n if ( v7 > v3 )\n v3 = v7;\n v4 = 0;\n }\n }\n else\n {\n v1 = v4++;\n nptr[v1] = *(_BYTE *)(i + a1);\n }\n }\n if ( v4 )\n {\n nptr[v4] = 0;\n v6 = atoi(nptr);\n if ( v6 > v3 )\n return (unsigned int)v6;\n }\n return (unsigned int)v3;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 140h\nmov [rbp+var_138], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_124], 0\nmov [rbp+var_120], 0\nmov [rbp+var_11C], 0\njmp loc_128F\nloc_11D1:\nmov eax, [rbp+var_11C]\nmovsxd rdx, eax\nmov rax, [rbp+var_138]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 2Fh ; '/'\njle short loc_1236\nmov eax, [rbp+var_11C]\nmovsxd rdx, eax\nmov rax, [rbp+var_138]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 39h ; '9'\njg short loc_1236\nmov eax, [rbp+var_11C]\nmovsxd rdx, eax\nmov rax, [rbp+var_138]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_120]\nlea edx, [rax+1]\nmov [rbp+var_120], edx\nmovzx edx, byte ptr [rcx]\ncdqe\nmov [rbp+rax+nptr], dl\njmp short loc_1288\nloc_1236:\ncmp [rbp+var_120], 0\njz short loc_1288\nmov eax, [rbp+var_120]\ncdqe\nmov [rbp+rax+nptr], 0\nlea rax, [rbp+nptr]\nmov rdi, rax; nptr\ncall _atoi\nmov [rbp+var_114], eax\nmov eax, [rbp+var_114]\ncmp eax, [rbp+var_124]\njle short loc_127E\nmov eax, [rbp+var_114]\nmov [rbp+var_124], eax\nloc_127E:\nmov [rbp+var_120], 0\nloc_1288:\nadd [rbp+var_11C], 1\nloc_128F:\nmov eax, [rbp+var_11C]\nmovsxd rdx, eax\nmov rax, [rbp+var_138]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_11D1\ncmp [rbp+var_120], 0\njz short loc_12F5\nmov eax, [rbp+var_120]\ncdqe\nmov [rbp+rax+nptr], 0\nlea rax, [rbp+nptr]\nmov rdi, rax; nptr\ncall _atoi\nmov [rbp+var_118], eax\nmov eax, [rbp+var_118]\ncmp eax, [rbp+var_124]\njle short loc_12F5\nmov eax, [rbp+var_118]\nmov [rbp+var_124], eax\nloc_12F5:\nmov eax, [rbp+var_124]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_130F\ncall ___stack_chk_fail\nlocret_130F:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1)\n{\n int v1; // eax\n int v3; // [rsp+1Ch] [rbp-124h]\n int v4; // [rsp+20h] [rbp-120h]\n int i; // [rsp+24h] [rbp-11Ch]\n int v6; // [rsp+28h] [rbp-118h]\n int v7; // [rsp+2Ch] [rbp-114h]\n char nptr[264]; // [rsp+30h] [rbp-110h] BYREF\n unsigned __int64 v9; // [rsp+138h] [rbp-8h]\n\n v9 = __readfsqword(0x28u);\n v3 = 0;\n v4 = 0;\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n {\n if ( *(char *)(i + a1) <= 47 || *(char *)(i + a1) > 57 )\n {\n if ( v4 )\n {\n nptr[v4] = 0;\n v7 = atoi(nptr);\n if ( v7 > v3 )\n v3 = v7;\n v4 = 0;\n }\n }\n else\n {\n v1 = v4++;\n nptr[v1] = *(_BYTE *)(i + a1);\n }\n }\n if ( v4 )\n {\n nptr[v4] = 0;\n v6 = atoi(nptr);\n if ( v6 > v3 )\n return (unsigned int)v6;\n }\n return (unsigned int)v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1) {\n int v1;\n int v3;\n int v4;\n int i;\n int v6;\n int v7;\n char nptr[264];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n v3 = 0;\n v4 = 0;\n for (i = 0; *(uint8_t *)(i + a1); ++i) {\n if (*(char *)(i + a1) <= 47 || *(char *)(i + a1) > 57) {\n if (v4) {\n nptr[v4] = 0;\n v7 = atoi(nptr);\n if (v7 > v3) v3 = v7;\n v4 = 0;\n }\n } else {\n v1 = v4++;\n nptr[v1] = *(uint8_t *)(i + a1);\n }\n }\n if (v4) {\n nptr[v4] = 0;\n v6 = atoi(nptr);\n if (v6 > v3) return (unsigned int)v6;\n }\n return (unsigned int)v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1) {\n int v1;\n int v3;\n int v4;\n int i;\n int v6;\n int v7;\n char nptr[264];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n v3 = 0;\n v4 = 0;\n for (i = 0; *(uint8_t *)(i + a1); ++i) {\n if (*(char *)(i + a1) <= 47 || *(char *)(i + a1) > 57) {\n if (v4) {\n nptr[v4] = 0;\n v7 = atoi(nptr);\n if (v7 > v3) v3 = v7;\n v4 = 0;\n }\n } else {\n v1 = v4++;\n nptr[v1] = *(uint8_t *)(i + a1);\n }\n }\n if (v4) {\n nptr[v4] = 0;\n v6 = atoi(nptr);\n if (v6 > v3) return (unsigned int)v6;\n }\n return (unsigned int)v3;\n}" + }, + { + "index": 832, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *input) {\n int max = 0;\n char temp[256];\n int index = 0;\n for (int i = 0; input[i] != '\\0'; i++) {\n if (input[i] >= '0' && input[i] <= '9') {\n temp[index++] = input[i];\n } else {\n if (index != 0) {\n temp[index] = '\\0';\n int number = atoi(temp);\n if (number > max) max = number;\n index = 0;\n }\n }\n }\n if (index != 0) {\n temp[index] = '\\0';\n int number = atoi(temp);\n if (number > max) max = number;\n }\n return max;\n}", + "test": "int main() {\n\n assert(func0(\"100klh564abc365bg\") == 564);\n\n assert(func0(\"hello300how546mer231\") == 546);\n\n assert(func0(\"its233beenalong343journey234\") == 343);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nsub $0x110,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x108(%rsp)\nxor %eax,%eax\nmovzbl (%rdi),%eax\ntest %al,%al\nje 1256 \nlea 0x1(%rdi),%rbx\nmov $0x0,%edx\nmov $0x0,%ebp\nmov %rsp,%r12\njmp 11d9 \ntest %edx,%edx\njne 11ec \nadd $0x1,%rbx\nmovzbl -0x1(%rbx),%eax\ntest %al,%al\nje 1211 \nlea -0x30(%rax),%ecx\ncmp $0x9,%cl\nja 11c9 \nmovslq %edx,%rcx\nmov %al,(%rsp,%rcx,1)\nlea 0x1(%rdx),%edx\njmp 11cd \nmovslq %edx,%rdx\nmovb $0x0,(%rsp,%rdx,1)\nmov $0xa,%edx\nmov $0x0,%esi\nmov %r12,%rdi\ncallq 1090 \ncmp %eax,%ebp\ncmovl %eax,%ebp\nmov $0x0,%edx\njmp 11cd \ntest %edx,%edx\njne 1236 \nmov 0x108(%rsp),%rax\nxor %fs:0x28,%rax\njne 125d \nmov %ebp,%eax\nadd $0x110,%rsp\npop %rbx\npop %rbp\npop %r12\nretq\nmovslq %edx,%rdx\nmovb $0x0,(%rsp,%rdx,1)\nmov %rsp,%rdi\nmov $0xa,%edx\nmov $0x0,%esi\ncallq 1090 \ncmp %eax,%ebp\ncmovl %eax,%ebp\njmp 1215 \nmov $0x0,%ebp\njmp 1215 \ncallq 1070 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 110h\nmov rax, fs:28h\nmov [rsp+128h+var_20], rax\nxor eax, eax\nmovzx eax, byte ptr [rdi]\ntest al, al\njz loc_1256\nlea rbx, [rdi+1]\nmov edx, 0\nmov ebp, 0\nmov r12, rsp\njmp short loc_11D9\nloc_11C9:\ntest edx, edx\njnz short loc_11EC\nloc_11CD:\nadd rbx, 1\nmovzx eax, byte ptr [rbx-1]\ntest al, al\njz short loc_1211\nloc_11D9:\nlea ecx, [rax-30h]\ncmp cl, 9\nja short loc_11C9\nmovsxd rcx, edx\nmov [rsp+rcx+128h+var_128], al\nlea edx, [rdx+1]\njmp short loc_11CD\nloc_11EC:\nmovsxd rdx, edx\nmov [rsp+rdx+128h+var_128], 0\nmov edx, 0Ah; base\nmov esi, 0; endptr\nmov rdi, r12; nptr\ncall _strtol\ncmp ebp, eax\ncmovl ebp, eax\nmov edx, 0\njmp short loc_11CD\nloc_1211:\ntest edx, edx\njnz short loc_1236\nloc_1215:\nmov rax, [rsp+128h+var_20]\nsub rax, fs:28h\njnz short loc_125D\nmov eax, ebp\nadd rsp, 110h\npop rbx\npop rbp\npop r12\nretn\nloc_1236:\nmovsxd rdx, edx\nmov [rsp+rdx+128h+var_128], 0\nmov rdi, rsp; nptr\nmov edx, 0Ah; base\nmov esi, 0; endptr\ncall _strtol\ncmp ebp, eax\ncmovl ebp, eax\njmp short loc_1215\nloc_1256:\nmov ebp, 0\njmp short loc_1215\nloc_125D:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(char *a1)\n{\n char v1; // al\n char *v2; // rbx\n int v3; // edx\n signed int v4; // ebp\n int v5; // eax\n unsigned int v7; // eax\n char v8[264]; // [rsp+0h] [rbp-128h] BYREF\n unsigned __int64 v9; // [rsp+108h] [rbp-20h]\n\n v9 = __readfsqword(0x28u);\n v1 = *a1;\n if ( *a1 )\n {\n v2 = a1 + 1;\n v3 = 0;\n v4 = 0;\n do\n {\n if ( (unsigned __int8)(v1 - 48) > 9u )\n {\n if ( v3 )\n {\n v8[v3] = 0;\n v5 = strtol(v8, 0LL, 10);\n if ( v4 < v5 )\n v4 = v5;\n v3 = 0;\n }\n }\n else\n {\n v8[v3++] = v1;\n }\n v1 = *v2++;\n }\n while ( v1 );\n if ( v3 )\n {\n v8[v3] = 0;\n v7 = strtol(v8, 0LL, 10);\n if ( v4 < (int)v7 )\n return v7;\n }\n }\n else\n {\n return 0;\n }\n return (unsigned int)v4;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 110h\nmov rax, fs:28h\nmov [rsp+128h+var_20], rax\nxor eax, eax\nmovzx eax, byte ptr [rdi]\ntest al, al\njz loc_1256\nlea rbx, [rdi+1]\nmov edx, 0\nmov ebp, 0\nmov r12, rsp\njmp short loc_11D9\nloc_11C9:\ntest edx, edx\njnz short loc_11EC\nloc_11CD:\nadd rbx, 1\nmovzx eax, byte ptr [rbx-1]\ntest al, al\njz short loc_1211\nloc_11D9:\nlea ecx, [rax-30h]\ncmp cl, 9\nja short loc_11C9\nmovsxd rcx, edx\nmov [rsp+rcx+128h+var_128], al\nlea edx, [rdx+1]\njmp short loc_11CD\nloc_11EC:\nmovsxd rdx, edx\nmov [rsp+rdx+128h+var_128], 0\nmov edx, 0Ah; base\nmov esi, 0; endptr\nmov rdi, r12; nptr\ncall _strtol\ncmp ebp, eax\ncmovl ebp, eax\nmov edx, 0\njmp short loc_11CD\nloc_1211:\ntest edx, edx\njnz short loc_1236\nloc_1215:\nmov rax, [rsp+128h+var_20]\nsub rax, fs:28h\njnz short loc_125D\nmov eax, ebp\nadd rsp, 110h\npop rbx\npop rbp\npop r12\nretn\nloc_1236:\nmovsxd rdx, edx\nmov [rsp+rdx+128h+var_128], 0\nmov rdi, rsp; nptr\nmov edx, 0Ah; base\nmov esi, 0; endptr\ncall _strtol\ncmp ebp, eax\ncmovl ebp, eax\njmp short loc_1215\nloc_1256:\nmov ebp, 0\njmp short loc_1215\nloc_125D:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(char *a1)\n{\n char v1; // al\n char *v2; // rbx\n int v3; // edx\n signed int v4; // ebp\n int v5; // eax\n unsigned int v7; // eax\n char v8[264]; // [rsp+0h] [rbp-128h] BYREF\n unsigned __int64 v9; // [rsp+108h] [rbp-20h]\n\n v9 = __readfsqword(0x28u);\n v1 = *a1;\n if ( *a1 )\n {\n v2 = a1 + 1;\n v3 = 0;\n v4 = 0;\n do\n {\n if ( (unsigned __int8)(v1 - 48) > 9u )\n {\n if ( v3 )\n {\n v8[v3] = 0;\n v5 = strtol(v8, 0LL, 10);\n if ( v4 < v5 )\n v4 = v5;\n v3 = 0;\n }\n }\n else\n {\n v8[v3++] = v1;\n }\n v1 = *v2++;\n }\n while ( v1 );\n if ( v3 )\n {\n v8[v3] = 0;\n v7 = strtol(v8, 0LL, 10);\n if ( v4 < (int)v7 )\n return v7;\n }\n }\n else\n {\n return 0;\n }\n return (unsigned int)v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(char *a1) {\n char v1;\n char *v2;\n int v3;\n signed int v4;\n int v5;\n unsigned int v7;\n char v8[264];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n v1 = *a1;\n if (*a1) {\n v2 = a1 + 1;\n v3 = 0;\n v4 = 0;\n do {\n if ((unsigned char)(v1 - 48) > 9u) {\n if (v3) {\n v8[v3] = 0;\n v5 = strtol(v8, 0LL, 10);\n if (v4 < v5) v4 = v5;\n v3 = 0;\n }\n } else {\n v8[v3++] = v1;\n }\n v1 = *v2++;\n } while (v1);\n if (v3) {\n v8[v3] = 0;\n v7 = strtol(v8, 0LL, 10);\n if (v4 < (int)v7) return v7;\n }\n } else {\n return 0;\n }\n return (unsigned int)v4;\n}", + "ida_pseudo_norm": "long long func0(char *a1) {\n char v1;\n char *v2;\n int v3;\n signed int v4;\n int v5;\n unsigned int v7;\n char v8[264];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n v1 = *a1;\n if (*a1) {\n v2 = a1 + 1;\n v3 = 0;\n v4 = 0;\n do {\n if ((unsigned char)(v1 - 48) > 9u) {\n if (v3) {\n v8[v3] = 0;\n v5 = strtol(v8, 0LL, 10);\n if (v4 < v5) v4 = v5;\n v3 = 0;\n }\n } else {\n v8[v3++] = v1;\n }\n v1 = *v2++;\n } while (v1);\n if (v3) {\n v8[v3] = 0;\n v7 = strtol(v8, 0LL, 10);\n if (v4 < (int)v7) return v7;\n }\n } else {\n return 0;\n }\n return (unsigned int)v4;\n}" + }, + { + "index": 832, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *input) {\n int max = 0;\n char temp[256];\n int index = 0;\n for (int i = 0; input[i] != '\\0'; i++) {\n if (input[i] >= '0' && input[i] <= '9') {\n temp[index++] = input[i];\n } else {\n if (index != 0) {\n temp[index] = '\\0';\n int number = atoi(temp);\n if (number > max) max = number;\n index = 0;\n }\n }\n }\n if (index != 0) {\n temp[index] = '\\0';\n int number = atoi(temp);\n if (number > max) max = number;\n }\n return max;\n}", + "test": "int main() {\n\n assert(func0(\"100klh564abc365bg\") == 564);\n\n assert(func0(\"hello300how546mer231\") == 546);\n\n assert(func0(\"its233beenalong343journey234\") == 343);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nsub $0x110,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x108(%rsp)\nxor %eax,%eax\nmovzbl (%rdi),%eax\ntest %al,%al\nje 1318 \nlea 0x1(%rdi),%rbx\nxor %edx,%edx\nxor %r12d,%r12d\nmov %rsp,%rbp\njmp 1294 \nnopl 0x0(%rax,%rax,1)\nmovslq %edx,%rcx\nadd $0x1,%edx\nmov %al,(%rsp,%rcx,1)\nmovzbl (%rbx),%eax\nadd $0x1,%rbx\ntest %al,%al\nje 12d0 \nlea -0x30(%rax),%ecx\ncmp $0x9,%cl\njbe 1280 \ntest %edx,%edx\nje 1289 \nmovslq %edx,%rdx\nxor %esi,%esi\nmov %rbp,%rdi\nmovb $0x0,(%rsp,%rdx,1)\nmov $0xa,%edx\ncallq 1090 \ncmp %eax,%r12d\ncmovl %eax,%r12d\nmovzbl (%rbx),%eax\nadd $0x1,%rbx\nxor %edx,%edx\ntest %al,%al\njne 1294 \nnopw 0x0(%rax,%rax,1)\ntest %edx,%edx\nje 12f1 \nmovslq %edx,%rdx\nxor %esi,%esi\nmov %rsp,%rdi\nmovb $0x0,(%rsp,%rdx,1)\nmov $0xa,%edx\ncallq 1090 \ncmp %eax,%r12d\ncmovl %eax,%r12d\nmov 0x108(%rsp),%rax\nxor %fs:0x28,%rax\njne 131d \nadd $0x110,%rsp\nmov %r12d,%eax\npop %rbx\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax,%rax,1)\nxor %r12d,%r12d\njmp 12f1 \ncallq 1070 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 110h\nmov rax, fs:28h\nmov [rsp+128h+var_20], rax\nxor eax, eax\nmovzx eax, byte ptr [rdi]\ntest al, al\njz loc_1318\nlea rbx, [rdi+1]\nxor edx, edx\nxor r12d, r12d\nmov rbp, rsp\njmp short loc_1294\nloc_1280:\nmovsxd rcx, edx\nadd edx, 1\nmov [rsp+rcx+128h+var_128], al\nloc_1289:\nmovzx eax, byte ptr [rbx]\nadd rbx, 1\ntest al, al\njz short loc_12D0\nloc_1294:\nlea ecx, [rax-30h]\ncmp cl, 9\njbe short loc_1280\ntest edx, edx\njz short loc_1289\nmovsxd rdx, edx\nxor esi, esi; endptr\nmov rdi, rbp; nptr\nmov [rsp+rdx+128h+var_128], 0\nmov edx, 0Ah; base\ncall _strtol\ncmp r12d, eax\ncmovl r12d, eax\nmovzx eax, byte ptr [rbx]\nadd rbx, 1\nxor edx, edx\ntest al, al\njnz short loc_1294\nnop word ptr [rax+rax+00h]\nloc_12D0:\ntest edx, edx\njz short loc_12F1\nmovsxd rdx, edx\nxor esi, esi; endptr\nmov rdi, rsp; nptr\nmov [rsp+rdx+128h+var_128], 0\nmov edx, 0Ah; base\ncall _strtol\ncmp r12d, eax\ncmovl r12d, eax\nloc_12F1:\nmov rax, [rsp+128h+var_20]\nsub rax, fs:28h\njnz short loc_131D\nadd rsp, 110h\nmov eax, r12d\npop rbx\npop rbp\npop r12\nretn\nloc_1318:\nxor r12d, r12d\njmp short loc_12F1\nloc_131D:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(char *a1)\n{\n char v1; // al\n char *v2; // rbx\n int v3; // edx\n signed int v4; // r12d\n __int64 v5; // rcx\n int v6; // eax\n unsigned int v7; // eax\n char v9[264]; // [rsp+0h] [rbp-128h] BYREF\n unsigned __int64 v10; // [rsp+108h] [rbp-20h]\n\n v10 = __readfsqword(0x28u);\n v1 = *a1;\n if ( !*a1 )\n return 0;\n v2 = a1 + 1;\n v3 = 0;\n v4 = 0;\n do\n {\n while ( (unsigned __int8)(v1 - 48) <= 9u )\n {\n v5 = v3++;\n v9[v5] = v1;\nLABEL_4:\n v1 = *v2++;\n if ( !v1 )\n goto LABEL_10;\n }\n if ( !v3 )\n goto LABEL_4;\n v9[v3] = 0;\n v6 = strtol(v9, 0LL, 10);\n if ( v4 < v6 )\n v4 = v6;\n v1 = *v2++;\n v3 = 0;\n }\n while ( v1 );\nLABEL_10:\n if ( v3 )\n {\n v9[v3] = 0;\n v7 = strtol(v9, 0LL, 10);\n if ( v4 < (int)v7 )\n return v7;\n }\n return (unsigned int)v4;\n}", + "ida_strip_asm": "sub_1240:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 110h\nmov rax, fs:28h\nmov [rsp+128h+var_20], rax\nxor eax, eax\nmovzx eax, byte ptr [rdi]\ntest al, al\njz loc_1318\nlea rbx, [rdi+1]\nxor edx, edx\nxor r12d, r12d\nmov rbp, rsp\njmp short loc_1294\nloc_1280:\nmovsxd rcx, edx\nadd edx, 1\nmov [rsp+rcx+128h+var_128], al\nloc_1289:\nmovzx eax, byte ptr [rbx]\nadd rbx, 1\ntest al, al\njz short loc_12D0\nloc_1294:\nlea ecx, [rax-30h]\ncmp cl, 9\njbe short loc_1280\ntest edx, edx\njz short loc_1289\nmovsxd rdx, edx\nxor esi, esi; endptr\nmov rdi, rbp; nptr\nmov [rsp+rdx+128h+var_128], 0\nmov edx, 0Ah; base\ncall _strtol\ncmp r12d, eax\ncmovl r12d, eax\nmovzx eax, byte ptr [rbx]\nadd rbx, 1\nxor edx, edx\ntest al, al\njnz short loc_1294\nnop word ptr [rax+rax+00h]\nloc_12D0:\ntest edx, edx\njz short loc_12F1\nmovsxd rdx, edx\nxor esi, esi; endptr\nmov rdi, rsp; nptr\nmov [rsp+rdx+128h+var_128], 0\nmov edx, 0Ah; base\ncall _strtol\ncmp r12d, eax\ncmovl r12d, eax\nloc_12F1:\nmov rax, [rsp+128h+var_20]\nsub rax, fs:28h\njnz short loc_131D\nadd rsp, 110h\nmov eax, r12d\npop rbx\npop rbp\npop r12\nretn\nloc_1318:\nxor r12d, r12d\njmp short loc_12F1\nloc_131D:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1240(char *a1)\n{\n char v1; // al\n char *v2; // rbx\n int v3; // edx\n signed int v4; // r12d\n __int64 v5; // rcx\n int v6; // eax\n unsigned int v7; // eax\n char v9[264]; // [rsp+0h] [rbp-128h] BYREF\n unsigned __int64 v10; // [rsp+108h] [rbp-20h]\n\n v10 = __readfsqword(0x28u);\n v1 = *a1;\n if ( !*a1 )\n return 0;\n v2 = a1 + 1;\n v3 = 0;\n v4 = 0;\n do\n {\n while ( (unsigned __int8)(v1 - 48) <= 9u )\n {\n v5 = v3++;\n v9[v5] = v1;\nLABEL_4:\n v1 = *v2++;\n if ( !v1 )\n goto LABEL_10;\n }\n if ( !v3 )\n goto LABEL_4;\n v9[v3] = 0;\n v6 = strtol(v9, 0LL, 10);\n if ( v4 < v6 )\n v4 = v6;\n v1 = *v2++;\n v3 = 0;\n }\n while ( v1 );\nLABEL_10:\n if ( v3 )\n {\n v9[v3] = 0;\n v7 = strtol(v9, 0LL, 10);\n if ( v4 < (int)v7 )\n return v7;\n }\n return (unsigned int)v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1240(char *a1) {\n char v1;\n char *v2;\n int v3;\n signed int v4;\n long long v5;\n int v6;\n unsigned int v7;\n char v9[264];\n unsigned long long v10;\n v10 = __readfsqword(40u);\n v1 = *a1;\n if (!*a1) return 0;\n v2 = a1 + 1;\n v3 = 0;\n v4 = 0;\n do {\n while ((unsigned char)(v1 - 48) <= 9u) {\n v5 = v3++;\n v9[v5] = v1;\n LABEL_4:\n v1 = *v2++;\n if (!v1) goto LABEL_10;\n }\n if (!v3) goto LABEL_4;\n v9[v3] = 0;\n v6 = strtol(v9, 0LL, 10);\n if (v4 < v6) v4 = v6;\n v1 = *v2++;\n v3 = 0;\n } while (v1);\nLABEL_10:\n if (v3) {\n v9[v3] = 0;\n v7 = strtol(v9, 0LL, 10);\n if (v4 < (int)v7) return v7;\n }\n return (unsigned int)v4;\n}", + "ida_pseudo_norm": "long long func0(char *a1) {\n char v1;\n char *v2;\n int v3;\n signed int v4;\n long long v5;\n int v6;\n unsigned int v7;\n char v9[264];\n unsigned long long v10;\n v10 = __readfsqword(40u);\n v1 = *a1;\n if (!*a1) return 0;\n v2 = a1 + 1;\n v3 = 0;\n v4 = 0;\n do {\n while ((unsigned char)(v1 - 48) <= 9u) {\n v5 = v3++;\n v9[v5] = v1;\n LABEL_4:\n v1 = *v2++;\n if (!v1) goto LABEL_10;\n }\n if (!v3) goto LABEL_4;\n v9[v3] = 0;\n v6 = strtol(v9, 0LL, 10);\n if (v4 < v6) v4 = v6;\n v1 = *v2++;\n v3 = 0;\n } while (v1);\nLABEL_10:\n if (v3) {\n v9[v3] = 0;\n v7 = strtol(v9, 0LL, 10);\n if (v4 < (int)v7) return v7;\n }\n return (unsigned int)v4;\n}" + }, + { + "index": 832, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *input) {\n int max = 0;\n char temp[256];\n int index = 0;\n for (int i = 0; input[i] != '\\0'; i++) {\n if (input[i] >= '0' && input[i] <= '9') {\n temp[index++] = input[i];\n } else {\n if (index != 0) {\n temp[index] = '\\0';\n int number = atoi(temp);\n if (number > max) max = number;\n index = 0;\n }\n }\n }\n if (index != 0) {\n temp[index] = '\\0';\n int number = atoi(temp);\n if (number > max) max = number;\n }\n return max;\n}", + "test": "int main() {\n\n assert(func0(\"100klh564abc365bg\") == 564);\n\n assert(func0(\"hello300how546mer231\") == 546);\n\n assert(func0(\"its233beenalong343journey234\") == 343);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nsub $0x110,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x108(%rsp)\nxor %eax,%eax\nmovzbl (%rdi),%eax\ntest %al,%al\nje 1318 \nlea 0x1(%rdi),%rbx\nxor %edx,%edx\nxor %r12d,%r12d\nmov %rsp,%rbp\njmp 1294 \nnopl 0x0(%rax,%rax,1)\nmovslq %edx,%rcx\nadd $0x1,%edx\nmov %al,(%rsp,%rcx,1)\nmovzbl (%rbx),%eax\nadd $0x1,%rbx\ntest %al,%al\nje 12d0 \nlea -0x30(%rax),%ecx\ncmp $0x9,%cl\njbe 1280 \ntest %edx,%edx\nje 1289 \nmovslq %edx,%rdx\nxor %esi,%esi\nmov %rbp,%rdi\nmovb $0x0,(%rsp,%rdx,1)\nmov $0xa,%edx\ncallq 1090 \ncmp %eax,%r12d\ncmovl %eax,%r12d\nmovzbl (%rbx),%eax\nadd $0x1,%rbx\nxor %edx,%edx\ntest %al,%al\njne 1294 \nnopw 0x0(%rax,%rax,1)\ntest %edx,%edx\nje 12f1 \nmovslq %edx,%rdx\nxor %esi,%esi\nmov %rsp,%rdi\nmovb $0x0,(%rsp,%rdx,1)\nmov $0xa,%edx\ncallq 1090 \ncmp %eax,%r12d\ncmovl %eax,%r12d\nmov 0x108(%rsp),%rax\nxor %fs:0x28,%rax\njne 131d \nadd $0x110,%rsp\nmov %r12d,%eax\npop %rbx\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax,%rax,1)\nxor %r12d,%r12d\njmp 12f1 \ncallq 1070 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 110h\nmov rax, fs:28h\nmov [rsp+128h+var_20], rax\nxor eax, eax\nmovzx eax, byte ptr [rdi]\ntest al, al\njz loc_1318\nlea rbx, [rdi+1]\nxor edx, edx\nxor r12d, r12d\nmov rbp, rsp\njmp short loc_1294\nloc_1280:\nmovsxd rcx, edx\nadd edx, 1\nmov [rsp+rcx+128h+var_128], al\nloc_1289:\nmovzx eax, byte ptr [rbx]\nadd rbx, 1\ntest al, al\njz short loc_12D0\nloc_1294:\nlea ecx, [rax-30h]\ncmp cl, 9\njbe short loc_1280\ntest edx, edx\njz short loc_1289\nmovsxd rdx, edx\nxor esi, esi; endptr\nmov rdi, rbp; nptr\nmov [rsp+rdx+128h+var_128], 0\nmov edx, 0Ah; base\ncall _strtol\ncmp r12d, eax\ncmovl r12d, eax\nmovzx eax, byte ptr [rbx]\nadd rbx, 1\nxor edx, edx\ntest al, al\njnz short loc_1294\nnop word ptr [rax+rax+00h]\nloc_12D0:\ntest edx, edx\njz short loc_12F1\nmovsxd rdx, edx\nxor esi, esi; endptr\nmov rdi, rsp; nptr\nmov [rsp+rdx+128h+var_128], 0\nmov edx, 0Ah; base\ncall _strtol\ncmp r12d, eax\ncmovl r12d, eax\nloc_12F1:\nmov rax, [rsp+128h+var_20]\nsub rax, fs:28h\njnz short loc_131D\nadd rsp, 110h\nmov eax, r12d\npop rbx\npop rbp\npop r12\nretn\nloc_1318:\nxor r12d, r12d\njmp short loc_12F1\nloc_131D:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(char *a1)\n{\n char v1; // al\n char *v2; // rbx\n int v3; // edx\n signed int v4; // r12d\n __int64 v5; // rcx\n int v6; // eax\n unsigned int v7; // eax\n char v9[264]; // [rsp+0h] [rbp-128h] BYREF\n unsigned __int64 v10; // [rsp+108h] [rbp-20h]\n\n v10 = __readfsqword(0x28u);\n v1 = *a1;\n if ( !*a1 )\n return 0;\n v2 = a1 + 1;\n v3 = 0;\n v4 = 0;\n do\n {\n while ( (unsigned __int8)(v1 - 48) <= 9u )\n {\n v5 = v3++;\n v9[v5] = v1;\nLABEL_4:\n v1 = *v2++;\n if ( !v1 )\n goto LABEL_10;\n }\n if ( !v3 )\n goto LABEL_4;\n v9[v3] = 0;\n v6 = strtol(v9, 0LL, 10);\n if ( v4 < v6 )\n v4 = v6;\n v1 = *v2++;\n v3 = 0;\n }\n while ( v1 );\nLABEL_10:\n if ( v3 )\n {\n v9[v3] = 0;\n v7 = strtol(v9, 0LL, 10);\n if ( v4 < (int)v7 )\n return v7;\n }\n return (unsigned int)v4;\n}", + "ida_strip_asm": "sub_1240:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 110h\nmov rax, fs:28h\nmov [rsp+128h+var_20], rax\nxor eax, eax\nmovzx eax, byte ptr [rdi]\ntest al, al\njz loc_1318\nlea rbx, [rdi+1]\nxor edx, edx\nxor r12d, r12d\nmov rbp, rsp\njmp short loc_1294\nloc_1280:\nmovsxd rcx, edx\nadd edx, 1\nmov [rsp+rcx+128h+var_128], al\nloc_1289:\nmovzx eax, byte ptr [rbx]\nadd rbx, 1\ntest al, al\njz short loc_12D0\nloc_1294:\nlea ecx, [rax-30h]\ncmp cl, 9\njbe short loc_1280\ntest edx, edx\njz short loc_1289\nmovsxd rdx, edx\nxor esi, esi; endptr\nmov rdi, rbp; nptr\nmov [rsp+rdx+128h+var_128], 0\nmov edx, 0Ah; base\ncall _strtol\ncmp r12d, eax\ncmovl r12d, eax\nmovzx eax, byte ptr [rbx]\nadd rbx, 1\nxor edx, edx\ntest al, al\njnz short loc_1294\nnop word ptr [rax+rax+00h]\nloc_12D0:\ntest edx, edx\njz short loc_12F1\nmovsxd rdx, edx\nxor esi, esi; endptr\nmov rdi, rsp; nptr\nmov [rsp+rdx+128h+var_128], 0\nmov edx, 0Ah; base\ncall _strtol\ncmp r12d, eax\ncmovl r12d, eax\nloc_12F1:\nmov rax, [rsp+128h+var_20]\nsub rax, fs:28h\njnz short loc_131D\nadd rsp, 110h\nmov eax, r12d\npop rbx\npop rbp\npop r12\nretn\nloc_1318:\nxor r12d, r12d\njmp short loc_12F1\nloc_131D:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1240(char *a1)\n{\n char v1; // al\n char *v2; // rbx\n int v3; // edx\n signed int v4; // r12d\n __int64 v5; // rcx\n int v6; // eax\n unsigned int v7; // eax\n char v9[264]; // [rsp+0h] [rbp-128h] BYREF\n unsigned __int64 v10; // [rsp+108h] [rbp-20h]\n\n v10 = __readfsqword(0x28u);\n v1 = *a1;\n if ( !*a1 )\n return 0;\n v2 = a1 + 1;\n v3 = 0;\n v4 = 0;\n do\n {\n while ( (unsigned __int8)(v1 - 48) <= 9u )\n {\n v5 = v3++;\n v9[v5] = v1;\nLABEL_4:\n v1 = *v2++;\n if ( !v1 )\n goto LABEL_10;\n }\n if ( !v3 )\n goto LABEL_4;\n v9[v3] = 0;\n v6 = strtol(v9, 0LL, 10);\n if ( v4 < v6 )\n v4 = v6;\n v1 = *v2++;\n v3 = 0;\n }\n while ( v1 );\nLABEL_10:\n if ( v3 )\n {\n v9[v3] = 0;\n v7 = strtol(v9, 0LL, 10);\n if ( v4 < (int)v7 )\n return v7;\n }\n return (unsigned int)v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1240(char *a1) {\n char v1;\n char *v2;\n int v3;\n signed int v4;\n long long v5;\n int v6;\n unsigned int v7;\n char v9[264];\n unsigned long long v10;\n v10 = __readfsqword(40u);\n v1 = *a1;\n if (!*a1) return 0;\n v2 = a1 + 1;\n v3 = 0;\n v4 = 0;\n do {\n while ((unsigned char)(v1 - 48) <= 9u) {\n v5 = v3++;\n v9[v5] = v1;\n LABEL_4:\n v1 = *v2++;\n if (!v1) goto LABEL_10;\n }\n if (!v3) goto LABEL_4;\n v9[v3] = 0;\n v6 = strtol(v9, 0LL, 10);\n if (v4 < v6) v4 = v6;\n v1 = *v2++;\n v3 = 0;\n } while (v1);\nLABEL_10:\n if (v3) {\n v9[v3] = 0;\n v7 = strtol(v9, 0LL, 10);\n if (v4 < (int)v7) return v7;\n }\n return (unsigned int)v4;\n}", + "ida_pseudo_norm": "long long func0(char *a1) {\n char v1;\n char *v2;\n int v3;\n signed int v4;\n long long v5;\n int v6;\n unsigned int v7;\n char v9[264];\n unsigned long long v10;\n v10 = __readfsqword(40u);\n v1 = *a1;\n if (!*a1) return 0;\n v2 = a1 + 1;\n v3 = 0;\n v4 = 0;\n do {\n while ((unsigned char)(v1 - 48) <= 9u) {\n v5 = v3++;\n v9[v5] = v1;\n LABEL_4:\n v1 = *v2++;\n if (!v1) goto LABEL_10;\n }\n if (!v3) goto LABEL_4;\n v9[v3] = 0;\n v6 = strtol(v9, 0LL, 10);\n if (v4 < v6) v4 = v6;\n v1 = *v2++;\n v3 = 0;\n } while (v1);\nLABEL_10:\n if (v3) {\n v9[v3] = 0;\n v7 = strtol(v9, 0LL, 10);\n if (v4 < (int)v7) return v7;\n }\n return (unsigned int)v4;\n}" + }, + { + "index": 833, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int key;\n\n char* value;\n\n} Item;\n\n\n\ntypedef struct {\n\n Item* items;\n\n int size;\n\n} Dictionary;\n\n\n\n", + "func": "int* func0(Dictionary dict) {\n int* keys = malloc(dict.size * sizeof(int));\n for (int i = 0; i < dict.size; i++) {\n keys[i] = dict.items[i].key;\n }\n return keys;\n}", + "test": "int main() {\n\n Dictionary dict1 = {\n\n .items = (Item[]){{1, \"python\"}, {2, \"java\"}},\n\n .size = 2\n\n };\n\n int* keys1 = func0(dict1);\n\n assert(keys1[0] == 1 && keys1[1] == 2);\n\n free(keys1);\n\n \n\n Dictionary dict2 = {\n\n .items = (Item[]){{10, \"red\"}, {20, \"blue\"}, {30, \"black\"}},\n\n .size = 3\n\n };\n\n int* keys2 = func0(dict2);\n\n assert(keys2[0] == 10 && keys2[1] == 20 && keys2[2] == 30);\n\n free(keys2);\n\n\n\n Dictionary dict3 = {\n\n .items = (Item[]){{27, \"language\"}, {39, \"java\"}, {44, \"little\"}},\n\n .size = 3\n\n };\n\n int* keys3 = func0(dict3);\n\n assert(keys3[0] == 27 && keys3[1] == 39 && keys3[2] == 44);\n\n free(keys3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,%rax\nmov %rsi,%rcx\nmov %rcx,%rdx\nmov %rax,-0x20(%rbp)\nmov %rdx,-0x18(%rbp)\nmov -0x18(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 1212 \nmov -0x20(%rbp),%rax\nmov -0xc(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x4,%rdx\nadd %rdx,%rax\nmov -0xc(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0xc(%rbp)\nmov -0x18(%rbp),%eax\ncmp %eax,-0xc(%rbp)\njl 11e4 \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov rax, rdi\nmov rcx, rsi\nmov rdx, rcx\nmov [rbp+var_20], rax\nmov [rbp+var_18], rdx\nmov eax, dword ptr [rbp+var_18]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp short loc_1212\nloc_11E4:\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nshl rdx, 4\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_C], 1\nloc_1212:\nmov eax, dword ptr [rbp+var_18]\ncmp [rbp+var_C], eax\njl short loc_11E4\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+14h] [rbp-Ch]\n _DWORD *v4; // [rsp+18h] [rbp-8h]\n\n v4 = malloc(4LL * a2);\n for ( i = 0; i < a2; ++i )\n v4[i] = *(_DWORD *)(16LL * i + a1);\n return v4;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov rax, rdi\nmov rcx, rsi\nmov rdx, rcx\nmov [rbp+var_20], rax\nmov [rbp+var_18], rdx\nmov eax, dword ptr [rbp+var_18]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp short loc_1212\nloc_11E4:\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nshl rdx, 4\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_C], 1\nloc_1212:\nmov eax, dword ptr [rbp+var_18]\ncmp [rbp+var_C], eax\njl short loc_11E4\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(__int64 a1, int a2)\n{\n int i; // [rsp+14h] [rbp-Ch]\n _DWORD *v4; // [rsp+18h] [rbp-8h]\n\n v4 = malloc(4LL * a2);\n for ( i = 0; i < a2; ++i )\n v4[i] = *(_DWORD *)(16LL * i + a1);\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(long long a1, int a2) {\n int i;\n uint32_t *v4;\n v4 = malloc(4LL * a2);\n for (i = 0; i < a2; ++i) v4[i] = *(uint32_t *)(16LL * i + a1);\n return v4;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2) {\n int i;\n uint32_t *v4;\n v4 = malloc(4LL * a2);\n for (i = 0; i < a2; ++i) v4[i] = *(uint32_t *)(16LL * i + a1);\n return v4;\n}" + }, + { + "index": 833, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int key;\n\n char* value;\n\n} Item;\n\n\n\ntypedef struct {\n\n Item* items;\n\n int size;\n\n} Dictionary;\n\n\n\n", + "func": "int* func0(Dictionary dict) {\n int* keys = malloc(dict.size * sizeof(int));\n for (int i = 0; i < dict.size; i++) {\n keys[i] = dict.items[i].key;\n }\n return keys;\n}", + "test": "int main() {\n\n Dictionary dict1 = {\n\n .items = (Item[]){{1, \"python\"}, {2, \"java\"}},\n\n .size = 2\n\n };\n\n int* keys1 = func0(dict1);\n\n assert(keys1[0] == 1 && keys1[1] == 2);\n\n free(keys1);\n\n \n\n Dictionary dict2 = {\n\n .items = (Item[]){{10, \"red\"}, {20, \"blue\"}, {30, \"black\"}},\n\n .size = 3\n\n };\n\n int* keys2 = func0(dict2);\n\n assert(keys2[0] == 10 && keys2[1] == 20 && keys2[2] == 30);\n\n free(keys2);\n\n\n\n Dictionary dict3 = {\n\n .items = (Item[]){{27, \"language\"}, {39, \"java\"}, {44, \"little\"}},\n\n .size = 3\n\n };\n\n int* keys3 = func0(dict3);\n\n assert(keys3[0] == 27 && keys3[1] == 39 && keys3[2] == 44);\n\n free(keys3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbp\nmov %rsi,%rbx\nmovslq %esi,%rdi\nshl $0x2,%rdi\ncallq 10b0 \ntest %ebx,%ebx\njle 11ec \nmov %rbp,%rdx\nmov %rax,%rcx\nlea -0x1(%rbx),%esi\nshl $0x4,%rsi\nlea 0x10(%rbp,%rsi,1),%rdi\nmov (%rdx),%esi\nmov %esi,(%rcx)\nadd $0x10,%rdx\nadd $0x4,%rcx\ncmp %rdi,%rdx\njne 11db \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov r12, rdi\nmov rbp, rsi\nmovsxd rbx, esi\nlea rdi, ds:0[rbx*4]; size\ncall _malloc\ntest ebp, ebp\njle short loc_11EA\nmov rdx, r12\nmov rcx, rax\nshl rbx, 4\nlea rdi, [rbx+r12]\nloc_11D9:\nmov esi, [rdx]\nmov [rcx], esi\nadd rdx, 10h\nadd rcx, 4\ncmp rdx, rdi\njnz short loc_11D9\nloc_11EA:\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *result; // rax\n _DWORD *v3; // rdx\n _DWORD *v4; // rcx\n\n result = malloc(4LL * a2);\n if ( a2 > 0 )\n {\n v3 = a1;\n v4 = result;\n do\n {\n *v4 = *v3;\n v3 += 4;\n ++v4;\n }\n while ( v3 != &a1[4 * a2] );\n }\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r12\npush rbp\npush rbx\nmov r12, rdi\nmov rbp, rsi\nmovsxd rbx, esi\nlea rdi, ds:0[rbx*4]; size\ncall _malloc\ntest ebp, ebp\njle short loc_11EA\nmov rdx, r12\nmov rcx, rax\nshl rbx, 4\nlea rdi, [rbx+r12]\nloc_11D9:\nmov esi, [rdx]\nmov [rcx], esi\nadd rdx, 10h\nadd rcx, 4\ncmp rdx, rdi\njnz short loc_11D9\nloc_11EA:\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(_DWORD *a1, int a2)\n{\n _DWORD *result; // rax\n _DWORD *v3; // rdx\n _DWORD *v4; // rcx\n\n result = malloc(4LL * a2);\n if ( a2 > 0 )\n {\n v3 = a1;\n v4 = result;\n do\n {\n *v4 = *v3;\n v3 += 4;\n ++v4;\n }\n while ( v3 != &a1[4 * a2] );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(uint32_t *a1, int a2) {\n uint32_t *result;\n uint32_t *v3;\n uint32_t *v4;\n result = malloc(4LL * a2);\n if (a2 > 0) {\n v3 = a1;\n v4 = result;\n do {\n *v4 = *v3;\n v3 += 4;\n ++v4;\n } while (v3 != &a1[4 * a2]);\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(uint32_t *a1, int a2) {\n uint32_t *result;\n uint32_t *v3;\n uint32_t *v4;\n result = malloc(4LL * a2);\n if (a2 > 0) {\n v3 = a1;\n v4 = result;\n do {\n *v4 = *v3;\n v3 += 4;\n ++v4;\n } while (v3 != &a1[4 * a2]);\n }\n return result;\n}" + }, + { + "index": 833, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int key;\n\n char* value;\n\n} Item;\n\n\n\ntypedef struct {\n\n Item* items;\n\n int size;\n\n} Dictionary;\n\n\n\n", + "func": "int* func0(Dictionary dict) {\n int* keys = malloc(dict.size * sizeof(int));\n for (int i = 0; i < dict.size; i++) {\n keys[i] = dict.items[i].key;\n }\n return keys;\n}", + "test": "int main() {\n\n Dictionary dict1 = {\n\n .items = (Item[]){{1, \"python\"}, {2, \"java\"}},\n\n .size = 2\n\n };\n\n int* keys1 = func0(dict1);\n\n assert(keys1[0] == 1 && keys1[1] == 2);\n\n free(keys1);\n\n \n\n Dictionary dict2 = {\n\n .items = (Item[]){{10, \"red\"}, {20, \"blue\"}, {30, \"black\"}},\n\n .size = 3\n\n };\n\n int* keys2 = func0(dict2);\n\n assert(keys2[0] == 10 && keys2[1] == 20 && keys2[2] == 30);\n\n free(keys2);\n\n\n\n Dictionary dict3 = {\n\n .items = (Item[]){{27, \"language\"}, {39, \"java\"}, {44, \"little\"}},\n\n .size = 3\n\n };\n\n int* keys3 = func0(dict3);\n\n assert(keys3[0] == 27 && keys3[1] == 39 && keys3[2] == 44);\n\n free(keys3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsi,%rbp\npush %rbx\nmov %rdi,%rbx\nmovslq %esi,%rdi\nshl $0x2,%rdi\nsub $0x8,%rsp\ncallq 10b0 \ntest %ebp,%ebp\njle 13ba \nlea -0x1(%rbp),%ecx\nmov %rbx,%rdi\nmov %rax,%rdx\nshl $0x4,%rcx\nlea 0x10(%rbx,%rcx,1),%rsi\nnopw 0x0(%rax,%rax,1)\nmov (%rdi),%ecx\nadd $0x10,%rdi\nadd $0x4,%rdx\nmov %ecx,-0x4(%rdx)\ncmp %rsi,%rdi\njne 13a8 \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r12\nmov r12, rsi\npush rbp\nmovsxd rbp, esi\npush rbx\nmov rbx, rdi\nlea rdi, ds:0[rbp*4]; size\ncall _malloc\ntest r12d, r12d\njle short loc_13BA\nshl rbp, 4\nmov rdx, rbx\nmov rcx, rax\nlea rdi, [rbp+rbx+0]\nnop word ptr [rax+rax+00h]\nloc_13A8:\nmov esi, [rdx]\nadd rdx, 10h\nadd rcx, 4\nmov [rcx-4], esi\ncmp rdx, rdi\njnz short loc_13A8\nloc_13BA:\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2)\n{\n _DWORD *result; // rax\n int *v3; // rdx\n _DWORD *v4; // rcx\n int *v5; // rdi\n int v6; // esi\n\n result = malloc(4LL * a2);\n if ( a2 > 0 )\n {\n v3 = a1;\n v4 = result;\n v5 = &a1[4 * a2];\n do\n {\n v6 = *v3;\n v3 += 4;\n *v4++ = v6;\n }\n while ( v3 != v5 );\n }\n return result;\n}", + "ida_strip_asm": "sub_1370:\nendbr64\npush r12\nmov r12, rsi\npush rbp\nmovsxd rbp, esi\npush rbx\nmov rbx, rdi\nlea rdi, ds:0[rbp*4]; size\ncall _malloc\ntest r12d, r12d\njle short loc_13BA\nshl rbp, 4\nmov rdx, rbx\nmov rcx, rax\nlea rdi, [rbp+rbx+0]\nnop word ptr [rax+rax+00h]\nloc_13A8:\nmov esi, [rdx]\nadd rdx, 10h\nadd rcx, 4\nmov [rcx-4], esi\ncmp rdx, rdi\njnz short loc_13A8\nloc_13BA:\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1370(int *a1, int a2)\n{\n _DWORD *result; // rax\n int *v3; // rdx\n _DWORD *v4; // rcx\n int *v5; // rdi\n int v6; // esi\n\n result = malloc(4LL * a2);\n if ( a2 > 0 )\n {\n v3 = a1;\n v4 = result;\n v5 = &a1[4 * a2];\n do\n {\n v6 = *v3;\n v3 += 4;\n *v4++ = v6;\n }\n while ( v3 != v5 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1370(int *a1, int a2) {\n uint32_t *result;\n int *v3;\n uint32_t *v4;\n int *v5;\n int v6;\n result = malloc(4LL * a2);\n if (a2 > 0) {\n v3 = a1;\n v4 = result;\n v5 = &a1[4 * a2];\n do {\n v6 = *v3;\n v3 += 4;\n *v4++ = v6;\n } while (v3 != v5);\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2) {\n uint32_t *result;\n int *v3;\n uint32_t *v4;\n int *v5;\n int v6;\n result = malloc(4LL * a2);\n if (a2 > 0) {\n v3 = a1;\n v4 = result;\n v5 = &a1[4 * a2];\n do {\n v6 = *v3;\n v3 += 4;\n *v4++ = v6;\n } while (v3 != v5);\n }\n return result;\n}" + }, + { + "index": 833, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int key;\n\n char* value;\n\n} Item;\n\n\n\ntypedef struct {\n\n Item* items;\n\n int size;\n\n} Dictionary;\n\n\n\n", + "func": "int* func0(Dictionary dict) {\n int* keys = malloc(dict.size * sizeof(int));\n for (int i = 0; i < dict.size; i++) {\n keys[i] = dict.items[i].key;\n }\n return keys;\n}", + "test": "int main() {\n\n Dictionary dict1 = {\n\n .items = (Item[]){{1, \"python\"}, {2, \"java\"}},\n\n .size = 2\n\n };\n\n int* keys1 = func0(dict1);\n\n assert(keys1[0] == 1 && keys1[1] == 2);\n\n free(keys1);\n\n \n\n Dictionary dict2 = {\n\n .items = (Item[]){{10, \"red\"}, {20, \"blue\"}, {30, \"black\"}},\n\n .size = 3\n\n };\n\n int* keys2 = func0(dict2);\n\n assert(keys2[0] == 10 && keys2[1] == 20 && keys2[2] == 30);\n\n free(keys2);\n\n\n\n Dictionary dict3 = {\n\n .items = (Item[]){{27, \"language\"}, {39, \"java\"}, {44, \"little\"}},\n\n .size = 3\n\n };\n\n int* keys3 = func0(dict3);\n\n assert(keys3[0] == 27 && keys3[1] == 39 && keys3[2] == 44);\n\n free(keys3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rdi,%rbp\nmovslq %esi,%rdi\npush %rbx\nshl $0x2,%rdi\nmov %rsi,%rbx\nsub $0x8,%rsp\ncallq 10b0 \ntest %ebx,%ebx\njle 1446 \nlea -0x1(%rbx),%edi\ncmp $0x3,%edi\njbe 144d \nmov %edi,%r8d\nmov %rbp,%rdx\nmov %rax,%rcx\nshr $0x2,%r8d\nshl $0x6,%r8\nadd %rbp,%r8\nnopl 0x0(%rax)\nmovdqu (%rdx),%xmm0\nmovdqu 0x10(%rdx),%xmm2\nadd $0x40,%rdx\nadd $0x10,%rcx\nmovdqu -0x20(%rdx),%xmm1\nmovdqu -0x10(%rdx),%xmm3\nshufps $0x88,%xmm2,%xmm0\nshufps $0x88,%xmm3,%xmm1\nshufps $0x88,%xmm1,%xmm0\nmovups %xmm0,-0x10(%rcx)\ncmp %r8,%rdx\njne 13b8 \nand $0xfffffffc,%edi\nmov %edi,%edx\nmovslq %edx,%rcx\nmov %rcx,%rsi\nshl $0x4,%rsi\nmov 0x0(%rbp,%rsi,1),%esi\nmov %esi,(%rax,%rcx,4)\nlea 0x1(%rdx),%ecx\ncmp %ecx,%ebx\njle 1446 \nmovslq %ecx,%rcx\nmov %rcx,%rsi\nshl $0x4,%rsi\nmov 0x0(%rbp,%rsi,1),%esi\nmov %esi,(%rax,%rcx,4)\nlea 0x2(%rdx),%ecx\ncmp %ecx,%ebx\njle 1446 \nmovslq %ecx,%rcx\nadd $0x3,%edx\nmov %rcx,%rsi\nshl $0x4,%rsi\nmov 0x0(%rbp,%rsi,1),%esi\nmov %esi,(%rax,%rcx,4)\ncmp %edx,%ebx\njle 1446 \nmovslq %edx,%rdx\nmov %rdx,%rcx\nshl $0x4,%rcx\nmov 0x0(%rbp,%rcx,1),%ecx\nmov %ecx,(%rax,%rdx,4)\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nxor %edx,%edx\njmp 13ed \nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rdi\nmovsxd rdi, esi\npush rbx\nshl rdi, 2; size\nmov rbx, rsi\nsub rsp, 8\ncall _malloc\nmov rdi, rax\ntest ebx, ebx\njle loc_1435\nlea esi, [rbx-1]\ncmp esi, 3\njbe loc_143F\nmov ecx, esi\nmov rax, rbp\nmov rdx, rdi\nshr ecx, 2\nshl rcx, 6\nadd rcx, rbp\nnop dword ptr [rax]\nloc_13B8:\nmovdqu xmm0, xmmword ptr [rax]\nmovdqu xmm2, xmmword ptr [rax+10h]\nadd rax, 40h ; '@'\nadd rdx, 10h\nmovdqu xmm1, xmmword ptr [rax-20h]\nmovdqu xmm3, xmmword ptr [rax-10h]\nshufps xmm0, xmm2, 88h\nshufps xmm1, xmm3, 88h\nshufps xmm0, xmm1, 88h\nmovups xmmword ptr [rdx-10h], xmm0\ncmp rax, rcx\njnz short loc_13B8\nmov eax, esi\nand eax, 0FFFFFFFCh\nloc_13ED:\nmovsxd rcx, eax\nmov rdx, rcx\nlea rsi, ds:0[rcx*4]\nshl rdx, 4\nmov r8d, [rbp+rdx+0]\nmov [rdi+rcx*4], r8d\nlea ecx, [rax+1]\ncmp ebx, ecx\njle short loc_1435\nmov ecx, [rdx+rbp+10h]\nmov [rdi+rsi+4], ecx\nlea ecx, [rax+2]\ncmp ecx, ebx\njge short loc_1435\nmov ecx, [rdx+rbp+20h]\nadd eax, 3\nmov [rdi+rsi+8], ecx\ncmp ebx, eax\njle short loc_1435\nmov eax, [rdx+rbp+30h]\nmov [rdi+rsi+0Ch], eax\nloc_1435:\nadd rsp, 8\nmov rax, rdi\npop rbx\npop rbp\nretn\nloc_143F:\nxor eax, eax\njmp short loc_13ED", + "ida_pseudo": "__m128 *__fastcall func0(const __m128i *a1, int a2)\n{\n __m128 *v4; // rdi\n unsigned int v5; // esi\n const __m128i *v6; // rax\n __m128 *v7; // rdx\n __m128 v8; // xmm0\n __m128 v9; // xmm2\n signed int v10; // eax\n __int64 v11; // rsi\n __int64 v12; // rdx\n\n v4 = (__m128 *)malloc(4LL * a2);\n if ( a2 > 0 )\n {\n v5 = a2 - 1;\n if ( v5 <= 3 )\n {\n v10 = 0;\n }\n else\n {\n v6 = a1;\n v7 = v4;\n do\n {\n v8 = (__m128)_mm_loadu_si128(v6);\n v9 = (__m128)_mm_loadu_si128(v6 + 1);\n v6 += 4;\n ++v7;\n v7[-1] = _mm_shuffle_ps(\n _mm_shuffle_ps(v8, v9, 136),\n _mm_shuffle_ps((__m128)_mm_loadu_si128(v6 - 2), (__m128)_mm_loadu_si128(v6 - 1), 136),\n 136);\n }\n while ( v6 != &a1[4 * (unsigned __int64)(v5 >> 2)] );\n v10 = v5 & 0xFFFFFFFC;\n }\n v11 = v10;\n v12 = v10;\n v4->m128_i32[v11] = a1[v12].m128i_i32[0];\n if ( a2 > v10 + 1 )\n {\n v4->m128_i32[v11 + 1] = a1[v12 + 1].m128i_i32[0];\n if ( v10 + 2 < a2 )\n {\n v4->m128_i32[v11 + 2] = a1[v12 + 2].m128i_i32[0];\n if ( a2 > v10 + 3 )\n v4->m128_i32[v11 + 3] = a1[v12 + 3].m128i_i32[0];\n }\n }\n }\n return v4;\n}", + "ida_strip_asm": "sub_1370:\nendbr64\npush rbp\nmov rbp, rdi\nmovsxd rdi, esi\npush rbx\nshl rdi, 2; size\nmov rbx, rsi\nsub rsp, 8\ncall _malloc\nmov rdi, rax\ntest ebx, ebx\njle loc_1435\nlea esi, [rbx-1]\ncmp esi, 3\njbe loc_143F\nmov ecx, esi\nmov rax, rbp\nmov rdx, rdi\nshr ecx, 2\nshl rcx, 6\nadd rcx, rbp\nnop dword ptr [rax]\nloc_13B8:\nmovdqu xmm0, xmmword ptr [rax]\nmovdqu xmm2, xmmword ptr [rax+10h]\nadd rax, 40h ; '@'\nadd rdx, 10h\nmovdqu xmm1, xmmword ptr [rax-20h]\nmovdqu xmm3, xmmword ptr [rax-10h]\nshufps xmm0, xmm2, 88h\nshufps xmm1, xmm3, 88h\nshufps xmm0, xmm1, 88h\nmovups xmmword ptr [rdx-10h], xmm0\ncmp rax, rcx\njnz short loc_13B8\nmov eax, esi\nand eax, 0FFFFFFFCh\nloc_13ED:\nmovsxd rcx, eax\nmov rdx, rcx\nlea rsi, ds:0[rcx*4]\nshl rdx, 4\nmov r8d, [rbp+rdx+0]\nmov [rdi+rcx*4], r8d\nlea ecx, [rax+1]\ncmp ebx, ecx\njle short loc_1435\nmov ecx, [rdx+rbp+10h]\nmov [rdi+rsi+4], ecx\nlea ecx, [rax+2]\ncmp ecx, ebx\njge short loc_1435\nmov ecx, [rdx+rbp+20h]\nadd eax, 3\nmov [rdi+rsi+8], ecx\ncmp ebx, eax\njle short loc_1435\nmov eax, [rdx+rbp+30h]\nmov [rdi+rsi+0Ch], eax\nloc_1435:\nadd rsp, 8\nmov rax, rdi\npop rbx\npop rbp\nretn\nloc_143F:\nxor eax, eax\njmp short loc_13ED", + "ida_strip_pseudo": "__m128 *__fastcall sub_1370(const __m128i *a1, int a2)\n{\n __m128 *v4; // rdi\n unsigned int v5; // esi\n const __m128i *v6; // rax\n __m128 *v7; // rdx\n __m128 v8; // xmm0\n __m128 v9; // xmm2\n signed int v10; // eax\n __int64 v11; // rsi\n __int64 v12; // rdx\n\n v4 = (__m128 *)malloc(4LL * a2);\n if ( a2 > 0 )\n {\n v5 = a2 - 1;\n if ( v5 <= 3 )\n {\n v10 = 0;\n }\n else\n {\n v6 = a1;\n v7 = v4;\n do\n {\n v8 = (__m128)_mm_loadu_si128(v6);\n v9 = (__m128)_mm_loadu_si128(v6 + 1);\n v6 += 4;\n ++v7;\n v7[-1] = _mm_shuffle_ps(\n _mm_shuffle_ps(v8, v9, 136),\n _mm_shuffle_ps((__m128)_mm_loadu_si128(v6 - 2), (__m128)_mm_loadu_si128(v6 - 1), 136),\n 136);\n }\n while ( v6 != &a1[4 * (unsigned __int64)(v5 >> 2)] );\n v10 = v5 & 0xFFFFFFFC;\n }\n v11 = v10;\n v12 = v10;\n v4->m128_i32[v11] = a1[v12].m128i_i32[0];\n if ( a2 > v10 + 1 )\n {\n v4->m128_i32[v11 + 1] = a1[v12 + 1].m128i_i32[0];\n if ( v10 + 2 < a2 )\n {\n v4->m128_i32[v11 + 2] = a1[v12 + 2].m128i_i32[0];\n if ( a2 > v10 + 3 )\n v4->m128_i32[v11 + 3] = a1[v12 + 3].m128i_i32[0];\n }\n }\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__m128 *sub_1370(const __m128i *a1, int a2) {\n __m128 *v4;\n unsigned int v5;\n const __m128i *v6;\n __m128 *v7;\n __m128 v8;\n __m128 v9;\n signed int v10;\n long long v11;\n long long v12;\n v4 = (__m128 *)malloc(4LL * a2);\n if (a2 > 0) {\n v5 = a2 - 1;\n if (v5 <= 3) {\n v10 = 0;\n } else {\n v6 = a1;\n v7 = v4;\n do {\n v8 = (__m128)_mm_loadu_si128(v6);\n v9 = (__m128)_mm_loadu_si128(v6 + 1);\n v6 += 4;\n ++v7;\n v7[-1] =\n _mm_shuffle_ps(_mm_shuffle_ps(v8, v9, 136),\n _mm_shuffle_ps((__m128)_mm_loadu_si128(v6 - 2),\n (__m128)_mm_loadu_si128(v6 - 1), 136),\n 136);\n } while (v6 != &a1[4 * (unsigned long long)(v5 >> 2)]);\n v10 = v5 & 4294967292;\n }\n v11 = v10;\n v12 = v10;\n v4->m128_i32[v11] = a1[v12].m128i_i32[0];\n if (a2 > v10 + 1) {\n v4->m128_i32[v11 + 1] = a1[v12 + 1].m128i_i32[0];\n if (v10 + 2 < a2) {\n v4->m128_i32[v11 + 2] = a1[v12 + 2].m128i_i32[0];\n if (a2 > v10 + 3) v4->m128_i32[v11 + 3] = a1[v12 + 3].m128i_i32[0];\n }\n }\n }\n return v4;\n}", + "ida_pseudo_norm": "__m128 *func0(const __m128i *a1, int a2) {\n __m128 *v4;\n unsigned int v5;\n const __m128i *v6;\n __m128 *v7;\n __m128 v8;\n __m128 v9;\n signed int v10;\n long long v11;\n long long v12;\n v4 = (__m128 *)malloc(4LL * a2);\n if (a2 > 0) {\n v5 = a2 - 1;\n if (v5 <= 3) {\n v10 = 0;\n } else {\n v6 = a1;\n v7 = v4;\n do {\n v8 = (__m128)_mm_loadu_si128(v6);\n v9 = (__m128)_mm_loadu_si128(v6 + 1);\n v6 += 4;\n ++v7;\n v7[-1] =\n _mm_shuffle_ps(_mm_shuffle_ps(v8, v9, 136),\n _mm_shuffle_ps((__m128)_mm_loadu_si128(v6 - 2),\n (__m128)_mm_loadu_si128(v6 - 1), 136),\n 136);\n } while (v6 != &a1[4 * (unsigned long long)(v5 >> 2)]);\n v10 = v5 & 4294967292;\n }\n v11 = v10;\n v12 = v10;\n v4->m128_i32[v11] = a1[v12].m128i_i32[0];\n if (a2 > v10 + 1) {\n v4->m128_i32[v11 + 1] = a1[v12 + 1].m128i_i32[0];\n if (v10 + 2 < a2) {\n v4->m128_i32[v11 + 2] = a1[v12 + 2].m128i_i32[0];\n if (a2 > v10 + 3) v4->m128_i32[v11 + 3] = a1[v12 + 3].m128i_i32[0];\n }\n }\n }\n return v4;\n}" + }, + { + "index": 834, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int **func0(int n) {\n if (n <= 0) return NULL;\n int **matrix = (int **)malloc(n * sizeof(int *));\n for (int i = 0; i < n; i++) {\n matrix[i] = (int *)calloc(n, sizeof(int));\n }\n int row_st = 0, row_ed = n - 1;\n int col_st = 0, col_ed = n - 1;\n int current = 1;\n while (1) {\n if (current > n * n) break;\n for (int c = col_st; c <= col_ed; c++) {\n matrix[row_st][c] = current++;\n }\n row_st++;\n for (int r = row_st; r <= row_ed; r++) {\n matrix[r][col_ed] = current++;\n }\n col_ed--;\n for (int c = col_ed; c >= col_st; c--) {\n matrix[row_ed][c] = current++;\n }\n row_ed--;\n for (int r = row_ed; r >= row_st; r--) {\n matrix[r][col_st] = current++;\n }\n col_st++;\n }\n return matrix;\n}", + "test": "int main() {\n\n int n1 = 3, n2 = 2, n7 = 7;\n\n \n\n int expected1[3][3] = {{1, 2, 3}, {8, 9, 4}, {7, 6, 5}};\n\n int expected2[2][2] = {{1,2}, {4,3}};\n\n int expected7[7][7] = {{1, 2, 3, 4, 5, 6, 7}, {24, 25, 26, 27, 28, 29, 8}, {23, 40, 41, 42, 43, 30, 9}, {22, 39, 48, 49, 44, 31, 10}, {21, 38, 47, 46, 45, 32, 11}, {20, 37, 36, 35, 34, 33, 12}, {19, 18, 17, 16, 15, 14, 13}};\n\n \n\n int **result1 = func0(n1);\n\n int **result2 = func0(n2);\n\n int **result7 = func0(n7);\n\n \n\n for (int i = 0; i < n1; i++) {\n\n for (int j = 0; j < n1; j++) {\n\n assert(result1[i][j] == expected1[i][j]);\n\n }\n\n }\n\n \n\n for (int i = 0; i < n2; i++) {\n\n for (int j = 0; j < n2; j++) {\n\n assert(result2[i][j] == expected2[i][j]);\n\n }\n\n }\n\n \n\n for (int i = 0; i < n7; i++) {\n\n for (int j = 0; j < n7; j++) {\n\n assert(result7[i][j] == expected7[i][j]);\n\n }\n\n }\n\n \n\n for (int i = 0; i < n1; i++) free(result1[i]);\n\n free(result1);\n\n for (int i = 0; i < n2; i++) free(result2[i]);\n\n free(result2);\n\n for (int i = 0; i < n7; i++) free(result7[i]);\n\n free(result7);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x48,%rsp\nmov %edi,-0x44(%rbp)\ncmpl $0x0,-0x44(%rbp)\njg 11e9 \nmov $0x0,%eax\njmpq 139e \nmov -0x44(%rbp),%eax\ncltq\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,-0x18(%rbp)\nmovl $0x0,-0x40(%rbp)\njmp 1236 \nmov -0x44(%rbp),%eax\ncltq\nmov -0x40(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x18(%rbp),%rdx\nlea (%rcx,%rdx,1),%rbx\nmov $0x4,%esi\nmov %rax,%rdi\ncallq 10c0 \nmov %rax,(%rbx)\naddl $0x1,-0x40(%rbp)\nmov -0x40(%rbp),%eax\ncmp -0x44(%rbp),%eax\njl 1207 \nmovl $0x0,-0x3c(%rbp)\nmov -0x44(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0x38(%rbp)\nmovl $0x0,-0x34(%rbp)\nmov -0x44(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0x30(%rbp)\nmovl $0x1,-0x2c(%rbp)\nmov -0x44(%rbp),%eax\nimul %eax,%eax\ncmp %eax,-0x2c(%rbp)\njg 1399 \nmov -0x34(%rbp),%eax\nmov %eax,-0x28(%rbp)\njmp 12b0 \nmov -0x2c(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x2c(%rbp)\nmov -0x3c(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rdx),%rdx\nmov -0x28(%rbp),%ecx\nmovslq %ecx,%rcx\nshl $0x2,%rcx\nadd %rcx,%rdx\nmov %eax,(%rdx)\naddl $0x1,-0x28(%rbp)\nmov -0x28(%rbp),%eax\ncmp -0x30(%rbp),%eax\njle 127c \naddl $0x1,-0x3c(%rbp)\nmov -0x3c(%rbp),%eax\nmov %eax,-0x24(%rbp)\njmp 12f8 \nmov -0x2c(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x2c(%rbp)\nmov -0x24(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rdx),%rdx\nmov -0x30(%rbp),%ecx\nmovslq %ecx,%rcx\nshl $0x2,%rcx\nadd %rcx,%rdx\nmov %eax,(%rdx)\naddl $0x1,-0x24(%rbp)\nmov -0x24(%rbp),%eax\ncmp -0x38(%rbp),%eax\njle 12c4 \nsubl $0x1,-0x30(%rbp)\nmov -0x30(%rbp),%eax\nmov %eax,-0x20(%rbp)\njmp 1340 \nmov -0x2c(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x2c(%rbp)\nmov -0x38(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rdx),%rdx\nmov -0x20(%rbp),%ecx\nmovslq %ecx,%rcx\nshl $0x2,%rcx\nadd %rcx,%rdx\nmov %eax,(%rdx)\nsubl $0x1,-0x20(%rbp)\nmov -0x20(%rbp),%eax\ncmp -0x34(%rbp),%eax\njge 130c \nsubl $0x1,-0x38(%rbp)\nmov -0x38(%rbp),%eax\nmov %eax,-0x1c(%rbp)\njmp 1388 \nmov -0x2c(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x2c(%rbp)\nmov -0x1c(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rdx),%rdx\nmov -0x34(%rbp),%ecx\nmovslq %ecx,%rcx\nshl $0x2,%rcx\nadd %rcx,%rdx\nmov %eax,(%rdx)\nsubl $0x1,-0x1c(%rbp)\nmov -0x1c(%rbp),%eax\ncmp -0x3c(%rbp),%eax\njge 1354 \naddl $0x1,-0x34(%rbp)\njmpq 1265 \nmov -0x18(%rbp),%rax\nadd $0x48,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 48h\nmov [rbp+var_44], edi\ncmp [rbp+var_44], 0\njg short loc_11E9\nmov eax, 0\njmp loc_139E\nloc_11E9:\nmov eax, [rbp+var_44]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_40], 0\njmp short loc_1236\nloc_1207:\nmov eax, [rbp+var_44]\ncdqe\nmov edx, [rbp+var_40]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nlea rbx, [rcx+rdx]\nmov esi, 4; size\nmov rdi, rax; nmemb\ncall _calloc\nmov [rbx], rax\nadd [rbp+var_40], 1\nloc_1236:\nmov eax, [rbp+var_40]\ncmp eax, [rbp+var_44]\njl short loc_1207\nmov [rbp+var_3C], 0\nmov eax, [rbp+var_44]\nsub eax, 1\nmov [rbp+var_38], eax\nmov [rbp+var_34], 0\nmov eax, [rbp+var_44]\nsub eax, 1\nmov [rbp+var_30], eax\nmov [rbp+var_2C], 1\nloc_1265:\nmov eax, [rbp+var_44]\nimul eax, eax\ncmp [rbp+var_2C], eax\njg loc_1399\nmov eax, [rbp+var_34]\nmov [rbp+var_28], eax\njmp short loc_12B0\nloc_127C:\nmov eax, [rbp+var_2C]\nlea edx, [rax+1]\nmov [rbp+var_2C], edx\nmov edx, [rbp+var_3C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov rdx, [rdx]\nmov ecx, [rbp+var_28]\nmovsxd rcx, ecx\nshl rcx, 2\nadd rdx, rcx\nmov [rdx], eax\nadd [rbp+var_28], 1\nloc_12B0:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_30]\njle short loc_127C\nadd [rbp+var_3C], 1\nmov eax, [rbp+var_3C]\nmov [rbp+var_24], eax\njmp short loc_12F8\nloc_12C4:\nmov eax, [rbp+var_2C]\nlea edx, [rax+1]\nmov [rbp+var_2C], edx\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov rdx, [rdx]\nmov ecx, [rbp+var_30]\nmovsxd rcx, ecx\nshl rcx, 2\nadd rdx, rcx\nmov [rdx], eax\nadd [rbp+var_24], 1\nloc_12F8:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_38]\njle short loc_12C4\nsub [rbp+var_30], 1\nmov eax, [rbp+var_30]\nmov [rbp+var_20], eax\njmp short loc_1340\nloc_130C:\nmov eax, [rbp+var_2C]\nlea edx, [rax+1]\nmov [rbp+var_2C], edx\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov rdx, [rdx]\nmov ecx, [rbp+var_20]\nmovsxd rcx, ecx\nshl rcx, 2\nadd rdx, rcx\nmov [rdx], eax\nsub [rbp+var_20], 1\nloc_1340:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_34]\njge short loc_130C\nsub [rbp+var_38], 1\nmov eax, [rbp+var_38]\nmov [rbp+var_1C], eax\njmp short loc_1388\nloc_1354:\nmov eax, [rbp+var_2C]\nlea edx, [rax+1]\nmov [rbp+var_2C], edx\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov rdx, [rdx]\nmov ecx, [rbp+var_34]\nmovsxd rcx, ecx\nshl rcx, 2\nadd rdx, rcx\nmov [rdx], eax\nsub [rbp+var_1C], 1\nloc_1388:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_3C]\njge short loc_1354\nadd [rbp+var_34], 1\njmp loc_1265\nloc_1399:\nnop\nmov rax, [rbp+var_18]\nloc_139E:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(int a1)\n{\n int v2; // eax\n int v3; // eax\n int v4; // eax\n int v5; // eax\n int i; // [rsp+10h] [rbp-40h]\n int v7; // [rsp+14h] [rbp-3Ch]\n int v8; // [rsp+18h] [rbp-38h]\n int v9; // [rsp+1Ch] [rbp-34h]\n int v10; // [rsp+20h] [rbp-30h]\n int v11; // [rsp+24h] [rbp-2Ch]\n int j; // [rsp+28h] [rbp-28h]\n int k; // [rsp+2Ch] [rbp-24h]\n int m; // [rsp+30h] [rbp-20h]\n int n; // [rsp+34h] [rbp-1Ch]\n _QWORD *v16; // [rsp+38h] [rbp-18h]\n\n if ( a1 <= 0 )\n return 0LL;\n v16 = malloc(8LL * a1);\n for ( i = 0; i < a1; ++i )\n v16[i] = calloc(a1, 4uLL);\n v7 = 0;\n v8 = a1 - 1;\n v9 = 0;\n v10 = a1 - 1;\n v11 = 1;\n while ( v11 <= a1 * a1 )\n {\n for ( j = v9; j <= v10; ++j )\n {\n v2 = v11++;\n *(_DWORD *)(4LL * j + v16[v7]) = v2;\n }\n for ( k = ++v7; k <= v8; ++k )\n {\n v3 = v11++;\n *(_DWORD *)(4LL * v10 + v16[k]) = v3;\n }\n for ( m = --v10; m >= v9; --m )\n {\n v4 = v11++;\n *(_DWORD *)(4LL * m + v16[v8]) = v4;\n }\n for ( n = --v8; n >= v7; --n )\n {\n v5 = v11++;\n *(_DWORD *)(4LL * v9 + v16[n]) = v5;\n }\n ++v9;\n }\n return v16;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 48h\nmov [rbp+var_44], edi\ncmp [rbp+var_44], 0\njg short loc_11E9\nmov eax, 0\njmp loc_139E\nloc_11E9:\nmov eax, [rbp+var_44]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_40], 0\njmp short loc_1236\nloc_1207:\nmov eax, [rbp+var_44]\ncdqe\nmov edx, [rbp+var_40]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nlea rbx, [rcx+rdx]\nmov esi, 4; size\nmov rdi, rax; nmemb\ncall _calloc\nmov [rbx], rax\nadd [rbp+var_40], 1\nloc_1236:\nmov eax, [rbp+var_40]\ncmp eax, [rbp+var_44]\njl short loc_1207\nmov [rbp+var_3C], 0\nmov eax, [rbp+var_44]\nsub eax, 1\nmov [rbp+var_38], eax\nmov [rbp+var_34], 0\nmov eax, [rbp+var_44]\nsub eax, 1\nmov [rbp+var_30], eax\nmov [rbp+var_2C], 1\nloc_1265:\nmov eax, [rbp+var_44]\nimul eax, eax\ncmp [rbp+var_2C], eax\njg loc_1399\nmov eax, [rbp+var_34]\nmov [rbp+var_28], eax\njmp short loc_12B0\nloc_127C:\nmov eax, [rbp+var_2C]\nlea edx, [rax+1]\nmov [rbp+var_2C], edx\nmov edx, [rbp+var_3C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov rdx, [rdx]\nmov ecx, [rbp+var_28]\nmovsxd rcx, ecx\nshl rcx, 2\nadd rdx, rcx\nmov [rdx], eax\nadd [rbp+var_28], 1\nloc_12B0:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_30]\njle short loc_127C\nadd [rbp+var_3C], 1\nmov eax, [rbp+var_3C]\nmov [rbp+var_24], eax\njmp short loc_12F8\nloc_12C4:\nmov eax, [rbp+var_2C]\nlea edx, [rax+1]\nmov [rbp+var_2C], edx\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov rdx, [rdx]\nmov ecx, [rbp+var_30]\nmovsxd rcx, ecx\nshl rcx, 2\nadd rdx, rcx\nmov [rdx], eax\nadd [rbp+var_24], 1\nloc_12F8:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_38]\njle short loc_12C4\nsub [rbp+var_30], 1\nmov eax, [rbp+var_30]\nmov [rbp+var_20], eax\njmp short loc_1340\nloc_130C:\nmov eax, [rbp+var_2C]\nlea edx, [rax+1]\nmov [rbp+var_2C], edx\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov rdx, [rdx]\nmov ecx, [rbp+var_20]\nmovsxd rcx, ecx\nshl rcx, 2\nadd rdx, rcx\nmov [rdx], eax\nsub [rbp+var_20], 1\nloc_1340:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_34]\njge short loc_130C\nsub [rbp+var_38], 1\nmov eax, [rbp+var_38]\nmov [rbp+var_1C], eax\njmp short loc_1388\nloc_1354:\nmov eax, [rbp+var_2C]\nlea edx, [rax+1]\nmov [rbp+var_2C], edx\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov rdx, [rdx]\nmov ecx, [rbp+var_34]\nmovsxd rcx, ecx\nshl rcx, 2\nadd rdx, rcx\nmov [rdx], eax\nsub [rbp+var_1C], 1\nloc_1388:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_3C]\njge short loc_1354\nadd [rbp+var_34], 1\njmp loc_1265\nloc_1399:\nnop\nmov rax, [rbp+var_18]\nloc_139E:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11C9(int a1)\n{\n int v2; // eax\n int v3; // eax\n int v4; // eax\n int v5; // eax\n int i; // [rsp+10h] [rbp-40h]\n int v7; // [rsp+14h] [rbp-3Ch]\n int v8; // [rsp+18h] [rbp-38h]\n int v9; // [rsp+1Ch] [rbp-34h]\n int v10; // [rsp+20h] [rbp-30h]\n int v11; // [rsp+24h] [rbp-2Ch]\n int j; // [rsp+28h] [rbp-28h]\n int k; // [rsp+2Ch] [rbp-24h]\n int m; // [rsp+30h] [rbp-20h]\n int n; // [rsp+34h] [rbp-1Ch]\n _QWORD *v16; // [rsp+38h] [rbp-18h]\n\n if ( a1 <= 0 )\n return 0LL;\n v16 = malloc(8LL * a1);\n for ( i = 0; i < a1; ++i )\n v16[i] = calloc(a1, 4uLL);\n v7 = 0;\n v8 = a1 - 1;\n v9 = 0;\n v10 = a1 - 1;\n v11 = 1;\n while ( v11 <= a1 * a1 )\n {\n for ( j = v9; j <= v10; ++j )\n {\n v2 = v11++;\n *(_DWORD *)(4LL * j + v16[v7]) = v2;\n }\n for ( k = ++v7; k <= v8; ++k )\n {\n v3 = v11++;\n *(_DWORD *)(4LL * v10 + v16[k]) = v3;\n }\n for ( m = --v10; m >= v9; --m )\n {\n v4 = v11++;\n *(_DWORD *)(4LL * m + v16[v8]) = v4;\n }\n for ( n = --v8; n >= v7; --n )\n {\n v5 = v11++;\n *(_DWORD *)(4LL * v9 + v16[n]) = v5;\n }\n ++v9;\n }\n return v16;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11C9(int a1) {\n int v2;\n int v3;\n int v4;\n int v5;\n int i;\n int v7;\n int v8;\n int v9;\n int v10;\n int v11;\n int j;\n int k;\n int m;\n int n;\n uint64_t *v16;\n if (a1 <= 0) return 0LL;\n v16 = malloc(8LL * a1);\n for (i = 0; i < a1; ++i) v16[i] = calloc(a1, 4uLL);\n v7 = 0;\n v8 = a1 - 1;\n v9 = 0;\n v10 = a1 - 1;\n v11 = 1;\n while (v11 <= a1 * a1) {\n for (j = v9; j <= v10; ++j) {\n v2 = v11++;\n *(uint32_t *)(4LL * j + v16[v7]) = v2;\n }\n for (k = ++v7; k <= v8; ++k) {\n v3 = v11++;\n *(uint32_t *)(4LL * v10 + v16[k]) = v3;\n }\n for (m = --v10; m >= v9; --m) {\n v4 = v11++;\n *(uint32_t *)(4LL * m + v16[v8]) = v4;\n }\n for (n = --v8; n >= v7; --n) {\n v5 = v11++;\n *(uint32_t *)(4LL * v9 + v16[n]) = v5;\n }\n ++v9;\n }\n return v16;\n}", + "ida_pseudo_norm": "uint64_t *func0(int a1) {\n int v2;\n int v3;\n int v4;\n int v5;\n int i;\n int v7;\n int v8;\n int v9;\n int v10;\n int v11;\n int j;\n int k;\n int m;\n int n;\n uint64_t *v16;\n if (a1 <= 0) return 0LL;\n v16 = malloc(8LL * a1);\n for (i = 0; i < a1; ++i) v16[i] = calloc(a1, 4uLL);\n v7 = 0;\n v8 = a1 - 1;\n v9 = 0;\n v10 = a1 - 1;\n v11 = 1;\n while (v11 <= a1 * a1) {\n for (j = v9; j <= v10; ++j) {\n v2 = v11++;\n *(uint32_t *)(4LL * j + v16[v7]) = v2;\n }\n for (k = ++v7; k <= v8; ++k) {\n v3 = v11++;\n *(uint32_t *)(4LL * v10 + v16[k]) = v3;\n }\n for (m = --v10; m >= v9; --m) {\n v4 = v11++;\n *(uint32_t *)(4LL * m + v16[v8]) = v4;\n }\n for (n = --v8; n >= v7; --n) {\n v5 = v11++;\n *(uint32_t *)(4LL * v9 + v16[n]) = v5;\n }\n ++v9;\n }\n return v16;\n}" + }, + { + "index": 834, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int **func0(int n) {\n if (n <= 0) return NULL;\n int **matrix = (int **)malloc(n * sizeof(int *));\n for (int i = 0; i < n; i++) {\n matrix[i] = (int *)calloc(n, sizeof(int));\n }\n int row_st = 0, row_ed = n - 1;\n int col_st = 0, col_ed = n - 1;\n int current = 1;\n while (1) {\n if (current > n * n) break;\n for (int c = col_st; c <= col_ed; c++) {\n matrix[row_st][c] = current++;\n }\n row_st++;\n for (int r = row_st; r <= row_ed; r++) {\n matrix[r][col_ed] = current++;\n }\n col_ed--;\n for (int c = col_ed; c >= col_st; c--) {\n matrix[row_ed][c] = current++;\n }\n row_ed--;\n for (int r = row_ed; r >= row_st; r--) {\n matrix[r][col_st] = current++;\n }\n col_st++;\n }\n return matrix;\n}", + "test": "int main() {\n\n int n1 = 3, n2 = 2, n7 = 7;\n\n \n\n int expected1[3][3] = {{1, 2, 3}, {8, 9, 4}, {7, 6, 5}};\n\n int expected2[2][2] = {{1,2}, {4,3}};\n\n int expected7[7][7] = {{1, 2, 3, 4, 5, 6, 7}, {24, 25, 26, 27, 28, 29, 8}, {23, 40, 41, 42, 43, 30, 9}, {22, 39, 48, 49, 44, 31, 10}, {21, 38, 47, 46, 45, 32, 11}, {20, 37, 36, 35, 34, 33, 12}, {19, 18, 17, 16, 15, 14, 13}};\n\n \n\n int **result1 = func0(n1);\n\n int **result2 = func0(n2);\n\n int **result7 = func0(n7);\n\n \n\n for (int i = 0; i < n1; i++) {\n\n for (int j = 0; j < n1; j++) {\n\n assert(result1[i][j] == expected1[i][j]);\n\n }\n\n }\n\n \n\n for (int i = 0; i < n2; i++) {\n\n for (int j = 0; j < n2; j++) {\n\n assert(result2[i][j] == expected2[i][j]);\n\n }\n\n }\n\n \n\n for (int i = 0; i < n7; i++) {\n\n for (int j = 0; j < n7; j++) {\n\n assert(result7[i][j] == expected7[i][j]);\n\n }\n\n }\n\n \n\n for (int i = 0; i < n1; i++) free(result1[i]);\n\n free(result1);\n\n for (int i = 0; i < n2; i++) free(result2[i]);\n\n free(result2);\n\n for (int i = 0; i < n7; i++) free(result7[i]);\n\n free(result7);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov $0x0,%ebp\ntest %edi,%edi\njle 1363 \nmov %edi,%r14d\nmovslq %edi,%r13\nlea 0x0(,%r13,8),%rax\nmov %rax,0x8(%rsp)\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,%rbp\nmov %rax,%rbx\nlea -0x1(%r14),%eax\nlea 0x8(%rbp,%rax,8),%r15\nmov %rbp,%r12\nmov $0x4,%esi\nmov %r13,%rdi\ncallq 10c0 \nmov %rax,(%r12)\nadd $0x8,%r12\ncmp %r15,%r12\njne 1215 \nlea -0x1(%r14),%r10d\nmov %r14d,%r15d\nimul %r14d,%r15d\nmovslq %r10d,%r14\nmov %r10d,%r13d\nmov 0x8(%rsp),%rax\nlea -0x8(%rbp,%rax,1),%r9\nmov $0x0,%r12d\nmov $0x1,%eax\nmov $0x0,%edi\njmpq 1324 \nadd $0x1,%edi\ncmp %r10d,%edi\njg 12a5 \nlea 0x0(,%r14,4),%r11\nmovslq %edi,%rdx\nlea 0x0(%rbp,%rdx,8),%rdx\nmov %r10d,%r8d\nsub %r12d,%r8d\nadd %eax,%r8d\nmov %edi,%esi\nmov %eax,0x8(%rsp)\nmov %eax,%edi\nadd $0x1,%eax\nmov (%rdx),%rcx\nmov %edi,(%rcx,%r11,1)\nadd $0x8,%rdx\ncmp %r8d,%eax\njne 1286 \nmov %esi,%edi\nmov 0x8(%rsp),%ecx\nlea (%rcx,%r13,1),%eax\nsub $0x1,%r10d\ncmp %r12d,%r10d\njl 12d9 \nmovslq %r10d,%rdx\nshl $0x2,%rdx\nmov %eax,%r11d\nmov %r14d,%r8d\nsub %r12d,%r8d\nadd %eax,%r8d\nmov %eax,%esi\nadd $0x1,%eax\nmov (%r9),%rcx\nmov %esi,(%rcx,%rdx,1)\nsub $0x4,%rdx\ncmp %r8d,%eax\njne 12c1 \nlea (%r11,%r13,1),%eax\ncmp %r10d,%edi\njg 130b \nlea 0x0(,%r12,4),%rsi\nmovslq %r10d,%rdx\nmov %eax,%r8d\nlea -0x1(%rax,%r14,1),%r11d\nmov 0x0(%rbp,%rdx,8),%rax\nmov %r11d,%ecx\nsub %edx,%ecx\nmov %ecx,(%rax,%rsi,1)\nsub $0x1,%rdx\ncmp %edx,%edi\njle 12f1 \nlea -0x1(%r8,%r13,1),%eax\nadd $0x1,%r12\nsub $0x1,%r14\nsub $0x2,%r13d\nsub $0x8,%r9\nadd $0x8,%rbx\ncmp %eax,%r15d\njl 1363 \ncmp %r10d,%edi\njg 125f \nlea 0x0(,%r12,4),%rdx\nmov %r13d,%ecx\nlea 0x1(%r12,%rcx,1),%r11\nshl $0x2,%r11\nmov %eax,%ecx\nmov %ecx,%r8d\nadd $0x1,%ecx\nmov (%rbx),%rsi\nmov %r8d,(%rsi,%rdx,1)\nadd $0x4,%rdx\ncmp %r11,%rdx\njne 1343 \nlea 0x1(%rax,%r13,1),%eax\njmpq 125f \nmov %rbp,%rax\nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov ebx, 0\ntest edi, edi\njle loc_131C\nmov r12d, edi\nmovsxd r14, edi\nlea r13, ds:0[r14*8]\nmov rdi, r13; size\ncall _malloc\nmov rbx, rax\nmov rbp, rax\nadd r13, rax\nloc_1207:\nmov esi, 4; size\nmov rdi, r14; nmemb\ncall _calloc\nmov [rbp+0], rax\nadd rbp, 8\ncmp rbp, r13\njnz short loc_1207\nlea r9d, [r12-1]\nimul r12d, r12d\nmovsxd r11, r9d\nmov r10d, r9d\nmov r8d, 0\nmov eax, 1\nmov ebp, 0\nmov edi, 0\nloc_1245:\ncmp edi, r9d\njg short loc_126F\nmov rdx, r8\nadd rdx, [rbx+r8*2]\nmov r13d, eax\nlea esi, [r9+rax+1]\nsub esi, edi\nloc_125B:\nmov ecx, eax\nadd eax, 1\nmov [rdx], ecx\nadd rdx, 4\ncmp eax, esi\njnz short loc_125B\nlea eax, [r13+r10+1]\nloc_126F:\nadd edi, 1\ncmp edi, r9d\njg short loc_12AB\nlea r14, ds:0[r11*4]\nmovsxd rdx, edi\nlea rdx, [rbx+rdx*8]\nmov r15d, eax\nmov r13d, r9d\nsub r13d, ebp\nadd r13d, eax\nloc_1292:\nmov esi, eax\nadd eax, 1\nmov rcx, [rdx]\nmov [rcx+r14], esi\nadd rdx, 8\ncmp eax, r13d\njnz short loc_1292\nlea eax, [r15+r10]\nloc_12AB:\nsub r9d, 1\ncmp r9d, ebp\njl short loc_12DD\nmovsxd rdx, r9d\nmov rcx, [rbx+r11*8]\nlea rdx, [rcx+rdx*4]\nmov r13d, eax\nmov esi, r11d\nsub esi, ebp\nadd esi, eax\nloc_12C9:\nmov ecx, eax\nadd eax, 1\nmov [rdx], ecx\nsub rdx, 4\ncmp eax, esi\njnz short loc_12C9\nlea eax, [r13+r10+0]\nloc_12DD:\ncmp edi, r9d\njg short loc_1304\nmovsxd rdx, r9d\nlea r13d, [rax+r11-1]\nloc_12EA:\nmov rcx, [rbx+rdx*8]\nmov esi, r13d\nsub esi, edx\nmov [rcx+r8], esi\nsub rdx, 1\ncmp edi, edx\njle short loc_12EA\nlea eax, [rax+r10-1]\nloc_1304:\nadd ebp, 1\nsub r11, 1\nsub r10d, 2\nadd r8, 4\ncmp r12d, eax\njge loc_1245\nloc_131C:\nmov rax, rbx\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "void **__fastcall func0(int a1)\n{\n void **v1; // rbx\n void **v2; // rbp\n int v3; // r9d\n int v4; // r12d\n __int64 v5; // r11\n int v6; // r10d\n __int64 v7; // r8\n int v8; // eax\n int v9; // ebp\n int v10; // edi\n int *v11; // rdx\n int v12; // r13d\n int v13; // esi\n int v14; // ecx\n void **v15; // rdx\n int v16; // r15d\n int v17; // r13d\n int v18; // esi\n int *v19; // rdx\n int v20; // r13d\n int v21; // esi\n int v22; // ecx\n __int64 v23; // rdx\n\n v1 = 0LL;\n if ( a1 > 0 )\n {\n v1 = (void **)malloc(8LL * a1);\n v2 = v1;\n do\n *v2++ = calloc(a1, 4uLL);\n while ( v2 != &v1[a1] );\n v3 = a1 - 1;\n v4 = a1 * a1;\n v5 = a1 - 1;\n v6 = a1 - 1;\n v7 = 0LL;\n v8 = 1;\n v9 = 0;\n v10 = 0;\n do\n {\n if ( v10 <= v3 )\n {\n v11 = (int *)((char *)v1[v7] + v7 * 4);\n v12 = v8;\n v13 = v3 + v8 + 1 - v10;\n do\n {\n v14 = v8++;\n *v11++ = v14;\n }\n while ( v8 != v13 );\n v8 = v12 + v6 + 1;\n }\n if ( ++v10 <= v3 )\n {\n v15 = &v1[v10];\n v16 = v8;\n v17 = v8 + v3 - v9;\n do\n {\n v18 = v8++;\n *((_DWORD *)*v15++ + v5) = v18;\n }\n while ( v8 != v17 );\n v8 = v16 + v6;\n }\n if ( --v3 >= v9 )\n {\n v19 = (int *)((char *)v1[v5] + 4 * v3);\n v20 = v8;\n v21 = v8 + v5 - v9;\n do\n {\n v22 = v8++;\n *v19-- = v22;\n }\n while ( v8 != v21 );\n v8 = v20 + v6;\n }\n if ( v10 <= v3 )\n {\n v23 = v3;\n do\n {\n *(_DWORD *)((char *)v1[v23] + v7 * 4) = v8 + v5 - 1 - v23;\n --v23;\n }\n while ( v10 <= (int)v23 );\n v8 = v8 + v6 - 1;\n }\n ++v9;\n --v5;\n v6 -= 2;\n ++v7;\n }\n while ( v4 >= v8 );\n }\n return v1;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov ebx, 0\ntest edi, edi\njle loc_131C\nmov r12d, edi\nmovsxd r14, edi\nlea r13, ds:0[r14*8]\nmov rdi, r13; size\ncall _malloc\nmov rbx, rax\nmov rbp, rax\nadd r13, rax\nloc_1207:\nmov esi, 4; size\nmov rdi, r14; nmemb\ncall _calloc\nmov [rbp+0], rax\nadd rbp, 8\ncmp rbp, r13\njnz short loc_1207\nlea r9d, [r12-1]\nimul r12d, r12d\nmovsxd r11, r9d\nmov r10d, r9d\nmov r8d, 0\nmov eax, 1\nmov ebp, 0\nmov edi, 0\nloc_1245:\ncmp edi, r9d\njg short loc_126F\nmov rdx, r8\nadd rdx, [rbx+r8*2]\nmov r13d, eax\nlea esi, [r9+rax+1]\nsub esi, edi\nloc_125B:\nmov ecx, eax\nadd eax, 1\nmov [rdx], ecx\nadd rdx, 4\ncmp eax, esi\njnz short loc_125B\nlea eax, [r13+r10+1]\nloc_126F:\nadd edi, 1\ncmp edi, r9d\njg short loc_12AB\nlea r14, ds:0[r11*4]\nmovsxd rdx, edi\nlea rdx, [rbx+rdx*8]\nmov r15d, eax\nmov r13d, r9d\nsub r13d, ebp\nadd r13d, eax\nloc_1292:\nmov esi, eax\nadd eax, 1\nmov rcx, [rdx]\nmov [rcx+r14], esi\nadd rdx, 8\ncmp eax, r13d\njnz short loc_1292\nlea eax, [r15+r10]\nloc_12AB:\nsub r9d, 1\ncmp r9d, ebp\njl short loc_12DD\nmovsxd rdx, r9d\nmov rcx, [rbx+r11*8]\nlea rdx, [rcx+rdx*4]\nmov r13d, eax\nmov esi, r11d\nsub esi, ebp\nadd esi, eax\nloc_12C9:\nmov ecx, eax\nadd eax, 1\nmov [rdx], ecx\nsub rdx, 4\ncmp eax, esi\njnz short loc_12C9\nlea eax, [r13+r10+0]\nloc_12DD:\ncmp edi, r9d\njg short loc_1304\nmovsxd rdx, r9d\nlea r13d, [rax+r11-1]\nloc_12EA:\nmov rcx, [rbx+rdx*8]\nmov esi, r13d\nsub esi, edx\nmov [rcx+r8], esi\nsub rdx, 1\ncmp edi, edx\njle short loc_12EA\nlea eax, [rax+r10-1]\nloc_1304:\nadd ebp, 1\nsub r11, 1\nsub r10d, 2\nadd r8, 4\ncmp r12d, eax\njge loc_1245\nloc_131C:\nmov rax, rbx\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "void **__fastcall sub_11C9(int a1)\n{\n void **v1; // rbx\n void **v2; // rbp\n int v3; // r9d\n int v4; // r12d\n __int64 v5; // r11\n int v6; // r10d\n __int64 v7; // r8\n int v8; // eax\n int v9; // ebp\n int v10; // edi\n int *v11; // rdx\n int v12; // r13d\n int v13; // esi\n int v14; // ecx\n void **v15; // rdx\n int v16; // r15d\n int v17; // r13d\n int v18; // esi\n int *v19; // rdx\n int v20; // r13d\n int v21; // esi\n int v22; // ecx\n __int64 v23; // rdx\n\n v1 = 0LL;\n if ( a1 > 0 )\n {\n v1 = (void **)malloc(8LL * a1);\n v2 = v1;\n do\n *v2++ = calloc(a1, 4uLL);\n while ( v2 != &v1[a1] );\n v3 = a1 - 1;\n v4 = a1 * a1;\n v5 = a1 - 1;\n v6 = a1 - 1;\n v7 = 0LL;\n v8 = 1;\n v9 = 0;\n v10 = 0;\n do\n {\n if ( v10 <= v3 )\n {\n v11 = (int *)((char *)v1[v7] + v7 * 4);\n v12 = v8;\n v13 = v3 + v8 + 1 - v10;\n do\n {\n v14 = v8++;\n *v11++ = v14;\n }\n while ( v8 != v13 );\n v8 = v12 + v6 + 1;\n }\n if ( ++v10 <= v3 )\n {\n v15 = &v1[v10];\n v16 = v8;\n v17 = v8 + v3 - v9;\n do\n {\n v18 = v8++;\n *((_DWORD *)*v15++ + v5) = v18;\n }\n while ( v8 != v17 );\n v8 = v16 + v6;\n }\n if ( --v3 >= v9 )\n {\n v19 = (int *)((char *)v1[v5] + 4 * v3);\n v20 = v8;\n v21 = v8 + v5 - v9;\n do\n {\n v22 = v8++;\n *v19-- = v22;\n }\n while ( v8 != v21 );\n v8 = v20 + v6;\n }\n if ( v10 <= v3 )\n {\n v23 = v3;\n do\n {\n *(_DWORD *)((char *)v1[v23] + v7 * 4) = v8 + v5 - 1 - v23;\n --v23;\n }\n while ( v10 <= (int)v23 );\n v8 = v8 + v6 - 1;\n }\n ++v9;\n --v5;\n v6 -= 2;\n ++v7;\n }\n while ( v4 >= v8 );\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void **sub_11C9(int a1) {\n void **v1;\n void **v2;\n int v3;\n int v4;\n long long v5;\n int v6;\n long long v7;\n int v8;\n int v9;\n int v10;\n int *v11;\n int v12;\n int v13;\n int v14;\n void **v15;\n int v16;\n int v17;\n int v18;\n int *v19;\n int v20;\n int v21;\n int v22;\n long long v23;\n v1 = 0LL;\n if (a1 > 0) {\n v1 = (void **)malloc(8LL * a1);\n v2 = v1;\n do\n *v2++ = calloc(a1, 4uLL);\n while (v2 != &v1[a1]);\n v3 = a1 - 1;\n v4 = a1 * a1;\n v5 = a1 - 1;\n v6 = a1 - 1;\n v7 = 0LL;\n v8 = 1;\n v9 = 0;\n v10 = 0;\n do {\n if (v10 <= v3) {\n v11 = (int *)((char *)v1[v7] + v7 * 4);\n v12 = v8;\n v13 = v3 + v8 + 1 - v10;\n do {\n v14 = v8++;\n *v11++ = v14;\n } while (v8 != v13);\n v8 = v12 + v6 + 1;\n }\n if (++v10 <= v3) {\n v15 = &v1[v10];\n v16 = v8;\n v17 = v8 + v3 - v9;\n do {\n v18 = v8++;\n *((uint32_t *)*v15++ + v5) = v18;\n } while (v8 != v17);\n v8 = v16 + v6;\n }\n if (--v3 >= v9) {\n v19 = (int *)((char *)v1[v5] + 4 * v3);\n v20 = v8;\n v21 = v8 + v5 - v9;\n do {\n v22 = v8++;\n *v19-- = v22;\n } while (v8 != v21);\n v8 = v20 + v6;\n }\n if (v10 <= v3) {\n v23 = v3;\n do {\n *(uint32_t *)((char *)v1[v23] + v7 * 4) = v8 + v5 - 1 - v23;\n --v23;\n } while (v10 <= (int)v23);\n v8 = v8 + v6 - 1;\n }\n ++v9;\n --v5;\n v6 -= 2;\n ++v7;\n } while (v4 >= v8);\n }\n return v1;\n}", + "ida_pseudo_norm": "void **func0(int a1) {\n void **v1;\n void **v2;\n int v3;\n int v4;\n long long v5;\n int v6;\n long long v7;\n int v8;\n int v9;\n int v10;\n int *v11;\n int v12;\n int v13;\n int v14;\n void **v15;\n int v16;\n int v17;\n int v18;\n int *v19;\n int v20;\n int v21;\n int v22;\n long long v23;\n v1 = 0LL;\n if (a1 > 0) {\n v1 = (void **)malloc(8LL * a1);\n v2 = v1;\n do\n *v2++ = calloc(a1, 4uLL);\n while (v2 != &v1[a1]);\n v3 = a1 - 1;\n v4 = a1 * a1;\n v5 = a1 - 1;\n v6 = a1 - 1;\n v7 = 0LL;\n v8 = 1;\n v9 = 0;\n v10 = 0;\n do {\n if (v10 <= v3) {\n v11 = (int *)((char *)v1[v7] + v7 * 4);\n v12 = v8;\n v13 = v3 + v8 + 1 - v10;\n do {\n v14 = v8++;\n *v11++ = v14;\n } while (v8 != v13);\n v8 = v12 + v6 + 1;\n }\n if (++v10 <= v3) {\n v15 = &v1[v10];\n v16 = v8;\n v17 = v8 + v3 - v9;\n do {\n v18 = v8++;\n *((uint32_t *)*v15++ + v5) = v18;\n } while (v8 != v17);\n v8 = v16 + v6;\n }\n if (--v3 >= v9) {\n v19 = (int *)((char *)v1[v5] + 4 * v3);\n v20 = v8;\n v21 = v8 + v5 - v9;\n do {\n v22 = v8++;\n *v19-- = v22;\n } while (v8 != v21);\n v8 = v20 + v6;\n }\n if (v10 <= v3) {\n v23 = v3;\n do {\n *(uint32_t *)((char *)v1[v23] + v7 * 4) = v8 + v5 - 1 - v23;\n --v23;\n } while (v10 <= (int)v23);\n v8 = v8 + v6 - 1;\n }\n ++v9;\n --v5;\n v6 -= 2;\n ++v7;\n } while (v4 >= v8);\n }\n return v1;\n}" + }, + { + "index": 834, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int **func0(int n) {\n if (n <= 0) return NULL;\n int **matrix = (int **)malloc(n * sizeof(int *));\n for (int i = 0; i < n; i++) {\n matrix[i] = (int *)calloc(n, sizeof(int));\n }\n int row_st = 0, row_ed = n - 1;\n int col_st = 0, col_ed = n - 1;\n int current = 1;\n while (1) {\n if (current > n * n) break;\n for (int c = col_st; c <= col_ed; c++) {\n matrix[row_st][c] = current++;\n }\n row_st++;\n for (int r = row_st; r <= row_ed; r++) {\n matrix[r][col_ed] = current++;\n }\n col_ed--;\n for (int c = col_ed; c >= col_st; c--) {\n matrix[row_ed][c] = current++;\n }\n row_ed--;\n for (int r = row_ed; r >= row_st; r--) {\n matrix[r][col_st] = current++;\n }\n col_st++;\n }\n return matrix;\n}", + "test": "int main() {\n\n int n1 = 3, n2 = 2, n7 = 7;\n\n \n\n int expected1[3][3] = {{1, 2, 3}, {8, 9, 4}, {7, 6, 5}};\n\n int expected2[2][2] = {{1,2}, {4,3}};\n\n int expected7[7][7] = {{1, 2, 3, 4, 5, 6, 7}, {24, 25, 26, 27, 28, 29, 8}, {23, 40, 41, 42, 43, 30, 9}, {22, 39, 48, 49, 44, 31, 10}, {21, 38, 47, 46, 45, 32, 11}, {20, 37, 36, 35, 34, 33, 12}, {19, 18, 17, 16, 15, 14, 13}};\n\n \n\n int **result1 = func0(n1);\n\n int **result2 = func0(n2);\n\n int **result7 = func0(n7);\n\n \n\n for (int i = 0; i < n1; i++) {\n\n for (int j = 0; j < n1; j++) {\n\n assert(result1[i][j] == expected1[i][j]);\n\n }\n\n }\n\n \n\n for (int i = 0; i < n2; i++) {\n\n for (int j = 0; j < n2; j++) {\n\n assert(result2[i][j] == expected2[i][j]);\n\n }\n\n }\n\n \n\n for (int i = 0; i < n7; i++) {\n\n for (int j = 0; j < n7; j++) {\n\n assert(result7[i][j] == expected7[i][j]);\n\n }\n\n }\n\n \n\n for (int i = 0; i < n1; i++) free(result1[i]);\n\n free(result1);\n\n for (int i = 0; i < n2; i++) free(result2[i]);\n\n free(result2);\n\n for (int i = 0; i < n7; i++) free(result7[i]);\n\n free(result7);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\nxor %r12d,%r12d\npush %rbp\npush %rbx\nsub $0x8,%rsp\ntest %edi,%edi\njle 16fd \nmovslq %edi,%r13\nmov %edi,%ebx\nlea 0x0(,%r13,8),%rdi\ncallq 10d0 \nmov %rax,%r12\nmov %rax,%rbp\nlea -0x1(%rbx),%eax\nmov %rax,%r15\nlea 0x8(%r12,%rax,8),%r14\nmov $0x4,%esi\nmov %r13,%rdi\nadd $0x8,%rbp\ncallq 10c0 \nmov %rax,-0x8(%rbp)\ncmp %r14,%rbp\njne 15d0 \nimul %ebx,%ebx\nmovslq %r15d,%r11\nxor %r9d,%r9d\nmov $0x1,%eax\nmov %r11,%r8\nmov %r11d,%r10d\nxor %edi,%edi\ncmp %r8d,%edi\njg 1637 \nmov (%r12,%r9,8),%rdx\nlea 0x1(%rax),%ecx\nmov %eax,%r13d\nlea (%rcx,%r8,1),%ebp\nlea (%rdx,%r9,4),%rdx\nsub %edi,%ebp\njmp 1623 \nnopl 0x0(%rax,%rax,1)\nadd $0x1,%ecx\nmov %eax,%esi\nadd $0x4,%rdx\nmov %ecx,%eax\nmov %esi,-0x4(%rdx)\ncmp %ebp,%ecx\njne 1620 \nlea 0x1(%r13,%r10,1),%eax\nadd $0x1,%edi\ncmp %r8d,%edi\njg 1678 \nmov %r8d,%ebp\nmovslq %edi,%rdx\nlea 0x0(,%r11,4),%r13\nmov %eax,%r14d\nsub %r9d,%ebp\nlea (%r12,%rdx,8),%rdx\nadd %eax,%ebp\nnopl 0x0(%rax)\nmov (%rdx),%rcx\nmov %eax,%esi\nadd $0x1,%eax\nadd $0x8,%rdx\nmov %esi,(%rcx,%r13,1)\ncmp %ebp,%eax\njne 1660 \nlea (%r14,%r10,1),%eax\nsub $0x1,%r8d\ncmp %r9d,%r8d\njl 16b5 \nmov (%r12,%r11,8),%rcx\nmov %r11d,%esi\nmovslq %r8d,%rdx\nmov %eax,%ebp\nsub %r9d,%esi\nlea (%rcx,%rdx,4),%rdx\nadd %eax,%esi\nnopw %cs:0x0(%rax,%rax,1)\nmov %eax,%ecx\nadd $0x1,%eax\nsub $0x4,%rdx\nmov %ecx,0x4(%rdx)\ncmp %esi,%eax\njne 16a0 \nlea 0x0(%rbp,%r10,1),%eax\ncmp %r8d,%edi\njg 16e9 \nlea 0x0(,%r9,4),%r13\nmovslq %r8d,%rdx\nlea -0x1(%rax,%r11,1),%ebp\nnopw 0x0(%rax,%rax,1)\nmov (%r12,%rdx,8),%rcx\nmov %ebp,%esi\nsub %edx,%esi\nsub $0x1,%rdx\nmov %esi,(%rcx,%r13,1)\ncmp %edx,%edi\njle 16d0 \nlea -0x1(%rax,%r10,1),%eax\nadd $0x1,%r9\nsub $0x1,%r11\nsub $0x2,%r10d\ncmp %eax,%ebx\njge 1600 \nadd $0x8,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nxor ebx, ebx\nsub rsp, 8\ntest edi, edi\njle loc_1603\nmovsxd r14, edi\nmov ebp, edi\nlea r13, ds:0[r14*8]\nmov rdi, r13; size\ncall _malloc\nmov rbx, rax\nmov r12, rax\nadd r13, rax\nnop word ptr [rax+rax+00h]\nloc_14D0:\nmov esi, 4; size\nmov rdi, r14; nmemb\nadd r12, 8\ncall _calloc\nmov [r12-8], rax\ncmp r12, r13\njnz short loc_14D0\nlea r8d, [rbp-1]\nxor edi, edi\nxor r9d, r9d\nmov eax, 1\nimul ebp, ebp\nmovsxd r11, r8d\nmov r10d, r8d\nxor esi, esi\nnop dword ptr [rax+00h]\nloc_1508:\ncmp esi, r8d\njg short loc_1542\nmov rdx, [rbx+r9*8]\nlea ecx, [rax+1]\nmov r14d, eax\nlea r13d, [rcx+r8]\nadd rdx, rdi\nsub r13d, esi\njmp short loc_152B\nloc_1528:\nadd ecx, 1\nloc_152B:\nmov r12d, eax\nadd rdx, 4\nmov eax, ecx\nmov [rdx-4], r12d\ncmp ecx, r13d\njnz short loc_1528\nlea eax, [r14+r10+1]\nloc_1542:\nadd esi, 1\ncmp esi, r8d\njg short loc_1582\nmov r13d, r8d\nmovsxd rdx, esi\nlea r14, ds:0[r11*4]\nmov r15d, eax\nsub r13d, r9d\nlea rdx, [rbx+rdx*8]\nadd r13d, eax\nnop dword ptr [rax]\nloc_1568:\nmov rcx, [rdx]\nmov r12d, eax\nadd eax, 1\nadd rdx, 8\nmov [rcx+r14], r12d\ncmp eax, r13d\njnz short loc_1568\nlea eax, [r15+r10]\nloc_1582:\nsub r8d, 1\ncmp r8d, r9d\njl short loc_15BE\nmov rcx, [rbx+r11*8]\nmov r12d, r11d\nmovsxd rdx, r8d\nmov r13d, eax\nsub r12d, r9d\nlea rdx, [rcx+rdx*4]\nadd r12d, eax\nnop word ptr [rax+rax+00h]\nloc_15A8:\nmov ecx, eax\nadd eax, 1\nsub rdx, 4\nmov [rdx+4], ecx\ncmp eax, r12d\njnz short loc_15A8\nlea eax, [r13+r10+0]\nloc_15BE:\ncmp esi, r8d\njg short loc_15EB\nmovsxd rdx, r8d\nlea r13d, [rax+r11-1]\nnop dword ptr [rax+rax+00h]\nloc_15D0:\nmov rcx, [rbx+rdx*8]\nmov r12d, r13d\nsub r12d, edx\nsub rdx, 1\nmov [rcx+rdi], r12d\ncmp esi, edx\njle short loc_15D0\nlea eax, [rax+r10-1]\nloc_15EB:\nadd r9, 1\nsub r11, 1\nsub r10d, 2\nadd rdi, 4\ncmp ebp, eax\njge loc_1508\nloc_1603:\nadd rsp, 8\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(int a1)\n{\n _QWORD *v1; // rbx\n _QWORD *v3; // r12\n int v4; // r8d\n __int64 v5; // rdi\n __int64 v6; // r9\n int v7; // eax\n int v8; // ebp\n __int64 v9; // r11\n int v10; // r10d\n int v11; // esi\n int v12; // ecx\n int v13; // r14d\n __int64 v14; // rdx\n int v15; // r13d\n int v16; // r12d\n int v17; // r15d\n __int64 *v18; // rdx\n int v19; // r13d\n __int64 v20; // rcx\n int v21; // r12d\n int v22; // r13d\n __int64 v23; // rdx\n int v24; // r12d\n int v25; // ecx\n __int64 v26; // rdx\n __int64 v27; // rcx\n int v28; // r12d\n\n v1 = 0LL;\n if ( a1 > 0 )\n {\n v1 = malloc(8LL * a1);\n v3 = v1;\n do\n *v3++ = calloc(a1, 4uLL);\n while ( v3 != &v1[a1] );\n v4 = a1 - 1;\n v5 = 0LL;\n v6 = 0LL;\n v7 = 1;\n v8 = a1 * a1;\n v9 = v4;\n v10 = v4;\n v11 = 0;\n do\n {\n if ( v11 <= v4 )\n {\n v12 = v7 + 1;\n v13 = v7;\n v14 = v5 + v1[v6];\n v15 = v7 + 1 + v4 - v11;\n while ( 1 )\n {\n v16 = v7;\n v14 += 4LL;\n v7 = v12;\n *(_DWORD *)(v14 - 4) = v16;\n if ( v12 == v15 )\n break;\n ++v12;\n }\n v7 = v13 + v10 + 1;\n }\n if ( ++v11 <= v4 )\n {\n v17 = v7;\n v18 = &v1[v11];\n v19 = v7 + v4 - v6;\n do\n {\n v20 = *v18;\n v21 = v7++;\n ++v18;\n *(_DWORD *)(v20 + 4 * v9) = v21;\n }\n while ( v7 != v19 );\n v7 = v17 + v10;\n }\n if ( --v4 >= (int)v6 )\n {\n v22 = v7;\n v23 = v1[v9] + 4LL * v4;\n v24 = v7 + v9 - v6;\n do\n {\n v25 = v7++;\n v23 -= 4LL;\n *(_DWORD *)(v23 + 4) = v25;\n }\n while ( v7 != v24 );\n v7 = v22 + v10;\n }\n if ( v11 <= v4 )\n {\n v26 = v4;\n do\n {\n v27 = v1[v26];\n v28 = v7 + v9 - 1 - v26--;\n *(_DWORD *)(v27 + v5) = v28;\n }\n while ( v11 <= (int)v26 );\n v7 = v7 + v10 - 1;\n }\n ++v6;\n --v9;\n v10 -= 2;\n v5 += 4LL;\n }\n while ( v8 >= v7 );\n }\n return v1;\n}", + "ida_strip_asm": "sub_1490:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nxor ebx, ebx\nsub rsp, 8\ntest edi, edi\njle loc_1603\nmovsxd r14, edi\nmov ebp, edi\nlea r13, ds:0[r14*8]\nmov rdi, r13; size\ncall _malloc\nmov rbx, rax\nmov r12, rax\nadd r13, rax\nnop word ptr [rax+rax+00h]\nloc_14D0:\nmov esi, 4; size\nmov rdi, r14; nmemb\nadd r12, 8\ncall _calloc\nmov [r12-8], rax\ncmp r12, r13\njnz short loc_14D0\nlea r8d, [rbp-1]\nxor edi, edi\nxor r9d, r9d\nmov eax, 1\nimul ebp, ebp\nmovsxd r11, r8d\nmov r10d, r8d\nxor esi, esi\nnop dword ptr [rax+00h]\nloc_1508:\ncmp esi, r8d\njg short loc_1542\nmov rdx, [rbx+r9*8]\nlea ecx, [rax+1]\nmov r14d, eax\nlea r13d, [rcx+r8]\nadd rdx, rdi\nsub r13d, esi\njmp short loc_152B\nloc_1528:\nadd ecx, 1\nloc_152B:\nmov r12d, eax\nadd rdx, 4\nmov eax, ecx\nmov [rdx-4], r12d\ncmp ecx, r13d\njnz short loc_1528\nlea eax, [r14+r10+1]\nloc_1542:\nadd esi, 1\ncmp esi, r8d\njg short loc_1582\nmov r13d, r8d\nmovsxd rdx, esi\nlea r14, ds:0[r11*4]\nmov r15d, eax\nsub r13d, r9d\nlea rdx, [rbx+rdx*8]\nadd r13d, eax\nnop dword ptr [rax]\nloc_1568:\nmov rcx, [rdx]\nmov r12d, eax\nadd eax, 1\nadd rdx, 8\nmov [rcx+r14], r12d\ncmp eax, r13d\njnz short loc_1568\nlea eax, [r15+r10]\nloc_1582:\nsub r8d, 1\ncmp r8d, r9d\njl short loc_15BE\nmov rcx, [rbx+r11*8]\nmov r12d, r11d\nmovsxd rdx, r8d\nmov r13d, eax\nsub r12d, r9d\nlea rdx, [rcx+rdx*4]\nadd r12d, eax\nnop word ptr [rax+rax+00h]\nloc_15A8:\nmov ecx, eax\nadd eax, 1\nsub rdx, 4\nmov [rdx+4], ecx\ncmp eax, r12d\njnz short loc_15A8\nlea eax, [r13+r10+0]\nloc_15BE:\ncmp esi, r8d\njg short loc_15EB\nmovsxd rdx, r8d\nlea r13d, [rax+r11-1]\nnop dword ptr [rax+rax+00h]\nloc_15D0:\nmov rcx, [rbx+rdx*8]\nmov r12d, r13d\nsub r12d, edx\nsub rdx, 1\nmov [rcx+rdi], r12d\ncmp esi, edx\njle short loc_15D0\nlea eax, [rax+r10-1]\nloc_15EB:\nadd r9, 1\nsub r11, 1\nsub r10d, 2\nadd rdi, 4\ncmp ebp, eax\njge loc_1508\nloc_1603:\nadd rsp, 8\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1490(int a1)\n{\n _QWORD *v1; // rbx\n _QWORD *v3; // r12\n int v4; // r8d\n __int64 v5; // rdi\n __int64 v6; // r9\n int v7; // eax\n int v8; // ebp\n __int64 v9; // r11\n int v10; // r10d\n int v11; // esi\n int v12; // ecx\n int v13; // r14d\n __int64 v14; // rdx\n int v15; // r13d\n int v16; // r12d\n int v17; // r15d\n __int64 *v18; // rdx\n int v19; // r13d\n __int64 v20; // rcx\n int v21; // r12d\n int v22; // r13d\n __int64 v23; // rdx\n int v24; // r12d\n int v25; // ecx\n __int64 v26; // rdx\n __int64 v27; // rcx\n int v28; // r12d\n\n v1 = 0LL;\n if ( a1 > 0 )\n {\n v1 = malloc(8LL * a1);\n v3 = v1;\n do\n *v3++ = calloc(a1, 4uLL);\n while ( v3 != &v1[a1] );\n v4 = a1 - 1;\n v5 = 0LL;\n v6 = 0LL;\n v7 = 1;\n v8 = a1 * a1;\n v9 = v4;\n v10 = v4;\n v11 = 0;\n do\n {\n if ( v11 <= v4 )\n {\n v12 = v7 + 1;\n v13 = v7;\n v14 = v5 + v1[v6];\n v15 = v7 + 1 + v4 - v11;\n while ( 1 )\n {\n v16 = v7;\n v14 += 4LL;\n v7 = v12;\n *(_DWORD *)(v14 - 4) = v16;\n if ( v12 == v15 )\n break;\n ++v12;\n }\n v7 = v13 + v10 + 1;\n }\n if ( ++v11 <= v4 )\n {\n v17 = v7;\n v18 = &v1[v11];\n v19 = v7 + v4 - v6;\n do\n {\n v20 = *v18;\n v21 = v7++;\n ++v18;\n *(_DWORD *)(v20 + 4 * v9) = v21;\n }\n while ( v7 != v19 );\n v7 = v17 + v10;\n }\n if ( --v4 >= (int)v6 )\n {\n v22 = v7;\n v23 = v1[v9] + 4LL * v4;\n v24 = v7 + v9 - v6;\n do\n {\n v25 = v7++;\n v23 -= 4LL;\n *(_DWORD *)(v23 + 4) = v25;\n }\n while ( v7 != v24 );\n v7 = v22 + v10;\n }\n if ( v11 <= v4 )\n {\n v26 = v4;\n do\n {\n v27 = v1[v26];\n v28 = v7 + v9 - 1 - v26--;\n *(_DWORD *)(v27 + v5) = v28;\n }\n while ( v11 <= (int)v26 );\n v7 = v7 + v10 - 1;\n }\n ++v6;\n --v9;\n v10 -= 2;\n v5 += 4LL;\n }\n while ( v8 >= v7 );\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1490(int a1) {\n uint64_t *v1;\n uint64_t *v3;\n int v4;\n long long v5;\n long long v6;\n int v7;\n int v8;\n long long v9;\n int v10;\n int v11;\n int v12;\n int v13;\n long long v14;\n int v15;\n int v16;\n int v17;\n long long *v18;\n int v19;\n long long v20;\n int v21;\n int v22;\n long long v23;\n int v24;\n int v25;\n long long v26;\n long long v27;\n int v28;\n v1 = 0LL;\n if (a1 > 0) {\n v1 = malloc(8LL * a1);\n v3 = v1;\n do\n *v3++ = calloc(a1, 4uLL);\n while (v3 != &v1[a1]);\n v4 = a1 - 1;\n v5 = 0LL;\n v6 = 0LL;\n v7 = 1;\n v8 = a1 * a1;\n v9 = v4;\n v10 = v4;\n v11 = 0;\n do {\n if (v11 <= v4) {\n v12 = v7 + 1;\n v13 = v7;\n v14 = v5 + v1[v6];\n v15 = v7 + 1 + v4 - v11;\n while (1) {\n v16 = v7;\n v14 += 4LL;\n v7 = v12;\n *(uint32_t *)(v14 - 4) = v16;\n if (v12 == v15) break;\n ++v12;\n }\n v7 = v13 + v10 + 1;\n }\n if (++v11 <= v4) {\n v17 = v7;\n v18 = &v1[v11];\n v19 = v7 + v4 - v6;\n do {\n v20 = *v18;\n v21 = v7++;\n ++v18;\n *(uint32_t *)(v20 + 4 * v9) = v21;\n } while (v7 != v19);\n v7 = v17 + v10;\n }\n if (--v4 >= (int)v6) {\n v22 = v7;\n v23 = v1[v9] + 4LL * v4;\n v24 = v7 + v9 - v6;\n do {\n v25 = v7++;\n v23 -= 4LL;\n *(uint32_t *)(v23 + 4) = v25;\n } while (v7 != v24);\n v7 = v22 + v10;\n }\n if (v11 <= v4) {\n v26 = v4;\n do {\n v27 = v1[v26];\n v28 = v7 + v9 - 1 - v26--;\n *(uint32_t *)(v27 + v5) = v28;\n } while (v11 <= (int)v26);\n v7 = v7 + v10 - 1;\n }\n ++v6;\n --v9;\n v10 -= 2;\n v5 += 4LL;\n } while (v8 >= v7);\n }\n return v1;\n}", + "ida_pseudo_norm": "uint64_t *func0(int a1) {\n uint64_t *v1;\n uint64_t *v3;\n int v4;\n long long v5;\n long long v6;\n int v7;\n int v8;\n long long v9;\n int v10;\n int v11;\n int v12;\n int v13;\n long long v14;\n int v15;\n int v16;\n int v17;\n long long *v18;\n int v19;\n long long v20;\n int v21;\n int v22;\n long long v23;\n int v24;\n int v25;\n long long v26;\n long long v27;\n int v28;\n v1 = 0LL;\n if (a1 > 0) {\n v1 = malloc(8LL * a1);\n v3 = v1;\n do\n *v3++ = calloc(a1, 4uLL);\n while (v3 != &v1[a1]);\n v4 = a1 - 1;\n v5 = 0LL;\n v6 = 0LL;\n v7 = 1;\n v8 = a1 * a1;\n v9 = v4;\n v10 = v4;\n v11 = 0;\n do {\n if (v11 <= v4) {\n v12 = v7 + 1;\n v13 = v7;\n v14 = v5 + v1[v6];\n v15 = v7 + 1 + v4 - v11;\n while (1) {\n v16 = v7;\n v14 += 4LL;\n v7 = v12;\n *(uint32_t *)(v14 - 4) = v16;\n if (v12 == v15) break;\n ++v12;\n }\n v7 = v13 + v10 + 1;\n }\n if (++v11 <= v4) {\n v17 = v7;\n v18 = &v1[v11];\n v19 = v7 + v4 - v6;\n do {\n v20 = *v18;\n v21 = v7++;\n ++v18;\n *(uint32_t *)(v20 + 4 * v9) = v21;\n } while (v7 != v19);\n v7 = v17 + v10;\n }\n if (--v4 >= (int)v6) {\n v22 = v7;\n v23 = v1[v9] + 4LL * v4;\n v24 = v7 + v9 - v6;\n do {\n v25 = v7++;\n v23 -= 4LL;\n *(uint32_t *)(v23 + 4) = v25;\n } while (v7 != v24);\n v7 = v22 + v10;\n }\n if (v11 <= v4) {\n v26 = v4;\n do {\n v27 = v1[v26];\n v28 = v7 + v9 - 1 - v26--;\n *(uint32_t *)(v27 + v5) = v28;\n } while (v11 <= (int)v26);\n v7 = v7 + v10 - 1;\n }\n ++v6;\n --v9;\n v10 -= 2;\n v5 += 4LL;\n } while (v8 >= v7);\n }\n return v1;\n}" + }, + { + "index": 834, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int **func0(int n) {\n if (n <= 0) return NULL;\n int **matrix = (int **)malloc(n * sizeof(int *));\n for (int i = 0; i < n; i++) {\n matrix[i] = (int *)calloc(n, sizeof(int));\n }\n int row_st = 0, row_ed = n - 1;\n int col_st = 0, col_ed = n - 1;\n int current = 1;\n while (1) {\n if (current > n * n) break;\n for (int c = col_st; c <= col_ed; c++) {\n matrix[row_st][c] = current++;\n }\n row_st++;\n for (int r = row_st; r <= row_ed; r++) {\n matrix[r][col_ed] = current++;\n }\n col_ed--;\n for (int c = col_ed; c >= col_st; c--) {\n matrix[row_ed][c] = current++;\n }\n row_ed--;\n for (int r = row_ed; r >= row_st; r--) {\n matrix[r][col_st] = current++;\n }\n col_st++;\n }\n return matrix;\n}", + "test": "int main() {\n\n int n1 = 3, n2 = 2, n7 = 7;\n\n \n\n int expected1[3][3] = {{1, 2, 3}, {8, 9, 4}, {7, 6, 5}};\n\n int expected2[2][2] = {{1,2}, {4,3}};\n\n int expected7[7][7] = {{1, 2, 3, 4, 5, 6, 7}, {24, 25, 26, 27, 28, 29, 8}, {23, 40, 41, 42, 43, 30, 9}, {22, 39, 48, 49, 44, 31, 10}, {21, 38, 47, 46, 45, 32, 11}, {20, 37, 36, 35, 34, 33, 12}, {19, 18, 17, 16, 15, 14, 13}};\n\n \n\n int **result1 = func0(n1);\n\n int **result2 = func0(n2);\n\n int **result7 = func0(n7);\n\n \n\n for (int i = 0; i < n1; i++) {\n\n for (int j = 0; j < n1; j++) {\n\n assert(result1[i][j] == expected1[i][j]);\n\n }\n\n }\n\n \n\n for (int i = 0; i < n2; i++) {\n\n for (int j = 0; j < n2; j++) {\n\n assert(result2[i][j] == expected2[i][j]);\n\n }\n\n }\n\n \n\n for (int i = 0; i < n7; i++) {\n\n for (int j = 0; j < n7; j++) {\n\n assert(result7[i][j] == expected7[i][j]);\n\n }\n\n }\n\n \n\n for (int i = 0; i < n1; i++) free(result1[i]);\n\n free(result1);\n\n for (int i = 0; i < n2; i++) free(result2[i]);\n\n free(result2);\n\n for (int i = 0; i < n7; i++) free(result7[i]);\n\n free(result7);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\nxor %r12d,%r12d\npush %rbp\npush %rbx\nsub $0x18,%rsp\ntest %edi,%edi\njle 1782 \nmovslq %edi,%rbx\nmov %edi,%r14d\nlea 0x0(,%rbx,8),%rdi\ncallq 10d0 \nmov %rax,%r12\nmov %rax,%rbp\nlea -0x1(%r14),%eax\nmov %rax,%r15\nlea 0x8(%r12,%rax,8),%r13\nnopw 0x0(%rax,%rax,1)\nmov $0x4,%esi\nmov %rbx,%rdi\nadd $0x8,%rbp\ncallq 10c0 \nmov %rax,-0x8(%rbp)\ncmp %r13,%rbp\njne 1558 \nlea -0x14(,%rbx,4),%rbx\nmovslq %r15d,%r13\nxor %r8d,%r8d\nxor %ebp,%ebp\nmovdqa 0xb36(%rip),%xmm4\nmov %r13,%r11\nmov %r13d,%r10d\nxor %edi,%edi\nimul %r14d,%r14d\nmov %rbx,0x8(%rsp)\nmov $0x1,%eax\nmovdqa 0xb28(%rip),%xmm2\nmovdqa %xmm4,%xmm5\nmovdqa %xmm2,%xmm3\ncmp %r11d,%edi\njg 164b \nmov (%r12,%r8,2),%rsi\nlea 0x1(%r10),%r9d\ncmp $0x2,%r10d\njbe 179e \nmov %r9d,%ecx\nmovd %eax,%xmm6\nlea (%rsi,%r8,1),%rdx\nshr $0x2,%ecx\npshufd $0x0,%xmm6,%xmm0\nshl $0x4,%rcx\npaddd %xmm4,%xmm0\nadd %rdx,%rcx\nnopl 0x0(%rax)\nmovdqa %xmm0,%xmm1\nadd $0x10,%rdx\npaddd %xmm2,%xmm0\nmovups %xmm1,-0x10(%rdx)\ncmp %rcx,%rdx\njne 15f0 \nmov %r9d,%ebx\nand $0xfffffffc,%ebx\nlea (%rax,%rbx,1),%ecx\nlea (%rdi,%rbx,1),%edx\ncmp %ebx,%r9d\nje 1646 \nmovslq %edx,%r9\nlea 0x1(%rcx),%r15d\nmov %ecx,(%rsi,%r9,4)\nlea 0x0(,%r9,4),%rbx\nlea 0x1(%rdx),%r9d\ncmp %r9d,%r11d\njl 1646 \nadd $0x2,%edx\nmov %r15d,0x4(%rsi,%rbx,1)\nadd $0x2,%ecx\ncmp %edx,%r11d\njl 1646 \nmov %ecx,0x8(%rsi,%rbx,1)\nlea 0x1(%rax,%r10,1),%eax\nadd $0x1,%edi\ncmp %r11d,%edi\njg 1688 \nmov %r11d,%r9d\nmovslq %edi,%rdx\nlea 0x0(,%r13,4),%rbx\nmov %eax,%r15d\nsub %ebp,%r9d\nlea (%r12,%rdx,8),%rdx\nadd %eax,%r9d\nxchg %ax,%ax\nmov (%rdx),%rcx\nmov %eax,%esi\nadd $0x1,%eax\nadd $0x8,%rdx\nmov %esi,(%rcx,%rbx,1)\ncmp %r9d,%eax\njne 1670 \nlea (%r15,%r10,1),%eax\nsub $0x1,%r11d\ncmp %ebp,%r11d\njl 173a \nlea -0x1(%r10),%edx\nmov (%r12,%r13,8),%rsi\ncmp $0x2,%edx\njbe 1794 \nmov 0x8(%rsp),%rdx\nmov %r10d,%ecx\nmovd %eax,%xmm7\nshr $0x2,%ecx\npshufd $0x0,%xmm7,%xmm1\nsub %r8,%rdx\nshl $0x4,%rcx\npaddd %xmm5,%xmm1\nadd %rsi,%rdx\nmov %rdx,%rbx\nsub %rcx,%rbx\nmov %rbx,%rcx\nnopl 0x0(%rax)\nmovdqa %xmm1,%xmm0\nsub $0x10,%rdx\npaddd %xmm3,%xmm1\npshufd $0x1b,%xmm0,%xmm0\nmovups %xmm0,0x10(%rdx)\ncmp %rcx,%rdx\njne 16d8 \nmov %r10d,%r9d\nmov %r11d,%edx\nand $0xfffffffc,%r9d\nlea (%rax,%r9,1),%ecx\nsub %r9d,%edx\ncmp %r10d,%r9d\nje 1737 \nmovslq %edx,%r9\nlea 0x1(%rcx),%r15d\nmov %ecx,(%rsi,%r9,4)\nlea 0x0(,%r9,4),%rbx\nlea -0x1(%rdx),%r9d\ncmp %ebp,%r9d\njl 1737 \nsub $0x2,%edx\nmov %r15d,-0x4(%rsi,%rbx,1)\nadd $0x2,%ecx\ncmp %ebp,%edx\njl 1737 \nmov %ecx,-0x8(%rsi,%rbx,1)\nadd %r10d,%eax\ncmp %r11d,%edi\njg 176a \nmovslq %r11d,%rdx\nlea -0x1(%rax,%r13,1),%r9d\nnopw 0x0(%rax,%rax,1)\nmov (%r12,%rdx,8),%rcx\nmov %r9d,%esi\nsub %edx,%esi\nsub $0x1,%rdx\nmov %esi,(%rcx,%r8,1)\ncmp %edx,%edi\njle 1750 \nlea -0x1(%rax,%r10,1),%eax\nadd $0x1,%ebp\nsub $0x1,%r13\nsub $0x2,%r10d\nadd $0x4,%r8\ncmp %eax,%r14d\njge 15b0 \nadd $0x18,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmov %r11d,%edx\nmov %eax,%ecx\njmpq 1708 \nmov %edi,%edx\nmov %eax,%ecx\njmpq 1616 \nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nxor ebx, ebx\nsub rsp, 18h\ntest edi, edi\njle loc_1724\nmovsxd rbp, edi\nmov r14d, edi\nlea r13, ds:0[rbp*8]\nmov rdi, r13; size\ncall _malloc\nmov rbx, rax\nmov r12, rax\nadd r13, rax\nnop dword ptr [rax+rax+00h]\nloc_1500:\nmov esi, 4; size\nmov rdi, rbp; nmemb\nadd r12, 8\ncall _calloc\nmov [r12-8], rax\ncmp r13, r12\njnz short loc_1500\nlea rcx, ds:0FFFFFFFFFFFFFFECh[rbp*4]\nlea r10d, [r14-1]\nxor edi, edi\nxor esi, esi\nimul r14d, r14d\nmov [rsp+48h+var_40], rcx\nmovsxd r13, r10d\nmov r9d, r10d\nmovdqa xmm3, cs:xmmword_20A0\nmovdqa xmm2, cs:xmmword_20B0\nxor r12d, r12d\nmov eax, 1\nnop word ptr [rax+rax+00h]\nloc_1558:\ncmp esi, r10d\njg loc_15EC\nmov r8, [rbx+rdi*2]\nlea edx, [r9+1]\ncmp r9d, 2\njbe loc_1740\nmov r11d, edx\nmovd xmm4, eax\nlea rcx, [r8+rdi]\nshr r11d, 2\npshufd xmm0, xmm4, 0\nshl r11, 4\npaddd xmm0, xmm3\nadd r11, rcx\nnop word ptr [rax+rax+00h]\nloc_1598:\nmovdqa xmm1, xmm0\nadd rcx, 10h\npaddd xmm0, xmm2\nmovups xmmword ptr [rcx-10h], xmm1\ncmp r11, rcx\njnz short loc_1598\ntest dl, 3\njz short loc_15E7\nand edx, 0FFFFFFFCh\nlea ecx, [rax+rdx]\nadd edx, esi\nloc_15BA:\nmovsxd r11, edx\nlea r15d, [rcx+1]\nmov [r8+r11*4], ecx\nlea rbp, ds:0[r11*4]\ncmp r10d, edx\njle short loc_15E7\nadd edx, 2\nmov [r8+rbp+4], r15d\nadd ecx, 2\ncmp r10d, edx\njl short loc_15E7\nmov [r8+rbp+8], ecx\nloc_15E7:\nlea eax, [r9+rax+1]\nloc_15EC:\nadd esi, 1\ncmp esi, r10d\njg short loc_162A\nmov r11d, r10d\nmovsxd rdx, esi\nlea rbp, ds:0[r13*4]\nmov r8d, eax\nsub r11d, r12d\nlea rdx, [rbx+rdx*8]\nadd r11d, eax\nnop\nloc_1610:\nmov rcx, [rdx]\nmov r15d, eax\nadd eax, 1\nadd rdx, 8\nmov [rcx+rbp], r15d\ncmp eax, r11d\njnz short loc_1610\nlea eax, [r9+r8]\nloc_162A:\nsub r10d, 1\ncmp r10d, r12d\njl loc_16D9\nlea edx, [r9-1]\nmov r8, [rbx+r13*8]\ncmp edx, 2\njbe loc_1736\nmov rdx, [rsp+48h+var_40]\nmov r11d, r9d\nmovd xmm5, eax\nshr r11d, 2\npshufd xmm1, xmm5, 0\nsub rdx, rdi\nshl r11, 4\npaddd xmm1, xmm3\nadd rdx, r8\nmov rcx, rdx\nsub rcx, r11\nnop dword ptr [rax+00000000h]\nloc_1678:\nmovdqa xmm0, xmm1\nsub rdx, 10h\npaddd xmm1, xmm2\npshufd xmm0, xmm0, 1Bh\nmovups xmmword ptr [rdx+10h], xmm0\ncmp rcx, rdx\njnz short loc_1678\ntest r9b, 3\njz short loc_16D6\nmov r11d, r9d\nmov edx, r10d\nand r11d, 0FFFFFFFCh\nlea ecx, [rax+r11]\nsub edx, r11d\nloc_16A9:\nmovsxd r11, edx\nlea r15d, [rcx+1]\nmov [r8+r11*4], ecx\nlea rbp, ds:0[r11*4]\ncmp r12d, edx\njge short loc_16D6\nsub edx, 2\nmov [r8+rbp-4], r15d\nadd ecx, 2\ncmp edx, r12d\njl short loc_16D6\nmov [r8+rbp-8], ecx\nloc_16D6:\nadd eax, r9d\nloc_16D9:\ncmp esi, r10d\njg short loc_170B\nmovsxd rdx, r10d\nlea r11d, [rax+r13-1]\nnop word ptr [rax+rax+00000000h]\nloc_16F0:\nmov rcx, [rbx+rdx*8]\nmov r8d, r11d\nsub r8d, edx\nsub rdx, 1\nmov [rcx+rdi], r8d\ncmp esi, edx\njle short loc_16F0\nlea eax, [r9+rax-1]\nloc_170B:\nadd r12d, 1\nsub r13, 1\nsub r9d, 2\nadd rdi, 4\ncmp r14d, eax\njge loc_1558\nloc_1724:\nadd rsp, 18h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1736:\nmov edx, r10d\nmov ecx, eax\njmp loc_16A9\nloc_1740:\nmov edx, esi\nmov ecx, eax\njmp loc_15BA", + "ida_pseudo": "_QWORD *__fastcall func0(int a1)\n{\n _QWORD *v1; // rbx\n __int64 v2; // rbp\n _QWORD *v4; // r12\n signed int v5; // r10d\n unsigned __int64 v6; // rdi\n int v7; // esi\n int v8; // r14d\n __int64 v9; // r13\n unsigned int v10; // r9d\n __m128i si128; // xmm3\n __m128i v12; // xmm2\n signed int v13; // r12d\n signed int v14; // eax\n __int64 v15; // r8\n unsigned int v16; // edx\n __int64 v17; // rcx\n __m128i v18; // xmm0\n __m128i v19; // xmm1\n unsigned int v20; // edx\n signed int v21; // ecx\n int v22; // edx\n __int64 v23; // rbp\n int v24; // ecx\n signed int v25; // r8d\n __int64 *v26; // rdx\n int v27; // r11d\n __int64 v28; // rcx\n signed int v29; // r15d\n __int64 v30; // r8\n __m128i v31; // xmm1\n __m128i *v32; // rdx\n __m128i v33; // xmm0\n signed int v34; // ecx\n signed int v35; // edx\n __int64 v36; // rbp\n int v37; // ecx\n __int64 v38; // rdx\n __int64 v39; // rcx\n int v40; // r8d\n __int64 v42; // [rsp+8h] [rbp-40h]\n\n v1 = 0LL;\n if ( a1 > 0 )\n {\n v2 = a1;\n v1 = malloc(8LL * a1);\n v4 = v1;\n do\n *v4++ = calloc(a1, 4uLL);\n while ( &v1[a1] != v4 );\n v5 = a1 - 1;\n v6 = 0LL;\n v7 = 0;\n v8 = a1 * a1;\n v42 = 4 * v2 - 20;\n v9 = v5;\n v10 = v5;\n si128 = _mm_load_si128((const __m128i *)&xmmword_20A0);\n v12 = _mm_load_si128((const __m128i *)&xmmword_20B0);\n v13 = 0;\n v14 = 1;\n while ( 1 )\n {\n if ( v7 > v5 )\n goto LABEL_15;\n v15 = v1[v6 / 4];\n v16 = v10 + 1;\n if ( v10 <= 2 )\n break;\n v17 = v15 + v6;\n v18 = _mm_add_epi32(_mm_shuffle_epi32(_mm_cvtsi32_si128(v14), 0), si128);\n do\n {\n v19 = v18;\n v17 += 16LL;\n v18 = _mm_add_epi32(v18, v12);\n *(__m128i *)(v17 - 16) = v19;\n }\n while ( v15 + v6 + 16LL * (v16 >> 2) != v17 );\n if ( (v16 & 3) != 0 )\n {\n v20 = v16 & 0xFFFFFFFC;\n v21 = v14 + v20;\n v22 = v7 + v20;\nLABEL_11:\n *(_DWORD *)(v15 + 4LL * v22) = v21;\n v23 = 4LL * v22;\n if ( v5 > v22 )\n {\n *(_DWORD *)(v15 + v23 + 4) = v21 + 1;\n v24 = v21 + 2;\n if ( v5 >= v22 + 2 )\n *(_DWORD *)(v15 + v23 + 8) = v24;\n }\n }\n v14 += v10 + 1;\nLABEL_15:\n if ( ++v7 <= v5 )\n {\n v25 = v14;\n v26 = &v1[v7];\n v27 = v14 + v5 - v13;\n do\n {\n v28 = *v26;\n v29 = v14++;\n ++v26;\n *(_DWORD *)(v28 + 4 * v9) = v29;\n }\n while ( v14 != v27 );\n v14 = v10 + v25;\n }\n if ( --v5 < v13 )\n goto LABEL_29;\n v30 = v1[v9];\n if ( v10 - 1 <= 2 )\n {\n v35 = v5;\n v34 = v14;\n goto LABEL_25;\n }\n v31 = _mm_add_epi32(_mm_shuffle_epi32(_mm_cvtsi32_si128(v14), 0), si128);\n v32 = (__m128i *)(v30 + v42 - v6);\n do\n {\n v33 = v31;\n --v32;\n v31 = _mm_add_epi32(v31, v12);\n v32[1] = _mm_shuffle_epi32(v33, 27);\n }\n while ( (__m128i *)(v30 + v42 - v6 - 16LL * (v10 >> 2)) != v32 );\n if ( (v10 & 3) != 0 )\n {\n v34 = v14 + (v10 & 0xFFFFFFFC);\n v35 = v5 - (v10 & 0xFFFFFFFC);\nLABEL_25:\n *(_DWORD *)(v30 + 4LL * v35) = v34;\n v36 = 4LL * v35;\n if ( v13 < v35 )\n {\n *(_DWORD *)(v30 + v36 - 4) = v34 + 1;\n v37 = v34 + 2;\n if ( v35 - 2 >= v13 )\n *(_DWORD *)(v30 + v36 - 8) = v37;\n }\n }\n v14 += v10;\nLABEL_29:\n if ( v7 <= v5 )\n {\n v38 = v5;\n do\n {\n v39 = v1[v38];\n v40 = v14 + v9 - 1 - v38--;\n *(_DWORD *)(v39 + v6) = v40;\n }\n while ( v7 <= (int)v38 );\n v14 = v10 + v14 - 1;\n }\n ++v13;\n --v9;\n v10 -= 2;\n v6 += 4LL;\n if ( v8 < v14 )\n return v1;\n }\n v22 = v7;\n v21 = v14;\n goto LABEL_11;\n }\n return v1;\n}", + "ida_strip_asm": "sub_14C0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nxor ebx, ebx\nsub rsp, 18h\ntest edi, edi\njle loc_1724\nmovsxd rbp, edi\nmov r14d, edi\nlea r13, ds:0[rbp*8]\nmov rdi, r13; size\ncall _malloc\nmov rbx, rax\nmov r12, rax\nadd r13, rax\nnop dword ptr [rax+rax+00h]\nloc_1500:\nmov esi, 4; size\nmov rdi, rbp; nmemb\nadd r12, 8\ncall _calloc\nmov [r12-8], rax\ncmp r13, r12\njnz short loc_1500\nlea rcx, ds:0FFFFFFFFFFFFFFECh[rbp*4]\nlea r10d, [r14-1]\nxor edi, edi\nxor esi, esi\nimul r14d, r14d\nmov [rsp+48h+var_40], rcx\nmovsxd r13, r10d\nmov r9d, r10d\nmovdqa xmm3, cs:xmmword_20A0\nmovdqa xmm2, cs:xmmword_20B0\nxor r12d, r12d\nmov eax, 1\nnop word ptr [rax+rax+00h]\nloc_1558:\ncmp esi, r10d\njg loc_15EC\nmov r8, [rbx+rdi*2]\nlea edx, [r9+1]\ncmp r9d, 2\njbe loc_1740\nmov r11d, edx\nmovd xmm4, eax\nlea rcx, [r8+rdi]\nshr r11d, 2\npshufd xmm0, xmm4, 0\nshl r11, 4\npaddd xmm0, xmm3\nadd r11, rcx\nnop word ptr [rax+rax+00h]\nloc_1598:\nmovdqa xmm1, xmm0\nadd rcx, 10h\npaddd xmm0, xmm2\nmovups xmmword ptr [rcx-10h], xmm1\ncmp r11, rcx\njnz short loc_1598\ntest dl, 3\njz short loc_15E7\nand edx, 0FFFFFFFCh\nlea ecx, [rax+rdx]\nadd edx, esi\nloc_15BA:\nmovsxd r11, edx\nlea r15d, [rcx+1]\nmov [r8+r11*4], ecx\nlea rbp, ds:0[r11*4]\ncmp r10d, edx\njle short loc_15E7\nadd edx, 2\nmov [r8+rbp+4], r15d\nadd ecx, 2\ncmp r10d, edx\njl short loc_15E7\nmov [r8+rbp+8], ecx\nloc_15E7:\nlea eax, [r9+rax+1]\nloc_15EC:\nadd esi, 1\ncmp esi, r10d\njg short loc_162A\nmov r11d, r10d\nmovsxd rdx, esi\nlea rbp, ds:0[r13*4]\nmov r8d, eax\nsub r11d, r12d\nlea rdx, [rbx+rdx*8]\nadd r11d, eax\nnop\nloc_1610:\nmov rcx, [rdx]\nmov r15d, eax\nadd eax, 1\nadd rdx, 8\nmov [rcx+rbp], r15d\ncmp eax, r11d\njnz short loc_1610\nlea eax, [r9+r8]\nloc_162A:\nsub r10d, 1\ncmp r10d, r12d\njl loc_16D9\nlea edx, [r9-1]\nmov r8, [rbx+r13*8]\ncmp edx, 2\njbe loc_1736\nmov rdx, [rsp+48h+var_40]\nmov r11d, r9d\nmovd xmm5, eax\nshr r11d, 2\npshufd xmm1, xmm5, 0\nsub rdx, rdi\nshl r11, 4\npaddd xmm1, xmm3\nadd rdx, r8\nmov rcx, rdx\nsub rcx, r11\nnop dword ptr [rax+00000000h]\nloc_1678:\nmovdqa xmm0, xmm1\nsub rdx, 10h\npaddd xmm1, xmm2\npshufd xmm0, xmm0, 1Bh\nmovups xmmword ptr [rdx+10h], xmm0\ncmp rcx, rdx\njnz short loc_1678\ntest r9b, 3\njz short loc_16D6\nmov r11d, r9d\nmov edx, r10d\nand r11d, 0FFFFFFFCh\nlea ecx, [rax+r11]\nsub edx, r11d\nloc_16A9:\nmovsxd r11, edx\nlea r15d, [rcx+1]\nmov [r8+r11*4], ecx\nlea rbp, ds:0[r11*4]\ncmp r12d, edx\njge short loc_16D6\nsub edx, 2\nmov [r8+rbp-4], r15d\nadd ecx, 2\ncmp edx, r12d\njl short loc_16D6\nmov [r8+rbp-8], ecx\nloc_16D6:\nadd eax, r9d\nloc_16D9:\ncmp esi, r10d\njg short loc_170B\nmovsxd rdx, r10d\nlea r11d, [rax+r13-1]\nnop word ptr [rax+rax+00000000h]\nloc_16F0:\nmov rcx, [rbx+rdx*8]\nmov r8d, r11d\nsub r8d, edx\nsub rdx, 1\nmov [rcx+rdi], r8d\ncmp esi, edx\njle short loc_16F0\nlea eax, [r9+rax-1]\nloc_170B:\nadd r12d, 1\nsub r13, 1\nsub r9d, 2\nadd rdi, 4\ncmp r14d, eax\njge loc_1558\nloc_1724:\nadd rsp, 18h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1736:\nmov edx, r10d\nmov ecx, eax\njmp loc_16A9\nloc_1740:\nmov edx, esi\nmov ecx, eax\njmp loc_15BA", + "ida_strip_pseudo": "_QWORD *__fastcall sub_14C0(int a1)\n{\n _QWORD *v1; // rbx\n __int64 v2; // rbp\n _QWORD *v4; // r12\n signed int v5; // r10d\n unsigned __int64 v6; // rdi\n int v7; // esi\n int v8; // r14d\n __int64 v9; // r13\n unsigned int v10; // r9d\n __m128i si128; // xmm3\n __m128i v12; // xmm2\n signed int v13; // r12d\n signed int v14; // eax\n __int64 v15; // r8\n unsigned int v16; // edx\n __int64 v17; // rcx\n __m128i v18; // xmm0\n __m128i v19; // xmm1\n unsigned int v20; // edx\n signed int v21; // ecx\n int v22; // edx\n __int64 v23; // rbp\n int v24; // ecx\n signed int v25; // r8d\n __int64 *v26; // rdx\n int v27; // r11d\n __int64 v28; // rcx\n signed int v29; // r15d\n __int64 v30; // r8\n __m128i v31; // xmm1\n __m128i *v32; // rdx\n __m128i v33; // xmm0\n signed int v34; // ecx\n signed int v35; // edx\n __int64 v36; // rbp\n int v37; // ecx\n __int64 v38; // rdx\n __int64 v39; // rcx\n int v40; // r8d\n __int64 v42; // [rsp+8h] [rbp-40h]\n\n v1 = 0LL;\n if ( a1 > 0 )\n {\n v2 = a1;\n v1 = malloc(8LL * a1);\n v4 = v1;\n do\n *v4++ = calloc(a1, 4uLL);\n while ( &v1[a1] != v4 );\n v5 = a1 - 1;\n v6 = 0LL;\n v7 = 0;\n v8 = a1 * a1;\n v42 = 4 * v2 - 20;\n v9 = v5;\n v10 = v5;\n si128 = _mm_load_si128((const __m128i *)&xmmword_20A0);\n v12 = _mm_load_si128((const __m128i *)&xmmword_20B0);\n v13 = 0;\n v14 = 1;\n while ( 1 )\n {\n if ( v7 > v5 )\n goto LABEL_15;\n v15 = v1[v6 / 4];\n v16 = v10 + 1;\n if ( v10 <= 2 )\n break;\n v17 = v15 + v6;\n v18 = _mm_add_epi32(_mm_shuffle_epi32(_mm_cvtsi32_si128(v14), 0), si128);\n do\n {\n v19 = v18;\n v17 += 16LL;\n v18 = _mm_add_epi32(v18, v12);\n *(__m128i *)(v17 - 16) = v19;\n }\n while ( v15 + v6 + 16LL * (v16 >> 2) != v17 );\n if ( (v16 & 3) != 0 )\n {\n v20 = v16 & 0xFFFFFFFC;\n v21 = v14 + v20;\n v22 = v7 + v20;\nLABEL_11:\n *(_DWORD *)(v15 + 4LL * v22) = v21;\n v23 = 4LL * v22;\n if ( v5 > v22 )\n {\n *(_DWORD *)(v15 + v23 + 4) = v21 + 1;\n v24 = v21 + 2;\n if ( v5 >= v22 + 2 )\n *(_DWORD *)(v15 + v23 + 8) = v24;\n }\n }\n v14 += v10 + 1;\nLABEL_15:\n if ( ++v7 <= v5 )\n {\n v25 = v14;\n v26 = &v1[v7];\n v27 = v14 + v5 - v13;\n do\n {\n v28 = *v26;\n v29 = v14++;\n ++v26;\n *(_DWORD *)(v28 + 4 * v9) = v29;\n }\n while ( v14 != v27 );\n v14 = v10 + v25;\n }\n if ( --v5 < v13 )\n goto LABEL_29;\n v30 = v1[v9];\n if ( v10 - 1 <= 2 )\n {\n v35 = v5;\n v34 = v14;\n goto LABEL_25;\n }\n v31 = _mm_add_epi32(_mm_shuffle_epi32(_mm_cvtsi32_si128(v14), 0), si128);\n v32 = (__m128i *)(v30 + v42 - v6);\n do\n {\n v33 = v31;\n --v32;\n v31 = _mm_add_epi32(v31, v12);\n v32[1] = _mm_shuffle_epi32(v33, 27);\n }\n while ( (__m128i *)(v30 + v42 - v6 - 16LL * (v10 >> 2)) != v32 );\n if ( (v10 & 3) != 0 )\n {\n v34 = v14 + (v10 & 0xFFFFFFFC);\n v35 = v5 - (v10 & 0xFFFFFFFC);\nLABEL_25:\n *(_DWORD *)(v30 + 4LL * v35) = v34;\n v36 = 4LL * v35;\n if ( v13 < v35 )\n {\n *(_DWORD *)(v30 + v36 - 4) = v34 + 1;\n v37 = v34 + 2;\n if ( v35 - 2 >= v13 )\n *(_DWORD *)(v30 + v36 - 8) = v37;\n }\n }\n v14 += v10;\nLABEL_29:\n if ( v7 <= v5 )\n {\n v38 = v5;\n do\n {\n v39 = v1[v38];\n v40 = v14 + v9 - 1 - v38--;\n *(_DWORD *)(v39 + v6) = v40;\n }\n while ( v7 <= (int)v38 );\n v14 = v10 + v14 - 1;\n }\n ++v13;\n --v9;\n v10 -= 2;\n v6 += 4LL;\n if ( v8 < v14 )\n return v1;\n }\n v22 = v7;\n v21 = v14;\n goto LABEL_11;\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_14C0(int a1) {\n uint64_t *v1;\n long long v2;\n uint64_t *v4;\n signed int v5;\n unsigned long long v6;\n int v7;\n int v8;\n long long v9;\n unsigned int v10;\n __m128i si128;\n __m128i v12;\n signed int v13;\n signed int v14;\n long long v15;\n unsigned int v16;\n long long v17;\n __m128i v18;\n __m128i v19;\n unsigned int v20;\n signed int v21;\n int v22;\n long long v23;\n int v24;\n signed int v25;\n long long *v26;\n int v27;\n long long v28;\n signed int v29;\n long long v30;\n __m128i v31;\n __m128i *v32;\n __m128i v33;\n signed int v34;\n signed int v35;\n long long v36;\n int v37;\n long long v38;\n long long v39;\n int v40;\n long long v42;\n v1 = 0LL;\n if (a1 > 0) {\n v2 = a1;\n v1 = malloc(8LL * a1);\n v4 = v1;\n do\n *v4++ = calloc(a1, 4uLL);\n while (&v1[a1] != v4);\n v5 = a1 - 1;\n v6 = 0LL;\n v7 = 0;\n v8 = a1 * a1;\n v42 = 4 * v2 - 20;\n v9 = v5;\n v10 = v5;\n si128 = _mm_load_si128((const __m128i *)&xmmword_20A0);\n v12 = _mm_load_si128((const __m128i *)&xmmword_20B0);\n v13 = 0;\n v14 = 1;\n while (1) {\n if (v7 > v5) goto LABEL_15;\n v15 = v1[v6 / 4];\n v16 = v10 + 1;\n if (v10 <= 2) break;\n v17 = v15 + v6;\n v18 = _mm_add_epi32(_mm_shuffle_epi32(_mm_cvtsi32_si128(v14), 0), si128);\n do {\n v19 = v18;\n v17 += 16LL;\n v18 = _mm_add_epi32(v18, v12);\n *(__m128i *)(v17 - 16) = v19;\n } while (v15 + v6 + 16LL * (v16 >> 2) != v17);\n if ((v16 & 3) != 0) {\n v20 = v16 & 4294967292;\n v21 = v14 + v20;\n v22 = v7 + v20;\n LABEL_11:\n *(uint32_t *)(v15 + 4LL * v22) = v21;\n v23 = 4LL * v22;\n if (v5 > v22) {\n *(uint32_t *)(v15 + v23 + 4) = v21 + 1;\n v24 = v21 + 2;\n if (v5 >= v22 + 2) *(uint32_t *)(v15 + v23 + 8) = v24;\n }\n }\n v14 += v10 + 1;\n LABEL_15:\n if (++v7 <= v5) {\n v25 = v14;\n v26 = &v1[v7];\n v27 = v14 + v5 - v13;\n do {\n v28 = *v26;\n v29 = v14++;\n ++v26;\n *(uint32_t *)(v28 + 4 * v9) = v29;\n } while (v14 != v27);\n v14 = v10 + v25;\n }\n if (--v5 < v13) goto LABEL_29;\n v30 = v1[v9];\n if (v10 - 1 <= 2) {\n v35 = v5;\n v34 = v14;\n goto LABEL_25;\n }\n v31 = _mm_add_epi32(_mm_shuffle_epi32(_mm_cvtsi32_si128(v14), 0), si128);\n v32 = (__m128i *)(v30 + v42 - v6);\n do {\n v33 = v31;\n --v32;\n v31 = _mm_add_epi32(v31, v12);\n v32[1] = _mm_shuffle_epi32(v33, 27);\n } while ((__m128i *)(v30 + v42 - v6 - 16LL * (v10 >> 2)) != v32);\n if ((v10 & 3) != 0) {\n v34 = v14 + (v10 & 4294967292);\n v35 = v5 - (v10 & 4294967292);\n LABEL_25:\n *(uint32_t *)(v30 + 4LL * v35) = v34;\n v36 = 4LL * v35;\n if (v13 < v35) {\n *(uint32_t *)(v30 + v36 - 4) = v34 + 1;\n v37 = v34 + 2;\n if (v35 - 2 >= v13) *(uint32_t *)(v30 + v36 - 8) = v37;\n }\n }\n v14 += v10;\n LABEL_29:\n if (v7 <= v5) {\n v38 = v5;\n do {\n v39 = v1[v38];\n v40 = v14 + v9 - 1 - v38--;\n *(uint32_t *)(v39 + v6) = v40;\n } while (v7 <= (int)v38);\n v14 = v10 + v14 - 1;\n }\n ++v13;\n --v9;\n v10 -= 2;\n v6 += 4LL;\n if (v8 < v14) return v1;\n }\n v22 = v7;\n v21 = v14;\n goto LABEL_11;\n }\n return v1;\n}", + "ida_pseudo_norm": "uint64_t *func0(int a1) {\n uint64_t *v1;\n long long v2;\n uint64_t *v4;\n signed int v5;\n unsigned long long v6;\n int v7;\n int v8;\n long long v9;\n unsigned int v10;\n __m128i si128;\n __m128i v12;\n signed int v13;\n signed int v14;\n long long v15;\n unsigned int v16;\n long long v17;\n __m128i v18;\n __m128i v19;\n unsigned int v20;\n signed int v21;\n int v22;\n long long v23;\n int v24;\n signed int v25;\n long long *v26;\n int v27;\n long long v28;\n signed int v29;\n long long v30;\n __m128i v31;\n __m128i *v32;\n __m128i v33;\n signed int v34;\n signed int v35;\n long long v36;\n int v37;\n long long v38;\n long long v39;\n int v40;\n long long v42;\n v1 = 0LL;\n if (a1 > 0) {\n v2 = a1;\n v1 = malloc(8LL * a1);\n v4 = v1;\n do\n *v4++ = calloc(a1, 4uLL);\n while (&v1[a1] != v4);\n v5 = a1 - 1;\n v6 = 0LL;\n v7 = 0;\n v8 = a1 * a1;\n v42 = 4 * v2 - 20;\n v9 = v5;\n v10 = v5;\n si128 = _mm_load_si128((const __m128i *)&xmmword_20A0);\n v12 = _mm_load_si128((const __m128i *)&xmmword_20B0);\n v13 = 0;\n v14 = 1;\n while (1) {\n if (v7 > v5) goto LABEL_15;\n v15 = v1[v6 / 4];\n v16 = v10 + 1;\n if (v10 <= 2) break;\n v17 = v15 + v6;\n v18 = _mm_add_epi32(_mm_shuffle_epi32(_mm_cvtsi32_si128(v14), 0), si128);\n do {\n v19 = v18;\n v17 += 16LL;\n v18 = _mm_add_epi32(v18, v12);\n *(__m128i *)(v17 - 16) = v19;\n } while (v15 + v6 + 16LL * (v16 >> 2) != v17);\n if ((v16 & 3) != 0) {\n v20 = v16 & 4294967292;\n v21 = v14 + v20;\n v22 = v7 + v20;\n LABEL_11:\n *(uint32_t *)(v15 + 4LL * v22) = v21;\n v23 = 4LL * v22;\n if (v5 > v22) {\n *(uint32_t *)(v15 + v23 + 4) = v21 + 1;\n v24 = v21 + 2;\n if (v5 >= v22 + 2) *(uint32_t *)(v15 + v23 + 8) = v24;\n }\n }\n v14 += v10 + 1;\n LABEL_15:\n if (++v7 <= v5) {\n v25 = v14;\n v26 = &v1[v7];\n v27 = v14 + v5 - v13;\n do {\n v28 = *v26;\n v29 = v14++;\n ++v26;\n *(uint32_t *)(v28 + 4 * v9) = v29;\n } while (v14 != v27);\n v14 = v10 + v25;\n }\n if (--v5 < v13) goto LABEL_29;\n v30 = v1[v9];\n if (v10 - 1 <= 2) {\n v35 = v5;\n v34 = v14;\n goto LABEL_25;\n }\n v31 = _mm_add_epi32(_mm_shuffle_epi32(_mm_cvtsi32_si128(v14), 0), si128);\n v32 = (__m128i *)(v30 + v42 - v6);\n do {\n v33 = v31;\n --v32;\n v31 = _mm_add_epi32(v31, v12);\n v32[1] = _mm_shuffle_epi32(v33, 27);\n } while ((__m128i *)(v30 + v42 - v6 - 16LL * (v10 >> 2)) != v32);\n if ((v10 & 3) != 0) {\n v34 = v14 + (v10 & 4294967292);\n v35 = v5 - (v10 & 4294967292);\n LABEL_25:\n *(uint32_t *)(v30 + 4LL * v35) = v34;\n v36 = 4LL * v35;\n if (v13 < v35) {\n *(uint32_t *)(v30 + v36 - 4) = v34 + 1;\n v37 = v34 + 2;\n if (v35 - 2 >= v13) *(uint32_t *)(v30 + v36 - 8) = v37;\n }\n }\n v14 += v10;\n LABEL_29:\n if (v7 <= v5) {\n v38 = v5;\n do {\n v39 = v1[v38];\n v40 = v14 + v9 - 1 - v38--;\n *(uint32_t *)(v39 + v6) = v40;\n } while (v7 <= (int)v38);\n v14 = v10 + v14 - 1;\n }\n ++v13;\n --v9;\n v10 -= 2;\n v6 += 4LL;\n if (v8 < v14) return v1;\n }\n v22 = v7;\n v21 = v14;\n goto LABEL_11;\n }\n return v1;\n}" + }, + { + "index": 835, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "float func0(int x1, int y1, int x2, int y2) {\n return (float)(y2 - y1) / (x2 - x1);\n}", + "test": "int main() {\n\n assert(func0(4, 2, 2, 5) == -1.5);\n\n assert(func0(2, 4, 4, 6) == 1.0);\n\n assert(func0(1, 2, 4, 2) == 0.0);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov %esi,-0x8(%rbp)\nmov %edx,-0xc(%rbp)\nmov %ecx,-0x10(%rbp)\nmov -0x10(%rbp),%eax\nsub -0x8(%rbp),%eax\ncvtsi2ss %eax,%xmm0\nmov -0xc(%rbp),%eax\nsub -0x4(%rbp),%eax\ncvtsi2ss %eax,%xmm1\ndivss %xmm1,%xmm0\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov [rbp+var_C], edx\nmov [rbp+var_10], ecx\nmov eax, [rbp+var_10]\nsub eax, [rbp+var_8]\npxor xmm0, xmm0\ncvtsi2ss xmm0, eax\nmov eax, [rbp+var_C]\nsub eax, [rbp+var_4]\npxor xmm1, xmm1\ncvtsi2ss xmm1, eax\ndivss xmm0, xmm1\npop rbp\nretn", + "ida_pseudo": "float __fastcall func0(int a1, int a2, int a3, int a4)\n{\n return (float)(a4 - a2) / (float)(a3 - a1);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov [rbp+var_C], edx\nmov [rbp+var_10], ecx\nmov eax, [rbp+var_10]\nsub eax, [rbp+var_8]\npxor xmm0, xmm0\ncvtsi2ss xmm0, eax\nmov eax, [rbp+var_C]\nsub eax, [rbp+var_4]\npxor xmm1, xmm1\ncvtsi2ss xmm1, eax\ndivss xmm0, xmm1\npop rbp\nretn", + "ida_strip_pseudo": "float __fastcall sub_1149(int a1, int a2, int a3, int a4)\n{\n return (float)(a4 - a2) / (float)(a3 - a1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "float sub_1149(int a1, int a2, int a3, int a4) {\n return (float)(a4 - a2) / (float)(a3 - a1);\n}", + "ida_pseudo_norm": "float func0(int a1, int a2, int a3, int a4) {\n return (float)(a4 - a2) / (float)(a3 - a1);\n}" + }, + { + "index": 836, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int a[], int size) {\n int max_so_far = INT_MIN;\n int max_ending_here = 0;\n int start = 0;\n int end = 0;\n int s = 0;\n for (int i = 0; i < size; i++) {\n max_ending_here += a[i];\n if (max_so_far < max_ending_here) {\n max_so_far = max_ending_here;\n start = s;\n end = i;\n }\n if (max_ending_here < 0) {\n max_ending_here = 0;\n s = i + 1;\n }\n }\n return (end - start + 1);\n}", + "test": "int main() {\n\n assert(func0((int[]){-2, -3, 4, -1, -2, 1, 5, -3}, 8) == 5);\n\n assert(func0((int[]){1, -2, 1, 1, -2, 1}, 6) == 2);\n\n assert(func0((int[]){-1, -2, 3, 4, 5}, 5) == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmovl $0x80000000,-0x18(%rbp)\nmovl $0x0,-0x14(%rbp)\nmovl $0x0,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11f1 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nadd %eax,-0x14(%rbp)\nmov -0x18(%rbp),%eax\ncmp -0x14(%rbp),%eax\njge 11d7 \nmov -0x14(%rbp),%eax\nmov %eax,-0x18(%rbp)\nmov -0x8(%rbp),%eax\nmov %eax,-0x10(%rbp)\nmov -0x4(%rbp),%eax\nmov %eax,-0xc(%rbp)\ncmpl $0x0,-0x14(%rbp)\njns 11ed \nmovl $0x0,-0x14(%rbp)\nmov -0x4(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 11a4 \nmov -0xc(%rbp),%eax\nsub -0x10(%rbp),%eax\nadd $0x1,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_18], 80000000h\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11F1\nloc_11A4:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_14], eax\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_14]\njge short loc_11D7\nmov eax, [rbp+var_14]\nmov [rbp+var_18], eax\nmov eax, [rbp+var_8]\nmov [rbp+var_10], eax\nmov eax, [rbp+var_4]\nmov [rbp+var_C], eax\nloc_11D7:\ncmp [rbp+var_14], 0\njns short loc_11ED\nmov [rbp+var_14], 0\nmov eax, [rbp+var_4]\nadd eax, 1\nmov [rbp+var_8], eax\nloc_11ED:\nadd [rbp+var_4], 1\nloc_11F1:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_2C]\njl short loc_11A4\nmov eax, [rbp+var_C]\nsub eax, [rbp+var_10]\nadd eax, 1\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n signed int v3; // [rsp+14h] [rbp-18h]\n int v4; // [rsp+18h] [rbp-14h]\n int v5; // [rsp+1Ch] [rbp-10h]\n int v6; // [rsp+20h] [rbp-Ch]\n int v7; // [rsp+24h] [rbp-8h]\n int i; // [rsp+28h] [rbp-4h]\n\n v3 = 0x80000000;\n v4 = 0;\n v5 = 0;\n v6 = 0;\n v7 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v4 += *(_DWORD *)(4LL * i + a1);\n if ( v3 < v4 )\n {\n v3 = v4;\n v5 = v7;\n v6 = i;\n }\n if ( v4 < 0 )\n {\n v4 = 0;\n v7 = i + 1;\n }\n }\n return (unsigned int)(v6 - v5 + 1);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_18], 80000000h\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11F1\nloc_11A4:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_14], eax\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_14]\njge short loc_11D7\nmov eax, [rbp+var_14]\nmov [rbp+var_18], eax\nmov eax, [rbp+var_8]\nmov [rbp+var_10], eax\nmov eax, [rbp+var_4]\nmov [rbp+var_C], eax\nloc_11D7:\ncmp [rbp+var_14], 0\njns short loc_11ED\nmov [rbp+var_14], 0\nmov eax, [rbp+var_4]\nadd eax, 1\nmov [rbp+var_8], eax\nloc_11ED:\nadd [rbp+var_4], 1\nloc_11F1:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_2C]\njl short loc_11A4\nmov eax, [rbp+var_C]\nsub eax, [rbp+var_10]\nadd eax, 1\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n signed int v3; // [rsp+14h] [rbp-18h]\n int v4; // [rsp+18h] [rbp-14h]\n int v5; // [rsp+1Ch] [rbp-10h]\n int v6; // [rsp+20h] [rbp-Ch]\n int v7; // [rsp+24h] [rbp-8h]\n int i; // [rsp+28h] [rbp-4h]\n\n v3 = 0x80000000;\n v4 = 0;\n v5 = 0;\n v6 = 0;\n v7 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v4 += *(_DWORD *)(4LL * i + a1);\n if ( v3 < v4 )\n {\n v3 = v4;\n v5 = v7;\n v6 = i;\n }\n if ( v4 < 0 )\n {\n v4 = 0;\n v7 = i + 1;\n }\n }\n return (unsigned int)(v6 - v5 + 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n signed int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n int i;\n v3 = 2147483648;\n v4 = 0;\n v5 = 0;\n v6 = 0;\n v7 = 0;\n for (i = 0; i < a2; ++i) {\n v4 += *(uint32_t *)(4LL * i + a1);\n if (v3 < v4) {\n v3 = v4;\n v5 = v7;\n v6 = i;\n }\n if (v4 < 0) {\n v4 = 0;\n v7 = i + 1;\n }\n }\n return (unsigned int)(v6 - v5 + 1);\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n signed int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n int i;\n v3 = 2147483648;\n v4 = 0;\n v5 = 0;\n v6 = 0;\n v7 = 0;\n for (i = 0; i < a2; ++i) {\n v4 += *(uint32_t *)(4LL * i + a1);\n if (v3 < v4) {\n v3 = v4;\n v5 = v7;\n v6 = i;\n }\n if (v4 < 0) {\n v4 = 0;\n v7 = i + 1;\n }\n }\n return (unsigned int)(v6 - v5 + 1);\n}" + }, + { + "index": 836, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int a[], int size) {\n int max_so_far = INT_MIN;\n int max_ending_here = 0;\n int start = 0;\n int end = 0;\n int s = 0;\n for (int i = 0; i < size; i++) {\n max_ending_here += a[i];\n if (max_so_far < max_ending_here) {\n max_so_far = max_ending_here;\n start = s;\n end = i;\n }\n if (max_ending_here < 0) {\n max_ending_here = 0;\n s = i + 1;\n }\n }\n return (end - start + 1);\n}", + "test": "int main() {\n\n assert(func0((int[]){-2, -3, 4, -1, -2, 1, 5, -3}, 8) == 5);\n\n assert(func0((int[]){1, -2, 1, 1, -2, 1}, 6) == 2);\n\n assert(func0((int[]){-1, -2, 3, 4, 5}, 5) == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\ntest %esi,%esi\njle 11cd \nlea -0x1(%rsi),%r10d\nmov $0x0,%edx\nmov $0x0,%r11d\nmov $0x0,%eax\nmov $0x0,%ebx\nmov $0x0,%esi\nmov $0x80000000,%r8d\nmov $0x0,%ebp\njmp 11ae \ntest %ecx,%ecx\njs 11c5 \nlea 0x1(%rdx),%rcx\ncmp %r10,%rdx\nje 11d7 \nmov %rcx,%rdx\nmov %edx,%r9d\nadd (%rdi,%rdx,4),%esi\nmov %esi,%ecx\ncmp %r8d,%esi\njle 119e \nmov %edx,%eax\nmov %r11d,%ebx\nmov %esi,%r8d\njmp 119e \nlea 0x1(%r9),%r11d\nmov %ebp,%esi\njmp 11a2 \nmov $0x0,%eax\nmov $0x0,%ebx\nsub %ebx,%eax\nadd $0x1,%eax\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11CC\npush rbx\nmovsxd rsi, esi\nmov edx, 0\nmov r10d, 0\nmov eax, 0\nmov r11d, 0\nmov r8d, 0\nmov r9d, 80000000h\nmov ebx, 0\njmp short loc_11AB\nloc_119E:\ntest ecx, ecx\njs short loc_11C3\nloc_11A2:\nadd rdx, 1\ncmp rdx, rsi\njz short loc_11DE\nloc_11AB:\nmov ecx, r8d\nadd ecx, [rdi+rdx*4]\nmov r8d, ecx\ncmp ecx, r9d\njle short loc_119E\nmov eax, edx\nmov r11d, r10d\nmov r9d, ecx\njmp short loc_119E\nloc_11C3:\nlea r10d, [rdx+1]\nmov r8d, ebx\njmp short loc_11A2\nloc_11CC:\nmov eax, 0\nmov r11d, 0\nsub eax, r11d\nadd eax, 1\nretn\nloc_11DE:\nsub eax, r11d\nadd eax, 1\npop rbx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // rdx\n int v3; // r10d\n int v4; // eax\n int v5; // r11d\n int v6; // r8d\n signed int v7; // r9d\n int v8; // ecx\n\n if ( a2 <= 0 )\n return 1LL;\n v2 = 0LL;\n v3 = 0;\n v4 = 0;\n v5 = 0;\n v6 = 0;\n v7 = 0x80000000;\n do\n {\n v8 = *(_DWORD *)(a1 + 4 * v2) + v6;\n v6 = v8;\n if ( v8 > v7 )\n {\n v4 = v2;\n v5 = v3;\n v7 = v8;\n }\n if ( v8 < 0 )\n {\n v3 = v2 + 1;\n v6 = 0;\n }\n ++v2;\n }\n while ( v2 != a2 );\n return (unsigned int)(v4 - v5 + 1);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11CC\npush rbx\nmovsxd rsi, esi\nmov edx, 0\nmov r10d, 0\nmov eax, 0\nmov r11d, 0\nmov r8d, 0\nmov r9d, 80000000h\nmov ebx, 0\njmp short loc_11AB\nloc_119E:\ntest ecx, ecx\njs short loc_11C3\nloc_11A2:\nadd rdx, 1\ncmp rdx, rsi\njz short loc_11DE\nloc_11AB:\nmov ecx, r8d\nadd ecx, [rdi+rdx*4]\nmov r8d, ecx\ncmp ecx, r9d\njle short loc_119E\nmov eax, edx\nmov r11d, r10d\nmov r9d, ecx\njmp short loc_119E\nloc_11C3:\nlea r10d, [rdx+1]\nmov r8d, ebx\njmp short loc_11A2\nloc_11CC:\nmov eax, 0\nmov r11d, 0\nsub eax, r11d\nadd eax, 1\nretn\nloc_11DE:\nsub eax, r11d\nadd eax, 1\npop rbx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n __int64 v2; // rdx\n int v3; // r10d\n int v4; // eax\n int v5; // r11d\n int v6; // r8d\n signed int v7; // r9d\n int v8; // ecx\n\n if ( a2 <= 0 )\n return 1LL;\n v2 = 0LL;\n v3 = 0;\n v4 = 0;\n v5 = 0;\n v6 = 0;\n v7 = 0x80000000;\n do\n {\n v8 = *(_DWORD *)(a1 + 4 * v2) + v6;\n v6 = v8;\n if ( v8 > v7 )\n {\n v4 = v2;\n v5 = v3;\n v7 = v8;\n }\n if ( v8 < 0 )\n {\n v3 = v2 + 1;\n v6 = 0;\n }\n ++v2;\n }\n while ( v2 != a2 );\n return (unsigned int)(v4 - v5 + 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n long long v2;\n int v3;\n int v4;\n int v5;\n int v6;\n signed int v7;\n int v8;\n if (a2 <= 0) return 1LL;\n v2 = 0LL;\n v3 = 0;\n v4 = 0;\n v5 = 0;\n v6 = 0;\n v7 = 2147483648;\n do {\n v8 = *(uint32_t *)(a1 + 4 * v2) + v6;\n v6 = v8;\n if (v8 > v7) {\n v4 = v2;\n v5 = v3;\n v7 = v8;\n }\n if (v8 < 0) {\n v3 = v2 + 1;\n v6 = 0;\n }\n ++v2;\n } while (v2 != a2);\n return (unsigned int)(v4 - v5 + 1);\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n int v3;\n int v4;\n int v5;\n int v6;\n signed int v7;\n int v8;\n if (a2 <= 0) return 1LL;\n v2 = 0LL;\n v3 = 0;\n v4 = 0;\n v5 = 0;\n v6 = 0;\n v7 = 2147483648;\n do {\n v8 = *(uint32_t *)(a1 + 4 * v2) + v6;\n v6 = v8;\n if (v8 > v7) {\n v4 = v2;\n v5 = v3;\n v7 = v8;\n }\n if (v8 < 0) {\n v3 = v2 + 1;\n v6 = 0;\n }\n ++v2;\n } while (v2 != a2);\n return (unsigned int)(v4 - v5 + 1);\n}" + }, + { + "index": 836, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int a[], int size) {\n int max_so_far = INT_MIN;\n int max_ending_here = 0;\n int start = 0;\n int end = 0;\n int s = 0;\n for (int i = 0; i < size; i++) {\n max_ending_here += a[i];\n if (max_so_far < max_ending_here) {\n max_so_far = max_ending_here;\n start = s;\n end = i;\n }\n if (max_ending_here < 0) {\n max_ending_here = 0;\n s = i + 1;\n }\n }\n return (end - start + 1);\n}", + "test": "int main() {\n\n assert(func0((int[]){-2, -3, 4, -1, -2, 1, 5, -3}, 8) == 5);\n\n assert(func0((int[]){1, -2, 1, 1, -2, 1}, 6) == 2);\n\n assert(func0((int[]){-1, -2, 3, 4, 5}, 5) == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 13d8 \npush %rbx\nxor %r8d,%r8d\nxor %r9d,%r9d\nxor %eax,%eax\nxor %ebx,%ebx\nxor %ecx,%ecx\nmov $0x80000000,%r10d\nxor %r11d,%r11d\nxchg %ax,%ax\nadd (%rdi),%ecx\nmov %ecx,%edx\ncmp %r10d,%ecx\njle 13b2 \nmov %r8d,%eax\nmov %r9d,%ebx\nmov %ecx,%r10d\nadd $0x1,%r8d\ntest %edx,%edx\ncmovs %r11d,%edx\ncmovs %r8d,%r9d\nadd $0x4,%rdi\nmov %edx,%ecx\ncmp %r8d,%esi\njne 13a0 \nsub %ebx,%eax\npop %rbx\nadd $0x1,%eax\nretq\nnopw 0x0(%rax,%rax,1)\nmov $0x1,%eax\nretq\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_12E0\nxor ecx, ecx\nxor r8d, r8d\nxor eax, eax\nxor r11d, r11d\nxor edx, edx\nmov r9d, 80000000h\nxor r10d, r10d\nnop dword ptr [rax]\nloc_12B0:\nadd edx, [rdi]\ncmp r9d, edx\njge short loc_12BF\nmov eax, ecx\nmov r11d, r8d\nmov r9d, edx\nloc_12BF:\nadd ecx, 1\ntest edx, edx\ncmovs r8d, ecx\ncmovs edx, r10d\nadd rdi, 4\ncmp esi, ecx\njnz short loc_12B0\nsub eax, r11d\nadd eax, 1\nretn\nloc_12E0:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n int v2; // ecx\n int v3; // r8d\n int v4; // eax\n int v5; // r11d\n int v6; // edx\n signed int v7; // r9d\n\n if ( a2 <= 0 )\n return 1LL;\n v2 = 0;\n v3 = 0;\n v4 = 0;\n v5 = 0;\n v6 = 0;\n v7 = 0x80000000;\n do\n {\n v6 += *a1;\n if ( v7 < v6 )\n {\n v4 = v2;\n v5 = v3;\n v7 = v6;\n }\n ++v2;\n if ( v6 < 0 )\n {\n v3 = v2;\n v6 = 0;\n }\n ++a1;\n }\n while ( a2 != v2 );\n return (unsigned int)(v4 - v5 + 1);\n}", + "ida_strip_asm": "sub_1290:\nendbr64\ntest esi, esi\njle short loc_12E0\nxor ecx, ecx\nxor r8d, r8d\nxor eax, eax\nxor r11d, r11d\nxor edx, edx\nmov r9d, 80000000h\nxor r10d, r10d\nnop dword ptr [rax]\nloc_12B0:\nadd edx, [rdi]\ncmp r9d, edx\njge short loc_12BF\nmov eax, ecx\nmov r11d, r8d\nmov r9d, edx\nloc_12BF:\nadd ecx, 1\ntest edx, edx\ncmovs r8d, ecx\ncmovs edx, r10d\nadd rdi, 4\ncmp esi, ecx\njnz short loc_12B0\nsub eax, r11d\nadd eax, 1\nretn\nloc_12E0:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1290(_DWORD *a1, int a2)\n{\n int v2; // ecx\n int v3; // r8d\n int v4; // eax\n int v5; // r11d\n int v6; // edx\n signed int v7; // r9d\n\n if ( a2 <= 0 )\n return 1LL;\n v2 = 0;\n v3 = 0;\n v4 = 0;\n v5 = 0;\n v6 = 0;\n v7 = 0x80000000;\n do\n {\n v6 += *a1;\n if ( v7 < v6 )\n {\n v4 = v2;\n v5 = v3;\n v7 = v6;\n }\n ++v2;\n if ( v6 < 0 )\n {\n v3 = v2;\n v6 = 0;\n }\n ++a1;\n }\n while ( a2 != v2 );\n return (unsigned int)(v4 - v5 + 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1290(uint32_t *a1, int a2) {\n int v2;\n int v3;\n int v4;\n int v5;\n int v6;\n signed int v7;\n if (a2 <= 0) return 1LL;\n v2 = 0;\n v3 = 0;\n v4 = 0;\n v5 = 0;\n v6 = 0;\n v7 = 2147483648;\n do {\n v6 += *a1;\n if (v7 < v6) {\n v4 = v2;\n v5 = v3;\n v7 = v6;\n }\n ++v2;\n if (v6 < 0) {\n v3 = v2;\n v6 = 0;\n }\n ++a1;\n } while (a2 != v2);\n return (unsigned int)(v4 - v5 + 1);\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n int v2;\n int v3;\n int v4;\n int v5;\n int v6;\n signed int v7;\n if (a2 <= 0) return 1LL;\n v2 = 0;\n v3 = 0;\n v4 = 0;\n v5 = 0;\n v6 = 0;\n v7 = 2147483648;\n do {\n v6 += *a1;\n if (v7 < v6) {\n v4 = v2;\n v5 = v3;\n v7 = v6;\n }\n ++v2;\n if (v6 < 0) {\n v3 = v2;\n v6 = 0;\n }\n ++a1;\n } while (a2 != v2);\n return (unsigned int)(v4 - v5 + 1);\n}" + }, + { + "index": 837, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int sum = 0;\n for (int i = 0; i < n; i++) {\n sum += (2 * i + 1) * (2 * i + 1) * (2 * i + 1);\n }\n return sum;\n}", + "test": "int main() {\n\n assert(func0(2) == 28);\n\n assert(func0(3) == 153);\n\n assert(func0(4) == 496);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 1189 \nmov -0x4(%rbp),%eax\nadd %eax,%eax\nlea 0x1(%rax),%edx\nmov -0x4(%rbp),%eax\nadd %eax,%eax\nadd $0x1,%eax\nimul %edx,%eax\nmov -0x4(%rbp),%edx\nadd %edx,%edx\nadd $0x1,%edx\nimul %edx,%eax\nadd %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x14(%rbp),%eax\njl 1164 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_1189\nloc_1164:\nmov eax, [rbp+var_4]\nadd eax, eax\nlea edx, [rax+1]\nmov eax, [rbp+var_4]\nadd eax, eax\nadd eax, 1\nimul eax, edx\nmov edx, [rbp+var_4]\nadd edx, edx\nadd edx, 1\nimul eax, edx\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_1189:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_14]\njl short loc_1164\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v2; // [rsp+Ch] [rbp-8h]\n int i; // [rsp+10h] [rbp-4h]\n\n v2 = 0;\n for ( i = 0; i < a1; ++i )\n v2 += (2 * i + 1) * (2 * i + 1) * (2 * i + 1);\n return v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_1189\nloc_1164:\nmov eax, [rbp+var_4]\nadd eax, eax\nlea edx, [rax+1]\nmov eax, [rbp+var_4]\nadd eax, eax\nadd eax, 1\nimul eax, edx\nmov edx, [rbp+var_4]\nadd edx, edx\nadd edx, 1\nimul eax, edx\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_1189:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_14]\njl short loc_1164\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n unsigned int v2; // [rsp+Ch] [rbp-8h]\n int i; // [rsp+10h] [rbp-4h]\n\n v2 = 0;\n for ( i = 0; i < a1; ++i )\n v2 += (2 * i + 1) * (2 * i + 1) * (2 * i + 1);\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n unsigned int v2;\n int i;\n v2 = 0;\n for (i = 0; i < a1; ++i) v2 += (2 * i + 1) * (2 * i + 1) * (2 * i + 1);\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v2;\n int i;\n v2 = 0;\n for (i = 0; i < a1; ++i) v2 += (2 * i + 1) * (2 * i + 1) * (2 * i + 1);\n return v2;\n}" + }, + { + "index": 837, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int sum = 0;\n for (int i = 0; i < n; i++) {\n sum += (2 * i + 1) * (2 * i + 1) * (2 * i + 1);\n }\n return sum;\n}", + "test": "int main() {\n\n assert(func0(2) == 28);\n\n assert(func0(3) == 153);\n\n assert(func0(4) == 496);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\njle 1173 \nlea 0x1(%rdi,%rdi,1),%esi\nmov $0x1,%eax\nmov $0x0,%ecx\nmov %eax,%edx\nimul %eax,%edx\nimul %eax,%edx\nadd %edx,%ecx\nadd $0x2,%eax\ncmp %esi,%eax\njne 115f \nmov %ecx,%eax\nretq\nmov $0x0,%ecx\njmp 1170 \n", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njle short loc_1173\nlea esi, [rdi+rdi+1]\nmov eax, 1\nmov ecx, 0\nloc_115F:\nmov edx, eax\nimul edx, eax\nimul edx, eax\nadd ecx, edx\nadd eax, 2\ncmp eax, esi\njnz short loc_115F\nloc_1170:\nmov eax, ecx\nretn\nloc_1173:\nmov ecx, 0\njmp short loc_1170", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // eax\n unsigned int v2; // ecx\n\n if ( a1 <= 0 )\n {\n return 0;\n }\n else\n {\n v1 = 1;\n v2 = 0;\n do\n {\n v2 += v1 * v1 * v1;\n v1 += 2;\n }\n while ( v1 != 2 * a1 + 1 );\n }\n return v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ntest edi, edi\njle short loc_1173\nlea esi, [rdi+rdi+1]\nmov eax, 1\nmov ecx, 0\nloc_115F:\nmov edx, eax\nimul edx, eax\nimul edx, eax\nadd ecx, edx\nadd eax, 2\ncmp eax, esi\njnz short loc_115F\nloc_1170:\nmov eax, ecx\nretn\nloc_1173:\nmov ecx, 0\njmp short loc_1170", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v1; // eax\n unsigned int v2; // ecx\n\n if ( a1 <= 0 )\n {\n return 0;\n }\n else\n {\n v1 = 1;\n v2 = 0;\n do\n {\n v2 += v1 * v1 * v1;\n v1 += 2;\n }\n while ( v1 != 2 * a1 + 1 );\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v1;\n unsigned int v2;\n if (a1 <= 0) {\n return 0;\n } else {\n v1 = 1;\n v2 = 0;\n do {\n v2 += v1 * v1 * v1;\n v1 += 2;\n } while (v1 != 2 * a1 + 1);\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n unsigned int v2;\n if (a1 <= 0) {\n return 0;\n } else {\n v1 = 1;\n v2 = 0;\n do {\n v2 += v1 * v1 * v1;\n v1 += 2;\n } while (v1 != 2 * a1 + 1);\n }\n return v2;\n}" + }, + { + "index": 838, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *s1, const char *s2) {\n int c0 = 0;\n int c1 = 0;\n int length = strlen(s1);\n for (int i = 0; i < length; i++) {\n if (s1[i] == '0' && s2[i] == '1') {\n c0++;\n } else if (s1[i] == '1' && s2[i] == '0') {\n c1++;\n }\n }\n int result = c0 / 2 + c1 / 2;\n if (c0 % 2 == 0 && c1 % 2 == 0) {\n return result;\n } else if ((c0 + c1) % 2 == 0) {\n return result + 2;\n } else {\n return -1;\n }\n}", + "test": "int main() {\n\n assert(func0(\"0011\", \"1111\") == 1);\n\n assert(func0(\"00011\", \"01001\") == 2);\n\n assert(func0(\"111\", \"111\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x28(%rbp)\nmov %rsi,-0x30(%rbp)\nmovl $0x0,-0x14(%rbp)\nmovl $0x0,-0x10(%rbp)\nmov -0x28(%rbp),%rax\nmov %rax,%rdi\ncallq 1060 \nmov %eax,-0x8(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 1201 \nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x30,%al\njne 11d1 \nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x30(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x31,%al\njne 11d1 \naddl $0x1,-0x14(%rbp)\njmp 11fd \nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x31,%al\njne 11fd \nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x30(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x30,%al\njne 11fd \naddl $0x1,-0x10(%rbp)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x8(%rbp),%eax\njl 11a3 \nmov -0x14(%rbp),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nmov %eax,%ecx\nmov -0x10(%rbp),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nadd %ecx,%eax\nmov %eax,-0x4(%rbp)\nmov -0x14(%rbp),%eax\nand $0x1,%eax\ntest %eax,%eax\njne 1241 \nmov -0x10(%rbp),%eax\nand $0x1,%eax\ntest %eax,%eax\njne 1241 \nmov -0x4(%rbp),%eax\njmp 125d \nmov -0x14(%rbp),%edx\nmov -0x10(%rbp),%eax\nadd %edx,%eax\nand $0x1,%eax\ntest %eax,%eax\njne 1258 \nmov -0x4(%rbp),%eax\nadd $0x2,%eax\njmp 125d \nmov $0xffffffff,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov [rbp+var_30], rsi\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_8], eax\nmov [rbp+var_C], 0\njmp short loc_1201\nloc_11A3:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 30h ; '0'\njnz short loc_11D1\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 31h ; '1'\njnz short loc_11D1\nadd [rbp+var_14], 1\njmp short loc_11FD\nloc_11D1:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 31h ; '1'\njnz short loc_11FD\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 30h ; '0'\njnz short loc_11FD\nadd [rbp+var_10], 1\nloc_11FD:\nadd [rbp+var_C], 1\nloc_1201:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_8]\njl short loc_11A3\nmov eax, [rbp+var_14]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov ecx, eax\nmov eax, [rbp+var_10]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nadd eax, ecx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_14]\nand eax, 1\ntest eax, eax\njnz short loc_1241\nmov eax, [rbp+var_10]\nand eax, 1\ntest eax, eax\njnz short loc_1241\nmov eax, [rbp+var_4]\njmp short locret_125D\nloc_1241:\nmov edx, [rbp+var_14]\nmov eax, [rbp+var_10]\nadd eax, edx\nand eax, 1\ntest eax, eax\njnz short loc_1258\nmov eax, [rbp+var_4]\nadd eax, 2\njmp short locret_125D\nloc_1258:\nmov eax, 0FFFFFFFFh\nlocret_125D:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, __int64 a2)\n{\n int v3; // [rsp+1Ch] [rbp-14h]\n int v4; // [rsp+20h] [rbp-10h]\n int i; // [rsp+24h] [rbp-Ch]\n int v6; // [rsp+28h] [rbp-8h]\n unsigned int v7; // [rsp+2Ch] [rbp-4h]\n\n v3 = 0;\n v4 = 0;\n v6 = strlen(a1);\n for ( i = 0; i < v6; ++i )\n {\n if ( a1[i] == 48 && *(_BYTE *)(i + a2) == 49 )\n {\n ++v3;\n }\n else if ( a1[i] == 49 && *(_BYTE *)(i + a2) == 48 )\n {\n ++v4;\n }\n }\n v7 = v3 / 2 + v4 / 2;\n if ( (v3 & 1) == 0 && (v4 & 1) == 0 )\n return v7;\n if ( (((_BYTE)v3 + (_BYTE)v4) & 1) != 0 )\n return 0xFFFFFFFFLL;\n return v7 + 2;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov [rbp+var_30], rsi\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_8], eax\nmov [rbp+var_C], 0\njmp short loc_1201\nloc_11A3:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 30h ; '0'\njnz short loc_11D1\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 31h ; '1'\njnz short loc_11D1\nadd [rbp+var_14], 1\njmp short loc_11FD\nloc_11D1:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 31h ; '1'\njnz short loc_11FD\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+var_30]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 30h ; '0'\njnz short loc_11FD\nadd [rbp+var_10], 1\nloc_11FD:\nadd [rbp+var_C], 1\nloc_1201:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_8]\njl short loc_11A3\nmov eax, [rbp+var_14]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov ecx, eax\nmov eax, [rbp+var_10]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nadd eax, ecx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_14]\nand eax, 1\ntest eax, eax\njnz short loc_1241\nmov eax, [rbp+var_10]\nand eax, 1\ntest eax, eax\njnz short loc_1241\nmov eax, [rbp+var_4]\njmp short locret_125D\nloc_1241:\nmov edx, [rbp+var_14]\nmov eax, [rbp+var_10]\nadd eax, edx\nand eax, 1\ntest eax, eax\njnz short loc_1258\nmov eax, [rbp+var_4]\nadd eax, 2\njmp short locret_125D\nloc_1258:\nmov eax, 0FFFFFFFFh\nlocret_125D:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1, __int64 a2)\n{\n int v3; // [rsp+1Ch] [rbp-14h]\n int v4; // [rsp+20h] [rbp-10h]\n int i; // [rsp+24h] [rbp-Ch]\n int v6; // [rsp+28h] [rbp-8h]\n unsigned int v7; // [rsp+2Ch] [rbp-4h]\n\n v3 = 0;\n v4 = 0;\n v6 = strlen(a1);\n for ( i = 0; i < v6; ++i )\n {\n if ( a1[i] == 48 && *(_BYTE *)(i + a2) == 49 )\n {\n ++v3;\n }\n else if ( a1[i] == 49 && *(_BYTE *)(i + a2) == 48 )\n {\n ++v4;\n }\n }\n v7 = v3 / 2 + v4 / 2;\n if ( (v3 & 1) == 0 && (v4 & 1) == 0 )\n return v7;\n if ( (((_BYTE)v3 + (_BYTE)v4) & 1) != 0 )\n return 0xFFFFFFFFLL;\n return v7 + 2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1, long long a2) {\n int v3;\n int v4;\n int i;\n int v6;\n unsigned int v7;\n v3 = 0;\n v4 = 0;\n v6 = strlen(a1);\n for (i = 0; i < v6; ++i) {\n if (a1[i] == 48 && *(uint8_t *)(i + a2) == 49) {\n ++v3;\n } else if (a1[i] == 49 && *(uint8_t *)(i + a2) == 48) {\n ++v4;\n }\n }\n v7 = v3 / 2 + v4 / 2;\n if ((v3 & 1) == 0 && (v4 & 1) == 0) return v7;\n if ((((uint8_t)v3 + (uint8_t)v4) & 1) != 0) return 4294967295LL;\n return v7 + 2;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, long long a2) {\n int v3;\n int v4;\n int i;\n int v6;\n unsigned int v7;\n v3 = 0;\n v4 = 0;\n v6 = strlen(a1);\n for (i = 0; i < v6; ++i) {\n if (a1[i] == 48 && *(uint8_t *)(i + a2) == 49) {\n ++v3;\n } else if (a1[i] == 49 && *(uint8_t *)(i + a2) == 48) {\n ++v4;\n }\n }\n v7 = v3 / 2 + v4 / 2;\n if ((v3 & 1) == 0 && (v4 & 1) == 0) return v7;\n if ((((uint8_t)v3 + (uint8_t)v4) & 1) != 0) return 4294967295LL;\n return v7 + 2;\n}" + }, + { + "index": 838, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *s1, const char *s2) {\n int c0 = 0;\n int c1 = 0;\n int length = strlen(s1);\n for (int i = 0; i < length; i++) {\n if (s1[i] == '0' && s2[i] == '1') {\n c0++;\n } else if (s1[i] == '1' && s2[i] == '0') {\n c1++;\n }\n }\n int result = c0 / 2 + c1 / 2;\n if (c0 % 2 == 0 && c1 % 2 == 0) {\n return result;\n } else if ((c0 + c1) % 2 == 0) {\n return result + 2;\n } else {\n return -1;\n }\n}", + "test": "int main() {\n\n assert(func0(\"0011\", \"1111\") == 1);\n\n assert(func0(\"00011\", \"01001\") == 2);\n\n assert(func0(\"111\", \"111\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%r8\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nsub $0x1,%rcx\ntest %ecx,%ecx\njle 11dd \nlea -0x1(%rcx),%r9d\nmov $0x0,%eax\nmov $0x0,%edi\nmov $0x0,%ecx\njmp 1196 \ncmpb $0x31,(%rsi,%rax,1)\nsete %dl\nmovzbl %dl,%edx\nadd %edx,%ecx\nlea 0x1(%rax),%rdx\ncmp %r9,%rax\nje 11b3 \nmov %rdx,%rax\nmovzbl (%r8,%rax,1),%edx\ncmp $0x30,%dl\nje 117e \ncmp $0x31,%dl\njne 118a \ncmpb $0x30,(%rsi,%rax,1)\nsete %dl\nmovzbl %dl,%edx\nadd %edx,%edi\njmp 118a \nmov %ecx,%eax\nshr $0x1f,%eax\nadd %ecx,%eax\nsar %eax\nmov %eax,%edx\nmov %edi,%eax\nshr $0x1f,%eax\nadd %edi,%eax\nsar %eax\nadd %edx,%eax\nmov %ecx,%edx\nor %edi,%edx\ntest $0x1,%dl\nje 11e8 \nadd %edi,%ecx\ntest $0x1,%cl\njne 11e3 \nadd $0x2,%eax\nretq\nmov $0x0,%eax\nretq\nmov $0xffffffff,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov rbp, rsi\ncall _strlen\ntest eax, eax\njle short loc_11F7\nlea ecx, [rax-1]\nmov eax, 0\nmov edi, 0\nmov esi, 0\njmp short loc_11A9\nloc_1196:\ncmp byte ptr [rbp+rax+0], 31h ; '1'\njz short loc_11C3\nloc_119D:\nlea rdx, [rax+1]\ncmp rcx, rax\njz short loc_11C8\nmov rax, rdx\nloc_11A9:\nmovzx edx, byte ptr [rbx+rax]\ncmp dl, 30h ; '0'\njz short loc_1196\ncmp dl, 31h ; '1'\njnz short loc_119D\ncmp byte ptr [rbp+rax+0], 30h ; '0'\njnz short loc_119D\nadd edi, 1\njmp short loc_119D\nloc_11C3:\nadd esi, 1\njmp short loc_119D\nloc_11C8:\nmov eax, esi\nshr eax, 1Fh\nadd eax, esi\nsar eax, 1\nmov edx, edi\nshr edx, 1Fh\nadd edx, edi\nsar edx, 1\nadd eax, edx\nmov edx, esi\nor edx, edi\ntest dl, 1\njz short loc_11F0\nadd esi, edi\ntest sil, 1\njnz short loc_11FE\nadd eax, 2\nloc_11F0:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_11F7:\nmov eax, 0\njmp short loc_11F0\nloc_11FE:\nmov eax, 0FFFFFFFFh\njmp short loc_11F0", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, __int64 a2)\n{\n int v4; // eax\n __int64 v5; // rcx\n __int64 v6; // rax\n int v7; // edi\n int v8; // esi\n char v9; // dl\n __int64 result; // rax\n\n v4 = strlen(a1);\n if ( v4 <= 0 )\n return 0LL;\n v5 = (unsigned int)(v4 - 1);\n v6 = 0LL;\n v7 = 0;\n v8 = 0;\n while ( 1 )\n {\n v9 = a1[v6];\n if ( v9 == 48 )\n {\n if ( *(_BYTE *)(a2 + v6) == 49 )\n ++v8;\n }\n else if ( v9 == 49 && *(_BYTE *)(a2 + v6) == 48 )\n {\n ++v7;\n }\n if ( v5 == v6 )\n break;\n ++v6;\n }\n result = (unsigned int)(v7 / 2 + v8 / 2);\n if ( (((unsigned __int8)v7 | (unsigned __int8)v8) & 1) != 0 )\n {\n if ( (((_BYTE)v7 + (_BYTE)v8) & 1) != 0 )\n return 0xFFFFFFFFLL;\n else\n return (unsigned int)(result + 2);\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov rbp, rsi\ncall _strlen\ntest eax, eax\njle short loc_11F7\nlea ecx, [rax-1]\nmov eax, 0\nmov edi, 0\nmov esi, 0\njmp short loc_11A9\nloc_1196:\ncmp byte ptr [rbp+rax+0], 31h ; '1'\njz short loc_11C3\nloc_119D:\nlea rdx, [rax+1]\ncmp rcx, rax\njz short loc_11C8\nmov rax, rdx\nloc_11A9:\nmovzx edx, byte ptr [rbx+rax]\ncmp dl, 30h ; '0'\njz short loc_1196\ncmp dl, 31h ; '1'\njnz short loc_119D\ncmp byte ptr [rbp+rax+0], 30h ; '0'\njnz short loc_119D\nadd edi, 1\njmp short loc_119D\nloc_11C3:\nadd esi, 1\njmp short loc_119D\nloc_11C8:\nmov eax, esi\nshr eax, 1Fh\nadd eax, esi\nsar eax, 1\nmov edx, edi\nshr edx, 1Fh\nadd edx, edi\nsar edx, 1\nadd eax, edx\nmov edx, esi\nor edx, edi\ntest dl, 1\njz short loc_11F0\nadd esi, edi\ntest sil, 1\njnz short loc_11FE\nadd eax, 2\nloc_11F0:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_11F7:\nmov eax, 0\njmp short loc_11F0\nloc_11FE:\nmov eax, 0FFFFFFFFh\njmp short loc_11F0", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1, __int64 a2)\n{\n int v4; // eax\n __int64 v5; // rcx\n __int64 v6; // rax\n int v7; // edi\n int v8; // esi\n char v9; // dl\n __int64 result; // rax\n\n v4 = strlen(a1);\n if ( v4 <= 0 )\n return 0LL;\n v5 = (unsigned int)(v4 - 1);\n v6 = 0LL;\n v7 = 0;\n v8 = 0;\n while ( 1 )\n {\n v9 = a1[v6];\n if ( v9 == 48 )\n {\n if ( *(_BYTE *)(a2 + v6) == 49 )\n ++v8;\n }\n else if ( v9 == 49 && *(_BYTE *)(a2 + v6) == 48 )\n {\n ++v7;\n }\n if ( v5 == v6 )\n break;\n ++v6;\n }\n result = (unsigned int)(v7 / 2 + v8 / 2);\n if ( (((unsigned __int8)v7 | (unsigned __int8)v8) & 1) != 0 )\n {\n if ( (((_BYTE)v7 + (_BYTE)v8) & 1) != 0 )\n return 0xFFFFFFFFLL;\n else\n return (unsigned int)(result + 2);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1, long long a2) {\n int v4;\n long long v5;\n long long v6;\n int v7;\n int v8;\n char v9;\n long long result;\n v4 = strlen(a1);\n if (v4 <= 0) return 0LL;\n v5 = (unsigned int)(v4 - 1);\n v6 = 0LL;\n v7 = 0;\n v8 = 0;\n while (1) {\n v9 = a1[v6];\n if (v9 == 48) {\n if (*(uint8_t *)(a2 + v6) == 49) ++v8;\n } else if (v9 == 49 && *(uint8_t *)(a2 + v6) == 48) {\n ++v7;\n }\n if (v5 == v6) break;\n ++v6;\n }\n result = (unsigned int)(v7 / 2 + v8 / 2);\n if ((((unsigned char)v7 | (unsigned char)v8) & 1) != 0) {\n if ((((uint8_t)v7 + (uint8_t)v8) & 1) != 0)\n return 4294967295LL;\n else\n return (unsigned int)(result + 2);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, long long a2) {\n int v4;\n long long v5;\n long long v6;\n int v7;\n int v8;\n char v9;\n long long result;\n v4 = strlen(a1);\n if (v4 <= 0) return 0LL;\n v5 = (unsigned int)(v4 - 1);\n v6 = 0LL;\n v7 = 0;\n v8 = 0;\n while (1) {\n v9 = a1[v6];\n if (v9 == 48) {\n if (*(uint8_t *)(a2 + v6) == 49) ++v8;\n } else if (v9 == 49 && *(uint8_t *)(a2 + v6) == 48) {\n ++v7;\n }\n if (v5 == v6) break;\n ++v6;\n }\n result = (unsigned int)(v7 / 2 + v8 / 2);\n if ((((unsigned char)v7 | (unsigned char)v8) & 1) != 0) {\n if ((((uint8_t)v7 + (uint8_t)v8) & 1) != 0)\n return 4294967295LL;\n else\n return (unsigned int)(result + 2);\n }\n return result;\n}" + }, + { + "index": 838, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *s1, const char *s2) {\n int c0 = 0;\n int c1 = 0;\n int length = strlen(s1);\n for (int i = 0; i < length; i++) {\n if (s1[i] == '0' && s2[i] == '1') {\n c0++;\n } else if (s1[i] == '1' && s2[i] == '0') {\n c1++;\n }\n }\n int result = c0 / 2 + c1 / 2;\n if (c0 % 2 == 0 && c1 % 2 == 0) {\n return result;\n } else if ((c0 + c1) % 2 == 0) {\n return result + 2;\n } else {\n return -1;\n }\n}", + "test": "int main() {\n\n assert(func0(\"0011\", \"1111\") == 1);\n\n assert(func0(\"00011\", \"01001\") == 2);\n\n assert(func0(\"111\", \"111\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsi,%rbp\npush %rbx\nmov %rdi,%rbx\nsub $0x8,%rsp\ncallq 1060 \ntest %eax,%eax\njle 12b0 \nlea -0x1(%rax),%edi\nxor %r8d,%r8d\nxor %eax,%eax\nxor %ecx,%ecx\njmp 1266 \nnopl (%rax)\ncmp $0x31,%dl\njne 125a \nxor %edx,%edx\ncmpb $0x30,0x0(%rbp,%rax,1)\nsete %dl\nadd %edx,%r8d\nlea 0x1(%rax),%rdx\ncmp %rax,%rdi\nje 1284 \nmov %rdx,%rax\nmovzbl (%rbx,%rax,1),%edx\ncmp $0x30,%dl\njne 1248 \nxor %edx,%edx\ncmpb $0x31,0x0(%rbp,%rax,1)\nsete %dl\nadd %edx,%ecx\nlea 0x1(%rax),%rdx\ncmp %rax,%rdi\njne 1263 \nmov %ecx,%eax\nmov %r8d,%edx\nsar %edx\nsar %eax\nadd %edx,%eax\nmov %ecx,%edx\nor %r8d,%edx\nand $0x1,%edx\nje 12a4 \nadd %r8d,%ecx\nand $0x1,%ecx\njne 12b9 \nadd $0x2,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopl 0x0(%rax,%rax,1)\nadd $0x8,%rsp\nxor %eax,%eax\npop %rbx\npop %rbp\nretq\nmov $0xffffffff,%eax\njmp 12a4 \n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsi\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\ntest eax, eax\njle loc_12C0\nlea ecx, [rax-1]\nxor edi, edi\nxor eax, eax\nxor esi, esi\njmp short loc_126C\nloc_1250:\ncmp dl, 31h ; '1'\njnz short loc_1260\ncmp byte ptr [rbp+rax+0], 30h ; '0'\njnz short loc_1260\nadd edi, 1\nnop\nloc_1260:\nlea rdx, [rax+1]\ncmp rax, rcx\njz short loc_1290\nloc_1269:\nmov rax, rdx\nloc_126C:\nmovzx edx, byte ptr [rbx+rax]\ncmp dl, 30h ; '0'\njnz short loc_1250\ncmp byte ptr [rbp+rax+0], 31h ; '1'\njnz short loc_1260\nadd esi, 1\nlea rdx, [rax+1]\ncmp rax, rcx\njnz short loc_1269\nnop dword ptr [rax+rax+00000000h]\nloc_1290:\nmov eax, esi\nmov edx, edi\nshr eax, 1Fh\nshr edx, 1Fh\nadd eax, esi\nadd edx, edi\nsar edx, 1\nsar eax, 1\nadd eax, edx\nmov edx, esi\nor edx, edi\nand edx, 1\njz short loc_12B7\nadd esi, edi\nand esi, 1\njnz short loc_12C9\nadd eax, 2\nloc_12B7:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_12C0:\nadd rsp, 8\nxor eax, eax\npop rbx\npop rbp\nretn\nloc_12C9:\nmov eax, 0FFFFFFFFh\njmp short loc_12B7", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, __int64 a2)\n{\n int v4; // eax\n __int64 v5; // rcx\n int v6; // edi\n __int64 v7; // rax\n int v8; // esi\n __int64 v9; // rdx\n char v10; // dl\n __int64 result; // rax\n\n v4 = strlen(a1);\n if ( v4 <= 0 )\n return 0LL;\n v5 = (unsigned int)(v4 - 1);\n v6 = 0;\n v7 = 0LL;\n v8 = 0;\n while ( 1 )\n {\n v10 = a1[v7];\n if ( v10 == 48 )\n break;\n if ( v10 == 49 && *(_BYTE *)(a2 + v7) == 48 )\n ++v6;\nLABEL_6:\n v9 = v7 + 1;\n if ( v7 == v5 )\n goto LABEL_11;\nLABEL_7:\n v7 = v9;\n }\n if ( *(_BYTE *)(a2 + v7) != 49 )\n goto LABEL_6;\n ++v8;\n v9 = v7 + 1;\n if ( v7 != v5 )\n goto LABEL_7;\nLABEL_11:\n result = (unsigned int)(v6 / 2 + v8 / 2);\n if ( (((unsigned __int8)v6 | (unsigned __int8)v8) & 1) != 0 )\n {\n if ( (((_BYTE)v6 + (_BYTE)v8) & 1) != 0 )\n return 0xFFFFFFFFLL;\n else\n return (unsigned int)(result + 2);\n }\n return result;\n}", + "ida_strip_asm": "sub_1220:\nendbr64\npush rbp\nmov rbp, rsi\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\ntest eax, eax\njle loc_12C0\nlea ecx, [rax-1]\nxor edi, edi\nxor eax, eax\nxor esi, esi\njmp short loc_126C\nloc_1250:\ncmp dl, 31h ; '1'\njnz short loc_1260\ncmp byte ptr [rbp+rax+0], 30h ; '0'\njnz short loc_1260\nadd edi, 1\nnop\nloc_1260:\nlea rdx, [rax+1]\ncmp rax, rcx\njz short loc_1290\nloc_1269:\nmov rax, rdx\nloc_126C:\nmovzx edx, byte ptr [rbx+rax]\ncmp dl, 30h ; '0'\njnz short loc_1250\ncmp byte ptr [rbp+rax+0], 31h ; '1'\njnz short loc_1260\nadd esi, 1\nlea rdx, [rax+1]\ncmp rax, rcx\njnz short loc_1269\nnop dword ptr [rax+rax+00000000h]\nloc_1290:\nmov eax, esi\nmov edx, edi\nshr eax, 1Fh\nshr edx, 1Fh\nadd eax, esi\nadd edx, edi\nsar edx, 1\nsar eax, 1\nadd eax, edx\nmov edx, esi\nor edx, edi\nand edx, 1\njz short loc_12B7\nadd esi, edi\nand esi, 1\njnz short loc_12C9\nadd eax, 2\nloc_12B7:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_12C0:\nadd rsp, 8\nxor eax, eax\npop rbx\npop rbp\nretn\nloc_12C9:\nmov eax, 0FFFFFFFFh\njmp short loc_12B7", + "ida_strip_pseudo": "__int64 __fastcall sub_1220(const char *a1, __int64 a2)\n{\n int v4; // eax\n __int64 v5; // rcx\n int v6; // edi\n __int64 v7; // rax\n int v8; // esi\n __int64 v9; // rdx\n char v10; // dl\n __int64 result; // rax\n\n v4 = strlen(a1);\n if ( v4 <= 0 )\n return 0LL;\n v5 = (unsigned int)(v4 - 1);\n v6 = 0;\n v7 = 0LL;\n v8 = 0;\n while ( 1 )\n {\n v10 = a1[v7];\n if ( v10 == 48 )\n break;\n if ( v10 == 49 && *(_BYTE *)(a2 + v7) == 48 )\n ++v6;\nLABEL_6:\n v9 = v7 + 1;\n if ( v7 == v5 )\n goto LABEL_11;\nLABEL_7:\n v7 = v9;\n }\n if ( *(_BYTE *)(a2 + v7) != 49 )\n goto LABEL_6;\n ++v8;\n v9 = v7 + 1;\n if ( v7 != v5 )\n goto LABEL_7;\nLABEL_11:\n result = (unsigned int)(v6 / 2 + v8 / 2);\n if ( (((unsigned __int8)v6 | (unsigned __int8)v8) & 1) != 0 )\n {\n if ( (((_BYTE)v6 + (_BYTE)v8) & 1) != 0 )\n return 0xFFFFFFFFLL;\n else\n return (unsigned int)(result + 2);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1220(const char *a1, long long a2) {\n int v4;\n long long v5;\n int v6;\n long long v7;\n int v8;\n long long v9;\n char v10;\n long long result;\n v4 = strlen(a1);\n if (v4 <= 0) return 0LL;\n v5 = (unsigned int)(v4 - 1);\n v6 = 0;\n v7 = 0LL;\n v8 = 0;\n while (1) {\n v10 = a1[v7];\n if (v10 == 48) break;\n if (v10 == 49 && *(uint8_t *)(a2 + v7) == 48) ++v6;\n LABEL_6:\n v9 = v7 + 1;\n if (v7 == v5) goto LABEL_11;\n LABEL_7:\n v7 = v9;\n }\n if (*(uint8_t *)(a2 + v7) != 49) goto LABEL_6;\n ++v8;\n v9 = v7 + 1;\n if (v7 != v5) goto LABEL_7;\nLABEL_11:\n result = (unsigned int)(v6 / 2 + v8 / 2);\n if ((((unsigned char)v6 | (unsigned char)v8) & 1) != 0) {\n if ((((uint8_t)v6 + (uint8_t)v8) & 1) != 0)\n return 4294967295LL;\n else\n return (unsigned int)(result + 2);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, long long a2) {\n int v4;\n long long v5;\n int v6;\n long long v7;\n int v8;\n long long v9;\n char v10;\n long long result;\n v4 = strlen(a1);\n if (v4 <= 0) return 0LL;\n v5 = (unsigned int)(v4 - 1);\n v6 = 0;\n v7 = 0LL;\n v8 = 0;\n while (1) {\n v10 = a1[v7];\n if (v10 == 48) break;\n if (v10 == 49 && *(uint8_t *)(a2 + v7) == 48) ++v6;\n LABEL_6:\n v9 = v7 + 1;\n if (v7 == v5) goto LABEL_11;\n LABEL_7:\n v7 = v9;\n }\n if (*(uint8_t *)(a2 + v7) != 49) goto LABEL_6;\n ++v8;\n v9 = v7 + 1;\n if (v7 != v5) goto LABEL_7;\nLABEL_11:\n result = (unsigned int)(v6 / 2 + v8 / 2);\n if ((((unsigned char)v6 | (unsigned char)v8) & 1) != 0) {\n if ((((uint8_t)v6 + (uint8_t)v8) & 1) != 0)\n return 4294967295LL;\n else\n return (unsigned int)(result + 2);\n }\n return result;\n}" + }, + { + "index": 838, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *s1, const char *s2) {\n int c0 = 0;\n int c1 = 0;\n int length = strlen(s1);\n for (int i = 0; i < length; i++) {\n if (s1[i] == '0' && s2[i] == '1') {\n c0++;\n } else if (s1[i] == '1' && s2[i] == '0') {\n c1++;\n }\n }\n int result = c0 / 2 + c1 / 2;\n if (c0 % 2 == 0 && c1 % 2 == 0) {\n return result;\n } else if ((c0 + c1) % 2 == 0) {\n return result + 2;\n } else {\n return -1;\n }\n}", + "test": "int main() {\n\n assert(func0(\"0011\", \"1111\") == 1);\n\n assert(func0(\"00011\", \"01001\") == 2);\n\n assert(func0(\"111\", \"111\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsi,%rbp\npush %rbx\nmov %rdi,%rbx\nsub $0x8,%rsp\ncallq 1060 \ntest %eax,%eax\njle 12b0 \nlea -0x1(%rax),%edi\nxor %r8d,%r8d\nxor %eax,%eax\nxor %ecx,%ecx\njmp 1266 \nnopl (%rax)\ncmp $0x31,%dl\njne 125a \nxor %edx,%edx\ncmpb $0x30,0x0(%rbp,%rax,1)\nsete %dl\nadd %edx,%r8d\nlea 0x1(%rax),%rdx\ncmp %rax,%rdi\nje 1284 \nmov %rdx,%rax\nmovzbl (%rbx,%rax,1),%edx\ncmp $0x30,%dl\njne 1248 \nxor %edx,%edx\ncmpb $0x31,0x0(%rbp,%rax,1)\nsete %dl\nadd %edx,%ecx\nlea 0x1(%rax),%rdx\ncmp %rax,%rdi\njne 1263 \nmov %ecx,%eax\nmov %r8d,%edx\nsar %edx\nsar %eax\nadd %edx,%eax\nmov %ecx,%edx\nor %r8d,%edx\nand $0x1,%edx\nje 12a4 \nadd %r8d,%ecx\nand $0x1,%ecx\njne 12b9 \nadd $0x2,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopl 0x0(%rax,%rax,1)\nadd $0x8,%rsp\nxor %eax,%eax\npop %rbx\npop %rbp\nretq\nmov $0xffffffff,%eax\njmp 12a4 \n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsi\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\ntest eax, eax\njle loc_12C0\nlea ecx, [rax-1]\nxor edi, edi\nxor eax, eax\nxor esi, esi\njmp short loc_126C\nloc_1250:\ncmp dl, 31h ; '1'\njnz short loc_1260\ncmp byte ptr [rbp+rax+0], 30h ; '0'\njnz short loc_1260\nadd edi, 1\nnop\nloc_1260:\nlea rdx, [rax+1]\ncmp rax, rcx\njz short loc_1290\nloc_1269:\nmov rax, rdx\nloc_126C:\nmovzx edx, byte ptr [rbx+rax]\ncmp dl, 30h ; '0'\njnz short loc_1250\ncmp byte ptr [rbp+rax+0], 31h ; '1'\njnz short loc_1260\nadd esi, 1\nlea rdx, [rax+1]\ncmp rax, rcx\njnz short loc_1269\nnop dword ptr [rax+rax+00000000h]\nloc_1290:\nmov eax, esi\nmov edx, edi\nshr eax, 1Fh\nshr edx, 1Fh\nadd eax, esi\nadd edx, edi\nsar edx, 1\nsar eax, 1\nadd eax, edx\nmov edx, esi\nor edx, edi\nand edx, 1\njz short loc_12B7\nadd esi, edi\nand esi, 1\njnz short loc_12C9\nadd eax, 2\nloc_12B7:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_12C0:\nadd rsp, 8\nxor eax, eax\npop rbx\npop rbp\nretn\nloc_12C9:\nmov eax, 0FFFFFFFFh\njmp short loc_12B7", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, __int64 a2)\n{\n int v4; // eax\n __int64 v5; // rcx\n int v6; // edi\n __int64 v7; // rax\n int v8; // esi\n __int64 v9; // rdx\n char v10; // dl\n __int64 result; // rax\n\n v4 = strlen(a1);\n if ( v4 <= 0 )\n return 0LL;\n v5 = (unsigned int)(v4 - 1);\n v6 = 0;\n v7 = 0LL;\n v8 = 0;\n while ( 1 )\n {\n v10 = a1[v7];\n if ( v10 == 48 )\n break;\n if ( v10 == 49 && *(_BYTE *)(a2 + v7) == 48 )\n ++v6;\nLABEL_6:\n v9 = v7 + 1;\n if ( v7 == v5 )\n goto LABEL_11;\nLABEL_7:\n v7 = v9;\n }\n if ( *(_BYTE *)(a2 + v7) != 49 )\n goto LABEL_6;\n ++v8;\n v9 = v7 + 1;\n if ( v7 != v5 )\n goto LABEL_7;\nLABEL_11:\n result = (unsigned int)(v6 / 2 + v8 / 2);\n if ( (((unsigned __int8)v6 | (unsigned __int8)v8) & 1) != 0 )\n {\n if ( (((_BYTE)v6 + (_BYTE)v8) & 1) != 0 )\n return 0xFFFFFFFFLL;\n else\n return (unsigned int)(result + 2);\n }\n return result;\n}", + "ida_strip_asm": "sub_1220:\nendbr64\npush rbp\nmov rbp, rsi\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\ntest eax, eax\njle loc_12C0\nlea ecx, [rax-1]\nxor edi, edi\nxor eax, eax\nxor esi, esi\njmp short loc_126C\nloc_1250:\ncmp dl, 31h ; '1'\njnz short loc_1260\ncmp byte ptr [rbp+rax+0], 30h ; '0'\njnz short loc_1260\nadd edi, 1\nnop\nloc_1260:\nlea rdx, [rax+1]\ncmp rax, rcx\njz short loc_1290\nloc_1269:\nmov rax, rdx\nloc_126C:\nmovzx edx, byte ptr [rbx+rax]\ncmp dl, 30h ; '0'\njnz short loc_1250\ncmp byte ptr [rbp+rax+0], 31h ; '1'\njnz short loc_1260\nadd esi, 1\nlea rdx, [rax+1]\ncmp rax, rcx\njnz short loc_1269\nnop dword ptr [rax+rax+00000000h]\nloc_1290:\nmov eax, esi\nmov edx, edi\nshr eax, 1Fh\nshr edx, 1Fh\nadd eax, esi\nadd edx, edi\nsar edx, 1\nsar eax, 1\nadd eax, edx\nmov edx, esi\nor edx, edi\nand edx, 1\njz short loc_12B7\nadd esi, edi\nand esi, 1\njnz short loc_12C9\nadd eax, 2\nloc_12B7:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_12C0:\nadd rsp, 8\nxor eax, eax\npop rbx\npop rbp\nretn\nloc_12C9:\nmov eax, 0FFFFFFFFh\njmp short loc_12B7", + "ida_strip_pseudo": "__int64 __fastcall sub_1220(const char *a1, __int64 a2)\n{\n int v4; // eax\n __int64 v5; // rcx\n int v6; // edi\n __int64 v7; // rax\n int v8; // esi\n __int64 v9; // rdx\n char v10; // dl\n __int64 result; // rax\n\n v4 = strlen(a1);\n if ( v4 <= 0 )\n return 0LL;\n v5 = (unsigned int)(v4 - 1);\n v6 = 0;\n v7 = 0LL;\n v8 = 0;\n while ( 1 )\n {\n v10 = a1[v7];\n if ( v10 == 48 )\n break;\n if ( v10 == 49 && *(_BYTE *)(a2 + v7) == 48 )\n ++v6;\nLABEL_6:\n v9 = v7 + 1;\n if ( v7 == v5 )\n goto LABEL_11;\nLABEL_7:\n v7 = v9;\n }\n if ( *(_BYTE *)(a2 + v7) != 49 )\n goto LABEL_6;\n ++v8;\n v9 = v7 + 1;\n if ( v7 != v5 )\n goto LABEL_7;\nLABEL_11:\n result = (unsigned int)(v6 / 2 + v8 / 2);\n if ( (((unsigned __int8)v6 | (unsigned __int8)v8) & 1) != 0 )\n {\n if ( (((_BYTE)v6 + (_BYTE)v8) & 1) != 0 )\n return 0xFFFFFFFFLL;\n else\n return (unsigned int)(result + 2);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1220(const char *a1, long long a2) {\n int v4;\n long long v5;\n int v6;\n long long v7;\n int v8;\n long long v9;\n char v10;\n long long result;\n v4 = strlen(a1);\n if (v4 <= 0) return 0LL;\n v5 = (unsigned int)(v4 - 1);\n v6 = 0;\n v7 = 0LL;\n v8 = 0;\n while (1) {\n v10 = a1[v7];\n if (v10 == 48) break;\n if (v10 == 49 && *(uint8_t *)(a2 + v7) == 48) ++v6;\n LABEL_6:\n v9 = v7 + 1;\n if (v7 == v5) goto LABEL_11;\n LABEL_7:\n v7 = v9;\n }\n if (*(uint8_t *)(a2 + v7) != 49) goto LABEL_6;\n ++v8;\n v9 = v7 + 1;\n if (v7 != v5) goto LABEL_7;\nLABEL_11:\n result = (unsigned int)(v6 / 2 + v8 / 2);\n if ((((unsigned char)v6 | (unsigned char)v8) & 1) != 0) {\n if ((((uint8_t)v6 + (uint8_t)v8) & 1) != 0)\n return 4294967295LL;\n else\n return (unsigned int)(result + 2);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, long long a2) {\n int v4;\n long long v5;\n int v6;\n long long v7;\n int v8;\n long long v9;\n char v10;\n long long result;\n v4 = strlen(a1);\n if (v4 <= 0) return 0LL;\n v5 = (unsigned int)(v4 - 1);\n v6 = 0;\n v7 = 0LL;\n v8 = 0;\n while (1) {\n v10 = a1[v7];\n if (v10 == 48) break;\n if (v10 == 49 && *(uint8_t *)(a2 + v7) == 48) ++v6;\n LABEL_6:\n v9 = v7 + 1;\n if (v7 == v5) goto LABEL_11;\n LABEL_7:\n v7 = v9;\n }\n if (*(uint8_t *)(a2 + v7) != 49) goto LABEL_6;\n ++v8;\n v9 = v7 + 1;\n if (v7 != v5) goto LABEL_7;\nLABEL_11:\n result = (unsigned int)(v6 / 2 + v8 / 2);\n if ((((unsigned char)v6 | (unsigned char)v8) & 1) != 0) {\n if ((((uint8_t)v6 + (uint8_t)v8) & 1) != 0)\n return 4294967295LL;\n else\n return (unsigned int)(result + 2);\n }\n return result;\n}" + }, + { + "index": 839, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char* first;\n\n char* second;\n\n} tuple;\n\n\n\n", + "func": "tuple* func0(tuple arr[], int n) {\n for (int i = 0; i < n; i++) {\n for (int j = 0; j < n - i - 1; j++) {\n if (strcmp(arr[j].first, arr[j + 1].first) > 0) {\n tuple temp = arr[j];\n arr[j] = arr[j + 1];\n arr[j + 1] = temp;\n }\n }\n }\n return arr;\n}", + "test": "int main() {\n\n // Test case 1\n\n tuple test1[] = {{\"Amana\", \"28\"}, {\"Zenat\", \"30\"}, {\"Abhishek\", \"29\"}, {\"Nikhil\", \"21\"}, {\"B\", \"C\"}};\n\n tuple expected1[] = {{\"Abhishek\", \"29\"}, {\"Amana\", \"28\"}, {\"B\", \"C\"}, {\"Nikhil\", \"21\"}, {\"Zenat\", \"30\"}};\n\n func0(test1, 5);\n\n for(int i = 0; i < 5; i++) {\n\n assert(strcmp(test1[i].first, expected1[i].first) == 0);\n\n assert(strcmp(test1[i].second, expected1[i].second) == 0);\n\n }\n\n\n\n // Test case 2\n\n tuple test2[] = {{\"aaaa\", \"28\"}, {\"aa\", \"30\"}, {\"bab\", \"29\"}, {\"bb\", \"21\"}, {\"csa\", \"C\"}};\n\n tuple expected2[] = {{\"aa\", \"30\"}, {\"aaaa\", \"28\"}, {\"bab\", \"29\"}, {\"bb\", \"21\"}, {\"csa\", \"C\"}};\n\n func0(test2, 5);\n\n for(int i = 0; i < 5; i++) {\n\n assert(strcmp(test2[i].first, expected2[i].first) == 0);\n\n assert(strcmp(test2[i].second, expected2[i].second) == 0);\n\n }\n\n\n\n // Test case 3\n\n tuple test3[] = {{\"Sarala\", \"28\"}, {\"Ayesha\", \"30\"}, {\"Suman\", \"29\"}, {\"Sai\", \"21\"}, {\"G\", \"H\"}};\n\n tuple expected3[] = {{\"Ayesha\", \"30\"}, {\"G\", \"H\"}, {\"Sai\", \"21\"}, {\"Sarala\", \"28\"}, {\"Suman\", \"29\"}};\n\n func0(test3, 5);\n\n for(int i = 0; i < 5; i++) {\n\n assert(strcmp(test3[i].first, expected3[i].first) == 0);\n\n assert(strcmp(test3[i].second, expected3[i].second) == 0);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmovl $0x0,-0x18(%rbp)\njmpq 1293 \nmovl $0x0,-0x14(%rbp)\njmpq 127d \nmov -0x14(%rbp),%eax\ncltq\nadd $0x1,%rax\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rdx\nmov -0x14(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1090 \ntest %eax,%eax\njle 1279 \nmov -0x14(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov 0x8(%rax),%rdx\nmov (%rax),%rax\nmov %rax,-0x10(%rbp)\nmov %rdx,-0x8(%rbp)\nmov -0x14(%rbp),%eax\ncltq\nadd $0x1,%rax\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov -0x14(%rbp),%edx\nmovslq %edx,%rdx\nmov %rdx,%rcx\nshl $0x4,%rcx\nmov -0x28(%rbp),%rdx\nadd %rdx,%rcx\nmov 0x8(%rax),%rdx\nmov (%rax),%rax\nmov %rax,(%rcx)\nmov %rdx,0x8(%rcx)\nmov -0x14(%rbp),%eax\ncltq\nadd $0x1,%rax\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x28(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x10(%rbp),%rax\nmov -0x8(%rbp),%rdx\nmov %rax,(%rcx)\nmov %rdx,0x8(%rcx)\naddl $0x1,-0x14(%rbp)\nmov -0x2c(%rbp),%eax\nsub -0x18(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x14(%rbp)\njl 11b4 \naddl $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 11a8 \nmov -0x28(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_18], 0\njmp loc_1293\nloc_11A8:\nmov [rbp+var_14], 0\njmp loc_127D\nloc_11B4:\nmov eax, [rbp+var_14]\ncdqe\nadd rax, 1\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_14]\ncdqe\nshl rax, 4\nmov rcx, rax\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njle loc_1279\nmov eax, [rbp+var_14]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rdx, [rax+8]\nmov rax, [rax]\nmov [rbp+var_10], rax\nmov [rbp+var_8], rdx\nmov eax, [rbp+var_14]\ncdqe\nadd rax, 1\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nmov rcx, rdx\nshl rcx, 4\nmov rdx, [rbp+var_28]\nadd rcx, rdx\nmov rdx, [rax+8]\nmov rax, [rax]\nmov [rcx], rax\nmov [rcx+8], rdx\nmov eax, [rbp+var_14]\ncdqe\nadd rax, 1\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov rax, [rbp+var_10]\nmov rdx, [rbp+var_8]\nmov [rcx], rax\nmov [rcx+8], rdx\nloc_1279:\nadd [rbp+var_14], 1\nloc_127D:\nmov eax, [rbp+var_2C]\nsub eax, [rbp+var_18]\nsub eax, 1\ncmp [rbp+var_14], eax\njl loc_11B4\nadd [rbp+var_18], 1\nloc_1293:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_2C]\njl loc_11A8\nmov rax, [rbp+var_28]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 *v2; // rax\n _QWORD *v3; // rax\n _QWORD *v4; // rcx\n __int64 v5; // rdx\n int i; // [rsp+18h] [rbp-18h]\n int j; // [rsp+1Ch] [rbp-14h]\n __int64 v9; // [rsp+20h] [rbp-10h]\n __int64 v10; // [rsp+28h] [rbp-8h]\n\n for ( i = 0; i < a2; ++i )\n {\n for ( j = 0; j < a2 - i - 1; ++j )\n {\n if ( strcmp(*(const char **)(16LL * j + a1), *(const char **)(16 * (j + 1LL) + a1)) > 0 )\n {\n v2 = (__int64 *)(16LL * j + a1);\n v9 = *v2;\n v10 = v2[1];\n v3 = (_QWORD *)(16 * (j + 1LL) + a1);\n v4 = (_QWORD *)(a1 + 16LL * j);\n v5 = v3[1];\n *v4 = *v3;\n v4[1] = v5;\n *v3 = v9;\n v3[1] = v10;\n }\n }\n }\n return a1;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_18], 0\njmp loc_1293\nloc_11A8:\nmov [rbp+var_14], 0\njmp loc_127D\nloc_11B4:\nmov eax, [rbp+var_14]\ncdqe\nadd rax, 1\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_14]\ncdqe\nshl rax, 4\nmov rcx, rax\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njle loc_1279\nmov eax, [rbp+var_14]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rdx, [rax+8]\nmov rax, [rax]\nmov [rbp+var_10], rax\nmov [rbp+var_8], rdx\nmov eax, [rbp+var_14]\ncdqe\nadd rax, 1\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nmov rcx, rdx\nshl rcx, 4\nmov rdx, [rbp+var_28]\nadd rcx, rdx\nmov rdx, [rax+8]\nmov rax, [rax]\nmov [rcx], rax\nmov [rcx+8], rdx\nmov eax, [rbp+var_14]\ncdqe\nadd rax, 1\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov rax, [rbp+var_10]\nmov rdx, [rbp+var_8]\nmov [rcx], rax\nmov [rcx+8], rdx\nloc_1279:\nadd [rbp+var_14], 1\nloc_127D:\nmov eax, [rbp+var_2C]\nsub eax, [rbp+var_18]\nsub eax, 1\ncmp [rbp+var_14], eax\njl loc_11B4\nadd [rbp+var_18], 1\nloc_1293:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_2C]\njl loc_11A8\nmov rax, [rbp+var_28]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2)\n{\n __int64 *v2; // rax\n _QWORD *v3; // rax\n _QWORD *v4; // rcx\n __int64 v5; // rdx\n int i; // [rsp+18h] [rbp-18h]\n int j; // [rsp+1Ch] [rbp-14h]\n __int64 v9; // [rsp+20h] [rbp-10h]\n __int64 v10; // [rsp+28h] [rbp-8h]\n\n for ( i = 0; i < a2; ++i )\n {\n for ( j = 0; j < a2 - i - 1; ++j )\n {\n if ( strcmp(*(const char **)(16LL * j + a1), *(const char **)(16 * (j + 1LL) + a1)) > 0 )\n {\n v2 = (__int64 *)(16LL * j + a1);\n v9 = *v2;\n v10 = v2[1];\n v3 = (_QWORD *)(16 * (j + 1LL) + a1);\n v4 = (_QWORD *)(a1 + 16LL * j);\n v5 = v3[1];\n *v4 = *v3;\n v4[1] = v5;\n *v3 = v9;\n v3[1] = v10;\n }\n }\n }\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2) {\n long long *v2;\n uint64_t *v3;\n uint64_t *v4;\n long long v5;\n int i;\n int j;\n long long v9;\n long long v10;\n for (i = 0; i < a2; ++i) {\n for (j = 0; j < a2 - i - 1; ++j) {\n if (strcmp(*(const char **)(16LL * j + a1),\n *(const char **)(16 * (j + 1LL) + a1)) > 0) {\n v2 = (long long *)(16LL * j + a1);\n v9 = *v2;\n v10 = v2[1];\n v3 = (uint64_t *)(16 * (j + 1LL) + a1);\n v4 = (uint64_t *)(a1 + 16LL * j);\n v5 = v3[1];\n *v4 = *v3;\n v4[1] = v5;\n *v3 = v9;\n v3[1] = v10;\n }\n }\n }\n return a1;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long *v2;\n uint64_t *v3;\n uint64_t *v4;\n long long v5;\n int i;\n int j;\n long long v9;\n long long v10;\n for (i = 0; i < a2; ++i) {\n for (j = 0; j < a2 - i - 1; ++j) {\n if (strcmp(*(const char **)(16LL * j + a1),\n *(const char **)(16 * (j + 1LL) + a1)) > 0) {\n v2 = (long long *)(16LL * j + a1);\n v9 = *v2;\n v10 = v2[1];\n v3 = (uint64_t *)(16 * (j + 1LL) + a1);\n v4 = (uint64_t *)(a1 + 16LL * j);\n v5 = v3[1];\n *v4 = *v3;\n v4[1] = v5;\n *v3 = v9;\n v3[1] = v10;\n }\n }\n }\n return a1;\n}" + }, + { + "index": 839, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char* first;\n\n char* second;\n\n} tuple;\n\n\n\n", + "func": "tuple* func0(tuple arr[], int n) {\n for (int i = 0; i < n; i++) {\n for (int j = 0; j < n - i - 1; j++) {\n if (strcmp(arr[j].first, arr[j + 1].first) > 0) {\n tuple temp = arr[j];\n arr[j] = arr[j + 1];\n arr[j + 1] = temp;\n }\n }\n }\n return arr;\n}", + "test": "int main() {\n\n // Test case 1\n\n tuple test1[] = {{\"Amana\", \"28\"}, {\"Zenat\", \"30\"}, {\"Abhishek\", \"29\"}, {\"Nikhil\", \"21\"}, {\"B\", \"C\"}};\n\n tuple expected1[] = {{\"Abhishek\", \"29\"}, {\"Amana\", \"28\"}, {\"B\", \"C\"}, {\"Nikhil\", \"21\"}, {\"Zenat\", \"30\"}};\n\n func0(test1, 5);\n\n for(int i = 0; i < 5; i++) {\n\n assert(strcmp(test1[i].first, expected1[i].first) == 0);\n\n assert(strcmp(test1[i].second, expected1[i].second) == 0);\n\n }\n\n\n\n // Test case 2\n\n tuple test2[] = {{\"aaaa\", \"28\"}, {\"aa\", \"30\"}, {\"bab\", \"29\"}, {\"bb\", \"21\"}, {\"csa\", \"C\"}};\n\n tuple expected2[] = {{\"aa\", \"30\"}, {\"aaaa\", \"28\"}, {\"bab\", \"29\"}, {\"bb\", \"21\"}, {\"csa\", \"C\"}};\n\n func0(test2, 5);\n\n for(int i = 0; i < 5; i++) {\n\n assert(strcmp(test2[i].first, expected2[i].first) == 0);\n\n assert(strcmp(test2[i].second, expected2[i].second) == 0);\n\n }\n\n\n\n // Test case 3\n\n tuple test3[] = {{\"Sarala\", \"28\"}, {\"Ayesha\", \"30\"}, {\"Suman\", \"29\"}, {\"Sai\", \"21\"}, {\"G\", \"H\"}};\n\n tuple expected3[] = {{\"Ayesha\", \"30\"}, {\"G\", \"H\"}, {\"Sai\", \"21\"}, {\"Sarala\", \"28\"}, {\"Suman\", \"29\"}};\n\n func0(test3, 5);\n\n for(int i = 0; i < 5; i++) {\n\n assert(strcmp(test3[i].first, expected3[i].first) == 0);\n\n assert(strcmp(test3[i].second, expected3[i].second) == 0);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%r14\ntest %esi,%esi\njle 11e8 \nlea -0x1(%rsi),%r13d\nlea 0x10(%rdi),%r15\njmp 11fe \nadd $0x10,%rbx\ncmp %r12,%rbx\nje 11fa \nmov (%rbx),%rbp\nmov 0x10(%rbx),%rsi\nmov %rbp,%rdi\ncallq 1090 \ntest %eax,%eax\njle 11ac \nmov 0x8(%rbx),%rax\nmovdqu 0x10(%rbx),%xmm0\nmovups %xmm0,(%rbx)\nmov %rbp,0x10(%rbx)\nmov %rax,0x18(%rbx)\njmp 11ac \nsub $0x1,%r13d\ncmp $0xffffffff,%r13d\njne 11fe \nmov %r14,%rax\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nsub $0x1,%r13d\ntest %r13d,%r13d\njle 11de \nmov %r14,%rbx\nlea -0x1(%r13),%r12d\nshl $0x4,%r12\nadd %r15,%r12\njmp 11b5 \n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r14, rdi\ntest esi, esi\njle short loc_11E3\nmov r13d, esi\nlea r15, [rdi+10h]\njmp short loc_11F9\nloc_11AB:\nadd rbx, 10h\ncmp rbx, r12\njz short loc_11F5\nloc_11B4:\nmov rbp, [rbx]\nmov rsi, [rbx+10h]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njle short loc_11AB\nmov rax, [rbx+8]\nmovdqu xmm0, xmmword ptr [rbx+10h]\nmovups xmmword ptr [rbx], xmm0\nmov [rbx+10h], rbp\nmov [rbx+18h], rax\njmp short loc_11AB\nloc_11DD:\nsub r13d, 1\njnz short loc_11F9\nloc_11E3:\nmov rax, r14\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_11F5:\nsub r13d, 1\nloc_11F9:\ncmp r13d, 1\njle short loc_11DD\nmov rbx, r14\nlea r12d, [r13-2]\nshl r12, 4\nadd r12, r15\njmp short loc_11B4", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int v2; // r13d\n __int64 v3; // rbx\n const char *v4; // rbp\n __int64 v5; // rax\n\n if ( a2 > 0 )\n {\n v2 = a2;\n do\n {\n while ( v2 > 1 )\n {\n v3 = a1;\n do\n {\n v4 = *(const char **)v3;\n if ( strcmp(*(const char **)v3, *(const char **)(v3 + 16)) > 0 )\n {\n v5 = *(_QWORD *)(v3 + 8);\n *(__m128i *)v3 = _mm_loadu_si128((const __m128i *)(v3 + 16));\n *(_QWORD *)(v3 + 16) = v4;\n *(_QWORD *)(v3 + 24) = v5;\n }\n v3 += 16LL;\n }\n while ( v3 != a1 + 16 + 16LL * (unsigned int)(v2 - 2) );\n --v2;\n }\n --v2;\n }\n while ( v2 );\n }\n return a1;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r14, rdi\ntest esi, esi\njle short loc_11E3\nmov r13d, esi\nlea r15, [rdi+10h]\njmp short loc_11F9\nloc_11AB:\nadd rbx, 10h\ncmp rbx, r12\njz short loc_11F5\nloc_11B4:\nmov rbp, [rbx]\nmov rsi, [rbx+10h]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njle short loc_11AB\nmov rax, [rbx+8]\nmovdqu xmm0, xmmword ptr [rbx+10h]\nmovups xmmword ptr [rbx], xmm0\nmov [rbx+10h], rbp\nmov [rbx+18h], rax\njmp short loc_11AB\nloc_11DD:\nsub r13d, 1\njnz short loc_11F9\nloc_11E3:\nmov rax, r14\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_11F5:\nsub r13d, 1\nloc_11F9:\ncmp r13d, 1\njle short loc_11DD\nmov rbx, r14\nlea r12d, [r13-2]\nshl r12, 4\nadd r12, r15\njmp short loc_11B4", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2)\n{\n int v2; // r13d\n __int64 v3; // rbx\n const char *v4; // rbp\n __int64 v5; // rax\n\n if ( a2 > 0 )\n {\n v2 = a2;\n do\n {\n while ( v2 > 1 )\n {\n v3 = a1;\n do\n {\n v4 = *(const char **)v3;\n if ( strcmp(*(const char **)v3, *(const char **)(v3 + 16)) > 0 )\n {\n v5 = *(_QWORD *)(v3 + 8);\n *(__m128i *)v3 = _mm_loadu_si128((const __m128i *)(v3 + 16));\n *(_QWORD *)(v3 + 16) = v4;\n *(_QWORD *)(v3 + 24) = v5;\n }\n v3 += 16LL;\n }\n while ( v3 != a1 + 16 + 16LL * (unsigned int)(v2 - 2) );\n --v2;\n }\n --v2;\n }\n while ( v2 );\n }\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2) {\n int v2;\n long long v3;\n const char *v4;\n long long v5;\n if (a2 > 0) {\n v2 = a2;\n do {\n while (v2 > 1) {\n v3 = a1;\n do {\n v4 = *(const char **)v3;\n if (strcmp(*(const char **)v3, *(const char **)(v3 + 16)) > 0) {\n v5 = *(uint64_t *)(v3 + 8);\n *(__m128i *)v3 = _mm_loadu_si128((const __m128i *)(v3 + 16));\n *(uint64_t *)(v3 + 16) = v4;\n *(uint64_t *)(v3 + 24) = v5;\n }\n v3 += 16LL;\n } while (v3 != a1 + 16 + 16LL * (unsigned int)(v2 - 2));\n --v2;\n }\n --v2;\n } while (v2);\n }\n return a1;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int v2;\n long long v3;\n const char *v4;\n long long v5;\n if (a2 > 0) {\n v2 = a2;\n do {\n while (v2 > 1) {\n v3 = a1;\n do {\n v4 = *(const char **)v3;\n if (strcmp(*(const char **)v3, *(const char **)(v3 + 16)) > 0) {\n v5 = *(uint64_t *)(v3 + 8);\n *(__m128i *)v3 = _mm_loadu_si128((const __m128i *)(v3 + 16));\n *(uint64_t *)(v3 + 16) = v4;\n *(uint64_t *)(v3 + 24) = v5;\n }\n v3 += 16LL;\n } while (v3 != a1 + 16 + 16LL * (unsigned int)(v2 - 2));\n --v2;\n }\n --v2;\n } while (v2);\n }\n return a1;\n}" + }, + { + "index": 839, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char* first;\n\n char* second;\n\n} tuple;\n\n\n\n", + "func": "tuple* func0(tuple arr[], int n) {\n for (int i = 0; i < n; i++) {\n for (int j = 0; j < n - i - 1; j++) {\n if (strcmp(arr[j].first, arr[j + 1].first) > 0) {\n tuple temp = arr[j];\n arr[j] = arr[j + 1];\n arr[j + 1] = temp;\n }\n }\n }\n return arr;\n}", + "test": "int main() {\n\n // Test case 1\n\n tuple test1[] = {{\"Amana\", \"28\"}, {\"Zenat\", \"30\"}, {\"Abhishek\", \"29\"}, {\"Nikhil\", \"21\"}, {\"B\", \"C\"}};\n\n tuple expected1[] = {{\"Abhishek\", \"29\"}, {\"Amana\", \"28\"}, {\"B\", \"C\"}, {\"Nikhil\", \"21\"}, {\"Zenat\", \"30\"}};\n\n func0(test1, 5);\n\n for(int i = 0; i < 5; i++) {\n\n assert(strcmp(test1[i].first, expected1[i].first) == 0);\n\n assert(strcmp(test1[i].second, expected1[i].second) == 0);\n\n }\n\n\n\n // Test case 2\n\n tuple test2[] = {{\"aaaa\", \"28\"}, {\"aa\", \"30\"}, {\"bab\", \"29\"}, {\"bb\", \"21\"}, {\"csa\", \"C\"}};\n\n tuple expected2[] = {{\"aa\", \"30\"}, {\"aaaa\", \"28\"}, {\"bab\", \"29\"}, {\"bb\", \"21\"}, {\"csa\", \"C\"}};\n\n func0(test2, 5);\n\n for(int i = 0; i < 5; i++) {\n\n assert(strcmp(test2[i].first, expected2[i].first) == 0);\n\n assert(strcmp(test2[i].second, expected2[i].second) == 0);\n\n }\n\n\n\n // Test case 3\n\n tuple test3[] = {{\"Sarala\", \"28\"}, {\"Ayesha\", \"30\"}, {\"Suman\", \"29\"}, {\"Sai\", \"21\"}, {\"G\", \"H\"}};\n\n tuple expected3[] = {{\"Ayesha\", \"30\"}, {\"G\", \"H\"}, {\"Sai\", \"21\"}, {\"Sarala\", \"28\"}, {\"Suman\", \"29\"}};\n\n func0(test3, 5);\n\n for(int i = 0; i < 5; i++) {\n\n assert(strcmp(test3[i].first, expected3[i].first) == 0);\n\n assert(strcmp(test3[i].second, expected3[i].second) == 0);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\nmov %rdi,%r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\ntest %esi,%esi\njle 167d \nmov %esi,%r13d\nlea 0x10(%rdi),%r15\nsub $0x1,%r13d\ntest %r13d,%r13d\nje 167d \nnopl 0x0(%rax)\nlea -0x1(%r13),%r12d\nmov %r14,%rbx\nmov %r12,%r13\nshl $0x4,%r12\nadd %r15,%r12\nnopl 0x0(%rax)\nmov (%rbx),%rbp\nmov 0x10(%rbx),%rsi\nmov %rbp,%rdi\ncallq 1090 \ntest %eax,%eax\njle 166f \nmov 0x8(%rbx),%rax\nmovdqu 0x10(%rbx),%xmm0\nmov %rbp,0x10(%rbx)\nmov %rax,0x18(%rbx)\nmovups %xmm0,(%rbx)\nadd $0x10,%rbx\ncmp %r12,%rbx\njne 1648 \ntest %r13d,%r13d\njne 1630 \nadd $0x8,%rsp\nmov %r14,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14, rdi\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\ntest esi, esi\njle short loc_16D1\nmov r13d, esi\nlea r15, [rdi+10h]\nloc_1670:\ncmp r13d, 1\njle short loc_16CB\nnop word ptr [rax+rax+00000000h]\nloc_1680:\nlea r12d, [r13-2]\nmov rbx, r14\nshl r12, 4\nadd r12, r15\nxchg ax, ax\nloc_1690:\nmov rbp, [rbx]\nmov rsi, [rbx+10h]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njle short loc_16B8\nmovdqu xmm1, xmmword ptr [rbx+10h]\nmovq xmm0, rbp\nmovhps xmm0, qword ptr [rbx+8]\nmovups xmmword ptr [rbx+10h], xmm0\nmovups xmmword ptr [rbx], xmm1\nloc_16B8:\nadd rbx, 10h\ncmp rbx, r12\njnz short loc_1690\nsub r13d, 1\ncmp r13d, 1\njg short loc_1680\nloc_16CB:\nsub r13d, 1\njnz short loc_1670\nloc_16D1:\nadd rsp, 8\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int v2; // r13d\n __int64 v3; // rbx\n __m128i v4; // xmm1\n\n if ( a2 > 0 )\n {\n v2 = a2;\n do\n {\n for ( ; v2 > 1; --v2 )\n {\n v3 = a1;\n do\n {\n if ( strcmp(*(const char **)v3, *(const char **)(v3 + 16)) > 0 )\n {\n v4 = _mm_loadu_si128((const __m128i *)(v3 + 16));\n *(__m128 *)(v3 + 16) = _mm_loadh_ps((const double *)(v3 + 8));\n *(__m128i *)v3 = v4;\n }\n v3 += 16LL;\n }\n while ( v3 != a1 + 16 + 16LL * (unsigned int)(v2 - 2) );\n }\n --v2;\n }\n while ( v2 );\n }\n return a1;\n}", + "ida_strip_asm": "sub_1650:\nendbr64\npush r15\npush r14\nmov r14, rdi\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\ntest esi, esi\njle short loc_16D1\nmov r13d, esi\nlea r15, [rdi+10h]\nloc_1670:\ncmp r13d, 1\njle short loc_16CB\nnop word ptr [rax+rax+00000000h]\nloc_1680:\nlea r12d, [r13-2]\nmov rbx, r14\nshl r12, 4\nadd r12, r15\nxchg ax, ax\nloc_1690:\nmov rbp, [rbx]\nmov rsi, [rbx+10h]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njle short loc_16B8\nmovdqu xmm1, xmmword ptr [rbx+10h]\nmovq xmm0, rbp\nmovhps xmm0, qword ptr [rbx+8]\nmovups xmmword ptr [rbx+10h], xmm0\nmovups xmmword ptr [rbx], xmm1\nloc_16B8:\nadd rbx, 10h\ncmp rbx, r12\njnz short loc_1690\nsub r13d, 1\ncmp r13d, 1\njg short loc_1680\nloc_16CB:\nsub r13d, 1\njnz short loc_1670\nloc_16D1:\nadd rsp, 8\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1650(__int64 a1, int a2)\n{\n int v2; // r13d\n __int64 v3; // rbx\n __m128i v4; // xmm1\n\n if ( a2 > 0 )\n {\n v2 = a2;\n do\n {\n for ( ; v2 > 1; --v2 )\n {\n v3 = a1;\n do\n {\n if ( strcmp(*(const char **)v3, *(const char **)(v3 + 16)) > 0 )\n {\n v4 = _mm_loadu_si128((const __m128i *)(v3 + 16));\n *(__m128 *)(v3 + 16) = _mm_loadh_ps((const double *)(v3 + 8));\n *(__m128i *)v3 = v4;\n }\n v3 += 16LL;\n }\n while ( v3 != a1 + 16 + 16LL * (unsigned int)(v2 - 2) );\n }\n --v2;\n }\n while ( v2 );\n }\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1650(long long a1, int a2) {\n int v2;\n long long v3;\n __m128i v4;\n if (a2 > 0) {\n v2 = a2;\n do {\n for (; v2 > 1; --v2) {\n v3 = a1;\n do {\n if (strcmp(*(const char **)v3, *(const char **)(v3 + 16)) > 0) {\n v4 = _mm_loadu_si128((const __m128i *)(v3 + 16));\n *(__m128 *)(v3 + 16) = _mm_loadh_ps((const double *)(v3 + 8));\n *(__m128i *)v3 = v4;\n }\n v3 += 16LL;\n } while (v3 != a1 + 16 + 16LL * (unsigned int)(v2 - 2));\n }\n --v2;\n } while (v2);\n }\n return a1;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int v2;\n long long v3;\n __m128i v4;\n if (a2 > 0) {\n v2 = a2;\n do {\n for (; v2 > 1; --v2) {\n v3 = a1;\n do {\n if (strcmp(*(const char **)v3, *(const char **)(v3 + 16)) > 0) {\n v4 = _mm_loadu_si128((const __m128i *)(v3 + 16));\n *(__m128 *)(v3 + 16) = _mm_loadh_ps((const double *)(v3 + 8));\n *(__m128i *)v3 = v4;\n }\n v3 += 16LL;\n } while (v3 != a1 + 16 + 16LL * (unsigned int)(v2 - 2));\n }\n --v2;\n } while (v2);\n }\n return a1;\n}" + }, + { + "index": 839, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char* first;\n\n char* second;\n\n} tuple;\n\n\n\n", + "func": "tuple* func0(tuple arr[], int n) {\n for (int i = 0; i < n; i++) {\n for (int j = 0; j < n - i - 1; j++) {\n if (strcmp(arr[j].first, arr[j + 1].first) > 0) {\n tuple temp = arr[j];\n arr[j] = arr[j + 1];\n arr[j + 1] = temp;\n }\n }\n }\n return arr;\n}", + "test": "int main() {\n\n // Test case 1\n\n tuple test1[] = {{\"Amana\", \"28\"}, {\"Zenat\", \"30\"}, {\"Abhishek\", \"29\"}, {\"Nikhil\", \"21\"}, {\"B\", \"C\"}};\n\n tuple expected1[] = {{\"Abhishek\", \"29\"}, {\"Amana\", \"28\"}, {\"B\", \"C\"}, {\"Nikhil\", \"21\"}, {\"Zenat\", \"30\"}};\n\n func0(test1, 5);\n\n for(int i = 0; i < 5; i++) {\n\n assert(strcmp(test1[i].first, expected1[i].first) == 0);\n\n assert(strcmp(test1[i].second, expected1[i].second) == 0);\n\n }\n\n\n\n // Test case 2\n\n tuple test2[] = {{\"aaaa\", \"28\"}, {\"aa\", \"30\"}, {\"bab\", \"29\"}, {\"bb\", \"21\"}, {\"csa\", \"C\"}};\n\n tuple expected2[] = {{\"aa\", \"30\"}, {\"aaaa\", \"28\"}, {\"bab\", \"29\"}, {\"bb\", \"21\"}, {\"csa\", \"C\"}};\n\n func0(test2, 5);\n\n for(int i = 0; i < 5; i++) {\n\n assert(strcmp(test2[i].first, expected2[i].first) == 0);\n\n assert(strcmp(test2[i].second, expected2[i].second) == 0);\n\n }\n\n\n\n // Test case 3\n\n tuple test3[] = {{\"Sarala\", \"28\"}, {\"Ayesha\", \"30\"}, {\"Suman\", \"29\"}, {\"Sai\", \"21\"}, {\"G\", \"H\"}};\n\n tuple expected3[] = {{\"Ayesha\", \"30\"}, {\"G\", \"H\"}, {\"Sai\", \"21\"}, {\"Sarala\", \"28\"}, {\"Suman\", \"29\"}};\n\n func0(test3, 5);\n\n for(int i = 0; i < 5; i++) {\n\n assert(strcmp(test3[i].first, expected3[i].first) == 0);\n\n assert(strcmp(test3[i].second, expected3[i].second) == 0);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\nmov %rdi,%r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\ntest %esi,%esi\njle 1877 \nmov %esi,%r13d\nlea 0x10(%rdi),%r15\nsub $0x1,%r13d\ntest %r13d,%r13d\nje 1877 \nnopl 0x0(%rax)\nlea -0x1(%r13),%r12d\nmov %r14,%rbx\nmov %r12,%r13\nshl $0x4,%r12\nadd %r15,%r12\nnopl 0x0(%rax)\nmov (%rbx),%rbp\nmov 0x10(%rbx),%rsi\nmov %rbp,%rdi\ncallq 1090 \ntest %eax,%eax\njle 1869 \nmov 0x8(%rbx),%rax\nmovdqu 0x10(%rbx),%xmm1\nmovq %rbp,%xmm0\nmovq %rax,%xmm2\nmovups %xmm1,(%rbx)\npunpcklqdq %xmm2,%xmm0\nmovups %xmm0,0x10(%rbx)\nadd $0x10,%rbx\ncmp %r12,%rbx\njne 1838 \ntest %r13d,%r13d\njne 1820 \nadd $0x8,%rsp\nmov %r14,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14, rdi\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\ntest esi, esi\njle short loc_1891\nmov r13d, esi\nlea r15, [rdi+10h]\nloc_1830:\ncmp r13d, 1\njle short loc_188B\nnop word ptr [rax+rax+00000000h]\nloc_1840:\nlea r12d, [r13-2]\nmov rbx, r14\nshl r12, 4\nadd r12, r15\nxchg ax, ax\nloc_1850:\nmov rbp, [rbx]\nmov rsi, [rbx+10h]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njle short loc_1878\nmovdqu xmm1, xmmword ptr [rbx+10h]\nmovq xmm0, rbp\nmovhps xmm0, qword ptr [rbx+8]\nmovups xmmword ptr [rbx+10h], xmm0\nmovups xmmword ptr [rbx], xmm1\nloc_1878:\nadd rbx, 10h\ncmp rbx, r12\njnz short loc_1850\nsub r13d, 1\ncmp r13d, 1\njg short loc_1840\nloc_188B:\nsub r13d, 1\njnz short loc_1830\nloc_1891:\nadd rsp, 8\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int v2; // r13d\n __int64 v3; // rbx\n __m128i v4; // xmm1\n\n if ( a2 > 0 )\n {\n v2 = a2;\n do\n {\n for ( ; v2 > 1; --v2 )\n {\n v3 = a1;\n do\n {\n if ( strcmp(*(const char **)v3, *(const char **)(v3 + 16)) > 0 )\n {\n v4 = _mm_loadu_si128((const __m128i *)(v3 + 16));\n *(__m128 *)(v3 + 16) = _mm_loadh_ps((const double *)(v3 + 8));\n *(__m128i *)v3 = v4;\n }\n v3 += 16LL;\n }\n while ( v3 != a1 + 16 + 16LL * (unsigned int)(v2 - 2) );\n }\n --v2;\n }\n while ( v2 );\n }\n return a1;\n}", + "ida_strip_asm": "sub_1810:\nendbr64\npush r15\npush r14\nmov r14, rdi\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\ntest esi, esi\njle short loc_1891\nmov r13d, esi\nlea r15, [rdi+10h]\nloc_1830:\ncmp r13d, 1\njle short loc_188B\nnop word ptr [rax+rax+00000000h]\nloc_1840:\nlea r12d, [r13-2]\nmov rbx, r14\nshl r12, 4\nadd r12, r15\nxchg ax, ax\nloc_1850:\nmov rbp, [rbx]\nmov rsi, [rbx+10h]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njle short loc_1878\nmovdqu xmm1, xmmword ptr [rbx+10h]\nmovq xmm0, rbp\nmovhps xmm0, qword ptr [rbx+8]\nmovups xmmword ptr [rbx+10h], xmm0\nmovups xmmword ptr [rbx], xmm1\nloc_1878:\nadd rbx, 10h\ncmp rbx, r12\njnz short loc_1850\nsub r13d, 1\ncmp r13d, 1\njg short loc_1840\nloc_188B:\nsub r13d, 1\njnz short loc_1830\nloc_1891:\nadd rsp, 8\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1810(__int64 a1, int a2)\n{\n int v2; // r13d\n __int64 v3; // rbx\n __m128i v4; // xmm1\n\n if ( a2 > 0 )\n {\n v2 = a2;\n do\n {\n for ( ; v2 > 1; --v2 )\n {\n v3 = a1;\n do\n {\n if ( strcmp(*(const char **)v3, *(const char **)(v3 + 16)) > 0 )\n {\n v4 = _mm_loadu_si128((const __m128i *)(v3 + 16));\n *(__m128 *)(v3 + 16) = _mm_loadh_ps((const double *)(v3 + 8));\n *(__m128i *)v3 = v4;\n }\n v3 += 16LL;\n }\n while ( v3 != a1 + 16 + 16LL * (unsigned int)(v2 - 2) );\n }\n --v2;\n }\n while ( v2 );\n }\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1810(long long a1, int a2) {\n int v2;\n long long v3;\n __m128i v4;\n if (a2 > 0) {\n v2 = a2;\n do {\n for (; v2 > 1; --v2) {\n v3 = a1;\n do {\n if (strcmp(*(const char **)v3, *(const char **)(v3 + 16)) > 0) {\n v4 = _mm_loadu_si128((const __m128i *)(v3 + 16));\n *(__m128 *)(v3 + 16) = _mm_loadh_ps((const double *)(v3 + 8));\n *(__m128i *)v3 = v4;\n }\n v3 += 16LL;\n } while (v3 != a1 + 16 + 16LL * (unsigned int)(v2 - 2));\n }\n --v2;\n } while (v2);\n }\n return a1;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int v2;\n long long v3;\n __m128i v4;\n if (a2 > 0) {\n v2 = a2;\n do {\n for (; v2 > 1; --v2) {\n v3 = a1;\n do {\n if (strcmp(*(const char **)v3, *(const char **)(v3 + 16)) > 0) {\n v4 = _mm_loadu_si128((const __m128i *)(v3 + 16));\n *(__m128 *)(v3 + 16) = _mm_loadh_ps((const double *)(v3 + 8));\n *(__m128i *)v3 = v4;\n }\n v3 += 16LL;\n } while (v3 != a1 + 16 + 16LL * (unsigned int)(v2 - 2));\n }\n --v2;\n } while (v2);\n }\n return a1;\n}" + }, + { + "index": 840, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(int a, int b, int c) {\n if (b == 0) {\n return \"Yes\";\n }\n else {\n return \"No\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(2, 0, -1), \"Yes\") == 0);\n\n assert(strcmp(func0(1, -5, 6), \"No\") == 0);\n\n assert(strcmp(func0(2, 0, 2), \"Yes\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov %esi,-0x8(%rbp)\nmov %edx,-0xc(%rbp)\ncmpl $0x0,-0x8(%rbp)\njne 1189 \nlea 0xe81(%rip),%rax\njmp 1190 \nlea 0xe7c(%rip),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov [rbp+var_C], edx\ncmp [rbp+var_8], 0\njnz short loc_1189\nlea rax, s2; \"Yes\"\njmp short loc_1190\nloc_1189:\nlea rax, aNo; \"No\"\nloc_1190:\npop rbp\nretn", + "ida_pseudo": "const char *__fastcall func0(__int64 a1, int a2)\n{\n if ( a2 )\n return \"No\";\n else\n return \"Yes\";\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov [rbp+var_C], edx\ncmp [rbp+var_8], 0\njnz short loc_1189\nlea rax, s2; \"Yes\"\njmp short loc_1190\nloc_1189:\nlea rax, aNo; \"No\"\nloc_1190:\npop rbp\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1169(__int64 a1, int a2)\n{\n if ( a2 )\n return \"No\";\n else\n return \"Yes\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char* sub_1169(long long a1, int a2) {\n if (a2)\n return \"No\";\n else\n return \"Yes\";\n}", + "ida_pseudo_norm": "const char* func0(long long a1, int a2) {\n if (a2)\n return \"No\";\n else\n return \"Yes\";\n}" + }, + { + "index": 841, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int inv_count = 0;\n for (int i = 0; i < n; i++) {\n for (int j = i + 1; j < n; j++) {\n if (arr[i] > arr[j]) {\n inv_count++;\n }\n }\n }\n return inv_count;\n}", + "test": "int main() {\n\n int arr1[] = {1, 20, 6, 4, 5};\n\n assert(func0(arr1, 5) == 5);\n\n\n\n int arr2[] = {8, 4, 2, 1};\n\n assert(func0(arr2, 4) == 6);\n\n\n\n int arr3[] = {3, 1, 2};\n\n assert(func0(arr3, 3) == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11d7 \nmov -0x8(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x4(%rbp)\njmp 11cb \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njle 11c7 \naddl $0x1,-0xc(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1193 \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1188 \nmov -0xc(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_11D7\nloc_1188:\nmov eax, [rbp+var_8]\nadd eax, 1\nmov [rbp+var_4], eax\njmp short loc_11CB\nloc_1193:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_11C7\nadd [rbp+var_C], 1\nloc_11C7:\nadd [rbp+var_4], 1\nloc_11CB:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1193\nadd [rbp+var_8], 1\nloc_11D7:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+10h] [rbp-Ch]\n int i; // [rsp+14h] [rbp-8h]\n int j; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a1) > *(_DWORD *)(4LL * j + a1) )\n ++v3;\n }\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 0\njmp short loc_11D7\nloc_1188:\nmov eax, [rbp+var_8]\nadd eax, 1\nmov [rbp+var_4], eax\njmp short loc_11CB\nloc_1193:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_11C7\nadd [rbp+var_C], 1\nloc_11C7:\nadd [rbp+var_4], 1\nloc_11CB:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1193\nadd [rbp+var_8], 1\nloc_11D7:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+10h] [rbp-Ch]\n int i; // [rsp+14h] [rbp-8h]\n int j; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a1) > *(_DWORD *)(4LL * j + a1) )\n ++v3;\n }\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n unsigned int v3;\n int i;\n int j;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if (*(uint32_t *)(4LL * i + a1) > *(uint32_t *)(4LL * j + a1)) ++v3;\n }\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n int j;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if (*(uint32_t *)(4LL * i + a1) > *(uint32_t *)(4LL * j + a1)) ++v3;\n }\n }\n return v3;\n}" + }, + { + "index": 841, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int inv_count = 0;\n for (int i = 0; i < n; i++) {\n for (int j = i + 1; j < n; j++) {\n if (arr[i] > arr[j]) {\n inv_count++;\n }\n }\n }\n return inv_count;\n}", + "test": "int main() {\n\n int arr1[] = {1, 20, 6, 4, 5};\n\n assert(func0(arr1, 5) == 5);\n\n\n\n int arr2[] = {8, 4, 2, 1};\n\n assert(func0(arr2, 4) == 6);\n\n\n\n int arr3[] = {3, 1, 2};\n\n assert(func0(arr3, 3) == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11ab \nlea -0x1(%rsi),%r9d\nadd $0x1,%r9\nmov $0x1,%r8d\nmov $0x0,%ecx\njmp 119c \nadd $0x1,%rax\ncmp %eax,%esi\njle 1198 \ncmp (%rdi,%rax,4),%edx\njle 1186 \nadd $0x1,%ecx\njmp 1186 \nadd $0x1,%r8\ncmp %r9,%r8\nje 11b0 \nmov -0x4(%rdi,%r8,4),%edx\nmov %r8,%rax\njmp 118e \nmov $0x0,%ecx\nmov %ecx,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11B1\nmov r9d, esi\nmovsxd r10, esi\nmov r8d, 1\nmov ecx, 0\njmp short loc_11A2\nloc_1184:\nadd rax, 1\ncmp esi, eax\njle short loc_1196\nloc_118C:\ncmp edx, [rdi+rax*4]\njle short loc_1184\nadd ecx, 1\njmp short loc_1184\nloc_1196:\nlea rax, [r8+1]\ncmp r8, r10\njz short loc_11B6\nmov r8, rax\nloc_11A2:\ncmp r8, r9\njz short loc_11B6\nmov edx, [rdi+r8*4-4]\nmov rax, r8\njmp short loc_118C\nloc_11B1:\nmov ecx, 0\nloc_11B6:\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // r8\n unsigned int v3; // ecx\n __int64 v4; // rax\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = 1LL;\n v3 = 0;\n while ( v2 != a2 )\n {\n v4 = v2;\n do\n {\n if ( *(_DWORD *)(a1 + 4 * v2 - 4) > *(_DWORD *)(a1 + 4 * v4) )\n ++v3;\n ++v4;\n }\n while ( a2 > (int)v4 );\n if ( v2 == a2 )\n break;\n ++v2;\n }\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11B1\nmov r9d, esi\nmovsxd r10, esi\nmov r8d, 1\nmov ecx, 0\njmp short loc_11A2\nloc_1184:\nadd rax, 1\ncmp esi, eax\njle short loc_1196\nloc_118C:\ncmp edx, [rdi+rax*4]\njle short loc_1184\nadd ecx, 1\njmp short loc_1184\nloc_1196:\nlea rax, [r8+1]\ncmp r8, r10\njz short loc_11B6\nmov r8, rax\nloc_11A2:\ncmp r8, r9\njz short loc_11B6\nmov edx, [rdi+r8*4-4]\nmov rax, r8\njmp short loc_118C\nloc_11B1:\nmov ecx, 0\nloc_11B6:\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n __int64 v2; // r8\n unsigned int v3; // ecx\n __int64 v4; // rax\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = 1LL;\n v3 = 0;\n while ( v2 != a2 )\n {\n v4 = v2;\n do\n {\n if ( *(_DWORD *)(a1 + 4 * v2 - 4) > *(_DWORD *)(a1 + 4 * v4) )\n ++v3;\n ++v4;\n }\n while ( a2 > (int)v4 );\n if ( v2 == a2 )\n break;\n ++v2;\n }\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n long long v4;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = 1LL;\n v3 = 0;\n while (v2 != a2) {\n v4 = v2;\n do {\n if (*(uint32_t *)(a1 + 4 * v2 - 4) > *(uint32_t *)(a1 + 4 * v4)) ++v3;\n ++v4;\n } while (a2 > (int)v4);\n if (v2 == a2) break;\n ++v2;\n }\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n long long v4;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = 1LL;\n v3 = 0;\n while (v2 != a2) {\n v4 = v2;\n do {\n if (*(uint32_t *)(a1 + 4 * v2 - 4) > *(uint32_t *)(a1 + 4 * v4)) ++v3;\n ++v4;\n } while (a2 > (int)v4);\n if (v2 == a2) break;\n ++v2;\n }\n }\n return v3;\n}" + }, + { + "index": 841, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int inv_count = 0;\n for (int i = 0; i < n; i++) {\n for (int j = i + 1; j < n; j++) {\n if (arr[i] > arr[j]) {\n inv_count++;\n }\n }\n }\n return inv_count;\n}", + "test": "int main() {\n\n int arr1[] = {1, 20, 6, 4, 5};\n\n assert(func0(arr1, 5) == 5);\n\n\n\n int arr2[] = {8, 4, 2, 1};\n\n assert(func0(arr2, 4) == 6);\n\n\n\n int arr3[] = {3, 1, 2};\n\n assert(func0(arr3, 3) == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 137e \nlea -0x1(%rsi),%r9d\nmov $0x1,%ecx\nxor %r8d,%r8d\nadd $0x1,%r9\ncmp %r9,%rcx\nje 137a \nnopl (%rax)\nmov -0x4(%rdi,%rcx,4),%edx\nmov %rcx,%rax\nnopw 0x0(%rax,%rax,1)\ncmp (%rdi,%rax,4),%edx\njle 1369 \nadd $0x1,%r8d\nadd $0x1,%rax\ncmp %eax,%esi\njg 1360 \nadd $0x1,%rcx\ncmp %r9,%rcx\njne 1350 \nmov %r8d,%eax\nretq\nxor %r8d,%r8d\nmov %r8d,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_12BC\nmov r9d, esi\nmov r8d, 1\nxor ecx, ecx\ncmp esi, 1\njz short loc_12B9\nnop dword ptr [rax+rax+00000000h]\nloc_1290:\nmov edx, [rdi+r8*4-4]\nmov rax, r8\nnop dword ptr [rax+rax+00000000h]\nloc_12A0:\ncmp edx, [rdi+rax*4]\njle short loc_12A8\nadd ecx, 1\nloc_12A8:\nadd rax, 1\ncmp esi, eax\njg short loc_12A0\nadd r8, 1\ncmp r8, r9\njnz short loc_1290\nloc_12B9:\nmov eax, ecx\nretn\nloc_12BC:\nxor ecx, ecx\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v2; // r8\n unsigned int v3; // ecx\n __int64 v4; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 1LL;\n v3 = 0;\n if ( a2 != 1 )\n {\n do\n {\n v4 = v2;\n do\n {\n if ( *(_DWORD *)(a1 + 4 * v2 - 4) > *(_DWORD *)(a1 + 4 * v4) )\n ++v3;\n ++v4;\n }\n while ( a2 > (int)v4 );\n ++v2;\n }\n while ( v2 != a2 );\n }\n return v3;\n}", + "ida_strip_asm": "sub_1270:\nendbr64\ntest esi, esi\njle short loc_12BC\nmov r9d, esi\nmov r8d, 1\nxor ecx, ecx\ncmp esi, 1\njz short loc_12B9\nnop dword ptr [rax+rax+00000000h]\nloc_1290:\nmov edx, [rdi+r8*4-4]\nmov rax, r8\nnop dword ptr [rax+rax+00000000h]\nloc_12A0:\ncmp edx, [rdi+rax*4]\njle short loc_12A8\nadd ecx, 1\nloc_12A8:\nadd rax, 1\ncmp esi, eax\njg short loc_12A0\nadd r8, 1\ncmp r8, r9\njnz short loc_1290\nloc_12B9:\nmov eax, ecx\nretn\nloc_12BC:\nxor ecx, ecx\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1270(__int64 a1, int a2)\n{\n __int64 v2; // r8\n unsigned int v3; // ecx\n __int64 v4; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v2 = 1LL;\n v3 = 0;\n if ( a2 != 1 )\n {\n do\n {\n v4 = v2;\n do\n {\n if ( *(_DWORD *)(a1 + 4 * v2 - 4) > *(_DWORD *)(a1 + 4 * v4) )\n ++v3;\n ++v4;\n }\n while ( a2 > (int)v4 );\n ++v2;\n }\n while ( v2 != a2 );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1270(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n long long v4;\n if (a2 <= 0) return 0LL;\n v2 = 1LL;\n v3 = 0;\n if (a2 != 1) {\n do {\n v4 = v2;\n do {\n if (*(uint32_t *)(a1 + 4 * v2 - 4) > *(uint32_t *)(a1 + 4 * v4)) ++v3;\n ++v4;\n } while (a2 > (int)v4);\n ++v2;\n } while (v2 != a2);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v2;\n unsigned int v3;\n long long v4;\n if (a2 <= 0) return 0LL;\n v2 = 1LL;\n v3 = 0;\n if (a2 != 1) {\n do {\n v4 = v2;\n do {\n if (*(uint32_t *)(a1 + 4 * v2 - 4) > *(uint32_t *)(a1 + 4 * v4)) ++v3;\n ++v4;\n } while (a2 > (int)v4);\n ++v2;\n } while (v2 != a2);\n }\n return v3;\n}" + }, + { + "index": 842, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int arr[], int arr_size) {\n for (int i = 0; i < arr_size; i++) {\n int count = 0;\n for (int j = 0; j < arr_size; j++) {\n if (arr[i] == arr[j]) {\n count++;\n }\n }\n if (count % 2 != 0) {\n return arr[i];\n }\n }\n return -1;\n}", + "test": "int main() {\n\n int arr1[] = {2, 3, 5, 4, 5, 2, 4, 3, 5, 2, 4, 4, 2};\n\n int arr2[] = {1, 2, 3, 2, 3, 1, 3};\n\n int arr3[] = {5, 7, 2, 7, 5, 2, 5};\n\n\n\n assert(func0(arr1, 13) == 5);\n\n assert(func0(arr2, 7) == 3);\n\n assert(func0(arr3, 7) == 5);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 11f7 \nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11c9 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 11c5 \naddl $0x1,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1191 \nmov -0x8(%rbp),%eax\nand $0x1,%eax\ntest %eax,%eax\nje 11f3 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\njmp 1204 \naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1181 \nmov $0xffffffff,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0\njmp short loc_11F7\nloc_1181:\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11C9\nloc_1191:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11C5\nadd [rbp+var_8], 1\nloc_11C5:\nadd [rbp+var_4], 1\nloc_11C9:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1191\nmov eax, [rbp+var_8]\nand eax, 1\ntest eax, eax\njz short loc_11F3\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\njmp short loc_1204\nloc_11F3:\nadd [rbp+var_C], 1\nloc_11F7:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_1181\nmov eax, 0FFFFFFFFh\nloc_1204:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+10h] [rbp-Ch]\n char v4; // [rsp+14h] [rbp-8h]\n int j; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n v4 = 0;\n for ( j = 0; j < a2; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4LL * j + a1) )\n ++v4;\n }\n if ( (v4 & 1) != 0 )\n return *(unsigned int *)(4LL * i + a1);\n }\n return 0xFFFFFFFFLL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_C], 0\njmp short loc_11F7\nloc_1181:\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11C9\nloc_1191:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11C5\nadd [rbp+var_8], 1\nloc_11C5:\nadd [rbp+var_4], 1\nloc_11C9:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1191\nmov eax, [rbp+var_8]\nand eax, 1\ntest eax, eax\njz short loc_11F3\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\njmp short loc_1204\nloc_11F3:\nadd [rbp+var_C], 1\nloc_11F7:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_1181\nmov eax, 0FFFFFFFFh\nloc_1204:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int i; // [rsp+10h] [rbp-Ch]\n char v4; // [rsp+14h] [rbp-8h]\n int j; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n v4 = 0;\n for ( j = 0; j < a2; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4LL * j + a1) )\n ++v4;\n }\n if ( (v4 & 1) != 0 )\n return *(unsigned int *)(4LL * i + a1);\n }\n return 0xFFFFFFFFLL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int i;\n char v4;\n int j;\n for (i = 0; i < a2; ++i) {\n v4 = 0;\n for (j = 0; j < a2; ++j) {\n if (*(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4LL * j + a1)) ++v4;\n }\n if ((v4 & 1) != 0) return *(unsigned int *)(4LL * i + a1);\n }\n return 4294967295LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int i;\n char v4;\n int j;\n for (i = 0; i < a2; ++i) {\n v4 = 0;\n for (j = 0; j < a2; ++j) {\n if (*(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4LL * j + a1)) ++v4;\n }\n if ((v4 & 1) != 0) return *(unsigned int *)(4LL * i + a1);\n }\n return 4294967295LL;\n}" + }, + { + "index": 842, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int arr[], int arr_size) {\n for (int i = 0; i < arr_size; i++) {\n int count = 0;\n for (int j = 0; j < arr_size; j++) {\n if (arr[i] == arr[j]) {\n count++;\n }\n }\n if (count % 2 != 0) {\n return arr[i];\n }\n }\n return -1;\n}", + "test": "int main() {\n\n int arr1[] = {2, 3, 5, 4, 5, 2, 4, 3, 5, 2, 4, 4, 2};\n\n int arr2[] = {1, 2, 3, 2, 3, 1, 3};\n\n int arr3[] = {5, 7, 2, 7, 5, 2, 5};\n\n\n\n assert(func0(arr1, 13) == 5);\n\n assert(func0(arr2, 7) == 3);\n\n assert(func0(arr3, 7) == 5);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11c4 \npush %rbx\nlea -0x1(%rsi),%r11d\nmov %rdi,%rbx\nlea 0x4(%rdi,%r11,4),%r8\nmov $0x0,%r9d\njmp 1197 \ntest $0x1,%dl\njne 11bb \nlea 0x1(%r9),%rax\ncmp %r11,%r9\nje 11ca \nmov %rax,%r9\nmov %r9d,%r10d\nmov (%rdi,%r9,4),%esi\nmov %rbx,%rax\nmov $0x0,%edx\ncmp (%rax),%esi\nsete %cl\nmovzbl %cl,%ecx\nadd %ecx,%edx\nadd $0x4,%rax\ncmp %r8,%rax\njne 11a6 \njmp 1186 \nmovslq %r10d,%r10\nmov (%rdi,%r10,4),%eax\npop %rbx\nretq\nmov $0xffffffff,%eax\nretq\nmov $0xffffffff,%eax\njmp 11c2 \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11B7\nmovsxd r10, esi\nlea r8, [rdi+r10*4]\nmov r9d, 0\njmp short loc_118E\nloc_1180:\ntest dl, 1\njnz short loc_11AF\nadd r9, 1\ncmp r9, r10\njz short loc_11BD\nloc_118E:\nmov esi, [rdi+r9*4]\nmov rax, rdi\nmov edx, 0\nloc_119A:\ncmp esi, [rax]\nsetz cl\nmovzx ecx, cl\nadd edx, ecx\nadd rax, 4\ncmp rax, r8\njnz short loc_119A\njmp short loc_1180\nloc_11AF:\nmovsxd r9, r9d\nmov eax, [rdi+r9*4]\nretn\nloc_11B7:\nmov eax, 0FFFFFFFFh\nretn\nloc_11BD:\nmov eax, 0FFFFFFFFh\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n __int64 i; // r9\n _DWORD *v3; // rax\n char v4; // dl\n\n if ( a2 <= 0 )\n return 0xFFFFFFFFLL;\n for ( i = 0LL; i != a2; ++i )\n {\n v3 = a1;\n v4 = 0;\n do\n v4 += a1[i] == *v3++;\n while ( v3 != &a1[a2] );\n if ( (v4 & 1) != 0 )\n return (unsigned int)a1[(int)i];\n }\n return 0xFFFFFFFFLL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11B7\nmovsxd r10, esi\nlea r8, [rdi+r10*4]\nmov r9d, 0\njmp short loc_118E\nloc_1180:\ntest dl, 1\njnz short loc_11AF\nadd r9, 1\ncmp r9, r10\njz short loc_11BD\nloc_118E:\nmov esi, [rdi+r9*4]\nmov rax, rdi\nmov edx, 0\nloc_119A:\ncmp esi, [rax]\nsetz cl\nmovzx ecx, cl\nadd edx, ecx\nadd rax, 4\ncmp rax, r8\njnz short loc_119A\njmp short loc_1180\nloc_11AF:\nmovsxd r9, r9d\nmov eax, [rdi+r9*4]\nretn\nloc_11B7:\nmov eax, 0FFFFFFFFh\nretn\nloc_11BD:\nmov eax, 0FFFFFFFFh\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2)\n{\n __int64 i; // r9\n _DWORD *v3; // rax\n char v4; // dl\n\n if ( a2 <= 0 )\n return 0xFFFFFFFFLL;\n for ( i = 0LL; i != a2; ++i )\n {\n v3 = a1;\n v4 = 0;\n do\n v4 += a1[i] == *v3++;\n while ( v3 != &a1[a2] );\n if ( (v4 & 1) != 0 )\n return (unsigned int)a1[(int)i];\n }\n return 0xFFFFFFFFLL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2) {\n long long i;\n uint32_t *v3;\n char v4;\n if (a2 <= 0) return 4294967295LL;\n for (i = 0LL; i != a2; ++i) {\n v3 = a1;\n v4 = 0;\n do\n v4 += a1[i] == *v3++;\n while (v3 != &a1[a2]);\n if ((v4 & 1) != 0) return (unsigned int)a1[(int)i];\n }\n return 4294967295LL;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n long long i;\n uint32_t *v3;\n char v4;\n if (a2 <= 0) return 4294967295LL;\n for (i = 0LL; i != a2; ++i) {\n v3 = a1;\n v4 = 0;\n do\n v4 += a1[i] == *v3++;\n while (v3 != &a1[a2]);\n if ((v4 & 1) != 0) return (unsigned int)a1[(int)i];\n }\n return 4294967295LL;\n}" + }, + { + "index": 842, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int arr[], int arr_size) {\n for (int i = 0; i < arr_size; i++) {\n int count = 0;\n for (int j = 0; j < arr_size; j++) {\n if (arr[i] == arr[j]) {\n count++;\n }\n }\n if (count % 2 != 0) {\n return arr[i];\n }\n }\n return -1;\n}", + "test": "int main() {\n\n int arr1[] = {2, 3, 5, 4, 5, 2, 4, 3, 5, 2, 4, 4, 2};\n\n int arr2[] = {1, 2, 3, 2, 3, 1, 3};\n\n int arr3[] = {5, 7, 2, 7, 5, 2, 5};\n\n\n\n assert(func0(arr1, 13) == 5);\n\n assert(func0(arr2, 7) == 3);\n\n assert(func0(arr3, 7) == 5);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1341 \nlea -0x1(%rsi),%eax\nmov %rdi,%r9\nlea 0x4(%rdi,%rax,4),%rsi\nnopl 0x0(%rax,%rax,1)\nmov (%r9),%r8d\nmov %rdi,%rax\nxor %edx,%edx\nxor %ecx,%ecx\ncmp (%rax),%r8d\nsete %cl\nadd $0x4,%rax\nadd %ecx,%edx\ncmp %rsi,%rax\njne 1320 \nand $0x1,%edx\njne 1347 \nadd $0x4,%r9\ncmp %rax,%r9\njne 1318 \nmov $0xffffffff,%r8d\nmov %r8d,%eax\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1300\nmovsxd rsi, esi\nmov r9, rdi\nlea r8, [rdi+rsi*4]\nnop word ptr [rax+rax+00h]\nloc_12D8:\nmov esi, [r9]\nmov rax, rdi\nxor edx, edx\nloc_12E0:\nxor ecx, ecx\ncmp esi, [rax]\nsetz cl\nadd rax, 4\nadd edx, ecx\ncmp rax, r8\njnz short loc_12E0\nand edx, 1\njnz short loc_1305\nadd r9, 4\ncmp r9, rax\njnz short loc_12D8\nloc_1300:\nmov esi, 0FFFFFFFFh\nloc_1305:\nmov eax, esi\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n unsigned int *v2; // r9\n unsigned int *v3; // r8\n unsigned int v4; // esi\n unsigned int *v5; // rax\n char v6; // dl\n char v7; // cl\n\n if ( a2 <= 0 )\n {\n return (unsigned int)-1;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n while ( 1 )\n {\n v4 = *v2;\n v5 = a1;\n v6 = 0;\n do\n {\n v7 = v4 == *v5++;\n v6 += v7;\n }\n while ( v5 != v3 );\n if ( (v6 & 1) != 0 )\n break;\n if ( ++v2 == v5 )\n return (unsigned int)-1;\n }\n }\n return v4;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\ntest esi, esi\njle short loc_1300\nmovsxd rsi, esi\nmov r9, rdi\nlea r8, [rdi+rsi*4]\nnop word ptr [rax+rax+00h]\nloc_12D8:\nmov esi, [r9]\nmov rax, rdi\nxor edx, edx\nloc_12E0:\nxor ecx, ecx\ncmp esi, [rax]\nsetz cl\nadd rax, 4\nadd edx, ecx\ncmp rax, r8\njnz short loc_12E0\nand edx, 1\njnz short loc_1305\nadd r9, 4\ncmp r9, rax\njnz short loc_12D8\nloc_1300:\nmov esi, 0FFFFFFFFh\nloc_1305:\nmov eax, esi\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12C0(unsigned int *a1, int a2)\n{\n unsigned int *v2; // r9\n unsigned int *v3; // r8\n unsigned int v4; // esi\n unsigned int *v5; // rax\n char v6; // dl\n char v7; // cl\n\n if ( a2 <= 0 )\n {\n return (unsigned int)-1;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n while ( 1 )\n {\n v4 = *v2;\n v5 = a1;\n v6 = 0;\n do\n {\n v7 = v4 == *v5++;\n v6 += v7;\n }\n while ( v5 != v3 );\n if ( (v6 & 1) != 0 )\n break;\n if ( ++v2 == v5 )\n return (unsigned int)-1;\n }\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12C0(unsigned int *a1, int a2) {\n unsigned int *v2;\n unsigned int *v3;\n unsigned int v4;\n unsigned int *v5;\n char v6;\n char v7;\n if (a2 <= 0) {\n return (unsigned int)-1;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n while (1) {\n v4 = *v2;\n v5 = a1;\n v6 = 0;\n do {\n v7 = v4 == *v5++;\n v6 += v7;\n } while (v5 != v3);\n if ((v6 & 1) != 0) break;\n if (++v2 == v5) return (unsigned int)-1;\n }\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n unsigned int *v2;\n unsigned int *v3;\n unsigned int v4;\n unsigned int *v5;\n char v6;\n char v7;\n if (a2 <= 0) {\n return (unsigned int)-1;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n while (1) {\n v4 = *v2;\n v5 = a1;\n v6 = 0;\n do {\n v7 = v4 == *v5++;\n v6 += v7;\n } while (v5 != v3);\n if ((v6 & 1) != 0) break;\n if (++v2 == v5) return (unsigned int)-1;\n }\n }\n return v4;\n}" + }, + { + "index": 842, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int arr[], int arr_size) {\n for (int i = 0; i < arr_size; i++) {\n int count = 0;\n for (int j = 0; j < arr_size; j++) {\n if (arr[i] == arr[j]) {\n count++;\n }\n }\n if (count % 2 != 0) {\n return arr[i];\n }\n }\n return -1;\n}", + "test": "int main() {\n\n int arr1[] = {2, 3, 5, 4, 5, 2, 4, 3, 5, 2, 4, 4, 2};\n\n int arr2[] = {1, 2, 3, 2, 3, 1, 3};\n\n int arr3[] = {5, 7, 2, 7, 5, 2, 5};\n\n\n\n assert(func0(arr1, 13) == 5);\n\n assert(func0(arr2, 7) == 3);\n\n assert(func0(arr3, 7) == 5);\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 13c6 \nmov %esi,%edx\npush %r12\nlea -0x1(%rsi),%eax\nmov %rdi,%r9\nshr $0x2,%edx\npush %rbp\nlea 0x4(%rdi,%rax,4),%r12\nmov %rax,%rbp\npush %rbx\nshl $0x4,%rdx\nmov %esi,%ebx\nadd %rdi,%rdx\nand $0xfffffffc,%ebx\nmov (%r9),%r8d\ncmp $0x3,%ebp\njbe 13c0 \nmovd %r8d,%xmm3\nmov %rdi,%rax\npxor %xmm1,%xmm1\npshufd $0x0,%xmm3,%xmm2\nnopl (%rax)\nmovdqu (%rax),%xmm0\nadd $0x10,%rax\npcmpeqd %xmm2,%xmm0\npsubd %xmm0,%xmm1\ncmp %rax,%rdx\njne 1310 \nmovdqa %xmm1,%xmm0\nmov %ebx,%ecx\npsrldq $0x8,%xmm0\npaddd %xmm0,%xmm1\nmovdqa %xmm1,%xmm0\npsrldq $0x4,%xmm0\npaddd %xmm0,%xmm1\nmovd %xmm1,%eax\ncmp %esi,%ebx\nje 13a0 \nmovslq %ecx,%r11\ncmp (%rdi,%r11,4),%r8d\nlea 0x0(,%r11,4),%r10\nsete %r11b\nmovzbl %r11b,%r11d\nadd %r11d,%eax\nlea 0x1(%rcx),%r11d\ncmp %esi,%r11d\njge 13a0 \ncmp 0x4(%rdi,%r10,1),%r8d\njne 1376 \nadd $0x1,%eax\nlea 0x2(%rcx),%r11d\ncmp %r11d,%esi\njle 13a0 \ncmp 0x8(%rdi,%r10,1),%r8d\njne 1389 \nadd $0x1,%eax\nadd $0x3,%ecx\ncmp %ecx,%esi\njle 13a0 \ncmp 0xc(%rdi,%r10,1),%r8d\njne 13a0 \nadd $0x1,%eax\nnopw 0x0(%rax,%rax,1)\ntest $0x1,%al\njne 13b7 \nadd $0x4,%r9\ncmp %r12,%r9\njne 12f0 \nmov $0xffffffff,%r8d\npop %rbx\nmov %r8d,%eax\npop %rbp\npop %r12\nretq\nxor %ecx,%ecx\nxor %eax,%eax\njmp 1349 \nmov $0xffffffff,%r8d\nmov %r8d,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle loc_13B6\nmov edx, esi\npush r12\nmovsxd rax, esi\nmov r12d, esi\nshr edx, 2\npush rbp\nmov r8, rdi\nmov r9d, esi\nshl rdx, 4\npush rbx\nlea r11d, [rsi-1]\nlea rbx, [rdi+rax*4]\nadd rdx, rdi\nand r12d, 0FFFFFFFCh\nnop dword ptr [rax+00h]\nloc_12F8:\nmov esi, [rdi]\ncmp r11d, 2\njbe loc_13B0\nmovd xmm3, esi\nmov rax, r8\npxor xmm0, xmm0\npshufd xmm2, xmm3, 0\nnop dword ptr [rax+00h]\nloc_1318:\nmovdqu xmm1, xmmword ptr [rax]\nadd rax, 10h\npcmpeqd xmm1, xmm2\npsubd xmm0, xmm1\ncmp rdx, rax\njnz short loc_1318\nmovdqa xmm1, xmm0\nmov ecx, r12d\npsrldq xmm1, 8\npaddd xmm0, xmm1\nmovdqa xmm1, xmm0\npsrldq xmm1, 4\npaddd xmm0, xmm1\nmovd eax, xmm0\ncmp r9d, r12d\njz short loc_138C\nloc_1353:\nmovsxd r10, ecx\nlea rbp, ds:0[r10*4]\ncmp esi, [r8+r10*4]\njnz short loc_1367\nadd eax, 1\nloc_1367:\nlea r10d, [rcx+1]\ncmp r9d, r10d\njle short loc_138C\ncmp esi, [r8+rbp+4]\njnz short loc_137A\nadd eax, 1\nloc_137A:\nadd ecx, 2\ncmp r9d, ecx\njle short loc_138C\ncmp esi, [r8+rbp+8]\njnz short loc_138C\nadd eax, 1\nloc_138C:\ntest al, 1\njnz short loc_13A2\nadd rdi, 4\ncmp rbx, rdi\njnz loc_12F8\nmov esi, 0FFFFFFFFh\nloc_13A2:\npop rbx\nmov eax, esi\npop rbp\npop r12\nretn\nloc_13B0:\nxor ecx, ecx\nxor eax, eax\njmp short loc_1353\nloc_13B6:\nmov eax, 0FFFFFFFFh\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n const __m128i *v2; // r8\n unsigned int v4; // r11d\n unsigned int *v5; // rbx\n const __m128i *v6; // rdx\n unsigned int v7; // r12d\n unsigned int v8; // esi\n const __m128i *v9; // rax\n __m128i v10; // xmm0\n __m128i v11; // xmm2\n __m128i v12; // xmm1\n signed int v13; // ecx\n __m128i v14; // xmm0\n char v15; // al\n __int64 v16; // rbp\n\n if ( a2 <= 0 )\n return 0xFFFFFFFFLL;\n v2 = (const __m128i *)a1;\n v4 = a2 - 1;\n v5 = &a1[a2];\n v6 = (const __m128i *)&a1[4 * ((unsigned int)a2 >> 2)];\n v7 = a2 & 0xFFFFFFFC;\n do\n {\n v8 = *a1;\n if ( v4 <= 2 )\n {\n v13 = 0;\n v15 = 0;\n }\n else\n {\n v9 = v2;\n v10 = 0LL;\n v11 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v8), 0);\n do\n {\n v12 = _mm_loadu_si128(v9++);\n v10 = _mm_sub_epi32(v10, _mm_cmpeq_epi32(v12, v11));\n }\n while ( v6 != v9 );\n v13 = v7;\n v14 = _mm_add_epi32(v10, _mm_srli_si128(v10, 8));\n v15 = _mm_cvtsi128_si32(_mm_add_epi32(v14, _mm_srli_si128(v14, 4)));\n if ( a2 == v7 )\n goto LABEL_15;\n }\n v16 = v13;\n if ( v8 == v2->m128i_i32[v16] )\n ++v15;\n if ( a2 > v13 + 1 )\n {\n if ( v8 == v2->m128i_i32[v16 + 1] )\n ++v15;\n if ( a2 > v13 + 2 && v8 == v2->m128i_i32[v16 + 2] )\n ++v15;\n }\nLABEL_15:\n if ( (v15 & 1) != 0 )\n return v8;\n ++a1;\n }\n while ( v5 != a1 );\n return (unsigned int)-1;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\ntest esi, esi\njle loc_13B6\nmov edx, esi\npush r12\nmovsxd rax, esi\nmov r12d, esi\nshr edx, 2\npush rbp\nmov r8, rdi\nmov r9d, esi\nshl rdx, 4\npush rbx\nlea r11d, [rsi-1]\nlea rbx, [rdi+rax*4]\nadd rdx, rdi\nand r12d, 0FFFFFFFCh\nnop dword ptr [rax+00h]\nloc_12F8:\nmov esi, [rdi]\ncmp r11d, 2\njbe loc_13B0\nmovd xmm3, esi\nmov rax, r8\npxor xmm0, xmm0\npshufd xmm2, xmm3, 0\nnop dword ptr [rax+00h]\nloc_1318:\nmovdqu xmm1, xmmword ptr [rax]\nadd rax, 10h\npcmpeqd xmm1, xmm2\npsubd xmm0, xmm1\ncmp rdx, rax\njnz short loc_1318\nmovdqa xmm1, xmm0\nmov ecx, r12d\npsrldq xmm1, 8\npaddd xmm0, xmm1\nmovdqa xmm1, xmm0\npsrldq xmm1, 4\npaddd xmm0, xmm1\nmovd eax, xmm0\ncmp r9d, r12d\njz short loc_138C\nloc_1353:\nmovsxd r10, ecx\nlea rbp, ds:0[r10*4]\ncmp esi, [r8+r10*4]\njnz short loc_1367\nadd eax, 1\nloc_1367:\nlea r10d, [rcx+1]\ncmp r9d, r10d\njle short loc_138C\ncmp esi, [r8+rbp+4]\njnz short loc_137A\nadd eax, 1\nloc_137A:\nadd ecx, 2\ncmp r9d, ecx\njle short loc_138C\ncmp esi, [r8+rbp+8]\njnz short loc_138C\nadd eax, 1\nloc_138C:\ntest al, 1\njnz short loc_13A2\nadd rdi, 4\ncmp rbx, rdi\njnz loc_12F8\nmov esi, 0FFFFFFFFh\nloc_13A2:\npop rbx\nmov eax, esi\npop rbp\npop r12\nretn\nloc_13B0:\nxor ecx, ecx\nxor eax, eax\njmp short loc_1353\nloc_13B6:\nmov eax, 0FFFFFFFFh\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12C0(unsigned int *a1, int a2)\n{\n const __m128i *v2; // r8\n unsigned int v4; // r11d\n unsigned int *v5; // rbx\n const __m128i *v6; // rdx\n unsigned int v7; // r12d\n unsigned int v8; // esi\n const __m128i *v9; // rax\n __m128i v10; // xmm0\n __m128i v11; // xmm2\n __m128i v12; // xmm1\n signed int v13; // ecx\n __m128i v14; // xmm0\n char v15; // al\n __int64 v16; // rbp\n\n if ( a2 <= 0 )\n return 0xFFFFFFFFLL;\n v2 = (const __m128i *)a1;\n v4 = a2 - 1;\n v5 = &a1[a2];\n v6 = (const __m128i *)&a1[4 * ((unsigned int)a2 >> 2)];\n v7 = a2 & 0xFFFFFFFC;\n do\n {\n v8 = *a1;\n if ( v4 <= 2 )\n {\n v13 = 0;\n v15 = 0;\n }\n else\n {\n v9 = v2;\n v10 = 0LL;\n v11 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v8), 0);\n do\n {\n v12 = _mm_loadu_si128(v9++);\n v10 = _mm_sub_epi32(v10, _mm_cmpeq_epi32(v12, v11));\n }\n while ( v6 != v9 );\n v13 = v7;\n v14 = _mm_add_epi32(v10, _mm_srli_si128(v10, 8));\n v15 = _mm_cvtsi128_si32(_mm_add_epi32(v14, _mm_srli_si128(v14, 4)));\n if ( a2 == v7 )\n goto LABEL_15;\n }\n v16 = v13;\n if ( v8 == v2->m128i_i32[v16] )\n ++v15;\n if ( a2 > v13 + 1 )\n {\n if ( v8 == v2->m128i_i32[v16 + 1] )\n ++v15;\n if ( a2 > v13 + 2 && v8 == v2->m128i_i32[v16 + 2] )\n ++v15;\n }\nLABEL_15:\n if ( (v15 & 1) != 0 )\n return v8;\n ++a1;\n }\n while ( v5 != a1 );\n return (unsigned int)-1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12C0(unsigned int *a1, int a2) {\n const __m128i *v2;\n unsigned int v4;\n unsigned int *v5;\n const __m128i *v6;\n unsigned int v7;\n unsigned int v8;\n const __m128i *v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n signed int v13;\n __m128i v14;\n char v15;\n long long v16;\n if (a2 <= 0) return 4294967295LL;\n v2 = (const __m128i *)a1;\n v4 = a2 - 1;\n v5 = &a1[a2];\n v6 = (const __m128i *)&a1[4 * ((unsigned int)a2 >> 2)];\n v7 = a2 & 4294967292;\n do {\n v8 = *a1;\n if (v4 <= 2) {\n v13 = 0;\n v15 = 0;\n } else {\n v9 = v2;\n v10 = 0LL;\n v11 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v8), 0);\n do {\n v12 = _mm_loadu_si128(v9++);\n v10 = _mm_sub_epi32(v10, _mm_cmpeq_epi32(v12, v11));\n } while (v6 != v9);\n v13 = v7;\n v14 = _mm_add_epi32(v10, _mm_srli_si128(v10, 8));\n v15 = _mm_cvtsi128_si32(_mm_add_epi32(v14, _mm_srli_si128(v14, 4)));\n if (a2 == v7) goto LABEL_15;\n }\n v16 = v13;\n if (v8 == v2->m128i_i32[v16]) ++v15;\n if (a2 > v13 + 1) {\n if (v8 == v2->m128i_i32[v16 + 1]) ++v15;\n if (a2 > v13 + 2 && v8 == v2->m128i_i32[v16 + 2]) ++v15;\n }\n LABEL_15:\n if ((v15 & 1) != 0) return v8;\n ++a1;\n } while (v5 != a1);\n return (unsigned int)-1;\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n const __m128i *v2;\n unsigned int v4;\n unsigned int *v5;\n const __m128i *v6;\n unsigned int v7;\n unsigned int v8;\n const __m128i *v9;\n __m128i v10;\n __m128i v11;\n __m128i v12;\n signed int v13;\n __m128i v14;\n char v15;\n long long v16;\n if (a2 <= 0) return 4294967295LL;\n v2 = (const __m128i *)a1;\n v4 = a2 - 1;\n v5 = &a1[a2];\n v6 = (const __m128i *)&a1[4 * ((unsigned int)a2 >> 2)];\n v7 = a2 & 4294967292;\n do {\n v8 = *a1;\n if (v4 <= 2) {\n v13 = 0;\n v15 = 0;\n } else {\n v9 = v2;\n v10 = 0LL;\n v11 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v8), 0);\n do {\n v12 = _mm_loadu_si128(v9++);\n v10 = _mm_sub_epi32(v10, _mm_cmpeq_epi32(v12, v11));\n } while (v6 != v9);\n v13 = v7;\n v14 = _mm_add_epi32(v10, _mm_srli_si128(v10, 8));\n v15 = _mm_cvtsi128_si32(_mm_add_epi32(v14, _mm_srli_si128(v14, 4)));\n if (a2 == v7) goto LABEL_15;\n }\n v16 = v13;\n if (v8 == v2->m128i_i32[v16]) ++v15;\n if (a2 > v13 + 1) {\n if (v8 == v2->m128i_i32[v16 + 1]) ++v15;\n if (a2 > v13 + 2 && v8 == v2->m128i_i32[v16 + 2]) ++v15;\n }\n LABEL_15:\n if ((v15 & 1) != 0) return v8;\n ++a1;\n } while (v5 != a1);\n return (unsigned int)-1;\n}" + }, + { + "index": 843, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint cmp(const void *a, const void *b) {\n\n long long num1 = *(const long long*)a;\n\n long long num2 = *(const long long*)b;\n\n return (num1 > num2) - (num1 < num2); \n\n}\n\n\n\n", + "func": "long long func0(int n, int* primes, int primesSize) {\n long long* uglies = malloc(n * sizeof(long long));\n int* indices = calloc(primesSize, sizeof(int));\n long long* values = malloc(primesSize * sizeof(long long));\n int i, j;\n uglies[0] = 1;\n for (i = 0; i < primesSize; i++) {\n values[i] = primes[i];\n }\n for (i = 1; i < n; i++) {\n long long next_ugly = values[0];\n for (j = 1; j < primesSize; j++) {\n if (values[j] < next_ugly) next_ugly = values[j];\n }\n uglies[i] = next_ugly;\n for (j = 0; j < primesSize; j++) {\n if (values[j] == next_ugly) values[j] = primes[j] * uglies[++indices[j]];\n }\n }\n long long result = uglies[n - 1];\n free(uglies);\n free(indices);\n free(values);\n return result;\n}", + "test": "int main() {\n\n int primes1[] = {2, 7, 13, 19};\n\n int primesSize1 = sizeof(primes1) / sizeof(primes1[0]);\n\n assert(func0(12, primes1, primesSize1) == 32);\n\n assert(func0(10, primes1, primesSize1) == 26);\n\n assert(func0(100, primes1, primesSize1) == 5408);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x40,%rsp\nmov %edi,-0x34(%rbp)\nmov %rsi,-0x40(%rbp)\nmov %edx,-0x38(%rbp)\nmov -0x34(%rbp),%eax\ncltq\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,-0x20(%rbp)\nmov -0x38(%rbp),%eax\ncltq\nmov $0x4,%esi\nmov %rax,%rdi\ncallq 10c0 \nmov %rax,-0x18(%rbp)\nmov -0x38(%rbp),%eax\ncltq\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,-0x10(%rbp)\nmov -0x20(%rbp),%rax\nmovq $0x1,(%rax)\nmovl $0x0,-0x30(%rbp)\njmp 12af \nmov -0x30(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x40(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov -0x30(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x10(%rbp),%rdx\nadd %rcx,%rdx\ncltq\nmov %rax,(%rdx)\naddl $0x1,-0x30(%rbp)\nmov -0x30(%rbp),%eax\ncmp -0x38(%rbp),%eax\njl 127b \nmovl $0x1,-0x30(%rbp)\njmpq 13d9 \nmov -0x10(%rbp),%rax\nmov (%rax),%rax\nmov %rax,-0x28(%rbp)\nmovl $0x1,-0x2c(%rbp)\njmp 1313 \nmov -0x2c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x10(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\ncmp %rax,-0x28(%rbp)\njle 130f \nmov -0x2c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x10(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov %rax,-0x28(%rbp)\naddl $0x1,-0x2c(%rbp)\nmov -0x2c(%rbp),%eax\ncmp -0x38(%rbp),%eax\njl 12d7 \nmov -0x30(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x20(%rbp),%rax\nadd %rax,%rdx\nmov -0x28(%rbp),%rax\nmov %rax,(%rdx)\nmovl $0x0,-0x2c(%rbp)\njmpq 13c9 \nmov -0x2c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x10(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\ncmp %rax,-0x28(%rbp)\njne 13c5 \nmov -0x2c(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x40(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmovslq %eax,%rcx\nmov -0x2c(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nadd $0x1,%edx\nmov %edx,(%rax)\nmov (%rax),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0x2c(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rsi\nmov -0x10(%rbp),%rdx\nadd %rsi,%rdx\nimul %rcx,%rax\nmov %rax,(%rdx)\naddl $0x1,-0x2c(%rbp)\nmov -0x2c(%rbp),%eax\ncmp -0x38(%rbp),%eax\njl 1342 \naddl $0x1,-0x30(%rbp)\nmov -0x30(%rbp),%eax\ncmp -0x34(%rbp),%eax\njl 12c3 \nmov -0x34(%rbp),%eax\ncltq\nshl $0x3,%rax\nlea -0x8(%rax),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov %rax,-0x8(%rbp)\nmov -0x20(%rbp),%rax\nmov %rax,%rdi\ncallq 1090 \nmov -0x18(%rbp),%rax\nmov %rax,%rdi\ncallq 1090 \nmov -0x10(%rbp),%rax\nmov %rax,%rdi\ncallq 1090 \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_34], edi\nmov [rbp+var_40], rsi\nmov [rbp+var_38], edx\nmov eax, [rbp+var_34]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov eax, [rbp+var_38]\ncdqe\nmov esi, 4; size\nmov rdi, rax; nmemb\ncall _calloc\nmov [rbp+var_18], rax\nmov eax, [rbp+var_38]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_10], rax\nmov rax, [rbp+ptr]\nmov qword ptr [rax], 1\nmov [rbp+var_30], 0\njmp short loc_12AF\nloc_127B:\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_30]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_10]\nadd rdx, rcx\ncdqe\nmov [rdx], rax\nadd [rbp+var_30], 1\nloc_12AF:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_38]\njl short loc_127B\nmov [rbp+var_30], 1\njmp loc_13D9\nloc_12C3:\nmov rax, [rbp+var_10]\nmov rax, [rax]\nmov [rbp+var_28], rax\nmov [rbp+var_2C], 1\njmp short loc_1313\nloc_12D7:\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_10]\nadd rax, rdx\nmov rax, [rax]\ncmp [rbp+var_28], rax\njle short loc_130F\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_10]\nadd rax, rdx\nmov rax, [rax]\nmov [rbp+var_28], rax\nloc_130F:\nadd [rbp+var_2C], 1\nloc_1313:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_38]\njl short loc_12D7\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov rax, [rbp+var_28]\nmov [rdx], rax\nmov [rbp+var_2C], 0\njmp loc_13C9\nloc_1342:\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_10]\nadd rax, rdx\nmov rax, [rax]\ncmp [rbp+var_28], rax\njnz short loc_13C5\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nadd rax, rdx\nmov eax, [rax]\nmovsxd rdx, eax\nmov eax, [rbp+var_2C]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov ecx, [rax]\nadd ecx, 1\nmov [rax], ecx\nmov eax, [rax]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rcx\nmov rax, [rax]\nmov ecx, [rbp+var_2C]\nmovsxd rcx, ecx\nlea rsi, ds:0[rcx*8]\nmov rcx, [rbp+var_10]\nadd rcx, rsi\nimul rax, rdx\nmov [rcx], rax\nloc_13C5:\nadd [rbp+var_2C], 1\nloc_13C9:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_38]\njl loc_1342\nadd [rbp+var_30], 1\nloc_13D9:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_34]\njl loc_12C3\nmov eax, [rbp+var_34]\ncdqe\nshl rax, 3\nlea rdx, [rax-8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rax, [rax]\nmov [rbp+var_8], rax\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_18]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_10]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, __int64 a2, int a3)\n{\n __int64 v3; // rdx\n char *v4; // rax\n int i; // [rsp+10h] [rbp-30h]\n int j; // [rsp+10h] [rbp-30h]\n int k; // [rsp+14h] [rbp-2Ch]\n int m; // [rsp+14h] [rbp-2Ch]\n __int64 v11; // [rsp+18h] [rbp-28h]\n _QWORD *ptr; // [rsp+20h] [rbp-20h]\n char *v13; // [rsp+28h] [rbp-18h]\n __int64 *v14; // [rsp+30h] [rbp-10h]\n __int64 v15; // [rsp+38h] [rbp-8h]\n\n ptr = malloc(8LL * a1);\n v13 = (char *)calloc(a3, 4uLL);\n v14 = (__int64 *)malloc(8LL * a3);\n *ptr = 1LL;\n for ( i = 0; i < a3; ++i )\n v14[i] = *(int *)(4LL * i + a2);\n for ( j = 1; j < a1; ++j )\n {\n v11 = *v14;\n for ( k = 1; k < a3; ++k )\n {\n if ( v11 > v14[k] )\n v11 = v14[k];\n }\n ptr[j] = v11;\n for ( m = 0; m < a3; ++m )\n {\n if ( v11 == v14[m] )\n {\n v3 = *(int *)(4LL * m + a2);\n v4 = &v13[4 * m];\n v14[m] = v3 * ptr[++*(_DWORD *)v4];\n }\n }\n }\n v15 = ptr[a1 - 1];\n free(ptr);\n free(v13);\n free(v14);\n return v15;\n}", + "ida_strip_asm": "sub_1211:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_34], edi\nmov [rbp+var_40], rsi\nmov [rbp+var_38], edx\nmov eax, [rbp+var_34]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov eax, [rbp+var_38]\ncdqe\nmov esi, 4; size\nmov rdi, rax; nmemb\ncall _calloc\nmov [rbp+var_18], rax\nmov eax, [rbp+var_38]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_10], rax\nmov rax, [rbp+ptr]\nmov qword ptr [rax], 1\nmov [rbp+var_30], 0\njmp short loc_12AF\nloc_127B:\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_30]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_10]\nadd rdx, rcx\ncdqe\nmov [rdx], rax\nadd [rbp+var_30], 1\nloc_12AF:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_38]\njl short loc_127B\nmov [rbp+var_30], 1\njmp loc_13D9\nloc_12C3:\nmov rax, [rbp+var_10]\nmov rax, [rax]\nmov [rbp+var_28], rax\nmov [rbp+var_2C], 1\njmp short loc_1313\nloc_12D7:\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_10]\nadd rax, rdx\nmov rax, [rax]\ncmp [rbp+var_28], rax\njle short loc_130F\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_10]\nadd rax, rdx\nmov rax, [rax]\nmov [rbp+var_28], rax\nloc_130F:\nadd [rbp+var_2C], 1\nloc_1313:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_38]\njl short loc_12D7\nmov eax, [rbp+var_30]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov rax, [rbp+var_28]\nmov [rdx], rax\nmov [rbp+var_2C], 0\njmp loc_13C9\nloc_1342:\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_10]\nadd rax, rdx\nmov rax, [rax]\ncmp [rbp+var_28], rax\njnz short loc_13C5\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nadd rax, rdx\nmov eax, [rax]\nmovsxd rdx, eax\nmov eax, [rbp+var_2C]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov ecx, [rax]\nadd ecx, 1\nmov [rax], ecx\nmov eax, [rax]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+ptr]\nadd rax, rcx\nmov rax, [rax]\nmov ecx, [rbp+var_2C]\nmovsxd rcx, ecx\nlea rsi, ds:0[rcx*8]\nmov rcx, [rbp+var_10]\nadd rcx, rsi\nimul rax, rdx\nmov [rcx], rax\nloc_13C5:\nadd [rbp+var_2C], 1\nloc_13C9:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_38]\njl loc_1342\nadd [rbp+var_30], 1\nloc_13D9:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_34]\njl loc_12C3\nmov eax, [rbp+var_34]\ncdqe\nshl rax, 3\nlea rdx, [rax-8]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rax, [rax]\nmov [rbp+var_8], rax\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_18]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_10]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1211(int a1, __int64 a2, int a3)\n{\n __int64 v3; // rdx\n char *v4; // rax\n int i; // [rsp+10h] [rbp-30h]\n int j; // [rsp+10h] [rbp-30h]\n int k; // [rsp+14h] [rbp-2Ch]\n int m; // [rsp+14h] [rbp-2Ch]\n __int64 v11; // [rsp+18h] [rbp-28h]\n _QWORD *ptr; // [rsp+20h] [rbp-20h]\n char *v13; // [rsp+28h] [rbp-18h]\n __int64 *v14; // [rsp+30h] [rbp-10h]\n __int64 v15; // [rsp+38h] [rbp-8h]\n\n ptr = malloc(8LL * a1);\n v13 = (char *)calloc(a3, 4uLL);\n v14 = (__int64 *)malloc(8LL * a3);\n *ptr = 1LL;\n for ( i = 0; i < a3; ++i )\n v14[i] = *(int *)(4LL * i + a2);\n for ( j = 1; j < a1; ++j )\n {\n v11 = *v14;\n for ( k = 1; k < a3; ++k )\n {\n if ( v11 > v14[k] )\n v11 = v14[k];\n }\n ptr[j] = v11;\n for ( m = 0; m < a3; ++m )\n {\n if ( v11 == v14[m] )\n {\n v3 = *(int *)(4LL * m + a2);\n v4 = &v13[4 * m];\n v14[m] = v3 * ptr[++*(_DWORD *)v4];\n }\n }\n }\n v15 = ptr[a1 - 1];\n free(ptr);\n free(v13);\n free(v14);\n return v15;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1211(int a1, long long a2, int a3) {\n long long v3;\n char *v4;\n int i;\n int j;\n int k;\n int m;\n long long v11;\n uint64_t *ptr;\n char *v13;\n long long *v14;\n long long v15;\n ptr = malloc(8LL * a1);\n v13 = (char *)calloc(a3, 4uLL);\n v14 = (long long *)malloc(8LL * a3);\n *ptr = 1LL;\n for (i = 0; i < a3; ++i) v14[i] = *(int *)(4LL * i + a2);\n for (j = 1; j < a1; ++j) {\n v11 = *v14;\n for (k = 1; k < a3; ++k) {\n if (v11 > v14[k]) v11 = v14[k];\n }\n ptr[j] = v11;\n for (m = 0; m < a3; ++m) {\n if (v11 == v14[m]) {\n v3 = *(int *)(4LL * m + a2);\n v4 = &v13[4 * m];\n v14[m] = v3 * ptr[++*(uint32_t *)v4];\n }\n }\n }\n v15 = ptr[a1 - 1];\n free(ptr);\n free(v13);\n free(v14);\n return v15;\n}", + "ida_pseudo_norm": "long long func0(int a1, long long a2, int a3) {\n long long v3;\n char *v4;\n int i;\n int j;\n int k;\n int m;\n long long v11;\n uint64_t *ptr;\n char *v13;\n long long *v14;\n long long v15;\n ptr = malloc(8LL * a1);\n v13 = (char *)calloc(a3, 4uLL);\n v14 = (long long *)malloc(8LL * a3);\n *ptr = 1LL;\n for (i = 0; i < a3; ++i) v14[i] = *(int *)(4LL * i + a2);\n for (j = 1; j < a1; ++j) {\n v11 = *v14;\n for (k = 1; k < a3; ++k) {\n if (v11 > v14[k]) v11 = v14[k];\n }\n ptr[j] = v11;\n for (m = 0; m < a3; ++m) {\n if (v11 == v14[m]) {\n v3 = *(int *)(4LL * m + a2);\n v4 = &v13[4 * m];\n v14[m] = v3 * ptr[++*(uint32_t *)v4];\n }\n }\n }\n v15 = ptr[a1 - 1];\n free(ptr);\n free(v13);\n free(v14);\n return v15;\n}" + }, + { + "index": 843, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint cmp(const void *a, const void *b) {\n\n long long num1 = *(const long long*)a;\n\n long long num2 = *(const long long*)b;\n\n return (num1 > num2) - (num1 < num2); \n\n}\n\n\n\n", + "func": "long long func0(int n, int* primes, int primesSize) {\n long long* uglies = malloc(n * sizeof(long long));\n int* indices = calloc(primesSize, sizeof(int));\n long long* values = malloc(primesSize * sizeof(long long));\n int i, j;\n uglies[0] = 1;\n for (i = 0; i < primesSize; i++) {\n values[i] = primes[i];\n }\n for (i = 1; i < n; i++) {\n long long next_ugly = values[0];\n for (j = 1; j < primesSize; j++) {\n if (values[j] < next_ugly) next_ugly = values[j];\n }\n uglies[i] = next_ugly;\n for (j = 0; j < primesSize; j++) {\n if (values[j] == next_ugly) values[j] = primes[j] * uglies[++indices[j]];\n }\n }\n long long result = uglies[n - 1];\n free(uglies);\n free(indices);\n free(values);\n return result;\n}", + "test": "int main() {\n\n int primes1[] = {2, 7, 13, 19};\n\n int primesSize1 = sizeof(primes1) / sizeof(primes1[0]);\n\n assert(func0(12, primes1, primesSize1) == 32);\n\n assert(func0(10, primes1, primesSize1) == 26);\n\n assert(func0(100, primes1, primesSize1) == 5408);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov %edi,%r15d\nmov %rsi,%r13\nmov %edx,%ebp\nmovslq %edi,%rax\nshl $0x3,%rax\nmov %rax,0x8(%rsp)\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,%r14\nmovslq %ebp,%rbx\nmov $0x4,%esi\nmov %rbx,%rdi\ncallq 10c0 \nmov %rax,%r12\nlea 0x0(,%rbx,8),%rdi\ncallq 10d0 \nmov %rax,%rbx\nmovq $0x1,(%r14)\ntest %ebp,%ebp\njle 1261 \nlea -0x1(%rbp),%ecx\nmov $0x0,%eax\nmovslq 0x0(%r13,%rax,4),%rdx\nmov %rdx,(%rbx,%rax,8)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rcx,%rdx\njne 124c \ncmp $0x1,%r15d\njle 12e1 \nlea 0x8(%r14),%rdi\nlea -0x2(%r15),%eax\nlea 0x10(%r14,%rax,8),%r8\nlea -0x2(%rbp),%eax\nlea 0x10(%rbx,%rax,8),%rsi\njmp 128c \nmov %rdx,(%rdi)\nje 12ae \nadd $0x8,%rdi\ncmp %r8,%rdi\nje 12e1 \nmov (%rbx),%rdx\ncmp $0x1,%ebp\njle 127e \nlea 0x8(%rbx),%rax\nmov (%rax),%rcx\ncmp %rcx,%rdx\ncmovg %rcx,%rdx\nadd $0x8,%rax\ncmp %rsi,%rax\njne 1298 \nmov %rdx,(%rdi)\nmov $0x0,%eax\njmp 12bd \nadd $0x1,%rax\ncmp %eax,%ebp\njle 1283 \ncmp %rdx,(%rbx,%rax,8)\njne 12b5 \nmovslq 0x0(%r13,%rax,4),%r9\nmov (%r12,%rax,4),%ecx\nadd $0x1,%ecx\nmov %ecx,(%r12,%rax,4)\nmovslq %ecx,%rcx\nimul (%r14,%rcx,8),%r9\nmov %r9,(%rbx,%rax,8)\njmp 12b5 \nmov 0x8(%rsp),%rax\nmov -0x8(%r14,%rax,1),%rbp\nmov %r14,%rdi\ncallq 1090 \nmov %r12,%rdi\ncallq 1090 \nmov %rbx,%rdi\ncallq 1090 \nmov %rbp,%rax\nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_3C], edi\nmov r13, rsi\nmov r15d, edx\nmovsxd rax, edi\nshl rax, 3\nmov [rsp+48h+var_48], rax\nmov rdi, rax; size\ncall _malloc\nmov r14, rax\nmovsxd rbp, r15d\nmov esi, 4; size\nmov rdi, rbp; nmemb\ncall _calloc\nmov r12, rax\nlea rdi, ds:0[rbp*8]; size\ncall _malloc\nmov rbx, rax\nmov qword ptr [r14], 1\ntest r15d, r15d\njle short loc_125A\nmov eax, 0\nloc_1248:\nmovsxd rdx, dword ptr [r13+rax*4+0]\nmov [rbx+rax*8], rdx\nadd rax, 1\ncmp rbp, rax\njnz short loc_1248\nloc_125A:\nmov eax, [rsp+48h+var_3C]\ncmp eax, 1\njle loc_12EA\nlea rdi, [r14+8]\nlea eax, [rax-2]\nlea r8, [r14+rax*8+10h]\nlea eax, [r15-2]\nlea rsi, [rbx+rax*8+10h]\nshl rbp, 2\njmp short loc_1293\nloc_1282:\nmov [rdi], rdx\ntest r15d, r15d\njg short loc_12B6\nloc_128A:\nadd rdi, 8\ncmp rdi, r8\njz short loc_12EA\nloc_1293:\nmov rdx, [rbx]\ncmp r15d, 1\njle short loc_1282\nlea rax, [rbx+8]\nloc_12A0:\nmov rcx, [rax]\ncmp rdx, rcx\ncmovg rdx, rcx\nadd rax, 8\ncmp rax, rsi\njnz short loc_12A0\nmov [rdi], rdx\nloc_12B6:\nmov eax, 0\njmp short loc_12C6\nloc_12BD:\nadd rax, 4\ncmp rbp, rax\njz short loc_128A\nloc_12C6:\ncmp [rbx+rax*2], rdx\njnz short loc_12BD\nmovsxd r9, dword ptr [r13+rax+0]\nmov ecx, [r12+rax]\nadd ecx, 1\nmov [r12+rax], ecx\nmovsxd rcx, ecx\nimul r9, [r14+rcx*8]\nmov [rbx+rax*2], r9\njmp short loc_12BD\nloc_12EA:\nmov rax, [rsp+48h+var_48]\nmov rbp, [r14+rax-8]\nmov rdi, r14; ptr\ncall _free\nmov rdi, r12; ptr\ncall _free\nmov rdi, rbx; ptr\ncall _free\nmov rax, rbp\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, __int64 a2, int a3)\n{\n _QWORD *v4; // r14\n char *v5; // r12\n __int64 *v6; // rbx\n __int64 v7; // rax\n _QWORD *v8; // rdi\n __int64 v9; // rdx\n __int64 *v10; // rax\n __int64 v11; // rax\n __int64 v12; // r9\n int v13; // ecx\n __int64 v14; // rbp\n size_t v16; // [rsp+0h] [rbp-48h]\n\n v16 = a1;\n v4 = malloc(v16 * 8);\n v5 = (char *)calloc(a3, 4uLL);\n v6 = (__int64 *)malloc(8LL * a3);\n *v4 = 1LL;\n if ( a3 > 0 )\n {\n v7 = 0LL;\n do\n {\n v6[v7] = *(int *)(a2 + 4 * v7);\n ++v7;\n }\n while ( a3 != v7 );\n }\n if ( a1 > 1 )\n {\n v8 = v4 + 1;\n while ( 1 )\n {\n v9 = *v6;\n if ( a3 > 1 )\n break;\n *v8 = v9;\n if ( a3 > 0 )\n goto LABEL_14;\nLABEL_7:\n if ( ++v8 == &v4[(unsigned int)(a1 - 2) + 2] )\n goto LABEL_18;\n }\n v10 = v6 + 1;\n do\n {\n if ( v9 > *v10 )\n v9 = *v10;\n ++v10;\n }\n while ( v10 != &v6[(unsigned int)(a3 - 2) + 2] );\n *v8 = v9;\nLABEL_14:\n v11 = 0LL;\n do\n {\n if ( v6[v11] == v9 )\n {\n v12 = *(int *)(a2 + v11 * 4);\n v13 = *(_DWORD *)&v5[v11 * 4] + 1;\n *(_DWORD *)&v5[v11 * 4] = v13;\n v6[v11] = v4[v13] * v12;\n }\n ++v11;\n }\n while ( a3 != v11 );\n goto LABEL_7;\n }\nLABEL_18:\n v14 = v4[v16 - 1];\n free(v4);\n free(v5);\n free(v6);\n return v14;\n}", + "ida_strip_asm": "sub_11E2:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_3C], edi\nmov r13, rsi\nmov r15d, edx\nmovsxd rax, edi\nshl rax, 3\nmov [rsp+48h+var_48], rax\nmov rdi, rax; size\ncall _malloc\nmov r14, rax\nmovsxd rbp, r15d\nmov esi, 4; size\nmov rdi, rbp; nmemb\ncall _calloc\nmov r12, rax\nlea rdi, ds:0[rbp*8]; size\ncall _malloc\nmov rbx, rax\nmov qword ptr [r14], 1\ntest r15d, r15d\njle short loc_125A\nmov eax, 0\nloc_1248:\nmovsxd rdx, dword ptr [r13+rax*4+0]\nmov [rbx+rax*8], rdx\nadd rax, 1\ncmp rbp, rax\njnz short loc_1248\nloc_125A:\nmov eax, [rsp+48h+var_3C]\ncmp eax, 1\njle loc_12EA\nlea rdi, [r14+8]\nlea eax, [rax-2]\nlea r8, [r14+rax*8+10h]\nlea eax, [r15-2]\nlea rsi, [rbx+rax*8+10h]\nshl rbp, 2\njmp short loc_1293\nloc_1282:\nmov [rdi], rdx\ntest r15d, r15d\njg short loc_12B6\nloc_128A:\nadd rdi, 8\ncmp rdi, r8\njz short loc_12EA\nloc_1293:\nmov rdx, [rbx]\ncmp r15d, 1\njle short loc_1282\nlea rax, [rbx+8]\nloc_12A0:\nmov rcx, [rax]\ncmp rdx, rcx\ncmovg rdx, rcx\nadd rax, 8\ncmp rax, rsi\njnz short loc_12A0\nmov [rdi], rdx\nloc_12B6:\nmov eax, 0\njmp short loc_12C6\nloc_12BD:\nadd rax, 4\ncmp rbp, rax\njz short loc_128A\nloc_12C6:\ncmp [rbx+rax*2], rdx\njnz short loc_12BD\nmovsxd r9, dword ptr [r13+rax+0]\nmov ecx, [r12+rax]\nadd ecx, 1\nmov [r12+rax], ecx\nmovsxd rcx, ecx\nimul r9, [r14+rcx*8]\nmov [rbx+rax*2], r9\njmp short loc_12BD\nloc_12EA:\nmov rax, [rsp+48h+var_48]\nmov rbp, [r14+rax-8]\nmov rdi, r14; ptr\ncall _free\nmov rdi, r12; ptr\ncall _free\nmov rdi, rbx; ptr\ncall _free\nmov rax, rbp\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11E2(int a1, __int64 a2, int a3)\n{\n _QWORD *v4; // r14\n char *v5; // r12\n __int64 *v6; // rbx\n __int64 v7; // rax\n _QWORD *v8; // rdi\n __int64 v9; // rdx\n __int64 *v10; // rax\n __int64 v11; // rax\n __int64 v12; // r9\n int v13; // ecx\n __int64 v14; // rbp\n size_t v16; // [rsp+0h] [rbp-48h]\n\n v16 = a1;\n v4 = malloc(v16 * 8);\n v5 = (char *)calloc(a3, 4uLL);\n v6 = (__int64 *)malloc(8LL * a3);\n *v4 = 1LL;\n if ( a3 > 0 )\n {\n v7 = 0LL;\n do\n {\n v6[v7] = *(int *)(a2 + 4 * v7);\n ++v7;\n }\n while ( a3 != v7 );\n }\n if ( a1 > 1 )\n {\n v8 = v4 + 1;\n while ( 1 )\n {\n v9 = *v6;\n if ( a3 > 1 )\n break;\n *v8 = v9;\n if ( a3 > 0 )\n goto LABEL_14;\nLABEL_7:\n if ( ++v8 == &v4[(unsigned int)(a1 - 2) + 2] )\n goto LABEL_18;\n }\n v10 = v6 + 1;\n do\n {\n if ( v9 > *v10 )\n v9 = *v10;\n ++v10;\n }\n while ( v10 != &v6[(unsigned int)(a3 - 2) + 2] );\n *v8 = v9;\nLABEL_14:\n v11 = 0LL;\n do\n {\n if ( v6[v11] == v9 )\n {\n v12 = *(int *)(a2 + v11 * 4);\n v13 = *(_DWORD *)&v5[v11 * 4] + 1;\n *(_DWORD *)&v5[v11 * 4] = v13;\n v6[v11] = v4[v13] * v12;\n }\n ++v11;\n }\n while ( a3 != v11 );\n goto LABEL_7;\n }\nLABEL_18:\n v14 = v4[v16 - 1];\n free(v4);\n free(v5);\n free(v6);\n return v14;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11E2(int a1, long long a2, int a3) {\n uint64_t *v4;\n char *v5;\n long long *v6;\n long long v7;\n uint64_t *v8;\n long long v9;\n long long *v10;\n long long v11;\n long long v12;\n int v13;\n long long v14;\n unsigned int v16;\n v16 = a1;\n v4 = malloc(v16 * 8);\n v5 = (char *)calloc(a3, 4uLL);\n v6 = (long long *)malloc(8LL * a3);\n *v4 = 1LL;\n if (a3 > 0) {\n v7 = 0LL;\n do {\n v6[v7] = *(int *)(a2 + 4 * v7);\n ++v7;\n } while (a3 != v7);\n }\n if (a1 > 1) {\n v8 = v4 + 1;\n while (1) {\n v9 = *v6;\n if (a3 > 1) break;\n *v8 = v9;\n if (a3 > 0) goto LABEL_14;\n LABEL_7:\n if (++v8 == &v4[(unsigned int)(a1 - 2) + 2]) goto LABEL_18;\n }\n v10 = v6 + 1;\n do {\n if (v9 > *v10) v9 = *v10;\n ++v10;\n } while (v10 != &v6[(unsigned int)(a3 - 2) + 2]);\n *v8 = v9;\n LABEL_14:\n v11 = 0LL;\n do {\n if (v6[v11] == v9) {\n v12 = *(int *)(a2 + v11 * 4);\n v13 = *(uint32_t *)&v5[v11 * 4] + 1;\n *(uint32_t *)&v5[v11 * 4] = v13;\n v6[v11] = v4[v13] * v12;\n }\n ++v11;\n } while (a3 != v11);\n goto LABEL_7;\n }\nLABEL_18:\n v14 = v4[v16 - 1];\n free(v4);\n free(v5);\n free(v6);\n return v14;\n}", + "ida_pseudo_norm": "long long func0(int a1, long long a2, int a3) {\n uint64_t *v4;\n char *v5;\n long long *v6;\n long long v7;\n uint64_t *v8;\n long long v9;\n long long *v10;\n long long v11;\n long long v12;\n int v13;\n long long v14;\n unsigned int v16;\n v16 = a1;\n v4 = malloc(v16 * 8);\n v5 = (char *)calloc(a3, 4uLL);\n v6 = (long long *)malloc(8LL * a3);\n *v4 = 1LL;\n if (a3 > 0) {\n v7 = 0LL;\n do {\n v6[v7] = *(int *)(a2 + 4 * v7);\n ++v7;\n } while (a3 != v7);\n }\n if (a1 > 1) {\n v8 = v4 + 1;\n while (1) {\n v9 = *v6;\n if (a3 > 1) break;\n *v8 = v9;\n if (a3 > 0) goto LABEL_14;\n LABEL_7:\n if (++v8 == &v4[(unsigned int)(a1 - 2) + 2]) goto LABEL_18;\n }\n v10 = v6 + 1;\n do {\n if (v9 > *v10) v9 = *v10;\n ++v10;\n } while (v10 != &v6[(unsigned int)(a3 - 2) + 2]);\n *v8 = v9;\n LABEL_14:\n v11 = 0LL;\n do {\n if (v6[v11] == v9) {\n v12 = *(int *)(a2 + v11 * 4);\n v13 = *(uint32_t *)&v5[v11 * 4] + 1;\n *(uint32_t *)&v5[v11 * 4] = v13;\n v6[v11] = v4[v13] * v12;\n }\n ++v11;\n } while (a3 != v11);\n goto LABEL_7;\n }\nLABEL_18:\n v14 = v4[v16 - 1];\n free(v4);\n free(v5);\n free(v6);\n return v14;\n}" + }, + { + "index": 843, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint cmp(const void *a, const void *b) {\n\n long long num1 = *(const long long*)a;\n\n long long num2 = *(const long long*)b;\n\n return (num1 > num2) - (num1 < num2); \n\n}\n\n\n\n", + "func": "long long func0(int n, int* primes, int primesSize) {\n long long* uglies = malloc(n * sizeof(long long));\n int* indices = calloc(primesSize, sizeof(int));\n long long* values = malloc(primesSize * sizeof(long long));\n int i, j;\n uglies[0] = 1;\n for (i = 0; i < primesSize; i++) {\n values[i] = primes[i];\n }\n for (i = 1; i < n; i++) {\n long long next_ugly = values[0];\n for (j = 1; j < primesSize; j++) {\n if (values[j] < next_ugly) next_ugly = values[j];\n }\n uglies[i] = next_ugly;\n for (j = 0; j < primesSize; j++) {\n if (values[j] == next_ugly) values[j] = primes[j] * uglies[++indices[j]];\n }\n }\n long long result = uglies[n - 1];\n free(uglies);\n free(indices);\n free(values);\n return result;\n}", + "test": "int main() {\n\n int primes1[] = {2, 7, 13, 19};\n\n int primesSize1 = sizeof(primes1) / sizeof(primes1[0]);\n\n assert(func0(12, primes1, primesSize1) == 32);\n\n assert(func0(10, primes1, primesSize1) == 26);\n\n assert(func0(100, primes1, primesSize1) == 5408);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\nmovslq %edi,%r14\npush %r13\npush %r12\nmov %rsi,%r12\npush %rbp\nmovslq %edx,%rbp\npush %rbx\nmov %rbp,%rbx\nsub $0x18,%rsp\nmov %r14d,0xc(%rsp)\nshl $0x3,%r14\nmov %r14,%rdi\ncallq 10d0 \nmov $0x4,%esi\nmov %rbp,%rdi\nmov %rax,%r13\ncallq 10c0 \nlea 0x0(,%rbp,8),%rdi\nmov %rax,%r15\ncallq 10d0 \nmovq $0x1,0x0(%r13)\nmov 0xc(%rsp),%ecx\nlea -0x1(%rbx),%esi\nmov %rax,%rbp\nxor %eax,%eax\ntest %ebx,%ebx\njle 1375 \nnopw 0x0(%rax,%rax,1)\nmovslq (%r12,%rax,4),%rdx\nmov %rdx,0x0(%rbp,%rax,8)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rdx,%rsi\njne 1360 \ncmp $0x1,%ecx\njle 1408 \nlea -0x2(%rcx),%eax\nlea 0x8(%r13),%rdx\nlea 0x10(%r13,%rax,8),%r8\nlea -0x2(%rbx),%eax\nlea 0x10(%rbp,%rax,8),%rax\nnopw 0x0(%rax,%rax,1)\nmov 0x0(%rbp),%r9\ncmp $0x1,%ebx\njle 1440 \nlea 0x8(%rbp),%rcx\nmov %r9,%rsi\nnopl 0x0(%rax)\nmov (%rcx),%rdi\ncmp %rdi,%rsi\ncmovg %rdi,%rsi\nadd $0x8,%rcx\ncmp %rcx,%rax\njne 13b0 \nmov %rsi,(%rdx)\nxor %ecx,%ecx\njmp 13d5 \nnopw 0x0(%rax,%rax,1)\nmov 0x0(%rbp,%rcx,8),%r9\ncmp %r9,%rsi\njne 13f7 \nmov (%r15,%rcx,4),%edi\nmovslq (%r12,%rcx,4),%r9\nadd $0x1,%edi\nmov %edi,(%r15,%rcx,4)\nmovslq %edi,%rdi\nimul 0x0(%r13,%rdi,8),%r9\nmov %r9,0x0(%rbp,%rcx,8)\nadd $0x1,%rcx\ncmp %ecx,%ebx\njg 13d0 \nadd $0x8,%rdx\ncmp %r8,%rdx\njne 1398 \nmov %r13,%rdi\nmov -0x8(%r13,%r14,1),%r12\ncallq 1090 \nmov %r15,%rdi\ncallq 1090 \nmov %rbp,%rdi\ncallq 1090 \nadd $0x18,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw 0x0(%rax,%rax,1)\nmov %r9,(%rdx)\njne 13ff \nmov %r9,%rsi\njmpq 13c6 \nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmovsxd r15, edi\npush r14\nlea r11, ds:0[r15*8]\nmov r14d, edx\npush r13\nmov rdi, r11; size\npush r12\nmov r12, rsi\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_3C], r15d\nmovsxd r15, r14d\nmov [rsp+48h+var_48], r11\ncall _malloc\nmov esi, 4; size\nmov rdi, r15; nmemb\nmov r13, rax\ncall _calloc\nlea rdi, ds:0[r15*8]; size\nmov rbp, rax\ncall _malloc\ntest r14d, r14d\nmov r11, [rsp+48h+var_48]\nmov qword ptr [r13+0], 1\nmov r9d, [rsp+48h+var_3C]\nmov rbx, rax\njle short loc_1369\nxor eax, eax\nnop word ptr [rax+rax+00h]\nloc_1358:\nmovsxd rdx, dword ptr [r12+rax*4]\nmov [rbx+rax*8], rdx\nadd rax, 1\ncmp r15, rax\njnz short loc_1358\nloc_1369:\ncmp r9d, 1\njle loc_1430\nlea eax, [r9-2]\nlea r8, [r13+8]\nlea r9, [r13+rax*8+10h]\nlea eax, [r14-2]\nlea rdi, [rbx+rax*8+10h]\nlea rsi, ds:0[r15*4]\nnop dword ptr [rax+00000000h]\nloc_1398:\nmov rdx, [rbx]\ncmp r14d, 1\njle loc_145F\nlea rax, [rbx+8]\nmov rcx, rdi\nsub rcx, rax\nand ecx, 8\njz short loc_13D0\nmov rax, [rbx+8]\ncmp rdx, rax\ncmovg rdx, rax\nlea rax, [rbx+10h]\ncmp rdi, rax\njz short loc_13EE\nnop dword ptr [rax+rax+00000000h]\nloc_13D0:\nmov rcx, [rax]\ncmp rdx, rcx\ncmovg rdx, rcx\nmov rcx, [rax+8]\ncmp rdx, rcx\ncmovg rdx, rcx\nadd rax, 10h\ncmp rdi, rax\njnz short loc_13D0\nloc_13EE:\nmov [r8], rdx\nloc_13F1:\nxor eax, eax\nnop dword ptr [rax+rax+00h]\nloc_13F8:\ncmp rdx, [rbx+rax*2]\njnz short loc_141A\nmov ecx, [rbp+rax+0]\nmovsxd r10, dword ptr [r12+rax]\nadd ecx, 1\nmov [rbp+rax+0], ecx\nmovsxd rcx, ecx\nimul r10, [r13+rcx*8+0]\nmov [rbx+rax*2], r10\nloc_141A:\nadd rax, 4\ncmp rax, rsi\njnz short loc_13F8\nadd r8, 8\ncmp r8, r9\njnz loc_1398\nloc_1430:\nmov rdi, r13; ptr\nmov r12, [r13+r11-8]\ncall _free\nmov rdi, rbp; ptr\ncall _free\nmov rdi, rbx; ptr\ncall _free\nadd rsp, 18h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_145F:\nmov [r8], rdx\njz short loc_13F1\nmov rax, r9\nsub rax, r8\ntest al, 8\njnz short loc_148C\nadd r8, 8\nmov [r8], rdx\njmp short loc_148C\nloc_1480:\nmov [r8+8], rdx\nadd r8, 10h\nmov [rax+8], rdx\nloc_148C:\nlea rax, [r8+8]\ncmp rax, r9\njnz short loc_1480\njmp short loc_1430", + "ida_pseudo": "__int64 __fastcall func0(int a1, __int64 a2, int a3)\n{\n size_t v4; // r15\n _QWORD *v5; // r13\n char *v6; // rbp\n __int64 *v7; // rax\n __int64 v8; // r11\n __int64 *v9; // rbx\n __int64 v10; // rax\n _QWORD *v11; // r8\n __int64 v12; // r9\n __int64 v13; // rdi\n __int64 v14; // rdx\n __int64 *v15; // rax\n __int64 v16; // rax\n __int64 v17; // r10\n int v18; // ecx\n __int64 v19; // r12\n _QWORD *v21; // rax\n\n v4 = a3;\n v5 = malloc(8LL * a1);\n v6 = (char *)calloc(v4, 4uLL);\n v7 = (__int64 *)malloc(8 * v4);\n v8 = a1;\n *v5 = 1LL;\n v9 = v7;\n if ( a3 > 0 )\n {\n v10 = 0LL;\n do\n {\n v9[v10] = *(int *)(a2 + 4 * v10);\n ++v10;\n }\n while ( v4 != v10 );\n }\n if ( a1 > 1 )\n {\n v11 = v5 + 1;\n v12 = (__int64)&v5[(unsigned int)(a1 - 2) + 2];\n v13 = (__int64)&v9[(unsigned int)(a3 - 2) + 2];\n do\n {\n v14 = *v9;\n if ( a3 <= 1 )\n {\n *v11 = v14;\n if ( a3 != 1 )\n {\n if ( (((_BYTE)v12 - (_BYTE)v11) & 8) == 0 )\n *++v11 = v14;\n while ( 1 )\n {\n v21 = v11 + 1;\n if ( v11 + 1 == (_QWORD *)v12 )\n break;\n v11[1] = v14;\n v11 += 2;\n v21[1] = v14;\n }\n break;\n }\n }\n else\n {\n v15 = v9 + 1;\n if ( ((8 * ((_BYTE)a3 - 2) + 8) & 8) == 0 )\n goto LABEL_31;\n if ( v14 > v9[1] )\n v14 = v9[1];\n v15 = v9 + 2;\n if ( (__int64 *)v13 != v9 + 2 )\n {\nLABEL_31:\n do\n {\n if ( v14 > *v15 )\n v14 = *v15;\n if ( v14 > v15[1] )\n v14 = v15[1];\n v15 += 2;\n }\n while ( (__int64 *)v13 != v15 );\n }\n *v11 = v14;\n }\n v16 = 0LL;\n do\n {\n if ( v14 == v9[v16] )\n {\n v17 = *(int *)(a2 + v16 * 4);\n v18 = *(_DWORD *)&v6[v16 * 4] + 1;\n *(_DWORD *)&v6[v16 * 4] = v18;\n v9[v16] = v5[v18] * v17;\n }\n ++v16;\n }\n while ( v16 != v4 );\n ++v11;\n }\n while ( v11 != (_QWORD *)v12 );\n }\n v19 = v5[v8 - 1];\n free(v5);\n free(v6);\n free(v9);\n return v19;\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\npush r15\nmovsxd r15, edi\npush r14\nlea r11, ds:0[r15*8]\nmov r14d, edx\npush r13\nmov rdi, r11; size\npush r12\nmov r12, rsi\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_3C], r15d\nmovsxd r15, r14d\nmov [rsp+48h+var_48], r11\ncall _malloc\nmov esi, 4; size\nmov rdi, r15; nmemb\nmov r13, rax\ncall _calloc\nlea rdi, ds:0[r15*8]; size\nmov rbp, rax\ncall _malloc\ntest r14d, r14d\nmov r11, [rsp+48h+var_48]\nmov qword ptr [r13+0], 1\nmov r9d, [rsp+48h+var_3C]\nmov rbx, rax\njle short loc_1369\nxor eax, eax\nnop word ptr [rax+rax+00h]\nloc_1358:\nmovsxd rdx, dword ptr [r12+rax*4]\nmov [rbx+rax*8], rdx\nadd rax, 1\ncmp r15, rax\njnz short loc_1358\nloc_1369:\ncmp r9d, 1\njle loc_1430\nlea eax, [r9-2]\nlea r8, [r13+8]\nlea r9, [r13+rax*8+10h]\nlea eax, [r14-2]\nlea rdi, [rbx+rax*8+10h]\nlea rsi, ds:0[r15*4]\nnop dword ptr [rax+00000000h]\nloc_1398:\nmov rdx, [rbx]\ncmp r14d, 1\njle loc_145F\nlea rax, [rbx+8]\nmov rcx, rdi\nsub rcx, rax\nand ecx, 8\njz short loc_13D0\nmov rax, [rbx+8]\ncmp rdx, rax\ncmovg rdx, rax\nlea rax, [rbx+10h]\ncmp rdi, rax\njz short loc_13EE\nnop dword ptr [rax+rax+00000000h]\nloc_13D0:\nmov rcx, [rax]\ncmp rdx, rcx\ncmovg rdx, rcx\nmov rcx, [rax+8]\ncmp rdx, rcx\ncmovg rdx, rcx\nadd rax, 10h\ncmp rdi, rax\njnz short loc_13D0\nloc_13EE:\nmov [r8], rdx\nloc_13F1:\nxor eax, eax\nnop dword ptr [rax+rax+00h]\nloc_13F8:\ncmp rdx, [rbx+rax*2]\njnz short loc_141A\nmov ecx, [rbp+rax+0]\nmovsxd r10, dword ptr [r12+rax]\nadd ecx, 1\nmov [rbp+rax+0], ecx\nmovsxd rcx, ecx\nimul r10, [r13+rcx*8+0]\nmov [rbx+rax*2], r10\nloc_141A:\nadd rax, 4\ncmp rax, rsi\njnz short loc_13F8\nadd r8, 8\ncmp r8, r9\njnz loc_1398\nloc_1430:\nmov rdi, r13; ptr\nmov r12, [r13+r11-8]\ncall _free\nmov rdi, rbp; ptr\ncall _free\nmov rdi, rbx; ptr\ncall _free\nadd rsp, 18h\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_145F:\nmov [r8], rdx\njz short loc_13F1\nmov rax, r9\nsub rax, r8\ntest al, 8\njnz short loc_148C\nadd r8, 8\nmov [r8], rdx\njmp short loc_148C\nloc_1480:\nmov [r8+8], rdx\nadd r8, 10h\nmov [rax+8], rdx\nloc_148C:\nlea rax, [r8+8]\ncmp rax, r9\njnz short loc_1480\njmp short loc_1430", + "ida_strip_pseudo": "__int64 __fastcall sub_12E0(int a1, __int64 a2, int a3)\n{\n size_t v4; // r15\n _QWORD *v5; // r13\n char *v6; // rbp\n __int64 *v7; // rax\n __int64 v8; // r11\n __int64 *v9; // rbx\n __int64 v10; // rax\n _QWORD *v11; // r8\n __int64 v12; // r9\n __int64 v13; // rdi\n __int64 v14; // rdx\n __int64 *v15; // rax\n __int64 v16; // rax\n __int64 v17; // r10\n int v18; // ecx\n __int64 v19; // r12\n _QWORD *v21; // rax\n\n v4 = a3;\n v5 = malloc(8LL * a1);\n v6 = (char *)calloc(v4, 4uLL);\n v7 = (__int64 *)malloc(8 * v4);\n v8 = a1;\n *v5 = 1LL;\n v9 = v7;\n if ( a3 > 0 )\n {\n v10 = 0LL;\n do\n {\n v9[v10] = *(int *)(a2 + 4 * v10);\n ++v10;\n }\n while ( v4 != v10 );\n }\n if ( a1 > 1 )\n {\n v11 = v5 + 1;\n v12 = (__int64)&v5[(unsigned int)(a1 - 2) + 2];\n v13 = (__int64)&v9[(unsigned int)(a3 - 2) + 2];\n do\n {\n v14 = *v9;\n if ( a3 <= 1 )\n {\n *v11 = v14;\n if ( a3 != 1 )\n {\n if ( (((_BYTE)v12 - (_BYTE)v11) & 8) == 0 )\n *++v11 = v14;\n while ( 1 )\n {\n v21 = v11 + 1;\n if ( v11 + 1 == (_QWORD *)v12 )\n break;\n v11[1] = v14;\n v11 += 2;\n v21[1] = v14;\n }\n break;\n }\n }\n else\n {\n v15 = v9 + 1;\n if ( ((8 * ((_BYTE)a3 - 2) + 8) & 8) == 0 )\n goto LABEL_31;\n if ( v14 > v9[1] )\n v14 = v9[1];\n v15 = v9 + 2;\n if ( (__int64 *)v13 != v9 + 2 )\n {\nLABEL_31:\n do\n {\n if ( v14 > *v15 )\n v14 = *v15;\n if ( v14 > v15[1] )\n v14 = v15[1];\n v15 += 2;\n }\n while ( (__int64 *)v13 != v15 );\n }\n *v11 = v14;\n }\n v16 = 0LL;\n do\n {\n if ( v14 == v9[v16] )\n {\n v17 = *(int *)(a2 + v16 * 4);\n v18 = *(_DWORD *)&v6[v16 * 4] + 1;\n *(_DWORD *)&v6[v16 * 4] = v18;\n v9[v16] = v5[v18] * v17;\n }\n ++v16;\n }\n while ( v16 != v4 );\n ++v11;\n }\n while ( v11 != (_QWORD *)v12 );\n }\n v19 = v5[v8 - 1];\n free(v5);\n free(v6);\n free(v9);\n return v19;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12E0(int a1, long long a2, int a3) {\n unsigned int v4;\n uint64_t *v5;\n char *v6;\n long long *v7;\n long long v8;\n long long *v9;\n long long v10;\n uint64_t *v11;\n long long v12;\n long long v13;\n long long v14;\n long long *v15;\n long long v16;\n long long v17;\n int v18;\n long long v19;\n uint64_t *v21;\n v4 = a3;\n v5 = malloc(8LL * a1);\n v6 = (char *)calloc(v4, 4uLL);\n v7 = (long long *)malloc(8 * v4);\n v8 = a1;\n *v5 = 1LL;\n v9 = v7;\n if (a3 > 0) {\n v10 = 0LL;\n do {\n v9[v10] = *(int *)(a2 + 4 * v10);\n ++v10;\n } while (v4 != v10);\n }\n if (a1 > 1) {\n v11 = v5 + 1;\n v12 = (long long)&v5[(unsigned int)(a1 - 2) + 2];\n v13 = (long long)&v9[(unsigned int)(a3 - 2) + 2];\n do {\n v14 = *v9;\n if (a3 <= 1) {\n *v11 = v14;\n if (a3 != 1) {\n if ((((uint8_t)v12 - (uint8_t)v11) & 8) == 0) *++v11 = v14;\n while (1) {\n v21 = v11 + 1;\n if (v11 + 1 == (uint64_t *)v12) break;\n v11[1] = v14;\n v11 += 2;\n v21[1] = v14;\n }\n break;\n }\n } else {\n v15 = v9 + 1;\n if (((8 * ((uint8_t)a3 - 2) + 8) & 8) == 0) goto LABEL_31;\n if (v14 > v9[1]) v14 = v9[1];\n v15 = v9 + 2;\n if ((long long *)v13 != v9 + 2) {\n LABEL_31:\n do {\n if (v14 > *v15) v14 = *v15;\n if (v14 > v15[1]) v14 = v15[1];\n v15 += 2;\n } while ((long long *)v13 != v15);\n }\n *v11 = v14;\n }\n v16 = 0LL;\n do {\n if (v14 == v9[v16]) {\n v17 = *(int *)(a2 + v16 * 4);\n v18 = *(uint32_t *)&v6[v16 * 4] + 1;\n *(uint32_t *)&v6[v16 * 4] = v18;\n v9[v16] = v5[v18] * v17;\n }\n ++v16;\n } while (v16 != v4);\n ++v11;\n } while (v11 != (uint64_t *)v12);\n }\n v19 = v5[v8 - 1];\n free(v5);\n free(v6);\n free(v9);\n return v19;\n}", + "ida_pseudo_norm": "long long func0(int a1, long long a2, int a3) {\n unsigned int v4;\n uint64_t *v5;\n char *v6;\n long long *v7;\n long long v8;\n long long *v9;\n long long v10;\n uint64_t *v11;\n long long v12;\n long long v13;\n long long v14;\n long long *v15;\n long long v16;\n long long v17;\n int v18;\n long long v19;\n uint64_t *v21;\n v4 = a3;\n v5 = malloc(8LL * a1);\n v6 = (char *)calloc(v4, 4uLL);\n v7 = (long long *)malloc(8 * v4);\n v8 = a1;\n *v5 = 1LL;\n v9 = v7;\n if (a3 > 0) {\n v10 = 0LL;\n do {\n v9[v10] = *(int *)(a2 + 4 * v10);\n ++v10;\n } while (v4 != v10);\n }\n if (a1 > 1) {\n v11 = v5 + 1;\n v12 = (long long)&v5[(unsigned int)(a1 - 2) + 2];\n v13 = (long long)&v9[(unsigned int)(a3 - 2) + 2];\n do {\n v14 = *v9;\n if (a3 <= 1) {\n *v11 = v14;\n if (a3 != 1) {\n if ((((uint8_t)v12 - (uint8_t)v11) & 8) == 0) *++v11 = v14;\n while (1) {\n v21 = v11 + 1;\n if (v11 + 1 == (uint64_t *)v12) break;\n v11[1] = v14;\n v11 += 2;\n v21[1] = v14;\n }\n break;\n }\n } else {\n v15 = v9 + 1;\n if (((8 * ((uint8_t)a3 - 2) + 8) & 8) == 0) goto LABEL_31;\n if (v14 > v9[1]) v14 = v9[1];\n v15 = v9 + 2;\n if ((long long *)v13 != v9 + 2) {\n LABEL_31:\n do {\n if (v14 > *v15) v14 = *v15;\n if (v14 > v15[1]) v14 = v15[1];\n v15 += 2;\n } while ((long long *)v13 != v15);\n }\n *v11 = v14;\n }\n v16 = 0LL;\n do {\n if (v14 == v9[v16]) {\n v17 = *(int *)(a2 + v16 * 4);\n v18 = *(uint32_t *)&v6[v16 * 4] + 1;\n *(uint32_t *)&v6[v16 * 4] = v18;\n v9[v16] = v5[v18] * v17;\n }\n ++v16;\n } while (v16 != v4);\n ++v11;\n } while (v11 != (uint64_t *)v12);\n }\n v19 = v5[v8 - 1];\n free(v5);\n free(v6);\n free(v9);\n return v19;\n}" + }, + { + "index": 843, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint cmp(const void *a, const void *b) {\n\n long long num1 = *(const long long*)a;\n\n long long num2 = *(const long long*)b;\n\n return (num1 > num2) - (num1 < num2); \n\n}\n\n\n\n", + "func": "long long func0(int n, int* primes, int primesSize) {\n long long* uglies = malloc(n * sizeof(long long));\n int* indices = calloc(primesSize, sizeof(int));\n long long* values = malloc(primesSize * sizeof(long long));\n int i, j;\n uglies[0] = 1;\n for (i = 0; i < primesSize; i++) {\n values[i] = primes[i];\n }\n for (i = 1; i < n; i++) {\n long long next_ugly = values[0];\n for (j = 1; j < primesSize; j++) {\n if (values[j] < next_ugly) next_ugly = values[j];\n }\n uglies[i] = next_ugly;\n for (j = 0; j < primesSize; j++) {\n if (values[j] == next_ugly) values[j] = primes[j] * uglies[++indices[j]];\n }\n }\n long long result = uglies[n - 1];\n free(uglies);\n free(indices);\n free(values);\n return result;\n}", + "test": "int main() {\n\n int primes1[] = {2, 7, 13, 19};\n\n int primesSize1 = sizeof(primes1) / sizeof(primes1[0]);\n\n assert(func0(12, primes1, primesSize1) == 32);\n\n assert(func0(10, primes1, primesSize1) == 26);\n\n assert(func0(100, primes1, primesSize1) == 5408);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\nmovslq %edi,%r14\npush %r13\npush %r12\nmov %rsi,%r12\npush %rbp\nmovslq %edx,%rbp\npush %rbx\nmov %rbp,%rbx\nsub $0x18,%rsp\nmov %r14d,0xc(%rsp)\nshl $0x3,%r14\nmov %r14,%rdi\ncallq 10d0 \nmov %rbp,%rdi\nmov $0x4,%esi\nmov %rax,%r13\ncallq 10c0 \nlea 0x0(,%rbp,8),%rdi\nmov %rax,%r15\ncallq 10d0 \ntest %ebx,%ebx\nmov 0xc(%rsp),%ecx\nmovq $0x1,0x0(%r13)\nmov %rax,%rbp\njle 13d0 \nlea -0x1(%rbx),%eax\ncmp $0x2,%eax\njbe 149c \nmov %ebx,%edx\nxor %eax,%eax\npxor %xmm3,%xmm3\nshr $0x2,%edx\nshl $0x4,%rdx\nnopl 0x0(%rax)\nmovdqu (%r12,%rax,1),%xmm0\nmovdqa %xmm3,%xmm1\npcmpgtd %xmm0,%xmm1\nmovdqa %xmm0,%xmm2\npunpckldq %xmm1,%xmm2\npunpckhdq %xmm1,%xmm0\nmovups %xmm2,0x0(%rbp,%rax,2)\nmovups %xmm0,0x10(%rbp,%rax,2)\nadd $0x10,%rax\ncmp %rdx,%rax\njne 1368 \nmov %ebx,%eax\nand $0xfffffffc,%eax\ntest $0x3,%bl\nje 13d0 \nmovslq %eax,%rdx\nmovslq (%r12,%rdx,4),%rsi\nmov %rsi,0x0(%rbp,%rdx,8)\nlea 0x1(%rax),%edx\ncmp %edx,%ebx\njle 13d0 \nmovslq %edx,%rdx\nadd $0x2,%eax\nmovslq (%r12,%rdx,4),%rsi\nmov %rsi,0x0(%rbp,%rdx,8)\ncmp %eax,%ebx\njle 13d0 \ncltq\nmovslq (%r12,%rax,4),%rdx\nmov %rdx,0x0(%rbp,%rax,8)\ncmp $0x1,%ecx\njle 1455 \nlea -0x2(%rcx),%eax\nlea 0x8(%r13),%rdx\nlea 0x10(%r13,%rax,8),%r8\nlea -0x2(%rbx),%eax\nlea 0x10(%rbp,%rax,8),%rax\nnopl (%rax)\nmov 0x0(%rbp),%rsi\ncmp $0x1,%ebx\njle 1488 \nlea 0x8(%rbp),%rcx\nnopl 0x0(%rax)\nmov (%rcx),%rdi\ncmp %rdi,%rsi\ncmovg %rdi,%rsi\nadd $0x8,%rcx\ncmp %rcx,%rax\njne 1408 \nmov %rsi,(%rdx)\nxor %ecx,%ecx\ncmp %rsi,0x0(%rbp,%rcx,8)\njne 1444 \nmov (%r15,%rcx,4),%edi\nmovslq (%r12,%rcx,4),%r9\nadd $0x1,%edi\nmov %edi,(%r15,%rcx,4)\nmovslq %edi,%rdi\nimul 0x0(%r13,%rdi,8),%r9\nmov %r9,0x0(%rbp,%rcx,8)\nadd $0x1,%rcx\ncmp %ecx,%ebx\njg 1420 \nadd $0x8,%rdx\ncmp %r8,%rdx\njne 13f0 \nmov %r13,%rdi\nmov -0x8(%r13,%r14,1),%r12\ncallq 1090 \nmov %r15,%rdi\ncallq 1090 \nmov %rbp,%rdi\ncallq 1090 \nadd $0x18,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\nmov %rsi,(%rdx)\nje 141e \nadd $0x8,%rdx\ncmp %r8,%rdx\njne 13f0 \njmp 1455 \nxor %eax,%eax\njmpq 139f \nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmovsxd r8, edi\npush r14\npush r13\nmov r13, rsi\npush r12\npush rbp\nmovsxd rbp, edx\npush rbx\nmov r15, rbp\nsub rsp, 18h\nmov [rsp+48h+var_3C], r8d\nshl r8, 3\nmov rdi, r8; size\nmov [rsp+48h+var_48], r8\ncall _malloc\nmov esi, 4; size\nmov rdi, rbp; nmemb\nmov r14, rax\ncall _calloc\nlea rdi, ds:0[rbp*8]; size\nmov r12, rax\ncall _malloc\ntest ebp, ebp\nmov r8, [rsp+48h+var_48]\nmov ecx, [rsp+48h+var_3C]\nmov qword ptr [r14], 1\nmov rbx, rax\njle loc_13E9\nlea eax, [rbp-1]\ncmp eax, 2\njbe loc_14CF\nmov edx, ebp\nxor eax, eax\npxor xmm3, xmm3\nshr edx, 2\nshl rdx, 4\nnop dword ptr [rax+rax+00000000h]\nloc_1370:\nmovdqu xmm0, xmmword ptr [r13+rax+0]\nmovdqa xmm1, xmm3\npcmpgtd xmm1, xmm0\nmovdqa xmm2, xmm0\npunpckldq xmm2, xmm1\npunpckhdq xmm0, xmm1\nmovups xmmword ptr [rbx+rax*2], xmm2\nmovups xmmword ptr [rbx+rax*2+10h], xmm0\nadd rax, 10h\ncmp rax, rdx\njnz short loc_1370\nmov eax, r15d\nand eax, 0FFFFFFFCh\ntest r15b, 3\njz short loc_13E9\nloc_13A9:\nmovsxd rdx, eax\nmovsxd r9, dword ptr [r13+rdx*4+0]\nlea rdi, ds:0[rdx*4]\nlea rsi, ds:0[rdx*8]\nmov [rbx+rdx*8], r9\nlea edx, [rax+1]\ncmp r15d, edx\njle short loc_13E9\nmovsxd rdx, dword ptr [r13+rdi+4]\nadd eax, 2\nmov [rbx+rsi+8], rdx\ncmp r15d, eax\njle short loc_13E9\nmovsxd rax, dword ptr [r13+rdi+8]\nmov [rbx+rsi+10h], rax\nloc_13E9:\ncmp ecx, 1\njle loc_14A0\nlea eax, [rcx-2]\nlea rdi, [r14+8]\nshl rbp, 2\nlea r9, [r14+rax*8+10h]\nlea eax, [r15-2]\nlea rsi, [rbx+rax*8+10h]\nnop dword ptr [rax+rax+00h]\nloc_1410:\nmov rdx, [rbx]\ncmp r15d, 1\njle loc_14D6\nlea rax, [rbx+8]\nmov rcx, rsi\nsub rcx, rax\nand ecx, 8\njz short loc_1440\nmov rax, [rbx+8]\ncmp rdx, rax\ncmovg rdx, rax\nlea rax, [rbx+10h]\ncmp rax, rsi\njz short loc_145E\nloc_1440:\nmov rcx, [rax]\ncmp rdx, rcx\ncmovg rdx, rcx\nmov rcx, [rax+8]\ncmp rdx, rcx\ncmovg rdx, rcx\nadd rax, 10h\ncmp rax, rsi\njnz short loc_1440\nloc_145E:\nmov [rdi], rdx\nloc_1461:\nxor eax, eax\nnop dword ptr [rax+rax+00h]\nloc_1468:\ncmp [rbx+rax*2], rdx\njnz short loc_148A\nmov ecx, [r12+rax]\nmovsxd r10, dword ptr [r13+rax+0]\nadd ecx, 1\nmov [r12+rax], ecx\nmovsxd rcx, ecx\nimul r10, [r14+rcx*8]\nmov [rbx+rax*2], r10\nloc_148A:\nadd rax, 4\ncmp rax, rbp\njnz short loc_1468\nadd rdi, 8\ncmp rdi, r9\njnz loc_1410\nloc_14A0:\nmov rdi, r14; ptr\nmov rbp, [r14+r8-8]\ncall _free\nmov rdi, r12; ptr\ncall _free\nmov rdi, rbx; ptr\ncall _free\nadd rsp, 18h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14CF:\nxor eax, eax\njmp loc_13A9\nloc_14D6:\nmov [rdi], rdx\njz short loc_1461\nmov rax, r9\nsub rax, rdi\ntest al, 8\njnz short loc_14FC\nadd rdi, 8\nmov [rdi], rdx\njmp short loc_14FC\nloc_14F0:\nmov [rdi+8], rdx\nadd rdi, 10h\nmov [rax+8], rdx\nloc_14FC:\nlea rax, [rdi+8]\ncmp rax, r9\njnz short loc_14F0\njmp short loc_14A0", + "ida_pseudo": "__int64 __fastcall func0(int a1, __int64 a2, int a3)\n{\n size_t v4; // rbp\n _QWORD *v6; // r14\n char *v7; // r12\n __int64 *v8; // rax\n __int64 v9; // r8\n __int64 *v11; // rbx\n __int64 v12; // rax\n __m128i v13; // xmm0\n __m128i v14; // xmm1\n signed int v15; // eax\n __int64 v16; // rdi\n __int64 v17; // rsi\n _QWORD *v18; // rdi\n __int64 v19; // rbp\n __int64 v20; // r9\n __int64 v21; // rsi\n __int64 v22; // rdx\n __int64 *v23; // rax\n unsigned __int64 v24; // rax\n __int64 v25; // r10\n int v26; // ecx\n __int64 v27; // rbp\n _QWORD *v29; // rax\n\n v4 = a3;\n v6 = malloc(8LL * a1);\n v7 = (char *)calloc(v4, 4uLL);\n v8 = (__int64 *)malloc(8 * v4);\n v9 = a1;\n *v6 = 1LL;\n v11 = v8;\n if ( (int)v4 > 0 )\n {\n if ( (unsigned int)(v4 - 1) <= 2 )\n {\n v15 = 0;\n goto LABEL_6;\n }\n v12 = 0LL;\n do\n {\n v13 = _mm_loadu_si128((const __m128i *)(a2 + v12 * 4));\n v14 = _mm_cmpgt_epi32((__m128i)0LL, v13);\n *(__m128i *)&v11[v12] = _mm_unpacklo_epi32(v13, v14);\n *(__m128i *)&v11[v12 + 2] = _mm_unpackhi_epi32(v13, v14);\n v12 += 4LL;\n }\n while ( v12 != 4LL * ((unsigned int)v4 >> 2) );\n v15 = a3 & 0xFFFFFFFC;\n if ( (a3 & 3) != 0 )\n {\nLABEL_6:\n v16 = 4LL * v15;\n v17 = v15;\n v11[v17] = *(int *)(a2 + v16);\n if ( a3 > v15 + 1 )\n {\n v11[v17 + 1] = *(int *)(a2 + v16 + 4);\n if ( a3 > v15 + 2 )\n v11[v17 + 2] = *(int *)(a2 + v16 + 8);\n }\n }\n }\n if ( a1 <= 1 )\n goto LABEL_27;\n v18 = v6 + 1;\n v19 = 4 * v4;\n v20 = (__int64)&v6[(unsigned int)(a1 - 2) + 2];\n v21 = (__int64)&v11[(unsigned int)(a3 - 2) + 2];\n while ( 1 )\n {\n v22 = *v11;\n if ( a3 > 1 )\n {\n v23 = v11 + 1;\n if ( ((8 * ((_BYTE)a3 - 2) + 8) & 8) == 0 )\n goto LABEL_37;\n if ( v22 > v11[1] )\n v22 = v11[1];\n v23 = v11 + 2;\n if ( v11 + 2 != (__int64 *)v21 )\n {\nLABEL_37:\n do\n {\n if ( v22 > *v23 )\n v22 = *v23;\n if ( v22 > v23[1] )\n v22 = v23[1];\n v23 += 2;\n }\n while ( v23 != (__int64 *)v21 );\n }\n *v18 = v22;\n goto LABEL_22;\n }\n *v18 = v22;\n if ( a3 != 1 )\n break;\nLABEL_22:\n v24 = 0LL;\n do\n {\n if ( v11[v24 / 4] == v22 )\n {\n v25 = *(int *)(a2 + v24);\n v26 = *(_DWORD *)&v7[v24] + 1;\n *(_DWORD *)&v7[v24] = v26;\n v11[v24 / 4] = v6[v26] * v25;\n }\n v24 += 4LL;\n }\n while ( v24 != v19 );\n if ( ++v18 == (_QWORD *)v20 )\n goto LABEL_27;\n }\n if ( (((_BYTE)v20 - (_BYTE)v18) & 8) == 0 )\n *++v18 = v22;\n while ( 1 )\n {\n v29 = v18 + 1;\n if ( v18 + 1 == (_QWORD *)v20 )\n break;\n v18[1] = v22;\n v18 += 2;\n v29[1] = v22;\n }\nLABEL_27:\n v27 = v6[v9 - 1];\n free(v6);\n free(v7);\n free(v11);\n return v27;\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\npush r15\nmovsxd r8, edi\npush r14\npush r13\nmov r13, rsi\npush r12\npush rbp\nmovsxd rbp, edx\npush rbx\nmov r15, rbp\nsub rsp, 18h\nmov [rsp+48h+var_3C], r8d\nshl r8, 3\nmov rdi, r8; size\nmov [rsp+48h+var_48], r8\ncall _malloc\nmov esi, 4; size\nmov rdi, rbp; nmemb\nmov r14, rax\ncall _calloc\nlea rdi, ds:0[rbp*8]; size\nmov r12, rax\ncall _malloc\ntest ebp, ebp\nmov r8, [rsp+48h+var_48]\nmov ecx, [rsp+48h+var_3C]\nmov qword ptr [r14], 1\nmov rbx, rax\njle loc_13E9\nlea eax, [rbp-1]\ncmp eax, 2\njbe loc_14CF\nmov edx, ebp\nxor eax, eax\npxor xmm3, xmm3\nshr edx, 2\nshl rdx, 4\nnop dword ptr [rax+rax+00000000h]\nloc_1370:\nmovdqu xmm0, xmmword ptr [r13+rax+0]\nmovdqa xmm1, xmm3\npcmpgtd xmm1, xmm0\nmovdqa xmm2, xmm0\npunpckldq xmm2, xmm1\npunpckhdq xmm0, xmm1\nmovups xmmword ptr [rbx+rax*2], xmm2\nmovups xmmword ptr [rbx+rax*2+10h], xmm0\nadd rax, 10h\ncmp rax, rdx\njnz short loc_1370\nmov eax, r15d\nand eax, 0FFFFFFFCh\ntest r15b, 3\njz short loc_13E9\nloc_13A9:\nmovsxd rdx, eax\nmovsxd r9, dword ptr [r13+rdx*4+0]\nlea rdi, ds:0[rdx*4]\nlea rsi, ds:0[rdx*8]\nmov [rbx+rdx*8], r9\nlea edx, [rax+1]\ncmp r15d, edx\njle short loc_13E9\nmovsxd rdx, dword ptr [r13+rdi+4]\nadd eax, 2\nmov [rbx+rsi+8], rdx\ncmp r15d, eax\njle short loc_13E9\nmovsxd rax, dword ptr [r13+rdi+8]\nmov [rbx+rsi+10h], rax\nloc_13E9:\ncmp ecx, 1\njle loc_14A0\nlea eax, [rcx-2]\nlea rdi, [r14+8]\nshl rbp, 2\nlea r9, [r14+rax*8+10h]\nlea eax, [r15-2]\nlea rsi, [rbx+rax*8+10h]\nnop dword ptr [rax+rax+00h]\nloc_1410:\nmov rdx, [rbx]\ncmp r15d, 1\njle loc_14D6\nlea rax, [rbx+8]\nmov rcx, rsi\nsub rcx, rax\nand ecx, 8\njz short loc_1440\nmov rax, [rbx+8]\ncmp rdx, rax\ncmovg rdx, rax\nlea rax, [rbx+10h]\ncmp rax, rsi\njz short loc_145E\nloc_1440:\nmov rcx, [rax]\ncmp rdx, rcx\ncmovg rdx, rcx\nmov rcx, [rax+8]\ncmp rdx, rcx\ncmovg rdx, rcx\nadd rax, 10h\ncmp rax, rsi\njnz short loc_1440\nloc_145E:\nmov [rdi], rdx\nloc_1461:\nxor eax, eax\nnop dword ptr [rax+rax+00h]\nloc_1468:\ncmp [rbx+rax*2], rdx\njnz short loc_148A\nmov ecx, [r12+rax]\nmovsxd r10, dword ptr [r13+rax+0]\nadd ecx, 1\nmov [r12+rax], ecx\nmovsxd rcx, ecx\nimul r10, [r14+rcx*8]\nmov [rbx+rax*2], r10\nloc_148A:\nadd rax, 4\ncmp rax, rbp\njnz short loc_1468\nadd rdi, 8\ncmp rdi, r9\njnz loc_1410\nloc_14A0:\nmov rdi, r14; ptr\nmov rbp, [r14+r8-8]\ncall _free\nmov rdi, r12; ptr\ncall _free\nmov rdi, rbx; ptr\ncall _free\nadd rsp, 18h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14CF:\nxor eax, eax\njmp loc_13A9\nloc_14D6:\nmov [rdi], rdx\njz short loc_1461\nmov rax, r9\nsub rax, rdi\ntest al, 8\njnz short loc_14FC\nadd rdi, 8\nmov [rdi], rdx\njmp short loc_14FC\nloc_14F0:\nmov [rdi+8], rdx\nadd rdi, 10h\nmov [rax+8], rdx\nloc_14FC:\nlea rax, [rdi+8]\ncmp rax, r9\njnz short loc_14F0\njmp short loc_14A0", + "ida_strip_pseudo": "__int64 __fastcall sub_12E0(int a1, __int64 a2, int a3)\n{\n size_t v4; // rbp\n _QWORD *v6; // r14\n char *v7; // r12\n __int64 *v8; // rax\n __int64 v9; // r8\n __int64 *v11; // rbx\n __int64 v12; // rax\n __m128i v13; // xmm0\n __m128i v14; // xmm1\n signed int v15; // eax\n __int64 v16; // rdi\n __int64 v17; // rsi\n _QWORD *v18; // rdi\n __int64 v19; // rbp\n __int64 v20; // r9\n __int64 v21; // rsi\n __int64 v22; // rdx\n __int64 *v23; // rax\n unsigned __int64 v24; // rax\n __int64 v25; // r10\n int v26; // ecx\n __int64 v27; // rbp\n _QWORD *v29; // rax\n\n v4 = a3;\n v6 = malloc(8LL * a1);\n v7 = (char *)calloc(v4, 4uLL);\n v8 = (__int64 *)malloc(8 * v4);\n v9 = a1;\n *v6 = 1LL;\n v11 = v8;\n if ( (int)v4 > 0 )\n {\n if ( (unsigned int)(v4 - 1) <= 2 )\n {\n v15 = 0;\n goto LABEL_6;\n }\n v12 = 0LL;\n do\n {\n v13 = _mm_loadu_si128((const __m128i *)(a2 + v12 * 4));\n v14 = _mm_cmpgt_epi32((__m128i)0LL, v13);\n *(__m128i *)&v11[v12] = _mm_unpacklo_epi32(v13, v14);\n *(__m128i *)&v11[v12 + 2] = _mm_unpackhi_epi32(v13, v14);\n v12 += 4LL;\n }\n while ( v12 != 4LL * ((unsigned int)v4 >> 2) );\n v15 = a3 & 0xFFFFFFFC;\n if ( (a3 & 3) != 0 )\n {\nLABEL_6:\n v16 = 4LL * v15;\n v17 = v15;\n v11[v17] = *(int *)(a2 + v16);\n if ( a3 > v15 + 1 )\n {\n v11[v17 + 1] = *(int *)(a2 + v16 + 4);\n if ( a3 > v15 + 2 )\n v11[v17 + 2] = *(int *)(a2 + v16 + 8);\n }\n }\n }\n if ( a1 <= 1 )\n goto LABEL_27;\n v18 = v6 + 1;\n v19 = 4 * v4;\n v20 = (__int64)&v6[(unsigned int)(a1 - 2) + 2];\n v21 = (__int64)&v11[(unsigned int)(a3 - 2) + 2];\n while ( 1 )\n {\n v22 = *v11;\n if ( a3 > 1 )\n {\n v23 = v11 + 1;\n if ( ((8 * ((_BYTE)a3 - 2) + 8) & 8) == 0 )\n goto LABEL_37;\n if ( v22 > v11[1] )\n v22 = v11[1];\n v23 = v11 + 2;\n if ( v11 + 2 != (__int64 *)v21 )\n {\nLABEL_37:\n do\n {\n if ( v22 > *v23 )\n v22 = *v23;\n if ( v22 > v23[1] )\n v22 = v23[1];\n v23 += 2;\n }\n while ( v23 != (__int64 *)v21 );\n }\n *v18 = v22;\n goto LABEL_22;\n }\n *v18 = v22;\n if ( a3 != 1 )\n break;\nLABEL_22:\n v24 = 0LL;\n do\n {\n if ( v11[v24 / 4] == v22 )\n {\n v25 = *(int *)(a2 + v24);\n v26 = *(_DWORD *)&v7[v24] + 1;\n *(_DWORD *)&v7[v24] = v26;\n v11[v24 / 4] = v6[v26] * v25;\n }\n v24 += 4LL;\n }\n while ( v24 != v19 );\n if ( ++v18 == (_QWORD *)v20 )\n goto LABEL_27;\n }\n if ( (((_BYTE)v20 - (_BYTE)v18) & 8) == 0 )\n *++v18 = v22;\n while ( 1 )\n {\n v29 = v18 + 1;\n if ( v18 + 1 == (_QWORD *)v20 )\n break;\n v18[1] = v22;\n v18 += 2;\n v29[1] = v22;\n }\nLABEL_27:\n v27 = v6[v9 - 1];\n free(v6);\n free(v7);\n free(v11);\n return v27;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12E0(int a1, long long a2, int a3) {\n unsigned int v4;\n uint64_t *v6;\n char *v7;\n long long *v8;\n long long v9;\n long long *v11;\n long long v12;\n __m128i v13;\n __m128i v14;\n signed int v15;\n long long v16;\n long long v17;\n uint64_t *v18;\n long long v19;\n long long v20;\n long long v21;\n long long v22;\n long long *v23;\n unsigned long long v24;\n long long v25;\n int v26;\n long long v27;\n uint64_t *v29;\n v4 = a3;\n v6 = malloc(8LL * a1);\n v7 = (char *)calloc(v4, 4uLL);\n v8 = (long long *)malloc(8 * v4);\n v9 = a1;\n *v6 = 1LL;\n v11 = v8;\n if ((int)v4 > 0) {\n if ((unsigned int)(v4 - 1) <= 2) {\n v15 = 0;\n goto LABEL_6;\n }\n v12 = 0LL;\n do {\n v13 = _mm_loadu_si128((const __m128i *)(a2 + v12 * 4));\n v14 = _mm_cmpgt_epi32((__m128i)0LL, v13);\n *(__m128i *)&v11[v12] = _mm_unpacklo_epi32(v13, v14);\n *(__m128i *)&v11[v12 + 2] = _mm_unpackhi_epi32(v13, v14);\n v12 += 4LL;\n } while (v12 != 4LL * ((unsigned int)v4 >> 2));\n v15 = a3 & 4294967292;\n if ((a3 & 3) != 0) {\n LABEL_6:\n v16 = 4LL * v15;\n v17 = v15;\n v11[v17] = *(int *)(a2 + v16);\n if (a3 > v15 + 1) {\n v11[v17 + 1] = *(int *)(a2 + v16 + 4);\n if (a3 > v15 + 2) v11[v17 + 2] = *(int *)(a2 + v16 + 8);\n }\n }\n }\n if (a1 <= 1) goto LABEL_27;\n v18 = v6 + 1;\n v19 = 4 * v4;\n v20 = (long long)&v6[(unsigned int)(a1 - 2) + 2];\n v21 = (long long)&v11[(unsigned int)(a3 - 2) + 2];\n while (1) {\n v22 = *v11;\n if (a3 > 1) {\n v23 = v11 + 1;\n if (((8 * ((uint8_t)a3 - 2) + 8) & 8) == 0) goto LABEL_37;\n if (v22 > v11[1]) v22 = v11[1];\n v23 = v11 + 2;\n if (v11 + 2 != (long long *)v21) {\n LABEL_37:\n do {\n if (v22 > *v23) v22 = *v23;\n if (v22 > v23[1]) v22 = v23[1];\n v23 += 2;\n } while (v23 != (long long *)v21);\n }\n *v18 = v22;\n goto LABEL_22;\n }\n *v18 = v22;\n if (a3 != 1) break;\n LABEL_22:\n v24 = 0LL;\n do {\n if (v11[v24 / 4] == v22) {\n v25 = *(int *)(a2 + v24);\n v26 = *(uint32_t *)&v7[v24] + 1;\n *(uint32_t *)&v7[v24] = v26;\n v11[v24 / 4] = v6[v26] * v25;\n }\n v24 += 4LL;\n } while (v24 != v19);\n if (++v18 == (uint64_t *)v20) goto LABEL_27;\n }\n if ((((uint8_t)v20 - (uint8_t)v18) & 8) == 0) *++v18 = v22;\n while (1) {\n v29 = v18 + 1;\n if (v18 + 1 == (uint64_t *)v20) break;\n v18[1] = v22;\n v18 += 2;\n v29[1] = v22;\n }\nLABEL_27:\n v27 = v6[v9 - 1];\n free(v6);\n free(v7);\n free(v11);\n return v27;\n}", + "ida_pseudo_norm": "long long func0(int a1, long long a2, int a3) {\n unsigned int v4;\n uint64_t *v6;\n char *v7;\n long long *v8;\n long long v9;\n long long *v11;\n long long v12;\n __m128i v13;\n __m128i v14;\n signed int v15;\n long long v16;\n long long v17;\n uint64_t *v18;\n long long v19;\n long long v20;\n long long v21;\n long long v22;\n long long *v23;\n unsigned long long v24;\n long long v25;\n int v26;\n long long v27;\n uint64_t *v29;\n v4 = a3;\n v6 = malloc(8LL * a1);\n v7 = (char *)calloc(v4, 4uLL);\n v8 = (long long *)malloc(8 * v4);\n v9 = a1;\n *v6 = 1LL;\n v11 = v8;\n if ((int)v4 > 0) {\n if ((unsigned int)(v4 - 1) <= 2) {\n v15 = 0;\n goto LABEL_6;\n }\n v12 = 0LL;\n do {\n v13 = _mm_loadu_si128((const __m128i *)(a2 + v12 * 4));\n v14 = _mm_cmpgt_epi32((__m128i)0LL, v13);\n *(__m128i *)&v11[v12] = _mm_unpacklo_epi32(v13, v14);\n *(__m128i *)&v11[v12 + 2] = _mm_unpackhi_epi32(v13, v14);\n v12 += 4LL;\n } while (v12 != 4LL * ((unsigned int)v4 >> 2));\n v15 = a3 & 4294967292;\n if ((a3 & 3) != 0) {\n LABEL_6:\n v16 = 4LL * v15;\n v17 = v15;\n v11[v17] = *(int *)(a2 + v16);\n if (a3 > v15 + 1) {\n v11[v17 + 1] = *(int *)(a2 + v16 + 4);\n if (a3 > v15 + 2) v11[v17 + 2] = *(int *)(a2 + v16 + 8);\n }\n }\n }\n if (a1 <= 1) goto LABEL_27;\n v18 = v6 + 1;\n v19 = 4 * v4;\n v20 = (long long)&v6[(unsigned int)(a1 - 2) + 2];\n v21 = (long long)&v11[(unsigned int)(a3 - 2) + 2];\n while (1) {\n v22 = *v11;\n if (a3 > 1) {\n v23 = v11 + 1;\n if (((8 * ((uint8_t)a3 - 2) + 8) & 8) == 0) goto LABEL_37;\n if (v22 > v11[1]) v22 = v11[1];\n v23 = v11 + 2;\n if (v11 + 2 != (long long *)v21) {\n LABEL_37:\n do {\n if (v22 > *v23) v22 = *v23;\n if (v22 > v23[1]) v22 = v23[1];\n v23 += 2;\n } while (v23 != (long long *)v21);\n }\n *v18 = v22;\n goto LABEL_22;\n }\n *v18 = v22;\n if (a3 != 1) break;\n LABEL_22:\n v24 = 0LL;\n do {\n if (v11[v24 / 4] == v22) {\n v25 = *(int *)(a2 + v24);\n v26 = *(uint32_t *)&v7[v24] + 1;\n *(uint32_t *)&v7[v24] = v26;\n v11[v24 / 4] = v6[v26] * v25;\n }\n v24 += 4LL;\n } while (v24 != v19);\n if (++v18 == (uint64_t *)v20) goto LABEL_27;\n }\n if ((((uint8_t)v20 - (uint8_t)v18) & 8) == 0) *++v18 = v22;\n while (1) {\n v29 = v18 + 1;\n if (v18 + 1 == (uint64_t *)v20) break;\n v18[1] = v22;\n v18 += 2;\n v29[1] = v22;\n }\nLABEL_27:\n v27 = v6[v9 - 1];\n free(v6);\n free(v7);\n free(v11);\n return v27;\n}" + }, + { + "index": 844, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n, int k) {\n int arr[n];\n int i = 0;\n int odd = 1;\n while (odd <= n) {\n arr[i] = odd;\n i += 1;\n odd += 2;\n }\n int even = 2;\n while (even <= n) {\n arr[i] = even;\n i += 1;\n even += 2;\n }\n return arr[k - 1];\n}", + "test": "int main() {\n\n assert(func0(8,5) == 2);\n\n assert(func0(7,2) == 3);\n\n assert(func0(5,2) == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x48,%rsp\nmov %edi,-0x44(%rbp)\nmov %esi,-0x48(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmov %rsp,%rax\nmov %rax,%rsi\nmov -0x44(%rbp),%eax\nmovslq %eax,%rdx\nsub $0x1,%rdx\nmov %rdx,-0x28(%rbp)\nmovslq %eax,%rdx\nmov %rdx,%r8\nmov $0x0,%r9d\nmovslq %eax,%rdx\nmov %rdx,%rcx\nmov $0x0,%ebx\ncltq\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%edi\nmov $0x0,%edx\ndiv %rdi\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rbx\nsub %rdx,%rbx\nmov %rbx,%rdx\ncmp %rdx,%rsp\nje 1207 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11f0 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 1231 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x20(%rbp)\nmovl $0x0,-0x2c(%rbp)\nmovl $0x1,-0x30(%rbp)\njmp 126c \nmov -0x20(%rbp),%rax\nmov -0x2c(%rbp),%edx\nmovslq %edx,%rdx\nmov -0x30(%rbp),%ecx\nmov %ecx,(%rax,%rdx,4)\naddl $0x1,-0x2c(%rbp)\naddl $0x2,-0x30(%rbp)\nmov -0x30(%rbp),%eax\ncmp -0x44(%rbp),%eax\njle 1254 \nmovl $0x2,-0x34(%rbp)\njmp 1295 \nmov -0x20(%rbp),%rax\nmov -0x2c(%rbp),%edx\nmovslq %edx,%rdx\nmov -0x34(%rbp),%ecx\nmov %ecx,(%rax,%rdx,4)\naddl $0x1,-0x2c(%rbp)\naddl $0x2,-0x34(%rbp)\nmov -0x34(%rbp),%eax\ncmp -0x44(%rbp),%eax\njle 127d \nmov -0x48(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x20(%rbp),%rax\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nmov %rsi,%rsp\nmov -0x18(%rbp),%rdi\nxor %fs:0x28,%rdi\nje 12c4 \ncallq 1060 <__stack_chk_fail@plt>\nmov -0x8(%rbp),%rbx\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_34], edi\nmov [rbp+var_38], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov eax, [rbp+var_34]\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11D5:\ncmp rsp, rdx\njz short loc_11EC\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_11D5\nloc_11EC:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1216\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1216:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov [rbp+var_24], 0\nmov [rbp+var_20], 1\njmp short loc_1251\nloc_1239:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov ecx, [rbp+var_20]\nmov [rax+rdx*4], ecx\nadd [rbp+var_24], 1\nadd [rbp+var_20], 2\nloc_1251:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_34]\njle short loc_1239\nmov [rbp+var_1C], 2\njmp short loc_127A\nloc_1262:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov ecx, [rbp+var_1C]\nmov [rax+rdx*4], ecx\nadd [rbp+var_24], 1\nadd [rbp+var_1C], 2\nloc_127A:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_34]\njle short loc_1262\nmov eax, [rbp+var_38]\nlea edx, [rax-1]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12A9\ncall ___stack_chk_fail\nlocret_12A9:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n unsigned __int64 v2; // rax\n void *v3; // rsp\n _BYTE v5[8]; // [rsp+8h] [rbp-40h] BYREF\n int v6; // [rsp+10h] [rbp-38h]\n int v7; // [rsp+14h] [rbp-34h]\n int v8; // [rsp+24h] [rbp-24h]\n int i; // [rsp+28h] [rbp-20h]\n int j; // [rsp+2Ch] [rbp-1Ch]\n __int64 v11; // [rsp+30h] [rbp-18h]\n _BYTE *v12; // [rsp+38h] [rbp-10h]\n unsigned __int64 v13; // [rsp+40h] [rbp-8h]\n\n v7 = a1;\n v6 = a2;\n v13 = __readfsqword(0x28u);\n v11 = a1 - 1LL;\n v2 = 16 * ((4LL * a1 + 15) / 0x10uLL);\n while ( v5 != &v5[-(v2 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = alloca(v2 & 0xFFF);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)&v5[(v2 & 0xFFF) - 8] = *(_QWORD *)&v5[(v2 & 0xFFF) - 8];\n v12 = v5;\n v8 = 0;\n for ( i = 1; i <= v7; i += 2 )\n *(_DWORD *)&v12[4 * v8++] = i;\n for ( j = 2; j <= v7; j += 2 )\n *(_DWORD *)&v12[4 * v8++] = j;\n return *(unsigned int *)&v12[4 * v6 - 4];\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_34], edi\nmov [rbp+var_38], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov eax, [rbp+var_34]\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11D5:\ncmp rsp, rdx\njz short loc_11EC\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_11D5\nloc_11EC:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1216\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1216:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov [rbp+var_24], 0\nmov [rbp+var_20], 1\njmp short loc_1251\nloc_1239:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov ecx, [rbp+var_20]\nmov [rax+rdx*4], ecx\nadd [rbp+var_24], 1\nadd [rbp+var_20], 2\nloc_1251:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_34]\njle short loc_1239\nmov [rbp+var_1C], 2\njmp short loc_127A\nloc_1262:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov ecx, [rbp+var_1C]\nmov [rax+rdx*4], ecx\nadd [rbp+var_24], 1\nadd [rbp+var_1C], 2\nloc_127A:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_34]\njle short loc_1262\nmov eax, [rbp+var_38]\nlea edx, [rax-1]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12A9\ncall ___stack_chk_fail\nlocret_12A9:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1, int a2)\n{\n unsigned __int64 v2; // rax\n void *v3; // rsp\n _BYTE v5[8]; // [rsp+8h] [rbp-40h] BYREF\n int v6; // [rsp+10h] [rbp-38h]\n int v7; // [rsp+14h] [rbp-34h]\n int v8; // [rsp+24h] [rbp-24h]\n int i; // [rsp+28h] [rbp-20h]\n int j; // [rsp+2Ch] [rbp-1Ch]\n __int64 v11; // [rsp+30h] [rbp-18h]\n _BYTE *v12; // [rsp+38h] [rbp-10h]\n unsigned __int64 v13; // [rsp+40h] [rbp-8h]\n\n v7 = a1;\n v6 = a2;\n v13 = __readfsqword(0x28u);\n v11 = a1 - 1LL;\n v2 = 16 * ((4LL * a1 + 15) / 0x10uLL);\n while ( v5 != &v5[-(v2 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = alloca(v2 & 0xFFF);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)&v5[(v2 & 0xFFF) - 8] = *(_QWORD *)&v5[(v2 & 0xFFF) - 8];\n v12 = v5;\n v8 = 0;\n for ( i = 1; i <= v7; i += 2 )\n *(_DWORD *)&v12[4 * v8++] = i;\n for ( j = 2; j <= v7; j += 2 )\n *(_DWORD *)&v12[4 * v8++] = j;\n return *(unsigned int *)&v12[4 * v6 - 4];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1, int a2) {\n unsigned long long v2;\n void *v3;\n uint8_t v5[8];\n int v6;\n int v7;\n int v8;\n int i;\n int j;\n long long v11;\n uint8_t *v12;\n unsigned long long v13;\n v7 = a1;\n v6 = a2;\n v13 = __readfsqword(40u);\n v11 = a1 - 1LL;\n v2 = 16 * ((4LL * a1 + 15) / 16uLL);\n while (v5 != &v5[-(v2 & 18446744073709547520LL)])\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)&v5[(v2 & 4095) - 8] = *(uint64_t *)&v5[(v2 & 4095) - 8];\n v12 = v5;\n v8 = 0;\n for (i = 1; i <= v7; i += 2) *(uint32_t *)&v12[4 * v8++] = i;\n for (j = 2; j <= v7; j += 2) *(uint32_t *)&v12[4 * v8++] = j;\n return *(unsigned int *)&v12[4 * v6 - 4];\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n unsigned long long v2;\n void *v3;\n uint8_t v5[8];\n int v6;\n int v7;\n int v8;\n int i;\n int j;\n long long v11;\n uint8_t *v12;\n unsigned long long v13;\n v7 = a1;\n v6 = a2;\n v13 = __readfsqword(40u);\n v11 = a1 - 1LL;\n v2 = 16 * ((4LL * a1 + 15) / 16uLL);\n while (v5 != &v5[-(v2 & 18446744073709547520LL)])\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)&v5[(v2 & 4095) - 8] = *(uint64_t *)&v5[(v2 & 4095) - 8];\n v12 = v5;\n v8 = 0;\n for (i = 1; i <= v7; i += 2) *(uint32_t *)&v12[4 * v8++] = i;\n for (j = 2; j <= v7; j += 2) *(uint32_t *)&v12[4 * v8++] = j;\n return *(unsigned int *)&v12[4 * v6 - 4];\n}" + }, + { + "index": 844, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n, int k) {\n int arr[n];\n int i = 0;\n int odd = 1;\n while (odd <= n) {\n arr[i] = odd;\n i += 1;\n odd += 2;\n }\n int even = 2;\n while (even <= n) {\n arr[i] = even;\n i += 1;\n even += 2;\n }\n return arr[k - 1];\n}", + "test": "int main() {\n\n assert(func0(8,5) == 2);\n\n assert(func0(7,2) == 3);\n\n assert(func0(5,2) == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovslq %edi,%rax\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffffff0,%rdx\nand $0xfffffffffffff000,%rax\nmov %rsp,%rcx\nsub %rax,%rcx\nmov %rcx,%rax\ncmp %rax,%rsp\nje 11bc \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11a5 \nmov %rdx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 11d2 \norq $0x0,-0x8(%rsp,%rax,1)\nmov %rsp,%rcx\ntest %edi,%edi\njle 122c \nmov %rcx,%rdx\nmov $0x1,%eax\nmov %eax,(%rdx)\nadd $0x2,%eax\nadd $0x4,%rdx\ncmp %eax,%edi\njge 11e1 \nlea -0x1(%rdi),%eax\nshr %eax\nadd $0x1,%eax\ncmp $0x1,%edi\njle 1213 \ncltq\nlea (%rcx,%rax,4),%rdx\nmov $0x2,%eax\nmov %eax,(%rdx)\nadd $0x2,%eax\nadd $0x4,%rdx\ncmp %eax,%edi\njge 1206 \nlea -0x1(%rsi),%eax\ncltq\nmov (%rcx,%rax,4),%eax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\njne 1233 \nleaveq\nretq\nmov $0x0,%eax\njmp 11f6 \ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov ecx, edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmovsxd rax, edi\nlea rax, ds:0Fh[rax*4]\nmov rdi, rax\nand rdi, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11A4:\ncmp rsp, rdx\njz short loc_11BB\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11A4\nloc_11BB:\nmov rax, rdi\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11D1\nor [rsp+rax+10h+var_18], 0\nloc_11D1:\nmov rdi, rsp\ntest ecx, ecx\njle short loc_1210\nmov rdx, rdi\nmov eax, 1\nloc_11E0:\nmov [rdx], eax\nadd eax, 2\nadd rdx, 4\ncmp ecx, eax\njge short loc_11E0\nlea eax, [rcx-1]\nshr eax, 1\ncmp ecx, 1\njle short loc_1210\ncdqe\nlea rdx, [rdi+rax*4]\nmov eax, 2\nloc_1202:\nmov [rdx+4], eax\nadd eax, 2\nadd rdx, 4\ncmp ecx, eax\njge short loc_1202\nloc_1210:\nlea eax, [rsi-1]\ncdqe\nmov eax, [rdi+rax*4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_1229\nleave\nretn\nloc_1229:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n __int64 v3; // rax\n __int16 v4; // di\n signed __int64 v5; // rax\n void *v6; // rsp\n int *v7; // rdx\n int v8; // eax\n _DWORD *v9; // rdx\n int v10; // eax\n _DWORD v13[2]; // [rsp+8h] [rbp-10h] BYREF\n unsigned __int64 v14; // [rsp+10h] [rbp-8h]\n\n v14 = __readfsqword(0x28u);\n v3 = 4LL * a1 + 15;\n v4 = (4 * a1 + 15) & 0xFFF0;\n while ( v13 != (_DWORD *)((char *)v13 - (v3 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v5 = v4 & 0xFFF;\n v6 = alloca(v5);\n if ( (v4 & 0xFFF) != 0 )\n *(_QWORD *)((char *)&v13[-2] + v5) = *(_QWORD *)((char *)&v13[-2] + v5);\n if ( a1 > 0 )\n {\n v7 = v13;\n v8 = 1;\n do\n {\n *v7 = v8;\n v8 += 2;\n ++v7;\n }\n while ( a1 >= v8 );\n if ( a1 > 1 )\n {\n v9 = &v13[(unsigned int)(a1 - 1) >> 1];\n v10 = 2;\n do\n {\n v9[1] = v10;\n v10 += 2;\n ++v9;\n }\n while ( a1 >= v10 );\n }\n }\n return (unsigned int)v13[a2 - 1];\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov ecx, edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmovsxd rax, edi\nlea rax, ds:0Fh[rax*4]\nmov rdi, rax\nand rdi, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11A4:\ncmp rsp, rdx\njz short loc_11BB\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11A4\nloc_11BB:\nmov rax, rdi\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11D1\nor [rsp+rax+10h+var_18], 0\nloc_11D1:\nmov rdi, rsp\ntest ecx, ecx\njle short loc_1210\nmov rdx, rdi\nmov eax, 1\nloc_11E0:\nmov [rdx], eax\nadd eax, 2\nadd rdx, 4\ncmp ecx, eax\njge short loc_11E0\nlea eax, [rcx-1]\nshr eax, 1\ncmp ecx, 1\njle short loc_1210\ncdqe\nlea rdx, [rdi+rax*4]\nmov eax, 2\nloc_1202:\nmov [rdx+4], eax\nadd eax, 2\nadd rdx, 4\ncmp ecx, eax\njge short loc_1202\nloc_1210:\nlea eax, [rsi-1]\ncdqe\nmov eax, [rdi+rax*4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_1229\nleave\nretn\nloc_1229:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1, int a2)\n{\n __int64 v3; // rax\n __int16 v4; // di\n signed __int64 v5; // rax\n void *v6; // rsp\n int *v7; // rdx\n int v8; // eax\n _DWORD *v9; // rdx\n int v10; // eax\n _DWORD v13[2]; // [rsp+8h] [rbp-10h] BYREF\n unsigned __int64 v14; // [rsp+10h] [rbp-8h]\n\n v14 = __readfsqword(0x28u);\n v3 = 4LL * a1 + 15;\n v4 = (4 * a1 + 15) & 0xFFF0;\n while ( v13 != (_DWORD *)((char *)v13 - (v3 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v5 = v4 & 0xFFF;\n v6 = alloca(v5);\n if ( (v4 & 0xFFF) != 0 )\n *(_QWORD *)((char *)&v13[-2] + v5) = *(_QWORD *)((char *)&v13[-2] + v5);\n if ( a1 > 0 )\n {\n v7 = v13;\n v8 = 1;\n do\n {\n *v7 = v8;\n v8 += 2;\n ++v7;\n }\n while ( a1 >= v8 );\n if ( a1 > 1 )\n {\n v9 = &v13[(unsigned int)(a1 - 1) >> 1];\n v10 = 2;\n do\n {\n v9[1] = v10;\n v10 += 2;\n ++v9;\n }\n while ( a1 >= v10 );\n }\n }\n return (unsigned int)v13[a2 - 1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1, int a2) {\n long long v3;\n short v4;\n signed long long v5;\n void *v6;\n int *v7;\n int v8;\n uint32_t *v9;\n int v10;\n uint32_t v13[2];\n unsigned long long v14;\n v14 = __readfsqword(40u);\n v3 = 4LL * a1 + 15;\n v4 = (4 * a1 + 15) & 65520;\n while (v13 != (uint32_t *)((char *)v13 - (v3 & 18446744073709547520LL)))\n ;\n v5 = v4 & 4095;\n v6 = alloca(v5);\n if ((v4 & 4095) != 0)\n *(uint64_t *)((char *)&v13[-2] + v5) = *(uint64_t *)((char *)&v13[-2] + v5);\n if (a1 > 0) {\n v7 = v13;\n v8 = 1;\n do {\n *v7 = v8;\n v8 += 2;\n ++v7;\n } while (a1 >= v8);\n if (a1 > 1) {\n v9 = &v13[(unsigned int)(a1 - 1) >> 1];\n v10 = 2;\n do {\n v9[1] = v10;\n v10 += 2;\n ++v9;\n } while (a1 >= v10);\n }\n }\n return (unsigned int)v13[a2 - 1];\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n long long v3;\n short v4;\n signed long long v5;\n void *v6;\n int *v7;\n int v8;\n uint32_t *v9;\n int v10;\n uint32_t v13[2];\n unsigned long long v14;\n v14 = __readfsqword(40u);\n v3 = 4LL * a1 + 15;\n v4 = (4 * a1 + 15) & 65520;\n while (v13 != (uint32_t *)((char *)v13 - (v3 & 18446744073709547520LL)))\n ;\n v5 = v4 & 4095;\n v6 = alloca(v5);\n if ((v4 & 4095) != 0)\n *(uint64_t *)((char *)&v13[-2] + v5) = *(uint64_t *)((char *)&v13[-2] + v5);\n if (a1 > 0) {\n v7 = v13;\n v8 = 1;\n do {\n *v7 = v8;\n v8 += 2;\n ++v7;\n } while (a1 >= v8);\n if (a1 > 1) {\n v9 = &v13[(unsigned int)(a1 - 1) >> 1];\n v10 = 2;\n do {\n v9[1] = v10;\n v10 += 2;\n ++v9;\n } while (a1 >= v10);\n }\n }\n return (unsigned int)v13[a2 - 1];\n}" + }, + { + "index": 844, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n, int k) {\n int arr[n];\n int i = 0;\n int odd = 1;\n while (odd <= n) {\n arr[i] = odd;\n i += 1;\n odd += 2;\n }\n int even = 2;\n while (even <= n) {\n arr[i] = even;\n i += 1;\n even += 2;\n }\n return arr[k - 1];\n}", + "test": "int main() {\n\n assert(func0(8,5) == 2);\n\n assert(func0(7,2) == 3);\n\n assert(func0(5,2) == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovslq %edi,%rax\nmov %rsp,%rcx\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rcx\nand $0xfffffffffffffff0,%rdx\nmov %rcx,%rax\ncmp %rax,%rsp\nje 11b6 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 11a1 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 1230 \nmov %rsp,%rcx\ntest %edi,%edi\njle 120d \nmov %rcx,%rdx\nmov $0x1,%eax\nnopl 0x0(%rax,%rax,1)\nmov %eax,(%rdx)\nadd $0x2,%eax\nadd $0x4,%rdx\ncmp %eax,%edi\njge 11d8 \nlea -0x1(%rdi),%eax\nshr %eax\nadd $0x1,%eax\ncmp $0x1,%edi\njle 120d \ncltq\nlea (%rcx,%rax,4),%rdx\nmov $0x2,%eax\nnopl (%rax)\nmov %eax,(%rdx)\nadd $0x2,%eax\nadd $0x4,%rdx\ncmp %eax,%edi\njge 1200 \nlea -0x1(%rsi),%eax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\ncltq\nmov (%rcx,%rax,4),%eax\njne 1238 \nleaveq\nretq\nnopw %cs:0x0(%rax,%rax,1)\norq $0x0,-0x8(%rsp,%rdx,1)\njmp 11c4 \ncallq 1050 <__stack_chk_fail@plt>\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov ecx, edi\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmovsxd rax, edi\nmov rdi, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rdi, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rdi\njz short loc_1275\nloc_1260:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rdi\njnz short loc_1260\nloc_1275:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz short loc_12F0\nloc_1283:\nmov rdi, rsp\ntest ecx, ecx\njle short loc_12CE\nmov rdx, rdi\nmov eax, 1\nnop word ptr [rax+rax+00h]\nloc_1298:\nmov [rdx], eax\nadd eax, 2\nadd rdx, 4\ncmp ecx, eax\njge short loc_1298\nlea eax, [rcx-1]\nshr eax, 1\ncmp ecx, 1\njz short loc_12CE\nlea rdx, [rdi+rax*4]\nmov eax, 2\nnop dword ptr [rax+rax+00000000h]\nloc_12C0:\nmov [rdx+4], eax\nadd eax, 2\nadd rdx, 4\ncmp ecx, eax\njge short loc_12C0\nloc_12CE:\nlea eax, [rsi-1]\ncdqe\nmov eax, [rdi+rax*4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_12F8\nleave\nretn\nloc_12F0:\nor [rsp+rdx+1010h+var_1018], 0\njmp short loc_1283\nloc_12F8:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n __int64 v3; // rdx\n _DWORD *v4; // rdi\n __int16 v5; // dx\n signed __int64 v6; // rdx\n void *v7; // rsp\n int *v8; // rdx\n int v9; // eax\n _DWORD *v10; // rdx\n int v11; // eax\n _DWORD v14[1022]; // [rsp+8h] [rbp-1010h] BYREF\n _QWORD v15[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v15[1] = __readfsqword(0x28u);\n v3 = 4LL * a1 + 15;\n v4 = (_DWORD *)((char *)v15 - (v3 & 0xFFFFFFFFFFFFF000LL));\n v5 = v3 & 0xFFF0;\n if ( v15 != (_QWORD *)v4 )\n {\n while ( v14 != v4 )\n ;\n }\n v6 = v5 & 0xFFF;\n v7 = alloca(v6);\n if ( v6 )\n *(_QWORD *)((char *)&v14[-2] + v6) = *(_QWORD *)((char *)&v14[-2] + v6);\n if ( a1 > 0 )\n {\n v8 = v14;\n v9 = 1;\n do\n {\n *v8 = v9;\n v9 += 2;\n ++v8;\n }\n while ( a1 >= v9 );\n if ( a1 != 1 )\n {\n v10 = &v14[(unsigned int)(a1 - 1) >> 1];\n v11 = 2;\n do\n {\n v10[1] = v11;\n v11 += 2;\n ++v10;\n }\n while ( a1 >= v11 );\n }\n }\n return (unsigned int)v14[a2 - 1];\n}", + "ida_strip_asm": "sub_1220:\nendbr64\npush rbp\nmov ecx, edi\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmovsxd rax, edi\nmov rdi, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rdi, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rdi\njz short loc_1275\nloc_1260:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rdi\njnz short loc_1260\nloc_1275:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz short loc_12F0\nloc_1283:\nmov rdi, rsp\ntest ecx, ecx\njle short loc_12CE\nmov rdx, rdi\nmov eax, 1\nnop word ptr [rax+rax+00h]\nloc_1298:\nmov [rdx], eax\nadd eax, 2\nadd rdx, 4\ncmp ecx, eax\njge short loc_1298\nlea eax, [rcx-1]\nshr eax, 1\ncmp ecx, 1\njz short loc_12CE\nlea rdx, [rdi+rax*4]\nmov eax, 2\nnop dword ptr [rax+rax+00000000h]\nloc_12C0:\nmov [rdx+4], eax\nadd eax, 2\nadd rdx, 4\ncmp ecx, eax\njge short loc_12C0\nloc_12CE:\nlea eax, [rsi-1]\ncdqe\nmov eax, [rdi+rax*4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_12F8\nleave\nretn\nloc_12F0:\nor [rsp+rdx+1010h+var_1018], 0\njmp short loc_1283\nloc_12F8:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1220(int a1, int a2)\n{\n __int64 v3; // rdx\n _DWORD *v4; // rdi\n __int16 v5; // dx\n signed __int64 v6; // rdx\n void *v7; // rsp\n int *v8; // rdx\n int v9; // eax\n _DWORD *v10; // rdx\n int v11; // eax\n _DWORD v14[1022]; // [rsp+8h] [rbp-1010h] BYREF\n _QWORD v15[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v15[1] = __readfsqword(0x28u);\n v3 = 4LL * a1 + 15;\n v4 = (_DWORD *)((char *)v15 - (v3 & 0xFFFFFFFFFFFFF000LL));\n v5 = v3 & 0xFFF0;\n if ( v15 != (_QWORD *)v4 )\n {\n while ( v14 != v4 )\n ;\n }\n v6 = v5 & 0xFFF;\n v7 = alloca(v6);\n if ( v6 )\n *(_QWORD *)((char *)&v14[-2] + v6) = *(_QWORD *)((char *)&v14[-2] + v6);\n if ( a1 > 0 )\n {\n v8 = v14;\n v9 = 1;\n do\n {\n *v8 = v9;\n v9 += 2;\n ++v8;\n }\n while ( a1 >= v9 );\n if ( a1 != 1 )\n {\n v10 = &v14[(unsigned int)(a1 - 1) >> 1];\n v11 = 2;\n do\n {\n v10[1] = v11;\n v11 += 2;\n ++v10;\n }\n while ( a1 >= v11 );\n }\n }\n return (unsigned int)v14[a2 - 1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1220(int a1, int a2) {\n long long v3;\n uint32_t *v4;\n short v5;\n signed long long v6;\n void *v7;\n int *v8;\n int v9;\n uint32_t *v10;\n int v11;\n uint32_t v14[1022];\n uint64_t v15[2];\n v15[1] = __readfsqword(40u);\n v3 = 4LL * a1 + 15;\n v4 = (uint32_t *)((char *)v15 - (v3 & 18446744073709547520LL));\n v5 = v3 & 65520;\n if (v15 != (uint64_t *)v4) {\n while (v14 != v4)\n ;\n }\n v6 = v5 & 4095;\n v7 = alloca(v6);\n if (v6)\n *(uint64_t *)((char *)&v14[-2] + v6) = *(uint64_t *)((char *)&v14[-2] + v6);\n if (a1 > 0) {\n v8 = v14;\n v9 = 1;\n do {\n *v8 = v9;\n v9 += 2;\n ++v8;\n } while (a1 >= v9);\n if (a1 != 1) {\n v10 = &v14[(unsigned int)(a1 - 1) >> 1];\n v11 = 2;\n do {\n v10[1] = v11;\n v11 += 2;\n ++v10;\n } while (a1 >= v11);\n }\n }\n return (unsigned int)v14[a2 - 1];\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n long long v3;\n uint32_t *v4;\n short v5;\n signed long long v6;\n void *v7;\n int *v8;\n int v9;\n uint32_t *v10;\n int v11;\n uint32_t v14[1022];\n uint64_t v15[2];\n v15[1] = __readfsqword(40u);\n v3 = 4LL * a1 + 15;\n v4 = (uint32_t *)((char *)v15 - (v3 & 18446744073709547520LL));\n v5 = v3 & 65520;\n if (v15 != (uint64_t *)v4) {\n while (v14 != v4)\n ;\n }\n v6 = v5 & 4095;\n v7 = alloca(v6);\n if (v6)\n *(uint64_t *)((char *)&v14[-2] + v6) = *(uint64_t *)((char *)&v14[-2] + v6);\n if (a1 > 0) {\n v8 = v14;\n v9 = 1;\n do {\n *v8 = v9;\n v9 += 2;\n ++v8;\n } while (a1 >= v9);\n if (a1 != 1) {\n v10 = &v14[(unsigned int)(a1 - 1) >> 1];\n v11 = 2;\n do {\n v10[1] = v11;\n v11 += 2;\n ++v10;\n } while (a1 >= v11);\n }\n }\n return (unsigned int)v14[a2 - 1];\n}" + }, + { + "index": 844, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n, int k) {\n int arr[n];\n int i = 0;\n int odd = 1;\n while (odd <= n) {\n arr[i] = odd;\n i += 1;\n odd += 2;\n }\n int even = 2;\n while (even <= n) {\n arr[i] = even;\n i += 1;\n even += 2;\n }\n return arr[k - 1];\n}", + "test": "int main() {\n\n assert(func0(8,5) == 2);\n\n assert(func0(7,2) == 3);\n\n assert(func0(5,2) == 3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovslq %edi,%rax\nmov %rsp,%rcx\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rcx\nand $0xfffffffffffffff0,%rdx\nmov %rcx,%rax\ncmp %rax,%rsp\nje 11b6 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 11a1 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 1310 \nmov %rsp,%r8\ntest %edi,%edi\njle 12f4 \nlea -0x1(%rdi),%eax\nmov %eax,%ecx\nshr %ecx\nadd $0x1,%ecx\ncmp $0x5,%eax\njbe 1322 \nmov %ecx,%edx\nmovdqa 0xe20(%rip),%xmm0\nmovdqa 0xe38(%rip),%xmm1\nmov %r8,%rax\nshr $0x2,%edx\nshl $0x4,%rdx\nadd %r8,%rdx\nnopl (%rax)\nmovdqa %xmm0,%xmm2\nadd $0x10,%rax\npaddd %xmm1,%xmm0\nmovups %xmm2,-0x10(%rax)\ncmp %rdx,%rax\njne 1208 \nmov %ecx,%eax\nand $0xfffffffc,%eax\nlea 0x1(%rax,%rax,1),%edx\ncmp %eax,%ecx\nje 1255 \nmovslq %eax,%r9\nlea 0x2(%rdx),%r10d\nmov %edx,(%r8,%r9,4)\nlea 0x1(%rax),%r9d\ncmp %r10d,%edi\njl 1255 \nmovslq %r9d,%r9\nadd $0x4,%edx\nadd $0x2,%eax\nmov %r10d,(%r8,%r9,4)\ncmp %edx,%edi\njl 1255 \ncltq\nmov %edx,(%r8,%rax,4)\nmov %ecx,%eax\ncmp $0x1,%edi\njle 12f4 \nlea -0x2(%rdi),%edx\nmov %edx,%r9d\nshr %r9d\nadd $0x1,%r9d\ncmp $0x5,%edx\njbe 131b \nmov %r9d,%edx\nmovslq %ecx,%rax\nmovdqa 0xd9c(%rip),%xmm0\nmovdqa 0xda4(%rip),%xmm1\nshr $0x2,%edx\nlea (%r8,%rax,4),%rax\nshl $0x4,%rdx\nadd %rax,%rdx\nnopw 0x0(%rax,%rax,1)\nmovdqa %xmm0,%xmm2\nadd $0x10,%rax\npaddd %xmm1,%xmm0\nmovups %xmm2,-0x10(%rax)\ncmp %rdx,%rax\njne 12a0 \nmov %r9d,%r10d\nand $0xfffffffc,%r10d\nlea 0x2(%r10,%r10,1),%edx\nlea (%rcx,%r10,1),%eax\ncmp %r10d,%r9d\nje 12f4 \nmovslq %eax,%rcx\nlea 0x2(%rdx),%r9d\nmov %edx,(%r8,%rcx,4)\nlea 0x1(%rax),%ecx\ncmp %r9d,%edi\njl 12f4 \nmovslq %ecx,%rcx\nadd $0x4,%edx\nadd $0x2,%eax\nmov %r9d,(%r8,%rcx,4)\ncmp %edi,%edx\njg 12f4 \ncltq\nmov %edx,(%r8,%rax,4)\nsub $0x1,%esi\nmovslq %esi,%rsi\nmov (%r8,%rsi,4),%eax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\njne 132e \nleaveq\nretq\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 11c8 \nmov $0x2,%edx\njmp 12ca \nxor %eax,%eax\nmov $0x1,%edx\njmpq 122a \ncallq 1050 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov ecx, edi\nmov edi, esi\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmovsxd rax, ecx\nmov rsi, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rsi, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rsi\njz short loc_11B7\nloc_11A2:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rsi\njnz short loc_11A2\nloc_11B7:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1310\nloc_11C9:\nlea r8, [rsp+1010h+var_100D]\nmov rdx, r8\nand r8, 0FFFFFFFFFFFFFFFCh\nshr rdx, 2\ntest ecx, ecx\njle loc_12F4\nlea eax, [rcx-1]\nmov r9d, eax\nshr r9d, 1\nlea esi, [r9+1]\ncmp eax, 5\njbe loc_131B\nmov edx, esi\nmovdqa xmm0, cs:xmmword_2010\nmovdqa xmm1, cs:xmmword_2030\nmov rax, r8\nshr edx, 2\nshl rdx, 4\nadd rdx, r8\nnop word ptr [rax+rax+00000000h]\nloc_1220:\nmovdqa xmm2, xmm0\nadd rax, 10h\npaddd xmm0, xmm1\nmovups xmmword ptr [rax-10h], xmm2\ncmp rdx, rax\njnz short loc_1220\ntest sil, 3\njz short loc_1269\nmov r10d, esi\nand r10d, 0FFFFFFFCh\nlea eax, [r10+r10]\nmovsxd r10, r10d\nlea edx, [rax+1]\nlea r10, [r8+r10*4]\nadd eax, 3\nmov [r10], edx\ncmp ecx, eax\njl short loc_1269\nloc_125A:\nadd edx, 4\nmov [r10+4], eax\ncmp ecx, edx\njl short loc_1269\nmov [r10+8], edx\nloc_1269:\nlea eax, [rcx-2]\nmov r10d, eax\nshr r10d, 1\nadd r10d, 1\ncmp eax, 5\njbe loc_133D\nadd r9d, 1\nmov edx, r10d\nmovdqa xmm0, cs:xmmword_2020\nmovdqa xmm1, cs:xmmword_2030\nmovsxd r9, r9d\nshr edx, 2\nlea rax, [r8+r9*4]\nshl rdx, 4\nadd rdx, rax\nnop word ptr [rax+rax+00000000h]\nloc_12B0:\nmovdqa xmm2, xmm0\nadd rax, 10h\npaddd xmm0, xmm1\nmovups xmmword ptr [rax-10h], xmm2\ncmp rax, rdx\njnz short loc_12B0\nmov eax, r10d\nand eax, 0FFFFFFFCh\nadd esi, eax\nand r10d, 3\nlea eax, [rax+rax+2]\njz short loc_12F4\nloc_12D7:\nmovsxd rsi, esi\nlea rdx, [r8+rsi*4]\nlea esi, [rax+2]\nmov [rdx], eax\ncmp ecx, esi\njl short loc_12F4\nadd eax, 4\nmov [rdx+4], esi\ncmp ecx, eax\njl short loc_12F4\nmov [rdx+8], eax\nloc_12F4:\nsub edi, 1\nmovsxd rdi, edi\nmov eax, [r8+rdi*4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_1353\nleave\nretn\nloc_1310:\nor [rsp+rdx+1010h+var_1018], 0\njmp loc_11C9\nloc_131B:\nmov ds:dword_0[rdx*4], 1\ncmp ecx, 2\njle short loc_1344\nmov r10, r8\nmov eax, 3\nmov edx, 1\njmp loc_125A\nloc_133D:\nmov eax, 2\njmp short loc_12D7\nloc_1344:\njnz short loc_12F4\nmov esi, 1\nxor r9d, r9d\njmp loc_1269\nloc_1353:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n __int64 v4; // rdx\n _DWORD *v5; // rsi\n __int16 v6; // dx\n signed __int64 v7; // rdx\n void *v8; // rsp\n unsigned int v9; // r9d\n unsigned int v10; // esi\n __m128i si128; // xmm0\n __m128i v12; // xmm1\n __m128i *v13; // rax\n __m128i v14; // xmm2\n unsigned int v15; // eax\n int v16; // edx\n int *v17; // r10\n int v18; // eax\n int v19; // edx\n unsigned int v20; // r10d\n __m128i v21; // xmm0\n __m128i v22; // xmm1\n __m128i *v23; // rax\n __m128i *v24; // rdx\n __m128i v25; // xmm2\n unsigned int v26; // eax\n unsigned int *v27; // rdx\n unsigned int v28; // esi\n int v29; // eax\n _DWORD v32[1022]; // [rsp+8h] [rbp-1010h] BYREF\n _QWORD v33[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v33[1] = __readfsqword(0x28u);\n v4 = 4LL * a1 + 15;\n v5 = (_DWORD *)((char *)v33 - (v4 & 0xFFFFFFFFFFFFF000LL));\n v6 = v4 & 0xFFF0;\n if ( v33 != (_QWORD *)v5 )\n {\n while ( v32 != v5 )\n ;\n }\n v7 = v6 & 0xFFF;\n v8 = alloca(v7);\n if ( v7 )\n *(_QWORD *)((char *)&v32[-2] + v7) = *(_QWORD *)((char *)&v32[-2] + v7);\n if ( a1 <= 0 )\n return (unsigned int)v32[a2 - 1];\n v9 = (unsigned int)(a1 - 1) >> 1;\n v10 = v9 + 1;\n if ( (unsigned int)(a1 - 1) <= 5 )\n {\n v32[0] = 1;\n if ( a1 <= 2 )\n {\n if ( a1 != 2 )\n return (unsigned int)v32[a2 - 1];\n v10 = 1;\n v9 = 0;\n goto LABEL_13;\n }\n v17 = v32;\n v18 = 3;\n v16 = 1;\n goto LABEL_11;\n }\n si128 = _mm_load_si128((const __m128i *)&xmmword_2010);\n v12 = _mm_load_si128((const __m128i *)&xmmword_2030);\n v13 = (__m128i *)v32;\n do\n {\n v14 = si128;\n ++v13;\n si128 = _mm_add_epi32(si128, v12);\n v13[-1] = v14;\n }\n while ( &v32[4 * (v10 >> 2)] != (_DWORD *)v13 );\n if ( (v10 & 3) != 0 )\n {\n v15 = 2 * (v10 & 0xFFFFFFFC);\n v16 = v15 + 1;\n v17 = &v32[v10 & 0xFFFFFFFC];\n v18 = v15 + 3;\n *v17 = v16;\n if ( a1 >= v18 )\n {\nLABEL_11:\n v19 = v16 + 4;\n v17[1] = v18;\n if ( a1 >= v19 )\n v17[2] = v19;\n }\n }\nLABEL_13:\n v20 = ((unsigned int)(a1 - 2) >> 1) + 1;\n if ( (unsigned int)(a1 - 2) <= 5 )\n {\n v26 = 2;\n }\n else\n {\n v21 = _mm_load_si128((const __m128i *)&xmmword_2020);\n v22 = _mm_load_si128((const __m128i *)&xmmword_2030);\n v23 = (__m128i *)&v32[v9 + 1];\n v24 = &v23[v20 >> 2];\n do\n {\n v25 = v21;\n ++v23;\n v21 = _mm_add_epi32(v21, v22);\n v23[-1] = v25;\n }\n while ( v23 != v24 );\n v10 += v20 & 0xFFFFFFFC;\n v26 = 2 * (v20 & 0xFFFFFFFC) + 2;\n if ( (v20 & 3) == 0 )\n return (unsigned int)v32[a2 - 1];\n }\n v27 = &v32[v10];\n v28 = v26 + 2;\n *v27 = v26;\n if ( a1 >= (int)(v26 + 2) )\n {\n v29 = v26 + 4;\n v27[1] = v28;\n if ( a1 >= v29 )\n v27[2] = v29;\n }\n return (unsigned int)v32[a2 - 1];\n}", + "ida_strip_asm": "sub_1160:\nendbr64\npush rbp\nmov ecx, edi\nmov edi, esi\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmovsxd rax, ecx\nmov rsi, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rsi, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rsi\njz short loc_11B7\nloc_11A2:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rsi\njnz short loc_11A2\nloc_11B7:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1310\nloc_11C9:\nlea r8, [rsp+1010h+var_100D]\nmov rdx, r8\nand r8, 0FFFFFFFFFFFFFFFCh\nshr rdx, 2\ntest ecx, ecx\njle loc_12F4\nlea eax, [rcx-1]\nmov r9d, eax\nshr r9d, 1\nlea esi, [r9+1]\ncmp eax, 5\njbe loc_131B\nmov edx, esi\nmovdqa xmm0, cs:xmmword_2010\nmovdqa xmm1, cs:xmmword_2030\nmov rax, r8\nshr edx, 2\nshl rdx, 4\nadd rdx, r8\nnop word ptr [rax+rax+00000000h]\nloc_1220:\nmovdqa xmm2, xmm0\nadd rax, 10h\npaddd xmm0, xmm1\nmovups xmmword ptr [rax-10h], xmm2\ncmp rdx, rax\njnz short loc_1220\ntest sil, 3\njz short loc_1269\nmov r10d, esi\nand r10d, 0FFFFFFFCh\nlea eax, [r10+r10]\nmovsxd r10, r10d\nlea edx, [rax+1]\nlea r10, [r8+r10*4]\nadd eax, 3\nmov [r10], edx\ncmp ecx, eax\njl short loc_1269\nloc_125A:\nadd edx, 4\nmov [r10+4], eax\ncmp ecx, edx\njl short loc_1269\nmov [r10+8], edx\nloc_1269:\nlea eax, [rcx-2]\nmov r10d, eax\nshr r10d, 1\nadd r10d, 1\ncmp eax, 5\njbe loc_133D\nadd r9d, 1\nmov edx, r10d\nmovdqa xmm0, cs:xmmword_2020\nmovdqa xmm1, cs:xmmword_2030\nmovsxd r9, r9d\nshr edx, 2\nlea rax, [r8+r9*4]\nshl rdx, 4\nadd rdx, rax\nnop word ptr [rax+rax+00000000h]\nloc_12B0:\nmovdqa xmm2, xmm0\nadd rax, 10h\npaddd xmm0, xmm1\nmovups xmmword ptr [rax-10h], xmm2\ncmp rax, rdx\njnz short loc_12B0\nmov eax, r10d\nand eax, 0FFFFFFFCh\nadd esi, eax\nand r10d, 3\nlea eax, [rax+rax+2]\njz short loc_12F4\nloc_12D7:\nmovsxd rsi, esi\nlea rdx, [r8+rsi*4]\nlea esi, [rax+2]\nmov [rdx], eax\ncmp ecx, esi\njl short loc_12F4\nadd eax, 4\nmov [rdx+4], esi\ncmp ecx, eax\njl short loc_12F4\nmov [rdx+8], eax\nloc_12F4:\nsub edi, 1\nmovsxd rdi, edi\nmov eax, [r8+rdi*4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_1353\nleave\nretn\nloc_1310:\nor [rsp+rdx+1010h+var_1018], 0\njmp loc_11C9\nloc_131B:\nmov ds:dword_0[rdx*4], 1\ncmp ecx, 2\njle short loc_1344\nmov r10, r8\nmov eax, 3\nmov edx, 1\njmp loc_125A\nloc_133D:\nmov eax, 2\njmp short loc_12D7\nloc_1344:\njnz short loc_12F4\nmov esi, 1\nxor r9d, r9d\njmp loc_1269\nloc_1353:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1160(int a1, int a2)\n{\n __int64 v4; // rdx\n _DWORD *v5; // rsi\n __int16 v6; // dx\n signed __int64 v7; // rdx\n void *v8; // rsp\n unsigned int v9; // r9d\n unsigned int v10; // esi\n __m128i si128; // xmm0\n __m128i v12; // xmm1\n __m128i *v13; // rax\n __m128i v14; // xmm2\n unsigned int v15; // eax\n int v16; // edx\n int *v17; // r10\n int v18; // eax\n int v19; // edx\n unsigned int v20; // r10d\n __m128i v21; // xmm0\n __m128i v22; // xmm1\n __m128i *v23; // rax\n __m128i *v24; // rdx\n __m128i v25; // xmm2\n unsigned int v26; // eax\n unsigned int *v27; // rdx\n unsigned int v28; // esi\n int v29; // eax\n _DWORD v32[1022]; // [rsp+8h] [rbp-1010h] BYREF\n _QWORD v33[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v33[1] = __readfsqword(0x28u);\n v4 = 4LL * a1 + 15;\n v5 = (_DWORD *)((char *)v33 - (v4 & 0xFFFFFFFFFFFFF000LL));\n v6 = v4 & 0xFFF0;\n if ( v33 != (_QWORD *)v5 )\n {\n while ( v32 != v5 )\n ;\n }\n v7 = v6 & 0xFFF;\n v8 = alloca(v7);\n if ( v7 )\n *(_QWORD *)((char *)&v32[-2] + v7) = *(_QWORD *)((char *)&v32[-2] + v7);\n if ( a1 <= 0 )\n return (unsigned int)v32[a2 - 1];\n v9 = (unsigned int)(a1 - 1) >> 1;\n v10 = v9 + 1;\n if ( (unsigned int)(a1 - 1) <= 5 )\n {\n v32[0] = 1;\n if ( a1 <= 2 )\n {\n if ( a1 != 2 )\n return (unsigned int)v32[a2 - 1];\n v10 = 1;\n v9 = 0;\n goto LABEL_13;\n }\n v17 = v32;\n v18 = 3;\n v16 = 1;\n goto LABEL_11;\n }\n si128 = _mm_load_si128((const __m128i *)&xmmword_2010);\n v12 = _mm_load_si128((const __m128i *)&xmmword_2030);\n v13 = (__m128i *)v32;\n do\n {\n v14 = si128;\n ++v13;\n si128 = _mm_add_epi32(si128, v12);\n v13[-1] = v14;\n }\n while ( &v32[4 * (v10 >> 2)] != (_DWORD *)v13 );\n if ( (v10 & 3) != 0 )\n {\n v15 = 2 * (v10 & 0xFFFFFFFC);\n v16 = v15 + 1;\n v17 = &v32[v10 & 0xFFFFFFFC];\n v18 = v15 + 3;\n *v17 = v16;\n if ( a1 >= v18 )\n {\nLABEL_11:\n v19 = v16 + 4;\n v17[1] = v18;\n if ( a1 >= v19 )\n v17[2] = v19;\n }\n }\nLABEL_13:\n v20 = ((unsigned int)(a1 - 2) >> 1) + 1;\n if ( (unsigned int)(a1 - 2) <= 5 )\n {\n v26 = 2;\n }\n else\n {\n v21 = _mm_load_si128((const __m128i *)&xmmword_2020);\n v22 = _mm_load_si128((const __m128i *)&xmmword_2030);\n v23 = (__m128i *)&v32[v9 + 1];\n v24 = &v23[v20 >> 2];\n do\n {\n v25 = v21;\n ++v23;\n v21 = _mm_add_epi32(v21, v22);\n v23[-1] = v25;\n }\n while ( v23 != v24 );\n v10 += v20 & 0xFFFFFFFC;\n v26 = 2 * (v20 & 0xFFFFFFFC) + 2;\n if ( (v20 & 3) == 0 )\n return (unsigned int)v32[a2 - 1];\n }\n v27 = &v32[v10];\n v28 = v26 + 2;\n *v27 = v26;\n if ( a1 >= (int)(v26 + 2) )\n {\n v29 = v26 + 4;\n v27[1] = v28;\n if ( a1 >= v29 )\n v27[2] = v29;\n }\n return (unsigned int)v32[a2 - 1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1160(int a1, int a2) {\n long long v4;\n uint32_t *v5;\n short v6;\n signed long long v7;\n void *v8;\n unsigned int v9;\n unsigned int v10;\n __m128i si128;\n __m128i v12;\n __m128i *v13;\n __m128i v14;\n unsigned int v15;\n int v16;\n int *v17;\n int v18;\n int v19;\n unsigned int v20;\n __m128i v21;\n __m128i v22;\n __m128i *v23;\n __m128i *v24;\n __m128i v25;\n unsigned int v26;\n unsigned int *v27;\n unsigned int v28;\n int v29;\n uint32_t v32[1022];\n uint64_t v33[2];\n v33[1] = __readfsqword(40u);\n v4 = 4LL * a1 + 15;\n v5 = (uint32_t *)((char *)v33 - (v4 & 18446744073709547520LL));\n v6 = v4 & 65520;\n if (v33 != (uint64_t *)v5) {\n while (v32 != v5)\n ;\n }\n v7 = v6 & 4095;\n v8 = alloca(v7);\n if (v7)\n *(uint64_t *)((char *)&v32[-2] + v7) = *(uint64_t *)((char *)&v32[-2] + v7);\n if (a1 <= 0) return (unsigned int)v32[a2 - 1];\n v9 = (unsigned int)(a1 - 1) >> 1;\n v10 = v9 + 1;\n if ((unsigned int)(a1 - 1) <= 5) {\n v32[0] = 1;\n if (a1 <= 2) {\n if (a1 != 2) return (unsigned int)v32[a2 - 1];\n v10 = 1;\n v9 = 0;\n goto LABEL_13;\n }\n v17 = v32;\n v18 = 3;\n v16 = 1;\n goto LABEL_11;\n }\n si128 = _mm_load_si128((const __m128i *)&xmmword_2010);\n v12 = _mm_load_si128((const __m128i *)&xmmword_2030);\n v13 = (__m128i *)v32;\n do {\n v14 = si128;\n ++v13;\n si128 = _mm_add_epi32(si128, v12);\n v13[-1] = v14;\n } while (&v32[4 * (v10 >> 2)] != (uint32_t *)v13);\n if ((v10 & 3) != 0) {\n v15 = 2 * (v10 & 4294967292);\n v16 = v15 + 1;\n v17 = &v32[v10 & 4294967292];\n v18 = v15 + 3;\n *v17 = v16;\n if (a1 >= v18) {\n LABEL_11:\n v19 = v16 + 4;\n v17[1] = v18;\n if (a1 >= v19) v17[2] = v19;\n }\n }\nLABEL_13:\n v20 = ((unsigned int)(a1 - 2) >> 1) + 1;\n if ((unsigned int)(a1 - 2) <= 5) {\n v26 = 2;\n } else {\n v21 = _mm_load_si128((const __m128i *)&xmmword_2020);\n v22 = _mm_load_si128((const __m128i *)&xmmword_2030);\n v23 = (__m128i *)&v32[v9 + 1];\n v24 = &v23[v20 >> 2];\n do {\n v25 = v21;\n ++v23;\n v21 = _mm_add_epi32(v21, v22);\n v23[-1] = v25;\n } while (v23 != v24);\n v10 += v20 & 4294967292;\n v26 = 2 * (v20 & 4294967292) + 2;\n if ((v20 & 3) == 0) return (unsigned int)v32[a2 - 1];\n }\n v27 = &v32[v10];\n v28 = v26 + 2;\n *v27 = v26;\n if (a1 >= (int)(v26 + 2)) {\n v29 = v26 + 4;\n v27[1] = v28;\n if (a1 >= v29) v27[2] = v29;\n }\n return (unsigned int)v32[a2 - 1];\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n long long v4;\n uint32_t *v5;\n short v6;\n signed long long v7;\n void *v8;\n unsigned int v9;\n unsigned int v10;\n __m128i si128;\n __m128i v12;\n __m128i *v13;\n __m128i v14;\n unsigned int v15;\n int v16;\n int *v17;\n int v18;\n int v19;\n unsigned int v20;\n __m128i v21;\n __m128i v22;\n __m128i *v23;\n __m128i *v24;\n __m128i v25;\n unsigned int v26;\n unsigned int *v27;\n unsigned int v28;\n int v29;\n uint32_t v32[1022];\n uint64_t v33[2];\n v33[1] = __readfsqword(40u);\n v4 = 4LL * a1 + 15;\n v5 = (uint32_t *)((char *)v33 - (v4 & 18446744073709547520LL));\n v6 = v4 & 65520;\n if (v33 != (uint64_t *)v5) {\n while (v32 != v5)\n ;\n }\n v7 = v6 & 4095;\n v8 = alloca(v7);\n if (v7)\n *(uint64_t *)((char *)&v32[-2] + v7) = *(uint64_t *)((char *)&v32[-2] + v7);\n if (a1 <= 0) return (unsigned int)v32[a2 - 1];\n v9 = (unsigned int)(a1 - 1) >> 1;\n v10 = v9 + 1;\n if ((unsigned int)(a1 - 1) <= 5) {\n v32[0] = 1;\n if (a1 <= 2) {\n if (a1 != 2) return (unsigned int)v32[a2 - 1];\n v10 = 1;\n v9 = 0;\n goto LABEL_13;\n }\n v17 = v32;\n v18 = 3;\n v16 = 1;\n goto LABEL_11;\n }\n si128 = _mm_load_si128((const __m128i *)&xmmword_2010);\n v12 = _mm_load_si128((const __m128i *)&xmmword_2030);\n v13 = (__m128i *)v32;\n do {\n v14 = si128;\n ++v13;\n si128 = _mm_add_epi32(si128, v12);\n v13[-1] = v14;\n } while (&v32[4 * (v10 >> 2)] != (uint32_t *)v13);\n if ((v10 & 3) != 0) {\n v15 = 2 * (v10 & 4294967292);\n v16 = v15 + 1;\n v17 = &v32[v10 & 4294967292];\n v18 = v15 + 3;\n *v17 = v16;\n if (a1 >= v18) {\n LABEL_11:\n v19 = v16 + 4;\n v17[1] = v18;\n if (a1 >= v19) v17[2] = v19;\n }\n }\nLABEL_13:\n v20 = ((unsigned int)(a1 - 2) >> 1) + 1;\n if ((unsigned int)(a1 - 2) <= 5) {\n v26 = 2;\n } else {\n v21 = _mm_load_si128((const __m128i *)&xmmword_2020);\n v22 = _mm_load_si128((const __m128i *)&xmmword_2030);\n v23 = (__m128i *)&v32[v9 + 1];\n v24 = &v23[v20 >> 2];\n do {\n v25 = v21;\n ++v23;\n v21 = _mm_add_epi32(v21, v22);\n v23[-1] = v25;\n } while (v23 != v24);\n v10 += v20 & 4294967292;\n v26 = 2 * (v20 & 4294967292) + 2;\n if ((v20 & 3) == 0) return (unsigned int)v32[a2 - 1];\n }\n v27 = &v32[v10];\n v28 = v26 + 2;\n *v27 = v26;\n if (a1 >= (int)(v26 + 2)) {\n v29 = v26 + 4;\n v27[1] = v28;\n if (a1 >= v29) v27[2] = v29;\n }\n return (unsigned int)v32[a2 - 1];\n}" + }, + { + "index": 845, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n < 0) {\n return 0;\n }\n if (n <= 1) {\n return 1;\n }\n double x = (n * log10((double)n / M_E) + log10(2 * M_PI * n) / 2.0);\n return (int)floor(x) + 1;\n}", + "test": "int main() {\n\n assert(func0(7) == 4);\n\n assert(func0(5) == 3);\n\n assert(func0(4) == 2);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %edi,-0x14(%rbp)\ncmpl $0x0,-0x14(%rbp)\njns 11a5 \nmov $0x0,%eax\njmp 121d \ncmpl $0x1,-0x14(%rbp)\njg 11b2 \nmov $0x1,%eax\njmp 121d \ncvtsi2sdl -0x14(%rbp),%xmm3\nmovsd %xmm3,-0x20(%rbp)\ncvtsi2sdl -0x14(%rbp),%xmm0\nmovsd 0xeaf(%rip),%xmm1\ndivsd %xmm1,%xmm0\ncallq 1080 \nmulsd -0x20(%rbp),%xmm0\nmovsd %xmm0,-0x20(%rbp)\ncvtsi2sdl -0x14(%rbp),%xmm1\nmovsd 0xe97(%rip),%xmm0\nmulsd %xmm1,%xmm0\ncallq 1080 \nmovsd 0xe8e(%rip),%xmm1\ndivsd %xmm1,%xmm0\naddsd -0x20(%rbp),%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmov -0x8(%rbp),%rax\nmovq %rax,%xmm0\ncallq 1090 \ncvttsd2si %xmm0,%eax\nadd $0x1,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\ncmp [rbp+var_14], 0\njns short loc_11A8\nmov eax, 0\njmp locret_1251\nloc_11A8:\ncmp [rbp+var_14], 1\njg short loc_11B8\nmov eax, 1\njmp locret_1251\nloc_11B8:\npxor xmm4, xmm4\ncvtsi2sd xmm4, [rbp+var_14]\nmovsd [rbp+var_20], xmm4\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_14]\nmovsd xmm1, cs:qword_2058\ndivsd xmm0, xmm1\nmovq rax, xmm0\nmovq xmm0, rax; x\ncall _log10\nmulsd xmm0, [rbp+var_20]\nmovsd [rbp+var_20], xmm0\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_14]\nmovsd xmm0, cs:qword_2060\nmulsd xmm1, xmm0\nmovq rax, xmm1\nmovq xmm0, rax; x\ncall _log10\nmovq rax, xmm0\nmovsd xmm1, cs:qword_2068\nmovq xmm3, rax\ndivsd xmm3, xmm1\nmovapd xmm0, xmm3\naddsd xmm0, [rbp+var_20]\nmovsd [rbp+x], xmm0\nmov rax, [rbp+x]\nmovq xmm0, rax; x\ncall _floor\ncvttsd2si eax, xmm0\nadd eax, 1\nlocret_1251:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n double v2; // [rsp+0h] [rbp-20h]\n double x; // [rsp+18h] [rbp-8h]\n\n if ( a1 < 0 )\n return 0LL;\n if ( a1 <= 1 )\n return 1LL;\n v2 = log10((double)a1 / 2.718281828459045) * (double)a1;\n x = log10((double)a1 * 6.283185307179586) / 2.0 + v2;\n return (unsigned int)((int)floor(x) + 1);\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\ncmp [rbp+var_14], 0\njns short loc_11A8\nmov eax, 0\njmp locret_1251\nloc_11A8:\ncmp [rbp+var_14], 1\njg short loc_11B8\nmov eax, 1\njmp locret_1251\nloc_11B8:\npxor xmm4, xmm4\ncvtsi2sd xmm4, [rbp+var_14]\nmovsd [rbp+var_20], xmm4\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_14]\nmovsd xmm1, cs:qword_2058\ndivsd xmm0, xmm1\nmovq rax, xmm0\nmovq xmm0, rax; x\ncall _log10\nmulsd xmm0, [rbp+var_20]\nmovsd [rbp+var_20], xmm0\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_14]\nmovsd xmm0, cs:qword_2060\nmulsd xmm1, xmm0\nmovq rax, xmm1\nmovq xmm0, rax; x\ncall _log10\nmovq rax, xmm0\nmovsd xmm1, cs:qword_2068\nmovq xmm3, rax\ndivsd xmm3, xmm1\nmovapd xmm0, xmm3\naddsd xmm0, [rbp+var_20]\nmovsd [rbp+x], xmm0\nmov rax, [rbp+x]\nmovq xmm0, rax; x\ncall _floor\ncvttsd2si eax, xmm0\nadd eax, 1\nlocret_1251:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(int a1)\n{\n double v2; // [rsp+0h] [rbp-20h]\n double x; // [rsp+18h] [rbp-8h]\n\n if ( a1 < 0 )\n return 0LL;\n if ( a1 <= 1 )\n return 1LL;\n v2 = log10((double)a1 / 2.718281828459045) * (double)a1;\n x = log10((double)a1 * 6.283185307179586) / 2.0 + v2;\n return (unsigned int)((int)floor(x) + 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(int a1) {\n double v2;\n double x;\n if (a1 < 0) return 0LL;\n if (a1 <= 1) return 1LL;\n v2 = log10((double)a1 / 2.718281828459045) * (double)a1;\n x = log10((double)a1 * 6.283185307179586) / 2.0 + v2;\n return (unsigned int)((int)floor(x) + 1);\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n double v2;\n double x;\n if (a1 < 0) return 0LL;\n if (a1 <= 1) return 1LL;\n v2 = log10((double)a1 / 2.718281828459045) * (double)a1;\n x = log10((double)a1 * 6.283185307179586) / 2.0 + v2;\n return (unsigned int)((int)floor(x) + 1);\n}" + }, + { + "index": 845, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n < 0) {\n return 0;\n }\n if (n <= 1) {\n return 1;\n }\n double x = (n * log10((double)n / M_E) + log10(2 * M_PI * n) / 2.0);\n return (int)floor(x) + 1;\n}", + "test": "int main() {\n\n assert(func0(7) == 4);\n\n assert(func0(5) == 3);\n\n assert(func0(4) == 2);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x0,%eax\ntest %edi,%edi\njs 1246 \nmov $0x1,%eax\ncmp $0x1,%edi\njle 1246 \nsub $0x18,%rsp\npxor %xmm5,%xmm5\ncvtsi2sd %edi,%xmm5\nmovsd %xmm5,(%rsp)\nmovapd %xmm5,%xmm0\ndivsd 0xed3(%rip),%xmm0\ncallq 1070 \nmovsd %xmm0,0x8(%rsp)\nmovsd (%rsp),%xmm6\nmulsd 0xec3(%rip),%xmm6\nmovapd %xmm6,%xmm0\ncallq 1070 \nmovapd %xmm0,%xmm1\nmovsd (%rsp),%xmm5\nmulsd 0x8(%rsp),%xmm5\nmovapd %xmm5,%xmm0\nmulsd 0xea7(%rip),%xmm1\naddsd %xmm1,%xmm0\nmovapd %xmm0,%xmm1\nmovsd 0xeaf(%rip),%xmm3\nmovapd %xmm0,%xmm2\nandpd %xmm3,%xmm2\nmovsd 0xe8f(%rip),%xmm4\nucomisd %xmm2,%xmm4\njbe 123a \ncvttsd2si %xmm0,%rax\npxor %xmm2,%xmm2\ncvtsi2sd %rax,%xmm2\nmovapd %xmm2,%xmm1\ncmpnlesd %xmm0,%xmm1\nmovsd 0xe72(%rip),%xmm4\nandpd %xmm4,%xmm1\nsubsd %xmm1,%xmm2\nandnpd %xmm0,%xmm3\nmovapd %xmm3,%xmm1\norpd %xmm2,%xmm1\ncvttsd2si %xmm1,%eax\nadd $0x1,%eax\nadd $0x18,%rsp\nretq\nretq\n", + "ida_asm": "func0:\nendbr64\nmov eax, 0\ntest edi, edi\njs locret_1246\nmov eax, 1\ncmp edi, 1\njle locret_1246\nsub rsp, 18h\npxor xmm5, xmm5\ncvtsi2sd xmm5, edi\nmovsd [rsp+18h+var_18], xmm5\nmovapd xmm0, xmm5\ndivsd xmm0, cs:qword_2058; x\ncall _log10\nmovsd [rsp+18h+var_10], xmm0\nmovsd xmm6, [rsp+18h+var_18]\nmulsd xmm6, cs:qword_2060\nmovapd xmm0, xmm6; x\ncall _log10\nmovapd xmm1, xmm0\nmovsd xmm5, [rsp+18h+var_18]\nmulsd xmm5, [rsp+18h+var_10]\nmovapd xmm0, xmm5\nmulsd xmm1, cs:qword_2068\naddsd xmm0, xmm1\nmovapd xmm3, xmm0\nmovsd xmm2, cs:qword_2080\nmovapd xmm1, xmm0\nandpd xmm1, xmm2\nmovsd xmm4, cs:qword_2070\nucomisd xmm4, xmm1\njbe short loc_123A\ncvttsd2si rax, xmm0\npxor xmm1, xmm1\ncvtsi2sd xmm1, rax\nmovapd xmm3, xmm1\ncmpnlesd xmm3, xmm0\nmovsd xmm4, cs:qword_2078\nandpd xmm3, xmm4\nsubsd xmm1, xmm3\nandnpd xmm2, xmm0\nmovapd xmm3, xmm1\norpd xmm3, xmm2\nloc_123A:\ncvttsd2si eax, xmm3\nadd eax, 1\nadd rsp, 18h\nretn\nlocret_1246:\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n __int64 result; // rax\n __m128d v2; // xmm0\n double v3; // xmm3_8\n __m128d v4; // xmm1\n double v5; // [rsp+8h] [rbp-10h]\n\n result = 0LL;\n if ( a1 >= 0 )\n {\n result = 1LL;\n if ( a1 > 1 )\n {\n v5 = log10((double)a1 / 2.718281828459045);\n v2.m128d_f64[0] = (double)a1 * v5 + log10((double)a1 * 6.283185307179586) * 0.5;\n v3 = v2.m128d_f64[0];\n if ( fabs(v2.m128d_f64[0]) < 4.503599627370496e15 )\n {\n v4 = 0LL;\n v4.m128d_f64[0] = (double)(int)v2.m128d_f64[0];\n *(_QWORD *)&v3 = COERCE_UNSIGNED_INT64(v4.m128d_f64[0] - COERCE_DOUBLE(*(_OWORD *)&_mm_cmpgt_sd(v4, v2) & 0x3FF0000000000000LL)) | *(_QWORD *)&v2.m128d_f64[0] & 0x8000000000000000LL;\n }\n return (unsigned int)((int)v3 + 1);\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov eax, 0\ntest edi, edi\njs locret_1246\nmov eax, 1\ncmp edi, 1\njle locret_1246\nsub rsp, 18h\npxor xmm5, xmm5\ncvtsi2sd xmm5, edi\nmovsd [rsp+18h+var_18], xmm5\nmovapd xmm0, xmm5\ndivsd xmm0, cs:qword_2058; x\ncall _log10\nmovsd [rsp+18h+var_10], xmm0\nmovsd xmm6, [rsp+18h+var_18]\nmulsd xmm6, cs:qword_2060\nmovapd xmm0, xmm6; x\ncall _log10\nmovapd xmm1, xmm0\nmovsd xmm5, [rsp+18h+var_18]\nmulsd xmm5, [rsp+18h+var_10]\nmovapd xmm0, xmm5\nmulsd xmm1, cs:qword_2068\naddsd xmm0, xmm1\nmovapd xmm3, xmm0\nmovsd xmm2, cs:qword_2080\nmovapd xmm1, xmm0\nandpd xmm1, xmm2\nmovsd xmm4, cs:qword_2070\nucomisd xmm4, xmm1\njbe short loc_123A\ncvttsd2si rax, xmm0\npxor xmm1, xmm1\ncvtsi2sd xmm1, rax\nmovapd xmm3, xmm1\ncmpnlesd xmm3, xmm0\nmovsd xmm4, cs:qword_2078\nandpd xmm3, xmm4\nsubsd xmm1, xmm3\nandnpd xmm2, xmm0\nmovapd xmm3, xmm1\norpd xmm3, xmm2\nloc_123A:\ncvttsd2si eax, xmm3\nadd eax, 1\nadd rsp, 18h\nretn\nlocret_1246:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n __int64 result; // rax\n __m128d v2; // xmm0\n double v3; // xmm3_8\n __m128d v4; // xmm1\n double v5; // [rsp+8h] [rbp-10h]\n\n result = 0LL;\n if ( a1 >= 0 )\n {\n result = 1LL;\n if ( a1 > 1 )\n {\n v5 = log10((double)a1 / 2.718281828459045);\n v2.m128d_f64[0] = (double)a1 * v5 + log10((double)a1 * 6.283185307179586) * 0.5;\n v3 = v2.m128d_f64[0];\n if ( fabs(v2.m128d_f64[0]) < 4.503599627370496e15 )\n {\n v4 = 0LL;\n v4.m128d_f64[0] = (double)(int)v2.m128d_f64[0];\n *(_QWORD *)&v3 = COERCE_UNSIGNED_INT64(v4.m128d_f64[0] - COERCE_DOUBLE(*(_OWORD *)&_mm_cmpgt_sd(v4, v2) & 0x3FF0000000000000LL)) | *(_QWORD *)&v2.m128d_f64[0] & 0x8000000000000000LL;\n }\n return (unsigned int)((int)v3 + 1);\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n long long result;\n __m128d v2;\n double v3;\n __m128d v4;\n double v5;\n result = 0LL;\n if (a1 >= 0) {\n result = 1LL;\n if (a1 > 1) {\n v5 = log10((double)a1 / 2.718281828459045);\n v2.m128d_f64[0] =\n (double)a1 * v5 + log10((double)a1 * 6.283185307179586) * 0.5;\n v3 = v2.m128d_f64[0];\n if (fabs(v2.m128d_f64[0]) < 4.503599627370496e15) {\n v4 = 0LL;\n v4.m128d_f64[0] = (double)(int)v2.m128d_f64[0];\n *(uint64_t *)&v3 =\n COERCE_UNSIGNED_INT64(\n v4.m128d_f64[0] -\n COERCE_DOUBLE(*(long double *)&_mm_cmpgt_sd(v4, v2) &\n 4607182418800017408LL)) |\n *(uint64_t *)&v2.m128d_f64[0] & 9223372036854775808LL;\n }\n return (unsigned int)((int)v3 + 1);\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n long long result;\n __m128d v2;\n double v3;\n __m128d v4;\n double v5;\n result = 0LL;\n if (a1 >= 0) {\n result = 1LL;\n if (a1 > 1) {\n v5 = log10((double)a1 / 2.718281828459045);\n v2.m128d_f64[0] =\n (double)a1 * v5 + log10((double)a1 * 6.283185307179586) * 0.5;\n v3 = v2.m128d_f64[0];\n if (fabs(v2.m128d_f64[0]) < 4.503599627370496e15) {\n v4 = 0LL;\n v4.m128d_f64[0] = (double)(int)v2.m128d_f64[0];\n *(uint64_t *)&v3 =\n COERCE_UNSIGNED_INT64(\n v4.m128d_f64[0] -\n COERCE_DOUBLE(*(long double *)&_mm_cmpgt_sd(v4, v2) &\n 4607182418800017408LL)) |\n *(uint64_t *)&v2.m128d_f64[0] & 9223372036854775808LL;\n }\n return (unsigned int)((int)v3 + 1);\n }\n }\n return result;\n}" + }, + { + "index": 845, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n < 0) {\n return 0;\n }\n if (n <= 1) {\n return 1;\n }\n double x = (n * log10((double)n / M_E) + log10(2 * M_PI * n) / 2.0);\n return (int)floor(x) + 1;\n}", + "test": "int main() {\n\n assert(func0(7) == 4);\n\n assert(func0(5) == 3);\n\n assert(func0(4) == 2);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\njs 12f0 \ncmp $0x1,%edi\njle 12e8 \njmpq 1210 \nnopw 0x0(%rax,%rax,1)\nmov $0x1,%eax\nretq\nxchg %ax,%ax\nxor %eax,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0_part_0:\npxor xmm5, xmm5\nsub rsp, 18h\ncvtsi2sd xmm5, edi\nmovapd xmm0, xmm5\nmovsd [rsp+18h+var_18], xmm5\ndivsd xmm0, cs:qword_2058; x\ncall _log10\nmovsd xmm6, [rsp+18h+var_18]\nmulsd xmm6, cs:qword_2060\nmovsd [rsp+18h+var_10], xmm0\nmovapd xmm0, xmm6; x\ncall _log10\nmovsd xmm5, [rsp+18h+var_18]\nmulsd xmm5, [rsp+18h+var_10]\nmovapd xmm1, xmm0\nmovsd xmm2, cs:qword_2080\nmovsd xmm3, cs:qword_2070\nmulsd xmm1, cs:qword_2068\nmovapd xmm0, xmm5\naddsd xmm0, xmm1\nmovapd xmm1, xmm0\nandpd xmm1, xmm2\nucomisd xmm3, xmm1\njbe short loc_12BE\ncvttsd2si rax, xmm0\npxor xmm1, xmm1\nmovsd xmm4, cs:qword_2078\nandnpd xmm2, xmm0\ncvtsi2sd xmm1, rax\nmovapd xmm3, xmm1\ncmpnlesd xmm3, xmm0\nandpd xmm3, xmm4\nsubsd xmm1, xmm3\norpd xmm1, xmm2\nmovapd xmm0, xmm1\nloc_12BE:\ncvttsd2si eax, xmm0\nadd rsp, 18h\nadd eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0_part_0(int a1)\n{\n __m128d v1; // xmm0\n __m128d v2; // xmm1\n double v4; // [rsp+8h] [rbp-10h]\n\n v4 = log10((double)a1 / 2.718281828459045);\n v1.m128d_f64[0] = (double)a1 * v4 + log10((double)a1 * 6.283185307179586) * 0.5;\n if ( fabs(v1.m128d_f64[0]) < 4.503599627370496e15 )\n {\n v2 = 0LL;\n v2.m128d_f64[0] = (double)(int)v1.m128d_f64[0];\n *(_QWORD *)&v1.m128d_f64[0] = COERCE_UNSIGNED_INT64(\n v2.m128d_f64[0]\n - COERCE_DOUBLE(*(_OWORD *)&_mm_cmpgt_sd(v2, v1) & 0x3FF0000000000000LL)) | *(_QWORD *)&v1.m128d_f64[0] & 0x8000000000000000LL;\n }\n return (unsigned int)((int)v1.m128d_f64[0] + 1);\n}", + "ida_strip_asm": "sub_1210:\npxor xmm5, xmm5\nsub rsp, 18h\ncvtsi2sd xmm5, edi\nmovapd xmm0, xmm5\nmovsd [rsp+18h+var_18], xmm5\ndivsd xmm0, cs:qword_2058; x\ncall _log10\nmovsd xmm6, [rsp+18h+var_18]\nmulsd xmm6, cs:qword_2060\nmovsd [rsp+18h+var_10], xmm0\nmovapd xmm0, xmm6; x\ncall _log10\nmovsd xmm5, [rsp+18h+var_18]\nmulsd xmm5, [rsp+18h+var_10]\nmovapd xmm1, xmm0\nmovsd xmm2, cs:qword_2080\nmovsd xmm3, cs:qword_2070\nmulsd xmm1, cs:qword_2068\nmovapd xmm0, xmm5\naddsd xmm0, xmm1\nmovapd xmm1, xmm0\nandpd xmm1, xmm2\nucomisd xmm3, xmm1\njbe short loc_12BE\ncvttsd2si rax, xmm0\npxor xmm1, xmm1\nmovsd xmm4, cs:qword_2078\nandnpd xmm2, xmm0\ncvtsi2sd xmm1, rax\nmovapd xmm3, xmm1\ncmpnlesd xmm3, xmm0\nandpd xmm3, xmm4\nsubsd xmm1, xmm3\norpd xmm1, xmm2\nmovapd xmm0, xmm1\nloc_12BE:\ncvttsd2si eax, xmm0\nadd rsp, 18h\nadd eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(int a1)\n{\n __m128d v1; // xmm0\n __m128d v2; // xmm1\n double v4; // [rsp+8h] [rbp-10h]\n\n v4 = log10((double)a1 / 2.718281828459045);\n v1.m128d_f64[0] = (double)a1 * v4 + log10((double)a1 * 6.283185307179586) * 0.5;\n if ( fabs(v1.m128d_f64[0]) < 4.503599627370496e15 )\n {\n v2 = 0LL;\n v2.m128d_f64[0] = (double)(int)v1.m128d_f64[0];\n *(_QWORD *)&v1.m128d_f64[0] = COERCE_UNSIGNED_INT64(\n v2.m128d_f64[0]\n - COERCE_DOUBLE(*(_OWORD *)&_mm_cmpgt_sd(v2, v1) & 0x3FF0000000000000LL)) | *(_QWORD *)&v1.m128d_f64[0] & 0x8000000000000000LL;\n }\n return (unsigned int)((int)v1.m128d_f64[0] + 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(int a1) {\n __m128d v1;\n __m128d v2;\n double v4;\n v4 = log10((double)a1 / 2.718281828459045);\n v1.m128d_f64[0] =\n (double)a1 * v4 + log10((double)a1 * 6.283185307179586) * 0.5;\n if (fabs(v1.m128d_f64[0]) < 4.503599627370496e15) {\n v2 = 0LL;\n v2.m128d_f64[0] = (double)(int)v1.m128d_f64[0];\n *(uint64_t *)&v1.m128d_f64[0] =\n COERCE_UNSIGNED_INT64(\n v2.m128d_f64[0] -\n COERCE_DOUBLE(*(long double *)&_mm_cmpgt_sd(v2, v1) &\n 4607182418800017408LL)) |\n *(uint64_t *)&v1.m128d_f64[0] & 9223372036854775808LL;\n }\n return (unsigned int)((int)v1.m128d_f64[0] + 1);\n}", + "ida_pseudo_norm": "long long func0_part_0(int a1) {\n __m128d v1;\n __m128d v2;\n double v4;\n v4 = log10((double)a1 / 2.718281828459045);\n v1.m128d_f64[0] =\n (double)a1 * v4 + log10((double)a1 * 6.283185307179586) * 0.5;\n if (fabs(v1.m128d_f64[0]) < 4.503599627370496e15) {\n v2 = 0LL;\n v2.m128d_f64[0] = (double)(int)v1.m128d_f64[0];\n *(uint64_t *)&v1.m128d_f64[0] =\n COERCE_UNSIGNED_INT64(\n v2.m128d_f64[0] -\n COERCE_DOUBLE(*(long double *)&_mm_cmpgt_sd(v2, v1) &\n 4607182418800017408LL)) |\n *(uint64_t *)&v1.m128d_f64[0] & 9223372036854775808LL;\n }\n return (unsigned int)((int)v1.m128d_f64[0] + 1);\n}" + }, + { + "index": 845, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n < 0) {\n return 0;\n }\n if (n <= 1) {\n return 1;\n }\n double x = (n * log10((double)n / M_E) + log10(2 * M_PI * n) / 2.0);\n return (int)floor(x) + 1;\n}", + "test": "int main() {\n\n assert(func0(7) == 4);\n\n assert(func0(5) == 3);\n\n assert(func0(4) == 2);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nxor %eax,%eax\ntest %edi,%edi\njs 13b0 \nmov $0x1,%eax\ncmp $0x1,%edi\njle 13b0 \npxor %xmm5,%xmm5\nsub $0x18,%rsp\ncvtsi2sd %edi,%xmm5\nmovapd %xmm5,%xmm0\nmovsd %xmm5,(%rsp)\ndivsd 0xd6f(%rip),%xmm0\ncallq 1070 \nmovsd (%rsp),%xmm6\nmulsd 0xd65(%rip),%xmm6\nmovsd %xmm0,0x8(%rsp)\nmovapd %xmm6,%xmm0\ncallq 1070 \nmovsd (%rsp),%xmm5\nmulsd 0x8(%rsp),%xmm5\nmovapd %xmm0,%xmm1\nmovsd 0xd5f(%rip),%xmm2\nmovsd 0xd47(%rip),%xmm3\nmulsd 0xd37(%rip),%xmm1\nmovapd %xmm5,%xmm0\naddsd %xmm1,%xmm0\nmovapd %xmm0,%xmm1\nandpd %xmm2,%xmm1\nucomisd %xmm1,%xmm3\njbe 139a \ncvttsd2si %xmm0,%rax\npxor %xmm1,%xmm1\nmovsd 0xd20(%rip),%xmm4\nandnpd %xmm0,%xmm2\ncvtsi2sd %rax,%xmm1\nmovapd %xmm1,%xmm3\ncmpnlesd %xmm0,%xmm3\nmovapd %xmm2,%xmm0\nandpd %xmm4,%xmm3\nsubsd %xmm3,%xmm1\norpd %xmm1,%xmm0\ncvttsd2si %xmm0,%eax\nadd $0x18,%rsp\nadd $0x1,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0_part_0:\npxor xmm5, xmm5\nsub rsp, 18h\ncvtsi2sd xmm5, edi\nmovapd xmm0, xmm5\nmovsd [rsp+18h+var_18], xmm5\ndivsd xmm0, cs:qword_2058; x\ncall _log10\nmovsd xmm6, [rsp+18h+var_18]\nmulsd xmm6, cs:qword_2060\nmovsd [rsp+18h+var_10], xmm0\nmovapd xmm0, xmm6; x\ncall _log10\nmovsd xmm5, [rsp+18h+var_18]\nmulsd xmm5, [rsp+18h+var_10]\nmovapd xmm1, xmm0\nmovsd xmm2, cs:qword_2080\nmovsd xmm3, cs:qword_2070\nmulsd xmm1, cs:qword_2068\nmovapd xmm0, xmm5\naddsd xmm0, xmm1\nmovapd xmm1, xmm0\nandpd xmm1, xmm2\nucomisd xmm3, xmm1\njbe short loc_12BE\ncvttsd2si rax, xmm0\npxor xmm1, xmm1\nmovsd xmm4, cs:qword_2078\nandnpd xmm2, xmm0\ncvtsi2sd xmm1, rax\nmovapd xmm3, xmm1\ncmpnlesd xmm3, xmm0\nandpd xmm3, xmm4\nsubsd xmm1, xmm3\norpd xmm1, xmm2\nmovapd xmm0, xmm1\nloc_12BE:\ncvttsd2si eax, xmm0\nadd rsp, 18h\nadd eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0_part_0(int a1)\n{\n __m128d v1; // xmm0\n __m128d v2; // xmm1\n double v4; // [rsp+8h] [rbp-10h]\n\n v4 = log10((double)a1 / 2.718281828459045);\n v1.m128d_f64[0] = (double)a1 * v4 + log10((double)a1 * 6.283185307179586) * 0.5;\n if ( fabs(v1.m128d_f64[0]) < 4.503599627370496e15 )\n {\n v2 = 0LL;\n v2.m128d_f64[0] = (double)(int)v1.m128d_f64[0];\n *(_QWORD *)&v1.m128d_f64[0] = COERCE_UNSIGNED_INT64(\n v2.m128d_f64[0]\n - COERCE_DOUBLE(*(_OWORD *)&_mm_cmpgt_sd(v2, v1) & 0x3FF0000000000000LL)) | *(_QWORD *)&v1.m128d_f64[0] & 0x8000000000000000LL;\n }\n return (unsigned int)((int)v1.m128d_f64[0] + 1);\n}", + "ida_strip_asm": "sub_1210:\npxor xmm5, xmm5\nsub rsp, 18h\ncvtsi2sd xmm5, edi\nmovapd xmm0, xmm5\nmovsd [rsp+18h+var_18], xmm5\ndivsd xmm0, cs:qword_2058; x\ncall _log10\nmovsd xmm6, [rsp+18h+var_18]\nmulsd xmm6, cs:qword_2060\nmovsd [rsp+18h+var_10], xmm0\nmovapd xmm0, xmm6; x\ncall _log10\nmovsd xmm5, [rsp+18h+var_18]\nmulsd xmm5, [rsp+18h+var_10]\nmovapd xmm1, xmm0\nmovsd xmm2, cs:qword_2080\nmovsd xmm3, cs:qword_2070\nmulsd xmm1, cs:qword_2068\nmovapd xmm0, xmm5\naddsd xmm0, xmm1\nmovapd xmm1, xmm0\nandpd xmm1, xmm2\nucomisd xmm3, xmm1\njbe short loc_12BE\ncvttsd2si rax, xmm0\npxor xmm1, xmm1\nmovsd xmm4, cs:qword_2078\nandnpd xmm2, xmm0\ncvtsi2sd xmm1, rax\nmovapd xmm3, xmm1\ncmpnlesd xmm3, xmm0\nandpd xmm3, xmm4\nsubsd xmm1, xmm3\norpd xmm1, xmm2\nmovapd xmm0, xmm1\nloc_12BE:\ncvttsd2si eax, xmm0\nadd rsp, 18h\nadd eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(int a1)\n{\n __m128d v1; // xmm0\n __m128d v2; // xmm1\n double v4; // [rsp+8h] [rbp-10h]\n\n v4 = log10((double)a1 / 2.718281828459045);\n v1.m128d_f64[0] = (double)a1 * v4 + log10((double)a1 * 6.283185307179586) * 0.5;\n if ( fabs(v1.m128d_f64[0]) < 4.503599627370496e15 )\n {\n v2 = 0LL;\n v2.m128d_f64[0] = (double)(int)v1.m128d_f64[0];\n *(_QWORD *)&v1.m128d_f64[0] = COERCE_UNSIGNED_INT64(\n v2.m128d_f64[0]\n - COERCE_DOUBLE(*(_OWORD *)&_mm_cmpgt_sd(v2, v1) & 0x3FF0000000000000LL)) | *(_QWORD *)&v1.m128d_f64[0] & 0x8000000000000000LL;\n }\n return (unsigned int)((int)v1.m128d_f64[0] + 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(int a1) {\n __m128d v1;\n __m128d v2;\n double v4;\n v4 = log10((double)a1 / 2.718281828459045);\n v1.m128d_f64[0] =\n (double)a1 * v4 + log10((double)a1 * 6.283185307179586) * 0.5;\n if (fabs(v1.m128d_f64[0]) < 4.503599627370496e15) {\n v2 = 0LL;\n v2.m128d_f64[0] = (double)(int)v1.m128d_f64[0];\n *(uint64_t *)&v1.m128d_f64[0] =\n COERCE_UNSIGNED_INT64(\n v2.m128d_f64[0] -\n COERCE_DOUBLE(*(long double *)&_mm_cmpgt_sd(v2, v1) &\n 4607182418800017408LL)) |\n *(uint64_t *)&v1.m128d_f64[0] & 9223372036854775808LL;\n }\n return (unsigned int)((int)v1.m128d_f64[0] + 1);\n}", + "ida_pseudo_norm": "long long func0_part_0(int a1) {\n __m128d v1;\n __m128d v2;\n double v4;\n v4 = log10((double)a1 / 2.718281828459045);\n v1.m128d_f64[0] =\n (double)a1 * v4 + log10((double)a1 * 6.283185307179586) * 0.5;\n if (fabs(v1.m128d_f64[0]) < 4.503599627370496e15) {\n v2 = 0LL;\n v2.m128d_f64[0] = (double)(int)v1.m128d_f64[0];\n *(uint64_t *)&v1.m128d_f64[0] =\n COERCE_UNSIGNED_INT64(\n v2.m128d_f64[0] -\n COERCE_DOUBLE(*(long double *)&_mm_cmpgt_sd(v2, v1) &\n 4607182418800017408LL)) |\n *(uint64_t *)&v1.m128d_f64[0] & 9223372036854775808LL;\n }\n return (unsigned int)((int)v1.m128d_f64[0] + 1);\n}" + }, + { + "index": 846, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint compare(const void *a, const void *b) {\n\n return (*(int*)a - *(int*)b);\n\n}\n\n\n\n", + "func": "int func0(int arr[], int dep[], int n) {\n qsort(arr, n, sizeof(int), compare);\n qsort(dep, n, sizeof(int), compare);\n int plat_needed = 1, result = 1;\n int i = 1, j = 0;\n while (i < n && j < n) {\n if (arr[i] <= dep[j]) {\n plat_needed++;\n i++;\n if (plat_needed > result) {\n result = plat_needed;\n }\n } else {\n plat_needed--;\n j++;\n }\n }\n return result;\n}", + "test": "int main() {\n\n int arr1[] = {900, 940, 950, 1100, 1500, 1800};\n\n int dep1[] = {910, 1200, 1120, 1130, 1900, 2000};\n\n assert(func0(arr1, dep1, 6) == 3);\n\n \n\n int arr2[] = {100, 200, 300, 400};\n\n int dep2[] = {700, 800, 900, 1000};\n\n assert(func0(arr2, dep2, 4) == 4);\n\n \n\n int arr3[] = {5, 6, 7, 8};\n\n int dep3[] = {4, 3, 2, 1};\n\n assert(func0(arr3, dep3, 4) == 1);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %edx,-0x24(%rbp)\nmov -0x24(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x18(%rbp),%rax\nlea -0x4a(%rip),%rcx\nmov $0x4,%edx\nmov %rax,%rdi\ncallq 1070 \nmov -0x24(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x20(%rbp),%rax\nlea -0x68(%rip),%rcx\nmov $0x4,%edx\nmov %rax,%rdi\ncallq 1070 \nmovl $0x1,-0x10(%rbp)\nmovl $0x1,-0xc(%rbp)\nmovl $0x1,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 126c \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x20(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njg 1264 \naddl $0x1,-0x10(%rbp)\naddl $0x1,-0x8(%rbp)\nmov -0x10(%rbp),%eax\ncmp -0xc(%rbp),%eax\njle 126c \nmov -0x10(%rbp),%eax\nmov %eax,-0xc(%rbp)\njmp 126c \nsubl $0x1,-0x10(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x24(%rbp),%eax\njge 127c \nmov -0x4(%rbp),%eax\ncmp -0x24(%rbp),%eax\njl 121c \nmov -0xc(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+base], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov eax, [rbp+var_24]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compare\nmov rcx, rdx; compar\nmov edx, 4; size\nmov rdi, rax; base\ncall _qsort\nmov eax, [rbp+var_24]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+var_20]\nlea rdx, compare\nmov rcx, rdx; compar\nmov edx, 4; size\nmov rdi, rax; base\ncall _qsort\nmov [rbp+var_10], 1\nmov [rbp+var_C], 1\nmov [rbp+var_8], 1\nmov [rbp+var_4], 0\njmp short loc_1272\nloc_1222:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njg short loc_126A\nadd [rbp+var_10], 1\nadd [rbp+var_8], 1\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_C]\njle short loc_1272\nmov eax, [rbp+var_10]\nmov [rbp+var_C], eax\njmp short loc_1272\nloc_126A:\nsub [rbp+var_10], 1\nadd [rbp+var_4], 1\nloc_1272:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_24]\njge short loc_1282\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_24]\njl short loc_1222\nloc_1282:\nmov eax, [rbp+var_C]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(void *a1, void *a2, int a3)\n{\n int v5; // [rsp+20h] [rbp-10h]\n int v6; // [rsp+24h] [rbp-Ch]\n int v7; // [rsp+28h] [rbp-8h]\n int v8; // [rsp+2Ch] [rbp-4h]\n\n qsort(a1, a3, 4uLL, compare);\n qsort(a2, a3, 4uLL, compare);\n v5 = 1;\n v6 = 1;\n v7 = 1;\n v8 = 0;\n while ( v7 < a3 && v8 < a3 )\n {\n if ( *((_DWORD *)a1 + v7) > *((_DWORD *)a2 + v8) )\n {\n --v5;\n ++v8;\n }\n else\n {\n ++v5;\n ++v7;\n if ( v5 > v6 )\n v6 = v5;\n }\n }\n return (unsigned int)v6;\n}", + "ida_strip_asm": "sub_11AB:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+base], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov eax, [rbp+var_24]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 4; size\nmov rdi, rax; base\ncall _qsort\nmov eax, [rbp+var_24]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+var_20]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 4; size\nmov rdi, rax; base\ncall _qsort\nmov [rbp+var_10], 1\nmov [rbp+var_C], 1\nmov [rbp+var_8], 1\nmov [rbp+var_4], 0\njmp short loc_1272\nloc_1222:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+base]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njg short loc_126A\nadd [rbp+var_10], 1\nadd [rbp+var_8], 1\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_C]\njle short loc_1272\nmov eax, [rbp+var_10]\nmov [rbp+var_C], eax\njmp short loc_1272\nloc_126A:\nsub [rbp+var_10], 1\nadd [rbp+var_4], 1\nloc_1272:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_24]\njge short loc_1282\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_24]\njl short loc_1222\nloc_1282:\nmov eax, [rbp+var_C]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11AB(void *a1, void *a2, int a3)\n{\n int v5; // [rsp+20h] [rbp-10h]\n int v6; // [rsp+24h] [rbp-Ch]\n int v7; // [rsp+28h] [rbp-8h]\n int v8; // [rsp+2Ch] [rbp-4h]\n\n qsort(a1, a3, 4uLL, compar);\n qsort(a2, a3, 4uLL, compar);\n v5 = 1;\n v6 = 1;\n v7 = 1;\n v8 = 0;\n while ( v7 < a3 && v8 < a3 )\n {\n if ( *((_DWORD *)a1 + v7) > *((_DWORD *)a2 + v8) )\n {\n --v5;\n ++v8;\n }\n else\n {\n ++v5;\n ++v7;\n if ( v5 > v6 )\n v6 = v5;\n }\n }\n return (unsigned int)v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11AB(void *a1, void *a2, int a3) {\n int v5;\n int v6;\n int v7;\n int v8;\n qsort(a1, a3, 4uLL, compar);\n qsort(a2, a3, 4uLL, compar);\n v5 = 1;\n v6 = 1;\n v7 = 1;\n v8 = 0;\n while (v7 < a3 && v8 < a3) {\n if (*((uint32_t *)a1 + v7) > *((uint32_t *)a2 + v8)) {\n --v5;\n ++v8;\n } else {\n ++v5;\n ++v7;\n if (v5 > v6) v6 = v5;\n }\n }\n return (unsigned int)v6;\n}", + "ida_pseudo_norm": "long long func0(void *a1, void *a2, int a3) {\n int v5;\n int v6;\n int v7;\n int v8;\n qsort(a1, a3, 4uLL, compare);\n qsort(a2, a3, 4uLL, compare);\n v5 = 1;\n v6 = 1;\n v7 = 1;\n v8 = 0;\n while (v7 < a3 && v8 < a3) {\n if (*((uint32_t *)a1 + v7) > *((uint32_t *)a2 + v8)) {\n --v5;\n ++v8;\n } else {\n ++v5;\n ++v7;\n if (v5 > v6) v6 = v5;\n }\n }\n return (unsigned int)v6;\n}" + }, + { + "index": 846, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint compare(const void *a, const void *b) {\n\n return (*(int*)a - *(int*)b);\n\n}\n\n\n\n", + "func": "int func0(int arr[], int dep[], int n) {\n qsort(arr, n, sizeof(int), compare);\n qsort(dep, n, sizeof(int), compare);\n int plat_needed = 1, result = 1;\n int i = 1, j = 0;\n while (i < n && j < n) {\n if (arr[i] <= dep[j]) {\n plat_needed++;\n i++;\n if (plat_needed > result) {\n result = plat_needed;\n }\n } else {\n plat_needed--;\n j++;\n }\n }\n return result;\n}", + "test": "int main() {\n\n int arr1[] = {900, 940, 950, 1100, 1500, 1800};\n\n int dep1[] = {910, 1200, 1120, 1130, 1900, 2000};\n\n assert(func0(arr1, dep1, 6) == 3);\n\n \n\n int arr2[] = {100, 200, 300, 400};\n\n int dep2[] = {700, 800, 900, 1000};\n\n assert(func0(arr2, dep2, 4) == 4);\n\n \n\n int arr3[] = {5, 6, 7, 8};\n\n int dep3[] = {4, 3, 2, 1};\n\n assert(func0(arr3, dep3, 4) == 1);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbp\nmov %rsi,%r12\nmov %edx,%ebx\nmovslq %edx,%r13\nlea -0x29(%rip),%rcx\nmov $0x4,%edx\nmov %r13,%rsi\ncallq 1070 \nlea -0x3d(%rip),%rcx\nmov $0x4,%edx\nmov %r13,%rsi\nmov %r12,%rdi\ncallq 1070 \ncmp $0x1,%ebx\njle 1222 \nmov $0x0,%edx\nmov $0x1,%eax\nmov $0x1,%r8d\nmov $0x1,%esi\njmp 1203 \nsub $0x1,%esi\nadd $0x1,%edx\ncmp %eax,%edx\nmov %eax,%ecx\ncmovge %edx,%ecx\ncmp %ecx,%ebx\njle 1228 \nmovslq %eax,%rcx\nmovslq %edx,%rdi\nmov (%r12,%rdi,4),%edi\ncmp %edi,0x0(%rbp,%rcx,4)\njg 11f2 \nadd $0x1,%esi\nadd $0x1,%eax\ncmp %esi,%r8d\ncmovl %esi,%r8d\njmp 11f8 \nmov $0x1,%r8d\nmov %r8d,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbp, rdi\nmov r12, rsi\nmov ebx, edx\nmovsxd r13, edx\nlea r14, compare\nmov rcx, r14; compar\nmov edx, 4; size\nmov rsi, r13; nmemb\ncall _qsort\nmov rcx, r14; compar\nmov edx, 4; size\nmov rsi, r13; nmemb\nmov rdi, r12; base\ncall _qsort\ncmp ebx, 1\njle short loc_121F\nmov edx, 0\nmov eax, 1\nmov r8d, 1\nmov esi, 1\njmp short loc_1200\nloc_11EF:\nsub esi, 1\nadd edx, 1\nloc_11F5:\ncmp eax, edx\nmov ecx, edx\ncmovge ecx, eax\ncmp ebx, ecx\njle short loc_1225\nloc_1200:\nmovsxd rcx, eax\nmovsxd rdi, edx\nmov edi, [r12+rdi*4]\ncmp [rbp+rcx*4+0], edi\njg short loc_11EF\nadd esi, 1\nadd eax, 1\ncmp r8d, esi\ncmovl r8d, esi\njmp short loc_11F5\nloc_121F:\nmov r8d, 1\nloc_1225:\nmov eax, r8d\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "__int64 __fastcall func0(void *a1, void *a2, int a3)\n{\n size_t v5; // r13\n int v6; // edx\n int v7; // eax\n int v8; // r8d\n int v9; // esi\n int v10; // ecx\n\n v5 = a3;\n qsort(a1, a3, 4uLL, compare);\n qsort(a2, v5, 4uLL, compare);\n if ( a3 <= 1 )\n {\n return 1;\n }\n else\n {\n v6 = 0;\n v7 = 1;\n v8 = 1;\n v9 = 1;\n do\n {\n if ( *((_DWORD *)a1 + v7) > *((_DWORD *)a2 + v6) )\n {\n --v9;\n ++v6;\n }\n else\n {\n ++v9;\n ++v7;\n if ( v8 < v9 )\n v8 = v9;\n }\n v10 = v6;\n if ( v7 >= v6 )\n v10 = v7;\n }\n while ( a3 > v10 );\n }\n return (unsigned int)v8;\n}", + "ida_strip_asm": "sub_1192:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbp, rdi\nmov r12, rsi\nmov ebx, edx\nmovsxd r13, edx\nlea r14, compar\nmov rcx, r14; compar\nmov edx, 4; size\nmov rsi, r13; nmemb\ncall _qsort\nmov rcx, r14; compar\nmov edx, 4; size\nmov rsi, r13; nmemb\nmov rdi, r12; base\ncall _qsort\ncmp ebx, 1\njle short loc_121F\nmov edx, 0\nmov eax, 1\nmov r8d, 1\nmov esi, 1\njmp short loc_1200\nloc_11EF:\nsub esi, 1\nadd edx, 1\nloc_11F5:\ncmp eax, edx\nmov ecx, edx\ncmovge ecx, eax\ncmp ebx, ecx\njle short loc_1225\nloc_1200:\nmovsxd rcx, eax\nmovsxd rdi, edx\nmov edi, [r12+rdi*4]\ncmp [rbp+rcx*4+0], edi\njg short loc_11EF\nadd esi, 1\nadd eax, 1\ncmp r8d, esi\ncmovl r8d, esi\njmp short loc_11F5\nloc_121F:\nmov r8d, 1\nloc_1225:\nmov eax, r8d\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1192(void *a1, void *a2, int a3)\n{\n size_t v5; // r13\n int v6; // edx\n int v7; // eax\n int v8; // r8d\n int v9; // esi\n int v10; // ecx\n\n v5 = a3;\n qsort(a1, a3, 4uLL, compar);\n qsort(a2, v5, 4uLL, compar);\n if ( a3 <= 1 )\n {\n return 1;\n }\n else\n {\n v6 = 0;\n v7 = 1;\n v8 = 1;\n v9 = 1;\n do\n {\n if ( *((_DWORD *)a1 + v7) > *((_DWORD *)a2 + v6) )\n {\n --v9;\n ++v6;\n }\n else\n {\n ++v9;\n ++v7;\n if ( v8 < v9 )\n v8 = v9;\n }\n v10 = v6;\n if ( v7 >= v6 )\n v10 = v7;\n }\n while ( a3 > v10 );\n }\n return (unsigned int)v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1192(void *a1, void *a2, int a3) {\n unsigned int v5;\n int v6;\n int v7;\n int v8;\n int v9;\n int v10;\n v5 = a3;\n qsort(a1, a3, 4uLL, compar);\n qsort(a2, v5, 4uLL, compar);\n if (a3 <= 1) {\n return 1;\n } else {\n v6 = 0;\n v7 = 1;\n v8 = 1;\n v9 = 1;\n do {\n if (*((uint32_t *)a1 + v7) > *((uint32_t *)a2 + v6)) {\n --v9;\n ++v6;\n } else {\n ++v9;\n ++v7;\n if (v8 < v9) v8 = v9;\n }\n v10 = v6;\n if (v7 >= v6) v10 = v7;\n } while (a3 > v10);\n }\n return (unsigned int)v8;\n}", + "ida_pseudo_norm": "long long func0(void *a1, void *a2, int a3) {\n unsigned int v5;\n int v6;\n int v7;\n int v8;\n int v9;\n int v10;\n v5 = a3;\n qsort(a1, a3, 4uLL, compare);\n qsort(a2, v5, 4uLL, compare);\n if (a3 <= 1) {\n return 1;\n } else {\n v6 = 0;\n v7 = 1;\n v8 = 1;\n v9 = 1;\n do {\n if (*((uint32_t *)a1 + v7) > *((uint32_t *)a2 + v6)) {\n --v9;\n ++v6;\n } else {\n ++v9;\n ++v7;\n if (v8 < v9) v8 = v9;\n }\n v10 = v6;\n if (v7 >= v6) v10 = v7;\n } while (a3 > v10);\n }\n return (unsigned int)v8;\n}" + }, + { + "index": 846, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint compare(const void *a, const void *b) {\n\n return (*(int*)a - *(int*)b);\n\n}\n\n\n\n", + "func": "int func0(int arr[], int dep[], int n) {\n qsort(arr, n, sizeof(int), compare);\n qsort(dep, n, sizeof(int), compare);\n int plat_needed = 1, result = 1;\n int i = 1, j = 0;\n while (i < n && j < n) {\n if (arr[i] <= dep[j]) {\n plat_needed++;\n i++;\n if (plat_needed > result) {\n result = plat_needed;\n }\n } else {\n plat_needed--;\n j++;\n }\n }\n return result;\n}", + "test": "int main() {\n\n int arr1[] = {900, 940, 950, 1100, 1500, 1800};\n\n int dep1[] = {910, 1200, 1120, 1130, 1900, 2000};\n\n assert(func0(arr1, dep1, 6) == 3);\n\n \n\n int arr2[] = {100, 200, 300, 400};\n\n int dep2[] = {700, 800, 900, 1000};\n\n assert(func0(arr2, dep2, 4) == 4);\n\n \n\n int arr3[] = {5, 6, 7, 8};\n\n int dep3[] = {4, 3, 2, 1};\n\n assert(func0(arr3, dep3, 4) == 1);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmovslq %edx,%r13\nlea -0x20(%rip),%rcx\nmov $0x4,%edx\npush %r12\nmov %rsi,%r12\nmov %r13,%rsi\npush %rbp\nmov %rdi,%rbp\npush %rbx\nsub $0x8,%rsp\ncallq 1070 \nmov $0x4,%edx\nmov %r13,%rsi\nmov %r12,%rdi\nlea -0x4d(%rip),%rcx\ncallq 1070 \ncmp $0x1,%r13d\njle 1410 \nmov %r13,%rbx\nxor %edx,%edx\nmov $0x1,%eax\nmov $0x1,%r8d\nmov $0x1,%esi\njmp 13d8 \nadd $0x1,%esi\nadd $0x1,%eax\ncmp %esi,%r8d\nmov %eax,%ecx\ncmovl %esi,%r8d\ncmp %eax,%edx\ncmovge %edx,%ecx\ncmp %ecx,%ebx\njle 13f9 \nmovslq %edx,%rdi\nmovslq %eax,%rcx\nmov (%r12,%rdi,4),%edi\ncmp %edi,0x0(%rbp,%rcx,4)\njle 13c0 \nadd $0x1,%edx\nsub $0x1,%esi\nmov %eax,%ecx\ncmp %eax,%edx\ncmovge %edx,%ecx\ncmp %ecx,%ebx\njg 13d8 \nadd $0x8,%rsp\nmov %r8d,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopw 0x0(%rax,%rax,1)\nadd $0x8,%rsp\nmov $0x1,%r8d\npop %rbx\nmov %r8d,%eax\npop %rbp\npop %r12\npop %r13\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r14\nlea r14, compare\npush r13\nmovsxd r13, edx\nmov rcx, r14; compar\nmov edx, 4; size\npush r12\nmov r12, rsi\nmov rsi, r13; nmemb\npush rbp\nmov rbp, rdi\npush rbx\ncall _qsort\nmov rcx, r14; compar\nmov edx, 4; size\nmov rsi, r13; nmemb\nmov rdi, r12; base\ncall _qsort\ncmp r13d, 1\njle short loc_1398\nmov rbx, r13\nxor edx, edx\nmov eax, 1\nmov r8d, 1\nmov esi, 1\njmp short loc_1368\nloc_1350:\nadd esi, 1\nadd eax, 1\nmov ecx, edx\ncmp r8d, esi\ncmovl r8d, esi\ncmp eax, edx\ncmovge ecx, eax\ncmp ebx, ecx\njle short loc_1389\nloc_1368:\nmovsxd rdi, edx\nmovsxd rcx, eax\nmov edi, [r12+rdi*4]\ncmp [rbp+rcx*4+0], edi\njle short loc_1350\nadd edx, 1\nsub esi, 1\nmov ecx, edx\ncmp eax, edx\ncmovge ecx, eax\ncmp ebx, ecx\njg short loc_1368\nloc_1389:\npop rbx\nmov eax, r8d\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1398:\nmov r8d, 1\npop rbx\npop rbp\nmov eax, r8d\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "__int64 __fastcall func0(void *a1, void *a2, int a3)\n{\n size_t v3; // r13\n int v5; // edx\n int v6; // eax\n unsigned int v7; // r8d\n int v8; // esi\n int v9; // ecx\n int v10; // ecx\n\n v3 = a3;\n qsort(a1, a3, 4uLL, compare);\n qsort(a2, v3, 4uLL, compare);\n if ( (int)v3 <= 1 )\n return 1LL;\n v5 = 0;\n v6 = 1;\n v7 = 1;\n v8 = 1;\n do\n {\n while ( *((_DWORD *)a1 + v6) > *((_DWORD *)a2 + v5) )\n {\n ++v5;\n --v8;\n v10 = v5;\n if ( v6 >= v5 )\n v10 = v6;\n if ( (int)v3 <= v10 )\n return v7;\n }\n ++v8;\n ++v6;\n v9 = v5;\n if ( (int)v7 < v8 )\n v7 = v8;\n if ( v6 >= v5 )\n v9 = v6;\n }\n while ( (int)v3 > v9 );\n return v7;\n}", + "ida_strip_asm": "sub_12F0:\nendbr64\npush r14\nlea r14, compar\npush r13\nmovsxd r13, edx\nmov rcx, r14; compar\nmov edx, 4; size\npush r12\nmov r12, rsi\nmov rsi, r13; nmemb\npush rbp\nmov rbp, rdi\npush rbx\ncall _qsort\nmov rcx, r14; compar\nmov edx, 4; size\nmov rsi, r13; nmemb\nmov rdi, r12; base\ncall _qsort\ncmp r13d, 1\njle short loc_1398\nmov rbx, r13\nxor edx, edx\nmov eax, 1\nmov r8d, 1\nmov esi, 1\njmp short loc_1368\nloc_1350:\nadd esi, 1\nadd eax, 1\nmov ecx, edx\ncmp r8d, esi\ncmovl r8d, esi\ncmp eax, edx\ncmovge ecx, eax\ncmp ebx, ecx\njle short loc_1389\nloc_1368:\nmovsxd rdi, edx\nmovsxd rcx, eax\nmov edi, [r12+rdi*4]\ncmp [rbp+rcx*4+0], edi\njle short loc_1350\nadd edx, 1\nsub esi, 1\nmov ecx, edx\ncmp eax, edx\ncmovge ecx, eax\ncmp ebx, ecx\njg short loc_1368\nloc_1389:\npop rbx\nmov eax, r8d\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1398:\nmov r8d, 1\npop rbx\npop rbp\nmov eax, r8d\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12F0(void *a1, void *a2, int a3)\n{\n size_t v3; // r13\n int v5; // edx\n int v6; // eax\n unsigned int v7; // r8d\n int v8; // esi\n int v9; // ecx\n int v10; // ecx\n\n v3 = a3;\n qsort(a1, a3, 4uLL, compar);\n qsort(a2, v3, 4uLL, compar);\n if ( (int)v3 <= 1 )\n return 1LL;\n v5 = 0;\n v6 = 1;\n v7 = 1;\n v8 = 1;\n do\n {\n while ( *((_DWORD *)a1 + v6) > *((_DWORD *)a2 + v5) )\n {\n ++v5;\n --v8;\n v10 = v5;\n if ( v6 >= v5 )\n v10 = v6;\n if ( (int)v3 <= v10 )\n return v7;\n }\n ++v8;\n ++v6;\n v9 = v5;\n if ( (int)v7 < v8 )\n v7 = v8;\n if ( v6 >= v5 )\n v9 = v6;\n }\n while ( (int)v3 > v9 );\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12F0(void *a1, void *a2, int a3) {\n unsigned int v3;\n int v5;\n int v6;\n unsigned int v7;\n int v8;\n int v9;\n int v10;\n v3 = a3;\n qsort(a1, a3, 4uLL, compar);\n qsort(a2, v3, 4uLL, compar);\n if ((int)v3 <= 1) return 1LL;\n v5 = 0;\n v6 = 1;\n v7 = 1;\n v8 = 1;\n do {\n while (*((uint32_t *)a1 + v6) > *((uint32_t *)a2 + v5)) {\n ++v5;\n --v8;\n v10 = v5;\n if (v6 >= v5) v10 = v6;\n if ((int)v3 <= v10) return v7;\n }\n ++v8;\n ++v6;\n v9 = v5;\n if ((int)v7 < v8) v7 = v8;\n if (v6 >= v5) v9 = v6;\n } while ((int)v3 > v9);\n return v7;\n}", + "ida_pseudo_norm": "long long func0(void *a1, void *a2, int a3) {\n unsigned int v3;\n int v5;\n int v6;\n unsigned int v7;\n int v8;\n int v9;\n int v10;\n v3 = a3;\n qsort(a1, a3, 4uLL, compare);\n qsort(a2, v3, 4uLL, compare);\n if ((int)v3 <= 1) return 1LL;\n v5 = 0;\n v6 = 1;\n v7 = 1;\n v8 = 1;\n do {\n while (*((uint32_t *)a1 + v6) > *((uint32_t *)a2 + v5)) {\n ++v5;\n --v8;\n v10 = v5;\n if (v6 >= v5) v10 = v6;\n if ((int)v3 <= v10) return v7;\n }\n ++v8;\n ++v6;\n v9 = v5;\n if ((int)v7 < v8) v7 = v8;\n if (v6 >= v5) v9 = v6;\n } while ((int)v3 > v9);\n return v7;\n}" + }, + { + "index": 846, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\nint compare(const void *a, const void *b) {\n\n return (*(int*)a - *(int*)b);\n\n}\n\n\n\n", + "func": "int func0(int arr[], int dep[], int n) {\n qsort(arr, n, sizeof(int), compare);\n qsort(dep, n, sizeof(int), compare);\n int plat_needed = 1, result = 1;\n int i = 1, j = 0;\n while (i < n && j < n) {\n if (arr[i] <= dep[j]) {\n plat_needed++;\n i++;\n if (plat_needed > result) {\n result = plat_needed;\n }\n } else {\n plat_needed--;\n j++;\n }\n }\n return result;\n}", + "test": "int main() {\n\n int arr1[] = {900, 940, 950, 1100, 1500, 1800};\n\n int dep1[] = {910, 1200, 1120, 1130, 1900, 2000};\n\n assert(func0(arr1, dep1, 6) == 3);\n\n \n\n int arr2[] = {100, 200, 300, 400};\n\n int dep2[] = {700, 800, 900, 1000};\n\n assert(func0(arr2, dep2, 4) == 4);\n\n \n\n int arr3[] = {5, 6, 7, 8};\n\n int dep3[] = {4, 3, 2, 1};\n\n assert(func0(arr3, dep3, 4) == 1);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmovslq %edx,%r13\nlea -0x20(%rip),%rcx\nmov $0x4,%edx\npush %r12\nmov %rsi,%r12\nmov %r13,%rsi\npush %rbp\nmov %rdi,%rbp\npush %rbx\nsub $0x8,%rsp\ncallq 1070 \nmov $0x4,%edx\nmov %r13,%rsi\nmov %r12,%rdi\nlea -0x4d(%rip),%rcx\ncallq 1070 \nmov $0x1,%r8d\ncmp $0x1,%r13d\njle 13c0 \nmov %r13,%rbx\nxor %edx,%edx\nmov $0x1,%eax\nmov $0x1,%r8d\nmov $0x1,%ecx\nxor %edi,%edi\nmov $0x1,%esi\nnopw 0x0(%rax,%rax,1)\nmov 0x0(%rbp,%rsi,4),%r9d\ncmp %r9d,(%r12,%rdi,4)\njl 13a1 \nadd $0x1,%ecx\nadd $0x1,%eax\nmov %edx,%esi\ncmp %ecx,%r8d\ncmovl %ecx,%r8d\ncmp %edx,%eax\ncmovge %eax,%esi\ncmp %esi,%ebx\njle 13c0 \nmovslq %eax,%rsi\nmov 0x0(%rbp,%rsi,4),%r9d\ncmp %r9d,(%r12,%rdi,4)\njge 137b \nadd $0x1,%edx\nsub $0x1,%ecx\nmov %eax,%edi\ncmp %eax,%edx\ncmovge %edx,%edi\ncmp %edi,%ebx\njle 13c0 \nmovslq %edx,%rdi\njmp 1370 \nnopw 0x0(%rax,%rax,1)\nadd $0x8,%rsp\nmov %r8d,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r14\nlea r14, compare\npush r13\nmovsxd r13, edx\nmov rcx, r14; compar\nmov edx, 4; size\npush r12\nmov r12, rsi\nmov rsi, r13; nmemb\npush rbp\nmov rbp, rdi\npush rbx\ncall _qsort\nmov rcx, r14; compar\nmov edx, 4; size\nmov rsi, r13; nmemb\nmov rdi, r12; base\ncall _qsort\ncmp r13d, 1\njle short loc_13A0\nmov rbx, r13\nxor edx, edx\nmov eax, 1\nmov esi, 1\nmov ecx, 1\nxor r8d, r8d\nmov edi, 1\nnop dword ptr [rax+00000000h]\nloc_1358:\nmov r9d, [rbp+rdi*4+0]\ncmp [r12+r8*4], r9d\njl short loc_1387\nloc_1363:\nadd ecx, 1\nadd eax, 1\ncmp esi, ecx\nmov edi, eax\ncmovl esi, ecx\ncmp edx, eax\ncmovge edi, edx\ncmp ebx, edi\njle short loc_13A5\nmovsxd rdi, eax\nmov r9d, [rbp+rdi*4+0]\ncmp [r12+r8*4], r9d\njge short loc_1363\nloc_1387:\nadd edx, 1\nsub ecx, 1\nmov r8d, edx\ncmp eax, edx\ncmovge r8d, eax\ncmp ebx, r8d\njle short loc_13A5\nmovsxd r8, edx\njmp short loc_1358\nloc_13A0:\nmov esi, 1\nloc_13A5:\npop rbx\nmov eax, esi\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "__int64 __fastcall func0(void *a1, void *a2, int a3)\n{\n size_t v3; // r13\n int v6; // edx\n int v7; // eax\n unsigned int v8; // esi\n int v9; // ecx\n __int64 v10; // r8\n __int64 v11; // rdi\n int v12; // edi\n int v13; // r8d\n\n v3 = a3;\n qsort(a1, a3, 4uLL, compare);\n qsort(a2, v3, 4uLL, compare);\n if ( (int)v3 <= 1 )\n {\n return 1;\n }\n else\n {\n v6 = 0;\n v7 = 1;\n v8 = 1;\n v9 = 1;\n v10 = 0LL;\n v11 = 1LL;\n while ( *((_DWORD *)a2 + v10) < *((_DWORD *)a1 + v11) )\n {\nLABEL_10:\n ++v6;\n --v9;\n v13 = v6;\n if ( v7 >= v6 )\n v13 = v7;\n if ( (int)v3 <= v13 )\n return v8;\n v10 = v6;\n }\n while ( 1 )\n {\n ++v9;\n v12 = ++v7;\n if ( (int)v8 < v9 )\n v8 = v9;\n if ( v6 >= v7 )\n v12 = v6;\n if ( (int)v3 <= v12 )\n break;\n v11 = v7;\n if ( *((_DWORD *)a2 + v10) < *((_DWORD *)a1 + v7) )\n goto LABEL_10;\n }\n }\n return v8;\n}", + "ida_strip_asm": "sub_12F0:\nendbr64\npush r14\nlea r14, compar\npush r13\nmovsxd r13, edx\nmov rcx, r14; compar\nmov edx, 4; size\npush r12\nmov r12, rsi\nmov rsi, r13; nmemb\npush rbp\nmov rbp, rdi\npush rbx\ncall _qsort\nmov rcx, r14; compar\nmov edx, 4; size\nmov rsi, r13; nmemb\nmov rdi, r12; base\ncall _qsort\ncmp r13d, 1\njle short loc_13A0\nmov rbx, r13\nxor edx, edx\nmov eax, 1\nmov esi, 1\nmov ecx, 1\nxor r8d, r8d\nmov edi, 1\nnop dword ptr [rax+00000000h]\nloc_1358:\nmov r9d, [rbp+rdi*4+0]\ncmp [r12+r8*4], r9d\njl short loc_1387\nloc_1363:\nadd ecx, 1\nadd eax, 1\ncmp esi, ecx\nmov edi, eax\ncmovl esi, ecx\ncmp edx, eax\ncmovge edi, edx\ncmp ebx, edi\njle short loc_13A5\nmovsxd rdi, eax\nmov r9d, [rbp+rdi*4+0]\ncmp [r12+r8*4], r9d\njge short loc_1363\nloc_1387:\nadd edx, 1\nsub ecx, 1\nmov r8d, edx\ncmp eax, edx\ncmovge r8d, eax\ncmp ebx, r8d\njle short loc_13A5\nmovsxd r8, edx\njmp short loc_1358\nloc_13A0:\nmov esi, 1\nloc_13A5:\npop rbx\nmov eax, esi\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12F0(void *a1, void *a2, int a3)\n{\n size_t v3; // r13\n int v6; // edx\n int v7; // eax\n unsigned int v8; // esi\n int v9; // ecx\n __int64 v10; // r8\n __int64 v11; // rdi\n int v12; // edi\n int v13; // r8d\n\n v3 = a3;\n qsort(a1, a3, 4uLL, compar);\n qsort(a2, v3, 4uLL, compar);\n if ( (int)v3 <= 1 )\n {\n return 1;\n }\n else\n {\n v6 = 0;\n v7 = 1;\n v8 = 1;\n v9 = 1;\n v10 = 0LL;\n v11 = 1LL;\n while ( *((_DWORD *)a2 + v10) < *((_DWORD *)a1 + v11) )\n {\nLABEL_10:\n ++v6;\n --v9;\n v13 = v6;\n if ( v7 >= v6 )\n v13 = v7;\n if ( (int)v3 <= v13 )\n return v8;\n v10 = v6;\n }\n while ( 1 )\n {\n ++v9;\n v12 = ++v7;\n if ( (int)v8 < v9 )\n v8 = v9;\n if ( v6 >= v7 )\n v12 = v6;\n if ( (int)v3 <= v12 )\n break;\n v11 = v7;\n if ( *((_DWORD *)a2 + v10) < *((_DWORD *)a1 + v7) )\n goto LABEL_10;\n }\n }\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12F0(void *a1, void *a2, int a3) {\n unsigned int v3;\n int v6;\n int v7;\n unsigned int v8;\n int v9;\n long long v10;\n long long v11;\n int v12;\n int v13;\n v3 = a3;\n qsort(a1, a3, 4uLL, compar);\n qsort(a2, v3, 4uLL, compar);\n if ((int)v3 <= 1) {\n return 1;\n } else {\n v6 = 0;\n v7 = 1;\n v8 = 1;\n v9 = 1;\n v10 = 0LL;\n v11 = 1LL;\n while (*((uint32_t *)a2 + v10) < *((uint32_t *)a1 + v11)) {\n LABEL_10:\n ++v6;\n --v9;\n v13 = v6;\n if (v7 >= v6) v13 = v7;\n if ((int)v3 <= v13) return v8;\n v10 = v6;\n }\n while (1) {\n ++v9;\n v12 = ++v7;\n if ((int)v8 < v9) v8 = v9;\n if (v6 >= v7) v12 = v6;\n if ((int)v3 <= v12) break;\n v11 = v7;\n if (*((uint32_t *)a2 + v10) < *((uint32_t *)a1 + v7)) goto LABEL_10;\n }\n }\n return v8;\n}", + "ida_pseudo_norm": "long long func0(void *a1, void *a2, int a3) {\n unsigned int v3;\n int v6;\n int v7;\n unsigned int v8;\n int v9;\n long long v10;\n long long v11;\n int v12;\n int v13;\n v3 = a3;\n qsort(a1, a3, 4uLL, compare);\n qsort(a2, v3, 4uLL, compare);\n if ((int)v3 <= 1) {\n return 1;\n } else {\n v6 = 0;\n v7 = 1;\n v8 = 1;\n v9 = 1;\n v10 = 0LL;\n v11 = 1LL;\n while (*((uint32_t *)a2 + v10) < *((uint32_t *)a1 + v11)) {\n LABEL_10:\n ++v6;\n --v9;\n v13 = v6;\n if (v7 >= v6) v13 = v7;\n if ((int)v3 <= v13) return v8;\n v10 = v6;\n }\n while (1) {\n ++v9;\n v12 = ++v7;\n if ((int)v8 < v9) v8 = v9;\n if (v6 >= v7) v12 = v6;\n if ((int)v3 <= v12) break;\n v11 = v7;\n if (*((uint32_t *)a2 + v10) < *((uint32_t *)a1 + v7)) goto LABEL_10;\n }\n }\n return v8;\n}" + }, + { + "index": 847, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\nint compare_arrays(int* arr1, int* arr2, int len) {\n\n for (int i = 0; i < len; i++) {\n\n if (arr1[i] != arr2[i]) {\n\n return 0;\n\n }\n\n }\n\n return 1;\n\n}\n\n\n\n", + "func": "int* func0(int* xs, int length) {\n int* copy = malloc(length * sizeof(int));\n for (int i = 0; i < length; i++) {\n copy[i] = xs[i];\n }\n return copy;\n}", + "test": "int main() {\n\n int xs1[] = {1, 2, 3};\n\n int* result1 = func0(xs1, 3);\n\n assert(compare_arrays(result1, xs1, 3));\n\n\n\n int xs2[] = {4, 8, 2, 10, 15, 18};\n\n int* result2 = func0(xs2, 6);\n\n assert(compare_arrays(result2, xs2, 6));\n\n\n\n int xs3[] = {4, 5, 6};\n\n int* result3 = func0(xs3, 3);\n\n assert(compare_arrays(result3, xs3, 3));\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov -0x1c(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 1271 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0xc(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1240 \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp short loc_1271\nloc_1240:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_C], 1\nloc_1271:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_1240\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+14h] [rbp-Ch]\n _DWORD *v4; // [rsp+18h] [rbp-8h]\n\n v4 = malloc(4LL * a2);\n for ( i = 0; i < a2; ++i )\n v4[i] = *(_DWORD *)(4LL * i + a1);\n return v4;\n}", + "ida_strip_asm": "sub_120F:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp short loc_1271\nloc_1240:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_C], 1\nloc_1271:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_1240\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_120F(__int64 a1, int a2)\n{\n int i; // [rsp+14h] [rbp-Ch]\n _DWORD *v4; // [rsp+18h] [rbp-8h]\n\n v4 = malloc(4LL * a2);\n for ( i = 0; i < a2; ++i )\n v4[i] = *(_DWORD *)(4LL * i + a1);\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_120F(long long a1, int a2) {\n int i;\n uint32_t *v4;\n v4 = malloc(4LL * a2);\n for (i = 0; i < a2; ++i) v4[i] = *(uint32_t *)(4LL * i + a1);\n return v4;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2) {\n int i;\n uint32_t *v4;\n v4 = malloc(4LL * a2);\n for (i = 0; i < a2; ++i) v4[i] = *(uint32_t *)(4LL * i + a1);\n return v4;\n}" + }, + { + "index": 847, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\nint compare_arrays(int* arr1, int* arr2, int len) {\n\n for (int i = 0; i < len; i++) {\n\n if (arr1[i] != arr2[i]) {\n\n return 0;\n\n }\n\n }\n\n return 1;\n\n}\n\n\n\n", + "func": "int* func0(int* xs, int length) {\n int* copy = malloc(length * sizeof(int));\n for (int i = 0; i < length; i++) {\n copy[i] = xs[i];\n }\n return copy;\n}", + "test": "int main() {\n\n int xs1[] = {1, 2, 3};\n\n int* result1 = func0(xs1, 3);\n\n assert(compare_arrays(result1, xs1, 3));\n\n\n\n int xs2[] = {4, 8, 2, 10, 15, 18};\n\n int* result2 = func0(xs2, 6);\n\n assert(compare_arrays(result2, xs2, 6));\n\n\n\n int xs3[] = {4, 5, 6};\n\n int* result3 = func0(xs3, 3);\n\n assert(compare_arrays(result3, xs3, 3));\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbx\nmov %esi,%ebp\nmovslq %esi,%rdi\nshl $0x2,%rdi\ncallq 10b0 \ntest %ebp,%ebp\njle 121a \nlea -0x1(%rbp),%esi\nmov $0x0,%edx\nmov (%rbx,%rdx,4),%ecx\nmov %ecx,(%rax,%rdx,4)\nmov %rdx,%rcx\nadd $0x1,%rdx\ncmp %rsi,%rcx\njne 1208 \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbp, rdi\nmov r12d, esi\nmovsxd rbx, esi\nshl rbx, 2\nmov rdi, rbx; size\ncall _malloc\ntest r12d, r12d\njle short loc_1217\nmov edx, 0\nloc_1207:\nmov ecx, [rbp+rdx+0]\nmov [rax+rdx], ecx\nadd rdx, 4\ncmp rbx, rdx\njnz short loc_1207\nloc_1217:\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2)\n{\n char *result; // rax\n __int64 v3; // rdx\n\n result = (char *)malloc(4LL * a2);\n if ( a2 > 0 )\n {\n v3 = 0LL;\n do\n {\n *(_DWORD *)&result[v3] = *(_DWORD *)(a1 + v3);\n v3 += 4LL;\n }\n while ( 4LL * a2 != v3 );\n }\n return result;\n}", + "ida_strip_asm": "sub_11E0:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbp, rdi\nmov r12d, esi\nmovsxd rbx, esi\nshl rbx, 2\nmov rdi, rbx; size\ncall _malloc\ntest r12d, r12d\njle short loc_1217\nmov edx, 0\nloc_1207:\nmov ecx, [rbp+rdx+0]\nmov [rax+rdx], ecx\nadd rdx, 4\ncmp rbx, rdx\njnz short loc_1207\nloc_1217:\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11E0(__int64 a1, int a2)\n{\n char *result; // rax\n __int64 v3; // rdx\n\n result = (char *)malloc(4LL * a2);\n if ( a2 > 0 )\n {\n v3 = 0LL;\n do\n {\n *(_DWORD *)&result[v3] = *(_DWORD *)(a1 + v3);\n v3 += 4LL;\n }\n while ( 4LL * a2 != v3 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11E0(long long a1, int a2) {\n char *result;\n long long v3;\n result = (char *)malloc(4LL * a2);\n if (a2 > 0) {\n v3 = 0LL;\n do {\n *(uint32_t *)&result[v3] = *(uint32_t *)(a1 + v3);\n v3 += 4LL;\n } while (4LL * a2 != v3);\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2) {\n char *result;\n long long v3;\n result = (char *)malloc(4LL * a2);\n if (a2 > 0) {\n v3 = 0LL;\n do {\n *(uint32_t *)&result[v3] = *(uint32_t *)(a1 + v3);\n v3 += 4LL;\n } while (4LL * a2 != v3);\n }\n return result;\n}" + }, + { + "index": 847, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\nint compare_arrays(int* arr1, int* arr2, int len) {\n\n for (int i = 0; i < len; i++) {\n\n if (arr1[i] != arr2[i]) {\n\n return 0;\n\n }\n\n }\n\n return 1;\n\n}\n\n\n\n", + "func": "int* func0(int* xs, int length) {\n int* copy = malloc(length * sizeof(int));\n for (int i = 0; i < length; i++) {\n copy[i] = xs[i];\n }\n return copy;\n}", + "test": "int main() {\n\n int xs1[] = {1, 2, 3};\n\n int* result1 = func0(xs1, 3);\n\n assert(compare_arrays(result1, xs1, 3));\n\n\n\n int xs2[] = {4, 8, 2, 10, 15, 18};\n\n int* result2 = func0(xs2, 6);\n\n assert(compare_arrays(result2, xs2, 6));\n\n\n\n int xs3[] = {4, 5, 6};\n\n int* result3 = func0(xs3, 3);\n\n assert(compare_arrays(result3, xs3, 3));\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nmov %rdi,%rbx\nmovslq %esi,%rdi\nmov %rdi,%rbp\nshl $0x2,%rdi\nsub $0x8,%rsp\ncallq 10b0 \ntest %ebp,%ebp\njle 12fa \nlea -0x1(%rbp),%esi\nxor %edx,%edx\nnopl (%rax)\nmov (%rbx,%rdx,4),%ecx\nmov %ecx,(%rax,%rdx,4)\nmov %rdx,%rcx\nadd $0x1,%rdx\ncmp %rsi,%rcx\njne 12e8 \nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rdi\nmovsxd rdi, esi\npush rbx\nmov rbx, rdi\nshl rdi, 2; size\nsub rsp, 8\ncall _malloc\nmov rcx, rax\ntest ebx, ebx\njle short loc_13E7\nmov edx, ebx\nmov rsi, rbp; src\nmov rdi, rax; dest\nshl rdx, 2; n\ncall _memcpy\nmov rcx, rax\nloc_13E7:\nadd rsp, 8\nmov rax, rcx\npop rbx\npop rbp\nretn", + "ida_pseudo": "void *__fastcall func0(void *src, int a2)\n{\n void *v2; // rax\n void *v3; // rcx\n\n v2 = malloc(4LL * a2);\n v3 = v2;\n if ( a2 > 0 )\n return memcpy(v2, src, 4LL * (unsigned int)a2);\n return v3;\n}", + "ida_strip_asm": "sub_13B0:\nendbr64\npush rbp\nmov rbp, rdi\nmovsxd rdi, esi\npush rbx\nmov rbx, rdi\nshl rdi, 2; size\nsub rsp, 8\ncall _malloc\nmov rcx, rax\ntest ebx, ebx\njle short loc_13E7\nmov edx, ebx\nmov rsi, rbp; src\nmov rdi, rax; dest\nshl rdx, 2; n\ncall _memcpy\nmov rcx, rax\nloc_13E7:\nadd rsp, 8\nmov rax, rcx\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "void *__fastcall sub_13B0(void *src, int a2)\n{\n void *v2; // rax\n void *v3; // rcx\n\n v2 = malloc(4LL * a2);\n v3 = v2;\n if ( a2 > 0 )\n return memcpy(v2, src, 4LL * (unsigned int)a2);\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_13B0(void *src, int a2) {\n void *v2;\n void *v3;\n v2 = malloc(4LL * a2);\n v3 = v2;\n if (a2 > 0) return memcpy(v2, src, 4LL * (unsigned int)a2);\n return v3;\n}", + "ida_pseudo_norm": "void *func0(void *src, int a2) {\n void *v2;\n void *v3;\n v2 = malloc(4LL * a2);\n v3 = v2;\n if (a2 > 0) return memcpy(v2, src, 4LL * (unsigned int)a2);\n return v3;\n}" + }, + { + "index": 847, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\nint compare_arrays(int* arr1, int* arr2, int len) {\n\n for (int i = 0; i < len; i++) {\n\n if (arr1[i] != arr2[i]) {\n\n return 0;\n\n }\n\n }\n\n return 1;\n\n}\n\n\n\n", + "func": "int* func0(int* xs, int length) {\n int* copy = malloc(length * sizeof(int));\n for (int i = 0; i < length; i++) {\n copy[i] = xs[i];\n }\n return copy;\n}", + "test": "int main() {\n\n int xs1[] = {1, 2, 3};\n\n int* result1 = func0(xs1, 3);\n\n assert(compare_arrays(result1, xs1, 3));\n\n\n\n int xs2[] = {4, 8, 2, 10, 15, 18};\n\n int* result2 = func0(xs2, 6);\n\n assert(compare_arrays(result2, xs2, 6));\n\n\n\n int xs3[] = {4, 5, 6};\n\n int* result3 = func0(xs3, 3);\n\n assert(compare_arrays(result3, xs3, 3));\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rdi,%rbp\nmovslq %esi,%rdi\npush %rbx\nmov %rdi,%rbx\nshl $0x2,%rdi\nsub $0x8,%rsp\ncallq 10d0 \nmov %rax,%r8\ntest %ebx,%ebx\njle 130c \nlea -0x1(%rbx),%eax\nmov %r8,%rdi\nmov %rbp,%rsi\nlea 0x4(,%rax,4),%rdx\ncallq 10c0 \nmov %rax,%r8\nadd $0x8,%rsp\nmov %r8,%rax\npop %rbx\npop %rbp\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rdi\nmovsxd rdi, esi\npush rbx\nmov rbx, rdi\nshl rdi, 2; size\nsub rsp, 8\ncall _malloc\nmov rcx, rax\ntest ebx, ebx\njle short loc_12F7\nmov edx, ebx\nmov rsi, rbp; src\nmov rdi, rax; dest\nshl rdx, 2; n\ncall _memcpy\nmov rcx, rax\nloc_12F7:\nadd rsp, 8\nmov rax, rcx\npop rbx\npop rbp\nretn", + "ida_pseudo": "void *__fastcall func0(void *src, int a2)\n{\n void *v2; // rax\n void *v3; // rcx\n\n v2 = malloc(4LL * a2);\n v3 = v2;\n if ( a2 > 0 )\n return memcpy(v2, src, 4LL * (unsigned int)a2);\n return v3;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\npush rbp\nmov rbp, rdi\nmovsxd rdi, esi\npush rbx\nmov rbx, rdi\nshl rdi, 2; size\nsub rsp, 8\ncall _malloc\nmov rcx, rax\ntest ebx, ebx\njle short loc_12F7\nmov edx, ebx\nmov rsi, rbp; src\nmov rdi, rax; dest\nshl rdx, 2; n\ncall _memcpy\nmov rcx, rax\nloc_12F7:\nadd rsp, 8\nmov rax, rcx\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "void *__fastcall sub_12C0(void *src, int a2)\n{\n void *v2; // rax\n void *v3; // rcx\n\n v2 = malloc(4LL * a2);\n v3 = v2;\n if ( a2 > 0 )\n return memcpy(v2, src, 4LL * (unsigned int)a2);\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_12C0(void *src, int a2) {\n void *v2;\n void *v3;\n v2 = malloc(4LL * a2);\n v3 = v2;\n if (a2 > 0) return memcpy(v2, src, 4LL * (unsigned int)a2);\n return v3;\n}", + "ida_pseudo_norm": "void *func0(void *src, int a2) {\n void *v2;\n void *v3;\n v2 = malloc(4LL * a2);\n v3 = v2;\n if (a2 > 0) return memcpy(v2, src, 4LL * (unsigned int)a2);\n return v3;\n}" + }, + { + "index": 848, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "double func0(double base1, double base2, double height) {\n double area = 0.5 * (base1 + base2) * height;\n return area;\n}", + "test": "int main() {\n\n assert(func0(6, 9, 4) == 30);\n\n assert(func0(10, 20, 30) == 450);\n\n assert(func0(15, 25, 35) == 700);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmovsd %xmm0,-0x18(%rbp)\nmovsd %xmm1,-0x20(%rbp)\nmovsd %xmm2,-0x28(%rbp)\nmovsd -0x18(%rbp),%xmm0\nmovapd %xmm0,%xmm1\naddsd -0x20(%rbp),%xmm1\nmovsd 0xf1a(%rip),%xmm0\nmulsd %xmm1,%xmm0\nmovsd -0x28(%rbp),%xmm1\nmulsd %xmm1,%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmovsd -0x8(%rbp),%xmm0\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmovsd [rbp+var_18], xmm0\nmovsd [rbp+var_20], xmm1\nmovsd [rbp+var_28], xmm2\nmovsd xmm0, [rbp+var_18]\nmovapd xmm1, xmm0\naddsd xmm1, [rbp+var_20]\nmovsd xmm0, cs:qword_2078\nmulsd xmm0, xmm1\nmovsd xmm1, [rbp+var_28]\nmulsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "double __fastcall func0(double a1, double a2, double a3)\n{\n return 0.5 * (a1 + a2) * a3;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmovsd [rbp+var_18], xmm0\nmovsd [rbp+var_20], xmm1\nmovsd [rbp+var_28], xmm2\nmovsd xmm0, [rbp+var_18]\nmovapd xmm1, xmm0\naddsd xmm1, [rbp+var_20]\nmovsd xmm0, cs:qword_2078\nmulsd xmm0, xmm1\nmovsd xmm1, [rbp+var_28]\nmulsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm0, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "double __fastcall sub_1149(double a1, double a2, double a3)\n{\n return 0.5 * (a1 + a2) * a3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1149(double a1, double a2, double a3) {\n return 0.5 * (a1 + a2) * a3;\n}", + "ida_pseudo_norm": "double func0(double a1, double a2, double a3) { return 0.5 * (a1 + a2) * a3; }" + }, + { + "index": 849, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int N) {\n int SumOfPrimeDivisors[N + 1];\n for (int i = 0; i <= N; i++) {\n SumOfPrimeDivisors[i] = 0;\n }\n for (int i = 2; i <= N; i++) {\n if (SumOfPrimeDivisors[i] == 0) {\n for (int j = i; j <= N; j += i) {\n SumOfPrimeDivisors[j] += i;\n }\n }\n }\n return SumOfPrimeDivisors[N];\n}", + "test": "int main() {\n\n assert(func0(60) == 10);\n\n assert(func0(39) == 16);\n\n assert(func0(40) == 7);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x48,%rsp\nmov %edi,-0x44(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmov %rsp,%rax\nmov %rax,%rsi\nmov -0x44(%rbp),%eax\nadd $0x1,%eax\nmovslq %eax,%rdx\nsub $0x1,%rdx\nmov %rdx,-0x28(%rbp)\nmovslq %eax,%rdx\nmov %rdx,%r8\nmov $0x0,%r9d\nmovslq %eax,%rdx\nmov %rdx,%rcx\nmov $0x0,%ebx\ncltq\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%edi\nmov $0x0,%edx\ndiv %rdi\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rbx\nsub %rdx,%rbx\nmov %rbx,%rdx\ncmp %rdx,%rsp\nje 1207 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11f0 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 1231 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x20(%rbp)\nmovl $0x0,-0x2c(%rbp)\njmp 1262 \nmov -0x20(%rbp),%rax\nmov -0x2c(%rbp),%edx\nmovslq %edx,%rdx\nmovl $0x0,(%rax,%rdx,4)\naddl $0x1,-0x2c(%rbp)\nmov -0x2c(%rbp),%eax\ncmp -0x44(%rbp),%eax\njle 124d \nmovl $0x2,-0x30(%rbp)\njmp 12be \nmov -0x20(%rbp),%rax\nmov -0x30(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\ntest %eax,%eax\njne 12ba \nmov -0x30(%rbp),%eax\nmov %eax,-0x34(%rbp)\njmp 12b2 \nmov -0x20(%rbp),%rax\nmov -0x34(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%edx\nmov -0x30(%rbp),%eax\nlea (%rdx,%rax,1),%ecx\nmov -0x20(%rbp),%rax\nmov -0x34(%rbp),%edx\nmovslq %edx,%rdx\nmov %ecx,(%rax,%rdx,4)\nmov -0x30(%rbp),%eax\nadd %eax,-0x34(%rbp)\nmov -0x34(%rbp),%eax\ncmp -0x44(%rbp),%eax\njle 128c \naddl $0x1,-0x30(%rbp)\nmov -0x30(%rbp),%eax\ncmp -0x44(%rbp),%eax\njle 1273 \nmov -0x20(%rbp),%rax\nmov -0x44(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nmov %rsi,%rsp\nmov -0x18(%rbp),%rdi\nxor %fs:0x28,%rdi\nje 12ea \ncallq 1060 <__stack_chk_fail@plt>\nmov -0x8(%rbp),%rbx\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_34], edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov eax, [rbp+var_34]\nadd eax, 1\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11D5:\ncmp rsp, rdx\njz short loc_11EC\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_11D5\nloc_11EC:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1216\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1216:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov [rbp+var_24], 0\njmp short loc_1247\nloc_1232:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov dword ptr [rax+rdx*4], 0\nadd [rbp+var_24], 1\nloc_1247:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_34]\njle short loc_1232\nmov [rbp+var_20], 2\njmp short loc_12A3\nloc_1258:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ntest eax, eax\njnz short loc_129F\nmov eax, [rbp+var_20]\nmov [rbp+var_1C], eax\njmp short loc_1297\nloc_1271:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov edx, [rax+rdx*4]\nmov eax, [rbp+var_20]\nlea ecx, [rdx+rax]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nmov eax, [rbp+var_20]\nadd [rbp+var_1C], eax\nloc_1297:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_34]\njle short loc_1271\nloc_129F:\nadd [rbp+var_20], 1\nloc_12A3:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_34]\njle short loc_1258\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_34]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12CF\ncall ___stack_chk_fail\nlocret_12CF:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned __int64 v1; // rax\n void *v2; // rsp\n _BYTE v4[12]; // [rsp+8h] [rbp-40h] BYREF\n int v5; // [rsp+14h] [rbp-34h]\n int i; // [rsp+24h] [rbp-24h]\n int j; // [rsp+28h] [rbp-20h]\n int k; // [rsp+2Ch] [rbp-1Ch]\n __int64 v9; // [rsp+30h] [rbp-18h]\n _BYTE *v10; // [rsp+38h] [rbp-10h]\n unsigned __int64 v11; // [rsp+40h] [rbp-8h]\n\n v5 = a1;\n v11 = __readfsqword(0x28u);\n v9 = a1 + 1 - 1LL;\n v1 = 16 * ((4LL * (a1 + 1) + 15) / 0x10uLL);\n while ( v4 != &v4[-(v1 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v2 = alloca(v1 & 0xFFF);\n if ( (v1 & 0xFFF) != 0 )\n *(_QWORD *)&v4[(v1 & 0xFFF) - 8] = *(_QWORD *)&v4[(v1 & 0xFFF) - 8];\n v10 = v4;\n for ( i = 0; i <= v5; ++i )\n *(_DWORD *)&v10[4 * i] = 0;\n for ( j = 2; j <= v5; ++j )\n {\n if ( !*(_DWORD *)&v10[4 * j] )\n {\n for ( k = j; k <= v5; k += j )\n *(_DWORD *)&v10[4 * k] += j;\n }\n }\n return *(unsigned int *)&v10[4 * v5];\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_34], edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov eax, [rbp+var_34]\nadd eax, 1\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11D5:\ncmp rsp, rdx\njz short loc_11EC\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_11D5\nloc_11EC:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1216\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1216:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov [rbp+var_24], 0\njmp short loc_1247\nloc_1232:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov dword ptr [rax+rdx*4], 0\nadd [rbp+var_24], 1\nloc_1247:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_34]\njle short loc_1232\nmov [rbp+var_20], 2\njmp short loc_12A3\nloc_1258:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ntest eax, eax\njnz short loc_129F\nmov eax, [rbp+var_20]\nmov [rbp+var_1C], eax\njmp short loc_1297\nloc_1271:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov edx, [rax+rdx*4]\nmov eax, [rbp+var_20]\nlea ecx, [rdx+rax]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nmov eax, [rbp+var_20]\nadd [rbp+var_1C], eax\nloc_1297:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_34]\njle short loc_1271\nloc_129F:\nadd [rbp+var_20], 1\nloc_12A3:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_34]\njle short loc_1258\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_34]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12CF\ncall ___stack_chk_fail\nlocret_12CF:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n unsigned __int64 v1; // rax\n void *v2; // rsp\n _BYTE v4[12]; // [rsp+8h] [rbp-40h] BYREF\n int v5; // [rsp+14h] [rbp-34h]\n int i; // [rsp+24h] [rbp-24h]\n int j; // [rsp+28h] [rbp-20h]\n int k; // [rsp+2Ch] [rbp-1Ch]\n __int64 v9; // [rsp+30h] [rbp-18h]\n _BYTE *v10; // [rsp+38h] [rbp-10h]\n unsigned __int64 v11; // [rsp+40h] [rbp-8h]\n\n v5 = a1;\n v11 = __readfsqword(0x28u);\n v9 = a1 + 1 - 1LL;\n v1 = 16 * ((4LL * (a1 + 1) + 15) / 0x10uLL);\n while ( v4 != &v4[-(v1 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v2 = alloca(v1 & 0xFFF);\n if ( (v1 & 0xFFF) != 0 )\n *(_QWORD *)&v4[(v1 & 0xFFF) - 8] = *(_QWORD *)&v4[(v1 & 0xFFF) - 8];\n v10 = v4;\n for ( i = 0; i <= v5; ++i )\n *(_DWORD *)&v10[4 * i] = 0;\n for ( j = 2; j <= v5; ++j )\n {\n if ( !*(_DWORD *)&v10[4 * j] )\n {\n for ( k = j; k <= v5; k += j )\n *(_DWORD *)&v10[4 * k] += j;\n }\n }\n return *(unsigned int *)&v10[4 * v5];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n unsigned long long v1;\n void *v2;\n uint8_t v4[12];\n int v5;\n int i;\n int j;\n int k;\n long long v9;\n uint8_t *v10;\n unsigned long long v11;\n v5 = a1;\n v11 = __readfsqword(40u);\n v9 = a1 + 1 - 1LL;\n v1 = 16 * ((4LL * (a1 + 1) + 15) / 16uLL);\n while (v4 != &v4[-(v1 & 18446744073709547520LL)])\n ;\n v2 = alloca(v1 & 4095);\n if ((v1 & 4095) != 0)\n *(uint64_t *)&v4[(v1 & 4095) - 8] = *(uint64_t *)&v4[(v1 & 4095) - 8];\n v10 = v4;\n for (i = 0; i <= v5; ++i) *(uint32_t *)&v10[4 * i] = 0;\n for (j = 2; j <= v5; ++j) {\n if (!*(uint32_t *)&v10[4 * j]) {\n for (k = j; k <= v5; k += j) *(uint32_t *)&v10[4 * k] += j;\n }\n }\n return *(unsigned int *)&v10[4 * v5];\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned long long v1;\n void *v2;\n uint8_t v4[12];\n int v5;\n int i;\n int j;\n int k;\n long long v9;\n uint8_t *v10;\n unsigned long long v11;\n v5 = a1;\n v11 = __readfsqword(40u);\n v9 = a1 + 1 - 1LL;\n v1 = 16 * ((4LL * (a1 + 1) + 15) / 16uLL);\n while (v4 != &v4[-(v1 & 18446744073709547520LL)])\n ;\n v2 = alloca(v1 & 4095);\n if ((v1 & 4095) != 0)\n *(uint64_t *)&v4[(v1 & 4095) - 8] = *(uint64_t *)&v4[(v1 & 4095) - 8];\n v10 = v4;\n for (i = 0; i <= v5; ++i) *(uint32_t *)&v10[4 * i] = 0;\n for (j = 2; j <= v5; ++j) {\n if (!*(uint32_t *)&v10[4 * j]) {\n for (k = j; k <= v5; k += j) *(uint32_t *)&v10[4 * k] += j;\n }\n }\n return *(unsigned int *)&v10[4 * v5];\n}" + }, + { + "index": 849, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int N) {\n int SumOfPrimeDivisors[N + 1];\n for (int i = 0; i <= N; i++) {\n SumOfPrimeDivisors[i] = 0;\n }\n for (int i = 2; i <= N; i++) {\n if (SumOfPrimeDivisors[i] == 0) {\n for (int j = i; j <= N; j += i) {\n SumOfPrimeDivisors[j] += i;\n }\n }\n }\n return SumOfPrimeDivisors[N];\n}", + "test": "int main() {\n\n assert(func0(60) == 10);\n\n assert(func0(39) == 16);\n\n assert(func0(40) == 7);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0x1(%rdi),%eax\ncltq\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffffff0,%rdx\nand $0xfffffffffffff000,%rax\nmov %rsp,%rsi\nsub %rax,%rsi\nmov %rsi,%rax\ncmp %rax,%rsp\nje 11be \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11a7 \nmov %rdx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 11d4 \norq $0x0,-0x8(%rsp,%rax,1)\nmov %rsp,%r9\nmov %r9,%rcx\ntest %edi,%edi\njs 11f7 \nmov %r9,%rax\nmov %edi,%edx\nlea 0x4(%r9,%rdx,4),%rdx\nmovl $0x0,(%rax)\nadd $0x4,%rax\ncmp %rdx,%rax\njne 11e8 \ncmp $0x1,%edi\njle 122f \nlea -0x2(%rdi),%r8d\nadd $0x3,%r8\nmov $0x2,%edx\njmp 1214 \nadd $0x1,%rdx\ncmp %r8,%rdx\nje 122f \nmov %edx,%esi\ncmpl $0x0,(%rcx,%rdx,4)\njne 120b \ncmp %edx,%edi\njl 120b \nmov %rdx,%rax\nadd %esi,(%rcx,%rax,4)\nadd %rdx,%rax\ncmp %eax,%edi\njge 1223 \njmp 120b \nmovslq %edi,%rdi\nmov (%r9,%rdi,4),%eax\nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\njne 1247 \nleaveq\nretq\ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov esi, edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea eax, [rdi+1]\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11A6:\ncmp rsp, rdx\njz short loc_11BD\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11A6\nloc_11BD:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11D3\nor [rsp+rax+10h+var_18], 0\nloc_11D3:\nmov rcx, rsp\ntest esi, esi\njs short loc_1227\nmov rax, rcx\nlea edx, [rsi+1]\nlea rdx, [rcx+rdx*4]\nloc_11E4:\nmov dword ptr [rax], 0\nadd rax, 4\ncmp rax, rdx\njnz short loc_11E4\ncmp esi, 1\njle short loc_1227\nlea r8d, [rsi+1]\nmov edx, 2\njmp short loc_120C\nloc_1203:\nadd rdx, 1\ncmp rdx, r8\njz short loc_1227\nloc_120C:\ncmp dword ptr [rcx+rdx*4], 0\njnz short loc_1203\ncmp esi, edx\njl short loc_1203\nmov edi, edx\nmov rax, rdx\nloc_121B:\nadd [rcx+rax*4], edi\nadd rax, rdx\ncmp esi, eax\njge short loc_121B\njmp short loc_1203\nloc_1227:\nmovsxd rsi, esi\nmov eax, [rcx+rsi*4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_123E\nleave\nretn\nloc_123E:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n signed __int64 v1; // rax\n void *v2; // rsp\n _DWORD *v3; // rax\n __int64 v4; // rdx\n __int64 v5; // rax\n _DWORD v8[2]; // [rsp+8h] [rbp-10h] BYREF\n unsigned __int64 v9; // [rsp+10h] [rbp-8h]\n\n v9 = __readfsqword(0x28u);\n while ( v8 != (_DWORD *)((char *)v8 - ((4LL * (a1 + 1) + 15) & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v1 = (4 * ((_WORD)a1 + 1) + 15) & 0xFF0;\n v2 = alloca(v1);\n if ( ((4 * ((_WORD)a1 + 1) + 15) & 0xFF0) != 0 )\n *(_QWORD *)((char *)&v8[-2] + v1) = *(_QWORD *)((char *)&v8[-2] + v1);\n if ( a1 >= 0 )\n {\n v3 = v8;\n do\n *v3++ = 0;\n while ( v3 != &v8[a1 + 1] );\n if ( a1 > 1 )\n {\n v4 = 2LL;\n do\n {\n if ( !v8[v4] && a1 >= (int)v4 )\n {\n v5 = v4;\n do\n {\n v8[v5] += v4;\n v5 += v4;\n }\n while ( a1 >= (int)v5 );\n }\n ++v4;\n }\n while ( v4 != a1 + 1 );\n }\n }\n return (unsigned int)v8[a1];\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov esi, edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea eax, [rdi+1]\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11A6:\ncmp rsp, rdx\njz short loc_11BD\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11A6\nloc_11BD:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11D3\nor [rsp+rax+10h+var_18], 0\nloc_11D3:\nmov rcx, rsp\ntest esi, esi\njs short loc_1227\nmov rax, rcx\nlea edx, [rsi+1]\nlea rdx, [rcx+rdx*4]\nloc_11E4:\nmov dword ptr [rax], 0\nadd rax, 4\ncmp rax, rdx\njnz short loc_11E4\ncmp esi, 1\njle short loc_1227\nlea r8d, [rsi+1]\nmov edx, 2\njmp short loc_120C\nloc_1203:\nadd rdx, 1\ncmp rdx, r8\njz short loc_1227\nloc_120C:\ncmp dword ptr [rcx+rdx*4], 0\njnz short loc_1203\ncmp esi, edx\njl short loc_1203\nmov edi, edx\nmov rax, rdx\nloc_121B:\nadd [rcx+rax*4], edi\nadd rax, rdx\ncmp esi, eax\njge short loc_121B\njmp short loc_1203\nloc_1227:\nmovsxd rsi, esi\nmov eax, [rcx+rsi*4]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_123E\nleave\nretn\nloc_123E:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n signed __int64 v1; // rax\n void *v2; // rsp\n _DWORD *v3; // rax\n __int64 v4; // rdx\n __int64 v5; // rax\n _DWORD v8[2]; // [rsp+8h] [rbp-10h] BYREF\n unsigned __int64 v9; // [rsp+10h] [rbp-8h]\n\n v9 = __readfsqword(0x28u);\n while ( v8 != (_DWORD *)((char *)v8 - ((4LL * (a1 + 1) + 15) & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v1 = (4 * ((_WORD)a1 + 1) + 15) & 0xFF0;\n v2 = alloca(v1);\n if ( ((4 * ((_WORD)a1 + 1) + 15) & 0xFF0) != 0 )\n *(_QWORD *)((char *)&v8[-2] + v1) = *(_QWORD *)((char *)&v8[-2] + v1);\n if ( a1 >= 0 )\n {\n v3 = v8;\n do\n *v3++ = 0;\n while ( v3 != &v8[a1 + 1] );\n if ( a1 > 1 )\n {\n v4 = 2LL;\n do\n {\n if ( !v8[v4] && a1 >= (int)v4 )\n {\n v5 = v4;\n do\n {\n v8[v5] += v4;\n v5 += v4;\n }\n while ( a1 >= (int)v5 );\n }\n ++v4;\n }\n while ( v4 != a1 + 1 );\n }\n }\n return (unsigned int)v8[a1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n signed long long v1;\n void *v2;\n uint32_t *v3;\n long long v4;\n long long v5;\n uint32_t v8[2];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n while (v8 != (uint32_t *)((char *)v8 -\n ((4LL * (a1 + 1) + 15) & 18446744073709547520LL)))\n ;\n v1 = (4 * ((unsigned short)a1 + 1) + 15) & 4080;\n v2 = alloca(v1);\n if (((4 * ((unsigned short)a1 + 1) + 15) & 4080) != 0)\n *(uint64_t *)((char *)&v8[-2] + v1) = *(uint64_t *)((char *)&v8[-2] + v1);\n if (a1 >= 0) {\n v3 = v8;\n do\n *v3++ = 0;\n while (v3 != &v8[a1 + 1]);\n if (a1 > 1) {\n v4 = 2LL;\n do {\n if (!v8[v4] && a1 >= (int)v4) {\n v5 = v4;\n do {\n v8[v5] += v4;\n v5 += v4;\n } while (a1 >= (int)v5);\n }\n ++v4;\n } while (v4 != a1 + 1);\n }\n }\n return (unsigned int)v8[a1];\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n signed long long v1;\n void *v2;\n uint32_t *v3;\n long long v4;\n long long v5;\n uint32_t v8[2];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n while (v8 != (uint32_t *)((char *)v8 -\n ((4LL * (a1 + 1) + 15) & 18446744073709547520LL)))\n ;\n v1 = (4 * ((unsigned short)a1 + 1) + 15) & 4080;\n v2 = alloca(v1);\n if (((4 * ((unsigned short)a1 + 1) + 15) & 4080) != 0)\n *(uint64_t *)((char *)&v8[-2] + v1) = *(uint64_t *)((char *)&v8[-2] + v1);\n if (a1 >= 0) {\n v3 = v8;\n do\n *v3++ = 0;\n while (v3 != &v8[a1 + 1]);\n if (a1 > 1) {\n v4 = 2LL;\n do {\n if (!v8[v4] && a1 >= (int)v4) {\n v5 = v4;\n do {\n v8[v5] += v4;\n v5 += v4;\n } while (a1 >= (int)v5);\n }\n ++v4;\n } while (v4 != a1 + 1);\n }\n }\n return (unsigned int)v8[a1];\n}" + }, + { + "index": 849, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int N) {\n int SumOfPrimeDivisors[N + 1];\n for (int i = 0; i <= N; i++) {\n SumOfPrimeDivisors[i] = 0;\n }\n for (int i = 2; i <= N; i++) {\n if (SumOfPrimeDivisors[i] == 0) {\n for (int j = i; j <= N; j += i) {\n SumOfPrimeDivisors[j] += i;\n }\n }\n }\n return SumOfPrimeDivisors[N];\n}", + "test": "int main() {\n\n assert(func0(60) == 10);\n\n assert(func0(39) == 16);\n\n assert(func0(40) == 7);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0x1(%rdi),%eax\nmov %rsp,%rsi\ncltq\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rsi\nand $0xfffffffffffffff0,%rdx\nmov %rsi,%rax\ncmp %rax,%rsp\nje 1268 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 1253 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 1306 \nmov %rsp,%rsi\nmovslq %edi,%r10\ntest %edi,%edi\njs 12f1 \nmovslq %edi,%r10\nmov %rsi,%rax\nlea 0x4(%rsi,%r10,4),%rdx\nmovl $0x0,(%rax)\nadd $0x4,%rax\ncmp %rdx,%rax\njne 1290 \ncmp $0x1,%edi\njle 12f1 \nlea -0x2(%rdi),%r9d\nmov $0x2,%ecx\nadd $0x3,%r9\njmp 12c1 \nnopl 0x0(%rax,%rax,1)\nadd $0x1,%rcx\ncmp %r9,%rcx\nje 12f1 \nmov (%rsi,%rcx,4),%edx\nmov %ecx,%r8d\ntest %edx,%edx\njne 12b8 \ncmp %ecx,%edi\njl 12b8 \nmov %rcx,%rax\njmp 12db \nnopl 0x0(%rax)\nmov (%rsi,%rax,4),%edx\nadd %r8d,%edx\nmov %edx,(%rsi,%rax,4)\nadd %rcx,%rax\ncmp %eax,%edi\njge 12d8 \nadd $0x1,%rcx\ncmp %r9,%rcx\njne 12c1 \nmov -0x8(%rbp),%rdi\nxor %fs:0x28,%rdi\nmov (%rsi,%r10,4),%eax\njne 1311 \nleaveq\nretq\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 127a \ncallq 1060 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r13\npush r12\nlea r12d, [rdi+1]\npush rbx\nmov ebx, edi\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nmovsxd rax, r12d\nmov rcx, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_128E\nloc_1279:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rcx\njnz short loc_1279\nloc_128E:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1321\nloc_12A0:\nmov rcx, rsp\nmovsxd r13, ebx\ntest ebx, ebx\njs short loc_1303\nmov rdi, rcx; s\nlea rdx, ds:4[r13*4]; n\nxor esi, esi; c\ncall _memset\nmov rcx, rax\ncmp ebx, 1\njle short loc_1303\nmov edi, r12d\nmov edx, 2\njmp short loc_12D9\nloc_12D0:\nadd rdx, 1\ncmp rdx, rdi\njz short loc_1303\nloc_12D9:\nmov eax, [rcx+rdx*4]\ntest eax, eax\njnz short loc_12D0\ncmp ebx, edx\njl short loc_12D0\nmov esi, edx\nmov rax, rdx\nnop dword ptr [rax+00000000h]\nloc_12F0:\nadd [rcx+rax*4], esi\nadd rax, rdx\ncmp ebx, eax\njge short loc_12F0\nadd rdx, 1\ncmp rdx, rdi\njnz short loc_12D9\nloc_1303:\nmov eax, [rcx+r13*4]\nmov rdx, [rbp+var_28]\nsub rdx, fs:28h\njnz short loc_132C\nlea rsp, [rbp-18h]\npop rbx\npop r12\npop r13\npop rbp\nretn\nloc_1321:\nor [rsp+rdx+1030h+var_1038], 0\njmp loc_12A0\nloc_132C:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // r12d\n __int64 v2; // rdx\n _BYTE *v3; // rcx\n __int16 v4; // dx\n signed __int64 v5; // rdx\n void *v6; // rsp\n _BYTE *v7; // rcx\n __int64 v8; // rdx\n __int64 v9; // rax\n _BYTE v12[4088]; // [rsp+8h] [rbp-1030h] BYREF\n _QWORD v13[6]; // [rsp+1008h] [rbp-30h] BYREF\n\n v1 = a1 + 1;\n v13[1] = __readfsqword(0x28u);\n v2 = 4LL * (a1 + 1) + 15;\n v3 = (char *)v13 - (v2 & 0xFFFFFFFFFFFFF000LL);\n v4 = v2 & 0xFFF0;\n if ( v13 != (_QWORD *)v3 )\n {\n while ( v12 != v3 )\n ;\n }\n v5 = v4 & 0xFFF;\n v6 = alloca(v5);\n if ( v5 )\n *(_QWORD *)&v12[v5 - 8] = *(_QWORD *)&v12[v5 - 8];\n v7 = v12;\n if ( a1 >= 0 )\n {\n v7 = memset(v12, 0, 4LL * a1 + 4);\n if ( a1 > 1 )\n {\n v8 = 2LL;\n do\n {\n while ( *(_DWORD *)&v7[4 * v8] || a1 < (int)v8 )\n {\n if ( ++v8 == v1 )\n return *(unsigned int *)&v7[4 * a1];\n }\n v9 = v8;\n do\n {\n *(_DWORD *)&v7[4 * v9] += v8;\n v9 += v8;\n }\n while ( a1 >= (int)v9 );\n ++v8;\n }\n while ( v8 != v1 );\n }\n }\n return *(unsigned int *)&v7[4 * a1];\n}", + "ida_strip_asm": "sub_1230:\nendbr64\npush rbp\nmov rbp, rsp\npush r13\npush r12\nlea r12d, [rdi+1]\npush rbx\nmov ebx, edi\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nmovsxd rax, r12d\nmov rcx, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_128E\nloc_1279:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rcx\njnz short loc_1279\nloc_128E:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1321\nloc_12A0:\nmov rcx, rsp\nmovsxd r13, ebx\ntest ebx, ebx\njs short loc_1303\nmov rdi, rcx; s\nlea rdx, ds:4[r13*4]; n\nxor esi, esi; c\ncall _memset\nmov rcx, rax\ncmp ebx, 1\njle short loc_1303\nmov edi, r12d\nmov edx, 2\njmp short loc_12D9\nloc_12D0:\nadd rdx, 1\ncmp rdx, rdi\njz short loc_1303\nloc_12D9:\nmov eax, [rcx+rdx*4]\ntest eax, eax\njnz short loc_12D0\ncmp ebx, edx\njl short loc_12D0\nmov esi, edx\nmov rax, rdx\nnop dword ptr [rax+00000000h]\nloc_12F0:\nadd [rcx+rax*4], esi\nadd rax, rdx\ncmp ebx, eax\njge short loc_12F0\nadd rdx, 1\ncmp rdx, rdi\njnz short loc_12D9\nloc_1303:\nmov eax, [rcx+r13*4]\nmov rdx, [rbp+var_28]\nsub rdx, fs:28h\njnz short loc_132C\nlea rsp, [rbp-18h]\npop rbx\npop r12\npop r13\npop rbp\nretn\nloc_1321:\nor [rsp+rdx+1030h+var_1038], 0\njmp loc_12A0\nloc_132C:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1230(int a1)\n{\n int v1; // r12d\n __int64 v2; // rdx\n _BYTE *v3; // rcx\n __int16 v4; // dx\n signed __int64 v5; // rdx\n void *v6; // rsp\n _BYTE *v7; // rcx\n __int64 v8; // rdx\n __int64 v9; // rax\n _BYTE v12[4088]; // [rsp+8h] [rbp-1030h] BYREF\n _QWORD v13[6]; // [rsp+1008h] [rbp-30h] BYREF\n\n v1 = a1 + 1;\n v13[1] = __readfsqword(0x28u);\n v2 = 4LL * (a1 + 1) + 15;\n v3 = (char *)v13 - (v2 & 0xFFFFFFFFFFFFF000LL);\n v4 = v2 & 0xFFF0;\n if ( v13 != (_QWORD *)v3 )\n {\n while ( v12 != v3 )\n ;\n }\n v5 = v4 & 0xFFF;\n v6 = alloca(v5);\n if ( v5 )\n *(_QWORD *)&v12[v5 - 8] = *(_QWORD *)&v12[v5 - 8];\n v7 = v12;\n if ( a1 >= 0 )\n {\n v7 = memset(v12, 0, 4LL * a1 + 4);\n if ( a1 > 1 )\n {\n v8 = 2LL;\n do\n {\n while ( *(_DWORD *)&v7[4 * v8] || a1 < (int)v8 )\n {\n if ( ++v8 == v1 )\n return *(unsigned int *)&v7[4 * a1];\n }\n v9 = v8;\n do\n {\n *(_DWORD *)&v7[4 * v9] += v8;\n v9 += v8;\n }\n while ( a1 >= (int)v9 );\n ++v8;\n }\n while ( v8 != v1 );\n }\n }\n return *(unsigned int *)&v7[4 * a1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1230(int a1) {\n int v1;\n long long v2;\n uint8_t *v3;\n short v4;\n signed long long v5;\n void *v6;\n uint8_t *v7;\n long long v8;\n long long v9;\n uint8_t v12[4088];\n uint64_t v13[6];\n v1 = a1 + 1;\n v13[1] = __readfsqword(40u);\n v2 = 4LL * (a1 + 1) + 15;\n v3 = (char *)v13 - (v2 & 18446744073709547520LL);\n v4 = v2 & 65520;\n if (v13 != (uint64_t *)v3) {\n while (v12 != v3)\n ;\n }\n v5 = v4 & 4095;\n v6 = alloca(v5);\n if (v5) *(uint64_t *)&v12[v5 - 8] = *(uint64_t *)&v12[v5 - 8];\n v7 = v12;\n if (a1 >= 0) {\n v7 = memset(v12, 0, 4LL * a1 + 4);\n if (a1 > 1) {\n v8 = 2LL;\n do {\n while (*(uint32_t *)&v7[4 * v8] || a1 < (int)v8) {\n if (++v8 == v1) return *(unsigned int *)&v7[4 * a1];\n }\n v9 = v8;\n do {\n *(uint32_t *)&v7[4 * v9] += v8;\n v9 += v8;\n } while (a1 >= (int)v9);\n ++v8;\n } while (v8 != v1);\n }\n }\n return *(unsigned int *)&v7[4 * a1];\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n long long v2;\n uint8_t *v3;\n short v4;\n signed long long v5;\n void *v6;\n uint8_t *v7;\n long long v8;\n long long v9;\n uint8_t v12[4088];\n uint64_t v13[6];\n v1 = a1 + 1;\n v13[1] = __readfsqword(40u);\n v2 = 4LL * (a1 + 1) + 15;\n v3 = (char *)v13 - (v2 & 18446744073709547520LL);\n v4 = v2 & 65520;\n if (v13 != (uint64_t *)v3) {\n while (v12 != v3)\n ;\n }\n v5 = v4 & 4095;\n v6 = alloca(v5);\n if (v5) *(uint64_t *)&v12[v5 - 8] = *(uint64_t *)&v12[v5 - 8];\n v7 = v12;\n if (a1 >= 0) {\n v7 = memset(v12, 0, 4LL * a1 + 4);\n if (a1 > 1) {\n v8 = 2LL;\n do {\n while (*(uint32_t *)&v7[4 * v8] || a1 < (int)v8) {\n if (++v8 == v1) return *(unsigned int *)&v7[4 * a1];\n }\n v9 = v8;\n do {\n *(uint32_t *)&v7[4 * v9] += v8;\n v9 += v8;\n } while (a1 >= (int)v9);\n ++v8;\n } while (v8 != v1);\n }\n }\n return *(unsigned int *)&v7[4 * a1];\n}" + }, + { + "index": 849, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int N) {\n int SumOfPrimeDivisors[N + 1];\n for (int i = 0; i <= N; i++) {\n SumOfPrimeDivisors[i] = 0;\n }\n for (int i = 2; i <= N; i++) {\n if (SumOfPrimeDivisors[i] == 0) {\n for (int j = i; j <= N; j += i) {\n SumOfPrimeDivisors[j] += i;\n }\n }\n }\n return SumOfPrimeDivisors[N];\n}", + "test": "int main() {\n\n assert(func0(60) == 10);\n\n assert(func0(39) == 16);\n\n assert(func0(40) == 7);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r12\npush %rbx\nmov %edi,%ebx\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nlea 0x1(%rdi),%eax\nmov %rsp,%rdi\ncltq\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rdi\nand $0xfffffffffffffff0,%rdx\nmov %rdi,%rax\ncmp %rax,%rsp\nje 128d \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 1278 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 1317 \nmov %rsp,%rcx\nmovslq %ebx,%r12\ntest %ebx,%ebx\njs 12fb \nmov %rcx,%rdi\nlea 0x4(,%r12,4),%rdx\nxor %esi,%esi\ncallq 1090 \nmov %rax,%rcx\ncmp $0x1,%ebx\njle 12fb \nlea -0x2(%rbx),%edi\nmov $0x2,%edx\nadd $0x3,%rdi\njmp 12d9 \nnopl (%rax)\nadd $0x1,%rdx\ncmp %rdi,%rdx\nje 12fb \nmov (%rcx,%rdx,4),%eax\nmov %edx,%esi\ntest %eax,%eax\njne 12d0 \nmov %rdx,%rax\nnopl (%rax)\nadd %esi,(%rcx,%rax,4)\nadd %rdx,%rax\ncmp %eax,%ebx\njge 12e8 \nadd $0x1,%rdx\ncmp %rdi,%rdx\njne 12d9 \nmov -0x18(%rbp),%rdi\nxor %fs:0x28,%rdi\nmov (%rcx,%r12,4),%eax\njne 1322 \nlea -0x10(%rbp),%rsp\npop %rbx\npop %r12\npop %rbp\nretq\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 129b \ncallq 1070 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r13\npush r12\nlea r12d, [rdi+1]\npush rbx\nmov ebx, edi\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nmovsxd rax, r12d\nmov rcx, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_128E\nloc_1279:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rcx\njnz short loc_1279\nloc_128E:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz short loc_1314\nloc_129C:\nmov rcx, rsp\nmovsxd r13, ebx\ntest ebx, ebx\njs short loc_12E0\nmov rdi, rcx; s\nlea rdx, ds:4[r13*4]; n\nxor esi, esi; c\ncall _memset\nmov rcx, rax\ncmp ebx, 1\njle short loc_12E0\nmov edi, r12d\nmov edx, 2\nnop dword ptr [rax+rax+00000000h]\nloc_12D0:\nmov eax, [rcx+rdx*4]\ntest eax, eax\njz short loc_1300\nloc_12D7:\nadd rdx, 1\ncmp rdi, rdx\njnz short loc_12D0\nloc_12E0:\nmov eax, [rcx+r13*4]\nmov rdx, [rbp+var_28]\nsub rdx, fs:28h\njnz short loc_131C\nlea rsp, [rbp-18h]\npop rbx\npop r12\npop r13\npop rbp\nretn\nloc_1300:\nmov esi, edx\nmov rax, rdx\nnop dword ptr [rax]\nloc_1308:\nadd [rcx+rax*4], esi\nadd rax, rdx\ncmp ebx, eax\njge short loc_1308\njmp short loc_12D7\nloc_1314:\nor [rsp+rdx+1030h+var_1038], 0\njmp short loc_129C\nloc_131C:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n __int64 v1; // rdx\n _BYTE *v2; // rcx\n __int16 v3; // dx\n signed __int64 v4; // rdx\n void *v5; // rsp\n _BYTE *v6; // rcx\n __int64 v7; // rdx\n __int64 v9; // rax\n _BYTE v11[4088]; // [rsp+8h] [rbp-1030h] BYREF\n _QWORD v12[6]; // [rsp+1008h] [rbp-30h] BYREF\n\n v12[1] = __readfsqword(0x28u);\n v1 = 4LL * (a1 + 1) + 15;\n v2 = (char *)v12 - (v1 & 0xFFFFFFFFFFFFF000LL);\n v3 = v1 & 0xFFF0;\n if ( v12 != (_QWORD *)v2 )\n {\n while ( v11 != v2 )\n ;\n }\n v4 = v3 & 0xFFF;\n v5 = alloca(v4);\n if ( v4 )\n *(_QWORD *)&v11[v4 - 8] = *(_QWORD *)&v11[v4 - 8];\n v6 = v11;\n if ( a1 >= 0 )\n {\n v6 = memset(v11, 0, 4LL * a1 + 4);\n if ( a1 > 1 )\n {\n v7 = 2LL;\n do\n {\n if ( !*(_DWORD *)&v6[4 * v7] )\n {\n v9 = v7;\n do\n {\n *(_DWORD *)&v6[4 * v9] += v7;\n v9 += v7;\n }\n while ( a1 >= (int)v9 );\n }\n ++v7;\n }\n while ( a1 + 1 != v7 );\n }\n }\n return *(unsigned int *)&v6[4 * a1];\n}", + "ida_strip_asm": "sub_1230:\nendbr64\npush rbp\nmov rbp, rsp\npush r13\npush r12\nlea r12d, [rdi+1]\npush rbx\nmov ebx, edi\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nmovsxd rax, r12d\nmov rcx, rsp\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_128E\nloc_1279:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rcx\njnz short loc_1279\nloc_128E:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz short loc_1314\nloc_129C:\nmov rcx, rsp\nmovsxd r13, ebx\ntest ebx, ebx\njs short loc_12E0\nmov rdi, rcx; s\nlea rdx, ds:4[r13*4]; n\nxor esi, esi; c\ncall _memset\nmov rcx, rax\ncmp ebx, 1\njle short loc_12E0\nmov edi, r12d\nmov edx, 2\nnop dword ptr [rax+rax+00000000h]\nloc_12D0:\nmov eax, [rcx+rdx*4]\ntest eax, eax\njz short loc_1300\nloc_12D7:\nadd rdx, 1\ncmp rdi, rdx\njnz short loc_12D0\nloc_12E0:\nmov eax, [rcx+r13*4]\nmov rdx, [rbp+var_28]\nsub rdx, fs:28h\njnz short loc_131C\nlea rsp, [rbp-18h]\npop rbx\npop r12\npop r13\npop rbp\nretn\nloc_1300:\nmov esi, edx\nmov rax, rdx\nnop dword ptr [rax]\nloc_1308:\nadd [rcx+rax*4], esi\nadd rax, rdx\ncmp ebx, eax\njge short loc_1308\njmp short loc_12D7\nloc_1314:\nor [rsp+rdx+1030h+var_1038], 0\njmp short loc_129C\nloc_131C:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1230(int a1)\n{\n __int64 v1; // rdx\n _BYTE *v2; // rcx\n __int16 v3; // dx\n signed __int64 v4; // rdx\n void *v5; // rsp\n _BYTE *v6; // rcx\n __int64 v7; // rdx\n __int64 v9; // rax\n _BYTE v11[4088]; // [rsp+8h] [rbp-1030h] BYREF\n _QWORD v12[6]; // [rsp+1008h] [rbp-30h] BYREF\n\n v12[1] = __readfsqword(0x28u);\n v1 = 4LL * (a1 + 1) + 15;\n v2 = (char *)v12 - (v1 & 0xFFFFFFFFFFFFF000LL);\n v3 = v1 & 0xFFF0;\n if ( v12 != (_QWORD *)v2 )\n {\n while ( v11 != v2 )\n ;\n }\n v4 = v3 & 0xFFF;\n v5 = alloca(v4);\n if ( v4 )\n *(_QWORD *)&v11[v4 - 8] = *(_QWORD *)&v11[v4 - 8];\n v6 = v11;\n if ( a1 >= 0 )\n {\n v6 = memset(v11, 0, 4LL * a1 + 4);\n if ( a1 > 1 )\n {\n v7 = 2LL;\n do\n {\n if ( !*(_DWORD *)&v6[4 * v7] )\n {\n v9 = v7;\n do\n {\n *(_DWORD *)&v6[4 * v9] += v7;\n v9 += v7;\n }\n while ( a1 >= (int)v9 );\n }\n ++v7;\n }\n while ( a1 + 1 != v7 );\n }\n }\n return *(unsigned int *)&v6[4 * a1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1230(int a1) {\n long long v1;\n uint8_t *v2;\n short v3;\n signed long long v4;\n void *v5;\n uint8_t *v6;\n long long v7;\n long long v9;\n uint8_t v11[4088];\n uint64_t v12[6];\n v12[1] = __readfsqword(40u);\n v1 = 4LL * (a1 + 1) + 15;\n v2 = (char *)v12 - (v1 & 18446744073709547520LL);\n v3 = v1 & 65520;\n if (v12 != (uint64_t *)v2) {\n while (v11 != v2)\n ;\n }\n v4 = v3 & 4095;\n v5 = alloca(v4);\n if (v4) *(uint64_t *)&v11[v4 - 8] = *(uint64_t *)&v11[v4 - 8];\n v6 = v11;\n if (a1 >= 0) {\n v6 = memset(v11, 0, 4LL * a1 + 4);\n if (a1 > 1) {\n v7 = 2LL;\n do {\n if (!*(uint32_t *)&v6[4 * v7]) {\n v9 = v7;\n do {\n *(uint32_t *)&v6[4 * v9] += v7;\n v9 += v7;\n } while (a1 >= (int)v9);\n }\n ++v7;\n } while (a1 + 1 != v7);\n }\n }\n return *(unsigned int *)&v6[4 * a1];\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n long long v1;\n uint8_t *v2;\n short v3;\n signed long long v4;\n void *v5;\n uint8_t *v6;\n long long v7;\n long long v9;\n uint8_t v11[4088];\n uint64_t v12[6];\n v12[1] = __readfsqword(40u);\n v1 = 4LL * (a1 + 1) + 15;\n v2 = (char *)v12 - (v1 & 18446744073709547520LL);\n v3 = v1 & 65520;\n if (v12 != (uint64_t *)v2) {\n while (v11 != v2)\n ;\n }\n v4 = v3 & 4095;\n v5 = alloca(v4);\n if (v4) *(uint64_t *)&v11[v4 - 8] = *(uint64_t *)&v11[v4 - 8];\n v6 = v11;\n if (a1 >= 0) {\n v6 = memset(v11, 0, 4LL * a1 + 4);\n if (a1 > 1) {\n v7 = 2LL;\n do {\n if (!*(uint32_t *)&v6[4 * v7]) {\n v9 = v7;\n do {\n *(uint32_t *)&v6[4 * v9] += v7;\n v9 += v7;\n } while (a1 >= (int)v9);\n }\n ++v7;\n } while (a1 + 1 != v7);\n }\n }\n return *(unsigned int *)&v6[4 * a1];\n}" + }, + { + "index": 850, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int a, int b, int c) {\n if (a != 0 && b != 0 && c != 0 && (a + b + c) == 180) {\n if ((a + b) >= c || (b + c) >= a || (a + c) >= b) {\n return 1;\n } else {\n return 0;\n }\n } else {\n return 0;\n }\n}", + "test": "int main() {\n\n assert(func0(50, 60, 70) == 1);\n\n assert(func0(90, 45, 45) == 1);\n\n assert(func0(150, 30, 70) == 0);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov %esi,-0x8(%rbp)\nmov %edx,-0xc(%rbp)\ncmpl $0x0,-0x4(%rbp)\nje 11b5 \ncmpl $0x0,-0x8(%rbp)\nje 11b5 \ncmpl $0x0,-0xc(%rbp)\nje 11b5 \nmov -0x4(%rbp),%edx\nmov -0x8(%rbp),%eax\nadd %eax,%edx\nmov -0xc(%rbp),%eax\nadd %edx,%eax\ncmp $0xb4,%eax\njne 11b5 \nmov -0x4(%rbp),%edx\nmov -0x8(%rbp),%eax\nadd %edx,%eax\ncmp %eax,-0xc(%rbp)\njle 11a7 \nmov -0x8(%rbp),%edx\nmov -0xc(%rbp),%eax\nadd %edx,%eax\ncmp %eax,-0x4(%rbp)\njle 11a7 \nmov -0x4(%rbp),%edx\nmov -0xc(%rbp),%eax\nadd %edx,%eax\ncmp %eax,-0x8(%rbp)\njg 11ae \nmov $0x1,%eax\njmp 11ba \nmov $0x0,%eax\njmp 11ba \nmov $0x0,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov [rbp+var_C], edx\ncmp [rbp+var_4], 0\njz short loc_11B5\ncmp [rbp+var_8], 0\njz short loc_11B5\ncmp [rbp+var_C], 0\njz short loc_11B5\nmov edx, [rbp+var_4]\nmov eax, [rbp+var_8]\nadd edx, eax\nmov eax, [rbp+var_C]\nadd eax, edx\ncmp eax, 0B4h\njnz short loc_11B5\nmov edx, [rbp+var_4]\nmov eax, [rbp+var_8]\nadd eax, edx\ncmp [rbp+var_C], eax\njle short loc_11A7\nmov edx, [rbp+var_8]\nmov eax, [rbp+var_C]\nadd eax, edx\ncmp [rbp+var_4], eax\njle short loc_11A7\nmov edx, [rbp+var_4]\nmov eax, [rbp+var_C]\nadd eax, edx\ncmp [rbp+var_8], eax\njg short loc_11AE\nloc_11A7:\nmov eax, 1\njmp short loc_11BA\nloc_11AE:\nmov eax, 0\njmp short loc_11BA\nloc_11B5:\nmov eax, 0\nloc_11BA:\npop rbp\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(int a1, int a2, int a3)\n{\n if ( !a1 || !a2 || !a3 || a2 + a1 + a3 != 180 )\n return 0LL;\n return a3 <= a1 + a2 || a1 <= a2 + a3 || a2 <= a1 + a3;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov [rbp+var_C], edx\ncmp [rbp+var_4], 0\njz short loc_11B5\ncmp [rbp+var_8], 0\njz short loc_11B5\ncmp [rbp+var_C], 0\njz short loc_11B5\nmov edx, [rbp+var_4]\nmov eax, [rbp+var_8]\nadd edx, eax\nmov eax, [rbp+var_C]\nadd eax, edx\ncmp eax, 0B4h\njnz short loc_11B5\nmov edx, [rbp+var_4]\nmov eax, [rbp+var_8]\nadd eax, edx\ncmp [rbp+var_C], eax\njle short loc_11A7\nmov edx, [rbp+var_8]\nmov eax, [rbp+var_C]\nadd eax, edx\ncmp [rbp+var_4], eax\njle short loc_11A7\nmov edx, [rbp+var_4]\nmov eax, [rbp+var_C]\nadd eax, edx\ncmp [rbp+var_8], eax\njg short loc_11AE\nloc_11A7:\nmov eax, 1\njmp short loc_11BA\nloc_11AE:\nmov eax, 0\njmp short loc_11BA\nloc_11B5:\nmov eax, 0\nloc_11BA:\npop rbp\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1149(int a1, int a2, int a3)\n{\n if ( !a1 || !a2 || !a3 || a2 + a1 + a3 != 180 )\n return 0LL;\n return a3 <= a1 + a2 || a1 <= a2 + a3 || a2 <= a1 + a3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1149(int a1, int a2, int a3) {\n if (!a1 || !a2 || !a3 || a2 + a1 + a3 != 180) return 0LL;\n return a3 <= a1 + a2 || a1 <= a2 + a3 || a2 <= a1 + a3;\n}", + "ida_pseudo_norm": "uint8_t func0(int a1, int a2, int a3) {\n if (!a1 || !a2 || !a3 || a2 + a1 + a3 != 180) return 0LL;\n return a3 <= a1 + a2 || a1 <= a2 + a3 || a2 <= a1 + a3;\n}" + }, + { + "index": 851, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "double func0(int N, int Sum) {\n double ans = (double)Sum / (double)N;\n return round(ans * 100) / 100;\n}", + "test": "int main() {\n\n assert(func0(6, 12) == 2);\n\n assert(fabs(func0(9, 13) - 1.44) < 0.01);\n\n assert(func0(1, 4) == 4);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\ncvtsi2sdl -0x18(%rbp),%xmm0\ncvtsi2sdl -0x14(%rbp),%xmm1\ndivsd %xmm1,%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmovsd -0x8(%rbp),%xmm1\nmovsd 0xefd(%rip),%xmm0\nmulsd %xmm1,%xmm0\ncallq 1060 \nmovsd 0xeec(%rip),%xmm1\ndivsd %xmm1,%xmm0\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_18]\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_14]\ndivsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm1, [rbp+var_8]\nmovsd xmm0, cs:qword_2080\nmulsd xmm1, xmm0\nmovq rax, xmm1\nmovq xmm0, rax; x\ncall _round\nmovq rax, xmm0\nmovsd xmm0, cs:qword_2080\nmovq xmm1, rax\ndivsd xmm1, xmm0\nmovapd xmm0, xmm1\nleave\nretn", + "ida_pseudo": "__int128 __usercall func0@(int a1@, int a2@)\n{\n double v2; // rax\n __int128 v3; // xmm1\n\n v2 = round((double)a2 / (double)a1 * 100.0);\n v3 = *(unsigned __int64 *)&v2;\n *(double *)&v3 = v2 / 100.0;\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_18]\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_14]\ndivsd xmm0, xmm1\nmovsd [rbp+var_8], xmm0\nmovsd xmm1, [rbp+var_8]\nmovsd xmm0, cs:qword_2080\nmulsd xmm1, xmm0\nmovq rax, xmm1\nmovq xmm0, rax; x\ncall _round\nmovq rax, xmm0\nmovsd xmm0, cs:qword_2080\nmovq xmm1, rax\ndivsd xmm1, xmm0\nmovapd xmm0, xmm1\nleave\nretn", + "ida_strip_pseudo": "__int128 __usercall sub_1169@(int a1@, int a2@)\n{\n double v2; // rax\n __int128 v3; // xmm1\n\n v2 = round((double)a2 / (double)a1 * 100.0);\n v3 = *(unsigned __int64 *)&v2;\n *(double *)&v3 = v2 / 100.0;\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "__int128 __usercall sub_1169 @(int a1 @, int a2 @) {\n double v2;\n __int128 v3;\n v2 = round((double)a2 / (double)a1 * 100.0);\n v3 = *(unsigned long long *)&v2;\n *(double *)&v3 = v2 / 100.0;\n return v3;\n}", + "ida_pseudo_norm": "__int128 __usercall func0 @(int a1 @, int a2 @) {\n double v2;\n __int128 v3;\n v2 = round((double)a2 / (double)a1 * 100.0);\n v3 = *(unsigned long long *)&v2;\n *(double *)&v3 = v2 / 100.0;\n return v3;\n}" + }, + { + "index": 851, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "double func0(int N, int Sum) {\n double ans = (double)Sum / (double)N;\n return round(ans * 100) / 100;\n}", + "test": "int main() {\n\n assert(func0(6, 12) == 2);\n\n assert(fabs(func0(9, 13) - 1.44) < 0.01);\n\n assert(func0(1, 4) == 4);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x8,%rsp\npxor %xmm0,%xmm0\ncvtsi2sd %esi,%xmm0\npxor %xmm1,%xmm1\ncvtsi2sd %edi,%xmm1\ndivsd %xmm1,%xmm0\nmulsd 0xe9b(%rip),%xmm0\ncallq 1050 \ndivsd 0xe8e(%rip),%xmm0\nadd $0x8,%rsp\nretq\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\npxor xmm0, xmm0\ncvtsi2sd xmm0, esi\npxor xmm1, xmm1\ncvtsi2sd xmm1, edi\ndivsd xmm0, xmm1\nmulsd xmm0, cs:qword_2008; x\ncall _round\ndivsd xmm0, cs:qword_2008\nadd rsp, 8\nretn", + "ida_pseudo": "double __fastcall func0(int a1, int a2)\n{\n return round((double)a2 / (double)a1 * 100.0) / 100.0;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nsub rsp, 8\npxor xmm0, xmm0\ncvtsi2sd xmm0, esi\npxor xmm1, xmm1\ncvtsi2sd xmm1, edi\ndivsd xmm0, xmm1\nmulsd xmm0, cs:qword_2008; x\ncall _round\ndivsd xmm0, cs:qword_2008\nadd rsp, 8\nretn", + "ida_strip_pseudo": "double __fastcall sub_1149(int a1, int a2)\n{\n return round((double)a2 / (double)a1 * 100.0) / 100.0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1149(int a1, int a2) {\n return round((double)a2 / (double)a1 * 100.0) / 100.0;\n}", + "ida_pseudo_norm": "double func0(int a1, int a2) {\n return round((double)a2 / (double)a1 * 100.0) / 100.0;\n}" + }, + { + "index": 851, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "double func0(int N, int Sum) {\n double ans = (double)Sum / (double)N;\n return round(ans * 100) / 100;\n}", + "test": "int main() {\n\n assert(func0(6, 12) == 2);\n\n assert(fabs(func0(9, 13) - 1.44) < 0.01);\n\n assert(func0(1, 4) == 4);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npxor %xmm0,%xmm0\npxor %xmm1,%xmm1\nsub $0x8,%rsp\ncvtsi2sd %esi,%xmm0\ncvtsi2sd %edi,%xmm1\ndivsd %xmm1,%xmm0\nmulsd 0xe84(%rip),%xmm0\ncallq 1050 \ndivsd 0xe77(%rip),%xmm0\nadd $0x8,%rsp\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npxor xmm0, xmm0\npxor xmm1, xmm1\nsub rsp, 8\ncvtsi2sd xmm0, esi\ncvtsi2sd xmm1, edi\ndivsd xmm0, xmm1\nmulsd xmm0, cs:qword_2008; x\ncall _round\ndivsd xmm0, cs:qword_2008\nadd rsp, 8\nretn", + "ida_pseudo": "double __fastcall func0(int a1, int a2)\n{\n return round((double)a2 / (double)a1 * 100.0) / 100.0;\n}", + "ida_strip_asm": "sub_1160:\nendbr64\npxor xmm0, xmm0\npxor xmm1, xmm1\nsub rsp, 8\ncvtsi2sd xmm0, esi\ncvtsi2sd xmm1, edi\ndivsd xmm0, xmm1\nmulsd xmm0, cs:qword_2008; x\ncall _round\ndivsd xmm0, cs:qword_2008\nadd rsp, 8\nretn", + "ida_strip_pseudo": "double __fastcall sub_1160(int a1, int a2)\n{\n return round((double)a2 / (double)a1 * 100.0) / 100.0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1160(int a1, int a2) {\n return round((double)a2 / (double)a1 * 100.0) / 100.0;\n}", + "ida_pseudo_norm": "double func0(int a1, int a2) {\n return round((double)a2 / (double)a1 * 100.0) / 100.0;\n}" + }, + { + "index": 851, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "double func0(int N, int Sum) {\n double ans = (double)Sum / (double)N;\n return round(ans * 100) / 100;\n}", + "test": "int main() {\n\n assert(func0(6, 12) == 2);\n\n assert(fabs(func0(9, 13) - 1.44) < 0.01);\n\n assert(func0(1, 4) == 4);\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npxor %xmm0,%xmm0\npxor %xmm1,%xmm1\nsub $0x8,%rsp\ncvtsi2sd %esi,%xmm0\ncvtsi2sd %edi,%xmm1\ndivsd %xmm1,%xmm0\nmulsd 0xe84(%rip),%xmm0\ncallq 1050 \ndivsd 0xe77(%rip),%xmm0\nadd $0x8,%rsp\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npxor xmm0, xmm0\npxor xmm1, xmm1\nsub rsp, 8\ncvtsi2sd xmm0, esi\ncvtsi2sd xmm1, edi\ndivsd xmm0, xmm1\nmulsd xmm0, cs:qword_2008; x\ncall _round\ndivsd xmm0, cs:qword_2008\nadd rsp, 8\nretn", + "ida_pseudo": "double __fastcall func0(int a1, int a2)\n{\n return round((double)a2 / (double)a1 * 100.0) / 100.0;\n}", + "ida_strip_asm": "sub_1160:\nendbr64\npxor xmm0, xmm0\npxor xmm1, xmm1\nsub rsp, 8\ncvtsi2sd xmm0, esi\ncvtsi2sd xmm1, edi\ndivsd xmm0, xmm1\nmulsd xmm0, cs:qword_2008; x\ncall _round\ndivsd xmm0, cs:qword_2008\nadd rsp, 8\nretn", + "ida_strip_pseudo": "double __fastcall sub_1160(int a1, int a2)\n{\n return round((double)a2 / (double)a1 * 100.0) / 100.0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1160(int a1, int a2) {\n return round((double)a2 / (double)a1 * 100.0) / 100.0;\n}", + "ida_pseudo_norm": "double func0(int a1, int a2) {\n return round((double)a2 / (double)a1 * 100.0) / 100.0;\n}" + }, + { + "index": 852, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int* func0(int num_list[], int num_elems, int* result_size) {\n int* new_list = (int*)malloc(num_elems * sizeof(int));\n int j = 0;\n for (int i = 0; i < num_elems; i++) {\n if (num_list[i] >= 0) {\n new_list[j++] = num_list[i];\n }\n }\n *result_size = j;\n return new_list;\n}", + "test": "int main() {\n\n int size;\n\n\n\n int list1[] = {1, -2, 3, -4};\n\n int* result1 = func0(list1, 4, &size);\n\n assert(size == 2 && result1[0] == 1 && result1[1] == 3);\n\n free(result1);\n\n\n\n int list2[] = {1, 2, 3, -4};\n\n int* result2 = func0(list2, 4, &size);\n\n assert(size == 3 && result2[0] == 1 && result2[1] == 2 && result2[2] == 3);\n\n free(result2);\n\n\n\n int list3[] = {4, 5, -6, 7, -8};\n\n int* result3 = func0(list3, 5, &size);\n\n assert(size == 3 && result3[0] == 4 && result3[1] == 5 && result3[2] == 7);\n\n free(result3);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmov -0x1c(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 1236 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ntest %eax,%eax\njs 1232 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x10(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x10(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11e5 \nmov -0x28(%rbp),%rax\nmov -0x10(%rbp),%edx\nmov %edx,(%rax)\nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp short loc_1236\nloc_11E5:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njs short loc_1232\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_1232:\nadd [rbp+var_C], 1\nloc_1236:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_11E5\nmov rax, [rbp+var_28]\nmov edx, [rbp+var_10]\nmov [rax], edx\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, _DWORD *a3)\n{\n int v3; // eax\n int v6; // [rsp+20h] [rbp-10h]\n int i; // [rsp+24h] [rbp-Ch]\n _DWORD *v8; // [rsp+28h] [rbp-8h]\n\n v8 = malloc(4LL * a2);\n v6 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(int *)(4LL * i + a1) >= 0 )\n {\n v3 = v6++;\n v8[v3] = *(_DWORD *)(4LL * i + a1);\n }\n }\n *a3 = v6;\n return v8;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp short loc_1236\nloc_11E5:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njs short loc_1232\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_1232:\nadd [rbp+var_C], 1\nloc_1236:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_11E5\nmov rax, [rbp+var_28]\nmov edx, [rbp+var_10]\nmov [rax], edx\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(__int64 a1, int a2, _DWORD *a3)\n{\n int v3; // eax\n int v6; // [rsp+20h] [rbp-10h]\n int i; // [rsp+24h] [rbp-Ch]\n _DWORD *v8; // [rsp+28h] [rbp-8h]\n\n v8 = malloc(4LL * a2);\n v6 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(int *)(4LL * i + a1) >= 0 )\n {\n v3 = v6++;\n v8[v3] = *(_DWORD *)(4LL * i + a1);\n }\n }\n *a3 = v6;\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(long long a1, int a2, uint32_t *a3) {\n int v3;\n int v6;\n int i;\n uint32_t *v8;\n v8 = malloc(4LL * a2);\n v6 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(int *)(4LL * i + a1) >= 0) {\n v3 = v6++;\n v8[v3] = *(uint32_t *)(4LL * i + a1);\n }\n }\n *a3 = v6;\n return v8;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, uint32_t *a3) {\n int v3;\n int v6;\n int i;\n uint32_t *v8;\n v8 = malloc(4LL * a2);\n v6 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(int *)(4LL * i + a1) >= 0) {\n v3 = v6++;\n v8[v3] = *(uint32_t *)(4LL * i + a1);\n }\n }\n *a3 = v6;\n return v8;\n}" + }, + { + "index": 852, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int* func0(int num_list[], int num_elems, int* result_size) {\n int* new_list = (int*)malloc(num_elems * sizeof(int));\n int j = 0;\n for (int i = 0; i < num_elems; i++) {\n if (num_list[i] >= 0) {\n new_list[j++] = num_list[i];\n }\n }\n *result_size = j;\n return new_list;\n}", + "test": "int main() {\n\n int size;\n\n\n\n int list1[] = {1, -2, 3, -4};\n\n int* result1 = func0(list1, 4, &size);\n\n assert(size == 2 && result1[0] == 1 && result1[1] == 3);\n\n free(result1);\n\n\n\n int list2[] = {1, 2, 3, -4};\n\n int* result2 = func0(list2, 4, &size);\n\n assert(size == 3 && result2[0] == 1 && result2[1] == 2 && result2[2] == 3);\n\n free(result2);\n\n\n\n int list3[] = {4, 5, -6, 7, -8};\n\n int* result3 = func0(list3, 5, &size);\n\n assert(size == 3 && result3[0] == 4 && result3[1] == 5 && result3[2] == 7);\n\n free(result3);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%r12\nmov %esi,%ebp\nmov %rdx,%rbx\nmovslq %esi,%rdi\nshl $0x2,%rdi\ncallq 10b0 \ntest %ebp,%ebp\njle 11f5 \nmov %r12,%rdx\nlea -0x1(%rbp),%ecx\nlea 0x4(%r12,%rcx,4),%r8\nmov $0x0,%esi\njmp 11e4 \nadd $0x4,%rdx\ncmp %r8,%rdx\nje 11fa \nmov (%rdx),%ecx\ntest %ecx,%ecx\njs 11db \nmovslq %esi,%rdi\nmov %ecx,(%rax,%rdi,4)\nlea 0x1(%rsi),%esi\njmp 11db \nmov $0x0,%esi\nmov %esi,(%rbx)\npop %rbx\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov r13d, esi\nmov rbp, rdx\nmovsxd r12, esi\nshl r12, 2\nmov rdi, r12; size\ncall _malloc\ntest r13d, r13d\njle short loc_11FD\nmov rdx, rbx\nlea rdi, [rbx+r12]\nmov esi, 0\njmp short loc_11F5\nloc_11E2:\nmovsxd r8, esi\nmov [rax+r8*4], ecx\nlea esi, [rsi+1]\nloc_11EC:\nadd rdx, 4\ncmp rdx, rdi\njz short loc_1202\nloc_11F5:\nmov ecx, [rdx]\ntest ecx, ecx\njns short loc_11E2\njmp short loc_11EC\nloc_11FD:\nmov esi, 0\nloc_1202:\nmov [rbp+0], esi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(_DWORD *a1, int a2, _DWORD *a3)\n{\n size_t v4; // r12\n _DWORD *result; // rax\n _DWORD *v6; // rdx\n int v7; // esi\n\n v4 = a2;\n result = malloc(v4 * 4);\n if ( a2 <= 0 )\n {\n v7 = 0;\n }\n else\n {\n v6 = a1;\n v7 = 0;\n do\n {\n if ( (int)*v6 >= 0 )\n result[v7++] = *v6;\n ++v6;\n }\n while ( v6 != &a1[v4] );\n }\n *a3 = v7;\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov r13d, esi\nmov rbp, rdx\nmovsxd r12, esi\nshl r12, 2\nmov rdi, r12; size\ncall _malloc\ntest r13d, r13d\njle short loc_11FD\nmov rdx, rbx\nlea rdi, [rbx+r12]\nmov esi, 0\njmp short loc_11F5\nloc_11E2:\nmovsxd r8, esi\nmov [rax+r8*4], ecx\nlea esi, [rsi+1]\nloc_11EC:\nadd rdx, 4\ncmp rdx, rdi\njz short loc_1202\nloc_11F5:\nmov ecx, [rdx]\ntest ecx, ecx\njns short loc_11E2\njmp short loc_11EC\nloc_11FD:\nmov esi, 0\nloc_1202:\nmov [rbp+0], esi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(_DWORD *a1, int a2, _DWORD *a3)\n{\n size_t v4; // r12\n _DWORD *result; // rax\n _DWORD *v6; // rdx\n int v7; // esi\n\n v4 = a2;\n result = malloc(v4 * 4);\n if ( a2 <= 0 )\n {\n v7 = 0;\n }\n else\n {\n v6 = a1;\n v7 = 0;\n do\n {\n if ( (int)*v6 >= 0 )\n result[v7++] = *v6;\n ++v6;\n }\n while ( v6 != &a1[v4] );\n }\n *a3 = v7;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(uint32_t *a1, int a2, uint32_t *a3) {\n unsigned int v4;\n uint32_t *result;\n uint32_t *v6;\n int v7;\n v4 = a2;\n result = malloc(v4 * 4);\n if (a2 <= 0) {\n v7 = 0;\n } else {\n v6 = a1;\n v7 = 0;\n do {\n if ((int)*v6 >= 0) result[v7++] = *v6;\n ++v6;\n } while (v6 != &a1[v4]);\n }\n *a3 = v7;\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(uint32_t *a1, int a2, uint32_t *a3) {\n unsigned int v4;\n uint32_t *result;\n uint32_t *v6;\n int v7;\n v4 = a2;\n result = malloc(v4 * 4);\n if (a2 <= 0) {\n v7 = 0;\n } else {\n v6 = a1;\n v7 = 0;\n do {\n if ((int)*v6 >= 0) result[v7++] = *v6;\n ++v6;\n } while (v6 != &a1[v4]);\n }\n *a3 = v7;\n return result;\n}" + }, + { + "index": 852, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int* func0(int num_list[], int num_elems, int* result_size) {\n int* new_list = (int*)malloc(num_elems * sizeof(int));\n int j = 0;\n for (int i = 0; i < num_elems; i++) {\n if (num_list[i] >= 0) {\n new_list[j++] = num_list[i];\n }\n }\n *result_size = j;\n return new_list;\n}", + "test": "int main() {\n\n int size;\n\n\n\n int list1[] = {1, -2, 3, -4};\n\n int* result1 = func0(list1, 4, &size);\n\n assert(size == 2 && result1[0] == 1 && result1[1] == 3);\n\n free(result1);\n\n\n\n int list2[] = {1, 2, 3, -4};\n\n int* result2 = func0(list2, 4, &size);\n\n assert(size == 3 && result2[0] == 1 && result2[1] == 2 && result2[2] == 3);\n\n free(result2);\n\n\n\n int list3[] = {4, 5, -6, 7, -8};\n\n int* result3 = func0(list3, 5, &size);\n\n assert(size == 3 && result3[0] == 4 && result3[1] == 5 && result3[2] == 7);\n\n free(result3);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %rdx,%r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nmovslq %esi,%rdi\nmov %rdi,%rbp\nshl $0x2,%rdi\ncallq 10b0 \ntest %ebp,%ebp\njle 13a8 \nlea -0x1(%rbp),%edx\nmov %rbx,%rdi\nxor %esi,%esi\nlea 0x4(%rbx,%rdx,4),%r9\nxchg %ax,%ax\nmov (%rdi),%ecx\ntest %ecx,%ecx\njs 1390 \nmovslq %esi,%r8\nadd $0x1,%esi\nmov %ecx,(%rax,%r8,4)\nadd $0x4,%rdi\ncmp %r9,%rdi\njne 1380 \npop %rbx\npop %rbp\nmov %esi,(%r12)\npop %r12\nretq\nnopw 0x0(%rax,%rax,1)\nxor %esi,%esi\npop %rbx\npop %rbp\nmov %esi,(%r12)\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r13\nmovsxd r8, esi\nmov r13, rdx\npush r12\nmov r12, r8\npush rbp\nlea rbp, ds:0[r8*4]\npush rbx\nmov rbx, rdi\nmov rdi, rbp; size\nsub rsp, 8\ncall _malloc\ntest r12d, r12d\njle short loc_1390\nmov rcx, rbx\nlea r8, [rbx+rbp]\nxor edi, edi\nnop dword ptr [rax+rax+00000000h]\nloc_1360:\nmov esi, [rcx]\ntest esi, esi\njs short loc_1370\nmovsxd r9, edi\nadd edi, 1\nmov [rax+r9*4], esi\nloc_1370:\nadd rcx, 4\ncmp rcx, r8\njnz short loc_1360\nmov [r13+0], edi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1390:\nxor edi, edi\nmov [r13+0], edi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(_DWORD *a1, int a2, _DWORD *a3)\n{\n _DWORD *result; // rax\n _DWORD *v6; // rcx\n int v7; // edi\n __int64 v8; // r9\n\n result = malloc(4LL * a2);\n if ( a2 <= 0 )\n {\n *a3 = 0;\n }\n else\n {\n v6 = a1;\n v7 = 0;\n do\n {\n if ( (int)*v6 >= 0 )\n {\n v8 = v7++;\n result[v8] = *v6;\n }\n ++v6;\n }\n while ( v6 != &a1[a2] );\n *a3 = v7;\n }\n return result;\n}", + "ida_strip_asm": "sub_1320:\nendbr64\npush r13\nmovsxd r8, esi\nmov r13, rdx\npush r12\nmov r12, r8\npush rbp\nlea rbp, ds:0[r8*4]\npush rbx\nmov rbx, rdi\nmov rdi, rbp; size\nsub rsp, 8\ncall _malloc\ntest r12d, r12d\njle short loc_1390\nmov rcx, rbx\nlea r8, [rbx+rbp]\nxor edi, edi\nnop dword ptr [rax+rax+00000000h]\nloc_1360:\nmov esi, [rcx]\ntest esi, esi\njs short loc_1370\nmovsxd r9, edi\nadd edi, 1\nmov [rax+r9*4], esi\nloc_1370:\nadd rcx, 4\ncmp rcx, r8\njnz short loc_1360\nmov [r13+0], edi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1390:\nxor edi, edi\nmov [r13+0], edi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1320(_DWORD *a1, int a2, _DWORD *a3)\n{\n _DWORD *result; // rax\n _DWORD *v6; // rcx\n int v7; // edi\n __int64 v8; // r9\n\n result = malloc(4LL * a2);\n if ( a2 <= 0 )\n {\n *a3 = 0;\n }\n else\n {\n v6 = a1;\n v7 = 0;\n do\n {\n if ( (int)*v6 >= 0 )\n {\n v8 = v7++;\n result[v8] = *v6;\n }\n ++v6;\n }\n while ( v6 != &a1[a2] );\n *a3 = v7;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1320(uint32_t *a1, int a2, uint32_t *a3) {\n uint32_t *result;\n uint32_t *v6;\n int v7;\n long long v8;\n result = malloc(4LL * a2);\n if (a2 <= 0) {\n *a3 = 0;\n } else {\n v6 = a1;\n v7 = 0;\n do {\n if ((int)*v6 >= 0) {\n v8 = v7++;\n result[v8] = *v6;\n }\n ++v6;\n } while (v6 != &a1[a2]);\n *a3 = v7;\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(uint32_t *a1, int a2, uint32_t *a3) {\n uint32_t *result;\n uint32_t *v6;\n int v7;\n long long v8;\n result = malloc(4LL * a2);\n if (a2 <= 0) {\n *a3 = 0;\n } else {\n v6 = a1;\n v7 = 0;\n do {\n if ((int)*v6 >= 0) {\n v8 = v7++;\n result[v8] = *v6;\n }\n ++v6;\n } while (v6 != &a1[a2]);\n *a3 = v7;\n }\n return result;\n}" + }, + { + "index": 852, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int* func0(int num_list[], int num_elems, int* result_size) {\n int* new_list = (int*)malloc(num_elems * sizeof(int));\n int j = 0;\n for (int i = 0; i < num_elems; i++) {\n if (num_list[i] >= 0) {\n new_list[j++] = num_list[i];\n }\n }\n *result_size = j;\n return new_list;\n}", + "test": "int main() {\n\n int size;\n\n\n\n int list1[] = {1, -2, 3, -4};\n\n int* result1 = func0(list1, 4, &size);\n\n assert(size == 2 && result1[0] == 1 && result1[1] == 3);\n\n free(result1);\n\n\n\n int list2[] = {1, 2, 3, -4};\n\n int* result2 = func0(list2, 4, &size);\n\n assert(size == 3 && result2[0] == 1 && result2[1] == 2 && result2[2] == 3);\n\n free(result2);\n\n\n\n int list3[] = {4, 5, -6, 7, -8};\n\n int* result3 = func0(list3, 5, &size);\n\n assert(size == 3 && result3[0] == 4 && result3[1] == 5 && result3[2] == 7);\n\n free(result3);\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %rdx,%r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nmovslq %esi,%rdi\nmov %rdi,%rbp\nshl $0x2,%rdi\ncallq 10b0 \ntest %ebp,%ebp\njle 1378 \nlea -0x1(%rbp),%edx\nmov %rbx,%rdi\nxor %esi,%esi\nlea 0x4(%rbx,%rdx,4),%r9\nxchg %ax,%ax\nmov (%rdi),%ecx\ntest %ecx,%ecx\njs 1360 \nmovslq %esi,%r8\nadd $0x1,%esi\nmov %ecx,(%rax,%r8,4)\nadd $0x4,%rdi\ncmp %r9,%rdi\njne 1350 \npop %rbx\npop %rbp\nmov %esi,(%r12)\npop %r12\nretq\nnopw 0x0(%rax,%rax,1)\nxor %esi,%esi\npop %rbx\npop %rbp\nmov %esi,(%r12)\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r13\nmovsxd r8, esi\nmov r13, rdx\npush r12\nmov r12, r8\npush rbp\nlea rbp, ds:0[r8*4]\npush rbx\nmov rbx, rdi\nmov rdi, rbp; size\nsub rsp, 8\ncall _malloc\ntest r12d, r12d\njle short loc_1390\nmov rcx, rbx\nlea r8, [rbx+rbp]\nxor edi, edi\nnop dword ptr [rax+rax+00000000h]\nloc_1360:\nmov esi, [rcx]\ntest esi, esi\njs short loc_1370\nmovsxd r9, edi\nadd edi, 1\nmov [rax+r9*4], esi\nloc_1370:\nadd rcx, 4\ncmp rcx, r8\njnz short loc_1360\nmov [r13+0], edi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1390:\nxor edi, edi\nmov [r13+0], edi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(_DWORD *a1, int a2, _DWORD *a3)\n{\n _DWORD *result; // rax\n _DWORD *v6; // rcx\n int v7; // edi\n __int64 v8; // r9\n\n result = malloc(4LL * a2);\n if ( a2 <= 0 )\n {\n *a3 = 0;\n }\n else\n {\n v6 = a1;\n v7 = 0;\n do\n {\n if ( (int)*v6 >= 0 )\n {\n v8 = v7++;\n result[v8] = *v6;\n }\n ++v6;\n }\n while ( v6 != &a1[a2] );\n *a3 = v7;\n }\n return result;\n}", + "ida_strip_asm": "sub_1320:\nendbr64\npush r13\nmovsxd r8, esi\nmov r13, rdx\npush r12\nmov r12, r8\npush rbp\nlea rbp, ds:0[r8*4]\npush rbx\nmov rbx, rdi\nmov rdi, rbp; size\nsub rsp, 8\ncall _malloc\ntest r12d, r12d\njle short loc_1390\nmov rcx, rbx\nlea r8, [rbx+rbp]\nxor edi, edi\nnop dword ptr [rax+rax+00000000h]\nloc_1360:\nmov esi, [rcx]\ntest esi, esi\njs short loc_1370\nmovsxd r9, edi\nadd edi, 1\nmov [rax+r9*4], esi\nloc_1370:\nadd rcx, 4\ncmp rcx, r8\njnz short loc_1360\nmov [r13+0], edi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1390:\nxor edi, edi\nmov [r13+0], edi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1320(_DWORD *a1, int a2, _DWORD *a3)\n{\n _DWORD *result; // rax\n _DWORD *v6; // rcx\n int v7; // edi\n __int64 v8; // r9\n\n result = malloc(4LL * a2);\n if ( a2 <= 0 )\n {\n *a3 = 0;\n }\n else\n {\n v6 = a1;\n v7 = 0;\n do\n {\n if ( (int)*v6 >= 0 )\n {\n v8 = v7++;\n result[v8] = *v6;\n }\n ++v6;\n }\n while ( v6 != &a1[a2] );\n *a3 = v7;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1320(uint32_t *a1, int a2, uint32_t *a3) {\n uint32_t *result;\n uint32_t *v6;\n int v7;\n long long v8;\n result = malloc(4LL * a2);\n if (a2 <= 0) {\n *a3 = 0;\n } else {\n v6 = a1;\n v7 = 0;\n do {\n if ((int)*v6 >= 0) {\n v8 = v7++;\n result[v8] = *v6;\n }\n ++v6;\n } while (v6 != &a1[a2]);\n *a3 = v7;\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(uint32_t *a1, int a2, uint32_t *a3) {\n uint32_t *result;\n uint32_t *v6;\n int v7;\n long long v8;\n result = malloc(4LL * a2);\n if (a2 <= 0) {\n *a3 = 0;\n } else {\n v6 = a1;\n v7 = 0;\n do {\n if ((int)*v6 >= 0) {\n v8 = v7++;\n result[v8] = *v6;\n }\n ++v6;\n } while (v6 != &a1[a2]);\n *a3 = v7;\n }\n return result;\n}" + }, + { + "index": 853, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int res = 1;\n while (n % 2 == 0) {\n n /= 2;\n }\n for (int i = 3; i <= sqrt(n) + 1; i += 2) {\n int count = 0;\n int curr_sum = 1;\n int curr_term = 1;\n while (n % i == 0) {\n count++;\n n /= i;\n curr_term *= i;\n curr_sum += curr_term;\n }\n res *= curr_sum;\n }\n if (n >= 2) {\n res *= (1 + n);\n }\n return res;\n}", + "test": "int main() {\n\n assert(func0(30) == 24);\n\n assert(func0(18) == 13);\n\n assert(func0(2) == 1);\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %edi,-0x24(%rbp)\nmovl $0x1,-0x14(%rbp)\njmp 11b0 \nmov -0x24(%rbp),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nmov %eax,-0x24(%rbp)\nmov -0x24(%rbp),%eax\nand $0x1,%eax\ntest %eax,%eax\nje 11a1 \nmovl $0x3,-0x10(%rbp)\njmp 1213 \nmovl $0x0,-0xc(%rbp)\nmovl $0x1,-0x8(%rbp)\nmovl $0x1,-0x4(%rbp)\njmp 11f8 \naddl $0x1,-0xc(%rbp)\nmov -0x24(%rbp),%eax\ncltd\nidivl -0x10(%rbp)\nmov %eax,-0x24(%rbp)\nmov -0x4(%rbp),%eax\nimul -0x10(%rbp),%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nadd %eax,-0x8(%rbp)\nmov -0x24(%rbp),%eax\ncltd\nidivl -0x10(%rbp)\nmov %edx,%eax\ntest %eax,%eax\nje 11da \nmov -0x14(%rbp),%eax\nimul -0x8(%rbp),%eax\nmov %eax,-0x14(%rbp)\naddl $0x2,-0x10(%rbp)\ncvtsi2sdl -0x10(%rbp),%xmm2\nmovsd %xmm2,-0x30(%rbp)\ncvtsi2sdl -0x24(%rbp),%xmm0\ncallq 1090 \nmovsd 0xe61(%rip),%xmm1\naddsd %xmm1,%xmm0\ncomisd -0x30(%rbp),%xmm0\njae 11c3 \ncmpl $0x1,-0x24(%rbp)\njle 124f \nmov -0x24(%rbp),%eax\nlea 0x1(%rax),%edx\nmov -0x14(%rbp),%eax\nimul %edx,%eax\nmov %eax,-0x14(%rbp)\nmov -0x14(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_24], edi\nmov [rbp+var_14], 1\njmp short loc_11B0\nloc_11A1:\nmov eax, [rbp+var_24]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_24], eax\nloc_11B0:\nmov eax, [rbp+var_24]\nand eax, 1\ntest eax, eax\njz short loc_11A1\nmov [rbp+var_10], 3\njmp short loc_1213\nloc_11C3:\nmov [rbp+var_C], 0\nmov [rbp+var_8], 1\nmov [rbp+var_4], 1\njmp short loc_11F8\nloc_11DA:\nadd [rbp+var_C], 1\nmov eax, [rbp+var_24]\ncdq\nidiv [rbp+var_10]\nmov [rbp+var_24], eax\nmov eax, [rbp+var_4]\nimul eax, [rbp+var_10]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\nadd [rbp+var_8], eax\nloc_11F8:\nmov eax, [rbp+var_24]\ncdq\nidiv [rbp+var_10]\nmov eax, edx\ntest eax, eax\njz short loc_11DA\nmov eax, [rbp+var_14]\nimul eax, [rbp+var_8]\nmov [rbp+var_14], eax\nadd [rbp+var_10], 2\nloc_1213:\npxor xmm2, xmm2\ncvtsi2sd xmm2, [rbp+var_10]\nmovsd [rbp+var_30], xmm2\npxor xmm3, xmm3\ncvtsi2sd xmm3, [rbp+var_24]\nmovq rax, xmm3\nmovq xmm0, rax; x\ncall _sqrt\nmovsd xmm1, cs:qword_2078\naddsd xmm0, xmm1\ncomisd xmm0, [rbp+var_30]\njnb loc_11C3\ncmp [rbp+var_24], 1\njle short loc_1265\nmov eax, [rbp+var_24]\nlea edx, [rax+1]\nmov eax, [rbp+var_14]\nimul eax, edx\nmov [rbp+var_14], eax\nloc_1265:\nmov eax, [rbp+var_14]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v3; // [rsp+1Ch] [rbp-14h]\n int i; // [rsp+20h] [rbp-10h]\n int v5; // [rsp+24h] [rbp-Ch]\n int v6; // [rsp+28h] [rbp-8h]\n int v7; // [rsp+2Ch] [rbp-4h]\n\n v3 = 1;\n while ( (a1 & 1) == 0 )\n a1 /= 2;\n for ( i = 3; sqrt((double)a1) + 1.0 >= (double)i; i += 2 )\n {\n v5 = 0;\n v6 = 1;\n v7 = 1;\n while ( !(a1 % i) )\n {\n ++v5;\n a1 /= i;\n v7 *= i;\n v6 += v7;\n }\n v3 *= v6;\n }\n if ( a1 > 1 )\n v3 *= a1 + 1;\n return v3;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_24], edi\nmov [rbp+var_14], 1\njmp short loc_11B0\nloc_11A1:\nmov eax, [rbp+var_24]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_24], eax\nloc_11B0:\nmov eax, [rbp+var_24]\nand eax, 1\ntest eax, eax\njz short loc_11A1\nmov [rbp+var_10], 3\njmp short loc_1213\nloc_11C3:\nmov [rbp+var_C], 0\nmov [rbp+var_8], 1\nmov [rbp+var_4], 1\njmp short loc_11F8\nloc_11DA:\nadd [rbp+var_C], 1\nmov eax, [rbp+var_24]\ncdq\nidiv [rbp+var_10]\nmov [rbp+var_24], eax\nmov eax, [rbp+var_4]\nimul eax, [rbp+var_10]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\nadd [rbp+var_8], eax\nloc_11F8:\nmov eax, [rbp+var_24]\ncdq\nidiv [rbp+var_10]\nmov eax, edx\ntest eax, eax\njz short loc_11DA\nmov eax, [rbp+var_14]\nimul eax, [rbp+var_8]\nmov [rbp+var_14], eax\nadd [rbp+var_10], 2\nloc_1213:\npxor xmm2, xmm2\ncvtsi2sd xmm2, [rbp+var_10]\nmovsd [rbp+var_30], xmm2\npxor xmm3, xmm3\ncvtsi2sd xmm3, [rbp+var_24]\nmovq rax, xmm3\nmovq xmm0, rax; x\ncall _sqrt\nmovsd xmm1, cs:qword_2078\naddsd xmm0, xmm1\ncomisd xmm0, [rbp+var_30]\njnb loc_11C3\ncmp [rbp+var_24], 1\njle short loc_1265\nmov eax, [rbp+var_24]\nlea edx, [rax+1]\nmov eax, [rbp+var_14]\nimul eax, edx\nmov [rbp+var_14], eax\nloc_1265:\nmov eax, [rbp+var_14]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(int a1)\n{\n unsigned int v3; // [rsp+1Ch] [rbp-14h]\n int i; // [rsp+20h] [rbp-10h]\n int v5; // [rsp+24h] [rbp-Ch]\n int v6; // [rsp+28h] [rbp-8h]\n int v7; // [rsp+2Ch] [rbp-4h]\n\n v3 = 1;\n while ( (a1 & 1) == 0 )\n a1 /= 2;\n for ( i = 3; sqrt((double)a1) + 1.0 >= (double)i; i += 2 )\n {\n v5 = 0;\n v6 = 1;\n v7 = 1;\n while ( !(a1 % i) )\n {\n ++v5;\n a1 /= i;\n v7 *= i;\n v6 += v7;\n }\n v3 *= v6;\n }\n if ( a1 > 1 )\n v3 *= a1 + 1;\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(int a1) {\n unsigned int v3;\n int i;\n int v5;\n int v6;\n int v7;\n v3 = 1;\n while ((a1 & 1) == 0) a1 /= 2;\n for (i = 3; sqrt((double)a1) + 1.0 >= (double)i; i += 2) {\n v5 = 0;\n v6 = 1;\n v7 = 1;\n while (!(a1 % i)) {\n ++v5;\n a1 /= i;\n v7 *= i;\n v6 += v7;\n }\n v3 *= v6;\n }\n if (a1 > 1) v3 *= a1 + 1;\n return v3;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v3;\n int i;\n int v5;\n int v6;\n int v7;\n v3 = 1;\n while ((a1 & 1) == 0) a1 /= 2;\n for (i = 3; sqrt((double)a1) + 1.0 >= (double)i; i += 2) {\n v5 = 0;\n v6 = 1;\n v7 = 1;\n while (!(a1 % i)) {\n ++v5;\n a1 /= i;\n v7 *= i;\n v6 += v7;\n }\n v3 *= v6;\n }\n if (a1 > 1) v3 *= a1 + 1;\n return v3;\n}" + }, + { + "index": 853, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int res = 1;\n while (n % 2 == 0) {\n n /= 2;\n }\n for (int i = 3; i <= sqrt(n) + 1; i += 2) {\n int count = 0;\n int curr_sum = 1;\n int curr_term = 1;\n while (n % i == 0) {\n count++;\n n /= i;\n curr_term *= i;\n curr_sum += curr_term;\n }\n res *= curr_sum;\n }\n if (n >= 2) {\n res *= (1 + n);\n }\n return res;\n}", + "test": "int main() {\n\n assert(func0(30) == 24);\n\n assert(func0(18) == 13);\n\n assert(func0(2) == 1);\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nsub $0x10,%rsp\nmov %edi,%ebx\ntest $0x1,%dil\njne 11ae \nmov %ebx,%edi\nshr $0x1f,%edi\nadd %ebx,%edi\nsar %edi\nmov %edi,%ebx\ntest $0x1,%dil\nje 119d \nmov $0x3,%ebp\nmov $0x1,%r12d\njmp 11d5 \nmov %ebx,%eax\ncltd\nidiv %ebp\nmov %eax,%ebx\nimul %ebp,%ecx\nadd %ecx,%esi\ncltd\nidiv %ebp\ntest %edx,%edx\nje 11bb \nimul %esi,%r12d\nadd $0x2,%ebp\npxor %xmm2,%xmm2\ncvtsi2sd %ebp,%xmm2\nmovsd %xmm2,(%rsp)\npxor %xmm0,%xmm0\ncvtsi2sd %ebx,%xmm0\nmovapd %xmm0,%xmm1\nsqrtsd %xmm1,%xmm1\nmovsd %xmm1,0x8(%rsp)\npxor %xmm3,%xmm3\nucomisd %xmm0,%xmm3\nja 122c \nmovsd 0xe86(%rip),%xmm0\naddsd 0x8(%rsp),%xmm0\ncomisd (%rsp),%xmm0\njb 1233 \nmov %ebx,%eax\ncltd\nidiv %ebp\nmov $0x1,%ecx\nmov $0x1,%esi\ntest %edx,%edx\nje 11bb \njmp 11ce \ncallq 1090 \njmp 1202 \ncmp $0x1,%ebx\njle 123f \nadd $0x1,%ebx\nimul %ebx,%r12d\nmov %r12d,%eax\nadd $0x10,%rsp\npop %rbx\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 10h\nmov ebx, edi\ntest dil, 1\njnz short loc_11AC\nloc_119D:\nmov eax, ebx\nshr eax, 1Fh\nadd eax, ebx\nsar eax, 1\nmov ebx, eax\ntest al, 1\njz short loc_119D\nloc_11AC:\nmov ebp, 3\nmov r12d, 1\njmp short loc_11D3\nloc_11B9:\nmov eax, ebx\ncdq\nidiv ebp\nmov ebx, eax\nimul ecx, ebp\nadd esi, ecx\ncdq\nidiv ebp\ntest edx, edx\njz short loc_11B9\nloc_11CC:\nimul r12d, esi\nadd ebp, 2\nloc_11D3:\npxor xmm2, xmm2\ncvtsi2sd xmm2, ebp\nmovsd [rsp+28h+var_20], xmm2\npxor xmm0, xmm0\ncvtsi2sd xmm0, ebx; x\npxor xmm1, xmm1\nucomisd xmm1, xmm0\nja short loc_121C\nsqrtsd xmm0, xmm0\nloc_11F7:\naddsd xmm0, cs:qword_2078\ncomisd xmm0, [rsp+28h+var_20]\njb short loc_1223\nmov eax, ebx\ncdq\nidiv ebp\nmov ecx, 1\nmov esi, 1\ntest edx, edx\njz short loc_11B9\njmp short loc_11CC\nloc_121C:\ncall _sqrt\njmp short loc_11F7\nloc_1223:\ncmp ebx, 1\njle short loc_122F\nadd ebx, 1\nimul r12d, ebx\nloc_122F:\nmov eax, r12d\nadd rsp, 10h\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int i; // ebx\n int v2; // ebp\n unsigned int v3; // r12d\n int v4; // ecx\n int j; // esi\n double v6; // xmm0_8\n double v7; // xmm0_8\n\n for ( i = a1; (i & 1) == 0; i /= 2 )\n ;\n v2 = 3;\n v3 = 1;\n while ( 1 )\n {\n v6 = (double)i;\n v7 = (double)i < 0.0 ? sqrt(v6) : sqrt(v6);\n if ( v7 + 1.0 < (double)v2 )\n break;\n v4 = 1;\n for ( j = 1; !(i % v2); j += v4 )\n {\n i /= v2;\n v4 *= v2;\n }\n v3 *= j;\n v2 += 2;\n }\n if ( i > 1 )\n v3 *= i + 1;\n return v3;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 10h\nmov ebx, edi\ntest dil, 1\njnz short loc_11AC\nloc_119D:\nmov eax, ebx\nshr eax, 1Fh\nadd eax, ebx\nsar eax, 1\nmov ebx, eax\ntest al, 1\njz short loc_119D\nloc_11AC:\nmov ebp, 3\nmov r12d, 1\njmp short loc_11D3\nloc_11B9:\nmov eax, ebx\ncdq\nidiv ebp\nmov ebx, eax\nimul ecx, ebp\nadd esi, ecx\ncdq\nidiv ebp\ntest edx, edx\njz short loc_11B9\nloc_11CC:\nimul r12d, esi\nadd ebp, 2\nloc_11D3:\npxor xmm2, xmm2\ncvtsi2sd xmm2, ebp\nmovsd [rsp+28h+var_20], xmm2\npxor xmm0, xmm0\ncvtsi2sd xmm0, ebx; x\npxor xmm1, xmm1\nucomisd xmm1, xmm0\nja short loc_121C\nsqrtsd xmm0, xmm0\nloc_11F7:\naddsd xmm0, cs:qword_2078\ncomisd xmm0, [rsp+28h+var_20]\njb short loc_1223\nmov eax, ebx\ncdq\nidiv ebp\nmov ecx, 1\nmov esi, 1\ntest edx, edx\njz short loc_11B9\njmp short loc_11CC\nloc_121C:\ncall _sqrt\njmp short loc_11F7\nloc_1223:\ncmp ebx, 1\njle short loc_122F\nadd ebx, 1\nimul r12d, ebx\nloc_122F:\nmov eax, r12d\nadd rsp, 10h\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(int a1)\n{\n int i; // ebx\n int v2; // ebp\n unsigned int v3; // r12d\n int v4; // ecx\n int j; // esi\n double v6; // xmm0_8\n double v7; // xmm0_8\n\n for ( i = a1; (i & 1) == 0; i /= 2 )\n ;\n v2 = 3;\n v3 = 1;\n while ( 1 )\n {\n v6 = (double)i;\n v7 = (double)i < 0.0 ? sqrt(v6) : sqrt(v6);\n if ( v7 + 1.0 < (double)v2 )\n break;\n v4 = 1;\n for ( j = 1; !(i % v2); j += v4 )\n {\n i /= v2;\n v4 *= v2;\n }\n v3 *= j;\n v2 += 2;\n }\n if ( i > 1 )\n v3 *= i + 1;\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(int a1) {\n int i;\n int v2;\n unsigned int v3;\n int v4;\n int j;\n double v6;\n double v7;\n for (i = a1; (i & 1) == 0; i /= 2)\n ;\n v2 = 3;\n v3 = 1;\n while (1) {\n v6 = (double)i;\n v7 = (double)i < 0.0 ? sqrt(v6) : sqrt(v6);\n if (v7 + 1.0 < (double)v2) break;\n v4 = 1;\n for (j = 1; !(i % v2); j += v4) {\n i /= v2;\n v4 *= v2;\n }\n v3 *= j;\n v2 += 2;\n }\n if (i > 1) v3 *= i + 1;\n return v3;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int i;\n int v2;\n unsigned int v3;\n int v4;\n int j;\n double v6;\n double v7;\n for (i = a1; (i & 1) == 0; i /= 2)\n ;\n v2 = 3;\n v3 = 1;\n while (1) {\n v6 = (double)i;\n v7 = (double)i < 0.0 ? sqrt(v6) : sqrt(v6);\n if (v7 + 1.0 < (double)v2) break;\n v4 = 1;\n for (j = 1; !(i % v2); j += v4) {\n i /= v2;\n v4 *= v2;\n }\n v3 *= j;\n v2 += 2;\n }\n if (i > 1) v3 *= i + 1;\n return v3;\n}" + }, + { + "index": 853, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int res = 1;\n while (n % 2 == 0) {\n n /= 2;\n }\n for (int i = 3; i <= sqrt(n) + 1; i += 2) {\n int count = 0;\n int curr_sum = 1;\n int curr_term = 1;\n while (n % i == 0) {\n count++;\n n /= i;\n curr_term *= i;\n curr_sum += curr_term;\n }\n res *= curr_sum;\n }\n if (n >= 2) {\n res *= (1 + n);\n }\n return res;\n}", + "test": "int main() {\n\n assert(func0(30) == 24);\n\n assert(func0(18) == 13);\n\n assert(func0(2) == 1);\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbx\nsub $0x28,%rsp\ntest $0x1,%dil\njne 1267 \nnopl 0x0(%rax)\nmov %edi,%eax\nshr $0x1f,%eax\nadd %edi,%eax\nmov %eax,%edi\nsar %edi\ntest $0x2,%al\nje 1258 \npxor %xmm2,%xmm2\nmov $0x3,%ebx\nmov $0x1,%r12d\nmovsd 0xe12(%rip),%xmm4\ncvtsi2sd %edi,%xmm2\npxor %xmm5,%xmm5\nnopw %cs:0x0(%rax,%rax,1)\nucomisd %xmm2,%xmm5\npxor %xmm3,%xmm3\nmovapd %xmm2,%xmm1\ncvtsi2sd %ebx,%xmm3\nsqrtsd %xmm1,%xmm1\nja 1307 \naddsd %xmm4,%xmm1\ncomisd %xmm3,%xmm1\njb 12f0 \nmov %edi,%eax\nmov $0x1,%ecx\nmov $0x1,%esi\ncltd\nidiv %ebx\ntest %edx,%edx\njne 12e7 \nnopl 0x0(%rax,%rax,1)\nmov %edi,%eax\nimul %ebx,%ecx\ncltd\nidiv %ebx\nadd %ecx,%esi\ncltd\nmov %eax,%edi\nidiv %ebx\ntest %edx,%edx\nje 12c8 \npxor %xmm2,%xmm2\nimul %esi,%r12d\ncvtsi2sd %edi,%xmm2\nadd $0x2,%ebx\njmp 1290 \nnopl 0x0(%rax)\ncmp $0x1,%edi\njle 12fc \nadd $0x1,%edi\nimul %edi,%r12d\nadd $0x28,%rsp\nmov %r12d,%eax\npop %rbx\npop %r12\nretq\nmovapd %xmm2,%xmm0\nmov %edi,0x1c(%rsp)\nmovsd %xmm1,0x10(%rsp)\nmovsd %xmm3,0x8(%rsp)\nmovsd %xmm2,(%rsp)\ncallq 1090 \nmov 0xd64(%rip),%rax\nmov 0x1c(%rsp),%edi\npxor %xmm5,%xmm5\nmovsd 0x10(%rsp),%xmm1\nmovsd 0x8(%rsp),%xmm3\nmovsd (%rsp),%xmm2\nmovq %rax,%xmm4\njmpq 12a6 \n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 20h\ntest dil, 1\njnz short loc_1267\nnop word ptr [rax+rax+00h]\nloc_1258:\nmov eax, edi\nshr eax, 1Fh\nadd eax, edi\nmov edi, eax\nsar edi, 1\ntest al, 2\njz short loc_1258\nloc_1267:\npxor xmm1, xmm1\nmov ebp, 3\nmov r12d, 1\nmovsd xmm4, cs:qword_2078\ncvtsi2sd xmm1, edi\npxor xmm3, xmm3\nnop word ptr [rax+rax+00000000h]\nloc_1290:\nucomisd xmm3, xmm1\npxor xmm2, xmm2\ncvtsi2sd xmm2, ebp\nja short loc_1308\nmovapd xmm0, xmm1\nsqrtsd xmm0, xmm0\nloc_12A6:\naddsd xmm0, xmm4\ncomisd xmm0, xmm2\njb short loc_12F0\nmov eax, edi\nmov ecx, 1\nmov esi, 1\ncdq\nidiv ebp\ntest edx, edx\njnz short loc_12E7\nnop dword ptr [rax+rax+00h]\nloc_12C8:\nmov eax, edi\nimul ecx, ebp\ncdq\nidiv ebp\nadd esi, ecx\ncdq\nmov edi, eax\nidiv ebp\ntest edx, edx\njz short loc_12C8\npxor xmm1, xmm1\nimul r12d, esi\ncvtsi2sd xmm1, edi\nloc_12E7:\nadd ebp, 2\njmp short loc_1290\nloc_12F0:\ncmp edi, 1\njle short loc_12FC\nlea ebx, [rdi+1]\nimul r12d, ebx\nloc_12FC:\nadd rsp, 20h\nmov eax, r12d\npop rbx\npop rbp\npop r12\nretn\nloc_1308:\nmovapd xmm0, xmm1; x\nmov [rsp+38h+var_1C], edi\nmovsd [rsp+38h+var_28], xmm2\nmovsd [rsp+38h+var_30], xmm1\ncall _sqrt\nmov edi, [rsp+38h+var_1C]\npxor xmm3, xmm3\nmovsd xmm4, cs:qword_2078\nmovsd xmm2, [rsp+38h+var_28]\nmovsd xmm1, [rsp+38h+var_30]\njmp loc_12A6", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v1; // eax\n int v2; // ebp\n unsigned int v3; // r12d\n double v4; // xmm1_8\n double v5; // xmm2_8\n double v6; // xmm0_8\n int v7; // ecx\n int v8; // esi\n int v9; // edx\n\n if ( (a1 & 1) == 0 )\n {\n do\n {\n v1 = a1 + ((unsigned int)a1 >> 31);\n a1 /= 2;\n }\n while ( (v1 & 2) == 0 );\n }\n v2 = 3;\n v3 = 1;\n v4 = (double)a1;\n while ( 1 )\n {\n v5 = (double)v2;\n if ( v4 < 0.0 )\n {\n v6 = sqrt(v4);\n v5 = (double)v2;\n }\n else\n {\n v6 = sqrt(v4);\n }\n if ( v6 + 1.0 < v5 )\n break;\n v7 = 1;\n v8 = 1;\n if ( !(a1 % v2) )\n {\n do\n {\n v7 *= v2;\n v8 += v7;\n v9 = (a1 / v2) >> 31;\n a1 /= v2;\n }\n while ( !(unsigned int)(__SPAIR64__(v9, a1) % v2) );\n v3 *= v8;\n v4 = (double)a1;\n }\n v2 += 2;\n }\n if ( a1 > 1 )\n v3 *= a1 + 1;\n return v3;\n}", + "ida_strip_asm": "sub_1240:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 20h\ntest dil, 1\njnz short loc_1267\nnop word ptr [rax+rax+00h]\nloc_1258:\nmov eax, edi\nshr eax, 1Fh\nadd eax, edi\nmov edi, eax\nsar edi, 1\ntest al, 2\njz short loc_1258\nloc_1267:\npxor xmm1, xmm1\nmov ebp, 3\nmov r12d, 1\nmovsd xmm4, cs:qword_2078\ncvtsi2sd xmm1, edi\npxor xmm3, xmm3\nnop word ptr [rax+rax+00000000h]\nloc_1290:\nucomisd xmm3, xmm1\npxor xmm2, xmm2\ncvtsi2sd xmm2, ebp\nja short loc_1308\nmovapd xmm0, xmm1\nsqrtsd xmm0, xmm0\nloc_12A6:\naddsd xmm0, xmm4\ncomisd xmm0, xmm2\njb short loc_12F0\nmov eax, edi\nmov ecx, 1\nmov esi, 1\ncdq\nidiv ebp\ntest edx, edx\njnz short loc_12E7\nnop dword ptr [rax+rax+00h]\nloc_12C8:\nmov eax, edi\nimul ecx, ebp\ncdq\nidiv ebp\nadd esi, ecx\ncdq\nmov edi, eax\nidiv ebp\ntest edx, edx\njz short loc_12C8\npxor xmm1, xmm1\nimul r12d, esi\ncvtsi2sd xmm1, edi\nloc_12E7:\nadd ebp, 2\njmp short loc_1290\nloc_12F0:\ncmp edi, 1\njle short loc_12FC\nlea ebx, [rdi+1]\nimul r12d, ebx\nloc_12FC:\nadd rsp, 20h\nmov eax, r12d\npop rbx\npop rbp\npop r12\nretn\nloc_1308:\nmovapd xmm0, xmm1; x\nmov [rsp+38h+var_1C], edi\nmovsd [rsp+38h+var_28], xmm2\nmovsd [rsp+38h+var_30], xmm1\ncall _sqrt\nmov edi, [rsp+38h+var_1C]\npxor xmm3, xmm3\nmovsd xmm4, cs:qword_2078\nmovsd xmm2, [rsp+38h+var_28]\nmovsd xmm1, [rsp+38h+var_30]\njmp loc_12A6", + "ida_strip_pseudo": "__int64 __fastcall sub_1240(int a1)\n{\n unsigned int v1; // eax\n int v2; // ebp\n unsigned int v3; // r12d\n double v4; // xmm1_8\n double v5; // xmm2_8\n double v6; // xmm0_8\n int v7; // ecx\n int v8; // esi\n int v9; // edx\n\n if ( (a1 & 1) == 0 )\n {\n do\n {\n v1 = a1 + ((unsigned int)a1 >> 31);\n a1 /= 2;\n }\n while ( (v1 & 2) == 0 );\n }\n v2 = 3;\n v3 = 1;\n v4 = (double)a1;\n while ( 1 )\n {\n v5 = (double)v2;\n if ( v4 < 0.0 )\n {\n v6 = sqrt(v4);\n v5 = (double)v2;\n }\n else\n {\n v6 = sqrt(v4);\n }\n if ( v6 + 1.0 < v5 )\n break;\n v7 = 1;\n v8 = 1;\n if ( !(a1 % v2) )\n {\n do\n {\n v7 *= v2;\n v8 += v7;\n v9 = (a1 / v2) >> 31;\n a1 /= v2;\n }\n while ( !(unsigned int)(__SPAIR64__(v9, a1) % v2) );\n v3 *= v8;\n v4 = (double)a1;\n }\n v2 += 2;\n }\n if ( a1 > 1 )\n v3 *= a1 + 1;\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1240(int a1) {\n unsigned int v1;\n int v2;\n unsigned int v3;\n double v4;\n double v5;\n double v6;\n int v7;\n int v8;\n int v9;\n if ((a1 & 1) == 0) {\n do {\n v1 = a1 + ((unsigned int)a1 >> 31);\n a1 /= 2;\n } while ((v1 & 2) == 0);\n }\n v2 = 3;\n v3 = 1;\n v4 = (double)a1;\n while (1) {\n v5 = (double)v2;\n if (v4 < 0.0) {\n v6 = sqrt(v4);\n v5 = (double)v2;\n } else {\n v6 = sqrt(v4);\n }\n if (v6 + 1.0 < v5) break;\n v7 = 1;\n v8 = 1;\n if (!(a1 % v2)) {\n do {\n v7 *= v2;\n v8 += v7;\n v9 = (a1 / v2) >> 31;\n a1 /= v2;\n } while (!(unsigned int)(__SPAIR64__(v9, a1) % v2));\n v3 *= v8;\n v4 = (double)a1;\n }\n v2 += 2;\n }\n if (a1 > 1) v3 *= a1 + 1;\n return v3;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v1;\n int v2;\n unsigned int v3;\n double v4;\n double v5;\n double v6;\n int v7;\n int v8;\n int v9;\n if ((a1 & 1) == 0) {\n do {\n v1 = a1 + ((unsigned int)a1 >> 31);\n a1 /= 2;\n } while ((v1 & 2) == 0);\n }\n v2 = 3;\n v3 = 1;\n v4 = (double)a1;\n while (1) {\n v5 = (double)v2;\n if (v4 < 0.0) {\n v6 = sqrt(v4);\n v5 = (double)v2;\n } else {\n v6 = sqrt(v4);\n }\n if (v6 + 1.0 < v5) break;\n v7 = 1;\n v8 = 1;\n if (!(a1 % v2)) {\n do {\n v7 *= v2;\n v8 += v7;\n v9 = (a1 / v2) >> 31;\n a1 /= v2;\n } while (!(unsigned int)(__SPAIR64__(v9, a1) % v2));\n v3 *= v8;\n v4 = (double)a1;\n }\n v2 += 2;\n }\n if (a1 > 1) v3 *= a1 + 1;\n return v3;\n}" + }, + { + "index": 853, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int res = 1;\n while (n % 2 == 0) {\n n /= 2;\n }\n for (int i = 3; i <= sqrt(n) + 1; i += 2) {\n int count = 0;\n int curr_sum = 1;\n int curr_term = 1;\n while (n % i == 0) {\n count++;\n n /= i;\n curr_term *= i;\n curr_sum += curr_term;\n }\n res *= curr_sum;\n }\n if (n >= 2) {\n res *= (1 + n);\n }\n return res;\n}", + "test": "int main() {\n\n assert(func0(30) == 24);\n\n assert(func0(18) == 13);\n\n assert(func0(2) == 1);\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbx\nsub $0x28,%rsp\ntest $0x1,%dil\njne 1267 \nnopl 0x0(%rax)\nmov %edi,%eax\nshr $0x1f,%eax\nadd %edi,%eax\nmov %eax,%edi\nsar %edi\ntest $0x2,%al\nje 1258 \npxor %xmm2,%xmm2\nmov $0x3,%ebx\nmov $0x1,%r12d\nmovsd 0xe12(%rip),%xmm4\ncvtsi2sd %edi,%xmm2\npxor %xmm5,%xmm5\nnopw %cs:0x0(%rax,%rax,1)\nucomisd %xmm2,%xmm5\npxor %xmm3,%xmm3\nmovapd %xmm2,%xmm1\ncvtsi2sd %ebx,%xmm3\nsqrtsd %xmm1,%xmm1\nja 1307 \naddsd %xmm4,%xmm1\ncomisd %xmm3,%xmm1\njb 12f0 \nmov %edi,%eax\nmov $0x1,%ecx\nmov $0x1,%esi\ncltd\nidiv %ebx\ntest %edx,%edx\njne 12e7 \nnopl 0x0(%rax,%rax,1)\nmov %edi,%eax\nimul %ebx,%ecx\ncltd\nidiv %ebx\nadd %ecx,%esi\ncltd\nmov %eax,%edi\nidiv %ebx\ntest %edx,%edx\nje 12c8 \npxor %xmm2,%xmm2\nimul %esi,%r12d\ncvtsi2sd %edi,%xmm2\nadd $0x2,%ebx\njmp 1290 \nnopl 0x0(%rax)\ncmp $0x1,%edi\njle 12fc \nadd $0x1,%edi\nimul %edi,%r12d\nadd $0x28,%rsp\nmov %r12d,%eax\npop %rbx\npop %r12\nretq\nmovapd %xmm2,%xmm0\nmov %edi,0x1c(%rsp)\nmovsd %xmm1,0x10(%rsp)\nmovsd %xmm3,0x8(%rsp)\nmovsd %xmm2,(%rsp)\ncallq 1090 \nmov 0xd64(%rip),%rax\nmov 0x1c(%rsp),%edi\npxor %xmm5,%xmm5\nmovsd 0x10(%rsp),%xmm1\nmovsd 0x8(%rsp),%xmm3\nmovsd (%rsp),%xmm2\nmovq %rax,%xmm4\njmpq 12a6 \n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 20h\ntest dil, 1\njnz short loc_1267\nnop word ptr [rax+rax+00h]\nloc_1258:\nmov eax, edi\nshr eax, 1Fh\nadd eax, edi\nmov edi, eax\nsar edi, 1\ntest al, 2\njz short loc_1258\nloc_1267:\npxor xmm1, xmm1\nmov ebp, 3\nmov r12d, 1\nmovsd xmm4, cs:qword_2078\ncvtsi2sd xmm1, edi\npxor xmm3, xmm3\nnop word ptr [rax+rax+00000000h]\nloc_1290:\nucomisd xmm3, xmm1\npxor xmm2, xmm2\ncvtsi2sd xmm2, ebp\nja short loc_1308\nmovapd xmm0, xmm1\nsqrtsd xmm0, xmm0\nloc_12A6:\naddsd xmm0, xmm4\ncomisd xmm0, xmm2\njb short loc_12F0\nmov eax, edi\nmov ecx, 1\nmov esi, 1\ncdq\nidiv ebp\ntest edx, edx\njnz short loc_12E7\nnop dword ptr [rax+rax+00h]\nloc_12C8:\nmov eax, edi\nimul ecx, ebp\ncdq\nidiv ebp\nadd esi, ecx\ncdq\nmov edi, eax\nidiv ebp\ntest edx, edx\njz short loc_12C8\npxor xmm1, xmm1\nimul r12d, esi\ncvtsi2sd xmm1, edi\nloc_12E7:\nadd ebp, 2\njmp short loc_1290\nloc_12F0:\ncmp edi, 1\njle short loc_12FC\nlea ebx, [rdi+1]\nimul r12d, ebx\nloc_12FC:\nadd rsp, 20h\nmov eax, r12d\npop rbx\npop rbp\npop r12\nretn\nloc_1308:\nmovapd xmm0, xmm1; x\nmov [rsp+38h+var_1C], edi\nmovsd [rsp+38h+var_28], xmm2\nmovsd [rsp+38h+var_30], xmm1\ncall _sqrt\nmov edi, [rsp+38h+var_1C]\npxor xmm3, xmm3\nmovsd xmm4, cs:qword_2078\nmovsd xmm2, [rsp+38h+var_28]\nmovsd xmm1, [rsp+38h+var_30]\njmp loc_12A6", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v1; // eax\n int v2; // ebp\n unsigned int v3; // r12d\n double v4; // xmm1_8\n double v5; // xmm2_8\n double v6; // xmm0_8\n int v7; // ecx\n int v8; // esi\n int v9; // edx\n\n if ( (a1 & 1) == 0 )\n {\n do\n {\n v1 = a1 + ((unsigned int)a1 >> 31);\n a1 /= 2;\n }\n while ( (v1 & 2) == 0 );\n }\n v2 = 3;\n v3 = 1;\n v4 = (double)a1;\n while ( 1 )\n {\n v5 = (double)v2;\n if ( v4 < 0.0 )\n {\n v6 = sqrt(v4);\n v5 = (double)v2;\n }\n else\n {\n v6 = sqrt(v4);\n }\n if ( v6 + 1.0 < v5 )\n break;\n v7 = 1;\n v8 = 1;\n if ( !(a1 % v2) )\n {\n do\n {\n v7 *= v2;\n v8 += v7;\n v9 = (a1 / v2) >> 31;\n a1 /= v2;\n }\n while ( !(unsigned int)(__SPAIR64__(v9, a1) % v2) );\n v3 *= v8;\n v4 = (double)a1;\n }\n v2 += 2;\n }\n if ( a1 > 1 )\n v3 *= a1 + 1;\n return v3;\n}", + "ida_strip_asm": "sub_1240:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 20h\ntest dil, 1\njnz short loc_1267\nnop word ptr [rax+rax+00h]\nloc_1258:\nmov eax, edi\nshr eax, 1Fh\nadd eax, edi\nmov edi, eax\nsar edi, 1\ntest al, 2\njz short loc_1258\nloc_1267:\npxor xmm1, xmm1\nmov ebp, 3\nmov r12d, 1\nmovsd xmm4, cs:qword_2078\ncvtsi2sd xmm1, edi\npxor xmm3, xmm3\nnop word ptr [rax+rax+00000000h]\nloc_1290:\nucomisd xmm3, xmm1\npxor xmm2, xmm2\ncvtsi2sd xmm2, ebp\nja short loc_1308\nmovapd xmm0, xmm1\nsqrtsd xmm0, xmm0\nloc_12A6:\naddsd xmm0, xmm4\ncomisd xmm0, xmm2\njb short loc_12F0\nmov eax, edi\nmov ecx, 1\nmov esi, 1\ncdq\nidiv ebp\ntest edx, edx\njnz short loc_12E7\nnop dword ptr [rax+rax+00h]\nloc_12C8:\nmov eax, edi\nimul ecx, ebp\ncdq\nidiv ebp\nadd esi, ecx\ncdq\nmov edi, eax\nidiv ebp\ntest edx, edx\njz short loc_12C8\npxor xmm1, xmm1\nimul r12d, esi\ncvtsi2sd xmm1, edi\nloc_12E7:\nadd ebp, 2\njmp short loc_1290\nloc_12F0:\ncmp edi, 1\njle short loc_12FC\nlea ebx, [rdi+1]\nimul r12d, ebx\nloc_12FC:\nadd rsp, 20h\nmov eax, r12d\npop rbx\npop rbp\npop r12\nretn\nloc_1308:\nmovapd xmm0, xmm1; x\nmov [rsp+38h+var_1C], edi\nmovsd [rsp+38h+var_28], xmm2\nmovsd [rsp+38h+var_30], xmm1\ncall _sqrt\nmov edi, [rsp+38h+var_1C]\npxor xmm3, xmm3\nmovsd xmm4, cs:qword_2078\nmovsd xmm2, [rsp+38h+var_28]\nmovsd xmm1, [rsp+38h+var_30]\njmp loc_12A6", + "ida_strip_pseudo": "__int64 __fastcall sub_1240(int a1)\n{\n unsigned int v1; // eax\n int v2; // ebp\n unsigned int v3; // r12d\n double v4; // xmm1_8\n double v5; // xmm2_8\n double v6; // xmm0_8\n int v7; // ecx\n int v8; // esi\n int v9; // edx\n\n if ( (a1 & 1) == 0 )\n {\n do\n {\n v1 = a1 + ((unsigned int)a1 >> 31);\n a1 /= 2;\n }\n while ( (v1 & 2) == 0 );\n }\n v2 = 3;\n v3 = 1;\n v4 = (double)a1;\n while ( 1 )\n {\n v5 = (double)v2;\n if ( v4 < 0.0 )\n {\n v6 = sqrt(v4);\n v5 = (double)v2;\n }\n else\n {\n v6 = sqrt(v4);\n }\n if ( v6 + 1.0 < v5 )\n break;\n v7 = 1;\n v8 = 1;\n if ( !(a1 % v2) )\n {\n do\n {\n v7 *= v2;\n v8 += v7;\n v9 = (a1 / v2) >> 31;\n a1 /= v2;\n }\n while ( !(unsigned int)(__SPAIR64__(v9, a1) % v2) );\n v3 *= v8;\n v4 = (double)a1;\n }\n v2 += 2;\n }\n if ( a1 > 1 )\n v3 *= a1 + 1;\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1240(int a1) {\n unsigned int v1;\n int v2;\n unsigned int v3;\n double v4;\n double v5;\n double v6;\n int v7;\n int v8;\n int v9;\n if ((a1 & 1) == 0) {\n do {\n v1 = a1 + ((unsigned int)a1 >> 31);\n a1 /= 2;\n } while ((v1 & 2) == 0);\n }\n v2 = 3;\n v3 = 1;\n v4 = (double)a1;\n while (1) {\n v5 = (double)v2;\n if (v4 < 0.0) {\n v6 = sqrt(v4);\n v5 = (double)v2;\n } else {\n v6 = sqrt(v4);\n }\n if (v6 + 1.0 < v5) break;\n v7 = 1;\n v8 = 1;\n if (!(a1 % v2)) {\n do {\n v7 *= v2;\n v8 += v7;\n v9 = (a1 / v2) >> 31;\n a1 /= v2;\n } while (!(unsigned int)(__SPAIR64__(v9, a1) % v2));\n v3 *= v8;\n v4 = (double)a1;\n }\n v2 += 2;\n }\n if (a1 > 1) v3 *= a1 + 1;\n return v3;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v1;\n int v2;\n unsigned int v3;\n double v4;\n double v5;\n double v6;\n int v7;\n int v8;\n int v9;\n if ((a1 & 1) == 0) {\n do {\n v1 = a1 + ((unsigned int)a1 >> 31);\n a1 /= 2;\n } while ((v1 & 2) == 0);\n }\n v2 = 3;\n v3 = 1;\n v4 = (double)a1;\n while (1) {\n v5 = (double)v2;\n if (v4 < 0.0) {\n v6 = sqrt(v4);\n v5 = (double)v2;\n } else {\n v6 = sqrt(v4);\n }\n if (v6 + 1.0 < v5) break;\n v7 = 1;\n v8 = 1;\n if (!(a1 % v2)) {\n do {\n v7 *= v2;\n v8 += v7;\n v9 = (a1 / v2) >> 31;\n a1 /= v2;\n } while (!(unsigned int)(__SPAIR64__(v9, a1) % v2));\n v3 *= v8;\n v4 = (double)a1;\n }\n v2 += 2;\n }\n if (a1 > 1) v3 *= a1 + 1;\n return v3;\n}" + }, + { + "index": 854, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int rawheap[], int size) {\n int i, j, temp;\n for (i = size / 2 - 1; i >= 0; i--) {\n for (j = 2 * i + 1; j < size; j = 2 * j + 1) {\n if (j + 1 < size && rawheap[j] > rawheap[j + 1]) {\n j++;\n }\n if (rawheap[i] <= rawheap[j]) {\n break;\n }\n temp = rawheap[i];\n rawheap[i] = rawheap[j];\n rawheap[j] = temp;\n i = j - 1;\n }\n }\n}", + "test": "int main() {\n\n int array1[] = {25, 44, 68, 21, 39, 23, 89};\n\n int size1 = sizeof(array1) / sizeof(array1[0]);\n\n func0(array1, size1);\n\n int expected1[] = {21, 25, 23, 44, 39, 68, 89};\n\n for (int i = 0; i < size1; i++) {\n\n assert(array1[i] == expected1[i]);\n\n }\n\n \n\n int array2[] = {25, 35, 22, 85, 14, 65, 75, 25, 58};\n\n int size2 = sizeof(array2) / sizeof(array2[0]);\n\n func0(array2, size2);\n\n int expected2[] = {14, 25, 22, 25, 35, 65, 75, 85, 58};\n\n for (int i = 0; i < size2; i++) {\n\n assert(array2[i] == expected2[i]);\n\n }\n\n \n\n int array3[] = {4, 5, 6, 2};\n\n int size3 = sizeof(array3) / sizeof(array3[0]);\n\n func0(array3, size3);\n\n int expected3[] = {2, 4, 6, 5};\n\n for (int i = 0; i < size3; i++) {\n\n assert(array3[i] == expected3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov -0x1c(%rbp),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nsub $0x1,%eax\nmov %eax,-0xc(%rbp)\njmpq 129c \nmov -0xc(%rbp),%eax\nadd %eax,%eax\nadd $0x1,%eax\nmov %eax,-0x8(%rbp)\njmpq 1289 \nmov -0x8(%rbp),%eax\nadd $0x1,%eax\ncmp %eax,-0x1c(%rbp)\njle 11e2 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x8(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njle 11e2 \naddl $0x1,-0x8(%rbp)\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njle 1297 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x4(%rbp)\nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0xc(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0x4(%rbp),%eax\nmov %eax,(%rdx)\nmov -0x8(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0xc(%rbp)\nmov -0x8(%rbp),%eax\nadd %eax,%eax\nadd $0x1,%eax\nmov %eax,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 119f \njmp 1298 \nsubl $0x1,-0xc(%rbp)\ncmpl $0x0,-0xc(%rbp)\njns 118f \npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov eax, [rbp+var_1C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nsub eax, 1\nmov [rbp+var_C], eax\njmp loc_129C\nloc_118F:\nmov eax, [rbp+var_C]\nadd eax, eax\nadd eax, 1\nmov [rbp+var_8], eax\njmp loc_1289\nloc_119F:\nmov eax, [rbp+var_8]\nadd eax, 1\ncmp [rbp+var_1C], eax\njle short loc_11E2\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_11E2\nadd [rbp+var_8], 1\nloc_11E2:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle loc_1297\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nmov eax, [rbp+var_8]\nsub eax, 1\nmov [rbp+var_C], eax\nmov eax, [rbp+var_8]\nadd eax, eax\nadd eax, 1\nmov [rbp+var_8], eax\nloc_1289:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl loc_119F\njmp short loc_1298\nloc_1297:\nnop\nloc_1298:\nsub [rbp+var_C], 1\nloc_129C:\ncmp [rbp+var_C], 0\njns loc_118F\nnop\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 result; // rax\n int i; // [rsp+10h] [rbp-Ch]\n int j; // [rsp+14h] [rbp-8h]\n int v5; // [rsp+18h] [rbp-4h]\n\n result = (unsigned int)(a2 / 2 - 1);\n for ( i = a2 / 2 - 1; i >= 0; --i )\n {\n for ( j = 2 * i + 1; ; j = 2 * j + 1 )\n {\n result = (unsigned int)j;\n if ( j >= a2 )\n break;\n if ( a2 > j + 1 && *(_DWORD *)(4LL * j + a1) > *(_DWORD *)(4 * (j + 1LL) + a1) )\n ++j;\n result = *(unsigned int *)(4LL * j + a1);\n if ( *(_DWORD *)(4LL * i + a1) <= (int)result )\n break;\n v5 = *(_DWORD *)(4LL * i + a1);\n *(_DWORD *)(4LL * i + a1) = *(_DWORD *)(4LL * j + a1);\n *(_DWORD *)(a1 + 4LL * j) = v5;\n i = j - 1;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov eax, [rbp+var_1C]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nsub eax, 1\nmov [rbp+var_C], eax\njmp loc_129C\nloc_118F:\nmov eax, [rbp+var_C]\nadd eax, eax\nadd eax, 1\nmov [rbp+var_8], eax\njmp loc_1289\nloc_119F:\nmov eax, [rbp+var_8]\nadd eax, 1\ncmp [rbp+var_1C], eax\njle short loc_11E2\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_11E2\nadd [rbp+var_8], 1\nloc_11E2:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle loc_1297\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nmov eax, [rbp+var_8]\nsub eax, 1\nmov [rbp+var_C], eax\nmov eax, [rbp+var_8]\nadd eax, eax\nadd eax, 1\nmov [rbp+var_8], eax\nloc_1289:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl loc_119F\njmp short loc_1298\nloc_1297:\nnop\nloc_1298:\nsub [rbp+var_C], 1\nloc_129C:\ncmp [rbp+var_C], 0\njns loc_118F\nnop\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n __int64 result; // rax\n int i; // [rsp+10h] [rbp-Ch]\n int j; // [rsp+14h] [rbp-8h]\n int v5; // [rsp+18h] [rbp-4h]\n\n result = (unsigned int)(a2 / 2 - 1);\n for ( i = a2 / 2 - 1; i >= 0; --i )\n {\n for ( j = 2 * i + 1; ; j = 2 * j + 1 )\n {\n result = (unsigned int)j;\n if ( j >= a2 )\n break;\n if ( a2 > j + 1 && *(_DWORD *)(4LL * j + a1) > *(_DWORD *)(4 * (j + 1LL) + a1) )\n ++j;\n result = *(unsigned int *)(4LL * j + a1);\n if ( *(_DWORD *)(4LL * i + a1) <= (int)result )\n break;\n v5 = *(_DWORD *)(4LL * i + a1);\n *(_DWORD *)(4LL * i + a1) = *(_DWORD *)(4LL * j + a1);\n *(_DWORD *)(a1 + 4LL * j) = v5;\n i = j - 1;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n long long result;\n int i;\n int j;\n int v5;\n result = (unsigned int)(a2 / 2 - 1);\n for (i = a2 / 2 - 1; i >= 0; --i) {\n for (j = 2 * i + 1;; j = 2 * j + 1) {\n result = (unsigned int)j;\n if (j >= a2) break;\n if (a2 > j + 1 &&\n *(uint32_t *)(4LL * j + a1) > *(uint32_t *)(4 * (j + 1LL) + a1))\n ++j;\n result = *(unsigned int *)(4LL * j + a1);\n if (*(uint32_t *)(4LL * i + a1) <= (int)result) break;\n v5 = *(uint32_t *)(4LL * i + a1);\n *(uint32_t *)(4LL * i + a1) = *(uint32_t *)(4LL * j + a1);\n *(uint32_t *)(a1 + 4LL * j) = v5;\n i = j - 1;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long result;\n int i;\n int j;\n int v5;\n result = (unsigned int)(a2 / 2 - 1);\n for (i = a2 / 2 - 1; i >= 0; --i) {\n for (j = 2 * i + 1;; j = 2 * j + 1) {\n result = (unsigned int)j;\n if (j >= a2) break;\n if (a2 > j + 1 &&\n *(uint32_t *)(4LL * j + a1) > *(uint32_t *)(4 * (j + 1LL) + a1))\n ++j;\n result = *(unsigned int *)(4LL * j + a1);\n if (*(uint32_t *)(4LL * i + a1) <= (int)result) break;\n v5 = *(uint32_t *)(4LL * i + a1);\n *(uint32_t *)(4LL * i + a1) = *(uint32_t *)(4LL * j + a1);\n *(uint32_t *)(a1 + 4LL * j) = v5;\n i = j - 1;\n }\n }\n return result;\n}" + }, + { + "index": 854, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int rawheap[], int size) {\n int i, j, temp;\n for (i = size / 2 - 1; i >= 0; i--) {\n for (j = 2 * i + 1; j < size; j = 2 * j + 1) {\n if (j + 1 < size && rawheap[j] > rawheap[j + 1]) {\n j++;\n }\n if (rawheap[i] <= rawheap[j]) {\n break;\n }\n temp = rawheap[i];\n rawheap[i] = rawheap[j];\n rawheap[j] = temp;\n i = j - 1;\n }\n }\n}", + "test": "int main() {\n\n int array1[] = {25, 44, 68, 21, 39, 23, 89};\n\n int size1 = sizeof(array1) / sizeof(array1[0]);\n\n func0(array1, size1);\n\n int expected1[] = {21, 25, 23, 44, 39, 68, 89};\n\n for (int i = 0; i < size1; i++) {\n\n assert(array1[i] == expected1[i]);\n\n }\n\n \n\n int array2[] = {25, 35, 22, 85, 14, 65, 75, 25, 58};\n\n int size2 = sizeof(array2) / sizeof(array2[0]);\n\n func0(array2, size2);\n\n int expected2[] = {14, 25, 22, 25, 35, 65, 75, 85, 58};\n\n for (int i = 0; i < size2; i++) {\n\n assert(array2[i] == expected2[i]);\n\n }\n\n \n\n int array3[] = {4, 5, 6, 2};\n\n int size3 = sizeof(array3) / sizeof(array3[0]);\n\n func0(array3, size3);\n\n int expected3[] = {2, 4, 6, 5};\n\n for (int i = 0; i < size3; i++) {\n\n assert(array3[i] == expected3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %esi,%r10d\nshr $0x1f,%r10d\nadd %esi,%r10d\nsar %r10d\nsub $0x1,%r10d\njns 11c9 \nretq\nmovslq %r10d,%rdx\nlea (%rdi,%rdx,4),%r8\nmov (%r8),%ecx\nmovslq %eax,%rdx\nlea (%rdi,%rdx,4),%rdx\nmov (%rdx),%r9d\ncmp %r9d,%ecx\njle 11c3 \nmov %r9d,(%r8)\nmov %ecx,(%rdx)\nlea -0x1(%rax),%r10d\nlea 0x1(%rax,%rax,1),%eax\ncmp %eax,%esi\njle 11c3 \nlea 0x1(%rax),%edx\ncmp %esi,%edx\njge 1181 \nmovslq %eax,%rcx\nmov 0x4(%rdi,%rcx,4),%r11d\ncmp %r11d,(%rdi,%rcx,4)\ncmovg %edx,%eax\njmp 1181 \nsub $0x1,%r10d\njs 1180 \nlea 0x1(%r10,%r10,1),%eax\ncmp %eax,%esi\njg 11ab \njmp 11c3 \n", + "ida_asm": "func0:\nendbr64\nmov rdx, rdi\nmov r10d, esi\nshr r10d, 1Fh\nadd r10d, esi\nsar r10d, 1\nsub r10d, 1\njns short loc_11CC\nlocret_1183:\nretn\nloc_1184:\nmovsxd rcx, r10d\nlea r8, [rdx+rcx*4]\nmov edi, [r8]\nmovsxd rcx, eax\nlea rcx, [rdx+rcx*4]\nmov r9d, [rcx]\ncmp edi, r9d\njle short loc_11C6\nmov [r8], r9d\nmov [rcx], edi\nlea r10d, [rax-1]\nlea eax, [rax+rax+1]\ncmp esi, eax\njle short loc_11C6\nloc_11AE:\nlea ecx, [rax+1]\ncmp ecx, esi\njge short loc_1184\nmovsxd rdi, eax\nmov r11d, [rdx+rdi*4+4]\ncmp [rdx+rdi*4], r11d\ncmovg eax, ecx\njmp short loc_1184\nloc_11C6:\nsub r10d, 1\njs short locret_1183\nloc_11CC:\nlea eax, [r10+r10+1]\ncmp esi, eax\njg short loc_11AE\njmp short loc_11C6", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2)\n{\n int i; // r10d\n int *v4; // r8\n int v5; // edi\n int *v6; // rcx\n int j; // eax\n\n for ( i = a2 / 2 - 1; i >= 0; --i )\n {\n for ( j = 2 * i + 1; a2 > j; j = 2 * j + 1 )\n {\n if ( j + 1 < a2 && *(_DWORD *)(a1 + 4LL * j) > *(_DWORD *)(a1 + 4LL * j + 4) )\n ++j;\n v4 = (int *)(a1 + 4LL * i);\n v5 = *v4;\n v6 = (int *)(a1 + 4LL * j);\n if ( *v4 <= *v6 )\n break;\n *v4 = *v6;\n *v6 = v5;\n i = j - 1;\n }\n }\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov rdx, rdi\nmov r10d, esi\nshr r10d, 1Fh\nadd r10d, esi\nsar r10d, 1\nsub r10d, 1\njns short loc_11CC\nlocret_1183:\nretn\nloc_1184:\nmovsxd rcx, r10d\nlea r8, [rdx+rcx*4]\nmov edi, [r8]\nmovsxd rcx, eax\nlea rcx, [rdx+rcx*4]\nmov r9d, [rcx]\ncmp edi, r9d\njle short loc_11C6\nmov [r8], r9d\nmov [rcx], edi\nlea r10d, [rax-1]\nlea eax, [rax+rax+1]\ncmp esi, eax\njle short loc_11C6\nloc_11AE:\nlea ecx, [rax+1]\ncmp ecx, esi\njge short loc_1184\nmovsxd rdi, eax\nmov r11d, [rdx+rdi*4+4]\ncmp [rdx+rdi*4], r11d\ncmovg eax, ecx\njmp short loc_1184\nloc_11C6:\nsub r10d, 1\njs short locret_1183\nloc_11CC:\nlea eax, [r10+r10+1]\ncmp esi, eax\njg short loc_11AE\njmp short loc_11C6", + "ida_strip_pseudo": "void __fastcall sub_1169(__int64 a1, int a2)\n{\n int i; // r10d\n int *v4; // r8\n int v5; // edi\n int *v6; // rcx\n int j; // eax\n\n for ( i = a2 / 2 - 1; i >= 0; --i )\n {\n for ( j = 2 * i + 1; a2 > j; j = 2 * j + 1 )\n {\n if ( j + 1 < a2 && *(_DWORD *)(a1 + 4LL * j) > *(_DWORD *)(a1 + 4LL * j + 4) )\n ++j;\n v4 = (int *)(a1 + 4LL * i);\n v5 = *v4;\n v6 = (int *)(a1 + 4LL * j);\n if ( *v4 <= *v6 )\n break;\n *v4 = *v6;\n *v6 = v5;\n i = j - 1;\n }\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1169(long long a1, int a2) {\n int i;\n int *v4;\n int v5;\n int *v6;\n int j;\n for (i = a2 / 2 - 1; i >= 0; --i) {\n for (j = 2 * i + 1; a2 > j; j = 2 * j + 1) {\n if (j + 1 < a2 &&\n *(uint32_t *)(a1 + 4LL * j) > *(uint32_t *)(a1 + 4LL * j + 4))\n ++j;\n v4 = (int *)(a1 + 4LL * i);\n v5 = *v4;\n v6 = (int *)(a1 + 4LL * j);\n if (*v4 <= *v6) break;\n *v4 = *v6;\n *v6 = v5;\n i = j - 1;\n }\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2) {\n int i;\n int *v4;\n int v5;\n int *v6;\n int j;\n for (i = a2 / 2 - 1; i >= 0; --i) {\n for (j = 2 * i + 1; a2 > j; j = 2 * j + 1) {\n if (j + 1 < a2 &&\n *(uint32_t *)(a1 + 4LL * j) > *(uint32_t *)(a1 + 4LL * j + 4))\n ++j;\n v4 = (int *)(a1 + 4LL * i);\n v5 = *v4;\n v6 = (int *)(a1 + 4LL * j);\n if (*v4 <= *v6) break;\n *v4 = *v6;\n *v6 = v5;\n i = j - 1;\n }\n }\n}" + }, + { + "index": 854, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int rawheap[], int size) {\n int i, j, temp;\n for (i = size / 2 - 1; i >= 0; i--) {\n for (j = 2 * i + 1; j < size; j = 2 * j + 1) {\n if (j + 1 < size && rawheap[j] > rawheap[j + 1]) {\n j++;\n }\n if (rawheap[i] <= rawheap[j]) {\n break;\n }\n temp = rawheap[i];\n rawheap[i] = rawheap[j];\n rawheap[j] = temp;\n i = j - 1;\n }\n }\n}", + "test": "int main() {\n\n int array1[] = {25, 44, 68, 21, 39, 23, 89};\n\n int size1 = sizeof(array1) / sizeof(array1[0]);\n\n func0(array1, size1);\n\n int expected1[] = {21, 25, 23, 44, 39, 68, 89};\n\n for (int i = 0; i < size1; i++) {\n\n assert(array1[i] == expected1[i]);\n\n }\n\n \n\n int array2[] = {25, 35, 22, 85, 14, 65, 75, 25, 58};\n\n int size2 = sizeof(array2) / sizeof(array2[0]);\n\n func0(array2, size2);\n\n int expected2[] = {14, 25, 22, 25, 35, 65, 75, 85, 58};\n\n for (int i = 0; i < size2; i++) {\n\n assert(array2[i] == expected2[i]);\n\n }\n\n \n\n int array3[] = {4, 5, 6, 2};\n\n int size3 = sizeof(array3) / sizeof(array3[0]);\n\n func0(array3, size3);\n\n int expected3[] = {2, 4, 6, 5};\n\n for (int i = 0; i < size3; i++) {\n\n assert(array3[i] == expected3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov %esi,%r10d\nshr $0x1f,%r10d\nadd %esi,%r10d\nsar %r10d\nsub $0x1,%r10d\njs 1457 \nnopw 0x0(%rax,%rax,1)\nlea 0x1(%r10,%r10,1),%eax\ncmp %eax,%esi\njg 1412 \njmp 144d \nnopl 0x0(%rax,%rax,1)\nlea -0x1(%rax),%r10d\nlea 0x1(%rax,%rax,1),%eax\nmov %ecx,(%r9)\nmov %edx,(%r8)\ncmp %eax,%esi\njle 144d \nmovslq %eax,%rdx\nlea 0x1(%rax),%r9d\nshl $0x2,%rdx\nlea (%rdi,%rdx,1),%r8\nmov (%r8),%ecx\ncmp %esi,%r9d\njge 143f \nlea 0x4(%rdi,%rdx,1),%rdx\nmov (%rdx),%r11d\ncmp %ecx,%r11d\njge 143f \nmov %r11d,%ecx\nmov %rdx,%r8\nmov %r9d,%eax\nmovslq %r10d,%rdx\nlea (%rdi,%rdx,4),%r9\nmov (%r9),%edx\ncmp %ecx,%edx\njg 1400 \nsub $0x1,%r10d\ncmp $0xffffffff,%r10d\njne 13f0 \nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmov r9d, esi\nmov r8, rdi\nmov r10d, esi\nshr r9d, 1Fh\nadd r9d, esi\nsar r9d, 1\nnop word ptr [rax+rax+00000000h]\nloc_1370:\nsub r9d, 1\njs short locret_13CE\nloc_1376:\nlea eax, [r9+r9+1]\ncmp r10d, eax\njle short loc_1370\nloc_1380:\nmovsxd rdx, eax\nlea edi, [rax+1]\nshl rdx, 2\nlea rsi, [r8+rdx]\nmov ecx, [rsi]\ncmp edi, r10d\njge short loc_13AA\nlea rdx, [r8+rdx+4]\nmov r11d, [rdx]\ncmp r11d, ecx\njge short loc_13AA\nmov ecx, r11d\nmov rsi, rdx\nmov eax, edi\nloc_13AA:\nmovsxd rdx, r9d\nlea rdi, [r8+rdx*4]\nmov edx, [rdi]\ncmp edx, ecx\njle short loc_1370\nlea r9d, [rax-1]\nlea eax, [rax+rax+1]\nmov [rdi], ecx\nmov [rsi], edx\ncmp r10d, eax\njg short loc_1380\nsub r9d, 1\njns short loc_1376\nlocret_13CE:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2)\n{\n int v4; // r9d\n int v5; // eax\n __int64 v6; // rdx\n _DWORD *v7; // rsi\n int v8; // ecx\n _DWORD *v9; // rdx\n int *v10; // rdi\n int v11; // edx\n\n v4 = a2 / 2;\n while ( --v4 >= 0 )\n {\nLABEL_3:\n v5 = 2 * v4 + 1;\n if ( a2 > v5 )\n {\n while ( 1 )\n {\n v6 = 4LL * v5;\n v7 = (_DWORD *)(a1 + v6);\n v8 = *(_DWORD *)(a1 + v6);\n if ( v5 + 1 < a2 )\n {\n v9 = (_DWORD *)(a1 + v6 + 4);\n if ( *v9 < v8 )\n {\n v8 = *v9;\n v7 = v9;\n ++v5;\n }\n }\n v10 = (int *)(a1 + 4LL * v4);\n v11 = *v10;\n if ( *v10 <= v8 )\n break;\n v4 = v5 - 1;\n v5 = 2 * v5 + 1;\n *v10 = v8;\n *v7 = v11;\n if ( a2 <= v5 )\n {\n if ( --v4 >= 0 )\n goto LABEL_3;\n return;\n }\n }\n }\n }\n}", + "ida_strip_asm": "sub_1350:\nendbr64\nmov r9d, esi\nmov r8, rdi\nmov r10d, esi\nshr r9d, 1Fh\nadd r9d, esi\nsar r9d, 1\nnop word ptr [rax+rax+00000000h]\nloc_1370:\nsub r9d, 1\njs short locret_13CE\nloc_1376:\nlea eax, [r9+r9+1]\ncmp r10d, eax\njle short loc_1370\nloc_1380:\nmovsxd rdx, eax\nlea edi, [rax+1]\nshl rdx, 2\nlea rsi, [r8+rdx]\nmov ecx, [rsi]\ncmp edi, r10d\njge short loc_13AA\nlea rdx, [r8+rdx+4]\nmov r11d, [rdx]\ncmp r11d, ecx\njge short loc_13AA\nmov ecx, r11d\nmov rsi, rdx\nmov eax, edi\nloc_13AA:\nmovsxd rdx, r9d\nlea rdi, [r8+rdx*4]\nmov edx, [rdi]\ncmp edx, ecx\njle short loc_1370\nlea r9d, [rax-1]\nlea eax, [rax+rax+1]\nmov [rdi], ecx\nmov [rsi], edx\ncmp r10d, eax\njg short loc_1380\nsub r9d, 1\njns short loc_1376\nlocret_13CE:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1350(__int64 a1, int a2)\n{\n int v4; // r9d\n int v5; // eax\n __int64 v6; // rdx\n _DWORD *v7; // rsi\n int v8; // ecx\n _DWORD *v9; // rdx\n int *v10; // rdi\n int v11; // edx\n\n v4 = a2 / 2;\n while ( --v4 >= 0 )\n {\nLABEL_3:\n v5 = 2 * v4 + 1;\n if ( a2 > v5 )\n {\n while ( 1 )\n {\n v6 = 4LL * v5;\n v7 = (_DWORD *)(a1 + v6);\n v8 = *(_DWORD *)(a1 + v6);\n if ( v5 + 1 < a2 )\n {\n v9 = (_DWORD *)(a1 + v6 + 4);\n if ( *v9 < v8 )\n {\n v8 = *v9;\n v7 = v9;\n ++v5;\n }\n }\n v10 = (int *)(a1 + 4LL * v4);\n v11 = *v10;\n if ( *v10 <= v8 )\n break;\n v4 = v5 - 1;\n v5 = 2 * v5 + 1;\n *v10 = v8;\n *v7 = v11;\n if ( a2 <= v5 )\n {\n if ( --v4 >= 0 )\n goto LABEL_3;\n return;\n }\n }\n }\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1350(long long a1, int a2) {\n int v4;\n int v5;\n long long v6;\n uint32_t *v7;\n int v8;\n uint32_t *v9;\n int *v10;\n int v11;\n v4 = a2 / 2;\n while (--v4 >= 0) {\n LABEL_3:\n v5 = 2 * v4 + 1;\n if (a2 > v5) {\n while (1) {\n v6 = 4LL * v5;\n v7 = (uint32_t *)(a1 + v6);\n v8 = *(uint32_t *)(a1 + v6);\n if (v5 + 1 < a2) {\n v9 = (uint32_t *)(a1 + v6 + 4);\n if (*v9 < v8) {\n v8 = *v9;\n v7 = v9;\n ++v5;\n }\n }\n v10 = (int *)(a1 + 4LL * v4);\n v11 = *v10;\n if (*v10 <= v8) break;\n v4 = v5 - 1;\n v5 = 2 * v5 + 1;\n *v10 = v8;\n *v7 = v11;\n if (a2 <= v5) {\n if (--v4 >= 0) goto LABEL_3;\n return;\n }\n }\n }\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2) {\n int v4;\n int v5;\n long long v6;\n uint32_t *v7;\n int v8;\n uint32_t *v9;\n int *v10;\n int v11;\n v4 = a2 / 2;\n while (--v4 >= 0) {\n LABEL_3:\n v5 = 2 * v4 + 1;\n if (a2 > v5) {\n while (1) {\n v6 = 4LL * v5;\n v7 = (uint32_t *)(a1 + v6);\n v8 = *(uint32_t *)(a1 + v6);\n if (v5 + 1 < a2) {\n v9 = (uint32_t *)(a1 + v6 + 4);\n if (*v9 < v8) {\n v8 = *v9;\n v7 = v9;\n ++v5;\n }\n }\n v10 = (int *)(a1 + 4LL * v4);\n v11 = *v10;\n if (*v10 <= v8) break;\n v4 = v5 - 1;\n v5 = 2 * v5 + 1;\n *v10 = v8;\n *v7 = v11;\n if (a2 <= v5) {\n if (--v4 >= 0) goto LABEL_3;\n return;\n }\n }\n }\n }\n}" + }, + { + "index": 854, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int rawheap[], int size) {\n int i, j, temp;\n for (i = size / 2 - 1; i >= 0; i--) {\n for (j = 2 * i + 1; j < size; j = 2 * j + 1) {\n if (j + 1 < size && rawheap[j] > rawheap[j + 1]) {\n j++;\n }\n if (rawheap[i] <= rawheap[j]) {\n break;\n }\n temp = rawheap[i];\n rawheap[i] = rawheap[j];\n rawheap[j] = temp;\n i = j - 1;\n }\n }\n}", + "test": "int main() {\n\n int array1[] = {25, 44, 68, 21, 39, 23, 89};\n\n int size1 = sizeof(array1) / sizeof(array1[0]);\n\n func0(array1, size1);\n\n int expected1[] = {21, 25, 23, 44, 39, 68, 89};\n\n for (int i = 0; i < size1; i++) {\n\n assert(array1[i] == expected1[i]);\n\n }\n\n \n\n int array2[] = {25, 35, 22, 85, 14, 65, 75, 25, 58};\n\n int size2 = sizeof(array2) / sizeof(array2[0]);\n\n func0(array2, size2);\n\n int expected2[] = {14, 25, 22, 25, 35, 65, 75, 85, 58};\n\n for (int i = 0; i < size2; i++) {\n\n assert(array2[i] == expected2[i]);\n\n }\n\n \n\n int array3[] = {4, 5, 6, 2};\n\n int size3 = sizeof(array3) / sizeof(array3[0]);\n\n func0(array3, size3);\n\n int expected3[] = {2, 4, 6, 5};\n\n for (int i = 0; i < size3; i++) {\n\n assert(array3[i] == expected3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nmov %esi,%r10d\nshr $0x1f,%r10d\nadd %esi,%r10d\nsar %r10d\nsub $0x1,%r10d\njs 1437 \nnopw 0x0(%rax,%rax,1)\nlea 0x1(%r10,%r10,1),%eax\ncmp %eax,%esi\njg 13f2 \njmp 142d \nnopl 0x0(%rax,%rax,1)\nlea -0x1(%rax),%r10d\nlea 0x1(%rax,%rax,1),%eax\nmov %ecx,(%r9)\nmov %edx,(%r8)\ncmp %eax,%esi\njle 142d \nmovslq %eax,%rdx\nlea 0x1(%rax),%r9d\nshl $0x2,%rdx\nlea (%rdi,%rdx,1),%r8\nmov (%r8),%ecx\ncmp %esi,%r9d\njge 141f \nlea 0x4(%rdi,%rdx,1),%rdx\nmov (%rdx),%r11d\ncmp %ecx,%r11d\njge 141f \nmov %r11d,%ecx\nmov %rdx,%r8\nmov %r9d,%eax\nmovslq %r10d,%rdx\nlea (%rdi,%rdx,4),%r9\nmov (%r9),%edx\ncmp %ecx,%edx\njg 13e0 \nsub $0x1,%r10d\ncmp $0xffffffff,%r10d\njne 13d0 \nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmov r9d, esi\nmov r8, rdi\nmov r10d, esi\nshr r9d, 1Fh\nadd r9d, esi\nsar r9d, 1\nnop word ptr [rax+rax+00000000h]\nloc_1350:\nsub r9d, 1\njs short locret_13AE\nloc_1356:\nlea eax, [r9+r9+1]\ncmp r10d, eax\njle short loc_1350\nloc_1360:\nmovsxd rdx, eax\nlea edi, [rax+1]\nshl rdx, 2\nlea rsi, [r8+rdx]\nmov ecx, [rsi]\ncmp edi, r10d\njge short loc_138A\nlea rdx, [r8+rdx+4]\nmov r11d, [rdx]\ncmp r11d, ecx\njge short loc_138A\nmov ecx, r11d\nmov rsi, rdx\nmov eax, edi\nloc_138A:\nmovsxd rdx, r9d\nlea rdi, [r8+rdx*4]\nmov edx, [rdi]\ncmp edx, ecx\njle short loc_1350\nlea r9d, [rax-1]\nlea eax, [rax+rax+1]\nmov [rdi], ecx\nmov [rsi], edx\ncmp r10d, eax\njg short loc_1360\nsub r9d, 1\njns short loc_1356\nlocret_13AE:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2)\n{\n int v4; // r9d\n int v5; // eax\n __int64 v6; // rdx\n _DWORD *v7; // rsi\n int v8; // ecx\n _DWORD *v9; // rdx\n int *v10; // rdi\n int v11; // edx\n\n v4 = a2 / 2;\n while ( --v4 >= 0 )\n {\nLABEL_3:\n v5 = 2 * v4 + 1;\n if ( a2 > v5 )\n {\n while ( 1 )\n {\n v6 = 4LL * v5;\n v7 = (_DWORD *)(a1 + v6);\n v8 = *(_DWORD *)(a1 + v6);\n if ( v5 + 1 < a2 )\n {\n v9 = (_DWORD *)(a1 + v6 + 4);\n if ( *v9 < v8 )\n {\n v8 = *v9;\n v7 = v9;\n ++v5;\n }\n }\n v10 = (int *)(a1 + 4LL * v4);\n v11 = *v10;\n if ( *v10 <= v8 )\n break;\n v4 = v5 - 1;\n v5 = 2 * v5 + 1;\n *v10 = v8;\n *v7 = v11;\n if ( a2 <= v5 )\n {\n if ( --v4 >= 0 )\n goto LABEL_3;\n return;\n }\n }\n }\n }\n}", + "ida_strip_asm": "sub_1330:\nendbr64\nmov r9d, esi\nmov r8, rdi\nmov r10d, esi\nshr r9d, 1Fh\nadd r9d, esi\nsar r9d, 1\nnop word ptr [rax+rax+00000000h]\nloc_1350:\nsub r9d, 1\njs short locret_13AE\nloc_1356:\nlea eax, [r9+r9+1]\ncmp r10d, eax\njle short loc_1350\nloc_1360:\nmovsxd rdx, eax\nlea edi, [rax+1]\nshl rdx, 2\nlea rsi, [r8+rdx]\nmov ecx, [rsi]\ncmp edi, r10d\njge short loc_138A\nlea rdx, [r8+rdx+4]\nmov r11d, [rdx]\ncmp r11d, ecx\njge short loc_138A\nmov ecx, r11d\nmov rsi, rdx\nmov eax, edi\nloc_138A:\nmovsxd rdx, r9d\nlea rdi, [r8+rdx*4]\nmov edx, [rdi]\ncmp edx, ecx\njle short loc_1350\nlea r9d, [rax-1]\nlea eax, [rax+rax+1]\nmov [rdi], ecx\nmov [rsi], edx\ncmp r10d, eax\njg short loc_1360\nsub r9d, 1\njns short loc_1356\nlocret_13AE:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1330(__int64 a1, int a2)\n{\n int v4; // r9d\n int v5; // eax\n __int64 v6; // rdx\n _DWORD *v7; // rsi\n int v8; // ecx\n _DWORD *v9; // rdx\n int *v10; // rdi\n int v11; // edx\n\n v4 = a2 / 2;\n while ( --v4 >= 0 )\n {\nLABEL_3:\n v5 = 2 * v4 + 1;\n if ( a2 > v5 )\n {\n while ( 1 )\n {\n v6 = 4LL * v5;\n v7 = (_DWORD *)(a1 + v6);\n v8 = *(_DWORD *)(a1 + v6);\n if ( v5 + 1 < a2 )\n {\n v9 = (_DWORD *)(a1 + v6 + 4);\n if ( *v9 < v8 )\n {\n v8 = *v9;\n v7 = v9;\n ++v5;\n }\n }\n v10 = (int *)(a1 + 4LL * v4);\n v11 = *v10;\n if ( *v10 <= v8 )\n break;\n v4 = v5 - 1;\n v5 = 2 * v5 + 1;\n *v10 = v8;\n *v7 = v11;\n if ( a2 <= v5 )\n {\n if ( --v4 >= 0 )\n goto LABEL_3;\n return;\n }\n }\n }\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1330(long long a1, int a2) {\n int v4;\n int v5;\n long long v6;\n uint32_t *v7;\n int v8;\n uint32_t *v9;\n int *v10;\n int v11;\n v4 = a2 / 2;\n while (--v4 >= 0) {\n LABEL_3:\n v5 = 2 * v4 + 1;\n if (a2 > v5) {\n while (1) {\n v6 = 4LL * v5;\n v7 = (uint32_t *)(a1 + v6);\n v8 = *(uint32_t *)(a1 + v6);\n if (v5 + 1 < a2) {\n v9 = (uint32_t *)(a1 + v6 + 4);\n if (*v9 < v8) {\n v8 = *v9;\n v7 = v9;\n ++v5;\n }\n }\n v10 = (int *)(a1 + 4LL * v4);\n v11 = *v10;\n if (*v10 <= v8) break;\n v4 = v5 - 1;\n v5 = 2 * v5 + 1;\n *v10 = v8;\n *v7 = v11;\n if (a2 <= v5) {\n if (--v4 >= 0) goto LABEL_3;\n return;\n }\n }\n }\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2) {\n int v4;\n int v5;\n long long v6;\n uint32_t *v7;\n int v8;\n uint32_t *v9;\n int *v10;\n int v11;\n v4 = a2 / 2;\n while (--v4 >= 0) {\n LABEL_3:\n v5 = 2 * v4 + 1;\n if (a2 > v5) {\n while (1) {\n v6 = 4LL * v5;\n v7 = (uint32_t *)(a1 + v6);\n v8 = *(uint32_t *)(a1 + v6);\n if (v5 + 1 < a2) {\n v9 = (uint32_t *)(a1 + v6 + 4);\n if (*v9 < v8) {\n v8 = *v9;\n v7 = v9;\n ++v5;\n }\n }\n v10 = (int *)(a1 + 4LL * v4);\n v11 = *v10;\n if (*v10 <= v8) break;\n v4 = v5 - 1;\n v5 = 2 * v5 + 1;\n *v10 = v8;\n *v7 = v11;\n if (a2 <= v5) {\n if (--v4 >= 0) goto LABEL_3;\n return;\n }\n }\n }\n }\n}" + }, + { + "index": 855, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int x) {\n int parity = 0;\n while (x != 0) {\n x = x & (x - 1);\n parity++;\n }\n return (parity % 2 == 0);\n}", + "test": "int main() {\n\n assert(func0(10) == true);\n\n assert(func0(11) == false);\n\n assert(func0(18) == true);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 116a \nmov -0x14(%rbp),%eax\nsub $0x1,%eax\nand %eax,-0x14(%rbp)\naddl $0x1,-0x4(%rbp)\ncmpl $0x0,-0x14(%rbp)\njne 115d \nmov -0x4(%rbp),%eax\nand $0x1,%eax\ntest %eax,%eax\nsete %al\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_4], 0\njmp short loc_116A\nloc_115D:\nmov eax, [rbp+var_14]\nsub eax, 1\nand [rbp+var_14], eax\nadd [rbp+var_4], 1\nloc_116A:\ncmp [rbp+var_14], 0\njnz short loc_115D\nmov eax, [rbp+var_4]\nand eax, 1\ntest eax, eax\nsetz al\npop rbp\nretn", + "ida_pseudo": "bool __fastcall func0(int a1)\n{\n char v3; // [rsp+10h] [rbp-4h]\n\n v3 = 0;\n while ( a1 )\n {\n a1 &= a1 - 1;\n ++v3;\n }\n return (v3 & 1) == 0;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_4], 0\njmp short loc_116A\nloc_115D:\nmov eax, [rbp+var_14]\nsub eax, 1\nand [rbp+var_14], eax\nadd [rbp+var_4], 1\nloc_116A:\ncmp [rbp+var_14], 0\njnz short loc_115D\nmov eax, [rbp+var_4]\nand eax, 1\ntest eax, eax\nsetz al\npop rbp\nretn", + "ida_strip_pseudo": "bool __fastcall sub_1149(int a1)\n{\n char v3; // [rsp+10h] [rbp-4h]\n\n v3 = 0;\n while ( a1 )\n {\n a1 &= a1 - 1;\n ++v3;\n }\n return (v3 & 1) == 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_1149(int a1) {\n char v3;\n v3 = 0;\n while (a1) {\n a1 &= a1 - 1;\n ++v3;\n }\n return (v3 & 1) == 0;\n}", + "ida_pseudo_norm": "bool func0(int a1) {\n char v3;\n v3 = 0;\n while (a1) {\n a1 &= a1 - 1;\n ++v3;\n }\n return (v3 & 1) == 0;\n}" + }, + { + "index": 855, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int x) {\n int parity = 0;\n while (x != 0) {\n x = x & (x - 1);\n parity++;\n }\n return (parity % 2 == 0);\n}", + "test": "int main() {\n\n assert(func0(10) == true);\n\n assert(func0(11) == false);\n\n assert(func0(18) == true);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\nje 1167 \nmov $0x0,%eax\nlea -0x1(%rdi),%edx\nadd $0x1,%eax\nand %edx,%edi\njne 1156 \nxor $0x1,%eax\nand $0x1,%eax\nretq\nmov %edi,%eax\njmp 1160 \n", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njz short loc_1167\nmov eax, 0\nloc_1156:\nlea edx, [rdi-1]\nadd eax, 1\nand edi, edx\njnz short loc_1156\nloc_1160:\nxor eax, 1\nand eax, 1\nretn\nloc_1167:\nmov eax, edi\njmp short loc_1160", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned __int8 v1; // al\n\n if ( a1 )\n {\n v1 = 0;\n do\n {\n ++v1;\n a1 &= a1 - 1;\n }\n while ( a1 );\n }\n else\n {\n v1 = 0;\n }\n return (v1 ^ 1) & 1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ntest edi, edi\njz short loc_1167\nmov eax, 0\nloc_1156:\nlea edx, [rdi-1]\nadd eax, 1\nand edi, edx\njnz short loc_1156\nloc_1160:\nxor eax, 1\nand eax, 1\nretn\nloc_1167:\nmov eax, edi\njmp short loc_1160", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n unsigned __int8 v1; // al\n\n if ( a1 )\n {\n v1 = 0;\n do\n {\n ++v1;\n a1 &= a1 - 1;\n }\n while ( a1 );\n }\n else\n {\n v1 = 0;\n }\n return (v1 ^ 1) & 1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n unsigned char v1;\n if (a1) {\n v1 = 0;\n do {\n ++v1;\n a1 &= a1 - 1;\n } while (a1);\n } else {\n v1 = 0;\n }\n return (v1 ^ 1) & 1;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned char v1;\n if (a1) {\n v1 = 0;\n do {\n ++v1;\n a1 &= a1 - 1;\n } while (a1);\n } else {\n v1 = 0;\n }\n return (v1 ^ 1) & 1;\n}" + }, + { + "index": 856, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int noOfZeroes[n];\n int count = 0;\n noOfZeroes[n - 1] = 1 - arr[n - 1];\n for (int i = n - 2; i >= 0; i--) {\n noOfZeroes[i] = noOfZeroes[i + 1];\n if (arr[i] == 0) {\n noOfZeroes[i]++;\n }\n }\n for (int i = 0; i < n; i++) {\n if (arr[i] == 1) {\n count += noOfZeroes[i];\n }\n }\n return count;\n}", + "test": "int main() {\n\n int arr1[] = {1, 0, 1, 0};\n\n int arr2[] = {0, 1, 0};\n\n int arr3[] = {0, 0, 1, 1, 0};\n\n\n\n assert(func0(arr1, 4) == 3);\n\n assert(func0(arr2, 3) == 1);\n\n assert(func0(arr3, 5) == 2);\n\n\n\n printf(\"All test cases passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x48,%rsp\nmov %rdi,-0x48(%rbp)\nmov %esi,-0x4c(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmov %rsp,%rax\nmov %rax,%rsi\nmov -0x4c(%rbp),%eax\nmovslq %eax,%rdx\nsub $0x1,%rdx\nmov %rdx,-0x28(%rbp)\nmovslq %eax,%rdx\nmov %rdx,%r8\nmov $0x0,%r9d\nmovslq %eax,%rdx\nmov %rdx,%rcx\nmov $0x0,%ebx\ncltq\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%edi\nmov $0x0,%edx\ndiv %rdi\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rbx\nsub %rdx,%rbx\nmov %rbx,%rdx\ncmp %rdx,%rsp\nje 1228 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 1211 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 1252 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x20(%rbp)\nmovl $0x0,-0x2c(%rbp)\nmov -0x4c(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov -0x4c(%rbp),%edx\nsub $0x1,%edx\nmov $0x1,%ecx\nsub %eax,%ecx\nmov -0x20(%rbp),%rax\nmovslq %edx,%rdx\nmov %ecx,(%rax,%rdx,4)\nmov -0x4c(%rbp),%eax\nsub $0x2,%eax\nmov %eax,-0x30(%rbp)\njmp 12fc \nmov -0x30(%rbp),%eax\nlea 0x1(%rax),%edx\nmov -0x20(%rbp),%rax\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%ecx\nmov -0x20(%rbp),%rax\nmov -0x30(%rbp),%edx\nmovslq %edx,%rdx\nmov %ecx,(%rax,%rdx,4)\nmov -0x30(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ntest %eax,%eax\njne 12f8 \nmov -0x20(%rbp),%rax\nmov -0x30(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nlea 0x1(%rax),%ecx\nmov -0x20(%rbp),%rax\nmov -0x30(%rbp),%edx\nmovslq %edx,%rdx\nmov %ecx,(%rax,%rdx,4)\nsubl $0x1,-0x30(%rbp)\ncmpl $0x0,-0x30(%rbp)\njns 12a4 \nmovl $0x0,-0x34(%rbp)\njmp 133a \nmov -0x34(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp $0x1,%eax\njne 1336 \nmov -0x20(%rbp),%rax\nmov -0x34(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nadd %eax,-0x2c(%rbp)\naddl $0x1,-0x34(%rbp)\nmov -0x34(%rbp),%eax\ncmp -0x4c(%rbp),%eax\njl 130b \nmov -0x2c(%rbp),%eax\nmov %rsi,%rsp\nmov -0x18(%rbp),%rdi\nxor %fs:0x28,%rdi\nje 135c \ncallq 1080 <__stack_chk_fail@plt>\nmov -0x8(%rbp),%rbx\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov eax, [rbp+var_3C]\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11F6:\ncmp rsp, rdx\njz short loc_120D\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_11F6\nloc_120D:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1237\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1237:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov [rbp+var_24], 0\nmov eax, [rbp+var_3C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_3C]\nsub edx, 1\nmov ecx, 1\nsub ecx, eax\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nmov eax, [rbp+var_3C]\nsub eax, 2\nmov [rbp+var_20], eax\njmp short loc_12E1\nloc_1289:\nmov eax, [rbp+var_20]\nlea edx, [rax+1]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njnz short loc_12DD\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nlea ecx, [rax+1]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nloc_12DD:\nsub [rbp+var_20], 1\nloc_12E1:\ncmp [rbp+var_20], 0\njns short loc_1289\nmov [rbp+var_1C], 0\njmp short loc_131F\nloc_12F0:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov eax, [rax]\ncmp eax, 1\njnz short loc_131B\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nadd [rbp+var_24], eax\nloc_131B:\nadd [rbp+var_1C], 1\nloc_131F:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_3C]\njl short loc_12F0\nmov eax, [rbp+var_24]\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1341\ncall ___stack_chk_fail\nlocret_1341:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned __int64 v2; // rax\n void *v3; // rsp\n _BYTE v5[4]; // [rsp+8h] [rbp-40h] BYREF\n int v6; // [rsp+Ch] [rbp-3Ch]\n __int64 v7; // [rsp+10h] [rbp-38h]\n unsigned int v8; // [rsp+24h] [rbp-24h]\n int i; // [rsp+28h] [rbp-20h]\n int j; // [rsp+2Ch] [rbp-1Ch]\n __int64 v11; // [rsp+30h] [rbp-18h]\n _BYTE *v12; // [rsp+38h] [rbp-10h]\n unsigned __int64 v13; // [rsp+40h] [rbp-8h]\n\n v7 = a1;\n v6 = a2;\n v13 = __readfsqword(0x28u);\n v11 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 0x10uLL);\n while ( v5 != &v5[-(v2 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = alloca(v2 & 0xFFF);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)&v5[(v2 & 0xFFF) - 8] = *(_QWORD *)&v5[(v2 & 0xFFF) - 8];\n v12 = v5;\n v8 = 0;\n *(_DWORD *)&v5[4 * v6 - 4] = 1 - *(_DWORD *)(4LL * v6 - 4 + v7);\n for ( i = v6 - 2; i >= 0; --i )\n {\n *(_DWORD *)&v12[4 * i] = *(_DWORD *)&v12[4 * i + 4];\n if ( !*(_DWORD *)(4LL * i + v7) )\n ++*(_DWORD *)&v12[4 * i];\n }\n for ( j = 0; j < v6; ++j )\n {\n if ( *(_DWORD *)(4LL * j + v7) == 1 )\n v8 += *(_DWORD *)&v12[4 * j];\n }\n return v8;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov eax, [rbp+var_3C]\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11F6:\ncmp rsp, rdx\njz short loc_120D\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_11F6\nloc_120D:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1237\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1237:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov [rbp+var_24], 0\nmov eax, [rbp+var_3C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_3C]\nsub edx, 1\nmov ecx, 1\nsub ecx, eax\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nmov eax, [rbp+var_3C]\nsub eax, 2\nmov [rbp+var_20], eax\njmp short loc_12E1\nloc_1289:\nmov eax, [rbp+var_20]\nlea edx, [rax+1]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njnz short loc_12DD\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nlea ecx, [rax+1]\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nloc_12DD:\nsub [rbp+var_20], 1\nloc_12E1:\ncmp [rbp+var_20], 0\njns short loc_1289\nmov [rbp+var_1C], 0\njmp short loc_131F\nloc_12F0:\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov eax, [rax]\ncmp eax, 1\njnz short loc_131B\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nadd [rbp+var_24], eax\nloc_131B:\nadd [rbp+var_1C], 1\nloc_131F:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_3C]\njl short loc_12F0\nmov eax, [rbp+var_24]\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1341\ncall ___stack_chk_fail\nlocret_1341:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2)\n{\n unsigned __int64 v2; // rax\n void *v3; // rsp\n _BYTE v5[4]; // [rsp+8h] [rbp-40h] BYREF\n int v6; // [rsp+Ch] [rbp-3Ch]\n __int64 v7; // [rsp+10h] [rbp-38h]\n unsigned int v8; // [rsp+24h] [rbp-24h]\n int i; // [rsp+28h] [rbp-20h]\n int j; // [rsp+2Ch] [rbp-1Ch]\n __int64 v11; // [rsp+30h] [rbp-18h]\n _BYTE *v12; // [rsp+38h] [rbp-10h]\n unsigned __int64 v13; // [rsp+40h] [rbp-8h]\n\n v7 = a1;\n v6 = a2;\n v13 = __readfsqword(0x28u);\n v11 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 0x10uLL);\n while ( v5 != &v5[-(v2 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v3 = alloca(v2 & 0xFFF);\n if ( (v2 & 0xFFF) != 0 )\n *(_QWORD *)&v5[(v2 & 0xFFF) - 8] = *(_QWORD *)&v5[(v2 & 0xFFF) - 8];\n v12 = v5;\n v8 = 0;\n *(_DWORD *)&v5[4 * v6 - 4] = 1 - *(_DWORD *)(4LL * v6 - 4 + v7);\n for ( i = v6 - 2; i >= 0; --i )\n {\n *(_DWORD *)&v12[4 * i] = *(_DWORD *)&v12[4 * i + 4];\n if ( !*(_DWORD *)(4LL * i + v7) )\n ++*(_DWORD *)&v12[4 * i];\n }\n for ( j = 0; j < v6; ++j )\n {\n if ( *(_DWORD *)(4LL * j + v7) == 1 )\n v8 += *(_DWORD *)&v12[4 * j];\n }\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2) {\n unsigned long long v2;\n void *v3;\n uint8_t v5[4];\n int v6;\n long long v7;\n unsigned int v8;\n int i;\n int j;\n long long v11;\n uint8_t *v12;\n unsigned long long v13;\n v7 = a1;\n v6 = a2;\n v13 = __readfsqword(40u);\n v11 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 16uLL);\n while (v5 != &v5[-(v2 & 18446744073709547520LL)])\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)&v5[(v2 & 4095) - 8] = *(uint64_t *)&v5[(v2 & 4095) - 8];\n v12 = v5;\n v8 = 0;\n *(uint32_t *)&v5[4 * v6 - 4] = 1 - *(uint32_t *)(4LL * v6 - 4 + v7);\n for (i = v6 - 2; i >= 0; --i) {\n *(uint32_t *)&v12[4 * i] = *(uint32_t *)&v12[4 * i + 4];\n if (!*(uint32_t *)(4LL * i + v7)) ++*(uint32_t *)&v12[4 * i];\n }\n for (j = 0; j < v6; ++j) {\n if (*(uint32_t *)(4LL * j + v7) == 1) v8 += *(uint32_t *)&v12[4 * j];\n }\n return v8;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned long long v2;\n void *v3;\n uint8_t v5[4];\n int v6;\n long long v7;\n unsigned int v8;\n int i;\n int j;\n long long v11;\n uint8_t *v12;\n unsigned long long v13;\n v7 = a1;\n v6 = a2;\n v13 = __readfsqword(40u);\n v11 = a2 - 1LL;\n v2 = 16 * ((4LL * a2 + 15) / 16uLL);\n while (v5 != &v5[-(v2 & 18446744073709547520LL)])\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)&v5[(v2 & 4095) - 8] = *(uint64_t *)&v5[(v2 & 4095) - 8];\n v12 = v5;\n v8 = 0;\n *(uint32_t *)&v5[4 * v6 - 4] = 1 - *(uint32_t *)(4LL * v6 - 4 + v7);\n for (i = v6 - 2; i >= 0; --i) {\n *(uint32_t *)&v12[4 * i] = *(uint32_t *)&v12[4 * i + 4];\n if (!*(uint32_t *)(4LL * i + v7)) ++*(uint32_t *)&v12[4 * i];\n }\n for (j = 0; j < v6; ++j) {\n if (*(uint32_t *)(4LL * j + v7) == 1) v8 += *(uint32_t *)&v12[4 * j];\n }\n return v8;\n}" + }, + { + "index": 856, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int noOfZeroes[n];\n int count = 0;\n noOfZeroes[n - 1] = 1 - arr[n - 1];\n for (int i = n - 2; i >= 0; i--) {\n noOfZeroes[i] = noOfZeroes[i + 1];\n if (arr[i] == 0) {\n noOfZeroes[i]++;\n }\n }\n for (int i = 0; i < n; i++) {\n if (arr[i] == 1) {\n count += noOfZeroes[i];\n }\n }\n return count;\n}", + "test": "int main() {\n\n int arr1[] = {1, 0, 1, 0};\n\n int arr2[] = {0, 1, 0};\n\n int arr3[] = {0, 0, 1, 1, 0};\n\n\n\n assert(func0(arr1, 4) == 3);\n\n assert(func0(arr2, 3) == 1);\n\n assert(func0(arr3, 5) == 2);\n\n\n\n printf(\"All test cases passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovslq %esi,%rdx\nshl $0x2,%rdx\nlea 0xf(%rdx),%rax\nmov %rax,%rcx\nand $0xfffffffffffffff0,%rcx\nand $0xfffffffffffff000,%rax\nmov %rsp,%r10\nsub %rax,%r10\nmov %r10,%rax\ncmp %rax,%rsp\nje 11dc \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11c5 \nmov %rcx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 11f2 \norq $0x0,-0x8(%rsp,%rax,1)\nmov %rsp,%r9\nmov %r9,%rcx\nlea -0x1(%rsi),%eax\ncltq\nmov $0x1,%r8d\nsub -0x4(%rdi,%rdx,1),%r8d\nmov %r8d,(%r9,%rax,4)\nmov %esi,%eax\nsub $0x2,%eax\njs 1234 \ncltq\njmp 121f \nsub $0x1,%rax\ntest %eax,%eax\njs 1234 \nmov 0x4(%rcx,%rax,4),%edx\nmov %edx,(%rcx,%rax,4)\ncmpl $0x0,(%rdi,%rax,4)\njne 1217 \nadd $0x1,%edx\nmov %edx,(%rcx,%rax,4)\njmp 1217 \ntest %esi,%esi\njle 1260 \nlea -0x1(%rsi),%esi\nmov $0x0,%eax\nmov $0x0,%r8d\njmp 1254 \nlea 0x1(%rax),%rdx\ncmp %rsi,%rax\nje 1266 \nmov %rdx,%rax\ncmpl $0x1,(%rdi,%rax,4)\njne 1248 \nadd (%rcx,%rax,4),%r8d\njmp 1248 \nmov $0x0,%r8d\nmov -0x8(%rbp),%rax\nxor %fs:0x28,%rax\njne 127a \nmov %r8d,%eax\nleaveq\nretq\ncallq 1080 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov edx, esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmovsxd rsi, esi\nshl rsi, 2\nlea rax, [rsi+0Fh]\nmov r8, rax\nand r8, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rcx, rsp\nsub rcx, rax\nloc_11C4:\ncmp rsp, rcx\njz short loc_11DB\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11C4\nloc_11DB:\nmov rax, r8\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11F1\nor [rsp+rax+10h+var_18], 0\nloc_11F1:\nmov rcx, rsp\nlea eax, [rdx-1]\ncdqe\nmov r8d, 1\nsub r8d, [rdi+rsi-4]\nmov [rcx+rax*4], r8d\nmov eax, edx\nsub eax, 2\njs short loc_1230\ncdqe\njmp short loc_121B\nloc_1213:\nsub rax, 1\ntest eax, eax\njs short loc_124C\nloc_121B:\nmov edx, [rcx+rax*4+4]\nmov [rcx+rax*4], edx\ncmp dword ptr [rdi+rax*4], 0\njnz short loc_1213\nadd edx, 1\nmov [rcx+rax*4], edx\njmp short loc_1213\nloc_1230:\ntest edx, edx\njg short loc_124C\nmov edx, 0\nloc_1239:\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njnz short loc_126C\nmov eax, edx\nleave\nretn\nloc_124C:\nmov eax, 0\nmov edx, 0\njmp short loc_1261\nloc_1258:\nadd rax, 4\ncmp rsi, rax\njz short loc_1239\nloc_1261:\ncmp dword ptr [rdi+rax], 1\njnz short loc_1258\nadd edx, [rcx+rax]\njmp short loc_1258\nloc_126C:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v3; // rsi\n signed __int64 v4; // rax\n void *v5; // rsp\n __int64 v6; // rax\n int v7; // edx\n unsigned int v8; // edx\n __int64 v10; // rax\n _BYTE v12[8]; // [rsp+8h] [rbp-10h] BYREF\n unsigned __int64 v13; // [rsp+10h] [rbp-8h]\n\n v13 = __readfsqword(0x28u);\n v3 = 4LL * a2;\n while ( v12 != &v12[-((v3 + 15) & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v4 = ((_WORD)v3 + 15) & 0xFF0;\n v5 = alloca(v4);\n if ( (((_WORD)v3 + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v12[v4 - 8] = *(_QWORD *)&v12[v4 - 8];\n *(_DWORD *)&v12[4 * a2 - 4] = 1 - *(_DWORD *)(a1 + v3 - 4);\n LODWORD(v6) = a2 - 2;\n if ( a2 - 2 < 0 )\n {\n if ( a2 <= 0 )\n return 0;\n }\n else\n {\n v6 = (int)v6;\n do\n {\n v7 = *(_DWORD *)&v12[4 * v6 + 4];\n *(_DWORD *)&v12[4 * v6] = v7;\n if ( !*(_DWORD *)(a1 + 4 * v6) )\n *(_DWORD *)&v12[4 * v6] = v7 + 1;\n --v6;\n }\n while ( (int)v6 >= 0 );\n }\n v10 = 0LL;\n v8 = 0;\n do\n {\n if ( *(_DWORD *)(a1 + v10) == 1 )\n v8 += *(_DWORD *)&v12[v10];\n v10 += 4LL;\n }\n while ( v3 != v10 );\n return v8;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov edx, esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmovsxd rsi, esi\nshl rsi, 2\nlea rax, [rsi+0Fh]\nmov r8, rax\nand r8, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rcx, rsp\nsub rcx, rax\nloc_11C4:\ncmp rsp, rcx\njz short loc_11DB\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11C4\nloc_11DB:\nmov rax, r8\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11F1\nor [rsp+rax+10h+var_18], 0\nloc_11F1:\nmov rcx, rsp\nlea eax, [rdx-1]\ncdqe\nmov r8d, 1\nsub r8d, [rdi+rsi-4]\nmov [rcx+rax*4], r8d\nmov eax, edx\nsub eax, 2\njs short loc_1230\ncdqe\njmp short loc_121B\nloc_1213:\nsub rax, 1\ntest eax, eax\njs short loc_124C\nloc_121B:\nmov edx, [rcx+rax*4+4]\nmov [rcx+rax*4], edx\ncmp dword ptr [rdi+rax*4], 0\njnz short loc_1213\nadd edx, 1\nmov [rcx+rax*4], edx\njmp short loc_1213\nloc_1230:\ntest edx, edx\njg short loc_124C\nmov edx, 0\nloc_1239:\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njnz short loc_126C\nmov eax, edx\nleave\nretn\nloc_124C:\nmov eax, 0\nmov edx, 0\njmp short loc_1261\nloc_1258:\nadd rax, 4\ncmp rsi, rax\njz short loc_1239\nloc_1261:\ncmp dword ptr [rdi+rax], 1\njnz short loc_1258\nadd edx, [rcx+rax]\njmp short loc_1258\nloc_126C:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2)\n{\n __int64 v3; // rsi\n signed __int64 v4; // rax\n void *v5; // rsp\n __int64 v6; // rax\n int v7; // edx\n unsigned int v8; // edx\n __int64 v10; // rax\n _BYTE v12[8]; // [rsp+8h] [rbp-10h] BYREF\n unsigned __int64 v13; // [rsp+10h] [rbp-8h]\n\n v13 = __readfsqword(0x28u);\n v3 = 4LL * a2;\n while ( v12 != &v12[-((v3 + 15) & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v4 = ((_WORD)v3 + 15) & 0xFF0;\n v5 = alloca(v4);\n if ( (((_WORD)v3 + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v12[v4 - 8] = *(_QWORD *)&v12[v4 - 8];\n *(_DWORD *)&v12[4 * a2 - 4] = 1 - *(_DWORD *)(a1 + v3 - 4);\n LODWORD(v6) = a2 - 2;\n if ( a2 - 2 < 0 )\n {\n if ( a2 <= 0 )\n return 0;\n }\n else\n {\n v6 = (int)v6;\n do\n {\n v7 = *(_DWORD *)&v12[4 * v6 + 4];\n *(_DWORD *)&v12[4 * v6] = v7;\n if ( !*(_DWORD *)(a1 + 4 * v6) )\n *(_DWORD *)&v12[4 * v6] = v7 + 1;\n --v6;\n }\n while ( (int)v6 >= 0 );\n }\n v10 = 0LL;\n v8 = 0;\n do\n {\n if ( *(_DWORD *)(a1 + v10) == 1 )\n v8 += *(_DWORD *)&v12[v10];\n v10 += 4LL;\n }\n while ( v3 != v10 );\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2) {\n long long v3;\n signed long long v4;\n void *v5;\n long long v6;\n int v7;\n unsigned int v8;\n long long v10;\n uint8_t v12[8];\n unsigned long long v13;\n v13 = __readfsqword(40u);\n v3 = 4LL * a2;\n while (v12 != &v12[-((v3 + 15) & 18446744073709547520LL)])\n ;\n v4 = ((unsigned short)v3 + 15) & 4080;\n v5 = alloca(v4);\n if ((((unsigned short)v3 + 15) & 4080) != 0)\n *(uint64_t *)&v12[v4 - 8] = *(uint64_t *)&v12[v4 - 8];\n *(uint32_t *)&v12[4 * a2 - 4] = 1 - *(uint32_t *)(a1 + v3 - 4);\n LODWORD(v6) = a2 - 2;\n if (a2 - 2 < 0) {\n if (a2 <= 0) return 0;\n } else {\n v6 = (int)v6;\n do {\n v7 = *(uint32_t *)&v12[4 * v6 + 4];\n *(uint32_t *)&v12[4 * v6] = v7;\n if (!*(uint32_t *)(a1 + 4 * v6)) *(uint32_t *)&v12[4 * v6] = v7 + 1;\n --v6;\n } while ((int)v6 >= 0);\n }\n v10 = 0LL;\n v8 = 0;\n do {\n if (*(uint32_t *)(a1 + v10) == 1) v8 += *(uint32_t *)&v12[v10];\n v10 += 4LL;\n } while (v3 != v10);\n return v8;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v3;\n signed long long v4;\n void *v5;\n long long v6;\n int v7;\n unsigned int v8;\n long long v10;\n uint8_t v12[8];\n unsigned long long v13;\n v13 = __readfsqword(40u);\n v3 = 4LL * a2;\n while (v12 != &v12[-((v3 + 15) & 18446744073709547520LL)])\n ;\n v4 = ((unsigned short)v3 + 15) & 4080;\n v5 = alloca(v4);\n if ((((unsigned short)v3 + 15) & 4080) != 0)\n *(uint64_t *)&v12[v4 - 8] = *(uint64_t *)&v12[v4 - 8];\n *(uint32_t *)&v12[4 * a2 - 4] = 1 - *(uint32_t *)(a1 + v3 - 4);\n LODWORD(v6) = a2 - 2;\n if (a2 - 2 < 0) {\n if (a2 <= 0) return 0;\n } else {\n v6 = (int)v6;\n do {\n v7 = *(uint32_t *)&v12[4 * v6 + 4];\n *(uint32_t *)&v12[4 * v6] = v7;\n if (!*(uint32_t *)(a1 + 4 * v6)) *(uint32_t *)&v12[4 * v6] = v7 + 1;\n --v6;\n } while ((int)v6 >= 0);\n }\n v10 = 0LL;\n v8 = 0;\n do {\n if (*(uint32_t *)(a1 + v10) == 1) v8 += *(uint32_t *)&v12[v10];\n v10 += 4LL;\n } while (v3 != v10);\n return v8;\n}" + }, + { + "index": 856, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int noOfZeroes[n];\n int count = 0;\n noOfZeroes[n - 1] = 1 - arr[n - 1];\n for (int i = n - 2; i >= 0; i--) {\n noOfZeroes[i] = noOfZeroes[i + 1];\n if (arr[i] == 0) {\n noOfZeroes[i]++;\n }\n }\n for (int i = 0; i < n; i++) {\n if (arr[i] == 1) {\n count += noOfZeroes[i];\n }\n }\n return count;\n}", + "test": "int main() {\n\n int arr1[] = {1, 0, 1, 0};\n\n int arr2[] = {0, 1, 0};\n\n int arr3[] = {0, 0, 1, 1, 0};\n\n\n\n assert(func0(arr1, 4) == 3);\n\n assert(func0(arr2, 3) == 1);\n\n assert(func0(arr3, 5) == 2);\n\n\n\n printf(\"All test cases passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmovslq %esi,%rsi\nmov %rsi,%r8\nshl $0x2,%rsi\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0xf(%rsi),%rax\nmov %rsp,%rcx\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rcx\nand $0xfffffffffffffff0,%rdx\nmov %rcx,%rax\ncmp %rax,%rsp\nje 1309 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 12f4 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 13a0 \nmov $0x1,%edx\nsub -0x4(%rdi,%rsi,1),%edx\nlea -0x1(%r8),%esi\nmov %rsp,%rcx\nmovslq %esi,%rax\nmov %edx,(%rcx,%rax,4)\nmov %r8d,%eax\nsub $0x2,%eax\njs 135e \ncltq\njmp 1344 \nnopl (%rax)\nmov 0x4(%rcx,%rax,4),%edx\nmov (%rdi,%rax,4),%r9d\nmov %edx,(%rcx,%rax,4)\ntest %r9d,%r9d\njne 1356 \nadd $0x1,%edx\nmov %edx,(%rcx,%rax,4)\nsub $0x1,%rax\ntest %eax,%eax\njns 1340 \ntest %r8d,%r8d\njle 13b0 \nmov %esi,%esi\nxor %eax,%eax\nxor %r8d,%r8d\njmp 1373 \nnopl 0x0(%rax)\nmov %rdx,%rax\ncmpl $0x1,(%rdi,%rax,4)\njne 137d \nadd (%rcx,%rax,4),%r8d\nlea 0x1(%rax),%rdx\ncmp %rax,%rsi\njne 1370 \nmov -0x8(%rbp),%rax\nxor %fs:0x28,%rax\njne 13b5 \nleaveq\nmov %r8d,%eax\nretq\nnopw 0x0(%rax,%rax,1)\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 131b \nnopl 0x0(%rax,%rax,1)\nxor %r8d,%r8d\njmp 1386 \ncallq 1080 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmovsxd rsi, esi\nmov rdx, rsi\nshl rsi, 2\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [rsi+0Fh]\nmov r8, rsp\nmov rcx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub r8, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, r8\njz short loc_12F6\nloc_12E1:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, r8\njnz short loc_12E1\nloc_12F6:\nand ecx, 0FFFh\nsub rsp, rcx\ntest rcx, rcx\njnz short loc_1378\nloc_1304:\nlea eax, [rdx-1]\nmov rcx, rsp\nmov r8d, 1\nsub r8d, [rdi+rsi-4]\ncdqe\nmov [rcx+rax*4], r8d\nmov eax, edx\nsub eax, 2\njs short loc_1380\ncdqe\nnop dword ptr [rax+00h]\nloc_1328:\nmov edx, [rcx+rax*4+4]\nmov r8d, [rdi+rax*4]\nmov [rcx+rax*4], edx\ntest r8d, r8d\njnz short loc_133E\nadd edx, 1\nmov [rcx+rax*4], edx\nloc_133E:\nsub rax, 1\ntest eax, eax\njns short loc_1328\nloc_1346:\nxor eax, eax\nxor edx, edx\nnop word ptr [rax+rax+00h]\nloc_1350:\ncmp dword ptr [rdi+rax], 1\njnz short loc_1359\nadd edx, [rcx+rax]\nloc_1359:\nadd rax, 4\ncmp rsi, rax\njnz short loc_1350\nloc_1362:\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njnz short loc_1389\nleave\nmov eax, edx\nretn\nloc_1378:\nor [rsp+rcx+1010h+var_1018], 0\njmp short loc_1304\nloc_1380:\ncmp edx, 1\njz short loc_1346\nxor edx, edx\njmp short loc_1362\nloc_1389:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v3; // rsi\n _BYTE *v4; // r8\n signed __int64 v5; // rcx\n void *v6; // rsp\n __int64 v7; // rax\n int v8; // edx\n int v9; // r8d\n __int64 v10; // rax\n unsigned int v11; // edx\n _BYTE v14[4088]; // [rsp+8h] [rbp-1010h] BYREF\n _QWORD v15[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v3 = 4LL * a2;\n v15[1] = __readfsqword(0x28u);\n v4 = (char *)v15 - ((v3 + 15) & 0xFFFFFFFFFFFFF000LL);\n if ( v15 != (_QWORD *)v4 )\n {\n while ( v14 != v4 )\n ;\n }\n v5 = ((_WORD)v3 + 15) & 0xFF0;\n v6 = alloca(v5);\n if ( (((_WORD)v3 + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v14[v5 - 8] = *(_QWORD *)&v14[v5 - 8];\n *(_DWORD *)&v14[4 * a2 - 4] = 1 - *(_DWORD *)(a1 + v3 - 4);\n LODWORD(v7) = a2 - 2;\n if ( a2 - 2 < 0 )\n {\n if ( a2 != 1 )\n return 0;\n }\n else\n {\n v7 = (int)v7;\n do\n {\n v8 = *(_DWORD *)&v14[4 * v7 + 4];\n v9 = *(_DWORD *)(a1 + 4 * v7);\n *(_DWORD *)&v14[4 * v7] = v8;\n if ( !v9 )\n *(_DWORD *)&v14[4 * v7] = v8 + 1;\n --v7;\n }\n while ( (int)v7 >= 0 );\n }\n v10 = 0LL;\n v11 = 0;\n do\n {\n if ( *(_DWORD *)(a1 + v10) == 1 )\n v11 += *(_DWORD *)&v14[v10];\n v10 += 4LL;\n }\n while ( v3 != v10 );\n return v11;\n}", + "ida_strip_asm": "sub_12A0:\nendbr64\npush rbp\nmovsxd rsi, esi\nmov rdx, rsi\nshl rsi, 2\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [rsi+0Fh]\nmov r8, rsp\nmov rcx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub r8, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, r8\njz short loc_12F6\nloc_12E1:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, r8\njnz short loc_12E1\nloc_12F6:\nand ecx, 0FFFh\nsub rsp, rcx\ntest rcx, rcx\njnz short loc_1378\nloc_1304:\nlea eax, [rdx-1]\nmov rcx, rsp\nmov r8d, 1\nsub r8d, [rdi+rsi-4]\ncdqe\nmov [rcx+rax*4], r8d\nmov eax, edx\nsub eax, 2\njs short loc_1380\ncdqe\nnop dword ptr [rax+00h]\nloc_1328:\nmov edx, [rcx+rax*4+4]\nmov r8d, [rdi+rax*4]\nmov [rcx+rax*4], edx\ntest r8d, r8d\njnz short loc_133E\nadd edx, 1\nmov [rcx+rax*4], edx\nloc_133E:\nsub rax, 1\ntest eax, eax\njns short loc_1328\nloc_1346:\nxor eax, eax\nxor edx, edx\nnop word ptr [rax+rax+00h]\nloc_1350:\ncmp dword ptr [rdi+rax], 1\njnz short loc_1359\nadd edx, [rcx+rax]\nloc_1359:\nadd rax, 4\ncmp rsi, rax\njnz short loc_1350\nloc_1362:\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njnz short loc_1389\nleave\nmov eax, edx\nretn\nloc_1378:\nor [rsp+rcx+1010h+var_1018], 0\njmp short loc_1304\nloc_1380:\ncmp edx, 1\njz short loc_1346\nxor edx, edx\njmp short loc_1362\nloc_1389:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12A0(__int64 a1, int a2)\n{\n __int64 v3; // rsi\n _BYTE *v4; // r8\n signed __int64 v5; // rcx\n void *v6; // rsp\n __int64 v7; // rax\n int v8; // edx\n int v9; // r8d\n __int64 v10; // rax\n unsigned int v11; // edx\n _BYTE v14[4088]; // [rsp+8h] [rbp-1010h] BYREF\n _QWORD v15[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v3 = 4LL * a2;\n v15[1] = __readfsqword(0x28u);\n v4 = (char *)v15 - ((v3 + 15) & 0xFFFFFFFFFFFFF000LL);\n if ( v15 != (_QWORD *)v4 )\n {\n while ( v14 != v4 )\n ;\n }\n v5 = ((_WORD)v3 + 15) & 0xFF0;\n v6 = alloca(v5);\n if ( (((_WORD)v3 + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v14[v5 - 8] = *(_QWORD *)&v14[v5 - 8];\n *(_DWORD *)&v14[4 * a2 - 4] = 1 - *(_DWORD *)(a1 + v3 - 4);\n LODWORD(v7) = a2 - 2;\n if ( a2 - 2 < 0 )\n {\n if ( a2 != 1 )\n return 0;\n }\n else\n {\n v7 = (int)v7;\n do\n {\n v8 = *(_DWORD *)&v14[4 * v7 + 4];\n v9 = *(_DWORD *)(a1 + 4 * v7);\n *(_DWORD *)&v14[4 * v7] = v8;\n if ( !v9 )\n *(_DWORD *)&v14[4 * v7] = v8 + 1;\n --v7;\n }\n while ( (int)v7 >= 0 );\n }\n v10 = 0LL;\n v11 = 0;\n do\n {\n if ( *(_DWORD *)(a1 + v10) == 1 )\n v11 += *(_DWORD *)&v14[v10];\n v10 += 4LL;\n }\n while ( v3 != v10 );\n return v11;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12A0(long long a1, int a2) {\n long long v3;\n uint8_t *v4;\n signed long long v5;\n void *v6;\n long long v7;\n int v8;\n int v9;\n long long v10;\n unsigned int v11;\n uint8_t v14[4088];\n uint64_t v15[2];\n v3 = 4LL * a2;\n v15[1] = __readfsqword(40u);\n v4 = (char *)v15 - ((v3 + 15) & 18446744073709547520LL);\n if (v15 != (uint64_t *)v4) {\n while (v14 != v4)\n ;\n }\n v5 = ((unsigned short)v3 + 15) & 4080;\n v6 = alloca(v5);\n if ((((unsigned short)v3 + 15) & 4080) != 0)\n *(uint64_t *)&v14[v5 - 8] = *(uint64_t *)&v14[v5 - 8];\n *(uint32_t *)&v14[4 * a2 - 4] = 1 - *(uint32_t *)(a1 + v3 - 4);\n LODWORD(v7) = a2 - 2;\n if (a2 - 2 < 0) {\n if (a2 != 1) return 0;\n } else {\n v7 = (int)v7;\n do {\n v8 = *(uint32_t *)&v14[4 * v7 + 4];\n v9 = *(uint32_t *)(a1 + 4 * v7);\n *(uint32_t *)&v14[4 * v7] = v8;\n if (!v9) *(uint32_t *)&v14[4 * v7] = v8 + 1;\n --v7;\n } while ((int)v7 >= 0);\n }\n v10 = 0LL;\n v11 = 0;\n do {\n if (*(uint32_t *)(a1 + v10) == 1) v11 += *(uint32_t *)&v14[v10];\n v10 += 4LL;\n } while (v3 != v10);\n return v11;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v3;\n uint8_t *v4;\n signed long long v5;\n void *v6;\n long long v7;\n int v8;\n int v9;\n long long v10;\n unsigned int v11;\n uint8_t v14[4088];\n uint64_t v15[2];\n v3 = 4LL * a2;\n v15[1] = __readfsqword(40u);\n v4 = (char *)v15 - ((v3 + 15) & 18446744073709547520LL);\n if (v15 != (uint64_t *)v4) {\n while (v14 != v4)\n ;\n }\n v5 = ((unsigned short)v3 + 15) & 4080;\n v6 = alloca(v5);\n if ((((unsigned short)v3 + 15) & 4080) != 0)\n *(uint64_t *)&v14[v5 - 8] = *(uint64_t *)&v14[v5 - 8];\n *(uint32_t *)&v14[4 * a2 - 4] = 1 - *(uint32_t *)(a1 + v3 - 4);\n LODWORD(v7) = a2 - 2;\n if (a2 - 2 < 0) {\n if (a2 != 1) return 0;\n } else {\n v7 = (int)v7;\n do {\n v8 = *(uint32_t *)&v14[4 * v7 + 4];\n v9 = *(uint32_t *)(a1 + 4 * v7);\n *(uint32_t *)&v14[4 * v7] = v8;\n if (!v9) *(uint32_t *)&v14[4 * v7] = v8 + 1;\n --v7;\n } while ((int)v7 >= 0);\n }\n v10 = 0LL;\n v11 = 0;\n do {\n if (*(uint32_t *)(a1 + v10) == 1) v11 += *(uint32_t *)&v14[v10];\n v10 += 4LL;\n } while (v3 != v10);\n return v11;\n}" + }, + { + "index": 856, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int noOfZeroes[n];\n int count = 0;\n noOfZeroes[n - 1] = 1 - arr[n - 1];\n for (int i = n - 2; i >= 0; i--) {\n noOfZeroes[i] = noOfZeroes[i + 1];\n if (arr[i] == 0) {\n noOfZeroes[i]++;\n }\n }\n for (int i = 0; i < n; i++) {\n if (arr[i] == 1) {\n count += noOfZeroes[i];\n }\n }\n return count;\n}", + "test": "int main() {\n\n int arr1[] = {1, 0, 1, 0};\n\n int arr2[] = {0, 1, 0};\n\n int arr3[] = {0, 0, 1, 1, 0};\n\n\n\n assert(func0(arr1, 4) == 3);\n\n assert(func0(arr2, 3) == 1);\n\n assert(func0(arr3, 5) == 2);\n\n\n\n printf(\"All test cases passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmovslq %esi,%rdx\nmov %rdx,%r8\nshl $0x2,%rdx\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0xf(%rdx),%rax\nmov %rsp,%rsi\nmov %rax,%rcx\nand $0xfffffffffffff000,%rax\nsub %rax,%rsi\nand $0xfffffffffffffff0,%rcx\nmov %rsi,%rax\ncmp %rax,%rsp\nje 1309 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 12f4 \nand $0xfff,%ecx\nsub %rcx,%rsp\ntest %rcx,%rcx\njne 13a0 \nlea -0x1(%r8),%esi\nmov %rsp,%rcx\nmov $0x1,%eax\nsub -0x4(%rdi,%rdx,1),%eax\nmovslq %esi,%r9\nmov %eax,(%rcx,%r9,4)\nmov %r8d,%eax\nsub $0x2,%eax\njs 135e \ncltq\nnopl 0x0(%rax)\nmov 0x4(%rcx,%rax,4),%edx\nmov (%rdi,%rax,4),%r9d\nmov %edx,(%rcx,%rax,4)\ntest %r9d,%r9d\njne 1356 \nadd $0x1,%edx\nmov %edx,(%rcx,%rax,4)\nsub $0x1,%rax\ntest %eax,%eax\njns 1340 \ntest %r8d,%r8d\njle 13b0 \nmov %esi,%esi\nxor %eax,%eax\nxor %r8d,%r8d\njmp 1373 \nnopl 0x0(%rax)\nmov %rdx,%rax\ncmpl $0x1,(%rdi,%rax,4)\njne 137d \nadd (%rcx,%rax,4),%r8d\nlea 0x1(%rax),%rdx\ncmp %rax,%rsi\njne 1370 \nmov -0x8(%rbp),%rax\nxor %fs:0x28,%rax\njne 13b5 \nleaveq\nmov %r8d,%eax\nretq\nnopw 0x0(%rax,%rax,1)\norq $0x0,-0x8(%rsp,%rcx,1)\njmpq 131b \nnopl 0x0(%rax,%rax,1)\nxor %r8d,%r8d\njmp 1386 \ncallq 1080 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmovsxd rsi, esi\nmov rdx, rsi\nshl rsi, 2\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [rsi+0Fh]\nmov r8, rsp\nmov rcx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub r8, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, r8\njz short loc_12F6\nloc_12E1:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, r8\njnz short loc_12E1\nloc_12F6:\nand ecx, 0FFFh\nsub rsp, rcx\ntest rcx, rcx\njnz short loc_1378\nloc_1304:\nlea eax, [rdx-1]\nmov rcx, rsp\nmov r8d, 1\nsub r8d, [rdi+rsi-4]\ncdqe\nmov [rcx+rax*4], r8d\nmov eax, edx\nsub eax, 2\njs short loc_1380\ncdqe\nnop dword ptr [rax+00h]\nloc_1328:\nmov edx, [rcx+rax*4+4]\nmov r8d, [rdi+rax*4]\nmov [rcx+rax*4], edx\ntest r8d, r8d\njnz short loc_133E\nadd edx, 1\nmov [rcx+rax*4], edx\nloc_133E:\nsub rax, 1\ntest eax, eax\njns short loc_1328\nloc_1346:\nxor eax, eax\nxor edx, edx\nnop word ptr [rax+rax+00h]\nloc_1350:\ncmp dword ptr [rdi+rax], 1\njnz short loc_1359\nadd edx, [rcx+rax]\nloc_1359:\nadd rax, 4\ncmp rsi, rax\njnz short loc_1350\nloc_1362:\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njnz short loc_1389\nleave\nmov eax, edx\nretn\nloc_1378:\nor [rsp+rcx+1010h+var_1018], 0\njmp short loc_1304\nloc_1380:\ncmp edx, 1\njz short loc_1346\nxor edx, edx\njmp short loc_1362\nloc_1389:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 v3; // rsi\n _BYTE *v4; // r8\n signed __int64 v5; // rcx\n void *v6; // rsp\n __int64 v7; // rax\n int v8; // edx\n int v9; // r8d\n __int64 v10; // rax\n unsigned int v11; // edx\n _BYTE v14[4088]; // [rsp+8h] [rbp-1010h] BYREF\n _QWORD v15[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v3 = 4LL * a2;\n v15[1] = __readfsqword(0x28u);\n v4 = (char *)v15 - ((v3 + 15) & 0xFFFFFFFFFFFFF000LL);\n if ( v15 != (_QWORD *)v4 )\n {\n while ( v14 != v4 )\n ;\n }\n v5 = ((_WORD)v3 + 15) & 0xFF0;\n v6 = alloca(v5);\n if ( (((_WORD)v3 + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v14[v5 - 8] = *(_QWORD *)&v14[v5 - 8];\n *(_DWORD *)&v14[4 * a2 - 4] = 1 - *(_DWORD *)(a1 + v3 - 4);\n LODWORD(v7) = a2 - 2;\n if ( a2 - 2 < 0 )\n {\n if ( a2 != 1 )\n return 0;\n }\n else\n {\n v7 = (int)v7;\n do\n {\n v8 = *(_DWORD *)&v14[4 * v7 + 4];\n v9 = *(_DWORD *)(a1 + 4 * v7);\n *(_DWORD *)&v14[4 * v7] = v8;\n if ( !v9 )\n *(_DWORD *)&v14[4 * v7] = v8 + 1;\n --v7;\n }\n while ( (int)v7 >= 0 );\n }\n v10 = 0LL;\n v11 = 0;\n do\n {\n if ( *(_DWORD *)(a1 + v10) == 1 )\n v11 += *(_DWORD *)&v14[v10];\n v10 += 4LL;\n }\n while ( v3 != v10 );\n return v11;\n}", + "ida_strip_asm": "sub_12A0:\nendbr64\npush rbp\nmovsxd rsi, esi\nmov rdx, rsi\nshl rsi, 2\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [rsi+0Fh]\nmov r8, rsp\nmov rcx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub r8, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, r8\njz short loc_12F6\nloc_12E1:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, r8\njnz short loc_12E1\nloc_12F6:\nand ecx, 0FFFh\nsub rsp, rcx\ntest rcx, rcx\njnz short loc_1378\nloc_1304:\nlea eax, [rdx-1]\nmov rcx, rsp\nmov r8d, 1\nsub r8d, [rdi+rsi-4]\ncdqe\nmov [rcx+rax*4], r8d\nmov eax, edx\nsub eax, 2\njs short loc_1380\ncdqe\nnop dword ptr [rax+00h]\nloc_1328:\nmov edx, [rcx+rax*4+4]\nmov r8d, [rdi+rax*4]\nmov [rcx+rax*4], edx\ntest r8d, r8d\njnz short loc_133E\nadd edx, 1\nmov [rcx+rax*4], edx\nloc_133E:\nsub rax, 1\ntest eax, eax\njns short loc_1328\nloc_1346:\nxor eax, eax\nxor edx, edx\nnop word ptr [rax+rax+00h]\nloc_1350:\ncmp dword ptr [rdi+rax], 1\njnz short loc_1359\nadd edx, [rcx+rax]\nloc_1359:\nadd rax, 4\ncmp rsi, rax\njnz short loc_1350\nloc_1362:\nmov rax, [rbp+var_8]\nsub rax, fs:28h\njnz short loc_1389\nleave\nmov eax, edx\nretn\nloc_1378:\nor [rsp+rcx+1010h+var_1018], 0\njmp short loc_1304\nloc_1380:\ncmp edx, 1\njz short loc_1346\nxor edx, edx\njmp short loc_1362\nloc_1389:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12A0(__int64 a1, int a2)\n{\n __int64 v3; // rsi\n _BYTE *v4; // r8\n signed __int64 v5; // rcx\n void *v6; // rsp\n __int64 v7; // rax\n int v8; // edx\n int v9; // r8d\n __int64 v10; // rax\n unsigned int v11; // edx\n _BYTE v14[4088]; // [rsp+8h] [rbp-1010h] BYREF\n _QWORD v15[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v3 = 4LL * a2;\n v15[1] = __readfsqword(0x28u);\n v4 = (char *)v15 - ((v3 + 15) & 0xFFFFFFFFFFFFF000LL);\n if ( v15 != (_QWORD *)v4 )\n {\n while ( v14 != v4 )\n ;\n }\n v5 = ((_WORD)v3 + 15) & 0xFF0;\n v6 = alloca(v5);\n if ( (((_WORD)v3 + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v14[v5 - 8] = *(_QWORD *)&v14[v5 - 8];\n *(_DWORD *)&v14[4 * a2 - 4] = 1 - *(_DWORD *)(a1 + v3 - 4);\n LODWORD(v7) = a2 - 2;\n if ( a2 - 2 < 0 )\n {\n if ( a2 != 1 )\n return 0;\n }\n else\n {\n v7 = (int)v7;\n do\n {\n v8 = *(_DWORD *)&v14[4 * v7 + 4];\n v9 = *(_DWORD *)(a1 + 4 * v7);\n *(_DWORD *)&v14[4 * v7] = v8;\n if ( !v9 )\n *(_DWORD *)&v14[4 * v7] = v8 + 1;\n --v7;\n }\n while ( (int)v7 >= 0 );\n }\n v10 = 0LL;\n v11 = 0;\n do\n {\n if ( *(_DWORD *)(a1 + v10) == 1 )\n v11 += *(_DWORD *)&v14[v10];\n v10 += 4LL;\n }\n while ( v3 != v10 );\n return v11;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12A0(long long a1, int a2) {\n long long v3;\n uint8_t *v4;\n signed long long v5;\n void *v6;\n long long v7;\n int v8;\n int v9;\n long long v10;\n unsigned int v11;\n uint8_t v14[4088];\n uint64_t v15[2];\n v3 = 4LL * a2;\n v15[1] = __readfsqword(40u);\n v4 = (char *)v15 - ((v3 + 15) & 18446744073709547520LL);\n if (v15 != (uint64_t *)v4) {\n while (v14 != v4)\n ;\n }\n v5 = ((unsigned short)v3 + 15) & 4080;\n v6 = alloca(v5);\n if ((((unsigned short)v3 + 15) & 4080) != 0)\n *(uint64_t *)&v14[v5 - 8] = *(uint64_t *)&v14[v5 - 8];\n *(uint32_t *)&v14[4 * a2 - 4] = 1 - *(uint32_t *)(a1 + v3 - 4);\n LODWORD(v7) = a2 - 2;\n if (a2 - 2 < 0) {\n if (a2 != 1) return 0;\n } else {\n v7 = (int)v7;\n do {\n v8 = *(uint32_t *)&v14[4 * v7 + 4];\n v9 = *(uint32_t *)(a1 + 4 * v7);\n *(uint32_t *)&v14[4 * v7] = v8;\n if (!v9) *(uint32_t *)&v14[4 * v7] = v8 + 1;\n --v7;\n } while ((int)v7 >= 0);\n }\n v10 = 0LL;\n v11 = 0;\n do {\n if (*(uint32_t *)(a1 + v10) == 1) v11 += *(uint32_t *)&v14[v10];\n v10 += 4LL;\n } while (v3 != v10);\n return v11;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long v3;\n uint8_t *v4;\n signed long long v5;\n void *v6;\n long long v7;\n int v8;\n int v9;\n long long v10;\n unsigned int v11;\n uint8_t v14[4088];\n uint64_t v15[2];\n v3 = 4LL * a2;\n v15[1] = __readfsqword(40u);\n v4 = (char *)v15 - ((v3 + 15) & 18446744073709547520LL);\n if (v15 != (uint64_t *)v4) {\n while (v14 != v4)\n ;\n }\n v5 = ((unsigned short)v3 + 15) & 4080;\n v6 = alloca(v5);\n if ((((unsigned short)v3 + 15) & 4080) != 0)\n *(uint64_t *)&v14[v5 - 8] = *(uint64_t *)&v14[v5 - 8];\n *(uint32_t *)&v14[4 * a2 - 4] = 1 - *(uint32_t *)(a1 + v3 - 4);\n LODWORD(v7) = a2 - 2;\n if (a2 - 2 < 0) {\n if (a2 != 1) return 0;\n } else {\n v7 = (int)v7;\n do {\n v8 = *(uint32_t *)&v14[4 * v7 + 4];\n v9 = *(uint32_t *)(a1 + 4 * v7);\n *(uint32_t *)&v14[4 * v7] = v8;\n if (!v9) *(uint32_t *)&v14[4 * v7] = v8 + 1;\n --v7;\n } while ((int)v7 >= 0);\n }\n v10 = 0LL;\n v11 = 0;\n do {\n if (*(uint32_t *)(a1 + v10) == 1) v11 += *(uint32_t *)&v14[v10];\n v10 += 4LL;\n } while (v3 != v10);\n return v11;\n}" + }, + { + "index": 857, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(char** list1, int num_elements, int* sizes) {\n char** result = (char**)malloc(num_elements * sizeof(char*));\n for (int i = 0; i < num_elements; i++) {\n int len = strlen(list1[i]);\n sizes[i] = len;\n result[i] = (char*)malloc((len + 1) * sizeof(char));\n for (int j = 0; j < len; j++) {\n result[i][j] = list1[i][j];\n }\n result[i][len] = '\\0';\n }\n return result;\n}", + "test": "int main() {\n\n int sizes1[5], sizes2[1], sizes3[6];\n\n \n\n char* list1[] = {\"Red\", \"Blue\", \"Black\", \"White\", \"Pink\"};\n\n char** result1 = func0(list1, 5, sizes1);\n\n assert(sizes1[0] == 3 && sizes1[1] == 4);\n\n assert(strcmp(result1[0], \"Red\") == 0 && strcmp(result1[1], \"Blue\") == 0);\n\n\n\n char* list2[] = {\"python\"};\n\n char** result2 = func0(list2, 1, sizes2);\n\n assert(sizes2[0] == 6);\n\n assert(strcmp(result2[0], \"python\") == 0);\n\n\n\n char* list3[] = {\" red \", \"green\", \" black\", \"blue \", \" orange\", \"brown\"};\n\n char** result3 = func0(list3, 6, sizes3);\n\n assert(sizes3[0] == 5 && sizes3[1] == 5);\n\n assert(strcmp(result3[0], \" red \") == 0 && strcmp(result3[1], \"green\") == 0);\n\n\n\n // Free allocated memory\n\n for (int i = 0; i < 5; i++) free(result1[i]);\n\n free(result1);\n\n for (int i = 0; i < 1; i++) free(result2[i]);\n\n free(result2);\n\n for (int i = 0; i < 6; i++) free(result3[i]);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x48,%rsp\nmov %rdi,-0x38(%rbp)\nmov %esi,-0x3c(%rbp)\nmov %rdx,-0x48(%rbp)\nmov -0x3c(%rbp),%eax\ncltq\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 10f0 \nmov %rax,-0x18(%rbp)\nmovl $0x0,-0x24(%rbp)\njmpq 1306 \nmov -0x24(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %eax,-0x1c(%rbp)\nmov -0x24(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x48(%rbp),%rax\nadd %rax,%rdx\nmov -0x1c(%rbp),%eax\nmov %eax,(%rdx)\nmov -0x1c(%rbp),%eax\nadd $0x1,%eax\ncltq\nmov -0x24(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x18(%rbp),%rdx\nlea (%rcx,%rdx,1),%rbx\nmov %rax,%rdi\ncallq 10f0 \nmov %rax,(%rbx)\nmovl $0x0,-0x20(%rbp)\njmp 12d8 \nmov -0x24(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rdx\nmov -0x20(%rbp),%eax\ncltq\nadd %rdx,%rax\nmov -0x24(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rdx),%rcx\nmov -0x20(%rbp),%edx\nmovslq %edx,%rdx\nadd %rcx,%rdx\nmovzbl (%rax),%eax\nmov %al,(%rdx)\naddl $0x1,-0x20(%rbp)\nmov -0x20(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 128f \nmov -0x24(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rdx\nmov -0x1c(%rbp),%eax\ncltq\nadd %rdx,%rax\nmovb $0x0,(%rax)\naddl $0x1,-0x24(%rbp)\nmov -0x24(%rbp),%eax\ncmp -0x3c(%rbp),%eax\njl 1222 \nmov -0x18(%rbp),%rax\nadd $0x48,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 48h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov [rbp+var_48], rdx\nmov eax, [rbp+var_3C]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_24], 0\njmp loc_1306\nloc_1222:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_1C], eax\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rdx, rax\nmov eax, [rbp+var_1C]\nmov [rdx], eax\nmov eax, [rbp+var_1C]\nadd eax, 1\ncdqe\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nlea rbx, [rcx+rdx]\nmov rdi, rax; size\ncall _malloc\nmov [rbx], rax\nmov [rbp+var_20], 0\njmp short loc_12D8\nloc_128F:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_20]\ncdqe\nadd rax, rdx\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov rcx, [rdx]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nadd rdx, rcx\nmovzx eax, byte ptr [rax]\nmov [rdx], al\nadd [rbp+var_20], 1\nloc_12D8:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_1C]\njl short loc_128F\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_1C]\ncdqe\nadd rax, rdx\nmov byte ptr [rax], 0\nadd [rbp+var_24], 1\nloc_1306:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_3C]\njl loc_1222\nmov rax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, int a2, __int64 a3)\n{\n int i; // [rsp+2Ch] [rbp-24h]\n int j; // [rsp+30h] [rbp-20h]\n int v7; // [rsp+34h] [rbp-1Ch]\n _QWORD *v8; // [rsp+38h] [rbp-18h]\n\n v8 = malloc(8LL * a2);\n for ( i = 0; i < a2; ++i )\n {\n v7 = strlen(*(const char **)(8LL * i + a1));\n *(_DWORD *)(a3 + 4LL * i) = v7;\n v8[i] = malloc(v7 + 1);\n for ( j = 0; j < v7; ++j )\n *(_BYTE *)(v8[i] + j) = *(_BYTE *)(*(_QWORD *)(8LL * i + a1) + j);\n *(_BYTE *)(v8[i] + v7) = 0;\n }\n return v8;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 48h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov [rbp+var_48], rdx\nmov eax, [rbp+var_3C]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_24], 0\njmp loc_1306\nloc_1222:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_1C], eax\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rdx, rax\nmov eax, [rbp+var_1C]\nmov [rdx], eax\nmov eax, [rbp+var_1C]\nadd eax, 1\ncdqe\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nlea rbx, [rcx+rdx]\nmov rdi, rax; size\ncall _malloc\nmov [rbx], rax\nmov [rbp+var_20], 0\njmp short loc_12D8\nloc_128F:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_20]\ncdqe\nadd rax, rdx\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov rcx, [rdx]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nadd rdx, rcx\nmovzx eax, byte ptr [rax]\nmov [rdx], al\nadd [rbp+var_20], 1\nloc_12D8:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_1C]\njl short loc_128F\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_1C]\ncdqe\nadd rax, rdx\nmov byte ptr [rax], 0\nadd [rbp+var_24], 1\nloc_1306:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_3C]\njl loc_1222\nmov rax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11E9(__int64 a1, int a2, __int64 a3)\n{\n int i; // [rsp+2Ch] [rbp-24h]\n int j; // [rsp+30h] [rbp-20h]\n int v7; // [rsp+34h] [rbp-1Ch]\n _QWORD *v8; // [rsp+38h] [rbp-18h]\n\n v8 = malloc(8LL * a2);\n for ( i = 0; i < a2; ++i )\n {\n v7 = strlen(*(const char **)(8LL * i + a1));\n *(_DWORD *)(a3 + 4LL * i) = v7;\n v8[i] = malloc(v7 + 1);\n for ( j = 0; j < v7; ++j )\n *(_BYTE *)(v8[i] + j) = *(_BYTE *)(*(_QWORD *)(8LL * i + a1) + j);\n *(_BYTE *)(v8[i] + v7) = 0;\n }\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11E9(long long a1, int a2, long long a3) {\n int i;\n int j;\n int v7;\n uint64_t *v8;\n v8 = malloc(8LL * a2);\n for (i = 0; i < a2; ++i) {\n v7 = strlen(*(const char **)(8LL * i + a1));\n *(uint32_t *)(a3 + 4LL * i) = v7;\n v8[i] = malloc(v7 + 1);\n for (j = 0; j < v7; ++j)\n *(uint8_t *)(v8[i] + j) = *(uint8_t *)(*(uint64_t *)(8LL * i + a1) + j);\n *(uint8_t *)(v8[i] + v7) = 0;\n }\n return v8;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, int a2, long long a3) {\n int i;\n int j;\n int v7;\n uint64_t *v8;\n v8 = malloc(8LL * a2);\n for (i = 0; i < a2; ++i) {\n v7 = strlen(*(const char **)(8LL * i + a1));\n *(uint32_t *)(a3 + 4LL * i) = v7;\n v8[i] = malloc(v7 + 1);\n for (j = 0; j < v7; ++j)\n *(uint8_t *)(v8[i] + j) = *(uint8_t *)(*(uint64_t *)(8LL * i + a1) + j);\n *(uint8_t *)(v8[i] + v7) = 0;\n }\n return v8;\n}" + }, + { + "index": 857, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(char** list1, int num_elements, int* sizes) {\n char** result = (char**)malloc(num_elements * sizeof(char*));\n for (int i = 0; i < num_elements; i++) {\n int len = strlen(list1[i]);\n sizes[i] = len;\n result[i] = (char*)malloc((len + 1) * sizeof(char));\n for (int j = 0; j < len; j++) {\n result[i][j] = list1[i][j];\n }\n result[i][len] = '\\0';\n }\n return result;\n}", + "test": "int main() {\n\n int sizes1[5], sizes2[1], sizes3[6];\n\n \n\n char* list1[] = {\"Red\", \"Blue\", \"Black\", \"White\", \"Pink\"};\n\n char** result1 = func0(list1, 5, sizes1);\n\n assert(sizes1[0] == 3 && sizes1[1] == 4);\n\n assert(strcmp(result1[0], \"Red\") == 0 && strcmp(result1[1], \"Blue\") == 0);\n\n\n\n char* list2[] = {\"python\"};\n\n char** result2 = func0(list2, 1, sizes2);\n\n assert(sizes2[0] == 6);\n\n assert(strcmp(result2[0], \"python\") == 0);\n\n\n\n char* list3[] = {\" red \", \"green\", \" black\", \"blue \", \" orange\", \"brown\"};\n\n char** result3 = func0(list3, 6, sizes3);\n\n assert(sizes3[0] == 5 && sizes3[1] == 5);\n\n assert(strcmp(result3[0], \" red \") == 0 && strcmp(result3[1], \"green\") == 0);\n\n\n\n // Free allocated memory\n\n for (int i = 0; i < 5; i++) free(result1[i]);\n\n free(result1);\n\n for (int i = 0; i < 1; i++) free(result2[i]);\n\n free(result2);\n\n for (int i = 0; i < 6; i++) free(result3[i]);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov %rdi,%rbp\nmov %esi,%ebx\nmov %rdx,%r14\nmovslq %esi,%rdi\nshl $0x3,%rdi\ncallq 10b0 \nmov %rax,0x8(%rsp)\ntest %ebx,%ebx\njle 1263 \nmov %rbp,%r12\nmov %rax,%r13\nlea -0x1(%rbx),%eax\nlea 0x8(%rbp,%rax,8),%r15\njmp 1207 \nmovslq %ebx,%rbx\nmov (%rsi),%rax\nmovb $0x0,(%rax,%rbx,1)\nadd $0x8,%r12\nadd $0x4,%r14\nadd $0x8,%r13\ncmp %r15,%r12\nje 1263 \nmov %r12,%rbp\nmov (%r12),%rdi\nmov $0x0,%eax\nmov $0xffffffffffffffff,%rcx\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rbx\nmov %ebx,(%r14)\nlea 0x1(%rbx),%edi\nmovslq %edi,%rdi\ncallq 10b0 \nmov %r13,%rsi\nmov %rax,0x0(%r13)\ntest %ebx,%ebx\njle 11ec \nlea -0x1(%rbx),%edi\nmov $0x0,%eax\nmov 0x0(%rbp),%rdx\nmovzbl (%rdx,%rax,1),%ecx\nmov (%rsi),%rdx\nmov %cl,(%rdx,%rax,1)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rdi,%rdx\njne 1247 \njmp 11ec \nmov 0x8(%rsp),%rax\nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12, rdi\nmov ebx, esi\nmov r14, rdx\nmovsxd r15, esi\nlea rdi, ds:0[r15*8]; size\ncall _malloc\nmov r13, rax\ntest ebx, ebx\njle short loc_1272\nmov ebp, 0\nloc_121F:\nmov rdi, [r12+rbp*8]; s\ncall _strlen\nmov rbx, rax\nmov [r14+rbp*4], eax\nlea edi, [rax+1]\nmovsxd rdi, edi; size\ncall _malloc\nmov [r13+rbp*8+0], rax\ntest ebx, ebx\njle short loc_1262\nmov rdi, [r12+rbp*8]\nlea esi, [rbx-1]\nmov edx, 0\nloc_124F:\nmovzx ecx, byte ptr [rdi+rdx]\nmov [rax+rdx], cl\nmov rcx, rdx\nadd rdx, 1\ncmp rcx, rsi\njnz short loc_124F\nloc_1262:\nmovsxd rbx, ebx\nmov byte ptr [rax+rbx], 0\nadd rbp, 1\ncmp r15, rbp\njnz short loc_121F\nloc_1272:\nmov rax, r13\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, int a2, __int64 a3)\n{\n _QWORD *v5; // r13\n __int64 i; // rbp\n int v7; // ebx\n _BYTE *v8; // rax\n __int64 v9; // rdi\n __int64 v10; // rdx\n __int64 v11; // rcx\n\n v5 = malloc(8LL * a2);\n if ( a2 > 0 )\n {\n for ( i = 0LL; i != a2; ++i )\n {\n v7 = strlen(*(const char **)(a1 + 8 * i));\n *(_DWORD *)(a3 + 4 * i) = v7;\n v8 = malloc(v7 + 1);\n v5[i] = v8;\n if ( v7 > 0 )\n {\n v9 = *(_QWORD *)(a1 + 8 * i);\n v10 = 0LL;\n do\n {\n v8[v10] = *(_BYTE *)(v9 + v10);\n v11 = v10++;\n }\n while ( v11 != v7 - 1 );\n }\n v8[v7] = 0;\n }\n }\n return v5;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12, rdi\nmov ebx, esi\nmov r14, rdx\nmovsxd r15, esi\nlea rdi, ds:0[r15*8]; size\ncall _malloc\nmov r13, rax\ntest ebx, ebx\njle short loc_1272\nmov ebp, 0\nloc_121F:\nmov rdi, [r12+rbp*8]; s\ncall _strlen\nmov rbx, rax\nmov [r14+rbp*4], eax\nlea edi, [rax+1]\nmovsxd rdi, edi; size\ncall _malloc\nmov [r13+rbp*8+0], rax\ntest ebx, ebx\njle short loc_1262\nmov rdi, [r12+rbp*8]\nlea esi, [rbx-1]\nmov edx, 0\nloc_124F:\nmovzx ecx, byte ptr [rdi+rdx]\nmov [rax+rdx], cl\nmov rcx, rdx\nadd rdx, 1\ncmp rcx, rsi\njnz short loc_124F\nloc_1262:\nmovsxd rbx, ebx\nmov byte ptr [rax+rbx], 0\nadd rbp, 1\ncmp r15, rbp\njnz short loc_121F\nloc_1272:\nmov rax, r13\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11E9(__int64 a1, int a2, __int64 a3)\n{\n _QWORD *v5; // r13\n __int64 i; // rbp\n int v7; // ebx\n _BYTE *v8; // rax\n __int64 v9; // rdi\n __int64 v10; // rdx\n __int64 v11; // rcx\n\n v5 = malloc(8LL * a2);\n if ( a2 > 0 )\n {\n for ( i = 0LL; i != a2; ++i )\n {\n v7 = strlen(*(const char **)(a1 + 8 * i));\n *(_DWORD *)(a3 + 4 * i) = v7;\n v8 = malloc(v7 + 1);\n v5[i] = v8;\n if ( v7 > 0 )\n {\n v9 = *(_QWORD *)(a1 + 8 * i);\n v10 = 0LL;\n do\n {\n v8[v10] = *(_BYTE *)(v9 + v10);\n v11 = v10++;\n }\n while ( v11 != v7 - 1 );\n }\n v8[v7] = 0;\n }\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11E9(long long a1, int a2, long long a3) {\n uint64_t *v5;\n long long i;\n int v7;\n uint8_t *v8;\n long long v9;\n long long v10;\n long long v11;\n v5 = malloc(8LL * a2);\n if (a2 > 0) {\n for (i = 0LL; i != a2; ++i) {\n v7 = strlen(*(const char **)(a1 + 8 * i));\n *(uint32_t *)(a3 + 4 * i) = v7;\n v8 = malloc(v7 + 1);\n v5[i] = v8;\n if (v7 > 0) {\n v9 = *(uint64_t *)(a1 + 8 * i);\n v10 = 0LL;\n do {\n v8[v10] = *(uint8_t *)(v9 + v10);\n v11 = v10++;\n } while (v11 != v7 - 1);\n }\n v8[v7] = 0;\n }\n }\n return v5;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, int a2, long long a3) {\n uint64_t *v5;\n long long i;\n int v7;\n uint8_t *v8;\n long long v9;\n long long v10;\n long long v11;\n v5 = malloc(8LL * a2);\n if (a2 > 0) {\n for (i = 0LL; i != a2; ++i) {\n v7 = strlen(*(const char **)(a1 + 8 * i));\n *(uint32_t *)(a3 + 4 * i) = v7;\n v8 = malloc(v7 + 1);\n v5[i] = v8;\n if (v7 > 0) {\n v9 = *(uint64_t *)(a1 + 8 * i);\n v10 = 0LL;\n do {\n v8[v10] = *(uint8_t *)(v9 + v10);\n v11 = v10++;\n } while (v11 != v7 - 1);\n }\n v8[v7] = 0;\n }\n }\n return v5;\n}" + }, + { + "index": 857, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(char** list1, int num_elements, int* sizes) {\n char** result = (char**)malloc(num_elements * sizeof(char*));\n for (int i = 0; i < num_elements; i++) {\n int len = strlen(list1[i]);\n sizes[i] = len;\n result[i] = (char*)malloc((len + 1) * sizeof(char));\n for (int j = 0; j < len; j++) {\n result[i][j] = list1[i][j];\n }\n result[i][len] = '\\0';\n }\n return result;\n}", + "test": "int main() {\n\n int sizes1[5], sizes2[1], sizes3[6];\n\n \n\n char* list1[] = {\"Red\", \"Blue\", \"Black\", \"White\", \"Pink\"};\n\n char** result1 = func0(list1, 5, sizes1);\n\n assert(sizes1[0] == 3 && sizes1[1] == 4);\n\n assert(strcmp(result1[0], \"Red\") == 0 && strcmp(result1[1], \"Blue\") == 0);\n\n\n\n char* list2[] = {\"python\"};\n\n char** result2 = func0(list2, 1, sizes2);\n\n assert(sizes2[0] == 6);\n\n assert(strcmp(result2[0], \"python\") == 0);\n\n\n\n char* list3[] = {\" red \", \"green\", \" black\", \"blue \", \" orange\", \"brown\"};\n\n char** result3 = func0(list3, 6, sizes3);\n\n assert(sizes3[0] == 5 && sizes3[1] == 5);\n\n assert(strcmp(result3[0], \" red \") == 0 && strcmp(result3[1], \"green\") == 0);\n\n\n\n // Free allocated memory\n\n for (int i = 0; i < 5; i++) free(result1[i]);\n\n free(result1);\n\n for (int i = 0; i < 1; i++) free(result2[i]);\n\n free(result2);\n\n for (int i = 0; i < 6; i++) free(result3[i]);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\nmov %rdi,%r14\nmovslq %esi,%rdi\npush %r13\npush %r12\npush %rbp\nmov %rdi,%rbp\nshl $0x3,%rdi\npush %rbx\nmov %rdx,%rbx\nsub $0x18,%rsp\ncallq 10d0 \nmov %rax,0x8(%rsp)\ntest %ebp,%ebp\njle 1586 \nmov %rax,%r15\nlea -0x1(%rbp),%eax\nlea 0x8(%r14,%rax,8),%rbp\nnopl 0x0(%rax,%rax,1)\nmov (%r14),%r13\nmov %r13,%rdi\ncallq 10a0 \nmov %eax,(%rbx)\nlea 0x1(%rax),%edi\nmov %rax,%r12\nmovslq %edi,%rdi\ncallq 10d0 \nmov %rax,(%r15)\ntest %r12d,%r12d\njle 156e \nlea -0x1(%r12),%edi\nxor %edx,%edx\njmp 1559 \nnopl 0x0(%rax)\nmov (%r14),%r13\nmov (%r15),%rax\nmov %rcx,%rdx\nmovzbl 0x0(%r13,%rdx,1),%ecx\nmov %cl,(%rax,%rdx,1)\nlea 0x1(%rdx),%rcx\ncmp %rdi,%rdx\njne 1550 \nmov (%r15),%rax\nmovslq %r12d,%rsi\nadd $0x8,%r14\nadd $0x4,%rbx\nadd $0x8,%r15\nmovb $0x0,(%rax,%rsi,1)\ncmp %rbp,%r14\njne 1520 \nmov 0x8(%rsp),%rax\nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmovsxd rax, esi\npush r14\nmov r14, rax\npush r13\npush r12\nmov r12, rdx\npush rbp\nmov rbp, rdi\nlea rdi, ds:0[rax*8]; size\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rax\ncall _malloc\nmov rbx, rax\ntest r14d, r14d\njle short loc_15A7\nxor r13d, r13d\nnop dword ptr [rax+rax+00h]\nloc_1550:\nmov r14, [rbp+r13*8+0]\nmov rdi, r14; s\ncall _strlen\nmov [r12+r13*4], eax\nlea edi, [rax+1]\nmov r15, rax\nmovsxd rdi, edi; size\ncall _malloc\nmov [rbx+r13*8], rax\ntest r15d, r15d\njle short loc_1594\nlea esi, [r15-1]\nxor edx, edx\nxchg ax, ax\nloc_1580:\nmovzx ecx, byte ptr [r14+rdx]\nmov [rax+rdx], cl\nmov rcx, rdx\nadd rdx, 1\ncmp rsi, rcx\njnz short loc_1580\nloc_1594:\nmovsxd r15, r15d\nadd r13, 1\nmov byte ptr [rax+r15], 0\ncmp [rsp+48h+var_40], r13\njnz short loc_1550\nloc_15A7:\nadd rsp, 18h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, int a2, __int64 a3)\n{\n _QWORD *v4; // rbx\n __int64 i; // r13\n const char *v6; // r14\n int v7; // eax\n int v8; // r15d\n _BYTE *v9; // rax\n __int64 v10; // rdx\n __int64 v11; // rcx\n\n v4 = malloc(8LL * a2);\n if ( a2 > 0 )\n {\n for ( i = 0LL; i != a2; ++i )\n {\n v6 = *(const char **)(a1 + 8 * i);\n v7 = strlen(v6);\n *(_DWORD *)(a3 + 4 * i) = v7;\n v8 = v7;\n v9 = malloc(v7 + 1);\n v4[i] = v9;\n if ( v8 > 0 )\n {\n v10 = 0LL;\n do\n {\n v9[v10] = v6[v10];\n v11 = v10++;\n }\n while ( v8 - 1 != v11 );\n }\n v9[v8] = 0;\n }\n }\n return v4;\n}", + "ida_strip_asm": "sub_1510:\nendbr64\npush r15\nmovsxd rax, esi\npush r14\nmov r14, rax\npush r13\npush r12\nmov r12, rdx\npush rbp\nmov rbp, rdi\nlea rdi, ds:0[rax*8]; size\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rax\ncall _malloc\nmov rbx, rax\ntest r14d, r14d\njle short loc_15A7\nxor r13d, r13d\nnop dword ptr [rax+rax+00h]\nloc_1550:\nmov r14, [rbp+r13*8+0]\nmov rdi, r14; s\ncall _strlen\nmov [r12+r13*4], eax\nlea edi, [rax+1]\nmov r15, rax\nmovsxd rdi, edi; size\ncall _malloc\nmov [rbx+r13*8], rax\ntest r15d, r15d\njle short loc_1594\nlea esi, [r15-1]\nxor edx, edx\nxchg ax, ax\nloc_1580:\nmovzx ecx, byte ptr [r14+rdx]\nmov [rax+rdx], cl\nmov rcx, rdx\nadd rdx, 1\ncmp rsi, rcx\njnz short loc_1580\nloc_1594:\nmovsxd r15, r15d\nadd r13, 1\nmov byte ptr [rax+r15], 0\ncmp [rsp+48h+var_40], r13\njnz short loc_1550\nloc_15A7:\nadd rsp, 18h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1510(__int64 a1, int a2, __int64 a3)\n{\n _QWORD *v4; // rbx\n __int64 i; // r13\n const char *v6; // r14\n int v7; // eax\n int v8; // r15d\n _BYTE *v9; // rax\n __int64 v10; // rdx\n __int64 v11; // rcx\n\n v4 = malloc(8LL * a2);\n if ( a2 > 0 )\n {\n for ( i = 0LL; i != a2; ++i )\n {\n v6 = *(const char **)(a1 + 8 * i);\n v7 = strlen(v6);\n *(_DWORD *)(a3 + 4 * i) = v7;\n v8 = v7;\n v9 = malloc(v7 + 1);\n v4[i] = v9;\n if ( v8 > 0 )\n {\n v10 = 0LL;\n do\n {\n v9[v10] = v6[v10];\n v11 = v10++;\n }\n while ( v8 - 1 != v11 );\n }\n v9[v8] = 0;\n }\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1510(long long a1, int a2, long long a3) {\n uint64_t *v4;\n long long i;\n const char *v6;\n int v7;\n int v8;\n uint8_t *v9;\n long long v10;\n long long v11;\n v4 = malloc(8LL * a2);\n if (a2 > 0) {\n for (i = 0LL; i != a2; ++i) {\n v6 = *(const char **)(a1 + 8 * i);\n v7 = strlen(v6);\n *(uint32_t *)(a3 + 4 * i) = v7;\n v8 = v7;\n v9 = malloc(v7 + 1);\n v4[i] = v9;\n if (v8 > 0) {\n v10 = 0LL;\n do {\n v9[v10] = v6[v10];\n v11 = v10++;\n } while (v8 - 1 != v11);\n }\n v9[v8] = 0;\n }\n }\n return v4;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, int a2, long long a3) {\n uint64_t *v4;\n long long i;\n const char *v6;\n int v7;\n int v8;\n uint8_t *v9;\n long long v10;\n long long v11;\n v4 = malloc(8LL * a2);\n if (a2 > 0) {\n for (i = 0LL; i != a2; ++i) {\n v6 = *(const char **)(a1 + 8 * i);\n v7 = strlen(v6);\n *(uint32_t *)(a3 + 4 * i) = v7;\n v8 = v7;\n v9 = malloc(v7 + 1);\n v4[i] = v9;\n if (v8 > 0) {\n v10 = 0LL;\n do {\n v9[v10] = v6[v10];\n v11 = v10++;\n } while (v8 - 1 != v11);\n }\n v9[v8] = 0;\n }\n }\n return v4;\n}" + }, + { + "index": 857, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(char** list1, int num_elements, int* sizes) {\n char** result = (char**)malloc(num_elements * sizeof(char*));\n for (int i = 0; i < num_elements; i++) {\n int len = strlen(list1[i]);\n sizes[i] = len;\n result[i] = (char*)malloc((len + 1) * sizeof(char));\n for (int j = 0; j < len; j++) {\n result[i][j] = list1[i][j];\n }\n result[i][len] = '\\0';\n }\n return result;\n}", + "test": "int main() {\n\n int sizes1[5], sizes2[1], sizes3[6];\n\n \n\n char* list1[] = {\"Red\", \"Blue\", \"Black\", \"White\", \"Pink\"};\n\n char** result1 = func0(list1, 5, sizes1);\n\n assert(sizes1[0] == 3 && sizes1[1] == 4);\n\n assert(strcmp(result1[0], \"Red\") == 0 && strcmp(result1[1], \"Blue\") == 0);\n\n\n\n char* list2[] = {\"python\"};\n\n char** result2 = func0(list2, 1, sizes2);\n\n assert(sizes2[0] == 6);\n\n assert(strcmp(result2[0], \"python\") == 0);\n\n\n\n char* list3[] = {\" red \", \"green\", \" black\", \"blue \", \" orange\", \"brown\"};\n\n char** result3 = func0(list3, 6, sizes3);\n\n assert(sizes3[0] == 5 && sizes3[1] == 5);\n\n assert(strcmp(result3[0], \" red \") == 0 && strcmp(result3[1], \"green\") == 0);\n\n\n\n // Free allocated memory\n\n for (int i = 0; i < 5; i++) free(result1[i]);\n\n free(result1);\n\n for (int i = 0; i < 1; i++) free(result2[i]);\n\n free(result2);\n\n for (int i = 0; i < 6; i++) free(result3[i]);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\nmov %rdi,%r13\nmovslq %esi,%rdi\npush %r12\npush %rbp\nmov %rdi,%rbp\nshl $0x3,%rdi\npush %rbx\nmov %rdx,%rbx\nsub $0x18,%rsp\ncallq 10d0 \nmov %rax,0x8(%rsp)\ntest %ebp,%ebp\njle 15bb \nmov %rax,%r14\nlea -0x1(%rbp),%eax\nlea 0x8(%r13,%rax,8),%rbp\nmov 0x0(%r13),%r12\nmov %r12,%rdi\ncallq 10a0 \nmov %eax,(%rbx)\nlea 0x1(%rax),%edi\nmov %rax,%r15\nmovslq %edi,%rdi\ncallq 10d0 \nmov %rax,(%r14)\nmov %rax,%rdx\ntest %r15d,%r15d\njle 15a2 \nmovzbl (%r12),%edx\nmov %dl,(%rax)\ncmp $0x1,%r15d\nje 159f \nlea -0x2(%r15),%esi\nmov $0x1,%eax\nadd $0x2,%rsi\nnopl 0x0(%rax)\nmov 0x0(%r13),%rdx\nmovzbl (%rdx,%rax,1),%ecx\nmov (%r14),%rdx\nmov %cl,(%rdx,%rax,1)\nadd $0x1,%rax\ncmp %rax,%rsi\njne 1588 \nmov (%r14),%rdx\nmovslq %r15d,%r15\nadd $0x8,%r13\nadd $0x4,%rbx\nadd $0x8,%r14\nmovb $0x0,(%rdx,%r15,1)\ncmp %r13,%rbp\njne 1540 \nmov 0x8(%rsp),%rax\nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\nmovsxd rax, esi\npush r14\nmov r14, rax\npush r13\npush r12\nmov r12, rdx\npush rbp\nmov rbp, rdi\nlea rdi, ds:0[rax*8]; size\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rax\ncall _malloc\nmov rbx, rax\ntest r14d, r14d\njle short loc_15C7\nxor r13d, r13d\nnop dword ptr [rax+rax+00h]\nloc_1550:\nmov r15, [rbp+r13*8+0]\nmov rdi, r15; s\ncall _strlen\nmov [r12+r13*4], eax\nlea edi, [rax+1]\nmov r14, rax\nmovsxd rdi, edi; size\ncall _malloc\nmov [rbx+r13*8], rax\nmov rdx, rax\ntest r14d, r14d\njle short loc_15B4\nlea edi, [r14-1]\nmov r8d, r14d\ncmp edi, 6\njbe short loc_1594\nlea rcx, [r15+1]\nsub rax, rcx\ncmp rax, 0Eh\nja short loc_15E0\nloc_1594:\nxor eax, eax\nnop word ptr [rax+rax+00000000h]\nloc_15A0:\nmovzx ecx, byte ptr [r15+rax]\nmov [rdx+rax], cl\nmov rcx, rax\nadd rax, 1\ncmp rcx, rdi\njnz short loc_15A0\nloc_15B4:\nmovsxd r14, r14d\nadd r13, 1\nmov byte ptr [rdx+r14], 0\ncmp [rsp+48h+var_40], r13\njnz short loc_1550\nloc_15C7:\nadd rsp, 18h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15E0:\ncmp edi, 0Eh\njbe loc_16E1\nmov ecx, r14d\nxor eax, eax\nshr ecx, 4\nshl rcx, 4\nnop dword ptr [rax]\nloc_15F8:\nmovdqu xmm0, xmmword ptr [r15+rax]\nmovups xmmword ptr [rdx+rax], xmm0\nadd rax, 10h\ncmp rax, rcx\njnz short loc_15F8\nmov ecx, r14d\nand ecx, 0FFFFFFF0h\nmov eax, ecx\ntest r14b, 0Fh\njz short loc_15B4\nmov r8d, r14d\nsub r8d, ecx\nlea edi, [r8-1]\ncmp edi, 6\njbe short loc_1642\nloc_1628:\nmov rdi, [r15+rcx]\nmov [rdx+rcx], rdi\nmov ecx, r8d\nand ecx, 0FFFFFFF8h\nadd eax, ecx\nand r8d, 7\njz loc_15B4\nloc_1642:\nmovsxd rcx, eax\nmovzx edi, byte ptr [r15+rcx]\nmov [rdx+rcx], dil\nlea ecx, [rax+1]\ncmp r14d, ecx\njle loc_15B4\nmovsxd rcx, ecx\nmovzx edi, byte ptr [r15+rcx]\nmov [rdx+rcx], dil\nlea ecx, [rax+2]\ncmp r14d, ecx\njle loc_15B4\nmovsxd rcx, ecx\nmovzx edi, byte ptr [r15+rcx]\nmov [rdx+rcx], dil\nlea ecx, [rax+3]\ncmp r14d, ecx\njle loc_15B4\nmovsxd rcx, ecx\nmovzx edi, byte ptr [r15+rcx]\nmov [rdx+rcx], dil\nlea ecx, [rax+4]\ncmp r14d, ecx\njle loc_15B4\nmovsxd rcx, ecx\nmovzx edi, byte ptr [r15+rcx]\nmov [rdx+rcx], dil\nlea ecx, [rax+5]\ncmp r14d, ecx\njle loc_15B4\nmovsxd rcx, ecx\nadd eax, 6\nmovzx edi, byte ptr [r15+rcx]\nmov [rdx+rcx], dil\ncmp r14d, eax\njle loc_15B4\ncdqe\nmovzx ecx, byte ptr [r15+rax]\nmov [rdx+rax], cl\njmp loc_15B4\nloc_16E1:\nxor ecx, ecx\nxor eax, eax\njmp loc_1628", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, int a2, __int64 a3)\n{\n _QWORD *v5; // rbx\n __int64 i; // r13\n const char *v7; // r15\n int v8; // eax\n int v9; // r14d\n _BYTE *v10; // rax\n _BYTE *v11; // rdx\n __int64 v12; // rdi\n int v13; // r8d\n __int64 v14; // rax\n __int64 v15; // rcx\n __int64 v17; // rax\n __int64 v18; // rcx\n signed int v19; // eax\n int v20; // ecx\n int v21; // eax\n\n v5 = malloc(8LL * a2);\n if ( a2 > 0 )\n {\n for ( i = 0LL; a2 != i; ++i )\n {\n v7 = *(const char **)(a1 + 8 * i);\n v8 = strlen(v7);\n *(_DWORD *)(a3 + 4 * i) = v8;\n v9 = v8;\n v10 = malloc(v8 + 1);\n v5[i] = v10;\n v11 = v10;\n if ( v9 > 0 )\n {\n v12 = (unsigned int)(v9 - 1);\n v13 = v9;\n if ( (unsigned int)v12 > 6 && (unsigned __int64)(v10 - (v7 + 1)) > 0xE )\n {\n if ( (unsigned int)v12 <= 0xE )\n {\n v18 = 0LL;\n v19 = 0;\n }\n else\n {\n v17 = 0LL;\n do\n {\n *(__m128i *)&v11[v17] = _mm_loadu_si128((const __m128i *)&v7[v17]);\n v17 += 16LL;\n }\n while ( v17 != 16LL * ((unsigned int)v9 >> 4) );\n v18 = v9 & 0xFFFFFFF0;\n v19 = v9 & 0xFFFFFFF0;\n if ( (v9 & 0xF) == 0 )\n goto LABEL_8;\n v13 = v9 - v18;\n if ( (unsigned int)(v9 - v18 - 1) <= 6 )\n goto LABEL_16;\n }\n *(_QWORD *)&v11[v18] = *(_QWORD *)&v7[v18];\n v19 += v13 & 0xFFFFFFF8;\n if ( (v13 & 7) != 0 )\n {\nLABEL_16:\n v11[v19] = v7[v19];\n if ( v9 > v19 + 1 )\n {\n v11[v19 + 1] = v7[v19 + 1];\n if ( v9 > v19 + 2 )\n {\n v11[v19 + 2] = v7[v19 + 2];\n if ( v9 > v19 + 3 )\n {\n v11[v19 + 3] = v7[v19 + 3];\n if ( v9 > v19 + 4 )\n {\n v11[v19 + 4] = v7[v19 + 4];\n v20 = v19 + 5;\n if ( v9 > v19 + 5 )\n {\n v21 = v19 + 6;\n v11[v20] = v7[v20];\n if ( v9 > v21 )\n v11[v21] = v7[v21];\n }\n }\n }\n }\n }\n }\n }\n else\n {\n v14 = 0LL;\n do\n {\n v11[v14] = v7[v14];\n v15 = v14++;\n }\n while ( v15 != v12 );\n }\n }\nLABEL_8:\n v11[v9] = 0;\n }\n }\n return v5;\n}", + "ida_strip_asm": "sub_1510:\nendbr64\npush r15\nmovsxd rax, esi\npush r14\nmov r14, rax\npush r13\npush r12\nmov r12, rdx\npush rbp\nmov rbp, rdi\nlea rdi, ds:0[rax*8]; size\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rax\ncall _malloc\nmov rbx, rax\ntest r14d, r14d\njle short loc_15C7\nxor r13d, r13d\nnop dword ptr [rax+rax+00h]\nloc_1550:\nmov r15, [rbp+r13*8+0]\nmov rdi, r15; s\ncall _strlen\nmov [r12+r13*4], eax\nlea edi, [rax+1]\nmov r14, rax\nmovsxd rdi, edi; size\ncall _malloc\nmov [rbx+r13*8], rax\nmov rdx, rax\ntest r14d, r14d\njle short loc_15B4\nlea edi, [r14-1]\nmov r8d, r14d\ncmp edi, 6\njbe short loc_1594\nlea rcx, [r15+1]\nsub rax, rcx\ncmp rax, 0Eh\nja short loc_15E0\nloc_1594:\nxor eax, eax\nnop word ptr [rax+rax+00000000h]\nloc_15A0:\nmovzx ecx, byte ptr [r15+rax]\nmov [rdx+rax], cl\nmov rcx, rax\nadd rax, 1\ncmp rcx, rdi\njnz short loc_15A0\nloc_15B4:\nmovsxd r14, r14d\nadd r13, 1\nmov byte ptr [rdx+r14], 0\ncmp [rsp+48h+var_40], r13\njnz short loc_1550\nloc_15C7:\nadd rsp, 18h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15E0:\ncmp edi, 0Eh\njbe loc_16E1\nmov ecx, r14d\nxor eax, eax\nshr ecx, 4\nshl rcx, 4\nnop dword ptr [rax]\nloc_15F8:\nmovdqu xmm0, xmmword ptr [r15+rax]\nmovups xmmword ptr [rdx+rax], xmm0\nadd rax, 10h\ncmp rax, rcx\njnz short loc_15F8\nmov ecx, r14d\nand ecx, 0FFFFFFF0h\nmov eax, ecx\ntest r14b, 0Fh\njz short loc_15B4\nmov r8d, r14d\nsub r8d, ecx\nlea edi, [r8-1]\ncmp edi, 6\njbe short loc_1642\nloc_1628:\nmov rdi, [r15+rcx]\nmov [rdx+rcx], rdi\nmov ecx, r8d\nand ecx, 0FFFFFFF8h\nadd eax, ecx\nand r8d, 7\njz loc_15B4\nloc_1642:\nmovsxd rcx, eax\nmovzx edi, byte ptr [r15+rcx]\nmov [rdx+rcx], dil\nlea ecx, [rax+1]\ncmp r14d, ecx\njle loc_15B4\nmovsxd rcx, ecx\nmovzx edi, byte ptr [r15+rcx]\nmov [rdx+rcx], dil\nlea ecx, [rax+2]\ncmp r14d, ecx\njle loc_15B4\nmovsxd rcx, ecx\nmovzx edi, byte ptr [r15+rcx]\nmov [rdx+rcx], dil\nlea ecx, [rax+3]\ncmp r14d, ecx\njle loc_15B4\nmovsxd rcx, ecx\nmovzx edi, byte ptr [r15+rcx]\nmov [rdx+rcx], dil\nlea ecx, [rax+4]\ncmp r14d, ecx\njle loc_15B4\nmovsxd rcx, ecx\nmovzx edi, byte ptr [r15+rcx]\nmov [rdx+rcx], dil\nlea ecx, [rax+5]\ncmp r14d, ecx\njle loc_15B4\nmovsxd rcx, ecx\nadd eax, 6\nmovzx edi, byte ptr [r15+rcx]\nmov [rdx+rcx], dil\ncmp r14d, eax\njle loc_15B4\ncdqe\nmovzx ecx, byte ptr [r15+rax]\nmov [rdx+rax], cl\njmp loc_15B4\nloc_16E1:\nxor ecx, ecx\nxor eax, eax\njmp loc_1628", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1510(__int64 a1, int a2, __int64 a3)\n{\n _QWORD *v5; // rbx\n __int64 i; // r13\n const char *v7; // r15\n int v8; // eax\n int v9; // r14d\n _BYTE *v10; // rax\n _BYTE *v11; // rdx\n __int64 v12; // rdi\n int v13; // r8d\n __int64 v14; // rax\n __int64 v15; // rcx\n __int64 v17; // rax\n __int64 v18; // rcx\n signed int v19; // eax\n int v20; // ecx\n int v21; // eax\n\n v5 = malloc(8LL * a2);\n if ( a2 > 0 )\n {\n for ( i = 0LL; a2 != i; ++i )\n {\n v7 = *(const char **)(a1 + 8 * i);\n v8 = strlen(v7);\n *(_DWORD *)(a3 + 4 * i) = v8;\n v9 = v8;\n v10 = malloc(v8 + 1);\n v5[i] = v10;\n v11 = v10;\n if ( v9 > 0 )\n {\n v12 = (unsigned int)(v9 - 1);\n v13 = v9;\n if ( (unsigned int)v12 > 6 && (unsigned __int64)(v10 - (v7 + 1)) > 0xE )\n {\n if ( (unsigned int)v12 <= 0xE )\n {\n v18 = 0LL;\n v19 = 0;\n }\n else\n {\n v17 = 0LL;\n do\n {\n *(__m128i *)&v11[v17] = _mm_loadu_si128((const __m128i *)&v7[v17]);\n v17 += 16LL;\n }\n while ( v17 != 16LL * ((unsigned int)v9 >> 4) );\n v18 = v9 & 0xFFFFFFF0;\n v19 = v9 & 0xFFFFFFF0;\n if ( (v9 & 0xF) == 0 )\n goto LABEL_8;\n v13 = v9 - v18;\n if ( (unsigned int)(v9 - v18 - 1) <= 6 )\n goto LABEL_16;\n }\n *(_QWORD *)&v11[v18] = *(_QWORD *)&v7[v18];\n v19 += v13 & 0xFFFFFFF8;\n if ( (v13 & 7) != 0 )\n {\nLABEL_16:\n v11[v19] = v7[v19];\n if ( v9 > v19 + 1 )\n {\n v11[v19 + 1] = v7[v19 + 1];\n if ( v9 > v19 + 2 )\n {\n v11[v19 + 2] = v7[v19 + 2];\n if ( v9 > v19 + 3 )\n {\n v11[v19 + 3] = v7[v19 + 3];\n if ( v9 > v19 + 4 )\n {\n v11[v19 + 4] = v7[v19 + 4];\n v20 = v19 + 5;\n if ( v9 > v19 + 5 )\n {\n v21 = v19 + 6;\n v11[v20] = v7[v20];\n if ( v9 > v21 )\n v11[v21] = v7[v21];\n }\n }\n }\n }\n }\n }\n }\n else\n {\n v14 = 0LL;\n do\n {\n v11[v14] = v7[v14];\n v15 = v14++;\n }\n while ( v15 != v12 );\n }\n }\nLABEL_8:\n v11[v9] = 0;\n }\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1510(long long a1, int a2, long long a3) {\n uint64_t *v5;\n long long i;\n const char *v7;\n int v8;\n int v9;\n uint8_t *v10;\n uint8_t *v11;\n long long v12;\n int v13;\n long long v14;\n long long v15;\n long long v17;\n long long v18;\n signed int v19;\n int v20;\n int v21;\n v5 = malloc(8LL * a2);\n if (a2 > 0) {\n for (i = 0LL; a2 != i; ++i) {\n v7 = *(const char **)(a1 + 8 * i);\n v8 = strlen(v7);\n *(uint32_t *)(a3 + 4 * i) = v8;\n v9 = v8;\n v10 = malloc(v8 + 1);\n v5[i] = v10;\n v11 = v10;\n if (v9 > 0) {\n v12 = (unsigned int)(v9 - 1);\n v13 = v9;\n if ((unsigned int)v12 > 6 &&\n (unsigned long long)(v10 - (v7 + 1)) > 14) {\n if ((unsigned int)v12 <= 14) {\n v18 = 0LL;\n v19 = 0;\n } else {\n v17 = 0LL;\n do {\n *(__m128i *)&v11[v17] =\n _mm_loadu_si128((const __m128i *)&v7[v17]);\n v17 += 16LL;\n } while (v17 != 16LL * ((unsigned int)v9 >> 4));\n v18 = v9 & 4294967280;\n v19 = v9 & 4294967280;\n if ((v9 & 15) == 0) goto LABEL_8;\n v13 = v9 - v18;\n if ((unsigned int)(v9 - v18 - 1) <= 6) goto LABEL_16;\n }\n *(uint64_t *)&v11[v18] = *(uint64_t *)&v7[v18];\n v19 += v13 & 4294967288;\n if ((v13 & 7) != 0) {\n LABEL_16:\n v11[v19] = v7[v19];\n if (v9 > v19 + 1) {\n v11[v19 + 1] = v7[v19 + 1];\n if (v9 > v19 + 2) {\n v11[v19 + 2] = v7[v19 + 2];\n if (v9 > v19 + 3) {\n v11[v19 + 3] = v7[v19 + 3];\n if (v9 > v19 + 4) {\n v11[v19 + 4] = v7[v19 + 4];\n v20 = v19 + 5;\n if (v9 > v19 + 5) {\n v21 = v19 + 6;\n v11[v20] = v7[v20];\n if (v9 > v21) v11[v21] = v7[v21];\n }\n }\n }\n }\n }\n }\n } else {\n v14 = 0LL;\n do {\n v11[v14] = v7[v14];\n v15 = v14++;\n } while (v15 != v12);\n }\n }\n LABEL_8:\n v11[v9] = 0;\n }\n }\n return v5;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, int a2, long long a3) {\n uint64_t *v5;\n long long i;\n const char *v7;\n int v8;\n int v9;\n uint8_t *v10;\n uint8_t *v11;\n long long v12;\n int v13;\n long long v14;\n long long v15;\n long long v17;\n long long v18;\n signed int v19;\n int v20;\n int v21;\n v5 = malloc(8LL * a2);\n if (a2 > 0) {\n for (i = 0LL; a2 != i; ++i) {\n v7 = *(const char **)(a1 + 8 * i);\n v8 = strlen(v7);\n *(uint32_t *)(a3 + 4 * i) = v8;\n v9 = v8;\n v10 = malloc(v8 + 1);\n v5[i] = v10;\n v11 = v10;\n if (v9 > 0) {\n v12 = (unsigned int)(v9 - 1);\n v13 = v9;\n if ((unsigned int)v12 > 6 &&\n (unsigned long long)(v10 - (v7 + 1)) > 14) {\n if ((unsigned int)v12 <= 14) {\n v18 = 0LL;\n v19 = 0;\n } else {\n v17 = 0LL;\n do {\n *(__m128i *)&v11[v17] =\n _mm_loadu_si128((const __m128i *)&v7[v17]);\n v17 += 16LL;\n } while (v17 != 16LL * ((unsigned int)v9 >> 4));\n v18 = v9 & 4294967280;\n v19 = v9 & 4294967280;\n if ((v9 & 15) == 0) goto LABEL_8;\n v13 = v9 - v18;\n if ((unsigned int)(v9 - v18 - 1) <= 6) goto LABEL_16;\n }\n *(uint64_t *)&v11[v18] = *(uint64_t *)&v7[v18];\n v19 += v13 & 4294967288;\n if ((v13 & 7) != 0) {\n LABEL_16:\n v11[v19] = v7[v19];\n if (v9 > v19 + 1) {\n v11[v19 + 1] = v7[v19 + 1];\n if (v9 > v19 + 2) {\n v11[v19 + 2] = v7[v19 + 2];\n if (v9 > v19 + 3) {\n v11[v19 + 3] = v7[v19 + 3];\n if (v9 > v19 + 4) {\n v11[v19 + 4] = v7[v19 + 4];\n v20 = v19 + 5;\n if (v9 > v19 + 5) {\n v21 = v19 + 6;\n v11[v20] = v7[v20];\n if (v9 > v21) v11[v21] = v7[v21];\n }\n }\n }\n }\n }\n }\n } else {\n v14 = 0LL;\n do {\n v11[v14] = v7[v14];\n v15 = v14++;\n } while (v15 != v12);\n }\n }\n LABEL_8:\n v11[v9] = 0;\n }\n }\n return v5;\n}" + }, + { + "index": 858, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int input_list[], int size) { return size * size; }", + "test": "int main() {\n\n int test1[] = {0, 1, 3, 5, 7, 9, 11, 13, 15, 17};\n\n int test2[] = {1, 3, 5, 7, 9, 11, 13, 15, 17};\n\n int test3[] = {2, 4, 6, 8, 4, 5, 8, 10, 12, 14};\n\n\n\n assert(func0(test1, 5) == 25);\n\n assert(func0(test2, 4) == 16);\n\n assert(func0(test3, 3) == 9);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x8(%rbp)\nmov %esi,-0xc(%rbp)\nmov -0xc(%rbp),%eax\nimul %eax,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_8], rdi\nmov [rbp+var_C], esi\nmov eax, [rbp+var_C]\nimul eax, eax\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n return (unsigned int)(a2 * a2);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_8], rdi\nmov [rbp+var_C], esi\nmov eax, [rbp+var_C]\nimul eax, eax\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n return (unsigned int)(a2 * a2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) { return (unsigned int)(a2 * a2); }", + "ida_pseudo_norm": "long long func0(long long a1, int a2) { return (unsigned int)(a2 * a2); }" + }, + { + "index": 859, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int my_list[], int list_size, int ***output, int *output_size,\n int **output_element_sizes) {\n int total_sublists = 1 << list_size;\n int **subs = malloc(total_sublists * sizeof(int *));\n int *sizes = malloc(total_sublists * sizeof(int));\n int count = 0;\n for (int mask = 0; mask < total_sublists; mask++) {\n sizes[count] = 0;\n for (int i = 0; i < list_size; i++) {\n if (mask & (1 << i)) {\n sizes[count]++;\n }\n }\n subs[count] = malloc(sizes[count] * sizeof(int));\n int pos = 0;\n for (int i = 0; i < list_size; i++) {\n if (mask & (1 << i)) {\n subs[count][pos] = my_list[i];\n pos++;\n }\n }\n count++;\n }\n *output = subs;\n *output_size = total_sublists;\n *output_element_sizes = sizes;\n}", + "test": "int main() {\n\n int list1[] = {10, 20, 30, 40};\n\n int list_size1 = 4;\n\n int **output1;\n\n int output_size1;\n\n int *output_element_sizes1;\n\n func0(list1, list_size1, &output1, &output_size1, &output_element_sizes1);\n\n assert(output_size1 == 16); // replace specific list comparison for simplicity\n\n\n\n char *list2[] = {'X', 'Y', 'Z'};\n\n int list_size2 = 3;\n\n int **output2;\n\n int output_size2;\n\n int *output_element_sizes2;\n\n func0((int*)list2, list_size2, &output2, &output_size2, &output_element_sizes2);\n\n assert(output_size2 == 8);\n\n\n\n int list3[] = {1, 2, 3};\n\n int list_size3 = 3;\n\n int **output3;\n\n int output_size3;\n\n int *output_element_sizes3;\n\n func0(list3, list_size3, &output3, &output_size3, &output_element_sizes3);\n\n assert(output_size3 == 8);\n\n\n\n // Free memory\n\n for (int i = 0; i < output_size1; i++) {\n\n free(output1[i]);\n\n }\n\n free(output1);\n\n free(output_element_sizes1);\n\n\n\n for (int i = 0; i < output_size2; i++) {\n\n free(output2[i]);\n\n }\n\n free(output2);\n\n free(output_element_sizes2);\n\n\n\n for (int i = 0; i < output_size3; i++) {\n\n free(output3[i]);\n\n }\n\n free(output3);\n\n free(output_element_sizes3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x68,%rsp\nmov %rdi,-0x48(%rbp)\nmov %esi,-0x4c(%rbp)\nmov %rdx,-0x58(%rbp)\nmov %rcx,-0x60(%rbp)\nmov %r8,-0x68(%rbp)\nmov -0x4c(%rbp),%eax\nmov $0x1,%edx\nmov %eax,%ecx\nshl %cl,%edx\nmov %edx,%eax\nmov %eax,-0x24(%rbp)\nmov -0x24(%rbp),%eax\ncltq\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x20(%rbp)\nmov -0x24(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x18(%rbp)\nmovl $0x0,-0x38(%rbp)\nmovl $0x0,-0x34(%rbp)\njmpq 1329 \nmov -0x38(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovl $0x0,(%rax)\nmovl $0x0,-0x30(%rbp)\njmp 126c \nmov -0x30(%rbp),%eax\nmov -0x34(%rbp),%edx\nmov %eax,%ecx\nsar %cl,%edx\nmov %edx,%eax\nand $0x1,%eax\ntest %eax,%eax\nje 1268 \nmov -0x38(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nadd $0x1,%edx\nmov %edx,(%rax)\naddl $0x1,-0x30(%rbp)\nmov -0x30(%rbp),%eax\ncmp -0x4c(%rbp),%eax\njl 123a \nmov -0x38(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncltq\nshl $0x2,%rax\nmov -0x38(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x20(%rbp),%rdx\nlea (%rcx,%rdx,1),%rbx\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,(%rbx)\nmovl $0x0,-0x2c(%rbp)\nmovl $0x0,-0x28(%rbp)\njmp 1319 \nmov -0x28(%rbp),%eax\nmov -0x34(%rbp),%edx\nmov %eax,%ecx\nsar %cl,%edx\nmov %edx,%eax\nand $0x1,%eax\ntest %eax,%eax\nje 1315 \nmov -0x28(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov -0x38(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x20(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rdx),%rdx\nmov -0x2c(%rbp),%ecx\nmovslq %ecx,%rcx\nshl $0x2,%rcx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x2c(%rbp)\naddl $0x1,-0x28(%rbp)\nmov -0x28(%rbp),%eax\ncmp -0x4c(%rbp),%eax\njl 12c1 \naddl $0x1,-0x38(%rbp)\naddl $0x1,-0x34(%rbp)\nmov -0x34(%rbp),%eax\ncmp -0x24(%rbp),%eax\njl 1217 \nmov -0x58(%rbp),%rax\nmov -0x20(%rbp),%rdx\nmov %rdx,(%rax)\nmov -0x60(%rbp),%rax\nmov -0x24(%rbp),%edx\nmov %edx,(%rax)\nmov -0x68(%rbp),%rax\nmov -0x18(%rbp),%rdx\nmov %rdx,(%rax)\nadd $0x68,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 68h\nmov [rbp+var_48], rdi\nmov [rbp+var_4C], esi\nmov [rbp+var_58], rdx\nmov [rbp+var_60], rcx\nmov [rbp+var_68], r8\nmov eax, [rbp+var_4C]\nmov edx, 1\nmov ecx, eax\nshl edx, cl\nmov eax, edx\nmov [rbp+var_24], eax\nmov eax, [rbp+var_24]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_20], rax\nmov eax, [rbp+var_24]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_38], 0\nmov [rbp+var_34], 0\njmp loc_1329\nloc_1217:\nmov eax, [rbp+var_38]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov dword ptr [rax], 0\nmov [rbp+var_30], 0\njmp short loc_126C\nloc_123A:\nmov eax, [rbp+var_30]\nmov edx, [rbp+var_34]\nmov ecx, eax\nsar edx, cl\nmov eax, edx\nand eax, 1\ntest eax, eax\njz short loc_1268\nmov eax, [rbp+var_38]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nadd edx, 1\nmov [rax], edx\nloc_1268:\nadd [rbp+var_30], 1\nloc_126C:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_4C]\njl short loc_123A\nmov eax, [rbp+var_38]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nshl rax, 2\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_20]\nlea rbx, [rcx+rdx]\nmov rdi, rax; size\ncall _malloc\nmov [rbx], rax\nmov [rbp+var_2C], 0\nmov [rbp+var_28], 0\njmp short loc_1319\nloc_12C1:\nmov eax, [rbp+var_28]\nmov edx, [rbp+var_34]\nmov ecx, eax\nsar edx, cl\nmov eax, edx\nand eax, 1\ntest eax, eax\njz short loc_1315\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_20]\nadd rdx, rcx\nmov rdx, [rdx]\nmov ecx, [rbp+var_2C]\nmovsxd rcx, ecx\nshl rcx, 2\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_2C], 1\nloc_1315:\nadd [rbp+var_28], 1\nloc_1319:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_4C]\njl short loc_12C1\nadd [rbp+var_38], 1\nadd [rbp+var_34], 1\nloc_1329:\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_24]\njl loc_1217\nmov rax, [rbp+var_58]\nmov rdx, [rbp+var_20]\nmov [rax], rdx\nmov rax, [rbp+var_60]\nmov edx, [rbp+var_24]\nmov [rax], edx\nmov rax, [rbp+var_68]\nmov rdx, [rbp+var_18]\nmov [rax], rdx\nnop\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, int a2, _QWORD *a3, int *a4, _QWORD *a5)\n{\n _QWORD *result; // rax\n int v9; // [rsp+38h] [rbp-38h]\n int i; // [rsp+3Ch] [rbp-34h]\n int j; // [rsp+40h] [rbp-30h]\n int v12; // [rsp+44h] [rbp-2Ch]\n int k; // [rsp+48h] [rbp-28h]\n int v14; // [rsp+4Ch] [rbp-24h]\n _QWORD *v15; // [rsp+50h] [rbp-20h]\n int *v16; // [rsp+58h] [rbp-18h]\n\n v14 = 1 << a2;\n v15 = malloc(8LL * (1 << a2));\n v16 = (int *)malloc(4LL * (1 << a2));\n v9 = 0;\n for ( i = 0; i < v14; ++i )\n {\n v16[v9] = 0;\n for ( j = 0; j < a2; ++j )\n {\n if ( ((i >> j) & 1) != 0 )\n ++v16[v9];\n }\n v15[v9] = malloc(4LL * v16[v9]);\n v12 = 0;\n for ( k = 0; k < a2; ++k )\n {\n if ( ((i >> k) & 1) != 0 )\n *(_DWORD *)(4LL * v12++ + v15[v9]) = *(_DWORD *)(4LL * k + a1);\n }\n ++v9;\n }\n *a3 = v15;\n *a4 = v14;\n result = a5;\n *a5 = v16;\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 68h\nmov [rbp+var_48], rdi\nmov [rbp+var_4C], esi\nmov [rbp+var_58], rdx\nmov [rbp+var_60], rcx\nmov [rbp+var_68], r8\nmov eax, [rbp+var_4C]\nmov edx, 1\nmov ecx, eax\nshl edx, cl\nmov eax, edx\nmov [rbp+var_24], eax\nmov eax, [rbp+var_24]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_20], rax\nmov eax, [rbp+var_24]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_38], 0\nmov [rbp+var_34], 0\njmp loc_1329\nloc_1217:\nmov eax, [rbp+var_38]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov dword ptr [rax], 0\nmov [rbp+var_30], 0\njmp short loc_126C\nloc_123A:\nmov eax, [rbp+var_30]\nmov edx, [rbp+var_34]\nmov ecx, eax\nsar edx, cl\nmov eax, edx\nand eax, 1\ntest eax, eax\njz short loc_1268\nmov eax, [rbp+var_38]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nadd edx, 1\nmov [rax], edx\nloc_1268:\nadd [rbp+var_30], 1\nloc_126C:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_4C]\njl short loc_123A\nmov eax, [rbp+var_38]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nshl rax, 2\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_20]\nlea rbx, [rcx+rdx]\nmov rdi, rax; size\ncall _malloc\nmov [rbx], rax\nmov [rbp+var_2C], 0\nmov [rbp+var_28], 0\njmp short loc_1319\nloc_12C1:\nmov eax, [rbp+var_28]\nmov edx, [rbp+var_34]\nmov ecx, eax\nsar edx, cl\nmov eax, edx\nand eax, 1\ntest eax, eax\njz short loc_1315\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_20]\nadd rdx, rcx\nmov rdx, [rdx]\nmov ecx, [rbp+var_2C]\nmovsxd rcx, ecx\nshl rcx, 2\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_2C], 1\nloc_1315:\nadd [rbp+var_28], 1\nloc_1319:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_4C]\njl short loc_12C1\nadd [rbp+var_38], 1\nadd [rbp+var_34], 1\nloc_1329:\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_24]\njl loc_1217\nmov rax, [rbp+var_58]\nmov rdx, [rbp+var_20]\nmov [rax], rdx\nmov rax, [rbp+var_60]\nmov edx, [rbp+var_24]\nmov [rax], edx\nmov rax, [rbp+var_68]\nmov rdx, [rbp+var_18]\nmov [rax], rdx\nnop\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11A9(__int64 a1, int a2, _QWORD *a3, int *a4, _QWORD *a5)\n{\n _QWORD *result; // rax\n int v9; // [rsp+38h] [rbp-38h]\n int i; // [rsp+3Ch] [rbp-34h]\n int j; // [rsp+40h] [rbp-30h]\n int v12; // [rsp+44h] [rbp-2Ch]\n int k; // [rsp+48h] [rbp-28h]\n int v14; // [rsp+4Ch] [rbp-24h]\n _QWORD *v15; // [rsp+50h] [rbp-20h]\n int *v16; // [rsp+58h] [rbp-18h]\n\n v14 = 1 << a2;\n v15 = malloc(8LL * (1 << a2));\n v16 = (int *)malloc(4LL * (1 << a2));\n v9 = 0;\n for ( i = 0; i < v14; ++i )\n {\n v16[v9] = 0;\n for ( j = 0; j < a2; ++j )\n {\n if ( ((i >> j) & 1) != 0 )\n ++v16[v9];\n }\n v15[v9] = malloc(4LL * v16[v9]);\n v12 = 0;\n for ( k = 0; k < a2; ++k )\n {\n if ( ((i >> k) & 1) != 0 )\n *(_DWORD *)(4LL * v12++ + v15[v9]) = *(_DWORD *)(4LL * k + a1);\n }\n ++v9;\n }\n *a3 = v15;\n *a4 = v14;\n result = a5;\n *a5 = v16;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11A9(long long a1, int a2, uint64_t *a3, int *a4, uint64_t *a5) {\n uint64_t *result;\n int v9;\n int i;\n int j;\n int v12;\n int k;\n int v14;\n uint64_t *v15;\n int *v16;\n v14 = 1 << a2;\n v15 = malloc(8LL * (1 << a2));\n v16 = (int *)malloc(4LL * (1 << a2));\n v9 = 0;\n for (i = 0; i < v14; ++i) {\n v16[v9] = 0;\n for (j = 0; j < a2; ++j) {\n if (((i >> j) & 1) != 0) ++v16[v9];\n }\n v15[v9] = malloc(4LL * v16[v9]);\n v12 = 0;\n for (k = 0; k < a2; ++k) {\n if (((i >> k) & 1) != 0)\n *(uint32_t *)(4LL * v12++ + v15[v9]) = *(uint32_t *)(4LL * k + a1);\n }\n ++v9;\n }\n *a3 = v15;\n *a4 = v14;\n result = a5;\n *a5 = v16;\n return result;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, int a2, uint64_t *a3, int *a4, uint64_t *a5) {\n uint64_t *result;\n int v9;\n int i;\n int j;\n int v12;\n int k;\n int v14;\n uint64_t *v15;\n int *v16;\n v14 = 1 << a2;\n v15 = malloc(8LL * (1 << a2));\n v16 = (int *)malloc(4LL * (1 << a2));\n v9 = 0;\n for (i = 0; i < v14; ++i) {\n v16[v9] = 0;\n for (j = 0; j < a2; ++j) {\n if (((i >> j) & 1) != 0) ++v16[v9];\n }\n v15[v9] = malloc(4LL * v16[v9]);\n v12 = 0;\n for (k = 0; k < a2; ++k) {\n if (((i >> k) & 1) != 0)\n *(uint32_t *)(4LL * v12++ + v15[v9]) = *(uint32_t *)(4LL * k + a1);\n }\n ++v9;\n }\n *a3 = v15;\n *a4 = v14;\n result = a5;\n *a5 = v16;\n return result;\n}" + }, + { + "index": 859, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int my_list[], int list_size, int ***output, int *output_size,\n int **output_element_sizes) {\n int total_sublists = 1 << list_size;\n int **subs = malloc(total_sublists * sizeof(int *));\n int *sizes = malloc(total_sublists * sizeof(int));\n int count = 0;\n for (int mask = 0; mask < total_sublists; mask++) {\n sizes[count] = 0;\n for (int i = 0; i < list_size; i++) {\n if (mask & (1 << i)) {\n sizes[count]++;\n }\n }\n subs[count] = malloc(sizes[count] * sizeof(int));\n int pos = 0;\n for (int i = 0; i < list_size; i++) {\n if (mask & (1 << i)) {\n subs[count][pos] = my_list[i];\n pos++;\n }\n }\n count++;\n }\n *output = subs;\n *output_size = total_sublists;\n *output_element_sizes = sizes;\n}", + "test": "int main() {\n\n int list1[] = {10, 20, 30, 40};\n\n int list_size1 = 4;\n\n int **output1;\n\n int output_size1;\n\n int *output_element_sizes1;\n\n func0(list1, list_size1, &output1, &output_size1, &output_element_sizes1);\n\n assert(output_size1 == 16); // replace specific list comparison for simplicity\n\n\n\n char *list2[] = {'X', 'Y', 'Z'};\n\n int list_size2 = 3;\n\n int **output2;\n\n int output_size2;\n\n int *output_element_sizes2;\n\n func0((int*)list2, list_size2, &output2, &output_size2, &output_element_sizes2);\n\n assert(output_size2 == 8);\n\n\n\n int list3[] = {1, 2, 3};\n\n int list_size3 = 3;\n\n int **output3;\n\n int output_size3;\n\n int *output_element_sizes3;\n\n func0(list3, list_size3, &output3, &output_size3, &output_element_sizes3);\n\n assert(output_size3 == 8);\n\n\n\n // Free memory\n\n for (int i = 0; i < output_size1; i++) {\n\n free(output1[i]);\n\n }\n\n free(output1);\n\n free(output_element_sizes1);\n\n\n\n for (int i = 0; i < output_size2; i++) {\n\n free(output2[i]);\n\n }\n\n free(output2);\n\n free(output_element_sizes2);\n\n\n\n for (int i = 0; i < output_size3; i++) {\n\n free(output3[i]);\n\n }\n\n free(output3);\n\n free(output_element_sizes3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x38,%rsp\nmov %rdi,%r13\nmov %esi,%r12d\nmov %rdx,0x18(%rsp)\nmov %rcx,0x20(%rsp)\nmov %r8,0x28(%rsp)\nmov $0x1,%eax\nmov %esi,%ecx\nshl %cl,%eax\nmov %eax,%ebp\nmov %eax,0x4(%rsp)\nmovslq %eax,%rbx\nlea 0x0(,%rbx,8),%rdi\ncallq 10b0 \nmov %rax,%r15\nmov %rax,0x8(%rsp)\nlea 0x0(,%rbx,4),%rdi\ncallq 10b0 \nmov %rax,0x10(%rsp)\ntest %ebp,%ebp\njle 1252 \nmov %rax,%r14\nmov $0x0,%ebp\njmpq 12c4 \nlea 0x1(%rbx),%eax\ncmp %eax,%r12d\nje 1286 \nmov %eax,%ebx\nbt %ebx,%ebp\njae 121a \naddl $0x1,(%rdx)\njmp 121a \nlea 0x1(%rax),%rdx\ncmp %rbx,%rax\nje 12b3 \nmov %rdx,%rax\nbt %eax,%ebp\njae 122e \nmov 0x0(%r13,%rax,4),%edi\nmovslq %ecx,%rsi\nmov (%r8),%rdx\nmov %edi,(%rdx,%rsi,4)\nadd $0x1,%ecx\njmp 122e \nmov 0x18(%rsp),%rax\nmov 0x8(%rsp),%rsi\nmov %rsi,(%rax)\nmov 0x20(%rsp),%rax\nmov 0x4(%rsp),%esi\nmov %esi,(%rax)\nmov 0x28(%rsp),%rax\nmov 0x10(%rsp),%rsi\nmov %rsi,(%rax)\nadd $0x38,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmovslq (%rdx),%rdi\nshl $0x2,%rdi\ncallq 10b0 \nmov %r15,%r8\nmov %rax,(%r15)\nmov %ebx,%ebx\nmov $0x0,%eax\nmov $0x0,%ecx\njmp 123a \nmov $0x0,%edi\ncallq 10b0 \nmov %rax,(%r15)\nadd $0x1,%ebp\nadd $0x4,%r14\nadd $0x8,%r15\ncmp %ebp,0x4(%rsp)\nje 1252 \nmov %r14,%rdx\nmovl $0x0,(%r14)\ntest %r12d,%r12d\njle 12a6 \nmov $0x0,%ebx\njmpq 1224 \n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 38h\nmov r13, rdi\nmov r12d, esi\nmov [rsp+68h+var_58], rdx\nmov [rsp+68h+var_50], rcx\nmov [rsp+68h+var_48], r8\nmov eax, 1\nmov ecx, esi\nshl eax, cl\nmov r14d, eax\nmov [rsp+68h+var_64], eax\nmovsxd rbx, eax\nlea rdi, ds:0[rbx*8]; size\ncall _malloc\nmov r15, rax\nmov [rsp+68h+var_60], rax\nlea rdi, ds:0[rbx*4]; size\ncall _malloc\nmov rbx, rax\ntest r14d, r14d\njle short loc_1278\nmov r14, rax\nmov ebp, 0\nmov [rsp+68h+var_40], rax\njmp loc_12C5\nloc_121F:\nadd ebx, 1\ncmp r12d, ebx\njz short loc_1231\nloc_1227:\nbt ebp, ebx\njnb short loc_121F\nadd dword ptr [rax], 1\njmp short loc_121F\nloc_1231:\nmovsxd rdi, dword ptr [rax]\nshl rdi, 2; size\ncall _malloc\nmov r8, r15\nmov [r15], rax\nmovsxd rbx, ebx\nmov eax, 0\nmov edx, 0\njmp short loc_125B\nloc_1252:\nadd rax, 1\ncmp rbx, rax\njz short loc_12B4\nloc_125B:\nbt ebp, eax\njnb short loc_1252\nmov edi, [r13+rax*4+0]\nmovsxd rsi, edx\nmov rcx, [r8]\nmov [rcx+rsi*4], edi\nadd edx, 1\njmp short loc_1252\nloc_1273:\nmov rbx, [rsp+68h+var_40]\nloc_1278:\nmov rax, [rsp+68h+var_58]\nmov rsi, [rsp+68h+var_60]\nmov [rax], rsi\nmov rax, [rsp+68h+var_50]\nmov ecx, [rsp+68h+var_64]\nmov [rax], ecx\nmov rax, [rsp+68h+var_48]\nmov [rax], rbx\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_12A7:\nmov edi, 0; size\ncall _malloc\nmov [r15], rax\nloc_12B4:\nadd ebp, 1\nadd r14, 4\nadd r15, 8\ncmp [rsp+68h+var_64], ebp\njz short loc_1273\nloc_12C5:\nmov rax, r14\nmov dword ptr [r14], 0\ntest r12d, r12d\njle short loc_12A7\nmov ebx, 0\njmp loc_1227", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, int a2, _QWORD *a3, int *a4, _QWORD *a5)\n{\n __int64 v5; // rbx\n _QWORD *v6; // r15\n int *v7; // rax\n int *v8; // rbx\n int *v9; // r14\n int v10; // ebp\n unsigned int i; // ebx\n __int64 v12; // rax\n int v13; // edx\n _QWORD *result; // rax\n int v15; // [rsp+4h] [rbp-64h]\n _QWORD *v16; // [rsp+8h] [rbp-60h]\n int *v20; // [rsp+28h] [rbp-40h]\n\n v15 = 1 << a2;\n v5 = 1 << a2;\n v6 = malloc(8 * v5);\n v16 = v6;\n v7 = (int *)malloc(4 * v5);\n v8 = v7;\n if ( 1 << a2 > 0 )\n {\n v9 = v7;\n v10 = 0;\n v20 = v7;\n do\n {\n *v9 = 0;\n if ( a2 <= 0 )\n {\n *v6 = malloc(0LL);\n }\n else\n {\n for ( i = 0; i != a2; ++i )\n {\n if ( _bittest(&v10, i) )\n ++*v9;\n }\n *v6 = malloc(4LL * *v9);\n v12 = 0LL;\n v13 = 0;\n do\n {\n if ( _bittest(&v10, v12) )\n *(_DWORD *)(*v6 + 4LL * v13++) = *(_DWORD *)(a1 + 4 * v12);\n ++v12;\n }\n while ( i != v12 );\n }\n ++v10;\n ++v9;\n ++v6;\n }\n while ( v15 != v10 );\n v8 = v20;\n }\n *a3 = v16;\n *a4 = v15;\n result = a5;\n *a5 = v8;\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 38h\nmov r13, rdi\nmov r12d, esi\nmov [rsp+68h+var_58], rdx\nmov [rsp+68h+var_50], rcx\nmov [rsp+68h+var_48], r8\nmov eax, 1\nmov ecx, esi\nshl eax, cl\nmov r14d, eax\nmov [rsp+68h+var_64], eax\nmovsxd rbx, eax\nlea rdi, ds:0[rbx*8]; size\ncall _malloc\nmov r15, rax\nmov [rsp+68h+var_60], rax\nlea rdi, ds:0[rbx*4]; size\ncall _malloc\nmov rbx, rax\ntest r14d, r14d\njle short loc_1278\nmov r14, rax\nmov ebp, 0\nmov [rsp+68h+var_40], rax\njmp loc_12C5\nloc_121F:\nadd ebx, 1\ncmp r12d, ebx\njz short loc_1231\nloc_1227:\nbt ebp, ebx\njnb short loc_121F\nadd dword ptr [rax], 1\njmp short loc_121F\nloc_1231:\nmovsxd rdi, dword ptr [rax]\nshl rdi, 2; size\ncall _malloc\nmov r8, r15\nmov [r15], rax\nmovsxd rbx, ebx\nmov eax, 0\nmov edx, 0\njmp short loc_125B\nloc_1252:\nadd rax, 1\ncmp rbx, rax\njz short loc_12B4\nloc_125B:\nbt ebp, eax\njnb short loc_1252\nmov edi, [r13+rax*4+0]\nmovsxd rsi, edx\nmov rcx, [r8]\nmov [rcx+rsi*4], edi\nadd edx, 1\njmp short loc_1252\nloc_1273:\nmov rbx, [rsp+68h+var_40]\nloc_1278:\nmov rax, [rsp+68h+var_58]\nmov rsi, [rsp+68h+var_60]\nmov [rax], rsi\nmov rax, [rsp+68h+var_50]\nmov ecx, [rsp+68h+var_64]\nmov [rax], ecx\nmov rax, [rsp+68h+var_48]\nmov [rax], rbx\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_12A7:\nmov edi, 0; size\ncall _malloc\nmov [r15], rax\nloc_12B4:\nadd ebp, 1\nadd r14, 4\nadd r15, 8\ncmp [rsp+68h+var_64], ebp\njz short loc_1273\nloc_12C5:\nmov rax, r14\nmov dword ptr [r14], 0\ntest r12d, r12d\njle short loc_12A7\nmov ebx, 0\njmp loc_1227", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11A9(__int64 a1, int a2, _QWORD *a3, int *a4, _QWORD *a5)\n{\n __int64 v5; // rbx\n _QWORD *v6; // r15\n int *v7; // rax\n int *v8; // rbx\n int *v9; // r14\n int v10; // ebp\n unsigned int i; // ebx\n __int64 v12; // rax\n int v13; // edx\n _QWORD *result; // rax\n int v15; // [rsp+4h] [rbp-64h]\n _QWORD *v16; // [rsp+8h] [rbp-60h]\n int *v20; // [rsp+28h] [rbp-40h]\n\n v15 = 1 << a2;\n v5 = 1 << a2;\n v6 = malloc(8 * v5);\n v16 = v6;\n v7 = (int *)malloc(4 * v5);\n v8 = v7;\n if ( 1 << a2 > 0 )\n {\n v9 = v7;\n v10 = 0;\n v20 = v7;\n do\n {\n *v9 = 0;\n if ( a2 <= 0 )\n {\n *v6 = malloc(0LL);\n }\n else\n {\n for ( i = 0; i != a2; ++i )\n {\n if ( _bittest(&v10, i) )\n ++*v9;\n }\n *v6 = malloc(4LL * *v9);\n v12 = 0LL;\n v13 = 0;\n do\n {\n if ( _bittest(&v10, v12) )\n *(_DWORD *)(*v6 + 4LL * v13++) = *(_DWORD *)(a1 + 4 * v12);\n ++v12;\n }\n while ( i != v12 );\n }\n ++v10;\n ++v9;\n ++v6;\n }\n while ( v15 != v10 );\n v8 = v20;\n }\n *a3 = v16;\n *a4 = v15;\n result = a5;\n *a5 = v8;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11A9(long long a1, int a2, uint64_t *a3, int *a4, uint64_t *a5) {\n long long v5;\n uint64_t *v6;\n int *v7;\n int *v8;\n int *v9;\n int v10;\n unsigned int i;\n long long v12;\n int v13;\n uint64_t *result;\n int v15;\n uint64_t *v16;\n int *v20;\n v15 = 1 << a2;\n v5 = 1 << a2;\n v6 = malloc(8 * v5);\n v16 = v6;\n v7 = (int *)malloc(4 * v5);\n v8 = v7;\n if (1 << a2 > 0) {\n v9 = v7;\n v10 = 0;\n v20 = v7;\n do {\n *v9 = 0;\n if (a2 <= 0) {\n *v6 = malloc(0LL);\n } else {\n for (i = 0; i != a2; ++i) {\n if (_bittest(&v10, i)) ++*v9;\n }\n *v6 = malloc(4LL * *v9);\n v12 = 0LL;\n v13 = 0;\n do {\n if (_bittest(&v10, v12))\n *(uint32_t *)(*v6 + 4LL * v13++) = *(uint32_t *)(a1 + 4 * v12);\n ++v12;\n } while (i != v12);\n }\n ++v10;\n ++v9;\n ++v6;\n } while (v15 != v10);\n v8 = v20;\n }\n *a3 = v16;\n *a4 = v15;\n result = a5;\n *a5 = v8;\n return result;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, int a2, uint64_t *a3, int *a4, uint64_t *a5) {\n long long v5;\n uint64_t *v6;\n int *v7;\n int *v8;\n int *v9;\n int v10;\n unsigned int i;\n long long v12;\n int v13;\n uint64_t *result;\n int v15;\n uint64_t *v16;\n int *v20;\n v15 = 1 << a2;\n v5 = 1 << a2;\n v6 = malloc(8 * v5);\n v16 = v6;\n v7 = (int *)malloc(4 * v5);\n v8 = v7;\n if (1 << a2 > 0) {\n v9 = v7;\n v10 = 0;\n v20 = v7;\n do {\n *v9 = 0;\n if (a2 <= 0) {\n *v6 = malloc(0LL);\n } else {\n for (i = 0; i != a2; ++i) {\n if (_bittest(&v10, i)) ++*v9;\n }\n *v6 = malloc(4LL * *v9);\n v12 = 0LL;\n v13 = 0;\n do {\n if (_bittest(&v10, v12))\n *(uint32_t *)(*v6 + 4LL * v13++) = *(uint32_t *)(a1 + 4 * v12);\n ++v12;\n } while (i != v12);\n }\n ++v10;\n ++v9;\n ++v6;\n } while (v15 != v10);\n v8 = v20;\n }\n *a3 = v16;\n *a4 = v15;\n result = a5;\n *a5 = v8;\n return result;\n}" + }, + { + "index": 859, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int my_list[], int list_size, int ***output, int *output_size,\n int **output_element_sizes) {\n int total_sublists = 1 << list_size;\n int **subs = malloc(total_sublists * sizeof(int *));\n int *sizes = malloc(total_sublists * sizeof(int));\n int count = 0;\n for (int mask = 0; mask < total_sublists; mask++) {\n sizes[count] = 0;\n for (int i = 0; i < list_size; i++) {\n if (mask & (1 << i)) {\n sizes[count]++;\n }\n }\n subs[count] = malloc(sizes[count] * sizeof(int));\n int pos = 0;\n for (int i = 0; i < list_size; i++) {\n if (mask & (1 << i)) {\n subs[count][pos] = my_list[i];\n pos++;\n }\n }\n count++;\n }\n *output = subs;\n *output_size = total_sublists;\n *output_element_sizes = sizes;\n}", + "test": "int main() {\n\n int list1[] = {10, 20, 30, 40};\n\n int list_size1 = 4;\n\n int **output1;\n\n int output_size1;\n\n int *output_element_sizes1;\n\n func0(list1, list_size1, &output1, &output_size1, &output_element_sizes1);\n\n assert(output_size1 == 16); // replace specific list comparison for simplicity\n\n\n\n char *list2[] = {'X', 'Y', 'Z'};\n\n int list_size2 = 3;\n\n int **output2;\n\n int output_size2;\n\n int *output_element_sizes2;\n\n func0((int*)list2, list_size2, &output2, &output_size2, &output_element_sizes2);\n\n assert(output_size2 == 8);\n\n\n\n int list3[] = {1, 2, 3};\n\n int list_size3 = 3;\n\n int **output3;\n\n int output_size3;\n\n int *output_element_sizes3;\n\n func0(list3, list_size3, &output3, &output_size3, &output_element_sizes3);\n\n assert(output_size3 == 8);\n\n\n\n // Free memory\n\n for (int i = 0; i < output_size1; i++) {\n\n free(output1[i]);\n\n }\n\n free(output1);\n\n free(output_element_sizes1);\n\n\n\n for (int i = 0; i < output_size2; i++) {\n\n free(output2[i]);\n\n }\n\n free(output2);\n\n free(output_element_sizes2);\n\n\n\n for (int i = 0; i < output_size3; i++) {\n\n free(output3[i]);\n\n }\n\n free(output3);\n\n free(output_element_sizes3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmov $0x1,%eax\npush %r14\npush %r13\npush %r12\nmov %esi,%r12d\npush %rbp\npush %rbx\nmov %rdi,%rbx\nsub $0x38,%rsp\nmov %rcx,0x20(%rsp)\nmov %esi,%ecx\nshl %cl,%eax\nmov %rdx,0x18(%rsp)\nmovslq %eax,%rbp\nmov %r8,0x28(%rsp)\nlea 0x0(,%rbp,8),%rdi\nmov %ebp,0x14(%rsp)\ncallq 10b0 \nlea 0x0(,%rbp,4),%rdi\nmov %rax,(%rsp)\ncallq 10b0 \nmov %rax,%r13\nlea -0x1(%rbp),%eax\nmov %rax,0x8(%rsp)\ntest %ebp,%ebp\njle 14f3 \nxor %r14d,%r14d\nmov %r13,%r15\nmov %r12d,%r13d\nmovl $0x0,(%r15,%r14,4)\nmov %r14d,%r12d\ntest %r13d,%r13d\njle 14d5 \nnopl (%rax)\nxor %edi,%edi\nxor %ebp,%ebp\njmp 1462 \nxchg %ax,%ax\nmov %eax,%ebp\nbt %ebp,%r12d\njae 146f \nadd $0x1,%edi\nmov %edi,(%r15,%r14,4)\nlea 0x1(%rbp),%eax\ncmp %eax,%r13d\njne 1460 \nmovslq %edi,%rdi\nshl $0x2,%rdi\ncallq 10b0 \nmov (%rsp),%rsi\nxor %edx,%edx\nxor %r8d,%r8d\nmov %rax,(%rsi,%r14,8)\njmp 149b \nnopw 0x0(%rax,%rax,1)\nmov %rcx,%rdx\nbt %edx,%r12d\njae 14ae \nmov (%rbx,%rdx,4),%esi\nmovslq %r8d,%rcx\nadd $0x1,%r8d\nmov %esi,(%rax,%rcx,4)\nlea 0x1(%rdx),%rcx\ncmp %rdx,%rbp\njne 1498 \nlea 0x1(%r14),%rax\ncmp 0x8(%rsp),%r14\nje 14f0 \nmov %rax,%r14\nmovl $0x0,(%r15,%r14,4)\nmov %r14d,%r12d\ntest %r13d,%r13d\njg 1458 \nxor %edi,%edi\ncallq 10b0 \nmov (%rsp),%rsi\nmov %rax,(%rsi,%r14,8)\nlea 0x1(%r14),%rax\ncmp 0x8(%rsp),%r14\njne 14c2 \nmov %r15,%r13\nmov 0x18(%rsp),%rax\nmov (%rsp),%rbx\nmov %rbx,(%rax)\nmov 0x20(%rsp),%rax\nmov 0x14(%rsp),%ebx\nmov %ebx,(%rax)\nmov 0x28(%rsp),%rax\nmov %r13,(%rax)\nadd $0x38,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov eax, 1\npush r14\npush r13\npush r12\nmov r12d, esi\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 38h\nmov [rsp+68h+var_48], rcx\nmov ecx, esi\nshl eax, cl\nmov [rsp+68h+var_50], rdx\nmovsxd r15, eax\nmov [rsp+68h+var_40], r8\nlea rdi, ds:0[r15*8]; size\nmov [rsp+68h+var_54], r15d\nmov [rsp+68h+var_60], r15\ncall _malloc\nlea rdi, ds:0[r15*4]; size\nmov [rsp+68h+var_68], rax\ncall _malloc\nmov r13, rax\ntest r15d, r15d\njle loc_148A\nmov dword ptr [rax], 0\ntest r12d, r12d\njle loc_147C\nmovsxd r14, r12d\nxor ebp, ebp\nxor r15d, r15d\nmov rax, r14\nmov r14d, r12d\nmov r12, rbp\nmov rbp, rbx\nmov rbx, r13\nmov r13, rax\nloc_1410:\nxor edi, edi\nxor eax, eax\nnop dword ptr [rax+00h]\nloc_1418:\nbt r15d, eax\njnb short loc_1425\nadd edi, 1\nmov [rbx+r12*4], edi\nloc_1425:\nadd eax, 1\ncmp r14d, eax\njnz short loc_1418\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov rsi, [rsp+68h+var_68]\nxor edx, edx\nxor edi, edi\nmov [rsi+r12*8], rax\nnop dword ptr [rax]\nloc_1448:\nbt r15d, edx\njnb short loc_145B\nmov esi, [rbp+rdx*4+0]\nmovsxd rcx, edi\nadd edi, 1\nmov [rax+rcx*4], esi\nloc_145B:\nadd rdx, 1\ncmp rdx, r13\njnz short loc_1448\nadd r12, 1\ncmp [rsp+68h+var_60], r12\njz short loc_14C0\nmov dword ptr [rbx+r12*4], 0\nmov r15d, r12d\njmp short loc_1410\nloc_147C:\nxor edi, edi; size\ncall _malloc\nmov rcx, [rsp+68h+var_68]\nmov [rcx], rax\nloc_148A:\nmov rax, [rsp+68h+var_50]\nmov rcx, [rsp+68h+var_68]\nmov [rax], rcx\nmov rax, [rsp+68h+var_48]\nmov ecx, [rsp+68h+var_54]\nmov [rax], ecx\nmov rax, [rsp+68h+var_40]\nmov [rax], r13\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14C0:\nmov r13, rbx\njmp short loc_148A", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, int a2, _QWORD *a3, _DWORD *a4, _QWORD *a5)\n{\n __int64 v5; // r15\n _DWORD *v6; // rax\n _DWORD *v7; // r13\n int v8; // r15d\n __int64 v9; // r12\n _DWORD *v11; // rbx\n int v12; // edi\n unsigned int i; // eax\n _DWORD *v14; // rax\n __int64 v15; // rdx\n int v16; // edi\n __int64 v17; // rcx\n _QWORD *result; // rax\n _QWORD *v19; // [rsp+0h] [rbp-68h]\n\n v5 = 1 << a2;\n v19 = malloc(8 * v5);\n v6 = malloc(4 * v5);\n v7 = v6;\n if ( (int)v5 > 0 )\n {\n *v6 = 0;\n if ( a2 <= 0 )\n {\n *v19 = malloc(0LL);\n }\n else\n {\n v8 = 0;\n v9 = 0LL;\n v11 = v6;\n while ( 1 )\n {\n v12 = 0;\n for ( i = 0; i != a2; ++i )\n {\n if ( _bittest(&v8, i) )\n v11[v9] = ++v12;\n }\n v14 = malloc(4LL * v12);\n v15 = 0LL;\n v16 = 0;\n v19[v9] = v14;\n do\n {\n if ( _bittest(&v8, v15) )\n {\n v17 = v16++;\n v14[v17] = *(_DWORD *)(a1 + 4 * v15);\n }\n ++v15;\n }\n while ( v15 != a2 );\n if ( 1 << a2 == ++v9 )\n break;\n v11[v9] = 0;\n v8 = v9;\n }\n v7 = v11;\n }\n }\n *a3 = v19;\n *a4 = 1 << a2;\n result = a5;\n *a5 = v7;\n return result;\n}", + "ida_strip_asm": "sub_1380:\nendbr64\npush r15\nmov eax, 1\npush r14\npush r13\npush r12\nmov r12d, esi\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 38h\nmov [rsp+68h+var_48], rcx\nmov ecx, esi\nshl eax, cl\nmov [rsp+68h+var_50], rdx\nmovsxd r15, eax\nmov [rsp+68h+var_40], r8\nlea rdi, ds:0[r15*8]; size\nmov [rsp+68h+var_54], r15d\nmov [rsp+68h+var_60], r15\ncall _malloc\nlea rdi, ds:0[r15*4]; size\nmov [rsp+68h+var_68], rax\ncall _malloc\nmov r13, rax\ntest r15d, r15d\njle loc_148A\nmov dword ptr [rax], 0\ntest r12d, r12d\njle loc_147C\nmovsxd r14, r12d\nxor ebp, ebp\nxor r15d, r15d\nmov rax, r14\nmov r14d, r12d\nmov r12, rbp\nmov rbp, rbx\nmov rbx, r13\nmov r13, rax\nloc_1410:\nxor edi, edi\nxor eax, eax\nnop dword ptr [rax+00h]\nloc_1418:\nbt r15d, eax\njnb short loc_1425\nadd edi, 1\nmov [rbx+r12*4], edi\nloc_1425:\nadd eax, 1\ncmp r14d, eax\njnz short loc_1418\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov rsi, [rsp+68h+var_68]\nxor edx, edx\nxor edi, edi\nmov [rsi+r12*8], rax\nnop dword ptr [rax]\nloc_1448:\nbt r15d, edx\njnb short loc_145B\nmov esi, [rbp+rdx*4+0]\nmovsxd rcx, edi\nadd edi, 1\nmov [rax+rcx*4], esi\nloc_145B:\nadd rdx, 1\ncmp rdx, r13\njnz short loc_1448\nadd r12, 1\ncmp [rsp+68h+var_60], r12\njz short loc_14C0\nmov dword ptr [rbx+r12*4], 0\nmov r15d, r12d\njmp short loc_1410\nloc_147C:\nxor edi, edi; size\ncall _malloc\nmov rcx, [rsp+68h+var_68]\nmov [rcx], rax\nloc_148A:\nmov rax, [rsp+68h+var_50]\nmov rcx, [rsp+68h+var_68]\nmov [rax], rcx\nmov rax, [rsp+68h+var_48]\nmov ecx, [rsp+68h+var_54]\nmov [rax], ecx\nmov rax, [rsp+68h+var_40]\nmov [rax], r13\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14C0:\nmov r13, rbx\njmp short loc_148A", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1380(__int64 a1, int a2, _QWORD *a3, _DWORD *a4, _QWORD *a5)\n{\n __int64 v5; // r15\n _DWORD *v6; // rax\n _DWORD *v7; // r13\n int v8; // r15d\n __int64 v9; // r12\n _DWORD *v11; // rbx\n int v12; // edi\n unsigned int i; // eax\n _DWORD *v14; // rax\n __int64 v15; // rdx\n int v16; // edi\n __int64 v17; // rcx\n _QWORD *result; // rax\n _QWORD *v19; // [rsp+0h] [rbp-68h]\n\n v5 = 1 << a2;\n v19 = malloc(8 * v5);\n v6 = malloc(4 * v5);\n v7 = v6;\n if ( (int)v5 > 0 )\n {\n *v6 = 0;\n if ( a2 <= 0 )\n {\n *v19 = malloc(0LL);\n }\n else\n {\n v8 = 0;\n v9 = 0LL;\n v11 = v6;\n while ( 1 )\n {\n v12 = 0;\n for ( i = 0; i != a2; ++i )\n {\n if ( _bittest(&v8, i) )\n v11[v9] = ++v12;\n }\n v14 = malloc(4LL * v12);\n v15 = 0LL;\n v16 = 0;\n v19[v9] = v14;\n do\n {\n if ( _bittest(&v8, v15) )\n {\n v17 = v16++;\n v14[v17] = *(_DWORD *)(a1 + 4 * v15);\n }\n ++v15;\n }\n while ( v15 != a2 );\n if ( 1 << a2 == ++v9 )\n break;\n v11[v9] = 0;\n v8 = v9;\n }\n v7 = v11;\n }\n }\n *a3 = v19;\n *a4 = 1 << a2;\n result = a5;\n *a5 = v7;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1380(long long a1, int a2, uint64_t *a3, uint32_t *a4,\n uint64_t *a5) {\n long long v5;\n uint32_t *v6;\n uint32_t *v7;\n int v8;\n long long v9;\n uint32_t *v11;\n int v12;\n unsigned int i;\n uint32_t *v14;\n long long v15;\n int v16;\n long long v17;\n uint64_t *result;\n uint64_t *v19;\n v5 = 1 << a2;\n v19 = malloc(8 * v5);\n v6 = malloc(4 * v5);\n v7 = v6;\n if ((int)v5 > 0) {\n *v6 = 0;\n if (a2 <= 0) {\n *v19 = malloc(0LL);\n } else {\n v8 = 0;\n v9 = 0LL;\n v11 = v6;\n while (1) {\n v12 = 0;\n for (i = 0; i != a2; ++i) {\n if (_bittest(&v8, i)) v11[v9] = ++v12;\n }\n v14 = malloc(4LL * v12);\n v15 = 0LL;\n v16 = 0;\n v19[v9] = v14;\n do {\n if (_bittest(&v8, v15)) {\n v17 = v16++;\n v14[v17] = *(uint32_t *)(a1 + 4 * v15);\n }\n ++v15;\n } while (v15 != a2);\n if (1 << a2 == ++v9) break;\n v11[v9] = 0;\n v8 = v9;\n }\n v7 = v11;\n }\n }\n *a3 = v19;\n *a4 = 1 << a2;\n result = a5;\n *a5 = v7;\n return result;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, int a2, uint64_t *a3, uint32_t *a4,\n uint64_t *a5) {\n long long v5;\n uint32_t *v6;\n uint32_t *v7;\n int v8;\n long long v9;\n uint32_t *v11;\n int v12;\n unsigned int i;\n uint32_t *v14;\n long long v15;\n int v16;\n long long v17;\n uint64_t *result;\n uint64_t *v19;\n v5 = 1 << a2;\n v19 = malloc(8 * v5);\n v6 = malloc(4 * v5);\n v7 = v6;\n if ((int)v5 > 0) {\n *v6 = 0;\n if (a2 <= 0) {\n *v19 = malloc(0LL);\n } else {\n v8 = 0;\n v9 = 0LL;\n v11 = v6;\n while (1) {\n v12 = 0;\n for (i = 0; i != a2; ++i) {\n if (_bittest(&v8, i)) v11[v9] = ++v12;\n }\n v14 = malloc(4LL * v12);\n v15 = 0LL;\n v16 = 0;\n v19[v9] = v14;\n do {\n if (_bittest(&v8, v15)) {\n v17 = v16++;\n v14[v17] = *(uint32_t *)(a1 + 4 * v15);\n }\n ++v15;\n } while (v15 != a2);\n if (1 << a2 == ++v9) break;\n v11[v9] = 0;\n v8 = v9;\n }\n v7 = v11;\n }\n }\n *a3 = v19;\n *a4 = 1 << a2;\n result = a5;\n *a5 = v7;\n return result;\n}" + }, + { + "index": 859, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int my_list[], int list_size, int ***output, int *output_size,\n int **output_element_sizes) {\n int total_sublists = 1 << list_size;\n int **subs = malloc(total_sublists * sizeof(int *));\n int *sizes = malloc(total_sublists * sizeof(int));\n int count = 0;\n for (int mask = 0; mask < total_sublists; mask++) {\n sizes[count] = 0;\n for (int i = 0; i < list_size; i++) {\n if (mask & (1 << i)) {\n sizes[count]++;\n }\n }\n subs[count] = malloc(sizes[count] * sizeof(int));\n int pos = 0;\n for (int i = 0; i < list_size; i++) {\n if (mask & (1 << i)) {\n subs[count][pos] = my_list[i];\n pos++;\n }\n }\n count++;\n }\n *output = subs;\n *output_size = total_sublists;\n *output_element_sizes = sizes;\n}", + "test": "int main() {\n\n int list1[] = {10, 20, 30, 40};\n\n int list_size1 = 4;\n\n int **output1;\n\n int output_size1;\n\n int *output_element_sizes1;\n\n func0(list1, list_size1, &output1, &output_size1, &output_element_sizes1);\n\n assert(output_size1 == 16); // replace specific list comparison for simplicity\n\n\n\n char *list2[] = {'X', 'Y', 'Z'};\n\n int list_size2 = 3;\n\n int **output2;\n\n int output_size2;\n\n int *output_element_sizes2;\n\n func0((int*)list2, list_size2, &output2, &output_size2, &output_element_sizes2);\n\n assert(output_size2 == 8);\n\n\n\n int list3[] = {1, 2, 3};\n\n int list_size3 = 3;\n\n int **output3;\n\n int output_size3;\n\n int *output_element_sizes3;\n\n func0(list3, list_size3, &output3, &output_size3, &output_element_sizes3);\n\n assert(output_size3 == 8);\n\n\n\n // Free memory\n\n for (int i = 0; i < output_size1; i++) {\n\n free(output1[i]);\n\n }\n\n free(output1);\n\n free(output_element_sizes1);\n\n\n\n for (int i = 0; i < output_size2; i++) {\n\n free(output2[i]);\n\n }\n\n free(output2);\n\n free(output_element_sizes2);\n\n\n\n for (int i = 0; i < output_size3; i++) {\n\n free(output3[i]);\n\n }\n\n free(output3);\n\n free(output_element_sizes3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmov $0x1,%eax\npush %r14\npush %r13\npush %r12\nmov %esi,%r12d\npush %rbp\npush %rbx\nmov %rdi,%rbx\nsub $0x38,%rsp\nmov %rcx,0x20(%rsp)\nmov %esi,%ecx\nshl %cl,%eax\nmov %rdx,0x18(%rsp)\nmovslq %eax,%rbp\nmov %r8,0x28(%rsp)\nlea 0x0(,%rbp,8),%rdi\nmov %ebp,0x14(%rsp)\ncallq 10b0 \nlea 0x0(,%rbp,4),%rdi\nmov %rax,(%rsp)\ncallq 10b0 \nmov %rax,%r13\nlea -0x1(%rbp),%eax\nmov %rax,0x8(%rsp)\ntest %ebp,%ebp\njle 14e3 \nxor %r14d,%r14d\nmov %r13,%r15\nmov %r12d,%r13d\nmovl $0x0,(%r15,%r14,4)\nmov %r14d,%r12d\ntest %r13d,%r13d\njle 14c5 \nnopl (%rax)\nxor %edi,%edi\nxor %ebp,%ebp\njmp 1452 \nxchg %ax,%ax\nmov %eax,%ebp\nbt %ebp,%r12d\njae 145f \nadd $0x1,%edi\nmov %edi,(%r15,%r14,4)\nlea 0x1(%rbp),%eax\ncmp %eax,%r13d\njne 1450 \nmovslq %edi,%rdi\nshl $0x2,%rdi\ncallq 10b0 \nmov (%rsp),%rsi\nxor %edx,%edx\nxor %r8d,%r8d\nmov %rax,(%rsi,%r14,8)\njmp 148b \nnopw 0x0(%rax,%rax,1)\nmov %rcx,%rdx\nbt %edx,%r12d\njae 149e \nmov (%rbx,%rdx,4),%esi\nmovslq %r8d,%rcx\nadd $0x1,%r8d\nmov %esi,(%rax,%rcx,4)\nlea 0x1(%rdx),%rcx\ncmp %rdx,%rbp\njne 1488 \nlea 0x1(%r14),%rax\ncmp %r14,0x8(%rsp)\nje 14e0 \nmov %rax,%r14\nmovl $0x0,(%r15,%r14,4)\nmov %r14d,%r12d\ntest %r13d,%r13d\njg 1448 \nxor %edi,%edi\ncallq 10b0 \nmov (%rsp),%rsi\nmov %rax,(%rsi,%r14,8)\nlea 0x1(%r14),%rax\ncmp %r14,0x8(%rsp)\njne 14b2 \nmov %r15,%r13\nmov 0x18(%rsp),%rax\nmov (%rsp),%rbx\nmov %rbx,(%rax)\nmov 0x20(%rsp),%rax\nmov 0x14(%rsp),%ebx\nmov %ebx,(%rax)\nmov 0x28(%rsp),%rax\nmov %r13,(%rax)\nadd $0x38,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov eax, 1\npush r14\npush r13\npush r12\nmov r12d, esi\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 38h\nmov [rsp+68h+var_48], rcx\nmov ecx, esi\nshl eax, cl\nmov [rsp+68h+var_50], rdx\nmovsxd r15, eax\nmov [rsp+68h+var_40], r8\nlea rdi, ds:0[r15*8]; size\nmov [rsp+68h+var_54], r15d\nmov [rsp+68h+var_60], r15\ncall _malloc\nlea rdi, ds:0[r15*4]; size\nmov [rsp+68h+var_68], rax\ncall _malloc\nmov r13, rax\ntest r15d, r15d\njle loc_148A\nmov dword ptr [rax], 0\ntest r12d, r12d\njle loc_147C\nmovsxd r14, r12d\nxor ebp, ebp\nxor r15d, r15d\nmov rax, r14\nmov r14d, r12d\nmov r12, rbp\nmov rbp, rbx\nmov rbx, r13\nmov r13, rax\nloc_1410:\nxor edi, edi\nxor eax, eax\nnop dword ptr [rax+00h]\nloc_1418:\nbt r15d, eax\njnb short loc_1425\nadd edi, 1\nmov [rbx+r12*4], edi\nloc_1425:\nadd eax, 1\ncmp r14d, eax\njnz short loc_1418\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov rsi, [rsp+68h+var_68]\nxor edx, edx\nxor edi, edi\nmov [rsi+r12*8], rax\nnop dword ptr [rax]\nloc_1448:\nbt r15d, edx\njnb short loc_145B\nmov esi, [rbp+rdx*4+0]\nmovsxd rcx, edi\nadd edi, 1\nmov [rax+rcx*4], esi\nloc_145B:\nadd rdx, 1\ncmp rdx, r13\njnz short loc_1448\nadd r12, 1\ncmp [rsp+68h+var_60], r12\njz short loc_14C0\nmov dword ptr [rbx+r12*4], 0\nmov r15d, r12d\njmp short loc_1410\nloc_147C:\nxor edi, edi; size\ncall _malloc\nmov rcx, [rsp+68h+var_68]\nmov [rcx], rax\nloc_148A:\nmov rax, [rsp+68h+var_50]\nmov rcx, [rsp+68h+var_68]\nmov [rax], rcx\nmov rax, [rsp+68h+var_48]\nmov ecx, [rsp+68h+var_54]\nmov [rax], ecx\nmov rax, [rsp+68h+var_40]\nmov [rax], r13\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14C0:\nmov r13, rbx\njmp short loc_148A", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, int a2, _QWORD *a3, _DWORD *a4, _QWORD *a5)\n{\n __int64 v5; // r15\n _DWORD *v6; // rax\n _DWORD *v7; // r13\n int v8; // r15d\n __int64 v9; // r12\n _DWORD *v11; // rbx\n int v12; // edi\n unsigned int i; // eax\n _DWORD *v14; // rax\n __int64 v15; // rdx\n int v16; // edi\n __int64 v17; // rcx\n _QWORD *result; // rax\n _QWORD *v19; // [rsp+0h] [rbp-68h]\n\n v5 = 1 << a2;\n v19 = malloc(8 * v5);\n v6 = malloc(4 * v5);\n v7 = v6;\n if ( (int)v5 > 0 )\n {\n *v6 = 0;\n if ( a2 <= 0 )\n {\n *v19 = malloc(0LL);\n }\n else\n {\n v8 = 0;\n v9 = 0LL;\n v11 = v6;\n while ( 1 )\n {\n v12 = 0;\n for ( i = 0; i != a2; ++i )\n {\n if ( _bittest(&v8, i) )\n v11[v9] = ++v12;\n }\n v14 = malloc(4LL * v12);\n v15 = 0LL;\n v16 = 0;\n v19[v9] = v14;\n do\n {\n if ( _bittest(&v8, v15) )\n {\n v17 = v16++;\n v14[v17] = *(_DWORD *)(a1 + 4 * v15);\n }\n ++v15;\n }\n while ( v15 != a2 );\n if ( 1 << a2 == ++v9 )\n break;\n v11[v9] = 0;\n v8 = v9;\n }\n v7 = v11;\n }\n }\n *a3 = v19;\n *a4 = 1 << a2;\n result = a5;\n *a5 = v7;\n return result;\n}", + "ida_strip_asm": "sub_1380:\nendbr64\npush r15\nmov eax, 1\npush r14\npush r13\npush r12\nmov r12d, esi\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 38h\nmov [rsp+68h+var_48], rcx\nmov ecx, esi\nshl eax, cl\nmov [rsp+68h+var_50], rdx\nmovsxd r15, eax\nmov [rsp+68h+var_40], r8\nlea rdi, ds:0[r15*8]; size\nmov [rsp+68h+var_54], r15d\nmov [rsp+68h+var_60], r15\ncall _malloc\nlea rdi, ds:0[r15*4]; size\nmov [rsp+68h+var_68], rax\ncall _malloc\nmov r13, rax\ntest r15d, r15d\njle loc_148A\nmov dword ptr [rax], 0\ntest r12d, r12d\njle loc_147C\nmovsxd r14, r12d\nxor ebp, ebp\nxor r15d, r15d\nmov rax, r14\nmov r14d, r12d\nmov r12, rbp\nmov rbp, rbx\nmov rbx, r13\nmov r13, rax\nloc_1410:\nxor edi, edi\nxor eax, eax\nnop dword ptr [rax+00h]\nloc_1418:\nbt r15d, eax\njnb short loc_1425\nadd edi, 1\nmov [rbx+r12*4], edi\nloc_1425:\nadd eax, 1\ncmp r14d, eax\njnz short loc_1418\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov rsi, [rsp+68h+var_68]\nxor edx, edx\nxor edi, edi\nmov [rsi+r12*8], rax\nnop dword ptr [rax]\nloc_1448:\nbt r15d, edx\njnb short loc_145B\nmov esi, [rbp+rdx*4+0]\nmovsxd rcx, edi\nadd edi, 1\nmov [rax+rcx*4], esi\nloc_145B:\nadd rdx, 1\ncmp rdx, r13\njnz short loc_1448\nadd r12, 1\ncmp [rsp+68h+var_60], r12\njz short loc_14C0\nmov dword ptr [rbx+r12*4], 0\nmov r15d, r12d\njmp short loc_1410\nloc_147C:\nxor edi, edi; size\ncall _malloc\nmov rcx, [rsp+68h+var_68]\nmov [rcx], rax\nloc_148A:\nmov rax, [rsp+68h+var_50]\nmov rcx, [rsp+68h+var_68]\nmov [rax], rcx\nmov rax, [rsp+68h+var_48]\nmov ecx, [rsp+68h+var_54]\nmov [rax], ecx\nmov rax, [rsp+68h+var_40]\nmov [rax], r13\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14C0:\nmov r13, rbx\njmp short loc_148A", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1380(__int64 a1, int a2, _QWORD *a3, _DWORD *a4, _QWORD *a5)\n{\n __int64 v5; // r15\n _DWORD *v6; // rax\n _DWORD *v7; // r13\n int v8; // r15d\n __int64 v9; // r12\n _DWORD *v11; // rbx\n int v12; // edi\n unsigned int i; // eax\n _DWORD *v14; // rax\n __int64 v15; // rdx\n int v16; // edi\n __int64 v17; // rcx\n _QWORD *result; // rax\n _QWORD *v19; // [rsp+0h] [rbp-68h]\n\n v5 = 1 << a2;\n v19 = malloc(8 * v5);\n v6 = malloc(4 * v5);\n v7 = v6;\n if ( (int)v5 > 0 )\n {\n *v6 = 0;\n if ( a2 <= 0 )\n {\n *v19 = malloc(0LL);\n }\n else\n {\n v8 = 0;\n v9 = 0LL;\n v11 = v6;\n while ( 1 )\n {\n v12 = 0;\n for ( i = 0; i != a2; ++i )\n {\n if ( _bittest(&v8, i) )\n v11[v9] = ++v12;\n }\n v14 = malloc(4LL * v12);\n v15 = 0LL;\n v16 = 0;\n v19[v9] = v14;\n do\n {\n if ( _bittest(&v8, v15) )\n {\n v17 = v16++;\n v14[v17] = *(_DWORD *)(a1 + 4 * v15);\n }\n ++v15;\n }\n while ( v15 != a2 );\n if ( 1 << a2 == ++v9 )\n break;\n v11[v9] = 0;\n v8 = v9;\n }\n v7 = v11;\n }\n }\n *a3 = v19;\n *a4 = 1 << a2;\n result = a5;\n *a5 = v7;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1380(long long a1, int a2, uint64_t *a3, uint32_t *a4,\n uint64_t *a5) {\n long long v5;\n uint32_t *v6;\n uint32_t *v7;\n int v8;\n long long v9;\n uint32_t *v11;\n int v12;\n unsigned int i;\n uint32_t *v14;\n long long v15;\n int v16;\n long long v17;\n uint64_t *result;\n uint64_t *v19;\n v5 = 1 << a2;\n v19 = malloc(8 * v5);\n v6 = malloc(4 * v5);\n v7 = v6;\n if ((int)v5 > 0) {\n *v6 = 0;\n if (a2 <= 0) {\n *v19 = malloc(0LL);\n } else {\n v8 = 0;\n v9 = 0LL;\n v11 = v6;\n while (1) {\n v12 = 0;\n for (i = 0; i != a2; ++i) {\n if (_bittest(&v8, i)) v11[v9] = ++v12;\n }\n v14 = malloc(4LL * v12);\n v15 = 0LL;\n v16 = 0;\n v19[v9] = v14;\n do {\n if (_bittest(&v8, v15)) {\n v17 = v16++;\n v14[v17] = *(uint32_t *)(a1 + 4 * v15);\n }\n ++v15;\n } while (v15 != a2);\n if (1 << a2 == ++v9) break;\n v11[v9] = 0;\n v8 = v9;\n }\n v7 = v11;\n }\n }\n *a3 = v19;\n *a4 = 1 << a2;\n result = a5;\n *a5 = v7;\n return result;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, int a2, uint64_t *a3, uint32_t *a4,\n uint64_t *a5) {\n long long v5;\n uint32_t *v6;\n uint32_t *v7;\n int v8;\n long long v9;\n uint32_t *v11;\n int v12;\n unsigned int i;\n uint32_t *v14;\n long long v15;\n int v16;\n long long v17;\n uint64_t *result;\n uint64_t *v19;\n v5 = 1 << a2;\n v19 = malloc(8 * v5);\n v6 = malloc(4 * v5);\n v7 = v6;\n if ((int)v5 > 0) {\n *v6 = 0;\n if (a2 <= 0) {\n *v19 = malloc(0LL);\n } else {\n v8 = 0;\n v9 = 0LL;\n v11 = v6;\n while (1) {\n v12 = 0;\n for (i = 0; i != a2; ++i) {\n if (_bittest(&v8, i)) v11[v9] = ++v12;\n }\n v14 = malloc(4LL * v12);\n v15 = 0LL;\n v16 = 0;\n v19[v9] = v14;\n do {\n if (_bittest(&v8, v15)) {\n v17 = v16++;\n v14[v17] = *(uint32_t *)(a1 + 4 * v15);\n }\n ++v15;\n } while (v15 != a2);\n if (1 << a2 == ++v9) break;\n v11[v9] = 0;\n v8 = v9;\n }\n v7 = v11;\n }\n }\n *a3 = v19;\n *a4 = 1 << a2;\n result = a5;\n *a5 = v7;\n return result;\n}" + }, + { + "index": 860, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "const char *func0(const char *string) {\n regex_t reg;\n const char *regex = \"[a-zA-Z0-9]$\";\n int ret;\n ret = regcomp(®, regex, REG_EXTENDED);\n if (ret) {\n return \"Error compiling regex\";\n }\n regmatch_t matches[1];\n ret = regexec(®, string, 1, matches, 0);\n regfree(®);\n if (!ret) {\n return \"Accept\";\n } else {\n return \"Discard\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"dawood@\"), \"Discard\") == 0);\n\n assert(strcmp(func0(\"skdmsam326\"), \"Accept\") == 0);\n\n assert(strcmp(func0(\"cooltricks@\"), \"Discard\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x70,%rsp\nmov %rdi,-0x68(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0xdf9(%rip),%rax\nmov %rax,-0x58(%rbp)\nmov -0x58(%rbp),%rcx\nlea -0x50(%rbp),%rax\nmov $0x1,%edx\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 10d0 \nmov %eax,-0x5c(%rbp)\ncmpl $0x0,-0x5c(%rbp)\nje 123d \nlea 0xdda(%rip),%rax\njmp 1284 \nlea -0x10(%rbp),%rdx\nmov -0x68(%rbp),%rsi\nlea -0x50(%rbp),%rax\nmov $0x0,%r8d\nmov %rdx,%rcx\nmov $0x1,%edx\nmov %rax,%rdi\ncallq 10f0 \nmov %eax,-0x5c(%rbp)\nlea -0x50(%rbp),%rax\nmov %rax,%rdi\ncallq 10a0 \ncmpl $0x0,-0x5c(%rbp)\njne 127d \nlea 0xdb0(%rip),%rax\njmp 1284 \nlea 0xdae(%rip),%rax\nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 1298 \ncallq 10b0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aAZaZ09; \"[a-zA-Z0-9]$\"\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+var_5C], eax\ncmp [rbp+var_5C], 0\njz short loc_123D\nlea rax, aErrorCompiling; \"Error compiling regex\"\njmp short loc_1284\nloc_123D:\nlea rdx, [rbp+pmatch]\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov rcx, rdx; pmatch\nmov edx, 1; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_5C], eax\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\ncmp [rbp+var_5C], 0\njnz short loc_127D\nlea rax, aAccept; \"Accept\"\njmp short loc_1284\nloc_127D:\nlea rax, s2; \"Discard\"\nloc_1284:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1298\ncall ___stack_chk_fail\nlocret_1298:\nleave\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n int v2; // [rsp+14h] [rbp-5Ch]\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n regmatch_t pmatch; // [rsp+60h] [rbp-10h] BYREF\n unsigned __int64 v5; // [rsp+68h] [rbp-8h]\n\n v5 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"[a-zA-Z0-9]$\", 1) )\n return \"Error compiling regex\";\n v2 = regexec(&preg, a1, 1uLL, &pmatch, 0);\n regfree(&preg);\n if ( v2 )\n return \"Discard\";\n else\n return \"Accept\";\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aAZaZ09; \"[a-zA-Z0-9]$\"\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+var_5C], eax\ncmp [rbp+var_5C], 0\njz short loc_123D\nlea rax, aErrorCompiling; \"Error compiling regex\"\njmp short loc_1284\nloc_123D:\nlea rdx, [rbp+pmatch]\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov rcx, rdx; pmatch\nmov edx, 1; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_5C], eax\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\ncmp [rbp+var_5C], 0\njnz short loc_127D\nlea rax, aAccept; \"Accept\"\njmp short loc_1284\nloc_127D:\nlea rax, s2; \"Discard\"\nloc_1284:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1298\ncall ___stack_chk_fail\nlocret_1298:\nleave\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_11E9(const char *a1)\n{\n int v2; // [rsp+14h] [rbp-5Ch]\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n regmatch_t pmatch; // [rsp+60h] [rbp-10h] BYREF\n unsigned __int64 v5; // [rsp+68h] [rbp-8h]\n\n v5 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"[a-zA-Z0-9]$\", 1) )\n return \"Error compiling regex\";\n v2 = regexec(&preg, a1, 1uLL, &pmatch, 0);\n regfree(&preg);\n if ( v2 )\n return \"Discard\";\n else\n return \"Accept\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_11E9(const char *a1) {\n int v2;\n regex_t preg;\n regmatch_t pmatch;\n unsigned long long v5;\n v5 = __readfsqword(40u);\n if (regcomp(&preg, \"[a-zA-Z0-9]$\", 1)) return \"Error compiling regex\";\n v2 = regexec(&preg, a1, 1uLL, &pmatch, 0);\n regfree(&preg);\n if (v2)\n return \"Discard\";\n else\n return \"Accept\";\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n int v2;\n regex_t preg;\n regmatch_t pmatch;\n unsigned long long v5;\n v5 = __readfsqword(40u);\n if (regcomp(&preg, \"[a-zA-Z0-9]$\", 1)) return \"Error compiling regex\";\n v2 = regexec(&preg, a1, 1uLL, &pmatch, 0);\n regfree(&preg);\n if (v2)\n return \"Discard\";\n else\n return \"Accept\";\n}" + }, + { + "index": 860, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "const char *func0(const char *string) {\n regex_t reg;\n const char *regex = \"[a-zA-Z0-9]$\";\n int ret;\n ret = regcomp(®, regex, REG_EXTENDED);\n if (ret) {\n return \"Error compiling regex\";\n }\n regmatch_t matches[1];\n ret = regexec(®, string, 1, matches, 0);\n regfree(®);\n if (!ret) {\n return \"Accept\";\n } else {\n return \"Discard\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"dawood@\"), \"Discard\") == 0);\n\n assert(strcmp(func0(\"skdmsam326\"), \"Accept\") == 0);\n\n assert(strcmp(func0(\"cooltricks@\"), \"Discard\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x58,%rsp\nmov %rdi,%rbx\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nmov $0x1,%edx\nlea 0xe34(%rip),%rsi\ncallq 10c0 \nmov %eax,%edx\nlea 0xe01(%rip),%rax\ntest %edx,%edx\nje 121e \nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 125c \nadd $0x58,%rsp\npop %rbx\npop %rbp\nretq\nlea 0x40(%rsp),%rcx\nmov %rsp,%rbp\nmov $0x0,%r8d\nmov $0x1,%edx\nmov %rbx,%rsi\nmov %rbp,%rdi\ncallq 10d0 \nmov %eax,%ebx\nmov %rbp,%rdi\ncallq 1090 \ntest %ebx,%ebx\nlea 0xdcb(%rip),%rax\nlea 0xdcb(%rip),%rdx\ncmovne %rdx,%rax\njmp 1207 \ncallq 10a0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+68h+var_20], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"[a-zA-Z0-9]$\"\ncall _regcomp\nmov edx, eax\nlea rax, aErrorCompiling; \"Error compiling regex\"\ntest edx, edx\njz short loc_123E\nloc_1227:\nmov rdx, [rsp+68h+var_20]\nsub rdx, fs:28h\njnz short loc_127C\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_123E:\nlea rcx, [rsp+68h+pmatch]; pmatch\nmov rbp, rsp\nmov r8d, 0; eflags\nmov edx, 1; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov ebx, eax\nmov rdi, rbp; preg\ncall _regfree\ntest ebx, ebx\nlea rax, s2; \"Discard\"\nlea rdx, aAccept; \"Accept\"\ncmovz rax, rdx\njmp short loc_1227\nloc_127C:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // edx\n const char *result; // rax\n int v3; // ebx\n regex_t v4; // [rsp+0h] [rbp-68h] BYREF\n regmatch_t pmatch; // [rsp+40h] [rbp-28h] BYREF\n unsigned __int64 v6; // [rsp+48h] [rbp-20h]\n\n v6 = __readfsqword(0x28u);\n v1 = regcomp(&v4, \"[a-zA-Z0-9]$\", 1);\n result = \"Error compiling regex\";\n if ( !v1 )\n {\n v3 = regexec(&v4, string, 1uLL, &pmatch, 0);\n regfree(&v4);\n result = \"Discard\";\n if ( !v3 )\n return \"Accept\";\n }\n return result;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+68h+var_20], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"[a-zA-Z0-9]$\"\ncall _regcomp\nmov edx, eax\nlea rax, aErrorCompiling; \"Error compiling regex\"\ntest edx, edx\njz short loc_123E\nloc_1227:\nmov rdx, [rsp+68h+var_20]\nsub rdx, fs:28h\njnz short loc_127C\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_123E:\nlea rcx, [rsp+68h+pmatch]; pmatch\nmov rbp, rsp\nmov r8d, 0; eflags\nmov edx, 1; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov ebx, eax\nmov rdi, rbp; preg\ncall _regfree\ntest ebx, ebx\nlea rax, s2; \"Discard\"\nlea rdx, aAccept; \"Accept\"\ncmovz rax, rdx\njmp short loc_1227\nloc_127C:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_11E9(char *string)\n{\n int v1; // edx\n const char *result; // rax\n int v3; // ebx\n regex_t v4; // [rsp+0h] [rbp-68h] BYREF\n regmatch_t pmatch; // [rsp+40h] [rbp-28h] BYREF\n unsigned __int64 v6; // [rsp+48h] [rbp-20h]\n\n v6 = __readfsqword(0x28u);\n v1 = regcomp(&v4, \"[a-zA-Z0-9]$\", 1);\n result = \"Error compiling regex\";\n if ( !v1 )\n {\n v3 = regexec(&v4, string, 1uLL, &pmatch, 0);\n regfree(&v4);\n result = \"Discard\";\n if ( !v3 )\n return \"Accept\";\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_11E9(char *string) {\n int v1;\n const char *result;\n int v3;\n regex_t v4;\n regmatch_t pmatch;\n unsigned long long v6;\n v6 = __readfsqword(40u);\n v1 = regcomp(&v4, \"[a-zA-Z0-9]$\", 1);\n result = \"Error compiling regex\";\n if (!v1) {\n v3 = regexec(&v4, string, 1uLL, &pmatch, 0);\n regfree(&v4);\n result = \"Discard\";\n if (!v3) return \"Accept\";\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n const char *result;\n int v3;\n regex_t v4;\n regmatch_t pmatch;\n unsigned long long v6;\n v6 = __readfsqword(40u);\n v1 = regcomp(&v4, \"[a-zA-Z0-9]$\", 1);\n result = \"Error compiling regex\";\n if (!v1) {\n v3 = regexec(&v4, string, 1uLL, &pmatch, 0);\n regfree(&v4);\n result = \"Discard\";\n if (!v3) return \"Accept\";\n }\n return result;\n}" + }, + { + "index": 860, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "const char *func0(const char *string) {\n regex_t reg;\n const char *regex = \"[a-zA-Z0-9]$\";\n int ret;\n ret = regcomp(®, regex, REG_EXTENDED);\n if (ret) {\n return \"Error compiling regex\";\n }\n regmatch_t matches[1];\n ret = regexec(®, string, 1, matches, 0);\n regfree(®);\n if (!ret) {\n return \"Accept\";\n } else {\n return \"Discard\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"dawood@\"), \"Discard\") == 0);\n\n assert(strcmp(func0(\"skdmsam326\"), \"Accept\") == 0);\n\n assert(strcmp(func0(\"cooltricks@\"), \"Discard\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov $0x1,%edx\nlea 0xd67(%rip),%rsi\npush %rbp\nmov %rdi,%rbp\nsub $0x58,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%r12\nmov %r12,%rdi\ncallq 10c0 \nmov %eax,%r8d\nlea 0xd15(%rip),%rax\ntest %r8d,%r8d\njne 1327 \nmov $0x1,%edx\nmov %rbp,%rsi\nlea 0x40(%rsp),%rcx\nmov %r12,%rdi\ncallq 10d0 \nmov %r12,%rdi\nmov %eax,%ebp\ncallq 1090 \ntest %ebp,%ebp\nlea 0xcfe(%rip),%rax\nlea 0xcfe(%rip),%rdx\ncmovne %rdx,%rax\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 133f \nadd $0x58,%rsp\npop %rbp\npop %r12\nretq\ncallq 10a0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"[a-zA-Z0-9]$\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nmov edx, eax\nlea rax, aErrorCompiling; \"Error compiling regex\"\ntest edx, edx\njnz short loc_1337\nxor r8d, r8d; eflags\nmov edx, 1; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\nlea rcx, [rsp+pmatch]; pmatch\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, s2; \"Discard\"\nlea rdx, aAccept; \"Accept\"\ncmovz rax, rdx\nloc_1337:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_134E\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_134E:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // edx\n const char *result; // rax\n int v3; // ebx\n regex_t vars0; // [rsp+0h] [rbp+0h] BYREF\n regmatch_t pmatch; // [rsp+40h] [rbp+40h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n v1 = regcomp(&vars0, \"[a-zA-Z0-9]$\", 1);\n result = \"Error compiling regex\";\n if ( !v1 )\n {\n v3 = regexec(&vars0, string, 1uLL, &pmatch, 0);\n regfree(&vars0);\n result = \"Discard\";\n if ( !v3 )\n return \"Accept\";\n }\n return result;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"[a-zA-Z0-9]$\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nmov edx, eax\nlea rax, aErrorCompiling; \"Error compiling regex\"\ntest edx, edx\njnz short loc_1337\nxor r8d, r8d; eflags\nmov edx, 1; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\nlea rcx, [rsp+pmatch]; pmatch\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, s2; \"Discard\"\nlea rdx, aAccept; \"Accept\"\ncmovz rax, rdx\nloc_1337:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_134E\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_134E:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_12C0(char *string)\n{\n int v1; // edx\n const char *result; // rax\n int v3; // ebx\n regex_t vars0; // [rsp+0h] [rbp+0h] BYREF\n regmatch_t pmatch; // [rsp+40h] [rbp+40h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n v1 = regcomp(&vars0, \"[a-zA-Z0-9]$\", 1);\n result = \"Error compiling regex\";\n if ( !v1 )\n {\n v3 = regexec(&vars0, string, 1uLL, &pmatch, 0);\n regfree(&vars0);\n result = \"Discard\";\n if ( !v3 )\n return \"Accept\";\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_12C0(char *string) {\n int v1;\n const char *result;\n int v3;\n regex_t vars0;\n regmatch_t pmatch;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n v1 = regcomp(&vars0, \"[a-zA-Z0-9]$\", 1);\n result = \"Error compiling regex\";\n if (!v1) {\n v3 = regexec(&vars0, string, 1uLL, &pmatch, 0);\n regfree(&vars0);\n result = \"Discard\";\n if (!v3) return \"Accept\";\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n const char *result;\n int v3;\n regex_t vars0;\n regmatch_t pmatch;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n v1 = regcomp(&vars0, \"[a-zA-Z0-9]$\", 1);\n result = \"Error compiling regex\";\n if (!v1) {\n v3 = regexec(&vars0, string, 1uLL, &pmatch, 0);\n regfree(&vars0);\n result = \"Discard\";\n if (!v3) return \"Accept\";\n }\n return result;\n}" + }, + { + "index": 860, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "const char *func0(const char *string) {\n regex_t reg;\n const char *regex = \"[a-zA-Z0-9]$\";\n int ret;\n ret = regcomp(®, regex, REG_EXTENDED);\n if (ret) {\n return \"Error compiling regex\";\n }\n regmatch_t matches[1];\n ret = regexec(®, string, 1, matches, 0);\n regfree(®);\n if (!ret) {\n return \"Accept\";\n } else {\n return \"Discard\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"dawood@\"), \"Discard\") == 0);\n\n assert(strcmp(func0(\"skdmsam326\"), \"Accept\") == 0);\n\n assert(strcmp(func0(\"cooltricks@\"), \"Discard\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov $0x1,%edx\nlea 0xd67(%rip),%rsi\npush %rbp\nmov %rdi,%rbp\nsub $0x58,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%r12\nmov %r12,%rdi\ncallq 10c0 \nmov %eax,%r8d\nlea 0xd15(%rip),%rax\ntest %r8d,%r8d\njne 1327 \nmov $0x1,%edx\nmov %rbp,%rsi\nlea 0x40(%rsp),%rcx\nmov %r12,%rdi\ncallq 10d0 \nmov %r12,%rdi\nmov %eax,%ebp\ncallq 1090 \ntest %ebp,%ebp\nlea 0xcfe(%rip),%rax\nlea 0xcfe(%rip),%rdx\ncmovne %rdx,%rax\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 133f \nadd $0x58,%rsp\npop %rbp\npop %r12\nretq\ncallq 10a0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"[a-zA-Z0-9]$\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nmov edx, eax\nlea rax, aErrorCompiling; \"Error compiling regex\"\ntest edx, edx\njnz short loc_1337\nxor r8d, r8d; eflags\nmov edx, 1; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\nlea rcx, [rsp+pmatch]; pmatch\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, s2; \"Discard\"\nlea rdx, aAccept; \"Accept\"\ncmovz rax, rdx\nloc_1337:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_134E\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_134E:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // edx\n const char *result; // rax\n int v3; // ebx\n regex_t vars0; // [rsp+0h] [rbp+0h] BYREF\n regmatch_t pmatch; // [rsp+40h] [rbp+40h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n v1 = regcomp(&vars0, \"[a-zA-Z0-9]$\", 1);\n result = \"Error compiling regex\";\n if ( !v1 )\n {\n v3 = regexec(&vars0, string, 1uLL, &pmatch, 0);\n regfree(&vars0);\n result = \"Discard\";\n if ( !v3 )\n return \"Accept\";\n }\n return result;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"[a-zA-Z0-9]$\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nmov edx, eax\nlea rax, aErrorCompiling; \"Error compiling regex\"\ntest edx, edx\njnz short loc_1337\nxor r8d, r8d; eflags\nmov edx, 1; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\nlea rcx, [rsp+pmatch]; pmatch\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nlea rax, s2; \"Discard\"\nlea rdx, aAccept; \"Accept\"\ncmovz rax, rdx\nloc_1337:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_134E\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_134E:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_12C0(char *string)\n{\n int v1; // edx\n const char *result; // rax\n int v3; // ebx\n regex_t vars0; // [rsp+0h] [rbp+0h] BYREF\n regmatch_t pmatch; // [rsp+40h] [rbp+40h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n v1 = regcomp(&vars0, \"[a-zA-Z0-9]$\", 1);\n result = \"Error compiling regex\";\n if ( !v1 )\n {\n v3 = regexec(&vars0, string, 1uLL, &pmatch, 0);\n regfree(&vars0);\n result = \"Discard\";\n if ( !v3 )\n return \"Accept\";\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_12C0(char *string) {\n int v1;\n const char *result;\n int v3;\n regex_t vars0;\n regmatch_t pmatch;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n v1 = regcomp(&vars0, \"[a-zA-Z0-9]$\", 1);\n result = \"Error compiling regex\";\n if (!v1) {\n v3 = regexec(&vars0, string, 1uLL, &pmatch, 0);\n regfree(&vars0);\n result = \"Discard\";\n if (!v3) return \"Accept\";\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n const char *result;\n int v3;\n regex_t vars0;\n regmatch_t pmatch;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n v1 = regcomp(&vars0, \"[a-zA-Z0-9]$\", 1);\n result = \"Error compiling regex\";\n if (!v1) {\n v3 = regexec(&vars0, string, 1uLL, &pmatch, 0);\n regfree(&vars0);\n result = \"Discard\";\n if (!v3) return \"Accept\";\n }\n return result;\n}" + }, + { + "index": 861, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\nint is_anagram(const char *str1, const char *str2) {\n\n int count1[256] = {0};\n\n int count2[256] = {0};\n\n while (*str1) {\n\n count1[(unsigned char)*str1++]++;\n\n }\n\n while (*str2) {\n\n count2[(unsigned char)*str2++]++;\n\n }\n\n for(int i=0;i<256;i++) {\n\n if(count1[i] != count2[i])\n\n return 0;\n\n }\n\n return 1;\n\n}\n\n\n\n", + "func": "int func0(char* texts[], int texts_size, char* str, char* result[]) {\n int result_size = 0;\n for (int i = 0; i < texts_size; i++) {\n if (is_anagram(texts[i], str)) {\n result[result_size++] = texts[i];\n }\n }\n return result_size;\n}", + "test": "int main() {\n\n // Test case 1\n\n char* texts1[] = {\"bcda\", \"abce\", \"cbda\", \"cbea\", \"adcb\"};\n\n char* str1 = \"abcd\";\n\n char* expected1[] = {\"bcda\", \"cbda\", \"adcb\"};\n\n char* result1[5];\n\n int size1 = func0(texts1, 5, str1, result1);\n\n assert(size1 == 3);\n\n assert(strcmp(result1[0], expected1[0]) == 0);\n\n assert(strcmp(result1[1], expected1[1]) == 0);\n\n assert(strcmp(result1[2], expected1[2]) == 0);\n\n\n\n // Test case 2\n\n char* texts2[] = {\"recitals\", \" python\"};\n\n char* str2 = \"articles\";\n\n char* expected2[] = {\"recitals\"};\n\n char* result2[2];\n\n int size2 = func0(texts2, 2, str2, result2);\n\n assert(size2 == 1);\n\n assert(strcmp(result2[0], expected2[0]) == 0);\n\n\n\n // Test case 3\n\n char* texts3[] = {\" keep\", \" abcdef\", \" xyz\"};\n\n char* str3 = \" peek\";\n\n char* expected3[] = {\" keep\"};\n\n char* result3[3];\n\n int size3 = func0(texts3, 3, str3, result3);\n\n assert(size3 == 1);\n\n assert(strcmp(result3[0], expected3[0]) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %rcx,-0x30(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 1350 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0x28(%rbp),%rdx\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1189 \ntest %eax,%eax\nje 134c \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x8(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x8(%rbp)\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x30(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%rax\nmov %rax,(%rdx)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 12ed \nmov -0x8(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_30], rcx\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_1350\nloc_12ED:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov rdx, [rbp+var_28]\nmov rsi, rdx\nmov rdi, rax\ncall is_anagram\ntest eax, eax\njz short loc_134C\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_8]\nlea edx, [rax+1]\nmov [rbp+var_8], edx\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_30]\nadd rdx, rax\nmov rax, [rcx]\nmov [rdx], rax\nloc_134C:\nadd [rbp+var_4], 1\nloc_1350:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_12ED\nmov eax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3, __int64 a4)\n{\n int v4; // eax\n unsigned int v8; // [rsp+28h] [rbp-8h]\n int i; // [rsp+2Ch] [rbp-4h]\n\n v8 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( (unsigned int)is_anagram(*(_QWORD *)(8LL * i + a1), a3) )\n {\n v4 = v8++;\n *(_QWORD *)(a4 + 8LL * v4) = *(_QWORD *)(8LL * i + a1);\n }\n }\n return v8;\n}", + "ida_strip_asm": "sub_12C2:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_30], rcx\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_1350\nloc_12ED:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov rdx, [rbp+var_28]\nmov rsi, rdx\nmov rdi, rax\ncall sub_1189\ntest eax, eax\njz short loc_134C\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_8]\nlea edx, [rax+1]\nmov [rbp+var_8], edx\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_30]\nadd rdx, rax\nmov rax, [rcx]\nmov [rdx], rax\nloc_134C:\nadd [rbp+var_4], 1\nloc_1350:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_12ED\nmov eax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12C2(__int64 a1, int a2, __int64 a3, __int64 a4)\n{\n int v4; // eax\n unsigned int v8; // [rsp+28h] [rbp-8h]\n int i; // [rsp+2Ch] [rbp-4h]\n\n v8 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( (unsigned int)sub_1189(*(_QWORD *)(8LL * i + a1), a3) )\n {\n v4 = v8++;\n *(_QWORD *)(a4 + 8LL * v4) = *(_QWORD *)(8LL * i + a1);\n }\n }\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12C2(long long a1, int a2, long long a3, long long a4) {\n int v4;\n unsigned int v8;\n int i;\n v8 = 0;\n for (i = 0; i < a2; ++i) {\n if ((unsigned int)sub_1189(*(uint64_t *)(8LL * i + a1), a3)) {\n v4 = v8++;\n *(uint64_t *)(a4 + 8LL * v4) = *(uint64_t *)(8LL * i + a1);\n }\n }\n return v8;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3, long long a4) {\n int v4;\n unsigned int v8;\n int i;\n v8 = 0;\n for (i = 0; i < a2; ++i) {\n if ((unsigned int)is_anagram(*(uint64_t *)(8LL * i + a1), a3)) {\n v4 = v8++;\n *(uint64_t *)(a4 + 8LL * v4) = *(uint64_t *)(8LL * i + a1);\n }\n }\n return v8;\n}" + }, + { + "index": 861, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\nint is_anagram(const char *str1, const char *str2) {\n\n int count1[256] = {0};\n\n int count2[256] = {0};\n\n while (*str1) {\n\n count1[(unsigned char)*str1++]++;\n\n }\n\n while (*str2) {\n\n count2[(unsigned char)*str2++]++;\n\n }\n\n for(int i=0;i<256;i++) {\n\n if(count1[i] != count2[i])\n\n return 0;\n\n }\n\n return 1;\n\n}\n\n\n\n", + "func": "int func0(char* texts[], int texts_size, char* str, char* result[]) {\n int result_size = 0;\n for (int i = 0; i < texts_size; i++) {\n if (is_anagram(texts[i], str)) {\n result[result_size++] = texts[i];\n }\n }\n return result_size;\n}", + "test": "int main() {\n\n // Test case 1\n\n char* texts1[] = {\"bcda\", \"abce\", \"cbda\", \"cbea\", \"adcb\"};\n\n char* str1 = \"abcd\";\n\n char* expected1[] = {\"bcda\", \"cbda\", \"adcb\"};\n\n char* result1[5];\n\n int size1 = func0(texts1, 5, str1, result1);\n\n assert(size1 == 3);\n\n assert(strcmp(result1[0], expected1[0]) == 0);\n\n assert(strcmp(result1[1], expected1[1]) == 0);\n\n assert(strcmp(result1[2], expected1[2]) == 0);\n\n\n\n // Test case 2\n\n char* texts2[] = {\"recitals\", \" python\"};\n\n char* str2 = \"articles\";\n\n char* expected2[] = {\"recitals\"};\n\n char* result2[2];\n\n int size2 = func0(texts2, 2, str2, result2);\n\n assert(size2 == 1);\n\n assert(strcmp(result2[0], expected2[0]) == 0);\n\n\n\n // Test case 3\n\n char* texts3[] = {\" keep\", \" abcdef\", \" xyz\"};\n\n char* str3 = \" peek\";\n\n char* expected3[] = {\" keep\"};\n\n char* result3[3];\n\n int size3 = func0(texts3, 3, str3, result3);\n\n assert(size3 == 1);\n\n assert(strcmp(result3[0], expected3[0]) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\ntest %esi,%esi\njle 1280 \nmov %rdx,%r13\nmov %rcx,%r15\nmov %rdi,%rbx\nlea -0x1(%rsi),%eax\nlea 0x8(%rdi,%rax,8),%r14\nmov $0x0,%r12d\njmp 1260 \nadd $0x8,%rbx\ncmp %r14,%rbx\nje 1286 \nmov (%rbx),%rbp\nmov %r13,%rsi\nmov %rbp,%rdi\ncallq 1169 \ntest %eax,%eax\nje 1257 \nmovslq %r12d,%rax\nmov %rbp,(%r15,%rax,8)\nlea 0x1(%r12),%r12d\njmp 1257 \nmov $0x0,%r12d\nmov %r12d,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\ntest esi, esi\njle short loc_129F\nmov r13, rdx\nmov r15, rcx\nmov rbx, rdi\nmovsxd rsi, esi\nlea r14, [rdi+rsi*8]\nmov r12d, 0\njmp short loc_127F\nloc_1276:\nadd rbx, 8\ncmp rbx, r14\njz short loc_12A5\nloc_127F:\nmov rbp, [rbx]\nmov rsi, r13\nmov rdi, rbp\ncall is_anagram\ntest eax, eax\njz short loc_1276\nmovsxd rax, r12d\nmov [r15+rax*8], rbp\nlea r12d, [r12+1]\njmp short loc_1276\nloc_129F:\nmov r12d, 0\nloc_12A5:\nmov eax, r12d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "__int64 __fastcall func0(_QWORD *a1, int a2, __int64 a3, __int64 a4)\n{\n _QWORD *v6; // rbx\n unsigned int v7; // r12d\n __int64 v8; // rbp\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v6 = a1;\n v7 = 0;\n do\n {\n v8 = *v6;\n if ( (unsigned int)is_anagram(*v6, a3) )\n *(_QWORD *)(a4 + 8LL * (int)v7++) = v8;\n ++v6;\n }\n while ( v6 != &a1[a2] );\n }\n return v7;\n}", + "ida_strip_asm": "sub_1248:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\ntest esi, esi\njle short loc_129F\nmov r13, rdx\nmov r15, rcx\nmov rbx, rdi\nmovsxd rsi, esi\nlea r14, [rdi+rsi*8]\nmov r12d, 0\njmp short loc_127F\nloc_1276:\nadd rbx, 8\ncmp rbx, r14\njz short loc_12A5\nloc_127F:\nmov rbp, [rbx]\nmov rsi, r13\nmov rdi, rbp\ncall sub_1189\ntest eax, eax\njz short loc_1276\nmovsxd rax, r12d\nmov [r15+rax*8], rbp\nlea r12d, [r12+1]\njmp short loc_1276\nloc_129F:\nmov r12d, 0\nloc_12A5:\nmov eax, r12d\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1248(_QWORD *a1, int a2, __int64 a3, __int64 a4)\n{\n _QWORD *v6; // rbx\n unsigned int v7; // r12d\n __int64 v8; // rbp\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v6 = a1;\n v7 = 0;\n do\n {\n v8 = *v6;\n if ( (unsigned int)sub_1189(*v6, a3) )\n *(_QWORD *)(a4 + 8LL * (int)v7++) = v8;\n ++v6;\n }\n while ( v6 != &a1[a2] );\n }\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1248(uint64_t *a1, int a2, long long a3, long long a4) {\n uint64_t *v6;\n unsigned int v7;\n long long v8;\n if (a2 <= 0) {\n return 0;\n } else {\n v6 = a1;\n v7 = 0;\n do {\n v8 = *v6;\n if ((unsigned int)sub_1189(*v6, a3))\n *(uint64_t *)(a4 + 8LL * (int)v7++) = v8;\n ++v6;\n } while (v6 != &a1[a2]);\n }\n return v7;\n}", + "ida_pseudo_norm": "long long func0(uint64_t *a1, int a2, long long a3, long long a4) {\n uint64_t *v6;\n unsigned int v7;\n long long v8;\n if (a2 <= 0) {\n return 0;\n } else {\n v6 = a1;\n v7 = 0;\n do {\n v8 = *v6;\n if ((unsigned int)is_anagram(*v6, a3))\n *(uint64_t *)(a4 + 8LL * (int)v7++) = v8;\n ++v6;\n } while (v6 != &a1[a2]);\n }\n return v7;\n}" + }, + { + "index": 861, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\nint is_anagram(const char *str1, const char *str2) {\n\n int count1[256] = {0};\n\n int count2[256] = {0};\n\n while (*str1) {\n\n count1[(unsigned char)*str1++]++;\n\n }\n\n while (*str2) {\n\n count2[(unsigned char)*str2++]++;\n\n }\n\n for(int i=0;i<256;i++) {\n\n if(count1[i] != count2[i])\n\n return 0;\n\n }\n\n return 1;\n\n}\n\n\n\n", + "func": "int func0(char* texts[], int texts_size, char* str, char* result[]) {\n int result_size = 0;\n for (int i = 0; i < texts_size; i++) {\n if (is_anagram(texts[i], str)) {\n result[result_size++] = texts[i];\n }\n }\n return result_size;\n}", + "test": "int main() {\n\n // Test case 1\n\n char* texts1[] = {\"bcda\", \"abce\", \"cbda\", \"cbea\", \"adcb\"};\n\n char* str1 = \"abcd\";\n\n char* expected1[] = {\"bcda\", \"cbda\", \"adcb\"};\n\n char* result1[5];\n\n int size1 = func0(texts1, 5, str1, result1);\n\n assert(size1 == 3);\n\n assert(strcmp(result1[0], expected1[0]) == 0);\n\n assert(strcmp(result1[1], expected1[1]) == 0);\n\n assert(strcmp(result1[2], expected1[2]) == 0);\n\n\n\n // Test case 2\n\n char* texts2[] = {\"recitals\", \" python\"};\n\n char* str2 = \"articles\";\n\n char* expected2[] = {\"recitals\"};\n\n char* result2[2];\n\n int size2 = func0(texts2, 2, str2, result2);\n\n assert(size2 == 1);\n\n assert(strcmp(result2[0], expected2[0]) == 0);\n\n\n\n // Test case 3\n\n char* texts3[] = {\" keep\", \" abcdef\", \" xyz\"};\n\n char* str3 = \" peek\";\n\n char* expected3[] = {\" keep\"};\n\n char* result3[3];\n\n int size3 = func0(texts3, 3, str3, result3);\n\n assert(size3 == 1);\n\n assert(strcmp(result3[0], expected3[0]) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\ntest %esi,%esi\njle 1580 \nlea -0x1(%rsi),%eax\nmov %rdx,%r13\nmov %rcx,%r14\nmov %rdi,%rbx\nlea 0x8(%rdi,%rax,8),%r15\nxor %r12d,%r12d\nnopw 0x0(%rax,%rax,1)\nmov (%rbx),%rbp\nmov %r13,%rsi\nmov %rbp,%rdi\ncallq 1430 \ntest %eax,%eax\nje 155d \nmovslq %r12d,%rax\nadd $0x1,%r12d\nmov %rbp,(%r14,%rax,8)\nadd $0x8,%rbx\ncmp %r15,%rbx\njne 1540 \nadd $0x8,%rsp\nmov %r12d,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax,%rax,1)\nxor %r12d,%r12d\njmp 1566 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\ntest esi, esi\njle short loc_15B0\nmovsxd rsi, esi\nmov r13, rdx\nmov r14, rcx\nmov rbx, rdi\nlea r15, [rdi+rsi*8]\nxor r12d, r12d\nnop dword ptr [rax+00000000h]\nloc_1570:\nmov rbp, [rbx]\nmov rsi, r13\nmov rdi, rbp\ncall is_anagram\ntest eax, eax\njz short loc_158D\nmovsxd rax, r12d\nadd r12d, 1\nmov [r14+rax*8], rbp\nloc_158D:\nadd rbx, 8\ncmp rbx, r15\njnz short loc_1570\nloc_1596:\nadd rsp, 8\nmov eax, r12d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15B0:\nxor r12d, r12d\njmp short loc_1596", + "ida_pseudo": "__int64 __fastcall func0(_QWORD *a1, int a2, __int64 a3, __int64 a4)\n{\n _QWORD *v6; // rbx\n unsigned int v7; // r12d\n __int64 v8; // rbp\n __int64 v9; // rax\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v6 = a1;\n v7 = 0;\n do\n {\n v8 = *v6;\n if ( (unsigned int)is_anagram(*v6, a3) )\n {\n v9 = (int)v7++;\n *(_QWORD *)(a4 + 8 * v9) = v8;\n }\n ++v6;\n }\n while ( v6 != &a1[a2] );\n }\n return v7;\n}", + "ida_strip_asm": "sub_1540:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\ntest esi, esi\njle short loc_15B0\nmovsxd rsi, esi\nmov r13, rdx\nmov r14, rcx\nmov rbx, rdi\nlea r15, [rdi+rsi*8]\nxor r12d, r12d\nnop dword ptr [rax+00000000h]\nloc_1570:\nmov rbp, [rbx]\nmov rsi, r13\nmov rdi, rbp\ncall sub_1470\ntest eax, eax\njz short loc_158D\nmovsxd rax, r12d\nadd r12d, 1\nmov [r14+rax*8], rbp\nloc_158D:\nadd rbx, 8\ncmp rbx, r15\njnz short loc_1570\nloc_1596:\nadd rsp, 8\nmov eax, r12d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15B0:\nxor r12d, r12d\njmp short loc_1596", + "ida_strip_pseudo": "__int64 __fastcall sub_1540(_QWORD *a1, int a2, __int64 a3, __int64 a4)\n{\n _QWORD *v6; // rbx\n unsigned int v7; // r12d\n __int64 v8; // rbp\n __int64 v9; // rax\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v6 = a1;\n v7 = 0;\n do\n {\n v8 = *v6;\n if ( (unsigned int)sub_1470(*v6, a3) )\n {\n v9 = (int)v7++;\n *(_QWORD *)(a4 + 8 * v9) = v8;\n }\n ++v6;\n }\n while ( v6 != &a1[a2] );\n }\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1540(uint64_t *a1, int a2, long long a3, long long a4) {\n uint64_t *v6;\n unsigned int v7;\n long long v8;\n long long v9;\n if (a2 <= 0) {\n return 0;\n } else {\n v6 = a1;\n v7 = 0;\n do {\n v8 = *v6;\n if ((unsigned int)sub_1470(*v6, a3)) {\n v9 = (int)v7++;\n *(uint64_t *)(a4 + 8 * v9) = v8;\n }\n ++v6;\n } while (v6 != &a1[a2]);\n }\n return v7;\n}", + "ida_pseudo_norm": "long long func0(uint64_t *a1, int a2, long long a3, long long a4) {\n uint64_t *v6;\n unsigned int v7;\n long long v8;\n long long v9;\n if (a2 <= 0) {\n return 0;\n } else {\n v6 = a1;\n v7 = 0;\n do {\n v8 = *v6;\n if ((unsigned int)is_anagram(*v6, a3)) {\n v9 = (int)v7++;\n *(uint64_t *)(a4 + 8 * v9) = v8;\n }\n ++v6;\n } while (v6 != &a1[a2]);\n }\n return v7;\n}" + }, + { + "index": 861, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\nint is_anagram(const char *str1, const char *str2) {\n\n int count1[256] = {0};\n\n int count2[256] = {0};\n\n while (*str1) {\n\n count1[(unsigned char)*str1++]++;\n\n }\n\n while (*str2) {\n\n count2[(unsigned char)*str2++]++;\n\n }\n\n for(int i=0;i<256;i++) {\n\n if(count1[i] != count2[i])\n\n return 0;\n\n }\n\n return 1;\n\n}\n\n\n\n", + "func": "int func0(char* texts[], int texts_size, char* str, char* result[]) {\n int result_size = 0;\n for (int i = 0; i < texts_size; i++) {\n if (is_anagram(texts[i], str)) {\n result[result_size++] = texts[i];\n }\n }\n return result_size;\n}", + "test": "int main() {\n\n // Test case 1\n\n char* texts1[] = {\"bcda\", \"abce\", \"cbda\", \"cbea\", \"adcb\"};\n\n char* str1 = \"abcd\";\n\n char* expected1[] = {\"bcda\", \"cbda\", \"adcb\"};\n\n char* result1[5];\n\n int size1 = func0(texts1, 5, str1, result1);\n\n assert(size1 == 3);\n\n assert(strcmp(result1[0], expected1[0]) == 0);\n\n assert(strcmp(result1[1], expected1[1]) == 0);\n\n assert(strcmp(result1[2], expected1[2]) == 0);\n\n\n\n // Test case 2\n\n char* texts2[] = {\"recitals\", \" python\"};\n\n char* str2 = \"articles\";\n\n char* expected2[] = {\"recitals\"};\n\n char* result2[2];\n\n int size2 = func0(texts2, 2, str2, result2);\n\n assert(size2 == 1);\n\n assert(strcmp(result2[0], expected2[0]) == 0);\n\n\n\n // Test case 3\n\n char* texts3[] = {\" keep\", \" abcdef\", \" xyz\"};\n\n char* str3 = \" peek\";\n\n char* expected3[] = {\" keep\"};\n\n char* result3[3];\n\n int size3 = func0(texts3, 3, str3, result3);\n\n assert(size3 == 1);\n\n assert(strcmp(result3[0], expected3[0]) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\ntest %esi,%esi\njle 15a0 \nlea -0x1(%rsi),%eax\nmov %rdx,%r13\nmov %rcx,%r14\nmov %rdi,%rbx\nlea 0x8(%rdi,%rax,8),%r15\nxor %r12d,%r12d\nnopw 0x0(%rax,%rax,1)\nmov (%rbx),%rbp\nmov %r13,%rsi\nmov %rbp,%rdi\ncallq 1450 \ntest %eax,%eax\nje 157d \nmovslq %r12d,%rax\nadd $0x1,%r12d\nmov %rbp,(%r14,%rax,8)\nadd $0x8,%rbx\ncmp %r15,%rbx\njne 1560 \nadd $0x8,%rsp\nmov %r12d,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax,%rax,1)\nxor %r12d,%r12d\njmp 1586 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\ntest esi, esi\njle short loc_15B0\nmovsxd rsi, esi\nmov r13, rdx\nmov r14, rcx\nmov rbx, rdi\nlea r15, [rdi+rsi*8]\nxor r12d, r12d\nnop dword ptr [rax+00000000h]\nloc_1570:\nmov rbp, [rbx]\nmov rsi, r13\nmov rdi, rbp\ncall is_anagram\ntest eax, eax\njz short loc_158D\nmovsxd rax, r12d\nadd r12d, 1\nmov [r14+rax*8], rbp\nloc_158D:\nadd rbx, 8\ncmp rbx, r15\njnz short loc_1570\nloc_1596:\nadd rsp, 8\nmov eax, r12d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15B0:\nxor r12d, r12d\njmp short loc_1596", + "ida_pseudo": "__int64 __fastcall func0(_QWORD *a1, int a2, __int64 a3, __int64 a4)\n{\n _QWORD *v6; // rbx\n unsigned int v7; // r12d\n __int64 v8; // rbp\n __int64 v9; // rax\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v6 = a1;\n v7 = 0;\n do\n {\n v8 = *v6;\n if ( (unsigned int)is_anagram(*v6, a3) )\n {\n v9 = (int)v7++;\n *(_QWORD *)(a4 + 8 * v9) = v8;\n }\n ++v6;\n }\n while ( v6 != &a1[a2] );\n }\n return v7;\n}", + "ida_strip_asm": "sub_1540:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\ntest esi, esi\njle short loc_15B0\nmovsxd rsi, esi\nmov r13, rdx\nmov r14, rcx\nmov rbx, rdi\nlea r15, [rdi+rsi*8]\nxor r12d, r12d\nnop dword ptr [rax+00000000h]\nloc_1570:\nmov rbp, [rbx]\nmov rsi, r13\nmov rdi, rbp\ncall sub_1470\ntest eax, eax\njz short loc_158D\nmovsxd rax, r12d\nadd r12d, 1\nmov [r14+rax*8], rbp\nloc_158D:\nadd rbx, 8\ncmp rbx, r15\njnz short loc_1570\nloc_1596:\nadd rsp, 8\nmov eax, r12d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15B0:\nxor r12d, r12d\njmp short loc_1596", + "ida_strip_pseudo": "__int64 __fastcall sub_1540(_QWORD *a1, int a2, __int64 a3, __int64 a4)\n{\n _QWORD *v6; // rbx\n unsigned int v7; // r12d\n __int64 v8; // rbp\n __int64 v9; // rax\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v6 = a1;\n v7 = 0;\n do\n {\n v8 = *v6;\n if ( (unsigned int)sub_1470(*v6, a3) )\n {\n v9 = (int)v7++;\n *(_QWORD *)(a4 + 8 * v9) = v8;\n }\n ++v6;\n }\n while ( v6 != &a1[a2] );\n }\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1540(uint64_t *a1, int a2, long long a3, long long a4) {\n uint64_t *v6;\n unsigned int v7;\n long long v8;\n long long v9;\n if (a2 <= 0) {\n return 0;\n } else {\n v6 = a1;\n v7 = 0;\n do {\n v8 = *v6;\n if ((unsigned int)sub_1470(*v6, a3)) {\n v9 = (int)v7++;\n *(uint64_t *)(a4 + 8 * v9) = v8;\n }\n ++v6;\n } while (v6 != &a1[a2]);\n }\n return v7;\n}", + "ida_pseudo_norm": "long long func0(uint64_t *a1, int a2, long long a3, long long a4) {\n uint64_t *v6;\n unsigned int v7;\n long long v8;\n long long v9;\n if (a2 <= 0) {\n return 0;\n } else {\n v6 = a1;\n v7 = 0;\n do {\n v8 = *v6;\n if ((unsigned int)is_anagram(*v6, a3)) {\n v9 = (int)v7++;\n *(uint64_t *)(a4 + 8 * v9) = v8;\n }\n ++v6;\n } while (v6 != &a1[a2]);\n }\n return v7;\n}" + }, + { + "index": 862, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char *word;\n\n int frequency;\n\n} WordFreq;\n\n\n\nint compare(const void *a, const void *b) {\n\n WordFreq *wordFreq1 = (WordFreq *)a;\n\n WordFreq *wordFreq2 = (WordFreq *)b;\n\n return wordFreq2->frequency - wordFreq1->frequency;\n\n}\n\n\n\n", + "func": "WordFreq *func0(char *text, int n, int *returnSize) {\n char *token;\n int size = 0, capacity = 10;\n WordFreq *freqs = (WordFreq *)malloc(capacity * sizeof(WordFreq));\n char *text_copy = strdup(text);\n for (token = strtok(text_copy, \" ,.-\"); token != NULL;\n token = strtok(NULL, \" ,.-\")) {\n int found = 0;\n for (int i = 0; i < size; ++i) {\n if (strcmp(freqs[i].word, token) == 0) {\n freqs[i].frequency++;\n found = 1;\n break;\n }\n }\n if (!found) {\n if (size >= capacity) {\n capacity *= 2;\n freqs = realloc(freqs, capacity * sizeof(WordFreq));\n }\n freqs[size].word = strdup(token);\n freqs[size].frequency = 1;\n size++;\n }\n }\n free(text_copy);\n qsort(freqs, size, sizeof(WordFreq), compare);\n *returnSize = n > size ? size : n;\n return freqs;\n}", + "test": "int main() {\n\n int size;\n\n WordFreq *result;\n\n \n\n result = func0(\"python is a programming language\", 1, &size);\n\n assert(size == 1 && strcmp(result[0].word, \"python\") == 0 && result[0].frequency == 1);\n\n free(result);\n\n\n\n result = func0(\"python is a programming language\", 2, &size);\n\n assert(size == 2 && strcmp(result[0].word, \"python\") == 0 && result[0].frequency == 1);\n\n free(result);\n\n\n\n result = func0(\"python is a programming language\", 5, &size);\n\n assert(size == 5 && strcmp(result[0].word, \"python\") == 0 && result[0].frequency == 1);\n\n for(int i = 0; i < size; i++) {\n\n free(result[i].word);\n\n }\n\n free(result);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x58,%rsp\nmov %rdi,-0x48(%rbp)\nmov %esi,-0x4c(%rbp)\nmov %rdx,-0x58(%rbp)\nmovl $0x0,-0x38(%rbp)\nmovl $0xa,-0x34(%rbp)\nmov -0x34(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdi\ncallq 1120 \nmov %rax,-0x20(%rbp)\nmov -0x48(%rbp),%rax\nmov %rax,%rdi\ncallq 1150 \nmov %rax,-0x18(%rbp)\nmov -0x18(%rbp),%rax\nlea 0xd35(%rip),%rsi\nmov %rax,%rdi\ncallq 1140 \nmov %rax,-0x28(%rbp)\njmpq 13d4 \nmovl $0x0,-0x30(%rbp)\nmovl $0x0,-0x2c(%rbp)\njmp 1346 \nmov -0x2c(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0x28(%rbp),%rdx\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1110 \ntest %eax,%eax\njne 1342 \nmov -0x2c(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov 0x8(%rax),%edx\nadd $0x1,%edx\nmov %edx,0x8(%rax)\nmovl $0x1,-0x30(%rbp)\njmp 134e \naddl $0x1,-0x2c(%rbp)\nmov -0x2c(%rbp),%eax\ncmp -0x38(%rbp),%eax\njl 12f4 \ncmpl $0x0,-0x30(%rbp)\njne 13bf \nmov -0x38(%rbp),%eax\ncmp -0x34(%rbp),%eax\njl 137e \nshll -0x34(%rbp)\nmov -0x34(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x20(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1130 \nmov %rax,-0x20(%rbp)\nmov -0x38(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x20(%rbp),%rax\nlea (%rdx,%rax,1),%rbx\nmov -0x28(%rbp),%rax\nmov %rax,%rdi\ncallq 1150 \nmov %rax,(%rbx)\nmov -0x38(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmovl $0x1,0x8(%rax)\naddl $0x1,-0x38(%rbp)\nlea 0xc42(%rip),%rsi\nmov $0x0,%edi\ncallq 1140 \nmov %rax,-0x28(%rbp)\ncmpq $0x0,-0x28(%rbp)\njne 12e4 \nmov -0x18(%rbp),%rax\nmov %rax,%rdi\ncallq 10d0 \nmov -0x38(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x20(%rbp),%rax\nlea -0x1b3(%rip),%rcx\nmov $0x10,%edx\nmov %rax,%rdi\ncallq 10e0 \nmov -0x38(%rbp),%eax\ncmp %eax,-0x4c(%rbp)\ncmovle -0x4c(%rbp),%eax\nmov %eax,%edx\nmov -0x58(%rbp),%rax\nmov %edx,(%rax)\nmov -0x20(%rbp),%rax\nadd $0x58,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 58h\nmov [rbp+s], rdi\nmov [rbp+var_4C], esi\nmov [rbp+var_58], rdx\nmov [rbp+var_38], 0\nmov [rbp+var_34], 0Ah\nmov eax, [rbp+var_34]\ncdqe\nshl rax, 4\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strdup\nmov [rbp+var_18], rax\nmov rax, [rbp+var_18]\nlea rdx, delim; \" ,.-\"\nmov rsi, rdx; delim\nmov rdi, rax; s\ncall _strtok\nmov [rbp+s2], rax\njmp loc_13DA\nloc_12E7:\nmov [rbp+var_30], 0\nmov [rbp+var_2C], 0\njmp short loc_1349\nloc_12F7:\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rax, [rax]\nmov rdx, [rbp+s2]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1345\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax+8]\nadd edx, 1\nmov [rax+8], edx\nmov [rbp+var_30], 1\njmp short loc_1351\nloc_1345:\nadd [rbp+var_2C], 1\nloc_1349:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_38]\njl short loc_12F7\nloc_1351:\ncmp [rbp+var_30], 0\njnz short loc_13C2\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_34]\njl short loc_1381\nshl [rbp+var_34], 1\nmov eax, [rbp+var_34]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+ptr]\nmov rsi, rdx; size\nmov rdi, rax; ptr\ncall _realloc\nmov [rbp+ptr], rax\nloc_1381:\nmov eax, [rbp+var_38]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+ptr]\nlea rbx, [rdx+rax]\nmov rax, [rbp+s2]\nmov rdi, rax; s\ncall _strdup\nmov [rbx], rax\nmov eax, [rbp+var_38]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov dword ptr [rax+8], 1\nadd [rbp+var_38], 1\nloc_13C2:\nlea rax, delim; \" ,.-\"\nmov rsi, rax; delim\nmov edi, 0; s\ncall _strtok\nmov [rbp+s2], rax\nloc_13DA:\ncmp [rbp+s2], 0\njnz loc_12E7\nmov rax, [rbp+var_18]\nmov rdi, rax; ptr\ncall _free\nmov eax, [rbp+var_38]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+ptr]\nlea rdx, compare\nmov rcx, rdx; compar\nmov edx, 10h; size\nmov rdi, rax; base\ncall _qsort\nmov edx, [rbp+var_4C]\nmov eax, [rbp+var_38]\ncmp edx, eax\ncmovg edx, eax\nmov rax, [rbp+var_58]\nmov [rax], edx\nmov rax, [rbp+ptr]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(const char *a1, int a2, int *a3)\n{\n int v3; // edx\n int v6; // [rsp+28h] [rbp-38h]\n int v7; // [rsp+2Ch] [rbp-34h]\n int v8; // [rsp+30h] [rbp-30h]\n int i; // [rsp+34h] [rbp-2Ch]\n const char *s2; // [rsp+38h] [rbp-28h]\n _DWORD *ptr; // [rsp+40h] [rbp-20h]\n char *v12; // [rsp+48h] [rbp-18h]\n\n v6 = 0;\n v7 = 10;\n ptr = malloc(0xA0uLL);\n v12 = strdup(a1);\n for ( s2 = strtok(v12, \" ,.-\"); s2; s2 = strtok(0LL, \" ,.-\") )\n {\n v8 = 0;\n for ( i = 0; i < v6; ++i )\n {\n if ( !strcmp(*(const char **)&ptr[4 * i], s2) )\n {\n ++ptr[4 * i + 2];\n v8 = 1;\n break;\n }\n }\n if ( !v8 )\n {\n if ( v6 >= v7 )\n {\n v7 *= 2;\n ptr = realloc(ptr, 16LL * v7);\n }\n *(_QWORD *)&ptr[4 * v6] = strdup(s2);\n ptr[4 * v6++ + 2] = 1;\n }\n }\n free(v12);\n qsort(ptr, v6, 0x10uLL, compare);\n v3 = a2;\n if ( a2 > v6 )\n v3 = v6;\n *a3 = v3;\n return ptr;\n}", + "ida_strip_asm": "sub_127D:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 58h\nmov [rbp+s], rdi\nmov [rbp+var_4C], esi\nmov [rbp+var_58], rdx\nmov [rbp+var_38], 0\nmov [rbp+var_34], 0Ah\nmov eax, [rbp+var_34]\ncdqe\nshl rax, 4\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strdup\nmov [rbp+var_18], rax\nmov rax, [rbp+var_18]\nlea rdx, delim; \" ,.-\"\nmov rsi, rdx; delim\nmov rdi, rax; s\ncall _strtok\nmov [rbp+s2], rax\njmp loc_13DA\nloc_12E7:\nmov [rbp+var_30], 0\nmov [rbp+var_2C], 0\njmp short loc_1349\nloc_12F7:\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov rax, [rax]\nmov rdx, [rbp+s2]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1345\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax+8]\nadd edx, 1\nmov [rax+8], edx\nmov [rbp+var_30], 1\njmp short loc_1351\nloc_1345:\nadd [rbp+var_2C], 1\nloc_1349:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_38]\njl short loc_12F7\nloc_1351:\ncmp [rbp+var_30], 0\njnz short loc_13C2\nmov eax, [rbp+var_38]\ncmp eax, [rbp+var_34]\njl short loc_1381\nshl [rbp+var_34], 1\nmov eax, [rbp+var_34]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+ptr]\nmov rsi, rdx; size\nmov rdi, rax; ptr\ncall _realloc\nmov [rbp+ptr], rax\nloc_1381:\nmov eax, [rbp+var_38]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+ptr]\nlea rbx, [rdx+rax]\nmov rax, [rbp+s2]\nmov rdi, rax; s\ncall _strdup\nmov [rbx], rax\nmov eax, [rbp+var_38]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov dword ptr [rax+8], 1\nadd [rbp+var_38], 1\nloc_13C2:\nlea rax, delim; \" ,.-\"\nmov rsi, rax; delim\nmov edi, 0; s\ncall _strtok\nmov [rbp+s2], rax\nloc_13DA:\ncmp [rbp+s2], 0\njnz loc_12E7\nmov rax, [rbp+var_18]\nmov rdi, rax; ptr\ncall _free\nmov eax, [rbp+var_38]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+ptr]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 10h; size\nmov rdi, rax; base\ncall _qsort\nmov edx, [rbp+var_4C]\nmov eax, [rbp+var_38]\ncmp edx, eax\ncmovg edx, eax\nmov rax, [rbp+var_58]\nmov [rax], edx\nmov rax, [rbp+ptr]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_127D(const char *a1, int a2, int *a3)\n{\n int v3; // edx\n int v6; // [rsp+28h] [rbp-38h]\n int v7; // [rsp+2Ch] [rbp-34h]\n int v8; // [rsp+30h] [rbp-30h]\n int i; // [rsp+34h] [rbp-2Ch]\n const char *s2; // [rsp+38h] [rbp-28h]\n _DWORD *ptr; // [rsp+40h] [rbp-20h]\n char *v12; // [rsp+48h] [rbp-18h]\n\n v6 = 0;\n v7 = 10;\n ptr = malloc(0xA0uLL);\n v12 = strdup(a1);\n for ( s2 = strtok(v12, \" ,.-\"); s2; s2 = strtok(0LL, \" ,.-\") )\n {\n v8 = 0;\n for ( i = 0; i < v6; ++i )\n {\n if ( !strcmp(*(const char **)&ptr[4 * i], s2) )\n {\n ++ptr[4 * i + 2];\n v8 = 1;\n break;\n }\n }\n if ( !v8 )\n {\n if ( v6 >= v7 )\n {\n v7 *= 2;\n ptr = realloc(ptr, 16LL * v7);\n }\n *(_QWORD *)&ptr[4 * v6] = strdup(s2);\n ptr[4 * v6++ + 2] = 1;\n }\n }\n free(v12);\n qsort(ptr, v6, 0x10uLL, compar);\n v3 = a2;\n if ( a2 > v6 )\n v3 = v6;\n *a3 = v3;\n return ptr;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_127D(const char *a1, int a2, int *a3) {\n int v3;\n int v6;\n int v7;\n int v8;\n int i;\n const char *s2;\n uint32_t *ptr;\n char *v12;\n v6 = 0;\n v7 = 10;\n ptr = malloc(160uLL);\n v12 = strdup(a1);\n for (s2 = strtok(v12, \" ,.-\"); s2; s2 = strtok(0LL, \" ,.-\")) {\n v8 = 0;\n for (i = 0; i < v6; ++i) {\n if (!strcmp(*(const char **)&ptr[4 * i], s2)) {\n ++ptr[4 * i + 2];\n v8 = 1;\n break;\n }\n }\n if (!v8) {\n if (v6 >= v7) {\n v7 *= 2;\n ptr = realloc(ptr, 16LL * v7);\n }\n *(uint64_t *)&ptr[4 * v6] = strdup(s2);\n ptr[4 * v6++ + 2] = 1;\n }\n }\n free(v12);\n qsort(ptr, v6, 16uLL, compar);\n v3 = a2;\n if (a2 > v6) v3 = v6;\n *a3 = v3;\n return ptr;\n}", + "ida_pseudo_norm": "uint32_t *func0(const char *a1, int a2, int *a3) {\n int v3;\n int v6;\n int v7;\n int v8;\n int i;\n const char *s2;\n uint32_t *ptr;\n char *v12;\n v6 = 0;\n v7 = 10;\n ptr = malloc(160uLL);\n v12 = strdup(a1);\n for (s2 = strtok(v12, \" ,.-\"); s2; s2 = strtok(0LL, \" ,.-\")) {\n v8 = 0;\n for (i = 0; i < v6; ++i) {\n if (!strcmp(*(const char **)&ptr[4 * i], s2)) {\n ++ptr[4 * i + 2];\n v8 = 1;\n break;\n }\n }\n if (!v8) {\n if (v6 >= v7) {\n v7 *= 2;\n ptr = realloc(ptr, 16LL * v7);\n }\n *(uint64_t *)&ptr[4 * v6] = strdup(s2);\n ptr[4 * v6++ + 2] = 1;\n }\n }\n free(v12);\n qsort(ptr, v6, 16uLL, compare);\n v3 = a2;\n if (a2 > v6) v3 = v6;\n *a3 = v3;\n return ptr;\n}" + }, + { + "index": 862, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char *word;\n\n int frequency;\n\n} WordFreq;\n\n\n\nint compare(const void *a, const void *b) {\n\n WordFreq *wordFreq1 = (WordFreq *)a;\n\n WordFreq *wordFreq2 = (WordFreq *)b;\n\n return wordFreq2->frequency - wordFreq1->frequency;\n\n}\n\n\n\n", + "func": "WordFreq *func0(char *text, int n, int *returnSize) {\n char *token;\n int size = 0, capacity = 10;\n WordFreq *freqs = (WordFreq *)malloc(capacity * sizeof(WordFreq));\n char *text_copy = strdup(text);\n for (token = strtok(text_copy, \" ,.-\"); token != NULL;\n token = strtok(NULL, \" ,.-\")) {\n int found = 0;\n for (int i = 0; i < size; ++i) {\n if (strcmp(freqs[i].word, token) == 0) {\n freqs[i].frequency++;\n found = 1;\n break;\n }\n }\n if (!found) {\n if (size >= capacity) {\n capacity *= 2;\n freqs = realloc(freqs, capacity * sizeof(WordFreq));\n }\n freqs[size].word = strdup(token);\n freqs[size].frequency = 1;\n size++;\n }\n }\n free(text_copy);\n qsort(freqs, size, sizeof(WordFreq), compare);\n *returnSize = n > size ? size : n;\n return freqs;\n}", + "test": "int main() {\n\n int size;\n\n WordFreq *result;\n\n \n\n result = func0(\"python is a programming language\", 1, &size);\n\n assert(size == 1 && strcmp(result[0].word, \"python\") == 0 && result[0].frequency == 1);\n\n free(result);\n\n\n\n result = func0(\"python is a programming language\", 2, &size);\n\n assert(size == 2 && strcmp(result[0].word, \"python\") == 0 && result[0].frequency == 1);\n\n free(result);\n\n\n\n result = func0(\"python is a programming language\", 5, &size);\n\n assert(size == 5 && strcmp(result[0].word, \"python\") == 0 && result[0].frequency == 1);\n\n for(int i = 0; i < size; i++) {\n\n free(result[i].word);\n\n }\n\n free(result);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x28,%rsp\nmov %rdi,%rbx\nmov %esi,0x14(%rsp)\nmov %rdx,0x18(%rsp)\nmov $0xa0,%edi\ncallq 1120 \nmov %rax,%r15\nmov %rbx,%rdi\ncallq 1150 \nmov %rax,0x8(%rsp)\nlea 0xd71(%rip),%rsi\nmov %rax,%rdi\ncallq 1140 \nmov %rax,%rbp\nmovl $0xa,0x10(%rsp)\nmov $0x0,%r14d\ntest %rax,%rax\njne 133e \nmov 0x8(%rsp),%rdi\ncallq 10d0 \nmovslq %r14d,%rsi\nlea -0x80(%rip),%rcx\nmov $0x10,%edx\nmov %r15,%rdi\ncallq 10e0 \nmov 0x14(%rsp),%eax\ncmp %r14d,%eax\ncmovle %eax,%r14d\nmov 0x18(%rsp),%rax\nmov %r14d,(%rax)\nmov %r15,%rax\nadd $0x28,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\naddl $0x1,0x8(%rbx)\njmp 1321 \nmovslq %r14d,%rbx\nshl $0x4,%rbx\nadd %r15,%rbx\nmov %rbp,%rdi\ncallq 1150 \nmov %rax,(%rbx)\nmovl $0x1,0x8(%rbx)\nadd $0x1,%r14d\nlea 0xcdc(%rip),%rsi\nmov $0x0,%edi\ncallq 1140 \nmov %rax,%rbp\ntest %rax,%rax\nje 12b5 \ntest %r14d,%r14d\njle 136b \nmov %r15,%rbx\nlea -0x1(%r14),%eax\nshl $0x4,%rax\nlea 0x10(%r15,%rax,1),%r13\nmov %rbp,%rsi\nmov (%rbx),%rdi\ncallq 1110 \ntest %eax,%eax\nje 12fb \nadd $0x10,%rbx\ncmp %r13,%rbx\njne 1353 \ncmp 0x10(%rsp),%r14d\njl 1301 \nshll 0x10(%rsp)\nmov 0x10(%rsp),%eax\nmovslq %eax,%rsi\nshl $0x4,%rsi\nmov %r15,%rdi\ncallq 1130 \nmov %rax,%r15\njmpq 1301 \n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov rbx, rdi\nmov [rsp+58h+var_44], esi\nmov [rsp+58h+var_40], rdx\nmov edi, 0A0h; size\ncall _malloc\nmov r14, rax\nmov rdi, rbx; s\ncall _strdup\nmov [rsp+58h+ptr], rax\nlea rsi, delim; \" ,.-\"\nmov rdi, rax; s\ncall _strtok\nmov rbp, rax\nmov r15d, 0Ah\nmov r13d, 0\ntest rax, rax\njnz loc_133B\nloc_12B3:\nmov rdi, [rsp+58h+ptr]; ptr\ncall _free\nmovsxd rsi, r13d; nmemb\nlea rcx, compare; compar\nmov edx, 10h; size\nmov rdi, r14; base\ncall _qsort\nmov eax, [rsp+58h+var_44]\ncmp eax, r13d\ncmovg eax, r13d\nmov rcx, [rsp+58h+var_40]\nmov [rcx], eax\nmov rax, r14\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_12F8:\nadd dword ptr [rbx+8], 1\njmp short loc_131E\nloc_12FE:\nmovsxd rbx, r13d\nshl rbx, 4\nadd rbx, r14\nmov rdi, rbp; s\ncall _strdup\nmov [rbx], rax\nmov dword ptr [rbx+8], 1\nadd r13d, 1\nloc_131E:\nlea rsi, delim; \" ,.-\"\nmov edi, 0; s\ncall _strtok\nmov rbp, rax\ntest rax, rax\njz loc_12B3\nloc_133B:\ntest r13d, r13d\njle short loc_1365\nmov rbx, r14\nmovsxd r12, r13d\nshl r12, 4\nadd r12, r14\nloc_134D:\nmov rdi, [rbx]; s1\nmov rsi, rbp; s2\ncall _strcmp\ntest eax, eax\njz short loc_12F8\nadd rbx, 10h\ncmp rbx, r12\njnz short loc_134D\nloc_1365:\ncmp r13d, r15d\njl short loc_12FE\nadd r15d, r15d\nmovsxd rsi, r15d\nshl rsi, 4; size\nmov rdi, r14; ptr\ncall _realloc\nmov r14, rax\njmp loc_12FE", + "ida_pseudo": "char *__fastcall func0(char *s, int a2, int *a3)\n{\n char *v3; // r14\n char *v4; // rbp\n int v5; // r15d\n int i; // r13d\n int v7; // eax\n char *v9; // rbx\n const char **v10; // rbx\n char *ptr; // [rsp+8h] [rbp-50h]\n\n v3 = (char *)malloc(0xA0uLL);\n ptr = strdup(s);\n v4 = strtok(ptr, \" ,.-\");\n v5 = 10;\n for ( i = 0; v4; v4 = strtok(0LL, \" ,.-\") )\n {\n if ( i <= 0 )\n {\nLABEL_12:\n if ( i >= v5 )\n {\n v5 *= 2;\n v3 = (char *)realloc(v3, 16LL * v5);\n }\n v9 = &v3[16 * i];\n *(_QWORD *)v9 = strdup(v4);\n *((_DWORD *)v9 + 2) = 1;\n ++i;\n }\n else\n {\n v10 = (const char **)v3;\n while ( strcmp(*v10, v4) )\n {\n v10 += 2;\n if ( v10 == (const char **)&v3[16 * i] )\n goto LABEL_12;\n }\n ++*((_DWORD *)v10 + 2);\n }\n }\n free(ptr);\n qsort(v3, i, 0x10uLL, compare);\n v7 = a2;\n if ( a2 > i )\n v7 = i;\n *a3 = v7;\n return v3;\n}", + "ida_strip_asm": "sub_1254:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov rbx, rdi\nmov [rsp+58h+var_44], esi\nmov [rsp+58h+var_40], rdx\nmov edi, 0A0h; size\ncall _malloc\nmov r14, rax\nmov rdi, rbx; s\ncall _strdup\nmov [rsp+58h+ptr], rax\nlea rsi, delim; \" ,.-\"\nmov rdi, rax; s\ncall _strtok\nmov rbp, rax\nmov r15d, 0Ah\nmov r13d, 0\ntest rax, rax\njnz loc_133B\nloc_12B3:\nmov rdi, [rsp+58h+ptr]; ptr\ncall _free\nmovsxd rsi, r13d; nmemb\nlea rcx, compar; compar\nmov edx, 10h; size\nmov rdi, r14; base\ncall _qsort\nmov eax, [rsp+58h+var_44]\ncmp eax, r13d\ncmovg eax, r13d\nmov rcx, [rsp+58h+var_40]\nmov [rcx], eax\nmov rax, r14\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_12F8:\nadd dword ptr [rbx+8], 1\njmp short loc_131E\nloc_12FE:\nmovsxd rbx, r13d\nshl rbx, 4\nadd rbx, r14\nmov rdi, rbp; s\ncall _strdup\nmov [rbx], rax\nmov dword ptr [rbx+8], 1\nadd r13d, 1\nloc_131E:\nlea rsi, delim; \" ,.-\"\nmov edi, 0; s\ncall _strtok\nmov rbp, rax\ntest rax, rax\njz loc_12B3\nloc_133B:\ntest r13d, r13d\njle short loc_1365\nmov rbx, r14\nmovsxd r12, r13d\nshl r12, 4\nadd r12, r14\nloc_134D:\nmov rdi, [rbx]; s1\nmov rsi, rbp; s2\ncall _strcmp\ntest eax, eax\njz short loc_12F8\nadd rbx, 10h\ncmp rbx, r12\njnz short loc_134D\nloc_1365:\ncmp r13d, r15d\njl short loc_12FE\nadd r15d, r15d\nmovsxd rsi, r15d\nshl rsi, 4; size\nmov rdi, r14; ptr\ncall _realloc\nmov r14, rax\njmp loc_12FE", + "ida_strip_pseudo": "char *__fastcall sub_1254(char *s, int a2, int *a3)\n{\n char *v3; // r14\n char *v4; // rbp\n int v5; // r15d\n int i; // r13d\n int v7; // eax\n char *v9; // rbx\n const char **v10; // rbx\n char *ptr; // [rsp+8h] [rbp-50h]\n\n v3 = (char *)malloc(0xA0uLL);\n ptr = strdup(s);\n v4 = strtok(ptr, \" ,.-\");\n v5 = 10;\n for ( i = 0; v4; v4 = strtok(0LL, \" ,.-\") )\n {\n if ( i <= 0 )\n {\nLABEL_12:\n if ( i >= v5 )\n {\n v5 *= 2;\n v3 = (char *)realloc(v3, 16LL * v5);\n }\n v9 = &v3[16 * i];\n *(_QWORD *)v9 = strdup(v4);\n *((_DWORD *)v9 + 2) = 1;\n ++i;\n }\n else\n {\n v10 = (const char **)v3;\n while ( strcmp(*v10, v4) )\n {\n v10 += 2;\n if ( v10 == (const char **)&v3[16 * i] )\n goto LABEL_12;\n }\n ++*((_DWORD *)v10 + 2);\n }\n }\n free(ptr);\n qsort(v3, i, 0x10uLL, compar);\n v7 = a2;\n if ( a2 > i )\n v7 = i;\n *a3 = v7;\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1254(char *s, int a2, int *a3) {\n char *v3;\n char *v4;\n int v5;\n int i;\n int v7;\n char *v9;\n const char **v10;\n char *ptr;\n v3 = (char *)malloc(160uLL);\n ptr = strdup(s);\n v4 = strtok(ptr, \" ,.-\");\n v5 = 10;\n for (i = 0; v4; v4 = strtok(0LL, \" ,.-\")) {\n if (i <= 0) {\n LABEL_12:\n if (i >= v5) {\n v5 *= 2;\n v3 = (char *)realloc(v3, 16LL * v5);\n }\n v9 = &v3[16 * i];\n *(uint64_t *)v9 = strdup(v4);\n *((uint32_t *)v9 + 2) = 1;\n ++i;\n } else {\n v10 = (const char **)v3;\n while (strcmp(*v10, v4)) {\n v10 += 2;\n if (v10 == (const char **)&v3[16 * i]) goto LABEL_12;\n }\n ++*((uint32_t *)v10 + 2);\n }\n }\n free(ptr);\n qsort(v3, i, 16uLL, compar);\n v7 = a2;\n if (a2 > i) v7 = i;\n *a3 = v7;\n return v3;\n}", + "ida_pseudo_norm": "char *func0(char *s, int a2, int *a3) {\n char *v3;\n char *v4;\n int v5;\n int i;\n int v7;\n char *v9;\n const char **v10;\n char *ptr;\n v3 = (char *)malloc(160uLL);\n ptr = strdup(s);\n v4 = strtok(ptr, \" ,.-\");\n v5 = 10;\n for (i = 0; v4; v4 = strtok(0LL, \" ,.-\")) {\n if (i <= 0) {\n LABEL_12:\n if (i >= v5) {\n v5 *= 2;\n v3 = (char *)realloc(v3, 16LL * v5);\n }\n v9 = &v3[16 * i];\n *(uint64_t *)v9 = strdup(v4);\n *((uint32_t *)v9 + 2) = 1;\n ++i;\n } else {\n v10 = (const char **)v3;\n while (strcmp(*v10, v4)) {\n v10 += 2;\n if (v10 == (const char **)&v3[16 * i]) goto LABEL_12;\n }\n ++*((uint32_t *)v10 + 2);\n }\n }\n free(ptr);\n qsort(v3, i, 16uLL, compare);\n v7 = a2;\n if (a2 > i) v7 = i;\n *a3 = v7;\n return v3;\n}" + }, + { + "index": 862, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char *word;\n\n int frequency;\n\n} WordFreq;\n\n\n\nint compare(const void *a, const void *b) {\n\n WordFreq *wordFreq1 = (WordFreq *)a;\n\n WordFreq *wordFreq2 = (WordFreq *)b;\n\n return wordFreq2->frequency - wordFreq1->frequency;\n\n}\n\n\n\n", + "func": "WordFreq *func0(char *text, int n, int *returnSize) {\n char *token;\n int size = 0, capacity = 10;\n WordFreq *freqs = (WordFreq *)malloc(capacity * sizeof(WordFreq));\n char *text_copy = strdup(text);\n for (token = strtok(text_copy, \" ,.-\"); token != NULL;\n token = strtok(NULL, \" ,.-\")) {\n int found = 0;\n for (int i = 0; i < size; ++i) {\n if (strcmp(freqs[i].word, token) == 0) {\n freqs[i].frequency++;\n found = 1;\n break;\n }\n }\n if (!found) {\n if (size >= capacity) {\n capacity *= 2;\n freqs = realloc(freqs, capacity * sizeof(WordFreq));\n }\n freqs[size].word = strdup(token);\n freqs[size].frequency = 1;\n size++;\n }\n }\n free(text_copy);\n qsort(freqs, size, sizeof(WordFreq), compare);\n *returnSize = n > size ? size : n;\n return freqs;\n}", + "test": "int main() {\n\n int size;\n\n WordFreq *result;\n\n \n\n result = func0(\"python is a programming language\", 1, &size);\n\n assert(size == 1 && strcmp(result[0].word, \"python\") == 0 && result[0].frequency == 1);\n\n free(result);\n\n\n\n result = func0(\"python is a programming language\", 2, &size);\n\n assert(size == 2 && strcmp(result[0].word, \"python\") == 0 && result[0].frequency == 1);\n\n free(result);\n\n\n\n result = func0(\"python is a programming language\", 5, &size);\n\n assert(size == 5 && strcmp(result[0].word, \"python\") == 0 && result[0].frequency == 1);\n\n for(int i = 0; i < size; i++) {\n\n free(result[i].word);\n\n }\n\n free(result);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\nxor %r13d,%r13d\npush %r12\npush %rbp\nmov %rdi,%rbp\nmov $0xa0,%edi\npush %rbx\nsub $0x28,%rsp\nmov %esi,0x14(%rsp)\nmov %rdx,0x18(%rsp)\ncallq 1120 \nmov %rbp,%rdi\nxor %ebp,%ebp\nmov %rax,%r12\ncallq 1150 \nlea 0xba5(%rip),%rsi\nmov %rax,%rdi\nmov %rax,0x8(%rsp)\ncallq 1140 \nmovl $0xa,0x10(%rsp)\ntest %rax,%rax\nje 14da \nmov %rax,%r15\nlea 0xb81(%rip),%r13\nnopl 0x0(%rax,%rax,1)\ntest %ebp,%ebp\nje 153e \nlea -0x1(%rbp),%eax\nmov %r12,%r14\nshl $0x4,%rax\nlea 0x10(%r12,%rax,1),%rbx\njmp 14b1 \nnopl 0x0(%rax)\nadd $0x10,%r14\ncmp %rbx,%r14\nje 1520 \nmov (%r14),%rdi\nmov %r15,%rsi\ncallq 1110 \ntest %eax,%eax\njne 14a8 \naddl $0x1,0x8(%r14)\nmov %r13,%rsi\nxor %edi,%edi\ncallq 1140 \nmov %rax,%r15\ntest %rax,%rax\njne 1488 \nmovslq %ebp,%r13\nmov 0x8(%rsp),%rdi\ncallq 10d0 \nmov %r13,%rsi\nmov %r12,%rdi\nmov $0x10,%edx\nlea -0xe6(%rip),%rcx\ncallq 10e0 \nmov 0x14(%rsp),%eax\ncmp %ebp,%eax\ncmovle %eax,%ebp\nmov 0x18(%rsp),%rax\nmov %ebp,(%rax)\nadd $0x28,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl (%rax)\ncmp %ebp,0x10(%rsp)\njg 153e \nshll 0x10(%rsp)\nmovslq 0x10(%rsp),%rsi\nmov %r12,%rdi\nshl $0x4,%rsi\ncallq 1130 \nmov %rax,%r12\nmovslq %ebp,%rbx\nmov %r15,%rdi\nadd $0x1,%ebp\ncallq 1150 \nshl $0x4,%rbx\nadd %r12,%rbx\nmov %rax,(%rbx)\nmovl $0x1,0x8(%rbx)\njmpq 14c5 \nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nxor r14d, r14d\npush r13\npush r12\nxor r12d, r12d\npush rbp\npush rbx\nmov rbx, rdi\nmov edi, 0A0h; size\nsub rsp, 28h\nmov [rsp+58h+var_44], esi\nmov [rsp+58h+var_40], rdx\ncall _malloc\nmov rdi, rbx; s\nmov r13, rax\ncall _strdup\nlea rsi, delim; \" ,.-\"\nmov rdi, rax; s\nmov [rsp+58h+ptr], rax\ncall _strtok\nmov [rsp+58h+var_48], 0Ah\nmov rbx, rax\ntest rax, rax\njz short loc_149B\nnop dword ptr [rax]\nloc_1450:\nmov rbp, r12\nmov r15, r13\nshl rbp, 4\nadd rbp, r13\ntest r14d, r14d\njg short loc_1471\njmp short loc_14E0\nloc_1468:\nadd r15, 10h\ncmp r15, rbp\njz short loc_14E0\nloc_1471:\nmov rdi, [r15]; s1\nmov rsi, rbx; s2\ncall _strcmp\ntest eax, eax\njnz short loc_1468\nadd dword ptr [r15+8], 1\nloc_1485:\nlea rsi, delim; \" ,.-\"\nxor edi, edi; s\ncall _strtok\nmov rbx, rax\ntest rax, rax\njnz short loc_1450\nloc_149B:\nmov rdi, [rsp+58h+ptr]; ptr\ncall _free\nmov rsi, r12; nmemb\nmov rdi, r13; base\nmov edx, 10h; size\nlea rcx, compare; compar\ncall _qsort\nmov eax, [rsp+58h+var_44]\nmov rcx, [rsp+58h+var_40]\ncmp eax, r14d\ncmovg eax, r14d\nmov [rcx], eax\nadd rsp, 28h\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14E0:\nmov eax, [rsp+58h+var_48]\ncmp r14d, eax\njge short loc_1518\nloc_14E9:\nshl r12, 4\nmov rdi, rbx; s\nadd r14d, 1\ncall _strdup\nadd r12, r13\nmov [r12], rax\nmov dword ptr [r12+8], 1\nmovsxd r12, r14d\njmp loc_1485\nloc_1518:\nshl [rsp+58h+var_48], 1\nmovsxd rsi, [rsp+58h+var_48]\nmov rdi, r13; ptr\nshl rsi, 4; size\ncall _realloc\nmov r13, rax\njmp short loc_14E9", + "ida_pseudo": "const char **__fastcall func0(char *s, int a2, int *a3)\n{\n int v3; // r14d\n size_t v4; // r12\n const char **v5; // r13\n char *i; // rbx\n const char **v7; // r15\n int v8; // eax\n char *v10; // r12\n char *ptr; // [rsp+8h] [rbp-50h]\n int v12; // [rsp+10h] [rbp-48h]\n\n v3 = 0;\n v4 = 0LL;\n v5 = (const char **)malloc(0xA0uLL);\n ptr = strdup(s);\n v12 = 10;\n for ( i = strtok(ptr, \" ,.-\"); i; i = strtok(0LL, \" ,.-\") )\n {\n v7 = v5;\n if ( v3 > 0 )\n {\n while ( strcmp(*v7, i) )\n {\n v7 += 2;\n if ( v7 == &v5[2 * v4] )\n goto LABEL_11;\n }\n ++*((_DWORD *)v7 + 2);\n }\n else\n {\nLABEL_11:\n if ( v3 >= v12 )\n {\n v12 *= 2;\n v5 = (const char **)realloc(v5, 16LL * v12);\n }\n ++v3;\n v10 = (char *)&v5[2 * v4];\n *(_QWORD *)v10 = strdup(i);\n *((_DWORD *)v10 + 2) = 1;\n v4 = v3;\n }\n }\n free(ptr);\n qsort(v5, v4, 0x10uLL, compare);\n v8 = a2;\n if ( a2 > v3 )\n v8 = v3;\n *a3 = v8;\n return v5;\n}", + "ida_strip_asm": "sub_13F0:\nendbr64\npush r15\npush r14\nxor r14d, r14d\npush r13\npush r12\nxor r12d, r12d\npush rbp\npush rbx\nmov rbx, rdi\nmov edi, 0A0h; size\nsub rsp, 28h\nmov [rsp+58h+var_44], esi\nmov [rsp+58h+var_40], rdx\ncall _malloc\nmov rdi, rbx; s\nmov r13, rax\ncall _strdup\nlea rsi, delim; \" ,.-\"\nmov rdi, rax; s\nmov [rsp+58h+ptr], rax\ncall _strtok\nmov [rsp+58h+var_48], 0Ah\nmov rbx, rax\ntest rax, rax\njz short loc_149B\nnop dword ptr [rax]\nloc_1450:\nmov rbp, r12\nmov r15, r13\nshl rbp, 4\nadd rbp, r13\ntest r14d, r14d\njg short loc_1471\njmp short loc_14E0\nloc_1468:\nadd r15, 10h\ncmp r15, rbp\njz short loc_14E0\nloc_1471:\nmov rdi, [r15]; s1\nmov rsi, rbx; s2\ncall _strcmp\ntest eax, eax\njnz short loc_1468\nadd dword ptr [r15+8], 1\nloc_1485:\nlea rsi, delim; \" ,.-\"\nxor edi, edi; s\ncall _strtok\nmov rbx, rax\ntest rax, rax\njnz short loc_1450\nloc_149B:\nmov rdi, [rsp+58h+ptr]; ptr\ncall _free\nmov rsi, r12; nmemb\nmov rdi, r13; base\nmov edx, 10h; size\nlea rcx, compar; compar\ncall _qsort\nmov eax, [rsp+58h+var_44]\nmov rcx, [rsp+58h+var_40]\ncmp eax, r14d\ncmovg eax, r14d\nmov [rcx], eax\nadd rsp, 28h\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14E0:\nmov eax, [rsp+58h+var_48]\ncmp r14d, eax\njge short loc_1518\nloc_14E9:\nshl r12, 4\nmov rdi, rbx; s\nadd r14d, 1\ncall _strdup\nadd r12, r13\nmov [r12], rax\nmov dword ptr [r12+8], 1\nmovsxd r12, r14d\njmp loc_1485\nloc_1518:\nshl [rsp+58h+var_48], 1\nmovsxd rsi, [rsp+58h+var_48]\nmov rdi, r13; ptr\nshl rsi, 4; size\ncall _realloc\nmov r13, rax\njmp short loc_14E9", + "ida_strip_pseudo": "const char **__fastcall sub_13F0(char *s, int a2, int *a3)\n{\n int v3; // r14d\n size_t v4; // r12\n const char **v5; // r13\n char *i; // rbx\n const char **v7; // r15\n int v8; // eax\n char *v10; // r12\n char *ptr; // [rsp+8h] [rbp-50h]\n int v12; // [rsp+10h] [rbp-48h]\n\n v3 = 0;\n v4 = 0LL;\n v5 = (const char **)malloc(0xA0uLL);\n ptr = strdup(s);\n v12 = 10;\n for ( i = strtok(ptr, \" ,.-\"); i; i = strtok(0LL, \" ,.-\") )\n {\n v7 = v5;\n if ( v3 > 0 )\n {\n while ( strcmp(*v7, i) )\n {\n v7 += 2;\n if ( v7 == &v5[2 * v4] )\n goto LABEL_11;\n }\n ++*((_DWORD *)v7 + 2);\n }\n else\n {\nLABEL_11:\n if ( v3 >= v12 )\n {\n v12 *= 2;\n v5 = (const char **)realloc(v5, 16LL * v12);\n }\n ++v3;\n v10 = (char *)&v5[2 * v4];\n *(_QWORD *)v10 = strdup(i);\n *((_DWORD *)v10 + 2) = 1;\n v4 = v3;\n }\n }\n free(ptr);\n qsort(v5, v4, 0x10uLL, compar);\n v8 = a2;\n if ( a2 > v3 )\n v8 = v3;\n *a3 = v8;\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char **sub_13F0(char *s, int a2, int *a3) {\n int v3;\n unsigned int v4;\n const char **v5;\n char *i;\n const char **v7;\n int v8;\n char *v10;\n char *ptr;\n int v12;\n v3 = 0;\n v4 = 0LL;\n v5 = (const char **)malloc(160uLL);\n ptr = strdup(s);\n v12 = 10;\n for (i = strtok(ptr, \" ,.-\"); i; i = strtok(0LL, \" ,.-\")) {\n v7 = v5;\n if (v3 > 0) {\n while (strcmp(*v7, i)) {\n v7 += 2;\n if (v7 == &v5[2 * v4]) goto LABEL_11;\n }\n ++*((uint32_t *)v7 + 2);\n } else {\n LABEL_11:\n if (v3 >= v12) {\n v12 *= 2;\n v5 = (const char **)realloc(v5, 16LL * v12);\n }\n ++v3;\n v10 = (char *)&v5[2 * v4];\n *(uint64_t *)v10 = strdup(i);\n *((uint32_t *)v10 + 2) = 1;\n v4 = v3;\n }\n }\n free(ptr);\n qsort(v5, v4, 16uLL, compar);\n v8 = a2;\n if (a2 > v3) v8 = v3;\n *a3 = v8;\n return v5;\n}", + "ida_pseudo_norm": "const char **func0(char *s, int a2, int *a3) {\n int v3;\n unsigned int v4;\n const char **v5;\n char *i;\n const char **v7;\n int v8;\n char *v10;\n char *ptr;\n int v12;\n v3 = 0;\n v4 = 0LL;\n v5 = (const char **)malloc(160uLL);\n ptr = strdup(s);\n v12 = 10;\n for (i = strtok(ptr, \" ,.-\"); i; i = strtok(0LL, \" ,.-\")) {\n v7 = v5;\n if (v3 > 0) {\n while (strcmp(*v7, i)) {\n v7 += 2;\n if (v7 == &v5[2 * v4]) goto LABEL_11;\n }\n ++*((uint32_t *)v7 + 2);\n } else {\n LABEL_11:\n if (v3 >= v12) {\n v12 *= 2;\n v5 = (const char **)realloc(v5, 16LL * v12);\n }\n ++v3;\n v10 = (char *)&v5[2 * v4];\n *(uint64_t *)v10 = strdup(i);\n *((uint32_t *)v10 + 2) = 1;\n v4 = v3;\n }\n }\n free(ptr);\n qsort(v5, v4, 16uLL, compare);\n v8 = a2;\n if (a2 > v3) v8 = v3;\n *a3 = v8;\n return v5;\n}" + }, + { + "index": 862, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char *word;\n\n int frequency;\n\n} WordFreq;\n\n\n\nint compare(const void *a, const void *b) {\n\n WordFreq *wordFreq1 = (WordFreq *)a;\n\n WordFreq *wordFreq2 = (WordFreq *)b;\n\n return wordFreq2->frequency - wordFreq1->frequency;\n\n}\n\n\n\n", + "func": "WordFreq *func0(char *text, int n, int *returnSize) {\n char *token;\n int size = 0, capacity = 10;\n WordFreq *freqs = (WordFreq *)malloc(capacity * sizeof(WordFreq));\n char *text_copy = strdup(text);\n for (token = strtok(text_copy, \" ,.-\"); token != NULL;\n token = strtok(NULL, \" ,.-\")) {\n int found = 0;\n for (int i = 0; i < size; ++i) {\n if (strcmp(freqs[i].word, token) == 0) {\n freqs[i].frequency++;\n found = 1;\n break;\n }\n }\n if (!found) {\n if (size >= capacity) {\n capacity *= 2;\n freqs = realloc(freqs, capacity * sizeof(WordFreq));\n }\n freqs[size].word = strdup(token);\n freqs[size].frequency = 1;\n size++;\n }\n }\n free(text_copy);\n qsort(freqs, size, sizeof(WordFreq), compare);\n *returnSize = n > size ? size : n;\n return freqs;\n}", + "test": "int main() {\n\n int size;\n\n WordFreq *result;\n\n \n\n result = func0(\"python is a programming language\", 1, &size);\n\n assert(size == 1 && strcmp(result[0].word, \"python\") == 0 && result[0].frequency == 1);\n\n free(result);\n\n\n\n result = func0(\"python is a programming language\", 2, &size);\n\n assert(size == 2 && strcmp(result[0].word, \"python\") == 0 && result[0].frequency == 1);\n\n free(result);\n\n\n\n result = func0(\"python is a programming language\", 5, &size);\n\n assert(size == 5 && strcmp(result[0].word, \"python\") == 0 && result[0].frequency == 1);\n\n for(int i = 0; i < size; i++) {\n\n free(result[i].word);\n\n }\n\n free(result);\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\nxor %r13d,%r13d\npush %r12\npush %rbp\nmov %rdi,%rbp\nmov $0xa0,%edi\npush %rbx\nsub $0x28,%rsp\nmov %esi,0x14(%rsp)\nmov %rdx,0x18(%rsp)\ncallq 1120 \nmov %rbp,%rdi\nxor %ebp,%ebp\nmov %rax,%r12\ncallq 1150 \nlea 0xbb5(%rip),%rsi\nmov %rax,%rdi\nmov %rax,0x8(%rsp)\ncallq 1140 \nmovl $0xa,0x10(%rsp)\ntest %rax,%rax\nje 14ca \nmov %rax,%r15\nlea 0xb91(%rip),%r13\nnopl 0x0(%rax,%rax,1)\ntest %ebp,%ebp\nje 152e \nlea -0x1(%rbp),%eax\nmov %r12,%r14\nshl $0x4,%rax\nlea 0x10(%r12,%rax,1),%rbx\njmp 14a1 \nnopl 0x0(%rax)\nadd $0x10,%r14\ncmp %rbx,%r14\nje 1510 \nmov (%r14),%rdi\nmov %r15,%rsi\ncallq 1110 \ntest %eax,%eax\njne 1498 \naddl $0x1,0x8(%r14)\nmov %r13,%rsi\nxor %edi,%edi\ncallq 1140 \nmov %rax,%r15\ntest %rax,%rax\njne 1478 \nmovslq %ebp,%r13\nmov 0x8(%rsp),%rdi\ncallq 10d0 \nmov %r13,%rsi\nmov %r12,%rdi\nmov $0x10,%edx\nlea -0xe6(%rip),%rcx\ncallq 10e0 \nmov 0x14(%rsp),%eax\ncmp %ebp,%eax\ncmovle %eax,%ebp\nmov 0x18(%rsp),%rax\nmov %ebp,(%rax)\nadd $0x28,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl (%rax)\ncmp %ebp,0x10(%rsp)\njg 152e \nshll 0x10(%rsp)\nmovslq 0x10(%rsp),%rsi\nmov %r12,%rdi\nshl $0x4,%rsi\ncallq 1130 \nmov %rax,%r12\nmovslq %ebp,%rbx\nmov %r15,%rdi\nadd $0x1,%ebp\ncallq 1150 \nshl $0x4,%rbx\nadd %r12,%rbx\nmov %rax,(%rbx)\nmovl $0x1,0x8(%rbx)\njmpq 14b5 \nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nxor r14d, r14d\npush r13\npush r12\nxor r12d, r12d\npush rbp\npush rbx\nmov rbx, rdi\nmov edi, 0A0h; size\nsub rsp, 28h\nmov [rsp+58h+var_44], esi\nmov [rsp+58h+var_40], rdx\ncall _malloc\nmov rdi, rbx; s\nmov r13, rax\ncall _strdup\nlea rsi, delim; \" ,.-\"\nmov rdi, rax; s\nmov [rsp+58h+ptr], rax\ncall _strtok\nmov [rsp+58h+var_48], 0Ah\nmov rbx, rax\ntest rax, rax\njz short loc_149B\nnop dword ptr [rax]\nloc_1450:\nmov rbp, r12\nmov r15, r13\nshl rbp, 4\nadd rbp, r13\ntest r14d, r14d\njg short loc_1471\njmp short loc_14E0\nloc_1468:\nadd r15, 10h\ncmp rbp, r15\njz short loc_14E0\nloc_1471:\nmov rdi, [r15]; s1\nmov rsi, rbx; s2\ncall _strcmp\ntest eax, eax\njnz short loc_1468\nadd dword ptr [r15+8], 1\nloc_1485:\nlea rsi, delim; \" ,.-\"\nxor edi, edi; s\ncall _strtok\nmov rbx, rax\ntest rax, rax\njnz short loc_1450\nloc_149B:\nmov rdi, [rsp+58h+ptr]; ptr\ncall _free\nmov rsi, r12; nmemb\nmov rdi, r13; base\nmov edx, 10h; size\nlea rcx, compare; compar\ncall _qsort\nmov eax, [rsp+58h+var_44]\nmov rcx, [rsp+58h+var_40]\ncmp eax, r14d\ncmovg eax, r14d\nmov [rcx], eax\nadd rsp, 28h\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14E0:\nmov eax, [rsp+58h+var_48]\ncmp r14d, eax\njge short loc_1518\nloc_14E9:\nshl r12, 4\nmov rdi, rbx; s\nadd r14d, 1\ncall _strdup\nadd r12, r13\nmov [r12], rax\nmov dword ptr [r12+8], 1\nmovsxd r12, r14d\njmp loc_1485\nloc_1518:\nshl [rsp+58h+var_48], 1\nmovsxd rsi, [rsp+58h+var_48]\nmov rdi, r13; ptr\nshl rsi, 4; size\ncall _realloc\nmov r13, rax\njmp short loc_14E9", + "ida_pseudo": "const char **__fastcall func0(char *s, int a2, int *a3)\n{\n int v3; // r14d\n size_t v4; // r12\n const char **v5; // r13\n char *i; // rbx\n const char **v7; // r15\n int v8; // eax\n char *v10; // r12\n char *ptr; // [rsp+8h] [rbp-50h]\n int v12; // [rsp+10h] [rbp-48h]\n\n v3 = 0;\n v4 = 0LL;\n v5 = (const char **)malloc(0xA0uLL);\n ptr = strdup(s);\n v12 = 10;\n for ( i = strtok(ptr, \" ,.-\"); i; i = strtok(0LL, \" ,.-\") )\n {\n v7 = v5;\n if ( v3 > 0 )\n {\n while ( strcmp(*v7, i) )\n {\n v7 += 2;\n if ( &v5[2 * v4] == v7 )\n goto LABEL_11;\n }\n ++*((_DWORD *)v7 + 2);\n }\n else\n {\nLABEL_11:\n if ( v3 >= v12 )\n {\n v12 *= 2;\n v5 = (const char **)realloc(v5, 16LL * v12);\n }\n ++v3;\n v10 = (char *)&v5[2 * v4];\n *(_QWORD *)v10 = strdup(i);\n *((_DWORD *)v10 + 2) = 1;\n v4 = v3;\n }\n }\n free(ptr);\n qsort(v5, v4, 0x10uLL, compare);\n v8 = a2;\n if ( a2 > v3 )\n v8 = v3;\n *a3 = v8;\n return v5;\n}", + "ida_strip_asm": "sub_13F0:\nendbr64\npush r15\npush r14\nxor r14d, r14d\npush r13\npush r12\nxor r12d, r12d\npush rbp\npush rbx\nmov rbx, rdi\nmov edi, 0A0h; size\nsub rsp, 28h\nmov [rsp+58h+var_44], esi\nmov [rsp+58h+var_40], rdx\ncall _malloc\nmov rdi, rbx; s\nmov r13, rax\ncall _strdup\nlea rsi, delim; \" ,.-\"\nmov rdi, rax; s\nmov [rsp+58h+ptr], rax\ncall _strtok\nmov [rsp+58h+var_48], 0Ah\nmov rbx, rax\ntest rax, rax\njz short loc_149B\nnop dword ptr [rax]\nloc_1450:\nmov rbp, r12\nmov r15, r13\nshl rbp, 4\nadd rbp, r13\ntest r14d, r14d\njg short loc_1471\njmp short loc_14E0\nloc_1468:\nadd r15, 10h\ncmp rbp, r15\njz short loc_14E0\nloc_1471:\nmov rdi, [r15]; s1\nmov rsi, rbx; s2\ncall _strcmp\ntest eax, eax\njnz short loc_1468\nadd dword ptr [r15+8], 1\nloc_1485:\nlea rsi, delim; \" ,.-\"\nxor edi, edi; s\ncall _strtok\nmov rbx, rax\ntest rax, rax\njnz short loc_1450\nloc_149B:\nmov rdi, [rsp+58h+ptr]; ptr\ncall _free\nmov rsi, r12; nmemb\nmov rdi, r13; base\nmov edx, 10h; size\nlea rcx, compar; compar\ncall _qsort\nmov eax, [rsp+58h+var_44]\nmov rcx, [rsp+58h+var_40]\ncmp eax, r14d\ncmovg eax, r14d\nmov [rcx], eax\nadd rsp, 28h\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14E0:\nmov eax, [rsp+58h+var_48]\ncmp r14d, eax\njge short loc_1518\nloc_14E9:\nshl r12, 4\nmov rdi, rbx; s\nadd r14d, 1\ncall _strdup\nadd r12, r13\nmov [r12], rax\nmov dword ptr [r12+8], 1\nmovsxd r12, r14d\njmp loc_1485\nloc_1518:\nshl [rsp+58h+var_48], 1\nmovsxd rsi, [rsp+58h+var_48]\nmov rdi, r13; ptr\nshl rsi, 4; size\ncall _realloc\nmov r13, rax\njmp short loc_14E9", + "ida_strip_pseudo": "const char **__fastcall sub_13F0(char *s, int a2, int *a3)\n{\n int v3; // r14d\n size_t v4; // r12\n const char **v5; // r13\n char *i; // rbx\n const char **v7; // r15\n int v8; // eax\n char *v10; // r12\n char *ptr; // [rsp+8h] [rbp-50h]\n int v12; // [rsp+10h] [rbp-48h]\n\n v3 = 0;\n v4 = 0LL;\n v5 = (const char **)malloc(0xA0uLL);\n ptr = strdup(s);\n v12 = 10;\n for ( i = strtok(ptr, \" ,.-\"); i; i = strtok(0LL, \" ,.-\") )\n {\n v7 = v5;\n if ( v3 > 0 )\n {\n while ( strcmp(*v7, i) )\n {\n v7 += 2;\n if ( &v5[2 * v4] == v7 )\n goto LABEL_11;\n }\n ++*((_DWORD *)v7 + 2);\n }\n else\n {\nLABEL_11:\n if ( v3 >= v12 )\n {\n v12 *= 2;\n v5 = (const char **)realloc(v5, 16LL * v12);\n }\n ++v3;\n v10 = (char *)&v5[2 * v4];\n *(_QWORD *)v10 = strdup(i);\n *((_DWORD *)v10 + 2) = 1;\n v4 = v3;\n }\n }\n free(ptr);\n qsort(v5, v4, 0x10uLL, compar);\n v8 = a2;\n if ( a2 > v3 )\n v8 = v3;\n *a3 = v8;\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char **sub_13F0(char *s, int a2, int *a3) {\n int v3;\n unsigned int v4;\n const char **v5;\n char *i;\n const char **v7;\n int v8;\n char *v10;\n char *ptr;\n int v12;\n v3 = 0;\n v4 = 0LL;\n v5 = (const char **)malloc(160uLL);\n ptr = strdup(s);\n v12 = 10;\n for (i = strtok(ptr, \" ,.-\"); i; i = strtok(0LL, \" ,.-\")) {\n v7 = v5;\n if (v3 > 0) {\n while (strcmp(*v7, i)) {\n v7 += 2;\n if (&v5[2 * v4] == v7) goto LABEL_11;\n }\n ++*((uint32_t *)v7 + 2);\n } else {\n LABEL_11:\n if (v3 >= v12) {\n v12 *= 2;\n v5 = (const char **)realloc(v5, 16LL * v12);\n }\n ++v3;\n v10 = (char *)&v5[2 * v4];\n *(uint64_t *)v10 = strdup(i);\n *((uint32_t *)v10 + 2) = 1;\n v4 = v3;\n }\n }\n free(ptr);\n qsort(v5, v4, 16uLL, compar);\n v8 = a2;\n if (a2 > v3) v8 = v3;\n *a3 = v8;\n return v5;\n}", + "ida_pseudo_norm": "const char **func0(char *s, int a2, int *a3) {\n int v3;\n unsigned int v4;\n const char **v5;\n char *i;\n const char **v7;\n int v8;\n char *v10;\n char *ptr;\n int v12;\n v3 = 0;\n v4 = 0LL;\n v5 = (const char **)malloc(160uLL);\n ptr = strdup(s);\n v12 = 10;\n for (i = strtok(ptr, \" ,.-\"); i; i = strtok(0LL, \" ,.-\")) {\n v7 = v5;\n if (v3 > 0) {\n while (strcmp(*v7, i)) {\n v7 += 2;\n if (&v5[2 * v4] == v7) goto LABEL_11;\n }\n ++*((uint32_t *)v7 + 2);\n } else {\n LABEL_11:\n if (v3 >= v12) {\n v12 *= 2;\n v5 = (const char **)realloc(v5, 16LL * v12);\n }\n ++v3;\n v10 = (char *)&v5[2 * v4];\n *(uint64_t *)v10 = strdup(i);\n *((uint32_t *)v10 + 2) = 1;\n v4 = v3;\n }\n }\n free(ptr);\n qsort(v5, v4, 16uLL, compare);\n v8 = a2;\n if (a2 > v3) v8 = v3;\n *a3 = v8;\n return v5;\n}" + }, + { + "index": 863, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int ans = 0, count = 0;\n int i, j;\n for (i = 0; i < n - 1; i++) {\n for (j = 0; j < n - i - 1; j++) {\n if (arr[j] > arr[j + 1]) {\n int temp = arr[j];\n arr[j] = arr[j + 1];\n arr[j + 1] = temp;\n }\n }\n }\n int *v = (int *)malloc(n * sizeof(int));\n int size_v = 0;\n v[size_v++] = arr[0];\n for (i = 1; i < n; i++) {\n if (arr[i] != arr[i - 1]) {\n v[size_v++] = arr[i];\n }\n }\n for (i = 0; i < size_v; i++) {\n if (i > 0 && v[i] == v[i - 1] + 1) {\n count++;\n } else {\n count = 1;\n }\n if (ans < count) {\n ans = count;\n }\n }\n free(v);\n return ans;\n}", + "test": "int main() {\n\n assert(func0((int[]){1, 2, 2, 3}, 4) == 3);\n\n assert(func0((int[]){1, 9, 3, 10, 4, 20, 2}, 7) == 4);\n\n assert(func0((int[]){36, 41, 56, 35, 44, 33, 34, 92, 43, 32, 42}, 11) == 5);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmovl $0x0,-0x20(%rbp)\nmovl $0x0,-0x1c(%rbp)\nmovl $0x0,-0x18(%rbp)\njmpq 1297 \nmovl $0x0,-0x14(%rbp)\njmpq 1281 \nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x14(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njle 127d \nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0xc(%rbp)\nmov -0x14(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov -0x14(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x28(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\nmov -0x14(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rax,%rdx\nmov -0xc(%rbp),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x14(%rbp)\nmov -0x2c(%rbp),%eax\nsub -0x18(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x14(%rbp)\njl 11e2 \naddl $0x1,-0x18(%rbp)\nmov -0x2c(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x18(%rbp)\njl 11d6 \nmov -0x2c(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0x10(%rbp)\nmov -0x10(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x10(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov -0x28(%rbp),%rax\nmov (%rax),%eax\nmov %eax,(%rdx)\nmovl $0x1,-0x18(%rbp)\njmp 1354 \nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x18(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\nje 1350 \nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x10(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x10(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 12ed \nmovl $0x0,-0x18(%rbp)\njmp 13be \ncmpl $0x0,-0x18(%rbp)\njle 13a5 \nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov -0x18(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x2,%rdx\nlea -0x4(%rdx),%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rdx),%edx\nadd $0x1,%edx\ncmp %edx,%eax\njne 13a5 \naddl $0x1,-0x1c(%rbp)\njmp 13ac \nmovl $0x1,-0x1c(%rbp)\nmov -0x20(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njge 13ba \nmov -0x1c(%rbp),%eax\nmov %eax,-0x20(%rbp)\naddl $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%eax\ncmp -0x10(%rbp),%eax\njl 1365 \nmov -0x8(%rbp),%rax\nmov %rax,%rdi\ncallq 1080 \nmov -0x20(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_20], 0\nmov [rbp+var_1C], 0\nmov [rbp+var_18], 0\njmp loc_1297\nloc_11D6:\nmov [rbp+var_14], 0\njmp loc_1281\nloc_11E2:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_14]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_127D\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nmov eax, [rbp+var_14]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_14]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov eax, [rbp+var_C]\nmov [rdx], eax\nloc_127D:\nadd [rbp+var_14], 1\nloc_1281:\nmov eax, [rbp+var_2C]\nsub eax, [rbp+var_18]\nsub eax, 1\ncmp [rbp+var_14], eax\njl loc_11E2\nadd [rbp+var_18], 1\nloc_1297:\nmov eax, [rbp+var_2C]\nsub eax, 1\ncmp [rbp+var_18], eax\njl loc_11D6\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov [rbp+var_10], 0\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov rax, [rbp+var_28]\nmov eax, [rax]\nmov [rdx], eax\nmov [rbp+var_18], 1\njmp short loc_1354\nloc_12ED:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_18]\ncdqe\nshl rax, 2\nlea rcx, [rax-4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_1350\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_1350:\nadd [rbp+var_18], 1\nloc_1354:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_2C]\njl short loc_12ED\nmov [rbp+var_18], 0\njmp short loc_13BD\nloc_1365:\ncmp [rbp+var_18], 0\njle short loc_13A4\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_18]\ncdqe\nshl rax, 2\nlea rcx, [rax-4]\nmov rax, [rbp+ptr]\nadd rax, rcx\nmov eax, [rax]\nadd eax, 1\ncmp edx, eax\njnz short loc_13A4\nadd [rbp+var_1C], 1\njmp short loc_13AB\nloc_13A4:\nmov [rbp+var_1C], 1\nloc_13AB:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_1C]\njge short loc_13B9\nmov eax, [rbp+var_1C]\nmov [rbp+var_20], eax\nloc_13B9:\nadd [rbp+var_18], 1\nloc_13BD:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_10]\njl short loc_1365\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov eax, [rbp+var_20]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n int v2; // eax\n int v4; // [rsp+10h] [rbp-20h]\n int v5; // [rsp+14h] [rbp-1Ch]\n int i; // [rsp+18h] [rbp-18h]\n int k; // [rsp+18h] [rbp-18h]\n int m; // [rsp+18h] [rbp-18h]\n int j; // [rsp+1Ch] [rbp-14h]\n int v10; // [rsp+20h] [rbp-10h]\n int v11; // [rsp+24h] [rbp-Ch]\n _DWORD *ptr; // [rsp+28h] [rbp-8h]\n\n v4 = 0;\n v5 = 0;\n for ( i = 0; i < a2 - 1; ++i )\n {\n for ( j = 0; j < a2 - i - 1; ++j )\n {\n if ( a1[j] > a1[j + 1] )\n {\n v11 = a1[j];\n a1[j] = a1[j + 1];\n a1[j + 1] = v11;\n }\n }\n }\n ptr = malloc(4LL * a2);\n v10 = 1;\n *ptr = *a1;\n for ( k = 1; k < a2; ++k )\n {\n if ( a1[k] != a1[k - 1] )\n {\n v2 = v10++;\n ptr[v2] = a1[k];\n }\n }\n for ( m = 0; m < v10; ++m )\n {\n if ( m > 0 && ptr[m] == ptr[m - 1] + 1 )\n ++v5;\n else\n v5 = 1;\n if ( v4 < v5 )\n v4 = v5;\n }\n free(ptr);\n return (unsigned int)v4;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_20], 0\nmov [rbp+var_1C], 0\nmov [rbp+var_18], 0\njmp loc_1297\nloc_11D6:\nmov [rbp+var_14], 0\njmp loc_1281\nloc_11E2:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_14]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_127D\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\nmov eax, [rbp+var_14]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_14]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov eax, [rbp+var_C]\nmov [rdx], eax\nloc_127D:\nadd [rbp+var_14], 1\nloc_1281:\nmov eax, [rbp+var_2C]\nsub eax, [rbp+var_18]\nsub eax, 1\ncmp [rbp+var_14], eax\njl loc_11E2\nadd [rbp+var_18], 1\nloc_1297:\nmov eax, [rbp+var_2C]\nsub eax, 1\ncmp [rbp+var_18], eax\njl loc_11D6\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov [rbp+var_10], 0\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov rax, [rbp+var_28]\nmov eax, [rax]\nmov [rdx], eax\nmov [rbp+var_18], 1\njmp short loc_1354\nloc_12ED:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_18]\ncdqe\nshl rax, 2\nlea rcx, [rax-4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_1350\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_1350:\nadd [rbp+var_18], 1\nloc_1354:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_2C]\njl short loc_12ED\nmov [rbp+var_18], 0\njmp short loc_13BD\nloc_1365:\ncmp [rbp+var_18], 0\njle short loc_13A4\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_18]\ncdqe\nshl rax, 2\nlea rcx, [rax-4]\nmov rax, [rbp+ptr]\nadd rax, rcx\nmov eax, [rax]\nadd eax, 1\ncmp edx, eax\njnz short loc_13A4\nadd [rbp+var_1C], 1\njmp short loc_13AB\nloc_13A4:\nmov [rbp+var_1C], 1\nloc_13AB:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_1C]\njge short loc_13B9\nmov eax, [rbp+var_1C]\nmov [rbp+var_20], eax\nloc_13B9:\nadd [rbp+var_18], 1\nloc_13BD:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_10]\njl short loc_1365\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov eax, [rbp+var_20]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(_DWORD *a1, int a2)\n{\n int v2; // eax\n int v4; // [rsp+10h] [rbp-20h]\n int v5; // [rsp+14h] [rbp-1Ch]\n int i; // [rsp+18h] [rbp-18h]\n int k; // [rsp+18h] [rbp-18h]\n int m; // [rsp+18h] [rbp-18h]\n int j; // [rsp+1Ch] [rbp-14h]\n int v10; // [rsp+20h] [rbp-10h]\n int v11; // [rsp+24h] [rbp-Ch]\n _DWORD *ptr; // [rsp+28h] [rbp-8h]\n\n v4 = 0;\n v5 = 0;\n for ( i = 0; i < a2 - 1; ++i )\n {\n for ( j = 0; j < a2 - i - 1; ++j )\n {\n if ( a1[j] > a1[j + 1] )\n {\n v11 = a1[j];\n a1[j] = a1[j + 1];\n a1[j + 1] = v11;\n }\n }\n }\n ptr = malloc(4LL * a2);\n v10 = 1;\n *ptr = *a1;\n for ( k = 1; k < a2; ++k )\n {\n if ( a1[k] != a1[k - 1] )\n {\n v2 = v10++;\n ptr[v2] = a1[k];\n }\n }\n for ( m = 0; m < v10; ++m )\n {\n if ( m > 0 && ptr[m] == ptr[m - 1] + 1 )\n ++v5;\n else\n v5 = 1;\n if ( v4 < v5 )\n v4 = v5;\n }\n free(ptr);\n return (unsigned int)v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(uint32_t *a1, int a2) {\n int v2;\n int v4;\n int v5;\n int i;\n int k;\n int m;\n int j;\n int v10;\n int v11;\n uint32_t *ptr;\n v4 = 0;\n v5 = 0;\n for (i = 0; i < a2 - 1; ++i) {\n for (j = 0; j < a2 - i - 1; ++j) {\n if (a1[j] > a1[j + 1]) {\n v11 = a1[j];\n a1[j] = a1[j + 1];\n a1[j + 1] = v11;\n }\n }\n }\n ptr = malloc(4LL * a2);\n v10 = 1;\n *ptr = *a1;\n for (k = 1; k < a2; ++k) {\n if (a1[k] != a1[k - 1]) {\n v2 = v10++;\n ptr[v2] = a1[k];\n }\n }\n for (m = 0; m < v10; ++m) {\n if (m > 0 && ptr[m] == ptr[m - 1] + 1)\n ++v5;\n else\n v5 = 1;\n if (v4 < v5) v4 = v5;\n }\n free(ptr);\n return (unsigned int)v4;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n int v2;\n int v4;\n int v5;\n int i;\n int k;\n int m;\n int j;\n int v10;\n int v11;\n uint32_t *ptr;\n v4 = 0;\n v5 = 0;\n for (i = 0; i < a2 - 1; ++i) {\n for (j = 0; j < a2 - i - 1; ++j) {\n if (a1[j] > a1[j + 1]) {\n v11 = a1[j];\n a1[j] = a1[j + 1];\n a1[j + 1] = v11;\n }\n }\n }\n ptr = malloc(4LL * a2);\n v10 = 1;\n *ptr = *a1;\n for (k = 1; k < a2; ++k) {\n if (a1[k] != a1[k - 1]) {\n v2 = v10++;\n ptr[v2] = a1[k];\n }\n }\n for (m = 0; m < v10; ++m) {\n if (m > 0 && ptr[m] == ptr[m - 1] + 1)\n ++v5;\n else\n v5 = 1;\n if (v4 < v5) v4 = v5;\n }\n free(ptr);\n return (unsigned int)v4;\n}" + }, + { + "index": 863, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int ans = 0, count = 0;\n int i, j;\n for (i = 0; i < n - 1; i++) {\n for (j = 0; j < n - i - 1; j++) {\n if (arr[j] > arr[j + 1]) {\n int temp = arr[j];\n arr[j] = arr[j + 1];\n arr[j + 1] = temp;\n }\n }\n }\n int *v = (int *)malloc(n * sizeof(int));\n int size_v = 0;\n v[size_v++] = arr[0];\n for (i = 1; i < n; i++) {\n if (arr[i] != arr[i - 1]) {\n v[size_v++] = arr[i];\n }\n }\n for (i = 0; i < size_v; i++) {\n if (i > 0 && v[i] == v[i - 1] + 1) {\n count++;\n } else {\n count = 1;\n }\n if (ans < count) {\n ans = count;\n }\n }\n free(v);\n return ans;\n}", + "test": "int main() {\n\n assert(func0((int[]){1, 2, 2, 3}, 4) == 3);\n\n assert(func0((int[]){1, 9, 3, 10, 4, 20, 2}, 7) == 4);\n\n assert(func0((int[]){36, 41, 56, 35, 44, 33, 34, 92, 43, 32, 42}, 11) == 5);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbx\nmov %esi,%ebp\nlea -0x1(%rsi),%edi\ntest %edi,%edi\njle 11f3 \nlea 0x4(%rbx),%r8\njmp 11e3 \nadd $0x4,%rax\ncmp %rsi,%rax\nje 11de \nmov (%rax),%edx\nmov 0x4(%rax),%ecx\ncmp %ecx,%edx\njle 11c5 \nmov %ecx,(%rax)\nmov %edx,0x4(%rax)\njmp 11c5 \nsub $0x1,%edi\nje 11f3 \ntest %edi,%edi\njle 11de \nmov %rbx,%rax\nlea -0x1(%rdi),%edx\nlea (%r8,%rdx,4),%rsi\njmp 11ce \nmovslq %ebp,%rdi\nshl $0x2,%rdi\ncallq 10b0 \nmov (%rbx),%edx\nmov %edx,(%rax)\ncmp $0x1,%ebp\njle 124a \nmov %rbx,%rdx\nlea -0x2(%rbp),%ecx\nlea 0x4(%rbx,%rcx,4),%r8\nmov $0x1,%esi\njmp 1223 \nadd $0x4,%rdx\ncmp %r8,%rdx\nje 1235 \nmov 0x4(%rdx),%ecx\ncmp (%rdx),%ecx\nje 121a \nmovslq %esi,%rdi\nmov %ecx,(%rax,%rdi,4)\nlea 0x1(%rsi),%esi\njmp 121a \ntest %esi,%esi\njle 127d \nmov $0x0,%edx\nmov $0x0,%ecx\nmov $0x0,%ebx\njmp 1263 \nmov $0x1,%esi\njmp 1239 \nmov $0x1,%ecx\ncmp %ecx,%ebx\ncmovl %ecx,%ebx\nadd $0x1,%rdx\ncmp %edx,%esi\njle 1282 \ntest %edx,%edx\njle 1251 \nmov -0x4(%rax,%rdx,4),%edi\nadd $0x1,%edi\nadd $0x1,%ecx\ncmp %edi,(%rax,%rdx,4)\nje 1256 \nmov $0x1,%ecx\njmp 1256 \nmov $0x0,%ebx\nmov %rax,%rdi\ncallq 1080 \nmov %ebx,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov ebp, esi\ncmp esi, 1\njle loc_1297\nmov edi, esi\nlea r8, [rbx+4]\njmp short loc_11EA\nloc_11C9:\nadd rax, 4\ncmp rax, rsi\njz short loc_11E2\nloc_11D2:\nmov edx, [rax]\nmov ecx, [rax+4]\ncmp edx, ecx\njle short loc_11C9\nmov [rax], ecx\nmov [rax+4], edx\njmp short loc_11C9\nloc_11E2:\nsub edi, 1\ncmp edi, 1\njz short loc_11FF\nloc_11EA:\ncmp edi, 1\njle loc_12B1\nmov rax, rbx\nlea edx, [rdi-2]\nlea rsi, [r8+rdx*4]\njmp short loc_11D2\nloc_11FF:\nmovsxd rdi, ebp\nshl rdi, 2; size\ncall _malloc\nmov rdi, rax; ptr\nmov eax, [rbx]\nmov [rdi], eax\nmov rax, rbx\nlea edx, [rbp-2]\nlea r8, [rbx+rdx*4+4]\nmov edx, 1\njmp short loc_122D\nloc_1224:\nadd rax, 4\ncmp rax, r8\njz short loc_123F\nloc_122D:\nmov ecx, [rax+4]\ncmp ecx, [rax]\njz short loc_1224\nmovsxd rsi, edx\nmov [rdi+rsi*4], ecx\nlea edx, [rdx+1]\njmp short loc_1224\nloc_123F:\ntest edx, edx\njle short loc_1284\nloc_1243:\nmovsxd rdx, edx\nmov eax, 0\nmov ecx, 0\nmov ebx, 0\njmp short loc_126A\nloc_1257:\nmov ecx, 1\nloc_125C:\ncmp ebx, ecx\ncmovl ebx, ecx\nadd rax, 1\ncmp rax, rdx\njz short loc_1289\nloc_126A:\ntest eax, eax\njle short loc_1257\nmov esi, [rdi+rax*4-4]\nadd esi, 1\nadd ecx, 1\ncmp [rdi+rax*4], esi\njz short loc_125C\nmov ecx, 1\njmp short loc_125C\nloc_1284:\nmov ebx, 0\nloc_1289:\ncall _free\nmov eax, ebx\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1297:\nmovsxd rdi, esi\nshl rdi, 2; size\ncall _malloc\nmov rdi, rax\nmov eax, [rbx]\nmov [rdi], eax\nmov edx, 1\njmp short loc_1243\nloc_12B1:\nsub edi, 1\njmp loc_11EA", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int i; // edi\n int *v4; // rax\n int v5; // edx\n int v6; // ecx\n _DWORD *v7; // rdi\n int *v8; // rax\n int v9; // edx\n int v10; // ecx\n __int64 v11; // rax\n int v12; // ecx\n int v13; // ebx\n\n if ( a2 <= 1 )\n {\n v7 = malloc(4LL * a2);\n *v7 = *a1;\n v9 = 1;\n }\n else\n {\n for ( i = a2; i != 1; --i )\n {\n while ( i <= 1 )\n --i;\n v4 = a1;\n do\n {\n v5 = *v4;\n v6 = v4[1];\n if ( *v4 > v6 )\n {\n *v4 = v6;\n v4[1] = v5;\n }\n ++v4;\n }\n while ( v4 != &a1[i - 2 + 1] );\n }\n v7 = malloc(4LL * a2);\n *v7 = *a1;\n v8 = a1;\n v9 = 1;\n do\n {\n v10 = v8[1];\n if ( v10 != *v8 )\n v7[v9++] = v10;\n ++v8;\n }\n while ( v8 != &a1[a2 - 2 + 1] );\n if ( v9 <= 0 )\n {\n v13 = 0;\n goto LABEL_23;\n }\n }\n v11 = 0LL;\n v12 = 0;\n v13 = 0;\n do\n {\n if ( (int)v11 <= 0 )\n {\n v12 = 1;\n }\n else\n {\n ++v12;\n if ( v7[v11] != v7[v11 - 1] + 1 )\n v12 = 1;\n }\n if ( v13 < v12 )\n v13 = v12;\n ++v11;\n }\n while ( v11 != v9 );\nLABEL_23:\n free(v7);\n return (unsigned int)v13;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov ebp, esi\ncmp esi, 1\njle loc_1297\nmov edi, esi\nlea r8, [rbx+4]\njmp short loc_11EA\nloc_11C9:\nadd rax, 4\ncmp rax, rsi\njz short loc_11E2\nloc_11D2:\nmov edx, [rax]\nmov ecx, [rax+4]\ncmp edx, ecx\njle short loc_11C9\nmov [rax], ecx\nmov [rax+4], edx\njmp short loc_11C9\nloc_11E2:\nsub edi, 1\ncmp edi, 1\njz short loc_11FF\nloc_11EA:\ncmp edi, 1\njle loc_12B1\nmov rax, rbx\nlea edx, [rdi-2]\nlea rsi, [r8+rdx*4]\njmp short loc_11D2\nloc_11FF:\nmovsxd rdi, ebp\nshl rdi, 2; size\ncall _malloc\nmov rdi, rax; ptr\nmov eax, [rbx]\nmov [rdi], eax\nmov rax, rbx\nlea edx, [rbp-2]\nlea r8, [rbx+rdx*4+4]\nmov edx, 1\njmp short loc_122D\nloc_1224:\nadd rax, 4\ncmp rax, r8\njz short loc_123F\nloc_122D:\nmov ecx, [rax+4]\ncmp ecx, [rax]\njz short loc_1224\nmovsxd rsi, edx\nmov [rdi+rsi*4], ecx\nlea edx, [rdx+1]\njmp short loc_1224\nloc_123F:\ntest edx, edx\njle short loc_1284\nloc_1243:\nmovsxd rdx, edx\nmov eax, 0\nmov ecx, 0\nmov ebx, 0\njmp short loc_126A\nloc_1257:\nmov ecx, 1\nloc_125C:\ncmp ebx, ecx\ncmovl ebx, ecx\nadd rax, 1\ncmp rax, rdx\njz short loc_1289\nloc_126A:\ntest eax, eax\njle short loc_1257\nmov esi, [rdi+rax*4-4]\nadd esi, 1\nadd ecx, 1\ncmp [rdi+rax*4], esi\njz short loc_125C\nmov ecx, 1\njmp short loc_125C\nloc_1284:\nmov ebx, 0\nloc_1289:\ncall _free\nmov eax, ebx\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1297:\nmovsxd rdi, esi\nshl rdi, 2; size\ncall _malloc\nmov rdi, rax\nmov eax, [rbx]\nmov [rdi], eax\nmov edx, 1\njmp short loc_1243\nloc_12B1:\nsub edi, 1\njmp loc_11EA", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(int *a1, int a2)\n{\n int i; // edi\n int *v4; // rax\n int v5; // edx\n int v6; // ecx\n _DWORD *v7; // rdi\n int *v8; // rax\n int v9; // edx\n int v10; // ecx\n __int64 v11; // rax\n int v12; // ecx\n int v13; // ebx\n\n if ( a2 <= 1 )\n {\n v7 = malloc(4LL * a2);\n *v7 = *a1;\n v9 = 1;\n }\n else\n {\n for ( i = a2; i != 1; --i )\n {\n while ( i <= 1 )\n --i;\n v4 = a1;\n do\n {\n v5 = *v4;\n v6 = v4[1];\n if ( *v4 > v6 )\n {\n *v4 = v6;\n v4[1] = v5;\n }\n ++v4;\n }\n while ( v4 != &a1[i - 2 + 1] );\n }\n v7 = malloc(4LL * a2);\n *v7 = *a1;\n v8 = a1;\n v9 = 1;\n do\n {\n v10 = v8[1];\n if ( v10 != *v8 )\n v7[v9++] = v10;\n ++v8;\n }\n while ( v8 != &a1[a2 - 2 + 1] );\n if ( v9 <= 0 )\n {\n v13 = 0;\n goto LABEL_23;\n }\n }\n v11 = 0LL;\n v12 = 0;\n v13 = 0;\n do\n {\n if ( (int)v11 <= 0 )\n {\n v12 = 1;\n }\n else\n {\n ++v12;\n if ( v7[v11] != v7[v11 - 1] + 1 )\n v12 = 1;\n }\n if ( v13 < v12 )\n v13 = v12;\n ++v11;\n }\n while ( v11 != v9 );\nLABEL_23:\n free(v7);\n return (unsigned int)v13;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(int *a1, int a2) {\n int i;\n int *v4;\n int v5;\n int v6;\n uint32_t *v7;\n int *v8;\n int v9;\n int v10;\n long long v11;\n int v12;\n int v13;\n if (a2 <= 1) {\n v7 = malloc(4LL * a2);\n *v7 = *a1;\n v9 = 1;\n } else {\n for (i = a2; i != 1; --i) {\n while (i <= 1) --i;\n v4 = a1;\n do {\n v5 = *v4;\n v6 = v4[1];\n if (*v4 > v6) {\n *v4 = v6;\n v4[1] = v5;\n }\n ++v4;\n } while (v4 != &a1[i - 2 + 1]);\n }\n v7 = malloc(4LL * a2);\n *v7 = *a1;\n v8 = a1;\n v9 = 1;\n do {\n v10 = v8[1];\n if (v10 != *v8) v7[v9++] = v10;\n ++v8;\n } while (v8 != &a1[a2 - 2 + 1]);\n if (v9 <= 0) {\n v13 = 0;\n goto LABEL_23;\n }\n }\n v11 = 0LL;\n v12 = 0;\n v13 = 0;\n do {\n if ((int)v11 <= 0) {\n v12 = 1;\n } else {\n ++v12;\n if (v7[v11] != v7[v11 - 1] + 1) v12 = 1;\n }\n if (v13 < v12) v13 = v12;\n ++v11;\n } while (v11 != v9);\nLABEL_23:\n free(v7);\n return (unsigned int)v13;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int i;\n int *v4;\n int v5;\n int v6;\n uint32_t *v7;\n int *v8;\n int v9;\n int v10;\n long long v11;\n int v12;\n int v13;\n if (a2 <= 1) {\n v7 = malloc(4LL * a2);\n *v7 = *a1;\n v9 = 1;\n } else {\n for (i = a2; i != 1; --i) {\n while (i <= 1) --i;\n v4 = a1;\n do {\n v5 = *v4;\n v6 = v4[1];\n if (*v4 > v6) {\n *v4 = v6;\n v4[1] = v5;\n }\n ++v4;\n } while (v4 != &a1[i - 2 + 1]);\n }\n v7 = malloc(4LL * a2);\n *v7 = *a1;\n v8 = a1;\n v9 = 1;\n do {\n v10 = v8[1];\n if (v10 != *v8) v7[v9++] = v10;\n ++v8;\n } while (v8 != &a1[a2 - 2 + 1]);\n if (v9 <= 0) {\n v13 = 0;\n goto LABEL_23;\n }\n }\n v11 = 0LL;\n v12 = 0;\n v13 = 0;\n do {\n if ((int)v11 <= 0) {\n v12 = 1;\n } else {\n ++v12;\n if (v7[v11] != v7[v11 - 1] + 1) v12 = 1;\n }\n if (v13 < v12) v13 = v12;\n ++v11;\n } while (v11 != v9);\nLABEL_23:\n free(v7);\n return (unsigned int)v13;\n}" + }, + { + "index": 863, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int ans = 0, count = 0;\n int i, j;\n for (i = 0; i < n - 1; i++) {\n for (j = 0; j < n - i - 1; j++) {\n if (arr[j] > arr[j + 1]) {\n int temp = arr[j];\n arr[j] = arr[j + 1];\n arr[j + 1] = temp;\n }\n }\n }\n int *v = (int *)malloc(n * sizeof(int));\n int size_v = 0;\n v[size_v++] = arr[0];\n for (i = 1; i < n; i++) {\n if (arr[i] != arr[i - 1]) {\n v[size_v++] = arr[i];\n }\n }\n for (i = 0; i < size_v; i++) {\n if (i > 0 && v[i] == v[i - 1] + 1) {\n count++;\n } else {\n count = 1;\n }\n if (ans < count) {\n ans = count;\n }\n }\n free(v);\n return ans;\n}", + "test": "int main() {\n\n assert(func0((int[]){1, 2, 2, 3}, 4) == 3);\n\n assert(func0((int[]){1, 9, 3, 10, 4, 20, 2}, 7) == 4);\n\n assert(func0((int[]){36, 41, 56, 35, 44, 33, 34, 92, 43, 32, 42}, 11) == 5);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nlea -0x1(%rsi),%edx\nmov %esi,%r12d\npush %rbx\nmov %rdi,%rbx\nsub $0x8,%rsp\ntest %edx,%edx\njle 137f \nlea 0x4(%rdi),%rsi\nnopl 0x0(%rax)\nsub $0x1,%edx\nmov %rbx,%rax\nmov %rdx,%r8\nlea (%rsi,%rdx,4),%rdi\nnopl (%rax)\nmov (%rax),%edx\nmov 0x4(%rax),%ecx\ncmp %ecx,%edx\njle 136e \nmov %ecx,(%rax)\nmov %edx,0x4(%rax)\nadd $0x4,%rax\ncmp %rdi,%rax\njne 1360 \nmov %r8d,%edx\ntest %r8d,%r8d\njne 1350 \nmovslq %r12d,%rdi\nshl $0x2,%rdi\ncallq 10b0 \nmov (%rbx),%edi\nmov %rax,%r8\nmov %edi,(%rax)\ncmp $0x1,%r12d\njle 1415 \nlea 0x4(%rbx),%rdx\nlea -0x2(%r12),%eax\nmov $0x1,%esi\nlea (%rdx,%rax,4),%r9\njmp 13b6 \nnopl 0x0(%rax)\nadd $0x4,%rdx\nmov %ecx,%edi\nmov (%rdx),%ecx\ncmp %edi,%ecx\nje 13c6 \nmovslq %esi,%rax\nadd $0x1,%esi\nmov %ecx,(%r8,%rax,4)\ncmp %r9,%rdx\njne 13b0 \nlea -0x1(%rsi),%eax\nmov %r8,%rdx\nxor %r12d,%r12d\nmov $0x1,%ecx\nlea (%r8,%rax,4),%rax\njmp 13f6 \nmov (%rdx),%ebx\nadd $0x1,%ecx\nlea 0x1(%rbx),%esi\ncmp %esi,0x4(%rdx)\nje 13f2 \nmov $0x1,%ecx\nadd $0x4,%rdx\ncmp %ecx,%r12d\ncmovl %ecx,%r12d\ncmp %rdx,%rax\njne 13e0 \nmov %r8,%rdi\ncallq 1080 \nadd $0x8,%rsp\nmov %r12d,%eax\npop %rbx\npop %r12\nretq\nmov $0x1,%esi\njmp 13cb \nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\nmovsxd r8, esi\npush r12\nmov r12, r8\npush rbp\nshl r8, 2\nmov rbp, rdi\npush rbx\ncmp r12d, 1\njle loc_13E8\nmov edi, r12d\nlea rbx, [rbp+4]\nnop word ptr [rax+rax+00000000h]\nloc_1310:\ncmp edi, 1\njle loc_13E0\nlea eax, [rdi-2]\nlea rsi, [rbx+rax*4]\nmov rax, rbp\nnop dword ptr [rax+rax+00h]\nloc_1328:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd edx, xmm0\nmovd ecx, xmm1\ncmp ecx, edx\njge short loc_1346\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_1346:\nadd rax, 4\ncmp rax, rsi\njnz short loc_1328\nsub edi, 1\ncmp edi, 1\njnz short loc_1310\nmov rdi, r8; size\ncall _malloc\nmov edx, [rbp+0]\nlea ecx, [r12-2]\nmov rdi, rax; ptr\nlea r8, [rbp+rcx*4+8]\nmov ecx, 1\nmov [rax], edx\nmov rax, rbx\nnop dword ptr [rax+00000000h]\nloc_1380:\nmov esi, edx\nmov edx, [rax]\ncmp esi, edx\njz short loc_1391\nmovsxd rsi, ecx\nadd ecx, 1\nmov [rdi+rsi*4], edx\nloc_1391:\nadd rax, 4\ncmp rax, r8\njnz short loc_1380\ntest ecx, ecx\njle short loc_13FF\nloc_139E:\nxor eax, eax\nxor edx, edx\nxor ebx, ebx\nnop dword ptr [rax+00h]\nloc_13A8:\ntest rax, rax\njz short loc_13BC\nmov esi, [rdi+rax*4-4]\nadd edx, 1\nadd esi, 1\ncmp [rdi+rax*4], esi\njz short loc_13C1\nloc_13BC:\nmov edx, 1\nloc_13C1:\ncmp ebx, edx\ncmovl ebx, edx\nadd rax, 1\ncmp ecx, eax\njg short loc_13A8\ncall _free\nmov eax, ebx\npop rbx\npop rbp\npop r12\nretn\nloc_13E0:\nsub edi, 1\njmp loc_1310\nloc_13E8:\nmov rdi, r8; size\ncall _malloc\nmov ecx, 1\nmov rdi, rax\nmov eax, [rbp+0]\nmov [rdi], eax\njmp short loc_139E\nloc_13FF:\ncall _free\nxor ebx, ebx\nmov eax, ebx\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "__int64 __fastcall func0(__m128i *a1, int a2)\n{\n int i; // edi\n __m128i *v5; // rax\n __m128i v6; // xmm0\n _DWORD *v7; // rax\n __int32 v8; // edx\n _DWORD *v9; // rdi\n int v10; // ecx\n __int32 *v11; // rax\n __int32 v12; // esi\n __int64 v13; // rsi\n __int64 v14; // rax\n int v15; // edx\n int v16; // ebx\n _DWORD *v18; // rax\n\n if ( a2 <= 1 )\n {\n v18 = malloc(4LL * a2);\n v10 = 1;\n v9 = v18;\n *v18 = a1->m128i_i32[0];\n }\n else\n {\n for ( i = a2; i != 1; --i )\n {\n while ( i <= 1 )\n --i;\n v5 = a1;\n do\n {\n v6 = _mm_loadl_epi64(v5);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v6, 229)) < _mm_cvtsi128_si32(v6) )\n v5->m128i_i64[0] = _mm_shuffle_epi32(v6, 225).m128i_u64[0];\n v5 = (__m128i *)((char *)v5 + 4);\n }\n while ( v5 != (__m128i *)((char *)a1->m128i_i64 + 4 * (unsigned int)(i - 2) + 4) );\n }\n v7 = malloc(4LL * a2);\n v8 = a1->m128i_i32[0];\n v9 = v7;\n v10 = 1;\n *v7 = a1->m128i_i32[0];\n v11 = &a1->m128i_i32[1];\n do\n {\n v12 = v8;\n v8 = *v11;\n if ( v12 != *v11 )\n {\n v13 = v10++;\n v9[v13] = v8;\n }\n ++v11;\n }\n while ( v11 != (__int32 *)((char *)&a1->m128i_u64[1] + 4 * (unsigned int)(a2 - 2)) );\n if ( v10 <= 0 )\n {\n free(v9);\n return 0LL;\n }\n }\n v14 = 0LL;\n v15 = 0;\n v16 = 0;\n do\n {\n if ( !v14 || (++v15, v9[v14] != v9[v14 - 1] + 1) )\n v15 = 1;\n if ( v16 < v15 )\n v16 = v15;\n ++v14;\n }\n while ( v10 > (int)v14 );\n free(v9);\n return (unsigned int)v16;\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\nmovsxd r8, esi\npush r12\nmov r12, r8\npush rbp\nshl r8, 2\nmov rbp, rdi\npush rbx\ncmp r12d, 1\njle loc_13E8\nmov edi, r12d\nlea rbx, [rbp+4]\nnop word ptr [rax+rax+00000000h]\nloc_1310:\ncmp edi, 1\njle loc_13E0\nlea eax, [rdi-2]\nlea rsi, [rbx+rax*4]\nmov rax, rbp\nnop dword ptr [rax+rax+00h]\nloc_1328:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd edx, xmm0\nmovd ecx, xmm1\ncmp ecx, edx\njge short loc_1346\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_1346:\nadd rax, 4\ncmp rax, rsi\njnz short loc_1328\nsub edi, 1\ncmp edi, 1\njnz short loc_1310\nmov rdi, r8; size\ncall _malloc\nmov edx, [rbp+0]\nlea ecx, [r12-2]\nmov rdi, rax; ptr\nlea r8, [rbp+rcx*4+8]\nmov ecx, 1\nmov [rax], edx\nmov rax, rbx\nnop dword ptr [rax+00000000h]\nloc_1380:\nmov esi, edx\nmov edx, [rax]\ncmp esi, edx\njz short loc_1391\nmovsxd rsi, ecx\nadd ecx, 1\nmov [rdi+rsi*4], edx\nloc_1391:\nadd rax, 4\ncmp rax, r8\njnz short loc_1380\ntest ecx, ecx\njle short loc_13FF\nloc_139E:\nxor eax, eax\nxor edx, edx\nxor ebx, ebx\nnop dword ptr [rax+00h]\nloc_13A8:\ntest rax, rax\njz short loc_13BC\nmov esi, [rdi+rax*4-4]\nadd edx, 1\nadd esi, 1\ncmp [rdi+rax*4], esi\njz short loc_13C1\nloc_13BC:\nmov edx, 1\nloc_13C1:\ncmp ebx, edx\ncmovl ebx, edx\nadd rax, 1\ncmp ecx, eax\njg short loc_13A8\ncall _free\nmov eax, ebx\npop rbx\npop rbp\npop r12\nretn\nloc_13E0:\nsub edi, 1\njmp loc_1310\nloc_13E8:\nmov rdi, r8; size\ncall _malloc\nmov ecx, 1\nmov rdi, rax\nmov eax, [rbp+0]\nmov [rdi], eax\njmp short loc_139E\nloc_13FF:\ncall _free\nxor ebx, ebx\nmov eax, ebx\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12E0(__m128i *a1, int a2)\n{\n int i; // edi\n __m128i *v5; // rax\n __m128i v6; // xmm0\n _DWORD *v7; // rax\n __int32 v8; // edx\n _DWORD *v9; // rdi\n int v10; // ecx\n __int32 *v11; // rax\n __int32 v12; // esi\n __int64 v13; // rsi\n __int64 v14; // rax\n int v15; // edx\n int v16; // ebx\n _DWORD *v18; // rax\n\n if ( a2 <= 1 )\n {\n v18 = malloc(4LL * a2);\n v10 = 1;\n v9 = v18;\n *v18 = a1->m128i_i32[0];\n }\n else\n {\n for ( i = a2; i != 1; --i )\n {\n while ( i <= 1 )\n --i;\n v5 = a1;\n do\n {\n v6 = _mm_loadl_epi64(v5);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v6, 229)) < _mm_cvtsi128_si32(v6) )\n v5->m128i_i64[0] = _mm_shuffle_epi32(v6, 225).m128i_u64[0];\n v5 = (__m128i *)((char *)v5 + 4);\n }\n while ( v5 != (__m128i *)((char *)a1->m128i_i64 + 4 * (unsigned int)(i - 2) + 4) );\n }\n v7 = malloc(4LL * a2);\n v8 = a1->m128i_i32[0];\n v9 = v7;\n v10 = 1;\n *v7 = a1->m128i_i32[0];\n v11 = &a1->m128i_i32[1];\n do\n {\n v12 = v8;\n v8 = *v11;\n if ( v12 != *v11 )\n {\n v13 = v10++;\n v9[v13] = v8;\n }\n ++v11;\n }\n while ( v11 != (__int32 *)((char *)&a1->m128i_u64[1] + 4 * (unsigned int)(a2 - 2)) );\n if ( v10 <= 0 )\n {\n free(v9);\n return 0LL;\n }\n }\n v14 = 0LL;\n v15 = 0;\n v16 = 0;\n do\n {\n if ( !v14 || (++v15, v9[v14] != v9[v14 - 1] + 1) )\n v15 = 1;\n if ( v16 < v15 )\n v16 = v15;\n ++v14;\n }\n while ( v10 > (int)v14 );\n free(v9);\n return (unsigned int)v16;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12E0(__m128i *a1, int a2) {\n int i;\n __m128i *v5;\n __m128i v6;\n uint32_t *v7;\n int v8;\n uint32_t *v9;\n int v10;\n int *v11;\n int v12;\n long long v13;\n long long v14;\n int v15;\n int v16;\n uint32_t *v18;\n if (a2 <= 1) {\n v18 = malloc(4LL * a2);\n v10 = 1;\n v9 = v18;\n *v18 = a1->m128i_i32[0];\n } else {\n for (i = a2; i != 1; --i) {\n while (i <= 1) --i;\n v5 = a1;\n do {\n v6 = _mm_loadl_epi64(v5);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v6, 229)) <\n _mm_cvtsi128_si32(v6))\n v5->m128i_i64[0] = _mm_shuffle_epi32(v6, 225).m128i_u64[0];\n v5 = (__m128i *)((char *)v5 + 4);\n } while (v5 != (__m128i *)((char *)a1->m128i_i64 +\n 4 * (unsigned int)(i - 2) + 4));\n }\n v7 = malloc(4LL * a2);\n v8 = a1->m128i_i32[0];\n v9 = v7;\n v10 = 1;\n *v7 = a1->m128i_i32[0];\n v11 = &a1->m128i_i32[1];\n do {\n v12 = v8;\n v8 = *v11;\n if (v12 != *v11) {\n v13 = v10++;\n v9[v13] = v8;\n }\n ++v11;\n } while (v11 !=\n (int *)((char *)&a1->m128i_u64[1] + 4 * (unsigned int)(a2 - 2)));\n if (v10 <= 0) {\n free(v9);\n return 0LL;\n }\n }\n v14 = 0LL;\n v15 = 0;\n v16 = 0;\n do {\n if (!v14 || (++v15, v9[v14] != v9[v14 - 1] + 1)) v15 = 1;\n if (v16 < v15) v16 = v15;\n ++v14;\n } while (v10 > (int)v14);\n free(v9);\n return (unsigned int)v16;\n}", + "ida_pseudo_norm": "long long func0(__m128i *a1, int a2) {\n int i;\n __m128i *v5;\n __m128i v6;\n uint32_t *v7;\n int v8;\n uint32_t *v9;\n int v10;\n int *v11;\n int v12;\n long long v13;\n long long v14;\n int v15;\n int v16;\n uint32_t *v18;\n if (a2 <= 1) {\n v18 = malloc(4LL * a2);\n v10 = 1;\n v9 = v18;\n *v18 = a1->m128i_i32[0];\n } else {\n for (i = a2; i != 1; --i) {\n while (i <= 1) --i;\n v5 = a1;\n do {\n v6 = _mm_loadl_epi64(v5);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v6, 229)) <\n _mm_cvtsi128_si32(v6))\n v5->m128i_i64[0] = _mm_shuffle_epi32(v6, 225).m128i_u64[0];\n v5 = (__m128i *)((char *)v5 + 4);\n } while (v5 != (__m128i *)((char *)a1->m128i_i64 +\n 4 * (unsigned int)(i - 2) + 4));\n }\n v7 = malloc(4LL * a2);\n v8 = a1->m128i_i32[0];\n v9 = v7;\n v10 = 1;\n *v7 = a1->m128i_i32[0];\n v11 = &a1->m128i_i32[1];\n do {\n v12 = v8;\n v8 = *v11;\n if (v12 != *v11) {\n v13 = v10++;\n v9[v13] = v8;\n }\n ++v11;\n } while (v11 !=\n (int *)((char *)&a1->m128i_u64[1] + 4 * (unsigned int)(a2 - 2)));\n if (v10 <= 0) {\n free(v9);\n return 0LL;\n }\n }\n v14 = 0LL;\n v15 = 0;\n v16 = 0;\n do {\n if (!v14 || (++v15, v9[v14] != v9[v14 - 1] + 1)) v15 = 1;\n if (v16 < v15) v16 = v15;\n ++v14;\n } while (v10 > (int)v14);\n free(v9);\n return (unsigned int)v16;\n}" + }, + { + "index": 863, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int ans = 0, count = 0;\n int i, j;\n for (i = 0; i < n - 1; i++) {\n for (j = 0; j < n - i - 1; j++) {\n if (arr[j] > arr[j + 1]) {\n int temp = arr[j];\n arr[j] = arr[j + 1];\n arr[j + 1] = temp;\n }\n }\n }\n int *v = (int *)malloc(n * sizeof(int));\n int size_v = 0;\n v[size_v++] = arr[0];\n for (i = 1; i < n; i++) {\n if (arr[i] != arr[i - 1]) {\n v[size_v++] = arr[i];\n }\n }\n for (i = 0; i < size_v; i++) {\n if (i > 0 && v[i] == v[i - 1] + 1) {\n count++;\n } else {\n count = 1;\n }\n if (ans < count) {\n ans = count;\n }\n }\n free(v);\n return ans;\n}", + "test": "int main() {\n\n assert(func0((int[]){1, 2, 2, 3}, 4) == 3);\n\n assert(func0((int[]){1, 9, 3, 10, 4, 20, 2}, 7) == 4);\n\n assert(func0((int[]){36, 41, 56, 35, 44, 33, 34, 92, 43, 32, 42}, 11) == 5);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nlea -0x1(%rsi),%edx\npush %r12\npush %rbp\nmov %esi,%ebp\npush %rbx\nmov %rdi,%rbx\ntest %edx,%edx\njle 133f \nlea 0x4(%rdi),%rsi\nnopl 0x0(%rax,%rax,1)\nsub $0x1,%edx\nmov %rbx,%rax\nmov %rdx,%r8\nlea (%rsi,%rdx,4),%rdi\nnopl (%rax)\nmov (%rax),%edx\nmov 0x4(%rax),%ecx\ncmp %ecx,%edx\njle 132e \nmov %ecx,(%rax)\nmov %edx,0x4(%rax)\nadd $0x4,%rax\ncmp %rdi,%rax\njne 1320 \nmov %r8d,%edx\ntest %r8d,%r8d\njne 1310 \nmovslq %ebp,%rdi\nshl $0x2,%rdi\ncallq 10b0 \nmov (%rbx),%esi\nmov %rax,%rdi\nmov %esi,(%rax)\ncmp $0x1,%ebp\njle 1488 \ncmp $0x3,%ebp\njle 149b \nlea -0x4(%rbp),%eax\nmov $0x1,%ecx\nshr %eax\nlea 0x5(%rax,%rax,1),%r8\nmov $0x3,%eax\nmov -0x8(%rbx,%rax,4),%edx\ncmp %esi,%edx\nje 1389 \nmovslq %ecx,%rsi\nadd $0x1,%ecx\nmov %edx,(%rdi,%rsi,4)\nmov -0x4(%rbx,%rax,4),%esi\ncmp %esi,%edx\nje 139a \nmovslq %ecx,%rdx\nadd $0x1,%ecx\nmov %esi,(%rdi,%rdx,4)\nmovslq %eax,%rdx\nadd $0x2,%rax\ncmp %r8,%rax\njne 1378 \nnopw %cs:0x0(%rax,%rax,1)\nmov (%rbx,%rdx,4),%eax\ncmp -0x4(%rbx,%rdx,4),%eax\nje 13c2 \nmovslq %ecx,%rsi\nadd $0x1,%ecx\nmov %eax,(%rdi,%rsi,4)\nadd $0x1,%rdx\ncmp %edx,%ebp\njg 13b0 \ncmp $0x1,%ecx\nje 1488 \ncmp $0x3,%ecx\njle 14aa \nlea -0x4(%rcx),%eax\nmov (%rdi),%r8d\nmov $0x1,%esi\nmov $0x1,%r12d\nshr %eax\nmov $0x1,%r10d\nlea 0x5(%rax,%rax,1),%r9\nmov $0x3,%eax\njmp 1419 \ncmp %esi,%r12d\nmovslq %eax,%rdx\ncmovl %esi,%r12d\nadd $0x2,%rax\nmov $0x1,%esi\ncmp %r9,%rax\nje 145d \nmov -0x8(%rdi,%rax,4),%edx\nadd $0x1,%r8d\nadd $0x1,%esi\ncmp %edx,%r8d\nmov -0x4(%rdi,%rax,4),%r8d\ncmovne %r10d,%esi\nadd $0x1,%edx\ncmp %edx,%r8d\njne 1401 \nadd $0x1,%esi\nmovslq %eax,%rdx\ncmp %esi,%r12d\ncmovl %esi,%r12d\nadd $0x2,%rax\ncmp %r9,%rax\njne 1419 \njmp 145d \nadd $0x1,%rdx\ncmp %edx,%ecx\njle 147b \nmov $0x1,%esi\nmov -0x4(%rdi,%rdx,4),%eax\nadd $0x1,%eax\ncmp %eax,(%rdi,%rdx,4)\njne 1450 \nadd $0x1,%esi\ncmp %esi,%r12d\ncmovl %esi,%r12d\nadd $0x1,%rdx\ncmp %edx,%ecx\njg 145d \ncallq 1080 \nmov %r12d,%eax\npop %rbx\npop %rbp\npop %r12\nretq\ncallq 1080 \nmov $0x1,%r12d\npop %rbx\npop %rbp\nmov %r12d,%eax\npop %r12\nretq\nmov $0x1,%ecx\nmov $0x1,%edx\njmpq 13b0 \nmov $0x1,%edx\nmov $0x1,%esi\nmov $0x1,%r12d\njmp 145d \nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmovsxd r9, esi\npush rbx\nmov rbp, r9\nmov rbx, rdi\nshl r9, 2\nsub rsp, 8\ncmp ebp, 1\njle loc_1438\nmov edi, ebp\nlea r8, [rbx+4]\nnop word ptr [rax+rax+00000000h]\nloc_1310:\ncmp edi, 1\njle loc_1420\nlea edx, [rdi-2]\nmov rax, rbx\nlea rsi, [r8+rdx*4]\nnop dword ptr [rax+rax+00h]\nloc_1328:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd ecx, xmm0\nmovd edx, xmm1\ncmp ecx, edx\njle short loc_1346\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_1346:\nadd rax, 4\ncmp rax, rsi\njnz short loc_1328\nsub edi, 1\ncmp edi, 1\njnz short loc_1310\nmov rdi, r9; size\ncall _malloc\nmov ecx, [rbx]\nmov rdi, rax; ptr\nmov [rax], ecx\ncmp ebp, 3\njle loc_144E\nlea eax, [rbp-4]\nmov edx, 1\nshr eax, 1\nlea esi, [rax+rax]\nmov eax, 3\nadd rsi, 5\njmp short loc_138A\nloc_1387:\nmov rax, r8\nloc_138A:\nmov r8d, [rbx+rax*4-8]\ncmp r8d, ecx\njz short loc_139E\nmovsxd rcx, edx\nadd edx, 1\nmov [rdi+rcx*4], r8d\nloc_139E:\nmov ecx, [rbx+rax*4-4]\ncmp r8d, ecx\njz short loc_13B1\nmovsxd r8, edx\nadd edx, 1\nmov [rdi+r8*4], ecx\nloc_13B1:\nlea r8, [rax+2]\ncmp rsi, r8\njnz short loc_1387\nloc_13BA:\ncdqe\nnop dword ptr [rax+00h]\nloc_13C0:\nmov ecx, [rbx+rax*4]\ncmp [rbx+rax*4-4], ecx\njz short loc_13D2\nmovsxd rsi, edx\nadd edx, 1\nmov [rdi+rsi*4], ecx\nloc_13D2:\nadd rax, 1\ncmp ebp, eax\njg short loc_13C0\ntest edx, edx\njle short loc_1428\nloc_13DE:\nxor eax, eax\nxor ecx, ecx\nxor ebx, ebx\nnop dword ptr [rax+00h]\nloc_13E8:\ntest rax, rax\njz short loc_13FC\nmov esi, [rdi+rax*4-4]\nadd ecx, 1\nadd esi, 1\ncmp [rdi+rax*4], esi\njz short loc_1401\nloc_13FC:\nmov ecx, 1\nloc_1401:\ncmp ebx, ecx\ncmovl ebx, ecx\nadd rax, 1\ncmp edx, eax\njg short loc_13E8\ncall _free\nadd rsp, 8\nmov eax, ebx\npop rbx\npop rbp\nretn\nloc_1420:\nsub edi, 1; ptr\njmp loc_1310\nloc_1428:\ncall _free\nxor ebx, ebx\nadd rsp, 8\nmov eax, ebx\npop rbx\npop rbp\nretn\nloc_1438:\nmov rdi, r9; size\ncall _malloc\nmov edx, 1\nmov rdi, rax\nmov eax, [rbx]\nmov [rdi], eax\njmp short loc_13DE\nloc_144E:\nmov edx, 1\nmov eax, 1\njmp loc_13BA", + "ida_pseudo": "__int64 __fastcall func0(__m128i *a1, int a2)\n{\n int i; // edi\n __m128i *v5; // rax\n __m128i v6; // xmm0\n _DWORD *v7; // rax\n __int32 v8; // ecx\n _DWORD *v9; // rdi\n int v10; // edx\n __int64 j; // rax\n __int32 v12; // r8d\n __int64 v13; // rcx\n __int64 v14; // r8\n __int32 v15; // ecx\n __int64 v16; // rsi\n __int64 v17; // rax\n int v18; // ecx\n int v19; // ebx\n _DWORD *v21; // rax\n\n if ( a2 <= 1 )\n {\n v21 = malloc(4LL * a2);\n v10 = 1;\n v9 = v21;\n *v21 = a1->m128i_i32[0];\n }\n else\n {\n for ( i = a2; i != 1; --i )\n {\n while ( i <= 1 )\n --i;\n v5 = a1;\n do\n {\n v6 = _mm_loadl_epi64(v5);\n if ( _mm_cvtsi128_si32(v6) > _mm_cvtsi128_si32(_mm_shuffle_epi32(v6, 229)) )\n v5->m128i_i64[0] = _mm_shuffle_epi32(v6, 225).m128i_u64[0];\n v5 = (__m128i *)((char *)v5 + 4);\n }\n while ( v5 != (__m128i *)((char *)a1->m128i_i64 + 4 * (unsigned int)(i - 2) + 4) );\n }\n v7 = malloc(4LL * a2);\n v8 = a1->m128i_i32[0];\n v9 = v7;\n *v7 = a1->m128i_i32[0];\n if ( a2 <= 3 )\n {\n v10 = 1;\n LODWORD(j) = 1;\n }\n else\n {\n v10 = 1;\n for ( j = 3LL; ; j += 2LL )\n {\n v12 = a1->m128i_i32[j - 2];\n if ( v12 != v8 )\n {\n v13 = v10++;\n v9[v13] = v12;\n }\n v8 = a1->m128i_i32[j - 1];\n if ( v12 != v8 )\n {\n v14 = v10++;\n v9[v14] = v8;\n }\n if ( 2 * ((unsigned int)(a2 - 4) >> 1) + 5LL == j + 2 )\n break;\n }\n }\n j = (int)j;\n do\n {\n v15 = a1->m128i_i32[j];\n if ( a1->m128i_i32[j - 1] != v15 )\n {\n v16 = v10++;\n v9[v16] = v15;\n }\n ++j;\n }\n while ( a2 > (int)j );\n if ( v10 <= 0 )\n {\n free(v9);\n return 0LL;\n }\n }\n v17 = 0LL;\n v18 = 0;\n v19 = 0;\n do\n {\n if ( !v17 || (++v18, v9[v17] != v9[v17 - 1] + 1) )\n v18 = 1;\n if ( v19 < v18 )\n v19 = v18;\n ++v17;\n }\n while ( v10 > (int)v17 );\n free(v9);\n return (unsigned int)v19;\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\npush rbp\nmovsxd r9, esi\npush rbx\nmov rbp, r9\nmov rbx, rdi\nshl r9, 2\nsub rsp, 8\ncmp ebp, 1\njle loc_1438\nmov edi, ebp\nlea r8, [rbx+4]\nnop word ptr [rax+rax+00000000h]\nloc_1310:\ncmp edi, 1\njle loc_1420\nlea edx, [rdi-2]\nmov rax, rbx\nlea rsi, [r8+rdx*4]\nnop dword ptr [rax+rax+00h]\nloc_1328:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd ecx, xmm0\nmovd edx, xmm1\ncmp ecx, edx\njle short loc_1346\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_1346:\nadd rax, 4\ncmp rax, rsi\njnz short loc_1328\nsub edi, 1\ncmp edi, 1\njnz short loc_1310\nmov rdi, r9; size\ncall _malloc\nmov ecx, [rbx]\nmov rdi, rax; ptr\nmov [rax], ecx\ncmp ebp, 3\njle loc_144E\nlea eax, [rbp-4]\nmov edx, 1\nshr eax, 1\nlea esi, [rax+rax]\nmov eax, 3\nadd rsi, 5\njmp short loc_138A\nloc_1387:\nmov rax, r8\nloc_138A:\nmov r8d, [rbx+rax*4-8]\ncmp r8d, ecx\njz short loc_139E\nmovsxd rcx, edx\nadd edx, 1\nmov [rdi+rcx*4], r8d\nloc_139E:\nmov ecx, [rbx+rax*4-4]\ncmp r8d, ecx\njz short loc_13B1\nmovsxd r8, edx\nadd edx, 1\nmov [rdi+r8*4], ecx\nloc_13B1:\nlea r8, [rax+2]\ncmp rsi, r8\njnz short loc_1387\nloc_13BA:\ncdqe\nnop dword ptr [rax+00h]\nloc_13C0:\nmov ecx, [rbx+rax*4]\ncmp [rbx+rax*4-4], ecx\njz short loc_13D2\nmovsxd rsi, edx\nadd edx, 1\nmov [rdi+rsi*4], ecx\nloc_13D2:\nadd rax, 1\ncmp ebp, eax\njg short loc_13C0\ntest edx, edx\njle short loc_1428\nloc_13DE:\nxor eax, eax\nxor ecx, ecx\nxor ebx, ebx\nnop dword ptr [rax+00h]\nloc_13E8:\ntest rax, rax\njz short loc_13FC\nmov esi, [rdi+rax*4-4]\nadd ecx, 1\nadd esi, 1\ncmp [rdi+rax*4], esi\njz short loc_1401\nloc_13FC:\nmov ecx, 1\nloc_1401:\ncmp ebx, ecx\ncmovl ebx, ecx\nadd rax, 1\ncmp edx, eax\njg short loc_13E8\ncall _free\nadd rsp, 8\nmov eax, ebx\npop rbx\npop rbp\nretn\nloc_1420:\nsub edi, 1; ptr\njmp loc_1310\nloc_1428:\ncall _free\nxor ebx, ebx\nadd rsp, 8\nmov eax, ebx\npop rbx\npop rbp\nretn\nloc_1438:\nmov rdi, r9; size\ncall _malloc\nmov edx, 1\nmov rdi, rax\nmov eax, [rbx]\nmov [rdi], eax\njmp short loc_13DE\nloc_144E:\nmov edx, 1\nmov eax, 1\njmp loc_13BA", + "ida_strip_pseudo": "__int64 __fastcall sub_12E0(__m128i *a1, int a2)\n{\n int i; // edi\n __m128i *v5; // rax\n __m128i v6; // xmm0\n _DWORD *v7; // rax\n __int32 v8; // ecx\n _DWORD *v9; // rdi\n int v10; // edx\n __int64 j; // rax\n __int32 v12; // r8d\n __int64 v13; // rcx\n __int64 v14; // r8\n __int32 v15; // ecx\n __int64 v16; // rsi\n __int64 v17; // rax\n int v18; // ecx\n int v19; // ebx\n _DWORD *v21; // rax\n\n if ( a2 <= 1 )\n {\n v21 = malloc(4LL * a2);\n v10 = 1;\n v9 = v21;\n *v21 = a1->m128i_i32[0];\n }\n else\n {\n for ( i = a2; i != 1; --i )\n {\n while ( i <= 1 )\n --i;\n v5 = a1;\n do\n {\n v6 = _mm_loadl_epi64(v5);\n if ( _mm_cvtsi128_si32(v6) > _mm_cvtsi128_si32(_mm_shuffle_epi32(v6, 229)) )\n v5->m128i_i64[0] = _mm_shuffle_epi32(v6, 225).m128i_u64[0];\n v5 = (__m128i *)((char *)v5 + 4);\n }\n while ( v5 != (__m128i *)((char *)a1->m128i_i64 + 4 * (unsigned int)(i - 2) + 4) );\n }\n v7 = malloc(4LL * a2);\n v8 = a1->m128i_i32[0];\n v9 = v7;\n *v7 = a1->m128i_i32[0];\n if ( a2 <= 3 )\n {\n v10 = 1;\n LODWORD(j) = 1;\n }\n else\n {\n v10 = 1;\n for ( j = 3LL; ; j += 2LL )\n {\n v12 = a1->m128i_i32[j - 2];\n if ( v12 != v8 )\n {\n v13 = v10++;\n v9[v13] = v12;\n }\n v8 = a1->m128i_i32[j - 1];\n if ( v12 != v8 )\n {\n v14 = v10++;\n v9[v14] = v8;\n }\n if ( 2 * ((unsigned int)(a2 - 4) >> 1) + 5LL == j + 2 )\n break;\n }\n }\n j = (int)j;\n do\n {\n v15 = a1->m128i_i32[j];\n if ( a1->m128i_i32[j - 1] != v15 )\n {\n v16 = v10++;\n v9[v16] = v15;\n }\n ++j;\n }\n while ( a2 > (int)j );\n if ( v10 <= 0 )\n {\n free(v9);\n return 0LL;\n }\n }\n v17 = 0LL;\n v18 = 0;\n v19 = 0;\n do\n {\n if ( !v17 || (++v18, v9[v17] != v9[v17 - 1] + 1) )\n v18 = 1;\n if ( v19 < v18 )\n v19 = v18;\n ++v17;\n }\n while ( v10 > (int)v17 );\n free(v9);\n return (unsigned int)v19;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12E0(__m128i *a1, int a2) {\n int i;\n __m128i *v5;\n __m128i v6;\n uint32_t *v7;\n int v8;\n uint32_t *v9;\n int v10;\n long long j;\n int v12;\n long long v13;\n long long v14;\n int v15;\n long long v16;\n long long v17;\n int v18;\n int v19;\n uint32_t *v21;\n if (a2 <= 1) {\n v21 = malloc(4LL * a2);\n v10 = 1;\n v9 = v21;\n *v21 = a1->m128i_i32[0];\n } else {\n for (i = a2; i != 1; --i) {\n while (i <= 1) --i;\n v5 = a1;\n do {\n v6 = _mm_loadl_epi64(v5);\n if (_mm_cvtsi128_si32(v6) >\n _mm_cvtsi128_si32(_mm_shuffle_epi32(v6, 229)))\n v5->m128i_i64[0] = _mm_shuffle_epi32(v6, 225).m128i_u64[0];\n v5 = (__m128i *)((char *)v5 + 4);\n } while (v5 != (__m128i *)((char *)a1->m128i_i64 +\n 4 * (unsigned int)(i - 2) + 4));\n }\n v7 = malloc(4LL * a2);\n v8 = a1->m128i_i32[0];\n v9 = v7;\n *v7 = a1->m128i_i32[0];\n if (a2 <= 3) {\n v10 = 1;\n LODWORD(j) = 1;\n } else {\n v10 = 1;\n for (j = 3LL;; j += 2LL) {\n v12 = a1->m128i_i32[j - 2];\n if (v12 != v8) {\n v13 = v10++;\n v9[v13] = v12;\n }\n v8 = a1->m128i_i32[j - 1];\n if (v12 != v8) {\n v14 = v10++;\n v9[v14] = v8;\n }\n if (2 * ((unsigned int)(a2 - 4) >> 1) + 5LL == j + 2) break;\n }\n }\n j = (int)j;\n do {\n v15 = a1->m128i_i32[j];\n if (a1->m128i_i32[j - 1] != v15) {\n v16 = v10++;\n v9[v16] = v15;\n }\n ++j;\n } while (a2 > (int)j);\n if (v10 <= 0) {\n free(v9);\n return 0LL;\n }\n }\n v17 = 0LL;\n v18 = 0;\n v19 = 0;\n do {\n if (!v17 || (++v18, v9[v17] != v9[v17 - 1] + 1)) v18 = 1;\n if (v19 < v18) v19 = v18;\n ++v17;\n } while (v10 > (int)v17);\n free(v9);\n return (unsigned int)v19;\n}", + "ida_pseudo_norm": "long long func0(__m128i *a1, int a2) {\n int i;\n __m128i *v5;\n __m128i v6;\n uint32_t *v7;\n int v8;\n uint32_t *v9;\n int v10;\n long long j;\n int v12;\n long long v13;\n long long v14;\n int v15;\n long long v16;\n long long v17;\n int v18;\n int v19;\n uint32_t *v21;\n if (a2 <= 1) {\n v21 = malloc(4LL * a2);\n v10 = 1;\n v9 = v21;\n *v21 = a1->m128i_i32[0];\n } else {\n for (i = a2; i != 1; --i) {\n while (i <= 1) --i;\n v5 = a1;\n do {\n v6 = _mm_loadl_epi64(v5);\n if (_mm_cvtsi128_si32(v6) >\n _mm_cvtsi128_si32(_mm_shuffle_epi32(v6, 229)))\n v5->m128i_i64[0] = _mm_shuffle_epi32(v6, 225).m128i_u64[0];\n v5 = (__m128i *)((char *)v5 + 4);\n } while (v5 != (__m128i *)((char *)a1->m128i_i64 +\n 4 * (unsigned int)(i - 2) + 4));\n }\n v7 = malloc(4LL * a2);\n v8 = a1->m128i_i32[0];\n v9 = v7;\n *v7 = a1->m128i_i32[0];\n if (a2 <= 3) {\n v10 = 1;\n LODWORD(j) = 1;\n } else {\n v10 = 1;\n for (j = 3LL;; j += 2LL) {\n v12 = a1->m128i_i32[j - 2];\n if (v12 != v8) {\n v13 = v10++;\n v9[v13] = v12;\n }\n v8 = a1->m128i_i32[j - 1];\n if (v12 != v8) {\n v14 = v10++;\n v9[v14] = v8;\n }\n if (2 * ((unsigned int)(a2 - 4) >> 1) + 5LL == j + 2) break;\n }\n }\n j = (int)j;\n do {\n v15 = a1->m128i_i32[j];\n if (a1->m128i_i32[j - 1] != v15) {\n v16 = v10++;\n v9[v16] = v15;\n }\n ++j;\n } while (a2 > (int)j);\n if (v10 <= 0) {\n free(v9);\n return 0LL;\n }\n }\n v17 = 0LL;\n v18 = 0;\n v19 = 0;\n do {\n if (!v17 || (++v18, v9[v17] != v9[v17 - 1] + 1)) v18 = 1;\n if (v19 < v18) v19 = v18;\n ++v17;\n } while (v10 > (int)v17);\n free(v9);\n return (unsigned int)v19;\n}" + }, + { + "index": 864, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\nbool is_palindrome(const char* text) {\n\n int length = strlen(text);\n\n for (int i = 0; i < length / 2; i++) {\n\n if (text[i] != text[length - 1 - i]) {\n\n return false;\n\n }\n\n }\n\n return true;\n\n}\n\n\n\n", + "func": "int func0(const char* texts[], int size, const char* result[]) {\n int count = 0;\n for (int i = 0; i < size; i++) {\n if (is_palindrome(texts[i])) {\n result[count++] = texts[i];\n }\n }\n return count;\n}", + "test": "int main() {\n\n const char* input1[] = {\"php\", \"res\", \"Python\", \"abcd\", \"Java\", \"aaa\"};\n\n const char* expected1[] = {\"php\", \"aaa\"};\n\n const char* results1[6];\n\n int count1 = func0(input1, 6, results1);\n\n assert(count1 == 2);\n\n for (int i = 0; i < count1; i++) {\n\n assert(strcmp(results1[i], expected1[i]) == 0);\n\n }\n\n\n\n const char* input2[] = {\"abcd\", \"Python\", \"abba\", \"aba\"};\n\n const char* expected2[] = {\"abba\", \"aba\"};\n\n const char* results2[4];\n\n int count2 = func0(input2, 4, results2);\n\n assert(count2 == 2);\n\n for (int i = 0; i < count2; i++) {\n\n assert(strcmp(results2[i], expected2[i]) == 0);\n\n }\n\n\n\n const char* input3[] = {\"abcd\", \"abbccbba\", \"abba\", \"aba\"};\n\n const char* expected3[] = {\"abbccbba\", \"abba\", \"aba\"};\n\n const char* results3[4];\n\n int count3 = func0(input3, 4, results3);\n\n assert(count3 == 3);\n\n for (int i = 0; i < count3; i++) {\n\n assert(strcmp(results3[i], expected3[i]) == 0);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 12a1 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov %rax,%rdi\ncallq 11a9 \ntest %al,%al\nje 129d \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x8(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x8(%rbp)\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x28(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%rax\nmov %rax,(%rdx)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1245 \nmov -0x8(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_12A1\nloc_1245:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax\ncall is_palindrome\ntest al, al\njz short loc_129D\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_8]\nlea edx, [rax+1]\nmov [rbp+var_8], edx\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov rax, [rcx]\nmov [rdx], rax\nloc_129D:\nadd [rbp+var_4], 1\nloc_12A1:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1245\nmov eax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3)\n{\n int v3; // eax\n unsigned int v6; // [rsp+28h] [rbp-8h]\n int i; // [rsp+2Ch] [rbp-4h]\n\n v6 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( (unsigned __int8)is_palindrome(*(_QWORD *)(8LL * i + a1)) )\n {\n v3 = v6++;\n *(_QWORD *)(a3 + 8LL * v3) = *(_QWORD *)(8LL * i + a1);\n }\n }\n return v6;\n}", + "ida_strip_asm": "sub_121E:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_12A1\nloc_1245:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax\ncall sub_11A9\ntest al, al\njz short loc_129D\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_8]\nlea edx, [rax+1]\nmov [rbp+var_8], edx\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov rax, [rcx]\nmov [rdx], rax\nloc_129D:\nadd [rbp+var_4], 1\nloc_12A1:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1245\nmov eax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_121E(__int64 a1, int a2, __int64 a3)\n{\n int v3; // eax\n unsigned int v6; // [rsp+28h] [rbp-8h]\n int i; // [rsp+2Ch] [rbp-4h]\n\n v6 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( (unsigned __int8)sub_11A9(*(_QWORD *)(8LL * i + a1)) )\n {\n v3 = v6++;\n *(_QWORD *)(a3 + 8LL * v3) = *(_QWORD *)(8LL * i + a1);\n }\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_121E(long long a1, int a2, long long a3) {\n int v3;\n unsigned int v6;\n int i;\n v6 = 0;\n for (i = 0; i < a2; ++i) {\n if ((unsigned char)sub_11A9(*(uint64_t *)(8LL * i + a1))) {\n v3 = v6++;\n *(uint64_t *)(a3 + 8LL * v3) = *(uint64_t *)(8LL * i + a1);\n }\n }\n return v6;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3) {\n int v3;\n unsigned int v6;\n int i;\n v6 = 0;\n for (i = 0; i < a2; ++i) {\n if ((unsigned char)is_palindrome(*(uint64_t *)(8LL * i + a1))) {\n v3 = v6++;\n *(uint64_t *)(a3 + 8LL * v3) = *(uint64_t *)(8LL * i + a1);\n }\n }\n return v6;\n}" + }, + { + "index": 864, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\nbool is_palindrome(const char* text) {\n\n int length = strlen(text);\n\n for (int i = 0; i < length / 2; i++) {\n\n if (text[i] != text[length - 1 - i]) {\n\n return false;\n\n }\n\n }\n\n return true;\n\n}\n\n\n\n", + "func": "int func0(const char* texts[], int size, const char* result[]) {\n int count = 0;\n for (int i = 0; i < size; i++) {\n if (is_palindrome(texts[i])) {\n result[count++] = texts[i];\n }\n }\n return count;\n}", + "test": "int main() {\n\n const char* input1[] = {\"php\", \"res\", \"Python\", \"abcd\", \"Java\", \"aaa\"};\n\n const char* expected1[] = {\"php\", \"aaa\"};\n\n const char* results1[6];\n\n int count1 = func0(input1, 6, results1);\n\n assert(count1 == 2);\n\n for (int i = 0; i < count1; i++) {\n\n assert(strcmp(results1[i], expected1[i]) == 0);\n\n }\n\n\n\n const char* input2[] = {\"abcd\", \"Python\", \"abba\", \"aba\"};\n\n const char* expected2[] = {\"abba\", \"aba\"};\n\n const char* results2[4];\n\n int count2 = func0(input2, 4, results2);\n\n assert(count2 == 2);\n\n for (int i = 0; i < count2; i++) {\n\n assert(strcmp(results2[i], expected2[i]) == 0);\n\n }\n\n\n\n const char* input3[] = {\"abcd\", \"abbccbba\", \"abba\", \"aba\"};\n\n const char* expected3[] = {\"abbccbba\", \"abba\", \"aba\"};\n\n const char* results3[4];\n\n int count3 = func0(input3, 4, results3);\n\n assert(count3 == 3);\n\n for (int i = 0; i < count3; i++) {\n\n assert(strcmp(results3[i], expected3[i]) == 0);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\ntest %esi,%esi\njle 1235 \nmov %rdx,%r14\nmov %rdi,%rbx\nlea -0x1(%rsi),%eax\nlea 0x8(%rdi,%rax,8),%r13\nmov $0x0,%r12d\njmp 1218 \nadd $0x8,%rbx\ncmp %r13,%rbx\nje 123b \nmov (%rbx),%rbp\nmov %rbp,%rdi\ncallq 1189 \ntest %al,%al\nje 120f \nmovslq %r12d,%rax\nmov %rbp,(%r14,%rax,8)\nlea 0x1(%r12),%r12d\njmp 120f \nmov $0x0,%r12d\nmov %r12d,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\ntest esi, esi\njle short loc_1245\nmov r14, rdx\nmov rbx, rdi\nmovsxd rsi, esi\nlea r13, [rdi+rsi*8]\nmov r12d, 0\njmp short loc_1228\nloc_121F:\nadd rbx, 8\ncmp rbx, r13\njz short loc_124B\nloc_1228:\nmov rbp, [rbx]\nmov rdi, rbp\ncall is_palindrome\ntest al, al\njz short loc_121F\nmovsxd rax, r12d\nmov [r14+rax*8], rbp\nlea r12d, [r12+1]\njmp short loc_121F\nloc_1245:\nmov r12d, 0\nloc_124B:\nmov eax, r12d\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "__int64 __fastcall func0(_QWORD *a1, int a2, __int64 a3)\n{\n _QWORD *v4; // rbx\n unsigned int v5; // r12d\n __int64 v6; // rbp\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v4 = a1;\n v5 = 0;\n do\n {\n v6 = *v4;\n if ( (unsigned __int8)is_palindrome(*v4) )\n *(_QWORD *)(a3 + 8LL * (int)v5++) = v6;\n ++v4;\n }\n while ( v4 != &a1[a2] );\n }\n return v5;\n}", + "ida_strip_asm": "sub_11FA:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\ntest esi, esi\njle short loc_1245\nmov r14, rdx\nmov rbx, rdi\nmovsxd rsi, esi\nlea r13, [rdi+rsi*8]\nmov r12d, 0\njmp short loc_1228\nloc_121F:\nadd rbx, 8\ncmp rbx, r13\njz short loc_124B\nloc_1228:\nmov rbp, [rbx]\nmov rdi, rbp\ncall sub_11A9\ntest al, al\njz short loc_121F\nmovsxd rax, r12d\nmov [r14+rax*8], rbp\nlea r12d, [r12+1]\njmp short loc_121F\nloc_1245:\nmov r12d, 0\nloc_124B:\nmov eax, r12d\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11FA(_QWORD *a1, int a2, __int64 a3)\n{\n _QWORD *v4; // rbx\n unsigned int v5; // r12d\n __int64 v6; // rbp\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v4 = a1;\n v5 = 0;\n do\n {\n v6 = *v4;\n if ( (unsigned __int8)sub_11A9(*v4) )\n *(_QWORD *)(a3 + 8LL * (int)v5++) = v6;\n ++v4;\n }\n while ( v4 != &a1[a2] );\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11FA(uint64_t *a1, int a2, long long a3) {\n uint64_t *v4;\n unsigned int v5;\n long long v6;\n if (a2 <= 0) {\n return 0;\n } else {\n v4 = a1;\n v5 = 0;\n do {\n v6 = *v4;\n if ((unsigned char)sub_11A9(*v4))\n *(uint64_t *)(a3 + 8LL * (int)v5++) = v6;\n ++v4;\n } while (v4 != &a1[a2]);\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(uint64_t *a1, int a2, long long a3) {\n uint64_t *v4;\n unsigned int v5;\n long long v6;\n if (a2 <= 0) {\n return 0;\n } else {\n v4 = a1;\n v5 = 0;\n do {\n v6 = *v4;\n if ((unsigned char)is_palindrome(*v4))\n *(uint64_t *)(a3 + 8LL * (int)v5++) = v6;\n ++v4;\n } while (v4 != &a1[a2]);\n }\n return v5;\n}" + }, + { + "index": 864, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\nbool is_palindrome(const char* text) {\n\n int length = strlen(text);\n\n for (int i = 0; i < length / 2; i++) {\n\n if (text[i] != text[length - 1 - i]) {\n\n return false;\n\n }\n\n }\n\n return true;\n\n}\n\n\n\n", + "func": "int func0(const char* texts[], int size, const char* result[]) {\n int count = 0;\n for (int i = 0; i < size; i++) {\n if (is_palindrome(texts[i])) {\n result[count++] = texts[i];\n }\n }\n return count;\n}", + "test": "int main() {\n\n const char* input1[] = {\"php\", \"res\", \"Python\", \"abcd\", \"Java\", \"aaa\"};\n\n const char* expected1[] = {\"php\", \"aaa\"};\n\n const char* results1[6];\n\n int count1 = func0(input1, 6, results1);\n\n assert(count1 == 2);\n\n for (int i = 0; i < count1; i++) {\n\n assert(strcmp(results1[i], expected1[i]) == 0);\n\n }\n\n\n\n const char* input2[] = {\"abcd\", \"Python\", \"abba\", \"aba\"};\n\n const char* expected2[] = {\"abba\", \"aba\"};\n\n const char* results2[4];\n\n int count2 = func0(input2, 4, results2);\n\n assert(count2 == 2);\n\n for (int i = 0; i < count2; i++) {\n\n assert(strcmp(results2[i], expected2[i]) == 0);\n\n }\n\n\n\n const char* input3[] = {\"abcd\", \"abbccbba\", \"abba\", \"aba\"};\n\n const char* expected3[] = {\"abbccbba\", \"abba\", \"aba\"};\n\n const char* results3[4];\n\n int count3 = func0(input3, 4, results3);\n\n assert(count3 == 3);\n\n for (int i = 0; i < count3; i++) {\n\n assert(strcmp(results3[i], expected3[i]) == 0);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\ntest %esi,%esi\njle 1530 \nlea -0x1(%rsi),%eax\nmov %rdx,%r13\nmov %rdi,%rbx\nxor %r12d,%r12d\nlea 0x8(%rdi,%rax,8),%r14\nnopl 0x0(%rax)\nmov (%rbx),%rbp\nmov %rbp,%rdi\ncallq 1470 \ntest %al,%al\nje 1513 \nmovslq %r12d,%rax\nadd $0x1,%r12d\nmov %rbp,0x0(%r13,%rax,8)\nadd $0x8,%rbx\ncmp %r14,%rbx\njne 14f8 \npop %rbx\nmov %r12d,%eax\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopl 0x0(%rax,%rax,1)\nxor %r12d,%r12d\npop %rbx\npop %rbp\nmov %r12d,%eax\npop %r12\npop %r13\npop %r14\nretq\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\ntest esi, esi\njle loc_15A5\nmovsxd rsi, esi\nmov r12, rdx\nmov r13, rdi\nxor ebx, ebx\nlea rbp, [rdi+rsi*8]\nnop dword ptr [rax+rax+00h]\nloc_1538:\nmov r14, [r13+0]\nmov rdi, r14; s\ncall _strlen\nmov ecx, eax\nshr ecx, 1Fh\nadd ecx, eax\nsar ecx, 1\ncmp eax, 1\njle short loc_1590\nsub eax, 1\nxor edx, edx\ncdqe\nadd rax, r14\njmp short loc_156C\nloc_1560:\nadd rdx, 1\nsub rax, 1\ncmp ecx, edx\njle short loc_1590\nloc_156C:\nmovzx esi, byte ptr [rax]\ncmp [r14+rdx], sil\njz short loc_1560\nadd r13, 8\ncmp r13, rbp\njnz short loc_1538\nloc_157E:\nmov eax, ebx\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1590:\nmovsxd rax, ebx\nadd r13, 8\nadd ebx, 1\nmov [r12+rax*8], r14\ncmp r13, rbp\njnz short loc_1538\njmp short loc_157E\nloc_15A5:\nxor ebx, ebx\nmov eax, ebx\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char **a1, int a2, __int64 a3)\n{\n const char **v4; // r13\n unsigned int v5; // ebx\n const char **v6; // rbp\n const char *v7; // r14\n int v8; // eax\n int v9; // ecx\n __int64 v10; // rdx\n const char *v11; // rax\n __int64 v13; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v4 = a1;\n v5 = 0;\n v6 = &a1[a2];\n do\n {\n while ( 1 )\n {\n v7 = *v4;\n v8 = strlen(*v4);\n v9 = v8 / 2;\n if ( v8 > 1 )\n break;\nLABEL_9:\n v13 = (int)v5;\n ++v4;\n ++v5;\n *(_QWORD *)(a3 + 8 * v13) = v7;\n if ( v4 == v6 )\n return v5;\n }\n v10 = 0LL;\n v11 = &v7[v8 - 1];\n while ( v7[v10] == *v11 )\n {\n ++v10;\n --v11;\n if ( v9 <= (int)v10 )\n goto LABEL_9;\n }\n ++v4;\n }\n while ( v4 != v6 );\n return v5;\n}", + "ida_strip_asm": "sub_1510:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\ntest esi, esi\njle loc_15A5\nmovsxd rsi, esi\nmov r12, rdx\nmov r13, rdi\nxor ebx, ebx\nlea rbp, [rdi+rsi*8]\nnop dword ptr [rax+rax+00h]\nloc_1538:\nmov r14, [r13+0]\nmov rdi, r14; s\ncall _strlen\nmov ecx, eax\nshr ecx, 1Fh\nadd ecx, eax\nsar ecx, 1\ncmp eax, 1\njle short loc_1590\nsub eax, 1\nxor edx, edx\ncdqe\nadd rax, r14\njmp short loc_156C\nloc_1560:\nadd rdx, 1\nsub rax, 1\ncmp ecx, edx\njle short loc_1590\nloc_156C:\nmovzx esi, byte ptr [rax]\ncmp [r14+rdx], sil\njz short loc_1560\nadd r13, 8\ncmp r13, rbp\njnz short loc_1538\nloc_157E:\nmov eax, ebx\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1590:\nmovsxd rax, ebx\nadd r13, 8\nadd ebx, 1\nmov [r12+rax*8], r14\ncmp r13, rbp\njnz short loc_1538\njmp short loc_157E\nloc_15A5:\nxor ebx, ebx\nmov eax, ebx\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1510(const char **a1, int a2, __int64 a3)\n{\n const char **v4; // r13\n unsigned int v5; // ebx\n const char **v6; // rbp\n const char *v7; // r14\n int v8; // eax\n int v9; // ecx\n __int64 v10; // rdx\n const char *v11; // rax\n __int64 v13; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v4 = a1;\n v5 = 0;\n v6 = &a1[a2];\n do\n {\n while ( 1 )\n {\n v7 = *v4;\n v8 = strlen(*v4);\n v9 = v8 / 2;\n if ( v8 > 1 )\n break;\nLABEL_9:\n v13 = (int)v5;\n ++v4;\n ++v5;\n *(_QWORD *)(a3 + 8 * v13) = v7;\n if ( v4 == v6 )\n return v5;\n }\n v10 = 0LL;\n v11 = &v7[v8 - 1];\n while ( v7[v10] == *v11 )\n {\n ++v10;\n --v11;\n if ( v9 <= (int)v10 )\n goto LABEL_9;\n }\n ++v4;\n }\n while ( v4 != v6 );\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1510(const char **a1, int a2, long long a3) {\n const char **v4;\n unsigned int v5;\n const char **v6;\n const char *v7;\n int v8;\n int v9;\n long long v10;\n const char *v11;\n long long v13;\n if (a2 <= 0) return 0LL;\n v4 = a1;\n v5 = 0;\n v6 = &a1[a2];\n do {\n while (1) {\n v7 = *v4;\n v8 = strlen(*v4);\n v9 = v8 / 2;\n if (v8 > 1) break;\n LABEL_9:\n v13 = (int)v5;\n ++v4;\n ++v5;\n *(uint64_t *)(a3 + 8 * v13) = v7;\n if (v4 == v6) return v5;\n }\n v10 = 0LL;\n v11 = &v7[v8 - 1];\n while (v7[v10] == *v11) {\n ++v10;\n --v11;\n if (v9 <= (int)v10) goto LABEL_9;\n }\n ++v4;\n } while (v4 != v6);\n return v5;\n}", + "ida_pseudo_norm": "long long func0(const char **a1, int a2, long long a3) {\n const char **v4;\n unsigned int v5;\n const char **v6;\n const char *v7;\n int v8;\n int v9;\n long long v10;\n const char *v11;\n long long v13;\n if (a2 <= 0) return 0LL;\n v4 = a1;\n v5 = 0;\n v6 = &a1[a2];\n do {\n while (1) {\n v7 = *v4;\n v8 = strlen(*v4);\n v9 = v8 / 2;\n if (v8 > 1) break;\n LABEL_9:\n v13 = (int)v5;\n ++v4;\n ++v5;\n *(uint64_t *)(a3 + 8 * v13) = v7;\n if (v4 == v6) return v5;\n }\n v10 = 0LL;\n v11 = &v7[v8 - 1];\n while (v7[v10] == *v11) {\n ++v10;\n --v11;\n if (v9 <= (int)v10) goto LABEL_9;\n }\n ++v4;\n } while (v4 != v6);\n return v5;\n}" + }, + { + "index": 864, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\nbool is_palindrome(const char* text) {\n\n int length = strlen(text);\n\n for (int i = 0; i < length / 2; i++) {\n\n if (text[i] != text[length - 1 - i]) {\n\n return false;\n\n }\n\n }\n\n return true;\n\n}\n\n\n\n", + "func": "int func0(const char* texts[], int size, const char* result[]) {\n int count = 0;\n for (int i = 0; i < size; i++) {\n if (is_palindrome(texts[i])) {\n result[count++] = texts[i];\n }\n }\n return count;\n}", + "test": "int main() {\n\n const char* input1[] = {\"php\", \"res\", \"Python\", \"abcd\", \"Java\", \"aaa\"};\n\n const char* expected1[] = {\"php\", \"aaa\"};\n\n const char* results1[6];\n\n int count1 = func0(input1, 6, results1);\n\n assert(count1 == 2);\n\n for (int i = 0; i < count1; i++) {\n\n assert(strcmp(results1[i], expected1[i]) == 0);\n\n }\n\n\n\n const char* input2[] = {\"abcd\", \"Python\", \"abba\", \"aba\"};\n\n const char* expected2[] = {\"abba\", \"aba\"};\n\n const char* results2[4];\n\n int count2 = func0(input2, 4, results2);\n\n assert(count2 == 2);\n\n for (int i = 0; i < count2; i++) {\n\n assert(strcmp(results2[i], expected2[i]) == 0);\n\n }\n\n\n\n const char* input3[] = {\"abcd\", \"abbccbba\", \"abba\", \"aba\"};\n\n const char* expected3[] = {\"abbccbba\", \"abba\", \"aba\"};\n\n const char* results3[4];\n\n int count3 = func0(input3, 4, results3);\n\n assert(count3 == 3);\n\n for (int i = 0; i < count3; i++) {\n\n assert(strcmp(results3[i], expected3[i]) == 0);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\ntest %esi,%esi\njle 15a0 \nlea -0x1(%rsi),%eax\nmov %rdx,%rbp\nmov %rdi,%r13\nxor %r12d,%r12d\nlea 0x8(%rdi,%rax,8),%rbx\nnopl (%rax)\nmov 0x0(%r13),%r14\nmov %r14,%rdi\ncallq 1080 \nmov %eax,%edx\nshr $0x1f,%edx\nadd %eax,%edx\nsar %edx\ncmp $0x1,%eax\njle 1580 \nsub $0x1,%eax\nxor %ecx,%ecx\ncltq\nadd %r14,%rax\njmp 155c \nxchg %ax,%ax\nadd $0x1,%rcx\nsub $0x1,%rax\ncmp %ecx,%edx\njle 1580 \nmovzbl (%rax),%esi\ncmp %sil,(%r14,%rcx,1)\nje 1550 \nadd $0x8,%r13\ncmp %r13,%rbx\njne 1528 \npop %rbx\nmov %r12d,%eax\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopw 0x0(%rax,%rax,1)\nmovslq %r12d,%rax\nadd $0x8,%r13\nadd $0x1,%r12d\nmov %r14,0x0(%rbp,%rax,8)\ncmp %r13,%rbx\njne 1528 \njmp 156e \nnopw 0x0(%rax,%rax,1)\nxor %r12d,%r12d\npop %rbx\npop %rbp\nmov %r12d,%eax\npop %r12\npop %r13\npop %r14\nretq\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\ntest esi, esi\njle loc_1595\nmovsxd rsi, esi\nmov r12, rdx\nmov r13, rdi\nxor ebx, ebx\nlea rbp, [rdi+rsi*8]\nnop dword ptr [rax+rax+00h]\nloc_1528:\nmov r14, [r13+0]\nmov rdi, r14; s\ncall _strlen\nmov ecx, eax\nshr ecx, 1Fh\nadd ecx, eax\nsar ecx, 1\ncmp eax, 1\njle short loc_1580\nsub eax, 1\nxor edx, edx\ncdqe\nadd rax, r14\njmp short loc_155C\nloc_1550:\nadd rdx, 1\nsub rax, 1\ncmp ecx, edx\njle short loc_1580\nloc_155C:\nmovzx esi, byte ptr [rax]\ncmp [r14+rdx], sil\njz short loc_1550\nadd r13, 8\ncmp rbp, r13\njnz short loc_1528\nloc_156E:\nmov eax, ebx\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1580:\nmovsxd rax, ebx\nadd r13, 8\nadd ebx, 1\nmov [r12+rax*8], r14\ncmp rbp, r13\njnz short loc_1528\njmp short loc_156E\nloc_1595:\nxor ebx, ebx\nmov eax, ebx\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char **a1, int a2, __int64 a3)\n{\n const char **v4; // r13\n unsigned int v5; // ebx\n const char **v6; // rbp\n const char *v7; // r14\n int v8; // eax\n int v9; // ecx\n __int64 v10; // rdx\n const char *v11; // rax\n __int64 v13; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v4 = a1;\n v5 = 0;\n v6 = &a1[a2];\n do\n {\n while ( 1 )\n {\n v7 = *v4;\n v8 = strlen(*v4);\n v9 = v8 / 2;\n if ( v8 > 1 )\n break;\nLABEL_9:\n v13 = (int)v5;\n ++v4;\n ++v5;\n *(_QWORD *)(a3 + 8 * v13) = v7;\n if ( v6 == v4 )\n return v5;\n }\n v10 = 0LL;\n v11 = &v7[v8 - 1];\n while ( v7[v10] == *v11 )\n {\n ++v10;\n --v11;\n if ( v9 <= (int)v10 )\n goto LABEL_9;\n }\n ++v4;\n }\n while ( v6 != v4 );\n return v5;\n}", + "ida_strip_asm": "sub_1500:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\ntest esi, esi\njle loc_1595\nmovsxd rsi, esi\nmov r12, rdx\nmov r13, rdi\nxor ebx, ebx\nlea rbp, [rdi+rsi*8]\nnop dword ptr [rax+rax+00h]\nloc_1528:\nmov r14, [r13+0]\nmov rdi, r14; s\ncall _strlen\nmov ecx, eax\nshr ecx, 1Fh\nadd ecx, eax\nsar ecx, 1\ncmp eax, 1\njle short loc_1580\nsub eax, 1\nxor edx, edx\ncdqe\nadd rax, r14\njmp short loc_155C\nloc_1550:\nadd rdx, 1\nsub rax, 1\ncmp ecx, edx\njle short loc_1580\nloc_155C:\nmovzx esi, byte ptr [rax]\ncmp [r14+rdx], sil\njz short loc_1550\nadd r13, 8\ncmp rbp, r13\njnz short loc_1528\nloc_156E:\nmov eax, ebx\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1580:\nmovsxd rax, ebx\nadd r13, 8\nadd ebx, 1\nmov [r12+rax*8], r14\ncmp rbp, r13\njnz short loc_1528\njmp short loc_156E\nloc_1595:\nxor ebx, ebx\nmov eax, ebx\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1500(const char **a1, int a2, __int64 a3)\n{\n const char **v4; // r13\n unsigned int v5; // ebx\n const char **v6; // rbp\n const char *v7; // r14\n int v8; // eax\n int v9; // ecx\n __int64 v10; // rdx\n const char *v11; // rax\n __int64 v13; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n v4 = a1;\n v5 = 0;\n v6 = &a1[a2];\n do\n {\n while ( 1 )\n {\n v7 = *v4;\n v8 = strlen(*v4);\n v9 = v8 / 2;\n if ( v8 > 1 )\n break;\nLABEL_9:\n v13 = (int)v5;\n ++v4;\n ++v5;\n *(_QWORD *)(a3 + 8 * v13) = v7;\n if ( v6 == v4 )\n return v5;\n }\n v10 = 0LL;\n v11 = &v7[v8 - 1];\n while ( v7[v10] == *v11 )\n {\n ++v10;\n --v11;\n if ( v9 <= (int)v10 )\n goto LABEL_9;\n }\n ++v4;\n }\n while ( v6 != v4 );\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1500(const char **a1, int a2, long long a3) {\n const char **v4;\n unsigned int v5;\n const char **v6;\n const char *v7;\n int v8;\n int v9;\n long long v10;\n const char *v11;\n long long v13;\n if (a2 <= 0) return 0LL;\n v4 = a1;\n v5 = 0;\n v6 = &a1[a2];\n do {\n while (1) {\n v7 = *v4;\n v8 = strlen(*v4);\n v9 = v8 / 2;\n if (v8 > 1) break;\n LABEL_9:\n v13 = (int)v5;\n ++v4;\n ++v5;\n *(uint64_t *)(a3 + 8 * v13) = v7;\n if (v6 == v4) return v5;\n }\n v10 = 0LL;\n v11 = &v7[v8 - 1];\n while (v7[v10] == *v11) {\n ++v10;\n --v11;\n if (v9 <= (int)v10) goto LABEL_9;\n }\n ++v4;\n } while (v6 != v4);\n return v5;\n}", + "ida_pseudo_norm": "long long func0(const char **a1, int a2, long long a3) {\n const char **v4;\n unsigned int v5;\n const char **v6;\n const char *v7;\n int v8;\n int v9;\n long long v10;\n const char *v11;\n long long v13;\n if (a2 <= 0) return 0LL;\n v4 = a1;\n v5 = 0;\n v6 = &a1[a2];\n do {\n while (1) {\n v7 = *v4;\n v8 = strlen(*v4);\n v9 = v8 / 2;\n if (v8 > 1) break;\n LABEL_9:\n v13 = (int)v5;\n ++v4;\n ++v5;\n *(uint64_t *)(a3 + 8 * v13) = v7;\n if (v6 == v4) return v5;\n }\n v10 = 0LL;\n v11 = &v7[v8 - 1];\n while (v7[v10] == *v11) {\n ++v10;\n --v11;\n if (v9 <= (int)v10) goto LABEL_9;\n }\n ++v4;\n } while (v6 != v4);\n return v5;\n}" + }, + { + "index": 865, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int nums[], int n, int size, int result[]) {\n for (int i = 0; i < size; i++) {\n result[i] = n * nums[i];\n }\n}", + "test": "int main() {\n\n int nums1[] = {1, 2, 3, 4, 5, 6, 7};\n\n int size1 = sizeof(nums1) / sizeof(nums1[0]);\n\n int result1[7];\n\n func0(nums1, 3, size1, result1);\n\n int expected1[] = {3, 6, 9, 12, 15, 18, 21};\n\n for (int i = 0; i < size1; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n\n\n int nums2[] = {1, 2, 3, 4, 5, 6, 7};\n\n int size2 = sizeof(nums2) / sizeof(nums2[0]);\n\n int result2[7];\n\n func0(nums2, 4, size2, result2);\n\n int expected2[] = {4, 8, 12, 16, 20, 24, 28};\n\n for (int i = 0; i < size2; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n\n\n int nums3[] = {1, 2, 3, 4, 5, 6, 7};\n\n int size3 = sizeof(nums3) / sizeof(nums3[0]);\n\n int result3[7];\n\n func0(nums3, 10, size3, result3);\n\n int expected3[] = {10, 20, 30, 40, 50, 60, 70};\n\n for (int i = 0; i < size3; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmov %rcx,-0x28(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11bd \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov -0x4(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x28(%rbp),%rdx\nadd %rcx,%rdx\nimul -0x1c(%rbp),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x20(%rbp),%eax\njl 1188 \npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_28], rcx\nmov [rbp+var_4], 0\njmp short loc_11BD\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nimul eax, [rbp+var_1C]\nmov [rdx], eax\nadd [rbp+var_4], 1\nloc_11BD:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_20]\njl short loc_1188\nnop\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3, __int64 a4)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+24h] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a3 )\n break;\n *(_DWORD *)(4LL * (int)i + a4) = a2 * *(_DWORD *)(4LL * (int)i + a1);\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_28], rcx\nmov [rbp+var_4], 0\njmp short loc_11BD\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nimul eax, [rbp+var_1C]\nmov [rdx], eax\nadd [rbp+var_4], 1\nloc_11BD:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_20]\njl short loc_1188\nnop\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3, __int64 a4)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+24h] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a3 )\n break;\n *(_DWORD *)(4LL * (int)i + a4) = a2 * *(_DWORD *)(4LL * (int)i + a1);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3, long long a4) {\n long long result;\n unsigned int i;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a3) break;\n *(uint32_t *)(4LL * (int)i + a4) = a2 * *(uint32_t *)(4LL * (int)i + a1);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3, long long a4) {\n long long result;\n unsigned int i;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a3) break;\n *(uint32_t *)(4LL * (int)i + a4) = a2 * *(uint32_t *)(4LL * (int)i + a1);\n }\n return result;\n}" + }, + { + "index": 865, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int nums[], int n, int size, int result[]) {\n for (int i = 0; i < size; i++) {\n result[i] = n * nums[i];\n }\n}", + "test": "int main() {\n\n int nums1[] = {1, 2, 3, 4, 5, 6, 7};\n\n int size1 = sizeof(nums1) / sizeof(nums1[0]);\n\n int result1[7];\n\n func0(nums1, 3, size1, result1);\n\n int expected1[] = {3, 6, 9, 12, 15, 18, 21};\n\n for (int i = 0; i < size1; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n\n\n int nums2[] = {1, 2, 3, 4, 5, 6, 7};\n\n int size2 = sizeof(nums2) / sizeof(nums2[0]);\n\n int result2[7];\n\n func0(nums2, 4, size2, result2);\n\n int expected2[] = {4, 8, 12, 16, 20, 24, 28};\n\n for (int i = 0; i < size2; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n\n\n int nums3[] = {1, 2, 3, 4, 5, 6, 7};\n\n int size3 = sizeof(nums3) / sizeof(nums3[0]);\n\n int result3[7];\n\n func0(nums3, 10, size3, result3);\n\n int expected3[] = {10, 20, 30, 40, 50, 60, 70};\n\n for (int i = 0; i < size3; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edx,%edx\njle 118f \nlea -0x1(%rdx),%r8d\nmov $0x0,%eax\nmov %esi,%edx\nimul (%rdi,%rax,4),%edx\nmov %edx,(%rcx,%rax,4)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %r8,%rdx\njne 117a \nretq\n", + "ida_asm": "func0:\nendbr64\ntest edx, edx\njle short locret_1193\nmovsxd rdx, edx\nlea r8, ds:0[rdx*4]\nmov eax, 0\nloc_1181:\nmov edx, esi\nimul edx, [rdi+rax]\nmov [rcx+rax], edx\nadd rax, 4\ncmp rax, r8\njnz short loc_1181\nlocret_1193:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, int a2, int a3, __int64 a4)\n{\n __int64 v4; // rax\n\n if ( a3 > 0 )\n {\n v4 = 0LL;\n do\n {\n *(_DWORD *)(a4 + v4) = *(_DWORD *)(a1 + v4) * a2;\n v4 += 4LL;\n }\n while ( v4 != 4LL * a3 );\n }\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest edx, edx\njle short locret_1193\nmovsxd rdx, edx\nlea r8, ds:0[rdx*4]\nmov eax, 0\nloc_1181:\nmov edx, esi\nimul edx, [rdi+rax]\nmov [rcx+rax], edx\nadd rax, 4\ncmp rax, r8\njnz short loc_1181\nlocret_1193:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1169(__int64 a1, int a2, int a3, __int64 a4)\n{\n __int64 v4; // rax\n\n if ( a3 > 0 )\n {\n v4 = 0LL;\n do\n {\n *(_DWORD *)(a4 + v4) = *(_DWORD *)(a1 + v4) * a2;\n v4 += 4LL;\n }\n while ( v4 != 4LL * a3 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1169(long long a1, int a2, int a3, long long a4) {\n long long v4;\n if (a3 > 0) {\n v4 = 0LL;\n do {\n *(uint32_t *)(a4 + v4) = *(uint32_t *)(a1 + v4) * a2;\n v4 += 4LL;\n } while (v4 != 4LL * a3);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, int a2, int a3, long long a4) {\n long long v4;\n if (a3 > 0) {\n v4 = 0LL;\n do {\n *(uint32_t *)(a4 + v4) = *(uint32_t *)(a1 + v4) * a2;\n v4 += 4LL;\n } while (v4 != 4LL * a3);\n }\n}" + }, + { + "index": 866, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char* monthname2) {\n if (strcmp(monthname2, \"January\") == 0 || strcmp(monthname2, \"March\") == 0 ||\n strcmp(monthname2, \"May\") == 0 ||\n strcmp(monthname2, \"July\") == 0 || strcmp(monthname2, \"Augest\") == 0 ||\n strcmp(monthname2, \"October\") == 0 ||\n strcmp(monthname2, \"December\") == 0) {\n return true;\n } else {\n return false;\n }\n}", + "test": "int main() {\n\n assert(func0(\"February\") == false);\n\n assert(func0(\"January\") == true);\n\n assert(func0(\"March\") == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %rdi,-0x8(%rbp)\nmov -0x8(%rbp),%rax\nlea 0xe84(%rip),%rsi\nmov %rax,%rdi\ncallq 1070 \ntest %eax,%eax\nje 121e \nmov -0x8(%rbp),%rax\nlea 0xe71(%rip),%rsi\nmov %rax,%rdi\ncallq 1070 \ntest %eax,%eax\nje 121e \nmov -0x8(%rbp),%rax\nlea 0xe60(%rip),%rsi\nmov %rax,%rdi\ncallq 1070 \ntest %eax,%eax\nje 121e \nmov -0x8(%rbp),%rax\nlea 0xe4d(%rip),%rsi\nmov %rax,%rdi\ncallq 1070 \ntest %eax,%eax\nje 121e \nmov -0x8(%rbp),%rax\nlea 0xe3b(%rip),%rsi\nmov %rax,%rdi\ncallq 1070 \ntest %eax,%eax\nje 121e \nmov -0x8(%rbp),%rax\nlea 0xe2b(%rip),%rsi\nmov %rax,%rdi\ncallq 1070 \ntest %eax,%eax\nje 121e \nmov -0x8(%rbp),%rax\nlea 0xe1c(%rip),%rsi\nmov %rax,%rdi\ncallq 1070 \ntest %eax,%eax\njne 1225 \nmov $0x1,%eax\njmp 122a \nmov $0x0,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+s1], rdi\nmov rax, [rbp+s1]\nlea rdx, s2; \"January\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz loc_1237\nmov rax, [rbp+s1]\nlea rdx, aMarch; \"March\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz loc_1237\nmov rax, [rbp+s1]\nlea rdx, aMay; \"May\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_1237\nmov rax, [rbp+s1]\nlea rdx, aJuly; \"July\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_1237\nmov rax, [rbp+s1]\nlea rdx, aAugest; \"Augest\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_1237\nmov rax, [rbp+s1]\nlea rdx, aOctober; \"October\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_1237\nmov rax, [rbp+s1]\nlea rdx, aDecember; \"December\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_123E\nloc_1237:\nmov eax, 1\njmp short locret_1243\nloc_123E:\nmov eax, 0\nlocret_1243:\nleave\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(const char *a1)\n{\n return !strcmp(a1, \"January\")\n || !strcmp(a1, \"March\")\n || !strcmp(a1, \"May\")\n || !strcmp(a1, \"July\")\n || !strcmp(a1, \"Augest\")\n || !strcmp(a1, \"October\")\n || !strcmp(a1, \"December\");\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+s1], rdi\nmov rax, [rbp+s1]\nlea rdx, s2; \"January\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz loc_1237\nmov rax, [rbp+s1]\nlea rdx, aMarch; \"March\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz loc_1237\nmov rax, [rbp+s1]\nlea rdx, aMay; \"May\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_1237\nmov rax, [rbp+s1]\nlea rdx, aJuly; \"July\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_1237\nmov rax, [rbp+s1]\nlea rdx, aAugest; \"Augest\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_1237\nmov rax, [rbp+s1]\nlea rdx, aOctober; \"October\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njz short loc_1237\nmov rax, [rbp+s1]\nlea rdx, aDecember; \"December\"\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_123E\nloc_1237:\nmov eax, 1\njmp short locret_1243\nloc_123E:\nmov eax, 0\nlocret_1243:\nleave\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1169(const char *a1)\n{\n return !strcmp(a1, \"January\")\n || !strcmp(a1, \"March\")\n || !strcmp(a1, \"May\")\n || !strcmp(a1, \"July\")\n || !strcmp(a1, \"Augest\")\n || !strcmp(a1, \"October\")\n || !strcmp(a1, \"December\");\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1169(const char *a1) {\n return !strcmp(a1, \"January\") || !strcmp(a1, \"March\") || !strcmp(a1, \"May\") ||\n !strcmp(a1, \"July\") || !strcmp(a1, \"Augest\") ||\n !strcmp(a1, \"October\") || !strcmp(a1, \"December\");\n}", + "ida_pseudo_norm": "uint8_t func0(const char *a1) {\n return !strcmp(a1, \"January\") || !strcmp(a1, \"March\") || !strcmp(a1, \"May\") ||\n !strcmp(a1, \"July\") || !strcmp(a1, \"Augest\") ||\n !strcmp(a1, \"October\") || !strcmp(a1, \"December\");\n}" + }, + { + "index": 866, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char* monthname2) {\n if (strcmp(monthname2, \"January\") == 0 || strcmp(monthname2, \"March\") == 0 ||\n strcmp(monthname2, \"May\") == 0 ||\n strcmp(monthname2, \"July\") == 0 || strcmp(monthname2, \"Augest\") == 0 ||\n strcmp(monthname2, \"October\") == 0 ||\n strcmp(monthname2, \"December\") == 0) {\n return true;\n } else {\n return false;\n }\n}", + "test": "int main() {\n\n assert(func0(\"February\") == false);\n\n assert(func0(\"January\") == true);\n\n assert(func0(\"March\") == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%rax\nmov $0x8,%ecx\nlea 0xea8(%rip),%rdi\nmov %rax,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %dl\nsbb $0x0,%dl\nmov $0x1,%ecx\ntest %dl,%dl\nje 1233 \nmov $0x6,%ecx\nlea 0xe8c(%rip),%rdi\nmov %rax,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %dl\nsbb $0x0,%dl\nmov $0x1,%ecx\ntest %dl,%dl\nje 1233 \nmov $0x4,%ecx\nlea 0xe6e(%rip),%rdi\nmov %rax,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %dl\nsbb $0x0,%dl\nmov $0x1,%ecx\ntest %dl,%dl\nje 1233 \nmov $0x5,%ecx\nlea 0xe52(%rip),%rdi\nmov %rax,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %dl\nsbb $0x0,%dl\nmov $0x1,%ecx\ntest %dl,%dl\nje 1233 \nmov $0x7,%ecx\nlea 0xe37(%rip),%rdi\nmov %rax,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %dl\nsbb $0x0,%dl\nmov $0x1,%ecx\ntest %dl,%dl\nje 1233 \nmov $0x8,%ecx\nlea 0xe1e(%rip),%rdi\nmov %rax,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %dl\nsbb $0x0,%dl\nmov $0x1,%ecx\ntest %dl,%dl\nje 1233 \nmov $0x9,%ecx\nlea 0xe06(%rip),%rdi\nmov %rax,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %al\nsbb $0x0,%al\ntest %al,%al\nsete %cl\nmov %ecx,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\nlea rsi, s2; \"January\"\ncall _strcmp\nmov edx, eax\nmov eax, 1\ntest edx, edx\njz loc_1222\nlea rsi, aMarch; \"March\"\nmov rdi, rbx; s1\ncall _strcmp\nmov edx, eax\nmov eax, 1\ntest edx, edx\njz short loc_1222\nlea rsi, aMay; \"May\"\nmov rdi, rbx; s1\ncall _strcmp\nmov edx, eax\nmov eax, 1\ntest edx, edx\njz short loc_1222\nlea rsi, aJuly; \"July\"\nmov rdi, rbx; s1\ncall _strcmp\nmov edx, eax\nmov eax, 1\ntest edx, edx\njz short loc_1222\nlea rsi, aAugest; \"Augest\"\nmov rdi, rbx; s1\ncall _strcmp\nmov edx, eax\nmov eax, 1\ntest edx, edx\njz short loc_1222\nlea rsi, aOctober; \"October\"\nmov rdi, rbx; s1\ncall _strcmp\nmov edx, eax\nmov eax, 1\ntest edx, edx\njz short loc_1222\nlea rsi, aDecember; \"December\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\nsetz al\nloc_1222:\npop rbx\nretn", + "ida_pseudo": "bool __fastcall func0(char *s1)\n{\n int v1; // edx\n bool result; // al\n int v3; // edx\n int v4; // edx\n int v5; // edx\n int v6; // edx\n int v7; // edx\n\n v1 = strcmp(s1, \"January\");\n result = 1;\n if ( v1 )\n {\n v3 = strcmp(s1, \"March\");\n result = 1;\n if ( v3 )\n {\n v4 = strcmp(s1, \"May\");\n result = 1;\n if ( v4 )\n {\n v5 = strcmp(s1, \"July\");\n result = 1;\n if ( v5 )\n {\n v6 = strcmp(s1, \"Augest\");\n result = 1;\n if ( v6 )\n {\n v7 = strcmp(s1, \"October\");\n result = 1;\n if ( v7 )\n return strcmp(s1, \"December\") == 0;\n }\n }\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbx\nmov rbx, rdi\nlea rsi, s2; \"January\"\ncall _strcmp\nmov edx, eax\nmov eax, 1\ntest edx, edx\njz loc_1222\nlea rsi, aMarch; \"March\"\nmov rdi, rbx; s1\ncall _strcmp\nmov edx, eax\nmov eax, 1\ntest edx, edx\njz short loc_1222\nlea rsi, aMay; \"May\"\nmov rdi, rbx; s1\ncall _strcmp\nmov edx, eax\nmov eax, 1\ntest edx, edx\njz short loc_1222\nlea rsi, aJuly; \"July\"\nmov rdi, rbx; s1\ncall _strcmp\nmov edx, eax\nmov eax, 1\ntest edx, edx\njz short loc_1222\nlea rsi, aAugest; \"Augest\"\nmov rdi, rbx; s1\ncall _strcmp\nmov edx, eax\nmov eax, 1\ntest edx, edx\njz short loc_1222\nlea rsi, aOctober; \"October\"\nmov rdi, rbx; s1\ncall _strcmp\nmov edx, eax\nmov eax, 1\ntest edx, edx\njz short loc_1222\nlea rsi, aDecember; \"December\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\nsetz al\nloc_1222:\npop rbx\nretn", + "ida_strip_pseudo": "bool __fastcall sub_1169(char *s1)\n{\n int v1; // edx\n bool result; // al\n int v3; // edx\n int v4; // edx\n int v5; // edx\n int v6; // edx\n int v7; // edx\n\n v1 = strcmp(s1, \"January\");\n result = 1;\n if ( v1 )\n {\n v3 = strcmp(s1, \"March\");\n result = 1;\n if ( v3 )\n {\n v4 = strcmp(s1, \"May\");\n result = 1;\n if ( v4 )\n {\n v5 = strcmp(s1, \"July\");\n result = 1;\n if ( v5 )\n {\n v6 = strcmp(s1, \"Augest\");\n result = 1;\n if ( v6 )\n {\n v7 = strcmp(s1, \"October\");\n result = 1;\n if ( v7 )\n return strcmp(s1, \"December\") == 0;\n }\n }\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_1169(char *s1) {\n int v1;\n bool result;\n int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n v1 = strcmp(s1, \"January\");\n result = 1;\n if (v1) {\n v3 = strcmp(s1, \"March\");\n result = 1;\n if (v3) {\n v4 = strcmp(s1, \"May\");\n result = 1;\n if (v4) {\n v5 = strcmp(s1, \"July\");\n result = 1;\n if (v5) {\n v6 = strcmp(s1, \"Augest\");\n result = 1;\n if (v6) {\n v7 = strcmp(s1, \"October\");\n result = 1;\n if (v7) return strcmp(s1, \"December\") == 0;\n }\n }\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "bool func0(char *s1) {\n int v1;\n bool result;\n int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n v1 = strcmp(s1, \"January\");\n result = 1;\n if (v1) {\n v3 = strcmp(s1, \"March\");\n result = 1;\n if (v3) {\n v4 = strcmp(s1, \"May\");\n result = 1;\n if (v4) {\n v5 = strcmp(s1, \"July\");\n result = 1;\n if (v5) {\n v6 = strcmp(s1, \"Augest\");\n result = 1;\n if (v6) {\n v7 = strcmp(s1, \"October\");\n result = 1;\n if (v7) return strcmp(s1, \"December\") == 0;\n }\n }\n }\n }\n }\n return result;\n}" + }, + { + "index": 866, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char* monthname2) {\n if (strcmp(monthname2, \"January\") == 0 || strcmp(monthname2, \"March\") == 0 ||\n strcmp(monthname2, \"May\") == 0 ||\n strcmp(monthname2, \"July\") == 0 || strcmp(monthname2, \"Augest\") == 0 ||\n strcmp(monthname2, \"October\") == 0 ||\n strcmp(monthname2, \"December\") == 0) {\n return true;\n } else {\n return false;\n }\n}", + "test": "int main() {\n\n assert(func0(\"February\") == false);\n\n assert(func0(\"January\") == true);\n\n assert(func0(\"March\") == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%rax\nmov $0x8,%ecx\nlea 0xe01(%rip),%rdi\nmov $0x1,%r8d\nmov %rax,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %dl\nsbb $0x0,%dl\ntest %dl,%dl\nje 12c3 \nmov $0x6,%ecx\nlea 0xde4(%rip),%rdi\nmov %rax,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %dl\nsbb $0x0,%dl\ntest %dl,%dl\nje 12c3 \nmov $0x4,%ecx\nlea 0xdcb(%rip),%rdi\nmov %rax,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %dl\nsbb $0x0,%dl\ntest %dl,%dl\nje 12c3 \nmov $0x5,%ecx\nlea 0xdb4(%rip),%rdi\nmov %rax,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %dl\nsbb $0x0,%dl\ntest %dl,%dl\nje 12c3 \nmov $0x7,%ecx\nlea 0xd9e(%rip),%rdi\nmov %rax,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %dl\nsbb $0x0,%dl\ntest %dl,%dl\nje 12c3 \nmov $0x8,%ecx\nlea 0xd8a(%rip),%rdi\nmov %rax,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %dl\nsbb $0x0,%dl\ntest %dl,%dl\nje 12c3 \nmov %rax,%rsi\nmov $0x9,%ecx\nlea 0xd74(%rip),%rdi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %al\nsbb $0x0,%al\ntest %al,%al\nsete %r8b\nmov %r8d,%eax\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nlea rsi, s2; \"January\"\nmov ebp, 1\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strcmp\ntest eax, eax\njz short loc_12A6\nlea rsi, aMarch; \"March\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz short loc_12A6\nlea rsi, aMay; \"May\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz short loc_12A6\nlea rsi, aJuly; \"July\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz short loc_12A6\nlea rsi, aAugest; \"Augest\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz short loc_12A6\nlea rsi, aOctober; \"October\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz short loc_12A6\nlea rsi, aDecember; \"December\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\nsetz bpl\nloc_12A6:\nadd rsp, 8\nmov eax, ebp\npop rbx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(char *s1)\n{\n unsigned int v1; // ebp\n\n v1 = 1;\n if ( strcmp(s1, \"January\")\n && strcmp(s1, \"March\")\n && strcmp(s1, \"May\")\n && strcmp(s1, \"July\")\n && strcmp(s1, \"Augest\")\n && strcmp(s1, \"October\") )\n {\n LOBYTE(v1) = strcmp(s1, \"December\") == 0;\n }\n return v1;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbp\nlea rsi, s2; \"January\"\nmov ebp, 1\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strcmp\ntest eax, eax\njz short loc_12A6\nlea rsi, aMarch; \"March\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz short loc_12A6\nlea rsi, aMay; \"May\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz short loc_12A6\nlea rsi, aJuly; \"July\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz short loc_12A6\nlea rsi, aAugest; \"Augest\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz short loc_12A6\nlea rsi, aOctober; \"October\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz short loc_12A6\nlea rsi, aDecember; \"December\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\nsetz bpl\nloc_12A6:\nadd rsp, 8\nmov eax, ebp\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(char *s1)\n{\n unsigned int v1; // ebp\n\n v1 = 1;\n if ( strcmp(s1, \"January\")\n && strcmp(s1, \"March\")\n && strcmp(s1, \"May\")\n && strcmp(s1, \"July\")\n && strcmp(s1, \"Augest\")\n && strcmp(s1, \"October\") )\n {\n LOBYTE(v1) = strcmp(s1, \"December\") == 0;\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(char *s1) {\n unsigned int v1;\n v1 = 1;\n if (strcmp(s1, \"January\") && strcmp(s1, \"March\") && strcmp(s1, \"May\") &&\n strcmp(s1, \"July\") && strcmp(s1, \"Augest\") && strcmp(s1, \"October\")) {\n LOBYTE(v1) = strcmp(s1, \"December\") == 0;\n }\n return v1;\n}", + "ida_pseudo_norm": "long long func0(char *s1) {\n unsigned int v1;\n v1 = 1;\n if (strcmp(s1, \"January\") && strcmp(s1, \"March\") && strcmp(s1, \"May\") &&\n strcmp(s1, \"July\") && strcmp(s1, \"Augest\") && strcmp(s1, \"October\")) {\n LOBYTE(v1) = strcmp(s1, \"December\") == 0;\n }\n return v1;\n}" + }, + { + "index": 866, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char* monthname2) {\n if (strcmp(monthname2, \"January\") == 0 || strcmp(monthname2, \"March\") == 0 ||\n strcmp(monthname2, \"May\") == 0 ||\n strcmp(monthname2, \"July\") == 0 || strcmp(monthname2, \"Augest\") == 0 ||\n strcmp(monthname2, \"October\") == 0 ||\n strcmp(monthname2, \"December\") == 0) {\n return true;\n } else {\n return false;\n }\n}", + "test": "int main() {\n\n assert(func0(\"February\") == false);\n\n assert(func0(\"January\") == true);\n\n assert(func0(\"March\") == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%rax\nmov $0x8,%ecx\nlea 0xe01(%rip),%rdi\nmov $0x1,%r8d\nmov %rax,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %dl\nsbb $0x0,%dl\ntest %dl,%dl\nje 12c3 \nmov $0x6,%ecx\nlea 0xde4(%rip),%rdi\nmov %rax,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %dl\nsbb $0x0,%dl\ntest %dl,%dl\nje 12c3 \nmov $0x4,%ecx\nlea 0xdcb(%rip),%rdi\nmov %rax,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %dl\nsbb $0x0,%dl\ntest %dl,%dl\nje 12c3 \nmov $0x5,%ecx\nlea 0xdb4(%rip),%rdi\nmov %rax,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %dl\nsbb $0x0,%dl\ntest %dl,%dl\nje 12c3 \nmov $0x7,%ecx\nlea 0xd9e(%rip),%rdi\nmov %rax,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %dl\nsbb $0x0,%dl\ntest %dl,%dl\nje 12c3 \nmov $0x8,%ecx\nlea 0xd8a(%rip),%rdi\nmov %rax,%rsi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %dl\nsbb $0x0,%dl\ntest %dl,%dl\nje 12c3 \nmov %rax,%rsi\nmov $0x9,%ecx\nlea 0xd74(%rip),%rdi\nrepz cmpsb %es:(%rdi),%ds:(%rsi)\nseta %al\nsbb $0x0,%al\ntest %al,%al\nsete %r8b\nmov %r8d,%eax\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nlea rsi, s2; \"January\"\nmov ebp, 1\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strcmp\ntest eax, eax\njz short loc_12A6\nlea rsi, aMarch; \"March\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz short loc_12A6\nlea rsi, aMay; \"May\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz short loc_12A6\nlea rsi, aJuly; \"July\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz short loc_12A6\nlea rsi, aAugest; \"Augest\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz short loc_12A6\nlea rsi, aOctober; \"October\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz short loc_12A6\nlea rsi, aDecember; \"December\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\nsetz bpl\nloc_12A6:\nadd rsp, 8\nmov eax, ebp\npop rbx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(char *s1)\n{\n unsigned int v1; // ebp\n\n v1 = 1;\n if ( strcmp(s1, \"January\")\n && strcmp(s1, \"March\")\n && strcmp(s1, \"May\")\n && strcmp(s1, \"July\")\n && strcmp(s1, \"Augest\")\n && strcmp(s1, \"October\") )\n {\n LOBYTE(v1) = strcmp(s1, \"December\") == 0;\n }\n return v1;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbp\nlea rsi, s2; \"January\"\nmov ebp, 1\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strcmp\ntest eax, eax\njz short loc_12A6\nlea rsi, aMarch; \"March\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz short loc_12A6\nlea rsi, aMay; \"May\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz short loc_12A6\nlea rsi, aJuly; \"July\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz short loc_12A6\nlea rsi, aAugest; \"Augest\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz short loc_12A6\nlea rsi, aOctober; \"October\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njz short loc_12A6\nlea rsi, aDecember; \"December\"\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\nsetz bpl\nloc_12A6:\nadd rsp, 8\nmov eax, ebp\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(char *s1)\n{\n unsigned int v1; // ebp\n\n v1 = 1;\n if ( strcmp(s1, \"January\")\n && strcmp(s1, \"March\")\n && strcmp(s1, \"May\")\n && strcmp(s1, \"July\")\n && strcmp(s1, \"Augest\")\n && strcmp(s1, \"October\") )\n {\n LOBYTE(v1) = strcmp(s1, \"December\") == 0;\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(char *s1) {\n unsigned int v1;\n v1 = 1;\n if (strcmp(s1, \"January\") && strcmp(s1, \"March\") && strcmp(s1, \"May\") &&\n strcmp(s1, \"July\") && strcmp(s1, \"Augest\") && strcmp(s1, \"October\")) {\n LOBYTE(v1) = strcmp(s1, \"December\") == 0;\n }\n return v1;\n}", + "ida_pseudo_norm": "long long func0(char *s1) {\n unsigned int v1;\n v1 = 1;\n if (strcmp(s1, \"January\") && strcmp(s1, \"March\") && strcmp(s1, \"May\") &&\n strcmp(s1, \"July\") && strcmp(s1, \"Augest\") && strcmp(s1, \"October\")) {\n LOBYTE(v1) = strcmp(s1, \"December\") == 0;\n }\n return v1;\n}" + }, + { + "index": 867, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int odd = 0;\n for (int i = 0; i < n; i++) {\n if (arr[i] % 2) {\n odd += 1;\n }\n }\n if (odd % 2) {\n return 1;\n }\n return 2;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4, 5, 6, 7, 8, 9};\n\n int arr2[] = {1, 2, 3, 4, 5, 6, 7, 8};\n\n int arr3[] = {1, 2, 3};\n\n\n\n assert(func0(arr1, 9) == 1);\n\n assert(func0(arr2, 8) == 2);\n\n assert(func0(arr3, 3) == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11ad \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nand $0x1,%eax\ntest %eax,%eax\nje 11a9 \naddl $0x1,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1188 \nmov -0x8(%rbp),%eax\nand $0x1,%eax\ntest %eax,%eax\nje 11c6 \nmov $0x1,%eax\njmp 11cb \nmov $0x2,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11AD\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njz short loc_11A9\nadd [rbp+var_8], 1\nloc_11A9:\nadd [rbp+var_4], 1\nloc_11AD:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\nand eax, 1\ntest eax, eax\njz short loc_11C6\nmov eax, 1\njmp short loc_11CB\nloc_11C6:\nmov eax, 2\nloc_11CB:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n char v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( (*(_DWORD *)(4LL * i + a1) & 1) != 0 )\n ++v3;\n }\n if ( (v3 & 1) != 0 )\n return 1LL;\n else\n return 2LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11AD\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njz short loc_11A9\nadd [rbp+var_8], 1\nloc_11A9:\nadd [rbp+var_4], 1\nloc_11AD:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\nand eax, 1\ntest eax, eax\njz short loc_11C6\nmov eax, 1\njmp short loc_11CB\nloc_11C6:\nmov eax, 2\nloc_11CB:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n char v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( (*(_DWORD *)(4LL * i + a1) & 1) != 0 )\n ++v3;\n }\n if ( (v3 & 1) != 0 )\n return 1LL;\n else\n return 2LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n char v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n if ((*(uint32_t *)(4LL * i + a1) & 1) != 0) ++v3;\n }\n if ((v3 & 1) != 0)\n return 1LL;\n else\n return 2LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n char v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n if ((*(uint32_t *)(4LL * i + a1) & 1) != 0) ++v3;\n }\n if ((v3 & 1) != 0)\n return 1LL;\n else\n return 2LL;\n}" + }, + { + "index": 867, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int odd = 0;\n for (int i = 0; i < n; i++) {\n if (arr[i] % 2) {\n odd += 1;\n }\n }\n if (odd % 2) {\n return 1;\n }\n return 2;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4, 5, 6, 7, 8, 9};\n\n int arr2[] = {1, 2, 3, 4, 5, 6, 7, 8};\n\n int arr3[] = {1, 2, 3};\n\n\n\n assert(func0(arr1, 9) == 1);\n\n assert(func0(arr2, 8) == 2);\n\n assert(func0(arr3, 3) == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11a0 \nmov %rdi,%rax\nlea -0x1(%rsi),%edx\nlea 0x4(%rdi,%rdx,4),%rsi\nmov $0x0,%ecx\nmov (%rax),%edx\nand $0x1,%edx\ncmp $0x1,%edx\nsbb $0xffffffff,%ecx\nadd $0x4,%rax\ncmp %rsi,%rax\njne 1181 \nand $0x1,%ecx\nmov $0x2,%eax\nsub %ecx,%eax\nretq\nmov $0x2,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_119F\nmov rax, rdi\nmovsxd rsi, esi\nlea rsi, [rdi+rsi*4]\nmov ecx, 0\nloc_1180:\nmov edx, [rax]\nand edx, 1\ncmp edx, 1\nsbb ecx, 0FFFFFFFFh\nadd rax, 4\ncmp rax, rsi\njnz short loc_1180\nloc_1194:\nand ecx, 1\nmov eax, 2\nsub eax, ecx\nretn\nloc_119F:\nmov ecx, 0\njmp short loc_1194", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n _DWORD *v3; // rsi\n char v4; // cl\n\n if ( a2 <= 0 )\n {\n v4 = 0;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n v4 -= ((*v2++ & 1) == 0) - 1;\n while ( v2 != v3 );\n }\n return 2 - (v4 & 1u);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_119F\nmov rax, rdi\nmovsxd rsi, esi\nlea rsi, [rdi+rsi*4]\nmov ecx, 0\nloc_1180:\nmov edx, [rax]\nand edx, 1\ncmp edx, 1\nsbb ecx, 0FFFFFFFFh\nadd rax, 4\ncmp rax, rsi\njnz short loc_1180\nloc_1194:\nand ecx, 1\nmov eax, 2\nsub eax, ecx\nretn\nloc_119F:\nmov ecx, 0\njmp short loc_1194", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n _DWORD *v3; // rsi\n char v4; // cl\n\n if ( a2 <= 0 )\n {\n v4 = 0;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n v4 -= ((*v2++ & 1) == 0) - 1;\n while ( v2 != v3 );\n }\n return 2 - (v4 & 1u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2) {\n uint32_t *v2;\n uint32_t *v3;\n char v4;\n if (a2 <= 0) {\n v4 = 0;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n v4 -= ((*v2++ & 1) == 0) - 1;\n while (v2 != v3);\n }\n return 2 - (v4 & 1u);\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n uint32_t *v3;\n char v4;\n if (a2 <= 0) {\n v4 = 0;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n v4 -= ((*v2++ & 1) == 0) - 1;\n while (v2 != v3);\n }\n return 2 - (v4 & 1u);\n}" + }, + { + "index": 867, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n int odd = 0;\n for (int i = 0; i < n; i++) {\n if (arr[i] % 2) {\n odd += 1;\n }\n }\n if (odd % 2) {\n return 1;\n }\n return 2;\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 3, 4, 5, 6, 7, 8, 9};\n\n int arr2[] = {1, 2, 3, 4, 5, 6, 7, 8};\n\n int arr3[] = {1, 2, 3};\n\n\n\n assert(func0(arr1, 9) == 1);\n\n assert(func0(arr2, 8) == 2);\n\n assert(func0(arr3, 3) == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 12e0 \nlea -0x1(%rsi),%eax\nxor %edx,%edx\nlea 0x4(%rdi,%rax,4),%rcx\nnopw 0x0(%rax,%rax,1)\nmov (%rdi),%eax\nand $0x1,%eax\ncmp $0x1,%eax\nsbb $0xffffffff,%edx\nadd $0x4,%rdi\ncmp %rdi,%rcx\njne 12b8 \nand $0x1,%edx\nmov $0x2,%eax\nsub %edx,%eax\nretq\nnopw 0x0(%rax,%rax,1)\nmov $0x2,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_12C0\nmovsxd rsi, esi\nxor edx, edx\nlea rcx, [rdi+rsi*4]\nnop dword ptr [rax+00000000h]\nloc_1298:\nmov eax, [rdi]\nand eax, 1\ncmp eax, 1\nsbb edx, 0FFFFFFFFh\nadd rdi, 4\ncmp rcx, rdi\njnz short loc_1298\nand edx, 1\nmov eax, 2\nsub eax, edx\nretn\nloc_12C0:\nmov eax, 2\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n char v2; // dl\n _DWORD *v3; // rcx\n\n if ( a2 <= 0 )\n return 2LL;\n v2 = 0;\n v3 = &a1[a2];\n do\n v2 -= ((*a1++ & 1) == 0) - 1;\n while ( v3 != a1 );\n return 2 - (v2 & 1u);\n}", + "ida_strip_asm": "sub_1280:\nendbr64\ntest esi, esi\njle short loc_12C0\nmovsxd rsi, esi\nxor edx, edx\nlea rcx, [rdi+rsi*4]\nnop dword ptr [rax+00000000h]\nloc_1298:\nmov eax, [rdi]\nand eax, 1\ncmp eax, 1\nsbb edx, 0FFFFFFFFh\nadd rdi, 4\ncmp rcx, rdi\njnz short loc_1298\nand edx, 1\nmov eax, 2\nsub eax, edx\nretn\nloc_12C0:\nmov eax, 2\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1280(_DWORD *a1, int a2)\n{\n char v2; // dl\n _DWORD *v3; // rcx\n\n if ( a2 <= 0 )\n return 2LL;\n v2 = 0;\n v3 = &a1[a2];\n do\n v2 -= ((*a1++ & 1) == 0) - 1;\n while ( v3 != a1 );\n return 2 - (v2 & 1u);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1280(uint32_t *a1, int a2) {\n char v2;\n uint32_t *v3;\n if (a2 <= 0) return 2LL;\n v2 = 0;\n v3 = &a1[a2];\n do\n v2 -= ((*a1++ & 1) == 0) - 1;\n while (v3 != a1);\n return 2 - (v2 & 1u);\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n char v2;\n uint32_t *v3;\n if (a2 <= 0) return 2LL;\n v2 = 0;\n v3 = &a1[a2];\n do\n v2 -= ((*a1++ & 1) == 0) - 1;\n while (v3 != a1);\n return 2 - (v2 & 1u);\n}" + }, + { + "index": 868, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(char *a) {\n int l = 0;\n char *x = a;\n while (*x == ' ') x++;\n for (int i = 0; i < strlen(x); i++) {\n if (x[i] == ' ') {\n l = 0;\n } else {\n l++;\n }\n }\n return l;\n}", + "test": "int main() {\n\n assert(func0(\"python language\") == 8);\n\n assert(func0(\"PHP\") == 3);\n\n assert(func0(\"\") == 0);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x28,%rsp\nmov %rdi,-0x28(%rbp)\nmovl $0x0,-0x20(%rbp)\nmov -0x28(%rbp),%rax\nmov %rax,-0x18(%rbp)\njmp 1190 \naddq $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%rax\nmovzbl (%rax),%eax\ncmp $0x20,%al\nje 118b \nmovl $0x0,-0x1c(%rbp)\njmp 11c9 \nmov -0x1c(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp $0x20,%al\njne 11c1 \nmovl $0x0,-0x20(%rbp)\njmp 11c5 \naddl $0x1,-0x20(%rbp)\naddl $0x1,-0x1c(%rbp)\nmov -0x1c(%rbp),%eax\nmovslq %eax,%rbx\nmov -0x18(%rbp),%rax\nmov %rax,%rdi\ncallq 1060 \ncmp %rax,%rbx\njb 11a4 \nmov -0x20(%rbp),%eax\nadd $0x28,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+var_28], rdi\nmov [rbp+var_20], 0\nmov rax, [rbp+var_28]\nmov [rbp+s], rax\njmp short loc_1190\nloc_118B:\nadd [rbp+s], 1\nloc_1190:\nmov rax, [rbp+s]\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njz short loc_118B\nmov [rbp+var_1C], 0\njmp short loc_11C9\nloc_11A4:\nmov eax, [rbp+var_1C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njnz short loc_11C1\nmov [rbp+var_20], 0\njmp short loc_11C5\nloc_11C1:\nadd [rbp+var_20], 1\nloc_11C5:\nadd [rbp+var_1C], 1\nloc_11C9:\nmov eax, [rbp+var_1C]\nmovsxd rbx, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rbx, rax\njb short loc_11A4\nmov eax, [rbp+var_20]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n unsigned int v2; // [rsp+10h] [rbp-20h]\n int i; // [rsp+14h] [rbp-1Ch]\n\n v2 = 0;\n while ( *a1 == 32 )\n ++a1;\n for ( i = 0; i < strlen(a1); ++i )\n {\n if ( a1[i] == 32 )\n v2 = 0;\n else\n ++v2;\n }\n return v2;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+var_28], rdi\nmov [rbp+var_20], 0\nmov rax, [rbp+var_28]\nmov [rbp+s], rax\njmp short loc_1190\nloc_118B:\nadd [rbp+s], 1\nloc_1190:\nmov rax, [rbp+s]\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njz short loc_118B\nmov [rbp+var_1C], 0\njmp short loc_11C9\nloc_11A4:\nmov eax, [rbp+var_1C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp al, 20h ; ' '\njnz short loc_11C1\nmov [rbp+var_20], 0\njmp short loc_11C5\nloc_11C1:\nadd [rbp+var_20], 1\nloc_11C5:\nadd [rbp+var_1C], 1\nloc_11C9:\nmov eax, [rbp+var_1C]\nmovsxd rbx, eax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\ncmp rbx, rax\njb short loc_11A4\nmov eax, [rbp+var_20]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1)\n{\n unsigned int v2; // [rsp+10h] [rbp-20h]\n int i; // [rsp+14h] [rbp-1Ch]\n\n v2 = 0;\n while ( *a1 == 32 )\n ++a1;\n for ( i = 0; i < strlen(a1); ++i )\n {\n if ( a1[i] == 32 )\n v2 = 0;\n else\n ++v2;\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1) {\n unsigned int v2;\n int i;\n v2 = 0;\n while (*a1 == 32) ++a1;\n for (i = 0; i < strlen(a1); ++i) {\n if (a1[i] == 32)\n v2 = 0;\n else\n ++v2;\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n unsigned int v2;\n int i;\n v2 = 0;\n while (*a1 == 32) ++a1;\n for (i = 0; i < strlen(a1); ++i) {\n if (a1[i] == 32)\n v2 = 0;\n else\n ++v2;\n }\n return v2;\n}" + }, + { + "index": 868, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(char *a) {\n int l = 0;\n char *x = a;\n while (*x == ' ') x++;\n for (int i = 0; i < strlen(x); i++) {\n if (x[i] == ' ') {\n l = 0;\n } else {\n l++;\n }\n }\n return l;\n}", + "test": "int main() {\n\n assert(func0(\"python language\") == 8);\n\n assert(func0(\"PHP\") == 3);\n\n assert(func0(\"\") == 0);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%rsi\ncmpb $0x20,(%rdi)\njne 115e \nadd $0x1,%rsi\ncmpb $0x20,(%rsi)\nje 1155 \nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nmov %rsi,%rdi\nrepnz scas %es:(%rdi),%al\nnot %rcx\nmov %rsi,%rdx\nlea -0x1(%rsi,%rcx,1),%rcx\nmov $0x0,%eax\nmov $0x0,%esi\ncmp %rcx,%rdx\nje 1198 \nadd $0x1,%eax\ncmpb $0x20,(%rdx)\ncmove %esi,%eax\nadd $0x1,%rdx\njmp 1184 \nretq\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncmp byte ptr [rdi], 20h ; ' '\njnz short loc_117F\nloc_1176:\nadd rbx, 1\ncmp byte ptr [rbx], 20h ; ' '\njz short loc_1176\nloc_117F:\nmov rdi, rbx; s\ncall _strlen\nmov rdx, rax\nmov rax, rbx\nadd rbx, rdx\nmov edx, 0\njmp short loc_119B\nloc_1197:\nadd rax, 1\nloc_119B:\ncmp rax, rbx\njz short loc_11AF\nadd edx, 1\ncmp byte ptr [rax], 20h ; ' '\njnz short loc_1197\nmov edx, 0\njmp short loc_1197\nloc_11AF:\nmov eax, edx\npop rbx\nretn", + "ida_pseudo": "__int64 __fastcall func0(char *s)\n{\n char *i; // rbx\n size_t v2; // rdx\n char *v3; // rax\n char *v4; // rbx\n unsigned int v5; // edx\n\n for ( i = s; *i == 32; ++i )\n ;\n v2 = strlen(i);\n v3 = i;\n v4 = &i[v2];\n v5 = 0;\n while ( v3 != v4 )\n {\n ++v5;\n if ( *v3 == 32 )\n v5 = 0;\n ++v3;\n }\n return v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbx\nmov rbx, rdi\ncmp byte ptr [rdi], 20h ; ' '\njnz short loc_117F\nloc_1176:\nadd rbx, 1\ncmp byte ptr [rbx], 20h ; ' '\njz short loc_1176\nloc_117F:\nmov rdi, rbx; s\ncall _strlen\nmov rdx, rax\nmov rax, rbx\nadd rbx, rdx\nmov edx, 0\njmp short loc_119B\nloc_1197:\nadd rax, 1\nloc_119B:\ncmp rax, rbx\njz short loc_11AF\nadd edx, 1\ncmp byte ptr [rax], 20h ; ' '\njnz short loc_1197\nmov edx, 0\njmp short loc_1197\nloc_11AF:\nmov eax, edx\npop rbx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(char *s)\n{\n char *i; // rbx\n size_t v2; // rdx\n char *v3; // rax\n char *v4; // rbx\n unsigned int v5; // edx\n\n for ( i = s; *i == 32; ++i )\n ;\n v2 = strlen(i);\n v3 = i;\n v4 = &i[v2];\n v5 = 0;\n while ( v3 != v4 )\n {\n ++v5;\n if ( *v3 == 32 )\n v5 = 0;\n ++v3;\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(char *s) {\n char *i;\n unsigned int v2;\n char *v3;\n char *v4;\n unsigned int v5;\n for (i = s; *i == 32; ++i)\n ;\n v2 = strlen(i);\n v3 = i;\n v4 = &i[v2];\n v5 = 0;\n while (v3 != v4) {\n ++v5;\n if (*v3 == 32) v5 = 0;\n ++v3;\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(char *s) {\n char *i;\n unsigned int v2;\n char *v3;\n char *v4;\n unsigned int v5;\n for (i = s; *i == 32; ++i)\n ;\n v2 = strlen(i);\n v3 = i;\n v4 = &i[v2];\n v5 = 0;\n while (v3 != v4) {\n ++v5;\n if (*v3 == 32) v5 = 0;\n ++v3;\n }\n return v5;\n}" + }, + { + "index": 868, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(char *a) {\n int l = 0;\n char *x = a;\n while (*x == ' ') x++;\n for (int i = 0; i < strlen(x); i++) {\n if (x[i] == ' ') {\n l = 0;\n } else {\n l++;\n }\n }\n return l;\n}", + "test": "int main() {\n\n assert(func0(\"python language\") == 8);\n\n assert(func0(\"PHP\") == 3);\n\n assert(func0(\"\") == 0);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\ncmpb $0x20,(%rdi)\nmov %rdi,%rbx\njne 1229 \nnopl (%rax)\nadd $0x1,%rbx\ncmpb $0x20,(%rbx)\nje 1220 \nmov %rbx,%rdi\ncallq 1060 \nmov %rbx,%rdi\nxor %ecx,%ecx\nlea (%rbx,%rax,1),%rdx\nxor %eax,%eax\njmp 124d \nxchg %ax,%ax\nadd $0x1,%eax\ncmpb $0x20,(%rdi)\ncmove %ecx,%eax\nadd $0x1,%rdi\ncmp %rdx,%rdi\njne 1240 \npop %rbx\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbx\ncmp byte ptr [rdi], 20h ; ' '\nmov rbx, rdi\njnz short loc_1229\nnop dword ptr [rax]\nloc_1220:\nadd rbx, 1\ncmp byte ptr [rbx], 20h ; ' '\njz short loc_1220\nloc_1229:\nmov rdi, rbx; s\ncall _strlen\ntest rax, rax\njz short loc_1258\nlea rdx, [rbx+rax]\nmov rdi, rbx\nxor eax, eax\nnop\nloc_1240:\nadd eax, 1\ncmp byte ptr [rdi], 20h ; ' '\njnz short loc_124A\nxor eax, eax\nloc_124A:\nadd rdi, 1\ncmp rdx, rdi\njnz short loc_1240\npop rbx\nretn\nloc_1258:\nxor eax, eax\npop rbx\nretn", + "ida_pseudo": "size_t __fastcall func0(char *s)\n{\n char *i; // rbx\n size_t result; // rax\n char *v3; // rdx\n char *v4; // rdi\n\n for ( i = s; *i == 32; ++i )\n ;\n result = strlen(i);\n if ( !result )\n return 0LL;\n v3 = &i[result];\n v4 = i;\n LODWORD(result) = 0;\n do\n {\n result = (unsigned int)(result + 1);\n if ( *v4 == 32 )\n result = 0LL;\n ++v4;\n }\n while ( v3 != v4 );\n return result;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbx\ncmp byte ptr [rdi], 20h ; ' '\nmov rbx, rdi\njnz short loc_1229\nnop dword ptr [rax]\nloc_1220:\nadd rbx, 1\ncmp byte ptr [rbx], 20h ; ' '\njz short loc_1220\nloc_1229:\nmov rdi, rbx; s\ncall _strlen\ntest rax, rax\njz short loc_1258\nlea rdx, [rbx+rax]\nmov rdi, rbx\nxor eax, eax\nnop\nloc_1240:\nadd eax, 1\ncmp byte ptr [rdi], 20h ; ' '\njnz short loc_124A\nxor eax, eax\nloc_124A:\nadd rdi, 1\ncmp rdx, rdi\njnz short loc_1240\npop rbx\nretn\nloc_1258:\nxor eax, eax\npop rbx\nretn", + "ida_strip_pseudo": "size_t __fastcall sub_1210(char *s)\n{\n char *i; // rbx\n size_t result; // rax\n char *v3; // rdx\n char *v4; // rdi\n\n for ( i = s; *i == 32; ++i )\n ;\n result = strlen(i);\n if ( !result )\n return 0LL;\n v3 = &i[result];\n v4 = i;\n LODWORD(result) = 0;\n do\n {\n result = (unsigned int)(result + 1);\n if ( *v4 == 32 )\n result = 0LL;\n ++v4;\n }\n while ( v3 != v4 );\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned int sub_1210(char *s) {\n char *i;\n unsigned int result;\n char *v3;\n char *v4;\n for (i = s; *i == 32; ++i)\n ;\n result = strlen(i);\n if (!result) return 0LL;\n v3 = &i[result];\n v4 = i;\n LODWORD(result) = 0;\n do {\n result = (unsigned int)(result + 1);\n if (*v4 == 32) result = 0LL;\n ++v4;\n } while (v3 != v4);\n return result;\n}", + "ida_pseudo_norm": "unsigned int func0(char *s) {\n char *i;\n unsigned int result;\n char *v3;\n char *v4;\n for (i = s; *i == 32; ++i)\n ;\n result = strlen(i);\n if (!result) return 0LL;\n v3 = &i[result];\n v4 = i;\n LODWORD(result) = 0;\n do {\n result = (unsigned int)(result + 1);\n if (*v4 == 32) result = 0LL;\n ++v4;\n } while (v3 != v4);\n return result;\n}" + }, + { + "index": 868, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(char *a) {\n int l = 0;\n char *x = a;\n while (*x == ' ') x++;\n for (int i = 0; i < strlen(x); i++) {\n if (x[i] == ' ') {\n l = 0;\n } else {\n l++;\n }\n }\n return l;\n}", + "test": "int main() {\n\n assert(func0(\"python language\") == 8);\n\n assert(func0(\"PHP\") == 3);\n\n assert(func0(\"\") == 0);\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\ncmpb $0x20,(%rdi)\nmov %rdi,%rbx\njne 1229 \nnopl (%rax)\nadd $0x1,%rbx\ncmpb $0x20,(%rbx)\nje 1220 \nmov %rbx,%rdi\ncallq 1060 \ntest %rax,%rax\nje 1260 \nlea (%rbx,%rax,1),%rdx\nmov %rbx,%rdi\nxor %eax,%eax\nxor %ecx,%ecx\nnopl 0x0(%rax)\nadd $0x1,%eax\ncmpb $0x20,(%rdi)\ncmove %ecx,%eax\nadd $0x1,%rdi\ncmp %rdi,%rdx\njne 1248 \npop %rbx\nretq\nnopl 0x0(%rax)\nxor %eax,%eax\npop %rbx\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush rbx\ncmp byte ptr [rdi], 20h ; ' '\nmov rbx, rdi\njnz short loc_1229\nnop dword ptr [rax]\nloc_1220:\nadd rbx, 1\ncmp byte ptr [rbx], 20h ; ' '\njz short loc_1220\nloc_1229:\nmov rdi, rbx; s\ncall _strlen\ntest rax, rax\njz short loc_1258\nlea rdx, [rbx+rax]\nmov rdi, rbx\nxor eax, eax\nnop\nloc_1240:\nadd eax, 1\ncmp byte ptr [rdi], 20h ; ' '\njnz short loc_124A\nxor eax, eax\nloc_124A:\nadd rdi, 1\ncmp rdx, rdi\njnz short loc_1240\npop rbx\nretn\nloc_1258:\nxor eax, eax\npop rbx\nretn", + "ida_pseudo": "size_t __fastcall func0(char *s)\n{\n char *i; // rbx\n size_t result; // rax\n char *v3; // rdx\n char *v4; // rdi\n\n for ( i = s; *i == 32; ++i )\n ;\n result = strlen(i);\n if ( !result )\n return 0LL;\n v3 = &i[result];\n v4 = i;\n LODWORD(result) = 0;\n do\n {\n result = (unsigned int)(result + 1);\n if ( *v4 == 32 )\n result = 0LL;\n ++v4;\n }\n while ( v3 != v4 );\n return result;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbx\ncmp byte ptr [rdi], 20h ; ' '\nmov rbx, rdi\njnz short loc_1229\nnop dword ptr [rax]\nloc_1220:\nadd rbx, 1\ncmp byte ptr [rbx], 20h ; ' '\njz short loc_1220\nloc_1229:\nmov rdi, rbx; s\ncall _strlen\ntest rax, rax\njz short loc_1258\nlea rdx, [rbx+rax]\nmov rdi, rbx\nxor eax, eax\nnop\nloc_1240:\nadd eax, 1\ncmp byte ptr [rdi], 20h ; ' '\njnz short loc_124A\nxor eax, eax\nloc_124A:\nadd rdi, 1\ncmp rdx, rdi\njnz short loc_1240\npop rbx\nretn\nloc_1258:\nxor eax, eax\npop rbx\nretn", + "ida_strip_pseudo": "size_t __fastcall sub_1210(char *s)\n{\n char *i; // rbx\n size_t result; // rax\n char *v3; // rdx\n char *v4; // rdi\n\n for ( i = s; *i == 32; ++i )\n ;\n result = strlen(i);\n if ( !result )\n return 0LL;\n v3 = &i[result];\n v4 = i;\n LODWORD(result) = 0;\n do\n {\n result = (unsigned int)(result + 1);\n if ( *v4 == 32 )\n result = 0LL;\n ++v4;\n }\n while ( v3 != v4 );\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned int sub_1210(char *s) {\n char *i;\n unsigned int result;\n char *v3;\n char *v4;\n for (i = s; *i == 32; ++i)\n ;\n result = strlen(i);\n if (!result) return 0LL;\n v3 = &i[result];\n v4 = i;\n LODWORD(result) = 0;\n do {\n result = (unsigned int)(result + 1);\n if (*v4 == 32) result = 0LL;\n ++v4;\n } while (v3 != v4);\n return result;\n}", + "ida_pseudo_norm": "unsigned int func0(char *s) {\n char *i;\n unsigned int result;\n char *v3;\n char *v4;\n for (i = s; *i == 32; ++i)\n ;\n result = strlen(i);\n if (!result) return 0LL;\n v3 = &i[result];\n v4 = i;\n LODWORD(result) = 0;\n do {\n result = (unsigned int)(result + 1);\n if (*v4 == 32) result = 0LL;\n ++v4;\n } while (v3 != v4);\n return result;\n}" + }, + { + "index": 869, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int elements[10];\n\n int size;\n\n} IntList;\n\n\n\ntypedef struct {\n\n IntList lists[10];\n\n int size;\n\n} ListOfLists;\n\n\n\nint compare_lists(ListOfLists a, ListOfLists b) {\n\n if(a.size != b.size) return 0;\n\n for(int i = 0; i < a.size; i++) {\n\n if(a.lists[i].size != b.lists[i].size) return 0;\n\n for(int j = 0; j < a.lists[i].size; j++) {\n\n if(a.lists[i].elements[j] != b.lists[i].elements[j]) return 0;\n\n }\n\n }\n\n return 1;\n\n}\n\n\n\n", + "func": "ListOfLists func0(ListOfLists list1, int leftrange, int rigthrange) {\n ListOfLists result;\n result.size = 0;\n for (int i = 0; i < list1.size; i++) {\n int min = list1.lists[i].elements[0];\n int max = list1.lists[i].elements[0];\n for (int j = 1; j < list1.lists[i].size; j++) {\n if (list1.lists[i].elements[j] < min) min = list1.lists[i].elements[j];\n if (list1.lists[i].elements[j] > max) max = list1.lists[i].elements[j];\n }\n if (min >= leftrange && max <= rigthrange) {\n result.lists[result.size++] = list1.lists[i];\n }\n }\n return result;\n}", + "test": "int main() {\n\n ListOfLists list1;\n\n list1.size = 6;\n\n list1.lists[0].size = 1; list1.lists[0].elements[0] = 2;\n\n list1.lists[1].size = 1; list1.lists[1].elements[0] = 0;\n\n list1.lists[2].size = 3; list1.lists[2].elements[0] = 1; list1.lists[2].elements[1] = 2; list1.lists[2].elements[2] = 3;\n\n list1.lists[3].size = 6; list1.lists[3].elements[0] = 0; list1.lists[3].elements[1] = 1; list1.lists[3].elements[2] = 2;\n\n list1.lists[3].elements[3] = 3; list1.lists[3].elements[4] = 6; list1.lists[3].elements[5] = 7;\n\n list1.lists[4].size = 2; list1.lists[4].elements[0] = 9; list1.lists[4].elements[1] = 11;\n\n list1.lists[5].size = 4; list1.lists[5].elements[0] = 13; list1.lists[5].elements[1] = 14;\n\n list1.lists[5].elements[2] = 15; list1.lists[5].elements[3] = 17;\n\n\n\n ListOfLists expected1;\n\n expected1.size = 1;\n\n expected1.lists[0].size = 4; expected1.lists[0].elements[0] = 13; expected1.lists[0].elements[1] = 14;\n\n expected1.lists[0].elements[2] = 15; expected1.lists[0].elements[3] = 17;\n\n\n\n ListOfLists result1 = func0(list1, 13, 17);\n\n assert(compare_lists(result1, expected1));\n\n\n\n ListOfLists expected2;\n\n expected2.size = 2;\n\n expected2.lists[0].size = 1; expected2.lists[0].elements[0] = 2;\n\n expected2.lists[1].size = 3; expected2.lists[1].elements[0] = 1; expected2.lists[1].elements[1] = 2; expected2.lists[1].elements[2] = 3;\n\n\n\n ListOfLists result2 = func0(list1, 1, 3);\n\n assert(compare_lists(result2, expected2));\n\n\n\n ListOfLists expected3;\n\n expected3.size = 4;\n\n expected3.lists[0].size = 1; expected3.lists[0].elements[0] = 2;\n\n expected3.lists[1].size = 1; expected3.lists[1].elements[0] = 0;\n\n expected3.lists[2].size = 3; expected3.lists[2].elements[0] = 1; expected3.lists[2].elements[1] = 2; expected3.lists[2].elements[2] = 3;\n\n expected3.lists[3].size = 6; expected3.lists[3].elements[0] = 0; expected3.lists[3].elements[1] = 1;\n\n expected3.lists[3].elements[2] = 2; expected3.lists[3].elements[3] = 3; expected3.lists[3].elements[4] = 6; expected3.lists[3].elements[5] = 7;\n\n\n\n ListOfLists result3 = func0(list1, 0, 7);\n\n assert(compare_lists(result3, expected3));\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x1f8,%rsp\nmov %rdi,-0x1f8(%rbp)\nmov %esi,-0x1fc(%rbp)\nmov %edx,-0x200(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmovl $0x0,-0x28(%rbp)\nmovl $0x0,-0x1f0(%rbp)\njmpq 14f1 \nmov -0x1f0(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nlea 0x10(%rbp),%rbx\nadd %rbx,%rax\nmov (%rax),%eax\nmov %eax,-0x1ec(%rbp)\nmov -0x1f0(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nlea 0x10(%rbp),%rbx\nadd %rbx,%rax\nmov (%rax),%eax\nmov %eax,-0x1e8(%rbp)\nmovl $0x1,-0x1e4(%rbp)\njmpq 1416 \nmov -0x1e4(%rbp),%eax\nmovslq %eax,%rcx\nmov -0x1f0(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nadd %rcx,%rax\nmov 0x10(%rbp,%rax,4),%eax\ncmp %eax,-0x1ec(%rbp)\njle 13af \nmov -0x1e4(%rbp),%eax\nmovslq %eax,%rcx\nmov -0x1f0(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nadd %rcx,%rax\nmov 0x10(%rbp,%rax,4),%eax\nmov %eax,-0x1ec(%rbp)\nmov -0x1e4(%rbp),%eax\nmovslq %eax,%rcx\nmov -0x1f0(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nadd %rcx,%rax\nmov 0x10(%rbp,%rax,4),%eax\ncmp %eax,-0x1e8(%rbp)\njge 140f \nmov -0x1e4(%rbp),%eax\nmovslq %eax,%rcx\nmov -0x1f0(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nadd %rcx,%rax\nmov 0x10(%rbp,%rax,4),%eax\nmov %eax,-0x1e8(%rbp)\naddl $0x1,-0x1e4(%rbp)\nmov -0x1f0(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nlea 0x10(%rbp),%rbx\nadd %rbx,%rax\nadd $0x28,%rax\nmov (%rax),%eax\ncmp %eax,-0x1e4(%rbp)\njl 134f \nmov -0x1ec(%rbp),%eax\ncmp -0x1fc(%rbp),%eax\njl 14ea \nmov -0x1e8(%rbp),%eax\ncmp -0x200(%rbp),%eax\njg 14ea \nmov -0x28(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x28(%rbp)\nmovslq %eax,%rdx\nmov %rdx,%rax\nshl $0x2,%rax\nadd %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nlea -0x10(%rbp),%rbx\nadd %rbx,%rax\nlea -0x1d0(%rax),%rdx\nmov -0x1f0(%rbp),%eax\nmovslq %eax,%rcx\nmov %rcx,%rax\nshl $0x2,%rax\nadd %rcx,%rax\nadd %rax,%rax\nadd %rcx,%rax\nshl $0x2,%rax\nlea 0x10(%rbp),%rdi\nadd %rdi,%rax\nmov (%rax),%rcx\nmov 0x8(%rax),%rbx\nmov %rcx,(%rdx)\nmov %rbx,0x8(%rdx)\nmov 0x10(%rax),%rcx\nmov 0x18(%rax),%rbx\nmov %rcx,0x10(%rdx)\nmov %rbx,0x18(%rdx)\nmov 0x20(%rax),%rcx\nmov %rcx,0x20(%rdx)\nmov 0x28(%rax),%eax\nmov %eax,0x28(%rdx)\naddl $0x1,-0x1f0(%rbp)\nmov 0x1c8(%rbp),%eax\ncmp %eax,-0x1f0(%rbp)\njl 12e8 \nmov -0x1f8(%rbp),%rax\nmov %rax,%rdx\nlea -0x1e0(%rbp),%rax\nmov $0x1bc,%ecx\nmov (%rax),%rsi\nmov %rsi,(%rdx)\nmov %ecx,%esi\nadd %rdx,%rsi\nlea 0x8(%rsi),%rdi\nmov %ecx,%esi\nadd %rax,%rsi\nadd $0x8,%rsi\nmov -0x10(%rsi),%rsi\nmov %rsi,-0x10(%rdi)\nlea 0x8(%rdx),%rdi\nand $0xfffffffffffffff8,%rdi\nsub %rdi,%rdx\nsub %rdx,%rax\nadd %edx,%ecx\nand $0xfffffff8,%ecx\nshr $0x3,%ecx\nmov %ecx,%edx\nmov %edx,%edx\nmov %rax,%rsi\nmov %rdx,%rcx\nrep movsq %ds:(%rsi),%es:(%rdi)\nmov -0x18(%rbp),%rax\nxor %fs:0x28,%rax\nje 1570 \ncallq 1060 <__stack_chk_fail@plt>\nmov -0x1f8(%rbp),%rax\nadd $0x1f8,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 1F8h\nmov [rbp+var_1F8], rdi\nmov [rbp+var_1FC], esi\nmov [rbp+var_200], edx\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov [rbp+var_28], 0\nmov [rbp+var_1F0], 0\njmp loc_14F7\nloc_12E8:\nmov eax, [rbp+var_1F0]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nlea rax, [rax+10h]\nadd rax, rbp\nmov eax, [rax]\nmov [rbp+var_1EC], eax\nmov eax, [rbp+var_1F0]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nlea rax, [rax+10h]\nadd rax, rbp\nmov eax, [rax]\nmov [rbp+var_1E8], eax\nmov [rbp+var_1E4], 1\njmp loc_1416\nloc_134F:\nmov eax, [rbp+var_1E4]\nmovsxd rcx, eax\nmov eax, [rbp+var_1F0]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nadd rax, rax\nadd rax, rdx\nadd rax, rcx\nmov eax, [rbp+rax*4+arg_0]\ncmp [rbp+var_1EC], eax\njle short loc_13AF\nmov eax, [rbp+var_1E4]\nmovsxd rcx, eax\nmov eax, [rbp+var_1F0]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nadd rax, rax\nadd rax, rdx\nadd rax, rcx\nmov eax, [rbp+rax*4+arg_0]\nmov [rbp+var_1EC], eax\nloc_13AF:\nmov eax, [rbp+var_1E4]\nmovsxd rcx, eax\nmov eax, [rbp+var_1F0]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nadd rax, rax\nadd rax, rdx\nadd rax, rcx\nmov eax, [rbp+rax*4+arg_0]\ncmp [rbp+var_1E8], eax\njge short loc_140F\nmov eax, [rbp+var_1E4]\nmovsxd rcx, eax\nmov eax, [rbp+var_1F0]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nadd rax, rax\nadd rax, rdx\nadd rax, rcx\nmov eax, [rbp+rax*4+arg_0]\nmov [rbp+var_1E8], eax\nloc_140F:\nadd [rbp+var_1E4], 1\nloc_1416:\nmov eax, [rbp+var_1F0]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nlea rax, [rax+10h]\nadd rax, rbp\nadd rax, 28h ; '('\nmov eax, [rax]\ncmp [rbp+var_1E4], eax\njl loc_134F\nmov eax, [rbp+var_1EC]\ncmp eax, [rbp+var_1FC]\njl loc_14F0\nmov eax, [rbp+var_1E8]\ncmp eax, [rbp+var_200]\njg loc_14F0\nmov eax, [rbp+var_28]\nlea edx, [rax+1]\nmov [rbp+var_28], edx\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nlea rax, [rax-10h]\nadd rax, rbp\nlea rdx, [rax-1D0h]\nmov eax, [rbp+var_1F0]\nmovsxd rcx, eax\nmov rax, rcx\nshl rax, 2\nadd rax, rcx\nadd rax, rax\nadd rax, rcx\nshl rax, 2\nlea rax, [rax+10h]\nadd rax, rbp\nmov rcx, [rax]\nmov rbx, [rax+8]\nmov [rdx], rcx\nmov [rdx+8], rbx\nmov rcx, [rax+10h]\nmov rbx, [rax+18h]\nmov [rdx+10h], rcx\nmov [rdx+18h], rbx\nmov rcx, [rax+1Ch]\nmov rbx, [rax+24h]\nmov [rdx+1Ch], rcx\nmov [rdx+24h], rbx\nloc_14F0:\nadd [rbp+var_1F0], 1\nloc_14F7:\nmov eax, [rbp+arg_1B8]\ncmp [rbp+var_1F0], eax\njl loc_12E8\nmov rax, [rbp+var_1F8]\nmov rdx, rax\nlea rax, [rbp+var_1E0]\nmov ecx, 1BCh\nmov rsi, [rax]\nmov [rdx], rsi\nmov esi, ecx\nadd rsi, rdx\nlea rdi, [rsi+8]\nmov esi, ecx\nadd rsi, rax\nadd rsi, 8\nmov rsi, [rsi-10h]\nmov [rdi-10h], rsi\nlea rdi, [rdx+8]\nand rdi, 0FFFFFFFFFFFFFFF8h\nsub rdx, rdi\nsub rax, rdx\nadd ecx, edx\nand ecx, 0FFFFFFF8h\nshr ecx, 3\nmov edx, ecx\nmov edx, edx\nmov rsi, rax\nmov rcx, rdx\nrep movsq\nmov rax, [rbp+var_18]\nsub rax, fs:28h\njz short loc_1576\ncall ___stack_chk_fail\nloc_1576:\nmov rax, [rbp+var_1F8]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(\n _QWORD *a1,\n int a2,\n int a3,\n __int64 a4,\n __int64 a5,\n __int64 a6,\n int a7,\n int a8,\n int a9,\n int a10,\n int a11,\n int a12,\n int a13,\n int a14,\n int a15,\n int a16,\n int a17,\n int a18,\n int a19,\n int a20,\n int a21,\n int a22,\n int a23,\n int a24,\n int a25,\n int a26,\n int a27,\n int a28,\n int a29,\n int a30,\n int a31,\n int a32,\n int a33,\n int a34,\n int a35,\n int a36,\n int a37,\n int a38,\n int a39,\n int a40,\n int a41,\n int a42,\n int a43,\n int a44,\n int a45,\n int a46,\n int a47,\n int a48,\n int a49,\n int a50,\n int a51,\n int a52,\n int a53,\n int a54,\n int a55,\n int a56,\n int a57,\n int a58,\n int a59,\n int a60,\n int a61,\n int a62)\n{\n int v62; // eax\n _QWORD *v63; // rdx\n _QWORD *v64; // rax\n __int64 v65; // rbx\n __int64 v66; // rbx\n __int64 v67; // rbx\n int i; // [rsp+10h] [rbp-1F0h]\n int v71; // [rsp+14h] [rbp-1ECh]\n int v72; // [rsp+18h] [rbp-1E8h]\n int j; // [rsp+1Ch] [rbp-1E4h]\n _QWORD v74[54]; // [rsp+20h] [rbp-1E0h] BYREF\n __int64 v75; // [rsp+1D4h] [rbp-2Ch]\n unsigned __int64 v76; // [rsp+1E8h] [rbp-18h]\n __int64 savedregs; // [rsp+200h] [rbp+0h] BYREF\n\n v76 = __readfsqword(0x28u);\n HIDWORD(v75) = 0;\n for ( i = 0; i < a62; ++i )\n {\n v71 = *((_DWORD *)&savedregs + 11 * i + 4);\n v72 = v71;\n for ( j = 1; j < *(&a10 + 11 * i + 4); ++j )\n {\n if ( v71 > *(&a7 + 11 * i + j) )\n v71 = *(&a7 + 11 * i + j);\n if ( v72 < *(&a7 + 11 * i + j) )\n v72 = *(&a7 + 11 * i + j);\n }\n if ( v71 >= a2 && v72 <= a3 )\n {\n v62 = HIDWORD(v75)++;\n v63 = (_QWORD *)((char *)v74 + 44 * v62);\n v64 = (__int64 *)((char *)&savedregs + 44 * i + 16);\n v65 = v64[1];\n *v63 = *v64;\n v63[1] = v65;\n v66 = v64[3];\n v63[2] = v64[2];\n v63[3] = v66;\n v67 = *(_QWORD *)((char *)v64 + 36);\n *(_QWORD *)((char *)v63 + 28) = *(_QWORD *)((char *)v64 + 28);\n *(_QWORD *)((char *)v63 + 36) = v67;\n }\n }\n *a1 = v74[0];\n *(_QWORD *)((char *)a1 + 436) = v75;\n qmemcpy(\n (void *)((unsigned __int64)(a1 + 1) & 0xFFFFFFFFFFFFFFF8LL),\n (const void *)((char *)v74 - ((char *)a1 - ((unsigned __int64)(a1 + 1) & 0xFFFFFFFFFFFFFFF8LL))),\n 8LL * ((((_DWORD)a1 - (((_DWORD)a1 + 8) & 0xFFFFFFF8) + 444) & 0xFFFFFFF8) >> 3));\n return a1;\n}", + "ida_strip_asm": "sub_12A0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 1F8h\nmov [rbp+var_1F8], rdi\nmov [rbp+var_1FC], esi\nmov [rbp+var_200], edx\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov [rbp+var_28], 0\nmov [rbp+var_1F0], 0\njmp loc_14F7\nloc_12E8:\nmov eax, [rbp+var_1F0]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nlea rax, [rax+10h]\nadd rax, rbp\nmov eax, [rax]\nmov [rbp+var_1EC], eax\nmov eax, [rbp+var_1F0]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nlea rax, [rax+10h]\nadd rax, rbp\nmov eax, [rax]\nmov [rbp+var_1E8], eax\nmov [rbp+var_1E4], 1\njmp loc_1416\nloc_134F:\nmov eax, [rbp+var_1E4]\nmovsxd rcx, eax\nmov eax, [rbp+var_1F0]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nadd rax, rax\nadd rax, rdx\nadd rax, rcx\nmov eax, [rbp+rax*4+arg_0]\ncmp [rbp+var_1EC], eax\njle short loc_13AF\nmov eax, [rbp+var_1E4]\nmovsxd rcx, eax\nmov eax, [rbp+var_1F0]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nadd rax, rax\nadd rax, rdx\nadd rax, rcx\nmov eax, [rbp+rax*4+arg_0]\nmov [rbp+var_1EC], eax\nloc_13AF:\nmov eax, [rbp+var_1E4]\nmovsxd rcx, eax\nmov eax, [rbp+var_1F0]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nadd rax, rax\nadd rax, rdx\nadd rax, rcx\nmov eax, [rbp+rax*4+arg_0]\ncmp [rbp+var_1E8], eax\njge short loc_140F\nmov eax, [rbp+var_1E4]\nmovsxd rcx, eax\nmov eax, [rbp+var_1F0]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nadd rax, rax\nadd rax, rdx\nadd rax, rcx\nmov eax, [rbp+rax*4+arg_0]\nmov [rbp+var_1E8], eax\nloc_140F:\nadd [rbp+var_1E4], 1\nloc_1416:\nmov eax, [rbp+var_1F0]\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nlea rax, [rax+10h]\nadd rax, rbp\nadd rax, 28h ; '('\nmov eax, [rax]\ncmp [rbp+var_1E4], eax\njl loc_134F\nmov eax, [rbp+var_1EC]\ncmp eax, [rbp+var_1FC]\njl loc_14F0\nmov eax, [rbp+var_1E8]\ncmp eax, [rbp+var_200]\njg loc_14F0\nmov eax, [rbp+var_28]\nlea edx, [rax+1]\nmov [rbp+var_28], edx\nmovsxd rdx, eax\nmov rax, rdx\nshl rax, 2\nadd rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nlea rax, [rax-10h]\nadd rax, rbp\nlea rdx, [rax-1D0h]\nmov eax, [rbp+var_1F0]\nmovsxd rcx, eax\nmov rax, rcx\nshl rax, 2\nadd rax, rcx\nadd rax, rax\nadd rax, rcx\nshl rax, 2\nlea rax, [rax+10h]\nadd rax, rbp\nmov rcx, [rax]\nmov rbx, [rax+8]\nmov [rdx], rcx\nmov [rdx+8], rbx\nmov rcx, [rax+10h]\nmov rbx, [rax+18h]\nmov [rdx+10h], rcx\nmov [rdx+18h], rbx\nmov rcx, [rax+1Ch]\nmov rbx, [rax+24h]\nmov [rdx+1Ch], rcx\nmov [rdx+24h], rbx\nloc_14F0:\nadd [rbp+var_1F0], 1\nloc_14F7:\nmov eax, [rbp+arg_1B8]\ncmp [rbp+var_1F0], eax\njl loc_12E8\nmov rax, [rbp+var_1F8]\nmov rdx, rax\nlea rax, [rbp+var_1E0]\nmov ecx, 1BCh\nmov rsi, [rax]\nmov [rdx], rsi\nmov esi, ecx\nadd rsi, rdx\nlea rdi, [rsi+8]\nmov esi, ecx\nadd rsi, rax\nadd rsi, 8\nmov rsi, [rsi-10h]\nmov [rdi-10h], rsi\nlea rdi, [rdx+8]\nand rdi, 0FFFFFFFFFFFFFFF8h\nsub rdx, rdi\nsub rax, rdx\nadd ecx, edx\nand ecx, 0FFFFFFF8h\nshr ecx, 3\nmov edx, ecx\nmov edx, edx\nmov rsi, rax\nmov rcx, rdx\nrep movsq\nmov rax, [rbp+var_18]\nsub rax, fs:28h\njz short loc_1576\ncall ___stack_chk_fail\nloc_1576:\nmov rax, [rbp+var_1F8]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_12A0(\n _QWORD *a1,\n int a2,\n int a3,\n __int64 a4,\n __int64 a5,\n __int64 a6,\n int a7,\n int a8,\n int a9,\n int a10,\n int a11,\n int a12,\n int a13,\n int a14,\n int a15,\n int a16,\n int a17,\n int a18,\n int a19,\n int a20,\n int a21,\n int a22,\n int a23,\n int a24,\n int a25,\n int a26,\n int a27,\n int a28,\n int a29,\n int a30,\n int a31,\n int a32,\n int a33,\n int a34,\n int a35,\n int a36,\n int a37,\n int a38,\n int a39,\n int a40,\n int a41,\n int a42,\n int a43,\n int a44,\n int a45,\n int a46,\n int a47,\n int a48,\n int a49,\n int a50,\n int a51,\n int a52,\n int a53,\n int a54,\n int a55,\n int a56,\n int a57,\n int a58,\n int a59,\n int a60,\n int a61,\n int a62)\n{\n int v62; // eax\n _QWORD *v63; // rdx\n _QWORD *v64; // rax\n __int64 v65; // rbx\n __int64 v66; // rbx\n __int64 v67; // rbx\n int i; // [rsp+10h] [rbp-1F0h]\n int v71; // [rsp+14h] [rbp-1ECh]\n int v72; // [rsp+18h] [rbp-1E8h]\n int j; // [rsp+1Ch] [rbp-1E4h]\n _QWORD v74[54]; // [rsp+20h] [rbp-1E0h] BYREF\n __int64 v75; // [rsp+1D4h] [rbp-2Ch]\n unsigned __int64 v76; // [rsp+1E8h] [rbp-18h]\n __int64 savedregs; // [rsp+200h] [rbp+0h] BYREF\n\n v76 = __readfsqword(0x28u);\n HIDWORD(v75) = 0;\n for ( i = 0; i < a62; ++i )\n {\n v71 = *((_DWORD *)&savedregs + 11 * i + 4);\n v72 = v71;\n for ( j = 1; j < *(&a10 + 11 * i + 4); ++j )\n {\n if ( v71 > *(&a7 + 11 * i + j) )\n v71 = *(&a7 + 11 * i + j);\n if ( v72 < *(&a7 + 11 * i + j) )\n v72 = *(&a7 + 11 * i + j);\n }\n if ( v71 >= a2 && v72 <= a3 )\n {\n v62 = HIDWORD(v75)++;\n v63 = (_QWORD *)((char *)v74 + 44 * v62);\n v64 = (__int64 *)((char *)&savedregs + 44 * i + 16);\n v65 = v64[1];\n *v63 = *v64;\n v63[1] = v65;\n v66 = v64[3];\n v63[2] = v64[2];\n v63[3] = v66;\n v67 = *(_QWORD *)((char *)v64 + 36);\n *(_QWORD *)((char *)v63 + 28) = *(_QWORD *)((char *)v64 + 28);\n *(_QWORD *)((char *)v63 + 36) = v67;\n }\n }\n *a1 = v74[0];\n *(_QWORD *)((char *)a1 + 436) = v75;\n qmemcpy(\n (void *)((unsigned __int64)(a1 + 1) & 0xFFFFFFFFFFFFFFF8LL),\n (const void *)((char *)v74 - ((char *)a1 - ((unsigned __int64)(a1 + 1) & 0xFFFFFFFFFFFFFFF8LL))),\n 8LL * ((((_DWORD)a1 - (((_DWORD)a1 + 8) & 0xFFFFFFF8) + 444) & 0xFFFFFFF8) >> 3));\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_12A0(uint64_t *a1, int a2, int a3, long long a4, long long a5,\n long long a6, int a7, int a8, int a9, int a10, int a11,\n int a12, int a13, int a14, int a15, int a16, int a17,\n int a18, int a19, int a20, int a21, int a22, int a23,\n int a24, int a25, int a26, int a27, int a28, int a29,\n int a30, int a31, int a32, int a33, int a34, int a35,\n int a36, int a37, int a38, int a39, int a40, int a41,\n int a42, int a43, int a44, int a45, int a46, int a47,\n int a48, int a49, int a50, int a51, int a52, int a53,\n int a54, int a55, int a56, int a57, int a58, int a59,\n int a60, int a61, int a62) {\n int v62;\n uint64_t *v63;\n uint64_t *v64;\n long long v65;\n long long v66;\n long long v67;\n int i;\n int v71;\n int v72;\n int j;\n uint64_t v74[54];\n long long v75;\n unsigned long long v76;\n long long savedregs;\n v76 = __readfsqword(40u);\n HIDWORD(v75) = 0;\n for (i = 0; i < a62; ++i) {\n v71 = *((uint32_t *)&savedregs + 11 * i + 4);\n v72 = v71;\n for (j = 1; j < *(&a10 + 11 * i + 4); ++j) {\n if (v71 > *(&a7 + 11 * i + j)) v71 = *(&a7 + 11 * i + j);\n if (v72 < *(&a7 + 11 * i + j)) v72 = *(&a7 + 11 * i + j);\n }\n if (v71 >= a2 && v72 <= a3) {\n v62 = HIDWORD(v75)++;\n v63 = (uint64_t *)((char *)v74 + 44 * v62);\n v64 = (long long *)((char *)&savedregs + 44 * i + 16);\n v65 = v64[1];\n *v63 = *v64;\n v63[1] = v65;\n v66 = v64[3];\n v63[2] = v64[2];\n v63[3] = v66;\n v67 = *(uint64_t *)((char *)v64 + 36);\n *(uint64_t *)((char *)v63 + 28) = *(uint64_t *)((char *)v64 + 28);\n *(uint64_t *)((char *)v63 + 36) = v67;\n }\n }\n *a1 = v74[0];\n *(uint64_t *)((char *)a1 + 436) = v75;\n qmemcpy(\n (void *)((unsigned long long)(a1 + 1) & 18446744073709551608LL),\n (const void *)((char *)v74 - ((char *)a1 - ((unsigned long long)(a1 + 1) &\n 18446744073709551608LL))),\n 8LL * ((((uint32_t)a1 - (((uint32_t)a1 + 8) & 4294967288) + 444) &\n 4294967288) >>\n 3));\n return a1;\n}", + "ida_pseudo_norm": "uint64_t *func0(uint64_t *a1, int a2, int a3, long long a4, long long a5,\n long long a6, int a7, int a8, int a9, int a10, int a11, int a12,\n int a13, int a14, int a15, int a16, int a17, int a18, int a19,\n int a20, int a21, int a22, int a23, int a24, int a25, int a26,\n int a27, int a28, int a29, int a30, int a31, int a32, int a33,\n int a34, int a35, int a36, int a37, int a38, int a39, int a40,\n int a41, int a42, int a43, int a44, int a45, int a46, int a47,\n int a48, int a49, int a50, int a51, int a52, int a53, int a54,\n int a55, int a56, int a57, int a58, int a59, int a60, int a61,\n int a62) {\n int v62;\n uint64_t *v63;\n uint64_t *v64;\n long long v65;\n long long v66;\n long long v67;\n int i;\n int v71;\n int v72;\n int j;\n uint64_t v74[54];\n long long v75;\n unsigned long long v76;\n long long savedregs;\n v76 = __readfsqword(40u);\n HIDWORD(v75) = 0;\n for (i = 0; i < a62; ++i) {\n v71 = *((uint32_t *)&savedregs + 11 * i + 4);\n v72 = v71;\n for (j = 1; j < *(&a10 + 11 * i + 4); ++j) {\n if (v71 > *(&a7 + 11 * i + j)) v71 = *(&a7 + 11 * i + j);\n if (v72 < *(&a7 + 11 * i + j)) v72 = *(&a7 + 11 * i + j);\n }\n if (v71 >= a2 && v72 <= a3) {\n v62 = HIDWORD(v75)++;\n v63 = (uint64_t *)((char *)v74 + 44 * v62);\n v64 = (long long *)((char *)&savedregs + 44 * i + 16);\n v65 = v64[1];\n *v63 = *v64;\n v63[1] = v65;\n v66 = v64[3];\n v63[2] = v64[2];\n v63[3] = v66;\n v67 = *(uint64_t *)((char *)v64 + 36);\n *(uint64_t *)((char *)v63 + 28) = *(uint64_t *)((char *)v64 + 28);\n *(uint64_t *)((char *)v63 + 36) = v67;\n }\n }\n *a1 = v74[0];\n *(uint64_t *)((char *)a1 + 436) = v75;\n qmemcpy(\n (void *)((unsigned long long)(a1 + 1) & 18446744073709551608LL),\n (const void *)((char *)v74 - ((char *)a1 - ((unsigned long long)(a1 + 1) &\n 18446744073709551608LL))),\n 8LL * ((((uint32_t)a1 - (((uint32_t)a1 + 8) & 4294967288) + 444) &\n 4294967288) >>\n 3));\n return a1;\n}" + }, + { + "index": 869, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int elements[10];\n\n int size;\n\n} IntList;\n\n\n\ntypedef struct {\n\n IntList lists[10];\n\n int size;\n\n} ListOfLists;\n\n\n\nint compare_lists(ListOfLists a, ListOfLists b) {\n\n if(a.size != b.size) return 0;\n\n for(int i = 0; i < a.size; i++) {\n\n if(a.lists[i].size != b.lists[i].size) return 0;\n\n for(int j = 0; j < a.lists[i].size; j++) {\n\n if(a.lists[i].elements[j] != b.lists[i].elements[j]) return 0;\n\n }\n\n }\n\n return 1;\n\n}\n\n\n\n", + "func": "ListOfLists func0(ListOfLists list1, int leftrange, int rigthrange) {\n ListOfLists result;\n result.size = 0;\n for (int i = 0; i < list1.size; i++) {\n int min = list1.lists[i].elements[0];\n int max = list1.lists[i].elements[0];\n for (int j = 1; j < list1.lists[i].size; j++) {\n if (list1.lists[i].elements[j] < min) min = list1.lists[i].elements[j];\n if (list1.lists[i].elements[j] > max) max = list1.lists[i].elements[j];\n }\n if (min >= leftrange && max <= rigthrange) {\n result.lists[result.size++] = list1.lists[i];\n }\n }\n return result;\n}", + "test": "int main() {\n\n ListOfLists list1;\n\n list1.size = 6;\n\n list1.lists[0].size = 1; list1.lists[0].elements[0] = 2;\n\n list1.lists[1].size = 1; list1.lists[1].elements[0] = 0;\n\n list1.lists[2].size = 3; list1.lists[2].elements[0] = 1; list1.lists[2].elements[1] = 2; list1.lists[2].elements[2] = 3;\n\n list1.lists[3].size = 6; list1.lists[3].elements[0] = 0; list1.lists[3].elements[1] = 1; list1.lists[3].elements[2] = 2;\n\n list1.lists[3].elements[3] = 3; list1.lists[3].elements[4] = 6; list1.lists[3].elements[5] = 7;\n\n list1.lists[4].size = 2; list1.lists[4].elements[0] = 9; list1.lists[4].elements[1] = 11;\n\n list1.lists[5].size = 4; list1.lists[5].elements[0] = 13; list1.lists[5].elements[1] = 14;\n\n list1.lists[5].elements[2] = 15; list1.lists[5].elements[3] = 17;\n\n\n\n ListOfLists expected1;\n\n expected1.size = 1;\n\n expected1.lists[0].size = 4; expected1.lists[0].elements[0] = 13; expected1.lists[0].elements[1] = 14;\n\n expected1.lists[0].elements[2] = 15; expected1.lists[0].elements[3] = 17;\n\n\n\n ListOfLists result1 = func0(list1, 13, 17);\n\n assert(compare_lists(result1, expected1));\n\n\n\n ListOfLists expected2;\n\n expected2.size = 2;\n\n expected2.lists[0].size = 1; expected2.lists[0].elements[0] = 2;\n\n expected2.lists[1].size = 3; expected2.lists[1].elements[0] = 1; expected2.lists[1].elements[1] = 2; expected2.lists[1].elements[2] = 3;\n\n\n\n ListOfLists result2 = func0(list1, 1, 3);\n\n assert(compare_lists(result2, expected2));\n\n\n\n ListOfLists expected3;\n\n expected3.size = 4;\n\n expected3.lists[0].size = 1; expected3.lists[0].elements[0] = 2;\n\n expected3.lists[1].size = 1; expected3.lists[1].elements[0] = 0;\n\n expected3.lists[2].size = 3; expected3.lists[2].elements[0] = 1; expected3.lists[2].elements[1] = 2; expected3.lists[2].elements[2] = 3;\n\n expected3.lists[3].size = 6; expected3.lists[3].elements[0] = 0; expected3.lists[3].elements[1] = 1;\n\n expected3.lists[3].elements[2] = 2; expected3.lists[3].elements[3] = 3; expected3.lists[3].elements[4] = 6; expected3.lists[3].elements[5] = 7;\n\n\n\n ListOfLists result3 = func0(list1, 0, 7);\n\n assert(compare_lists(result3, expected3));\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x1d0,%rsp\nmov %rdi,%rbx\nmov %fs:0x28,%rax\nmov %rax,0x1c8(%rsp)\nxor %eax,%eax\nmov 0x3b8(%rsp),%eax\ntest %eax,%eax\njle 12f8 \nmov %esi,%ebp\nmov %edx,%r13d\nlea 0x204(%rsp),%r10\nlea -0x1(%rax),%eax\nadd $0x1,%rax\nlea (%rax,%rax,4),%rdx\nlea (%rax,%rdx,2),%r12\nmov $0x0,%r11d\nmov $0x0,%esi\nlea 0x208(%rsp),%r14\njmp 127d \nmov %edi,%r8d\njmp 12b4 \nadd $0x2c,%r10\nadd $0xb,%r11\ncmp %r12,%r11\nje 12fd \nmov %r10,%rdx\nmov -0x4(%r10),%edi\nmov 0x24(%r10),%eax\ncmp $0x1,%eax\njle 1267 \nlea -0x2(%rax),%eax\nadd %r11,%rax\nlea (%r14,%rax,4),%r9\nmov %r10,%rcx\nmov %edi,%r8d\nmov (%rcx),%eax\ncmp %eax,%edi\ncmovg %eax,%edi\ncmp %eax,%r8d\ncmovl %eax,%r8d\nadd $0x4,%rcx\ncmp %r9,%rcx\njne 129d \ncmp %edi,%ebp\njg 126c \ncmp %r8d,%r13d\njl 126c \nmovslq %esi,%rax\nlea (%rax,%rax,4),%rcx\nlea (%rax,%rcx,2),%rax\nshl $0x2,%rax\nlea (%rsp,%rax,1),%rcx\nmovdqu -0x4(%rdx),%xmm0\nmovups %xmm0,(%rsp,%rax,1)\nmovdqu 0xc(%rdx),%xmm1\nmovups %xmm1,0x10(%rcx)\nmov 0x1c(%rdx),%rax\nmov %rax,0x20(%rcx)\nmov 0x24(%rdx),%eax\nmov %eax,0x28(%rcx)\nlea 0x1(%rsi),%esi\njmpq 126c \nmov $0x0,%esi\nmov %esi,0x1b8(%rsp)\nmov %rsp,%rsi\nmov (%rsp),%rax\nmov %rax,(%rbx)\nmov 0x1b4(%rsp),%rax\nmov %rax,0x1b4(%rbx)\nlea 0x8(%rbx),%rdi\nand $0xfffffffffffffff8,%rdi\nmov %rbx,%rax\nsub %rdi,%rax\nsub %rax,%rsi\nadd $0x1bc,%eax\nshr $0x3,%eax\nmov %eax,%ecx\nrep movsq %ds:(%rsi),%es:(%rdi)\nmov 0x1c8(%rsp),%rax\nxor %fs:0x28,%rax\njne 1361 \nmov %rbx,%rax\nadd $0x1d0,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 1D0h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+1F8h+var_30], rax\nxor eax, eax\nmov eax, [rsp+1F8h+arg_1B8]\ntest eax, eax\njle loc_12E4\nmov ebp, esi\nmov r13d, edx\nlea r8, [rsp+1F8h+arg_4]\ncdqe\nlea rdx, [rax+rax*4]\nlea r12, [rax+rdx*2]\nmov r9d, 0\nmov r11d, 0\nlea r14, [rsp+1F8h+arg_8]\njmp short loc_126D\nloc_125C:\nmov esi, ecx\njmp short loc_12A1\nloc_1260:\nadd r8, 2Ch ; ','\nadd r9, 0Bh\ncmp r9, r12\njz short loc_12EA\nloc_126D:\nmov r10, r8\nmov ecx, [r8-4]\nmov eax, [r8+24h]\ncmp eax, 1\njle short loc_125C\nlea eax, [rax-2]\nadd rax, r9\nlea rdi, [r14+rax*4]\nmov rdx, r8\nmov esi, ecx\nloc_128C:\nmov eax, [rdx]\ncmp ecx, eax\ncmovg ecx, eax\ncmp esi, eax\ncmovl esi, eax\nadd rdx, 4\ncmp rdx, rdi\njnz short loc_128C\nloc_12A1:\ncmp ebp, ecx\njg short loc_1260\ncmp r13d, esi\njl short loc_1260\nmovsxd rax, r11d\nlea rdx, [rax+rax*4]\nlea rax, [rax+rdx*2]\nshl rax, 2\nlea rdx, [rsp+rax+1F8h+var_1F8]\nmovdqu xmm0, xmmword ptr [r10-4]\nmovups [rsp+rax+1F8h+var_1F8], xmm0\nmovdqu xmm1, xmmword ptr [r10+0Ch]\nmovups xmmword ptr [rdx+10h], xmm1\nmovdqu xmm2, xmmword ptr [r10+18h]\nmovups xmmword ptr [rdx+1Ch], xmm2\nlea r11d, [r11+1]\njmp loc_1260\nloc_12E4:\nmov r11d, 0\nloc_12EA:\nmov [rsp+1F8h+var_40], r11d\nmov rsi, rsp\nmov rax, qword ptr [rsp+1F8h+var_1F8]\nmov [rbx], rax\nmov rax, [rsp+1B4h]\nmov [rbx+1B4h], rax\nlea rdi, [rbx+8]\nand rdi, 0FFFFFFFFFFFFFFF8h\nmov rax, rbx\nsub rax, rdi\nsub rsi, rax\nadd eax, 1BCh\nshr eax, 3\nmov ecx, eax\nrep movsq\nmov rax, [rsp+1F8h+var_30]\nsub rax, fs:28h\njnz short loc_134F\nmov rax, rbx\nadd rsp, 1D0h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_134F:\ncall ___stack_chk_fail", + "ida_pseudo": "_QWORD *__fastcall func0(\n _QWORD *a1,\n int a2,\n int a3,\n __int64 a4,\n __int64 a5,\n __int64 a6,\n __int64 a7,\n char a8,\n int a9,\n int a10,\n int a11,\n int a12,\n int a13,\n int a14,\n int a15,\n int a16,\n int a17,\n int a18,\n int a19,\n int a20,\n int a21,\n int a22,\n int a23,\n int a24,\n int a25,\n int a26,\n int a27,\n int a28,\n int a29,\n int a30,\n int a31,\n int a32,\n int a33,\n int a34,\n int a35,\n int a36,\n int a37,\n int a38,\n int a39,\n int a40,\n int a41,\n int a42,\n int a43,\n int a44,\n int a45,\n int a46,\n int a47,\n int a48,\n int a49,\n int a50,\n int a51,\n int a52,\n int a53,\n int a54,\n int a55,\n int a56,\n int a57,\n int a58,\n int a59,\n int a60,\n int a61,\n int a62)\n{\n char *v64; // r8\n __int64 v65; // r12\n __int64 v66; // r9\n int v67; // r11d\n int v68; // esi\n int v69; // ecx\n int v70; // eax\n char *v71; // rdx\n char *v72; // rdx\n _QWORD v74[54]; // [rsp+0h] [rbp-1F8h] BYREF\n __int64 v75; // [rsp+1B4h] [rbp-44h]\n unsigned __int64 v76; // [rsp+1C8h] [rbp-30h]\n\n v76 = __readfsqword(0x28u);\n if ( a62 <= 0 )\n {\n v67 = 0;\n }\n else\n {\n v64 = (char *)&a7 + 4;\n v65 = 11LL * a62;\n v66 = 0LL;\n v67 = 0;\n do\n {\n v69 = *((_DWORD *)v64 - 1);\n v70 = *((_DWORD *)v64 + 9);\n if ( v70 <= 1 )\n {\n v68 = *((_DWORD *)v64 - 1);\n }\n else\n {\n v71 = v64;\n v68 = *((_DWORD *)v64 - 1);\n do\n {\n if ( v69 > *(_DWORD *)v71 )\n v69 = *(_DWORD *)v71;\n if ( v68 < *(_DWORD *)v71 )\n v68 = *(_DWORD *)v71;\n v71 += 4;\n }\n while ( v71 != &a8 + 4 * v66 + 4 * (unsigned int)(v70 - 2) );\n }\n if ( a2 <= v69 && a3 >= v68 )\n {\n v72 = (char *)v74 + 44 * v67;\n *(__m128i *)v72 = _mm_loadu_si128((const __m128i *)(v64 - 4));\n *((__m128i *)v72 + 1) = _mm_loadu_si128((const __m128i *)(v64 + 12));\n *(__m128i *)(v72 + 28) = _mm_loadu_si128((const __m128i *)(v64 + 24));\n ++v67;\n }\n v64 += 44;\n v66 += 11LL;\n }\n while ( v66 != v65 );\n }\n HIDWORD(v75) = v67;\n *a1 = v74[0];\n *(_QWORD *)((char *)a1 + 436) = v75;\n qmemcpy(\n (void *)((unsigned __int64)(a1 + 1) & 0xFFFFFFFFFFFFFFF8LL),\n (const void *)((char *)v74 - ((char *)a1 - ((unsigned __int64)(a1 + 1) & 0xFFFFFFFFFFFFFFF8LL))),\n 8LL * (((unsigned int)a1 - (((_DWORD)a1 + 8) & 0xFFFFFFF8) + 444) >> 3));\n return a1;\n}", + "ida_strip_asm": "sub_11F7:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 1D0h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+1F8h+var_30], rax\nxor eax, eax\nmov eax, [rsp+1F8h+arg_1B8]\ntest eax, eax\njle loc_12E4\nmov ebp, esi\nmov r13d, edx\nlea r8, [rsp+1F8h+arg_4]\ncdqe\nlea rdx, [rax+rax*4]\nlea r12, [rax+rdx*2]\nmov r9d, 0\nmov r11d, 0\nlea r14, [rsp+1F8h+arg_8]\njmp short loc_126D\nloc_125C:\nmov esi, ecx\njmp short loc_12A1\nloc_1260:\nadd r8, 2Ch ; ','\nadd r9, 0Bh\ncmp r9, r12\njz short loc_12EA\nloc_126D:\nmov r10, r8\nmov ecx, [r8-4]\nmov eax, [r8+24h]\ncmp eax, 1\njle short loc_125C\nlea eax, [rax-2]\nadd rax, r9\nlea rdi, [r14+rax*4]\nmov rdx, r8\nmov esi, ecx\nloc_128C:\nmov eax, [rdx]\ncmp ecx, eax\ncmovg ecx, eax\ncmp esi, eax\ncmovl esi, eax\nadd rdx, 4\ncmp rdx, rdi\njnz short loc_128C\nloc_12A1:\ncmp ebp, ecx\njg short loc_1260\ncmp r13d, esi\njl short loc_1260\nmovsxd rax, r11d\nlea rdx, [rax+rax*4]\nlea rax, [rax+rdx*2]\nshl rax, 2\nlea rdx, [rsp+rax+1F8h+var_1F8]\nmovdqu xmm0, xmmword ptr [r10-4]\nmovups [rsp+rax+1F8h+var_1F8], xmm0\nmovdqu xmm1, xmmword ptr [r10+0Ch]\nmovups xmmword ptr [rdx+10h], xmm1\nmovdqu xmm2, xmmword ptr [r10+18h]\nmovups xmmword ptr [rdx+1Ch], xmm2\nlea r11d, [r11+1]\njmp loc_1260\nloc_12E4:\nmov r11d, 0\nloc_12EA:\nmov [rsp+1F8h+var_40], r11d\nmov rsi, rsp\nmov rax, qword ptr [rsp+1F8h+var_1F8]\nmov [rbx], rax\nmov rax, [rsp+1B4h]\nmov [rbx+1B4h], rax\nlea rdi, [rbx+8]\nand rdi, 0FFFFFFFFFFFFFFF8h\nmov rax, rbx\nsub rax, rdi\nsub rsi, rax\nadd eax, 1BCh\nshr eax, 3\nmov ecx, eax\nrep movsq\nmov rax, [rsp+1F8h+var_30]\nsub rax, fs:28h\njnz short loc_134F\nmov rax, rbx\nadd rsp, 1D0h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_134F:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11F7(\n _QWORD *a1,\n int a2,\n int a3,\n __int64 a4,\n __int64 a5,\n __int64 a6,\n __int64 a7,\n char a8,\n int a9,\n int a10,\n int a11,\n int a12,\n int a13,\n int a14,\n int a15,\n int a16,\n int a17,\n int a18,\n int a19,\n int a20,\n int a21,\n int a22,\n int a23,\n int a24,\n int a25,\n int a26,\n int a27,\n int a28,\n int a29,\n int a30,\n int a31,\n int a32,\n int a33,\n int a34,\n int a35,\n int a36,\n int a37,\n int a38,\n int a39,\n int a40,\n int a41,\n int a42,\n int a43,\n int a44,\n int a45,\n int a46,\n int a47,\n int a48,\n int a49,\n int a50,\n int a51,\n int a52,\n int a53,\n int a54,\n int a55,\n int a56,\n int a57,\n int a58,\n int a59,\n int a60,\n int a61,\n int a62)\n{\n char *v64; // r8\n __int64 v65; // r12\n __int64 v66; // r9\n int v67; // r11d\n int v68; // esi\n int v69; // ecx\n int v70; // eax\n char *v71; // rdx\n char *v72; // rdx\n _QWORD v74[54]; // [rsp+0h] [rbp-1F8h] BYREF\n __int64 v75; // [rsp+1B4h] [rbp-44h]\n unsigned __int64 v76; // [rsp+1C8h] [rbp-30h]\n\n v76 = __readfsqword(0x28u);\n if ( a62 <= 0 )\n {\n v67 = 0;\n }\n else\n {\n v64 = (char *)&a7 + 4;\n v65 = 11LL * a62;\n v66 = 0LL;\n v67 = 0;\n do\n {\n v69 = *((_DWORD *)v64 - 1);\n v70 = *((_DWORD *)v64 + 9);\n if ( v70 <= 1 )\n {\n v68 = *((_DWORD *)v64 - 1);\n }\n else\n {\n v71 = v64;\n v68 = *((_DWORD *)v64 - 1);\n do\n {\n if ( v69 > *(_DWORD *)v71 )\n v69 = *(_DWORD *)v71;\n if ( v68 < *(_DWORD *)v71 )\n v68 = *(_DWORD *)v71;\n v71 += 4;\n }\n while ( v71 != &a8 + 4 * v66 + 4 * (unsigned int)(v70 - 2) );\n }\n if ( a2 <= v69 && a3 >= v68 )\n {\n v72 = (char *)v74 + 44 * v67;\n *(__m128i *)v72 = _mm_loadu_si128((const __m128i *)(v64 - 4));\n *((__m128i *)v72 + 1) = _mm_loadu_si128((const __m128i *)(v64 + 12));\n *(__m128i *)(v72 + 28) = _mm_loadu_si128((const __m128i *)(v64 + 24));\n ++v67;\n }\n v64 += 44;\n v66 += 11LL;\n }\n while ( v66 != v65 );\n }\n HIDWORD(v75) = v67;\n *a1 = v74[0];\n *(_QWORD *)((char *)a1 + 436) = v75;\n qmemcpy(\n (void *)((unsigned __int64)(a1 + 1) & 0xFFFFFFFFFFFFFFF8LL),\n (const void *)((char *)v74 - ((char *)a1 - ((unsigned __int64)(a1 + 1) & 0xFFFFFFFFFFFFFFF8LL))),\n 8LL * (((unsigned int)a1 - (((_DWORD)a1 + 8) & 0xFFFFFFF8) + 444) >> 3));\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11F7(uint64_t *a1, int a2, int a3, long long a4, long long a5,\n long long a6, long long a7, char a8, int a9, int a10,\n int a11, int a12, int a13, int a14, int a15, int a16,\n int a17, int a18, int a19, int a20, int a21, int a22,\n int a23, int a24, int a25, int a26, int a27, int a28,\n int a29, int a30, int a31, int a32, int a33, int a34,\n int a35, int a36, int a37, int a38, int a39, int a40,\n int a41, int a42, int a43, int a44, int a45, int a46,\n int a47, int a48, int a49, int a50, int a51, int a52,\n int a53, int a54, int a55, int a56, int a57, int a58,\n int a59, int a60, int a61, int a62) {\n char *v64;\n long long v65;\n long long v66;\n int v67;\n int v68;\n int v69;\n int v70;\n char *v71;\n char *v72;\n uint64_t v74[54];\n long long v75;\n unsigned long long v76;\n v76 = __readfsqword(40u);\n if (a62 <= 0) {\n v67 = 0;\n } else {\n v64 = (char *)&a7 + 4;\n v65 = 11LL * a62;\n v66 = 0LL;\n v67 = 0;\n do {\n v69 = *((uint32_t *)v64 - 1);\n v70 = *((uint32_t *)v64 + 9);\n if (v70 <= 1) {\n v68 = *((uint32_t *)v64 - 1);\n } else {\n v71 = v64;\n v68 = *((uint32_t *)v64 - 1);\n do {\n if (v69 > *(uint32_t *)v71) v69 = *(uint32_t *)v71;\n if (v68 < *(uint32_t *)v71) v68 = *(uint32_t *)v71;\n v71 += 4;\n } while (v71 != &a8 + 4 * v66 + 4 * (unsigned int)(v70 - 2));\n }\n if (a2 <= v69 && a3 >= v68) {\n v72 = (char *)v74 + 44 * v67;\n *(__m128i *)v72 = _mm_loadu_si128((const __m128i *)(v64 - 4));\n *((__m128i *)v72 + 1) = _mm_loadu_si128((const __m128i *)(v64 + 12));\n *(__m128i *)(v72 + 28) = _mm_loadu_si128((const __m128i *)(v64 + 24));\n ++v67;\n }\n v64 += 44;\n v66 += 11LL;\n } while (v66 != v65);\n }\n HIDWORD(v75) = v67;\n *a1 = v74[0];\n *(uint64_t *)((char *)a1 + 436) = v75;\n qmemcpy(\n (void *)((unsigned long long)(a1 + 1) & 18446744073709551608LL),\n (const void *)((char *)v74 - ((char *)a1 - ((unsigned long long)(a1 + 1) &\n 18446744073709551608LL))),\n 8LL *\n (((unsigned int)a1 - (((uint32_t)a1 + 8) & 4294967288) + 444) >> 3));\n return a1;\n}", + "ida_pseudo_norm": "uint64_t *func0(uint64_t *a1, int a2, int a3, long long a4, long long a5,\n long long a6, long long a7, char a8, int a9, int a10, int a11,\n int a12, int a13, int a14, int a15, int a16, int a17, int a18,\n int a19, int a20, int a21, int a22, int a23, int a24, int a25,\n int a26, int a27, int a28, int a29, int a30, int a31, int a32,\n int a33, int a34, int a35, int a36, int a37, int a38, int a39,\n int a40, int a41, int a42, int a43, int a44, int a45, int a46,\n int a47, int a48, int a49, int a50, int a51, int a52, int a53,\n int a54, int a55, int a56, int a57, int a58, int a59, int a60,\n int a61, int a62) {\n char *v64;\n long long v65;\n long long v66;\n int v67;\n int v68;\n int v69;\n int v70;\n char *v71;\n char *v72;\n uint64_t v74[54];\n long long v75;\n unsigned long long v76;\n v76 = __readfsqword(40u);\n if (a62 <= 0) {\n v67 = 0;\n } else {\n v64 = (char *)&a7 + 4;\n v65 = 11LL * a62;\n v66 = 0LL;\n v67 = 0;\n do {\n v69 = *((uint32_t *)v64 - 1);\n v70 = *((uint32_t *)v64 + 9);\n if (v70 <= 1) {\n v68 = *((uint32_t *)v64 - 1);\n } else {\n v71 = v64;\n v68 = *((uint32_t *)v64 - 1);\n do {\n if (v69 > *(uint32_t *)v71) v69 = *(uint32_t *)v71;\n if (v68 < *(uint32_t *)v71) v68 = *(uint32_t *)v71;\n v71 += 4;\n } while (v71 != &a8 + 4 * v66 + 4 * (unsigned int)(v70 - 2));\n }\n if (a2 <= v69 && a3 >= v68) {\n v72 = (char *)v74 + 44 * v67;\n *(__m128i *)v72 = _mm_loadu_si128((const __m128i *)(v64 - 4));\n *((__m128i *)v72 + 1) = _mm_loadu_si128((const __m128i *)(v64 + 12));\n *(__m128i *)(v72 + 28) = _mm_loadu_si128((const __m128i *)(v64 + 24));\n ++v67;\n }\n v64 += 44;\n v66 += 11LL;\n } while (v66 != v65);\n }\n HIDWORD(v75) = v67;\n *a1 = v74[0];\n *(uint64_t *)((char *)a1 + 436) = v75;\n qmemcpy(\n (void *)((unsigned long long)(a1 + 1) & 18446744073709551608LL),\n (const void *)((char *)v74 - ((char *)a1 - ((unsigned long long)(a1 + 1) &\n 18446744073709551608LL))),\n 8LL *\n (((unsigned int)a1 - (((uint32_t)a1 + 8) & 4294967288) + 444) >> 3));\n return a1;\n}" + }, + { + "index": 869, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int elements[10];\n\n int size;\n\n} IntList;\n\n\n\ntypedef struct {\n\n IntList lists[10];\n\n int size;\n\n} ListOfLists;\n\n\n\nint compare_lists(ListOfLists a, ListOfLists b) {\n\n if(a.size != b.size) return 0;\n\n for(int i = 0; i < a.size; i++) {\n\n if(a.lists[i].size != b.lists[i].size) return 0;\n\n for(int j = 0; j < a.lists[i].size; j++) {\n\n if(a.lists[i].elements[j] != b.lists[i].elements[j]) return 0;\n\n }\n\n }\n\n return 1;\n\n}\n\n\n\n", + "func": "ListOfLists func0(ListOfLists list1, int leftrange, int rigthrange) {\n ListOfLists result;\n result.size = 0;\n for (int i = 0; i < list1.size; i++) {\n int min = list1.lists[i].elements[0];\n int max = list1.lists[i].elements[0];\n for (int j = 1; j < list1.lists[i].size; j++) {\n if (list1.lists[i].elements[j] < min) min = list1.lists[i].elements[j];\n if (list1.lists[i].elements[j] > max) max = list1.lists[i].elements[j];\n }\n if (min >= leftrange && max <= rigthrange) {\n result.lists[result.size++] = list1.lists[i];\n }\n }\n return result;\n}", + "test": "int main() {\n\n ListOfLists list1;\n\n list1.size = 6;\n\n list1.lists[0].size = 1; list1.lists[0].elements[0] = 2;\n\n list1.lists[1].size = 1; list1.lists[1].elements[0] = 0;\n\n list1.lists[2].size = 3; list1.lists[2].elements[0] = 1; list1.lists[2].elements[1] = 2; list1.lists[2].elements[2] = 3;\n\n list1.lists[3].size = 6; list1.lists[3].elements[0] = 0; list1.lists[3].elements[1] = 1; list1.lists[3].elements[2] = 2;\n\n list1.lists[3].elements[3] = 3; list1.lists[3].elements[4] = 6; list1.lists[3].elements[5] = 7;\n\n list1.lists[4].size = 2; list1.lists[4].elements[0] = 9; list1.lists[4].elements[1] = 11;\n\n list1.lists[5].size = 4; list1.lists[5].elements[0] = 13; list1.lists[5].elements[1] = 14;\n\n list1.lists[5].elements[2] = 15; list1.lists[5].elements[3] = 17;\n\n\n\n ListOfLists expected1;\n\n expected1.size = 1;\n\n expected1.lists[0].size = 4; expected1.lists[0].elements[0] = 13; expected1.lists[0].elements[1] = 14;\n\n expected1.lists[0].elements[2] = 15; expected1.lists[0].elements[3] = 17;\n\n\n\n ListOfLists result1 = func0(list1, 13, 17);\n\n assert(compare_lists(result1, expected1));\n\n\n\n ListOfLists expected2;\n\n expected2.size = 2;\n\n expected2.lists[0].size = 1; expected2.lists[0].elements[0] = 2;\n\n expected2.lists[1].size = 3; expected2.lists[1].elements[0] = 1; expected2.lists[1].elements[1] = 2; expected2.lists[1].elements[2] = 3;\n\n\n\n ListOfLists result2 = func0(list1, 1, 3);\n\n assert(compare_lists(result2, expected2));\n\n\n\n ListOfLists expected3;\n\n expected3.size = 4;\n\n expected3.lists[0].size = 1; expected3.lists[0].elements[0] = 2;\n\n expected3.lists[1].size = 1; expected3.lists[1].elements[0] = 0;\n\n expected3.lists[2].size = 3; expected3.lists[2].elements[0] = 1; expected3.lists[2].elements[1] = 2; expected3.lists[2].elements[2] = 3;\n\n expected3.lists[3].size = 6; expected3.lists[3].elements[0] = 0; expected3.lists[3].elements[1] = 1;\n\n expected3.lists[3].elements[2] = 2; expected3.lists[3].elements[3] = 3; expected3.lists[3].elements[4] = 6; expected3.lists[3].elements[5] = 7;\n\n\n\n ListOfLists result3 = func0(list1, 0, 7);\n\n assert(compare_lists(result3, expected3));\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\nmov %rdi,%r12\npush %rbp\npush %rbx\nsub $0x1d8,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x1c8(%rsp)\nxor %eax,%eax\nmov 0x3b8(%rsp),%eax\ntest %eax,%eax\njle 1768 \nsub $0x1,%eax\nmov %edx,%ebp\nlea 0x204(%rsp),%r10\nxor %r11d,%r11d\nadd $0x1,%rax\nlea 0x208(%rsp),%r13\nlea (%rax,%rax,4),%rdx\nlea (%rax,%rdx,2),%rbx\nxor %edx,%edx\nnopl 0x0(%rax)\nmov 0x24(%r10),%eax\nmov -0x4(%r10),%edi\ncmp $0x1,%eax\njle 1760 \nsub $0x2,%eax\nmov %r10,%rcx\nmov %edi,%r8d\nadd %r11,%rax\nlea 0x0(%r13,%rax,4),%r9\nnopw 0x0(%rax,%rax,1)\nmov (%rcx),%eax\ncmp %eax,%edi\ncmovg %eax,%edi\ncmp %eax,%r8d\ncmovl %eax,%r8d\nadd $0x4,%rcx\ncmp %r9,%rcx\njne 1688 \ncmp %edi,%esi\njg 16e1 \ncmp %r8d,%ebp\njl 16e1 \nmovslq %edx,%rax\nmovdqu -0x4(%r10),%xmm0\nmovdqu 0xc(%r10),%xmm1\nadd $0x1,%edx\nlea (%rax,%rax,4),%rcx\nlea (%rax,%rcx,2),%rax\nshl $0x2,%rax\nlea (%rsp,%rax,1),%rcx\nmovups %xmm0,(%rsp,%rax,1)\nmov 0x1c(%r10),%rax\nmovups %xmm1,0x10(%rcx)\nmov %rax,0x20(%rcx)\nmov 0x24(%r10),%eax\nmov %eax,0x28(%rcx)\nadd $0xb,%r11\nadd $0x2c,%r10\ncmp %rbx,%r11\njne 1660 \nmov (%rsp),%rax\nmov %edx,0x1b8(%rsp)\nlea 0x8(%r12),%rdi\nmov %rsp,%rsi\nand $0xfffffffffffffff8,%rdi\nmov %rax,(%r12)\nmov 0x1b4(%rsp),%rax\nmov %rax,0x1b4(%r12)\nmov %r12,%rax\nsub %rdi,%rax\nsub %rax,%rsi\nadd $0x1bc,%eax\nshr $0x3,%eax\nmov %eax,%ecx\nrep movsq %ds:(%rsi),%es:(%rdi)\nmov 0x1c8(%rsp),%rax\nxor %fs:0x28,%rax\njne 176c \nadd $0x1d8,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopw 0x0(%rax,%rax,1)\nmov %edi,%r8d\njmpq 169f \nxor %edx,%edx\njmp 16f2 \ncallq 1060 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r13\nmov r11, rdi\npush r12\npush rbp\npush rbx\nsub rsp, 1D8h\nmov rax, fs:28h\nmov [rsp+1F8h+var_30], rax\nxor eax, eax\nmovsxd rax, [rsp+1F8h+arg_1B8]\ntest eax, eax\njle loc_16B7\nmov r12d, edx\nlea rdx, [rax+rax*4]\nmov ebx, esi\nxor r9d, r9d\nlea r8, [rsp+1F8h+arg_4]\nlea rbp, [rax+rdx*2]\nxor r10d, r10d\nlea r13, [rsp+1F8h+arg_8]\nnop word ptr [rax+rax+00h]\nloc_15C0:\nmov eax, [r8+24h]\nmov ecx, [r8-4]\ncmp eax, 1\njle loc_16B0\nsub eax, 2\nmov rdx, r8\nmov esi, ecx\nadd rax, r9\nlea rdi, [r13+rax*4+0]\nnop dword ptr [rax+00000000h]\nloc_15E8:\nmov eax, [rdx]\ncmp ecx, eax\ncmovg ecx, eax\ncmp esi, eax\ncmovl esi, eax\nadd rdx, 4\ncmp rdx, rdi\njnz short loc_15E8\nloc_15FD:\ncmp ebx, ecx\njg short loc_163B\ncmp r12d, esi\njl short loc_163B\nmovsxd rax, r10d\nmovdqu xmm0, xmmword ptr [r8-4]\nmovdqu xmm1, xmmword ptr [r8+0Ch]\nadd r10d, 1\nlea rdx, [rax+rax*4]\nmovdqu xmm2, xmmword ptr [r8+18h]\nlea rax, [rax+rdx*2]\nshl rax, 2\nlea rdx, [rsp+rax+1F8h+var_1F8]\nmovups [rsp+rax+1F8h+var_1F8], xmm0\nmovups xmmword ptr [rdx+10h], xmm1\nmovups xmmword ptr [rdx+1Ch], xmm2\nloc_163B:\nadd r9, 0Bh\nadd r8, 2Ch ; ','\ncmp r9, rbp\njnz loc_15C0\nloc_164C:\nmov rax, qword ptr [rsp+1F8h+var_1F8]\nmov [rsp+1F8h+var_40], r10d\nlea rdi, [r11+8]\nmov rsi, rsp\nand rdi, 0FFFFFFFFFFFFFFF8h\nmov [r11], rax\nmov rax, [rsp+1B4h]\nmov [r11+1B4h], rax\nmov rax, r11\nsub rax, rdi\nsub rsi, rax\nadd eax, 1BCh\nshr eax, 3\nmov ecx, eax\nrep movsq\nmov rax, [rsp+1F8h+var_30]\nsub rax, fs:28h\njnz short loc_16BC\nadd rsp, 1D8h\nmov rax, r11\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_16B0:\nmov esi, ecx\njmp loc_15FD\nloc_16B7:\nxor r10d, r10d\njmp short loc_164C\nloc_16BC:\ncall ___stack_chk_fail", + "ida_pseudo": "_QWORD *__fastcall func0(\n _QWORD *a1,\n int a2,\n int a3,\n __int64 a4,\n __int64 a5,\n __int64 a6,\n __int64 a7,\n char a8,\n int a9,\n int a10,\n int a11,\n int a12,\n int a13,\n int a14,\n int a15,\n int a16,\n int a17,\n int a18,\n int a19,\n int a20,\n int a21,\n int a22,\n int a23,\n int a24,\n int a25,\n int a26,\n int a27,\n int a28,\n int a29,\n int a30,\n int a31,\n int a32,\n int a33,\n int a34,\n int a35,\n int a36,\n int a37,\n int a38,\n int a39,\n int a40,\n int a41,\n int a42,\n int a43,\n int a44,\n int a45,\n int a46,\n int a47,\n int a48,\n int a49,\n int a50,\n int a51,\n int a52,\n int a53,\n int a54,\n int a55,\n int a56,\n int a57,\n int a58,\n int a59,\n int a60,\n int a61,\n int a62)\n{\n __int64 v64; // r9\n char *v65; // r8\n __int64 v66; // rbp\n int v67; // r10d\n int v68; // eax\n int v69; // ecx\n char *v70; // rdx\n int v71; // esi\n __int64 v72; // rax\n __m128i v73; // xmm1\n __m128i v74; // xmm2\n char *v75; // rdx\n _QWORD v77[54]; // [rsp+0h] [rbp-1F8h] BYREF\n __int64 v78; // [rsp+1B4h] [rbp-44h]\n unsigned __int64 v79; // [rsp+1C8h] [rbp-30h]\n\n v79 = __readfsqword(0x28u);\n if ( a62 <= 0 )\n {\n v67 = 0;\n }\n else\n {\n v64 = 0LL;\n v65 = (char *)&a7 + 4;\n v66 = 11LL * a62;\n v67 = 0;\n do\n {\n v68 = *((_DWORD *)v65 + 9);\n v69 = *((_DWORD *)v65 - 1);\n if ( v68 <= 1 )\n {\n v71 = *((_DWORD *)v65 - 1);\n }\n else\n {\n v70 = v65;\n v71 = *((_DWORD *)v65 - 1);\n do\n {\n if ( v69 > *(_DWORD *)v70 )\n v69 = *(_DWORD *)v70;\n if ( v71 < *(_DWORD *)v70 )\n v71 = *(_DWORD *)v70;\n v70 += 4;\n }\n while ( v70 != &a8 + 4 * v64 + 4 * (unsigned int)(v68 - 2) );\n }\n if ( a2 <= v69 && a3 >= v71 )\n {\n v72 = v67;\n v73 = _mm_loadu_si128((const __m128i *)(v65 + 12));\n ++v67;\n v74 = _mm_loadu_si128((const __m128i *)(v65 + 24));\n v75 = (char *)v77 + 44 * v72;\n *(__m128i *)v75 = _mm_loadu_si128((const __m128i *)(v65 - 4));\n *((__m128i *)v75 + 1) = v73;\n *(__m128i *)(v75 + 28) = v74;\n }\n v64 += 11LL;\n v65 += 44;\n }\n while ( v64 != v66 );\n }\n HIDWORD(v78) = v67;\n *a1 = v77[0];\n *(_QWORD *)((char *)a1 + 436) = v78;\n qmemcpy(\n (void *)((unsigned __int64)(a1 + 1) & 0xFFFFFFFFFFFFFFF8LL),\n (const void *)((char *)v77 - ((char *)a1 - ((unsigned __int64)(a1 + 1) & 0xFFFFFFFFFFFFFFF8LL))),\n 8LL * (((unsigned int)a1 - (((_DWORD)a1 + 8) & 0xFFFFFFF8) + 444) >> 3));\n return a1;\n}", + "ida_strip_asm": "sub_1560:\nendbr64\npush r13\nmov r11, rdi\npush r12\npush rbp\npush rbx\nsub rsp, 1D8h\nmov rax, fs:28h\nmov [rsp+1F8h+var_30], rax\nxor eax, eax\nmovsxd rax, [rsp+1F8h+arg_1B8]\ntest eax, eax\njle loc_16B7\nmov r12d, edx\nlea rdx, [rax+rax*4]\nmov ebx, esi\nxor r9d, r9d\nlea r8, [rsp+1F8h+arg_4]\nlea rbp, [rax+rdx*2]\nxor r10d, r10d\nlea r13, [rsp+1F8h+arg_8]\nnop word ptr [rax+rax+00h]\nloc_15C0:\nmov eax, [r8+24h]\nmov ecx, [r8-4]\ncmp eax, 1\njle loc_16B0\nsub eax, 2\nmov rdx, r8\nmov esi, ecx\nadd rax, r9\nlea rdi, [r13+rax*4+0]\nnop dword ptr [rax+00000000h]\nloc_15E8:\nmov eax, [rdx]\ncmp ecx, eax\ncmovg ecx, eax\ncmp esi, eax\ncmovl esi, eax\nadd rdx, 4\ncmp rdx, rdi\njnz short loc_15E8\nloc_15FD:\ncmp ebx, ecx\njg short loc_163B\ncmp r12d, esi\njl short loc_163B\nmovsxd rax, r10d\nmovdqu xmm0, xmmword ptr [r8-4]\nmovdqu xmm1, xmmword ptr [r8+0Ch]\nadd r10d, 1\nlea rdx, [rax+rax*4]\nmovdqu xmm2, xmmword ptr [r8+18h]\nlea rax, [rax+rdx*2]\nshl rax, 2\nlea rdx, [rsp+rax+1F8h+var_1F8]\nmovups [rsp+rax+1F8h+var_1F8], xmm0\nmovups xmmword ptr [rdx+10h], xmm1\nmovups xmmword ptr [rdx+1Ch], xmm2\nloc_163B:\nadd r9, 0Bh\nadd r8, 2Ch ; ','\ncmp r9, rbp\njnz loc_15C0\nloc_164C:\nmov rax, qword ptr [rsp+1F8h+var_1F8]\nmov [rsp+1F8h+var_40], r10d\nlea rdi, [r11+8]\nmov rsi, rsp\nand rdi, 0FFFFFFFFFFFFFFF8h\nmov [r11], rax\nmov rax, [rsp+1B4h]\nmov [r11+1B4h], rax\nmov rax, r11\nsub rax, rdi\nsub rsi, rax\nadd eax, 1BCh\nshr eax, 3\nmov ecx, eax\nrep movsq\nmov rax, [rsp+1F8h+var_30]\nsub rax, fs:28h\njnz short loc_16BC\nadd rsp, 1D8h\nmov rax, r11\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_16B0:\nmov esi, ecx\njmp loc_15FD\nloc_16B7:\nxor r10d, r10d\njmp short loc_164C\nloc_16BC:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1560(\n _QWORD *a1,\n int a2,\n int a3,\n __int64 a4,\n __int64 a5,\n __int64 a6,\n __int64 a7,\n char a8,\n int a9,\n int a10,\n int a11,\n int a12,\n int a13,\n int a14,\n int a15,\n int a16,\n int a17,\n int a18,\n int a19,\n int a20,\n int a21,\n int a22,\n int a23,\n int a24,\n int a25,\n int a26,\n int a27,\n int a28,\n int a29,\n int a30,\n int a31,\n int a32,\n int a33,\n int a34,\n int a35,\n int a36,\n int a37,\n int a38,\n int a39,\n int a40,\n int a41,\n int a42,\n int a43,\n int a44,\n int a45,\n int a46,\n int a47,\n int a48,\n int a49,\n int a50,\n int a51,\n int a52,\n int a53,\n int a54,\n int a55,\n int a56,\n int a57,\n int a58,\n int a59,\n int a60,\n int a61,\n int a62)\n{\n __int64 v64; // r9\n char *v65; // r8\n __int64 v66; // rbp\n int v67; // r10d\n int v68; // eax\n int v69; // ecx\n char *v70; // rdx\n int v71; // esi\n __int64 v72; // rax\n __m128i v73; // xmm1\n __m128i v74; // xmm2\n char *v75; // rdx\n _QWORD v77[54]; // [rsp+0h] [rbp-1F8h] BYREF\n __int64 v78; // [rsp+1B4h] [rbp-44h]\n unsigned __int64 v79; // [rsp+1C8h] [rbp-30h]\n\n v79 = __readfsqword(0x28u);\n if ( a62 <= 0 )\n {\n v67 = 0;\n }\n else\n {\n v64 = 0LL;\n v65 = (char *)&a7 + 4;\n v66 = 11LL * a62;\n v67 = 0;\n do\n {\n v68 = *((_DWORD *)v65 + 9);\n v69 = *((_DWORD *)v65 - 1);\n if ( v68 <= 1 )\n {\n v71 = *((_DWORD *)v65 - 1);\n }\n else\n {\n v70 = v65;\n v71 = *((_DWORD *)v65 - 1);\n do\n {\n if ( v69 > *(_DWORD *)v70 )\n v69 = *(_DWORD *)v70;\n if ( v71 < *(_DWORD *)v70 )\n v71 = *(_DWORD *)v70;\n v70 += 4;\n }\n while ( v70 != &a8 + 4 * v64 + 4 * (unsigned int)(v68 - 2) );\n }\n if ( a2 <= v69 && a3 >= v71 )\n {\n v72 = v67;\n v73 = _mm_loadu_si128((const __m128i *)(v65 + 12));\n ++v67;\n v74 = _mm_loadu_si128((const __m128i *)(v65 + 24));\n v75 = (char *)v77 + 44 * v72;\n *(__m128i *)v75 = _mm_loadu_si128((const __m128i *)(v65 - 4));\n *((__m128i *)v75 + 1) = v73;\n *(__m128i *)(v75 + 28) = v74;\n }\n v64 += 11LL;\n v65 += 44;\n }\n while ( v64 != v66 );\n }\n HIDWORD(v78) = v67;\n *a1 = v77[0];\n *(_QWORD *)((char *)a1 + 436) = v78;\n qmemcpy(\n (void *)((unsigned __int64)(a1 + 1) & 0xFFFFFFFFFFFFFFF8LL),\n (const void *)((char *)v77 - ((char *)a1 - ((unsigned __int64)(a1 + 1) & 0xFFFFFFFFFFFFFFF8LL))),\n 8LL * (((unsigned int)a1 - (((_DWORD)a1 + 8) & 0xFFFFFFF8) + 444) >> 3));\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1560(uint64_t *a1, int a2, int a3, long long a4, long long a5,\n long long a6, long long a7, char a8, int a9, int a10,\n int a11, int a12, int a13, int a14, int a15, int a16,\n int a17, int a18, int a19, int a20, int a21, int a22,\n int a23, int a24, int a25, int a26, int a27, int a28,\n int a29, int a30, int a31, int a32, int a33, int a34,\n int a35, int a36, int a37, int a38, int a39, int a40,\n int a41, int a42, int a43, int a44, int a45, int a46,\n int a47, int a48, int a49, int a50, int a51, int a52,\n int a53, int a54, int a55, int a56, int a57, int a58,\n int a59, int a60, int a61, int a62) {\n long long v64;\n char *v65;\n long long v66;\n int v67;\n int v68;\n int v69;\n char *v70;\n int v71;\n long long v72;\n __m128i v73;\n __m128i v74;\n char *v75;\n uint64_t v77[54];\n long long v78;\n unsigned long long v79;\n v79 = __readfsqword(40u);\n if (a62 <= 0) {\n v67 = 0;\n } else {\n v64 = 0LL;\n v65 = (char *)&a7 + 4;\n v66 = 11LL * a62;\n v67 = 0;\n do {\n v68 = *((uint32_t *)v65 + 9);\n v69 = *((uint32_t *)v65 - 1);\n if (v68 <= 1) {\n v71 = *((uint32_t *)v65 - 1);\n } else {\n v70 = v65;\n v71 = *((uint32_t *)v65 - 1);\n do {\n if (v69 > *(uint32_t *)v70) v69 = *(uint32_t *)v70;\n if (v71 < *(uint32_t *)v70) v71 = *(uint32_t *)v70;\n v70 += 4;\n } while (v70 != &a8 + 4 * v64 + 4 * (unsigned int)(v68 - 2));\n }\n if (a2 <= v69 && a3 >= v71) {\n v72 = v67;\n v73 = _mm_loadu_si128((const __m128i *)(v65 + 12));\n ++v67;\n v74 = _mm_loadu_si128((const __m128i *)(v65 + 24));\n v75 = (char *)v77 + 44 * v72;\n *(__m128i *)v75 = _mm_loadu_si128((const __m128i *)(v65 - 4));\n *((__m128i *)v75 + 1) = v73;\n *(__m128i *)(v75 + 28) = v74;\n }\n v64 += 11LL;\n v65 += 44;\n } while (v64 != v66);\n }\n HIDWORD(v78) = v67;\n *a1 = v77[0];\n *(uint64_t *)((char *)a1 + 436) = v78;\n qmemcpy(\n (void *)((unsigned long long)(a1 + 1) & 18446744073709551608LL),\n (const void *)((char *)v77 - ((char *)a1 - ((unsigned long long)(a1 + 1) &\n 18446744073709551608LL))),\n 8LL *\n (((unsigned int)a1 - (((uint32_t)a1 + 8) & 4294967288) + 444) >> 3));\n return a1;\n}", + "ida_pseudo_norm": "uint64_t *func0(uint64_t *a1, int a2, int a3, long long a4, long long a5,\n long long a6, long long a7, char a8, int a9, int a10, int a11,\n int a12, int a13, int a14, int a15, int a16, int a17, int a18,\n int a19, int a20, int a21, int a22, int a23, int a24, int a25,\n int a26, int a27, int a28, int a29, int a30, int a31, int a32,\n int a33, int a34, int a35, int a36, int a37, int a38, int a39,\n int a40, int a41, int a42, int a43, int a44, int a45, int a46,\n int a47, int a48, int a49, int a50, int a51, int a52, int a53,\n int a54, int a55, int a56, int a57, int a58, int a59, int a60,\n int a61, int a62) {\n long long v64;\n char *v65;\n long long v66;\n int v67;\n int v68;\n int v69;\n char *v70;\n int v71;\n long long v72;\n __m128i v73;\n __m128i v74;\n char *v75;\n uint64_t v77[54];\n long long v78;\n unsigned long long v79;\n v79 = __readfsqword(40u);\n if (a62 <= 0) {\n v67 = 0;\n } else {\n v64 = 0LL;\n v65 = (char *)&a7 + 4;\n v66 = 11LL * a62;\n v67 = 0;\n do {\n v68 = *((uint32_t *)v65 + 9);\n v69 = *((uint32_t *)v65 - 1);\n if (v68 <= 1) {\n v71 = *((uint32_t *)v65 - 1);\n } else {\n v70 = v65;\n v71 = *((uint32_t *)v65 - 1);\n do {\n if (v69 > *(uint32_t *)v70) v69 = *(uint32_t *)v70;\n if (v71 < *(uint32_t *)v70) v71 = *(uint32_t *)v70;\n v70 += 4;\n } while (v70 != &a8 + 4 * v64 + 4 * (unsigned int)(v68 - 2));\n }\n if (a2 <= v69 && a3 >= v71) {\n v72 = v67;\n v73 = _mm_loadu_si128((const __m128i *)(v65 + 12));\n ++v67;\n v74 = _mm_loadu_si128((const __m128i *)(v65 + 24));\n v75 = (char *)v77 + 44 * v72;\n *(__m128i *)v75 = _mm_loadu_si128((const __m128i *)(v65 - 4));\n *((__m128i *)v75 + 1) = v73;\n *(__m128i *)(v75 + 28) = v74;\n }\n v64 += 11LL;\n v65 += 44;\n } while (v64 != v66);\n }\n HIDWORD(v78) = v67;\n *a1 = v77[0];\n *(uint64_t *)((char *)a1 + 436) = v78;\n qmemcpy(\n (void *)((unsigned long long)(a1 + 1) & 18446744073709551608LL),\n (const void *)((char *)v77 - ((char *)a1 - ((unsigned long long)(a1 + 1) &\n 18446744073709551608LL))),\n 8LL *\n (((unsigned int)a1 - (((uint32_t)a1 + 8) & 4294967288) + 444) >> 3));\n return a1;\n}" + }, + { + "index": 869, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int elements[10];\n\n int size;\n\n} IntList;\n\n\n\ntypedef struct {\n\n IntList lists[10];\n\n int size;\n\n} ListOfLists;\n\n\n\nint compare_lists(ListOfLists a, ListOfLists b) {\n\n if(a.size != b.size) return 0;\n\n for(int i = 0; i < a.size; i++) {\n\n if(a.lists[i].size != b.lists[i].size) return 0;\n\n for(int j = 0; j < a.lists[i].size; j++) {\n\n if(a.lists[i].elements[j] != b.lists[i].elements[j]) return 0;\n\n }\n\n }\n\n return 1;\n\n}\n\n\n\n", + "func": "ListOfLists func0(ListOfLists list1, int leftrange, int rigthrange) {\n ListOfLists result;\n result.size = 0;\n for (int i = 0; i < list1.size; i++) {\n int min = list1.lists[i].elements[0];\n int max = list1.lists[i].elements[0];\n for (int j = 1; j < list1.lists[i].size; j++) {\n if (list1.lists[i].elements[j] < min) min = list1.lists[i].elements[j];\n if (list1.lists[i].elements[j] > max) max = list1.lists[i].elements[j];\n }\n if (min >= leftrange && max <= rigthrange) {\n result.lists[result.size++] = list1.lists[i];\n }\n }\n return result;\n}", + "test": "int main() {\n\n ListOfLists list1;\n\n list1.size = 6;\n\n list1.lists[0].size = 1; list1.lists[0].elements[0] = 2;\n\n list1.lists[1].size = 1; list1.lists[1].elements[0] = 0;\n\n list1.lists[2].size = 3; list1.lists[2].elements[0] = 1; list1.lists[2].elements[1] = 2; list1.lists[2].elements[2] = 3;\n\n list1.lists[3].size = 6; list1.lists[3].elements[0] = 0; list1.lists[3].elements[1] = 1; list1.lists[3].elements[2] = 2;\n\n list1.lists[3].elements[3] = 3; list1.lists[3].elements[4] = 6; list1.lists[3].elements[5] = 7;\n\n list1.lists[4].size = 2; list1.lists[4].elements[0] = 9; list1.lists[4].elements[1] = 11;\n\n list1.lists[5].size = 4; list1.lists[5].elements[0] = 13; list1.lists[5].elements[1] = 14;\n\n list1.lists[5].elements[2] = 15; list1.lists[5].elements[3] = 17;\n\n\n\n ListOfLists expected1;\n\n expected1.size = 1;\n\n expected1.lists[0].size = 4; expected1.lists[0].elements[0] = 13; expected1.lists[0].elements[1] = 14;\n\n expected1.lists[0].elements[2] = 15; expected1.lists[0].elements[3] = 17;\n\n\n\n ListOfLists result1 = func0(list1, 13, 17);\n\n assert(compare_lists(result1, expected1));\n\n\n\n ListOfLists expected2;\n\n expected2.size = 2;\n\n expected2.lists[0].size = 1; expected2.lists[0].elements[0] = 2;\n\n expected2.lists[1].size = 3; expected2.lists[1].elements[0] = 1; expected2.lists[1].elements[1] = 2; expected2.lists[1].elements[2] = 3;\n\n\n\n ListOfLists result2 = func0(list1, 1, 3);\n\n assert(compare_lists(result2, expected2));\n\n\n\n ListOfLists expected3;\n\n expected3.size = 4;\n\n expected3.lists[0].size = 1; expected3.lists[0].elements[0] = 2;\n\n expected3.lists[1].size = 1; expected3.lists[1].elements[0] = 0;\n\n expected3.lists[2].size = 3; expected3.lists[2].elements[0] = 1; expected3.lists[2].elements[1] = 2; expected3.lists[2].elements[2] = 3;\n\n expected3.lists[3].size = 6; expected3.lists[3].elements[0] = 0; expected3.lists[3].elements[1] = 1;\n\n expected3.lists[3].elements[2] = 2; expected3.lists[3].elements[3] = 3; expected3.lists[3].elements[4] = 6; expected3.lists[3].elements[5] = 7;\n\n\n\n ListOfLists result3 = func0(list1, 0, 7);\n\n assert(compare_lists(result3, expected3));\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\nmov %rdi,%r12\npush %rbp\npush %rbx\nsub $0x1d0,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x1c8(%rsp)\nxor %eax,%eax\nmov 0x3b8(%rsp),%ebp\ntest %ebp,%ebp\njle 1900 \nmov %esi,%ebx\nmov %edx,%r13d\nlea 0x200(%rsp),%rcx\nxor %esi,%esi\nxor %r11d,%r11d\njmpq 18eb \nlea -0x2(%r8),%edi\nlea -0x1(%r8),%edx\ncmp $0x2,%edi\njbe 196f \nmovd %eax,%xmm5\nmovdqu 0x4(%rcx),%xmm3\nmov %edx,%eax\npshufd $0x0,%xmm5,%xmm0\nshr $0x2,%eax\nmovdqa %xmm0,%xmm1\nmovdqa %xmm3,%xmm2\npcmpgtd %xmm3,%xmm1\nmovdqa %xmm1,%xmm4\npand %xmm1,%xmm2\npandn %xmm0,%xmm4\npand %xmm1,%xmm0\npandn %xmm3,%xmm1\npor %xmm4,%xmm2\npor %xmm1,%xmm0\ncmp $0x1,%eax\nje 17a2 \nmovdqu 0x14(%rcx),%xmm1\nmovdqa %xmm1,%xmm3\npcmpgtd %xmm2,%xmm3\npand %xmm3,%xmm2\npandn %xmm1,%xmm3\npor %xmm3,%xmm2\nmovdqa %xmm1,%xmm3\npcmpgtd %xmm0,%xmm3\npand %xmm3,%xmm1\npandn %xmm0,%xmm3\nmovdqa %xmm3,%xmm0\npor %xmm1,%xmm0\nmovdqa %xmm0,%xmm3\nmov %edx,%r10d\npsrldq $0x8,%xmm3\nand $0xfffffffc,%r10d\nmovdqa %xmm3,%xmm1\nlea 0x1(%r10),%edi\npcmpgtd %xmm0,%xmm1\npand %xmm1,%xmm3\npandn %xmm0,%xmm1\nmovdqa %xmm1,%xmm0\npor %xmm3,%xmm0\nmovdqa %xmm0,%xmm3\npsrldq $0x4,%xmm3\nmovdqa %xmm3,%xmm1\npcmpgtd %xmm0,%xmm1\npand %xmm1,%xmm3\npandn %xmm0,%xmm1\npor %xmm3,%xmm1\nmovd %xmm1,%r9d\nmovdqa %xmm2,%xmm1\npsrldq $0x8,%xmm1\nmovdqa %xmm1,%xmm0\npcmpgtd %xmm2,%xmm0\npand %xmm0,%xmm2\npandn %xmm1,%xmm0\npor %xmm0,%xmm2\nmovdqa %xmm2,%xmm1\npsrldq $0x4,%xmm1\nmovdqa %xmm1,%xmm0\npcmpgtd %xmm2,%xmm0\npand %xmm0,%xmm2\npandn %xmm1,%xmm0\npor %xmm0,%xmm2\nmovd %xmm2,%eax\ncmp %edx,%r10d\nje 18a0 \nmovslq %r11d,%rdx\nmovslq %edi,%r10\nlea (%rdx,%rdx,4),%r14\nlea (%rdx,%r14,2),%rdx\nadd %rdx,%r10\nmov 0x200(%rsp,%r10,4),%r10d\ncmp %r10d,%eax\ncmovg %r10d,%eax\ncmp %r10d,%r9d\ncmovl %r10d,%r9d\nlea 0x1(%rdi),%r10d\ncmp %r8d,%r10d\njge 18a0 \nmovslq %r10d,%r10\nadd %rdx,%r10\nmov 0x200(%rsp,%r10,4),%r10d\ncmp %r10d,%eax\ncmovg %r10d,%eax\ncmp %r10d,%r9d\ncmovl %r10d,%r9d\nadd $0x2,%edi\ncmp %edi,%r8d\njle 18a0 \nmovslq %edi,%rdi\nadd %rdx,%rdi\nmov 0x200(%rsp,%rdi,4),%edx\ncmp %edx,%eax\ncmovg %edx,%eax\ncmp %edx,%r9d\ncmovl %edx,%r9d\ncmp %eax,%ebx\njg 18de \ncmp %r9d,%r13d\njl 18de \nmovslq %esi,%rax\nmovdqu (%rcx),%xmm6\nmovdqu 0x10(%rcx),%xmm7\nadd $0x1,%esi\nlea (%rax,%rax,4),%rdx\nlea (%rax,%rdx,2),%rax\nshl $0x2,%rax\nlea (%rsp,%rax,1),%rdx\nmovups %xmm6,(%rsp,%rax,1)\nmov 0x20(%rcx),%rax\nmovups %xmm7,0x10(%rdx)\nmov %rax,0x20(%rdx)\nmov 0x28(%rcx),%eax\nmov %eax,0x28(%rdx)\nadd $0x1,%r11d\nadd $0x2c,%rcx\ncmp %r11d,%ebp\nje 1908 \nmov 0x28(%rcx),%r8d\nmov (%rcx),%eax\ncmp $0x1,%r8d\njg 1720 \nmov %eax,%r9d\njmp 18a0 \nxor %esi,%esi\nnopw 0x0(%rax,%rax,1)\nmov (%rsp),%rax\nmov %esi,0x1b8(%rsp)\nlea 0x8(%r12),%rdi\nmov %rsp,%rsi\nand $0xfffffffffffffff8,%rdi\nmov %rax,(%r12)\nmov 0x1b4(%rsp),%rax\nmov %rax,0x1b4(%r12)\nmov %r12,%rax\nsub %rdi,%rax\nsub %rax,%rsi\nadd $0x1bc,%eax\nshr $0x3,%eax\nmov %eax,%ecx\nrep movsq %ds:(%rsi),%es:(%rdi)\nmov 0x1c8(%rsp),%rax\nxor %fs:0x28,%rax\njne 197c \nadd $0x1d0,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nmov %eax,%r9d\nmov $0x1,%edi\njmpq 1833 \ncallq 1060 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\nmov r11, rdi\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 1D0h\nmov rax, fs:28h\nmov [rsp+1F8h+var_30], rax\nxor eax, eax\nmov r12d, [rsp+1F8h+arg_1B8]\ntest r12d, r12d\njle loc_1896\nmov ebp, esi\nmov r13d, edx\nlea rcx, [rsp+1F8h+arg_0]\nxor ebx, ebx\nxor r9d, r9d\njmp loc_1884\nloc_16C8:\nlea edi, [rsi-2]\nlea edx, [rsi-1]\ncmp edi, 2\njbe loc_1904\nmovd xmm5, eax\nmovdqu xmm3, xmmword ptr [rcx+4]\nmov eax, edx\npshufd xmm2, xmm5, 0\nshr eax, 2\nmovdqa xmm0, xmm2\nmovdqa xmm4, xmm3\npcmpgtd xmm0, xmm3\nmovdqa xmm1, xmm0\npand xmm4, xmm0\npandn xmm1, xmm2\npand xmm2, xmm0\npandn xmm0, xmm3\npor xmm1, xmm4\npor xmm0, xmm2\ncmp eax, 1\njz short loc_1748\nmovdqu xmm2, xmmword ptr [rcx+14h]\nmovdqa xmm3, xmm2\npcmpgtd xmm3, xmm1\npand xmm1, xmm3\npandn xmm3, xmm2\npor xmm1, xmm3\nmovdqa xmm3, xmm2\npcmpgtd xmm3, xmm0\npand xmm2, xmm3\npandn xmm3, xmm0\npor xmm3, xmm2\nmovdqa xmm0, xmm3\nloc_1748:\nmovdqa xmm3, xmm0\npsrldq xmm3, 8\nmovdqa xmm2, xmm3\npcmpgtd xmm2, xmm0\npand xmm3, xmm2\npandn xmm2, xmm0\npor xmm2, xmm3\nmovdqa xmm3, xmm2\nmovdqa xmm0, xmm2\npsrldq xmm3, 4\nmovdqa xmm2, xmm3\npcmpgtd xmm2, xmm0\npand xmm3, xmm2\npandn xmm2, xmm0\npor xmm2, xmm3\nmovd edi, xmm2\nmovdqa xmm2, xmm1\npsrldq xmm2, 8\nmovdqa xmm0, xmm2\npcmpgtd xmm0, xmm1\npand xmm1, xmm0\npandn xmm0, xmm2\npor xmm1, xmm0\nmovdqa xmm2, xmm1\npsrldq xmm2, 4\nmovdqa xmm0, xmm2\npcmpgtd xmm0, xmm1\npand xmm1, xmm0\npandn xmm0, xmm2\npor xmm0, xmm1\nmovd eax, xmm0\ntest dl, 3\njz short loc_183E\nand edx, 0FFFFFFFCh\nadd edx, 1\nloc_17D3:\nmovsxd r10, r9d\nmovsxd r8, edx\nlea r14, [r10+r10*4]\nlea r10, [r10+r14*2]\nadd r8, r10\nmov r8d, [rsp+r8*4+1F8h+arg_0]\ncmp eax, r8d\ncmovg eax, r8d\ncmp edi, r8d\ncmovl edi, r8d\nlea r8d, [rdx+1]\ncmp r8d, esi\njge short loc_183E\nmovsxd r8, r8d\nadd r8, r10\nmov r8d, [rsp+r8*4+1F8h+arg_0]\ncmp eax, r8d\ncmovg eax, r8d\ncmp edi, r8d\ncmovl edi, r8d\nadd edx, 2\ncmp esi, edx\njle short loc_183E\nmovsxd rdx, edx\nadd r10, rdx\nmov edx, [rsp+r10*4+1F8h+arg_0]\ncmp eax, edx\ncmovg eax, edx\ncmp edi, edx\ncmovl edi, edx\nloc_183E:\ncmp ebp, eax\njg short loc_1877\ncmp r13d, edi\njl short loc_1877\nmovsxd rax, ebx\nmovdqu xmm6, xmmword ptr [rcx]\nmovdqu xmm7, xmmword ptr [rcx+10h]\nadd ebx, 1\nlea rdx, [rax+rax*4]\nlea rax, [rax+rdx*2]\nshl rax, 2\nmovups [rsp+rax+1F8h+var_1F8], xmm6\nmovdqu xmm6, xmmword ptr [rcx+1Ch]\nlea rdx, [rsp+rax+1F8h+var_1F8]\nmovups xmmword ptr [rdx+10h], xmm7\nmovups xmmword ptr [rdx+1Ch], xmm6\nloc_1877:\nadd r9d, 1\nadd rcx, 2Ch ; ','\ncmp r12d, r9d\njz short loc_18A0\nloc_1884:\nmov esi, [rcx+28h]\nmov eax, [rcx]\ncmp esi, 1\njg loc_16C8\nmov edi, eax\njmp short loc_183E\nloc_1896:\nxor ebx, ebx\nnop dword ptr [rax+rax+00000000h]\nloc_18A0:\nmov rax, qword ptr [rsp+1F8h+var_1F8]\nmov [rsp+1F8h+var_40], ebx\nlea rdi, [r11+8]\nmov rsi, rsp\nand rdi, 0FFFFFFFFFFFFFFF8h\nmov [r11], rax\nmov rax, [rsp+1B4h]\nmov [r11+1B4h], rax\nmov rax, r11\nsub rax, rdi\nsub rsi, rax\nadd eax, 1BCh\nshr eax, 3\nmov ecx, eax\nrep movsq\nmov rax, [rsp+1F8h+var_30]\nsub rax, fs:28h\njnz short loc_1910\nadd rsp, 1D0h\nmov rax, r11\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1904:\nmov edi, eax\nmov edx, 1\njmp loc_17D3\nloc_1910:\ncall ___stack_chk_fail", + "ida_pseudo": "_QWORD *__fastcall func0(\n _QWORD *a1,\n signed int a2,\n int a3,\n __int64 a4,\n __int64 a5,\n __int64 a6,\n int a7,\n int a8,\n int a9,\n int a10,\n int a11,\n int a12,\n int a13,\n int a14,\n int a15,\n int a16,\n int a17,\n int a18,\n int a19,\n int a20,\n int a21,\n int a22,\n int a23,\n int a24,\n int a25,\n int a26,\n int a27,\n int a28,\n int a29,\n int a30,\n int a31,\n int a32,\n int a33,\n int a34,\n int a35,\n int a36,\n int a37,\n int a38,\n int a39,\n int a40,\n int a41,\n int a42,\n int a43,\n int a44,\n int a45,\n int a46,\n int a47,\n int a48,\n int a49,\n int a50,\n int a51,\n int a52,\n int a53,\n int a54,\n int a55,\n int a56,\n int a57,\n int a58,\n int a59,\n int a60,\n int a61,\n int a62)\n{\n int v63; // r12d\n int *v66; // rcx\n int v67; // ebx\n int v68; // r9d\n unsigned int v69; // edx\n __m128i v70; // xmm3\n __m128i v71; // xmm2\n __m128i v72; // xmm0\n __m128i v73; // xmm1\n __m128i v74; // xmm0\n __m128i v75; // xmm2\n __m128i v76; // xmm3\n __m128i v77; // xmm3\n __m128i v78; // xmm3\n __m128i v79; // xmm2\n __m128i v80; // xmm0\n __m128i v81; // xmm3\n __m128i v82; // xmm2\n int v83; // edi\n __m128i v84; // xmm2\n __m128i v85; // xmm0\n __m128i v86; // xmm1\n __m128i v87; // xmm2\n __m128i v88; // xmm0\n signed int v89; // eax\n signed int v90; // edx\n __int64 v91; // r10\n signed int v92; // r8d\n signed int v93; // r8d\n int v94; // edx\n signed int v95; // edx\n __int64 v96; // rax\n __m128i v97; // xmm7\n __m128i v98; // xmm6\n char *v99; // rdx\n int v100; // esi\n _QWORD v102[54]; // [rsp+0h] [rbp-1F8h] BYREF\n __int64 v103; // [rsp+1B4h] [rbp-44h]\n unsigned __int64 v104; // [rsp+1C8h] [rbp-30h]\n\n v104 = __readfsqword(0x28u);\n v63 = a62;\n if ( a62 > 0 )\n {\n v66 = &a7;\n v67 = 0;\n v68 = 0;\n while ( 1 )\n {\n v100 = v66[10];\n v89 = *v66;\n if ( v100 > 1 )\n {\n v69 = v100 - 1;\n if ( (unsigned int)(v100 - 2) <= 2 )\n {\n v83 = *v66;\n v90 = 1;\n }\n else\n {\n v70 = _mm_loadu_si128((const __m128i *)(v66 + 1));\n v71 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v89), 0);\n v72 = _mm_cmpgt_epi32(v71, v70);\n v73 = _mm_or_si128(_mm_andnot_si128(v72, v71), _mm_and_si128(v70, v72));\n v74 = _mm_or_si128(_mm_andnot_si128(v72, v70), _mm_and_si128(v71, v72));\n if ( v69 >> 2 != 1 )\n {\n v75 = _mm_loadu_si128((const __m128i *)(v66 + 5));\n v76 = _mm_cmpgt_epi32(v75, v73);\n v73 = _mm_or_si128(_mm_and_si128(v73, v76), _mm_andnot_si128(v76, v75));\n v77 = _mm_cmpgt_epi32(v75, v74);\n v74 = _mm_or_si128(_mm_andnot_si128(v77, v74), _mm_and_si128(v75, v77));\n }\n v78 = _mm_srli_si128(v74, 8);\n v79 = _mm_cmpgt_epi32(v78, v74);\n v80 = _mm_or_si128(_mm_andnot_si128(v79, v74), _mm_and_si128(v78, v79));\n v81 = _mm_srli_si128(v80, 4);\n v82 = _mm_cmpgt_epi32(v81, v80);\n v83 = _mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v82, v80), _mm_and_si128(v81, v82)));\n v84 = _mm_srli_si128(v73, 8);\n v85 = _mm_cmpgt_epi32(v84, v73);\n v86 = _mm_or_si128(_mm_and_si128(v73, v85), _mm_andnot_si128(v85, v84));\n v87 = _mm_srli_si128(v86, 4);\n v88 = _mm_cmpgt_epi32(v87, v86);\n v89 = _mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v88, v87), _mm_and_si128(v86, v88)));\n if ( (v69 & 3) == 0 )\n goto LABEL_22;\n v90 = (v69 & 0xFFFFFFFC) + 1;\n }\n v91 = 11LL * v68;\n v92 = *(&a7 + v91 + v90);\n if ( v89 > v92 )\n v89 = *(&a7 + v91 + v90);\n if ( v83 < v92 )\n v83 = *(&a7 + v91 + v90);\n if ( v90 + 1 < v100 )\n {\n v93 = *(&a7 + v91 + v90 + 1);\n if ( v89 > v93 )\n v89 = *(&a7 + v91 + v90 + 1);\n if ( v83 < v93 )\n v83 = *(&a7 + v91 + v90 + 1);\n v94 = v90 + 2;\n if ( v100 > v94 )\n {\n v95 = *(&a7 + v94 + v91);\n if ( v89 > v95 )\n v89 = v95;\n if ( v83 < v95 )\n v83 = v95;\n }\n }\n }\n else\n {\n v83 = *v66;\n }\nLABEL_22:\n if ( a2 <= v89 && a3 >= v83 )\n {\n v96 = v67;\n v97 = _mm_loadu_si128((const __m128i *)v66 + 1);\n ++v67;\n v96 *= 44LL;\n *(__m128i *)((char *)v102 + v96) = _mm_loadu_si128((const __m128i *)v66);\n v98 = _mm_loadu_si128((const __m128i *)(v66 + 7));\n v99 = (char *)v102 + v96;\n *((__m128i *)v99 + 1) = v97;\n *(__m128i *)(v99 + 28) = v98;\n }\n ++v68;\n v66 += 11;\n if ( v63 == v68 )\n goto LABEL_29;\n }\n }\n v67 = 0;\nLABEL_29:\n HIDWORD(v103) = v67;\n *a1 = v102[0];\n *(_QWORD *)((char *)a1 + 436) = v103;\n qmemcpy(\n (void *)((unsigned __int64)(a1 + 1) & 0xFFFFFFFFFFFFFFF8LL),\n (const void *)((char *)v102 - ((char *)a1 - ((unsigned __int64)(a1 + 1) & 0xFFFFFFFFFFFFFFF8LL))),\n 8LL * (((unsigned int)a1 - (((_DWORD)a1 + 8) & 0xFFFFFFF8) + 444) >> 3));\n return a1;\n}", + "ida_strip_asm": "sub_1670:\nendbr64\npush r14\nmov r11, rdi\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 1D0h\nmov rax, fs:28h\nmov [rsp+1F8h+var_30], rax\nxor eax, eax\nmov r12d, [rsp+1F8h+arg_1B8]\ntest r12d, r12d\njle loc_1896\nmov ebp, esi\nmov r13d, edx\nlea rcx, [rsp+1F8h+arg_0]\nxor ebx, ebx\nxor r9d, r9d\njmp loc_1884\nloc_16C8:\nlea edi, [rsi-2]\nlea edx, [rsi-1]\ncmp edi, 2\njbe loc_1904\nmovd xmm5, eax\nmovdqu xmm3, xmmword ptr [rcx+4]\nmov eax, edx\npshufd xmm2, xmm5, 0\nshr eax, 2\nmovdqa xmm0, xmm2\nmovdqa xmm4, xmm3\npcmpgtd xmm0, xmm3\nmovdqa xmm1, xmm0\npand xmm4, xmm0\npandn xmm1, xmm2\npand xmm2, xmm0\npandn xmm0, xmm3\npor xmm1, xmm4\npor xmm0, xmm2\ncmp eax, 1\njz short loc_1748\nmovdqu xmm2, xmmword ptr [rcx+14h]\nmovdqa xmm3, xmm2\npcmpgtd xmm3, xmm1\npand xmm1, xmm3\npandn xmm3, xmm2\npor xmm1, xmm3\nmovdqa xmm3, xmm2\npcmpgtd xmm3, xmm0\npand xmm2, xmm3\npandn xmm3, xmm0\npor xmm3, xmm2\nmovdqa xmm0, xmm3\nloc_1748:\nmovdqa xmm3, xmm0\npsrldq xmm3, 8\nmovdqa xmm2, xmm3\npcmpgtd xmm2, xmm0\npand xmm3, xmm2\npandn xmm2, xmm0\npor xmm2, xmm3\nmovdqa xmm3, xmm2\nmovdqa xmm0, xmm2\npsrldq xmm3, 4\nmovdqa xmm2, xmm3\npcmpgtd xmm2, xmm0\npand xmm3, xmm2\npandn xmm2, xmm0\npor xmm2, xmm3\nmovd edi, xmm2\nmovdqa xmm2, xmm1\npsrldq xmm2, 8\nmovdqa xmm0, xmm2\npcmpgtd xmm0, xmm1\npand xmm1, xmm0\npandn xmm0, xmm2\npor xmm1, xmm0\nmovdqa xmm2, xmm1\npsrldq xmm2, 4\nmovdqa xmm0, xmm2\npcmpgtd xmm0, xmm1\npand xmm1, xmm0\npandn xmm0, xmm2\npor xmm0, xmm1\nmovd eax, xmm0\ntest dl, 3\njz short loc_183E\nand edx, 0FFFFFFFCh\nadd edx, 1\nloc_17D3:\nmovsxd r10, r9d\nmovsxd r8, edx\nlea r14, [r10+r10*4]\nlea r10, [r10+r14*2]\nadd r8, r10\nmov r8d, [rsp+r8*4+1F8h+arg_0]\ncmp eax, r8d\ncmovg eax, r8d\ncmp edi, r8d\ncmovl edi, r8d\nlea r8d, [rdx+1]\ncmp r8d, esi\njge short loc_183E\nmovsxd r8, r8d\nadd r8, r10\nmov r8d, [rsp+r8*4+1F8h+arg_0]\ncmp eax, r8d\ncmovg eax, r8d\ncmp edi, r8d\ncmovl edi, r8d\nadd edx, 2\ncmp esi, edx\njle short loc_183E\nmovsxd rdx, edx\nadd r10, rdx\nmov edx, [rsp+r10*4+1F8h+arg_0]\ncmp eax, edx\ncmovg eax, edx\ncmp edi, edx\ncmovl edi, edx\nloc_183E:\ncmp ebp, eax\njg short loc_1877\ncmp r13d, edi\njl short loc_1877\nmovsxd rax, ebx\nmovdqu xmm6, xmmword ptr [rcx]\nmovdqu xmm7, xmmword ptr [rcx+10h]\nadd ebx, 1\nlea rdx, [rax+rax*4]\nlea rax, [rax+rdx*2]\nshl rax, 2\nmovups [rsp+rax+1F8h+var_1F8], xmm6\nmovdqu xmm6, xmmword ptr [rcx+1Ch]\nlea rdx, [rsp+rax+1F8h+var_1F8]\nmovups xmmword ptr [rdx+10h], xmm7\nmovups xmmword ptr [rdx+1Ch], xmm6\nloc_1877:\nadd r9d, 1\nadd rcx, 2Ch ; ','\ncmp r12d, r9d\njz short loc_18A0\nloc_1884:\nmov esi, [rcx+28h]\nmov eax, [rcx]\ncmp esi, 1\njg loc_16C8\nmov edi, eax\njmp short loc_183E\nloc_1896:\nxor ebx, ebx\nnop dword ptr [rax+rax+00000000h]\nloc_18A0:\nmov rax, qword ptr [rsp+1F8h+var_1F8]\nmov [rsp+1F8h+var_40], ebx\nlea rdi, [r11+8]\nmov rsi, rsp\nand rdi, 0FFFFFFFFFFFFFFF8h\nmov [r11], rax\nmov rax, [rsp+1B4h]\nmov [r11+1B4h], rax\nmov rax, r11\nsub rax, rdi\nsub rsi, rax\nadd eax, 1BCh\nshr eax, 3\nmov ecx, eax\nrep movsq\nmov rax, [rsp+1F8h+var_30]\nsub rax, fs:28h\njnz short loc_1910\nadd rsp, 1D0h\nmov rax, r11\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1904:\nmov edi, eax\nmov edx, 1\njmp loc_17D3\nloc_1910:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1670(\n _QWORD *a1,\n signed int a2,\n int a3,\n __int64 a4,\n __int64 a5,\n __int64 a6,\n int a7,\n int a8,\n int a9,\n int a10,\n int a11,\n int a12,\n int a13,\n int a14,\n int a15,\n int a16,\n int a17,\n int a18,\n int a19,\n int a20,\n int a21,\n int a22,\n int a23,\n int a24,\n int a25,\n int a26,\n int a27,\n int a28,\n int a29,\n int a30,\n int a31,\n int a32,\n int a33,\n int a34,\n int a35,\n int a36,\n int a37,\n int a38,\n int a39,\n int a40,\n int a41,\n int a42,\n int a43,\n int a44,\n int a45,\n int a46,\n int a47,\n int a48,\n int a49,\n int a50,\n int a51,\n int a52,\n int a53,\n int a54,\n int a55,\n int a56,\n int a57,\n int a58,\n int a59,\n int a60,\n int a61,\n int a62)\n{\n int v63; // r12d\n int *v66; // rcx\n int v67; // ebx\n int v68; // r9d\n unsigned int v69; // edx\n __m128i v70; // xmm3\n __m128i v71; // xmm2\n __m128i v72; // xmm0\n __m128i v73; // xmm1\n __m128i v74; // xmm0\n __m128i v75; // xmm2\n __m128i v76; // xmm3\n __m128i v77; // xmm3\n __m128i v78; // xmm3\n __m128i v79; // xmm2\n __m128i v80; // xmm0\n __m128i v81; // xmm3\n __m128i v82; // xmm2\n int v83; // edi\n __m128i v84; // xmm2\n __m128i v85; // xmm0\n __m128i v86; // xmm1\n __m128i v87; // xmm2\n __m128i v88; // xmm0\n signed int v89; // eax\n signed int v90; // edx\n __int64 v91; // r10\n signed int v92; // r8d\n signed int v93; // r8d\n int v94; // edx\n signed int v95; // edx\n __int64 v96; // rax\n __m128i v97; // xmm7\n __m128i v98; // xmm6\n char *v99; // rdx\n int v100; // esi\n _QWORD v102[54]; // [rsp+0h] [rbp-1F8h] BYREF\n __int64 v103; // [rsp+1B4h] [rbp-44h]\n unsigned __int64 v104; // [rsp+1C8h] [rbp-30h]\n\n v104 = __readfsqword(0x28u);\n v63 = a62;\n if ( a62 > 0 )\n {\n v66 = &a7;\n v67 = 0;\n v68 = 0;\n while ( 1 )\n {\n v100 = v66[10];\n v89 = *v66;\n if ( v100 > 1 )\n {\n v69 = v100 - 1;\n if ( (unsigned int)(v100 - 2) <= 2 )\n {\n v83 = *v66;\n v90 = 1;\n }\n else\n {\n v70 = _mm_loadu_si128((const __m128i *)(v66 + 1));\n v71 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v89), 0);\n v72 = _mm_cmpgt_epi32(v71, v70);\n v73 = _mm_or_si128(_mm_andnot_si128(v72, v71), _mm_and_si128(v70, v72));\n v74 = _mm_or_si128(_mm_andnot_si128(v72, v70), _mm_and_si128(v71, v72));\n if ( v69 >> 2 != 1 )\n {\n v75 = _mm_loadu_si128((const __m128i *)(v66 + 5));\n v76 = _mm_cmpgt_epi32(v75, v73);\n v73 = _mm_or_si128(_mm_and_si128(v73, v76), _mm_andnot_si128(v76, v75));\n v77 = _mm_cmpgt_epi32(v75, v74);\n v74 = _mm_or_si128(_mm_andnot_si128(v77, v74), _mm_and_si128(v75, v77));\n }\n v78 = _mm_srli_si128(v74, 8);\n v79 = _mm_cmpgt_epi32(v78, v74);\n v80 = _mm_or_si128(_mm_andnot_si128(v79, v74), _mm_and_si128(v78, v79));\n v81 = _mm_srli_si128(v80, 4);\n v82 = _mm_cmpgt_epi32(v81, v80);\n v83 = _mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v82, v80), _mm_and_si128(v81, v82)));\n v84 = _mm_srli_si128(v73, 8);\n v85 = _mm_cmpgt_epi32(v84, v73);\n v86 = _mm_or_si128(_mm_and_si128(v73, v85), _mm_andnot_si128(v85, v84));\n v87 = _mm_srli_si128(v86, 4);\n v88 = _mm_cmpgt_epi32(v87, v86);\n v89 = _mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v88, v87), _mm_and_si128(v86, v88)));\n if ( (v69 & 3) == 0 )\n goto LABEL_22;\n v90 = (v69 & 0xFFFFFFFC) + 1;\n }\n v91 = 11LL * v68;\n v92 = *(&a7 + v91 + v90);\n if ( v89 > v92 )\n v89 = *(&a7 + v91 + v90);\n if ( v83 < v92 )\n v83 = *(&a7 + v91 + v90);\n if ( v90 + 1 < v100 )\n {\n v93 = *(&a7 + v91 + v90 + 1);\n if ( v89 > v93 )\n v89 = *(&a7 + v91 + v90 + 1);\n if ( v83 < v93 )\n v83 = *(&a7 + v91 + v90 + 1);\n v94 = v90 + 2;\n if ( v100 > v94 )\n {\n v95 = *(&a7 + v94 + v91);\n if ( v89 > v95 )\n v89 = v95;\n if ( v83 < v95 )\n v83 = v95;\n }\n }\n }\n else\n {\n v83 = *v66;\n }\nLABEL_22:\n if ( a2 <= v89 && a3 >= v83 )\n {\n v96 = v67;\n v97 = _mm_loadu_si128((const __m128i *)v66 + 1);\n ++v67;\n v96 *= 44LL;\n *(__m128i *)((char *)v102 + v96) = _mm_loadu_si128((const __m128i *)v66);\n v98 = _mm_loadu_si128((const __m128i *)(v66 + 7));\n v99 = (char *)v102 + v96;\n *((__m128i *)v99 + 1) = v97;\n *(__m128i *)(v99 + 28) = v98;\n }\n ++v68;\n v66 += 11;\n if ( v63 == v68 )\n goto LABEL_29;\n }\n }\n v67 = 0;\nLABEL_29:\n HIDWORD(v103) = v67;\n *a1 = v102[0];\n *(_QWORD *)((char *)a1 + 436) = v103;\n qmemcpy(\n (void *)((unsigned __int64)(a1 + 1) & 0xFFFFFFFFFFFFFFF8LL),\n (const void *)((char *)v102 - ((char *)a1 - ((unsigned __int64)(a1 + 1) & 0xFFFFFFFFFFFFFFF8LL))),\n 8LL * (((unsigned int)a1 - (((_DWORD)a1 + 8) & 0xFFFFFFF8) + 444) >> 3));\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1670(uint64_t *a1, signed int a2, int a3, long long a4,\n long long a5, long long a6, int a7, int a8, int a9, int a10,\n int a11, int a12, int a13, int a14, int a15, int a16,\n int a17, int a18, int a19, int a20, int a21, int a22,\n int a23, int a24, int a25, int a26, int a27, int a28,\n int a29, int a30, int a31, int a32, int a33, int a34,\n int a35, int a36, int a37, int a38, int a39, int a40,\n int a41, int a42, int a43, int a44, int a45, int a46,\n int a47, int a48, int a49, int a50, int a51, int a52,\n int a53, int a54, int a55, int a56, int a57, int a58,\n int a59, int a60, int a61, int a62) {\n int v63;\n int *v66;\n int v67;\n int v68;\n unsigned int v69;\n __m128i v70;\n __m128i v71;\n __m128i v72;\n __m128i v73;\n __m128i v74;\n __m128i v75;\n __m128i v76;\n __m128i v77;\n __m128i v78;\n __m128i v79;\n __m128i v80;\n __m128i v81;\n __m128i v82;\n int v83;\n __m128i v84;\n __m128i v85;\n __m128i v86;\n __m128i v87;\n __m128i v88;\n signed int v89;\n signed int v90;\n long long v91;\n signed int v92;\n signed int v93;\n int v94;\n signed int v95;\n long long v96;\n __m128i v97;\n __m128i v98;\n char *v99;\n int v100;\n uint64_t v102[54];\n long long v103;\n unsigned long long v104;\n v104 = __readfsqword(40u);\n v63 = a62;\n if (a62 > 0) {\n v66 = &a7;\n v67 = 0;\n v68 = 0;\n while (1) {\n v100 = v66[10];\n v89 = *v66;\n if (v100 > 1) {\n v69 = v100 - 1;\n if ((unsigned int)(v100 - 2) <= 2) {\n v83 = *v66;\n v90 = 1;\n } else {\n v70 = _mm_loadu_si128((const __m128i *)(v66 + 1));\n v71 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v89), 0);\n v72 = _mm_cmpgt_epi32(v71, v70);\n v73 =\n _mm_or_si128(_mm_andnot_si128(v72, v71), _mm_and_si128(v70, v72));\n v74 =\n _mm_or_si128(_mm_andnot_si128(v72, v70), _mm_and_si128(v71, v72));\n if (v69 >> 2 != 1) {\n v75 = _mm_loadu_si128((const __m128i *)(v66 + 5));\n v76 = _mm_cmpgt_epi32(v75, v73);\n v73 = _mm_or_si128(_mm_and_si128(v73, v76),\n _mm_andnot_si128(v76, v75));\n v77 = _mm_cmpgt_epi32(v75, v74);\n v74 = _mm_or_si128(_mm_andnot_si128(v77, v74),\n _mm_and_si128(v75, v77));\n }\n v78 = _mm_srli_si128(v74, 8);\n v79 = _mm_cmpgt_epi32(v78, v74);\n v80 =\n _mm_or_si128(_mm_andnot_si128(v79, v74), _mm_and_si128(v78, v79));\n v81 = _mm_srli_si128(v80, 4);\n v82 = _mm_cmpgt_epi32(v81, v80);\n v83 = _mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v82, v80),\n _mm_and_si128(v81, v82)));\n v84 = _mm_srli_si128(v73, 8);\n v85 = _mm_cmpgt_epi32(v84, v73);\n v86 =\n _mm_or_si128(_mm_and_si128(v73, v85), _mm_andnot_si128(v85, v84));\n v87 = _mm_srli_si128(v86, 4);\n v88 = _mm_cmpgt_epi32(v87, v86);\n v89 = _mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v88, v87),\n _mm_and_si128(v86, v88)));\n if ((v69 & 3) == 0) goto LABEL_22;\n v90 = (v69 & 4294967292) + 1;\n }\n v91 = 11LL * v68;\n v92 = *(&a7 + v91 + v90);\n if (v89 > v92) v89 = *(&a7 + v91 + v90);\n if (v83 < v92) v83 = *(&a7 + v91 + v90);\n if (v90 + 1 < v100) {\n v93 = *(&a7 + v91 + v90 + 1);\n if (v89 > v93) v89 = *(&a7 + v91 + v90 + 1);\n if (v83 < v93) v83 = *(&a7 + v91 + v90 + 1);\n v94 = v90 + 2;\n if (v100 > v94) {\n v95 = *(&a7 + v94 + v91);\n if (v89 > v95) v89 = v95;\n if (v83 < v95) v83 = v95;\n }\n }\n } else {\n v83 = *v66;\n }\n LABEL_22:\n if (a2 <= v89 && a3 >= v83) {\n v96 = v67;\n v97 = _mm_loadu_si128((const __m128i *)v66 + 1);\n ++v67;\n v96 *= 44LL;\n *(__m128i *)((char *)v102 + v96) =\n _mm_loadu_si128((const __m128i *)v66);\n v98 = _mm_loadu_si128((const __m128i *)(v66 + 7));\n v99 = (char *)v102 + v96;\n *((__m128i *)v99 + 1) = v97;\n *(__m128i *)(v99 + 28) = v98;\n }\n ++v68;\n v66 += 11;\n if (v63 == v68) goto LABEL_29;\n }\n }\n v67 = 0;\nLABEL_29:\n HIDWORD(v103) = v67;\n *a1 = v102[0];\n *(uint64_t *)((char *)a1 + 436) = v103;\n qmemcpy((void *)((unsigned long long)(a1 + 1) & 18446744073709551608LL),\n (const void *)((char *)v102 -\n ((char *)a1 - ((unsigned long long)(a1 + 1) &\n 18446744073709551608LL))),\n 8LL * (((unsigned int)a1 - (((uint32_t)a1 + 8) & 4294967288) + 444) >>\n 3));\n return a1;\n}", + "ida_pseudo_norm": "uint64_t *func0(uint64_t *a1, signed int a2, int a3, long long a4, long long a5,\n long long a6, int a7, int a8, int a9, int a10, int a11, int a12,\n int a13, int a14, int a15, int a16, int a17, int a18, int a19,\n int a20, int a21, int a22, int a23, int a24, int a25, int a26,\n int a27, int a28, int a29, int a30, int a31, int a32, int a33,\n int a34, int a35, int a36, int a37, int a38, int a39, int a40,\n int a41, int a42, int a43, int a44, int a45, int a46, int a47,\n int a48, int a49, int a50, int a51, int a52, int a53, int a54,\n int a55, int a56, int a57, int a58, int a59, int a60, int a61,\n int a62) {\n int v63;\n int *v66;\n int v67;\n int v68;\n unsigned int v69;\n __m128i v70;\n __m128i v71;\n __m128i v72;\n __m128i v73;\n __m128i v74;\n __m128i v75;\n __m128i v76;\n __m128i v77;\n __m128i v78;\n __m128i v79;\n __m128i v80;\n __m128i v81;\n __m128i v82;\n int v83;\n __m128i v84;\n __m128i v85;\n __m128i v86;\n __m128i v87;\n __m128i v88;\n signed int v89;\n signed int v90;\n long long v91;\n signed int v92;\n signed int v93;\n int v94;\n signed int v95;\n long long v96;\n __m128i v97;\n __m128i v98;\n char *v99;\n int v100;\n uint64_t v102[54];\n long long v103;\n unsigned long long v104;\n v104 = __readfsqword(40u);\n v63 = a62;\n if (a62 > 0) {\n v66 = &a7;\n v67 = 0;\n v68 = 0;\n while (1) {\n v100 = v66[10];\n v89 = *v66;\n if (v100 > 1) {\n v69 = v100 - 1;\n if ((unsigned int)(v100 - 2) <= 2) {\n v83 = *v66;\n v90 = 1;\n } else {\n v70 = _mm_loadu_si128((const __m128i *)(v66 + 1));\n v71 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v89), 0);\n v72 = _mm_cmpgt_epi32(v71, v70);\n v73 =\n _mm_or_si128(_mm_andnot_si128(v72, v71), _mm_and_si128(v70, v72));\n v74 =\n _mm_or_si128(_mm_andnot_si128(v72, v70), _mm_and_si128(v71, v72));\n if (v69 >> 2 != 1) {\n v75 = _mm_loadu_si128((const __m128i *)(v66 + 5));\n v76 = _mm_cmpgt_epi32(v75, v73);\n v73 = _mm_or_si128(_mm_and_si128(v73, v76),\n _mm_andnot_si128(v76, v75));\n v77 = _mm_cmpgt_epi32(v75, v74);\n v74 = _mm_or_si128(_mm_andnot_si128(v77, v74),\n _mm_and_si128(v75, v77));\n }\n v78 = _mm_srli_si128(v74, 8);\n v79 = _mm_cmpgt_epi32(v78, v74);\n v80 =\n _mm_or_si128(_mm_andnot_si128(v79, v74), _mm_and_si128(v78, v79));\n v81 = _mm_srli_si128(v80, 4);\n v82 = _mm_cmpgt_epi32(v81, v80);\n v83 = _mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v82, v80),\n _mm_and_si128(v81, v82)));\n v84 = _mm_srli_si128(v73, 8);\n v85 = _mm_cmpgt_epi32(v84, v73);\n v86 =\n _mm_or_si128(_mm_and_si128(v73, v85), _mm_andnot_si128(v85, v84));\n v87 = _mm_srli_si128(v86, 4);\n v88 = _mm_cmpgt_epi32(v87, v86);\n v89 = _mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v88, v87),\n _mm_and_si128(v86, v88)));\n if ((v69 & 3) == 0) goto LABEL_22;\n v90 = (v69 & 4294967292) + 1;\n }\n v91 = 11LL * v68;\n v92 = *(&a7 + v91 + v90);\n if (v89 > v92) v89 = *(&a7 + v91 + v90);\n if (v83 < v92) v83 = *(&a7 + v91 + v90);\n if (v90 + 1 < v100) {\n v93 = *(&a7 + v91 + v90 + 1);\n if (v89 > v93) v89 = *(&a7 + v91 + v90 + 1);\n if (v83 < v93) v83 = *(&a7 + v91 + v90 + 1);\n v94 = v90 + 2;\n if (v100 > v94) {\n v95 = *(&a7 + v94 + v91);\n if (v89 > v95) v89 = v95;\n if (v83 < v95) v83 = v95;\n }\n }\n } else {\n v83 = *v66;\n }\n LABEL_22:\n if (a2 <= v89 && a3 >= v83) {\n v96 = v67;\n v97 = _mm_loadu_si128((const __m128i *)v66 + 1);\n ++v67;\n v96 *= 44LL;\n *(__m128i *)((char *)v102 + v96) =\n _mm_loadu_si128((const __m128i *)v66);\n v98 = _mm_loadu_si128((const __m128i *)(v66 + 7));\n v99 = (char *)v102 + v96;\n *((__m128i *)v99 + 1) = v97;\n *(__m128i *)(v99 + 28) = v98;\n }\n ++v68;\n v66 += 11;\n if (v63 == v68) goto LABEL_29;\n }\n }\n v67 = 0;\nLABEL_29:\n HIDWORD(v103) = v67;\n *a1 = v102[0];\n *(uint64_t *)((char *)a1 + 436) = v103;\n qmemcpy((void *)((unsigned long long)(a1 + 1) & 18446744073709551608LL),\n (const void *)((char *)v102 -\n ((char *)a1 - ((unsigned long long)(a1 + 1) &\n 18446744073709551608LL))),\n 8LL * (((unsigned int)a1 - (((uint32_t)a1 + 8) & 4294967288) + 444) >>\n 3));\n return a1;\n}" + }, + { + "index": 870, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int nums[], int size) {\n int sum = 0;\n for (int i = 0; i < size; i++) {\n if (nums[i] > 0) {\n sum += nums[i];\n }\n }\n return sum;\n}", + "test": "int main() {\n\n int array1[] = {2, 4, -6, -9, 11, -12, 14, -5, 17};\n\n int array2[] = {10, 15, -14, 13, -18, 12, -20};\n\n int array3[] = {19, -65, 57, 39, 152, -639, 121, 44, 90, -190};\n\n \n\n assert(func0(array1, sizeof(array1)/sizeof(array1[0])) == 48);\n\n assert(func0(array2, sizeof(array2)/sizeof(array2[0])) == 50);\n\n assert(func0(array3, sizeof(array3)/sizeof(array3[0])) == 522);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11bf \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ntest %eax,%eax\njle 11bb \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nadd %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1188 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11BF\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njle short loc_11BB\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nloc_11BB:\nadd [rbp+var_4], 1\nloc_11BF:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(int *)(4LL * i + a1) > 0 )\n v3 += *(_DWORD *)(4LL * i + a1);\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11BF\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njle short loc_11BB\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nloc_11BB:\nadd [rbp+var_4], 1\nloc_11BF:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(int *)(4LL * i + a1) > 0 )\n v3 += *(_DWORD *)(4LL * i + a1);\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(int *)(4LL * i + a1) > 0) v3 += *(uint32_t *)(4LL * i + a1);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(int *)(4LL * i + a1) > 0) v3 += *(uint32_t *)(4LL * i + a1);\n }\n return v3;\n}" + }, + { + "index": 870, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int nums[], int size) {\n int sum = 0;\n for (int i = 0; i < size; i++) {\n if (nums[i] > 0) {\n sum += nums[i];\n }\n }\n return sum;\n}", + "test": "int main() {\n\n int array1[] = {2, 4, -6, -9, 11, -12, 14, -5, 17};\n\n int array2[] = {10, 15, -14, 13, -18, 12, -20};\n\n int array3[] = {19, -65, 57, 39, 152, -639, 121, 44, 90, -190};\n\n \n\n assert(func0(array1, sizeof(array1)/sizeof(array1[0])) == 48);\n\n assert(func0(array2, sizeof(array2)/sizeof(array2[0])) == 50);\n\n assert(func0(array3, sizeof(array3)/sizeof(array3[0])) == 522);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1197 \nmov %rdi,%rax\nlea -0x1(%rsi),%edx\nlea 0x4(%rdi,%rdx,4),%rdi\nmov $0x0,%edx\nmov (%rax),%ecx\nlea (%rdx,%rcx,1),%esi\ntest %ecx,%ecx\ncmovg %esi,%edx\nadd $0x4,%rax\ncmp %rdi,%rax\njne 1181 \nmov %edx,%eax\nretq\nmov $0x0,%edx\njmp 1194 \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1196\nmov rax, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*4]\nmov edx, 0\nloc_1180:\nmov ecx, [rax]\nlea esi, [rdx+rcx]\ntest ecx, ecx\ncmovg edx, esi\nadd rax, 4\ncmp rax, rdi\njnz short loc_1180\nloc_1193:\nmov eax, edx\nretn\nloc_1196:\nmov edx, 0\njmp short loc_1193", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int *v2; // rax\n int *v3; // rdi\n unsigned int v4; // edx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n {\n if ( *v2 > 0 )\n v4 += *v2;\n ++v2;\n }\n while ( v2 != v3 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_1196\nmov rax, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*4]\nmov edx, 0\nloc_1180:\nmov ecx, [rax]\nlea esi, [rdx+rcx]\ntest ecx, ecx\ncmovg edx, esi\nadd rax, 4\ncmp rax, rdi\njnz short loc_1180\nloc_1193:\nmov eax, edx\nretn\nloc_1196:\nmov edx, 0\njmp short loc_1193", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int *a1, int a2)\n{\n int *v2; // rax\n int *v3; // rdi\n unsigned int v4; // edx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do\n {\n if ( *v2 > 0 )\n v4 += *v2;\n ++v2;\n }\n while ( v2 != v3 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int *a1, int a2) {\n int *v2;\n int *v3;\n unsigned int v4;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do {\n if (*v2 > 0) v4 += *v2;\n ++v2;\n } while (v2 != v3);\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int *v2;\n int *v3;\n unsigned int v4;\n if (a2 <= 0) {\n return 0;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n v4 = 0;\n do {\n if (*v2 > 0) v4 += *v2;\n ++v2;\n } while (v2 != v3);\n }\n return v4;\n}" + }, + { + "index": 871, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char *string1, char *string2) {\n int size1 = strlen(string1);\n int size2 = strlen(string2);\n if (size1 != size2) return 0;\n char temp[2 * size1 + 1];\n strcpy(temp, string1);\n strcat(temp, string1);\n if (strstr(temp, string2) != NULL)\n return 1;\n else\n return 0;\n}", + "test": "int main() {\n\n assert(func0(\"abc\", \"cba\") == 0);\n\n assert(func0(\"abcd\", \"cdba\") == 0);\n\n assert(func0(\"abacd\", \"cdaba\") == 1);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0x38,%rsp\nmov %rdi,-0x58(%rbp)\nmov %rsi,-0x60(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nmov %rsp,%rax\nmov %rax,%rbx\nmov -0x58(%rbp),%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %eax,-0x50(%rbp)\nmov -0x60(%rbp),%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %eax,-0x4c(%rbp)\nmov -0x50(%rbp),%eax\ncmp -0x4c(%rbp),%eax\nje 124b \nmov $0x0,%eax\njmpq 133e \nmov -0x50(%rbp),%eax\nadd %eax,%eax\nadd $0x1,%eax\nmovslq %eax,%rdx\nsub $0x1,%rdx\nmov %rdx,-0x48(%rbp)\nmovslq %eax,%rdx\nmov %rdx,%r14\nmov $0x0,%r15d\nmovslq %eax,%rdx\nmov %rdx,%r12\nmov $0x0,%r13d\ncltq\nmov $0x10,%edx\nsub $0x1,%rdx\nadd %rdx,%rax\nmov $0x10,%ecx\nmov $0x0,%edx\ndiv %rcx\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rcx\nsub %rdx,%rcx\nmov %rcx,%rdx\ncmp %rdx,%rsp\nje 12bf \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 12a8 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 12e9 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x0,%rax\nmov %rax,-0x40(%rbp)\nmov -0x58(%rbp),%rdx\nmov -0x40(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10a0 \nmov -0x58(%rbp),%rdx\nmov -0x40(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10e0 \nmov -0x60(%rbp),%rdx\nmov -0x40(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10f0 \ntest %rax,%rax\nje 1339 \nmov $0x1,%eax\njmp 133e \nmov $0x0,%eax\nmov %rbx,%rsp\nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\nje 1355 \ncallq 10c0 <__stack_chk_fail@plt>\nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+s], rdi\nmov [rbp+needle], rsi\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov rax, rsp\nmov rbx, rax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_30], eax\nmov rax, [rbp+needle]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_2C], eax\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_2C]\njz short loc_1243\nmov eax, 0\njmp loc_131B\nloc_1243:\nmov eax, [rbp+var_30]\nadd eax, eax\nadd eax, 1\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_28], rdx\ncdqe\nmov edx, 10h\nsub rdx, 1\nadd rax, rdx\nmov esi, 10h\nmov edx, 0\ndiv rsi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_1285:\ncmp rsp, rdx\njz short loc_129C\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_1285\nloc_129C:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_12C6\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_12C6:\nmov rax, rsp\nadd rax, 0\nmov [rbp+dest], rax\nmov rdx, [rbp+s]\nmov rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\nmov rdx, [rbp+s]\nmov rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\nmov rdx, [rbp+needle]\nmov rax, [rbp+dest]\nmov rsi, rdx; needle\nmov rdi, rax; haystack\ncall _strstr\ntest rax, rax\njz short loc_1316\nmov eax, 1\njmp short loc_131B\nloc_1316:\nmov eax, 0\nloc_131B:\nmov rsp, rbx\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njz short loc_1332\ncall ___stack_chk_fail\nloc_1332:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(char *a1, char *a2)\n{\n int v3; // eax\n unsigned __int64 v4; // rax\n void *v5; // rsp\n char *needle; // [rsp+8h] [rbp-40h] BYREF\n char *s; // [rsp+10h] [rbp-38h]\n int v8; // [rsp+18h] [rbp-30h]\n int v9; // [rsp+1Ch] [rbp-2Ch]\n __int64 v10; // [rsp+20h] [rbp-28h]\n char *dest; // [rsp+28h] [rbp-20h]\n unsigned __int64 v12; // [rsp+30h] [rbp-18h]\n\n s = a1;\n needle = a2;\n v12 = __readfsqword(0x28u);\n v8 = strlen(a1);\n v9 = strlen(a2);\n if ( v8 != v9 )\n return 0LL;\n v3 = 2 * v8 + 1;\n v10 = v3 - 1LL;\n v4 = 16 * ((v3 + 15LL) / 0x10uLL);\n while ( &needle != (char **)((char *)&needle - (v4 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v5 = alloca(v4 & 0xFFF);\n if ( (v4 & 0xFFF) != 0 )\n *(char **)((char *)&needle + (v4 & 0xFFF) - 8) = *(char **)((char *)&needle + (v4 & 0xFFF) - 8);\n dest = (char *)&needle;\n strcpy((char *)&needle, s);\n strcat(dest, s);\n return strstr(dest, needle) != 0LL;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+s], rdi\nmov [rbp+needle], rsi\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov rax, rsp\nmov rbx, rax\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_30], eax\nmov rax, [rbp+needle]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_2C], eax\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_2C]\njz short loc_1243\nmov eax, 0\njmp loc_131B\nloc_1243:\nmov eax, [rbp+var_30]\nadd eax, eax\nadd eax, 1\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_28], rdx\ncdqe\nmov edx, 10h\nsub rdx, 1\nadd rax, rdx\nmov esi, 10h\nmov edx, 0\ndiv rsi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_1285:\ncmp rsp, rdx\njz short loc_129C\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_1285\nloc_129C:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_12C6\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_12C6:\nmov rax, rsp\nadd rax, 0\nmov [rbp+dest], rax\nmov rdx, [rbp+s]\nmov rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\nmov rdx, [rbp+s]\nmov rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\nmov rdx, [rbp+needle]\nmov rax, [rbp+dest]\nmov rsi, rdx; needle\nmov rdi, rax; haystack\ncall _strstr\ntest rax, rax\njz short loc_1316\nmov eax, 1\njmp short loc_131B\nloc_1316:\nmov eax, 0\nloc_131B:\nmov rsp, rbx\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njz short loc_1332\ncall ___stack_chk_fail\nloc_1332:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_11E9(char *a1, char *a2)\n{\n int v3; // eax\n unsigned __int64 v4; // rax\n void *v5; // rsp\n char *needle; // [rsp+8h] [rbp-40h] BYREF\n char *s; // [rsp+10h] [rbp-38h]\n int v8; // [rsp+18h] [rbp-30h]\n int v9; // [rsp+1Ch] [rbp-2Ch]\n __int64 v10; // [rsp+20h] [rbp-28h]\n char *dest; // [rsp+28h] [rbp-20h]\n unsigned __int64 v12; // [rsp+30h] [rbp-18h]\n\n s = a1;\n needle = a2;\n v12 = __readfsqword(0x28u);\n v8 = strlen(a1);\n v9 = strlen(a2);\n if ( v8 != v9 )\n return 0LL;\n v3 = 2 * v8 + 1;\n v10 = v3 - 1LL;\n v4 = 16 * ((v3 + 15LL) / 0x10uLL);\n while ( &needle != (char **)((char *)&needle - (v4 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v5 = alloca(v4 & 0xFFF);\n if ( (v4 & 0xFFF) != 0 )\n *(char **)((char *)&needle + (v4 & 0xFFF) - 8) = *(char **)((char *)&needle + (v4 & 0xFFF) - 8);\n dest = (char *)&needle;\n strcpy((char *)&needle, s);\n strcat(dest, s);\n return strstr(dest, needle) != 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_11E9(char *a1, char *a2) {\n int v3;\n unsigned long long v4;\n void *v5;\n char *needle;\n char *s;\n int v8;\n int v9;\n long long v10;\n char *dest;\n unsigned long long v12;\n s = a1;\n needle = a2;\n v12 = __readfsqword(40u);\n v8 = strlen(a1);\n v9 = strlen(a2);\n if (v8 != v9) return 0LL;\n v3 = 2 * v8 + 1;\n v10 = v3 - 1LL;\n v4 = 16 * ((v3 + 15LL) / 16uLL);\n while (&needle != (char **)((char *)&needle - (v4 & 18446744073709547520LL)))\n ;\n v5 = alloca(v4 & 4095);\n if ((v4 & 4095) != 0)\n *(char **)((char *)&needle + (v4 & 4095) - 8) =\n *(char **)((char *)&needle + (v4 & 4095) - 8);\n dest = (char *)&needle;\n strcpy((char *)&needle, s);\n strcat(dest, s);\n return strstr(dest, needle) != 0LL;\n}", + "ida_pseudo_norm": "uint8_t func0(char *a1, char *a2) {\n int v3;\n unsigned long long v4;\n void *v5;\n char *needle;\n char *s;\n int v8;\n int v9;\n long long v10;\n char *dest;\n unsigned long long v12;\n s = a1;\n needle = a2;\n v12 = __readfsqword(40u);\n v8 = strlen(a1);\n v9 = strlen(a2);\n if (v8 != v9) return 0LL;\n v3 = 2 * v8 + 1;\n v10 = v3 - 1LL;\n v4 = 16 * ((v3 + 15LL) / 16uLL);\n while (&needle != (char **)((char *)&needle - (v4 & 18446744073709547520LL)))\n ;\n v5 = alloca(v4 & 4095);\n if ((v4 & 4095) != 0)\n *(char **)((char *)&needle + (v4 & 4095) - 8) =\n *(char **)((char *)&needle + (v4 & 4095) - 8);\n dest = (char *)&needle;\n strcpy((char *)&needle, s);\n strcat(dest, s);\n return strstr(dest, needle) != 0LL;\n}" + }, + { + "index": 871, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char *string1, char *string2) {\n int size1 = strlen(string1);\n int size2 = strlen(string2);\n if (size1 != size2) return 0;\n char temp[2 * size1 + 1];\n strcpy(temp, string1);\n strcat(temp, string1);\n if (strstr(temp, string2) != NULL)\n return 1;\n else\n return 0;\n}", + "test": "int main() {\n\n assert(func0(\"abc\", \"cba\") == 0);\n\n assert(func0(\"abcd\", \"cdba\") == 0);\n\n assert(func0(\"abacd\", \"cdaba\") == 1);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r12\npush %rbx\nsub $0x10,%rsp\nmov %rdi,%rbx\nmov %rsi,%r12\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmov $0xffffffffffffffff,%rsi\nmov %rsi,%rcx\nrepnz scas %es:(%rdi),%al\nnot %rcx\nlea -0x1(%rcx),%rdx\nmov %rsi,%rcx\nmov %r12,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nsub $0x1,%rax\nmov $0x0,%ecx\ncmp %eax,%edx\nje 1239 \nmov -0x18(%rbp),%rax\nxor %fs:0x28,%rax\njne 12b5 \nmov %ecx,%eax\nlea -0x10(%rbp),%rsp\npop %rbx\npop %r12\npop %rbp\nretq\nlea 0x1(%rdx,%rdx,1),%eax\ncltq\nadd $0xf,%rax\nmov %rax,%rdx\nand $0xfffffffffffffff0,%rdx\nand $0xfffffffffffff000,%rax\nmov %rsp,%rsi\nsub %rax,%rsi\nmov %rsi,%rax\ncmp %rax,%rsp\nje 1270 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 1259 \nmov %rdx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 1286 \norq $0x0,-0x8(%rsp,%rax,1)\nmov %rbx,%rsi\nmov %rsp,%rdi\ncallq 1090 \nmov %rbx,%rsi\nmov %rsp,%rdi\ncallq 10c0 \nmov %r12,%rsi\nmov %rsp,%rdi\ncallq 10d0 \ntest %rax,%rax\nsetne %cl\nmovzbl %cl,%ecx\njmpq 121b \ncallq 10a0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r13\npush r12\npush rbx\nsub rsp, 18h\nmov r12, rdi\nmov r13, rsi\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\ncall _strlen\nmov rbx, rax\nmov rdi, r13; s\ncall _strlen\nmov rdx, rax\nmov eax, 0\ncmp ebx, edx\njz short loc_1249\nloc_122B:\nmov rdx, [rbp+var_28]\nsub rdx, fs:28h\njnz loc_12C9\nlea rsp, [rbp-18h]\npop rbx\npop r12\npop r13\npop rbp\nretn\nloc_1249:\nlea ebx, [rbx+rbx+1]\nmovsxd rbx, ebx\nlea rax, [rbx+0Fh]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_1267:\ncmp rsp, rdx\njz short loc_127E\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\njmp short loc_1267\nloc_127E:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_1294\nor [rsp+rax+30h+var_38], 0\nloc_1294:\nmov rdx, rbx\nmov rsi, r12\nmov rdi, rsp\ncall ___strcpy_chk\nmov rdx, rbx\nmov rsi, r12\nmov rdi, rsp\ncall ___strcat_chk\nmov rsi, r13; needle\nmov rdi, rsp; haystack\ncall _strstr\ntest rax, rax\nsetnz al\nmovzx eax, al\njmp loc_122B\nloc_12C9:\ncall ___stack_chk_fail", + "ida_pseudo": "_BOOL8 __fastcall func0(const char *a1, const char *a2)\n{\n int v2; // ebx\n int v3; // edx\n _BOOL8 result; // rax\n __int64 v5; // rbx\n signed __int64 v6; // rax\n void *v7; // rsp\n char v9[8]; // [rsp+8h] [rbp-30h] BYREF\n unsigned __int64 v10; // [rsp+10h] [rbp-28h]\n\n v10 = __readfsqword(0x28u);\n v2 = strlen(a1);\n v3 = strlen(a2);\n result = 0LL;\n if ( v2 == v3 )\n {\n v5 = 2 * v2 + 1;\n while ( v9 != &v9[-((v5 + 15) & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v6 = ((_WORD)v5 + 15) & 0xFF0;\n v7 = alloca(v6);\n if ( (((_WORD)v5 + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v9[v6 - 8] = *(_QWORD *)&v9[v6 - 8];\n __strcpy_chk(v9, a1, v5);\n __strcat_chk(v9, a1, v5);\n return strstr(v9, a2) != 0LL;\n }\n return result;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\npush r13\npush r12\npush rbx\nsub rsp, 18h\nmov r12, rdi\nmov r13, rsi\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\ncall _strlen\nmov rbx, rax\nmov rdi, r13; s\ncall _strlen\nmov rdx, rax\nmov eax, 0\ncmp ebx, edx\njz short loc_1249\nloc_122B:\nmov rdx, [rbp+var_28]\nsub rdx, fs:28h\njnz loc_12C9\nlea rsp, [rbp-18h]\npop rbx\npop r12\npop r13\npop rbp\nretn\nloc_1249:\nlea ebx, [rbx+rbx+1]\nmovsxd rbx, ebx\nlea rax, [rbx+0Fh]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_1267:\ncmp rsp, rdx\njz short loc_127E\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\njmp short loc_1267\nloc_127E:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_1294\nor [rsp+rax+30h+var_38], 0\nloc_1294:\nmov rdx, rbx\nmov rsi, r12\nmov rdi, rsp\ncall ___strcpy_chk\nmov rdx, rbx\nmov rsi, r12\nmov rdi, rsp\ncall ___strcat_chk\nmov rsi, r13; needle\nmov rdi, rsp; haystack\ncall _strstr\ntest rax, rax\nsetnz al\nmovzx eax, al\njmp loc_122B\nloc_12C9:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_11E9(const char *a1, const char *a2)\n{\n int v2; // ebx\n int v3; // edx\n _BOOL8 result; // rax\n __int64 v5; // rbx\n signed __int64 v6; // rax\n void *v7; // rsp\n char v9[8]; // [rsp+8h] [rbp-30h] BYREF\n unsigned __int64 v10; // [rsp+10h] [rbp-28h]\n\n v10 = __readfsqword(0x28u);\n v2 = strlen(a1);\n v3 = strlen(a2);\n result = 0LL;\n if ( v2 == v3 )\n {\n v5 = 2 * v2 + 1;\n while ( v9 != &v9[-((v5 + 15) & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v6 = ((_WORD)v5 + 15) & 0xFF0;\n v7 = alloca(v6);\n if ( (((_WORD)v5 + 15) & 0xFF0) != 0 )\n *(_QWORD *)&v9[v6 - 8] = *(_QWORD *)&v9[v6 - 8];\n __strcpy_chk(v9, a1, v5);\n __strcat_chk(v9, a1, v5);\n return strstr(v9, a2) != 0LL;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_11E9(const char *a1, const char *a2) {\n int v2;\n int v3;\n uint8_t result;\n long long v5;\n signed long long v6;\n void *v7;\n char v9[8];\n unsigned long long v10;\n v10 = __readfsqword(40u);\n v2 = strlen(a1);\n v3 = strlen(a2);\n result = 0LL;\n if (v2 == v3) {\n v5 = 2 * v2 + 1;\n while (v9 != &v9[-((v5 + 15) & 18446744073709547520LL)])\n ;\n v6 = ((unsigned short)v5 + 15) & 4080;\n v7 = alloca(v6);\n if ((((unsigned short)v5 + 15) & 4080) != 0)\n *(uint64_t *)&v9[v6 - 8] = *(uint64_t *)&v9[v6 - 8];\n __strcpy_chk(v9, a1, v5);\n __strcat_chk(v9, a1, v5);\n return strstr(v9, a2) != 0LL;\n }\n return result;\n}", + "ida_pseudo_norm": "uint8_t func0(const char *a1, const char *a2) {\n int v2;\n int v3;\n uint8_t result;\n long long v5;\n signed long long v6;\n void *v7;\n char v9[8];\n unsigned long long v10;\n v10 = __readfsqword(40u);\n v2 = strlen(a1);\n v3 = strlen(a2);\n result = 0LL;\n if (v2 == v3) {\n v5 = 2 * v2 + 1;\n while (v9 != &v9[-((v5 + 15) & 18446744073709547520LL)])\n ;\n v6 = ((unsigned short)v5 + 15) & 4080;\n v7 = alloca(v6);\n if ((((unsigned short)v5 + 15) & 4080) != 0)\n *(uint64_t *)&v9[v6 - 8] = *(uint64_t *)&v9[v6 - 8];\n __strcpy_chk(v9, a1, v5);\n __strcat_chk(v9, a1, v5);\n return strstr(v9, a2) != 0LL;\n }\n return result;\n}" + }, + { + "index": 871, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char *string1, char *string2) {\n int size1 = strlen(string1);\n int size2 = strlen(string2);\n if (size1 != size2) return 0;\n char temp[2 * size1 + 1];\n strcpy(temp, string1);\n strcat(temp, string1);\n if (strstr(temp, string2) != NULL)\n return 1;\n else\n return 0;\n}", + "test": "int main() {\n\n assert(func0(\"abc\", \"cba\") == 0);\n\n assert(func0(\"abcd\", \"cdba\") == 0);\n\n assert(func0(\"abacd\", \"cdaba\") == 1);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r13\nmov %rdi,%r13\npush %r12\nmov %rsi,%r12\npush %rbx\nsub $0x18,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x28(%rbp)\nxor %eax,%eax\ncallq 1090 \nmov %r12,%rdi\nmov %rax,%rbx\ncallq 1090 \nmov %rax,%r8\nxor %eax,%eax\ncmp %r8d,%ebx\nje 12f0 \nmov -0x28(%rbp),%rcx\nxor %fs:0x28,%rcx\njne 1378 \nlea -0x18(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %rbp\nretq\nxchg %ax,%ax\nlea 0x1(%rbx,%rbx,1),%eax\nmov %rsp,%rcx\ncltq\nadd $0xf,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rcx\nand $0xfffffffffffffff0,%rdx\nmov %rcx,%rax\ncmp %rax,%rsp\nje 132a \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 1315 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 1370 \nmov %rbx,%rdx\nmov %r13,%rsi\nmov %rsp,%rdi\ncallq 10c0 \nlea (%rsp,%rbx,1),%rdi\nlea 0x1(%rbx),%rdx\nmov %r13,%rsi\ncallq 10c0 \nmov %r12,%rsi\nmov %rsp,%rdi\ncallq 10d0 \ntest %rax,%rax\nsetne %al\nmovzbl %al,%eax\njmpq 12d0 \norq $0x0,-0x8(%rsp,%rdx,1)\njmp 1338 \ncallq 10a0 <__stack_chk_fail@plt>\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r14\npush r13\nmov r13, rsi\npush r12\nmov r12, rdi\npush rbx\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\ncall _strlen\nmov rdi, r13; s\nmov rbx, rax\ncall _strlen\nmov rdx, rax\nxor eax, eax\ncmp ebx, edx\njz short loc_12F8\nloc_12D1:\nmov rdx, [rbp+var_28]\nsub rdx, fs:28h\njnz loc_1388\nlea rsp, [rbp-20h]\npop rbx\npop r12\npop r13\npop r14\npop rbp\nretn\nloc_12F8:\nlea r14d, [rbx+rbx+1]\nmov rcx, rsp\nmovsxd r14, r14d\nlea rax, [r14+0Fh]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_1331\nloc_131C:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rcx\njnz short loc_131C\nloc_1331:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz short loc_1380\nloc_133F:\nmov rcx, r14\nmov rdx, rbx\nmov rsi, r12\nmov rdi, rsp\ncall ___memcpy_chk\nmov rcx, r14\nlea rdx, [rbx+1]\nlea rdi, [rsp+rbx+1030h+var_1030]\nsub rcx, rbx\nmov rsi, r12\ncall ___memcpy_chk\nmov rsi, r13; needle\nmov rdi, rsp; haystack\ncall _strstr\ntest rax, rax\nsetnz al\nmovzx eax, al\njmp loc_12D1\nloc_1380:\nor [rsp+rdx+1030h+var_1038], 0\njmp short loc_133F\nloc_1388:\ncall ___stack_chk_fail", + "ida_pseudo": "_BOOL8 __fastcall func0(const char *a1, const char *a2)\n{\n size_t v2; // rbx\n int v3; // edx\n _BOOL8 result; // rax\n __int64 v5; // r14\n char *v6; // rcx\n signed __int64 v7; // rdx\n void *v8; // rsp\n char v10[4088]; // [rsp+8h] [rbp-1030h] BYREF\n _QWORD v11[6]; // [rsp+1008h] [rbp-30h] BYREF\n\n v11[1] = __readfsqword(0x28u);\n v2 = strlen(a1);\n v3 = strlen(a2);\n result = 0LL;\n if ( (_DWORD)v2 == v3 )\n {\n v5 = 2 * (int)v2 + 1;\n v6 = (char *)v11 - ((v5 + 15) & 0xFFFFFFFFFFFFF000LL);\n if ( v11 != (_QWORD *)v6 )\n {\n while ( v10 != v6 )\n ;\n }\n v7 = (2 * (_WORD)v2 + 16) & 0xFF0;\n v8 = alloca(v7);\n if ( ((2 * (_WORD)v2 + 16) & 0xFF0) != 0 )\n *(_QWORD *)&v10[v7 - 8] = *(_QWORD *)&v10[v7 - 8];\n __memcpy_chk(v10, a1, v2, 2 * (int)v2 + 1);\n __memcpy_chk(&v10[v2], a1, v2 + 1, v5 - v2);\n return strstr(v10, a2) != 0LL;\n }\n return result;\n}", + "ida_strip_asm": "sub_1290:\nendbr64\npush rbp\nmov rbp, rsp\npush r14\npush r13\nmov r13, rsi\npush r12\nmov r12, rdi\npush rbx\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\ncall _strlen\nmov rdi, r13; s\nmov rbx, rax\ncall _strlen\nmov rdx, rax\nxor eax, eax\ncmp ebx, edx\njz short loc_12F8\nloc_12D1:\nmov rdx, [rbp+var_28]\nsub rdx, fs:28h\njnz loc_1388\nlea rsp, [rbp-20h]\npop rbx\npop r12\npop r13\npop r14\npop rbp\nretn\nloc_12F8:\nlea r14d, [rbx+rbx+1]\nmov rcx, rsp\nmovsxd r14, r14d\nlea rax, [r14+0Fh]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_1331\nloc_131C:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rcx\njnz short loc_131C\nloc_1331:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz short loc_1380\nloc_133F:\nmov rcx, r14\nmov rdx, rbx\nmov rsi, r12\nmov rdi, rsp\ncall ___memcpy_chk\nmov rcx, r14\nlea rdx, [rbx+1]\nlea rdi, [rsp+rbx+1030h+var_1030]\nsub rcx, rbx\nmov rsi, r12\ncall ___memcpy_chk\nmov rsi, r13; needle\nmov rdi, rsp; haystack\ncall _strstr\ntest rax, rax\nsetnz al\nmovzx eax, al\njmp loc_12D1\nloc_1380:\nor [rsp+rdx+1030h+var_1038], 0\njmp short loc_133F\nloc_1388:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1290(const char *a1, const char *a2)\n{\n size_t v2; // rbx\n int v3; // edx\n _BOOL8 result; // rax\n __int64 v5; // r14\n char *v6; // rcx\n signed __int64 v7; // rdx\n void *v8; // rsp\n char v10[4088]; // [rsp+8h] [rbp-1030h] BYREF\n _QWORD v11[6]; // [rsp+1008h] [rbp-30h] BYREF\n\n v11[1] = __readfsqword(0x28u);\n v2 = strlen(a1);\n v3 = strlen(a2);\n result = 0LL;\n if ( (_DWORD)v2 == v3 )\n {\n v5 = 2 * (int)v2 + 1;\n v6 = (char *)v11 - ((v5 + 15) & 0xFFFFFFFFFFFFF000LL);\n if ( v11 != (_QWORD *)v6 )\n {\n while ( v10 != v6 )\n ;\n }\n v7 = (2 * (_WORD)v2 + 16) & 0xFF0;\n v8 = alloca(v7);\n if ( ((2 * (_WORD)v2 + 16) & 0xFF0) != 0 )\n *(_QWORD *)&v10[v7 - 8] = *(_QWORD *)&v10[v7 - 8];\n __memcpy_chk(v10, a1, v2, 2 * (int)v2 + 1);\n __memcpy_chk(&v10[v2], a1, v2 + 1, v5 - v2);\n return strstr(v10, a2) != 0LL;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1290(const char *a1, const char *a2) {\n unsigned int v2;\n int v3;\n uint8_t result;\n long long v5;\n char *v6;\n signed long long v7;\n void *v8;\n char v10[4088];\n uint64_t v11[6];\n v11[1] = __readfsqword(40u);\n v2 = strlen(a1);\n v3 = strlen(a2);\n result = 0LL;\n if ((uint32_t)v2 == v3) {\n v5 = 2 * (int)v2 + 1;\n v6 = (char *)v11 - ((v5 + 15) & 18446744073709547520LL);\n if (v11 != (uint64_t *)v6) {\n while (v10 != v6)\n ;\n }\n v7 = (2 * (unsigned short)v2 + 16) & 4080;\n v8 = alloca(v7);\n if (((2 * (unsigned short)v2 + 16) & 4080) != 0)\n *(uint64_t *)&v10[v7 - 8] = *(uint64_t *)&v10[v7 - 8];\n __memcpy_chk(v10, a1, v2, 2 * (int)v2 + 1);\n __memcpy_chk(&v10[v2], a1, v2 + 1, v5 - v2);\n return strstr(v10, a2) != 0LL;\n }\n return result;\n}", + "ida_pseudo_norm": "uint8_t func0(const char *a1, const char *a2) {\n unsigned int v2;\n int v3;\n uint8_t result;\n long long v5;\n char *v6;\n signed long long v7;\n void *v8;\n char v10[4088];\n uint64_t v11[6];\n v11[1] = __readfsqword(40u);\n v2 = strlen(a1);\n v3 = strlen(a2);\n result = 0LL;\n if ((uint32_t)v2 == v3) {\n v5 = 2 * (int)v2 + 1;\n v6 = (char *)v11 - ((v5 + 15) & 18446744073709547520LL);\n if (v11 != (uint64_t *)v6) {\n while (v10 != v6)\n ;\n }\n v7 = (2 * (unsigned short)v2 + 16) & 4080;\n v8 = alloca(v7);\n if (((2 * (unsigned short)v2 + 16) & 4080) != 0)\n *(uint64_t *)&v10[v7 - 8] = *(uint64_t *)&v10[v7 - 8];\n __memcpy_chk(v10, a1, v2, 2 * (int)v2 + 1);\n __memcpy_chk(&v10[v2], a1, v2 + 1, v5 - v2);\n return strstr(v10, a2) != 0LL;\n }\n return result;\n}" + }, + { + "index": 871, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char *string1, char *string2) {\n int size1 = strlen(string1);\n int size2 = strlen(string2);\n if (size1 != size2) return 0;\n char temp[2 * size1 + 1];\n strcpy(temp, string1);\n strcat(temp, string1);\n if (strstr(temp, string2) != NULL)\n return 1;\n else\n return 0;\n}", + "test": "int main() {\n\n assert(func0(\"abc\", \"cba\") == 0);\n\n assert(func0(\"abcd\", \"cdba\") == 0);\n\n assert(func0(\"abacd\", \"cdaba\") == 1);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r13\nmov %rdi,%r13\npush %r12\nmov %rsi,%r12\npush %rbx\nsub $0x18,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x28(%rbp)\nxor %eax,%eax\ncallq 1090 \nmov %r12,%rdi\nmov %rax,%rbx\ncallq 1090 \nmov %rax,%r8\nxor %eax,%eax\ncmp %r8d,%ebx\nje 12f0 \nmov -0x28(%rbp),%rcx\nxor %fs:0x28,%rcx\njne 1378 \nlea -0x18(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %rbp\nretq\nxchg %ax,%ax\nlea 0x1(%rbx,%rbx,1),%eax\nmov %rsp,%rcx\ncltq\nadd $0xf,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rcx\nand $0xfffffffffffffff0,%rdx\nmov %rcx,%rax\ncmp %rax,%rsp\nje 132a \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 1315 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 1370 \nmov %rbx,%rdx\nmov %r13,%rsi\nmov %rsp,%rdi\ncallq 10c0 \nlea (%rsp,%rbx,1),%rdi\nlea 0x1(%rbx),%rdx\nmov %r13,%rsi\ncallq 10c0 \nmov %r12,%rsi\nmov %rsp,%rdi\ncallq 10d0 \ntest %rax,%rax\nsetne %al\nmovzbl %al,%eax\njmpq 12d0 \norq $0x0,-0x8(%rsp,%rdx,1)\njmp 1338 \ncallq 10a0 <__stack_chk_fail@plt>\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r14\npush r13\nmov r13, rsi\npush r12\nmov r12, rdi\npush rbx\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\ncall _strlen\nmov rdi, r13; s\nmov rbx, rax\ncall _strlen\nmov rdx, rax\nxor eax, eax\ncmp ebx, edx\njz short loc_12F8\nloc_12D1:\nmov rdx, [rbp+var_28]\nsub rdx, fs:28h\njnz loc_1388\nlea rsp, [rbp-20h]\npop rbx\npop r12\npop r13\npop r14\npop rbp\nretn\nloc_12F8:\nlea r14d, [rbx+rbx+1]\nmov rcx, rsp\nmovsxd r14, r14d\nlea rax, [r14+0Fh]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_1331\nloc_131C:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rcx\njnz short loc_131C\nloc_1331:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz short loc_1380\nloc_133F:\nmov rcx, r14\nmov rdx, rbx\nmov rsi, r12\nmov rdi, rsp\ncall ___memcpy_chk\nmov rcx, r14\nlea rdx, [rbx+1]\nlea rdi, [rsp+rbx+1030h+var_1030]\nsub rcx, rbx\nmov rsi, r12\ncall ___memcpy_chk\nmov rsi, r13; needle\nmov rdi, rsp; haystack\ncall _strstr\ntest rax, rax\nsetnz al\nmovzx eax, al\njmp loc_12D1\nloc_1380:\nor [rsp+rdx+1030h+var_1038], 0\njmp short loc_133F\nloc_1388:\ncall ___stack_chk_fail", + "ida_pseudo": "_BOOL8 __fastcall func0(const char *a1, const char *a2)\n{\n size_t v2; // rbx\n int v3; // edx\n _BOOL8 result; // rax\n __int64 v5; // r14\n char *v6; // rcx\n signed __int64 v7; // rdx\n void *v8; // rsp\n char v10[4088]; // [rsp+8h] [rbp-1030h] BYREF\n _QWORD v11[6]; // [rsp+1008h] [rbp-30h] BYREF\n\n v11[1] = __readfsqword(0x28u);\n v2 = strlen(a1);\n v3 = strlen(a2);\n result = 0LL;\n if ( (_DWORD)v2 == v3 )\n {\n v5 = 2 * (int)v2 + 1;\n v6 = (char *)v11 - ((v5 + 15) & 0xFFFFFFFFFFFFF000LL);\n if ( v11 != (_QWORD *)v6 )\n {\n while ( v10 != v6 )\n ;\n }\n v7 = (2 * (_WORD)v2 + 16) & 0xFF0;\n v8 = alloca(v7);\n if ( ((2 * (_WORD)v2 + 16) & 0xFF0) != 0 )\n *(_QWORD *)&v10[v7 - 8] = *(_QWORD *)&v10[v7 - 8];\n __memcpy_chk(v10, a1, v2, 2 * (int)v2 + 1);\n __memcpy_chk(&v10[v2], a1, v2 + 1, v5 - v2);\n return strstr(v10, a2) != 0LL;\n }\n return result;\n}", + "ida_strip_asm": "sub_1290:\nendbr64\npush rbp\nmov rbp, rsp\npush r14\npush r13\nmov r13, rsi\npush r12\nmov r12, rdi\npush rbx\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\ncall _strlen\nmov rdi, r13; s\nmov rbx, rax\ncall _strlen\nmov rdx, rax\nxor eax, eax\ncmp ebx, edx\njz short loc_12F8\nloc_12D1:\nmov rdx, [rbp+var_28]\nsub rdx, fs:28h\njnz loc_1388\nlea rsp, [rbp-20h]\npop rbx\npop r12\npop r13\npop r14\npop rbp\nretn\nloc_12F8:\nlea r14d, [rbx+rbx+1]\nmov rcx, rsp\nmovsxd r14, r14d\nlea rax, [r14+0Fh]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_1331\nloc_131C:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rcx\njnz short loc_131C\nloc_1331:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz short loc_1380\nloc_133F:\nmov rcx, r14\nmov rdx, rbx\nmov rsi, r12\nmov rdi, rsp\ncall ___memcpy_chk\nmov rcx, r14\nlea rdx, [rbx+1]\nlea rdi, [rsp+rbx+1030h+var_1030]\nsub rcx, rbx\nmov rsi, r12\ncall ___memcpy_chk\nmov rsi, r13; needle\nmov rdi, rsp; haystack\ncall _strstr\ntest rax, rax\nsetnz al\nmovzx eax, al\njmp loc_12D1\nloc_1380:\nor [rsp+rdx+1030h+var_1038], 0\njmp short loc_133F\nloc_1388:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1290(const char *a1, const char *a2)\n{\n size_t v2; // rbx\n int v3; // edx\n _BOOL8 result; // rax\n __int64 v5; // r14\n char *v6; // rcx\n signed __int64 v7; // rdx\n void *v8; // rsp\n char v10[4088]; // [rsp+8h] [rbp-1030h] BYREF\n _QWORD v11[6]; // [rsp+1008h] [rbp-30h] BYREF\n\n v11[1] = __readfsqword(0x28u);\n v2 = strlen(a1);\n v3 = strlen(a2);\n result = 0LL;\n if ( (_DWORD)v2 == v3 )\n {\n v5 = 2 * (int)v2 + 1;\n v6 = (char *)v11 - ((v5 + 15) & 0xFFFFFFFFFFFFF000LL);\n if ( v11 != (_QWORD *)v6 )\n {\n while ( v10 != v6 )\n ;\n }\n v7 = (2 * (_WORD)v2 + 16) & 0xFF0;\n v8 = alloca(v7);\n if ( ((2 * (_WORD)v2 + 16) & 0xFF0) != 0 )\n *(_QWORD *)&v10[v7 - 8] = *(_QWORD *)&v10[v7 - 8];\n __memcpy_chk(v10, a1, v2, 2 * (int)v2 + 1);\n __memcpy_chk(&v10[v2], a1, v2 + 1, v5 - v2);\n return strstr(v10, a2) != 0LL;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1290(const char *a1, const char *a2) {\n unsigned int v2;\n int v3;\n uint8_t result;\n long long v5;\n char *v6;\n signed long long v7;\n void *v8;\n char v10[4088];\n uint64_t v11[6];\n v11[1] = __readfsqword(40u);\n v2 = strlen(a1);\n v3 = strlen(a2);\n result = 0LL;\n if ((uint32_t)v2 == v3) {\n v5 = 2 * (int)v2 + 1;\n v6 = (char *)v11 - ((v5 + 15) & 18446744073709547520LL);\n if (v11 != (uint64_t *)v6) {\n while (v10 != v6)\n ;\n }\n v7 = (2 * (unsigned short)v2 + 16) & 4080;\n v8 = alloca(v7);\n if (((2 * (unsigned short)v2 + 16) & 4080) != 0)\n *(uint64_t *)&v10[v7 - 8] = *(uint64_t *)&v10[v7 - 8];\n __memcpy_chk(v10, a1, v2, 2 * (int)v2 + 1);\n __memcpy_chk(&v10[v2], a1, v2 + 1, v5 - v2);\n return strstr(v10, a2) != 0LL;\n }\n return result;\n}", + "ida_pseudo_norm": "uint8_t func0(const char *a1, const char *a2) {\n unsigned int v2;\n int v3;\n uint8_t result;\n long long v5;\n char *v6;\n signed long long v7;\n void *v8;\n char v10[4088];\n uint64_t v11[6];\n v11[1] = __readfsqword(40u);\n v2 = strlen(a1);\n v3 = strlen(a2);\n result = 0LL;\n if ((uint32_t)v2 == v3) {\n v5 = 2 * (int)v2 + 1;\n v6 = (char *)v11 - ((v5 + 15) & 18446744073709547520LL);\n if (v11 != (uint64_t *)v6) {\n while (v10 != v6)\n ;\n }\n v7 = (2 * (unsigned short)v2 + 16) & 4080;\n v8 = alloca(v7);\n if (((2 * (unsigned short)v2 + 16) & 4080) != 0)\n *(uint64_t *)&v10[v7 - 8] = *(uint64_t *)&v10[v7 - 8];\n __memcpy_chk(v10, a1, v2, 2 * (int)v2 + 1);\n __memcpy_chk(&v10[v2], a1, v2 + 1, v5 - v2);\n return strstr(v10, a2) != 0LL;\n }\n return result;\n}" + }, + { + "index": 872, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int list1[][2], int size1, int list2[][2], int size2) {\n for (int i = 0; i < size2; i++) {\n bool found = false;\n for (int j = 0; j < size1; j++) {\n if (list1[j][0] == list2[i][0] && list1[j][1] == list2[i][1]) {\n found = true;\n break;\n }\n }\n if (!found) return false;\n }\n return true;\n}", + "test": "int main() {\n\n int list1[][2] = {{1, 3}, {5, 7}, {9, 11}, {13, 15}};\n\n int list2[][2] = {{1, 3}, {13, 15}};\n\n assert(func0(list1, 4, list2, 2) == true);\n\n\n\n int list3[][2] = {{1, 2}, {2, 3}, {3, 4}, {5, 6}};\n\n int list4[][2] = {{3, 4}, {5, 6}};\n\n assert(func0(list3, 4, list4, 2) == true);\n\n\n\n int list5[][2] = {{1, 2}, {3, 4}, {5, 7}, {8, 9}};\n\n int list6[][2] = {{3, 4}, {5, 6}};\n\n assert(func0(list5, 4, list6, 2) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %ecx,-0x20(%rbp)\nmovl $0x0,-0x8(%rbp)\njmpq 1222 \nmovb $0x0,-0x9(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 1204 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 1200 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov 0x4(%rax),%edx\nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov 0x4(%rax),%eax\ncmp %eax,%edx\njne 1200 \nmovb $0x1,-0x9(%rbp)\njmp 120c \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1198 \nmovzbl -0x9(%rbp),%eax\nxor $0x1,%eax\ntest %al,%al\nje 121e \nmov $0x0,%eax\njmp 1233 \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x20(%rbp),%eax\njl 118b \nmov $0x1,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov [rbp+var_8], 0\njmp loc_1222\nloc_118B:\nmov [rbp+var_9], 0\nmov [rbp+var_4], 0\njmp short loc_1204\nloc_1198:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_1200\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax+4]\nmov eax, [rbp+var_8]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax+4]\ncmp edx, eax\njnz short loc_1200\nmov [rbp+var_9], 1\njmp short loc_120C\nloc_1200:\nadd [rbp+var_4], 1\nloc_1204:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1198\nloc_120C:\nmovzx eax, [rbp+var_9]\nxor eax, 1\ntest al, al\njz short loc_121E\nmov eax, 0\njmp short loc_1233\nloc_121E:\nadd [rbp+var_8], 1\nloc_1222:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_20]\njl loc_118B\nmov eax, 1\nloc_1233:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3, int a4)\n{\n char v5; // [rsp+1Fh] [rbp-9h]\n int i; // [rsp+20h] [rbp-8h]\n int j; // [rsp+24h] [rbp-4h]\n\n for ( i = 0; i < a4; ++i )\n {\n v5 = 0;\n for ( j = 0; j < a2; ++j )\n {\n if ( *(_DWORD *)(8LL * j + a1) == *(_DWORD *)(8LL * i + a3)\n && *(_DWORD *)(8LL * j + a1 + 4) == *(_DWORD *)(8LL * i + a3 + 4) )\n {\n v5 = 1;\n break;\n }\n }\n if ( v5 != 1 )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov [rbp+var_8], 0\njmp loc_1222\nloc_118B:\nmov [rbp+var_9], 0\nmov [rbp+var_4], 0\njmp short loc_1204\nloc_1198:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_1200\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax+4]\nmov eax, [rbp+var_8]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax+4]\ncmp edx, eax\njnz short loc_1200\nmov [rbp+var_9], 1\njmp short loc_120C\nloc_1200:\nadd [rbp+var_4], 1\nloc_1204:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1198\nloc_120C:\nmovzx eax, [rbp+var_9]\nxor eax, 1\ntest al, al\njz short loc_121E\nmov eax, 0\njmp short loc_1233\nloc_121E:\nadd [rbp+var_8], 1\nloc_1222:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_20]\njl loc_118B\nmov eax, 1\nloc_1233:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, __int64 a3, int a4)\n{\n char v5; // [rsp+1Fh] [rbp-9h]\n int i; // [rsp+20h] [rbp-8h]\n int j; // [rsp+24h] [rbp-4h]\n\n for ( i = 0; i < a4; ++i )\n {\n v5 = 0;\n for ( j = 0; j < a2; ++j )\n {\n if ( *(_DWORD *)(8LL * j + a1) == *(_DWORD *)(8LL * i + a3)\n && *(_DWORD *)(8LL * j + a1 + 4) == *(_DWORD *)(8LL * i + a3 + 4) )\n {\n v5 = 1;\n break;\n }\n }\n if ( v5 != 1 )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, long long a3, int a4) {\n char v5;\n int i;\n int j;\n for (i = 0; i < a4; ++i) {\n v5 = 0;\n for (j = 0; j < a2; ++j) {\n if (*(uint32_t *)(8LL * j + a1) == *(uint32_t *)(8LL * i + a3) &&\n *(uint32_t *)(8LL * j + a1 + 4) == *(uint32_t *)(8LL * i + a3 + 4)) {\n v5 = 1;\n break;\n }\n }\n if (v5 != 1) return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3, int a4) {\n char v5;\n int i;\n int j;\n for (i = 0; i < a4; ++i) {\n v5 = 0;\n for (j = 0; j < a2; ++j) {\n if (*(uint32_t *)(8LL * j + a1) == *(uint32_t *)(8LL * i + a3) &&\n *(uint32_t *)(8LL * j + a1 + 4) == *(uint32_t *)(8LL * i + a3 + 4)) {\n v5 = 1;\n break;\n }\n }\n if (v5 != 1) return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": 872, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int list1[][2], int size1, int list2[][2], int size2) {\n for (int i = 0; i < size2; i++) {\n bool found = false;\n for (int j = 0; j < size1; j++) {\n if (list1[j][0] == list2[i][0] && list1[j][1] == list2[i][1]) {\n found = true;\n break;\n }\n }\n if (!found) return false;\n }\n return true;\n}", + "test": "int main() {\n\n int list1[][2] = {{1, 3}, {5, 7}, {9, 11}, {13, 15}};\n\n int list2[][2] = {{1, 3}, {13, 15}};\n\n assert(func0(list1, 4, list2, 2) == true);\n\n\n\n int list3[][2] = {{1, 2}, {2, 3}, {3, 4}, {5, 6}};\n\n int list4[][2] = {{3, 4}, {5, 6}};\n\n assert(func0(list3, 4, list4, 2) == true);\n\n\n\n int list5[][2] = {{1, 2}, {3, 4}, {5, 7}, {8, 9}};\n\n int list6[][2] = {{3, 4}, {5, 6}};\n\n assert(func0(list5, 4, list6, 2) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %ecx,%ecx\njle 1189 \nmov %rdx,%r8\nlea -0x1(%rcx),%eax\nlea 0x8(%rdx,%rax,8),%r10\nmov %rdi,%r9\nlea -0x1(%rsi),%eax\nlea 0x8(%rdi,%rax,8),%rcx\njmp 11af \nmov $0x1,%eax\nretq\nadd $0x8,%rax\ncmp %rcx,%rax\nje 11be \ncmp %edx,(%rax)\njne 118f \nmov 0x4(%rdi),%r11d\ncmp %r11d,0x4(%rax)\njne 118f \nadd $0x8,%r8\ncmp %r10,%r8\nje 11ca \ntest %esi,%esi\njle 11c4 \nmov %r8,%rdi\nmov (%r8),%edx\nmov %r9,%rax\njmp 1198 \nmov $0x0,%eax\nretq\nmov $0x0,%eax\nretq\nmov $0x1,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov r9, rdi\nmov r8d, esi\ntest ecx, ecx\njle short loc_11C5\nmov rdi, rdx\nmovsxd rcx, ecx\nlea r10, [rdx+rcx*8]\nmovsxd rax, esi\nlea rcx, [r9+rax*8]\njmp short loc_11AA\nloc_118A:\nadd rax, 8\ncmp rax, rcx\njz short loc_11B9\nloc_1193:\ncmp [rax], edx\njnz short loc_118A\nmov r11d, [rsi+4]\ncmp [rax+4], r11d\njnz short loc_118A\nadd rdi, 8\ncmp rdi, r10\njz short loc_11CB\nloc_11AA:\ntest r8d, r8d\njle short loc_11BF\nmov rsi, rdi\nmov edx, [rdi]\nmov rax, r9\njmp short loc_1193\nloc_11B9:\nmov eax, 0\nretn\nloc_11BF:\nmov eax, 0\nretn\nloc_11C5:\nmov eax, 1\nretn\nloc_11CB:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2, _DWORD *a3, int a4)\n{\n _DWORD *v5; // rdi\n _DWORD *v6; // rax\n\n if ( a4 <= 0 )\n return 1LL;\n v5 = a3;\n while ( 2 )\n {\n if ( a2 <= 0 )\n return 0LL;\n v6 = a1;\n while ( *v6 != *v5 || v6[1] != v5[1] )\n {\n v6 += 2;\n if ( v6 == &a1[2 * a2] )\n return 0LL;\n }\n v5 += 2;\n if ( v5 != &a3[2 * a4] )\n continue;\n break;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov r9, rdi\nmov r8d, esi\ntest ecx, ecx\njle short loc_11C5\nmov rdi, rdx\nmovsxd rcx, ecx\nlea r10, [rdx+rcx*8]\nmovsxd rax, esi\nlea rcx, [r9+rax*8]\njmp short loc_11AA\nloc_118A:\nadd rax, 8\ncmp rax, rcx\njz short loc_11B9\nloc_1193:\ncmp [rax], edx\njnz short loc_118A\nmov r11d, [rsi+4]\ncmp [rax+4], r11d\njnz short loc_118A\nadd rdi, 8\ncmp rdi, r10\njz short loc_11CB\nloc_11AA:\ntest r8d, r8d\njle short loc_11BF\nmov rsi, rdi\nmov edx, [rdi]\nmov rax, r9\njmp short loc_1193\nloc_11B9:\nmov eax, 0\nretn\nloc_11BF:\nmov eax, 0\nretn\nloc_11C5:\nmov eax, 1\nretn\nloc_11CB:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2, _DWORD *a3, int a4)\n{\n _DWORD *v5; // rdi\n _DWORD *v6; // rax\n\n if ( a4 <= 0 )\n return 1LL;\n v5 = a3;\n while ( 2 )\n {\n if ( a2 <= 0 )\n return 0LL;\n v6 = a1;\n while ( *v6 != *v5 || v6[1] != v5[1] )\n {\n v6 += 2;\n if ( v6 == &a1[2 * a2] )\n return 0LL;\n }\n v5 += 2;\n if ( v5 != &a3[2 * a4] )\n continue;\n break;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2, uint32_t *a3, int a4) {\n uint32_t *v5;\n uint32_t *v6;\n if (a4 <= 0) return 1LL;\n v5 = a3;\n while (2) {\n if (a2 <= 0) return 0LL;\n v6 = a1;\n while (*v6 != *v5 || v6[1] != v5[1]) {\n v6 += 2;\n if (v6 == &a1[2 * a2]) return 0LL;\n }\n v5 += 2;\n if (v5 != &a3[2 * a4]) continue;\n break;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2, uint32_t *a3, int a4) {\n uint32_t *v5;\n uint32_t *v6;\n if (a4 <= 0) return 1LL;\n v5 = a3;\n while (2) {\n if (a2 <= 0) return 0LL;\n v6 = a1;\n while (*v6 != *v5 || v6[1] != v5[1]) {\n v6 += 2;\n if (v6 == &a1[2 * a2]) return 0LL;\n }\n v5 += 2;\n if (v5 != &a3[2 * a4]) continue;\n break;\n }\n return 1LL;\n}" + }, + { + "index": 872, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int list1[][2], int size1, int list2[][2], int size2) {\n for (int i = 0; i < size2; i++) {\n bool found = false;\n for (int j = 0; j < size1; j++) {\n if (list1[j][0] == list2[i][0] && list1[j][1] == list2[i][1]) {\n found = true;\n break;\n }\n }\n if (!found) return false;\n }\n return true;\n}", + "test": "int main() {\n\n int list1[][2] = {{1, 3}, {5, 7}, {9, 11}, {13, 15}};\n\n int list2[][2] = {{1, 3}, {13, 15}};\n\n assert(func0(list1, 4, list2, 2) == true);\n\n\n\n int list3[][2] = {{1, 2}, {2, 3}, {3, 4}, {5, 6}};\n\n int list4[][2] = {{3, 4}, {5, 6}};\n\n assert(func0(list3, 4, list4, 2) == true);\n\n\n\n int list5[][2] = {{1, 2}, {3, 4}, {5, 7}, {8, 9}};\n\n int list6[][2] = {{3, 4}, {5, 6}};\n\n assert(func0(list5, 4, list6, 2) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %ecx,%ecx\njle 1420 \nlea -0x1(%rcx),%eax\nmov %rdx,%r8\nlea 0x8(%rdx,%rax,8),%r9\nlea -0x1(%rsi),%eax\nlea 0x8(%rdi,%rax,8),%rcx\nnopl 0x0(%rax,%rax,1)\ntest %esi,%esi\njle 1430 \nmov (%r8),%edx\nmov %rdi,%rax\njmp 1409 \nnopl 0x0(%rax)\nadd $0x8,%rax\ncmp %rcx,%rax\nje 1430 \ncmp %edx,(%rax)\njne 1400 \nmov 0x4(%r8),%r10d\ncmp %r10d,0x4(%rax)\njne 1400 \nadd $0x8,%r8\ncmp %r9,%r8\njne 13f0 \nmov $0x1,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxor %eax,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\nmov r8, rdi\ntest ecx, ecx\njle short loc_132E\nmovsxd rcx, ecx\nmovsxd rax, esi\nmov rdi, rdx\nlea r9, [rdx+rcx*8]\nlea rcx, [r8+rax*8]\ntest esi, esi\njle short loc_1338\nloc_1300:\nmov edx, [rdi]\nmov rax, r8\njmp short loc_1319\nloc_1310:\nadd rax, 8\ncmp rax, rcx\njz short loc_1338\nloc_1319:\ncmp [rax], edx\njnz short loc_1310\nmov esi, [rdi+4]\ncmp [rax+4], esi\njnz short loc_1310\nadd rdi, 8\ncmp rdi, r9\njnz short loc_1300\nloc_132E:\nmov eax, 1\nretn\nloc_1338:\nxor eax, eax\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2, _DWORD *a3, int a4)\n{\n _DWORD *v5; // rdi\n _DWORD *v6; // rax\n\n if ( a4 <= 0 )\n return 1LL;\n v5 = a3;\n if ( a2 > 0 )\n {\n do\n {\n v6 = a1;\n while ( *v6 != *v5 || v6[1] != v5[1] )\n {\n v6 += 2;\n if ( v6 == &a1[2 * a2] )\n return 0LL;\n }\n v5 += 2;\n }\n while ( v5 != &a3[2 * a4] );\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\nmov r8, rdi\ntest ecx, ecx\njle short loc_132E\nmovsxd rcx, ecx\nmovsxd rax, esi\nmov rdi, rdx\nlea r9, [rdx+rcx*8]\nlea rcx, [r8+rax*8]\ntest esi, esi\njle short loc_1338\nloc_1300:\nmov edx, [rdi]\nmov rax, r8\njmp short loc_1319\nloc_1310:\nadd rax, 8\ncmp rax, rcx\njz short loc_1338\nloc_1319:\ncmp [rax], edx\njnz short loc_1310\nmov esi, [rdi+4]\ncmp [rax+4], esi\njnz short loc_1310\nadd rdi, 8\ncmp rdi, r9\njnz short loc_1300\nloc_132E:\nmov eax, 1\nretn\nloc_1338:\nxor eax, eax\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12E0(_DWORD *a1, int a2, _DWORD *a3, int a4)\n{\n _DWORD *v5; // rdi\n _DWORD *v6; // rax\n\n if ( a4 <= 0 )\n return 1LL;\n v5 = a3;\n if ( a2 > 0 )\n {\n do\n {\n v6 = a1;\n while ( *v6 != *v5 || v6[1] != v5[1] )\n {\n v6 += 2;\n if ( v6 == &a1[2 * a2] )\n return 0LL;\n }\n v5 += 2;\n }\n while ( v5 != &a3[2 * a4] );\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12E0(uint32_t *a1, int a2, uint32_t *a3, int a4) {\n uint32_t *v5;\n uint32_t *v6;\n if (a4 <= 0) return 1LL;\n v5 = a3;\n if (a2 > 0) {\n do {\n v6 = a1;\n while (*v6 != *v5 || v6[1] != v5[1]) {\n v6 += 2;\n if (v6 == &a1[2 * a2]) return 0LL;\n }\n v5 += 2;\n } while (v5 != &a3[2 * a4]);\n return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2, uint32_t *a3, int a4) {\n uint32_t *v5;\n uint32_t *v6;\n if (a4 <= 0) return 1LL;\n v5 = a3;\n if (a2 > 0) {\n do {\n v6 = a1;\n while (*v6 != *v5 || v6[1] != v5[1]) {\n v6 += 2;\n if (v6 == &a1[2 * a2]) return 0LL;\n }\n v5 += 2;\n } while (v5 != &a3[2 * a4]);\n return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 873, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n == 1 || n == 2) {\n return 1;\n } else {\n return (func0(n - 1) + func0(n - 2));\n }\n}", + "test": "int main() {\n\n assert(func0(7) == 13);\n\n assert(func0(8) == 21);\n\n assert(func0(9) == 34);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x18,%rsp\nmov %edi,-0x14(%rbp)\ncmpl $0x1,-0x14(%rbp)\nje 1165 \ncmpl $0x2,-0x14(%rbp)\njne 116c \nmov $0x1,%eax\njmp 118a \nmov -0x14(%rbp),%eax\nsub $0x1,%eax\nmov %eax,%edi\ncallq 1149 \nmov %eax,%ebx\nmov -0x14(%rbp),%eax\nsub $0x2,%eax\nmov %eax,%edi\ncallq 1149 \nadd %ebx,%eax\nadd $0x18,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 18h\nmov [rbp+var_14], edi\ncmp [rbp+var_14], 1\njz short loc_1165\ncmp [rbp+var_14], 2\njnz short loc_116C\nloc_1165:\nmov eax, 1\njmp short loc_118A\nloc_116C:\nmov eax, [rbp+var_14]\nsub eax, 1\nmov edi, eax\ncall func0\nmov ebx, eax\nmov eax, [rbp+var_14]\nsub eax, 2\nmov edi, eax\ncall func0\nadd eax, ebx\nloc_118A:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v2; // ebx\n\n if ( a1 == 1 || a1 == 2 )\n return 1LL;\n v2 = func0((unsigned int)(a1 - 1));\n return v2 + (unsigned int)func0((unsigned int)(a1 - 2));\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 18h\nmov [rbp+var_14], edi\ncmp [rbp+var_14], 1\njz short loc_1165\ncmp [rbp+var_14], 2\njnz short loc_116C\nloc_1165:\nmov eax, 1\njmp short loc_118A\nloc_116C:\nmov eax, [rbp+var_14]\nsub eax, 1\nmov edi, eax\ncall sub_1149\nmov ebx, eax\nmov eax, [rbp+var_14]\nsub eax, 2\nmov edi, eax\ncall sub_1149\nadd eax, ebx\nloc_118A:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v2; // ebx\n\n if ( a1 == 1 || a1 == 2 )\n return 1LL;\n v2 = sub_1149((unsigned int)(a1 - 1));\n return v2 + (unsigned int)sub_1149((unsigned int)(a1 - 2));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v2;\n if (a1 == 1 || a1 == 2) return 1LL;\n v2 = sub_1149((unsigned int)(a1 - 1));\n return v2 + (unsigned int)sub_1149((unsigned int)(a1 - 2));\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v2;\n if (a1 == 1 || a1 == 2) return 1LL;\n v2 = func0((unsigned int)(a1 - 1));\n return v2 + (unsigned int)func0((unsigned int)(a1 - 2));\n}" + }, + { + "index": 873, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n == 1 || n == 2) {\n return 1;\n } else {\n return (func0(n - 1) + func0(n - 2));\n }\n}", + "test": "int main() {\n\n assert(func0(7) == 13);\n\n assert(func0(8) == 21);\n\n assert(func0(9) == 34);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nlea -0x1(%rdi),%edx\nmov $0x1,%eax\ncmp $0x1,%edx\nja 115b \nretq\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %edi,%ebx\nmov %edx,%edi\ncallq 1149 \nmov %eax,%ebp\nlea -0x2(%rbx),%edi\ncallq 1149 \nadd %ebp,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\nlea edx, [rdi-1]\nmov eax, 1\ncmp edx, 1\nja short loc_115B\nretn\nloc_115B:\npush rbp\npush rbx\nsub rsp, 8\nmov ebx, edi\nmov edi, edx\ncall func0\nmov ebp, eax\nlea edi, [rbx-2]\ncall func0\nadd eax, ebp\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n __int64 result; // rax\n int v2; // ebp\n\n result = 1LL;\n if ( (unsigned int)(a1 - 1) > 1 )\n {\n v2 = func0((unsigned int)(a1 - 1));\n return v2 + (unsigned int)func0((unsigned int)(a1 - 2));\n }\n return result;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nlea edx, [rdi-1]\nmov eax, 1\ncmp edx, 1\nja short loc_115B\nretn\nloc_115B:\npush rbp\npush rbx\nsub rsp, 8\nmov ebx, edi\nmov edi, edx\ncall sub_1149\nmov ebp, eax\nlea edi, [rbx-2]\ncall sub_1149\nadd eax, ebp\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n __int64 result; // rax\n int v2; // ebp\n\n result = 1LL;\n if ( (unsigned int)(a1 - 1) > 1 )\n {\n v2 = sub_1149((unsigned int)(a1 - 1));\n return v2 + (unsigned int)sub_1149((unsigned int)(a1 - 2));\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n long long result;\n int v2;\n result = 1LL;\n if ((unsigned int)(a1 - 1) > 1) {\n v2 = sub_1149((unsigned int)(a1 - 1));\n return v2 + (unsigned int)sub_1149((unsigned int)(a1 - 2));\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n long long result;\n int v2;\n result = 1LL;\n if ((unsigned int)(a1 - 1) > 1) {\n v2 = func0((unsigned int)(a1 - 1));\n return v2 + (unsigned int)func0((unsigned int)(a1 - 2));\n }\n return result;\n}" + }, + { + "index": 873, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n == 1 || n == 2) {\n return 1;\n } else {\n return (func0(n - 1) + func0(n - 2));\n }\n}", + "test": "int main() {\n\n assert(func0(7) == 13);\n\n assert(func0(8) == 21);\n\n assert(func0(9) == 34);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov $0x1,%eax\npush %rbx\nlea -0x1(%rdi),%ebx\nsub $0x8,%rsp\ncmp $0x1,%ebx\njbe 127d \nxor %ebp,%ebp\nmov %ebx,%edi\nsub $0x2,%ebx\ncallq 1250 \nadd %eax,%ebp\ncmp $0x1,%ebx\nja 1269 \nlea 0x1(%rbp),%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r15\nlea edx, [rdi-1]\npush r14\npush r13\nmov r13d, 1\npush r12\npush rbp\npush rbx\nsub rsp, 58h\ncmp edx, 1\njbe loc_14EC\nlea r15d, [rdi-2]\nxor r13d, r13d\nloc_121B:\ncmp r15d, 1\njz loc_14E8\nlea ebp, [r15-1]\nmov [rsp+88h+var_70], r13d\nxor r14d, r14d\nmov [rsp+88h+var_6C], ebp\nmov [rsp+88h+var_68], r15d\nloc_123A:\ncmp ebp, 1\njz loc_14FE\nlea ecx, [rbp-1]\nxor r13d, r13d\nmov r15d, ecx\nloc_124C:\ncmp r15d, 1\njz loc_14CE\nmov [rsp+88h+var_64], r14d\nlea edi, [r15-1]\nxor r12d, r12d\nmov esi, ecx\nmov [rsp+88h+var_60], r13d\nmov ebx, edi\nloc_126B:\ncmp ebx, 1\njz loc_148C\nmov [rsp+88h+var_5C], r12d\nlea r10d, [rbx-1]\nmov r11d, esi\nxor r14d, r14d\nmov [rsp+88h+var_58], ebx\nmov r13d, r10d\nmov esi, ebp\nmov r9d, edi\nmov ecx, r15d\nloc_1292:\ncmp r13d, 1\njz loc_146F\nlea r15d, [r13-1]\nxor ebp, ebp\nmov ebx, r15d\nloc_12A5:\ncmp ebx, 1\njz loc_13B6\nlea eax, [rbx-1]\nlea edx, [rbx-2]\nmov r8d, ebx\nxor r12d, r12d\nmov edi, eax\nmov [rsp+88h+var_88], edx\nand edi, 0FFFFFFFEh\nsub r8d, edi\nmov edi, edx\nmov [rsp+88h+var_74], r8d\nmov r8d, eax\nloc_12CF:\ncmp [rsp+88h+var_74], ebx\njz loc_1450\nmov [rsp+88h+var_84], r11d\nmov r11d, ebx\nmov ebx, edi\nxor edx, edx\nmov [rsp+88h+var_80], esi\nmov esi, r15d\nmov r15d, r12d\nmov [rsp+88h+var_7C], r9d\nmov r9d, r13d\nmov r13d, ebp\nmov [rsp+88h+var_78], edi\ncmp ebx, 1\njbe short loc_1373\nloc_1303:\nmov r12d, ebx\nxor ebp, ebp\nloc_1308:\nmov edi, r12d\nmov [rsp+88h+var_3C], r11d\nsub r12d, 2\nmov [rsp+88h+var_40], r8d\nmov [rsp+88h+var_44], r9d\nmov [rsp+88h+var_48], esi\nmov [rsp+88h+var_4C], r10d\nmov [rsp+88h+var_50], ecx\nmov [rsp+88h+var_54], edx\ncall func0\nmov edx, [rsp+88h+var_54]\nmov ecx, [rsp+88h+var_50]\nadd ebp, eax\ncmp r12d, 1\nmov r10d, [rsp+88h+var_4C]\nmov esi, [rsp+88h+var_48]\nmov r9d, [rsp+88h+var_44]\nmov r8d, [rsp+88h+var_40]\nmov r11d, [rsp+88h+var_3C]\nja short loc_1308\nlea edx, [rdx+rbp+1]\nlea edi, [rbx-2]\ncmp ebx, 2\njz loc_14A8\nmov ebx, edi\ncmp ebx, 1\nja short loc_1303\nloc_1373:\nmov ebp, r13d\nmov r12d, r15d\nmov r13d, r9d\nmov r15d, esi\nmov ebx, r11d\nmov esi, [rsp+88h+var_80]\nmov r9d, [rsp+88h+var_7C]\nadd edx, 1\nmov r11d, [rsp+88h+var_84]\nmov edi, [rsp+88h+var_78]\nloc_1397:\nsub ebx, 2\nlea r12d, [r12+rdx+1]\nsub edi, 2\ncmp ebx, 1\nja loc_12CF\nmov edx, [rsp+88h+var_88]\nmov eax, r8d\njmp loc_145A\nloc_13B6:\nadd ebp, 1\nloc_13B9:\nlea r14d, [r14+rbp+1]\nsub r13d, 2\ncmp r15d, 1\njnz loc_1292\nmov r12d, [rsp+88h+var_5C]\nmov ebx, [rsp+88h+var_58]\nmov ebp, esi\nmov edi, r9d\nmov esi, r11d\nmov r15d, ecx\nloc_13E0:\nlea r12d, [r12+r14+1]\nsub ebx, 2\ncmp r10d, 1\njnz loc_126B\nmov r14d, [rsp+88h+var_64]\nmov r13d, [rsp+88h+var_60]\nmov ecx, esi\nloc_13FE:\nlea r13d, [r13+r12+1]\nsub r15d, 2\ncmp edi, 1\njnz loc_124C\nlea r14d, [r14+r13+1]\nsub ebp, 2\ncmp ecx, 1\njnz loc_123A\nloc_1421:\nmov r13d, [rsp+88h+var_70]\nmov r15d, [rsp+88h+var_68]\nmov ebp, [rsp+88h+var_6C]\nlea r13d, [r13+r14+1]\nsub r15d, 2\ncmp ebp, 1\njnz loc_121B\nadd r13d, 1\njmp loc_14EC\nloc_1450:\nmov edx, [rsp+88h+var_88]\nmov eax, r8d\nadd r12d, 1\nloc_145A:\nlea ebp, [rbp+r12+1]\ncmp eax, 1\njz loc_13B9\nmov ebx, edx\njmp loc_12A5\nloc_146F:\nmov ebp, esi\nmov r12d, [rsp+88h+var_5C]\nmov ebx, [rsp+88h+var_58]\nmov esi, r11d\nmov edi, r9d\nmov r15d, ecx\nadd r14d, 1\njmp loc_13E0\nloc_148C:\nmov r14d, [rsp+88h+var_64]\nmov r13d, [rsp+88h+var_60]\nmov ecx, esi\nadd r12d, 1\njmp loc_13FE\nloc_14A8:\nmov ebp, r13d\nmov r12d, r15d\nmov r13d, r9d\nmov r15d, esi\nmov ebx, r11d\nmov esi, [rsp+88h+var_80]\nmov r9d, [rsp+88h+var_7C]\nmov r11d, [rsp+88h+var_84]\nmov edi, [rsp+88h+var_78]\njmp loc_1397\nloc_14CE:\nadd r13d, 1\nsub ebp, 2\nlea r14d, [r14+r13+1]\ncmp ecx, 1\njnz loc_123A\njmp loc_1421\nloc_14E8:\nadd r13d, 2\nloc_14EC:\nadd rsp, 58h\nmov eax, r13d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14FE:\nmov r13d, [rsp+88h+var_70]\nmov r15d, [rsp+88h+var_68]\nadd r14d, 1\nmov ebp, [rsp+88h+var_6C]\nlea r13d, [r13+r14+1]\nsub r15d, 2\ncmp ebp, 1\njnz loc_121B\nadd r13d, 1\njmp short loc_14EC", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v1; // r13d\n int v2; // r15d\n int v3; // r13d\n int v4; // ebp\n int v5; // r14d\n int v6; // ecx\n int v7; // r13d\n int v8; // r15d\n int v9; // edi\n int v10; // r12d\n int v11; // esi\n int v12; // ebx\n int v13; // r10d\n int v14; // r11d\n int v15; // r14d\n int v16; // r13d\n int v17; // esi\n int v18; // r9d\n int v19; // ecx\n int v20; // r15d\n int v21; // ebp\n unsigned int i; // ebx\n int v23; // r12d\n unsigned int v24; // edi\n unsigned int v25; // r8d\n unsigned int v26; // r11d\n unsigned int v27; // ebx\n int v28; // edx\n int v29; // esi\n int v30; // r15d\n int v31; // r9d\n int v32; // r13d\n unsigned int v33; // r12d\n int v34; // ebp\n __int64 v35; // rdi\n int v36; // eax\n unsigned int v37; // edi\n int v38; // r12d\n unsigned int v39; // ebx\n unsigned int v40; // edi\n unsigned int v41; // edx\n unsigned int v42; // eax\n int v43; // r12d\n int v44; // ebx\n int v45; // r13d\n unsigned int v47; // [rsp+0h] [rbp-88h]\n int v48; // [rsp+4h] [rbp-84h]\n int v49; // [rsp+8h] [rbp-80h]\n int v50; // [rsp+Ch] [rbp-7Ch]\n unsigned int v51; // [rsp+10h] [rbp-78h]\n unsigned int v52; // [rsp+14h] [rbp-74h]\n int v53; // [rsp+18h] [rbp-70h]\n int v54; // [rsp+1Ch] [rbp-6Ch]\n int v55; // [rsp+20h] [rbp-68h]\n int v56; // [rsp+24h] [rbp-64h]\n int v57; // [rsp+28h] [rbp-60h]\n int v58; // [rsp+2Ch] [rbp-5Ch]\n int v59; // [rsp+30h] [rbp-58h]\n int v60; // [rsp+34h] [rbp-54h]\n int v61; // [rsp+38h] [rbp-50h]\n int v62; // [rsp+3Ch] [rbp-4Ch]\n int v63; // [rsp+44h] [rbp-44h]\n unsigned int v64; // [rsp+48h] [rbp-40h]\n unsigned int v65; // [rsp+4Ch] [rbp-3Ch]\n\n v1 = 1;\n if ( (unsigned int)(a1 - 1) > 1 )\n {\n v2 = a1 - 2;\n v3 = 0;\n while ( 1 )\n {\nLABEL_3:\n if ( v2 == 1 )\n return (unsigned int)(v3 + 2);\n v4 = v2 - 1;\n v53 = v3;\n v5 = 0;\n v54 = v2 - 1;\n v55 = v2;\nLABEL_5:\n if ( v4 != 1 )\n break;\n v3 = v53 + v5 + 1 + 1;\n v2 = v55 - 2;\n if ( v54 == 1 )\n return (unsigned int)(v53 + v5 + 1 + 2);\n }\n v6 = v4 - 1;\n v7 = 0;\n v8 = v4 - 1;\n while ( v8 != 1 )\n {\n v56 = v5;\n v9 = v8 - 1;\n v10 = 0;\n v11 = v6;\n v57 = v7;\n v12 = v8 - 1;\n while ( v12 != 1 )\n {\n v58 = v10;\n v13 = v12 - 1;\n v14 = v11;\n v15 = 0;\n v59 = v12;\n v16 = v12 - 1;\n v17 = v4;\n v18 = v9;\n v19 = v8;\n while ( v16 != 1 )\n {\n v20 = v16 - 1;\n v21 = 0;\n for ( i = v16 - 1; i != 1; i = v41 )\n {\n v23 = 0;\n v47 = i - 2;\n v24 = i - 2;\n v52 = i - ((i - 1) & 0xFFFFFFFE);\n v25 = i - 1;\n while ( v52 != i )\n {\n v48 = v14;\n v26 = i;\n v27 = v24;\n v28 = 0;\n v49 = v17;\n v29 = v20;\n v30 = v23;\n v50 = v18;\n v31 = v16;\n v32 = v21;\n v51 = v24;\n if ( v24 <= 1 )\n {\nLABEL_21:\n v21 = v32;\n v38 = v30;\n v16 = v31;\n v20 = v29;\n v39 = v26;\n v17 = v49;\n v18 = v50;\n ++v28;\n v14 = v48;\n v40 = v51;\n }\n else\n {\n while ( 1 )\n {\n v33 = v27;\n v34 = 0;\n do\n {\n v35 = v33;\n v65 = v26;\n v33 -= 2;\n v64 = v25;\n v63 = v31;\n v62 = v13;\n v61 = v19;\n v60 = v28;\n v36 = func0(v35);\n v28 = v60;\n v19 = v61;\n v34 += v36;\n v13 = v62;\n v31 = v63;\n v25 = v64;\n v26 = v65;\n }\n while ( v33 > 1 );\n v28 = v60 + v34 + 1;\n v37 = v27 - 2;\n if ( v27 == 2 )\n break;\n v27 -= 2;\n if ( v37 <= 1 )\n goto LABEL_21;\n }\n v21 = v32;\n v38 = v30;\n v16 = v63;\n v20 = v29;\n v39 = v65;\n v17 = v49;\n v18 = v50;\n v14 = v48;\n v40 = v51;\n }\n i = v39 - 2;\n v23 = v38 + v28 + 1;\n v24 = v40 - 2;\n if ( i <= 1 )\n {\n v41 = v47;\n v42 = v25;\n goto LABEL_34;\n }\n }\n v41 = v47;\n v42 = v25;\n ++v23;\nLABEL_34:\n v21 += v23 + 1;\n if ( v42 == 1 )\n goto LABEL_25;\n }\n ++v21;\nLABEL_25:\n v15 += v21 + 1;\n v16 -= 2;\n if ( v20 == 1 )\n {\n v43 = v58;\n v44 = v59;\n v4 = v17;\n v9 = v18;\n v11 = v14;\n v8 = v19;\n goto LABEL_27;\n }\n }\n v4 = v17;\n v43 = v58;\n v44 = v59;\n v11 = v14;\n v9 = v18;\n v8 = v19;\n ++v15;\nLABEL_27:\n v10 = v43 + v15 + 1;\n v12 = v44 - 2;\n if ( v13 == 1 )\n {\n v5 = v56;\n v45 = v57;\n v6 = v11;\n goto LABEL_29;\n }\n }\n v5 = v56;\n v45 = v57;\n v6 = v11;\n ++v10;\nLABEL_29:\n v7 = v45 + v10 + 1;\n v8 -= 2;\n if ( v9 == 1 )\n {\n v5 += v7 + 1;\n v4 -= 2;\n if ( v6 != 1 )\n goto LABEL_5;\n goto LABEL_31;\n }\n }\n v4 -= 2;\n v5 += v7 + 1 + 1;\n if ( v6 != 1 )\n goto LABEL_5;\nLABEL_31:\n v3 = v53 + v5 + 1;\n v2 = v55 - 2;\n if ( v54 != 1 )\n goto LABEL_3;\n return (unsigned int)(v53 + v5 + 2);\n }\n return v1;\n}", + "ida_strip_asm": "sub_11F0:\nendbr64\npush r15\nlea edx, [rdi-1]\npush r14\npush r13\nmov r13d, 1\npush r12\npush rbp\npush rbx\nsub rsp, 58h\ncmp edx, 1\njbe loc_14EC\nlea r15d, [rdi-2]\nxor r13d, r13d\nloc_121B:\ncmp r15d, 1\njz loc_14E8\nlea ebp, [r15-1]\nmov [rsp+88h+var_70], r13d\nxor r14d, r14d\nmov [rsp+88h+var_6C], ebp\nmov [rsp+88h+var_68], r15d\nloc_123A:\ncmp ebp, 1\njz loc_14FE\nlea ecx, [rbp-1]\nxor r13d, r13d\nmov r15d, ecx\nloc_124C:\ncmp r15d, 1\njz loc_14CE\nmov [rsp+88h+var_64], r14d\nlea edi, [r15-1]\nxor r12d, r12d\nmov esi, ecx\nmov [rsp+88h+var_60], r13d\nmov ebx, edi\nloc_126B:\ncmp ebx, 1\njz loc_148C\nmov [rsp+88h+var_5C], r12d\nlea r10d, [rbx-1]\nmov r11d, esi\nxor r14d, r14d\nmov [rsp+88h+var_58], ebx\nmov r13d, r10d\nmov esi, ebp\nmov r9d, edi\nmov ecx, r15d\nloc_1292:\ncmp r13d, 1\njz loc_146F\nlea r15d, [r13-1]\nxor ebp, ebp\nmov ebx, r15d\nloc_12A5:\ncmp ebx, 1\njz loc_13B6\nlea eax, [rbx-1]\nlea edx, [rbx-2]\nmov r8d, ebx\nxor r12d, r12d\nmov edi, eax\nmov [rsp+88h+var_88], edx\nand edi, 0FFFFFFFEh\nsub r8d, edi\nmov edi, edx\nmov [rsp+88h+var_74], r8d\nmov r8d, eax\nloc_12CF:\ncmp [rsp+88h+var_74], ebx\njz loc_1450\nmov [rsp+88h+var_84], r11d\nmov r11d, ebx\nmov ebx, edi\nxor edx, edx\nmov [rsp+88h+var_80], esi\nmov esi, r15d\nmov r15d, r12d\nmov [rsp+88h+var_7C], r9d\nmov r9d, r13d\nmov r13d, ebp\nmov [rsp+88h+var_78], edi\ncmp ebx, 1\njbe short loc_1373\nloc_1303:\nmov r12d, ebx\nxor ebp, ebp\nloc_1308:\nmov edi, r12d\nmov [rsp+88h+var_3C], r11d\nsub r12d, 2\nmov [rsp+88h+var_40], r8d\nmov [rsp+88h+var_44], r9d\nmov [rsp+88h+var_48], esi\nmov [rsp+88h+var_4C], r10d\nmov [rsp+88h+var_50], ecx\nmov [rsp+88h+var_54], edx\ncall sub_11F0\nmov edx, [rsp+88h+var_54]\nmov ecx, [rsp+88h+var_50]\nadd ebp, eax\ncmp r12d, 1\nmov r10d, [rsp+88h+var_4C]\nmov esi, [rsp+88h+var_48]\nmov r9d, [rsp+88h+var_44]\nmov r8d, [rsp+88h+var_40]\nmov r11d, [rsp+88h+var_3C]\nja short loc_1308\nlea edx, [rdx+rbp+1]\nlea edi, [rbx-2]\ncmp ebx, 2\njz loc_14A8\nmov ebx, edi\ncmp ebx, 1\nja short loc_1303\nloc_1373:\nmov ebp, r13d\nmov r12d, r15d\nmov r13d, r9d\nmov r15d, esi\nmov ebx, r11d\nmov esi, [rsp+88h+var_80]\nmov r9d, [rsp+88h+var_7C]\nadd edx, 1\nmov r11d, [rsp+88h+var_84]\nmov edi, [rsp+88h+var_78]\nloc_1397:\nsub ebx, 2\nlea r12d, [r12+rdx+1]\nsub edi, 2\ncmp ebx, 1\nja loc_12CF\nmov edx, [rsp+88h+var_88]\nmov eax, r8d\njmp loc_145A\nloc_13B6:\nadd ebp, 1\nloc_13B9:\nlea r14d, [r14+rbp+1]\nsub r13d, 2\ncmp r15d, 1\njnz loc_1292\nmov r12d, [rsp+88h+var_5C]\nmov ebx, [rsp+88h+var_58]\nmov ebp, esi\nmov edi, r9d\nmov esi, r11d\nmov r15d, ecx\nloc_13E0:\nlea r12d, [r12+r14+1]\nsub ebx, 2\ncmp r10d, 1\njnz loc_126B\nmov r14d, [rsp+88h+var_64]\nmov r13d, [rsp+88h+var_60]\nmov ecx, esi\nloc_13FE:\nlea r13d, [r13+r12+1]\nsub r15d, 2\ncmp edi, 1\njnz loc_124C\nlea r14d, [r14+r13+1]\nsub ebp, 2\ncmp ecx, 1\njnz loc_123A\nloc_1421:\nmov r13d, [rsp+88h+var_70]\nmov r15d, [rsp+88h+var_68]\nmov ebp, [rsp+88h+var_6C]\nlea r13d, [r13+r14+1]\nsub r15d, 2\ncmp ebp, 1\njnz loc_121B\nadd r13d, 1\njmp loc_14EC\nloc_1450:\nmov edx, [rsp+88h+var_88]\nmov eax, r8d\nadd r12d, 1\nloc_145A:\nlea ebp, [rbp+r12+1]\ncmp eax, 1\njz loc_13B9\nmov ebx, edx\njmp loc_12A5\nloc_146F:\nmov ebp, esi\nmov r12d, [rsp+88h+var_5C]\nmov ebx, [rsp+88h+var_58]\nmov esi, r11d\nmov edi, r9d\nmov r15d, ecx\nadd r14d, 1\njmp loc_13E0\nloc_148C:\nmov r14d, [rsp+88h+var_64]\nmov r13d, [rsp+88h+var_60]\nmov ecx, esi\nadd r12d, 1\njmp loc_13FE\nloc_14A8:\nmov ebp, r13d\nmov r12d, r15d\nmov r13d, r9d\nmov r15d, esi\nmov ebx, r11d\nmov esi, [rsp+88h+var_80]\nmov r9d, [rsp+88h+var_7C]\nmov r11d, [rsp+88h+var_84]\nmov edi, [rsp+88h+var_78]\njmp loc_1397\nloc_14CE:\nadd r13d, 1\nsub ebp, 2\nlea r14d, [r14+r13+1]\ncmp ecx, 1\njnz loc_123A\njmp loc_1421\nloc_14E8:\nadd r13d, 2\nloc_14EC:\nadd rsp, 58h\nmov eax, r13d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14FE:\nmov r13d, [rsp+88h+var_70]\nmov r15d, [rsp+88h+var_68]\nadd r14d, 1\nmov ebp, [rsp+88h+var_6C]\nlea r13d, [r13+r14+1]\nsub r15d, 2\ncmp ebp, 1\njnz loc_121B\nadd r13d, 1\njmp short loc_14EC", + "ida_strip_pseudo": "__int64 __fastcall sub_11F0(int a1)\n{\n unsigned int v1; // r13d\n int v2; // r15d\n int v3; // r13d\n int v4; // ebp\n int v5; // r14d\n int v6; // ecx\n int v7; // r13d\n int v8; // r15d\n int v9; // edi\n int v10; // r12d\n int v11; // esi\n int v12; // ebx\n int v13; // r10d\n int v14; // r11d\n int v15; // r14d\n int v16; // r13d\n int v17; // esi\n int v18; // r9d\n int v19; // ecx\n int v20; // r15d\n int v21; // ebp\n unsigned int i; // ebx\n int v23; // r12d\n unsigned int v24; // edi\n unsigned int v25; // r8d\n unsigned int v26; // r11d\n unsigned int v27; // ebx\n int v28; // edx\n int v29; // esi\n int v30; // r15d\n int v31; // r9d\n int v32; // r13d\n unsigned int v33; // r12d\n int v34; // ebp\n __int64 v35; // rdi\n int v36; // eax\n unsigned int v37; // edi\n int v38; // r12d\n unsigned int v39; // ebx\n unsigned int v40; // edi\n unsigned int v41; // edx\n unsigned int v42; // eax\n int v43; // r12d\n int v44; // ebx\n int v45; // r13d\n unsigned int v47; // [rsp+0h] [rbp-88h]\n int v48; // [rsp+4h] [rbp-84h]\n int v49; // [rsp+8h] [rbp-80h]\n int v50; // [rsp+Ch] [rbp-7Ch]\n unsigned int v51; // [rsp+10h] [rbp-78h]\n unsigned int v52; // [rsp+14h] [rbp-74h]\n int v53; // [rsp+18h] [rbp-70h]\n int v54; // [rsp+1Ch] [rbp-6Ch]\n int v55; // [rsp+20h] [rbp-68h]\n int v56; // [rsp+24h] [rbp-64h]\n int v57; // [rsp+28h] [rbp-60h]\n int v58; // [rsp+2Ch] [rbp-5Ch]\n int v59; // [rsp+30h] [rbp-58h]\n int v60; // [rsp+34h] [rbp-54h]\n int v61; // [rsp+38h] [rbp-50h]\n int v62; // [rsp+3Ch] [rbp-4Ch]\n int v63; // [rsp+44h] [rbp-44h]\n unsigned int v64; // [rsp+48h] [rbp-40h]\n unsigned int v65; // [rsp+4Ch] [rbp-3Ch]\n\n v1 = 1;\n if ( (unsigned int)(a1 - 1) > 1 )\n {\n v2 = a1 - 2;\n v3 = 0;\n while ( 1 )\n {\nLABEL_3:\n if ( v2 == 1 )\n return (unsigned int)(v3 + 2);\n v4 = v2 - 1;\n v53 = v3;\n v5 = 0;\n v54 = v2 - 1;\n v55 = v2;\nLABEL_5:\n if ( v4 != 1 )\n break;\n v3 = v53 + v5 + 1 + 1;\n v2 = v55 - 2;\n if ( v54 == 1 )\n return (unsigned int)(v53 + v5 + 1 + 2);\n }\n v6 = v4 - 1;\n v7 = 0;\n v8 = v4 - 1;\n while ( v8 != 1 )\n {\n v56 = v5;\n v9 = v8 - 1;\n v10 = 0;\n v11 = v6;\n v57 = v7;\n v12 = v8 - 1;\n while ( v12 != 1 )\n {\n v58 = v10;\n v13 = v12 - 1;\n v14 = v11;\n v15 = 0;\n v59 = v12;\n v16 = v12 - 1;\n v17 = v4;\n v18 = v9;\n v19 = v8;\n while ( v16 != 1 )\n {\n v20 = v16 - 1;\n v21 = 0;\n for ( i = v16 - 1; i != 1; i = v41 )\n {\n v23 = 0;\n v47 = i - 2;\n v24 = i - 2;\n v52 = i - ((i - 1) & 0xFFFFFFFE);\n v25 = i - 1;\n while ( v52 != i )\n {\n v48 = v14;\n v26 = i;\n v27 = v24;\n v28 = 0;\n v49 = v17;\n v29 = v20;\n v30 = v23;\n v50 = v18;\n v31 = v16;\n v32 = v21;\n v51 = v24;\n if ( v24 <= 1 )\n {\nLABEL_21:\n v21 = v32;\n v38 = v30;\n v16 = v31;\n v20 = v29;\n v39 = v26;\n v17 = v49;\n v18 = v50;\n ++v28;\n v14 = v48;\n v40 = v51;\n }\n else\n {\n while ( 1 )\n {\n v33 = v27;\n v34 = 0;\n do\n {\n v35 = v33;\n v65 = v26;\n v33 -= 2;\n v64 = v25;\n v63 = v31;\n v62 = v13;\n v61 = v19;\n v60 = v28;\n v36 = sub_11F0(v35);\n v28 = v60;\n v19 = v61;\n v34 += v36;\n v13 = v62;\n v31 = v63;\n v25 = v64;\n v26 = v65;\n }\n while ( v33 > 1 );\n v28 = v60 + v34 + 1;\n v37 = v27 - 2;\n if ( v27 == 2 )\n break;\n v27 -= 2;\n if ( v37 <= 1 )\n goto LABEL_21;\n }\n v21 = v32;\n v38 = v30;\n v16 = v63;\n v20 = v29;\n v39 = v65;\n v17 = v49;\n v18 = v50;\n v14 = v48;\n v40 = v51;\n }\n i = v39 - 2;\n v23 = v38 + v28 + 1;\n v24 = v40 - 2;\n if ( i <= 1 )\n {\n v41 = v47;\n v42 = v25;\n goto LABEL_34;\n }\n }\n v41 = v47;\n v42 = v25;\n ++v23;\nLABEL_34:\n v21 += v23 + 1;\n if ( v42 == 1 )\n goto LABEL_25;\n }\n ++v21;\nLABEL_25:\n v15 += v21 + 1;\n v16 -= 2;\n if ( v20 == 1 )\n {\n v43 = v58;\n v44 = v59;\n v4 = v17;\n v9 = v18;\n v11 = v14;\n v8 = v19;\n goto LABEL_27;\n }\n }\n v4 = v17;\n v43 = v58;\n v44 = v59;\n v11 = v14;\n v9 = v18;\n v8 = v19;\n ++v15;\nLABEL_27:\n v10 = v43 + v15 + 1;\n v12 = v44 - 2;\n if ( v13 == 1 )\n {\n v5 = v56;\n v45 = v57;\n v6 = v11;\n goto LABEL_29;\n }\n }\n v5 = v56;\n v45 = v57;\n v6 = v11;\n ++v10;\nLABEL_29:\n v7 = v45 + v10 + 1;\n v8 -= 2;\n if ( v9 == 1 )\n {\n v5 += v7 + 1;\n v4 -= 2;\n if ( v6 != 1 )\n goto LABEL_5;\n goto LABEL_31;\n }\n }\n v4 -= 2;\n v5 += v7 + 1 + 1;\n if ( v6 != 1 )\n goto LABEL_5;\nLABEL_31:\n v3 = v53 + v5 + 1;\n v2 = v55 - 2;\n if ( v54 != 1 )\n goto LABEL_3;\n return (unsigned int)(v53 + v5 + 2);\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11F0(int a1) {\n unsigned int v1;\n int v2;\n int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n int v8;\n int v9;\n int v10;\n int v11;\n int v12;\n int v13;\n int v14;\n int v15;\n int v16;\n int v17;\n int v18;\n int v19;\n int v20;\n int v21;\n unsigned int i;\n int v23;\n unsigned int v24;\n unsigned int v25;\n unsigned int v26;\n unsigned int v27;\n int v28;\n int v29;\n int v30;\n int v31;\n int v32;\n unsigned int v33;\n int v34;\n long long v35;\n int v36;\n unsigned int v37;\n int v38;\n unsigned int v39;\n unsigned int v40;\n unsigned int v41;\n unsigned int v42;\n int v43;\n int v44;\n int v45;\n unsigned int v47;\n int v48;\n int v49;\n int v50;\n unsigned int v51;\n unsigned int v52;\n int v53;\n int v54;\n int v55;\n int v56;\n int v57;\n int v58;\n int v59;\n int v60;\n int v61;\n int v62;\n int v63;\n unsigned int v64;\n unsigned int v65;\n v1 = 1;\n if ((unsigned int)(a1 - 1) > 1) {\n v2 = a1 - 2;\n v3 = 0;\n while (1) {\n LABEL_3:\n if (v2 == 1) return (unsigned int)(v3 + 2);\n v4 = v2 - 1;\n v53 = v3;\n v5 = 0;\n v54 = v2 - 1;\n v55 = v2;\n LABEL_5:\n if (v4 != 1) break;\n v3 = v53 + v5 + 1 + 1;\n v2 = v55 - 2;\n if (v54 == 1) return (unsigned int)(v53 + v5 + 1 + 2);\n }\n v6 = v4 - 1;\n v7 = 0;\n v8 = v4 - 1;\n while (v8 != 1) {\n v56 = v5;\n v9 = v8 - 1;\n v10 = 0;\n v11 = v6;\n v57 = v7;\n v12 = v8 - 1;\n while (v12 != 1) {\n v58 = v10;\n v13 = v12 - 1;\n v14 = v11;\n v15 = 0;\n v59 = v12;\n v16 = v12 - 1;\n v17 = v4;\n v18 = v9;\n v19 = v8;\n while (v16 != 1) {\n v20 = v16 - 1;\n v21 = 0;\n for (i = v16 - 1; i != 1; i = v41) {\n v23 = 0;\n v47 = i - 2;\n v24 = i - 2;\n v52 = i - ((i - 1) & 4294967294);\n v25 = i - 1;\n while (v52 != i) {\n v48 = v14;\n v26 = i;\n v27 = v24;\n v28 = 0;\n v49 = v17;\n v29 = v20;\n v30 = v23;\n v50 = v18;\n v31 = v16;\n v32 = v21;\n v51 = v24;\n if (v24 <= 1) {\n LABEL_21:\n v21 = v32;\n v38 = v30;\n v16 = v31;\n v20 = v29;\n v39 = v26;\n v17 = v49;\n v18 = v50;\n ++v28;\n v14 = v48;\n v40 = v51;\n } else {\n while (1) {\n v33 = v27;\n v34 = 0;\n do {\n v35 = v33;\n v65 = v26;\n v33 -= 2;\n v64 = v25;\n v63 = v31;\n v62 = v13;\n v61 = v19;\n v60 = v28;\n v36 = sub_11F0(v35);\n v28 = v60;\n v19 = v61;\n v34 += v36;\n v13 = v62;\n v31 = v63;\n v25 = v64;\n v26 = v65;\n } while (v33 > 1);\n v28 = v60 + v34 + 1;\n v37 = v27 - 2;\n if (v27 == 2) break;\n v27 -= 2;\n if (v37 <= 1) goto LABEL_21;\n }\n v21 = v32;\n v38 = v30;\n v16 = v63;\n v20 = v29;\n v39 = v65;\n v17 = v49;\n v18 = v50;\n v14 = v48;\n v40 = v51;\n }\n i = v39 - 2;\n v23 = v38 + v28 + 1;\n v24 = v40 - 2;\n if (i <= 1) {\n v41 = v47;\n v42 = v25;\n goto LABEL_34;\n }\n }\n v41 = v47;\n v42 = v25;\n ++v23;\n LABEL_34:\n v21 += v23 + 1;\n if (v42 == 1) goto LABEL_25;\n }\n ++v21;\n LABEL_25:\n v15 += v21 + 1;\n v16 -= 2;\n if (v20 == 1) {\n v43 = v58;\n v44 = v59;\n v4 = v17;\n v9 = v18;\n v11 = v14;\n v8 = v19;\n goto LABEL_27;\n }\n }\n v4 = v17;\n v43 = v58;\n v44 = v59;\n v11 = v14;\n v9 = v18;\n v8 = v19;\n ++v15;\n LABEL_27:\n v10 = v43 + v15 + 1;\n v12 = v44 - 2;\n if (v13 == 1) {\n v5 = v56;\n v45 = v57;\n v6 = v11;\n goto LABEL_29;\n }\n }\n v5 = v56;\n v45 = v57;\n v6 = v11;\n ++v10;\n LABEL_29:\n v7 = v45 + v10 + 1;\n v8 -= 2;\n if (v9 == 1) {\n v5 += v7 + 1;\n v4 -= 2;\n if (v6 != 1) goto LABEL_5;\n goto LABEL_31;\n }\n }\n v4 -= 2;\n v5 += v7 + 1 + 1;\n if (v6 != 1) goto LABEL_5;\n LABEL_31:\n v3 = v53 + v5 + 1;\n v2 = v55 - 2;\n if (v54 != 1) goto LABEL_3;\n return (unsigned int)(v53 + v5 + 2);\n }\n return v1;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v1;\n int v2;\n int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n int v8;\n int v9;\n int v10;\n int v11;\n int v12;\n int v13;\n int v14;\n int v15;\n int v16;\n int v17;\n int v18;\n int v19;\n int v20;\n int v21;\n unsigned int i;\n int v23;\n unsigned int v24;\n unsigned int v25;\n unsigned int v26;\n unsigned int v27;\n int v28;\n int v29;\n int v30;\n int v31;\n int v32;\n unsigned int v33;\n int v34;\n long long v35;\n int v36;\n unsigned int v37;\n int v38;\n unsigned int v39;\n unsigned int v40;\n unsigned int v41;\n unsigned int v42;\n int v43;\n int v44;\n int v45;\n unsigned int v47;\n int v48;\n int v49;\n int v50;\n unsigned int v51;\n unsigned int v52;\n int v53;\n int v54;\n int v55;\n int v56;\n int v57;\n int v58;\n int v59;\n int v60;\n int v61;\n int v62;\n int v63;\n unsigned int v64;\n unsigned int v65;\n v1 = 1;\n if ((unsigned int)(a1 - 1) > 1) {\n v2 = a1 - 2;\n v3 = 0;\n while (1) {\n LABEL_3:\n if (v2 == 1) return (unsigned int)(v3 + 2);\n v4 = v2 - 1;\n v53 = v3;\n v5 = 0;\n v54 = v2 - 1;\n v55 = v2;\n LABEL_5:\n if (v4 != 1) break;\n v3 = v53 + v5 + 1 + 1;\n v2 = v55 - 2;\n if (v54 == 1) return (unsigned int)(v53 + v5 + 1 + 2);\n }\n v6 = v4 - 1;\n v7 = 0;\n v8 = v4 - 1;\n while (v8 != 1) {\n v56 = v5;\n v9 = v8 - 1;\n v10 = 0;\n v11 = v6;\n v57 = v7;\n v12 = v8 - 1;\n while (v12 != 1) {\n v58 = v10;\n v13 = v12 - 1;\n v14 = v11;\n v15 = 0;\n v59 = v12;\n v16 = v12 - 1;\n v17 = v4;\n v18 = v9;\n v19 = v8;\n while (v16 != 1) {\n v20 = v16 - 1;\n v21 = 0;\n for (i = v16 - 1; i != 1; i = v41) {\n v23 = 0;\n v47 = i - 2;\n v24 = i - 2;\n v52 = i - ((i - 1) & 4294967294);\n v25 = i - 1;\n while (v52 != i) {\n v48 = v14;\n v26 = i;\n v27 = v24;\n v28 = 0;\n v49 = v17;\n v29 = v20;\n v30 = v23;\n v50 = v18;\n v31 = v16;\n v32 = v21;\n v51 = v24;\n if (v24 <= 1) {\n LABEL_21:\n v21 = v32;\n v38 = v30;\n v16 = v31;\n v20 = v29;\n v39 = v26;\n v17 = v49;\n v18 = v50;\n ++v28;\n v14 = v48;\n v40 = v51;\n } else {\n while (1) {\n v33 = v27;\n v34 = 0;\n do {\n v35 = v33;\n v65 = v26;\n v33 -= 2;\n v64 = v25;\n v63 = v31;\n v62 = v13;\n v61 = v19;\n v60 = v28;\n v36 = func0(v35);\n v28 = v60;\n v19 = v61;\n v34 += v36;\n v13 = v62;\n v31 = v63;\n v25 = v64;\n v26 = v65;\n } while (v33 > 1);\n v28 = v60 + v34 + 1;\n v37 = v27 - 2;\n if (v27 == 2) break;\n v27 -= 2;\n if (v37 <= 1) goto LABEL_21;\n }\n v21 = v32;\n v38 = v30;\n v16 = v63;\n v20 = v29;\n v39 = v65;\n v17 = v49;\n v18 = v50;\n v14 = v48;\n v40 = v51;\n }\n i = v39 - 2;\n v23 = v38 + v28 + 1;\n v24 = v40 - 2;\n if (i <= 1) {\n v41 = v47;\n v42 = v25;\n goto LABEL_34;\n }\n }\n v41 = v47;\n v42 = v25;\n ++v23;\n LABEL_34:\n v21 += v23 + 1;\n if (v42 == 1) goto LABEL_25;\n }\n ++v21;\n LABEL_25:\n v15 += v21 + 1;\n v16 -= 2;\n if (v20 == 1) {\n v43 = v58;\n v44 = v59;\n v4 = v17;\n v9 = v18;\n v11 = v14;\n v8 = v19;\n goto LABEL_27;\n }\n }\n v4 = v17;\n v43 = v58;\n v44 = v59;\n v11 = v14;\n v9 = v18;\n v8 = v19;\n ++v15;\n LABEL_27:\n v10 = v43 + v15 + 1;\n v12 = v44 - 2;\n if (v13 == 1) {\n v5 = v56;\n v45 = v57;\n v6 = v11;\n goto LABEL_29;\n }\n }\n v5 = v56;\n v45 = v57;\n v6 = v11;\n ++v10;\n LABEL_29:\n v7 = v45 + v10 + 1;\n v8 -= 2;\n if (v9 == 1) {\n v5 += v7 + 1;\n v4 -= 2;\n if (v6 != 1) goto LABEL_5;\n goto LABEL_31;\n }\n }\n v4 -= 2;\n v5 += v7 + 1 + 1;\n if (v6 != 1) goto LABEL_5;\n LABEL_31:\n v3 = v53 + v5 + 1;\n v2 = v55 - 2;\n if (v54 != 1) goto LABEL_3;\n return (unsigned int)(v53 + v5 + 2);\n }\n return v1;\n}" + }, + { + "index": 873, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n == 1 || n == 2) {\n return 1;\n } else {\n return (func0(n - 1) + func0(n - 2));\n }\n}", + "test": "int main() {\n\n assert(func0(7) == 13);\n\n assert(func0(8) == 21);\n\n assert(func0(9) == 34);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov $0x1,%eax\npush %rbx\nlea -0x1(%rdi),%ebx\nsub $0x8,%rsp\ncmp $0x1,%ebx\njbe 12dd \nxor %ebp,%ebp\nmov %ebx,%edi\nsub $0x2,%ebx\ncallq 12b0 \nadd %eax,%ebp\ncmp $0x1,%ebx\nja 12c9 \nlea 0x1(%rbp),%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r15\nlea edx, [rdi-1]\npush r14\npush r13\nmov r13d, 1\npush r12\npush rbp\npush rbx\nsub rsp, 58h\ncmp edx, 1\njbe loc_155C\nlea r15d, [rdi-2]\nxor r13d, r13d\nloc_128B:\ncmp r15d, 1\njz loc_1558\nlea ebp, [r15-1]\nmov [rsp+88h+var_70], r13d\nxor r14d, r14d\nmov [rsp+88h+var_6C], ebp\nmov [rsp+88h+var_68], r15d\nloc_12AA:\ncmp ebp, 1\njz loc_156E\nlea ecx, [rbp-1]\nxor r13d, r13d\nmov r15d, ecx\nloc_12BC:\ncmp r15d, 1\njz loc_153E\nmov [rsp+88h+var_64], r14d\nlea edi, [r15-1]\nxor r12d, r12d\nmov esi, ecx\nmov [rsp+88h+var_60], r13d\nmov ebx, edi\nloc_12DB:\ncmp ebx, 1\njz loc_14FC\nmov [rsp+88h+var_5C], r12d\nlea r10d, [rbx-1]\nmov r11d, esi\nxor r14d, r14d\nmov [rsp+88h+var_58], ebx\nmov r13d, r10d\nmov esi, ebp\nmov r9d, edi\nmov ecx, r15d\nloc_1302:\ncmp r13d, 1\njz loc_14DF\nlea r15d, [r13-1]\nxor ebp, ebp\nmov ebx, r15d\nloc_1315:\ncmp ebx, 1\njz loc_1426\nlea eax, [rbx-1]\nlea edx, [rbx-2]\nmov r8d, ebx\nxor r12d, r12d\nmov edi, eax\nmov [rsp+88h+var_88], edx\nand edi, 0FFFFFFFEh\nsub r8d, edi\nmov edi, edx\nmov [rsp+88h+var_74], r8d\nmov r8d, eax\nloc_133F:\ncmp [rsp+88h+var_74], ebx\njz loc_14C0\nmov [rsp+88h+var_84], r11d\nmov r11d, ebx\nmov ebx, edi\nxor edx, edx\nmov [rsp+88h+var_80], esi\nmov esi, r15d\nmov r15d, r12d\nmov [rsp+88h+var_7C], r9d\nmov r9d, r13d\nmov r13d, ebp\nmov [rsp+88h+var_78], edi\ncmp ebx, 1\njbe short loc_13E3\nloc_1373:\nmov r12d, ebx\nxor ebp, ebp\nloc_1378:\nmov edi, r12d\nmov [rsp+88h+var_3C], r11d\nsub r12d, 2\nmov [rsp+88h+var_40], r8d\nmov [rsp+88h+var_44], r9d\nmov [rsp+88h+var_48], esi\nmov [rsp+88h+var_4C], r10d\nmov [rsp+88h+var_50], ecx\nmov [rsp+88h+var_54], edx\ncall func0\nmov edx, [rsp+88h+var_54]\nmov ecx, [rsp+88h+var_50]\nadd ebp, eax\ncmp r12d, 1\nmov r10d, [rsp+88h+var_4C]\nmov esi, [rsp+88h+var_48]\nmov r9d, [rsp+88h+var_44]\nmov r8d, [rsp+88h+var_40]\nmov r11d, [rsp+88h+var_3C]\nja short loc_1378\nlea edx, [rdx+rbp+1]\nlea edi, [rbx-2]\ncmp ebx, 2\njz loc_1518\nmov ebx, edi\ncmp ebx, 1\nja short loc_1373\nloc_13E3:\nmov ebp, r13d\nmov r12d, r15d\nmov r13d, r9d\nmov r15d, esi\nmov ebx, r11d\nmov esi, [rsp+88h+var_80]\nmov r9d, [rsp+88h+var_7C]\nadd edx, 1\nmov r11d, [rsp+88h+var_84]\nmov edi, [rsp+88h+var_78]\nloc_1407:\nsub ebx, 2\nlea r12d, [r12+rdx+1]\nsub edi, 2\ncmp ebx, 1\nja loc_133F\nmov edx, [rsp+88h+var_88]\nmov eax, r8d\njmp loc_14CA\nloc_1426:\nadd ebp, 1\nloc_1429:\nlea r14d, [r14+rbp+1]\nsub r13d, 2\ncmp r15d, 1\njnz loc_1302\nmov r12d, [rsp+88h+var_5C]\nmov ebx, [rsp+88h+var_58]\nmov ebp, esi\nmov edi, r9d\nmov esi, r11d\nmov r15d, ecx\nloc_1450:\nlea r12d, [r12+r14+1]\nsub ebx, 2\ncmp r10d, 1\njnz loc_12DB\nmov r14d, [rsp+88h+var_64]\nmov r13d, [rsp+88h+var_60]\nmov ecx, esi\nloc_146E:\nlea r13d, [r13+r12+1]\nsub r15d, 2\ncmp edi, 1\njnz loc_12BC\nlea r14d, [r14+r13+1]\nsub ebp, 2\ncmp ecx, 1\njnz loc_12AA\nloc_1491:\nmov r13d, [rsp+88h+var_70]\nmov r15d, [rsp+88h+var_68]\nmov ebp, [rsp+88h+var_6C]\nlea r13d, [r13+r14+1]\nsub r15d, 2\ncmp ebp, 1\njnz loc_128B\nadd r13d, 1\njmp loc_155C\nloc_14C0:\nmov edx, [rsp+88h+var_88]\nmov eax, r8d\nadd r12d, 1\nloc_14CA:\nlea ebp, [rbp+r12+1]\ncmp eax, 1\njz loc_1429\nmov ebx, edx\njmp loc_1315\nloc_14DF:\nmov ebp, esi\nmov r12d, [rsp+88h+var_5C]\nmov ebx, [rsp+88h+var_58]\nmov esi, r11d\nmov edi, r9d\nmov r15d, ecx\nadd r14d, 1\njmp loc_1450\nloc_14FC:\nmov r14d, [rsp+88h+var_64]\nmov r13d, [rsp+88h+var_60]\nmov ecx, esi\nadd r12d, 1\njmp loc_146E\nloc_1518:\nmov ebp, r13d\nmov r12d, r15d\nmov r13d, r9d\nmov r15d, esi\nmov ebx, r11d\nmov esi, [rsp+88h+var_80]\nmov r9d, [rsp+88h+var_7C]\nmov r11d, [rsp+88h+var_84]\nmov edi, [rsp+88h+var_78]\njmp loc_1407\nloc_153E:\nadd r13d, 1\nsub ebp, 2\nlea r14d, [r14+r13+1]\ncmp ecx, 1\njnz loc_12AA\njmp loc_1491\nloc_1558:\nadd r13d, 2\nloc_155C:\nadd rsp, 58h\nmov eax, r13d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_156E:\nmov r13d, [rsp+88h+var_70]\nmov r15d, [rsp+88h+var_68]\nadd r14d, 1\nmov ebp, [rsp+88h+var_6C]\nlea r13d, [r13+r14+1]\nsub r15d, 2\ncmp ebp, 1\njnz loc_128B\nadd r13d, 1\njmp short loc_155C", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v1; // r13d\n int v2; // r15d\n int v3; // r13d\n int v4; // ebp\n int v5; // r14d\n int v6; // ecx\n int v7; // r13d\n int v8; // r15d\n int v9; // edi\n int v10; // r12d\n int v11; // esi\n int v12; // ebx\n int v13; // r10d\n int v14; // r11d\n int v15; // r14d\n int v16; // r13d\n int v17; // esi\n int v18; // r9d\n int v19; // ecx\n int v20; // r15d\n int v21; // ebp\n unsigned int i; // ebx\n int v23; // r12d\n unsigned int v24; // edi\n unsigned int v25; // r8d\n unsigned int v26; // r11d\n unsigned int v27; // ebx\n int v28; // edx\n int v29; // esi\n int v30; // r15d\n int v31; // r9d\n int v32; // r13d\n unsigned int v33; // r12d\n int v34; // ebp\n __int64 v35; // rdi\n int v36; // eax\n unsigned int v37; // edi\n int v38; // r12d\n unsigned int v39; // ebx\n unsigned int v40; // edi\n unsigned int v41; // edx\n unsigned int v42; // eax\n int v43; // r12d\n int v44; // ebx\n int v45; // r13d\n unsigned int v47; // [rsp+0h] [rbp-88h]\n int v48; // [rsp+4h] [rbp-84h]\n int v49; // [rsp+8h] [rbp-80h]\n int v50; // [rsp+Ch] [rbp-7Ch]\n unsigned int v51; // [rsp+10h] [rbp-78h]\n unsigned int v52; // [rsp+14h] [rbp-74h]\n int v53; // [rsp+18h] [rbp-70h]\n int v54; // [rsp+1Ch] [rbp-6Ch]\n int v55; // [rsp+20h] [rbp-68h]\n int v56; // [rsp+24h] [rbp-64h]\n int v57; // [rsp+28h] [rbp-60h]\n int v58; // [rsp+2Ch] [rbp-5Ch]\n int v59; // [rsp+30h] [rbp-58h]\n int v60; // [rsp+34h] [rbp-54h]\n int v61; // [rsp+38h] [rbp-50h]\n int v62; // [rsp+3Ch] [rbp-4Ch]\n int v63; // [rsp+44h] [rbp-44h]\n unsigned int v64; // [rsp+48h] [rbp-40h]\n unsigned int v65; // [rsp+4Ch] [rbp-3Ch]\n\n v1 = 1;\n if ( (unsigned int)(a1 - 1) > 1 )\n {\n v2 = a1 - 2;\n v3 = 0;\n while ( 1 )\n {\nLABEL_3:\n if ( v2 == 1 )\n return (unsigned int)(v3 + 2);\n v4 = v2 - 1;\n v53 = v3;\n v5 = 0;\n v54 = v2 - 1;\n v55 = v2;\nLABEL_5:\n if ( v4 != 1 )\n break;\n v3 = v53 + v5 + 1 + 1;\n v2 = v55 - 2;\n if ( v54 == 1 )\n return (unsigned int)(v53 + v5 + 1 + 2);\n }\n v6 = v4 - 1;\n v7 = 0;\n v8 = v4 - 1;\n while ( v8 != 1 )\n {\n v56 = v5;\n v9 = v8 - 1;\n v10 = 0;\n v11 = v6;\n v57 = v7;\n v12 = v8 - 1;\n while ( v12 != 1 )\n {\n v58 = v10;\n v13 = v12 - 1;\n v14 = v11;\n v15 = 0;\n v59 = v12;\n v16 = v12 - 1;\n v17 = v4;\n v18 = v9;\n v19 = v8;\n while ( v16 != 1 )\n {\n v20 = v16 - 1;\n v21 = 0;\n for ( i = v16 - 1; i != 1; i = v41 )\n {\n v23 = 0;\n v47 = i - 2;\n v24 = i - 2;\n v52 = i - ((i - 1) & 0xFFFFFFFE);\n v25 = i - 1;\n while ( v52 != i )\n {\n v48 = v14;\n v26 = i;\n v27 = v24;\n v28 = 0;\n v49 = v17;\n v29 = v20;\n v30 = v23;\n v50 = v18;\n v31 = v16;\n v32 = v21;\n v51 = v24;\n if ( v24 <= 1 )\n {\nLABEL_21:\n v21 = v32;\n v38 = v30;\n v16 = v31;\n v20 = v29;\n v39 = v26;\n v17 = v49;\n v18 = v50;\n ++v28;\n v14 = v48;\n v40 = v51;\n }\n else\n {\n while ( 1 )\n {\n v33 = v27;\n v34 = 0;\n do\n {\n v35 = v33;\n v65 = v26;\n v33 -= 2;\n v64 = v25;\n v63 = v31;\n v62 = v13;\n v61 = v19;\n v60 = v28;\n v36 = func0(v35);\n v28 = v60;\n v19 = v61;\n v34 += v36;\n v13 = v62;\n v31 = v63;\n v25 = v64;\n v26 = v65;\n }\n while ( v33 > 1 );\n v28 = v60 + v34 + 1;\n v37 = v27 - 2;\n if ( v27 == 2 )\n break;\n v27 -= 2;\n if ( v37 <= 1 )\n goto LABEL_21;\n }\n v21 = v32;\n v38 = v30;\n v16 = v63;\n v20 = v29;\n v39 = v65;\n v17 = v49;\n v18 = v50;\n v14 = v48;\n v40 = v51;\n }\n i = v39 - 2;\n v23 = v38 + v28 + 1;\n v24 = v40 - 2;\n if ( i <= 1 )\n {\n v41 = v47;\n v42 = v25;\n goto LABEL_34;\n }\n }\n v41 = v47;\n v42 = v25;\n ++v23;\nLABEL_34:\n v21 += v23 + 1;\n if ( v42 == 1 )\n goto LABEL_25;\n }\n ++v21;\nLABEL_25:\n v15 += v21 + 1;\n v16 -= 2;\n if ( v20 == 1 )\n {\n v43 = v58;\n v44 = v59;\n v4 = v17;\n v9 = v18;\n v11 = v14;\n v8 = v19;\n goto LABEL_27;\n }\n }\n v4 = v17;\n v43 = v58;\n v44 = v59;\n v11 = v14;\n v9 = v18;\n v8 = v19;\n ++v15;\nLABEL_27:\n v10 = v43 + v15 + 1;\n v12 = v44 - 2;\n if ( v13 == 1 )\n {\n v5 = v56;\n v45 = v57;\n v6 = v11;\n goto LABEL_29;\n }\n }\n v5 = v56;\n v45 = v57;\n v6 = v11;\n ++v10;\nLABEL_29:\n v7 = v45 + v10 + 1;\n v8 -= 2;\n if ( v9 == 1 )\n {\n v5 += v7 + 1;\n v4 -= 2;\n if ( v6 != 1 )\n goto LABEL_5;\n goto LABEL_31;\n }\n }\n v4 -= 2;\n v5 += v7 + 1 + 1;\n if ( v6 != 1 )\n goto LABEL_5;\nLABEL_31:\n v3 = v53 + v5 + 1;\n v2 = v55 - 2;\n if ( v54 != 1 )\n goto LABEL_3;\n return (unsigned int)(v53 + v5 + 2);\n }\n return v1;\n}", + "ida_strip_asm": "sub_1260:\nendbr64\npush r15\nlea edx, [rdi-1]\npush r14\npush r13\nmov r13d, 1\npush r12\npush rbp\npush rbx\nsub rsp, 58h\ncmp edx, 1\njbe loc_155C\nlea r15d, [rdi-2]\nxor r13d, r13d\nloc_128B:\ncmp r15d, 1\njz loc_1558\nlea ebp, [r15-1]\nmov [rsp+88h+var_70], r13d\nxor r14d, r14d\nmov [rsp+88h+var_6C], ebp\nmov [rsp+88h+var_68], r15d\nloc_12AA:\ncmp ebp, 1\njz loc_156E\nlea ecx, [rbp-1]\nxor r13d, r13d\nmov r15d, ecx\nloc_12BC:\ncmp r15d, 1\njz loc_153E\nmov [rsp+88h+var_64], r14d\nlea edi, [r15-1]\nxor r12d, r12d\nmov esi, ecx\nmov [rsp+88h+var_60], r13d\nmov ebx, edi\nloc_12DB:\ncmp ebx, 1\njz loc_14FC\nmov [rsp+88h+var_5C], r12d\nlea r10d, [rbx-1]\nmov r11d, esi\nxor r14d, r14d\nmov [rsp+88h+var_58], ebx\nmov r13d, r10d\nmov esi, ebp\nmov r9d, edi\nmov ecx, r15d\nloc_1302:\ncmp r13d, 1\njz loc_14DF\nlea r15d, [r13-1]\nxor ebp, ebp\nmov ebx, r15d\nloc_1315:\ncmp ebx, 1\njz loc_1426\nlea eax, [rbx-1]\nlea edx, [rbx-2]\nmov r8d, ebx\nxor r12d, r12d\nmov edi, eax\nmov [rsp+88h+var_88], edx\nand edi, 0FFFFFFFEh\nsub r8d, edi\nmov edi, edx\nmov [rsp+88h+var_74], r8d\nmov r8d, eax\nloc_133F:\ncmp [rsp+88h+var_74], ebx\njz loc_14C0\nmov [rsp+88h+var_84], r11d\nmov r11d, ebx\nmov ebx, edi\nxor edx, edx\nmov [rsp+88h+var_80], esi\nmov esi, r15d\nmov r15d, r12d\nmov [rsp+88h+var_7C], r9d\nmov r9d, r13d\nmov r13d, ebp\nmov [rsp+88h+var_78], edi\ncmp ebx, 1\njbe short loc_13E3\nloc_1373:\nmov r12d, ebx\nxor ebp, ebp\nloc_1378:\nmov edi, r12d\nmov [rsp+88h+var_3C], r11d\nsub r12d, 2\nmov [rsp+88h+var_40], r8d\nmov [rsp+88h+var_44], r9d\nmov [rsp+88h+var_48], esi\nmov [rsp+88h+var_4C], r10d\nmov [rsp+88h+var_50], ecx\nmov [rsp+88h+var_54], edx\ncall sub_1260\nmov edx, [rsp+88h+var_54]\nmov ecx, [rsp+88h+var_50]\nadd ebp, eax\ncmp r12d, 1\nmov r10d, [rsp+88h+var_4C]\nmov esi, [rsp+88h+var_48]\nmov r9d, [rsp+88h+var_44]\nmov r8d, [rsp+88h+var_40]\nmov r11d, [rsp+88h+var_3C]\nja short loc_1378\nlea edx, [rdx+rbp+1]\nlea edi, [rbx-2]\ncmp ebx, 2\njz loc_1518\nmov ebx, edi\ncmp ebx, 1\nja short loc_1373\nloc_13E3:\nmov ebp, r13d\nmov r12d, r15d\nmov r13d, r9d\nmov r15d, esi\nmov ebx, r11d\nmov esi, [rsp+88h+var_80]\nmov r9d, [rsp+88h+var_7C]\nadd edx, 1\nmov r11d, [rsp+88h+var_84]\nmov edi, [rsp+88h+var_78]\nloc_1407:\nsub ebx, 2\nlea r12d, [r12+rdx+1]\nsub edi, 2\ncmp ebx, 1\nja loc_133F\nmov edx, [rsp+88h+var_88]\nmov eax, r8d\njmp loc_14CA\nloc_1426:\nadd ebp, 1\nloc_1429:\nlea r14d, [r14+rbp+1]\nsub r13d, 2\ncmp r15d, 1\njnz loc_1302\nmov r12d, [rsp+88h+var_5C]\nmov ebx, [rsp+88h+var_58]\nmov ebp, esi\nmov edi, r9d\nmov esi, r11d\nmov r15d, ecx\nloc_1450:\nlea r12d, [r12+r14+1]\nsub ebx, 2\ncmp r10d, 1\njnz loc_12DB\nmov r14d, [rsp+88h+var_64]\nmov r13d, [rsp+88h+var_60]\nmov ecx, esi\nloc_146E:\nlea r13d, [r13+r12+1]\nsub r15d, 2\ncmp edi, 1\njnz loc_12BC\nlea r14d, [r14+r13+1]\nsub ebp, 2\ncmp ecx, 1\njnz loc_12AA\nloc_1491:\nmov r13d, [rsp+88h+var_70]\nmov r15d, [rsp+88h+var_68]\nmov ebp, [rsp+88h+var_6C]\nlea r13d, [r13+r14+1]\nsub r15d, 2\ncmp ebp, 1\njnz loc_128B\nadd r13d, 1\njmp loc_155C\nloc_14C0:\nmov edx, [rsp+88h+var_88]\nmov eax, r8d\nadd r12d, 1\nloc_14CA:\nlea ebp, [rbp+r12+1]\ncmp eax, 1\njz loc_1429\nmov ebx, edx\njmp loc_1315\nloc_14DF:\nmov ebp, esi\nmov r12d, [rsp+88h+var_5C]\nmov ebx, [rsp+88h+var_58]\nmov esi, r11d\nmov edi, r9d\nmov r15d, ecx\nadd r14d, 1\njmp loc_1450\nloc_14FC:\nmov r14d, [rsp+88h+var_64]\nmov r13d, [rsp+88h+var_60]\nmov ecx, esi\nadd r12d, 1\njmp loc_146E\nloc_1518:\nmov ebp, r13d\nmov r12d, r15d\nmov r13d, r9d\nmov r15d, esi\nmov ebx, r11d\nmov esi, [rsp+88h+var_80]\nmov r9d, [rsp+88h+var_7C]\nmov r11d, [rsp+88h+var_84]\nmov edi, [rsp+88h+var_78]\njmp loc_1407\nloc_153E:\nadd r13d, 1\nsub ebp, 2\nlea r14d, [r14+r13+1]\ncmp ecx, 1\njnz loc_12AA\njmp loc_1491\nloc_1558:\nadd r13d, 2\nloc_155C:\nadd rsp, 58h\nmov eax, r13d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_156E:\nmov r13d, [rsp+88h+var_70]\nmov r15d, [rsp+88h+var_68]\nadd r14d, 1\nmov ebp, [rsp+88h+var_6C]\nlea r13d, [r13+r14+1]\nsub r15d, 2\ncmp ebp, 1\njnz loc_128B\nadd r13d, 1\njmp short loc_155C", + "ida_strip_pseudo": "__int64 __fastcall sub_1260(int a1)\n{\n unsigned int v1; // r13d\n int v2; // r15d\n int v3; // r13d\n int v4; // ebp\n int v5; // r14d\n int v6; // ecx\n int v7; // r13d\n int v8; // r15d\n int v9; // edi\n int v10; // r12d\n int v11; // esi\n int v12; // ebx\n int v13; // r10d\n int v14; // r11d\n int v15; // r14d\n int v16; // r13d\n int v17; // esi\n int v18; // r9d\n int v19; // ecx\n int v20; // r15d\n int v21; // ebp\n unsigned int i; // ebx\n int v23; // r12d\n unsigned int v24; // edi\n unsigned int v25; // r8d\n unsigned int v26; // r11d\n unsigned int v27; // ebx\n int v28; // edx\n int v29; // esi\n int v30; // r15d\n int v31; // r9d\n int v32; // r13d\n unsigned int v33; // r12d\n int v34; // ebp\n __int64 v35; // rdi\n int v36; // eax\n unsigned int v37; // edi\n int v38; // r12d\n unsigned int v39; // ebx\n unsigned int v40; // edi\n unsigned int v41; // edx\n unsigned int v42; // eax\n int v43; // r12d\n int v44; // ebx\n int v45; // r13d\n unsigned int v47; // [rsp+0h] [rbp-88h]\n int v48; // [rsp+4h] [rbp-84h]\n int v49; // [rsp+8h] [rbp-80h]\n int v50; // [rsp+Ch] [rbp-7Ch]\n unsigned int v51; // [rsp+10h] [rbp-78h]\n unsigned int v52; // [rsp+14h] [rbp-74h]\n int v53; // [rsp+18h] [rbp-70h]\n int v54; // [rsp+1Ch] [rbp-6Ch]\n int v55; // [rsp+20h] [rbp-68h]\n int v56; // [rsp+24h] [rbp-64h]\n int v57; // [rsp+28h] [rbp-60h]\n int v58; // [rsp+2Ch] [rbp-5Ch]\n int v59; // [rsp+30h] [rbp-58h]\n int v60; // [rsp+34h] [rbp-54h]\n int v61; // [rsp+38h] [rbp-50h]\n int v62; // [rsp+3Ch] [rbp-4Ch]\n int v63; // [rsp+44h] [rbp-44h]\n unsigned int v64; // [rsp+48h] [rbp-40h]\n unsigned int v65; // [rsp+4Ch] [rbp-3Ch]\n\n v1 = 1;\n if ( (unsigned int)(a1 - 1) > 1 )\n {\n v2 = a1 - 2;\n v3 = 0;\n while ( 1 )\n {\nLABEL_3:\n if ( v2 == 1 )\n return (unsigned int)(v3 + 2);\n v4 = v2 - 1;\n v53 = v3;\n v5 = 0;\n v54 = v2 - 1;\n v55 = v2;\nLABEL_5:\n if ( v4 != 1 )\n break;\n v3 = v53 + v5 + 1 + 1;\n v2 = v55 - 2;\n if ( v54 == 1 )\n return (unsigned int)(v53 + v5 + 1 + 2);\n }\n v6 = v4 - 1;\n v7 = 0;\n v8 = v4 - 1;\n while ( v8 != 1 )\n {\n v56 = v5;\n v9 = v8 - 1;\n v10 = 0;\n v11 = v6;\n v57 = v7;\n v12 = v8 - 1;\n while ( v12 != 1 )\n {\n v58 = v10;\n v13 = v12 - 1;\n v14 = v11;\n v15 = 0;\n v59 = v12;\n v16 = v12 - 1;\n v17 = v4;\n v18 = v9;\n v19 = v8;\n while ( v16 != 1 )\n {\n v20 = v16 - 1;\n v21 = 0;\n for ( i = v16 - 1; i != 1; i = v41 )\n {\n v23 = 0;\n v47 = i - 2;\n v24 = i - 2;\n v52 = i - ((i - 1) & 0xFFFFFFFE);\n v25 = i - 1;\n while ( v52 != i )\n {\n v48 = v14;\n v26 = i;\n v27 = v24;\n v28 = 0;\n v49 = v17;\n v29 = v20;\n v30 = v23;\n v50 = v18;\n v31 = v16;\n v32 = v21;\n v51 = v24;\n if ( v24 <= 1 )\n {\nLABEL_21:\n v21 = v32;\n v38 = v30;\n v16 = v31;\n v20 = v29;\n v39 = v26;\n v17 = v49;\n v18 = v50;\n ++v28;\n v14 = v48;\n v40 = v51;\n }\n else\n {\n while ( 1 )\n {\n v33 = v27;\n v34 = 0;\n do\n {\n v35 = v33;\n v65 = v26;\n v33 -= 2;\n v64 = v25;\n v63 = v31;\n v62 = v13;\n v61 = v19;\n v60 = v28;\n v36 = sub_1260(v35);\n v28 = v60;\n v19 = v61;\n v34 += v36;\n v13 = v62;\n v31 = v63;\n v25 = v64;\n v26 = v65;\n }\n while ( v33 > 1 );\n v28 = v60 + v34 + 1;\n v37 = v27 - 2;\n if ( v27 == 2 )\n break;\n v27 -= 2;\n if ( v37 <= 1 )\n goto LABEL_21;\n }\n v21 = v32;\n v38 = v30;\n v16 = v63;\n v20 = v29;\n v39 = v65;\n v17 = v49;\n v18 = v50;\n v14 = v48;\n v40 = v51;\n }\n i = v39 - 2;\n v23 = v38 + v28 + 1;\n v24 = v40 - 2;\n if ( i <= 1 )\n {\n v41 = v47;\n v42 = v25;\n goto LABEL_34;\n }\n }\n v41 = v47;\n v42 = v25;\n ++v23;\nLABEL_34:\n v21 += v23 + 1;\n if ( v42 == 1 )\n goto LABEL_25;\n }\n ++v21;\nLABEL_25:\n v15 += v21 + 1;\n v16 -= 2;\n if ( v20 == 1 )\n {\n v43 = v58;\n v44 = v59;\n v4 = v17;\n v9 = v18;\n v11 = v14;\n v8 = v19;\n goto LABEL_27;\n }\n }\n v4 = v17;\n v43 = v58;\n v44 = v59;\n v11 = v14;\n v9 = v18;\n v8 = v19;\n ++v15;\nLABEL_27:\n v10 = v43 + v15 + 1;\n v12 = v44 - 2;\n if ( v13 == 1 )\n {\n v5 = v56;\n v45 = v57;\n v6 = v11;\n goto LABEL_29;\n }\n }\n v5 = v56;\n v45 = v57;\n v6 = v11;\n ++v10;\nLABEL_29:\n v7 = v45 + v10 + 1;\n v8 -= 2;\n if ( v9 == 1 )\n {\n v5 += v7 + 1;\n v4 -= 2;\n if ( v6 != 1 )\n goto LABEL_5;\n goto LABEL_31;\n }\n }\n v4 -= 2;\n v5 += v7 + 1 + 1;\n if ( v6 != 1 )\n goto LABEL_5;\nLABEL_31:\n v3 = v53 + v5 + 1;\n v2 = v55 - 2;\n if ( v54 != 1 )\n goto LABEL_3;\n return (unsigned int)(v53 + v5 + 2);\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1260(int a1) {\n unsigned int v1;\n int v2;\n int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n int v8;\n int v9;\n int v10;\n int v11;\n int v12;\n int v13;\n int v14;\n int v15;\n int v16;\n int v17;\n int v18;\n int v19;\n int v20;\n int v21;\n unsigned int i;\n int v23;\n unsigned int v24;\n unsigned int v25;\n unsigned int v26;\n unsigned int v27;\n int v28;\n int v29;\n int v30;\n int v31;\n int v32;\n unsigned int v33;\n int v34;\n long long v35;\n int v36;\n unsigned int v37;\n int v38;\n unsigned int v39;\n unsigned int v40;\n unsigned int v41;\n unsigned int v42;\n int v43;\n int v44;\n int v45;\n unsigned int v47;\n int v48;\n int v49;\n int v50;\n unsigned int v51;\n unsigned int v52;\n int v53;\n int v54;\n int v55;\n int v56;\n int v57;\n int v58;\n int v59;\n int v60;\n int v61;\n int v62;\n int v63;\n unsigned int v64;\n unsigned int v65;\n v1 = 1;\n if ((unsigned int)(a1 - 1) > 1) {\n v2 = a1 - 2;\n v3 = 0;\n while (1) {\n LABEL_3:\n if (v2 == 1) return (unsigned int)(v3 + 2);\n v4 = v2 - 1;\n v53 = v3;\n v5 = 0;\n v54 = v2 - 1;\n v55 = v2;\n LABEL_5:\n if (v4 != 1) break;\n v3 = v53 + v5 + 1 + 1;\n v2 = v55 - 2;\n if (v54 == 1) return (unsigned int)(v53 + v5 + 1 + 2);\n }\n v6 = v4 - 1;\n v7 = 0;\n v8 = v4 - 1;\n while (v8 != 1) {\n v56 = v5;\n v9 = v8 - 1;\n v10 = 0;\n v11 = v6;\n v57 = v7;\n v12 = v8 - 1;\n while (v12 != 1) {\n v58 = v10;\n v13 = v12 - 1;\n v14 = v11;\n v15 = 0;\n v59 = v12;\n v16 = v12 - 1;\n v17 = v4;\n v18 = v9;\n v19 = v8;\n while (v16 != 1) {\n v20 = v16 - 1;\n v21 = 0;\n for (i = v16 - 1; i != 1; i = v41) {\n v23 = 0;\n v47 = i - 2;\n v24 = i - 2;\n v52 = i - ((i - 1) & 4294967294);\n v25 = i - 1;\n while (v52 != i) {\n v48 = v14;\n v26 = i;\n v27 = v24;\n v28 = 0;\n v49 = v17;\n v29 = v20;\n v30 = v23;\n v50 = v18;\n v31 = v16;\n v32 = v21;\n v51 = v24;\n if (v24 <= 1) {\n LABEL_21:\n v21 = v32;\n v38 = v30;\n v16 = v31;\n v20 = v29;\n v39 = v26;\n v17 = v49;\n v18 = v50;\n ++v28;\n v14 = v48;\n v40 = v51;\n } else {\n while (1) {\n v33 = v27;\n v34 = 0;\n do {\n v35 = v33;\n v65 = v26;\n v33 -= 2;\n v64 = v25;\n v63 = v31;\n v62 = v13;\n v61 = v19;\n v60 = v28;\n v36 = sub_1260(v35);\n v28 = v60;\n v19 = v61;\n v34 += v36;\n v13 = v62;\n v31 = v63;\n v25 = v64;\n v26 = v65;\n } while (v33 > 1);\n v28 = v60 + v34 + 1;\n v37 = v27 - 2;\n if (v27 == 2) break;\n v27 -= 2;\n if (v37 <= 1) goto LABEL_21;\n }\n v21 = v32;\n v38 = v30;\n v16 = v63;\n v20 = v29;\n v39 = v65;\n v17 = v49;\n v18 = v50;\n v14 = v48;\n v40 = v51;\n }\n i = v39 - 2;\n v23 = v38 + v28 + 1;\n v24 = v40 - 2;\n if (i <= 1) {\n v41 = v47;\n v42 = v25;\n goto LABEL_34;\n }\n }\n v41 = v47;\n v42 = v25;\n ++v23;\n LABEL_34:\n v21 += v23 + 1;\n if (v42 == 1) goto LABEL_25;\n }\n ++v21;\n LABEL_25:\n v15 += v21 + 1;\n v16 -= 2;\n if (v20 == 1) {\n v43 = v58;\n v44 = v59;\n v4 = v17;\n v9 = v18;\n v11 = v14;\n v8 = v19;\n goto LABEL_27;\n }\n }\n v4 = v17;\n v43 = v58;\n v44 = v59;\n v11 = v14;\n v9 = v18;\n v8 = v19;\n ++v15;\n LABEL_27:\n v10 = v43 + v15 + 1;\n v12 = v44 - 2;\n if (v13 == 1) {\n v5 = v56;\n v45 = v57;\n v6 = v11;\n goto LABEL_29;\n }\n }\n v5 = v56;\n v45 = v57;\n v6 = v11;\n ++v10;\n LABEL_29:\n v7 = v45 + v10 + 1;\n v8 -= 2;\n if (v9 == 1) {\n v5 += v7 + 1;\n v4 -= 2;\n if (v6 != 1) goto LABEL_5;\n goto LABEL_31;\n }\n }\n v4 -= 2;\n v5 += v7 + 1 + 1;\n if (v6 != 1) goto LABEL_5;\n LABEL_31:\n v3 = v53 + v5 + 1;\n v2 = v55 - 2;\n if (v54 != 1) goto LABEL_3;\n return (unsigned int)(v53 + v5 + 2);\n }\n return v1;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v1;\n int v2;\n int v3;\n int v4;\n int v5;\n int v6;\n int v7;\n int v8;\n int v9;\n int v10;\n int v11;\n int v12;\n int v13;\n int v14;\n int v15;\n int v16;\n int v17;\n int v18;\n int v19;\n int v20;\n int v21;\n unsigned int i;\n int v23;\n unsigned int v24;\n unsigned int v25;\n unsigned int v26;\n unsigned int v27;\n int v28;\n int v29;\n int v30;\n int v31;\n int v32;\n unsigned int v33;\n int v34;\n long long v35;\n int v36;\n unsigned int v37;\n int v38;\n unsigned int v39;\n unsigned int v40;\n unsigned int v41;\n unsigned int v42;\n int v43;\n int v44;\n int v45;\n unsigned int v47;\n int v48;\n int v49;\n int v50;\n unsigned int v51;\n unsigned int v52;\n int v53;\n int v54;\n int v55;\n int v56;\n int v57;\n int v58;\n int v59;\n int v60;\n int v61;\n int v62;\n int v63;\n unsigned int v64;\n unsigned int v65;\n v1 = 1;\n if ((unsigned int)(a1 - 1) > 1) {\n v2 = a1 - 2;\n v3 = 0;\n while (1) {\n LABEL_3:\n if (v2 == 1) return (unsigned int)(v3 + 2);\n v4 = v2 - 1;\n v53 = v3;\n v5 = 0;\n v54 = v2 - 1;\n v55 = v2;\n LABEL_5:\n if (v4 != 1) break;\n v3 = v53 + v5 + 1 + 1;\n v2 = v55 - 2;\n if (v54 == 1) return (unsigned int)(v53 + v5 + 1 + 2);\n }\n v6 = v4 - 1;\n v7 = 0;\n v8 = v4 - 1;\n while (v8 != 1) {\n v56 = v5;\n v9 = v8 - 1;\n v10 = 0;\n v11 = v6;\n v57 = v7;\n v12 = v8 - 1;\n while (v12 != 1) {\n v58 = v10;\n v13 = v12 - 1;\n v14 = v11;\n v15 = 0;\n v59 = v12;\n v16 = v12 - 1;\n v17 = v4;\n v18 = v9;\n v19 = v8;\n while (v16 != 1) {\n v20 = v16 - 1;\n v21 = 0;\n for (i = v16 - 1; i != 1; i = v41) {\n v23 = 0;\n v47 = i - 2;\n v24 = i - 2;\n v52 = i - ((i - 1) & 4294967294);\n v25 = i - 1;\n while (v52 != i) {\n v48 = v14;\n v26 = i;\n v27 = v24;\n v28 = 0;\n v49 = v17;\n v29 = v20;\n v30 = v23;\n v50 = v18;\n v31 = v16;\n v32 = v21;\n v51 = v24;\n if (v24 <= 1) {\n LABEL_21:\n v21 = v32;\n v38 = v30;\n v16 = v31;\n v20 = v29;\n v39 = v26;\n v17 = v49;\n v18 = v50;\n ++v28;\n v14 = v48;\n v40 = v51;\n } else {\n while (1) {\n v33 = v27;\n v34 = 0;\n do {\n v35 = v33;\n v65 = v26;\n v33 -= 2;\n v64 = v25;\n v63 = v31;\n v62 = v13;\n v61 = v19;\n v60 = v28;\n v36 = func0(v35);\n v28 = v60;\n v19 = v61;\n v34 += v36;\n v13 = v62;\n v31 = v63;\n v25 = v64;\n v26 = v65;\n } while (v33 > 1);\n v28 = v60 + v34 + 1;\n v37 = v27 - 2;\n if (v27 == 2) break;\n v27 -= 2;\n if (v37 <= 1) goto LABEL_21;\n }\n v21 = v32;\n v38 = v30;\n v16 = v63;\n v20 = v29;\n v39 = v65;\n v17 = v49;\n v18 = v50;\n v14 = v48;\n v40 = v51;\n }\n i = v39 - 2;\n v23 = v38 + v28 + 1;\n v24 = v40 - 2;\n if (i <= 1) {\n v41 = v47;\n v42 = v25;\n goto LABEL_34;\n }\n }\n v41 = v47;\n v42 = v25;\n ++v23;\n LABEL_34:\n v21 += v23 + 1;\n if (v42 == 1) goto LABEL_25;\n }\n ++v21;\n LABEL_25:\n v15 += v21 + 1;\n v16 -= 2;\n if (v20 == 1) {\n v43 = v58;\n v44 = v59;\n v4 = v17;\n v9 = v18;\n v11 = v14;\n v8 = v19;\n goto LABEL_27;\n }\n }\n v4 = v17;\n v43 = v58;\n v44 = v59;\n v11 = v14;\n v9 = v18;\n v8 = v19;\n ++v15;\n LABEL_27:\n v10 = v43 + v15 + 1;\n v12 = v44 - 2;\n if (v13 == 1) {\n v5 = v56;\n v45 = v57;\n v6 = v11;\n goto LABEL_29;\n }\n }\n v5 = v56;\n v45 = v57;\n v6 = v11;\n ++v10;\n LABEL_29:\n v7 = v45 + v10 + 1;\n v8 -= 2;\n if (v9 == 1) {\n v5 += v7 + 1;\n v4 -= 2;\n if (v6 != 1) goto LABEL_5;\n goto LABEL_31;\n }\n }\n v4 -= 2;\n v5 += v7 + 1 + 1;\n if (v6 != 1) goto LABEL_5;\n LABEL_31:\n v3 = v53 + v5 + 1;\n v2 = v55 - 2;\n if (v54 != 1) goto LABEL_3;\n return (unsigned int)(v53 + v5 + 2);\n }\n return v1;\n}" + }, + { + "index": 874, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char* str1, const char* str2) {\n int N = strlen(str1);\n int M = strlen(str2);\n if (N % M != 0) {\n return false;\n }\n for (int i = 0; i < N; i++) {\n if (str1[i] != str2[i % M]) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n assert(func0(\"abcabcabc\", \"abc\") == true);\n\n assert(func0(\"abcab\", \"abc\") == false);\n\n assert(func0(\"aba\", \"ab\") == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov -0x18(%rbp),%rax\nmov %rax,%rdi\ncallq 1060 \nmov %eax,-0x8(%rbp)\nmov -0x20(%rbp),%rax\nmov %rax,%rdi\ncallq 1060 \nmov %eax,-0x4(%rbp)\nmov -0x8(%rbp),%eax\ncltd\nidivl -0x4(%rbp)\nmov %edx,%eax\ntest %eax,%eax\nje 11af \nmov $0x0,%eax\njmp 11fa \nmovl $0x0,-0xc(%rbp)\njmp 11ed \nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%ecx\nmov -0xc(%rbp),%eax\ncltd\nidivl -0x4(%rbp)\nmov %edx,%eax\nmovslq %eax,%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ncmp %al,%cl\nje 11e9 \nmov $0x0,%eax\njmp 11fa \naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x8(%rbp),%eax\njl 11b8 \nmov $0x1,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov [rbp+var_20], rsi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_8], eax\nmov rax, [rbp+var_20]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov eax, [rbp+var_8]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njz short loc_11AF\nmov eax, 0\njmp short locret_11FA\nloc_11AF:\nmov [rbp+var_C], 0\njmp short loc_11ED\nloc_11B8:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx ecx, byte ptr [rax]\nmov eax, [rbp+var_C]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\nmovsxd rdx, eax\nmov rax, [rbp+var_20]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp cl, al\njz short loc_11E9\nmov eax, 0\njmp short locret_11FA\nloc_11E9:\nadd [rbp+var_C], 1\nloc_11ED:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_8]\njl short loc_11B8\nmov eax, 1\nlocret_11FA:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, const char *a2)\n{\n int i; // [rsp+14h] [rbp-Ch]\n int v4; // [rsp+18h] [rbp-8h]\n int v5; // [rsp+1Ch] [rbp-4h]\n\n v4 = strlen(a1);\n v5 = strlen(a2);\n if ( v4 % v5 )\n return 0LL;\n for ( i = 0; i < v4; ++i )\n {\n if ( a1[i] != a2[i % v5] )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov [rbp+var_20], rsi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_8], eax\nmov rax, [rbp+var_20]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov eax, [rbp+var_8]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njz short loc_11AF\nmov eax, 0\njmp short locret_11FA\nloc_11AF:\nmov [rbp+var_C], 0\njmp short loc_11ED\nloc_11B8:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx ecx, byte ptr [rax]\nmov eax, [rbp+var_C]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\nmovsxd rdx, eax\nmov rax, [rbp+var_20]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ncmp cl, al\njz short loc_11E9\nmov eax, 0\njmp short locret_11FA\nloc_11E9:\nadd [rbp+var_C], 1\nloc_11ED:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_8]\njl short loc_11B8\nmov eax, 1\nlocret_11FA:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1, const char *a2)\n{\n int i; // [rsp+14h] [rbp-Ch]\n int v4; // [rsp+18h] [rbp-8h]\n int v5; // [rsp+1Ch] [rbp-4h]\n\n v4 = strlen(a1);\n v5 = strlen(a2);\n if ( v4 % v5 )\n return 0LL;\n for ( i = 0; i < v4; ++i )\n {\n if ( a1[i] != a2[i % v5] )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1, const char *a2) {\n int i;\n int v4;\n int v5;\n v4 = strlen(a1);\n v5 = strlen(a2);\n if (v4 % v5) return 0LL;\n for (i = 0; i < v4; ++i) {\n if (a1[i] != a2[i % v5]) return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, const char *a2) {\n int i;\n int v4;\n int v5;\n v4 = strlen(a1);\n v5 = strlen(a2);\n if (v4 % v5) return 0LL;\n for (i = 0; i < v4; ++i) {\n if (a1[i] != a2[i % v5]) return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": 874, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char* str1, const char* str2) {\n int N = strlen(str1);\n int M = strlen(str2);\n if (N % M != 0) {\n return false;\n }\n for (int i = 0; i < N; i++) {\n if (str1[i] != str2[i % M]) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n assert(func0(\"abcabcabc\", \"abc\") == true);\n\n assert(func0(\"abcab\", \"abc\") == false);\n\n assert(func0(\"aba\", \"ab\") == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%r8\nmov $0xffffffffffffffff,%rdx\nmov $0x0,%eax\nmov %rdx,%rcx\nrepnz scas %es:(%rdi),%al\nnot %rcx\nlea -0x1(%rcx),%r9\nmov %rdx,%rcx\nmov %rsi,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%edi\nmov %r9d,%eax\ncltd\nidiv %edi\nmov $0x0,%eax\ntest %edx,%edx\njne 11c7 \ntest %r9d,%r9d\njle 11bc \nlea -0x1(%r9),%r9d\nmov $0x0,%ecx\njmp 119b \nmov %rax,%rcx\nmov %ecx,%eax\ncltd\nidiv %edi\nmovslq %edx,%rdx\nmovzbl (%rsi,%rdx,1),%eax\ncmp %al,(%r8,%rcx,1)\njne 11c2 \nlea 0x1(%rcx),%rax\ncmp %r9,%rcx\njne 1198 \nmov $0x1,%eax\nretq\nmov $0x1,%eax\nretq\nmov $0x0,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov rbp, rsi\ncall _strlen\nmov r12, rax\nmov rdi, rbp; s\ncall _strlen\nmov esi, eax\nmov eax, r12d\ncdq\nidiv esi\nmov eax, 0\ntest edx, edx\njnz short loc_11E0\ntest r12d, r12d\njle short loc_11D4\nlea edi, [r12-1]\nmov ecx, 0\njmp short loc_11B2\nloc_11AF:\nmov rcx, rax\nloc_11B2:\nmov eax, ecx\ncdq\nidiv esi\nmovsxd rdx, edx\nmovzx eax, byte ptr [rbp+rdx+0]\ncmp [rbx+rcx], al\njnz short loc_11DB\nlea rax, [rcx+1]\ncmp rcx, rdi\njnz short loc_11AF\nmov eax, 1\njmp short loc_11E0\nloc_11D4:\nmov eax, 1\njmp short loc_11E0\nloc_11DB:\nmov eax, 0\nloc_11E0:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, const char *a2)\n{\n int v3; // r12d\n int v4; // esi\n __int64 result; // rax\n __int64 i; // rcx\n\n v3 = strlen(a1);\n v4 = strlen(a2);\n result = 0LL;\n if ( !(v3 % v4) )\n {\n if ( v3 <= 0 )\n {\n return 1LL;\n }\n else\n {\n for ( i = 0LL; a1[i] == a2[(int)i % v4]; ++i )\n {\n if ( i == v3 - 1 )\n return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov rbp, rsi\ncall _strlen\nmov r12, rax\nmov rdi, rbp; s\ncall _strlen\nmov esi, eax\nmov eax, r12d\ncdq\nidiv esi\nmov eax, 0\ntest edx, edx\njnz short loc_11E0\ntest r12d, r12d\njle short loc_11D4\nlea edi, [r12-1]\nmov ecx, 0\njmp short loc_11B2\nloc_11AF:\nmov rcx, rax\nloc_11B2:\nmov eax, ecx\ncdq\nidiv esi\nmovsxd rdx, edx\nmovzx eax, byte ptr [rbp+rdx+0]\ncmp [rbx+rcx], al\njnz short loc_11DB\nlea rax, [rcx+1]\ncmp rcx, rdi\njnz short loc_11AF\nmov eax, 1\njmp short loc_11E0\nloc_11D4:\nmov eax, 1\njmp short loc_11E0\nloc_11DB:\nmov eax, 0\nloc_11E0:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(const char *a1, const char *a2)\n{\n int v3; // r12d\n int v4; // esi\n __int64 result; // rax\n __int64 i; // rcx\n\n v3 = strlen(a1);\n v4 = strlen(a2);\n result = 0LL;\n if ( !(v3 % v4) )\n {\n if ( v3 <= 0 )\n {\n return 1LL;\n }\n else\n {\n for ( i = 0LL; a1[i] == a2[(int)i % v4]; ++i )\n {\n if ( i == v3 - 1 )\n return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(const char *a1, const char *a2) {\n int v3;\n int v4;\n long long result;\n long long i;\n v3 = strlen(a1);\n v4 = strlen(a2);\n result = 0LL;\n if (!(v3 % v4)) {\n if (v3 <= 0) {\n return 1LL;\n } else {\n for (i = 0LL; a1[i] == a2[(int)i % v4]; ++i) {\n if (i == v3 - 1) return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, const char *a2) {\n int v3;\n int v4;\n long long result;\n long long i;\n v3 = strlen(a1);\n v4 = strlen(a2);\n result = 0LL;\n if (!(v3 % v4)) {\n if (v3 <= 0) {\n return 1LL;\n } else {\n for (i = 0LL; a1[i] == a2[(int)i % v4]; ++i) {\n if (i == v3 - 1) return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}" + }, + { + "index": 874, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char* str1, const char* str2) {\n int N = strlen(str1);\n int M = strlen(str2);\n if (N % M != 0) {\n return false;\n }\n for (int i = 0; i < N; i++) {\n if (str1[i] != str2[i % M]) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n assert(func0(\"abcabcabc\", \"abc\") == true);\n\n assert(func0(\"abcab\", \"abc\") == false);\n\n assert(func0(\"aba\", \"ab\") == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\nmov %rsi,%rbp\npush %rbx\nmov %rdi,%rbx\nsub $0x8,%rsp\ncallq 1060 \nmov %rbp,%rdi\nmov %rax,%r12\ncallq 1060 \nmov %eax,%edi\nmov %r12d,%eax\ncltd\nidiv %edi\nxor %eax,%eax\ntest %edx,%edx\njne 1290 \ntest %r12d,%r12d\njle 12a0 \nlea -0x1(%r12),%esi\nxor %ecx,%ecx\njmp 127c \nlea 0x1(%rcx),%rax\ncmp %rsi,%rcx\nje 12a0 \nmov %rax,%rcx\nmov %ecx,%eax\ncltd\nidiv %edi\nmovslq %edx,%rdx\nmovzbl 0x0(%rbp,%rdx,1),%eax\ncmp %al,(%rbx,%rcx,1)\nje 1270 \nxor %eax,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax,%rax,1)\nadd $0x8,%rsp\nmov $0x1,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\nmov rbp, rsi\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\nmov rdi, rbp; s\nmov r12, rax\ncall _strlen\nmov esi, eax\nmov eax, r12d\ncdq\nidiv esi\nxor eax, eax\ntest edx, edx\njnz short loc_1280\ntest r12d, r12d\njle short loc_1290\nlea edi, [r12-1]\nxor ecx, ecx\njmp short loc_126C\nloc_1260:\nlea rax, [rcx+1]\ncmp rcx, rdi\njz short loc_1290\nmov rcx, rax\nloc_126C:\nmov eax, ecx\ncdq\nidiv esi\nmovsxd rdx, edx\nmovzx eax, byte ptr [rbp+rdx+0]\ncmp [rbx+rcx], al\njz short loc_1260\nxor eax, eax\nloc_1280:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1290:\nadd rsp, 8\nmov eax, 1\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, const char *a2)\n{\n int v3; // r12d\n int v4; // esi\n __int64 result; // rax\n __int64 i; // rcx\n\n v3 = strlen(a1);\n v4 = strlen(a2);\n result = 0LL;\n if ( !(v3 % v4) )\n {\n if ( v3 <= 0 )\n {\n return 1LL;\n }\n else\n {\n for ( i = 0LL; a1[i] == a2[(int)i % v4]; ++i )\n {\n if ( i == v3 - 1 )\n return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1220:\nendbr64\npush r13\npush r12\npush rbp\nmov rbp, rsi\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\nmov rdi, rbp; s\nmov r12, rax\ncall _strlen\nmov esi, eax\nmov eax, r12d\ncdq\nidiv esi\nxor eax, eax\ntest edx, edx\njnz short loc_1280\ntest r12d, r12d\njle short loc_1290\nlea edi, [r12-1]\nxor ecx, ecx\njmp short loc_126C\nloc_1260:\nlea rax, [rcx+1]\ncmp rcx, rdi\njz short loc_1290\nmov rcx, rax\nloc_126C:\nmov eax, ecx\ncdq\nidiv esi\nmovsxd rdx, edx\nmovzx eax, byte ptr [rbp+rdx+0]\ncmp [rbx+rcx], al\njz short loc_1260\nxor eax, eax\nloc_1280:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1290:\nadd rsp, 8\nmov eax, 1\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1220(const char *a1, const char *a2)\n{\n int v3; // r12d\n int v4; // esi\n __int64 result; // rax\n __int64 i; // rcx\n\n v3 = strlen(a1);\n v4 = strlen(a2);\n result = 0LL;\n if ( !(v3 % v4) )\n {\n if ( v3 <= 0 )\n {\n return 1LL;\n }\n else\n {\n for ( i = 0LL; a1[i] == a2[(int)i % v4]; ++i )\n {\n if ( i == v3 - 1 )\n return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1220(const char *a1, const char *a2) {\n int v3;\n int v4;\n long long result;\n long long i;\n v3 = strlen(a1);\n v4 = strlen(a2);\n result = 0LL;\n if (!(v3 % v4)) {\n if (v3 <= 0) {\n return 1LL;\n } else {\n for (i = 0LL; a1[i] == a2[(int)i % v4]; ++i) {\n if (i == v3 - 1) return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, const char *a2) {\n int v3;\n int v4;\n long long result;\n long long i;\n v3 = strlen(a1);\n v4 = strlen(a2);\n result = 0LL;\n if (!(v3 % v4)) {\n if (v3 <= 0) {\n return 1LL;\n } else {\n for (i = 0LL; a1[i] == a2[(int)i % v4]; ++i) {\n if (i == v3 - 1) return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}" + }, + { + "index": 874, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char* str1, const char* str2) {\n int N = strlen(str1);\n int M = strlen(str2);\n if (N % M != 0) {\n return false;\n }\n for (int i = 0; i < N; i++) {\n if (str1[i] != str2[i % M]) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n assert(func0(\"abcabcabc\", \"abc\") == true);\n\n assert(func0(\"abcab\", \"abc\") == false);\n\n assert(func0(\"aba\", \"ab\") == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\nmov %rsi,%rbp\npush %rbx\nmov %rdi,%rbx\nsub $0x8,%rsp\ncallq 1060 \nmov %rbp,%rdi\nmov %rax,%r12\ncallq 1060 \nmov %eax,%edi\nmov %r12d,%eax\ncltd\nidiv %edi\nxor %eax,%eax\ntest %edx,%edx\njne 1290 \ntest %r12d,%r12d\njle 12a0 \nlea -0x1(%r12),%esi\nxor %ecx,%ecx\njmp 127c \nlea 0x1(%rcx),%rax\ncmp %rsi,%rcx\nje 12a0 \nmov %rax,%rcx\nmov %ecx,%eax\ncltd\nidiv %edi\nmovslq %edx,%rdx\nmovzbl 0x0(%rbp,%rdx,1),%eax\ncmp %al,(%rbx,%rcx,1)\nje 1270 \nxor %eax,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax,%rax,1)\nadd $0x8,%rsp\nmov $0x1,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\nmov rbp, rsi\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\nmov rdi, rbp; s\nmov r12, rax\ncall _strlen\nmov esi, eax\nmov eax, r12d\ncdq\nidiv esi\nxor eax, eax\ntest edx, edx\njnz short loc_1280\ntest r12d, r12d\njle short loc_1290\nlea edi, [r12-1]\nxor ecx, ecx\njmp short loc_126C\nloc_1260:\nlea rax, [rcx+1]\ncmp rcx, rdi\njz short loc_1290\nmov rcx, rax\nloc_126C:\nmov eax, ecx\ncdq\nidiv esi\nmovsxd rdx, edx\nmovzx eax, byte ptr [rbp+rdx+0]\ncmp [rbx+rcx], al\njz short loc_1260\nxor eax, eax\nloc_1280:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1290:\nadd rsp, 8\nmov eax, 1\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, const char *a2)\n{\n int v3; // r12d\n int v4; // esi\n __int64 result; // rax\n __int64 i; // rcx\n\n v3 = strlen(a1);\n v4 = strlen(a2);\n result = 0LL;\n if ( !(v3 % v4) )\n {\n if ( v3 <= 0 )\n {\n return 1LL;\n }\n else\n {\n for ( i = 0LL; a1[i] == a2[(int)i % v4]; ++i )\n {\n if ( i == v3 - 1 )\n return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1220:\nendbr64\npush r13\npush r12\npush rbp\nmov rbp, rsi\npush rbx\nmov rbx, rdi\nsub rsp, 8\ncall _strlen\nmov rdi, rbp; s\nmov r12, rax\ncall _strlen\nmov esi, eax\nmov eax, r12d\ncdq\nidiv esi\nxor eax, eax\ntest edx, edx\njnz short loc_1280\ntest r12d, r12d\njle short loc_1290\nlea edi, [r12-1]\nxor ecx, ecx\njmp short loc_126C\nloc_1260:\nlea rax, [rcx+1]\ncmp rcx, rdi\njz short loc_1290\nmov rcx, rax\nloc_126C:\nmov eax, ecx\ncdq\nidiv esi\nmovsxd rdx, edx\nmovzx eax, byte ptr [rbp+rdx+0]\ncmp [rbx+rcx], al\njz short loc_1260\nxor eax, eax\nloc_1280:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1290:\nadd rsp, 8\nmov eax, 1\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1220(const char *a1, const char *a2)\n{\n int v3; // r12d\n int v4; // esi\n __int64 result; // rax\n __int64 i; // rcx\n\n v3 = strlen(a1);\n v4 = strlen(a2);\n result = 0LL;\n if ( !(v3 % v4) )\n {\n if ( v3 <= 0 )\n {\n return 1LL;\n }\n else\n {\n for ( i = 0LL; a1[i] == a2[(int)i % v4]; ++i )\n {\n if ( i == v3 - 1 )\n return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1220(const char *a1, const char *a2) {\n int v3;\n int v4;\n long long result;\n long long i;\n v3 = strlen(a1);\n v4 = strlen(a2);\n result = 0LL;\n if (!(v3 % v4)) {\n if (v3 <= 0) {\n return 1LL;\n } else {\n for (i = 0LL; a1[i] == a2[(int)i % v4]; ++i) {\n if (i == v3 - 1) return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, const char *a2) {\n int v3;\n int v4;\n long long result;\n long long i;\n v3 = strlen(a1);\n v4 = strlen(a2);\n result = 0LL;\n if (!(v3 % v4)) {\n if (v3 <= 0) {\n return 1LL;\n } else {\n for (i = 0LL; a1[i] == a2[(int)i % v4]; ++i) {\n if (i == v3 - 1) return 1LL;\n }\n return 0LL;\n }\n }\n return result;\n}" + }, + { + "index": 875, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int test_list[][2], int len) {\n int* temp = (int*)malloc(sizeof(int) * len);\n for (int i = 0; i < len; i++) {\n temp[i] = abs(test_list[i][1] - test_list[i][0]);\n }\n int res = temp[0];\n for (int i = 1; i < len; i++) {\n if (temp[i] < res) {\n res = temp[i];\n }\n }\n free(temp);\n return res;\n}", + "test": "int main() {\n\n int arr1[][2] = {{3, 5}, {1, 7}, {10, 3}, {1, 2}};\n\n int arr2[][2] = {{4, 6}, {12, 8}, {11, 4}, {2, 13}};\n\n int arr3[][2] = {{5, 17}, {3, 9}, {12, 5}, {3, 24}};\n\n \n\n assert(func0(arr1, 4) == 1);\n\n assert(func0(arr2, 4) == 2);\n\n assert(func0(arr3, 4) == 6);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmov -0x2c(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0x14(%rbp)\njmp 122b \nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov 0x4(%rax),%edx\nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\nsub %eax,%edx\nmov %edx,%eax\nmov -0x14(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x8(%rbp),%rdx\nadd %rdx,%rcx\ncltd\nxor %edx,%eax\nsub %edx,%eax\nmov %eax,(%rcx)\naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 11da \nmov -0x8(%rbp),%rax\nmov (%rax),%eax\nmov %eax,-0x10(%rbp)\nmovl $0x1,-0xc(%rbp)\njmp 127d \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x10(%rbp)\njle 1279 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x10(%rbp)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 1245 \nmov -0x8(%rbp),%rax\nmov %rax,%rdi\ncallq 1080 \nmov -0x10(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov [rbp+var_14], 0\njmp short loc_122C\nloc_11DA:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax+4]\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov edx, [rdx]\nsub eax, edx\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+ptr]\nadd rdx, rcx\nmov ecx, eax\nneg ecx\ncmovns eax, ecx\nmov [rdx], eax\nadd [rbp+var_14], 1\nloc_122C:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl short loc_11DA\nmov rax, [rbp+ptr]\nmov eax, [rax]\nmov [rbp+var_10], eax\nmov [rbp+var_C], 1\njmp short loc_127E\nloc_1246:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_10], eax\njle short loc_127A\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_10], eax\nloc_127A:\nadd [rbp+var_C], 1\nloc_127E:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_2C]\njl short loc_1246\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov eax, [rbp+var_10]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int v2; // eax\n int i; // [rsp+1Ch] [rbp-14h]\n unsigned int v5; // [rsp+20h] [rbp-10h]\n int j; // [rsp+24h] [rbp-Ch]\n unsigned int *ptr; // [rsp+28h] [rbp-8h]\n\n ptr = (unsigned int *)malloc(4LL * a2);\n for ( i = 0; i < a2; ++i )\n {\n v2 = *(_DWORD *)(8LL * i + a1 + 4) - *(_DWORD *)(8LL * i + a1);\n if ( *(_DWORD *)(8LL * i + a1) - *(_DWORD *)(8LL * i + a1 + 4) >= 0 )\n v2 = *(_DWORD *)(8LL * i + a1) - *(_DWORD *)(8LL * i + a1 + 4);\n ptr[i] = v2;\n }\n v5 = *ptr;\n for ( j = 1; j < a2; ++j )\n {\n if ( (int)v5 > (int)ptr[j] )\n v5 = ptr[j];\n }\n free(ptr);\n return v5;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov [rbp+var_14], 0\njmp short loc_122C\nloc_11DA:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax+4]\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov edx, [rdx]\nsub eax, edx\nmov edx, [rbp+var_14]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+ptr]\nadd rdx, rcx\nmov ecx, eax\nneg ecx\ncmovns eax, ecx\nmov [rdx], eax\nadd [rbp+var_14], 1\nloc_122C:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl short loc_11DA\nmov rax, [rbp+ptr]\nmov eax, [rax]\nmov [rbp+var_10], eax\nmov [rbp+var_C], 1\njmp short loc_127E\nloc_1246:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_10], eax\njle short loc_127A\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_10], eax\nloc_127A:\nadd [rbp+var_C], 1\nloc_127E:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_2C]\njl short loc_1246\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov eax, [rbp+var_10]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(__int64 a1, int a2)\n{\n int v2; // eax\n int i; // [rsp+1Ch] [rbp-14h]\n unsigned int v5; // [rsp+20h] [rbp-10h]\n int j; // [rsp+24h] [rbp-Ch]\n unsigned int *ptr; // [rsp+28h] [rbp-8h]\n\n ptr = (unsigned int *)malloc(4LL * a2);\n for ( i = 0; i < a2; ++i )\n {\n v2 = *(_DWORD *)(8LL * i + a1 + 4) - *(_DWORD *)(8LL * i + a1);\n if ( *(_DWORD *)(8LL * i + a1) - *(_DWORD *)(8LL * i + a1 + 4) >= 0 )\n v2 = *(_DWORD *)(8LL * i + a1) - *(_DWORD *)(8LL * i + a1 + 4);\n ptr[i] = v2;\n }\n v5 = *ptr;\n for ( j = 1; j < a2; ++j )\n {\n if ( (int)v5 > (int)ptr[j] )\n v5 = ptr[j];\n }\n free(ptr);\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(long long a1, int a2) {\n int v2;\n int i;\n unsigned int v5;\n int j;\n unsigned int *ptr;\n ptr = (unsigned int *)malloc(4LL * a2);\n for (i = 0; i < a2; ++i) {\n v2 = *(uint32_t *)(8LL * i + a1 + 4) - *(uint32_t *)(8LL * i + a1);\n if (*(uint32_t *)(8LL * i + a1) - *(uint32_t *)(8LL * i + a1 + 4) >= 0)\n v2 = *(uint32_t *)(8LL * i + a1) - *(uint32_t *)(8LL * i + a1 + 4);\n ptr[i] = v2;\n }\n v5 = *ptr;\n for (j = 1; j < a2; ++j) {\n if ((int)v5 > (int)ptr[j]) v5 = ptr[j];\n }\n free(ptr);\n return v5;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int v2;\n int i;\n unsigned int v5;\n int j;\n unsigned int *ptr;\n ptr = (unsigned int *)malloc(4LL * a2);\n for (i = 0; i < a2; ++i) {\n v2 = *(uint32_t *)(8LL * i + a1 + 4) - *(uint32_t *)(8LL * i + a1);\n if (*(uint32_t *)(8LL * i + a1) - *(uint32_t *)(8LL * i + a1 + 4) >= 0)\n v2 = *(uint32_t *)(8LL * i + a1) - *(uint32_t *)(8LL * i + a1 + 4);\n ptr[i] = v2;\n }\n v5 = *ptr;\n for (j = 1; j < a2; ++j) {\n if ((int)v5 > (int)ptr[j]) v5 = ptr[j];\n }\n free(ptr);\n return v5;\n}" + }, + { + "index": 875, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int test_list[][2], int len) {\n int* temp = (int*)malloc(sizeof(int) * len);\n for (int i = 0; i < len; i++) {\n temp[i] = abs(test_list[i][1] - test_list[i][0]);\n }\n int res = temp[0];\n for (int i = 1; i < len; i++) {\n if (temp[i] < res) {\n res = temp[i];\n }\n }\n free(temp);\n return res;\n}", + "test": "int main() {\n\n int arr1[][2] = {{3, 5}, {1, 7}, {10, 3}, {1, 2}};\n\n int arr2[][2] = {{4, 6}, {12, 8}, {11, 4}, {2, 13}};\n\n int arr3[][2] = {{5, 17}, {3, 9}, {12, 5}, {3, 24}};\n\n \n\n assert(func0(arr1, 4) == 1);\n\n assert(func0(arr2, 4) == 2);\n\n assert(func0(arr3, 4) == 6);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbp\nmov %esi,%ebx\nmovslq %esi,%rdi\nshl $0x2,%rdi\ncallq 10b0 \nmov %rax,%rdi\ntest %ebx,%ebx\njle 11f4 \nlea -0x1(%rbx),%esi\nmov $0x0,%edx\nmov 0x4(%rbp,%rdx,8),%ecx\nsub 0x0(%rbp,%rdx,8),%ecx\nmov %ecx,%eax\nsar $0x1f,%eax\nxor %eax,%ecx\nmov %ecx,(%rdi,%rdx,4)\nsub %eax,(%rdi,%rdx,4)\nmov %rdx,%rax\nadd $0x1,%rdx\ncmp %rsi,%rax\njne 11d3 \nmov (%rdi),%ebp\ncmp $0x1,%ebx\njle 1217 \nlea 0x4(%rdi),%rdx\nlea -0x2(%rbx),%eax\nlea 0x8(%rdi,%rax,4),%rcx\nmov (%rdx),%eax\ncmp %eax,%ebp\ncmovg %eax,%ebp\nadd $0x4,%rdx\ncmp %rcx,%rdx\njne 1207 \ncallq 1080 \nmov %ebp,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nmov ebp, esi\nmovsxd r12, esi\nlea rdi, ds:0[r12*4]; size\ncall _malloc\nmov rdi, rax; ptr\ntest ebp, ebp\njle short loc_121B\nmov edx, 0\nloc_11D2:\nmov ecx, [rbx+rdx*8+4]\nsub ecx, [rbx+rdx*8]\nmov esi, ecx\nneg esi\ncmovns ecx, esi\nmov [rdi+rdx*4], ecx\nadd rdx, 1\ncmp r12, rdx\njnz short loc_11D2\nmov ebx, [rdi]\ncmp ebp, 1\njle short loc_120F\nlea rdx, [rdi+4]\nlea eax, [rbp-2]\nlea rax, [rdi+rax*4+8]\nloc_11FF:\nmov ecx, [rdx]\ncmp ebx, ecx\ncmovg ebx, ecx\nadd rdx, 4\ncmp rdx, rax\njnz short loc_11FF\nloc_120F:\ncall _free\nmov eax, ebx\npop rbx\npop rbp\npop r12\nretn\nloc_121B:\nmov ebx, [rax]\njmp short loc_120F", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int *v3; // rax\n unsigned int *v4; // rdi\n __int64 i; // rdx\n int v6; // ecx\n unsigned int v7; // ebx\n unsigned int *v8; // rdx\n __int64 v9; // rax\n\n v3 = (unsigned int *)malloc(4LL * a2);\n v4 = v3;\n if ( a2 <= 0 )\n {\n v7 = *v3;\n }\n else\n {\n for ( i = 0LL; i != a2; v3[i++] = v6 )\n {\n v6 = *(_DWORD *)(a1 + 8 * i + 4) - *(_DWORD *)(a1 + 8 * i);\n if ( *(_DWORD *)(a1 + 8 * i) - *(_DWORD *)(a1 + 8 * i + 4) >= 0 )\n v6 = *(_DWORD *)(a1 + 8 * i) - *(_DWORD *)(a1 + 8 * i + 4);\n }\n v7 = *v3;\n if ( a2 > 1 )\n {\n v8 = v3 + 1;\n v9 = (__int64)&v3[a2 - 2 + 2];\n do\n {\n if ( (int)v7 > (int)*v8 )\n v7 = *v8;\n ++v8;\n }\n while ( v8 != (unsigned int *)v9 );\n }\n }\n free(v4);\n return v7;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nmov ebp, esi\nmovsxd r12, esi\nlea rdi, ds:0[r12*4]; size\ncall _malloc\nmov rdi, rax; ptr\ntest ebp, ebp\njle short loc_121B\nmov edx, 0\nloc_11D2:\nmov ecx, [rbx+rdx*8+4]\nsub ecx, [rbx+rdx*8]\nmov esi, ecx\nneg esi\ncmovns ecx, esi\nmov [rdi+rdx*4], ecx\nadd rdx, 1\ncmp r12, rdx\njnz short loc_11D2\nmov ebx, [rdi]\ncmp ebp, 1\njle short loc_120F\nlea rdx, [rdi+4]\nlea eax, [rbp-2]\nlea rax, [rdi+rax*4+8]\nloc_11FF:\nmov ecx, [rdx]\ncmp ebx, ecx\ncmovg ebx, ecx\nadd rdx, 4\ncmp rdx, rax\njnz short loc_11FF\nloc_120F:\ncall _free\nmov eax, ebx\npop rbx\npop rbp\npop r12\nretn\nloc_121B:\nmov ebx, [rax]\njmp short loc_120F", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(__int64 a1, int a2)\n{\n unsigned int *v3; // rax\n unsigned int *v4; // rdi\n __int64 i; // rdx\n int v6; // ecx\n unsigned int v7; // ebx\n unsigned int *v8; // rdx\n __int64 v9; // rax\n\n v3 = (unsigned int *)malloc(4LL * a2);\n v4 = v3;\n if ( a2 <= 0 )\n {\n v7 = *v3;\n }\n else\n {\n for ( i = 0LL; i != a2; v3[i++] = v6 )\n {\n v6 = *(_DWORD *)(a1 + 8 * i + 4) - *(_DWORD *)(a1 + 8 * i);\n if ( *(_DWORD *)(a1 + 8 * i) - *(_DWORD *)(a1 + 8 * i + 4) >= 0 )\n v6 = *(_DWORD *)(a1 + 8 * i) - *(_DWORD *)(a1 + 8 * i + 4);\n }\n v7 = *v3;\n if ( a2 > 1 )\n {\n v8 = v3 + 1;\n v9 = (__int64)&v3[a2 - 2 + 2];\n do\n {\n if ( (int)v7 > (int)*v8 )\n v7 = *v8;\n ++v8;\n }\n while ( v8 != (unsigned int *)v9 );\n }\n }\n free(v4);\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(long long a1, int a2) {\n unsigned int *v3;\n unsigned int *v4;\n long long i;\n int v6;\n unsigned int v7;\n unsigned int *v8;\n long long v9;\n v3 = (unsigned int *)malloc(4LL * a2);\n v4 = v3;\n if (a2 <= 0) {\n v7 = *v3;\n } else {\n for (i = 0LL; i != a2; v3[i++] = v6) {\n v6 = *(uint32_t *)(a1 + 8 * i + 4) - *(uint32_t *)(a1 + 8 * i);\n if (*(uint32_t *)(a1 + 8 * i) - *(uint32_t *)(a1 + 8 * i + 4) >= 0)\n v6 = *(uint32_t *)(a1 + 8 * i) - *(uint32_t *)(a1 + 8 * i + 4);\n }\n v7 = *v3;\n if (a2 > 1) {\n v8 = v3 + 1;\n v9 = (long long)&v3[a2 - 2 + 2];\n do {\n if ((int)v7 > (int)*v8) v7 = *v8;\n ++v8;\n } while (v8 != (unsigned int *)v9);\n }\n }\n free(v4);\n return v7;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int *v3;\n unsigned int *v4;\n long long i;\n int v6;\n unsigned int v7;\n unsigned int *v8;\n long long v9;\n v3 = (unsigned int *)malloc(4LL * a2);\n v4 = v3;\n if (a2 <= 0) {\n v7 = *v3;\n } else {\n for (i = 0LL; i != a2; v3[i++] = v6) {\n v6 = *(uint32_t *)(a1 + 8 * i + 4) - *(uint32_t *)(a1 + 8 * i);\n if (*(uint32_t *)(a1 + 8 * i) - *(uint32_t *)(a1 + 8 * i + 4) >= 0)\n v6 = *(uint32_t *)(a1 + 8 * i) - *(uint32_t *)(a1 + 8 * i + 4);\n }\n v7 = *v3;\n if (a2 > 1) {\n v8 = v3 + 1;\n v9 = (long long)&v3[a2 - 2 + 2];\n do {\n if ((int)v7 > (int)*v8) v7 = *v8;\n ++v8;\n } while (v8 != (unsigned int *)v9);\n }\n }\n free(v4);\n return v7;\n}" + }, + { + "index": 875, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int test_list[][2], int len) {\n int* temp = (int*)malloc(sizeof(int) * len);\n for (int i = 0; i < len; i++) {\n temp[i] = abs(test_list[i][1] - test_list[i][0]);\n }\n int res = temp[0];\n for (int i = 1; i < len; i++) {\n if (temp[i] < res) {\n res = temp[i];\n }\n }\n free(temp);\n return res;\n}", + "test": "int main() {\n\n int arr1[][2] = {{3, 5}, {1, 7}, {10, 3}, {1, 2}};\n\n int arr2[][2] = {{4, 6}, {12, 8}, {11, 4}, {2, 13}};\n\n int arr3[][2] = {{5, 17}, {3, 9}, {12, 5}, {3, 24}};\n\n \n\n assert(func0(arr1, 4) == 1);\n\n assert(func0(arr2, 4) == 2);\n\n assert(func0(arr3, 4) == 6);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %rdi,%r12\nmovslq %esi,%rdi\npush %rbx\nmov %rdi,%rbx\nshl $0x2,%rdi\nsub $0x8,%rsp\ncallq 10b0 \nmov %rax,%rdi\ntest %ebx,%ebx\njle 13c8 \nlea -0x1(%rbx),%r8d\nxor %edx,%edx\nnopw 0x0(%rax,%rax,1)\nmov 0x4(%r12,%rdx,8),%ecx\nsub (%r12,%rdx,8),%ecx\nmov %ecx,%eax\nsar $0x1f,%eax\nxor %eax,%ecx\nmov %ecx,(%rdi,%rdx,4)\nsub %eax,(%rdi,%rdx,4)\nmov %rdx,%rax\nadd $0x1,%rdx\ncmp %r8,%rax\njne 1360 \nmov (%rdi),%r12d\ncmp $0x1,%ebx\njle 13b2 \nlea -0x2(%rbx),%eax\nlea 0x4(%rdi),%rdx\nlea 0x8(%rdi,%rax,4),%rcx\nnopw %cs:0x0(%rax,%rax,1)\nmov (%rdx),%eax\ncmp %eax,%r12d\ncmovg %eax,%r12d\nadd $0x4,%rdx\ncmp %rdx,%rcx\njne 13a0 \ncallq 1080 \nadd $0x8,%rsp\nmov %r12d,%eax\npop %rbx\npop %r12\nretq\nnopw 0x0(%rax,%rax,1)\nmov (%rax),%r12d\ncallq 1080 \nadd $0x8,%rsp\nmov %r12d,%eax\npop %rbx\npop %r12\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\nmovsxd rbp, esi\npush rbx\nmov rbx, rdi\nlea rdi, ds:0[rbp*4]; size\ncall _malloc\nmov rdi, rax; ptr\ntest ebp, ebp\njle loc_1378\nmov r12, rbp\nxor eax, eax\nnop dword ptr [rax+rax+00h]\nloc_1300:\nmov edx, [rbx+rax*8+4]\nsub edx, [rbx+rax*8]\nmov ecx, edx\nneg ecx\ncmovns edx, ecx\nmov [rdi+rax*4], edx\nadd rax, 1\ncmp rbp, rax\njnz short loc_1300\nmov ebx, [rdi]\ncmp r12d, 1\njz short loc_1368\nlea edx, [r12-2]\nlea rax, [rdi+4]\nlea rcx, [rdi+rdx*4+8]\nmov rdx, rcx\nsub rdx, rax\nand edx, 4\njz short loc_1350\nmov eax, [rax]\ncmp ebx, eax\ncmovg ebx, eax\nlea rax, [rdi+8]\ncmp rcx, rax\njz short loc_1368\nnop dword ptr [rax+rax+00h]\nloc_1350:\nmov edx, [rax]\ncmp ebx, edx\ncmovg ebx, edx\nmov edx, [rax+4]\ncmp ebx, edx\ncmovg ebx, edx\nadd rax, 8\ncmp rcx, rax\njnz short loc_1350\nloc_1368:\ncall _free\nmov eax, ebx\npop rbx\npop rbp\npop r12\nretn\nloc_1378:\nmov ebx, [rax]\ncall _free\nmov eax, ebx\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n signed int *v3; // rax\n signed int *v4; // rdi\n __int64 i; // rax\n int v6; // edx\n signed int v7; // ebx\n signed int *v8; // rax\n __int64 v9; // rcx\n int v10; // eax\n unsigned int v12; // ebx\n\n v3 = (signed int *)malloc(4LL * a2);\n v4 = v3;\n if ( a2 <= 0 )\n {\n v12 = *v3;\n free(v3);\n return v12;\n }\n else\n {\n for ( i = 0LL; i != a2; v4[i++] = v6 )\n {\n v6 = *(_DWORD *)(a1 + 8 * i + 4) - *(_DWORD *)(a1 + 8 * i);\n if ( *(_DWORD *)(a1 + 8 * i) - *(_DWORD *)(a1 + 8 * i + 4) >= 0 )\n v6 = *(_DWORD *)(a1 + 8 * i) - *(_DWORD *)(a1 + 8 * i + 4);\n }\n v7 = *v4;\n if ( a2 != 1 )\n {\n v8 = v4 + 1;\n v9 = (__int64)&v4[a2 - 2 + 2];\n if ( ((4 * ((_BYTE)a2 - 2) + 4) & 4) == 0 )\n goto LABEL_20;\n v10 = *v8;\n if ( v7 > v10 )\n v7 = v10;\n v8 = v4 + 2;\n if ( (signed int *)v9 != v4 + 2 )\n {\nLABEL_20:\n do\n {\n if ( v7 > *v8 )\n v7 = *v8;\n if ( v7 > v8[1] )\n v7 = v8[1];\n v8 += 2;\n }\n while ( (signed int *)v9 != v8 );\n }\n }\n free(v4);\n return (unsigned int)v7;\n }\n}", + "ida_strip_asm": "sub_12D0:\nendbr64\npush r12\npush rbp\nmovsxd rbp, esi\npush rbx\nmov rbx, rdi\nlea rdi, ds:0[rbp*4]; size\ncall _malloc\nmov rdi, rax; ptr\ntest ebp, ebp\njle loc_1378\nmov r12, rbp\nxor eax, eax\nnop dword ptr [rax+rax+00h]\nloc_1300:\nmov edx, [rbx+rax*8+4]\nsub edx, [rbx+rax*8]\nmov ecx, edx\nneg ecx\ncmovns edx, ecx\nmov [rdi+rax*4], edx\nadd rax, 1\ncmp rbp, rax\njnz short loc_1300\nmov ebx, [rdi]\ncmp r12d, 1\njz short loc_1368\nlea edx, [r12-2]\nlea rax, [rdi+4]\nlea rcx, [rdi+rdx*4+8]\nmov rdx, rcx\nsub rdx, rax\nand edx, 4\njz short loc_1350\nmov eax, [rax]\ncmp ebx, eax\ncmovg ebx, eax\nlea rax, [rdi+8]\ncmp rcx, rax\njz short loc_1368\nnop dword ptr [rax+rax+00h]\nloc_1350:\nmov edx, [rax]\ncmp ebx, edx\ncmovg ebx, edx\nmov edx, [rax+4]\ncmp ebx, edx\ncmovg ebx, edx\nadd rax, 8\ncmp rcx, rax\njnz short loc_1350\nloc_1368:\ncall _free\nmov eax, ebx\npop rbx\npop rbp\npop r12\nretn\nloc_1378:\nmov ebx, [rax]\ncall _free\nmov eax, ebx\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12D0(__int64 a1, int a2)\n{\n signed int *v3; // rax\n signed int *v4; // rdi\n __int64 i; // rax\n int v6; // edx\n signed int v7; // ebx\n signed int *v8; // rax\n __int64 v9; // rcx\n int v10; // eax\n unsigned int v12; // ebx\n\n v3 = (signed int *)malloc(4LL * a2);\n v4 = v3;\n if ( a2 <= 0 )\n {\n v12 = *v3;\n free(v3);\n return v12;\n }\n else\n {\n for ( i = 0LL; i != a2; v4[i++] = v6 )\n {\n v6 = *(_DWORD *)(a1 + 8 * i + 4) - *(_DWORD *)(a1 + 8 * i);\n if ( *(_DWORD *)(a1 + 8 * i) - *(_DWORD *)(a1 + 8 * i + 4) >= 0 )\n v6 = *(_DWORD *)(a1 + 8 * i) - *(_DWORD *)(a1 + 8 * i + 4);\n }\n v7 = *v4;\n if ( a2 != 1 )\n {\n v8 = v4 + 1;\n v9 = (__int64)&v4[a2 - 2 + 2];\n if ( ((4 * ((_BYTE)a2 - 2) + 4) & 4) == 0 )\n goto LABEL_20;\n v10 = *v8;\n if ( v7 > v10 )\n v7 = v10;\n v8 = v4 + 2;\n if ( (signed int *)v9 != v4 + 2 )\n {\nLABEL_20:\n do\n {\n if ( v7 > *v8 )\n v7 = *v8;\n if ( v7 > v8[1] )\n v7 = v8[1];\n v8 += 2;\n }\n while ( (signed int *)v9 != v8 );\n }\n }\n free(v4);\n return (unsigned int)v7;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12D0(long long a1, int a2) {\n signed int *v3;\n signed int *v4;\n long long i;\n int v6;\n signed int v7;\n signed int *v8;\n long long v9;\n int v10;\n unsigned int v12;\n v3 = (signed int *)malloc(4LL * a2);\n v4 = v3;\n if (a2 <= 0) {\n v12 = *v3;\n free(v3);\n return v12;\n } else {\n for (i = 0LL; i != a2; v4[i++] = v6) {\n v6 = *(uint32_t *)(a1 + 8 * i + 4) - *(uint32_t *)(a1 + 8 * i);\n if (*(uint32_t *)(a1 + 8 * i) - *(uint32_t *)(a1 + 8 * i + 4) >= 0)\n v6 = *(uint32_t *)(a1 + 8 * i) - *(uint32_t *)(a1 + 8 * i + 4);\n }\n v7 = *v4;\n if (a2 != 1) {\n v8 = v4 + 1;\n v9 = (long long)&v4[a2 - 2 + 2];\n if (((4 * ((uint8_t)a2 - 2) + 4) & 4) == 0) goto LABEL_20;\n v10 = *v8;\n if (v7 > v10) v7 = v10;\n v8 = v4 + 2;\n if ((signed int *)v9 != v4 + 2) {\n LABEL_20:\n do {\n if (v7 > *v8) v7 = *v8;\n if (v7 > v8[1]) v7 = v8[1];\n v8 += 2;\n } while ((signed int *)v9 != v8);\n }\n }\n free(v4);\n return (unsigned int)v7;\n }\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n signed int *v3;\n signed int *v4;\n long long i;\n int v6;\n signed int v7;\n signed int *v8;\n long long v9;\n int v10;\n unsigned int v12;\n v3 = (signed int *)malloc(4LL * a2);\n v4 = v3;\n if (a2 <= 0) {\n v12 = *v3;\n free(v3);\n return v12;\n } else {\n for (i = 0LL; i != a2; v4[i++] = v6) {\n v6 = *(uint32_t *)(a1 + 8 * i + 4) - *(uint32_t *)(a1 + 8 * i);\n if (*(uint32_t *)(a1 + 8 * i) - *(uint32_t *)(a1 + 8 * i + 4) >= 0)\n v6 = *(uint32_t *)(a1 + 8 * i) - *(uint32_t *)(a1 + 8 * i + 4);\n }\n v7 = *v4;\n if (a2 != 1) {\n v8 = v4 + 1;\n v9 = (long long)&v4[a2 - 2 + 2];\n if (((4 * ((uint8_t)a2 - 2) + 4) & 4) == 0) goto LABEL_20;\n v10 = *v8;\n if (v7 > v10) v7 = v10;\n v8 = v4 + 2;\n if ((signed int *)v9 != v4 + 2) {\n LABEL_20:\n do {\n if (v7 > *v8) v7 = *v8;\n if (v7 > v8[1]) v7 = v8[1];\n v8 += 2;\n } while ((signed int *)v9 != v8);\n }\n }\n free(v4);\n return (unsigned int)v7;\n }\n}" + }, + { + "index": 875, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int test_list[][2], int len) {\n int* temp = (int*)malloc(sizeof(int) * len);\n for (int i = 0; i < len; i++) {\n temp[i] = abs(test_list[i][1] - test_list[i][0]);\n }\n int res = temp[0];\n for (int i = 1; i < len; i++) {\n if (temp[i] < res) {\n res = temp[i];\n }\n }\n free(temp);\n return res;\n}", + "test": "int main() {\n\n int arr1[][2] = {{3, 5}, {1, 7}, {10, 3}, {1, 2}};\n\n int arr2[][2] = {{4, 6}, {12, 8}, {11, 4}, {2, 13}};\n\n int arr3[][2] = {{5, 17}, {3, 9}, {12, 5}, {3, 24}};\n\n \n\n assert(func0(arr1, 4) == 1);\n\n assert(func0(arr2, 4) == 2);\n\n assert(func0(arr3, 4) == 6);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %rdi,%r12\nmovslq %esi,%rdi\npush %rbx\nmov %rdi,%rbx\nshl $0x2,%rdi\nsub $0x8,%rsp\ncallq 10b0 \nmov %rax,%rdi\ntest %ebx,%ebx\njle 14a0 \nlea -0x1(%rbx),%ecx\ncmp $0x2,%ecx\njbe 14b3 \nmov %ebx,%eax\nxor %edx,%edx\nshr $0x2,%eax\nshl $0x4,%rax\nmovdqu (%r12,%rdx,2),%xmm1\nmovdqu 0x10(%r12,%rdx,2),%xmm3\nmovdqa %xmm1,%xmm0\nshufps $0x88,%xmm3,%xmm1\nshufps $0xdd,%xmm3,%xmm0\npsubd %xmm1,%xmm0\nmovdqa %xmm0,%xmm1\npsrad $0x1f,%xmm1\npxor %xmm1,%xmm0\npsubd %xmm1,%xmm0\nmovups %xmm0,(%rdi,%rdx,1)\nadd $0x10,%rdx\ncmp %rax,%rdx\njne 1310 \nmov %ebx,%eax\nand $0xfffffffc,%eax\ntest $0x3,%bl\nje 13b9 \nmovslq %eax,%rsi\nmov 0x4(%r12,%rsi,8),%edx\nsub (%r12,%rsi,8),%edx\nmov %edx,%r8d\nsar $0x1f,%r8d\nxor %r8d,%edx\nmov %edx,(%rdi,%rsi,4)\nlea 0x1(%rax),%edx\nsub %r8d,(%rdi,%rsi,4)\ncmp %edx,%ebx\njle 14c1 \nmovslq %edx,%rdx\nadd $0x2,%eax\nmov 0x4(%r12,%rdx,8),%esi\nsub (%r12,%rdx,8),%esi\nmov %esi,%r8d\nsar $0x1f,%r8d\nxor %r8d,%esi\nmov %esi,(%rdi,%rdx,4)\nsub %r8d,(%rdi,%rdx,4)\ncmp %eax,%ebx\njle 13b9 \ncltq\nmov 0x4(%r12,%rax,8),%edx\nsub (%r12,%rax,8),%edx\nmov %edx,%esi\nsar $0x1f,%esi\nxor %esi,%edx\nmov %edx,(%rdi,%rax,4)\nsub %esi,(%rdi,%rax,4)\nmov (%rdi),%r12d\nlea -0x2(%rbx),%eax\ncmp $0x2,%eax\njbe 14ba \nmov %ecx,%eax\nmovd %r12d,%xmm6\nmov %rdi,%rdx\nshr $0x2,%eax\npshufd $0x0,%xmm6,%xmm0\nshl $0x4,%rax\nadd %rdi,%rax\nnopl 0x0(%rax)\nmovdqu 0x4(%rdx),%xmm1\nmovdqu 0x4(%rdx),%xmm5\nadd $0x10,%rdx\npcmpgtd %xmm0,%xmm1\npand %xmm1,%xmm0\npandn %xmm5,%xmm1\npor %xmm1,%xmm0\ncmp %rax,%rdx\njne 13e8 \nmovdqa %xmm0,%xmm2\nmov %ecx,%edx\npsrldq $0x8,%xmm2\nand $0xfffffffc,%edx\nmovdqa %xmm2,%xmm1\nlea 0x1(%rdx),%eax\npcmpgtd %xmm0,%xmm1\npand %xmm1,%xmm0\npandn %xmm2,%xmm1\npor %xmm1,%xmm0\nmovdqa %xmm0,%xmm2\npsrldq $0x4,%xmm2\nmovdqa %xmm2,%xmm1\npcmpgtd %xmm0,%xmm1\npand %xmm1,%xmm0\npandn %xmm2,%xmm1\npor %xmm1,%xmm0\nmovd %xmm0,%r12d\ncmp %ecx,%edx\nje 148a \nmovslq %eax,%rdx\nmov (%rdi,%rdx,4),%edx\ncmp %edx,%r12d\ncmovg %edx,%r12d\nlea 0x1(%rax),%edx\ncmp %ebx,%edx\njge 148a \nmovslq %edx,%rdx\nmov (%rdi,%rdx,4),%edx\ncmp %edx,%r12d\ncmovg %edx,%r12d\nadd $0x2,%eax\ncmp %ebx,%eax\njge 148a \ncltq\nmov (%rdi,%rax,4),%eax\ncmp %eax,%r12d\ncmovg %eax,%r12d\ncallq 1080 \nadd $0x8,%rsp\nmov %r12d,%eax\npop %rbx\npop %r12\nretq\nnopw 0x0(%rax,%rax,1)\nmov (%rax),%r12d\ncallq 1080 \nadd $0x8,%rsp\nmov %r12d,%eax\npop %rbx\npop %r12\nretq\nxor %eax,%eax\njmpq 1355 \nmov $0x1,%eax\njmp 1456 \nmov (%rdi),%r12d\ncmp $0x1,%ebx\njg 13bc \njmp 148a \n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nmov rbx, rdi\nmovsxd rdi, esi\nmov rbp, rdi\nshl rdi, 2; size\nsub rsp, 8\ncall _malloc\nmov rdi, rax; ptr\ntest ebp, ebp\njle loc_14A0\nlea ecx, [rbp-1]\ncmp ecx, 2\njbe loc_14B0\nmov edx, ebp\nxor eax, eax\nshr edx, 2\nshl rdx, 4\nxchg ax, ax\nloc_1310:\nmovdqu xmm1, xmmword ptr [rbx+rax*2]\nmovdqu xmm3, xmmword ptr [rbx+rax*2+10h]\nmovdqa xmm0, xmm1\nshufps xmm1, xmm3, 88h\nshufps xmm0, xmm3, 0DDh\npsubd xmm0, xmm1\nmovdqa xmm1, xmm0\npsrad xmm1, 1Fh\npxor xmm0, xmm1\npsubd xmm0, xmm1\nmovups xmmword ptr [rdi+rax], xmm0\nadd rax, 10h\ncmp rdx, rax\njnz short loc_1310\nmov edx, ebp\nand edx, 0FFFFFFFCh\ntest bpl, 3\njz short loc_13BD\nloc_1354:\nmovsxd rsi, edx\nlea r10, ds:0[rsi*8]\nlea r8, ds:0[rsi*4]\nlea r9, [rbx+r10]\nmov eax, [r9+4]\nsub eax, [r9]\nmov r9d, eax\nneg r9d\ncmovns eax, r9d\nmov [rdi+rsi*4], eax\nlea eax, [rdx+1]\ncmp ebp, eax\njle loc_14BE\nlea rsi, [rbx+r10+8]\nmov eax, [rsi+4]\nsub eax, [rsi]\nmov esi, eax\nneg esi\ncmovns eax, esi\nadd edx, 2\nmov [rdi+r8+4], eax\ncmp ebp, edx\njle short loc_13BD\nlea rdx, [rbx+r10+10h]\nmov eax, [rdx+4]\nsub eax, [rdx]\nmov edx, eax\nneg edx\ncmovns eax, edx\nmov [rdi+r8+8], eax\nloc_13BD:\nmov ebx, [rdi]\nloc_13BF:\nlea eax, [rbp-2]\ncmp eax, 2\njbe loc_14B7\nmov edx, ecx\nmovd xmm6, ebx\nmov rax, rdi\nshr edx, 2\npshufd xmm0, xmm6, 0\nshl rdx, 4\nadd rdx, rdi\nnop dword ptr [rax+rax+00h]\nloc_13E8:\nmovdqu xmm1, xmmword ptr [rax+4]\nmovdqu xmm5, xmmword ptr [rax+4]\nadd rax, 10h\npcmpgtd xmm1, xmm0\npand xmm0, xmm1\npandn xmm1, xmm5\npor xmm0, xmm1\ncmp rax, rdx\njnz short loc_13E8\nmovdqa xmm2, xmm0\nmov eax, ecx\npsrldq xmm2, 8\nand eax, 0FFFFFFFCh\nmovdqa xmm1, xmm2\nadd eax, 1\nand ecx, 3\npcmpgtd xmm1, xmm0\npand xmm0, xmm1\npandn xmm1, xmm2\npor xmm0, xmm1\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\nmovdqa xmm1, xmm2\npcmpgtd xmm1, xmm0\npand xmm0, xmm1\npandn xmm1, xmm2\npor xmm1, xmm0\nmovd ebx, xmm1\njz short loc_1489\nloc_1456:\nmovsxd rdx, eax\nlea rcx, ds:0[rdx*4]\nmov edx, [rdi+rdx*4]\ncmp ebx, edx\ncmovg ebx, edx\nlea edx, [rax+1]\ncmp edx, ebp\njge short loc_1489\nmov edx, [rdi+rcx+4]\ncmp ebx, edx\ncmovg ebx, edx\nadd eax, 2\ncmp eax, ebp\njge short loc_1489\nmov eax, [rdi+rcx+8]\ncmp ebx, eax\ncmovg ebx, eax\nloc_1489:\ncall _free\nadd rsp, 8\nmov eax, ebx\npop rbx\npop rbp\nretn\nloc_14A0:\nmov ebx, [rax]\ncall _free\nadd rsp, 8\nmov eax, ebx\npop rbx\npop rbp\nretn\nloc_14B0:\nxor edx, edx\njmp loc_1354\nloc_14B7:\nmov eax, 1\njmp short loc_1456\nloc_14BE:\nmov ebx, [rdi]\ncmp ebp, 1\njnz loc_13BF\njmp short loc_1489", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n signed int *v3; // rax\n signed int *v4; // rdi\n unsigned int v5; // ecx\n unsigned __int64 v6; // rax\n __m128 v7; // xmm3\n __m128 v8; // xmm0\n __m128i v9; // xmm0\n __m128i v10; // xmm1\n int v11; // edx\n __int64 v12; // r10\n __int64 v13; // r8\n int v14; // eax\n int v15; // eax\n int v16; // eax\n signed int v17; // ebx\n signed int *v18; // rax\n __m128i v19; // xmm0\n __m128i v20; // xmm1\n __m128i v21; // xmm5\n __m128i v22; // xmm1\n __m128i v23; // xmm2\n signed int v24; // eax\n __m128i v25; // xmm1\n __m128i v26; // xmm0\n __m128i v27; // xmm2\n __m128i v28; // xmm1\n __int64 v29; // rcx\n unsigned int v31; // ebx\n\n v3 = (signed int *)malloc(4LL * a2);\n v4 = v3;\n if ( a2 > 0 )\n {\n v5 = a2 - 1;\n if ( (unsigned int)(a2 - 1) <= 2 )\n {\n v11 = 0;\n }\n else\n {\n v6 = 0LL;\n do\n {\n v7 = (__m128)_mm_loadu_si128((const __m128i *)(a1 + 2 * v6 + 16));\n v8 = (__m128)_mm_loadu_si128((const __m128i *)(a1 + 2 * v6));\n v9 = _mm_sub_epi32((__m128i)_mm_shuffle_ps(v8, v7, 221), (__m128i)_mm_shuffle_ps(v8, v7, 136));\n v10 = _mm_srai_epi32(v9, 0x1Fu);\n *(__m128i *)&v4[v6 / 4] = _mm_sub_epi32(_mm_xor_si128(v9, v10), v10);\n v6 += 16LL;\n }\n while ( 16LL * ((unsigned int)a2 >> 2) != v6 );\n v11 = a2 & 0x7FFFFFFC;\n if ( (a2 & 3) == 0 )\n goto LABEL_15;\n }\n v12 = 8LL * v11;\n v13 = v11;\n v14 = *(_DWORD *)(a1 + v12 + 4) - *(_DWORD *)(a1 + v12);\n if ( *(_DWORD *)(a1 + v12) - *(_DWORD *)(a1 + v12 + 4) >= 0 )\n v14 = *(_DWORD *)(a1 + 8LL * v11) - *(_DWORD *)(a1 + 8LL * v11 + 4);\n v4[v11] = v14;\n if ( a2 <= v11 + 1 )\n {\n v17 = *v4;\n if ( a2 == 1 )\n goto LABEL_28;\n goto LABEL_16;\n }\n v15 = *(_DWORD *)(a1 + v12 + 12) - *(_DWORD *)(a1 + v12 + 8);\n if ( *(_DWORD *)(a1 + v12 + 8) - *(_DWORD *)(a1 + v12 + 12) >= 0 )\n v15 = *(_DWORD *)(a1 + v12 + 8) - *(_DWORD *)(a1 + v12 + 12);\n v4[v13 + 1] = v15;\n if ( a2 > v11 + 2 )\n {\n v16 = *(_DWORD *)(a1 + v12 + 20) - *(_DWORD *)(a1 + v12 + 16);\n if ( *(_DWORD *)(a1 + v12 + 16) - *(_DWORD *)(a1 + v12 + 20) >= 0 )\n v16 = *(_DWORD *)(a1 + v12 + 16) - *(_DWORD *)(a1 + v12 + 20);\n v4[v13 + 2] = v16;\n }\nLABEL_15:\n v17 = *v4;\nLABEL_16:\n if ( (unsigned int)(a2 - 2) <= 2 )\n {\n v24 = 1;\nLABEL_20:\n v29 = v24;\n if ( v17 > v4[v29] )\n v17 = v4[v24];\n if ( v24 + 1 < a2 )\n {\n if ( v17 > v4[v29 + 1] )\n v17 = v4[v29 + 1];\n if ( v24 + 2 < a2 && v17 > v4[v29 + 2] )\n v17 = v4[v29 + 2];\n }\n goto LABEL_28;\n }\n v18 = v4;\n v19 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v17), 0);\n do\n {\n v20 = _mm_loadu_si128((const __m128i *)(v18 + 1));\n v21 = v20;\n v18 += 4;\n v22 = _mm_cmpgt_epi32(v20, v19);\n v19 = _mm_or_si128(_mm_and_si128(v19, v22), _mm_andnot_si128(v22, v21));\n }\n while ( v18 != &v4[4 * (v5 >> 2)] );\n v23 = _mm_srli_si128(v19, 8);\n v24 = (v5 & 0xFFFFFFFC) + 1;\n v25 = _mm_cmpgt_epi32(v23, v19);\n v26 = _mm_or_si128(_mm_and_si128(v19, v25), _mm_andnot_si128(v25, v23));\n v27 = _mm_srli_si128(v26, 4);\n v28 = _mm_cmpgt_epi32(v27, v26);\n v17 = _mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v28, v27), _mm_and_si128(v26, v28)));\n if ( (v5 & 3) != 0 )\n goto LABEL_20;\nLABEL_28:\n free(v4);\n return (unsigned int)v17;\n }\n v31 = *v3;\n free(v3);\n return v31;\n}", + "ida_strip_asm": "sub_12D0:\nendbr64\npush rbp\npush rbx\nmov rbx, rdi\nmovsxd rdi, esi\nmov rbp, rdi\nshl rdi, 2; size\nsub rsp, 8\ncall _malloc\nmov rdi, rax; ptr\ntest ebp, ebp\njle loc_14A0\nlea ecx, [rbp-1]\ncmp ecx, 2\njbe loc_14B0\nmov edx, ebp\nxor eax, eax\nshr edx, 2\nshl rdx, 4\nxchg ax, ax\nloc_1310:\nmovdqu xmm1, xmmword ptr [rbx+rax*2]\nmovdqu xmm3, xmmword ptr [rbx+rax*2+10h]\nmovdqa xmm0, xmm1\nshufps xmm1, xmm3, 88h\nshufps xmm0, xmm3, 0DDh\npsubd xmm0, xmm1\nmovdqa xmm1, xmm0\npsrad xmm1, 1Fh\npxor xmm0, xmm1\npsubd xmm0, xmm1\nmovups xmmword ptr [rdi+rax], xmm0\nadd rax, 10h\ncmp rdx, rax\njnz short loc_1310\nmov edx, ebp\nand edx, 0FFFFFFFCh\ntest bpl, 3\njz short loc_13BD\nloc_1354:\nmovsxd rsi, edx\nlea r10, ds:0[rsi*8]\nlea r8, ds:0[rsi*4]\nlea r9, [rbx+r10]\nmov eax, [r9+4]\nsub eax, [r9]\nmov r9d, eax\nneg r9d\ncmovns eax, r9d\nmov [rdi+rsi*4], eax\nlea eax, [rdx+1]\ncmp ebp, eax\njle loc_14BE\nlea rsi, [rbx+r10+8]\nmov eax, [rsi+4]\nsub eax, [rsi]\nmov esi, eax\nneg esi\ncmovns eax, esi\nadd edx, 2\nmov [rdi+r8+4], eax\ncmp ebp, edx\njle short loc_13BD\nlea rdx, [rbx+r10+10h]\nmov eax, [rdx+4]\nsub eax, [rdx]\nmov edx, eax\nneg edx\ncmovns eax, edx\nmov [rdi+r8+8], eax\nloc_13BD:\nmov ebx, [rdi]\nloc_13BF:\nlea eax, [rbp-2]\ncmp eax, 2\njbe loc_14B7\nmov edx, ecx\nmovd xmm6, ebx\nmov rax, rdi\nshr edx, 2\npshufd xmm0, xmm6, 0\nshl rdx, 4\nadd rdx, rdi\nnop dword ptr [rax+rax+00h]\nloc_13E8:\nmovdqu xmm1, xmmword ptr [rax+4]\nmovdqu xmm5, xmmword ptr [rax+4]\nadd rax, 10h\npcmpgtd xmm1, xmm0\npand xmm0, xmm1\npandn xmm1, xmm5\npor xmm0, xmm1\ncmp rax, rdx\njnz short loc_13E8\nmovdqa xmm2, xmm0\nmov eax, ecx\npsrldq xmm2, 8\nand eax, 0FFFFFFFCh\nmovdqa xmm1, xmm2\nadd eax, 1\nand ecx, 3\npcmpgtd xmm1, xmm0\npand xmm0, xmm1\npandn xmm1, xmm2\npor xmm0, xmm1\nmovdqa xmm2, xmm0\npsrldq xmm2, 4\nmovdqa xmm1, xmm2\npcmpgtd xmm1, xmm0\npand xmm0, xmm1\npandn xmm1, xmm2\npor xmm1, xmm0\nmovd ebx, xmm1\njz short loc_1489\nloc_1456:\nmovsxd rdx, eax\nlea rcx, ds:0[rdx*4]\nmov edx, [rdi+rdx*4]\ncmp ebx, edx\ncmovg ebx, edx\nlea edx, [rax+1]\ncmp edx, ebp\njge short loc_1489\nmov edx, [rdi+rcx+4]\ncmp ebx, edx\ncmovg ebx, edx\nadd eax, 2\ncmp eax, ebp\njge short loc_1489\nmov eax, [rdi+rcx+8]\ncmp ebx, eax\ncmovg ebx, eax\nloc_1489:\ncall _free\nadd rsp, 8\nmov eax, ebx\npop rbx\npop rbp\nretn\nloc_14A0:\nmov ebx, [rax]\ncall _free\nadd rsp, 8\nmov eax, ebx\npop rbx\npop rbp\nretn\nloc_14B0:\nxor edx, edx\njmp loc_1354\nloc_14B7:\nmov eax, 1\njmp short loc_1456\nloc_14BE:\nmov ebx, [rdi]\ncmp ebp, 1\njnz loc_13BF\njmp short loc_1489", + "ida_strip_pseudo": "__int64 __fastcall sub_12D0(__int64 a1, int a2)\n{\n signed int *v3; // rax\n signed int *v4; // rdi\n unsigned int v5; // ecx\n unsigned __int64 v6; // rax\n __m128 v7; // xmm3\n __m128 v8; // xmm0\n __m128i v9; // xmm0\n __m128i v10; // xmm1\n int v11; // edx\n __int64 v12; // r10\n __int64 v13; // r8\n int v14; // eax\n int v15; // eax\n int v16; // eax\n signed int v17; // ebx\n signed int *v18; // rax\n __m128i v19; // xmm0\n __m128i v20; // xmm1\n __m128i v21; // xmm5\n __m128i v22; // xmm1\n __m128i v23; // xmm2\n signed int v24; // eax\n __m128i v25; // xmm1\n __m128i v26; // xmm0\n __m128i v27; // xmm2\n __m128i v28; // xmm1\n __int64 v29; // rcx\n unsigned int v31; // ebx\n\n v3 = (signed int *)malloc(4LL * a2);\n v4 = v3;\n if ( a2 > 0 )\n {\n v5 = a2 - 1;\n if ( (unsigned int)(a2 - 1) <= 2 )\n {\n v11 = 0;\n }\n else\n {\n v6 = 0LL;\n do\n {\n v7 = (__m128)_mm_loadu_si128((const __m128i *)(a1 + 2 * v6 + 16));\n v8 = (__m128)_mm_loadu_si128((const __m128i *)(a1 + 2 * v6));\n v9 = _mm_sub_epi32((__m128i)_mm_shuffle_ps(v8, v7, 221), (__m128i)_mm_shuffle_ps(v8, v7, 136));\n v10 = _mm_srai_epi32(v9, 0x1Fu);\n *(__m128i *)&v4[v6 / 4] = _mm_sub_epi32(_mm_xor_si128(v9, v10), v10);\n v6 += 16LL;\n }\n while ( 16LL * ((unsigned int)a2 >> 2) != v6 );\n v11 = a2 & 0x7FFFFFFC;\n if ( (a2 & 3) == 0 )\n goto LABEL_15;\n }\n v12 = 8LL * v11;\n v13 = v11;\n v14 = *(_DWORD *)(a1 + v12 + 4) - *(_DWORD *)(a1 + v12);\n if ( *(_DWORD *)(a1 + v12) - *(_DWORD *)(a1 + v12 + 4) >= 0 )\n v14 = *(_DWORD *)(a1 + 8LL * v11) - *(_DWORD *)(a1 + 8LL * v11 + 4);\n v4[v11] = v14;\n if ( a2 <= v11 + 1 )\n {\n v17 = *v4;\n if ( a2 == 1 )\n goto LABEL_28;\n goto LABEL_16;\n }\n v15 = *(_DWORD *)(a1 + v12 + 12) - *(_DWORD *)(a1 + v12 + 8);\n if ( *(_DWORD *)(a1 + v12 + 8) - *(_DWORD *)(a1 + v12 + 12) >= 0 )\n v15 = *(_DWORD *)(a1 + v12 + 8) - *(_DWORD *)(a1 + v12 + 12);\n v4[v13 + 1] = v15;\n if ( a2 > v11 + 2 )\n {\n v16 = *(_DWORD *)(a1 + v12 + 20) - *(_DWORD *)(a1 + v12 + 16);\n if ( *(_DWORD *)(a1 + v12 + 16) - *(_DWORD *)(a1 + v12 + 20) >= 0 )\n v16 = *(_DWORD *)(a1 + v12 + 16) - *(_DWORD *)(a1 + v12 + 20);\n v4[v13 + 2] = v16;\n }\nLABEL_15:\n v17 = *v4;\nLABEL_16:\n if ( (unsigned int)(a2 - 2) <= 2 )\n {\n v24 = 1;\nLABEL_20:\n v29 = v24;\n if ( v17 > v4[v29] )\n v17 = v4[v24];\n if ( v24 + 1 < a2 )\n {\n if ( v17 > v4[v29 + 1] )\n v17 = v4[v29 + 1];\n if ( v24 + 2 < a2 && v17 > v4[v29 + 2] )\n v17 = v4[v29 + 2];\n }\n goto LABEL_28;\n }\n v18 = v4;\n v19 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v17), 0);\n do\n {\n v20 = _mm_loadu_si128((const __m128i *)(v18 + 1));\n v21 = v20;\n v18 += 4;\n v22 = _mm_cmpgt_epi32(v20, v19);\n v19 = _mm_or_si128(_mm_and_si128(v19, v22), _mm_andnot_si128(v22, v21));\n }\n while ( v18 != &v4[4 * (v5 >> 2)] );\n v23 = _mm_srli_si128(v19, 8);\n v24 = (v5 & 0xFFFFFFFC) + 1;\n v25 = _mm_cmpgt_epi32(v23, v19);\n v26 = _mm_or_si128(_mm_and_si128(v19, v25), _mm_andnot_si128(v25, v23));\n v27 = _mm_srli_si128(v26, 4);\n v28 = _mm_cmpgt_epi32(v27, v26);\n v17 = _mm_cvtsi128_si32(_mm_or_si128(_mm_andnot_si128(v28, v27), _mm_and_si128(v26, v28)));\n if ( (v5 & 3) != 0 )\n goto LABEL_20;\nLABEL_28:\n free(v4);\n return (unsigned int)v17;\n }\n v31 = *v3;\n free(v3);\n return v31;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12D0(long long a1, int a2) {\n signed int *v3;\n signed int *v4;\n unsigned int v5;\n unsigned long long v6;\n __m128 v7;\n __m128 v8;\n __m128i v9;\n __m128i v10;\n int v11;\n long long v12;\n long long v13;\n int v14;\n int v15;\n int v16;\n signed int v17;\n signed int *v18;\n __m128i v19;\n __m128i v20;\n __m128i v21;\n __m128i v22;\n __m128i v23;\n signed int v24;\n __m128i v25;\n __m128i v26;\n __m128i v27;\n __m128i v28;\n long long v29;\n unsigned int v31;\n v3 = (signed int *)malloc(4LL * a2);\n v4 = v3;\n if (a2 > 0) {\n v5 = a2 - 1;\n if ((unsigned int)(a2 - 1) <= 2) {\n v11 = 0;\n } else {\n v6 = 0LL;\n do {\n v7 = (__m128)_mm_loadu_si128((const __m128i *)(a1 + 2 * v6 + 16));\n v8 = (__m128)_mm_loadu_si128((const __m128i *)(a1 + 2 * v6));\n v9 = _mm_sub_epi32((__m128i)_mm_shuffle_ps(v8, v7, 221),\n (__m128i)_mm_shuffle_ps(v8, v7, 136));\n v10 = _mm_srai_epi32(v9, 31u);\n *(__m128i *)&v4[v6 / 4] = _mm_sub_epi32(_mm_xor_si128(v9, v10), v10);\n v6 += 16LL;\n } while (16LL * ((unsigned int)a2 >> 2) != v6);\n v11 = a2 & 2147483644;\n if ((a2 & 3) == 0) goto LABEL_15;\n }\n v12 = 8LL * v11;\n v13 = v11;\n v14 = *(uint32_t *)(a1 + v12 + 4) - *(uint32_t *)(a1 + v12);\n if (*(uint32_t *)(a1 + v12) - *(uint32_t *)(a1 + v12 + 4) >= 0)\n v14 = *(uint32_t *)(a1 + 8LL * v11) - *(uint32_t *)(a1 + 8LL * v11 + 4);\n v4[v11] = v14;\n if (a2 <= v11 + 1) {\n v17 = *v4;\n if (a2 == 1) goto LABEL_28;\n goto LABEL_16;\n }\n v15 = *(uint32_t *)(a1 + v12 + 12) - *(uint32_t *)(a1 + v12 + 8);\n if (*(uint32_t *)(a1 + v12 + 8) - *(uint32_t *)(a1 + v12 + 12) >= 0)\n v15 = *(uint32_t *)(a1 + v12 + 8) - *(uint32_t *)(a1 + v12 + 12);\n v4[v13 + 1] = v15;\n if (a2 > v11 + 2) {\n v16 = *(uint32_t *)(a1 + v12 + 20) - *(uint32_t *)(a1 + v12 + 16);\n if (*(uint32_t *)(a1 + v12 + 16) - *(uint32_t *)(a1 + v12 + 20) >= 0)\n v16 = *(uint32_t *)(a1 + v12 + 16) - *(uint32_t *)(a1 + v12 + 20);\n v4[v13 + 2] = v16;\n }\n LABEL_15:\n v17 = *v4;\n LABEL_16:\n if ((unsigned int)(a2 - 2) <= 2) {\n v24 = 1;\n LABEL_20:\n v29 = v24;\n if (v17 > v4[v29]) v17 = v4[v24];\n if (v24 + 1 < a2) {\n if (v17 > v4[v29 + 1]) v17 = v4[v29 + 1];\n if (v24 + 2 < a2 && v17 > v4[v29 + 2]) v17 = v4[v29 + 2];\n }\n goto LABEL_28;\n }\n v18 = v4;\n v19 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v17), 0);\n do {\n v20 = _mm_loadu_si128((const __m128i *)(v18 + 1));\n v21 = v20;\n v18 += 4;\n v22 = _mm_cmpgt_epi32(v20, v19);\n v19 = _mm_or_si128(_mm_and_si128(v19, v22), _mm_andnot_si128(v22, v21));\n } while (v18 != &v4[4 * (v5 >> 2)]);\n v23 = _mm_srli_si128(v19, 8);\n v24 = (v5 & 4294967292) + 1;\n v25 = _mm_cmpgt_epi32(v23, v19);\n v26 = _mm_or_si128(_mm_and_si128(v19, v25), _mm_andnot_si128(v25, v23));\n v27 = _mm_srli_si128(v26, 4);\n v28 = _mm_cmpgt_epi32(v27, v26);\n v17 = _mm_cvtsi128_si32(\n _mm_or_si128(_mm_andnot_si128(v28, v27), _mm_and_si128(v26, v28)));\n if ((v5 & 3) != 0) goto LABEL_20;\n LABEL_28:\n free(v4);\n return (unsigned int)v17;\n }\n v31 = *v3;\n free(v3);\n return v31;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n signed int *v3;\n signed int *v4;\n unsigned int v5;\n unsigned long long v6;\n __m128 v7;\n __m128 v8;\n __m128i v9;\n __m128i v10;\n int v11;\n long long v12;\n long long v13;\n int v14;\n int v15;\n int v16;\n signed int v17;\n signed int *v18;\n __m128i v19;\n __m128i v20;\n __m128i v21;\n __m128i v22;\n __m128i v23;\n signed int v24;\n __m128i v25;\n __m128i v26;\n __m128i v27;\n __m128i v28;\n long long v29;\n unsigned int v31;\n v3 = (signed int *)malloc(4LL * a2);\n v4 = v3;\n if (a2 > 0) {\n v5 = a2 - 1;\n if ((unsigned int)(a2 - 1) <= 2) {\n v11 = 0;\n } else {\n v6 = 0LL;\n do {\n v7 = (__m128)_mm_loadu_si128((const __m128i *)(a1 + 2 * v6 + 16));\n v8 = (__m128)_mm_loadu_si128((const __m128i *)(a1 + 2 * v6));\n v9 = _mm_sub_epi32((__m128i)_mm_shuffle_ps(v8, v7, 221),\n (__m128i)_mm_shuffle_ps(v8, v7, 136));\n v10 = _mm_srai_epi32(v9, 31u);\n *(__m128i *)&v4[v6 / 4] = _mm_sub_epi32(_mm_xor_si128(v9, v10), v10);\n v6 += 16LL;\n } while (16LL * ((unsigned int)a2 >> 2) != v6);\n v11 = a2 & 2147483644;\n if ((a2 & 3) == 0) goto LABEL_15;\n }\n v12 = 8LL * v11;\n v13 = v11;\n v14 = *(uint32_t *)(a1 + v12 + 4) - *(uint32_t *)(a1 + v12);\n if (*(uint32_t *)(a1 + v12) - *(uint32_t *)(a1 + v12 + 4) >= 0)\n v14 = *(uint32_t *)(a1 + 8LL * v11) - *(uint32_t *)(a1 + 8LL * v11 + 4);\n v4[v11] = v14;\n if (a2 <= v11 + 1) {\n v17 = *v4;\n if (a2 == 1) goto LABEL_28;\n goto LABEL_16;\n }\n v15 = *(uint32_t *)(a1 + v12 + 12) - *(uint32_t *)(a1 + v12 + 8);\n if (*(uint32_t *)(a1 + v12 + 8) - *(uint32_t *)(a1 + v12 + 12) >= 0)\n v15 = *(uint32_t *)(a1 + v12 + 8) - *(uint32_t *)(a1 + v12 + 12);\n v4[v13 + 1] = v15;\n if (a2 > v11 + 2) {\n v16 = *(uint32_t *)(a1 + v12 + 20) - *(uint32_t *)(a1 + v12 + 16);\n if (*(uint32_t *)(a1 + v12 + 16) - *(uint32_t *)(a1 + v12 + 20) >= 0)\n v16 = *(uint32_t *)(a1 + v12 + 16) - *(uint32_t *)(a1 + v12 + 20);\n v4[v13 + 2] = v16;\n }\n LABEL_15:\n v17 = *v4;\n LABEL_16:\n if ((unsigned int)(a2 - 2) <= 2) {\n v24 = 1;\n LABEL_20:\n v29 = v24;\n if (v17 > v4[v29]) v17 = v4[v24];\n if (v24 + 1 < a2) {\n if (v17 > v4[v29 + 1]) v17 = v4[v29 + 1];\n if (v24 + 2 < a2 && v17 > v4[v29 + 2]) v17 = v4[v29 + 2];\n }\n goto LABEL_28;\n }\n v18 = v4;\n v19 = _mm_shuffle_epi32(_mm_cvtsi32_si128(v17), 0);\n do {\n v20 = _mm_loadu_si128((const __m128i *)(v18 + 1));\n v21 = v20;\n v18 += 4;\n v22 = _mm_cmpgt_epi32(v20, v19);\n v19 = _mm_or_si128(_mm_and_si128(v19, v22), _mm_andnot_si128(v22, v21));\n } while (v18 != &v4[4 * (v5 >> 2)]);\n v23 = _mm_srli_si128(v19, 8);\n v24 = (v5 & 4294967292) + 1;\n v25 = _mm_cmpgt_epi32(v23, v19);\n v26 = _mm_or_si128(_mm_and_si128(v19, v25), _mm_andnot_si128(v25, v23));\n v27 = _mm_srli_si128(v26, 4);\n v28 = _mm_cmpgt_epi32(v27, v26);\n v17 = _mm_cvtsi128_si32(\n _mm_or_si128(_mm_andnot_si128(v28, v27), _mm_and_si128(v26, v28)));\n if ((v5 & 3) != 0) goto LABEL_20;\n LABEL_28:\n free(v4);\n return (unsigned int)v17;\n }\n v31 = *v3;\n free(v3);\n return v31;\n}" + }, + { + "index": 876, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int x, int y) {\n int z;\n if (x > y) {\n z = x;\n } else {\n z = y;\n }\n while (1) {\n if ((z % x == 0) && (z % y == 0)) {\n return z;\n }\n z += 1;\n }\n}", + "test": "int main() {\n\n assert(func0(4, 6) == 12);\n\n assert(func0(15, 17) == 255);\n\n assert(func0(2, 6) == 6);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov -0x14(%rbp),%eax\ncmp -0x18(%rbp),%eax\njle 1167 \nmov -0x14(%rbp),%eax\nmov %eax,-0x4(%rbp)\njmp 116d \nmov -0x18(%rbp),%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncltd\nidivl -0x14(%rbp)\nmov %edx,%eax\ntest %eax,%eax\njne 118c \nmov -0x4(%rbp),%eax\ncltd\nidivl -0x18(%rbp)\nmov %edx,%eax\ntest %eax,%eax\njne 118c \nmov -0x4(%rbp),%eax\njmp 1192 \naddl $0x1,-0x4(%rbp)\njmp 116d \npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_18]\njle short loc_1167\nmov eax, [rbp+var_14]\nmov [rbp+var_4], eax\njmp short loc_116D\nloc_1167:\nmov eax, [rbp+var_18]\nmov [rbp+var_4], eax\nloc_116D:\nmov eax, [rbp+var_4]\ncdq\nidiv [rbp+var_14]\nmov eax, edx\ntest eax, eax\njnz short loc_118C\nmov eax, [rbp+var_4]\ncdq\nidiv [rbp+var_18]\nmov eax, edx\ntest eax, eax\njnz short loc_118C\nmov eax, [rbp+var_4]\njmp short loc_1192\nloc_118C:\nadd [rbp+var_4], 1\njmp short loc_116D\nloc_1192:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(signed int a1, signed int a2)\n{\n signed int v3; // [rsp+14h] [rbp-4h]\n\n if ( a1 <= a2 )\n v3 = a2;\n else\n v3 = a1;\n while ( v3 % a1 || v3 % a2 )\n ++v3;\n return (unsigned int)v3;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_18]\njle short loc_1167\nmov eax, [rbp+var_14]\nmov [rbp+var_4], eax\njmp short loc_116D\nloc_1167:\nmov eax, [rbp+var_18]\nmov [rbp+var_4], eax\nloc_116D:\nmov eax, [rbp+var_4]\ncdq\nidiv [rbp+var_14]\nmov eax, edx\ntest eax, eax\njnz short loc_118C\nmov eax, [rbp+var_4]\ncdq\nidiv [rbp+var_18]\nmov eax, edx\ntest eax, eax\njnz short loc_118C\nmov eax, [rbp+var_4]\njmp short loc_1192\nloc_118C:\nadd [rbp+var_4], 1\njmp short loc_116D\nloc_1192:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(signed int a1, signed int a2)\n{\n signed int v3; // [rsp+14h] [rbp-4h]\n\n if ( a1 <= a2 )\n v3 = a2;\n else\n v3 = a1;\n while ( v3 % a1 || v3 % a2 )\n ++v3;\n return (unsigned int)v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(signed int a1, signed int a2) {\n signed int v3;\n if (a1 <= a2)\n v3 = a2;\n else\n v3 = a1;\n while (v3 % a1 || v3 % a2) ++v3;\n return (unsigned int)v3;\n}", + "ida_pseudo_norm": "long long func0(signed int a1, signed int a2) {\n signed int v3;\n if (a1 <= a2)\n v3 = a2;\n else\n v3 = a1;\n while (v3 % a1 || v3 % a2) ++v3;\n return (unsigned int)v3;\n}" + }, + { + "index": 876, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int x, int y) {\n int z;\n if (x > y) {\n z = x;\n } else {\n z = y;\n }\n while (1) {\n if ((z % x == 0) && (z % y == 0)) {\n return z;\n }\n z += 1;\n }\n}", + "test": "int main() {\n\n assert(func0(4, 6) == 12);\n\n assert(func0(15, 17) == 255);\n\n assert(func0(2, 6) == 6);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ncmp %esi,%edi\nmov %esi,%ecx\ncmovge %edi,%ecx\njmp 1159 \nadd $0x1,%ecx\nmov %ecx,%eax\ncltd\nidiv %edi\ntest %edx,%edx\njne 1156 \nmov %ecx,%eax\ncltd\nidiv %esi\ntest %edx,%edx\njne 1156 \nmov %ecx,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ncmp edi, esi\nmov ecx, esi\ncmovge ecx, edi\njmp short loc_1159\nloc_1156:\nadd ecx, 1\nloc_1159:\nmov eax, ecx\ncdq\nidiv edi\ntest edx, edx\njnz short loc_1156\nmov eax, ecx\ncdq\nidiv esi\ntest edx, edx\njnz short loc_1156\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(signed int a1, signed int a2)\n{\n signed int v2; // ecx\n\n v2 = a2;\n if ( a1 >= a2 )\n v2 = a1;\n while ( v2 % a1 || v2 % a2 )\n ++v2;\n return (unsigned int)v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ncmp edi, esi\nmov ecx, esi\ncmovge ecx, edi\njmp short loc_1159\nloc_1156:\nadd ecx, 1\nloc_1159:\nmov eax, ecx\ncdq\nidiv edi\ntest edx, edx\njnz short loc_1156\nmov eax, ecx\ncdq\nidiv esi\ntest edx, edx\njnz short loc_1156\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(signed int a1, signed int a2)\n{\n signed int v2; // ecx\n\n v2 = a2;\n if ( a1 >= a2 )\n v2 = a1;\n while ( v2 % a1 || v2 % a2 )\n ++v2;\n return (unsigned int)v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(signed int a1, signed int a2) {\n signed int v2;\n v2 = a2;\n if (a1 >= a2) v2 = a1;\n while (v2 % a1 || v2 % a2) ++v2;\n return (unsigned int)v2;\n}", + "ida_pseudo_norm": "long long func0(signed int a1, signed int a2) {\n signed int v2;\n v2 = a2;\n if (a1 >= a2) v2 = a1;\n while (v2 % a1 || v2 % a2) ++v2;\n return (unsigned int)v2;\n}" + }, + { + "index": 877, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(char *str) {\n int n = strlen(str);\n char temp;\n for (int i = 0; i < n - 1; i++) {\n for (int j = i + 1; j < n; j++) {\n if (str[i] > str[j]) {\n temp = str[i];\n str[i] = str[j];\n str[j] = temp;\n }\n }\n }\n}", + "test": "int main() {\n\n char str1[] = \"cba\";\n\n char str2[] = \"data\";\n\n char str3[] = \"zxy\";\n\n\n\n func0(str1);\n\n func0(str2);\n\n func0(str3);\n\n \n\n assert(strcmp(str1, \"abc\") == 0);\n\n assert(strcmp(str2, \"aadt\") == 0);\n\n assert(strcmp(str3, \"xyz\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov -0x18(%rbp),%rax\nmov %rax,%rdi\ncallq 1080 \nmov %eax,-0x4(%rbp)\nmovl $0x0,-0xc(%rbp)\njmpq 1258 \nmov -0xc(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x8(%rbp)\njmp 124c \nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%edx\nmov -0x8(%rbp),%eax\nmovslq %eax,%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmovzbl (%rax),%eax\ncmp %al,%dl\njle 1248 \nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmov %al,-0xd(%rbp)\nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0xc(%rbp),%edx\nmovslq %edx,%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rax),%eax\nmov %al,(%rdx)\nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmovzbl -0xd(%rbp),%eax\nmov %al,(%rdx)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x4(%rbp),%eax\njl 11df \naddl $0x1,-0xc(%rbp)\nmov -0x4(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0xc(%rbp)\njl 11d4 \nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_C], 0\njmp loc_1258\nloc_11D4:\nmov eax, [rbp+var_C]\nadd eax, 1\nmov [rbp+var_8], eax\njmp short loc_124C\nloc_11DF:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_8]\nmovsxd rcx, eax\nmov rax, [rbp+s]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njle short loc_1248\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_D], al\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx eax, byte ptr [rax]\nmov [rdx], al\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rdx, rax\nmovzx eax, [rbp+var_D]\nmov [rdx], al\nloc_1248:\nadd [rbp+var_8], 1\nloc_124C:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njl short loc_11DF\nadd [rbp+var_C], 1\nloc_1258:\nmov eax, [rbp+var_4]\nsub eax, 1\ncmp [rbp+var_C], eax\njl loc_11D4\nnop\nnop\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n __int64 result; // rax\n char v2; // [rsp+13h] [rbp-Dh]\n int i; // [rsp+14h] [rbp-Ch]\n int j; // [rsp+18h] [rbp-8h]\n int v5; // [rsp+1Ch] [rbp-4h]\n\n v5 = strlen(a1);\n for ( i = 0; ; ++i )\n {\n result = (unsigned int)(v5 - 1);\n if ( i >= (int)result )\n break;\n for ( j = i + 1; j < v5; ++j )\n {\n if ( a1[i] > a1[j] )\n {\n v2 = a1[i];\n a1[i] = a1[j];\n a1[j] = v2;\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_C], 0\njmp loc_1258\nloc_11D4:\nmov eax, [rbp+var_C]\nadd eax, 1\nmov [rbp+var_8], eax\njmp short loc_124C\nloc_11DF:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_8]\nmovsxd rcx, eax\nmov rax, [rbp+s]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njle short loc_1248\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_D], al\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx eax, byte ptr [rax]\nmov [rdx], al\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rdx, rax\nmovzx eax, [rbp+var_D]\nmov [rdx], al\nloc_1248:\nadd [rbp+var_8], 1\nloc_124C:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njl short loc_11DF\nadd [rbp+var_C], 1\nloc_1258:\nmov eax, [rbp+var_4]\nsub eax, 1\ncmp [rbp+var_C], eax\njl loc_11D4\nnop\nnop\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(const char *a1)\n{\n __int64 result; // rax\n char v2; // [rsp+13h] [rbp-Dh]\n int i; // [rsp+14h] [rbp-Ch]\n int j; // [rsp+18h] [rbp-8h]\n int v5; // [rsp+1Ch] [rbp-4h]\n\n v5 = strlen(a1);\n for ( i = 0; ; ++i )\n {\n result = (unsigned int)(v5 - 1);\n if ( i >= (int)result )\n break;\n for ( j = i + 1; j < v5; ++j )\n {\n if ( a1[i] > a1[j] )\n {\n v2 = a1[i];\n a1[i] = a1[j];\n a1[j] = v2;\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(const char *a1) {\n long long result;\n char v2;\n int i;\n int j;\n int v5;\n v5 = strlen(a1);\n for (i = 0;; ++i) {\n result = (unsigned int)(v5 - 1);\n if (i >= (int)result) break;\n for (j = i + 1; j < v5; ++j) {\n if (a1[i] > a1[j]) {\n v2 = a1[i];\n a1[i] = a1[j];\n a1[j] = v2;\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n long long result;\n char v2;\n int i;\n int j;\n int v5;\n v5 = strlen(a1);\n for (i = 0;; ++i) {\n result = (unsigned int)(v5 - 1);\n if (i >= (int)result) break;\n for (j = i + 1; j < v5; ++j) {\n if (a1[i] > a1[j]) {\n v2 = a1[i];\n a1[i] = a1[j];\n a1[j] = v2;\n }\n }\n }\n return result;\n}" + }, + { + "index": 877, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(char *str) {\n int n = strlen(str);\n char temp;\n for (int i = 0; i < n - 1; i++) {\n for (int j = i + 1; j < n; j++) {\n if (str[i] > str[j]) {\n temp = str[i];\n str[i] = str[j];\n str[j] = temp;\n }\n }\n }\n}", + "test": "int main() {\n\n char str1[] = \"cba\";\n\n char str2[] = \"data\";\n\n char str3[] = \"zxy\";\n\n\n\n func0(str1);\n\n func0(str2);\n\n func0(str3);\n\n \n\n assert(strcmp(str1, \"abc\") == 0);\n\n assert(strcmp(str2, \"aadt\") == 0);\n\n assert(strcmp(str3, \"xyz\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%r8\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nsub $0x1,%rax\nmov %eax,%edi\ncmp $0x1,%eax\njle 11d5 \nmov %r8,%rsi\nlea -0x2(%rax),%r10d\nadd $0x2,%r10\nmov $0x1,%r9d\njmp 11cb \nadd $0x1,%rax\ncmp %eax,%edi\njle 11be \nmovzbl (%rsi),%edx\nmovzbl (%r8,%rax,1),%ecx\ncmp %cl,%dl\njle 11a2 \nmov %cl,(%rsi)\nmov %dl,(%r8,%rax,1)\njmp 11a2 \nadd $0x1,%r9\nadd $0x1,%rsi\ncmp %r10,%r9\nje 11d5 \ncmp %r9d,%edi\njle 11be \nmov %r9,%rax\njmp 11aa \nretq\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ncmp eax, 1\njle short loc_1209\nmov r10d, eax\nmov rdi, rbx\nlea r9d, [rax-1]\nmov r8d, 0\njmp short loc_11EF\nloc_11CD:\nadd rax, 1\ncmp rax, rsi\njz short loc_11E6\nloc_11D6:\nmovzx edx, byte ptr [rdi]\nmovzx ecx, byte ptr [rax]\ncmp dl, cl\njle short loc_11CD\nmov [rdi], cl\nmov [rax], dl\njmp short loc_11CD\nloc_11E6:\nadd rdi, 1\ncmp r8d, r9d\njz short loc_1209\nloc_11EF:\nadd r8d, 1\ncmp r10d, r8d\njle short loc_11E6\nlea rax, [rdi+1]\nmov edx, r9d\nsub edx, r8d\nlea rsi, [rdi+rdx+2]\njmp short loc_11D6\nloc_1209:\npop rbx\nretn", + "ida_pseudo": "char *__fastcall func0(char *a1)\n{\n char *result; // rax\n int v2; // r10d\n int v3; // r9d\n int v4; // r8d\n char v5; // dl\n\n result = (char *)strlen(a1);\n if ( (int)result > 1 )\n {\n v2 = (int)result;\n v3 = (_DWORD)result - 1;\n v4 = 0;\n do\n {\n if ( v2 > ++v4 )\n {\n result = a1 + 1;\n do\n {\n v5 = *a1;\n if ( *a1 > *result )\n {\n *a1 = *result;\n *result = v5;\n }\n ++result;\n }\n while ( result != &a1[v3 - v4 + 2] );\n }\n ++a1;\n }\n while ( v4 != v3 );\n }\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ncmp eax, 1\njle short loc_1209\nmov r10d, eax\nmov rdi, rbx\nlea r9d, [rax-1]\nmov r8d, 0\njmp short loc_11EF\nloc_11CD:\nadd rax, 1\ncmp rax, rsi\njz short loc_11E6\nloc_11D6:\nmovzx edx, byte ptr [rdi]\nmovzx ecx, byte ptr [rax]\ncmp dl, cl\njle short loc_11CD\nmov [rdi], cl\nmov [rax], dl\njmp short loc_11CD\nloc_11E6:\nadd rdi, 1\ncmp r8d, r9d\njz short loc_1209\nloc_11EF:\nadd r8d, 1\ncmp r10d, r8d\njle short loc_11E6\nlea rax, [rdi+1]\nmov edx, r9d\nsub edx, r8d\nlea rsi, [rdi+rdx+2]\njmp short loc_11D6\nloc_1209:\npop rbx\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11A9(char *a1)\n{\n char *result; // rax\n int v2; // r10d\n int v3; // r9d\n int v4; // r8d\n char v5; // dl\n\n result = (char *)strlen(a1);\n if ( (int)result > 1 )\n {\n v2 = (int)result;\n v3 = (_DWORD)result - 1;\n v4 = 0;\n do\n {\n if ( v2 > ++v4 )\n {\n result = a1 + 1;\n do\n {\n v5 = *a1;\n if ( *a1 > *result )\n {\n *a1 = *result;\n *result = v5;\n }\n ++result;\n }\n while ( result != &a1[v3 - v4 + 2] );\n }\n ++a1;\n }\n while ( v4 != v3 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11A9(char *a1) {\n char *result;\n int v2;\n int v3;\n int v4;\n char v5;\n result = (char *)strlen(a1);\n if ((int)result > 1) {\n v2 = (int)result;\n v3 = (uint32_t)result - 1;\n v4 = 0;\n do {\n if (v2 > ++v4) {\n result = a1 + 1;\n do {\n v5 = *a1;\n if (*a1 > *result) {\n *a1 = *result;\n *result = v5;\n }\n ++result;\n } while (result != &a1[v3 - v4 + 2]);\n }\n ++a1;\n } while (v4 != v3);\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(char *a1) {\n char *result;\n int v2;\n int v3;\n int v4;\n char v5;\n result = (char *)strlen(a1);\n if ((int)result > 1) {\n v2 = (int)result;\n v3 = (uint32_t)result - 1;\n v4 = 0;\n do {\n if (v2 > ++v4) {\n result = a1 + 1;\n do {\n v5 = *a1;\n if (*a1 > *result) {\n *a1 = *result;\n *result = v5;\n }\n ++result;\n } while (result != &a1[v3 - v4 + 2]);\n }\n ++a1;\n } while (v4 != v3);\n }\n return result;\n}" + }, + { + "index": 877, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(char *str) {\n int n = strlen(str);\n char temp;\n for (int i = 0; i < n - 1; i++) {\n for (int j = i + 1; j < n; j++) {\n if (str[i] > str[j]) {\n temp = str[i];\n str[i] = str[j];\n str[j] = temp;\n }\n }\n }\n}", + "test": "int main() {\n\n char str1[] = \"cba\";\n\n char str2[] = \"data\";\n\n char str3[] = \"zxy\";\n\n\n\n func0(str1);\n\n func0(str2);\n\n func0(str3);\n\n \n\n assert(strcmp(str1, \"abc\") == 0);\n\n assert(strcmp(str2, \"aadt\") == 0);\n\n assert(strcmp(str3, \"xyz\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\ncallq 1070 \ncmp $0x1,%eax\njle 131f \nmov %eax,%r11d\nmov %rbx,%rdi\nlea -0x1(%rax),%r10d\nxor %r8d,%r8d\nadd $0x1,%r8d\nlea 0x1(%rdi),%r9\ncmp %r8d,%r11d\njle 1317 \nmov %r10d,%edx\nmov %r9,%rax\nsub %r8d,%edx\nlea 0x2(%rdi,%rdx,1),%rsi\nnopl 0x0(%rax,%rax,1)\nmovzbl (%rdi),%edx\nmovzbl (%rax),%ecx\ncmp %cl,%dl\njle 130e \nmov %cl,(%rdi)\nmov %dl,(%rax)\nadd $0x1,%rax\ncmp %rsi,%rax\njne 1300 \nmov %r9,%rdi\ncmp %r10d,%r8d\njne 12e0 \npop %rbx\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ncmp eax, 1\njle short loc_132F\nmov r11d, eax\nmov rdi, rbx\nlea r10d, [rax-1]\nxor r8d, r8d\nnop\nloc_12F0:\nadd r8d, 1\nlea r9, [rdi+1]\ncmp r11d, r8d\njle short loc_1327\nmov edx, r10d\nmov rax, r9\nsub edx, r8d\nlea rsi, [rdi+rdx+2]\nnop dword ptr [rax+rax+00h]\nloc_1310:\nmovzx edx, byte ptr [rdi]\nmovzx ecx, byte ptr [rax]\ncmp dl, cl\njle short loc_131E\nmov [rdi], cl\nmov [rax], dl\nloc_131E:\nadd rax, 1\ncmp rax, rsi\njnz short loc_1310\nloc_1327:\nmov rdi, r9\ncmp r8d, r10d\njnz short loc_12F0\nloc_132F:\npop rbx\nretn", + "ida_pseudo": "char *__fastcall func0(char *a1)\n{\n char *result; // rax\n int v2; // r11d\n int v3; // r10d\n int v4; // r8d\n char v5; // dl\n\n result = (char *)strlen(a1);\n if ( (int)result > 1 )\n {\n v2 = (int)result;\n v3 = (_DWORD)result - 1;\n v4 = 0;\n do\n {\n if ( v2 > ++v4 )\n {\n result = a1 + 1;\n do\n {\n v5 = *a1;\n if ( *a1 > *result )\n {\n *a1 = *result;\n *result = v5;\n }\n ++result;\n }\n while ( result != &a1[v3 - v4 + 2] );\n }\n ++a1;\n }\n while ( v4 != v3 );\n }\n return result;\n}", + "ida_strip_asm": "sub_12D0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ncmp eax, 1\njle short loc_132F\nmov r11d, eax\nmov rdi, rbx\nlea r10d, [rax-1]\nxor r8d, r8d\nnop\nloc_12F0:\nadd r8d, 1\nlea r9, [rdi+1]\ncmp r11d, r8d\njle short loc_1327\nmov edx, r10d\nmov rax, r9\nsub edx, r8d\nlea rsi, [rdi+rdx+2]\nnop dword ptr [rax+rax+00h]\nloc_1310:\nmovzx edx, byte ptr [rdi]\nmovzx ecx, byte ptr [rax]\ncmp dl, cl\njle short loc_131E\nmov [rdi], cl\nmov [rax], dl\nloc_131E:\nadd rax, 1\ncmp rax, rsi\njnz short loc_1310\nloc_1327:\nmov rdi, r9\ncmp r8d, r10d\njnz short loc_12F0\nloc_132F:\npop rbx\nretn", + "ida_strip_pseudo": "char *__fastcall sub_12D0(char *a1)\n{\n char *result; // rax\n int v2; // r11d\n int v3; // r10d\n int v4; // r8d\n char v5; // dl\n\n result = (char *)strlen(a1);\n if ( (int)result > 1 )\n {\n v2 = (int)result;\n v3 = (_DWORD)result - 1;\n v4 = 0;\n do\n {\n if ( v2 > ++v4 )\n {\n result = a1 + 1;\n do\n {\n v5 = *a1;\n if ( *a1 > *result )\n {\n *a1 = *result;\n *result = v5;\n }\n ++result;\n }\n while ( result != &a1[v3 - v4 + 2] );\n }\n ++a1;\n }\n while ( v4 != v3 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_12D0(char *a1) {\n char *result;\n int v2;\n int v3;\n int v4;\n char v5;\n result = (char *)strlen(a1);\n if ((int)result > 1) {\n v2 = (int)result;\n v3 = (uint32_t)result - 1;\n v4 = 0;\n do {\n if (v2 > ++v4) {\n result = a1 + 1;\n do {\n v5 = *a1;\n if (*a1 > *result) {\n *a1 = *result;\n *result = v5;\n }\n ++result;\n } while (result != &a1[v3 - v4 + 2]);\n }\n ++a1;\n } while (v4 != v3);\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(char *a1) {\n char *result;\n int v2;\n int v3;\n int v4;\n char v5;\n result = (char *)strlen(a1);\n if ((int)result > 1) {\n v2 = (int)result;\n v3 = (uint32_t)result - 1;\n v4 = 0;\n do {\n if (v2 > ++v4) {\n result = a1 + 1;\n do {\n v5 = *a1;\n if (*a1 > *result) {\n *a1 = *result;\n *result = v5;\n }\n ++result;\n } while (result != &a1[v3 - v4 + 2]);\n }\n ++a1;\n } while (v4 != v3);\n }\n return result;\n}" + }, + { + "index": 877, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "void func0(char *str) {\n int n = strlen(str);\n char temp;\n for (int i = 0; i < n - 1; i++) {\n for (int j = i + 1; j < n; j++) {\n if (str[i] > str[j]) {\n temp = str[i];\n str[i] = str[j];\n str[j] = temp;\n }\n }\n }\n}", + "test": "int main() {\n\n char str1[] = \"cba\";\n\n char str2[] = \"data\";\n\n char str3[] = \"zxy\";\n\n\n\n func0(str1);\n\n func0(str2);\n\n func0(str3);\n\n \n\n assert(strcmp(str1, \"abc\") == 0);\n\n assert(strcmp(str2, \"aadt\") == 0);\n\n assert(strcmp(str3, \"xyz\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\ncallq 1070 \ncmp $0x1,%eax\njle 131f \nmov %eax,%r11d\nmov %rbx,%rdi\nlea -0x1(%rax),%r10d\nxor %r8d,%r8d\nadd $0x1,%r8d\nlea 0x1(%rdi),%r9\ncmp %r8d,%r11d\njle 1317 \nmov %r10d,%edx\nmov %r9,%rax\nsub %r8d,%edx\nlea 0x2(%rdi,%rdx,1),%rsi\nnopl 0x0(%rax,%rax,1)\nmovzbl (%rdi),%edx\nmovzbl (%rax),%ecx\ncmp %cl,%dl\njle 130e \nmov %cl,(%rdi)\nmov %dl,(%rax)\nadd $0x1,%rax\ncmp %rsi,%rax\njne 1300 \nmov %r9,%rdi\ncmp %r10d,%r8d\njne 12e0 \npop %rbx\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ncmp eax, 1\njle short loc_132F\nmov r11d, eax\nmov rdi, rbx\nlea r10d, [rax-1]\nxor r8d, r8d\nnop\nloc_12F0:\nadd r8d, 1\nlea r9, [rdi+1]\ncmp r11d, r8d\njle short loc_1327\nmov edx, r10d\nmov rax, r9\nsub edx, r8d\nlea rsi, [rdi+rdx+2]\nnop dword ptr [rax+rax+00h]\nloc_1310:\nmovzx edx, byte ptr [rdi]\nmovzx ecx, byte ptr [rax]\ncmp dl, cl\njle short loc_131E\nmov [rdi], cl\nmov [rax], dl\nloc_131E:\nadd rax, 1\ncmp rax, rsi\njnz short loc_1310\nloc_1327:\nmov rdi, r9\ncmp r8d, r10d\njnz short loc_12F0\nloc_132F:\npop rbx\nretn", + "ida_pseudo": "char *__fastcall func0(char *a1)\n{\n char *result; // rax\n int v2; // r11d\n int v3; // r10d\n int v4; // r8d\n char v5; // dl\n\n result = (char *)strlen(a1);\n if ( (int)result > 1 )\n {\n v2 = (int)result;\n v3 = (_DWORD)result - 1;\n v4 = 0;\n do\n {\n if ( v2 > ++v4 )\n {\n result = a1 + 1;\n do\n {\n v5 = *a1;\n if ( *a1 > *result )\n {\n *a1 = *result;\n *result = v5;\n }\n ++result;\n }\n while ( result != &a1[v3 - v4 + 2] );\n }\n ++a1;\n }\n while ( v4 != v3 );\n }\n return result;\n}", + "ida_strip_asm": "sub_12D0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ncmp eax, 1\njle short loc_132F\nmov r11d, eax\nmov rdi, rbx\nlea r10d, [rax-1]\nxor r8d, r8d\nnop\nloc_12F0:\nadd r8d, 1\nlea r9, [rdi+1]\ncmp r11d, r8d\njle short loc_1327\nmov edx, r10d\nmov rax, r9\nsub edx, r8d\nlea rsi, [rdi+rdx+2]\nnop dword ptr [rax+rax+00h]\nloc_1310:\nmovzx edx, byte ptr [rdi]\nmovzx ecx, byte ptr [rax]\ncmp dl, cl\njle short loc_131E\nmov [rdi], cl\nmov [rax], dl\nloc_131E:\nadd rax, 1\ncmp rax, rsi\njnz short loc_1310\nloc_1327:\nmov rdi, r9\ncmp r8d, r10d\njnz short loc_12F0\nloc_132F:\npop rbx\nretn", + "ida_strip_pseudo": "char *__fastcall sub_12D0(char *a1)\n{\n char *result; // rax\n int v2; // r11d\n int v3; // r10d\n int v4; // r8d\n char v5; // dl\n\n result = (char *)strlen(a1);\n if ( (int)result > 1 )\n {\n v2 = (int)result;\n v3 = (_DWORD)result - 1;\n v4 = 0;\n do\n {\n if ( v2 > ++v4 )\n {\n result = a1 + 1;\n do\n {\n v5 = *a1;\n if ( *a1 > *result )\n {\n *a1 = *result;\n *result = v5;\n }\n ++result;\n }\n while ( result != &a1[v3 - v4 + 2] );\n }\n ++a1;\n }\n while ( v4 != v3 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_12D0(char *a1) {\n char *result;\n int v2;\n int v3;\n int v4;\n char v5;\n result = (char *)strlen(a1);\n if ((int)result > 1) {\n v2 = (int)result;\n v3 = (uint32_t)result - 1;\n v4 = 0;\n do {\n if (v2 > ++v4) {\n result = a1 + 1;\n do {\n v5 = *a1;\n if (*a1 > *result) {\n *a1 = *result;\n *result = v5;\n }\n ++result;\n } while (result != &a1[v3 - v4 + 2]);\n }\n ++a1;\n } while (v4 != v3);\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(char *a1) {\n char *result;\n int v2;\n int v3;\n int v4;\n char v5;\n result = (char *)strlen(a1);\n if ((int)result > 1) {\n v2 = (int)result;\n v3 = (uint32_t)result - 1;\n v4 = 0;\n do {\n if (v2 > ++v4) {\n result = a1 + 1;\n do {\n v5 = *a1;\n if (*a1 > *result) {\n *a1 = *result;\n *result = v5;\n }\n ++result;\n } while (result != &a1[v3 - v4 + 2]);\n }\n ++a1;\n } while (v4 != v3);\n }\n return result;\n}" + }, + { + "index": 878, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int test_tuple[], int tuple_size, int K[], int K_size) {\n for (int i = 0; i < tuple_size; i++) {\n bool found = false;\n for (int j = 0; j < K_size; j++) {\n if (test_tuple[i] == K[j]) {\n found = true;\n break;\n }\n }\n if (!found) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n int tuple1[] = {3, 5, 6, 5, 3, 6};\n\n int K1[] = {3, 6, 5};\n\n assert(func0(tuple1, 6, K1, 3) == true);\n\n\n\n int tuple2[] = {4, 5, 6, 4, 6, 5};\n\n int K2[] = {4, 5, 6};\n\n assert(func0(tuple2, 6, K2, 3) == true);\n\n\n\n int tuple3[] = {9, 8, 7, 6, 8, 9};\n\n int K3[] = {9, 8, 1};\n\n assert(func0(tuple3, 6, K3, 3) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %ecx,-0x20(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11ed \nmovb $0x0,-0x9(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11cf \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 11cb \nmovb $0x1,-0x9(%rbp)\njmp 11d7 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x20(%rbp),%eax\njl 1195 \nmovzbl -0x9(%rbp),%eax\nxor $0x1,%eax\ntest %al,%al\nje 11e9 \nmov $0x0,%eax\njmp 11fa \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1188 \nmov $0x1,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov [rbp+var_8], 0\njmp short loc_11ED\nloc_1188:\nmov [rbp+var_9], 0\nmov [rbp+var_4], 0\njmp short loc_11CF\nloc_1195:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11CB\nmov [rbp+var_9], 1\njmp short loc_11D7\nloc_11CB:\nadd [rbp+var_4], 1\nloc_11CF:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_20]\njl short loc_1195\nloc_11D7:\nmovzx eax, [rbp+var_9]\nxor eax, 1\ntest al, al\njz short loc_11E9\nmov eax, 0\njmp short loc_11FA\nloc_11E9:\nadd [rbp+var_8], 1\nloc_11ED:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, 1\nloc_11FA:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3, int a4)\n{\n char v5; // [rsp+1Fh] [rbp-9h]\n int i; // [rsp+20h] [rbp-8h]\n int j; // [rsp+24h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n v5 = 0;\n for ( j = 0; j < a4; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4LL * j + a3) )\n {\n v5 = 1;\n break;\n }\n }\n if ( v5 != 1 )\n return 0LL;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov [rbp+var_8], 0\njmp short loc_11ED\nloc_1188:\nmov [rbp+var_9], 0\nmov [rbp+var_4], 0\njmp short loc_11CF\nloc_1195:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11CB\nmov [rbp+var_9], 1\njmp short loc_11D7\nloc_11CB:\nadd [rbp+var_4], 1\nloc_11CF:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_20]\njl short loc_1195\nloc_11D7:\nmovzx eax, [rbp+var_9]\nxor eax, 1\ntest al, al\njz short loc_11E9\nmov eax, 0\njmp short loc_11FA\nloc_11E9:\nadd [rbp+var_8], 1\nloc_11ED:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, 1\nloc_11FA:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, __int64 a3, int a4)\n{\n char v5; // [rsp+1Fh] [rbp-9h]\n int i; // [rsp+20h] [rbp-8h]\n int j; // [rsp+24h] [rbp-4h]\n\n for ( i = 0; i < a2; ++i )\n {\n v5 = 0;\n for ( j = 0; j < a4; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a1) == *(_DWORD *)(4LL * j + a3) )\n {\n v5 = 1;\n break;\n }\n }\n if ( v5 != 1 )\n return 0LL;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, long long a3, int a4) {\n char v5;\n int i;\n int j;\n for (i = 0; i < a2; ++i) {\n v5 = 0;\n for (j = 0; j < a4; ++j) {\n if (*(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4LL * j + a3)) {\n v5 = 1;\n break;\n }\n }\n if (v5 != 1) return 0LL;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3, int a4) {\n char v5;\n int i;\n int j;\n for (i = 0; i < a2; ++i) {\n v5 = 0;\n for (j = 0; j < a4; ++j) {\n if (*(uint32_t *)(4LL * i + a1) == *(uint32_t *)(4LL * j + a3)) {\n v5 = 1;\n break;\n }\n }\n if (v5 != 1) return 0LL;\n }\n return 1LL;\n}" + }, + { + "index": 878, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int test_tuple[], int tuple_size, int K[], int K_size) {\n for (int i = 0; i < tuple_size; i++) {\n bool found = false;\n for (int j = 0; j < K_size; j++) {\n if (test_tuple[i] == K[j]) {\n found = true;\n break;\n }\n }\n if (!found) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n int tuple1[] = {3, 5, 6, 5, 3, 6};\n\n int K1[] = {3, 6, 5};\n\n assert(func0(tuple1, 6, K1, 3) == true);\n\n\n\n int tuple2[] = {4, 5, 6, 4, 6, 5};\n\n int K2[] = {4, 5, 6};\n\n assert(func0(tuple2, 6, K2, 3) == true);\n\n\n\n int tuple3[] = {9, 8, 7, 6, 8, 9};\n\n int K3[] = {9, 8, 1};\n\n assert(func0(tuple3, 6, K3, 3) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1189 \nmov %rdi,%r8\nlea -0x1(%rsi),%eax\nlea 0x4(%rdi,%rax,4),%r9\nmov %rdx,%rdi\nlea -0x1(%rcx),%eax\nlea 0x4(%rdx,%rax,4),%rsi\njmp 119e \nmov $0x1,%eax\nretq\nmov $0x0,%eax\nretq\nadd $0x4,%r8\ncmp %r9,%r8\nje 11bb \ntest %ecx,%ecx\njle 118f \nmov (%r8),%edx\nmov %rdi,%rax\ncmp (%rax),%edx\nje 1195 \nadd $0x4,%rax\ncmp %rsi,%rax\njne 11a8 \nmov $0x0,%eax\nretq\nmov $0x1,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11B0\nmov r8, rdi\nmovsxd rsi, esi\nlea r9, [rdi+rsi*4]\nmovsxd rax, ecx\nlea rdi, [rdx+rax*4]\njmp short loc_118D\nloc_1184:\nadd r8, 4\ncmp r8, r9\njz short loc_11B6\nloc_118D:\ntest ecx, ecx\njle short loc_11AA\nmov esi, [r8]\nmov rax, rdx\nloc_1197:\ncmp esi, [rax]\njz short loc_1184\nadd rax, 4\ncmp rax, rdi\njnz short loc_1197\nmov eax, 0\nretn\nloc_11AA:\nmov eax, 0\nretn\nloc_11B0:\nmov eax, 1\nretn\nloc_11B6:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2, _DWORD *a3, int a4)\n{\n _DWORD *v4; // r8\n _DWORD *v5; // rax\n\n if ( a2 <= 0 )\n return 1LL;\n v4 = a1;\n while ( 2 )\n {\n if ( a4 <= 0 )\n return 0LL;\n v5 = a3;\n while ( *v4 != *v5 )\n {\n if ( ++v5 == &a3[a4] )\n return 0LL;\n }\n if ( ++v4 != &a1[a2] )\n continue;\n break;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11B0\nmov r8, rdi\nmovsxd rsi, esi\nlea r9, [rdi+rsi*4]\nmovsxd rax, ecx\nlea rdi, [rdx+rax*4]\njmp short loc_118D\nloc_1184:\nadd r8, 4\ncmp r8, r9\njz short loc_11B6\nloc_118D:\ntest ecx, ecx\njle short loc_11AA\nmov esi, [r8]\nmov rax, rdx\nloc_1197:\ncmp esi, [rax]\njz short loc_1184\nadd rax, 4\ncmp rax, rdi\njnz short loc_1197\nmov eax, 0\nretn\nloc_11AA:\nmov eax, 0\nretn\nloc_11B0:\nmov eax, 1\nretn\nloc_11B6:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2, _DWORD *a3, int a4)\n{\n _DWORD *v4; // r8\n _DWORD *v5; // rax\n\n if ( a2 <= 0 )\n return 1LL;\n v4 = a1;\n while ( 2 )\n {\n if ( a4 <= 0 )\n return 0LL;\n v5 = a3;\n while ( *v4 != *v5 )\n {\n if ( ++v5 == &a3[a4] )\n return 0LL;\n }\n if ( ++v4 != &a1[a2] )\n continue;\n break;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2, uint32_t *a3, int a4) {\n uint32_t *v4;\n uint32_t *v5;\n if (a2 <= 0) return 1LL;\n v4 = a1;\n while (2) {\n if (a4 <= 0) return 0LL;\n v5 = a3;\n while (*v4 != *v5) {\n if (++v5 == &a3[a4]) return 0LL;\n }\n if (++v4 != &a1[a2]) continue;\n break;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2, uint32_t *a3, int a4) {\n uint32_t *v4;\n uint32_t *v5;\n if (a2 <= 0) return 1LL;\n v4 = a1;\n while (2) {\n if (a4 <= 0) return 0LL;\n v5 = a3;\n while (*v4 != *v5) {\n if (++v5 == &a3[a4]) return 0LL;\n }\n if (++v4 != &a1[a2]) continue;\n break;\n }\n return 1LL;\n}" + }, + { + "index": 878, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int test_tuple[], int tuple_size, int K[], int K_size) {\n for (int i = 0; i < tuple_size; i++) {\n bool found = false;\n for (int j = 0; j < K_size; j++) {\n if (test_tuple[i] == K[j]) {\n found = true;\n break;\n }\n }\n if (!found) {\n return false;\n }\n }\n return true;\n}", + "test": "int main() {\n\n int tuple1[] = {3, 5, 6, 5, 3, 6};\n\n int K1[] = {3, 6, 5};\n\n assert(func0(tuple1, 6, K1, 3) == true);\n\n\n\n int tuple2[] = {4, 5, 6, 4, 6, 5};\n\n int K2[] = {4, 5, 6};\n\n assert(func0(tuple2, 6, K2, 3) == true);\n\n\n\n int tuple3[] = {9, 8, 7, 6, 8, 9};\n\n int K3[] = {9, 8, 1};\n\n assert(func0(tuple3, 6, K3, 3) == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1336 \nlea -0x1(%rsi),%eax\nmov %rdi,%r8\nlea 0x4(%rdi,%rax,4),%r9\nlea -0x1(%rcx),%eax\nlea 0x4(%rdx,%rax,4),%rdi\nnopl 0x0(%rax,%rax,1)\ntest %ecx,%ecx\njle 1340 \nmov (%r8),%esi\nmov %rdx,%rax\njmp 1329 \nnopl 0x0(%rax)\nadd $0x4,%rax\ncmp %rdi,%rax\nje 1340 \ncmp (%rax),%esi\njne 1320 \nadd $0x4,%r8\ncmp %r9,%r8\njne 1310 \nmov $0x1,%eax\nretq\nnopl 0x0(%rax)\nxor %eax,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1336\nmovsxd rsi, esi\nmovsxd rax, ecx\nlea r8, [rdi+rsi*4]\nlea rsi, [rdx+rax*4]\ntest ecx, ecx\njle short loc_1340\nnop word ptr [rax+rax+00h]\nloc_1310:\nmov ecx, [rdi]\nmov rax, rdx\njmp short loc_1329\nloc_1320:\nadd rax, 4\ncmp rax, rsi\njz short loc_1340\nloc_1329:\ncmp ecx, [rax]\njnz short loc_1320\nadd rdi, 4\ncmp rdi, r8\njnz short loc_1310\nloc_1336:\nmov eax, 1\nretn\nloc_1340:\nxor eax, eax\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2, _DWORD *a3, int a4)\n{\n _DWORD *v4; // r8\n _DWORD *v5; // rax\n\n if ( a2 <= 0 )\n return 1LL;\n v4 = &a1[a2];\n if ( a4 > 0 )\n {\n do\n {\n v5 = a3;\n while ( *a1 != *v5 )\n {\n if ( ++v5 == &a3[a4] )\n return 0LL;\n }\n ++a1;\n }\n while ( a1 != v4 );\n return 1LL;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_12F0:\nendbr64\ntest esi, esi\njle short loc_1336\nmovsxd rsi, esi\nmovsxd rax, ecx\nlea r8, [rdi+rsi*4]\nlea rsi, [rdx+rax*4]\ntest ecx, ecx\njle short loc_1340\nnop word ptr [rax+rax+00h]\nloc_1310:\nmov ecx, [rdi]\nmov rax, rdx\njmp short loc_1329\nloc_1320:\nadd rax, 4\ncmp rax, rsi\njz short loc_1340\nloc_1329:\ncmp ecx, [rax]\njnz short loc_1320\nadd rdi, 4\ncmp rdi, r8\njnz short loc_1310\nloc_1336:\nmov eax, 1\nretn\nloc_1340:\nxor eax, eax\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12F0(_DWORD *a1, int a2, _DWORD *a3, int a4)\n{\n _DWORD *v4; // r8\n _DWORD *v5; // rax\n\n if ( a2 <= 0 )\n return 1LL;\n v4 = &a1[a2];\n if ( a4 > 0 )\n {\n do\n {\n v5 = a3;\n while ( *a1 != *v5 )\n {\n if ( ++v5 == &a3[a4] )\n return 0LL;\n }\n ++a1;\n }\n while ( a1 != v4 );\n return 1LL;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12F0(uint32_t *a1, int a2, uint32_t *a3, int a4) {\n uint32_t *v4;\n uint32_t *v5;\n if (a2 <= 0) return 1LL;\n v4 = &a1[a2];\n if (a4 > 0) {\n do {\n v5 = a3;\n while (*a1 != *v5) {\n if (++v5 == &a3[a4]) return 0LL;\n }\n ++a1;\n } while (a1 != v4);\n return 1LL;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2, uint32_t *a3, int a4) {\n uint32_t *v4;\n uint32_t *v5;\n if (a2 <= 0) return 1LL;\n v4 = &a1[a2];\n if (a4 > 0) {\n do {\n v5 = a3;\n while (*a1 != *v5) {\n if (++v5 == &a3[a4]) return 0LL;\n }\n ++a1;\n } while (a1 != v4);\n return 1LL;\n }\n return 0LL;\n}" + }, + { + "index": 879, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n", + "func": "char *func0(const char *text) {\n regex_t regex;\n int result;\n char *pattern = \"a.*?b$\";\n result = regcomp(®ex, pattern, REG_EXTENDED);\n if (result) {\n return (\"Regex compilation failed.\");\n }\n result = regexec(®ex, text, 0, NULL, 0);\n if (!result) {\n return (\"Found a match!\");\n } else if (result == REG_NOMATCH) {\n return (\"Not matched!\");\n } else {\n return (\"Regex match failed.\");\n }\n regfree(®ex);\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"aabbbbd\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"aabAbbbc\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"accddbbjjjb\"), \"Found a match!\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x70,%rsp\nmov %rdi,-0x68(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0xe19(%rip),%rax\nmov %rax,-0x58(%rbp)\nmov -0x58(%rbp),%rcx\nlea -0x50(%rbp),%rax\nmov $0x1,%edx\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 10b0 \nmov %eax,-0x5c(%rbp)\ncmpl $0x0,-0x5c(%rbp)\nje 121d \nlea 0xdf4(%rip),%rax\njmp 1265 \nmov -0x68(%rbp),%rsi\nlea -0x50(%rbp),%rax\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rax,%rdi\ncallq 10d0 \nmov %eax,-0x5c(%rbp)\ncmpl $0x0,-0x5c(%rbp)\njne 124f \nlea 0xddc(%rip),%rax\njmp 1265 \ncmpl $0x1,-0x5c(%rbp)\njne 125e \nlea 0xddc(%rip),%rax\njmp 1265 \nlea 0xde0(%rip),%rax\nmov -0x8(%rbp),%rdx\nxor %fs:0x28,%rdx\nje 1279 \ncallq 1090 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aAB; \"a.*?b$\"\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+var_5C], eax\ncmp [rbp+var_5C], 0\njz short loc_121D\nlea rax, aRegexCompilati; \"Regex compilation failed.\"\njmp short loc_1265\nloc_121D:\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_5C], eax\ncmp [rbp+var_5C], 0\njnz short loc_124F\nlea rax, aFoundAMatch; \"Found a match!\"\njmp short loc_1265\nloc_124F:\ncmp [rbp+var_5C], 1\njnz short loc_125E\nlea rax, s2; \"Not matched!\"\njmp short loc_1265\nloc_125E:\nlea rax, aRegexMatchFail; \"Regex match failed.\"\nloc_1265:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1279\ncall ___stack_chk_fail\nlocret_1279:\nleave\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n int v2; // [rsp+14h] [rbp-5Ch]\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n unsigned __int64 v4; // [rsp+68h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"a.*?b$\", 1) )\n return \"Regex compilation failed.\";\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n if ( !v2 )\n return \"Found a match!\";\n if ( v2 == 1 )\n return \"Not matched!\";\n return \"Regex match failed.\";\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aAB; \"a.*?b$\"\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+var_5C], eax\ncmp [rbp+var_5C], 0\njz short loc_121D\nlea rax, aRegexCompilati; \"Regex compilation failed.\"\njmp short loc_1265\nloc_121D:\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_5C], eax\ncmp [rbp+var_5C], 0\njnz short loc_124F\nlea rax, aFoundAMatch; \"Found a match!\"\njmp short loc_1265\nloc_124F:\ncmp [rbp+var_5C], 1\njnz short loc_125E\nlea rax, s2; \"Not matched!\"\njmp short loc_1265\nloc_125E:\nlea rax, aRegexMatchFail; \"Regex match failed.\"\nloc_1265:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1279\ncall ___stack_chk_fail\nlocret_1279:\nleave\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_11C9(const char *a1)\n{\n int v2; // [rsp+14h] [rbp-5Ch]\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n unsigned __int64 v4; // [rsp+68h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"a.*?b$\", 1) )\n return \"Regex compilation failed.\";\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n if ( !v2 )\n return \"Found a match!\";\n if ( v2 == 1 )\n return \"Not matched!\";\n return \"Regex match failed.\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_11C9(const char *a1) {\n int v2;\n regex_t preg;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n if (regcomp(&preg, \"a.*?b$\", 1)) return \"Regex compilation failed.\";\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n if (!v2) return \"Found a match!\";\n if (v2 == 1) return \"Not matched!\";\n return \"Regex match failed.\";\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n int v2;\n regex_t preg;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n if (regcomp(&preg, \"a.*?b$\", 1)) return \"Regex compilation failed.\";\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n if (!v2) return \"Found a match!\";\n if (v2 == 1) return \"Not matched!\";\n return \"Regex match failed.\";\n}" + }, + { + "index": 879, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n", + "func": "char *func0(const char *text) {\n regex_t regex;\n int result;\n char *pattern = \"a.*?b$\";\n result = regcomp(®ex, pattern, REG_EXTENDED);\n if (result) {\n return (\"Regex compilation failed.\");\n }\n result = regexec(®ex, text, 0, NULL, 0);\n if (!result) {\n return (\"Found a match!\");\n } else if (result == REG_NOMATCH) {\n return (\"Not matched!\");\n } else {\n return (\"Regex match failed.\");\n }\n regfree(®ex);\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"aabbbbd\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"aabAbbbc\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"accddbbjjjb\"), \"Found a match!\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nsub $0x50,%rsp\nmov %rdi,%rbx\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nmov $0x1,%edx\nlea 0xe7a(%rip),%rsi\ncallq 10a0 \nmov %eax,%edx\nlea 0xe3e(%rip),%rax\ntest %edx,%edx\nje 11fc \nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 123b \nadd $0x50,%rsp\npop %rbx\nretq\nmov %rsp,%rdi\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rbx,%rsi\ncallq 10b0 \nmov %eax,%edx\nlea 0xde4(%rip),%rax\ntest %edx,%edx\nje 11e6 \ncmp $0x1,%edx\nlea 0xde5(%rip),%rax\nlea 0xe05(%rip),%rdx\ncmovne %rdx,%rax\njmp 11e6 \ncallq 1080 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbx\nsub rsp, 50h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+58h+var_10], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"a.*?b$\"\ncall _regcomp\nmov edx, eax\nlea rax, aRegexCompilati; \"Regex compilation failed.\"\ntest edx, edx\njz short loc_121C\nloc_1206:\nmov rdx, [rsp+58h+var_10]\nsub rdx, fs:28h\njnz short loc_125B\nadd rsp, 50h\npop rbx\nretn\nloc_121C:\nmov rdi, rsp; preg\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\ncall _regexec\nmov edx, eax\nlea rax, aFoundAMatch; \"Found a match!\"\ntest edx, edx\njz short loc_1206\ncmp edx, 1\nlea rax, aRegexMatchFail; \"Regex match failed.\"\nlea rdx, s2; \"Not matched!\"\ncmovz rax, rdx\njmp short loc_1206\nloc_125B:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // edx\n const char *result; // rax\n int v3; // edx\n regex_t v4; // [rsp+0h] [rbp-58h] BYREF\n unsigned __int64 v5; // [rsp+48h] [rbp-10h]\n\n v5 = __readfsqword(0x28u);\n v1 = regcomp(&v4, \"a.*?b$\", 1);\n result = \"Regex compilation failed.\";\n if ( !v1 )\n {\n v3 = regexec(&v4, string, 0LL, 0LL, 0);\n result = \"Found a match!\";\n if ( v3 )\n {\n result = \"Regex match failed.\";\n if ( v3 == 1 )\n return \"Not matched!\";\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbx\nsub rsp, 50h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+58h+var_10], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"a.*?b$\"\ncall _regcomp\nmov edx, eax\nlea rax, aRegexCompilati; \"Regex compilation failed.\"\ntest edx, edx\njz short loc_121C\nloc_1206:\nmov rdx, [rsp+58h+var_10]\nsub rdx, fs:28h\njnz short loc_125B\nadd rsp, 50h\npop rbx\nretn\nloc_121C:\nmov rdi, rsp; preg\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\ncall _regexec\nmov edx, eax\nlea rax, aFoundAMatch; \"Found a match!\"\ntest edx, edx\njz short loc_1206\ncmp edx, 1\nlea rax, aRegexMatchFail; \"Regex match failed.\"\nlea rdx, s2; \"Not matched!\"\ncmovz rax, rdx\njmp short loc_1206\nloc_125B:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_11C9(char *string)\n{\n int v1; // edx\n const char *result; // rax\n int v3; // edx\n regex_t v4; // [rsp+0h] [rbp-58h] BYREF\n unsigned __int64 v5; // [rsp+48h] [rbp-10h]\n\n v5 = __readfsqword(0x28u);\n v1 = regcomp(&v4, \"a.*?b$\", 1);\n result = \"Regex compilation failed.\";\n if ( !v1 )\n {\n v3 = regexec(&v4, string, 0LL, 0LL, 0);\n result = \"Found a match!\";\n if ( v3 )\n {\n result = \"Regex match failed.\";\n if ( v3 == 1 )\n return \"Not matched!\";\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_11C9(char *string) {\n int v1;\n const char *result;\n int v3;\n regex_t v4;\n unsigned long long v5;\n v5 = __readfsqword(40u);\n v1 = regcomp(&v4, \"a.*?b$\", 1);\n result = \"Regex compilation failed.\";\n if (!v1) {\n v3 = regexec(&v4, string, 0LL, 0LL, 0);\n result = \"Found a match!\";\n if (v3) {\n result = \"Regex match failed.\";\n if (v3 == 1) return \"Not matched!\";\n }\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n const char *result;\n int v3;\n regex_t v4;\n unsigned long long v5;\n v5 = __readfsqword(40u);\n v1 = regcomp(&v4, \"a.*?b$\", 1);\n result = \"Regex compilation failed.\";\n if (!v1) {\n v3 = regexec(&v4, string, 0LL, 0LL, 0);\n result = \"Found a match!\";\n if (v3) {\n result = \"Regex match failed.\";\n if (v3 == 1) return \"Not matched!\";\n }\n }\n return result;\n}" + }, + { + "index": 879, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n", + "func": "char *func0(const char *text) {\n regex_t regex;\n int result;\n char *pattern = \"a.*?b$\";\n result = regcomp(®ex, pattern, REG_EXTENDED);\n if (result) {\n return (\"Regex compilation failed.\");\n }\n result = regexec(®ex, text, 0, NULL, 0);\n if (!result) {\n return (\"Found a match!\");\n } else if (result == REG_NOMATCH) {\n return (\"Not matched!\");\n } else {\n return (\"Regex match failed.\");\n }\n regfree(®ex);\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"aabbbbd\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"aabAbbbc\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"accddbbjjjb\"), \"Found a match!\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov $0x1,%edx\nlea 0xdac(%rip),%rsi\npush %rbp\nmov %rdi,%rbp\nsub $0x58,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%r12\nmov %r12,%rdi\ncallq 10a0 \nmov %eax,%r8d\nlea 0xd51(%rip),%rax\ntest %r8d,%r8d\nje 12f0 \nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 1323 \nadd $0x58,%rsp\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax)\nxor %edx,%edx\nxor %ecx,%ecx\nmov %rbp,%rsi\nmov %r12,%rdi\ncallq 10b0 \nmov %eax,%edx\nlea 0xcfc(%rip),%rax\ntest %edx,%edx\nje 12d4 \ncmp $0x1,%edx\nlea 0xcfd(%rip),%rax\nlea 0xd1d(%rip),%rdx\ncmovne %rdx,%rax\njmp 12d4 \ncallq 1080 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"a.*?b$\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nmov edx, eax\nlea rax, aRegexCompilati; \"Regex compilation failed.\"\ntest edx, edx\njz short loc_1300\nloc_12E1:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_1336\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1300:\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov edx, eax\nlea rax, aFoundAMatch; \"Found a match!\"\ntest edx, edx\njz short loc_12E1\ncmp edx, 1\nlea rax, aRegexMatchFail; \"Regex match failed.\"\nlea rdx, s2; \"Not matched!\"\ncmovz rax, rdx\njmp short loc_12E1\nloc_1336:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // edx\n const char *result; // rax\n int v3; // edx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n v1 = regcomp(&_0, \"a.*?b$\", 1);\n result = \"Regex compilation failed.\";\n if ( !v1 )\n {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n result = \"Found a match!\";\n if ( v3 )\n {\n result = \"Regex match failed.\";\n if ( v3 == 1 )\n return \"Not matched!\";\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_12A0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"a.*?b$\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nmov edx, eax\nlea rax, aRegexCompilati; \"Regex compilation failed.\"\ntest edx, edx\njz short loc_1300\nloc_12E1:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_1336\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1300:\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov edx, eax\nlea rax, aFoundAMatch; \"Found a match!\"\ntest edx, edx\njz short loc_12E1\ncmp edx, 1\nlea rax, aRegexMatchFail; \"Regex match failed.\"\nlea rdx, s2; \"Not matched!\"\ncmovz rax, rdx\njmp short loc_12E1\nloc_1336:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_12A0(char *string)\n{\n int v1; // edx\n const char *result; // rax\n int v3; // edx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n v1 = regcomp(&_0, \"a.*?b$\", 1);\n result = \"Regex compilation failed.\";\n if ( !v1 )\n {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n result = \"Found a match!\";\n if ( v3 )\n {\n result = \"Regex match failed.\";\n if ( v3 == 1 )\n return \"Not matched!\";\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_12A0(char *string) {\n int v1;\n const char *result;\n int v3;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n v1 = regcomp(&_0, \"a.*?b$\", 1);\n result = \"Regex compilation failed.\";\n if (!v1) {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n result = \"Found a match!\";\n if (v3) {\n result = \"Regex match failed.\";\n if (v3 == 1) return \"Not matched!\";\n }\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n const char *result;\n int v3;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n v1 = regcomp(&_0, \"a.*?b$\", 1);\n result = \"Regex compilation failed.\";\n if (!v1) {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n result = \"Found a match!\";\n if (v3) {\n result = \"Regex match failed.\";\n if (v3 == 1) return \"Not matched!\";\n }\n }\n return result;\n}" + }, + { + "index": 879, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n", + "func": "char *func0(const char *text) {\n regex_t regex;\n int result;\n char *pattern = \"a.*?b$\";\n result = regcomp(®ex, pattern, REG_EXTENDED);\n if (result) {\n return (\"Regex compilation failed.\");\n }\n result = regexec(®ex, text, 0, NULL, 0);\n if (!result) {\n return (\"Found a match!\");\n } else if (result == REG_NOMATCH) {\n return (\"Not matched!\");\n } else {\n return (\"Regex match failed.\");\n }\n regfree(®ex);\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"aabbbbd\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"aabAbbbc\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"accddbbjjjb\"), \"Found a match!\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov $0x1,%edx\nlea 0xdac(%rip),%rsi\npush %rbp\nmov %rdi,%rbp\nsub $0x58,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%r12\nmov %r12,%rdi\ncallq 10a0 \nmov %eax,%r8d\nlea 0xd51(%rip),%rax\ntest %r8d,%r8d\nje 12f0 \nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 1323 \nadd $0x58,%rsp\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax)\nxor %edx,%edx\nxor %ecx,%ecx\nmov %rbp,%rsi\nmov %r12,%rdi\ncallq 10b0 \nmov %eax,%edx\nlea 0xcfc(%rip),%rax\ntest %edx,%edx\nje 12d4 \ncmp $0x1,%edx\nlea 0xcfd(%rip),%rax\nlea 0xd1d(%rip),%rdx\ncmovne %rdx,%rax\njmp 12d4 \ncallq 1080 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"a.*?b$\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nmov edx, eax\nlea rax, aRegexCompilati; \"Regex compilation failed.\"\ntest edx, edx\njz short loc_1300\nloc_12E1:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_1336\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1300:\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov edx, eax\nlea rax, aFoundAMatch; \"Found a match!\"\ntest edx, edx\njz short loc_12E1\ncmp edx, 1\nlea rax, aRegexMatchFail; \"Regex match failed.\"\nlea rdx, s2; \"Not matched!\"\ncmovz rax, rdx\njmp short loc_12E1\nloc_1336:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // edx\n const char *result; // rax\n int v3; // edx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n v1 = regcomp(&_0, \"a.*?b$\", 1);\n result = \"Regex compilation failed.\";\n if ( !v1 )\n {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n result = \"Found a match!\";\n if ( v3 )\n {\n result = \"Regex match failed.\";\n if ( v3 == 1 )\n return \"Not matched!\";\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_12A0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"a.*?b$\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nmov edx, eax\nlea rax, aRegexCompilati; \"Regex compilation failed.\"\ntest edx, edx\njz short loc_1300\nloc_12E1:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_1336\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1300:\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov edx, eax\nlea rax, aFoundAMatch; \"Found a match!\"\ntest edx, edx\njz short loc_12E1\ncmp edx, 1\nlea rax, aRegexMatchFail; \"Regex match failed.\"\nlea rdx, s2; \"Not matched!\"\ncmovz rax, rdx\njmp short loc_12E1\nloc_1336:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_12A0(char *string)\n{\n int v1; // edx\n const char *result; // rax\n int v3; // edx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n v1 = regcomp(&_0, \"a.*?b$\", 1);\n result = \"Regex compilation failed.\";\n if ( !v1 )\n {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n result = \"Found a match!\";\n if ( v3 )\n {\n result = \"Regex match failed.\";\n if ( v3 == 1 )\n return \"Not matched!\";\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_12A0(char *string) {\n int v1;\n const char *result;\n int v3;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n v1 = regcomp(&_0, \"a.*?b$\", 1);\n result = \"Regex compilation failed.\";\n if (!v1) {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n result = \"Found a match!\";\n if (v3) {\n result = \"Regex match failed.\";\n if (v3 == 1) return \"Not matched!\";\n }\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n const char *result;\n int v3;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n v1 = regcomp(&_0, \"a.*?b$\", 1);\n result = \"Regex compilation failed.\";\n if (!v1) {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n result = \"Found a match!\";\n if (v3) {\n result = \"Regex match failed.\";\n if (v3 == 1) return \"Not matched!\";\n }\n }\n return result;\n}" + }, + { + "index": 880, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "const char* func0(int a, int b, int c) {\n if ((b * b) - (4 * a * c) > 0) {\n return \"2 solutions\";\n } else if ((b * b) - (4 * a * c) == 0) {\n return \"1 solution\";\n } else {\n return \"No solutions\";\n }\n}", + "test": "int main() {\n\n assert(func0(2, 5, 2) == \"2 solutions\");\n\n assert(func0(1, 1, 1) == \"No solutions\");\n\n assert(func0(1, 2, 1) == \"1 solution\");\n\n \n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov %esi,-0x8(%rbp)\nmov %edx,-0xc(%rbp)\nmov -0x8(%rbp),%eax\nimul %eax,%eax\nmov %eax,%edx\nmov -0x4(%rbp),%eax\nimul -0xc(%rbp),%eax\nshl $0x2,%eax\nsub %eax,%edx\nmov %edx,%eax\ntest %eax,%eax\njle 117d \nlea 0xe8d(%rip),%rax\njmp 11a3 \nmov -0x8(%rbp),%eax\nimul %eax,%eax\nmov %eax,%edx\nmov -0x4(%rbp),%eax\nimul -0xc(%rbp),%eax\nshl $0x2,%eax\ncmp %eax,%edx\njne 119c \nlea 0xe7a(%rip),%rax\njmp 11a3 \nlea 0xe7c(%rip),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov [rbp+var_C], edx\nmov eax, [rbp+var_8]\nimul eax, eax\nmov ecx, eax\nmov eax, [rbp+var_4]\nimul eax, [rbp+var_C]\nlea edx, ds:0[rax*4]\nmov eax, ecx\nsub eax, edx\ntest eax, eax\njle short loc_1181\nlea rax, a2Solutions; \"2 solutions\"\njmp short loc_11A7\nloc_1181:\nmov eax, [rbp+var_8]\nimul eax, eax\nmov edx, eax\nmov eax, [rbp+var_4]\nimul eax, [rbp+var_C]\nshl eax, 2\ncmp edx, eax\njnz short loc_11A0\nlea rax, a1Solution; \"1 solution\"\njmp short loc_11A7\nloc_11A0:\nlea rax, aNoSolutions; \"No solutions\"\nloc_11A7:\npop rbp\nretn", + "ida_pseudo": "const char *__fastcall func0(int a1, int a2, int a3)\n{\n if ( a2 * a2 - 4 * a3 * a1 > 0 )\n return \"2 solutions\";\n if ( a2 * a2 == 4 * a3 * a1 )\n return \"1 solution\";\n return \"No solutions\";\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov [rbp+var_C], edx\nmov eax, [rbp+var_8]\nimul eax, eax\nmov ecx, eax\nmov eax, [rbp+var_4]\nimul eax, [rbp+var_C]\nlea edx, ds:0[rax*4]\nmov eax, ecx\nsub eax, edx\ntest eax, eax\njle short loc_1181\nlea rax, a2Solutions; \"2 solutions\"\njmp short loc_11A7\nloc_1181:\nmov eax, [rbp+var_8]\nimul eax, eax\nmov edx, eax\nmov eax, [rbp+var_4]\nimul eax, [rbp+var_C]\nshl eax, 2\ncmp edx, eax\njnz short loc_11A0\nlea rax, a1Solution; \"1 solution\"\njmp short loc_11A7\nloc_11A0:\nlea rax, aNoSolutions; \"No solutions\"\nloc_11A7:\npop rbp\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1149(int a1, int a2, int a3)\n{\n if ( a2 * a2 - 4 * a3 * a1 > 0 )\n return \"2 solutions\";\n if ( a2 * a2 == 4 * a3 * a1 )\n return \"1 solution\";\n return \"No solutions\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char* sub_1149(int a1, int a2, int a3) {\n if (a2 * a2 - 4 * a3 * a1 > 0) return \"2 solutions\";\n if (a2 * a2 == 4 * a3 * a1) return \"1 solution\";\n return \"No solutions\";\n}", + "ida_pseudo_norm": "const char* func0(int a1, int a2, int a3) {\n if (a2 * a2 - 4 * a3 * a1 > 0) return \"2 solutions\";\n if (a2 * a2 == 4 * a3 * a1) return \"1 solution\";\n return \"No solutions\";\n}" + }, + { + "index": 881, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int list1[], int size) {\n int first_even = -1;\n int first_odd = -1;\n for (int i = 0; i < size; i++) {\n if (list1[i] % 2 == 0) {\n first_even = list1[i];\n break;\n }\n }\n for (int i = 0; i < size; i++) {\n if (list1[i] % 2 != 0) {\n first_odd = list1[i];\n break;\n }\n }\n return first_even + first_odd;\n}", + "test": "int main() {\n\n int list1[] = {1, 3, 5, 7, 4, 1, 6, 8};\n\n int list2[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n int list3[] = {1, 5, 7, 9, 10};\n\n \n\n assert(func0(list1, 8) == 5);\n\n assert(func0(list2, 10) == 3);\n\n assert(func0(list3, 5) == 11);\n\n \n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0xffffffff,-0x10(%rbp)\nmovl $0xffffffff,-0xc(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11cb \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nand $0x1,%eax\ntest %eax,%eax\njne 11c7 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x10(%rbp)\njmp 11d3 \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 118f \nmovl $0x0,-0x4(%rbp)\njmp 1218 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nand $0x1,%eax\ntest %eax,%eax\nje 1214 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0xc(%rbp)\njmp 1220 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11dc \nmov -0x10(%rbp),%edx\nmov -0xc(%rbp),%eax\nadd %edx,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_10], 0FFFFFFFFh\nmov [rbp+var_C], 0FFFFFFFFh\nmov [rbp+var_8], 0\njmp short loc_11CB\nloc_118F:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njnz short loc_11C7\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_10], eax\njmp short loc_11D3\nloc_11C7:\nadd [rbp+var_8], 1\nloc_11CB:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_118F\nloc_11D3:\nmov [rbp+var_4], 0\njmp short loc_1218\nloc_11DC:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njz short loc_1214\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\njmp short loc_1220\nloc_1214:\nadd [rbp+var_4], 1\nloc_1218:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11DC\nloc_1220:\nmov edx, [rbp+var_10]\nmov eax, [rbp+var_C]\nadd eax, edx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int v3; // [rsp+Ch] [rbp-10h]\n int v4; // [rsp+10h] [rbp-Ch]\n int i; // [rsp+14h] [rbp-8h]\n int j; // [rsp+18h] [rbp-4h]\n\n v3 = -1;\n v4 = -1;\n for ( i = 0; i < a2; ++i )\n {\n if ( (*(_DWORD *)(4LL * i + a1) & 1) == 0 )\n {\n v3 = *(_DWORD *)(4LL * i + a1);\n break;\n }\n }\n for ( j = 0; j < a2; ++j )\n {\n if ( (*(_DWORD *)(4LL * j + a1) & 1) != 0 )\n {\n v4 = *(_DWORD *)(4LL * j + a1);\n return (unsigned int)(v3 + v4);\n }\n }\n return (unsigned int)(v3 + v4);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_10], 0FFFFFFFFh\nmov [rbp+var_C], 0FFFFFFFFh\nmov [rbp+var_8], 0\njmp short loc_11CB\nloc_118F:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njnz short loc_11C7\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_10], eax\njmp short loc_11D3\nloc_11C7:\nadd [rbp+var_8], 1\nloc_11CB:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_118F\nloc_11D3:\nmov [rbp+var_4], 0\njmp short loc_1218\nloc_11DC:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nand eax, 1\ntest eax, eax\njz short loc_1214\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_C], eax\njmp short loc_1220\nloc_1214:\nadd [rbp+var_4], 1\nloc_1218:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11DC\nloc_1220:\nmov edx, [rbp+var_10]\nmov eax, [rbp+var_C]\nadd eax, edx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int v3; // [rsp+Ch] [rbp-10h]\n int v4; // [rsp+10h] [rbp-Ch]\n int i; // [rsp+14h] [rbp-8h]\n int j; // [rsp+18h] [rbp-4h]\n\n v3 = -1;\n v4 = -1;\n for ( i = 0; i < a2; ++i )\n {\n if ( (*(_DWORD *)(4LL * i + a1) & 1) == 0 )\n {\n v3 = *(_DWORD *)(4LL * i + a1);\n break;\n }\n }\n for ( j = 0; j < a2; ++j )\n {\n if ( (*(_DWORD *)(4LL * j + a1) & 1) != 0 )\n {\n v4 = *(_DWORD *)(4LL * j + a1);\n return (unsigned int)(v3 + v4);\n }\n }\n return (unsigned int)(v3 + v4);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int v3;\n int v4;\n int i;\n int j;\n v3 = -1;\n v4 = -1;\n for (i = 0; i < a2; ++i) {\n if ((*(uint32_t *)(4LL * i + a1) & 1) == 0) {\n v3 = *(uint32_t *)(4LL * i + a1);\n break;\n }\n }\n for (j = 0; j < a2; ++j) {\n if ((*(uint32_t *)(4LL * j + a1) & 1) != 0) {\n v4 = *(uint32_t *)(4LL * j + a1);\n return (unsigned int)(v3 + v4);\n }\n }\n return (unsigned int)(v3 + v4);\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int v3;\n int v4;\n int i;\n int j;\n v3 = -1;\n v4 = -1;\n for (i = 0; i < a2; ++i) {\n if ((*(uint32_t *)(4LL * i + a1) & 1) == 0) {\n v3 = *(uint32_t *)(4LL * i + a1);\n break;\n }\n }\n for (j = 0; j < a2; ++j) {\n if ((*(uint32_t *)(4LL * j + a1) & 1) != 0) {\n v4 = *(uint32_t *)(4LL * j + a1);\n return (unsigned int)(v3 + v4);\n }\n }\n return (unsigned int)(v3 + v4);\n}" + }, + { + "index": 881, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int list1[], int size) {\n int first_even = -1;\n int first_odd = -1;\n for (int i = 0; i < size; i++) {\n if (list1[i] % 2 == 0) {\n first_even = list1[i];\n break;\n }\n }\n for (int i = 0; i < size; i++) {\n if (list1[i] % 2 != 0) {\n first_odd = list1[i];\n break;\n }\n }\n return first_even + first_odd;\n}", + "test": "int main() {\n\n int list1[] = {1, 3, 5, 7, 4, 1, 6, 8};\n\n int list2[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n int list3[] = {1, 5, 7, 9, 10};\n\n \n\n assert(func0(list1, 8) == 5);\n\n assert(func0(list2, 10) == 3);\n\n assert(func0(list3, 5) == 11);\n\n \n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11a8 \nmov %rdi,%rdx\nlea -0x1(%rsi),%eax\nlea 0x4(%rdi,%rax,4),%rsi\nmov (%rdi),%ecx\ntest $0x1,%cl\nje 1191 \nadd $0x4,%rdi\ncmp %rsi,%rdi\njne 117c \nmov $0xffffffff,%ecx\nmov (%rdx),%eax\ntest $0x1,%al\njne 11a5 \nadd $0x4,%rdx\ncmp %rsi,%rdx\njne 1191 \nmov $0xffffffff,%eax\nadd %ecx,%eax\nretq\nmov $0xffffffff,%ecx\nmov $0xffffffff,%eax\njmp 11a5 \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11A7\nmov rdx, rdi\nmovsxd rsi, esi\nlea rsi, [rdi+rsi*4]\nloc_117B:\nmov ecx, [rdi]\ntest cl, 1\njz short loc_1190\nadd rdi, 4\ncmp rdi, rsi\njnz short loc_117B\nmov ecx, 0FFFFFFFFh\nloc_1190:\nmov eax, [rdx]\ntest al, 1\njnz short loc_11A4\nadd rdx, 4\ncmp rdx, rsi\njnz short loc_1190\nmov eax, 0FFFFFFFFh\nloc_11A4:\nadd eax, ecx\nretn\nloc_11A7:\nmov ecx, 0FFFFFFFFh\nmov eax, 0FFFFFFFFh\njmp short loc_11A4", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int *v2; // rdx\n int *v3; // rsi\n int v4; // ecx\n int v5; // eax\n\n if ( a2 <= 0 )\n {\n v4 = -1;\n v5 = -1;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n do\n {\n v4 = *a1;\n if ( (*a1 & 1) == 0 )\n goto LABEL_6;\n ++a1;\n }\n while ( a1 != v3 );\n v4 = -1;\nLABEL_6:\n while ( 1 )\n {\n v5 = *v2;\n if ( (*v2 & 1) != 0 )\n break;\n if ( ++v2 == v3 )\n {\n v5 = -1;\n return (unsigned int)(v4 + v5);\n }\n }\n }\n return (unsigned int)(v4 + v5);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11A7\nmov rdx, rdi\nmovsxd rsi, esi\nlea rsi, [rdi+rsi*4]\nloc_117B:\nmov ecx, [rdi]\ntest cl, 1\njz short loc_1190\nadd rdi, 4\ncmp rdi, rsi\njnz short loc_117B\nmov ecx, 0FFFFFFFFh\nloc_1190:\nmov eax, [rdx]\ntest al, 1\njnz short loc_11A4\nadd rdx, 4\ncmp rdx, rsi\njnz short loc_1190\nmov eax, 0FFFFFFFFh\nloc_11A4:\nadd eax, ecx\nretn\nloc_11A7:\nmov ecx, 0FFFFFFFFh\nmov eax, 0FFFFFFFFh\njmp short loc_11A4", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int *a1, int a2)\n{\n int *v2; // rdx\n int *v3; // rsi\n int v4; // ecx\n int v5; // eax\n\n if ( a2 <= 0 )\n {\n v4 = -1;\n v5 = -1;\n }\n else\n {\n v2 = a1;\n v3 = &a1[a2];\n do\n {\n v4 = *a1;\n if ( (*a1 & 1) == 0 )\n goto LABEL_6;\n ++a1;\n }\n while ( a1 != v3 );\n v4 = -1;\nLABEL_6:\n while ( 1 )\n {\n v5 = *v2;\n if ( (*v2 & 1) != 0 )\n break;\n if ( ++v2 == v3 )\n {\n v5 = -1;\n return (unsigned int)(v4 + v5);\n }\n }\n }\n return (unsigned int)(v4 + v5);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int *a1, int a2) {\n int *v2;\n int *v3;\n int v4;\n int v5;\n if (a2 <= 0) {\n v4 = -1;\n v5 = -1;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n do {\n v4 = *a1;\n if ((*a1 & 1) == 0) goto LABEL_6;\n ++a1;\n } while (a1 != v3);\n v4 = -1;\n LABEL_6:\n while (1) {\n v5 = *v2;\n if ((*v2 & 1) != 0) break;\n if (++v2 == v3) {\n v5 = -1;\n return (unsigned int)(v4 + v5);\n }\n }\n }\n return (unsigned int)(v4 + v5);\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int *v2;\n int *v3;\n int v4;\n int v5;\n if (a2 <= 0) {\n v4 = -1;\n v5 = -1;\n } else {\n v2 = a1;\n v3 = &a1[a2];\n do {\n v4 = *a1;\n if ((*a1 & 1) == 0) goto LABEL_6;\n ++a1;\n } while (a1 != v3);\n v4 = -1;\n LABEL_6:\n while (1) {\n v5 = *v2;\n if ((*v2 & 1) != 0) break;\n if (++v2 == v3) {\n v5 = -1;\n return (unsigned int)(v4 + v5);\n }\n }\n }\n return (unsigned int)(v4 + v5);\n}" + }, + { + "index": 881, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int list1[], int size) {\n int first_even = -1;\n int first_odd = -1;\n for (int i = 0; i < size; i++) {\n if (list1[i] % 2 == 0) {\n first_even = list1[i];\n break;\n }\n }\n for (int i = 0; i < size; i++) {\n if (list1[i] % 2 != 0) {\n first_odd = list1[i];\n break;\n }\n }\n return first_even + first_odd;\n}", + "test": "int main() {\n\n int list1[] = {1, 3, 5, 7, 4, 1, 6, 8};\n\n int list2[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n int list3[] = {1, 5, 7, 9, 10};\n\n \n\n assert(func0(list1, 8) == 5);\n\n assert(func0(list2, 10) == 3);\n\n assert(func0(list3, 5) == 11);\n\n \n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1344 \nlea -0x1(%rsi),%eax\nmov %rdi,%rdx\nlea 0x4(%rdi,%rax,4),%rcx\njmp 1311 \nnopl (%rax)\nadd $0x4,%rdx\ncmp %rcx,%rdx\nje 1338 \nmov (%rdx),%eax\ntest $0x1,%al\njne 1308 \njmp 1329 \nnopl 0x0(%rax)\nadd $0x4,%rdi\ncmp %rcx,%rdi\nje 1340 \nmov (%rdi),%edx\ntest $0x1,%dl\nje 1320 \nadd %edx,%eax\nretq\nnopl 0x0(%rax,%rax,1)\nmov $0xffffffff,%eax\njmp 1329 \nsub $0x1,%eax\nretq\nmov $0xfffffffe,%eax\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_12E4\nmovsxd rsi, esi\nmov rdx, rdi\nlea rcx, [rdi+rsi*4]\njmp short loc_12B1\nloc_12A8:\nadd rdx, 4\ncmp rdx, rcx\njz short loc_12D8\nloc_12B1:\nmov eax, [rdx]\ntest al, 1\njnz short loc_12A8\njmp short loc_12C9\nloc_12C0:\nadd rdi, 4\ncmp rdi, rcx\njz short loc_12E0\nloc_12C9:\nmov edx, [rdi]\ntest dl, 1\njz short loc_12C0\nadd eax, edx\nretn\nloc_12D8:\nmov eax, 0FFFFFFFFh\njmp short loc_12C9\nloc_12E0:\nsub eax, 1\nretn\nloc_12E4:\nmov eax, 0FFFFFFFEh\nretn", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int *v2; // rdx\n int *v3; // rcx\n int v4; // eax\n\n if ( a2 <= 0 )\n return 4294967294LL;\n v2 = a1;\n v3 = &a1[a2];\n while ( 1 )\n {\n v4 = *v2;\n if ( (*v2 & 1) == 0 )\n break;\n if ( ++v2 == v3 )\n {\n v4 = -1;\n goto LABEL_7;\n }\n }\n do\n {\nLABEL_7:\n if ( (*a1 & 1) != 0 )\n return (unsigned int)(*a1 + v4);\n ++a1;\n }\n while ( a1 != v3 );\n return (unsigned int)(v4 - 1);\n}", + "ida_strip_asm": "sub_1290:\nendbr64\ntest esi, esi\njle short loc_12E4\nmovsxd rsi, esi\nmov rdx, rdi\nlea rcx, [rdi+rsi*4]\njmp short loc_12B1\nloc_12A8:\nadd rdx, 4\ncmp rdx, rcx\njz short loc_12D8\nloc_12B1:\nmov eax, [rdx]\ntest al, 1\njnz short loc_12A8\njmp short loc_12C9\nloc_12C0:\nadd rdi, 4\ncmp rdi, rcx\njz short loc_12E0\nloc_12C9:\nmov edx, [rdi]\ntest dl, 1\njz short loc_12C0\nadd eax, edx\nretn\nloc_12D8:\nmov eax, 0FFFFFFFFh\njmp short loc_12C9\nloc_12E0:\nsub eax, 1\nretn\nloc_12E4:\nmov eax, 0FFFFFFFEh\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1290(int *a1, int a2)\n{\n int *v2; // rdx\n int *v3; // rcx\n int v4; // eax\n\n if ( a2 <= 0 )\n return 4294967294LL;\n v2 = a1;\n v3 = &a1[a2];\n while ( 1 )\n {\n v4 = *v2;\n if ( (*v2 & 1) == 0 )\n break;\n if ( ++v2 == v3 )\n {\n v4 = -1;\n goto LABEL_7;\n }\n }\n do\n {\nLABEL_7:\n if ( (*a1 & 1) != 0 )\n return (unsigned int)(*a1 + v4);\n ++a1;\n }\n while ( a1 != v3 );\n return (unsigned int)(v4 - 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1290(int *a1, int a2) {\n int *v2;\n int *v3;\n int v4;\n if (a2 <= 0) return 4294967294LL;\n v2 = a1;\n v3 = &a1[a2];\n while (1) {\n v4 = *v2;\n if ((*v2 & 1) == 0) break;\n if (++v2 == v3) {\n v4 = -1;\n goto LABEL_7;\n }\n }\n do {\n LABEL_7:\n if ((*a1 & 1) != 0) return (unsigned int)(*a1 + v4);\n ++a1;\n } while (a1 != v3);\n return (unsigned int)(v4 - 1);\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int *v2;\n int *v3;\n int v4;\n if (a2 <= 0) return 4294967294LL;\n v2 = a1;\n v3 = &a1[a2];\n while (1) {\n v4 = *v2;\n if ((*v2 & 1) == 0) break;\n if (++v2 == v3) {\n v4 = -1;\n goto LABEL_7;\n }\n }\n do {\n LABEL_7:\n if ((*a1 & 1) != 0) return (unsigned int)(*a1 + v4);\n ++a1;\n } while (a1 != v3);\n return (unsigned int)(v4 - 1);\n}" + }, + { + "index": 881, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int list1[], int size) {\n int first_even = -1;\n int first_odd = -1;\n for (int i = 0; i < size; i++) {\n if (list1[i] % 2 == 0) {\n first_even = list1[i];\n break;\n }\n }\n for (int i = 0; i < size; i++) {\n if (list1[i] % 2 != 0) {\n first_odd = list1[i];\n break;\n }\n }\n return first_even + first_odd;\n}", + "test": "int main() {\n\n int list1[] = {1, 3, 5, 7, 4, 1, 6, 8};\n\n int list2[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};\n\n int list3[] = {1, 5, 7, 9, 10};\n\n \n\n assert(func0(list1, 8) == 5);\n\n assert(func0(list2, 10) == 3);\n\n assert(func0(list3, 5) == 11);\n\n \n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 12f4 \nlea -0x1(%rsi),%eax\nmov %rdi,%rdx\nlea 0x4(%rdi,%rax,4),%rcx\njmp 12c1 \nnopl (%rax)\nadd $0x4,%rdx\ncmp %rcx,%rdx\nje 12e8 \nmov (%rdx),%eax\ntest $0x1,%al\njne 12b8 \njmp 12d9 \nnopl 0x0(%rax)\nadd $0x4,%rdi\ncmp %rcx,%rdi\nje 12f0 \nmov (%rdi),%edx\ntest $0x1,%dl\nje 12d0 \nadd %edx,%eax\nretq\nnopl 0x0(%rax,%rax,1)\nmov $0xffffffff,%eax\njmp 12d9 \nsub $0x1,%eax\nretq\nmov $0xfffffffe,%eax\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_12E4\nmovsxd rsi, esi\nmov rdx, rdi\nlea rcx, [rdi+rsi*4]\njmp short loc_12B1\nloc_12A8:\nadd rdx, 4\ncmp rdx, rcx\njz short loc_12D8\nloc_12B1:\nmov eax, [rdx]\ntest al, 1\njnz short loc_12A8\njmp short loc_12C9\nloc_12C0:\nadd rdi, 4\ncmp rdi, rcx\njz short loc_12E0\nloc_12C9:\nmov edx, [rdi]\ntest dl, 1\njz short loc_12C0\nadd eax, edx\nretn\nloc_12D8:\nmov eax, 0FFFFFFFFh\njmp short loc_12C9\nloc_12E0:\nsub eax, 1\nretn\nloc_12E4:\nmov eax, 0FFFFFFFEh\nretn", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int *v2; // rdx\n int *v3; // rcx\n int v4; // eax\n\n if ( a2 <= 0 )\n return 4294967294LL;\n v2 = a1;\n v3 = &a1[a2];\n while ( 1 )\n {\n v4 = *v2;\n if ( (*v2 & 1) == 0 )\n break;\n if ( ++v2 == v3 )\n {\n v4 = -1;\n goto LABEL_7;\n }\n }\n do\n {\nLABEL_7:\n if ( (*a1 & 1) != 0 )\n return (unsigned int)(*a1 + v4);\n ++a1;\n }\n while ( a1 != v3 );\n return (unsigned int)(v4 - 1);\n}", + "ida_strip_asm": "sub_1290:\nendbr64\ntest esi, esi\njle short loc_12E4\nmovsxd rsi, esi\nmov rdx, rdi\nlea rcx, [rdi+rsi*4]\njmp short loc_12B1\nloc_12A8:\nadd rdx, 4\ncmp rdx, rcx\njz short loc_12D8\nloc_12B1:\nmov eax, [rdx]\ntest al, 1\njnz short loc_12A8\njmp short loc_12C9\nloc_12C0:\nadd rdi, 4\ncmp rdi, rcx\njz short loc_12E0\nloc_12C9:\nmov edx, [rdi]\ntest dl, 1\njz short loc_12C0\nadd eax, edx\nretn\nloc_12D8:\nmov eax, 0FFFFFFFFh\njmp short loc_12C9\nloc_12E0:\nsub eax, 1\nretn\nloc_12E4:\nmov eax, 0FFFFFFFEh\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1290(int *a1, int a2)\n{\n int *v2; // rdx\n int *v3; // rcx\n int v4; // eax\n\n if ( a2 <= 0 )\n return 4294967294LL;\n v2 = a1;\n v3 = &a1[a2];\n while ( 1 )\n {\n v4 = *v2;\n if ( (*v2 & 1) == 0 )\n break;\n if ( ++v2 == v3 )\n {\n v4 = -1;\n goto LABEL_7;\n }\n }\n do\n {\nLABEL_7:\n if ( (*a1 & 1) != 0 )\n return (unsigned int)(*a1 + v4);\n ++a1;\n }\n while ( a1 != v3 );\n return (unsigned int)(v4 - 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1290(int *a1, int a2) {\n int *v2;\n int *v3;\n int v4;\n if (a2 <= 0) return 4294967294LL;\n v2 = a1;\n v3 = &a1[a2];\n while (1) {\n v4 = *v2;\n if ((*v2 & 1) == 0) break;\n if (++v2 == v3) {\n v4 = -1;\n goto LABEL_7;\n }\n }\n do {\n LABEL_7:\n if ((*a1 & 1) != 0) return (unsigned int)(*a1 + v4);\n ++a1;\n } while (a1 != v3);\n return (unsigned int)(v4 - 1);\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int *v2;\n int *v3;\n int v4;\n if (a2 <= 0) return 4294967294LL;\n v2 = a1;\n v3 = &a1[a2];\n while (1) {\n v4 = *v2;\n if ((*v2 & 1) == 0) break;\n if (++v2 == v3) {\n v4 = -1;\n goto LABEL_7;\n }\n }\n do {\n LABEL_7:\n if ((*a1 & 1) != 0) return (unsigned int)(*a1 + v4);\n ++a1;\n } while (a1 != v3);\n return (unsigned int)(v4 - 1);\n}" + }, + { + "index": 882, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int b, int h) {\n int perimeter = 2 * (b + h);\n return perimeter;\n}", + "test": "int main() {\n\n assert(func0(10, 20) == 60);\n\n assert(func0(15, 20) == 70);\n\n assert(func0(8, 9) == 34);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov -0x14(%rbp),%edx\nmov -0x18(%rbp),%eax\nadd %edx,%eax\nadd %eax,%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov edx, [rbp+var_14]\nmov eax, [rbp+var_18]\nadd eax, edx\nadd eax, eax\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n return (unsigned int)(2 * (a1 + a2));\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov edx, [rbp+var_14]\nmov eax, [rbp+var_18]\nadd eax, edx\nadd eax, eax\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2)\n{\n return (unsigned int)(2 * (a1 + a2));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2) { return (unsigned int)(2 * (a1 + a2)); }", + "ida_pseudo_norm": "long long func0(int a1, int a2) { return (unsigned int)(2 * (a1 + a2)); }" + }, + { + "index": 883, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int nums[], int size, int m, int n, int* result_size) {\n static int result[100];\n int count = 0;\n for (int i = 0; i < size; i++) {\n if (nums[i] % m == 0 && nums[i] % n == 0) {\n result[count++] = nums[i];\n }\n }\n *result_size = count;\n return result;\n}", + "test": "int main() {\n\n int size;\n\n int result1_size;\n\n int arr1[] = {19, 65, 57, 39, 152, 639, 121, 44, 90, 190};\n\n int expected1[] = {152, 44};\n\n int* result1 = func0(arr1, 10, 2, 4, &result1_size);\n\n assert(result1_size == 2);\n\n for (int i = 0; i < result1_size; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n \n\n int result2_size;\n\n int arr2[] = {1, 2, 3, 5, 7, 8, 10};\n\n int expected2[] = {10};\n\n int* result2 = func0(arr2, 7, 2, 5, &result2_size);\n\n assert(result2_size == 1);\n\n for (int i = 0; i < result2_size; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n \n\n int result3_size;\n\n int arr3[] = {10, 15, 14, 13, 18, 12, 20};\n\n int expected3[] = {10, 20};\n\n int* result3 = func0(arr3, 7, 10, 5, &result3_size);\n\n assert(result3_size == 2);\n\n for (int i = 0; i < result3_size; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmov %ecx,-0x24(%rbp)\nmov %r8,-0x30(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 120a \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncltd\nidivl -0x20(%rbp)\nmov %edx,%eax\ntest %eax,%eax\njne 1206 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncltd\nidivl -0x24(%rbp)\nmov %edx,%eax\ntest %eax,%eax\njne 1206 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x8(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x8(%rbp)\nmov (%rcx),%edx\ncltq\nlea 0x0(,%rax,4),%rcx\nlea 0x2e3d(%rip),%rax\nmov %edx,(%rcx,%rax,1)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1192 \nmov -0x30(%rbp),%rax\nmov -0x8(%rbp),%edx\nmov %edx,(%rax)\nlea 0x2e1e(%rip),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_24], ecx\nmov [rbp+var_30], r8\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_120A\nloc_1192:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncdq\nidiv [rbp+var_20]\nmov eax, edx\ntest eax, eax\njnz short loc_1206\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncdq\nidiv [rbp+var_24]\nmov eax, edx\ntest eax, eax\njnz short loc_1206\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_8]\nlea edx, [rax+1]\nmov [rbp+var_8], edx\nmov edx, [rcx]\ncdqe\nlea rcx, ds:0[rax*4]\nlea rax, result_1\nmov [rcx+rax], edx\nloc_1206:\nadd [rbp+var_4], 1\nloc_120A:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1192\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_8]\nmov [rax], edx\nlea rax, result_1\npop rbp\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, int a3, int a4, _DWORD *a5)\n{\n int v5; // eax\n int v7; // [rsp+28h] [rbp-8h]\n int i; // [rsp+2Ch] [rbp-4h]\n\n v7 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( !(*(_DWORD *)(4LL * i + a1) % a3) && !(*(_DWORD *)(4LL * i + a1) % a4) )\n {\n v5 = v7++;\n result_1[v5] = *(_DWORD *)(4LL * i + a1);\n }\n }\n *a5 = v7;\n return result_1;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_24], ecx\nmov [rbp+var_30], r8\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_120A\nloc_1192:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncdq\nidiv [rbp+var_20]\nmov eax, edx\ntest eax, eax\njnz short loc_1206\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncdq\nidiv [rbp+var_24]\nmov eax, edx\ntest eax, eax\njnz short loc_1206\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_8]\nlea edx, [rax+1]\nmov [rbp+var_8], edx\nmov edx, [rcx]\ncdqe\nlea rcx, ds:0[rax*4]\nlea rax, unk_4040\nmov [rcx+rax], edx\nloc_1206:\nadd [rbp+var_4], 1\nloc_120A:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1192\nmov rax, [rbp+var_30]\nmov edx, [rbp+var_8]\nmov [rax], edx\nlea rax, unk_4040\npop rbp\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1169(__int64 a1, int a2, int a3, int a4, _DWORD *a5)\n{\n int v5; // eax\n int v7; // [rsp+28h] [rbp-8h]\n int i; // [rsp+2Ch] [rbp-4h]\n\n v7 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( !(*(_DWORD *)(4LL * i + a1) % a3) && !(*(_DWORD *)(4LL * i + a1) % a4) )\n {\n v5 = v7++;\n dword_4040[v5] = *(_DWORD *)(4LL * i + a1);\n }\n }\n *a5 = v7;\n return dword_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1169(long long a1, int a2, int a3, int a4, uint32_t *a5) {\n int v5;\n int v7;\n int i;\n v7 = 0;\n for (i = 0; i < a2; ++i) {\n if (!(*(uint32_t *)(4LL * i + a1) % a3) &&\n !(*(uint32_t *)(4LL * i + a1) % a4)) {\n v5 = v7++;\n dword_4040[v5] = *(uint32_t *)(4LL * i + a1);\n }\n }\n *a5 = v7;\n return dword_4040;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, int a3, int a4, uint32_t *a5) {\n int v5;\n int v7;\n int i;\n v7 = 0;\n for (i = 0; i < a2; ++i) {\n if (!(*(uint32_t *)(4LL * i + a1) % a3) &&\n !(*(uint32_t *)(4LL * i + a1) % a4)) {\n v5 = v7++;\n result_1[v5] = *(uint32_t *)(4LL * i + a1);\n }\n }\n *a5 = v7;\n return result_1;\n}" + }, + { + "index": 883, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int nums[], int size, int m, int n, int* result_size) {\n static int result[100];\n int count = 0;\n for (int i = 0; i < size; i++) {\n if (nums[i] % m == 0 && nums[i] % n == 0) {\n result[count++] = nums[i];\n }\n }\n *result_size = count;\n return result;\n}", + "test": "int main() {\n\n int size;\n\n int result1_size;\n\n int arr1[] = {19, 65, 57, 39, 152, 639, 121, 44, 90, 190};\n\n int expected1[] = {152, 44};\n\n int* result1 = func0(arr1, 10, 2, 4, &result1_size);\n\n assert(result1_size == 2);\n\n for (int i = 0; i < result1_size; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n \n\n int result2_size;\n\n int arr2[] = {1, 2, 3, 5, 7, 8, 10};\n\n int expected2[] = {10};\n\n int* result2 = func0(arr2, 7, 2, 5, &result2_size);\n\n assert(result2_size == 1);\n\n for (int i = 0; i < result2_size; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n \n\n int result3_size;\n\n int arr3[] = {10, 15, 14, 13, 18, 12, 20};\n\n int expected3[] = {10, 20};\n\n int* result3 = func0(arr3, 7, 10, 5, &result3_size);\n\n assert(result3_size == 2);\n\n for (int i = 0; i < result3_size; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11ba \npush %rbx\nmov %edx,%r10d\nmov %rdi,%r9\nlea -0x1(%rsi),%eax\nlea 0x4(%rdi,%rax,4),%rdi\nmov $0x0,%r11d\nlea 0x2eb3(%rip),%rbx\njmp 1198 \nadd $0x4,%r9\ncmp %rdi,%r9\nje 11cb \nmov (%r9),%esi\nmov %esi,%eax\ncltd\nidiv %r10d\ntest %edx,%edx\njne 118f \nmov %esi,%eax\ncltd\nidiv %ecx\ntest %edx,%edx\njne 118f \nmovslq %r11d,%rax\nmov %esi,(%rbx,%rax,4)\nlea 0x1(%r11),%r11d\njmp 118f \nmov $0x0,%r11d\nmov %r11d,(%r8)\nlea 0x2e76(%rip),%rax\nretq\nmov %r11d,(%r8)\nlea 0x2e6b(%rip),%rax\npop %rbx\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11BB\npush rbx\nmov r10d, edx\nmov r11d, ecx\nmov r9, rdi\nmovsxd rsi, esi\nlea rsi, [rdi+rsi*4]\nmov edi, 0\nlea rbx, result_1\njmp short loc_1199\nloc_1190:\nadd r9, 4\ncmp r9, rsi\njz short loc_11CB\nloc_1199:\nmov ecx, [r9]\nmov eax, ecx\ncdq\nidiv r10d\ntest edx, edx\njnz short loc_1190\nmov eax, ecx\ncdq\nidiv r11d\ntest edx, edx\njnz short loc_1190\nmovsxd rax, edi\nmov [rbx+rax*4], ecx\nlea edi, [rdi+1]\njmp short loc_1190\nloc_11BB:\nmov edi, 0\nmov [r8], edi\nlea rax, result_1\nretn\nloc_11CB:\nmov [r8], edi\nlea rax, result_1\npop rbx\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2, int a3, int a4, _DWORD *a5)\n{\n int *v6; // r9\n int *v7; // rsi\n int v8; // edi\n int v9; // ecx\n\n if ( a2 <= 0 )\n {\n *a5 = 0;\n return result_1;\n }\n else\n {\n v6 = a1;\n v7 = &a1[a2];\n v8 = 0;\n do\n {\n v9 = *v6;\n if ( !(*v6 % a3) && !(v9 % a4) )\n result_1[v8++] = v9;\n ++v6;\n }\n while ( v6 != v7 );\n *a5 = v8;\n return result_1;\n }\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11BB\npush rbx\nmov r10d, edx\nmov r11d, ecx\nmov r9, rdi\nmovsxd rsi, esi\nlea rsi, [rdi+rsi*4]\nmov edi, 0\nlea rbx, unk_4040\njmp short loc_1199\nloc_1190:\nadd r9, 4\ncmp r9, rsi\njz short loc_11CB\nloc_1199:\nmov ecx, [r9]\nmov eax, ecx\ncdq\nidiv r10d\ntest edx, edx\njnz short loc_1190\nmov eax, ecx\ncdq\nidiv r11d\ntest edx, edx\njnz short loc_1190\nmovsxd rax, edi\nmov [rbx+rax*4], ecx\nlea edi, [rdi+1]\njmp short loc_1190\nloc_11BB:\nmov edi, 0\nmov [r8], edi\nlea rax, unk_4040\nretn\nloc_11CB:\nmov [r8], edi\nlea rax, unk_4040\npop rbx\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1169(int *a1, int a2, int a3, int a4, _DWORD *a5)\n{\n int *v6; // r9\n int *v7; // rsi\n int v8; // edi\n int v9; // ecx\n\n if ( a2 <= 0 )\n {\n *a5 = 0;\n return dword_4040;\n }\n else\n {\n v6 = a1;\n v7 = &a1[a2];\n v8 = 0;\n do\n {\n v9 = *v6;\n if ( !(*v6 % a3) && !(v9 % a4) )\n dword_4040[v8++] = v9;\n ++v6;\n }\n while ( v6 != v7 );\n *a5 = v8;\n return dword_4040;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1169(int *a1, int a2, int a3, int a4, uint32_t *a5) {\n int *v6;\n int *v7;\n int v8;\n int v9;\n if (a2 <= 0) {\n *a5 = 0;\n return dword_4040;\n } else {\n v6 = a1;\n v7 = &a1[a2];\n v8 = 0;\n do {\n v9 = *v6;\n if (!(*v6 % a3) && !(v9 % a4)) dword_4040[v8++] = v9;\n ++v6;\n } while (v6 != v7);\n *a5 = v8;\n return dword_4040;\n }\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2, int a3, int a4, uint32_t *a5) {\n int *v6;\n int *v7;\n int v8;\n int v9;\n if (a2 <= 0) {\n *a5 = 0;\n return result_1;\n } else {\n v6 = a1;\n v7 = &a1[a2];\n v8 = 0;\n do {\n v9 = *v6;\n if (!(*v6 % a3) && !(v9 % a4)) result_1[v8++] = v9;\n ++v6;\n } while (v6 != v7);\n *a5 = v8;\n return result_1;\n }\n}" + }, + { + "index": 883, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int nums[], int size, int m, int n, int* result_size) {\n static int result[100];\n int count = 0;\n for (int i = 0; i < size; i++) {\n if (nums[i] % m == 0 && nums[i] % n == 0) {\n result[count++] = nums[i];\n }\n }\n *result_size = count;\n return result;\n}", + "test": "int main() {\n\n int size;\n\n int result1_size;\n\n int arr1[] = {19, 65, 57, 39, 152, 639, 121, 44, 90, 190};\n\n int expected1[] = {152, 44};\n\n int* result1 = func0(arr1, 10, 2, 4, &result1_size);\n\n assert(result1_size == 2);\n\n for (int i = 0; i < result1_size; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n \n\n int result2_size;\n\n int arr2[] = {1, 2, 3, 5, 7, 8, 10};\n\n int expected2[] = {10};\n\n int* result2 = func0(arr2, 7, 2, 5, &result2_size);\n\n assert(result2_size == 1);\n\n for (int i = 0; i < result2_size; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n \n\n int result3_size;\n\n int arr3[] = {10, 15, 14, 13, 18, 12, 20};\n\n int expected3[] = {10, 20};\n\n int* result3 = func0(arr3, 7, 10, 5, &result3_size);\n\n assert(result3_size == 2);\n\n for (int i = 0; i < result3_size; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 14c8 \nlea -0x1(%rsi),%eax\npush %rbx\nmov %edx,%r11d\nxor %r10d,%r10d\nlea 0x4(%rdi,%rax,4),%r9\nlea 0x2bb2(%rip),%rbx\nxchg %ax,%ax\nmov (%rdi),%esi\nmov %esi,%eax\ncltd\nidiv %r11d\ntest %edx,%edx\njne 14af \nmov %esi,%eax\ncltd\nidiv %ecx\ntest %edx,%edx\njne 14af \nmovslq %r10d,%rax\nadd $0x1,%r10d\nmov %esi,(%rbx,%rax,4)\nadd $0x4,%rdi\ncmp %r9,%rdi\njne 1490 \nlea 0x2b81(%rip),%rax\nmov %r10d,(%r8)\npop %rbx\nretq\nnopl 0x0(%rax)\nxor %r10d,%r10d\nlea 0x2b6e(%rip),%rax\nmov %r10d,(%r8)\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbx\ntest esi, esi\njle short loc_13D8\nmovsxd rsi, esi\nmov r9d, edx\nmov r10d, ecx\nxor r11d, r11d\nlea rsi, [rdi+rsi*4]\nlea rbx, result_1\nloc_13A0:\nmov ecx, [rdi]\nmov eax, ecx\ncdq\nidiv r9d\ntest edx, edx\njnz short loc_13C0\nmov eax, ecx\ncdq\nidiv r10d\ntest edx, edx\njnz short loc_13C0\nmovsxd rax, r11d\nadd r11d, 1\nmov [rbx+rax*4], ecx\nloc_13C0:\nadd rdi, 4\ncmp rsi, rdi\njnz short loc_13A0\nmov rax, rbx\nmov [r8], r11d\npop rbx\nretn\nloc_13D8:\nlea rbx, result_1\nxor r11d, r11d\nmov rax, rbx\nmov [r8], r11d\npop rbx\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2, int a3, int a4, _DWORD *a5)\n{\n int v6; // r11d\n int *v7; // rsi\n int v8; // ecx\n __int64 v9; // rax\n _DWORD *result; // rax\n\n if ( a2 <= 0 )\n {\n result = result_1;\n *a5 = 0;\n }\n else\n {\n v6 = 0;\n v7 = &a1[a2];\n do\n {\n v8 = *a1;\n if ( !(*a1 % a3) && !(v8 % a4) )\n {\n v9 = v6++;\n result_1[v9] = v8;\n }\n ++a1;\n }\n while ( v7 != a1 );\n result = result_1;\n *a5 = v6;\n }\n return result;\n}", + "ida_strip_asm": "sub_1380:\nendbr64\npush rbx\ntest esi, esi\njle short loc_13D8\nmovsxd rsi, esi\nmov r9d, edx\nmov r10d, ecx\nxor r11d, r11d\nlea rsi, [rdi+rsi*4]\nlea rbx, unk_4040\nloc_13A0:\nmov ecx, [rdi]\nmov eax, ecx\ncdq\nidiv r9d\ntest edx, edx\njnz short loc_13C0\nmov eax, ecx\ncdq\nidiv r10d\ntest edx, edx\njnz short loc_13C0\nmovsxd rax, r11d\nadd r11d, 1\nmov [rbx+rax*4], ecx\nloc_13C0:\nadd rdi, 4\ncmp rsi, rdi\njnz short loc_13A0\nmov rax, rbx\nmov [r8], r11d\npop rbx\nretn\nloc_13D8:\nlea rbx, unk_4040\nxor r11d, r11d\nmov rax, rbx\nmov [r8], r11d\npop rbx\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1380(int *a1, int a2, int a3, int a4, _DWORD *a5)\n{\n int v6; // r11d\n int *v7; // rsi\n int v8; // ecx\n __int64 v9; // rax\n _DWORD *result; // rax\n\n if ( a2 <= 0 )\n {\n result = dword_4040;\n *a5 = 0;\n }\n else\n {\n v6 = 0;\n v7 = &a1[a2];\n do\n {\n v8 = *a1;\n if ( !(*a1 % a3) && !(v8 % a4) )\n {\n v9 = v6++;\n dword_4040[v9] = v8;\n }\n ++a1;\n }\n while ( v7 != a1 );\n result = dword_4040;\n *a5 = v6;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1380(int *a1, int a2, int a3, int a4, uint32_t *a5) {\n int v6;\n int *v7;\n int v8;\n long long v9;\n uint32_t *result;\n if (a2 <= 0) {\n result = dword_4040;\n *a5 = 0;\n } else {\n v6 = 0;\n v7 = &a1[a2];\n do {\n v8 = *a1;\n if (!(*a1 % a3) && !(v8 % a4)) {\n v9 = v6++;\n dword_4040[v9] = v8;\n }\n ++a1;\n } while (v7 != a1);\n result = dword_4040;\n *a5 = v6;\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2, int a3, int a4, uint32_t *a5) {\n int v6;\n int *v7;\n int v8;\n long long v9;\n uint32_t *result;\n if (a2 <= 0) {\n result = result_1;\n *a5 = 0;\n } else {\n v6 = 0;\n v7 = &a1[a2];\n do {\n v8 = *a1;\n if (!(*a1 % a3) && !(v8 % a4)) {\n v9 = v6++;\n result_1[v9] = v8;\n }\n ++a1;\n } while (v7 != a1);\n result = result_1;\n *a5 = v6;\n }\n return result;\n}" + }, + { + "index": 884, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "int func0(int n, int l, int r) {\n int num = ((1 << r) - 1) ^ ((1 << (l - 1)) - 1);\n int new_num = n & num;\n if (num == new_num) {\n return 1;\n }\n return 0;\n}", + "test": "int main() {\n\n assert(func0(10, 2, 1) == 1);\n\n assert(func0(5, 2, 4) == 0);\n\n assert(func0(22, 2, 3) == 1);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov %edx,-0x1c(%rbp)\nmov -0x1c(%rbp),%eax\nmov $0x1,%edx\nmov %eax,%ecx\nshl %cl,%edx\nmov %edx,%eax\nlea -0x1(%rax),%edx\nmov -0x18(%rbp),%eax\nsub $0x1,%eax\nmov $0x1,%esi\nmov %eax,%ecx\nshl %cl,%esi\nmov %esi,%eax\nsub $0x1,%eax\nxor %edx,%eax\nmov %eax,-0x8(%rbp)\nmov -0x14(%rbp),%eax\nand -0x8(%rbp),%eax\nmov %eax,-0x4(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x4(%rbp),%eax\njne 119c \nmov $0x1,%eax\njmp 11a1 \nmov $0x0,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov eax, [rbp+var_1C]\nmov edx, 1\nmov ecx, eax\nshl edx, cl\nmov eax, edx\nlea edx, [rax-1]\nmov eax, [rbp+var_18]\nsub eax, 1\nmov esi, 1\nmov ecx, eax\nshl esi, cl\nmov eax, esi\nsub eax, 1\nxor eax, edx\nmov [rbp+var_8], eax\nmov eax, [rbp+var_14]\nand eax, [rbp+var_8]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njnz short loc_119C\nmov eax, 1\njmp short loc_11A1\nloc_119C:\nmov eax, 0\nloc_11A1:\npop rbp\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(int a1, char a2, char a3)\n{\n int v4; // [rsp+14h] [rbp-8h]\n\n v4 = ((1 << a3) - 1) ^ ((1 << (a2 - 1)) - 1);\n return v4 == (v4 & a1);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov eax, [rbp+var_1C]\nmov edx, 1\nmov ecx, eax\nshl edx, cl\nmov eax, edx\nlea edx, [rax-1]\nmov eax, [rbp+var_18]\nsub eax, 1\nmov esi, 1\nmov ecx, eax\nshl esi, cl\nmov eax, esi\nsub eax, 1\nxor eax, edx\nmov [rbp+var_8], eax\nmov eax, [rbp+var_14]\nand eax, [rbp+var_8]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njnz short loc_119C\nmov eax, 1\njmp short loc_11A1\nloc_119C:\nmov eax, 0\nloc_11A1:\npop rbp\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1149(int a1, char a2, char a3)\n{\n int v4; // [rsp+14h] [rbp-8h]\n\n v4 = ((1 << a3) - 1) ^ ((1 << (a2 - 1)) - 1);\n return v4 == (v4 & a1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1149(int a1, char a2, char a3) {\n int v4;\n v4 = ((1 << a3) - 1) ^ ((1 << (a2 - 1)) - 1);\n return v4 == (v4 & a1);\n}", + "ida_pseudo_norm": "uint8_t func0(int a1, char a2, char a3) {\n int v4;\n v4 = ((1 << a3) - 1) ^ ((1 << (a2 - 1)) - 1);\n return v4 == (v4 & a1);\n}" + }, + { + "index": 886, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "double func0(int numbers[], int size) {\n int total = 0;\n for (int i = 0; i < size; i++) {\n total += numbers[i];\n }\n return (double)total / size;\n}", + "test": "int main() {\n\n int arr1[] = {8, 2, 3, 0, 7};\n\n int arr2[] = {-10, -20, -30};\n\n int arr3[] = {19, 15, 18};\n\n \n\n assert(func0(arr1, 5) == 4.0);\n\n assert(func0(arr2, 3) == -20.0);\n\n assert(func0(arr3, 3) == 17.333333333333332);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11a5 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nadd %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1188 \ncvtsi2sdl -0x8(%rbp),%xmm0\ncvtsi2sdl -0x1c(%rbp),%xmm1\ndivsd %xmm1,%xmm0\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11A5\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_11A5:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_8]\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_1C]\ndivsd xmm0, xmm1\npop rbp\nretn", + "ida_pseudo": "double __fastcall func0(__int64 a1, int a2)\n{\n int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n v3 += *(_DWORD *)(4LL * i + a1);\n return (double)v3 / (double)a2;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11A5\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_11A5:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_8]\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_1C]\ndivsd xmm0, xmm1\npop rbp\nretn", + "ida_strip_pseudo": "double __fastcall sub_1169(__int64 a1, int a2)\n{\n int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n v3 += *(_DWORD *)(4LL * i + a1);\n return (double)v3 / (double)a2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1169(long long a1, int a2) {\n int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) v3 += *(uint32_t *)(4LL * i + a1);\n return (double)v3 / (double)a2;\n}", + "ida_pseudo_norm": "double func0(long long a1, int a2) {\n int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) v3 += *(uint32_t *)(4LL * i + a1);\n return (double)v3 / (double)a2;\n}" + }, + { + "index": 886, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "double func0(int numbers[], int size) {\n int total = 0;\n for (int i = 0; i < size; i++) {\n total += numbers[i];\n }\n return (double)total / size;\n}", + "test": "int main() {\n\n int arr1[] = {8, 2, 3, 0, 7};\n\n int arr2[] = {-10, -20, -30};\n\n int arr3[] = {19, 15, 18};\n\n \n\n assert(func0(arr1, 5) == 4.0);\n\n assert(func0(arr2, 3) == -20.0);\n\n assert(func0(arr3, 3) == 17.333333333333332);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11a1 \nmov %rdi,%rax\nlea -0x1(%rsi),%edx\nlea 0x4(%rdi,%rdx,4),%rcx\nmov $0x0,%edx\nadd (%rax),%edx\nadd $0x4,%rax\ncmp %rcx,%rax\njne 1181 \npxor %xmm0,%xmm0\ncvtsi2sd %edx,%xmm0\npxor %xmm1,%xmm1\ncvtsi2sd %esi,%xmm1\ndivsd %xmm1,%xmm0\nretq\nmov $0x0,%edx\njmp 118c \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11A0\nmov rax, rdi\nmovsxd rdx, esi\nlea rcx, [rdi+rdx*4]\nmov edx, 0\nloc_1180:\nadd edx, [rax]\nadd rax, 4\ncmp rax, rcx\njnz short loc_1180\nloc_118B:\npxor xmm0, xmm0\ncvtsi2sd xmm0, edx\npxor xmm1, xmm1\ncvtsi2sd xmm1, esi\ndivsd xmm0, xmm1\nretn\nloc_11A0:\nmov edx, 0\njmp short loc_118B", + "ida_pseudo": "double __fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n int v3; // edx\n\n if ( a2 <= 0 )\n {\n v3 = 0;\n }\n else\n {\n v2 = a1;\n v3 = 0;\n do\n v3 += *v2++;\n while ( v2 != &a1[a2] );\n }\n return (double)v3 / (double)a2;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11A0\nmov rax, rdi\nmovsxd rdx, esi\nlea rcx, [rdi+rdx*4]\nmov edx, 0\nloc_1180:\nadd edx, [rax]\nadd rax, 4\ncmp rax, rcx\njnz short loc_1180\nloc_118B:\npxor xmm0, xmm0\ncvtsi2sd xmm0, edx\npxor xmm1, xmm1\ncvtsi2sd xmm1, esi\ndivsd xmm0, xmm1\nretn\nloc_11A0:\nmov edx, 0\njmp short loc_118B", + "ida_strip_pseudo": "double __fastcall sub_1169(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n int v3; // edx\n\n if ( a2 <= 0 )\n {\n v3 = 0;\n }\n else\n {\n v2 = a1;\n v3 = 0;\n do\n v3 += *v2++;\n while ( v2 != &a1[a2] );\n }\n return (double)v3 / (double)a2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1169(uint32_t *a1, int a2) {\n uint32_t *v2;\n int v3;\n if (a2 <= 0) {\n v3 = 0;\n } else {\n v2 = a1;\n v3 = 0;\n do\n v3 += *v2++;\n while (v2 != &a1[a2]);\n }\n return (double)v3 / (double)a2;\n}", + "ida_pseudo_norm": "double func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n int v3;\n if (a2 <= 0) {\n v3 = 0;\n } else {\n v2 = a1;\n v3 = 0;\n do\n v3 += *v2++;\n while (v2 != &a1[a2]);\n }\n return (double)v3 / (double)a2;\n}" + }, + { + "index": 887, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int n) {\n if ((n ^ 1) == n - 1)\n return true;\n else\n return false;\n}", + "test": "int main() {\n\n assert(func0(5) == true);\n\n assert(func0(6) == false);\n\n assert(func0(7) == true);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nxor $0x1,%eax\nmov %eax,%edx\nmov -0x4(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,%edx\njne 116d \nmov $0x1,%eax\njmp 1172 \nmov $0x0,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov eax, [rbp+var_4]\nxor eax, 1\nmov edx, eax\nmov eax, [rbp+var_4]\nsub eax, 1\ncmp edx, eax\njnz short loc_116D\nmov eax, 1\njmp short loc_1172\nloc_116D:\nmov eax, 0\nloc_1172:\npop rbp\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(int a1)\n{\n return (a1 ^ 1) == a1 - 1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov eax, [rbp+var_4]\nxor eax, 1\nmov edx, eax\nmov eax, [rbp+var_4]\nsub eax, 1\ncmp edx, eax\njnz short loc_116D\nmov eax, 1\njmp short loc_1172\nloc_116D:\nmov eax, 0\nloc_1172:\npop rbp\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1149(int a1)\n{\n return (a1 ^ 1) == a1 - 1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1149(int a1) { return (a1 ^ 1) == a1 - 1; }", + "ida_pseudo_norm": "uint8_t func0(int a1) { return (a1 ^ 1) == a1 - 1; }" + }, + { + "index": 888, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "void func0(const int test_tup1[][2], const int test_tup2[][2], int n,\n int res[][2]) {\n for (int i = 0; i < n; i++) {\n for (int j = 0; j < 2; j++) {\n res[i][j] = test_tup1[i][j] - test_tup2[i][j];\n }\n }\n}", + "test": "int main() {\n\n int res[4][2];\n\n\n\n int test1_1[4][2] = {{1, 3}, {4, 5}, {2, 9}, {1, 10}};\n\n int test1_2[4][2] = {{6, 7}, {3, 9}, {1, 1}, {7, 3}};\n\n int expected1[4][2] = {{-5, -4}, {1, -4}, {1, 8}, {-6, 7}};\n\n func0(test1_1, test1_2, 4, res);\n\n for (int i = 0; i < 4; i++)\n\n for (int j = 0; j < 2; j++)\n\n assert(res[i][j] == expected1[i][j]);\n\n\n\n int test2_1[4][2] = {{13, 4}, {14, 6}, {13, 10}, {12, 11}};\n\n int test2_2[4][2] = {{19, 8}, {14, 10}, {12, 2}, {18, 4}};\n\n int expected2[4][2] = {{-6, -4}, {0, -4}, {1, 8}, {-6, 7}};\n\n func0(test2_1, test2_2, 4, res);\n\n for (int i = 0; i < 4; i++)\n\n for (int j = 0; j < 2; j++)\n\n assert(res[i][j] == expected2[i][j]);\n\n\n\n int test3_1[4][2] = {{19, 5}, {18, 7}, {19, 11}, {17, 12}};\n\n int test3_2[4][2] = {{12, 9}, {17, 11}, {13, 3}, {19, 5}};\n\n int expected3[4][2] = {{7, -4}, {1, -4}, {6, 8}, {-2, 7}};\n\n func0(test3_1, test3_2, 4, res);\n\n for (int i = 0; i < 4; i++)\n\n for (int j = 0; j < 2; j++)\n\n assert(res[i][j] == expected3[i][j]);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %edx,-0x24(%rbp)\nmov %rcx,-0x30(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11f7 \nmovl $0x0,-0x4(%rbp)\njmp 11ed \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0x4(%rbp),%eax\ncltq\nmov (%rdx,%rax,4),%ecx\nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x20(%rbp),%rax\nadd %rax,%rdx\nmov -0x4(%rbp),%eax\ncltq\nmov (%rdx,%rax,4),%eax\nmov -0x8(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rsi\nmov -0x30(%rbp),%rdx\nadd %rsi,%rdx\nsub %eax,%ecx\nmov -0x4(%rbp),%eax\ncltq\nmov %ecx,(%rdx,%rax,4)\naddl $0x1,-0x4(%rbp)\ncmpl $0x1,-0x4(%rbp)\njle 1192 \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x24(%rbp),%eax\njl 1189 \npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_30], rcx\nmov [rbp+var_8], 0\njmp short loc_11F7\nloc_1189:\nmov [rbp+var_4], 0\njmp short loc_11ED\nloc_1192:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\ncdqe\nmov ecx, [rdx+rax*4]\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_20]\nadd rdx, rax\nmov eax, [rbp+var_4]\ncdqe\nmov eax, [rdx+rax*4]\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nlea rsi, ds:0[rdx*8]\nmov rdx, [rbp+var_30]\nadd rdx, rsi\nsub ecx, eax\nmov eax, [rbp+var_4]\ncdqe\nmov [rdx+rax*4], ecx\nadd [rbp+var_4], 1\nloc_11ED:\ncmp [rbp+var_4], 1\njle short loc_1192\nadd [rbp+var_8], 1\nloc_11F7:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_24]\njl short loc_1189\nnop\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3, __int64 a4)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+28h] [rbp-8h]\n int j; // [rsp+2Ch] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a3 )\n break;\n for ( j = 0; j <= 1; ++j )\n *(_DWORD *)(8LL * (int)i + a4 + 4LL * j) = *(_DWORD *)(a1 + 8LL * (int)i + 4LL * j)\n - *(_DWORD *)(a2 + 8LL * (int)i + 4LL * j);\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_30], rcx\nmov [rbp+var_8], 0\njmp short loc_11F7\nloc_1189:\nmov [rbp+var_4], 0\njmp short loc_11ED\nloc_1192:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_4]\ncdqe\nmov ecx, [rdx+rax*4]\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_20]\nadd rdx, rax\nmov eax, [rbp+var_4]\ncdqe\nmov eax, [rdx+rax*4]\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nlea rsi, ds:0[rdx*8]\nmov rdx, [rbp+var_30]\nadd rdx, rsi\nsub ecx, eax\nmov eax, [rbp+var_4]\ncdqe\nmov [rdx+rax*4], ecx\nadd [rbp+var_4], 1\nloc_11ED:\ncmp [rbp+var_4], 1\njle short loc_1192\nadd [rbp+var_8], 1\nloc_11F7:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_24]\njl short loc_1189\nnop\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, int a3, __int64 a4)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+28h] [rbp-8h]\n int j; // [rsp+2Ch] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a3 )\n break;\n for ( j = 0; j <= 1; ++j )\n *(_DWORD *)(8LL * (int)i + a4 + 4LL * j) = *(_DWORD *)(a1 + 8LL * (int)i + 4LL * j)\n - *(_DWORD *)(a2 + 8LL * (int)i + 4LL * j);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, int a3, long long a4) {\n long long result;\n unsigned int i;\n int j;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a3) break;\n for (j = 0; j <= 1; ++j)\n *(uint32_t *)(8LL * (int)i + a4 + 4LL * j) =\n *(uint32_t *)(a1 + 8LL * (int)i + 4LL * j) -\n *(uint32_t *)(a2 + 8LL * (int)i + 4LL * j);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3, long long a4) {\n long long result;\n unsigned int i;\n int j;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a3) break;\n for (j = 0; j <= 1; ++j)\n *(uint32_t *)(8LL * (int)i + a4 + 4LL * j) =\n *(uint32_t *)(a1 + 8LL * (int)i + 4LL * j) -\n *(uint32_t *)(a2 + 8LL * (int)i + 4LL * j);\n }\n return result;\n}" + }, + { + "index": 888, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "void func0(const int test_tup1[][2], const int test_tup2[][2], int n,\n int res[][2]) {\n for (int i = 0; i < n; i++) {\n for (int j = 0; j < 2; j++) {\n res[i][j] = test_tup1[i][j] - test_tup2[i][j];\n }\n }\n}", + "test": "int main() {\n\n int res[4][2];\n\n\n\n int test1_1[4][2] = {{1, 3}, {4, 5}, {2, 9}, {1, 10}};\n\n int test1_2[4][2] = {{6, 7}, {3, 9}, {1, 1}, {7, 3}};\n\n int expected1[4][2] = {{-5, -4}, {1, -4}, {1, 8}, {-6, 7}};\n\n func0(test1_1, test1_2, 4, res);\n\n for (int i = 0; i < 4; i++)\n\n for (int j = 0; j < 2; j++)\n\n assert(res[i][j] == expected1[i][j]);\n\n\n\n int test2_1[4][2] = {{13, 4}, {14, 6}, {13, 10}, {12, 11}};\n\n int test2_2[4][2] = {{19, 8}, {14, 10}, {12, 2}, {18, 4}};\n\n int expected2[4][2] = {{-6, -4}, {0, -4}, {1, 8}, {-6, 7}};\n\n func0(test2_1, test2_2, 4, res);\n\n for (int i = 0; i < 4; i++)\n\n for (int j = 0; j < 2; j++)\n\n assert(res[i][j] == expected2[i][j]);\n\n\n\n int test3_1[4][2] = {{19, 5}, {18, 7}, {19, 11}, {17, 12}};\n\n int test3_2[4][2] = {{12, 9}, {17, 11}, {13, 3}, {19, 5}};\n\n int expected3[4][2] = {{7, -4}, {1, -4}, {6, 8}, {-2, 7}};\n\n func0(test3_1, test3_2, 4, res);\n\n for (int i = 0; i < 4; i++)\n\n for (int j = 0; j < 2; j++)\n\n assert(res[i][j] == expected3[i][j]);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edx,%edx\njle 119b \nlea -0x1(%rdx),%r8d\nmov $0x0,%eax\nmov (%rdi,%rax,8),%edx\nsub (%rsi,%rax,8),%edx\nmov %edx,(%rcx,%rax,8)\nmov 0x4(%rdi,%rax,8),%edx\nsub 0x4(%rsi,%rax,8),%edx\nmov %edx,0x4(%rcx,%rax,8)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %r8,%rdx\njne 117a \nretq\n", + "ida_asm": "func0:\nendbr64\ntest edx, edx\njle short locret_119F\nmovsxd rdx, edx\nlea r8, ds:0[rdx*8]\nmov eax, 0\nloc_1181:\nmov edx, [rdi+rax]\nsub edx, [rsi+rax]\nmov [rcx+rax], edx\nmov edx, [rdi+rax+4]\nsub edx, [rsi+rax+4]\nmov [rcx+rax+4], edx\nadd rax, 8\ncmp r8, rax\njnz short loc_1181\nlocret_119F:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, __int64 a2, int a3, __int64 a4)\n{\n __int64 v4; // rax\n\n if ( a3 > 0 )\n {\n v4 = 0LL;\n do\n {\n *(_DWORD *)(a4 + v4) = *(_DWORD *)(a1 + v4) - *(_DWORD *)(a2 + v4);\n *(_DWORD *)(a4 + v4 + 4) = *(_DWORD *)(a1 + v4 + 4) - *(_DWORD *)(a2 + v4 + 4);\n v4 += 8LL;\n }\n while ( 8LL * a3 != v4 );\n }\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest edx, edx\njle short locret_119F\nmovsxd rdx, edx\nlea r8, ds:0[rdx*8]\nmov eax, 0\nloc_1181:\nmov edx, [rdi+rax]\nsub edx, [rsi+rax]\nmov [rcx+rax], edx\nmov edx, [rdi+rax+4]\nsub edx, [rsi+rax+4]\nmov [rcx+rax+4], edx\nadd rax, 8\ncmp r8, rax\njnz short loc_1181\nlocret_119F:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1169(__int64 a1, __int64 a2, int a3, __int64 a4)\n{\n __int64 v4; // rax\n\n if ( a3 > 0 )\n {\n v4 = 0LL;\n do\n {\n *(_DWORD *)(a4 + v4) = *(_DWORD *)(a1 + v4) - *(_DWORD *)(a2 + v4);\n *(_DWORD *)(a4 + v4 + 4) = *(_DWORD *)(a1 + v4 + 4) - *(_DWORD *)(a2 + v4 + 4);\n v4 += 8LL;\n }\n while ( 8LL * a3 != v4 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1169(long long a1, long long a2, int a3, long long a4) {\n long long v4;\n if (a3 > 0) {\n v4 = 0LL;\n do {\n *(uint32_t *)(a4 + v4) = *(uint32_t *)(a1 + v4) - *(uint32_t *)(a2 + v4);\n *(uint32_t *)(a4 + v4 + 4) =\n *(uint32_t *)(a1 + v4 + 4) - *(uint32_t *)(a2 + v4 + 4);\n v4 += 8LL;\n } while (8LL * a3 != v4);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, long long a2, int a3, long long a4) {\n long long v4;\n if (a3 > 0) {\n v4 = 0LL;\n do {\n *(uint32_t *)(a4 + v4) = *(uint32_t *)(a1 + v4) - *(uint32_t *)(a2 + v4);\n *(uint32_t *)(a4 + v4 + 4) =\n *(uint32_t *)(a1 + v4 + 4) - *(uint32_t *)(a2 + v4 + 4);\n v4 += 8LL;\n } while (8LL * a3 != v4);\n }\n}" + }, + { + "index": 888, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "void func0(const int test_tup1[][2], const int test_tup2[][2], int n,\n int res[][2]) {\n for (int i = 0; i < n; i++) {\n for (int j = 0; j < 2; j++) {\n res[i][j] = test_tup1[i][j] - test_tup2[i][j];\n }\n }\n}", + "test": "int main() {\n\n int res[4][2];\n\n\n\n int test1_1[4][2] = {{1, 3}, {4, 5}, {2, 9}, {1, 10}};\n\n int test1_2[4][2] = {{6, 7}, {3, 9}, {1, 1}, {7, 3}};\n\n int expected1[4][2] = {{-5, -4}, {1, -4}, {1, 8}, {-6, 7}};\n\n func0(test1_1, test1_2, 4, res);\n\n for (int i = 0; i < 4; i++)\n\n for (int j = 0; j < 2; j++)\n\n assert(res[i][j] == expected1[i][j]);\n\n\n\n int test2_1[4][2] = {{13, 4}, {14, 6}, {13, 10}, {12, 11}};\n\n int test2_2[4][2] = {{19, 8}, {14, 10}, {12, 2}, {18, 4}};\n\n int expected2[4][2] = {{-6, -4}, {0, -4}, {1, 8}, {-6, 7}};\n\n func0(test2_1, test2_2, 4, res);\n\n for (int i = 0; i < 4; i++)\n\n for (int j = 0; j < 2; j++)\n\n assert(res[i][j] == expected2[i][j]);\n\n\n\n int test3_1[4][2] = {{19, 5}, {18, 7}, {19, 11}, {17, 12}};\n\n int test3_2[4][2] = {{12, 9}, {17, 11}, {13, 3}, {19, 5}};\n\n int expected3[4][2] = {{7, -4}, {1, -4}, {6, 8}, {-2, 7}};\n\n func0(test3_1, test3_2, 4, res);\n\n for (int i = 0; i < 4; i++)\n\n for (int j = 0; j < 2; j++)\n\n assert(res[i][j] == expected3[i][j]);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %edx,%edx\njle 1581 \nlea -0x1(%rdx),%r8d\nxor %eax,%eax\nxchg %ax,%ax\nmov (%rdi,%rax,8),%edx\nsub (%rsi,%rax,8),%edx\nmov %edx,(%rcx,%rax,8)\nmov 0x4(%rdi,%rax,8),%edx\nsub 0x4(%rsi,%rax,8),%edx\nmov %edx,0x4(%rcx,%rax,8)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rdx,%r8\njne 1560 \nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\ntest edx, edx\njle short locret_1426\nmovsxd rdx, edx\nxor eax, eax\nlea r8, ds:0[rdx*8]\nnop dword ptr [rax]\nloc_1408:\nmov edx, [rdi+rax]\nsub edx, [rsi+rax]\nmov [rcx+rax], edx\nmov edx, [rdi+rax+4]\nsub edx, [rsi+rax+4]\nmov [rcx+rax+4], edx\nadd rax, 8\ncmp r8, rax\njnz short loc_1408\nlocret_1426:\nretn", + "ida_pseudo": "void __fastcall func0(__int64 a1, __int64 a2, int a3, __int64 a4)\n{\n __int64 v4; // rax\n\n if ( a3 > 0 )\n {\n v4 = 0LL;\n do\n {\n *(_DWORD *)(a4 + v4) = *(_DWORD *)(a1 + v4) - *(_DWORD *)(a2 + v4);\n *(_DWORD *)(a4 + v4 + 4) = *(_DWORD *)(a1 + v4 + 4) - *(_DWORD *)(a2 + v4 + 4);\n v4 += 8LL;\n }\n while ( 8LL * a3 != v4 );\n }\n}", + "ida_strip_asm": "sub_13F0:\nendbr64\ntest edx, edx\njle short locret_1426\nmovsxd rdx, edx\nxor eax, eax\nlea r8, ds:0[rdx*8]\nnop dword ptr [rax]\nloc_1408:\nmov edx, [rdi+rax]\nsub edx, [rsi+rax]\nmov [rcx+rax], edx\nmov edx, [rdi+rax+4]\nsub edx, [rsi+rax+4]\nmov [rcx+rax+4], edx\nadd rax, 8\ncmp r8, rax\njnz short loc_1408\nlocret_1426:\nretn", + "ida_strip_pseudo": "void __fastcall sub_13F0(__int64 a1, __int64 a2, int a3, __int64 a4)\n{\n __int64 v4; // rax\n\n if ( a3 > 0 )\n {\n v4 = 0LL;\n do\n {\n *(_DWORD *)(a4 + v4) = *(_DWORD *)(a1 + v4) - *(_DWORD *)(a2 + v4);\n *(_DWORD *)(a4 + v4 + 4) = *(_DWORD *)(a1 + v4 + 4) - *(_DWORD *)(a2 + v4 + 4);\n v4 += 8LL;\n }\n while ( 8LL * a3 != v4 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_13F0(long long a1, long long a2, int a3, long long a4) {\n long long v4;\n if (a3 > 0) {\n v4 = 0LL;\n do {\n *(uint32_t *)(a4 + v4) = *(uint32_t *)(a1 + v4) - *(uint32_t *)(a2 + v4);\n *(uint32_t *)(a4 + v4 + 4) =\n *(uint32_t *)(a1 + v4 + 4) - *(uint32_t *)(a2 + v4 + 4);\n v4 += 8LL;\n } while (8LL * a3 != v4);\n }\n}", + "ida_pseudo_norm": "void func0(long long a1, long long a2, int a3, long long a4) {\n long long v4;\n if (a3 > 0) {\n v4 = 0LL;\n do {\n *(uint32_t *)(a4 + v4) = *(uint32_t *)(a1 + v4) - *(uint32_t *)(a2 + v4);\n *(uint32_t *)(a4 + v4 + 4) =\n *(uint32_t *)(a1 + v4 + 4) - *(uint32_t *)(a2 + v4 + 4);\n v4 += 8LL;\n } while (8LL * a3 != v4);\n }\n}" + }, + { + "index": 889, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\nint compare_desc(const void* a, const void* b) {\n\n return (*(int*)b - *(int*)a);\n\n}\n\n\n\n", + "func": "void func0(int** lists, int* sizes, int num_lists) {\n for (int i = 0; i < num_lists; i++) {\n qsort(lists[i], sizes[i], sizeof(int), compare_desc);\n }\n}", + "test": "int main() {\n\n // First test case\n\n int list1_1[] = {1, 2, 3, 4};\n\n int list1_2[] = {5, 6, 7, 8};\n\n int list1_3[] = {9, 10, 11, 12};\n\n int list1_4[] = {13, 14, 15, 16};\n\n int* lists1[] = {list1_1, list1_2, list1_3, list1_4};\n\n int sizes1[] = {4, 4, 4, 4};\n\n func0(lists1, sizes1, 4);\n\n int expected1_1[] = {4, 3, 2, 1};\n\n int expected1_2[] = {8, 7, 6, 5};\n\n int expected1_3[] = {12, 11, 10, 9};\n\n int expected1_4[] = {16, 15, 14, 13};\n\n assert(memcmp(lists1[0], expected1_1, sizeof(expected1_1)) == 0);\n\n assert(memcmp(lists1[1], expected1_2, sizeof(expected1_2)) == 0);\n\n assert(memcmp(lists1[2], expected1_3, sizeof(expected1_3)) == 0);\n\n assert(memcmp(lists1[3], expected1_4, sizeof(expected1_4)) == 0);\n\n\n\n // Second test case\n\n int list2_1[] = {1, 2};\n\n int list2_2[] = {2, 3};\n\n int list2_3[] = {3, 4};\n\n int* lists2[] = {list2_1, list2_2, list2_3};\n\n int sizes2[] = {2, 2, 2};\n\n func0(lists2, sizes2, 3);\n\n int expected2_1[] = {2, 1};\n\n int expected2_2[] = {3, 2};\n\n int expected2_3[] = {4, 3};\n\n assert(memcmp(lists2[0], expected2_1, sizeof(expected2_1)) == 0);\n\n assert(memcmp(lists2[1], expected2_2, sizeof(expected2_2)) == 0);\n\n assert(memcmp(lists2[2], expected2_3, sizeof(expected2_3)) == 0);\n\n\n\n // Third test case\n\n int list3_1[] = {10, 20};\n\n int list3_2[] = {30, 40};\n\n int* lists3[] = {list3_1, list3_2};\n\n int sizes3[] = {2, 2};\n\n func0(lists3, sizes3, 2);\n\n int expected3_1[] = {20, 10};\n\n int expected3_2[] = {40, 30};\n\n assert(memcmp(lists3[0], expected3_1, sizeof(expected3_1)) == 0);\n\n assert(memcmp(lists3[1], expected3_2, sizeof(expected3_2)) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %edx,-0x24(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 1233 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmovslq %eax,%rsi\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nlea -0x79(%rip),%rcx\nmov $0x4,%edx\nmov %rax,%rdi\ncallq 1080 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x24(%rbp),%eax\njl 11eb \nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_4], 0\njmp short loc_1236\nloc_11EB:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov eax, [rax]\nmovsxd rsi, eax; nmemb\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nlea rdx, compare_desc\nmov rcx, rdx; compar\nmov edx, 4; size\nmov rdi, rax; base\ncall _qsort\nadd [rbp+var_4], 1\nloc_1236:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_24]\njl short loc_11EB\nnop\nnop\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+2Ch] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a3 )\n break;\n qsort(*(void **)(8LL * (int)i + a1), *(int *)(4LL * (int)i + a2), 4uLL, compare_desc);\n }\n return result;\n}", + "ida_strip_asm": "sub_11CB:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_4], 0\njmp short loc_1236\nloc_11EB:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov eax, [rax]\nmovsxd rsi, eax; nmemb\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 4; size\nmov rdi, rax; base\ncall _qsort\nadd [rbp+var_4], 1\nloc_1236:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_24]\njl short loc_11EB\nnop\nnop\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11CB(__int64 a1, __int64 a2, int a3)\n{\n __int64 result; // rax\n unsigned int i; // [rsp+2Ch] [rbp-4h]\n\n for ( i = 0; ; ++i )\n {\n result = i;\n if ( (int)i >= a3 )\n break;\n qsort(*(void **)(8LL * (int)i + a1), *(int *)(4LL * (int)i + a2), 4uLL, compar);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11CB(long long a1, long long a2, int a3) {\n long long result;\n unsigned int i;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a3) break;\n qsort(*(void **)(8LL * (int)i + a1), *(int *)(4LL * (int)i + a2), 4uLL,\n compar);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3) {\n long long result;\n unsigned int i;\n for (i = 0;; ++i) {\n result = i;\n if ((int)i >= a3) break;\n qsort(*(void **)(8LL * (int)i + a1), *(int *)(4LL * (int)i + a2), 4uLL,\n compare_desc);\n }\n return result;\n}" + }, + { + "index": 889, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\nint compare_desc(const void* a, const void* b) {\n\n return (*(int*)b - *(int*)a);\n\n}\n\n\n\n", + "func": "void func0(int** lists, int* sizes, int num_lists) {\n for (int i = 0; i < num_lists; i++) {\n qsort(lists[i], sizes[i], sizeof(int), compare_desc);\n }\n}", + "test": "int main() {\n\n // First test case\n\n int list1_1[] = {1, 2, 3, 4};\n\n int list1_2[] = {5, 6, 7, 8};\n\n int list1_3[] = {9, 10, 11, 12};\n\n int list1_4[] = {13, 14, 15, 16};\n\n int* lists1[] = {list1_1, list1_2, list1_3, list1_4};\n\n int sizes1[] = {4, 4, 4, 4};\n\n func0(lists1, sizes1, 4);\n\n int expected1_1[] = {4, 3, 2, 1};\n\n int expected1_2[] = {8, 7, 6, 5};\n\n int expected1_3[] = {12, 11, 10, 9};\n\n int expected1_4[] = {16, 15, 14, 13};\n\n assert(memcmp(lists1[0], expected1_1, sizeof(expected1_1)) == 0);\n\n assert(memcmp(lists1[1], expected1_2, sizeof(expected1_2)) == 0);\n\n assert(memcmp(lists1[2], expected1_3, sizeof(expected1_3)) == 0);\n\n assert(memcmp(lists1[3], expected1_4, sizeof(expected1_4)) == 0);\n\n\n\n // Second test case\n\n int list2_1[] = {1, 2};\n\n int list2_2[] = {2, 3};\n\n int list2_3[] = {3, 4};\n\n int* lists2[] = {list2_1, list2_2, list2_3};\n\n int sizes2[] = {2, 2, 2};\n\n func0(lists2, sizes2, 3);\n\n int expected2_1[] = {2, 1};\n\n int expected2_2[] = {3, 2};\n\n int expected2_3[] = {4, 3};\n\n assert(memcmp(lists2[0], expected2_1, sizeof(expected2_1)) == 0);\n\n assert(memcmp(lists2[1], expected2_2, sizeof(expected2_2)) == 0);\n\n assert(memcmp(lists2[2], expected2_3, sizeof(expected2_3)) == 0);\n\n\n\n // Third test case\n\n int list3_1[] = {10, 20};\n\n int list3_2[] = {30, 40};\n\n int* lists3[] = {list3_1, list3_2};\n\n int sizes3[] = {2, 2};\n\n func0(lists3, sizes3, 2);\n\n int expected3_1[] = {20, 10};\n\n int expected3_2[] = {40, 30};\n\n assert(memcmp(lists3[0], expected3_1, sizeof(expected3_1)) == 0);\n\n assert(memcmp(lists3[1], expected3_2, sizeof(expected3_2)) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edx,%edx\njle 1203 \npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbp\nmov %rsi,%r12\nlea -0x1(%rdx),%r14d\nmov $0x0,%ebx\nlea -0x2f(%rip),%r13\nmovslq (%r12,%rbx,4),%rsi\nmov 0x0(%rbp,%rbx,8),%rdi\nmov %r13,%rcx\nmov $0x4,%edx\ncallq 1080 \nmov %rbx,%rax\nadd $0x1,%rbx\ncmp %r14,%rax\njne 11d8 \npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nretq\n", + "ida_asm": "func0:\nendbr64\ntest edx, edx\njle short locret_1204\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rsi\nmov rbp, rdi\nmovsxd rdx, edx\nlea r13, [rsi+rdx*4]\nlea r12, compare_desc\nloc_11D8:\nmovsxd rsi, dword ptr [rbx]; nmemb\nmov rdi, [rbp+0]; base\nmov rcx, r12; compar\nmov edx, 4; size\ncall _qsort\nadd rbx, 4\nadd rbp, 8\ncmp rbx, r13\njnz short loc_11D8\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nlocret_1204:\nretn", + "ida_pseudo": "void __fastcall func0(void **a1, int *a2, int a3)\n{\n int *v3; // rbx\n int *v5; // r13\n\n if ( a3 > 0 )\n {\n v3 = a2;\n v5 = &a2[a3];\n do\n qsort(*a1++, *v3++, 4uLL, compare_desc);\n while ( v3 != v5 );\n }\n}", + "ida_strip_asm": "sub_11B2:\nendbr64\ntest edx, edx\njle short locret_1204\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rsi\nmov rbp, rdi\nmovsxd rdx, edx\nlea r13, [rsi+rdx*4]\nlea r12, compar\nloc_11D8:\nmovsxd rsi, dword ptr [rbx]; nmemb\nmov rdi, [rbp+0]; base\nmov rcx, r12; compar\nmov edx, 4; size\ncall _qsort\nadd rbx, 4\nadd rbp, 8\ncmp rbx, r13\njnz short loc_11D8\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nlocret_1204:\nretn", + "ida_strip_pseudo": "void __fastcall sub_11B2(void **a1, int *a2, int a3)\n{\n int *v3; // rbx\n int *v5; // r13\n\n if ( a3 > 0 )\n {\n v3 = a2;\n v5 = &a2[a3];\n do\n qsort(*a1++, *v3++, 4uLL, compar);\n while ( v3 != v5 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_11B2(void **a1, int *a2, int a3) {\n int *v3;\n int *v5;\n if (a3 > 0) {\n v3 = a2;\n v5 = &a2[a3];\n do\n qsort(*a1++, *v3++, 4uLL, compar);\n while (v3 != v5);\n }\n}", + "ida_pseudo_norm": "void func0(void **a1, int *a2, int a3) {\n int *v3;\n int *v5;\n if (a3 > 0) {\n v3 = a2;\n v5 = &a2[a3];\n do\n qsort(*a1++, *v3++, 4uLL, compare_desc);\n while (v3 != v5);\n }\n}" + }, + { + "index": 889, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\nint compare_desc(const void* a, const void* b) {\n\n return (*(int*)b - *(int*)a);\n\n}\n\n\n\n", + "func": "void func0(int** lists, int* sizes, int num_lists) {\n for (int i = 0; i < num_lists; i++) {\n qsort(lists[i], sizes[i], sizeof(int), compare_desc);\n }\n}", + "test": "int main() {\n\n // First test case\n\n int list1_1[] = {1, 2, 3, 4};\n\n int list1_2[] = {5, 6, 7, 8};\n\n int list1_3[] = {9, 10, 11, 12};\n\n int list1_4[] = {13, 14, 15, 16};\n\n int* lists1[] = {list1_1, list1_2, list1_3, list1_4};\n\n int sizes1[] = {4, 4, 4, 4};\n\n func0(lists1, sizes1, 4);\n\n int expected1_1[] = {4, 3, 2, 1};\n\n int expected1_2[] = {8, 7, 6, 5};\n\n int expected1_3[] = {12, 11, 10, 9};\n\n int expected1_4[] = {16, 15, 14, 13};\n\n assert(memcmp(lists1[0], expected1_1, sizeof(expected1_1)) == 0);\n\n assert(memcmp(lists1[1], expected1_2, sizeof(expected1_2)) == 0);\n\n assert(memcmp(lists1[2], expected1_3, sizeof(expected1_3)) == 0);\n\n assert(memcmp(lists1[3], expected1_4, sizeof(expected1_4)) == 0);\n\n\n\n // Second test case\n\n int list2_1[] = {1, 2};\n\n int list2_2[] = {2, 3};\n\n int list2_3[] = {3, 4};\n\n int* lists2[] = {list2_1, list2_2, list2_3};\n\n int sizes2[] = {2, 2, 2};\n\n func0(lists2, sizes2, 3);\n\n int expected2_1[] = {2, 1};\n\n int expected2_2[] = {3, 2};\n\n int expected2_3[] = {4, 3};\n\n assert(memcmp(lists2[0], expected2_1, sizeof(expected2_1)) == 0);\n\n assert(memcmp(lists2[1], expected2_2, sizeof(expected2_2)) == 0);\n\n assert(memcmp(lists2[2], expected2_3, sizeof(expected2_3)) == 0);\n\n\n\n // Third test case\n\n int list3_1[] = {10, 20};\n\n int list3_2[] = {30, 40};\n\n int* lists3[] = {list3_1, list3_2};\n\n int sizes3[] = {2, 2};\n\n func0(lists3, sizes3, 2);\n\n int expected3_1[] = {20, 10};\n\n int expected3_2[] = {40, 30};\n\n assert(memcmp(lists3[0], expected3_1, sizeof(expected3_1)) == 0);\n\n assert(memcmp(lists3[1], expected3_2, sizeof(expected3_2)) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %edx,%edx\njle 16d8 \npush %r14\nmov %rdi,%r14\npush %r13\nlea -0x1(%rdx),%r13d\npush %r12\nlea -0x2c(%rip),%r12\npush %rbp\nmov %rsi,%rbp\npush %rbx\nxor %ebx,%ebx\nnopl 0x0(%rax,%rax,1)\nmovslq 0x0(%rbp,%rbx,4),%rsi\nmov (%r14,%rbx,8),%rdi\nmov %r12,%rcx\nmov $0x4,%edx\ncallq 1070 \nmov %rbx,%rax\nadd $0x1,%rbx\ncmp %rax,%r13\njne 16a8 \npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopl 0x0(%rax,%rax,1)\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\ntest edx, edx\njle short locret_1620\npush r13\nmovsxd rdx, edx\npush r12\nlea r13, [rsi+rdx*4]\nlea r12, compare_desc\npush rbp\nmov rbp, rdi\npush rbx\nmov rbx, rsi\nsub rsp, 8\nnop word ptr [rax+rax+00000000h]\nloc_15F0:\nmovsxd rsi, dword ptr [rbx]; nmemb\nmov rdi, [rbp+0]; base\nmov rcx, r12; compar\nmov edx, 4; size\nadd rbx, 4\nadd rbp, 8\ncall _qsort\ncmp rbx, r13\njnz short loc_15F0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nlocret_1620:\nretn", + "ida_pseudo": "void __fastcall func0(void **a1, int *a2, int a3)\n{\n int *v3; // r13\n int *v5; // rbx\n size_t v6; // rsi\n void *v7; // rdi\n\n if ( a3 > 0 )\n {\n v3 = &a2[a3];\n v5 = a2;\n do\n {\n v6 = *v5;\n v7 = *a1;\n ++v5;\n ++a1;\n qsort(v7, v6, 4uLL, compare_desc);\n }\n while ( v5 != v3 );\n }\n}", + "ida_strip_asm": "sub_15C0:\nendbr64\ntest edx, edx\njle short locret_1620\npush r13\nmovsxd rdx, edx\npush r12\nlea r13, [rsi+rdx*4]\nlea r12, compar\npush rbp\nmov rbp, rdi\npush rbx\nmov rbx, rsi\nsub rsp, 8\nnop word ptr [rax+rax+00000000h]\nloc_15F0:\nmovsxd rsi, dword ptr [rbx]; nmemb\nmov rdi, [rbp+0]; base\nmov rcx, r12; compar\nmov edx, 4; size\nadd rbx, 4\nadd rbp, 8\ncall _qsort\ncmp rbx, r13\njnz short loc_15F0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nlocret_1620:\nretn", + "ida_strip_pseudo": "void __fastcall sub_15C0(void **a1, int *a2, int a3)\n{\n int *v3; // r13\n int *v5; // rbx\n size_t v6; // rsi\n void *v7; // rdi\n\n if ( a3 > 0 )\n {\n v3 = &a2[a3];\n v5 = a2;\n do\n {\n v6 = *v5;\n v7 = *a1;\n ++v5;\n ++a1;\n qsort(v7, v6, 4uLL, compar);\n }\n while ( v5 != v3 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_15C0(void **a1, int *a2, int a3) {\n int *v3;\n int *v5;\n unsigned int v6;\n void *v7;\n if (a3 > 0) {\n v3 = &a2[a3];\n v5 = a2;\n do {\n v6 = *v5;\n v7 = *a1;\n ++v5;\n ++a1;\n qsort(v7, v6, 4uLL, compar);\n } while (v5 != v3);\n }\n}", + "ida_pseudo_norm": "void func0(void **a1, int *a2, int a3) {\n int *v3;\n int *v5;\n unsigned int v6;\n void *v7;\n if (a3 > 0) {\n v3 = &a2[a3];\n v5 = a2;\n do {\n v6 = *v5;\n v7 = *a1;\n ++v5;\n ++a1;\n qsort(v7, v6, 4uLL, compare_desc);\n } while (v5 != v3);\n }\n}" + }, + { + "index": 889, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\nint compare_desc(const void* a, const void* b) {\n\n return (*(int*)b - *(int*)a);\n\n}\n\n\n\n", + "func": "void func0(int** lists, int* sizes, int num_lists) {\n for (int i = 0; i < num_lists; i++) {\n qsort(lists[i], sizes[i], sizeof(int), compare_desc);\n }\n}", + "test": "int main() {\n\n // First test case\n\n int list1_1[] = {1, 2, 3, 4};\n\n int list1_2[] = {5, 6, 7, 8};\n\n int list1_3[] = {9, 10, 11, 12};\n\n int list1_4[] = {13, 14, 15, 16};\n\n int* lists1[] = {list1_1, list1_2, list1_3, list1_4};\n\n int sizes1[] = {4, 4, 4, 4};\n\n func0(lists1, sizes1, 4);\n\n int expected1_1[] = {4, 3, 2, 1};\n\n int expected1_2[] = {8, 7, 6, 5};\n\n int expected1_3[] = {12, 11, 10, 9};\n\n int expected1_4[] = {16, 15, 14, 13};\n\n assert(memcmp(lists1[0], expected1_1, sizeof(expected1_1)) == 0);\n\n assert(memcmp(lists1[1], expected1_2, sizeof(expected1_2)) == 0);\n\n assert(memcmp(lists1[2], expected1_3, sizeof(expected1_3)) == 0);\n\n assert(memcmp(lists1[3], expected1_4, sizeof(expected1_4)) == 0);\n\n\n\n // Second test case\n\n int list2_1[] = {1, 2};\n\n int list2_2[] = {2, 3};\n\n int list2_3[] = {3, 4};\n\n int* lists2[] = {list2_1, list2_2, list2_3};\n\n int sizes2[] = {2, 2, 2};\n\n func0(lists2, sizes2, 3);\n\n int expected2_1[] = {2, 1};\n\n int expected2_2[] = {3, 2};\n\n int expected2_3[] = {4, 3};\n\n assert(memcmp(lists2[0], expected2_1, sizeof(expected2_1)) == 0);\n\n assert(memcmp(lists2[1], expected2_2, sizeof(expected2_2)) == 0);\n\n assert(memcmp(lists2[2], expected2_3, sizeof(expected2_3)) == 0);\n\n\n\n // Third test case\n\n int list3_1[] = {10, 20};\n\n int list3_2[] = {30, 40};\n\n int* lists3[] = {list3_1, list3_2};\n\n int sizes3[] = {2, 2};\n\n func0(lists3, sizes3, 2);\n\n int expected3_1[] = {20, 10};\n\n int expected3_2[] = {40, 30};\n\n assert(memcmp(lists3[0], expected3_1, sizeof(expected3_1)) == 0);\n\n assert(memcmp(lists3[1], expected3_2, sizeof(expected3_2)) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ntest %edx,%edx\njle 1658 \npush %r14\nmov %rdi,%r14\npush %r13\nlea -0x1(%rdx),%r13d\npush %r12\nlea -0x2c(%rip),%r12\npush %rbp\nmov %rsi,%rbp\npush %rbx\nxor %ebx,%ebx\nnopl 0x0(%rax,%rax,1)\nmovslq 0x0(%rbp,%rbx,4),%rsi\nmov (%r14,%rbx,8),%rdi\nmov %r12,%rcx\nmov $0x4,%edx\ncallq 1070 \nmov %rbx,%rax\nadd $0x1,%rbx\ncmp %r13,%rax\njne 1628 \npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopl 0x0(%rax,%rax,1)\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\ntest edx, edx\njle short locret_1620\npush r13\nmovsxd rdx, edx\npush r12\nlea r13, [rsi+rdx*4]\nlea r12, compare_desc\npush rbp\nmov rbp, rdi\npush rbx\nmov rbx, rsi\nsub rsp, 8\nnop word ptr [rax+rax+00000000h]\nloc_15F0:\nmovsxd rsi, dword ptr [rbx]; nmemb\nmov rdi, [rbp+0]; base\nmov rcx, r12; compar\nmov edx, 4; size\nadd rbx, 4\nadd rbp, 8\ncall _qsort\ncmp rbx, r13\njnz short loc_15F0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nlocret_1620:\nretn", + "ida_pseudo": "void __fastcall func0(void **a1, int *a2, int a3)\n{\n int *v3; // r13\n int *v5; // rbx\n size_t v6; // rsi\n void *v7; // rdi\n\n if ( a3 > 0 )\n {\n v3 = &a2[a3];\n v5 = a2;\n do\n {\n v6 = *v5;\n v7 = *a1;\n ++v5;\n ++a1;\n qsort(v7, v6, 4uLL, compare_desc);\n }\n while ( v5 != v3 );\n }\n}", + "ida_strip_asm": "sub_15C0:\nendbr64\ntest edx, edx\njle short locret_1620\npush r13\nmovsxd rdx, edx\npush r12\nlea r13, [rsi+rdx*4]\nlea r12, compar\npush rbp\nmov rbp, rdi\npush rbx\nmov rbx, rsi\nsub rsp, 8\nnop word ptr [rax+rax+00000000h]\nloc_15F0:\nmovsxd rsi, dword ptr [rbx]; nmemb\nmov rdi, [rbp+0]; base\nmov rcx, r12; compar\nmov edx, 4; size\nadd rbx, 4\nadd rbp, 8\ncall _qsort\ncmp rbx, r13\njnz short loc_15F0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nlocret_1620:\nretn", + "ida_strip_pseudo": "void __fastcall sub_15C0(void **a1, int *a2, int a3)\n{\n int *v3; // r13\n int *v5; // rbx\n size_t v6; // rsi\n void *v7; // rdi\n\n if ( a3 > 0 )\n {\n v3 = &a2[a3];\n v5 = a2;\n do\n {\n v6 = *v5;\n v7 = *a1;\n ++v5;\n ++a1;\n qsort(v7, v6, 4uLL, compar);\n }\n while ( v5 != v3 );\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_15C0(void **a1, int *a2, int a3) {\n int *v3;\n int *v5;\n unsigned int v6;\n void *v7;\n if (a3 > 0) {\n v3 = &a2[a3];\n v5 = a2;\n do {\n v6 = *v5;\n v7 = *a1;\n ++v5;\n ++a1;\n qsort(v7, v6, 4uLL, compar);\n } while (v5 != v3);\n }\n}", + "ida_pseudo_norm": "void func0(void **a1, int *a2, int a3) {\n int *v3;\n int *v5;\n unsigned int v6;\n void *v7;\n if (a3 > 0) {\n v3 = &a2[a3];\n v5 = a2;\n do {\n v6 = *v5;\n v7 = *a1;\n ++v5;\n ++a1;\n qsort(v7, v6, 4uLL, compare_desc);\n } while (v5 != v3);\n }\n}" + }, + { + "index": 890, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr1[], int arr2[], int n) {\n for (int i = 0; i < n; i++) {\n if (arr1[i] != arr2[i]) {\n return i;\n }\n }\n return n;\n}", + "test": "int main() {\n\n int arr1_1[] = {1, 2, 3, 4};\n\n int arr2_1[] = {1, 2, 3};\n\n int arr1_2[] = {2, 4, 6, 8, 10};\n\n int arr2_2[] = {2, 4, 6, 8};\n\n int arr1_3[] = {1, 3, 5, 7, 9, 11};\n\n int arr2_3[] = {1, 3, 5, 7, 9};\n\n\n\n assert(func0(arr1_1, arr2_1, 3) == 3);\n\n assert(func0(arr1_2, arr2_2, 4) == 4);\n\n assert(func0(arr1_3, arr2_3, 5) == 5);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %edx,-0x24(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11be \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x20(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\nje 11ba \nmov -0x4(%rbp),%eax\njmp 11c9 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x24(%rbp),%eax\njl 1185 \nmov -0x24(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_4], 0\njmp short loc_11BE\nloc_1185:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_11BA\nmov eax, [rbp+var_4]\njmp short loc_11C9\nloc_11BA:\nadd [rbp+var_4], 1\nloc_11BE:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_24]\njl short loc_1185\nmov eax, [rbp+var_24]\nloc_11C9:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, unsigned int a3)\n{\n unsigned int i; // [rsp+20h] [rbp-4h]\n\n for ( i = 0; (int)i < (int)a3; ++i )\n {\n if ( *(_DWORD *)(4LL * (int)i + a1) != *(_DWORD *)(4LL * (int)i + a2) )\n return i;\n }\n return a3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_4], 0\njmp short loc_11BE\nloc_1185:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_20]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_11BA\nmov eax, [rbp+var_4]\njmp short loc_11C9\nloc_11BA:\nadd [rbp+var_4], 1\nloc_11BE:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_24]\njl short loc_1185\nmov eax, [rbp+var_24]\nloc_11C9:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, unsigned int a3)\n{\n unsigned int i; // [rsp+20h] [rbp-4h]\n\n for ( i = 0; (int)i < (int)a3; ++i )\n {\n if ( *(_DWORD *)(4LL * (int)i + a1) != *(_DWORD *)(4LL * (int)i + a2) )\n return i;\n }\n return a3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, unsigned int a3) {\n unsigned int i;\n for (i = 0; (int)i < (int)a3; ++i) {\n if (*(uint32_t *)(4LL * (int)i + a1) != *(uint32_t *)(4LL * (int)i + a2))\n return i;\n }\n return a3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, unsigned int a3) {\n unsigned int i;\n for (i = 0; (int)i < (int)a3; ++i) {\n if (*(uint32_t *)(4LL * (int)i + a1) != *(uint32_t *)(4LL * (int)i + a2))\n return i;\n }\n return a3;\n}" + }, + { + "index": 890, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr1[], int arr2[], int n) {\n for (int i = 0; i < n; i++) {\n if (arr1[i] != arr2[i]) {\n return i;\n }\n }\n return n;\n}", + "test": "int main() {\n\n int arr1_1[] = {1, 2, 3, 4};\n\n int arr2_1[] = {1, 2, 3};\n\n int arr1_2[] = {2, 4, 6, 8, 10};\n\n int arr2_2[] = {2, 4, 6, 8};\n\n int arr1_3[] = {1, 3, 5, 7, 9, 11};\n\n int arr2_3[] = {1, 3, 5, 7, 9};\n\n\n\n assert(func0(arr1_1, arr2_1, 3) == 3);\n\n assert(func0(arr1_2, arr2_2, 4) == 4);\n\n assert(func0(arr1_3, arr2_3, 5) == 5);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %edx,%eax\ntest %edx,%edx\njle 1195 \nlea -0x1(%rdx),%r9d\nmov $0x0,%ecx\njmp 1181 \nmov %r8,%rcx\nmov (%rsi,%rcx,4),%edx\ncmp %edx,(%rdi,%rcx,4)\njne 1193 \nlea 0x1(%rcx),%r8\ncmp %r9,%rcx\njne 117e \nretq\nmov %ecx,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov eax, edx\ntest edx, edx\njle short locret_118C\nmovsxd r8, edx\nmov ecx, 0\nloc_117B:\nmov edx, [rsi+rcx*4]\ncmp [rdi+rcx*4], edx\njnz short loc_118D\nadd rcx, 1\ncmp rcx, r8\njnz short loc_117B\nlocret_118C:\nretn\nloc_118D:\nmov eax, ecx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n __int64 result; // rax\n __int64 v4; // rcx\n\n result = (unsigned int)a3;\n if ( a3 > 0 )\n {\n v4 = 0LL;\n while ( *(_DWORD *)(a1 + 4 * v4) == *(_DWORD *)(a2 + 4 * v4) )\n {\n if ( ++v4 == a3 )\n return result;\n }\n return (unsigned int)v4;\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov eax, edx\ntest edx, edx\njle short locret_118C\nmovsxd r8, edx\nmov ecx, 0\nloc_117B:\nmov edx, [rsi+rcx*4]\ncmp [rdi+rcx*4], edx\njnz short loc_118D\nadd rcx, 1\ncmp rcx, r8\njnz short loc_117B\nlocret_118C:\nretn\nloc_118D:\nmov eax, ecx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, int a3)\n{\n __int64 result; // rax\n __int64 v4; // rcx\n\n result = (unsigned int)a3;\n if ( a3 > 0 )\n {\n v4 = 0LL;\n while ( *(_DWORD *)(a1 + 4 * v4) == *(_DWORD *)(a2 + 4 * v4) )\n {\n if ( ++v4 == a3 )\n return result;\n }\n return (unsigned int)v4;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, int a3) {\n long long result;\n long long v4;\n result = (unsigned int)a3;\n if (a3 > 0) {\n v4 = 0LL;\n while (*(uint32_t *)(a1 + 4 * v4) == *(uint32_t *)(a2 + 4 * v4)) {\n if (++v4 == a3) return result;\n }\n return (unsigned int)v4;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, int a3) {\n long long result;\n long long v4;\n result = (unsigned int)a3;\n if (a3 > 0) {\n v4 = 0LL;\n while (*(uint32_t *)(a1 + 4 * v4) == *(uint32_t *)(a2 + 4 * v4)) {\n if (++v4 == a3) return result;\n }\n return (unsigned int)v4;\n }\n return result;\n}" + }, + { + "index": 891, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "bool func0(int A, int B) {\n while (A > 0 && B > 0) {\n A = A / 10;\n B = B / 10;\n }\n if (A == 0 && B == 0) {\n return true;\n }\n return false;\n}", + "test": "int main() {\n\n assert(func0(12, 1) == false);\n\n assert(func0(2, 2) == true);\n\n assert(func0(10, 20) == true);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov %esi,-0x8(%rbp)\njmp 1195 \nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nimul $0x66666667,%rdx,%rdx\nshr $0x20,%rdx\nsar $0x2,%edx\nsar $0x1f,%eax\nsub %eax,%edx\nmov %edx,%eax\nmov %eax,-0x4(%rbp)\nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nimul $0x66666667,%rdx,%rdx\nshr $0x20,%rdx\nsar $0x2,%edx\nsar $0x1f,%eax\nsub %eax,%edx\nmov %edx,%eax\nmov %eax,-0x8(%rbp)\ncmpl $0x0,-0x4(%rbp)\njle 11a1 \ncmpl $0x0,-0x8(%rbp)\njg 1159 \ncmpl $0x0,-0x4(%rbp)\njne 11b4 \ncmpl $0x0,-0x8(%rbp)\njne 11b4 \nmov $0x1,%eax\njmp 11b9 \nmov $0x0,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\njmp short loc_1195\nloc_1159:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_8], eax\nloc_1195:\ncmp [rbp+var_4], 0\njle short loc_11A1\ncmp [rbp+var_8], 0\njg short loc_1159\nloc_11A1:\ncmp [rbp+var_4], 0\njnz short loc_11B4\ncmp [rbp+var_8], 0\njnz short loc_11B4\nmov eax, 1\njmp short loc_11B9\nloc_11B4:\nmov eax, 0\nloc_11B9:\npop rbp\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(int a1, int a2)\n{\n while ( a1 > 0 && a2 > 0 )\n {\n a1 /= 10;\n a2 /= 10;\n }\n return !a1 && !a2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\njmp short loc_1195\nloc_1159:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nimul rdx, 66666667h\nshr rdx, 20h\nmov ecx, edx\nsar ecx, 2\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_8], eax\nloc_1195:\ncmp [rbp+var_4], 0\njle short loc_11A1\ncmp [rbp+var_8], 0\njg short loc_1159\nloc_11A1:\ncmp [rbp+var_4], 0\njnz short loc_11B4\ncmp [rbp+var_8], 0\njnz short loc_11B4\nmov eax, 1\njmp short loc_11B9\nloc_11B4:\nmov eax, 0\nloc_11B9:\npop rbp\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1149(int a1, int a2)\n{\n while ( a1 > 0 && a2 > 0 )\n {\n a1 /= 10;\n a2 /= 10;\n }\n return !a1 && !a2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1149(int a1, int a2) {\n while (a1 > 0 && a2 > 0) {\n a1 /= 10;\n a2 /= 10;\n }\n return !a1 && !a2;\n}", + "ida_pseudo_norm": "uint8_t func0(int a1, int a2) {\n while (a1 > 0 && a2 > 0) {\n a1 /= 10;\n a2 /= 10;\n }\n return !a1 && !a2;\n}" + }, + { + "index": 891, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "bool func0(int A, int B) {\n while (A > 0 && B > 0) {\n A = A / 10;\n B = B / 10;\n }\n if (A == 0 && B == 0) {\n return true;\n }\n return false;\n}", + "test": "int main() {\n\n assert(func0(12, 1) == false);\n\n assert(func0(2, 2) == true);\n\n assert(func0(10, 20) == true);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\njle 118d \ntest %esi,%esi\njle 118d \nmov %edi,%edx\nmovslq %edi,%rax\nimul $0x66666667,%rax,%rax\nsar $0x22,%rax\nsar $0x1f,%edi\nsub %edi,%eax\nmov %eax,%edi\nmov %esi,%ecx\nmovslq %esi,%rax\nimul $0x66666667,%rax,%rax\nsar $0x22,%rax\nsar $0x1f,%esi\nsub %esi,%eax\nmov %eax,%esi\ncmp $0x9,%edx\njle 118d \ncmp $0x9,%ecx\njg 1155 \nor %esi,%edi\nsete %al\nretq\n", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njle short loc_1191\ntest esi, esi\njle short loc_1191\nloc_1155:\nmov edx, edi\nmovsxd rax, edi\nimul rax, 66666667h\nsar rax, 22h\nmov ecx, edi\nsar ecx, 1Fh\nsub eax, ecx\nmov edi, eax\nmov r8d, esi\nmovsxd rax, esi\nimul rax, 66666667h\nsar rax, 22h\nsar esi, 1Fh\nsub eax, esi\nmov esi, eax\ncmp edx, 9\njle short loc_1191\ncmp r8d, 9\njg short loc_1155\nloc_1191:\nor edi, esi\nsetz al\nretn", + "ida_pseudo": "bool __fastcall func0(int a1, int a2)\n{\n int v2; // edx\n int v3; // r8d\n\n if ( a1 > 0 && a2 > 0 )\n {\n do\n {\n v2 = a1;\n a1 /= 10;\n v3 = a2;\n a2 /= 10;\n }\n while ( v2 > 9 && v3 > 9 );\n }\n return (a2 | a1) == 0;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ntest edi, edi\njle short loc_1191\ntest esi, esi\njle short loc_1191\nloc_1155:\nmov edx, edi\nmovsxd rax, edi\nimul rax, 66666667h\nsar rax, 22h\nmov ecx, edi\nsar ecx, 1Fh\nsub eax, ecx\nmov edi, eax\nmov r8d, esi\nmovsxd rax, esi\nimul rax, 66666667h\nsar rax, 22h\nsar esi, 1Fh\nsub eax, esi\nmov esi, eax\ncmp edx, 9\njle short loc_1191\ncmp r8d, 9\njg short loc_1155\nloc_1191:\nor edi, esi\nsetz al\nretn", + "ida_strip_pseudo": "bool __fastcall sub_1149(int a1, int a2)\n{\n int v2; // edx\n int v3; // r8d\n\n if ( a1 > 0 && a2 > 0 )\n {\n do\n {\n v2 = a1;\n a1 /= 10;\n v3 = a2;\n a2 /= 10;\n }\n while ( v2 > 9 && v3 > 9 );\n }\n return (a2 | a1) == 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_1149(int a1, int a2) {\n int v2;\n int v3;\n if (a1 > 0 && a2 > 0) {\n do {\n v2 = a1;\n a1 /= 10;\n v3 = a2;\n a2 /= 10;\n } while (v2 > 9 && v3 > 9);\n }\n return (a2 | a1) == 0;\n}", + "ida_pseudo_norm": "bool func0(int a1, int a2) {\n int v2;\n int v3;\n if (a1 > 0 && a2 > 0) {\n do {\n v2 = a1;\n a1 /= 10;\n v3 = a2;\n a2 /= 10;\n } while (v2 > 9 && v3 > 9);\n }\n return (a2 | a1) == 0;\n}" + }, + { + "index": 892, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n static char buffer[1024];\n regex_t regex;\n regmatch_t match;\n const char* cursor = text;\n char* bufptr = buffer;\n int err;\n err = regcomp(®ex, \" +\", REG_EXTENDED);\n if (err != 0) {\n return NULL;\n }\n while (*cursor != '\\0') {\n if (regexec(®ex, cursor, 1, &match, 0) == 0) {\n memcpy(bufptr, cursor, match.rm_so);\n bufptr += match.rm_so;\n *bufptr++ = ' ';\n cursor += match.rm_eo;\n } else {\n strcpy(bufptr, cursor);\n break;\n }\n }\n regfree(®ex);\n return buffer;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"python program\"), \"python program\") == 0);\n\n assert(strcmp(func0(\"python programming language\"), \"python programming language\") == 0);\n\n assert(strcmp(func0(\"python program\"), \"python program\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nadd $0xffffffffffffff80,%rsp\nmov %rdi,-0x78(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmov -0x78(%rbp),%rax\nmov %rax,-0x68(%rbp)\nlea 0x2de9(%rip),%rax\nmov %rax,-0x60(%rbp)\nlea -0x50(%rbp),%rax\nmov $0x1,%edx\nlea 0xd9d(%rip),%rsi\nmov %rax,%rdi\ncallq 1100 \nmov %eax,-0x6c(%rbp)\ncmpl $0x0,-0x6c(%rbp)\nje 1301 \nmov $0x0,%eax\njmpq 1323 \nlea -0x58(%rbp),%rdx\nmov -0x68(%rbp),%rsi\nlea -0x50(%rbp),%rax\nmov $0x0,%r8d\nmov %rdx,%rcx\nmov $0x1,%edx\nmov %rax,%rdi\ncallq 1130 \ntest %eax,%eax\njne 12ec \nmov -0x58(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x68(%rbp),%rcx\nmov -0x60(%rbp),%rax\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 1120 \nmov -0x58(%rbp),%eax\ncltq\nadd %rax,-0x60(%rbp)\nmov -0x60(%rbp),%rax\nlea 0x1(%rax),%rdx\nmov %rdx,-0x60(%rbp)\nmovb $0x20,(%rax)\nmov -0x54(%rbp),%eax\ncltq\nadd %rax,-0x68(%rbp)\njmp 1301 \nmov -0x68(%rbp),%rdx\nmov -0x60(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10c0 \njmp 1310 \nmov -0x68(%rbp),%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 128a \nlea -0x50(%rbp),%rax\nmov %rax,%rdi\ncallq 10d0 \nlea 0x2d1d(%rip),%rax\nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 1337 \ncallq 10e0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nadd rsp, 0FFFFFFFFFFFFFF80h\nmov [rbp+var_78], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, [rbp+var_78]\nmov [rbp+string], rax\nlea rax, buffer_1\nmov [rbp+dest], rax\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nlea rcx, pattern; \" +\"\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+var_6C], eax\ncmp [rbp+var_6C], 0\njz loc_1304\nmov eax, 0\njmp loc_1326\nloc_128D:\nlea rdx, [rbp+pmatch]\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov rcx, rdx; pmatch\nmov edx, 1; nmatch\nmov rdi, rax; preg\ncall _regexec\ntest eax, eax\njnz short loc_12EF\nmov eax, [rbp+pmatch.rm_so]\nmovsxd rdx, eax; n\nmov rcx, [rbp+string]\nmov rax, [rbp+dest]\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _memcpy\nmov eax, [rbp+pmatch.rm_so]\ncdqe\nadd [rbp+dest], rax\nmov rax, [rbp+dest]\nlea rdx, [rax+1]\nmov [rbp+dest], rdx\nmov byte ptr [rax], 20h ; ' '\nmov eax, [rbp+pmatch.rm_eo]\ncdqe\nadd [rbp+string], rax\njmp short loc_1304\nloc_12EF:\nmov rdx, [rbp+string]\nmov rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\njmp short loc_1313\nloc_1304:\nmov rax, [rbp+string]\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_128D\nloc_1313:\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nlea rax, buffer_1\nloc_1326:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_133A\ncall ___stack_chk_fail\nlocret_133A:\nleave\nretn", + "ida_pseudo": "void *__fastcall func0(const char *a1)\n{\n char *v2; // rax\n char *dest; // [rsp+20h] [rbp-60h]\n regmatch_t pmatch; // [rsp+28h] [rbp-58h] BYREF\n regex_t preg; // [rsp+30h] [rbp-50h] BYREF\n unsigned __int64 v7; // [rsp+78h] [rbp-8h]\n\n v7 = __readfsqword(0x28u);\n dest = (char *)&buffer_1;\n if ( regcomp(&preg, \" +\", 1) )\n return 0LL;\n while ( *a1 )\n {\n if ( regexec(&preg, a1, 1uLL, &pmatch, 0) )\n {\n strcpy(dest, a1);\n break;\n }\n memcpy(dest, a1, pmatch.rm_so);\n v2 = &dest[pmatch.rm_so];\n dest = v2 + 1;\n *v2 = 32;\n a1 += pmatch.rm_eo;\n }\n regfree(&preg);\n return &buffer_1;\n}", + "ida_strip_asm": "sub_1229:\nendbr64\npush rbp\nmov rbp, rsp\nadd rsp, 0FFFFFFFFFFFFFF80h\nmov [rbp+var_78], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, [rbp+var_78]\nmov [rbp+string], rax\nlea rax, unk_4040\nmov [rbp+dest], rax\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nlea rcx, pattern; \" +\"\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+var_6C], eax\ncmp [rbp+var_6C], 0\njz loc_1304\nmov eax, 0\njmp loc_1326\nloc_128D:\nlea rdx, [rbp+pmatch]\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov rcx, rdx; pmatch\nmov edx, 1; nmatch\nmov rdi, rax; preg\ncall _regexec\ntest eax, eax\njnz short loc_12EF\nmov eax, [rbp+pmatch.rm_so]\nmovsxd rdx, eax; n\nmov rcx, [rbp+string]\nmov rax, [rbp+dest]\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _memcpy\nmov eax, [rbp+pmatch.rm_so]\ncdqe\nadd [rbp+dest], rax\nmov rax, [rbp+dest]\nlea rdx, [rax+1]\nmov [rbp+dest], rdx\nmov byte ptr [rax], 20h ; ' '\nmov eax, [rbp+pmatch.rm_eo]\ncdqe\nadd [rbp+string], rax\njmp short loc_1304\nloc_12EF:\nmov rdx, [rbp+string]\nmov rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\njmp short loc_1313\nloc_1304:\nmov rax, [rbp+string]\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_128D\nloc_1313:\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nlea rax, unk_4040\nloc_1326:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_133A\ncall ___stack_chk_fail\nlocret_133A:\nleave\nretn", + "ida_strip_pseudo": "void *__fastcall sub_1229(const char *a1)\n{\n char *v2; // rax\n char *dest; // [rsp+20h] [rbp-60h]\n regmatch_t pmatch; // [rsp+28h] [rbp-58h] BYREF\n regex_t preg; // [rsp+30h] [rbp-50h] BYREF\n unsigned __int64 v7; // [rsp+78h] [rbp-8h]\n\n v7 = __readfsqword(0x28u);\n dest = (char *)&unk_4040;\n if ( regcomp(&preg, \" +\", 1) )\n return 0LL;\n while ( *a1 )\n {\n if ( regexec(&preg, a1, 1uLL, &pmatch, 0) )\n {\n strcpy(dest, a1);\n break;\n }\n memcpy(dest, a1, pmatch.rm_so);\n v2 = &dest[pmatch.rm_so];\n dest = v2 + 1;\n *v2 = 32;\n a1 += pmatch.rm_eo;\n }\n regfree(&preg);\n return &unk_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1229(const char *a1) {\n char *v2;\n char *dest;\n regmatch_t pmatch;\n regex_t preg;\n unsigned long long v7;\n v7 = __readfsqword(40u);\n dest = (char *)&unk_4040;\n if (regcomp(&preg, \" +\", 1)) return 0LL;\n while (*a1) {\n if (regexec(&preg, a1, 1uLL, &pmatch, 0)) {\n strcpy(dest, a1);\n break;\n }\n memcpy(dest, a1, pmatch.rm_so);\n v2 = &dest[pmatch.rm_so];\n dest = v2 + 1;\n *v2 = 32;\n a1 += pmatch.rm_eo;\n }\n regfree(&preg);\n return &unk_4040;\n}", + "ida_pseudo_norm": "void *func0(const char *a1) {\n char *v2;\n char *dest;\n regmatch_t pmatch;\n regex_t preg;\n unsigned long long v7;\n v7 = __readfsqword(40u);\n dest = (char *)&buffer_1;\n if (regcomp(&preg, \" +\", 1)) return 0LL;\n while (*a1) {\n if (regexec(&preg, a1, 1uLL, &pmatch, 0)) {\n strcpy(dest, a1);\n break;\n }\n memcpy(dest, a1, pmatch.rm_so);\n v2 = &dest[pmatch.rm_so];\n dest = v2 + 1;\n *v2 = 32;\n a1 += pmatch.rm_eo;\n }\n regfree(&preg);\n return &buffer_1;\n}" + }, + { + "index": 892, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n static char buffer[1024];\n regex_t regex;\n regmatch_t match;\n const char* cursor = text;\n char* bufptr = buffer;\n int err;\n err = regcomp(®ex, \" +\", REG_EXTENDED);\n if (err != 0) {\n return NULL;\n }\n while (*cursor != '\\0') {\n if (regexec(®ex, cursor, 1, &match, 0) == 0) {\n memcpy(bufptr, cursor, match.rm_so);\n bufptr += match.rm_so;\n *bufptr++ = ' ';\n cursor += match.rm_eo;\n } else {\n strcpy(bufptr, cursor);\n break;\n }\n }\n regfree(®ex);\n return buffer;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"python program\"), \"python program\") == 0);\n\n assert(strcmp(func0(\"python programming language\"), \"python programming language\") == 0);\n\n assert(strcmp(func0(\"python program\"), \"python program\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x68,%rsp\nmov %rdi,%rbp\nmov %fs:0x28,%rax\nmov %rax,0x58(%rsp)\nxor %eax,%eax\nlea 0x10(%rsp),%rdi\nmov $0x1,%edx\nlea 0xdc9(%rip),%rsi\ncallq 10f0 \ntest %eax,%eax\njne 12dd \nlea 0x2df1(%rip),%r12\nlea 0x8(%rsp),%r13\ncmpb $0x0,0x0(%rbp)\nje 12b1 \nlea 0x10(%rsp),%rdi\nmov $0x0,%r8d\nmov %r13,%rcx\nmov $0x1,%edx\nmov %rbp,%rsi\ncallq 1110 \ntest %eax,%eax\njne 12a6 \nmovslq 0x8(%rsp),%rbx\nmov %rbx,%rdx\nmov %rbp,%rsi\nmov %r12,%rdi\ncallq 1100 \nadd %r12,%rbx\nlea 0x1(%rbx),%r12\nmovb $0x20,(%rbx)\nmovslq 0xc(%rsp),%rax\nadd %rax,%rbp\ncmpb $0x0,0x0(%rbp)\njne 125a \njmp 12b1 \nmov %rbp,%rsi\nmov %r12,%rdi\ncallq 10b0 \nlea 0x10(%rsp),%rdi\ncallq 10c0 \nlea 0x2d7e(%rip),%rax\nmov 0x58(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 12e4 \nadd $0x68,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nmov $0x0,%eax\njmp 12c2 \ncallq 10d0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 68h\nmov r13, rdi\nmov rax, fs:28h\nmov [rsp+98h+var_40], rax\nxor eax, eax\nlea rdi, [rsp+98h+preg]; preg\nmov edx, 1; cflags\nlea rsi, pattern; \" +\"\ncall _regcomp\ntest eax, eax\njnz loc_13BA\nmov ebp, 400h\nmov ebx, 400h\nlea r14, buffer_1\nlea r15, [rsp+98h+pmatch]\ncmp byte ptr [r13+0], 0\njz loc_138A\nloc_128D:\nlea rdi, [rsp+98h+preg]; preg\nmov r8d, 0; eflags\nmov rcx, r15; pmatch\nmov edx, 1; nmatch\nmov rsi, r13; string\ncall _regexec\ntest eax, eax\njnz loc_137C\nmovsxd r12, [rsp+98h+pmatch.rm_so]\nmov rcx, rbx\nmov rdx, r12\nmov rsi, r13\nmov rdi, r14\ncall ___memcpy_chk\nmov eax, 400h\ncmp rbx, rax\ncmovnb rax, rbx\nlea rcx, [r12+rax]\nmov rdx, rcx\nsub rdx, rbx\ncmp rdx, rax\ncmovb rdx, rax\nsub rbx, rcx\nadd rdx, rbx\nmov ecx, 400h\ncmp rbp, rcx\ncmovnb rcx, rbp\nlea rsi, [r12+rcx]\nmov rax, rsi\nsub rax, rbp\ncmp rax, rcx\ncmovb rax, rcx\nsub rbp, rsi\nadd rax, rbp\nadd r12, r14\nmov ecx, 400h\ncmp rdx, rcx\ncmovnb rcx, rdx\nmov rbx, rcx\nsub rbx, rdx\nadd rbx, 1\ncmp rbx, rcx\ncmovb rbx, rcx\nsub rdx, 1\nsub rdx, rcx\nadd rbx, rdx\nmov edx, 400h\ncmp rax, rdx\ncmovnb rdx, rax\nmov rbp, rdx\nsub rbp, rax\nadd rbp, 1\ncmp rbp, rdx\ncmovb rbp, rdx\nsub rax, 1\nsub rax, rdx\nadd rbp, rax\nlea r14, [r12+1]\nmov byte ptr [r12], 20h ; ' '\nmovsxd rax, [rsp+98h+pmatch.rm_eo]\nadd r13, rax\ncmp byte ptr [r13+0], 0\njnz loc_128D\njmp short loc_138A\nloc_137C:\nmov rdx, rbp\nmov rsi, r13\nmov rdi, r14\ncall ___strcpy_chk\nloc_138A:\nlea rdi, [rsp+98h+preg]; preg\ncall _regfree\nlea rax, buffer_1\nloc_139B:\nmov rdx, [rsp+98h+var_40]\nsub rdx, fs:28h\njnz short loc_13C1\nadd rsp, 68h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_13BA:\nmov eax, 0\njmp short loc_139B\nloc_13C1:\ncall ___stack_chk_fail", + "ida_pseudo": "void *__fastcall func0(char *string)\n{\n char *v1; // r13\n unsigned __int64 v2; // rbp\n unsigned __int64 v3; // rbx\n char *v4; // r14\n __int64 rm_so; // r12\n unsigned __int64 v6; // rax\n unsigned __int64 v7; // rdx\n unsigned __int64 v8; // rdx\n unsigned __int64 v9; // rcx\n unsigned __int64 v10; // rax\n unsigned __int64 v11; // rax\n char *v12; // r12\n unsigned __int64 v13; // rcx\n unsigned __int64 v14; // rbx\n unsigned __int64 v15; // rdx\n unsigned __int64 v16; // rbp\n regmatch_t pmatch; // [rsp+8h] [rbp-90h] BYREF\n regex_t preg; // [rsp+10h] [rbp-88h] BYREF\n unsigned __int64 v20; // [rsp+58h] [rbp-40h]\n\n v1 = string;\n v20 = __readfsqword(0x28u);\n if ( regcomp(&preg, \" +\", 1) )\n return 0LL;\n v2 = 1024LL;\n v3 = 1024LL;\n v4 = (char *)&buffer_1;\n if ( *string )\n {\n while ( !regexec(&preg, v1, 1uLL, &pmatch, 0) )\n {\n rm_so = pmatch.rm_so;\n __memcpy_chk(v4, v1, pmatch.rm_so, v3);\n v6 = 1024LL;\n if ( v3 >= 0x400 )\n v6 = v3;\n v7 = rm_so + v6 - v3;\n if ( v7 < v6 )\n v7 = v6;\n v8 = v3 - (rm_so + v6) + v7;\n v9 = 1024LL;\n if ( v2 >= 0x400 )\n v9 = v2;\n v10 = rm_so + v9 - v2;\n if ( v10 < v9 )\n v10 = v9;\n v11 = v2 - (rm_so + v9) + v10;\n v12 = &v4[rm_so];\n v13 = 1024LL;\n if ( v8 >= 0x400 )\n v13 = v8;\n v14 = v13 - v8 + 1;\n if ( v14 < v13 )\n v14 = v13;\n v3 = v8 - 1 - v13 + v14;\n v15 = 1024LL;\n if ( v11 >= 0x400 )\n v15 = v11;\n v16 = v15 - v11 + 1;\n if ( v16 < v15 )\n v16 = v15;\n v2 = v11 - 1 - v15 + v16;\n v4 = v12 + 1;\n *v12 = 32;\n v1 += pmatch.rm_eo;\n if ( !*v1 )\n goto LABEL_23;\n }\n __strcpy_chk(v4, v1, v2);\n }\nLABEL_23:\n regfree(&preg);\n return &buffer_1;\n}", + "ida_strip_asm": "sub_1229:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 68h\nmov r13, rdi\nmov rax, fs:28h\nmov [rsp+98h+var_40], rax\nxor eax, eax\nlea rdi, [rsp+98h+preg]; preg\nmov edx, 1; cflags\nlea rsi, pattern; \" +\"\ncall _regcomp\ntest eax, eax\njnz loc_13BA\nmov ebp, 400h\nmov ebx, 400h\nlea r14, unk_4040\nlea r15, [rsp+98h+pmatch]\ncmp byte ptr [r13+0], 0\njz loc_138A\nloc_128D:\nlea rdi, [rsp+98h+preg]; preg\nmov r8d, 0; eflags\nmov rcx, r15; pmatch\nmov edx, 1; nmatch\nmov rsi, r13; string\ncall _regexec\ntest eax, eax\njnz loc_137C\nmovsxd r12, [rsp+98h+pmatch.rm_so]\nmov rcx, rbx\nmov rdx, r12\nmov rsi, r13\nmov rdi, r14\ncall ___memcpy_chk\nmov eax, 400h\ncmp rbx, rax\ncmovnb rax, rbx\nlea rcx, [r12+rax]\nmov rdx, rcx\nsub rdx, rbx\ncmp rdx, rax\ncmovb rdx, rax\nsub rbx, rcx\nadd rdx, rbx\nmov ecx, 400h\ncmp rbp, rcx\ncmovnb rcx, rbp\nlea rsi, [r12+rcx]\nmov rax, rsi\nsub rax, rbp\ncmp rax, rcx\ncmovb rax, rcx\nsub rbp, rsi\nadd rax, rbp\nadd r12, r14\nmov ecx, 400h\ncmp rdx, rcx\ncmovnb rcx, rdx\nmov rbx, rcx\nsub rbx, rdx\nadd rbx, 1\ncmp rbx, rcx\ncmovb rbx, rcx\nsub rdx, 1\nsub rdx, rcx\nadd rbx, rdx\nmov edx, 400h\ncmp rax, rdx\ncmovnb rdx, rax\nmov rbp, rdx\nsub rbp, rax\nadd rbp, 1\ncmp rbp, rdx\ncmovb rbp, rdx\nsub rax, 1\nsub rax, rdx\nadd rbp, rax\nlea r14, [r12+1]\nmov byte ptr [r12], 20h ; ' '\nmovsxd rax, [rsp+98h+pmatch.rm_eo]\nadd r13, rax\ncmp byte ptr [r13+0], 0\njnz loc_128D\njmp short loc_138A\nloc_137C:\nmov rdx, rbp\nmov rsi, r13\nmov rdi, r14\ncall ___strcpy_chk\nloc_138A:\nlea rdi, [rsp+98h+preg]; preg\ncall _regfree\nlea rax, unk_4040\nloc_139B:\nmov rdx, [rsp+98h+var_40]\nsub rdx, fs:28h\njnz short loc_13C1\nadd rsp, 68h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_13BA:\nmov eax, 0\njmp short loc_139B\nloc_13C1:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "void *__fastcall sub_1229(char *string)\n{\n char *v1; // r13\n unsigned __int64 v2; // rbp\n unsigned __int64 v3; // rbx\n char *v4; // r14\n __int64 rm_so; // r12\n unsigned __int64 v6; // rax\n unsigned __int64 v7; // rdx\n unsigned __int64 v8; // rdx\n unsigned __int64 v9; // rcx\n unsigned __int64 v10; // rax\n unsigned __int64 v11; // rax\n char *v12; // r12\n unsigned __int64 v13; // rcx\n unsigned __int64 v14; // rbx\n unsigned __int64 v15; // rdx\n unsigned __int64 v16; // rbp\n regmatch_t pmatch; // [rsp+8h] [rbp-90h] BYREF\n regex_t preg; // [rsp+10h] [rbp-88h] BYREF\n unsigned __int64 v20; // [rsp+58h] [rbp-40h]\n\n v1 = string;\n v20 = __readfsqword(0x28u);\n if ( regcomp(&preg, \" +\", 1) )\n return 0LL;\n v2 = 1024LL;\n v3 = 1024LL;\n v4 = (char *)&unk_4040;\n if ( *string )\n {\n while ( !regexec(&preg, v1, 1uLL, &pmatch, 0) )\n {\n rm_so = pmatch.rm_so;\n __memcpy_chk(v4, v1, pmatch.rm_so, v3);\n v6 = 1024LL;\n if ( v3 >= 0x400 )\n v6 = v3;\n v7 = rm_so + v6 - v3;\n if ( v7 < v6 )\n v7 = v6;\n v8 = v3 - (rm_so + v6) + v7;\n v9 = 1024LL;\n if ( v2 >= 0x400 )\n v9 = v2;\n v10 = rm_so + v9 - v2;\n if ( v10 < v9 )\n v10 = v9;\n v11 = v2 - (rm_so + v9) + v10;\n v12 = &v4[rm_so];\n v13 = 1024LL;\n if ( v8 >= 0x400 )\n v13 = v8;\n v14 = v13 - v8 + 1;\n if ( v14 < v13 )\n v14 = v13;\n v3 = v8 - 1 - v13 + v14;\n v15 = 1024LL;\n if ( v11 >= 0x400 )\n v15 = v11;\n v16 = v15 - v11 + 1;\n if ( v16 < v15 )\n v16 = v15;\n v2 = v11 - 1 - v15 + v16;\n v4 = v12 + 1;\n *v12 = 32;\n v1 += pmatch.rm_eo;\n if ( !*v1 )\n goto LABEL_23;\n }\n __strcpy_chk(v4, v1, v2);\n }\nLABEL_23:\n regfree(&preg);\n return &unk_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1229(char *string) {\n char *v1;\n unsigned long long v2;\n unsigned long long v3;\n char *v4;\n long long rm_so;\n unsigned long long v6;\n unsigned long long v7;\n unsigned long long v8;\n unsigned long long v9;\n unsigned long long v10;\n unsigned long long v11;\n char *v12;\n unsigned long long v13;\n unsigned long long v14;\n unsigned long long v15;\n unsigned long long v16;\n regmatch_t pmatch;\n regex_t preg;\n unsigned long long v20;\n v1 = string;\n v20 = __readfsqword(40u);\n if (regcomp(&preg, \" +\", 1)) return 0LL;\n v2 = 1024LL;\n v3 = 1024LL;\n v4 = (char *)&unk_4040;\n if (*string) {\n while (!regexec(&preg, v1, 1uLL, &pmatch, 0)) {\n rm_so = pmatch.rm_so;\n __memcpy_chk(v4, v1, pmatch.rm_so, v3);\n v6 = 1024LL;\n if (v3 >= 1024) v6 = v3;\n v7 = rm_so + v6 - v3;\n if (v7 < v6) v7 = v6;\n v8 = v3 - (rm_so + v6) + v7;\n v9 = 1024LL;\n if (v2 >= 1024) v9 = v2;\n v10 = rm_so + v9 - v2;\n if (v10 < v9) v10 = v9;\n v11 = v2 - (rm_so + v9) + v10;\n v12 = &v4[rm_so];\n v13 = 1024LL;\n if (v8 >= 1024) v13 = v8;\n v14 = v13 - v8 + 1;\n if (v14 < v13) v14 = v13;\n v3 = v8 - 1 - v13 + v14;\n v15 = 1024LL;\n if (v11 >= 1024) v15 = v11;\n v16 = v15 - v11 + 1;\n if (v16 < v15) v16 = v15;\n v2 = v11 - 1 - v15 + v16;\n v4 = v12 + 1;\n *v12 = 32;\n v1 += pmatch.rm_eo;\n if (!*v1) goto LABEL_23;\n }\n __strcpy_chk(v4, v1, v2);\n }\nLABEL_23:\n regfree(&preg);\n return &unk_4040;\n}", + "ida_pseudo_norm": "void *func0(char *string) {\n char *v1;\n unsigned long long v2;\n unsigned long long v3;\n char *v4;\n long long rm_so;\n unsigned long long v6;\n unsigned long long v7;\n unsigned long long v8;\n unsigned long long v9;\n unsigned long long v10;\n unsigned long long v11;\n char *v12;\n unsigned long long v13;\n unsigned long long v14;\n unsigned long long v15;\n unsigned long long v16;\n regmatch_t pmatch;\n regex_t preg;\n unsigned long long v20;\n v1 = string;\n v20 = __readfsqword(40u);\n if (regcomp(&preg, \" +\", 1)) return 0LL;\n v2 = 1024LL;\n v3 = 1024LL;\n v4 = (char *)&buffer_1;\n if (*string) {\n while (!regexec(&preg, v1, 1uLL, &pmatch, 0)) {\n rm_so = pmatch.rm_so;\n __memcpy_chk(v4, v1, pmatch.rm_so, v3);\n v6 = 1024LL;\n if (v3 >= 1024) v6 = v3;\n v7 = rm_so + v6 - v3;\n if (v7 < v6) v7 = v6;\n v8 = v3 - (rm_so + v6) + v7;\n v9 = 1024LL;\n if (v2 >= 1024) v9 = v2;\n v10 = rm_so + v9 - v2;\n if (v10 < v9) v10 = v9;\n v11 = v2 - (rm_so + v9) + v10;\n v12 = &v4[rm_so];\n v13 = 1024LL;\n if (v8 >= 1024) v13 = v8;\n v14 = v13 - v8 + 1;\n if (v14 < v13) v14 = v13;\n v3 = v8 - 1 - v13 + v14;\n v15 = 1024LL;\n if (v11 >= 1024) v15 = v11;\n v16 = v15 - v11 + 1;\n if (v16 < v15) v16 = v15;\n v2 = v11 - 1 - v15 + v16;\n v4 = v12 + 1;\n *v12 = 32;\n v1 += pmatch.rm_eo;\n if (!*v1) goto LABEL_23;\n }\n __strcpy_chk(v4, v1, v2);\n }\nLABEL_23:\n regfree(&preg);\n return &buffer_1;\n}" + }, + { + "index": 892, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n static char buffer[1024];\n regex_t regex;\n regmatch_t match;\n const char* cursor = text;\n char* bufptr = buffer;\n int err;\n err = regcomp(®ex, \" +\", REG_EXTENDED);\n if (err != 0) {\n return NULL;\n }\n while (*cursor != '\\0') {\n if (regexec(®ex, cursor, 1, &match, 0) == 0) {\n memcpy(bufptr, cursor, match.rm_so);\n bufptr += match.rm_so;\n *bufptr++ = ' ';\n cursor += match.rm_eo;\n } else {\n strcpy(bufptr, cursor);\n break;\n }\n }\n regfree(®ex);\n return buffer;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"python program\"), \"python program\") == 0);\n\n assert(strcmp(func0(\"python programming language\"), \"python programming language\") == 0);\n\n assert(strcmp(func0(\"python program\"), \"python program\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\nmov $0x1,%edx\nlea 0xd02(%rip),%rsi\npush %r13\npush %r12\npush %rbp\nmov %rdi,%rbp\npush %rbx\nsub $0x60,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x58(%rsp)\nxor %eax,%eax\nlea 0x10(%rsp),%r13\nmov %r13,%rdi\ncallq 10f0 \ntest %eax,%eax\njne 13d0 \ncmpb $0x0,0x0(%rbp)\nlea 0x2d01(%rip),%r12\nlea 0x8(%rsp),%r14\njne 137b \njmp 13a0 \nnopl 0x0(%rax,%rax,1)\nmovslq 0x8(%rsp),%rbx\nmov %rbp,%rsi\nmov %r12,%rdi\nmov %rbx,%rdx\nadd %r12,%rbx\ncallq 1100 \nmovslq 0xc(%rsp),%rax\nmovb $0x20,(%rbx)\nlea 0x1(%rbx),%r12\nadd %rax,%rbp\ncmpb $0x0,0x0(%rbp)\nje 13a0 \nxor %r8d,%r8d\nmov %r14,%rcx\nmov $0x1,%edx\nmov %rbp,%rsi\nmov %r13,%rdi\ncallq 1110 \ntest %eax,%eax\nje 1350 \nmov %rbp,%rsi\nmov %r12,%rdi\ncallq 10b0 \nmov %r13,%rdi\ncallq 10c0 \nlea 0x2c91(%rip),%rax\nmov 0x58(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 13d4 \nadd $0x60,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopl 0x0(%rax)\nxor %eax,%eax\njmp 13af \ncallq 10d0 <__stack_chk_fail@plt>\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov edx, 1; cflags\nlea rsi, pattern; \" +\"\npush r14\nmov r14, rdi\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 68h\nmov rax, fs:28h\nmov [rsp+98h+var_40], rax\nxor eax, eax\nlea rbp, [rsp+98h+preg]\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njnz loc_1448\ncmp byte ptr [r14], 0\nmov ebx, 400h\nlea r12, [rsp+98h+pmatch]\nlea r13, buffer_1\njnz loc_13E9\njmp loc_1415\nloc_1370:\nmovsxd r15, [rsp+98h+pmatch.rm_so]\nmov rcx, rbx\nmov rsi, r14\nmov rdi, r13\nmov rdx, r15\ncall ___memcpy_chk\nmov edx, 400h\ncmp rbx, rdx\ncmovnb rdx, rbx\nlea rcx, [r15+rdx]\nmov rax, rcx\nsub rax, rbx\ncmp rax, rdx\ncmovb rax, rdx\nsub rbx, rcx\nmov edx, 400h\nadd r15, r13\nmov byte ptr [r15], 20h ; ' '\nlea r13, [r15+1]\nadd rax, rbx\ncmp rax, rdx\ncmovnb rdx, rax\nmov rbx, rdx\nsub rbx, rax\nadd rbx, 1\ncmp rbx, rdx\ncmovb rbx, rdx\nsub rax, 1\nsub rax, rdx\nadd rbx, rax\nmovsxd rax, [rsp+98h+pmatch.rm_eo]\nadd r14, rax\ncmp byte ptr [r14], 0\njz short loc_1415\nloc_13E9:\nxor r8d, r8d; eflags\nmov rcx, r12; pmatch\nmov edx, 1; nmatch\nmov rsi, r14; string\nmov rdi, rbp; preg\ncall _regexec\ntest eax, eax\njz loc_1370\nmov rdx, rbx\nmov rsi, r14\nmov rdi, r13\ncall ___strcpy_chk\nloc_1415:\nmov rdi, rbp; preg\ncall _regfree\nlea rax, buffer_1\nloc_1424:\nmov rdx, [rsp+98h+var_40]\nsub rdx, fs:28h\njnz short loc_144C\nadd rsp, 68h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1448:\nxor eax, eax\njmp short loc_1424\nloc_144C:\ncall ___stack_chk_fail", + "ida_pseudo": "void *__fastcall func0(char *string)\n{\n char *v1; // r14\n unsigned __int64 v2; // rbx\n char *v3; // r13\n __int64 rm_so; // r15\n unsigned __int64 v5; // rdx\n __int64 v6; // rcx\n unsigned __int64 v7; // rax\n unsigned __int64 v8; // rdx\n char *v9; // r15\n unsigned __int64 v10; // rax\n unsigned __int64 v11; // rbx\n regmatch_t pmatch; // [rsp+8h] [rbp-90h] BYREF\n regex_t preg; // [rsp+10h] [rbp-88h] BYREF\n unsigned __int64 v15; // [rsp+58h] [rbp-40h]\n\n v1 = string;\n v15 = __readfsqword(0x28u);\n if ( regcomp(&preg, \" +\", 1) )\n return 0LL;\n v2 = 1024LL;\n v3 = (char *)&buffer_1;\n if ( *string )\n {\n while ( !regexec(&preg, v1, 1uLL, &pmatch, 0) )\n {\n rm_so = pmatch.rm_so;\n __memcpy_chk(v3, v1, pmatch.rm_so, v2);\n v5 = 1024LL;\n if ( v2 >= 0x400 )\n v5 = v2;\n v6 = rm_so + v5;\n v7 = rm_so + v5 - v2;\n if ( v7 < v5 )\n v7 = v5;\n v8 = 1024LL;\n v9 = &v3[rm_so];\n *v9 = 32;\n v3 = v9 + 1;\n v10 = v2 - v6 + v7;\n if ( v10 >= 0x400 )\n v8 = v10;\n v11 = v8 - v10 + 1;\n if ( v11 < v8 )\n v11 = v8;\n v2 = v10 - 1 - v8 + v11;\n v1 += pmatch.rm_eo;\n if ( !*v1 )\n goto LABEL_15;\n }\n __strcpy_chk(v3, v1, v2);\n }\nLABEL_15:\n regfree(&preg);\n return &buffer_1;\n}", + "ida_strip_asm": "sub_1300:\nendbr64\npush r15\nmov edx, 1; cflags\nlea rsi, pattern; \" +\"\npush r14\nmov r14, rdi\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 68h\nmov rax, fs:28h\nmov [rsp+98h+var_40], rax\nxor eax, eax\nlea rbp, [rsp+98h+preg]\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njnz loc_1448\ncmp byte ptr [r14], 0\nmov ebx, 400h\nlea r12, [rsp+98h+pmatch]\nlea r13, unk_4040\njnz loc_13E9\njmp loc_1415\nloc_1370:\nmovsxd r15, [rsp+98h+pmatch.rm_so]\nmov rcx, rbx\nmov rsi, r14\nmov rdi, r13\nmov rdx, r15\ncall ___memcpy_chk\nmov edx, 400h\ncmp rbx, rdx\ncmovnb rdx, rbx\nlea rcx, [r15+rdx]\nmov rax, rcx\nsub rax, rbx\ncmp rax, rdx\ncmovb rax, rdx\nsub rbx, rcx\nmov edx, 400h\nadd r15, r13\nmov byte ptr [r15], 20h ; ' '\nlea r13, [r15+1]\nadd rax, rbx\ncmp rax, rdx\ncmovnb rdx, rax\nmov rbx, rdx\nsub rbx, rax\nadd rbx, 1\ncmp rbx, rdx\ncmovb rbx, rdx\nsub rax, 1\nsub rax, rdx\nadd rbx, rax\nmovsxd rax, [rsp+98h+pmatch.rm_eo]\nadd r14, rax\ncmp byte ptr [r14], 0\njz short loc_1415\nloc_13E9:\nxor r8d, r8d; eflags\nmov rcx, r12; pmatch\nmov edx, 1; nmatch\nmov rsi, r14; string\nmov rdi, rbp; preg\ncall _regexec\ntest eax, eax\njz loc_1370\nmov rdx, rbx\nmov rsi, r14\nmov rdi, r13\ncall ___strcpy_chk\nloc_1415:\nmov rdi, rbp; preg\ncall _regfree\nlea rax, unk_4040\nloc_1424:\nmov rdx, [rsp+98h+var_40]\nsub rdx, fs:28h\njnz short loc_144C\nadd rsp, 68h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1448:\nxor eax, eax\njmp short loc_1424\nloc_144C:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "void *__fastcall sub_1300(char *string)\n{\n char *v1; // r14\n unsigned __int64 v2; // rbx\n char *v3; // r13\n __int64 rm_so; // r15\n unsigned __int64 v5; // rdx\n __int64 v6; // rcx\n unsigned __int64 v7; // rax\n unsigned __int64 v8; // rdx\n char *v9; // r15\n unsigned __int64 v10; // rax\n unsigned __int64 v11; // rbx\n regmatch_t pmatch; // [rsp+8h] [rbp-90h] BYREF\n regex_t preg; // [rsp+10h] [rbp-88h] BYREF\n unsigned __int64 v15; // [rsp+58h] [rbp-40h]\n\n v1 = string;\n v15 = __readfsqword(0x28u);\n if ( regcomp(&preg, \" +\", 1) )\n return 0LL;\n v2 = 1024LL;\n v3 = (char *)&unk_4040;\n if ( *string )\n {\n while ( !regexec(&preg, v1, 1uLL, &pmatch, 0) )\n {\n rm_so = pmatch.rm_so;\n __memcpy_chk(v3, v1, pmatch.rm_so, v2);\n v5 = 1024LL;\n if ( v2 >= 0x400 )\n v5 = v2;\n v6 = rm_so + v5;\n v7 = rm_so + v5 - v2;\n if ( v7 < v5 )\n v7 = v5;\n v8 = 1024LL;\n v9 = &v3[rm_so];\n *v9 = 32;\n v3 = v9 + 1;\n v10 = v2 - v6 + v7;\n if ( v10 >= 0x400 )\n v8 = v10;\n v11 = v8 - v10 + 1;\n if ( v11 < v8 )\n v11 = v8;\n v2 = v10 - 1 - v8 + v11;\n v1 += pmatch.rm_eo;\n if ( !*v1 )\n goto LABEL_15;\n }\n __strcpy_chk(v3, v1, v2);\n }\nLABEL_15:\n regfree(&preg);\n return &unk_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1300(char *string) {\n char *v1;\n unsigned long long v2;\n char *v3;\n long long rm_so;\n unsigned long long v5;\n long long v6;\n unsigned long long v7;\n unsigned long long v8;\n char *v9;\n unsigned long long v10;\n unsigned long long v11;\n regmatch_t pmatch;\n regex_t preg;\n unsigned long long v15;\n v1 = string;\n v15 = __readfsqword(40u);\n if (regcomp(&preg, \" +\", 1)) return 0LL;\n v2 = 1024LL;\n v3 = (char *)&unk_4040;\n if (*string) {\n while (!regexec(&preg, v1, 1uLL, &pmatch, 0)) {\n rm_so = pmatch.rm_so;\n __memcpy_chk(v3, v1, pmatch.rm_so, v2);\n v5 = 1024LL;\n if (v2 >= 1024) v5 = v2;\n v6 = rm_so + v5;\n v7 = rm_so + v5 - v2;\n if (v7 < v5) v7 = v5;\n v8 = 1024LL;\n v9 = &v3[rm_so];\n *v9 = 32;\n v3 = v9 + 1;\n v10 = v2 - v6 + v7;\n if (v10 >= 1024) v8 = v10;\n v11 = v8 - v10 + 1;\n if (v11 < v8) v11 = v8;\n v2 = v10 - 1 - v8 + v11;\n v1 += pmatch.rm_eo;\n if (!*v1) goto LABEL_15;\n }\n __strcpy_chk(v3, v1, v2);\n }\nLABEL_15:\n regfree(&preg);\n return &unk_4040;\n}", + "ida_pseudo_norm": "void *func0(char *string) {\n char *v1;\n unsigned long long v2;\n char *v3;\n long long rm_so;\n unsigned long long v5;\n long long v6;\n unsigned long long v7;\n unsigned long long v8;\n char *v9;\n unsigned long long v10;\n unsigned long long v11;\n regmatch_t pmatch;\n regex_t preg;\n unsigned long long v15;\n v1 = string;\n v15 = __readfsqword(40u);\n if (regcomp(&preg, \" +\", 1)) return 0LL;\n v2 = 1024LL;\n v3 = (char *)&buffer_1;\n if (*string) {\n while (!regexec(&preg, v1, 1uLL, &pmatch, 0)) {\n rm_so = pmatch.rm_so;\n __memcpy_chk(v3, v1, pmatch.rm_so, v2);\n v5 = 1024LL;\n if (v2 >= 1024) v5 = v2;\n v6 = rm_so + v5;\n v7 = rm_so + v5 - v2;\n if (v7 < v5) v7 = v5;\n v8 = 1024LL;\n v9 = &v3[rm_so];\n *v9 = 32;\n v3 = v9 + 1;\n v10 = v2 - v6 + v7;\n if (v10 >= 1024) v8 = v10;\n v11 = v8 - v10 + 1;\n if (v11 < v8) v11 = v8;\n v2 = v10 - 1 - v8 + v11;\n v1 += pmatch.rm_eo;\n if (!*v1) goto LABEL_15;\n }\n __strcpy_chk(v3, v1, v2);\n }\nLABEL_15:\n regfree(&preg);\n return &buffer_1;\n}" + }, + { + "index": 892, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n static char buffer[1024];\n regex_t regex;\n regmatch_t match;\n const char* cursor = text;\n char* bufptr = buffer;\n int err;\n err = regcomp(®ex, \" +\", REG_EXTENDED);\n if (err != 0) {\n return NULL;\n }\n while (*cursor != '\\0') {\n if (regexec(®ex, cursor, 1, &match, 0) == 0) {\n memcpy(bufptr, cursor, match.rm_so);\n bufptr += match.rm_so;\n *bufptr++ = ' ';\n cursor += match.rm_eo;\n } else {\n strcpy(bufptr, cursor);\n break;\n }\n }\n regfree(®ex);\n return buffer;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"python program\"), \"python program\") == 0);\n\n assert(strcmp(func0(\"python programming language\"), \"python programming language\") == 0);\n\n assert(strcmp(func0(\"python program\"), \"python program\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\nmov $0x1,%edx\nlea 0xd02(%rip),%rsi\npush %r13\npush %r12\npush %rbp\nmov %rdi,%rbp\npush %rbx\nsub $0x60,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x58(%rsp)\nxor %eax,%eax\nlea 0x10(%rsp),%r13\nmov %r13,%rdi\ncallq 10f0 \ntest %eax,%eax\njne 13d0 \ncmpb $0x0,0x0(%rbp)\nlea 0x2d01(%rip),%r12\nlea 0x8(%rsp),%r14\njne 137b \njmp 13a0 \nnopl 0x0(%rax,%rax,1)\nmovslq 0x8(%rsp),%rbx\nmov %rbp,%rsi\nmov %r12,%rdi\nmov %rbx,%rdx\nadd %r12,%rbx\ncallq 1100 \nmovslq 0xc(%rsp),%rax\nmovb $0x20,(%rbx)\nlea 0x1(%rbx),%r12\nadd %rax,%rbp\ncmpb $0x0,0x0(%rbp)\nje 13a0 \nxor %r8d,%r8d\nmov %r14,%rcx\nmov $0x1,%edx\nmov %rbp,%rsi\nmov %r13,%rdi\ncallq 1110 \ntest %eax,%eax\nje 1350 \nmov %rbp,%rsi\nmov %r12,%rdi\ncallq 10b0 \nmov %r13,%rdi\ncallq 10c0 \nlea 0x2c91(%rip),%rax\nmov 0x58(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 13d4 \nadd $0x60,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopl 0x0(%rax)\nxor %eax,%eax\njmp 13af \ncallq 10d0 <__stack_chk_fail@plt>\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov edx, 1; cflags\nlea rsi, pattern; \" +\"\npush r14\nmov r14, rdi\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 68h\nmov rax, fs:28h\nmov [rsp+98h+var_40], rax\nxor eax, eax\nlea rbp, [rsp+98h+preg]\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njnz loc_1448\ncmp byte ptr [r14], 0\nmov ebx, 400h\nlea r12, [rsp+98h+pmatch]\nlea r13, buffer_1\njnz loc_13E9\njmp loc_1415\nloc_1370:\nmovsxd r15, [rsp+98h+pmatch.rm_so]\nmov rcx, rbx\nmov rsi, r14\nmov rdi, r13\nmov rdx, r15\ncall ___memcpy_chk\nmov edx, 400h\ncmp rbx, rdx\ncmovnb rdx, rbx\nlea rcx, [r15+rdx]\nmov rax, rcx\nsub rax, rbx\ncmp rax, rdx\ncmovb rax, rdx\nsub rbx, rcx\nmov edx, 400h\nadd r15, r13\nmov byte ptr [r15], 20h ; ' '\nlea r13, [r15+1]\nadd rax, rbx\ncmp rax, rdx\ncmovnb rdx, rax\nmov rbx, rdx\nsub rbx, rax\nadd rbx, 1\ncmp rbx, rdx\ncmovb rbx, rdx\nsub rax, 1\nsub rax, rdx\nadd rbx, rax\nmovsxd rax, [rsp+98h+pmatch.rm_eo]\nadd r14, rax\ncmp byte ptr [r14], 0\njz short loc_1415\nloc_13E9:\nxor r8d, r8d; eflags\nmov rcx, r12; pmatch\nmov edx, 1; nmatch\nmov rsi, r14; string\nmov rdi, rbp; preg\ncall _regexec\ntest eax, eax\njz loc_1370\nmov rdx, rbx\nmov rsi, r14\nmov rdi, r13\ncall ___strcpy_chk\nloc_1415:\nmov rdi, rbp; preg\ncall _regfree\nlea rax, buffer_1\nloc_1424:\nmov rdx, [rsp+98h+var_40]\nsub rdx, fs:28h\njnz short loc_144C\nadd rsp, 68h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1448:\nxor eax, eax\njmp short loc_1424\nloc_144C:\ncall ___stack_chk_fail", + "ida_pseudo": "void *__fastcall func0(char *string)\n{\n char *v1; // r14\n unsigned __int64 v2; // rbx\n char *v3; // r13\n __int64 rm_so; // r15\n unsigned __int64 v5; // rdx\n __int64 v6; // rcx\n unsigned __int64 v7; // rax\n unsigned __int64 v8; // rdx\n char *v9; // r15\n unsigned __int64 v10; // rax\n unsigned __int64 v11; // rbx\n regmatch_t pmatch; // [rsp+8h] [rbp-90h] BYREF\n regex_t preg; // [rsp+10h] [rbp-88h] BYREF\n unsigned __int64 v15; // [rsp+58h] [rbp-40h]\n\n v1 = string;\n v15 = __readfsqword(0x28u);\n if ( regcomp(&preg, \" +\", 1) )\n return 0LL;\n v2 = 1024LL;\n v3 = (char *)&buffer_1;\n if ( *string )\n {\n while ( !regexec(&preg, v1, 1uLL, &pmatch, 0) )\n {\n rm_so = pmatch.rm_so;\n __memcpy_chk(v3, v1, pmatch.rm_so, v2);\n v5 = 1024LL;\n if ( v2 >= 0x400 )\n v5 = v2;\n v6 = rm_so + v5;\n v7 = rm_so + v5 - v2;\n if ( v7 < v5 )\n v7 = v5;\n v8 = 1024LL;\n v9 = &v3[rm_so];\n *v9 = 32;\n v3 = v9 + 1;\n v10 = v2 - v6 + v7;\n if ( v10 >= 0x400 )\n v8 = v10;\n v11 = v8 - v10 + 1;\n if ( v11 < v8 )\n v11 = v8;\n v2 = v10 - 1 - v8 + v11;\n v1 += pmatch.rm_eo;\n if ( !*v1 )\n goto LABEL_15;\n }\n __strcpy_chk(v3, v1, v2);\n }\nLABEL_15:\n regfree(&preg);\n return &buffer_1;\n}", + "ida_strip_asm": "sub_1300:\nendbr64\npush r15\nmov edx, 1; cflags\nlea rsi, pattern; \" +\"\npush r14\nmov r14, rdi\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 68h\nmov rax, fs:28h\nmov [rsp+98h+var_40], rax\nxor eax, eax\nlea rbp, [rsp+98h+preg]\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njnz loc_1448\ncmp byte ptr [r14], 0\nmov ebx, 400h\nlea r12, [rsp+98h+pmatch]\nlea r13, unk_4040\njnz loc_13E9\njmp loc_1415\nloc_1370:\nmovsxd r15, [rsp+98h+pmatch.rm_so]\nmov rcx, rbx\nmov rsi, r14\nmov rdi, r13\nmov rdx, r15\ncall ___memcpy_chk\nmov edx, 400h\ncmp rbx, rdx\ncmovnb rdx, rbx\nlea rcx, [r15+rdx]\nmov rax, rcx\nsub rax, rbx\ncmp rax, rdx\ncmovb rax, rdx\nsub rbx, rcx\nmov edx, 400h\nadd r15, r13\nmov byte ptr [r15], 20h ; ' '\nlea r13, [r15+1]\nadd rax, rbx\ncmp rax, rdx\ncmovnb rdx, rax\nmov rbx, rdx\nsub rbx, rax\nadd rbx, 1\ncmp rbx, rdx\ncmovb rbx, rdx\nsub rax, 1\nsub rax, rdx\nadd rbx, rax\nmovsxd rax, [rsp+98h+pmatch.rm_eo]\nadd r14, rax\ncmp byte ptr [r14], 0\njz short loc_1415\nloc_13E9:\nxor r8d, r8d; eflags\nmov rcx, r12; pmatch\nmov edx, 1; nmatch\nmov rsi, r14; string\nmov rdi, rbp; preg\ncall _regexec\ntest eax, eax\njz loc_1370\nmov rdx, rbx\nmov rsi, r14\nmov rdi, r13\ncall ___strcpy_chk\nloc_1415:\nmov rdi, rbp; preg\ncall _regfree\nlea rax, unk_4040\nloc_1424:\nmov rdx, [rsp+98h+var_40]\nsub rdx, fs:28h\njnz short loc_144C\nadd rsp, 68h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1448:\nxor eax, eax\njmp short loc_1424\nloc_144C:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "void *__fastcall sub_1300(char *string)\n{\n char *v1; // r14\n unsigned __int64 v2; // rbx\n char *v3; // r13\n __int64 rm_so; // r15\n unsigned __int64 v5; // rdx\n __int64 v6; // rcx\n unsigned __int64 v7; // rax\n unsigned __int64 v8; // rdx\n char *v9; // r15\n unsigned __int64 v10; // rax\n unsigned __int64 v11; // rbx\n regmatch_t pmatch; // [rsp+8h] [rbp-90h] BYREF\n regex_t preg; // [rsp+10h] [rbp-88h] BYREF\n unsigned __int64 v15; // [rsp+58h] [rbp-40h]\n\n v1 = string;\n v15 = __readfsqword(0x28u);\n if ( regcomp(&preg, \" +\", 1) )\n return 0LL;\n v2 = 1024LL;\n v3 = (char *)&unk_4040;\n if ( *string )\n {\n while ( !regexec(&preg, v1, 1uLL, &pmatch, 0) )\n {\n rm_so = pmatch.rm_so;\n __memcpy_chk(v3, v1, pmatch.rm_so, v2);\n v5 = 1024LL;\n if ( v2 >= 0x400 )\n v5 = v2;\n v6 = rm_so + v5;\n v7 = rm_so + v5 - v2;\n if ( v7 < v5 )\n v7 = v5;\n v8 = 1024LL;\n v9 = &v3[rm_so];\n *v9 = 32;\n v3 = v9 + 1;\n v10 = v2 - v6 + v7;\n if ( v10 >= 0x400 )\n v8 = v10;\n v11 = v8 - v10 + 1;\n if ( v11 < v8 )\n v11 = v8;\n v2 = v10 - 1 - v8 + v11;\n v1 += pmatch.rm_eo;\n if ( !*v1 )\n goto LABEL_15;\n }\n __strcpy_chk(v3, v1, v2);\n }\nLABEL_15:\n regfree(&preg);\n return &unk_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1300(char *string) {\n char *v1;\n unsigned long long v2;\n char *v3;\n long long rm_so;\n unsigned long long v5;\n long long v6;\n unsigned long long v7;\n unsigned long long v8;\n char *v9;\n unsigned long long v10;\n unsigned long long v11;\n regmatch_t pmatch;\n regex_t preg;\n unsigned long long v15;\n v1 = string;\n v15 = __readfsqword(40u);\n if (regcomp(&preg, \" +\", 1)) return 0LL;\n v2 = 1024LL;\n v3 = (char *)&unk_4040;\n if (*string) {\n while (!regexec(&preg, v1, 1uLL, &pmatch, 0)) {\n rm_so = pmatch.rm_so;\n __memcpy_chk(v3, v1, pmatch.rm_so, v2);\n v5 = 1024LL;\n if (v2 >= 1024) v5 = v2;\n v6 = rm_so + v5;\n v7 = rm_so + v5 - v2;\n if (v7 < v5) v7 = v5;\n v8 = 1024LL;\n v9 = &v3[rm_so];\n *v9 = 32;\n v3 = v9 + 1;\n v10 = v2 - v6 + v7;\n if (v10 >= 1024) v8 = v10;\n v11 = v8 - v10 + 1;\n if (v11 < v8) v11 = v8;\n v2 = v10 - 1 - v8 + v11;\n v1 += pmatch.rm_eo;\n if (!*v1) goto LABEL_15;\n }\n __strcpy_chk(v3, v1, v2);\n }\nLABEL_15:\n regfree(&preg);\n return &unk_4040;\n}", + "ida_pseudo_norm": "void *func0(char *string) {\n char *v1;\n unsigned long long v2;\n char *v3;\n long long rm_so;\n unsigned long long v5;\n long long v6;\n unsigned long long v7;\n unsigned long long v8;\n char *v9;\n unsigned long long v10;\n unsigned long long v11;\n regmatch_t pmatch;\n regex_t preg;\n unsigned long long v15;\n v1 = string;\n v15 = __readfsqword(40u);\n if (regcomp(&preg, \" +\", 1)) return 0LL;\n v2 = 1024LL;\n v3 = (char *)&buffer_1;\n if (*string) {\n while (!regexec(&preg, v1, 1uLL, &pmatch, 0)) {\n rm_so = pmatch.rm_so;\n __memcpy_chk(v3, v1, pmatch.rm_so, v2);\n v5 = 1024LL;\n if (v2 >= 1024) v5 = v2;\n v6 = rm_so + v5;\n v7 = rm_so + v5 - v2;\n if (v7 < v5) v7 = v5;\n v8 = 1024LL;\n v9 = &v3[rm_so];\n *v9 = 32;\n v3 = v9 + 1;\n v10 = v2 - v6 + v7;\n if (v10 >= 1024) v8 = v10;\n v11 = v8 - v10 + 1;\n if (v11 < v8) v11 = v8;\n v2 = v10 - 1 - v8 + v11;\n v1 += pmatch.rm_eo;\n if (!*v1) goto LABEL_15;\n }\n __strcpy_chk(v3, v1, v2);\n }\nLABEL_15:\n regfree(&preg);\n return &buffer_1;\n}" + }, + { + "index": 893, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int *func0(int **lst, int *sizes, int rows) {\n int *result = malloc(rows * sizeof(int));\n for (int i = 0; i < rows; ++i) {\n result[i] = lst[i][sizes[i] - 1];\n }\n return result;\n}", + "test": "int main() {\n\n // Test case 1\n\n int row1[] = {1, 2, 3};\n\n int row2[] = {4, 5};\n\n int row3[] = {6, 7, 8, 9};\n\n int *list1[] = {row1, row2, row3};\n\n int sizes1[] = {3, 2, 4};\n\n int *result1 = func0(list1, sizes1, 3);\n\n assert(result1[0] == 3 && result1[1] == 5 && result1[2] == 9);\n\n free(result1);\n\n\n\n // Test case 2\n\n int rowx[] = {120, 121, 122}; // 'x', 'y', 'z'\n\n int rowm[] = {109}; // 'm'\n\n int rowa[] = {97, 98}; // 'a', 'b'\n\n int rowu[] = {117, 118}; // 'u', 'v'\n\n int *list2[] = {rowx, rowm, rowa, rowu};\n\n int sizes2[] = {3, 1, 2, 2};\n\n int *result2 = func0(list2, sizes2, 4);\n\n assert(result2[0] == 122 && result2[1] == 109 && result2[2] == 98 && result2[3] == 118);\n\n free(result2);\n\n\n\n // Test case 3\n\n int row31[] = {1, 2, 3};\n\n int row32[] = {4, 5};\n\n int *list3[] = {row31, row32};\n\n int sizes3[] = {3, 2};\n\n int *result3 = func0(list3, sizes3, 2);\n\n assert(result3[0] == 3 && result3[1] == 5);\n\n free(result3);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %edx,-0x24(%rbp)\nmov -0x24(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 1237 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0xc(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x20(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rdx),%edx\nmovslq %edx,%rdx\nshl $0x2,%rdx\nsub $0x4,%rdx\nadd %rdx,%rax\nmov -0xc(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x24(%rbp),%eax\njl 11de \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov eax, [rbp+var_24]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp short loc_1237\nloc_11DE:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_20]\nadd rdx, rcx\nmov edx, [rdx]\nmovsxd rdx, edx\nshl rdx, 2\nsub rdx, 4\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_C], 1\nloc_1237:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_24]\njl short loc_11DE\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n int i; // [rsp+24h] [rbp-Ch]\n _DWORD *v6; // [rsp+28h] [rbp-8h]\n\n v6 = malloc(4LL * a3);\n for ( i = 0; i < a3; ++i )\n v6[i] = *(_DWORD *)(4LL * *(int *)(4LL * i + a2) - 4 + *(_QWORD *)(8LL * i + a1));\n return v6;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov eax, [rbp+var_24]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_C], 0\njmp short loc_1237\nloc_11DE:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_20]\nadd rdx, rcx\nmov edx, [rdx]\nmovsxd rdx, edx\nshl rdx, 2\nsub rdx, 4\nadd rax, rdx\nmov edx, [rbp+var_C]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_C], 1\nloc_1237:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_24]\njl short loc_11DE\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(__int64 a1, __int64 a2, int a3)\n{\n int i; // [rsp+24h] [rbp-Ch]\n _DWORD *v6; // [rsp+28h] [rbp-8h]\n\n v6 = malloc(4LL * a3);\n for ( i = 0; i < a3; ++i )\n v6[i] = *(_DWORD *)(4LL * *(int *)(4LL * i + a2) - 4 + *(_QWORD *)(8LL * i + a1));\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(long long a1, long long a2, int a3) {\n int i;\n uint32_t *v6;\n v6 = malloc(4LL * a3);\n for (i = 0; i < a3; ++i)\n v6[i] = *(uint32_t *)(4LL * *(int *)(4LL * i + a2) - 4 +\n *(uint64_t *)(8LL * i + a1));\n return v6;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, long long a2, int a3) {\n int i;\n uint32_t *v6;\n v6 = malloc(4LL * a3);\n for (i = 0; i < a3; ++i)\n v6[i] = *(uint32_t *)(4LL * *(int *)(4LL * i + a2) - 4 +\n *(uint64_t *)(8LL * i + a1));\n return v6;\n}" + }, + { + "index": 893, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int *func0(int **lst, int *sizes, int rows) {\n int *result = malloc(rows * sizeof(int));\n for (int i = 0; i < rows; ++i) {\n result[i] = lst[i][sizes[i] - 1];\n }\n return result;\n}", + "test": "int main() {\n\n // Test case 1\n\n int row1[] = {1, 2, 3};\n\n int row2[] = {4, 5};\n\n int row3[] = {6, 7, 8, 9};\n\n int *list1[] = {row1, row2, row3};\n\n int sizes1[] = {3, 2, 4};\n\n int *result1 = func0(list1, sizes1, 3);\n\n assert(result1[0] == 3 && result1[1] == 5 && result1[2] == 9);\n\n free(result1);\n\n\n\n // Test case 2\n\n int rowx[] = {120, 121, 122}; // 'x', 'y', 'z'\n\n int rowm[] = {109}; // 'm'\n\n int rowa[] = {97, 98}; // 'a', 'b'\n\n int rowu[] = {117, 118}; // 'u', 'v'\n\n int *list2[] = {rowx, rowm, rowa, rowu};\n\n int sizes2[] = {3, 1, 2, 2};\n\n int *result2 = func0(list2, sizes2, 4);\n\n assert(result2[0] == 122 && result2[1] == 109 && result2[2] == 98 && result2[3] == 118);\n\n free(result2);\n\n\n\n // Test case 3\n\n int row31[] = {1, 2, 3};\n\n int row32[] = {4, 5};\n\n int *list3[] = {row31, row32};\n\n int sizes3[] = {3, 2};\n\n int *result3 = func0(list3, sizes3, 2);\n\n assert(result3[0] == 3 && result3[1] == 5);\n\n free(result3);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nmov %rsi,%rbp\nmov %edx,%r12d\nmovslq %edx,%rdi\nshl $0x2,%rdi\ncallq 10b0 \ntest %r12d,%r12d\njle 11f1 \nlea -0x1(%r12),%edi\nmov $0x0,%edx\nmovslq 0x0(%rbp,%rdx,4),%rsi\nmov (%rbx,%rdx,8),%rcx\nmov -0x4(%rcx,%rsi,4),%ecx\nmov %ecx,(%rax,%rdx,4)\nmov %rdx,%rcx\nadd $0x1,%rdx\ncmp %rdi,%rcx\njne 11d5 \npop %rbx\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov r12, rsi\nmov r13d, edx\nmovsxd rbx, edx\nshl rbx, 2\nmov rdi, rbx; size\ncall _malloc\ntest r13d, r13d\njle short loc_11F2\nmov edx, 0\nloc_11D9:\nmovsxd rsi, dword ptr [r12+rdx]\nmov rcx, [rbp+rdx*2+0]\nmov ecx, [rcx+rsi*4-4]\nmov [rax+rdx], ecx\nadd rdx, 4\ncmp rbx, rdx\njnz short loc_11D9\nloc_11F2:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n size_t v4; // rbx\n char *result; // rax\n __int64 v6; // rdx\n\n v4 = 4LL * a3;\n result = (char *)malloc(v4);\n if ( a3 > 0 )\n {\n v6 = 0LL;\n do\n {\n *(_DWORD *)&result[v6] = *(_DWORD *)(*(_QWORD *)(a1 + 2 * v6) + 4LL * *(int *)(a2 + v6) - 4);\n v6 += 4LL;\n }\n while ( v4 != v6 );\n }\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov r12, rsi\nmov r13d, edx\nmovsxd rbx, edx\nshl rbx, 2\nmov rdi, rbx; size\ncall _malloc\ntest r13d, r13d\njle short loc_11F2\nmov edx, 0\nloc_11D9:\nmovsxd rsi, dword ptr [r12+rdx]\nmov rcx, [rbp+rdx*2+0]\nmov ecx, [rcx+rsi*4-4]\nmov [rax+rdx], ecx\nadd rdx, 4\ncmp rbx, rdx\njnz short loc_11D9\nloc_11F2:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11A9(__int64 a1, __int64 a2, int a3)\n{\n size_t v4; // rbx\n char *result; // rax\n __int64 v6; // rdx\n\n v4 = 4LL * a3;\n result = (char *)malloc(v4);\n if ( a3 > 0 )\n {\n v6 = 0LL;\n do\n {\n *(_DWORD *)&result[v6] = *(_DWORD *)(*(_QWORD *)(a1 + 2 * v6) + 4LL * *(int *)(a2 + v6) - 4);\n v6 += 4LL;\n }\n while ( v4 != v6 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11A9(long long a1, long long a2, int a3) {\n unsigned int v4;\n char *result;\n long long v6;\n v4 = 4LL * a3;\n result = (char *)malloc(v4);\n if (a3 > 0) {\n v6 = 0LL;\n do {\n *(uint32_t *)&result[v6] = *(uint32_t *)(*(uint64_t *)(a1 + 2 * v6) +\n 4LL * *(int *)(a2 + v6) - 4);\n v6 += 4LL;\n } while (v4 != v6);\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(long long a1, long long a2, int a3) {\n unsigned int v4;\n char *result;\n long long v6;\n v4 = 4LL * a3;\n result = (char *)malloc(v4);\n if (a3 > 0) {\n v6 = 0LL;\n do {\n *(uint32_t *)&result[v6] = *(uint32_t *)(*(uint64_t *)(a1 + 2 * v6) +\n 4LL * *(int *)(a2 + v6) - 4);\n v6 += 4LL;\n } while (v4 != v6);\n }\n return result;\n}" + }, + { + "index": 893, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int *func0(int **lst, int *sizes, int rows) {\n int *result = malloc(rows * sizeof(int));\n for (int i = 0; i < rows; ++i) {\n result[i] = lst[i][sizes[i] - 1];\n }\n return result;\n}", + "test": "int main() {\n\n // Test case 1\n\n int row1[] = {1, 2, 3};\n\n int row2[] = {4, 5};\n\n int row3[] = {6, 7, 8, 9};\n\n int *list1[] = {row1, row2, row3};\n\n int sizes1[] = {3, 2, 4};\n\n int *result1 = func0(list1, sizes1, 3);\n\n assert(result1[0] == 3 && result1[1] == 5 && result1[2] == 9);\n\n free(result1);\n\n\n\n // Test case 2\n\n int rowx[] = {120, 121, 122}; // 'x', 'y', 'z'\n\n int rowm[] = {109}; // 'm'\n\n int rowa[] = {97, 98}; // 'a', 'b'\n\n int rowu[] = {117, 118}; // 'u', 'v'\n\n int *list2[] = {rowx, rowm, rowa, rowu};\n\n int sizes2[] = {3, 1, 2, 2};\n\n int *result2 = func0(list2, sizes2, 4);\n\n assert(result2[0] == 122 && result2[1] == 109 && result2[2] == 98 && result2[3] == 118);\n\n free(result2);\n\n\n\n // Test case 3\n\n int row31[] = {1, 2, 3};\n\n int row32[] = {4, 5};\n\n int *list3[] = {row31, row32};\n\n int sizes3[] = {3, 2};\n\n int *result3 = func0(list3, sizes3, 2);\n\n assert(result3[0] == 3 && result3[1] == 5);\n\n free(result3);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\nmov %rsi,%rbp\npush %rbx\nmov %rdi,%rbx\nmovslq %edx,%rdi\nmov %rdi,%r12\nshl $0x2,%rdi\ncallq 10b0 \ntest %r12d,%r12d\njle 149c \nlea -0x1(%r12),%esi\nxor %edx,%edx\nnopl 0x0(%rax)\nmovslq 0x0(%rbp,%rdx,4),%rdi\nmov (%rbx,%rdx,8),%rcx\nmov -0x4(%rcx,%rdi,4),%ecx\nmov %ecx,(%rax,%rdx,4)\nmov %rdx,%rcx\nadd $0x1,%rdx\ncmp %rsi,%rcx\njne 1480 \npop %rbx\npop %rbp\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\nmov r12, rsi\npush rbp\nmov rbp, rdi\npush rbx\nmovsxd rbx, edx\nmov r13, rbx\nshl rbx, 2\nmov rdi, rbx; size\nsub rsp, 8\ncall _malloc\ntest r13d, r13d\njle short loc_14A9\nxor edx, edx\nnop dword ptr [rax]\nloc_1490:\nmovsxd rdi, dword ptr [r12+rdx]\nmov rcx, [rbp+rdx*2+0]\nmov ecx, [rcx+rdi*4-4]\nmov [rax+rdx], ecx\nadd rdx, 4\ncmp rbx, rdx\njnz short loc_1490\nloc_14A9:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n size_t v4; // rbx\n char *result; // rax\n __int64 v6; // rdx\n\n v4 = 4LL * a3;\n result = (char *)malloc(v4);\n if ( a3 > 0 )\n {\n v6 = 0LL;\n do\n {\n *(_DWORD *)&result[v6] = *(_DWORD *)(*(_QWORD *)(a1 + 2 * v6) + 4LL * *(int *)(a2 + v6) - 4);\n v6 += 4LL;\n }\n while ( v4 != v6 );\n }\n return result;\n}", + "ida_strip_asm": "sub_1460:\nendbr64\npush r13\npush r12\nmov r12, rsi\npush rbp\nmov rbp, rdi\npush rbx\nmovsxd rbx, edx\nmov r13, rbx\nshl rbx, 2\nmov rdi, rbx; size\nsub rsp, 8\ncall _malloc\ntest r13d, r13d\njle short loc_14A9\nxor edx, edx\nnop dword ptr [rax]\nloc_1490:\nmovsxd rdi, dword ptr [r12+rdx]\nmov rcx, [rbp+rdx*2+0]\nmov ecx, [rcx+rdi*4-4]\nmov [rax+rdx], ecx\nadd rdx, 4\ncmp rbx, rdx\njnz short loc_1490\nloc_14A9:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1460(__int64 a1, __int64 a2, int a3)\n{\n size_t v4; // rbx\n char *result; // rax\n __int64 v6; // rdx\n\n v4 = 4LL * a3;\n result = (char *)malloc(v4);\n if ( a3 > 0 )\n {\n v6 = 0LL;\n do\n {\n *(_DWORD *)&result[v6] = *(_DWORD *)(*(_QWORD *)(a1 + 2 * v6) + 4LL * *(int *)(a2 + v6) - 4);\n v6 += 4LL;\n }\n while ( v4 != v6 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1460(long long a1, long long a2, int a3) {\n unsigned int v4;\n char *result;\n long long v6;\n v4 = 4LL * a3;\n result = (char *)malloc(v4);\n if (a3 > 0) {\n v6 = 0LL;\n do {\n *(uint32_t *)&result[v6] = *(uint32_t *)(*(uint64_t *)(a1 + 2 * v6) +\n 4LL * *(int *)(a2 + v6) - 4);\n v6 += 4LL;\n } while (v4 != v6);\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(long long a1, long long a2, int a3) {\n unsigned int v4;\n char *result;\n long long v6;\n v4 = 4LL * a3;\n result = (char *)malloc(v4);\n if (a3 > 0) {\n v6 = 0LL;\n do {\n *(uint32_t *)&result[v6] = *(uint32_t *)(*(uint64_t *)(a1 + 2 * v6) +\n 4LL * *(int *)(a2 + v6) - 4);\n v6 += 4LL;\n } while (v4 != v6);\n }\n return result;\n}" + }, + { + "index": 893, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int *func0(int **lst, int *sizes, int rows) {\n int *result = malloc(rows * sizeof(int));\n for (int i = 0; i < rows; ++i) {\n result[i] = lst[i][sizes[i] - 1];\n }\n return result;\n}", + "test": "int main() {\n\n // Test case 1\n\n int row1[] = {1, 2, 3};\n\n int row2[] = {4, 5};\n\n int row3[] = {6, 7, 8, 9};\n\n int *list1[] = {row1, row2, row3};\n\n int sizes1[] = {3, 2, 4};\n\n int *result1 = func0(list1, sizes1, 3);\n\n assert(result1[0] == 3 && result1[1] == 5 && result1[2] == 9);\n\n free(result1);\n\n\n\n // Test case 2\n\n int rowx[] = {120, 121, 122}; // 'x', 'y', 'z'\n\n int rowm[] = {109}; // 'm'\n\n int rowa[] = {97, 98}; // 'a', 'b'\n\n int rowu[] = {117, 118}; // 'u', 'v'\n\n int *list2[] = {rowx, rowm, rowa, rowu};\n\n int sizes2[] = {3, 1, 2, 2};\n\n int *result2 = func0(list2, sizes2, 4);\n\n assert(result2[0] == 122 && result2[1] == 109 && result2[2] == 98 && result2[3] == 118);\n\n free(result2);\n\n\n\n // Test case 3\n\n int row31[] = {1, 2, 3};\n\n int row32[] = {4, 5};\n\n int *list3[] = {row31, row32};\n\n int sizes3[] = {3, 2};\n\n int *result3 = func0(list3, sizes3, 2);\n\n assert(result3[0] == 3 && result3[1] == 5);\n\n free(result3);\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\nmov %rsi,%rbp\npush %rbx\nmov %rdi,%rbx\nmovslq %edx,%rdi\nmov %rdi,%r12\nshl $0x2,%rdi\ncallq 10b0 \ntest %r12d,%r12d\njle 148c \nlea -0x1(%r12),%esi\nxor %edx,%edx\nnopl 0x0(%rax)\nmovslq 0x0(%rbp,%rdx,4),%rdi\nmov (%rbx,%rdx,8),%rcx\nmov -0x4(%rcx,%rdi,4),%ecx\nmov %ecx,(%rax,%rdx,4)\nmov %rdx,%rcx\nadd $0x1,%rdx\ncmp %rsi,%rcx\njne 1470 \npop %rbx\npop %rbp\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\nmov r12, rsi\npush rbp\nmov rbp, rdi\npush rbx\nmovsxd rbx, edx\nmov r13, rbx\nshl rbx, 2\nmov rdi, rbx; size\nsub rsp, 8\ncall _malloc\ntest r13d, r13d\njle short loc_14A9\nxor edx, edx\nnop dword ptr [rax]\nloc_1490:\nmovsxd rdi, dword ptr [r12+rdx]\nmov rcx, [rbp+rdx*2+0]\nmov ecx, [rcx+rdi*4-4]\nmov [rax+rdx], ecx\nadd rdx, 4\ncmp rbx, rdx\njnz short loc_1490\nloc_14A9:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n size_t v4; // rbx\n char *result; // rax\n __int64 v6; // rdx\n\n v4 = 4LL * a3;\n result = (char *)malloc(v4);\n if ( a3 > 0 )\n {\n v6 = 0LL;\n do\n {\n *(_DWORD *)&result[v6] = *(_DWORD *)(*(_QWORD *)(a1 + 2 * v6) + 4LL * *(int *)(a2 + v6) - 4);\n v6 += 4LL;\n }\n while ( v4 != v6 );\n }\n return result;\n}", + "ida_strip_asm": "sub_1460:\nendbr64\npush r13\npush r12\nmov r12, rsi\npush rbp\nmov rbp, rdi\npush rbx\nmovsxd rbx, edx\nmov r13, rbx\nshl rbx, 2\nmov rdi, rbx; size\nsub rsp, 8\ncall _malloc\ntest r13d, r13d\njle short loc_14A9\nxor edx, edx\nnop dword ptr [rax]\nloc_1490:\nmovsxd rdi, dword ptr [r12+rdx]\nmov rcx, [rbp+rdx*2+0]\nmov ecx, [rcx+rdi*4-4]\nmov [rax+rdx], ecx\nadd rdx, 4\ncmp rbx, rdx\njnz short loc_1490\nloc_14A9:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1460(__int64 a1, __int64 a2, int a3)\n{\n size_t v4; // rbx\n char *result; // rax\n __int64 v6; // rdx\n\n v4 = 4LL * a3;\n result = (char *)malloc(v4);\n if ( a3 > 0 )\n {\n v6 = 0LL;\n do\n {\n *(_DWORD *)&result[v6] = *(_DWORD *)(*(_QWORD *)(a1 + 2 * v6) + 4LL * *(int *)(a2 + v6) - 4);\n v6 += 4LL;\n }\n while ( v4 != v6 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1460(long long a1, long long a2, int a3) {\n unsigned int v4;\n char *result;\n long long v6;\n v4 = 4LL * a3;\n result = (char *)malloc(v4);\n if (a3 > 0) {\n v6 = 0LL;\n do {\n *(uint32_t *)&result[v6] = *(uint32_t *)(*(uint64_t *)(a1 + 2 * v6) +\n 4LL * *(int *)(a2 + v6) - 4);\n v6 += 4LL;\n } while (v4 != v6);\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(long long a1, long long a2, int a3) {\n unsigned int v4;\n char *result;\n long long v6;\n v4 = 4LL * a3;\n result = (char *)malloc(v4);\n if (a3 > 0) {\n v6 = 0LL;\n do {\n *(uint32_t *)&result[v6] = *(uint32_t *)(*(uint64_t *)(a1 + 2 * v6) +\n 4LL * *(int *)(a2 + v6) - 4);\n v6 += 4LL;\n } while (v4 != v6);\n }\n return result;\n}" + }, + { + "index": 894, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n float *elements;\n\n int size;\n\n} FloatTuple;\n\n\n\n", + "func": "FloatTuple func0(const char *test_str) {\n FloatTuple res;\n int estimate_size = 10;\n res.elements = malloc(estimate_size * sizeof(float));\n res.size = 0;\n char *token = strtok(strdup(test_str), \", \");\n while (token != NULL) {\n if (res.size >= estimate_size) {\n estimate_size *= 2;\n res.elements = realloc(res.elements, estimate_size * sizeof(float));\n }\n res.elements[res.size++] = atof(token);\n token = strtok(NULL, \", \");\n }\n return res;\n}", + "test": "int main() {\n\n FloatTuple result1 = func0(\"1.2, 1.3, 2.3, 2.4, 6.5\");\n\n FloatTuple expected1 = {.elements = (float[]){1.2, 1.3, 2.3, 2.4, 6.5}, .size = 5};\n\n assert(result1.size == expected1.size && memcmp(result1.elements, expected1.elements, result1.size * sizeof(float)) == 0);\n\n\n\n FloatTuple result2 = func0(\"2.3, 2.4, 5.6, 5.4, 8.9\");\n\n FloatTuple expected2 = {.elements = (float[]){2.3, 2.4, 5.6, 5.4, 8.9}, .size = 5};\n\n assert(result2.size == expected2.size && memcmp(result2.elements, expected2.elements, result2.size * sizeof(float)) == 0);\n\n\n\n FloatTuple result3 = func0(\"0.3, 0.5, 7.8, 9.4\");\n\n FloatTuple expected3 = {.elements = (float[]){0.3, 0.5, 7.8, 9.4}, .size = 4};\n\n assert(result3.size == expected3.size && memcmp(result3.elements, expected3.elements, result3.size * sizeof(float)) == 0);\n\n\n\n free(result1.elements);\n\n free(result2.elements);\n\n free(result3.elements);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x28(%rbp)\nmovl $0xa,-0x1c(%rbp)\nmov -0x1c(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 1120 \nmov %rax,-0x10(%rbp)\nmovl $0x0,-0x8(%rbp)\nmov -0x28(%rbp),%rax\nmov %rax,%rdi\ncallq 1150 \nlea 0xd79(%rip),%rsi\nmov %rax,%rdi\ncallq 1140 \nmov %rax,-0x18(%rbp)\njmp 1307 \nmov -0x8(%rbp),%eax\ncmp %eax,-0x1c(%rbp)\njg 12c8 \nshll -0x1c(%rbp)\nmov -0x1c(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x10(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1130 \nmov %rax,-0x10(%rbp)\nmov -0x18(%rbp),%rax\nmov %rax,%rdi\ncallq 10e0 \nmov -0x10(%rbp),%rcx\nmov -0x8(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x8(%rbp)\ncltq\nshl $0x2,%rax\nadd %rcx,%rax\ncvtsd2ss %xmm0,%xmm0\nmovss %xmm0,(%rax)\nlea 0xd0f(%rip),%rsi\nmov $0x0,%edi\ncallq 1140 \nmov %rax,-0x18(%rbp)\ncmpq $0x0,-0x18(%rbp)\njne 129d \nmov -0x10(%rbp),%rax\nmov -0x8(%rbp),%rdx\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov [rbp+var_1C], 0Ah\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov dword ptr [rbp+var_8], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strdup\nmov rdx, rax\nlea rax, delim; \", \"\nmov rsi, rax; delim\nmov rdi, rdx; s\ncall _strtok\nmov [rbp+nptr], rax\njmp short loc_1310\nloc_12A3:\nmov eax, dword ptr [rbp+var_8]\ncmp [rbp+var_1C], eax\njg short loc_12CE\nshl [rbp+var_1C], 1\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nmov rsi, rdx; size\nmov rdi, rax; ptr\ncall _realloc\nmov [rbp+ptr], rax\nloc_12CE:\nmov rax, [rbp+nptr]\nmov rdi, rax; nptr\ncall _atof\nmov rcx, [rbp+ptr]\nmov eax, dword ptr [rbp+var_8]\nlea edx, [rax+1]\nmov dword ptr [rbp+var_8], edx\ncdqe\nshl rax, 2\nadd rax, rcx\ncvtsd2ss xmm0, xmm0\nmovss dword ptr [rax], xmm0\nlea rax, delim; \", \"\nmov rsi, rax; delim\nmov edi, 0; s\ncall _strtok\nmov [rbp+nptr], rax\nloc_1310:\ncmp [rbp+nptr], 0\njnz short loc_12A3\nmov rax, [rbp+ptr]\nmov rdx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "void *__fastcall func0(const char *a1)\n{\n char *v1; // rax\n double v2; // xmm0_8\n int v3; // eax\n int v5; // [rsp+14h] [rbp-1Ch]\n const char *nptr; // [rsp+18h] [rbp-18h]\n void *ptr; // [rsp+20h] [rbp-10h]\n int v8; // [rsp+28h] [rbp-8h]\n\n v5 = 10;\n ptr = malloc(0x28uLL);\n v8 = 0;\n v1 = strdup(a1);\n for ( nptr = strtok(v1, \", \"); nptr; nptr = strtok(0LL, \", \") )\n {\n if ( v5 <= v8 )\n {\n v5 *= 2;\n ptr = realloc(ptr, 4LL * v5);\n }\n v2 = atof(nptr);\n v3 = v8++;\n *(float *)&v2 = v2;\n *((_DWORD *)ptr + v3) = LODWORD(v2);\n }\n return ptr;\n}", + "ida_strip_asm": "sub_1249:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov [rbp+var_1C], 0Ah\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov dword ptr [rbp+var_8], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strdup\nmov rdx, rax\nlea rax, delim; \", \"\nmov rsi, rax; delim\nmov rdi, rdx; s\ncall _strtok\nmov [rbp+nptr], rax\njmp short loc_1310\nloc_12A3:\nmov eax, dword ptr [rbp+var_8]\ncmp [rbp+var_1C], eax\njg short loc_12CE\nshl [rbp+var_1C], 1\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nmov rsi, rdx; size\nmov rdi, rax; ptr\ncall _realloc\nmov [rbp+ptr], rax\nloc_12CE:\nmov rax, [rbp+nptr]\nmov rdi, rax; nptr\ncall _atof\nmov rcx, [rbp+ptr]\nmov eax, dword ptr [rbp+var_8]\nlea edx, [rax+1]\nmov dword ptr [rbp+var_8], edx\ncdqe\nshl rax, 2\nadd rax, rcx\ncvtsd2ss xmm0, xmm0\nmovss dword ptr [rax], xmm0\nlea rax, delim; \", \"\nmov rsi, rax; delim\nmov edi, 0; s\ncall _strtok\nmov [rbp+nptr], rax\nloc_1310:\ncmp [rbp+nptr], 0\njnz short loc_12A3\nmov rax, [rbp+ptr]\nmov rdx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "void *__fastcall sub_1249(const char *a1)\n{\n char *v1; // rax\n double v2; // xmm0_8\n int v3; // eax\n int v5; // [rsp+14h] [rbp-1Ch]\n const char *nptr; // [rsp+18h] [rbp-18h]\n void *ptr; // [rsp+20h] [rbp-10h]\n int v8; // [rsp+28h] [rbp-8h]\n\n v5 = 10;\n ptr = malloc(0x28uLL);\n v8 = 0;\n v1 = strdup(a1);\n for ( nptr = strtok(v1, \", \"); nptr; nptr = strtok(0LL, \", \") )\n {\n if ( v5 <= v8 )\n {\n v5 *= 2;\n ptr = realloc(ptr, 4LL * v5);\n }\n v2 = atof(nptr);\n v3 = v8++;\n *(float *)&v2 = v2;\n *((_DWORD *)ptr + v3) = LODWORD(v2);\n }\n return ptr;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1249(const char *a1) {\n char *v1;\n double v2;\n int v3;\n int v5;\n const char *nptr;\n void *ptr;\n int v8;\n v5 = 10;\n ptr = malloc(40uLL);\n v8 = 0;\n v1 = strdup(a1);\n for (nptr = strtok(v1, \", \"); nptr; nptr = strtok(0LL, \", \")) {\n if (v5 <= v8) {\n v5 *= 2;\n ptr = realloc(ptr, 4LL * v5);\n }\n v2 = atof(nptr);\n v3 = v8++;\n *(float *)&v2 = v2;\n *((uint32_t *)ptr + v3) = LODWORD(v2);\n }\n return ptr;\n}", + "ida_pseudo_norm": "void *func0(const char *a1) {\n char *v1;\n double v2;\n int v3;\n int v5;\n const char *nptr;\n void *ptr;\n int v8;\n v5 = 10;\n ptr = malloc(40uLL);\n v8 = 0;\n v1 = strdup(a1);\n for (nptr = strtok(v1, \", \"); nptr; nptr = strtok(0LL, \", \")) {\n if (v5 <= v8) {\n v5 *= 2;\n ptr = realloc(ptr, 4LL * v5);\n }\n v2 = atof(nptr);\n v3 = v8++;\n *(float *)&v2 = v2;\n *((uint32_t *)ptr + v3) = LODWORD(v2);\n }\n return ptr;\n}" + }, + { + "index": 894, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n float *elements;\n\n int size;\n\n} FloatTuple;\n\n\n\n", + "func": "FloatTuple func0(const char *test_str) {\n FloatTuple res;\n int estimate_size = 10;\n res.elements = malloc(estimate_size * sizeof(float));\n res.size = 0;\n char *token = strtok(strdup(test_str), \", \");\n while (token != NULL) {\n if (res.size >= estimate_size) {\n estimate_size *= 2;\n res.elements = realloc(res.elements, estimate_size * sizeof(float));\n }\n res.elements[res.size++] = atof(token);\n token = strtok(NULL, \", \");\n }\n return res;\n}", + "test": "int main() {\n\n FloatTuple result1 = func0(\"1.2, 1.3, 2.3, 2.4, 6.5\");\n\n FloatTuple expected1 = {.elements = (float[]){1.2, 1.3, 2.3, 2.4, 6.5}, .size = 5};\n\n assert(result1.size == expected1.size && memcmp(result1.elements, expected1.elements, result1.size * sizeof(float)) == 0);\n\n\n\n FloatTuple result2 = func0(\"2.3, 2.4, 5.6, 5.4, 8.9\");\n\n FloatTuple expected2 = {.elements = (float[]){2.3, 2.4, 5.6, 5.4, 8.9}, .size = 5};\n\n assert(result2.size == expected2.size && memcmp(result2.elements, expected2.elements, result2.size * sizeof(float)) == 0);\n\n\n\n FloatTuple result3 = func0(\"0.3, 0.5, 7.8, 9.4\");\n\n FloatTuple expected3 = {.elements = (float[]){0.3, 0.5, 7.8, 9.4}, .size = 4};\n\n assert(result3.size == expected3.size && memcmp(result3.elements, expected3.elements, result3.size * sizeof(float)) == 0);\n\n\n\n free(result1.elements);\n\n free(result2.elements);\n\n free(result3.elements);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbx\nmov $0x28,%edi\ncallq 1120 \nmov %rax,%r12\nmov %rbx,%rdi\ncallq 1150 \nmov %rax,%rdi\nlea 0xd87(%rip),%rsi\ncallq 1140 \nmov %rax,%rbx\nmov $0x0,%ebp\nmov $0xa,%r14d\nlea 0xd6d(%rip),%r15\nmov $0x0,%r13d\ntest %rax,%rax\njne 12bb \nmov %r13d,%edx\nmov %r12,%rax\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nadd $0x1,%rbp\nmov $0x0,%esi\nmov %rbx,%rdi\ncallq 10e0 \nlea 0x1(%rbp),%r13d\ncvtsd2ss %xmm0,%xmm0\nmovss %xmm0,(%r12,%rbp,4)\nmov %r15,%rsi\nmov $0x0,%edi\ncallq 1140 \nmov %rax,%rbx\ntest %rax,%rax\nje 12a2 \ncmp %r13d,%r14d\njg 12b7 \nadd %r14d,%r14d\nmovslq %r14d,%rsi\nshl $0x2,%rsi\nmov %r12,%rdi\ncallq 1130 \nmov %rax,%r12\njmp 12b7 \n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nmov edi, 28h ; '('; size\ncall _malloc\nmov r12, rax\nmov rdi, rbx; s\ncall _strdup\nmov rdi, rax; s\nlea rsi, delim; \", \"\ncall _strtok\ntest rax, rax\njz short loc_12F8\nmov rbx, rax\nmov ebp, 0\nmov r13d, 0Ah\nlea r14, delim; \", \"\njmp short loc_12CB\nloc_1298:\nmov esi, 0; endptr\nmov rdi, rbx; nptr\ncall _strtod\ncvtsd2ss xmm0, xmm0\nmovss dword ptr [r12+rbp*4], xmm0\nmov rsi, r14; delim\nmov edi, 0; s\ncall _strtok\nmov rbx, rax\nlea rax, [rbp+1]\ntest rbx, rbx\njz short loc_12E7\nmov rbp, rax\nloc_12CB:\ncmp r13d, ebp\njg short loc_1298\nadd r13d, r13d\nmovsxd rsi, r13d\nshl rsi, 2; size\nmov rdi, r12; ptr\ncall _realloc\nmov r12, rax\njmp short loc_1298\nloc_12E7:\nlea edx, [rbp+1]\nloc_12EA:\nmov edx, edx\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_12F8:\nmov edx, 0\njmp short loc_12EA", + "ida_pseudo": "void *__fastcall func0(char *s)\n{\n void *v1; // r12\n char *v2; // rax\n char *v3; // rax\n char *v4; // rbx\n __int64 v5; // rbp\n int v6; // r13d\n float v7; // xmm0_4\n\n v1 = malloc(0x28uLL);\n v2 = strdup(s);\n v3 = strtok(v2, \", \");\n if ( v3 )\n {\n v4 = v3;\n v5 = 0LL;\n v6 = 10;\n while ( 1 )\n {\n if ( v6 <= (int)v5 )\n {\n v6 *= 2;\n v1 = realloc(v1, 4LL * v6);\n }\n v7 = strtod(v4, 0LL);\n *((float *)v1 + v5) = v7;\n v4 = strtok(0LL, \", \");\n if ( !v4 )\n break;\n ++v5;\n }\n }\n return v1;\n}", + "ida_strip_asm": "sub_1249:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nmov edi, 28h ; '('; size\ncall _malloc\nmov r12, rax\nmov rdi, rbx; s\ncall _strdup\nmov rdi, rax; s\nlea rsi, delim; \", \"\ncall _strtok\ntest rax, rax\njz short loc_12F8\nmov rbx, rax\nmov ebp, 0\nmov r13d, 0Ah\nlea r14, delim; \", \"\njmp short loc_12CB\nloc_1298:\nmov esi, 0; endptr\nmov rdi, rbx; nptr\ncall _strtod\ncvtsd2ss xmm0, xmm0\nmovss dword ptr [r12+rbp*4], xmm0\nmov rsi, r14; delim\nmov edi, 0; s\ncall _strtok\nmov rbx, rax\nlea rax, [rbp+1]\ntest rbx, rbx\njz short loc_12E7\nmov rbp, rax\nloc_12CB:\ncmp r13d, ebp\njg short loc_1298\nadd r13d, r13d\nmovsxd rsi, r13d\nshl rsi, 2; size\nmov rdi, r12; ptr\ncall _realloc\nmov r12, rax\njmp short loc_1298\nloc_12E7:\nlea edx, [rbp+1]\nloc_12EA:\nmov edx, edx\nmov rax, r12\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_12F8:\nmov edx, 0\njmp short loc_12EA", + "ida_strip_pseudo": "void *__fastcall sub_1249(char *s)\n{\n void *v1; // r12\n char *v2; // rax\n char *v3; // rax\n char *v4; // rbx\n __int64 v5; // rbp\n int v6; // r13d\n float v7; // xmm0_4\n\n v1 = malloc(0x28uLL);\n v2 = strdup(s);\n v3 = strtok(v2, \", \");\n if ( v3 )\n {\n v4 = v3;\n v5 = 0LL;\n v6 = 10;\n while ( 1 )\n {\n if ( v6 <= (int)v5 )\n {\n v6 *= 2;\n v1 = realloc(v1, 4LL * v6);\n }\n v7 = strtod(v4, 0LL);\n *((float *)v1 + v5) = v7;\n v4 = strtok(0LL, \", \");\n if ( !v4 )\n break;\n ++v5;\n }\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1249(char *s) {\n void *v1;\n char *v2;\n char *v3;\n char *v4;\n long long v5;\n int v6;\n float v7;\n v1 = malloc(40uLL);\n v2 = strdup(s);\n v3 = strtok(v2, \", \");\n if (v3) {\n v4 = v3;\n v5 = 0LL;\n v6 = 10;\n while (1) {\n if (v6 <= (int)v5) {\n v6 *= 2;\n v1 = realloc(v1, 4LL * v6);\n }\n v7 = strtod(v4, 0LL);\n *((float *)v1 + v5) = v7;\n v4 = strtok(0LL, \", \");\n if (!v4) break;\n ++v5;\n }\n }\n return v1;\n}", + "ida_pseudo_norm": "void *func0(char *s) {\n void *v1;\n char *v2;\n char *v3;\n char *v4;\n long long v5;\n int v6;\n float v7;\n v1 = malloc(40uLL);\n v2 = strdup(s);\n v3 = strtok(v2, \", \");\n if (v3) {\n v4 = v3;\n v5 = 0LL;\n v6 = 10;\n while (1) {\n if (v6 <= (int)v5) {\n v6 *= 2;\n v1 = realloc(v1, 4LL * v6);\n }\n v7 = strtod(v4, 0LL);\n *((float *)v1 + v5) = v7;\n v4 = strtok(0LL, \", \");\n if (!v4) break;\n ++v5;\n }\n }\n return v1;\n}" + }, + { + "index": 894, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n float *elements;\n\n int size;\n\n} FloatTuple;\n\n\n\n", + "func": "FloatTuple func0(const char *test_str) {\n FloatTuple res;\n int estimate_size = 10;\n res.elements = malloc(estimate_size * sizeof(float));\n res.size = 0;\n char *token = strtok(strdup(test_str), \", \");\n while (token != NULL) {\n if (res.size >= estimate_size) {\n estimate_size *= 2;\n res.elements = realloc(res.elements, estimate_size * sizeof(float));\n }\n res.elements[res.size++] = atof(token);\n token = strtok(NULL, \", \");\n }\n return res;\n}", + "test": "int main() {\n\n FloatTuple result1 = func0(\"1.2, 1.3, 2.3, 2.4, 6.5\");\n\n FloatTuple expected1 = {.elements = (float[]){1.2, 1.3, 2.3, 2.4, 6.5}, .size = 5};\n\n assert(result1.size == expected1.size && memcmp(result1.elements, expected1.elements, result1.size * sizeof(float)) == 0);\n\n\n\n FloatTuple result2 = func0(\"2.3, 2.4, 5.6, 5.4, 8.9\");\n\n FloatTuple expected2 = {.elements = (float[]){2.3, 2.4, 5.6, 5.4, 8.9}, .size = 5};\n\n assert(result2.size == expected2.size && memcmp(result2.elements, expected2.elements, result2.size * sizeof(float)) == 0);\n\n\n\n FloatTuple result3 = func0(\"0.3, 0.5, 7.8, 9.4\");\n\n FloatTuple expected3 = {.elements = (float[]){0.3, 0.5, 7.8, 9.4}, .size = 4};\n\n assert(result3.size == expected3.size && memcmp(result3.elements, expected3.elements, result3.size * sizeof(float)) == 0);\n\n\n\n free(result1.elements);\n\n free(result2.elements);\n\n free(result3.elements);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\nxor %r13d,%r13d\npush %r12\npush %rbp\nmov %rdi,%rbp\nmov $0x28,%edi\npush %rbx\nsub $0x8,%rsp\ncallq 1100 \nmov %rbp,%rdi\nmov %rax,%r12\ncallq 1130 \nlea 0xbf0(%rip),%rsi\nmov %rax,%rdi\ncallq 1120 \ntest %rax,%rax\nje 1480 \nmov %rax,%rbp\nxor %ebx,%ebx\nmov $0xa,%r14d\nlea 0xbd1(%rip),%r15\njmp 1456 \nnopl (%rax)\ncmp %r13d,%r14d\njg 1452 \nadd %r14d,%r14d\nmov %r12,%rdi\nmovslq %r14d,%rsi\nshl $0x2,%rsi\ncallq 1110 \nmov %rax,%r12\nadd $0x1,%rbx\nmov %rbp,%rdi\nxor %esi,%esi\nlea 0x1(%rbx),%r13d\ncallq 10d0 \nmov %r15,%rsi\nxor %edi,%edi\ncvtsd2ss %xmm0,%xmm0\nmovss %xmm0,(%r12,%rbx,4)\ncallq 1120 \nmov %rax,%rbp\ntest %rax,%rax\njne 1438 \nadd $0x8,%rsp\nmov %r13d,%edx\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\nlea r13, delim; \", \"\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nmov edi, 28h ; '('; size\ncall _malloc\nmov rdi, rbx; s\nmov r12, rax\ncall _strdup\nmov rsi, r13; delim\nmov rdi, rax; s\ncall _strtok\ntest rax, rax\njz short loc_1460\nmov rbx, rax\nxor ebp, ebp\nmov r14d, 0Ah\njmp short loc_142D\nloc_1400:\nmov rdi, rbx; nptr\nxor esi, esi; endptr\ncall _strtod\nmov rsi, r13; delim\nxor edi, edi; s\ncvtsd2ss xmm0, xmm0\nmovss dword ptr [r12+rbp*4], xmm0\ncall _strtok\nmov rbx, rax\nlea rax, [rbp+1]\ntest rbx, rbx\njz short loc_1450\nmov rbp, rax\nloc_142D:\ncmp r14d, ebp\njg short loc_1400\nadd r14d, r14d\nmov rdi, r12; ptr\nmovsxd rsi, r14d\nshl rsi, 2; size\ncall _realloc\nmov r12, rax\njmp short loc_1400\nloc_1450:\npop rbx\nlea edx, [rbp+1]\nmov rax, r12\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1460:\npop rbx\nmov rax, r12\npop rbp\nxor edx, edx\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "void *__fastcall func0(char *s)\n{\n void *v1; // r12\n char *v2; // rax\n char *v3; // rax\n char *v4; // rbx\n __int64 v5; // rbp\n int v6; // r14d\n float v7; // xmm0_4\n\n v1 = malloc(0x28uLL);\n v2 = strdup(s);\n v3 = strtok(v2, \", \");\n if ( !v3 )\n return v1;\n v4 = v3;\n v5 = 0LL;\n v6 = 10;\n while ( 1 )\n {\n if ( v6 <= (int)v5 )\n {\n v6 *= 2;\n v1 = realloc(v1, 4LL * v6);\n }\n v7 = strtod(v4, 0LL);\n *((float *)v1 + v5) = v7;\n v4 = strtok(0LL, \", \");\n if ( !v4 )\n break;\n ++v5;\n }\n return v1;\n}", + "ida_strip_asm": "sub_13B0:\nendbr64\npush r14\npush r13\nlea r13, delim; \", \"\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nmov edi, 28h ; '('; size\ncall _malloc\nmov rdi, rbx; s\nmov r12, rax\ncall _strdup\nmov rsi, r13; delim\nmov rdi, rax; s\ncall _strtok\ntest rax, rax\njz short loc_1460\nmov rbx, rax\nxor ebp, ebp\nmov r14d, 0Ah\njmp short loc_142D\nloc_1400:\nmov rdi, rbx; nptr\nxor esi, esi; endptr\ncall _strtod\nmov rsi, r13; delim\nxor edi, edi; s\ncvtsd2ss xmm0, xmm0\nmovss dword ptr [r12+rbp*4], xmm0\ncall _strtok\nmov rbx, rax\nlea rax, [rbp+1]\ntest rbx, rbx\njz short loc_1450\nmov rbp, rax\nloc_142D:\ncmp r14d, ebp\njg short loc_1400\nadd r14d, r14d\nmov rdi, r12; ptr\nmovsxd rsi, r14d\nshl rsi, 2; size\ncall _realloc\nmov r12, rax\njmp short loc_1400\nloc_1450:\npop rbx\nlea edx, [rbp+1]\nmov rax, r12\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1460:\npop rbx\nmov rax, r12\npop rbp\nxor edx, edx\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "void *__fastcall sub_13B0(char *s)\n{\n void *v1; // r12\n char *v2; // rax\n char *v3; // rax\n char *v4; // rbx\n __int64 v5; // rbp\n int v6; // r14d\n float v7; // xmm0_4\n\n v1 = malloc(0x28uLL);\n v2 = strdup(s);\n v3 = strtok(v2, \", \");\n if ( !v3 )\n return v1;\n v4 = v3;\n v5 = 0LL;\n v6 = 10;\n while ( 1 )\n {\n if ( v6 <= (int)v5 )\n {\n v6 *= 2;\n v1 = realloc(v1, 4LL * v6);\n }\n v7 = strtod(v4, 0LL);\n *((float *)v1 + v5) = v7;\n v4 = strtok(0LL, \", \");\n if ( !v4 )\n break;\n ++v5;\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_13B0(char *s) {\n void *v1;\n char *v2;\n char *v3;\n char *v4;\n long long v5;\n int v6;\n float v7;\n v1 = malloc(40uLL);\n v2 = strdup(s);\n v3 = strtok(v2, \", \");\n if (!v3) return v1;\n v4 = v3;\n v5 = 0LL;\n v6 = 10;\n while (1) {\n if (v6 <= (int)v5) {\n v6 *= 2;\n v1 = realloc(v1, 4LL * v6);\n }\n v7 = strtod(v4, 0LL);\n *((float *)v1 + v5) = v7;\n v4 = strtok(0LL, \", \");\n if (!v4) break;\n ++v5;\n }\n return v1;\n}", + "ida_pseudo_norm": "void *func0(char *s) {\n void *v1;\n char *v2;\n char *v3;\n char *v4;\n long long v5;\n int v6;\n float v7;\n v1 = malloc(40uLL);\n v2 = strdup(s);\n v3 = strtok(v2, \", \");\n if (!v3) return v1;\n v4 = v3;\n v5 = 0LL;\n v6 = 10;\n while (1) {\n if (v6 <= (int)v5) {\n v6 *= 2;\n v1 = realloc(v1, 4LL * v6);\n }\n v7 = strtod(v4, 0LL);\n *((float *)v1 + v5) = v7;\n v4 = strtok(0LL, \", \");\n if (!v4) break;\n ++v5;\n }\n return v1;\n}" + }, + { + "index": 894, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n float *elements;\n\n int size;\n\n} FloatTuple;\n\n\n\n", + "func": "FloatTuple func0(const char *test_str) {\n FloatTuple res;\n int estimate_size = 10;\n res.elements = malloc(estimate_size * sizeof(float));\n res.size = 0;\n char *token = strtok(strdup(test_str), \", \");\n while (token != NULL) {\n if (res.size >= estimate_size) {\n estimate_size *= 2;\n res.elements = realloc(res.elements, estimate_size * sizeof(float));\n }\n res.elements[res.size++] = atof(token);\n token = strtok(NULL, \", \");\n }\n return res;\n}", + "test": "int main() {\n\n FloatTuple result1 = func0(\"1.2, 1.3, 2.3, 2.4, 6.5\");\n\n FloatTuple expected1 = {.elements = (float[]){1.2, 1.3, 2.3, 2.4, 6.5}, .size = 5};\n\n assert(result1.size == expected1.size && memcmp(result1.elements, expected1.elements, result1.size * sizeof(float)) == 0);\n\n\n\n FloatTuple result2 = func0(\"2.3, 2.4, 5.6, 5.4, 8.9\");\n\n FloatTuple expected2 = {.elements = (float[]){2.3, 2.4, 5.6, 5.4, 8.9}, .size = 5};\n\n assert(result2.size == expected2.size && memcmp(result2.elements, expected2.elements, result2.size * sizeof(float)) == 0);\n\n\n\n FloatTuple result3 = func0(\"0.3, 0.5, 7.8, 9.4\");\n\n FloatTuple expected3 = {.elements = (float[]){0.3, 0.5, 7.8, 9.4}, .size = 4};\n\n assert(result3.size == expected3.size && memcmp(result3.elements, expected3.elements, result3.size * sizeof(float)) == 0);\n\n\n\n free(result1.elements);\n\n free(result2.elements);\n\n free(result3.elements);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\nxor %r13d,%r13d\npush %r12\npush %rbp\nmov %rdi,%rbp\nmov $0x28,%edi\npush %rbx\nsub $0x8,%rsp\ncallq 1100 \nmov %rbp,%rdi\nmov %rax,%r12\ncallq 1130 \nlea 0xc20(%rip),%rsi\nmov %rax,%rdi\ncallq 1120 \ntest %rax,%rax\nje 1450 \nmov %rax,%rbp\nxor %ebx,%ebx\nmov $0xa,%r14d\nlea 0xc01(%rip),%r15\njmp 1426 \nnopl (%rax)\ncmp %r14d,%r13d\njl 1422 \nadd %r14d,%r14d\nmov %r12,%rdi\nmovslq %r14d,%rsi\nshl $0x2,%rsi\ncallq 1110 \nmov %rax,%r12\nadd $0x1,%rbx\nmov %rbp,%rdi\nxor %esi,%esi\nlea 0x1(%rbx),%r13d\ncallq 10d0 \nmov %r15,%rsi\nxor %edi,%edi\ncvtsd2ss %xmm0,%xmm0\nmovss %xmm0,(%r12,%rbx,4)\ncallq 1120 \nmov %rax,%rbp\ntest %rax,%rax\njne 1408 \nadd $0x8,%rsp\nmov %r13d,%edx\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\nlea r12, delim; \", \"\npush rbp\npush rbx\nmov rbx, rdi\nmov edi, 28h ; '('; size\ncall _malloc\nmov rdi, rbx; s\nmov rbp, rax\ncall _strdup\nmov rsi, r12; delim\nmov rdi, rax; s\ncall _strtok\ntest rax, rax\njz short loc_1460\nmov rbx, rax\nxor r14d, r14d\nmov r13d, 0Ah\njmp short loc_142E\nloc_1400:\nmov rdi, rbx; nptr\nxor esi, esi; endptr\ncall _strtod\nmov rsi, r12; delim\nxor edi, edi; s\ncvtsd2ss xmm0, xmm0\nmovss dword ptr [rbp+r14*4+0], xmm0\ncall _strtok\nmov rbx, rax\nlea rax, [r14+1]\ntest rbx, rbx\njz short loc_1450\nmov r14, rax\nloc_142E:\ncmp r13d, r14d\njg short loc_1400\nadd r13d, r13d\nmov rdi, rbp; ptr\nmovsxd rsi, r13d\nshl rsi, 2; size\ncall _realloc\nmov rbp, rax\njmp short loc_1400\nloc_1450:\npop rbx\nlea edx, [r14+1]\nmov rax, rbp\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1460:\npop rbx\nmov rax, rbp\nxor edx, edx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "void *__fastcall func0(char *s)\n{\n void *v1; // rbp\n char *v2; // rax\n char *v3; // rax\n char *v4; // rbx\n __int64 v5; // r14\n int v6; // r13d\n float v7; // xmm0_4\n\n v1 = malloc(0x28uLL);\n v2 = strdup(s);\n v3 = strtok(v2, \", \");\n if ( !v3 )\n return v1;\n v4 = v3;\n v5 = 0LL;\n v6 = 10;\n while ( 1 )\n {\n if ( v6 <= (int)v5 )\n {\n v6 *= 2;\n v1 = realloc(v1, 4LL * v6);\n }\n v7 = strtod(v4, 0LL);\n *((float *)v1 + v5) = v7;\n v4 = strtok(0LL, \", \");\n if ( !v4 )\n break;\n ++v5;\n }\n return v1;\n}", + "ida_strip_asm": "sub_13B0:\nendbr64\npush r14\npush r13\npush r12\nlea r12, delim; \", \"\npush rbp\npush rbx\nmov rbx, rdi\nmov edi, 28h ; '('; size\ncall _malloc\nmov rdi, rbx; s\nmov rbp, rax\ncall _strdup\nmov rsi, r12; delim\nmov rdi, rax; s\ncall _strtok\ntest rax, rax\njz short loc_1460\nmov rbx, rax\nxor r14d, r14d\nmov r13d, 0Ah\njmp short loc_142E\nloc_1400:\nmov rdi, rbx; nptr\nxor esi, esi; endptr\ncall _strtod\nmov rsi, r12; delim\nxor edi, edi; s\ncvtsd2ss xmm0, xmm0\nmovss dword ptr [rbp+r14*4+0], xmm0\ncall _strtok\nmov rbx, rax\nlea rax, [r14+1]\ntest rbx, rbx\njz short loc_1450\nmov r14, rax\nloc_142E:\ncmp r13d, r14d\njg short loc_1400\nadd r13d, r13d\nmov rdi, rbp; ptr\nmovsxd rsi, r13d\nshl rsi, 2; size\ncall _realloc\nmov rbp, rax\njmp short loc_1400\nloc_1450:\npop rbx\nlea edx, [r14+1]\nmov rax, rbp\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1460:\npop rbx\nmov rax, rbp\nxor edx, edx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "void *__fastcall sub_13B0(char *s)\n{\n void *v1; // rbp\n char *v2; // rax\n char *v3; // rax\n char *v4; // rbx\n __int64 v5; // r14\n int v6; // r13d\n float v7; // xmm0_4\n\n v1 = malloc(0x28uLL);\n v2 = strdup(s);\n v3 = strtok(v2, \", \");\n if ( !v3 )\n return v1;\n v4 = v3;\n v5 = 0LL;\n v6 = 10;\n while ( 1 )\n {\n if ( v6 <= (int)v5 )\n {\n v6 *= 2;\n v1 = realloc(v1, 4LL * v6);\n }\n v7 = strtod(v4, 0LL);\n *((float *)v1 + v5) = v7;\n v4 = strtok(0LL, \", \");\n if ( !v4 )\n break;\n ++v5;\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_13B0(char *s) {\n void *v1;\n char *v2;\n char *v3;\n char *v4;\n long long v5;\n int v6;\n float v7;\n v1 = malloc(40uLL);\n v2 = strdup(s);\n v3 = strtok(v2, \", \");\n if (!v3) return v1;\n v4 = v3;\n v5 = 0LL;\n v6 = 10;\n while (1) {\n if (v6 <= (int)v5) {\n v6 *= 2;\n v1 = realloc(v1, 4LL * v6);\n }\n v7 = strtod(v4, 0LL);\n *((float *)v1 + v5) = v7;\n v4 = strtok(0LL, \", \");\n if (!v4) break;\n ++v5;\n }\n return v1;\n}", + "ida_pseudo_norm": "void *func0(char *s) {\n void *v1;\n char *v2;\n char *v3;\n char *v4;\n long long v5;\n int v6;\n float v7;\n v1 = malloc(40uLL);\n v2 = strdup(s);\n v3 = strtok(v2, \", \");\n if (!v3) return v1;\n v4 = v3;\n v5 = 0LL;\n v6 = 10;\n while (1) {\n if (v6 <= (int)v5) {\n v6 *= 2;\n v1 = realloc(v1, 4LL * v6);\n }\n v7 = strtod(v4, 0LL);\n *((float *)v1 + v5) = v7;\n v4 = strtok(0LL, \", \");\n if (!v4) break;\n ++v5;\n }\n return v1;\n}" + }, + { + "index": 895, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int A[], int n) {\n if (n == 1) {\n return A[0];\n }\n int look_up[n];\n look_up[0] = A[0];\n look_up[1] = A[0] > A[1] ? A[0] : A[1];\n for (int i = 2; i < n; i++) {\n int option1 = look_up[i - 1];\n int option2 = look_up[i - 2] + A[i];\n int option3 = A[i];\n look_up[i] = option1 > option2 ? option1 : option2;\n look_up[i] = look_up[i] > option3 ? look_up[i] : option3;\n }\n return look_up[n - 1];\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 9, 4, 5, 0, 4, 11, 6};\n\n int arr2[] = {1, 2, 9, 5, 6, 0, 5, 12, 7};\n\n int arr3[] = {1, 3, 10, 5, 6, 0, 6, 14, 21};\n\n\n\n assert(func0(arr1, 9) == 26);\n\n assert(func0(arr2, 9) == 28);\n\n assert(func0(arr3, 9) == 44);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x48,%rsp\nmov %rdi,-0x48(%rbp)\nmov %esi,-0x4c(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmov %rsp,%rax\nmov %rax,%rsi\ncmpl $0x1,-0x4c(%rbp)\njne 11a3 \nmov -0x48(%rbp),%rax\nmov (%rax),%eax\njmpq 133d \nmov -0x4c(%rbp),%eax\nmovslq %eax,%rdx\nsub $0x1,%rdx\nmov %rdx,-0x28(%rbp)\nmovslq %eax,%rdx\nmov %rdx,%r8\nmov $0x0,%r9d\nmovslq %eax,%rdx\nmov %rdx,%rcx\nmov $0x0,%ebx\ncltq\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%edi\nmov $0x0,%edx\ndiv %rdi\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rbx\nsub %rdx,%rbx\nmov %rbx,%rdx\ncmp %rdx,%rsp\nje 1219 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 1202 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 1243 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x20(%rbp)\nmov -0x48(%rbp),%rax\nmov (%rax),%edx\nmov -0x20(%rbp),%rax\nmov %edx,(%rax)\nmov -0x48(%rbp),%rax\nadd $0x4,%rax\nmov (%rax),%edx\nmov -0x48(%rbp),%rax\nmov (%rax),%eax\ncmp %eax,%edx\ncmovl %eax,%edx\nmov -0x20(%rbp),%rax\nmov %edx,0x4(%rax)\nmovl $0x2,-0x38(%rbp)\njmpq 1321 \nmov -0x38(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x20(%rbp),%rax\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nmov %eax,-0x34(%rbp)\nmov -0x38(%rbp),%eax\nlea -0x2(%rax),%edx\nmov -0x20(%rbp),%rax\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%edx\nmov -0x38(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x48(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\nadd %edx,%eax\nmov %eax,-0x30(%rbp)\nmov -0x38(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x2c(%rbp)\nmov -0x34(%rbp),%eax\ncmp %eax,-0x30(%rbp)\ncmovge -0x30(%rbp),%eax\nmov %eax,%ecx\nmov -0x20(%rbp),%rax\nmov -0x38(%rbp),%edx\nmovslq %edx,%rdx\nmov %ecx,(%rax,%rdx,4)\nmov -0x20(%rbp),%rax\nmov -0x38(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\ncmp %eax,-0x2c(%rbp)\ncmovge -0x2c(%rbp),%eax\nmov %eax,%ecx\nmov -0x20(%rbp),%rax\nmov -0x38(%rbp),%edx\nmovslq %edx,%rdx\nmov %ecx,(%rax,%rdx,4)\naddl $0x1,-0x38(%rbp)\nmov -0x38(%rbp),%eax\ncmp -0x4c(%rbp),%eax\njl 128a \nmov -0x4c(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x20(%rbp),%rax\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nmov %rsi,%rsp\nmov -0x18(%rbp),%rdi\nxor %fs:0x28,%rdi\nje 1354 \ncallq 1060 <__stack_chk_fail@plt>\nmov -0x8(%rbp),%rbx\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\ncmp [rbp+var_3C], 1\njnz short loc_11A2\nmov rax, [rbp+var_38]\nmov eax, [rax]\njmp loc_1324\nloc_11A2:\nmov eax, [rbp+var_3C]\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11E7:\ncmp rsp, rdx\njz short loc_11FE\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_11E7\nloc_11FE:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1228\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1228:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov rax, [rbp+var_38]\nmov edx, [rax]\nmov rax, [rbp+var_10]\nmov [rax], edx\nmov rax, [rbp+var_38]\nadd rax, 4\nmov edx, [rax]\nmov rax, [rbp+var_38]\nmov eax, [rax]\ncmp edx, eax\ncmovl edx, eax\nmov rax, [rbp+var_10]\nmov [rax+4], edx\nmov [rbp+var_28], 2\njmp loc_1308\nloc_126F:\nmov eax, [rbp+var_28]\nlea edx, [rax-1]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov [rbp+var_24], eax\nmov eax, [rbp+var_28]\nlea edx, [rax-2]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov edx, [rax+rdx*4]\nmov eax, [rbp+var_28]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov eax, [rax]\nadd eax, edx\nmov [rbp+var_20], eax\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_1C], eax\nmov edx, [rbp+var_20]\nmov eax, [rbp+var_24]\ncmp edx, eax\ncmovge eax, edx\nmov ecx, eax\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nmov edx, [rax+rdx*4]\nmov eax, [rbp+var_1C]\ncmp edx, eax\ncmovge eax, edx\nmov ecx, eax\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nadd [rbp+var_28], 1\nloc_1308:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_3C]\njl loc_126F\nmov eax, [rbp+var_3C]\nlea edx, [rax-1]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nloc_1324:\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_133B\ncall ___stack_chk_fail\nlocret_133B:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n unsigned __int64 v3; // rax\n void *v4; // rsp\n signed int v5; // edx\n int v6; // eax\n signed int v7; // eax\n signed int v8; // [rsp+8h] [rbp-40h] BYREF\n int v9; // [rsp+Ch] [rbp-3Ch]\n signed int *v10; // [rsp+10h] [rbp-38h]\n int i; // [rsp+20h] [rbp-28h]\n int v12; // [rsp+24h] [rbp-24h]\n int v13; // [rsp+28h] [rbp-20h]\n signed int v14; // [rsp+2Ch] [rbp-1Ch]\n __int64 v15; // [rsp+30h] [rbp-18h]\n signed int *v16; // [rsp+38h] [rbp-10h]\n unsigned __int64 v17; // [rsp+40h] [rbp-8h]\n\n v10 = (signed int *)a1;\n v9 = a2;\n v17 = __readfsqword(0x28u);\n if ( a2 == 1 )\n return (unsigned int)*v10;\n v15 = v9 - 1LL;\n v3 = 16 * ((4LL * v9 + 15) / 0x10uLL);\n while ( &v8 != (signed int *)((char *)&v8 - (v3 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v4 = alloca(v3 & 0xFFF);\n if ( (v3 & 0xFFF) != 0 )\n *(_QWORD *)((char *)&v8 + (v3 & 0xFFF) - 8) = *(_QWORD *)((char *)&v8 + (v3 & 0xFFF) - 8);\n v16 = &v8;\n v8 = *v10;\n v5 = v10[1];\n if ( v5 < *v10 )\n v5 = *v10;\n v16[1] = v5;\n for ( i = 2; i < v9; ++i )\n {\n v12 = v16[i - 1];\n v13 = v16[i - 2] + v10[i];\n v14 = v10[i];\n v6 = v12;\n if ( v13 >= v12 )\n v6 = v13;\n v16[i] = v6;\n v7 = v14;\n if ( v16[i] >= v14 )\n v7 = v16[i];\n v16[i] = v7;\n }\n return (unsigned int)v16[v9 - 1];\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\ncmp [rbp+var_3C], 1\njnz short loc_11A2\nmov rax, [rbp+var_38]\nmov eax, [rax]\njmp loc_1324\nloc_11A2:\nmov eax, [rbp+var_3C]\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11E7:\ncmp rsp, rdx\njz short loc_11FE\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_11E7\nloc_11FE:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1228\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1228:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov rax, [rbp+var_38]\nmov edx, [rax]\nmov rax, [rbp+var_10]\nmov [rax], edx\nmov rax, [rbp+var_38]\nadd rax, 4\nmov edx, [rax]\nmov rax, [rbp+var_38]\nmov eax, [rax]\ncmp edx, eax\ncmovl edx, eax\nmov rax, [rbp+var_10]\nmov [rax+4], edx\nmov [rbp+var_28], 2\njmp loc_1308\nloc_126F:\nmov eax, [rbp+var_28]\nlea edx, [rax-1]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov [rbp+var_24], eax\nmov eax, [rbp+var_28]\nlea edx, [rax-2]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov edx, [rax+rdx*4]\nmov eax, [rbp+var_28]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov eax, [rax]\nadd eax, edx\nmov [rbp+var_20], eax\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_1C], eax\nmov edx, [rbp+var_20]\nmov eax, [rbp+var_24]\ncmp edx, eax\ncmovge eax, edx\nmov ecx, eax\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nmov edx, [rax+rdx*4]\nmov eax, [rbp+var_1C]\ncmp edx, eax\ncmovge eax, edx\nmov ecx, eax\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nadd [rbp+var_28], 1\nloc_1308:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_3C]\njl loc_126F\nmov eax, [rbp+var_3C]\nlea edx, [rax-1]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nloc_1324:\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_133B\ncall ___stack_chk_fail\nlocret_133B:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(unsigned int *a1, int a2)\n{\n unsigned __int64 v3; // rax\n void *v4; // rsp\n signed int v5; // edx\n int v6; // eax\n signed int v7; // eax\n signed int v8; // [rsp+8h] [rbp-40h] BYREF\n int v9; // [rsp+Ch] [rbp-3Ch]\n signed int *v10; // [rsp+10h] [rbp-38h]\n int i; // [rsp+20h] [rbp-28h]\n int v12; // [rsp+24h] [rbp-24h]\n int v13; // [rsp+28h] [rbp-20h]\n signed int v14; // [rsp+2Ch] [rbp-1Ch]\n __int64 v15; // [rsp+30h] [rbp-18h]\n signed int *v16; // [rsp+38h] [rbp-10h]\n unsigned __int64 v17; // [rsp+40h] [rbp-8h]\n\n v10 = (signed int *)a1;\n v9 = a2;\n v17 = __readfsqword(0x28u);\n if ( a2 == 1 )\n return (unsigned int)*v10;\n v15 = v9 - 1LL;\n v3 = 16 * ((4LL * v9 + 15) / 0x10uLL);\n while ( &v8 != (signed int *)((char *)&v8 - (v3 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v4 = alloca(v3 & 0xFFF);\n if ( (v3 & 0xFFF) != 0 )\n *(_QWORD *)((char *)&v8 + (v3 & 0xFFF) - 8) = *(_QWORD *)((char *)&v8 + (v3 & 0xFFF) - 8);\n v16 = &v8;\n v8 = *v10;\n v5 = v10[1];\n if ( v5 < *v10 )\n v5 = *v10;\n v16[1] = v5;\n for ( i = 2; i < v9; ++i )\n {\n v12 = v16[i - 1];\n v13 = v16[i - 2] + v10[i];\n v14 = v10[i];\n v6 = v12;\n if ( v13 >= v12 )\n v6 = v13;\n v16[i] = v6;\n v7 = v14;\n if ( v16[i] >= v14 )\n v7 = v16[i];\n v16[i] = v7;\n }\n return (unsigned int)v16[v9 - 1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(unsigned int *a1, int a2) {\n unsigned long long v3;\n void *v4;\n signed int v5;\n int v6;\n signed int v7;\n signed int v8;\n int v9;\n signed int *v10;\n int i;\n int v12;\n int v13;\n signed int v14;\n long long v15;\n signed int *v16;\n unsigned long long v17;\n v10 = (signed int *)a1;\n v9 = a2;\n v17 = __readfsqword(40u);\n if (a2 == 1) return (unsigned int)*v10;\n v15 = v9 - 1LL;\n v3 = 16 * ((4LL * v9 + 15) / 16uLL);\n while (&v8 != (signed int *)((char *)&v8 - (v3 & 18446744073709547520LL)))\n ;\n v4 = alloca(v3 & 4095);\n if ((v3 & 4095) != 0)\n *(uint64_t *)((char *)&v8 + (v3 & 4095) - 8) =\n *(uint64_t *)((char *)&v8 + (v3 & 4095) - 8);\n v16 = &v8;\n v8 = *v10;\n v5 = v10[1];\n if (v5 < *v10) v5 = *v10;\n v16[1] = v5;\n for (i = 2; i < v9; ++i) {\n v12 = v16[i - 1];\n v13 = v16[i - 2] + v10[i];\n v14 = v10[i];\n v6 = v12;\n if (v13 >= v12) v6 = v13;\n v16[i] = v6;\n v7 = v14;\n if (v16[i] >= v14) v7 = v16[i];\n v16[i] = v7;\n }\n return (unsigned int)v16[v9 - 1];\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n unsigned long long v3;\n void *v4;\n signed int v5;\n int v6;\n signed int v7;\n signed int v8;\n int v9;\n signed int *v10;\n int i;\n int v12;\n int v13;\n signed int v14;\n long long v15;\n signed int *v16;\n unsigned long long v17;\n v10 = (signed int *)a1;\n v9 = a2;\n v17 = __readfsqword(40u);\n if (a2 == 1) return (unsigned int)*v10;\n v15 = v9 - 1LL;\n v3 = 16 * ((4LL * v9 + 15) / 16uLL);\n while (&v8 != (signed int *)((char *)&v8 - (v3 & 18446744073709547520LL)))\n ;\n v4 = alloca(v3 & 4095);\n if ((v3 & 4095) != 0)\n *(uint64_t *)((char *)&v8 + (v3 & 4095) - 8) =\n *(uint64_t *)((char *)&v8 + (v3 & 4095) - 8);\n v16 = &v8;\n v8 = *v10;\n v5 = v10[1];\n if (v5 < *v10) v5 = *v10;\n v16[1] = v5;\n for (i = 2; i < v9; ++i) {\n v12 = v16[i - 1];\n v13 = v16[i - 2] + v10[i];\n v14 = v10[i];\n v6 = v12;\n if (v13 >= v12) v6 = v13;\n v16[i] = v6;\n v7 = v14;\n if (v16[i] >= v14) v7 = v16[i];\n v16[i] = v7;\n }\n return (unsigned int)v16[v9 - 1];\n}" + }, + { + "index": 895, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int A[], int n) {\n if (n == 1) {\n return A[0];\n }\n int look_up[n];\n look_up[0] = A[0];\n look_up[1] = A[0] > A[1] ? A[0] : A[1];\n for (int i = 2; i < n; i++) {\n int option1 = look_up[i - 1];\n int option2 = look_up[i - 2] + A[i];\n int option3 = A[i];\n look_up[i] = option1 > option2 ? option1 : option2;\n look_up[i] = look_up[i] > option3 ? look_up[i] : option3;\n }\n return look_up[n - 1];\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 9, 4, 5, 0, 4, 11, 6};\n\n int arr2[] = {1, 2, 9, 5, 6, 0, 5, 12, 7};\n\n int arr3[] = {1, 3, 10, 5, 6, 0, 6, 14, 21};\n\n\n\n assert(func0(arr1, 9) == 26);\n\n assert(func0(arr2, 9) == 28);\n\n assert(func0(arr3, 9) == 44);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\ncmp $0x1,%esi\nje 11c1 \nmovslq %esi,%rax\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffffff0,%rdx\nand $0xfffffffffffff000,%rax\nmov %rsp,%rcx\nsub %rax,%rcx\nmov %rcx,%rax\ncmp %rax,%rsp\nje 11c8 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11aa \nmov (%rdi),%eax\njmpq 124b \nmov %rdx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 11de \norq $0x0,-0x8(%rsp,%rax,1)\nlea 0x3(%rsp),%r10\nmov %r10,%rdx\nshr $0x2,%rdx\nand $0xfffffffffffffffc,%r10\nmov %r10,%r8\nmov (%rdi),%eax\nmov %eax,0x0(,%rdx,4)\ncmp %eax,0x4(%rdi)\ncmovge 0x4(%rdi),%eax\nmov %eax,0x4(,%rdx,4)\ncmp $0x2,%esi\njle 1241 \nlea -0x3(%rsi),%r9d\nadd $0x3,%r9\nmov $0x2,%eax\nmov (%rdi,%rax,4),%edx\ncmp %edx,-0x4(%r8,%rax,4)\nmov %edx,%ecx\ncmovge -0x4(%r8,%rax,4),%ecx\nadd -0x8(%r8,%rax,4),%edx\ncmp %edx,%ecx\ncmovge %ecx,%edx\nmov %edx,(%r8,%rax,4)\nadd $0x1,%rax\ncmp %r9,%rax\njne 121a \nsub $0x1,%esi\nmovslq %esi,%rsi\nmov (%r10,%rsi,4),%eax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\njne 125c \nleaveq\nretq\ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\ncmp esi, 1\njz short loc_11C1\nmov r8d, esi\nmovsxd rax, esi\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11AA:\ncmp rsp, rdx\njz short loc_11C5\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11AA\nloc_11C1:\nmov eax, [rdi]\njmp short loc_123D\nloc_11C5:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11DB\nor [rsp+rax+10h+var_18], 0\nloc_11DB:\nlea rsi, [rsp+10h+var_D]\nmov rcx, rsi\nshr rcx, 2\nand rsi, 0FFFFFFFFFFFFFFFCh\nmov edx, [rdi]\nmov ds:dword_0[rcx*4], edx\nmov eax, [rdi+4]\ncmp eax, edx\ncmovl eax, edx\nmov dword ptr ds:byte_4[rcx*4], eax\ncmp r8d, 2\njle short loc_1232\nmov r9d, r8d\nmov edx, 2\nloc_1211:\nmov ecx, [rdi+rdx*4]\nmov eax, [rsi+rdx*4-4]\ncmp ecx, eax\ncmovge eax, ecx\nadd ecx, [rsi+rdx*4-8]\ncmp eax, ecx\ncmovl eax, ecx\nmov [rsi+rdx*4], eax\nadd rdx, 1\ncmp rdx, r9\njnz short loc_1211\nloc_1232:\nsub r8d, 1\nmovsxd r8, r8d\nmov eax, [rsi+r8*4]\nloc_123D:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_124E\nleave\nretn\nloc_124E:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n signed __int64 v3; // rax\n void *v4; // rsp\n signed int v5; // edx\n signed int v6; // eax\n __int64 i; // rdx\n signed int v8; // ecx\n signed int v9; // eax\n signed int v10; // ecx\n _DWORD v12[2]; // [rsp+8h] [rbp-10h] BYREF\n unsigned __int64 v13; // [rsp+10h] [rbp-8h]\n\n v13 = __readfsqword(0x28u);\n if ( a2 == 1 )\n return *a1;\n while ( v12 != (_DWORD *)((char *)v12 - ((4LL * a2 + 15) & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v3 = (4 * (_WORD)a2 + 15) & 0xFF0;\n v4 = alloca(v3);\n if ( ((4 * (_WORD)a2 + 15) & 0xFF0) != 0 )\n *(_QWORD *)((char *)&v12[-2] + v3) = *(_QWORD *)((char *)&v12[-2] + v3);\n v5 = *a1;\n v12[0] = v5;\n v6 = a1[1];\n if ( v6 < v5 )\n v6 = v5;\n v12[1] = v6;\n if ( a2 > 2 )\n {\n for ( i = 2LL; i != a2; v12[i++] = v9 )\n {\n v8 = a1[i];\n v9 = v12[i - 1];\n if ( v8 >= v9 )\n v9 = a1[i];\n v10 = v12[i - 2] + v8;\n if ( v9 < v10 )\n v9 = v10;\n }\n }\n return (unsigned int)v12[a2 - 1];\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\ncmp esi, 1\njz short loc_11C1\nmov r8d, esi\nmovsxd rax, esi\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11AA:\ncmp rsp, rdx\njz short loc_11C5\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\njmp short loc_11AA\nloc_11C1:\nmov eax, [rdi]\njmp short loc_123D\nloc_11C5:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11DB\nor [rsp+rax+10h+var_18], 0\nloc_11DB:\nlea rsi, [rsp+10h+var_D]\nmov rcx, rsi\nshr rcx, 2\nand rsi, 0FFFFFFFFFFFFFFFCh\nmov edx, [rdi]\nmov ds:dword_0[rcx*4], edx\nmov eax, [rdi+4]\ncmp eax, edx\ncmovl eax, edx\nmov dword ptr ds:byte_4[rcx*4], eax\ncmp r8d, 2\njle short loc_1232\nmov r9d, r8d\nmov edx, 2\nloc_1211:\nmov ecx, [rdi+rdx*4]\nmov eax, [rsi+rdx*4-4]\ncmp ecx, eax\ncmovge eax, ecx\nadd ecx, [rsi+rdx*4-8]\ncmp eax, ecx\ncmovl eax, ecx\nmov [rsi+rdx*4], eax\nadd rdx, 1\ncmp rdx, r9\njnz short loc_1211\nloc_1232:\nsub r8d, 1\nmovsxd r8, r8d\nmov eax, [rsi+r8*4]\nloc_123D:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_124E\nleave\nretn\nloc_124E:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(unsigned int *a1, int a2)\n{\n signed __int64 v3; // rax\n void *v4; // rsp\n signed int v5; // edx\n signed int v6; // eax\n __int64 i; // rdx\n signed int v8; // ecx\n signed int v9; // eax\n signed int v10; // ecx\n _DWORD v12[2]; // [rsp+8h] [rbp-10h] BYREF\n unsigned __int64 v13; // [rsp+10h] [rbp-8h]\n\n v13 = __readfsqword(0x28u);\n if ( a2 == 1 )\n return *a1;\n while ( v12 != (_DWORD *)((char *)v12 - ((4LL * a2 + 15) & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v3 = (4 * (_WORD)a2 + 15) & 0xFF0;\n v4 = alloca(v3);\n if ( ((4 * (_WORD)a2 + 15) & 0xFF0) != 0 )\n *(_QWORD *)((char *)&v12[-2] + v3) = *(_QWORD *)((char *)&v12[-2] + v3);\n v5 = *a1;\n v12[0] = v5;\n v6 = a1[1];\n if ( v6 < v5 )\n v6 = v5;\n v12[1] = v6;\n if ( a2 > 2 )\n {\n for ( i = 2LL; i != a2; v12[i++] = v9 )\n {\n v8 = a1[i];\n v9 = v12[i - 1];\n if ( v8 >= v9 )\n v9 = a1[i];\n v10 = v12[i - 2] + v8;\n if ( v9 < v10 )\n v9 = v10;\n }\n }\n return (unsigned int)v12[a2 - 1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(unsigned int *a1, int a2) {\n signed long long v3;\n void *v4;\n signed int v5;\n signed int v6;\n long long i;\n signed int v8;\n signed int v9;\n signed int v10;\n uint32_t v12[2];\n unsigned long long v13;\n v13 = __readfsqword(40u);\n if (a2 == 1) return *a1;\n while (v12 !=\n (uint32_t *)((char *)v12 - ((4LL * a2 + 15) & 18446744073709547520LL)))\n ;\n v3 = (4 * (unsigned short)a2 + 15) & 4080;\n v4 = alloca(v3);\n if (((4 * (unsigned short)a2 + 15) & 4080) != 0)\n *(uint64_t *)((char *)&v12[-2] + v3) = *(uint64_t *)((char *)&v12[-2] + v3);\n v5 = *a1;\n v12[0] = v5;\n v6 = a1[1];\n if (v6 < v5) v6 = v5;\n v12[1] = v6;\n if (a2 > 2) {\n for (i = 2LL; i != a2; v12[i++] = v9) {\n v8 = a1[i];\n v9 = v12[i - 1];\n if (v8 >= v9) v9 = a1[i];\n v10 = v12[i - 2] + v8;\n if (v9 < v10) v9 = v10;\n }\n }\n return (unsigned int)v12[a2 - 1];\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n signed long long v3;\n void *v4;\n signed int v5;\n signed int v6;\n long long i;\n signed int v8;\n signed int v9;\n signed int v10;\n uint32_t v12[2];\n unsigned long long v13;\n v13 = __readfsqword(40u);\n if (a2 == 1) return *a1;\n while (v12 !=\n (uint32_t *)((char *)v12 - ((4LL * a2 + 15) & 18446744073709547520LL)))\n ;\n v3 = (4 * (unsigned short)a2 + 15) & 4080;\n v4 = alloca(v3);\n if (((4 * (unsigned short)a2 + 15) & 4080) != 0)\n *(uint64_t *)((char *)&v12[-2] + v3) = *(uint64_t *)((char *)&v12[-2] + v3);\n v5 = *a1;\n v12[0] = v5;\n v6 = a1[1];\n if (v6 < v5) v6 = v5;\n v12[1] = v6;\n if (a2 > 2) {\n for (i = 2LL; i != a2; v12[i++] = v9) {\n v8 = a1[i];\n v9 = v12[i - 1];\n if (v8 >= v9) v9 = a1[i];\n v10 = v12[i - 2] + v8;\n if (v9 < v10) v9 = v10;\n }\n }\n return (unsigned int)v12[a2 - 1];\n}" + }, + { + "index": 895, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int A[], int n) {\n if (n == 1) {\n return A[0];\n }\n int look_up[n];\n look_up[0] = A[0];\n look_up[1] = A[0] > A[1] ? A[0] : A[1];\n for (int i = 2; i < n; i++) {\n int option1 = look_up[i - 1];\n int option2 = look_up[i - 2] + A[i];\n int option3 = A[i];\n look_up[i] = option1 > option2 ? option1 : option2;\n look_up[i] = look_up[i] > option3 ? look_up[i] : option3;\n }\n return look_up[n - 1];\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 9, 4, 5, 0, 4, 11, 6};\n\n int arr2[] = {1, 2, 9, 5, 6, 0, 5, 12, 7};\n\n int arr3[] = {1, 3, 10, 5, 6, 0, 6, 14, 21};\n\n\n\n assert(func0(arr1, 9) == 26);\n\n assert(func0(arr2, 9) == 28);\n\n assert(func0(arr3, 9) == 44);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\ncmp $0x1,%esi\nje 13f8 \nmovslq %esi,%rax\nmov %rsp,%rcx\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rcx\nand $0xfffffffffffffff0,%rdx\nmov %rcx,%rax\ncmp %rax,%rsp\nje 135f \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 134a \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 1400 \nmov (%rdi),%eax\nlea 0x3(%rsp),%r9\nmov %r9,%rdx\nand $0xfffffffffffffffc,%r9\nshr $0x2,%rdx\nmov %eax,%ecx\ncmp %eax,0x4(%rdi)\ncmovge 0x4(%rdi),%ecx\nmov %eax,0x0(,%rdx,4)\nmov %ecx,0x4(,%rdx,4)\ncmp $0x2,%esi\njle 13d7 \nlea -0x3(%rsi),%r10d\nxor %edx,%edx\nshl $0x2,%r10\njmp 13b9 \nnopl 0x0(%rax,%rax,1)\nmov 0x4(%r9,%rdx,1),%eax\nadd $0x4,%rdx\nmov 0x8(%rdi,%rdx,1),%r8d\nadd %r8d,%eax\ncmp %r8d,%eax\ncmovl %r8d,%eax\ncmp %eax,%ecx\ncmovl %eax,%ecx\nmov %ecx,0x8(%r9,%rdx,1)\ncmp %r10,%rdx\njne 13b0 \nsub $0x1,%esi\nmovslq %esi,%rsi\nmov (%r9,%rsi,4),%eax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\njne 140b \nleaveq\nretq\nnopw 0x0(%rax,%rax,1)\nmov (%rdi),%eax\njmp 13e1 \nnopl 0x0(%rax)\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 1371 \ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov r8, rdi\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\ncmp esi, 1\njz loc_13A8\nmovsxd rax, esi\nmov rcx, rsp\nmov r9d, esi\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_1312\nloc_12FD:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rcx\njnz short loc_12FD\nloc_1312:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_13B0\nloc_1324:\nmov edi, [r8]\nmov eax, [r8+4]\nlea r10, [rsp+1010h+var_100D]\nmov rdx, r10\nand r10, 0FFFFFFFFFFFFFFFCh\nshr rdx, 2\ncmp edi, eax\nmovd xmm0, edi\ncmovge eax, edi\nmovd xmm1, eax\npunpckldq xmm0, xmm1\nmovq qword ptr ds:dword_0[rdx*4], xmm0\ncmp r9d, 2\njle short loc_1388\nmov r11d, r9d\nmov edx, 2\nnop dword ptr [rax+rax+00h]\nloc_1368:\nmov ecx, [r8+rdx*4]\ncmp ecx, eax\nlea esi, [rcx+rdi]\nmov edi, eax\ncmovge eax, ecx\ncmp eax, esi\ncmovl eax, esi\nmov [r10+rdx*4], eax\nadd rdx, 1\ncmp r11, rdx\njnz short loc_1368\nloc_1388:\nsub r9d, 1\nmovsxd r9, r9d\nmov eax, [r10+r9*4]\nloc_1393:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_13BB\nleave\nretn\nloc_13A8:\nmov eax, [rdi]\njmp short loc_1393\nloc_13B0:\nor [rsp+rdx+1010h+var_1018], 0\njmp loc_1324\nloc_13BB:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(signed int *a1, int a2)\n{\n __int64 v4; // rdx\n _QWORD *v5; // rcx\n __int16 v6; // dx\n signed __int64 v7; // rdx\n void *v8; // rsp\n signed int v9; // edi\n signed int v10; // eax\n __m128i v11; // xmm0\n __int64 i; // rdx\n signed int v13; // ecx\n signed int v14; // esi\n _QWORD v17[511]; // [rsp+8h] [rbp-1010h] BYREF\n _QWORD v18[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v18[1] = __readfsqword(0x28u);\n if ( a2 == 1 )\n return (unsigned int)*a1;\n v4 = 4LL * a2 + 15;\n v5 = (_QWORD *)((char *)v18 - (v4 & 0xFFFFFFFFFFFFF000LL));\n v6 = v4 & 0xFFF0;\n if ( v18 != v5 )\n {\n while ( v17 != v5 )\n ;\n }\n v7 = v6 & 0xFFF;\n v8 = alloca(v7);\n if ( v7 )\n *(_QWORD *)((char *)&v17[-1] + v7) = *(_QWORD *)((char *)&v17[-1] + v7);\n v9 = *a1;\n v10 = a1[1];\n v11 = _mm_cvtsi32_si128(v9);\n if ( v9 >= v10 )\n v10 = v9;\n v17[0] = _mm_unpacklo_epi32(v11, _mm_cvtsi32_si128(v10)).m128i_u64[0];\n if ( a2 > 2 )\n {\n for ( i = 2LL; i != a2; *((_DWORD *)v17 + i++) = v10 )\n {\n v13 = a1[i];\n v14 = v13 + v9;\n v9 = v10;\n if ( v13 >= v10 )\n v10 = a1[i];\n if ( v10 < v14 )\n v10 = v14;\n }\n }\n return *((unsigned int *)v17 + a2 - 1);\n}", + "ida_strip_asm": "sub_12B0:\nendbr64\npush rbp\nmov r8, rdi\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\ncmp esi, 1\njz loc_13A8\nmovsxd rax, esi\nmov rcx, rsp\nmov r9d, esi\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_1312\nloc_12FD:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rcx\njnz short loc_12FD\nloc_1312:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_13B0\nloc_1324:\nmov edi, [r8]\nmov eax, [r8+4]\nlea r10, [rsp+1010h+var_100D]\nmov rdx, r10\nand r10, 0FFFFFFFFFFFFFFFCh\nshr rdx, 2\ncmp edi, eax\nmovd xmm0, edi\ncmovge eax, edi\nmovd xmm1, eax\npunpckldq xmm0, xmm1\nmovq qword ptr ds:dword_0[rdx*4], xmm0\ncmp r9d, 2\njle short loc_1388\nmov r11d, r9d\nmov edx, 2\nnop dword ptr [rax+rax+00h]\nloc_1368:\nmov ecx, [r8+rdx*4]\ncmp ecx, eax\nlea esi, [rcx+rdi]\nmov edi, eax\ncmovge eax, ecx\ncmp eax, esi\ncmovl eax, esi\nmov [r10+rdx*4], eax\nadd rdx, 1\ncmp r11, rdx\njnz short loc_1368\nloc_1388:\nsub r9d, 1\nmovsxd r9, r9d\nmov eax, [r10+r9*4]\nloc_1393:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_13BB\nleave\nretn\nloc_13A8:\nmov eax, [rdi]\njmp short loc_1393\nloc_13B0:\nor [rsp+rdx+1010h+var_1018], 0\njmp loc_1324\nloc_13BB:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12B0(signed int *a1, int a2)\n{\n __int64 v4; // rdx\n _QWORD *v5; // rcx\n __int16 v6; // dx\n signed __int64 v7; // rdx\n void *v8; // rsp\n signed int v9; // edi\n signed int v10; // eax\n __m128i v11; // xmm0\n __int64 i; // rdx\n signed int v13; // ecx\n signed int v14; // esi\n _QWORD v17[511]; // [rsp+8h] [rbp-1010h] BYREF\n _QWORD v18[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v18[1] = __readfsqword(0x28u);\n if ( a2 == 1 )\n return (unsigned int)*a1;\n v4 = 4LL * a2 + 15;\n v5 = (_QWORD *)((char *)v18 - (v4 & 0xFFFFFFFFFFFFF000LL));\n v6 = v4 & 0xFFF0;\n if ( v18 != v5 )\n {\n while ( v17 != v5 )\n ;\n }\n v7 = v6 & 0xFFF;\n v8 = alloca(v7);\n if ( v7 )\n *(_QWORD *)((char *)&v17[-1] + v7) = *(_QWORD *)((char *)&v17[-1] + v7);\n v9 = *a1;\n v10 = a1[1];\n v11 = _mm_cvtsi32_si128(v9);\n if ( v9 >= v10 )\n v10 = v9;\n v17[0] = _mm_unpacklo_epi32(v11, _mm_cvtsi32_si128(v10)).m128i_u64[0];\n if ( a2 > 2 )\n {\n for ( i = 2LL; i != a2; *((_DWORD *)v17 + i++) = v10 )\n {\n v13 = a1[i];\n v14 = v13 + v9;\n v9 = v10;\n if ( v13 >= v10 )\n v10 = a1[i];\n if ( v10 < v14 )\n v10 = v14;\n }\n }\n return *((unsigned int *)v17 + a2 - 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12B0(signed int *a1, int a2) {\n long long v4;\n uint64_t *v5;\n short v6;\n signed long long v7;\n void *v8;\n signed int v9;\n signed int v10;\n __m128i v11;\n long long i;\n signed int v13;\n signed int v14;\n uint64_t v17[511];\n uint64_t v18[2];\n v18[1] = __readfsqword(40u);\n if (a2 == 1) return (unsigned int)*a1;\n v4 = 4LL * a2 + 15;\n v5 = (uint64_t *)((char *)v18 - (v4 & 18446744073709547520LL));\n v6 = v4 & 65520;\n if (v18 != v5) {\n while (v17 != v5)\n ;\n }\n v7 = v6 & 4095;\n v8 = alloca(v7);\n if (v7)\n *(uint64_t *)((char *)&v17[-1] + v7) = *(uint64_t *)((char *)&v17[-1] + v7);\n v9 = *a1;\n v10 = a1[1];\n v11 = _mm_cvtsi32_si128(v9);\n if (v9 >= v10) v10 = v9;\n v17[0] = _mm_unpacklo_epi32(v11, _mm_cvtsi32_si128(v10)).m128i_u64[0];\n if (a2 > 2) {\n for (i = 2LL; i != a2; *((uint32_t *)v17 + i++) = v10) {\n v13 = a1[i];\n v14 = v13 + v9;\n v9 = v10;\n if (v13 >= v10) v10 = a1[i];\n if (v10 < v14) v10 = v14;\n }\n }\n return *((unsigned int *)v17 + a2 - 1);\n}", + "ida_pseudo_norm": "long long func0(signed int *a1, int a2) {\n long long v4;\n uint64_t *v5;\n short v6;\n signed long long v7;\n void *v8;\n signed int v9;\n signed int v10;\n __m128i v11;\n long long i;\n signed int v13;\n signed int v14;\n uint64_t v17[511];\n uint64_t v18[2];\n v18[1] = __readfsqword(40u);\n if (a2 == 1) return (unsigned int)*a1;\n v4 = 4LL * a2 + 15;\n v5 = (uint64_t *)((char *)v18 - (v4 & 18446744073709547520LL));\n v6 = v4 & 65520;\n if (v18 != v5) {\n while (v17 != v5)\n ;\n }\n v7 = v6 & 4095;\n v8 = alloca(v7);\n if (v7)\n *(uint64_t *)((char *)&v17[-1] + v7) = *(uint64_t *)((char *)&v17[-1] + v7);\n v9 = *a1;\n v10 = a1[1];\n v11 = _mm_cvtsi32_si128(v9);\n if (v9 >= v10) v10 = v9;\n v17[0] = _mm_unpacklo_epi32(v11, _mm_cvtsi32_si128(v10)).m128i_u64[0];\n if (a2 > 2) {\n for (i = 2LL; i != a2; *((uint32_t *)v17 + i++) = v10) {\n v13 = a1[i];\n v14 = v13 + v9;\n v9 = v10;\n if (v13 >= v10) v10 = a1[i];\n if (v10 < v14) v10 = v14;\n }\n }\n return *((unsigned int *)v17 + a2 - 1);\n}" + }, + { + "index": 895, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int A[], int n) {\n if (n == 1) {\n return A[0];\n }\n int look_up[n];\n look_up[0] = A[0];\n look_up[1] = A[0] > A[1] ? A[0] : A[1];\n for (int i = 2; i < n; i++) {\n int option1 = look_up[i - 1];\n int option2 = look_up[i - 2] + A[i];\n int option3 = A[i];\n look_up[i] = option1 > option2 ? option1 : option2;\n look_up[i] = look_up[i] > option3 ? look_up[i] : option3;\n }\n return look_up[n - 1];\n}", + "test": "int main() {\n\n int arr1[] = {1, 2, 9, 4, 5, 0, 4, 11, 6};\n\n int arr2[] = {1, 2, 9, 5, 6, 0, 5, 12, 7};\n\n int arr3[] = {1, 3, 10, 5, 6, 0, 6, 14, 21};\n\n\n\n assert(func0(arr1, 9) == 26);\n\n assert(func0(arr2, 9) == 28);\n\n assert(func0(arr3, 9) == 44);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\ncmp $0x1,%esi\nje 13f8 \nmovslq %esi,%rax\nmov %rsp,%rcx\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rcx\nand $0xfffffffffffffff0,%rdx\nmov %rcx,%rax\ncmp %rax,%rsp\nje 130f \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 12fa \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 1400 \nmov (%rdi),%eax\nlea 0x3(%rsp),%r8\nmov %r8,%rcx\nand $0xfffffffffffffffc,%r8\nshr $0x2,%rcx\nmov %eax,%edx\ncmp %eax,0x4(%rdi)\ncmovge 0x4(%rdi),%edx\nmov %eax,0x0(,%rcx,4)\nmov %edx,0x4(,%rcx,4)\ncmp $0x2,%esi\njle 13d6 \ncmp $0x4,%esi\njle 140b \nlea -0x5(%rsi),%ecx\nmov %eax,%r9d\nshr %ecx\nlea 0x6(%rcx,%rcx,1),%r11\nmov $0x4,%ecx\nmov -0x8(%rdi,%rcx,4),%eax\nmov %edx,%r10d\ncmp %edx,%eax\ncmovge %eax,%r10d\nadd %r9d,%eax\ncmp %eax,%r10d\ncmovge %r10d,%eax\nmov %eax,%r9d\nmov %eax,-0x8(%r8,%rcx,4)\nmov -0x4(%rdi,%rcx,4),%eax\nadd %eax,%edx\ncmp %eax,%edx\ncmovl %eax,%edx\nmovslq %ecx,%rax\ncmp %r9d,%edx\ncmovl %r9d,%edx\nmov %edx,-0x4(%r8,%rcx,4)\nadd $0x2,%rcx\ncmp %rcx,%r11\njne 136e \nmov (%rdi,%rax,4),%edx\ncmp %edx,-0x4(%r8,%rax,4)\nmov %edx,%ecx\ncmovge -0x4(%r8,%rax,4),%ecx\nadd -0x8(%r8,%rax,4),%edx\ncmp %edx,%ecx\ncmovge %ecx,%edx\nmov %edx,(%r8,%rax,4)\nadd $0x1,%rax\ncmp %eax,%esi\njg 13b0 \nsub $0x1,%esi\nmovslq %esi,%rsi\nmov (%r8,%rsi,4),%eax\nmov -0x8(%rbp),%rdi\nxor %fs:0x28,%rdi\njne 1412 \nleaveq\nretq\nnopl 0x0(%rax)\nmov (%rdi),%eax\njmp 13e0 \nnopl 0x0(%rax)\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 1321 \nmov $0x2,%eax\njmp 13b0 \ncallq 1060 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov r8, rdi\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\ncmp esi, 1\njz loc_1400\nmovsxd rax, esi\nmov rcx, rsp\nmov edi, esi\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_1311\nloc_12FC:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rcx\njnz short loc_12FC\nloc_1311:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1408\nloc_1323:\nmov r9d, [r8]\nmov eax, [r8+4]\nlea rsi, [rsp+1010h+var_100D]\nmov rdx, rsi\nand rsi, 0FFFFFFFFFFFFFFFCh\nshr rdx, 2\ncmp r9d, eax\nmovd xmm0, r9d\ncmovge eax, r9d\nmovd xmm1, eax\npunpckldq xmm0, xmm1\nmovq qword ptr ds:dword_0[rdx*4], xmm0\ncmp edi, 2\njle loc_13E1\ncmp edi, 4\njle loc_1413\nlea edx, [rdi-5]\nmov ecx, 4\nshr edx, 1\nlea r10d, [rdx+3]\nadd r10, r10\nloc_137A:\nmov edx, [r8+rcx*4-8]\nmov r11d, eax\ncmp edx, eax\ncmovge r11d, edx\nadd edx, r9d\ncmp r11d, edx\ncmovge edx, r11d\nmov r9d, edx\nmov [rsi+rcx*4-8], edx\nmov edx, [r8+rcx*4-4]\nadd eax, edx\ncmp eax, edx\ncmovl eax, edx\nmov rdx, rcx\ncmp eax, r9d\ncmovl eax, r9d\nmov [rsi+rcx*4-4], eax\nadd rcx, 2\ncmp r10, rcx\njnz short loc_137A\nloc_13BC:\nmovsxd rdx, edx\nnop\nloc_13C0:\nmov ecx, [r8+rdx*4]\nmov eax, [rsi+rdx*4-4]\ncmp ecx, eax\ncmovge eax, ecx\nadd ecx, [rsi+rdx*4-8]\ncmp eax, ecx\ncmovl eax, ecx\nmov [rsi+rdx*4], eax\nadd rdx, 1\ncmp edi, edx\njg short loc_13C0\nloc_13E1:\nsub edi, 1\nmovsxd rdi, edi\nmov eax, [rsi+rdi*4]\nloc_13EA:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_141A\nleave\nretn\nloc_1400:\nmov eax, [rdi]\njmp short loc_13EA\nloc_1408:\nor [rsp+rdx+1010h+var_1018], 0\njmp loc_1323\nloc_1413:\nmov edx, 2\njmp short loc_13BC\nloc_141A:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(unsigned int *a1, int a2)\n{\n __int64 v2; // rdx\n _QWORD *v3; // rcx\n __int16 v4; // dx\n signed __int64 v5; // rdx\n void *v6; // rsp\n signed int v7; // r9d\n signed int v8; // eax\n __m128i v9; // xmm0\n __int64 v10; // rcx\n signed int v11; // edx\n signed int v12; // r11d\n int v13; // edx\n signed int v14; // edx\n __int64 v15; // rdx\n signed int v16; // ecx\n signed int v17; // eax\n signed int v18; // ecx\n _QWORD v21[511]; // [rsp+8h] [rbp-1010h] BYREF\n _QWORD v22[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v22[1] = __readfsqword(0x28u);\n if ( a2 == 1 )\n return *a1;\n v2 = 4LL * a2 + 15;\n v3 = (_QWORD *)((char *)v22 - (v2 & 0xFFFFFFFFFFFFF000LL));\n v4 = v2 & 0xFFF0;\n if ( v22 != v3 )\n {\n while ( v21 != v3 )\n ;\n }\n v5 = v4 & 0xFFF;\n v6 = alloca(v5);\n if ( v5 )\n *(_QWORD *)((char *)&v21[-1] + v5) = *(_QWORD *)((char *)&v21[-1] + v5);\n v7 = *a1;\n v8 = a1[1];\n v9 = _mm_cvtsi32_si128(*a1);\n if ( (int)*a1 >= v8 )\n v8 = *a1;\n v21[0] = _mm_unpacklo_epi32(v9, _mm_cvtsi32_si128(v8)).m128i_u64[0];\n if ( a2 > 2 )\n {\n if ( a2 <= 4 )\n {\n LODWORD(v15) = 2;\n }\n else\n {\n v10 = 4LL;\n do\n {\n v11 = a1[v10 - 2];\n v12 = v8;\n if ( v11 >= v8 )\n v12 = a1[v10 - 2];\n v13 = v7 + v11;\n if ( v12 >= v13 )\n v13 = v12;\n v7 = v13;\n LODWORD(v21[(unsigned __int64)v10 / 2 - 1]) = v13;\n v14 = a1[v10 - 1];\n v8 += v14;\n if ( v8 < v14 )\n v8 = a1[v10 - 1];\n LODWORD(v15) = v10;\n if ( v8 < v7 )\n v8 = v7;\n HIDWORD(v21[(unsigned __int64)v10 / 2 - 1]) = v8;\n v10 += 2LL;\n }\n while ( 2LL * (((unsigned int)(a2 - 5) >> 1) + 3) != v10 );\n }\n v15 = (int)v15;\n do\n {\n v16 = a1[v15];\n v17 = *((_DWORD *)v21 + v15 - 1);\n if ( v16 >= v17 )\n v17 = a1[v15];\n v18 = *((_DWORD *)&v21[-1] + v15) + v16;\n if ( v17 < v18 )\n v17 = v18;\n *((_DWORD *)v21 + v15++) = v17;\n }\n while ( a2 > (int)v15 );\n }\n return *((unsigned int *)v21 + a2 - 1);\n}", + "ida_strip_asm": "sub_12B0:\nendbr64\npush rbp\nmov r8, rdi\nmov rbp, rsp\nsub rsp, 10h\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\ncmp esi, 1\njz loc_1400\nmovsxd rax, esi\nmov rcx, rsp\nmov edi, esi\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_1311\nloc_12FC:\nsub rsp, 1000h\nor [rsp+1010h+var_18], 0\ncmp rsp, rcx\njnz short loc_12FC\nloc_1311:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1408\nloc_1323:\nmov r9d, [r8]\nmov eax, [r8+4]\nlea rsi, [rsp+1010h+var_100D]\nmov rdx, rsi\nand rsi, 0FFFFFFFFFFFFFFFCh\nshr rdx, 2\ncmp r9d, eax\nmovd xmm0, r9d\ncmovge eax, r9d\nmovd xmm1, eax\npunpckldq xmm0, xmm1\nmovq qword ptr ds:dword_0[rdx*4], xmm0\ncmp edi, 2\njle loc_13E1\ncmp edi, 4\njle loc_1413\nlea edx, [rdi-5]\nmov ecx, 4\nshr edx, 1\nlea r10d, [rdx+3]\nadd r10, r10\nloc_137A:\nmov edx, [r8+rcx*4-8]\nmov r11d, eax\ncmp edx, eax\ncmovge r11d, edx\nadd edx, r9d\ncmp r11d, edx\ncmovge edx, r11d\nmov r9d, edx\nmov [rsi+rcx*4-8], edx\nmov edx, [r8+rcx*4-4]\nadd eax, edx\ncmp eax, edx\ncmovl eax, edx\nmov rdx, rcx\ncmp eax, r9d\ncmovl eax, r9d\nmov [rsi+rcx*4-4], eax\nadd rcx, 2\ncmp r10, rcx\njnz short loc_137A\nloc_13BC:\nmovsxd rdx, edx\nnop\nloc_13C0:\nmov ecx, [r8+rdx*4]\nmov eax, [rsi+rdx*4-4]\ncmp ecx, eax\ncmovge eax, ecx\nadd ecx, [rsi+rdx*4-8]\ncmp eax, ecx\ncmovl eax, ecx\nmov [rsi+rdx*4], eax\nadd rdx, 1\ncmp edi, edx\njg short loc_13C0\nloc_13E1:\nsub edi, 1\nmovsxd rdi, edi\nmov eax, [rsi+rdi*4]\nloc_13EA:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njnz short loc_141A\nleave\nretn\nloc_1400:\nmov eax, [rdi]\njmp short loc_13EA\nloc_1408:\nor [rsp+rdx+1010h+var_1018], 0\njmp loc_1323\nloc_1413:\nmov edx, 2\njmp short loc_13BC\nloc_141A:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12B0(unsigned int *a1, int a2)\n{\n __int64 v2; // rdx\n _QWORD *v3; // rcx\n __int16 v4; // dx\n signed __int64 v5; // rdx\n void *v6; // rsp\n signed int v7; // r9d\n signed int v8; // eax\n __m128i v9; // xmm0\n __int64 v10; // rcx\n signed int v11; // edx\n signed int v12; // r11d\n int v13; // edx\n signed int v14; // edx\n __int64 v15; // rdx\n signed int v16; // ecx\n signed int v17; // eax\n signed int v18; // ecx\n _QWORD v21[511]; // [rsp+8h] [rbp-1010h] BYREF\n _QWORD v22[2]; // [rsp+1008h] [rbp-10h] BYREF\n\n v22[1] = __readfsqword(0x28u);\n if ( a2 == 1 )\n return *a1;\n v2 = 4LL * a2 + 15;\n v3 = (_QWORD *)((char *)v22 - (v2 & 0xFFFFFFFFFFFFF000LL));\n v4 = v2 & 0xFFF0;\n if ( v22 != v3 )\n {\n while ( v21 != v3 )\n ;\n }\n v5 = v4 & 0xFFF;\n v6 = alloca(v5);\n if ( v5 )\n *(_QWORD *)((char *)&v21[-1] + v5) = *(_QWORD *)((char *)&v21[-1] + v5);\n v7 = *a1;\n v8 = a1[1];\n v9 = _mm_cvtsi32_si128(*a1);\n if ( (int)*a1 >= v8 )\n v8 = *a1;\n v21[0] = _mm_unpacklo_epi32(v9, _mm_cvtsi32_si128(v8)).m128i_u64[0];\n if ( a2 > 2 )\n {\n if ( a2 <= 4 )\n {\n LODWORD(v15) = 2;\n }\n else\n {\n v10 = 4LL;\n do\n {\n v11 = a1[v10 - 2];\n v12 = v8;\n if ( v11 >= v8 )\n v12 = a1[v10 - 2];\n v13 = v7 + v11;\n if ( v12 >= v13 )\n v13 = v12;\n v7 = v13;\n LODWORD(v21[(unsigned __int64)v10 / 2 - 1]) = v13;\n v14 = a1[v10 - 1];\n v8 += v14;\n if ( v8 < v14 )\n v8 = a1[v10 - 1];\n LODWORD(v15) = v10;\n if ( v8 < v7 )\n v8 = v7;\n HIDWORD(v21[(unsigned __int64)v10 / 2 - 1]) = v8;\n v10 += 2LL;\n }\n while ( 2LL * (((unsigned int)(a2 - 5) >> 1) + 3) != v10 );\n }\n v15 = (int)v15;\n do\n {\n v16 = a1[v15];\n v17 = *((_DWORD *)v21 + v15 - 1);\n if ( v16 >= v17 )\n v17 = a1[v15];\n v18 = *((_DWORD *)&v21[-1] + v15) + v16;\n if ( v17 < v18 )\n v17 = v18;\n *((_DWORD *)v21 + v15++) = v17;\n }\n while ( a2 > (int)v15 );\n }\n return *((unsigned int *)v21 + a2 - 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12B0(unsigned int *a1, int a2) {\n long long v2;\n uint64_t *v3;\n short v4;\n signed long long v5;\n void *v6;\n signed int v7;\n signed int v8;\n __m128i v9;\n long long v10;\n signed int v11;\n signed int v12;\n int v13;\n signed int v14;\n long long v15;\n signed int v16;\n signed int v17;\n signed int v18;\n uint64_t v21[511];\n uint64_t v22[2];\n v22[1] = __readfsqword(40u);\n if (a2 == 1) return *a1;\n v2 = 4LL * a2 + 15;\n v3 = (uint64_t *)((char *)v22 - (v2 & 18446744073709547520LL));\n v4 = v2 & 65520;\n if (v22 != v3) {\n while (v21 != v3)\n ;\n }\n v5 = v4 & 4095;\n v6 = alloca(v5);\n if (v5)\n *(uint64_t *)((char *)&v21[-1] + v5) = *(uint64_t *)((char *)&v21[-1] + v5);\n v7 = *a1;\n v8 = a1[1];\n v9 = _mm_cvtsi32_si128(*a1);\n if ((int)*a1 >= v8) v8 = *a1;\n v21[0] = _mm_unpacklo_epi32(v9, _mm_cvtsi32_si128(v8)).m128i_u64[0];\n if (a2 > 2) {\n if (a2 <= 4) {\n LODWORD(v15) = 2;\n } else {\n v10 = 4LL;\n do {\n v11 = a1[v10 - 2];\n v12 = v8;\n if (v11 >= v8) v12 = a1[v10 - 2];\n v13 = v7 + v11;\n if (v12 >= v13) v13 = v12;\n v7 = v13;\n LODWORD(v21[(unsigned long long)v10 / 2 - 1]) = v13;\n v14 = a1[v10 - 1];\n v8 += v14;\n if (v8 < v14) v8 = a1[v10 - 1];\n LODWORD(v15) = v10;\n if (v8 < v7) v8 = v7;\n HIDWORD(v21[(unsigned long long)v10 / 2 - 1]) = v8;\n v10 += 2LL;\n } while (2LL * (((unsigned int)(a2 - 5) >> 1) + 3) != v10);\n }\n v15 = (int)v15;\n do {\n v16 = a1[v15];\n v17 = *((uint32_t *)v21 + v15 - 1);\n if (v16 >= v17) v17 = a1[v15];\n v18 = *((uint32_t *)&v21[-1] + v15) + v16;\n if (v17 < v18) v17 = v18;\n *((uint32_t *)v21 + v15++) = v17;\n } while (a2 > (int)v15);\n }\n return *((unsigned int *)v21 + a2 - 1);\n}", + "ida_pseudo_norm": "long long func0(unsigned int *a1, int a2) {\n long long v2;\n uint64_t *v3;\n short v4;\n signed long long v5;\n void *v6;\n signed int v7;\n signed int v8;\n __m128i v9;\n long long v10;\n signed int v11;\n signed int v12;\n int v13;\n signed int v14;\n long long v15;\n signed int v16;\n signed int v17;\n signed int v18;\n uint64_t v21[511];\n uint64_t v22[2];\n v22[1] = __readfsqword(40u);\n if (a2 == 1) return *a1;\n v2 = 4LL * a2 + 15;\n v3 = (uint64_t *)((char *)v22 - (v2 & 18446744073709547520LL));\n v4 = v2 & 65520;\n if (v22 != v3) {\n while (v21 != v3)\n ;\n }\n v5 = v4 & 4095;\n v6 = alloca(v5);\n if (v5)\n *(uint64_t *)((char *)&v21[-1] + v5) = *(uint64_t *)((char *)&v21[-1] + v5);\n v7 = *a1;\n v8 = a1[1];\n v9 = _mm_cvtsi32_si128(*a1);\n if ((int)*a1 >= v8) v8 = *a1;\n v21[0] = _mm_unpacklo_epi32(v9, _mm_cvtsi32_si128(v8)).m128i_u64[0];\n if (a2 > 2) {\n if (a2 <= 4) {\n LODWORD(v15) = 2;\n } else {\n v10 = 4LL;\n do {\n v11 = a1[v10 - 2];\n v12 = v8;\n if (v11 >= v8) v12 = a1[v10 - 2];\n v13 = v7 + v11;\n if (v12 >= v13) v13 = v12;\n v7 = v13;\n LODWORD(v21[(unsigned long long)v10 / 2 - 1]) = v13;\n v14 = a1[v10 - 1];\n v8 += v14;\n if (v8 < v14) v8 = a1[v10 - 1];\n LODWORD(v15) = v10;\n if (v8 < v7) v8 = v7;\n HIDWORD(v21[(unsigned long long)v10 / 2 - 1]) = v8;\n v10 += 2LL;\n } while (2LL * (((unsigned int)(a2 - 5) >> 1) + 3) != v10);\n }\n v15 = (int)v15;\n do {\n v16 = a1[v15];\n v17 = *((uint32_t *)v21 + v15 - 1);\n if (v16 >= v17) v17 = a1[v15];\n v18 = *((uint32_t *)&v21[-1] + v15) + v16;\n if (v17 < v18) v17 = v18;\n *((uint32_t *)v21 + v15++) = v17;\n } while (a2 > (int)v15);\n }\n return *((unsigned int *)v21 + a2 - 1);\n}" + }, + { + "index": 896, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n} Tuple;\n\n\n\nint compare_tuples(const void *a, const void *b) {\n\n Tuple *tuple_a = (Tuple *)a;\n\n Tuple *tuple_b = (Tuple *)b;\n\n return tuple_a->second - tuple_b->second;\n\n}\n\n\n\n", + "func": "void func0(Tuple *tuples, int length) {\n qsort(tuples, length, sizeof(Tuple), compare_tuples);\n}", + "test": "int main() {\n\n Tuple list1[5] = {{2, 5}, {1, 2}, {4, 4}, {2, 3}, {2, 1}};\n\n Tuple list2[5] = {{9, 8}, {4, 7}, {3, 5}, {7, 9}, {1, 2}};\n\n Tuple list3[3] = {{20, 50}, {10, 20}, {40, 40}};\n\n\n\n func0(list1, 5);\n\n func0(list2, 5);\n\n func0(list3, 3);\n\n\n\n assert(list1[0].first == 2 && list1[0].second == 1);\n\n assert(list1[1].first == 1 && list1[1].second == 2);\n\n assert(list1[2].first == 2 && list1[2].second == 3);\n\n assert(list1[3].first == 4 && list1[3].second == 4);\n\n assert(list1[4].first == 2 && list1[4].second == 5);\n\n\n\n assert(list2[0].first == 1 && list2[0].second == 2);\n\n assert(list2[1].first == 3 && list2[1].second == 5);\n\n assert(list2[2].first == 4 && list2[2].second == 7);\n\n assert(list2[3].first == 9 && list2[3].second == 8);\n\n assert(list2[4].first == 7 && list2[4].second == 9);\n\n\n\n assert(list3[0].first == 10 && list3[0].second == 20);\n\n assert(list3[1].first == 40 && list3[1].second == 40);\n\n assert(list3[2].first == 20 && list3[2].second == 50);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %rdi,-0x8(%rbp)\nmov %esi,-0xc(%rbp)\nmov -0xc(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x8(%rbp),%rax\nlea -0x58(%rip),%rcx\nmov $0x8,%edx\nmov %rax,%rdi\ncallq 1090 \nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+base], rdi\nmov [rbp+var_C], esi\nmov eax, [rbp+var_C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compare_tuples\nmov rcx, rdx; compar\nmov edx, 8; size\nmov rdi, rax; base\ncall _qsort\nnop\nleave\nretn", + "ida_pseudo": "void __fastcall func0(void *a1, int a2)\n{\n qsort(a1, a2, 8uLL, compare_tuples);\n}", + "ida_strip_asm": "sub_11DD:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+base], rdi\nmov [rbp+var_C], esi\nmov eax, [rbp+var_C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 8; size\nmov rdi, rax; base\ncall _qsort\nnop\nleave\nretn", + "ida_strip_pseudo": "void __fastcall sub_11DD(void *a1, int a2)\n{\n qsort(a1, a2, 8uLL, compar);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_11DD(void *a1, int a2) { qsort(a1, a2, 8uLL, compar); }", + "ida_pseudo_norm": "void func0(void *a1, int a2) { qsort(a1, a2, 8uLL, compare_tuples); }" + }, + { + "index": 896, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n} Tuple;\n\n\n\nint compare_tuples(const void *a, const void *b) {\n\n Tuple *tuple_a = (Tuple *)a;\n\n Tuple *tuple_b = (Tuple *)b;\n\n return tuple_a->second - tuple_b->second;\n\n}\n\n\n\n", + "func": "void func0(Tuple *tuples, int length) {\n qsort(tuples, length, sizeof(Tuple), compare_tuples);\n}", + "test": "int main() {\n\n Tuple list1[5] = {{2, 5}, {1, 2}, {4, 4}, {2, 3}, {2, 1}};\n\n Tuple list2[5] = {{9, 8}, {4, 7}, {3, 5}, {7, 9}, {1, 2}};\n\n Tuple list3[3] = {{20, 50}, {10, 20}, {40, 40}};\n\n\n\n func0(list1, 5);\n\n func0(list2, 5);\n\n func0(list3, 3);\n\n\n\n assert(list1[0].first == 2 && list1[0].second == 1);\n\n assert(list1[1].first == 1 && list1[1].second == 2);\n\n assert(list1[2].first == 2 && list1[2].second == 3);\n\n assert(list1[3].first == 4 && list1[3].second == 4);\n\n assert(list1[4].first == 2 && list1[4].second == 5);\n\n\n\n assert(list2[0].first == 1 && list2[0].second == 2);\n\n assert(list2[1].first == 3 && list2[1].second == 5);\n\n assert(list2[2].first == 4 && list2[2].second == 7);\n\n assert(list2[3].first == 9 && list2[3].second == 8);\n\n assert(list2[4].first == 7 && list2[4].second == 9);\n\n\n\n assert(list3[0].first == 10 && list3[0].second == 20);\n\n assert(list3[1].first == 40 && list3[1].second == 40);\n\n assert(list3[2].first == 20 && list3[2].second == 50);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x8,%rsp\nmovslq %esi,%rsi\nlea -0x1d(%rip),%rcx\nmov $0x8,%edx\ncallq 1090 \nadd $0x8,%rsp\nretq\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\nmovsxd rsi, esi; nmemb\nlea rcx, compare_tuples; compar\nmov edx, 8; size\ncall _qsort\nadd rsp, 8\nretn", + "ida_pseudo": "void __fastcall func0(void *a1, int a2)\n{\n qsort(a1, a2, 8uLL, compare_tuples);\n}", + "ida_strip_asm": "sub_11B4:\nendbr64\nsub rsp, 8\nmovsxd rsi, esi; nmemb\nlea rcx, compar; compar\nmov edx, 8; size\ncall _qsort\nadd rsp, 8\nretn", + "ida_strip_pseudo": "void __fastcall sub_11B4(void *a1, int a2)\n{\n qsort(a1, a2, 8uLL, compar);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_11B4(void *a1, int a2) { qsort(a1, a2, 8uLL, compar); }", + "ida_pseudo_norm": "void func0(void *a1, int a2) { qsort(a1, a2, 8uLL, compare_tuples); }" + }, + { + "index": 897, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char* sentence, const char* word) {\n char* token;\n char* toFree;\n char* sentenceCopy = strdup(sentence);\n if (!sentenceCopy) return false;\n toFree = sentenceCopy;\n token = strtok(sentenceCopy, \" \");\n while (token != NULL) {\n if (strcmp(token, word) == 0) {\n free(toFree);\n return true;\n }\n token = strtok(NULL, \" \");\n }\n free(toFree);\n return false;\n}", + "test": "int main() {\n\n assert(func0(\"machine learning\", \"machine\") == true);\n\n assert(func0(\"easy\", \"fun\") == false);\n\n assert(func0(\"python language\", \"code\") == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x28(%rbp)\nmov %rsi,-0x30(%rbp)\nmov -0x28(%rbp),%rax\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,-0x10(%rbp)\ncmpq $0x0,-0x10(%rbp)\njne 11fb \nmov $0x0,%eax\njmp 1273 \nmov -0x10(%rbp),%rax\nmov %rax,-0x8(%rbp)\nmov -0x10(%rbp),%rax\nlea 0xdfa(%rip),%rsi\nmov %rax,%rdi\ncallq 10c0 \nmov %rax,-0x18(%rbp)\njmp 125b \nmov -0x30(%rbp),%rdx\nmov -0x18(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10b0 \ntest %eax,%eax\njne 1246 \nmov -0x8(%rbp),%rax\nmov %rax,%rdi\ncallq 1090 \nmov $0x1,%eax\njmp 1273 \nlea 0xdbb(%rip),%rsi\nmov $0x0,%edi\ncallq 10c0 \nmov %rax,-0x18(%rbp)\ncmpq $0x0,-0x18(%rbp)\njne 121c \nmov -0x8(%rbp),%rax\nmov %rax,%rdi\ncallq 1090 \nmov $0x0,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov [rbp+s2], rsi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strdup\nmov [rbp+var_10], rax\ncmp [rbp+var_10], 0\njnz short loc_11FB\nmov eax, 0\njmp short locret_1279\nloc_11FB:\nmov rax, [rbp+var_10]\nmov [rbp+ptr], rax\nmov rax, [rbp+var_10]\nlea rdx, delim; \" \"\nmov rsi, rdx; delim\nmov rdi, rax; s\ncall _strtok\nmov [rbp+s1], rax\njmp short loc_1261\nloc_121F:\nmov rdx, [rbp+s2]\nmov rax, [rbp+s1]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1249\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov eax, 1\njmp short locret_1279\nloc_1249:\nlea rax, delim; \" \"\nmov rsi, rax; delim\nmov edi, 0; s\ncall _strtok\nmov [rbp+s1], rax\nloc_1261:\ncmp [rbp+s1], 0\njnz short loc_121F\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov eax, 0\nlocret_1279:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, const char *a2)\n{\n const char *s1; // [rsp+18h] [rbp-18h]\n char *v4; // [rsp+20h] [rbp-10h]\n\n v4 = strdup(a1);\n if ( !v4 )\n return 0LL;\n for ( s1 = strtok(v4, \" \"); s1; s1 = strtok(0LL, \" \") )\n {\n if ( !strcmp(s1, a2) )\n {\n free(v4);\n return 1LL;\n }\n }\n free(v4);\n return 0LL;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov [rbp+s2], rsi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strdup\nmov [rbp+var_10], rax\ncmp [rbp+var_10], 0\njnz short loc_11FB\nmov eax, 0\njmp short locret_1279\nloc_11FB:\nmov rax, [rbp+var_10]\nmov [rbp+ptr], rax\nmov rax, [rbp+var_10]\nlea rdx, delim; \" \"\nmov rsi, rdx; delim\nmov rdi, rax; s\ncall _strtok\nmov [rbp+s1], rax\njmp short loc_1261\nloc_121F:\nmov rdx, [rbp+s2]\nmov rax, [rbp+s1]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1249\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov eax, 1\njmp short locret_1279\nloc_1249:\nlea rax, delim; \" \"\nmov rsi, rax; delim\nmov edi, 0; s\ncall _strtok\nmov [rbp+s1], rax\nloc_1261:\ncmp [rbp+s1], 0\njnz short loc_121F\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov eax, 0\nlocret_1279:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11C9(const char *a1, const char *a2)\n{\n const char *s1; // [rsp+18h] [rbp-18h]\n char *v4; // [rsp+20h] [rbp-10h]\n\n v4 = strdup(a1);\n if ( !v4 )\n return 0LL;\n for ( s1 = strtok(v4, \" \"); s1; s1 = strtok(0LL, \" \") )\n {\n if ( !strcmp(s1, a2) )\n {\n free(v4);\n return 1LL;\n }\n }\n free(v4);\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11C9(const char *a1, const char *a2) {\n const char *s1;\n char *v4;\n v4 = strdup(a1);\n if (!v4) return 0LL;\n for (s1 = strtok(v4, \" \"); s1; s1 = strtok(0LL, \" \")) {\n if (!strcmp(s1, a2)) {\n free(v4);\n return 1LL;\n }\n }\n free(v4);\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, const char *a2) {\n const char *s1;\n char *v4;\n v4 = strdup(a1);\n if (!v4) return 0LL;\n for (s1 = strtok(v4, \" \"); s1; s1 = strtok(0LL, \" \")) {\n if (!strcmp(s1, a2)) {\n free(v4);\n return 1LL;\n }\n }\n free(v4);\n return 0LL;\n}" + }, + { + "index": 897, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char* sentence, const char* word) {\n char* token;\n char* toFree;\n char* sentenceCopy = strdup(sentence);\n if (!sentenceCopy) return false;\n toFree = sentenceCopy;\n token = strtok(sentenceCopy, \" \");\n while (token != NULL) {\n if (strcmp(token, word) == 0) {\n free(toFree);\n return true;\n }\n token = strtok(NULL, \" \");\n }\n free(toFree);\n return false;\n}", + "test": "int main() {\n\n assert(func0(\"machine learning\", \"machine\") == true);\n\n assert(func0(\"easy\", \"fun\") == false);\n\n assert(func0(\"python language\", \"code\") == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmov %rsi,%rbx\ncallq 10d0 \ntest %rax,%rax\nje 1241 \nmov %rax,%rbp\nlea 0xe1c(%rip),%rsi\nmov %rax,%rdi\ncallq 10c0 \nmov %rax,%rdi\ntest %rax,%rax\nje 1220 \nlea 0xe05(%rip),%r12\nmov %rbx,%rsi\ncallq 10b0 \ntest %eax,%eax\nje 1232 \nmov %r12,%rsi\nmov $0x0,%edi\ncallq 10c0 \nmov %rax,%rdi\ntest %rax,%rax\njne 11ff \nmov %rbp,%rdi\ncallq 1090 \nmov $0x0,%eax\npop %rbx\npop %rbp\npop %r12\nretq\nmov %rbp,%rdi\ncallq 1090 \nmov $0x1,%eax\njmp 122d \nmov $0x0,%eax\njmp 122d \n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbx, rsi\ncall _strdup\ntest rax, rax\njz short loc_1241\nmov rbp, rax\nlea rsi, delim; \" \"\nmov rdi, rax; s\ncall _strtok\nmov rdi, rax; s1\ntest rax, rax\njz short loc_1220\nlea r12, delim; \" \"\nloc_11FF:\nmov rsi, rbx; s2\ncall _strcmp\ntest eax, eax\njz short loc_1232\nmov rsi, r12; delim\nmov edi, 0; s\ncall _strtok\nmov rdi, rax\ntest rax, rax\njnz short loc_11FF\nloc_1220:\nmov rdi, rbp; ptr\ncall _free\nmov eax, 0\nloc_122D:\npop rbx\npop rbp\npop r12\nretn\nloc_1232:\nmov rdi, rbp; ptr\ncall _free\nmov eax, 1\njmp short loc_122D\nloc_1241:\nmov eax, 0\njmp short loc_122D", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, const char *a2)\n{\n char *v2; // rax\n char *v3; // rbp\n char *v4; // rdi\n\n v2 = strdup(a1);\n if ( !v2 )\n return 0LL;\n v3 = v2;\n v4 = strtok(v2, \" \");\n if ( v4 )\n {\n while ( strcmp(v4, a2) )\n {\n v4 = strtok(0LL, \" \");\n if ( !v4 )\n goto LABEL_5;\n }\n free(v3);\n return 1LL;\n }\n else\n {\nLABEL_5:\n free(v3);\n return 0LL;\n }\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbx, rsi\ncall _strdup\ntest rax, rax\njz short loc_1241\nmov rbp, rax\nlea rsi, delim; \" \"\nmov rdi, rax; s\ncall _strtok\nmov rdi, rax; s1\ntest rax, rax\njz short loc_1220\nlea r12, delim; \" \"\nloc_11FF:\nmov rsi, rbx; s2\ncall _strcmp\ntest eax, eax\njz short loc_1232\nmov rsi, r12; delim\nmov edi, 0; s\ncall _strtok\nmov rdi, rax\ntest rax, rax\njnz short loc_11FF\nloc_1220:\nmov rdi, rbp; ptr\ncall _free\nmov eax, 0\nloc_122D:\npop rbx\npop rbp\npop r12\nretn\nloc_1232:\nmov rdi, rbp; ptr\ncall _free\nmov eax, 1\njmp short loc_122D\nloc_1241:\nmov eax, 0\njmp short loc_122D", + "ida_strip_pseudo": "__int64 __fastcall sub_11C9(const char *a1, const char *a2)\n{\n char *v2; // rax\n char *v3; // rbp\n char *v4; // rdi\n\n v2 = strdup(a1);\n if ( !v2 )\n return 0LL;\n v3 = v2;\n v4 = strtok(v2, \" \");\n if ( v4 )\n {\n while ( strcmp(v4, a2) )\n {\n v4 = strtok(0LL, \" \");\n if ( !v4 )\n goto LABEL_5;\n }\n free(v3);\n return 1LL;\n }\n else\n {\nLABEL_5:\n free(v3);\n return 0LL;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11C9(const char *a1, const char *a2) {\n char *v2;\n char *v3;\n char *v4;\n v2 = strdup(a1);\n if (!v2) return 0LL;\n v3 = v2;\n v4 = strtok(v2, \" \");\n if (v4) {\n while (strcmp(v4, a2)) {\n v4 = strtok(0LL, \" \");\n if (!v4) goto LABEL_5;\n }\n free(v3);\n return 1LL;\n } else {\n LABEL_5:\n free(v3);\n return 0LL;\n }\n}", + "ida_pseudo_norm": "long long func0(const char *a1, const char *a2) {\n char *v2;\n char *v3;\n char *v4;\n v2 = strdup(a1);\n if (!v2) return 0LL;\n v3 = v2;\n v4 = strtok(v2, \" \");\n if (v4) {\n while (strcmp(v4, a2)) {\n v4 = strtok(0LL, \" \");\n if (!v4) goto LABEL_5;\n }\n free(v3);\n return 1LL;\n } else {\n LABEL_5:\n free(v3);\n return 0LL;\n }\n}" + }, + { + "index": 897, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char* sentence, const char* word) {\n char* token;\n char* toFree;\n char* sentenceCopy = strdup(sentence);\n if (!sentenceCopy) return false;\n toFree = sentenceCopy;\n token = strtok(sentenceCopy, \" \");\n while (token != NULL) {\n if (strcmp(token, word) == 0) {\n free(toFree);\n return true;\n }\n token = strtok(NULL, \" \");\n }\n free(toFree);\n return false;\n}", + "test": "int main() {\n\n assert(func0(\"machine learning\", \"machine\") == true);\n\n assert(func0(\"easy\", \"fun\") == false);\n\n assert(func0(\"python language\", \"code\") == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmov %rsi,%rbx\ncallq 10d0 \ntest %rax,%rax\nje 130f \nmov %rax,%rdi\nlea 0xd55(%rip),%rsi\nmov %rax,%rbp\ncallq 10c0 \nmov %rax,%rdi\ntest %rax,%rax\nje 1300 \nlea 0xd3e(%rip),%r12\njmp 12e2 \nnopl 0x0(%rax,%rax,1)\nxor %edi,%edi\nmov %r12,%rsi\ncallq 10c0 \nmov %rax,%rdi\ntest %rax,%rax\nje 1300 \nmov %rbx,%rsi\ncallq 10b0 \ntest %eax,%eax\njne 12d0 \nmov %rbp,%rdi\ncallq 1090 \npop %rbx\nmov $0x1,%eax\npop %rbp\npop %r12\nretq\nmov %rbp,%rdi\ncallq 1090 \nxor %eax,%eax\npop %rbx\npop %rbp\npop %r12\nretq\nxor %eax,%eax\njmp 130a \nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbx, rsi\ncall _strdup\ntest rax, rax\njz short loc_1308\nlea rbp, delim; \" \"\nmov rdi, rax; s\nmov r12, rax\nmov rsi, rbp; delim\ncall _strtok\nmov rdi, rax\ntest rax, rax\njnz short loc_12DA\njmp short loc_1300\nloc_12C8:\nxor edi, edi; s\nmov rsi, rbp; delim\ncall _strtok\nmov rdi, rax; s1\ntest rax, rax\njz short loc_1300\nloc_12DA:\nmov rsi, rbx; s2\ncall _strcmp\ntest eax, eax\njnz short loc_12C8\nmov rdi, r12; ptr\ncall _free\npop rbx\nmov eax, 1\npop rbp\npop r12\nretn\nloc_1300:\nmov rdi, r12; ptr\ncall _free\nloc_1308:\npop rbx\nxor eax, eax\npop rbp\npop r12\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, const char *a2)\n{\n char *v2; // rax\n char *v3; // r12\n char *v4; // rdi\n\n v2 = strdup(a1);\n if ( !v2 )\n return 0LL;\n v3 = v2;\n v4 = strtok(v2, \" \");\n if ( !v4 )\n {\nLABEL_7:\n free(v3);\n return 0LL;\n }\n while ( strcmp(v4, a2) )\n {\n v4 = strtok(0LL, \" \");\n if ( !v4 )\n goto LABEL_7;\n }\n free(v3);\n return 1LL;\n}", + "ida_strip_asm": "sub_1290:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbx, rsi\ncall _strdup\ntest rax, rax\njz short loc_1308\nlea rbp, delim; \" \"\nmov rdi, rax; s\nmov r12, rax\nmov rsi, rbp; delim\ncall _strtok\nmov rdi, rax\ntest rax, rax\njnz short loc_12DA\njmp short loc_1300\nloc_12C8:\nxor edi, edi; s\nmov rsi, rbp; delim\ncall _strtok\nmov rdi, rax; s1\ntest rax, rax\njz short loc_1300\nloc_12DA:\nmov rsi, rbx; s2\ncall _strcmp\ntest eax, eax\njnz short loc_12C8\nmov rdi, r12; ptr\ncall _free\npop rbx\nmov eax, 1\npop rbp\npop r12\nretn\nloc_1300:\nmov rdi, r12; ptr\ncall _free\nloc_1308:\npop rbx\nxor eax, eax\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1290(const char *a1, const char *a2)\n{\n char *v2; // rax\n char *v3; // r12\n char *v4; // rdi\n\n v2 = strdup(a1);\n if ( !v2 )\n return 0LL;\n v3 = v2;\n v4 = strtok(v2, \" \");\n if ( !v4 )\n {\nLABEL_7:\n free(v3);\n return 0LL;\n }\n while ( strcmp(v4, a2) )\n {\n v4 = strtok(0LL, \" \");\n if ( !v4 )\n goto LABEL_7;\n }\n free(v3);\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1290(const char *a1, const char *a2) {\n char *v2;\n char *v3;\n char *v4;\n v2 = strdup(a1);\n if (!v2) return 0LL;\n v3 = v2;\n v4 = strtok(v2, \" \");\n if (!v4) {\n LABEL_7:\n free(v3);\n return 0LL;\n }\n while (strcmp(v4, a2)) {\n v4 = strtok(0LL, \" \");\n if (!v4) goto LABEL_7;\n }\n free(v3);\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, const char *a2) {\n char *v2;\n char *v3;\n char *v4;\n v2 = strdup(a1);\n if (!v2) return 0LL;\n v3 = v2;\n v4 = strtok(v2, \" \");\n if (!v4) {\n LABEL_7:\n free(v3);\n return 0LL;\n }\n while (strcmp(v4, a2)) {\n v4 = strtok(0LL, \" \");\n if (!v4) goto LABEL_7;\n }\n free(v3);\n return 1LL;\n}" + }, + { + "index": 897, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char* sentence, const char* word) {\n char* token;\n char* toFree;\n char* sentenceCopy = strdup(sentence);\n if (!sentenceCopy) return false;\n toFree = sentenceCopy;\n token = strtok(sentenceCopy, \" \");\n while (token != NULL) {\n if (strcmp(token, word) == 0) {\n free(toFree);\n return true;\n }\n token = strtok(NULL, \" \");\n }\n free(toFree);\n return false;\n}", + "test": "int main() {\n\n assert(func0(\"machine learning\", \"machine\") == true);\n\n assert(func0(\"easy\", \"fun\") == false);\n\n assert(func0(\"python language\", \"code\") == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmov %rsi,%rbx\ncallq 10d0 \ntest %rax,%rax\nje 130f \nmov %rax,%rdi\nlea 0xd55(%rip),%rsi\nmov %rax,%rbp\ncallq 10c0 \nmov %rax,%rdi\ntest %rax,%rax\nje 1300 \nlea 0xd3e(%rip),%r12\njmp 12e2 \nnopl 0x0(%rax,%rax,1)\nxor %edi,%edi\nmov %r12,%rsi\ncallq 10c0 \nmov %rax,%rdi\ntest %rax,%rax\nje 1300 \nmov %rbx,%rsi\ncallq 10b0 \ntest %eax,%eax\njne 12d0 \nmov %rbp,%rdi\ncallq 1090 \npop %rbx\nmov $0x1,%eax\npop %rbp\npop %r12\nretq\nmov %rbp,%rdi\ncallq 1090 \nxor %eax,%eax\npop %rbx\npop %rbp\npop %r12\nretq\nxor %eax,%eax\njmp 130a \nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbx, rsi\ncall _strdup\ntest rax, rax\njz short loc_1308\nlea rbp, delim; \" \"\nmov rdi, rax; s\nmov r12, rax\nmov rsi, rbp; delim\ncall _strtok\nmov rdi, rax\ntest rax, rax\njnz short loc_12DA\njmp short loc_1300\nloc_12C8:\nxor edi, edi; s\nmov rsi, rbp; delim\ncall _strtok\nmov rdi, rax; s1\ntest rax, rax\njz short loc_1300\nloc_12DA:\nmov rsi, rbx; s2\ncall _strcmp\ntest eax, eax\njnz short loc_12C8\nmov rdi, r12; ptr\ncall _free\npop rbx\nmov eax, 1\npop rbp\npop r12\nretn\nloc_1300:\nmov rdi, r12; ptr\ncall _free\nloc_1308:\npop rbx\nxor eax, eax\npop rbp\npop r12\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1, const char *a2)\n{\n char *v2; // rax\n char *v3; // r12\n char *v4; // rdi\n\n v2 = strdup(a1);\n if ( !v2 )\n return 0LL;\n v3 = v2;\n v4 = strtok(v2, \" \");\n if ( !v4 )\n {\nLABEL_7:\n free(v3);\n return 0LL;\n }\n while ( strcmp(v4, a2) )\n {\n v4 = strtok(0LL, \" \");\n if ( !v4 )\n goto LABEL_7;\n }\n free(v3);\n return 1LL;\n}", + "ida_strip_asm": "sub_1290:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbx, rsi\ncall _strdup\ntest rax, rax\njz short loc_1308\nlea rbp, delim; \" \"\nmov rdi, rax; s\nmov r12, rax\nmov rsi, rbp; delim\ncall _strtok\nmov rdi, rax\ntest rax, rax\njnz short loc_12DA\njmp short loc_1300\nloc_12C8:\nxor edi, edi; s\nmov rsi, rbp; delim\ncall _strtok\nmov rdi, rax; s1\ntest rax, rax\njz short loc_1300\nloc_12DA:\nmov rsi, rbx; s2\ncall _strcmp\ntest eax, eax\njnz short loc_12C8\nmov rdi, r12; ptr\ncall _free\npop rbx\nmov eax, 1\npop rbp\npop r12\nretn\nloc_1300:\nmov rdi, r12; ptr\ncall _free\nloc_1308:\npop rbx\nxor eax, eax\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1290(const char *a1, const char *a2)\n{\n char *v2; // rax\n char *v3; // r12\n char *v4; // rdi\n\n v2 = strdup(a1);\n if ( !v2 )\n return 0LL;\n v3 = v2;\n v4 = strtok(v2, \" \");\n if ( !v4 )\n {\nLABEL_7:\n free(v3);\n return 0LL;\n }\n while ( strcmp(v4, a2) )\n {\n v4 = strtok(0LL, \" \");\n if ( !v4 )\n goto LABEL_7;\n }\n free(v3);\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1290(const char *a1, const char *a2) {\n char *v2;\n char *v3;\n char *v4;\n v2 = strdup(a1);\n if (!v2) return 0LL;\n v3 = v2;\n v4 = strtok(v2, \" \");\n if (!v4) {\n LABEL_7:\n free(v3);\n return 0LL;\n }\n while (strcmp(v4, a2)) {\n v4 = strtok(0LL, \" \");\n if (!v4) goto LABEL_7;\n }\n free(v3);\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(const char *a1, const char *a2) {\n char *v2;\n char *v3;\n char *v4;\n v2 = strdup(a1);\n if (!v2) return 0LL;\n v3 = v2;\n v4 = strtok(v2, \" \");\n if (!v4) {\n LABEL_7:\n free(v3);\n return 0LL;\n }\n while (strcmp(v4, a2)) {\n v4 = strtok(0LL, \" \");\n if (!v4) goto LABEL_7;\n }\n free(v3);\n return 1LL;\n}" + }, + { + "index": 898, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(const int numbers[], int length, int n, int* result_size) {\n int* result = malloc(length * sizeof(int));\n *result_size = 0;\n int count = 1;\n int current = numbers[0];\n for (int i = 1; i < length; i++) {\n if (numbers[i] == current) {\n count++;\n } else {\n if (count == n) {\n result[*result_size] = current;\n (*result_size)++;\n }\n current = numbers[i];\n count = 1;\n }\n }\n if (count == n) {\n result[*result_size] = current;\n (*result_size)++;\n }\n return result;\n}", + "test": "int main() {\n\n // Test Case 1\n\n int numbers1[] = {1, 1, 3, 4, 4, 5, 6, 7};\n\n int result1_size = 0;\n\n int* result1 = func0(numbers1, 8, 2, &result1_size);\n\n int expected1[] = {1, 4};\n\n assert(result1_size == 2 && result1[0] == expected1[0] && result1[1] == expected1[1]);\n\n \n\n // Test Case 2\n\n int numbers2[] = {0, 1, 2, 3, 4, 4, 4, 4, 5, 7};\n\n int result2_size = 0;\n\n int* result2 = func0(numbers2, 10, 4, &result2_size);\n\n int expected2[] = {4};\n\n assert(result2_size == 1 && result2[0] == expected2[0]);\n\n\n\n // Test Case 3\n\n int numbers3[] = {0, 0, 0, 0, 0};\n\n int result3_size = 0;\n\n int* result3 = func0(numbers3, 5, 5, &result3_size);\n\n int expected3[] = {0};\n\n assert(result3_size == 1 && result3[0] == expected3[0]);\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n printf(\"All tests passed!\\n\");\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x40,%rsp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmov %edx,-0x30(%rbp)\nmov %rcx,-0x38(%rbp)\nmov -0x2c(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,-0x8(%rbp)\nmov -0x38(%rbp),%rax\nmovl $0x0,(%rax)\nmovl $0x1,-0x14(%rbp)\nmov -0x28(%rbp),%rax\nmov (%rax),%eax\nmov %eax,-0x10(%rbp)\nmovl $0x1,-0xc(%rbp)\njmp 1293 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x10(%rbp)\njne 123c \naddl $0x1,-0x14(%rbp)\njmp 128f \nmov -0x14(%rbp),%eax\ncmp -0x30(%rbp),%eax\njne 126f \nmov -0x38(%rbp),%rax\nmov (%rax),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov -0x10(%rbp),%eax\nmov %eax,(%rdx)\nmov -0x38(%rbp),%rax\nmov (%rax),%eax\nlea 0x1(%rax),%edx\nmov -0x38(%rbp),%rax\nmov %edx,(%rax)\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x10(%rbp)\nmovl $0x1,-0x14(%rbp)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 121b \nmov -0x14(%rbp),%eax\ncmp -0x30(%rbp),%eax\njne 12ce \nmov -0x38(%rbp),%rax\nmov (%rax),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov -0x10(%rbp),%eax\nmov %eax,(%rdx)\nmov -0x38(%rbp),%rax\nmov (%rax),%eax\nlea 0x1(%rax),%edx\nmov -0x38(%rbp),%rax\nmov %edx,(%rax)\nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_30], edx\nmov [rbp+var_38], rcx\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov rax, [rbp+var_38]\nmov dword ptr [rax], 0\nmov [rbp+var_14], 1\nmov rax, [rbp+var_28]\nmov eax, [rax]\nmov [rbp+var_10], eax\nmov [rbp+var_C], 1\njmp short loc_1293\nloc_121B:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_10], eax\njnz short loc_123C\nadd [rbp+var_14], 1\njmp short loc_128F\nloc_123C:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_30]\njnz short loc_126F\nmov rax, [rbp+var_38]\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_10]\nmov [rdx], eax\nmov rax, [rbp+var_38]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_38]\nmov [rax], edx\nloc_126F:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_10], eax\nmov [rbp+var_14], 1\nloc_128F:\nadd [rbp+var_C], 1\nloc_1293:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_2C]\njl short loc_121B\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_30]\njnz short loc_12CE\nmov rax, [rbp+var_38]\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_10]\nmov [rdx], eax\nmov rax, [rbp+var_38]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_38]\nmov [rax], edx\nloc_12CE:\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2, int a3, _DWORD *a4)\n{\n int v7; // [rsp+2Ch] [rbp-14h]\n int v8; // [rsp+30h] [rbp-10h]\n int i; // [rsp+34h] [rbp-Ch]\n _DWORD *v10; // [rsp+38h] [rbp-8h]\n\n v10 = malloc(4LL * a2);\n *a4 = 0;\n v7 = 1;\n v8 = *a1;\n for ( i = 1; i < a2; ++i )\n {\n if ( v8 == a1[i] )\n {\n ++v7;\n }\n else\n {\n if ( v7 == a3 )\n v10[(*a4)++] = v8;\n v8 = a1[i];\n v7 = 1;\n }\n }\n if ( v7 == a3 )\n v10[(*a4)++] = v8;\n return v10;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_30], edx\nmov [rbp+var_38], rcx\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov rax, [rbp+var_38]\nmov dword ptr [rax], 0\nmov [rbp+var_14], 1\nmov rax, [rbp+var_28]\nmov eax, [rax]\nmov [rbp+var_10], eax\nmov [rbp+var_C], 1\njmp short loc_1293\nloc_121B:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_10], eax\njnz short loc_123C\nadd [rbp+var_14], 1\njmp short loc_128F\nloc_123C:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_30]\njnz short loc_126F\nmov rax, [rbp+var_38]\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_10]\nmov [rdx], eax\nmov rax, [rbp+var_38]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_38]\nmov [rax], edx\nloc_126F:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_10], eax\nmov [rbp+var_14], 1\nloc_128F:\nadd [rbp+var_C], 1\nloc_1293:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_2C]\njl short loc_121B\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_30]\njnz short loc_12CE\nmov rax, [rbp+var_38]\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rbp+var_10]\nmov [rdx], eax\nmov rax, [rbp+var_38]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_38]\nmov [rax], edx\nloc_12CE:\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11C9(int *a1, int a2, int a3, _DWORD *a4)\n{\n int v7; // [rsp+2Ch] [rbp-14h]\n int v8; // [rsp+30h] [rbp-10h]\n int i; // [rsp+34h] [rbp-Ch]\n _DWORD *v10; // [rsp+38h] [rbp-8h]\n\n v10 = malloc(4LL * a2);\n *a4 = 0;\n v7 = 1;\n v8 = *a1;\n for ( i = 1; i < a2; ++i )\n {\n if ( v8 == a1[i] )\n {\n ++v7;\n }\n else\n {\n if ( v7 == a3 )\n v10[(*a4)++] = v8;\n v8 = a1[i];\n v7 = 1;\n }\n }\n if ( v7 == a3 )\n v10[(*a4)++] = v8;\n return v10;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11C9(int *a1, int a2, int a3, uint32_t *a4) {\n int v7;\n int v8;\n int i;\n uint32_t *v10;\n v10 = malloc(4LL * a2);\n *a4 = 0;\n v7 = 1;\n v8 = *a1;\n for (i = 1; i < a2; ++i) {\n if (v8 == a1[i]) {\n ++v7;\n } else {\n if (v7 == a3) v10[(*a4)++] = v8;\n v8 = a1[i];\n v7 = 1;\n }\n }\n if (v7 == a3) v10[(*a4)++] = v8;\n return v10;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2, int a3, uint32_t *a4) {\n int v7;\n int v8;\n int i;\n uint32_t *v10;\n v10 = malloc(4LL * a2);\n *a4 = 0;\n v7 = 1;\n v8 = *a1;\n for (i = 1; i < a2; ++i) {\n if (v8 == a1[i]) {\n ++v7;\n } else {\n if (v7 == a3) v10[(*a4)++] = v8;\n v8 = a1[i];\n v7 = 1;\n }\n }\n if (v7 == a3) v10[(*a4)++] = v8;\n return v10;\n}" + }, + { + "index": 898, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(const int numbers[], int length, int n, int* result_size) {\n int* result = malloc(length * sizeof(int));\n *result_size = 0;\n int count = 1;\n int current = numbers[0];\n for (int i = 1; i < length; i++) {\n if (numbers[i] == current) {\n count++;\n } else {\n if (count == n) {\n result[*result_size] = current;\n (*result_size)++;\n }\n current = numbers[i];\n count = 1;\n }\n }\n if (count == n) {\n result[*result_size] = current;\n (*result_size)++;\n }\n return result;\n}", + "test": "int main() {\n\n // Test Case 1\n\n int numbers1[] = {1, 1, 3, 4, 4, 5, 6, 7};\n\n int result1_size = 0;\n\n int* result1 = func0(numbers1, 8, 2, &result1_size);\n\n int expected1[] = {1, 4};\n\n assert(result1_size == 2 && result1[0] == expected1[0] && result1[1] == expected1[1]);\n\n \n\n // Test Case 2\n\n int numbers2[] = {0, 1, 2, 3, 4, 4, 4, 4, 5, 7};\n\n int result2_size = 0;\n\n int* result2 = func0(numbers2, 10, 4, &result2_size);\n\n int expected2[] = {4};\n\n assert(result2_size == 1 && result2[0] == expected2[0]);\n\n\n\n // Test Case 3\n\n int numbers3[] = {0, 0, 0, 0, 0};\n\n int result3_size = 0;\n\n int* result3 = func0(numbers3, 5, 5, &result3_size);\n\n int expected3[] = {0};\n\n assert(result3_size == 1 && result3[0] == expected3[0]);\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n printf(\"All tests passed!\\n\");\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%r13\nmov %esi,%r12d\nmov %edx,%ebx\nmov %rcx,%rbp\nmovslq %esi,%rdi\nshl $0x2,%rdi\ncallq 10d0 \nmovl $0x0,0x0(%rbp)\nmov 0x0(%r13),%esi\ncmp $0x1,%r12d\njle 1246 \nlea 0x4(%r13),%rdx\nlea -0x2(%r12),%ecx\nlea 0x8(%r13,%rcx,4),%r8\nmov $0x1,%ecx\njmp 1229 \nadd $0x1,%ecx\njmp 1220 \nmov (%rdi),%esi\nmov $0x1,%ecx\nadd $0x4,%rdx\ncmp %r8,%rdx\nje 124b \nmov %rdx,%rdi\ncmp %esi,(%rdx)\nje 1214 \ncmp %ecx,%ebx\njne 1219 \nmov 0x0(%rbp),%ecx\nmovslq %ecx,%r9\nmov %esi,(%rax,%r9,4)\nadd $0x1,%ecx\nmov %ecx,0x0(%rbp)\njmp 1219 \nmov $0x1,%ecx\ncmp %ecx,%ebx\nje 125a \nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nmov 0x0(%rbp),%edx\nmovslq %edx,%rcx\nmov %esi,(%rax,%rcx,4)\nadd $0x1,%edx\nmov %edx,0x0(%rbp)\njmp 124f \n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r13, rdi\nmov r12d, esi\nmov ebx, edx\nmov rbp, rcx\nmovsxd rdi, esi\nshl rdi, 2; size\ncall _malloc\nmov r8, rax\nmov dword ptr [rbp+0], 0\nmov ecx, [r13+0]\ncmp r12d, 1\njle short loc_1249\nlea rax, [r13+4]\nlea edx, [r12-2]\nlea rdi, [r13+rdx*4+8]\nmov edx, 1\njmp short loc_122C\nloc_1217:\nadd edx, 1\njmp short loc_1223\nloc_121C:\nmov ecx, [rsi]\nmov edx, 1\nloc_1223:\nadd rax, 4\ncmp rax, rdi\njz short loc_124E\nloc_122C:\nmov rsi, rax\ncmp [rax], ecx\njz short loc_1217\ncmp ebx, edx\njnz short loc_121C\nmov edx, [rbp+0]\nmovsxd r9, edx\nmov [r8+r9*4], ecx\nadd edx, 1\nmov [rbp+0], edx\njmp short loc_121C\nloc_1249:\nmov edx, 1\nloc_124E:\ncmp ebx, edx\njz short loc_1260\nloc_1252:\nmov rax, r8\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1260:\nmov eax, [rbp+0]\nmovsxd rdx, eax\nmov [r8+rdx*4], ecx\nadd eax, 1\nmov [rbp+0], eax\njmp short loc_1252", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2, int a3, int *a4)\n{\n _DWORD *v6; // r8\n int v7; // ecx\n int *v8; // rax\n int v9; // edx\n int v10; // edx\n int v12; // eax\n\n v6 = malloc(4LL * a2);\n *a4 = 0;\n v7 = *a1;\n if ( a2 <= 1 )\n {\n v9 = 1;\n }\n else\n {\n v8 = a1 + 1;\n v9 = 1;\n do\n {\n if ( *v8 == v7 )\n {\n ++v9;\n }\n else\n {\n if ( a3 == v9 )\n {\n v10 = *a4;\n v6[*a4] = v7;\n *a4 = v10 + 1;\n }\n v7 = *v8;\n v9 = 1;\n }\n ++v8;\n }\n while ( v8 != &a1[a2 - 2 + 2] );\n }\n if ( a3 == v9 )\n {\n v12 = *a4;\n v6[*a4] = v7;\n *a4 = v12 + 1;\n }\n return v6;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r13, rdi\nmov r12d, esi\nmov ebx, edx\nmov rbp, rcx\nmovsxd rdi, esi\nshl rdi, 2; size\ncall _malloc\nmov r8, rax\nmov dword ptr [rbp+0], 0\nmov ecx, [r13+0]\ncmp r12d, 1\njle short loc_1249\nlea rax, [r13+4]\nlea edx, [r12-2]\nlea rdi, [r13+rdx*4+8]\nmov edx, 1\njmp short loc_122C\nloc_1217:\nadd edx, 1\njmp short loc_1223\nloc_121C:\nmov ecx, [rsi]\nmov edx, 1\nloc_1223:\nadd rax, 4\ncmp rax, rdi\njz short loc_124E\nloc_122C:\nmov rsi, rax\ncmp [rax], ecx\njz short loc_1217\ncmp ebx, edx\njnz short loc_121C\nmov edx, [rbp+0]\nmovsxd r9, edx\nmov [r8+r9*4], ecx\nadd edx, 1\nmov [rbp+0], edx\njmp short loc_121C\nloc_1249:\nmov edx, 1\nloc_124E:\ncmp ebx, edx\njz short loc_1260\nloc_1252:\nmov rax, r8\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1260:\nmov eax, [rbp+0]\nmovsxd rdx, eax\nmov [r8+rdx*4], ecx\nadd eax, 1\nmov [rbp+0], eax\njmp short loc_1252", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11C9(int *a1, int a2, int a3, int *a4)\n{\n _DWORD *v6; // r8\n int v7; // ecx\n int *v8; // rax\n int v9; // edx\n int v10; // edx\n int v12; // eax\n\n v6 = malloc(4LL * a2);\n *a4 = 0;\n v7 = *a1;\n if ( a2 <= 1 )\n {\n v9 = 1;\n }\n else\n {\n v8 = a1 + 1;\n v9 = 1;\n do\n {\n if ( *v8 == v7 )\n {\n ++v9;\n }\n else\n {\n if ( a3 == v9 )\n {\n v10 = *a4;\n v6[*a4] = v7;\n *a4 = v10 + 1;\n }\n v7 = *v8;\n v9 = 1;\n }\n ++v8;\n }\n while ( v8 != &a1[a2 - 2 + 2] );\n }\n if ( a3 == v9 )\n {\n v12 = *a4;\n v6[*a4] = v7;\n *a4 = v12 + 1;\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11C9(int *a1, int a2, int a3, int *a4) {\n uint32_t *v6;\n int v7;\n int *v8;\n int v9;\n int v10;\n int v12;\n v6 = malloc(4LL * a2);\n *a4 = 0;\n v7 = *a1;\n if (a2 <= 1) {\n v9 = 1;\n } else {\n v8 = a1 + 1;\n v9 = 1;\n do {\n if (*v8 == v7) {\n ++v9;\n } else {\n if (a3 == v9) {\n v10 = *a4;\n v6[*a4] = v7;\n *a4 = v10 + 1;\n }\n v7 = *v8;\n v9 = 1;\n }\n ++v8;\n } while (v8 != &a1[a2 - 2 + 2]);\n }\n if (a3 == v9) {\n v12 = *a4;\n v6[*a4] = v7;\n *a4 = v12 + 1;\n }\n return v6;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2, int a3, int *a4) {\n uint32_t *v6;\n int v7;\n int *v8;\n int v9;\n int v10;\n int v12;\n v6 = malloc(4LL * a2);\n *a4 = 0;\n v7 = *a1;\n if (a2 <= 1) {\n v9 = 1;\n } else {\n v8 = a1 + 1;\n v9 = 1;\n do {\n if (*v8 == v7) {\n ++v9;\n } else {\n if (a3 == v9) {\n v10 = *a4;\n v6[*a4] = v7;\n *a4 = v10 + 1;\n }\n v7 = *v8;\n v9 = 1;\n }\n ++v8;\n } while (v8 != &a1[a2 - 2 + 2]);\n }\n if (a3 == v9) {\n v12 = *a4;\n v6[*a4] = v7;\n *a4 = v12 + 1;\n }\n return v6;\n}" + }, + { + "index": 898, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(const int numbers[], int length, int n, int* result_size) {\n int* result = malloc(length * sizeof(int));\n *result_size = 0;\n int count = 1;\n int current = numbers[0];\n for (int i = 1; i < length; i++) {\n if (numbers[i] == current) {\n count++;\n } else {\n if (count == n) {\n result[*result_size] = current;\n (*result_size)++;\n }\n current = numbers[i];\n count = 1;\n }\n }\n if (count == n) {\n result[*result_size] = current;\n (*result_size)++;\n }\n return result;\n}", + "test": "int main() {\n\n // Test Case 1\n\n int numbers1[] = {1, 1, 3, 4, 4, 5, 6, 7};\n\n int result1_size = 0;\n\n int* result1 = func0(numbers1, 8, 2, &result1_size);\n\n int expected1[] = {1, 4};\n\n assert(result1_size == 2 && result1[0] == expected1[0] && result1[1] == expected1[1]);\n\n \n\n // Test Case 2\n\n int numbers2[] = {0, 1, 2, 3, 4, 4, 4, 4, 5, 7};\n\n int result2_size = 0;\n\n int* result2 = func0(numbers2, 10, 4, &result2_size);\n\n int expected2[] = {4};\n\n assert(result2_size == 1 && result2[0] == expected2[0]);\n\n\n\n // Test Case 3\n\n int numbers3[] = {0, 0, 0, 0, 0};\n\n int result3_size = 0;\n\n int* result3 = func0(numbers3, 5, 5, &result3_size);\n\n int expected3[] = {0};\n\n assert(result3_size == 1 && result3[0] == expected3[0]);\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n printf(\"All tests passed!\\n\");\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov %rdi,%r13\nmovslq %esi,%rdi\npush %r12\nmov %rdi,%r12\nshl $0x2,%rdi\npush %rbp\nmov %rcx,%rbp\npush %rbx\nmov %edx,%ebx\nsub $0x8,%rsp\ncallq 10d0 \nmovl $0x0,0x0(%rbp)\nmov 0x0(%r13),%r9d\ncmp $0x1,%r12d\njle 1490 \nlea -0x2(%r12),%edx\nlea 0x4(%r13),%rdi\nmov $0x1,%r8d\nlea 0x8(%r13,%rdx,4),%r10\njmp 145a \nnopl 0x0(%rax)\ncmp %r8d,%ebx\njne 1448 \nmovslq 0x0(%rbp),%rcx\nmov %rcx,%rdx\nmov %r9d,(%rax,%rcx,4)\nadd $0x1,%edx\nmov %edx,0x0(%rbp)\nmov (%rdi),%esi\nadd $0x4,%rdi\nmov %esi,%r9d\nmov $0x1,%r8d\ncmp %r10,%rdi\nje 146e \nmov (%rdi),%esi\ncmp %r9d,%esi\njne 1430 \nadd $0x4,%rdi\nadd $0x1,%r8d\ncmp %r10,%rdi\njne 145a \ncmp %r8d,%ebx\njne 1484 \nmovslq 0x0(%rbp),%rcx\nmov %rcx,%rdx\nmov %r9d,(%rax,%rcx,4)\nadd $0x1,%edx\nmov %edx,0x0(%rbp)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nmov $0x1,%r8d\njmp 146e \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r13\nmov r13, rdi\nmovsxd rdi, esi\npush r12\nmov r12, rdi\nshl rdi, 2; size\npush rbp\nmov rbp, rcx\npush rbx\nmov ebx, edx\nsub rsp, 8\ncall _malloc\nmov dword ptr [rbp+0], 0\nmov esi, [r13+0]\nmov r8, rax\ncmp r12d, 1\njle short loc_1440\nlea edx, [r12-2]\nlea rax, [r13+4]\nmov ecx, 1\nlea rdi, [r13+rdx*4+8]\njmp short loc_1407\nloc_13E0:\ncmp ebx, ecx\njnz short loc_13F7\nmovsxd rcx, dword ptr [rbp+0]\nmov rdx, rcx\nmov [r8+rcx*4], esi\nadd edx, 1\nmov [rbp+0], edx\nmov edx, [rax]\nloc_13F7:\nadd rax, 4\nmov esi, edx\nmov ecx, 1\ncmp rax, rdi\njz short loc_1419\nloc_1407:\nmov edx, [rax]\ncmp edx, esi\njnz short loc_13E0\nadd rax, 4\nadd ecx, 1\ncmp rax, rdi\njnz short loc_1407\nloc_1419:\ncmp ebx, ecx\njnz short loc_142E\nmovsxd rdx, dword ptr [rbp+0]\nmov rax, rdx\nmov [r8+rdx*4], esi\nadd eax, 1\nmov [rbp+0], eax\nloc_142E:\nadd rsp, 8\nmov rax, r8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1440:\nmov ecx, 1\njmp short loc_1419", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2, int a3, int *a4)\n{\n _DWORD *v7; // rax\n int v8; // esi\n _DWORD *v9; // r8\n int *v10; // rax\n int v11; // ecx\n __int64 v12; // rdi\n int v13; // edx\n int v14; // edx\n int v15; // eax\n\n v7 = malloc(4LL * a2);\n *a4 = 0;\n v8 = *a1;\n v9 = v7;\n if ( a2 <= 1 )\n {\n v11 = 1;\n }\n else\n {\n v10 = a1 + 1;\n v11 = 1;\n v12 = (__int64)&a1[a2 - 2 + 2];\n do\n {\n while ( 1 )\n {\n v14 = *v10;\n if ( *v10 != v8 )\n break;\n ++v10;\n ++v11;\n if ( v10 == (int *)v12 )\n goto LABEL_8;\n }\n if ( a3 == v11 )\n {\n v13 = *a4;\n v9[*a4] = v8;\n *a4 = v13 + 1;\n v14 = *v10;\n }\n ++v10;\n v8 = v14;\n v11 = 1;\n }\n while ( v10 != (int *)v12 );\n }\nLABEL_8:\n if ( a3 == v11 )\n {\n v15 = *a4;\n v9[*a4] = v8;\n *a4 = v15 + 1;\n }\n return v9;\n}", + "ida_strip_asm": "sub_1390:\nendbr64\npush r13\nmov r13, rdi\nmovsxd rdi, esi\npush r12\nmov r12, rdi\nshl rdi, 2; size\npush rbp\nmov rbp, rcx\npush rbx\nmov ebx, edx\nsub rsp, 8\ncall _malloc\nmov dword ptr [rbp+0], 0\nmov esi, [r13+0]\nmov r8, rax\ncmp r12d, 1\njle short loc_1440\nlea edx, [r12-2]\nlea rax, [r13+4]\nmov ecx, 1\nlea rdi, [r13+rdx*4+8]\njmp short loc_1407\nloc_13E0:\ncmp ebx, ecx\njnz short loc_13F7\nmovsxd rcx, dword ptr [rbp+0]\nmov rdx, rcx\nmov [r8+rcx*4], esi\nadd edx, 1\nmov [rbp+0], edx\nmov edx, [rax]\nloc_13F7:\nadd rax, 4\nmov esi, edx\nmov ecx, 1\ncmp rax, rdi\njz short loc_1419\nloc_1407:\nmov edx, [rax]\ncmp edx, esi\njnz short loc_13E0\nadd rax, 4\nadd ecx, 1\ncmp rax, rdi\njnz short loc_1407\nloc_1419:\ncmp ebx, ecx\njnz short loc_142E\nmovsxd rdx, dword ptr [rbp+0]\nmov rax, rdx\nmov [r8+rdx*4], esi\nadd eax, 1\nmov [rbp+0], eax\nloc_142E:\nadd rsp, 8\nmov rax, r8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1440:\nmov ecx, 1\njmp short loc_1419", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1390(int *a1, int a2, int a3, int *a4)\n{\n _DWORD *v7; // rax\n int v8; // esi\n _DWORD *v9; // r8\n int *v10; // rax\n int v11; // ecx\n __int64 v12; // rdi\n int v13; // edx\n int v14; // edx\n int v15; // eax\n\n v7 = malloc(4LL * a2);\n *a4 = 0;\n v8 = *a1;\n v9 = v7;\n if ( a2 <= 1 )\n {\n v11 = 1;\n }\n else\n {\n v10 = a1 + 1;\n v11 = 1;\n v12 = (__int64)&a1[a2 - 2 + 2];\n do\n {\n while ( 1 )\n {\n v14 = *v10;\n if ( *v10 != v8 )\n break;\n ++v10;\n ++v11;\n if ( v10 == (int *)v12 )\n goto LABEL_8;\n }\n if ( a3 == v11 )\n {\n v13 = *a4;\n v9[*a4] = v8;\n *a4 = v13 + 1;\n v14 = *v10;\n }\n ++v10;\n v8 = v14;\n v11 = 1;\n }\n while ( v10 != (int *)v12 );\n }\nLABEL_8:\n if ( a3 == v11 )\n {\n v15 = *a4;\n v9[*a4] = v8;\n *a4 = v15 + 1;\n }\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1390(int *a1, int a2, int a3, int *a4) {\n uint32_t *v7;\n int v8;\n uint32_t *v9;\n int *v10;\n int v11;\n long long v12;\n int v13;\n int v14;\n int v15;\n v7 = malloc(4LL * a2);\n *a4 = 0;\n v8 = *a1;\n v9 = v7;\n if (a2 <= 1) {\n v11 = 1;\n } else {\n v10 = a1 + 1;\n v11 = 1;\n v12 = (long long)&a1[a2 - 2 + 2];\n do {\n while (1) {\n v14 = *v10;\n if (*v10 != v8) break;\n ++v10;\n ++v11;\n if (v10 == (int *)v12) goto LABEL_8;\n }\n if (a3 == v11) {\n v13 = *a4;\n v9[*a4] = v8;\n *a4 = v13 + 1;\n v14 = *v10;\n }\n ++v10;\n v8 = v14;\n v11 = 1;\n } while (v10 != (int *)v12);\n }\nLABEL_8:\n if (a3 == v11) {\n v15 = *a4;\n v9[*a4] = v8;\n *a4 = v15 + 1;\n }\n return v9;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2, int a3, int *a4) {\n uint32_t *v7;\n int v8;\n uint32_t *v9;\n int *v10;\n int v11;\n long long v12;\n int v13;\n int v14;\n int v15;\n v7 = malloc(4LL * a2);\n *a4 = 0;\n v8 = *a1;\n v9 = v7;\n if (a2 <= 1) {\n v11 = 1;\n } else {\n v10 = a1 + 1;\n v11 = 1;\n v12 = (long long)&a1[a2 - 2 + 2];\n do {\n while (1) {\n v14 = *v10;\n if (*v10 != v8) break;\n ++v10;\n ++v11;\n if (v10 == (int *)v12) goto LABEL_8;\n }\n if (a3 == v11) {\n v13 = *a4;\n v9[*a4] = v8;\n *a4 = v13 + 1;\n v14 = *v10;\n }\n ++v10;\n v8 = v14;\n v11 = 1;\n } while (v10 != (int *)v12);\n }\nLABEL_8:\n if (a3 == v11) {\n v15 = *a4;\n v9[*a4] = v8;\n *a4 = v15 + 1;\n }\n return v9;\n}" + }, + { + "index": 898, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(const int numbers[], int length, int n, int* result_size) {\n int* result = malloc(length * sizeof(int));\n *result_size = 0;\n int count = 1;\n int current = numbers[0];\n for (int i = 1; i < length; i++) {\n if (numbers[i] == current) {\n count++;\n } else {\n if (count == n) {\n result[*result_size] = current;\n (*result_size)++;\n }\n current = numbers[i];\n count = 1;\n }\n }\n if (count == n) {\n result[*result_size] = current;\n (*result_size)++;\n }\n return result;\n}", + "test": "int main() {\n\n // Test Case 1\n\n int numbers1[] = {1, 1, 3, 4, 4, 5, 6, 7};\n\n int result1_size = 0;\n\n int* result1 = func0(numbers1, 8, 2, &result1_size);\n\n int expected1[] = {1, 4};\n\n assert(result1_size == 2 && result1[0] == expected1[0] && result1[1] == expected1[1]);\n\n \n\n // Test Case 2\n\n int numbers2[] = {0, 1, 2, 3, 4, 4, 4, 4, 5, 7};\n\n int result2_size = 0;\n\n int* result2 = func0(numbers2, 10, 4, &result2_size);\n\n int expected2[] = {4};\n\n assert(result2_size == 1 && result2[0] == expected2[0]);\n\n\n\n // Test Case 3\n\n int numbers3[] = {0, 0, 0, 0, 0};\n\n int result3_size = 0;\n\n int* result3 = func0(numbers3, 5, 5, &result3_size);\n\n int expected3[] = {0};\n\n assert(result3_size == 1 && result3[0] == expected3[0]);\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n printf(\"All tests passed!\\n\");\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov %rdi,%r13\nmovslq %esi,%rdi\npush %r12\nmov %rdi,%r12\nshl $0x2,%rdi\npush %rbp\nmov %rcx,%rbp\npush %rbx\nmov %edx,%ebx\nsub $0x8,%rsp\ncallq 10d0 \nmovl $0x0,0x0(%rbp)\nmov 0x0(%r13),%r9d\ncmp $0x1,%r12d\njle 1440 \nlea -0x2(%r12),%edx\nlea 0x4(%r13),%rdi\nmov $0x1,%r8d\nlea 0x8(%r13,%rdx,4),%r10\njmp 140a \nnopl 0x0(%rax)\ncmp %r8d,%ebx\njne 13f8 \nmovslq 0x0(%rbp),%rcx\nmov %rcx,%rdx\nmov %r9d,(%rax,%rcx,4)\nadd $0x1,%edx\nmov %edx,0x0(%rbp)\nmov (%rdi),%esi\nadd $0x4,%rdi\nmov %esi,%r9d\nmov $0x1,%r8d\ncmp %r10,%rdi\nje 141e \nmov (%rdi),%esi\ncmp %r9d,%esi\njne 13e0 \nadd $0x4,%rdi\nadd $0x1,%r8d\ncmp %r10,%rdi\njne 140a \ncmp %r8d,%ebx\njne 1434 \nmovslq 0x0(%rbp),%rcx\nmov %rcx,%rdx\nmov %r9d,(%rax,%rcx,4)\nadd $0x1,%edx\nmov %edx,0x0(%rbp)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nmov $0x1,%r8d\njmp 141e \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r13\nmov r13, rdi\nmovsxd rdi, esi\npush r12\nmov r12, rdi\nshl rdi, 2; size\npush rbp\nmov rbp, rcx\npush rbx\nmov ebx, edx\nsub rsp, 8\ncall _malloc\nmov dword ptr [rbp+0], 0\nmov esi, [r13+0]\nmov r8, rax\ncmp r12d, 1\njle short loc_1440\nlea edx, [r12-2]\nlea rax, [r13+4]\nmov ecx, 1\nlea rdi, [r13+rdx*4+8]\njmp short loc_1407\nloc_13E0:\ncmp ebx, ecx\njnz short loc_13F7\nmovsxd rcx, dword ptr [rbp+0]\nmov rdx, rcx\nmov [r8+rcx*4], esi\nadd edx, 1\nmov [rbp+0], edx\nmov edx, [rax]\nloc_13F7:\nadd rax, 4\nmov esi, edx\nmov ecx, 1\ncmp rax, rdi\njz short loc_1419\nloc_1407:\nmov edx, [rax]\ncmp edx, esi\njnz short loc_13E0\nadd rax, 4\nadd ecx, 1\ncmp rax, rdi\njnz short loc_1407\nloc_1419:\ncmp ebx, ecx\njnz short loc_142E\nmovsxd rdx, dword ptr [rbp+0]\nmov rax, rdx\nmov [r8+rdx*4], esi\nadd eax, 1\nmov [rbp+0], eax\nloc_142E:\nadd rsp, 8\nmov rax, r8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1440:\nmov ecx, 1\njmp short loc_1419", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int a2, int a3, int *a4)\n{\n _DWORD *v7; // rax\n int v8; // esi\n _DWORD *v9; // r8\n int *v10; // rax\n int v11; // ecx\n __int64 v12; // rdi\n int v13; // edx\n int v14; // edx\n int v15; // eax\n\n v7 = malloc(4LL * a2);\n *a4 = 0;\n v8 = *a1;\n v9 = v7;\n if ( a2 <= 1 )\n {\n v11 = 1;\n }\n else\n {\n v10 = a1 + 1;\n v11 = 1;\n v12 = (__int64)&a1[a2 - 2 + 2];\n do\n {\n while ( 1 )\n {\n v14 = *v10;\n if ( *v10 != v8 )\n break;\n ++v10;\n ++v11;\n if ( v10 == (int *)v12 )\n goto LABEL_8;\n }\n if ( a3 == v11 )\n {\n v13 = *a4;\n v9[*a4] = v8;\n *a4 = v13 + 1;\n v14 = *v10;\n }\n ++v10;\n v8 = v14;\n v11 = 1;\n }\n while ( v10 != (int *)v12 );\n }\nLABEL_8:\n if ( a3 == v11 )\n {\n v15 = *a4;\n v9[*a4] = v8;\n *a4 = v15 + 1;\n }\n return v9;\n}", + "ida_strip_asm": "sub_1390:\nendbr64\npush r13\nmov r13, rdi\nmovsxd rdi, esi\npush r12\nmov r12, rdi\nshl rdi, 2; size\npush rbp\nmov rbp, rcx\npush rbx\nmov ebx, edx\nsub rsp, 8\ncall _malloc\nmov dword ptr [rbp+0], 0\nmov esi, [r13+0]\nmov r8, rax\ncmp r12d, 1\njle short loc_1440\nlea edx, [r12-2]\nlea rax, [r13+4]\nmov ecx, 1\nlea rdi, [r13+rdx*4+8]\njmp short loc_1407\nloc_13E0:\ncmp ebx, ecx\njnz short loc_13F7\nmovsxd rcx, dword ptr [rbp+0]\nmov rdx, rcx\nmov [r8+rcx*4], esi\nadd edx, 1\nmov [rbp+0], edx\nmov edx, [rax]\nloc_13F7:\nadd rax, 4\nmov esi, edx\nmov ecx, 1\ncmp rax, rdi\njz short loc_1419\nloc_1407:\nmov edx, [rax]\ncmp edx, esi\njnz short loc_13E0\nadd rax, 4\nadd ecx, 1\ncmp rax, rdi\njnz short loc_1407\nloc_1419:\ncmp ebx, ecx\njnz short loc_142E\nmovsxd rdx, dword ptr [rbp+0]\nmov rax, rdx\nmov [r8+rdx*4], esi\nadd eax, 1\nmov [rbp+0], eax\nloc_142E:\nadd rsp, 8\nmov rax, r8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1440:\nmov ecx, 1\njmp short loc_1419", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1390(int *a1, int a2, int a3, int *a4)\n{\n _DWORD *v7; // rax\n int v8; // esi\n _DWORD *v9; // r8\n int *v10; // rax\n int v11; // ecx\n __int64 v12; // rdi\n int v13; // edx\n int v14; // edx\n int v15; // eax\n\n v7 = malloc(4LL * a2);\n *a4 = 0;\n v8 = *a1;\n v9 = v7;\n if ( a2 <= 1 )\n {\n v11 = 1;\n }\n else\n {\n v10 = a1 + 1;\n v11 = 1;\n v12 = (__int64)&a1[a2 - 2 + 2];\n do\n {\n while ( 1 )\n {\n v14 = *v10;\n if ( *v10 != v8 )\n break;\n ++v10;\n ++v11;\n if ( v10 == (int *)v12 )\n goto LABEL_8;\n }\n if ( a3 == v11 )\n {\n v13 = *a4;\n v9[*a4] = v8;\n *a4 = v13 + 1;\n v14 = *v10;\n }\n ++v10;\n v8 = v14;\n v11 = 1;\n }\n while ( v10 != (int *)v12 );\n }\nLABEL_8:\n if ( a3 == v11 )\n {\n v15 = *a4;\n v9[*a4] = v8;\n *a4 = v15 + 1;\n }\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1390(int *a1, int a2, int a3, int *a4) {\n uint32_t *v7;\n int v8;\n uint32_t *v9;\n int *v10;\n int v11;\n long long v12;\n int v13;\n int v14;\n int v15;\n v7 = malloc(4LL * a2);\n *a4 = 0;\n v8 = *a1;\n v9 = v7;\n if (a2 <= 1) {\n v11 = 1;\n } else {\n v10 = a1 + 1;\n v11 = 1;\n v12 = (long long)&a1[a2 - 2 + 2];\n do {\n while (1) {\n v14 = *v10;\n if (*v10 != v8) break;\n ++v10;\n ++v11;\n if (v10 == (int *)v12) goto LABEL_8;\n }\n if (a3 == v11) {\n v13 = *a4;\n v9[*a4] = v8;\n *a4 = v13 + 1;\n v14 = *v10;\n }\n ++v10;\n v8 = v14;\n v11 = 1;\n } while (v10 != (int *)v12);\n }\nLABEL_8:\n if (a3 == v11) {\n v15 = *a4;\n v9[*a4] = v8;\n *a4 = v15 + 1;\n }\n return v9;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int a2, int a3, int *a4) {\n uint32_t *v7;\n int v8;\n uint32_t *v9;\n int *v10;\n int v11;\n long long v12;\n int v13;\n int v14;\n int v15;\n v7 = malloc(4LL * a2);\n *a4 = 0;\n v8 = *a1;\n v9 = v7;\n if (a2 <= 1) {\n v11 = 1;\n } else {\n v10 = a1 + 1;\n v11 = 1;\n v12 = (long long)&a1[a2 - 2 + 2];\n do {\n while (1) {\n v14 = *v10;\n if (*v10 != v8) break;\n ++v10;\n ++v11;\n if (v10 == (int *)v12) goto LABEL_8;\n }\n if (a3 == v11) {\n v13 = *a4;\n v9[*a4] = v8;\n *a4 = v13 + 1;\n v14 = *v10;\n }\n ++v10;\n v8 = v14;\n v11 = 1;\n } while (v10 != (int *)v12);\n }\nLABEL_8:\n if (a3 == v11) {\n v15 = *a4;\n v9[*a4] = v8;\n *a4 = v15 + 1;\n }\n return v9;\n}" + }, + { + "index": 899, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int arr[], int n) {\n int g = 0;\n for (int i = 1; i < n; i++) {\n if ((arr[i] - arr[i - 1] > 0) && (g == 1)) {\n return false;\n }\n if ((arr[i] - arr[i] < 0)) {\n g = 1;\n }\n }\n return true;\n}", + "test": "int main() {\n\n assert(func0((int[]){3,2,1,2,3,4}, 6) == true);\n\n assert(func0((int[]){2,1,4,5,1}, 5) == true);\n\n assert(func0((int[]){1,2,2,1,2,3}, 6) == true);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x4(%rbp)\nmovl $0x1,-0x8(%rbp)\njmp 11cd \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x8(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\nsub %eax,%edx\nmov %edx,%eax\ntest %eax,%eax\njle 11c9 \ncmpl $0x1,-0x4(%rbp)\njne 11c9 \nmov $0x0,%eax\njmp 11da \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1188 \nmov $0x1,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 0\nmov [rbp+var_8], 1\njmp short loc_11CB\nloc_1188:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nshl rax, 2\nlea rcx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nsub edx, eax\ntest edx, edx\njle short loc_11C7\ncmp [rbp+var_4], 1\njnz short loc_11C7\nmov eax, 0\njmp short loc_11D8\nloc_11C7:\nadd [rbp+var_8], 1\nloc_11CB:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, 1\nloc_11D8:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+14h] [rbp-8h]\n\n for ( i = 1; i < a2; ++i )\n ;\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 0\nmov [rbp+var_8], 1\njmp short loc_11CB\nloc_1188:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nshl rax, 2\nlea rcx, [rax-4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nsub edx, eax\ntest edx, edx\njle short loc_11C7\ncmp [rbp+var_4], 1\njnz short loc_11C7\nmov eax, 0\njmp short loc_11D8\nloc_11C7:\nadd [rbp+var_8], 1\nloc_11CB:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, 1\nloc_11D8:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n int i; // [rsp+14h] [rbp-8h]\n\n for ( i = 1; i < a2; ++i )\n ;\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n int i;\n for (i = 1; i < a2; ++i)\n ;\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int i;\n for (i = 1; i < a2; ++i)\n ;\n return 1LL;\n}" + }, + { + "index": 900, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char *string) {\n regex_t regex;\n int result;\n result = regcomp(®ex, \"^5\", 0);\n if (result) {\n fprintf(stderr, \"Could not compile regex\\n\");\n return false;\n }\n result = regexec(®ex, string, 0, NULL, 0);\n regfree(®ex);\n if (result == 0) {\n return true;\n } else {\n return false;\n }\n}", + "test": "int main() {\n\n assert(func0(\"5-2345861\") == true);\n\n assert(func0(\"6-2345861\") == false);\n\n assert(func0(\"78910\") == false);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x70,%rsp\nmov %rdi,-0x68(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea -0x50(%rbp),%rax\nmov $0x0,%edx\nlea 0xdf0(%rip),%rsi\nmov %rax,%rdi\ncallq 10d0 \nmov %eax,-0x54(%rbp)\ncmpl $0x0,-0x54(%rbp)\nje 1250 \nmov 0x2df0(%rip),%rax\nmov %rax,%rcx\nmov $0x18,%edx\nmov $0x1,%esi\nlea 0xdc7(%rip),%rdi\ncallq 10f0 \nmov $0x0,%eax\njmp 1291 \nmov -0x68(%rbp),%rsi\nlea -0x50(%rbp),%rax\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rax,%rdi\ncallq 10e0 \nmov %eax,-0x54(%rbp)\nlea -0x50(%rbp),%rax\nmov %rax,%rdi\ncallq 10a0 \ncmpl $0x0,-0x54(%rbp)\njne 128c \nmov $0x1,%eax\njmp 1291 \nmov $0x0,%eax\nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 12a5 \ncallq 10b0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [rbp+preg]\nmov edx, 0; cflags\nlea rcx, pattern; \"^5\"\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+var_54], eax\ncmp [rbp+var_54], 0\njz short loc_1256\nmov rax, cs:__bss_start\nmov rcx, rax; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rax, aCouldNotCompil; \"Could not compile regex\\n\"\nmov rdi, rax; ptr\ncall _fwrite\nmov eax, 0\njmp short loc_1297\nloc_1256:\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_54], eax\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\ncmp [rbp+var_54], 0\njnz short loc_1292\nmov eax, 1\njmp short loc_1297\nloc_1292:\nmov eax, 0\nloc_1297:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12AB\ncall ___stack_chk_fail\nlocret_12AB:\nleave\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(const char *a1)\n{\n int v2; // [rsp+1Ch] [rbp-54h]\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n unsigned __int64 v4; // [rsp+68h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"^5\", 0) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n return 0LL;\n }\n else\n {\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n return v2 == 0;\n }\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [rbp+preg]\nmov edx, 0; cflags\nlea rcx, pattern; \"^5\"\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+var_54], eax\ncmp [rbp+var_54], 0\njz short loc_1256\nmov rax, cs:stderr\nmov rcx, rax; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rax, aCouldNotCompil; \"Could not compile regex\\n\"\nmov rdi, rax; ptr\ncall _fwrite\nmov eax, 0\njmp short loc_1297\nloc_1256:\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_54], eax\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\ncmp [rbp+var_54], 0\njnz short loc_1292\nmov eax, 1\njmp short loc_1297\nloc_1292:\nmov eax, 0\nloc_1297:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12AB\ncall ___stack_chk_fail\nlocret_12AB:\nleave\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_11E9(const char *a1)\n{\n int v2; // [rsp+1Ch] [rbp-54h]\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n unsigned __int64 v4; // [rsp+68h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"^5\", 0) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n return 0LL;\n }\n else\n {\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n return v2 == 0;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_11E9(const char *a1) {\n int v2;\n regex_t preg;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n if (regcomp(&preg, \"^5\", 0)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n return 0LL;\n } else {\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n return v2 == 0;\n }\n}", + "ida_pseudo_norm": "uint8_t func0(const char *a1) {\n int v2;\n regex_t preg;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n if (regcomp(&preg, \"^5\", 0)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n return 0LL;\n } else {\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n return v2 == 0;\n }\n}" + }, + { + "index": 900, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char *string) {\n regex_t regex;\n int result;\n result = regcomp(®ex, \"^5\", 0);\n if (result) {\n fprintf(stderr, \"Could not compile regex\\n\");\n return false;\n }\n result = regexec(®ex, string, 0, NULL, 0);\n regfree(®ex);\n if (result == 0) {\n return true;\n } else {\n return false;\n }\n}", + "test": "int main() {\n\n assert(func0(\"5-2345861\") == true);\n\n assert(func0(\"6-2345861\") == false);\n\n assert(func0(\"78910\") == false);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x58,%rsp\nmov %rdi,%rbx\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nmov $0x0,%edx\nlea 0xdef(%rip),%rsi\ncallq 10d0 \ntest %eax,%eax\njne 1262 \nmov %rsp,%rbp\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rbx,%rsi\nmov %rbp,%rdi\ncallq 10e0 \nmov %eax,%ebx\nmov %rbp,%rdi\ncallq 10a0 \ntest %ebx,%ebx\nsete %al\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 1286 \nadd $0x58,%rsp\npop %rbx\npop %rbp\nretq\nmov 0x2db7(%rip),%rcx\nmov $0x18,%edx\nmov $0x1,%esi\nlea 0xd8d(%rip),%rdi\ncallq 10f0 \nmov $0x0,%eax\njmp 124b \ncallq 10b0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+68h+var_20], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 0; cflags\nlea rsi, pattern; \"^5\"\ncall _regcomp\ntest eax, eax\njnz short loc_1262\nmov rbp, rsp\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov ebx, eax\nmov rdi, rbp; preg\ncall _regfree\ntest ebx, ebx\nsetz al\nloc_124B:\nmov rdx, [rsp+68h+var_20]\nsub rdx, fs:28h\njnz short loc_1286\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1262:\nmov rcx, cs:__bss_start; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nmov eax, 0\njmp short loc_124B\nloc_1286:\ncall ___stack_chk_fail", + "ida_pseudo": "bool __fastcall func0(char *string)\n{\n int v1; // ebx\n regex_t v3; // [rsp+0h] [rbp-68h] BYREF\n unsigned __int64 v4; // [rsp+48h] [rbp-20h]\n\n v4 = __readfsqword(0x28u);\n if ( regcomp(&v3, \"^5\", 0) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n return 0;\n }\n else\n {\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n regfree(&v3);\n return v1 == 0;\n }\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+68h+var_20], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 0; cflags\nlea rsi, pattern; \"^5\"\ncall _regcomp\ntest eax, eax\njnz short loc_1262\nmov rbp, rsp\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov ebx, eax\nmov rdi, rbp; preg\ncall _regfree\ntest ebx, ebx\nsetz al\nloc_124B:\nmov rdx, [rsp+68h+var_20]\nsub rdx, fs:28h\njnz short loc_1286\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1262:\nmov rcx, cs:stderr; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nmov eax, 0\njmp short loc_124B\nloc_1286:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "bool __fastcall sub_11E9(char *string)\n{\n int v1; // ebx\n regex_t v3; // [rsp+0h] [rbp-68h] BYREF\n unsigned __int64 v4; // [rsp+48h] [rbp-20h]\n\n v4 = __readfsqword(0x28u);\n if ( regcomp(&v3, \"^5\", 0) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n return 0;\n }\n else\n {\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n regfree(&v3);\n return v1 == 0;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_11E9(char *string) {\n int v1;\n regex_t v3;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n if (regcomp(&v3, \"^5\", 0)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n return 0;\n } else {\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n regfree(&v3);\n return v1 == 0;\n }\n}", + "ida_pseudo_norm": "bool func0(char *string) {\n int v1;\n regex_t v3;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n if (regcomp(&v3, \"^5\", 0)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n return 0;\n } else {\n v1 = regexec(&v3, string, 0LL, 0LL, 0);\n regfree(&v3);\n return v1 == 0;\n }\n}" + }, + { + "index": 900, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char *string) {\n regex_t regex;\n int result;\n result = regcomp(®ex, \"^5\", 0);\n if (result) {\n fprintf(stderr, \"Could not compile regex\\n\");\n return false;\n }\n result = regexec(®ex, string, 0, NULL, 0);\n regfree(®ex);\n if (result == 0) {\n return true;\n } else {\n return false;\n }\n}", + "test": "int main() {\n\n assert(func0(\"5-2345861\") == true);\n\n assert(func0(\"6-2345861\") == false);\n\n assert(func0(\"78910\") == false);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nxor %edx,%edx\nlea 0xd65(%rip),%rsi\npush %rbp\nmov %rdi,%rbp\nsub $0x58,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%r12\nmov %r12,%rdi\ncallq 10d0 \ntest %eax,%eax\njne 1300 \nxor %r8d,%r8d\nxor %ecx,%ecx\nxor %edx,%edx\nmov %rbp,%rsi\nmov %r12,%rdi\ncallq 10e0 \nmov %r12,%rdi\nmov %eax,%ebp\ncallq 10a0 \ntest %ebp,%ebp\nsete %al\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 1321 \nadd $0x58,%rsp\npop %rbp\npop %r12\nretq\nmov 0x2d19(%rip),%rcx\nmov $0x18,%edx\nmov $0x1,%esi\nlea 0xcef(%rip),%rdi\ncallq 10f0 \nxor %eax,%eax\njmp 12e7 \ncallq 10b0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nxor edx, edx; cflags\nlea rsi, pattern; \"^5\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njnz short loc_1300\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nsetz al\nloc_12E6:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_1321\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1300:\nmov rcx, cs:__bss_start; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nxor eax, eax\njmp short loc_12E6\nloc_1321:\ncall ___stack_chk_fail", + "ida_pseudo": "bool __fastcall func0(char *string)\n{\n int v1; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n if ( regcomp(&_0, \"^5\", 0) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n return 0;\n }\n else\n {\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 0;\n }\n}", + "ida_strip_asm": "sub_1290:\nendbr64\npush rbp\nxor edx, edx; cflags\nlea rsi, pattern; \"^5\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njnz short loc_1300\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nsetz al\nloc_12E6:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_1321\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1300:\nmov rcx, cs:stderr; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nxor eax, eax\njmp short loc_12E6\nloc_1321:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "bool __fastcall sub_1290(char *string)\n{\n int v1; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n if ( regcomp(&_0, \"^5\", 0) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n return 0;\n }\n else\n {\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 0;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_1290(char *string) {\n int v1;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n if (regcomp(&_0, \"^5\", 0)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n return 0;\n } else {\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 0;\n }\n}", + "ida_pseudo_norm": "bool func0(char *string) {\n int v1;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n if (regcomp(&_0, \"^5\", 0)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n return 0;\n } else {\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 0;\n }\n}" + }, + { + "index": 900, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char *string) {\n regex_t regex;\n int result;\n result = regcomp(®ex, \"^5\", 0);\n if (result) {\n fprintf(stderr, \"Could not compile regex\\n\");\n return false;\n }\n result = regexec(®ex, string, 0, NULL, 0);\n regfree(®ex);\n if (result == 0) {\n return true;\n } else {\n return false;\n }\n}", + "test": "int main() {\n\n assert(func0(\"5-2345861\") == true);\n\n assert(func0(\"6-2345861\") == false);\n\n assert(func0(\"78910\") == false);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nxor %edx,%edx\nlea 0xd65(%rip),%rsi\npush %rbp\nmov %rdi,%rbp\nsub $0x58,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%r12\nmov %r12,%rdi\ncallq 10d0 \ntest %eax,%eax\njne 1300 \nxor %r8d,%r8d\nxor %ecx,%ecx\nxor %edx,%edx\nmov %rbp,%rsi\nmov %r12,%rdi\ncallq 10e0 \nmov %r12,%rdi\nmov %eax,%ebp\ncallq 10a0 \ntest %ebp,%ebp\nsete %al\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 1321 \nadd $0x58,%rsp\npop %rbp\npop %r12\nretq\nmov 0x2d19(%rip),%rcx\nmov $0x18,%edx\nmov $0x1,%esi\nlea 0xcef(%rip),%rdi\ncallq 10f0 \nxor %eax,%eax\njmp 12e7 \ncallq 10b0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nxor edx, edx; cflags\nlea rsi, pattern; \"^5\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njnz short loc_1300\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nsetz al\nloc_12E6:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_1321\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1300:\nmov rcx, cs:__bss_start; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nxor eax, eax\njmp short loc_12E6\nloc_1321:\ncall ___stack_chk_fail", + "ida_pseudo": "bool __fastcall func0(char *string)\n{\n int v1; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n if ( regcomp(&_0, \"^5\", 0) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, _bss_start);\n return 0;\n }\n else\n {\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 0;\n }\n}", + "ida_strip_asm": "sub_1290:\nendbr64\npush rbp\nxor edx, edx; cflags\nlea rsi, pattern; \"^5\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\ntest eax, eax\njnz short loc_1300\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nsetz al\nloc_12E6:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_1321\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1300:\nmov rcx, cs:stderr; s\nmov edx, 18h; n\nmov esi, 1; size\nlea rdi, aCouldNotCompil; \"Could not compile regex\\n\"\ncall _fwrite\nxor eax, eax\njmp short loc_12E6\nloc_1321:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "bool __fastcall sub_1290(char *string)\n{\n int v1; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n if ( regcomp(&_0, \"^5\", 0) )\n {\n fwrite(\"Could not compile regex\\n\", 1uLL, 0x18uLL, stderr);\n return 0;\n }\n else\n {\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 0;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_1290(char *string) {\n int v1;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n if (regcomp(&_0, \"^5\", 0)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, stderr);\n return 0;\n } else {\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 0;\n }\n}", + "ida_pseudo_norm": "bool func0(char *string) {\n int v1;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n if (regcomp(&_0, \"^5\", 0)) {\n fwrite(\"Could not compile regex\\n\", 1uLL, 24uLL, _bss_start);\n return 0;\n } else {\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 0;\n }\n}" + }, + { + "index": 901, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n <= 2) {\n return n;\n }\n int i = n * 2;\n int factors[100];\n int factor_count = 0;\n for (int number = n; number > 1; number--) {\n if (number * 2 > n) {\n factors[factor_count++] = number;\n }\n }\n while (1) {\n for (int j = 0; j < factor_count; j++) {\n if (i % factors[j] != 0) {\n i += n;\n break;\n }\n if (j == factor_count - 1 && i % factors[j] == 0) {\n return i;\n }\n }\n }\n}", + "test": "int main() {\n\n assert(func0(13) == 360360);\n\n assert(func0(2) == 2);\n\n assert(func0(1) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x1c0,%rsp\nmov %edi,-0x1b4(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\ncmpl $0x2,-0x1b4(%rbp)\njg 11a1 \nmov -0x1b4(%rbp),%eax\njmpq 128e \nmov -0x1b4(%rbp),%eax\nadd %eax,%eax\nmov %eax,-0x1b0(%rbp)\nmovl $0x0,-0x1ac(%rbp)\nmov -0x1b4(%rbp),%eax\nmov %eax,-0x1a8(%rbp)\njmp 11fc \nmov -0x1a8(%rbp),%eax\nadd %eax,%eax\ncmp %eax,-0x1b4(%rbp)\njge 11f5 \nmov -0x1ac(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x1ac(%rbp)\ncltq\nmov -0x1a8(%rbp),%edx\nmov %edx,-0x1a0(%rbp,%rax,4)\nsubl $0x1,-0x1a8(%rbp)\ncmpl $0x1,-0x1a8(%rbp)\njg 11c7 \nmovl $0x0,-0x1a4(%rbp)\njmp 127b \nmov -0x1a4(%rbp),%eax\ncltq\nmov -0x1a0(%rbp,%rax,4),%ecx\nmov -0x1b0(%rbp),%eax\ncltd\nidiv %ecx\nmov %edx,%eax\ntest %eax,%eax\nje 123d \nmov -0x1b4(%rbp),%eax\nadd %eax,-0x1b0(%rbp)\njmp 1289 \nmov -0x1ac(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x1a4(%rbp)\njne 1274 \nmov -0x1a4(%rbp),%eax\ncltq\nmov -0x1a0(%rbp,%rax,4),%ecx\nmov -0x1b0(%rbp),%eax\ncltd\nidiv %ecx\nmov %edx,%eax\ntest %eax,%eax\njne 1274 \nmov -0x1b0(%rbp),%eax\njmp 128e \naddl $0x1,-0x1a4(%rbp)\nmov -0x1a4(%rbp),%eax\ncmp -0x1ac(%rbp),%eax\njl 1211 \njmpq 1205 \nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 12a2 \ncallq 1060 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 1C0h\nmov [rbp+var_1B4], edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\ncmp [rbp+var_1B4], 2\njg short loc_11A1\nmov eax, [rbp+var_1B4]\njmp loc_1292\nloc_11A1:\nmov eax, [rbp+var_1B4]\nadd eax, eax\nmov [rbp+var_1B0], eax\nmov [rbp+var_1AC], 0\nmov eax, [rbp+var_1B4]\nmov [rbp+var_1A8], eax\njmp short loc_11FC\nloc_11C7:\nmov eax, [rbp+var_1A8]\nadd eax, eax\ncmp [rbp+var_1B4], eax\njge short loc_11F5\nmov eax, [rbp+var_1AC]\nlea edx, [rax+1]\nmov [rbp+var_1AC], edx\ncdqe\nmov edx, [rbp+var_1A8]\nmov [rbp+rax*4+var_1A0], edx\nloc_11F5:\nsub [rbp+var_1A8], 1\nloc_11FC:\ncmp [rbp+var_1A8], 1\njg short loc_11C7\nloc_1205:\nmov [rbp+var_1A4], 0\njmp short loc_127F\nloc_1211:\nmov eax, [rbp+var_1A4]\ncdqe\nmov esi, [rbp+rax*4+var_1A0]\nmov eax, [rbp+var_1B0]\ncdq\nidiv esi\nmov ecx, edx\nmov eax, ecx\ntest eax, eax\njz short loc_123F\nmov eax, [rbp+var_1B4]\nadd [rbp+var_1B0], eax\njmp short loc_128D\nloc_123F:\nmov eax, [rbp+var_1AC]\nsub eax, 1\ncmp [rbp+var_1A4], eax\njnz short loc_1278\nmov eax, [rbp+var_1A4]\ncdqe\nmov edi, [rbp+rax*4+var_1A0]\nmov eax, [rbp+var_1B0]\ncdq\nidiv edi\nmov ecx, edx\nmov eax, ecx\ntest eax, eax\njnz short loc_1278\nmov eax, [rbp+var_1B0]\njmp short loc_1292\nloc_1278:\nadd [rbp+var_1A4], 1\nloc_127F:\nmov eax, [rbp+var_1A4]\ncmp eax, [rbp+var_1AC]\njl short loc_1211\nloc_128D:\njmp loc_1205\nloc_1292:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12A6\ncall ___stack_chk_fail\nlocret_12A6:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v2; // eax\n int v3; // [rsp+10h] [rbp-1B0h]\n int v4; // [rsp+14h] [rbp-1ACh]\n int i; // [rsp+18h] [rbp-1A8h]\n int j; // [rsp+1Ch] [rbp-1A4h]\n _DWORD v7[102]; // [rsp+20h] [rbp-1A0h]\n unsigned __int64 v8; // [rsp+1B8h] [rbp-8h]\n\n v8 = __readfsqword(0x28u);\n if ( a1 <= 2 )\n return (unsigned int)a1;\n v3 = 2 * a1;\n v4 = 0;\n for ( i = a1; i > 1; --i )\n {\n if ( a1 < 2 * i )\n {\n v2 = v4++;\n v7[v2] = i;\n }\n }\nLABEL_8:\n for ( j = 0; ; ++j )\n {\n if ( j >= v4 )\n goto LABEL_8;\n if ( v3 % v7[j] )\n {\n v3 += a1;\n goto LABEL_8;\n }\n if ( j == v4 - 1 && !(v3 % v7[j]) )\n break;\n }\n return (unsigned int)v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 1C0h\nmov [rbp+var_1B4], edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\ncmp [rbp+var_1B4], 2\njg short loc_11A1\nmov eax, [rbp+var_1B4]\njmp loc_1292\nloc_11A1:\nmov eax, [rbp+var_1B4]\nadd eax, eax\nmov [rbp+var_1B0], eax\nmov [rbp+var_1AC], 0\nmov eax, [rbp+var_1B4]\nmov [rbp+var_1A8], eax\njmp short loc_11FC\nloc_11C7:\nmov eax, [rbp+var_1A8]\nadd eax, eax\ncmp [rbp+var_1B4], eax\njge short loc_11F5\nmov eax, [rbp+var_1AC]\nlea edx, [rax+1]\nmov [rbp+var_1AC], edx\ncdqe\nmov edx, [rbp+var_1A8]\nmov [rbp+rax*4+var_1A0], edx\nloc_11F5:\nsub [rbp+var_1A8], 1\nloc_11FC:\ncmp [rbp+var_1A8], 1\njg short loc_11C7\nloc_1205:\nmov [rbp+var_1A4], 0\njmp short loc_127F\nloc_1211:\nmov eax, [rbp+var_1A4]\ncdqe\nmov esi, [rbp+rax*4+var_1A0]\nmov eax, [rbp+var_1B0]\ncdq\nidiv esi\nmov ecx, edx\nmov eax, ecx\ntest eax, eax\njz short loc_123F\nmov eax, [rbp+var_1B4]\nadd [rbp+var_1B0], eax\njmp short loc_128D\nloc_123F:\nmov eax, [rbp+var_1AC]\nsub eax, 1\ncmp [rbp+var_1A4], eax\njnz short loc_1278\nmov eax, [rbp+var_1A4]\ncdqe\nmov edi, [rbp+rax*4+var_1A0]\nmov eax, [rbp+var_1B0]\ncdq\nidiv edi\nmov ecx, edx\nmov eax, ecx\ntest eax, eax\njnz short loc_1278\nmov eax, [rbp+var_1B0]\njmp short loc_1292\nloc_1278:\nadd [rbp+var_1A4], 1\nloc_127F:\nmov eax, [rbp+var_1A4]\ncmp eax, [rbp+var_1AC]\njl short loc_1211\nloc_128D:\njmp loc_1205\nloc_1292:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12A6\ncall ___stack_chk_fail\nlocret_12A6:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n int v2; // eax\n int v3; // [rsp+10h] [rbp-1B0h]\n int v4; // [rsp+14h] [rbp-1ACh]\n int i; // [rsp+18h] [rbp-1A8h]\n int j; // [rsp+1Ch] [rbp-1A4h]\n _DWORD v7[102]; // [rsp+20h] [rbp-1A0h]\n unsigned __int64 v8; // [rsp+1B8h] [rbp-8h]\n\n v8 = __readfsqword(0x28u);\n if ( a1 <= 2 )\n return (unsigned int)a1;\n v3 = 2 * a1;\n v4 = 0;\n for ( i = a1; i > 1; --i )\n {\n if ( a1 < 2 * i )\n {\n v2 = v4++;\n v7[v2] = i;\n }\n }\nLABEL_8:\n for ( j = 0; ; ++j )\n {\n if ( j >= v4 )\n goto LABEL_8;\n if ( v3 % v7[j] )\n {\n v3 += a1;\n goto LABEL_8;\n }\n if ( j == v4 - 1 && !(v3 % v7[j]) )\n break;\n }\n return (unsigned int)v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n int v2;\n int v3;\n int v4;\n int i;\n int j;\n uint32_t v7[102];\n unsigned long long v8;\n v8 = __readfsqword(40u);\n if (a1 <= 2) return (unsigned int)a1;\n v3 = 2 * a1;\n v4 = 0;\n for (i = a1; i > 1; --i) {\n if (a1 < 2 * i) {\n v2 = v4++;\n v7[v2] = i;\n }\n }\nLABEL_8:\n for (j = 0;; ++j) {\n if (j >= v4) goto LABEL_8;\n if (v3 % v7[j]) {\n v3 += a1;\n goto LABEL_8;\n }\n if (j == v4 - 1 && !(v3 % v7[j])) break;\n }\n return (unsigned int)v3;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v2;\n int v3;\n int v4;\n int i;\n int j;\n uint32_t v7[102];\n unsigned long long v8;\n v8 = __readfsqword(40u);\n if (a1 <= 2) return (unsigned int)a1;\n v3 = 2 * a1;\n v4 = 0;\n for (i = a1; i > 1; --i) {\n if (a1 < 2 * i) {\n v2 = v4++;\n v7[v2] = i;\n }\n }\nLABEL_8:\n for (j = 0;; ++j) {\n if (j >= v4) goto LABEL_8;\n if (v3 % v7[j]) {\n v3 += a1;\n goto LABEL_8;\n }\n if (j == v4 - 1 && !(v3 % v7[j])) break;\n }\n return (unsigned int)v3;\n}" + }, + { + "index": 901, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n <= 2) {\n return n;\n }\n int i = n * 2;\n int factors[100];\n int factor_count = 0;\n for (int number = n; number > 1; number--) {\n if (number * 2 > n) {\n factors[factor_count++] = number;\n }\n }\n while (1) {\n for (int j = 0; j < factor_count; j++) {\n if (i % factors[j] != 0) {\n i += n;\n break;\n }\n if (j == factor_count - 1 && i % factors[j] == 0) {\n return i;\n }\n }\n }\n}", + "test": "int main() {\n\n assert(func0(13) == 360360);\n\n assert(func0(2) == 2);\n\n assert(func0(1) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x1a8,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x198(%rsp)\nxor %eax,%eax\ncmp $0x2,%edi\njle 11ee \nlea (%rdi,%rdi,1),%esi\nmov %edi,%eax\nmov $0x0,%r10d\njmp 11a1 \nsub $0x1,%eax\ncmp $0x1,%eax\nje 11b4 \nlea (%rax,%rax,1),%edx\ncmp %edx,%edi\njge 1199 \nmovslq %r10d,%rdx\nmov %eax,(%rsp,%rdx,4)\nlea 0x1(%r10),%r10d\njmp 1199 \nmov %rsp,%r11\nlea -0x1(%r10),%r8d\nshl $0x2,%r8\nlea 0x4(%rsp,%r8,1),%r9\nadd %r11,%r8\njmp 11cb \nadd %edi,%esi\ntest %r10d,%r10d\njle 11cb \nmov %r11,%rcx\nmov %esi,%eax\ncltd\nidivl (%rcx)\ntest %edx,%edx\njne 11c9 \ncmp %r8,%rcx\nje 11ec \nadd $0x4,%rcx\ncmp %r9,%rcx\njne 11d3 \njmp 11cb \nmov %esi,%edi\nmov 0x198(%rsp),%rax\nxor %fs:0x28,%rax\njne 120b \nmov %edi,%eax\nadd $0x1a8,%rsp\nretq\ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 1A8h\nmov r9d, edi\nmov rax, fs:28h\nmov [rsp+1A8h+var_10], rax\nxor eax, eax\ncmp edi, 2\njle short loc_11F3\nlea esi, [rdi+rdi]\nmov eax, edi\nmov r11d, 0\njmp short loc_11A4\nloc_119C:\nsub eax, 1\ncmp eax, 1\njz short loc_11B8\nloc_11A4:\nlea edx, [rax+rax]\ncmp r9d, edx\njge short loc_119C\nmovsxd rdx, r11d\nmov [rsp+rdx*4+1A8h+var_1A8], eax\nlea r11d, [r11+1]\njmp short loc_119C\nloc_11B8:\nmov r10, rsp\nmovsxd rax, r11d\nlea r8, [r10+rax*4]\nlea eax, [r11-1]\nlea rdi, [r10+rax*4]\njmp short loc_11CF\nloc_11CC:\nadd esi, r9d\nloc_11CF:\ntest r11d, r11d\njle short loc_11CF\nmov rcx, r10\nloc_11D7:\nmov eax, esi\ncdq\nidiv dword ptr [rcx]\ntest edx, edx\njnz short loc_11CC\ncmp rcx, rdi\njz short loc_11F0\nadd rcx, 4\ncmp rcx, r8\njnz short loc_11D7\njmp short loc_11CF\nloc_11F0:\nmov r9d, esi\nloc_11F3:\nmov rax, [rsp+1A8h+var_10]\nsub rax, fs:28h\njnz short loc_1211\nmov eax, r9d\nadd rsp, 1A8h\nretn\nloc_1211:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v1; // r9d\n int v2; // esi\n int v3; // eax\n int v4; // r11d\n _DWORD *v5; // rcx\n _DWORD v7[102]; // [rsp+0h] [rbp-1A8h] BYREF\n unsigned __int64 v8; // [rsp+198h] [rbp-10h]\n\n v1 = a1;\n v8 = __readfsqword(0x28u);\n if ( a1 > 2 )\n {\n v2 = 2 * a1;\n v3 = a1;\n v4 = 0;\n do\n {\n if ( a1 < 2 * v3 )\n v7[v4++] = v3;\n --v3;\n }\n while ( v3 != 1 );\nLABEL_8:\n while ( v4 <= 0 )\n ;\n v5 = v7;\n while ( 1 )\n {\n if ( v2 % *v5 )\n {\n v2 += a1;\n goto LABEL_8;\n }\n if ( v5 == &v7[v4 - 1] )\n return (unsigned int)v2;\n if ( ++v5 == &v7[v4] )\n goto LABEL_8;\n }\n }\n return v1;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nsub rsp, 1A8h\nmov r9d, edi\nmov rax, fs:28h\nmov [rsp+1A8h+var_10], rax\nxor eax, eax\ncmp edi, 2\njle short loc_11F3\nlea esi, [rdi+rdi]\nmov eax, edi\nmov r11d, 0\njmp short loc_11A4\nloc_119C:\nsub eax, 1\ncmp eax, 1\njz short loc_11B8\nloc_11A4:\nlea edx, [rax+rax]\ncmp r9d, edx\njge short loc_119C\nmovsxd rdx, r11d\nmov [rsp+rdx*4+1A8h+var_1A8], eax\nlea r11d, [r11+1]\njmp short loc_119C\nloc_11B8:\nmov r10, rsp\nmovsxd rax, r11d\nlea r8, [r10+rax*4]\nlea eax, [r11-1]\nlea rdi, [r10+rax*4]\njmp short loc_11CF\nloc_11CC:\nadd esi, r9d\nloc_11CF:\ntest r11d, r11d\njle short loc_11CF\nmov rcx, r10\nloc_11D7:\nmov eax, esi\ncdq\nidiv dword ptr [rcx]\ntest edx, edx\njnz short loc_11CC\ncmp rcx, rdi\njz short loc_11F0\nadd rcx, 4\ncmp rcx, r8\njnz short loc_11D7\njmp short loc_11CF\nloc_11F0:\nmov r9d, esi\nloc_11F3:\nmov rax, [rsp+1A8h+var_10]\nsub rax, fs:28h\njnz short loc_1211\nmov eax, r9d\nadd rsp, 1A8h\nretn\nloc_1211:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n unsigned int v1; // r9d\n int v2; // esi\n int v3; // eax\n int v4; // r11d\n _DWORD *v5; // rcx\n _DWORD v7[102]; // [rsp+0h] [rbp-1A8h] BYREF\n unsigned __int64 v8; // [rsp+198h] [rbp-10h]\n\n v1 = a1;\n v8 = __readfsqword(0x28u);\n if ( a1 > 2 )\n {\n v2 = 2 * a1;\n v3 = a1;\n v4 = 0;\n do\n {\n if ( a1 < 2 * v3 )\n v7[v4++] = v3;\n --v3;\n }\n while ( v3 != 1 );\nLABEL_8:\n while ( v4 <= 0 )\n ;\n v5 = v7;\n while ( 1 )\n {\n if ( v2 % *v5 )\n {\n v2 += a1;\n goto LABEL_8;\n }\n if ( v5 == &v7[v4 - 1] )\n return (unsigned int)v2;\n if ( ++v5 == &v7[v4] )\n goto LABEL_8;\n }\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n unsigned int v1;\n int v2;\n int v3;\n int v4;\n uint32_t *v5;\n uint32_t v7[102];\n unsigned long long v8;\n v1 = a1;\n v8 = __readfsqword(40u);\n if (a1 > 2) {\n v2 = 2 * a1;\n v3 = a1;\n v4 = 0;\n do {\n if (a1 < 2 * v3) v7[v4++] = v3;\n --v3;\n } while (v3 != 1);\n LABEL_8:\n while (v4 <= 0)\n ;\n v5 = v7;\n while (1) {\n if (v2 % *v5) {\n v2 += a1;\n goto LABEL_8;\n }\n if (v5 == &v7[v4 - 1]) return (unsigned int)v2;\n if (++v5 == &v7[v4]) goto LABEL_8;\n }\n }\n return v1;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v1;\n int v2;\n int v3;\n int v4;\n uint32_t *v5;\n uint32_t v7[102];\n unsigned long long v8;\n v1 = a1;\n v8 = __readfsqword(40u);\n if (a1 > 2) {\n v2 = 2 * a1;\n v3 = a1;\n v4 = 0;\n do {\n if (a1 < 2 * v3) v7[v4++] = v3;\n --v3;\n } while (v3 != 1);\n LABEL_8:\n while (v4 <= 0)\n ;\n v5 = v7;\n while (1) {\n if (v2 % *v5) {\n v2 += a1;\n goto LABEL_8;\n }\n if (v5 == &v7[v4 - 1]) return (unsigned int)v2;\n if (++v5 == &v7[v4]) goto LABEL_8;\n }\n }\n return v1;\n}" + }, + { + "index": 901, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n <= 2) {\n return n;\n }\n int i = n * 2;\n int factors[100];\n int factor_count = 0;\n for (int number = n; number > 1; number--) {\n if (number * 2 > n) {\n factors[factor_count++] = number;\n }\n }\n while (1) {\n for (int j = 0; j < factor_count; j++) {\n if (i % factors[j] != 0) {\n i += n;\n break;\n }\n if (j == factor_count - 1 && i % factors[j] == 0) {\n return i;\n }\n }\n }\n}", + "test": "int main() {\n\n assert(func0(13) == 360360);\n\n assert(func0(2) == 2);\n\n assert(func0(1) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x2,%edi\njle 1290 \njmpq 11b0 \nxchg %ax,%ax\nmov %edi,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0_part_0:\nsub rsp, 1A8h\nmov r9d, edi\nlea esi, [rdi+rdi]\nmov rax, fs:28h\nmov [rsp+1A8h+var_10], rax\nxor eax, eax\ncmp edi, 1\njz loc_1260\nmov eax, edi\nxor r10d, r10d\nxchg ax, ax\nloc_11E0:\nlea edx, [rax+rax]\ncmp r9d, edx\njge short loc_11F2\nmovsxd rdx, r10d\nadd r10d, 1\nmov [rsp+rdx*4+1A8h+var_1A8], eax\nloc_11F2:\nsub eax, 1\ncmp eax, 1\njnz short loc_11E0\nlea eax, [r10-1]\nloc_11FE:\nmov r11, rsp\nmovsxd rdx, r10d\nlea r8, [r11+rdx*4]\nlea rdi, [r11+rax*4]\nloc_120C:\ntest r10d, r10d\njle short loc_125D\nmov rcx, r11\njmp short loc_122E\nloc_1220:\ncmp rcx, rdi\njz short loc_1240\nadd rcx, 4\ncmp rcx, r8\njz short loc_120C\nloc_122E:\nmov eax, esi\ncdq\nidiv dword ptr [rcx]\ntest edx, edx\njz short loc_1220\nadd esi, r9d\njmp short loc_120C\nloc_1240:\nmov rax, [rsp+1A8h+var_10]\nsub rax, fs:28h\njnz short loc_126A\nmov eax, esi\nadd rsp, 1A8h\nretn\nloc_125D:\njmp short loc_125D\nloc_1260:\nmov eax, 0FFFFFFFFh\nxor r10d, r10d\njmp short loc_11FE\nloc_126A:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0_part_0(int a1)\n{\n int v1; // esi\n int v2; // eax\n int v3; // r10d\n __int64 v4; // rdx\n __int64 v5; // rax\n _DWORD *v6; // rcx\n _DWORD v8[102]; // [rsp+0h] [rbp-1A8h] BYREF\n unsigned __int64 v9; // [rsp+198h] [rbp-10h]\n\n v1 = 2 * a1;\n v9 = __readfsqword(0x28u);\n if ( a1 == 1 )\n {\n v5 = 0xFFFFFFFFLL;\n v3 = 0;\n }\n else\n {\n v2 = a1;\n v3 = 0;\n do\n {\n if ( a1 < 2 * v2 )\n {\n v4 = v3++;\n v8[v4] = v2;\n }\n --v2;\n }\n while ( v2 != 1 );\n v5 = (unsigned int)(v3 - 1);\n }\nLABEL_7:\n if ( v3 <= 0 )\n {\n while ( 1 )\n ;\n }\n v6 = v8;\n while ( 1 )\n {\n if ( v1 % *v6 )\n {\n v1 += a1;\n goto LABEL_7;\n }\n if ( v6 == &v8[v5] )\n return (unsigned int)v1;\n if ( ++v6 == &v8[v3] )\n goto LABEL_7;\n }\n}", + "ida_strip_asm": "sub_11B0:\nsub rsp, 1A8h\nmov r9d, edi\nlea esi, [rdi+rdi]\nmov rax, fs:28h\nmov [rsp+1A8h+var_10], rax\nxor eax, eax\ncmp edi, 1\njz loc_1260\nmov eax, edi\nxor r10d, r10d\nxchg ax, ax\nloc_11E0:\nlea edx, [rax+rax]\ncmp r9d, edx\njge short loc_11F2\nmovsxd rdx, r10d\nadd r10d, 1\nmov [rsp+rdx*4+1A8h+var_1A8], eax\nloc_11F2:\nsub eax, 1\ncmp eax, 1\njnz short loc_11E0\nlea eax, [r10-1]\nloc_11FE:\nmov r11, rsp\nmovsxd rdx, r10d\nlea r8, [r11+rdx*4]\nlea rdi, [r11+rax*4]\nloc_120C:\ntest r10d, r10d\njle short loc_125D\nmov rcx, r11\njmp short loc_122E\nloc_1220:\ncmp rcx, rdi\njz short loc_1240\nadd rcx, 4\ncmp rcx, r8\njz short loc_120C\nloc_122E:\nmov eax, esi\ncdq\nidiv dword ptr [rcx]\ntest edx, edx\njz short loc_1220\nadd esi, r9d\njmp short loc_120C\nloc_1240:\nmov rax, [rsp+1A8h+var_10]\nsub rax, fs:28h\njnz short loc_126A\nmov eax, esi\nadd rsp, 1A8h\nretn\nloc_125D:\njmp short loc_125D\nloc_1260:\nmov eax, 0FFFFFFFFh\nxor r10d, r10d\njmp short loc_11FE\nloc_126A:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_11B0(int a1)\n{\n int v1; // esi\n int v2; // eax\n int v3; // r10d\n __int64 v4; // rdx\n __int64 v5; // rax\n _DWORD *v6; // rcx\n _DWORD v8[102]; // [rsp+0h] [rbp-1A8h] BYREF\n unsigned __int64 v9; // [rsp+198h] [rbp-10h]\n\n v1 = 2 * a1;\n v9 = __readfsqword(0x28u);\n if ( a1 == 1 )\n {\n v5 = 0xFFFFFFFFLL;\n v3 = 0;\n }\n else\n {\n v2 = a1;\n v3 = 0;\n do\n {\n if ( a1 < 2 * v2 )\n {\n v4 = v3++;\n v8[v4] = v2;\n }\n --v2;\n }\n while ( v2 != 1 );\n v5 = (unsigned int)(v3 - 1);\n }\nLABEL_7:\n if ( v3 <= 0 )\n {\n while ( 1 )\n ;\n }\n v6 = v8;\n while ( 1 )\n {\n if ( v1 % *v6 )\n {\n v1 += a1;\n goto LABEL_7;\n }\n if ( v6 == &v8[v5] )\n return (unsigned int)v1;\n if ( ++v6 == &v8[v3] )\n goto LABEL_7;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11B0(int a1) {\n int v1;\n int v2;\n int v3;\n long long v4;\n long long v5;\n uint32_t *v6;\n uint32_t v8[102];\n unsigned long long v9;\n v1 = 2 * a1;\n v9 = __readfsqword(40u);\n if (a1 == 1) {\n v5 = 4294967295LL;\n v3 = 0;\n } else {\n v2 = a1;\n v3 = 0;\n do {\n if (a1 < 2 * v2) {\n v4 = v3++;\n v8[v4] = v2;\n }\n --v2;\n } while (v2 != 1);\n v5 = (unsigned int)(v3 - 1);\n }\nLABEL_7:\n if (v3 <= 0) {\n while (1)\n ;\n }\n v6 = v8;\n while (1) {\n if (v1 % *v6) {\n v1 += a1;\n goto LABEL_7;\n }\n if (v6 == &v8[v5]) return (unsigned int)v1;\n if (++v6 == &v8[v3]) goto LABEL_7;\n }\n}", + "ida_pseudo_norm": "long long func0_part_0(int a1) {\n int v1;\n int v2;\n int v3;\n long long v4;\n long long v5;\n uint32_t *v6;\n uint32_t v8[102];\n unsigned long long v9;\n v1 = 2 * a1;\n v9 = __readfsqword(40u);\n if (a1 == 1) {\n v5 = 4294967295LL;\n v3 = 0;\n } else {\n v2 = a1;\n v3 = 0;\n do {\n if (a1 < 2 * v2) {\n v4 = v3++;\n v8[v4] = v2;\n }\n --v2;\n } while (v2 != 1);\n v5 = (unsigned int)(v3 - 1);\n }\nLABEL_7:\n if (v3 <= 0) {\n while (1)\n ;\n }\n v6 = v8;\n while (1) {\n if (v1 % *v6) {\n v1 += a1;\n goto LABEL_7;\n }\n if (v6 == &v8[v5]) return (unsigned int)v1;\n if (++v6 == &v8[v3]) goto LABEL_7;\n }\n}" + }, + { + "index": 901, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n <= 2) {\n return n;\n }\n int i = n * 2;\n int factors[100];\n int factor_count = 0;\n for (int number = n; number > 1; number--) {\n if (number * 2 > n) {\n factors[factor_count++] = number;\n }\n }\n while (1) {\n for (int j = 0; j < factor_count; j++) {\n if (i % factors[j] != 0) {\n i += n;\n break;\n }\n if (j == factor_count - 1 && i % factors[j] == 0) {\n return i;\n }\n }\n }\n}", + "test": "int main() {\n\n assert(func0(13) == 360360);\n\n assert(func0(2) == 2);\n\n assert(func0(1) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x2,%edi\njle 1290 \njmpq 11b0 \nxchg %ax,%ax\nmov %edi,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0_part_0:\nsub rsp, 1A8h\nmov r9d, edi\nlea esi, [rdi+rdi]\nmov rax, fs:28h\nmov [rsp+1A8h+var_10], rax\nxor eax, eax\ncmp edi, 1\njz loc_1265\nmov eax, edi\nxor r10d, r10d\nxchg ax, ax\nloc_11E0:\nlea edx, [rax+rax]\ncmp r9d, edx\njge short loc_11F2\nmovsxd rdx, r10d\nadd r10d, 1\nmov [rsp+rdx*4+1A8h+var_1A8], eax\nloc_11F2:\nsub eax, 1\ncmp eax, 1\njnz short loc_11E0\nlea eax, [r10-1]\nloc_11FE:\nmov r11, rsp\nmovsxd rdx, r10d\nlea r8, [r11+rdx*4]\nlea rdi, [r11+rax*4]\ntest r10d, r10d\njle short loc_123F\nloc_1211:\nmov rcx, r11\njmp short loc_122E\nloc_1220:\ncmp rcx, rdi\njz short loc_1248\nadd rcx, 4\ncmp rcx, r8\njz short loc_1211\nloc_122E:\nmov eax, esi\ncdq\nidiv dword ptr [rcx]\ntest edx, edx\njz short loc_1220\nadd esi, r9d\ntest r10d, r10d\njg short loc_1211\nloc_123F:\njmp short loc_123F\nloc_1248:\nmov rax, [rsp+1A8h+var_10]\nsub rax, fs:28h\njnz short loc_126F\nmov eax, esi\nadd rsp, 1A8h\nretn\nloc_1265:\nmov eax, 0FFFFFFFFh\nxor r10d, r10d\njmp short loc_11FE\nloc_126F:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0_part_0(int a1)\n{\n int v1; // esi\n int v2; // eax\n int v3; // r10d\n __int64 v4; // rdx\n __int64 v5; // rax\n _DWORD *v6; // rcx\n _DWORD v8[102]; // [rsp+0h] [rbp-1A8h] BYREF\n unsigned __int64 v9; // [rsp+198h] [rbp-10h]\n\n v1 = 2 * a1;\n v9 = __readfsqword(0x28u);\n if ( a1 == 1 )\n {\n v5 = 0xFFFFFFFFLL;\n v3 = 0;\n }\n else\n {\n v2 = a1;\n v3 = 0;\n do\n {\n if ( a1 < 2 * v2 )\n {\n v4 = v3++;\n v8[v4] = v2;\n }\n --v2;\n }\n while ( v2 != 1 );\n v5 = (unsigned int)(v3 - 1);\n }\n if ( v3 <= 0 )\n {\n while ( 1 )\n ;\n }\nLABEL_8:\n v6 = v8;\n while ( 1 )\n {\n if ( v1 % *v6 )\n {\n v1 += a1;\n goto LABEL_8;\n }\n if ( v6 == &v8[v5] )\n return (unsigned int)v1;\n if ( ++v6 == &v8[v3] )\n goto LABEL_8;\n }\n}", + "ida_strip_asm": "sub_11B0:\nsub rsp, 1A8h\nmov r9d, edi\nlea esi, [rdi+rdi]\nmov rax, fs:28h\nmov [rsp+1A8h+var_10], rax\nxor eax, eax\ncmp edi, 1\njz loc_1265\nmov eax, edi\nxor r10d, r10d\nxchg ax, ax\nloc_11E0:\nlea edx, [rax+rax]\ncmp r9d, edx\njge short loc_11F2\nmovsxd rdx, r10d\nadd r10d, 1\nmov [rsp+rdx*4+1A8h+var_1A8], eax\nloc_11F2:\nsub eax, 1\ncmp eax, 1\njnz short loc_11E0\nlea eax, [r10-1]\nloc_11FE:\nmov r11, rsp\nmovsxd rdx, r10d\nlea r8, [r11+rdx*4]\nlea rdi, [r11+rax*4]\ntest r10d, r10d\njle short loc_123F\nloc_1211:\nmov rcx, r11\njmp short loc_122E\nloc_1220:\ncmp rcx, rdi\njz short loc_1248\nadd rcx, 4\ncmp rcx, r8\njz short loc_1211\nloc_122E:\nmov eax, esi\ncdq\nidiv dword ptr [rcx]\ntest edx, edx\njz short loc_1220\nadd esi, r9d\ntest r10d, r10d\njg short loc_1211\nloc_123F:\njmp short loc_123F\nloc_1248:\nmov rax, [rsp+1A8h+var_10]\nsub rax, fs:28h\njnz short loc_126F\nmov eax, esi\nadd rsp, 1A8h\nretn\nloc_1265:\nmov eax, 0FFFFFFFFh\nxor r10d, r10d\njmp short loc_11FE\nloc_126F:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_11B0(int a1)\n{\n int v1; // esi\n int v2; // eax\n int v3; // r10d\n __int64 v4; // rdx\n __int64 v5; // rax\n _DWORD *v6; // rcx\n _DWORD v8[102]; // [rsp+0h] [rbp-1A8h] BYREF\n unsigned __int64 v9; // [rsp+198h] [rbp-10h]\n\n v1 = 2 * a1;\n v9 = __readfsqword(0x28u);\n if ( a1 == 1 )\n {\n v5 = 0xFFFFFFFFLL;\n v3 = 0;\n }\n else\n {\n v2 = a1;\n v3 = 0;\n do\n {\n if ( a1 < 2 * v2 )\n {\n v4 = v3++;\n v8[v4] = v2;\n }\n --v2;\n }\n while ( v2 != 1 );\n v5 = (unsigned int)(v3 - 1);\n }\n if ( v3 <= 0 )\n {\n while ( 1 )\n ;\n }\nLABEL_8:\n v6 = v8;\n while ( 1 )\n {\n if ( v1 % *v6 )\n {\n v1 += a1;\n goto LABEL_8;\n }\n if ( v6 == &v8[v5] )\n return (unsigned int)v1;\n if ( ++v6 == &v8[v3] )\n goto LABEL_8;\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11B0(int a1) {\n int v1;\n int v2;\n int v3;\n long long v4;\n long long v5;\n uint32_t *v6;\n uint32_t v8[102];\n unsigned long long v9;\n v1 = 2 * a1;\n v9 = __readfsqword(40u);\n if (a1 == 1) {\n v5 = 4294967295LL;\n v3 = 0;\n } else {\n v2 = a1;\n v3 = 0;\n do {\n if (a1 < 2 * v2) {\n v4 = v3++;\n v8[v4] = v2;\n }\n --v2;\n } while (v2 != 1);\n v5 = (unsigned int)(v3 - 1);\n }\n if (v3 <= 0) {\n while (1)\n ;\n }\nLABEL_8:\n v6 = v8;\n while (1) {\n if (v1 % *v6) {\n v1 += a1;\n goto LABEL_8;\n }\n if (v6 == &v8[v5]) return (unsigned int)v1;\n if (++v6 == &v8[v3]) goto LABEL_8;\n }\n}", + "ida_pseudo_norm": "long long func0_part_0(int a1) {\n int v1;\n int v2;\n int v3;\n long long v4;\n long long v5;\n uint32_t *v6;\n uint32_t v8[102];\n unsigned long long v9;\n v1 = 2 * a1;\n v9 = __readfsqword(40u);\n if (a1 == 1) {\n v5 = 4294967295LL;\n v3 = 0;\n } else {\n v2 = a1;\n v3 = 0;\n do {\n if (a1 < 2 * v2) {\n v4 = v3++;\n v8[v4] = v2;\n }\n --v2;\n } while (v2 != 1);\n v5 = (unsigned int)(v3 - 1);\n }\n if (v3 <= 0) {\n while (1)\n ;\n }\nLABEL_8:\n v6 = v8;\n while (1) {\n if (v1 % *v6) {\n v1 += a1;\n goto LABEL_8;\n }\n if (v6 == &v8[v5]) return (unsigned int)v1;\n if (++v6 == &v8[v3]) goto LABEL_8;\n }\n}" + }, + { + "index": 902, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char key;\n\n int value;\n\n} KeyValue;\n\n\n\n", + "func": "KeyValue *func0(KeyValue d1[], int size1, KeyValue d2[], int size2) {\n KeyValue *result = malloc((size1 + size2) * sizeof(KeyValue));\n int sizeResult = 0;\n for (int i = 0; i < size1; i++) {\n int found = 0;\n for (int j = 0; j < sizeResult; j++) {\n if (result[j].key == d1[i].key) {\n result[j].value += d1[i].value;\n found = 1;\n break;\n }\n }\n if (!found) {\n result[sizeResult].key = d1[i].key;\n result[sizeResult].value = d1[i].value;\n sizeResult++;\n }\n }\n for (int i = 0; i < size2; i++) {\n int found = 0;\n for (int j = 0; j < sizeResult; j++) {\n if (result[j].key == d2[i].key) {\n result[j].value += d2[i].value;\n found = 1;\n break;\n }\n }\n if (!found) {\n result[sizeResult].key = d2[i].key;\n result[sizeResult].value = d2[i].value;\n sizeResult++;\n }\n }\n return result;\n}", + "test": "int main() {\n\n KeyValue d1[] = { {'a', 100}, {'b', 200}, {'c', 300} };\n\n KeyValue d2[] = { {'a', 300}, {'b', 200}, {'d', 400} };\n\n KeyValue *result1 = func0(d1, 3, d2, 3);\n\n assert(result1[0].value == 400 && result1[1].value == 400 && result1[2].value == 300 && result1[3].value == 400); // Since order may vary, checks are grouped by values only\n\n\n\n KeyValue d3[] = { {'a', 500}, {'b', 700}, {'c', 900} };\n\n KeyValue d4[] = { {'a', 500}, {'b', 600}, {'d', 900} };\n\n KeyValue *result2 = func0(d3, 3, d4, 3);\n\n assert(result2[0].value == 1000 && result2[1].value == 1300 && result2[2].value == 900 && result2[3].value == 900); // Since order may vary, checks are grouped by values only\n\n\n\n KeyValue d5[] = { {'a', 900}, {'b', 900}, {'d', 900} };\n\n KeyValue d6[] = { {'a', 900}, {'b', 900}, {'d', 900} };\n\n KeyValue *result3 = func0(d5, 3, d6, 3);\n\n assert(result3[0].value == 1800 && result3[1].value == 1800 && result3[2].value == 1800); // Since order may vary, checks are grouped by values only\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x50,%rsp\nmov %rdi,-0x38(%rbp)\nmov %esi,-0x3c(%rbp)\nmov %rdx,-0x48(%rbp)\nmov %ecx,-0x40(%rbp)\nmov -0x3c(%rbp),%edx\nmov -0x40(%rbp),%eax\nadd %edx,%eax\ncltq\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0x24(%rbp)\nmovl $0x0,-0x20(%rbp)\njmpq 1300 \nmovl $0x0,-0x1c(%rbp)\nmovl $0x0,-0x18(%rbp)\njmpq 1289 \nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%edx\nmov -0x20(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x38(%rbp),%rax\nadd %rcx,%rax\nmovzbl (%rax),%eax\ncmp %al,%dl\njne 1285 \nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov 0x4(%rax),%ecx\nmov -0x20(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov 0x4(%rax),%edx\nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rsi\nmov -0x8(%rbp),%rax\nadd %rsi,%rax\nadd %ecx,%edx\nmov %edx,0x4(%rax)\nmovl $0x1,-0x1c(%rbp)\njmp 1295 \naddl $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%eax\ncmp -0x24(%rbp),%eax\njl 1203 \ncmpl $0x0,-0x1c(%rbp)\njne 12fc \nmov -0x20(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov -0x24(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rax),%eax\nmov %al,(%rdx)\nmov -0x20(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov -0x24(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nmov 0x4(%rax),%eax\nmov %eax,0x4(%rdx)\naddl $0x1,-0x24(%rbp)\naddl $0x1,-0x20(%rbp)\nmov -0x20(%rbp),%eax\ncmp -0x3c(%rbp),%eax\njl 11f0 \nmovl $0x0,-0x14(%rbp)\njmpq 1428 \nmovl $0x0,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\njmpq 13b1 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%edx\nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x48(%rbp),%rax\nadd %rcx,%rax\nmovzbl (%rax),%eax\ncmp %al,%dl\njne 13ad \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov 0x4(%rax),%ecx\nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov 0x4(%rax),%edx\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rsi\nmov -0x8(%rbp),%rax\nadd %rsi,%rax\nadd %ecx,%edx\nmov %edx,0x4(%rax)\nmovl $0x1,-0x10(%rbp)\njmp 13bd \naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x24(%rbp),%eax\njl 132b \ncmpl $0x0,-0x10(%rbp)\njne 1424 \nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov -0x24(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rax),%eax\nmov %al,(%rdx)\nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov -0x24(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nmov 0x4(%rax),%eax\nmov %eax,0x4(%rdx)\naddl $0x1,-0x24(%rbp)\naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\ncmp -0x40(%rbp),%eax\njl 1318 \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov [rbp+var_48], rdx\nmov [rbp+var_40], ecx\nmov edx, [rbp+var_3C]\nmov eax, [rbp+var_40]\nadd eax, edx\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_24], 0\nmov [rbp+var_20], 0\njmp loc_1300\nloc_11F0:\nmov [rbp+var_1C], 0\nmov [rbp+var_18], 0\njmp loc_1289\nloc_1203:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_20]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njnz short loc_1285\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov ecx, [rax+4]\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rax+4]\nmov eax, [rbp+var_18]\ncdqe\nlea rsi, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rsi\nadd edx, ecx\nmov [rax+4], edx\nmov [rbp+var_1C], 1\njmp short loc_1295\nloc_1285:\nadd [rbp+var_18], 1\nloc_1289:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_24]\njl loc_1203\nloc_1295:\ncmp [rbp+var_1C], 0\njnz short loc_12FC\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmovzx eax, byte ptr [rax]\nmov [rdx], al\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax+4]\nmov [rdx+4], eax\nadd [rbp+var_24], 1\nloc_12FC:\nadd [rbp+var_20], 1\nloc_1300:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_3C]\njl loc_11F0\nmov [rbp+var_14], 0\njmp loc_1428\nloc_1318:\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp loc_13B1\nloc_132B:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_14]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njnz short loc_13AD\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov ecx, [rax+4]\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov edx, [rax+4]\nmov eax, [rbp+var_C]\ncdqe\nlea rsi, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rsi\nadd edx, ecx\nmov [rax+4], edx\nmov [rbp+var_10], 1\njmp short loc_13BD\nloc_13AD:\nadd [rbp+var_C], 1\nloc_13B1:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_24]\njl loc_132B\nloc_13BD:\ncmp [rbp+var_10], 0\njnz short loc_1424\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmovzx eax, byte ptr [rax]\nmov [rdx], al\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax+4]\nmov [rdx+4], eax\nadd [rbp+var_24], 1\nloc_1424:\nadd [rbp+var_14], 1\nloc_1428:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_40]\njl loc_1318\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, __int64 a3, int a4)\n{\n int v7; // [rsp+2Ch] [rbp-24h]\n int i; // [rsp+30h] [rbp-20h]\n int v9; // [rsp+34h] [rbp-1Ch]\n int j; // [rsp+38h] [rbp-18h]\n int k; // [rsp+3Ch] [rbp-14h]\n int v12; // [rsp+40h] [rbp-10h]\n int m; // [rsp+44h] [rbp-Ch]\n _DWORD *v14; // [rsp+48h] [rbp-8h]\n\n v14 = malloc(8LL * (a2 + a4));\n v7 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v9 = 0;\n for ( j = 0; j < v7; ++j )\n {\n if ( LOBYTE(v14[2 * j]) == *(_BYTE *)(8LL * i + a1) )\n {\n v14[2 * j + 1] += *(_DWORD *)(8LL * i + a1 + 4);\n v9 = 1;\n break;\n }\n }\n if ( !v9 )\n {\n LOBYTE(v14[2 * v7]) = *(_BYTE *)(8LL * i + a1);\n v14[2 * v7++ + 1] = *(_DWORD *)(8LL * i + a1 + 4);\n }\n }\n for ( k = 0; k < a4; ++k )\n {\n v12 = 0;\n for ( m = 0; m < v7; ++m )\n {\n if ( LOBYTE(v14[2 * m]) == *(_BYTE *)(8LL * k + a3) )\n {\n v14[2 * m + 1] += *(_DWORD *)(8LL * k + a3 + 4);\n v12 = 1;\n break;\n }\n }\n if ( !v12 )\n {\n LOBYTE(v14[2 * v7]) = *(_BYTE *)(8LL * k + a3);\n v14[2 * v7++ + 1] = *(_DWORD *)(8LL * k + a3 + 4);\n }\n }\n return v14;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov [rbp+var_48], rdx\nmov [rbp+var_40], ecx\nmov edx, [rbp+var_3C]\nmov eax, [rbp+var_40]\nadd eax, edx\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_24], 0\nmov [rbp+var_20], 0\njmp loc_1300\nloc_11F0:\nmov [rbp+var_1C], 0\nmov [rbp+var_18], 0\njmp loc_1289\nloc_1203:\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_20]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njnz short loc_1285\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov ecx, [rax+4]\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rax+4]\nmov eax, [rbp+var_18]\ncdqe\nlea rsi, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rsi\nadd edx, ecx\nmov [rax+4], edx\nmov [rbp+var_1C], 1\njmp short loc_1295\nloc_1285:\nadd [rbp+var_18], 1\nloc_1289:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_24]\njl loc_1203\nloc_1295:\ncmp [rbp+var_1C], 0\njnz short loc_12FC\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmovzx eax, byte ptr [rax]\nmov [rdx], al\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax+4]\nmov [rdx+4], eax\nadd [rbp+var_24], 1\nloc_12FC:\nadd [rbp+var_20], 1\nloc_1300:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_3C]\njl loc_11F0\nmov [rbp+var_14], 0\njmp loc_1428\nloc_1318:\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp loc_13B1\nloc_132B:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_14]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njnz short loc_13AD\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov ecx, [rax+4]\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov edx, [rax+4]\nmov eax, [rbp+var_C]\ncdqe\nlea rsi, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rax, rsi\nadd edx, ecx\nmov [rax+4], edx\nmov [rbp+var_10], 1\njmp short loc_13BD\nloc_13AD:\nadd [rbp+var_C], 1\nloc_13B1:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_24]\njl loc_132B\nloc_13BD:\ncmp [rbp+var_10], 0\njnz short loc_1424\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmovzx eax, byte ptr [rax]\nmov [rdx], al\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax+4]\nmov [rdx+4], eax\nadd [rbp+var_24], 1\nloc_1424:\nadd [rbp+var_14], 1\nloc_1428:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_40]\njl loc_1318\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(__int64 a1, int a2, __int64 a3, int a4)\n{\n int v7; // [rsp+2Ch] [rbp-24h]\n int i; // [rsp+30h] [rbp-20h]\n int v9; // [rsp+34h] [rbp-1Ch]\n int j; // [rsp+38h] [rbp-18h]\n int k; // [rsp+3Ch] [rbp-14h]\n int v12; // [rsp+40h] [rbp-10h]\n int m; // [rsp+44h] [rbp-Ch]\n _DWORD *v14; // [rsp+48h] [rbp-8h]\n\n v14 = malloc(8LL * (a2 + a4));\n v7 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v9 = 0;\n for ( j = 0; j < v7; ++j )\n {\n if ( LOBYTE(v14[2 * j]) == *(_BYTE *)(8LL * i + a1) )\n {\n v14[2 * j + 1] += *(_DWORD *)(8LL * i + a1 + 4);\n v9 = 1;\n break;\n }\n }\n if ( !v9 )\n {\n LOBYTE(v14[2 * v7]) = *(_BYTE *)(8LL * i + a1);\n v14[2 * v7++ + 1] = *(_DWORD *)(8LL * i + a1 + 4);\n }\n }\n for ( k = 0; k < a4; ++k )\n {\n v12 = 0;\n for ( m = 0; m < v7; ++m )\n {\n if ( LOBYTE(v14[2 * m]) == *(_BYTE *)(8LL * k + a3) )\n {\n v14[2 * m + 1] += *(_DWORD *)(8LL * k + a3 + 4);\n v12 = 1;\n break;\n }\n }\n if ( !v12 )\n {\n LOBYTE(v14[2 * v7]) = *(_BYTE *)(8LL * k + a3);\n v14[2 * v7++ + 1] = *(_DWORD *)(8LL * k + a3 + 4);\n }\n }\n return v14;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(long long a1, int a2, long long a3, int a4) {\n int v7;\n int i;\n int v9;\n int j;\n int k;\n int v12;\n int m;\n uint32_t *v14;\n v14 = malloc(8LL * (a2 + a4));\n v7 = 0;\n for (i = 0; i < a2; ++i) {\n v9 = 0;\n for (j = 0; j < v7; ++j) {\n if (LOBYTE(v14[2 * j]) == *(uint8_t *)(8LL * i + a1)) {\n v14[2 * j + 1] += *(uint32_t *)(8LL * i + a1 + 4);\n v9 = 1;\n break;\n }\n }\n if (!v9) {\n LOBYTE(v14[2 * v7]) = *(uint8_t *)(8LL * i + a1);\n v14[2 * v7++ + 1] = *(uint32_t *)(8LL * i + a1 + 4);\n }\n }\n for (k = 0; k < a4; ++k) {\n v12 = 0;\n for (m = 0; m < v7; ++m) {\n if (LOBYTE(v14[2 * m]) == *(uint8_t *)(8LL * k + a3)) {\n v14[2 * m + 1] += *(uint32_t *)(8LL * k + a3 + 4);\n v12 = 1;\n break;\n }\n }\n if (!v12) {\n LOBYTE(v14[2 * v7]) = *(uint8_t *)(8LL * k + a3);\n v14[2 * v7++ + 1] = *(uint32_t *)(8LL * k + a3 + 4);\n }\n }\n return v14;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, long long a3, int a4) {\n int v7;\n int i;\n int v9;\n int j;\n int k;\n int v12;\n int m;\n uint32_t *v14;\n v14 = malloc(8LL * (a2 + a4));\n v7 = 0;\n for (i = 0; i < a2; ++i) {\n v9 = 0;\n for (j = 0; j < v7; ++j) {\n if (LOBYTE(v14[2 * j]) == *(uint8_t *)(8LL * i + a1)) {\n v14[2 * j + 1] += *(uint32_t *)(8LL * i + a1 + 4);\n v9 = 1;\n break;\n }\n }\n if (!v9) {\n LOBYTE(v14[2 * v7]) = *(uint8_t *)(8LL * i + a1);\n v14[2 * v7++ + 1] = *(uint32_t *)(8LL * i + a1 + 4);\n }\n }\n for (k = 0; k < a4; ++k) {\n v12 = 0;\n for (m = 0; m < v7; ++m) {\n if (LOBYTE(v14[2 * m]) == *(uint8_t *)(8LL * k + a3)) {\n v14[2 * m + 1] += *(uint32_t *)(8LL * k + a3 + 4);\n v12 = 1;\n break;\n }\n }\n if (!v12) {\n LOBYTE(v14[2 * v7]) = *(uint8_t *)(8LL * k + a3);\n v14[2 * v7++ + 1] = *(uint32_t *)(8LL * k + a3 + 4);\n }\n }\n return v14;\n}" + }, + { + "index": 902, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char key;\n\n int value;\n\n} KeyValue;\n\n\n\n", + "func": "KeyValue *func0(KeyValue d1[], int size1, KeyValue d2[], int size2) {\n KeyValue *result = malloc((size1 + size2) * sizeof(KeyValue));\n int sizeResult = 0;\n for (int i = 0; i < size1; i++) {\n int found = 0;\n for (int j = 0; j < sizeResult; j++) {\n if (result[j].key == d1[i].key) {\n result[j].value += d1[i].value;\n found = 1;\n break;\n }\n }\n if (!found) {\n result[sizeResult].key = d1[i].key;\n result[sizeResult].value = d1[i].value;\n sizeResult++;\n }\n }\n for (int i = 0; i < size2; i++) {\n int found = 0;\n for (int j = 0; j < sizeResult; j++) {\n if (result[j].key == d2[i].key) {\n result[j].value += d2[i].value;\n found = 1;\n break;\n }\n }\n if (!found) {\n result[sizeResult].key = d2[i].key;\n result[sizeResult].value = d2[i].value;\n sizeResult++;\n }\n }\n return result;\n}", + "test": "int main() {\n\n KeyValue d1[] = { {'a', 100}, {'b', 200}, {'c', 300} };\n\n KeyValue d2[] = { {'a', 300}, {'b', 200}, {'d', 400} };\n\n KeyValue *result1 = func0(d1, 3, d2, 3);\n\n assert(result1[0].value == 400 && result1[1].value == 400 && result1[2].value == 300 && result1[3].value == 400); // Since order may vary, checks are grouped by values only\n\n\n\n KeyValue d3[] = { {'a', 500}, {'b', 700}, {'c', 900} };\n\n KeyValue d4[] = { {'a', 500}, {'b', 600}, {'d', 900} };\n\n KeyValue *result2 = func0(d3, 3, d4, 3);\n\n assert(result2[0].value == 1000 && result2[1].value == 1300 && result2[2].value == 900 && result2[3].value == 900); // Since order may vary, checks are grouped by values only\n\n\n\n KeyValue d5[] = { {'a', 900}, {'b', 900}, {'d', 900} };\n\n KeyValue d6[] = { {'a', 900}, {'b', 900}, {'d', 900} };\n\n KeyValue *result3 = func0(d5, 3, d6, 3);\n\n assert(result3[0].value == 1800 && result3[1].value == 1800 && result3[2].value == 1800); // Since order may vary, checks are grouped by values only\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%r13\nmov %esi,%r12d\nmov %rdx,%rbp\nmov %ecx,%ebx\nlea (%rsi,%rcx,1),%edi\nmovslq %edi,%rdi\nshl $0x3,%rdi\ncallq 10b0 \ntest %r12d,%r12d\njle 1243 \nmov %r13,%r9\nlea -0x1(%r12),%edx\nlea 0x8(%r13,%rdx,8),%r11\nmov $0x0,%r8d\nlea 0x8(%rax),%r12\njmp 1219 \nmov 0x4(%r10),%edx\nadd %edx,0x4(%rcx)\njmp 1210 \nmovslq %r8d,%rdx\nlea (%rax,%rdx,8),%rdx\nmovzbl (%r9),%ecx\nmov %cl,(%rdx)\nmov 0x4(%r9),%ecx\nmov %ecx,0x4(%rdx)\nadd $0x1,%r8d\nadd $0x8,%r9\ncmp %r11,%r9\nje 1249 \ntest %r8d,%r8d\njle 11f8 \nmov %r9,%r10\nmovzbl (%r9),%esi\nmov %rax,%rdx\nlea -0x1(%r8),%ecx\nlea (%r12,%rcx,8),%rdi\nmov %rdx,%rcx\ncmp %sil,(%rdx)\nje 11ef \nadd $0x8,%rdx\ncmp %rdi,%rdx\njne 1230 \njmp 11f8 \nmov $0x0,%r8d\ntest %ebx,%ebx\njle 12b2 \nmov %rbp,%r9\nlea -0x1(%rbx),%edx\nlea 0x8(%rbp,%rdx,8),%r11\nlea 0x8(%rax),%rbx\njmp 1288 \nmov 0x4(%r10),%edx\nadd %edx,0x4(%rcx)\njmp 127f \nmovslq %r8d,%rdx\nlea (%rax,%rdx,8),%rdx\nmovzbl (%r9),%ecx\nmov %cl,(%rdx)\nmov 0x4(%r9),%ecx\nmov %ecx,0x4(%rdx)\nadd $0x1,%r8d\nadd $0x8,%r9\ncmp %r11,%r9\nje 12b2 \ntest %r8d,%r8d\njle 1267 \nmov %r9,%r10\nmovzbl (%r9),%esi\nmov %rax,%rdx\nlea -0x1(%r8),%ecx\nlea (%rbx,%rcx,8),%rdi\nmov %rdx,%rcx\ncmp %sil,(%rdx)\nje 125e \nadd $0x8,%rdx\ncmp %rdi,%rdx\njne 129f \njmp 1267 \nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r13, rdi\nmov r12d, esi\nmov rbp, rdx\nmov ebx, ecx\nlea edi, [rsi+rcx]\nmovsxd rdi, edi\nshl rdi, 3; size\ncall _malloc\nmov r8, rax\ntest r12d, r12d\njle short loc_1235\nmov rdi, r13\nmovsxd r12, r12d\nlea r10, [r13+r12*8+0]\nmov esi, 0\njmp short loc_1212\nloc_11EB:\nmov edx, [r9+4]\nadd [rax+4], edx\njmp short loc_1209\nloc_11F4:\nmovsxd rax, esi\nlea rax, [r8+rax*8]\nmovzx edx, byte ptr [rdi]\nmov [rax], dl\nmov edx, [rdi+4]\nmov [rax+4], edx\nadd esi, 1\nloc_1209:\nadd rdi, 8\ncmp rdi, r10\njz short loc_123A\nloc_1212:\ntest esi, esi\njle short loc_11F4\nmov r9, rdi\nmovzx edx, byte ptr [rdi]\nmov rax, r8\nmovsxd rcx, esi\nlea rcx, [r8+rcx*8]\nloc_1226:\ncmp [rax], dl\njz short loc_11EB\nadd rax, 8\ncmp rax, rcx\njnz short loc_1226\njmp short loc_11F4\nloc_1235:\nmov esi, 0\nloc_123A:\ntest ebx, ebx\njle short loc_1295\nmov rdi, rbp\nmovsxd rbx, ebx\nlea r10, [rbp+rbx*8+0]\njmp short loc_1272\nloc_124B:\nmov edx, [r9+4]\nadd [rax+4], edx\njmp short loc_1269\nloc_1254:\nmovsxd rax, esi\nlea rax, [r8+rax*8]\nmovzx edx, byte ptr [rdi]\nmov [rax], dl\nmov edx, [rdi+4]\nmov [rax+4], edx\nadd esi, 1\nloc_1269:\nadd rdi, 8\ncmp rdi, r10\njz short loc_1295\nloc_1272:\ntest esi, esi\njle short loc_1254\nmov r9, rdi\nmovzx edx, byte ptr [rdi]\nmov rax, r8\nmovsxd rcx, esi\nlea rcx, [r8+rcx*8]\nloc_1286:\ncmp [rax], dl\njz short loc_124B\nadd rax, 8\ncmp rax, rcx\njnz short loc_1286\njmp short loc_1254\nloc_1295:\nmov rax, r8\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "char *__fastcall func0(char *a1, int a2, char *a3, int a4)\n{\n char *v4; // r13\n char *v8; // r8\n int v9; // esi\n char *v10; // rax\n char *v11; // rax\n char *v12; // rdi\n char *v13; // rax\n char *v14; // rax\n\n v4 = a1;\n v8 = (char *)malloc(8LL * (a2 + a4));\n if ( a2 <= 0 )\n {\n v9 = 0;\n }\n else\n {\n v9 = 0;\n do\n {\n if ( v9 <= 0 )\n {\nLABEL_4:\n v10 = &v8[8 * v9];\n *v10 = *a1;\n *((_DWORD *)v10 + 1) = *((_DWORD *)a1 + 1);\n ++v9;\n }\n else\n {\n v11 = v8;\n while ( *v11 != *a1 )\n {\n v11 += 8;\n if ( v11 == &v8[8 * v9] )\n goto LABEL_4;\n }\n *((_DWORD *)v11 + 1) += *((_DWORD *)a1 + 1);\n }\n a1 += 8;\n }\n while ( a1 != &v4[8 * a2] );\n }\n if ( a4 > 0 )\n {\n v12 = a3;\n do\n {\n if ( v9 <= 0 )\n {\nLABEL_15:\n v13 = &v8[8 * v9];\n *v13 = *v12;\n *((_DWORD *)v13 + 1) = *((_DWORD *)v12 + 1);\n ++v9;\n }\n else\n {\n v14 = v8;\n while ( *v14 != *v12 )\n {\n v14 += 8;\n if ( v14 == &v8[8 * v9] )\n goto LABEL_15;\n }\n *((_DWORD *)v14 + 1) += *((_DWORD *)v12 + 1);\n }\n v12 += 8;\n }\n while ( v12 != &a3[8 * a4] );\n }\n return v8;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r13, rdi\nmov r12d, esi\nmov rbp, rdx\nmov ebx, ecx\nlea edi, [rsi+rcx]\nmovsxd rdi, edi\nshl rdi, 3; size\ncall _malloc\nmov r8, rax\ntest r12d, r12d\njle short loc_1235\nmov rdi, r13\nmovsxd r12, r12d\nlea r10, [r13+r12*8+0]\nmov esi, 0\njmp short loc_1212\nloc_11EB:\nmov edx, [r9+4]\nadd [rax+4], edx\njmp short loc_1209\nloc_11F4:\nmovsxd rax, esi\nlea rax, [r8+rax*8]\nmovzx edx, byte ptr [rdi]\nmov [rax], dl\nmov edx, [rdi+4]\nmov [rax+4], edx\nadd esi, 1\nloc_1209:\nadd rdi, 8\ncmp rdi, r10\njz short loc_123A\nloc_1212:\ntest esi, esi\njle short loc_11F4\nmov r9, rdi\nmovzx edx, byte ptr [rdi]\nmov rax, r8\nmovsxd rcx, esi\nlea rcx, [r8+rcx*8]\nloc_1226:\ncmp [rax], dl\njz short loc_11EB\nadd rax, 8\ncmp rax, rcx\njnz short loc_1226\njmp short loc_11F4\nloc_1235:\nmov esi, 0\nloc_123A:\ntest ebx, ebx\njle short loc_1295\nmov rdi, rbp\nmovsxd rbx, ebx\nlea r10, [rbp+rbx*8+0]\njmp short loc_1272\nloc_124B:\nmov edx, [r9+4]\nadd [rax+4], edx\njmp short loc_1269\nloc_1254:\nmovsxd rax, esi\nlea rax, [r8+rax*8]\nmovzx edx, byte ptr [rdi]\nmov [rax], dl\nmov edx, [rdi+4]\nmov [rax+4], edx\nadd esi, 1\nloc_1269:\nadd rdi, 8\ncmp rdi, r10\njz short loc_1295\nloc_1272:\ntest esi, esi\njle short loc_1254\nmov r9, rdi\nmovzx edx, byte ptr [rdi]\nmov rax, r8\nmovsxd rcx, esi\nlea rcx, [r8+rcx*8]\nloc_1286:\ncmp [rax], dl\njz short loc_124B\nadd rax, 8\ncmp rax, rcx\njnz short loc_1286\njmp short loc_1254\nloc_1295:\nmov rax, r8\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11A9(char *a1, int a2, char *a3, int a4)\n{\n char *v4; // r13\n char *v8; // r8\n int v9; // esi\n char *v10; // rax\n char *v11; // rax\n char *v12; // rdi\n char *v13; // rax\n char *v14; // rax\n\n v4 = a1;\n v8 = (char *)malloc(8LL * (a2 + a4));\n if ( a2 <= 0 )\n {\n v9 = 0;\n }\n else\n {\n v9 = 0;\n do\n {\n if ( v9 <= 0 )\n {\nLABEL_4:\n v10 = &v8[8 * v9];\n *v10 = *a1;\n *((_DWORD *)v10 + 1) = *((_DWORD *)a1 + 1);\n ++v9;\n }\n else\n {\n v11 = v8;\n while ( *v11 != *a1 )\n {\n v11 += 8;\n if ( v11 == &v8[8 * v9] )\n goto LABEL_4;\n }\n *((_DWORD *)v11 + 1) += *((_DWORD *)a1 + 1);\n }\n a1 += 8;\n }\n while ( a1 != &v4[8 * a2] );\n }\n if ( a4 > 0 )\n {\n v12 = a3;\n do\n {\n if ( v9 <= 0 )\n {\nLABEL_15:\n v13 = &v8[8 * v9];\n *v13 = *v12;\n *((_DWORD *)v13 + 1) = *((_DWORD *)v12 + 1);\n ++v9;\n }\n else\n {\n v14 = v8;\n while ( *v14 != *v12 )\n {\n v14 += 8;\n if ( v14 == &v8[8 * v9] )\n goto LABEL_15;\n }\n *((_DWORD *)v14 + 1) += *((_DWORD *)v12 + 1);\n }\n v12 += 8;\n }\n while ( v12 != &a3[8 * a4] );\n }\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11A9(char *a1, int a2, char *a3, int a4) {\n char *v4;\n char *v8;\n int v9;\n char *v10;\n char *v11;\n char *v12;\n char *v13;\n char *v14;\n v4 = a1;\n v8 = (char *)malloc(8LL * (a2 + a4));\n if (a2 <= 0) {\n v9 = 0;\n } else {\n v9 = 0;\n do {\n if (v9 <= 0) {\n LABEL_4:\n v10 = &v8[8 * v9];\n *v10 = *a1;\n *((uint32_t *)v10 + 1) = *((uint32_t *)a1 + 1);\n ++v9;\n } else {\n v11 = v8;\n while (*v11 != *a1) {\n v11 += 8;\n if (v11 == &v8[8 * v9]) goto LABEL_4;\n }\n *((uint32_t *)v11 + 1) += *((uint32_t *)a1 + 1);\n }\n a1 += 8;\n } while (a1 != &v4[8 * a2]);\n }\n if (a4 > 0) {\n v12 = a3;\n do {\n if (v9 <= 0) {\n LABEL_15:\n v13 = &v8[8 * v9];\n *v13 = *v12;\n *((uint32_t *)v13 + 1) = *((uint32_t *)v12 + 1);\n ++v9;\n } else {\n v14 = v8;\n while (*v14 != *v12) {\n v14 += 8;\n if (v14 == &v8[8 * v9]) goto LABEL_15;\n }\n *((uint32_t *)v14 + 1) += *((uint32_t *)v12 + 1);\n }\n v12 += 8;\n } while (v12 != &a3[8 * a4]);\n }\n return v8;\n}", + "ida_pseudo_norm": "char *func0(char *a1, int a2, char *a3, int a4) {\n char *v4;\n char *v8;\n int v9;\n char *v10;\n char *v11;\n char *v12;\n char *v13;\n char *v14;\n v4 = a1;\n v8 = (char *)malloc(8LL * (a2 + a4));\n if (a2 <= 0) {\n v9 = 0;\n } else {\n v9 = 0;\n do {\n if (v9 <= 0) {\n LABEL_4:\n v10 = &v8[8 * v9];\n *v10 = *a1;\n *((uint32_t *)v10 + 1) = *((uint32_t *)a1 + 1);\n ++v9;\n } else {\n v11 = v8;\n while (*v11 != *a1) {\n v11 += 8;\n if (v11 == &v8[8 * v9]) goto LABEL_4;\n }\n *((uint32_t *)v11 + 1) += *((uint32_t *)a1 + 1);\n }\n a1 += 8;\n } while (a1 != &v4[8 * a2]);\n }\n if (a4 > 0) {\n v12 = a3;\n do {\n if (v9 <= 0) {\n LABEL_15:\n v13 = &v8[8 * v9];\n *v13 = *v12;\n *((uint32_t *)v13 + 1) = *((uint32_t *)v12 + 1);\n ++v9;\n } else {\n v14 = v8;\n while (*v14 != *v12) {\n v14 += 8;\n if (v14 == &v8[8 * v9]) goto LABEL_15;\n }\n *((uint32_t *)v14 + 1) += *((uint32_t *)v12 + 1);\n }\n v12 += 8;\n } while (v12 != &a3[8 * a4]);\n }\n return v8;\n}" + }, + { + "index": 902, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char key;\n\n int value;\n\n} KeyValue;\n\n\n\n", + "func": "KeyValue *func0(KeyValue d1[], int size1, KeyValue d2[], int size2) {\n KeyValue *result = malloc((size1 + size2) * sizeof(KeyValue));\n int sizeResult = 0;\n for (int i = 0; i < size1; i++) {\n int found = 0;\n for (int j = 0; j < sizeResult; j++) {\n if (result[j].key == d1[i].key) {\n result[j].value += d1[i].value;\n found = 1;\n break;\n }\n }\n if (!found) {\n result[sizeResult].key = d1[i].key;\n result[sizeResult].value = d1[i].value;\n sizeResult++;\n }\n }\n for (int i = 0; i < size2; i++) {\n int found = 0;\n for (int j = 0; j < sizeResult; j++) {\n if (result[j].key == d2[i].key) {\n result[j].value += d2[i].value;\n found = 1;\n break;\n }\n }\n if (!found) {\n result[sizeResult].key = d2[i].key;\n result[sizeResult].value = d2[i].value;\n sizeResult++;\n }\n }\n return result;\n}", + "test": "int main() {\n\n KeyValue d1[] = { {'a', 100}, {'b', 200}, {'c', 300} };\n\n KeyValue d2[] = { {'a', 300}, {'b', 200}, {'d', 400} };\n\n KeyValue *result1 = func0(d1, 3, d2, 3);\n\n assert(result1[0].value == 400 && result1[1].value == 400 && result1[2].value == 300 && result1[3].value == 400); // Since order may vary, checks are grouped by values only\n\n\n\n KeyValue d3[] = { {'a', 500}, {'b', 700}, {'c', 900} };\n\n KeyValue d4[] = { {'a', 500}, {'b', 600}, {'d', 900} };\n\n KeyValue *result2 = func0(d3, 3, d4, 3);\n\n assert(result2[0].value == 1000 && result2[1].value == 1300 && result2[2].value == 900 && result2[3].value == 900); // Since order may vary, checks are grouped by values only\n\n\n\n KeyValue d5[] = { {'a', 900}, {'b', 900}, {'d', 900} };\n\n KeyValue d6[] = { {'a', 900}, {'b', 900}, {'d', 900} };\n\n KeyValue *result3 = func0(d5, 3, d6, 3);\n\n assert(result3[0].value == 1800 && result3[1].value == 1800 && result3[2].value == 1800); // Since order may vary, checks are grouped by values only\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov %esi,%r13d\npush %r12\nmov %ecx,%r12d\npush %rbp\nmov %rdx,%rbp\npush %rbx\nmov %rdi,%rbx\nlea (%rsi,%rcx,1),%edi\nmovslq %edi,%rdi\nshl $0x3,%rdi\nsub $0x8,%rsp\ncallq 10b0 \ntest %r13d,%r13d\njle 1584 \nlea -0x1(%r13),%edx\nmov %rbx,%r10\nxor %r9d,%r9d\nlea 0x8(%rbx,%rdx,8),%r11\nlea 0x8(%rax),%rdx\nnopl (%rax)\nmovzbl (%r10),%edi\ntest %r9d,%r9d\nje 1550 \nlea -0x1(%r9),%r8d\nmov %rax,%rsi\nlea (%rdx,%r8,8),%r8\njmp 14d1 \nnopw 0x0(%rax,%rax,1)\nadd $0x8,%rsi\ncmp %rsi,%r8\nje 1550 \ncmp %dil,(%rsi)\njne 14c8 \nmov 0x4(%r10),%ecx\nadd %ecx,0x4(%rsi)\nadd $0x8,%r10\ncmp %r11,%r10\njne 14a8 \ntest %r12d,%r12d\njle 153b \nlea -0x1(%r12),%edx\nlea 0x4(%rbp),%rdi\nlea 0xc(%rbp,%rdx,8),%r8\nlea 0x8(%rax),%r10\nnopl (%rax)\nmovzbl -0x4(%rdi),%ecx\ntest %r9d,%r9d\nje 1570 \nlea -0x1(%r9),%esi\nmov %rax,%rdx\nlea (%r10,%rsi,8),%rsi\njmp 1529 \nnopw %cs:0x0(%rax,%rax,1)\nadd $0x8,%rdx\ncmp %rdx,%rsi\nje 1570 \ncmp %cl,(%rdx)\njne 1520 \nmov (%rdi),%ecx\nadd %ecx,0x4(%rdx)\nadd $0x8,%rdi\ncmp %r8,%rdi\njne 1500 \nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopw %cs:0x0(%rax,%rax,1)\nmovslq %r9d,%rcx\nadd $0x1,%r9d\nlea (%rax,%rcx,8),%rsi\nmov 0x4(%r10),%ecx\nmov %dil,(%rsi)\nmov %ecx,0x4(%rsi)\njmpq 14dd \nnopw 0x0(%rax,%rax,1)\nmovslq %r9d,%rdx\nadd $0x1,%r9d\nlea (%rax,%rdx,8),%rdx\nmov %cl,(%rdx)\nmov (%rdi),%ecx\nmov %ecx,0x4(%rdx)\njmp 1532 \nxor %r9d,%r9d\njmpq 14e6 \nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r13\nmovsxd r13, esi\npush r12\nmovsxd r12, ecx\npush rbp\nmov rbp, rdi\nlea edi, [r13+r12+0]\npush rbx\nmovsxd rdi, edi\nmov rbx, rdx\nshl rdi, 3; size\nsub rsp, 8\ncall _malloc\nmov rdi, rax\ntest r13d, r13d\njle loc_1577\nmov rsi, rbp\nlea r10, [rbp+r13*8+0]\nxor r8d, r8d\nnop word ptr [rax+rax+00h]\nloc_14A8:\nmovsxd r9, r8d\nmovzx edx, byte ptr [rsi]\nlea rcx, [rdi+r9*8]\ntest r8d, r8d\njle short loc_14E8\nloc_14B7:\nmov rax, rdi\njmp short loc_14C9\nloc_14C0:\nadd rax, 8\ncmp rax, rcx\njz short loc_14E8\nloc_14C9:\ncmp [rax], dl\njnz short loc_14C0\nmov edx, [rsi+4]\nadd rsi, 8\nadd [rax+4], edx\ncmp r10, rsi\njz short loc_1501\nmovzx edx, byte ptr [rsi]\njmp short loc_14B7\nloc_14E8:\nlea rax, [rdi+r9*8]\nadd rsi, 8\nadd r8d, 1\nmov [rax], dl\nmov edx, [rsi-4]\nmov [rax+4], edx\ncmp r10, rsi\njnz short loc_14A8\nloc_1501:\ntest r12d, r12d\njle short loc_1569\nmov rsi, rbx\nlea r10, [rbx+r12*8]\nnop dword ptr [rax]\nloc_1510:\nmovsxd r9, r8d\nmovzx edx, byte ptr [rsi]\nlea rcx, [rdi+r9*8]\ntest r8d, r8d\njle short loc_1550\nloc_151F:\nmov rax, rdi\njmp short loc_1531\nloc_1528:\nadd rax, 8\ncmp rcx, rax\njz short loc_1550\nloc_1531:\ncmp [rax], dl\njnz short loc_1528\nmov edx, [rsi+4]\nadd rsi, 8\nadd [rax+4], edx\ncmp rsi, r10\njz short loc_1569\nmovzx edx, byte ptr [rsi]\njmp short loc_151F\nloc_1550:\nlea rax, [rdi+r9*8]\nadd rsi, 8\nadd r8d, 1\nmov [rax], dl\nmov edx, [rsi-4]\nmov [rax+4], edx\ncmp rsi, r10\njnz short loc_1510\nloc_1569:\nadd rsp, 8\nmov rax, rdi\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1577:\nxor r8d, r8d\njmp short loc_1501", + "ida_pseudo": "char *__fastcall func0(char *a1, int a2, char *a3, int a4)\n{\n __int64 v4; // r13\n __int64 v5; // r12\n char *v8; // rdi\n char *v9; // rsi\n char *v10; // r10\n int v11; // r8d\n char v12; // dl\n char *v13; // rax\n int v14; // edx\n char *v15; // rax\n char *v16; // rsi\n char *v17; // r10\n char v18; // dl\n char *v19; // rax\n int v20; // edx\n char *v21; // rax\n\n v4 = a2;\n v5 = a4;\n v8 = (char *)malloc(8LL * (a2 + a4));\n if ( a2 <= 0 )\n {\n v11 = 0;\n }\n else\n {\n v9 = a1;\n v10 = &a1[8 * v4];\n v11 = 0;\n while ( 1 )\n {\n v12 = *v9;\n if ( v11 > 0 )\n break;\nLABEL_9:\n v15 = &v8[8 * v11];\n v9 += 8;\n ++v11;\n *v15 = v12;\n *((_DWORD *)v15 + 1) = *((_DWORD *)v9 - 1);\n if ( v10 == v9 )\n goto LABEL_10;\n }\n while ( 1 )\n {\n v13 = v8;\n while ( *v13 != v12 )\n {\n v13 += 8;\n if ( v13 == &v8[8 * v11] )\n goto LABEL_9;\n }\n v14 = *((_DWORD *)v9 + 1);\n v9 += 8;\n *((_DWORD *)v13 + 1) += v14;\n if ( v10 == v9 )\n break;\n v12 = *v9;\n }\n }\nLABEL_10:\n if ( (int)v5 > 0 )\n {\n v16 = a3;\n v17 = &a3[8 * v5];\n while ( 1 )\n {\n v18 = *v16;\n if ( v11 > 0 )\n break;\nLABEL_18:\n v21 = &v8[8 * v11];\n v16 += 8;\n ++v11;\n *v21 = v18;\n *((_DWORD *)v21 + 1) = *((_DWORD *)v16 - 1);\n if ( v16 == v17 )\n return v8;\n }\n while ( 1 )\n {\n v19 = v8;\n while ( *v19 != v18 )\n {\n v19 += 8;\n if ( &v8[8 * v11] == v19 )\n goto LABEL_18;\n }\n v20 = *((_DWORD *)v16 + 1);\n v16 += 8;\n *((_DWORD *)v19 + 1) += v20;\n if ( v16 == v17 )\n break;\n v18 = *v16;\n }\n }\n return v8;\n}", + "ida_strip_asm": "sub_1460:\nendbr64\npush r13\nmovsxd r13, esi\npush r12\nmovsxd r12, ecx\npush rbp\nmov rbp, rdi\nlea edi, [r13+r12+0]\npush rbx\nmovsxd rdi, edi\nmov rbx, rdx\nshl rdi, 3; size\nsub rsp, 8\ncall _malloc\nmov rdi, rax\ntest r13d, r13d\njle loc_1577\nmov rsi, rbp\nlea r10, [rbp+r13*8+0]\nxor r8d, r8d\nnop word ptr [rax+rax+00h]\nloc_14A8:\nmovsxd r9, r8d\nmovzx edx, byte ptr [rsi]\nlea rcx, [rdi+r9*8]\ntest r8d, r8d\njle short loc_14E8\nloc_14B7:\nmov rax, rdi\njmp short loc_14C9\nloc_14C0:\nadd rax, 8\ncmp rax, rcx\njz short loc_14E8\nloc_14C9:\ncmp [rax], dl\njnz short loc_14C0\nmov edx, [rsi+4]\nadd rsi, 8\nadd [rax+4], edx\ncmp r10, rsi\njz short loc_1501\nmovzx edx, byte ptr [rsi]\njmp short loc_14B7\nloc_14E8:\nlea rax, [rdi+r9*8]\nadd rsi, 8\nadd r8d, 1\nmov [rax], dl\nmov edx, [rsi-4]\nmov [rax+4], edx\ncmp r10, rsi\njnz short loc_14A8\nloc_1501:\ntest r12d, r12d\njle short loc_1569\nmov rsi, rbx\nlea r10, [rbx+r12*8]\nnop dword ptr [rax]\nloc_1510:\nmovsxd r9, r8d\nmovzx edx, byte ptr [rsi]\nlea rcx, [rdi+r9*8]\ntest r8d, r8d\njle short loc_1550\nloc_151F:\nmov rax, rdi\njmp short loc_1531\nloc_1528:\nadd rax, 8\ncmp rcx, rax\njz short loc_1550\nloc_1531:\ncmp [rax], dl\njnz short loc_1528\nmov edx, [rsi+4]\nadd rsi, 8\nadd [rax+4], edx\ncmp rsi, r10\njz short loc_1569\nmovzx edx, byte ptr [rsi]\njmp short loc_151F\nloc_1550:\nlea rax, [rdi+r9*8]\nadd rsi, 8\nadd r8d, 1\nmov [rax], dl\nmov edx, [rsi-4]\nmov [rax+4], edx\ncmp rsi, r10\njnz short loc_1510\nloc_1569:\nadd rsp, 8\nmov rax, rdi\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1577:\nxor r8d, r8d\njmp short loc_1501", + "ida_strip_pseudo": "char *__fastcall sub_1460(char *a1, int a2, char *a3, int a4)\n{\n __int64 v4; // r13\n __int64 v5; // r12\n char *v8; // rdi\n char *v9; // rsi\n char *v10; // r10\n int v11; // r8d\n char v12; // dl\n char *v13; // rax\n int v14; // edx\n char *v15; // rax\n char *v16; // rsi\n char *v17; // r10\n char v18; // dl\n char *v19; // rax\n int v20; // edx\n char *v21; // rax\n\n v4 = a2;\n v5 = a4;\n v8 = (char *)malloc(8LL * (a2 + a4));\n if ( a2 <= 0 )\n {\n v11 = 0;\n }\n else\n {\n v9 = a1;\n v10 = &a1[8 * v4];\n v11 = 0;\n while ( 1 )\n {\n v12 = *v9;\n if ( v11 > 0 )\n break;\nLABEL_9:\n v15 = &v8[8 * v11];\n v9 += 8;\n ++v11;\n *v15 = v12;\n *((_DWORD *)v15 + 1) = *((_DWORD *)v9 - 1);\n if ( v10 == v9 )\n goto LABEL_10;\n }\n while ( 1 )\n {\n v13 = v8;\n while ( *v13 != v12 )\n {\n v13 += 8;\n if ( v13 == &v8[8 * v11] )\n goto LABEL_9;\n }\n v14 = *((_DWORD *)v9 + 1);\n v9 += 8;\n *((_DWORD *)v13 + 1) += v14;\n if ( v10 == v9 )\n break;\n v12 = *v9;\n }\n }\nLABEL_10:\n if ( (int)v5 > 0 )\n {\n v16 = a3;\n v17 = &a3[8 * v5];\n while ( 1 )\n {\n v18 = *v16;\n if ( v11 > 0 )\n break;\nLABEL_18:\n v21 = &v8[8 * v11];\n v16 += 8;\n ++v11;\n *v21 = v18;\n *((_DWORD *)v21 + 1) = *((_DWORD *)v16 - 1);\n if ( v16 == v17 )\n return v8;\n }\n while ( 1 )\n {\n v19 = v8;\n while ( *v19 != v18 )\n {\n v19 += 8;\n if ( &v8[8 * v11] == v19 )\n goto LABEL_18;\n }\n v20 = *((_DWORD *)v16 + 1);\n v16 += 8;\n *((_DWORD *)v19 + 1) += v20;\n if ( v16 == v17 )\n break;\n v18 = *v16;\n }\n }\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1460(char *a1, int a2, char *a3, int a4) {\n long long v4;\n long long v5;\n char *v8;\n char *v9;\n char *v10;\n int v11;\n char v12;\n char *v13;\n int v14;\n char *v15;\n char *v16;\n char *v17;\n char v18;\n char *v19;\n int v20;\n char *v21;\n v4 = a2;\n v5 = a4;\n v8 = (char *)malloc(8LL * (a2 + a4));\n if (a2 <= 0) {\n v11 = 0;\n } else {\n v9 = a1;\n v10 = &a1[8 * v4];\n v11 = 0;\n while (1) {\n v12 = *v9;\n if (v11 > 0) break;\n LABEL_9:\n v15 = &v8[8 * v11];\n v9 += 8;\n ++v11;\n *v15 = v12;\n *((uint32_t *)v15 + 1) = *((uint32_t *)v9 - 1);\n if (v10 == v9) goto LABEL_10;\n }\n while (1) {\n v13 = v8;\n while (*v13 != v12) {\n v13 += 8;\n if (v13 == &v8[8 * v11]) goto LABEL_9;\n }\n v14 = *((uint32_t *)v9 + 1);\n v9 += 8;\n *((uint32_t *)v13 + 1) += v14;\n if (v10 == v9) break;\n v12 = *v9;\n }\n }\nLABEL_10:\n if ((int)v5 > 0) {\n v16 = a3;\n v17 = &a3[8 * v5];\n while (1) {\n v18 = *v16;\n if (v11 > 0) break;\n LABEL_18:\n v21 = &v8[8 * v11];\n v16 += 8;\n ++v11;\n *v21 = v18;\n *((uint32_t *)v21 + 1) = *((uint32_t *)v16 - 1);\n if (v16 == v17) return v8;\n }\n while (1) {\n v19 = v8;\n while (*v19 != v18) {\n v19 += 8;\n if (&v8[8 * v11] == v19) goto LABEL_18;\n }\n v20 = *((uint32_t *)v16 + 1);\n v16 += 8;\n *((uint32_t *)v19 + 1) += v20;\n if (v16 == v17) break;\n v18 = *v16;\n }\n }\n return v8;\n}", + "ida_pseudo_norm": "char *func0(char *a1, int a2, char *a3, int a4) {\n long long v4;\n long long v5;\n char *v8;\n char *v9;\n char *v10;\n int v11;\n char v12;\n char *v13;\n int v14;\n char *v15;\n char *v16;\n char *v17;\n char v18;\n char *v19;\n int v20;\n char *v21;\n v4 = a2;\n v5 = a4;\n v8 = (char *)malloc(8LL * (a2 + a4));\n if (a2 <= 0) {\n v11 = 0;\n } else {\n v9 = a1;\n v10 = &a1[8 * v4];\n v11 = 0;\n while (1) {\n v12 = *v9;\n if (v11 > 0) break;\n LABEL_9:\n v15 = &v8[8 * v11];\n v9 += 8;\n ++v11;\n *v15 = v12;\n *((uint32_t *)v15 + 1) = *((uint32_t *)v9 - 1);\n if (v10 == v9) goto LABEL_10;\n }\n while (1) {\n v13 = v8;\n while (*v13 != v12) {\n v13 += 8;\n if (v13 == &v8[8 * v11]) goto LABEL_9;\n }\n v14 = *((uint32_t *)v9 + 1);\n v9 += 8;\n *((uint32_t *)v13 + 1) += v14;\n if (v10 == v9) break;\n v12 = *v9;\n }\n }\nLABEL_10:\n if ((int)v5 > 0) {\n v16 = a3;\n v17 = &a3[8 * v5];\n while (1) {\n v18 = *v16;\n if (v11 > 0) break;\n LABEL_18:\n v21 = &v8[8 * v11];\n v16 += 8;\n ++v11;\n *v21 = v18;\n *((uint32_t *)v21 + 1) = *((uint32_t *)v16 - 1);\n if (v16 == v17) return v8;\n }\n while (1) {\n v19 = v8;\n while (*v19 != v18) {\n v19 += 8;\n if (&v8[8 * v11] == v19) goto LABEL_18;\n }\n v20 = *((uint32_t *)v16 + 1);\n v16 += 8;\n *((uint32_t *)v19 + 1) += v20;\n if (v16 == v17) break;\n v18 = *v16;\n }\n }\n return v8;\n}" + }, + { + "index": 902, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char key;\n\n int value;\n\n} KeyValue;\n\n\n\n", + "func": "KeyValue *func0(KeyValue d1[], int size1, KeyValue d2[], int size2) {\n KeyValue *result = malloc((size1 + size2) * sizeof(KeyValue));\n int sizeResult = 0;\n for (int i = 0; i < size1; i++) {\n int found = 0;\n for (int j = 0; j < sizeResult; j++) {\n if (result[j].key == d1[i].key) {\n result[j].value += d1[i].value;\n found = 1;\n break;\n }\n }\n if (!found) {\n result[sizeResult].key = d1[i].key;\n result[sizeResult].value = d1[i].value;\n sizeResult++;\n }\n }\n for (int i = 0; i < size2; i++) {\n int found = 0;\n for (int j = 0; j < sizeResult; j++) {\n if (result[j].key == d2[i].key) {\n result[j].value += d2[i].value;\n found = 1;\n break;\n }\n }\n if (!found) {\n result[sizeResult].key = d2[i].key;\n result[sizeResult].value = d2[i].value;\n sizeResult++;\n }\n }\n return result;\n}", + "test": "int main() {\n\n KeyValue d1[] = { {'a', 100}, {'b', 200}, {'c', 300} };\n\n KeyValue d2[] = { {'a', 300}, {'b', 200}, {'d', 400} };\n\n KeyValue *result1 = func0(d1, 3, d2, 3);\n\n assert(result1[0].value == 400 && result1[1].value == 400 && result1[2].value == 300 && result1[3].value == 400); // Since order may vary, checks are grouped by values only\n\n\n\n KeyValue d3[] = { {'a', 500}, {'b', 700}, {'c', 900} };\n\n KeyValue d4[] = { {'a', 500}, {'b', 600}, {'d', 900} };\n\n KeyValue *result2 = func0(d3, 3, d4, 3);\n\n assert(result2[0].value == 1000 && result2[1].value == 1300 && result2[2].value == 900 && result2[3].value == 900); // Since order may vary, checks are grouped by values only\n\n\n\n KeyValue d5[] = { {'a', 900}, {'b', 900}, {'d', 900} };\n\n KeyValue d6[] = { {'a', 900}, {'b', 900}, {'d', 900} };\n\n KeyValue *result3 = func0(d5, 3, d6, 3);\n\n assert(result3[0].value == 1800 && result3[1].value == 1800 && result3[2].value == 1800); // Since order may vary, checks are grouped by values only\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov %esi,%r13d\npush %r12\nmov %ecx,%r12d\npush %rbp\nmov %rdx,%rbp\npush %rbx\nmov %rdi,%rbx\nlea (%rsi,%rcx,1),%edi\nmovslq %edi,%rdi\nshl $0x3,%rdi\nsub $0x8,%rsp\ncallq 10b0 \ntest %r13d,%r13d\njle 1584 \nlea -0x1(%r13),%edx\nmov %rbx,%r10\nxor %r9d,%r9d\nlea 0x8(%rbx,%rdx,8),%r11\nlea 0x8(%rax),%rdx\nnopl (%rax)\nmovzbl (%r10),%edi\ntest %r9d,%r9d\nje 1550 \nlea -0x1(%r9),%r8d\nmov %rax,%rsi\nlea (%rdx,%r8,8),%r8\njmp 14d1 \nnopw 0x0(%rax,%rax,1)\nadd $0x8,%rsi\ncmp %rsi,%r8\nje 1550 \ncmp %dil,(%rsi)\njne 14c8 \nmov 0x4(%r10),%ecx\nadd %ecx,0x4(%rsi)\nadd $0x8,%r10\ncmp %r11,%r10\njne 14a8 \ntest %r12d,%r12d\njle 153b \nlea -0x1(%r12),%edx\nlea 0x4(%rbp),%rdi\nlea 0xc(%rbp,%rdx,8),%r8\nlea 0x8(%rax),%r10\nnopl (%rax)\nmovzbl -0x4(%rdi),%ecx\ntest %r9d,%r9d\nje 1570 \nlea -0x1(%r9),%esi\nmov %rax,%rdx\nlea (%r10,%rsi,8),%rsi\njmp 1529 \nnopw %cs:0x0(%rax,%rax,1)\nadd $0x8,%rdx\ncmp %rdx,%rsi\nje 1570 \ncmp %cl,(%rdx)\njne 1520 \nmov (%rdi),%ecx\nadd %ecx,0x4(%rdx)\nadd $0x8,%rdi\ncmp %r8,%rdi\njne 1500 \nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopw %cs:0x0(%rax,%rax,1)\nmovslq %r9d,%rcx\nadd $0x1,%r9d\nlea (%rax,%rcx,8),%rsi\nmov 0x4(%r10),%ecx\nmov %dil,(%rsi)\nmov %ecx,0x4(%rsi)\njmpq 14dd \nnopw 0x0(%rax,%rax,1)\nmovslq %r9d,%rdx\nadd $0x1,%r9d\nlea (%rax,%rdx,8),%rdx\nmov %cl,(%rdx)\nmov (%rdi),%ecx\nmov %ecx,0x4(%rdx)\njmp 1532 \nxor %r9d,%r9d\njmpq 14e6 \nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r13\nmovsxd r13, esi\npush r12\nmovsxd r12, ecx\npush rbp\nmov rbp, rdi\nlea edi, [r13+r12+0]\npush rbx\nmovsxd rdi, edi\nmov rbx, rdx\nshl rdi, 3; size\nsub rsp, 8\ncall _malloc\nmov rdi, rax\ntest r13d, r13d\njle loc_1577\nmov rsi, rbp\nlea r10, [rbp+r13*8+0]\nxor r8d, r8d\nnop word ptr [rax+rax+00h]\nloc_14A8:\nmovsxd r9, r8d\nmovzx edx, byte ptr [rsi]\nlea rcx, [rdi+r9*8]\ntest r8d, r8d\njle short loc_14E8\nloc_14B7:\nmov rax, rdi\njmp short loc_14C9\nloc_14C0:\nadd rax, 8\ncmp rcx, rax\njz short loc_14E8\nloc_14C9:\ncmp [rax], dl\njnz short loc_14C0\nmov edx, [rsi+4]\nadd rsi, 8\nadd [rax+4], edx\ncmp r10, rsi\njz short loc_1501\nmovzx edx, byte ptr [rsi]\njmp short loc_14B7\nloc_14E8:\nlea rax, [rdi+r9*8]\nadd rsi, 8\nadd r8d, 1\nmov [rax], dl\nmov edx, [rsi-4]\nmov [rax+4], edx\ncmp rsi, r10\njnz short loc_14A8\nloc_1501:\ntest r12d, r12d\njle short loc_1569\nmov rsi, rbx\nlea r10, [rbx+r12*8]\nnop dword ptr [rax]\nloc_1510:\nmovsxd r9, r8d\nmovzx edx, byte ptr [rsi]\nlea rcx, [rdi+r9*8]\ntest r8d, r8d\njle short loc_1550\nloc_151F:\nmov rax, rdi\njmp short loc_1531\nloc_1528:\nadd rax, 8\ncmp rcx, rax\njz short loc_1550\nloc_1531:\ncmp [rax], dl\njnz short loc_1528\nmov edx, [rsi+4]\nadd rsi, 8\nadd [rax+4], edx\ncmp rsi, r10\njz short loc_1569\nmovzx edx, byte ptr [rsi]\njmp short loc_151F\nloc_1550:\nlea rax, [rdi+r9*8]\nadd rsi, 8\nadd r8d, 1\nmov [rax], dl\nmov edx, [rsi-4]\nmov [rax+4], edx\ncmp r10, rsi\njnz short loc_1510\nloc_1569:\nadd rsp, 8\nmov rax, rdi\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1577:\nxor r8d, r8d\njmp short loc_1501", + "ida_pseudo": "char *__fastcall func0(char *a1, int a2, char *a3, int a4)\n{\n __int64 v4; // r13\n __int64 v5; // r12\n char *v8; // rdi\n char *v9; // rsi\n char *v10; // r10\n int v11; // r8d\n char v12; // dl\n char *v13; // rax\n int v14; // edx\n char *v15; // rax\n char *v16; // rsi\n char *v17; // r10\n char v18; // dl\n char *v19; // rax\n int v20; // edx\n char *v21; // rax\n\n v4 = a2;\n v5 = a4;\n v8 = (char *)malloc(8LL * (a2 + a4));\n if ( a2 <= 0 )\n {\n v11 = 0;\n }\n else\n {\n v9 = a1;\n v10 = &a1[8 * v4];\n v11 = 0;\n while ( 1 )\n {\n v12 = *v9;\n if ( v11 > 0 )\n break;\nLABEL_9:\n v15 = &v8[8 * v11];\n v9 += 8;\n ++v11;\n *v15 = v12;\n *((_DWORD *)v15 + 1) = *((_DWORD *)v9 - 1);\n if ( v9 == v10 )\n goto LABEL_10;\n }\n while ( 1 )\n {\n v13 = v8;\n while ( *v13 != v12 )\n {\n v13 += 8;\n if ( &v8[8 * v11] == v13 )\n goto LABEL_9;\n }\n v14 = *((_DWORD *)v9 + 1);\n v9 += 8;\n *((_DWORD *)v13 + 1) += v14;\n if ( v10 == v9 )\n break;\n v12 = *v9;\n }\n }\nLABEL_10:\n if ( (int)v5 > 0 )\n {\n v16 = a3;\n v17 = &a3[8 * v5];\n while ( 1 )\n {\n v18 = *v16;\n if ( v11 > 0 )\n break;\nLABEL_18:\n v21 = &v8[8 * v11];\n v16 += 8;\n ++v11;\n *v21 = v18;\n *((_DWORD *)v21 + 1) = *((_DWORD *)v16 - 1);\n if ( v17 == v16 )\n return v8;\n }\n while ( 1 )\n {\n v19 = v8;\n while ( *v19 != v18 )\n {\n v19 += 8;\n if ( &v8[8 * v11] == v19 )\n goto LABEL_18;\n }\n v20 = *((_DWORD *)v16 + 1);\n v16 += 8;\n *((_DWORD *)v19 + 1) += v20;\n if ( v16 == v17 )\n break;\n v18 = *v16;\n }\n }\n return v8;\n}", + "ida_strip_asm": "sub_1460:\nendbr64\npush r13\nmovsxd r13, esi\npush r12\nmovsxd r12, ecx\npush rbp\nmov rbp, rdi\nlea edi, [r13+r12+0]\npush rbx\nmovsxd rdi, edi\nmov rbx, rdx\nshl rdi, 3; size\nsub rsp, 8\ncall _malloc\nmov rdi, rax\ntest r13d, r13d\njle loc_1577\nmov rsi, rbp\nlea r10, [rbp+r13*8+0]\nxor r8d, r8d\nnop word ptr [rax+rax+00h]\nloc_14A8:\nmovsxd r9, r8d\nmovzx edx, byte ptr [rsi]\nlea rcx, [rdi+r9*8]\ntest r8d, r8d\njle short loc_14E8\nloc_14B7:\nmov rax, rdi\njmp short loc_14C9\nloc_14C0:\nadd rax, 8\ncmp rcx, rax\njz short loc_14E8\nloc_14C9:\ncmp [rax], dl\njnz short loc_14C0\nmov edx, [rsi+4]\nadd rsi, 8\nadd [rax+4], edx\ncmp r10, rsi\njz short loc_1501\nmovzx edx, byte ptr [rsi]\njmp short loc_14B7\nloc_14E8:\nlea rax, [rdi+r9*8]\nadd rsi, 8\nadd r8d, 1\nmov [rax], dl\nmov edx, [rsi-4]\nmov [rax+4], edx\ncmp rsi, r10\njnz short loc_14A8\nloc_1501:\ntest r12d, r12d\njle short loc_1569\nmov rsi, rbx\nlea r10, [rbx+r12*8]\nnop dword ptr [rax]\nloc_1510:\nmovsxd r9, r8d\nmovzx edx, byte ptr [rsi]\nlea rcx, [rdi+r9*8]\ntest r8d, r8d\njle short loc_1550\nloc_151F:\nmov rax, rdi\njmp short loc_1531\nloc_1528:\nadd rax, 8\ncmp rcx, rax\njz short loc_1550\nloc_1531:\ncmp [rax], dl\njnz short loc_1528\nmov edx, [rsi+4]\nadd rsi, 8\nadd [rax+4], edx\ncmp rsi, r10\njz short loc_1569\nmovzx edx, byte ptr [rsi]\njmp short loc_151F\nloc_1550:\nlea rax, [rdi+r9*8]\nadd rsi, 8\nadd r8d, 1\nmov [rax], dl\nmov edx, [rsi-4]\nmov [rax+4], edx\ncmp r10, rsi\njnz short loc_1510\nloc_1569:\nadd rsp, 8\nmov rax, rdi\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_1577:\nxor r8d, r8d\njmp short loc_1501", + "ida_strip_pseudo": "char *__fastcall sub_1460(char *a1, int a2, char *a3, int a4)\n{\n __int64 v4; // r13\n __int64 v5; // r12\n char *v8; // rdi\n char *v9; // rsi\n char *v10; // r10\n int v11; // r8d\n char v12; // dl\n char *v13; // rax\n int v14; // edx\n char *v15; // rax\n char *v16; // rsi\n char *v17; // r10\n char v18; // dl\n char *v19; // rax\n int v20; // edx\n char *v21; // rax\n\n v4 = a2;\n v5 = a4;\n v8 = (char *)malloc(8LL * (a2 + a4));\n if ( a2 <= 0 )\n {\n v11 = 0;\n }\n else\n {\n v9 = a1;\n v10 = &a1[8 * v4];\n v11 = 0;\n while ( 1 )\n {\n v12 = *v9;\n if ( v11 > 0 )\n break;\nLABEL_9:\n v15 = &v8[8 * v11];\n v9 += 8;\n ++v11;\n *v15 = v12;\n *((_DWORD *)v15 + 1) = *((_DWORD *)v9 - 1);\n if ( v9 == v10 )\n goto LABEL_10;\n }\n while ( 1 )\n {\n v13 = v8;\n while ( *v13 != v12 )\n {\n v13 += 8;\n if ( &v8[8 * v11] == v13 )\n goto LABEL_9;\n }\n v14 = *((_DWORD *)v9 + 1);\n v9 += 8;\n *((_DWORD *)v13 + 1) += v14;\n if ( v10 == v9 )\n break;\n v12 = *v9;\n }\n }\nLABEL_10:\n if ( (int)v5 > 0 )\n {\n v16 = a3;\n v17 = &a3[8 * v5];\n while ( 1 )\n {\n v18 = *v16;\n if ( v11 > 0 )\n break;\nLABEL_18:\n v21 = &v8[8 * v11];\n v16 += 8;\n ++v11;\n *v21 = v18;\n *((_DWORD *)v21 + 1) = *((_DWORD *)v16 - 1);\n if ( v17 == v16 )\n return v8;\n }\n while ( 1 )\n {\n v19 = v8;\n while ( *v19 != v18 )\n {\n v19 += 8;\n if ( &v8[8 * v11] == v19 )\n goto LABEL_18;\n }\n v20 = *((_DWORD *)v16 + 1);\n v16 += 8;\n *((_DWORD *)v19 + 1) += v20;\n if ( v16 == v17 )\n break;\n v18 = *v16;\n }\n }\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1460(char *a1, int a2, char *a3, int a4) {\n long long v4;\n long long v5;\n char *v8;\n char *v9;\n char *v10;\n int v11;\n char v12;\n char *v13;\n int v14;\n char *v15;\n char *v16;\n char *v17;\n char v18;\n char *v19;\n int v20;\n char *v21;\n v4 = a2;\n v5 = a4;\n v8 = (char *)malloc(8LL * (a2 + a4));\n if (a2 <= 0) {\n v11 = 0;\n } else {\n v9 = a1;\n v10 = &a1[8 * v4];\n v11 = 0;\n while (1) {\n v12 = *v9;\n if (v11 > 0) break;\n LABEL_9:\n v15 = &v8[8 * v11];\n v9 += 8;\n ++v11;\n *v15 = v12;\n *((uint32_t *)v15 + 1) = *((uint32_t *)v9 - 1);\n if (v9 == v10) goto LABEL_10;\n }\n while (1) {\n v13 = v8;\n while (*v13 != v12) {\n v13 += 8;\n if (&v8[8 * v11] == v13) goto LABEL_9;\n }\n v14 = *((uint32_t *)v9 + 1);\n v9 += 8;\n *((uint32_t *)v13 + 1) += v14;\n if (v10 == v9) break;\n v12 = *v9;\n }\n }\nLABEL_10:\n if ((int)v5 > 0) {\n v16 = a3;\n v17 = &a3[8 * v5];\n while (1) {\n v18 = *v16;\n if (v11 > 0) break;\n LABEL_18:\n v21 = &v8[8 * v11];\n v16 += 8;\n ++v11;\n *v21 = v18;\n *((uint32_t *)v21 + 1) = *((uint32_t *)v16 - 1);\n if (v17 == v16) return v8;\n }\n while (1) {\n v19 = v8;\n while (*v19 != v18) {\n v19 += 8;\n if (&v8[8 * v11] == v19) goto LABEL_18;\n }\n v20 = *((uint32_t *)v16 + 1);\n v16 += 8;\n *((uint32_t *)v19 + 1) += v20;\n if (v16 == v17) break;\n v18 = *v16;\n }\n }\n return v8;\n}", + "ida_pseudo_norm": "char *func0(char *a1, int a2, char *a3, int a4) {\n long long v4;\n long long v5;\n char *v8;\n char *v9;\n char *v10;\n int v11;\n char v12;\n char *v13;\n int v14;\n char *v15;\n char *v16;\n char *v17;\n char v18;\n char *v19;\n int v20;\n char *v21;\n v4 = a2;\n v5 = a4;\n v8 = (char *)malloc(8LL * (a2 + a4));\n if (a2 <= 0) {\n v11 = 0;\n } else {\n v9 = a1;\n v10 = &a1[8 * v4];\n v11 = 0;\n while (1) {\n v12 = *v9;\n if (v11 > 0) break;\n LABEL_9:\n v15 = &v8[8 * v11];\n v9 += 8;\n ++v11;\n *v15 = v12;\n *((uint32_t *)v15 + 1) = *((uint32_t *)v9 - 1);\n if (v9 == v10) goto LABEL_10;\n }\n while (1) {\n v13 = v8;\n while (*v13 != v12) {\n v13 += 8;\n if (&v8[8 * v11] == v13) goto LABEL_9;\n }\n v14 = *((uint32_t *)v9 + 1);\n v9 += 8;\n *((uint32_t *)v13 + 1) += v14;\n if (v10 == v9) break;\n v12 = *v9;\n }\n }\nLABEL_10:\n if ((int)v5 > 0) {\n v16 = a3;\n v17 = &a3[8 * v5];\n while (1) {\n v18 = *v16;\n if (v11 > 0) break;\n LABEL_18:\n v21 = &v8[8 * v11];\n v16 += 8;\n ++v11;\n *v21 = v18;\n *((uint32_t *)v21 + 1) = *((uint32_t *)v16 - 1);\n if (v17 == v16) return v8;\n }\n while (1) {\n v19 = v8;\n while (*v19 != v18) {\n v19 += 8;\n if (&v8[8 * v11] == v19) goto LABEL_18;\n }\n v20 = *((uint32_t *)v16 + 1);\n v16 += 8;\n *((uint32_t *)v19 + 1) += v20;\n if (v16 == v17) break;\n v18 = *v16;\n }\n }\n return v8;\n}" + }, + { + "index": 903, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int cnt = 0;\n for (int i = 1; i <= n; i++) {\n int temp = i;\n while (temp) {\n if (temp % 2 == 0) {\n cnt++;\n }\n temp = temp / 2;\n }\n }\n return cnt;\n}", + "test": "int main() {\n\n assert(func0(2) == 1);\n\n assert(func0(5) == 4);\n\n assert(func0(14) == 17);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmovl $0x0,-0xc(%rbp)\nmovl $0x1,-0x8(%rbp)\njmp 1193 \nmov -0x8(%rbp),%eax\nmov %eax,-0x4(%rbp)\njmp 1189 \nmov -0x4(%rbp),%eax\nand $0x1,%eax\ntest %eax,%eax\njne 117a \naddl $0x1,-0xc(%rbp)\nmov -0x4(%rbp),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nmov %eax,-0x4(%rbp)\ncmpl $0x0,-0x4(%rbp)\njne 116c \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x14(%rbp),%eax\njle 1164 \nmov -0xc(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 1\njmp short loc_1193\nloc_1164:\nmov eax, [rbp+var_8]\nmov [rbp+var_4], eax\njmp short loc_1189\nloc_116C:\nmov eax, [rbp+var_4]\nand eax, 1\ntest eax, eax\njnz short loc_117A\nadd [rbp+var_C], 1\nloc_117A:\nmov eax, [rbp+var_4]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_4], eax\nloc_1189:\ncmp [rbp+var_4], 0\njnz short loc_116C\nadd [rbp+var_8], 1\nloc_1193:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_14]\njle short loc_1164\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v2; // [rsp+8h] [rbp-Ch]\n int i; // [rsp+Ch] [rbp-8h]\n int j; // [rsp+10h] [rbp-4h]\n\n v2 = 0;\n for ( i = 1; i <= a1; ++i )\n {\n for ( j = i; j; j /= 2 )\n {\n if ( (j & 1) == 0 )\n ++v2;\n }\n }\n return v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_C], 0\nmov [rbp+var_8], 1\njmp short loc_1193\nloc_1164:\nmov eax, [rbp+var_8]\nmov [rbp+var_4], eax\njmp short loc_1189\nloc_116C:\nmov eax, [rbp+var_4]\nand eax, 1\ntest eax, eax\njnz short loc_117A\nadd [rbp+var_C], 1\nloc_117A:\nmov eax, [rbp+var_4]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_4], eax\nloc_1189:\ncmp [rbp+var_4], 0\njnz short loc_116C\nadd [rbp+var_8], 1\nloc_1193:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_14]\njle short loc_1164\nmov eax, [rbp+var_C]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n unsigned int v2; // [rsp+8h] [rbp-Ch]\n int i; // [rsp+Ch] [rbp-8h]\n int j; // [rsp+10h] [rbp-4h]\n\n v2 = 0;\n for ( i = 1; i <= a1; ++i )\n {\n for ( j = i; j; j /= 2 )\n {\n if ( (j & 1) == 0 )\n ++v2;\n }\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n unsigned int v2;\n int i;\n int j;\n v2 = 0;\n for (i = 1; i <= a1; ++i) {\n for (j = i; j; j /= 2) {\n if ((j & 1) == 0) ++v2;\n }\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v2;\n int i;\n int j;\n v2 = 0;\n for (i = 1; i <= a1; ++i) {\n for (j = i; j; j /= 2) {\n if ((j & 1) == 0) ++v2;\n }\n }\n return v2;\n}" + }, + { + "index": 903, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int cnt = 0;\n for (int i = 1; i <= n; i++) {\n int temp = i;\n while (temp) {\n if (temp % 2 == 0) {\n cnt++;\n }\n temp = temp / 2;\n }\n }\n return cnt;\n}", + "test": "int main() {\n\n assert(func0(2) == 1);\n\n assert(func0(5) == 4);\n\n assert(func0(14) == 17);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x1,%esi\nmov $0x0,%ecx\ntest %edi,%edi\njg 1160 \njmp 1185 \nadd $0x1,%esi\nmov %esi,%edx\ntest %esi,%esi\nje 115d \nmov %edx,%eax\nand $0x1,%eax\ncmp $0x1,%eax\nadc $0x0,%ecx\nmov %edx,%eax\nshr $0x1f,%eax\nadd %edx,%eax\nsar %eax\nmov %eax,%edx\njne 1166 \nlea 0x1(%rsi),%eax\ncmp %eax,%edi\njge 115d \nmov %ecx,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njle short loc_1186\nadd edi, 1\nmov esi, 1\nmov ecx, 0\nloc_115E:\nmov edx, esi\ntest esi, esi\njz short loc_118D\nloc_1164:\nmov eax, edx\nand eax, 1\ncmp eax, 1\nadc ecx, 0\nmov eax, edx\nshr eax, 1Fh\nadd eax, edx\nsar eax, 1\nmov edx, eax\njnz short loc_1164\nadd esi, 1\ncmp edi, esi\njnz short loc_115E\nloc_1183:\nmov eax, ecx\nretn\nloc_1186:\nmov ecx, 0\njmp short loc_1183\nloc_118D:\nadd esi, 1\njmp short loc_115E", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // edi\n int v2; // esi\n unsigned int v3; // ecx\n int v4; // edx\n\n if ( a1 <= 0 )\n {\n return 0;\n }\n else\n {\n v1 = a1 + 1;\n v2 = 1;\n v3 = 0;\n do\n {\n while ( 1 )\n {\n v4 = v2;\n if ( v2 )\n break;\n v2 = 1;\n }\n do\n {\n v3 += (v4 & 1) == 0;\n v4 /= 2;\n }\n while ( v4 );\n ++v2;\n }\n while ( v1 != v2 );\n }\n return v3;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ntest edi, edi\njle short loc_1186\nadd edi, 1\nmov esi, 1\nmov ecx, 0\nloc_115E:\nmov edx, esi\ntest esi, esi\njz short loc_118D\nloc_1164:\nmov eax, edx\nand eax, 1\ncmp eax, 1\nadc ecx, 0\nmov eax, edx\nshr eax, 1Fh\nadd eax, edx\nsar eax, 1\nmov edx, eax\njnz short loc_1164\nadd esi, 1\ncmp edi, esi\njnz short loc_115E\nloc_1183:\nmov eax, ecx\nretn\nloc_1186:\nmov ecx, 0\njmp short loc_1183\nloc_118D:\nadd esi, 1\njmp short loc_115E", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v1; // edi\n int v2; // esi\n unsigned int v3; // ecx\n int v4; // edx\n\n if ( a1 <= 0 )\n {\n return 0;\n }\n else\n {\n v1 = a1 + 1;\n v2 = 1;\n v3 = 0;\n do\n {\n while ( 1 )\n {\n v4 = v2;\n if ( v2 )\n break;\n v2 = 1;\n }\n do\n {\n v3 += (v4 & 1) == 0;\n v4 /= 2;\n }\n while ( v4 );\n ++v2;\n }\n while ( v1 != v2 );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v1;\n int v2;\n unsigned int v3;\n int v4;\n if (a1 <= 0) {\n return 0;\n } else {\n v1 = a1 + 1;\n v2 = 1;\n v3 = 0;\n do {\n while (1) {\n v4 = v2;\n if (v2) break;\n v2 = 1;\n }\n do {\n v3 += (v4 & 1) == 0;\n v4 /= 2;\n } while (v4);\n ++v2;\n } while (v1 != v2);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v2;\n unsigned int v3;\n int v4;\n if (a1 <= 0) {\n return 0;\n } else {\n v1 = a1 + 1;\n v2 = 1;\n v3 = 0;\n do {\n while (1) {\n v4 = v2;\n if (v2) break;\n v2 = 1;\n }\n do {\n v3 += (v4 & 1) == 0;\n v4 /= 2;\n } while (v4);\n ++v2;\n } while (v1 != v2);\n }\n return v3;\n}" + }, + { + "index": 903, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int cnt = 0;\n for (int i = 1; i <= n; i++) {\n int temp = i;\n while (temp) {\n if (temp % 2 == 0) {\n cnt++;\n }\n temp = temp / 2;\n }\n }\n return cnt;\n}", + "test": "int main() {\n\n assert(func0(2) == 1);\n\n assert(func0(5) == 4);\n\n assert(func0(14) == 17);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %edi,%edi\njle 123b \nlea 0x1(%rdi),%esi\nmov $0x1,%ecx\nxor %r8d,%r8d\nnopl 0x0(%rax,%rax,1)\nmov %ecx,%eax\nnopw 0x0(%rax,%rax,1)\nmov %eax,%edx\nand $0x1,%edx\ncmp $0x1,%edx\nadc $0x0,%r8d\nsar %eax\njne 1220 \nadd $0x1,%ecx\ncmp %esi,%ecx\njne 1218 \nmov %r8d,%eax\nretq\nxor %r8d,%r8d\nmov %r8d,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\ntest edi, edi\njle short loc_1230\nadd edi, 1\nmov esi, 1\nxor edx, edx\nnop word ptr [rax+rax+00h]\nloc_1208:\nmov eax, esi\nnop word ptr [rax+rax+00h]\nloc_1210:\nmov ecx, eax\nand ecx, 1\ncmp ecx, 1\nmov ecx, eax\nadc edx, 0\nshr ecx, 1Fh\nadd eax, ecx\nsar eax, 1\njnz short loc_1210\nadd esi, 1\ncmp edi, esi\njnz short loc_1208\nmov eax, edx\nretn\nloc_1230:\nxor edx, edx\nmov eax, edx\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // edi\n int v2; // esi\n unsigned int v3; // edx\n int v4; // eax\n\n if ( a1 <= 0 )\n return 0LL;\n v1 = a1 + 1;\n v2 = 1;\n v3 = 0;\n do\n {\n v4 = v2;\n do\n {\n v3 += (v4 & 1) == 0;\n v4 /= 2;\n }\n while ( v4 );\n ++v2;\n }\n while ( v1 != v2 );\n return v3;\n}", + "ida_strip_asm": "sub_11F0:\nendbr64\ntest edi, edi\njle short loc_1230\nadd edi, 1\nmov esi, 1\nxor edx, edx\nnop word ptr [rax+rax+00h]\nloc_1208:\nmov eax, esi\nnop word ptr [rax+rax+00h]\nloc_1210:\nmov ecx, eax\nand ecx, 1\ncmp ecx, 1\nmov ecx, eax\nadc edx, 0\nshr ecx, 1Fh\nadd eax, ecx\nsar eax, 1\njnz short loc_1210\nadd esi, 1\ncmp edi, esi\njnz short loc_1208\nmov eax, edx\nretn\nloc_1230:\nxor edx, edx\nmov eax, edx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11F0(int a1)\n{\n int v1; // edi\n int v2; // esi\n unsigned int v3; // edx\n int v4; // eax\n\n if ( a1 <= 0 )\n return 0LL;\n v1 = a1 + 1;\n v2 = 1;\n v3 = 0;\n do\n {\n v4 = v2;\n do\n {\n v3 += (v4 & 1) == 0;\n v4 /= 2;\n }\n while ( v4 );\n ++v2;\n }\n while ( v1 != v2 );\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11F0(int a1) {\n int v1;\n int v2;\n unsigned int v3;\n int v4;\n if (a1 <= 0) return 0LL;\n v1 = a1 + 1;\n v2 = 1;\n v3 = 0;\n do {\n v4 = v2;\n do {\n v3 += (v4 & 1) == 0;\n v4 /= 2;\n } while (v4);\n ++v2;\n } while (v1 != v2);\n return v3;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v2;\n unsigned int v3;\n int v4;\n if (a1 <= 0) return 0LL;\n v1 = a1 + 1;\n v2 = 1;\n v3 = 0;\n do {\n v4 = v2;\n do {\n v3 += (v4 & 1) == 0;\n v4 /= 2;\n } while (v4);\n ++v2;\n } while (v1 != v2);\n return v3;\n}" + }, + { + "index": 904, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int x) {\n if (x % 2 == 0)\n return true;\n else\n return false;\n}", + "test": "int main() {\n\n assert(func0(13) == false);\n\n assert(func0(0) == true);\n\n assert(func0(-9) == false);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nand $0x1,%eax\ntest %eax,%eax\njne 1165 \nmov $0x1,%eax\njmp 116a \nmov $0x0,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov eax, [rbp+var_4]\nand eax, 1\ntest eax, eax\njnz short loc_1165\nmov eax, 1\njmp short loc_116A\nloc_1165:\nmov eax, 0\nloc_116A:\npop rbp\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(char a1)\n{\n return (a1 & 1) == 0;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov eax, [rbp+var_4]\nand eax, 1\ntest eax, eax\njnz short loc_1165\nmov eax, 1\njmp short loc_116A\nloc_1165:\nmov eax, 0\nloc_116A:\npop rbp\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1149(char a1)\n{\n return (a1 & 1) == 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1149(char a1) { return (a1 & 1) == 0; }", + "ida_pseudo_norm": "uint8_t func0(char a1) { return (a1 & 1) == 0; }" + }, + { + "index": 905, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\nint factorial(int start, int end) {\n\n int res = 1;\n\n for (int i = start; i <= end; i++) {\n\n res *= i;\n\n }\n\n return res;\n\n}\n\n\n\n", + "func": "int func0(int n) { return factorial(n + 1, 2 * n) / factorial(1, n); }", + "test": "int main() {\n\n assert(func0(4) == 70);\n\n assert(func0(5) == 252);\n\n assert(func0(2) == 6);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x8,%rsp\nmov %edi,-0xc(%rbp)\nmov -0xc(%rbp),%eax\nlea (%rax,%rax,1),%edx\nmov -0xc(%rbp),%eax\nadd $0x1,%eax\nmov %edx,%esi\nmov %eax,%edi\ncallq 1149 \nmov %eax,%ebx\nmov -0xc(%rbp),%eax\nmov %eax,%esi\nmov $0x1,%edi\ncallq 1149 \nmov %eax,%ecx\nmov %ebx,%eax\ncltd\nidiv %ecx\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 8\nmov [rbp+var_C], edi\nmov eax, [rbp+var_C]\nlea edx, [rax+rax]\nmov eax, [rbp+var_C]\nadd eax, 1\nmov esi, edx\nmov edi, eax\ncall factorial\nmov ebx, eax\nmov eax, [rbp+var_C]\nmov esi, eax\nmov edi, 1\ncall factorial\nmov ecx, eax\nmov eax, ebx\ncdq\nidiv ecx\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1)\n{\n int v1; // ebx\n\n v1 = factorial(a1 + 1, 2 * a1);\n return (unsigned int)(v1 / (int)factorial(1LL, a1));\n}", + "ida_strip_asm": "sub_1181:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 8\nmov [rbp+var_C], edi\nmov eax, [rbp+var_C]\nlea edx, [rax+rax]\nmov eax, [rbp+var_C]\nadd eax, 1\nmov esi, edx\nmov edi, eax\ncall sub_1149\nmov ebx, eax\nmov eax, [rbp+var_C]\nmov esi, eax\nmov edi, 1\ncall sub_1149\nmov ecx, eax\nmov eax, ebx\ncdq\nidiv ecx\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1181(unsigned int a1)\n{\n int v1; // ebx\n\n v1 = sub_1149(a1 + 1, 2 * a1);\n return (unsigned int)(v1 / (int)sub_1149(1LL, a1));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1181(unsigned int a1) {\n int v1;\n v1 = sub_1149(a1 + 1, 2 * a1);\n return (unsigned int)(v1 / (int)sub_1149(1LL, a1));\n}", + "ida_pseudo_norm": "long long func0(unsigned int a1) {\n int v1;\n v1 = factorial(a1 + 1, 2 * a1);\n return (unsigned int)(v1 / (int)factorial(1LL, a1));\n}" + }, + { + "index": 905, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\nint factorial(int start, int end) {\n\n int res = 1;\n\n for (int i = start; i <= end; i++) {\n\n res *= i;\n\n }\n\n return res;\n\n}\n\n\n\n", + "func": "int func0(int n) { return factorial(n + 1, 2 * n) / factorial(1, n); }", + "test": "int main() {\n\n assert(func0(4) == 70);\n\n assert(func0(5) == 252);\n\n assert(func0(2) == 6);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nlea (%rdi,%rdi,1),%eax\nlea 0x1(%rdi),%edx\ncmp %edx,%eax\njl 11a9 \nlea 0x1(%rax),%ecx\nmov $0x1,%eax\nimul %edx,%eax\nadd $0x1,%edx\ncmp %edx,%ecx\njne 1180 \ntest %edi,%edi\njle 11b0 \nadd $0x1,%edi\nmov $0x1,%edx\nmov $0x1,%ecx\nimul %edx,%ecx\nadd $0x1,%edx\ncmp %edx,%edi\njne 119b \ncltd\nidiv %ecx\nretq\nmov $0x1,%eax\njmp 118a \nmov $0x1,%ecx\njmp 11a5 \n", + "ida_asm": "func0:\nendbr64\nlea edx, [rdi+1]\nlea eax, [rdi+rdi]\ncmp eax, edx\njl short loc_11AA\nlea ecx, [rdi+rdi+1]\nmov eax, 1\nloc_1181:\nimul eax, edx\nadd edx, 1\ncmp edx, ecx\njnz short loc_1181\nloc_118B:\ntest edi, edi\njle short loc_11B1\nadd edi, 1\nmov edx, 1\nmov ecx, 1\nloc_119C:\nimul ecx, edx\nadd edx, 1\ncmp edi, edx\njnz short loc_119C\nloc_11A6:\ncdq\nidiv ecx\nretn\nloc_11AA:\nmov eax, 1\njmp short loc_118B\nloc_11B1:\nmov ecx, 1\njmp short loc_11A6", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v1; // edx\n int v2; // eax\n int v3; // edi\n int v4; // edx\n int v5; // ecx\n\n v1 = a1 + 1;\n if ( 2 * a1 < a1 + 1 )\n {\n v2 = 1;\n }\n else\n {\n v2 = 1;\n do\n v2 *= v1++;\n while ( v1 != 2 * a1 + 1 );\n }\n if ( a1 <= 0 )\n {\n v5 = 1;\n }\n else\n {\n v3 = a1 + 1;\n v4 = 1;\n v5 = 1;\n do\n v5 *= v4++;\n while ( v3 != v4 );\n }\n return (unsigned int)(v2 / v5);\n}", + "ida_strip_asm": "sub_116A:\nendbr64\nlea edx, [rdi+1]\nlea eax, [rdi+rdi]\ncmp eax, edx\njl short loc_11AA\nlea ecx, [rdi+rdi+1]\nmov eax, 1\nloc_1181:\nimul eax, edx\nadd edx, 1\ncmp edx, ecx\njnz short loc_1181\nloc_118B:\ntest edi, edi\njle short loc_11B1\nadd edi, 1\nmov edx, 1\nmov ecx, 1\nloc_119C:\nimul ecx, edx\nadd edx, 1\ncmp edi, edx\njnz short loc_119C\nloc_11A6:\ncdq\nidiv ecx\nretn\nloc_11AA:\nmov eax, 1\njmp short loc_118B\nloc_11B1:\nmov ecx, 1\njmp short loc_11A6", + "ida_strip_pseudo": "__int64 __fastcall sub_116A(int a1)\n{\n int v1; // edx\n int v2; // eax\n int v3; // edi\n int v4; // edx\n int v5; // ecx\n\n v1 = a1 + 1;\n if ( 2 * a1 < a1 + 1 )\n {\n v2 = 1;\n }\n else\n {\n v2 = 1;\n do\n v2 *= v1++;\n while ( v1 != 2 * a1 + 1 );\n }\n if ( a1 <= 0 )\n {\n v5 = 1;\n }\n else\n {\n v3 = a1 + 1;\n v4 = 1;\n v5 = 1;\n do\n v5 *= v4++;\n while ( v3 != v4 );\n }\n return (unsigned int)(v2 / v5);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_116A(int a1) {\n int v1;\n int v2;\n int v3;\n int v4;\n int v5;\n v1 = a1 + 1;\n if (2 * a1 < a1 + 1) {\n v2 = 1;\n } else {\n v2 = 1;\n do\n v2 *= v1++;\n while (v1 != 2 * a1 + 1);\n }\n if (a1 <= 0) {\n v5 = 1;\n } else {\n v3 = a1 + 1;\n v4 = 1;\n v5 = 1;\n do\n v5 *= v4++;\n while (v3 != v4);\n }\n return (unsigned int)(v2 / v5);\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v1;\n int v2;\n int v3;\n int v4;\n int v5;\n v1 = a1 + 1;\n if (2 * a1 < a1 + 1) {\n v2 = 1;\n } else {\n v2 = 1;\n do\n v2 *= v1++;\n while (v1 != 2 * a1 + 1);\n }\n if (a1 <= 0) {\n v5 = 1;\n } else {\n v3 = a1 + 1;\n v4 = 1;\n v5 = 1;\n do\n v5 *= v4++;\n while (v3 != v4);\n }\n return (unsigned int)(v2 / v5);\n}" + }, + { + "index": 906, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char year[5];\n\n char month[3];\n\n char day[3];\n\n} Date;\n\n\n\n", + "func": "Date func0(const char* url) {\n regex_t regex;\n regmatch_t matches[4];\n Date date = {\"\", \"\", \"\"};\n const char* pattern = \"/([0-9]{4})/([0-9]{1,2})/([0-9]{1,2})/\";\n if (regcomp(®ex, pattern, REG_EXTENDED)) {\n return date;\n }\n if (!regexec(®ex, url, 4, matches, 0)) {\n int start, end;\n start = matches[1].rm_so;\n end = matches[1].rm_eo;\n snprintf(date.year, sizeof(date.year), \"%.*s\", end - start, url + start);\n start = matches[2].rm_so;\n end = matches[2].rm_eo;\n snprintf(date.month, sizeof(date.month), \"%.*s\", end - start, url + start);\n start = matches[3].rm_so;\n end = matches[3].rm_eo;\n snprintf(date.day, sizeof(date.day), \"%.*s\", end - start, url + start);\n }\n regfree(®ex);\n return date;\n}", + "test": "int main() {\n\n Date d1 = func0(\"https://www.washingtonpost.com/news/football-insider/wp/2016/09/02/odell-beckhams-fame-rests-on-one-stupid-little-ball-josh-norman-tells-author/\");\n\n assert(strcmp(d1.year, \"2016\") == 0 && strcmp(d1.month, \"09\") == 0 && strcmp(d1.day, \"02\") == 0);\n\n\n\n Date d2 = func0(\"https://www.indiatoday.in/movies/celebrities/story/wp/2020/11/03/odeof-sushant-singh-rajput-s-death-his-brother-in-law-shares-advice-for-fans-1749646/\");\n\n assert(strcmp(d2.year, \"2020\") == 0 && strcmp(d2.month, \"11\") == 0 && strcmp(d2.day, \"03\") == 0);\n\n\n\n Date d3 = func0(\"https://economictimes.indiatimes.com/news/economy/2020/12/29/finance/pension-assets-under-pfrda-touch-rs-5-32-lakh-crore/articleshow/79736619.cms\");\n\n assert(strcmp(d3.year, \"2020\") == 0 && strcmp(d3.month, \"12\") == 0 && strcmp(d3.day, \"29\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0xc0,%rsp\nmov %rdi,-0xa8(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovl $0x0,-0x46(%rbp)\nmovb $0x0,-0x42(%rbp)\nmovw $0x0,-0x41(%rbp)\nmovb $0x0,-0x3f(%rbp)\nmovw $0x0,-0x3e(%rbp)\nmovb $0x0,-0x3c(%rbp)\nlea 0xdb4(%rip),%rax\nmov %rax,-0x98(%rbp)\nmov -0x98(%rbp),%rcx\nlea -0x90(%rbp),%rax\nmov $0x1,%edx\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 10f0 \ntest %eax,%eax\nje 1299 \nmov -0x46(%rbp),%rax\nmov %rax,-0x3b(%rbp)\nmovzwl -0x3e(%rbp),%eax\nmov %ax,-0x33(%rbp)\nmovzbl -0x3c(%rbp),%eax\nmov %al,-0x31(%rbp)\njmpq 13ef \nlea -0x30(%rbp),%rdx\nmov -0xa8(%rbp),%rsi\nlea -0x90(%rbp),%rax\nmov $0x0,%r8d\nmov %rdx,%rcx\nmov $0x4,%edx\nmov %rax,%rdi\ncallq 1110 \ntest %eax,%eax\njne 13c9 \nmov -0x28(%rbp),%eax\nmov %eax,-0xa0(%rbp)\nmov -0x24(%rbp),%eax\nmov %eax,-0x9c(%rbp)\nmov -0xa0(%rbp),%eax\nmovslq %eax,%rdx\nmov -0xa8(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x9c(%rbp),%eax\nsub -0xa0(%rbp),%eax\nmov %eax,%edx\nlea -0x46(%rbp),%rax\nmov %rcx,%r8\nmov %edx,%ecx\nlea 0xd22(%rip),%rdx\nmov $0x5,%esi\nmov %rax,%rdi\nmov $0x0,%eax\ncallq 10d0 \nmov -0x20(%rbp),%eax\nmov %eax,-0xa0(%rbp)\nmov -0x1c(%rbp),%eax\nmov %eax,-0x9c(%rbp)\nmov -0xa0(%rbp),%eax\nmovslq %eax,%rdx\nmov -0xa8(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x9c(%rbp),%eax\nsub -0xa0(%rbp),%eax\nlea -0x46(%rbp),%rdx\nlea 0x5(%rdx),%rdi\nmov %rcx,%r8\nmov %eax,%ecx\nlea 0xcca(%rip),%rdx\nmov $0x3,%esi\nmov $0x0,%eax\ncallq 10d0 \nmov -0x18(%rbp),%eax\nmov %eax,-0xa0(%rbp)\nmov -0x14(%rbp),%eax\nmov %eax,-0x9c(%rbp)\nmov -0xa0(%rbp),%eax\nmovslq %eax,%rdx\nmov -0xa8(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x9c(%rbp),%eax\nsub -0xa0(%rbp),%eax\nlea -0x46(%rbp),%rdx\nlea 0x8(%rdx),%rdi\nmov %rcx,%r8\nmov %eax,%ecx\nlea 0xc75(%rip),%rdx\nmov $0x3,%esi\nmov $0x0,%eax\ncallq 10d0 \nlea -0x90(%rbp),%rax\nmov %rax,%rdi\ncallq 10b0 \nmov -0x46(%rbp),%rax\nmov %rax,-0x3b(%rbp)\nmovzwl -0x3e(%rbp),%eax\nmov %ax,-0x33(%rbp)\nmovzbl -0x3c(%rbp),%eax\nmov %al,-0x31(%rbp)\nmov -0x3b(%rbp),%rax\nmovzbl -0x33(%rbp),%ecx\nmovzbl -0x32(%rbp),%esi\nshl $0x8,%rsi\nor %rcx,%rsi\nmovzbl -0x31(%rbp),%ecx\nshl $0x10,%rcx\nor %rsi,%rcx\nmov %rcx,%rdx\nmov -0x8(%rbp),%rdi\nxor %fs:0x28,%rdi\nje 1424 \ncallq 10c0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0C0h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov dword ptr [rbp+s], 0\nmov [rbp+s+4], 0\nmov word ptr [rbp+s+5], 0\nmov [rbp+s+7], 0\nmov [rbp+var_3E], 0\nmov [rbp+var_3C], 0\nlea rax, a09409120912; \"/([0-9]{4})/([0-9]{1,2})/([0-9]{1,2})/\"\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\ntest eax, eax\njz short loc_1290\nmov rax, qword ptr [rbp+s]\nmov [rbp+var_3B], rax\nmov eax, dword ptr [rbp+s+7]\nmov dword ptr [rbp+var_3B+7], eax\njmp loc_13E3\nloc_1290:\nlea rdx, [rbp+pmatch]\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov rcx, rdx; pmatch\nmov edx, 4; nmatch\nmov rdi, rax; preg\ncall _regexec\ntest eax, eax\njnz loc_13C6\nmov eax, [rbp+var_28]\nmov [rbp+var_A0], eax\nmov eax, [rbp+var_24]\nmov [rbp+var_9C], eax\nmov eax, [rbp+var_A0]\nmovsxd rdx, eax\nmov rax, [rbp+string]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_9C]\nsub eax, [rbp+var_A0]\nmov edx, eax\nlea rax, [rbp+s]\nmov r8, rcx\nmov ecx, edx\nlea rdx, format; \"%.*s\"\nmov esi, 5; maxlen\nmov rdi, rax; s\nmov eax, 0\ncall _snprintf\nmov eax, [rbp+var_20]\nmov [rbp+var_A0], eax\nmov eax, [rbp+var_1C]\nmov [rbp+var_9C], eax\nmov eax, [rbp+var_A0]\nmovsxd rdx, eax\nmov rax, [rbp+string]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_9C]\nsub eax, [rbp+var_A0]\nlea rdx, [rbp+s]\nlea rdi, [rdx+5]; s\nmov r8, rcx\nmov ecx, eax\nlea rax, format; \"%.*s\"\nmov rdx, rax; format\nmov esi, 3; maxlen\nmov eax, 0\ncall _snprintf\nmov eax, [rbp+var_18]\nmov [rbp+var_A0], eax\nmov eax, [rbp+var_14]\nmov [rbp+var_9C], eax\nmov eax, [rbp+var_A0]\nmovsxd rdx, eax\nmov rax, [rbp+string]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_9C]\nsub eax, [rbp+var_A0]\nlea rdx, [rbp+s]\nlea rdi, [rdx+8]; s\nmov r8, rcx\nmov ecx, eax\nlea rax, format; \"%.*s\"\nmov rdx, rax; format\nmov esi, 3; maxlen\nmov eax, 0\ncall _snprintf\nloc_13C6:\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nmov rax, qword ptr [rbp+s]\nmov [rbp+var_3B], rax\nmov eax, dword ptr [rbp+s+7]\nmov dword ptr [rbp+var_3B+7], eax\nloc_13E3:\nmov rax, [rbp+var_3B]\nmovzx ecx, [rbp+var_33]\nmovzx esi, [rbp+var_32]\nshl rsi, 8\nor rsi, rcx\nmovzx ecx, [rbp+var_31]\nshl rcx, 10h\nor rcx, rsi\nmov rdx, rcx\nmov rcx, [rbp+var_8]\nsub rcx, fs:28h\njz short locret_1418\ncall ___stack_chk_fail\nlocret_1418:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n regex_t preg; // [rsp+30h] [rbp-90h] BYREF\n char s[11]; // [rsp+7Ah] [rbp-46h] BYREF\n _BYTE v4[11]; // [rsp+85h] [rbp-3Bh]\n regmatch_t pmatch; // [rsp+90h] [rbp-30h] BYREF\n int v6; // [rsp+98h] [rbp-28h]\n int v7; // [rsp+9Ch] [rbp-24h]\n int v8; // [rsp+A0h] [rbp-20h]\n int v9; // [rsp+A4h] [rbp-1Ch]\n int v10; // [rsp+A8h] [rbp-18h]\n int v11; // [rsp+ACh] [rbp-14h]\n unsigned __int64 v12; // [rsp+B8h] [rbp-8h]\n\n v12 = __readfsqword(0x28u);\n memset(s, 0, sizeof(s));\n if ( regcomp(&preg, \"/([0-9]{4})/([0-9]{1,2})/([0-9]{1,2})/\", 1) )\n {\n *(_QWORD *)v4 = *(_QWORD *)s;\n *(_DWORD *)&v4[7] = *(_DWORD *)&s[7];\n }\n else\n {\n if ( !regexec(&preg, a1, 4uLL, &pmatch, 0) )\n {\n snprintf(s, 5uLL, \"%.*s\", v7 - v6, &a1[v6]);\n snprintf(&s[5], 3uLL, \"%.*s\", v9 - v8, &a1[v8]);\n snprintf(&s[8], 3uLL, \"%.*s\", v11 - v10, &a1[v10]);\n }\n regfree(&preg);\n *(_QWORD *)v4 = *(_QWORD *)s;\n *(_DWORD *)&v4[7] = *(_DWORD *)&s[7];\n }\n return *(_QWORD *)v4;\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0C0h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov dword ptr [rbp+s], 0\nmov [rbp+s+4], 0\nmov word ptr [rbp+s+5], 0\nmov [rbp+s+7], 0\nmov [rbp+var_3E], 0\nmov [rbp+var_3C], 0\nlea rax, a09409120912; \"/([0-9]{4})/([0-9]{1,2})/([0-9]{1,2})/\"\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\ntest eax, eax\njz short loc_1290\nmov rax, qword ptr [rbp+s]\nmov [rbp+var_3B], rax\nmov eax, dword ptr [rbp+s+7]\nmov dword ptr [rbp+var_3B+7], eax\njmp loc_13E3\nloc_1290:\nlea rdx, [rbp+pmatch]\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov rcx, rdx; pmatch\nmov edx, 4; nmatch\nmov rdi, rax; preg\ncall _regexec\ntest eax, eax\njnz loc_13C6\nmov eax, [rbp+var_28]\nmov [rbp+var_A0], eax\nmov eax, [rbp+var_24]\nmov [rbp+var_9C], eax\nmov eax, [rbp+var_A0]\nmovsxd rdx, eax\nmov rax, [rbp+string]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_9C]\nsub eax, [rbp+var_A0]\nmov edx, eax\nlea rax, [rbp+s]\nmov r8, rcx\nmov ecx, edx\nlea rdx, format; \"%.*s\"\nmov esi, 5; maxlen\nmov rdi, rax; s\nmov eax, 0\ncall _snprintf\nmov eax, [rbp+var_20]\nmov [rbp+var_A0], eax\nmov eax, [rbp+var_1C]\nmov [rbp+var_9C], eax\nmov eax, [rbp+var_A0]\nmovsxd rdx, eax\nmov rax, [rbp+string]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_9C]\nsub eax, [rbp+var_A0]\nlea rdx, [rbp+s]\nlea rdi, [rdx+5]; s\nmov r8, rcx\nmov ecx, eax\nlea rax, format; \"%.*s\"\nmov rdx, rax; format\nmov esi, 3; maxlen\nmov eax, 0\ncall _snprintf\nmov eax, [rbp+var_18]\nmov [rbp+var_A0], eax\nmov eax, [rbp+var_14]\nmov [rbp+var_9C], eax\nmov eax, [rbp+var_A0]\nmovsxd rdx, eax\nmov rax, [rbp+string]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_9C]\nsub eax, [rbp+var_A0]\nlea rdx, [rbp+s]\nlea rdi, [rdx+8]; s\nmov r8, rcx\nmov ecx, eax\nlea rax, format; \"%.*s\"\nmov rdx, rax; format\nmov esi, 3; maxlen\nmov eax, 0\ncall _snprintf\nloc_13C6:\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nmov rax, qword ptr [rbp+s]\nmov [rbp+var_3B], rax\nmov eax, dword ptr [rbp+s+7]\nmov dword ptr [rbp+var_3B+7], eax\nloc_13E3:\nmov rax, [rbp+var_3B]\nmovzx ecx, [rbp+var_33]\nmovzx esi, [rbp+var_32]\nshl rsi, 8\nor rsi, rcx\nmovzx ecx, [rbp+var_31]\nshl rcx, 10h\nor rcx, rsi\nmov rdx, rcx\nmov rcx, [rbp+var_8]\nsub rcx, fs:28h\njz short locret_1418\ncall ___stack_chk_fail\nlocret_1418:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1209(const char *a1)\n{\n regex_t preg; // [rsp+30h] [rbp-90h] BYREF\n char s[11]; // [rsp+7Ah] [rbp-46h] BYREF\n _BYTE v4[11]; // [rsp+85h] [rbp-3Bh]\n regmatch_t pmatch; // [rsp+90h] [rbp-30h] BYREF\n int v6; // [rsp+98h] [rbp-28h]\n int v7; // [rsp+9Ch] [rbp-24h]\n int v8; // [rsp+A0h] [rbp-20h]\n int v9; // [rsp+A4h] [rbp-1Ch]\n int v10; // [rsp+A8h] [rbp-18h]\n int v11; // [rsp+ACh] [rbp-14h]\n unsigned __int64 v12; // [rsp+B8h] [rbp-8h]\n\n v12 = __readfsqword(0x28u);\n memset(s, 0, sizeof(s));\n if ( regcomp(&preg, \"/([0-9]{4})/([0-9]{1,2})/([0-9]{1,2})/\", 1) )\n {\n *(_QWORD *)v4 = *(_QWORD *)s;\n *(_DWORD *)&v4[7] = *(_DWORD *)&s[7];\n }\n else\n {\n if ( !regexec(&preg, a1, 4uLL, &pmatch, 0) )\n {\n snprintf(s, 5uLL, \"%.*s\", v7 - v6, &a1[v6]);\n snprintf(&s[5], 3uLL, \"%.*s\", v9 - v8, &a1[v8]);\n snprintf(&s[8], 3uLL, \"%.*s\", v11 - v10, &a1[v10]);\n }\n regfree(&preg);\n *(_QWORD *)v4 = *(_QWORD *)s;\n *(_DWORD *)&v4[7] = *(_DWORD *)&s[7];\n }\n return *(_QWORD *)v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1209(const char *a1) {\n regex_t preg;\n char s[11];\n uint8_t v4[11];\n regmatch_t pmatch;\n int v6;\n int v7;\n int v8;\n int v9;\n int v10;\n int v11;\n unsigned long long v12;\n v12 = __readfsqword(40u);\n memset(s, 0, sizeof(s));\n if (regcomp(&preg, \"/([0-9]{4})/([0-9]{1,2})/([0-9]{1,2})/\", 1)) {\n *(uint64_t *)v4 = *(uint64_t *)s;\n *(uint32_t *)&v4[7] = *(uint32_t *)&s[7];\n } else {\n if (!regexec(&preg, a1, 4uLL, &pmatch, 0)) {\n snprintf(s, 5uLL, \"%.*s\", v7 - v6, &a1[v6]);\n snprintf(&s[5], 3uLL, \"%.*s\", v9 - v8, &a1[v8]);\n snprintf(&s[8], 3uLL, \"%.*s\", v11 - v10, &a1[v10]);\n }\n regfree(&preg);\n *(uint64_t *)v4 = *(uint64_t *)s;\n *(uint32_t *)&v4[7] = *(uint32_t *)&s[7];\n }\n return *(uint64_t *)v4;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n regex_t preg;\n char s[11];\n uint8_t v4[11];\n regmatch_t pmatch;\n int v6;\n int v7;\n int v8;\n int v9;\n int v10;\n int v11;\n unsigned long long v12;\n v12 = __readfsqword(40u);\n memset(s, 0, sizeof(s));\n if (regcomp(&preg, \"/([0-9]{4})/([0-9]{1,2})/([0-9]{1,2})/\", 1)) {\n *(uint64_t *)v4 = *(uint64_t *)s;\n *(uint32_t *)&v4[7] = *(uint32_t *)&s[7];\n } else {\n if (!regexec(&preg, a1, 4uLL, &pmatch, 0)) {\n snprintf(s, 5uLL, \"%.*s\", v7 - v6, &a1[v6]);\n snprintf(&s[5], 3uLL, \"%.*s\", v9 - v8, &a1[v8]);\n snprintf(&s[8], 3uLL, \"%.*s\", v11 - v10, &a1[v10]);\n }\n regfree(&preg);\n *(uint64_t *)v4 = *(uint64_t *)s;\n *(uint32_t *)&v4[7] = *(uint32_t *)&s[7];\n }\n return *(uint64_t *)v4;\n}" + }, + { + "index": 906, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char year[5];\n\n char month[3];\n\n char day[3];\n\n} Date;\n\n\n\n", + "func": "Date func0(const char* url) {\n regex_t regex;\n regmatch_t matches[4];\n Date date = {\"\", \"\", \"\"};\n const char* pattern = \"/([0-9]{4})/([0-9]{1,2})/([0-9]{1,2})/\";\n if (regcomp(®ex, pattern, REG_EXTENDED)) {\n return date;\n }\n if (!regexec(®ex, url, 4, matches, 0)) {\n int start, end;\n start = matches[1].rm_so;\n end = matches[1].rm_eo;\n snprintf(date.year, sizeof(date.year), \"%.*s\", end - start, url + start);\n start = matches[2].rm_so;\n end = matches[2].rm_eo;\n snprintf(date.month, sizeof(date.month), \"%.*s\", end - start, url + start);\n start = matches[3].rm_so;\n end = matches[3].rm_eo;\n snprintf(date.day, sizeof(date.day), \"%.*s\", end - start, url + start);\n }\n regfree(®ex);\n return date;\n}", + "test": "int main() {\n\n Date d1 = func0(\"https://www.washingtonpost.com/news/football-insider/wp/2016/09/02/odell-beckhams-fame-rests-on-one-stupid-little-ball-josh-norman-tells-author/\");\n\n assert(strcmp(d1.year, \"2016\") == 0 && strcmp(d1.month, \"09\") == 0 && strcmp(d1.day, \"02\") == 0);\n\n\n\n Date d2 = func0(\"https://www.indiatoday.in/movies/celebrities/story/wp/2020/11/03/odeof-sushant-singh-rajput-s-death-his-brother-in-law-shares-advice-for-fans-1749646/\");\n\n assert(strcmp(d2.year, \"2020\") == 0 && strcmp(d2.month, \"11\") == 0 && strcmp(d2.day, \"03\") == 0);\n\n\n\n Date d3 = func0(\"https://economictimes.indiatimes.com/news/economy/2020/12/29/finance/pension-assets-under-pfrda-touch-rs-5-32-lakh-crore/articleshow/79736619.cms\");\n\n assert(strcmp(d3.year, \"2020\") == 0 && strcmp(d3.month, \"12\") == 0 && strcmp(d3.day, \"29\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nsub $0xa0,%rsp\nmov %rdi,%rbx\nmov %fs:0x28,%rax\nmov %rax,0x98(%rsp)\nxor %eax,%eax\nmovl $0x0,0x5a(%rsp)\nmovb $0x0,0x5e(%rsp)\nmovw $0x0,0x5f(%rsp)\nmovb $0x0,0x61(%rsp)\nmovw $0x0,0x62(%rsp)\nmovb $0x0,0x64(%rsp)\nlea 0x10(%rsp),%rdi\nmov $0x1,%edx\nlea 0xdc7(%rip),%rsi\ncallq 10e0 \ntest %eax,%eax\nje 12ac \nmov 0x5a(%rsp),%rax\nmov %rax,0x65(%rsp)\nmovzwl 0x62(%rsp),%eax\nmov %ax,0x6d(%rsp)\nmovzbl 0x64(%rsp),%eax\nmov %al,0x6f(%rsp)\nmov 0x65(%rsp),%rcx\nmovzbl 0x6d(%rsp),%eax\nmovzbl 0x6e(%rsp),%edx\nshl $0x8,%rdx\nor %rax,%rdx\nmovzbl 0x6f(%rsp),%eax\nshl $0x10,%rax\nor %rax,%rdx\nmov 0x98(%rsp),%rax\nxor %fs:0x28,%rax\njne 13c6 \nmov %rcx,%rax\nadd $0xa0,%rsp\npop %rbx\nretq\nlea 0x70(%rsp),%rcx\nlea 0x10(%rsp),%rdi\nmov $0x0,%r8d\nmov $0x4,%edx\nmov %rbx,%rsi\ncallq 10f0 \ntest %eax,%eax\nje 12f9 \nlea 0x10(%rsp),%rdi\ncallq 10b0 \nmov 0x5a(%rsp),%rax\nmov %rax,0x65(%rsp)\nmovzwl 0x62(%rsp),%eax\nmov %ax,0x6d(%rsp)\nmovzbl 0x64(%rsp),%eax\nmov %al,0x6f(%rsp)\njmpq 1267 \nmov 0x78(%rsp),%edx\nlea 0x5a(%rsp),%rdi\nsub $0x8,%rsp\nmovslq %edx,%rax\nadd %rbx,%rax\npush %rax\nmov 0x8c(%rsp),%r9d\nsub %edx,%r9d\nlea 0x1032(%rip),%r8\nmov $0x5,%ecx\nmov $0x1,%edx\nmov $0x5,%esi\nmov $0x0,%eax\ncallq 10a0 <__snprintf_chk@plt>\nmov 0x90(%rsp),%edx\nlea 0x6f(%rsp),%rdi\nmovslq %edx,%rax\nadd %rbx,%rax\nmov %rax,(%rsp)\nmov 0x94(%rsp),%r9d\nsub %edx,%r9d\nlea 0xff1(%rip),%r8\nmov $0x3,%ecx\nmov $0x1,%edx\nmov $0x3,%esi\nmov $0x0,%eax\ncallq 10a0 <__snprintf_chk@plt>\nmov 0x98(%rsp),%eax\nlea 0x72(%rsp),%r10\nmovslq %eax,%rdi\nadd %rbx,%rdi\nmov %rdi,(%rsp)\nmov 0x9c(%rsp),%r9d\nsub %eax,%r9d\nlea 0xfb0(%rip),%r8\nmov $0x3,%ecx\nmov $0x1,%edx\nmov $0x3,%esi\nmov %r10,%rdi\nmov $0x0,%eax\ncallq 10a0 <__snprintf_chk@plt>\nadd $0x10,%rsp\njmpq 12cd \ncallq 10c0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbx\nsub rsp, 0A0h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+0A8h+var_10], rax\nxor eax, eax\nmov dword ptr [rsp+0A8h+var_4E], 0\nmov byte ptr [rsp+0A8h+var_4E+4], 0\nmov word ptr [rsp+0A8h+var_4E+5], 0\nmov byte ptr [rsp+0A8h+var_4E+7], 0\nmov [rsp+0A8h+var_46], 0\nmov [rsp+0A8h+var_44], 0\nlea rdi, [rsp+0A8h+preg]; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"/([0-9]{4})/([0-9]{1,2})/([0-9]{1,2})/\"\ncall _regcomp\ntest eax, eax\njz short loc_12C1\nloc_126A:\nmov rax, [rsp+0A8h+var_4E]\nmov [rsp+0A8h+var_43], rax\nmov eax, dword ptr [rsp+0A8h+var_4E+7]\nmov dword ptr [rsp+0A8h+var_43+7], eax\nmov rcx, [rsp+0A8h+var_43]\nmovzx edx, [rsp+0A8h+var_3B]\nmovzx eax, [rsp+0A8h+var_3A]\nshl rax, 8\nor rax, rdx\nmovzx edx, [rsp+0A8h+var_39]\nshl rdx, 10h\nor rdx, rax\nmov rax, [rsp+0A8h+var_10]\nsub rax, fs:28h\njnz loc_13BB\nmov rax, rcx\nadd rsp, 0A0h\npop rbx\nretn\nloc_12C1:\nlea rcx, [rsp+0A8h+pmatch]; pmatch\nlea rdi, [rsp+0A8h+preg]; preg\nmov r8d, 0; eflags\nmov edx, 4; nmatch\nmov rsi, rbx; string\ncall _regexec\ntest eax, eax\njz short loc_12F1\nloc_12E2:\nlea rdi, [rsp+0A8h+preg]; preg\ncall _regfree\njmp loc_126A\nloc_12F1:\nmov edx, [rsp+0A8h+var_30]\nlea rdi, [rsp+0A8h+var_4E]\nsub rsp, 8\nmovsxd rax, edx\nadd rax, rbx\npush rax\nmov r9d, [rsp+0B8h+var_2C]\nsub r9d, edx\nlea r8, aS; \"%.*s\"\nmov ecx, 5\nmov edx, 2\nmov esi, 5\nmov eax, 0\ncall ___snprintf_chk\nmov edx, [rsp+0B8h+var_28]\nlea rdi, [rsp+0B8h+var_4E+5]\nmovsxd rax, edx\nadd rax, rbx\nmov [rsp+0B8h+var_B8], rax\nmov r9d, [rsp+0B8h+var_24]\nsub r9d, edx\nlea r8, aS; \"%.*s\"\nmov ecx, 3\nmov edx, 2\nmov esi, 3\nmov eax, 0\ncall ___snprintf_chk\nmov edx, [rsp+0B8h+var_20]\nlea rdi, [rsp+0B8h+var_46]\nmovsxd rax, edx\nadd rax, rbx\nmov [rsp+0B8h+var_B8], rax\nmov r9d, [rsp+0B8h+var_1C]\nsub r9d, edx\nlea r8, aS; \"%.*s\"\nmov ecx, 3\nmov edx, 2\nmov esi, 3\nmov eax, 0\ncall ___snprintf_chk\nadd rsp, 10h\njmp loc_12E2\nloc_13BB:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(char *string)\n{\n regex_t preg; // [rsp+20h] [rbp-98h] BYREF\n _BYTE v3[11]; // [rsp+6Ah] [rbp-4Eh] BYREF\n _BYTE v4[11]; // [rsp+75h] [rbp-43h]\n regmatch_t pmatch; // [rsp+80h] [rbp-38h] BYREF\n int v6; // [rsp+88h] [rbp-30h]\n int v7; // [rsp+8Ch] [rbp-2Ch]\n int v8; // [rsp+90h] [rbp-28h]\n int v9; // [rsp+94h] [rbp-24h]\n int v10; // [rsp+98h] [rbp-20h]\n int v11; // [rsp+9Ch] [rbp-1Ch]\n unsigned __int64 v12; // [rsp+A8h] [rbp-10h]\n\n v12 = __readfsqword(0x28u);\n memset(v3, 0, sizeof(v3));\n if ( !regcomp(&preg, \"/([0-9]{4})/([0-9]{1,2})/([0-9]{1,2})/\", 1) )\n {\n if ( !regexec(&preg, string, 4uLL, &pmatch, 0) )\n {\n __snprintf_chk(v3, 5LL, 2LL, 5LL, \"%.*s\", v7 - v6, &string[v6]);\n __snprintf_chk(&v3[5], 3LL, 2LL, 3LL, \"%.*s\", v9 - v8, &string[v8]);\n __snprintf_chk(&v3[8], 3LL, 2LL, 3LL, \"%.*s\", v11 - v10, &string[v10]);\n }\n regfree(&preg);\n }\n *(_QWORD *)v4 = *(_QWORD *)v3;\n *(_DWORD *)&v4[7] = *(_DWORD *)&v3[7];\n return *(_QWORD *)v4;\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush rbx\nsub rsp, 0A0h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+0A8h+var_10], rax\nxor eax, eax\nmov dword ptr [rsp+0A8h+var_4E], 0\nmov byte ptr [rsp+0A8h+var_4E+4], 0\nmov word ptr [rsp+0A8h+var_4E+5], 0\nmov byte ptr [rsp+0A8h+var_4E+7], 0\nmov [rsp+0A8h+var_46], 0\nmov [rsp+0A8h+var_44], 0\nlea rdi, [rsp+0A8h+preg]; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"/([0-9]{4})/([0-9]{1,2})/([0-9]{1,2})/\"\ncall _regcomp\ntest eax, eax\njz short loc_12C1\nloc_126A:\nmov rax, [rsp+0A8h+var_4E]\nmov [rsp+0A8h+var_43], rax\nmov eax, dword ptr [rsp+0A8h+var_4E+7]\nmov dword ptr [rsp+0A8h+var_43+7], eax\nmov rcx, [rsp+0A8h+var_43]\nmovzx edx, [rsp+0A8h+var_3B]\nmovzx eax, [rsp+0A8h+var_3A]\nshl rax, 8\nor rax, rdx\nmovzx edx, [rsp+0A8h+var_39]\nshl rdx, 10h\nor rdx, rax\nmov rax, [rsp+0A8h+var_10]\nsub rax, fs:28h\njnz loc_13BB\nmov rax, rcx\nadd rsp, 0A0h\npop rbx\nretn\nloc_12C1:\nlea rcx, [rsp+0A8h+pmatch]; pmatch\nlea rdi, [rsp+0A8h+preg]; preg\nmov r8d, 0; eflags\nmov edx, 4; nmatch\nmov rsi, rbx; string\ncall _regexec\ntest eax, eax\njz short loc_12F1\nloc_12E2:\nlea rdi, [rsp+0A8h+preg]; preg\ncall _regfree\njmp loc_126A\nloc_12F1:\nmov edx, [rsp+0A8h+var_30]\nlea rdi, [rsp+0A8h+var_4E]\nsub rsp, 8\nmovsxd rax, edx\nadd rax, rbx\npush rax\nmov r9d, [rsp+0B8h+var_2C]\nsub r9d, edx\nlea r8, aS; \"%.*s\"\nmov ecx, 5\nmov edx, 2\nmov esi, 5\nmov eax, 0\ncall ___snprintf_chk\nmov edx, [rsp+0B8h+var_28]\nlea rdi, [rsp+0B8h+var_4E+5]\nmovsxd rax, edx\nadd rax, rbx\nmov [rsp+0B8h+var_B8], rax\nmov r9d, [rsp+0B8h+var_24]\nsub r9d, edx\nlea r8, aS; \"%.*s\"\nmov ecx, 3\nmov edx, 2\nmov esi, 3\nmov eax, 0\ncall ___snprintf_chk\nmov edx, [rsp+0B8h+var_20]\nlea rdi, [rsp+0B8h+var_46]\nmovsxd rax, edx\nadd rax, rbx\nmov [rsp+0B8h+var_B8], rax\nmov r9d, [rsp+0B8h+var_1C]\nsub r9d, edx\nlea r8, aS; \"%.*s\"\nmov ecx, 3\nmov edx, 2\nmov esi, 3\nmov eax, 0\ncall ___snprintf_chk\nadd rsp, 10h\njmp loc_12E2\nloc_13BB:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1209(char *string)\n{\n regex_t preg; // [rsp+20h] [rbp-98h] BYREF\n _BYTE v3[11]; // [rsp+6Ah] [rbp-4Eh] BYREF\n _BYTE v4[11]; // [rsp+75h] [rbp-43h]\n regmatch_t pmatch; // [rsp+80h] [rbp-38h] BYREF\n int v6; // [rsp+88h] [rbp-30h]\n int v7; // [rsp+8Ch] [rbp-2Ch]\n int v8; // [rsp+90h] [rbp-28h]\n int v9; // [rsp+94h] [rbp-24h]\n int v10; // [rsp+98h] [rbp-20h]\n int v11; // [rsp+9Ch] [rbp-1Ch]\n unsigned __int64 v12; // [rsp+A8h] [rbp-10h]\n\n v12 = __readfsqword(0x28u);\n memset(v3, 0, sizeof(v3));\n if ( !regcomp(&preg, \"/([0-9]{4})/([0-9]{1,2})/([0-9]{1,2})/\", 1) )\n {\n if ( !regexec(&preg, string, 4uLL, &pmatch, 0) )\n {\n __snprintf_chk(v3, 5LL, 2LL, 5LL, \"%.*s\", v7 - v6, &string[v6]);\n __snprintf_chk(&v3[5], 3LL, 2LL, 3LL, \"%.*s\", v9 - v8, &string[v8]);\n __snprintf_chk(&v3[8], 3LL, 2LL, 3LL, \"%.*s\", v11 - v10, &string[v10]);\n }\n regfree(&preg);\n }\n *(_QWORD *)v4 = *(_QWORD *)v3;\n *(_DWORD *)&v4[7] = *(_DWORD *)&v3[7];\n return *(_QWORD *)v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1209(char *string) {\n regex_t preg;\n uint8_t v3[11];\n uint8_t v4[11];\n regmatch_t pmatch;\n int v6;\n int v7;\n int v8;\n int v9;\n int v10;\n int v11;\n unsigned long long v12;\n v12 = __readfsqword(40u);\n memset(v3, 0, sizeof(v3));\n if (!regcomp(&preg, \"/([0-9]{4})/([0-9]{1,2})/([0-9]{1,2})/\", 1)) {\n if (!regexec(&preg, string, 4uLL, &pmatch, 0)) {\n __snprintf_chk(v3, 5LL, 2LL, 5LL, \"%.*s\", v7 - v6, &string[v6]);\n __snprintf_chk(&v3[5], 3LL, 2LL, 3LL, \"%.*s\", v9 - v8, &string[v8]);\n __snprintf_chk(&v3[8], 3LL, 2LL, 3LL, \"%.*s\", v11 - v10, &string[v10]);\n }\n regfree(&preg);\n }\n *(uint64_t *)v4 = *(uint64_t *)v3;\n *(uint32_t *)&v4[7] = *(uint32_t *)&v3[7];\n return *(uint64_t *)v4;\n}", + "ida_pseudo_norm": "long long func0(char *string) {\n regex_t preg;\n uint8_t v3[11];\n uint8_t v4[11];\n regmatch_t pmatch;\n int v6;\n int v7;\n int v8;\n int v9;\n int v10;\n int v11;\n unsigned long long v12;\n v12 = __readfsqword(40u);\n memset(v3, 0, sizeof(v3));\n if (!regcomp(&preg, \"/([0-9]{4})/([0-9]{1,2})/([0-9]{1,2})/\", 1)) {\n if (!regexec(&preg, string, 4uLL, &pmatch, 0)) {\n __snprintf_chk(v3, 5LL, 2LL, 5LL, \"%.*s\", v7 - v6, &string[v6]);\n __snprintf_chk(&v3[5], 3LL, 2LL, 3LL, \"%.*s\", v9 - v8, &string[v8]);\n __snprintf_chk(&v3[8], 3LL, 2LL, 3LL, \"%.*s\", v11 - v10, &string[v10]);\n }\n regfree(&preg);\n }\n *(uint64_t *)v4 = *(uint64_t *)v3;\n *(uint32_t *)&v4[7] = *(uint32_t *)&v3[7];\n return *(uint64_t *)v4;\n}" + }, + { + "index": 906, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char year[5];\n\n char month[3];\n\n char day[3];\n\n} Date;\n\n\n\n", + "func": "Date func0(const char* url) {\n regex_t regex;\n regmatch_t matches[4];\n Date date = {\"\", \"\", \"\"};\n const char* pattern = \"/([0-9]{4})/([0-9]{1,2})/([0-9]{1,2})/\";\n if (regcomp(®ex, pattern, REG_EXTENDED)) {\n return date;\n }\n if (!regexec(®ex, url, 4, matches, 0)) {\n int start, end;\n start = matches[1].rm_so;\n end = matches[1].rm_eo;\n snprintf(date.year, sizeof(date.year), \"%.*s\", end - start, url + start);\n start = matches[2].rm_so;\n end = matches[2].rm_eo;\n snprintf(date.month, sizeof(date.month), \"%.*s\", end - start, url + start);\n start = matches[3].rm_so;\n end = matches[3].rm_eo;\n snprintf(date.day, sizeof(date.day), \"%.*s\", end - start, url + start);\n }\n regfree(®ex);\n return date;\n}", + "test": "int main() {\n\n Date d1 = func0(\"https://www.washingtonpost.com/news/football-insider/wp/2016/09/02/odell-beckhams-fame-rests-on-one-stupid-little-ball-josh-norman-tells-author/\");\n\n assert(strcmp(d1.year, \"2016\") == 0 && strcmp(d1.month, \"09\") == 0 && strcmp(d1.day, \"02\") == 0);\n\n\n\n Date d2 = func0(\"https://www.indiatoday.in/movies/celebrities/story/wp/2020/11/03/odeof-sushant-singh-rajput-s-death-his-brother-in-law-shares-advice-for-fans-1749646/\");\n\n assert(strcmp(d2.year, \"2020\") == 0 && strcmp(d2.month, \"11\") == 0 && strcmp(d2.day, \"03\") == 0);\n\n\n\n Date d3 = func0(\"https://economictimes.indiatimes.com/news/economy/2020/12/29/finance/pension-assets-under-pfrda-touch-rs-5-32-lakh-crore/articleshow/79736619.cms\");\n\n assert(strcmp(d3.year, \"2020\") == 0 && strcmp(d3.month, \"12\") == 0 && strcmp(d3.day, \"29\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nxor %esi,%esi\nxor %ecx,%ecx\nmov $0x1,%edx\npush %rbx\nmov %rdi,%rbx\nsub $0xa8,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x98(%rsp)\nxor %eax,%eax\nlea 0x10(%rsp),%rbp\nmov %si,0x62(%rsp)\nlea 0xc4b(%rip),%rsi\nmov %rbp,%rdi\nmovl $0x0,0x5a(%rsp)\nmovb $0x0,0x5e(%rsp)\nmov %cx,0x5f(%rsp)\nmovb $0x0,0x61(%rsp)\nmovb $0x0,0x64(%rsp)\ncallq 10e0 \ntest %eax,%eax\nje 1450 \nmov 0x5a(%rsp),%rax\nmov %rax,0x65(%rsp)\nmovzwl 0x62(%rsp),%eax\nmov 0x65(%rsp),%r8\nmov %ax,0x6d(%rsp)\nmovzbl 0x64(%rsp),%eax\nmovzbl 0x6e(%rsp),%edx\nmov %al,0x6f(%rsp)\nmovzbl 0x6d(%rsp),%eax\nshl $0x8,%rdx\nor %rax,%rdx\nmovzbl 0x6f(%rsp),%eax\nshl $0x10,%rax\nor %rax,%rdx\nmov 0x98(%rsp),%rax\nxor %fs:0x28,%rax\njne 1545 \nadd $0xa8,%rsp\nmov %r8,%rax\npop %rbx\npop %rbp\nretq\nnopl 0x0(%rax,%rax,1)\nxor %r8d,%r8d\nlea 0x70(%rsp),%rcx\nmov $0x4,%edx\nmov %rbx,%rsi\nmov %rbp,%rdi\ncallq 10f0 \ntest %eax,%eax\nje 1480 \nmov %rbp,%rdi\ncallq 10b0 \njmpq 13e5 \nnopl 0x0(%rax)\nmovslq 0x78(%rsp),%rax\nlea 0x5a(%rsp),%rdi\nsub $0x8,%rsp\nlea 0xebc(%rip),%r8\nmov $0x5,%ecx\nmov $0x5,%esi\nmov %rax,%rdx\nadd %rbx,%rax\npush %rax\nmov 0x8c(%rsp),%r9d\nxor %eax,%eax\nsub %edx,%r9d\nmov $0x1,%edx\ncallq 10a0 <__snprintf_chk@plt>\nlea 0x6f(%rsp),%rdi\nmovslq 0x90(%rsp),%rax\nmov 0x94(%rsp),%r9d\nlea 0xe78(%rip),%r8\nmov $0x3,%ecx\nmov $0x3,%esi\nmov %rax,%rdx\nadd %rbx,%rax\nmov %rax,(%rsp)\nsub %edx,%r9d\nxor %eax,%eax\nmov $0x1,%edx\ncallq 10a0 <__snprintf_chk@plt>\nlea 0x72(%rsp),%r10\nmov $0x1,%edx\nmovslq 0x98(%rsp),%rdi\nmov 0x9c(%rsp),%r9d\nmov $0x3,%ecx\nmov $0x3,%esi\nlea 0xe2a(%rip),%r8\nmov %rdi,%rax\nadd %rbx,%rdi\nmov %rdi,(%rsp)\nsub %eax,%r9d\nmov %r10,%rdi\nxor %eax,%eax\ncallq 10a0 <__snprintf_chk@plt>\npop %rax\npop %rdx\njmpq 146c \ncallq 10c0 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nxor ecx, ecx\nmov rbp, rdi\nmov edx, 1; cflags\npush rbx\nlea rsi, pattern; \"/([0-9]{4})/([0-9]{1,2})/([0-9]{1,2})/\"\nsub rsp, 0A8h\nmov rax, fs:28h\nmov [rsp+0B8h+var_20], rax\nxor eax, eax\nlea rbx, [rsp+0B8h+preg]\nmov [rsp+0B8h+var_56], cx\nmov rdi, rbx; preg\nmov [rsp+0B8h+var_54], 0\nmov [rsp+0B8h+var_5E], 0\ncall _regcomp\ntest eax, eax\njz short loc_1470\nloc_1415:\nmov rax, [rsp+0B8h+var_5E]\nmov [rsp+0B8h+var_53], rax\nmov eax, dword ptr [rsp+0B8h+var_5E+7]\nmov dword ptr [rsp+0B8h+var_53+7], eax\nmovzx eax, [rsp+0B8h+var_4A]\nmovzx edx, [rsp+0B8h+var_4B]\nmov rcx, [rsp+0B8h+var_53]\nshl rax, 8\nor rax, rdx\nmovzx edx, [rsp+0B8h+var_49]\nshl rdx, 10h\nor rdx, rax\nmov rax, [rsp+0B8h+var_20]\nsub rax, fs:28h\njnz loc_1562\nadd rsp, 0A8h\nmov rax, rcx\npop rbx\npop rbp\nretn\nloc_1470:\nxor r8d, r8d; eflags\nlea rcx, [rsp+0B8h+pmatch]; pmatch\nmov edx, 4; nmatch\nmov rsi, rbp; string\nmov rdi, rbx; preg\ncall _regexec\ntest eax, eax\njz short loc_14A0\nloc_148C:\nmov rdi, rbx; preg\ncall _regfree\njmp loc_1415\nloc_14A0:\nmovsxd rax, [rsp+0B8h+var_40]\nlea rdi, [rsp+0B8h+var_5E]\nsub rsp, 8\nlea r8, aS; \"%.*s\"\nmov ecx, 5\nmov esi, 5\nmov rdx, rax\nadd rax, rbp\npush rax\nmov r9d, [rsp+0C8h+var_3C]\nxor eax, eax\nsub r9d, edx\nmov edx, 2\ncall ___snprintf_chk\nlea rdi, [rsp+0C8h+var_5E+5]\nmovsxd rax, [rsp+0C8h+var_38]\nmov r9d, [rsp+0C8h+var_34]\nlea r8, aS; \"%.*s\"\nmov ecx, 3\nmov esi, 3\nmov rdx, rax\nadd rax, rbp\nmov [rsp+0C8h+var_C8], rax\nsub r9d, edx\nxor eax, eax\nmov edx, 2\ncall ___snprintf_chk\nlea rdi, [rsp+0C8h+var_56]\nmovsxd rax, [rsp+0C8h+var_30]\nmov r9d, [rsp+0C8h+var_2C]\nlea r8, aS; \"%.*s\"\nmov ecx, 3\nmov esi, 3\nmov rdx, rax\nadd rax, rbp\nmov [rsp+0C8h+var_C8], rax\nsub r9d, edx\nxor eax, eax\nmov edx, 2\ncall ___snprintf_chk\npop rax\npop rdx\njmp loc_148C\nloc_1562:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(char *string)\n{\n regex_t preg; // [rsp+20h] [rbp-A8h] BYREF\n _BYTE v3[11]; // [rsp+6Ah] [rbp-5Eh] BYREF\n _BYTE v4[11]; // [rsp+75h] [rbp-53h]\n regmatch_t pmatch; // [rsp+80h] [rbp-48h] BYREF\n int v6; // [rsp+88h] [rbp-40h]\n int v7; // [rsp+8Ch] [rbp-3Ch]\n int v8; // [rsp+90h] [rbp-38h]\n int v9; // [rsp+94h] [rbp-34h]\n int v10; // [rsp+98h] [rbp-30h]\n int v11; // [rsp+9Ch] [rbp-2Ch]\n unsigned __int64 v12; // [rsp+A8h] [rbp-20h]\n\n v12 = __readfsqword(0x28u);\n memset(v3, 0, sizeof(v3));\n if ( !regcomp(&preg, \"/([0-9]{4})/([0-9]{1,2})/([0-9]{1,2})/\", 1) )\n {\n if ( !regexec(&preg, string, 4uLL, &pmatch, 0) )\n {\n __snprintf_chk(v3, 5LL, 2LL, 5LL, \"%.*s\", v7 - v6, &string[v6]);\n __snprintf_chk(&v3[5], 3LL, 2LL, 3LL, \"%.*s\", v9 - v8, &string[v8]);\n __snprintf_chk(&v3[8], 3LL, 2LL, 3LL, \"%.*s\", v11 - v10, &string[v10]);\n }\n regfree(&preg);\n }\n *(_QWORD *)v4 = *(_QWORD *)v3;\n *(_DWORD *)&v4[7] = *(_DWORD *)&v3[7];\n return *(_QWORD *)v4;\n}", + "ida_strip_asm": "sub_13C0:\nendbr64\npush rbp\nxor ecx, ecx\nmov rbp, rdi\nmov edx, 1; cflags\npush rbx\nlea rsi, pattern; \"/([0-9]{4})/([0-9]{1,2})/([0-9]{1,2})/\"\nsub rsp, 0A8h\nmov rax, fs:28h\nmov [rsp+0B8h+var_20], rax\nxor eax, eax\nlea rbx, [rsp+0B8h+preg]\nmov [rsp+0B8h+var_56], cx\nmov rdi, rbx; preg\nmov [rsp+0B8h+var_54], 0\nmov [rsp+0B8h+var_5E], 0\ncall _regcomp\ntest eax, eax\njz short loc_1470\nloc_1415:\nmov rax, [rsp+0B8h+var_5E]\nmov [rsp+0B8h+var_53], rax\nmov eax, dword ptr [rsp+0B8h+var_5E+7]\nmov dword ptr [rsp+0B8h+var_53+7], eax\nmovzx eax, [rsp+0B8h+var_4A]\nmovzx edx, [rsp+0B8h+var_4B]\nmov rcx, [rsp+0B8h+var_53]\nshl rax, 8\nor rax, rdx\nmovzx edx, [rsp+0B8h+var_49]\nshl rdx, 10h\nor rdx, rax\nmov rax, [rsp+0B8h+var_20]\nsub rax, fs:28h\njnz loc_1562\nadd rsp, 0A8h\nmov rax, rcx\npop rbx\npop rbp\nretn\nloc_1470:\nxor r8d, r8d; eflags\nlea rcx, [rsp+0B8h+pmatch]; pmatch\nmov edx, 4; nmatch\nmov rsi, rbp; string\nmov rdi, rbx; preg\ncall _regexec\ntest eax, eax\njz short loc_14A0\nloc_148C:\nmov rdi, rbx; preg\ncall _regfree\njmp loc_1415\nloc_14A0:\nmovsxd rax, [rsp+0B8h+var_40]\nlea rdi, [rsp+0B8h+var_5E]\nsub rsp, 8\nlea r8, aS; \"%.*s\"\nmov ecx, 5\nmov esi, 5\nmov rdx, rax\nadd rax, rbp\npush rax\nmov r9d, [rsp+0C8h+var_3C]\nxor eax, eax\nsub r9d, edx\nmov edx, 2\ncall ___snprintf_chk\nlea rdi, [rsp+0C8h+var_5E+5]\nmovsxd rax, [rsp+0C8h+var_38]\nmov r9d, [rsp+0C8h+var_34]\nlea r8, aS; \"%.*s\"\nmov ecx, 3\nmov esi, 3\nmov rdx, rax\nadd rax, rbp\nmov [rsp+0C8h+var_C8], rax\nsub r9d, edx\nxor eax, eax\nmov edx, 2\ncall ___snprintf_chk\nlea rdi, [rsp+0C8h+var_56]\nmovsxd rax, [rsp+0C8h+var_30]\nmov r9d, [rsp+0C8h+var_2C]\nlea r8, aS; \"%.*s\"\nmov ecx, 3\nmov esi, 3\nmov rdx, rax\nadd rax, rbp\nmov [rsp+0C8h+var_C8], rax\nsub r9d, edx\nxor eax, eax\nmov edx, 2\ncall ___snprintf_chk\npop rax\npop rdx\njmp loc_148C\nloc_1562:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_13C0(char *string)\n{\n regex_t preg; // [rsp+20h] [rbp-A8h] BYREF\n _BYTE v3[11]; // [rsp+6Ah] [rbp-5Eh] BYREF\n _BYTE v4[11]; // [rsp+75h] [rbp-53h]\n regmatch_t pmatch; // [rsp+80h] [rbp-48h] BYREF\n int v6; // [rsp+88h] [rbp-40h]\n int v7; // [rsp+8Ch] [rbp-3Ch]\n int v8; // [rsp+90h] [rbp-38h]\n int v9; // [rsp+94h] [rbp-34h]\n int v10; // [rsp+98h] [rbp-30h]\n int v11; // [rsp+9Ch] [rbp-2Ch]\n unsigned __int64 v12; // [rsp+A8h] [rbp-20h]\n\n v12 = __readfsqword(0x28u);\n memset(v3, 0, sizeof(v3));\n if ( !regcomp(&preg, \"/([0-9]{4})/([0-9]{1,2})/([0-9]{1,2})/\", 1) )\n {\n if ( !regexec(&preg, string, 4uLL, &pmatch, 0) )\n {\n __snprintf_chk(v3, 5LL, 2LL, 5LL, \"%.*s\", v7 - v6, &string[v6]);\n __snprintf_chk(&v3[5], 3LL, 2LL, 3LL, \"%.*s\", v9 - v8, &string[v8]);\n __snprintf_chk(&v3[8], 3LL, 2LL, 3LL, \"%.*s\", v11 - v10, &string[v10]);\n }\n regfree(&preg);\n }\n *(_QWORD *)v4 = *(_QWORD *)v3;\n *(_DWORD *)&v4[7] = *(_DWORD *)&v3[7];\n return *(_QWORD *)v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_13C0(char *string) {\n regex_t preg;\n uint8_t v3[11];\n uint8_t v4[11];\n regmatch_t pmatch;\n int v6;\n int v7;\n int v8;\n int v9;\n int v10;\n int v11;\n unsigned long long v12;\n v12 = __readfsqword(40u);\n memset(v3, 0, sizeof(v3));\n if (!regcomp(&preg, \"/([0-9]{4})/([0-9]{1,2})/([0-9]{1,2})/\", 1)) {\n if (!regexec(&preg, string, 4uLL, &pmatch, 0)) {\n __snprintf_chk(v3, 5LL, 2LL, 5LL, \"%.*s\", v7 - v6, &string[v6]);\n __snprintf_chk(&v3[5], 3LL, 2LL, 3LL, \"%.*s\", v9 - v8, &string[v8]);\n __snprintf_chk(&v3[8], 3LL, 2LL, 3LL, \"%.*s\", v11 - v10, &string[v10]);\n }\n regfree(&preg);\n }\n *(uint64_t *)v4 = *(uint64_t *)v3;\n *(uint32_t *)&v4[7] = *(uint32_t *)&v3[7];\n return *(uint64_t *)v4;\n}", + "ida_pseudo_norm": "long long func0(char *string) {\n regex_t preg;\n uint8_t v3[11];\n uint8_t v4[11];\n regmatch_t pmatch;\n int v6;\n int v7;\n int v8;\n int v9;\n int v10;\n int v11;\n unsigned long long v12;\n v12 = __readfsqword(40u);\n memset(v3, 0, sizeof(v3));\n if (!regcomp(&preg, \"/([0-9]{4})/([0-9]{1,2})/([0-9]{1,2})/\", 1)) {\n if (!regexec(&preg, string, 4uLL, &pmatch, 0)) {\n __snprintf_chk(v3, 5LL, 2LL, 5LL, \"%.*s\", v7 - v6, &string[v6]);\n __snprintf_chk(&v3[5], 3LL, 2LL, 3LL, \"%.*s\", v9 - v8, &string[v8]);\n __snprintf_chk(&v3[8], 3LL, 2LL, 3LL, \"%.*s\", v11 - v10, &string[v10]);\n }\n regfree(&preg);\n }\n *(uint64_t *)v4 = *(uint64_t *)v3;\n *(uint32_t *)&v4[7] = *(uint32_t *)&v3[7];\n return *(uint64_t *)v4;\n}" + }, + { + "index": 906, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char year[5];\n\n char month[3];\n\n char day[3];\n\n} Date;\n\n\n\n", + "func": "Date func0(const char* url) {\n regex_t regex;\n regmatch_t matches[4];\n Date date = {\"\", \"\", \"\"};\n const char* pattern = \"/([0-9]{4})/([0-9]{1,2})/([0-9]{1,2})/\";\n if (regcomp(®ex, pattern, REG_EXTENDED)) {\n return date;\n }\n if (!regexec(®ex, url, 4, matches, 0)) {\n int start, end;\n start = matches[1].rm_so;\n end = matches[1].rm_eo;\n snprintf(date.year, sizeof(date.year), \"%.*s\", end - start, url + start);\n start = matches[2].rm_so;\n end = matches[2].rm_eo;\n snprintf(date.month, sizeof(date.month), \"%.*s\", end - start, url + start);\n start = matches[3].rm_so;\n end = matches[3].rm_eo;\n snprintf(date.day, sizeof(date.day), \"%.*s\", end - start, url + start);\n }\n regfree(®ex);\n return date;\n}", + "test": "int main() {\n\n Date d1 = func0(\"https://www.washingtonpost.com/news/football-insider/wp/2016/09/02/odell-beckhams-fame-rests-on-one-stupid-little-ball-josh-norman-tells-author/\");\n\n assert(strcmp(d1.year, \"2016\") == 0 && strcmp(d1.month, \"09\") == 0 && strcmp(d1.day, \"02\") == 0);\n\n\n\n Date d2 = func0(\"https://www.indiatoday.in/movies/celebrities/story/wp/2020/11/03/odeof-sushant-singh-rajput-s-death-his-brother-in-law-shares-advice-for-fans-1749646/\");\n\n assert(strcmp(d2.year, \"2020\") == 0 && strcmp(d2.month, \"11\") == 0 && strcmp(d2.day, \"03\") == 0);\n\n\n\n Date d3 = func0(\"https://economictimes.indiatimes.com/news/economy/2020/12/29/finance/pension-assets-under-pfrda-touch-rs-5-32-lakh-crore/articleshow/79736619.cms\");\n\n assert(strcmp(d3.year, \"2020\") == 0 && strcmp(d3.month, \"12\") == 0 && strcmp(d3.day, \"29\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nxor %esi,%esi\nxor %ecx,%ecx\nmov $0x1,%edx\npush %rbx\nmov %rdi,%rbx\nsub $0xa8,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x98(%rsp)\nxor %eax,%eax\nlea 0x10(%rsp),%rbp\nmov %si,0x62(%rsp)\nlea 0xc4b(%rip),%rsi\nmov %rbp,%rdi\nmovl $0x0,0x5a(%rsp)\nmovb $0x0,0x5e(%rsp)\nmov %cx,0x5f(%rsp)\nmovb $0x0,0x61(%rsp)\nmovb $0x0,0x64(%rsp)\ncallq 10e0 \ntest %eax,%eax\nje 1450 \nmov 0x5a(%rsp),%rax\nmov %rax,0x65(%rsp)\nmovzwl 0x62(%rsp),%eax\nmov 0x65(%rsp),%r8\nmov %ax,0x6d(%rsp)\nmovzbl 0x64(%rsp),%eax\nmovzbl 0x6e(%rsp),%edx\nmov %al,0x6f(%rsp)\nmovzbl 0x6d(%rsp),%eax\nshl $0x8,%rdx\nor %rax,%rdx\nmovzbl 0x6f(%rsp),%eax\nshl $0x10,%rax\nor %rax,%rdx\nmov 0x98(%rsp),%rax\nxor %fs:0x28,%rax\njne 1545 \nadd $0xa8,%rsp\nmov %r8,%rax\npop %rbx\npop %rbp\nretq\nnopl 0x0(%rax,%rax,1)\nxor %r8d,%r8d\nlea 0x70(%rsp),%rcx\nmov $0x4,%edx\nmov %rbx,%rsi\nmov %rbp,%rdi\ncallq 10f0 \ntest %eax,%eax\nje 1480 \nmov %rbp,%rdi\ncallq 10b0 \njmpq 13e5 \nnopl 0x0(%rax)\nmovslq 0x78(%rsp),%rax\nlea 0x5a(%rsp),%rdi\nsub $0x8,%rsp\nlea 0xebc(%rip),%r8\nmov $0x5,%ecx\nmov $0x5,%esi\nmov %rax,%rdx\nadd %rbx,%rax\npush %rax\nmov 0x8c(%rsp),%r9d\nxor %eax,%eax\nsub %edx,%r9d\nmov $0x1,%edx\ncallq 10a0 <__snprintf_chk@plt>\nlea 0x6f(%rsp),%rdi\nmovslq 0x90(%rsp),%rax\nmov 0x94(%rsp),%r9d\nlea 0xe78(%rip),%r8\nmov $0x3,%ecx\nmov $0x3,%esi\nmov %rax,%rdx\nadd %rbx,%rax\nmov %rax,(%rsp)\nsub %edx,%r9d\nxor %eax,%eax\nmov $0x1,%edx\ncallq 10a0 <__snprintf_chk@plt>\nlea 0x72(%rsp),%r10\nmov $0x1,%edx\nmovslq 0x98(%rsp),%rdi\nmov 0x9c(%rsp),%r9d\nmov $0x3,%ecx\nmov $0x3,%esi\nlea 0xe2a(%rip),%r8\nmov %rdi,%rax\nadd %rbx,%rdi\nmov %rdi,(%rsp)\nsub %eax,%r9d\nmov %r10,%rdi\nxor %eax,%eax\ncallq 10a0 <__snprintf_chk@plt>\npop %rax\npop %rdx\njmpq 146c \ncallq 10c0 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nxor ecx, ecx\nmov rbp, rdi\nmov edx, 1; cflags\npush rbx\nlea rsi, pattern; \"/([0-9]{4})/([0-9]{1,2})/([0-9]{1,2})/\"\nsub rsp, 0A8h\nmov rax, fs:28h\nmov [rsp+0B8h+var_20], rax\nxor eax, eax\nlea rbx, [rsp+0B8h+preg]\nmov [rsp+0B8h+var_56], cx\nmov rdi, rbx; preg\nmov [rsp+0B8h+var_54], 0\nmov [rsp+0B8h+var_5E], 0\ncall _regcomp\ntest eax, eax\njz short loc_1470\nloc_1415:\nmov rax, [rsp+0B8h+var_5E]\nmov [rsp+0B8h+var_53], rax\nmov eax, dword ptr [rsp+0B8h+var_5E+7]\nmov dword ptr [rsp+0B8h+var_53+7], eax\nmovzx eax, [rsp+0B8h+var_4A]\nmovzx edx, [rsp+0B8h+var_4B]\nmov rcx, [rsp+0B8h+var_53]\nshl rax, 8\nor rax, rdx\nmovzx edx, [rsp+0B8h+var_49]\nshl rdx, 10h\nor rdx, rax\nmov rax, [rsp+0B8h+var_20]\nsub rax, fs:28h\njnz loc_1562\nadd rsp, 0A8h\nmov rax, rcx\npop rbx\npop rbp\nretn\nloc_1470:\nxor r8d, r8d; eflags\nlea rcx, [rsp+0B8h+pmatch]; pmatch\nmov edx, 4; nmatch\nmov rsi, rbp; string\nmov rdi, rbx; preg\ncall _regexec\ntest eax, eax\njz short loc_14A0\nloc_148C:\nmov rdi, rbx; preg\ncall _regfree\njmp loc_1415\nloc_14A0:\nmovsxd rax, [rsp+0B8h+var_40]\nlea rdi, [rsp+0B8h+var_5E]\nsub rsp, 8\nlea r8, aS; \"%.*s\"\nmov ecx, 5\nmov esi, 5\nmov rdx, rax\nadd rax, rbp\npush rax\nmov r9d, [rsp+0C8h+var_3C]\nxor eax, eax\nsub r9d, edx\nmov edx, 2\ncall ___snprintf_chk\nlea rdi, [rsp+0C8h+var_5E+5]\nmovsxd rax, [rsp+0C8h+var_38]\nmov r9d, [rsp+0C8h+var_34]\nlea r8, aS; \"%.*s\"\nmov ecx, 3\nmov esi, 3\nmov rdx, rax\nadd rax, rbp\nmov [rsp+0C8h+var_C8], rax\nsub r9d, edx\nxor eax, eax\nmov edx, 2\ncall ___snprintf_chk\nlea rdi, [rsp+0C8h+var_56]\nmovsxd rax, [rsp+0C8h+var_30]\nmov r9d, [rsp+0C8h+var_2C]\nlea r8, aS; \"%.*s\"\nmov ecx, 3\nmov esi, 3\nmov rdx, rax\nadd rax, rbp\nmov [rsp+0C8h+var_C8], rax\nsub r9d, edx\nxor eax, eax\nmov edx, 2\ncall ___snprintf_chk\npop rax\npop rdx\njmp loc_148C\nloc_1562:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(char *string)\n{\n regex_t preg; // [rsp+20h] [rbp-A8h] BYREF\n _BYTE v3[11]; // [rsp+6Ah] [rbp-5Eh] BYREF\n _BYTE v4[11]; // [rsp+75h] [rbp-53h]\n regmatch_t pmatch; // [rsp+80h] [rbp-48h] BYREF\n int v6; // [rsp+88h] [rbp-40h]\n int v7; // [rsp+8Ch] [rbp-3Ch]\n int v8; // [rsp+90h] [rbp-38h]\n int v9; // [rsp+94h] [rbp-34h]\n int v10; // [rsp+98h] [rbp-30h]\n int v11; // [rsp+9Ch] [rbp-2Ch]\n unsigned __int64 v12; // [rsp+A8h] [rbp-20h]\n\n v12 = __readfsqword(0x28u);\n memset(v3, 0, sizeof(v3));\n if ( !regcomp(&preg, \"/([0-9]{4})/([0-9]{1,2})/([0-9]{1,2})/\", 1) )\n {\n if ( !regexec(&preg, string, 4uLL, &pmatch, 0) )\n {\n __snprintf_chk(v3, 5LL, 2LL, 5LL, \"%.*s\", v7 - v6, &string[v6]);\n __snprintf_chk(&v3[5], 3LL, 2LL, 3LL, \"%.*s\", v9 - v8, &string[v8]);\n __snprintf_chk(&v3[8], 3LL, 2LL, 3LL, \"%.*s\", v11 - v10, &string[v10]);\n }\n regfree(&preg);\n }\n *(_QWORD *)v4 = *(_QWORD *)v3;\n *(_DWORD *)&v4[7] = *(_DWORD *)&v3[7];\n return *(_QWORD *)v4;\n}", + "ida_strip_asm": "sub_13C0:\nendbr64\npush rbp\nxor ecx, ecx\nmov rbp, rdi\nmov edx, 1; cflags\npush rbx\nlea rsi, pattern; \"/([0-9]{4})/([0-9]{1,2})/([0-9]{1,2})/\"\nsub rsp, 0A8h\nmov rax, fs:28h\nmov [rsp+0B8h+var_20], rax\nxor eax, eax\nlea rbx, [rsp+0B8h+preg]\nmov [rsp+0B8h+var_56], cx\nmov rdi, rbx; preg\nmov [rsp+0B8h+var_54], 0\nmov [rsp+0B8h+var_5E], 0\ncall _regcomp\ntest eax, eax\njz short loc_1470\nloc_1415:\nmov rax, [rsp+0B8h+var_5E]\nmov [rsp+0B8h+var_53], rax\nmov eax, dword ptr [rsp+0B8h+var_5E+7]\nmov dword ptr [rsp+0B8h+var_53+7], eax\nmovzx eax, [rsp+0B8h+var_4A]\nmovzx edx, [rsp+0B8h+var_4B]\nmov rcx, [rsp+0B8h+var_53]\nshl rax, 8\nor rax, rdx\nmovzx edx, [rsp+0B8h+var_49]\nshl rdx, 10h\nor rdx, rax\nmov rax, [rsp+0B8h+var_20]\nsub rax, fs:28h\njnz loc_1562\nadd rsp, 0A8h\nmov rax, rcx\npop rbx\npop rbp\nretn\nloc_1470:\nxor r8d, r8d; eflags\nlea rcx, [rsp+0B8h+pmatch]; pmatch\nmov edx, 4; nmatch\nmov rsi, rbp; string\nmov rdi, rbx; preg\ncall _regexec\ntest eax, eax\njz short loc_14A0\nloc_148C:\nmov rdi, rbx; preg\ncall _regfree\njmp loc_1415\nloc_14A0:\nmovsxd rax, [rsp+0B8h+var_40]\nlea rdi, [rsp+0B8h+var_5E]\nsub rsp, 8\nlea r8, aS; \"%.*s\"\nmov ecx, 5\nmov esi, 5\nmov rdx, rax\nadd rax, rbp\npush rax\nmov r9d, [rsp+0C8h+var_3C]\nxor eax, eax\nsub r9d, edx\nmov edx, 2\ncall ___snprintf_chk\nlea rdi, [rsp+0C8h+var_5E+5]\nmovsxd rax, [rsp+0C8h+var_38]\nmov r9d, [rsp+0C8h+var_34]\nlea r8, aS; \"%.*s\"\nmov ecx, 3\nmov esi, 3\nmov rdx, rax\nadd rax, rbp\nmov [rsp+0C8h+var_C8], rax\nsub r9d, edx\nxor eax, eax\nmov edx, 2\ncall ___snprintf_chk\nlea rdi, [rsp+0C8h+var_56]\nmovsxd rax, [rsp+0C8h+var_30]\nmov r9d, [rsp+0C8h+var_2C]\nlea r8, aS; \"%.*s\"\nmov ecx, 3\nmov esi, 3\nmov rdx, rax\nadd rax, rbp\nmov [rsp+0C8h+var_C8], rax\nsub r9d, edx\nxor eax, eax\nmov edx, 2\ncall ___snprintf_chk\npop rax\npop rdx\njmp loc_148C\nloc_1562:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_13C0(char *string)\n{\n regex_t preg; // [rsp+20h] [rbp-A8h] BYREF\n _BYTE v3[11]; // [rsp+6Ah] [rbp-5Eh] BYREF\n _BYTE v4[11]; // [rsp+75h] [rbp-53h]\n regmatch_t pmatch; // [rsp+80h] [rbp-48h] BYREF\n int v6; // [rsp+88h] [rbp-40h]\n int v7; // [rsp+8Ch] [rbp-3Ch]\n int v8; // [rsp+90h] [rbp-38h]\n int v9; // [rsp+94h] [rbp-34h]\n int v10; // [rsp+98h] [rbp-30h]\n int v11; // [rsp+9Ch] [rbp-2Ch]\n unsigned __int64 v12; // [rsp+A8h] [rbp-20h]\n\n v12 = __readfsqword(0x28u);\n memset(v3, 0, sizeof(v3));\n if ( !regcomp(&preg, \"/([0-9]{4})/([0-9]{1,2})/([0-9]{1,2})/\", 1) )\n {\n if ( !regexec(&preg, string, 4uLL, &pmatch, 0) )\n {\n __snprintf_chk(v3, 5LL, 2LL, 5LL, \"%.*s\", v7 - v6, &string[v6]);\n __snprintf_chk(&v3[5], 3LL, 2LL, 3LL, \"%.*s\", v9 - v8, &string[v8]);\n __snprintf_chk(&v3[8], 3LL, 2LL, 3LL, \"%.*s\", v11 - v10, &string[v10]);\n }\n regfree(&preg);\n }\n *(_QWORD *)v4 = *(_QWORD *)v3;\n *(_DWORD *)&v4[7] = *(_DWORD *)&v3[7];\n return *(_QWORD *)v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_13C0(char *string) {\n regex_t preg;\n uint8_t v3[11];\n uint8_t v4[11];\n regmatch_t pmatch;\n int v6;\n int v7;\n int v8;\n int v9;\n int v10;\n int v11;\n unsigned long long v12;\n v12 = __readfsqword(40u);\n memset(v3, 0, sizeof(v3));\n if (!regcomp(&preg, \"/([0-9]{4})/([0-9]{1,2})/([0-9]{1,2})/\", 1)) {\n if (!regexec(&preg, string, 4uLL, &pmatch, 0)) {\n __snprintf_chk(v3, 5LL, 2LL, 5LL, \"%.*s\", v7 - v6, &string[v6]);\n __snprintf_chk(&v3[5], 3LL, 2LL, 3LL, \"%.*s\", v9 - v8, &string[v8]);\n __snprintf_chk(&v3[8], 3LL, 2LL, 3LL, \"%.*s\", v11 - v10, &string[v10]);\n }\n regfree(&preg);\n }\n *(uint64_t *)v4 = *(uint64_t *)v3;\n *(uint32_t *)&v4[7] = *(uint32_t *)&v3[7];\n return *(uint64_t *)v4;\n}", + "ida_pseudo_norm": "long long func0(char *string) {\n regex_t preg;\n uint8_t v3[11];\n uint8_t v4[11];\n regmatch_t pmatch;\n int v6;\n int v7;\n int v8;\n int v9;\n int v10;\n int v11;\n unsigned long long v12;\n v12 = __readfsqword(40u);\n memset(v3, 0, sizeof(v3));\n if (!regcomp(&preg, \"/([0-9]{4})/([0-9]{1,2})/([0-9]{1,2})/\", 1)) {\n if (!regexec(&preg, string, 4uLL, &pmatch, 0)) {\n __snprintf_chk(v3, 5LL, 2LL, 5LL, \"%.*s\", v7 - v6, &string[v6]);\n __snprintf_chk(&v3[5], 3LL, 2LL, 3LL, \"%.*s\", v9 - v8, &string[v8]);\n __snprintf_chk(&v3[8], 3LL, 2LL, 3LL, \"%.*s\", v11 - v10, &string[v10]);\n }\n regfree(&preg);\n }\n *(uint64_t *)v4 = *(uint64_t *)v3;\n *(uint32_t *)&v4[7] = *(uint32_t *)&v3[7];\n return *(uint64_t *)v4;\n}" + }, + { + "index": 907, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int n) {\n int size = n * n + 9;\n int capacity = (size + 1) / 2;\n int* list = malloc(capacity * sizeof(int));\n if (!list) return NULL;\n int index = 0;\n for (int num = -1; num < size; num += 2) {\n list[index++] = num;\n }\n int current_size = index;\n int i = 2;\n while (i < current_size) {\n if (i >= current_size) break;\n int step = list[i];\n if (step <= 0) break;\n int* new_list = malloc(current_size * sizeof(int));\n int new_index = 0;\n for (int j = 0; j < current_size; j++) {\n if ((j < step) || ((j - step) % step != 0)) {\n new_list[new_index++] = list[j];\n }\n }\n free(list);\n list = new_list;\n current_size = new_index;\n i++;\n }\n int* result = malloc(n * sizeof(int));\n for (int k = 0; k < n; k++) {\n if (k + 1 < current_size) {\n result[k] = list[k + 1];\n } else {\n result[k] = 0;\n }\n }\n free(list);\n return result;\n}", + "test": "int main() {\n\n int expected1[10] = {1, 3, 7, 9, 13, 15, 21, 25, 31, 33};\n\n int expected2[5] = {1, 3, 7, 9, 13};\n\n int expected3[8] = {1, 3, 7, 9, 13, 15, 21, 25};\n\n\n\n int* result1 = func0(10);\n\n for(int i = 0; i < 10; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n free(result1);\n\n\n\n int* result2 = func0(5);\n\n for(int i = 0; i < 5; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n free(result2);\n\n\n\n int* result3 = func0(8);\n\n for(int i = 0; i < 8; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x50,%rsp\nmov %edi,-0x44(%rbp)\nmov -0x44(%rbp),%eax\nimul %eax,%eax\nadd $0x9,%eax\nmov %eax,-0x24(%rbp)\nmov -0x24(%rbp),%eax\nadd $0x1,%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nmov %eax,-0x20(%rbp)\nmov -0x20(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x18(%rbp)\ncmpq $0x0,-0x18(%rbp)\njne 11fc \nmov $0x0,%eax\njmpq 13b6 \nmovl $0x0,-0x40(%rbp)\nmovl $0xffffffff,-0x3c(%rbp)\njmp 122f \nmov -0x40(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x40(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0x3c(%rbp),%eax\nmov %eax,(%rdx)\naddl $0x2,-0x3c(%rbp)\nmov -0x3c(%rbp),%eax\ncmp -0x24(%rbp),%eax\njl 120c \nmov -0x40(%rbp),%eax\nmov %eax,-0x38(%rbp)\nmovl $0x2,-0x34(%rbp)\njmpq 1312 \nmov -0x34(%rbp),%eax\ncmp -0x38(%rbp),%eax\njge 1320 \nmov -0x34(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x1c(%rbp)\ncmpl $0x0,-0x1c(%rbp)\njle 1323 \nmov -0x38(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x10(%rbp)\nmovl $0x0,-0x30(%rbp)\nmovl $0x0,-0x2c(%rbp)\njmp 12ec \nmov -0x2c(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 12b5 \nmov -0x2c(%rbp),%eax\nsub -0x1c(%rbp),%eax\ncltd\nidivl -0x1c(%rbp)\nmov %edx,%eax\ntest %eax,%eax\nje 12e8 \nmov -0x2c(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x30(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x30(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x10(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x2c(%rbp)\nmov -0x2c(%rbp),%eax\ncmp -0x38(%rbp),%eax\njl 129d \nmov -0x18(%rbp),%rax\nmov %rax,%rdi\ncallq 1080 \nmov -0x10(%rbp),%rax\nmov %rax,-0x18(%rbp)\nmov -0x30(%rbp),%eax\nmov %eax,-0x38(%rbp)\naddl $0x1,-0x34(%rbp)\nmov -0x34(%rbp),%eax\ncmp -0x38(%rbp),%eax\njl 1249 \njmp 1324 \njmp 1324 \nmov -0x44(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0x28(%rbp)\njmp 139e \nmov -0x28(%rbp),%eax\nadd $0x1,%eax\ncmp %eax,-0x38(%rbp)\njle 1380 \nmov -0x28(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0x28(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\njmp 139a \nmov -0x28(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmovl $0x0,(%rax)\naddl $0x1,-0x28(%rbp)\nmov -0x28(%rbp),%eax\ncmp -0x44(%rbp),%eax\njl 1342 \nmov -0x18(%rbp),%rax\nmov %rax,%rdi\ncallq 1080 \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+var_44], edi\nmov eax, [rbp+var_44]\nimul eax, eax\nadd eax, 9\nmov [rbp+var_24], eax\nmov eax, [rbp+var_24]\nadd eax, 1\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_20], eax\nmov eax, [rbp+var_20]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\ncmp [rbp+ptr], 0\njnz short loc_11FC\nmov eax, 0\njmp locret_13B6\nloc_11FC:\nmov [rbp+var_40], 0\nmov [rbp+var_3C], 0FFFFFFFFh\njmp short loc_122F\nloc_120C:\nmov eax, [rbp+var_40]\nlea edx, [rax+1]\nmov [rbp+var_40], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov eax, [rbp+var_3C]\nmov [rdx], eax\nadd [rbp+var_3C], 2\nloc_122F:\nmov eax, [rbp+var_3C]\ncmp eax, [rbp+var_24]\njl short loc_120C\nmov eax, [rbp+var_40]\nmov [rbp+var_38], eax\nmov [rbp+var_34], 2\njmp loc_1312\nloc_1249:\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_38]\njge loc_1320\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_1C], eax\ncmp [rbp+var_1C], 0\njle loc_1323\nmov eax, [rbp+var_38]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_10], rax\nmov [rbp+var_30], 0\nmov [rbp+var_2C], 0\njmp short loc_12EC\nloc_129D:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_1C]\njl short loc_12B5\nmov eax, [rbp+var_2C]\nsub eax, [rbp+var_1C]\ncdq\nidiv [rbp+var_1C]\nmov eax, edx\ntest eax, eax\njz short loc_12E8\nloc_12B5:\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_30]\nlea edx, [rax+1]\nmov [rbp+var_30], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_10]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_12E8:\nadd [rbp+var_2C], 1\nloc_12EC:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_38]\njl short loc_129D\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_10]\nmov [rbp+ptr], rax\nmov eax, [rbp+var_30]\nmov [rbp+var_38], eax\nadd [rbp+var_34], 1\nloc_1312:\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_38]\njl loc_1249\njmp short loc_1324\nloc_1320:\nnop\njmp short loc_1324\nloc_1323:\nnop\nloc_1324:\nmov eax, [rbp+var_44]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_28], 0\njmp short loc_139E\nloc_1342:\nmov eax, [rbp+var_28]\nadd eax, 1\ncmp [rbp+var_38], eax\njle short loc_1380\nmov eax, [rbp+var_28]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\njmp short loc_139A\nloc_1380:\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov dword ptr [rax], 0\nloc_139A:\nadd [rbp+var_28], 1\nloc_139E:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_44]\njl short loc_1342\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_8]\nlocret_13B6:\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(int a1)\n{\n int v2; // eax\n int v3; // eax\n int v4; // [rsp+10h] [rbp-40h]\n int i; // [rsp+14h] [rbp-3Ch]\n int v6; // [rsp+18h] [rbp-38h]\n int j; // [rsp+1Ch] [rbp-34h]\n int v8; // [rsp+20h] [rbp-30h]\n int k; // [rsp+24h] [rbp-2Ch]\n int m; // [rsp+28h] [rbp-28h]\n int v11; // [rsp+34h] [rbp-1Ch]\n _DWORD *ptr; // [rsp+38h] [rbp-18h]\n _DWORD *v13; // [rsp+40h] [rbp-10h]\n _DWORD *v14; // [rsp+48h] [rbp-8h]\n\n ptr = malloc(4LL * ((a1 * a1 + 10) / 2));\n if ( !ptr )\n return 0LL;\n v4 = 0;\n for ( i = -1; i < a1 * a1 + 9; i += 2 )\n {\n v2 = v4++;\n ptr[v2] = i;\n }\n v6 = v4;\n for ( j = 2; j < v6; ++j )\n {\n v11 = ptr[j];\n if ( v11 <= 0 )\n break;\n v13 = malloc(4LL * v6);\n v8 = 0;\n for ( k = 0; k < v6; ++k )\n {\n if ( k < v11 || (k - v11) % v11 )\n {\n v3 = v8++;\n v13[v3] = ptr[k];\n }\n }\n free(ptr);\n ptr = v13;\n v6 = v8;\n }\n v14 = malloc(4LL * a1);\n for ( m = 0; m < a1; ++m )\n {\n if ( v6 <= m + 1 )\n v14[m] = 0;\n else\n v14[m] = ptr[m + 1];\n }\n free(ptr);\n return v14;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+var_44], edi\nmov eax, [rbp+var_44]\nimul eax, eax\nadd eax, 9\nmov [rbp+var_24], eax\nmov eax, [rbp+var_24]\nadd eax, 1\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov [rbp+var_20], eax\nmov eax, [rbp+var_20]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\ncmp [rbp+ptr], 0\njnz short loc_11FC\nmov eax, 0\njmp locret_13B6\nloc_11FC:\nmov [rbp+var_40], 0\nmov [rbp+var_3C], 0FFFFFFFFh\njmp short loc_122F\nloc_120C:\nmov eax, [rbp+var_40]\nlea edx, [rax+1]\nmov [rbp+var_40], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rdx, rax\nmov eax, [rbp+var_3C]\nmov [rdx], eax\nadd [rbp+var_3C], 2\nloc_122F:\nmov eax, [rbp+var_3C]\ncmp eax, [rbp+var_24]\njl short loc_120C\nmov eax, [rbp+var_40]\nmov [rbp+var_38], eax\nmov [rbp+var_34], 2\njmp loc_1312\nloc_1249:\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_38]\njge loc_1320\nmov eax, [rbp+var_34]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_1C], eax\ncmp [rbp+var_1C], 0\njle loc_1323\nmov eax, [rbp+var_38]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_10], rax\nmov [rbp+var_30], 0\nmov [rbp+var_2C], 0\njmp short loc_12EC\nloc_129D:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_1C]\njl short loc_12B5\nmov eax, [rbp+var_2C]\nsub eax, [rbp+var_1C]\ncdq\nidiv [rbp+var_1C]\nmov eax, edx\ntest eax, eax\njz short loc_12E8\nloc_12B5:\nmov eax, [rbp+var_2C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_30]\nlea edx, [rax+1]\nmov [rbp+var_30], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_10]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_12E8:\nadd [rbp+var_2C], 1\nloc_12EC:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_38]\njl short loc_129D\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_10]\nmov [rbp+ptr], rax\nmov eax, [rbp+var_30]\nmov [rbp+var_38], eax\nadd [rbp+var_34], 1\nloc_1312:\nmov eax, [rbp+var_34]\ncmp eax, [rbp+var_38]\njl loc_1249\njmp short loc_1324\nloc_1320:\nnop\njmp short loc_1324\nloc_1323:\nnop\nloc_1324:\nmov eax, [rbp+var_44]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_28], 0\njmp short loc_139E\nloc_1342:\nmov eax, [rbp+var_28]\nadd eax, 1\ncmp [rbp+var_38], eax\njle short loc_1380\nmov eax, [rbp+var_28]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\njmp short loc_139A\nloc_1380:\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov dword ptr [rax], 0\nloc_139A:\nadd [rbp+var_28], 1\nloc_139E:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_44]\njl short loc_1342\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov rax, [rbp+var_8]\nlocret_13B6:\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(int a1)\n{\n int v2; // eax\n int v3; // eax\n int v4; // [rsp+10h] [rbp-40h]\n int i; // [rsp+14h] [rbp-3Ch]\n int v6; // [rsp+18h] [rbp-38h]\n int j; // [rsp+1Ch] [rbp-34h]\n int v8; // [rsp+20h] [rbp-30h]\n int k; // [rsp+24h] [rbp-2Ch]\n int m; // [rsp+28h] [rbp-28h]\n int v11; // [rsp+34h] [rbp-1Ch]\n _DWORD *ptr; // [rsp+38h] [rbp-18h]\n _DWORD *v13; // [rsp+40h] [rbp-10h]\n _DWORD *v14; // [rsp+48h] [rbp-8h]\n\n ptr = malloc(4LL * ((a1 * a1 + 10) / 2));\n if ( !ptr )\n return 0LL;\n v4 = 0;\n for ( i = -1; i < a1 * a1 + 9; i += 2 )\n {\n v2 = v4++;\n ptr[v2] = i;\n }\n v6 = v4;\n for ( j = 2; j < v6; ++j )\n {\n v11 = ptr[j];\n if ( v11 <= 0 )\n break;\n v13 = malloc(4LL * v6);\n v8 = 0;\n for ( k = 0; k < v6; ++k )\n {\n if ( k < v11 || (k - v11) % v11 )\n {\n v3 = v8++;\n v13[v3] = ptr[k];\n }\n }\n free(ptr);\n ptr = v13;\n v6 = v8;\n }\n v14 = malloc(4LL * a1);\n for ( m = 0; m < a1; ++m )\n {\n if ( v6 <= m + 1 )\n v14[m] = 0;\n else\n v14[m] = ptr[m + 1];\n }\n free(ptr);\n return v14;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(int a1) {\n int v2;\n int v3;\n int v4;\n int i;\n int v6;\n int j;\n int v8;\n int k;\n int m;\n int v11;\n uint32_t *ptr;\n uint32_t *v13;\n uint32_t *v14;\n ptr = malloc(4LL * ((a1 * a1 + 10) / 2));\n if (!ptr) return 0LL;\n v4 = 0;\n for (i = -1; i < a1 * a1 + 9; i += 2) {\n v2 = v4++;\n ptr[v2] = i;\n }\n v6 = v4;\n for (j = 2; j < v6; ++j) {\n v11 = ptr[j];\n if (v11 <= 0) break;\n v13 = malloc(4LL * v6);\n v8 = 0;\n for (k = 0; k < v6; ++k) {\n if (k < v11 || (k - v11) % v11) {\n v3 = v8++;\n v13[v3] = ptr[k];\n }\n }\n free(ptr);\n ptr = v13;\n v6 = v8;\n }\n v14 = malloc(4LL * a1);\n for (m = 0; m < a1; ++m) {\n if (v6 <= m + 1)\n v14[m] = 0;\n else\n v14[m] = ptr[m + 1];\n }\n free(ptr);\n return v14;\n}", + "ida_pseudo_norm": "uint32_t *func0(int a1) {\n int v2;\n int v3;\n int v4;\n int i;\n int v6;\n int j;\n int v8;\n int k;\n int m;\n int v11;\n uint32_t *ptr;\n uint32_t *v13;\n uint32_t *v14;\n ptr = malloc(4LL * ((a1 * a1 + 10) / 2));\n if (!ptr) return 0LL;\n v4 = 0;\n for (i = -1; i < a1 * a1 + 9; i += 2) {\n v2 = v4++;\n ptr[v2] = i;\n }\n v6 = v4;\n for (j = 2; j < v6; ++j) {\n v11 = ptr[j];\n if (v11 <= 0) break;\n v13 = malloc(4LL * v6);\n v8 = 0;\n for (k = 0; k < v6; ++k) {\n if (k < v11 || (k - v11) % v11) {\n v3 = v8++;\n v13[v3] = ptr[k];\n }\n }\n free(ptr);\n ptr = v13;\n v6 = v8;\n }\n v14 = malloc(4LL * a1);\n for (m = 0; m < a1; ++m) {\n if (v6 <= m + 1)\n v14[m] = 0;\n else\n v14[m] = ptr[m + 1];\n }\n free(ptr);\n return v14;\n}" + }, + { + "index": 907, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int n) {\n int size = n * n + 9;\n int capacity = (size + 1) / 2;\n int* list = malloc(capacity * sizeof(int));\n if (!list) return NULL;\n int index = 0;\n for (int num = -1; num < size; num += 2) {\n list[index++] = num;\n }\n int current_size = index;\n int i = 2;\n while (i < current_size) {\n if (i >= current_size) break;\n int step = list[i];\n if (step <= 0) break;\n int* new_list = malloc(current_size * sizeof(int));\n int new_index = 0;\n for (int j = 0; j < current_size; j++) {\n if ((j < step) || ((j - step) % step != 0)) {\n new_list[new_index++] = list[j];\n }\n }\n free(list);\n list = new_list;\n current_size = new_index;\n i++;\n }\n int* result = malloc(n * sizeof(int));\n for (int k = 0; k < n; k++) {\n if (k + 1 < current_size) {\n result[k] = list[k + 1];\n } else {\n result[k] = 0;\n }\n }\n free(list);\n return result;\n}", + "test": "int main() {\n\n int expected1[10] = {1, 3, 7, 9, 13, 15, 21, 25, 31, 33};\n\n int expected2[5] = {1, 3, 7, 9, 13};\n\n int expected3[8] = {1, 3, 7, 9, 13, 15, 21, 25};\n\n\n\n int* result1 = func0(10);\n\n for(int i = 0; i < 10; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n free(result1);\n\n\n\n int* result2 = func0(5);\n\n for(int i = 0; i < 5; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n free(result2);\n\n\n\n int* result3 = func0(8);\n\n for(int i = 0; i < 8; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov %edi,0xc(%rsp)\nmov %edi,%ebp\nimul %edi,%ebp\nlea 0xa(%rbp),%eax\nmov %eax,%edi\nshr $0x1f,%edi\nadd %eax,%edi\nsar %edi\nmovslq %edi,%rdi\nshl $0x2,%rdi\ncallq 10b0 \nmov %rax,%r12\ntest %rax,%rax\nje 12ed \nlea 0x9(%rbp),%ebx\nmov %rax,%rdx\nmov $0xffffffff,%eax\nmov %eax,(%rdx)\nadd $0x2,%eax\nadd $0x4,%rdx\ncmp %eax,%ebx\njg 11f3 \nadd $0x9,%ebp\nshr %ebp\nlea 0x1(%rbp),%ebx\nmov $0x8,%r14d\nmov $0x2,%r15d\njmp 125f \nmov (%r12,%rcx,4),%edx\nmovslq %ebx,%rax\nmov %edx,0x0(%r13,%rax,4)\nlea 0x1(%rbx),%ebx\nlea 0x1(%rcx),%rax\ncmp %rsi,%rcx\nje 1247 \nmov %rax,%rcx\ncmp %ecx,%ebp\njg 1216 \nmov %ecx,%eax\nsub %ebp,%eax\ncltd\nidiv %ebp\ntest %edx,%edx\nje 1225 \njmp 1216 \nmov $0x0,%ebx\nmov %r12,%rdi\ncallq 1080 \nadd $0x1,%r15d\nadd $0x4,%r14\ncmp %ebx,%r15d\njge 1289 \nmov %r13,%r12\nmov (%r12,%r14,1),%ebp\ntest %ebp,%ebp\njle 128c \nmovslq %ebx,%rdi\nshl $0x2,%rdi\ncallq 10b0 \nmov %rax,%r13\ntest %ebx,%ebx\njle 1242 \nlea -0x1(%rbx),%esi\nmov $0x0,%ecx\nmov $0x0,%ebx\njmp 1231 \nmov %r13,%r12\nmov 0xc(%rsp),%r15d\nmovslq %r15d,%rdi\nshl $0x2,%rdi\ncallq 10b0 \nmov %rax,%rbp\ntest %r15d,%r15d\njle 12d3 \nlea -0x1(%r15),%edx\nadd $0x2,%rdx\nmov $0x1,%eax\njmp 12c5 \nmovl $0x0,-0x4(%rbp,%rax,4)\nadd $0x1,%rax\ncmp %rdx,%rax\nje 12d3 \ncmp %eax,%ebx\njle 12b4 \nmov (%r12,%rax,4),%ecx\nmov %ecx,-0x4(%rbp,%rax,4)\njmp 12bc \nmov %r12,%rdi\ncallq 1080 \nmov %rbp,%rax\nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmov %rax,%rbp\njmp 12db \n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_3C], edi\nmov ebp, edi\nimul ebp, edi\nlea eax, [rbp+0Ah]\nmov edi, eax\nshr edi, 1Fh\nadd edi, eax\nsar edi, 1\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov r12, rax\ntest rax, rax\njz loc_12ED\nlea ebx, [rbp+9]\nmov rdx, rax\nmov eax, 0FFFFFFFFh\nloc_11F3:\nmov [rdx], eax\nadd eax, 2\nadd rdx, 4\ncmp ebx, eax\njg short loc_11F3\nadd ebp, 9\nshr ebp, 1\nlea ebx, [rbp+1]\nmov r14d, 8\nmov r15d, 2\njmp short loc_125C\nloc_1216:\nmov edx, [r12+rsi*4]\nmovsxd rax, ebx\nmov [r13+rax*4+0], edx\nlea ebx, [rbx+1]\nloc_1225:\nadd rsi, 1\nadd ecx, 1\ncmp ecx, edi\njz short loc_1244\nloc_1230:\ncmp ebp, esi\njg short loc_1216\nmov eax, ecx\ncdq\nidiv ebp\ntest edx, edx\njz short loc_1225\njmp short loc_1216\nloc_123F:\nmov ebx, 0\nloc_1244:\nmov rdi, r12; ptr\ncall _free\nadd r15d, 1\nadd r14, 4\ncmp r15d, ebx\njge short loc_128B\nmov r12, r13\nloc_125C:\nmov ebp, [r12+r14]\ntest ebp, ebp\njle short loc_128E\nmovsxd rdi, ebx\nshl rdi, 2; size\ncall _malloc\nmov r13, rax\ntest ebx, ebx\njle short loc_123F\nmov ecx, ebp\nneg ecx\nmov edi, ebx\nsub edi, ebp\nmov esi, 0\nmov ebx, 0\njmp short loc_1230\nloc_128B:\nmov r12, r13\nloc_128E:\nmov r15d, [rsp+48h+var_3C]\nmovsxd r13, r15d\nlea rdi, ds:0[r13*4]; size\ncall _malloc\nmov rbp, rax\ntest r15d, r15d\njle short loc_12D3\nmov eax, 1\nmov ecx, 0\njmp short loc_12C7\nloc_12B7:\nmov [rbp+rax*4-4], edx\nlea rdx, [rax+1]\ncmp r13, rax\njz short loc_12D3\nmov rax, rdx\nloc_12C7:\nmov edx, ecx\ncmp ebx, eax\njle short loc_12B7\nmov edx, [r12+rax*4]\njmp short loc_12B7\nloc_12D3:\nmov rdi, r12; ptr\ncall _free\nloc_12DB:\nmov rax, rbp\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_12ED:\nmov rbp, rax\njmp short loc_12DB", + "ida_pseudo": "_DWORD *__fastcall func0(int a1)\n{\n int v1; // ebp\n _DWORD *v2; // rax\n _DWORD *v3; // r12\n int *v4; // rdx\n int v5; // eax\n signed int v6; // ebx\n __int64 v7; // r14\n int v8; // r15d\n __int64 v9; // rsi\n int v10; // ecx\n int v11; // ebp\n _DWORD *v12; // r13\n int v13; // edi\n _DWORD *v14; // rbp\n __int64 i; // rax\n int v16; // edx\n\n v1 = a1 * a1;\n v2 = malloc(4LL * ((a1 * a1 + 10) / 2));\n v3 = v2;\n if ( !v2 )\n return 0LL;\n v4 = v2;\n v5 = -1;\n do\n {\n *v4 = v5;\n v5 += 2;\n ++v4;\n }\n while ( v1 + 9 > v5 );\n v6 = ((unsigned int)(v1 + 9) >> 1) + 1;\n v7 = 2LL;\n v8 = 2;\n while ( 1 )\n {\n v11 = v3[v7];\n if ( v11 <= 0 )\n break;\n v12 = malloc(4LL * v6);\n if ( v6 <= 0 )\n {\n v6 = 0;\n }\n else\n {\n v10 = -v11;\n v13 = v6 - v11;\n v9 = 0LL;\n v6 = 0;\n do\n {\n if ( v11 > (int)v9 || v10 % v11 )\n v12[v6++] = v3[v9];\n ++v9;\n ++v10;\n }\n while ( v10 != v13 );\n }\n free(v3);\n ++v8;\n ++v7;\n if ( v8 >= v6 )\n {\n v3 = v12;\n break;\n }\n v3 = v12;\n }\n v14 = malloc(4LL * a1);\n if ( a1 > 0 )\n {\n for ( i = 1LL; ; ++i )\n {\n v16 = 0;\n if ( v6 > (int)i )\n v16 = v3[i];\n v14[i - 1] = v16;\n if ( a1 == i )\n break;\n }\n }\n free(v3);\n return v14;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_3C], edi\nmov ebp, edi\nimul ebp, edi\nlea eax, [rbp+0Ah]\nmov edi, eax\nshr edi, 1Fh\nadd edi, eax\nsar edi, 1\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov r12, rax\ntest rax, rax\njz loc_12ED\nlea ebx, [rbp+9]\nmov rdx, rax\nmov eax, 0FFFFFFFFh\nloc_11F3:\nmov [rdx], eax\nadd eax, 2\nadd rdx, 4\ncmp ebx, eax\njg short loc_11F3\nadd ebp, 9\nshr ebp, 1\nlea ebx, [rbp+1]\nmov r14d, 8\nmov r15d, 2\njmp short loc_125C\nloc_1216:\nmov edx, [r12+rsi*4]\nmovsxd rax, ebx\nmov [r13+rax*4+0], edx\nlea ebx, [rbx+1]\nloc_1225:\nadd rsi, 1\nadd ecx, 1\ncmp ecx, edi\njz short loc_1244\nloc_1230:\ncmp ebp, esi\njg short loc_1216\nmov eax, ecx\ncdq\nidiv ebp\ntest edx, edx\njz short loc_1225\njmp short loc_1216\nloc_123F:\nmov ebx, 0\nloc_1244:\nmov rdi, r12; ptr\ncall _free\nadd r15d, 1\nadd r14, 4\ncmp r15d, ebx\njge short loc_128B\nmov r12, r13\nloc_125C:\nmov ebp, [r12+r14]\ntest ebp, ebp\njle short loc_128E\nmovsxd rdi, ebx\nshl rdi, 2; size\ncall _malloc\nmov r13, rax\ntest ebx, ebx\njle short loc_123F\nmov ecx, ebp\nneg ecx\nmov edi, ebx\nsub edi, ebp\nmov esi, 0\nmov ebx, 0\njmp short loc_1230\nloc_128B:\nmov r12, r13\nloc_128E:\nmov r15d, [rsp+48h+var_3C]\nmovsxd r13, r15d\nlea rdi, ds:0[r13*4]; size\ncall _malloc\nmov rbp, rax\ntest r15d, r15d\njle short loc_12D3\nmov eax, 1\nmov ecx, 0\njmp short loc_12C7\nloc_12B7:\nmov [rbp+rax*4-4], edx\nlea rdx, [rax+1]\ncmp r13, rax\njz short loc_12D3\nmov rax, rdx\nloc_12C7:\nmov edx, ecx\ncmp ebx, eax\njle short loc_12B7\nmov edx, [r12+rax*4]\njmp short loc_12B7\nloc_12D3:\nmov rdi, r12; ptr\ncall _free\nloc_12DB:\nmov rax, rbp\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_12ED:\nmov rbp, rax\njmp short loc_12DB", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11A9(int a1)\n{\n int v1; // ebp\n _DWORD *v2; // rax\n _DWORD *v3; // r12\n int *v4; // rdx\n int v5; // eax\n signed int v6; // ebx\n __int64 v7; // r14\n int v8; // r15d\n __int64 v9; // rsi\n int v10; // ecx\n int v11; // ebp\n _DWORD *v12; // r13\n int v13; // edi\n _DWORD *v14; // rbp\n __int64 i; // rax\n int v16; // edx\n\n v1 = a1 * a1;\n v2 = malloc(4LL * ((a1 * a1 + 10) / 2));\n v3 = v2;\n if ( !v2 )\n return 0LL;\n v4 = v2;\n v5 = -1;\n do\n {\n *v4 = v5;\n v5 += 2;\n ++v4;\n }\n while ( v1 + 9 > v5 );\n v6 = ((unsigned int)(v1 + 9) >> 1) + 1;\n v7 = 2LL;\n v8 = 2;\n while ( 1 )\n {\n v11 = v3[v7];\n if ( v11 <= 0 )\n break;\n v12 = malloc(4LL * v6);\n if ( v6 <= 0 )\n {\n v6 = 0;\n }\n else\n {\n v10 = -v11;\n v13 = v6 - v11;\n v9 = 0LL;\n v6 = 0;\n do\n {\n if ( v11 > (int)v9 || v10 % v11 )\n v12[v6++] = v3[v9];\n ++v9;\n ++v10;\n }\n while ( v10 != v13 );\n }\n free(v3);\n ++v8;\n ++v7;\n if ( v8 >= v6 )\n {\n v3 = v12;\n break;\n }\n v3 = v12;\n }\n v14 = malloc(4LL * a1);\n if ( a1 > 0 )\n {\n for ( i = 1LL; ; ++i )\n {\n v16 = 0;\n if ( v6 > (int)i )\n v16 = v3[i];\n v14[i - 1] = v16;\n if ( a1 == i )\n break;\n }\n }\n free(v3);\n return v14;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11A9(int a1) {\n int v1;\n uint32_t *v2;\n uint32_t *v3;\n int *v4;\n int v5;\n signed int v6;\n long long v7;\n int v8;\n long long v9;\n int v10;\n int v11;\n uint32_t *v12;\n int v13;\n uint32_t *v14;\n long long i;\n int v16;\n v1 = a1 * a1;\n v2 = malloc(4LL * ((a1 * a1 + 10) / 2));\n v3 = v2;\n if (!v2) return 0LL;\n v4 = v2;\n v5 = -1;\n do {\n *v4 = v5;\n v5 += 2;\n ++v4;\n } while (v1 + 9 > v5);\n v6 = ((unsigned int)(v1 + 9) >> 1) + 1;\n v7 = 2LL;\n v8 = 2;\n while (1) {\n v11 = v3[v7];\n if (v11 <= 0) break;\n v12 = malloc(4LL * v6);\n if (v6 <= 0) {\n v6 = 0;\n } else {\n v10 = -v11;\n v13 = v6 - v11;\n v9 = 0LL;\n v6 = 0;\n do {\n if (v11 > (int)v9 || v10 % v11) v12[v6++] = v3[v9];\n ++v9;\n ++v10;\n } while (v10 != v13);\n }\n free(v3);\n ++v8;\n ++v7;\n if (v8 >= v6) {\n v3 = v12;\n break;\n }\n v3 = v12;\n }\n v14 = malloc(4LL * a1);\n if (a1 > 0) {\n for (i = 1LL;; ++i) {\n v16 = 0;\n if (v6 > (int)i) v16 = v3[i];\n v14[i - 1] = v16;\n if (a1 == i) break;\n }\n }\n free(v3);\n return v14;\n}", + "ida_pseudo_norm": "uint32_t *func0(int a1) {\n int v1;\n uint32_t *v2;\n uint32_t *v3;\n int *v4;\n int v5;\n signed int v6;\n long long v7;\n int v8;\n long long v9;\n int v10;\n int v11;\n uint32_t *v12;\n int v13;\n uint32_t *v14;\n long long i;\n int v16;\n v1 = a1 * a1;\n v2 = malloc(4LL * ((a1 * a1 + 10) / 2));\n v3 = v2;\n if (!v2) return 0LL;\n v4 = v2;\n v5 = -1;\n do {\n *v4 = v5;\n v5 += 2;\n ++v4;\n } while (v1 + 9 > v5);\n v6 = ((unsigned int)(v1 + 9) >> 1) + 1;\n v7 = 2LL;\n v8 = 2;\n while (1) {\n v11 = v3[v7];\n if (v11 <= 0) break;\n v12 = malloc(4LL * v6);\n if (v6 <= 0) {\n v6 = 0;\n } else {\n v10 = -v11;\n v13 = v6 - v11;\n v9 = 0LL;\n v6 = 0;\n do {\n if (v11 > (int)v9 || v10 % v11) v12[v6++] = v3[v9];\n ++v9;\n ++v10;\n } while (v10 != v13);\n }\n free(v3);\n ++v8;\n ++v7;\n if (v8 >= v6) {\n v3 = v12;\n break;\n }\n v3 = v12;\n }\n v14 = malloc(4LL * a1);\n if (a1 > 0) {\n for (i = 1LL;; ++i) {\n v16 = 0;\n if (v6 > (int)i) v16 = v3[i];\n v14[i - 1] = v16;\n if (a1 == i) break;\n }\n }\n free(v3);\n return v14;\n}" + }, + { + "index": 907, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int n) {\n int size = n * n + 9;\n int capacity = (size + 1) / 2;\n int* list = malloc(capacity * sizeof(int));\n if (!list) return NULL;\n int index = 0;\n for (int num = -1; num < size; num += 2) {\n list[index++] = num;\n }\n int current_size = index;\n int i = 2;\n while (i < current_size) {\n if (i >= current_size) break;\n int step = list[i];\n if (step <= 0) break;\n int* new_list = malloc(current_size * sizeof(int));\n int new_index = 0;\n for (int j = 0; j < current_size; j++) {\n if ((j < step) || ((j - step) % step != 0)) {\n new_list[new_index++] = list[j];\n }\n }\n free(list);\n list = new_list;\n current_size = new_index;\n i++;\n }\n int* result = malloc(n * sizeof(int));\n for (int k = 0; k < n; k++) {\n if (k + 1 < current_size) {\n result[k] = list[k + 1];\n } else {\n result[k] = 0;\n }\n }\n free(list);\n return result;\n}", + "test": "int main() {\n\n int expected1[10] = {1, 3, 7, 9, 13, 15, 21, 25, 31, 33};\n\n int expected2[5] = {1, 3, 7, 9, 13};\n\n int expected3[8] = {1, 3, 7, 9, 13, 15, 21, 25};\n\n\n\n int* result1 = func0(10);\n\n for(int i = 0; i < 10; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n free(result1);\n\n\n\n int* result2 = func0(5);\n\n for(int i = 0; i < 5; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n free(result2);\n\n\n\n int* result3 = func0(8);\n\n for(int i = 0; i < 8; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmov %edi,%eax\npush %r14\nimul %edi,%eax\npush %r13\npush %r12\npush %rbp\nlea 0x9(%rax),%r15d\npush %rbx\nsub $0x18,%rsp\nmov %edi,0xc(%rsp)\nlea 0xa(%rax),%edi\nmov %edi,%eax\nsar %eax\nmovslq %eax,%rdi\nshl $0x2,%rdi\ncallq 10b0 \ntest %rax,%rax\nje 14c3 \nmov %rax,%r14\nmov %rax,%rdx\nmov $0xffffffff,%eax\nnopw %cs:0x0(%rax,%rax,1)\nmov %eax,(%rdx)\nadd $0x2,%eax\nadd $0x4,%rdx\ncmp %eax,%r15d\njg 13c0 \nshr %r15d\nmov $0x8,%r12d\nmov $0x2,%r13d\nadd $0x1,%r15d\nnopl 0x0(%rax)\nmov (%r14,%r12,1),%ebx\ntest %ebx,%ebx\njle 1450 \nmovslq %r15d,%rdi\nxor %ebp,%ebp\nshl $0x2,%rdi\ncallq 10b0 \nxor %ecx,%ecx\nmov %rax,%rsi\nnopl 0x0(%rax,%rax,1)\ncmp %ecx,%ebx\njg 1417 \nmov %ecx,%eax\nsub %ebx,%eax\ncltd\nidiv %ebx\ntest %edx,%edx\nje 1424 \nmov (%r14,%rcx,4),%edx\nmovslq %ebp,%rax\nadd $0x1,%ebp\nmov %edx,(%rsi,%rax,4)\nadd $0x1,%rcx\ncmp %ecx,%r15d\njg 1408 \nmov %r14,%rdi\nmov %rsi,(%rsp)\nadd $0x1,%r13d\nadd $0x4,%r12\ncallq 1080 \nmov (%rsp),%rsi\ncmp %r13d,%ebp\nmov %ebp,%r15d\nmov %rsi,%r14\njg 13e8 \nmovslq 0xc(%rsp),%rdi\nmov %rdi,%rbx\nshl $0x2,%rdi\ncallq 10b0 \nmov %rax,%r12\ntest %ebx,%ebx\njle 14a9 \nmov 0xc(%rsp),%eax\nmov $0x1,%edx\nsub $0x1,%eax\nadd $0x2,%rax\njmp 1492 \nnopw 0x0(%rax,%rax,1)\nmov (%r14,%rdx,4),%ecx\nmov %ecx,-0x4(%r12,%rdx,4)\nadd $0x1,%rdx\ncmp %rdx,%rax\nje 14a9 \ncmp %edx,%r15d\njg 1480 \nmovl $0x0,-0x4(%r12,%rdx,4)\nadd $0x1,%rdx\ncmp %rdx,%rax\njne 1492 \nmov %r14,%rdi\ncallq 1080 \nadd $0x18,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nxor %r12d,%r12d\njmp 14b1 \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov eax, edi\npush r14\nimul eax, edi\npush r13\npush r12\npush rbp\npush rbx\nlea ebx, [rax+9]\nsub rsp, 18h\nmov [rsp+48h+var_3C], edi\nlea edi, [rax+0Ah]\nmov eax, edi\nsar eax, 1\nmovsxd rdi, eax\nshl rdi, 2; size\ncall _malloc\ntest rax, rax\njz loc_143C\nmov r15, rax\nmov rdx, rax\nmov eax, 0FFFFFFFFh\nnop dword ptr [rax]\nloc_1358:\nmov [rdx], eax\nadd eax, 2\nadd rdx, 4\ncmp ebx, eax\njg short loc_1358\nshr ebx, 1\nmov ebp, 8\nmov r12d, 2\nadd ebx, 1\nnop dword ptr [rax]\nloc_1378:\nmov r14d, [r15+rbp]\ntest r14d, r14d\njle short loc_13E1\nmovsxd rdi, ebx\nshl rdi, 2; size\ncall _malloc\nmov edi, ebx\nmov ecx, r14d\nxor esi, esi\nmov r13, rax\nneg ecx\nsub edi, r14d\nxor ebx, ebx\nxchg ax, ax\nloc_13A0:\ncmp r14d, esi\njg short loc_13AF\nmov eax, ecx\ncdq\nidiv r14d\ntest edx, edx\njz short loc_13BE\nloc_13AF:\nmov edx, [r15+rsi*4]\nmovsxd rax, ebx\nadd ebx, 1\nmov [r13+rax*4+0], edx\nloc_13BE:\nadd ecx, 1\nadd rsi, 1\ncmp ecx, edi\njnz short loc_13A0\nmov rdi, r15; ptr\nadd r12d, 1\nadd rbp, 4\nmov r15, r13\ncall _free\ncmp ebx, r12d\njg short loc_1378\nloc_13E1:\nmovsxd r12, [rsp+48h+var_3C]\nlea rdi, ds:0[r12*4]; size\ncall _malloc\nmov edx, 1\nmov rbp, rax\ntest r12d, r12d\njg short loc_140B\njmp short loc_1422\nloc_1408:\nmov rdx, rcx\nloc_140B:\nxor ecx, ecx\ncmp ebx, edx\njle short loc_1415\nmov ecx, [r15+rdx*4]\nloc_1415:\nmov [rbp+rdx*4-4], ecx\nlea rcx, [rdx+1]\ncmp r12, rdx\njnz short loc_1408\nloc_1422:\nmov rdi, r15; ptr\ncall _free\nloc_142A:\nadd rsp, 18h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_143C:\nxor ebp, ebp\njmp short loc_142A", + "ida_pseudo": "_DWORD *__fastcall func0(int a1)\n{\n int v1; // ebx\n _DWORD *v2; // rax\n _DWORD *v3; // r15\n int *v4; // rdx\n int v5; // eax\n __int64 v6; // rbp\n int v7; // r12d\n int v8; // ebx\n int v9; // r14d\n __int64 v10; // rsi\n _DWORD *v11; // r13\n int v12; // ecx\n int v13; // edi\n __int64 v14; // rax\n void *v15; // rdi\n _DWORD *v16; // rax\n __int64 v17; // rdx\n _DWORD *v18; // rbp\n int v19; // ecx\n\n v1 = a1 * a1 + 9;\n v2 = malloc(4LL * ((a1 * a1 + 10) >> 1));\n if ( !v2 )\n return 0LL;\n v3 = v2;\n v4 = v2;\n v5 = -1;\n do\n {\n *v4 = v5;\n v5 += 2;\n ++v4;\n }\n while ( v1 > v5 );\n v6 = 2LL;\n v7 = 2;\n v8 = ((unsigned int)v1 >> 1) + 1;\n do\n {\n v9 = v3[v6];\n if ( v9 <= 0 )\n break;\n v10 = 0LL;\n v11 = malloc(4LL * v8);\n v12 = -v9;\n v13 = v8 - v9;\n v8 = 0;\n do\n {\n if ( v9 > (int)v10 || v12 % v9 )\n {\n v14 = v8++;\n v11[v14] = v3[v10];\n }\n ++v12;\n ++v10;\n }\n while ( v12 != v13 );\n v15 = v3;\n ++v7;\n ++v6;\n v3 = v11;\n free(v15);\n }\n while ( v8 > v7 );\n v16 = malloc(4LL * a1);\n v17 = 1LL;\n v18 = v16;\n if ( a1 > 0 )\n {\n while ( 1 )\n {\n v19 = 0;\n if ( v8 > (int)v17 )\n v19 = v3[v17];\n v16[v17 - 1] = v19;\n if ( a1 == v17 )\n break;\n ++v17;\n }\n }\n free(v3);\n return v18;\n}", + "ida_strip_asm": "sub_1310:\nendbr64\npush r15\nmov eax, edi\npush r14\nimul eax, edi\npush r13\npush r12\npush rbp\npush rbx\nlea ebx, [rax+9]\nsub rsp, 18h\nmov [rsp+48h+var_3C], edi\nlea edi, [rax+0Ah]\nmov eax, edi\nsar eax, 1\nmovsxd rdi, eax\nshl rdi, 2; size\ncall _malloc\ntest rax, rax\njz loc_143C\nmov r15, rax\nmov rdx, rax\nmov eax, 0FFFFFFFFh\nnop dword ptr [rax]\nloc_1358:\nmov [rdx], eax\nadd eax, 2\nadd rdx, 4\ncmp ebx, eax\njg short loc_1358\nshr ebx, 1\nmov ebp, 8\nmov r12d, 2\nadd ebx, 1\nnop dword ptr [rax]\nloc_1378:\nmov r14d, [r15+rbp]\ntest r14d, r14d\njle short loc_13E1\nmovsxd rdi, ebx\nshl rdi, 2; size\ncall _malloc\nmov edi, ebx\nmov ecx, r14d\nxor esi, esi\nmov r13, rax\nneg ecx\nsub edi, r14d\nxor ebx, ebx\nxchg ax, ax\nloc_13A0:\ncmp r14d, esi\njg short loc_13AF\nmov eax, ecx\ncdq\nidiv r14d\ntest edx, edx\njz short loc_13BE\nloc_13AF:\nmov edx, [r15+rsi*4]\nmovsxd rax, ebx\nadd ebx, 1\nmov [r13+rax*4+0], edx\nloc_13BE:\nadd ecx, 1\nadd rsi, 1\ncmp ecx, edi\njnz short loc_13A0\nmov rdi, r15; ptr\nadd r12d, 1\nadd rbp, 4\nmov r15, r13\ncall _free\ncmp ebx, r12d\njg short loc_1378\nloc_13E1:\nmovsxd r12, [rsp+48h+var_3C]\nlea rdi, ds:0[r12*4]; size\ncall _malloc\nmov edx, 1\nmov rbp, rax\ntest r12d, r12d\njg short loc_140B\njmp short loc_1422\nloc_1408:\nmov rdx, rcx\nloc_140B:\nxor ecx, ecx\ncmp ebx, edx\njle short loc_1415\nmov ecx, [r15+rdx*4]\nloc_1415:\nmov [rbp+rdx*4-4], ecx\nlea rcx, [rdx+1]\ncmp r12, rdx\njnz short loc_1408\nloc_1422:\nmov rdi, r15; ptr\ncall _free\nloc_142A:\nadd rsp, 18h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_143C:\nxor ebp, ebp\njmp short loc_142A", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1310(int a1)\n{\n int v1; // ebx\n _DWORD *v2; // rax\n _DWORD *v3; // r15\n int *v4; // rdx\n int v5; // eax\n __int64 v6; // rbp\n int v7; // r12d\n int v8; // ebx\n int v9; // r14d\n __int64 v10; // rsi\n _DWORD *v11; // r13\n int v12; // ecx\n int v13; // edi\n __int64 v14; // rax\n void *v15; // rdi\n _DWORD *v16; // rax\n __int64 v17; // rdx\n _DWORD *v18; // rbp\n int v19; // ecx\n\n v1 = a1 * a1 + 9;\n v2 = malloc(4LL * ((a1 * a1 + 10) >> 1));\n if ( !v2 )\n return 0LL;\n v3 = v2;\n v4 = v2;\n v5 = -1;\n do\n {\n *v4 = v5;\n v5 += 2;\n ++v4;\n }\n while ( v1 > v5 );\n v6 = 2LL;\n v7 = 2;\n v8 = ((unsigned int)v1 >> 1) + 1;\n do\n {\n v9 = v3[v6];\n if ( v9 <= 0 )\n break;\n v10 = 0LL;\n v11 = malloc(4LL * v8);\n v12 = -v9;\n v13 = v8 - v9;\n v8 = 0;\n do\n {\n if ( v9 > (int)v10 || v12 % v9 )\n {\n v14 = v8++;\n v11[v14] = v3[v10];\n }\n ++v12;\n ++v10;\n }\n while ( v12 != v13 );\n v15 = v3;\n ++v7;\n ++v6;\n v3 = v11;\n free(v15);\n }\n while ( v8 > v7 );\n v16 = malloc(4LL * a1);\n v17 = 1LL;\n v18 = v16;\n if ( a1 > 0 )\n {\n while ( 1 )\n {\n v19 = 0;\n if ( v8 > (int)v17 )\n v19 = v3[v17];\n v16[v17 - 1] = v19;\n if ( a1 == v17 )\n break;\n ++v17;\n }\n }\n free(v3);\n return v18;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1310(int a1) {\n int v1;\n uint32_t *v2;\n uint32_t *v3;\n int *v4;\n int v5;\n long long v6;\n int v7;\n int v8;\n int v9;\n long long v10;\n uint32_t *v11;\n int v12;\n int v13;\n long long v14;\n void *v15;\n uint32_t *v16;\n long long v17;\n uint32_t *v18;\n int v19;\n v1 = a1 * a1 + 9;\n v2 = malloc(4LL * ((a1 * a1 + 10) >> 1));\n if (!v2) return 0LL;\n v3 = v2;\n v4 = v2;\n v5 = -1;\n do {\n *v4 = v5;\n v5 += 2;\n ++v4;\n } while (v1 > v5);\n v6 = 2LL;\n v7 = 2;\n v8 = ((unsigned int)v1 >> 1) + 1;\n do {\n v9 = v3[v6];\n if (v9 <= 0) break;\n v10 = 0LL;\n v11 = malloc(4LL * v8);\n v12 = -v9;\n v13 = v8 - v9;\n v8 = 0;\n do {\n if (v9 > (int)v10 || v12 % v9) {\n v14 = v8++;\n v11[v14] = v3[v10];\n }\n ++v12;\n ++v10;\n } while (v12 != v13);\n v15 = v3;\n ++v7;\n ++v6;\n v3 = v11;\n free(v15);\n } while (v8 > v7);\n v16 = malloc(4LL * a1);\n v17 = 1LL;\n v18 = v16;\n if (a1 > 0) {\n while (1) {\n v19 = 0;\n if (v8 > (int)v17) v19 = v3[v17];\n v16[v17 - 1] = v19;\n if (a1 == v17) break;\n ++v17;\n }\n }\n free(v3);\n return v18;\n}", + "ida_pseudo_norm": "uint32_t *func0(int a1) {\n int v1;\n uint32_t *v2;\n uint32_t *v3;\n int *v4;\n int v5;\n long long v6;\n int v7;\n int v8;\n int v9;\n long long v10;\n uint32_t *v11;\n int v12;\n int v13;\n long long v14;\n void *v15;\n uint32_t *v16;\n long long v17;\n uint32_t *v18;\n int v19;\n v1 = a1 * a1 + 9;\n v2 = malloc(4LL * ((a1 * a1 + 10) >> 1));\n if (!v2) return 0LL;\n v3 = v2;\n v4 = v2;\n v5 = -1;\n do {\n *v4 = v5;\n v5 += 2;\n ++v4;\n } while (v1 > v5);\n v6 = 2LL;\n v7 = 2;\n v8 = ((unsigned int)v1 >> 1) + 1;\n do {\n v9 = v3[v6];\n if (v9 <= 0) break;\n v10 = 0LL;\n v11 = malloc(4LL * v8);\n v12 = -v9;\n v13 = v8 - v9;\n v8 = 0;\n do {\n if (v9 > (int)v10 || v12 % v9) {\n v14 = v8++;\n v11[v14] = v3[v10];\n }\n ++v12;\n ++v10;\n } while (v12 != v13);\n v15 = v3;\n ++v7;\n ++v6;\n v3 = v11;\n free(v15);\n } while (v8 > v7);\n v16 = malloc(4LL * a1);\n v17 = 1LL;\n v18 = v16;\n if (a1 > 0) {\n while (1) {\n v19 = 0;\n if (v8 > (int)v17) v19 = v3[v17];\n v16[v17 - 1] = v19;\n if (a1 == v17) break;\n ++v17;\n }\n }\n free(v3);\n return v18;\n}" + }, + { + "index": 907, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int* func0(int n) {\n int size = n * n + 9;\n int capacity = (size + 1) / 2;\n int* list = malloc(capacity * sizeof(int));\n if (!list) return NULL;\n int index = 0;\n for (int num = -1; num < size; num += 2) {\n list[index++] = num;\n }\n int current_size = index;\n int i = 2;\n while (i < current_size) {\n if (i >= current_size) break;\n int step = list[i];\n if (step <= 0) break;\n int* new_list = malloc(current_size * sizeof(int));\n int new_index = 0;\n for (int j = 0; j < current_size; j++) {\n if ((j < step) || ((j - step) % step != 0)) {\n new_list[new_index++] = list[j];\n }\n }\n free(list);\n list = new_list;\n current_size = new_index;\n i++;\n }\n int* result = malloc(n * sizeof(int));\n for (int k = 0; k < n; k++) {\n if (k + 1 < current_size) {\n result[k] = list[k + 1];\n } else {\n result[k] = 0;\n }\n }\n free(list);\n return result;\n}", + "test": "int main() {\n\n int expected1[10] = {1, 3, 7, 9, 13, 15, 21, 25, 31, 33};\n\n int expected2[5] = {1, 3, 7, 9, 13};\n\n int expected3[8] = {1, 3, 7, 9, 13, 15, 21, 25};\n\n\n\n int* result1 = func0(10);\n\n for(int i = 0; i < 10; i++) {\n\n assert(result1[i] == expected1[i]);\n\n }\n\n free(result1);\n\n\n\n int* result2 = func0(5);\n\n for(int i = 0; i < 5; i++) {\n\n assert(result2[i] == expected2[i]);\n\n }\n\n free(result2);\n\n\n\n int* result3 = func0(8);\n\n for(int i = 0; i < 8; i++) {\n\n assert(result3[i] == expected3[i]);\n\n }\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmov %edi,%eax\npush %r14\nimul %edi,%eax\npush %r13\npush %r12\npush %rbp\nlea 0x9(%rax),%ebp\npush %rbx\nsub $0x18,%rsp\nmov %edi,0xc(%rsp)\nlea 0xa(%rax),%edi\nmov %edi,%eax\nsar %eax\nmovslq %eax,%rdi\nshl $0x2,%rdi\ncallq 10b0 \ntest %rax,%rax\nje 1680 \nmov %ebp,%ebx\nmovdqa 0xcac(%rip),%xmm0\nmovdqa 0xcc4(%rip),%xmm2\nmov %rax,%r13\nshr %ebx\nadd $0x1,%ebx\nmov %ebx,%edx\nshr $0x2,%edx\nshl $0x4,%rdx\nadd %rax,%rdx\nmovdqa %xmm0,%xmm1\nadd $0x10,%rax\npaddd %xmm2,%xmm0\nmovups %xmm1,-0x10(%rax)\ncmp %rdx,%rax\njne 1410 \nmov %ebx,%eax\nand $0xfffffffc,%eax\nlea (%rax,%rax,1),%edx\nlea -0x1(%rdx),%esi\ncmp %eax,%ebx\nje 145f \nmov %esi,0x0(%r13,%rax,4)\nlea 0x1(%rdx),%esi\nlea 0x1(%rax),%ecx\ncmp %esi,%ebp\njle 145f \nmovslq %ecx,%rax\nadd $0x3,%edx\nmov %esi,0x0(%r13,%rax,4)\nlea 0x0(,%rax,4),%rcx\ncmp %edx,%ebp\njle 145f \nmov %edx,0x4(%r13,%rcx,1)\nmov $0x8,%ebp\nmov $0x2,%r12d\nnopw 0x0(%rax,%rax,1)\nmov 0x0(%r13,%rbp,1),%r15d\ntest %r15d,%r15d\njle 15d6 \nmovslq %ebx,%rdi\nshl $0x2,%rdi\ncallq 10b0 \ncmp %r15d,%ebx\nmov %r15d,%ecx\nmovdqa 0xc38(%rip),%xmm5\nmov %rax,%r14\nlea 0xf(%rax),%rax\ncmovle %ebx,%ecx\nmovdqa 0xc36(%rip),%xmm4\nsub %r13,%rax\ncmp $0x1e,%rax\njbe 1650 \ncmp $0x5,%ecx\njle 1650 \ntest %ecx,%ecx\nmov $0x1,%edi\nmovdqa 0xbe1(%rip),%xmm2\ncmovg %ecx,%edi\nxor %eax,%eax\nmovdqa %xmm2,%xmm3\nmov %edi,%edx\nshr $0x2,%edx\nshl $0x4,%rdx\nnopl 0x0(%rax)\nmovdqu 0x0(%r13,%rax,1),%xmm6\nmovdqa %xmm2,%xmm0\nmovdqa %xmm3,%xmm1\npaddd %xmm5,%xmm2\npaddd %xmm5,%xmm3\npaddd %xmm4,%xmm1\nmovups %xmm6,(%r14,%rax,1)\nadd $0x10,%rax\npaddd %xmm4,%xmm0\ncmp %rdx,%rax\njne 14e8 \nmov %edi,%r9d\npshufd $0xff,%xmm0,%xmm0\npshufd $0xff,%xmm1,%xmm1\nand $0xfffffffc,%r9d\nmovd %xmm0,%eax\nmovd %xmm1,%edx\nand $0x3,%edi\nje 1579 \nmov %r9d,%edi\nlea 0x1(%r9),%edx\nmov 0x0(%r13,%rdi,4),%r10d\nlea 0x0(,%rdi,4),%rax\nmov %r10d,(%r14,%rdi,4)\ncmp %edx,%ecx\njle 166f \nmov 0x4(%r13,%rax,1),%edi\nlea 0x2(%r9),%edx\nmov %edi,0x4(%r14,%rax,1)\ncmp %edx,%ecx\njle 166f \nmov 0x8(%r13,%rax,1),%ecx\nlea 0x3(%r9),%edx\nmov %ecx,0x8(%r14,%rax,1)\nmov %edx,%eax\ncmp %ebx,%eax\njge 1679 \nmov %eax,%ecx\nsub %r15d,%ebx\ncltq\nmov %ebx,%r9d\nsub %r15d,%ecx\nlea 0x0(%r13,%rax,4),%rdi\nmov %edx,%ebx\nnopl (%rax)\nmov %ecx,%eax\ncltd\nidiv %r15d\ntest %edx,%edx\nje 15ae \nmov (%rdi),%edx\nmovslq %ebx,%rax\nadd $0x1,%ebx\nmov %edx,(%r14,%rax,4)\nadd $0x1,%ecx\nadd $0x4,%rdi\ncmp %r9d,%ecx\njne 1598 \nmov %r13,%rdi\nadd $0x1,%r12d\nadd $0x4,%rbp\nmov %r14,%r13\ncallq 1080 \ncmp %ebx,%r12d\njl 1470 \nmovslq 0xc(%rsp),%rdi\nmov %rdi,%r15\nshl $0x2,%rdi\ncallq 10b0 \nmov %rax,%r12\ntest %r15d,%r15d\njle 1631 \nmov 0xc(%rsp),%eax\nmov $0x1,%edx\nsub $0x1,%eax\nadd $0x2,%rax\njmp 161b \nnopl 0x0(%rax)\nmov 0x0(%r13,%rdx,4),%ecx\nmov %ecx,-0x4(%r12,%rdx,4)\nadd $0x1,%rdx\ncmp %rax,%rdx\nje 1631 \ncmp %edx,%ebx\njg 1608 \nmovl $0x0,-0x4(%r12,%rdx,4)\nadd $0x1,%rdx\ncmp %rax,%rdx\njne 161b \nmov %r13,%rdi\ncallq 1080 \nadd $0x18,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax,%rax,1)\nmov $0x1,%eax\nnopl (%rax)\nmov -0x4(%r13,%rax,4),%edi\nmov %eax,%edx\nmov %edi,-0x4(%r14,%rax,4)\nadd $0x1,%rax\nlea -0x1(%rax),%edi\ncmp %edi,%ecx\njg 1658 \nmov %edx,%eax\ncmp %ebx,%eax\njl 1581 \nmov %edx,%ebx\njmpq 15ba \nxor %r12d,%r12d\njmp 1639 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov eax, edi\npush r14\nimul eax, edi\npush r13\npush r12\npush rbp\npush rbx\nlea ebx, [rax+9]\nsub rsp, 18h\nmov [rsp+48h+var_3C], edi\nlea edi, [rax+0Ah]\nmov eax, edi\nsar eax, 1\nmovsxd rdi, eax\nshl rdi, 2; size\ncall _malloc\ntest rax, rax\njz loc_15E7\nmov r13d, ebx\nmovdqa xmm0, cs:xmmword_2080\nmovdqa xmm2, cs:xmmword_20A0\nmov r12, rax\nshr r13d, 1\nadd r13d, 1\nmov edx, r13d\nshr edx, 2\nshl rdx, 4\nadd rdx, rax\nnop dword ptr [rax+00h]\nloc_1368:\nmovdqa xmm1, xmm0\nadd rax, 10h\npaddd xmm0, xmm2\nmovups xmmword ptr [rax-10h], xmm1\ncmp rax, rdx\njnz short loc_1368\nmov edx, r13d\nand edx, 0FFFFFFFCh\nlea eax, [rdx+rdx]\nlea esi, [rax-1]\ntest r13b, 3\njz short loc_13B3\nmov [r12+rdx*4], esi\nlea rcx, ds:0[rdx*4]\nlea edx, [rax+1]\ncmp ebx, edx\njle short loc_13B3\nadd eax, 3\nmov [r12+rcx+4], edx\ncmp ebx, eax\njle short loc_13B3\nmov [r12+rcx+8], eax\nloc_13B3:\nmov ebx, 8\nmov ebp, 2\nnop dword ptr [rax]\nloc_13C0:\nmov r14d, [r12+rbx]\ntest r14d, r14d\njle loc_1485\nmovsxd rdi, r13d\nshl rdi, 2; size\ncall _malloc\ncmp r14d, r13d\nmov ecx, r13d\ncmovle ecx, r14d\nmov r15, rax\ncmp ecx, 4\njle loc_1500\nlea rax, [r12+4]\nmov rdx, r15\nsub rdx, rax\nmov eax, 1\ncmp rdx, 8\nja loc_1510\nnop dword ptr [rax+00000000h]\nloc_1410:\nmov edx, [r12+rax*4-4]\nmov [r15+rax*4-4], edx\nlea rdx, [rax+1]\ncmp ecx, eax\njg loc_14F0\nmov edx, eax\nloc_1428:\ncmp eax, r13d\njge loc_15B8\nloc_1431:\nmov ecx, eax\nmov edi, r13d\ncdqe\nmov r13d, edx\nsub ecx, r14d\nlea rsi, [r12+rax*4]\nsub edi, r14d\nnop dword ptr [rax]\nloc_1448:\nmov eax, ecx\ncdq\nidiv r14d\ntest edx, edx\njz short loc_145F\nmov edx, [rsi]\nmovsxd rax, r13d\nadd r13d, 1\nmov [r15+rax*4], edx\nloc_145F:\nadd ecx, 1\nadd rsi, 4\ncmp edi, ecx\njnz short loc_1448\nloc_146A:\nmov rdi, r12; ptr\nadd ebp, 1\nadd rbx, 4\nmov r12, r15\ncall _free\ncmp ebp, r13d\njl loc_13C0\nloc_1485:\nmovsxd rbp, [rsp+48h+var_3C]\nlea rdi, ds:0[rbp*4]; size\ncall _malloc\nmov edx, 1\nmov rbx, rax\ntest ebp, ebp\njg short loc_14BC\njmp short loc_14D2\nloc_14A8:\nmov eax, [r12+rdx*4]\nmov [rbx+rdx*4-4], eax\nlea rax, [rdx+1]\ncmp rbp, rdx\njz short loc_14D2\nloc_14B9:\nmov rdx, rax\nloc_14BC:\ncmp r13d, edx\njg short loc_14A8\nmov dword ptr [rbx+rdx*4-4], 0\nlea rax, [rdx+1]\ncmp rbp, rdx\njnz short loc_14B9\nloc_14D2:\nmov rdi, r12; ptr\ncall _free\nloc_14DA:\nadd rsp, 18h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14F0:\nmov rax, rdx\njmp loc_1410\nloc_1500:\nmov eax, 1\njmp loc_1410\nloc_1510:\nmovdqa xmm1, cs:xmmword_2090\nmov edx, ecx\nxor eax, eax\nshr edx, 2\nshl rdx, 4\nmovdqa xmm2, xmm1\nnop word ptr [rax+rax+00000000h]\nloc_1530:\nmovdqu xmm4, xmmword ptr [r12+rax]\nmovdqa xmm0, xmm1\nmovdqa xmm3, xmm2\npaddd xmm1, cs:xmmword_20B0\npaddd xmm2, cs:xmmword_20B0\nmovups xmmword ptr [r15+rax], xmm4\nadd rax, 10h\ncmp rax, rdx\njnz short loc_1530\nmov esi, ecx\nand esi, 0FFFFFFFCh\ntest cl, 3\njz short loc_15C0\nmov eax, esi\nlea edx, [rsi+1]\nmov r9d, [r12+rax*4]\nlea rdi, ds:0[rax*4]\nmov [r15+rax*4], r9d\nmov eax, edx\ncmp edx, ecx\njge loc_1428\nmov eax, [r12+rdi+4]\nlea edx, [rsi+2]\nmov [r15+rdi+4], eax\nmov eax, edx\ncmp ecx, edx\njle loc_1428\nmov eax, [r12+rdi+8]\nlea edx, [rsi+3]\nmov [r15+rdi+8], eax\nmov eax, edx\ncmp eax, r13d\njl loc_1431\nnop dword ptr [rax+00h]\nloc_15B8:\nmov r13d, edx\njmp loc_146A\nloc_15C0:\nmovdqa xmm1, cs:xmmword_20C0\npaddd xmm0, xmm1\npaddd xmm3, xmm1\npshufd xmm0, xmm0, 0FFh\nmovd eax, xmm0\npshufd xmm0, xmm3, 0FFh\nmovd edx, xmm0\njmp loc_1428\nloc_15E7:\nxor ebx, ebx\njmp loc_14DA", + "ida_pseudo": "_DWORD *__fastcall func0(int a1)\n{\n int v1; // ebx\n __m128i *v2; // rax\n __m128i si128; // xmm0\n __m128i v4; // xmm2\n __m128i *v5; // r12\n int v6; // r13d\n char *m128i_i8; // rdx\n __m128i v8; // xmm1\n __int64 v9; // rdx\n int v10; // eax\n __int64 v11; // rcx\n int v12; // edx\n int v13; // eax\n __int64 v14; // rbx\n int v15; // ebp\n int v16; // r14d\n __m128i *v17; // rax\n int v18; // ecx\n __m128i *v19; // r15\n unsigned __int64 v20; // rdx\n __int64 v21; // rax\n int v22; // edx\n int v23; // edi\n int v24; // ecx\n __int32 *v25; // rsi\n int v26; // edi\n __int64 v27; // rax\n __m128i *v28; // rdi\n _DWORD *v29; // rax\n __int64 v30; // rdx\n _DWORD *v31; // rbx\n __int64 v32; // rax\n __m128i v34; // xmm1\n unsigned __int64 v35; // rax\n __m128i v36; // xmm2\n __m128i v37; // xmm0\n __m128i v38; // xmm3\n unsigned int v39; // esi\n __int64 v40; // rdi\n __m128i v41; // xmm1\n\n v1 = a1 * a1 + 9;\n v2 = (__m128i *)malloc(4LL * ((a1 * a1 + 10) >> 1));\n if ( !v2 )\n return 0LL;\n si128 = _mm_load_si128((const __m128i *)&xmmword_2080);\n v4 = _mm_load_si128((const __m128i *)&xmmword_20A0);\n v5 = v2;\n v6 = ((unsigned int)v1 >> 1) + 1;\n m128i_i8 = v2[(unsigned int)v6 >> 2].m128i_i8;\n do\n {\n v8 = si128;\n ++v2;\n si128 = _mm_add_epi32(si128, v4);\n v2[-1] = v8;\n }\n while ( v2 != (__m128i *)m128i_i8 );\n v9 = v6 & 0xFFFFFFFC;\n v10 = 2 * v9;\n if ( (v6 & 3) != 0 )\n {\n v5->m128i_i32[v9] = 2 * v9 - 1;\n v11 = v9;\n v12 = v10 + 1;\n if ( v1 > v10 + 1 )\n {\n v13 = v10 + 3;\n v5->m128i_i32[v11 + 1] = v12;\n if ( v1 > v13 )\n v5->m128i_i32[v11 + 2] = v13;\n }\n }\n v14 = 2LL;\n v15 = 2;\n do\n {\n v16 = v5->m128i_i32[v14];\n if ( v16 <= 0 )\n break;\n v17 = (__m128i *)malloc(4LL * v6);\n v18 = v6;\n if ( v16 <= v6 )\n v18 = v16;\n v19 = v17;\n if ( v18 <= 4 )\n {\n v21 = 1LL;\nLABEL_14:\n while ( 1 )\n {\n v19->m128i_i32[v21 - 1] = v5->m128i_i32[v21 - 1];\n if ( v18 <= (int)v21 )\n break;\n ++v21;\n }\n v22 = v21;\nLABEL_16:\n if ( (int)v21 < v6 )\n goto LABEL_17;\n goto LABEL_38;\n }\n v20 = (char *)v17 - ((char *)v5->m128i_i64 + 4);\n v21 = 1LL;\n if ( v20 <= 8 )\n goto LABEL_14;\n v34 = _mm_load_si128((const __m128i *)&xmmword_2090);\n v35 = 0LL;\n v36 = v34;\n do\n {\n v37 = v34;\n v38 = v36;\n v34 = _mm_add_epi32(v34, (__m128i)xmmword_20B0);\n v36 = _mm_add_epi32(v36, (__m128i)xmmword_20B0);\n v19[v35] = _mm_loadu_si128(&v5[v35]);\n ++v35;\n }\n while ( v35 != (unsigned int)v18 >> 2 );\n v39 = v18 & 0x7FFFFFFC;\n if ( (v18 & 3) == 0 )\n {\n v41 = _mm_load_si128((const __m128i *)&xmmword_20C0);\n LODWORD(v21) = _mm_cvtsi128_si32(_mm_shuffle_epi32(_mm_add_epi32(v37, v41), 255));\n v22 = _mm_cvtsi128_si32(_mm_shuffle_epi32(_mm_add_epi32(v38, v41), 255));\n goto LABEL_16;\n }\n v22 = v39 + 1;\n v40 = v39;\n v19->m128i_i32[v40] = v5->m128i_i32[v40];\n LODWORD(v21) = v39 + 1;\n if ( (int)(v39 + 1) >= v18 )\n goto LABEL_16;\n v22 = v39 + 2;\n v19->m128i_i32[v40 + 1] = v5->m128i_i32[v40 + 1];\n LODWORD(v21) = v39 + 2;\n if ( v18 <= (int)(v39 + 2) )\n goto LABEL_16;\n v22 = v39 + 3;\n v19->m128i_i32[v40 + 2] = v5->m128i_i32[v40 + 2];\n LODWORD(v21) = v39 + 3;\n if ( (int)(v39 + 3) < v6 )\n {\nLABEL_17:\n v23 = v6;\n v6 = v22;\n v24 = v21 - v16;\n v25 = &v5->m128i_i32[(int)v21];\n v26 = v23 - v16;\n do\n {\n if ( v24 % v16 )\n {\n v27 = v6++;\n v19->m128i_i32[v27] = *v25;\n }\n ++v24;\n ++v25;\n }\n while ( v26 != v24 );\n goto LABEL_21;\n }\nLABEL_38:\n v6 = v22;\nLABEL_21:\n v28 = v5;\n ++v15;\n ++v14;\n v5 = v19;\n free(v28);\n }\n while ( v15 < v6 );\n v29 = malloc(4LL * a1);\n v30 = 1LL;\n v31 = v29;\n if ( a1 > 0 )\n {\n while ( 1 )\n {\n if ( v6 > (int)v30 )\n {\n v31[v30 - 1] = v5->m128i_i32[v30];\n v32 = v30 + 1;\n if ( a1 == v30 )\n break;\n }\n else\n {\n v31[v30 - 1] = 0;\n v32 = v30 + 1;\n if ( a1 == v30 )\n break;\n }\n v30 = v32;\n }\n }\n free(v5);\n return v31;\n}", + "ida_strip_asm": "sub_1300:\nendbr64\npush r15\nmov eax, edi\npush r14\nimul eax, edi\npush r13\npush r12\npush rbp\npush rbx\nlea ebx, [rax+9]\nsub rsp, 18h\nmov [rsp+48h+var_3C], edi\nlea edi, [rax+0Ah]\nmov eax, edi\nsar eax, 1\nmovsxd rdi, eax\nshl rdi, 2; size\ncall _malloc\ntest rax, rax\njz loc_15E7\nmov r13d, ebx\nmovdqa xmm0, cs:xmmword_2080\nmovdqa xmm2, cs:xmmword_20A0\nmov r12, rax\nshr r13d, 1\nadd r13d, 1\nmov edx, r13d\nshr edx, 2\nshl rdx, 4\nadd rdx, rax\nnop dword ptr [rax+00h]\nloc_1368:\nmovdqa xmm1, xmm0\nadd rax, 10h\npaddd xmm0, xmm2\nmovups xmmword ptr [rax-10h], xmm1\ncmp rax, rdx\njnz short loc_1368\nmov edx, r13d\nand edx, 0FFFFFFFCh\nlea eax, [rdx+rdx]\nlea esi, [rax-1]\ntest r13b, 3\njz short loc_13B3\nmov [r12+rdx*4], esi\nlea rcx, ds:0[rdx*4]\nlea edx, [rax+1]\ncmp ebx, edx\njle short loc_13B3\nadd eax, 3\nmov [r12+rcx+4], edx\ncmp ebx, eax\njle short loc_13B3\nmov [r12+rcx+8], eax\nloc_13B3:\nmov ebx, 8\nmov ebp, 2\nnop dword ptr [rax]\nloc_13C0:\nmov r14d, [r12+rbx]\ntest r14d, r14d\njle loc_1485\nmovsxd rdi, r13d\nshl rdi, 2; size\ncall _malloc\ncmp r14d, r13d\nmov ecx, r13d\ncmovle ecx, r14d\nmov r15, rax\ncmp ecx, 4\njle loc_1500\nlea rax, [r12+4]\nmov rdx, r15\nsub rdx, rax\nmov eax, 1\ncmp rdx, 8\nja loc_1510\nnop dword ptr [rax+00000000h]\nloc_1410:\nmov edx, [r12+rax*4-4]\nmov [r15+rax*4-4], edx\nlea rdx, [rax+1]\ncmp ecx, eax\njg loc_14F0\nmov edx, eax\nloc_1428:\ncmp eax, r13d\njge loc_15B8\nloc_1431:\nmov ecx, eax\nmov edi, r13d\ncdqe\nmov r13d, edx\nsub ecx, r14d\nlea rsi, [r12+rax*4]\nsub edi, r14d\nnop dword ptr [rax]\nloc_1448:\nmov eax, ecx\ncdq\nidiv r14d\ntest edx, edx\njz short loc_145F\nmov edx, [rsi]\nmovsxd rax, r13d\nadd r13d, 1\nmov [r15+rax*4], edx\nloc_145F:\nadd ecx, 1\nadd rsi, 4\ncmp edi, ecx\njnz short loc_1448\nloc_146A:\nmov rdi, r12; ptr\nadd ebp, 1\nadd rbx, 4\nmov r12, r15\ncall _free\ncmp ebp, r13d\njl loc_13C0\nloc_1485:\nmovsxd rbp, [rsp+48h+var_3C]\nlea rdi, ds:0[rbp*4]; size\ncall _malloc\nmov edx, 1\nmov rbx, rax\ntest ebp, ebp\njg short loc_14BC\njmp short loc_14D2\nloc_14A8:\nmov eax, [r12+rdx*4]\nmov [rbx+rdx*4-4], eax\nlea rax, [rdx+1]\ncmp rbp, rdx\njz short loc_14D2\nloc_14B9:\nmov rdx, rax\nloc_14BC:\ncmp r13d, edx\njg short loc_14A8\nmov dword ptr [rbx+rdx*4-4], 0\nlea rax, [rdx+1]\ncmp rbp, rdx\njnz short loc_14B9\nloc_14D2:\nmov rdi, r12; ptr\ncall _free\nloc_14DA:\nadd rsp, 18h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14F0:\nmov rax, rdx\njmp loc_1410\nloc_1500:\nmov eax, 1\njmp loc_1410\nloc_1510:\nmovdqa xmm1, cs:xmmword_2090\nmov edx, ecx\nxor eax, eax\nshr edx, 2\nshl rdx, 4\nmovdqa xmm2, xmm1\nnop word ptr [rax+rax+00000000h]\nloc_1530:\nmovdqu xmm4, xmmword ptr [r12+rax]\nmovdqa xmm0, xmm1\nmovdqa xmm3, xmm2\npaddd xmm1, cs:xmmword_20B0\npaddd xmm2, cs:xmmword_20B0\nmovups xmmword ptr [r15+rax], xmm4\nadd rax, 10h\ncmp rax, rdx\njnz short loc_1530\nmov esi, ecx\nand esi, 0FFFFFFFCh\ntest cl, 3\njz short loc_15C0\nmov eax, esi\nlea edx, [rsi+1]\nmov r9d, [r12+rax*4]\nlea rdi, ds:0[rax*4]\nmov [r15+rax*4], r9d\nmov eax, edx\ncmp edx, ecx\njge loc_1428\nmov eax, [r12+rdi+4]\nlea edx, [rsi+2]\nmov [r15+rdi+4], eax\nmov eax, edx\ncmp ecx, edx\njle loc_1428\nmov eax, [r12+rdi+8]\nlea edx, [rsi+3]\nmov [r15+rdi+8], eax\nmov eax, edx\ncmp eax, r13d\njl loc_1431\nnop dword ptr [rax+00h]\nloc_15B8:\nmov r13d, edx\njmp loc_146A\nloc_15C0:\nmovdqa xmm1, cs:xmmword_20C0\npaddd xmm0, xmm1\npaddd xmm3, xmm1\npshufd xmm0, xmm0, 0FFh\nmovd eax, xmm0\npshufd xmm0, xmm3, 0FFh\nmovd edx, xmm0\njmp loc_1428\nloc_15E7:\nxor ebx, ebx\njmp loc_14DA", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1300(int a1)\n{\n int v1; // ebx\n __m128i *v2; // rax\n __m128i si128; // xmm0\n __m128i v4; // xmm2\n __m128i *v5; // r12\n int v6; // r13d\n char *m128i_i8; // rdx\n __m128i v8; // xmm1\n __int64 v9; // rdx\n int v10; // eax\n __int64 v11; // rcx\n int v12; // edx\n int v13; // eax\n __int64 v14; // rbx\n int v15; // ebp\n int v16; // r14d\n __m128i *v17; // rax\n int v18; // ecx\n __m128i *v19; // r15\n unsigned __int64 v20; // rdx\n __int64 v21; // rax\n int v22; // edx\n int v23; // edi\n int v24; // ecx\n __int32 *v25; // rsi\n int v26; // edi\n __int64 v27; // rax\n __m128i *v28; // rdi\n _DWORD *v29; // rax\n __int64 v30; // rdx\n _DWORD *v31; // rbx\n __int64 v32; // rax\n __m128i v34; // xmm1\n unsigned __int64 v35; // rax\n __m128i v36; // xmm2\n __m128i v37; // xmm0\n __m128i v38; // xmm3\n unsigned int v39; // esi\n __int64 v40; // rdi\n __m128i v41; // xmm1\n\n v1 = a1 * a1 + 9;\n v2 = (__m128i *)malloc(4LL * ((a1 * a1 + 10) >> 1));\n if ( !v2 )\n return 0LL;\n si128 = _mm_load_si128((const __m128i *)&xmmword_2080);\n v4 = _mm_load_si128((const __m128i *)&xmmword_20A0);\n v5 = v2;\n v6 = ((unsigned int)v1 >> 1) + 1;\n m128i_i8 = v2[(unsigned int)v6 >> 2].m128i_i8;\n do\n {\n v8 = si128;\n ++v2;\n si128 = _mm_add_epi32(si128, v4);\n v2[-1] = v8;\n }\n while ( v2 != (__m128i *)m128i_i8 );\n v9 = v6 & 0xFFFFFFFC;\n v10 = 2 * v9;\n if ( (v6 & 3) != 0 )\n {\n v5->m128i_i32[v9] = 2 * v9 - 1;\n v11 = v9;\n v12 = v10 + 1;\n if ( v1 > v10 + 1 )\n {\n v13 = v10 + 3;\n v5->m128i_i32[v11 + 1] = v12;\n if ( v1 > v13 )\n v5->m128i_i32[v11 + 2] = v13;\n }\n }\n v14 = 2LL;\n v15 = 2;\n do\n {\n v16 = v5->m128i_i32[v14];\n if ( v16 <= 0 )\n break;\n v17 = (__m128i *)malloc(4LL * v6);\n v18 = v6;\n if ( v16 <= v6 )\n v18 = v16;\n v19 = v17;\n if ( v18 <= 4 )\n {\n v21 = 1LL;\nLABEL_14:\n while ( 1 )\n {\n v19->m128i_i32[v21 - 1] = v5->m128i_i32[v21 - 1];\n if ( v18 <= (int)v21 )\n break;\n ++v21;\n }\n v22 = v21;\nLABEL_16:\n if ( (int)v21 < v6 )\n goto LABEL_17;\n goto LABEL_38;\n }\n v20 = (char *)v17 - ((char *)v5->m128i_i64 + 4);\n v21 = 1LL;\n if ( v20 <= 8 )\n goto LABEL_14;\n v34 = _mm_load_si128((const __m128i *)&xmmword_2090);\n v35 = 0LL;\n v36 = v34;\n do\n {\n v37 = v34;\n v38 = v36;\n v34 = _mm_add_epi32(v34, (__m128i)xmmword_20B0);\n v36 = _mm_add_epi32(v36, (__m128i)xmmword_20B0);\n v19[v35] = _mm_loadu_si128(&v5[v35]);\n ++v35;\n }\n while ( v35 != (unsigned int)v18 >> 2 );\n v39 = v18 & 0x7FFFFFFC;\n if ( (v18 & 3) == 0 )\n {\n v41 = _mm_load_si128((const __m128i *)&xmmword_20C0);\n LODWORD(v21) = _mm_cvtsi128_si32(_mm_shuffle_epi32(_mm_add_epi32(v37, v41), 255));\n v22 = _mm_cvtsi128_si32(_mm_shuffle_epi32(_mm_add_epi32(v38, v41), 255));\n goto LABEL_16;\n }\n v22 = v39 + 1;\n v40 = v39;\n v19->m128i_i32[v40] = v5->m128i_i32[v40];\n LODWORD(v21) = v39 + 1;\n if ( (int)(v39 + 1) >= v18 )\n goto LABEL_16;\n v22 = v39 + 2;\n v19->m128i_i32[v40 + 1] = v5->m128i_i32[v40 + 1];\n LODWORD(v21) = v39 + 2;\n if ( v18 <= (int)(v39 + 2) )\n goto LABEL_16;\n v22 = v39 + 3;\n v19->m128i_i32[v40 + 2] = v5->m128i_i32[v40 + 2];\n LODWORD(v21) = v39 + 3;\n if ( (int)(v39 + 3) < v6 )\n {\nLABEL_17:\n v23 = v6;\n v6 = v22;\n v24 = v21 - v16;\n v25 = &v5->m128i_i32[(int)v21];\n v26 = v23 - v16;\n do\n {\n if ( v24 % v16 )\n {\n v27 = v6++;\n v19->m128i_i32[v27] = *v25;\n }\n ++v24;\n ++v25;\n }\n while ( v26 != v24 );\n goto LABEL_21;\n }\nLABEL_38:\n v6 = v22;\nLABEL_21:\n v28 = v5;\n ++v15;\n ++v14;\n v5 = v19;\n free(v28);\n }\n while ( v15 < v6 );\n v29 = malloc(4LL * a1);\n v30 = 1LL;\n v31 = v29;\n if ( a1 > 0 )\n {\n while ( 1 )\n {\n if ( v6 > (int)v30 )\n {\n v31[v30 - 1] = v5->m128i_i32[v30];\n v32 = v30 + 1;\n if ( a1 == v30 )\n break;\n }\n else\n {\n v31[v30 - 1] = 0;\n v32 = v30 + 1;\n if ( a1 == v30 )\n break;\n }\n v30 = v32;\n }\n }\n free(v5);\n return v31;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1300(int a1) {\n int v1;\n __m128i *v2;\n __m128i si128;\n __m128i v4;\n __m128i *v5;\n int v6;\n char *m128i_i8;\n __m128i v8;\n long long v9;\n int v10;\n long long v11;\n int v12;\n int v13;\n long long v14;\n int v15;\n int v16;\n __m128i *v17;\n int v18;\n __m128i *v19;\n unsigned long long v20;\n long long v21;\n int v22;\n int v23;\n int v24;\n int *v25;\n int v26;\n long long v27;\n __m128i *v28;\n uint32_t *v29;\n long long v30;\n uint32_t *v31;\n long long v32;\n __m128i v34;\n unsigned long long v35;\n __m128i v36;\n __m128i v37;\n __m128i v38;\n unsigned int v39;\n long long v40;\n __m128i v41;\n v1 = a1 * a1 + 9;\n v2 = (__m128i *)malloc(4LL * ((a1 * a1 + 10) >> 1));\n if (!v2) return 0LL;\n si128 = _mm_load_si128((const __m128i *)&xmmword_2080);\n v4 = _mm_load_si128((const __m128i *)&xmmword_20A0);\n v5 = v2;\n v6 = ((unsigned int)v1 >> 1) + 1;\n m128i_i8 = v2[(unsigned int)v6 >> 2].m128i_i8;\n do {\n v8 = si128;\n ++v2;\n si128 = _mm_add_epi32(si128, v4);\n v2[-1] = v8;\n } while (v2 != (__m128i *)m128i_i8);\n v9 = v6 & 4294967292;\n v10 = 2 * v9;\n if ((v6 & 3) != 0) {\n v5->m128i_i32[v9] = 2 * v9 - 1;\n v11 = v9;\n v12 = v10 + 1;\n if (v1 > v10 + 1) {\n v13 = v10 + 3;\n v5->m128i_i32[v11 + 1] = v12;\n if (v1 > v13) v5->m128i_i32[v11 + 2] = v13;\n }\n }\n v14 = 2LL;\n v15 = 2;\n do {\n v16 = v5->m128i_i32[v14];\n if (v16 <= 0) break;\n v17 = (__m128i *)malloc(4LL * v6);\n v18 = v6;\n if (v16 <= v6) v18 = v16;\n v19 = v17;\n if (v18 <= 4) {\n v21 = 1LL;\n LABEL_14:\n while (1) {\n v19->m128i_i32[v21 - 1] = v5->m128i_i32[v21 - 1];\n if (v18 <= (int)v21) break;\n ++v21;\n }\n v22 = v21;\n LABEL_16:\n if ((int)v21 < v6) goto LABEL_17;\n goto LABEL_38;\n }\n v20 = (char *)v17 - ((char *)v5->m128i_i64 + 4);\n v21 = 1LL;\n if (v20 <= 8) goto LABEL_14;\n v34 = _mm_load_si128((const __m128i *)&xmmword_2090);\n v35 = 0LL;\n v36 = v34;\n do {\n v37 = v34;\n v38 = v36;\n v34 = _mm_add_epi32(v34, (__m128i)xmmword_20B0);\n v36 = _mm_add_epi32(v36, (__m128i)xmmword_20B0);\n v19[v35] = _mm_loadu_si128(&v5[v35]);\n ++v35;\n } while (v35 != (unsigned int)v18 >> 2);\n v39 = v18 & 2147483644;\n if ((v18 & 3) == 0) {\n v41 = _mm_load_si128((const __m128i *)&xmmword_20C0);\n LODWORD(v21) =\n _mm_cvtsi128_si32(_mm_shuffle_epi32(_mm_add_epi32(v37, v41), 255));\n v22 = _mm_cvtsi128_si32(_mm_shuffle_epi32(_mm_add_epi32(v38, v41), 255));\n goto LABEL_16;\n }\n v22 = v39 + 1;\n v40 = v39;\n v19->m128i_i32[v40] = v5->m128i_i32[v40];\n LODWORD(v21) = v39 + 1;\n if ((int)(v39 + 1) >= v18) goto LABEL_16;\n v22 = v39 + 2;\n v19->m128i_i32[v40 + 1] = v5->m128i_i32[v40 + 1];\n LODWORD(v21) = v39 + 2;\n if (v18 <= (int)(v39 + 2)) goto LABEL_16;\n v22 = v39 + 3;\n v19->m128i_i32[v40 + 2] = v5->m128i_i32[v40 + 2];\n LODWORD(v21) = v39 + 3;\n if ((int)(v39 + 3) < v6) {\n LABEL_17:\n v23 = v6;\n v6 = v22;\n v24 = v21 - v16;\n v25 = &v5->m128i_i32[(int)v21];\n v26 = v23 - v16;\n do {\n if (v24 % v16) {\n v27 = v6++;\n v19->m128i_i32[v27] = *v25;\n }\n ++v24;\n ++v25;\n } while (v26 != v24);\n goto LABEL_21;\n }\n LABEL_38:\n v6 = v22;\n LABEL_21:\n v28 = v5;\n ++v15;\n ++v14;\n v5 = v19;\n free(v28);\n } while (v15 < v6);\n v29 = malloc(4LL * a1);\n v30 = 1LL;\n v31 = v29;\n if (a1 > 0) {\n while (1) {\n if (v6 > (int)v30) {\n v31[v30 - 1] = v5->m128i_i32[v30];\n v32 = v30 + 1;\n if (a1 == v30) break;\n } else {\n v31[v30 - 1] = 0;\n v32 = v30 + 1;\n if (a1 == v30) break;\n }\n v30 = v32;\n }\n }\n free(v5);\n return v31;\n}", + "ida_pseudo_norm": "uint32_t *func0(int a1) {\n int v1;\n __m128i *v2;\n __m128i si128;\n __m128i v4;\n __m128i *v5;\n int v6;\n char *m128i_i8;\n __m128i v8;\n long long v9;\n int v10;\n long long v11;\n int v12;\n int v13;\n long long v14;\n int v15;\n int v16;\n __m128i *v17;\n int v18;\n __m128i *v19;\n unsigned long long v20;\n long long v21;\n int v22;\n int v23;\n int v24;\n int *v25;\n int v26;\n long long v27;\n __m128i *v28;\n uint32_t *v29;\n long long v30;\n uint32_t *v31;\n long long v32;\n __m128i v34;\n unsigned long long v35;\n __m128i v36;\n __m128i v37;\n __m128i v38;\n unsigned int v39;\n long long v40;\n __m128i v41;\n v1 = a1 * a1 + 9;\n v2 = (__m128i *)malloc(4LL * ((a1 * a1 + 10) >> 1));\n if (!v2) return 0LL;\n si128 = _mm_load_si128((const __m128i *)&xmmword_2080);\n v4 = _mm_load_si128((const __m128i *)&xmmword_20A0);\n v5 = v2;\n v6 = ((unsigned int)v1 >> 1) + 1;\n m128i_i8 = v2[(unsigned int)v6 >> 2].m128i_i8;\n do {\n v8 = si128;\n ++v2;\n si128 = _mm_add_epi32(si128, v4);\n v2[-1] = v8;\n } while (v2 != (__m128i *)m128i_i8);\n v9 = v6 & 4294967292;\n v10 = 2 * v9;\n if ((v6 & 3) != 0) {\n v5->m128i_i32[v9] = 2 * v9 - 1;\n v11 = v9;\n v12 = v10 + 1;\n if (v1 > v10 + 1) {\n v13 = v10 + 3;\n v5->m128i_i32[v11 + 1] = v12;\n if (v1 > v13) v5->m128i_i32[v11 + 2] = v13;\n }\n }\n v14 = 2LL;\n v15 = 2;\n do {\n v16 = v5->m128i_i32[v14];\n if (v16 <= 0) break;\n v17 = (__m128i *)malloc(4LL * v6);\n v18 = v6;\n if (v16 <= v6) v18 = v16;\n v19 = v17;\n if (v18 <= 4) {\n v21 = 1LL;\n LABEL_14:\n while (1) {\n v19->m128i_i32[v21 - 1] = v5->m128i_i32[v21 - 1];\n if (v18 <= (int)v21) break;\n ++v21;\n }\n v22 = v21;\n LABEL_16:\n if ((int)v21 < v6) goto LABEL_17;\n goto LABEL_38;\n }\n v20 = (char *)v17 - ((char *)v5->m128i_i64 + 4);\n v21 = 1LL;\n if (v20 <= 8) goto LABEL_14;\n v34 = _mm_load_si128((const __m128i *)&xmmword_2090);\n v35 = 0LL;\n v36 = v34;\n do {\n v37 = v34;\n v38 = v36;\n v34 = _mm_add_epi32(v34, (__m128i)xmmword_20B0);\n v36 = _mm_add_epi32(v36, (__m128i)xmmword_20B0);\n v19[v35] = _mm_loadu_si128(&v5[v35]);\n ++v35;\n } while (v35 != (unsigned int)v18 >> 2);\n v39 = v18 & 2147483644;\n if ((v18 & 3) == 0) {\n v41 = _mm_load_si128((const __m128i *)&xmmword_20C0);\n LODWORD(v21) =\n _mm_cvtsi128_si32(_mm_shuffle_epi32(_mm_add_epi32(v37, v41), 255));\n v22 = _mm_cvtsi128_si32(_mm_shuffle_epi32(_mm_add_epi32(v38, v41), 255));\n goto LABEL_16;\n }\n v22 = v39 + 1;\n v40 = v39;\n v19->m128i_i32[v40] = v5->m128i_i32[v40];\n LODWORD(v21) = v39 + 1;\n if ((int)(v39 + 1) >= v18) goto LABEL_16;\n v22 = v39 + 2;\n v19->m128i_i32[v40 + 1] = v5->m128i_i32[v40 + 1];\n LODWORD(v21) = v39 + 2;\n if (v18 <= (int)(v39 + 2)) goto LABEL_16;\n v22 = v39 + 3;\n v19->m128i_i32[v40 + 2] = v5->m128i_i32[v40 + 2];\n LODWORD(v21) = v39 + 3;\n if ((int)(v39 + 3) < v6) {\n LABEL_17:\n v23 = v6;\n v6 = v22;\n v24 = v21 - v16;\n v25 = &v5->m128i_i32[(int)v21];\n v26 = v23 - v16;\n do {\n if (v24 % v16) {\n v27 = v6++;\n v19->m128i_i32[v27] = *v25;\n }\n ++v24;\n ++v25;\n } while (v26 != v24);\n goto LABEL_21;\n }\n LABEL_38:\n v6 = v22;\n LABEL_21:\n v28 = v5;\n ++v15;\n ++v14;\n v5 = v19;\n free(v28);\n } while (v15 < v6);\n v29 = malloc(4LL * a1);\n v30 = 1LL;\n v31 = v29;\n if (a1 > 0) {\n while (1) {\n if (v6 > (int)v30) {\n v31[v30 - 1] = v5->m128i_i32[v30];\n v32 = v30 + 1;\n if (a1 == v30) break;\n } else {\n v31[v30 - 1] = 0;\n v32 = v30 + 1;\n if (a1 == v30) break;\n }\n v30 = v32;\n }\n }\n free(v5);\n return v31;\n}" + }, + { + "index": 908, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n for (int i = 0; i < n; i++) {\n if (arr[i] == i) {\n return i;\n }\n }\n return -1;\n}", + "test": "int main() {\n\n int arr1[] = {-10, -1, 0, 3, 10, 11, 30, 50, 100};\n\n int arr2[] = {1, 2, 3, 4, 5, 6, 7, 8};\n\n int arr3[] = {0, 2, 5, 8, 17};\n\n \n\n assert(func0(arr1, 9) == 3);\n\n assert(func0(arr2, 8) == -1);\n\n assert(func0(arr3, 5) == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11a5 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x4(%rbp)\njne 11a1 \nmov -0x4(%rbp),%eax\njmp 11b2 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1181 \nmov $0xffffffff,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 0\njmp short loc_11A5\nloc_1181:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_4], eax\njnz short loc_11A1\nmov eax, [rbp+var_4]\njmp short loc_11B2\nloc_11A1:\nadd [rbp+var_4], 1\nloc_11A5:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1181\nmov eax, 0FFFFFFFFh\nloc_11B2:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int i; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; (int)i < a2; ++i )\n {\n if ( i == *(_DWORD *)(4LL * (int)i + a1) )\n return i;\n }\n return 0xFFFFFFFFLL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_4], 0\njmp short loc_11A5\nloc_1181:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_4], eax\njnz short loc_11A1\nmov eax, [rbp+var_4]\njmp short loc_11B2\nloc_11A1:\nadd [rbp+var_4], 1\nloc_11A5:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1181\nmov eax, 0FFFFFFFFh\nloc_11B2:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned int i; // [rsp+18h] [rbp-4h]\n\n for ( i = 0; (int)i < a2; ++i )\n {\n if ( i == *(_DWORD *)(4LL * (int)i + a1) )\n return i;\n }\n return 0xFFFFFFFFLL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n unsigned int i;\n for (i = 0; (int)i < a2; ++i) {\n if (i == *(uint32_t *)(4LL * (int)i + a1)) return i;\n }\n return 4294967295LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int i;\n for (i = 0; (int)i < a2; ++i) {\n if (i == *(uint32_t *)(4LL * (int)i + a1)) return i;\n }\n return 4294967295LL;\n}" + }, + { + "index": 908, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int arr[], int n) {\n for (int i = 0; i < n; i++) {\n if (arr[i] == i) {\n return i;\n }\n }\n return -1;\n}", + "test": "int main() {\n\n int arr1[] = {-10, -1, 0, 3, 10, 11, 30, 50, 100};\n\n int arr2[] = {1, 2, 3, 4, 5, 6, 7, 8};\n\n int arr3[] = {0, 2, 5, 8, 17};\n\n \n\n assert(func0(arr1, 9) == 3);\n\n assert(func0(arr2, 8) == -1);\n\n assert(func0(arr3, 5) == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1196 \nlea -0x1(%rsi),%ecx\nmov $0x0,%eax\njmp 117e \nmov %rdx,%rax\nmov %eax,%edx\ncmp %eax,(%rdi,%rax,4)\nje 1193 \nlea 0x1(%rax),%rdx\ncmp %rcx,%rax\njne 117b \nmov $0xffffffff,%edx\nmov %edx,%eax\nretq\nmov $0xffffffff,%edx\njmp 1193 \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_118D\nmovsxd rsi, esi\nmov eax, 0\nloc_1179:\ncmp [rdi+rax*4], eax\njz short locret_1192\nadd rax, 1\ncmp rax, rsi\njnz short loc_1179\nmov eax, 0FFFFFFFFh\nretn\nloc_118D:\nmov eax, 0FFFFFFFFh\nlocret_1192:\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n __int64 result; // rax\n\n if ( a2 <= 0 )\n return 0xFFFFFFFFLL;\n result = 0LL;\n while ( *(_DWORD *)(a1 + 4 * result) != (_DWORD)result )\n {\n if ( ++result == a2 )\n return 0xFFFFFFFFLL;\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_118D\nmovsxd rsi, esi\nmov eax, 0\nloc_1179:\ncmp [rdi+rax*4], eax\njz short locret_1192\nadd rax, 1\ncmp rax, rsi\njnz short loc_1179\nmov eax, 0FFFFFFFFh\nretn\nloc_118D:\nmov eax, 0FFFFFFFFh\nlocret_1192:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n __int64 result; // rax\n\n if ( a2 <= 0 )\n return 0xFFFFFFFFLL;\n result = 0LL;\n while ( *(_DWORD *)(a1 + 4 * result) != (_DWORD)result )\n {\n if ( ++result == a2 )\n return 0xFFFFFFFFLL;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n long long result;\n if (a2 <= 0) return 4294967295LL;\n result = 0LL;\n while (*(uint32_t *)(a1 + 4 * result) != (uint32_t)result) {\n if (++result == a2) return 4294967295LL;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n long long result;\n if (a2 <= 0) return 4294967295LL;\n result = 0LL;\n while (*(uint32_t *)(a1 + 4 * result) != (uint32_t)result) {\n if (++result == a2) return 4294967295LL;\n }\n return result;\n}" + }, + { + "index": 909, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int num) {\n char num_str[12], rev_str[12];\n for (int x = num - 1; x > 0; x--) {\n sprintf(num_str, \"%d\", x);\n strcpy(rev_str, num_str);\n int len = strlen(rev_str);\n char temp;\n for (int i = 0; i < len / 2; i++) {\n temp = rev_str[i];\n rev_str[i] = rev_str[len - 1 - i];\n rev_str[len - 1 - i] = temp;\n }\n if (strcmp(num_str, rev_str) == 0) {\n return x;\n }\n }\n return 0;\n}", + "test": "int main() {\n\n assert(func0(99) == 88);\n\n assert(func0(1221) == 1111);\n\n assert(func0(120) == 111);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x40,%rsp\nmov %edi,-0x34(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmov -0x34(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0x2c(%rbp)\njmpq 12c9 \nmov -0x2c(%rbp),%edx\nlea -0x20(%rbp),%rax\nlea 0xde5(%rip),%rsi\nmov %rax,%rdi\nmov $0x0,%eax\ncallq 10f0 \nlea -0x20(%rbp),%rdx\nlea -0x14(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10a0 \nlea -0x14(%rbp),%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %eax,-0x24(%rbp)\nmovl $0x0,-0x28(%rbp)\njmp 1298 \nmov -0x28(%rbp),%eax\ncltq\nmovzbl -0x14(%rbp,%rax,1),%eax\nmov %al,-0x2d(%rbp)\nmov -0x24(%rbp),%eax\nsub $0x1,%eax\nsub -0x28(%rbp),%eax\ncltq\nmovzbl -0x14(%rbp,%rax,1),%edx\nmov -0x28(%rbp),%eax\ncltq\nmov %dl,-0x14(%rbp,%rax,1)\nmov -0x24(%rbp),%eax\nsub $0x1,%eax\nsub -0x28(%rbp),%eax\ncltq\nmovzbl -0x2d(%rbp),%edx\nmov %dl,-0x14(%rbp,%rax,1)\naddl $0x1,-0x28(%rbp)\nmov -0x24(%rbp),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\ncmp %eax,-0x28(%rbp)\njl 125b \nlea -0x14(%rbp),%rdx\nlea -0x20(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10e0 \ntest %eax,%eax\njne 12c5 \nmov -0x2c(%rbp),%eax\njmp 12d8 \nsubl $0x1,-0x2c(%rbp)\ncmpl $0x0,-0x2c(%rbp)\njg 1215 \nmov $0x0,%eax\nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 12ec \ncallq 10c0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_34], edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov eax, [rbp+var_34]\nsub eax, 1\nmov [rbp+var_2C], eax\njmp loc_12CC\nloc_1215:\nmov edx, [rbp+var_2C]\nlea rax, [rbp+s]\nlea rcx, format; \"%d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rdx, [rbp+s]\nlea rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\nlea rax, [rbp+dest]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_24], eax\nmov [rbp+var_28], 0\njmp short loc_129B\nloc_125E:\nmov eax, [rbp+var_28]\ncdqe\nmovzx eax, [rbp+rax+dest]\nmov [rbp+var_2D], al\nmov eax, [rbp+var_24]\nsub eax, 1\nsub eax, [rbp+var_28]\ncdqe\nmovzx edx, [rbp+rax+dest]\nmov eax, [rbp+var_28]\ncdqe\nmov [rbp+rax+dest], dl\nmov eax, [rbp+var_24]\nsub eax, 1\nsub eax, [rbp+var_28]\ncdqe\nmovzx edx, [rbp+var_2D]\nmov [rbp+rax+dest], dl\nadd [rbp+var_28], 1\nloc_129B:\nmov eax, [rbp+var_24]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\ncmp [rbp+var_28], eax\njl short loc_125E\nlea rdx, [rbp+dest]\nlea rax, [rbp+s]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_12C8\nmov eax, [rbp+var_2C]\njmp short loc_12DB\nloc_12C8:\nsub [rbp+var_2C], 1\nloc_12CC:\ncmp [rbp+var_2C], 0\njg loc_1215\nmov eax, 0\nloc_12DB:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12EF\ncall ___stack_chk_fail\nlocret_12EF:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n char v2; // [rsp+13h] [rbp-2Dh]\n int i; // [rsp+14h] [rbp-2Ch]\n int j; // [rsp+18h] [rbp-28h]\n int v5; // [rsp+1Ch] [rbp-24h]\n char s[12]; // [rsp+20h] [rbp-20h] BYREF\n char dest[12]; // [rsp+2Ch] [rbp-14h] BYREF\n unsigned __int64 v8; // [rsp+38h] [rbp-8h]\n\n v8 = __readfsqword(0x28u);\n for ( i = a1 - 1; i > 0; --i )\n {\n sprintf(s, \"%d\", i);\n strcpy(dest, s);\n v5 = strlen(dest);\n for ( j = 0; j < v5 / 2; ++j )\n {\n v2 = dest[j];\n dest[j] = dest[v5 - 1 - j];\n dest[v5 - 1 - j] = v2;\n }\n if ( !strcmp(s, dest) )\n return (unsigned int)i;\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_34], edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov eax, [rbp+var_34]\nsub eax, 1\nmov [rbp+var_2C], eax\njmp loc_12CC\nloc_1215:\nmov edx, [rbp+var_2C]\nlea rax, [rbp+s]\nlea rcx, format; \"%d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rdx, [rbp+s]\nlea rax, [rbp+dest]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcpy\nlea rax, [rbp+dest]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_24], eax\nmov [rbp+var_28], 0\njmp short loc_129B\nloc_125E:\nmov eax, [rbp+var_28]\ncdqe\nmovzx eax, [rbp+rax+dest]\nmov [rbp+var_2D], al\nmov eax, [rbp+var_24]\nsub eax, 1\nsub eax, [rbp+var_28]\ncdqe\nmovzx edx, [rbp+rax+dest]\nmov eax, [rbp+var_28]\ncdqe\nmov [rbp+rax+dest], dl\nmov eax, [rbp+var_24]\nsub eax, 1\nsub eax, [rbp+var_28]\ncdqe\nmovzx edx, [rbp+var_2D]\nmov [rbp+rax+dest], dl\nadd [rbp+var_28], 1\nloc_129B:\nmov eax, [rbp+var_24]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\ncmp [rbp+var_28], eax\njl short loc_125E\nlea rdx, [rbp+dest]\nlea rax, [rbp+s]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_12C8\nmov eax, [rbp+var_2C]\njmp short loc_12DB\nloc_12C8:\nsub [rbp+var_2C], 1\nloc_12CC:\ncmp [rbp+var_2C], 0\njg loc_1215\nmov eax, 0\nloc_12DB:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12EF\ncall ___stack_chk_fail\nlocret_12EF:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11E9(int a1)\n{\n char v2; // [rsp+13h] [rbp-2Dh]\n int i; // [rsp+14h] [rbp-2Ch]\n int j; // [rsp+18h] [rbp-28h]\n int v5; // [rsp+1Ch] [rbp-24h]\n char s[12]; // [rsp+20h] [rbp-20h] BYREF\n char dest[12]; // [rsp+2Ch] [rbp-14h] BYREF\n unsigned __int64 v8; // [rsp+38h] [rbp-8h]\n\n v8 = __readfsqword(0x28u);\n for ( i = a1 - 1; i > 0; --i )\n {\n sprintf(s, \"%d\", i);\n strcpy(dest, s);\n v5 = strlen(dest);\n for ( j = 0; j < v5 / 2; ++j )\n {\n v2 = dest[j];\n dest[j] = dest[v5 - 1 - j];\n dest[v5 - 1 - j] = v2;\n }\n if ( !strcmp(s, dest) )\n return (unsigned int)i;\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11E9(int a1) {\n char v2;\n int i;\n int j;\n int v5;\n char s[12];\n char dest[12];\n unsigned long long v8;\n v8 = __readfsqword(40u);\n for (i = a1 - 1; i > 0; --i) {\n sprintf(s, \"%d\", i);\n strcpy(dest, s);\n v5 = strlen(dest);\n for (j = 0; j < v5 / 2; ++j) {\n v2 = dest[j];\n dest[j] = dest[v5 - 1 - j];\n dest[v5 - 1 - j] = v2;\n }\n if (!strcmp(s, dest)) return (unsigned int)i;\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n char v2;\n int i;\n int j;\n int v5;\n char s[12];\n char dest[12];\n unsigned long long v8;\n v8 = __readfsqword(40u);\n for (i = a1 - 1; i > 0; --i) {\n sprintf(s, \"%d\", i);\n strcpy(dest, s);\n v5 = strlen(dest);\n for (j = 0; j < v5 / 2; ++j) {\n v2 = dest[j];\n dest[j] = dest[v5 - 1 - j];\n dest[v5 - 1 - j] = v2;\n }\n if (!strcmp(s, dest)) return (unsigned int)i;\n }\n return 0LL;\n}" + }, + { + "index": 909, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int num) {\n char num_str[12], rev_str[12];\n for (int x = num - 1; x > 0; x--) {\n sprintf(num_str, \"%d\", x);\n strcpy(rev_str, num_str);\n int len = strlen(rev_str);\n char temp;\n for (int i = 0; i < len / 2; i++) {\n temp = rev_str[i];\n rev_str[i] = rev_str[len - 1 - i];\n rev_str[len - 1 - i] = temp;\n }\n if (strcmp(num_str, rev_str) == 0) {\n return x;\n }\n }\n return 0;\n}", + "test": "int main() {\n\n assert(func0(99) == 88);\n\n assert(func0(1221) == 1111);\n\n assert(func0(120) == 111);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x28,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x18(%rsp)\nxor %eax,%eax\nlea -0x1(%rdi),%ebx\ntest %ebx,%ebx\njle 12ab \nmov %rsp,%r12\nlea 0xc(%rsp),%rbp\nmov $0xffffffffffffffff,%r13\njmp 121f \nmov %rbp,%rsi\nmov %r12,%rdi\ncallq 10b0 \ntest %eax,%eax\nje 12b0 \nsub $0x1,%ebx\nje 12b0 \nmov %ebx,%r8d\nlea 0xddb(%rip),%rcx\nmov $0xc,%edx\nmov $0x1,%esi\nmov %r12,%rdi\nmov $0x0,%eax\ncallq 10d0 <__sprintf_chk@plt>\nmov $0xc,%edx\nmov %r12,%rsi\nmov %rbp,%rdi\ncallq 10c0 <__strcpy_chk@plt>\nmov $0x0,%eax\nmov %r13,%rcx\nmov %rbp,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nsub $0x1,%rax\nmov %eax,%r8d\nshr $0x1f,%r8d\nadd %eax,%r8d\nsar %r8d\ncmp $0x1,%eax\njle 1203 \nlea 0xc(%rsp),%rdx\ncltq\nadd %rdx,%rax\nmov $0x0,%ecx\nmovzbl (%rdx),%esi\nmovzbl -0x1(%rax),%edi\nmov %dil,(%rdx)\nmov %sil,-0x1(%rax)\nadd $0x1,%ecx\nadd $0x1,%rdx\nsub $0x1,%rax\ncmp %r8d,%ecx\njl 1288 \njmpq 1203 \nmov $0x0,%ebx\nmov 0x18(%rsp),%rax\nxor %fs:0x28,%rax\njne 12cd \nmov %ebx,%eax\nadd $0x28,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\ncallq 1090 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov rax, fs:28h\nmov [rsp+48h+var_30], rax\nxor eax, eax\nlea ebx, [rdi-1]\ntest ebx, ebx\njle loc_12B4\nmov r12, rsp\nlea r13, unk_2004\nlea rbp, [rsp+48h+s2]\njmp short loc_123B\nloc_1223:\nmov rsi, rbp; s2\nmov rdi, r12; s1\ncall _strcmp\ntest eax, eax\njz loc_12B9\nsub ebx, 1\njz short loc_12B9\nloc_123B:\nmov r8d, ebx\nmov rcx, r13\nmov edx, 0Ch\nmov esi, 2\nmov rdi, r12\nmov eax, 0\ncall ___sprintf_chk\nmov edx, 0Ch\nmov rsi, r12\nmov rdi, rbp\ncall ___strcpy_chk\nmov rdi, rbp; s\ncall _strlen\nmov r8d, eax\nshr r8d, 1Fh\nadd r8d, eax\nsar r8d, 1\ncmp eax, 1\njle short loc_1223\nlea rdx, [rsp+48h+s2]\ncdqe\nadd rax, rdx\nmov ecx, 0\nloc_1291:\nmovzx esi, byte ptr [rdx]\nmovzx edi, byte ptr [rax-1]\nmov [rdx], dil\nmov [rax-1], sil\nadd ecx, 1\nadd rdx, 1\nsub rax, 1\ncmp ecx, r8d\njl short loc_1291\njmp loc_1223\nloc_12B4:\nmov ebx, 0\nloc_12B9:\nmov rax, [rsp+48h+var_30]\nsub rax, fs:28h\njnz short loc_12D6\nmov eax, ebx\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_12D6:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v1; // ebx\n int v2; // eax\n int v3; // r8d\n char *v4; // rdx\n char *v5; // rax\n int v6; // ecx\n char v7; // si\n char v9[12]; // [rsp+0h] [rbp-48h] BYREF\n char s2[12]; // [rsp+Ch] [rbp-3Ch] BYREF\n unsigned __int64 v11; // [rsp+18h] [rbp-30h]\n\n v11 = __readfsqword(0x28u);\n v1 = a1 - 1;\n if ( a1 - 1 <= 0 )\n {\n return 0;\n }\n else\n {\n do\n {\n __sprintf_chk(v9, 2LL, 12LL, &unk_2004, v1);\n __strcpy_chk(s2, v9, 12LL);\n v2 = strlen(s2);\n v3 = v2 / 2;\n if ( v2 > 1 )\n {\n v4 = s2;\n v5 = &s2[v2];\n v6 = 0;\n do\n {\n v7 = *v4;\n *v4 = *(v5 - 1);\n *(v5 - 1) = v7;\n ++v6;\n ++v4;\n --v5;\n }\n while ( v6 < v3 );\n }\n if ( !strcmp(v9, s2) )\n break;\n --v1;\n }\n while ( v1 );\n }\n return v1;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov rax, fs:28h\nmov [rsp+48h+var_30], rax\nxor eax, eax\nlea ebx, [rdi-1]\ntest ebx, ebx\njle loc_12B4\nmov r12, rsp\nlea r13, unk_2004\nlea rbp, [rsp+48h+s2]\njmp short loc_123B\nloc_1223:\nmov rsi, rbp; s2\nmov rdi, r12; s1\ncall _strcmp\ntest eax, eax\njz loc_12B9\nsub ebx, 1\njz short loc_12B9\nloc_123B:\nmov r8d, ebx\nmov rcx, r13\nmov edx, 0Ch\nmov esi, 2\nmov rdi, r12\nmov eax, 0\ncall ___sprintf_chk\nmov edx, 0Ch\nmov rsi, r12\nmov rdi, rbp\ncall ___strcpy_chk\nmov rdi, rbp; s\ncall _strlen\nmov r8d, eax\nshr r8d, 1Fh\nadd r8d, eax\nsar r8d, 1\ncmp eax, 1\njle short loc_1223\nlea rdx, [rsp+48h+s2]\ncdqe\nadd rax, rdx\nmov ecx, 0\nloc_1291:\nmovzx esi, byte ptr [rdx]\nmovzx edi, byte ptr [rax-1]\nmov [rdx], dil\nmov [rax-1], sil\nadd ecx, 1\nadd rdx, 1\nsub rax, 1\ncmp ecx, r8d\njl short loc_1291\njmp loc_1223\nloc_12B4:\nmov ebx, 0\nloc_12B9:\nmov rax, [rsp+48h+var_30]\nsub rax, fs:28h\njnz short loc_12D6\nmov eax, ebx\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_12D6:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_11E9(int a1)\n{\n unsigned int v1; // ebx\n int v2; // eax\n int v3; // r8d\n char *v4; // rdx\n char *v5; // rax\n int v6; // ecx\n char v7; // si\n char v9[12]; // [rsp+0h] [rbp-48h] BYREF\n char s2[12]; // [rsp+Ch] [rbp-3Ch] BYREF\n unsigned __int64 v11; // [rsp+18h] [rbp-30h]\n\n v11 = __readfsqword(0x28u);\n v1 = a1 - 1;\n if ( a1 - 1 <= 0 )\n {\n return 0;\n }\n else\n {\n do\n {\n __sprintf_chk(v9, 2LL, 12LL, &unk_2004, v1);\n __strcpy_chk(s2, v9, 12LL);\n v2 = strlen(s2);\n v3 = v2 / 2;\n if ( v2 > 1 )\n {\n v4 = s2;\n v5 = &s2[v2];\n v6 = 0;\n do\n {\n v7 = *v4;\n *v4 = *(v5 - 1);\n *(v5 - 1) = v7;\n ++v6;\n ++v4;\n --v5;\n }\n while ( v6 < v3 );\n }\n if ( !strcmp(v9, s2) )\n break;\n --v1;\n }\n while ( v1 );\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11E9(int a1) {\n unsigned int v1;\n int v2;\n int v3;\n char *v4;\n char *v5;\n int v6;\n char v7;\n char v9[12];\n char s2[12];\n unsigned long long v11;\n v11 = __readfsqword(40u);\n v1 = a1 - 1;\n if (a1 - 1 <= 0) {\n return 0;\n } else {\n do {\n __sprintf_chk(v9, 2LL, 12LL, &unk_2004, v1);\n __strcpy_chk(s2, v9, 12LL);\n v2 = strlen(s2);\n v3 = v2 / 2;\n if (v2 > 1) {\n v4 = s2;\n v5 = &s2[v2];\n v6 = 0;\n do {\n v7 = *v4;\n *v4 = *(v5 - 1);\n *(v5 - 1) = v7;\n ++v6;\n ++v4;\n --v5;\n } while (v6 < v3);\n }\n if (!strcmp(v9, s2)) break;\n --v1;\n } while (v1);\n }\n return v1;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v1;\n int v2;\n int v3;\n char *v4;\n char *v5;\n int v6;\n char v7;\n char v9[12];\n char s2[12];\n unsigned long long v11;\n v11 = __readfsqword(40u);\n v1 = a1 - 1;\n if (a1 - 1 <= 0) {\n return 0;\n } else {\n do {\n __sprintf_chk(v9, 2LL, 12LL, &unk_2004, v1);\n __strcpy_chk(s2, v9, 12LL);\n v2 = strlen(s2);\n v3 = v2 / 2;\n if (v2 > 1) {\n v4 = s2;\n v5 = &s2[v2];\n v6 = 0;\n do {\n v7 = *v4;\n *v4 = *(v5 - 1);\n *(v5 - 1) = v7;\n ++v6;\n ++v4;\n --v5;\n } while (v6 < v3);\n }\n if (!strcmp(v9, s2)) break;\n --v1;\n } while (v1);\n }\n return v1;\n}" + }, + { + "index": 909, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int num) {\n char num_str[12], rev_str[12];\n for (int x = num - 1; x > 0; x--) {\n sprintf(num_str, \"%d\", x);\n strcpy(rev_str, num_str);\n int len = strlen(rev_str);\n char temp;\n for (int i = 0; i < len / 2; i++) {\n temp = rev_str[i];\n rev_str[i] = rev_str[len - 1 - i];\n rev_str[len - 1 - i] = temp;\n }\n if (strcmp(num_str, rev_str) == 0) {\n return x;\n }\n }\n return 0;\n}", + "test": "int main() {\n\n assert(func0(99) == 88);\n\n assert(func0(1221) == 1111);\n\n assert(func0(120) == 111);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nlea -0x1(%rdi),%r13d\npush %r12\npush %rbp\npush %rbx\nsub $0x28,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x18(%rsp)\nxor %eax,%eax\nmov %rsp,%rbp\nlea 0xc(%rsp),%rbx\nlea 0xd(%rsp),%r12\ntest %r13d,%r13d\njle 131f \nnopl 0x0(%rax)\nlea 0xd55(%rip),%rcx\nmov %r13d,%r8d\nmov %rbp,%rdi\nxor %eax,%eax\nmov $0xc,%edx\nmov $0x1,%esi\ncallq 10d0 <__sprintf_chk@plt>\nmov $0xc,%edx\nmov %rbp,%rsi\nmov %rbx,%rdi\ncallq 10c0 <__stpcpy_chk@plt>\nsub %rbx,%rax\nmov %eax,%ecx\nsar %ecx\nje 130a \ncltq\nlea -0x1(%rcx),%edi\nmov %rbx,%rdx\nlea -0x1(%rbx,%rax,1),%rax\nadd %r12,%rdi\nmovzbl (%rax),%esi\nmovzbl (%rdx),%ecx\nadd $0x1,%rdx\nsub $0x1,%rax\nmov %sil,-0x1(%rdx)\nmov %cl,0x1(%rax)\ncmp %rdi,%rdx\njne 12f0 \nmov %rbx,%rsi\nmov %rbp,%rdi\ncallq 10b0 \ntest %eax,%eax\nje 1322 \nsub $0x1,%r13d\njne 12a8 \nxor %r13d,%r13d\nmov 0x18(%rsp),%rax\nxor %fs:0x28,%rax\njne 1340 \nadd $0x28,%rsp\nmov %r13d,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\ncallq 1090 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r13\nlea r13, unk_2004\npush r12\npush rbp\nlea ebp, [rdi-1]\npush rbx\nsub rsp, 28h\nmov rax, fs:28h\nmov [rsp+48h+var_30], rax\nxor eax, eax\nmov r12, rsp\nlea rbx, [rsp+48h+s2]\ntest ebp, ebp\njle short loc_131E\nnop dword ptr [rax+00h]\nloc_12A8:\nmov r8d, ebp\nmov rcx, r13\nmov edx, 0Ch\nmov esi, 2\nmov rdi, r12\nxor eax, eax\ncall ___sprintf_chk\nmov rdi, rbx\nmov edx, 0Ch\nmov rsi, r12\ncall ___stpcpy_chk\nsub rax, rbx\nmov edi, eax\nsar edi, 1\njz short loc_130A\nmovsxd rdi, edi\nmov rdx, rbx\nlea rax, [rbx+rax-1]\nadd rdi, rbx\nnop dword ptr [rax+00000000h]\nloc_12F0:\nmovzx esi, byte ptr [rax]\nmovzx ecx, byte ptr [rdx]\nadd rdx, 1\nsub rax, 1\nmov [rdx-1], sil\nmov [rax+1], cl\ncmp rdx, rdi\njnz short loc_12F0\nloc_130A:\nmov rsi, rbx; s2\nmov rdi, r12; s1\ncall _strcmp\ntest eax, eax\njz short loc_1320\nsub ebp, 1\njnz short loc_12A8\nloc_131E:\nxor ebp, ebp\nloc_1320:\nmov rax, [rsp+48h+var_30]\nsub rax, fs:28h\njnz short loc_133D\nadd rsp, 28h\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_133D:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v1; // ebp\n __int64 v2; // rax\n int v3; // edi\n char *v4; // rdx\n char *v5; // rax\n char *v6; // rdi\n char v7; // si\n char v8; // cl\n char v10[12]; // [rsp+0h] [rbp-48h] BYREF\n char s2[12]; // [rsp+Ch] [rbp-3Ch] BYREF\n unsigned __int64 v12; // [rsp+18h] [rbp-30h]\n\n v1 = a1 - 1;\n v12 = __readfsqword(0x28u);\n if ( a1 - 1 <= 0 )\n {\n return 0;\n }\n else\n {\n while ( 1 )\n {\n __sprintf_chk(v10, 2LL, 12LL, &unk_2004, v1);\n v2 = __stpcpy_chk(s2, v10, 12LL) - (_QWORD)s2;\n v3 = (int)v2 >> 1;\n if ( (int)v2 >> 1 )\n {\n v4 = s2;\n v5 = &s2[v2 - 1];\n v6 = &s2[v3];\n do\n {\n v7 = *v5;\n v8 = *v4++;\n --v5;\n *(v4 - 1) = v7;\n v5[1] = v8;\n }\n while ( v4 != v6 );\n }\n if ( !strcmp(v10, s2) )\n break;\n if ( !--v1 )\n return 0;\n }\n }\n return v1;\n}", + "ida_strip_asm": "sub_1270:\nendbr64\npush r13\nlea r13, unk_2004\npush r12\npush rbp\nlea ebp, [rdi-1]\npush rbx\nsub rsp, 28h\nmov rax, fs:28h\nmov [rsp+48h+var_30], rax\nxor eax, eax\nmov r12, rsp\nlea rbx, [rsp+48h+s2]\ntest ebp, ebp\njle short loc_131E\nnop dword ptr [rax+00h]\nloc_12A8:\nmov r8d, ebp\nmov rcx, r13\nmov edx, 0Ch\nmov esi, 2\nmov rdi, r12\nxor eax, eax\ncall ___sprintf_chk\nmov rdi, rbx\nmov edx, 0Ch\nmov rsi, r12\ncall ___stpcpy_chk\nsub rax, rbx\nmov edi, eax\nsar edi, 1\njz short loc_130A\nmovsxd rdi, edi\nmov rdx, rbx\nlea rax, [rbx+rax-1]\nadd rdi, rbx\nnop dword ptr [rax+00000000h]\nloc_12F0:\nmovzx esi, byte ptr [rax]\nmovzx ecx, byte ptr [rdx]\nadd rdx, 1\nsub rax, 1\nmov [rdx-1], sil\nmov [rax+1], cl\ncmp rdx, rdi\njnz short loc_12F0\nloc_130A:\nmov rsi, rbx; s2\nmov rdi, r12; s1\ncall _strcmp\ntest eax, eax\njz short loc_1320\nsub ebp, 1\njnz short loc_12A8\nloc_131E:\nxor ebp, ebp\nloc_1320:\nmov rax, [rsp+48h+var_30]\nsub rax, fs:28h\njnz short loc_133D\nadd rsp, 28h\nmov eax, ebp\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_133D:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1270(int a1)\n{\n unsigned int v1; // ebp\n __int64 v2; // rax\n int v3; // edi\n char *v4; // rdx\n char *v5; // rax\n char *v6; // rdi\n char v7; // si\n char v8; // cl\n char v10[12]; // [rsp+0h] [rbp-48h] BYREF\n char s2[12]; // [rsp+Ch] [rbp-3Ch] BYREF\n unsigned __int64 v12; // [rsp+18h] [rbp-30h]\n\n v1 = a1 - 1;\n v12 = __readfsqword(0x28u);\n if ( a1 - 1 <= 0 )\n {\n return 0;\n }\n else\n {\n while ( 1 )\n {\n __sprintf_chk(v10, 2LL, 12LL, &unk_2004, v1);\n v2 = __stpcpy_chk(s2, v10, 12LL) - (_QWORD)s2;\n v3 = (int)v2 >> 1;\n if ( (int)v2 >> 1 )\n {\n v4 = s2;\n v5 = &s2[v2 - 1];\n v6 = &s2[v3];\n do\n {\n v7 = *v5;\n v8 = *v4++;\n --v5;\n *(v4 - 1) = v7;\n v5[1] = v8;\n }\n while ( v4 != v6 );\n }\n if ( !strcmp(v10, s2) )\n break;\n if ( !--v1 )\n return 0;\n }\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1270(int a1) {\n unsigned int v1;\n long long v2;\n int v3;\n char *v4;\n char *v5;\n char *v6;\n char v7;\n char v8;\n char v10[12];\n char s2[12];\n unsigned long long v12;\n v1 = a1 - 1;\n v12 = __readfsqword(40u);\n if (a1 - 1 <= 0) {\n return 0;\n } else {\n while (1) {\n __sprintf_chk(v10, 2LL, 12LL, &unk_2004, v1);\n v2 = __stpcpy_chk(s2, v10, 12LL) - (uint64_t)s2;\n v3 = (int)v2 >> 1;\n if ((int)v2 >> 1) {\n v4 = s2;\n v5 = &s2[v2 - 1];\n v6 = &s2[v3];\n do {\n v7 = *v5;\n v8 = *v4++;\n --v5;\n *(v4 - 1) = v7;\n v5[1] = v8;\n } while (v4 != v6);\n }\n if (!strcmp(v10, s2)) break;\n if (!--v1) return 0;\n }\n }\n return v1;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v1;\n long long v2;\n int v3;\n char *v4;\n char *v5;\n char *v6;\n char v7;\n char v8;\n char v10[12];\n char s2[12];\n unsigned long long v12;\n v1 = a1 - 1;\n v12 = __readfsqword(40u);\n if (a1 - 1 <= 0) {\n return 0;\n } else {\n while (1) {\n __sprintf_chk(v10, 2LL, 12LL, &unk_2004, v1);\n v2 = __stpcpy_chk(s2, v10, 12LL) - (uint64_t)s2;\n v3 = (int)v2 >> 1;\n if ((int)v2 >> 1) {\n v4 = s2;\n v5 = &s2[v2 - 1];\n v6 = &s2[v3];\n do {\n v7 = *v5;\n v8 = *v4++;\n --v5;\n *(v4 - 1) = v7;\n v5[1] = v8;\n } while (v4 != v6);\n }\n if (!strcmp(v10, s2)) break;\n if (!--v1) return 0;\n }\n }\n return v1;\n}" + }, + { + "index": 909, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int num) {\n char num_str[12], rev_str[12];\n for (int x = num - 1; x > 0; x--) {\n sprintf(num_str, \"%d\", x);\n strcpy(rev_str, num_str);\n int len = strlen(rev_str);\n char temp;\n for (int i = 0; i < len / 2; i++) {\n temp = rev_str[i];\n rev_str[i] = rev_str[len - 1 - i];\n rev_str[len - 1 - i] = temp;\n }\n if (strcmp(num_str, rev_str) == 0) {\n return x;\n }\n }\n return 0;\n}", + "test": "int main() {\n\n assert(func0(99) == 88);\n\n assert(func0(1221) == 1111);\n\n assert(func0(120) == 111);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nlea -0x1(%rdi),%r13d\npush %r12\nlea 0xd81(%rip),%r12\npush %rbp\npush %rbx\nsub $0x28,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x18(%rsp)\nxor %eax,%eax\nmov %rsp,%rbp\nlea 0xc(%rsp),%rbx\ntest %r13d,%r13d\njg 12ba \njmpq 13b5 \nnopl 0x0(%rax,%rax,1)\nsub $0x1,%r13d\nje 13b5 \nmov %r12,%rcx\nmov %r13d,%r8d\nmov $0xc,%edx\nmov $0x1,%esi\nmov %rbp,%rdi\nxor %eax,%eax\ncallq 10d0 <__sprintf_chk@plt>\nmov $0xc,%edx\nmov %rbp,%rsi\nmov %rbx,%rdi\ncallq 10c0 <__stpcpy_chk@plt>\nsub %rbx,%rax\nmov %eax,%ecx\nsar %ecx\nje 1384 \nlea -0x1(%rax),%edx\nmovzbl 0xc(%rsp),%esi\nmovslq %edx,%rdx\nmovzbl 0xc(%rsp,%rdx,1),%edi\nmov %dil,0xc(%rsp)\nmov %sil,0xc(%rsp,%rdx,1)\ncmp $0x1,%ecx\nje 1384 \nlea -0x2(%rax),%edx\nmovzbl 0xd(%rsp),%esi\nmovslq %edx,%rdx\nmovzbl 0xc(%rsp,%rdx,1),%edi\nmov %dil,0xd(%rsp)\nmov %sil,0xc(%rsp,%rdx,1)\ncmp $0x2,%ecx\nje 1384 \nlea -0x3(%rax),%edx\nmovzbl 0xe(%rsp),%esi\nmovslq %edx,%rdx\nmovzbl 0xc(%rsp,%rdx,1),%edi\nmov %dil,0xe(%rsp)\nmov %sil,0xc(%rsp,%rdx,1)\ncmp $0x3,%ecx\nje 1384 \nlea -0x4(%rax),%edx\nmovzbl 0xf(%rsp),%esi\nmovslq %edx,%rdx\nmovzbl 0xc(%rsp,%rdx,1),%edi\nmov %dil,0xf(%rsp)\nmov %sil,0xc(%rsp,%rdx,1)\ncmp $0x5,%ecx\njne 1384 \nsub $0x5,%eax\nmovzbl 0x10(%rsp),%edx\ncltq\nmovzbl 0xc(%rsp,%rax,1),%ecx\nmov %cl,0x10(%rsp)\nmov %dl,0xc(%rsp,%rax,1)\nmov %rbx,%rsi\nmov %rbp,%rdi\ncallq 10b0 \ntest %eax,%eax\njne 12b0 \nmov 0x18(%rsp),%rax\nxor %fs:0x28,%rax\njne 13ba \nadd $0x28,%rsp\nmov %r13d,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nxor %r13d,%r13d\njmp 1397 \ncallq 1090 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r13\nlea r13, unk_2004\npush r12\npush rbp\npush rbx\nlea ebx, [rdi-1]\nsub rsp, 28h\nmov rax, fs:28h\nmov [rsp+48h+var_30], rax\nxor eax, eax\nmov r12, rsp\nlea rbp, [rsp+48h+s2]\ntest ebx, ebx\njg short loc_12B9\njmp loc_13B3\nloc_12B0:\nsub ebx, 1\njz loc_13B3\nloc_12B9:\nmov rcx, r13\nmov r8d, ebx\nmov edx, 0Ch\nmov esi, 2\nmov rdi, r12\nxor eax, eax\ncall ___sprintf_chk\nmov edx, 0Ch\nmov rsi, r12\nmov rdi, rbp\ncall ___stpcpy_chk\nsub rax, rbp\nmov ecx, eax\nsar ecx, 1\njz loc_1383\nlea edx, [rax-1]\nmovzx esi, [rsp+48h+s2]\nmovsxd rdx, edx\nmovzx edi, [rsp+rdx+48h+s2]\nmov [rsp+rdx+48h+s2], sil\nmov [rsp+48h+s2], dil\ncmp ecx, 1\njz short loc_1383\nlea edx, [rax-2]\nmovzx esi, [rsp+48h+var_3B]\nmovsxd rdx, edx\nmovzx edi, [rsp+rdx+48h+s2]\nmov [rsp+rdx+48h+s2], sil\nmov [rsp+48h+var_3B], dil\ncmp ecx, 2\njz short loc_1383\nlea edx, [rax-3]\nmovzx esi, [rsp+48h+var_3A]\nmovsxd rdx, edx\nmovzx edi, [rsp+rdx+48h+s2]\nmov [rsp+rdx+48h+s2], sil\nmov [rsp+48h+var_3A], dil\ncmp ecx, 3\njz short loc_1383\nlea edx, [rax-4]\nmovzx esi, [rsp+48h+var_39]\nmovsxd rdx, edx\nmovzx edi, [rsp+rdx+48h+s2]\nmov [rsp+rdx+48h+s2], sil\nmov [rsp+48h+var_39], dil\ncmp ecx, 5\njnz short loc_1383\nsub eax, 5\nmovzx edx, [rsp+48h+var_38]\ncdqe\nmovzx ecx, [rsp+rax+48h+s2]\nmov [rsp+rax+48h+s2], dl\nmov [rsp+48h+var_38], cl\nloc_1383:\nmov rsi, rbp; s2\nmov rdi, r12; s1\ncall _strcmp\ntest eax, eax\njnz loc_12B0\nloc_1396:\nmov rax, [rsp+48h+var_30]\nsub rax, fs:28h\njnz short loc_13B7\nadd rsp, 28h\nmov eax, ebx\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_13B3:\nxor ebx, ebx\njmp short loc_1396\nloc_13B7:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n unsigned int v1; // ebx\n __int64 v2; // rax\n int v3; // ecx\n char v4; // di\n char v5; // di\n char v6; // di\n char v7; // di\n int v8; // eax\n char v9; // cl\n char v11[12]; // [rsp+0h] [rbp-48h] BYREF\n char s2; // [rsp+Ch] [rbp-3Ch] BYREF\n char v13; // [rsp+Dh] [rbp-3Bh]\n char v14; // [rsp+Eh] [rbp-3Ah]\n char v15; // [rsp+Fh] [rbp-39h]\n char v16; // [rsp+10h] [rbp-38h]\n unsigned __int64 v17; // [rsp+18h] [rbp-30h]\n\n v1 = a1 - 1;\n v17 = __readfsqword(0x28u);\n if ( a1 - 1 > 0 )\n {\n while ( 1 )\n {\n __sprintf_chk(v11, 2LL, 12LL, &unk_2004, v1);\n v2 = __stpcpy_chk(&s2, v11, 12LL) - (_QWORD)&s2;\n v3 = (int)v2 >> 1;\n if ( (int)v2 >> 1 )\n {\n v4 = *(&s2 + (int)v2 - 1);\n *(&s2 + (int)v2 - 1) = s2;\n s2 = v4;\n if ( v3 != 1 )\n {\n v5 = *(&s2 + (int)v2 - 2);\n *(&s2 + (int)v2 - 2) = v13;\n v13 = v5;\n if ( v3 != 2 )\n {\n v6 = *(&s2 + (int)v2 - 3);\n *(&s2 + (int)v2 - 3) = v14;\n v14 = v6;\n if ( v3 != 3 )\n {\n v7 = *(&s2 + (int)v2 - 4);\n *(&s2 + (int)v2 - 4) = v15;\n v15 = v7;\n if ( v3 == 5 )\n {\n v8 = v2 - 5;\n v9 = *(&s2 + v8);\n *(&s2 + v8) = v16;\n v16 = v9;\n }\n }\n }\n }\n }\n if ( !strcmp(v11, &s2) )\n break;\n if ( !--v1 )\n return 0;\n }\n }\n else\n {\n return 0;\n }\n return v1;\n}", + "ida_strip_asm": "sub_1270:\nendbr64\npush r13\nlea r13, unk_2004\npush r12\npush rbp\npush rbx\nlea ebx, [rdi-1]\nsub rsp, 28h\nmov rax, fs:28h\nmov [rsp+48h+var_30], rax\nxor eax, eax\nmov r12, rsp\nlea rbp, [rsp+48h+s2]\ntest ebx, ebx\njg short loc_12B9\njmp loc_13B3\nloc_12B0:\nsub ebx, 1\njz loc_13B3\nloc_12B9:\nmov rcx, r13\nmov r8d, ebx\nmov edx, 0Ch\nmov esi, 2\nmov rdi, r12\nxor eax, eax\ncall ___sprintf_chk\nmov edx, 0Ch\nmov rsi, r12\nmov rdi, rbp\ncall ___stpcpy_chk\nsub rax, rbp\nmov ecx, eax\nsar ecx, 1\njz loc_1383\nlea edx, [rax-1]\nmovzx esi, [rsp+48h+s2]\nmovsxd rdx, edx\nmovzx edi, [rsp+rdx+48h+s2]\nmov [rsp+rdx+48h+s2], sil\nmov [rsp+48h+s2], dil\ncmp ecx, 1\njz short loc_1383\nlea edx, [rax-2]\nmovzx esi, [rsp+48h+var_3B]\nmovsxd rdx, edx\nmovzx edi, [rsp+rdx+48h+s2]\nmov [rsp+rdx+48h+s2], sil\nmov [rsp+48h+var_3B], dil\ncmp ecx, 2\njz short loc_1383\nlea edx, [rax-3]\nmovzx esi, [rsp+48h+var_3A]\nmovsxd rdx, edx\nmovzx edi, [rsp+rdx+48h+s2]\nmov [rsp+rdx+48h+s2], sil\nmov [rsp+48h+var_3A], dil\ncmp ecx, 3\njz short loc_1383\nlea edx, [rax-4]\nmovzx esi, [rsp+48h+var_39]\nmovsxd rdx, edx\nmovzx edi, [rsp+rdx+48h+s2]\nmov [rsp+rdx+48h+s2], sil\nmov [rsp+48h+var_39], dil\ncmp ecx, 5\njnz short loc_1383\nsub eax, 5\nmovzx edx, [rsp+48h+var_38]\ncdqe\nmovzx ecx, [rsp+rax+48h+s2]\nmov [rsp+rax+48h+s2], dl\nmov [rsp+48h+var_38], cl\nloc_1383:\nmov rsi, rbp; s2\nmov rdi, r12; s1\ncall _strcmp\ntest eax, eax\njnz loc_12B0\nloc_1396:\nmov rax, [rsp+48h+var_30]\nsub rax, fs:28h\njnz short loc_13B7\nadd rsp, 28h\nmov eax, ebx\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_13B3:\nxor ebx, ebx\njmp short loc_1396\nloc_13B7:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1270(int a1)\n{\n unsigned int v1; // ebx\n __int64 v2; // rax\n int v3; // ecx\n char v4; // di\n char v5; // di\n char v6; // di\n char v7; // di\n int v8; // eax\n char v9; // cl\n char v11[12]; // [rsp+0h] [rbp-48h] BYREF\n char s2; // [rsp+Ch] [rbp-3Ch] BYREF\n char v13; // [rsp+Dh] [rbp-3Bh]\n char v14; // [rsp+Eh] [rbp-3Ah]\n char v15; // [rsp+Fh] [rbp-39h]\n char v16; // [rsp+10h] [rbp-38h]\n unsigned __int64 v17; // [rsp+18h] [rbp-30h]\n\n v1 = a1 - 1;\n v17 = __readfsqword(0x28u);\n if ( a1 - 1 > 0 )\n {\n while ( 1 )\n {\n __sprintf_chk(v11, 2LL, 12LL, &unk_2004, v1);\n v2 = __stpcpy_chk(&s2, v11, 12LL) - (_QWORD)&s2;\n v3 = (int)v2 >> 1;\n if ( (int)v2 >> 1 )\n {\n v4 = *(&s2 + (int)v2 - 1);\n *(&s2 + (int)v2 - 1) = s2;\n s2 = v4;\n if ( v3 != 1 )\n {\n v5 = *(&s2 + (int)v2 - 2);\n *(&s2 + (int)v2 - 2) = v13;\n v13 = v5;\n if ( v3 != 2 )\n {\n v6 = *(&s2 + (int)v2 - 3);\n *(&s2 + (int)v2 - 3) = v14;\n v14 = v6;\n if ( v3 != 3 )\n {\n v7 = *(&s2 + (int)v2 - 4);\n *(&s2 + (int)v2 - 4) = v15;\n v15 = v7;\n if ( v3 == 5 )\n {\n v8 = v2 - 5;\n v9 = *(&s2 + v8);\n *(&s2 + v8) = v16;\n v16 = v9;\n }\n }\n }\n }\n }\n if ( !strcmp(v11, &s2) )\n break;\n if ( !--v1 )\n return 0;\n }\n }\n else\n {\n return 0;\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1270(int a1) {\n unsigned int v1;\n long long v2;\n int v3;\n char v4;\n char v5;\n char v6;\n char v7;\n int v8;\n char v9;\n char v11[12];\n char s2;\n char v13;\n char v14;\n char v15;\n char v16;\n unsigned long long v17;\n v1 = a1 - 1;\n v17 = __readfsqword(40u);\n if (a1 - 1 > 0) {\n while (1) {\n __sprintf_chk(v11, 2LL, 12LL, &unk_2004, v1);\n v2 = __stpcpy_chk(&s2, v11, 12LL) - (uint64_t)&s2;\n v3 = (int)v2 >> 1;\n if ((int)v2 >> 1) {\n v4 = *(&s2 + (int)v2 - 1);\n *(&s2 + (int)v2 - 1) = s2;\n s2 = v4;\n if (v3 != 1) {\n v5 = *(&s2 + (int)v2 - 2);\n *(&s2 + (int)v2 - 2) = v13;\n v13 = v5;\n if (v3 != 2) {\n v6 = *(&s2 + (int)v2 - 3);\n *(&s2 + (int)v2 - 3) = v14;\n v14 = v6;\n if (v3 != 3) {\n v7 = *(&s2 + (int)v2 - 4);\n *(&s2 + (int)v2 - 4) = v15;\n v15 = v7;\n if (v3 == 5) {\n v8 = v2 - 5;\n v9 = *(&s2 + v8);\n *(&s2 + v8) = v16;\n v16 = v9;\n }\n }\n }\n }\n }\n if (!strcmp(v11, &s2)) break;\n if (!--v1) return 0;\n }\n } else {\n return 0;\n }\n return v1;\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n unsigned int v1;\n long long v2;\n int v3;\n char v4;\n char v5;\n char v6;\n char v7;\n int v8;\n char v9;\n char v11[12];\n char s2;\n char v13;\n char v14;\n char v15;\n char v16;\n unsigned long long v17;\n v1 = a1 - 1;\n v17 = __readfsqword(40u);\n if (a1 - 1 > 0) {\n while (1) {\n __sprintf_chk(v11, 2LL, 12LL, &unk_2004, v1);\n v2 = __stpcpy_chk(&s2, v11, 12LL) - (uint64_t)&s2;\n v3 = (int)v2 >> 1;\n if ((int)v2 >> 1) {\n v4 = *(&s2 + (int)v2 - 1);\n *(&s2 + (int)v2 - 1) = s2;\n s2 = v4;\n if (v3 != 1) {\n v5 = *(&s2 + (int)v2 - 2);\n *(&s2 + (int)v2 - 2) = v13;\n v13 = v5;\n if (v3 != 2) {\n v6 = *(&s2 + (int)v2 - 3);\n *(&s2 + (int)v2 - 3) = v14;\n v14 = v6;\n if (v3 != 3) {\n v7 = *(&s2 + (int)v2 - 4);\n *(&s2 + (int)v2 - 4) = v15;\n v15 = v7;\n if (v3 == 5) {\n v8 = v2 - 5;\n v9 = *(&s2 + v8);\n *(&s2 + v8) = v16;\n v16 = v9;\n }\n }\n }\n }\n }\n if (!strcmp(v11, &s2)) break;\n if (!--v1) return 0;\n }\n } else {\n return 0;\n }\n return v1;\n}" + }, + { + "index": 910, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int m, int d, int y) {\n struct tm time;\n time.tm_year = y - 1900;\n time.tm_mon = m - 1;\n time.tm_mday = d;\n time.tm_hour = 0;\n time.tm_min = 0;\n time.tm_sec = 0;\n time.tm_isdst = -1;\n if (mktime(&time) == -1) {\n return false;\n } else {\n if (time.tm_year + 1900 != y || time.tm_mon + 1 != m || time.tm_mday != d) {\n return false;\n }\n return true;\n }\n}", + "test": "int main() {\n\n assert(func0(11,11,2002) == true);\n\n assert(func0(13,11,2002) == false);\n\n assert(func0(11,11,2002) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x50,%rsp\nmov %edi,-0x44(%rbp)\nmov %esi,-0x48(%rbp)\nmov %edx,-0x4c(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmov -0x4c(%rbp),%eax\nsub $0x76c,%eax\nmov %eax,-0x2c(%rbp)\nmov -0x44(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0x30(%rbp)\nmov -0x48(%rbp),%eax\nmov %eax,-0x34(%rbp)\nmovl $0x0,-0x38(%rbp)\nmovl $0x0,-0x3c(%rbp)\nmovl $0x0,-0x40(%rbp)\nmovl $0xffffffff,-0x20(%rbp)\nlea -0x40(%rbp),%rax\nmov %rax,%rdi\ncallq 1090 \ncmp $0xffffffffffffffff,%rax\njne 11fc \nmov $0x0,%eax\njmp 1228 \nmov -0x2c(%rbp),%eax\nadd $0x76c,%eax\ncmp %eax,-0x4c(%rbp)\njne 121c \nmov -0x30(%rbp),%eax\nadd $0x1,%eax\ncmp %eax,-0x44(%rbp)\njne 121c \nmov -0x34(%rbp),%eax\ncmp %eax,-0x48(%rbp)\nje 1223 \nmov $0x0,%eax\njmp 1228 \nmov $0x1,%eax\nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 123c \ncallq 1070 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+var_44], edi\nmov [rbp+var_48], esi\nmov [rbp+var_4C], edx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov eax, [rbp+var_4C]\nsub eax, 76Ch\nmov [rbp+tp.tm_year], eax\nmov eax, [rbp+var_44]\nsub eax, 1\nmov [rbp+tp.tm_mon], eax\nmov eax, [rbp+var_48]\nmov [rbp+tp.tm_mday], eax\nmov [rbp+tp.tm_hour], 0\nmov [rbp+tp.tm_min], 0\nmov [rbp+tp.tm_sec], 0\nmov [rbp+tp.tm_isdst], 0FFFFFFFFh\nlea rax, [rbp+tp]\nmov rdi, rax; tp\ncall _mktime\ncmp rax, 0FFFFFFFFFFFFFFFFh\njnz short loc_11FC\nmov eax, 0\njmp short loc_1228\nloc_11FC:\nmov eax, [rbp+tp.tm_year]\nadd eax, 76Ch\ncmp [rbp+var_4C], eax\njnz short loc_121C\nmov eax, [rbp+tp.tm_mon]\nadd eax, 1\ncmp [rbp+var_44], eax\njnz short loc_121C\nmov eax, [rbp+tp.tm_mday]\ncmp [rbp+var_48], eax\njz short loc_1223\nloc_121C:\nmov eax, 0\njmp short loc_1228\nloc_1223:\nmov eax, 1\nloc_1228:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_123C\ncall ___stack_chk_fail\nlocret_123C:\nleave\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(int a1, int a2, int a3)\n{\n tm tp; // [rsp+10h] [rbp-40h] BYREF\n unsigned __int64 v6; // [rsp+48h] [rbp-8h]\n\n v6 = __readfsqword(0x28u);\n tp.tm_year = a3 - 1900;\n tp.tm_mon = a1 - 1;\n tp.tm_mday = a2;\n tp.tm_hour = 0;\n tp.tm_min = 0;\n tp.tm_sec = 0;\n tp.tm_isdst = -1;\n if ( mktime(&tp) == -1 )\n return 0LL;\n return a3 == tp.tm_year + 1900 && a1 == tp.tm_mon + 1 && a2 == tp.tm_mday;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+var_44], edi\nmov [rbp+var_48], esi\nmov [rbp+var_4C], edx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov eax, [rbp+var_4C]\nsub eax, 76Ch\nmov [rbp+tp.tm_year], eax\nmov eax, [rbp+var_44]\nsub eax, 1\nmov [rbp+tp.tm_mon], eax\nmov eax, [rbp+var_48]\nmov [rbp+tp.tm_mday], eax\nmov [rbp+tp.tm_hour], 0\nmov [rbp+tp.tm_min], 0\nmov [rbp+tp.tm_sec], 0\nmov [rbp+tp.tm_isdst], 0FFFFFFFFh\nlea rax, [rbp+tp]\nmov rdi, rax; tp\ncall _mktime\ncmp rax, 0FFFFFFFFFFFFFFFFh\njnz short loc_11FC\nmov eax, 0\njmp short loc_1228\nloc_11FC:\nmov eax, [rbp+tp.tm_year]\nadd eax, 76Ch\ncmp [rbp+var_4C], eax\njnz short loc_121C\nmov eax, [rbp+tp.tm_mon]\nadd eax, 1\ncmp [rbp+var_44], eax\njnz short loc_121C\nmov eax, [rbp+tp.tm_mday]\ncmp [rbp+var_48], eax\njz short loc_1223\nloc_121C:\nmov eax, 0\njmp short loc_1228\nloc_1223:\nmov eax, 1\nloc_1228:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_123C\ncall ___stack_chk_fail\nlocret_123C:\nleave\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1189(int a1, int a2, int a3)\n{\n tm tp; // [rsp+10h] [rbp-40h] BYREF\n unsigned __int64 v6; // [rsp+48h] [rbp-8h]\n\n v6 = __readfsqword(0x28u);\n tp.tm_year = a3 - 1900;\n tp.tm_mon = a1 - 1;\n tp.tm_mday = a2;\n tp.tm_hour = 0;\n tp.tm_min = 0;\n tp.tm_sec = 0;\n tp.tm_isdst = -1;\n if ( mktime(&tp) == -1 )\n return 0LL;\n return a3 == tp.tm_year + 1900 && a1 == tp.tm_mon + 1 && a2 == tp.tm_mday;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1189(int a1, int a2, int a3) {\n tm tp;\n unsigned long long v6;\n v6 = __readfsqword(40u);\n tp.tm_year = a3 - 1900;\n tp.tm_mon = a1 - 1;\n tp.tm_mday = a2;\n tp.tm_hour = 0;\n tp.tm_min = 0;\n tp.tm_sec = 0;\n tp.tm_isdst = -1;\n if (mktime(&tp) == -1) return 0LL;\n return a3 == tp.tm_year + 1900 && a1 == tp.tm_mon + 1 && a2 == tp.tm_mday;\n}", + "ida_pseudo_norm": "uint8_t func0(int a1, int a2, int a3) {\n tm tp;\n unsigned long long v6;\n v6 = __readfsqword(40u);\n tp.tm_year = a3 - 1900;\n tp.tm_mon = a1 - 1;\n tp.tm_mday = a2;\n tp.tm_hour = 0;\n tp.tm_min = 0;\n tp.tm_sec = 0;\n tp.tm_isdst = -1;\n if (mktime(&tp) == -1) return 0LL;\n return a3 == tp.tm_year + 1900 && a1 == tp.tm_mon + 1 && a2 == tp.tm_mday;\n}" + }, + { + "index": 910, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int m, int d, int y) {\n struct tm time;\n time.tm_year = y - 1900;\n time.tm_mon = m - 1;\n time.tm_mday = d;\n time.tm_hour = 0;\n time.tm_min = 0;\n time.tm_sec = 0;\n time.tm_isdst = -1;\n if (mktime(&time) == -1) {\n return false;\n } else {\n if (time.tm_year + 1900 != y || time.tm_mon + 1 != m || time.tm_mday != d) {\n return false;\n }\n return true;\n }\n}", + "test": "int main() {\n\n assert(func0(11,11,2002) == true);\n\n assert(func0(13,11,2002) == false);\n\n assert(func0(11,11,2002) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nsub $0x40,%rsp\nmov %edi,%ebp\nmov %esi,%r12d\nmov %edx,%ebx\nmov %fs:0x28,%rax\nmov %rax,0x38(%rsp)\nxor %eax,%eax\nlea -0x76c(%rdx),%eax\nmov %eax,0x14(%rsp)\nlea -0x1(%rdi),%eax\nmov %eax,0x10(%rsp)\nmov %esi,0xc(%rsp)\nmovl $0x0,0x8(%rsp)\nmovl $0x0,0x4(%rsp)\nmovl $0x0,(%rsp)\nmovl $0xffffffff,0x20(%rsp)\nmov %rsp,%rdi\ncallq 1090 \nmov %rax,%rdx\nmov $0x0,%eax\ncmp $0xffffffffffffffff,%rdx\nje 1221 \nmov 0x14(%rsp),%eax\nlea 0x76c(%rax),%edx\nmov $0x0,%eax\ncmp %ebx,%edx\njne 1221 \nmov 0x10(%rsp),%eax\nlea 0x1(%rax),%edx\nmov $0x0,%eax\ncmp %ebp,%edx\njne 1221 \ncmp %r12d,0xc(%rsp)\nsete %al\nmov 0x38(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 123a \nadd $0x40,%rsp\npop %rbx\npop %rbp\npop %r12\nretq\ncallq 1070 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 40h\nmov ebp, edi\nmov r12d, esi\nmov ebx, edx\nmov rax, fs:28h\nmov [rsp+58h+var_20], rax\nxor eax, eax\nlea eax, [rdx-76Ch]\nmov [rsp+58h+var_44], eax\nlea eax, [rdi-1]\nmov [rsp+58h+var_48], eax\nmov [rsp+58h+var_4C], esi\nmov [rsp+58h+var_50], 0\nmov [rsp+58h+var_54], 0\nmov [rsp+58h+var_58], 0\nmov [rsp+58h+var_38], 0FFFFFFFFh\nmov rdi, rsp; tp\ncall _mktime\nmov rdx, rax\nmov eax, 0\ncmp rdx, 0FFFFFFFFFFFFFFFFh\njz short loc_1221\nmov eax, [rsp+58h+var_44]\nlea edx, [rax+76Ch]\nmov eax, 0\ncmp edx, ebx\njnz short loc_1221\nmov eax, [rsp+58h+var_48]\nlea edx, [rax+1]\nmov eax, 0\ncmp edx, ebp\njnz short loc_1221\ncmp [rsp+58h+var_4C], r12d\nsetz al\nloc_1221:\nmov rdx, [rsp+58h+var_20]\nsub rdx, fs:28h\njnz short loc_123A\nadd rsp, 40h\npop rbx\npop rbp\npop r12\nretn\nloc_123A:\ncall ___stack_chk_fail", + "ida_pseudo": "bool __fastcall func0(int a1, int a2, int a3)\n{\n time_t v4; // rdx\n bool result; // al\n struct tm v6; // [rsp+0h] [rbp-58h] BYREF\n unsigned __int64 v7; // [rsp+38h] [rbp-20h]\n\n v7 = __readfsqword(0x28u);\n v6.tm_year = a3 - 1900;\n v6.tm_mon = a1 - 1;\n v6.tm_mday = a2;\n v6.tm_hour = 0;\n v6.tm_min = 0;\n v6.tm_sec = 0;\n v6.tm_isdst = -1;\n v4 = mktime(&v6);\n result = 0;\n if ( v4 != -1 )\n {\n result = 0;\n if ( v6.tm_year + 1900 == a3 )\n {\n result = 0;\n if ( v6.tm_mon + 1 == a1 )\n return v6.tm_mday == a2;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 40h\nmov ebp, edi\nmov r12d, esi\nmov ebx, edx\nmov rax, fs:28h\nmov [rsp+58h+var_20], rax\nxor eax, eax\nlea eax, [rdx-76Ch]\nmov [rsp+58h+var_44], eax\nlea eax, [rdi-1]\nmov [rsp+58h+var_48], eax\nmov [rsp+58h+var_4C], esi\nmov [rsp+58h+var_50], 0\nmov [rsp+58h+var_54], 0\nmov [rsp+58h+var_58], 0\nmov [rsp+58h+var_38], 0FFFFFFFFh\nmov rdi, rsp; tp\ncall _mktime\nmov rdx, rax\nmov eax, 0\ncmp rdx, 0FFFFFFFFFFFFFFFFh\njz short loc_1221\nmov eax, [rsp+58h+var_44]\nlea edx, [rax+76Ch]\nmov eax, 0\ncmp edx, ebx\njnz short loc_1221\nmov eax, [rsp+58h+var_48]\nlea edx, [rax+1]\nmov eax, 0\ncmp edx, ebp\njnz short loc_1221\ncmp [rsp+58h+var_4C], r12d\nsetz al\nloc_1221:\nmov rdx, [rsp+58h+var_20]\nsub rdx, fs:28h\njnz short loc_123A\nadd rsp, 40h\npop rbx\npop rbp\npop r12\nretn\nloc_123A:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "bool __fastcall sub_1189(int a1, int a2, int a3)\n{\n time_t v4; // rdx\n bool result; // al\n struct tm v6; // [rsp+0h] [rbp-58h] BYREF\n unsigned __int64 v7; // [rsp+38h] [rbp-20h]\n\n v7 = __readfsqword(0x28u);\n v6.tm_year = a3 - 1900;\n v6.tm_mon = a1 - 1;\n v6.tm_mday = a2;\n v6.tm_hour = 0;\n v6.tm_min = 0;\n v6.tm_sec = 0;\n v6.tm_isdst = -1;\n v4 = mktime(&v6);\n result = 0;\n if ( v4 != -1 )\n {\n result = 0;\n if ( v6.tm_year + 1900 == a3 )\n {\n result = 0;\n if ( v6.tm_mon + 1 == a1 )\n return v6.tm_mday == a2;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_1189(int a1, int a2, int a3) {\n time_t v4;\n bool result;\n struct tm v6;\n unsigned long long v7;\n v7 = __readfsqword(40u);\n v6.tm_year = a3 - 1900;\n v6.tm_mon = a1 - 1;\n v6.tm_mday = a2;\n v6.tm_hour = 0;\n v6.tm_min = 0;\n v6.tm_sec = 0;\n v6.tm_isdst = -1;\n v4 = mktime(&v6);\n result = 0;\n if (v4 != -1) {\n result = 0;\n if (v6.tm_year + 1900 == a3) {\n result = 0;\n if (v6.tm_mon + 1 == a1) return v6.tm_mday == a2;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "bool func0(int a1, int a2, int a3) {\n time_t v4;\n bool result;\n struct tm v6;\n unsigned long long v7;\n v7 = __readfsqword(40u);\n v6.tm_year = a3 - 1900;\n v6.tm_mon = a1 - 1;\n v6.tm_mday = a2;\n v6.tm_hour = 0;\n v6.tm_min = 0;\n v6.tm_sec = 0;\n v6.tm_isdst = -1;\n v4 = mktime(&v6);\n result = 0;\n if (v4 != -1) {\n result = 0;\n if (v6.tm_year + 1900 == a3) {\n result = 0;\n if (v6.tm_mon + 1 == a1) return v6.tm_mday == a2;\n }\n }\n return result;\n}" + }, + { + "index": 910, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int m, int d, int y) {\n struct tm time;\n time.tm_year = y - 1900;\n time.tm_mon = m - 1;\n time.tm_mday = d;\n time.tm_hour = 0;\n time.tm_min = 0;\n time.tm_sec = 0;\n time.tm_isdst = -1;\n if (mktime(&time) == -1) {\n return false;\n } else {\n if (time.tm_year + 1900 != y || time.tm_mon + 1 != m || time.tm_mday != d) {\n return false;\n }\n return true;\n }\n}", + "test": "int main() {\n\n assert(func0(11,11,2002) == true);\n\n assert(func0(13,11,2002) == false);\n\n assert(func0(11,11,2002) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %esi,%r12d\npush %rbp\nmov %edi,%ebp\npush %rbx\nmov %edx,%ebx\nsub $0x40,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x38(%rsp)\nxor %eax,%eax\nlea -0x76c(%rdx),%eax\nmov %esi,0xc(%rsp)\nmov %eax,0x14(%rsp)\nlea -0x1(%rdi),%eax\nmov %rsp,%rdi\nmov %eax,0x10(%rsp)\nmovq $0x0,(%rsp)\nmovl $0x0,0x8(%rsp)\nmovl $0xffffffff,0x20(%rsp)\ncallq 1090 \nxor %r8d,%r8d\ncmp $0xffffffffffffffff,%rax\nje 12be \nmov 0x14(%rsp),%eax\nadd $0x76c,%eax\ncmp %ebx,%eax\nje 12e0 \nmov 0x38(%rsp),%rax\nxor %fs:0x28,%rax\njne 12f6 \nadd $0x40,%rsp\nmov %r8d,%eax\npop %rbx\npop %rbp\npop %r12\nretq\nnopw 0x0(%rax,%rax,1)\nmov 0x10(%rsp),%eax\nadd $0x1,%eax\ncmp %ebp,%eax\njne 12be \ncmp %r12d,0xc(%rsp)\nsete %r8b\njmp 12be \ncallq 1070 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r12\nmov r12d, esi\npush rbp\nmov ebp, edi\npush rbx\nmov ebx, edx\nsub rsp, 40h\nmov rax, fs:28h\nmov [rsp+58h+var_20], rax\nxor eax, eax\nlea eax, [rdx-76Ch]\nmov [rsp+58h+var_4C], esi\nmov [rsp+58h+var_44], eax\nlea eax, [rdi-1]\nmov rdi, rsp; tp\nmov [rsp+58h+var_48], eax\nmov [rsp+58h+var_50], 0\nmov [rsp+58h+var_58], 0\nmov [rsp+58h+var_38], 0FFFFFFFFh\ncall _mktime\nxor edx, edx\ncmp rax, 0FFFFFFFFFFFFFFFFh\njz short loc_12BD\nmov eax, [rsp+58h+var_44]\nadd eax, 76Ch\ncmp eax, ebx\njz short loc_12E0\nloc_12BD:\nmov rax, [rsp+58h+var_20]\nsub rax, fs:28h\njnz short loc_12F5\nadd rsp, 40h\nmov eax, edx\npop rbx\npop rbp\npop r12\nretn\nloc_12E0:\nmov eax, [rsp+58h+var_48]\nadd eax, 1\ncmp eax, ebp\njnz short loc_12BD\ncmp [rsp+58h+var_4C], r12d\nsetz dl\njmp short loc_12BD\nloc_12F5:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, int a3)\n{\n time_t v4; // rax\n unsigned int v5; // edx\n struct tm v7; // [rsp+0h] [rbp-58h] BYREF\n unsigned __int64 v8; // [rsp+38h] [rbp-20h]\n\n v8 = __readfsqword(0x28u);\n v7.tm_mday = a2;\n v7.tm_year = a3 - 1900;\n v7.tm_mon = a1 - 1;\n v7.tm_hour = 0;\n *(_QWORD *)&v7.tm_sec = 0LL;\n v7.tm_isdst = -1;\n v4 = mktime(&v7);\n v5 = 0;\n if ( v4 != -1 && v7.tm_year + 1900 == a3 && v7.tm_mon + 1 == a1 )\n LOBYTE(v5) = v7.tm_mday == a2;\n return v5;\n}", + "ida_strip_asm": "sub_1250:\nendbr64\npush r12\nmov r12d, esi\npush rbp\nmov ebp, edi\npush rbx\nmov ebx, edx\nsub rsp, 40h\nmov rax, fs:28h\nmov [rsp+58h+var_20], rax\nxor eax, eax\nlea eax, [rdx-76Ch]\nmov [rsp+58h+var_4C], esi\nmov [rsp+58h+var_44], eax\nlea eax, [rdi-1]\nmov rdi, rsp; tp\nmov [rsp+58h+var_48], eax\nmov [rsp+58h+var_50], 0\nmov [rsp+58h+var_58], 0\nmov [rsp+58h+var_38], 0FFFFFFFFh\ncall _mktime\nxor edx, edx\ncmp rax, 0FFFFFFFFFFFFFFFFh\njz short loc_12BD\nmov eax, [rsp+58h+var_44]\nadd eax, 76Ch\ncmp eax, ebx\njz short loc_12E0\nloc_12BD:\nmov rax, [rsp+58h+var_20]\nsub rax, fs:28h\njnz short loc_12F5\nadd rsp, 40h\nmov eax, edx\npop rbx\npop rbp\npop r12\nretn\nloc_12E0:\nmov eax, [rsp+58h+var_48]\nadd eax, 1\ncmp eax, ebp\njnz short loc_12BD\ncmp [rsp+58h+var_4C], r12d\nsetz dl\njmp short loc_12BD\nloc_12F5:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1250(int a1, int a2, int a3)\n{\n time_t v4; // rax\n unsigned int v5; // edx\n struct tm v7; // [rsp+0h] [rbp-58h] BYREF\n unsigned __int64 v8; // [rsp+38h] [rbp-20h]\n\n v8 = __readfsqword(0x28u);\n v7.tm_mday = a2;\n v7.tm_year = a3 - 1900;\n v7.tm_mon = a1 - 1;\n v7.tm_hour = 0;\n *(_QWORD *)&v7.tm_sec = 0LL;\n v7.tm_isdst = -1;\n v4 = mktime(&v7);\n v5 = 0;\n if ( v4 != -1 && v7.tm_year + 1900 == a3 && v7.tm_mon + 1 == a1 )\n LOBYTE(v5) = v7.tm_mday == a2;\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1250(int a1, int a2, int a3) {\n time_t v4;\n unsigned int v5;\n struct tm v7;\n unsigned long long v8;\n v8 = __readfsqword(40u);\n v7.tm_mday = a2;\n v7.tm_year = a3 - 1900;\n v7.tm_mon = a1 - 1;\n v7.tm_hour = 0;\n *(uint64_t *)&v7.tm_sec = 0LL;\n v7.tm_isdst = -1;\n v4 = mktime(&v7);\n v5 = 0;\n if (v4 != -1 && v7.tm_year + 1900 == a3 && v7.tm_mon + 1 == a1)\n LOBYTE(v5) = v7.tm_mday == a2;\n return v5;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, int a3) {\n time_t v4;\n unsigned int v5;\n struct tm v7;\n unsigned long long v8;\n v8 = __readfsqword(40u);\n v7.tm_mday = a2;\n v7.tm_year = a3 - 1900;\n v7.tm_mon = a1 - 1;\n v7.tm_hour = 0;\n *(uint64_t *)&v7.tm_sec = 0LL;\n v7.tm_isdst = -1;\n v4 = mktime(&v7);\n v5 = 0;\n if (v4 != -1 && v7.tm_year + 1900 == a3 && v7.tm_mon + 1 == a1)\n LOBYTE(v5) = v7.tm_mday == a2;\n return v5;\n}" + }, + { + "index": 910, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int m, int d, int y) {\n struct tm time;\n time.tm_year = y - 1900;\n time.tm_mon = m - 1;\n time.tm_mday = d;\n time.tm_hour = 0;\n time.tm_min = 0;\n time.tm_sec = 0;\n time.tm_isdst = -1;\n if (mktime(&time) == -1) {\n return false;\n } else {\n if (time.tm_year + 1900 != y || time.tm_mon + 1 != m || time.tm_mday != d) {\n return false;\n }\n return true;\n }\n}", + "test": "int main() {\n\n assert(func0(11,11,2002) == true);\n\n assert(func0(13,11,2002) == false);\n\n assert(func0(11,11,2002) == true);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %esi,%r12d\npush %rbp\nmov %edi,%ebp\npush %rbx\nmov %edx,%ebx\nsub $0x40,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x38(%rsp)\nxor %eax,%eax\nlea -0x76c(%rdx),%eax\nmov %esi,0xc(%rsp)\nmov %eax,0x14(%rsp)\nlea -0x1(%rdi),%eax\nmov %rsp,%rdi\nmov %eax,0x10(%rsp)\nmovq $0x0,(%rsp)\nmovl $0x0,0x8(%rsp)\nmovl $0xffffffff,0x20(%rsp)\ncallq 1090 \nxor %r8d,%r8d\ncmp $0xffffffffffffffff,%rax\nje 12be \nmov 0x14(%rsp),%eax\nadd $0x76c,%eax\ncmp %ebx,%eax\nje 12e0 \nmov 0x38(%rsp),%rax\nxor %fs:0x28,%rax\njne 12f6 \nadd $0x40,%rsp\nmov %r8d,%eax\npop %rbx\npop %rbp\npop %r12\nretq\nnopw 0x0(%rax,%rax,1)\nmov 0x10(%rsp),%eax\nadd $0x1,%eax\ncmp %ebp,%eax\njne 12be \ncmp %r12d,0xc(%rsp)\nsete %r8b\njmp 12be \ncallq 1070 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r12\nmov r12d, esi\npush rbp\nmov ebp, edi\npush rbx\nmov ebx, edx\nsub rsp, 40h\nmov rax, fs:28h\nmov [rsp+58h+var_20], rax\nxor eax, eax\nlea eax, [rdx-76Ch]\nmov [rsp+58h+var_4C], esi\nmov [rsp+58h+var_44], eax\nlea eax, [rdi-1]\nmov rdi, rsp; tp\nmov [rsp+58h+var_48], eax\nmov [rsp+58h+var_50], 0\nmov [rsp+58h+var_58], 0\nmov [rsp+58h+var_38], 0FFFFFFFFh\ncall _mktime\nxor edx, edx\ncmp rax, 0FFFFFFFFFFFFFFFFh\njz short loc_12BD\nmov eax, [rsp+58h+var_44]\nadd eax, 76Ch\ncmp eax, ebx\njz short loc_12E0\nloc_12BD:\nmov rax, [rsp+58h+var_20]\nsub rax, fs:28h\njnz short loc_12F5\nadd rsp, 40h\nmov eax, edx\npop rbx\npop rbp\npop r12\nretn\nloc_12E0:\nmov eax, [rsp+58h+var_48]\nadd eax, 1\ncmp eax, ebp\njnz short loc_12BD\ncmp [rsp+58h+var_4C], r12d\nsetz dl\njmp short loc_12BD\nloc_12F5:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, int a3)\n{\n time_t v4; // rax\n unsigned int v5; // edx\n struct tm v7; // [rsp+0h] [rbp-58h] BYREF\n unsigned __int64 v8; // [rsp+38h] [rbp-20h]\n\n v8 = __readfsqword(0x28u);\n v7.tm_mday = a2;\n v7.tm_year = a3 - 1900;\n v7.tm_mon = a1 - 1;\n v7.tm_hour = 0;\n *(_QWORD *)&v7.tm_sec = 0LL;\n v7.tm_isdst = -1;\n v4 = mktime(&v7);\n v5 = 0;\n if ( v4 != -1 && v7.tm_year + 1900 == a3 && v7.tm_mon + 1 == a1 )\n LOBYTE(v5) = v7.tm_mday == a2;\n return v5;\n}", + "ida_strip_asm": "sub_1250:\nendbr64\npush r12\nmov r12d, esi\npush rbp\nmov ebp, edi\npush rbx\nmov ebx, edx\nsub rsp, 40h\nmov rax, fs:28h\nmov [rsp+58h+var_20], rax\nxor eax, eax\nlea eax, [rdx-76Ch]\nmov [rsp+58h+var_4C], esi\nmov [rsp+58h+var_44], eax\nlea eax, [rdi-1]\nmov rdi, rsp; tp\nmov [rsp+58h+var_48], eax\nmov [rsp+58h+var_50], 0\nmov [rsp+58h+var_58], 0\nmov [rsp+58h+var_38], 0FFFFFFFFh\ncall _mktime\nxor edx, edx\ncmp rax, 0FFFFFFFFFFFFFFFFh\njz short loc_12BD\nmov eax, [rsp+58h+var_44]\nadd eax, 76Ch\ncmp eax, ebx\njz short loc_12E0\nloc_12BD:\nmov rax, [rsp+58h+var_20]\nsub rax, fs:28h\njnz short loc_12F5\nadd rsp, 40h\nmov eax, edx\npop rbx\npop rbp\npop r12\nretn\nloc_12E0:\nmov eax, [rsp+58h+var_48]\nadd eax, 1\ncmp eax, ebp\njnz short loc_12BD\ncmp [rsp+58h+var_4C], r12d\nsetz dl\njmp short loc_12BD\nloc_12F5:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1250(int a1, int a2, int a3)\n{\n time_t v4; // rax\n unsigned int v5; // edx\n struct tm v7; // [rsp+0h] [rbp-58h] BYREF\n unsigned __int64 v8; // [rsp+38h] [rbp-20h]\n\n v8 = __readfsqword(0x28u);\n v7.tm_mday = a2;\n v7.tm_year = a3 - 1900;\n v7.tm_mon = a1 - 1;\n v7.tm_hour = 0;\n *(_QWORD *)&v7.tm_sec = 0LL;\n v7.tm_isdst = -1;\n v4 = mktime(&v7);\n v5 = 0;\n if ( v4 != -1 && v7.tm_year + 1900 == a3 && v7.tm_mon + 1 == a1 )\n LOBYTE(v5) = v7.tm_mday == a2;\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1250(int a1, int a2, int a3) {\n time_t v4;\n unsigned int v5;\n struct tm v7;\n unsigned long long v8;\n v8 = __readfsqword(40u);\n v7.tm_mday = a2;\n v7.tm_year = a3 - 1900;\n v7.tm_mon = a1 - 1;\n v7.tm_hour = 0;\n *(uint64_t *)&v7.tm_sec = 0LL;\n v7.tm_isdst = -1;\n v4 = mktime(&v7);\n v5 = 0;\n if (v4 != -1 && v7.tm_year + 1900 == a3 && v7.tm_mon + 1 == a1)\n LOBYTE(v5) = v7.tm_mday == a2;\n return v5;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, int a3) {\n time_t v4;\n unsigned int v5;\n struct tm v7;\n unsigned long long v8;\n v8 = __readfsqword(40u);\n v7.tm_mday = a2;\n v7.tm_year = a3 - 1900;\n v7.tm_mon = a1 - 1;\n v7.tm_hour = 0;\n *(uint64_t *)&v7.tm_sec = 0LL;\n v7.tm_isdst = -1;\n v4 = mktime(&v7);\n v5 = 0;\n if (v4 != -1 && v7.tm_year + 1900 == a3 && v7.tm_mon + 1 == a1)\n LOBYTE(v5) = v7.tm_mday == a2;\n return v5;\n}" + }, + { + "index": 911, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int nums[], int size) {\n int i, j, temp;\n if (size < 3) {\n return -1;\n }\n for (i = 0; i < size - 1; i++) {\n for (j = i + 1; j < size; j++) {\n if (nums[i] < nums[j]) {\n temp = nums[i];\n nums[i] = nums[j];\n nums[j] = temp;\n }\n }\n }\n int highest = nums[0];\n int second_highest = nums[1];\n int third_highest = nums[2];\n int lowest = nums[size - 1];\n int second_lowest = nums[size - 2];\n int product1 = highest * second_highest * third_highest;\n int product2 = highest * lowest * second_lowest;\n return (product1 > product2) ? product1 : product2;\n}", + "test": "int main() {\n\n int arr1[] = {12, 74, 9, 50, 61, 41};\n\n int size1 = sizeof(arr1) / sizeof(arr1[0]);\n\n assert(func0(arr1, size1) == 225700);\n\n\n\n int arr2[] = {25, 35, 22, 85, 14, 65, 75, 25, 58};\n\n int size2 = sizeof(arr2) / sizeof(arr2[0]);\n\n assert(func0(arr2, size2) == 414375);\n\n\n\n int arr3[] = {18, 14, 10, 9, 8, 7, 9, 3, 2, 4, 1};\n\n int size3 = sizeof(arr3) / sizeof(arr3[0]);\n\n assert(func0(arr3, size3) == 2520);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x38(%rbp)\nmov %esi,-0x3c(%rbp)\ncmpl $0x2,-0x3c(%rbp)\njg 1188 \nmov $0xffffffff,%eax\njmpq 12cd \nmovl $0x0,-0x28(%rbp)\njmpq 1245 \nmov -0x28(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x24(%rbp)\njmpq 1235 \nmov -0x28(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x24(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x38(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njge 1231 \nmov -0x28(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x4(%rbp)\nmov -0x24(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov -0x28(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x38(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\nmov -0x24(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x38(%rbp),%rax\nadd %rax,%rdx\nmov -0x4(%rbp),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x24(%rbp)\nmov -0x24(%rbp),%eax\ncmp -0x3c(%rbp),%eax\njl 11a2 \naddl $0x1,-0x28(%rbp)\nmov -0x3c(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x28(%rbp)\njl 1194 \nmov -0x38(%rbp),%rax\nmov (%rax),%eax\nmov %eax,-0x20(%rbp)\nmov -0x38(%rbp),%rax\nmov 0x4(%rax),%eax\nmov %eax,-0x1c(%rbp)\nmov -0x38(%rbp),%rax\nmov 0x8(%rax),%eax\nmov %eax,-0x18(%rbp)\nmov -0x3c(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x4(%rax),%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x14(%rbp)\nmov -0x3c(%rbp),%eax\ncltq\nshl $0x2,%rax\nlea -0x8(%rax),%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x10(%rbp)\nmov -0x20(%rbp),%eax\nimul -0x1c(%rbp),%eax\nmov -0x18(%rbp),%edx\nimul %edx,%eax\nmov %eax,-0xc(%rbp)\nmov -0x20(%rbp),%eax\nimul -0x14(%rbp),%eax\nmov -0x10(%rbp),%edx\nimul %edx,%eax\nmov %eax,-0x8(%rbp)\nmov -0xc(%rbp),%eax\ncmp %eax,-0x8(%rbp)\ncmovge -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\ncmp [rbp+var_3C], 2\njg short loc_1188\nmov eax, 0FFFFFFFFh\njmp loc_12CE\nloc_1188:\nmov [rbp+var_28], 0\njmp loc_1245\nloc_1194:\nmov eax, [rbp+var_28]\nadd eax, 1\nmov [rbp+var_24], eax\njmp loc_1235\nloc_11A2:\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_24]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njge short loc_1231\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_38]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nloc_1231:\nadd [rbp+var_24], 1\nloc_1235:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_3C]\njl loc_11A2\nadd [rbp+var_28], 1\nloc_1245:\nmov eax, [rbp+var_3C]\nsub eax, 1\ncmp [rbp+var_28], eax\njl loc_1194\nmov rax, [rbp+var_38]\nmov eax, [rax]\nmov [rbp+var_20], eax\nmov rax, [rbp+var_38]\nmov eax, [rax+4]\nmov [rbp+var_1C], eax\nmov rax, [rbp+var_38]\nmov eax, [rax+8]\nmov [rbp+var_18], eax\nmov eax, [rbp+var_3C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_14], eax\nmov eax, [rbp+var_3C]\ncdqe\nshl rax, 2\nlea rdx, [rax-8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_10], eax\nmov eax, [rbp+var_20]\nimul eax, [rbp+var_1C]\nmov edx, [rbp+var_18]\nimul eax, edx\nmov [rbp+var_C], eax\nmov eax, [rbp+var_20]\nimul eax, [rbp+var_14]\nmov edx, [rbp+var_10]\nimul eax, edx\nmov [rbp+var_8], eax\nmov edx, [rbp+var_8]\nmov eax, [rbp+var_C]\ncmp edx, eax\ncmovge eax, edx\nloc_12CE:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n __int64 result; // rax\n int v3; // edx\n int i; // [rsp+14h] [rbp-28h]\n int j; // [rsp+18h] [rbp-24h]\n int v6; // [rsp+38h] [rbp-4h]\n\n if ( a2 <= 2 )\n return 0xFFFFFFFFLL;\n for ( i = 0; i < a2 - 1; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( a1[i] < a1[j] )\n {\n v6 = a1[i];\n a1[i] = a1[j];\n a1[j] = v6;\n }\n }\n }\n v3 = a1[a2 - 2] * a1[a2 - 1] * *a1;\n result = (unsigned int)(a1[2] * a1[1] * *a1);\n if ( v3 >= (int)result )\n return (unsigned int)v3;\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\ncmp [rbp+var_3C], 2\njg short loc_1188\nmov eax, 0FFFFFFFFh\njmp loc_12CE\nloc_1188:\nmov [rbp+var_28], 0\njmp loc_1245\nloc_1194:\nmov eax, [rbp+var_28]\nadd eax, 1\nmov [rbp+var_24], eax\njmp loc_1235\nloc_11A2:\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_24]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njge short loc_1231\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_38]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nloc_1231:\nadd [rbp+var_24], 1\nloc_1235:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_3C]\njl loc_11A2\nadd [rbp+var_28], 1\nloc_1245:\nmov eax, [rbp+var_3C]\nsub eax, 1\ncmp [rbp+var_28], eax\njl loc_1194\nmov rax, [rbp+var_38]\nmov eax, [rax]\nmov [rbp+var_20], eax\nmov rax, [rbp+var_38]\nmov eax, [rax+4]\nmov [rbp+var_1C], eax\nmov rax, [rbp+var_38]\nmov eax, [rax+8]\nmov [rbp+var_18], eax\nmov eax, [rbp+var_3C]\ncdqe\nshl rax, 2\nlea rdx, [rax-4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_14], eax\nmov eax, [rbp+var_3C]\ncdqe\nshl rax, 2\nlea rdx, [rax-8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_10], eax\nmov eax, [rbp+var_20]\nimul eax, [rbp+var_1C]\nmov edx, [rbp+var_18]\nimul eax, edx\nmov [rbp+var_C], eax\nmov eax, [rbp+var_20]\nimul eax, [rbp+var_14]\nmov edx, [rbp+var_10]\nimul eax, edx\nmov [rbp+var_8], eax\nmov edx, [rbp+var_8]\nmov eax, [rbp+var_C]\ncmp edx, eax\ncmovge eax, edx\nloc_12CE:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2)\n{\n __int64 result; // rax\n int v3; // edx\n int i; // [rsp+14h] [rbp-28h]\n int j; // [rsp+18h] [rbp-24h]\n int v6; // [rsp+38h] [rbp-4h]\n\n if ( a2 <= 2 )\n return 0xFFFFFFFFLL;\n for ( i = 0; i < a2 - 1; ++i )\n {\n for ( j = i + 1; j < a2; ++j )\n {\n if ( a1[i] < a1[j] )\n {\n v6 = a1[i];\n a1[i] = a1[j];\n a1[j] = v6;\n }\n }\n }\n v3 = a1[a2 - 2] * a1[a2 - 1] * *a1;\n result = (unsigned int)(a1[2] * a1[1] * *a1);\n if ( v3 >= (int)result )\n return (unsigned int)v3;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2) {\n long long result;\n int v3;\n int i;\n int j;\n int v6;\n if (a2 <= 2) return 4294967295LL;\n for (i = 0; i < a2 - 1; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if (a1[i] < a1[j]) {\n v6 = a1[i];\n a1[i] = a1[j];\n a1[j] = v6;\n }\n }\n }\n v3 = a1[a2 - 2] * a1[a2 - 1] * *a1;\n result = (unsigned int)(a1[2] * a1[1] * *a1);\n if (v3 >= (int)result) return (unsigned int)v3;\n return result;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n long long result;\n int v3;\n int i;\n int j;\n int v6;\n if (a2 <= 2) return 4294967295LL;\n for (i = 0; i < a2 - 1; ++i) {\n for (j = i + 1; j < a2; ++j) {\n if (a1[i] < a1[j]) {\n v6 = a1[i];\n a1[i] = a1[j];\n a1[j] = v6;\n }\n }\n }\n v3 = a1[a2 - 2] * a1[a2 - 1] * *a1;\n result = (unsigned int)(a1[2] * a1[1] * *a1);\n if (v3 >= (int)result) return (unsigned int)v3;\n return result;\n}" + }, + { + "index": 911, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int nums[], int size) {\n int i, j, temp;\n if (size < 3) {\n return -1;\n }\n for (i = 0; i < size - 1; i++) {\n for (j = i + 1; j < size; j++) {\n if (nums[i] < nums[j]) {\n temp = nums[i];\n nums[i] = nums[j];\n nums[j] = temp;\n }\n }\n }\n int highest = nums[0];\n int second_highest = nums[1];\n int third_highest = nums[2];\n int lowest = nums[size - 1];\n int second_lowest = nums[size - 2];\n int product1 = highest * second_highest * third_highest;\n int product2 = highest * lowest * second_lowest;\n return (product1 > product2) ? product1 : product2;\n}", + "test": "int main() {\n\n int arr1[] = {12, 74, 9, 50, 61, 41};\n\n int size1 = sizeof(arr1) / sizeof(arr1[0]);\n\n assert(func0(arr1, size1) == 225700);\n\n\n\n int arr2[] = {25, 35, 22, 85, 14, 65, 75, 25, 58};\n\n int size2 = sizeof(arr2) / sizeof(arr2[0]);\n\n assert(func0(arr2, size2) == 414375);\n\n\n\n int arr3[] = {18, 14, 10, 9, 8, 7, 9, 3, 2, 4, 1};\n\n int size3 = sizeof(arr3) / sizeof(arr3[0]);\n\n assert(func0(arr3, size3) == 2520);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x2,%esi\njle 11d5 \nmov %rdi,%r8\nlea -0x2(%rsi),%r10d\nadd $0x2,%r10\nmov $0x1,%r9d\njmp 11ac \nadd $0x1,%rax\ncmp %eax,%esi\njle 119f \nmov (%r8),%edx\nmov (%rdi,%rax,4),%ecx\ncmp %ecx,%edx\njge 1185 \nmov %ecx,(%r8)\nmov %edx,(%rdi,%rax,4)\njmp 1185 \nadd $0x1,%r9\nadd $0x4,%r8\ncmp %r10,%r9\nje 11b6 \ncmp %r9d,%esi\njle 119f \nmov %r9,%rax\njmp 118d \nmov (%rdi),%eax\nmovslq %esi,%rsi\nmov %eax,%edx\nimul -0x4(%rdi,%rsi,4),%edx\nimul -0x8(%rdi,%rsi,4),%edx\nimul 0x4(%rdi),%eax\nimul 0x8(%rdi),%eax\ncmp %eax,%edx\ncmovge %edx,%eax\nretq\nmov $0xffffffff,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ncmp esi, 2\njle short loc_11F1\npush rbp\npush rbx\nmov r10, rdi\nlea rdi, [rdi+4]\nmov r11d, esi\nmov r9d, 1\nlea ebp, [rsi-1]\nlea rbx, [r10+8]\njmp short loc_11B3\nloc_118D:\nadd rax, 4\ncmp rax, r8\njz short loc_11A6\nloc_1196:\nmov edx, [rdi-4]\nmov ecx, [rax]\ncmp edx, ecx\njge short loc_118D\nmov [rdi-4], ecx\nmov [rax], edx\njmp short loc_118D\nloc_11A6:\nadd r9, 1\nadd rdi, 4\ncmp r9, r11\njz short loc_11CB\nloc_11B3:\ncmp esi, r9d\njle short loc_11A6\nmov eax, ebp\nsub eax, r9d\nlea rax, [r9+rax-1]\nlea r8, [rbx+rax*4]\nmov rax, rdi\njmp short loc_1196\nloc_11CB:\nmov eax, [r10]\nmovsxd rsi, esi\nmov edx, eax\nimul edx, [r10+rsi*4-4]\nimul edx, [r10+rsi*4-8]\nimul eax, [r10+4]\nimul eax, [r10+8]\ncmp edx, eax\ncmovge eax, edx\npop rbx\npop rbp\nretn\nloc_11F1:\nmov eax, 0FFFFFFFFh\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v3; // rdi\n __int64 i; // r9\n _DWORD *v5; // rax\n int v6; // edx\n int v7; // edx\n __int64 result; // rax\n\n if ( a2 <= 2 )\n return 0xFFFFFFFFLL;\n v3 = a1 + 1;\n for ( i = 1LL; i != a2; ++i )\n {\n if ( a2 > (int)i )\n {\n v5 = v3;\n do\n {\n v6 = *(v3 - 1);\n if ( v6 < *v5 )\n {\n *(v3 - 1) = *v5;\n *v5 = v6;\n }\n ++v5;\n }\n while ( v5 != &a1[i + 1 + (unsigned int)(a2 - 1 - i)] );\n }\n ++v3;\n }\n v7 = a1[a2 - 2] * a1[a2 - 1] * *a1;\n result = (unsigned int)(a1[2] * a1[1] * *a1);\n if ( v7 >= (int)result )\n return (unsigned int)v7;\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ncmp esi, 2\njle short loc_11F1\npush rbp\npush rbx\nmov r10, rdi\nlea rdi, [rdi+4]\nmov r11d, esi\nmov r9d, 1\nlea ebp, [rsi-1]\nlea rbx, [r10+8]\njmp short loc_11B3\nloc_118D:\nadd rax, 4\ncmp rax, r8\njz short loc_11A6\nloc_1196:\nmov edx, [rdi-4]\nmov ecx, [rax]\ncmp edx, ecx\njge short loc_118D\nmov [rdi-4], ecx\nmov [rax], edx\njmp short loc_118D\nloc_11A6:\nadd r9, 1\nadd rdi, 4\ncmp r9, r11\njz short loc_11CB\nloc_11B3:\ncmp esi, r9d\njle short loc_11A6\nmov eax, ebp\nsub eax, r9d\nlea rax, [r9+rax-1]\nlea r8, [rbx+rax*4]\nmov rax, rdi\njmp short loc_1196\nloc_11CB:\nmov eax, [r10]\nmovsxd rsi, esi\nmov edx, eax\nimul edx, [r10+rsi*4-4]\nimul edx, [r10+rsi*4-8]\nimul eax, [r10+4]\nimul eax, [r10+8]\ncmp edx, eax\ncmovge eax, edx\npop rbx\npop rbp\nretn\nloc_11F1:\nmov eax, 0FFFFFFFFh\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2)\n{\n _DWORD *v3; // rdi\n __int64 i; // r9\n _DWORD *v5; // rax\n int v6; // edx\n int v7; // edx\n __int64 result; // rax\n\n if ( a2 <= 2 )\n return 0xFFFFFFFFLL;\n v3 = a1 + 1;\n for ( i = 1LL; i != a2; ++i )\n {\n if ( a2 > (int)i )\n {\n v5 = v3;\n do\n {\n v6 = *(v3 - 1);\n if ( v6 < *v5 )\n {\n *(v3 - 1) = *v5;\n *v5 = v6;\n }\n ++v5;\n }\n while ( v5 != &a1[i + 1 + (unsigned int)(a2 - 1 - i)] );\n }\n ++v3;\n }\n v7 = a1[a2 - 2] * a1[a2 - 1] * *a1;\n result = (unsigned int)(a1[2] * a1[1] * *a1);\n if ( v7 >= (int)result )\n return (unsigned int)v7;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2) {\n uint32_t *v3;\n long long i;\n uint32_t *v5;\n int v6;\n int v7;\n long long result;\n if (a2 <= 2) return 4294967295LL;\n v3 = a1 + 1;\n for (i = 1LL; i != a2; ++i) {\n if (a2 > (int)i) {\n v5 = v3;\n do {\n v6 = *(v3 - 1);\n if (v6 < *v5) {\n *(v3 - 1) = *v5;\n *v5 = v6;\n }\n ++v5;\n } while (v5 != &a1[i + 1 + (unsigned int)(a2 - 1 - i)]);\n }\n ++v3;\n }\n v7 = a1[a2 - 2] * a1[a2 - 1] * *a1;\n result = (unsigned int)(a1[2] * a1[1] * *a1);\n if (v7 >= (int)result) return (unsigned int)v7;\n return result;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n uint32_t *v3;\n long long i;\n uint32_t *v5;\n int v6;\n int v7;\n long long result;\n if (a2 <= 2) return 4294967295LL;\n v3 = a1 + 1;\n for (i = 1LL; i != a2; ++i) {\n if (a2 > (int)i) {\n v5 = v3;\n do {\n v6 = *(v3 - 1);\n if (v6 < *v5) {\n *(v3 - 1) = *v5;\n *v5 = v6;\n }\n ++v5;\n } while (v5 != &a1[i + 1 + (unsigned int)(a2 - 1 - i)]);\n }\n ++v3;\n }\n v7 = a1[a2 - 2] * a1[a2 - 1] * *a1;\n result = (unsigned int)(a1[2] * a1[1] * *a1);\n if (v7 >= (int)result) return (unsigned int)v7;\n return result;\n}" + }, + { + "index": 911, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int nums[], int size) {\n int i, j, temp;\n if (size < 3) {\n return -1;\n }\n for (i = 0; i < size - 1; i++) {\n for (j = i + 1; j < size; j++) {\n if (nums[i] < nums[j]) {\n temp = nums[i];\n nums[i] = nums[j];\n nums[j] = temp;\n }\n }\n }\n int highest = nums[0];\n int second_highest = nums[1];\n int third_highest = nums[2];\n int lowest = nums[size - 1];\n int second_lowest = nums[size - 2];\n int product1 = highest * second_highest * third_highest;\n int product2 = highest * lowest * second_lowest;\n return (product1 > product2) ? product1 : product2;\n}", + "test": "int main() {\n\n int arr1[] = {12, 74, 9, 50, 61, 41};\n\n int size1 = sizeof(arr1) / sizeof(arr1[0]);\n\n assert(func0(arr1, size1) == 225700);\n\n\n\n int arr2[] = {25, 35, 22, 85, 14, 65, 75, 25, 58};\n\n int size2 = sizeof(arr2) / sizeof(arr2[0]);\n\n assert(func0(arr2, size2) == 414375);\n\n\n\n int arr3[] = {18, 14, 10, 9, 8, 7, 9, 3, 2, 4, 1};\n\n int size3 = sizeof(arr3) / sizeof(arr3[0]);\n\n assert(func0(arr3, size3) == 2520);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x2,%esi\njle 13a0 \njmp 1320 \nnopl 0x0(%rax,%rax,1)\nmov $0xffffffff,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0_part_0:\npush rbp\nmov r10, rdi\npush rbx\ncmp esi, 1\njle short loc_1324\nlea rdi, [rdi+4]\nmov r11d, esi\nlea ebp, [rsi-1]\nmov r9d, 1\nlea rbx, [r10+8]\nxchg ax, ax\nloc_12E0:\ncmp esi, r9d\njle short loc_1317\nmov eax, ebp\nsub eax, r9d\nlea rax, [r9+rax-1]\nlea r8, [rbx+rax*4]\nmov rax, rdi\nnop word ptr [rax+rax+00000000h]\nloc_1300:\nmov edx, [rdi-4]\nmov ecx, [rax]\ncmp edx, ecx\njge short loc_130E\nmov [rdi-4], ecx\nmov [rax], edx\nloc_130E:\nadd rax, 4\ncmp r8, rax\njnz short loc_1300\nloc_1317:\nadd r9, 1\nadd rdi, 4\ncmp r11, r9\njnz short loc_12E0\nloc_1324:\nmovsxd rsi, esi\nmov eax, [r10]\npop rbx\nmov edx, [r10+rsi*4-4]\npop rbp\nimul edx, eax\nimul eax, [r10+4]\nimul edx, [r10+rsi*4-8]\nimul eax, [r10+8]\ncmp edx, eax\ncmovge eax, edx\nretn", + "ida_pseudo": "__int64 __fastcall func0_part_0(_DWORD *a1, int a2)\n{\n _DWORD *v3; // rdi\n __int64 i; // r9\n _DWORD *v5; // rax\n int v6; // edx\n int v7; // edx\n __int64 result; // rax\n\n if ( a2 > 1 )\n {\n v3 = a1 + 1;\n for ( i = 1LL; i != a2; ++i )\n {\n if ( a2 > (int)i )\n {\n v5 = v3;\n do\n {\n v6 = *(v3 - 1);\n if ( v6 < *v5 )\n {\n *(v3 - 1) = *v5;\n *v5 = v6;\n }\n ++v5;\n }\n while ( &a1[i + 1 + (unsigned int)(a2 - 1 - i)] != v5 );\n }\n ++v3;\n }\n }\n v7 = a1[a2 - 2] * *a1 * a1[a2 - 1];\n result = (unsigned int)(a1[2] * a1[1] * *a1);\n if ( v7 >= (int)result )\n return (unsigned int)v7;\n return result;\n}", + "ida_strip_asm": "sub_12C0:\npush rbp\nmov r10, rdi\npush rbx\ncmp esi, 1\njle short loc_1324\nlea rdi, [rdi+4]\nmov r11d, esi\nlea ebp, [rsi-1]\nmov r9d, 1\nlea rbx, [r10+8]\nxchg ax, ax\nloc_12E0:\ncmp esi, r9d\njle short loc_1317\nmov eax, ebp\nsub eax, r9d\nlea rax, [r9+rax-1]\nlea r8, [rbx+rax*4]\nmov rax, rdi\nnop word ptr [rax+rax+00000000h]\nloc_1300:\nmov edx, [rdi-4]\nmov ecx, [rax]\ncmp edx, ecx\njge short loc_130E\nmov [rdi-4], ecx\nmov [rax], edx\nloc_130E:\nadd rax, 4\ncmp r8, rax\njnz short loc_1300\nloc_1317:\nadd r9, 1\nadd rdi, 4\ncmp r11, r9\njnz short loc_12E0\nloc_1324:\nmovsxd rsi, esi\nmov eax, [r10]\npop rbx\nmov edx, [r10+rsi*4-4]\npop rbp\nimul edx, eax\nimul eax, [r10+4]\nimul edx, [r10+rsi*4-8]\nimul eax, [r10+8]\ncmp edx, eax\ncmovge eax, edx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12C0(_DWORD *a1, int a2)\n{\n _DWORD *v3; // rdi\n __int64 i; // r9\n _DWORD *v5; // rax\n int v6; // edx\n int v7; // edx\n __int64 result; // rax\n\n if ( a2 > 1 )\n {\n v3 = a1 + 1;\n for ( i = 1LL; i != a2; ++i )\n {\n if ( a2 > (int)i )\n {\n v5 = v3;\n do\n {\n v6 = *(v3 - 1);\n if ( v6 < *v5 )\n {\n *(v3 - 1) = *v5;\n *v5 = v6;\n }\n ++v5;\n }\n while ( &a1[i + 1 + (unsigned int)(a2 - 1 - i)] != v5 );\n }\n ++v3;\n }\n }\n v7 = a1[a2 - 2] * *a1 * a1[a2 - 1];\n result = (unsigned int)(a1[2] * a1[1] * *a1);\n if ( v7 >= (int)result )\n return (unsigned int)v7;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12C0(uint32_t *a1, int a2) {\n uint32_t *v3;\n long long i;\n uint32_t *v5;\n int v6;\n int v7;\n long long result;\n if (a2 > 1) {\n v3 = a1 + 1;\n for (i = 1LL; i != a2; ++i) {\n if (a2 > (int)i) {\n v5 = v3;\n do {\n v6 = *(v3 - 1);\n if (v6 < *v5) {\n *(v3 - 1) = *v5;\n *v5 = v6;\n }\n ++v5;\n } while (&a1[i + 1 + (unsigned int)(a2 - 1 - i)] != v5);\n }\n ++v3;\n }\n }\n v7 = a1[a2 - 2] * *a1 * a1[a2 - 1];\n result = (unsigned int)(a1[2] * a1[1] * *a1);\n if (v7 >= (int)result) return (unsigned int)v7;\n return result;\n}", + "ida_pseudo_norm": "long long func0_part_0(uint32_t *a1, int a2) {\n uint32_t *v3;\n long long i;\n uint32_t *v5;\n int v6;\n int v7;\n long long result;\n if (a2 > 1) {\n v3 = a1 + 1;\n for (i = 1LL; i != a2; ++i) {\n if (a2 > (int)i) {\n v5 = v3;\n do {\n v6 = *(v3 - 1);\n if (v6 < *v5) {\n *(v3 - 1) = *v5;\n *v5 = v6;\n }\n ++v5;\n } while (&a1[i + 1 + (unsigned int)(a2 - 1 - i)] != v5);\n }\n ++v3;\n }\n }\n v7 = a1[a2 - 2] * *a1 * a1[a2 - 1];\n result = (unsigned int)(a1[2] * a1[1] * *a1);\n if (v7 >= (int)result) return (unsigned int)v7;\n return result;\n}" + }, + { + "index": 911, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int nums[], int size) {\n int i, j, temp;\n if (size < 3) {\n return -1;\n }\n for (i = 0; i < size - 1; i++) {\n for (j = i + 1; j < size; j++) {\n if (nums[i] < nums[j]) {\n temp = nums[i];\n nums[i] = nums[j];\n nums[j] = temp;\n }\n }\n }\n int highest = nums[0];\n int second_highest = nums[1];\n int third_highest = nums[2];\n int lowest = nums[size - 1];\n int second_lowest = nums[size - 2];\n int product1 = highest * second_highest * third_highest;\n int product2 = highest * lowest * second_lowest;\n return (product1 > product2) ? product1 : product2;\n}", + "test": "int main() {\n\n int arr1[] = {12, 74, 9, 50, 61, 41};\n\n int size1 = sizeof(arr1) / sizeof(arr1[0]);\n\n assert(func0(arr1, size1) == 225700);\n\n\n\n int arr2[] = {25, 35, 22, 85, 14, 65, 75, 25, 58};\n\n int size2 = sizeof(arr2) / sizeof(arr2[0]);\n\n assert(func0(arr2, size2) == 414375);\n\n\n\n int arr3[] = {18, 14, 10, 9, 8, 7, 9, 3, 2, 4, 1};\n\n int size3 = sizeof(arr3) / sizeof(arr3[0]);\n\n assert(func0(arr3, size3) == 2520);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x2,%esi\njle 13b4 \nlea -0x2(%rsi),%r10d\nmov %rdi,%r8\nmov $0x1,%r9d\nadd $0x2,%r10\nnopw 0x0(%rax,%rax,1)\ncmp %r9d,%esi\njle 1388 \nmov %r9,%rax\nnopl 0x0(%rax,%rax,1)\nmov (%r8),%edx\nmov (%rdi,%rax,4),%ecx\ncmp %ecx,%edx\njge 1380 \nmov %ecx,(%r8)\nmov %edx,(%rdi,%rax,4)\nadd $0x1,%rax\ncmp %eax,%esi\njg 1370 \nadd $0x1,%r9\nadd $0x4,%r8\ncmp %r9,%r10\njne 1360 \nmovslq %esi,%rsi\nmov (%rdi),%eax\nmov -0x4(%rdi,%rsi,4),%edx\nimul %eax,%edx\nimul 0x4(%rdi),%eax\nimul -0x8(%rdi,%rsi,4),%edx\nimul 0x8(%rdi),%eax\ncmp %eax,%edx\ncmovge %edx,%eax\nretq\nmov $0xffffffff,%eax\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0_part_0:\npush rbp\nmov r10, rdi\npush rbx\ncmp esi, 1\njle short loc_1324\nlea rdi, [rdi+4]\nmov r11d, esi\nlea ebp, [rsi-1]\nmov r9d, 1\nlea rbx, [r10+8]\nxchg ax, ax\nloc_12E0:\ncmp esi, r9d\njle short loc_1317\nmov eax, ebp\nsub eax, r9d\nlea rax, [r9+rax-1]\nlea r8, [rbx+rax*4]\nmov rax, rdi\nnop word ptr [rax+rax+00000000h]\nloc_1300:\nmov edx, [rdi-4]\nmov ecx, [rax]\ncmp edx, ecx\njge short loc_130E\nmov [rdi-4], ecx\nmov [rax], edx\nloc_130E:\nadd rax, 4\ncmp r8, rax\njnz short loc_1300\nloc_1317:\nadd r9, 1\nadd rdi, 4\ncmp r11, r9\njnz short loc_12E0\nloc_1324:\nmovsxd rsi, esi\nmov eax, [r10]\npop rbx\nmov edx, [r10+rsi*4-4]\npop rbp\nimul edx, eax\nimul eax, [r10+4]\nimul edx, [r10+rsi*4-8]\nimul eax, [r10+8]\ncmp edx, eax\ncmovge eax, edx\nretn", + "ida_pseudo": "__int64 __fastcall func0_part_0(_DWORD *a1, int a2)\n{\n _DWORD *v3; // rdi\n __int64 i; // r9\n _DWORD *v5; // rax\n int v6; // edx\n int v7; // edx\n __int64 result; // rax\n\n if ( a2 > 1 )\n {\n v3 = a1 + 1;\n for ( i = 1LL; i != a2; ++i )\n {\n if ( a2 > (int)i )\n {\n v5 = v3;\n do\n {\n v6 = *(v3 - 1);\n if ( v6 < *v5 )\n {\n *(v3 - 1) = *v5;\n *v5 = v6;\n }\n ++v5;\n }\n while ( &a1[i + 1 + (unsigned int)(a2 - 1 - i)] != v5 );\n }\n ++v3;\n }\n }\n v7 = a1[a2 - 2] * *a1 * a1[a2 - 1];\n result = (unsigned int)(a1[2] * a1[1] * *a1);\n if ( v7 >= (int)result )\n return (unsigned int)v7;\n return result;\n}", + "ida_strip_asm": "sub_12C0:\npush rbp\nmov r10, rdi\npush rbx\ncmp esi, 1\njle short loc_1324\nlea rdi, [rdi+4]\nmov r11d, esi\nlea ebp, [rsi-1]\nmov r9d, 1\nlea rbx, [r10+8]\nxchg ax, ax\nloc_12E0:\ncmp esi, r9d\njle short loc_1317\nmov eax, ebp\nsub eax, r9d\nlea rax, [r9+rax-1]\nlea r8, [rbx+rax*4]\nmov rax, rdi\nnop word ptr [rax+rax+00000000h]\nloc_1300:\nmov edx, [rdi-4]\nmov ecx, [rax]\ncmp edx, ecx\njge short loc_130E\nmov [rdi-4], ecx\nmov [rax], edx\nloc_130E:\nadd rax, 4\ncmp r8, rax\njnz short loc_1300\nloc_1317:\nadd r9, 1\nadd rdi, 4\ncmp r11, r9\njnz short loc_12E0\nloc_1324:\nmovsxd rsi, esi\nmov eax, [r10]\npop rbx\nmov edx, [r10+rsi*4-4]\npop rbp\nimul edx, eax\nimul eax, [r10+4]\nimul edx, [r10+rsi*4-8]\nimul eax, [r10+8]\ncmp edx, eax\ncmovge eax, edx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12C0(_DWORD *a1, int a2)\n{\n _DWORD *v3; // rdi\n __int64 i; // r9\n _DWORD *v5; // rax\n int v6; // edx\n int v7; // edx\n __int64 result; // rax\n\n if ( a2 > 1 )\n {\n v3 = a1 + 1;\n for ( i = 1LL; i != a2; ++i )\n {\n if ( a2 > (int)i )\n {\n v5 = v3;\n do\n {\n v6 = *(v3 - 1);\n if ( v6 < *v5 )\n {\n *(v3 - 1) = *v5;\n *v5 = v6;\n }\n ++v5;\n }\n while ( &a1[i + 1 + (unsigned int)(a2 - 1 - i)] != v5 );\n }\n ++v3;\n }\n }\n v7 = a1[a2 - 2] * *a1 * a1[a2 - 1];\n result = (unsigned int)(a1[2] * a1[1] * *a1);\n if ( v7 >= (int)result )\n return (unsigned int)v7;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12C0(uint32_t *a1, int a2) {\n uint32_t *v3;\n long long i;\n uint32_t *v5;\n int v6;\n int v7;\n long long result;\n if (a2 > 1) {\n v3 = a1 + 1;\n for (i = 1LL; i != a2; ++i) {\n if (a2 > (int)i) {\n v5 = v3;\n do {\n v6 = *(v3 - 1);\n if (v6 < *v5) {\n *(v3 - 1) = *v5;\n *v5 = v6;\n }\n ++v5;\n } while (&a1[i + 1 + (unsigned int)(a2 - 1 - i)] != v5);\n }\n ++v3;\n }\n }\n v7 = a1[a2 - 2] * *a1 * a1[a2 - 1];\n result = (unsigned int)(a1[2] * a1[1] * *a1);\n if (v7 >= (int)result) return (unsigned int)v7;\n return result;\n}", + "ida_pseudo_norm": "long long func0_part_0(uint32_t *a1, int a2) {\n uint32_t *v3;\n long long i;\n uint32_t *v5;\n int v6;\n int v7;\n long long result;\n if (a2 > 1) {\n v3 = a1 + 1;\n for (i = 1LL; i != a2; ++i) {\n if (a2 > (int)i) {\n v5 = v3;\n do {\n v6 = *(v3 - 1);\n if (v6 < *v5) {\n *(v3 - 1) = *v5;\n *v5 = v6;\n }\n ++v5;\n } while (&a1[i + 1 + (unsigned int)(a2 - 1 - i)] != v5);\n }\n ++v3;\n }\n }\n v7 = a1[a2 - 2] * *a1 * a1[a2 - 1];\n result = (unsigned int)(a1[2] * a1[1] * *a1);\n if (v7 >= (int)result) return (unsigned int)v7;\n return result;\n}" + }, + { + "index": 912, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nint binomial_coeff(int n, int k) {\n\n int C[n + 1][k + 1];\n\n for (int i = 0; i <= n; i++) {\n\n for (int j = 0; j <= (i < k ? i : k); j++) {\n\n if (j == 0 || j == i) {\n\n C[i][j] = 1;\n\n } else {\n\n C[i][j] = C[i - 1][j - 1] + C[i - 1][j];\n\n }\n\n }\n\n }\n\n return C[n][k];\n\n}\n\n\n\n", + "func": "int func0(int n, int m) {\n int numerator = (2 * m + 1) * binomial_coeff(2 * n, m + n);\n int denominator = m + n + 1;\n return numerator / denominator;\n}", + "test": "int main() {\n\n assert(func0(5, 3) == 35);\n\n assert(func0(3, 2) == 5);\n\n assert(func0(4, 2) == 20);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x28,%rsp\nmov %edi,-0x24(%rbp)\nmov %esi,-0x28(%rbp)\nmov -0x28(%rbp),%eax\nadd %eax,%eax\nlea 0x1(%rax),%ebx\nmov -0x28(%rbp),%edx\nmov -0x24(%rbp),%eax\nadd %eax,%edx\nmov -0x24(%rbp),%eax\nadd %eax,%eax\nmov %edx,%esi\nmov %eax,%edi\ncallq 1169 \nimul %ebx,%eax\nmov %eax,-0x18(%rbp)\nmov -0x28(%rbp),%edx\nmov -0x24(%rbp),%eax\nadd %edx,%eax\nadd $0x1,%eax\nmov %eax,-0x14(%rbp)\nmov -0x18(%rbp),%eax\ncltd\nidivl -0x14(%rbp)\nadd $0x28,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+var_24], edi\nmov [rbp+var_28], esi\nmov eax, [rbp+var_28]\nadd eax, eax\nlea ebx, [rax+1]\nmov edx, [rbp+var_28]\nmov eax, [rbp+var_24]\nadd edx, eax\nmov eax, [rbp+var_24]\nadd eax, eax\nmov esi, edx\nmov edi, eax\ncall binomial_coeff\nimul eax, ebx\nmov [rbp+var_18], eax\nmov edx, [rbp+var_28]\nmov eax, [rbp+var_24]\nadd eax, edx\nadd eax, 1\nmov [rbp+var_14], eax\nmov eax, [rbp+var_18]\ncdq\nidiv [rbp+var_14]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n return (unsigned int)((int)((2 * a2 + 1) * binomial_coeff((unsigned int)(2 * a1), (unsigned int)(a1 + a2)))\n / (a2 + a1 + 1));\n}", + "ida_strip_asm": "sub_13D3:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 28h\nmov [rbp+var_24], edi\nmov [rbp+var_28], esi\nmov eax, [rbp+var_28]\nadd eax, eax\nlea ebx, [rax+1]\nmov edx, [rbp+var_28]\nmov eax, [rbp+var_24]\nadd edx, eax\nmov eax, [rbp+var_24]\nadd eax, eax\nmov esi, edx\nmov edi, eax\ncall sub_1169\nimul eax, ebx\nmov [rbp+var_18], eax\nmov edx, [rbp+var_28]\nmov eax, [rbp+var_24]\nadd eax, edx\nadd eax, 1\nmov [rbp+var_14], eax\nmov eax, [rbp+var_18]\ncdq\nidiv [rbp+var_14]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_13D3(int a1, int a2)\n{\n return (unsigned int)((int)((2 * a2 + 1) * sub_1169((unsigned int)(2 * a1), (unsigned int)(a1 + a2))) / (a2 + a1 + 1));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_13D3(int a1, int a2) {\n return (\n unsigned int)((int)((2 * a2 + 1) * sub_1169((unsigned int)(2 * a1),\n (unsigned int)(a1 + a2))) /\n (a2 + a1 + 1));\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n return (unsigned int)((int)((2 * a2 + 1) *\n binomial_coeff((unsigned int)(2 * a1),\n (unsigned int)(a1 + a2))) /\n (a2 + a1 + 1));\n}" + }, + { + "index": 912, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nint binomial_coeff(int n, int k) {\n\n int C[n + 1][k + 1];\n\n for (int i = 0; i <= n; i++) {\n\n for (int j = 0; j <= (i < k ? i : k); j++) {\n\n if (j == 0 || j == i) {\n\n C[i][j] = 1;\n\n } else {\n\n C[i][j] = C[i - 1][j - 1] + C[i - 1][j];\n\n }\n\n }\n\n }\n\n return C[n][k];\n\n}\n\n\n\n", + "func": "int func0(int n, int m) {\n int numerator = (2 * m + 1) * binomial_coeff(2 * n, m + n);\n int denominator = m + n + 1;\n return numerator / denominator;\n}", + "test": "int main() {\n\n assert(func0(5, 3) == 35);\n\n assert(func0(3, 2) == 5);\n\n assert(func0(4, 2) == 20);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %esi,%ebp\nlea (%rsi,%rdi,1),%ebx\nadd %edi,%edi\nmov %ebx,%esi\ncallq 1169 \nmov %eax,%edx\nlea 0x1(%rbp,%rbp,1),%eax\nimul %edx,%eax\nadd $0x1,%ebx\ncltd\nidiv %ebx\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov ebp, esi\nlea ebx, [rsi+rdi]\nadd edi, edi\nmov esi, ebx\ncall binomial_coeff\nmov edx, eax\nlea eax, [rbp+rbp+1]\nimul eax, edx\nadd ebx, 1\ncdq\nidiv ebx\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n return (unsigned int)((int)(binomial_coeff((unsigned int)(2 * a1), (unsigned int)(a2 + a1)) * (2 * a2 + 1))\n / (a2 + a1 + 1));\n}", + "ida_strip_asm": "sub_128F:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov ebp, esi\nlea ebx, [rsi+rdi]\nadd edi, edi\nmov esi, ebx\ncall sub_1169\nmov edx, eax\nlea eax, [rbp+rbp+1]\nimul eax, edx\nadd ebx, 1\ncdq\nidiv ebx\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_128F(int a1, int a2)\n{\n return (unsigned int)((int)(sub_1169((unsigned int)(2 * a1), (unsigned int)(a2 + a1)) * (2 * a2 + 1)) / (a2 + a1 + 1));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_128F(int a1, int a2) {\n return (unsigned int)((int)(sub_1169((unsigned int)(2 * a1),\n (unsigned int)(a2 + a1)) *\n (2 * a2 + 1)) /\n (a2 + a1 + 1));\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n return (unsigned int)((int)(binomial_coeff((unsigned int)(2 * a1),\n (unsigned int)(a2 + a1)) *\n (2 * a2 + 1)) /\n (a2 + a1 + 1));\n}" + }, + { + "index": 912, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nint binomial_coeff(int n, int k) {\n\n int C[n + 1][k + 1];\n\n for (int i = 0; i <= n; i++) {\n\n for (int j = 0; j <= (i < k ? i : k); j++) {\n\n if (j == 0 || j == i) {\n\n C[i][j] = 1;\n\n } else {\n\n C[i][j] = C[i - 1][j - 1] + C[i - 1][j];\n\n }\n\n }\n\n }\n\n return C[n][k];\n\n}\n\n\n\n", + "func": "int func0(int n, int m) {\n int numerator = (2 * m + 1) * binomial_coeff(2 * n, m + n);\n int denominator = m + n + 1;\n return numerator / denominator;\n}", + "test": "int main() {\n\n assert(func0(5, 3) == 35);\n\n assert(func0(3, 2) == 5);\n\n assert(func0(4, 2) == 20);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %esi,%ebp\npush %rbx\nlea (%rsi,%rdi,1),%ebx\nadd %edi,%edi\nmov %ebx,%esi\nadd $0x1,%ebx\nsub $0x8,%rsp\ncallq 1240 \nadd $0x8,%rsp\nmov %eax,%r8d\nlea 0x1(%rbp,%rbp,1),%eax\nimul %r8d,%eax\ncltd\nidiv %ebx\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov ebp, esi\npush rbx\nlea ebx, [rsi+rdi]\nadd edi, edi\nmov esi, ebx\nadd ebx, 1\nsub rsp, 8\ncall binomial_coeff\nadd rsp, 8\nmov edx, eax\nlea eax, [rbp+rbp+1]\nimul eax, edx\ncdq\nidiv ebx\npop rbx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n return (unsigned int)((int)(binomial_coeff((unsigned int)(2 * a1), (unsigned int)(a2 + a1)) * (2 * a2 + 1))\n / (a2 + a1 + 1));\n}", + "ida_strip_asm": "sub_13A0:\nendbr64\npush rbp\nmov ebp, esi\npush rbx\nlea ebx, [rsi+rdi]\nadd edi, edi\nmov esi, ebx\nadd ebx, 1\nsub rsp, 8\ncall sub_1240\nadd rsp, 8\nmov edx, eax\nlea eax, [rbp+rbp+1]\nimul eax, edx\ncdq\nidiv ebx\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_13A0(int a1, int a2)\n{\n return (unsigned int)((int)(sub_1240((unsigned int)(2 * a1), (unsigned int)(a2 + a1)) * (2 * a2 + 1)) / (a2 + a1 + 1));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_13A0(int a1, int a2) {\n return (unsigned int)((int)(sub_1240((unsigned int)(2 * a1),\n (unsigned int)(a2 + a1)) *\n (2 * a2 + 1)) /\n (a2 + a1 + 1));\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n return (unsigned int)((int)(binomial_coeff((unsigned int)(2 * a1),\n (unsigned int)(a2 + a1)) *\n (2 * a2 + 1)) /\n (a2 + a1 + 1));\n}" + }, + { + "index": 912, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nint binomial_coeff(int n, int k) {\n\n int C[n + 1][k + 1];\n\n for (int i = 0; i <= n; i++) {\n\n for (int j = 0; j <= (i < k ? i : k); j++) {\n\n if (j == 0 || j == i) {\n\n C[i][j] = 1;\n\n } else {\n\n C[i][j] = C[i - 1][j - 1] + C[i - 1][j];\n\n }\n\n }\n\n }\n\n return C[n][k];\n\n}\n\n\n\n", + "func": "int func0(int n, int m) {\n int numerator = (2 * m + 1) * binomial_coeff(2 * n, m + n);\n int denominator = m + n + 1;\n return numerator / denominator;\n}", + "test": "int main() {\n\n assert(func0(5, 3) == 35);\n\n assert(func0(3, 2) == 5);\n\n assert(func0(4, 2) == 20);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0x28,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nlea 0x1(%rsi,%rsi,1),%eax\nadd %edi,%esi\nadd %edi,%edi\nlea 0x1(%rsi),%r10d\nlea 0x1(%rdi),%edx\nmov %rsp,%rbx\nmovslq %r10d,%rcx\nmovslq %edx,%rdx\nimul %rcx,%rdx\nlea 0x0(,%rcx,4),%r14\nlea 0xf(,%rdx,4),%rdx\nmov %rdx,%rcx\nand $0xfffffffffffff000,%rdx\nsub %rdx,%rbx\nand $0xfffffffffffffff0,%rcx\nmov %rbx,%rdx\ncmp %rdx,%rsp\nje 13fe \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rdx,%rsp\njne 13e9 \nand $0xfff,%ecx\nsub %rcx,%rsp\ntest %rcx,%rcx\njne 14f0 \nmov %r14,%r13\nmov %rsp,%r15\nshr $0x2,%r13\ntest %edi,%edi\njs 14b0 \nmov %r15,%r12\nmovslq %edi,%rdi\nmov $0xffffffffffffffff,%rbx\nxor %ecx,%ecx\nnopl 0x0(%rax)\ncmp %ecx,%esi\nmov %ecx,%edx\ncmovl %esi,%edx\ntest %edx,%edx\njs 1494 \nmov %rbx,%r9\nadd $0x1,%edx\nmov %r12,%r8\nsub %rcx,%r9\nmov %edx,-0x44(%rbp)\nxor %edx,%edx\nimul %r13,%r9\njmp 1479 \nnopw 0x0(%rax,%rax,1)\nmov (%r8,%r9,4),%r11d\nadd -0x4(%r8,%r9,4),%r11d\nadd $0x1,%edx\nadd $0x4,%r8\nmov %r11d,-0x4(%r8)\ncmp -0x44(%rbp),%edx\nje 1494 \ntest %edx,%edx\nje 1481 \ncmp %ecx,%edx\njne 1460 \nmovl $0x1,(%r8)\nadd $0x1,%edx\nadd $0x4,%r8\ncmp -0x44(%rbp),%edx\njne 1479 \nlea 0x1(%rcx),%rdx\nadd $0x1,%rbx\nadd %r14,%r12\ncmp %rdi,%rcx\nje 14b8 \nmov %rdx,%rcx\njmp 1438 \nnopl 0x0(%rax)\nmovslq %edi,%rdi\nnopl 0x0(%rax,%rax,1)\nimul %r13,%rdi\nmovslq %esi,%rsi\nadd %rsi,%rdi\nimul (%r15,%rdi,4),%eax\ncltd\nidiv %r10d\nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\njne 14fb \nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\nnopl 0x0(%rax)\norq $0x0,-0x8(%rsp,%rcx,1)\njmpq 1410 \ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov ebp, esi\npush rbx\nlea ebx, [rsi+rdi]\nadd edi, edi\nmov esi, ebx\nadd ebx, 1\nsub rsp, 8\ncall binomial_coeff\nadd rsp, 8\nmov edx, eax\nlea eax, [rbp+rbp+1]\nimul eax, edx\ncdq\nidiv ebx\npop rbx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n return (unsigned int)((int)(binomial_coeff((unsigned int)(2 * a1), (unsigned int)(a2 + a1)) * (2 * a2 + 1))\n / (a2 + a1 + 1));\n}", + "ida_strip_asm": "sub_13B0:\nendbr64\npush rbp\nmov ebp, esi\npush rbx\nlea ebx, [rsi+rdi]\nadd edi, edi\nmov esi, ebx\nadd ebx, 1\nsub rsp, 8\ncall sub_1240\nadd rsp, 8\nmov edx, eax\nlea eax, [rbp+rbp+1]\nimul eax, edx\ncdq\nidiv ebx\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_13B0(int a1, int a2)\n{\n return (unsigned int)((int)(sub_1240((unsigned int)(2 * a1), (unsigned int)(a2 + a1)) * (2 * a2 + 1)) / (a2 + a1 + 1));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_13B0(int a1, int a2) {\n return (unsigned int)((int)(sub_1240((unsigned int)(2 * a1),\n (unsigned int)(a2 + a1)) *\n (2 * a2 + 1)) /\n (a2 + a1 + 1));\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n return (unsigned int)((int)(binomial_coeff((unsigned int)(2 * a1),\n (unsigned int)(a2 + a1)) *\n (2 * a2 + 1)) /\n (a2 + a1 + 1));\n}" + }, + { + "index": 913, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char *string) {\n regex_t regex;\n int result;\n bool match_found;\n regcomp(®ex, \".*[0-9]$\", 0);\n result = regexec(®ex, string, 0, NULL, 0);\n match_found = (result == 0);\n regfree(®ex);\n return match_found;\n}", + "test": "int main() {\n\n assert(func0(\"abcdef\") == false);\n\n assert(func0(\"abcdef7\") == true);\n\n assert(func0(\"abc\") == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x70,%rsp\nmov %rdi,-0x68(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea -0x50(%rbp),%rax\nmov $0x0,%edx\nlea 0xe10(%rip),%rsi\nmov %rax,%rdi\ncallq 10c0 \nmov -0x68(%rbp),%rsi\nlea -0x50(%rbp),%rax\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rax,%rdi\ncallq 10d0 \nmov %eax,-0x54(%rbp)\ncmpl $0x0,-0x54(%rbp)\nsete %al\nmov %al,-0x55(%rbp)\nlea -0x50(%rbp),%rax\nmov %rax,%rdi\ncallq 1090 \nmovzbl -0x55(%rbp),%eax\nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 1251 \ncallq 10a0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [rbp+preg]\nmov edx, 0; cflags\nlea rcx, pattern; \".*[0-9]$\"\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_54], eax\ncmp [rbp+var_54], 0\nsetz al\nmov [rbp+var_55], al\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nmovzx eax, [rbp+var_55]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1254\ncall ___stack_chk_fail\nlocret_1254:\nleave\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(const char *a1)\n{\n bool v2; // [rsp+1Bh] [rbp-55h]\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n unsigned __int64 v4; // [rsp+68h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n regcomp(&preg, \".*[0-9]$\", 0);\n v2 = regexec(&preg, a1, 0LL, 0LL, 0) == 0;\n regfree(&preg);\n return v2;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, [rbp+preg]\nmov edx, 0; cflags\nlea rcx, pattern; \".*[0-9]$\"\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_54], eax\ncmp [rbp+var_54], 0\nsetz al\nmov [rbp+var_55], al\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\nmovzx eax, [rbp+var_55]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1254\ncall ___stack_chk_fail\nlocret_1254:\nleave\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_11C9(const char *a1)\n{\n bool v2; // [rsp+1Bh] [rbp-55h]\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n unsigned __int64 v4; // [rsp+68h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n regcomp(&preg, \".*[0-9]$\", 0);\n v2 = regexec(&preg, a1, 0LL, 0LL, 0) == 0;\n regfree(&preg);\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_11C9(const char *a1) {\n bool v2;\n regex_t preg;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n regcomp(&preg, \".*[0-9]$\", 0);\n v2 = regexec(&preg, a1, 0LL, 0LL, 0) == 0;\n regfree(&preg);\n return v2;\n}", + "ida_pseudo_norm": "uint8_t func0(const char *a1) {\n bool v2;\n regex_t preg;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n regcomp(&preg, \".*[0-9]$\", 0);\n v2 = regexec(&preg, a1, 0LL, 0LL, 0) == 0;\n regfree(&preg);\n return v2;\n}" + }, + { + "index": 913, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char *string) {\n regex_t regex;\n int result;\n bool match_found;\n regcomp(®ex, \".*[0-9]$\", 0);\n result = regexec(®ex, string, 0, NULL, 0);\n match_found = (result == 0);\n regfree(®ex);\n return match_found;\n}", + "test": "int main() {\n\n assert(func0(\"abcdef\") == false);\n\n assert(func0(\"abcdef7\") == true);\n\n assert(func0(\"abc\") == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nsub $0x50,%rsp\nmov %rdi,%rbx\nmov $0x28,%r12d\nmov %fs:(%r12),%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%rbp\nmov $0x0,%edx\nlea 0xe0b(%rip),%rsi\nmov %rbp,%rdi\ncallq 10c0 \nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rbx,%rsi\nmov %rbp,%rdi\ncallq 10d0 \nmov %eax,%ebx\nmov %rbp,%rdi\ncallq 1090 \ntest %ebx,%ebx\nsete %al\nmov 0x48(%rsp),%rcx\nxor %fs:(%r12),%rcx\njne 1240 \nadd $0x50,%rsp\npop %rbx\npop %rbp\npop %r12\nretq\ncallq 10a0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov edx, 0; cflags\nlea rsi, pattern; \".*[0-9]$\"\nmov rdi, rbp; preg\ncall _regcomp\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov ebx, eax\nmov rdi, rbp; preg\ncall _regfree\ntest ebx, ebx\nsetz al\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_123E\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_123E:\ncall ___stack_chk_fail", + "ida_pseudo": "bool __fastcall func0(char *string)\n{\n int v1; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \".*[0-9]$\", 0);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 0;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov edx, 0; cflags\nlea rsi, pattern; \".*[0-9]$\"\nmov rdi, rbp; preg\ncall _regcomp\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov ebx, eax\nmov rdi, rbp; preg\ncall _regfree\ntest ebx, ebx\nsetz al\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_123E\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_123E:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "bool __fastcall sub_11C9(char *string)\n{\n int v1; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \".*[0-9]$\", 0);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_11C9(char *string) {\n int v1;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \".*[0-9]$\", 0);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 0;\n}", + "ida_pseudo_norm": "bool func0(char *string) {\n int v1;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \".*[0-9]$\", 0);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 0;\n}" + }, + { + "index": 913, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char *string) {\n regex_t regex;\n int result;\n bool match_found;\n regcomp(®ex, \".*[0-9]$\", 0);\n result = regexec(®ex, string, 0, NULL, 0);\n match_found = (result == 0);\n regfree(®ex);\n return match_found;\n}", + "test": "int main() {\n\n assert(func0(\"abcdef\") == false);\n\n assert(func0(\"abcdef7\") == true);\n\n assert(func0(\"abc\") == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nxor %edx,%edx\nmov %rdi,%r12\nlea 0xd82(%rip),%rsi\npush %rbp\npush %rbx\nsub $0x50,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%rbp\nmov %rbp,%rdi\ncallq 10c0 \nxor %ecx,%ecx\nxor %r8d,%r8d\nxor %edx,%edx\nmov %r12,%rsi\nmov %rbp,%rdi\ncallq 10d0 \nmov %rbp,%rdi\nmov %eax,%ebx\ncallq 1090 \ntest %ebx,%ebx\nsete %al\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 12dd \nadd $0x50,%rsp\npop %rbx\npop %rbp\npop %r12\nretq\ncallq 10a0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nxor edx, edx; cflags\nlea rsi, pattern; \".*[0-9]$\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nsetz al\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_12D9\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_12D9:\ncall ___stack_chk_fail", + "ida_pseudo": "bool __fastcall func0(char *string)\n{\n int v1; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \".*[0-9]$\", 0);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 0;\n}", + "ida_strip_asm": "sub_1270:\nendbr64\npush rbp\nxor edx, edx; cflags\nlea rsi, pattern; \".*[0-9]$\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nsetz al\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_12D9\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_12D9:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "bool __fastcall sub_1270(char *string)\n{\n int v1; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \".*[0-9]$\", 0);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_1270(char *string) {\n int v1;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \".*[0-9]$\", 0);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 0;\n}", + "ida_pseudo_norm": "bool func0(char *string) {\n int v1;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \".*[0-9]$\", 0);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 0;\n}" + }, + { + "index": 913, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char *string) {\n regex_t regex;\n int result;\n bool match_found;\n regcomp(®ex, \".*[0-9]$\", 0);\n result = regexec(®ex, string, 0, NULL, 0);\n match_found = (result == 0);\n regfree(®ex);\n return match_found;\n}", + "test": "int main() {\n\n assert(func0(\"abcdef\") == false);\n\n assert(func0(\"abcdef7\") == true);\n\n assert(func0(\"abc\") == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nxor %edx,%edx\nmov %rdi,%r12\nlea 0xd82(%rip),%rsi\npush %rbp\npush %rbx\nsub $0x50,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%rbp\nmov %rbp,%rdi\ncallq 10c0 \nxor %ecx,%ecx\nxor %r8d,%r8d\nxor %edx,%edx\nmov %r12,%rsi\nmov %rbp,%rdi\ncallq 10d0 \nmov %rbp,%rdi\nmov %eax,%ebx\ncallq 1090 \ntest %ebx,%ebx\nsete %al\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 12dd \nadd $0x50,%rsp\npop %rbx\npop %rbp\npop %r12\nretq\ncallq 10a0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nxor edx, edx; cflags\nlea rsi, pattern; \".*[0-9]$\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nsetz al\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_12D9\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_12D9:\ncall ___stack_chk_fail", + "ida_pseudo": "bool __fastcall func0(char *string)\n{\n int v1; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \".*[0-9]$\", 0);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 0;\n}", + "ida_strip_asm": "sub_1270:\nendbr64\npush rbp\nxor edx, edx; cflags\nlea rsi, pattern; \".*[0-9]$\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\ntest ebx, ebx\nsetz al\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_12D9\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_12D9:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "bool __fastcall sub_1270(char *string)\n{\n int v1; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \".*[0-9]$\", 0);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_1270(char *string) {\n int v1;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \".*[0-9]$\", 0);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 0;\n}", + "ida_pseudo_norm": "bool func0(char *string) {\n int v1;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \".*[0-9]$\", 0);\n v1 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n return v1 == 0;\n}" + }, + { + "index": 914, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char* s) {\n int length = strlen(s);\n for (int i = 0; i < length - 2; i++) {\n if (s[i] != s[i + 2]) {\n return false;\n }\n }\n if (s[0] == s[1]) {\n return false;\n }\n return true;\n}", + "test": "int main() {\n\n assert(func0(\"abab\") == true);\n\n assert(func0(\"aaaa\") == false);\n\n assert(func0(\"xyz\") == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov -0x18(%rbp),%rax\nmov %rax,%rdi\ncallq 1060 \nmov %eax,-0x4(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11c3 \nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%edx\nmov -0x8(%rbp),%eax\ncltq\nlea 0x2(%rax),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmovzbl (%rax),%eax\ncmp %al,%dl\nje 11bf \nmov $0x0,%eax\njmp 11f0 \naddl $0x1,-0x8(%rbp)\nmov -0x4(%rbp),%eax\nsub $0x2,%eax\ncmp %eax,-0x8(%rbp)\njl 1191 \nmov -0x18(%rbp),%rax\nmovzbl (%rax),%edx\nmov -0x18(%rbp),%rax\nadd $0x1,%rax\nmovzbl (%rax),%eax\ncmp %al,%dl\njne 11eb \nmov $0x0,%eax\njmp 11f0 \nmov $0x1,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_8], 0\njmp short loc_11C3\nloc_1191:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_8]\ncdqe\nlea rcx, [rax+2]\nmov rax, [rbp+s]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njz short loc_11BF\nmov eax, 0\njmp short locret_11F0\nloc_11BF:\nadd [rbp+var_8], 1\nloc_11C3:\nmov eax, [rbp+var_4]\nsub eax, 2\ncmp [rbp+var_8], eax\njl short loc_1191\nmov rax, [rbp+s]\nmovzx edx, byte ptr [rax]\nmov rax, [rbp+s]\nadd rax, 1\nmovzx eax, byte ptr [rax]\ncmp dl, al\njnz short loc_11EB\nmov eax, 0\njmp short locret_11F0\nloc_11EB:\nmov eax, 1\nlocret_11F0:\nleave\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(__int64 a1)\n{\n int i; // [rsp+18h] [rbp-8h]\n int v3; // [rsp+1Ch] [rbp-4h]\n\n v3 = strlen((const char *)a1);\n for ( i = 0; i < v3 - 2; ++i )\n {\n if ( *(_BYTE *)(i + a1) != *(_BYTE *)(i + 2LL + a1) )\n return 0LL;\n }\n return *(_BYTE *)a1 != *(_BYTE *)(a1 + 1);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_4], eax\nmov [rbp+var_8], 0\njmp short loc_11C3\nloc_1191:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_8]\ncdqe\nlea rcx, [rax+2]\nmov rax, [rbp+s]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njz short loc_11BF\nmov eax, 0\njmp short locret_11F0\nloc_11BF:\nadd [rbp+var_8], 1\nloc_11C3:\nmov eax, [rbp+var_4]\nsub eax, 2\ncmp [rbp+var_8], eax\njl short loc_1191\nmov rax, [rbp+s]\nmovzx edx, byte ptr [rax]\nmov rax, [rbp+s]\nadd rax, 1\nmovzx eax, byte ptr [rax]\ncmp dl, al\njnz short loc_11EB\nmov eax, 0\njmp short locret_11F0\nloc_11EB:\nmov eax, 1\nlocret_11F0:\nleave\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1169(__int64 a1)\n{\n int i; // [rsp+18h] [rbp-8h]\n int v3; // [rsp+1Ch] [rbp-4h]\n\n v3 = strlen((const char *)a1);\n for ( i = 0; i < v3 - 2; ++i )\n {\n if ( *(_BYTE *)(i + a1) != *(_BYTE *)(i + 2LL + a1) )\n return 0LL;\n }\n return *(_BYTE *)a1 != *(_BYTE *)(a1 + 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1169(long long a1) {\n int i;\n int v3;\n v3 = strlen((const char *)a1);\n for (i = 0; i < v3 - 2; ++i) {\n if (*(uint8_t *)(i + a1) != *(uint8_t *)(i + 2LL + a1)) return 0LL;\n }\n return *(uint8_t *)a1 != *(uint8_t *)(a1 + 1);\n}", + "ida_pseudo_norm": "uint8_t func0(long long a1) {\n int i;\n int v3;\n v3 = strlen((const char *)a1);\n for (i = 0; i < v3 - 2; ++i) {\n if (*(uint8_t *)(i + a1) != *(uint8_t *)(i + 2LL + a1)) return 0LL;\n }\n return *(uint8_t *)a1 != *(uint8_t *)(a1 + 1);\n}" + }, + { + "index": 914, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char* s) {\n int length = strlen(s);\n for (int i = 0; i < length - 2; i++) {\n if (s[i] != s[i + 2]) {\n return false;\n }\n }\n if (s[0] == s[1]) {\n return false;\n }\n return true;\n}", + "test": "int main() {\n\n assert(func0(\"abab\") == true);\n\n assert(func0(\"aaaa\") == false);\n\n assert(func0(\"xyz\") == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%rsi\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nsub $0x1,%rcx\ncmp $0x2,%ecx\njle 1187 \nmov %rsi,%rax\nlea -0x3(%rcx),%edx\nlea 0x1(%rsi,%rdx,1),%rdx\nmovzbl 0x2(%rax),%edi\ncmp %dil,(%rax)\njne 1191 \nadd $0x1,%rax\ncmp %rdx,%rax\njne 1175 \nmovzbl 0x1(%rsi),%eax\ncmp %al,(%rsi)\nsetne %al\nretq\nmov $0x0,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ncmp eax, 2\njle short loc_1197\nmov rdx, rbx\nlea eax, [rax-3]\nlea rax, [rbx+rax+1]\nloc_1186:\nmovzx ecx, byte ptr [rdx+2]\ncmp [rdx], cl\njnz short loc_11A2\nadd rdx, 1\ncmp rdx, rax\njnz short loc_1186\nloc_1197:\nmovzx eax, byte ptr [rbx+1]\ncmp [rbx], al\nsetnz al\nloc_11A0:\npop rbx\nretn\nloc_11A2:\nmov eax, 0\njmp short loc_11A0", + "ida_pseudo": "bool __fastcall func0(__int64 a1)\n{\n int v1; // eax\n _BYTE *v2; // rdx\n __int64 v3; // rax\n\n v1 = strlen((const char *)a1);\n if ( v1 <= 2 )\n return *(_BYTE *)a1 != *(_BYTE *)(a1 + 1);\n v2 = (_BYTE *)a1;\n v3 = a1 + (unsigned int)(v1 - 3) + 1;\n while ( *v2 == v2[2] )\n {\n if ( ++v2 == (_BYTE *)v3 )\n return *(_BYTE *)a1 != *(_BYTE *)(a1 + 1);\n }\n return 0;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\ncmp eax, 2\njle short loc_1197\nmov rdx, rbx\nlea eax, [rax-3]\nlea rax, [rbx+rax+1]\nloc_1186:\nmovzx ecx, byte ptr [rdx+2]\ncmp [rdx], cl\njnz short loc_11A2\nadd rdx, 1\ncmp rdx, rax\njnz short loc_1186\nloc_1197:\nmovzx eax, byte ptr [rbx+1]\ncmp [rbx], al\nsetnz al\nloc_11A0:\npop rbx\nretn\nloc_11A2:\nmov eax, 0\njmp short loc_11A0", + "ida_strip_pseudo": "bool __fastcall sub_1169(__int64 a1)\n{\n int v1; // eax\n _BYTE *v2; // rdx\n __int64 v3; // rax\n\n v1 = strlen((const char *)a1);\n if ( v1 <= 2 )\n return *(_BYTE *)a1 != *(_BYTE *)(a1 + 1);\n v2 = (_BYTE *)a1;\n v3 = a1 + (unsigned int)(v1 - 3) + 1;\n while ( *v2 == v2[2] )\n {\n if ( ++v2 == (_BYTE *)v3 )\n return *(_BYTE *)a1 != *(_BYTE *)(a1 + 1);\n }\n return 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_1169(long long a1) {\n int v1;\n uint8_t *v2;\n long long v3;\n v1 = strlen((const char *)a1);\n if (v1 <= 2) return *(uint8_t *)a1 != *(uint8_t *)(a1 + 1);\n v2 = (uint8_t *)a1;\n v3 = a1 + (unsigned int)(v1 - 3) + 1;\n while (*v2 == v2[2]) {\n if (++v2 == (uint8_t *)v3) return *(uint8_t *)a1 != *(uint8_t *)(a1 + 1);\n }\n return 0;\n}", + "ida_pseudo_norm": "bool func0(long long a1) {\n int v1;\n uint8_t *v2;\n long long v3;\n v1 = strlen((const char *)a1);\n if (v1 <= 2) return *(uint8_t *)a1 != *(uint8_t *)(a1 + 1);\n v2 = (uint8_t *)a1;\n v3 = a1 + (unsigned int)(v1 - 3) + 1;\n while (*v2 == v2[2]) {\n if (++v2 == (uint8_t *)v3) return *(uint8_t *)a1 != *(uint8_t *)(a1 + 1);\n }\n return 0;\n}" + }, + { + "index": 914, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char* s) {\n int length = strlen(s);\n for (int i = 0; i < length - 2; i++) {\n if (s[i] != s[i + 2]) {\n return false;\n }\n }\n if (s[0] == s[1]) {\n return false;\n }\n return true;\n}", + "test": "int main() {\n\n assert(func0(\"abab\") == true);\n\n assert(func0(\"aaaa\") == false);\n\n assert(func0(\"xyz\") == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\ncallq 1060 \ncmp $0x2,%eax\njle 1248 \nsub $0x3,%eax\nmov %rbx,%rdx\nlea 0x1(%rbx,%rax,1),%rax\njmp 1239 \nadd $0x1,%rdx\ncmp %rax,%rdx\nje 1248 \nmovzbl 0x2(%rdx),%ecx\ncmp %cl,(%rdx)\nje 1230 \nxor %eax,%eax\npop %rbx\nretq\nnopl (%rax)\nmovzbl 0x1(%rbx),%eax\ncmp %al,(%rbx)\nsetne %al\npop %rbx\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmovzx edi, byte ptr [rbx]\ncmp eax, 2\njle short loc_1260\nsub eax, 3\nmovzx ecx, byte ptr [rbx+1]\nmov esi, edi\nlea rdx, [rbx+2]\nlea r8, [rbx+rax+3]\njmp short loc_124B\nloc_1240:\nadd rdx, 1\nmov esi, eax\ncmp rdx, r8\njz short loc_1260\nloc_124B:\nmov eax, ecx\nmovzx ecx, byte ptr [rdx]\ncmp cl, sil\njz short loc_1240\nxor eax, eax\npop rbx\nretn\nloc_1260:\ncmp dil, [rbx+1]\npop rbx\nsetnz al\nretn", + "ida_pseudo": "bool __fastcall func0(__int64 a1)\n{\n int v2; // eax\n char v3; // di\n char v4; // cl\n char v5; // si\n char *v6; // rdx\n __int64 v7; // r8\n char v8; // al\n\n v2 = strlen((const char *)a1);\n v3 = *(_BYTE *)a1;\n if ( v2 <= 2 )\n return v3 != *(_BYTE *)(a1 + 1);\n v4 = *(_BYTE *)(a1 + 1);\n v5 = v3;\n v6 = (char *)(a1 + 2);\n v7 = a1 + (unsigned int)(v2 - 3) + 3;\n while ( 1 )\n {\n v8 = v4;\n v4 = *v6;\n if ( *v6 != v5 )\n break;\n ++v6;\n v5 = v8;\n if ( v6 == (char *)v7 )\n return v3 != *(_BYTE *)(a1 + 1);\n }\n return 0;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmovzx edi, byte ptr [rbx]\ncmp eax, 2\njle short loc_1260\nsub eax, 3\nmovzx ecx, byte ptr [rbx+1]\nmov esi, edi\nlea rdx, [rbx+2]\nlea r8, [rbx+rax+3]\njmp short loc_124B\nloc_1240:\nadd rdx, 1\nmov esi, eax\ncmp rdx, r8\njz short loc_1260\nloc_124B:\nmov eax, ecx\nmovzx ecx, byte ptr [rdx]\ncmp cl, sil\njz short loc_1240\nxor eax, eax\npop rbx\nretn\nloc_1260:\ncmp dil, [rbx+1]\npop rbx\nsetnz al\nretn", + "ida_strip_pseudo": "bool __fastcall sub_1210(__int64 a1)\n{\n int v2; // eax\n char v3; // di\n char v4; // cl\n char v5; // si\n char *v6; // rdx\n __int64 v7; // r8\n char v8; // al\n\n v2 = strlen((const char *)a1);\n v3 = *(_BYTE *)a1;\n if ( v2 <= 2 )\n return v3 != *(_BYTE *)(a1 + 1);\n v4 = *(_BYTE *)(a1 + 1);\n v5 = v3;\n v6 = (char *)(a1 + 2);\n v7 = a1 + (unsigned int)(v2 - 3) + 3;\n while ( 1 )\n {\n v8 = v4;\n v4 = *v6;\n if ( *v6 != v5 )\n break;\n ++v6;\n v5 = v8;\n if ( v6 == (char *)v7 )\n return v3 != *(_BYTE *)(a1 + 1);\n }\n return 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_1210(long long a1) {\n int v2;\n char v3;\n char v4;\n char v5;\n char *v6;\n long long v7;\n char v8;\n v2 = strlen((const char *)a1);\n v3 = *(uint8_t *)a1;\n if (v2 <= 2) return v3 != *(uint8_t *)(a1 + 1);\n v4 = *(uint8_t *)(a1 + 1);\n v5 = v3;\n v6 = (char *)(a1 + 2);\n v7 = a1 + (unsigned int)(v2 - 3) + 3;\n while (1) {\n v8 = v4;\n v4 = *v6;\n if (*v6 != v5) break;\n ++v6;\n v5 = v8;\n if (v6 == (char *)v7) return v3 != *(uint8_t *)(a1 + 1);\n }\n return 0;\n}", + "ida_pseudo_norm": "bool func0(long long a1) {\n int v2;\n char v3;\n char v4;\n char v5;\n char *v6;\n long long v7;\n char v8;\n v2 = strlen((const char *)a1);\n v3 = *(uint8_t *)a1;\n if (v2 <= 2) return v3 != *(uint8_t *)(a1 + 1);\n v4 = *(uint8_t *)(a1 + 1);\n v5 = v3;\n v6 = (char *)(a1 + 2);\n v7 = a1 + (unsigned int)(v2 - 3) + 3;\n while (1) {\n v8 = v4;\n v4 = *v6;\n if (*v6 != v5) break;\n ++v6;\n v5 = v8;\n if (v6 == (char *)v7) return v3 != *(uint8_t *)(a1 + 1);\n }\n return 0;\n}" + }, + { + "index": 914, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(const char* s) {\n int length = strlen(s);\n for (int i = 0; i < length - 2; i++) {\n if (s[i] != s[i + 2]) {\n return false;\n }\n }\n if (s[0] == s[1]) {\n return false;\n }\n return true;\n}", + "test": "int main() {\n\n assert(func0(\"abab\") == true);\n\n assert(func0(\"aaaa\") == false);\n\n assert(func0(\"xyz\") == false);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\ncallq 1060 \nmovzbl (%rbx),%edi\ncmp $0x2,%eax\njle 1260 \nsub $0x3,%eax\nmovzbl 0x1(%rbx),%esi\nmov %edi,%ecx\nlea 0x2(%rbx),%rdx\nlea 0x3(%rbx,%rax,1),%r8\njmp 124f \nnopl 0x0(%rax)\nadd $0x1,%rdx\nmov %esi,%eax\nmov %ecx,%esi\ncmp %r8,%rdx\nje 1260 \nmov %eax,%ecx\ncmp %cl,(%rdx)\nje 1240 \nxor %eax,%eax\npop %rbx\nretq\nnopw 0x0(%rax,%rax,1)\ncmp 0x1(%rbx),%dil\npop %rbx\nsetne %al\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmovzx edi, byte ptr [rbx]\ncmp eax, 2\njle short loc_1260\nsub eax, 3\nmovzx ecx, byte ptr [rbx+1]\nmov esi, edi\nlea rdx, [rbx+2]\nlea r8, [rbx+rax+3]\njmp short loc_124B\nloc_1240:\nadd rdx, 1\nmov esi, eax\ncmp rdx, r8\njz short loc_1260\nloc_124B:\nmov eax, ecx\nmovzx ecx, byte ptr [rdx]\ncmp cl, sil\njz short loc_1240\nxor eax, eax\npop rbx\nretn\nloc_1260:\ncmp dil, [rbx+1]\npop rbx\nsetnz al\nretn", + "ida_pseudo": "bool __fastcall func0(__int64 a1)\n{\n int v2; // eax\n char v3; // di\n char v4; // cl\n char v5; // si\n char *v6; // rdx\n __int64 v7; // r8\n char v8; // al\n\n v2 = strlen((const char *)a1);\n v3 = *(_BYTE *)a1;\n if ( v2 <= 2 )\n return v3 != *(_BYTE *)(a1 + 1);\n v4 = *(_BYTE *)(a1 + 1);\n v5 = v3;\n v6 = (char *)(a1 + 2);\n v7 = a1 + (unsigned int)(v2 - 3) + 3;\n while ( 1 )\n {\n v8 = v4;\n v4 = *v6;\n if ( *v6 != v5 )\n break;\n ++v6;\n v5 = v8;\n if ( v6 == (char *)v7 )\n return v3 != *(_BYTE *)(a1 + 1);\n }\n return 0;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbx\nmov rbx, rdi\ncall _strlen\nmovzx edi, byte ptr [rbx]\ncmp eax, 2\njle short loc_1260\nsub eax, 3\nmovzx ecx, byte ptr [rbx+1]\nmov esi, edi\nlea rdx, [rbx+2]\nlea r8, [rbx+rax+3]\njmp short loc_124B\nloc_1240:\nadd rdx, 1\nmov esi, eax\ncmp rdx, r8\njz short loc_1260\nloc_124B:\nmov eax, ecx\nmovzx ecx, byte ptr [rdx]\ncmp cl, sil\njz short loc_1240\nxor eax, eax\npop rbx\nretn\nloc_1260:\ncmp dil, [rbx+1]\npop rbx\nsetnz al\nretn", + "ida_strip_pseudo": "bool __fastcall sub_1210(__int64 a1)\n{\n int v2; // eax\n char v3; // di\n char v4; // cl\n char v5; // si\n char *v6; // rdx\n __int64 v7; // r8\n char v8; // al\n\n v2 = strlen((const char *)a1);\n v3 = *(_BYTE *)a1;\n if ( v2 <= 2 )\n return v3 != *(_BYTE *)(a1 + 1);\n v4 = *(_BYTE *)(a1 + 1);\n v5 = v3;\n v6 = (char *)(a1 + 2);\n v7 = a1 + (unsigned int)(v2 - 3) + 3;\n while ( 1 )\n {\n v8 = v4;\n v4 = *v6;\n if ( *v6 != v5 )\n break;\n ++v6;\n v5 = v8;\n if ( v6 == (char *)v7 )\n return v3 != *(_BYTE *)(a1 + 1);\n }\n return 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "bool sub_1210(long long a1) {\n int v2;\n char v3;\n char v4;\n char v5;\n char *v6;\n long long v7;\n char v8;\n v2 = strlen((const char *)a1);\n v3 = *(uint8_t *)a1;\n if (v2 <= 2) return v3 != *(uint8_t *)(a1 + 1);\n v4 = *(uint8_t *)(a1 + 1);\n v5 = v3;\n v6 = (char *)(a1 + 2);\n v7 = a1 + (unsigned int)(v2 - 3) + 3;\n while (1) {\n v8 = v4;\n v4 = *v6;\n if (*v6 != v5) break;\n ++v6;\n v5 = v8;\n if (v6 == (char *)v7) return v3 != *(uint8_t *)(a1 + 1);\n }\n return 0;\n}", + "ida_pseudo_norm": "bool func0(long long a1) {\n int v2;\n char v3;\n char v4;\n char v5;\n char *v6;\n long long v7;\n char v8;\n v2 = strlen((const char *)a1);\n v3 = *(uint8_t *)a1;\n if (v2 <= 2) return v3 != *(uint8_t *)(a1 + 1);\n v4 = *(uint8_t *)(a1 + 1);\n v5 = v3;\n v6 = (char *)(a1 + 2);\n v7 = a1 + (unsigned int)(v2 - 3) + 3;\n while (1) {\n v8 = v4;\n v4 = *v6;\n if (*v6 != v5) break;\n ++v6;\n v5 = v8;\n if (v6 == (char *)v7) return v3 != *(uint8_t *)(a1 + 1);\n }\n return 0;\n}" + }, + { + "index": 915, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n// Function to rearrange numbers based on the specified key\n\nint comparator(const void* a, const void* b) {\n\n int ia = *(int*)a;\n\n int ib = *(int*)b;\n\n\n\n double key_a = (ia == 0) ? 0.0 : (-1.0 / ia);\n\n double key_b = (ib == 0) ? 0.0 : (-1.0 / ib);\n\n\n\n if (key_a < key_b) return -1;\n\n if (key_a > key_b) return 1;\n\n return 0;\n\n}\n\n\n\n", + "func": "int* func0(int array_nums[], int size) {\n qsort(array_nums, size, sizeof(int), comparator);\n return array_nums;\n}", + "test": "int main() {\n\n // Test case 1\n\n int array1[] = {-1, 2, -3, 5, 7, 8, 9, -10};\n\n int expected1[] = {2, 5, 7, 8, 9, -10, -3, -1};\n\n int size1 = sizeof(array1) / sizeof(array1[0]);\n\n func0(array1, size1);\n\n for(int i = 0; i < size1; i++) {\n\n assert(array1[i] == expected1[i]);\n\n }\n\n\n\n // Test case 2\n\n int array2[] = {10, 15, 14, 13, -18, 12, -20};\n\n int expected2[] = {10, 12, 13, 14, 15, -20, -18};\n\n int size2 = sizeof(array2) / sizeof(array2[0]);\n\n func0(array2, size2);\n\n for(int i = 0; i < size2; i++) {\n\n assert(array2[i] == expected2[i]);\n\n }\n\n\n\n // Test case 3\n\n int array3[] = {-20, 20, -10, 10, -30, 30};\n\n int expected3[] = {10, 20, 30, -30, -20, -10};\n\n int size3 = sizeof(array3) / sizeof(array3[0]);\n\n func0(array3, size3);\n\n for(int i = 0; i < size3; i++) {\n\n assert(array3[i] == expected3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %rdi,-0x8(%rbp)\nmov %esi,-0xc(%rbp)\nmov -0xc(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x8(%rbp),%rax\nlea -0xb7(%rip),%rcx\nmov $0x4,%edx\nmov %rax,%rdi\ncallq 1070 \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+base], rdi\nmov [rbp+var_C], esi\nmov eax, [rbp+var_C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, comparator\nmov rcx, rdx; compar\nmov edx, 4; size\nmov rdi, rax; base\ncall _qsort\nmov rax, [rbp+base]\nleave\nretn", + "ida_pseudo": "void *__fastcall func0(void *a1, int a2)\n{\n qsort(a1, a2, 4uLL, comparator);\n return a1;\n}", + "ida_strip_asm": "sub_1224:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+base], rdi\nmov [rbp+var_C], esi\nmov eax, [rbp+var_C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 4; size\nmov rdi, rax; base\ncall _qsort\nmov rax, [rbp+base]\nleave\nretn", + "ida_strip_pseudo": "void *__fastcall sub_1224(void *a1, int a2)\n{\n qsort(a1, a2, 4uLL, compar);\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1224(void *a1, int a2) {\n qsort(a1, a2, 4uLL, compar);\n return a1;\n}", + "ida_pseudo_norm": "void *func0(void *a1, int a2) {\n qsort(a1, a2, 4uLL, comparator);\n return a1;\n}" + }, + { + "index": 915, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n// Function to rearrange numbers based on the specified key\n\nint comparator(const void* a, const void* b) {\n\n int ia = *(int*)a;\n\n int ib = *(int*)b;\n\n\n\n double key_a = (ia == 0) ? 0.0 : (-1.0 / ia);\n\n double key_b = (ib == 0) ? 0.0 : (-1.0 / ib);\n\n\n\n if (key_a < key_b) return -1;\n\n if (key_a > key_b) return 1;\n\n return 0;\n\n}\n\n\n\n", + "func": "int* func0(int array_nums[], int size) {\n qsort(array_nums, size, sizeof(int), comparator);\n return array_nums;\n}", + "test": "int main() {\n\n // Test case 1\n\n int array1[] = {-1, 2, -3, 5, 7, 8, 9, -10};\n\n int expected1[] = {2, 5, 7, 8, 9, -10, -3, -1};\n\n int size1 = sizeof(array1) / sizeof(array1[0]);\n\n func0(array1, size1);\n\n for(int i = 0; i < size1; i++) {\n\n assert(array1[i] == expected1[i]);\n\n }\n\n\n\n // Test case 2\n\n int array2[] = {10, 15, 14, 13, -18, 12, -20};\n\n int expected2[] = {10, 12, 13, 14, 15, -20, -18};\n\n int size2 = sizeof(array2) / sizeof(array2[0]);\n\n func0(array2, size2);\n\n for(int i = 0; i < size2; i++) {\n\n assert(array2[i] == expected2[i]);\n\n }\n\n\n\n // Test case 3\n\n int array3[] = {-20, 20, -10, 10, -30, 30};\n\n int expected3[] = {10, 20, 30, -30, -20, -10};\n\n int size3 = sizeof(array3) / sizeof(array3[0]);\n\n func0(array3, size3);\n\n for(int i = 0; i < size3; i++) {\n\n assert(array3[i] == expected3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov %rdi,%rbx\nmovslq %esi,%rsi\nlea -0x79(%rip),%rcx\nmov $0x4,%edx\ncallq 1070 \nmov %rbx,%rax\npop %rbx\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov rbx, rdi\nmovsxd rsi, esi; nmemb\nlea rcx, comparator; compar\nmov edx, 4; size\ncall _qsort\nmov rax, rbx\npop rbx\nretn", + "ida_pseudo": "void *__fastcall func0(void *a1, int a2)\n{\n qsort(a1, a2, 4uLL, comparator);\n return a1;\n}", + "ida_strip_asm": "sub_11F0:\nendbr64\npush rbx\nmov rbx, rdi\nmovsxd rsi, esi; nmemb\nlea rcx, compar; compar\nmov edx, 4; size\ncall _qsort\nmov rax, rbx\npop rbx\nretn", + "ida_strip_pseudo": "void *__fastcall sub_11F0(void *a1, int a2)\n{\n qsort(a1, a2, 4uLL, compar);\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_11F0(void *a1, int a2) {\n qsort(a1, a2, 4uLL, compar);\n return a1;\n}", + "ida_pseudo_norm": "void *func0(void *a1, int a2) {\n qsort(a1, a2, 4uLL, comparator);\n return a1;\n}" + }, + { + "index": 916, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "bool func0(int A[], int arr_size, int sum, int* triplet) {\n for (int i = 0; i < arr_size - 2; i++) {\n for (int j = i + 1; j < arr_size - 1; j++) {\n for (int k = j + 1; k < arr_size; k++) {\n if (A[i] + A[j] + A[k] == sum) {\n triplet[0] = A[i];\n triplet[1] = A[j];\n triplet[2] = A[k];\n return true;\n }\n }\n }\n }\n return false;\n}", + "test": "int main() {\n\n int triplet[3];\n\n\n\n assert(func0((int[]){1, 4, 45, 6, 10, 8}, 6, 22, triplet) && triplet[0] == 4 && triplet[1] == 10 && triplet[2] == 8);\n\n assert(func0((int[]){12, 3, 5, 2, 6, 9}, 6, 24, triplet) && triplet[0] == 12 && triplet[1] == 3 && triplet[2] == 9);\n\n assert(func0((int[]){1, 2, 3, 4, 5}, 5, 9, triplet) && triplet[0] == 1 && triplet[1] == 3 && triplet[2] == 5);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmov %rcx,-0x28(%rbp)\nmovl $0x0,-0xc(%rbp)\njmpq 127c \nmov -0xc(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x8(%rbp)\njmpq 1269 \nmov -0x8(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x4(%rbp)\njmpq 1259 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\nadd %eax,%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\nadd %edx,%eax\ncmp %eax,-0x20(%rbp)\njne 1255 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x28(%rbp),%rax\nmov %edx,(%rax)\nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0x28(%rbp),%rdx\nadd $0x4,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0x28(%rbp),%rdx\nadd $0x8,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\nmov $0x1,%eax\njmp 1290 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11a7 \naddl $0x1,-0x8(%rbp)\nmov -0x1c(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x8(%rbp)\njl 1199 \naddl $0x1,-0xc(%rbp)\nmov -0x1c(%rbp),%eax\nsub $0x2,%eax\ncmp %eax,-0xc(%rbp)\njl 118b \nmov $0x0,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_28], rcx\nmov [rbp+var_C], 0\njmp loc_127C\nloc_118B:\nmov eax, [rbp+var_C]\nadd eax, 1\nmov [rbp+var_8], eax\njmp loc_1269\nloc_1199:\nmov eax, [rbp+var_8]\nadd eax, 1\nmov [rbp+var_4], eax\njmp loc_1259\nloc_11A7:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nadd edx, eax\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nadd eax, edx\ncmp [rbp+var_20], eax\njnz short loc_1255\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_28]\nmov [rax], edx\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rdx, [rbp+var_28]\nadd rdx, 4\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rdx, [rbp+var_28]\nadd rdx, 8\nmov eax, [rax]\nmov [rdx], eax\nmov eax, 1\njmp short loc_1290\nloc_1255:\nadd [rbp+var_4], 1\nloc_1259:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl loc_11A7\nadd [rbp+var_8], 1\nloc_1269:\nmov eax, [rbp+var_1C]\nsub eax, 1\ncmp [rbp+var_8], eax\njl loc_1199\nadd [rbp+var_C], 1\nloc_127C:\nmov eax, [rbp+var_1C]\nsub eax, 2\ncmp [rbp+var_C], eax\njl loc_118B\nmov eax, 0\nloc_1290:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3, _DWORD *a4)\n{\n int i; // [rsp+1Ch] [rbp-Ch]\n int j; // [rsp+20h] [rbp-8h]\n int k; // [rsp+24h] [rbp-4h]\n\n for ( i = 0; i < a2 - 2; ++i )\n {\n for ( j = i + 1; j < a2 - 1; ++j )\n {\n for ( k = j + 1; k < a2; ++k )\n {\n if ( a3 == *(_DWORD *)(4LL * j + a1) + *(_DWORD *)(4LL * i + a1) + *(_DWORD *)(4LL * k + a1) )\n {\n *a4 = *(_DWORD *)(4LL * i + a1);\n a4[1] = *(_DWORD *)(4LL * j + a1);\n a4[2] = *(_DWORD *)(4LL * k + a1);\n return 1LL;\n }\n }\n }\n }\n return 0LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_28], rcx\nmov [rbp+var_C], 0\njmp loc_127C\nloc_118B:\nmov eax, [rbp+var_C]\nadd eax, 1\nmov [rbp+var_8], eax\njmp loc_1269\nloc_1199:\nmov eax, [rbp+var_8]\nadd eax, 1\nmov [rbp+var_4], eax\njmp loc_1259\nloc_11A7:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nadd edx, eax\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nadd eax, edx\ncmp [rbp+var_20], eax\njnz short loc_1255\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_28]\nmov [rax], edx\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rdx, [rbp+var_28]\nadd rdx, 4\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rdx, [rbp+var_28]\nadd rdx, 8\nmov eax, [rax]\nmov [rdx], eax\nmov eax, 1\njmp short loc_1290\nloc_1255:\nadd [rbp+var_4], 1\nloc_1259:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl loc_11A7\nadd [rbp+var_8], 1\nloc_1269:\nmov eax, [rbp+var_1C]\nsub eax, 1\ncmp [rbp+var_8], eax\njl loc_1199\nadd [rbp+var_C], 1\nloc_127C:\nmov eax, [rbp+var_1C]\nsub eax, 2\ncmp [rbp+var_C], eax\njl loc_118B\nmov eax, 0\nloc_1290:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3, _DWORD *a4)\n{\n int i; // [rsp+1Ch] [rbp-Ch]\n int j; // [rsp+20h] [rbp-8h]\n int k; // [rsp+24h] [rbp-4h]\n\n for ( i = 0; i < a2 - 2; ++i )\n {\n for ( j = i + 1; j < a2 - 1; ++j )\n {\n for ( k = j + 1; k < a2; ++k )\n {\n if ( a3 == *(_DWORD *)(4LL * j + a1) + *(_DWORD *)(4LL * i + a1) + *(_DWORD *)(4LL * k + a1) )\n {\n *a4 = *(_DWORD *)(4LL * i + a1);\n a4[1] = *(_DWORD *)(4LL * j + a1);\n a4[2] = *(_DWORD *)(4LL * k + a1);\n return 1LL;\n }\n }\n }\n }\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3, uint32_t *a4) {\n int i;\n int j;\n int k;\n for (i = 0; i < a2 - 2; ++i) {\n for (j = i + 1; j < a2 - 1; ++j) {\n for (k = j + 1; k < a2; ++k) {\n if (a3 == *(uint32_t *)(4LL * j + a1) + *(uint32_t *)(4LL * i + a1) +\n *(uint32_t *)(4LL * k + a1)) {\n *a4 = *(uint32_t *)(4LL * i + a1);\n a4[1] = *(uint32_t *)(4LL * j + a1);\n a4[2] = *(uint32_t *)(4LL * k + a1);\n return 1LL;\n }\n }\n }\n }\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3, uint32_t *a4) {\n int i;\n int j;\n int k;\n for (i = 0; i < a2 - 2; ++i) {\n for (j = i + 1; j < a2 - 1; ++j) {\n for (k = j + 1; k < a2; ++k) {\n if (a3 == *(uint32_t *)(4LL * j + a1) + *(uint32_t *)(4LL * i + a1) +\n *(uint32_t *)(4LL * k + a1)) {\n *a4 = *(uint32_t *)(4LL * i + a1);\n a4[1] = *(uint32_t *)(4LL * j + a1);\n a4[2] = *(uint32_t *)(4LL * k + a1);\n return 1LL;\n }\n }\n }\n }\n return 0LL;\n}" + }, + { + "index": 916, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "bool func0(int A[], int arr_size, int sum, int* triplet) {\n for (int i = 0; i < arr_size - 2; i++) {\n for (int j = i + 1; j < arr_size - 1; j++) {\n for (int k = j + 1; k < arr_size; k++) {\n if (A[i] + A[j] + A[k] == sum) {\n triplet[0] = A[i];\n triplet[1] = A[j];\n triplet[2] = A[k];\n return true;\n }\n }\n }\n }\n return false;\n}", + "test": "int main() {\n\n int triplet[3];\n\n\n\n assert(func0((int[]){1, 4, 45, 6, 10, 8}, 6, 22, triplet) && triplet[0] == 4 && triplet[1] == 10 && triplet[2] == 8);\n\n assert(func0((int[]){12, 3, 5, 2, 6, 9}, 6, 24, triplet) && triplet[0] == 12 && triplet[1] == 3 && triplet[2] == 9);\n\n assert(func0((int[]){1, 2, 3, 4, 5}, 5, 9, triplet) && triplet[0] == 1 && triplet[1] == 3 && triplet[2] == 5);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x2,%esi\njle 125d \npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %rcx,%rbp\nlea 0x4(%rdi),%r14\nmov %esi,%eax\nlea -0x3(%rsi),%ecx\nlea 0x2(%rcx),%rbx\nmov %rbx,-0x8(%rsp)\nmov $0x1,%r12d\nlea -0x1(%rsi),%ebx\nmov %ebx,-0x10(%rsp)\nlea -0x2(%rsi),%ebx\nmov %ebx,-0xc(%rsp)\nsub $0x1,%eax\nmov %eax,-0x1c(%rsp)\nlea 0x8(%rdi),%r15\ncmp %r12d,-0x10(%rsp)\njle 1223 \nlea 0x1(%r12),%r11\nmov -0xc(%rsp),%eax\nsub %r12d,%eax\nlea 0x2(%r12,%rax,1),%rax\nmov %rax,-0x18(%rsp)\nmov %r14,%rbx\ncmp %r11d,%esi\njle 1214 \nmov -0x4(%r14),%r13d\nmov %rbx,-0x28(%rsp)\nmov %r13d,%r8d\nadd (%rbx),%r8d\nmovslq %r11d,%rax\nlea (%rdi,%rax,4),%rax\nmov -0x1c(%rsp),%ecx\nsub %r11d,%ecx\nlea -0x1(%r11,%rcx,1),%rcx\nlea (%r15,%rcx,4),%r9\nmov %rax,%r10\nmov %r8d,%ecx\nadd (%rax),%ecx\ncmp %edx,%ecx\nje 1239 \nadd $0x4,%rax\ncmp %r9,%rax\njne 11ff \nadd $0x1,%r11\nadd $0x4,%rbx\ncmp -0x18(%rsp),%r11\njne 11d4 \nadd $0x1,%r12\nadd $0x4,%r14\ncmp -0x8(%rsp),%r12\njne 11b4 \nmov $0x0,%eax\njmp 1252 \nmov %r13d,0x0(%rbp)\nmov -0x28(%rsp),%rax\nmov (%rax),%eax\nmov %eax,0x4(%rbp)\nmov (%r10),%eax\nmov %eax,0x8(%rbp)\nmov $0x1,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmov $0x0,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov r9d, esi\ncmp esi, 2\njle loc_1250\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r10, rdi\nmov esi, edx\nmov rdx, rcx\nlea r13, [rdi+4]\nlea edi, [r9-1]\nmov ecx, 1\nlea ebx, [r9-1]\nlea r14, [r10+8]\nmov r8, rcx\nmov rcx, rdx\nmov edx, r9d\nloc_11A9:\nmov r11d, r8d\ncmp ebx, r8d\njle short loc_1216\nmov rbp, r13\nmov r15, r8\nmov [rsp+30h+var_40], r8\nmov [rsp+30h+var_38], rdi\nloc_11C1:\nadd r11d, 1\ncmp edx, r11d\njle short loc_11FF\nmov r12d, [r13-4]\nmov [rsp+30h+var_48], rbp\nmov r8d, r12d\nadd r8d, [rbp+0]\nmovsxd rax, r11d\nlea rax, [r10+rax*4]\nmov edi, ebx\nsub edi, r11d\nadd rdi, r15\nlea r9, [r14+rdi*4]\nloc_11ED:\nmov edi, r8d\nadd edi, [rax]\ncmp edi, esi\njz short loc_122A\nadd rax, 4\ncmp rax, r9\njnz short loc_11ED\nloc_11FF:\nadd r15, 1\nadd rbp, 4\ncmp r11d, ebx\njnz short loc_11C1\nmov r8, [rsp+30h+var_40]\nmov rdi, [rsp+30h+var_38]\nloc_1216:\nadd r8, 1\nadd r13, 4\ncmp r8, rdi\njnz short loc_11A9\nmov eax, 0\njmp short loc_1245\nloc_122A:\nmov r15, [rsp+30h+var_48]\nmov rdx, rcx\nmov [rcx], r12d\nmov ecx, [r15]\nmov [rdx+4], ecx\nmov eax, [rax]\nmov [rdx+8], eax\nmov eax, 1\nloc_1245:\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1250:\nmov eax, 0\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3, _DWORD *a4)\n{\n _DWORD *v4; // r13\n int v5; // ebx\n __int64 v6; // r8\n int v7; // r11d\n _DWORD *v8; // rbp\n __int64 v9; // r15\n int v10; // r12d\n _DWORD *v11; // rax\n\n if ( a2 <= 2 )\n return 0LL;\n v4 = (_DWORD *)(a1 + 4);\n v5 = a2 - 1;\n v6 = 1LL;\n while ( 1 )\n {\n v7 = v6;\n if ( v5 > (int)v6 )\n break;\nLABEL_10:\n ++v6;\n ++v4;\n if ( v6 == a2 - 1 )\n return 0LL;\n }\n v8 = v4;\n v9 = v6;\n while ( a2 <= ++v7 )\n {\nLABEL_9:\n ++v9;\n ++v8;\n if ( v7 == v5 )\n goto LABEL_10;\n }\n v10 = *(v4 - 1);\n v11 = (_DWORD *)(a1 + 4LL * v7);\n while ( *v11 + *v8 + v10 != a3 )\n {\n if ( ++v11 == (_DWORD *)(a1 + 8 + 4 * (v9 + (unsigned int)(v5 - v7))) )\n goto LABEL_9;\n }\n *a4 = v10;\n a4[1] = *v8;\n a4[2] = *v11;\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov r9d, esi\ncmp esi, 2\njle loc_1250\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r10, rdi\nmov esi, edx\nmov rdx, rcx\nlea r13, [rdi+4]\nlea edi, [r9-1]\nmov ecx, 1\nlea ebx, [r9-1]\nlea r14, [r10+8]\nmov r8, rcx\nmov rcx, rdx\nmov edx, r9d\nloc_11A9:\nmov r11d, r8d\ncmp ebx, r8d\njle short loc_1216\nmov rbp, r13\nmov r15, r8\nmov [rsp+30h+var_40], r8\nmov [rsp+30h+var_38], rdi\nloc_11C1:\nadd r11d, 1\ncmp edx, r11d\njle short loc_11FF\nmov r12d, [r13-4]\nmov [rsp+30h+var_48], rbp\nmov r8d, r12d\nadd r8d, [rbp+0]\nmovsxd rax, r11d\nlea rax, [r10+rax*4]\nmov edi, ebx\nsub edi, r11d\nadd rdi, r15\nlea r9, [r14+rdi*4]\nloc_11ED:\nmov edi, r8d\nadd edi, [rax]\ncmp edi, esi\njz short loc_122A\nadd rax, 4\ncmp rax, r9\njnz short loc_11ED\nloc_11FF:\nadd r15, 1\nadd rbp, 4\ncmp r11d, ebx\njnz short loc_11C1\nmov r8, [rsp+30h+var_40]\nmov rdi, [rsp+30h+var_38]\nloc_1216:\nadd r8, 1\nadd r13, 4\ncmp r8, rdi\njnz short loc_11A9\nmov eax, 0\njmp short loc_1245\nloc_122A:\nmov r15, [rsp+30h+var_48]\nmov rdx, rcx\nmov [rcx], r12d\nmov ecx, [r15]\nmov [rdx+4], ecx\nmov eax, [rax]\nmov [rdx+8], eax\nmov eax, 1\nloc_1245:\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1250:\nmov eax, 0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3, _DWORD *a4)\n{\n _DWORD *v4; // r13\n int v5; // ebx\n __int64 v6; // r8\n int v7; // r11d\n _DWORD *v8; // rbp\n __int64 v9; // r15\n int v10; // r12d\n _DWORD *v11; // rax\n\n if ( a2 <= 2 )\n return 0LL;\n v4 = (_DWORD *)(a1 + 4);\n v5 = a2 - 1;\n v6 = 1LL;\n while ( 1 )\n {\n v7 = v6;\n if ( v5 > (int)v6 )\n break;\nLABEL_10:\n ++v6;\n ++v4;\n if ( v6 == a2 - 1 )\n return 0LL;\n }\n v8 = v4;\n v9 = v6;\n while ( a2 <= ++v7 )\n {\nLABEL_9:\n ++v9;\n ++v8;\n if ( v7 == v5 )\n goto LABEL_10;\n }\n v10 = *(v4 - 1);\n v11 = (_DWORD *)(a1 + 4LL * v7);\n while ( *v11 + *v8 + v10 != a3 )\n {\n if ( ++v11 == (_DWORD *)(a1 + 8 + 4 * (v9 + (unsigned int)(v5 - v7))) )\n goto LABEL_9;\n }\n *a4 = v10;\n a4[1] = *v8;\n a4[2] = *v11;\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3, uint32_t *a4) {\n uint32_t *v4;\n int v5;\n long long v6;\n int v7;\n uint32_t *v8;\n long long v9;\n int v10;\n uint32_t *v11;\n if (a2 <= 2) return 0LL;\n v4 = (uint32_t *)(a1 + 4);\n v5 = a2 - 1;\n v6 = 1LL;\n while (1) {\n v7 = v6;\n if (v5 > (int)v6) break;\n LABEL_10:\n ++v6;\n ++v4;\n if (v6 == a2 - 1) return 0LL;\n }\n v8 = v4;\n v9 = v6;\n while (a2 <= ++v7) {\n LABEL_9:\n ++v9;\n ++v8;\n if (v7 == v5) goto LABEL_10;\n }\n v10 = *(v4 - 1);\n v11 = (uint32_t *)(a1 + 4LL * v7);\n while (*v11 + *v8 + v10 != a3) {\n if (++v11 == (uint32_t *)(a1 + 8 + 4 * (v9 + (unsigned int)(v5 - v7))))\n goto LABEL_9;\n }\n *a4 = v10;\n a4[1] = *v8;\n a4[2] = *v11;\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3, uint32_t *a4) {\n uint32_t *v4;\n int v5;\n long long v6;\n int v7;\n uint32_t *v8;\n long long v9;\n int v10;\n uint32_t *v11;\n if (a2 <= 2) return 0LL;\n v4 = (uint32_t *)(a1 + 4);\n v5 = a2 - 1;\n v6 = 1LL;\n while (1) {\n v7 = v6;\n if (v5 > (int)v6) break;\n LABEL_10:\n ++v6;\n ++v4;\n if (v6 == a2 - 1) return 0LL;\n }\n v8 = v4;\n v9 = v6;\n while (a2 <= ++v7) {\n LABEL_9:\n ++v9;\n ++v8;\n if (v7 == v5) goto LABEL_10;\n }\n v10 = *(v4 - 1);\n v11 = (uint32_t *)(a1 + 4LL * v7);\n while (*v11 + *v8 + v10 != a3) {\n if (++v11 == (uint32_t *)(a1 + 8 + 4 * (v9 + (unsigned int)(v5 - v7))))\n goto LABEL_9;\n }\n *a4 = v10;\n a4[1] = *v8;\n a4[2] = *v11;\n return 1LL;\n}" + }, + { + "index": 916, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "bool func0(int A[], int arr_size, int sum, int* triplet) {\n for (int i = 0; i < arr_size - 2; i++) {\n for (int j = i + 1; j < arr_size - 1; j++) {\n for (int k = j + 1; k < arr_size; k++) {\n if (A[i] + A[j] + A[k] == sum) {\n triplet[0] = A[i];\n triplet[1] = A[j];\n triplet[2] = A[k];\n return true;\n }\n }\n }\n }\n return false;\n}", + "test": "int main() {\n\n int triplet[3];\n\n\n\n assert(func0((int[]){1, 4, 45, 6, 10, 8}, 6, 22, triplet) && triplet[0] == 4 && triplet[1] == 10 && triplet[2] == 8);\n\n assert(func0((int[]){12, 3, 5, 2, 6, 9}, 6, 24, triplet) && triplet[0] == 12 && triplet[1] == 3 && triplet[2] == 9);\n\n assert(func0((int[]){1, 2, 3, 4, 5}, 5, 9, triplet) && triplet[0] == 1 && triplet[1] == 3 && triplet[2] == 5);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x2,%esi\njle 1415 \npush %r15\nlea -0x3(%rsi),%eax\nlea 0x8(%rdi),%r15\npush %r14\nadd $0x2,%rax\npush %r13\nlea -0x1(%rsi),%r13d\npush %r12\nlea 0x4(%rdi),%r12\npush %rbp\npush %rbx\nlea -0x2(%rsi),%ebx\nmov %ebx,-0xc(%rsp)\nmov %rax,-0x8(%rsp)\nmov $0x1,%eax\nlea 0x1(%rax),%r14\ncmp %eax,%r13d\njle 13ff \nmov -0xc(%rsp),%r8d\nmov %r14,%r11\nmov %r12,%rbx\nsub %eax,%r8d\nlea 0x2(%rax,%r8,1),%rax\nmov %rax,-0x18(%rsp)\ncmp %r11d,%esi\njle 13f0 \nmov %r13d,%r8d\nmov -0x4(%r12),%ebp\nmov (%rbx),%r9d\nmovslq %r11d,%rax\nsub %r11d,%r8d\nlea (%rdi,%rax,4),%rax\nlea -0x1(%r11,%r8,1),%r8\nadd %ebp,%r9d\nlea (%r15,%r8,4),%r10\njmp 13c9 \nnopl 0x0(%rax,%rax,1)\nadd $0x4,%rax\ncmp %rax,%r10\nje 13f0 \nmov (%rax),%r8d\nadd %r9d,%r8d\ncmp %edx,%r8d\njne 13c0 \nmov %ebp,(%rcx)\nmov (%rbx),%edx\nmov %edx,0x4(%rcx)\nmov (%rax),%eax\nmov %eax,0x8(%rcx)\nmov $0x1,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nadd $0x1,%r11\nadd $0x4,%rbx\ncmp -0x18(%rsp),%r11\njne 1390 \nmov %r14,%rax\nadd $0x4,%r12\ncmp -0x8(%rsp),%r14\njne 136b \nxor %eax,%eax\njmp 13e5 \nxor %eax,%eax\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmov r9d, esi\ncmp esi, 2\njle loc_13E3\npush r15\nlea r15d, [r9-1]\nmov esi, edx\nmov rdx, rcx\npush r14\nmov ecx, 1\nmov r10, rdi\nlea r14, [rdi+8]\npush r13\nmov r8, rcx\nlea r13, [rdi+4]\nmov rcx, rdx\npush r12\nmov edx, r9d\npush rbp\npush rbx\nmov rbx, r15\nmov [rsp+30h+var_40], r15\nloc_1344:\nmov ebp, r8d\ncmp ebx, r8d\njle short loc_13C9\nmov [rsp+30h+var_38], r8\nmov r11, r13\nmov r15, r8\nloc_1357:\nadd ebp, 1\ncmp edx, ebp\njle short loc_13B8\nmov edi, ebx\nmov r12d, [r13-4]\nmov r8d, [r11]\nmovsxd rax, ebp\nsub edi, ebp\nlea rax, [r10+rax*4]\nadd rdi, r15\nadd r8d, r12d\nlea r9, [r14+rdi*4]\njmp short loc_1389\nloc_1380:\nadd rax, 4\ncmp r9, rax\njz short loc_13B8\nloc_1389:\nmov edi, [rax]\nadd edi, r8d\ncmp edi, esi\njnz short loc_1380\nmov [rcx], r12d\nmov rdx, rcx\nmov ecx, [r11]\nmov [rdx+4], ecx\nmov eax, [rax]\nmov [rdx+8], eax\nmov eax, 1\nloc_13A8:\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_13B8:\nadd r15, 1\nadd r11, 4\ncmp ebp, ebx\njnz short loc_1357\nmov r8, [rsp+30h+var_38]\nloc_13C9:\nmov rax, [rsp+30h+var_40]\nadd r8, 1\nadd r13, 4\ncmp r8, rax\njnz loc_1344\nxor eax, eax\njmp short loc_13A8\nloc_13E3:\nxor eax, eax\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3, _DWORD *a4)\n{\n __int64 v4; // r8\n _DWORD *v5; // r13\n int v6; // ebx\n int v7; // ebp\n _DWORD *v8; // r11\n __int64 v9; // r15\n int v10; // r12d\n _DWORD *v11; // rax\n\n if ( a2 <= 2 )\n return 0LL;\n v4 = 1LL;\n v5 = (_DWORD *)(a1 + 4);\n v6 = a2 - 1;\n while ( 1 )\n {\n v7 = v4;\n if ( v6 > (int)v4 )\n break;\nLABEL_11:\n ++v4;\n ++v5;\n if ( v4 == a2 - 1 )\n return 0LL;\n }\n v8 = v5;\n v9 = v4;\n while ( a2 <= ++v7 )\n {\nLABEL_10:\n ++v9;\n ++v8;\n if ( v7 == v6 )\n goto LABEL_11;\n }\n v10 = *(v5 - 1);\n v11 = (_DWORD *)(a1 + 4LL * v7);\n while ( v10 + *v8 + *v11 != a3 )\n {\n if ( (_DWORD *)(a1 + 8 + 4 * (v9 + (unsigned int)(v6 - v7))) == ++v11 )\n goto LABEL_10;\n }\n *a4 = v10;\n a4[1] = *v8;\n a4[2] = *v11;\n return 1LL;\n}", + "ida_strip_asm": "sub_1300:\nendbr64\nmov r9d, esi\ncmp esi, 2\njle loc_13E3\npush r15\nlea r15d, [r9-1]\nmov esi, edx\nmov rdx, rcx\npush r14\nmov ecx, 1\nmov r10, rdi\nlea r14, [rdi+8]\npush r13\nmov r8, rcx\nlea r13, [rdi+4]\nmov rcx, rdx\npush r12\nmov edx, r9d\npush rbp\npush rbx\nmov rbx, r15\nmov [rsp+30h+var_40], r15\nloc_1344:\nmov ebp, r8d\ncmp ebx, r8d\njle short loc_13C9\nmov [rsp+30h+var_38], r8\nmov r11, r13\nmov r15, r8\nloc_1357:\nadd ebp, 1\ncmp edx, ebp\njle short loc_13B8\nmov edi, ebx\nmov r12d, [r13-4]\nmov r8d, [r11]\nmovsxd rax, ebp\nsub edi, ebp\nlea rax, [r10+rax*4]\nadd rdi, r15\nadd r8d, r12d\nlea r9, [r14+rdi*4]\njmp short loc_1389\nloc_1380:\nadd rax, 4\ncmp r9, rax\njz short loc_13B8\nloc_1389:\nmov edi, [rax]\nadd edi, r8d\ncmp edi, esi\njnz short loc_1380\nmov [rcx], r12d\nmov rdx, rcx\nmov ecx, [r11]\nmov [rdx+4], ecx\nmov eax, [rax]\nmov [rdx+8], eax\nmov eax, 1\nloc_13A8:\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_13B8:\nadd r15, 1\nadd r11, 4\ncmp ebp, ebx\njnz short loc_1357\nmov r8, [rsp+30h+var_38]\nloc_13C9:\nmov rax, [rsp+30h+var_40]\nadd r8, 1\nadd r13, 4\ncmp r8, rax\njnz loc_1344\nxor eax, eax\njmp short loc_13A8\nloc_13E3:\nxor eax, eax\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1300(__int64 a1, int a2, int a3, _DWORD *a4)\n{\n __int64 v4; // r8\n _DWORD *v5; // r13\n int v6; // ebx\n int v7; // ebp\n _DWORD *v8; // r11\n __int64 v9; // r15\n int v10; // r12d\n _DWORD *v11; // rax\n\n if ( a2 <= 2 )\n return 0LL;\n v4 = 1LL;\n v5 = (_DWORD *)(a1 + 4);\n v6 = a2 - 1;\n while ( 1 )\n {\n v7 = v4;\n if ( v6 > (int)v4 )\n break;\nLABEL_11:\n ++v4;\n ++v5;\n if ( v4 == a2 - 1 )\n return 0LL;\n }\n v8 = v5;\n v9 = v4;\n while ( a2 <= ++v7 )\n {\nLABEL_10:\n ++v9;\n ++v8;\n if ( v7 == v6 )\n goto LABEL_11;\n }\n v10 = *(v5 - 1);\n v11 = (_DWORD *)(a1 + 4LL * v7);\n while ( v10 + *v8 + *v11 != a3 )\n {\n if ( (_DWORD *)(a1 + 8 + 4 * (v9 + (unsigned int)(v6 - v7))) == ++v11 )\n goto LABEL_10;\n }\n *a4 = v10;\n a4[1] = *v8;\n a4[2] = *v11;\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1300(long long a1, int a2, int a3, uint32_t *a4) {\n long long v4;\n uint32_t *v5;\n int v6;\n int v7;\n uint32_t *v8;\n long long v9;\n int v10;\n uint32_t *v11;\n if (a2 <= 2) return 0LL;\n v4 = 1LL;\n v5 = (uint32_t *)(a1 + 4);\n v6 = a2 - 1;\n while (1) {\n v7 = v4;\n if (v6 > (int)v4) break;\n LABEL_11:\n ++v4;\n ++v5;\n if (v4 == a2 - 1) return 0LL;\n }\n v8 = v5;\n v9 = v4;\n while (a2 <= ++v7) {\n LABEL_10:\n ++v9;\n ++v8;\n if (v7 == v6) goto LABEL_11;\n }\n v10 = *(v5 - 1);\n v11 = (uint32_t *)(a1 + 4LL * v7);\n while (v10 + *v8 + *v11 != a3) {\n if ((uint32_t *)(a1 + 8 + 4 * (v9 + (unsigned int)(v6 - v7))) == ++v11)\n goto LABEL_10;\n }\n *a4 = v10;\n a4[1] = *v8;\n a4[2] = *v11;\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3, uint32_t *a4) {\n long long v4;\n uint32_t *v5;\n int v6;\n int v7;\n uint32_t *v8;\n long long v9;\n int v10;\n uint32_t *v11;\n if (a2 <= 2) return 0LL;\n v4 = 1LL;\n v5 = (uint32_t *)(a1 + 4);\n v6 = a2 - 1;\n while (1) {\n v7 = v4;\n if (v6 > (int)v4) break;\n LABEL_11:\n ++v4;\n ++v5;\n if (v4 == a2 - 1) return 0LL;\n }\n v8 = v5;\n v9 = v4;\n while (a2 <= ++v7) {\n LABEL_10:\n ++v9;\n ++v8;\n if (v7 == v6) goto LABEL_11;\n }\n v10 = *(v5 - 1);\n v11 = (uint32_t *)(a1 + 4LL * v7);\n while (v10 + *v8 + *v11 != a3) {\n if ((uint32_t *)(a1 + 8 + 4 * (v9 + (unsigned int)(v6 - v7))) == ++v11)\n goto LABEL_10;\n }\n *a4 = v10;\n a4[1] = *v8;\n a4[2] = *v11;\n return 1LL;\n}" + }, + { + "index": 916, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "bool func0(int A[], int arr_size, int sum, int* triplet) {\n for (int i = 0; i < arr_size - 2; i++) {\n for (int j = i + 1; j < arr_size - 1; j++) {\n for (int k = j + 1; k < arr_size; k++) {\n if (A[i] + A[j] + A[k] == sum) {\n triplet[0] = A[i];\n triplet[1] = A[j];\n triplet[2] = A[k];\n return true;\n }\n }\n }\n }\n return false;\n}", + "test": "int main() {\n\n int triplet[3];\n\n\n\n assert(func0((int[]){1, 4, 45, 6, 10, 8}, 6, 22, triplet) && triplet[0] == 4 && triplet[1] == 10 && triplet[2] == 8);\n\n assert(func0((int[]){12, 3, 5, 2, 6, 9}, 6, 24, triplet) && triplet[0] == 12 && triplet[1] == 3 && triplet[2] == 9);\n\n assert(func0((int[]){1, 2, 3, 4, 5}, 5, 9, triplet) && triplet[0] == 1 && triplet[1] == 3 && triplet[2] == 5);\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x2,%esi\njle 13d5 \npush %r15\nlea -0x3(%rsi),%eax\nlea 0x8(%rdi),%r15\npush %r14\nadd $0x2,%rax\npush %r13\nlea -0x1(%rsi),%r13d\npush %r12\nlea 0x4(%rdi),%r12\npush %rbp\npush %rbx\nlea -0x2(%rsi),%ebx\nmov %ebx,-0xc(%rsp)\nmov %rax,-0x8(%rsp)\nmov $0x1,%eax\nlea 0x1(%rax),%r14\ncmp %eax,%r13d\njle 13bf \nmov -0xc(%rsp),%r8d\nmov %r14,%r11\nmov %r12,%rbx\nsub %eax,%r8d\nlea 0x2(%rax,%r8,1),%rax\nmov %rax,-0x18(%rsp)\ncmp %r11d,%esi\njle 13b0 \nmov %r13d,%r8d\nmov -0x4(%r12),%ebp\nmov (%rbx),%r9d\nmovslq %r11d,%rax\nsub %r11d,%r8d\nlea (%rdi,%rax,4),%rax\nlea -0x1(%r11,%r8,1),%r8\nadd %ebp,%r9d\nlea (%r15,%r8,4),%r10\njmp 1389 \nnopl 0x0(%rax,%rax,1)\nadd $0x4,%rax\ncmp %rax,%r10\nje 13b0 \nmov (%rax),%r8d\nadd %r9d,%r8d\ncmp %edx,%r8d\njne 1380 \nmov %ebp,(%rcx)\nmov (%rbx),%edx\nmov %edx,0x4(%rcx)\nmov (%rax),%eax\nmov %eax,0x8(%rcx)\nmov $0x1,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nadd $0x1,%r11\nadd $0x4,%rbx\ncmp -0x18(%rsp),%r11\njne 1350 \nmov %r14,%rax\nadd $0x4,%r12\ncmp -0x8(%rsp),%r14\njne 132b \nxor %eax,%eax\njmp 13a5 \nxor %eax,%eax\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nmov r9d, esi\ncmp esi, 2\njle loc_13E3\npush r15\nlea r15d, [r9-1]\nmov esi, edx\nmov rdx, rcx\npush r14\nmov ecx, 1\nmov r10, rdi\nlea r14, [rdi+8]\npush r13\nmov r8, rcx\nlea r13, [rdi+4]\nmov rcx, rdx\npush r12\nmov edx, r9d\npush rbp\npush rbx\nmov rbx, r15\nmov [rsp+30h+var_40], r15\nloc_1344:\nmov ebp, r8d\ncmp ebx, r8d\njle short loc_13C9\nmov [rsp+30h+var_38], r8\nmov r11, r13\nmov r15, r8\nloc_1357:\nadd ebp, 1\ncmp edx, ebp\njle short loc_13B8\nmov edi, ebx\nmov r12d, [r13-4]\nmov r8d, [r11]\nmovsxd rax, ebp\nsub edi, ebp\nlea rax, [r10+rax*4]\nadd rdi, r15\nadd r8d, r12d\nlea r9, [r14+rdi*4]\njmp short loc_1389\nloc_1380:\nadd rax, 4\ncmp r9, rax\njz short loc_13B8\nloc_1389:\nmov edi, [rax]\nadd edi, r8d\ncmp edi, esi\njnz short loc_1380\nmov [rcx], r12d\nmov rdx, rcx\nmov ecx, [r11]\nmov [rdx+4], ecx\nmov eax, [rax]\nmov [rdx+8], eax\nmov eax, 1\nloc_13A8:\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_13B8:\nadd r15, 1\nadd r11, 4\ncmp ebp, ebx\njnz short loc_1357\nmov r8, [rsp+30h+var_38]\nloc_13C9:\nmov rax, [rsp+30h+var_40]\nadd r8, 1\nadd r13, 4\ncmp r8, rax\njnz loc_1344\nxor eax, eax\njmp short loc_13A8\nloc_13E3:\nxor eax, eax\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3, _DWORD *a4)\n{\n __int64 v4; // r8\n _DWORD *v5; // r13\n int v6; // ebx\n int v7; // ebp\n _DWORD *v8; // r11\n __int64 v9; // r15\n int v10; // r12d\n _DWORD *v11; // rax\n\n if ( a2 <= 2 )\n return 0LL;\n v4 = 1LL;\n v5 = (_DWORD *)(a1 + 4);\n v6 = a2 - 1;\n while ( 1 )\n {\n v7 = v4;\n if ( v6 > (int)v4 )\n break;\nLABEL_11:\n ++v4;\n ++v5;\n if ( v4 == a2 - 1 )\n return 0LL;\n }\n v8 = v5;\n v9 = v4;\n while ( a2 <= ++v7 )\n {\nLABEL_10:\n ++v9;\n ++v8;\n if ( v7 == v6 )\n goto LABEL_11;\n }\n v10 = *(v5 - 1);\n v11 = (_DWORD *)(a1 + 4LL * v7);\n while ( v10 + *v8 + *v11 != a3 )\n {\n if ( (_DWORD *)(a1 + 8 + 4 * (v9 + (unsigned int)(v6 - v7))) == ++v11 )\n goto LABEL_10;\n }\n *a4 = v10;\n a4[1] = *v8;\n a4[2] = *v11;\n return 1LL;\n}", + "ida_strip_asm": "sub_1300:\nendbr64\nmov r9d, esi\ncmp esi, 2\njle loc_13E3\npush r15\nlea r15d, [r9-1]\nmov esi, edx\nmov rdx, rcx\npush r14\nmov ecx, 1\nmov r10, rdi\nlea r14, [rdi+8]\npush r13\nmov r8, rcx\nlea r13, [rdi+4]\nmov rcx, rdx\npush r12\nmov edx, r9d\npush rbp\npush rbx\nmov rbx, r15\nmov [rsp+30h+var_40], r15\nloc_1344:\nmov ebp, r8d\ncmp ebx, r8d\njle short loc_13C9\nmov [rsp+30h+var_38], r8\nmov r11, r13\nmov r15, r8\nloc_1357:\nadd ebp, 1\ncmp edx, ebp\njle short loc_13B8\nmov edi, ebx\nmov r12d, [r13-4]\nmov r8d, [r11]\nmovsxd rax, ebp\nsub edi, ebp\nlea rax, [r10+rax*4]\nadd rdi, r15\nadd r8d, r12d\nlea r9, [r14+rdi*4]\njmp short loc_1389\nloc_1380:\nadd rax, 4\ncmp r9, rax\njz short loc_13B8\nloc_1389:\nmov edi, [rax]\nadd edi, r8d\ncmp edi, esi\njnz short loc_1380\nmov [rcx], r12d\nmov rdx, rcx\nmov ecx, [r11]\nmov [rdx+4], ecx\nmov eax, [rax]\nmov [rdx+8], eax\nmov eax, 1\nloc_13A8:\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_13B8:\nadd r15, 1\nadd r11, 4\ncmp ebp, ebx\njnz short loc_1357\nmov r8, [rsp+30h+var_38]\nloc_13C9:\nmov rax, [rsp+30h+var_40]\nadd r8, 1\nadd r13, 4\ncmp r8, rax\njnz loc_1344\nxor eax, eax\njmp short loc_13A8\nloc_13E3:\nxor eax, eax\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1300(__int64 a1, int a2, int a3, _DWORD *a4)\n{\n __int64 v4; // r8\n _DWORD *v5; // r13\n int v6; // ebx\n int v7; // ebp\n _DWORD *v8; // r11\n __int64 v9; // r15\n int v10; // r12d\n _DWORD *v11; // rax\n\n if ( a2 <= 2 )\n return 0LL;\n v4 = 1LL;\n v5 = (_DWORD *)(a1 + 4);\n v6 = a2 - 1;\n while ( 1 )\n {\n v7 = v4;\n if ( v6 > (int)v4 )\n break;\nLABEL_11:\n ++v4;\n ++v5;\n if ( v4 == a2 - 1 )\n return 0LL;\n }\n v8 = v5;\n v9 = v4;\n while ( a2 <= ++v7 )\n {\nLABEL_10:\n ++v9;\n ++v8;\n if ( v7 == v6 )\n goto LABEL_11;\n }\n v10 = *(v5 - 1);\n v11 = (_DWORD *)(a1 + 4LL * v7);\n while ( v10 + *v8 + *v11 != a3 )\n {\n if ( (_DWORD *)(a1 + 8 + 4 * (v9 + (unsigned int)(v6 - v7))) == ++v11 )\n goto LABEL_10;\n }\n *a4 = v10;\n a4[1] = *v8;\n a4[2] = *v11;\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1300(long long a1, int a2, int a3, uint32_t *a4) {\n long long v4;\n uint32_t *v5;\n int v6;\n int v7;\n uint32_t *v8;\n long long v9;\n int v10;\n uint32_t *v11;\n if (a2 <= 2) return 0LL;\n v4 = 1LL;\n v5 = (uint32_t *)(a1 + 4);\n v6 = a2 - 1;\n while (1) {\n v7 = v4;\n if (v6 > (int)v4) break;\n LABEL_11:\n ++v4;\n ++v5;\n if (v4 == a2 - 1) return 0LL;\n }\n v8 = v5;\n v9 = v4;\n while (a2 <= ++v7) {\n LABEL_10:\n ++v9;\n ++v8;\n if (v7 == v6) goto LABEL_11;\n }\n v10 = *(v5 - 1);\n v11 = (uint32_t *)(a1 + 4LL * v7);\n while (v10 + *v8 + *v11 != a3) {\n if ((uint32_t *)(a1 + 8 + 4 * (v9 + (unsigned int)(v6 - v7))) == ++v11)\n goto LABEL_10;\n }\n *a4 = v10;\n a4[1] = *v8;\n a4[2] = *v11;\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3, uint32_t *a4) {\n long long v4;\n uint32_t *v5;\n int v6;\n int v7;\n uint32_t *v8;\n long long v9;\n int v10;\n uint32_t *v11;\n if (a2 <= 2) return 0LL;\n v4 = 1LL;\n v5 = (uint32_t *)(a1 + 4);\n v6 = a2 - 1;\n while (1) {\n v7 = v4;\n if (v6 > (int)v4) break;\n LABEL_11:\n ++v4;\n ++v5;\n if (v4 == a2 - 1) return 0LL;\n }\n v8 = v5;\n v9 = v4;\n while (a2 <= ++v7) {\n LABEL_10:\n ++v9;\n ++v8;\n if (v7 == v6) goto LABEL_11;\n }\n v10 = *(v5 - 1);\n v11 = (uint32_t *)(a1 + 4LL * v7);\n while (v10 + *v8 + *v11 != a3) {\n if ((uint32_t *)(a1 + 8 + 4 * (v9 + (unsigned int)(v6 - v7))) == ++v11)\n goto LABEL_10;\n }\n *a4 = v10;\n a4[1] = *v8;\n a4[2] = *v11;\n return 1LL;\n}" + }, + { + "index": 917, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* text) {\n regex_t regex;\n int reti;\n char* patterns = \"[A-Z]+[a-z]+$\";\n regcomp(®ex, patterns, REG_EXTENDED);\n reti = regexec(®ex, text, 0, NULL, 0);\n if (!reti) {\n return \"Found a match!\";\n } else {\n return \"Not matched!\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"AaBbGg\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\"aA\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"PYTHON\"), \"Not matched!\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x70,%rsp\nmov %rdi,-0x68(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0xe19(%rip),%rax\nmov %rax,-0x58(%rbp)\nmov -0x58(%rbp),%rcx\nlea -0x50(%rbp),%rax\nmov $0x1,%edx\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 10b0 \nmov -0x68(%rbp),%rsi\nlea -0x50(%rbp),%rax\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rax,%rdi\ncallq 10d0 \nmov %eax,-0x5c(%rbp)\ncmpl $0x0,-0x5c(%rbp)\njne 123d \nlea 0xddb(%rip),%rax\njmp 1244 \nlea 0xde1(%rip),%rax\nmov -0x8(%rbp),%rdx\nxor %fs:0x28,%rdx\nje 1258 \ncallq 1090 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aAZAZ; \"[A-Z]+[a-z]+$\"\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_5C], eax\ncmp [rbp+var_5C], 0\njnz short loc_123D\nlea rax, s2; \"Found a match!\"\njmp short loc_1244\nloc_123D:\nlea rax, aNotMatched; \"Not matched!\"\nloc_1244:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1258\ncall ___stack_chk_fail\nlocret_1258:\nleave\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n unsigned __int64 v3; // [rsp+68h] [rbp-8h]\n\n v3 = __readfsqword(0x28u);\n regcomp(&preg, \"[A-Z]+[a-z]+$\", 1);\n if ( regexec(&preg, a1, 0LL, 0LL, 0) )\n return \"Not matched!\";\n else\n return \"Found a match!\";\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aAZAZ; \"[A-Z]+[a-z]+$\"\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_5C], eax\ncmp [rbp+var_5C], 0\njnz short loc_123D\nlea rax, s2; \"Found a match!\"\njmp short loc_1244\nloc_123D:\nlea rax, aNotMatched; \"Not matched!\"\nloc_1244:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1258\ncall ___stack_chk_fail\nlocret_1258:\nleave\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_11C9(const char *a1)\n{\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n unsigned __int64 v3; // [rsp+68h] [rbp-8h]\n\n v3 = __readfsqword(0x28u);\n regcomp(&preg, \"[A-Z]+[a-z]+$\", 1);\n if ( regexec(&preg, a1, 0LL, 0LL, 0) )\n return \"Not matched!\";\n else\n return \"Found a match!\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_11C9(const char *a1) {\n regex_t preg;\n unsigned long long v3;\n v3 = __readfsqword(40u);\n regcomp(&preg, \"[A-Z]+[a-z]+$\", 1);\n if (regexec(&preg, a1, 0LL, 0LL, 0))\n return \"Not matched!\";\n else\n return \"Found a match!\";\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n regex_t preg;\n unsigned long long v3;\n v3 = __readfsqword(40u);\n regcomp(&preg, \"[A-Z]+[a-z]+$\", 1);\n if (regexec(&preg, a1, 0LL, 0LL, 0))\n return \"Not matched!\";\n else\n return \"Found a match!\";\n}" + }, + { + "index": 917, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* text) {\n regex_t regex;\n int reti;\n char* patterns = \"[A-Z]+[a-z]+$\";\n regcomp(®ex, patterns, REG_EXTENDED);\n reti = regexec(®ex, text, 0, NULL, 0);\n if (!reti) {\n return \"Found a match!\";\n } else {\n return \"Not matched!\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"AaBbGg\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\"aA\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"PYTHON\"), \"Not matched!\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x58,%rsp\nmov %rdi,%rbx\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%rbp\nmov $0x1,%edx\nlea 0xe4b(%rip),%rsi\nmov %rbp,%rdi\ncallq 10a0 \nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rbx,%rsi\nmov %rbp,%rdi\ncallq 10b0 \ntest %eax,%eax\nlea 0xe03(%rip),%rax\nlea 0xe0b(%rip),%rdx\ncmovne %rdx,%rax\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 1223 \nadd $0x58,%rsp\npop %rbx\npop %rbp\nretq\ncallq 1080 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov edx, 1; cflags\nlea rsi, pattern; \"[A-Z]+[a-z]+$\"\nmov rdi, rbp; preg\ncall _regcomp\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\ntest eax, eax\nlea rax, aNotMatched; \"Not matched!\"\nlea rdx, s2; \"Found a match!\"\ncmovz rax, rdx\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_1243\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1243:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n bool v1; // zf\n const char *result; // rax\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \"[A-Z]+[a-z]+$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0) == 0;\n result = \"Not matched!\";\n if ( v1 )\n return \"Found a match!\";\n return result;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov edx, 1; cflags\nlea rsi, pattern; \"[A-Z]+[a-z]+$\"\nmov rdi, rbp; preg\ncall _regcomp\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\ntest eax, eax\nlea rax, aNotMatched; \"Not matched!\"\nlea rdx, s2; \"Found a match!\"\ncmovz rax, rdx\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_1243\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1243:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_11C9(char *string)\n{\n bool v1; // zf\n const char *result; // rax\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \"[A-Z]+[a-z]+$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0) == 0;\n result = \"Not matched!\";\n if ( v1 )\n return \"Found a match!\";\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_11C9(char *string) {\n bool v1;\n const char *result;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \"[A-Z]+[a-z]+$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0) == 0;\n result = \"Not matched!\";\n if (v1) return \"Found a match!\";\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n bool v1;\n const char *result;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \"[A-Z]+[a-z]+$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0) == 0;\n result = \"Not matched!\";\n if (v1) return \"Found a match!\";\n return result;\n}" + }, + { + "index": 917, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* text) {\n regex_t regex;\n int reti;\n char* patterns = \"[A-Z]+[a-z]+$\";\n regcomp(®ex, patterns, REG_EXTENDED);\n reti = regexec(®ex, text, 0, NULL, 0);\n if (!reti) {\n return \"Found a match!\";\n } else {\n return \"Not matched!\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"AaBbGg\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\"aA\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"PYTHON\"), \"Not matched!\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov $0x1,%edx\nlea 0xd7e(%rip),%rsi\npush %rbp\nmov %rdi,%rbp\nsub $0x58,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%r12\nmov %r12,%rdi\ncallq 10a0 \nxor %ecx,%ecx\nxor %edx,%edx\nxor %r8d,%r8d\nmov %rbp,%rsi\nmov %r12,%rdi\ncallq 10b0 \nlea 0xd35(%rip),%rdx\ntest %eax,%eax\nlea 0xd1d(%rip),%rax\ncmovne %rdx,%rax\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 1303 \nadd $0x58,%rsp\npop %rbp\npop %r12\nretq\ncallq 1080 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"[A-Z]+[a-z]+$\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nlea rdx, s2; \"Found a match!\"\ntest eax, eax\nlea rax, aNotMatched; \"Not matched!\"\ncmovz rax, rdx\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_1311\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1311:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n bool v1; // zf\n const char *result; // rax\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \"[A-Z]+[a-z]+$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0) == 0;\n result = \"Not matched!\";\n if ( v1 )\n return \"Found a match!\";\n return result;\n}", + "ida_strip_asm": "sub_12A0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"[A-Z]+[a-z]+$\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nlea rdx, s2; \"Found a match!\"\ntest eax, eax\nlea rax, aNotMatched; \"Not matched!\"\ncmovz rax, rdx\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_1311\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1311:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_12A0(char *string)\n{\n bool v1; // zf\n const char *result; // rax\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \"[A-Z]+[a-z]+$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0) == 0;\n result = \"Not matched!\";\n if ( v1 )\n return \"Found a match!\";\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_12A0(char *string) {\n bool v1;\n const char *result;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \"[A-Z]+[a-z]+$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0) == 0;\n result = \"Not matched!\";\n if (v1) return \"Found a match!\";\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n bool v1;\n const char *result;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \"[A-Z]+[a-z]+$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0) == 0;\n result = \"Not matched!\";\n if (v1) return \"Found a match!\";\n return result;\n}" + }, + { + "index": 917, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* text) {\n regex_t regex;\n int reti;\n char* patterns = \"[A-Z]+[a-z]+$\";\n regcomp(®ex, patterns, REG_EXTENDED);\n reti = regexec(®ex, text, 0, NULL, 0);\n if (!reti) {\n return \"Found a match!\";\n } else {\n return \"Not matched!\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"AaBbGg\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\"aA\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"PYTHON\"), \"Not matched!\") == 0);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov $0x1,%edx\nlea 0xd7e(%rip),%rsi\npush %rbp\nmov %rdi,%rbp\nsub $0x58,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%r12\nmov %r12,%rdi\ncallq 10a0 \nxor %ecx,%ecx\nxor %edx,%edx\nxor %r8d,%r8d\nmov %rbp,%rsi\nmov %r12,%rdi\ncallq 10b0 \nlea 0xd35(%rip),%rdx\ntest %eax,%eax\nlea 0xd1d(%rip),%rax\ncmovne %rdx,%rax\nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 1303 \nadd $0x58,%rsp\npop %rbp\npop %r12\nretq\ncallq 1080 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"[A-Z]+[a-z]+$\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nlea rdx, s2; \"Found a match!\"\ntest eax, eax\nlea rax, aNotMatched; \"Not matched!\"\ncmovz rax, rdx\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_1311\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1311:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n bool v1; // zf\n const char *result; // rax\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \"[A-Z]+[a-z]+$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0) == 0;\n result = \"Not matched!\";\n if ( v1 )\n return \"Found a match!\";\n return result;\n}", + "ida_strip_asm": "sub_12A0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"[A-Z]+[a-z]+$\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nxor edx, edx; nmatch\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nlea rdx, s2; \"Found a match!\"\ntest eax, eax\nlea rax, aNotMatched; \"Not matched!\"\ncmovz rax, rdx\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_1311\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1311:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_12A0(char *string)\n{\n bool v1; // zf\n const char *result; // rax\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n regcomp(&_0, \"[A-Z]+[a-z]+$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0) == 0;\n result = \"Not matched!\";\n if ( v1 )\n return \"Found a match!\";\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_12A0(char *string) {\n bool v1;\n const char *result;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \"[A-Z]+[a-z]+$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0) == 0;\n result = \"Not matched!\";\n if (v1) return \"Found a match!\";\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n bool v1;\n const char *result;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n regcomp(&_0, \"[A-Z]+[a-z]+$\", 1);\n v1 = regexec(&_0, string, 0LL, 0LL, 0) == 0;\n result = \"Not matched!\";\n if (v1) return \"Found a match!\";\n return result;\n}" + }, + { + "index": 918, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int S[], int m, int n) {\n int table[n + 1][m];\n for (int i = 0; i < m; i++) {\n table[0][i] = 1;\n }\n for (int i = 1; i <= n; i++) {\n for (int j = 0; j < m; j++) {\n int x = (i - S[j] >= 0) ? table[i - S[j]][j] : 0;\n int y = (j >= 1) ? table[i][j - 1] : 0;\n table[i][j] = x + y;\n }\n }\n return table[n][m - 1];\n}", + "test": "int main() {\n\n int S1[] = {1, 2, 3};\n\n int m1 = 3;\n\n int n1 = 4;\n\n assert(func0(S1, m1, n1) == 4);\n\n\n\n int S2[] = {4, 5, 6, 7, 8, 9};\n\n int m2 = 6;\n\n int n2 = 9;\n\n assert(func0(S2, m2, n2) == 2);\n\n\n\n int S3[] = {4, 5, 6, 7, 8, 9};\n\n int m3 = 6;\n\n int n3 = 4;\n\n assert(func0(S3, m3, n3) == 1);\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0x78,%rsp\nmov %rdi,-0x78(%rbp)\nmov %esi,-0x7c(%rbp)\nmov %edx,-0x80(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nmov %rsp,%rax\nmov %rax,-0x98(%rbp)\nmov -0x7c(%rbp),%ecx\nmov -0x80(%rbp),%eax\nlea 0x1(%rax),%edi\nmovslq %ecx,%rax\nsub $0x1,%rax\nmov %rax,-0x50(%rbp)\nmovslq %ecx,%rax\nmov %rax,-0x90(%rbp)\nmovq $0x0,-0x88(%rbp)\nmovslq %ecx,%rax\nlea 0x0(,%rax,4),%rsi\nmovslq %edi,%rax\nsub $0x1,%rax\nmov %rax,-0x48(%rbp)\nmovslq %ecx,%rax\nmov %rax,%r14\nmov $0x0,%r15d\nmovslq %edi,%rax\nmov %rax,%r12\nmov $0x0,%r13d\nmov %r15,%rdx\nimul %r12,%rdx\nmov %r13,%rax\nimul %r14,%rax\nlea (%rdx,%rax,1),%rbx\nmov %r14,%rax\nmul %r12\nadd %rdx,%rbx\nmov %rbx,%rdx\nmovslq %ecx,%rax\nmov %rax,%r10\nmov $0x0,%r11d\nmovslq %edi,%rax\nmov %rax,%r8\nmov $0x0,%r9d\nmov %r11,%rdx\nimul %r8,%rdx\nmov %r9,%rax\nimul %r10,%rax\nlea (%rdx,%rax,1),%rbx\nmov %r10,%rax\nmul %r8\nlea (%rbx,%rdx,1),%r8\nmov %r8,%rdx\nmovslq %ecx,%rdx\nmovslq %edi,%rax\nimul %rdx,%rax\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%ebx\nmov $0x0,%edx\ndiv %rbx\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rbx\nsub %rdx,%rbx\nmov %rbx,%rdx\ncmp %rdx,%rsp\nje 12c6 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 12af \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 12f0 \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x40(%rbp)\nmovl $0x0,-0x5c(%rbp)\njmp 1321 \nmov -0x40(%rbp),%rax\nmov -0x5c(%rbp),%edx\nmovslq %edx,%rdx\nmovl $0x1,(%rax,%rdx,4)\naddl $0x1,-0x5c(%rbp)\nmov -0x5c(%rbp),%eax\ncmp -0x7c(%rbp),%eax\njl 130c \nmovl $0x1,-0x60(%rbp)\njmpq 141a \nmovl $0x0,-0x64(%rbp)\njmpq 140a \nmov -0x64(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x78(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov -0x60(%rbp),%edx\nsub %eax,%edx\nmov %edx,%eax\ntest %eax,%eax\njs 13a0 \nmov %rsi,%rdi\nshr $0x2,%rdi\nmov -0x64(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x78(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov -0x60(%rbp),%edx\nsub %eax,%edx\nmov %edx,%r8d\nmov -0x40(%rbp),%rax\nmov -0x64(%rbp),%edx\nmovslq %edx,%rcx\nmovslq %r8d,%rdx\nimul %rdi,%rdx\nadd %rcx,%rdx\nmov (%rax,%rdx,4),%eax\njmp 13a5 \nmov $0x0,%eax\nmov %eax,-0x58(%rbp)\ncmpl $0x0,-0x64(%rbp)\njle 13d4 \nmov %rsi,%rdi\nshr $0x2,%rdi\nmov -0x64(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x40(%rbp),%rax\nmovslq %edx,%rcx\nmov -0x60(%rbp),%edx\nmovslq %edx,%rdx\nimul %rdi,%rdx\nadd %rcx,%rdx\nmov (%rax,%rdx,4),%eax\njmp 13d9 \nmov $0x0,%eax\nmov %eax,-0x54(%rbp)\nmov %rsi,%r8\nshr $0x2,%r8\nmov -0x58(%rbp),%edx\nmov -0x54(%rbp),%eax\nlea (%rdx,%rax,1),%ecx\nmov -0x40(%rbp),%rax\nmov -0x64(%rbp),%edx\nmovslq %edx,%rdi\nmov -0x60(%rbp),%edx\nmovslq %edx,%rdx\nimul %r8,%rdx\nadd %rdi,%rdx\nmov %ecx,(%rax,%rdx,4)\naddl $0x1,-0x64(%rbp)\nmov -0x64(%rbp),%eax\ncmp -0x7c(%rbp),%eax\njl 1341 \naddl $0x1,-0x60(%rbp)\nmov -0x60(%rbp),%eax\ncmp -0x80(%rbp),%eax\njle 1335 \nshr $0x2,%rsi\nmov -0x7c(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x40(%rbp),%rax\nmovslq %edx,%rcx\nmov -0x80(%rbp),%edx\nmovslq %edx,%rdx\nimul %rsi,%rdx\nadd %rcx,%rdx\nmov (%rax,%rdx,4),%eax\nmov -0x98(%rbp),%rsp\nmov -0x38(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 1462 \ncallq 1080 <__stack_chk_fail@plt>\nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 58h\nmov [rbp+var_58], rdi\nmov [rbp+var_5C], esi\nmov [rbp+var_60], edx\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov rax, rsp\nmov r11, rax\nmov esi, [rbp+var_5C]\nmov eax, [rbp+var_60]\nlea r8d, [rax+1]\nmovsxd rax, esi\nsub rax, 1\nmov [rbp+var_30], rax\nmovsxd rax, esi\nlea rdi, ds:0[rax*4]\nmovsxd rax, r8d\nsub rax, 1\nmov [rbp+var_28], rax\nmovsxd rax, esi\nmov rcx, rax\nmov ebx, 0\nmovsxd rax, r8d\nmov rax, rax\nmov edx, 0\nmov r10, rbx\nimul r10, rax\nmov r9, rdx\nimul r9, rcx\nadd r9, r10\nmul rcx\nlea rcx, [r9+rdx]\nmov rdx, rcx\nmovsxd rax, esi\nmov rcx, rax\nmov ebx, 0\nmovsxd rax, r8d\nmov rax, rax\nmov edx, 0\nmov r10, rbx\nimul r10, rax\nmov r9, rdx\nimul r9, rcx\nadd r9, r10\nmul rcx\nlea rcx, [r9+rdx]\nmov rdx, rcx\nmovsxd rdx, esi\nmovsxd rax, r8d\nimul rax, rdx\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov ebx, 10h\nmov edx, 0\ndiv rbx\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_1281:\ncmp rsp, rdx\njz short loc_1298\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\njmp short loc_1281\nloc_1298:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_12C2\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_12C2:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_20], rax\nmov [rbp+var_44], 0\njmp short loc_12F3\nloc_12DE:\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_44]\nmovsxd rdx, edx\nmov dword ptr [rax+rdx*4], 1\nadd [rbp+var_44], 1\nloc_12F3:\nmov eax, [rbp+var_44]\ncmp eax, [rbp+var_5C]\njl short loc_12DE\nmov [rbp+var_40], 1\njmp loc_13EA\nloc_1307:\nmov [rbp+var_3C], 0\njmp loc_13DA\nloc_1313:\nmov eax, [rbp+var_3C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_40]\nsub edx, eax\ntest edx, edx\njs short loc_1370\nmov rsi, rdi\nshr rsi, 2\nmov eax, [rbp+var_3C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_40]\nsub edx, eax\nmov r8d, edx\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_3C]\nmovsxd rcx, edx\nmovsxd rdx, r8d\nimul rdx, rsi\nadd rdx, rcx\nmov eax, [rax+rdx*4]\njmp short loc_1375\nloc_1370:\nmov eax, 0\nloc_1375:\nmov [rbp+var_38], eax\ncmp [rbp+var_3C], 0\njle short loc_13A4\nmov rsi, rdi\nshr rsi, 2\nmov eax, [rbp+var_3C]\nlea edx, [rax-1]\nmov rax, [rbp+var_20]\nmovsxd rcx, edx\nmov edx, [rbp+var_40]\nmovsxd rdx, edx\nimul rdx, rsi\nadd rdx, rcx\nmov eax, [rax+rdx*4]\njmp short loc_13A9\nloc_13A4:\nmov eax, 0\nloc_13A9:\nmov [rbp+var_34], eax\nmov r8, rdi\nshr r8, 2\nmov edx, [rbp+var_38]\nmov eax, [rbp+var_34]\nlea ecx, [rdx+rax]\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_3C]\nmovsxd rsi, edx\nmov edx, [rbp+var_40]\nmovsxd rdx, edx\nimul rdx, r8\nadd rdx, rsi\nmov [rax+rdx*4], ecx\nadd [rbp+var_3C], 1\nloc_13DA:\nmov eax, [rbp+var_3C]\ncmp eax, [rbp+var_5C]\njl loc_1313\nadd [rbp+var_40], 1\nloc_13EA:\nmov eax, [rbp+var_40]\ncmp eax, [rbp+var_60]\njle loc_1307\nshr rdi, 2\nmov rsi, rdi\nmov eax, [rbp+var_5C]\nlea edx, [rax-1]\nmov rax, [rbp+var_20]\nmovsxd rcx, edx\nmov edx, [rbp+var_60]\nmovsxd rdx, edx\nimul rdx, rsi\nadd rdx, rcx\nmov eax, [rax+rdx*4]\nmov rsp, r11\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njz short loc_1431\ncall ___stack_chk_fail\nloc_1431:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n unsigned __int64 v3; // rdi\n unsigned __int64 v4; // rax\n void *v5; // rsp\n int v6; // eax\n int v7; // eax\n int v9; // [rsp+8h] [rbp-60h] BYREF\n int v10; // [rsp+Ch] [rbp-5Ch]\n __int64 v11; // [rsp+10h] [rbp-58h]\n int i; // [rsp+24h] [rbp-44h]\n int j; // [rsp+28h] [rbp-40h]\n int k; // [rsp+2Ch] [rbp-3Ch]\n int v15; // [rsp+30h] [rbp-38h]\n int v16; // [rsp+34h] [rbp-34h]\n __int64 v17; // [rsp+38h] [rbp-30h]\n __int64 v18; // [rsp+40h] [rbp-28h]\n int *v19; // [rsp+48h] [rbp-20h]\n unsigned __int64 v20; // [rsp+50h] [rbp-18h]\n\n v11 = a1;\n v10 = a2;\n v9 = a3;\n v20 = __readfsqword(0x28u);\n v17 = a2 - 1LL;\n v3 = 4LL * a2;\n v18 = a3 + 1 - 1LL;\n v4 = 16 * ((4 * a2 * (__int64)(a3 + 1) + 15) / 0x10uLL);\n while ( &v9 != (int *)((char *)&v9 - (v4 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v5 = alloca(v4 & 0xFFF);\n if ( (v4 & 0xFFF) != 0 )\n *(_QWORD *)((char *)&v9 + (v4 & 0xFFF) - 8) = *(_QWORD *)((char *)&v9 + (v4 & 0xFFF) - 8);\n v19 = &v9;\n for ( i = 0; i < v10; ++i )\n v19[i] = 1;\n for ( j = 1; j <= v9; ++j )\n {\n for ( k = 0; k < v10; ++k )\n {\n if ( j - *(_DWORD *)(4LL * k + v11) < 0 )\n v6 = 0;\n else\n v6 = v19[k + (v3 >> 2) * (j - *(_DWORD *)(4LL * k + v11))];\n v15 = v6;\n if ( k <= 0 )\n v7 = 0;\n else\n v7 = v19[k - 1 + (v3 >> 2) * j];\n v16 = v7;\n v19[k + (v3 >> 2) * j] = v15 + v7;\n }\n }\n return (unsigned int)v19[v10 - 1 + (v3 >> 2) * v9];\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 58h\nmov [rbp+var_58], rdi\nmov [rbp+var_5C], esi\nmov [rbp+var_60], edx\nmov rax, fs:28h\nmov [rbp+var_18], rax\nxor eax, eax\nmov rax, rsp\nmov r11, rax\nmov esi, [rbp+var_5C]\nmov eax, [rbp+var_60]\nlea r8d, [rax+1]\nmovsxd rax, esi\nsub rax, 1\nmov [rbp+var_30], rax\nmovsxd rax, esi\nlea rdi, ds:0[rax*4]\nmovsxd rax, r8d\nsub rax, 1\nmov [rbp+var_28], rax\nmovsxd rax, esi\nmov rcx, rax\nmov ebx, 0\nmovsxd rax, r8d\nmov rax, rax\nmov edx, 0\nmov r10, rbx\nimul r10, rax\nmov r9, rdx\nimul r9, rcx\nadd r9, r10\nmul rcx\nlea rcx, [r9+rdx]\nmov rdx, rcx\nmovsxd rax, esi\nmov rcx, rax\nmov ebx, 0\nmovsxd rax, r8d\nmov rax, rax\nmov edx, 0\nmov r10, rbx\nimul r10, rax\nmov r9, rdx\nimul r9, rcx\nadd r9, r10\nmul rcx\nlea rcx, [r9+rdx]\nmov rdx, rcx\nmovsxd rdx, esi\nmovsxd rax, r8d\nimul rax, rdx\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov ebx, 10h\nmov edx, 0\ndiv rbx\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_1281:\ncmp rsp, rdx\njz short loc_1298\nsub rsp, 1000h\nor [rsp+1060h+var_68], 0\njmp short loc_1281\nloc_1298:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_12C2\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_12C2:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_20], rax\nmov [rbp+var_44], 0\njmp short loc_12F3\nloc_12DE:\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_44]\nmovsxd rdx, edx\nmov dword ptr [rax+rdx*4], 1\nadd [rbp+var_44], 1\nloc_12F3:\nmov eax, [rbp+var_44]\ncmp eax, [rbp+var_5C]\njl short loc_12DE\nmov [rbp+var_40], 1\njmp loc_13EA\nloc_1307:\nmov [rbp+var_3C], 0\njmp loc_13DA\nloc_1313:\nmov eax, [rbp+var_3C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_40]\nsub edx, eax\ntest edx, edx\njs short loc_1370\nmov rsi, rdi\nshr rsi, 2\nmov eax, [rbp+var_3C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_58]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_40]\nsub edx, eax\nmov r8d, edx\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_3C]\nmovsxd rcx, edx\nmovsxd rdx, r8d\nimul rdx, rsi\nadd rdx, rcx\nmov eax, [rax+rdx*4]\njmp short loc_1375\nloc_1370:\nmov eax, 0\nloc_1375:\nmov [rbp+var_38], eax\ncmp [rbp+var_3C], 0\njle short loc_13A4\nmov rsi, rdi\nshr rsi, 2\nmov eax, [rbp+var_3C]\nlea edx, [rax-1]\nmov rax, [rbp+var_20]\nmovsxd rcx, edx\nmov edx, [rbp+var_40]\nmovsxd rdx, edx\nimul rdx, rsi\nadd rdx, rcx\nmov eax, [rax+rdx*4]\njmp short loc_13A9\nloc_13A4:\nmov eax, 0\nloc_13A9:\nmov [rbp+var_34], eax\nmov r8, rdi\nshr r8, 2\nmov edx, [rbp+var_38]\nmov eax, [rbp+var_34]\nlea ecx, [rdx+rax]\nmov rax, [rbp+var_20]\nmov edx, [rbp+var_3C]\nmovsxd rsi, edx\nmov edx, [rbp+var_40]\nmovsxd rdx, edx\nimul rdx, r8\nadd rdx, rsi\nmov [rax+rdx*4], ecx\nadd [rbp+var_3C], 1\nloc_13DA:\nmov eax, [rbp+var_3C]\ncmp eax, [rbp+var_5C]\njl loc_1313\nadd [rbp+var_40], 1\nloc_13EA:\nmov eax, [rbp+var_40]\ncmp eax, [rbp+var_60]\njle loc_1307\nshr rdi, 2\nmov rsi, rdi\nmov eax, [rbp+var_5C]\nlea edx, [rax-1]\nmov rax, [rbp+var_20]\nmovsxd rcx, edx\nmov edx, [rbp+var_60]\nmovsxd rdx, edx\nimul rdx, rsi\nadd rdx, rcx\nmov eax, [rax+rdx*4]\nmov rsp, r11\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njz short loc_1431\ncall ___stack_chk_fail\nloc_1431:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2, int a3)\n{\n unsigned __int64 v3; // rdi\n unsigned __int64 v4; // rax\n void *v5; // rsp\n int v6; // eax\n int v7; // eax\n int v9; // [rsp+8h] [rbp-60h] BYREF\n int v10; // [rsp+Ch] [rbp-5Ch]\n __int64 v11; // [rsp+10h] [rbp-58h]\n int i; // [rsp+24h] [rbp-44h]\n int j; // [rsp+28h] [rbp-40h]\n int k; // [rsp+2Ch] [rbp-3Ch]\n int v15; // [rsp+30h] [rbp-38h]\n int v16; // [rsp+34h] [rbp-34h]\n __int64 v17; // [rsp+38h] [rbp-30h]\n __int64 v18; // [rsp+40h] [rbp-28h]\n int *v19; // [rsp+48h] [rbp-20h]\n unsigned __int64 v20; // [rsp+50h] [rbp-18h]\n\n v11 = a1;\n v10 = a2;\n v9 = a3;\n v20 = __readfsqword(0x28u);\n v17 = a2 - 1LL;\n v3 = 4LL * a2;\n v18 = a3 + 1 - 1LL;\n v4 = 16 * ((4 * a2 * (__int64)(a3 + 1) + 15) / 0x10uLL);\n while ( &v9 != (int *)((char *)&v9 - (v4 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v5 = alloca(v4 & 0xFFF);\n if ( (v4 & 0xFFF) != 0 )\n *(_QWORD *)((char *)&v9 + (v4 & 0xFFF) - 8) = *(_QWORD *)((char *)&v9 + (v4 & 0xFFF) - 8);\n v19 = &v9;\n for ( i = 0; i < v10; ++i )\n v19[i] = 1;\n for ( j = 1; j <= v9; ++j )\n {\n for ( k = 0; k < v10; ++k )\n {\n if ( j - *(_DWORD *)(4LL * k + v11) < 0 )\n v6 = 0;\n else\n v6 = v19[k + (v3 >> 2) * (j - *(_DWORD *)(4LL * k + v11))];\n v15 = v6;\n if ( k <= 0 )\n v7 = 0;\n else\n v7 = v19[k - 1 + (v3 >> 2) * j];\n v16 = v7;\n v19[k + (v3 >> 2) * j] = v15 + v7;\n }\n }\n return (unsigned int)v19[v10 - 1 + (v3 >> 2) * v9];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2, int a3) {\n unsigned long long v3;\n unsigned long long v4;\n void *v5;\n int v6;\n int v7;\n int v9;\n int v10;\n long long v11;\n int i;\n int j;\n int k;\n int v15;\n int v16;\n long long v17;\n long long v18;\n int *v19;\n unsigned long long v20;\n v11 = a1;\n v10 = a2;\n v9 = a3;\n v20 = __readfsqword(40u);\n v17 = a2 - 1LL;\n v3 = 4LL * a2;\n v18 = a3 + 1 - 1LL;\n v4 = 16 * ((4 * a2 * (long long)(a3 + 1) + 15) / 16uLL);\n while (&v9 != (int *)((char *)&v9 - (v4 & 18446744073709547520LL)))\n ;\n v5 = alloca(v4 & 4095);\n if ((v4 & 4095) != 0)\n *(uint64_t *)((char *)&v9 + (v4 & 4095) - 8) =\n *(uint64_t *)((char *)&v9 + (v4 & 4095) - 8);\n v19 = &v9;\n for (i = 0; i < v10; ++i) v19[i] = 1;\n for (j = 1; j <= v9; ++j) {\n for (k = 0; k < v10; ++k) {\n if (j - *(uint32_t *)(4LL * k + v11) < 0)\n v6 = 0;\n else\n v6 = v19[k + (v3 >> 2) * (j - *(uint32_t *)(4LL * k + v11))];\n v15 = v6;\n if (k <= 0)\n v7 = 0;\n else\n v7 = v19[k - 1 + (v3 >> 2) * j];\n v16 = v7;\n v19[k + (v3 >> 2) * j] = v15 + v7;\n }\n }\n return (unsigned int)v19[v10 - 1 + (v3 >> 2) * v9];\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n unsigned long long v3;\n unsigned long long v4;\n void *v5;\n int v6;\n int v7;\n int v9;\n int v10;\n long long v11;\n int i;\n int j;\n int k;\n int v15;\n int v16;\n long long v17;\n long long v18;\n int *v19;\n unsigned long long v20;\n v11 = a1;\n v10 = a2;\n v9 = a3;\n v20 = __readfsqword(40u);\n v17 = a2 - 1LL;\n v3 = 4LL * a2;\n v18 = a3 + 1 - 1LL;\n v4 = 16 * ((4 * a2 * (long long)(a3 + 1) + 15) / 16uLL);\n while (&v9 != (int *)((char *)&v9 - (v4 & 18446744073709547520LL)))\n ;\n v5 = alloca(v4 & 4095);\n if ((v4 & 4095) != 0)\n *(uint64_t *)((char *)&v9 + (v4 & 4095) - 8) =\n *(uint64_t *)((char *)&v9 + (v4 & 4095) - 8);\n v19 = &v9;\n for (i = 0; i < v10; ++i) v19[i] = 1;\n for (j = 1; j <= v9; ++j) {\n for (k = 0; k < v10; ++k) {\n if (j - *(uint32_t *)(4LL * k + v11) < 0)\n v6 = 0;\n else\n v6 = v19[k + (v3 >> 2) * (j - *(uint32_t *)(4LL * k + v11))];\n v15 = v6;\n if (k <= 0)\n v7 = 0;\n else\n v7 = v19[k - 1 + (v3 >> 2) * j];\n v16 = v7;\n v19[k + (v3 >> 2) * j] = v15 + v7;\n }\n }\n return (unsigned int)v19[v10 - 1 + (v3 >> 2) * v9];\n}" + }, + { + "index": 918, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int S[], int m, int n) {\n int table[n + 1][m];\n for (int i = 0; i < m; i++) {\n table[0][i] = 1;\n }\n for (int i = 1; i <= n; i++) {\n for (int j = 0; j < m; j++) {\n int x = (i - S[j] >= 0) ? table[i - S[j]][j] : 0;\n int y = (j >= 1) ? table[i][j - 1] : 0;\n table[i][j] = x + y;\n }\n }\n return table[n][m - 1];\n}", + "test": "int main() {\n\n int S1[] = {1, 2, 3};\n\n int m1 = 3;\n\n int n1 = 4;\n\n assert(func0(S1, m1, n1) == 4);\n\n\n\n int S2[] = {4, 5, 6, 7, 8, 9};\n\n int m2 = 6;\n\n int n2 = 9;\n\n assert(func0(S2, m2, n2) == 2);\n\n\n\n int S3[] = {4, 5, 6, 7, 8, 9};\n\n int m3 = 6;\n\n int n3 = 4;\n\n assert(func0(S3, m3, n3) == 1);\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0x28,%rsp\nmov %esi,%r14d\nmov %edx,-0x44(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nmovslq %esi,%rcx\nlea 0x0(,%rcx,4),%r13\nadd $0x1,%edx\nmovslq %edx,%rax\nimul %rcx,%rax\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffffff0,%rdx\nand $0xfffffffffffff000,%rax\nmov %rsp,%rbx\nsub %rax,%rbx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 11fd \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11e6 \nmov %rdx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 1213 \norq $0x0,-0x8(%rsp,%rax,1)\nmov %rsp,%rbx\nmov %rbx,-0x50(%rbp)\nmov %rbx,%r12\ntest %r14d,%r14d\njle 123d \nmov %rbx,%rax\nlea -0x1(%r14),%edx\nlea 0x4(%rbx,%rdx,4),%rdx\nmovl $0x1,(%rax)\nadd $0x4,%rax\ncmp %rdx,%rax\njne 122e \nmov -0x44(%rbp),%eax\ntest %eax,%eax\njle 12c2 \nmov %r13,%rbx\nshr $0x2,%rbx\nmov -0x50(%rbp),%rsi\nlea (%rsi,%r13,1),%r10\nlea 0x1(%rax),%r15d\nmov %r10,%rsi\nmov $0x1,%r8d\nlea -0x1(%r14),%r11d\nmov $0x0,%r9d\njmp 12b6 \nmov %r9d,%edx\ntest %eax,%eax\njle 1277 \nmov -0x4(%rsi,%rax,4),%edx\nadd %ecx,%edx\nmov %edx,(%r10,%rax,4)\nlea 0x1(%rax),%rdx\ncmp %r11,%rax\nje 12a7 \nmov %rdx,%rax\nmov %r9d,%ecx\nmov %r8d,%edx\nsub (%rdi,%rax,4),%edx\njs 126c \nmovslq %eax,%rcx\nmovslq %edx,%rdx\nimul %rbx,%rdx\nadd %rcx,%rdx\nmov (%r12,%rdx,4),%ecx\njmp 126c \nadd $0x1,%r8d\nadd %r13,%r10\nadd %r13,%rsi\ncmp %r15d,%r8d\nje 12c2 \nmov $0x0,%eax\ntest %r14d,%r14d\njg 1289 \njmp 12a7 \nlea -0x1(%r14),%eax\nmovslq %eax,%rdx\nmovslq -0x44(%rbp),%rax\nshr $0x2,%r13\nimul %rax,%r13\nlea (%rdx,%r13,1),%rax\nmov -0x50(%rbp),%rbx\nmov (%rbx,%rax,4),%eax\nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\njne 12fe \nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\ncallq 1080 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 28h\nmov r14d, esi\nmov [rbp+var_44], edx\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nmovsxd r10, esi\nlea r13, ds:0[r10*4]\nlea eax, [rdx+1]\ncdqe\nimul rax, r10\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11E2:\ncmp rsp, rdx\njz short loc_11F9\nsub rsp, 1000h\nor [rsp+1050h+var_58], 0\njmp short loc_11E2\nloc_11F9:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_120F\nor [rsp+rax+50h+var_58], 0\nloc_120F:\nmov rbx, rsp\ntest r14d, r14d\njle short loc_122D\nmov rax, rbx\nlea rdx, [rbx+r13]\nloc_121E:\nmov dword ptr [rax], 1\nadd rax, 4\ncmp rax, rdx\njnz short loc_121E\nloc_122D:\nmov eax, [rbp+var_44]\ntest eax, eax\njle short loc_12A4\nmov r12, r13\nshr r12, 2\nlea r9, [rbx+r13]\nlea r15d, [rax+1]\nmov r11, r9\nmov esi, 1\nmov r8d, 0\njmp short loc_1298\nloc_1253:\nmov ecx, r8d\ntest eax, eax\njle short loc_125F\nmov ecx, [r11+rax*4-4]\nloc_125F:\nadd edx, ecx\nmov [r9+rax*4], edx\nadd rax, 1\ncmp r10, rax\njz short loc_128A\nloc_126E:\nmov edx, r8d\nmov ecx, esi\nsub ecx, [rdi+rax*4]\njs short loc_1253\nmovsxd rdx, eax\nmovsxd rcx, ecx\nimul rcx, r12\nadd rdx, rcx\nmov edx, [rbx+rdx*4]\njmp short loc_1253\nloc_128A:\nadd esi, 1\nadd r9, r13\nadd r11, r13\ncmp esi, r15d\njz short loc_12A4\nloc_1298:\nmov eax, 0\ntest r14d, r14d\njg short loc_126E\njmp short loc_128A\nloc_12A4:\nlea eax, [r14-1]\ncdqe\nmovsxd rdx, [rbp+var_44]\nshr r13, 2\nimul rdx, r13\nadd rax, rdx\nmov eax, [rbx+rax*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_12DA\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_12DA:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n __int64 v4; // r10\n unsigned __int64 v5; // r13\n __int16 v6; // cx\n _BYTE *v7; // rdx\n signed __int64 v8; // rax\n void *v9; // rsp\n _BYTE *v10; // rax\n _BYTE *v11; // r9\n int v12; // r15d\n _BYTE *v13; // r11\n int v14; // esi\n int v15; // ecx\n __int64 v16; // rax\n int v17; // edx\n _BYTE v20[12]; // [rsp+8h] [rbp-50h] BYREF\n int v21; // [rsp+14h] [rbp-44h]\n unsigned __int64 v22; // [rsp+20h] [rbp-38h]\n\n v21 = a3;\n v22 = __readfsqword(0x28u);\n v4 = a2;\n v5 = 4LL * a2;\n v6 = (4 * a2 * (a3 + 1) + 15) & 0xFFF0;\n v7 = &v20[-((4 * a2 * (__int64)(a3 + 1) + 15) & 0xFFFFFFFFFFFFF000LL)];\n while ( v20 != v7 )\n ;\n v8 = v6 & 0xFFF;\n v9 = alloca(v8);\n if ( (v6 & 0xFFF) != 0 )\n *(_QWORD *)&v20[v8 - 8] = *(_QWORD *)&v20[v8 - 8];\n if ( a2 > 0 )\n {\n v10 = v20;\n do\n {\n *(_DWORD *)v10 = 1;\n v10 += 4;\n }\n while ( v10 != &v20[v5] );\n }\n if ( v21 > 0 )\n {\n v11 = &v20[v5];\n v12 = v21 + 1;\n v13 = &v20[v5];\n v14 = 1;\n do\n {\n v16 = 0LL;\n if ( a2 > 0 )\n {\n do\n {\n v17 = 0;\n if ( v14 - *(_DWORD *)(a1 + 4 * v16) >= 0 )\n v17 = *(_DWORD *)&v20[4 * (v5 >> 2) * (v14 - *(_DWORD *)(a1 + 4 * v16)) + 4 * (int)v16];\n v15 = 0;\n if ( (int)v16 > 0 )\n v15 = *(_DWORD *)&v13[4 * v16 - 4];\n *(_DWORD *)&v11[4 * v16++] = v15 + v17;\n }\n while ( v4 != v16 );\n }\n ++v14;\n v11 += v5;\n v13 += v5;\n }\n while ( v14 != v12 );\n }\n return *(unsigned int *)&v20[4 * (v5 >> 2) * v21 - 4 + 4 * a2];\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\npush r13\npush r12\npush rbx\nsub rsp, 28h\nmov r14d, esi\nmov [rbp+var_44], edx\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nmovsxd r10, esi\nlea r13, ds:0[r10*4]\nlea eax, [rdx+1]\ncdqe\nimul rax, r10\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11E2:\ncmp rsp, rdx\njz short loc_11F9\nsub rsp, 1000h\nor [rsp+1050h+var_58], 0\njmp short loc_11E2\nloc_11F9:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_120F\nor [rsp+rax+50h+var_58], 0\nloc_120F:\nmov rbx, rsp\ntest r14d, r14d\njle short loc_122D\nmov rax, rbx\nlea rdx, [rbx+r13]\nloc_121E:\nmov dword ptr [rax], 1\nadd rax, 4\ncmp rax, rdx\njnz short loc_121E\nloc_122D:\nmov eax, [rbp+var_44]\ntest eax, eax\njle short loc_12A4\nmov r12, r13\nshr r12, 2\nlea r9, [rbx+r13]\nlea r15d, [rax+1]\nmov r11, r9\nmov esi, 1\nmov r8d, 0\njmp short loc_1298\nloc_1253:\nmov ecx, r8d\ntest eax, eax\njle short loc_125F\nmov ecx, [r11+rax*4-4]\nloc_125F:\nadd edx, ecx\nmov [r9+rax*4], edx\nadd rax, 1\ncmp r10, rax\njz short loc_128A\nloc_126E:\nmov edx, r8d\nmov ecx, esi\nsub ecx, [rdi+rax*4]\njs short loc_1253\nmovsxd rdx, eax\nmovsxd rcx, ecx\nimul rcx, r12\nadd rdx, rcx\nmov edx, [rbx+rdx*4]\njmp short loc_1253\nloc_128A:\nadd esi, 1\nadd r9, r13\nadd r11, r13\ncmp esi, r15d\njz short loc_12A4\nloc_1298:\nmov eax, 0\ntest r14d, r14d\njg short loc_126E\njmp short loc_128A\nloc_12A4:\nlea eax, [r14-1]\ncdqe\nmovsxd rdx, [rbp+var_44]\nshr r13, 2\nimul rdx, r13\nadd rax, rdx\nmov eax, [rbx+rax*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_12DA\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_12DA:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2, int a3)\n{\n __int64 v4; // r10\n unsigned __int64 v5; // r13\n __int16 v6; // cx\n _BYTE *v7; // rdx\n signed __int64 v8; // rax\n void *v9; // rsp\n _BYTE *v10; // rax\n _BYTE *v11; // r9\n int v12; // r15d\n _BYTE *v13; // r11\n int v14; // esi\n int v15; // ecx\n __int64 v16; // rax\n int v17; // edx\n _BYTE v20[12]; // [rsp+8h] [rbp-50h] BYREF\n int v21; // [rsp+14h] [rbp-44h]\n unsigned __int64 v22; // [rsp+20h] [rbp-38h]\n\n v21 = a3;\n v22 = __readfsqword(0x28u);\n v4 = a2;\n v5 = 4LL * a2;\n v6 = (4 * a2 * (a3 + 1) + 15) & 0xFFF0;\n v7 = &v20[-((4 * a2 * (__int64)(a3 + 1) + 15) & 0xFFFFFFFFFFFFF000LL)];\n while ( v20 != v7 )\n ;\n v8 = v6 & 0xFFF;\n v9 = alloca(v8);\n if ( (v6 & 0xFFF) != 0 )\n *(_QWORD *)&v20[v8 - 8] = *(_QWORD *)&v20[v8 - 8];\n if ( a2 > 0 )\n {\n v10 = v20;\n do\n {\n *(_DWORD *)v10 = 1;\n v10 += 4;\n }\n while ( v10 != &v20[v5] );\n }\n if ( v21 > 0 )\n {\n v11 = &v20[v5];\n v12 = v21 + 1;\n v13 = &v20[v5];\n v14 = 1;\n do\n {\n v16 = 0LL;\n if ( a2 > 0 )\n {\n do\n {\n v17 = 0;\n if ( v14 - *(_DWORD *)(a1 + 4 * v16) >= 0 )\n v17 = *(_DWORD *)&v20[4 * (v5 >> 2) * (v14 - *(_DWORD *)(a1 + 4 * v16)) + 4 * (int)v16];\n v15 = 0;\n if ( (int)v16 > 0 )\n v15 = *(_DWORD *)&v13[4 * v16 - 4];\n *(_DWORD *)&v11[4 * v16++] = v15 + v17;\n }\n while ( v4 != v16 );\n }\n ++v14;\n v11 += v5;\n v13 += v5;\n }\n while ( v14 != v12 );\n }\n return *(unsigned int *)&v20[4 * (v5 >> 2) * v21 - 4 + 4 * a2];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2, int a3) {\n long long v4;\n unsigned long long v5;\n short v6;\n uint8_t *v7;\n signed long long v8;\n void *v9;\n uint8_t *v10;\n uint8_t *v11;\n int v12;\n uint8_t *v13;\n int v14;\n int v15;\n long long v16;\n int v17;\n uint8_t v20[12];\n int v21;\n unsigned long long v22;\n v21 = a3;\n v22 = __readfsqword(40u);\n v4 = a2;\n v5 = 4LL * a2;\n v6 = (4 * a2 * (a3 + 1) + 15) & 65520;\n v7 = &v20[-((4 * a2 * (long long)(a3 + 1) + 15) & 18446744073709547520LL)];\n while (v20 != v7)\n ;\n v8 = v6 & 4095;\n v9 = alloca(v8);\n if ((v6 & 4095) != 0) *(uint64_t *)&v20[v8 - 8] = *(uint64_t *)&v20[v8 - 8];\n if (a2 > 0) {\n v10 = v20;\n do {\n *(uint32_t *)v10 = 1;\n v10 += 4;\n } while (v10 != &v20[v5]);\n }\n if (v21 > 0) {\n v11 = &v20[v5];\n v12 = v21 + 1;\n v13 = &v20[v5];\n v14 = 1;\n do {\n v16 = 0LL;\n if (a2 > 0) {\n do {\n v17 = 0;\n if (v14 - *(uint32_t *)(a1 + 4 * v16) >= 0)\n v17 = *(uint32_t *)&v20[4 * (v5 >> 2) *\n (v14 - *(uint32_t *)(a1 + 4 * v16)) +\n 4 * (int)v16];\n v15 = 0;\n if ((int)v16 > 0) v15 = *(uint32_t *)&v13[4 * v16 - 4];\n *(uint32_t *)&v11[4 * v16++] = v15 + v17;\n } while (v4 != v16);\n }\n ++v14;\n v11 += v5;\n v13 += v5;\n } while (v14 != v12);\n }\n return *(unsigned int *)&v20[4 * (v5 >> 2) * v21 - 4 + 4 * a2];\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n long long v4;\n unsigned long long v5;\n short v6;\n uint8_t *v7;\n signed long long v8;\n void *v9;\n uint8_t *v10;\n uint8_t *v11;\n int v12;\n uint8_t *v13;\n int v14;\n int v15;\n long long v16;\n int v17;\n uint8_t v20[12];\n int v21;\n unsigned long long v22;\n v21 = a3;\n v22 = __readfsqword(40u);\n v4 = a2;\n v5 = 4LL * a2;\n v6 = (4 * a2 * (a3 + 1) + 15) & 65520;\n v7 = &v20[-((4 * a2 * (long long)(a3 + 1) + 15) & 18446744073709547520LL)];\n while (v20 != v7)\n ;\n v8 = v6 & 4095;\n v9 = alloca(v8);\n if ((v6 & 4095) != 0) *(uint64_t *)&v20[v8 - 8] = *(uint64_t *)&v20[v8 - 8];\n if (a2 > 0) {\n v10 = v20;\n do {\n *(uint32_t *)v10 = 1;\n v10 += 4;\n } while (v10 != &v20[v5]);\n }\n if (v21 > 0) {\n v11 = &v20[v5];\n v12 = v21 + 1;\n v13 = &v20[v5];\n v14 = 1;\n do {\n v16 = 0LL;\n if (a2 > 0) {\n do {\n v17 = 0;\n if (v14 - *(uint32_t *)(a1 + 4 * v16) >= 0)\n v17 = *(uint32_t *)&v20[4 * (v5 >> 2) *\n (v14 - *(uint32_t *)(a1 + 4 * v16)) +\n 4 * (int)v16];\n v15 = 0;\n if ((int)v16 > 0) v15 = *(uint32_t *)&v13[4 * v16 - 4];\n *(uint32_t *)&v11[4 * v16++] = v15 + v17;\n } while (v4 != v16);\n }\n ++v14;\n v11 += v5;\n v13 += v5;\n } while (v14 != v12);\n }\n return *(unsigned int *)&v20[4 * (v5 >> 2) * v21 - 4 + 4 * a2];\n}" + }, + { + "index": 918, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int S[], int m, int n) {\n int table[n + 1][m];\n for (int i = 0; i < m; i++) {\n table[0][i] = 1;\n }\n for (int i = 1; i <= n; i++) {\n for (int j = 0; j < m; j++) {\n int x = (i - S[j] >= 0) ? table[i - S[j]][j] : 0;\n int y = (j >= 1) ? table[i][j - 1] : 0;\n table[i][j] = x + y;\n }\n }\n return table[n][m - 1];\n}", + "test": "int main() {\n\n int S1[] = {1, 2, 3};\n\n int m1 = 3;\n\n int n1 = 4;\n\n assert(func0(S1, m1, n1) == 4);\n\n\n\n int S2[] = {4, 5, 6, 7, 8, 9};\n\n int m2 = 6;\n\n int n2 = 9;\n\n assert(func0(S2, m2, n2) == 2);\n\n\n\n int S3[] = {4, 5, 6, 7, 8, 9};\n\n int m3 = 6;\n\n int n3 = 4;\n\n assert(func0(S3, m3, n3) == 1);\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\npush %r14\nmovslq %edx,%r14\nmovslq %esi,%rdx\npush %r13\nlea 0x1(%r14),%r13d\npush %r12\nlea 0x0(,%rdx,4),%r12\npush %rbx\nmov %esi,%ebx\nsub $0x18,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nmovslq %r13d,%rax\nmov %rsp,%rsi\nimul %rdx,%rax\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rsi\nand $0xfffffffffffffff0,%rdx\nmov %rsi,%rax\ncmp %rax,%rsp\nje 1357 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 1342 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 142d \nmov %r12,%rsi\nmov %rsp,%rdx\nshr $0x2,%rsi\ntest %ebx,%ebx\njle 1438 \nlea -0x1(%rbx),%ecx\nmov %rdx,%rax\nmov %rcx,%r15\nlea 0x4(%rdx,%rcx,4),%rcx\nnopl 0x0(%rax)\nmovl $0x1,(%rax)\nadd $0x4,%rax\ncmp %rcx,%rax\njne 1390 \ntest %r14d,%r14d\njle 1402 \nlea (%rdx,%r12,1),%r10\nmov $0x1,%r9d\nmov %r15d,%r11d\nnopl 0x0(%rax)\nxor %eax,%eax\ntest %ebx,%ebx\njg 13c3 \njmp 13f6 \nmov %rcx,%rax\nxor %r8d,%r8d\nmov %r9d,%ecx\nsub (%rdi,%rax,4),%ecx\njs 13df \nmovslq %ecx,%rcx\nmovslq %eax,%r8\nimul %rsi,%rcx\nadd %r8,%rcx\nmov (%rdx,%rcx,4),%r8d\ntest %rax,%rax\nje 13e9 \nadd -0x4(%r10,%rax,4),%r8d\nmov %r8d,(%r10,%rax,4)\nlea 0x1(%rax),%rcx\ncmp %rax,%r11\njne 13c0 \nadd $0x1,%r9d\nadd %r12,%r10\ncmp %r13d,%r9d\njne 13b8 \nimul %r14,%rsi\nmovslq %r15d,%r15\nadd %r15,%rsi\nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\nmov (%rdx,%rsi,4),%eax\njne 1441 \nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 1369 \nlea -0x1(%rbx),%r15d\njmpq 139f \ncallq 1080 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmovsxd r9, esi\nmov rbp, rsp\npush r13\nlea r13, ds:0[r9*4]\npush r12\nmov r12, r9\npush rbx\nmovsxd rbx, edx\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nlea eax, [rbx+1]\nmov rcx, rsp\ncdqe\nimul rax, r9\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_132F\nloc_131A:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rcx\njnz short loc_131A\nloc_132F:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1424\nloc_1341:\nmov r10, rsp\nmov r11, r13\nshr r11, 2\nmov rax, r10\nlea rdx, [r10+r13]\ntest r12d, r12d\njle short loc_138E\nmov rcx, rdx\nsub rcx, r10\nand ecx, 4\njz short loc_1378\nlea rax, [r10+4]\nmov dword ptr [r10], 1\ncmp rax, rdx\njz short loc_138E\nnop word ptr [rax+rax+00h]\nloc_1378:\nmov dword ptr [rax], 1\nadd rax, 8\nmov dword ptr [rax-4], 1\ncmp rax, rdx\njnz short loc_1378\nloc_138E:\ntest ebx, ebx\njle short loc_13F8\nlea r8, [r10+r13]\nmov esi, 1\nloc_139B:\ntest r12d, r12d\njle short loc_13E7\nloc_13A0:\nxor eax, eax\nnop word ptr [rax+rax+00h]\nloc_13A8:\nxor ecx, ecx\nmov edx, esi\nsub edx, [rdi+rax*4]\njs short loc_13C2\nmovsxd rdx, edx\nmovsxd rcx, eax\nimul rdx, r11\nadd rdx, rcx\nmov ecx, [r10+rdx*4]\nloc_13C2:\ntest rax, rax\njz short loc_13CC\nadd ecx, [r8+rax*4-4]\nloc_13CC:\nmov [r8+rax*4], ecx\nadd rax, 1\ncmp r9, rax\njnz short loc_13A8\nlea eax, [rsi+1]\nadd r8, r13\ncmp esi, ebx\njz short loc_13F8\nmov esi, eax\njmp short loc_13A0\nloc_13E7:\nlea eax, [rsi+1]\nadd r8, r13\ncmp ebx, esi\njz short loc_13F8\nmov esi, eax\njmp short loc_139B\nloc_13F8:\nimul rbx, r11\nlea eax, [r12-1]\ncdqe\nadd rax, rbx\nmov eax, [r10+rax*4]\nmov rdx, [rbp+var_28]\nsub rdx, fs:28h\njnz short loc_142F\nlea rsp, [rbp-18h]\npop rbx\npop r12\npop r13\npop rbp\nretn\nloc_1424:\nor [rsp+rdx+1030h+var_1038], 0\njmp loc_1341\nloc_142F:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n __int64 v3; // r9\n unsigned __int64 v4; // r13\n __int64 v6; // rbx\n __int64 v7; // rdx\n int *v8; // rcx\n __int16 v9; // dx\n signed __int64 v10; // rdx\n void *v11; // rsp\n unsigned __int64 v12; // r11\n int *v13; // rax\n int *v14; // rdx\n _BYTE *v15; // r8\n int v16; // esi\n __int64 v17; // rax\n int v18; // ecx\n __int64 v20; // [rsp+0h] [rbp-1038h]\n int v21; // [rsp+8h] [rbp-1030h] BYREF\n _BYTE v22[4084]; // [rsp+Ch] [rbp-102Ch] BYREF\n _QWORD v23[6]; // [rsp+1008h] [rbp-30h] BYREF\n\n v3 = a2;\n v4 = 4LL * a2;\n v6 = a3;\n v23[1] = __readfsqword(0x28u);\n v7 = 4 * a2 * (__int64)(a3 + 1) + 15;\n v8 = (int *)((char *)v23 - (v7 & 0xFFFFFFFFFFFFF000LL));\n v9 = v7 & 0xFFF0;\n if ( v23 != (_QWORD *)v8 )\n {\n while ( &v21 != v8 )\n ;\n }\n v10 = v9 & 0xFFF;\n v11 = alloca(v10);\n if ( v10 )\n *(__int64 *)((char *)&v20 + v10) = *(__int64 *)((char *)&v20 + v10);\n v12 = v4 >> 2;\n v13 = &v21;\n v14 = (int *)&v22[v4 - 4];\n if ( a2 > 0 )\n {\n if ( (((_BYTE)v14 - (unsigned __int8)&v21) & 4) == 0 || (v13 = (int *)v22, v21 = 1, v22 != (_BYTE *)v14) )\n {\n do\n {\n *v13 = 1;\n v13 += 2;\n *(v13 - 1) = 1;\n }\n while ( v13 != v14 );\n }\n }\n if ( (int)v6 > 0 )\n {\n v15 = &v22[v4 - 4];\n v16 = 1;\n while ( a2 <= 0 )\n {\n v15 += v4;\n if ( (_DWORD)v6 == v16 )\n return (unsigned int)*(&v21 + v12 * v6 + a2 - 1);\n ++v16;\n }\n while ( 1 )\n {\n v17 = 0LL;\n do\n {\n v18 = 0;\n if ( v16 - *(_DWORD *)(a1 + 4 * v17) >= 0 )\n v18 = *(_DWORD *)&v22[4 * (int)v17 - 4 + 4 * v12 * (v16 - *(_DWORD *)(a1 + 4 * v17))];\n if ( v17 )\n v18 += *(_DWORD *)&v15[4 * v17 - 4];\n *(_DWORD *)&v15[4 * v17++] = v18;\n }\n while ( v3 != v17 );\n v15 += v4;\n if ( v16 == (_DWORD)v6 )\n break;\n ++v16;\n }\n }\n return (unsigned int)*(&v21 + v12 * v6 + a2 - 1);\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\npush rbp\nmovsxd r9, esi\nmov rbp, rsp\npush r13\nlea r13, ds:0[r9*4]\npush r12\nmov r12, r9\npush rbx\nmovsxd rbx, edx\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nlea eax, [rbx+1]\nmov rcx, rsp\ncdqe\nimul rax, r9\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_132F\nloc_131A:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rcx\njnz short loc_131A\nloc_132F:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1424\nloc_1341:\nmov r10, rsp\nmov r11, r13\nshr r11, 2\nmov rax, r10\nlea rdx, [r10+r13]\ntest r12d, r12d\njle short loc_138E\nmov rcx, rdx\nsub rcx, r10\nand ecx, 4\njz short loc_1378\nlea rax, [r10+4]\nmov dword ptr [r10], 1\ncmp rax, rdx\njz short loc_138E\nnop word ptr [rax+rax+00h]\nloc_1378:\nmov dword ptr [rax], 1\nadd rax, 8\nmov dword ptr [rax-4], 1\ncmp rax, rdx\njnz short loc_1378\nloc_138E:\ntest ebx, ebx\njle short loc_13F8\nlea r8, [r10+r13]\nmov esi, 1\nloc_139B:\ntest r12d, r12d\njle short loc_13E7\nloc_13A0:\nxor eax, eax\nnop word ptr [rax+rax+00h]\nloc_13A8:\nxor ecx, ecx\nmov edx, esi\nsub edx, [rdi+rax*4]\njs short loc_13C2\nmovsxd rdx, edx\nmovsxd rcx, eax\nimul rdx, r11\nadd rdx, rcx\nmov ecx, [r10+rdx*4]\nloc_13C2:\ntest rax, rax\njz short loc_13CC\nadd ecx, [r8+rax*4-4]\nloc_13CC:\nmov [r8+rax*4], ecx\nadd rax, 1\ncmp r9, rax\njnz short loc_13A8\nlea eax, [rsi+1]\nadd r8, r13\ncmp esi, ebx\njz short loc_13F8\nmov esi, eax\njmp short loc_13A0\nloc_13E7:\nlea eax, [rsi+1]\nadd r8, r13\ncmp ebx, esi\njz short loc_13F8\nmov esi, eax\njmp short loc_139B\nloc_13F8:\nimul rbx, r11\nlea eax, [r12-1]\ncdqe\nadd rax, rbx\nmov eax, [r10+rax*4]\nmov rdx, [rbp+var_28]\nsub rdx, fs:28h\njnz short loc_142F\nlea rsp, [rbp-18h]\npop rbx\npop r12\npop r13\npop rbp\nretn\nloc_1424:\nor [rsp+rdx+1030h+var_1038], 0\njmp loc_1341\nloc_142F:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12C0(__int64 a1, int a2, int a3)\n{\n __int64 v3; // r9\n unsigned __int64 v4; // r13\n __int64 v6; // rbx\n __int64 v7; // rdx\n int *v8; // rcx\n __int16 v9; // dx\n signed __int64 v10; // rdx\n void *v11; // rsp\n unsigned __int64 v12; // r11\n int *v13; // rax\n int *v14; // rdx\n _BYTE *v15; // r8\n int v16; // esi\n __int64 v17; // rax\n int v18; // ecx\n __int64 v20; // [rsp+0h] [rbp-1038h]\n int v21; // [rsp+8h] [rbp-1030h] BYREF\n _BYTE v22[4084]; // [rsp+Ch] [rbp-102Ch] BYREF\n _QWORD v23[6]; // [rsp+1008h] [rbp-30h] BYREF\n\n v3 = a2;\n v4 = 4LL * a2;\n v6 = a3;\n v23[1] = __readfsqword(0x28u);\n v7 = 4 * a2 * (__int64)(a3 + 1) + 15;\n v8 = (int *)((char *)v23 - (v7 & 0xFFFFFFFFFFFFF000LL));\n v9 = v7 & 0xFFF0;\n if ( v23 != (_QWORD *)v8 )\n {\n while ( &v21 != v8 )\n ;\n }\n v10 = v9 & 0xFFF;\n v11 = alloca(v10);\n if ( v10 )\n *(__int64 *)((char *)&v20 + v10) = *(__int64 *)((char *)&v20 + v10);\n v12 = v4 >> 2;\n v13 = &v21;\n v14 = (int *)&v22[v4 - 4];\n if ( a2 > 0 )\n {\n if ( (((_BYTE)v14 - (unsigned __int8)&v21) & 4) == 0 || (v13 = (int *)v22, v21 = 1, v22 != (_BYTE *)v14) )\n {\n do\n {\n *v13 = 1;\n v13 += 2;\n *(v13 - 1) = 1;\n }\n while ( v13 != v14 );\n }\n }\n if ( (int)v6 > 0 )\n {\n v15 = &v22[v4 - 4];\n v16 = 1;\n while ( a2 <= 0 )\n {\n v15 += v4;\n if ( (_DWORD)v6 == v16 )\n return (unsigned int)*(&v21 + v12 * v6 + a2 - 1);\n ++v16;\n }\n while ( 1 )\n {\n v17 = 0LL;\n do\n {\n v18 = 0;\n if ( v16 - *(_DWORD *)(a1 + 4 * v17) >= 0 )\n v18 = *(_DWORD *)&v22[4 * (int)v17 - 4 + 4 * v12 * (v16 - *(_DWORD *)(a1 + 4 * v17))];\n if ( v17 )\n v18 += *(_DWORD *)&v15[4 * v17 - 4];\n *(_DWORD *)&v15[4 * v17++] = v18;\n }\n while ( v3 != v17 );\n v15 += v4;\n if ( v16 == (_DWORD)v6 )\n break;\n ++v16;\n }\n }\n return (unsigned int)*(&v21 + v12 * v6 + a2 - 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12C0(long long a1, int a2, int a3) {\n long long v3;\n unsigned long long v4;\n long long v6;\n long long v7;\n int *v8;\n short v9;\n signed long long v10;\n void *v11;\n unsigned long long v12;\n int *v13;\n int *v14;\n uint8_t *v15;\n int v16;\n long long v17;\n int v18;\n long long v20;\n int v21;\n uint8_t v22[4084];\n uint64_t v23[6];\n v3 = a2;\n v4 = 4LL * a2;\n v6 = a3;\n v23[1] = __readfsqword(40u);\n v7 = 4 * a2 * (long long)(a3 + 1) + 15;\n v8 = (int *)((char *)v23 - (v7 & 18446744073709547520LL));\n v9 = v7 & 65520;\n if (v23 != (uint64_t *)v8) {\n while (&v21 != v8)\n ;\n }\n v10 = v9 & 4095;\n v11 = alloca(v10);\n if (v10)\n *(long long *)((char *)&v20 + v10) = *(long long *)((char *)&v20 + v10);\n v12 = v4 >> 2;\n v13 = &v21;\n v14 = (int *)&v22[v4 - 4];\n if (a2 > 0) {\n if ((((uint8_t)v14 - (unsigned char)&v21) & 4) == 0 ||\n (v13 = (int *)v22, v21 = 1, v22 != (uint8_t *)v14)) {\n do {\n *v13 = 1;\n v13 += 2;\n *(v13 - 1) = 1;\n } while (v13 != v14);\n }\n }\n if ((int)v6 > 0) {\n v15 = &v22[v4 - 4];\n v16 = 1;\n while (a2 <= 0) {\n v15 += v4;\n if ((uint32_t)v6 == v16) return (unsigned int)*(&v21 + v12 * v6 + a2 - 1);\n ++v16;\n }\n while (1) {\n v17 = 0LL;\n do {\n v18 = 0;\n if (v16 - *(uint32_t *)(a1 + 4 * v17) >= 0)\n v18 =\n *(uint32_t *)&v22[4 * (int)v17 - 4 +\n 4 * v12 * (v16 - *(uint32_t *)(a1 + 4 * v17))];\n if (v17) v18 += *(uint32_t *)&v15[4 * v17 - 4];\n *(uint32_t *)&v15[4 * v17++] = v18;\n } while (v3 != v17);\n v15 += v4;\n if (v16 == (uint32_t)v6) break;\n ++v16;\n }\n }\n return (unsigned int)*(&v21 + v12 * v6 + a2 - 1);\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n long long v3;\n unsigned long long v4;\n long long v6;\n long long v7;\n int *v8;\n short v9;\n signed long long v10;\n void *v11;\n unsigned long long v12;\n int *v13;\n int *v14;\n uint8_t *v15;\n int v16;\n long long v17;\n int v18;\n long long v20;\n int v21;\n uint8_t v22[4084];\n uint64_t v23[6];\n v3 = a2;\n v4 = 4LL * a2;\n v6 = a3;\n v23[1] = __readfsqword(40u);\n v7 = 4 * a2 * (long long)(a3 + 1) + 15;\n v8 = (int *)((char *)v23 - (v7 & 18446744073709547520LL));\n v9 = v7 & 65520;\n if (v23 != (uint64_t *)v8) {\n while (&v21 != v8)\n ;\n }\n v10 = v9 & 4095;\n v11 = alloca(v10);\n if (v10)\n *(long long *)((char *)&v20 + v10) = *(long long *)((char *)&v20 + v10);\n v12 = v4 >> 2;\n v13 = &v21;\n v14 = (int *)&v22[v4 - 4];\n if (a2 > 0) {\n if ((((uint8_t)v14 - (unsigned char)&v21) & 4) == 0 ||\n (v13 = (int *)v22, v21 = 1, v22 != (uint8_t *)v14)) {\n do {\n *v13 = 1;\n v13 += 2;\n *(v13 - 1) = 1;\n } while (v13 != v14);\n }\n }\n if ((int)v6 > 0) {\n v15 = &v22[v4 - 4];\n v16 = 1;\n while (a2 <= 0) {\n v15 += v4;\n if ((uint32_t)v6 == v16) return (unsigned int)*(&v21 + v12 * v6 + a2 - 1);\n ++v16;\n }\n while (1) {\n v17 = 0LL;\n do {\n v18 = 0;\n if (v16 - *(uint32_t *)(a1 + 4 * v17) >= 0)\n v18 =\n *(uint32_t *)&v22[4 * (int)v17 - 4 +\n 4 * v12 * (v16 - *(uint32_t *)(a1 + 4 * v17))];\n if (v17) v18 += *(uint32_t *)&v15[4 * v17 - 4];\n *(uint32_t *)&v15[4 * v17++] = v18;\n } while (v3 != v17);\n v15 += v4;\n if (v16 == (uint32_t)v6) break;\n ++v16;\n }\n }\n return (unsigned int)*(&v21 + v12 * v6 + a2 - 1);\n}" + }, + { + "index": 918, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int S[], int m, int n) {\n int table[n + 1][m];\n for (int i = 0; i < m; i++) {\n table[0][i] = 1;\n }\n for (int i = 1; i <= n; i++) {\n for (int j = 0; j < m; j++) {\n int x = (i - S[j] >= 0) ? table[i - S[j]][j] : 0;\n int y = (j >= 1) ? table[i][j - 1] : 0;\n table[i][j] = x + y;\n }\n }\n return table[n][m - 1];\n}", + "test": "int main() {\n\n int S1[] = {1, 2, 3};\n\n int m1 = 3;\n\n int n1 = 4;\n\n assert(func0(S1, m1, n1) == 4);\n\n\n\n int S2[] = {4, 5, 6, 7, 8, 9};\n\n int m2 = 6;\n\n int n2 = 9;\n\n assert(func0(S2, m2, n2) == 2);\n\n\n\n int S3[] = {4, 5, 6, 7, 8, 9};\n\n int m3 = 6;\n\n int n3 = 4;\n\n assert(func0(S3, m3, n3) == 1);\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r14\npush %r13\npush %r12\npush %rbx\nmovslq %edx,%rbx\nmovslq %esi,%rdx\nlea 0x1(%rbx),%r13d\nlea 0x0(,%rdx,4),%r12\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x28(%rbp)\nxor %eax,%eax\nmovslq %r13d,%rax\nmov %rsp,%rcx\nimul %rdx,%rax\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rcx\nand $0xfffffffffffffff0,%rdx\nmov %rcx,%rax\ncmp %rax,%rsp\nje 1343 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 132e \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 1470 \nmov %r12,%rdx\nmov %rsp,%r11\nlea -0x1(%rsi),%r14d\nshr $0x2,%rdx\ntest %esi,%esi\njle 1446 \ncmp $0x2,%r14d\njbe 147b \nmov %esi,%ecx\nmovdqa 0xd31(%rip),%xmm0\nmov %r11,%rax\nshr $0x2,%ecx\nshl $0x4,%rcx\nadd %r11,%rcx\nnopl 0x0(%rax)\nmovups %xmm0,(%rax)\nadd $0x10,%rax\ncmp %rcx,%rax\njne 1390 \nmov %esi,%eax\nand $0xfffffffc,%eax\ntest $0x3,%sil\nje 13d5 \nmovslq %eax,%rcx\nmovl $0x1,(%r11,%rcx,4)\nlea 0x1(%rax),%ecx\ncmp %ecx,%esi\njle 13d5 \nmovslq %ecx,%rcx\nadd $0x2,%eax\nmovl $0x1,(%r11,%rcx,4)\ncmp %eax,%esi\njle 13d5 \ncltq\nmovl $0x1,(%r11,%rax,4)\nlea (%r11,%r12,1),%r9\nmov $0x1,%r8d\nmov %r14d,%r10d\ntest %ebx,%ebx\njle 1446 \nnopw %cs:0x0(%rax,%rax,1)\nxor %eax,%eax\njmp 140d \nnopl 0x0(%rax)\nadd -0x4(%r9,%rax,4),%esi\nlea 0x1(%rax),%rcx\nmov %esi,(%r9,%rax,4)\ncmp %r10,%rax\nje 143a \nmov %rcx,%rax\nxor %esi,%esi\nmov %r8d,%ecx\nsub (%rdi,%rax,4),%ecx\njs 1428 \nmovslq %ecx,%rcx\nmovslq %eax,%rsi\nimul %rdx,%rcx\nadd %rsi,%rcx\nmov (%r11,%rcx,4),%esi\ntest %rax,%rax\njne 13f8 \nmov %esi,(%r9)\nmov $0x1,%ecx\ncmp %r10,%rax\njne 140a \nadd $0x1,%r8d\nadd %r12,%r9\ncmp %r13d,%r8d\njne 13f0 \nimul %rbx,%rdx\nmovslq %r14d,%r14\nadd %r14,%rdx\nmov -0x28(%rbp),%rbx\nxor %fs:0x28,%rbx\nmov (%r11,%rdx,4),%eax\njne 1482 \nlea -0x20(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %rbp\nretq\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 1355 \nxor %eax,%eax\njmpq 13a7 \ncallq 1080 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmovsxd r9, esi\nmov rcx, r9\nmov rbp, rsp\npush r13\npush r12\nlea r12, ds:0[r9*4]\npush rbx\nmovsxd rbx, edx\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nlea eax, [rbx+1]\nmov rsi, rsp\ncdqe\nimul rax, r9\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rsi, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rsi\njz short loc_132F\nloc_131A:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rsi\njnz short loc_131A\nloc_132F:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1473\nloc_1341:\nmov r11, r12\nmov r10, rsp\nlea r13d, [rcx-1]\nshr r11, 2\ntest ecx, ecx\njle loc_1430\ncmp r13d, 2\njbe loc_147E\nmov edx, ecx\nmovdqa xmm0, cs:xmmword_2090\nmov rax, r10\nshr edx, 2\nshl rdx, 4\nlea rsi, [r10+rdx]\nand edx, 10h\njz short loc_1390\nlea rax, [r10+10h]\nmovups xmmword ptr [r10], xmm0\ncmp rax, rsi\njz short loc_13A0\nnop dword ptr [rax+rax+00h]\nloc_1390:\nmovups xmmword ptr [rax], xmm0\nadd rax, 20h ; ' '\nmovups xmmword ptr [rax-10h], xmm0\ncmp rax, rsi\njnz short loc_1390\nloc_13A0:\ntest cl, 3\njz short loc_13D3\nmov eax, ecx\nand eax, 0FFFFFFFCh\nloc_13AA:\nmovsxd rdx, eax\nlea esi, [rax+1]\nlea rdx, [r10+rdx*4]\nmov dword ptr [rdx], 1\ncmp esi, ecx\njge short loc_13D3\nadd eax, 2\nmov dword ptr [rdx+4], 1\ncmp eax, ecx\njge short loc_13D3\nmov dword ptr [rdx+8], 1\nloc_13D3:\nlea r8, [r10+r12]\nmov esi, 1\ntest ebx, ebx\njle short loc_1430\nloc_13E0:\nxor eax, eax\nnop word ptr [rax+rax+00h]\nloc_13E8:\nxor ecx, ecx\nmov edx, esi\nsub edx, [rdi+rax*4]\njs short loc_1402\nmovsxd rdx, edx\nmovsxd rcx, eax\nimul rdx, r11\nadd rdx, rcx\nmov ecx, [r10+rdx*4]\nloc_1402:\ntest rax, rax\njz short loc_1460\nadd ecx, [r8+rax*4-4]\nmov [r8+rax*4], ecx\nadd rax, 1\ncmp r9, rax\njnz short loc_13E8\nloc_1419:\nlea eax, [rsi+1]\nadd r8, r12\ncmp ebx, esi\njz short loc_1430\nmov esi, eax\njmp short loc_13E0\nloc_1430:\nimul rbx, r11\nmovsxd rax, r13d\nadd rax, rbx\nmov eax, [r10+rax*4]\nmov rdx, [rbp+var_28]\nsub rdx, fs:28h\njnz short loc_1485\nlea rsp, [rbp-18h]\npop rbx\npop r12\npop r13\npop rbp\nretn\nloc_1460:\nmov [r8], ecx\ncmp r9, 1\njz short loc_1419\nmov eax, 1\njmp loc_13E8\nloc_1473:\nor [rsp+rdx+1030h+var_1038], 0\njmp loc_1341\nloc_147E:\nxor eax, eax\njmp loc_13AA\nloc_1485:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n __int64 v3; // r9\n unsigned __int64 v5; // r12\n __int64 v6; // rbx\n __int64 v7; // rdx\n __m128i *v8; // rsi\n __int16 v9; // dx\n signed __int64 v10; // rdx\n void *v11; // rsp\n unsigned int v12; // r13d\n unsigned __int64 v13; // r11\n __m128i si128; // xmm0\n __m128i *v15; // rax\n __int64 v16; // rdx\n __m128i *v17; // rsi\n int v18; // eax\n __int32 *v19; // rdx\n __int32 *v20; // r8\n int v21; // esi\n __int64 i; // rax\n __int32 v23; // ecx\n __int64 v25; // [rsp+0h] [rbp-1038h]\n __m128i v26; // [rsp+8h] [rbp-1030h] BYREF\n _BYTE v27[4072]; // [rsp+18h] [rbp-1020h] BYREF\n _QWORD v28[6]; // [rsp+1008h] [rbp-30h] BYREF\n\n v3 = a2;\n v5 = 4LL * a2;\n v6 = a3;\n v28[1] = __readfsqword(0x28u);\n v7 = 4 * a2 * (__int64)(a3 + 1) + 15;\n v8 = (__m128i *)((char *)v28 - (v7 & 0xFFFFFFFFFFFFF000LL));\n v9 = v7 & 0xFFF0;\n if ( v28 != (_QWORD *)v8 )\n {\n while ( &v26 != v8 )\n ;\n }\n v10 = v9 & 0xFFF;\n v11 = alloca(v10);\n if ( v10 )\n *(__int64 *)((char *)&v25 + v10) = *(__int64 *)((char *)&v25 + v10);\n v12 = a2 - 1;\n v13 = v5 >> 2;\n if ( a2 <= 0 )\n return v26.m128i_u32[v13 * v6 + (int)v12];\n if ( v12 <= 2 )\n {\n v18 = 0;\n goto LABEL_12;\n }\n si128 = _mm_load_si128((const __m128i *)&xmmword_2090);\n v15 = &v26;\n v16 = 16LL * ((unsigned int)a2 >> 2);\n v17 = (__m128i *)((char *)&v26 + v16);\n if ( (v16 & 0x10) == 0 || (v15 = (__m128i *)v27, v26 = si128, v27 != (_BYTE *)v17) )\n {\n do\n {\n *v15 = si128;\n v15 += 2;\n v15[-1] = si128;\n }\n while ( v15 != v17 );\n }\n if ( (a2 & 3) != 0 )\n {\n v18 = a2 & 0x7FFFFFFC;\nLABEL_12:\n v19 = &v26.m128i_i32[v18];\n *v19 = 1;\n if ( v18 + 1 < a2 )\n {\n v19[1] = 1;\n if ( v18 + 2 < a2 )\n v19[2] = 1;\n }\n }\n v20 = &v26.m128i_i32[v5 / 4];\n v21 = 1;\n if ( (int)v6 > 0 )\n {\n while ( 1 )\n {\n for ( i = 0LL; ; i = 1LL )\n {\n while ( 1 )\n {\n v23 = 0;\n if ( v21 - *(_DWORD *)(a1 + 4 * i) >= 0 )\n v23 = v26.m128i_i32[(int)i + v13 * (v21 - *(_DWORD *)(a1 + 4 * i))];\n if ( !i )\n break;\n v20[i] = v20[i - 1] + v23;\n if ( v3 == ++i )\n goto LABEL_21;\n }\n *v20 = v23;\n if ( v3 == 1 )\n break;\n }\nLABEL_21:\n v20 = (__int32 *)((char *)v20 + v5);\n if ( (_DWORD)v6 == v21 )\n break;\n ++v21;\n }\n }\n return v26.m128i_u32[v13 * v6 + (int)v12];\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\npush rbp\nmovsxd r9, esi\nmov rcx, r9\nmov rbp, rsp\npush r13\npush r12\nlea r12, ds:0[r9*4]\npush rbx\nmovsxd rbx, edx\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nlea eax, [rbx+1]\nmov rsi, rsp\ncdqe\nimul rax, r9\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rsi, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rsi\njz short loc_132F\nloc_131A:\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\ncmp rsp, rsi\njnz short loc_131A\nloc_132F:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1473\nloc_1341:\nmov r11, r12\nmov r10, rsp\nlea r13d, [rcx-1]\nshr r11, 2\ntest ecx, ecx\njle loc_1430\ncmp r13d, 2\njbe loc_147E\nmov edx, ecx\nmovdqa xmm0, cs:xmmword_2090\nmov rax, r10\nshr edx, 2\nshl rdx, 4\nlea rsi, [r10+rdx]\nand edx, 10h\njz short loc_1390\nlea rax, [r10+10h]\nmovups xmmword ptr [r10], xmm0\ncmp rax, rsi\njz short loc_13A0\nnop dword ptr [rax+rax+00h]\nloc_1390:\nmovups xmmword ptr [rax], xmm0\nadd rax, 20h ; ' '\nmovups xmmword ptr [rax-10h], xmm0\ncmp rax, rsi\njnz short loc_1390\nloc_13A0:\ntest cl, 3\njz short loc_13D3\nmov eax, ecx\nand eax, 0FFFFFFFCh\nloc_13AA:\nmovsxd rdx, eax\nlea esi, [rax+1]\nlea rdx, [r10+rdx*4]\nmov dword ptr [rdx], 1\ncmp esi, ecx\njge short loc_13D3\nadd eax, 2\nmov dword ptr [rdx+4], 1\ncmp eax, ecx\njge short loc_13D3\nmov dword ptr [rdx+8], 1\nloc_13D3:\nlea r8, [r10+r12]\nmov esi, 1\ntest ebx, ebx\njle short loc_1430\nloc_13E0:\nxor eax, eax\nnop word ptr [rax+rax+00h]\nloc_13E8:\nxor ecx, ecx\nmov edx, esi\nsub edx, [rdi+rax*4]\njs short loc_1402\nmovsxd rdx, edx\nmovsxd rcx, eax\nimul rdx, r11\nadd rdx, rcx\nmov ecx, [r10+rdx*4]\nloc_1402:\ntest rax, rax\njz short loc_1460\nadd ecx, [r8+rax*4-4]\nmov [r8+rax*4], ecx\nadd rax, 1\ncmp r9, rax\njnz short loc_13E8\nloc_1419:\nlea eax, [rsi+1]\nadd r8, r12\ncmp ebx, esi\njz short loc_1430\nmov esi, eax\njmp short loc_13E0\nloc_1430:\nimul rbx, r11\nmovsxd rax, r13d\nadd rax, rbx\nmov eax, [r10+rax*4]\nmov rdx, [rbp+var_28]\nsub rdx, fs:28h\njnz short loc_1485\nlea rsp, [rbp-18h]\npop rbx\npop r12\npop r13\npop rbp\nretn\nloc_1460:\nmov [r8], ecx\ncmp r9, 1\njz short loc_1419\nmov eax, 1\njmp loc_13E8\nloc_1473:\nor [rsp+rdx+1030h+var_1038], 0\njmp loc_1341\nloc_147E:\nxor eax, eax\njmp loc_13AA\nloc_1485:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_12C0(__int64 a1, int a2, int a3)\n{\n __int64 v3; // r9\n unsigned __int64 v5; // r12\n __int64 v6; // rbx\n __int64 v7; // rdx\n __m128i *v8; // rsi\n __int16 v9; // dx\n signed __int64 v10; // rdx\n void *v11; // rsp\n unsigned int v12; // r13d\n unsigned __int64 v13; // r11\n __m128i si128; // xmm0\n __m128i *v15; // rax\n __int64 v16; // rdx\n __m128i *v17; // rsi\n int v18; // eax\n __int32 *v19; // rdx\n __int32 *v20; // r8\n int v21; // esi\n __int64 i; // rax\n __int32 v23; // ecx\n __int64 v25; // [rsp+0h] [rbp-1038h]\n __m128i v26; // [rsp+8h] [rbp-1030h] BYREF\n _BYTE v27[4072]; // [rsp+18h] [rbp-1020h] BYREF\n _QWORD v28[6]; // [rsp+1008h] [rbp-30h] BYREF\n\n v3 = a2;\n v5 = 4LL * a2;\n v6 = a3;\n v28[1] = __readfsqword(0x28u);\n v7 = 4 * a2 * (__int64)(a3 + 1) + 15;\n v8 = (__m128i *)((char *)v28 - (v7 & 0xFFFFFFFFFFFFF000LL));\n v9 = v7 & 0xFFF0;\n if ( v28 != (_QWORD *)v8 )\n {\n while ( &v26 != v8 )\n ;\n }\n v10 = v9 & 0xFFF;\n v11 = alloca(v10);\n if ( v10 )\n *(__int64 *)((char *)&v25 + v10) = *(__int64 *)((char *)&v25 + v10);\n v12 = a2 - 1;\n v13 = v5 >> 2;\n if ( a2 <= 0 )\n return v26.m128i_u32[v13 * v6 + (int)v12];\n if ( v12 <= 2 )\n {\n v18 = 0;\n goto LABEL_12;\n }\n si128 = _mm_load_si128((const __m128i *)&xmmword_2090);\n v15 = &v26;\n v16 = 16LL * ((unsigned int)a2 >> 2);\n v17 = (__m128i *)((char *)&v26 + v16);\n if ( (v16 & 0x10) == 0 || (v15 = (__m128i *)v27, v26 = si128, v27 != (_BYTE *)v17) )\n {\n do\n {\n *v15 = si128;\n v15 += 2;\n v15[-1] = si128;\n }\n while ( v15 != v17 );\n }\n if ( (a2 & 3) != 0 )\n {\n v18 = a2 & 0x7FFFFFFC;\nLABEL_12:\n v19 = &v26.m128i_i32[v18];\n *v19 = 1;\n if ( v18 + 1 < a2 )\n {\n v19[1] = 1;\n if ( v18 + 2 < a2 )\n v19[2] = 1;\n }\n }\n v20 = &v26.m128i_i32[v5 / 4];\n v21 = 1;\n if ( (int)v6 > 0 )\n {\n while ( 1 )\n {\n for ( i = 0LL; ; i = 1LL )\n {\n while ( 1 )\n {\n v23 = 0;\n if ( v21 - *(_DWORD *)(a1 + 4 * i) >= 0 )\n v23 = v26.m128i_i32[(int)i + v13 * (v21 - *(_DWORD *)(a1 + 4 * i))];\n if ( !i )\n break;\n v20[i] = v20[i - 1] + v23;\n if ( v3 == ++i )\n goto LABEL_21;\n }\n *v20 = v23;\n if ( v3 == 1 )\n break;\n }\nLABEL_21:\n v20 = (__int32 *)((char *)v20 + v5);\n if ( (_DWORD)v6 == v21 )\n break;\n ++v21;\n }\n }\n return v26.m128i_u32[v13 * v6 + (int)v12];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12C0(long long a1, int a2, int a3) {\n long long v3;\n unsigned long long v5;\n long long v6;\n long long v7;\n __m128i *v8;\n short v9;\n signed long long v10;\n void *v11;\n unsigned int v12;\n unsigned long long v13;\n __m128i si128;\n __m128i *v15;\n long long v16;\n __m128i *v17;\n int v18;\n int *v19;\n int *v20;\n int v21;\n long long i;\n int v23;\n long long v25;\n __m128i v26;\n uint8_t v27[4072];\n uint64_t v28[6];\n v3 = a2;\n v5 = 4LL * a2;\n v6 = a3;\n v28[1] = __readfsqword(40u);\n v7 = 4 * a2 * (long long)(a3 + 1) + 15;\n v8 = (__m128i *)((char *)v28 - (v7 & 18446744073709547520LL));\n v9 = v7 & 65520;\n if (v28 != (uint64_t *)v8) {\n while (&v26 != v8)\n ;\n }\n v10 = v9 & 4095;\n v11 = alloca(v10);\n if (v10)\n *(long long *)((char *)&v25 + v10) = *(long long *)((char *)&v25 + v10);\n v12 = a2 - 1;\n v13 = v5 >> 2;\n if (a2 <= 0) return v26.m128i_u32[v13 * v6 + (int)v12];\n if (v12 <= 2) {\n v18 = 0;\n goto LABEL_12;\n }\n si128 = _mm_load_si128((const __m128i *)&xmmword_2090);\n v15 = &v26;\n v16 = 16LL * ((unsigned int)a2 >> 2);\n v17 = (__m128i *)((char *)&v26 + v16);\n if ((v16 & 16) == 0 ||\n (v15 = (__m128i *)v27, v26 = si128, v27 != (uint8_t *)v17)) {\n do {\n *v15 = si128;\n v15 += 2;\n v15[-1] = si128;\n } while (v15 != v17);\n }\n if ((a2 & 3) != 0) {\n v18 = a2 & 2147483644;\n LABEL_12:\n v19 = &v26.m128i_i32[v18];\n *v19 = 1;\n if (v18 + 1 < a2) {\n v19[1] = 1;\n if (v18 + 2 < a2) v19[2] = 1;\n }\n }\n v20 = &v26.m128i_i32[v5 / 4];\n v21 = 1;\n if ((int)v6 > 0) {\n while (1) {\n for (i = 0LL;; i = 1LL) {\n while (1) {\n v23 = 0;\n if (v21 - *(uint32_t *)(a1 + 4 * i) >= 0)\n v23 =\n v26.m128i_i32[(int)i + v13 * (v21 - *(uint32_t *)(a1 + 4 * i))];\n if (!i) break;\n v20[i] = v20[i - 1] + v23;\n if (v3 == ++i) goto LABEL_21;\n }\n *v20 = v23;\n if (v3 == 1) break;\n }\n LABEL_21:\n v20 = (int *)((char *)v20 + v5);\n if ((uint32_t)v6 == v21) break;\n ++v21;\n }\n }\n return v26.m128i_u32[v13 * v6 + (int)v12];\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n long long v3;\n unsigned long long v5;\n long long v6;\n long long v7;\n __m128i *v8;\n short v9;\n signed long long v10;\n void *v11;\n unsigned int v12;\n unsigned long long v13;\n __m128i si128;\n __m128i *v15;\n long long v16;\n __m128i *v17;\n int v18;\n int *v19;\n int *v20;\n int v21;\n long long i;\n int v23;\n long long v25;\n __m128i v26;\n uint8_t v27[4072];\n uint64_t v28[6];\n v3 = a2;\n v5 = 4LL * a2;\n v6 = a3;\n v28[1] = __readfsqword(40u);\n v7 = 4 * a2 * (long long)(a3 + 1) + 15;\n v8 = (__m128i *)((char *)v28 - (v7 & 18446744073709547520LL));\n v9 = v7 & 65520;\n if (v28 != (uint64_t *)v8) {\n while (&v26 != v8)\n ;\n }\n v10 = v9 & 4095;\n v11 = alloca(v10);\n if (v10)\n *(long long *)((char *)&v25 + v10) = *(long long *)((char *)&v25 + v10);\n v12 = a2 - 1;\n v13 = v5 >> 2;\n if (a2 <= 0) return v26.m128i_u32[v13 * v6 + (int)v12];\n if (v12 <= 2) {\n v18 = 0;\n goto LABEL_12;\n }\n si128 = _mm_load_si128((const __m128i *)&xmmword_2090);\n v15 = &v26;\n v16 = 16LL * ((unsigned int)a2 >> 2);\n v17 = (__m128i *)((char *)&v26 + v16);\n if ((v16 & 16) == 0 ||\n (v15 = (__m128i *)v27, v26 = si128, v27 != (uint8_t *)v17)) {\n do {\n *v15 = si128;\n v15 += 2;\n v15[-1] = si128;\n } while (v15 != v17);\n }\n if ((a2 & 3) != 0) {\n v18 = a2 & 2147483644;\n LABEL_12:\n v19 = &v26.m128i_i32[v18];\n *v19 = 1;\n if (v18 + 1 < a2) {\n v19[1] = 1;\n if (v18 + 2 < a2) v19[2] = 1;\n }\n }\n v20 = &v26.m128i_i32[v5 / 4];\n v21 = 1;\n if ((int)v6 > 0) {\n while (1) {\n for (i = 0LL;; i = 1LL) {\n while (1) {\n v23 = 0;\n if (v21 - *(uint32_t *)(a1 + 4 * i) >= 0)\n v23 =\n v26.m128i_i32[(int)i + v13 * (v21 - *(uint32_t *)(a1 + 4 * i))];\n if (!i) break;\n v20[i] = v20[i - 1] + v23;\n if (v3 == ++i) goto LABEL_21;\n }\n *v20 = v23;\n if (v3 == 1) break;\n }\n LABEL_21:\n v20 = (int *)((char *)v20 + v5);\n if ((uint32_t)v6 == v21) break;\n ++v21;\n }\n }\n return v26.m128i_u32[v13 * v6 + (int)v12];\n}" + }, + { + "index": 919, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int items[], int length) {\n int tot = 1;\n for (int i = 0; i < length; i++) {\n tot *= items[i];\n }\n return tot;\n}", + "test": "int main() {\n\n int list1[] = {1, -2, 3};\n\n int list2[] = {1, 2, 3, 4};\n\n int list3[] = {3, 1, 2, 3};\n\n \n\n assert(func0(list1, 3) == -6);\n\n assert(func0(list2, 4) == 24);\n\n assert(func0(list3, 4) == 18);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x1,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11ab \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov -0x8(%rbp),%edx\nimul %edx,%eax\nmov %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1188 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 1\nmov [rbp+var_4], 0\njmp short loc_11AB\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_8]\nimul eax, edx\nmov [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_11AB:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 1;\n for ( i = 0; i < a2; ++i )\n v3 *= *(_DWORD *)(4LL * i + a1);\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 1\nmov [rbp+var_4], 0\njmp short loc_11AB\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_8]\nimul eax, edx\nmov [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_11AB:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 1;\n for ( i = 0; i < a2; ++i )\n v3 *= *(_DWORD *)(4LL * i + a1);\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 1;\n for (i = 0; i < a2; ++i) v3 *= *(uint32_t *)(4LL * i + a1);\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 1;\n for (i = 0; i < a2; ++i) v3 *= *(uint32_t *)(4LL * i + a1);\n return v3;\n}" + }, + { + "index": 919, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int items[], int length) {\n int tot = 1;\n for (int i = 0; i < length; i++) {\n tot *= items[i];\n }\n return tot;\n}", + "test": "int main() {\n\n int list1[] = {1, -2, 3};\n\n int list2[] = {1, 2, 3, 4};\n\n int list3[] = {3, 1, 2, 3};\n\n \n\n assert(func0(list1, 3) == -6);\n\n assert(func0(list2, 4) == 24);\n\n assert(func0(list3, 4) == 18);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1190 \nmov %rdi,%rax\nlea -0x1(%rsi),%edx\nlea 0x4(%rdi,%rdx,4),%rcx\nmov $0x1,%edx\nimul (%rax),%edx\nadd $0x4,%rax\ncmp %rcx,%rax\njne 1181 \nmov %edx,%eax\nretq\nmov $0x1,%edx\njmp 118d \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_118F\nmov rax, rdi\nmovsxd rsi, esi\nlea rcx, [rdi+rsi*4]\nmov edx, 1\nloc_1180:\nimul edx, [rax]\nadd rax, 4\ncmp rax, rcx\njnz short loc_1180\nloc_118C:\nmov eax, edx\nretn\nloc_118F:\nmov edx, 1\njmp short loc_118C", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n unsigned int v3; // edx\n\n if ( a2 <= 0 )\n {\n return 1;\n }\n else\n {\n v2 = a1;\n v3 = 1;\n do\n v3 *= *v2++;\n while ( v2 != &a1[a2] );\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_118F\nmov rax, rdi\nmovsxd rsi, esi\nlea rcx, [rdi+rsi*4]\nmov edx, 1\nloc_1180:\nimul edx, [rax]\nadd rax, 4\ncmp rax, rcx\njnz short loc_1180\nloc_118C:\nmov eax, edx\nretn\nloc_118F:\nmov edx, 1\njmp short loc_118C", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n unsigned int v3; // edx\n\n if ( a2 <= 0 )\n {\n return 1;\n }\n else\n {\n v2 = a1;\n v3 = 1;\n do\n v3 *= *v2++;\n while ( v2 != &a1[a2] );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2) {\n uint32_t *v2;\n unsigned int v3;\n if (a2 <= 0) {\n return 1;\n } else {\n v2 = a1;\n v3 = 1;\n do\n v3 *= *v2++;\n while (v2 != &a1[a2]);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n unsigned int v3;\n if (a2 <= 0) {\n return 1;\n } else {\n v2 = a1;\n v3 = 1;\n do\n v3 *= *v2++;\n while (v2 != &a1[a2]);\n }\n return v3;\n}" + }, + { + "index": 920, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int has_first;\n\n int first;\n\n int has_second;\n\n int second;\n\n} tuple_t;\n\n\n\n", + "func": "char* func0(tuple_t* test_list, int size) {\n char* res = malloc(1024);\n if (!res) return NULL;\n strcpy(res, \"[\");\n int first = 1;\n for (int i = 0; i < size; i++) {\n int all_null = 1;\n if (test_list[i].has_first) all_null = 0;\n if (test_list[i].has_second) all_null = 0;\n if (!all_null) {\n if (!first) strcat(res, \", \");\n first = 0;\n strcat(res, \"(\");\n if (test_list[i].has_first) {\n char num[20];\n sprintf(num, \"%d\", test_list[i].first);\n strcat(res, num);\n } else {\n strcat(res, \"None\");\n }\n strcat(res, \", \");\n if (test_list[i].has_second) {\n char num[20];\n sprintf(num, \"%d\", test_list[i].second);\n strcat(res, num);\n } else {\n strcat(res, \"None\");\n }\n strcat(res, \")\");\n }\n }\n strcat(res, \"]\");\n return res;\n}", + "test": "int main() {\n\n // First test case\n\n tuple_t test1[] = {\n\n {0, 0, 1, 2},\n\n {0, 0, 0, 0},\n\n {1, 3, 1, 4},\n\n {1, 12, 1, 3},\n\n {0, 0, 0, 0}\n\n };\n\n char* result1 = func0(test1, 5);\n\n assert(strcmp(result1, \"[(None, 2), (3, 4), (12, 3)]\") == 0);\n\n free(result1);\n\n\n\n // Second test case\n\n tuple_t test2[] = {\n\n {0, 0, 0, 0},\n\n {0, 0, 0, 0},\n\n {1, 3, 1, 6},\n\n {1, 17, 1, 3},\n\n {0, 0, 1, 1}\n\n };\n\n char* result2 = func0(test2, 5);\n\n assert(strcmp(result2, \"[(3, 6), (17, 3), (None, 1)]\") == 0);\n\n free(result2);\n\n\n\n // Third test case\n\n tuple_t test3[] = {\n\n {1, 1, 1, 2},\n\n {1, 2, 0, 0},\n\n {1, 3, 0, 0},\n\n {1, 24, 1, 3},\n\n {0, 0, 0, 0}\n\n };\n\n char* result3 = func0(test3, 5);\n\n assert(strcmp(result3, \"[(1, 2), (2, None), (3, None), (24, 3)]\") == 0);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x50,%rsp\nmov %rdi,-0x48(%rbp)\nmov %esi,-0x4c(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmov $0x400,%edi\ncallq 10f0 \nmov %rax,-0x28(%rbp)\ncmpq $0x0,-0x28(%rbp)\njne 124a \nmov $0x0,%eax\njmpq 14e6 \nmov -0x28(%rbp),%rax\nmovw $0x5b,(%rax)\nmovl $0x1,-0x34(%rbp)\nmovl $0x0,-0x30(%rbp)\njmpq 14a8 \nmovl $0x1,-0x2c(%rbp)\nmov -0x30(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ntest %eax,%eax\nje 128d \nmovl $0x0,-0x2c(%rbp)\nmov -0x30(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov 0x8(%rax),%eax\ntest %eax,%eax\nje 12ae \nmovl $0x0,-0x2c(%rbp)\ncmpl $0x0,-0x2c(%rbp)\njne 14a4 \ncmpl $0x0,-0x34(%rbp)\njne 12f0 \nmov -0x28(%rbp),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovw $0x202c,(%rax)\nmovb $0x0,0x2(%rax)\nmovl $0x0,-0x34(%rbp)\nmov -0x28(%rbp),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovw $0x28,(%rax)\nmov -0x30(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ntest %eax,%eax\nje 1381 \nmov -0x30(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov 0x4(%rax),%edx\nlea -0x20(%rbp),%rax\nlea 0xca9(%rip),%rsi\nmov %rax,%rdi\nmov $0x0,%eax\ncallq 1110 \nlea -0x20(%rbp),%rdx\nmov -0x28(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1100 \njmp 13b4 \nmov -0x28(%rbp),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovl $0x656e6f4e,(%rax)\nmovb $0x0,0x4(%rax)\nmov -0x28(%rbp),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovw $0x202c,(%rax)\nmovb $0x0,0x2(%rax)\nmov -0x30(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov 0x8(%rax),%eax\ntest %eax,%eax\nje 1443 \nmov -0x30(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov 0xc(%rax),%edx\nlea -0x20(%rbp),%rax\nlea 0xbe7(%rip),%rsi\nmov %rax,%rdi\nmov $0x0,%eax\ncallq 1110 \nlea -0x20(%rbp),%rdx\nmov -0x28(%rbp),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1100 \njmp 1476 \nmov -0x28(%rbp),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovl $0x656e6f4e,(%rax)\nmovb $0x0,0x4(%rax)\nmov -0x28(%rbp),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovw $0x29,(%rax)\naddl $0x1,-0x30(%rbp)\nmov -0x30(%rbp),%eax\ncmp -0x4c(%rbp),%eax\njl 1266 \nmov -0x28(%rbp),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovw $0x5d,(%rax)\nmov -0x28(%rbp),%rax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 14fa \ncallq 10c0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+var_48], rdi\nmov [rbp+var_4C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov edi, 400h; size\ncall _malloc\nmov [rbp+s], rax\ncmp [rbp+s], 0\njnz short loc_126A\nmov eax, 0\njmp loc_1487\nloc_126A:\nmov rax, [rbp+s]\nmov word ptr [rax], 5Bh ; '['\nmov [rbp+var_34], 1\nmov [rbp+var_30], 0\njmp loc_145C\nloc_1286:\nmov [rbp+var_2C], 1\nmov eax, [rbp+var_30]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njz short loc_12AD\nmov [rbp+var_2C], 0\nloc_12AD:\nmov eax, [rbp+var_30]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax+8]\ntest eax, eax\njz short loc_12CE\nmov [rbp+var_2C], 0\nloc_12CE:\ncmp [rbp+var_2C], 0\njnz loc_1458\ncmp [rbp+var_34], 0\njnz short loc_12FD\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+s]\nadd rax, rdx\nmov word ptr [rax], 202Ch\nmov byte ptr [rax+2], 0\nloc_12FD:\nmov [rbp+var_34], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+s]\nadd rax, rdx\nmov word ptr [rax], 28h ; '('\nmov eax, [rbp+var_30]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njz short loc_137E\nmov eax, [rbp+var_30]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov edx, [rax+4]\nlea rax, [rbp+src]\nlea rcx, format; \"%d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rdx, [rbp+src]\nmov rax, [rbp+s]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\njmp short loc_139E\nloc_137E:\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+s]\nadd rax, rdx\nmov dword ptr [rax], 656E6F4Eh\nmov byte ptr [rax+4], 0\nloc_139E:\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+s]\nadd rax, rdx\nmov word ptr [rax], 202Ch\nmov byte ptr [rax+2], 0\nmov eax, [rbp+var_30]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax+8]\ntest eax, eax\njz short loc_141D\nmov eax, [rbp+var_30]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov edx, [rax+0Ch]\nlea rax, [rbp+src]\nlea rcx, format; \"%d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rdx, [rbp+src]\nmov rax, [rbp+s]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\njmp short loc_143D\nloc_141D:\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+s]\nadd rax, rdx\nmov dword ptr [rax], 656E6F4Eh\nmov byte ptr [rax+4], 0\nloc_143D:\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+s]\nadd rax, rdx\nmov word ptr [rax], 29h ; ')'\nloc_1458:\nadd [rbp+var_30], 1\nloc_145C:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_4C]\njl loc_1286\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+s]\nadd rax, rdx\nmov word ptr [rax], 5Dh ; ']'\nmov rax, [rbp+s]\nloc_1487:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_149B\ncall ___stack_chk_fail\nlocret_149B:\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2)\n{\n int v3; // [rsp+1Ch] [rbp-34h]\n int i; // [rsp+20h] [rbp-30h]\n _BOOL4 v5; // [rsp+24h] [rbp-2Ch]\n char *s; // [rsp+28h] [rbp-28h]\n char src[24]; // [rsp+30h] [rbp-20h] BYREF\n unsigned __int64 v8; // [rsp+48h] [rbp-8h]\n\n v8 = __readfsqword(0x28u);\n s = (char *)malloc(0x400uLL);\n if ( !s )\n return 0LL;\n *(_WORD *)s = 91;\n v3 = 1;\n for ( i = 0; i < a2; ++i )\n {\n v5 = *(_DWORD *)(16LL * i + a1) == 0;\n if ( *(_DWORD *)(16LL * i + a1 + 8) )\n v5 = 0;\n if ( !v5 )\n {\n if ( !v3 )\n strcpy(&s[strlen(s)], \", \");\n v3 = 0;\n *(_WORD *)&s[strlen(s)] = 40;\n if ( *(_DWORD *)(16LL * i + a1) )\n {\n sprintf(src, \"%d\", *(_DWORD *)(16LL * i + a1 + 4));\n strcat(s, src);\n }\n else\n {\n strcpy(&s[strlen(s)], \"None\");\n }\n strcpy(&s[strlen(s)], \", \");\n if ( *(_DWORD *)(16LL * i + a1 + 8) )\n {\n sprintf(src, \"%d\", *(_DWORD *)(16LL * i + a1 + 12));\n strcat(s, src);\n }\n else\n {\n strcpy(&s[strlen(s)], \"None\");\n }\n *(_WORD *)&s[strlen(s)] = 41;\n }\n }\n *(_WORD *)&s[strlen(s)] = 93;\n return s;\n}", + "ida_strip_asm": "sub_1229:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 50h\nmov [rbp+var_48], rdi\nmov [rbp+var_4C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov edi, 400h; size\ncall _malloc\nmov [rbp+s], rax\ncmp [rbp+s], 0\njnz short loc_126A\nmov eax, 0\njmp loc_1487\nloc_126A:\nmov rax, [rbp+s]\nmov word ptr [rax], 5Bh ; '['\nmov [rbp+var_34], 1\nmov [rbp+var_30], 0\njmp loc_145C\nloc_1286:\nmov [rbp+var_2C], 1\nmov eax, [rbp+var_30]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njz short loc_12AD\nmov [rbp+var_2C], 0\nloc_12AD:\nmov eax, [rbp+var_30]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax+8]\ntest eax, eax\njz short loc_12CE\nmov [rbp+var_2C], 0\nloc_12CE:\ncmp [rbp+var_2C], 0\njnz loc_1458\ncmp [rbp+var_34], 0\njnz short loc_12FD\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+s]\nadd rax, rdx\nmov word ptr [rax], 202Ch\nmov byte ptr [rax+2], 0\nloc_12FD:\nmov [rbp+var_34], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+s]\nadd rax, rdx\nmov word ptr [rax], 28h ; '('\nmov eax, [rbp+var_30]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax]\ntest eax, eax\njz short loc_137E\nmov eax, [rbp+var_30]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov edx, [rax+4]\nlea rax, [rbp+src]\nlea rcx, format; \"%d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rdx, [rbp+src]\nmov rax, [rbp+s]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\njmp short loc_139E\nloc_137E:\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+s]\nadd rax, rdx\nmov dword ptr [rax], 656E6F4Eh\nmov byte ptr [rax+4], 0\nloc_139E:\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+s]\nadd rax, rdx\nmov word ptr [rax], 202Ch\nmov byte ptr [rax+2], 0\nmov eax, [rbp+var_30]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov eax, [rax+8]\ntest eax, eax\njz short loc_141D\nmov eax, [rbp+var_30]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov edx, [rax+0Ch]\nlea rax, [rbp+src]\nlea rcx, format; \"%d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rdx, [rbp+src]\nmov rax, [rbp+s]\nmov rsi, rdx; src\nmov rdi, rax; dest\ncall _strcat\njmp short loc_143D\nloc_141D:\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+s]\nadd rax, rdx\nmov dword ptr [rax], 656E6F4Eh\nmov byte ptr [rax+4], 0\nloc_143D:\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+s]\nadd rax, rdx\nmov word ptr [rax], 29h ; ')'\nloc_1458:\nadd [rbp+var_30], 1\nloc_145C:\nmov eax, [rbp+var_30]\ncmp eax, [rbp+var_4C]\njl loc_1286\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov rax, [rbp+s]\nadd rax, rdx\nmov word ptr [rax], 5Dh ; ']'\nmov rax, [rbp+s]\nloc_1487:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_149B\ncall ___stack_chk_fail\nlocret_149B:\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1229(__int64 a1, int a2)\n{\n int v3; // [rsp+1Ch] [rbp-34h]\n int i; // [rsp+20h] [rbp-30h]\n _BOOL4 v5; // [rsp+24h] [rbp-2Ch]\n char *s; // [rsp+28h] [rbp-28h]\n char src[24]; // [rsp+30h] [rbp-20h] BYREF\n unsigned __int64 v8; // [rsp+48h] [rbp-8h]\n\n v8 = __readfsqword(0x28u);\n s = (char *)malloc(0x400uLL);\n if ( !s )\n return 0LL;\n *(_WORD *)s = 91;\n v3 = 1;\n for ( i = 0; i < a2; ++i )\n {\n v5 = *(_DWORD *)(16LL * i + a1) == 0;\n if ( *(_DWORD *)(16LL * i + a1 + 8) )\n v5 = 0;\n if ( !v5 )\n {\n if ( !v3 )\n strcpy(&s[strlen(s)], \", \");\n v3 = 0;\n *(_WORD *)&s[strlen(s)] = 40;\n if ( *(_DWORD *)(16LL * i + a1) )\n {\n sprintf(src, \"%d\", *(_DWORD *)(16LL * i + a1 + 4));\n strcat(s, src);\n }\n else\n {\n strcpy(&s[strlen(s)], \"None\");\n }\n strcpy(&s[strlen(s)], \", \");\n if ( *(_DWORD *)(16LL * i + a1 + 8) )\n {\n sprintf(src, \"%d\", *(_DWORD *)(16LL * i + a1 + 12));\n strcat(s, src);\n }\n else\n {\n strcpy(&s[strlen(s)], \"None\");\n }\n *(_WORD *)&s[strlen(s)] = 41;\n }\n }\n *(_WORD *)&s[strlen(s)] = 93;\n return s;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1229(long long a1, int a2) {\n int v3;\n int i;\n int v5;\n char *s;\n char src[24];\n unsigned long long v8;\n v8 = __readfsqword(40u);\n s = (char *)malloc(1024uLL);\n if (!s) return 0LL;\n *(unsigned short *)s = 91;\n v3 = 1;\n for (i = 0; i < a2; ++i) {\n v5 = *(uint32_t *)(16LL * i + a1) == 0;\n if (*(uint32_t *)(16LL * i + a1 + 8)) v5 = 0;\n if (!v5) {\n if (!v3) strcpy(&s[strlen(s)], \", \");\n v3 = 0;\n *(unsigned short *)&s[strlen(s)] = 40;\n if (*(uint32_t *)(16LL * i + a1)) {\n sprintf(src, \"%d\", *(uint32_t *)(16LL * i + a1 + 4));\n strcat(s, src);\n } else {\n strcpy(&s[strlen(s)], \"None\");\n }\n strcpy(&s[strlen(s)], \", \");\n if (*(uint32_t *)(16LL * i + a1 + 8)) {\n sprintf(src, \"%d\", *(uint32_t *)(16LL * i + a1 + 12));\n strcat(s, src);\n } else {\n strcpy(&s[strlen(s)], \"None\");\n }\n *(unsigned short *)&s[strlen(s)] = 41;\n }\n }\n *(unsigned short *)&s[strlen(s)] = 93;\n return s;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2) {\n int v3;\n int i;\n int v5;\n char *s;\n char src[24];\n unsigned long long v8;\n v8 = __readfsqword(40u);\n s = (char *)malloc(1024uLL);\n if (!s) return 0LL;\n *(unsigned short *)s = 91;\n v3 = 1;\n for (i = 0; i < a2; ++i) {\n v5 = *(uint32_t *)(16LL * i + a1) == 0;\n if (*(uint32_t *)(16LL * i + a1 + 8)) v5 = 0;\n if (!v5) {\n if (!v3) strcpy(&s[strlen(s)], \", \");\n v3 = 0;\n *(unsigned short *)&s[strlen(s)] = 40;\n if (*(uint32_t *)(16LL * i + a1)) {\n sprintf(src, \"%d\", *(uint32_t *)(16LL * i + a1 + 4));\n strcat(s, src);\n } else {\n strcpy(&s[strlen(s)], \"None\");\n }\n strcpy(&s[strlen(s)], \", \");\n if (*(uint32_t *)(16LL * i + a1 + 8)) {\n sprintf(src, \"%d\", *(uint32_t *)(16LL * i + a1 + 12));\n strcat(s, src);\n } else {\n strcpy(&s[strlen(s)], \"None\");\n }\n *(unsigned short *)&s[strlen(s)] = 41;\n }\n }\n *(unsigned short *)&s[strlen(s)] = 93;\n return s;\n}" + }, + { + "index": 920, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int has_first;\n\n int first;\n\n int has_second;\n\n int second;\n\n} tuple_t;\n\n\n\n", + "func": "char* func0(tuple_t* test_list, int size) {\n char* res = malloc(1024);\n if (!res) return NULL;\n strcpy(res, \"[\");\n int first = 1;\n for (int i = 0; i < size; i++) {\n int all_null = 1;\n if (test_list[i].has_first) all_null = 0;\n if (test_list[i].has_second) all_null = 0;\n if (!all_null) {\n if (!first) strcat(res, \", \");\n first = 0;\n strcat(res, \"(\");\n if (test_list[i].has_first) {\n char num[20];\n sprintf(num, \"%d\", test_list[i].first);\n strcat(res, num);\n } else {\n strcat(res, \"None\");\n }\n strcat(res, \", \");\n if (test_list[i].has_second) {\n char num[20];\n sprintf(num, \"%d\", test_list[i].second);\n strcat(res, num);\n } else {\n strcat(res, \"None\");\n }\n strcat(res, \")\");\n }\n }\n strcat(res, \"]\");\n return res;\n}", + "test": "int main() {\n\n // First test case\n\n tuple_t test1[] = {\n\n {0, 0, 1, 2},\n\n {0, 0, 0, 0},\n\n {1, 3, 1, 4},\n\n {1, 12, 1, 3},\n\n {0, 0, 0, 0}\n\n };\n\n char* result1 = func0(test1, 5);\n\n assert(strcmp(result1, \"[(None, 2), (3, 4), (12, 3)]\") == 0);\n\n free(result1);\n\n\n\n // Second test case\n\n tuple_t test2[] = {\n\n {0, 0, 0, 0},\n\n {0, 0, 0, 0},\n\n {1, 3, 1, 6},\n\n {1, 17, 1, 3},\n\n {0, 0, 1, 1}\n\n };\n\n char* result2 = func0(test2, 5);\n\n assert(strcmp(result2, \"[(3, 6), (17, 3), (None, 1)]\") == 0);\n\n free(result2);\n\n\n\n // Third test case\n\n tuple_t test3[] = {\n\n {1, 1, 1, 2},\n\n {1, 2, 0, 0},\n\n {1, 3, 0, 0},\n\n {1, 24, 1, 3},\n\n {0, 0, 0, 0}\n\n };\n\n char* result3 = func0(test3, 5);\n\n assert(strcmp(result3, \"[(1, 2), (2, None), (3, None), (24, 3)]\") == 0);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x28,%rsp\nmov %rdi,%r13\nmov %esi,%r12d\nmov %fs:0x28,%rax\nmov %rax,0x18(%rsp)\nxor %eax,%eax\nmov $0x400,%edi\ncallq 10e0 \nmov %rax,%rbp\ntest %rax,%rax\nje 1387 \nmovw $0x5b,(%rax)\ntest %r12d,%r12d\njle 1373 \nmov %r13,%rbx\nlea -0x1(%r12),%eax\nshl $0x4,%rax\nlea 0x10(%r13,%rax,1),%r14\nmov $0x1,%eax\nmov $0x0,%r15d\njmp 12ba \nmov $0x400,%edx\nlea 0xda5(%rip),%rsi\nmov %rbp,%rdi\ncallq 10a0 <__strcat_chk@plt>\njmp 12cc \nmov $0x400,%edx\nlea 0xd97(%rip),%rsi\nmov %rbp,%rdi\ncallq 10a0 <__strcat_chk@plt>\njmpq 131a \nmov $0x400,%edx\nlea 0xd7e(%rip),%rsi\nmov %rbp,%rdi\ncallq 10a0 <__strcat_chk@plt>\nmov $0x400,%edx\nlea 0xd6f(%rip),%rsi\nmov %rbp,%rdi\ncallq 10a0 <__strcat_chk@plt>\nmov %r15d,%eax\nadd $0x10,%rbx\ncmp %r14,%rbx\nje 1373 \nmov %rbx,%r13\nmov (%rbx),%r12d\nmov %r12d,%ecx\nor 0x8(%rbx),%ecx\nje 12ad \ntest %eax,%eax\nje 1253 \nmov $0x400,%edx\nlea 0xd2f(%rip),%rsi\nmov %rbp,%rdi\ncallq 10a0 <__strcat_chk@plt>\ntest %r12d,%r12d\nje 1269 \nmov %rsp,%r12\nmov 0x4(%r13),%r8d\nlea 0xd16(%rip),%rcx\nmov $0x14,%edx\nmov $0x1,%esi\nmov %r12,%rdi\nmov $0x0,%eax\ncallq 10f0 <__sprintf_chk@plt>\nmov $0x400,%edx\nmov %r12,%rsi\nmov %rbp,%rdi\ncallq 10a0 <__strcat_chk@plt>\nmov $0x400,%edx\nlea 0xcde(%rip),%rsi\nmov %rbp,%rdi\ncallq 10a0 <__strcat_chk@plt>\ncmpl $0x0,0x8(%r13)\nje 1282 \nmov %rsp,%r12\nmov 0xc(%r13),%r8d\nlea 0xcc2(%rip),%rcx\nmov $0x14,%edx\nmov $0x1,%esi\nmov %r12,%rdi\nmov $0x0,%eax\ncallq 10f0 <__sprintf_chk@plt>\nmov $0x400,%edx\nmov %r12,%rsi\nmov %rbp,%rdi\ncallq 10a0 <__strcat_chk@plt>\njmpq 1296 \nmov $0x400,%edx\nlea 0xccc(%rip),%rsi\nmov %rbp,%rdi\ncallq 10a0 <__strcat_chk@plt>\nmov 0x18(%rsp),%rax\nxor %fs:0x28,%rax\njne 13a9 \nmov %rbp,%rax\nadd $0x28,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\ncallq 10c0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov r14, rdi\nmov r12d, esi\nmov rax, fs:28h\nmov [rsp+58h+var_40], rax\nxor eax, eax\nmov edi, 400h; size\ncall _malloc\nmov rbp, rax\ntest rax, rax\njz loc_139E\nmov word ptr [rax], 5Bh ; '['\ntest r12d, r12d\njle loc_138A\nmov rbx, r14\nmovsxd r12, r12d\nshl r12, 4\nadd r14, r12\nmov eax, 1\nlea r15, unk_2004\njmp short loc_12D5\nloc_1270:\nmov edx, 400h\nmov rsi, r15\nmov rdi, rbp\ncall ___strcat_chk\njmp short loc_12E7\nloc_1282:\nmov edx, 400h\nlea rsi, aNone; \"None\"\nmov rdi, rbp\ncall ___strcat_chk\njmp loc_1335\nloc_129B:\nmov edx, 400h\nlea rsi, aNone; \"None\"\nmov rdi, rbp\ncall ___strcat_chk\nloc_12AF:\nmov edx, 400h\nlea rsi, asc_2011; \")\"\nmov rdi, rbp\ncall ___strcat_chk\nmov eax, 0\nloc_12C8:\nadd rbx, 10h\ncmp rbx, r14\njz loc_138A\nloc_12D5:\nmov r13, rbx\nmov r12d, [rbx]\nmov ecx, r12d\nor ecx, [rbx+8]\njz short loc_12C8\ntest eax, eax\njz short loc_1270\nloc_12E7:\nmov edx, 400h\nlea rsi, unk_2007\nmov rdi, rbp\ncall ___strcat_chk\ntest r12d, r12d\njz short loc_1282\nmov r12, rsp\nmov r8d, [r13+4]\nlea rcx, unk_2009\nmov edx, 14h\nmov esi, 2\nmov rdi, r12\nmov eax, 0\ncall ___sprintf_chk\nmov edx, 400h\nmov rsi, r12\nmov rdi, rbp\ncall ___strcat_chk\nloc_1335:\nmov edx, 400h\nmov rsi, r15\nmov rdi, rbp\ncall ___strcat_chk\ncmp dword ptr [r13+8], 0\njz loc_129B\nmov r12, rsp\nmov r8d, [r13+0Ch]\nlea rcx, unk_2009\nmov edx, 14h\nmov esi, 2\nmov rdi, r12\nmov eax, 0\ncall ___sprintf_chk\nmov edx, 400h\nmov rsi, r12\nmov rdi, rbp\ncall ___strcat_chk\njmp loc_12AF\nloc_138A:\nmov edx, 400h\nlea rsi, a36173None1+1Bh; \"]\"\nmov rdi, rbp\ncall ___strcat_chk\nloc_139E:\nmov rax, [rsp+58h+var_40]\nsub rax, fs:28h\njnz short loc_13C0\nmov rax, rbp\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_13C0:\ncall ___stack_chk_fail", + "ida_pseudo": "_WORD *__fastcall func0(int *a1, int a2)\n{\n _WORD *v2; // rax\n _WORD *v3; // rbp\n int *v4; // rbx\n int v5; // eax\n int v6; // r12d\n _QWORD v8[11]; // [rsp+0h] [rbp-58h] BYREF\n\n v8[3] = __readfsqword(0x28u);\n v2 = malloc(0x400uLL);\n v3 = v2;\n if ( v2 )\n {\n *v2 = 91;\n if ( a2 > 0 )\n {\n v4 = a1;\n v5 = 1;\n do\n {\n v6 = *v4;\n if ( v4[2] | *v4 )\n {\n if ( !v5 )\n __strcat_chk(v3, &unk_2004, 1024LL);\n __strcat_chk(v3, &unk_2007, 1024LL);\n if ( v6 )\n {\n __sprintf_chk(v8, 2LL, 20LL, &unk_2009, (unsigned int)v4[1]);\n __strcat_chk(v3, v8, 1024LL);\n }\n else\n {\n __strcat_chk(v3, \"None\", 1024LL);\n }\n __strcat_chk(v3, &unk_2004, 1024LL);\n if ( v4[2] )\n {\n __sprintf_chk(v8, 2LL, 20LL, &unk_2009, (unsigned int)v4[3]);\n __strcat_chk(v3, v8, 1024LL);\n }\n else\n {\n __strcat_chk(v3, \"None\", 1024LL);\n }\n __strcat_chk(v3, \")\", 1024LL);\n v5 = 0;\n }\n v4 += 4;\n }\n while ( v4 != &a1[4 * a2] );\n }\n __strcat_chk(v3, \"]\", 1024LL);\n }\n return v3;\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov r14, rdi\nmov r12d, esi\nmov rax, fs:28h\nmov [rsp+58h+var_40], rax\nxor eax, eax\nmov edi, 400h; size\ncall _malloc\nmov rbp, rax\ntest rax, rax\njz loc_139E\nmov word ptr [rax], 5Bh ; '['\ntest r12d, r12d\njle loc_138A\nmov rbx, r14\nmovsxd r12, r12d\nshl r12, 4\nadd r14, r12\nmov eax, 1\nlea r15, unk_2004\njmp short loc_12D5\nloc_1270:\nmov edx, 400h\nmov rsi, r15\nmov rdi, rbp\ncall ___strcat_chk\njmp short loc_12E7\nloc_1282:\nmov edx, 400h\nlea rsi, aNone; \"None\"\nmov rdi, rbp\ncall ___strcat_chk\njmp loc_1335\nloc_129B:\nmov edx, 400h\nlea rsi, aNone; \"None\"\nmov rdi, rbp\ncall ___strcat_chk\nloc_12AF:\nmov edx, 400h\nlea rsi, asc_2011; \")\"\nmov rdi, rbp\ncall ___strcat_chk\nmov eax, 0\nloc_12C8:\nadd rbx, 10h\ncmp rbx, r14\njz loc_138A\nloc_12D5:\nmov r13, rbx\nmov r12d, [rbx]\nmov ecx, r12d\nor ecx, [rbx+8]\njz short loc_12C8\ntest eax, eax\njz short loc_1270\nloc_12E7:\nmov edx, 400h\nlea rsi, unk_2007\nmov rdi, rbp\ncall ___strcat_chk\ntest r12d, r12d\njz short loc_1282\nmov r12, rsp\nmov r8d, [r13+4]\nlea rcx, unk_2009\nmov edx, 14h\nmov esi, 2\nmov rdi, r12\nmov eax, 0\ncall ___sprintf_chk\nmov edx, 400h\nmov rsi, r12\nmov rdi, rbp\ncall ___strcat_chk\nloc_1335:\nmov edx, 400h\nmov rsi, r15\nmov rdi, rbp\ncall ___strcat_chk\ncmp dword ptr [r13+8], 0\njz loc_129B\nmov r12, rsp\nmov r8d, [r13+0Ch]\nlea rcx, unk_2009\nmov edx, 14h\nmov esi, 2\nmov rdi, r12\nmov eax, 0\ncall ___sprintf_chk\nmov edx, 400h\nmov rsi, r12\nmov rdi, rbp\ncall ___strcat_chk\njmp loc_12AF\nloc_138A:\nmov edx, 400h\nlea rsi, a36173None1+1Bh; \"]\"\nmov rdi, rbp\ncall ___strcat_chk\nloc_139E:\nmov rax, [rsp+58h+var_40]\nsub rax, fs:28h\njnz short loc_13C0\nmov rax, rbp\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_13C0:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "_WORD *__fastcall sub_1209(int *a1, int a2)\n{\n _WORD *v2; // rax\n _WORD *v3; // rbp\n int *v4; // rbx\n int v5; // eax\n int v6; // r12d\n _QWORD v8[11]; // [rsp+0h] [rbp-58h] BYREF\n\n v8[3] = __readfsqword(0x28u);\n v2 = malloc(0x400uLL);\n v3 = v2;\n if ( v2 )\n {\n *v2 = 91;\n if ( a2 > 0 )\n {\n v4 = a1;\n v5 = 1;\n do\n {\n v6 = *v4;\n if ( v4[2] | *v4 )\n {\n if ( !v5 )\n __strcat_chk(v3, &unk_2004, 1024LL);\n __strcat_chk(v3, &unk_2007, 1024LL);\n if ( v6 )\n {\n __sprintf_chk(v8, 2LL, 20LL, &unk_2009, (unsigned int)v4[1]);\n __strcat_chk(v3, v8, 1024LL);\n }\n else\n {\n __strcat_chk(v3, \"None\", 1024LL);\n }\n __strcat_chk(v3, &unk_2004, 1024LL);\n if ( v4[2] )\n {\n __sprintf_chk(v8, 2LL, 20LL, &unk_2009, (unsigned int)v4[3]);\n __strcat_chk(v3, v8, 1024LL);\n }\n else\n {\n __strcat_chk(v3, \"None\", 1024LL);\n }\n __strcat_chk(v3, \")\", 1024LL);\n v5 = 0;\n }\n v4 += 4;\n }\n while ( v4 != &a1[4 * a2] );\n }\n __strcat_chk(v3, \"]\", 1024LL);\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned short *sub_1209(int *a1, int a2) {\n unsigned short *v2;\n unsigned short *v3;\n int *v4;\n int v5;\n int v6;\n uint64_t v8[11];\n v8[3] = __readfsqword(40u);\n v2 = malloc(1024uLL);\n v3 = v2;\n if (v2) {\n *v2 = 91;\n if (a2 > 0) {\n v4 = a1;\n v5 = 1;\n do {\n v6 = *v4;\n if (v4[2] | *v4) {\n if (!v5) __strcat_chk(v3, &unk_2004, 1024LL);\n __strcat_chk(v3, &unk_2007, 1024LL);\n if (v6) {\n __sprintf_chk(v8, 2LL, 20LL, &unk_2009, (unsigned int)v4[1]);\n __strcat_chk(v3, v8, 1024LL);\n } else {\n __strcat_chk(v3, \"None\", 1024LL);\n }\n __strcat_chk(v3, &unk_2004, 1024LL);\n if (v4[2]) {\n __sprintf_chk(v8, 2LL, 20LL, &unk_2009, (unsigned int)v4[3]);\n __strcat_chk(v3, v8, 1024LL);\n } else {\n __strcat_chk(v3, \"None\", 1024LL);\n }\n __strcat_chk(v3, \")\", 1024LL);\n v5 = 0;\n }\n v4 += 4;\n } while (v4 != &a1[4 * a2]);\n }\n __strcat_chk(v3, \"]\", 1024LL);\n }\n return v3;\n}", + "ida_pseudo_norm": "unsigned short *func0(int *a1, int a2) {\n unsigned short *v2;\n unsigned short *v3;\n int *v4;\n int v5;\n int v6;\n uint64_t v8[11];\n v8[3] = __readfsqword(40u);\n v2 = malloc(1024uLL);\n v3 = v2;\n if (v2) {\n *v2 = 91;\n if (a2 > 0) {\n v4 = a1;\n v5 = 1;\n do {\n v6 = *v4;\n if (v4[2] | *v4) {\n if (!v5) __strcat_chk(v3, &unk_2004, 1024LL);\n __strcat_chk(v3, &unk_2007, 1024LL);\n if (v6) {\n __sprintf_chk(v8, 2LL, 20LL, &unk_2009, (unsigned int)v4[1]);\n __strcat_chk(v3, v8, 1024LL);\n } else {\n __strcat_chk(v3, \"None\", 1024LL);\n }\n __strcat_chk(v3, &unk_2004, 1024LL);\n if (v4[2]) {\n __sprintf_chk(v8, 2LL, 20LL, &unk_2009, (unsigned int)v4[3]);\n __strcat_chk(v3, v8, 1024LL);\n } else {\n __strcat_chk(v3, \"None\", 1024LL);\n }\n __strcat_chk(v3, \")\", 1024LL);\n v5 = 0;\n }\n v4 += 4;\n } while (v4 != &a1[4 * a2]);\n }\n __strcat_chk(v3, \"]\", 1024LL);\n }\n return v3;\n}" + }, + { + "index": 920, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int has_first;\n\n int first;\n\n int has_second;\n\n int second;\n\n} tuple_t;\n\n\n\n", + "func": "char* func0(tuple_t* test_list, int size) {\n char* res = malloc(1024);\n if (!res) return NULL;\n strcpy(res, \"[\");\n int first = 1;\n for (int i = 0; i < size; i++) {\n int all_null = 1;\n if (test_list[i].has_first) all_null = 0;\n if (test_list[i].has_second) all_null = 0;\n if (!all_null) {\n if (!first) strcat(res, \", \");\n first = 0;\n strcat(res, \"(\");\n if (test_list[i].has_first) {\n char num[20];\n sprintf(num, \"%d\", test_list[i].first);\n strcat(res, num);\n } else {\n strcat(res, \"None\");\n }\n strcat(res, \", \");\n if (test_list[i].has_second) {\n char num[20];\n sprintf(num, \"%d\", test_list[i].second);\n strcat(res, num);\n } else {\n strcat(res, \"None\");\n }\n strcat(res, \")\");\n }\n }\n strcat(res, \"]\");\n return res;\n}", + "test": "int main() {\n\n // First test case\n\n tuple_t test1[] = {\n\n {0, 0, 1, 2},\n\n {0, 0, 0, 0},\n\n {1, 3, 1, 4},\n\n {1, 12, 1, 3},\n\n {0, 0, 0, 0}\n\n };\n\n char* result1 = func0(test1, 5);\n\n assert(strcmp(result1, \"[(None, 2), (3, 4), (12, 3)]\") == 0);\n\n free(result1);\n\n\n\n // Second test case\n\n tuple_t test2[] = {\n\n {0, 0, 0, 0},\n\n {0, 0, 0, 0},\n\n {1, 3, 1, 6},\n\n {1, 17, 1, 3},\n\n {0, 0, 1, 1}\n\n };\n\n char* result2 = func0(test2, 5);\n\n assert(strcmp(result2, \"[(3, 6), (17, 3), (None, 1)]\") == 0);\n\n free(result2);\n\n\n\n // Third test case\n\n tuple_t test3[] = {\n\n {1, 1, 1, 2},\n\n {1, 2, 0, 0},\n\n {1, 3, 0, 0},\n\n {1, 24, 1, 3},\n\n {0, 0, 0, 0}\n\n };\n\n char* result3 = func0(test3, 5);\n\n assert(strcmp(result3, \"[(1, 2), (2, None), (3, None), (24, 3)]\") == 0);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\nmov %esi,%ebp\npush %rbx\nmov %rdi,%rbx\nmov $0x400,%edi\nsub $0x20,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x18(%rsp)\nxor %eax,%eax\ncallq 1100 \nmov %rax,%r12\ntest %rax,%rax\nje 1771 \nmov $0x5b,%r11d\nmov %r11w,(%rax)\ntest %ebp,%ebp\njle 175d \nlea -0x1(%rbp),%eax\nmov %rsp,%rbp\nshl $0x4,%rax\nlea 0x10(%rbx,%rax,1),%r13\nmov $0x1,%eax\nmov (%rbx),%r10d\ntest %r10d,%r10d\njne 1798 \nmov 0x8(%rbx),%r9d\ntest %r9d,%r9d\nje 1750 \ntest %eax,%eax\nje 16e7 \nmov $0x400,%edx\nlea 0xac6(%rip),%rsi\nmov %r12,%rdi\ncallq 10b0 <__strcat_chk@plt>\nmov $0x400,%edx\nlea 0xab7(%rip),%rsi\nmov %r12,%rdi\ncallq 10b0 <__strcat_chk@plt>\nmov %r12,%rdi\nmov (%rdi),%edx\nadd $0x4,%rdi\nlea -0x1010101(%rdx),%eax\nnot %edx\nand %edx,%eax\nand $0x80808080,%eax\nje 155d \nmov %eax,%edx\nmov $0x202c,%ecx\nshr $0x10,%edx\ntest $0x8080,%eax\ncmove %edx,%eax\nlea 0x2(%rdi),%rdx\ncmove %rdx,%rdi\nmov %eax,%esi\nadd %al,%sil\nsbb $0x3,%rdi\nmov %cx,(%rdi)\nadd $0x2,%rdi\nmovb $0x0,(%rdi)\nmov 0x8(%rbx),%esi\ntest %esi,%esi\nje 16b8 \nmov 0xc(%rbx),%r8d\nmov $0x14,%edx\nmov $0x1,%esi\nxor %eax,%eax\nmov %rbp,%rdi\nlea 0xa40(%rip),%rcx\ncallq 1110 <__sprintf_chk@plt>\nmov $0x400,%edx\nmov %rbp,%rsi\nmov %r12,%rdi\ncallq 10b0 <__strcat_chk@plt>\nmov $0x400,%edx\nlea 0xa27(%rip),%rsi\nmov %r12,%rdi\nadd $0x10,%rbx\ncallq 10b0 <__strcat_chk@plt>\ncmp %r13,%rbx\nje 175d \nmov (%rbx),%r14d\ntest %r14d,%r14d\nje 16e0 \nmov %r12,%rdi\nmov (%rdi),%edx\nadd $0x4,%rdi\nlea -0x1010101(%rdx),%eax\nnot %edx\nand %edx,%eax\nand $0x80808080,%eax\nje 160b \nmov %eax,%edx\nmov $0x202c,%r8d\nmov %r12,%rcx\nshr $0x10,%edx\ntest $0x8080,%eax\ncmove %edx,%eax\nlea 0x2(%rdi),%rdx\ncmove %rdx,%rdi\nmov $0x2,%edx\nmov %eax,%esi\nadd %al,%sil\nlea 0x9b3(%rip),%rsi\nsbb $0x3,%rdi\nmov %r8w,(%rdi)\nadd $0x2,%rdi\nmovb $0x0,(%rdi)\nsub %rdi,%rcx\nadd $0x400,%rcx\ncallq 10f0 <__memcpy_chk@plt>\ntest %r14d,%r14d\nje 1546 \nnopl 0x0(%rax,%rax,1)\nmov 0x4(%rbx),%r8d\nmov %rbp,%rdi\nlea 0x978(%rip),%rcx\nxor %eax,%eax\nmov $0x14,%edx\nmov $0x1,%esi\ncallq 1110 <__sprintf_chk@plt>\nmov $0x400,%edx\nmov %rbp,%rsi\nmov %r12,%rdi\ncallq 10b0 <__strcat_chk@plt>\njmpq 155a \nnopl 0x0(%rax)\nmov %r12,%rcx\nmov $0x5,%edx\nlea 0x942(%rip),%rsi\nsub %rdi,%rcx\nadd $0x400,%rcx\ncallq 10f0 <__memcpy_chk@plt>\njmpq 15db \nnopl 0x0(%rax,%rax,1)\nmov 0x8(%rbx),%eax\ntest %eax,%eax\nje 1750 \nmov %r12,%rdi\nmov (%rdi),%edx\nadd $0x4,%rdi\nlea -0x1010101(%rdx),%eax\nnot %edx\nand %edx,%eax\nand $0x80808080,%eax\nje 16ea \nmov %eax,%edx\nlea 0x8fa(%rip),%rsi\nshr $0x10,%edx\ntest $0x8080,%eax\ncmove %edx,%eax\nlea 0x2(%rdi),%rdx\ncmove %rdx,%rdi\nmov $0x2,%edx\nmov %eax,%ecx\nadd %al,%cl\nmov $0x202c,%eax\nmov %r12,%rcx\nsbb $0x3,%rdi\nmov %ax,(%rdi)\nadd $0x2,%rdi\nmovb $0x0,(%rdi)\nsub %rdi,%rcx\nadd $0x400,%rcx\ncallq 10f0 <__memcpy_chk@plt>\njmpq 1546 \nadd $0x10,%rbx\ncmp %r13,%rbx\njne 1511 \nmov $0x400,%edx\nlea 0x8df(%rip),%rsi\nmov %r12,%rdi\ncallq 10b0 <__strcat_chk@plt>\nmov 0x18(%rsp),%rax\nxor %fs:0x28,%rax\njne 1822 \nadd $0x20,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopl (%rax)\ntest %eax,%eax\nje 17b8 \nmov $0x400,%edx\nlea 0x85c(%rip),%rsi\nmov %r12,%rdi\ncallq 10b0 <__strcat_chk@plt>\njmpq 1680 \nnopl (%rax)\nmov %r12,%rdi\nmov (%rdi),%edx\nadd $0x4,%rdi\nlea -0x1010101(%rdx),%eax\nnot %edx\nand %edx,%eax\nand $0x80808080,%eax\nje 17bb \nmov %eax,%edx\nmov %r12,%rcx\nshr $0x10,%edx\ntest $0x8080,%eax\ncmove %edx,%eax\nlea 0x2(%rdi),%rdx\ncmove %rdx,%rdi\nmov $0x202c,%edx\nmov %eax,%esi\nadd %al,%sil\nlea 0x809(%rip),%rsi\nsbb $0x3,%rdi\nmov %dx,(%rdi)\nadd $0x2,%rdi\nmov $0x2,%edx\nmovb $0x0,(%rdi)\nsub %rdi,%rcx\nadd $0x400,%rcx\ncallq 10f0 <__memcpy_chk@plt>\njmpq 1680 \ncallq 10d0 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14, rdi\nmov edi, 400h; size\npush r13\npush r12\npush rbp\npush rbx\nmovsxd rbx, esi\nsub rsp, 38h\nmov rax, fs:28h\nmov [rsp+68h+var_40], rax\nxor eax, eax\ncall _malloc\nmov r13, rax\ntest rax, rax\njz loc_164D\nmov r10d, 5Bh ; '['\nmov [rax], r10w\ntest ebx, ebx\njle loc_1639\nshl rbx, 4\nmov eax, 1\nlea r12, unk_2004\nadd rbx, r14\nloc_14A3:\nmov r9d, [r14]\ntest r9d, r9d\njz loc_1678\ntest eax, eax\njz loc_16A8\nmov edx, 400h\nmov rsi, r12\nmov rdi, r13\nmov [rsp+68h+var_68], r12\ncall ___strcat_chk\nlea rbp, asc_200E; \")\"\nloc_14D2:\nlea r15, [rsp+68h+var_58]\nmov r8d, [r14+4]\nmov edx, 14h\nxor eax, eax\nmov esi, 2\nmov rdi, r15\nlea rcx, unk_2006\ncall ___sprintf_chk\nmov edx, 400h\nmov rsi, r15\nmov rdi, r13\ncall ___strcat_chk\nloc_1506:\nmov rdi, r13; s\ncall _strlen\nmov ecx, 202Ch\nadd rax, r13\nmov [rax], cx\nmov byte ptr [rax+2], 0\nmov esi, [r14+8]\ntest esi, esi\njz loc_15F0\nlea r15, [rsp+68h+var_58]\nmov r8d, [r14+0Ch]\nmov edx, 14h\nxor eax, eax\nmov esi, 2\nmov rdi, r15\nlea rcx, unk_2006\ncall ___sprintf_chk\nmov edx, 400h\nmov rsi, r15\nmov rdi, r13\ncall ___strcat_chk\nloc_155D:\nmov edx, 400h\nmov rsi, rbp\nmov rdi, r13\nadd r14, 10h\ncall ___strcat_chk\ncmp r14, rbx\njz loc_1639\nmov r8d, [r14]\ntest r8d, r8d\njz loc_1620\nloc_1586:\nmov rdi, r13; s\nmov [rsp+68h+var_5C], r8d\ncall _strlen\nmov edi, 202Ch\nmov rcx, r13\nmov rsi, [rsp+68h+var_68]\nadd rax, r13\nmov edx, 2\nmov [rax], di\nlea rdi, [rax+2]\nmov byte ptr [rax+2], 0\nsub rcx, rdi\nadd rcx, 400h\ncall ___memcpy_chk\nmov r8d, [rsp+68h+var_5C]\ntest r8d, r8d\njnz loc_14D2\nloc_15CF:\nmov edx, 400h\nlea rsi, aNone; \"None\"\nmov rdi, r13\ncall ___strcat_chk\njmp loc_1506\nloc_15F0:\nlea rdi, [rax+2]\nmov rcx, r13\nmov edx, 5\nsub rcx, rdi\nlea rsi, aNone; \"None\"\nadd rcx, 400h\ncall ___memcpy_chk\njmp loc_155D\nloc_1620:\nmov eax, [r14+8]\ntest eax, eax\njnz loc_1586\nloc_162C:\nadd r14, 10h\ncmp r14, rbx\njnz loc_14A3\nloc_1639:\nmov edx, 400h\nlea rsi, a36173None1+1Bh; \"]\"\nmov rdi, r13\ncall ___strcat_chk\nloc_164D:\nmov rax, [rsp+68h+var_40]\nsub rax, fs:28h\njnz loc_170E\nadd rsp, 38h\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1678:\nmov r8d, [r14+8]\ntest r8d, r8d\njz short loc_162C\ntest eax, eax\njz short loc_16F4\nmov edx, 400h\nmov rsi, r12\nmov rdi, r13\nmov [rsp+68h+var_68], r12\ncall ___strcat_chk\nlea rbp, asc_200E; \")\"\njmp loc_15CF\nloc_16A8:\nmov rdi, r13; s\nlea rbp, asc_200E; \")\"\ncall _strlen\nmov edx, 202Ch\nmov rcx, r13\nadd rax, r13\nmov [rax], dx\nlea rdi, [rax+2]\nmov edx, 2\nmov byte ptr [rax+2], 0\nsub rcx, rdi\nlea rax, unk_2004\nadd rcx, 400h\nmov rsi, rax\nmov [rsp+68h+var_68], rax\ncall ___memcpy_chk\njmp loc_14D2\nloc_16F4:\nlea rax, unk_2004\nxor r8d, r8d\nlea rbp, asc_200E; \")\"\nmov [rsp+68h+var_68], rax\njmp loc_1586\nloc_170E:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(int *a1, int a2)\n{\n int *v2; // r14\n char *v3; // rax\n const char *v4; // r13\n int v5; // eax\n int *v6; // rbx\n char *v7; // rax\n int v8; // r8d\n char *v9; // rax\n char *v11; // rax\n int v12; // [rsp+Ch] [rbp-5Ch]\n _BYTE v13[24]; // [rsp+10h] [rbp-58h] BYREF\n unsigned __int64 v14; // [rsp+28h] [rbp-40h]\n\n v2 = a1;\n v14 = __readfsqword(0x28u);\n v3 = (char *)malloc(0x400uLL);\n v4 = v3;\n if ( v3 )\n {\n *(_WORD *)v3 = 91;\n if ( a2 > 0 )\n {\n v5 = 1;\n v6 = &a1[4 * a2];\n while ( !*v2 )\n {\n if ( v2[2] )\n {\n if ( v5 )\n {\n __strcat_chk(v4, &unk_2004, 1024LL);\n goto LABEL_13;\n }\n v8 = 0;\n while ( 1 )\n {\n v12 = v8;\n v9 = (char *)&v4[strlen(v4)];\n strcpy(v9, \", \");\n __memcpy_chk(v9 + 2, &unk_2004, 2LL, v4 - (v9 + 2) + 1024);\n if ( v12 )\n break;\nLABEL_13:\n __strcat_chk(v4, \"None\", 1024LL);\nLABEL_8:\n v7 = (char *)&v4[strlen(v4)];\n strcpy(v7, \", \");\n if ( v2[2] )\n {\n __sprintf_chk(v13, 2LL, 20LL, &unk_2006, (unsigned int)v2[3]);\n __strcat_chk(v4, v13, 1024LL);\n }\n else\n {\n __memcpy_chk(v7 + 2, \"None\", 5LL, v4 - (v7 + 2) + 1024);\n }\n v2 += 4;\n __strcat_chk(v4, \")\", 1024LL);\n if ( v2 == v6 )\n goto LABEL_17;\n v8 = *v2;\n if ( !*v2 )\n {\n v5 = v2[2];\n if ( !v5 )\n goto LABEL_16;\n }\n }\nLABEL_7:\n __sprintf_chk(v13, 2LL, 20LL, &unk_2006, (unsigned int)v2[1]);\n __strcat_chk(v4, v13, 1024LL);\n goto LABEL_8;\n }\nLABEL_16:\n v2 += 4;\n if ( v2 == v6 )\n goto LABEL_17;\n }\n if ( v5 )\n {\n __strcat_chk(v4, &unk_2004, 1024LL);\n }\n else\n {\n v11 = (char *)&v4[strlen(v4)];\n strcpy(v11, \", \");\n __memcpy_chk(v11 + 2, &unk_2004, 2LL, v4 - (v11 + 2) + 1024);\n }\n goto LABEL_7;\n }\nLABEL_17:\n __strcat_chk(v4, \"]\", 1024LL);\n }\n return v4;\n}", + "ida_strip_asm": "sub_1440:\nendbr64\npush r15\npush r14\nmov r14, rdi\nmov edi, 400h; size\npush r13\npush r12\npush rbp\npush rbx\nmovsxd rbx, esi\nsub rsp, 38h\nmov rax, fs:28h\nmov [rsp+68h+var_40], rax\nxor eax, eax\ncall _malloc\nmov r13, rax\ntest rax, rax\njz loc_164D\nmov r10d, 5Bh ; '['\nmov [rax], r10w\ntest ebx, ebx\njle loc_1639\nshl rbx, 4\nmov eax, 1\nlea r12, unk_2004\nadd rbx, r14\nloc_14A3:\nmov r9d, [r14]\ntest r9d, r9d\njz loc_1678\ntest eax, eax\njz loc_16A8\nmov edx, 400h\nmov rsi, r12\nmov rdi, r13\nmov [rsp+68h+var_68], r12\ncall ___strcat_chk\nlea rbp, asc_200E; \")\"\nloc_14D2:\nlea r15, [rsp+68h+var_58]\nmov r8d, [r14+4]\nmov edx, 14h\nxor eax, eax\nmov esi, 2\nmov rdi, r15\nlea rcx, unk_2006\ncall ___sprintf_chk\nmov edx, 400h\nmov rsi, r15\nmov rdi, r13\ncall ___strcat_chk\nloc_1506:\nmov rdi, r13; s\ncall _strlen\nmov ecx, 202Ch\nadd rax, r13\nmov [rax], cx\nmov byte ptr [rax+2], 0\nmov esi, [r14+8]\ntest esi, esi\njz loc_15F0\nlea r15, [rsp+68h+var_58]\nmov r8d, [r14+0Ch]\nmov edx, 14h\nxor eax, eax\nmov esi, 2\nmov rdi, r15\nlea rcx, unk_2006\ncall ___sprintf_chk\nmov edx, 400h\nmov rsi, r15\nmov rdi, r13\ncall ___strcat_chk\nloc_155D:\nmov edx, 400h\nmov rsi, rbp\nmov rdi, r13\nadd r14, 10h\ncall ___strcat_chk\ncmp r14, rbx\njz loc_1639\nmov r8d, [r14]\ntest r8d, r8d\njz loc_1620\nloc_1586:\nmov rdi, r13; s\nmov [rsp+68h+var_5C], r8d\ncall _strlen\nmov edi, 202Ch\nmov rcx, r13\nmov rsi, [rsp+68h+var_68]\nadd rax, r13\nmov edx, 2\nmov [rax], di\nlea rdi, [rax+2]\nmov byte ptr [rax+2], 0\nsub rcx, rdi\nadd rcx, 400h\ncall ___memcpy_chk\nmov r8d, [rsp+68h+var_5C]\ntest r8d, r8d\njnz loc_14D2\nloc_15CF:\nmov edx, 400h\nlea rsi, aNone; \"None\"\nmov rdi, r13\ncall ___strcat_chk\njmp loc_1506\nloc_15F0:\nlea rdi, [rax+2]\nmov rcx, r13\nmov edx, 5\nsub rcx, rdi\nlea rsi, aNone; \"None\"\nadd rcx, 400h\ncall ___memcpy_chk\njmp loc_155D\nloc_1620:\nmov eax, [r14+8]\ntest eax, eax\njnz loc_1586\nloc_162C:\nadd r14, 10h\ncmp r14, rbx\njnz loc_14A3\nloc_1639:\nmov edx, 400h\nlea rsi, a36173None1+1Bh; \"]\"\nmov rdi, r13\ncall ___strcat_chk\nloc_164D:\nmov rax, [rsp+68h+var_40]\nsub rax, fs:28h\njnz loc_170E\nadd rsp, 38h\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1678:\nmov r8d, [r14+8]\ntest r8d, r8d\njz short loc_162C\ntest eax, eax\njz short loc_16F4\nmov edx, 400h\nmov rsi, r12\nmov rdi, r13\nmov [rsp+68h+var_68], r12\ncall ___strcat_chk\nlea rbp, asc_200E; \")\"\njmp loc_15CF\nloc_16A8:\nmov rdi, r13; s\nlea rbp, asc_200E; \")\"\ncall _strlen\nmov edx, 202Ch\nmov rcx, r13\nadd rax, r13\nmov [rax], dx\nlea rdi, [rax+2]\nmov edx, 2\nmov byte ptr [rax+2], 0\nsub rcx, rdi\nlea rax, unk_2004\nadd rcx, 400h\nmov rsi, rax\nmov [rsp+68h+var_68], rax\ncall ___memcpy_chk\njmp loc_14D2\nloc_16F4:\nlea rax, unk_2004\nxor r8d, r8d\nlea rbp, asc_200E; \")\"\nmov [rsp+68h+var_68], rax\njmp loc_1586\nloc_170E:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_1440(int *a1, int a2)\n{\n int *v2; // r14\n char *v3; // rax\n const char *v4; // r13\n int v5; // eax\n int *v6; // rbx\n char *v7; // rax\n int v8; // r8d\n char *v9; // rax\n char *v11; // rax\n int v12; // [rsp+Ch] [rbp-5Ch]\n _BYTE v13[24]; // [rsp+10h] [rbp-58h] BYREF\n unsigned __int64 v14; // [rsp+28h] [rbp-40h]\n\n v2 = a1;\n v14 = __readfsqword(0x28u);\n v3 = (char *)malloc(0x400uLL);\n v4 = v3;\n if ( v3 )\n {\n *(_WORD *)v3 = 91;\n if ( a2 > 0 )\n {\n v5 = 1;\n v6 = &a1[4 * a2];\n while ( !*v2 )\n {\n if ( v2[2] )\n {\n if ( v5 )\n {\n __strcat_chk(v4, &unk_2004, 1024LL);\n goto LABEL_13;\n }\n v8 = 0;\n while ( 1 )\n {\n v12 = v8;\n v9 = (char *)&v4[strlen(v4)];\n strcpy(v9, \", \");\n __memcpy_chk(v9 + 2, &unk_2004, 2LL, v4 - (v9 + 2) + 1024);\n if ( v12 )\n break;\nLABEL_13:\n __strcat_chk(v4, \"None\", 1024LL);\nLABEL_8:\n v7 = (char *)&v4[strlen(v4)];\n strcpy(v7, \", \");\n if ( v2[2] )\n {\n __sprintf_chk(v13, 2LL, 20LL, &unk_2006, (unsigned int)v2[3]);\n __strcat_chk(v4, v13, 1024LL);\n }\n else\n {\n __memcpy_chk(v7 + 2, \"None\", 5LL, v4 - (v7 + 2) + 1024);\n }\n v2 += 4;\n __strcat_chk(v4, \")\", 1024LL);\n if ( v2 == v6 )\n goto LABEL_17;\n v8 = *v2;\n if ( !*v2 )\n {\n v5 = v2[2];\n if ( !v5 )\n goto LABEL_16;\n }\n }\nLABEL_7:\n __sprintf_chk(v13, 2LL, 20LL, &unk_2006, (unsigned int)v2[1]);\n __strcat_chk(v4, v13, 1024LL);\n goto LABEL_8;\n }\nLABEL_16:\n v2 += 4;\n if ( v2 == v6 )\n goto LABEL_17;\n }\n if ( v5 )\n {\n __strcat_chk(v4, &unk_2004, 1024LL);\n }\n else\n {\n v11 = (char *)&v4[strlen(v4)];\n strcpy(v11, \", \");\n __memcpy_chk(v11 + 2, &unk_2004, 2LL, v4 - (v11 + 2) + 1024);\n }\n goto LABEL_7;\n }\nLABEL_17:\n __strcat_chk(v4, \"]\", 1024LL);\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1440(int *a1, int a2) {\n int *v2;\n char *v3;\n const char *v4;\n int v5;\n int *v6;\n char *v7;\n int v8;\n char *v9;\n char *v11;\n int v12;\n uint8_t v13[24];\n unsigned long long v14;\n v2 = a1;\n v14 = __readfsqword(40u);\n v3 = (char *)malloc(1024uLL);\n v4 = v3;\n if (v3) {\n *(unsigned short *)v3 = 91;\n if (a2 > 0) {\n v5 = 1;\n v6 = &a1[4 * a2];\n while (!*v2) {\n if (v2[2]) {\n if (v5) {\n __strcat_chk(v4, &unk_2004, 1024LL);\n goto LABEL_13;\n }\n v8 = 0;\n while (1) {\n v12 = v8;\n v9 = (char *)&v4[strlen(v4)];\n strcpy(v9, \", \");\n __memcpy_chk(v9 + 2, &unk_2004, 2LL, v4 - (v9 + 2) + 1024);\n if (v12) break;\n LABEL_13:\n __strcat_chk(v4, \"None\", 1024LL);\n LABEL_8:\n v7 = (char *)&v4[strlen(v4)];\n strcpy(v7, \", \");\n if (v2[2]) {\n __sprintf_chk(v13, 2LL, 20LL, &unk_2006, (unsigned int)v2[3]);\n __strcat_chk(v4, v13, 1024LL);\n } else {\n __memcpy_chk(v7 + 2, \"None\", 5LL, v4 - (v7 + 2) + 1024);\n }\n v2 += 4;\n __strcat_chk(v4, \")\", 1024LL);\n if (v2 == v6) goto LABEL_17;\n v8 = *v2;\n if (!*v2) {\n v5 = v2[2];\n if (!v5) goto LABEL_16;\n }\n }\n LABEL_7:\n __sprintf_chk(v13, 2LL, 20LL, &unk_2006, (unsigned int)v2[1]);\n __strcat_chk(v4, v13, 1024LL);\n goto LABEL_8;\n }\n LABEL_16:\n v2 += 4;\n if (v2 == v6) goto LABEL_17;\n }\n if (v5) {\n __strcat_chk(v4, &unk_2004, 1024LL);\n } else {\n v11 = (char *)&v4[strlen(v4)];\n strcpy(v11, \", \");\n __memcpy_chk(v11 + 2, &unk_2004, 2LL, v4 - (v11 + 2) + 1024);\n }\n goto LABEL_7;\n }\n LABEL_17:\n __strcat_chk(v4, \"]\", 1024LL);\n }\n return v4;\n}", + "ida_pseudo_norm": "const char *func0(int *a1, int a2) {\n int *v2;\n char *v3;\n const char *v4;\n int v5;\n int *v6;\n char *v7;\n int v8;\n char *v9;\n char *v11;\n int v12;\n uint8_t v13[24];\n unsigned long long v14;\n v2 = a1;\n v14 = __readfsqword(40u);\n v3 = (char *)malloc(1024uLL);\n v4 = v3;\n if (v3) {\n *(unsigned short *)v3 = 91;\n if (a2 > 0) {\n v5 = 1;\n v6 = &a1[4 * a2];\n while (!*v2) {\n if (v2[2]) {\n if (v5) {\n __strcat_chk(v4, &unk_2004, 1024LL);\n goto LABEL_13;\n }\n v8 = 0;\n while (1) {\n v12 = v8;\n v9 = (char *)&v4[strlen(v4)];\n strcpy(v9, \", \");\n __memcpy_chk(v9 + 2, &unk_2004, 2LL, v4 - (v9 + 2) + 1024);\n if (v12) break;\n LABEL_13:\n __strcat_chk(v4, \"None\", 1024LL);\n LABEL_8:\n v7 = (char *)&v4[strlen(v4)];\n strcpy(v7, \", \");\n if (v2[2]) {\n __sprintf_chk(v13, 2LL, 20LL, &unk_2006, (unsigned int)v2[3]);\n __strcat_chk(v4, v13, 1024LL);\n } else {\n __memcpy_chk(v7 + 2, \"None\", 5LL, v4 - (v7 + 2) + 1024);\n }\n v2 += 4;\n __strcat_chk(v4, \")\", 1024LL);\n if (v2 == v6) goto LABEL_17;\n v8 = *v2;\n if (!*v2) {\n v5 = v2[2];\n if (!v5) goto LABEL_16;\n }\n }\n LABEL_7:\n __sprintf_chk(v13, 2LL, 20LL, &unk_2006, (unsigned int)v2[1]);\n __strcat_chk(v4, v13, 1024LL);\n goto LABEL_8;\n }\n LABEL_16:\n v2 += 4;\n if (v2 == v6) goto LABEL_17;\n }\n if (v5) {\n __strcat_chk(v4, &unk_2004, 1024LL);\n } else {\n v11 = (char *)&v4[strlen(v4)];\n strcpy(v11, \", \");\n __memcpy_chk(v11 + 2, &unk_2004, 2LL, v4 - (v11 + 2) + 1024);\n }\n goto LABEL_7;\n }\n LABEL_17:\n __strcat_chk(v4, \"]\", 1024LL);\n }\n return v4;\n}" + }, + { + "index": 920, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int has_first;\n\n int first;\n\n int has_second;\n\n int second;\n\n} tuple_t;\n\n\n\n", + "func": "char* func0(tuple_t* test_list, int size) {\n char* res = malloc(1024);\n if (!res) return NULL;\n strcpy(res, \"[\");\n int first = 1;\n for (int i = 0; i < size; i++) {\n int all_null = 1;\n if (test_list[i].has_first) all_null = 0;\n if (test_list[i].has_second) all_null = 0;\n if (!all_null) {\n if (!first) strcat(res, \", \");\n first = 0;\n strcat(res, \"(\");\n if (test_list[i].has_first) {\n char num[20];\n sprintf(num, \"%d\", test_list[i].first);\n strcat(res, num);\n } else {\n strcat(res, \"None\");\n }\n strcat(res, \", \");\n if (test_list[i].has_second) {\n char num[20];\n sprintf(num, \"%d\", test_list[i].second);\n strcat(res, num);\n } else {\n strcat(res, \"None\");\n }\n strcat(res, \")\");\n }\n }\n strcat(res, \"]\");\n return res;\n}", + "test": "int main() {\n\n // First test case\n\n tuple_t test1[] = {\n\n {0, 0, 1, 2},\n\n {0, 0, 0, 0},\n\n {1, 3, 1, 4},\n\n {1, 12, 1, 3},\n\n {0, 0, 0, 0}\n\n };\n\n char* result1 = func0(test1, 5);\n\n assert(strcmp(result1, \"[(None, 2), (3, 4), (12, 3)]\") == 0);\n\n free(result1);\n\n\n\n // Second test case\n\n tuple_t test2[] = {\n\n {0, 0, 0, 0},\n\n {0, 0, 0, 0},\n\n {1, 3, 1, 6},\n\n {1, 17, 1, 3},\n\n {0, 0, 1, 1}\n\n };\n\n char* result2 = func0(test2, 5);\n\n assert(strcmp(result2, \"[(3, 6), (17, 3), (None, 1)]\") == 0);\n\n free(result2);\n\n\n\n // Third test case\n\n tuple_t test3[] = {\n\n {1, 1, 1, 2},\n\n {1, 2, 0, 0},\n\n {1, 3, 0, 0},\n\n {1, 24, 1, 3},\n\n {0, 0, 0, 0}\n\n };\n\n char* result3 = func0(test3, 5);\n\n assert(strcmp(result3, \"[(1, 2), (2, None), (3, None), (24, 3)]\") == 0);\n\n free(result3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\nmov %esi,%ebp\npush %rbx\nmov %rdi,%rbx\nmov $0x400,%edi\nsub $0x20,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x18(%rsp)\nxor %eax,%eax\ncallq 1100 \nmov %rax,%r12\ntest %rax,%rax\nje 16d1 \nmov $0x5b,%r11d\nmov %r11w,(%rax)\ntest %ebp,%ebp\njle 16bd \nlea -0x1(%rbp),%eax\nmov %rsp,%rbp\nshl $0x4,%rax\nlea 0x10(%rbx,%rax,1),%r13\nmov $0x1,%eax\nmov (%rbx),%r10d\ntest %r10d,%r10d\njne 16f8 \nmov 0x8(%rbx),%r9d\ntest %r9d,%r9d\nje 16b0 \ntest %eax,%eax\nje 1647 \nmov $0x400,%edx\nlea 0xb66(%rip),%rsi\nmov %r12,%rdi\ncallq 10b0 <__strcat_chk@plt>\nmov $0x400,%edx\nlea 0xb57(%rip),%rsi\nmov %r12,%rdi\ncallq 10b0 <__strcat_chk@plt>\nmov %r12,%rdi\nmov (%rdi),%edx\nadd $0x4,%rdi\nlea -0x1010101(%rdx),%eax\nnot %edx\nand %edx,%eax\nand $0x80808080,%eax\nje 14bd \nmov %eax,%edx\nmov $0x202c,%ecx\nshr $0x10,%edx\ntest $0x8080,%eax\ncmove %edx,%eax\nlea 0x2(%rdi),%rdx\ncmove %rdx,%rdi\nmov %eax,%esi\nadd %al,%sil\nsbb $0x3,%rdi\nmov %cx,(%rdi)\nadd $0x2,%rdi\nmovb $0x0,(%rdi)\nmov 0x8(%rbx),%esi\ntest %esi,%esi\nje 1618 \nmov 0xc(%rbx),%r8d\nmov $0x14,%edx\nmov $0x1,%esi\nxor %eax,%eax\nmov %rbp,%rdi\nlea 0xae0(%rip),%rcx\ncallq 1110 <__sprintf_chk@plt>\nmov $0x400,%edx\nmov %rbp,%rsi\nmov %r12,%rdi\ncallq 10b0 <__strcat_chk@plt>\nmov $0x400,%edx\nlea 0xac7(%rip),%rsi\nmov %r12,%rdi\nadd $0x10,%rbx\ncallq 10b0 <__strcat_chk@plt>\ncmp %r13,%rbx\nje 16bd \nmov (%rbx),%r14d\ntest %r14d,%r14d\nje 1640 \nmov %r12,%rdi\nmov (%rdi),%edx\nadd $0x4,%rdi\nlea -0x1010101(%rdx),%eax\nnot %edx\nand %edx,%eax\nand $0x80808080,%eax\nje 156b \nmov %eax,%edx\nmov $0x202c,%r8d\nmov %r12,%rcx\nshr $0x10,%edx\ntest $0x8080,%eax\ncmove %edx,%eax\nlea 0x2(%rdi),%rdx\ncmove %rdx,%rdi\nmov $0x2,%edx\nmov %eax,%esi\nadd %al,%sil\nlea 0xa53(%rip),%rsi\nsbb $0x3,%rdi\nmov %r8w,(%rdi)\nadd $0x2,%rdi\nmovb $0x0,(%rdi)\nsub %rdi,%rcx\nadd $0x400,%rcx\ncallq 10f0 <__memcpy_chk@plt>\ntest %r14d,%r14d\nje 14a6 \nnopl 0x0(%rax,%rax,1)\nmov 0x4(%rbx),%r8d\nmov %rbp,%rdi\nlea 0xa18(%rip),%rcx\nxor %eax,%eax\nmov $0x14,%edx\nmov $0x1,%esi\ncallq 1110 <__sprintf_chk@plt>\nmov $0x400,%edx\nmov %rbp,%rsi\nmov %r12,%rdi\ncallq 10b0 <__strcat_chk@plt>\njmpq 14ba \nnopl 0x0(%rax)\nmov %r12,%rcx\nmov $0x5,%edx\nlea 0x9e2(%rip),%rsi\nsub %rdi,%rcx\nadd $0x400,%rcx\ncallq 10f0 <__memcpy_chk@plt>\njmpq 153b \nnopl 0x0(%rax,%rax,1)\nmov 0x8(%rbx),%eax\ntest %eax,%eax\nje 16b0 \nmov %r12,%rdi\nmov (%rdi),%edx\nadd $0x4,%rdi\nlea -0x1010101(%rdx),%eax\nnot %edx\nand %edx,%eax\nand $0x80808080,%eax\nje 164a \nmov %eax,%edx\nlea 0x99a(%rip),%rsi\nshr $0x10,%edx\ntest $0x8080,%eax\ncmove %edx,%eax\nlea 0x2(%rdi),%rdx\ncmove %rdx,%rdi\nmov $0x2,%edx\nmov %eax,%ecx\nadd %al,%cl\nmov $0x202c,%eax\nmov %r12,%rcx\nsbb $0x3,%rdi\nmov %ax,(%rdi)\nadd $0x2,%rdi\nmovb $0x0,(%rdi)\nsub %rdi,%rcx\nadd $0x400,%rcx\ncallq 10f0 <__memcpy_chk@plt>\njmpq 14a6 \nadd $0x10,%rbx\ncmp %r13,%rbx\njne 1471 \nmov $0x400,%edx\nlea 0x97f(%rip),%rsi\nmov %r12,%rdi\ncallq 10b0 <__strcat_chk@plt>\nmov 0x18(%rsp),%rax\nxor %fs:0x28,%rax\njne 1782 \nadd $0x20,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nnopl (%rax)\ntest %eax,%eax\nje 1718 \nmov $0x400,%edx\nlea 0x8fc(%rip),%rsi\nmov %r12,%rdi\ncallq 10b0 <__strcat_chk@plt>\njmpq 15e0 \nnopl (%rax)\nmov %r12,%rdi\nmov (%rdi),%edx\nadd $0x4,%rdi\nlea -0x1010101(%rdx),%eax\nnot %edx\nand %edx,%eax\nand $0x80808080,%eax\nje 171b \nmov %eax,%edx\nmov %r12,%rcx\nshr $0x10,%edx\ntest $0x8080,%eax\ncmove %edx,%eax\nlea 0x2(%rdi),%rdx\ncmove %rdx,%rdi\nmov $0x202c,%edx\nmov %eax,%esi\nadd %al,%sil\nlea 0x8a9(%rip),%rsi\nsbb $0x3,%rdi\nmov %dx,(%rdi)\nadd $0x2,%rdi\nmov $0x2,%edx\nmovb $0x0,(%rdi)\nsub %rdi,%rcx\nadd $0x400,%rcx\ncallq 10f0 <__memcpy_chk@plt>\njmpq 15e0 \ncallq 10d0 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14, rdi\nmov edi, 400h; size\npush r13\npush r12\npush rbp\npush rbx\nmovsxd rbx, esi\nsub rsp, 38h\nmov rax, fs:28h\nmov [rsp+68h+var_40], rax\nxor eax, eax\ncall _malloc\nmov r13, rax\ntest rax, rax\njz loc_164D\nmov r10d, 5Bh ; '['\nmov [rax], r10w\ntest ebx, ebx\njle loc_1639\nshl rbx, 4\nmov eax, 1\nlea r12, unk_2004\nadd rbx, r14\nloc_14A3:\nmov r9d, [r14]\ntest r9d, r9d\njz loc_1678\ntest eax, eax\njz loc_16A8\nmov edx, 400h\nmov rsi, r12\nmov rdi, r13\nmov [rsp+68h+var_68], r12\ncall ___strcat_chk\nlea rbp, asc_200E; \")\"\nloc_14D2:\nlea r15, [rsp+68h+var_58]\nmov r8d, [r14+4]\nmov edx, 14h\nxor eax, eax\nmov esi, 2\nmov rdi, r15\nlea rcx, unk_2006\ncall ___sprintf_chk\nmov edx, 400h\nmov rsi, r15\nmov rdi, r13\ncall ___strcat_chk\nloc_1506:\nmov rdi, r13; s\ncall _strlen\nmov ecx, 202Ch\nadd rax, r13\nmov [rax], cx\nmov byte ptr [rax+2], 0\nmov esi, [r14+8]\ntest esi, esi\njz loc_15F0\nlea r15, [rsp+68h+var_58]\nmov r8d, [r14+0Ch]\nmov edx, 14h\nxor eax, eax\nmov esi, 2\nmov rdi, r15\nlea rcx, unk_2006\ncall ___sprintf_chk\nmov edx, 400h\nmov rsi, r15\nmov rdi, r13\ncall ___strcat_chk\nloc_155D:\nmov edx, 400h\nmov rsi, rbp\nmov rdi, r13\nadd r14, 10h\ncall ___strcat_chk\ncmp r14, rbx\njz loc_1639\nmov r8d, [r14]\ntest r8d, r8d\njz loc_1620\nloc_1586:\nmov rdi, r13; s\nmov [rsp+68h+var_5C], r8d\ncall _strlen\nmov edi, 202Ch\nmov rcx, r13\nmov rsi, [rsp+68h+var_68]\nadd rax, r13\nmov edx, 2\nmov [rax], di\nlea rdi, [rax+2]\nmov byte ptr [rax+2], 0\nsub rcx, rdi\nadd rcx, 400h\ncall ___memcpy_chk\nmov r8d, [rsp+68h+var_5C]\ntest r8d, r8d\njnz loc_14D2\nloc_15CF:\nmov edx, 400h\nlea rsi, aNone; \"None\"\nmov rdi, r13\ncall ___strcat_chk\njmp loc_1506\nloc_15F0:\nlea rdi, [rax+2]\nmov rcx, r13\nmov edx, 5\nsub rcx, rdi\nlea rsi, aNone; \"None\"\nadd rcx, 400h\ncall ___memcpy_chk\njmp loc_155D\nloc_1620:\nmov eax, [r14+8]\ntest eax, eax\njnz loc_1586\nloc_162C:\nadd r14, 10h\ncmp r14, rbx\njnz loc_14A3\nloc_1639:\nmov edx, 400h\nlea rsi, a36173None1+1Bh; \"]\"\nmov rdi, r13\ncall ___strcat_chk\nloc_164D:\nmov rax, [rsp+68h+var_40]\nsub rax, fs:28h\njnz loc_170E\nadd rsp, 38h\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1678:\nmov r8d, [r14+8]\ntest r8d, r8d\njz short loc_162C\ntest eax, eax\njz short loc_16F4\nmov edx, 400h\nmov rsi, r12\nmov rdi, r13\nmov [rsp+68h+var_68], r12\ncall ___strcat_chk\nlea rbp, asc_200E; \")\"\njmp loc_15CF\nloc_16A8:\nmov rdi, r13; s\nlea rbp, asc_200E; \")\"\ncall _strlen\nmov edx, 202Ch\nmov rcx, r13\nadd rax, r13\nmov [rax], dx\nlea rdi, [rax+2]\nmov edx, 2\nmov byte ptr [rax+2], 0\nsub rcx, rdi\nlea rax, unk_2004\nadd rcx, 400h\nmov rsi, rax\nmov [rsp+68h+var_68], rax\ncall ___memcpy_chk\njmp loc_14D2\nloc_16F4:\nlea rax, unk_2004\nxor r8d, r8d\nlea rbp, asc_200E; \")\"\nmov [rsp+68h+var_68], rax\njmp loc_1586\nloc_170E:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(int *a1, int a2)\n{\n int *v2; // r14\n char *v3; // rax\n const char *v4; // r13\n int v5; // eax\n int *v6; // rbx\n char *v7; // rax\n int v8; // r8d\n char *v9; // rax\n char *v11; // rax\n int v12; // [rsp+Ch] [rbp-5Ch]\n _BYTE v13[24]; // [rsp+10h] [rbp-58h] BYREF\n unsigned __int64 v14; // [rsp+28h] [rbp-40h]\n\n v2 = a1;\n v14 = __readfsqword(0x28u);\n v3 = (char *)malloc(0x400uLL);\n v4 = v3;\n if ( v3 )\n {\n *(_WORD *)v3 = 91;\n if ( a2 > 0 )\n {\n v5 = 1;\n v6 = &a1[4 * a2];\n while ( !*v2 )\n {\n if ( v2[2] )\n {\n if ( v5 )\n {\n __strcat_chk(v4, &unk_2004, 1024LL);\n goto LABEL_13;\n }\n v8 = 0;\n while ( 1 )\n {\n v12 = v8;\n v9 = (char *)&v4[strlen(v4)];\n strcpy(v9, \", \");\n __memcpy_chk(v9 + 2, &unk_2004, 2LL, v4 - (v9 + 2) + 1024);\n if ( v12 )\n break;\nLABEL_13:\n __strcat_chk(v4, \"None\", 1024LL);\nLABEL_8:\n v7 = (char *)&v4[strlen(v4)];\n strcpy(v7, \", \");\n if ( v2[2] )\n {\n __sprintf_chk(v13, 2LL, 20LL, &unk_2006, (unsigned int)v2[3]);\n __strcat_chk(v4, v13, 1024LL);\n }\n else\n {\n __memcpy_chk(v7 + 2, \"None\", 5LL, v4 - (v7 + 2) + 1024);\n }\n v2 += 4;\n __strcat_chk(v4, \")\", 1024LL);\n if ( v2 == v6 )\n goto LABEL_17;\n v8 = *v2;\n if ( !*v2 )\n {\n v5 = v2[2];\n if ( !v5 )\n goto LABEL_16;\n }\n }\nLABEL_7:\n __sprintf_chk(v13, 2LL, 20LL, &unk_2006, (unsigned int)v2[1]);\n __strcat_chk(v4, v13, 1024LL);\n goto LABEL_8;\n }\nLABEL_16:\n v2 += 4;\n if ( v2 == v6 )\n goto LABEL_17;\n }\n if ( v5 )\n {\n __strcat_chk(v4, &unk_2004, 1024LL);\n }\n else\n {\n v11 = (char *)&v4[strlen(v4)];\n strcpy(v11, \", \");\n __memcpy_chk(v11 + 2, &unk_2004, 2LL, v4 - (v11 + 2) + 1024);\n }\n goto LABEL_7;\n }\nLABEL_17:\n __strcat_chk(v4, \"]\", 1024LL);\n }\n return v4;\n}", + "ida_strip_asm": "sub_1440:\nendbr64\npush r15\npush r14\nmov r14, rdi\nmov edi, 400h; size\npush r13\npush r12\npush rbp\npush rbx\nmovsxd rbx, esi\nsub rsp, 38h\nmov rax, fs:28h\nmov [rsp+68h+var_40], rax\nxor eax, eax\ncall _malloc\nmov r13, rax\ntest rax, rax\njz loc_164D\nmov r10d, 5Bh ; '['\nmov [rax], r10w\ntest ebx, ebx\njle loc_1639\nshl rbx, 4\nmov eax, 1\nlea r12, unk_2004\nadd rbx, r14\nloc_14A3:\nmov r9d, [r14]\ntest r9d, r9d\njz loc_1678\ntest eax, eax\njz loc_16A8\nmov edx, 400h\nmov rsi, r12\nmov rdi, r13\nmov [rsp+68h+var_68], r12\ncall ___strcat_chk\nlea rbp, asc_200E; \")\"\nloc_14D2:\nlea r15, [rsp+68h+var_58]\nmov r8d, [r14+4]\nmov edx, 14h\nxor eax, eax\nmov esi, 2\nmov rdi, r15\nlea rcx, unk_2006\ncall ___sprintf_chk\nmov edx, 400h\nmov rsi, r15\nmov rdi, r13\ncall ___strcat_chk\nloc_1506:\nmov rdi, r13; s\ncall _strlen\nmov ecx, 202Ch\nadd rax, r13\nmov [rax], cx\nmov byte ptr [rax+2], 0\nmov esi, [r14+8]\ntest esi, esi\njz loc_15F0\nlea r15, [rsp+68h+var_58]\nmov r8d, [r14+0Ch]\nmov edx, 14h\nxor eax, eax\nmov esi, 2\nmov rdi, r15\nlea rcx, unk_2006\ncall ___sprintf_chk\nmov edx, 400h\nmov rsi, r15\nmov rdi, r13\ncall ___strcat_chk\nloc_155D:\nmov edx, 400h\nmov rsi, rbp\nmov rdi, r13\nadd r14, 10h\ncall ___strcat_chk\ncmp r14, rbx\njz loc_1639\nmov r8d, [r14]\ntest r8d, r8d\njz loc_1620\nloc_1586:\nmov rdi, r13; s\nmov [rsp+68h+var_5C], r8d\ncall _strlen\nmov edi, 202Ch\nmov rcx, r13\nmov rsi, [rsp+68h+var_68]\nadd rax, r13\nmov edx, 2\nmov [rax], di\nlea rdi, [rax+2]\nmov byte ptr [rax+2], 0\nsub rcx, rdi\nadd rcx, 400h\ncall ___memcpy_chk\nmov r8d, [rsp+68h+var_5C]\ntest r8d, r8d\njnz loc_14D2\nloc_15CF:\nmov edx, 400h\nlea rsi, aNone; \"None\"\nmov rdi, r13\ncall ___strcat_chk\njmp loc_1506\nloc_15F0:\nlea rdi, [rax+2]\nmov rcx, r13\nmov edx, 5\nsub rcx, rdi\nlea rsi, aNone; \"None\"\nadd rcx, 400h\ncall ___memcpy_chk\njmp loc_155D\nloc_1620:\nmov eax, [r14+8]\ntest eax, eax\njnz loc_1586\nloc_162C:\nadd r14, 10h\ncmp r14, rbx\njnz loc_14A3\nloc_1639:\nmov edx, 400h\nlea rsi, a36173None1+1Bh; \"]\"\nmov rdi, r13\ncall ___strcat_chk\nloc_164D:\nmov rax, [rsp+68h+var_40]\nsub rax, fs:28h\njnz loc_170E\nadd rsp, 38h\nmov rax, r13\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1678:\nmov r8d, [r14+8]\ntest r8d, r8d\njz short loc_162C\ntest eax, eax\njz short loc_16F4\nmov edx, 400h\nmov rsi, r12\nmov rdi, r13\nmov [rsp+68h+var_68], r12\ncall ___strcat_chk\nlea rbp, asc_200E; \")\"\njmp loc_15CF\nloc_16A8:\nmov rdi, r13; s\nlea rbp, asc_200E; \")\"\ncall _strlen\nmov edx, 202Ch\nmov rcx, r13\nadd rax, r13\nmov [rax], dx\nlea rdi, [rax+2]\nmov edx, 2\nmov byte ptr [rax+2], 0\nsub rcx, rdi\nlea rax, unk_2004\nadd rcx, 400h\nmov rsi, rax\nmov [rsp+68h+var_68], rax\ncall ___memcpy_chk\njmp loc_14D2\nloc_16F4:\nlea rax, unk_2004\nxor r8d, r8d\nlea rbp, asc_200E; \")\"\nmov [rsp+68h+var_68], rax\njmp loc_1586\nloc_170E:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_1440(int *a1, int a2)\n{\n int *v2; // r14\n char *v3; // rax\n const char *v4; // r13\n int v5; // eax\n int *v6; // rbx\n char *v7; // rax\n int v8; // r8d\n char *v9; // rax\n char *v11; // rax\n int v12; // [rsp+Ch] [rbp-5Ch]\n _BYTE v13[24]; // [rsp+10h] [rbp-58h] BYREF\n unsigned __int64 v14; // [rsp+28h] [rbp-40h]\n\n v2 = a1;\n v14 = __readfsqword(0x28u);\n v3 = (char *)malloc(0x400uLL);\n v4 = v3;\n if ( v3 )\n {\n *(_WORD *)v3 = 91;\n if ( a2 > 0 )\n {\n v5 = 1;\n v6 = &a1[4 * a2];\n while ( !*v2 )\n {\n if ( v2[2] )\n {\n if ( v5 )\n {\n __strcat_chk(v4, &unk_2004, 1024LL);\n goto LABEL_13;\n }\n v8 = 0;\n while ( 1 )\n {\n v12 = v8;\n v9 = (char *)&v4[strlen(v4)];\n strcpy(v9, \", \");\n __memcpy_chk(v9 + 2, &unk_2004, 2LL, v4 - (v9 + 2) + 1024);\n if ( v12 )\n break;\nLABEL_13:\n __strcat_chk(v4, \"None\", 1024LL);\nLABEL_8:\n v7 = (char *)&v4[strlen(v4)];\n strcpy(v7, \", \");\n if ( v2[2] )\n {\n __sprintf_chk(v13, 2LL, 20LL, &unk_2006, (unsigned int)v2[3]);\n __strcat_chk(v4, v13, 1024LL);\n }\n else\n {\n __memcpy_chk(v7 + 2, \"None\", 5LL, v4 - (v7 + 2) + 1024);\n }\n v2 += 4;\n __strcat_chk(v4, \")\", 1024LL);\n if ( v2 == v6 )\n goto LABEL_17;\n v8 = *v2;\n if ( !*v2 )\n {\n v5 = v2[2];\n if ( !v5 )\n goto LABEL_16;\n }\n }\nLABEL_7:\n __sprintf_chk(v13, 2LL, 20LL, &unk_2006, (unsigned int)v2[1]);\n __strcat_chk(v4, v13, 1024LL);\n goto LABEL_8;\n }\nLABEL_16:\n v2 += 4;\n if ( v2 == v6 )\n goto LABEL_17;\n }\n if ( v5 )\n {\n __strcat_chk(v4, &unk_2004, 1024LL);\n }\n else\n {\n v11 = (char *)&v4[strlen(v4)];\n strcpy(v11, \", \");\n __memcpy_chk(v11 + 2, &unk_2004, 2LL, v4 - (v11 + 2) + 1024);\n }\n goto LABEL_7;\n }\nLABEL_17:\n __strcat_chk(v4, \"]\", 1024LL);\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1440(int *a1, int a2) {\n int *v2;\n char *v3;\n const char *v4;\n int v5;\n int *v6;\n char *v7;\n int v8;\n char *v9;\n char *v11;\n int v12;\n uint8_t v13[24];\n unsigned long long v14;\n v2 = a1;\n v14 = __readfsqword(40u);\n v3 = (char *)malloc(1024uLL);\n v4 = v3;\n if (v3) {\n *(unsigned short *)v3 = 91;\n if (a2 > 0) {\n v5 = 1;\n v6 = &a1[4 * a2];\n while (!*v2) {\n if (v2[2]) {\n if (v5) {\n __strcat_chk(v4, &unk_2004, 1024LL);\n goto LABEL_13;\n }\n v8 = 0;\n while (1) {\n v12 = v8;\n v9 = (char *)&v4[strlen(v4)];\n strcpy(v9, \", \");\n __memcpy_chk(v9 + 2, &unk_2004, 2LL, v4 - (v9 + 2) + 1024);\n if (v12) break;\n LABEL_13:\n __strcat_chk(v4, \"None\", 1024LL);\n LABEL_8:\n v7 = (char *)&v4[strlen(v4)];\n strcpy(v7, \", \");\n if (v2[2]) {\n __sprintf_chk(v13, 2LL, 20LL, &unk_2006, (unsigned int)v2[3]);\n __strcat_chk(v4, v13, 1024LL);\n } else {\n __memcpy_chk(v7 + 2, \"None\", 5LL, v4 - (v7 + 2) + 1024);\n }\n v2 += 4;\n __strcat_chk(v4, \")\", 1024LL);\n if (v2 == v6) goto LABEL_17;\n v8 = *v2;\n if (!*v2) {\n v5 = v2[2];\n if (!v5) goto LABEL_16;\n }\n }\n LABEL_7:\n __sprintf_chk(v13, 2LL, 20LL, &unk_2006, (unsigned int)v2[1]);\n __strcat_chk(v4, v13, 1024LL);\n goto LABEL_8;\n }\n LABEL_16:\n v2 += 4;\n if (v2 == v6) goto LABEL_17;\n }\n if (v5) {\n __strcat_chk(v4, &unk_2004, 1024LL);\n } else {\n v11 = (char *)&v4[strlen(v4)];\n strcpy(v11, \", \");\n __memcpy_chk(v11 + 2, &unk_2004, 2LL, v4 - (v11 + 2) + 1024);\n }\n goto LABEL_7;\n }\n LABEL_17:\n __strcat_chk(v4, \"]\", 1024LL);\n }\n return v4;\n}", + "ida_pseudo_norm": "const char *func0(int *a1, int a2) {\n int *v2;\n char *v3;\n const char *v4;\n int v5;\n int *v6;\n char *v7;\n int v8;\n char *v9;\n char *v11;\n int v12;\n uint8_t v13[24];\n unsigned long long v14;\n v2 = a1;\n v14 = __readfsqword(40u);\n v3 = (char *)malloc(1024uLL);\n v4 = v3;\n if (v3) {\n *(unsigned short *)v3 = 91;\n if (a2 > 0) {\n v5 = 1;\n v6 = &a1[4 * a2];\n while (!*v2) {\n if (v2[2]) {\n if (v5) {\n __strcat_chk(v4, &unk_2004, 1024LL);\n goto LABEL_13;\n }\n v8 = 0;\n while (1) {\n v12 = v8;\n v9 = (char *)&v4[strlen(v4)];\n strcpy(v9, \", \");\n __memcpy_chk(v9 + 2, &unk_2004, 2LL, v4 - (v9 + 2) + 1024);\n if (v12) break;\n LABEL_13:\n __strcat_chk(v4, \"None\", 1024LL);\n LABEL_8:\n v7 = (char *)&v4[strlen(v4)];\n strcpy(v7, \", \");\n if (v2[2]) {\n __sprintf_chk(v13, 2LL, 20LL, &unk_2006, (unsigned int)v2[3]);\n __strcat_chk(v4, v13, 1024LL);\n } else {\n __memcpy_chk(v7 + 2, \"None\", 5LL, v4 - (v7 + 2) + 1024);\n }\n v2 += 4;\n __strcat_chk(v4, \")\", 1024LL);\n if (v2 == v6) goto LABEL_17;\n v8 = *v2;\n if (!*v2) {\n v5 = v2[2];\n if (!v5) goto LABEL_16;\n }\n }\n LABEL_7:\n __sprintf_chk(v13, 2LL, 20LL, &unk_2006, (unsigned int)v2[1]);\n __strcat_chk(v4, v13, 1024LL);\n goto LABEL_8;\n }\n LABEL_16:\n v2 += 4;\n if (v2 == v6) goto LABEL_17;\n }\n if (v5) {\n __strcat_chk(v4, &unk_2004, 1024LL);\n } else {\n v11 = (char *)&v4[strlen(v4)];\n strcpy(v11, \", \");\n __memcpy_chk(v11 + 2, &unk_2004, 2LL, v4 - (v11 + 2) + 1024);\n }\n goto LABEL_7;\n }\n LABEL_17:\n __strcat_chk(v4, \"]\", 1024LL);\n }\n return v4;\n}" + }, + { + "index": 921, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct\n\n{\n\n int *elements;\n\n int size;\n\n} tuple;\n\n\n\n", + "func": "tuple *func0(const int *test_tup, int tup_size, int N, int *num_chunks)\n{\n *num_chunks = (tup_size + N - 1) / N;\n tuple *res = malloc(*num_chunks * sizeof(tuple));\n for (int i = 0; i < *num_chunks; i++)\n {\n int start = i * N;\n int end = start + N < tup_size ? start + N : tup_size;\n int chunk_size = end - start;\n res[i].elements = malloc(chunk_size * sizeof(int));\n res[i].size = chunk_size;\n for (int j = start; j < end; j++)\n {\n res[i].elements[j - start] = test_tup[j];\n }\n }\n return res;\n}", + "test": "int main()\n\n{\n\n int test1[] = {10, 4, 5, 6, 7, 6, 8, 3, 4};\n\n int num_chunks1;\n\n tuple *chunks1 = func0(test1, sizeof(test1) / sizeof(test1[0]), 3, &num_chunks1);\n\n assert(num_chunks1 == 3 && chunks1[0].size == 3 && chunks1[1].size == 3 && chunks1[2].size == 3);\n\n free(chunks1);\n\n\n\n int test2[] = {1, 2, 3, 4, 5, 6, 7, 8, 9};\n\n int num_chunks2;\n\n tuple *chunks2 = func0(test2, sizeof(test2) / sizeof(test2[0]), 2, &num_chunks2);\n\n assert(num_chunks2 == 5 && chunks2[0].size == 2 && chunks2[4].size == 1);\n\n free(chunks2);\n\n\n\n int test3[] = {11, 14, 16, 17, 19, 21, 22, 25};\n\n int num_chunks3;\n\n tuple *chunks3 = func0(test3, sizeof(test3) / sizeof(test3[0]), 4, &num_chunks3);\n\n assert(num_chunks3 == 2 && chunks3[0].size == 4 && chunks3[1].size == 4);\n\n free(chunks3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x48,%rsp\nmov %rdi,-0x38(%rbp)\nmov %esi,-0x3c(%rbp)\nmov %edx,-0x40(%rbp)\nmov %rcx,-0x48(%rbp)\nmov -0x3c(%rbp),%edx\nmov -0x40(%rbp),%eax\nadd %edx,%eax\nsub $0x1,%eax\ncltd\nidivl -0x40(%rbp)\nmov %eax,%edx\nmov -0x48(%rbp),%rax\nmov %edx,(%rax)\nmov -0x48(%rbp),%rax\nmov (%rax),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x18(%rbp)\nmovl $0x0,-0x2c(%rbp)\njmpq 12bc \nmov -0x2c(%rbp),%eax\nimul -0x40(%rbp),%eax\nmov %eax,-0x24(%rbp)\nmov -0x24(%rbp),%edx\nmov -0x40(%rbp),%eax\nadd %edx,%eax\ncmp %eax,-0x3c(%rbp)\ncmovle -0x3c(%rbp),%eax\nmov %eax,-0x20(%rbp)\nmov -0x20(%rbp),%eax\nsub -0x24(%rbp),%eax\nmov %eax,-0x1c(%rbp)\nmov -0x1c(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov -0x2c(%rbp),%edx\nmovslq %edx,%rdx\nmov %rdx,%rcx\nshl $0x4,%rcx\nmov -0x18(%rbp),%rdx\nlea (%rcx,%rdx,1),%rbx\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,(%rbx)\nmov -0x2c(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0x1c(%rbp),%eax\nmov %eax,0x8(%rdx)\nmov -0x24(%rbp),%eax\nmov %eax,-0x28(%rbp)\njmp 12b0 \nmov -0x28(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x38(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x2c(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rdx\nmov -0x28(%rbp),%eax\nsub -0x24(%rbp),%eax\ncltq\nshl $0x2,%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x28(%rbp)\nmov -0x28(%rbp),%eax\ncmp -0x20(%rbp),%eax\njl 126e \naddl $0x1,-0x2c(%rbp)\nmov -0x48(%rbp),%rax\nmov (%rax),%eax\ncmp %eax,-0x2c(%rbp)\njl 11ff \nmov -0x18(%rbp),%rax\nadd $0x48,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 48h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov [rbp+var_40], edx\nmov [rbp+var_48], rcx\nmov edx, [rbp+var_3C]\nmov eax, [rbp+var_40]\nadd eax, edx\nsub eax, 1\ncdq\nidiv [rbp+var_40]\nmov edx, eax\nmov rax, [rbp+var_48]\nmov [rax], edx\nmov rax, [rbp+var_48]\nmov eax, [rax]\ncdqe\nshl rax, 4\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_2C], 0\njmp loc_12BD\nloc_11FF:\nmov eax, [rbp+var_2C]\nimul eax, [rbp+var_40]\nmov [rbp+var_24], eax\nmov edx, [rbp+var_24]\nmov eax, [rbp+var_40]\nadd eax, edx\nmov edx, [rbp+var_3C]\ncmp edx, eax\ncmovle eax, edx\nmov [rbp+var_20], eax\nmov eax, [rbp+var_20]\nsub eax, [rbp+var_24]\nmov [rbp+var_1C], eax\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nmov edx, [rbp+var_2C]\nmovsxd rdx, edx\nmov rcx, rdx\nshl rcx, 4\nmov rdx, [rbp+var_18]\nlea rbx, [rcx+rdx]\nmov rdi, rax; size\ncall _malloc\nmov [rbx], rax\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_1C]\nmov [rdx+8], eax\nmov eax, [rbp+var_24]\nmov [rbp+var_28], eax\njmp short loc_12B1\nloc_126F:\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_28]\nsub eax, [rbp+var_24]\ncdqe\nshl rax, 2\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nadd [rbp+var_28], 1\nloc_12B1:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_20]\njl short loc_126F\nadd [rbp+var_2C], 1\nloc_12BD:\nmov rax, [rbp+var_48]\nmov eax, [rax]\ncmp [rbp+var_2C], eax\njl loc_11FF\nmov rax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, int a2, int a3, int *a4)\n{\n int v4; // eax\n int i; // [rsp+24h] [rbp-2Ch]\n int j; // [rsp+28h] [rbp-28h]\n int v10; // [rsp+2Ch] [rbp-24h]\n int v11; // [rsp+30h] [rbp-20h]\n int v12; // [rsp+34h] [rbp-1Ch]\n _QWORD *v13; // [rsp+38h] [rbp-18h]\n\n *a4 = (a2 + a3 - 1) / a3;\n v13 = malloc(16LL * *a4);\n for ( i = 0; i < *a4; ++i )\n {\n v10 = a3 * i;\n v4 = a3 * i + a3;\n if ( a2 <= v4 )\n v4 = a2;\n v11 = v4;\n v12 = v4 - v10;\n v13[2 * i] = malloc(4LL * (v4 - v10));\n LODWORD(v13[2 * i + 1]) = v12;\n for ( j = a3 * i; j < v11; ++j )\n *(_DWORD *)(4LL * (j - v10) + v13[2 * i]) = *(_DWORD *)(4LL * j + a1);\n }\n return v13;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 48h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov [rbp+var_40], edx\nmov [rbp+var_48], rcx\nmov edx, [rbp+var_3C]\nmov eax, [rbp+var_40]\nadd eax, edx\nsub eax, 1\ncdq\nidiv [rbp+var_40]\nmov edx, eax\nmov rax, [rbp+var_48]\nmov [rax], edx\nmov rax, [rbp+var_48]\nmov eax, [rax]\ncdqe\nshl rax, 4\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_2C], 0\njmp loc_12BD\nloc_11FF:\nmov eax, [rbp+var_2C]\nimul eax, [rbp+var_40]\nmov [rbp+var_24], eax\nmov edx, [rbp+var_24]\nmov eax, [rbp+var_40]\nadd eax, edx\nmov edx, [rbp+var_3C]\ncmp edx, eax\ncmovle eax, edx\nmov [rbp+var_20], eax\nmov eax, [rbp+var_20]\nsub eax, [rbp+var_24]\nmov [rbp+var_1C], eax\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 2\nmov edx, [rbp+var_2C]\nmovsxd rdx, edx\nmov rcx, rdx\nshl rcx, 4\nmov rdx, [rbp+var_18]\nlea rbx, [rcx+rdx]\nmov rdi, rax; size\ncall _malloc\nmov [rbx], rax\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov eax, [rbp+var_1C]\nmov [rdx+8], eax\nmov eax, [rbp+var_24]\nmov [rbp+var_28], eax\njmp short loc_12B1\nloc_126F:\nmov eax, [rbp+var_28]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_28]\nsub eax, [rbp+var_24]\ncdqe\nshl rax, 2\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nadd [rbp+var_28], 1\nloc_12B1:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_20]\njl short loc_126F\nadd [rbp+var_2C], 1\nloc_12BD:\nmov rax, [rbp+var_48]\nmov eax, [rax]\ncmp [rbp+var_2C], eax\njl loc_11FF\nmov rax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11A9(__int64 a1, int a2, int a3, int *a4)\n{\n int v4; // eax\n int i; // [rsp+24h] [rbp-2Ch]\n int j; // [rsp+28h] [rbp-28h]\n int v10; // [rsp+2Ch] [rbp-24h]\n int v11; // [rsp+30h] [rbp-20h]\n int v12; // [rsp+34h] [rbp-1Ch]\n _QWORD *v13; // [rsp+38h] [rbp-18h]\n\n *a4 = (a2 + a3 - 1) / a3;\n v13 = malloc(16LL * *a4);\n for ( i = 0; i < *a4; ++i )\n {\n v10 = a3 * i;\n v4 = a3 * i + a3;\n if ( a2 <= v4 )\n v4 = a2;\n v11 = v4;\n v12 = v4 - v10;\n v13[2 * i] = malloc(4LL * (v4 - v10));\n LODWORD(v13[2 * i + 1]) = v12;\n for ( j = a3 * i; j < v11; ++j )\n *(_DWORD *)(4LL * (j - v10) + v13[2 * i]) = *(_DWORD *)(4LL * j + a1);\n }\n return v13;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11A9(long long a1, int a2, int a3, int *a4) {\n int v4;\n int i;\n int j;\n int v10;\n int v11;\n int v12;\n uint64_t *v13;\n *a4 = (a2 + a3 - 1) / a3;\n v13 = malloc(16LL * *a4);\n for (i = 0; i < *a4; ++i) {\n v10 = a3 * i;\n v4 = a3 * i + a3;\n if (a2 <= v4) v4 = a2;\n v11 = v4;\n v12 = v4 - v10;\n v13[2 * i] = malloc(4LL * (v4 - v10));\n LODWORD(v13[2 * i + 1]) = v12;\n for (j = a3 * i; j < v11; ++j)\n *(uint32_t *)(4LL * (j - v10) + v13[2 * i]) = *(uint32_t *)(4LL * j + a1);\n }\n return v13;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, int a2, int a3, int *a4) {\n int v4;\n int i;\n int j;\n int v10;\n int v11;\n int v12;\n uint64_t *v13;\n *a4 = (a2 + a3 - 1) / a3;\n v13 = malloc(16LL * *a4);\n for (i = 0; i < *a4; ++i) {\n v10 = a3 * i;\n v4 = a3 * i + a3;\n if (a2 <= v4) v4 = a2;\n v11 = v4;\n v12 = v4 - v10;\n v13[2 * i] = malloc(4LL * (v4 - v10));\n LODWORD(v13[2 * i + 1]) = v12;\n for (j = a3 * i; j < v11; ++j)\n *(uint32_t *)(4LL * (j - v10) + v13[2 * i]) = *(uint32_t *)(4LL * j + a1);\n }\n return v13;\n}" + }, + { + "index": 921, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct\n\n{\n\n int *elements;\n\n int size;\n\n} tuple;\n\n\n\n", + "func": "tuple *func0(const int *test_tup, int tup_size, int N, int *num_chunks)\n{\n *num_chunks = (tup_size + N - 1) / N;\n tuple *res = malloc(*num_chunks * sizeof(tuple));\n for (int i = 0; i < *num_chunks; i++)\n {\n int start = i * N;\n int end = start + N < tup_size ? start + N : tup_size;\n int chunk_size = end - start;\n res[i].elements = malloc(chunk_size * sizeof(int));\n res[i].size = chunk_size;\n for (int j = start; j < end; j++)\n {\n res[i].elements[j - start] = test_tup[j];\n }\n }\n return res;\n}", + "test": "int main()\n\n{\n\n int test1[] = {10, 4, 5, 6, 7, 6, 8, 3, 4};\n\n int num_chunks1;\n\n tuple *chunks1 = func0(test1, sizeof(test1) / sizeof(test1[0]), 3, &num_chunks1);\n\n assert(num_chunks1 == 3 && chunks1[0].size == 3 && chunks1[1].size == 3 && chunks1[2].size == 3);\n\n free(chunks1);\n\n\n\n int test2[] = {1, 2, 3, 4, 5, 6, 7, 8, 9};\n\n int num_chunks2;\n\n tuple *chunks2 = func0(test2, sizeof(test2) / sizeof(test2[0]), 2, &num_chunks2);\n\n assert(num_chunks2 == 5 && chunks2[0].size == 2 && chunks2[4].size == 1);\n\n free(chunks2);\n\n\n\n int test3[] = {11, 14, 16, 17, 19, 21, 22, 25};\n\n int num_chunks3;\n\n tuple *chunks3 = func0(test3, sizeof(test3) / sizeof(test3[0]), 4, &num_chunks3);\n\n assert(num_chunks3 == 2 && chunks3[0].size == 4 && chunks3[1].size == 4);\n\n free(chunks3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x38,%rsp\nmov %rdi,%rbp\nmov %esi,0x18(%rsp)\nmov %edx,%ebx\nmov %rcx,%r14\nmov %rcx,0x10(%rsp)\nlea -0x1(%rsi,%rdx,1),%eax\ncltd\nidiv %ebx\nmov %eax,(%rcx)\nmovslq %eax,%rdi\nshl $0x4,%rdi\ncallq 10b0 \nmov %rax,0x28(%rsp)\ncmpl $0x0,(%r14)\njle 129c \nmov %ebx,0x1c(%rsp)\nmov %rax,%r12\nmovslq %ebx,%rbx\nlea 0x0(,%rbx,4),%rax\nmov %rax,0x20(%rsp)\nmov %rbp,%rbx\nmov $0x0,%ebp\nmov $0x0,%r14d\njmp 122e \nadd $0x1,%r14d\nadd $0x10,%r12\nadd 0x20(%rsp),%rbx\nmov 0x10(%rsp),%rax\ncmp %r14d,(%rax)\njle 129c \nmov %ebp,%esi\nmov %ebp,0xc(%rsp)\nadd 0x1c(%rsp),%ebp\nmov 0x18(%rsp),%eax\ncmp %eax,%ebp\nmov %eax,%r13d\ncmovle %ebp,%r13d\nmov %r13d,%r15d\nmov %esi,0x8(%rsp)\nsub %esi,%r15d\nmovslq %r15d,%rdi\nshl $0x2,%rdi\ncallq 10b0 \nmov %r12,%rsi\nmov %rax,(%r12)\nmov %r15d,0x8(%r12)\ncmp %r13d,0x8(%rsp)\njge 1217 \nmov 0xc(%rsp),%eax\nnot %eax\nlea (%rax,%r13,1),%eax\nlea 0x4(,%rax,4),%rdi\nmov $0x0,%eax\nmov (%rbx,%rax,1),%ecx\nmov (%rsi),%rdx\nmov %ecx,(%rdx,%rax,1)\nadd $0x4,%rax\ncmp %rdi,%rax\njne 1285 \njmpq 1217 \nmov 0x28(%rsp),%rax\nadd $0x38,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 38h\nmov rbp, rdi\nmov [rsp+68h+var_58], esi\nmov ebx, edx\nmov [rsp+68h+var_54], edx\nmov r14, rcx\nmov [rsp+68h+var_50], rcx\nlea eax, [rsi+rdx-1]\ncdq\nidiv ebx\nmov [rcx], eax\nmovsxd rdi, eax\nshl rdi, 4; size\ncall _malloc\nmov [rsp+68h+var_40], rax\ncmp dword ptr [r14], 0\njle loc_1288\nmov r13, rax\nmovsxd rax, ebx\nshl rax, 2\nmov [rsp+68h+var_48], rax\nmov r12d, 0\nmov r14d, 0\nloc_120F:\nmov esi, r12d\nmov [rsp+68h+var_5C], r12d\nmov eax, [rsp+68h+var_54]\nadd r12d, eax\nmov eax, [rsp+68h+var_58]\ncmp r12d, eax\nmov ebx, eax\ncmovle ebx, r12d\nmov r15d, ebx\nmov [rsp+68h+var_60], esi\nsub r15d, esi\nmovsxd rdi, r15d\nshl rdi, 2; size\ncall _malloc\nmov [r13+0], rax\nmov [r13+8], r15d\ncmp [rsp+68h+var_60], ebx\njge short loc_126E\nmov edi, [rsp+68h+var_5C]\nsub ebx, edi\nshl rbx, 2\nmov edx, 0\nloc_125E:\nmov ecx, [rbp+rdx+0]\nmov [rax+rdx], ecx\nadd rdx, 4\ncmp rdx, rbx\njnz short loc_125E\nloc_126E:\nadd r14d, 1\nadd r13, 10h\nmov rax, [rsp+68h+var_48]\nadd rbp, rax\nmov rax, [rsp+68h+var_50]\ncmp [rax], r14d\njg short loc_120F\nloc_1288:\nmov rax, [rsp+68h+var_40]\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "void *__fastcall func0(__int64 a1, int a2, int a3, int *a4)\n{\n int v7; // eax\n void *v8; // rax\n _DWORD *v9; // r13\n int v10; // r12d\n int v11; // r14d\n int v12; // esi\n int v13; // ebx\n char *v14; // rax\n __int64 v15; // rbx\n __int64 v16; // rdx\n int v18; // [rsp+Ch] [rbp-5Ch]\n __int64 v22; // [rsp+20h] [rbp-48h]\n void *v23; // [rsp+28h] [rbp-40h]\n\n v7 = (a2 + a3 - 1) / a3;\n *a4 = v7;\n v8 = malloc(16LL * v7);\n v23 = v8;\n if ( *a4 > 0 )\n {\n v9 = v8;\n v22 = 4LL * a3;\n v10 = 0;\n v11 = 0;\n do\n {\n v12 = v10;\n v18 = v10;\n v10 += a3;\n v13 = a2;\n if ( v10 <= a2 )\n v13 = v10;\n v14 = (char *)malloc(4LL * (v13 - v12));\n *(_QWORD *)v9 = v14;\n v9[2] = v13 - v12;\n if ( v12 < v13 )\n {\n v15 = 4LL * (unsigned int)(v13 - v18);\n v16 = 0LL;\n do\n {\n *(_DWORD *)&v14[v16] = *(_DWORD *)(a1 + v16);\n v16 += 4LL;\n }\n while ( v16 != v15 );\n }\n ++v11;\n v9 += 4;\n a1 += v22;\n }\n while ( *a4 > v11 );\n }\n return v23;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 38h\nmov rbp, rdi\nmov [rsp+68h+var_58], esi\nmov ebx, edx\nmov [rsp+68h+var_54], edx\nmov r14, rcx\nmov [rsp+68h+var_50], rcx\nlea eax, [rsi+rdx-1]\ncdq\nidiv ebx\nmov [rcx], eax\nmovsxd rdi, eax\nshl rdi, 4; size\ncall _malloc\nmov [rsp+68h+var_40], rax\ncmp dword ptr [r14], 0\njle loc_1288\nmov r13, rax\nmovsxd rax, ebx\nshl rax, 2\nmov [rsp+68h+var_48], rax\nmov r12d, 0\nmov r14d, 0\nloc_120F:\nmov esi, r12d\nmov [rsp+68h+var_5C], r12d\nmov eax, [rsp+68h+var_54]\nadd r12d, eax\nmov eax, [rsp+68h+var_58]\ncmp r12d, eax\nmov ebx, eax\ncmovle ebx, r12d\nmov r15d, ebx\nmov [rsp+68h+var_60], esi\nsub r15d, esi\nmovsxd rdi, r15d\nshl rdi, 2; size\ncall _malloc\nmov [r13+0], rax\nmov [r13+8], r15d\ncmp [rsp+68h+var_60], ebx\njge short loc_126E\nmov edi, [rsp+68h+var_5C]\nsub ebx, edi\nshl rbx, 2\nmov edx, 0\nloc_125E:\nmov ecx, [rbp+rdx+0]\nmov [rax+rdx], ecx\nadd rdx, 4\ncmp rdx, rbx\njnz short loc_125E\nloc_126E:\nadd r14d, 1\nadd r13, 10h\nmov rax, [rsp+68h+var_48]\nadd rbp, rax\nmov rax, [rsp+68h+var_50]\ncmp [rax], r14d\njg short loc_120F\nloc_1288:\nmov rax, [rsp+68h+var_40]\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "void *__fastcall sub_11A9(__int64 a1, int a2, int a3, int *a4)\n{\n int v7; // eax\n void *v8; // rax\n _DWORD *v9; // r13\n int v10; // r12d\n int v11; // r14d\n int v12; // esi\n int v13; // ebx\n char *v14; // rax\n __int64 v15; // rbx\n __int64 v16; // rdx\n int v18; // [rsp+Ch] [rbp-5Ch]\n __int64 v22; // [rsp+20h] [rbp-48h]\n void *v23; // [rsp+28h] [rbp-40h]\n\n v7 = (a2 + a3 - 1) / a3;\n *a4 = v7;\n v8 = malloc(16LL * v7);\n v23 = v8;\n if ( *a4 > 0 )\n {\n v9 = v8;\n v22 = 4LL * a3;\n v10 = 0;\n v11 = 0;\n do\n {\n v12 = v10;\n v18 = v10;\n v10 += a3;\n v13 = a2;\n if ( v10 <= a2 )\n v13 = v10;\n v14 = (char *)malloc(4LL * (v13 - v12));\n *(_QWORD *)v9 = v14;\n v9[2] = v13 - v12;\n if ( v12 < v13 )\n {\n v15 = 4LL * (unsigned int)(v13 - v18);\n v16 = 0LL;\n do\n {\n *(_DWORD *)&v14[v16] = *(_DWORD *)(a1 + v16);\n v16 += 4LL;\n }\n while ( v16 != v15 );\n }\n ++v11;\n v9 += 4;\n a1 += v22;\n }\n while ( *a4 > v11 );\n }\n return v23;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_11A9(long long a1, int a2, int a3, int *a4) {\n int v7;\n void *v8;\n uint32_t *v9;\n int v10;\n int v11;\n int v12;\n int v13;\n char *v14;\n long long v15;\n long long v16;\n int v18;\n long long v22;\n void *v23;\n v7 = (a2 + a3 - 1) / a3;\n *a4 = v7;\n v8 = malloc(16LL * v7);\n v23 = v8;\n if (*a4 > 0) {\n v9 = v8;\n v22 = 4LL * a3;\n v10 = 0;\n v11 = 0;\n do {\n v12 = v10;\n v18 = v10;\n v10 += a3;\n v13 = a2;\n if (v10 <= a2) v13 = v10;\n v14 = (char *)malloc(4LL * (v13 - v12));\n *(uint64_t *)v9 = v14;\n v9[2] = v13 - v12;\n if (v12 < v13) {\n v15 = 4LL * (unsigned int)(v13 - v18);\n v16 = 0LL;\n do {\n *(uint32_t *)&v14[v16] = *(uint32_t *)(a1 + v16);\n v16 += 4LL;\n } while (v16 != v15);\n }\n ++v11;\n v9 += 4;\n a1 += v22;\n } while (*a4 > v11);\n }\n return v23;\n}", + "ida_pseudo_norm": "void *func0(long long a1, int a2, int a3, int *a4) {\n int v7;\n void *v8;\n uint32_t *v9;\n int v10;\n int v11;\n int v12;\n int v13;\n char *v14;\n long long v15;\n long long v16;\n int v18;\n long long v22;\n void *v23;\n v7 = (a2 + a3 - 1) / a3;\n *a4 = v7;\n v8 = malloc(16LL * v7);\n v23 = v8;\n if (*a4 > 0) {\n v9 = v8;\n v22 = 4LL * a3;\n v10 = 0;\n v11 = 0;\n do {\n v12 = v10;\n v18 = v10;\n v10 += a3;\n v13 = a2;\n if (v10 <= a2) v13 = v10;\n v14 = (char *)malloc(4LL * (v13 - v12));\n *(uint64_t *)v9 = v14;\n v9[2] = v13 - v12;\n if (v12 < v13) {\n v15 = 4LL * (unsigned int)(v13 - v18);\n v16 = 0LL;\n do {\n *(uint32_t *)&v14[v16] = *(uint32_t *)(a1 + v16);\n v16 += 4LL;\n } while (v16 != v15);\n }\n ++v11;\n v9 += 4;\n a1 += v22;\n } while (*a4 > v11);\n }\n return v23;\n}" + }, + { + "index": 921, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct\n\n{\n\n int *elements;\n\n int size;\n\n} tuple;\n\n\n\n", + "func": "tuple *func0(const int *test_tup, int tup_size, int N, int *num_chunks)\n{\n *num_chunks = (tup_size + N - 1) / N;\n tuple *res = malloc(*num_chunks * sizeof(tuple));\n for (int i = 0; i < *num_chunks; i++)\n {\n int start = i * N;\n int end = start + N < tup_size ? start + N : tup_size;\n int chunk_size = end - start;\n res[i].elements = malloc(chunk_size * sizeof(int));\n res[i].size = chunk_size;\n for (int j = start; j < end; j++)\n {\n res[i].elements[j - start] = test_tup[j];\n }\n }\n return res;\n}", + "test": "int main()\n\n{\n\n int test1[] = {10, 4, 5, 6, 7, 6, 8, 3, 4};\n\n int num_chunks1;\n\n tuple *chunks1 = func0(test1, sizeof(test1) / sizeof(test1[0]), 3, &num_chunks1);\n\n assert(num_chunks1 == 3 && chunks1[0].size == 3 && chunks1[1].size == 3 && chunks1[2].size == 3);\n\n free(chunks1);\n\n\n\n int test2[] = {1, 2, 3, 4, 5, 6, 7, 8, 9};\n\n int num_chunks2;\n\n tuple *chunks2 = func0(test2, sizeof(test2) / sizeof(test2[0]), 2, &num_chunks2);\n\n assert(num_chunks2 == 5 && chunks2[0].size == 2 && chunks2[4].size == 1);\n\n free(chunks2);\n\n\n\n int test3[] = {11, 14, 16, 17, 19, 21, 22, 25};\n\n int num_chunks3;\n\n tuple *chunks3 = func0(test3, sizeof(test3) / sizeof(test3[0]), 4, &num_chunks3);\n\n assert(num_chunks3 == 2 && chunks3[0].size == 4 && chunks3[1].size == 4);\n\n free(chunks3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nlea -0x1(%rsi,%rdx,1),%eax\npush %r14\nmov %rcx,%r14\npush %r13\npush %r12\npush %rbp\nmov %rdi,%rbp\npush %rbx\nmov %edx,%ebx\nsub $0x48,%rsp\nmov %edx,0x1c(%rsp)\ncltd\nidiv %ebx\nmov %esi,0x18(%rsp)\nmov %rcx,0x20(%rsp)\nmov %eax,(%rcx)\nmovslq %eax,%rdi\nshl $0x4,%rdi\ncallq 10b0 \nmov (%r14),%edx\nmov %rax,0x38(%rsp)\ntest %edx,%edx\njle 14d8 \nmov %rax,%rcx\nmovslq %ebx,%rax\nxor %r12d,%r12d\nxor %r13d,%r13d\nmov %rax,0x28(%rsp)\nneg %rax\nmov %r13d,%edx\nxor %r14d,%r14d\nshl $0x2,%rax\nmov %r12,%r13\nxor %r15d,%r15d\nmov %rcx,%r12\nmov %rax,0x30(%rsp)\nnopl 0x0(%rax,%rax,1)\nmov 0x18(%rsp),%ebx\nmov %edx,%r8d\nadd 0x1c(%rsp),%edx\nmov %edx,0x14(%rsp)\ncmp %ebx,%edx\nmov %r8d,0x10(%rsp)\ncmovle %edx,%ebx\nmov %ebx,%r9d\nsub %r8d,%r9d\nmovslq %r9d,%rdi\nmov %r9d,0xc(%rsp)\nshl $0x2,%rdi\ncallq 10b0 \nmov 0x10(%rsp),%r8d\nmov 0xc(%rsp),%r9d\nmov %rax,(%r12)\nmov 0x14(%rsp),%edx\ncmp %ebx,%r8d\nmov %r9d,0x8(%r12)\njge 14b8 \nmov %r14,%rdi\nlea (%rax,%r13,1),%r8\nnopl 0x0(%rax,%rax,1)\nmov 0x0(%rbp,%rdi,4),%eax\nmov %eax,(%r8,%rdi,4)\nadd $0x1,%rdi\ncmp %edi,%ebx\njg 14a8 \nmov 0x20(%rsp),%rax\nadd $0x1,%r15d\nadd $0x10,%r12\nadd 0x28(%rsp),%r14\nadd 0x30(%rsp),%r13\ncmp %r15d,(%rax)\njg 1450 \nmov 0x38(%rsp),%rax\nadd $0x48,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmovsxd r15, edx\nlea eax, [rsi+r15-1]\npush r14\ncdq\npush r13\nidiv r15d\npush r12\npush rbp\npush rbx\nsub rsp, 38h\nmov rbx, rdi\nmov rbp, rcx\nmov r12d, esi\nmov [rsp+68h+var_54], r15d\nmov [rsp+68h+var_50], rcx\nmov [rcx], eax\nmovsxd rdi, eax\nshl rdi, 4; size\ncall _malloc\nmov edx, [rbp+0]\nmov [rsp+68h+var_40], rax\ntest edx, edx\njle loc_146B\nmov r14, rax\nlea rax, ds:0[r15*4]\nxor ebp, ebp\nxor r15d, r15d\nmov [rsp+68h+var_48], rax\nnop dword ptr [rax+00h]\nloc_13F8:\nmov eax, [rsp+68h+var_54]\nmov r9d, r15d\nmov esi, r12d\nmov [rsp+68h+var_5C], r9d\nadd r15d, eax\ncmp r15d, r12d\ncmovle esi, r15d\nmov r13d, esi\nmov [rsp+68h+var_58], esi\nsub r13d, r9d\nmovsxd rdi, r13d\nshl rdi, 2; size\ncall _malloc\nmov r9d, [rsp+68h+var_5C]\nmov esi, [rsp+68h+var_58]\nmov [r14+8], r13d\nmov [r14], rax\nmov rdi, rax; dest\ncmp r9d, esi\njge short loc_1453\nlea eax, [r13-1]\nmov rsi, rbx; src\nlea rdx, ds:4[rax*4]; n\ncall _memcpy\nloc_1453:\nmov rax, [rsp+68h+var_48]\nadd ebp, 1\nadd r14, 10h\nadd rbx, rax\nmov rax, [rsp+68h+var_50]\ncmp [rax], ebp\njg short loc_13F8\nloc_146B:\nmov rax, [rsp+68h+var_40]\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "void *__fastcall func0(char *src, int a2, int a3, int *a4)\n{\n __int64 v4; // r15\n int v5; // eax\n void *v9; // rax\n _DWORD *v10; // r14\n __int64 v11; // rax\n int v12; // ebp\n int v13; // r15d\n int v14; // r9d\n int v15; // esi\n int v16; // r13d\n void *v17; // rax\n int v19; // [rsp+Ch] [rbp-5Ch]\n __int64 v22; // [rsp+20h] [rbp-48h]\n void *v23; // [rsp+28h] [rbp-40h]\n\n v4 = a3;\n v5 = (a2 + a3 - 1) / a3;\n *a4 = v5;\n v9 = malloc(16LL * v5);\n v23 = v9;\n if ( *a4 > 0 )\n {\n v10 = v9;\n v11 = 4 * v4;\n v12 = 0;\n v13 = 0;\n v22 = v11;\n do\n {\n v14 = v13;\n v15 = a2;\n v19 = v13;\n v13 += a3;\n if ( v13 <= a2 )\n v15 = v13;\n v16 = v15 - v14;\n v17 = malloc(4LL * (v15 - v14));\n v10[2] = v16;\n *(_QWORD *)v10 = v17;\n if ( v19 < v15 )\n memcpy(v17, src, 4LL * (unsigned int)(v16 - 1) + 4);\n ++v12;\n v10 += 4;\n src += v22;\n }\n while ( *a4 > v12 );\n }\n return v23;\n}", + "ida_strip_asm": "sub_1390:\nendbr64\npush r15\nmovsxd r15, edx\nlea eax, [rsi+r15-1]\npush r14\ncdq\npush r13\nidiv r15d\npush r12\npush rbp\npush rbx\nsub rsp, 38h\nmov rbx, rdi\nmov rbp, rcx\nmov r12d, esi\nmov [rsp+68h+var_54], r15d\nmov [rsp+68h+var_50], rcx\nmov [rcx], eax\nmovsxd rdi, eax\nshl rdi, 4; size\ncall _malloc\nmov edx, [rbp+0]\nmov [rsp+68h+var_40], rax\ntest edx, edx\njle loc_146B\nmov r14, rax\nlea rax, ds:0[r15*4]\nxor ebp, ebp\nxor r15d, r15d\nmov [rsp+68h+var_48], rax\nnop dword ptr [rax+00h]\nloc_13F8:\nmov eax, [rsp+68h+var_54]\nmov r9d, r15d\nmov esi, r12d\nmov [rsp+68h+var_5C], r9d\nadd r15d, eax\ncmp r15d, r12d\ncmovle esi, r15d\nmov r13d, esi\nmov [rsp+68h+var_58], esi\nsub r13d, r9d\nmovsxd rdi, r13d\nshl rdi, 2; size\ncall _malloc\nmov r9d, [rsp+68h+var_5C]\nmov esi, [rsp+68h+var_58]\nmov [r14+8], r13d\nmov [r14], rax\nmov rdi, rax; dest\ncmp r9d, esi\njge short loc_1453\nlea eax, [r13-1]\nmov rsi, rbx; src\nlea rdx, ds:4[rax*4]; n\ncall _memcpy\nloc_1453:\nmov rax, [rsp+68h+var_48]\nadd ebp, 1\nadd r14, 10h\nadd rbx, rax\nmov rax, [rsp+68h+var_50]\ncmp [rax], ebp\njg short loc_13F8\nloc_146B:\nmov rax, [rsp+68h+var_40]\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "void *__fastcall sub_1390(char *src, int a2, int a3, int *a4)\n{\n __int64 v4; // r15\n int v5; // eax\n void *v9; // rax\n _DWORD *v10; // r14\n __int64 v11; // rax\n int v12; // ebp\n int v13; // r15d\n int v14; // r9d\n int v15; // esi\n int v16; // r13d\n void *v17; // rax\n int v19; // [rsp+Ch] [rbp-5Ch]\n __int64 v22; // [rsp+20h] [rbp-48h]\n void *v23; // [rsp+28h] [rbp-40h]\n\n v4 = a3;\n v5 = (a2 + a3 - 1) / a3;\n *a4 = v5;\n v9 = malloc(16LL * v5);\n v23 = v9;\n if ( *a4 > 0 )\n {\n v10 = v9;\n v11 = 4 * v4;\n v12 = 0;\n v13 = 0;\n v22 = v11;\n do\n {\n v14 = v13;\n v15 = a2;\n v19 = v13;\n v13 += a3;\n if ( v13 <= a2 )\n v15 = v13;\n v16 = v15 - v14;\n v17 = malloc(4LL * (v15 - v14));\n v10[2] = v16;\n *(_QWORD *)v10 = v17;\n if ( v19 < v15 )\n memcpy(v17, src, 4LL * (unsigned int)(v16 - 1) + 4);\n ++v12;\n v10 += 4;\n src += v22;\n }\n while ( *a4 > v12 );\n }\n return v23;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1390(char *src, int a2, int a3, int *a4) {\n long long v4;\n int v5;\n void *v9;\n uint32_t *v10;\n long long v11;\n int v12;\n int v13;\n int v14;\n int v15;\n int v16;\n void *v17;\n int v19;\n long long v22;\n void *v23;\n v4 = a3;\n v5 = (a2 + a3 - 1) / a3;\n *a4 = v5;\n v9 = malloc(16LL * v5);\n v23 = v9;\n if (*a4 > 0) {\n v10 = v9;\n v11 = 4 * v4;\n v12 = 0;\n v13 = 0;\n v22 = v11;\n do {\n v14 = v13;\n v15 = a2;\n v19 = v13;\n v13 += a3;\n if (v13 <= a2) v15 = v13;\n v16 = v15 - v14;\n v17 = malloc(4LL * (v15 - v14));\n v10[2] = v16;\n *(uint64_t *)v10 = v17;\n if (v19 < v15) memcpy(v17, src, 4LL * (unsigned int)(v16 - 1) + 4);\n ++v12;\n v10 += 4;\n src += v22;\n } while (*a4 > v12);\n }\n return v23;\n}", + "ida_pseudo_norm": "void *func0(char *src, int a2, int a3, int *a4) {\n long long v4;\n int v5;\n void *v9;\n uint32_t *v10;\n long long v11;\n int v12;\n int v13;\n int v14;\n int v15;\n int v16;\n void *v17;\n int v19;\n long long v22;\n void *v23;\n v4 = a3;\n v5 = (a2 + a3 - 1) / a3;\n *a4 = v5;\n v9 = malloc(16LL * v5);\n v23 = v9;\n if (*a4 > 0) {\n v10 = v9;\n v11 = 4 * v4;\n v12 = 0;\n v13 = 0;\n v22 = v11;\n do {\n v14 = v13;\n v15 = a2;\n v19 = v13;\n v13 += a3;\n if (v13 <= a2) v15 = v13;\n v16 = v15 - v14;\n v17 = malloc(4LL * (v15 - v14));\n v10[2] = v16;\n *(uint64_t *)v10 = v17;\n if (v19 < v15) memcpy(v17, src, 4LL * (unsigned int)(v16 - 1) + 4);\n ++v12;\n v10 += 4;\n src += v22;\n } while (*a4 > v12);\n }\n return v23;\n}" + }, + { + "index": 921, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct\n\n{\n\n int *elements;\n\n int size;\n\n} tuple;\n\n\n\n", + "func": "tuple *func0(const int *test_tup, int tup_size, int N, int *num_chunks)\n{\n *num_chunks = (tup_size + N - 1) / N;\n tuple *res = malloc(*num_chunks * sizeof(tuple));\n for (int i = 0; i < *num_chunks; i++)\n {\n int start = i * N;\n int end = start + N < tup_size ? start + N : tup_size;\n int chunk_size = end - start;\n res[i].elements = malloc(chunk_size * sizeof(int));\n res[i].size = chunk_size;\n for (int j = start; j < end; j++)\n {\n res[i].elements[j - start] = test_tup[j];\n }\n }\n return res;\n}", + "test": "int main()\n\n{\n\n int test1[] = {10, 4, 5, 6, 7, 6, 8, 3, 4};\n\n int num_chunks1;\n\n tuple *chunks1 = func0(test1, sizeof(test1) / sizeof(test1[0]), 3, &num_chunks1);\n\n assert(num_chunks1 == 3 && chunks1[0].size == 3 && chunks1[1].size == 3 && chunks1[2].size == 3);\n\n free(chunks1);\n\n\n\n int test2[] = {1, 2, 3, 4, 5, 6, 7, 8, 9};\n\n int num_chunks2;\n\n tuple *chunks2 = func0(test2, sizeof(test2) / sizeof(test2[0]), 2, &num_chunks2);\n\n assert(num_chunks2 == 5 && chunks2[0].size == 2 && chunks2[4].size == 1);\n\n free(chunks2);\n\n\n\n int test3[] = {11, 14, 16, 17, 19, 21, 22, 25};\n\n int num_chunks3;\n\n tuple *chunks3 = func0(test3, sizeof(test3) / sizeof(test3[0]), 4, &num_chunks3);\n\n assert(num_chunks3 == 2 && chunks3[0].size == 4 && chunks3[1].size == 4);\n\n free(chunks3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nlea -0x1(%rsi,%rdx,1),%eax\nmov %edx,%r15d\npush %r14\npush %r13\npush %r12\nmov %rcx,%r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nsub $0x28,%rsp\nmov %edx,0x14(%rsp)\ncltd\nidiv %r15d\nmov %esi,0x10(%rsp)\nmov %eax,(%rcx)\nmovslq %eax,%rdi\nshl $0x4,%rdi\ncallq 10d0 \nmov (%r12),%edx\nmov %rax,0x18(%rsp)\ntest %edx,%edx\njle 148b \nmovslq %r15d,%r13\nmov %rax,%rbp\nxor %r14d,%r14d\nxor %r15d,%r15d\nlea 0x0(,%r13,4),%rax\nmov %rbx,%r13\nmov %rax,0x8(%rsp)\njmp 142f \nnopl 0x0(%rax,%rax,1)\nmov %r14d,%edx\nmov %r13,%rsi\nadd $0x1,%r15d\nadd $0x10,%rbp\nnot %edx\nlea (%rdx,%r9,1),%eax\nlea 0x4(,%rax,4),%rdx\ncallq 10c0 \nadd 0x8(%rsp),%r13\ncmp (%r12),%r15d\njge 148b \nmov %ebx,%r14d\nmov 0x14(%rsp),%eax\nlea (%rax,%r14,1),%ebx\nmov 0x10(%rsp),%eax\ncmp %eax,%ebx\nmov %eax,%r9d\ncmovle %ebx,%r9d\nmov %r9d,%r10d\nmov %r9d,0x4(%rsp)\nsub %r14d,%r10d\nmovslq %r10d,%rdi\nmov %r10d,(%rsp)\nshl $0x2,%rdi\ncallq 10d0 \nmov (%rsp),%r10d\nmov 0x4(%rsp),%r9d\nmov %rax,0x0(%rbp)\nmov %rax,%rdi\nmov %r10d,0x8(%rbp)\ncmp %r9d,%r14d\njl 1400 \nadd $0x1,%r15d\nadd $0x10,%rbp\nadd 0x8(%rsp),%r13\ncmp %r15d,(%r12)\njg 142c \nmov 0x18(%rsp),%rax\nadd $0x28,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\nlea eax, [rsi+rdx-1]\nmov r15d, edx\npush r14\nmov r14d, esi\npush r13\npush r12\nmov r12, rdi\npush rbp\nmov rbp, rcx\npush rbx\nsub rsp, 38h\nmov [rsp+68h+var_54], edx\ncdq\nidiv r15d\nmov [rsp+68h+var_50], rcx\nmov [rcx], eax\nmovsxd rdi, eax\nshl rdi, 4; size\ncall _malloc\nmov edx, [rbp+0]\nmov [rsp+68h+var_40], rax\ntest edx, edx\njle loc_1482\nmov rbx, rax\nmovsxd rax, r15d\nxor r13d, r13d\nxor r15d, r15d\nshl rax, 2\nmov [rsp+68h+var_48], rax\njmp short loc_1428\nloc_13F8:\nlea eax, [rcx-1]\nmov rsi, r12; src\nadd r13d, 1\nadd rbx, 10h\nlea rdx, ds:4[rax*4]; n\ncall _memcpy\nmov rax, [rsp+68h+var_48]\nadd r12, rax\nmov rax, [rsp+68h+var_50]\ncmp r13d, [rax]\njge short loc_1482\nloc_1425:\nmov r15d, ebp\nloc_1428:\nmov eax, [rsp+68h+var_54]\nmov esi, r14d\nlea ebp, [rax+r15]\ncmp ebp, r14d\ncmovle esi, ebp\nmov ecx, esi\nmov [rsp+68h+var_58], esi\nsub ecx, r15d\nmovsxd rdi, ecx\nmov [rsp+68h+var_5C], ecx\nshl rdi, 2; size\ncall _malloc\nmov ecx, [rsp+68h+var_5C]\nmov esi, [rsp+68h+var_58]\nmov [rbx], rax\nmov rdi, rax; dest\nmov [rbx+8], ecx\ncmp r15d, esi\njl short loc_13F8\nmov rax, [rsp+68h+var_48]\nadd r13d, 1\nadd rbx, 10h\nadd r12, rax\nmov rax, [rsp+68h+var_50]\ncmp [rax], r13d\njg short loc_1425\nloc_1482:\nmov rax, [rsp+68h+var_40]\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "void *__fastcall func0(char *src, int a2, int a3, int *a4)\n{\n int v8; // eax\n void *v9; // rax\n _DWORD *v10; // rbx\n __int64 v11; // rax\n int v12; // r13d\n int v13; // r15d\n int v14; // esi\n void *v15; // rax\n __int64 v19; // [rsp+20h] [rbp-48h]\n void *v20; // [rsp+28h] [rbp-40h]\n\n v8 = (a2 + a3 - 1) / a3;\n *a4 = v8;\n v9 = malloc(16LL * v8);\n v20 = v9;\n if ( *a4 > 0 )\n {\n v10 = v9;\n v11 = a3;\n v12 = 0;\n v13 = 0;\n v19 = 4 * v11;\n while ( 1 )\n {\n v14 = a2;\n if ( a3 + v13 <= a2 )\n v14 = a3 + v13;\n v15 = malloc(4LL * (v14 - v13));\n *(_QWORD *)v10 = v15;\n v10[2] = v14 - v13;\n if ( v13 < v14 )\n {\n ++v12;\n v10 += 4;\n memcpy(v15, src, 4LL * (unsigned int)(v14 - v13 - 1) + 4);\n src += v19;\n if ( v12 >= *a4 )\n return v20;\n }\n else\n {\n ++v12;\n v10 += 4;\n src += v19;\n if ( *a4 <= v12 )\n return v20;\n }\n v13 += a3;\n }\n }\n return v20;\n}", + "ida_strip_asm": "sub_1390:\nendbr64\npush r15\nlea eax, [rsi+rdx-1]\nmov r15d, edx\npush r14\nmov r14d, esi\npush r13\npush r12\nmov r12, rdi\npush rbp\nmov rbp, rcx\npush rbx\nsub rsp, 38h\nmov [rsp+68h+var_54], edx\ncdq\nidiv r15d\nmov [rsp+68h+var_50], rcx\nmov [rcx], eax\nmovsxd rdi, eax\nshl rdi, 4; size\ncall _malloc\nmov edx, [rbp+0]\nmov [rsp+68h+var_40], rax\ntest edx, edx\njle loc_1482\nmov rbx, rax\nmovsxd rax, r15d\nxor r13d, r13d\nxor r15d, r15d\nshl rax, 2\nmov [rsp+68h+var_48], rax\njmp short loc_1428\nloc_13F8:\nlea eax, [rcx-1]\nmov rsi, r12; src\nadd r13d, 1\nadd rbx, 10h\nlea rdx, ds:4[rax*4]; n\ncall _memcpy\nmov rax, [rsp+68h+var_48]\nadd r12, rax\nmov rax, [rsp+68h+var_50]\ncmp r13d, [rax]\njge short loc_1482\nloc_1425:\nmov r15d, ebp\nloc_1428:\nmov eax, [rsp+68h+var_54]\nmov esi, r14d\nlea ebp, [rax+r15]\ncmp ebp, r14d\ncmovle esi, ebp\nmov ecx, esi\nmov [rsp+68h+var_58], esi\nsub ecx, r15d\nmovsxd rdi, ecx\nmov [rsp+68h+var_5C], ecx\nshl rdi, 2; size\ncall _malloc\nmov ecx, [rsp+68h+var_5C]\nmov esi, [rsp+68h+var_58]\nmov [rbx], rax\nmov rdi, rax; dest\nmov [rbx+8], ecx\ncmp r15d, esi\njl short loc_13F8\nmov rax, [rsp+68h+var_48]\nadd r13d, 1\nadd rbx, 10h\nadd r12, rax\nmov rax, [rsp+68h+var_50]\ncmp [rax], r13d\njg short loc_1425\nloc_1482:\nmov rax, [rsp+68h+var_40]\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "void *__fastcall sub_1390(char *src, int a2, int a3, int *a4)\n{\n int v8; // eax\n void *v9; // rax\n _DWORD *v10; // rbx\n __int64 v11; // rax\n int v12; // r13d\n int v13; // r15d\n int v14; // esi\n void *v15; // rax\n __int64 v19; // [rsp+20h] [rbp-48h]\n void *v20; // [rsp+28h] [rbp-40h]\n\n v8 = (a2 + a3 - 1) / a3;\n *a4 = v8;\n v9 = malloc(16LL * v8);\n v20 = v9;\n if ( *a4 > 0 )\n {\n v10 = v9;\n v11 = a3;\n v12 = 0;\n v13 = 0;\n v19 = 4 * v11;\n while ( 1 )\n {\n v14 = a2;\n if ( a3 + v13 <= a2 )\n v14 = a3 + v13;\n v15 = malloc(4LL * (v14 - v13));\n *(_QWORD *)v10 = v15;\n v10[2] = v14 - v13;\n if ( v13 < v14 )\n {\n ++v12;\n v10 += 4;\n memcpy(v15, src, 4LL * (unsigned int)(v14 - v13 - 1) + 4);\n src += v19;\n if ( v12 >= *a4 )\n return v20;\n }\n else\n {\n ++v12;\n v10 += 4;\n src += v19;\n if ( *a4 <= v12 )\n return v20;\n }\n v13 += a3;\n }\n }\n return v20;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1390(char *src, int a2, int a3, int *a4) {\n int v8;\n void *v9;\n uint32_t *v10;\n long long v11;\n int v12;\n int v13;\n int v14;\n void *v15;\n long long v19;\n void *v20;\n v8 = (a2 + a3 - 1) / a3;\n *a4 = v8;\n v9 = malloc(16LL * v8);\n v20 = v9;\n if (*a4 > 0) {\n v10 = v9;\n v11 = a3;\n v12 = 0;\n v13 = 0;\n v19 = 4 * v11;\n while (1) {\n v14 = a2;\n if (a3 + v13 <= a2) v14 = a3 + v13;\n v15 = malloc(4LL * (v14 - v13));\n *(uint64_t *)v10 = v15;\n v10[2] = v14 - v13;\n if (v13 < v14) {\n ++v12;\n v10 += 4;\n memcpy(v15, src, 4LL * (unsigned int)(v14 - v13 - 1) + 4);\n src += v19;\n if (v12 >= *a4) return v20;\n } else {\n ++v12;\n v10 += 4;\n src += v19;\n if (*a4 <= v12) return v20;\n }\n v13 += a3;\n }\n }\n return v20;\n}", + "ida_pseudo_norm": "void *func0(char *src, int a2, int a3, int *a4) {\n int v8;\n void *v9;\n uint32_t *v10;\n long long v11;\n int v12;\n int v13;\n int v14;\n void *v15;\n long long v19;\n void *v20;\n v8 = (a2 + a3 - 1) / a3;\n *a4 = v8;\n v9 = malloc(16LL * v8);\n v20 = v9;\n if (*a4 > 0) {\n v10 = v9;\n v11 = a3;\n v12 = 0;\n v13 = 0;\n v19 = 4 * v11;\n while (1) {\n v14 = a2;\n if (a3 + v13 <= a2) v14 = a3 + v13;\n v15 = malloc(4LL * (v14 - v13));\n *(uint64_t *)v10 = v15;\n v10[2] = v14 - v13;\n if (v13 < v14) {\n ++v12;\n v10 += 4;\n memcpy(v15, src, 4LL * (unsigned int)(v14 - v13 - 1) + 4);\n src += v19;\n if (v12 >= *a4) return v20;\n } else {\n ++v12;\n v10 += 4;\n src += v19;\n if (*a4 <= v12) return v20;\n }\n v13 += a3;\n }\n }\n return v20;\n}" + }, + { + "index": 922, + "func_name": "func0", + "func_dep": "#include \n\n\n\n// Function to find max product pairs in an array\n\n", + "func": "void func0(int arr[], int arr_len, int *x, int *y) {\n if (arr_len < 2) {\n *x = 0;\n *y = 0;\n return;\n }\n *x = arr[0];\n *y = arr[1];\n for (int i = 0; i < arr_len; i++) {\n for (int j = i + 1; j < arr_len; j++) {\n if (arr[i] * arr[j] > (*x) * (*y)) {\n *x = arr[i];\n *y = arr[j];\n }\n }\n }\n}", + "test": "int main() {\n\n int x, y;\n\n\n\n // Test Case 1\n\n int arr1[] = {1, 2, 3, 4, 7, 0, 8, 4};\n\n func0(arr1, 8, &x, &y);\n\n assert(x == 7 && y == 8);\n\n\n\n // Test Case 2\n\n int arr2[] = {0, -1, -2, -4, 5, 0, -6};\n\n func0(arr2, 7, &x, &y);\n\n assert(x == -4 && y == -6);\n\n\n\n // Test Case 3\n\n int arr3[] = {1, 3, 5, 6, 8, 9};\n\n func0(arr3, 6, &x, &y);\n\n assert(x == 8 && y == 9);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %rcx,-0x30(%rbp)\ncmpl $0x1,-0x1c(%rbp)\njg 119f \nmov -0x28(%rbp),%rax\nmovl $0x0,(%rax)\nmov -0x30(%rbp),%rax\nmovl $0x0,(%rax)\njmpq 1269 \nmov -0x18(%rbp),%rax\nmov (%rax),%edx\nmov -0x28(%rbp),%rax\nmov %edx,(%rax)\nmov -0x18(%rbp),%rax\nmov 0x4(%rax),%edx\nmov -0x30(%rbp),%rax\nmov %edx,(%rax)\nmovl $0x0,-0x8(%rbp)\njmpq 125d \nmov -0x8(%rbp),%eax\nadd $0x1,%eax\nmov %eax,-0x4(%rbp)\njmp 124d \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\nimul %eax,%edx\nmov -0x28(%rbp),%rax\nmov (%rax),%ecx\nmov -0x30(%rbp),%rax\nmov (%rax),%eax\nimul %ecx,%eax\ncmp %eax,%edx\njle 1249 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x28(%rbp),%rax\nmov %edx,(%rax)\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x30(%rbp),%rax\nmov %edx,(%rax)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11cf \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11c4 \npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_30], rcx\ncmp [rbp+var_1C], 1\njg short loc_119F\nmov rax, [rbp+var_28]\nmov dword ptr [rax], 0\nmov rax, [rbp+var_30]\nmov dword ptr [rax], 0\njmp loc_126E\nloc_119F:\nmov rax, [rbp+var_18]\nmov edx, [rax]\nmov rax, [rbp+var_28]\nmov [rax], edx\nmov rax, [rbp+var_18]\nmov edx, [rax+4]\nmov rax, [rbp+var_30]\nmov [rax], edx\nmov [rbp+var_8], 0\njmp loc_1262\nloc_11C4:\nmov eax, [rbp+var_8]\nadd eax, 1\nmov [rbp+var_4], eax\njmp loc_1252\nloc_11D2:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nmov ecx, edx\nimul ecx, eax\nmov rax, [rbp+var_28]\nmov edx, [rax]\nmov rax, [rbp+var_30]\nmov eax, [rax]\nimul eax, edx\ncmp ecx, eax\njle short loc_124E\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_28]\nmov [rax], edx\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_30]\nmov [rax], edx\nloc_124E:\nadd [rbp+var_4], 1\nloc_1252:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl loc_11D2\nadd [rbp+var_8], 1\nloc_1262:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl loc_11C4\nloc_126E:\npop rbp\nretn", + "ida_pseudo": "unsigned __int64 __fastcall func0(_DWORD *a1, int a2, _DWORD *a3, _DWORD *a4)\n{\n unsigned __int64 result; // rax\n int i; // [rsp+28h] [rbp-8h]\n int j; // [rsp+2Ch] [rbp-4h]\n\n if ( a2 > 1 )\n {\n *a3 = *a1;\n *a4 = a1[1];\n for ( i = 0; ; ++i )\n {\n result = (unsigned int)i;\n if ( i >= a2 )\n break;\n for ( j = i + 1; j < a2; ++j )\n {\n if ( a1[j] * a1[i] > *a3 * *a4 )\n {\n *a3 = a1[i];\n *a4 = a1[j];\n }\n }\n }\n }\n else\n {\n *a3 = 0;\n result = (unsigned __int64)a4;\n *a4 = 0;\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_30], rcx\ncmp [rbp+var_1C], 1\njg short loc_119F\nmov rax, [rbp+var_28]\nmov dword ptr [rax], 0\nmov rax, [rbp+var_30]\nmov dword ptr [rax], 0\njmp loc_126E\nloc_119F:\nmov rax, [rbp+var_18]\nmov edx, [rax]\nmov rax, [rbp+var_28]\nmov [rax], edx\nmov rax, [rbp+var_18]\nmov edx, [rax+4]\nmov rax, [rbp+var_30]\nmov [rax], edx\nmov [rbp+var_8], 0\njmp loc_1262\nloc_11C4:\nmov eax, [rbp+var_8]\nadd eax, 1\nmov [rbp+var_4], eax\njmp loc_1252\nloc_11D2:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\nmov ecx, edx\nimul ecx, eax\nmov rax, [rbp+var_28]\nmov edx, [rax]\nmov rax, [rbp+var_30]\nmov eax, [rax]\nimul eax, edx\ncmp ecx, eax\njle short loc_124E\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_28]\nmov [rax], edx\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+var_30]\nmov [rax], edx\nloc_124E:\nadd [rbp+var_4], 1\nloc_1252:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl loc_11D2\nadd [rbp+var_8], 1\nloc_1262:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_1C]\njl loc_11C4\nloc_126E:\npop rbp\nretn", + "ida_strip_pseudo": "unsigned __int64 __fastcall sub_1169(_DWORD *a1, int a2, _DWORD *a3, _DWORD *a4)\n{\n unsigned __int64 result; // rax\n int i; // [rsp+28h] [rbp-8h]\n int j; // [rsp+2Ch] [rbp-4h]\n\n if ( a2 > 1 )\n {\n *a3 = *a1;\n *a4 = a1[1];\n for ( i = 0; ; ++i )\n {\n result = (unsigned int)i;\n if ( i >= a2 )\n break;\n for ( j = i + 1; j < a2; ++j )\n {\n if ( a1[j] * a1[i] > *a3 * *a4 )\n {\n *a3 = a1[i];\n *a4 = a1[j];\n }\n }\n }\n }\n else\n {\n *a3 = 0;\n result = (unsigned __int64)a4;\n *a4 = 0;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "unsigned long long sub_1169(uint32_t *a1, int a2, uint32_t *a3, uint32_t *a4) {\n unsigned long long result;\n int i;\n int j;\n if (a2 > 1) {\n *a3 = *a1;\n *a4 = a1[1];\n for (i = 0;; ++i) {\n result = (unsigned int)i;\n if (i >= a2) break;\n for (j = i + 1; j < a2; ++j) {\n if (a1[j] * a1[i] > *a3 * *a4) {\n *a3 = a1[i];\n *a4 = a1[j];\n }\n }\n }\n } else {\n *a3 = 0;\n result = (unsigned long long)a4;\n *a4 = 0;\n }\n return result;\n}", + "ida_pseudo_norm": "unsigned long long func0(uint32_t *a1, int a2, uint32_t *a3, uint32_t *a4) {\n unsigned long long result;\n int i;\n int j;\n if (a2 > 1) {\n *a3 = *a1;\n *a4 = a1[1];\n for (i = 0;; ++i) {\n result = (unsigned int)i;\n if (i >= a2) break;\n for (j = i + 1; j < a2; ++j) {\n if (a1[j] * a1[i] > *a3 * *a4) {\n *a3 = a1[i];\n *a4 = a1[j];\n }\n }\n }\n } else {\n *a3 = 0;\n result = (unsigned long long)a4;\n *a4 = 0;\n }\n return result;\n}" + }, + { + "index": 922, + "func_name": "func0", + "func_dep": "#include \n\n\n\n// Function to find max product pairs in an array\n\n", + "func": "void func0(int arr[], int arr_len, int *x, int *y) {\n if (arr_len < 2) {\n *x = 0;\n *y = 0;\n return;\n }\n *x = arr[0];\n *y = arr[1];\n for (int i = 0; i < arr_len; i++) {\n for (int j = i + 1; j < arr_len; j++) {\n if (arr[i] * arr[j] > (*x) * (*y)) {\n *x = arr[i];\n *y = arr[j];\n }\n }\n }\n}", + "test": "int main() {\n\n int x, y;\n\n\n\n // Test Case 1\n\n int arr1[] = {1, 2, 3, 4, 7, 0, 8, 4};\n\n func0(arr1, 8, &x, &y);\n\n assert(x == 7 && y == 8);\n\n\n\n // Test Case 2\n\n int arr2[] = {0, -1, -2, -4, 5, 0, -6};\n\n func0(arr2, 7, &x, &y);\n\n assert(x == -4 && y == -6);\n\n\n\n // Test Case 3\n\n int arr3[] = {1, 3, 5, 6, 8, 9};\n\n func0(arr3, 6, &x, &y);\n\n assert(x == 8 && y == 9);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%esi\njle 118e \npush %rbp\npush %rbx\nmov (%rdi),%eax\nmov %eax,(%rdx)\nmov 0x4(%rdi),%eax\nmov %eax,(%rcx)\nmov $0x0,%ebx\nmov $0x1,%ebp\nmov $0x1,%eax\njmp 11a2 \nmovl $0x0,(%rdx)\nmovl $0x0,(%rcx)\nretq\nadd $0x1,%eax\ncmp %eax,%esi\njle 11ce \nmovslq %ebx,%r8\nmov (%rdi,%r8,4),%r10d\nmovslq %eax,%r8\nlea (%rdi,%r8,4),%r9\nmov %r10d,%r11d\nimul (%r9),%r11d\nmov (%rdx),%r8d\nimul (%rcx),%r8d\ncmp %r8d,%r11d\njle 119b \nmov %r10d,(%rdx)\nmov (%r9),%r8d\nmov %r8d,(%rcx)\njmp 119b \nlea 0x1(%rbp),%eax\ncmp %eax,%esi\njle 11db \nmov %ebp,%ebx\nmov %eax,%ebp\njmp 11a2 \npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nmov rbp, rdi\nmov r8, rdx\nmov rdi, rcx\ncmp esi, 1\njle short loc_11A5\nmov eax, [rbp+0]\nmov [rdx], eax\nmov eax, [rbp+4]\nmov [rcx], eax\nlea r9, [rbp+4]\nlea r13d, [rsi-1]\nmov r12d, esi\nmovsxd rbx, esi\nmov r11d, 1\nadd rbp, 8\njmp short loc_11ED\nloc_11A5:\nmov dword ptr [rdx], 0\nmov dword ptr [rcx], 0\nloc_11B1:\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_11B8:\nadd rax, 4\ncmp rax, r10\njz short loc_11DD\nloc_11C1:\nmov ecx, [r9-4]\nmov esi, ecx\nimul esi, [rax]\nmov edx, [r8]\nimul edx, [rdi]\ncmp esi, edx\njle short loc_11B8\nmov [r8], ecx\nmov edx, [rax]\nmov [rdi], edx\njmp short loc_11B8\nloc_11DD:\nlea rax, [r11+1]\nadd r9, 4\ncmp r11, rbx\njz short loc_11B1\nmov r11, rax\nloc_11ED:\ncmp r11, r12\njz short loc_11B1\nmov eax, r13d\nsub eax, r11d\nlea rax, [r11+rax-1]\nlea r10, [rbp+rax*4+0]\nmov rax, r9\njmp short loc_11C1", + "ida_pseudo": "void __fastcall func0(_DWORD *a1, int a2, _DWORD *a3, _DWORD *a4)\n{\n _DWORD *v4; // r9\n __int64 i; // r11\n _DWORD *v6; // rax\n\n if ( a2 <= 1 )\n {\n *a3 = 0;\n *a4 = 0;\n }\n else\n {\n *a3 = *a1;\n *a4 = a1[1];\n v4 = a1 + 1;\n for ( i = 1LL; i != a2; ++i )\n {\n v6 = v4;\n do\n {\n if ( *v6 * *(v4 - 1) > *a4 * *a3 )\n {\n *a3 = *(v4 - 1);\n *a4 = *v6;\n }\n ++v6;\n }\n while ( v6 != &a1[i + 1 + (unsigned int)(a2 - 1 - i)] );\n ++v4;\n if ( i == a2 )\n break;\n }\n }\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nmov rbp, rdi\nmov r8, rdx\nmov rdi, rcx\ncmp esi, 1\njle short loc_11A5\nmov eax, [rbp+0]\nmov [rdx], eax\nmov eax, [rbp+4]\nmov [rcx], eax\nlea r9, [rbp+4]\nlea r13d, [rsi-1]\nmov r12d, esi\nmovsxd rbx, esi\nmov r11d, 1\nadd rbp, 8\njmp short loc_11ED\nloc_11A5:\nmov dword ptr [rdx], 0\nmov dword ptr [rcx], 0\nloc_11B1:\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_11B8:\nadd rax, 4\ncmp rax, r10\njz short loc_11DD\nloc_11C1:\nmov ecx, [r9-4]\nmov esi, ecx\nimul esi, [rax]\nmov edx, [r8]\nimul edx, [rdi]\ncmp esi, edx\njle short loc_11B8\nmov [r8], ecx\nmov edx, [rax]\nmov [rdi], edx\njmp short loc_11B8\nloc_11DD:\nlea rax, [r11+1]\nadd r9, 4\ncmp r11, rbx\njz short loc_11B1\nmov r11, rax\nloc_11ED:\ncmp r11, r12\njz short loc_11B1\nmov eax, r13d\nsub eax, r11d\nlea rax, [r11+rax-1]\nlea r10, [rbp+rax*4+0]\nmov rax, r9\njmp short loc_11C1", + "ida_strip_pseudo": "void __fastcall sub_1169(_DWORD *a1, int a2, _DWORD *a3, _DWORD *a4)\n{\n _DWORD *v4; // r9\n __int64 i; // r11\n _DWORD *v6; // rax\n\n if ( a2 <= 1 )\n {\n *a3 = 0;\n *a4 = 0;\n }\n else\n {\n *a3 = *a1;\n *a4 = a1[1];\n v4 = a1 + 1;\n for ( i = 1LL; i != a2; ++i )\n {\n v6 = v4;\n do\n {\n if ( *v6 * *(v4 - 1) > *a4 * *a3 )\n {\n *a3 = *(v4 - 1);\n *a4 = *v6;\n }\n ++v6;\n }\n while ( v6 != &a1[i + 1 + (unsigned int)(a2 - 1 - i)] );\n ++v4;\n if ( i == a2 )\n break;\n }\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1169(uint32_t *a1, int a2, uint32_t *a3, uint32_t *a4) {\n uint32_t *v4;\n long long i;\n uint32_t *v6;\n if (a2 <= 1) {\n *a3 = 0;\n *a4 = 0;\n } else {\n *a3 = *a1;\n *a4 = a1[1];\n v4 = a1 + 1;\n for (i = 1LL; i != a2; ++i) {\n v6 = v4;\n do {\n if (*v6 * *(v4 - 1) > *a4 * *a3) {\n *a3 = *(v4 - 1);\n *a4 = *v6;\n }\n ++v6;\n } while (v6 != &a1[i + 1 + (unsigned int)(a2 - 1 - i)]);\n ++v4;\n if (i == a2) break;\n }\n }\n}", + "ida_pseudo_norm": "void func0(uint32_t *a1, int a2, uint32_t *a3, uint32_t *a4) {\n uint32_t *v4;\n long long i;\n uint32_t *v6;\n if (a2 <= 1) {\n *a3 = 0;\n *a4 = 0;\n } else {\n *a3 = *a1;\n *a4 = a1[1];\n v4 = a1 + 1;\n for (i = 1LL; i != a2; ++i) {\n v6 = v4;\n do {\n if (*v6 * *(v4 - 1) > *a4 * *a3) {\n *a3 = *(v4 - 1);\n *a4 = *v6;\n }\n ++v6;\n } while (v6 != &a1[i + 1 + (unsigned int)(a2 - 1 - i)]);\n ++v4;\n if (i == a2) break;\n }\n }\n}" + }, + { + "index": 922, + "func_name": "func0", + "func_dep": "#include \n\n\n\n// Function to find max product pairs in an array\n\n", + "func": "void func0(int arr[], int arr_len, int *x, int *y) {\n if (arr_len < 2) {\n *x = 0;\n *y = 0;\n return;\n }\n *x = arr[0];\n *y = arr[1];\n for (int i = 0; i < arr_len; i++) {\n for (int j = i + 1; j < arr_len; j++) {\n if (arr[i] * arr[j] > (*x) * (*y)) {\n *x = arr[i];\n *y = arr[j];\n }\n }\n }\n}", + "test": "int main() {\n\n int x, y;\n\n\n\n // Test Case 1\n\n int arr1[] = {1, 2, 3, 4, 7, 0, 8, 4};\n\n func0(arr1, 8, &x, &y);\n\n assert(x == 7 && y == 8);\n\n\n\n // Test Case 2\n\n int arr2[] = {0, -1, -2, -4, 5, 0, -6};\n\n func0(arr2, 7, &x, &y);\n\n assert(x == -4 && y == -6);\n\n\n\n // Test Case 3\n\n int arr3[] = {1, 3, 5, 6, 8, 9};\n\n func0(arr3, 6, &x, &y);\n\n assert(x == 8 && y == 9);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%esi\njle 13d0 \nmov (%rdi),%eax\nmov %eax,(%rdx)\nmov 0x4(%rdi),%eax\nmov %eax,(%rcx)\njmpq 1340 \nnopw 0x0(%rax,%rax,1)\nmovl $0x0,(%rdx)\nmovl $0x0,(%rcx)\nretq\nnopl (%rax)\n", + "ida_asm": "func0_part_0:\ntest esi, esi\njle short locret_135E\npush rbp\nmov r9, rdi\nmov r11d, esi\nmov r10, rdi\npush rbx\nmov ebp, esi\nmov ebx, 1\ncmp esi, 1\njz short loc_135B\nnop dword ptr [rax+rax+00h]\nloc_1320:\nmov rax, rbx\nnop dword ptr [rax+rax+00h]\nloc_1328:\nmov edi, [r10]\nmov r8d, [r9+rax*4]\nmov esi, [rdx]\nimul esi, [rcx]\nimul r8d, edi\ncmp r8d, esi\njle short loc_1345\nmov [rdx], edi\nmov esi, [r9+rax*4]\nmov [rcx], esi\nloc_1345:\nadd rax, 1\ncmp r11d, eax\njg short loc_1328\nadd rbx, 1\nadd r10, 4\ncmp rbx, rbp\njnz short loc_1320\nloc_135B:\npop rbx\npop rbp\nretn\nlocret_135E:\nretn", + "ida_pseudo": "void __fastcall func0_part_0(_DWORD *a1, int a2, _DWORD *a3, _DWORD *a4)\n{\n _DWORD *v4; // r10\n __int64 v5; // rbx\n __int64 v6; // rax\n\n if ( a2 > 0 )\n {\n v4 = a1;\n v5 = 1LL;\n if ( a2 != 1 )\n {\n do\n {\n v6 = v5;\n do\n {\n if ( *v4 * a1[v6] > *a4 * *a3 )\n {\n *a3 = *v4;\n *a4 = a1[v6];\n }\n ++v6;\n }\n while ( a2 > (int)v6 );\n ++v5;\n ++v4;\n }\n while ( v5 != a2 );\n }\n }\n}", + "ida_strip_asm": "sub_1300:\ntest esi, esi\njle short locret_135E\npush rbp\nmov r9, rdi\nmov r11d, esi\nmov r10, rdi\npush rbx\nmov ebp, esi\nmov ebx, 1\ncmp esi, 1\njz short loc_135B\nnop dword ptr [rax+rax+00h]\nloc_1320:\nmov rax, rbx\nnop dword ptr [rax+rax+00h]\nloc_1328:\nmov edi, [r10]\nmov r8d, [r9+rax*4]\nmov esi, [rdx]\nimul esi, [rcx]\nimul r8d, edi\ncmp r8d, esi\njle short loc_1345\nmov [rdx], edi\nmov esi, [r9+rax*4]\nmov [rcx], esi\nloc_1345:\nadd rax, 1\ncmp r11d, eax\njg short loc_1328\nadd rbx, 1\nadd r10, 4\ncmp rbx, rbp\njnz short loc_1320\nloc_135B:\npop rbx\npop rbp\nretn\nlocret_135E:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1300(_DWORD *a1, int a2, _DWORD *a3, _DWORD *a4)\n{\n _DWORD *v4; // r10\n __int64 v5; // rbx\n __int64 v6; // rax\n\n if ( a2 > 0 )\n {\n v4 = a1;\n v5 = 1LL;\n if ( a2 != 1 )\n {\n do\n {\n v6 = v5;\n do\n {\n if ( *v4 * a1[v6] > *a4 * *a3 )\n {\n *a3 = *v4;\n *a4 = a1[v6];\n }\n ++v6;\n }\n while ( a2 > (int)v6 );\n ++v5;\n ++v4;\n }\n while ( v5 != a2 );\n }\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1300(uint32_t *a1, int a2, uint32_t *a3, uint32_t *a4) {\n uint32_t *v4;\n long long v5;\n long long v6;\n if (a2 > 0) {\n v4 = a1;\n v5 = 1LL;\n if (a2 != 1) {\n do {\n v6 = v5;\n do {\n if (*v4 * a1[v6] > *a4 * *a3) {\n *a3 = *v4;\n *a4 = a1[v6];\n }\n ++v6;\n } while (a2 > (int)v6);\n ++v5;\n ++v4;\n } while (v5 != a2);\n }\n }\n}", + "ida_pseudo_norm": "void func0_part_0(uint32_t *a1, int a2, uint32_t *a3, uint32_t *a4) {\n uint32_t *v4;\n long long v5;\n long long v6;\n if (a2 > 0) {\n v4 = a1;\n v5 = 1LL;\n if (a2 != 1) {\n do {\n v6 = v5;\n do {\n if (*v4 * a1[v6] > *a4 * *a3) {\n *a3 = *v4;\n *a4 = a1[v6];\n }\n ++v6;\n } while (a2 > (int)v6);\n ++v5;\n ++v4;\n } while (v5 != a2);\n }\n }\n}" + }, + { + "index": 922, + "func_name": "func0", + "func_dep": "#include \n\n\n\n// Function to find max product pairs in an array\n\n", + "func": "void func0(int arr[], int arr_len, int *x, int *y) {\n if (arr_len < 2) {\n *x = 0;\n *y = 0;\n return;\n }\n *x = arr[0];\n *y = arr[1];\n for (int i = 0; i < arr_len; i++) {\n for (int j = i + 1; j < arr_len; j++) {\n if (arr[i] * arr[j] > (*x) * (*y)) {\n *x = arr[i];\n *y = arr[j];\n }\n }\n }\n}", + "test": "int main() {\n\n int x, y;\n\n\n\n // Test Case 1\n\n int arr1[] = {1, 2, 3, 4, 7, 0, 8, 4};\n\n func0(arr1, 8, &x, &y);\n\n assert(x == 7 && y == 8);\n\n\n\n // Test Case 2\n\n int arr2[] = {0, -1, -2, -4, 5, 0, -6};\n\n func0(arr2, 7, &x, &y);\n\n assert(x == -4 && y == -6);\n\n\n\n // Test Case 3\n\n int arr3[] = {1, 3, 5, 6, 8, 9};\n\n func0(arr3, 6, &x, &y);\n\n assert(x == 8 && y == 9);\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\nmov %rcx,%rbp\npush %rbx\nmov %esi,%ebx\nmov %rdx,%rsi\ncmp $0x1,%ebx\njle 13f0 \nmov (%rdi),%eax\nmov $0x1,%r12d\nmov %eax,(%rdx)\nmov 0x4(%rdi),%r10d\nmov $0x1,%eax\nmov %r10d,(%rcx)\nxor %ecx,%ecx\nnopl (%rax)\nmovslq %eax,%r8\nmov (%rdi,%rcx,4),%r9d\nmov (%rsi),%r11d\nlea (%rdi,%r8,4),%r8\nmov (%r8),%edx\nimul %r10d,%r11d\nimul %r9d,%edx\ncmp %r11d,%edx\njle 13d8 \nmov %r9d,(%rsi)\nmov (%r8),%r10d\nmov %r10d,0x0(%rbp)\nadd $0x1,%eax\ncmp %eax,%ebx\njg 13b0 \nlea 0x1(%r12),%eax\ncmp %eax,%ebx\njle 13fc \nmovslq %r12d,%rcx\nmov %eax,%r12d\njmp 13b0 \nmovl $0x0,(%rdx)\nmovl $0x0,(%rcx)\npop %rbx\npop %rbp\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0_part_0:\ntest esi, esi\njle short locret_1361\npush r12\nmov r10, rdi\nmov r11, rdi\nmov r12d, esi\npush rbp\nmov ebp, 1\npush rbx\nmov ebx, esi\ncmp esi, 1\njz short loc_135C\nnop dword ptr [rax]\nloc_1320:\nmov edi, [rcx]\nmov rax, rbp\nnop dword ptr [rax]\nloc_1328:\nmov esi, [r11]\nmov r9d, [r10+rax*4]\nmov r8d, [rdx]\nimul r9d, esi\nimul r8d, edi\ncmp r9d, r8d\njle short loc_1347\nmov [rdx], esi\nmov edi, [r10+rax*4]\nmov [rcx], edi\nloc_1347:\nadd rax, 1\ncmp ebx, eax\njg short loc_1328\nadd rbp, 1\nadd r11, 4\ncmp r12, rbp\njnz short loc_1320\nloc_135C:\npop rbx\npop rbp\npop r12\nretn\nlocret_1361:\nretn", + "ida_pseudo": "void __fastcall func0_part_0(_DWORD *a1, int a2, _DWORD *a3, int *a4)\n{\n _DWORD *v5; // r11\n __int64 v6; // rbp\n int v7; // edi\n __int64 v8; // rax\n\n if ( a2 > 0 )\n {\n v5 = a1;\n v6 = 1LL;\n if ( a2 != 1 )\n {\n do\n {\n v7 = *a4;\n v8 = v6;\n do\n {\n if ( *v5 * a1[v8] > v7 * *a3 )\n {\n *a3 = *v5;\n v7 = a1[v8];\n *a4 = v7;\n }\n ++v8;\n }\n while ( a2 > (int)v8 );\n ++v6;\n ++v5;\n }\n while ( a2 != v6 );\n }\n }\n}", + "ida_strip_asm": "sub_1300:\ntest esi, esi\njle short locret_1361\npush r12\nmov r10, rdi\nmov r11, rdi\nmov r12d, esi\npush rbp\nmov ebp, 1\npush rbx\nmov ebx, esi\ncmp esi, 1\njz short loc_135C\nnop dword ptr [rax]\nloc_1320:\nmov edi, [rcx]\nmov rax, rbp\nnop dword ptr [rax]\nloc_1328:\nmov esi, [r11]\nmov r9d, [r10+rax*4]\nmov r8d, [rdx]\nimul r9d, esi\nimul r8d, edi\ncmp r9d, r8d\njle short loc_1347\nmov [rdx], esi\nmov edi, [r10+rax*4]\nmov [rcx], edi\nloc_1347:\nadd rax, 1\ncmp ebx, eax\njg short loc_1328\nadd rbp, 1\nadd r11, 4\ncmp r12, rbp\njnz short loc_1320\nloc_135C:\npop rbx\npop rbp\npop r12\nretn\nlocret_1361:\nretn", + "ida_strip_pseudo": "void __fastcall sub_1300(_DWORD *a1, int a2, _DWORD *a3, int *a4)\n{\n _DWORD *v5; // r11\n __int64 v6; // rbp\n int v7; // edi\n __int64 v8; // rax\n\n if ( a2 > 0 )\n {\n v5 = a1;\n v6 = 1LL;\n if ( a2 != 1 )\n {\n do\n {\n v7 = *a4;\n v8 = v6;\n do\n {\n if ( *v5 * a1[v8] > v7 * *a3 )\n {\n *a3 = *v5;\n v7 = a1[v8];\n *a4 = v7;\n }\n ++v8;\n }\n while ( a2 > (int)v8 );\n ++v6;\n ++v5;\n }\n while ( a2 != v6 );\n }\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1300(uint32_t *a1, int a2, uint32_t *a3, int *a4) {\n uint32_t *v5;\n long long v6;\n int v7;\n long long v8;\n if (a2 > 0) {\n v5 = a1;\n v6 = 1LL;\n if (a2 != 1) {\n do {\n v7 = *a4;\n v8 = v6;\n do {\n if (*v5 * a1[v8] > v7 * *a3) {\n *a3 = *v5;\n v7 = a1[v8];\n *a4 = v7;\n }\n ++v8;\n } while (a2 > (int)v8);\n ++v6;\n ++v5;\n } while (a2 != v6);\n }\n }\n}", + "ida_pseudo_norm": "void func0_part_0(uint32_t *a1, int a2, uint32_t *a3, int *a4) {\n uint32_t *v5;\n long long v6;\n int v7;\n long long v8;\n if (a2 > 0) {\n v5 = a1;\n v6 = 1LL;\n if (a2 != 1) {\n do {\n v7 = *a4;\n v8 = v6;\n do {\n if (*v5 * a1[v8] > v7 * *a3) {\n *a3 = *v5;\n v7 = a1[v8];\n *a4 = v7;\n }\n ++v8;\n } while (a2 > (int)v8);\n ++v6;\n ++v5;\n } while (a2 != v6);\n }\n }\n}" + }, + { + "index": 923, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *X, const char *Y, int m, int n) {\n if (!m) return n;\n if (!n) return m;\n if (X[m - 1] == Y[n - 1]) return 1 + func0(X, Y, m - 1, n - 1);\n int left = func0(X, Y, m - 1, n);\n int right = func0(X, Y, m, n - 1);\n return 1 + (left < right ? left : right);\n}", + "test": "int main() {\n\n assert(func0(\"AGGTAB\", \"GXTXAYB\", 6, 7) == 9);\n\n assert(func0(\"feek\", \"eke\", 4, 3) == 5);\n\n assert(func0(\"PARRT\", \"RTA\", 5, 3) == 6);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %edx,-0x24(%rbp)\nmov %ecx,-0x28(%rbp)\ncmpl $0x0,-0x24(%rbp)\njne 1171 \nmov -0x28(%rbp),%eax\njmpq 1213 \ncmpl $0x0,-0x28(%rbp)\njne 117f \nmov -0x24(%rbp),%eax\njmpq 1213 \nmov -0x24(%rbp),%eax\ncltq\nlea -0x1(%rax),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%edx\nmov -0x28(%rbp),%eax\ncltq\nlea -0x1(%rax),%rcx\nmov -0x20(%rbp),%rax\nadd %rcx,%rax\nmovzbl (%rax),%eax\ncmp %al,%dl\njne 11ca \nmov -0x28(%rbp),%eax\nlea -0x1(%rax),%ecx\nmov -0x24(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x20(%rbp),%rsi\nmov -0x18(%rbp),%rax\nmov %rax,%rdi\ncallq 1149 \nadd $0x1,%eax\njmp 1213 \nmov -0x24(%rbp),%eax\nlea -0x1(%rax),%edi\nmov -0x28(%rbp),%edx\nmov -0x20(%rbp),%rsi\nmov -0x18(%rbp),%rax\nmov %edx,%ecx\nmov %edi,%edx\nmov %rax,%rdi\ncallq 1149 \nmov %eax,-0x8(%rbp)\nmov -0x28(%rbp),%eax\nlea -0x1(%rax),%ecx\nmov -0x24(%rbp),%edx\nmov -0x20(%rbp),%rsi\nmov -0x18(%rbp),%rax\nmov %rax,%rdi\ncallq 1149 \nmov %eax,-0x4(%rbp)\nmov -0x8(%rbp),%eax\ncmp %eax,-0x4(%rbp)\ncmovle -0x4(%rbp),%eax\nadd $0x1,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_28], ecx\ncmp [rbp+var_24], 0\njnz short loc_1171\nmov eax, [rbp+var_28]\njmp locret_1214\nloc_1171:\ncmp [rbp+var_28], 0\njnz short loc_117F\nmov eax, [rbp+var_24]\njmp locret_1214\nloc_117F:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_28]\ncdqe\nlea rcx, [rax-1]\nmov rax, [rbp+var_20]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njnz short loc_11CA\nmov eax, [rbp+var_28]\nlea ecx, [rax-1]\nmov eax, [rbp+var_24]\nlea edx, [rax-1]\nmov rsi, [rbp+var_20]\nmov rax, [rbp+var_18]\nmov rdi, rax\ncall func0\nadd eax, 1\njmp short locret_1214\nloc_11CA:\nmov eax, [rbp+var_24]\nlea edi, [rax-1]\nmov edx, [rbp+var_28]\nmov rsi, [rbp+var_20]\nmov rax, [rbp+var_18]\nmov ecx, edx\nmov edx, edi\nmov rdi, rax\ncall func0\nmov [rbp+var_8], eax\nmov eax, [rbp+var_28]\nlea ecx, [rax-1]\nmov edx, [rbp+var_24]\nmov rsi, [rbp+var_20]\nmov rax, [rbp+var_18]\nmov rdi, rax\ncall func0\nmov [rbp+var_4], eax\nmov edx, [rbp+var_4]\nmov eax, [rbp+var_8]\ncmp edx, eax\ncmovle eax, edx\nadd eax, 1\nlocret_1214:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, unsigned int a3, unsigned int a4)\n{\n int v5; // edx\n int v6; // eax\n int v9; // [rsp+28h] [rbp-8h]\n\n if ( !a3 )\n return a4;\n if ( !a4 )\n return a3;\n if ( *(_BYTE *)((int)a3 - 1LL + a1) == *(_BYTE *)((int)a4 - 1LL + a2) )\n return (unsigned int)func0(a1, a2, a3 - 1, a4 - 1) + 1;\n v9 = func0(a1, a2, a3 - 1, a4);\n v5 = func0(a1, a2, a3, a4 - 1);\n v6 = v9;\n if ( v5 <= v9 )\n v6 = v5;\n return (unsigned int)(v6 + 1);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_28], ecx\ncmp [rbp+var_24], 0\njnz short loc_1171\nmov eax, [rbp+var_28]\njmp locret_1214\nloc_1171:\ncmp [rbp+var_28], 0\njnz short loc_117F\nmov eax, [rbp+var_24]\njmp locret_1214\nloc_117F:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_28]\ncdqe\nlea rcx, [rax-1]\nmov rax, [rbp+var_20]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\ncmp dl, al\njnz short loc_11CA\nmov eax, [rbp+var_28]\nlea ecx, [rax-1]\nmov eax, [rbp+var_24]\nlea edx, [rax-1]\nmov rsi, [rbp+var_20]\nmov rax, [rbp+var_18]\nmov rdi, rax\ncall sub_1149\nadd eax, 1\njmp short locret_1214\nloc_11CA:\nmov eax, [rbp+var_24]\nlea edi, [rax-1]\nmov edx, [rbp+var_28]\nmov rsi, [rbp+var_20]\nmov rax, [rbp+var_18]\nmov ecx, edx\nmov edx, edi\nmov rdi, rax\ncall sub_1149\nmov [rbp+var_8], eax\nmov eax, [rbp+var_28]\nlea ecx, [rax-1]\nmov edx, [rbp+var_24]\nmov rsi, [rbp+var_20]\nmov rax, [rbp+var_18]\nmov rdi, rax\ncall sub_1149\nmov [rbp+var_4], eax\nmov edx, [rbp+var_4]\nmov eax, [rbp+var_8]\ncmp edx, eax\ncmovle eax, edx\nadd eax, 1\nlocret_1214:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(__int64 a1, __int64 a2, unsigned int a3, unsigned int a4)\n{\n int v5; // edx\n int v6; // eax\n int v9; // [rsp+28h] [rbp-8h]\n\n if ( !a3 )\n return a4;\n if ( !a4 )\n return a3;\n if ( *(_BYTE *)((int)a3 - 1LL + a1) == *(_BYTE *)((int)a4 - 1LL + a2) )\n return (unsigned int)sub_1149(a1, a2, a3 - 1, a4 - 1) + 1;\n v9 = sub_1149(a1, a2, a3 - 1, a4);\n v5 = sub_1149(a1, a2, a3, a4 - 1);\n v6 = v9;\n if ( v5 <= v9 )\n v6 = v5;\n return (unsigned int)(v6 + 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(long long a1, long long a2, unsigned int a3,\n unsigned int a4) {\n int v5;\n int v6;\n int v9;\n if (!a3) return a4;\n if (!a4) return a3;\n if (*(uint8_t *)((int)a3 - 1LL + a1) == *(uint8_t *)((int)a4 - 1LL + a2))\n return (unsigned int)sub_1149(a1, a2, a3 - 1, a4 - 1) + 1;\n v9 = sub_1149(a1, a2, a3 - 1, a4);\n v5 = sub_1149(a1, a2, a3, a4 - 1);\n v6 = v9;\n if (v5 <= v9) v6 = v5;\n return (unsigned int)(v6 + 1);\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, unsigned int a3, unsigned int a4) {\n int v5;\n int v6;\n int v9;\n if (!a3) return a4;\n if (!a4) return a3;\n if (*(uint8_t *)((int)a3 - 1LL + a1) == *(uint8_t *)((int)a4 - 1LL + a2))\n return (unsigned int)func0(a1, a2, a3 - 1, a4 - 1) + 1;\n v9 = func0(a1, a2, a3 - 1, a4);\n v5 = func0(a1, a2, a3, a4 - 1);\n v6 = v9;\n if (v5 <= v9) v6 = v5;\n return (unsigned int)(v6 + 1);\n}" + }, + { + "index": 923, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *X, const char *Y, int m, int n) {\n if (!m) return n;\n if (!n) return m;\n if (X[m - 1] == Y[n - 1]) return 1 + func0(X, Y, m - 1, n - 1);\n int left = func0(X, Y, m - 1, n);\n int right = func0(X, Y, m, n - 1);\n return 1 + (left < right ? left : right);\n}", + "test": "int main() {\n\n assert(func0(\"AGGTAB\", \"GXTXAYB\", 6, 7) == 9);\n\n assert(func0(\"feek\", \"eke\", 4, 3) == 5);\n\n assert(func0(\"PARRT\", \"RTA\", 5, 3) == 6);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %ecx,%eax\ntest %edx,%edx\nje 11c1 \npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%r13\nmov %rsi,%r14\nmov %edx,%ebp\nmov %ecx,%ebx\nmov %edx,%eax\ntest %ecx,%ecx\nje 11a5 \nmovslq %edx,%rax\nmovslq %ecx,%rdx\nmovzbl -0x1(%rsi,%rdx,1),%esi\ncmp %sil,-0x1(%rdi,%rax,1)\nje 11ae \nlea -0x1(%rbp),%edx\nmov %r14,%rsi\ncallq 1149 \nmov %eax,%r12d\nlea -0x1(%rbx),%ecx\nmov %ebp,%edx\nmov %r14,%rsi\nmov %r13,%rdi\ncallq 1149 \ncmp %eax,%r12d\ncmovle %r12d,%eax\nadd $0x1,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\nlea -0x1(%rcx),%ecx\nlea -0x1(%rbp),%edx\nmov %r14,%rsi\ncallq 1149 \nadd $0x1,%eax\njmp 11a5 \nretq\n", + "ida_asm": "func0:\nendbr64\nmov eax, ecx\ntest edx, edx\njz short locret_11C1\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r13, rdi\nmov r14, rsi\nmov ebp, edx\nmov ebx, ecx\nmov eax, edx\ntest ecx, ecx\njz short loc_11A5\nmovsxd rax, edx\nmovsxd rdx, ecx\nmovzx esi, byte ptr [rsi+rdx-1]\ncmp [rdi+rax-1], sil\njz short loc_11AE\nlea edx, [rbp-1]\nmov rsi, r14\ncall func0\nmov r12d, eax\nlea ecx, [rbx-1]\nmov edx, ebp\nmov rsi, r14\nmov rdi, r13\ncall func0\ncmp r12d, eax\ncmovle eax, r12d\nadd eax, 1\nloc_11A5:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_11AE:\nlea ecx, [rcx-1]\nlea edx, [rbp-1]\nmov rsi, r14\ncall func0\nadd eax, 1\njmp short loc_11A5\nlocret_11C1:\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, unsigned int a3, __int64 a4)\n{\n __int64 result; // rax\n int v6; // ebx\n int v7; // r12d\n int v8; // eax\n\n result = (unsigned int)a4;\n if ( a3 )\n {\n v6 = a4;\n result = a3;\n if ( (_DWORD)a4 )\n {\n if ( *(_BYTE *)(a1 + (int)a3 - 1) == *(_BYTE *)(a2 + (int)a4 - 1) )\n {\n return (unsigned int)func0(a1, a2, a3 - 1, (unsigned int)(a4 - 1)) + 1;\n }\n else\n {\n v7 = func0(a1, a2, a3 - 1, a4);\n v8 = func0(a1, a2, a3, (unsigned int)(v6 - 1));\n if ( v7 <= v8 )\n v8 = v7;\n return (unsigned int)(v8 + 1);\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\nmov eax, ecx\ntest edx, edx\njz short locret_11C1\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r13, rdi\nmov r14, rsi\nmov ebp, edx\nmov ebx, ecx\nmov eax, edx\ntest ecx, ecx\njz short loc_11A5\nmovsxd rax, edx\nmovsxd rdx, ecx\nmovzx esi, byte ptr [rsi+rdx-1]\ncmp [rdi+rax-1], sil\njz short loc_11AE\nlea edx, [rbp-1]\nmov rsi, r14\ncall sub_1149\nmov r12d, eax\nlea ecx, [rbx-1]\nmov edx, ebp\nmov rsi, r14\nmov rdi, r13\ncall sub_1149\ncmp r12d, eax\ncmovle eax, r12d\nadd eax, 1\nloc_11A5:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_11AE:\nlea ecx, [rcx-1]\nlea edx, [rbp-1]\nmov rsi, r14\ncall sub_1149\nadd eax, 1\njmp short loc_11A5\nlocret_11C1:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(__int64 a1, __int64 a2, unsigned int a3, __int64 a4)\n{\n __int64 result; // rax\n int v6; // ebx\n int v7; // r12d\n int v8; // eax\n\n result = (unsigned int)a4;\n if ( a3 )\n {\n v6 = a4;\n result = a3;\n if ( (_DWORD)a4 )\n {\n if ( *(_BYTE *)(a1 + (int)a3 - 1) == *(_BYTE *)(a2 + (int)a4 - 1) )\n {\n return (unsigned int)sub_1149(a1, a2, a3 - 1, (unsigned int)(a4 - 1)) + 1;\n }\n else\n {\n v7 = sub_1149(a1, a2, a3 - 1, a4);\n v8 = sub_1149(a1, a2, a3, (unsigned int)(v6 - 1));\n if ( v7 <= v8 )\n v8 = v7;\n return (unsigned int)(v8 + 1);\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(long long a1, long long a2, unsigned int a3, long long a4) {\n long long result;\n int v6;\n int v7;\n int v8;\n result = (unsigned int)a4;\n if (a3) {\n v6 = a4;\n result = a3;\n if ((uint32_t)a4) {\n if (*(uint8_t *)(a1 + (int)a3 - 1) == *(uint8_t *)(a2 + (int)a4 - 1)) {\n return (unsigned int)sub_1149(a1, a2, a3 - 1, (unsigned int)(a4 - 1)) +\n 1;\n } else {\n v7 = sub_1149(a1, a2, a3 - 1, a4);\n v8 = sub_1149(a1, a2, a3, (unsigned int)(v6 - 1));\n if (v7 <= v8) v8 = v7;\n return (unsigned int)(v8 + 1);\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, unsigned int a3, long long a4) {\n long long result;\n int v6;\n int v7;\n int v8;\n result = (unsigned int)a4;\n if (a3) {\n v6 = a4;\n result = a3;\n if ((uint32_t)a4) {\n if (*(uint8_t *)(a1 + (int)a3 - 1) == *(uint8_t *)(a2 + (int)a4 - 1)) {\n return (unsigned int)func0(a1, a2, a3 - 1, (unsigned int)(a4 - 1)) + 1;\n } else {\n v7 = func0(a1, a2, a3 - 1, a4);\n v8 = func0(a1, a2, a3, (unsigned int)(v6 - 1));\n if (v7 <= v8) v8 = v7;\n return (unsigned int)(v8 + 1);\n }\n }\n }\n return result;\n}" + }, + { + "index": 923, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *X, const char *Y, int m, int n) {\n if (!m) return n;\n if (!n) return m;\n if (X[m - 1] == Y[n - 1]) return 1 + func0(X, Y, m - 1, n - 1);\n int left = func0(X, Y, m - 1, n);\n int right = func0(X, Y, m, n - 1);\n return 1 + (left < right ? left : right);\n}", + "test": "int main() {\n\n assert(func0(\"AGGTAB\", \"GXTXAYB\", 6, 7) == 9);\n\n assert(func0(\"feek\", \"eke\", 4, 3) == 5);\n\n assert(func0(\"PARRT\", \"RTA\", 5, 3) == 6);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %edx,%edx\nje 12fa \ntest %ecx,%ecx\nje 12fd \npush %r15\nmovslq %ecx,%rcx\nmovslq %edx,%rax\npush %r14\nsub %rcx,%rax\npush %r13\nadd %rdi,%rax\npush %r12\nmov %rdi,%r12\npush %rbp\nmov %rsi,%rbp\npush %rbx\nxor %ebx,%ebx\nsub $0x8,%rsp\njmp 127f \nnopl 0x0(%rax,%rax,1)\nadd $0x1,%ebx\ntest %edx,%edx\nje 12d0 \nsub $0x1,%rcx\ntest %ecx,%ecx\nje 12e8 \nmov %edx,%r14d\nmovzbl -0x1(%rbp,%rcx,1),%esi\nlea -0x1(%rcx),%r13d\nsub $0x1,%edx\ncmp %sil,-0x1(%rcx,%rax,1)\nje 1270 \nmov %rbp,%rsi\nmov %r12,%rdi\ncallq 1230 \nmov %r13d,%ecx\nmov %r14d,%edx\nmov %rbp,%rsi\nmov %r12,%rdi\nmov %eax,%r15d\ncallq 1230 \ncmp %eax,%r15d\ncmovg %eax,%r15d\nadd $0x8,%rsp\nlea 0x1(%rbx,%r15,1),%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nadd $0x8,%rsp\nlea 0x0(%r13,%rbx,1),%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\nadd $0x8,%rsp\nlea (%rbx,%rdx,1),%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmov %ecx,%eax\nretq\nmov %edx,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest edx, edx\njz loc_12FA\ntest ecx, ecx\njz loc_12FD\npush r15\nmovsxd rcx, ecx\nmovsxd rax, edx\npush r14\nsub rax, rcx\npush r13\nadd rax, rdi\npush r12\nmov r12, rdi\npush rbp\nmov rbp, rsi\npush rbx\nxor ebx, ebx\nsub rsp, 8\njmp short loc_127F\nloc_1270:\nadd ebx, 1\ntest edx, edx\njz short loc_12D0\nsub rcx, 1\ntest ecx, ecx\njz short loc_12E8\nloc_127F:\nmov r14d, edx\nmovzx esi, byte ptr [rbp+rcx-1]\nlea r13d, [rcx-1]\nsub edx, 1\ncmp [rcx+rax-1], sil\njz short loc_1270\nmov rsi, rbp\nmov rdi, r12\ncall func0\nmov ecx, r13d\nmov edx, r14d\nmov rsi, rbp\nmov rdi, r12\nmov r15d, eax\ncall func0\ncmp r15d, eax\ncmovg r15d, eax\nadd rsp, 8\nlea eax, [rbx+r15+1]\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_12D0:\nadd rsp, 8\nlea eax, [rbx+r13]\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_12E8:\nadd rsp, 8\nlea eax, [rbx+rdx]\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_12FA:\nmov eax, ecx\nretn\nloc_12FD:\nmov eax, edx\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, __int64 a3, __int64 a4)\n{\n __int64 v4; // rax\n int v5; // ebx\n unsigned int v6; // r14d\n int v7; // r15d\n int v8; // eax\n\n if ( !(_DWORD)a3 )\n return (unsigned int)a4;\n if ( !(_DWORD)a4 )\n return (unsigned int)a3;\n a4 = (int)a4;\n v4 = a1 + (int)a3 - (__int64)(int)a4;\n v5 = 0;\n while ( 1 )\n {\n v6 = a3;\n a3 = (unsigned int)(a3 - 1);\n if ( *(_BYTE *)(a4 + v4 - 1) != *(_BYTE *)(a2 + a4 - 1) )\n break;\n ++v5;\n if ( !(_DWORD)a3 )\n return (unsigned int)(v5 + a4 - 1);\n if ( !(_DWORD)--a4 )\n return (unsigned int)(v5 + a3);\n }\n v7 = func0(a1, a2, a3);\n v8 = func0(a1, a2, v6);\n if ( v7 > v8 )\n v7 = v8;\n return (unsigned int)(v5 + v7 + 1);\n}", + "ida_strip_asm": "sub_1230:\nendbr64\ntest edx, edx\njz loc_12FA\ntest ecx, ecx\njz loc_12FD\npush r15\nmovsxd rcx, ecx\nmovsxd rax, edx\npush r14\nsub rax, rcx\npush r13\nadd rax, rdi\npush r12\nmov r12, rdi\npush rbp\nmov rbp, rsi\npush rbx\nxor ebx, ebx\nsub rsp, 8\njmp short loc_127F\nloc_1270:\nadd ebx, 1\ntest edx, edx\njz short loc_12D0\nsub rcx, 1\ntest ecx, ecx\njz short loc_12E8\nloc_127F:\nmov r14d, edx\nmovzx esi, byte ptr [rbp+rcx-1]\nlea r13d, [rcx-1]\nsub edx, 1\ncmp [rcx+rax-1], sil\njz short loc_1270\nmov rsi, rbp\nmov rdi, r12\ncall sub_1230\nmov ecx, r13d\nmov edx, r14d\nmov rsi, rbp\nmov rdi, r12\nmov r15d, eax\ncall sub_1230\ncmp r15d, eax\ncmovg r15d, eax\nadd rsp, 8\nlea eax, [rbx+r15+1]\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_12D0:\nadd rsp, 8\nlea eax, [rbx+r13]\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_12E8:\nadd rsp, 8\nlea eax, [rbx+rdx]\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_12FA:\nmov eax, ecx\nretn\nloc_12FD:\nmov eax, edx\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1230(__int64 a1, __int64 a2, __int64 a3, __int64 a4)\n{\n __int64 v4; // rax\n int v5; // ebx\n unsigned int v6; // r14d\n int v7; // r15d\n int v8; // eax\n\n if ( !(_DWORD)a3 )\n return (unsigned int)a4;\n if ( !(_DWORD)a4 )\n return (unsigned int)a3;\n a4 = (int)a4;\n v4 = a1 + (int)a3 - (__int64)(int)a4;\n v5 = 0;\n while ( 1 )\n {\n v6 = a3;\n a3 = (unsigned int)(a3 - 1);\n if ( *(_BYTE *)(a4 + v4 - 1) != *(_BYTE *)(a2 + a4 - 1) )\n break;\n ++v5;\n if ( !(_DWORD)a3 )\n return (unsigned int)(v5 + a4 - 1);\n if ( !(_DWORD)--a4 )\n return (unsigned int)(v5 + a3);\n }\n v7 = sub_1230(a1, a2, a3);\n v8 = sub_1230(a1, a2, v6);\n if ( v7 > v8 )\n v7 = v8;\n return (unsigned int)(v5 + v7 + 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1230(long long a1, long long a2, long long a3, long long a4) {\n long long v4;\n int v5;\n unsigned int v6;\n int v7;\n int v8;\n if (!(uint32_t)a3) return (unsigned int)a4;\n if (!(uint32_t)a4) return (unsigned int)a3;\n a4 = (int)a4;\n v4 = a1 + (int)a3 - (long long)(int)a4;\n v5 = 0;\n while (1) {\n v6 = a3;\n a3 = (unsigned int)(a3 - 1);\n if (*(uint8_t *)(a4 + v4 - 1) != *(uint8_t *)(a2 + a4 - 1)) break;\n ++v5;\n if (!(uint32_t)a3) return (unsigned int)(v5 + a4 - 1);\n if (!(uint32_t)--a4) return (unsigned int)(v5 + a3);\n }\n v7 = sub_1230(a1, a2, a3);\n v8 = sub_1230(a1, a2, v6);\n if (v7 > v8) v7 = v8;\n return (unsigned int)(v5 + v7 + 1);\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, long long a3, long long a4) {\n long long v4;\n int v5;\n unsigned int v6;\n int v7;\n int v8;\n if (!(uint32_t)a3) return (unsigned int)a4;\n if (!(uint32_t)a4) return (unsigned int)a3;\n a4 = (int)a4;\n v4 = a1 + (int)a3 - (long long)(int)a4;\n v5 = 0;\n while (1) {\n v6 = a3;\n a3 = (unsigned int)(a3 - 1);\n if (*(uint8_t *)(a4 + v4 - 1) != *(uint8_t *)(a2 + a4 - 1)) break;\n ++v5;\n if (!(uint32_t)a3) return (unsigned int)(v5 + a4 - 1);\n if (!(uint32_t)--a4) return (unsigned int)(v5 + a3);\n }\n v7 = func0(a1, a2, a3);\n v8 = func0(a1, a2, v6);\n if (v7 > v8) v7 = v8;\n return (unsigned int)(v5 + v7 + 1);\n}" + }, + { + "index": 923, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *X, const char *Y, int m, int n) {\n if (!m) return n;\n if (!n) return m;\n if (X[m - 1] == Y[n - 1]) return 1 + func0(X, Y, m - 1, n - 1);\n int left = func0(X, Y, m - 1, n);\n int right = func0(X, Y, m, n - 1);\n return 1 + (left < right ? left : right);\n}", + "test": "int main() {\n\n assert(func0(\"AGGTAB\", \"GXTXAYB\", 6, 7) == 9);\n\n assert(func0(\"feek\", \"eke\", 4, 3) == 5);\n\n assert(func0(\"PARRT\", \"RTA\", 5, 3) == 6);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ntest %edx,%edx\nje 12fa \ntest %ecx,%ecx\nje 12fd \npush %r15\nmovslq %ecx,%rcx\nmovslq %edx,%rax\npush %r14\nsub %rcx,%rax\npush %r13\nadd %rdi,%rax\npush %r12\nmov %rdi,%r12\npush %rbp\nmov %rsi,%rbp\npush %rbx\nxor %ebx,%ebx\nsub $0x8,%rsp\njmp 127f \nnopl 0x0(%rax,%rax,1)\nadd $0x1,%ebx\ntest %edx,%edx\nje 12d0 \nsub $0x1,%rcx\ntest %ecx,%ecx\nje 12e8 \nmov %edx,%r14d\nmovzbl -0x1(%rbp,%rcx,1),%esi\nlea -0x1(%rcx),%r13d\nsub $0x1,%edx\ncmp %sil,-0x1(%rcx,%rax,1)\nje 1270 \nmov %rbp,%rsi\nmov %r12,%rdi\ncallq 1230 \nmov %r13d,%ecx\nmov %r14d,%edx\nmov %rbp,%rsi\nmov %r12,%rdi\nmov %eax,%r15d\ncallq 1230 \ncmp %eax,%r15d\ncmovg %eax,%r15d\nadd $0x8,%rsp\nlea 0x1(%rbx,%r15,1),%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nadd $0x8,%rsp\nlea 0x0(%r13,%rbx,1),%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\nadd $0x8,%rsp\nlea (%rbx,%rdx,1),%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmov %ecx,%eax\nretq\nmov %edx,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmovsxd rbx, ecx\nsub rsp, 38h\ntest edx, edx\njz loc_16D5\nmov ebp, edx\ntest ebx, ebx\njz loc_16D9\nmovsxd rdx, edx\nxor r13d, r13d\nsub rdx, rbx\nadd rdx, rdi\njmp short loc_12E0\nloc_12C8:\nadd r13d, 1\ntest ebp, ebp\njz loc_1680\nsub rbx, 1\ntest ebx, ebx\njz loc_1698\nloc_12E0:\nmovzx r12d, byte ptr [rdx+rbx-1]\nmovzx eax, byte ptr [rsi+rbx-1]\nmovsxd r15, ebp\nlea r14d, [rbx-1]\nsub ebp, 1\ncmp r12b, al\njz short loc_12C8\nmov r9d, ebx\ncmp r15d, 1\njz loc_14CF\nmovsxd rcx, ebx\nmovsxd r9, ebp\nlea edx, [r15-2]\nxor r8d, r8d\nsub rcx, r9\nmovsxd rdx, edx\nadd rcx, rsi\njmp short loc_1340\nloc_1320:\nadd r8d, 1\ntest edx, edx\njz loc_14CC\nsub rdx, 1\ntest r9d, r9d\njz loc_16C0\nmovzx eax, byte ptr [rcx+rdx]\nmov ebx, r9d\nloc_1340:\nlea r9d, [rbx-1]\nmov r10d, edx\ncmp [rdi+rdx], al\njz short loc_1320\nlea eax, [rdx+1]\nmov dword ptr [rsp+68h+var_68], eax\ntest edx, edx\njz loc_1404\nmovsxd rcx, ebx\nmovsxd rax, edx\nmov [rsp+68h+var_60], rdi\nxor ebx, ebx\nsub rax, rcx\nadd rax, rdi\njmp short loc_1387\nloc_1370:\nadd ebx, 1\ntest edx, edx\njz loc_16F7\nsub rcx, 1\ntest ecx, ecx\njz loc_170B\nloc_1387:\nmov r11d, edx\nmovzx edi, byte ptr [rsi+rcx-1]\nlea r10d, [rcx-1]\nsub edx, 1\ncmp [rcx+rax-1], dil\njz short loc_1370\nmov rdi, [rsp+68h+var_60]\nmov [rsp+68h+var_3C], r8d\nmov [rsp+68h+var_40], r9d\nmov [rsp+68h+var_44], r10d\nmov [rsp+68h+var_48], r11d\nmov [rsp+68h+var_50], rsi\nmov [rsp+68h+var_58], rdi\ncall func0\nmov rsi, [rsp+68h+var_50]\nmov rdi, [rsp+68h+var_58]\nmov ecx, [rsp+68h+var_44]\nmov edx, [rsp+68h+var_48]\nmov dword ptr [rsp+68h+var_60], eax\ncall func0\nmov edi, dword ptr [rsp+68h+var_60]\nmov rsi, [rsp+68h+var_50]\nmov r9d, [rsp+68h+var_40]\nmov r8d, [rsp+68h+var_3C]\ncmp edi, eax\ncmovle eax, edi\nmov rdi, [rsp+68h+var_58]\nlea r10d, [rax+1]\nloc_1401:\nadd ebx, r10d\nloc_1404:\nmov eax, dword ptr [rsp+68h+var_68]\ntest r9d, r9d\njz loc_14C3\nmovsxd rax, dword ptr [rsp+68h+var_68]\nmovsxd rcx, r9d\nmov [rsp+68h+var_68], rdi\nxor r9d, r9d\nmov rdx, rax\nsub rax, rcx\nadd rax, rdi\njmp short loc_1448\nloc_1430:\nadd r9d, 1\ntest edx, edx\njz loc_16DD\nsub rcx, 1\ntest ecx, ecx\njz loc_171F\nloc_1448:\nmov r11d, edx\nmovzx edi, byte ptr [rsi+rcx-1]\nlea r10d, [rcx-1]\nsub edx, 1\ncmp [rcx+rax-1], dil\njz short loc_1430\nmov rdi, [rsp+68h+var_68]\nmov [rsp+68h+var_40], r8d\nmov [rsp+68h+var_44], r9d\nmov [rsp+68h+var_48], r11d\nmov dword ptr [rsp+68h+var_50], r10d\nmov [rsp+68h+var_58], rsi\nmov [rsp+68h+var_60], rdi\ncall func0\nmov rsi, [rsp+68h+var_58]\nmov rdi, [rsp+68h+var_60]\nmov ecx, dword ptr [rsp+68h+var_50]\nmov edx, [rsp+68h+var_48]\nmov dword ptr [rsp+68h+var_68], eax\ncall func0\nmov edi, dword ptr [rsp+68h+var_68]\nmov r9d, [rsp+68h+var_44]\nmov r8d, [rsp+68h+var_40]\nmov rsi, [rsp+68h+var_58]\ncmp edi, eax\ncmovle eax, edi\nmov rdi, [rsp+68h+var_60]\nlea eax, [r9+rax+1]\nmov dword ptr [rsp+68h+var_68], eax\nloc_14C3:\ncmp ebx, eax\ncmovg ebx, eax\nlea r9d, [rbx+1]\nloc_14CC:\nadd r9d, r8d\nloc_14CF:\ntest r14d, r14d\njz loc_1663\nmovsxd rax, r14d\nmovsxd rbp, ebp\nxor ebx, ebx\nsub rax, r15\nadd rax, rsi\njmp short loc_1511\nloc_14F0:\nsub r14d, 1\nadd ebx, 1\ntest ebp, ebp\njz loc_16B0\nsub rbp, 1\ntest r14d, r14d\njz loc_16D0\nmovzx r12d, byte ptr [rdi+rbp]\nloc_1511:\nmov r15d, ebp\ncmp [rax+rbp], r12b\njz short loc_14F0\nlea r12d, [rbp+1]\nlea ecx, [r14-1]\nmov r15d, r14d\ntest ebp, ebp\njz loc_15C7\nmovsxd rax, ebp\nmovsxd rcx, r14d\nxor r15d, r15d\nmov rdx, rax\nsub rax, rcx\nadd rax, rdi\njmp short loc_155C\nloc_1548:\nadd r15d, 1\ntest edx, edx\njz short loc_15C0\nsub rcx, 1\ntest ecx, ecx\njz loc_1718\nloc_155C:\nmov r8d, edx\nmovzx r11d, byte ptr [rsi+rcx-1]\nlea ebp, [rcx-1]\nsub edx, 1\ncmp [rcx+rax-1], r11b\njz short loc_1548\nmov [rsp+68h+var_48], r9d\nmov dword ptr [rsp+68h+var_50], r8d\nmov [rsp+68h+var_60], rsi\nmov [rsp+68h+var_68], rdi\ncall func0\nmov rsi, [rsp+68h+var_60]\nmov rdi, [rsp+68h+var_68]\nmov ecx, ebp\nmov edx, dword ptr [rsp+68h+var_50]\nmov dword ptr [rsp+68h+var_58], eax\ncall func0\nmov r10d, dword ptr [rsp+68h+var_58]\nmov rdi, [rsp+68h+var_68]\nmov rsi, [rsp+68h+var_60]\nmov r9d, [rsp+68h+var_48]\ncmp r10d, eax\ncmovg r10d, eax\nlea ebp, [r10+1]\nloc_15C0:\nadd r15d, ebp\nlea ecx, [r14-1]\nloc_15C7:\ntest ecx, ecx\njz loc_1657\nmovsxd rax, r12d\nmovsxd rcx, ecx\nxor ebp, ebp\nmov rdx, rax\nsub rax, rcx\nadd rax, rdi\njmp short loc_15FF\nloc_15E8:\nadd ebp, 1\ntest edx, edx\njz loc_16ED\nsub rcx, 1\ntest ecx, ecx\njz loc_1701\nloc_15FF:\nmov r12d, edx\nmovzx r11d, byte ptr [rsi+rcx-1]\nlea r14d, [rcx-1]\nsub edx, 1\ncmp [rcx+rax-1], r11b\njz short loc_15E8\nmov dword ptr [rsp+68h+var_50], r9d\nmov [rsp+68h+var_58], rsi\nmov [rsp+68h+var_60], rdi\ncall func0\nmov rsi, [rsp+68h+var_58]\nmov edx, r12d\nmov ecx, r14d\nmov rdi, [rsp+68h+var_60]\nmov dword ptr [rsp+68h+var_68], eax\ncall func0\nmov r8d, dword ptr [rsp+68h+var_68]\nmov r9d, dword ptr [rsp+68h+var_50]\ncmp r8d, eax\ncmovg r8d, eax\nlea r12d, [rbp+r8+1]\nloc_1657:\ncmp r15d, r12d\ncmovg r15d, r12d\nlea r15d, [rbx+r15+1]\nloc_1663:\ncmp r9d, r15d\ncmovg r9d, r15d\nadd rsp, 38h\npop rbx\npop rbp\nlea eax, [r13+r9+1]\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1680:\nlea eax, [r13+r14+0]\nloc_1685:\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1698:\nadd rsp, 38h\nlea eax, [r13+rbp+0]\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_16B0:\nlea r15d, [r14+rbx]\njmp short loc_1663\nloc_16C0:\nmov r9d, r10d\njmp loc_14CC\nloc_16D0:\nadd r15d, ebx\njmp short loc_1663\nloc_16D5:\nmov eax, ebx\njmp short loc_1685\nloc_16D9:\nmov eax, edx\njmp short loc_1685\nloc_16DD:\nlea eax, [r9+r10]\nmov rdi, [rsp+68h+var_68]\nmov dword ptr [rsp+68h+var_68], eax\njmp loc_14C3\nloc_16ED:\nlea r12d, [rbp+r14+0]\njmp loc_1657\nloc_16F7:\nmov rdi, [rsp+68h+var_60]\njmp loc_1401\nloc_1701:\nlea r12d, [rbp+rdx+0]\njmp loc_1657\nloc_170B:\nmov rdi, [rsp+68h+var_60]\nmov r10d, edx\njmp loc_1401\nloc_1718:\nmov ebp, edx\njmp loc_15C0\nloc_171F:\nlea eax, [r9+rdx]\nmov rdi, [rsp+68h+var_68]\nmov dword ptr [rsp+68h+var_68], eax\njmp loc_14C3", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, unsigned int a3, unsigned int a4)\n{\n __int64 v4; // rbx\n __int64 v5; // rbp\n int v6; // r13d\n __int64 v7; // rdx\n char v8; // r12\n char v9; // al\n __int64 v10; // r15\n int v11; // r14d\n int v12; // r9d\n int v13; // r8d\n __int64 v14; // rdx\n __int64 v15; // rcx\n int v16; // r9d\n int v17; // r10d\n __int64 v18; // rcx\n int v19; // ebx\n __int64 v20; // rax\n unsigned int v21; // r11d\n int v22; // r10d\n int v23; // eax\n int v24; // eax\n __int64 v25; // rcx\n int v26; // r9d\n __int64 v27; // rdx\n __int64 v28; // rax\n unsigned int v29; // r11d\n int v30; // eax\n int v31; // ebx\n __int64 v32; // rax\n int v33; // r15d\n int v34; // r12d\n __int64 v35; // rcx\n int v36; // r15d\n __int64 v37; // rcx\n int v38; // r15d\n __int64 v39; // rdx\n __int64 v40; // rax\n unsigned int v41; // r8d\n int v42; // ebp\n int v43; // eax\n int v44; // r10d\n int v45; // ebp\n __int64 v46; // rdx\n __int64 v47; // rax\n unsigned int v48; // r12d\n int v49; // eax\n int v50; // r8d\n int v52; // [rsp+0h] [rbp-68h]\n int v53; // [rsp+0h] [rbp-68h]\n int v54; // [rsp+0h] [rbp-68h]\n int v55; // [rsp+8h] [rbp-60h]\n int v56; // [rsp+10h] [rbp-58h]\n unsigned int v57; // [rsp+18h] [rbp-50h]\n int v58; // [rsp+18h] [rbp-50h]\n unsigned int v59; // [rsp+20h] [rbp-48h]\n unsigned int v60; // [rsp+20h] [rbp-48h]\n int v61; // [rsp+20h] [rbp-48h]\n int v62; // [rsp+24h] [rbp-44h]\n int v63; // [rsp+28h] [rbp-40h]\n int v64; // [rsp+28h] [rbp-40h]\n int v65; // [rsp+2Ch] [rbp-3Ch]\n\n v4 = (int)a4;\n if ( !a3 )\n return a4;\n LODWORD(v5) = a3;\n if ( !a4 )\n return a3;\n v6 = 0;\n v7 = a1 + (int)a3 - (__int64)(int)a4;\n while ( 1 )\n {\n v8 = *(_BYTE *)(v7 + v4 - 1);\n v9 = *(_BYTE *)(a2 + v4 - 1);\n v10 = (int)v5;\n v11 = v4 - 1;\n LODWORD(v5) = v5 - 1;\n if ( v8 != v9 )\n break;\n ++v6;\n if ( !(_DWORD)v5 )\n return (unsigned int)(v6 + v11);\n if ( !(_DWORD)--v4 )\n return (unsigned int)(v6 + v5);\n }\n v12 = v4;\n if ( (_DWORD)v10 != 1 )\n {\n v13 = 0;\n v14 = (int)v10 - 2;\n v15 = a2 + (int)v4 - (__int64)(int)v5;\n while ( 1 )\n {\n v16 = v4 - 1;\n v17 = v14;\n if ( *(_BYTE *)(a1 + v14) != v9 )\n break;\n ++v13;\n if ( !(_DWORD)v14 )\n goto LABEL_33;\n --v14;\n if ( (_DWORD)v4 == 1 )\n {\n v16 = v17;\n goto LABEL_33;\n }\n v9 = *(_BYTE *)(v15 + v14);\n LODWORD(v4) = v4 - 1;\n }\n v52 = v14 + 1;\n if ( (_DWORD)v14 )\n {\n v18 = (int)v4;\n v19 = 0;\n v20 = a1 + (int)v14 - v18;\n while ( 1 )\n {\n v21 = v14;\n v22 = v18 - 1;\n v14 = (unsigned int)(v14 - 1);\n if ( *(_BYTE *)(v18 + v20 - 1) != *(_BYTE *)(a2 + v18 - 1) )\n break;\n ++v19;\n if ( !(_DWORD)v14 )\n goto LABEL_21;\n if ( !(_DWORD)--v18 )\n {\n v22 = v14;\n goto LABEL_21;\n }\n }\n v65 = v13;\n v63 = v16;\n v59 = v21;\n v55 = func0(a1, a2, v14);\n v23 = func0(a1, a2, v59);\n v16 = v63;\n v13 = v65;\n if ( v55 <= v23 )\n v23 = v55;\n v22 = v23 + 1;\nLABEL_21:\n LODWORD(v4) = v22 + v19;\n }\n v24 = v52;\n if ( v16 )\n {\n v25 = v16;\n v26 = 0;\n LODWORD(v27) = v52;\n v28 = a1 + v52 - v25;\n while ( 1 )\n {\n v29 = v27;\n v27 = (unsigned int)(v27 - 1);\n if ( *(_BYTE *)(v25 + v28 - 1) != *(_BYTE *)(a2 + v25 - 1) )\n break;\n ++v26;\n if ( !(_DWORD)v27 )\n {\n v24 = v26 + v25 - 1;\n goto LABEL_30;\n }\n if ( !(_DWORD)--v25 )\n {\n v24 = v26 + v27;\n goto LABEL_30;\n }\n }\n v64 = v13;\n v62 = v26;\n v60 = v29;\n v53 = func0(a1, a2, v27);\n v30 = func0(a1, a2, v60);\n v13 = v64;\n if ( v53 <= v30 )\n v30 = v53;\n v24 = v62 + v30 + 1;\n }\nLABEL_30:\n if ( (int)v4 > v24 )\n LODWORD(v4) = v24;\n v16 = v4 + 1;\nLABEL_33:\n v12 = v13 + v16;\n }\n if ( v11 )\n {\n v5 = (int)v5;\n v31 = 0;\n v32 = a2 + v11 - v10;\n while ( 1 )\n {\n v33 = v5;\n if ( *(_BYTE *)(v32 + v5) != v8 )\n break;\n --v11;\n ++v31;\n if ( !(_DWORD)v5 )\n {\n LODWORD(v10) = v11 + v31;\n goto LABEL_60;\n }\n --v5;\n if ( !v11 )\n {\n LODWORD(v10) = v31 + v33;\n goto LABEL_60;\n }\n v8 = *(_BYTE *)(a1 + v5);\n }\n v34 = v5 + 1;\n LODWORD(v35) = v11 - 1;\n v36 = v11;\n if ( (_DWORD)v5 )\n {\n v37 = v11;\n v38 = 0;\n LODWORD(v39) = v5;\n v40 = a1 + (int)v5 - (__int64)v11;\n while ( 1 )\n {\n v41 = v39;\n v42 = v37 - 1;\n v39 = (unsigned int)(v39 - 1);\n if ( *(_BYTE *)(v37 + v40 - 1) != *(_BYTE *)(a2 + v37 - 1) )\n break;\n ++v38;\n if ( !(_DWORD)v39 )\n goto LABEL_48;\n if ( !(_DWORD)--v37 )\n {\n v42 = v39;\n goto LABEL_48;\n }\n }\n v61 = v12;\n v57 = v41;\n v56 = func0(a1, a2, v39);\n v43 = func0(a1, a2, v57);\n v44 = v56;\n v12 = v61;\n if ( v56 > v43 )\n v44 = v43;\n v42 = v44 + 1;\nLABEL_48:\n v36 = v42 + v38;\n LODWORD(v35) = v11 - 1;\n }\n if ( (_DWORD)v35 )\n {\n v35 = (int)v35;\n v45 = 0;\n LODWORD(v46) = v34;\n v47 = a1 + v34 - (__int64)(int)v35;\n while ( 1 )\n {\n v48 = v46;\n v46 = (unsigned int)(v46 - 1);\n if ( *(_BYTE *)(v35 + v47 - 1) != *(_BYTE *)(a2 + v35 - 1) )\n break;\n ++v45;\n if ( !(_DWORD)v46 )\n {\n v34 = v45 + v35 - 1;\n goto LABEL_57;\n }\n if ( !(_DWORD)--v35 )\n {\n v34 = v45 + v46;\n goto LABEL_57;\n }\n }\n v58 = v12;\n v54 = func0(a1, a2, v46);\n v49 = func0(a1, a2, v48);\n v50 = v54;\n v12 = v58;\n if ( v54 > v49 )\n v50 = v49;\n v34 = v45 + v50 + 1;\n }\nLABEL_57:\n if ( v36 > v34 )\n v36 = v34;\n LODWORD(v10) = v31 + v36 + 1;\n }\nLABEL_60:\n if ( v12 > (int)v10 )\n v12 = v10;\n return (unsigned int)(v6 + v12 + 1);\n}", + "ida_strip_asm": "sub_1290:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmovsxd rbx, ecx\nsub rsp, 38h\ntest edx, edx\njz loc_16D5\nmov ebp, edx\ntest ebx, ebx\njz loc_16D9\nmovsxd rdx, edx\nxor r13d, r13d\nsub rdx, rbx\nadd rdx, rdi\njmp short loc_12E0\nloc_12C8:\nadd r13d, 1\ntest ebp, ebp\njz loc_1680\nsub rbx, 1\ntest ebx, ebx\njz loc_1698\nloc_12E0:\nmovzx r12d, byte ptr [rdx+rbx-1]\nmovzx eax, byte ptr [rsi+rbx-1]\nmovsxd r15, ebp\nlea r14d, [rbx-1]\nsub ebp, 1\ncmp r12b, al\njz short loc_12C8\nmov r9d, ebx\ncmp r15d, 1\njz loc_14CF\nmovsxd rcx, ebx\nmovsxd r9, ebp\nlea edx, [r15-2]\nxor r8d, r8d\nsub rcx, r9\nmovsxd rdx, edx\nadd rcx, rsi\njmp short loc_1340\nloc_1320:\nadd r8d, 1\ntest edx, edx\njz loc_14CC\nsub rdx, 1\ntest r9d, r9d\njz loc_16C0\nmovzx eax, byte ptr [rcx+rdx]\nmov ebx, r9d\nloc_1340:\nlea r9d, [rbx-1]\nmov r10d, edx\ncmp [rdi+rdx], al\njz short loc_1320\nlea eax, [rdx+1]\nmov dword ptr [rsp+68h+var_68], eax\ntest edx, edx\njz loc_1404\nmovsxd rcx, ebx\nmovsxd rax, edx\nmov [rsp+68h+var_60], rdi\nxor ebx, ebx\nsub rax, rcx\nadd rax, rdi\njmp short loc_1387\nloc_1370:\nadd ebx, 1\ntest edx, edx\njz loc_16F7\nsub rcx, 1\ntest ecx, ecx\njz loc_170B\nloc_1387:\nmov r11d, edx\nmovzx edi, byte ptr [rsi+rcx-1]\nlea r10d, [rcx-1]\nsub edx, 1\ncmp [rcx+rax-1], dil\njz short loc_1370\nmov rdi, [rsp+68h+var_60]\nmov [rsp+68h+var_3C], r8d\nmov [rsp+68h+var_40], r9d\nmov [rsp+68h+var_44], r10d\nmov [rsp+68h+var_48], r11d\nmov [rsp+68h+var_50], rsi\nmov [rsp+68h+var_58], rdi\ncall sub_1290\nmov rsi, [rsp+68h+var_50]\nmov rdi, [rsp+68h+var_58]\nmov ecx, [rsp+68h+var_44]\nmov edx, [rsp+68h+var_48]\nmov dword ptr [rsp+68h+var_60], eax\ncall sub_1290\nmov edi, dword ptr [rsp+68h+var_60]\nmov rsi, [rsp+68h+var_50]\nmov r9d, [rsp+68h+var_40]\nmov r8d, [rsp+68h+var_3C]\ncmp edi, eax\ncmovle eax, edi\nmov rdi, [rsp+68h+var_58]\nlea r10d, [rax+1]\nloc_1401:\nadd ebx, r10d\nloc_1404:\nmov eax, dword ptr [rsp+68h+var_68]\ntest r9d, r9d\njz loc_14C3\nmovsxd rax, dword ptr [rsp+68h+var_68]\nmovsxd rcx, r9d\nmov [rsp+68h+var_68], rdi\nxor r9d, r9d\nmov rdx, rax\nsub rax, rcx\nadd rax, rdi\njmp short loc_1448\nloc_1430:\nadd r9d, 1\ntest edx, edx\njz loc_16DD\nsub rcx, 1\ntest ecx, ecx\njz loc_171F\nloc_1448:\nmov r11d, edx\nmovzx edi, byte ptr [rsi+rcx-1]\nlea r10d, [rcx-1]\nsub edx, 1\ncmp [rcx+rax-1], dil\njz short loc_1430\nmov rdi, [rsp+68h+var_68]\nmov [rsp+68h+var_40], r8d\nmov [rsp+68h+var_44], r9d\nmov [rsp+68h+var_48], r11d\nmov dword ptr [rsp+68h+var_50], r10d\nmov [rsp+68h+var_58], rsi\nmov [rsp+68h+var_60], rdi\ncall sub_1290\nmov rsi, [rsp+68h+var_58]\nmov rdi, [rsp+68h+var_60]\nmov ecx, dword ptr [rsp+68h+var_50]\nmov edx, [rsp+68h+var_48]\nmov dword ptr [rsp+68h+var_68], eax\ncall sub_1290\nmov edi, dword ptr [rsp+68h+var_68]\nmov r9d, [rsp+68h+var_44]\nmov r8d, [rsp+68h+var_40]\nmov rsi, [rsp+68h+var_58]\ncmp edi, eax\ncmovle eax, edi\nmov rdi, [rsp+68h+var_60]\nlea eax, [r9+rax+1]\nmov dword ptr [rsp+68h+var_68], eax\nloc_14C3:\ncmp ebx, eax\ncmovg ebx, eax\nlea r9d, [rbx+1]\nloc_14CC:\nadd r9d, r8d\nloc_14CF:\ntest r14d, r14d\njz loc_1663\nmovsxd rax, r14d\nmovsxd rbp, ebp\nxor ebx, ebx\nsub rax, r15\nadd rax, rsi\njmp short loc_1511\nloc_14F0:\nsub r14d, 1\nadd ebx, 1\ntest ebp, ebp\njz loc_16B0\nsub rbp, 1\ntest r14d, r14d\njz loc_16D0\nmovzx r12d, byte ptr [rdi+rbp]\nloc_1511:\nmov r15d, ebp\ncmp [rax+rbp], r12b\njz short loc_14F0\nlea r12d, [rbp+1]\nlea ecx, [r14-1]\nmov r15d, r14d\ntest ebp, ebp\njz loc_15C7\nmovsxd rax, ebp\nmovsxd rcx, r14d\nxor r15d, r15d\nmov rdx, rax\nsub rax, rcx\nadd rax, rdi\njmp short loc_155C\nloc_1548:\nadd r15d, 1\ntest edx, edx\njz short loc_15C0\nsub rcx, 1\ntest ecx, ecx\njz loc_1718\nloc_155C:\nmov r8d, edx\nmovzx r11d, byte ptr [rsi+rcx-1]\nlea ebp, [rcx-1]\nsub edx, 1\ncmp [rcx+rax-1], r11b\njz short loc_1548\nmov [rsp+68h+var_48], r9d\nmov dword ptr [rsp+68h+var_50], r8d\nmov [rsp+68h+var_60], rsi\nmov [rsp+68h+var_68], rdi\ncall sub_1290\nmov rsi, [rsp+68h+var_60]\nmov rdi, [rsp+68h+var_68]\nmov ecx, ebp\nmov edx, dword ptr [rsp+68h+var_50]\nmov dword ptr [rsp+68h+var_58], eax\ncall sub_1290\nmov r10d, dword ptr [rsp+68h+var_58]\nmov rdi, [rsp+68h+var_68]\nmov rsi, [rsp+68h+var_60]\nmov r9d, [rsp+68h+var_48]\ncmp r10d, eax\ncmovg r10d, eax\nlea ebp, [r10+1]\nloc_15C0:\nadd r15d, ebp\nlea ecx, [r14-1]\nloc_15C7:\ntest ecx, ecx\njz loc_1657\nmovsxd rax, r12d\nmovsxd rcx, ecx\nxor ebp, ebp\nmov rdx, rax\nsub rax, rcx\nadd rax, rdi\njmp short loc_15FF\nloc_15E8:\nadd ebp, 1\ntest edx, edx\njz loc_16ED\nsub rcx, 1\ntest ecx, ecx\njz loc_1701\nloc_15FF:\nmov r12d, edx\nmovzx r11d, byte ptr [rsi+rcx-1]\nlea r14d, [rcx-1]\nsub edx, 1\ncmp [rcx+rax-1], r11b\njz short loc_15E8\nmov dword ptr [rsp+68h+var_50], r9d\nmov [rsp+68h+var_58], rsi\nmov [rsp+68h+var_60], rdi\ncall sub_1290\nmov rsi, [rsp+68h+var_58]\nmov edx, r12d\nmov ecx, r14d\nmov rdi, [rsp+68h+var_60]\nmov dword ptr [rsp+68h+var_68], eax\ncall sub_1290\nmov r8d, dword ptr [rsp+68h+var_68]\nmov r9d, dword ptr [rsp+68h+var_50]\ncmp r8d, eax\ncmovg r8d, eax\nlea r12d, [rbp+r8+1]\nloc_1657:\ncmp r15d, r12d\ncmovg r15d, r12d\nlea r15d, [rbx+r15+1]\nloc_1663:\ncmp r9d, r15d\ncmovg r9d, r15d\nadd rsp, 38h\npop rbx\npop rbp\nlea eax, [r13+r9+1]\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1680:\nlea eax, [r13+r14+0]\nloc_1685:\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1698:\nadd rsp, 38h\nlea eax, [r13+rbp+0]\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_16B0:\nlea r15d, [r14+rbx]\njmp short loc_1663\nloc_16C0:\nmov r9d, r10d\njmp loc_14CC\nloc_16D0:\nadd r15d, ebx\njmp short loc_1663\nloc_16D5:\nmov eax, ebx\njmp short loc_1685\nloc_16D9:\nmov eax, edx\njmp short loc_1685\nloc_16DD:\nlea eax, [r9+r10]\nmov rdi, [rsp+68h+var_68]\nmov dword ptr [rsp+68h+var_68], eax\njmp loc_14C3\nloc_16ED:\nlea r12d, [rbp+r14+0]\njmp loc_1657\nloc_16F7:\nmov rdi, [rsp+68h+var_60]\njmp loc_1401\nloc_1701:\nlea r12d, [rbp+rdx+0]\njmp loc_1657\nloc_170B:\nmov rdi, [rsp+68h+var_60]\nmov r10d, edx\njmp loc_1401\nloc_1718:\nmov ebp, edx\njmp loc_15C0\nloc_171F:\nlea eax, [r9+rdx]\nmov rdi, [rsp+68h+var_68]\nmov dword ptr [rsp+68h+var_68], eax\njmp loc_14C3", + "ida_strip_pseudo": "__int64 __fastcall sub_1290(__int64 a1, __int64 a2, unsigned int a3, unsigned int a4)\n{\n __int64 v4; // rbx\n __int64 v5; // rbp\n int v6; // r13d\n __int64 v7; // rdx\n char v8; // r12\n char v9; // al\n __int64 v10; // r15\n int v11; // r14d\n int v12; // r9d\n int v13; // r8d\n __int64 v14; // rdx\n __int64 v15; // rcx\n int v16; // r9d\n int v17; // r10d\n __int64 v18; // rcx\n int v19; // ebx\n __int64 v20; // rax\n unsigned int v21; // r11d\n int v22; // r10d\n int v23; // eax\n int v24; // eax\n __int64 v25; // rcx\n int v26; // r9d\n __int64 v27; // rdx\n __int64 v28; // rax\n unsigned int v29; // r11d\n int v30; // eax\n int v31; // ebx\n __int64 v32; // rax\n int v33; // r15d\n int v34; // r12d\n __int64 v35; // rcx\n int v36; // r15d\n __int64 v37; // rcx\n int v38; // r15d\n __int64 v39; // rdx\n __int64 v40; // rax\n unsigned int v41; // r8d\n int v42; // ebp\n int v43; // eax\n int v44; // r10d\n int v45; // ebp\n __int64 v46; // rdx\n __int64 v47; // rax\n unsigned int v48; // r12d\n int v49; // eax\n int v50; // r8d\n int v52; // [rsp+0h] [rbp-68h]\n int v53; // [rsp+0h] [rbp-68h]\n int v54; // [rsp+0h] [rbp-68h]\n int v55; // [rsp+8h] [rbp-60h]\n int v56; // [rsp+10h] [rbp-58h]\n unsigned int v57; // [rsp+18h] [rbp-50h]\n int v58; // [rsp+18h] [rbp-50h]\n unsigned int v59; // [rsp+20h] [rbp-48h]\n unsigned int v60; // [rsp+20h] [rbp-48h]\n int v61; // [rsp+20h] [rbp-48h]\n int v62; // [rsp+24h] [rbp-44h]\n int v63; // [rsp+28h] [rbp-40h]\n int v64; // [rsp+28h] [rbp-40h]\n int v65; // [rsp+2Ch] [rbp-3Ch]\n\n v4 = (int)a4;\n if ( !a3 )\n return a4;\n LODWORD(v5) = a3;\n if ( !a4 )\n return a3;\n v6 = 0;\n v7 = a1 + (int)a3 - (__int64)(int)a4;\n while ( 1 )\n {\n v8 = *(_BYTE *)(v7 + v4 - 1);\n v9 = *(_BYTE *)(a2 + v4 - 1);\n v10 = (int)v5;\n v11 = v4 - 1;\n LODWORD(v5) = v5 - 1;\n if ( v8 != v9 )\n break;\n ++v6;\n if ( !(_DWORD)v5 )\n return (unsigned int)(v6 + v11);\n if ( !(_DWORD)--v4 )\n return (unsigned int)(v6 + v5);\n }\n v12 = v4;\n if ( (_DWORD)v10 != 1 )\n {\n v13 = 0;\n v14 = (int)v10 - 2;\n v15 = a2 + (int)v4 - (__int64)(int)v5;\n while ( 1 )\n {\n v16 = v4 - 1;\n v17 = v14;\n if ( *(_BYTE *)(a1 + v14) != v9 )\n break;\n ++v13;\n if ( !(_DWORD)v14 )\n goto LABEL_33;\n --v14;\n if ( (_DWORD)v4 == 1 )\n {\n v16 = v17;\n goto LABEL_33;\n }\n v9 = *(_BYTE *)(v15 + v14);\n LODWORD(v4) = v4 - 1;\n }\n v52 = v14 + 1;\n if ( (_DWORD)v14 )\n {\n v18 = (int)v4;\n v19 = 0;\n v20 = a1 + (int)v14 - v18;\n while ( 1 )\n {\n v21 = v14;\n v22 = v18 - 1;\n v14 = (unsigned int)(v14 - 1);\n if ( *(_BYTE *)(v18 + v20 - 1) != *(_BYTE *)(a2 + v18 - 1) )\n break;\n ++v19;\n if ( !(_DWORD)v14 )\n goto LABEL_21;\n if ( !(_DWORD)--v18 )\n {\n v22 = v14;\n goto LABEL_21;\n }\n }\n v65 = v13;\n v63 = v16;\n v59 = v21;\n v55 = sub_1290(a1, a2, v14);\n v23 = sub_1290(a1, a2, v59);\n v16 = v63;\n v13 = v65;\n if ( v55 <= v23 )\n v23 = v55;\n v22 = v23 + 1;\nLABEL_21:\n LODWORD(v4) = v22 + v19;\n }\n v24 = v52;\n if ( v16 )\n {\n v25 = v16;\n v26 = 0;\n LODWORD(v27) = v52;\n v28 = a1 + v52 - v25;\n while ( 1 )\n {\n v29 = v27;\n v27 = (unsigned int)(v27 - 1);\n if ( *(_BYTE *)(v25 + v28 - 1) != *(_BYTE *)(a2 + v25 - 1) )\n break;\n ++v26;\n if ( !(_DWORD)v27 )\n {\n v24 = v26 + v25 - 1;\n goto LABEL_30;\n }\n if ( !(_DWORD)--v25 )\n {\n v24 = v26 + v27;\n goto LABEL_30;\n }\n }\n v64 = v13;\n v62 = v26;\n v60 = v29;\n v53 = sub_1290(a1, a2, v27);\n v30 = sub_1290(a1, a2, v60);\n v13 = v64;\n if ( v53 <= v30 )\n v30 = v53;\n v24 = v62 + v30 + 1;\n }\nLABEL_30:\n if ( (int)v4 > v24 )\n LODWORD(v4) = v24;\n v16 = v4 + 1;\nLABEL_33:\n v12 = v13 + v16;\n }\n if ( v11 )\n {\n v5 = (int)v5;\n v31 = 0;\n v32 = a2 + v11 - v10;\n while ( 1 )\n {\n v33 = v5;\n if ( *(_BYTE *)(v32 + v5) != v8 )\n break;\n --v11;\n ++v31;\n if ( !(_DWORD)v5 )\n {\n LODWORD(v10) = v11 + v31;\n goto LABEL_60;\n }\n --v5;\n if ( !v11 )\n {\n LODWORD(v10) = v31 + v33;\n goto LABEL_60;\n }\n v8 = *(_BYTE *)(a1 + v5);\n }\n v34 = v5 + 1;\n LODWORD(v35) = v11 - 1;\n v36 = v11;\n if ( (_DWORD)v5 )\n {\n v37 = v11;\n v38 = 0;\n LODWORD(v39) = v5;\n v40 = a1 + (int)v5 - (__int64)v11;\n while ( 1 )\n {\n v41 = v39;\n v42 = v37 - 1;\n v39 = (unsigned int)(v39 - 1);\n if ( *(_BYTE *)(v37 + v40 - 1) != *(_BYTE *)(a2 + v37 - 1) )\n break;\n ++v38;\n if ( !(_DWORD)v39 )\n goto LABEL_48;\n if ( !(_DWORD)--v37 )\n {\n v42 = v39;\n goto LABEL_48;\n }\n }\n v61 = v12;\n v57 = v41;\n v56 = sub_1290(a1, a2, v39);\n v43 = sub_1290(a1, a2, v57);\n v44 = v56;\n v12 = v61;\n if ( v56 > v43 )\n v44 = v43;\n v42 = v44 + 1;\nLABEL_48:\n v36 = v42 + v38;\n LODWORD(v35) = v11 - 1;\n }\n if ( (_DWORD)v35 )\n {\n v35 = (int)v35;\n v45 = 0;\n LODWORD(v46) = v34;\n v47 = a1 + v34 - (__int64)(int)v35;\n while ( 1 )\n {\n v48 = v46;\n v46 = (unsigned int)(v46 - 1);\n if ( *(_BYTE *)(v35 + v47 - 1) != *(_BYTE *)(a2 + v35 - 1) )\n break;\n ++v45;\n if ( !(_DWORD)v46 )\n {\n v34 = v45 + v35 - 1;\n goto LABEL_57;\n }\n if ( !(_DWORD)--v35 )\n {\n v34 = v45 + v46;\n goto LABEL_57;\n }\n }\n v58 = v12;\n v54 = sub_1290(a1, a2, v46);\n v49 = sub_1290(a1, a2, v48);\n v50 = v54;\n v12 = v58;\n if ( v54 > v49 )\n v50 = v49;\n v34 = v45 + v50 + 1;\n }\nLABEL_57:\n if ( v36 > v34 )\n v36 = v34;\n LODWORD(v10) = v31 + v36 + 1;\n }\nLABEL_60:\n if ( v12 > (int)v10 )\n v12 = v10;\n return (unsigned int)(v6 + v12 + 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1290(long long a1, long long a2, unsigned int a3,\n unsigned int a4) {\n long long v4;\n long long v5;\n int v6;\n long long v7;\n char v8;\n char v9;\n long long v10;\n int v11;\n int v12;\n int v13;\n long long v14;\n long long v15;\n int v16;\n int v17;\n long long v18;\n int v19;\n long long v20;\n unsigned int v21;\n int v22;\n int v23;\n int v24;\n long long v25;\n int v26;\n long long v27;\n long long v28;\n unsigned int v29;\n int v30;\n int v31;\n long long v32;\n int v33;\n int v34;\n long long v35;\n int v36;\n long long v37;\n int v38;\n long long v39;\n long long v40;\n unsigned int v41;\n int v42;\n int v43;\n int v44;\n int v45;\n long long v46;\n long long v47;\n unsigned int v48;\n int v49;\n int v50;\n int v52;\n int v53;\n int v54;\n int v55;\n int v56;\n unsigned int v57;\n int v58;\n unsigned int v59;\n unsigned int v60;\n int v61;\n int v62;\n int v63;\n int v64;\n int v65;\n v4 = (int)a4;\n if (!a3) return a4;\n LODWORD(v5) = a3;\n if (!a4) return a3;\n v6 = 0;\n v7 = a1 + (int)a3 - (long long)(int)a4;\n while (1) {\n v8 = *(uint8_t *)(v7 + v4 - 1);\n v9 = *(uint8_t *)(a2 + v4 - 1);\n v10 = (int)v5;\n v11 = v4 - 1;\n LODWORD(v5) = v5 - 1;\n if (v8 != v9) break;\n ++v6;\n if (!(uint32_t)v5) return (unsigned int)(v6 + v11);\n if (!(uint32_t)--v4) return (unsigned int)(v6 + v5);\n }\n v12 = v4;\n if ((uint32_t)v10 != 1) {\n v13 = 0;\n v14 = (int)v10 - 2;\n v15 = a2 + (int)v4 - (long long)(int)v5;\n while (1) {\n v16 = v4 - 1;\n v17 = v14;\n if (*(uint8_t *)(a1 + v14) != v9) break;\n ++v13;\n if (!(uint32_t)v14) goto LABEL_33;\n --v14;\n if ((uint32_t)v4 == 1) {\n v16 = v17;\n goto LABEL_33;\n }\n v9 = *(uint8_t *)(v15 + v14);\n LODWORD(v4) = v4 - 1;\n }\n v52 = v14 + 1;\n if ((uint32_t)v14) {\n v18 = (int)v4;\n v19 = 0;\n v20 = a1 + (int)v14 - v18;\n while (1) {\n v21 = v14;\n v22 = v18 - 1;\n v14 = (unsigned int)(v14 - 1);\n if (*(uint8_t *)(v18 + v20 - 1) != *(uint8_t *)(a2 + v18 - 1)) break;\n ++v19;\n if (!(uint32_t)v14) goto LABEL_21;\n if (!(uint32_t)--v18) {\n v22 = v14;\n goto LABEL_21;\n }\n }\n v65 = v13;\n v63 = v16;\n v59 = v21;\n v55 = sub_1290(a1, a2, v14);\n v23 = sub_1290(a1, a2, v59);\n v16 = v63;\n v13 = v65;\n if (v55 <= v23) v23 = v55;\n v22 = v23 + 1;\n LABEL_21:\n LODWORD(v4) = v22 + v19;\n }\n v24 = v52;\n if (v16) {\n v25 = v16;\n v26 = 0;\n LODWORD(v27) = v52;\n v28 = a1 + v52 - v25;\n while (1) {\n v29 = v27;\n v27 = (unsigned int)(v27 - 1);\n if (*(uint8_t *)(v25 + v28 - 1) != *(uint8_t *)(a2 + v25 - 1)) break;\n ++v26;\n if (!(uint32_t)v27) {\n v24 = v26 + v25 - 1;\n goto LABEL_30;\n }\n if (!(uint32_t)--v25) {\n v24 = v26 + v27;\n goto LABEL_30;\n }\n }\n v64 = v13;\n v62 = v26;\n v60 = v29;\n v53 = sub_1290(a1, a2, v27);\n v30 = sub_1290(a1, a2, v60);\n v13 = v64;\n if (v53 <= v30) v30 = v53;\n v24 = v62 + v30 + 1;\n }\n LABEL_30:\n if ((int)v4 > v24) LODWORD(v4) = v24;\n v16 = v4 + 1;\n LABEL_33:\n v12 = v13 + v16;\n }\n if (v11) {\n v5 = (int)v5;\n v31 = 0;\n v32 = a2 + v11 - v10;\n while (1) {\n v33 = v5;\n if (*(uint8_t *)(v32 + v5) != v8) break;\n --v11;\n ++v31;\n if (!(uint32_t)v5) {\n LODWORD(v10) = v11 + v31;\n goto LABEL_60;\n }\n --v5;\n if (!v11) {\n LODWORD(v10) = v31 + v33;\n goto LABEL_60;\n }\n v8 = *(uint8_t *)(a1 + v5);\n }\n v34 = v5 + 1;\n LODWORD(v35) = v11 - 1;\n v36 = v11;\n if ((uint32_t)v5) {\n v37 = v11;\n v38 = 0;\n LODWORD(v39) = v5;\n v40 = a1 + (int)v5 - (long long)v11;\n while (1) {\n v41 = v39;\n v42 = v37 - 1;\n v39 = (unsigned int)(v39 - 1);\n if (*(uint8_t *)(v37 + v40 - 1) != *(uint8_t *)(a2 + v37 - 1)) break;\n ++v38;\n if (!(uint32_t)v39) goto LABEL_48;\n if (!(uint32_t)--v37) {\n v42 = v39;\n goto LABEL_48;\n }\n }\n v61 = v12;\n v57 = v41;\n v56 = sub_1290(a1, a2, v39);\n v43 = sub_1290(a1, a2, v57);\n v44 = v56;\n v12 = v61;\n if (v56 > v43) v44 = v43;\n v42 = v44 + 1;\n LABEL_48:\n v36 = v42 + v38;\n LODWORD(v35) = v11 - 1;\n }\n if ((uint32_t)v35) {\n v35 = (int)v35;\n v45 = 0;\n LODWORD(v46) = v34;\n v47 = a1 + v34 - (long long)(int)v35;\n while (1) {\n v48 = v46;\n v46 = (unsigned int)(v46 - 1);\n if (*(uint8_t *)(v35 + v47 - 1) != *(uint8_t *)(a2 + v35 - 1)) break;\n ++v45;\n if (!(uint32_t)v46) {\n v34 = v45 + v35 - 1;\n goto LABEL_57;\n }\n if (!(uint32_t)--v35) {\n v34 = v45 + v46;\n goto LABEL_57;\n }\n }\n v58 = v12;\n v54 = sub_1290(a1, a2, v46);\n v49 = sub_1290(a1, a2, v48);\n v50 = v54;\n v12 = v58;\n if (v54 > v49) v50 = v49;\n v34 = v45 + v50 + 1;\n }\n LABEL_57:\n if (v36 > v34) v36 = v34;\n LODWORD(v10) = v31 + v36 + 1;\n }\nLABEL_60:\n if (v12 > (int)v10) v12 = v10;\n return (unsigned int)(v6 + v12 + 1);\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, unsigned int a3, unsigned int a4) {\n long long v4;\n long long v5;\n int v6;\n long long v7;\n char v8;\n char v9;\n long long v10;\n int v11;\n int v12;\n int v13;\n long long v14;\n long long v15;\n int v16;\n int v17;\n long long v18;\n int v19;\n long long v20;\n unsigned int v21;\n int v22;\n int v23;\n int v24;\n long long v25;\n int v26;\n long long v27;\n long long v28;\n unsigned int v29;\n int v30;\n int v31;\n long long v32;\n int v33;\n int v34;\n long long v35;\n int v36;\n long long v37;\n int v38;\n long long v39;\n long long v40;\n unsigned int v41;\n int v42;\n int v43;\n int v44;\n int v45;\n long long v46;\n long long v47;\n unsigned int v48;\n int v49;\n int v50;\n int v52;\n int v53;\n int v54;\n int v55;\n int v56;\n unsigned int v57;\n int v58;\n unsigned int v59;\n unsigned int v60;\n int v61;\n int v62;\n int v63;\n int v64;\n int v65;\n v4 = (int)a4;\n if (!a3) return a4;\n LODWORD(v5) = a3;\n if (!a4) return a3;\n v6 = 0;\n v7 = a1 + (int)a3 - (long long)(int)a4;\n while (1) {\n v8 = *(uint8_t *)(v7 + v4 - 1);\n v9 = *(uint8_t *)(a2 + v4 - 1);\n v10 = (int)v5;\n v11 = v4 - 1;\n LODWORD(v5) = v5 - 1;\n if (v8 != v9) break;\n ++v6;\n if (!(uint32_t)v5) return (unsigned int)(v6 + v11);\n if (!(uint32_t)--v4) return (unsigned int)(v6 + v5);\n }\n v12 = v4;\n if ((uint32_t)v10 != 1) {\n v13 = 0;\n v14 = (int)v10 - 2;\n v15 = a2 + (int)v4 - (long long)(int)v5;\n while (1) {\n v16 = v4 - 1;\n v17 = v14;\n if (*(uint8_t *)(a1 + v14) != v9) break;\n ++v13;\n if (!(uint32_t)v14) goto LABEL_33;\n --v14;\n if ((uint32_t)v4 == 1) {\n v16 = v17;\n goto LABEL_33;\n }\n v9 = *(uint8_t *)(v15 + v14);\n LODWORD(v4) = v4 - 1;\n }\n v52 = v14 + 1;\n if ((uint32_t)v14) {\n v18 = (int)v4;\n v19 = 0;\n v20 = a1 + (int)v14 - v18;\n while (1) {\n v21 = v14;\n v22 = v18 - 1;\n v14 = (unsigned int)(v14 - 1);\n if (*(uint8_t *)(v18 + v20 - 1) != *(uint8_t *)(a2 + v18 - 1)) break;\n ++v19;\n if (!(uint32_t)v14) goto LABEL_21;\n if (!(uint32_t)--v18) {\n v22 = v14;\n goto LABEL_21;\n }\n }\n v65 = v13;\n v63 = v16;\n v59 = v21;\n v55 = func0(a1, a2, v14);\n v23 = func0(a1, a2, v59);\n v16 = v63;\n v13 = v65;\n if (v55 <= v23) v23 = v55;\n v22 = v23 + 1;\n LABEL_21:\n LODWORD(v4) = v22 + v19;\n }\n v24 = v52;\n if (v16) {\n v25 = v16;\n v26 = 0;\n LODWORD(v27) = v52;\n v28 = a1 + v52 - v25;\n while (1) {\n v29 = v27;\n v27 = (unsigned int)(v27 - 1);\n if (*(uint8_t *)(v25 + v28 - 1) != *(uint8_t *)(a2 + v25 - 1)) break;\n ++v26;\n if (!(uint32_t)v27) {\n v24 = v26 + v25 - 1;\n goto LABEL_30;\n }\n if (!(uint32_t)--v25) {\n v24 = v26 + v27;\n goto LABEL_30;\n }\n }\n v64 = v13;\n v62 = v26;\n v60 = v29;\n v53 = func0(a1, a2, v27);\n v30 = func0(a1, a2, v60);\n v13 = v64;\n if (v53 <= v30) v30 = v53;\n v24 = v62 + v30 + 1;\n }\n LABEL_30:\n if ((int)v4 > v24) LODWORD(v4) = v24;\n v16 = v4 + 1;\n LABEL_33:\n v12 = v13 + v16;\n }\n if (v11) {\n v5 = (int)v5;\n v31 = 0;\n v32 = a2 + v11 - v10;\n while (1) {\n v33 = v5;\n if (*(uint8_t *)(v32 + v5) != v8) break;\n --v11;\n ++v31;\n if (!(uint32_t)v5) {\n LODWORD(v10) = v11 + v31;\n goto LABEL_60;\n }\n --v5;\n if (!v11) {\n LODWORD(v10) = v31 + v33;\n goto LABEL_60;\n }\n v8 = *(uint8_t *)(a1 + v5);\n }\n v34 = v5 + 1;\n LODWORD(v35) = v11 - 1;\n v36 = v11;\n if ((uint32_t)v5) {\n v37 = v11;\n v38 = 0;\n LODWORD(v39) = v5;\n v40 = a1 + (int)v5 - (long long)v11;\n while (1) {\n v41 = v39;\n v42 = v37 - 1;\n v39 = (unsigned int)(v39 - 1);\n if (*(uint8_t *)(v37 + v40 - 1) != *(uint8_t *)(a2 + v37 - 1)) break;\n ++v38;\n if (!(uint32_t)v39) goto LABEL_48;\n if (!(uint32_t)--v37) {\n v42 = v39;\n goto LABEL_48;\n }\n }\n v61 = v12;\n v57 = v41;\n v56 = func0(a1, a2, v39);\n v43 = func0(a1, a2, v57);\n v44 = v56;\n v12 = v61;\n if (v56 > v43) v44 = v43;\n v42 = v44 + 1;\n LABEL_48:\n v36 = v42 + v38;\n LODWORD(v35) = v11 - 1;\n }\n if ((uint32_t)v35) {\n v35 = (int)v35;\n v45 = 0;\n LODWORD(v46) = v34;\n v47 = a1 + v34 - (long long)(int)v35;\n while (1) {\n v48 = v46;\n v46 = (unsigned int)(v46 - 1);\n if (*(uint8_t *)(v35 + v47 - 1) != *(uint8_t *)(a2 + v35 - 1)) break;\n ++v45;\n if (!(uint32_t)v46) {\n v34 = v45 + v35 - 1;\n goto LABEL_57;\n }\n if (!(uint32_t)--v35) {\n v34 = v45 + v46;\n goto LABEL_57;\n }\n }\n v58 = v12;\n v54 = func0(a1, a2, v46);\n v49 = func0(a1, a2, v48);\n v50 = v54;\n v12 = v58;\n if (v54 > v49) v50 = v49;\n v34 = v45 + v50 + 1;\n }\n LABEL_57:\n if (v36 > v34) v36 = v34;\n LODWORD(v10) = v31 + v36 + 1;\n }\nLABEL_60:\n if (v12 > (int)v10) v12 = v10;\n return (unsigned int)(v6 + v12 + 1);\n}" + }, + { + "index": 924, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int x, int y) {\n if (x > y) {\n return x;\n }\n return y;\n}", + "test": "int main() {\n\n assert(func0(10, 20) == 20);\n\n assert(func0(19, 15) == 19);\n\n assert(func0(-10, -20) == -10);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov %esi,-0x8(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x8(%rbp),%eax\njle 1164 \nmov -0x4(%rbp),%eax\njmp 1167 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_8]\njle short loc_1164\nmov eax, [rbp+var_4]\njmp short loc_1167\nloc_1164:\nmov eax, [rbp+var_8]\nloc_1167:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1, unsigned int a2)\n{\n if ( (int)a1 <= (int)a2 )\n return a2;\n else\n return a1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_8]\njle short loc_1164\nmov eax, [rbp+var_4]\njmp short loc_1167\nloc_1164:\nmov eax, [rbp+var_8]\nloc_1167:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(unsigned int a1, unsigned int a2)\n{\n if ( (int)a1 <= (int)a2 )\n return a2;\n else\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(unsigned int a1, unsigned int a2) {\n if ((int)a1 <= (int)a2)\n return a2;\n else\n return a1;\n}", + "ida_pseudo_norm": "long long func0(unsigned int a1, unsigned int a2) {\n if ((int)a1 <= (int)a2)\n return a2;\n else\n return a1;\n}" + }, + { + "index": 925, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int nums[], int size) {\n int product = 1;\n for (int i = 0; i < size; i++) {\n product *= nums[i];\n }\n return product;\n}", + "test": "int main() {\n\n int nums1[] = {4, 3, 2, 2, -1, 18};\n\n assert(func0(nums1, 6) == -864);\n\n\n\n int nums2[] = {1, 2, 3};\n\n assert(func0(nums2, 3) == 6);\n\n \n\n int nums3[] = {-2, -4, -6};\n\n assert(func0(nums3, 3) == -48);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x1,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11ab \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov -0x8(%rbp),%edx\nimul %edx,%eax\nmov %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1188 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 1\nmov [rbp+var_4], 0\njmp short loc_11AB\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_8]\nimul eax, edx\nmov [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_11AB:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 1;\n for ( i = 0; i < a2; ++i )\n v3 *= *(_DWORD *)(4LL * i + a1);\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 1\nmov [rbp+var_4], 0\njmp short loc_11AB\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov edx, [rbp+var_8]\nimul eax, edx\nmov [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_11AB:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 1;\n for ( i = 0; i < a2; ++i )\n v3 *= *(_DWORD *)(4LL * i + a1);\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 1;\n for (i = 0; i < a2; ++i) v3 *= *(uint32_t *)(4LL * i + a1);\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 1;\n for (i = 0; i < a2; ++i) v3 *= *(uint32_t *)(4LL * i + a1);\n return v3;\n}" + }, + { + "index": 925, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int nums[], int size) {\n int product = 1;\n for (int i = 0; i < size; i++) {\n product *= nums[i];\n }\n return product;\n}", + "test": "int main() {\n\n int nums1[] = {4, 3, 2, 2, -1, 18};\n\n assert(func0(nums1, 6) == -864);\n\n\n\n int nums2[] = {1, 2, 3};\n\n assert(func0(nums2, 3) == 6);\n\n \n\n int nums3[] = {-2, -4, -6};\n\n assert(func0(nums3, 3) == -48);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1190 \nmov %rdi,%rax\nlea -0x1(%rsi),%edx\nlea 0x4(%rdi,%rdx,4),%rcx\nmov $0x1,%edx\nimul (%rax),%edx\nadd $0x4,%rax\ncmp %rcx,%rax\njne 1181 \nmov %edx,%eax\nretq\nmov $0x1,%edx\njmp 118d \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_118F\nmov rax, rdi\nmovsxd rsi, esi\nlea rcx, [rdi+rsi*4]\nmov edx, 1\nloc_1180:\nimul edx, [rax]\nadd rax, 4\ncmp rax, rcx\njnz short loc_1180\nloc_118C:\nmov eax, edx\nretn\nloc_118F:\nmov edx, 1\njmp short loc_118C", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n unsigned int v3; // edx\n\n if ( a2 <= 0 )\n {\n return 1;\n }\n else\n {\n v2 = a1;\n v3 = 1;\n do\n v3 *= *v2++;\n while ( v2 != &a1[a2] );\n }\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_118F\nmov rax, rdi\nmovsxd rsi, esi\nlea rcx, [rdi+rsi*4]\nmov edx, 1\nloc_1180:\nimul edx, [rax]\nadd rax, 4\ncmp rax, rcx\njnz short loc_1180\nloc_118C:\nmov eax, edx\nretn\nloc_118F:\nmov edx, 1\njmp short loc_118C", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n unsigned int v3; // edx\n\n if ( a2 <= 0 )\n {\n return 1;\n }\n else\n {\n v2 = a1;\n v3 = 1;\n do\n v3 *= *v2++;\n while ( v2 != &a1[a2] );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2) {\n uint32_t *v2;\n unsigned int v3;\n if (a2 <= 0) {\n return 1;\n } else {\n v2 = a1;\n v3 = 1;\n do\n v3 *= *v2++;\n while (v2 != &a1[a2]);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n unsigned int v3;\n if (a2 <= 0) {\n return 1;\n } else {\n v2 = a1;\n v3 = 1;\n do\n v3 *= *v2++;\n while (v2 != &a1[a2]);\n }\n return v3;\n}" + }, + { + "index": 926, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nint binomial_coeffi(int n, int k) {\n\n if (k == 0 || k == n)\n\n return 1;\n\n return binomial_coeffi(n - 1, k - 1) + binomial_coeffi(n - 1, k);\n\n}\n\n\n\n", + "func": "int func0(int n, int m) {\n if (n == 0 && m == 0) return 1;\n if (n == 1 && m == 0) return 0;\n if (m == 0) return (n - 1) * (func0(n - 1, 0) + func0(n - 2, 0));\n return binomial_coeffi(n, m) * func0(n - m, 0);\n}", + "test": "int main() {\n\n assert(func0(7, 2) == 924);\n\n assert(func0(3, 0) == 2);\n\n assert(func0(3, 1) == 3);\n\n\n\n printf(\"All test cases passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r12\npush %rbx\nsub $0x10,%rsp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\ncmpl $0x0,-0x14(%rbp)\njne 11eb \ncmpl $0x0,-0x18(%rbp)\njne 11eb \nmov $0x1,%eax\njmp 125f \ncmpl $0x1,-0x14(%rbp)\njne 11fe \ncmpl $0x0,-0x18(%rbp)\njne 11fe \nmov $0x0,%eax\njmp 125f \ncmpl $0x0,-0x18(%rbp)\njne 1239 \nmov -0x14(%rbp),%eax\nlea -0x1(%rax),%r12d\nmov -0x14(%rbp),%eax\nsub $0x1,%eax\nmov $0x0,%esi\nmov %eax,%edi\ncallq 11c3 \nmov %eax,%ebx\nmov -0x14(%rbp),%eax\nsub $0x2,%eax\nmov $0x0,%esi\nmov %eax,%edi\ncallq 11c3 \nadd %ebx,%eax\nimul %r12d,%eax\njmp 125f \nmov -0x18(%rbp),%edx\nmov -0x14(%rbp),%eax\nmov %edx,%esi\nmov %eax,%edi\ncallq 1169 \nmov %eax,%ebx\nmov -0x14(%rbp),%eax\nsub -0x18(%rbp),%eax\nmov $0x0,%esi\nmov %eax,%edi\ncallq 11c3 \nimul %ebx,%eax\nadd $0x10,%rsp\npop %rbx\npop %r12\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r12\npush rbx\nsub rsp, 10h\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\ncmp [rbp+var_14], 0\njnz short loc_11EA\ncmp [rbp+var_18], 0\njnz short loc_11EA\nmov eax, 1\njmp short loc_125E\nloc_11EA:\ncmp [rbp+var_14], 1\njnz short loc_11FD\ncmp [rbp+var_18], 0\njnz short loc_11FD\nmov eax, 0\njmp short loc_125E\nloc_11FD:\ncmp [rbp+var_18], 0\njnz short loc_1238\nmov eax, [rbp+var_14]\nlea r12d, [rax-1]\nmov eax, [rbp+var_14]\nsub eax, 1\nmov esi, 0\nmov edi, eax\ncall func0\nmov ebx, eax\nmov eax, [rbp+var_14]\nsub eax, 2\nmov esi, 0\nmov edi, eax\ncall func0\nadd eax, ebx\nimul eax, r12d\njmp short loc_125E\nloc_1238:\nmov edx, [rbp+var_18]\nmov eax, [rbp+var_14]\nmov esi, edx\nmov edi, eax\ncall binomial_coeffi\nmov ebx, eax\nmov eax, [rbp+var_14]\nsub eax, [rbp+var_18]\nmov esi, 0\nmov edi, eax\ncall func0\nimul eax, ebx\nloc_125E:\nadd rsp, 10h\npop rbx\npop r12\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1, unsigned int a2)\n{\n int v3; // ebx\n int v4; // ebx\n\n if ( !a1 && !a2 )\n return 1LL;\n if ( a1 == 1 && !a2 )\n return 0LL;\n if ( a2 )\n {\n v4 = binomial_coeffi(a1, a2);\n return v4 * (unsigned int)func0(a1 - a2, 0LL);\n }\n else\n {\n v3 = func0(a1 - 1, 0LL);\n return (a1 - 1) * (v3 + (unsigned int)func0(a1 - 2, 0LL));\n }\n}", + "ida_strip_asm": "sub_11C2:\nendbr64\npush rbp\nmov rbp, rsp\npush r12\npush rbx\nsub rsp, 10h\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\ncmp [rbp+var_14], 0\njnz short loc_11EA\ncmp [rbp+var_18], 0\njnz short loc_11EA\nmov eax, 1\njmp short loc_125E\nloc_11EA:\ncmp [rbp+var_14], 1\njnz short loc_11FD\ncmp [rbp+var_18], 0\njnz short loc_11FD\nmov eax, 0\njmp short loc_125E\nloc_11FD:\ncmp [rbp+var_18], 0\njnz short loc_1238\nmov eax, [rbp+var_14]\nlea r12d, [rax-1]\nmov eax, [rbp+var_14]\nsub eax, 1\nmov esi, 0\nmov edi, eax\ncall sub_11C2\nmov ebx, eax\nmov eax, [rbp+var_14]\nsub eax, 2\nmov esi, 0\nmov edi, eax\ncall sub_11C2\nadd eax, ebx\nimul eax, r12d\njmp short loc_125E\nloc_1238:\nmov edx, [rbp+var_18]\nmov eax, [rbp+var_14]\nmov esi, edx\nmov edi, eax\ncall sub_1169\nmov ebx, eax\nmov eax, [rbp+var_14]\nsub eax, [rbp+var_18]\nmov esi, 0\nmov edi, eax\ncall sub_11C2\nimul eax, ebx\nloc_125E:\nadd rsp, 10h\npop rbx\npop r12\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11C2(unsigned int a1, unsigned int a2)\n{\n int v3; // ebx\n int v4; // ebx\n\n if ( !a1 && !a2 )\n return 1LL;\n if ( a1 == 1 && !a2 )\n return 0LL;\n if ( a2 )\n {\n v4 = sub_1169(a1, a2);\n return v4 * (unsigned int)sub_11C2(a1 - a2, 0LL);\n }\n else\n {\n v3 = sub_11C2(a1 - 1, 0LL);\n return (a1 - 1) * (v3 + (unsigned int)sub_11C2(a1 - 2, 0LL));\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11C2(unsigned int a1, unsigned int a2) {\n int v3;\n int v4;\n if (!a1 && !a2) return 1LL;\n if (a1 == 1 && !a2) return 0LL;\n if (a2) {\n v4 = sub_1169(a1, a2);\n return v4 * (unsigned int)sub_11C2(a1 - a2, 0LL);\n } else {\n v3 = sub_11C2(a1 - 1, 0LL);\n return (a1 - 1) * (v3 + (unsigned int)sub_11C2(a1 - 2, 0LL));\n }\n}", + "ida_pseudo_norm": "long long func0(unsigned int a1, unsigned int a2) {\n int v3;\n int v4;\n if (!a1 && !a2) return 1LL;\n if (a1 == 1 && !a2) return 0LL;\n if (a2) {\n v4 = binomial_coeffi(a1, a2);\n return v4 * (unsigned int)func0(a1 - a2, 0LL);\n } else {\n v3 = func0(a1 - 1, 0LL);\n return (a1 - 1) * (v3 + (unsigned int)func0(a1 - 2, 0LL));\n }\n}" + }, + { + "index": 926, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nint binomial_coeffi(int n, int k) {\n\n if (k == 0 || k == n)\n\n return 1;\n\n return binomial_coeffi(n - 1, k - 1) + binomial_coeffi(n - 1, k);\n\n}\n\n\n\n", + "func": "int func0(int n, int m) {\n if (n == 0 && m == 0) return 1;\n if (n == 1 && m == 0) return 0;\n if (m == 0) return (n - 1) * (func0(n - 1, 0) + func0(n - 2, 0));\n return binomial_coeffi(n, m) * func0(n - m, 0);\n}", + "test": "int main() {\n\n assert(func0(7, 2) == 924);\n\n assert(func0(3, 0) == 2);\n\n assert(func0(3, 1) == 3);\n\n\n\n printf(\"All test cases passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x1,%eax\nmov %edi,%edx\nor %esi,%edx\nje 121b \npush %r12\npush %rbp\npush %rbx\nmov %edi,%ebx\nmov %esi,%ebp\ncmp $0x1,%edi\njne 11cc \nmov $0x0,%eax\ntest %esi,%esi\nje 11ee \ntest %ebp,%ebp\nje 11f3 \nmov %ebp,%esi\nmov %ebx,%edi\ncallq 1169 \nmov %eax,%r12d\nsub %ebp,%ebx\nmov %ebx,%edi\nmov $0x0,%esi\ncallq 11a7 \nimul %r12d,%eax\npop %rbx\npop %rbp\npop %r12\nretq\nlea -0x1(%rbx),%r12d\nmov $0x0,%esi\nmov %r12d,%edi\ncallq 11a7 \nmov %eax,%ebp\nlea -0x2(%rbx),%edi\nmov $0x0,%esi\ncallq 11a7 \nadd %ebp,%eax\nimul %r12d,%eax\njmp 11ee \nretq\n", + "ida_asm": "func0:\nendbr64\nmov eax, 1\nmov edx, edi\nor edx, esi\njz short locret_121B\npush r12\npush rbp\npush rbx\nmov ebx, edi\nmov ebp, esi\ncmp edi, 1\njnz short loc_11CC\nmov eax, 0\ntest esi, esi\njz short loc_11EE\nloc_11CC:\ntest ebp, ebp\njz short loc_11F3\nmov esi, ebp\nmov edi, ebx\ncall binomial_coeffi\nmov r12d, eax\nsub ebx, ebp\nmov edi, ebx\nmov esi, 0\ncall func0\nimul eax, r12d\nloc_11EE:\npop rbx\npop rbp\npop r12\nretn\nloc_11F3:\nlea r12d, [rbx-1]\nmov esi, 0\nmov edi, r12d\ncall func0\nmov ebp, eax\nlea edi, [rbx-2]\nmov esi, 0\ncall func0\nadd eax, ebp\nimul eax, r12d\njmp short loc_11EE\nlocret_121B:\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1, unsigned int a2)\n{\n __int64 result; // rax\n int v3; // r12d\n int v4; // ebp\n\n result = 1LL;\n if ( a2 | a1 )\n {\n if ( a1 != 1 || (result = 0LL, a2) )\n {\n if ( a2 )\n {\n v3 = binomial_coeffi(a1, a2);\n return v3 * (unsigned int)func0(a1 - a2, 0LL);\n }\n else\n {\n v4 = func0(a1 - 1, 0LL);\n return (a1 - 1) * (v4 + (unsigned int)func0(a1 - 2, 0LL));\n }\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_11A7:\nendbr64\nmov eax, 1\nmov edx, edi\nor edx, esi\njz short locret_121B\npush r12\npush rbp\npush rbx\nmov ebx, edi\nmov ebp, esi\ncmp edi, 1\njnz short loc_11CC\nmov eax, 0\ntest esi, esi\njz short loc_11EE\nloc_11CC:\ntest ebp, ebp\njz short loc_11F3\nmov esi, ebp\nmov edi, ebx\ncall sub_1169\nmov r12d, eax\nsub ebx, ebp\nmov edi, ebx\nmov esi, 0\ncall sub_11A7\nimul eax, r12d\nloc_11EE:\npop rbx\npop rbp\npop r12\nretn\nloc_11F3:\nlea r12d, [rbx-1]\nmov esi, 0\nmov edi, r12d\ncall sub_11A7\nmov ebp, eax\nlea edi, [rbx-2]\nmov esi, 0\ncall sub_11A7\nadd eax, ebp\nimul eax, r12d\njmp short loc_11EE\nlocret_121B:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11A7(unsigned int a1, unsigned int a2)\n{\n __int64 result; // rax\n int v3; // r12d\n int v4; // ebp\n\n result = 1LL;\n if ( a2 | a1 )\n {\n if ( a1 != 1 || (result = 0LL, a2) )\n {\n if ( a2 )\n {\n v3 = sub_1169(a1, a2);\n return v3 * (unsigned int)sub_11A7(a1 - a2, 0LL);\n }\n else\n {\n v4 = sub_11A7(a1 - 1, 0LL);\n return (a1 - 1) * (v4 + (unsigned int)sub_11A7(a1 - 2, 0LL));\n }\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A7(unsigned int a1, unsigned int a2) {\n long long result;\n int v3;\n int v4;\n result = 1LL;\n if (a2 | a1) {\n if (a1 != 1 || (result = 0LL, a2)) {\n if (a2) {\n v3 = sub_1169(a1, a2);\n return v3 * (unsigned int)sub_11A7(a1 - a2, 0LL);\n } else {\n v4 = sub_11A7(a1 - 1, 0LL);\n return (a1 - 1) * (v4 + (unsigned int)sub_11A7(a1 - 2, 0LL));\n }\n }\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(unsigned int a1, unsigned int a2) {\n long long result;\n int v3;\n int v4;\n result = 1LL;\n if (a2 | a1) {\n if (a1 != 1 || (result = 0LL, a2)) {\n if (a2) {\n v3 = binomial_coeffi(a1, a2);\n return v3 * (unsigned int)func0(a1 - a2, 0LL);\n } else {\n v4 = func0(a1 - 1, 0LL);\n return (a1 - 1) * (v4 + (unsigned int)func0(a1 - 2, 0LL));\n }\n }\n }\n return result;\n}" + }, + { + "index": 926, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nint binomial_coeffi(int n, int k) {\n\n if (k == 0 || k == n)\n\n return 1;\n\n return binomial_coeffi(n - 1, k - 1) + binomial_coeffi(n - 1, k);\n\n}\n\n\n\n", + "func": "int func0(int n, int m) {\n if (n == 0 && m == 0) return 1;\n if (n == 1 && m == 0) return 0;\n if (m == 0) return (n - 1) * (func0(n - 1, 0) + func0(n - 2, 0));\n return binomial_coeffi(n, m) * func0(n - m, 0);\n}", + "test": "int main() {\n\n assert(func0(7, 2) == 924);\n\n assert(func0(3, 0) == 2);\n\n assert(func0(3, 1) == 3);\n\n\n\n printf(\"All test cases passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov %edi,%eax\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nor %esi,%eax\nje 1320 \nmov %edi,%ebx\nmov %esi,%edx\ncmp $0x1,%edi\njne 1310 \ntest %esi,%esi\nje 1338 \nmov %ebx,%edi\nmov %edx,%esi\nxor %r12d,%r12d\ncallq 1230 \nsub %edx,%ebx\nmov %eax,%ebp\ntest %ebx,%ebx\nje 12fd \ncmp $0x1,%ebx\nje 1300 \nlea -0x1(%rbx),%r13d\nxor %esi,%esi\nsub $0x2,%ebx\nmov %r13d,%edi\ncallq 12a0 \nimul %r13d,%eax\nimul %ebp,%eax\nimul %r13d,%ebp\nadd %eax,%r12d\ntest %ebx,%ebx\njne 12d5 \nadd %ebp,%r12d\nadd $0x8,%rsp\nmov %r12d,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nxchg %ax,%ax\ntest %esi,%esi\njne 12c1 \nxor %r12d,%r12d\nmov $0x1,%ebp\njmp 12da \nxchg %ax,%ax\nadd $0x8,%rsp\nmov $0x1,%r12d\npop %rbx\nmov %r12d,%eax\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax)\nxor %r12d,%r12d\njmp 1300 \nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\nmov eax, edi\npush r14\nor eax, esi\npush r13\npush r12\npush rbp\npush rbx\njz loc_16B8\nmov r12d, edi\nmov r13d, esi\ncmp edi, 1\njnz short loc_1698\ntest esi, esi\njz loc_16D0\nloc_1629:\ncmp r12d, r13d\njz short loc_16A8\nlea r14d, [r13-1]\nmov ebx, r12d\nxor ebp, ebp\nloc_1637:\nsub ebx, 1\nmov esi, r14d\nmov edi, ebx\ncall binomial_coeffi\nadd ebp, eax\ncmp r13d, ebx\njnz short loc_1637\nsub r12d, r13d\nadd ebp, 1\nxor ebx, ebx\ntest r12d, r12d\njz short loc_1688\nloc_1658:\ncmp r12d, 1\njz short loc_168A\nloc_165E:\nlea r13d, [r12-1]\nxor esi, esi\nsub r12d, 2\nmov edi, r13d\ncall func0\nimul eax, r13d\nimul eax, ebp\nimul ebp, r13d\nadd ebx, eax\ntest r12d, r12d\njnz short loc_1658\nnop dword ptr [rax+rax+00h]\nloc_1688:\nadd ebx, ebp\nloc_168A:\nmov eax, ebx\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1698:\ntest esi, esi\njnz short loc_1629\nxor ebx, ebx\nmov ebp, 1\njmp short loc_165E\nloc_16A8:\nxor ebx, ebx\nmov ebp, 1\njmp short loc_1688\nloc_16B8:\nmov ebx, 1\nmov eax, ebx\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_16D0:\nxor ebx, ebx\njmp short loc_168A", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n int v2; // r12d\n int v3; // ebx\n int v4; // ebp\n int v5; // ebp\n unsigned int v6; // ebx\n unsigned int v7; // r13d\n int v8; // eax\n\n if ( a2 | a1 )\n {\n v2 = a1;\n if ( a1 == 1 )\n {\n if ( !a2 )\n return 0;\n }\n else if ( !a2 )\n {\n v6 = 0;\n v5 = 1;\n goto LABEL_9;\n }\n if ( a1 == a2 )\n {\n v6 = 0;\n v5 = 1;\n }\n else\n {\n v3 = a1;\n v4 = 0;\n do\n v4 += binomial_coeffi((unsigned int)--v3, (unsigned int)(a2 - 1));\n while ( a2 != v3 );\n v2 = a1 - a2;\n v5 = v4 + 1;\n v6 = 0;\n if ( a1 != a2 )\n {\n while ( v2 != 1 )\n {\nLABEL_9:\n v7 = v2 - 1;\n v2 -= 2;\n v8 = v5 * v7 * func0(v7, 0LL);\n v5 *= v7;\n v6 += v8;\n if ( !v2 )\n goto LABEL_10;\n }\n return v6;\n }\n }\nLABEL_10:\n v6 += v5;\n return v6;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1600:\nendbr64\nmov eax, edi\npush r14\nor eax, esi\npush r13\npush r12\npush rbp\npush rbx\njz loc_16B8\nmov r12d, edi\nmov r13d, esi\ncmp edi, 1\njnz short loc_1698\ntest esi, esi\njz loc_16D0\nloc_1629:\ncmp r12d, r13d\njz short loc_16A8\nlea r14d, [r13-1]\nmov ebx, r12d\nxor ebp, ebp\nloc_1637:\nsub ebx, 1\nmov esi, r14d\nmov edi, ebx\ncall sub_1230\nadd ebp, eax\ncmp r13d, ebx\njnz short loc_1637\nsub r12d, r13d\nadd ebp, 1\nxor ebx, ebx\ntest r12d, r12d\njz short loc_1688\nloc_1658:\ncmp r12d, 1\njz short loc_168A\nloc_165E:\nlea r13d, [r12-1]\nxor esi, esi\nsub r12d, 2\nmov edi, r13d\ncall sub_1600\nimul eax, r13d\nimul eax, ebp\nimul ebp, r13d\nadd ebx, eax\ntest r12d, r12d\njnz short loc_1658\nnop dword ptr [rax+rax+00h]\nloc_1688:\nadd ebx, ebp\nloc_168A:\nmov eax, ebx\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1698:\ntest esi, esi\njnz short loc_1629\nxor ebx, ebx\nmov ebp, 1\njmp short loc_165E\nloc_16A8:\nxor ebx, ebx\nmov ebp, 1\njmp short loc_1688\nloc_16B8:\nmov ebx, 1\nmov eax, ebx\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_16D0:\nxor ebx, ebx\njmp short loc_168A", + "ida_strip_pseudo": "__int64 __fastcall sub_1600(int a1, int a2)\n{\n int v2; // r12d\n int v3; // ebx\n int v4; // ebp\n int v5; // ebp\n unsigned int v6; // ebx\n unsigned int v7; // r13d\n int v8; // eax\n\n if ( a2 | a1 )\n {\n v2 = a1;\n if ( a1 == 1 )\n {\n if ( !a2 )\n return 0;\n }\n else if ( !a2 )\n {\n v6 = 0;\n v5 = 1;\n goto LABEL_9;\n }\n if ( a1 == a2 )\n {\n v6 = 0;\n v5 = 1;\n }\n else\n {\n v3 = a1;\n v4 = 0;\n do\n v4 += sub_1230((unsigned int)--v3, (unsigned int)(a2 - 1));\n while ( a2 != v3 );\n v2 = a1 - a2;\n v5 = v4 + 1;\n v6 = 0;\n if ( a1 != a2 )\n {\n while ( v2 != 1 )\n {\nLABEL_9:\n v7 = v2 - 1;\n v2 -= 2;\n v8 = v5 * v7 * sub_1600(v7, 0LL);\n v5 *= v7;\n v6 += v8;\n if ( !v2 )\n goto LABEL_10;\n }\n return v6;\n }\n }\nLABEL_10:\n v6 += v5;\n return v6;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1600(int a1, int a2) {\n int v2;\n int v3;\n int v4;\n int v5;\n unsigned int v6;\n unsigned int v7;\n int v8;\n if (a2 | a1) {\n v2 = a1;\n if (a1 == 1) {\n if (!a2) return 0;\n } else if (!a2) {\n v6 = 0;\n v5 = 1;\n goto LABEL_9;\n }\n if (a1 == a2) {\n v6 = 0;\n v5 = 1;\n } else {\n v3 = a1;\n v4 = 0;\n do\n v4 += sub_1230((unsigned int)--v3, (unsigned int)(a2 - 1));\n while (a2 != v3);\n v2 = a1 - a2;\n v5 = v4 + 1;\n v6 = 0;\n if (a1 != a2) {\n while (v2 != 1) {\n LABEL_9:\n v7 = v2 - 1;\n v2 -= 2;\n v8 = v5 * v7 * sub_1600(v7, 0LL);\n v5 *= v7;\n v6 += v8;\n if (!v2) goto LABEL_10;\n }\n return v6;\n }\n }\n LABEL_10:\n v6 += v5;\n return v6;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n int v2;\n int v3;\n int v4;\n int v5;\n unsigned int v6;\n unsigned int v7;\n int v8;\n if (a2 | a1) {\n v2 = a1;\n if (a1 == 1) {\n if (!a2) return 0;\n } else if (!a2) {\n v6 = 0;\n v5 = 1;\n goto LABEL_9;\n }\n if (a1 == a2) {\n v6 = 0;\n v5 = 1;\n } else {\n v3 = a1;\n v4 = 0;\n do\n v4 += binomial_coeffi((unsigned int)--v3, (unsigned int)(a2 - 1));\n while (a2 != v3);\n v2 = a1 - a2;\n v5 = v4 + 1;\n v6 = 0;\n if (a1 != a2) {\n while (v2 != 1) {\n LABEL_9:\n v7 = v2 - 1;\n v2 -= 2;\n v8 = v5 * v7 * func0(v7, 0LL);\n v5 *= v7;\n v6 += v8;\n if (!v2) goto LABEL_10;\n }\n return v6;\n }\n }\n LABEL_10:\n v6 += v5;\n return v6;\n }\n return 1LL;\n}" + }, + { + "index": 926, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nint binomial_coeffi(int n, int k) {\n\n if (k == 0 || k == n)\n\n return 1;\n\n return binomial_coeffi(n - 1, k - 1) + binomial_coeffi(n - 1, k);\n\n}\n\n\n\n", + "func": "int func0(int n, int m) {\n if (n == 0 && m == 0) return 1;\n if (n == 1 && m == 0) return 0;\n if (m == 0) return (n - 1) * (func0(n - 1, 0) + func0(n - 2, 0));\n return binomial_coeffi(n, m) * func0(n - m, 0);\n}", + "test": "int main() {\n\n assert(func0(7, 2) == 924);\n\n assert(func0(3, 0) == 2);\n\n assert(func0(3, 1) == 3);\n\n\n\n printf(\"All test cases passed!\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov %edi,%eax\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nor %esi,%eax\nje 1350 \ntest %esi,%esi\nmov %edi,%ebx\nmov %esi,%ecx\nsete %dl\nmov %edx,%eax\ncmp $0x1,%edi\njne 12cc \ntest %dl,%dl\njne 1348 \nmov $0x1,%ebp\nxor %r12d,%r12d\ntest %ecx,%ecx\nje 1310 \ncmp %ecx,%ebx\nje 1305 \nlea -0x1(%rcx),%r9d\nmov %ebx,%edx\nxor %r8d,%r8d\ntest %al,%al\njne 1305 \nsub $0x1,%edx\nmov %r9d,%esi\nmov %edx,%edi\ncallq 1230 \nadd %eax,%r8d\ncmp %ecx,%edx\njne 12e9 \nadd $0x1,%r8d\nimul %r8d,%ebp\nsub %ecx,%ebx\ntest %ebx,%ebx\nje 1333 \ncmp $0x1,%ebx\nje 1336 \nlea -0x1(%rbx),%r13d\nxor %esi,%esi\nsub $0x2,%ebx\nmov %r13d,%edi\ncallq 12a0 \nimul %r13d,%eax\nimul %ebp,%eax\nimul %r13d,%ebp\nadd %eax,%r12d\ntest %ebx,%ebx\njne 130b \nadd %ebp,%r12d\nadd $0x8,%rsp\nmov %r12d,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax)\nxor %r12d,%r12d\njmp 1336 \nnopl (%rax)\nadd $0x8,%rsp\nmov $0x1,%r12d\npop %rbx\nmov %r12d,%eax\npop %rbp\npop %r12\npop %r13\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\nmov eax, edi\npush r14\nor eax, esi\npush r13\npush r12\npush rbp\npush rbx\njz loc_16B8\nmov r12d, edi\nmov r13d, esi\ncmp edi, 1\njnz short loc_1698\ntest esi, esi\njz loc_16D0\nloc_1629:\ncmp r12d, r13d\njz short loc_16A8\nlea r14d, [r13-1]\nmov ebx, r12d\nxor ebp, ebp\nloc_1637:\nsub ebx, 1\nmov esi, r14d\nmov edi, ebx\ncall binomial_coeffi\nadd ebp, eax\ncmp r13d, ebx\njnz short loc_1637\nsub r12d, r13d\nadd ebp, 1\nxor ebx, ebx\ntest r12d, r12d\njz short loc_1688\nloc_1658:\ncmp r12d, 1\njz short loc_168A\nloc_165E:\nlea r13d, [r12-1]\nxor esi, esi\nsub r12d, 2\nmov edi, r13d\ncall func0\nimul eax, r13d\nimul eax, ebp\nimul ebp, r13d\nadd ebx, eax\ntest r12d, r12d\njnz short loc_1658\nnop dword ptr [rax+rax+00h]\nloc_1688:\nadd ebx, ebp\nloc_168A:\nmov eax, ebx\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1698:\ntest esi, esi\njnz short loc_1629\nxor ebx, ebx\nmov ebp, 1\njmp short loc_165E\nloc_16A8:\nxor ebx, ebx\nmov ebp, 1\njmp short loc_1688\nloc_16B8:\nmov ebx, 1\nmov eax, ebx\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_16D0:\nxor ebx, ebx\njmp short loc_168A", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n int v2; // r12d\n int v3; // ebx\n int v4; // ebp\n int v5; // ebp\n unsigned int v6; // ebx\n unsigned int v7; // r13d\n int v8; // eax\n\n if ( a2 | a1 )\n {\n v2 = a1;\n if ( a1 == 1 )\n {\n if ( !a2 )\n return 0;\n }\n else if ( !a2 )\n {\n v6 = 0;\n v5 = 1;\n goto LABEL_9;\n }\n if ( a1 == a2 )\n {\n v6 = 0;\n v5 = 1;\n }\n else\n {\n v3 = a1;\n v4 = 0;\n do\n v4 += binomial_coeffi((unsigned int)--v3, (unsigned int)(a2 - 1));\n while ( a2 != v3 );\n v2 = a1 - a2;\n v5 = v4 + 1;\n v6 = 0;\n if ( a1 != a2 )\n {\n while ( v2 != 1 )\n {\nLABEL_9:\n v7 = v2 - 1;\n v2 -= 2;\n v8 = v5 * v7 * func0(v7, 0LL);\n v5 *= v7;\n v6 += v8;\n if ( !v2 )\n goto LABEL_10;\n }\n return v6;\n }\n }\nLABEL_10:\n v6 += v5;\n return v6;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1600:\nendbr64\nmov eax, edi\npush r14\nor eax, esi\npush r13\npush r12\npush rbp\npush rbx\njz loc_16B8\nmov r12d, edi\nmov r13d, esi\ncmp edi, 1\njnz short loc_1698\ntest esi, esi\njz loc_16D0\nloc_1629:\ncmp r12d, r13d\njz short loc_16A8\nlea r14d, [r13-1]\nmov ebx, r12d\nxor ebp, ebp\nloc_1637:\nsub ebx, 1\nmov esi, r14d\nmov edi, ebx\ncall sub_1230\nadd ebp, eax\ncmp r13d, ebx\njnz short loc_1637\nsub r12d, r13d\nadd ebp, 1\nxor ebx, ebx\ntest r12d, r12d\njz short loc_1688\nloc_1658:\ncmp r12d, 1\njz short loc_168A\nloc_165E:\nlea r13d, [r12-1]\nxor esi, esi\nsub r12d, 2\nmov edi, r13d\ncall sub_1600\nimul eax, r13d\nimul eax, ebp\nimul ebp, r13d\nadd ebx, eax\ntest r12d, r12d\njnz short loc_1658\nnop dword ptr [rax+rax+00h]\nloc_1688:\nadd ebx, ebp\nloc_168A:\nmov eax, ebx\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1698:\ntest esi, esi\njnz short loc_1629\nxor ebx, ebx\nmov ebp, 1\njmp short loc_165E\nloc_16A8:\nxor ebx, ebx\nmov ebp, 1\njmp short loc_1688\nloc_16B8:\nmov ebx, 1\nmov eax, ebx\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_16D0:\nxor ebx, ebx\njmp short loc_168A", + "ida_strip_pseudo": "__int64 __fastcall sub_1600(int a1, int a2)\n{\n int v2; // r12d\n int v3; // ebx\n int v4; // ebp\n int v5; // ebp\n unsigned int v6; // ebx\n unsigned int v7; // r13d\n int v8; // eax\n\n if ( a2 | a1 )\n {\n v2 = a1;\n if ( a1 == 1 )\n {\n if ( !a2 )\n return 0;\n }\n else if ( !a2 )\n {\n v6 = 0;\n v5 = 1;\n goto LABEL_9;\n }\n if ( a1 == a2 )\n {\n v6 = 0;\n v5 = 1;\n }\n else\n {\n v3 = a1;\n v4 = 0;\n do\n v4 += sub_1230((unsigned int)--v3, (unsigned int)(a2 - 1));\n while ( a2 != v3 );\n v2 = a1 - a2;\n v5 = v4 + 1;\n v6 = 0;\n if ( a1 != a2 )\n {\n while ( v2 != 1 )\n {\nLABEL_9:\n v7 = v2 - 1;\n v2 -= 2;\n v8 = v5 * v7 * sub_1600(v7, 0LL);\n v5 *= v7;\n v6 += v8;\n if ( !v2 )\n goto LABEL_10;\n }\n return v6;\n }\n }\nLABEL_10:\n v6 += v5;\n return v6;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1600(int a1, int a2) {\n int v2;\n int v3;\n int v4;\n int v5;\n unsigned int v6;\n unsigned int v7;\n int v8;\n if (a2 | a1) {\n v2 = a1;\n if (a1 == 1) {\n if (!a2) return 0;\n } else if (!a2) {\n v6 = 0;\n v5 = 1;\n goto LABEL_9;\n }\n if (a1 == a2) {\n v6 = 0;\n v5 = 1;\n } else {\n v3 = a1;\n v4 = 0;\n do\n v4 += sub_1230((unsigned int)--v3, (unsigned int)(a2 - 1));\n while (a2 != v3);\n v2 = a1 - a2;\n v5 = v4 + 1;\n v6 = 0;\n if (a1 != a2) {\n while (v2 != 1) {\n LABEL_9:\n v7 = v2 - 1;\n v2 -= 2;\n v8 = v5 * v7 * sub_1600(v7, 0LL);\n v5 *= v7;\n v6 += v8;\n if (!v2) goto LABEL_10;\n }\n return v6;\n }\n }\n LABEL_10:\n v6 += v5;\n return v6;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n int v2;\n int v3;\n int v4;\n int v5;\n unsigned int v6;\n unsigned int v7;\n int v8;\n if (a2 | a1) {\n v2 = a1;\n if (a1 == 1) {\n if (!a2) return 0;\n } else if (!a2) {\n v6 = 0;\n v5 = 1;\n goto LABEL_9;\n }\n if (a1 == a2) {\n v6 = 0;\n v5 = 1;\n } else {\n v3 = a1;\n v4 = 0;\n do\n v4 += binomial_coeffi((unsigned int)--v3, (unsigned int)(a2 - 1));\n while (a2 != v3);\n v2 = a1 - a2;\n v5 = v4 + 1;\n v6 = 0;\n if (a1 != a2) {\n while (v2 != 1) {\n LABEL_9:\n v7 = v2 - 1;\n v2 -= 2;\n v8 = v5 * v7 * func0(v7, 0LL);\n v5 *= v7;\n v6 += v8;\n if (!v2) goto LABEL_10;\n }\n return v6;\n }\n }\n LABEL_10:\n v6 += v5;\n return v6;\n }\n return 1LL;\n}" + }, + { + "index": 927, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n// Node structure\n\ntypedef struct Node {\n\n int data;\n\n struct Node* left;\n\n struct Node* right;\n\n} Node;\n\n\n\n// Function to create a new node\n\nNode* newNode(int data) {\n\n Node* node = (Node*) malloc(sizeof(Node));\n\n node->data = data;\n\n node->left = NULL;\n\n node->right = NULL;\n\n return node;\n\n}\n\n\n\n// Function to find the maximum height of the binary tree\n\n", + "func": "int func0(Node* node) {\n if (node == NULL) {\n return 0;\n } else {\n int left_height = func0(node->left);\n int right_height = func0(node->right);\n if (left_height > right_height) {\n return left_height + 1;\n } else {\n return right_height + 1;\n }\n }\n}", + "test": "int main() {\n\n // Constructing trees as per the given Python code\n\n Node* root = newNode(1);\n\n root->left = newNode(2);\n\n root->right = newNode(3);\n\n root->left->left = newNode(4);\n\n root->left->right = newNode(5);\n\n \n\n Node* root1 = newNode(1);\n\n root1->left = newNode(2);\n\n root1->right = newNode(3);\n\n root1->left->left = newNode(4);\n\n root1->right->left = newNode(5);\n\n root1->right->right = newNode(6);\n\n root1->right->right->right = newNode(7);\n\n root1->right->right->right->right = newNode(8);\n\n \n\n Node* root2 = newNode(1);\n\n root2->left = newNode(2);\n\n root2->right = newNode(3);\n\n root2->left->left = newNode(4);\n\n root2->left->right = newNode(5);\n\n root2->left->left->left = newNode(6);\n\n root2->left->left->right = newNode(7);\n\n \n\n // Testing the max_height function\n\n assert(func0(root) == 3);\n\n assert(func0(root1) == 5);\n\n assert(func0(root2) == 4);\n\n \n\n printf(\"All tests passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\ncmpq $0x0,-0x18(%rbp)\njne 11eb \nmov $0x0,%eax\njmp 1227 \nmov -0x18(%rbp),%rax\nmov 0x8(%rax),%rax\nmov %rax,%rdi\ncallq 11cd \nmov %eax,-0x8(%rbp)\nmov -0x18(%rbp),%rax\nmov 0x10(%rax),%rax\nmov %rax,%rdi\ncallq 11cd \nmov %eax,-0x4(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x4(%rbp),%eax\njle 1221 \nmov -0x8(%rbp),%eax\nadd $0x1,%eax\njmp 1227 \nmov -0x4(%rbp),%eax\nadd $0x1,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\ncmp [rbp+var_18], 0\njnz short loc_11EB\nmov eax, 0\njmp short locret_1227\nloc_11EB:\nmov rax, [rbp+var_18]\nmov rax, [rax+8]\nmov rdi, rax\ncall func0\nmov [rbp+var_8], eax\nmov rax, [rbp+var_18]\nmov rax, [rax+10h]\nmov rdi, rax\ncall func0\nmov [rbp+var_4], eax\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njle short loc_1221\nmov eax, [rbp+var_8]\nadd eax, 1\njmp short locret_1227\nloc_1221:\nmov eax, [rbp+var_4]\nadd eax, 1\nlocret_1227:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1)\n{\n int v2; // [rsp+18h] [rbp-8h]\n int v3; // [rsp+1Ch] [rbp-4h]\n\n if ( !a1 )\n return 0LL;\n v2 = func0(*(_QWORD *)(a1 + 8));\n v3 = func0(*(_QWORD *)(a1 + 16));\n if ( v2 <= v3 )\n return (unsigned int)(v3 + 1);\n else\n return (unsigned int)(v2 + 1);\n}", + "ida_strip_asm": "sub_11CD:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\ncmp [rbp+var_18], 0\njnz short loc_11EB\nmov eax, 0\njmp short locret_1227\nloc_11EB:\nmov rax, [rbp+var_18]\nmov rax, [rax+8]\nmov rdi, rax\ncall sub_11CD\nmov [rbp+var_8], eax\nmov rax, [rbp+var_18]\nmov rax, [rax+10h]\nmov rdi, rax\ncall sub_11CD\nmov [rbp+var_4], eax\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_4]\njle short loc_1221\nmov eax, [rbp+var_8]\nadd eax, 1\njmp short locret_1227\nloc_1221:\nmov eax, [rbp+var_4]\nadd eax, 1\nlocret_1227:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11CD(__int64 a1)\n{\n int v2; // [rsp+18h] [rbp-8h]\n int v3; // [rsp+1Ch] [rbp-4h]\n\n if ( !a1 )\n return 0LL;\n v2 = sub_11CD(*(_QWORD *)(a1 + 8));\n v3 = sub_11CD(*(_QWORD *)(a1 + 16));\n if ( v2 <= v3 )\n return (unsigned int)(v3 + 1);\n else\n return (unsigned int)(v2 + 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11CD(long long a1) {\n int v2;\n int v3;\n if (!a1) return 0LL;\n v2 = sub_11CD(*(uint64_t *)(a1 + 8));\n v3 = sub_11CD(*(uint64_t *)(a1 + 16));\n if (v2 <= v3)\n return (unsigned int)(v3 + 1);\n else\n return (unsigned int)(v2 + 1);\n}", + "ida_pseudo_norm": "long long func0(long long a1) {\n int v2;\n int v3;\n if (!a1) return 0LL;\n v2 = func0(*(uint64_t *)(a1 + 8));\n v3 = func0(*(uint64_t *)(a1 + 16));\n if (v2 <= v3)\n return (unsigned int)(v3 + 1);\n else\n return (unsigned int)(v2 + 1);\n}" + }, + { + "index": 927, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n// Node structure\n\ntypedef struct Node {\n\n int data;\n\n struct Node* left;\n\n struct Node* right;\n\n} Node;\n\n\n\n// Function to create a new node\n\nNode* newNode(int data) {\n\n Node* node = (Node*) malloc(sizeof(Node));\n\n node->data = data;\n\n node->left = NULL;\n\n node->right = NULL;\n\n return node;\n\n}\n\n\n\n// Function to find the maximum height of the binary tree\n\n", + "func": "int func0(Node* node) {\n if (node == NULL) {\n return 0;\n } else {\n int left_height = func0(node->left);\n int right_height = func0(node->right);\n if (left_height > right_height) {\n return left_height + 1;\n } else {\n return right_height + 1;\n }\n }\n}", + "test": "int main() {\n\n // Constructing trees as per the given Python code\n\n Node* root = newNode(1);\n\n root->left = newNode(2);\n\n root->right = newNode(3);\n\n root->left->left = newNode(4);\n\n root->left->right = newNode(5);\n\n \n\n Node* root1 = newNode(1);\n\n root1->left = newNode(2);\n\n root1->right = newNode(3);\n\n root1->left->left = newNode(4);\n\n root1->right->left = newNode(5);\n\n root1->right->right = newNode(6);\n\n root1->right->right->right = newNode(7);\n\n root1->right->right->right->right = newNode(8);\n\n \n\n Node* root2 = newNode(1);\n\n root2->left = newNode(2);\n\n root2->right = newNode(3);\n\n root2->left->left = newNode(4);\n\n root2->left->right = newNode(5);\n\n root2->left->left->left = newNode(6);\n\n root2->left->left->right = newNode(7);\n\n \n\n // Testing the max_height function\n\n assert(func0(root) == 3);\n\n assert(func0(root1) == 5);\n\n assert(func0(root2) == 4);\n\n \n\n printf(\"All tests passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov $0x0,%eax\ntest %rdi,%rdi\nje 11ed \npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbx\nmov 0x8(%rdi),%rdi\ncallq 11ae \nmov %eax,%ebp\nmov 0x10(%rbx),%rdi\ncallq 11ae \nmov %eax,%edx\nlea 0x1(%rbp),%ecx\nlea 0x1(%rax),%eax\ncmp %edx,%ebp\ncmovg %ecx,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nretq\n", + "ida_asm": "func0:\nendbr64\nmov eax, 0\ntest rdi, rdi\njz short locret_11ED\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov rdi, [rdi+8]\ncall func0\nmov ebp, eax\nmov rdi, [rbx+10h]\ncall func0\nlea ecx, [rbp+1]\nlea edx, [rax+1]\ncmp ebp, eax\nmov eax, ecx\ncmovle eax, edx\nadd rsp, 8\npop rbx\npop rbp\nretn\nlocret_11ED:\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1)\n{\n __int64 result; // rax\n int v2; // ebp\n int v3; // eax\n unsigned int v4; // edx\n bool v5; // cc\n\n result = 0LL;\n if ( a1 )\n {\n v2 = func0(*(_QWORD *)(a1 + 8));\n v3 = func0(*(_QWORD *)(a1 + 16));\n v4 = v3 + 1;\n v5 = v2 <= v3;\n result = (unsigned int)(v2 + 1);\n if ( v5 )\n return v4;\n }\n return result;\n}", + "ida_strip_asm": "sub_11AE:\nendbr64\nmov eax, 0\ntest rdi, rdi\njz short locret_11ED\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov rdi, [rdi+8]\ncall sub_11AE\nmov ebp, eax\nmov rdi, [rbx+10h]\ncall sub_11AE\nlea ecx, [rbp+1]\nlea edx, [rax+1]\ncmp ebp, eax\nmov eax, ecx\ncmovle eax, edx\nadd rsp, 8\npop rbx\npop rbp\nretn\nlocret_11ED:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11AE(__int64 a1)\n{\n __int64 result; // rax\n int v2; // ebp\n int v3; // eax\n unsigned int v4; // edx\n bool v5; // cc\n\n result = 0LL;\n if ( a1 )\n {\n v2 = sub_11AE(*(_QWORD *)(a1 + 8));\n v3 = sub_11AE(*(_QWORD *)(a1 + 16));\n v4 = v3 + 1;\n v5 = v2 <= v3;\n result = (unsigned int)(v2 + 1);\n if ( v5 )\n return v4;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11AE(long long a1) {\n long long result;\n int v2;\n int v3;\n unsigned int v4;\n bool v5;\n result = 0LL;\n if (a1) {\n v2 = sub_11AE(*(uint64_t *)(a1 + 8));\n v3 = sub_11AE(*(uint64_t *)(a1 + 16));\n v4 = v3 + 1;\n v5 = v2 <= v3;\n result = (unsigned int)(v2 + 1);\n if (v5) return v4;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1) {\n long long result;\n int v2;\n int v3;\n unsigned int v4;\n bool v5;\n result = 0LL;\n if (a1) {\n v2 = func0(*(uint64_t *)(a1 + 8));\n v3 = func0(*(uint64_t *)(a1 + 16));\n v4 = v3 + 1;\n v5 = v2 <= v3;\n result = (unsigned int)(v2 + 1);\n if (v5) return v4;\n }\n return result;\n}" + }, + { + "index": 927, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n// Node structure\n\ntypedef struct Node {\n\n int data;\n\n struct Node* left;\n\n struct Node* right;\n\n} Node;\n\n\n\n// Function to create a new node\n\nNode* newNode(int data) {\n\n Node* node = (Node*) malloc(sizeof(Node));\n\n node->data = data;\n\n node->left = NULL;\n\n node->right = NULL;\n\n return node;\n\n}\n\n\n\n// Function to find the maximum height of the binary tree\n\n", + "func": "int func0(Node* node) {\n if (node == NULL) {\n return 0;\n } else {\n int left_height = func0(node->left);\n int right_height = func0(node->right);\n if (left_height > right_height) {\n return left_height + 1;\n } else {\n return right_height + 1;\n }\n }\n}", + "test": "int main() {\n\n // Constructing trees as per the given Python code\n\n Node* root = newNode(1);\n\n root->left = newNode(2);\n\n root->right = newNode(3);\n\n root->left->left = newNode(4);\n\n root->left->right = newNode(5);\n\n \n\n Node* root1 = newNode(1);\n\n root1->left = newNode(2);\n\n root1->right = newNode(3);\n\n root1->left->left = newNode(4);\n\n root1->right->left = newNode(5);\n\n root1->right->right = newNode(6);\n\n root1->right->right->right = newNode(7);\n\n root1->right->right->right->right = newNode(8);\n\n \n\n Node* root2 = newNode(1);\n\n root2->left = newNode(2);\n\n root2->right = newNode(3);\n\n root2->left->left = newNode(4);\n\n root2->left->right = newNode(5);\n\n root2->left->left->left = newNode(6);\n\n root2->left->left->right = newNode(7);\n\n \n\n // Testing the max_height function\n\n assert(func0(root) == 3);\n\n assert(func0(root1) == 5);\n\n assert(func0(root2) == 4);\n\n \n\n printf(\"All tests passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %rdi,%rdi\nje 14e0 \njmp 14f0 \nnopl 0x0(%rax,%rax,1)\nxor %eax,%eax\nretq\ndata16 nopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0_part_0:\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 8\nmov rbp, [rdi+8]\ntest rbp, rbp\njz loc_16E8\nmov r12, [rbp+8]\ntest r12, r12\njz loc_1590\nmov r13, [r12+8]\ntest r13, r13\njz loc_1C10\nmov r14, [r13+8]\ntest r14, r14\njz loc_1C50\nmov rdi, [r14+8]\ntest rdi, rdi\njz loc_1AC0\ncall func0_part_0\nmov rdi, [r14+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_143B\nloc_1436:\ncall func0_part_0\nloc_143B:\nmov r13, [r13+10h]\nlea r14d, [rax+1]\ncmp eax, r15d\nlea edx, [r15+1]\ncmovl r14d, edx\nxor eax, eax\ntest r13, r13\njz short loc_1489\nloc_1455:\nmov rdi, [r13+8]\ntest rdi, rdi\njz loc_1DF0\ncall func0_part_0\nmov rdi, [r13+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_147A\nloc_1475:\ncall func0_part_0\nloc_147A:\nlea ecx, [rax+1]\ncmp eax, r15d\nlea edx, [r15+1]\nmov eax, ecx\ncmovl eax, edx\nloc_1489:\nmov r12, [r12+10h]\nlea r13d, [rax+1]\nlea edx, [r14+1]\ncmp eax, r14d\ncmovl r13d, edx\nxor eax, eax\ntest r12, r12\njz loc_1537\nloc_14A8:\nmov r14, [r12+8]\ntest r14, r14\njz loc_1D60\nmov rdi, [r14+8]\ntest rdi, rdi\njz loc_1DA0\ncall func0_part_0\nmov rdi, [r14+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_14DB\nloc_14D6:\ncall func0_part_0\nloc_14DB:\nmov r12, [r12+10h]\nlea edx, [r15+1]\ncmp eax, r15d\nlea r14d, [rax+1]\ncmovl r14d, edx\nxor edx, edx\ntest r12, r12\njz short loc_152A\nloc_14F6:\nmov rdi, [r12+8]\ntest rdi, rdi\njz loc_1DD0\ncall func0_part_0\nmov rdi, [r12+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_151D\nloc_1518:\ncall func0_part_0\nloc_151D:\nlea ecx, [rax+1]\nlea edx, [r15+1]\ncmp eax, r15d\ncmovge edx, ecx\nloc_152A:\nlea ecx, [rdx+1]\nlea eax, [r14+1]\ncmp edx, r14d\ncmovge eax, ecx\nloc_1537:\nlea edx, [r13+1]\nlea r12d, [rax+1]\ncmp eax, r13d\nmov r13, [rbp+10h]\ncmovl r12d, edx\nxor eax, eax\ntest r13, r13\njnz short loc_159D\nloc_1551:\nlea ebp, [rax+1]\ncmp eax, r12d\njge short loc_155E\nloc_1559:\nlea ebp, [r12+1]\nloc_155E:\nmov r12, [rbx+10h]\nxor eax, eax\ntest r12, r12\njnz loc_16FA\nloc_156D:\ncmp eax, ebp\njge loc_19B9\nloc_1575:\nlea eax, [rbp+1]\nloc_1578:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1590:\nmov r13, [rbp+10h]\ntest r13, r13\njz loc_1B50\nloc_159D:\nmov rbp, [r13+8]\ntest rbp, rbp\njz loc_1BA0\nmov r14, [rbp+8]\ntest r14, r14\njz loc_1D00\nmov rdi, [r14+8]\ntest rdi, rdi\njz loc_1B10\ncall func0_part_0\nmov rdi, [r14+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_15DC\nloc_15D7:\ncall func0_part_0\nloc_15DC:\nmov rbp, [rbp+10h]\nlea edx, [r15+1]\ncmp eax, r15d\nlea r14d, [rax+1]\ncmovl r14d, edx\nxor edx, edx\ntest rbp, rbp\njz short loc_1628\nloc_15F6:\nmov rdi, [rbp+8]\ntest rdi, rdi\njz loc_1ED0\ncall func0_part_0\nmov rdi, [rbp+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_161B\nloc_1616:\ncall func0_part_0\nloc_161B:\nlea ecx, [rax+1]\nlea edx, [r15+1]\ncmp eax, r15d\ncmovge edx, ecx\nloc_1628:\nlea eax, [rdx+1]\nlea ecx, [r14+1]\ncmp edx, r14d\nmov r13, [r13+10h]\ncmovge ecx, eax\nxor eax, eax\nmov ebp, ecx\ntest r13, r13\njz loc_16D1\nloc_1646:\nmov r14, [r13+8]\ntest r14, r14\njz loc_1BBF\nloc_1653:\nmov rdi, [r14+8]\ntest rdi, rdi\njz loc_1F10\ncall func0_part_0\nmov rdi, [r14+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_1678\nloc_1673:\ncall func0_part_0\nloc_1678:\nmov r13, [r13+10h]\nlea edx, [r15+1]\ncmp eax, r15d\nlea r14d, [rax+1]\ncmovl r14d, edx\nxor edx, edx\ntest r13, r13\njz short loc_16C4\nloc_1692:\nmov rdi, [r13+8]\ntest rdi, rdi\njz loc_1EF0\ncall func0_part_0\nmov rdi, [r13+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_16B7\nloc_16B2:\ncall func0_part_0\nloc_16B7:\nlea ecx, [rax+1]\nlea edx, [r15+1]\ncmp eax, r15d\ncmovge edx, ecx\nloc_16C4:\nlea ecx, [rdx+1]\nlea eax, [r14+1]\ncmp edx, r14d\ncmovge eax, ecx\nloc_16D1:\ncmp eax, ebp\njge loc_1B90\nloc_16D9:\nlea eax, [rbp+1]\njmp loc_1551\nloc_16E8:\nmov r12, [rdi+10h]\nmov eax, 1\ntest r12, r12\njz loc_1578\nloc_16FA:\nmov rbx, [r12+8]\ntest rbx, rbx\njz loc_19D0\nmov r13, [rbx+8]\ntest r13, r13\njz loc_1BE0\nmov r14, [r13+8]\ntest r14, r14\njz loc_1CA0\nmov rdi, [r14+8]\ntest rdi, rdi\njz loc_1A28\ncall func0_part_0\nmov rdi, [r14+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_1747\nloc_1742:\ncall func0_part_0\nloc_1747:\nmov r13, [r13+10h]\nlea r14d, [rax+1]\ncmp eax, r15d\nlea edx, [r15+1]\ncmovl r14d, edx\nxor eax, eax\ntest r13, r13\njz short loc_1795\nloc_1761:\nmov rdi, [r13+8]\ntest rdi, rdi\njz loc_1D80\ncall func0_part_0\nmov rdi, [r13+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_1786\nloc_1781:\ncall func0_part_0\nloc_1786:\nlea ecx, [rax+1]\ncmp eax, r15d\nlea edx, [r15+1]\nmov eax, ecx\ncmovl eax, edx\nloc_1795:\nmov rbx, [rbx+10h]\nlea edx, [r14+1]\nlea r13d, [rax+1]\ncmp eax, r14d\ncmovl r13d, edx\nxor edx, edx\ntest rbx, rbx\njz loc_1840\nloc_17B3:\nmov r14, [rbx+8]\ntest r14, r14\njz loc_1CE0\nmov rdi, [r14+8]\ntest rdi, rdi\njz loc_1E70\ncall func0_part_0\nmov rdi, [r14+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_17E5\nloc_17E0:\ncall func0_part_0\nloc_17E5:\nmov rbx, [rbx+10h]\nlea r14d, [rax+1]\ncmp eax, r15d\nlea edx, [r15+1]\ncmovl r14d, edx\nxor eax, eax\ntest rbx, rbx\njz short loc_1833\nloc_17FF:\nmov rdi, [rbx+8]\ntest rdi, rdi\njz loc_1E50\ncall func0_part_0\nmov rdi, [rbx+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_1824\nloc_181F:\ncall func0_part_0\nloc_1824:\nlea ecx, [rax+1]\ncmp eax, r15d\nlea edx, [r15+1]\nmov eax, ecx\ncmovl eax, edx\nloc_1833:\nlea ecx, [rax+1]\nlea edx, [r14+1]\ncmp eax, r14d\ncmovge edx, ecx\nloc_1840:\nlea ecx, [r13+1]\nlea eax, [rdx+1]\ncmp edx, r13d\nmov r13, [r12+10h]\ncmovge ecx, eax\nxor eax, eax\nmov ebx, ecx\ntest r13, r13\njz loc_19A6\nloc_185F:\nmov r12, [r13+8]\ntest r12, r12\njz loc_19F0\nloc_186C:\nmov r14, [r12+8]\ntest r14, r14\njz loc_1D30\nmov rdi, [r14+8]\ntest rdi, rdi\njz loc_1A80\ncall func0_part_0\nmov rdi, [r14+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_189F\nloc_189A:\ncall func0_part_0\nloc_189F:\nmov r12, [r12+10h]\nlea edx, [r15+1]\ncmp eax, r15d\nlea r14d, [rax+1]\ncmovl r14d, edx\nxor edx, edx\ntest r12, r12\njz short loc_18EE\nloc_18BA:\nmov rdi, [r12+8]\ntest rdi, rdi\njz loc_1E30\ncall func0_part_0\nmov rdi, [r12+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_18E1\nloc_18DC:\ncall func0_part_0\nloc_18E1:\nlea ecx, [rax+1]\nlea edx, [r15+1]\ncmp eax, r15d\ncmovge edx, ecx\nloc_18EE:\nlea eax, [rdx+1]\nlea ecx, [r14+1]\ncmp edx, r14d\nmov r13, [r13+10h]\ncmovge ecx, eax\nxor eax, eax\nmov r12d, ecx\ntest r13, r13\njz loc_1998\nloc_190D:\nmov r14, [r13+8]\ntest r14, r14\njz loc_1A0B\nloc_191A:\nmov rdi, [r14+8]\ntest rdi, rdi\njz loc_1EA0\ncall func0_part_0\nmov rdi, [r14+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_193F\nloc_193A:\ncall func0_part_0\nloc_193F:\nmov r13, [r13+10h]\nlea edx, [r15+1]\ncmp eax, r15d\nlea r14d, [rax+1]\ncmovl r14d, edx\nxor edx, edx\ntest r13, r13\njz short loc_198B\nloc_1959:\nmov rdi, [r13+8]\ntest rdi, rdi\njz loc_1E10\ncall func0_part_0\nmov rdi, [r13+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_197E\nloc_1979:\ncall func0_part_0\nloc_197E:\nlea ecx, [rax+1]\nlea edx, [r15+1]\ncmp eax, r15d\ncmovge edx, ecx\nloc_198B:\nlea ecx, [rdx+1]\nlea eax, [r14+1]\ncmp edx, r14d\ncmovge eax, ecx\nloc_1998:\ncmp eax, r12d\njge loc_1B80\nloc_19A1:\nlea eax, [r12+1]\nloc_19A6:\ncmp eax, ebx\njge loc_1B70\nloc_19AE:\nlea eax, [rbx+1]\ncmp eax, ebp\njl loc_1575\nloc_19B9:\nadd rsp, 8\nadd eax, 1\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_19D0:\nmov r13, [r12+10h]\nmov eax, 1\ntest r13, r13\njz loc_156D\nmov r12, [r13+8]\ntest r12, r12\njnz loc_186C\nloc_19F0:\nmov r13, [r13+10h]\nmov eax, 1\ntest r13, r13\njz short loc_19A6\nmov r14, [r13+8]\ntest r14, r14\njnz loc_191A\nloc_1A0B:\nmov r13, [r13+10h]\nmov eax, 1\ntest r13, r13\njnz loc_1959\njmp loc_1998\nloc_1A28:\nmov rdi, [r14+10h]\nxor r15d, r15d\ntest rdi, rdi\njnz loc_1742\nmov r13, [r13+10h]\nmov r14d, 1\ntest r13, r13\njnz loc_1761\nmov rbx, [rbx+10h]\nmov r13d, 2\ntest rbx, rbx\njnz loc_17B3\nmov r13, [r12+10h]\nmov ebx, 3\ntest r13, r13\njnz loc_185F\njmp loc_19AE\nloc_1A80:\nmov rdi, [r14+10h]\nxor r15d, r15d\ntest rdi, rdi\njnz loc_189A\nmov r12, [r12+10h]\nmov r14d, 1\ntest r12, r12\njnz loc_18BA\nmov r13, [r13+10h]\nmov r12d, 2\ntest r13, r13\njnz loc_190D\njmp loc_19A1\nloc_1AC0:\nmov rdi, [r14+10h]\nxor r15d, r15d\ntest rdi, rdi\njnz loc_1436\nmov r13, [r13+10h]\nmov r14d, 1\ntest r13, r13\njnz loc_1455\nmov r12, [r12+10h]\nmov r13d, 2\ntest r12, r12\njnz loc_14A8\nmov r13, [rbp+10h]\nmov r12d, 3\ntest r13, r13\njnz loc_159D\njmp loc_1559\nloc_1B10:\nmov rdi, [r14+10h]\nxor r15d, r15d\ntest rdi, rdi\njnz loc_15D7\nmov rbp, [rbp+10h]\nmov r14d, 1\ntest rbp, rbp\njnz loc_15F6\nmov r13, [r13+10h]\nmov ebp, 2\ntest r13, r13\njnz loc_1646\njmp loc_16D9\nloc_1B50:\nmov r12, [rdi+10h]\nmov eax, 2\nmov ebp, 1\ntest r12, r12\njnz loc_16FA\njmp loc_1578\nloc_1B70:\nadd eax, 1\njmp loc_156D\nloc_1B80:\nadd eax, 1\njmp loc_19A6\nloc_1B90:\nadd eax, 1\njmp loc_1551\nloc_1BA0:\nmov r13, [r13+10h]\nmov eax, 1\ntest r13, r13\njz loc_1551\nmov r14, [r13+8]\ntest r14, r14\njnz loc_1653\nloc_1BBF:\nmov r13, [r13+10h]\nmov eax, 1\ntest r13, r13\njnz loc_1692\njmp loc_16D1\nloc_1BE0:\nmov rbx, [rbx+10h]\ntest rbx, rbx\njnz loc_17B3\nmov r13, [r12+10h]\nmov eax, 2\ntest r13, r13\njz loc_156D\nmov ebx, 1\njmp loc_185F\nloc_1C10:\nmov r12, [r12+10h]\ntest r12, r12\njnz loc_14A8\nmov r13, [rbp+10h]\nmov r12d, 1\ntest r13, r13\njnz loc_159D\nmov r12, [rdi+10h]\nmov ebp, 2\ntest r12, r12\njnz loc_16FA\njmp loc_1575\nloc_1C50:\nmov r13, [r13+10h]\ntest r13, r13\njnz loc_1455\nmov r12, [r12+10h]\nmov r13d, 1\ntest r12, r12\njnz loc_14A8\nmov r13, [rbp+10h]\nmov r12d, 2\ntest r13, r13\njnz loc_159D\nmov r12, [rdi+10h]\nmov ebp, 3\ntest r12, r12\njnz loc_16FA\njmp loc_1575\nloc_1CA0:\nmov r13, [r13+10h]\ntest r13, r13\njnz loc_1761\nmov rbx, [rbx+10h]\nmov r13d, 1\ntest rbx, rbx\njnz loc_17B3\nmov r13, [r12+10h]\nmov ebx, 2\ntest r13, r13\njnz loc_185F\njmp loc_19AE\nloc_1CE0:\nmov rbx, [rbx+10h]\nmov edx, 1\ntest rbx, rbx\njnz loc_17FF\njmp loc_1840\nloc_1D00:\nmov rbp, [rbp+10h]\ntest rbp, rbp\njnz loc_15F6\nmov r13, [r13+10h]\nmov eax, 2\ntest r13, r13\njz loc_1551\nmov ebp, 1\njmp loc_1646\nloc_1D30:\nmov r12, [r12+10h]\ntest r12, r12\njnz loc_18BA\nmov r13, [r13+10h]\nmov eax, 2\ntest r13, r13\njz loc_19A6\nmov r12d, 1\njmp loc_190D\nloc_1D60:\nmov r12, [r12+10h]\nmov eax, 1\ntest r12, r12\njnz loc_14F6\njmp loc_1537\nloc_1D80:\nmov rdi, [r13+10h]\nmov eax, 1\nxor r15d, r15d\ntest rdi, rdi\njnz loc_1781\njmp loc_1795\nloc_1DA0:\nmov rdi, [r14+10h]\nxor r15d, r15d\ntest rdi, rdi\njnz loc_14D6\nmov r12, [r12+10h]\nmov eax, 2\ntest r12, r12\njz loc_1537\nmov r14d, 1\njmp loc_14F6\nloc_1DD0:\nmov rdi, [r12+10h]\nmov edx, 1\nxor r15d, r15d\ntest rdi, rdi\njnz loc_1518\njmp loc_152A\nloc_1DF0:\nmov rdi, [r13+10h]\nmov eax, 1\nxor r15d, r15d\ntest rdi, rdi\njnz loc_1475\njmp loc_1489\nloc_1E10:\nmov rdi, [r13+10h]\nmov edx, 1\nxor r15d, r15d\ntest rdi, rdi\njnz loc_1979\njmp loc_198B\nloc_1E30:\nmov rdi, [r12+10h]\nmov edx, 1\nxor r15d, r15d\ntest rdi, rdi\njnz loc_18DC\njmp loc_18EE\nloc_1E50:\nmov rdi, [rbx+10h]\nmov eax, 1\nxor r15d, r15d\ntest rdi, rdi\njnz loc_181F\njmp loc_1833\nloc_1E70:\nmov rdi, [r14+10h]\nxor r15d, r15d\ntest rdi, rdi\njnz loc_17E0\nmov rbx, [rbx+10h]\nmov edx, 2\ntest rbx, rbx\njz loc_1840\nmov r14d, 1\njmp loc_17FF\nloc_1EA0:\nmov rdi, [r14+10h]\nxor r15d, r15d\ntest rdi, rdi\njnz loc_193A\nmov r13, [r13+10h]\nmov eax, 2\ntest r13, r13\njz loc_1998\nmov r14d, 1\njmp loc_1959\nloc_1ED0:\nmov rdi, [rbp+10h]\nmov edx, 1\nxor r15d, r15d\ntest rdi, rdi\njnz loc_1616\njmp loc_1628\nloc_1EF0:\nmov rdi, [r13+10h]\nmov edx, 1\nxor r15d, r15d\ntest rdi, rdi\njnz loc_16B2\njmp loc_16C4\nloc_1F10:\nmov rdi, [r14+10h]\nxor r15d, r15d\ntest rdi, rdi\njnz loc_1673\nmov r13, [r13+10h]\nmov eax, 2\ntest r13, r13\njz loc_16D1\nmov r14d, 1\njmp loc_1692", + "ida_pseudo": "__int64 __fastcall func0_part_0(__int64 a1, __int64 a2, __int64 a3)\n{\n __int64 v4; // rbp\n __int64 v5; // r12\n __int64 v6; // r13\n __int64 v7; // r14\n int v8; // r15d\n int v9; // eax\n __int64 v10; // r13\n int v11; // eax\n int v12; // r15d\n int v13; // eax\n bool v14; // cc\n __int64 v15; // r12\n int v16; // eax\n __int64 v17; // r14\n int v18; // r15d\n int v19; // eax\n __int64 v20; // r12\n __int64 v21; // rdi\n int v22; // eax\n __int64 v23; // rdi\n int v24; // r15d\n int v25; // eax\n __int64 v26; // r13\n int v27; // eax\n __int64 v28; // r12\n int v29; // eax\n __int64 result; // rax\n __int64 v31; // rbp\n __int64 v32; // r14\n __int64 v33; // rdi\n int v34; // eax\n __int64 v35; // rdi\n int v36; // r15d\n int v37; // eax\n __int64 v38; // rbp\n __int64 v39; // rdi\n int v40; // eax\n __int64 v41; // rdi\n int v42; // r15d\n int v43; // eax\n int v44; // ecx\n __int64 v45; // r13\n int v46; // eax\n __int64 v47; // r14\n __int64 v48; // rdi\n int v49; // eax\n __int64 v50; // rdi\n int v51; // r15d\n int v52; // eax\n __int64 v53; // r13\n __int64 v54; // rdi\n int v55; // eax\n __int64 v56; // rdi\n int v57; // r15d\n int v58; // eax\n __int64 v59; // rbx\n __int64 v60; // r13\n __int64 v61; // r14\n __int64 v62; // rdi\n int v63; // eax\n __int64 v64; // rdi\n int v65; // r15d\n int v66; // eax\n __int64 v67; // r13\n int v68; // eax\n __int64 v69; // rdi\n int v70; // eax\n __int64 v71; // rdi\n int v72; // r15d\n int v73; // eax\n __int64 v74; // rbx\n __int64 v75; // r14\n __int64 v76; // rdi\n int v77; // eax\n __int64 v78; // rdi\n int v79; // r15d\n int v80; // eax\n __int64 v81; // rbx\n int v82; // eax\n __int64 v83; // rdi\n int v84; // eax\n __int64 v85; // rdi\n int v86; // r15d\n int v87; // eax\n int v88; // ecx\n __int64 v89; // r13\n int v90; // eax\n __int64 v91; // r12\n __int64 v92; // r14\n __int64 v93; // rdi\n int v94; // eax\n __int64 v95; // rdi\n int v96; // r15d\n int v97; // eax\n __int64 v98; // r12\n __int64 v99; // rdi\n int v100; // eax\n __int64 v101; // rdi\n int v102; // r15d\n int v103; // eax\n int v104; // ecx\n __int64 v105; // r13\n int v106; // eax\n __int64 v107; // r14\n __int64 v108; // rdi\n int v109; // eax\n __int64 v110; // rdi\n int v111; // r15d\n int v112; // eax\n __int64 v113; // r13\n __int64 v114; // rdi\n int v115; // eax\n __int64 v116; // rdi\n int v117; // r15d\n int v118; // eax\n\n v4 = *(_QWORD *)(a1 + 8);\n if ( v4 )\n {\n v5 = *(_QWORD *)(v4 + 8);\n if ( v5 )\n {\n v6 = *(_QWORD *)(v5 + 8);\n if ( !v6 )\n {\n v15 = *(_QWORD *)(v5 + 16);\n if ( !v15 )\n {\n v26 = *(_QWORD *)(v4 + 16);\n LODWORD(v5) = 1;\n if ( !v26 )\n {\n v28 = *(_QWORD *)(a1 + 16);\n LODWORD(v4) = 2;\n if ( !v28 )\n return (unsigned int)(v4 + 1);\n goto LABEL_76;\n }\n goto LABEL_43;\n }\n goto LABEL_19;\n }\n v7 = *(_QWORD *)(v6 + 8);\n if ( !v7 )\n {\n v10 = *(_QWORD *)(v6 + 16);\n if ( !v10 )\n {\n v15 = *(_QWORD *)(v5 + 16);\n LODWORD(v6) = 1;\n if ( !v15 )\n {\n v26 = *(_QWORD *)(v4 + 16);\n LODWORD(v5) = 2;\n if ( !v26 )\n {\n v28 = *(_QWORD *)(a1 + 16);\n LODWORD(v4) = 3;\n if ( !v28 )\n return (unsigned int)(v4 + 1);\n goto LABEL_76;\n }\n goto LABEL_43;\n }\n goto LABEL_19;\n }\n goto LABEL_11;\n }\n if ( *(_QWORD *)(v7 + 8) )\n {\n v8 = ((__int64 (*)(void))func0_part_0)();\n v9 = 0;\n if ( !*(_QWORD *)(v7 + 16) )\n goto LABEL_8;\n }\n else\n {\n v8 = 0;\n if ( !*(_QWORD *)(v7 + 16) )\n {\n v10 = *(_QWORD *)(v6 + 16);\n LODWORD(v7) = 1;\n if ( !v10 )\n {\n v15 = *(_QWORD *)(v5 + 16);\n LODWORD(v6) = 2;\n if ( !v15 )\n {\n v26 = *(_QWORD *)(v4 + 16);\n LODWORD(v5) = 3;\n if ( !v26 )\n {\nLABEL_37:\n LODWORD(v4) = v5 + 1;\nLABEL_38:\n v28 = *(_QWORD *)(a1 + 16);\n v29 = 0;\n if ( !v28 )\n goto LABEL_39;\nLABEL_76:\n v59 = *(_QWORD *)(v28 + 8);\n if ( !v59 )\n {\n v89 = *(_QWORD *)(v28 + 16);\n v29 = 1;\n if ( !v89 )\n goto LABEL_39;\n v91 = *(_QWORD *)(v89 + 8);\n if ( v91 )\n {\nLABEL_111:\n v92 = *(_QWORD *)(v91 + 8);\n if ( !v92 )\n {\n v98 = *(_QWORD *)(v91 + 16);\n if ( !v98 )\n {\n v105 = *(_QWORD *)(v89 + 16);\n v90 = 2;\n if ( !v105 )\n goto LABEL_142;\n LODWORD(v91) = 1;\n goto LABEL_126;\n }\n goto LABEL_118;\n }\n v93 = *(_QWORD *)(v92 + 8);\n if ( v93 )\n {\n v94 = func0_part_0(v93, a2, a3);\n v95 = *(_QWORD *)(v92 + 16);\n v96 = v94;\n v97 = 0;\n if ( !v95 )\n goto LABEL_115;\n }\n else\n {\n v95 = *(_QWORD *)(v92 + 16);\n v96 = 0;\n if ( !v95 )\n {\n v98 = *(_QWORD *)(v91 + 16);\n LODWORD(v92) = 1;\n if ( !v98 )\n {\n v105 = *(_QWORD *)(v89 + 16);\n LODWORD(v91) = 2;\n if ( !v105 )\n {\nLABEL_141:\n v90 = v91 + 1;\nLABEL_142:\n if ( v90 < (int)v59 )\n goto LABEL_143;\n v29 = v90 + 1;\nLABEL_39:\n if ( v29 < (int)v4 )\n return (unsigned int)(v4 + 1);\n return (unsigned int)(v29 + 1);\n }\n goto LABEL_126;\n }\n goto LABEL_118;\n }\n }\n v97 = func0_part_0(v95, a2, a3);\nLABEL_115:\n v98 = *(_QWORD *)(v91 + 16);\n LODWORD(v92) = v97 + 1;\n if ( v97 < v96 )\n LODWORD(v92) = v96 + 1;\n a3 = 0LL;\n if ( !v98 )\n {\nLABEL_123:\n v104 = v92 + 1;\n v105 = *(_QWORD *)(v89 + 16);\n if ( (int)a3 >= (int)v92 )\n v104 = a3 + 1;\n v106 = 0;\n LODWORD(v91) = v104;\n if ( !v105 )\n {\nLABEL_140:\n if ( v106 >= (int)v91 )\n {\n v90 = v106 + 1;\n goto LABEL_142;\n }\n goto LABEL_141;\n }\nLABEL_126:\n v107 = *(_QWORD *)(v105 + 8);\n if ( v107 )\n goto LABEL_127;\n goto LABEL_149;\n }\nLABEL_118:\n v99 = *(_QWORD *)(v98 + 8);\n if ( v99 )\n {\n v100 = func0_part_0(v99, a2, a3);\n v101 = *(_QWORD *)(v98 + 16);\n v102 = v100;\n v103 = 0;\n if ( !v101 )\n goto LABEL_121;\n }\n else\n {\n v101 = *(_QWORD *)(v98 + 16);\n a3 = 1LL;\n v102 = 0;\n if ( !v101 )\n goto LABEL_123;\n }\n v103 = func0_part_0(v101, a2, a3);\nLABEL_121:\n a3 = (unsigned int)(v102 + 1);\n if ( v103 >= v102 )\n a3 = (unsigned int)(v103 + 1);\n goto LABEL_123;\n }\nLABEL_147:\n v105 = *(_QWORD *)(v89 + 16);\n v90 = 1;\n if ( !v105 )\n goto LABEL_142;\n v107 = *(_QWORD *)(v105 + 8);\n if ( v107 )\n {\nLABEL_127:\n v108 = *(_QWORD *)(v107 + 8);\n if ( v108 )\n {\n v109 = func0_part_0(v108, a2, a3);\n v110 = *(_QWORD *)(v107 + 16);\n v111 = v109;\n v112 = 0;\n if ( !v110 )\n goto LABEL_130;\n }\n else\n {\n v110 = *(_QWORD *)(v107 + 16);\n v111 = 0;\n if ( !v110 )\n {\n v113 = *(_QWORD *)(v105 + 16);\n v106 = 2;\n if ( !v113 )\n goto LABEL_140;\n LODWORD(v107) = 1;\n goto LABEL_133;\n }\n }\n v112 = func0_part_0(v110, a2, a3);\nLABEL_130:\n v113 = *(_QWORD *)(v105 + 16);\n LODWORD(v107) = v112 + 1;\n if ( v112 < v111 )\n LODWORD(v107) = v111 + 1;\n a3 = 0LL;\n if ( !v113 )\n goto LABEL_138;\nLABEL_133:\n v114 = *(_QWORD *)(v113 + 8);\n if ( v114 )\n {\n v115 = func0_part_0(v114, a2, a3);\n v116 = *(_QWORD *)(v113 + 16);\n v117 = v115;\n v118 = 0;\n if ( !v116 )\n goto LABEL_136;\n }\n else\n {\n v116 = *(_QWORD *)(v113 + 16);\n a3 = 1LL;\n v117 = 0;\n if ( !v116 )\n {\nLABEL_138:\n v106 = v107 + 1;\n if ( (int)a3 >= (int)v107 )\n v106 = a3 + 1;\n goto LABEL_140;\n }\n }\n v118 = func0_part_0(v116, a2, a3);\nLABEL_136:\n LODWORD(a3) = v117 + 1;\n if ( v118 >= v117 )\n LODWORD(a3) = v118 + 1;\n goto LABEL_138;\n }\nLABEL_149:\n v113 = *(_QWORD *)(v105 + 16);\n v106 = 1;\n if ( !v113 )\n goto LABEL_140;\n goto LABEL_133;\n }\n v60 = *(_QWORD *)(v59 + 8);\n if ( !v60 )\n {\n v74 = *(_QWORD *)(v59 + 16);\n if ( !v74 )\n {\n v89 = *(_QWORD *)(v28 + 16);\n v29 = 2;\n if ( !v89 )\n goto LABEL_39;\n LODWORD(v59) = 1;\n goto LABEL_110;\n }\n goto LABEL_93;\n }\n v61 = *(_QWORD *)(v60 + 8);\n if ( v61 )\n {\n v62 = *(_QWORD *)(v61 + 8);\n if ( v62 )\n {\n v63 = func0_part_0(v62, a2, a3);\n v64 = *(_QWORD *)(v61 + 16);\n v65 = v63;\n v66 = 0;\n if ( !v64 )\n goto LABEL_82;\n goto LABEL_81;\n }\n v64 = *(_QWORD *)(v61 + 16);\n v65 = 0;\n if ( v64 )\n {\nLABEL_81:\n v66 = func0_part_0(v64, a2, a3);\nLABEL_82:\n v67 = *(_QWORD *)(v60 + 16);\n LODWORD(v61) = v66 + 1;\n a3 = (unsigned int)(v65 + 1);\n if ( v66 < v65 )\n LODWORD(v61) = v65 + 1;\n v68 = 0;\n if ( !v67 )\n {\nLABEL_90:\n v74 = *(_QWORD *)(v59 + 16);\n LODWORD(v60) = v68 + 1;\n if ( v68 < (int)v61 )\n LODWORD(v60) = v61 + 1;\n a3 = 0LL;\n if ( !v74 )\n {\nLABEL_107:\n v88 = v60 + 1;\n v14 = (int)a3 < (int)v60;\n v89 = *(_QWORD *)(v28 + 16);\n if ( !v14 )\n v88 = a3 + 1;\n v90 = 0;\n LODWORD(v59) = v88;\n if ( !v89 )\n goto LABEL_142;\nLABEL_110:\n v91 = *(_QWORD *)(v89 + 8);\n if ( v91 )\n goto LABEL_111;\n goto LABEL_147;\n }\nLABEL_93:\n v75 = *(_QWORD *)(v74 + 8);\n if ( !v75 )\n {\n v81 = *(_QWORD *)(v74 + 16);\n a3 = 1LL;\n if ( !v81 )\n goto LABEL_107;\n goto LABEL_100;\n }\n v76 = *(_QWORD *)(v75 + 8);\n if ( v76 )\n {\n v77 = func0_part_0(v76, a2, a3);\n v78 = *(_QWORD *)(v75 + 16);\n v79 = v77;\n v80 = 0;\n if ( !v78 )\n goto LABEL_97;\n }\n else\n {\n v78 = *(_QWORD *)(v75 + 16);\n v79 = 0;\n if ( !v78 )\n {\n v81 = *(_QWORD *)(v74 + 16);\n a3 = 2LL;\n if ( !v81 )\n goto LABEL_107;\n LODWORD(v75) = 1;\n goto LABEL_100;\n }\n }\n v80 = func0_part_0(v78, a2, a3);\nLABEL_97:\n v81 = *(_QWORD *)(v74 + 16);\n LODWORD(v75) = v80 + 1;\n a3 = (unsigned int)(v79 + 1);\n if ( v80 < v79 )\n LODWORD(v75) = v79 + 1;\n v82 = 0;\n if ( !v81 )\n goto LABEL_105;\nLABEL_100:\n v83 = *(_QWORD *)(v81 + 8);\n if ( v83 )\n {\n v84 = func0_part_0(v83, a2, a3);\n v85 = *(_QWORD *)(v81 + 16);\n v86 = v84;\n v87 = 0;\n if ( !v85 )\n goto LABEL_103;\n }\n else\n {\n v85 = *(_QWORD *)(v81 + 16);\n v82 = 1;\n v86 = 0;\n if ( !v85 )\n {\nLABEL_105:\n a3 = (unsigned int)(v75 + 1);\n if ( v82 >= (int)v75 )\n a3 = (unsigned int)(v82 + 1);\n goto LABEL_107;\n }\n }\n v87 = func0_part_0(v85, a2, a3);\nLABEL_103:\n v14 = v87 < v86;\n v82 = v87 + 1;\n if ( v14 )\n v82 = v86 + 1;\n goto LABEL_105;\n }\nLABEL_85:\n v69 = *(_QWORD *)(v67 + 8);\n if ( v69 )\n {\n v70 = func0_part_0(v69, a2, a3);\n v71 = *(_QWORD *)(v67 + 16);\n v72 = v70;\n v73 = 0;\n if ( !v71 )\n goto LABEL_88;\n }\n else\n {\n v71 = *(_QWORD *)(v67 + 16);\n v68 = 1;\n v72 = 0;\n if ( !v71 )\n goto LABEL_90;\n }\n v73 = func0_part_0(v71, a2, a3);\nLABEL_88:\n v14 = v73 < v72;\n v68 = v73 + 1;\n if ( v14 )\n v68 = v72 + 1;\n goto LABEL_90;\n }\n v67 = *(_QWORD *)(v60 + 16);\n LODWORD(v61) = 1;\n if ( v67 )\n goto LABEL_85;\n v74 = *(_QWORD *)(v59 + 16);\n LODWORD(v60) = 2;\n if ( v74 )\n goto LABEL_93;\n v89 = *(_QWORD *)(v28 + 16);\n LODWORD(v59) = 3;\n if ( v89 )\n goto LABEL_110;\n }\n else\n {\n v67 = *(_QWORD *)(v60 + 16);\n if ( v67 )\n goto LABEL_85;\n v74 = *(_QWORD *)(v59 + 16);\n LODWORD(v60) = 1;\n if ( v74 )\n goto LABEL_93;\n v89 = *(_QWORD *)(v28 + 16);\n LODWORD(v59) = 2;\n if ( v89 )\n goto LABEL_110;\n }\nLABEL_143:\n v29 = v59 + 1;\n if ( (int)v59 + 1 < (int)v4 )\n return (unsigned int)(v4 + 1);\n return (unsigned int)(v29 + 1);\n }\n goto LABEL_43;\n }\n goto LABEL_19;\n }\n goto LABEL_11;\n }\n }\n v9 = ((__int64 (*)(void))func0_part_0)();\nLABEL_8:\n v10 = *(_QWORD *)(v6 + 16);\n LODWORD(v7) = v9 + 1;\n if ( v9 < v8 )\n LODWORD(v7) = v8 + 1;\n v11 = 0;\n if ( !v10 )\n {\nLABEL_16:\n v15 = *(_QWORD *)(v5 + 16);\n LODWORD(v6) = v11 + 1;\n a3 = (unsigned int)(v7 + 1);\n if ( v11 < (int)v7 )\n LODWORD(v6) = v7 + 1;\n v16 = 0;\n if ( !v15 )\n {\nLABEL_33:\n a3 = (unsigned int)(v6 + 1);\n LODWORD(v5) = v16 + 1;\n v14 = v16 < (int)v6;\n v26 = *(_QWORD *)(v4 + 16);\n if ( v14 )\n LODWORD(v5) = a3;\n v27 = 0;\n if ( !v26 )\n {\nLABEL_36:\n LODWORD(v4) = v27 + 1;\n if ( v27 >= (int)v5 )\n goto LABEL_38;\n goto LABEL_37;\n }\nLABEL_43:\n v31 = *(_QWORD *)(v26 + 8);\n if ( !v31 )\n {\n v45 = *(_QWORD *)(v26 + 16);\n v27 = 1;\n if ( !v45 )\n goto LABEL_36;\n v47 = *(_QWORD *)(v45 + 8);\n if ( v47 )\n {\nLABEL_60:\n v48 = *(_QWORD *)(v47 + 8);\n if ( v48 )\n {\n v49 = func0_part_0(v48, a2, a3);\n v50 = *(_QWORD *)(v47 + 16);\n v51 = v49;\n v52 = 0;\n if ( !v50 )\n goto LABEL_63;\n }\n else\n {\n v50 = *(_QWORD *)(v47 + 16);\n v51 = 0;\n if ( !v50 )\n {\n v53 = *(_QWORD *)(v45 + 16);\n v46 = 2;\n if ( !v53 )\n goto LABEL_73;\n LODWORD(v47) = 1;\n goto LABEL_66;\n }\n }\n v52 = func0_part_0(v50, a2, a3);\nLABEL_63:\n v53 = *(_QWORD *)(v45 + 16);\n LODWORD(v47) = v52 + 1;\n if ( v52 < v51 )\n LODWORD(v47) = v51 + 1;\n a3 = 0LL;\n if ( !v53 )\n goto LABEL_71;\nLABEL_66:\n v54 = *(_QWORD *)(v53 + 8);\n if ( v54 )\n {\n v55 = func0_part_0(v54, a2, a3);\n v56 = *(_QWORD *)(v53 + 16);\n v57 = v55;\n v58 = 0;\n if ( !v56 )\n goto LABEL_69;\n }\n else\n {\n v56 = *(_QWORD *)(v53 + 16);\n a3 = 1LL;\n v57 = 0;\n if ( !v56 )\n {\nLABEL_71:\n v46 = v47 + 1;\n if ( (int)a3 >= (int)v47 )\n v46 = a3 + 1;\n goto LABEL_73;\n }\n }\n v58 = func0_part_0(v56, a2, a3);\nLABEL_69:\n a3 = (unsigned int)(v57 + 1);\n if ( v58 >= v57 )\n a3 = (unsigned int)(v58 + 1);\n goto LABEL_71;\n }\nLABEL_176:\n v53 = *(_QWORD *)(v45 + 16);\n v46 = 1;\n if ( !v53 )\n goto LABEL_73;\n goto LABEL_66;\n }\n v32 = *(_QWORD *)(v31 + 8);\n if ( !v32 )\n {\n v38 = *(_QWORD *)(v31 + 16);\n if ( !v38 )\n {\n v45 = *(_QWORD *)(v26 + 16);\n v27 = 2;\n if ( !v45 )\n goto LABEL_36;\n LODWORD(v31) = 1;\n goto LABEL_59;\n }\n goto LABEL_51;\n }\n v33 = *(_QWORD *)(v32 + 8);\n if ( v33 )\n {\n v34 = func0_part_0(v33, a2, a3);\n v35 = *(_QWORD *)(v32 + 16);\n v36 = v34;\n v37 = 0;\n if ( !v35 )\n goto LABEL_48;\n }\n else\n {\n v35 = *(_QWORD *)(v32 + 16);\n v36 = 0;\n if ( !v35 )\n {\n v38 = *(_QWORD *)(v31 + 16);\n LODWORD(v32) = 1;\n if ( !v38 )\n {\n v45 = *(_QWORD *)(v26 + 16);\n LODWORD(v31) = 2;\n if ( !v45 )\n goto LABEL_74;\n goto LABEL_59;\n }\n goto LABEL_51;\n }\n }\n v37 = func0_part_0(v35, a2, a3);\nLABEL_48:\n v38 = *(_QWORD *)(v31 + 16);\n LODWORD(v32) = v37 + 1;\n if ( v37 < v36 )\n LODWORD(v32) = v36 + 1;\n a3 = 0LL;\n if ( !v38 )\n {\nLABEL_56:\n v44 = v32 + 1;\n v45 = *(_QWORD *)(v26 + 16);\n if ( (int)a3 >= (int)v32 )\n v44 = a3 + 1;\n v46 = 0;\n LODWORD(v31) = v44;\n if ( !v45 )\n {\nLABEL_73:\n if ( v46 >= (int)v31 )\n {\n v27 = v46 + 1;\n goto LABEL_36;\n }\nLABEL_74:\n v27 = v31 + 1;\n goto LABEL_36;\n }\nLABEL_59:\n v47 = *(_QWORD *)(v45 + 8);\n if ( v47 )\n goto LABEL_60;\n goto LABEL_176;\n }\nLABEL_51:\n v39 = *(_QWORD *)(v38 + 8);\n if ( v39 )\n {\n v40 = func0_part_0(v39, a2, a3);\n v41 = *(_QWORD *)(v38 + 16);\n v42 = v40;\n v43 = 0;\n if ( !v41 )\n goto LABEL_54;\n }\n else\n {\n v41 = *(_QWORD *)(v38 + 16);\n a3 = 1LL;\n v42 = 0;\n if ( !v41 )\n goto LABEL_56;\n }\n v43 = func0_part_0(v41, a2, a3);\nLABEL_54:\n a3 = (unsigned int)(v42 + 1);\n if ( v43 >= v42 )\n a3 = (unsigned int)(v43 + 1);\n goto LABEL_56;\n }\nLABEL_19:\n v17 = *(_QWORD *)(v15 + 8);\n if ( !v17 )\n {\n v20 = *(_QWORD *)(v15 + 16);\n v16 = 1;\n if ( !v20 )\n goto LABEL_33;\n goto LABEL_26;\n }\n if ( *(_QWORD *)(v17 + 8) )\n {\n v18 = ((__int64 (*)(void))func0_part_0)();\n v19 = 0;\n if ( !*(_QWORD *)(v17 + 16) )\n goto LABEL_23;\n }\n else\n {\n v18 = 0;\n if ( !*(_QWORD *)(v17 + 16) )\n {\n v20 = *(_QWORD *)(v15 + 16);\n v16 = 2;\n if ( !v20 )\n goto LABEL_33;\n LODWORD(v17) = 1;\n goto LABEL_26;\n }\n }\n v19 = ((__int64 (*)(void))func0_part_0)();\nLABEL_23:\n v20 = *(_QWORD *)(v15 + 16);\n LODWORD(v17) = v19 + 1;\n if ( v19 < v18 )\n LODWORD(v17) = v18 + 1;\n a3 = 0LL;\n if ( !v20 )\n goto LABEL_31;\nLABEL_26:\n v21 = *(_QWORD *)(v20 + 8);\n if ( v21 )\n {\n v22 = func0_part_0(v21, a2, a3);\n v23 = *(_QWORD *)(v20 + 16);\n v24 = v22;\n v25 = 0;\n if ( !v23 )\n goto LABEL_29;\n }\n else\n {\n v23 = *(_QWORD *)(v20 + 16);\n a3 = 1LL;\n v24 = 0;\n if ( !v23 )\n {\nLABEL_31:\n v16 = v17 + 1;\n if ( (int)a3 >= (int)v17 )\n v16 = a3 + 1;\n goto LABEL_33;\n }\n }\n v25 = func0_part_0(v23, a2, a3);\nLABEL_29:\n LODWORD(a3) = v24 + 1;\n if ( v25 >= v24 )\n LODWORD(a3) = v25 + 1;\n goto LABEL_31;\n }\nLABEL_11:\n if ( *(_QWORD *)(v10 + 8) )\n {\n v12 = ((__int64 (*)(void))func0_part_0)();\n v13 = 0;\n if ( !*(_QWORD *)(v10 + 16) )\n goto LABEL_14;\n }\n else\n {\n v11 = 1;\n v12 = 0;\n if ( !*(_QWORD *)(v10 + 16) )\n goto LABEL_16;\n }\n v13 = ((__int64 (*)(void))func0_part_0)();\nLABEL_14:\n v14 = v13 < v12;\n v11 = v13 + 1;\n if ( v14 )\n v11 = v12 + 1;\n goto LABEL_16;\n }\n v26 = *(_QWORD *)(v4 + 16);\n if ( v26 )\n goto LABEL_43;\n v28 = *(_QWORD *)(a1 + 16);\n result = 2LL;\n LODWORD(v4) = 1;\n if ( v28 )\n goto LABEL_76;\n }\n else\n {\n v28 = *(_QWORD *)(a1 + 16);\n result = 1LL;\n if ( v28 )\n goto LABEL_76;\n }\n return result;\n}", + "ida_strip_asm": "sub_13D0:\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 8\nmov rbp, [rdi+8]\ntest rbp, rbp\njz loc_16E8\nmov r12, [rbp+8]\ntest r12, r12\njz loc_1590\nmov r13, [r12+8]\ntest r13, r13\njz loc_1C10\nmov r14, [r13+8]\ntest r14, r14\njz loc_1C50\nmov rdi, [r14+8]\ntest rdi, rdi\njz loc_1AC0\ncall sub_13D0\nmov rdi, [r14+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_143B\nloc_1436:\ncall sub_13D0\nloc_143B:\nmov r13, [r13+10h]\nlea r14d, [rax+1]\ncmp eax, r15d\nlea edx, [r15+1]\ncmovl r14d, edx\nxor eax, eax\ntest r13, r13\njz short loc_1489\nloc_1455:\nmov rdi, [r13+8]\ntest rdi, rdi\njz loc_1DF0\ncall sub_13D0\nmov rdi, [r13+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_147A\nloc_1475:\ncall sub_13D0\nloc_147A:\nlea ecx, [rax+1]\ncmp eax, r15d\nlea edx, [r15+1]\nmov eax, ecx\ncmovl eax, edx\nloc_1489:\nmov r12, [r12+10h]\nlea r13d, [rax+1]\nlea edx, [r14+1]\ncmp eax, r14d\ncmovl r13d, edx\nxor eax, eax\ntest r12, r12\njz loc_1537\nloc_14A8:\nmov r14, [r12+8]\ntest r14, r14\njz loc_1D60\nmov rdi, [r14+8]\ntest rdi, rdi\njz loc_1DA0\ncall sub_13D0\nmov rdi, [r14+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_14DB\nloc_14D6:\ncall sub_13D0\nloc_14DB:\nmov r12, [r12+10h]\nlea edx, [r15+1]\ncmp eax, r15d\nlea r14d, [rax+1]\ncmovl r14d, edx\nxor edx, edx\ntest r12, r12\njz short loc_152A\nloc_14F6:\nmov rdi, [r12+8]\ntest rdi, rdi\njz loc_1DD0\ncall sub_13D0\nmov rdi, [r12+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_151D\nloc_1518:\ncall sub_13D0\nloc_151D:\nlea ecx, [rax+1]\nlea edx, [r15+1]\ncmp eax, r15d\ncmovge edx, ecx\nloc_152A:\nlea ecx, [rdx+1]\nlea eax, [r14+1]\ncmp edx, r14d\ncmovge eax, ecx\nloc_1537:\nlea edx, [r13+1]\nlea r12d, [rax+1]\ncmp eax, r13d\nmov r13, [rbp+10h]\ncmovl r12d, edx\nxor eax, eax\ntest r13, r13\njnz short loc_159D\nloc_1551:\nlea ebp, [rax+1]\ncmp eax, r12d\njge short loc_155E\nloc_1559:\nlea ebp, [r12+1]\nloc_155E:\nmov r12, [rbx+10h]\nxor eax, eax\ntest r12, r12\njnz loc_16FA\nloc_156D:\ncmp eax, ebp\njge loc_19B9\nloc_1575:\nlea eax, [rbp+1]\nloc_1578:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1590:\nmov r13, [rbp+10h]\ntest r13, r13\njz loc_1B50\nloc_159D:\nmov rbp, [r13+8]\ntest rbp, rbp\njz loc_1BA0\nmov r14, [rbp+8]\ntest r14, r14\njz loc_1D00\nmov rdi, [r14+8]\ntest rdi, rdi\njz loc_1B10\ncall sub_13D0\nmov rdi, [r14+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_15DC\nloc_15D7:\ncall sub_13D0\nloc_15DC:\nmov rbp, [rbp+10h]\nlea edx, [r15+1]\ncmp eax, r15d\nlea r14d, [rax+1]\ncmovl r14d, edx\nxor edx, edx\ntest rbp, rbp\njz short loc_1628\nloc_15F6:\nmov rdi, [rbp+8]\ntest rdi, rdi\njz loc_1ED0\ncall sub_13D0\nmov rdi, [rbp+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_161B\nloc_1616:\ncall sub_13D0\nloc_161B:\nlea ecx, [rax+1]\nlea edx, [r15+1]\ncmp eax, r15d\ncmovge edx, ecx\nloc_1628:\nlea eax, [rdx+1]\nlea ecx, [r14+1]\ncmp edx, r14d\nmov r13, [r13+10h]\ncmovge ecx, eax\nxor eax, eax\nmov ebp, ecx\ntest r13, r13\njz loc_16D1\nloc_1646:\nmov r14, [r13+8]\ntest r14, r14\njz loc_1BBF\nloc_1653:\nmov rdi, [r14+8]\ntest rdi, rdi\njz loc_1F10\ncall sub_13D0\nmov rdi, [r14+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_1678\nloc_1673:\ncall sub_13D0\nloc_1678:\nmov r13, [r13+10h]\nlea edx, [r15+1]\ncmp eax, r15d\nlea r14d, [rax+1]\ncmovl r14d, edx\nxor edx, edx\ntest r13, r13\njz short loc_16C4\nloc_1692:\nmov rdi, [r13+8]\ntest rdi, rdi\njz loc_1EF0\ncall sub_13D0\nmov rdi, [r13+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_16B7\nloc_16B2:\ncall sub_13D0\nloc_16B7:\nlea ecx, [rax+1]\nlea edx, [r15+1]\ncmp eax, r15d\ncmovge edx, ecx\nloc_16C4:\nlea ecx, [rdx+1]\nlea eax, [r14+1]\ncmp edx, r14d\ncmovge eax, ecx\nloc_16D1:\ncmp eax, ebp\njge loc_1B90\nloc_16D9:\nlea eax, [rbp+1]\njmp loc_1551\nloc_16E8:\nmov r12, [rdi+10h]\nmov eax, 1\ntest r12, r12\njz loc_1578\nloc_16FA:\nmov rbx, [r12+8]\ntest rbx, rbx\njz loc_19D0\nmov r13, [rbx+8]\ntest r13, r13\njz loc_1BE0\nmov r14, [r13+8]\ntest r14, r14\njz loc_1CA0\nmov rdi, [r14+8]\ntest rdi, rdi\njz loc_1A28\ncall sub_13D0\nmov rdi, [r14+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_1747\nloc_1742:\ncall sub_13D0\nloc_1747:\nmov r13, [r13+10h]\nlea r14d, [rax+1]\ncmp eax, r15d\nlea edx, [r15+1]\ncmovl r14d, edx\nxor eax, eax\ntest r13, r13\njz short loc_1795\nloc_1761:\nmov rdi, [r13+8]\ntest rdi, rdi\njz loc_1D80\ncall sub_13D0\nmov rdi, [r13+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_1786\nloc_1781:\ncall sub_13D0\nloc_1786:\nlea ecx, [rax+1]\ncmp eax, r15d\nlea edx, [r15+1]\nmov eax, ecx\ncmovl eax, edx\nloc_1795:\nmov rbx, [rbx+10h]\nlea edx, [r14+1]\nlea r13d, [rax+1]\ncmp eax, r14d\ncmovl r13d, edx\nxor edx, edx\ntest rbx, rbx\njz loc_1840\nloc_17B3:\nmov r14, [rbx+8]\ntest r14, r14\njz loc_1CE0\nmov rdi, [r14+8]\ntest rdi, rdi\njz loc_1E70\ncall sub_13D0\nmov rdi, [r14+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_17E5\nloc_17E0:\ncall sub_13D0\nloc_17E5:\nmov rbx, [rbx+10h]\nlea r14d, [rax+1]\ncmp eax, r15d\nlea edx, [r15+1]\ncmovl r14d, edx\nxor eax, eax\ntest rbx, rbx\njz short loc_1833\nloc_17FF:\nmov rdi, [rbx+8]\ntest rdi, rdi\njz loc_1E50\ncall sub_13D0\nmov rdi, [rbx+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_1824\nloc_181F:\ncall sub_13D0\nloc_1824:\nlea ecx, [rax+1]\ncmp eax, r15d\nlea edx, [r15+1]\nmov eax, ecx\ncmovl eax, edx\nloc_1833:\nlea ecx, [rax+1]\nlea edx, [r14+1]\ncmp eax, r14d\ncmovge edx, ecx\nloc_1840:\nlea ecx, [r13+1]\nlea eax, [rdx+1]\ncmp edx, r13d\nmov r13, [r12+10h]\ncmovge ecx, eax\nxor eax, eax\nmov ebx, ecx\ntest r13, r13\njz loc_19A6\nloc_185F:\nmov r12, [r13+8]\ntest r12, r12\njz loc_19F0\nloc_186C:\nmov r14, [r12+8]\ntest r14, r14\njz loc_1D30\nmov rdi, [r14+8]\ntest rdi, rdi\njz loc_1A80\ncall sub_13D0\nmov rdi, [r14+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_189F\nloc_189A:\ncall sub_13D0\nloc_189F:\nmov r12, [r12+10h]\nlea edx, [r15+1]\ncmp eax, r15d\nlea r14d, [rax+1]\ncmovl r14d, edx\nxor edx, edx\ntest r12, r12\njz short loc_18EE\nloc_18BA:\nmov rdi, [r12+8]\ntest rdi, rdi\njz loc_1E30\ncall sub_13D0\nmov rdi, [r12+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_18E1\nloc_18DC:\ncall sub_13D0\nloc_18E1:\nlea ecx, [rax+1]\nlea edx, [r15+1]\ncmp eax, r15d\ncmovge edx, ecx\nloc_18EE:\nlea eax, [rdx+1]\nlea ecx, [r14+1]\ncmp edx, r14d\nmov r13, [r13+10h]\ncmovge ecx, eax\nxor eax, eax\nmov r12d, ecx\ntest r13, r13\njz loc_1998\nloc_190D:\nmov r14, [r13+8]\ntest r14, r14\njz loc_1A0B\nloc_191A:\nmov rdi, [r14+8]\ntest rdi, rdi\njz loc_1EA0\ncall sub_13D0\nmov rdi, [r14+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_193F\nloc_193A:\ncall sub_13D0\nloc_193F:\nmov r13, [r13+10h]\nlea edx, [r15+1]\ncmp eax, r15d\nlea r14d, [rax+1]\ncmovl r14d, edx\nxor edx, edx\ntest r13, r13\njz short loc_198B\nloc_1959:\nmov rdi, [r13+8]\ntest rdi, rdi\njz loc_1E10\ncall sub_13D0\nmov rdi, [r13+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_197E\nloc_1979:\ncall sub_13D0\nloc_197E:\nlea ecx, [rax+1]\nlea edx, [r15+1]\ncmp eax, r15d\ncmovge edx, ecx\nloc_198B:\nlea ecx, [rdx+1]\nlea eax, [r14+1]\ncmp edx, r14d\ncmovge eax, ecx\nloc_1998:\ncmp eax, r12d\njge loc_1B80\nloc_19A1:\nlea eax, [r12+1]\nloc_19A6:\ncmp eax, ebx\njge loc_1B70\nloc_19AE:\nlea eax, [rbx+1]\ncmp eax, ebp\njl loc_1575\nloc_19B9:\nadd rsp, 8\nadd eax, 1\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_19D0:\nmov r13, [r12+10h]\nmov eax, 1\ntest r13, r13\njz loc_156D\nmov r12, [r13+8]\ntest r12, r12\njnz loc_186C\nloc_19F0:\nmov r13, [r13+10h]\nmov eax, 1\ntest r13, r13\njz short loc_19A6\nmov r14, [r13+8]\ntest r14, r14\njnz loc_191A\nloc_1A0B:\nmov r13, [r13+10h]\nmov eax, 1\ntest r13, r13\njnz loc_1959\njmp loc_1998\nloc_1A28:\nmov rdi, [r14+10h]\nxor r15d, r15d\ntest rdi, rdi\njnz loc_1742\nmov r13, [r13+10h]\nmov r14d, 1\ntest r13, r13\njnz loc_1761\nmov rbx, [rbx+10h]\nmov r13d, 2\ntest rbx, rbx\njnz loc_17B3\nmov r13, [r12+10h]\nmov ebx, 3\ntest r13, r13\njnz loc_185F\njmp loc_19AE\nloc_1A80:\nmov rdi, [r14+10h]\nxor r15d, r15d\ntest rdi, rdi\njnz loc_189A\nmov r12, [r12+10h]\nmov r14d, 1\ntest r12, r12\njnz loc_18BA\nmov r13, [r13+10h]\nmov r12d, 2\ntest r13, r13\njnz loc_190D\njmp loc_19A1\nloc_1AC0:\nmov rdi, [r14+10h]\nxor r15d, r15d\ntest rdi, rdi\njnz loc_1436\nmov r13, [r13+10h]\nmov r14d, 1\ntest r13, r13\njnz loc_1455\nmov r12, [r12+10h]\nmov r13d, 2\ntest r12, r12\njnz loc_14A8\nmov r13, [rbp+10h]\nmov r12d, 3\ntest r13, r13\njnz loc_159D\njmp loc_1559\nloc_1B10:\nmov rdi, [r14+10h]\nxor r15d, r15d\ntest rdi, rdi\njnz loc_15D7\nmov rbp, [rbp+10h]\nmov r14d, 1\ntest rbp, rbp\njnz loc_15F6\nmov r13, [r13+10h]\nmov ebp, 2\ntest r13, r13\njnz loc_1646\njmp loc_16D9\nloc_1B50:\nmov r12, [rdi+10h]\nmov eax, 2\nmov ebp, 1\ntest r12, r12\njnz loc_16FA\njmp loc_1578\nloc_1B70:\nadd eax, 1\njmp loc_156D\nloc_1B80:\nadd eax, 1\njmp loc_19A6\nloc_1B90:\nadd eax, 1\njmp loc_1551\nloc_1BA0:\nmov r13, [r13+10h]\nmov eax, 1\ntest r13, r13\njz loc_1551\nmov r14, [r13+8]\ntest r14, r14\njnz loc_1653\nloc_1BBF:\nmov r13, [r13+10h]\nmov eax, 1\ntest r13, r13\njnz loc_1692\njmp loc_16D1\nloc_1BE0:\nmov rbx, [rbx+10h]\ntest rbx, rbx\njnz loc_17B3\nmov r13, [r12+10h]\nmov eax, 2\ntest r13, r13\njz loc_156D\nmov ebx, 1\njmp loc_185F\nloc_1C10:\nmov r12, [r12+10h]\ntest r12, r12\njnz loc_14A8\nmov r13, [rbp+10h]\nmov r12d, 1\ntest r13, r13\njnz loc_159D\nmov r12, [rdi+10h]\nmov ebp, 2\ntest r12, r12\njnz loc_16FA\njmp loc_1575\nloc_1C50:\nmov r13, [r13+10h]\ntest r13, r13\njnz loc_1455\nmov r12, [r12+10h]\nmov r13d, 1\ntest r12, r12\njnz loc_14A8\nmov r13, [rbp+10h]\nmov r12d, 2\ntest r13, r13\njnz loc_159D\nmov r12, [rdi+10h]\nmov ebp, 3\ntest r12, r12\njnz loc_16FA\njmp loc_1575\nloc_1CA0:\nmov r13, [r13+10h]\ntest r13, r13\njnz loc_1761\nmov rbx, [rbx+10h]\nmov r13d, 1\ntest rbx, rbx\njnz loc_17B3\nmov r13, [r12+10h]\nmov ebx, 2\ntest r13, r13\njnz loc_185F\njmp loc_19AE\nloc_1CE0:\nmov rbx, [rbx+10h]\nmov edx, 1\ntest rbx, rbx\njnz loc_17FF\njmp loc_1840\nloc_1D00:\nmov rbp, [rbp+10h]\ntest rbp, rbp\njnz loc_15F6\nmov r13, [r13+10h]\nmov eax, 2\ntest r13, r13\njz loc_1551\nmov ebp, 1\njmp loc_1646\nloc_1D30:\nmov r12, [r12+10h]\ntest r12, r12\njnz loc_18BA\nmov r13, [r13+10h]\nmov eax, 2\ntest r13, r13\njz loc_19A6\nmov r12d, 1\njmp loc_190D\nloc_1D60:\nmov r12, [r12+10h]\nmov eax, 1\ntest r12, r12\njnz loc_14F6\njmp loc_1537\nloc_1D80:\nmov rdi, [r13+10h]\nmov eax, 1\nxor r15d, r15d\ntest rdi, rdi\njnz loc_1781\njmp loc_1795\nloc_1DA0:\nmov rdi, [r14+10h]\nxor r15d, r15d\ntest rdi, rdi\njnz loc_14D6\nmov r12, [r12+10h]\nmov eax, 2\ntest r12, r12\njz loc_1537\nmov r14d, 1\njmp loc_14F6\nloc_1DD0:\nmov rdi, [r12+10h]\nmov edx, 1\nxor r15d, r15d\ntest rdi, rdi\njnz loc_1518\njmp loc_152A\nloc_1DF0:\nmov rdi, [r13+10h]\nmov eax, 1\nxor r15d, r15d\ntest rdi, rdi\njnz loc_1475\njmp loc_1489\nloc_1E10:\nmov rdi, [r13+10h]\nmov edx, 1\nxor r15d, r15d\ntest rdi, rdi\njnz loc_1979\njmp loc_198B\nloc_1E30:\nmov rdi, [r12+10h]\nmov edx, 1\nxor r15d, r15d\ntest rdi, rdi\njnz loc_18DC\njmp loc_18EE\nloc_1E50:\nmov rdi, [rbx+10h]\nmov eax, 1\nxor r15d, r15d\ntest rdi, rdi\njnz loc_181F\njmp loc_1833\nloc_1E70:\nmov rdi, [r14+10h]\nxor r15d, r15d\ntest rdi, rdi\njnz loc_17E0\nmov rbx, [rbx+10h]\nmov edx, 2\ntest rbx, rbx\njz loc_1840\nmov r14d, 1\njmp loc_17FF\nloc_1EA0:\nmov rdi, [r14+10h]\nxor r15d, r15d\ntest rdi, rdi\njnz loc_193A\nmov r13, [r13+10h]\nmov eax, 2\ntest r13, r13\njz loc_1998\nmov r14d, 1\njmp loc_1959\nloc_1ED0:\nmov rdi, [rbp+10h]\nmov edx, 1\nxor r15d, r15d\ntest rdi, rdi\njnz loc_1616\njmp loc_1628\nloc_1EF0:\nmov rdi, [r13+10h]\nmov edx, 1\nxor r15d, r15d\ntest rdi, rdi\njnz loc_16B2\njmp loc_16C4\nloc_1F10:\nmov rdi, [r14+10h]\nxor r15d, r15d\ntest rdi, rdi\njnz loc_1673\nmov r13, [r13+10h]\nmov eax, 2\ntest r13, r13\njz loc_16D1\nmov r14d, 1\njmp loc_1692", + "ida_strip_pseudo": "__int64 __fastcall sub_13D0(__int64 a1, __int64 a2, __int64 a3)\n{\n __int64 v4; // rbp\n __int64 v5; // r12\n __int64 v6; // r13\n __int64 v7; // r14\n int v8; // r15d\n int v9; // eax\n __int64 v10; // r13\n int v11; // eax\n int v12; // r15d\n int v13; // eax\n bool v14; // cc\n __int64 v15; // r12\n int v16; // eax\n __int64 v17; // r14\n int v18; // r15d\n int v19; // eax\n __int64 v20; // r12\n __int64 v21; // rdi\n int v22; // eax\n __int64 v23; // rdi\n int v24; // r15d\n int v25; // eax\n __int64 v26; // r13\n int v27; // eax\n __int64 v28; // r12\n int v29; // eax\n __int64 result; // rax\n __int64 v31; // rbp\n __int64 v32; // r14\n __int64 v33; // rdi\n int v34; // eax\n __int64 v35; // rdi\n int v36; // r15d\n int v37; // eax\n __int64 v38; // rbp\n __int64 v39; // rdi\n int v40; // eax\n __int64 v41; // rdi\n int v42; // r15d\n int v43; // eax\n int v44; // ecx\n __int64 v45; // r13\n int v46; // eax\n __int64 v47; // r14\n __int64 v48; // rdi\n int v49; // eax\n __int64 v50; // rdi\n int v51; // r15d\n int v52; // eax\n __int64 v53; // r13\n __int64 v54; // rdi\n int v55; // eax\n __int64 v56; // rdi\n int v57; // r15d\n int v58; // eax\n __int64 v59; // rbx\n __int64 v60; // r13\n __int64 v61; // r14\n __int64 v62; // rdi\n int v63; // eax\n __int64 v64; // rdi\n int v65; // r15d\n int v66; // eax\n __int64 v67; // r13\n int v68; // eax\n __int64 v69; // rdi\n int v70; // eax\n __int64 v71; // rdi\n int v72; // r15d\n int v73; // eax\n __int64 v74; // rbx\n __int64 v75; // r14\n __int64 v76; // rdi\n int v77; // eax\n __int64 v78; // rdi\n int v79; // r15d\n int v80; // eax\n __int64 v81; // rbx\n int v82; // eax\n __int64 v83; // rdi\n int v84; // eax\n __int64 v85; // rdi\n int v86; // r15d\n int v87; // eax\n int v88; // ecx\n __int64 v89; // r13\n int v90; // eax\n __int64 v91; // r12\n __int64 v92; // r14\n __int64 v93; // rdi\n int v94; // eax\n __int64 v95; // rdi\n int v96; // r15d\n int v97; // eax\n __int64 v98; // r12\n __int64 v99; // rdi\n int v100; // eax\n __int64 v101; // rdi\n int v102; // r15d\n int v103; // eax\n int v104; // ecx\n __int64 v105; // r13\n int v106; // eax\n __int64 v107; // r14\n __int64 v108; // rdi\n int v109; // eax\n __int64 v110; // rdi\n int v111; // r15d\n int v112; // eax\n __int64 v113; // r13\n __int64 v114; // rdi\n int v115; // eax\n __int64 v116; // rdi\n int v117; // r15d\n int v118; // eax\n\n v4 = *(_QWORD *)(a1 + 8);\n if ( v4 )\n {\n v5 = *(_QWORD *)(v4 + 8);\n if ( v5 )\n {\n v6 = *(_QWORD *)(v5 + 8);\n if ( !v6 )\n {\n v15 = *(_QWORD *)(v5 + 16);\n if ( !v15 )\n {\n v26 = *(_QWORD *)(v4 + 16);\n LODWORD(v5) = 1;\n if ( !v26 )\n {\n v28 = *(_QWORD *)(a1 + 16);\n LODWORD(v4) = 2;\n if ( !v28 )\n return (unsigned int)(v4 + 1);\n goto LABEL_76;\n }\n goto LABEL_43;\n }\n goto LABEL_19;\n }\n v7 = *(_QWORD *)(v6 + 8);\n if ( !v7 )\n {\n v10 = *(_QWORD *)(v6 + 16);\n if ( !v10 )\n {\n v15 = *(_QWORD *)(v5 + 16);\n LODWORD(v6) = 1;\n if ( !v15 )\n {\n v26 = *(_QWORD *)(v4 + 16);\n LODWORD(v5) = 2;\n if ( !v26 )\n {\n v28 = *(_QWORD *)(a1 + 16);\n LODWORD(v4) = 3;\n if ( !v28 )\n return (unsigned int)(v4 + 1);\n goto LABEL_76;\n }\n goto LABEL_43;\n }\n goto LABEL_19;\n }\n goto LABEL_11;\n }\n if ( *(_QWORD *)(v7 + 8) )\n {\n v8 = ((__int64 (*)(void))sub_13D0)();\n v9 = 0;\n if ( !*(_QWORD *)(v7 + 16) )\n goto LABEL_8;\n }\n else\n {\n v8 = 0;\n if ( !*(_QWORD *)(v7 + 16) )\n {\n v10 = *(_QWORD *)(v6 + 16);\n LODWORD(v7) = 1;\n if ( !v10 )\n {\n v15 = *(_QWORD *)(v5 + 16);\n LODWORD(v6) = 2;\n if ( !v15 )\n {\n v26 = *(_QWORD *)(v4 + 16);\n LODWORD(v5) = 3;\n if ( !v26 )\n {\nLABEL_37:\n LODWORD(v4) = v5 + 1;\nLABEL_38:\n v28 = *(_QWORD *)(a1 + 16);\n v29 = 0;\n if ( !v28 )\n goto LABEL_39;\nLABEL_76:\n v59 = *(_QWORD *)(v28 + 8);\n if ( !v59 )\n {\n v89 = *(_QWORD *)(v28 + 16);\n v29 = 1;\n if ( !v89 )\n goto LABEL_39;\n v91 = *(_QWORD *)(v89 + 8);\n if ( v91 )\n {\nLABEL_111:\n v92 = *(_QWORD *)(v91 + 8);\n if ( !v92 )\n {\n v98 = *(_QWORD *)(v91 + 16);\n if ( !v98 )\n {\n v105 = *(_QWORD *)(v89 + 16);\n v90 = 2;\n if ( !v105 )\n goto LABEL_142;\n LODWORD(v91) = 1;\n goto LABEL_126;\n }\n goto LABEL_118;\n }\n v93 = *(_QWORD *)(v92 + 8);\n if ( v93 )\n {\n v94 = sub_13D0(v93, a2, a3);\n v95 = *(_QWORD *)(v92 + 16);\n v96 = v94;\n v97 = 0;\n if ( !v95 )\n goto LABEL_115;\n }\n else\n {\n v95 = *(_QWORD *)(v92 + 16);\n v96 = 0;\n if ( !v95 )\n {\n v98 = *(_QWORD *)(v91 + 16);\n LODWORD(v92) = 1;\n if ( !v98 )\n {\n v105 = *(_QWORD *)(v89 + 16);\n LODWORD(v91) = 2;\n if ( !v105 )\n {\nLABEL_141:\n v90 = v91 + 1;\nLABEL_142:\n if ( v90 < (int)v59 )\n goto LABEL_143;\n v29 = v90 + 1;\nLABEL_39:\n if ( v29 < (int)v4 )\n return (unsigned int)(v4 + 1);\n return (unsigned int)(v29 + 1);\n }\n goto LABEL_126;\n }\n goto LABEL_118;\n }\n }\n v97 = sub_13D0(v95, a2, a3);\nLABEL_115:\n v98 = *(_QWORD *)(v91 + 16);\n LODWORD(v92) = v97 + 1;\n if ( v97 < v96 )\n LODWORD(v92) = v96 + 1;\n a3 = 0LL;\n if ( !v98 )\n {\nLABEL_123:\n v104 = v92 + 1;\n v105 = *(_QWORD *)(v89 + 16);\n if ( (int)a3 >= (int)v92 )\n v104 = a3 + 1;\n v106 = 0;\n LODWORD(v91) = v104;\n if ( !v105 )\n {\nLABEL_140:\n if ( v106 >= (int)v91 )\n {\n v90 = v106 + 1;\n goto LABEL_142;\n }\n goto LABEL_141;\n }\nLABEL_126:\n v107 = *(_QWORD *)(v105 + 8);\n if ( v107 )\n goto LABEL_127;\n goto LABEL_149;\n }\nLABEL_118:\n v99 = *(_QWORD *)(v98 + 8);\n if ( v99 )\n {\n v100 = sub_13D0(v99, a2, a3);\n v101 = *(_QWORD *)(v98 + 16);\n v102 = v100;\n v103 = 0;\n if ( !v101 )\n goto LABEL_121;\n }\n else\n {\n v101 = *(_QWORD *)(v98 + 16);\n a3 = 1LL;\n v102 = 0;\n if ( !v101 )\n goto LABEL_123;\n }\n v103 = sub_13D0(v101, a2, a3);\nLABEL_121:\n a3 = (unsigned int)(v102 + 1);\n if ( v103 >= v102 )\n a3 = (unsigned int)(v103 + 1);\n goto LABEL_123;\n }\nLABEL_147:\n v105 = *(_QWORD *)(v89 + 16);\n v90 = 1;\n if ( !v105 )\n goto LABEL_142;\n v107 = *(_QWORD *)(v105 + 8);\n if ( v107 )\n {\nLABEL_127:\n v108 = *(_QWORD *)(v107 + 8);\n if ( v108 )\n {\n v109 = sub_13D0(v108, a2, a3);\n v110 = *(_QWORD *)(v107 + 16);\n v111 = v109;\n v112 = 0;\n if ( !v110 )\n goto LABEL_130;\n }\n else\n {\n v110 = *(_QWORD *)(v107 + 16);\n v111 = 0;\n if ( !v110 )\n {\n v113 = *(_QWORD *)(v105 + 16);\n v106 = 2;\n if ( !v113 )\n goto LABEL_140;\n LODWORD(v107) = 1;\n goto LABEL_133;\n }\n }\n v112 = sub_13D0(v110, a2, a3);\nLABEL_130:\n v113 = *(_QWORD *)(v105 + 16);\n LODWORD(v107) = v112 + 1;\n if ( v112 < v111 )\n LODWORD(v107) = v111 + 1;\n a3 = 0LL;\n if ( !v113 )\n goto LABEL_138;\nLABEL_133:\n v114 = *(_QWORD *)(v113 + 8);\n if ( v114 )\n {\n v115 = sub_13D0(v114, a2, a3);\n v116 = *(_QWORD *)(v113 + 16);\n v117 = v115;\n v118 = 0;\n if ( !v116 )\n goto LABEL_136;\n }\n else\n {\n v116 = *(_QWORD *)(v113 + 16);\n a3 = 1LL;\n v117 = 0;\n if ( !v116 )\n {\nLABEL_138:\n v106 = v107 + 1;\n if ( (int)a3 >= (int)v107 )\n v106 = a3 + 1;\n goto LABEL_140;\n }\n }\n v118 = sub_13D0(v116, a2, a3);\nLABEL_136:\n LODWORD(a3) = v117 + 1;\n if ( v118 >= v117 )\n LODWORD(a3) = v118 + 1;\n goto LABEL_138;\n }\nLABEL_149:\n v113 = *(_QWORD *)(v105 + 16);\n v106 = 1;\n if ( !v113 )\n goto LABEL_140;\n goto LABEL_133;\n }\n v60 = *(_QWORD *)(v59 + 8);\n if ( !v60 )\n {\n v74 = *(_QWORD *)(v59 + 16);\n if ( !v74 )\n {\n v89 = *(_QWORD *)(v28 + 16);\n v29 = 2;\n if ( !v89 )\n goto LABEL_39;\n LODWORD(v59) = 1;\n goto LABEL_110;\n }\n goto LABEL_93;\n }\n v61 = *(_QWORD *)(v60 + 8);\n if ( v61 )\n {\n v62 = *(_QWORD *)(v61 + 8);\n if ( v62 )\n {\n v63 = sub_13D0(v62, a2, a3);\n v64 = *(_QWORD *)(v61 + 16);\n v65 = v63;\n v66 = 0;\n if ( !v64 )\n goto LABEL_82;\n goto LABEL_81;\n }\n v64 = *(_QWORD *)(v61 + 16);\n v65 = 0;\n if ( v64 )\n {\nLABEL_81:\n v66 = sub_13D0(v64, a2, a3);\nLABEL_82:\n v67 = *(_QWORD *)(v60 + 16);\n LODWORD(v61) = v66 + 1;\n a3 = (unsigned int)(v65 + 1);\n if ( v66 < v65 )\n LODWORD(v61) = v65 + 1;\n v68 = 0;\n if ( !v67 )\n {\nLABEL_90:\n v74 = *(_QWORD *)(v59 + 16);\n LODWORD(v60) = v68 + 1;\n if ( v68 < (int)v61 )\n LODWORD(v60) = v61 + 1;\n a3 = 0LL;\n if ( !v74 )\n {\nLABEL_107:\n v88 = v60 + 1;\n v14 = (int)a3 < (int)v60;\n v89 = *(_QWORD *)(v28 + 16);\n if ( !v14 )\n v88 = a3 + 1;\n v90 = 0;\n LODWORD(v59) = v88;\n if ( !v89 )\n goto LABEL_142;\nLABEL_110:\n v91 = *(_QWORD *)(v89 + 8);\n if ( v91 )\n goto LABEL_111;\n goto LABEL_147;\n }\nLABEL_93:\n v75 = *(_QWORD *)(v74 + 8);\n if ( !v75 )\n {\n v81 = *(_QWORD *)(v74 + 16);\n a3 = 1LL;\n if ( !v81 )\n goto LABEL_107;\n goto LABEL_100;\n }\n v76 = *(_QWORD *)(v75 + 8);\n if ( v76 )\n {\n v77 = sub_13D0(v76, a2, a3);\n v78 = *(_QWORD *)(v75 + 16);\n v79 = v77;\n v80 = 0;\n if ( !v78 )\n goto LABEL_97;\n }\n else\n {\n v78 = *(_QWORD *)(v75 + 16);\n v79 = 0;\n if ( !v78 )\n {\n v81 = *(_QWORD *)(v74 + 16);\n a3 = 2LL;\n if ( !v81 )\n goto LABEL_107;\n LODWORD(v75) = 1;\n goto LABEL_100;\n }\n }\n v80 = sub_13D0(v78, a2, a3);\nLABEL_97:\n v81 = *(_QWORD *)(v74 + 16);\n LODWORD(v75) = v80 + 1;\n a3 = (unsigned int)(v79 + 1);\n if ( v80 < v79 )\n LODWORD(v75) = v79 + 1;\n v82 = 0;\n if ( !v81 )\n goto LABEL_105;\nLABEL_100:\n v83 = *(_QWORD *)(v81 + 8);\n if ( v83 )\n {\n v84 = sub_13D0(v83, a2, a3);\n v85 = *(_QWORD *)(v81 + 16);\n v86 = v84;\n v87 = 0;\n if ( !v85 )\n goto LABEL_103;\n }\n else\n {\n v85 = *(_QWORD *)(v81 + 16);\n v82 = 1;\n v86 = 0;\n if ( !v85 )\n {\nLABEL_105:\n a3 = (unsigned int)(v75 + 1);\n if ( v82 >= (int)v75 )\n a3 = (unsigned int)(v82 + 1);\n goto LABEL_107;\n }\n }\n v87 = sub_13D0(v85, a2, a3);\nLABEL_103:\n v14 = v87 < v86;\n v82 = v87 + 1;\n if ( v14 )\n v82 = v86 + 1;\n goto LABEL_105;\n }\nLABEL_85:\n v69 = *(_QWORD *)(v67 + 8);\n if ( v69 )\n {\n v70 = sub_13D0(v69, a2, a3);\n v71 = *(_QWORD *)(v67 + 16);\n v72 = v70;\n v73 = 0;\n if ( !v71 )\n goto LABEL_88;\n }\n else\n {\n v71 = *(_QWORD *)(v67 + 16);\n v68 = 1;\n v72 = 0;\n if ( !v71 )\n goto LABEL_90;\n }\n v73 = sub_13D0(v71, a2, a3);\nLABEL_88:\n v14 = v73 < v72;\n v68 = v73 + 1;\n if ( v14 )\n v68 = v72 + 1;\n goto LABEL_90;\n }\n v67 = *(_QWORD *)(v60 + 16);\n LODWORD(v61) = 1;\n if ( v67 )\n goto LABEL_85;\n v74 = *(_QWORD *)(v59 + 16);\n LODWORD(v60) = 2;\n if ( v74 )\n goto LABEL_93;\n v89 = *(_QWORD *)(v28 + 16);\n LODWORD(v59) = 3;\n if ( v89 )\n goto LABEL_110;\n }\n else\n {\n v67 = *(_QWORD *)(v60 + 16);\n if ( v67 )\n goto LABEL_85;\n v74 = *(_QWORD *)(v59 + 16);\n LODWORD(v60) = 1;\n if ( v74 )\n goto LABEL_93;\n v89 = *(_QWORD *)(v28 + 16);\n LODWORD(v59) = 2;\n if ( v89 )\n goto LABEL_110;\n }\nLABEL_143:\n v29 = v59 + 1;\n if ( (int)v59 + 1 < (int)v4 )\n return (unsigned int)(v4 + 1);\n return (unsigned int)(v29 + 1);\n }\n goto LABEL_43;\n }\n goto LABEL_19;\n }\n goto LABEL_11;\n }\n }\n v9 = ((__int64 (*)(void))sub_13D0)();\nLABEL_8:\n v10 = *(_QWORD *)(v6 + 16);\n LODWORD(v7) = v9 + 1;\n if ( v9 < v8 )\n LODWORD(v7) = v8 + 1;\n v11 = 0;\n if ( !v10 )\n {\nLABEL_16:\n v15 = *(_QWORD *)(v5 + 16);\n LODWORD(v6) = v11 + 1;\n a3 = (unsigned int)(v7 + 1);\n if ( v11 < (int)v7 )\n LODWORD(v6) = v7 + 1;\n v16 = 0;\n if ( !v15 )\n {\nLABEL_33:\n a3 = (unsigned int)(v6 + 1);\n LODWORD(v5) = v16 + 1;\n v14 = v16 < (int)v6;\n v26 = *(_QWORD *)(v4 + 16);\n if ( v14 )\n LODWORD(v5) = a3;\n v27 = 0;\n if ( !v26 )\n {\nLABEL_36:\n LODWORD(v4) = v27 + 1;\n if ( v27 >= (int)v5 )\n goto LABEL_38;\n goto LABEL_37;\n }\nLABEL_43:\n v31 = *(_QWORD *)(v26 + 8);\n if ( !v31 )\n {\n v45 = *(_QWORD *)(v26 + 16);\n v27 = 1;\n if ( !v45 )\n goto LABEL_36;\n v47 = *(_QWORD *)(v45 + 8);\n if ( v47 )\n {\nLABEL_60:\n v48 = *(_QWORD *)(v47 + 8);\n if ( v48 )\n {\n v49 = sub_13D0(v48, a2, a3);\n v50 = *(_QWORD *)(v47 + 16);\n v51 = v49;\n v52 = 0;\n if ( !v50 )\n goto LABEL_63;\n }\n else\n {\n v50 = *(_QWORD *)(v47 + 16);\n v51 = 0;\n if ( !v50 )\n {\n v53 = *(_QWORD *)(v45 + 16);\n v46 = 2;\n if ( !v53 )\n goto LABEL_73;\n LODWORD(v47) = 1;\n goto LABEL_66;\n }\n }\n v52 = sub_13D0(v50, a2, a3);\nLABEL_63:\n v53 = *(_QWORD *)(v45 + 16);\n LODWORD(v47) = v52 + 1;\n if ( v52 < v51 )\n LODWORD(v47) = v51 + 1;\n a3 = 0LL;\n if ( !v53 )\n goto LABEL_71;\nLABEL_66:\n v54 = *(_QWORD *)(v53 + 8);\n if ( v54 )\n {\n v55 = sub_13D0(v54, a2, a3);\n v56 = *(_QWORD *)(v53 + 16);\n v57 = v55;\n v58 = 0;\n if ( !v56 )\n goto LABEL_69;\n }\n else\n {\n v56 = *(_QWORD *)(v53 + 16);\n a3 = 1LL;\n v57 = 0;\n if ( !v56 )\n {\nLABEL_71:\n v46 = v47 + 1;\n if ( (int)a3 >= (int)v47 )\n v46 = a3 + 1;\n goto LABEL_73;\n }\n }\n v58 = sub_13D0(v56, a2, a3);\nLABEL_69:\n a3 = (unsigned int)(v57 + 1);\n if ( v58 >= v57 )\n a3 = (unsigned int)(v58 + 1);\n goto LABEL_71;\n }\nLABEL_176:\n v53 = *(_QWORD *)(v45 + 16);\n v46 = 1;\n if ( !v53 )\n goto LABEL_73;\n goto LABEL_66;\n }\n v32 = *(_QWORD *)(v31 + 8);\n if ( !v32 )\n {\n v38 = *(_QWORD *)(v31 + 16);\n if ( !v38 )\n {\n v45 = *(_QWORD *)(v26 + 16);\n v27 = 2;\n if ( !v45 )\n goto LABEL_36;\n LODWORD(v31) = 1;\n goto LABEL_59;\n }\n goto LABEL_51;\n }\n v33 = *(_QWORD *)(v32 + 8);\n if ( v33 )\n {\n v34 = sub_13D0(v33, a2, a3);\n v35 = *(_QWORD *)(v32 + 16);\n v36 = v34;\n v37 = 0;\n if ( !v35 )\n goto LABEL_48;\n }\n else\n {\n v35 = *(_QWORD *)(v32 + 16);\n v36 = 0;\n if ( !v35 )\n {\n v38 = *(_QWORD *)(v31 + 16);\n LODWORD(v32) = 1;\n if ( !v38 )\n {\n v45 = *(_QWORD *)(v26 + 16);\n LODWORD(v31) = 2;\n if ( !v45 )\n goto LABEL_74;\n goto LABEL_59;\n }\n goto LABEL_51;\n }\n }\n v37 = sub_13D0(v35, a2, a3);\nLABEL_48:\n v38 = *(_QWORD *)(v31 + 16);\n LODWORD(v32) = v37 + 1;\n if ( v37 < v36 )\n LODWORD(v32) = v36 + 1;\n a3 = 0LL;\n if ( !v38 )\n {\nLABEL_56:\n v44 = v32 + 1;\n v45 = *(_QWORD *)(v26 + 16);\n if ( (int)a3 >= (int)v32 )\n v44 = a3 + 1;\n v46 = 0;\n LODWORD(v31) = v44;\n if ( !v45 )\n {\nLABEL_73:\n if ( v46 >= (int)v31 )\n {\n v27 = v46 + 1;\n goto LABEL_36;\n }\nLABEL_74:\n v27 = v31 + 1;\n goto LABEL_36;\n }\nLABEL_59:\n v47 = *(_QWORD *)(v45 + 8);\n if ( v47 )\n goto LABEL_60;\n goto LABEL_176;\n }\nLABEL_51:\n v39 = *(_QWORD *)(v38 + 8);\n if ( v39 )\n {\n v40 = sub_13D0(v39, a2, a3);\n v41 = *(_QWORD *)(v38 + 16);\n v42 = v40;\n v43 = 0;\n if ( !v41 )\n goto LABEL_54;\n }\n else\n {\n v41 = *(_QWORD *)(v38 + 16);\n a3 = 1LL;\n v42 = 0;\n if ( !v41 )\n goto LABEL_56;\n }\n v43 = sub_13D0(v41, a2, a3);\nLABEL_54:\n a3 = (unsigned int)(v42 + 1);\n if ( v43 >= v42 )\n a3 = (unsigned int)(v43 + 1);\n goto LABEL_56;\n }\nLABEL_19:\n v17 = *(_QWORD *)(v15 + 8);\n if ( !v17 )\n {\n v20 = *(_QWORD *)(v15 + 16);\n v16 = 1;\n if ( !v20 )\n goto LABEL_33;\n goto LABEL_26;\n }\n if ( *(_QWORD *)(v17 + 8) )\n {\n v18 = ((__int64 (*)(void))sub_13D0)();\n v19 = 0;\n if ( !*(_QWORD *)(v17 + 16) )\n goto LABEL_23;\n }\n else\n {\n v18 = 0;\n if ( !*(_QWORD *)(v17 + 16) )\n {\n v20 = *(_QWORD *)(v15 + 16);\n v16 = 2;\n if ( !v20 )\n goto LABEL_33;\n LODWORD(v17) = 1;\n goto LABEL_26;\n }\n }\n v19 = ((__int64 (*)(void))sub_13D0)();\nLABEL_23:\n v20 = *(_QWORD *)(v15 + 16);\n LODWORD(v17) = v19 + 1;\n if ( v19 < v18 )\n LODWORD(v17) = v18 + 1;\n a3 = 0LL;\n if ( !v20 )\n goto LABEL_31;\nLABEL_26:\n v21 = *(_QWORD *)(v20 + 8);\n if ( v21 )\n {\n v22 = sub_13D0(v21, a2, a3);\n v23 = *(_QWORD *)(v20 + 16);\n v24 = v22;\n v25 = 0;\n if ( !v23 )\n goto LABEL_29;\n }\n else\n {\n v23 = *(_QWORD *)(v20 + 16);\n a3 = 1LL;\n v24 = 0;\n if ( !v23 )\n {\nLABEL_31:\n v16 = v17 + 1;\n if ( (int)a3 >= (int)v17 )\n v16 = a3 + 1;\n goto LABEL_33;\n }\n }\n v25 = sub_13D0(v23, a2, a3);\nLABEL_29:\n LODWORD(a3) = v24 + 1;\n if ( v25 >= v24 )\n LODWORD(a3) = v25 + 1;\n goto LABEL_31;\n }\nLABEL_11:\n if ( *(_QWORD *)(v10 + 8) )\n {\n v12 = ((__int64 (*)(void))sub_13D0)();\n v13 = 0;\n if ( !*(_QWORD *)(v10 + 16) )\n goto LABEL_14;\n }\n else\n {\n v11 = 1;\n v12 = 0;\n if ( !*(_QWORD *)(v10 + 16) )\n goto LABEL_16;\n }\n v13 = ((__int64 (*)(void))sub_13D0)();\nLABEL_14:\n v14 = v13 < v12;\n v11 = v13 + 1;\n if ( v14 )\n v11 = v12 + 1;\n goto LABEL_16;\n }\n v26 = *(_QWORD *)(v4 + 16);\n if ( v26 )\n goto LABEL_43;\n v28 = *(_QWORD *)(a1 + 16);\n result = 2LL;\n LODWORD(v4) = 1;\n if ( v28 )\n goto LABEL_76;\n }\n else\n {\n v28 = *(_QWORD *)(a1 + 16);\n result = 1LL;\n if ( v28 )\n goto LABEL_76;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_13D0(long long a1, long long a2, long long a3) {\n long long v4;\n long long v5;\n long long v6;\n long long v7;\n int v8;\n int v9;\n long long v10;\n int v11;\n int v12;\n int v13;\n bool v14;\n long long v15;\n int v16;\n long long v17;\n int v18;\n int v19;\n long long v20;\n long long v21;\n int v22;\n long long v23;\n int v24;\n int v25;\n long long v26;\n int v27;\n long long v28;\n int v29;\n long long result;\n long long v31;\n long long v32;\n long long v33;\n int v34;\n long long v35;\n int v36;\n int v37;\n long long v38;\n long long v39;\n int v40;\n long long v41;\n int v42;\n int v43;\n int v44;\n long long v45;\n int v46;\n long long v47;\n long long v48;\n int v49;\n long long v50;\n int v51;\n int v52;\n long long v53;\n long long v54;\n int v55;\n long long v56;\n int v57;\n int v58;\n long long v59;\n long long v60;\n long long v61;\n long long v62;\n int v63;\n long long v64;\n int v65;\n int v66;\n long long v67;\n int v68;\n long long v69;\n int v70;\n long long v71;\n int v72;\n int v73;\n long long v74;\n long long v75;\n long long v76;\n int v77;\n long long v78;\n int v79;\n int v80;\n long long v81;\n int v82;\n long long v83;\n int v84;\n long long v85;\n int v86;\n int v87;\n int v88;\n long long v89;\n int v90;\n long long v91;\n long long v92;\n long long v93;\n int v94;\n long long v95;\n int v96;\n int v97;\n long long v98;\n long long v99;\n int v100;\n long long v101;\n int v102;\n int v103;\n int v104;\n long long v105;\n int v106;\n long long v107;\n long long v108;\n int v109;\n long long v110;\n int v111;\n int v112;\n long long v113;\n long long v114;\n int v115;\n long long v116;\n int v117;\n int v118;\n v4 = *(uint64_t *)(a1 + 8);\n if (v4) {\n v5 = *(uint64_t *)(v4 + 8);\n if (v5) {\n v6 = *(uint64_t *)(v5 + 8);\n if (!v6) {\n v15 = *(uint64_t *)(v5 + 16);\n if (!v15) {\n v26 = *(uint64_t *)(v4 + 16);\n LODWORD(v5) = 1;\n if (!v26) {\n v28 = *(uint64_t *)(a1 + 16);\n LODWORD(v4) = 2;\n if (!v28) return (unsigned int)(v4 + 1);\n goto LABEL_76;\n }\n goto LABEL_43;\n }\n goto LABEL_19;\n }\n v7 = *(uint64_t *)(v6 + 8);\n if (!v7) {\n v10 = *(uint64_t *)(v6 + 16);\n if (!v10) {\n v15 = *(uint64_t *)(v5 + 16);\n LODWORD(v6) = 1;\n if (!v15) {\n v26 = *(uint64_t *)(v4 + 16);\n LODWORD(v5) = 2;\n if (!v26) {\n v28 = *(uint64_t *)(a1 + 16);\n LODWORD(v4) = 3;\n if (!v28) return (unsigned int)(v4 + 1);\n goto LABEL_76;\n }\n goto LABEL_43;\n }\n goto LABEL_19;\n }\n goto LABEL_11;\n }\n if (*(uint64_t *)(v7 + 8)) {\n v8 = ((long long (*)(void))sub_13D0)();\n v9 = 0;\n if (!*(uint64_t *)(v7 + 16)) goto LABEL_8;\n } else {\n v8 = 0;\n if (!*(uint64_t *)(v7 + 16)) {\n v10 = *(uint64_t *)(v6 + 16);\n LODWORD(v7) = 1;\n if (!v10) {\n v15 = *(uint64_t *)(v5 + 16);\n LODWORD(v6) = 2;\n if (!v15) {\n v26 = *(uint64_t *)(v4 + 16);\n LODWORD(v5) = 3;\n if (!v26) {\n LABEL_37:\n LODWORD(v4) = v5 + 1;\n LABEL_38:\n v28 = *(uint64_t *)(a1 + 16);\n v29 = 0;\n if (!v28) goto LABEL_39;\n LABEL_76:\n v59 = *(uint64_t *)(v28 + 8);\n if (!v59) {\n v89 = *(uint64_t *)(v28 + 16);\n v29 = 1;\n if (!v89) goto LABEL_39;\n v91 = *(uint64_t *)(v89 + 8);\n if (v91) {\n LABEL_111:\n v92 = *(uint64_t *)(v91 + 8);\n if (!v92) {\n v98 = *(uint64_t *)(v91 + 16);\n if (!v98) {\n v105 = *(uint64_t *)(v89 + 16);\n v90 = 2;\n if (!v105) goto LABEL_142;\n LODWORD(v91) = 1;\n goto LABEL_126;\n }\n goto LABEL_118;\n }\n v93 = *(uint64_t *)(v92 + 8);\n if (v93) {\n v94 = sub_13D0(v93, a2, a3);\n v95 = *(uint64_t *)(v92 + 16);\n v96 = v94;\n v97 = 0;\n if (!v95) goto LABEL_115;\n } else {\n v95 = *(uint64_t *)(v92 + 16);\n v96 = 0;\n if (!v95) {\n v98 = *(uint64_t *)(v91 + 16);\n LODWORD(v92) = 1;\n if (!v98) {\n v105 = *(uint64_t *)(v89 + 16);\n LODWORD(v91) = 2;\n if (!v105) {\n LABEL_141:\n v90 = v91 + 1;\n LABEL_142:\n if (v90 < (int)v59) goto LABEL_143;\n v29 = v90 + 1;\n LABEL_39:\n if (v29 < (int)v4) return (unsigned int)(v4 + 1);\n return (unsigned int)(v29 + 1);\n }\n goto LABEL_126;\n }\n goto LABEL_118;\n }\n }\n v97 = sub_13D0(v95, a2, a3);\n LABEL_115:\n v98 = *(uint64_t *)(v91 + 16);\n LODWORD(v92) = v97 + 1;\n if (v97 < v96) LODWORD(v92) = v96 + 1;\n a3 = 0LL;\n if (!v98) {\n LABEL_123:\n v104 = v92 + 1;\n v105 = *(uint64_t *)(v89 + 16);\n if ((int)a3 >= (int)v92) v104 = a3 + 1;\n v106 = 0;\n LODWORD(v91) = v104;\n if (!v105) {\n LABEL_140:\n if (v106 >= (int)v91) {\n v90 = v106 + 1;\n goto LABEL_142;\n }\n goto LABEL_141;\n }\n LABEL_126:\n v107 = *(uint64_t *)(v105 + 8);\n if (v107) goto LABEL_127;\n goto LABEL_149;\n }\n LABEL_118:\n v99 = *(uint64_t *)(v98 + 8);\n if (v99) {\n v100 = sub_13D0(v99, a2, a3);\n v101 = *(uint64_t *)(v98 + 16);\n v102 = v100;\n v103 = 0;\n if (!v101) goto LABEL_121;\n } else {\n v101 = *(uint64_t *)(v98 + 16);\n a3 = 1LL;\n v102 = 0;\n if (!v101) goto LABEL_123;\n }\n v103 = sub_13D0(v101, a2, a3);\n LABEL_121:\n a3 = (unsigned int)(v102 + 1);\n if (v103 >= v102) a3 = (unsigned int)(v103 + 1);\n goto LABEL_123;\n }\n LABEL_147:\n v105 = *(uint64_t *)(v89 + 16);\n v90 = 1;\n if (!v105) goto LABEL_142;\n v107 = *(uint64_t *)(v105 + 8);\n if (v107) {\n LABEL_127:\n v108 = *(uint64_t *)(v107 + 8);\n if (v108) {\n v109 = sub_13D0(v108, a2, a3);\n v110 = *(uint64_t *)(v107 + 16);\n v111 = v109;\n v112 = 0;\n if (!v110) goto LABEL_130;\n } else {\n v110 = *(uint64_t *)(v107 + 16);\n v111 = 0;\n if (!v110) {\n v113 = *(uint64_t *)(v105 + 16);\n v106 = 2;\n if (!v113) goto LABEL_140;\n LODWORD(v107) = 1;\n goto LABEL_133;\n }\n }\n v112 = sub_13D0(v110, a2, a3);\n LABEL_130:\n v113 = *(uint64_t *)(v105 + 16);\n LODWORD(v107) = v112 + 1;\n if (v112 < v111) LODWORD(v107) = v111 + 1;\n a3 = 0LL;\n if (!v113) goto LABEL_138;\n LABEL_133:\n v114 = *(uint64_t *)(v113 + 8);\n if (v114) {\n v115 = sub_13D0(v114, a2, a3);\n v116 = *(uint64_t *)(v113 + 16);\n v117 = v115;\n v118 = 0;\n if (!v116) goto LABEL_136;\n } else {\n v116 = *(uint64_t *)(v113 + 16);\n a3 = 1LL;\n v117 = 0;\n if (!v116) {\n LABEL_138:\n v106 = v107 + 1;\n if ((int)a3 >= (int)v107) v106 = a3 + 1;\n goto LABEL_140;\n }\n }\n v118 = sub_13D0(v116, a2, a3);\n LABEL_136:\n LODWORD(a3) = v117 + 1;\n if (v118 >= v117) LODWORD(a3) = v118 + 1;\n goto LABEL_138;\n }\n LABEL_149:\n v113 = *(uint64_t *)(v105 + 16);\n v106 = 1;\n if (!v113) goto LABEL_140;\n goto LABEL_133;\n }\n v60 = *(uint64_t *)(v59 + 8);\n if (!v60) {\n v74 = *(uint64_t *)(v59 + 16);\n if (!v74) {\n v89 = *(uint64_t *)(v28 + 16);\n v29 = 2;\n if (!v89) goto LABEL_39;\n LODWORD(v59) = 1;\n goto LABEL_110;\n }\n goto LABEL_93;\n }\n v61 = *(uint64_t *)(v60 + 8);\n if (v61) {\n v62 = *(uint64_t *)(v61 + 8);\n if (v62) {\n v63 = sub_13D0(v62, a2, a3);\n v64 = *(uint64_t *)(v61 + 16);\n v65 = v63;\n v66 = 0;\n if (!v64) goto LABEL_82;\n goto LABEL_81;\n }\n v64 = *(uint64_t *)(v61 + 16);\n v65 = 0;\n if (v64) {\n LABEL_81:\n v66 = sub_13D0(v64, a2, a3);\n LABEL_82:\n v67 = *(uint64_t *)(v60 + 16);\n LODWORD(v61) = v66 + 1;\n a3 = (unsigned int)(v65 + 1);\n if (v66 < v65) LODWORD(v61) = v65 + 1;\n v68 = 0;\n if (!v67) {\n LABEL_90:\n v74 = *(uint64_t *)(v59 + 16);\n LODWORD(v60) = v68 + 1;\n if (v68 < (int)v61) LODWORD(v60) = v61 + 1;\n a3 = 0LL;\n if (!v74) {\n LABEL_107:\n v88 = v60 + 1;\n v14 = (int)a3 < (int)v60;\n v89 = *(uint64_t *)(v28 + 16);\n if (!v14) v88 = a3 + 1;\n v90 = 0;\n LODWORD(v59) = v88;\n if (!v89) goto LABEL_142;\n LABEL_110:\n v91 = *(uint64_t *)(v89 + 8);\n if (v91) goto LABEL_111;\n goto LABEL_147;\n }\n LABEL_93:\n v75 = *(uint64_t *)(v74 + 8);\n if (!v75) {\n v81 = *(uint64_t *)(v74 + 16);\n a3 = 1LL;\n if (!v81) goto LABEL_107;\n goto LABEL_100;\n }\n v76 = *(uint64_t *)(v75 + 8);\n if (v76) {\n v77 = sub_13D0(v76, a2, a3);\n v78 = *(uint64_t *)(v75 + 16);\n v79 = v77;\n v80 = 0;\n if (!v78) goto LABEL_97;\n } else {\n v78 = *(uint64_t *)(v75 + 16);\n v79 = 0;\n if (!v78) {\n v81 = *(uint64_t *)(v74 + 16);\n a3 = 2LL;\n if (!v81) goto LABEL_107;\n LODWORD(v75) = 1;\n goto LABEL_100;\n }\n }\n v80 = sub_13D0(v78, a2, a3);\n LABEL_97:\n v81 = *(uint64_t *)(v74 + 16);\n LODWORD(v75) = v80 + 1;\n a3 = (unsigned int)(v79 + 1);\n if (v80 < v79) LODWORD(v75) = v79 + 1;\n v82 = 0;\n if (!v81) goto LABEL_105;\n LABEL_100:\n v83 = *(uint64_t *)(v81 + 8);\n if (v83) {\n v84 = sub_13D0(v83, a2, a3);\n v85 = *(uint64_t *)(v81 + 16);\n v86 = v84;\n v87 = 0;\n if (!v85) goto LABEL_103;\n } else {\n v85 = *(uint64_t *)(v81 + 16);\n v82 = 1;\n v86 = 0;\n if (!v85) {\n LABEL_105:\n a3 = (unsigned int)(v75 + 1);\n if (v82 >= (int)v75) a3 = (unsigned int)(v82 + 1);\n goto LABEL_107;\n }\n }\n v87 = sub_13D0(v85, a2, a3);\n LABEL_103:\n v14 = v87 < v86;\n v82 = v87 + 1;\n if (v14) v82 = v86 + 1;\n goto LABEL_105;\n }\n LABEL_85:\n v69 = *(uint64_t *)(v67 + 8);\n if (v69) {\n v70 = sub_13D0(v69, a2, a3);\n v71 = *(uint64_t *)(v67 + 16);\n v72 = v70;\n v73 = 0;\n if (!v71) goto LABEL_88;\n } else {\n v71 = *(uint64_t *)(v67 + 16);\n v68 = 1;\n v72 = 0;\n if (!v71) goto LABEL_90;\n }\n v73 = sub_13D0(v71, a2, a3);\n LABEL_88:\n v14 = v73 < v72;\n v68 = v73 + 1;\n if (v14) v68 = v72 + 1;\n goto LABEL_90;\n }\n v67 = *(uint64_t *)(v60 + 16);\n LODWORD(v61) = 1;\n if (v67) goto LABEL_85;\n v74 = *(uint64_t *)(v59 + 16);\n LODWORD(v60) = 2;\n if (v74) goto LABEL_93;\n v89 = *(uint64_t *)(v28 + 16);\n LODWORD(v59) = 3;\n if (v89) goto LABEL_110;\n } else {\n v67 = *(uint64_t *)(v60 + 16);\n if (v67) goto LABEL_85;\n v74 = *(uint64_t *)(v59 + 16);\n LODWORD(v60) = 1;\n if (v74) goto LABEL_93;\n v89 = *(uint64_t *)(v28 + 16);\n LODWORD(v59) = 2;\n if (v89) goto LABEL_110;\n }\n LABEL_143:\n v29 = v59 + 1;\n if ((int)v59 + 1 < (int)v4) return (unsigned int)(v4 + 1);\n return (unsigned int)(v29 + 1);\n }\n goto LABEL_43;\n }\n goto LABEL_19;\n }\n goto LABEL_11;\n }\n }\n v9 = ((long long (*)(void))sub_13D0)();\n LABEL_8:\n v10 = *(uint64_t *)(v6 + 16);\n LODWORD(v7) = v9 + 1;\n if (v9 < v8) LODWORD(v7) = v8 + 1;\n v11 = 0;\n if (!v10) {\n LABEL_16:\n v15 = *(uint64_t *)(v5 + 16);\n LODWORD(v6) = v11 + 1;\n a3 = (unsigned int)(v7 + 1);\n if (v11 < (int)v7) LODWORD(v6) = v7 + 1;\n v16 = 0;\n if (!v15) {\n LABEL_33:\n a3 = (unsigned int)(v6 + 1);\n LODWORD(v5) = v16 + 1;\n v14 = v16 < (int)v6;\n v26 = *(uint64_t *)(v4 + 16);\n if (v14) LODWORD(v5) = a3;\n v27 = 0;\n if (!v26) {\n LABEL_36:\n LODWORD(v4) = v27 + 1;\n if (v27 >= (int)v5) goto LABEL_38;\n goto LABEL_37;\n }\n LABEL_43:\n v31 = *(uint64_t *)(v26 + 8);\n if (!v31) {\n v45 = *(uint64_t *)(v26 + 16);\n v27 = 1;\n if (!v45) goto LABEL_36;\n v47 = *(uint64_t *)(v45 + 8);\n if (v47) {\n LABEL_60:\n v48 = *(uint64_t *)(v47 + 8);\n if (v48) {\n v49 = sub_13D0(v48, a2, a3);\n v50 = *(uint64_t *)(v47 + 16);\n v51 = v49;\n v52 = 0;\n if (!v50) goto LABEL_63;\n } else {\n v50 = *(uint64_t *)(v47 + 16);\n v51 = 0;\n if (!v50) {\n v53 = *(uint64_t *)(v45 + 16);\n v46 = 2;\n if (!v53) goto LABEL_73;\n LODWORD(v47) = 1;\n goto LABEL_66;\n }\n }\n v52 = sub_13D0(v50, a2, a3);\n LABEL_63:\n v53 = *(uint64_t *)(v45 + 16);\n LODWORD(v47) = v52 + 1;\n if (v52 < v51) LODWORD(v47) = v51 + 1;\n a3 = 0LL;\n if (!v53) goto LABEL_71;\n LABEL_66:\n v54 = *(uint64_t *)(v53 + 8);\n if (v54) {\n v55 = sub_13D0(v54, a2, a3);\n v56 = *(uint64_t *)(v53 + 16);\n v57 = v55;\n v58 = 0;\n if (!v56) goto LABEL_69;\n } else {\n v56 = *(uint64_t *)(v53 + 16);\n a3 = 1LL;\n v57 = 0;\n if (!v56) {\n LABEL_71:\n v46 = v47 + 1;\n if ((int)a3 >= (int)v47) v46 = a3 + 1;\n goto LABEL_73;\n }\n }\n v58 = sub_13D0(v56, a2, a3);\n LABEL_69:\n a3 = (unsigned int)(v57 + 1);\n if (v58 >= v57) a3 = (unsigned int)(v58 + 1);\n goto LABEL_71;\n }\n LABEL_176:\n v53 = *(uint64_t *)(v45 + 16);\n v46 = 1;\n if (!v53) goto LABEL_73;\n goto LABEL_66;\n }\n v32 = *(uint64_t *)(v31 + 8);\n if (!v32) {\n v38 = *(uint64_t *)(v31 + 16);\n if (!v38) {\n v45 = *(uint64_t *)(v26 + 16);\n v27 = 2;\n if (!v45) goto LABEL_36;\n LODWORD(v31) = 1;\n goto LABEL_59;\n }\n goto LABEL_51;\n }\n v33 = *(uint64_t *)(v32 + 8);\n if (v33) {\n v34 = sub_13D0(v33, a2, a3);\n v35 = *(uint64_t *)(v32 + 16);\n v36 = v34;\n v37 = 0;\n if (!v35) goto LABEL_48;\n } else {\n v35 = *(uint64_t *)(v32 + 16);\n v36 = 0;\n if (!v35) {\n v38 = *(uint64_t *)(v31 + 16);\n LODWORD(v32) = 1;\n if (!v38) {\n v45 = *(uint64_t *)(v26 + 16);\n LODWORD(v31) = 2;\n if (!v45) goto LABEL_74;\n goto LABEL_59;\n }\n goto LABEL_51;\n }\n }\n v37 = sub_13D0(v35, a2, a3);\n LABEL_48:\n v38 = *(uint64_t *)(v31 + 16);\n LODWORD(v32) = v37 + 1;\n if (v37 < v36) LODWORD(v32) = v36 + 1;\n a3 = 0LL;\n if (!v38) {\n LABEL_56:\n v44 = v32 + 1;\n v45 = *(uint64_t *)(v26 + 16);\n if ((int)a3 >= (int)v32) v44 = a3 + 1;\n v46 = 0;\n LODWORD(v31) = v44;\n if (!v45) {\n LABEL_73:\n if (v46 >= (int)v31) {\n v27 = v46 + 1;\n goto LABEL_36;\n }\n LABEL_74:\n v27 = v31 + 1;\n goto LABEL_36;\n }\n LABEL_59:\n v47 = *(uint64_t *)(v45 + 8);\n if (v47) goto LABEL_60;\n goto LABEL_176;\n }\n LABEL_51:\n v39 = *(uint64_t *)(v38 + 8);\n if (v39) {\n v40 = sub_13D0(v39, a2, a3);\n v41 = *(uint64_t *)(v38 + 16);\n v42 = v40;\n v43 = 0;\n if (!v41) goto LABEL_54;\n } else {\n v41 = *(uint64_t *)(v38 + 16);\n a3 = 1LL;\n v42 = 0;\n if (!v41) goto LABEL_56;\n }\n v43 = sub_13D0(v41, a2, a3);\n LABEL_54:\n a3 = (unsigned int)(v42 + 1);\n if (v43 >= v42) a3 = (unsigned int)(v43 + 1);\n goto LABEL_56;\n }\n LABEL_19:\n v17 = *(uint64_t *)(v15 + 8);\n if (!v17) {\n v20 = *(uint64_t *)(v15 + 16);\n v16 = 1;\n if (!v20) goto LABEL_33;\n goto LABEL_26;\n }\n if (*(uint64_t *)(v17 + 8)) {\n v18 = ((long long (*)(void))sub_13D0)();\n v19 = 0;\n if (!*(uint64_t *)(v17 + 16)) goto LABEL_23;\n } else {\n v18 = 0;\n if (!*(uint64_t *)(v17 + 16)) {\n v20 = *(uint64_t *)(v15 + 16);\n v16 = 2;\n if (!v20) goto LABEL_33;\n LODWORD(v17) = 1;\n goto LABEL_26;\n }\n }\n v19 = ((long long (*)(void))sub_13D0)();\n LABEL_23:\n v20 = *(uint64_t *)(v15 + 16);\n LODWORD(v17) = v19 + 1;\n if (v19 < v18) LODWORD(v17) = v18 + 1;\n a3 = 0LL;\n if (!v20) goto LABEL_31;\n LABEL_26:\n v21 = *(uint64_t *)(v20 + 8);\n if (v21) {\n v22 = sub_13D0(v21, a2, a3);\n v23 = *(uint64_t *)(v20 + 16);\n v24 = v22;\n v25 = 0;\n if (!v23) goto LABEL_29;\n } else {\n v23 = *(uint64_t *)(v20 + 16);\n a3 = 1LL;\n v24 = 0;\n if (!v23) {\n LABEL_31:\n v16 = v17 + 1;\n if ((int)a3 >= (int)v17) v16 = a3 + 1;\n goto LABEL_33;\n }\n }\n v25 = sub_13D0(v23, a2, a3);\n LABEL_29:\n LODWORD(a3) = v24 + 1;\n if (v25 >= v24) LODWORD(a3) = v25 + 1;\n goto LABEL_31;\n }\n LABEL_11:\n if (*(uint64_t *)(v10 + 8)) {\n v12 = ((long long (*)(void))sub_13D0)();\n v13 = 0;\n if (!*(uint64_t *)(v10 + 16)) goto LABEL_14;\n } else {\n v11 = 1;\n v12 = 0;\n if (!*(uint64_t *)(v10 + 16)) goto LABEL_16;\n }\n v13 = ((long long (*)(void))sub_13D0)();\n LABEL_14:\n v14 = v13 < v12;\n v11 = v13 + 1;\n if (v14) v11 = v12 + 1;\n goto LABEL_16;\n }\n v26 = *(uint64_t *)(v4 + 16);\n if (v26) goto LABEL_43;\n v28 = *(uint64_t *)(a1 + 16);\n result = 2LL;\n LODWORD(v4) = 1;\n if (v28) goto LABEL_76;\n } else {\n v28 = *(uint64_t *)(a1 + 16);\n result = 1LL;\n if (v28) goto LABEL_76;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0_part_0(long long a1, long long a2, long long a3) {\n long long v4;\n long long v5;\n long long v6;\n long long v7;\n int v8;\n int v9;\n long long v10;\n int v11;\n int v12;\n int v13;\n bool v14;\n long long v15;\n int v16;\n long long v17;\n int v18;\n int v19;\n long long v20;\n long long v21;\n int v22;\n long long v23;\n int v24;\n int v25;\n long long v26;\n int v27;\n long long v28;\n int v29;\n long long result;\n long long v31;\n long long v32;\n long long v33;\n int v34;\n long long v35;\n int v36;\n int v37;\n long long v38;\n long long v39;\n int v40;\n long long v41;\n int v42;\n int v43;\n int v44;\n long long v45;\n int v46;\n long long v47;\n long long v48;\n int v49;\n long long v50;\n int v51;\n int v52;\n long long v53;\n long long v54;\n int v55;\n long long v56;\n int v57;\n int v58;\n long long v59;\n long long v60;\n long long v61;\n long long v62;\n int v63;\n long long v64;\n int v65;\n int v66;\n long long v67;\n int v68;\n long long v69;\n int v70;\n long long v71;\n int v72;\n int v73;\n long long v74;\n long long v75;\n long long v76;\n int v77;\n long long v78;\n int v79;\n int v80;\n long long v81;\n int v82;\n long long v83;\n int v84;\n long long v85;\n int v86;\n int v87;\n int v88;\n long long v89;\n int v90;\n long long v91;\n long long v92;\n long long v93;\n int v94;\n long long v95;\n int v96;\n int v97;\n long long v98;\n long long v99;\n int v100;\n long long v101;\n int v102;\n int v103;\n int v104;\n long long v105;\n int v106;\n long long v107;\n long long v108;\n int v109;\n long long v110;\n int v111;\n int v112;\n long long v113;\n long long v114;\n int v115;\n long long v116;\n int v117;\n int v118;\n v4 = *(uint64_t *)(a1 + 8);\n if (v4) {\n v5 = *(uint64_t *)(v4 + 8);\n if (v5) {\n v6 = *(uint64_t *)(v5 + 8);\n if (!v6) {\n v15 = *(uint64_t *)(v5 + 16);\n if (!v15) {\n v26 = *(uint64_t *)(v4 + 16);\n LODWORD(v5) = 1;\n if (!v26) {\n v28 = *(uint64_t *)(a1 + 16);\n LODWORD(v4) = 2;\n if (!v28) return (unsigned int)(v4 + 1);\n goto LABEL_76;\n }\n goto LABEL_43;\n }\n goto LABEL_19;\n }\n v7 = *(uint64_t *)(v6 + 8);\n if (!v7) {\n v10 = *(uint64_t *)(v6 + 16);\n if (!v10) {\n v15 = *(uint64_t *)(v5 + 16);\n LODWORD(v6) = 1;\n if (!v15) {\n v26 = *(uint64_t *)(v4 + 16);\n LODWORD(v5) = 2;\n if (!v26) {\n v28 = *(uint64_t *)(a1 + 16);\n LODWORD(v4) = 3;\n if (!v28) return (unsigned int)(v4 + 1);\n goto LABEL_76;\n }\n goto LABEL_43;\n }\n goto LABEL_19;\n }\n goto LABEL_11;\n }\n if (*(uint64_t *)(v7 + 8)) {\n v8 = ((long long (*)(void))func0_part_0)();\n v9 = 0;\n if (!*(uint64_t *)(v7 + 16)) goto LABEL_8;\n } else {\n v8 = 0;\n if (!*(uint64_t *)(v7 + 16)) {\n v10 = *(uint64_t *)(v6 + 16);\n LODWORD(v7) = 1;\n if (!v10) {\n v15 = *(uint64_t *)(v5 + 16);\n LODWORD(v6) = 2;\n if (!v15) {\n v26 = *(uint64_t *)(v4 + 16);\n LODWORD(v5) = 3;\n if (!v26) {\n LABEL_37:\n LODWORD(v4) = v5 + 1;\n LABEL_38:\n v28 = *(uint64_t *)(a1 + 16);\n v29 = 0;\n if (!v28) goto LABEL_39;\n LABEL_76:\n v59 = *(uint64_t *)(v28 + 8);\n if (!v59) {\n v89 = *(uint64_t *)(v28 + 16);\n v29 = 1;\n if (!v89) goto LABEL_39;\n v91 = *(uint64_t *)(v89 + 8);\n if (v91) {\n LABEL_111:\n v92 = *(uint64_t *)(v91 + 8);\n if (!v92) {\n v98 = *(uint64_t *)(v91 + 16);\n if (!v98) {\n v105 = *(uint64_t *)(v89 + 16);\n v90 = 2;\n if (!v105) goto LABEL_142;\n LODWORD(v91) = 1;\n goto LABEL_126;\n }\n goto LABEL_118;\n }\n v93 = *(uint64_t *)(v92 + 8);\n if (v93) {\n v94 = func0_part_0(v93, a2, a3);\n v95 = *(uint64_t *)(v92 + 16);\n v96 = v94;\n v97 = 0;\n if (!v95) goto LABEL_115;\n } else {\n v95 = *(uint64_t *)(v92 + 16);\n v96 = 0;\n if (!v95) {\n v98 = *(uint64_t *)(v91 + 16);\n LODWORD(v92) = 1;\n if (!v98) {\n v105 = *(uint64_t *)(v89 + 16);\n LODWORD(v91) = 2;\n if (!v105) {\n LABEL_141:\n v90 = v91 + 1;\n LABEL_142:\n if (v90 < (int)v59) goto LABEL_143;\n v29 = v90 + 1;\n LABEL_39:\n if (v29 < (int)v4) return (unsigned int)(v4 + 1);\n return (unsigned int)(v29 + 1);\n }\n goto LABEL_126;\n }\n goto LABEL_118;\n }\n }\n v97 = func0_part_0(v95, a2, a3);\n LABEL_115:\n v98 = *(uint64_t *)(v91 + 16);\n LODWORD(v92) = v97 + 1;\n if (v97 < v96) LODWORD(v92) = v96 + 1;\n a3 = 0LL;\n if (!v98) {\n LABEL_123:\n v104 = v92 + 1;\n v105 = *(uint64_t *)(v89 + 16);\n if ((int)a3 >= (int)v92) v104 = a3 + 1;\n v106 = 0;\n LODWORD(v91) = v104;\n if (!v105) {\n LABEL_140:\n if (v106 >= (int)v91) {\n v90 = v106 + 1;\n goto LABEL_142;\n }\n goto LABEL_141;\n }\n LABEL_126:\n v107 = *(uint64_t *)(v105 + 8);\n if (v107) goto LABEL_127;\n goto LABEL_149;\n }\n LABEL_118:\n v99 = *(uint64_t *)(v98 + 8);\n if (v99) {\n v100 = func0_part_0(v99, a2, a3);\n v101 = *(uint64_t *)(v98 + 16);\n v102 = v100;\n v103 = 0;\n if (!v101) goto LABEL_121;\n } else {\n v101 = *(uint64_t *)(v98 + 16);\n a3 = 1LL;\n v102 = 0;\n if (!v101) goto LABEL_123;\n }\n v103 = func0_part_0(v101, a2, a3);\n LABEL_121:\n a3 = (unsigned int)(v102 + 1);\n if (v103 >= v102) a3 = (unsigned int)(v103 + 1);\n goto LABEL_123;\n }\n LABEL_147:\n v105 = *(uint64_t *)(v89 + 16);\n v90 = 1;\n if (!v105) goto LABEL_142;\n v107 = *(uint64_t *)(v105 + 8);\n if (v107) {\n LABEL_127:\n v108 = *(uint64_t *)(v107 + 8);\n if (v108) {\n v109 = func0_part_0(v108, a2, a3);\n v110 = *(uint64_t *)(v107 + 16);\n v111 = v109;\n v112 = 0;\n if (!v110) goto LABEL_130;\n } else {\n v110 = *(uint64_t *)(v107 + 16);\n v111 = 0;\n if (!v110) {\n v113 = *(uint64_t *)(v105 + 16);\n v106 = 2;\n if (!v113) goto LABEL_140;\n LODWORD(v107) = 1;\n goto LABEL_133;\n }\n }\n v112 = func0_part_0(v110, a2, a3);\n LABEL_130:\n v113 = *(uint64_t *)(v105 + 16);\n LODWORD(v107) = v112 + 1;\n if (v112 < v111) LODWORD(v107) = v111 + 1;\n a3 = 0LL;\n if (!v113) goto LABEL_138;\n LABEL_133:\n v114 = *(uint64_t *)(v113 + 8);\n if (v114) {\n v115 = func0_part_0(v114, a2, a3);\n v116 = *(uint64_t *)(v113 + 16);\n v117 = v115;\n v118 = 0;\n if (!v116) goto LABEL_136;\n } else {\n v116 = *(uint64_t *)(v113 + 16);\n a3 = 1LL;\n v117 = 0;\n if (!v116) {\n LABEL_138:\n v106 = v107 + 1;\n if ((int)a3 >= (int)v107) v106 = a3 + 1;\n goto LABEL_140;\n }\n }\n v118 = func0_part_0(v116, a2, a3);\n LABEL_136:\n LODWORD(a3) = v117 + 1;\n if (v118 >= v117) LODWORD(a3) = v118 + 1;\n goto LABEL_138;\n }\n LABEL_149:\n v113 = *(uint64_t *)(v105 + 16);\n v106 = 1;\n if (!v113) goto LABEL_140;\n goto LABEL_133;\n }\n v60 = *(uint64_t *)(v59 + 8);\n if (!v60) {\n v74 = *(uint64_t *)(v59 + 16);\n if (!v74) {\n v89 = *(uint64_t *)(v28 + 16);\n v29 = 2;\n if (!v89) goto LABEL_39;\n LODWORD(v59) = 1;\n goto LABEL_110;\n }\n goto LABEL_93;\n }\n v61 = *(uint64_t *)(v60 + 8);\n if (v61) {\n v62 = *(uint64_t *)(v61 + 8);\n if (v62) {\n v63 = func0_part_0(v62, a2, a3);\n v64 = *(uint64_t *)(v61 + 16);\n v65 = v63;\n v66 = 0;\n if (!v64) goto LABEL_82;\n goto LABEL_81;\n }\n v64 = *(uint64_t *)(v61 + 16);\n v65 = 0;\n if (v64) {\n LABEL_81:\n v66 = func0_part_0(v64, a2, a3);\n LABEL_82:\n v67 = *(uint64_t *)(v60 + 16);\n LODWORD(v61) = v66 + 1;\n a3 = (unsigned int)(v65 + 1);\n if (v66 < v65) LODWORD(v61) = v65 + 1;\n v68 = 0;\n if (!v67) {\n LABEL_90:\n v74 = *(uint64_t *)(v59 + 16);\n LODWORD(v60) = v68 + 1;\n if (v68 < (int)v61) LODWORD(v60) = v61 + 1;\n a3 = 0LL;\n if (!v74) {\n LABEL_107:\n v88 = v60 + 1;\n v14 = (int)a3 < (int)v60;\n v89 = *(uint64_t *)(v28 + 16);\n if (!v14) v88 = a3 + 1;\n v90 = 0;\n LODWORD(v59) = v88;\n if (!v89) goto LABEL_142;\n LABEL_110:\n v91 = *(uint64_t *)(v89 + 8);\n if (v91) goto LABEL_111;\n goto LABEL_147;\n }\n LABEL_93:\n v75 = *(uint64_t *)(v74 + 8);\n if (!v75) {\n v81 = *(uint64_t *)(v74 + 16);\n a3 = 1LL;\n if (!v81) goto LABEL_107;\n goto LABEL_100;\n }\n v76 = *(uint64_t *)(v75 + 8);\n if (v76) {\n v77 = func0_part_0(v76, a2, a3);\n v78 = *(uint64_t *)(v75 + 16);\n v79 = v77;\n v80 = 0;\n if (!v78) goto LABEL_97;\n } else {\n v78 = *(uint64_t *)(v75 + 16);\n v79 = 0;\n if (!v78) {\n v81 = *(uint64_t *)(v74 + 16);\n a3 = 2LL;\n if (!v81) goto LABEL_107;\n LODWORD(v75) = 1;\n goto LABEL_100;\n }\n }\n v80 = func0_part_0(v78, a2, a3);\n LABEL_97:\n v81 = *(uint64_t *)(v74 + 16);\n LODWORD(v75) = v80 + 1;\n a3 = (unsigned int)(v79 + 1);\n if (v80 < v79) LODWORD(v75) = v79 + 1;\n v82 = 0;\n if (!v81) goto LABEL_105;\n LABEL_100:\n v83 = *(uint64_t *)(v81 + 8);\n if (v83) {\n v84 = func0_part_0(v83, a2, a3);\n v85 = *(uint64_t *)(v81 + 16);\n v86 = v84;\n v87 = 0;\n if (!v85) goto LABEL_103;\n } else {\n v85 = *(uint64_t *)(v81 + 16);\n v82 = 1;\n v86 = 0;\n if (!v85) {\n LABEL_105:\n a3 = (unsigned int)(v75 + 1);\n if (v82 >= (int)v75) a3 = (unsigned int)(v82 + 1);\n goto LABEL_107;\n }\n }\n v87 = func0_part_0(v85, a2, a3);\n LABEL_103:\n v14 = v87 < v86;\n v82 = v87 + 1;\n if (v14) v82 = v86 + 1;\n goto LABEL_105;\n }\n LABEL_85:\n v69 = *(uint64_t *)(v67 + 8);\n if (v69) {\n v70 = func0_part_0(v69, a2, a3);\n v71 = *(uint64_t *)(v67 + 16);\n v72 = v70;\n v73 = 0;\n if (!v71) goto LABEL_88;\n } else {\n v71 = *(uint64_t *)(v67 + 16);\n v68 = 1;\n v72 = 0;\n if (!v71) goto LABEL_90;\n }\n v73 = func0_part_0(v71, a2, a3);\n LABEL_88:\n v14 = v73 < v72;\n v68 = v73 + 1;\n if (v14) v68 = v72 + 1;\n goto LABEL_90;\n }\n v67 = *(uint64_t *)(v60 + 16);\n LODWORD(v61) = 1;\n if (v67) goto LABEL_85;\n v74 = *(uint64_t *)(v59 + 16);\n LODWORD(v60) = 2;\n if (v74) goto LABEL_93;\n v89 = *(uint64_t *)(v28 + 16);\n LODWORD(v59) = 3;\n if (v89) goto LABEL_110;\n } else {\n v67 = *(uint64_t *)(v60 + 16);\n if (v67) goto LABEL_85;\n v74 = *(uint64_t *)(v59 + 16);\n LODWORD(v60) = 1;\n if (v74) goto LABEL_93;\n v89 = *(uint64_t *)(v28 + 16);\n LODWORD(v59) = 2;\n if (v89) goto LABEL_110;\n }\n LABEL_143:\n v29 = v59 + 1;\n if ((int)v59 + 1 < (int)v4) return (unsigned int)(v4 + 1);\n return (unsigned int)(v29 + 1);\n }\n goto LABEL_43;\n }\n goto LABEL_19;\n }\n goto LABEL_11;\n }\n }\n v9 = ((long long (*)(void))func0_part_0)();\n LABEL_8:\n v10 = *(uint64_t *)(v6 + 16);\n LODWORD(v7) = v9 + 1;\n if (v9 < v8) LODWORD(v7) = v8 + 1;\n v11 = 0;\n if (!v10) {\n LABEL_16:\n v15 = *(uint64_t *)(v5 + 16);\n LODWORD(v6) = v11 + 1;\n a3 = (unsigned int)(v7 + 1);\n if (v11 < (int)v7) LODWORD(v6) = v7 + 1;\n v16 = 0;\n if (!v15) {\n LABEL_33:\n a3 = (unsigned int)(v6 + 1);\n LODWORD(v5) = v16 + 1;\n v14 = v16 < (int)v6;\n v26 = *(uint64_t *)(v4 + 16);\n if (v14) LODWORD(v5) = a3;\n v27 = 0;\n if (!v26) {\n LABEL_36:\n LODWORD(v4) = v27 + 1;\n if (v27 >= (int)v5) goto LABEL_38;\n goto LABEL_37;\n }\n LABEL_43:\n v31 = *(uint64_t *)(v26 + 8);\n if (!v31) {\n v45 = *(uint64_t *)(v26 + 16);\n v27 = 1;\n if (!v45) goto LABEL_36;\n v47 = *(uint64_t *)(v45 + 8);\n if (v47) {\n LABEL_60:\n v48 = *(uint64_t *)(v47 + 8);\n if (v48) {\n v49 = func0_part_0(v48, a2, a3);\n v50 = *(uint64_t *)(v47 + 16);\n v51 = v49;\n v52 = 0;\n if (!v50) goto LABEL_63;\n } else {\n v50 = *(uint64_t *)(v47 + 16);\n v51 = 0;\n if (!v50) {\n v53 = *(uint64_t *)(v45 + 16);\n v46 = 2;\n if (!v53) goto LABEL_73;\n LODWORD(v47) = 1;\n goto LABEL_66;\n }\n }\n v52 = func0_part_0(v50, a2, a3);\n LABEL_63:\n v53 = *(uint64_t *)(v45 + 16);\n LODWORD(v47) = v52 + 1;\n if (v52 < v51) LODWORD(v47) = v51 + 1;\n a3 = 0LL;\n if (!v53) goto LABEL_71;\n LABEL_66:\n v54 = *(uint64_t *)(v53 + 8);\n if (v54) {\n v55 = func0_part_0(v54, a2, a3);\n v56 = *(uint64_t *)(v53 + 16);\n v57 = v55;\n v58 = 0;\n if (!v56) goto LABEL_69;\n } else {\n v56 = *(uint64_t *)(v53 + 16);\n a3 = 1LL;\n v57 = 0;\n if (!v56) {\n LABEL_71:\n v46 = v47 + 1;\n if ((int)a3 >= (int)v47) v46 = a3 + 1;\n goto LABEL_73;\n }\n }\n v58 = func0_part_0(v56, a2, a3);\n LABEL_69:\n a3 = (unsigned int)(v57 + 1);\n if (v58 >= v57) a3 = (unsigned int)(v58 + 1);\n goto LABEL_71;\n }\n LABEL_176:\n v53 = *(uint64_t *)(v45 + 16);\n v46 = 1;\n if (!v53) goto LABEL_73;\n goto LABEL_66;\n }\n v32 = *(uint64_t *)(v31 + 8);\n if (!v32) {\n v38 = *(uint64_t *)(v31 + 16);\n if (!v38) {\n v45 = *(uint64_t *)(v26 + 16);\n v27 = 2;\n if (!v45) goto LABEL_36;\n LODWORD(v31) = 1;\n goto LABEL_59;\n }\n goto LABEL_51;\n }\n v33 = *(uint64_t *)(v32 + 8);\n if (v33) {\n v34 = func0_part_0(v33, a2, a3);\n v35 = *(uint64_t *)(v32 + 16);\n v36 = v34;\n v37 = 0;\n if (!v35) goto LABEL_48;\n } else {\n v35 = *(uint64_t *)(v32 + 16);\n v36 = 0;\n if (!v35) {\n v38 = *(uint64_t *)(v31 + 16);\n LODWORD(v32) = 1;\n if (!v38) {\n v45 = *(uint64_t *)(v26 + 16);\n LODWORD(v31) = 2;\n if (!v45) goto LABEL_74;\n goto LABEL_59;\n }\n goto LABEL_51;\n }\n }\n v37 = func0_part_0(v35, a2, a3);\n LABEL_48:\n v38 = *(uint64_t *)(v31 + 16);\n LODWORD(v32) = v37 + 1;\n if (v37 < v36) LODWORD(v32) = v36 + 1;\n a3 = 0LL;\n if (!v38) {\n LABEL_56:\n v44 = v32 + 1;\n v45 = *(uint64_t *)(v26 + 16);\n if ((int)a3 >= (int)v32) v44 = a3 + 1;\n v46 = 0;\n LODWORD(v31) = v44;\n if (!v45) {\n LABEL_73:\n if (v46 >= (int)v31) {\n v27 = v46 + 1;\n goto LABEL_36;\n }\n LABEL_74:\n v27 = v31 + 1;\n goto LABEL_36;\n }\n LABEL_59:\n v47 = *(uint64_t *)(v45 + 8);\n if (v47) goto LABEL_60;\n goto LABEL_176;\n }\n LABEL_51:\n v39 = *(uint64_t *)(v38 + 8);\n if (v39) {\n v40 = func0_part_0(v39, a2, a3);\n v41 = *(uint64_t *)(v38 + 16);\n v42 = v40;\n v43 = 0;\n if (!v41) goto LABEL_54;\n } else {\n v41 = *(uint64_t *)(v38 + 16);\n a3 = 1LL;\n v42 = 0;\n if (!v41) goto LABEL_56;\n }\n v43 = func0_part_0(v41, a2, a3);\n LABEL_54:\n a3 = (unsigned int)(v42 + 1);\n if (v43 >= v42) a3 = (unsigned int)(v43 + 1);\n goto LABEL_56;\n }\n LABEL_19:\n v17 = *(uint64_t *)(v15 + 8);\n if (!v17) {\n v20 = *(uint64_t *)(v15 + 16);\n v16 = 1;\n if (!v20) goto LABEL_33;\n goto LABEL_26;\n }\n if (*(uint64_t *)(v17 + 8)) {\n v18 = ((long long (*)(void))func0_part_0)();\n v19 = 0;\n if (!*(uint64_t *)(v17 + 16)) goto LABEL_23;\n } else {\n v18 = 0;\n if (!*(uint64_t *)(v17 + 16)) {\n v20 = *(uint64_t *)(v15 + 16);\n v16 = 2;\n if (!v20) goto LABEL_33;\n LODWORD(v17) = 1;\n goto LABEL_26;\n }\n }\n v19 = ((long long (*)(void))func0_part_0)();\n LABEL_23:\n v20 = *(uint64_t *)(v15 + 16);\n LODWORD(v17) = v19 + 1;\n if (v19 < v18) LODWORD(v17) = v18 + 1;\n a3 = 0LL;\n if (!v20) goto LABEL_31;\n LABEL_26:\n v21 = *(uint64_t *)(v20 + 8);\n if (v21) {\n v22 = func0_part_0(v21, a2, a3);\n v23 = *(uint64_t *)(v20 + 16);\n v24 = v22;\n v25 = 0;\n if (!v23) goto LABEL_29;\n } else {\n v23 = *(uint64_t *)(v20 + 16);\n a3 = 1LL;\n v24 = 0;\n if (!v23) {\n LABEL_31:\n v16 = v17 + 1;\n if ((int)a3 >= (int)v17) v16 = a3 + 1;\n goto LABEL_33;\n }\n }\n v25 = func0_part_0(v23, a2, a3);\n LABEL_29:\n LODWORD(a3) = v24 + 1;\n if (v25 >= v24) LODWORD(a3) = v25 + 1;\n goto LABEL_31;\n }\n LABEL_11:\n if (*(uint64_t *)(v10 + 8)) {\n v12 = ((long long (*)(void))func0_part_0)();\n v13 = 0;\n if (!*(uint64_t *)(v10 + 16)) goto LABEL_14;\n } else {\n v11 = 1;\n v12 = 0;\n if (!*(uint64_t *)(v10 + 16)) goto LABEL_16;\n }\n v13 = ((long long (*)(void))func0_part_0)();\n LABEL_14:\n v14 = v13 < v12;\n v11 = v13 + 1;\n if (v14) v11 = v12 + 1;\n goto LABEL_16;\n }\n v26 = *(uint64_t *)(v4 + 16);\n if (v26) goto LABEL_43;\n v28 = *(uint64_t *)(a1 + 16);\n result = 2LL;\n LODWORD(v4) = 1;\n if (v28) goto LABEL_76;\n } else {\n v28 = *(uint64_t *)(a1 + 16);\n result = 1LL;\n if (v28) goto LABEL_76;\n }\n return result;\n}" + }, + { + "index": 927, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n// Node structure\n\ntypedef struct Node {\n\n int data;\n\n struct Node* left;\n\n struct Node* right;\n\n} Node;\n\n\n\n// Function to create a new node\n\nNode* newNode(int data) {\n\n Node* node = (Node*) malloc(sizeof(Node));\n\n node->data = data;\n\n node->left = NULL;\n\n node->right = NULL;\n\n return node;\n\n}\n\n\n\n// Function to find the maximum height of the binary tree\n\n", + "func": "int func0(Node* node) {\n if (node == NULL) {\n return 0;\n } else {\n int left_height = func0(node->left);\n int right_height = func0(node->right);\n if (left_height > right_height) {\n return left_height + 1;\n } else {\n return right_height + 1;\n }\n }\n}", + "test": "int main() {\n\n // Constructing trees as per the given Python code\n\n Node* root = newNode(1);\n\n root->left = newNode(2);\n\n root->right = newNode(3);\n\n root->left->left = newNode(4);\n\n root->left->right = newNode(5);\n\n \n\n Node* root1 = newNode(1);\n\n root1->left = newNode(2);\n\n root1->right = newNode(3);\n\n root1->left->left = newNode(4);\n\n root1->right->left = newNode(5);\n\n root1->right->right = newNode(6);\n\n root1->right->right->right = newNode(7);\n\n root1->right->right->right->right = newNode(8);\n\n \n\n Node* root2 = newNode(1);\n\n root2->left = newNode(2);\n\n root2->right = newNode(3);\n\n root2->left->left = newNode(4);\n\n root2->left->right = newNode(5);\n\n root2->left->left->left = newNode(6);\n\n root2->left->left->right = newNode(7);\n\n \n\n // Testing the max_height function\n\n assert(func0(root) == 3);\n\n assert(func0(root1) == 5);\n\n assert(func0(root2) == 4);\n\n \n\n printf(\"All tests passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nxor %eax,%eax\ntest %rdi,%rdi\nje 1aa0 \npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov 0x8(%rdi),%rax\nmov 0x10(%rdi),%r8\ntest %rax,%rax\nje 1a50 \nmov 0x8(%rax),%rdx\nmov 0x10(%rax),%r10\ntest %rdx,%rdx\nje 1ae0 \nmov 0x8(%rdx),%rax\nmov 0x10(%rdx),%r11\ntest %rax,%rax\nje 1b20 \nmov 0x8(%rax),%rsi\nmov 0x10(%rax),%rbx\ntest %rsi,%rsi\nje 1aa8 \nmov 0x8(%rsi),%rdi\ntest %rdi,%rdi\nje 1d20 \ncallq 1450 \nmov 0x10(%rsi),%rdi\nmov %eax,%ebp\nxor %eax,%eax\ntest %rdi,%rdi\nje 154d \ncallq 1450 \nlea 0x1(%rbp),%edx\nlea 0x1(%rax),%r9d\ncmp %ebp,%eax\ncmovl %edx,%r9d\nxor %eax,%eax\ntest %rbx,%rbx\nje 1592 \nmov 0x8(%rbx),%rdi\ntest %rdi,%rdi\nje 1d00 \ncallq 1450 \nmov 0x10(%rbx),%rdi\nxor %edx,%edx\nmov %eax,%esi\ntest %rdi,%rdi\nje 1587 \ncallq 1450 \nmov %eax,%edx\nlea 0x1(%rsi),%ecx\nlea 0x1(%rdx),%eax\ncmp %esi,%edx\ncmovl %ecx,%eax\nlea 0x1(%r9),%edx\nlea 0x1(%rax),%esi\ncmp %r9d,%eax\ncmovl %edx,%esi\nxor %eax,%eax\ntest %r11,%r11\nje 162f \nmov 0x8(%r11),%r9\nmov 0x10(%r11),%r11\ntest %r9,%r9\nje 1ba0 \nmov 0x8(%r9),%rdi\ntest %rdi,%rdi\nje 1ce0 \ncallq 1450 \nmov 0x10(%r9),%rdi\nmov %eax,%ebx\nxor %eax,%eax\ntest %rdi,%rdi\nje 15df \ncallq 1450 \nlea 0x1(%rbx),%edx\nlea 0x1(%rax),%r9d\ncmp %ebx,%eax\ncmovl %edx,%r9d\nxor %edx,%edx\ntest %r11,%r11\nje 1622 \nmov 0x8(%r11),%rdi\ntest %rdi,%rdi\nje 1cc0 \ncallq 1450 \nmov 0x10(%r11),%rdi\nmov %eax,%ebx\nxor %eax,%eax\ntest %rdi,%rdi\nje 1617 \ncallq 1450 \nlea 0x1(%rbx),%ecx\nlea 0x1(%rax),%edx\ncmp %ebx,%eax\ncmovl %ecx,%edx\nlea 0x1(%r9),%ecx\nlea 0x1(%rdx),%eax\ncmp %r9d,%edx\ncmovl %ecx,%eax\nlea 0x1(%rsi),%edx\nlea 0x1(%rax),%r9d\ncmp %esi,%eax\ncmovl %edx,%r9d\nxor %eax,%eax\ntest %r10,%r10\nje 177c \nmov 0x8(%r10),%rax\nmov 0x10(%r10),%r10\ntest %rax,%rax\nje 1b02 \nmov 0x8(%rax),%rsi\nmov 0x10(%rax),%rbx\ntest %rsi,%rsi\nje 1b80 \nmov 0x8(%rsi),%rdi\ntest %rdi,%rdi\nje 1ca0 \ncallq 1450 \nmov 0x10(%rsi),%rdi\nmov %eax,%ebp\nxor %eax,%eax\ntest %rdi,%rdi\nje 168d \ncallq 1450 \nlea 0x1(%rbp),%edx\nlea 0x1(%rax),%r11d\ncmp %ebp,%eax\ncmovl %edx,%r11d\nxor %eax,%eax\ntest %rbx,%rbx\nje 16d2 \nmov 0x8(%rbx),%rdi\ntest %rdi,%rdi\nje 1c80 \ncallq 1450 \nmov 0x10(%rbx),%rdi\nxor %edx,%edx\nmov %eax,%esi\ntest %rdi,%rdi\nje 16c7 \ncallq 1450 \nmov %eax,%edx\nlea 0x1(%rsi),%ecx\nlea 0x1(%rdx),%eax\ncmp %esi,%edx\ncmovl %ecx,%eax\nlea 0x1(%r11),%edx\nlea 0x1(%rax),%esi\ncmp %r11d,%eax\ncmovl %edx,%esi\nxor %edx,%edx\ntest %r10,%r10\nje 1771 \nmov 0x8(%r10),%rbx\nmov 0x10(%r10),%r11\ntest %rbx,%rbx\nje 1b60 \nmov 0x8(%rbx),%rdi\ntest %rdi,%rdi\nje 1c60 \ncallq 1450 \nmov 0x10(%rbx),%rdi\nmov %eax,%ebp\nxor %eax,%eax\ntest %rdi,%rdi\nje 171f \ncallq 1450 \nlea 0x1(%rbp),%edx\nlea 0x1(%rax),%r10d\ncmp %ebp,%eax\ncmovl %edx,%r10d\nxor %eax,%eax\ntest %r11,%r11\nje 1764 \nmov 0x8(%r11),%rdi\ntest %rdi,%rdi\nje 1c40 \ncallq 1450 \nxor %edx,%edx\nmov 0x10(%r11),%rdi\nmov %eax,%ebx\ntest %rdi,%rdi\nje 1759 \ncallq 1450 \nmov %eax,%edx\nlea 0x1(%rbx),%ecx\nlea 0x1(%rdx),%eax\ncmp %ebx,%edx\ncmovl %ecx,%eax\nlea 0x1(%r10),%ecx\nlea 0x1(%rax),%edx\ncmp %r10d,%eax\ncmovl %ecx,%edx\nlea 0x1(%rsi),%ecx\nlea 0x1(%rdx),%eax\ncmp %esi,%edx\ncmovl %ecx,%eax\nlea 0x1(%r9),%edx\nlea 0x1(%rax),%esi\ncmp %r9d,%eax\ncmovl %edx,%esi\nxor %edx,%edx\ntest %r8,%r8\nje 1a38 \nmov 0x8(%r8),%rax\nmov 0x10(%r8),%r9\ntest %rax,%rax\nje 1a6d \nmov 0x8(%rax),%rdx\nmov 0x10(%rax),%r11\ntest %rdx,%rdx\nje 1b40 \nmov 0x8(%rdx),%r8\nmov 0x10(%rdx),%rbx\ntest %r8,%r8\nje 1ac0 \nmov 0x8(%r8),%rdi\ntest %rdi,%rdi\nje 1c20 \ncallq 1450 \nmov 0x10(%r8),%rdi\nmov %eax,%r10d\nxor %eax,%eax\ntest %rdi,%rdi\nje 17ec \ncallq 1450 \nlea 0x1(%r10),%edx\nlea 0x1(%rax),%r8d\ncmp %r10d,%eax\ncmovl %edx,%r8d\nxor %eax,%eax\ntest %rbx,%rbx\nje 1836 \nmov 0x8(%rbx),%rdi\ntest %rdi,%rdi\nje 1e00 \ncallq 1450 \nmov 0x10(%rbx),%rdi\nxor %edx,%edx\nmov %eax,%r10d\ntest %rdi,%rdi\nje 1829 \ncallq 1450 \nmov %eax,%edx\nlea 0x1(%r10),%ecx\nlea 0x1(%rdx),%eax\ncmp %r10d,%edx\ncmovl %ecx,%eax\nlea 0x1(%r8),%edx\nlea 0x1(%rax),%r10d\ncmp %r8d,%eax\ncmovl %edx,%r10d\nxor %eax,%eax\ntest %r11,%r11\nje 18d5 \nmov 0x8(%r11),%r8\nmov 0x10(%r11),%r11\ntest %r8,%r8\nje 1c00 \nmov 0x8(%r8),%rdi\ntest %rdi,%rdi\nje 1de0 \ncallq 1450 \nmov 0x10(%r8),%rdi\nmov %eax,%ebx\nxor %eax,%eax\ntest %rdi,%rdi\nje 1885 \ncallq 1450 \nlea 0x1(%rbx),%edx\nlea 0x1(%rax),%r8d\ncmp %ebx,%eax\ncmovl %edx,%r8d\nxor %edx,%edx\ntest %r11,%r11\nje 18c8 \nmov 0x8(%r11),%rdi\ntest %rdi,%rdi\nje 1dc0 \ncallq 1450 \nmov 0x10(%r11),%rdi\nmov %eax,%ebx\nxor %eax,%eax\ntest %rdi,%rdi\nje 18bd \ncallq 1450 \nlea 0x1(%rbx),%ecx\nlea 0x1(%rax),%edx\ncmp %ebx,%eax\ncmovl %ecx,%edx\nlea 0x1(%r8),%ecx\nlea 0x1(%rdx),%eax\ncmp %r8d,%edx\ncmovl %ecx,%eax\nlea 0x1(%r10),%edx\nlea 0x1(%rax),%r8d\ncmp %r10d,%eax\ncmovl %edx,%r8d\nxor %eax,%eax\ntest %r9,%r9\nje 1a2b \nmov 0x8(%r9),%rax\nmov 0x10(%r9),%r10\ntest %rax,%rax\nje 1a8b \nmov 0x8(%rax),%r9\nmov 0x10(%rax),%rbx\ntest %r9,%r9\nje 1bc0 \nmov 0x8(%r9),%rdi\ntest %rdi,%rdi\nje 1da0 \ncallq 1450 \nmov 0x10(%r9),%rdi\nmov %eax,%ebp\nxor %eax,%eax\ntest %rdi,%rdi\nje 1935 \ncallq 1450 \nlea 0x1(%rbp),%edx\nlea 0x1(%rax),%r11d\ncmp %ebp,%eax\ncmovl %edx,%r11d\nxor %eax,%eax\ntest %rbx,%rbx\nje 197d \nmov 0x8(%rbx),%rdi\ntest %rdi,%rdi\nje 1d80 \ncallq 1450 \nmov 0x10(%rbx),%rdi\nxor %edx,%edx\nmov %eax,%r9d\ntest %rdi,%rdi\nje 1970 \ncallq 1450 \nmov %eax,%edx\nlea 0x1(%r9),%ecx\nlea 0x1(%rdx),%eax\ncmp %r9d,%edx\ncmovl %ecx,%eax\nlea 0x1(%r11),%edx\nlea 0x1(%rax),%r9d\ncmp %r11d,%eax\ncmovl %edx,%r9d\nxor %edx,%edx\ntest %r10,%r10\nje 1a1e \nmov 0x8(%r10),%rbx\nmov 0x10(%r10),%r11\ntest %rbx,%rbx\nje 1be0 \nmov 0x8(%rbx),%rdi\ntest %rdi,%rdi\nje 1d60 \ncallq 1450 \nmov 0x10(%rbx),%rdi\nmov %eax,%ebp\nxor %eax,%eax\ntest %rdi,%rdi\nje 19cc \ncallq 1450 \nlea 0x1(%rbp),%edx\nlea 0x1(%rax),%r10d\ncmp %ebp,%eax\ncmovl %edx,%r10d\nxor %eax,%eax\ntest %r11,%r11\nje 1a11 \nmov 0x8(%r11),%rdi\ntest %rdi,%rdi\nje 1d40 \ncallq 1450 \nxor %edx,%edx\nmov 0x10(%r11),%rdi\nmov %eax,%ebx\ntest %rdi,%rdi\nje 1a06 \ncallq 1450 \nmov %eax,%edx\nlea 0x1(%rbx),%ecx\nlea 0x1(%rdx),%eax\ncmp %ebx,%edx\ncmovl %ecx,%eax\nlea 0x1(%r10),%ecx\nlea 0x1(%rax),%edx\ncmp %r10d,%eax\ncmovl %ecx,%edx\nlea 0x1(%r9),%ecx\nlea 0x1(%rdx),%eax\ncmp %r9d,%edx\ncmovl %ecx,%eax\nlea 0x1(%r8),%ecx\nlea 0x1(%rax),%edx\ncmp %r8d,%eax\ncmovl %ecx,%edx\nlea 0x1(%rsi),%ecx\nlea 0x1(%rdx),%eax\ncmp %esi,%edx\ncmovl %ecx,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nnopw 0x0(%rax,%rax,1)\nmov $0x1,%eax\nxor %esi,%esi\ntest %r8,%r8\nje 1a43 \nmov 0x8(%r8),%rax\nmov 0x10(%r8),%r9\ntest %rax,%rax\njne 17a5 \nmov $0x1,%edx\nxor %r8d,%r8d\ntest %r9,%r9\nje 1a38 \nmov 0x8(%r9),%rax\nmov 0x10(%r9),%r10\ntest %rax,%rax\njne 1900 \nmov $0x1,%eax\nxor %r9d,%r9d\ntest %r10,%r10\njne 1997 \njmp 1a2b \nxchg %ax,%ax\nretq\nnopl 0x0(%rax)\nmov $0x1,%esi\nxor %r9d,%r9d\ntest %rbx,%rbx\njne 1561 \njmpq 159f \nxchg %ax,%ax\nmov $0x1,%r10d\nxor %r8d,%r8d\ntest %rbx,%rbx\njne 1802 \njmpq 1845 \nnopw 0x0(%rax,%rax,1)\nmov $0x1,%esi\nxor %r9d,%r9d\ntest %r10,%r10\nje 1789 \nmov 0x8(%r10),%rax\nmov 0x10(%r10),%r10\ntest %rax,%rax\njne 1658 \nmov $0x1,%eax\nxor %esi,%esi\ntest %r10,%r10\njne 16ea \njmpq 177c \nnopw 0x0(%rax,%rax,1)\nmov $0x1,%r9d\nxor %esi,%esi\ntest %r11,%r11\njne 15aa \njmpq 163c \nnopw %cs:0x0(%rax,%rax,1)\nmov $0x1,%r8d\nxor %r10d,%r10d\ntest %r11,%r11\njne 1850 \njmpq 18e4 \nnopw 0x0(%rax,%rax,1)\nmov $0x1,%edx\nxor %r10d,%r10d\ntest %r11,%r11\njne 1733 \njmpq 1771 \nnopw %cs:0x0(%rax,%rax,1)\nmov $0x1,%esi\nxor %r11d,%r11d\ntest %rbx,%rbx\njne 16a1 \njmpq 16df \nnopw %cs:0x0(%rax,%rax,1)\nmov $0x1,%eax\nxor %r9d,%r9d\ntest %r11,%r11\njne 15f3 \njmpq 162f \nnopw %cs:0x0(%rax,%rax,1)\nmov $0x1,%r9d\nxor %r11d,%r11d\ntest %rbx,%rbx\njne 1949 \njmpq 198c \nnopw 0x0(%rax,%rax,1)\nmov $0x1,%edx\nxor %r10d,%r10d\ntest %r11,%r11\njne 19e0 \njmpq 1a1e \nnopw %cs:0x0(%rax,%rax,1)\nmov $0x1,%eax\nxor %r8d,%r8d\ntest %r11,%r11\njne 1899 \njmpq 18d5 \nnopw %cs:0x0(%rax,%rax,1)\nmov 0x10(%r8),%rdi\nxor %r10d,%r10d\nmov $0x1,%r8d\ntest %rdi,%rdi\njne 17e7 \njmpq 17fb \nnopl 0x0(%rax,%rax,1)\nmov 0x10(%r11),%rdi\nmov $0x1,%eax\nxor %ebx,%ebx\ntest %rdi,%rdi\njne 1752 \njmpq 1764 \nnopl 0x0(%rax)\nmov 0x10(%rbx),%rdi\nmov $0x1,%r10d\nxor %ebp,%ebp\ntest %rdi,%rdi\njne 171a \njmpq 172c \nnopw 0x0(%rax,%rax,1)\nmov 0x10(%rbx),%rdi\nmov $0x1,%eax\nxor %esi,%esi\ntest %rdi,%rdi\njne 16c0 \njmpq 16d2 \nnopl 0x0(%rax)\nmov 0x10(%rsi),%rdi\nmov $0x1,%r11d\nxor %ebp,%ebp\ntest %rdi,%rdi\njne 1688 \njmpq 169a \nnopw 0x0(%rax,%rax,1)\nmov 0x10(%r11),%rdi\nmov $0x1,%edx\nxor %ebx,%ebx\ntest %rdi,%rdi\njne 1612 \njmpq 1622 \nnopl 0x0(%rax)\nmov 0x10(%r9),%rdi\nxor %ebx,%ebx\nmov $0x1,%r9d\ntest %rdi,%rdi\njne 15da \njmpq 15ec \nnopw 0x0(%rax,%rax,1)\nmov 0x10(%rbx),%rdi\nmov $0x1,%eax\nxor %esi,%esi\ntest %rdi,%rdi\njne 1580 \njmpq 1592 \nnopl 0x0(%rax)\nmov 0x10(%rsi),%rdi\nmov $0x1,%r9d\nxor %ebp,%ebp\ntest %rdi,%rdi\njne 1548 \njmpq 155a \nnopw 0x0(%rax,%rax,1)\nmov 0x10(%r11),%rdi\nmov $0x1,%eax\nxor %ebx,%ebx\ntest %rdi,%rdi\njne 19ff \njmpq 1a11 \nnopl 0x0(%rax)\nmov 0x10(%rbx),%rdi\nmov $0x1,%r10d\nxor %ebp,%ebp\ntest %rdi,%rdi\njne 19c7 \njmpq 19d9 \nnopw 0x0(%rax,%rax,1)\nmov 0x10(%rbx),%rdi\nmov $0x1,%eax\nxor %r9d,%r9d\ntest %rdi,%rdi\njne 1969 \njmpq 197d \nnopw 0x0(%rax,%rax,1)\nmov 0x10(%r9),%rdi\nmov $0x1,%r11d\nxor %ebp,%ebp\ntest %rdi,%rdi\njne 1930 \njmpq 1942 \nnopw 0x0(%rax,%rax,1)\nmov 0x10(%r11),%rdi\nmov $0x1,%edx\nxor %ebx,%ebx\ntest %rdi,%rdi\njne 18b8 \njmpq 18c8 \nnopl 0x0(%rax)\nmov 0x10(%r8),%rdi\nxor %ebx,%ebx\nmov $0x1,%r8d\ntest %rdi,%rdi\njne 1880 \njmpq 1892 \nnopw 0x0(%rax,%rax,1)\nmov 0x10(%rbx),%rdi\nmov $0x1,%eax\nxor %r10d,%r10d\ntest %rdi,%rdi\njne 1822 \njmpq 1836 \nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0_part_0:\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 8\nmov rbp, [rdi+8]\ntest rbp, rbp\njz loc_16E8\nmov r12, [rbp+8]\ntest r12, r12\njz loc_1590\nmov r13, [r12+8]\ntest r13, r13\njz loc_1C10\nmov r14, [r13+8]\ntest r14, r14\njz loc_1C50\nmov rdi, [r14+8]\ntest rdi, rdi\njz loc_1AC0\ncall func0_part_0\nmov rdi, [r14+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_143B\nloc_1436:\ncall func0_part_0\nloc_143B:\nmov r13, [r13+10h]\nlea r14d, [rax+1]\ncmp eax, r15d\nlea edx, [r15+1]\ncmovl r14d, edx\nxor eax, eax\ntest r13, r13\njz short loc_1489\nloc_1455:\nmov rdi, [r13+8]\ntest rdi, rdi\njz loc_1DF0\ncall func0_part_0\nmov rdi, [r13+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_147A\nloc_1475:\ncall func0_part_0\nloc_147A:\nlea ecx, [rax+1]\ncmp eax, r15d\nlea edx, [r15+1]\nmov eax, ecx\ncmovl eax, edx\nloc_1489:\nmov r12, [r12+10h]\nlea r13d, [rax+1]\nlea edx, [r14+1]\ncmp eax, r14d\ncmovl r13d, edx\nxor eax, eax\ntest r12, r12\njz loc_1537\nloc_14A8:\nmov r14, [r12+8]\ntest r14, r14\njz loc_1D60\nmov rdi, [r14+8]\ntest rdi, rdi\njz loc_1DA0\ncall func0_part_0\nmov rdi, [r14+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_14DB\nloc_14D6:\ncall func0_part_0\nloc_14DB:\nmov r12, [r12+10h]\nlea edx, [r15+1]\ncmp eax, r15d\nlea r14d, [rax+1]\ncmovl r14d, edx\nxor edx, edx\ntest r12, r12\njz short loc_152A\nloc_14F6:\nmov rdi, [r12+8]\ntest rdi, rdi\njz loc_1DD0\ncall func0_part_0\nmov rdi, [r12+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_151D\nloc_1518:\ncall func0_part_0\nloc_151D:\nlea ecx, [rax+1]\nlea edx, [r15+1]\ncmp eax, r15d\ncmovge edx, ecx\nloc_152A:\nlea ecx, [rdx+1]\nlea eax, [r14+1]\ncmp edx, r14d\ncmovge eax, ecx\nloc_1537:\nlea edx, [r13+1]\nlea r12d, [rax+1]\ncmp eax, r13d\nmov r13, [rbp+10h]\ncmovl r12d, edx\nxor eax, eax\ntest r13, r13\njnz short loc_159D\nloc_1551:\nlea ebp, [rax+1]\ncmp eax, r12d\njge short loc_155E\nloc_1559:\nlea ebp, [r12+1]\nloc_155E:\nmov r12, [rbx+10h]\nxor eax, eax\ntest r12, r12\njnz loc_16FA\nloc_156D:\ncmp eax, ebp\njge loc_19B9\nloc_1575:\nlea eax, [rbp+1]\nloc_1578:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1590:\nmov r13, [rbp+10h]\ntest r13, r13\njz loc_1B50\nloc_159D:\nmov rbp, [r13+8]\ntest rbp, rbp\njz loc_1BA0\nmov r14, [rbp+8]\ntest r14, r14\njz loc_1D00\nmov rdi, [r14+8]\ntest rdi, rdi\njz loc_1B10\ncall func0_part_0\nmov rdi, [r14+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_15DC\nloc_15D7:\ncall func0_part_0\nloc_15DC:\nmov rbp, [rbp+10h]\nlea edx, [r15+1]\ncmp eax, r15d\nlea r14d, [rax+1]\ncmovl r14d, edx\nxor edx, edx\ntest rbp, rbp\njz short loc_1628\nloc_15F6:\nmov rdi, [rbp+8]\ntest rdi, rdi\njz loc_1ED0\ncall func0_part_0\nmov rdi, [rbp+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_161B\nloc_1616:\ncall func0_part_0\nloc_161B:\nlea ecx, [rax+1]\nlea edx, [r15+1]\ncmp eax, r15d\ncmovge edx, ecx\nloc_1628:\nlea eax, [rdx+1]\nlea ecx, [r14+1]\ncmp edx, r14d\nmov r13, [r13+10h]\ncmovge ecx, eax\nxor eax, eax\nmov ebp, ecx\ntest r13, r13\njz loc_16D1\nloc_1646:\nmov r14, [r13+8]\ntest r14, r14\njz loc_1BBF\nloc_1653:\nmov rdi, [r14+8]\ntest rdi, rdi\njz loc_1F10\ncall func0_part_0\nmov rdi, [r14+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_1678\nloc_1673:\ncall func0_part_0\nloc_1678:\nmov r13, [r13+10h]\nlea edx, [r15+1]\ncmp eax, r15d\nlea r14d, [rax+1]\ncmovl r14d, edx\nxor edx, edx\ntest r13, r13\njz short loc_16C4\nloc_1692:\nmov rdi, [r13+8]\ntest rdi, rdi\njz loc_1EF0\ncall func0_part_0\nmov rdi, [r13+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_16B7\nloc_16B2:\ncall func0_part_0\nloc_16B7:\nlea ecx, [rax+1]\nlea edx, [r15+1]\ncmp eax, r15d\ncmovge edx, ecx\nloc_16C4:\nlea ecx, [rdx+1]\nlea eax, [r14+1]\ncmp edx, r14d\ncmovge eax, ecx\nloc_16D1:\ncmp eax, ebp\njge loc_1B90\nloc_16D9:\nlea eax, [rbp+1]\njmp loc_1551\nloc_16E8:\nmov r12, [rdi+10h]\nmov eax, 1\ntest r12, r12\njz loc_1578\nloc_16FA:\nmov rbx, [r12+8]\ntest rbx, rbx\njz loc_19D0\nmov r13, [rbx+8]\ntest r13, r13\njz loc_1BE0\nmov r14, [r13+8]\ntest r14, r14\njz loc_1CA0\nmov rdi, [r14+8]\ntest rdi, rdi\njz loc_1A28\ncall func0_part_0\nmov rdi, [r14+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_1747\nloc_1742:\ncall func0_part_0\nloc_1747:\nmov r13, [r13+10h]\nlea r14d, [rax+1]\ncmp eax, r15d\nlea edx, [r15+1]\ncmovl r14d, edx\nxor eax, eax\ntest r13, r13\njz short loc_1795\nloc_1761:\nmov rdi, [r13+8]\ntest rdi, rdi\njz loc_1D80\ncall func0_part_0\nmov rdi, [r13+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_1786\nloc_1781:\ncall func0_part_0\nloc_1786:\nlea ecx, [rax+1]\ncmp eax, r15d\nlea edx, [r15+1]\nmov eax, ecx\ncmovl eax, edx\nloc_1795:\nmov rbx, [rbx+10h]\nlea edx, [r14+1]\nlea r13d, [rax+1]\ncmp eax, r14d\ncmovl r13d, edx\nxor edx, edx\ntest rbx, rbx\njz loc_1840\nloc_17B3:\nmov r14, [rbx+8]\ntest r14, r14\njz loc_1CE0\nmov rdi, [r14+8]\ntest rdi, rdi\njz loc_1E70\ncall func0_part_0\nmov rdi, [r14+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_17E5\nloc_17E0:\ncall func0_part_0\nloc_17E5:\nmov rbx, [rbx+10h]\nlea r14d, [rax+1]\ncmp eax, r15d\nlea edx, [r15+1]\ncmovl r14d, edx\nxor eax, eax\ntest rbx, rbx\njz short loc_1833\nloc_17FF:\nmov rdi, [rbx+8]\ntest rdi, rdi\njz loc_1E50\ncall func0_part_0\nmov rdi, [rbx+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_1824\nloc_181F:\ncall func0_part_0\nloc_1824:\nlea ecx, [rax+1]\ncmp eax, r15d\nlea edx, [r15+1]\nmov eax, ecx\ncmovl eax, edx\nloc_1833:\nlea ecx, [rax+1]\nlea edx, [r14+1]\ncmp eax, r14d\ncmovge edx, ecx\nloc_1840:\nlea ecx, [r13+1]\nlea eax, [rdx+1]\ncmp edx, r13d\nmov r13, [r12+10h]\ncmovge ecx, eax\nxor eax, eax\nmov ebx, ecx\ntest r13, r13\njz loc_19A6\nloc_185F:\nmov r12, [r13+8]\ntest r12, r12\njz loc_19F0\nloc_186C:\nmov r14, [r12+8]\ntest r14, r14\njz loc_1D30\nmov rdi, [r14+8]\ntest rdi, rdi\njz loc_1A80\ncall func0_part_0\nmov rdi, [r14+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_189F\nloc_189A:\ncall func0_part_0\nloc_189F:\nmov r12, [r12+10h]\nlea edx, [r15+1]\ncmp eax, r15d\nlea r14d, [rax+1]\ncmovl r14d, edx\nxor edx, edx\ntest r12, r12\njz short loc_18EE\nloc_18BA:\nmov rdi, [r12+8]\ntest rdi, rdi\njz loc_1E30\ncall func0_part_0\nmov rdi, [r12+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_18E1\nloc_18DC:\ncall func0_part_0\nloc_18E1:\nlea ecx, [rax+1]\nlea edx, [r15+1]\ncmp eax, r15d\ncmovge edx, ecx\nloc_18EE:\nlea eax, [rdx+1]\nlea ecx, [r14+1]\ncmp edx, r14d\nmov r13, [r13+10h]\ncmovge ecx, eax\nxor eax, eax\nmov r12d, ecx\ntest r13, r13\njz loc_1998\nloc_190D:\nmov r14, [r13+8]\ntest r14, r14\njz loc_1A0B\nloc_191A:\nmov rdi, [r14+8]\ntest rdi, rdi\njz loc_1EA0\ncall func0_part_0\nmov rdi, [r14+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_193F\nloc_193A:\ncall func0_part_0\nloc_193F:\nmov r13, [r13+10h]\nlea edx, [r15+1]\ncmp eax, r15d\nlea r14d, [rax+1]\ncmovl r14d, edx\nxor edx, edx\ntest r13, r13\njz short loc_198B\nloc_1959:\nmov rdi, [r13+8]\ntest rdi, rdi\njz loc_1E10\ncall func0_part_0\nmov rdi, [r13+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_197E\nloc_1979:\ncall func0_part_0\nloc_197E:\nlea ecx, [rax+1]\nlea edx, [r15+1]\ncmp eax, r15d\ncmovge edx, ecx\nloc_198B:\nlea ecx, [rdx+1]\nlea eax, [r14+1]\ncmp edx, r14d\ncmovge eax, ecx\nloc_1998:\ncmp eax, r12d\njge loc_1B80\nloc_19A1:\nlea eax, [r12+1]\nloc_19A6:\ncmp eax, ebx\njge loc_1B70\nloc_19AE:\nlea eax, [rbx+1]\ncmp eax, ebp\njl loc_1575\nloc_19B9:\nadd rsp, 8\nadd eax, 1\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_19D0:\nmov r13, [r12+10h]\nmov eax, 1\ntest r13, r13\njz loc_156D\nmov r12, [r13+8]\ntest r12, r12\njnz loc_186C\nloc_19F0:\nmov r13, [r13+10h]\nmov eax, 1\ntest r13, r13\njz short loc_19A6\nmov r14, [r13+8]\ntest r14, r14\njnz loc_191A\nloc_1A0B:\nmov r13, [r13+10h]\nmov eax, 1\ntest r13, r13\njnz loc_1959\njmp loc_1998\nloc_1A28:\nmov rdi, [r14+10h]\nxor r15d, r15d\ntest rdi, rdi\njnz loc_1742\nmov r13, [r13+10h]\nmov r14d, 1\ntest r13, r13\njnz loc_1761\nmov rbx, [rbx+10h]\nmov r13d, 2\ntest rbx, rbx\njnz loc_17B3\nmov r13, [r12+10h]\nmov ebx, 3\ntest r13, r13\njnz loc_185F\njmp loc_19AE\nloc_1A80:\nmov rdi, [r14+10h]\nxor r15d, r15d\ntest rdi, rdi\njnz loc_189A\nmov r12, [r12+10h]\nmov r14d, 1\ntest r12, r12\njnz loc_18BA\nmov r13, [r13+10h]\nmov r12d, 2\ntest r13, r13\njnz loc_190D\njmp loc_19A1\nloc_1AC0:\nmov rdi, [r14+10h]\nxor r15d, r15d\ntest rdi, rdi\njnz loc_1436\nmov r13, [r13+10h]\nmov r14d, 1\ntest r13, r13\njnz loc_1455\nmov r12, [r12+10h]\nmov r13d, 2\ntest r12, r12\njnz loc_14A8\nmov r13, [rbp+10h]\nmov r12d, 3\ntest r13, r13\njnz loc_159D\njmp loc_1559\nloc_1B10:\nmov rdi, [r14+10h]\nxor r15d, r15d\ntest rdi, rdi\njnz loc_15D7\nmov rbp, [rbp+10h]\nmov r14d, 1\ntest rbp, rbp\njnz loc_15F6\nmov r13, [r13+10h]\nmov ebp, 2\ntest r13, r13\njnz loc_1646\njmp loc_16D9\nloc_1B50:\nmov r12, [rdi+10h]\nmov eax, 2\nmov ebp, 1\ntest r12, r12\njnz loc_16FA\njmp loc_1578\nloc_1B70:\nadd eax, 1\njmp loc_156D\nloc_1B80:\nadd eax, 1\njmp loc_19A6\nloc_1B90:\nadd eax, 1\njmp loc_1551\nloc_1BA0:\nmov r13, [r13+10h]\nmov eax, 1\ntest r13, r13\njz loc_1551\nmov r14, [r13+8]\ntest r14, r14\njnz loc_1653\nloc_1BBF:\nmov r13, [r13+10h]\nmov eax, 1\ntest r13, r13\njnz loc_1692\njmp loc_16D1\nloc_1BE0:\nmov rbx, [rbx+10h]\ntest rbx, rbx\njnz loc_17B3\nmov r13, [r12+10h]\nmov eax, 2\ntest r13, r13\njz loc_156D\nmov ebx, 1\njmp loc_185F\nloc_1C10:\nmov r12, [r12+10h]\ntest r12, r12\njnz loc_14A8\nmov r13, [rbp+10h]\nmov r12d, 1\ntest r13, r13\njnz loc_159D\nmov r12, [rdi+10h]\nmov ebp, 2\ntest r12, r12\njnz loc_16FA\njmp loc_1575\nloc_1C50:\nmov r13, [r13+10h]\ntest r13, r13\njnz loc_1455\nmov r12, [r12+10h]\nmov r13d, 1\ntest r12, r12\njnz loc_14A8\nmov r13, [rbp+10h]\nmov r12d, 2\ntest r13, r13\njnz loc_159D\nmov r12, [rdi+10h]\nmov ebp, 3\ntest r12, r12\njnz loc_16FA\njmp loc_1575\nloc_1CA0:\nmov r13, [r13+10h]\ntest r13, r13\njnz loc_1761\nmov rbx, [rbx+10h]\nmov r13d, 1\ntest rbx, rbx\njnz loc_17B3\nmov r13, [r12+10h]\nmov ebx, 2\ntest r13, r13\njnz loc_185F\njmp loc_19AE\nloc_1CE0:\nmov rbx, [rbx+10h]\nmov edx, 1\ntest rbx, rbx\njnz loc_17FF\njmp loc_1840\nloc_1D00:\nmov rbp, [rbp+10h]\ntest rbp, rbp\njnz loc_15F6\nmov r13, [r13+10h]\nmov eax, 2\ntest r13, r13\njz loc_1551\nmov ebp, 1\njmp loc_1646\nloc_1D30:\nmov r12, [r12+10h]\ntest r12, r12\njnz loc_18BA\nmov r13, [r13+10h]\nmov eax, 2\ntest r13, r13\njz loc_19A6\nmov r12d, 1\njmp loc_190D\nloc_1D60:\nmov r12, [r12+10h]\nmov eax, 1\ntest r12, r12\njnz loc_14F6\njmp loc_1537\nloc_1D80:\nmov rdi, [r13+10h]\nmov eax, 1\nxor r15d, r15d\ntest rdi, rdi\njnz loc_1781\njmp loc_1795\nloc_1DA0:\nmov rdi, [r14+10h]\nxor r15d, r15d\ntest rdi, rdi\njnz loc_14D6\nmov r12, [r12+10h]\nmov eax, 2\ntest r12, r12\njz loc_1537\nmov r14d, 1\njmp loc_14F6\nloc_1DD0:\nmov rdi, [r12+10h]\nmov edx, 1\nxor r15d, r15d\ntest rdi, rdi\njnz loc_1518\njmp loc_152A\nloc_1DF0:\nmov rdi, [r13+10h]\nmov eax, 1\nxor r15d, r15d\ntest rdi, rdi\njnz loc_1475\njmp loc_1489\nloc_1E10:\nmov rdi, [r13+10h]\nmov edx, 1\nxor r15d, r15d\ntest rdi, rdi\njnz loc_1979\njmp loc_198B\nloc_1E30:\nmov rdi, [r12+10h]\nmov edx, 1\nxor r15d, r15d\ntest rdi, rdi\njnz loc_18DC\njmp loc_18EE\nloc_1E50:\nmov rdi, [rbx+10h]\nmov eax, 1\nxor r15d, r15d\ntest rdi, rdi\njnz loc_181F\njmp loc_1833\nloc_1E70:\nmov rdi, [r14+10h]\nxor r15d, r15d\ntest rdi, rdi\njnz loc_17E0\nmov rbx, [rbx+10h]\nmov edx, 2\ntest rbx, rbx\njz loc_1840\nmov r14d, 1\njmp loc_17FF\nloc_1EA0:\nmov rdi, [r14+10h]\nxor r15d, r15d\ntest rdi, rdi\njnz loc_193A\nmov r13, [r13+10h]\nmov eax, 2\ntest r13, r13\njz loc_1998\nmov r14d, 1\njmp loc_1959\nloc_1ED0:\nmov rdi, [rbp+10h]\nmov edx, 1\nxor r15d, r15d\ntest rdi, rdi\njnz loc_1616\njmp loc_1628\nloc_1EF0:\nmov rdi, [r13+10h]\nmov edx, 1\nxor r15d, r15d\ntest rdi, rdi\njnz loc_16B2\njmp loc_16C4\nloc_1F10:\nmov rdi, [r14+10h]\nxor r15d, r15d\ntest rdi, rdi\njnz loc_1673\nmov r13, [r13+10h]\nmov eax, 2\ntest r13, r13\njz loc_16D1\nmov r14d, 1\njmp loc_1692", + "ida_pseudo": "__int64 __fastcall func0_part_0(__int64 a1, __int64 a2, __int64 a3)\n{\n __int64 v4; // rbp\n __int64 v5; // r12\n __int64 v6; // r13\n __int64 v7; // r14\n int v8; // r15d\n int v9; // eax\n __int64 v10; // r13\n int v11; // eax\n int v12; // r15d\n int v13; // eax\n bool v14; // cc\n __int64 v15; // r12\n int v16; // eax\n __int64 v17; // r14\n int v18; // r15d\n int v19; // eax\n __int64 v20; // r12\n __int64 v21; // rdi\n int v22; // eax\n __int64 v23; // rdi\n int v24; // r15d\n int v25; // eax\n __int64 v26; // r13\n int v27; // eax\n __int64 v28; // r12\n int v29; // eax\n __int64 result; // rax\n __int64 v31; // rbp\n __int64 v32; // r14\n __int64 v33; // rdi\n int v34; // eax\n __int64 v35; // rdi\n int v36; // r15d\n int v37; // eax\n __int64 v38; // rbp\n __int64 v39; // rdi\n int v40; // eax\n __int64 v41; // rdi\n int v42; // r15d\n int v43; // eax\n int v44; // ecx\n __int64 v45; // r13\n int v46; // eax\n __int64 v47; // r14\n __int64 v48; // rdi\n int v49; // eax\n __int64 v50; // rdi\n int v51; // r15d\n int v52; // eax\n __int64 v53; // r13\n __int64 v54; // rdi\n int v55; // eax\n __int64 v56; // rdi\n int v57; // r15d\n int v58; // eax\n __int64 v59; // rbx\n __int64 v60; // r13\n __int64 v61; // r14\n __int64 v62; // rdi\n int v63; // eax\n __int64 v64; // rdi\n int v65; // r15d\n int v66; // eax\n __int64 v67; // r13\n int v68; // eax\n __int64 v69; // rdi\n int v70; // eax\n __int64 v71; // rdi\n int v72; // r15d\n int v73; // eax\n __int64 v74; // rbx\n __int64 v75; // r14\n __int64 v76; // rdi\n int v77; // eax\n __int64 v78; // rdi\n int v79; // r15d\n int v80; // eax\n __int64 v81; // rbx\n int v82; // eax\n __int64 v83; // rdi\n int v84; // eax\n __int64 v85; // rdi\n int v86; // r15d\n int v87; // eax\n int v88; // ecx\n __int64 v89; // r13\n int v90; // eax\n __int64 v91; // r12\n __int64 v92; // r14\n __int64 v93; // rdi\n int v94; // eax\n __int64 v95; // rdi\n int v96; // r15d\n int v97; // eax\n __int64 v98; // r12\n __int64 v99; // rdi\n int v100; // eax\n __int64 v101; // rdi\n int v102; // r15d\n int v103; // eax\n int v104; // ecx\n __int64 v105; // r13\n int v106; // eax\n __int64 v107; // r14\n __int64 v108; // rdi\n int v109; // eax\n __int64 v110; // rdi\n int v111; // r15d\n int v112; // eax\n __int64 v113; // r13\n __int64 v114; // rdi\n int v115; // eax\n __int64 v116; // rdi\n int v117; // r15d\n int v118; // eax\n\n v4 = *(_QWORD *)(a1 + 8);\n if ( v4 )\n {\n v5 = *(_QWORD *)(v4 + 8);\n if ( v5 )\n {\n v6 = *(_QWORD *)(v5 + 8);\n if ( !v6 )\n {\n v15 = *(_QWORD *)(v5 + 16);\n if ( !v15 )\n {\n v26 = *(_QWORD *)(v4 + 16);\n LODWORD(v5) = 1;\n if ( !v26 )\n {\n v28 = *(_QWORD *)(a1 + 16);\n LODWORD(v4) = 2;\n if ( !v28 )\n return (unsigned int)(v4 + 1);\n goto LABEL_76;\n }\n goto LABEL_43;\n }\n goto LABEL_19;\n }\n v7 = *(_QWORD *)(v6 + 8);\n if ( !v7 )\n {\n v10 = *(_QWORD *)(v6 + 16);\n if ( !v10 )\n {\n v15 = *(_QWORD *)(v5 + 16);\n LODWORD(v6) = 1;\n if ( !v15 )\n {\n v26 = *(_QWORD *)(v4 + 16);\n LODWORD(v5) = 2;\n if ( !v26 )\n {\n v28 = *(_QWORD *)(a1 + 16);\n LODWORD(v4) = 3;\n if ( !v28 )\n return (unsigned int)(v4 + 1);\n goto LABEL_76;\n }\n goto LABEL_43;\n }\n goto LABEL_19;\n }\n goto LABEL_11;\n }\n if ( *(_QWORD *)(v7 + 8) )\n {\n v8 = ((__int64 (*)(void))func0_part_0)();\n v9 = 0;\n if ( !*(_QWORD *)(v7 + 16) )\n goto LABEL_8;\n }\n else\n {\n v8 = 0;\n if ( !*(_QWORD *)(v7 + 16) )\n {\n v10 = *(_QWORD *)(v6 + 16);\n LODWORD(v7) = 1;\n if ( !v10 )\n {\n v15 = *(_QWORD *)(v5 + 16);\n LODWORD(v6) = 2;\n if ( !v15 )\n {\n v26 = *(_QWORD *)(v4 + 16);\n LODWORD(v5) = 3;\n if ( !v26 )\n {\nLABEL_37:\n LODWORD(v4) = v5 + 1;\nLABEL_38:\n v28 = *(_QWORD *)(a1 + 16);\n v29 = 0;\n if ( !v28 )\n goto LABEL_39;\nLABEL_76:\n v59 = *(_QWORD *)(v28 + 8);\n if ( !v59 )\n {\n v89 = *(_QWORD *)(v28 + 16);\n v29 = 1;\n if ( !v89 )\n goto LABEL_39;\n v91 = *(_QWORD *)(v89 + 8);\n if ( v91 )\n {\nLABEL_111:\n v92 = *(_QWORD *)(v91 + 8);\n if ( !v92 )\n {\n v98 = *(_QWORD *)(v91 + 16);\n if ( !v98 )\n {\n v105 = *(_QWORD *)(v89 + 16);\n v90 = 2;\n if ( !v105 )\n goto LABEL_142;\n LODWORD(v91) = 1;\n goto LABEL_126;\n }\n goto LABEL_118;\n }\n v93 = *(_QWORD *)(v92 + 8);\n if ( v93 )\n {\n v94 = func0_part_0(v93, a2, a3);\n v95 = *(_QWORD *)(v92 + 16);\n v96 = v94;\n v97 = 0;\n if ( !v95 )\n goto LABEL_115;\n }\n else\n {\n v95 = *(_QWORD *)(v92 + 16);\n v96 = 0;\n if ( !v95 )\n {\n v98 = *(_QWORD *)(v91 + 16);\n LODWORD(v92) = 1;\n if ( !v98 )\n {\n v105 = *(_QWORD *)(v89 + 16);\n LODWORD(v91) = 2;\n if ( !v105 )\n {\nLABEL_141:\n v90 = v91 + 1;\nLABEL_142:\n if ( v90 < (int)v59 )\n goto LABEL_143;\n v29 = v90 + 1;\nLABEL_39:\n if ( v29 < (int)v4 )\n return (unsigned int)(v4 + 1);\n return (unsigned int)(v29 + 1);\n }\n goto LABEL_126;\n }\n goto LABEL_118;\n }\n }\n v97 = func0_part_0(v95, a2, a3);\nLABEL_115:\n v98 = *(_QWORD *)(v91 + 16);\n LODWORD(v92) = v97 + 1;\n if ( v97 < v96 )\n LODWORD(v92) = v96 + 1;\n a3 = 0LL;\n if ( !v98 )\n {\nLABEL_123:\n v104 = v92 + 1;\n v105 = *(_QWORD *)(v89 + 16);\n if ( (int)a3 >= (int)v92 )\n v104 = a3 + 1;\n v106 = 0;\n LODWORD(v91) = v104;\n if ( !v105 )\n {\nLABEL_140:\n if ( v106 >= (int)v91 )\n {\n v90 = v106 + 1;\n goto LABEL_142;\n }\n goto LABEL_141;\n }\nLABEL_126:\n v107 = *(_QWORD *)(v105 + 8);\n if ( v107 )\n goto LABEL_127;\n goto LABEL_149;\n }\nLABEL_118:\n v99 = *(_QWORD *)(v98 + 8);\n if ( v99 )\n {\n v100 = func0_part_0(v99, a2, a3);\n v101 = *(_QWORD *)(v98 + 16);\n v102 = v100;\n v103 = 0;\n if ( !v101 )\n goto LABEL_121;\n }\n else\n {\n v101 = *(_QWORD *)(v98 + 16);\n a3 = 1LL;\n v102 = 0;\n if ( !v101 )\n goto LABEL_123;\n }\n v103 = func0_part_0(v101, a2, a3);\nLABEL_121:\n a3 = (unsigned int)(v102 + 1);\n if ( v103 >= v102 )\n a3 = (unsigned int)(v103 + 1);\n goto LABEL_123;\n }\nLABEL_147:\n v105 = *(_QWORD *)(v89 + 16);\n v90 = 1;\n if ( !v105 )\n goto LABEL_142;\n v107 = *(_QWORD *)(v105 + 8);\n if ( v107 )\n {\nLABEL_127:\n v108 = *(_QWORD *)(v107 + 8);\n if ( v108 )\n {\n v109 = func0_part_0(v108, a2, a3);\n v110 = *(_QWORD *)(v107 + 16);\n v111 = v109;\n v112 = 0;\n if ( !v110 )\n goto LABEL_130;\n }\n else\n {\n v110 = *(_QWORD *)(v107 + 16);\n v111 = 0;\n if ( !v110 )\n {\n v113 = *(_QWORD *)(v105 + 16);\n v106 = 2;\n if ( !v113 )\n goto LABEL_140;\n LODWORD(v107) = 1;\n goto LABEL_133;\n }\n }\n v112 = func0_part_0(v110, a2, a3);\nLABEL_130:\n v113 = *(_QWORD *)(v105 + 16);\n LODWORD(v107) = v112 + 1;\n if ( v112 < v111 )\n LODWORD(v107) = v111 + 1;\n a3 = 0LL;\n if ( !v113 )\n goto LABEL_138;\nLABEL_133:\n v114 = *(_QWORD *)(v113 + 8);\n if ( v114 )\n {\n v115 = func0_part_0(v114, a2, a3);\n v116 = *(_QWORD *)(v113 + 16);\n v117 = v115;\n v118 = 0;\n if ( !v116 )\n goto LABEL_136;\n }\n else\n {\n v116 = *(_QWORD *)(v113 + 16);\n a3 = 1LL;\n v117 = 0;\n if ( !v116 )\n {\nLABEL_138:\n v106 = v107 + 1;\n if ( (int)a3 >= (int)v107 )\n v106 = a3 + 1;\n goto LABEL_140;\n }\n }\n v118 = func0_part_0(v116, a2, a3);\nLABEL_136:\n LODWORD(a3) = v117 + 1;\n if ( v118 >= v117 )\n LODWORD(a3) = v118 + 1;\n goto LABEL_138;\n }\nLABEL_149:\n v113 = *(_QWORD *)(v105 + 16);\n v106 = 1;\n if ( !v113 )\n goto LABEL_140;\n goto LABEL_133;\n }\n v60 = *(_QWORD *)(v59 + 8);\n if ( !v60 )\n {\n v74 = *(_QWORD *)(v59 + 16);\n if ( !v74 )\n {\n v89 = *(_QWORD *)(v28 + 16);\n v29 = 2;\n if ( !v89 )\n goto LABEL_39;\n LODWORD(v59) = 1;\n goto LABEL_110;\n }\n goto LABEL_93;\n }\n v61 = *(_QWORD *)(v60 + 8);\n if ( v61 )\n {\n v62 = *(_QWORD *)(v61 + 8);\n if ( v62 )\n {\n v63 = func0_part_0(v62, a2, a3);\n v64 = *(_QWORD *)(v61 + 16);\n v65 = v63;\n v66 = 0;\n if ( !v64 )\n goto LABEL_82;\n goto LABEL_81;\n }\n v64 = *(_QWORD *)(v61 + 16);\n v65 = 0;\n if ( v64 )\n {\nLABEL_81:\n v66 = func0_part_0(v64, a2, a3);\nLABEL_82:\n v67 = *(_QWORD *)(v60 + 16);\n LODWORD(v61) = v66 + 1;\n a3 = (unsigned int)(v65 + 1);\n if ( v66 < v65 )\n LODWORD(v61) = v65 + 1;\n v68 = 0;\n if ( !v67 )\n {\nLABEL_90:\n v74 = *(_QWORD *)(v59 + 16);\n LODWORD(v60) = v68 + 1;\n if ( v68 < (int)v61 )\n LODWORD(v60) = v61 + 1;\n a3 = 0LL;\n if ( !v74 )\n {\nLABEL_107:\n v88 = v60 + 1;\n v14 = (int)a3 < (int)v60;\n v89 = *(_QWORD *)(v28 + 16);\n if ( !v14 )\n v88 = a3 + 1;\n v90 = 0;\n LODWORD(v59) = v88;\n if ( !v89 )\n goto LABEL_142;\nLABEL_110:\n v91 = *(_QWORD *)(v89 + 8);\n if ( v91 )\n goto LABEL_111;\n goto LABEL_147;\n }\nLABEL_93:\n v75 = *(_QWORD *)(v74 + 8);\n if ( !v75 )\n {\n v81 = *(_QWORD *)(v74 + 16);\n a3 = 1LL;\n if ( !v81 )\n goto LABEL_107;\n goto LABEL_100;\n }\n v76 = *(_QWORD *)(v75 + 8);\n if ( v76 )\n {\n v77 = func0_part_0(v76, a2, a3);\n v78 = *(_QWORD *)(v75 + 16);\n v79 = v77;\n v80 = 0;\n if ( !v78 )\n goto LABEL_97;\n }\n else\n {\n v78 = *(_QWORD *)(v75 + 16);\n v79 = 0;\n if ( !v78 )\n {\n v81 = *(_QWORD *)(v74 + 16);\n a3 = 2LL;\n if ( !v81 )\n goto LABEL_107;\n LODWORD(v75) = 1;\n goto LABEL_100;\n }\n }\n v80 = func0_part_0(v78, a2, a3);\nLABEL_97:\n v81 = *(_QWORD *)(v74 + 16);\n LODWORD(v75) = v80 + 1;\n a3 = (unsigned int)(v79 + 1);\n if ( v80 < v79 )\n LODWORD(v75) = v79 + 1;\n v82 = 0;\n if ( !v81 )\n goto LABEL_105;\nLABEL_100:\n v83 = *(_QWORD *)(v81 + 8);\n if ( v83 )\n {\n v84 = func0_part_0(v83, a2, a3);\n v85 = *(_QWORD *)(v81 + 16);\n v86 = v84;\n v87 = 0;\n if ( !v85 )\n goto LABEL_103;\n }\n else\n {\n v85 = *(_QWORD *)(v81 + 16);\n v82 = 1;\n v86 = 0;\n if ( !v85 )\n {\nLABEL_105:\n a3 = (unsigned int)(v75 + 1);\n if ( v82 >= (int)v75 )\n a3 = (unsigned int)(v82 + 1);\n goto LABEL_107;\n }\n }\n v87 = func0_part_0(v85, a2, a3);\nLABEL_103:\n v14 = v87 < v86;\n v82 = v87 + 1;\n if ( v14 )\n v82 = v86 + 1;\n goto LABEL_105;\n }\nLABEL_85:\n v69 = *(_QWORD *)(v67 + 8);\n if ( v69 )\n {\n v70 = func0_part_0(v69, a2, a3);\n v71 = *(_QWORD *)(v67 + 16);\n v72 = v70;\n v73 = 0;\n if ( !v71 )\n goto LABEL_88;\n }\n else\n {\n v71 = *(_QWORD *)(v67 + 16);\n v68 = 1;\n v72 = 0;\n if ( !v71 )\n goto LABEL_90;\n }\n v73 = func0_part_0(v71, a2, a3);\nLABEL_88:\n v14 = v73 < v72;\n v68 = v73 + 1;\n if ( v14 )\n v68 = v72 + 1;\n goto LABEL_90;\n }\n v67 = *(_QWORD *)(v60 + 16);\n LODWORD(v61) = 1;\n if ( v67 )\n goto LABEL_85;\n v74 = *(_QWORD *)(v59 + 16);\n LODWORD(v60) = 2;\n if ( v74 )\n goto LABEL_93;\n v89 = *(_QWORD *)(v28 + 16);\n LODWORD(v59) = 3;\n if ( v89 )\n goto LABEL_110;\n }\n else\n {\n v67 = *(_QWORD *)(v60 + 16);\n if ( v67 )\n goto LABEL_85;\n v74 = *(_QWORD *)(v59 + 16);\n LODWORD(v60) = 1;\n if ( v74 )\n goto LABEL_93;\n v89 = *(_QWORD *)(v28 + 16);\n LODWORD(v59) = 2;\n if ( v89 )\n goto LABEL_110;\n }\nLABEL_143:\n v29 = v59 + 1;\n if ( (int)v59 + 1 < (int)v4 )\n return (unsigned int)(v4 + 1);\n return (unsigned int)(v29 + 1);\n }\n goto LABEL_43;\n }\n goto LABEL_19;\n }\n goto LABEL_11;\n }\n }\n v9 = ((__int64 (*)(void))func0_part_0)();\nLABEL_8:\n v10 = *(_QWORD *)(v6 + 16);\n LODWORD(v7) = v9 + 1;\n if ( v9 < v8 )\n LODWORD(v7) = v8 + 1;\n v11 = 0;\n if ( !v10 )\n {\nLABEL_16:\n v15 = *(_QWORD *)(v5 + 16);\n LODWORD(v6) = v11 + 1;\n a3 = (unsigned int)(v7 + 1);\n if ( v11 < (int)v7 )\n LODWORD(v6) = v7 + 1;\n v16 = 0;\n if ( !v15 )\n {\nLABEL_33:\n a3 = (unsigned int)(v6 + 1);\n LODWORD(v5) = v16 + 1;\n v14 = v16 < (int)v6;\n v26 = *(_QWORD *)(v4 + 16);\n if ( v14 )\n LODWORD(v5) = a3;\n v27 = 0;\n if ( !v26 )\n {\nLABEL_36:\n LODWORD(v4) = v27 + 1;\n if ( v27 >= (int)v5 )\n goto LABEL_38;\n goto LABEL_37;\n }\nLABEL_43:\n v31 = *(_QWORD *)(v26 + 8);\n if ( !v31 )\n {\n v45 = *(_QWORD *)(v26 + 16);\n v27 = 1;\n if ( !v45 )\n goto LABEL_36;\n v47 = *(_QWORD *)(v45 + 8);\n if ( v47 )\n {\nLABEL_60:\n v48 = *(_QWORD *)(v47 + 8);\n if ( v48 )\n {\n v49 = func0_part_0(v48, a2, a3);\n v50 = *(_QWORD *)(v47 + 16);\n v51 = v49;\n v52 = 0;\n if ( !v50 )\n goto LABEL_63;\n }\n else\n {\n v50 = *(_QWORD *)(v47 + 16);\n v51 = 0;\n if ( !v50 )\n {\n v53 = *(_QWORD *)(v45 + 16);\n v46 = 2;\n if ( !v53 )\n goto LABEL_73;\n LODWORD(v47) = 1;\n goto LABEL_66;\n }\n }\n v52 = func0_part_0(v50, a2, a3);\nLABEL_63:\n v53 = *(_QWORD *)(v45 + 16);\n LODWORD(v47) = v52 + 1;\n if ( v52 < v51 )\n LODWORD(v47) = v51 + 1;\n a3 = 0LL;\n if ( !v53 )\n goto LABEL_71;\nLABEL_66:\n v54 = *(_QWORD *)(v53 + 8);\n if ( v54 )\n {\n v55 = func0_part_0(v54, a2, a3);\n v56 = *(_QWORD *)(v53 + 16);\n v57 = v55;\n v58 = 0;\n if ( !v56 )\n goto LABEL_69;\n }\n else\n {\n v56 = *(_QWORD *)(v53 + 16);\n a3 = 1LL;\n v57 = 0;\n if ( !v56 )\n {\nLABEL_71:\n v46 = v47 + 1;\n if ( (int)a3 >= (int)v47 )\n v46 = a3 + 1;\n goto LABEL_73;\n }\n }\n v58 = func0_part_0(v56, a2, a3);\nLABEL_69:\n a3 = (unsigned int)(v57 + 1);\n if ( v58 >= v57 )\n a3 = (unsigned int)(v58 + 1);\n goto LABEL_71;\n }\nLABEL_176:\n v53 = *(_QWORD *)(v45 + 16);\n v46 = 1;\n if ( !v53 )\n goto LABEL_73;\n goto LABEL_66;\n }\n v32 = *(_QWORD *)(v31 + 8);\n if ( !v32 )\n {\n v38 = *(_QWORD *)(v31 + 16);\n if ( !v38 )\n {\n v45 = *(_QWORD *)(v26 + 16);\n v27 = 2;\n if ( !v45 )\n goto LABEL_36;\n LODWORD(v31) = 1;\n goto LABEL_59;\n }\n goto LABEL_51;\n }\n v33 = *(_QWORD *)(v32 + 8);\n if ( v33 )\n {\n v34 = func0_part_0(v33, a2, a3);\n v35 = *(_QWORD *)(v32 + 16);\n v36 = v34;\n v37 = 0;\n if ( !v35 )\n goto LABEL_48;\n }\n else\n {\n v35 = *(_QWORD *)(v32 + 16);\n v36 = 0;\n if ( !v35 )\n {\n v38 = *(_QWORD *)(v31 + 16);\n LODWORD(v32) = 1;\n if ( !v38 )\n {\n v45 = *(_QWORD *)(v26 + 16);\n LODWORD(v31) = 2;\n if ( !v45 )\n goto LABEL_74;\n goto LABEL_59;\n }\n goto LABEL_51;\n }\n }\n v37 = func0_part_0(v35, a2, a3);\nLABEL_48:\n v38 = *(_QWORD *)(v31 + 16);\n LODWORD(v32) = v37 + 1;\n if ( v37 < v36 )\n LODWORD(v32) = v36 + 1;\n a3 = 0LL;\n if ( !v38 )\n {\nLABEL_56:\n v44 = v32 + 1;\n v45 = *(_QWORD *)(v26 + 16);\n if ( (int)a3 >= (int)v32 )\n v44 = a3 + 1;\n v46 = 0;\n LODWORD(v31) = v44;\n if ( !v45 )\n {\nLABEL_73:\n if ( v46 >= (int)v31 )\n {\n v27 = v46 + 1;\n goto LABEL_36;\n }\nLABEL_74:\n v27 = v31 + 1;\n goto LABEL_36;\n }\nLABEL_59:\n v47 = *(_QWORD *)(v45 + 8);\n if ( v47 )\n goto LABEL_60;\n goto LABEL_176;\n }\nLABEL_51:\n v39 = *(_QWORD *)(v38 + 8);\n if ( v39 )\n {\n v40 = func0_part_0(v39, a2, a3);\n v41 = *(_QWORD *)(v38 + 16);\n v42 = v40;\n v43 = 0;\n if ( !v41 )\n goto LABEL_54;\n }\n else\n {\n v41 = *(_QWORD *)(v38 + 16);\n a3 = 1LL;\n v42 = 0;\n if ( !v41 )\n goto LABEL_56;\n }\n v43 = func0_part_0(v41, a2, a3);\nLABEL_54:\n a3 = (unsigned int)(v42 + 1);\n if ( v43 >= v42 )\n a3 = (unsigned int)(v43 + 1);\n goto LABEL_56;\n }\nLABEL_19:\n v17 = *(_QWORD *)(v15 + 8);\n if ( !v17 )\n {\n v20 = *(_QWORD *)(v15 + 16);\n v16 = 1;\n if ( !v20 )\n goto LABEL_33;\n goto LABEL_26;\n }\n if ( *(_QWORD *)(v17 + 8) )\n {\n v18 = ((__int64 (*)(void))func0_part_0)();\n v19 = 0;\n if ( !*(_QWORD *)(v17 + 16) )\n goto LABEL_23;\n }\n else\n {\n v18 = 0;\n if ( !*(_QWORD *)(v17 + 16) )\n {\n v20 = *(_QWORD *)(v15 + 16);\n v16 = 2;\n if ( !v20 )\n goto LABEL_33;\n LODWORD(v17) = 1;\n goto LABEL_26;\n }\n }\n v19 = ((__int64 (*)(void))func0_part_0)();\nLABEL_23:\n v20 = *(_QWORD *)(v15 + 16);\n LODWORD(v17) = v19 + 1;\n if ( v19 < v18 )\n LODWORD(v17) = v18 + 1;\n a3 = 0LL;\n if ( !v20 )\n goto LABEL_31;\nLABEL_26:\n v21 = *(_QWORD *)(v20 + 8);\n if ( v21 )\n {\n v22 = func0_part_0(v21, a2, a3);\n v23 = *(_QWORD *)(v20 + 16);\n v24 = v22;\n v25 = 0;\n if ( !v23 )\n goto LABEL_29;\n }\n else\n {\n v23 = *(_QWORD *)(v20 + 16);\n a3 = 1LL;\n v24 = 0;\n if ( !v23 )\n {\nLABEL_31:\n v16 = v17 + 1;\n if ( (int)a3 >= (int)v17 )\n v16 = a3 + 1;\n goto LABEL_33;\n }\n }\n v25 = func0_part_0(v23, a2, a3);\nLABEL_29:\n LODWORD(a3) = v24 + 1;\n if ( v25 >= v24 )\n LODWORD(a3) = v25 + 1;\n goto LABEL_31;\n }\nLABEL_11:\n if ( *(_QWORD *)(v10 + 8) )\n {\n v12 = ((__int64 (*)(void))func0_part_0)();\n v13 = 0;\n if ( !*(_QWORD *)(v10 + 16) )\n goto LABEL_14;\n }\n else\n {\n v11 = 1;\n v12 = 0;\n if ( !*(_QWORD *)(v10 + 16) )\n goto LABEL_16;\n }\n v13 = ((__int64 (*)(void))func0_part_0)();\nLABEL_14:\n v14 = v13 < v12;\n v11 = v13 + 1;\n if ( v14 )\n v11 = v12 + 1;\n goto LABEL_16;\n }\n v26 = *(_QWORD *)(v4 + 16);\n if ( v26 )\n goto LABEL_43;\n v28 = *(_QWORD *)(a1 + 16);\n result = 2LL;\n LODWORD(v4) = 1;\n if ( v28 )\n goto LABEL_76;\n }\n else\n {\n v28 = *(_QWORD *)(a1 + 16);\n result = 1LL;\n if ( v28 )\n goto LABEL_76;\n }\n return result;\n}", + "ida_strip_asm": "sub_13D0:\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nsub rsp, 8\nmov rbp, [rdi+8]\ntest rbp, rbp\njz loc_16E8\nmov r12, [rbp+8]\ntest r12, r12\njz loc_1590\nmov r13, [r12+8]\ntest r13, r13\njz loc_1C10\nmov r14, [r13+8]\ntest r14, r14\njz loc_1C50\nmov rdi, [r14+8]\ntest rdi, rdi\njz loc_1AC0\ncall sub_13D0\nmov rdi, [r14+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_143B\nloc_1436:\ncall sub_13D0\nloc_143B:\nmov r13, [r13+10h]\nlea r14d, [rax+1]\ncmp eax, r15d\nlea edx, [r15+1]\ncmovl r14d, edx\nxor eax, eax\ntest r13, r13\njz short loc_1489\nloc_1455:\nmov rdi, [r13+8]\ntest rdi, rdi\njz loc_1DF0\ncall sub_13D0\nmov rdi, [r13+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_147A\nloc_1475:\ncall sub_13D0\nloc_147A:\nlea ecx, [rax+1]\ncmp eax, r15d\nlea edx, [r15+1]\nmov eax, ecx\ncmovl eax, edx\nloc_1489:\nmov r12, [r12+10h]\nlea r13d, [rax+1]\nlea edx, [r14+1]\ncmp eax, r14d\ncmovl r13d, edx\nxor eax, eax\ntest r12, r12\njz loc_1537\nloc_14A8:\nmov r14, [r12+8]\ntest r14, r14\njz loc_1D60\nmov rdi, [r14+8]\ntest rdi, rdi\njz loc_1DA0\ncall sub_13D0\nmov rdi, [r14+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_14DB\nloc_14D6:\ncall sub_13D0\nloc_14DB:\nmov r12, [r12+10h]\nlea edx, [r15+1]\ncmp eax, r15d\nlea r14d, [rax+1]\ncmovl r14d, edx\nxor edx, edx\ntest r12, r12\njz short loc_152A\nloc_14F6:\nmov rdi, [r12+8]\ntest rdi, rdi\njz loc_1DD0\ncall sub_13D0\nmov rdi, [r12+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_151D\nloc_1518:\ncall sub_13D0\nloc_151D:\nlea ecx, [rax+1]\nlea edx, [r15+1]\ncmp eax, r15d\ncmovge edx, ecx\nloc_152A:\nlea ecx, [rdx+1]\nlea eax, [r14+1]\ncmp edx, r14d\ncmovge eax, ecx\nloc_1537:\nlea edx, [r13+1]\nlea r12d, [rax+1]\ncmp eax, r13d\nmov r13, [rbp+10h]\ncmovl r12d, edx\nxor eax, eax\ntest r13, r13\njnz short loc_159D\nloc_1551:\nlea ebp, [rax+1]\ncmp eax, r12d\njge short loc_155E\nloc_1559:\nlea ebp, [r12+1]\nloc_155E:\nmov r12, [rbx+10h]\nxor eax, eax\ntest r12, r12\njnz loc_16FA\nloc_156D:\ncmp eax, ebp\njge loc_19B9\nloc_1575:\nlea eax, [rbp+1]\nloc_1578:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1590:\nmov r13, [rbp+10h]\ntest r13, r13\njz loc_1B50\nloc_159D:\nmov rbp, [r13+8]\ntest rbp, rbp\njz loc_1BA0\nmov r14, [rbp+8]\ntest r14, r14\njz loc_1D00\nmov rdi, [r14+8]\ntest rdi, rdi\njz loc_1B10\ncall sub_13D0\nmov rdi, [r14+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_15DC\nloc_15D7:\ncall sub_13D0\nloc_15DC:\nmov rbp, [rbp+10h]\nlea edx, [r15+1]\ncmp eax, r15d\nlea r14d, [rax+1]\ncmovl r14d, edx\nxor edx, edx\ntest rbp, rbp\njz short loc_1628\nloc_15F6:\nmov rdi, [rbp+8]\ntest rdi, rdi\njz loc_1ED0\ncall sub_13D0\nmov rdi, [rbp+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_161B\nloc_1616:\ncall sub_13D0\nloc_161B:\nlea ecx, [rax+1]\nlea edx, [r15+1]\ncmp eax, r15d\ncmovge edx, ecx\nloc_1628:\nlea eax, [rdx+1]\nlea ecx, [r14+1]\ncmp edx, r14d\nmov r13, [r13+10h]\ncmovge ecx, eax\nxor eax, eax\nmov ebp, ecx\ntest r13, r13\njz loc_16D1\nloc_1646:\nmov r14, [r13+8]\ntest r14, r14\njz loc_1BBF\nloc_1653:\nmov rdi, [r14+8]\ntest rdi, rdi\njz loc_1F10\ncall sub_13D0\nmov rdi, [r14+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_1678\nloc_1673:\ncall sub_13D0\nloc_1678:\nmov r13, [r13+10h]\nlea edx, [r15+1]\ncmp eax, r15d\nlea r14d, [rax+1]\ncmovl r14d, edx\nxor edx, edx\ntest r13, r13\njz short loc_16C4\nloc_1692:\nmov rdi, [r13+8]\ntest rdi, rdi\njz loc_1EF0\ncall sub_13D0\nmov rdi, [r13+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_16B7\nloc_16B2:\ncall sub_13D0\nloc_16B7:\nlea ecx, [rax+1]\nlea edx, [r15+1]\ncmp eax, r15d\ncmovge edx, ecx\nloc_16C4:\nlea ecx, [rdx+1]\nlea eax, [r14+1]\ncmp edx, r14d\ncmovge eax, ecx\nloc_16D1:\ncmp eax, ebp\njge loc_1B90\nloc_16D9:\nlea eax, [rbp+1]\njmp loc_1551\nloc_16E8:\nmov r12, [rdi+10h]\nmov eax, 1\ntest r12, r12\njz loc_1578\nloc_16FA:\nmov rbx, [r12+8]\ntest rbx, rbx\njz loc_19D0\nmov r13, [rbx+8]\ntest r13, r13\njz loc_1BE0\nmov r14, [r13+8]\ntest r14, r14\njz loc_1CA0\nmov rdi, [r14+8]\ntest rdi, rdi\njz loc_1A28\ncall sub_13D0\nmov rdi, [r14+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_1747\nloc_1742:\ncall sub_13D0\nloc_1747:\nmov r13, [r13+10h]\nlea r14d, [rax+1]\ncmp eax, r15d\nlea edx, [r15+1]\ncmovl r14d, edx\nxor eax, eax\ntest r13, r13\njz short loc_1795\nloc_1761:\nmov rdi, [r13+8]\ntest rdi, rdi\njz loc_1D80\ncall sub_13D0\nmov rdi, [r13+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_1786\nloc_1781:\ncall sub_13D0\nloc_1786:\nlea ecx, [rax+1]\ncmp eax, r15d\nlea edx, [r15+1]\nmov eax, ecx\ncmovl eax, edx\nloc_1795:\nmov rbx, [rbx+10h]\nlea edx, [r14+1]\nlea r13d, [rax+1]\ncmp eax, r14d\ncmovl r13d, edx\nxor edx, edx\ntest rbx, rbx\njz loc_1840\nloc_17B3:\nmov r14, [rbx+8]\ntest r14, r14\njz loc_1CE0\nmov rdi, [r14+8]\ntest rdi, rdi\njz loc_1E70\ncall sub_13D0\nmov rdi, [r14+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_17E5\nloc_17E0:\ncall sub_13D0\nloc_17E5:\nmov rbx, [rbx+10h]\nlea r14d, [rax+1]\ncmp eax, r15d\nlea edx, [r15+1]\ncmovl r14d, edx\nxor eax, eax\ntest rbx, rbx\njz short loc_1833\nloc_17FF:\nmov rdi, [rbx+8]\ntest rdi, rdi\njz loc_1E50\ncall sub_13D0\nmov rdi, [rbx+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_1824\nloc_181F:\ncall sub_13D0\nloc_1824:\nlea ecx, [rax+1]\ncmp eax, r15d\nlea edx, [r15+1]\nmov eax, ecx\ncmovl eax, edx\nloc_1833:\nlea ecx, [rax+1]\nlea edx, [r14+1]\ncmp eax, r14d\ncmovge edx, ecx\nloc_1840:\nlea ecx, [r13+1]\nlea eax, [rdx+1]\ncmp edx, r13d\nmov r13, [r12+10h]\ncmovge ecx, eax\nxor eax, eax\nmov ebx, ecx\ntest r13, r13\njz loc_19A6\nloc_185F:\nmov r12, [r13+8]\ntest r12, r12\njz loc_19F0\nloc_186C:\nmov r14, [r12+8]\ntest r14, r14\njz loc_1D30\nmov rdi, [r14+8]\ntest rdi, rdi\njz loc_1A80\ncall sub_13D0\nmov rdi, [r14+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_189F\nloc_189A:\ncall sub_13D0\nloc_189F:\nmov r12, [r12+10h]\nlea edx, [r15+1]\ncmp eax, r15d\nlea r14d, [rax+1]\ncmovl r14d, edx\nxor edx, edx\ntest r12, r12\njz short loc_18EE\nloc_18BA:\nmov rdi, [r12+8]\ntest rdi, rdi\njz loc_1E30\ncall sub_13D0\nmov rdi, [r12+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_18E1\nloc_18DC:\ncall sub_13D0\nloc_18E1:\nlea ecx, [rax+1]\nlea edx, [r15+1]\ncmp eax, r15d\ncmovge edx, ecx\nloc_18EE:\nlea eax, [rdx+1]\nlea ecx, [r14+1]\ncmp edx, r14d\nmov r13, [r13+10h]\ncmovge ecx, eax\nxor eax, eax\nmov r12d, ecx\ntest r13, r13\njz loc_1998\nloc_190D:\nmov r14, [r13+8]\ntest r14, r14\njz loc_1A0B\nloc_191A:\nmov rdi, [r14+8]\ntest rdi, rdi\njz loc_1EA0\ncall sub_13D0\nmov rdi, [r14+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_193F\nloc_193A:\ncall sub_13D0\nloc_193F:\nmov r13, [r13+10h]\nlea edx, [r15+1]\ncmp eax, r15d\nlea r14d, [rax+1]\ncmovl r14d, edx\nxor edx, edx\ntest r13, r13\njz short loc_198B\nloc_1959:\nmov rdi, [r13+8]\ntest rdi, rdi\njz loc_1E10\ncall sub_13D0\nmov rdi, [r13+10h]\nmov r15d, eax\nxor eax, eax\ntest rdi, rdi\njz short loc_197E\nloc_1979:\ncall sub_13D0\nloc_197E:\nlea ecx, [rax+1]\nlea edx, [r15+1]\ncmp eax, r15d\ncmovge edx, ecx\nloc_198B:\nlea ecx, [rdx+1]\nlea eax, [r14+1]\ncmp edx, r14d\ncmovge eax, ecx\nloc_1998:\ncmp eax, r12d\njge loc_1B80\nloc_19A1:\nlea eax, [r12+1]\nloc_19A6:\ncmp eax, ebx\njge loc_1B70\nloc_19AE:\nlea eax, [rbx+1]\ncmp eax, ebp\njl loc_1575\nloc_19B9:\nadd rsp, 8\nadd eax, 1\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_19D0:\nmov r13, [r12+10h]\nmov eax, 1\ntest r13, r13\njz loc_156D\nmov r12, [r13+8]\ntest r12, r12\njnz loc_186C\nloc_19F0:\nmov r13, [r13+10h]\nmov eax, 1\ntest r13, r13\njz short loc_19A6\nmov r14, [r13+8]\ntest r14, r14\njnz loc_191A\nloc_1A0B:\nmov r13, [r13+10h]\nmov eax, 1\ntest r13, r13\njnz loc_1959\njmp loc_1998\nloc_1A28:\nmov rdi, [r14+10h]\nxor r15d, r15d\ntest rdi, rdi\njnz loc_1742\nmov r13, [r13+10h]\nmov r14d, 1\ntest r13, r13\njnz loc_1761\nmov rbx, [rbx+10h]\nmov r13d, 2\ntest rbx, rbx\njnz loc_17B3\nmov r13, [r12+10h]\nmov ebx, 3\ntest r13, r13\njnz loc_185F\njmp loc_19AE\nloc_1A80:\nmov rdi, [r14+10h]\nxor r15d, r15d\ntest rdi, rdi\njnz loc_189A\nmov r12, [r12+10h]\nmov r14d, 1\ntest r12, r12\njnz loc_18BA\nmov r13, [r13+10h]\nmov r12d, 2\ntest r13, r13\njnz loc_190D\njmp loc_19A1\nloc_1AC0:\nmov rdi, [r14+10h]\nxor r15d, r15d\ntest rdi, rdi\njnz loc_1436\nmov r13, [r13+10h]\nmov r14d, 1\ntest r13, r13\njnz loc_1455\nmov r12, [r12+10h]\nmov r13d, 2\ntest r12, r12\njnz loc_14A8\nmov r13, [rbp+10h]\nmov r12d, 3\ntest r13, r13\njnz loc_159D\njmp loc_1559\nloc_1B10:\nmov rdi, [r14+10h]\nxor r15d, r15d\ntest rdi, rdi\njnz loc_15D7\nmov rbp, [rbp+10h]\nmov r14d, 1\ntest rbp, rbp\njnz loc_15F6\nmov r13, [r13+10h]\nmov ebp, 2\ntest r13, r13\njnz loc_1646\njmp loc_16D9\nloc_1B50:\nmov r12, [rdi+10h]\nmov eax, 2\nmov ebp, 1\ntest r12, r12\njnz loc_16FA\njmp loc_1578\nloc_1B70:\nadd eax, 1\njmp loc_156D\nloc_1B80:\nadd eax, 1\njmp loc_19A6\nloc_1B90:\nadd eax, 1\njmp loc_1551\nloc_1BA0:\nmov r13, [r13+10h]\nmov eax, 1\ntest r13, r13\njz loc_1551\nmov r14, [r13+8]\ntest r14, r14\njnz loc_1653\nloc_1BBF:\nmov r13, [r13+10h]\nmov eax, 1\ntest r13, r13\njnz loc_1692\njmp loc_16D1\nloc_1BE0:\nmov rbx, [rbx+10h]\ntest rbx, rbx\njnz loc_17B3\nmov r13, [r12+10h]\nmov eax, 2\ntest r13, r13\njz loc_156D\nmov ebx, 1\njmp loc_185F\nloc_1C10:\nmov r12, [r12+10h]\ntest r12, r12\njnz loc_14A8\nmov r13, [rbp+10h]\nmov r12d, 1\ntest r13, r13\njnz loc_159D\nmov r12, [rdi+10h]\nmov ebp, 2\ntest r12, r12\njnz loc_16FA\njmp loc_1575\nloc_1C50:\nmov r13, [r13+10h]\ntest r13, r13\njnz loc_1455\nmov r12, [r12+10h]\nmov r13d, 1\ntest r12, r12\njnz loc_14A8\nmov r13, [rbp+10h]\nmov r12d, 2\ntest r13, r13\njnz loc_159D\nmov r12, [rdi+10h]\nmov ebp, 3\ntest r12, r12\njnz loc_16FA\njmp loc_1575\nloc_1CA0:\nmov r13, [r13+10h]\ntest r13, r13\njnz loc_1761\nmov rbx, [rbx+10h]\nmov r13d, 1\ntest rbx, rbx\njnz loc_17B3\nmov r13, [r12+10h]\nmov ebx, 2\ntest r13, r13\njnz loc_185F\njmp loc_19AE\nloc_1CE0:\nmov rbx, [rbx+10h]\nmov edx, 1\ntest rbx, rbx\njnz loc_17FF\njmp loc_1840\nloc_1D00:\nmov rbp, [rbp+10h]\ntest rbp, rbp\njnz loc_15F6\nmov r13, [r13+10h]\nmov eax, 2\ntest r13, r13\njz loc_1551\nmov ebp, 1\njmp loc_1646\nloc_1D30:\nmov r12, [r12+10h]\ntest r12, r12\njnz loc_18BA\nmov r13, [r13+10h]\nmov eax, 2\ntest r13, r13\njz loc_19A6\nmov r12d, 1\njmp loc_190D\nloc_1D60:\nmov r12, [r12+10h]\nmov eax, 1\ntest r12, r12\njnz loc_14F6\njmp loc_1537\nloc_1D80:\nmov rdi, [r13+10h]\nmov eax, 1\nxor r15d, r15d\ntest rdi, rdi\njnz loc_1781\njmp loc_1795\nloc_1DA0:\nmov rdi, [r14+10h]\nxor r15d, r15d\ntest rdi, rdi\njnz loc_14D6\nmov r12, [r12+10h]\nmov eax, 2\ntest r12, r12\njz loc_1537\nmov r14d, 1\njmp loc_14F6\nloc_1DD0:\nmov rdi, [r12+10h]\nmov edx, 1\nxor r15d, r15d\ntest rdi, rdi\njnz loc_1518\njmp loc_152A\nloc_1DF0:\nmov rdi, [r13+10h]\nmov eax, 1\nxor r15d, r15d\ntest rdi, rdi\njnz loc_1475\njmp loc_1489\nloc_1E10:\nmov rdi, [r13+10h]\nmov edx, 1\nxor r15d, r15d\ntest rdi, rdi\njnz loc_1979\njmp loc_198B\nloc_1E30:\nmov rdi, [r12+10h]\nmov edx, 1\nxor r15d, r15d\ntest rdi, rdi\njnz loc_18DC\njmp loc_18EE\nloc_1E50:\nmov rdi, [rbx+10h]\nmov eax, 1\nxor r15d, r15d\ntest rdi, rdi\njnz loc_181F\njmp loc_1833\nloc_1E70:\nmov rdi, [r14+10h]\nxor r15d, r15d\ntest rdi, rdi\njnz loc_17E0\nmov rbx, [rbx+10h]\nmov edx, 2\ntest rbx, rbx\njz loc_1840\nmov r14d, 1\njmp loc_17FF\nloc_1EA0:\nmov rdi, [r14+10h]\nxor r15d, r15d\ntest rdi, rdi\njnz loc_193A\nmov r13, [r13+10h]\nmov eax, 2\ntest r13, r13\njz loc_1998\nmov r14d, 1\njmp loc_1959\nloc_1ED0:\nmov rdi, [rbp+10h]\nmov edx, 1\nxor r15d, r15d\ntest rdi, rdi\njnz loc_1616\njmp loc_1628\nloc_1EF0:\nmov rdi, [r13+10h]\nmov edx, 1\nxor r15d, r15d\ntest rdi, rdi\njnz loc_16B2\njmp loc_16C4\nloc_1F10:\nmov rdi, [r14+10h]\nxor r15d, r15d\ntest rdi, rdi\njnz loc_1673\nmov r13, [r13+10h]\nmov eax, 2\ntest r13, r13\njz loc_16D1\nmov r14d, 1\njmp loc_1692", + "ida_strip_pseudo": "__int64 __fastcall sub_13D0(__int64 a1, __int64 a2, __int64 a3)\n{\n __int64 v4; // rbp\n __int64 v5; // r12\n __int64 v6; // r13\n __int64 v7; // r14\n int v8; // r15d\n int v9; // eax\n __int64 v10; // r13\n int v11; // eax\n int v12; // r15d\n int v13; // eax\n bool v14; // cc\n __int64 v15; // r12\n int v16; // eax\n __int64 v17; // r14\n int v18; // r15d\n int v19; // eax\n __int64 v20; // r12\n __int64 v21; // rdi\n int v22; // eax\n __int64 v23; // rdi\n int v24; // r15d\n int v25; // eax\n __int64 v26; // r13\n int v27; // eax\n __int64 v28; // r12\n int v29; // eax\n __int64 result; // rax\n __int64 v31; // rbp\n __int64 v32; // r14\n __int64 v33; // rdi\n int v34; // eax\n __int64 v35; // rdi\n int v36; // r15d\n int v37; // eax\n __int64 v38; // rbp\n __int64 v39; // rdi\n int v40; // eax\n __int64 v41; // rdi\n int v42; // r15d\n int v43; // eax\n int v44; // ecx\n __int64 v45; // r13\n int v46; // eax\n __int64 v47; // r14\n __int64 v48; // rdi\n int v49; // eax\n __int64 v50; // rdi\n int v51; // r15d\n int v52; // eax\n __int64 v53; // r13\n __int64 v54; // rdi\n int v55; // eax\n __int64 v56; // rdi\n int v57; // r15d\n int v58; // eax\n __int64 v59; // rbx\n __int64 v60; // r13\n __int64 v61; // r14\n __int64 v62; // rdi\n int v63; // eax\n __int64 v64; // rdi\n int v65; // r15d\n int v66; // eax\n __int64 v67; // r13\n int v68; // eax\n __int64 v69; // rdi\n int v70; // eax\n __int64 v71; // rdi\n int v72; // r15d\n int v73; // eax\n __int64 v74; // rbx\n __int64 v75; // r14\n __int64 v76; // rdi\n int v77; // eax\n __int64 v78; // rdi\n int v79; // r15d\n int v80; // eax\n __int64 v81; // rbx\n int v82; // eax\n __int64 v83; // rdi\n int v84; // eax\n __int64 v85; // rdi\n int v86; // r15d\n int v87; // eax\n int v88; // ecx\n __int64 v89; // r13\n int v90; // eax\n __int64 v91; // r12\n __int64 v92; // r14\n __int64 v93; // rdi\n int v94; // eax\n __int64 v95; // rdi\n int v96; // r15d\n int v97; // eax\n __int64 v98; // r12\n __int64 v99; // rdi\n int v100; // eax\n __int64 v101; // rdi\n int v102; // r15d\n int v103; // eax\n int v104; // ecx\n __int64 v105; // r13\n int v106; // eax\n __int64 v107; // r14\n __int64 v108; // rdi\n int v109; // eax\n __int64 v110; // rdi\n int v111; // r15d\n int v112; // eax\n __int64 v113; // r13\n __int64 v114; // rdi\n int v115; // eax\n __int64 v116; // rdi\n int v117; // r15d\n int v118; // eax\n\n v4 = *(_QWORD *)(a1 + 8);\n if ( v4 )\n {\n v5 = *(_QWORD *)(v4 + 8);\n if ( v5 )\n {\n v6 = *(_QWORD *)(v5 + 8);\n if ( !v6 )\n {\n v15 = *(_QWORD *)(v5 + 16);\n if ( !v15 )\n {\n v26 = *(_QWORD *)(v4 + 16);\n LODWORD(v5) = 1;\n if ( !v26 )\n {\n v28 = *(_QWORD *)(a1 + 16);\n LODWORD(v4) = 2;\n if ( !v28 )\n return (unsigned int)(v4 + 1);\n goto LABEL_76;\n }\n goto LABEL_43;\n }\n goto LABEL_19;\n }\n v7 = *(_QWORD *)(v6 + 8);\n if ( !v7 )\n {\n v10 = *(_QWORD *)(v6 + 16);\n if ( !v10 )\n {\n v15 = *(_QWORD *)(v5 + 16);\n LODWORD(v6) = 1;\n if ( !v15 )\n {\n v26 = *(_QWORD *)(v4 + 16);\n LODWORD(v5) = 2;\n if ( !v26 )\n {\n v28 = *(_QWORD *)(a1 + 16);\n LODWORD(v4) = 3;\n if ( !v28 )\n return (unsigned int)(v4 + 1);\n goto LABEL_76;\n }\n goto LABEL_43;\n }\n goto LABEL_19;\n }\n goto LABEL_11;\n }\n if ( *(_QWORD *)(v7 + 8) )\n {\n v8 = ((__int64 (*)(void))sub_13D0)();\n v9 = 0;\n if ( !*(_QWORD *)(v7 + 16) )\n goto LABEL_8;\n }\n else\n {\n v8 = 0;\n if ( !*(_QWORD *)(v7 + 16) )\n {\n v10 = *(_QWORD *)(v6 + 16);\n LODWORD(v7) = 1;\n if ( !v10 )\n {\n v15 = *(_QWORD *)(v5 + 16);\n LODWORD(v6) = 2;\n if ( !v15 )\n {\n v26 = *(_QWORD *)(v4 + 16);\n LODWORD(v5) = 3;\n if ( !v26 )\n {\nLABEL_37:\n LODWORD(v4) = v5 + 1;\nLABEL_38:\n v28 = *(_QWORD *)(a1 + 16);\n v29 = 0;\n if ( !v28 )\n goto LABEL_39;\nLABEL_76:\n v59 = *(_QWORD *)(v28 + 8);\n if ( !v59 )\n {\n v89 = *(_QWORD *)(v28 + 16);\n v29 = 1;\n if ( !v89 )\n goto LABEL_39;\n v91 = *(_QWORD *)(v89 + 8);\n if ( v91 )\n {\nLABEL_111:\n v92 = *(_QWORD *)(v91 + 8);\n if ( !v92 )\n {\n v98 = *(_QWORD *)(v91 + 16);\n if ( !v98 )\n {\n v105 = *(_QWORD *)(v89 + 16);\n v90 = 2;\n if ( !v105 )\n goto LABEL_142;\n LODWORD(v91) = 1;\n goto LABEL_126;\n }\n goto LABEL_118;\n }\n v93 = *(_QWORD *)(v92 + 8);\n if ( v93 )\n {\n v94 = sub_13D0(v93, a2, a3);\n v95 = *(_QWORD *)(v92 + 16);\n v96 = v94;\n v97 = 0;\n if ( !v95 )\n goto LABEL_115;\n }\n else\n {\n v95 = *(_QWORD *)(v92 + 16);\n v96 = 0;\n if ( !v95 )\n {\n v98 = *(_QWORD *)(v91 + 16);\n LODWORD(v92) = 1;\n if ( !v98 )\n {\n v105 = *(_QWORD *)(v89 + 16);\n LODWORD(v91) = 2;\n if ( !v105 )\n {\nLABEL_141:\n v90 = v91 + 1;\nLABEL_142:\n if ( v90 < (int)v59 )\n goto LABEL_143;\n v29 = v90 + 1;\nLABEL_39:\n if ( v29 < (int)v4 )\n return (unsigned int)(v4 + 1);\n return (unsigned int)(v29 + 1);\n }\n goto LABEL_126;\n }\n goto LABEL_118;\n }\n }\n v97 = sub_13D0(v95, a2, a3);\nLABEL_115:\n v98 = *(_QWORD *)(v91 + 16);\n LODWORD(v92) = v97 + 1;\n if ( v97 < v96 )\n LODWORD(v92) = v96 + 1;\n a3 = 0LL;\n if ( !v98 )\n {\nLABEL_123:\n v104 = v92 + 1;\n v105 = *(_QWORD *)(v89 + 16);\n if ( (int)a3 >= (int)v92 )\n v104 = a3 + 1;\n v106 = 0;\n LODWORD(v91) = v104;\n if ( !v105 )\n {\nLABEL_140:\n if ( v106 >= (int)v91 )\n {\n v90 = v106 + 1;\n goto LABEL_142;\n }\n goto LABEL_141;\n }\nLABEL_126:\n v107 = *(_QWORD *)(v105 + 8);\n if ( v107 )\n goto LABEL_127;\n goto LABEL_149;\n }\nLABEL_118:\n v99 = *(_QWORD *)(v98 + 8);\n if ( v99 )\n {\n v100 = sub_13D0(v99, a2, a3);\n v101 = *(_QWORD *)(v98 + 16);\n v102 = v100;\n v103 = 0;\n if ( !v101 )\n goto LABEL_121;\n }\n else\n {\n v101 = *(_QWORD *)(v98 + 16);\n a3 = 1LL;\n v102 = 0;\n if ( !v101 )\n goto LABEL_123;\n }\n v103 = sub_13D0(v101, a2, a3);\nLABEL_121:\n a3 = (unsigned int)(v102 + 1);\n if ( v103 >= v102 )\n a3 = (unsigned int)(v103 + 1);\n goto LABEL_123;\n }\nLABEL_147:\n v105 = *(_QWORD *)(v89 + 16);\n v90 = 1;\n if ( !v105 )\n goto LABEL_142;\n v107 = *(_QWORD *)(v105 + 8);\n if ( v107 )\n {\nLABEL_127:\n v108 = *(_QWORD *)(v107 + 8);\n if ( v108 )\n {\n v109 = sub_13D0(v108, a2, a3);\n v110 = *(_QWORD *)(v107 + 16);\n v111 = v109;\n v112 = 0;\n if ( !v110 )\n goto LABEL_130;\n }\n else\n {\n v110 = *(_QWORD *)(v107 + 16);\n v111 = 0;\n if ( !v110 )\n {\n v113 = *(_QWORD *)(v105 + 16);\n v106 = 2;\n if ( !v113 )\n goto LABEL_140;\n LODWORD(v107) = 1;\n goto LABEL_133;\n }\n }\n v112 = sub_13D0(v110, a2, a3);\nLABEL_130:\n v113 = *(_QWORD *)(v105 + 16);\n LODWORD(v107) = v112 + 1;\n if ( v112 < v111 )\n LODWORD(v107) = v111 + 1;\n a3 = 0LL;\n if ( !v113 )\n goto LABEL_138;\nLABEL_133:\n v114 = *(_QWORD *)(v113 + 8);\n if ( v114 )\n {\n v115 = sub_13D0(v114, a2, a3);\n v116 = *(_QWORD *)(v113 + 16);\n v117 = v115;\n v118 = 0;\n if ( !v116 )\n goto LABEL_136;\n }\n else\n {\n v116 = *(_QWORD *)(v113 + 16);\n a3 = 1LL;\n v117 = 0;\n if ( !v116 )\n {\nLABEL_138:\n v106 = v107 + 1;\n if ( (int)a3 >= (int)v107 )\n v106 = a3 + 1;\n goto LABEL_140;\n }\n }\n v118 = sub_13D0(v116, a2, a3);\nLABEL_136:\n LODWORD(a3) = v117 + 1;\n if ( v118 >= v117 )\n LODWORD(a3) = v118 + 1;\n goto LABEL_138;\n }\nLABEL_149:\n v113 = *(_QWORD *)(v105 + 16);\n v106 = 1;\n if ( !v113 )\n goto LABEL_140;\n goto LABEL_133;\n }\n v60 = *(_QWORD *)(v59 + 8);\n if ( !v60 )\n {\n v74 = *(_QWORD *)(v59 + 16);\n if ( !v74 )\n {\n v89 = *(_QWORD *)(v28 + 16);\n v29 = 2;\n if ( !v89 )\n goto LABEL_39;\n LODWORD(v59) = 1;\n goto LABEL_110;\n }\n goto LABEL_93;\n }\n v61 = *(_QWORD *)(v60 + 8);\n if ( v61 )\n {\n v62 = *(_QWORD *)(v61 + 8);\n if ( v62 )\n {\n v63 = sub_13D0(v62, a2, a3);\n v64 = *(_QWORD *)(v61 + 16);\n v65 = v63;\n v66 = 0;\n if ( !v64 )\n goto LABEL_82;\n goto LABEL_81;\n }\n v64 = *(_QWORD *)(v61 + 16);\n v65 = 0;\n if ( v64 )\n {\nLABEL_81:\n v66 = sub_13D0(v64, a2, a3);\nLABEL_82:\n v67 = *(_QWORD *)(v60 + 16);\n LODWORD(v61) = v66 + 1;\n a3 = (unsigned int)(v65 + 1);\n if ( v66 < v65 )\n LODWORD(v61) = v65 + 1;\n v68 = 0;\n if ( !v67 )\n {\nLABEL_90:\n v74 = *(_QWORD *)(v59 + 16);\n LODWORD(v60) = v68 + 1;\n if ( v68 < (int)v61 )\n LODWORD(v60) = v61 + 1;\n a3 = 0LL;\n if ( !v74 )\n {\nLABEL_107:\n v88 = v60 + 1;\n v14 = (int)a3 < (int)v60;\n v89 = *(_QWORD *)(v28 + 16);\n if ( !v14 )\n v88 = a3 + 1;\n v90 = 0;\n LODWORD(v59) = v88;\n if ( !v89 )\n goto LABEL_142;\nLABEL_110:\n v91 = *(_QWORD *)(v89 + 8);\n if ( v91 )\n goto LABEL_111;\n goto LABEL_147;\n }\nLABEL_93:\n v75 = *(_QWORD *)(v74 + 8);\n if ( !v75 )\n {\n v81 = *(_QWORD *)(v74 + 16);\n a3 = 1LL;\n if ( !v81 )\n goto LABEL_107;\n goto LABEL_100;\n }\n v76 = *(_QWORD *)(v75 + 8);\n if ( v76 )\n {\n v77 = sub_13D0(v76, a2, a3);\n v78 = *(_QWORD *)(v75 + 16);\n v79 = v77;\n v80 = 0;\n if ( !v78 )\n goto LABEL_97;\n }\n else\n {\n v78 = *(_QWORD *)(v75 + 16);\n v79 = 0;\n if ( !v78 )\n {\n v81 = *(_QWORD *)(v74 + 16);\n a3 = 2LL;\n if ( !v81 )\n goto LABEL_107;\n LODWORD(v75) = 1;\n goto LABEL_100;\n }\n }\n v80 = sub_13D0(v78, a2, a3);\nLABEL_97:\n v81 = *(_QWORD *)(v74 + 16);\n LODWORD(v75) = v80 + 1;\n a3 = (unsigned int)(v79 + 1);\n if ( v80 < v79 )\n LODWORD(v75) = v79 + 1;\n v82 = 0;\n if ( !v81 )\n goto LABEL_105;\nLABEL_100:\n v83 = *(_QWORD *)(v81 + 8);\n if ( v83 )\n {\n v84 = sub_13D0(v83, a2, a3);\n v85 = *(_QWORD *)(v81 + 16);\n v86 = v84;\n v87 = 0;\n if ( !v85 )\n goto LABEL_103;\n }\n else\n {\n v85 = *(_QWORD *)(v81 + 16);\n v82 = 1;\n v86 = 0;\n if ( !v85 )\n {\nLABEL_105:\n a3 = (unsigned int)(v75 + 1);\n if ( v82 >= (int)v75 )\n a3 = (unsigned int)(v82 + 1);\n goto LABEL_107;\n }\n }\n v87 = sub_13D0(v85, a2, a3);\nLABEL_103:\n v14 = v87 < v86;\n v82 = v87 + 1;\n if ( v14 )\n v82 = v86 + 1;\n goto LABEL_105;\n }\nLABEL_85:\n v69 = *(_QWORD *)(v67 + 8);\n if ( v69 )\n {\n v70 = sub_13D0(v69, a2, a3);\n v71 = *(_QWORD *)(v67 + 16);\n v72 = v70;\n v73 = 0;\n if ( !v71 )\n goto LABEL_88;\n }\n else\n {\n v71 = *(_QWORD *)(v67 + 16);\n v68 = 1;\n v72 = 0;\n if ( !v71 )\n goto LABEL_90;\n }\n v73 = sub_13D0(v71, a2, a3);\nLABEL_88:\n v14 = v73 < v72;\n v68 = v73 + 1;\n if ( v14 )\n v68 = v72 + 1;\n goto LABEL_90;\n }\n v67 = *(_QWORD *)(v60 + 16);\n LODWORD(v61) = 1;\n if ( v67 )\n goto LABEL_85;\n v74 = *(_QWORD *)(v59 + 16);\n LODWORD(v60) = 2;\n if ( v74 )\n goto LABEL_93;\n v89 = *(_QWORD *)(v28 + 16);\n LODWORD(v59) = 3;\n if ( v89 )\n goto LABEL_110;\n }\n else\n {\n v67 = *(_QWORD *)(v60 + 16);\n if ( v67 )\n goto LABEL_85;\n v74 = *(_QWORD *)(v59 + 16);\n LODWORD(v60) = 1;\n if ( v74 )\n goto LABEL_93;\n v89 = *(_QWORD *)(v28 + 16);\n LODWORD(v59) = 2;\n if ( v89 )\n goto LABEL_110;\n }\nLABEL_143:\n v29 = v59 + 1;\n if ( (int)v59 + 1 < (int)v4 )\n return (unsigned int)(v4 + 1);\n return (unsigned int)(v29 + 1);\n }\n goto LABEL_43;\n }\n goto LABEL_19;\n }\n goto LABEL_11;\n }\n }\n v9 = ((__int64 (*)(void))sub_13D0)();\nLABEL_8:\n v10 = *(_QWORD *)(v6 + 16);\n LODWORD(v7) = v9 + 1;\n if ( v9 < v8 )\n LODWORD(v7) = v8 + 1;\n v11 = 0;\n if ( !v10 )\n {\nLABEL_16:\n v15 = *(_QWORD *)(v5 + 16);\n LODWORD(v6) = v11 + 1;\n a3 = (unsigned int)(v7 + 1);\n if ( v11 < (int)v7 )\n LODWORD(v6) = v7 + 1;\n v16 = 0;\n if ( !v15 )\n {\nLABEL_33:\n a3 = (unsigned int)(v6 + 1);\n LODWORD(v5) = v16 + 1;\n v14 = v16 < (int)v6;\n v26 = *(_QWORD *)(v4 + 16);\n if ( v14 )\n LODWORD(v5) = a3;\n v27 = 0;\n if ( !v26 )\n {\nLABEL_36:\n LODWORD(v4) = v27 + 1;\n if ( v27 >= (int)v5 )\n goto LABEL_38;\n goto LABEL_37;\n }\nLABEL_43:\n v31 = *(_QWORD *)(v26 + 8);\n if ( !v31 )\n {\n v45 = *(_QWORD *)(v26 + 16);\n v27 = 1;\n if ( !v45 )\n goto LABEL_36;\n v47 = *(_QWORD *)(v45 + 8);\n if ( v47 )\n {\nLABEL_60:\n v48 = *(_QWORD *)(v47 + 8);\n if ( v48 )\n {\n v49 = sub_13D0(v48, a2, a3);\n v50 = *(_QWORD *)(v47 + 16);\n v51 = v49;\n v52 = 0;\n if ( !v50 )\n goto LABEL_63;\n }\n else\n {\n v50 = *(_QWORD *)(v47 + 16);\n v51 = 0;\n if ( !v50 )\n {\n v53 = *(_QWORD *)(v45 + 16);\n v46 = 2;\n if ( !v53 )\n goto LABEL_73;\n LODWORD(v47) = 1;\n goto LABEL_66;\n }\n }\n v52 = sub_13D0(v50, a2, a3);\nLABEL_63:\n v53 = *(_QWORD *)(v45 + 16);\n LODWORD(v47) = v52 + 1;\n if ( v52 < v51 )\n LODWORD(v47) = v51 + 1;\n a3 = 0LL;\n if ( !v53 )\n goto LABEL_71;\nLABEL_66:\n v54 = *(_QWORD *)(v53 + 8);\n if ( v54 )\n {\n v55 = sub_13D0(v54, a2, a3);\n v56 = *(_QWORD *)(v53 + 16);\n v57 = v55;\n v58 = 0;\n if ( !v56 )\n goto LABEL_69;\n }\n else\n {\n v56 = *(_QWORD *)(v53 + 16);\n a3 = 1LL;\n v57 = 0;\n if ( !v56 )\n {\nLABEL_71:\n v46 = v47 + 1;\n if ( (int)a3 >= (int)v47 )\n v46 = a3 + 1;\n goto LABEL_73;\n }\n }\n v58 = sub_13D0(v56, a2, a3);\nLABEL_69:\n a3 = (unsigned int)(v57 + 1);\n if ( v58 >= v57 )\n a3 = (unsigned int)(v58 + 1);\n goto LABEL_71;\n }\nLABEL_176:\n v53 = *(_QWORD *)(v45 + 16);\n v46 = 1;\n if ( !v53 )\n goto LABEL_73;\n goto LABEL_66;\n }\n v32 = *(_QWORD *)(v31 + 8);\n if ( !v32 )\n {\n v38 = *(_QWORD *)(v31 + 16);\n if ( !v38 )\n {\n v45 = *(_QWORD *)(v26 + 16);\n v27 = 2;\n if ( !v45 )\n goto LABEL_36;\n LODWORD(v31) = 1;\n goto LABEL_59;\n }\n goto LABEL_51;\n }\n v33 = *(_QWORD *)(v32 + 8);\n if ( v33 )\n {\n v34 = sub_13D0(v33, a2, a3);\n v35 = *(_QWORD *)(v32 + 16);\n v36 = v34;\n v37 = 0;\n if ( !v35 )\n goto LABEL_48;\n }\n else\n {\n v35 = *(_QWORD *)(v32 + 16);\n v36 = 0;\n if ( !v35 )\n {\n v38 = *(_QWORD *)(v31 + 16);\n LODWORD(v32) = 1;\n if ( !v38 )\n {\n v45 = *(_QWORD *)(v26 + 16);\n LODWORD(v31) = 2;\n if ( !v45 )\n goto LABEL_74;\n goto LABEL_59;\n }\n goto LABEL_51;\n }\n }\n v37 = sub_13D0(v35, a2, a3);\nLABEL_48:\n v38 = *(_QWORD *)(v31 + 16);\n LODWORD(v32) = v37 + 1;\n if ( v37 < v36 )\n LODWORD(v32) = v36 + 1;\n a3 = 0LL;\n if ( !v38 )\n {\nLABEL_56:\n v44 = v32 + 1;\n v45 = *(_QWORD *)(v26 + 16);\n if ( (int)a3 >= (int)v32 )\n v44 = a3 + 1;\n v46 = 0;\n LODWORD(v31) = v44;\n if ( !v45 )\n {\nLABEL_73:\n if ( v46 >= (int)v31 )\n {\n v27 = v46 + 1;\n goto LABEL_36;\n }\nLABEL_74:\n v27 = v31 + 1;\n goto LABEL_36;\n }\nLABEL_59:\n v47 = *(_QWORD *)(v45 + 8);\n if ( v47 )\n goto LABEL_60;\n goto LABEL_176;\n }\nLABEL_51:\n v39 = *(_QWORD *)(v38 + 8);\n if ( v39 )\n {\n v40 = sub_13D0(v39, a2, a3);\n v41 = *(_QWORD *)(v38 + 16);\n v42 = v40;\n v43 = 0;\n if ( !v41 )\n goto LABEL_54;\n }\n else\n {\n v41 = *(_QWORD *)(v38 + 16);\n a3 = 1LL;\n v42 = 0;\n if ( !v41 )\n goto LABEL_56;\n }\n v43 = sub_13D0(v41, a2, a3);\nLABEL_54:\n a3 = (unsigned int)(v42 + 1);\n if ( v43 >= v42 )\n a3 = (unsigned int)(v43 + 1);\n goto LABEL_56;\n }\nLABEL_19:\n v17 = *(_QWORD *)(v15 + 8);\n if ( !v17 )\n {\n v20 = *(_QWORD *)(v15 + 16);\n v16 = 1;\n if ( !v20 )\n goto LABEL_33;\n goto LABEL_26;\n }\n if ( *(_QWORD *)(v17 + 8) )\n {\n v18 = ((__int64 (*)(void))sub_13D0)();\n v19 = 0;\n if ( !*(_QWORD *)(v17 + 16) )\n goto LABEL_23;\n }\n else\n {\n v18 = 0;\n if ( !*(_QWORD *)(v17 + 16) )\n {\n v20 = *(_QWORD *)(v15 + 16);\n v16 = 2;\n if ( !v20 )\n goto LABEL_33;\n LODWORD(v17) = 1;\n goto LABEL_26;\n }\n }\n v19 = ((__int64 (*)(void))sub_13D0)();\nLABEL_23:\n v20 = *(_QWORD *)(v15 + 16);\n LODWORD(v17) = v19 + 1;\n if ( v19 < v18 )\n LODWORD(v17) = v18 + 1;\n a3 = 0LL;\n if ( !v20 )\n goto LABEL_31;\nLABEL_26:\n v21 = *(_QWORD *)(v20 + 8);\n if ( v21 )\n {\n v22 = sub_13D0(v21, a2, a3);\n v23 = *(_QWORD *)(v20 + 16);\n v24 = v22;\n v25 = 0;\n if ( !v23 )\n goto LABEL_29;\n }\n else\n {\n v23 = *(_QWORD *)(v20 + 16);\n a3 = 1LL;\n v24 = 0;\n if ( !v23 )\n {\nLABEL_31:\n v16 = v17 + 1;\n if ( (int)a3 >= (int)v17 )\n v16 = a3 + 1;\n goto LABEL_33;\n }\n }\n v25 = sub_13D0(v23, a2, a3);\nLABEL_29:\n LODWORD(a3) = v24 + 1;\n if ( v25 >= v24 )\n LODWORD(a3) = v25 + 1;\n goto LABEL_31;\n }\nLABEL_11:\n if ( *(_QWORD *)(v10 + 8) )\n {\n v12 = ((__int64 (*)(void))sub_13D0)();\n v13 = 0;\n if ( !*(_QWORD *)(v10 + 16) )\n goto LABEL_14;\n }\n else\n {\n v11 = 1;\n v12 = 0;\n if ( !*(_QWORD *)(v10 + 16) )\n goto LABEL_16;\n }\n v13 = ((__int64 (*)(void))sub_13D0)();\nLABEL_14:\n v14 = v13 < v12;\n v11 = v13 + 1;\n if ( v14 )\n v11 = v12 + 1;\n goto LABEL_16;\n }\n v26 = *(_QWORD *)(v4 + 16);\n if ( v26 )\n goto LABEL_43;\n v28 = *(_QWORD *)(a1 + 16);\n result = 2LL;\n LODWORD(v4) = 1;\n if ( v28 )\n goto LABEL_76;\n }\n else\n {\n v28 = *(_QWORD *)(a1 + 16);\n result = 1LL;\n if ( v28 )\n goto LABEL_76;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_13D0(long long a1, long long a2, long long a3) {\n long long v4;\n long long v5;\n long long v6;\n long long v7;\n int v8;\n int v9;\n long long v10;\n int v11;\n int v12;\n int v13;\n bool v14;\n long long v15;\n int v16;\n long long v17;\n int v18;\n int v19;\n long long v20;\n long long v21;\n int v22;\n long long v23;\n int v24;\n int v25;\n long long v26;\n int v27;\n long long v28;\n int v29;\n long long result;\n long long v31;\n long long v32;\n long long v33;\n int v34;\n long long v35;\n int v36;\n int v37;\n long long v38;\n long long v39;\n int v40;\n long long v41;\n int v42;\n int v43;\n int v44;\n long long v45;\n int v46;\n long long v47;\n long long v48;\n int v49;\n long long v50;\n int v51;\n int v52;\n long long v53;\n long long v54;\n int v55;\n long long v56;\n int v57;\n int v58;\n long long v59;\n long long v60;\n long long v61;\n long long v62;\n int v63;\n long long v64;\n int v65;\n int v66;\n long long v67;\n int v68;\n long long v69;\n int v70;\n long long v71;\n int v72;\n int v73;\n long long v74;\n long long v75;\n long long v76;\n int v77;\n long long v78;\n int v79;\n int v80;\n long long v81;\n int v82;\n long long v83;\n int v84;\n long long v85;\n int v86;\n int v87;\n int v88;\n long long v89;\n int v90;\n long long v91;\n long long v92;\n long long v93;\n int v94;\n long long v95;\n int v96;\n int v97;\n long long v98;\n long long v99;\n int v100;\n long long v101;\n int v102;\n int v103;\n int v104;\n long long v105;\n int v106;\n long long v107;\n long long v108;\n int v109;\n long long v110;\n int v111;\n int v112;\n long long v113;\n long long v114;\n int v115;\n long long v116;\n int v117;\n int v118;\n v4 = *(uint64_t *)(a1 + 8);\n if (v4) {\n v5 = *(uint64_t *)(v4 + 8);\n if (v5) {\n v6 = *(uint64_t *)(v5 + 8);\n if (!v6) {\n v15 = *(uint64_t *)(v5 + 16);\n if (!v15) {\n v26 = *(uint64_t *)(v4 + 16);\n LODWORD(v5) = 1;\n if (!v26) {\n v28 = *(uint64_t *)(a1 + 16);\n LODWORD(v4) = 2;\n if (!v28) return (unsigned int)(v4 + 1);\n goto LABEL_76;\n }\n goto LABEL_43;\n }\n goto LABEL_19;\n }\n v7 = *(uint64_t *)(v6 + 8);\n if (!v7) {\n v10 = *(uint64_t *)(v6 + 16);\n if (!v10) {\n v15 = *(uint64_t *)(v5 + 16);\n LODWORD(v6) = 1;\n if (!v15) {\n v26 = *(uint64_t *)(v4 + 16);\n LODWORD(v5) = 2;\n if (!v26) {\n v28 = *(uint64_t *)(a1 + 16);\n LODWORD(v4) = 3;\n if (!v28) return (unsigned int)(v4 + 1);\n goto LABEL_76;\n }\n goto LABEL_43;\n }\n goto LABEL_19;\n }\n goto LABEL_11;\n }\n if (*(uint64_t *)(v7 + 8)) {\n v8 = ((long long (*)(void))sub_13D0)();\n v9 = 0;\n if (!*(uint64_t *)(v7 + 16)) goto LABEL_8;\n } else {\n v8 = 0;\n if (!*(uint64_t *)(v7 + 16)) {\n v10 = *(uint64_t *)(v6 + 16);\n LODWORD(v7) = 1;\n if (!v10) {\n v15 = *(uint64_t *)(v5 + 16);\n LODWORD(v6) = 2;\n if (!v15) {\n v26 = *(uint64_t *)(v4 + 16);\n LODWORD(v5) = 3;\n if (!v26) {\n LABEL_37:\n LODWORD(v4) = v5 + 1;\n LABEL_38:\n v28 = *(uint64_t *)(a1 + 16);\n v29 = 0;\n if (!v28) goto LABEL_39;\n LABEL_76:\n v59 = *(uint64_t *)(v28 + 8);\n if (!v59) {\n v89 = *(uint64_t *)(v28 + 16);\n v29 = 1;\n if (!v89) goto LABEL_39;\n v91 = *(uint64_t *)(v89 + 8);\n if (v91) {\n LABEL_111:\n v92 = *(uint64_t *)(v91 + 8);\n if (!v92) {\n v98 = *(uint64_t *)(v91 + 16);\n if (!v98) {\n v105 = *(uint64_t *)(v89 + 16);\n v90 = 2;\n if (!v105) goto LABEL_142;\n LODWORD(v91) = 1;\n goto LABEL_126;\n }\n goto LABEL_118;\n }\n v93 = *(uint64_t *)(v92 + 8);\n if (v93) {\n v94 = sub_13D0(v93, a2, a3);\n v95 = *(uint64_t *)(v92 + 16);\n v96 = v94;\n v97 = 0;\n if (!v95) goto LABEL_115;\n } else {\n v95 = *(uint64_t *)(v92 + 16);\n v96 = 0;\n if (!v95) {\n v98 = *(uint64_t *)(v91 + 16);\n LODWORD(v92) = 1;\n if (!v98) {\n v105 = *(uint64_t *)(v89 + 16);\n LODWORD(v91) = 2;\n if (!v105) {\n LABEL_141:\n v90 = v91 + 1;\n LABEL_142:\n if (v90 < (int)v59) goto LABEL_143;\n v29 = v90 + 1;\n LABEL_39:\n if (v29 < (int)v4) return (unsigned int)(v4 + 1);\n return (unsigned int)(v29 + 1);\n }\n goto LABEL_126;\n }\n goto LABEL_118;\n }\n }\n v97 = sub_13D0(v95, a2, a3);\n LABEL_115:\n v98 = *(uint64_t *)(v91 + 16);\n LODWORD(v92) = v97 + 1;\n if (v97 < v96) LODWORD(v92) = v96 + 1;\n a3 = 0LL;\n if (!v98) {\n LABEL_123:\n v104 = v92 + 1;\n v105 = *(uint64_t *)(v89 + 16);\n if ((int)a3 >= (int)v92) v104 = a3 + 1;\n v106 = 0;\n LODWORD(v91) = v104;\n if (!v105) {\n LABEL_140:\n if (v106 >= (int)v91) {\n v90 = v106 + 1;\n goto LABEL_142;\n }\n goto LABEL_141;\n }\n LABEL_126:\n v107 = *(uint64_t *)(v105 + 8);\n if (v107) goto LABEL_127;\n goto LABEL_149;\n }\n LABEL_118:\n v99 = *(uint64_t *)(v98 + 8);\n if (v99) {\n v100 = sub_13D0(v99, a2, a3);\n v101 = *(uint64_t *)(v98 + 16);\n v102 = v100;\n v103 = 0;\n if (!v101) goto LABEL_121;\n } else {\n v101 = *(uint64_t *)(v98 + 16);\n a3 = 1LL;\n v102 = 0;\n if (!v101) goto LABEL_123;\n }\n v103 = sub_13D0(v101, a2, a3);\n LABEL_121:\n a3 = (unsigned int)(v102 + 1);\n if (v103 >= v102) a3 = (unsigned int)(v103 + 1);\n goto LABEL_123;\n }\n LABEL_147:\n v105 = *(uint64_t *)(v89 + 16);\n v90 = 1;\n if (!v105) goto LABEL_142;\n v107 = *(uint64_t *)(v105 + 8);\n if (v107) {\n LABEL_127:\n v108 = *(uint64_t *)(v107 + 8);\n if (v108) {\n v109 = sub_13D0(v108, a2, a3);\n v110 = *(uint64_t *)(v107 + 16);\n v111 = v109;\n v112 = 0;\n if (!v110) goto LABEL_130;\n } else {\n v110 = *(uint64_t *)(v107 + 16);\n v111 = 0;\n if (!v110) {\n v113 = *(uint64_t *)(v105 + 16);\n v106 = 2;\n if (!v113) goto LABEL_140;\n LODWORD(v107) = 1;\n goto LABEL_133;\n }\n }\n v112 = sub_13D0(v110, a2, a3);\n LABEL_130:\n v113 = *(uint64_t *)(v105 + 16);\n LODWORD(v107) = v112 + 1;\n if (v112 < v111) LODWORD(v107) = v111 + 1;\n a3 = 0LL;\n if (!v113) goto LABEL_138;\n LABEL_133:\n v114 = *(uint64_t *)(v113 + 8);\n if (v114) {\n v115 = sub_13D0(v114, a2, a3);\n v116 = *(uint64_t *)(v113 + 16);\n v117 = v115;\n v118 = 0;\n if (!v116) goto LABEL_136;\n } else {\n v116 = *(uint64_t *)(v113 + 16);\n a3 = 1LL;\n v117 = 0;\n if (!v116) {\n LABEL_138:\n v106 = v107 + 1;\n if ((int)a3 >= (int)v107) v106 = a3 + 1;\n goto LABEL_140;\n }\n }\n v118 = sub_13D0(v116, a2, a3);\n LABEL_136:\n LODWORD(a3) = v117 + 1;\n if (v118 >= v117) LODWORD(a3) = v118 + 1;\n goto LABEL_138;\n }\n LABEL_149:\n v113 = *(uint64_t *)(v105 + 16);\n v106 = 1;\n if (!v113) goto LABEL_140;\n goto LABEL_133;\n }\n v60 = *(uint64_t *)(v59 + 8);\n if (!v60) {\n v74 = *(uint64_t *)(v59 + 16);\n if (!v74) {\n v89 = *(uint64_t *)(v28 + 16);\n v29 = 2;\n if (!v89) goto LABEL_39;\n LODWORD(v59) = 1;\n goto LABEL_110;\n }\n goto LABEL_93;\n }\n v61 = *(uint64_t *)(v60 + 8);\n if (v61) {\n v62 = *(uint64_t *)(v61 + 8);\n if (v62) {\n v63 = sub_13D0(v62, a2, a3);\n v64 = *(uint64_t *)(v61 + 16);\n v65 = v63;\n v66 = 0;\n if (!v64) goto LABEL_82;\n goto LABEL_81;\n }\n v64 = *(uint64_t *)(v61 + 16);\n v65 = 0;\n if (v64) {\n LABEL_81:\n v66 = sub_13D0(v64, a2, a3);\n LABEL_82:\n v67 = *(uint64_t *)(v60 + 16);\n LODWORD(v61) = v66 + 1;\n a3 = (unsigned int)(v65 + 1);\n if (v66 < v65) LODWORD(v61) = v65 + 1;\n v68 = 0;\n if (!v67) {\n LABEL_90:\n v74 = *(uint64_t *)(v59 + 16);\n LODWORD(v60) = v68 + 1;\n if (v68 < (int)v61) LODWORD(v60) = v61 + 1;\n a3 = 0LL;\n if (!v74) {\n LABEL_107:\n v88 = v60 + 1;\n v14 = (int)a3 < (int)v60;\n v89 = *(uint64_t *)(v28 + 16);\n if (!v14) v88 = a3 + 1;\n v90 = 0;\n LODWORD(v59) = v88;\n if (!v89) goto LABEL_142;\n LABEL_110:\n v91 = *(uint64_t *)(v89 + 8);\n if (v91) goto LABEL_111;\n goto LABEL_147;\n }\n LABEL_93:\n v75 = *(uint64_t *)(v74 + 8);\n if (!v75) {\n v81 = *(uint64_t *)(v74 + 16);\n a3 = 1LL;\n if (!v81) goto LABEL_107;\n goto LABEL_100;\n }\n v76 = *(uint64_t *)(v75 + 8);\n if (v76) {\n v77 = sub_13D0(v76, a2, a3);\n v78 = *(uint64_t *)(v75 + 16);\n v79 = v77;\n v80 = 0;\n if (!v78) goto LABEL_97;\n } else {\n v78 = *(uint64_t *)(v75 + 16);\n v79 = 0;\n if (!v78) {\n v81 = *(uint64_t *)(v74 + 16);\n a3 = 2LL;\n if (!v81) goto LABEL_107;\n LODWORD(v75) = 1;\n goto LABEL_100;\n }\n }\n v80 = sub_13D0(v78, a2, a3);\n LABEL_97:\n v81 = *(uint64_t *)(v74 + 16);\n LODWORD(v75) = v80 + 1;\n a3 = (unsigned int)(v79 + 1);\n if (v80 < v79) LODWORD(v75) = v79 + 1;\n v82 = 0;\n if (!v81) goto LABEL_105;\n LABEL_100:\n v83 = *(uint64_t *)(v81 + 8);\n if (v83) {\n v84 = sub_13D0(v83, a2, a3);\n v85 = *(uint64_t *)(v81 + 16);\n v86 = v84;\n v87 = 0;\n if (!v85) goto LABEL_103;\n } else {\n v85 = *(uint64_t *)(v81 + 16);\n v82 = 1;\n v86 = 0;\n if (!v85) {\n LABEL_105:\n a3 = (unsigned int)(v75 + 1);\n if (v82 >= (int)v75) a3 = (unsigned int)(v82 + 1);\n goto LABEL_107;\n }\n }\n v87 = sub_13D0(v85, a2, a3);\n LABEL_103:\n v14 = v87 < v86;\n v82 = v87 + 1;\n if (v14) v82 = v86 + 1;\n goto LABEL_105;\n }\n LABEL_85:\n v69 = *(uint64_t *)(v67 + 8);\n if (v69) {\n v70 = sub_13D0(v69, a2, a3);\n v71 = *(uint64_t *)(v67 + 16);\n v72 = v70;\n v73 = 0;\n if (!v71) goto LABEL_88;\n } else {\n v71 = *(uint64_t *)(v67 + 16);\n v68 = 1;\n v72 = 0;\n if (!v71) goto LABEL_90;\n }\n v73 = sub_13D0(v71, a2, a3);\n LABEL_88:\n v14 = v73 < v72;\n v68 = v73 + 1;\n if (v14) v68 = v72 + 1;\n goto LABEL_90;\n }\n v67 = *(uint64_t *)(v60 + 16);\n LODWORD(v61) = 1;\n if (v67) goto LABEL_85;\n v74 = *(uint64_t *)(v59 + 16);\n LODWORD(v60) = 2;\n if (v74) goto LABEL_93;\n v89 = *(uint64_t *)(v28 + 16);\n LODWORD(v59) = 3;\n if (v89) goto LABEL_110;\n } else {\n v67 = *(uint64_t *)(v60 + 16);\n if (v67) goto LABEL_85;\n v74 = *(uint64_t *)(v59 + 16);\n LODWORD(v60) = 1;\n if (v74) goto LABEL_93;\n v89 = *(uint64_t *)(v28 + 16);\n LODWORD(v59) = 2;\n if (v89) goto LABEL_110;\n }\n LABEL_143:\n v29 = v59 + 1;\n if ((int)v59 + 1 < (int)v4) return (unsigned int)(v4 + 1);\n return (unsigned int)(v29 + 1);\n }\n goto LABEL_43;\n }\n goto LABEL_19;\n }\n goto LABEL_11;\n }\n }\n v9 = ((long long (*)(void))sub_13D0)();\n LABEL_8:\n v10 = *(uint64_t *)(v6 + 16);\n LODWORD(v7) = v9 + 1;\n if (v9 < v8) LODWORD(v7) = v8 + 1;\n v11 = 0;\n if (!v10) {\n LABEL_16:\n v15 = *(uint64_t *)(v5 + 16);\n LODWORD(v6) = v11 + 1;\n a3 = (unsigned int)(v7 + 1);\n if (v11 < (int)v7) LODWORD(v6) = v7 + 1;\n v16 = 0;\n if (!v15) {\n LABEL_33:\n a3 = (unsigned int)(v6 + 1);\n LODWORD(v5) = v16 + 1;\n v14 = v16 < (int)v6;\n v26 = *(uint64_t *)(v4 + 16);\n if (v14) LODWORD(v5) = a3;\n v27 = 0;\n if (!v26) {\n LABEL_36:\n LODWORD(v4) = v27 + 1;\n if (v27 >= (int)v5) goto LABEL_38;\n goto LABEL_37;\n }\n LABEL_43:\n v31 = *(uint64_t *)(v26 + 8);\n if (!v31) {\n v45 = *(uint64_t *)(v26 + 16);\n v27 = 1;\n if (!v45) goto LABEL_36;\n v47 = *(uint64_t *)(v45 + 8);\n if (v47) {\n LABEL_60:\n v48 = *(uint64_t *)(v47 + 8);\n if (v48) {\n v49 = sub_13D0(v48, a2, a3);\n v50 = *(uint64_t *)(v47 + 16);\n v51 = v49;\n v52 = 0;\n if (!v50) goto LABEL_63;\n } else {\n v50 = *(uint64_t *)(v47 + 16);\n v51 = 0;\n if (!v50) {\n v53 = *(uint64_t *)(v45 + 16);\n v46 = 2;\n if (!v53) goto LABEL_73;\n LODWORD(v47) = 1;\n goto LABEL_66;\n }\n }\n v52 = sub_13D0(v50, a2, a3);\n LABEL_63:\n v53 = *(uint64_t *)(v45 + 16);\n LODWORD(v47) = v52 + 1;\n if (v52 < v51) LODWORD(v47) = v51 + 1;\n a3 = 0LL;\n if (!v53) goto LABEL_71;\n LABEL_66:\n v54 = *(uint64_t *)(v53 + 8);\n if (v54) {\n v55 = sub_13D0(v54, a2, a3);\n v56 = *(uint64_t *)(v53 + 16);\n v57 = v55;\n v58 = 0;\n if (!v56) goto LABEL_69;\n } else {\n v56 = *(uint64_t *)(v53 + 16);\n a3 = 1LL;\n v57 = 0;\n if (!v56) {\n LABEL_71:\n v46 = v47 + 1;\n if ((int)a3 >= (int)v47) v46 = a3 + 1;\n goto LABEL_73;\n }\n }\n v58 = sub_13D0(v56, a2, a3);\n LABEL_69:\n a3 = (unsigned int)(v57 + 1);\n if (v58 >= v57) a3 = (unsigned int)(v58 + 1);\n goto LABEL_71;\n }\n LABEL_176:\n v53 = *(uint64_t *)(v45 + 16);\n v46 = 1;\n if (!v53) goto LABEL_73;\n goto LABEL_66;\n }\n v32 = *(uint64_t *)(v31 + 8);\n if (!v32) {\n v38 = *(uint64_t *)(v31 + 16);\n if (!v38) {\n v45 = *(uint64_t *)(v26 + 16);\n v27 = 2;\n if (!v45) goto LABEL_36;\n LODWORD(v31) = 1;\n goto LABEL_59;\n }\n goto LABEL_51;\n }\n v33 = *(uint64_t *)(v32 + 8);\n if (v33) {\n v34 = sub_13D0(v33, a2, a3);\n v35 = *(uint64_t *)(v32 + 16);\n v36 = v34;\n v37 = 0;\n if (!v35) goto LABEL_48;\n } else {\n v35 = *(uint64_t *)(v32 + 16);\n v36 = 0;\n if (!v35) {\n v38 = *(uint64_t *)(v31 + 16);\n LODWORD(v32) = 1;\n if (!v38) {\n v45 = *(uint64_t *)(v26 + 16);\n LODWORD(v31) = 2;\n if (!v45) goto LABEL_74;\n goto LABEL_59;\n }\n goto LABEL_51;\n }\n }\n v37 = sub_13D0(v35, a2, a3);\n LABEL_48:\n v38 = *(uint64_t *)(v31 + 16);\n LODWORD(v32) = v37 + 1;\n if (v37 < v36) LODWORD(v32) = v36 + 1;\n a3 = 0LL;\n if (!v38) {\n LABEL_56:\n v44 = v32 + 1;\n v45 = *(uint64_t *)(v26 + 16);\n if ((int)a3 >= (int)v32) v44 = a3 + 1;\n v46 = 0;\n LODWORD(v31) = v44;\n if (!v45) {\n LABEL_73:\n if (v46 >= (int)v31) {\n v27 = v46 + 1;\n goto LABEL_36;\n }\n LABEL_74:\n v27 = v31 + 1;\n goto LABEL_36;\n }\n LABEL_59:\n v47 = *(uint64_t *)(v45 + 8);\n if (v47) goto LABEL_60;\n goto LABEL_176;\n }\n LABEL_51:\n v39 = *(uint64_t *)(v38 + 8);\n if (v39) {\n v40 = sub_13D0(v39, a2, a3);\n v41 = *(uint64_t *)(v38 + 16);\n v42 = v40;\n v43 = 0;\n if (!v41) goto LABEL_54;\n } else {\n v41 = *(uint64_t *)(v38 + 16);\n a3 = 1LL;\n v42 = 0;\n if (!v41) goto LABEL_56;\n }\n v43 = sub_13D0(v41, a2, a3);\n LABEL_54:\n a3 = (unsigned int)(v42 + 1);\n if (v43 >= v42) a3 = (unsigned int)(v43 + 1);\n goto LABEL_56;\n }\n LABEL_19:\n v17 = *(uint64_t *)(v15 + 8);\n if (!v17) {\n v20 = *(uint64_t *)(v15 + 16);\n v16 = 1;\n if (!v20) goto LABEL_33;\n goto LABEL_26;\n }\n if (*(uint64_t *)(v17 + 8)) {\n v18 = ((long long (*)(void))sub_13D0)();\n v19 = 0;\n if (!*(uint64_t *)(v17 + 16)) goto LABEL_23;\n } else {\n v18 = 0;\n if (!*(uint64_t *)(v17 + 16)) {\n v20 = *(uint64_t *)(v15 + 16);\n v16 = 2;\n if (!v20) goto LABEL_33;\n LODWORD(v17) = 1;\n goto LABEL_26;\n }\n }\n v19 = ((long long (*)(void))sub_13D0)();\n LABEL_23:\n v20 = *(uint64_t *)(v15 + 16);\n LODWORD(v17) = v19 + 1;\n if (v19 < v18) LODWORD(v17) = v18 + 1;\n a3 = 0LL;\n if (!v20) goto LABEL_31;\n LABEL_26:\n v21 = *(uint64_t *)(v20 + 8);\n if (v21) {\n v22 = sub_13D0(v21, a2, a3);\n v23 = *(uint64_t *)(v20 + 16);\n v24 = v22;\n v25 = 0;\n if (!v23) goto LABEL_29;\n } else {\n v23 = *(uint64_t *)(v20 + 16);\n a3 = 1LL;\n v24 = 0;\n if (!v23) {\n LABEL_31:\n v16 = v17 + 1;\n if ((int)a3 >= (int)v17) v16 = a3 + 1;\n goto LABEL_33;\n }\n }\n v25 = sub_13D0(v23, a2, a3);\n LABEL_29:\n LODWORD(a3) = v24 + 1;\n if (v25 >= v24) LODWORD(a3) = v25 + 1;\n goto LABEL_31;\n }\n LABEL_11:\n if (*(uint64_t *)(v10 + 8)) {\n v12 = ((long long (*)(void))sub_13D0)();\n v13 = 0;\n if (!*(uint64_t *)(v10 + 16)) goto LABEL_14;\n } else {\n v11 = 1;\n v12 = 0;\n if (!*(uint64_t *)(v10 + 16)) goto LABEL_16;\n }\n v13 = ((long long (*)(void))sub_13D0)();\n LABEL_14:\n v14 = v13 < v12;\n v11 = v13 + 1;\n if (v14) v11 = v12 + 1;\n goto LABEL_16;\n }\n v26 = *(uint64_t *)(v4 + 16);\n if (v26) goto LABEL_43;\n v28 = *(uint64_t *)(a1 + 16);\n result = 2LL;\n LODWORD(v4) = 1;\n if (v28) goto LABEL_76;\n } else {\n v28 = *(uint64_t *)(a1 + 16);\n result = 1LL;\n if (v28) goto LABEL_76;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0_part_0(long long a1, long long a2, long long a3) {\n long long v4;\n long long v5;\n long long v6;\n long long v7;\n int v8;\n int v9;\n long long v10;\n int v11;\n int v12;\n int v13;\n bool v14;\n long long v15;\n int v16;\n long long v17;\n int v18;\n int v19;\n long long v20;\n long long v21;\n int v22;\n long long v23;\n int v24;\n int v25;\n long long v26;\n int v27;\n long long v28;\n int v29;\n long long result;\n long long v31;\n long long v32;\n long long v33;\n int v34;\n long long v35;\n int v36;\n int v37;\n long long v38;\n long long v39;\n int v40;\n long long v41;\n int v42;\n int v43;\n int v44;\n long long v45;\n int v46;\n long long v47;\n long long v48;\n int v49;\n long long v50;\n int v51;\n int v52;\n long long v53;\n long long v54;\n int v55;\n long long v56;\n int v57;\n int v58;\n long long v59;\n long long v60;\n long long v61;\n long long v62;\n int v63;\n long long v64;\n int v65;\n int v66;\n long long v67;\n int v68;\n long long v69;\n int v70;\n long long v71;\n int v72;\n int v73;\n long long v74;\n long long v75;\n long long v76;\n int v77;\n long long v78;\n int v79;\n int v80;\n long long v81;\n int v82;\n long long v83;\n int v84;\n long long v85;\n int v86;\n int v87;\n int v88;\n long long v89;\n int v90;\n long long v91;\n long long v92;\n long long v93;\n int v94;\n long long v95;\n int v96;\n int v97;\n long long v98;\n long long v99;\n int v100;\n long long v101;\n int v102;\n int v103;\n int v104;\n long long v105;\n int v106;\n long long v107;\n long long v108;\n int v109;\n long long v110;\n int v111;\n int v112;\n long long v113;\n long long v114;\n int v115;\n long long v116;\n int v117;\n int v118;\n v4 = *(uint64_t *)(a1 + 8);\n if (v4) {\n v5 = *(uint64_t *)(v4 + 8);\n if (v5) {\n v6 = *(uint64_t *)(v5 + 8);\n if (!v6) {\n v15 = *(uint64_t *)(v5 + 16);\n if (!v15) {\n v26 = *(uint64_t *)(v4 + 16);\n LODWORD(v5) = 1;\n if (!v26) {\n v28 = *(uint64_t *)(a1 + 16);\n LODWORD(v4) = 2;\n if (!v28) return (unsigned int)(v4 + 1);\n goto LABEL_76;\n }\n goto LABEL_43;\n }\n goto LABEL_19;\n }\n v7 = *(uint64_t *)(v6 + 8);\n if (!v7) {\n v10 = *(uint64_t *)(v6 + 16);\n if (!v10) {\n v15 = *(uint64_t *)(v5 + 16);\n LODWORD(v6) = 1;\n if (!v15) {\n v26 = *(uint64_t *)(v4 + 16);\n LODWORD(v5) = 2;\n if (!v26) {\n v28 = *(uint64_t *)(a1 + 16);\n LODWORD(v4) = 3;\n if (!v28) return (unsigned int)(v4 + 1);\n goto LABEL_76;\n }\n goto LABEL_43;\n }\n goto LABEL_19;\n }\n goto LABEL_11;\n }\n if (*(uint64_t *)(v7 + 8)) {\n v8 = ((long long (*)(void))func0_part_0)();\n v9 = 0;\n if (!*(uint64_t *)(v7 + 16)) goto LABEL_8;\n } else {\n v8 = 0;\n if (!*(uint64_t *)(v7 + 16)) {\n v10 = *(uint64_t *)(v6 + 16);\n LODWORD(v7) = 1;\n if (!v10) {\n v15 = *(uint64_t *)(v5 + 16);\n LODWORD(v6) = 2;\n if (!v15) {\n v26 = *(uint64_t *)(v4 + 16);\n LODWORD(v5) = 3;\n if (!v26) {\n LABEL_37:\n LODWORD(v4) = v5 + 1;\n LABEL_38:\n v28 = *(uint64_t *)(a1 + 16);\n v29 = 0;\n if (!v28) goto LABEL_39;\n LABEL_76:\n v59 = *(uint64_t *)(v28 + 8);\n if (!v59) {\n v89 = *(uint64_t *)(v28 + 16);\n v29 = 1;\n if (!v89) goto LABEL_39;\n v91 = *(uint64_t *)(v89 + 8);\n if (v91) {\n LABEL_111:\n v92 = *(uint64_t *)(v91 + 8);\n if (!v92) {\n v98 = *(uint64_t *)(v91 + 16);\n if (!v98) {\n v105 = *(uint64_t *)(v89 + 16);\n v90 = 2;\n if (!v105) goto LABEL_142;\n LODWORD(v91) = 1;\n goto LABEL_126;\n }\n goto LABEL_118;\n }\n v93 = *(uint64_t *)(v92 + 8);\n if (v93) {\n v94 = func0_part_0(v93, a2, a3);\n v95 = *(uint64_t *)(v92 + 16);\n v96 = v94;\n v97 = 0;\n if (!v95) goto LABEL_115;\n } else {\n v95 = *(uint64_t *)(v92 + 16);\n v96 = 0;\n if (!v95) {\n v98 = *(uint64_t *)(v91 + 16);\n LODWORD(v92) = 1;\n if (!v98) {\n v105 = *(uint64_t *)(v89 + 16);\n LODWORD(v91) = 2;\n if (!v105) {\n LABEL_141:\n v90 = v91 + 1;\n LABEL_142:\n if (v90 < (int)v59) goto LABEL_143;\n v29 = v90 + 1;\n LABEL_39:\n if (v29 < (int)v4) return (unsigned int)(v4 + 1);\n return (unsigned int)(v29 + 1);\n }\n goto LABEL_126;\n }\n goto LABEL_118;\n }\n }\n v97 = func0_part_0(v95, a2, a3);\n LABEL_115:\n v98 = *(uint64_t *)(v91 + 16);\n LODWORD(v92) = v97 + 1;\n if (v97 < v96) LODWORD(v92) = v96 + 1;\n a3 = 0LL;\n if (!v98) {\n LABEL_123:\n v104 = v92 + 1;\n v105 = *(uint64_t *)(v89 + 16);\n if ((int)a3 >= (int)v92) v104 = a3 + 1;\n v106 = 0;\n LODWORD(v91) = v104;\n if (!v105) {\n LABEL_140:\n if (v106 >= (int)v91) {\n v90 = v106 + 1;\n goto LABEL_142;\n }\n goto LABEL_141;\n }\n LABEL_126:\n v107 = *(uint64_t *)(v105 + 8);\n if (v107) goto LABEL_127;\n goto LABEL_149;\n }\n LABEL_118:\n v99 = *(uint64_t *)(v98 + 8);\n if (v99) {\n v100 = func0_part_0(v99, a2, a3);\n v101 = *(uint64_t *)(v98 + 16);\n v102 = v100;\n v103 = 0;\n if (!v101) goto LABEL_121;\n } else {\n v101 = *(uint64_t *)(v98 + 16);\n a3 = 1LL;\n v102 = 0;\n if (!v101) goto LABEL_123;\n }\n v103 = func0_part_0(v101, a2, a3);\n LABEL_121:\n a3 = (unsigned int)(v102 + 1);\n if (v103 >= v102) a3 = (unsigned int)(v103 + 1);\n goto LABEL_123;\n }\n LABEL_147:\n v105 = *(uint64_t *)(v89 + 16);\n v90 = 1;\n if (!v105) goto LABEL_142;\n v107 = *(uint64_t *)(v105 + 8);\n if (v107) {\n LABEL_127:\n v108 = *(uint64_t *)(v107 + 8);\n if (v108) {\n v109 = func0_part_0(v108, a2, a3);\n v110 = *(uint64_t *)(v107 + 16);\n v111 = v109;\n v112 = 0;\n if (!v110) goto LABEL_130;\n } else {\n v110 = *(uint64_t *)(v107 + 16);\n v111 = 0;\n if (!v110) {\n v113 = *(uint64_t *)(v105 + 16);\n v106 = 2;\n if (!v113) goto LABEL_140;\n LODWORD(v107) = 1;\n goto LABEL_133;\n }\n }\n v112 = func0_part_0(v110, a2, a3);\n LABEL_130:\n v113 = *(uint64_t *)(v105 + 16);\n LODWORD(v107) = v112 + 1;\n if (v112 < v111) LODWORD(v107) = v111 + 1;\n a3 = 0LL;\n if (!v113) goto LABEL_138;\n LABEL_133:\n v114 = *(uint64_t *)(v113 + 8);\n if (v114) {\n v115 = func0_part_0(v114, a2, a3);\n v116 = *(uint64_t *)(v113 + 16);\n v117 = v115;\n v118 = 0;\n if (!v116) goto LABEL_136;\n } else {\n v116 = *(uint64_t *)(v113 + 16);\n a3 = 1LL;\n v117 = 0;\n if (!v116) {\n LABEL_138:\n v106 = v107 + 1;\n if ((int)a3 >= (int)v107) v106 = a3 + 1;\n goto LABEL_140;\n }\n }\n v118 = func0_part_0(v116, a2, a3);\n LABEL_136:\n LODWORD(a3) = v117 + 1;\n if (v118 >= v117) LODWORD(a3) = v118 + 1;\n goto LABEL_138;\n }\n LABEL_149:\n v113 = *(uint64_t *)(v105 + 16);\n v106 = 1;\n if (!v113) goto LABEL_140;\n goto LABEL_133;\n }\n v60 = *(uint64_t *)(v59 + 8);\n if (!v60) {\n v74 = *(uint64_t *)(v59 + 16);\n if (!v74) {\n v89 = *(uint64_t *)(v28 + 16);\n v29 = 2;\n if (!v89) goto LABEL_39;\n LODWORD(v59) = 1;\n goto LABEL_110;\n }\n goto LABEL_93;\n }\n v61 = *(uint64_t *)(v60 + 8);\n if (v61) {\n v62 = *(uint64_t *)(v61 + 8);\n if (v62) {\n v63 = func0_part_0(v62, a2, a3);\n v64 = *(uint64_t *)(v61 + 16);\n v65 = v63;\n v66 = 0;\n if (!v64) goto LABEL_82;\n goto LABEL_81;\n }\n v64 = *(uint64_t *)(v61 + 16);\n v65 = 0;\n if (v64) {\n LABEL_81:\n v66 = func0_part_0(v64, a2, a3);\n LABEL_82:\n v67 = *(uint64_t *)(v60 + 16);\n LODWORD(v61) = v66 + 1;\n a3 = (unsigned int)(v65 + 1);\n if (v66 < v65) LODWORD(v61) = v65 + 1;\n v68 = 0;\n if (!v67) {\n LABEL_90:\n v74 = *(uint64_t *)(v59 + 16);\n LODWORD(v60) = v68 + 1;\n if (v68 < (int)v61) LODWORD(v60) = v61 + 1;\n a3 = 0LL;\n if (!v74) {\n LABEL_107:\n v88 = v60 + 1;\n v14 = (int)a3 < (int)v60;\n v89 = *(uint64_t *)(v28 + 16);\n if (!v14) v88 = a3 + 1;\n v90 = 0;\n LODWORD(v59) = v88;\n if (!v89) goto LABEL_142;\n LABEL_110:\n v91 = *(uint64_t *)(v89 + 8);\n if (v91) goto LABEL_111;\n goto LABEL_147;\n }\n LABEL_93:\n v75 = *(uint64_t *)(v74 + 8);\n if (!v75) {\n v81 = *(uint64_t *)(v74 + 16);\n a3 = 1LL;\n if (!v81) goto LABEL_107;\n goto LABEL_100;\n }\n v76 = *(uint64_t *)(v75 + 8);\n if (v76) {\n v77 = func0_part_0(v76, a2, a3);\n v78 = *(uint64_t *)(v75 + 16);\n v79 = v77;\n v80 = 0;\n if (!v78) goto LABEL_97;\n } else {\n v78 = *(uint64_t *)(v75 + 16);\n v79 = 0;\n if (!v78) {\n v81 = *(uint64_t *)(v74 + 16);\n a3 = 2LL;\n if (!v81) goto LABEL_107;\n LODWORD(v75) = 1;\n goto LABEL_100;\n }\n }\n v80 = func0_part_0(v78, a2, a3);\n LABEL_97:\n v81 = *(uint64_t *)(v74 + 16);\n LODWORD(v75) = v80 + 1;\n a3 = (unsigned int)(v79 + 1);\n if (v80 < v79) LODWORD(v75) = v79 + 1;\n v82 = 0;\n if (!v81) goto LABEL_105;\n LABEL_100:\n v83 = *(uint64_t *)(v81 + 8);\n if (v83) {\n v84 = func0_part_0(v83, a2, a3);\n v85 = *(uint64_t *)(v81 + 16);\n v86 = v84;\n v87 = 0;\n if (!v85) goto LABEL_103;\n } else {\n v85 = *(uint64_t *)(v81 + 16);\n v82 = 1;\n v86 = 0;\n if (!v85) {\n LABEL_105:\n a3 = (unsigned int)(v75 + 1);\n if (v82 >= (int)v75) a3 = (unsigned int)(v82 + 1);\n goto LABEL_107;\n }\n }\n v87 = func0_part_0(v85, a2, a3);\n LABEL_103:\n v14 = v87 < v86;\n v82 = v87 + 1;\n if (v14) v82 = v86 + 1;\n goto LABEL_105;\n }\n LABEL_85:\n v69 = *(uint64_t *)(v67 + 8);\n if (v69) {\n v70 = func0_part_0(v69, a2, a3);\n v71 = *(uint64_t *)(v67 + 16);\n v72 = v70;\n v73 = 0;\n if (!v71) goto LABEL_88;\n } else {\n v71 = *(uint64_t *)(v67 + 16);\n v68 = 1;\n v72 = 0;\n if (!v71) goto LABEL_90;\n }\n v73 = func0_part_0(v71, a2, a3);\n LABEL_88:\n v14 = v73 < v72;\n v68 = v73 + 1;\n if (v14) v68 = v72 + 1;\n goto LABEL_90;\n }\n v67 = *(uint64_t *)(v60 + 16);\n LODWORD(v61) = 1;\n if (v67) goto LABEL_85;\n v74 = *(uint64_t *)(v59 + 16);\n LODWORD(v60) = 2;\n if (v74) goto LABEL_93;\n v89 = *(uint64_t *)(v28 + 16);\n LODWORD(v59) = 3;\n if (v89) goto LABEL_110;\n } else {\n v67 = *(uint64_t *)(v60 + 16);\n if (v67) goto LABEL_85;\n v74 = *(uint64_t *)(v59 + 16);\n LODWORD(v60) = 1;\n if (v74) goto LABEL_93;\n v89 = *(uint64_t *)(v28 + 16);\n LODWORD(v59) = 2;\n if (v89) goto LABEL_110;\n }\n LABEL_143:\n v29 = v59 + 1;\n if ((int)v59 + 1 < (int)v4) return (unsigned int)(v4 + 1);\n return (unsigned int)(v29 + 1);\n }\n goto LABEL_43;\n }\n goto LABEL_19;\n }\n goto LABEL_11;\n }\n }\n v9 = ((long long (*)(void))func0_part_0)();\n LABEL_8:\n v10 = *(uint64_t *)(v6 + 16);\n LODWORD(v7) = v9 + 1;\n if (v9 < v8) LODWORD(v7) = v8 + 1;\n v11 = 0;\n if (!v10) {\n LABEL_16:\n v15 = *(uint64_t *)(v5 + 16);\n LODWORD(v6) = v11 + 1;\n a3 = (unsigned int)(v7 + 1);\n if (v11 < (int)v7) LODWORD(v6) = v7 + 1;\n v16 = 0;\n if (!v15) {\n LABEL_33:\n a3 = (unsigned int)(v6 + 1);\n LODWORD(v5) = v16 + 1;\n v14 = v16 < (int)v6;\n v26 = *(uint64_t *)(v4 + 16);\n if (v14) LODWORD(v5) = a3;\n v27 = 0;\n if (!v26) {\n LABEL_36:\n LODWORD(v4) = v27 + 1;\n if (v27 >= (int)v5) goto LABEL_38;\n goto LABEL_37;\n }\n LABEL_43:\n v31 = *(uint64_t *)(v26 + 8);\n if (!v31) {\n v45 = *(uint64_t *)(v26 + 16);\n v27 = 1;\n if (!v45) goto LABEL_36;\n v47 = *(uint64_t *)(v45 + 8);\n if (v47) {\n LABEL_60:\n v48 = *(uint64_t *)(v47 + 8);\n if (v48) {\n v49 = func0_part_0(v48, a2, a3);\n v50 = *(uint64_t *)(v47 + 16);\n v51 = v49;\n v52 = 0;\n if (!v50) goto LABEL_63;\n } else {\n v50 = *(uint64_t *)(v47 + 16);\n v51 = 0;\n if (!v50) {\n v53 = *(uint64_t *)(v45 + 16);\n v46 = 2;\n if (!v53) goto LABEL_73;\n LODWORD(v47) = 1;\n goto LABEL_66;\n }\n }\n v52 = func0_part_0(v50, a2, a3);\n LABEL_63:\n v53 = *(uint64_t *)(v45 + 16);\n LODWORD(v47) = v52 + 1;\n if (v52 < v51) LODWORD(v47) = v51 + 1;\n a3 = 0LL;\n if (!v53) goto LABEL_71;\n LABEL_66:\n v54 = *(uint64_t *)(v53 + 8);\n if (v54) {\n v55 = func0_part_0(v54, a2, a3);\n v56 = *(uint64_t *)(v53 + 16);\n v57 = v55;\n v58 = 0;\n if (!v56) goto LABEL_69;\n } else {\n v56 = *(uint64_t *)(v53 + 16);\n a3 = 1LL;\n v57 = 0;\n if (!v56) {\n LABEL_71:\n v46 = v47 + 1;\n if ((int)a3 >= (int)v47) v46 = a3 + 1;\n goto LABEL_73;\n }\n }\n v58 = func0_part_0(v56, a2, a3);\n LABEL_69:\n a3 = (unsigned int)(v57 + 1);\n if (v58 >= v57) a3 = (unsigned int)(v58 + 1);\n goto LABEL_71;\n }\n LABEL_176:\n v53 = *(uint64_t *)(v45 + 16);\n v46 = 1;\n if (!v53) goto LABEL_73;\n goto LABEL_66;\n }\n v32 = *(uint64_t *)(v31 + 8);\n if (!v32) {\n v38 = *(uint64_t *)(v31 + 16);\n if (!v38) {\n v45 = *(uint64_t *)(v26 + 16);\n v27 = 2;\n if (!v45) goto LABEL_36;\n LODWORD(v31) = 1;\n goto LABEL_59;\n }\n goto LABEL_51;\n }\n v33 = *(uint64_t *)(v32 + 8);\n if (v33) {\n v34 = func0_part_0(v33, a2, a3);\n v35 = *(uint64_t *)(v32 + 16);\n v36 = v34;\n v37 = 0;\n if (!v35) goto LABEL_48;\n } else {\n v35 = *(uint64_t *)(v32 + 16);\n v36 = 0;\n if (!v35) {\n v38 = *(uint64_t *)(v31 + 16);\n LODWORD(v32) = 1;\n if (!v38) {\n v45 = *(uint64_t *)(v26 + 16);\n LODWORD(v31) = 2;\n if (!v45) goto LABEL_74;\n goto LABEL_59;\n }\n goto LABEL_51;\n }\n }\n v37 = func0_part_0(v35, a2, a3);\n LABEL_48:\n v38 = *(uint64_t *)(v31 + 16);\n LODWORD(v32) = v37 + 1;\n if (v37 < v36) LODWORD(v32) = v36 + 1;\n a3 = 0LL;\n if (!v38) {\n LABEL_56:\n v44 = v32 + 1;\n v45 = *(uint64_t *)(v26 + 16);\n if ((int)a3 >= (int)v32) v44 = a3 + 1;\n v46 = 0;\n LODWORD(v31) = v44;\n if (!v45) {\n LABEL_73:\n if (v46 >= (int)v31) {\n v27 = v46 + 1;\n goto LABEL_36;\n }\n LABEL_74:\n v27 = v31 + 1;\n goto LABEL_36;\n }\n LABEL_59:\n v47 = *(uint64_t *)(v45 + 8);\n if (v47) goto LABEL_60;\n goto LABEL_176;\n }\n LABEL_51:\n v39 = *(uint64_t *)(v38 + 8);\n if (v39) {\n v40 = func0_part_0(v39, a2, a3);\n v41 = *(uint64_t *)(v38 + 16);\n v42 = v40;\n v43 = 0;\n if (!v41) goto LABEL_54;\n } else {\n v41 = *(uint64_t *)(v38 + 16);\n a3 = 1LL;\n v42 = 0;\n if (!v41) goto LABEL_56;\n }\n v43 = func0_part_0(v41, a2, a3);\n LABEL_54:\n a3 = (unsigned int)(v42 + 1);\n if (v43 >= v42) a3 = (unsigned int)(v43 + 1);\n goto LABEL_56;\n }\n LABEL_19:\n v17 = *(uint64_t *)(v15 + 8);\n if (!v17) {\n v20 = *(uint64_t *)(v15 + 16);\n v16 = 1;\n if (!v20) goto LABEL_33;\n goto LABEL_26;\n }\n if (*(uint64_t *)(v17 + 8)) {\n v18 = ((long long (*)(void))func0_part_0)();\n v19 = 0;\n if (!*(uint64_t *)(v17 + 16)) goto LABEL_23;\n } else {\n v18 = 0;\n if (!*(uint64_t *)(v17 + 16)) {\n v20 = *(uint64_t *)(v15 + 16);\n v16 = 2;\n if (!v20) goto LABEL_33;\n LODWORD(v17) = 1;\n goto LABEL_26;\n }\n }\n v19 = ((long long (*)(void))func0_part_0)();\n LABEL_23:\n v20 = *(uint64_t *)(v15 + 16);\n LODWORD(v17) = v19 + 1;\n if (v19 < v18) LODWORD(v17) = v18 + 1;\n a3 = 0LL;\n if (!v20) goto LABEL_31;\n LABEL_26:\n v21 = *(uint64_t *)(v20 + 8);\n if (v21) {\n v22 = func0_part_0(v21, a2, a3);\n v23 = *(uint64_t *)(v20 + 16);\n v24 = v22;\n v25 = 0;\n if (!v23) goto LABEL_29;\n } else {\n v23 = *(uint64_t *)(v20 + 16);\n a3 = 1LL;\n v24 = 0;\n if (!v23) {\n LABEL_31:\n v16 = v17 + 1;\n if ((int)a3 >= (int)v17) v16 = a3 + 1;\n goto LABEL_33;\n }\n }\n v25 = func0_part_0(v23, a2, a3);\n LABEL_29:\n LODWORD(a3) = v24 + 1;\n if (v25 >= v24) LODWORD(a3) = v25 + 1;\n goto LABEL_31;\n }\n LABEL_11:\n if (*(uint64_t *)(v10 + 8)) {\n v12 = ((long long (*)(void))func0_part_0)();\n v13 = 0;\n if (!*(uint64_t *)(v10 + 16)) goto LABEL_14;\n } else {\n v11 = 1;\n v12 = 0;\n if (!*(uint64_t *)(v10 + 16)) goto LABEL_16;\n }\n v13 = ((long long (*)(void))func0_part_0)();\n LABEL_14:\n v14 = v13 < v12;\n v11 = v13 + 1;\n if (v14) v11 = v12 + 1;\n goto LABEL_16;\n }\n v26 = *(uint64_t *)(v4 + 16);\n if (v26) goto LABEL_43;\n v28 = *(uint64_t *)(a1 + 16);\n result = 2LL;\n LODWORD(v4) = 1;\n if (v28) goto LABEL_76;\n } else {\n v28 = *(uint64_t *)(a1 + 16);\n result = 1LL;\n if (v28) goto LABEL_76;\n }\n return result;\n}" + }, + { + "index": 928, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* dt) {\n static char new_format[11];\n int year, month, day;\n sscanf(dt, \"%d-%d-%d\", &year, &month, &day);\n sprintf(new_format, \"%02d-%02d-%d\", day, month, year);\n return new_format;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"2026-01-02\"), \"02-01-2026\") == 0);\n\n assert(strcmp(func0(\"2021-01-04\"), \"04-01-2021\") == 0);\n\n assert(strcmp(func0(\"2030-06-06\"), \"06-06-2030\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x28(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea -0xc(%rbp),%rsi\nlea -0x10(%rbp),%rcx\nlea -0x14(%rbp),%rdx\nmov -0x28(%rbp),%rax\nmov %rsi,%r8\nlea 0xe06(%rip),%rsi\nmov %rax,%rdi\nmov $0x0,%eax\ncallq 10c0 <__isoc99_sscanf@plt>\nmov -0x14(%rbp),%ecx\nmov -0x10(%rbp),%edx\nmov -0xc(%rbp),%eax\nmov %ecx,%r8d\nmov %edx,%ecx\nmov %eax,%edx\nlea 0xdeb(%rip),%rsi\nlea 0x2deb(%rip),%rdi\nmov $0x0,%eax\ncallq 10d0 \nlea 0x2dda(%rip),%rax\nmov -0x8(%rbp),%rdi\nxor %fs:0x28,%rdi\nje 1252 \ncallq 1090 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rsi, [rbp+var_C]\nlea rcx, [rbp+var_10]\nlea rdx, [rbp+var_14]\nmov rax, [rbp+var_28]\nmov r8, rsi\nlea rsi, aDDD; \"%d-%d-%d\"\nmov rdi, rax\nmov eax, 0\ncall ___isoc99_sscanf\nmov ecx, [rbp+var_14]\nmov edx, [rbp+var_10]\nmov eax, [rbp+var_C]\nmov r8d, ecx\nmov ecx, edx\nmov edx, eax\nlea rax, format; \"%02d-%02d-%d\"\nmov rsi, rax; format\nlea rax, new_format_1\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rax, new_format_1\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1258\ncall ___stack_chk_fail\nlocret_1258:\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1)\n{\n int v2; // [rsp+1Ch] [rbp-14h] BYREF\n int v3; // [rsp+20h] [rbp-10h] BYREF\n int v4; // [rsp+24h] [rbp-Ch] BYREF\n unsigned __int64 v5; // [rsp+28h] [rbp-8h]\n\n v5 = __readfsqword(0x28u);\n __isoc99_sscanf(a1, \"%d-%d-%d\", &v2, &v3, &v4);\n sprintf(new_format_1, \"%02d-%02d-%d\", v4, v3, v2);\n return new_format_1;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rsi, [rbp+var_C]\nlea rcx, [rbp+var_10]\nlea rdx, [rbp+var_14]\nmov rax, [rbp+var_28]\nmov r8, rsi\nlea rsi, aDDD; \"%d-%d-%d\"\nmov rdi, rax\nmov eax, 0\ncall ___isoc99_sscanf\nmov ecx, [rbp+var_14]\nmov edx, [rbp+var_10]\nmov eax, [rbp+var_C]\nmov r8d, ecx\nmov ecx, edx\nmov edx, eax\nlea rax, format; \"%02d-%02d-%d\"\nmov rsi, rax; format\nlea rax, s\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rax, s\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1258\ncall ___stack_chk_fail\nlocret_1258:\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11C9(__int64 a1)\n{\n int v2; // [rsp+1Ch] [rbp-14h] BYREF\n int v3; // [rsp+20h] [rbp-10h] BYREF\n int v4; // [rsp+24h] [rbp-Ch] BYREF\n unsigned __int64 v5; // [rsp+28h] [rbp-8h]\n\n v5 = __readfsqword(0x28u);\n __isoc99_sscanf(a1, \"%d-%d-%d\", &v2, &v3, &v4);\n sprintf(s, \"%02d-%02d-%d\", v4, v3, v2);\n return s;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char* sub_11C9(long long a1) {\n int v2;\n int v3;\n int v4;\n unsigned long long v5;\n v5 = __readfsqword(40u);\n __isoc99_sscanf(a1, \"%d-%d-%d\", &v2, &v3, &v4);\n sprintf(s, \"%02d-%02d-%d\", v4, v3, v2);\n return s;\n}", + "ida_pseudo_norm": "char* func0(long long a1) {\n int v2;\n int v3;\n int v4;\n unsigned long long v5;\n v5 = __readfsqword(40u);\n __isoc99_sscanf(a1, \"%d-%d-%d\", &v2, &v3, &v4);\n sprintf(new_format_1, \"%02d-%02d-%d\", v4, v3, v2);\n return new_format_1;\n}" + }, + { + "index": 928, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* dt) {\n static char new_format[11];\n int year, month, day;\n sscanf(dt, \"%d-%d-%d\", &year, &month, &day);\n sprintf(new_format, \"%02d-%02d-%d\", day, month, year);\n return new_format;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"2026-01-02\"), \"02-01-2026\") == 0);\n\n assert(strcmp(func0(\"2021-01-04\"), \"04-01-2021\") == 0);\n\n assert(strcmp(func0(\"2030-06-06\"), \"06-06-2030\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nsub $0x20,%rsp\nmov $0x28,%ebx\nmov %fs:(%rbx),%rax\nmov %rax,0x18(%rsp)\nxor %eax,%eax\nlea 0x10(%rsp),%rcx\nlea 0xc(%rsp),%rdx\nlea 0x14(%rsp),%r8\nlea 0xe2c(%rip),%rsi\ncallq 10a0 <__isoc99_sscanf@plt>\nsub $0x8,%rsp\nmov 0x14(%rsp),%eax\npush %rax\nmov 0x20(%rsp),%r9d\nmov 0x24(%rsp),%r8d\nlea 0xe16(%rip),%rcx\nmov $0xb,%edx\nmov $0x1,%esi\nlea 0x2e10(%rip),%rdi\nmov $0x0,%eax\ncallq 10b0 <__sprintf_chk@plt>\nadd $0x10,%rsp\nmov 0x18(%rsp),%rax\nxor %fs:(%rbx),%rax\njne 122e \nlea 0x2df0(%rip),%rax\nadd $0x20,%rsp\npop %rbx\nretq\ncallq 1080 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbx\nsub rsp, 20h\nmov rax, fs:28h\nmov [rsp+28h+var_10], rax\nxor eax, eax\nlea rcx, [rsp+28h+var_18]\nlea rdx, [rsp+28h+var_1C]\nlea r8, [rsp+28h+var_14]\nlea rsi, aDDD; \"%d-%d-%d\"\ncall ___isoc99_sscanf\nsub rsp, 8\nmov eax, [rsp+30h+var_1C]\npush rax\nmov r9d, [rsp+38h+var_18]\nmov r8d, [rsp+38h+var_14]\nlea rcx, a02d02dD; \"%02d-%02d-%d\"\nmov edx, 0Bh\nmov esi, 2\nlea rbx, new_format_1\nmov rdi, rbx\nmov eax, 0\ncall ___sprintf_chk\nadd rsp, 10h\nmov rax, [rsp+28h+var_10]\nsub rax, fs:28h\njnz short loc_1252\nmov rax, rbx\nadd rsp, 20h\npop rbx\nretn\nloc_1252:\ncall ___stack_chk_fail", + "ida_pseudo": "void *__fastcall func0(__int64 a1)\n{\n int v2; // [rsp+Ch] [rbp-1Ch] BYREF\n int v3; // [rsp+10h] [rbp-18h] BYREF\n int v4; // [rsp+14h] [rbp-14h] BYREF\n unsigned __int64 v5; // [rsp+18h] [rbp-10h]\n\n v5 = __readfsqword(0x28u);\n __isoc99_sscanf(a1, \"%d-%d-%d\", &v2, &v3, &v4);\n __sprintf_chk(&new_format_1, 2LL, 11LL, \"%02d-%02d-%d\", v4, v3, v2);\n return &new_format_1;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbx\nsub rsp, 20h\nmov rax, fs:28h\nmov [rsp+28h+var_10], rax\nxor eax, eax\nlea rcx, [rsp+28h+var_18]\nlea rdx, [rsp+28h+var_1C]\nlea r8, [rsp+28h+var_14]\nlea rsi, aDDD; \"%d-%d-%d\"\ncall ___isoc99_sscanf\nsub rsp, 8\nmov eax, [rsp+30h+var_1C]\npush rax\nmov r9d, [rsp+38h+var_18]\nmov r8d, [rsp+38h+var_14]\nlea rcx, a02d02dD; \"%02d-%02d-%d\"\nmov edx, 0Bh\nmov esi, 2\nlea rbx, unk_4018\nmov rdi, rbx\nmov eax, 0\ncall ___sprintf_chk\nadd rsp, 10h\nmov rax, [rsp+28h+var_10]\nsub rax, fs:28h\njnz short loc_1252\nmov rax, rbx\nadd rsp, 20h\npop rbx\nretn\nloc_1252:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "void *__fastcall sub_11C9(__int64 a1)\n{\n int v2; // [rsp+Ch] [rbp-1Ch] BYREF\n int v3; // [rsp+10h] [rbp-18h] BYREF\n int v4; // [rsp+14h] [rbp-14h] BYREF\n unsigned __int64 v5; // [rsp+18h] [rbp-10h]\n\n v5 = __readfsqword(0x28u);\n __isoc99_sscanf(a1, \"%d-%d-%d\", &v2, &v3, &v4);\n __sprintf_chk(&unk_4018, 2LL, 11LL, \"%02d-%02d-%d\", v4, v3, v2);\n return &unk_4018;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void* sub_11C9(long long a1) {\n int v2;\n int v3;\n int v4;\n unsigned long long v5;\n v5 = __readfsqword(40u);\n __isoc99_sscanf(a1, \"%d-%d-%d\", &v2, &v3, &v4);\n __sprintf_chk(&unk_4018, 2LL, 11LL, \"%02d-%02d-%d\", v4, v3, v2);\n return &unk_4018;\n}", + "ida_pseudo_norm": "void* func0(long long a1) {\n int v2;\n int v3;\n int v4;\n unsigned long long v5;\n v5 = __readfsqword(40u);\n __isoc99_sscanf(a1, \"%d-%d-%d\", &v2, &v3, &v4);\n __sprintf_chk(&new_format_1, 2LL, 11LL, \"%02d-%02d-%d\", v4, v3, v2);\n return &new_format_1;\n}" + }, + { + "index": 928, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* dt) {\n static char new_format[11];\n int year, month, day;\n sscanf(dt, \"%d-%d-%d\", &year, &month, &day);\n sprintf(new_format, \"%02d-%02d-%d\", day, month, year);\n return new_format;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"2026-01-02\"), \"02-01-2026\") == 0);\n\n assert(strcmp(func0(\"2021-01-04\"), \"04-01-2021\") == 0);\n\n assert(strcmp(func0(\"2030-06-06\"), \"06-06-2030\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x28,%rsp\nlea 0xd65(%rip),%rsi\nmov %fs:0x28,%rax\nmov %rax,0x18(%rsp)\nxor %eax,%eax\nlea 0x10(%rsp),%rcx\nlea 0xc(%rsp),%rdx\nlea 0x14(%rsp),%r8\ncallq 10a0 <__isoc99_sscanf@plt>\nsub $0x8,%rsp\nmov $0xb,%edx\nlea 0xd3a(%rip),%rcx\nmov 0x14(%rsp),%eax\nmov $0x1,%esi\nlea 0x2d35(%rip),%rdi\npush %rax\nmov 0x20(%rsp),%r9d\nxor %eax,%eax\nmov 0x24(%rsp),%r8d\ncallq 10b0 <__sprintf_chk@plt>\npop %rax\npop %rdx\nmov 0x18(%rsp),%rax\nxor %fs:0x28,%rax\njne 1313 \nlea 0x2d0a(%rip),%rax\nadd $0x28,%rsp\nretq\ncallq 1080 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nlea rsi, aDDD; \"%d-%d-%d\"\nlea rbx, new_format_1\nsub rsp, 20h\nmov rax, fs:28h\nmov [rsp+28h+var_10], rax\nxor eax, eax\nlea rcx, [rsp+28h+var_18]\nlea rdx, [rsp+28h+var_1C]\nlea r8, [rsp+28h+var_14]\ncall ___isoc99_sscanf\nsub rsp, 8\nmov edx, 0Bh\nmov rdi, rbx\nmov eax, [rsp+30h+var_1C]\nlea rcx, a02d02dD; \"%02d-%02d-%d\"\nmov esi, 2\npush rax\nmov r9d, [rsp+38h+var_18]\nxor eax, eax\nmov r8d, [rsp+38h+var_14]\ncall ___sprintf_chk\npop rax\npop rdx\nmov rax, [rsp+28h+var_10]\nsub rax, fs:28h\njnz short loc_1324\nadd rsp, 20h\nmov rax, rbx\npop rbx\nretn\nloc_1324:\ncall ___stack_chk_fail", + "ida_pseudo": "void *__fastcall func0(__int64 a1)\n{\n int v2; // [rsp+Ch] [rbp-1Ch] BYREF\n int v3; // [rsp+10h] [rbp-18h] BYREF\n int v4; // [rsp+14h] [rbp-14h] BYREF\n unsigned __int64 v5; // [rsp+18h] [rbp-10h]\n\n v5 = __readfsqword(0x28u);\n __isoc99_sscanf(a1, \"%d-%d-%d\", &v2, &v3, &v4);\n __sprintf_chk(&new_format_1, 2LL, 11LL, \"%02d-%02d-%d\", v4, v3, v2);\n return &new_format_1;\n}", + "ida_strip_asm": "sub_12A0:\nendbr64\npush rbx\nlea rsi, aDDD; \"%d-%d-%d\"\nlea rbx, unk_4018\nsub rsp, 20h\nmov rax, fs:28h\nmov [rsp+28h+var_10], rax\nxor eax, eax\nlea rcx, [rsp+28h+var_18]\nlea rdx, [rsp+28h+var_1C]\nlea r8, [rsp+28h+var_14]\ncall ___isoc99_sscanf\nsub rsp, 8\nmov edx, 0Bh\nmov rdi, rbx\nmov eax, [rsp+30h+var_1C]\nlea rcx, a02d02dD; \"%02d-%02d-%d\"\nmov esi, 2\npush rax\nmov r9d, [rsp+38h+var_18]\nxor eax, eax\nmov r8d, [rsp+38h+var_14]\ncall ___sprintf_chk\npop rax\npop rdx\nmov rax, [rsp+28h+var_10]\nsub rax, fs:28h\njnz short loc_1324\nadd rsp, 20h\nmov rax, rbx\npop rbx\nretn\nloc_1324:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "void *__fastcall sub_12A0(__int64 a1)\n{\n int v2; // [rsp+Ch] [rbp-1Ch] BYREF\n int v3; // [rsp+10h] [rbp-18h] BYREF\n int v4; // [rsp+14h] [rbp-14h] BYREF\n unsigned __int64 v5; // [rsp+18h] [rbp-10h]\n\n v5 = __readfsqword(0x28u);\n __isoc99_sscanf(a1, \"%d-%d-%d\", &v2, &v3, &v4);\n __sprintf_chk(&unk_4018, 2LL, 11LL, \"%02d-%02d-%d\", v4, v3, v2);\n return &unk_4018;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void* sub_12A0(long long a1) {\n int v2;\n int v3;\n int v4;\n unsigned long long v5;\n v5 = __readfsqword(40u);\n __isoc99_sscanf(a1, \"%d-%d-%d\", &v2, &v3, &v4);\n __sprintf_chk(&unk_4018, 2LL, 11LL, \"%02d-%02d-%d\", v4, v3, v2);\n return &unk_4018;\n}", + "ida_pseudo_norm": "void* func0(long long a1) {\n int v2;\n int v3;\n int v4;\n unsigned long long v5;\n v5 = __readfsqword(40u);\n __isoc99_sscanf(a1, \"%d-%d-%d\", &v2, &v3, &v4);\n __sprintf_chk(&new_format_1, 2LL, 11LL, \"%02d-%02d-%d\", v4, v3, v2);\n return &new_format_1;\n}" + }, + { + "index": 928, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* dt) {\n static char new_format[11];\n int year, month, day;\n sscanf(dt, \"%d-%d-%d\", &year, &month, &day);\n sprintf(new_format, \"%02d-%02d-%d\", day, month, year);\n return new_format;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"2026-01-02\"), \"02-01-2026\") == 0);\n\n assert(strcmp(func0(\"2021-01-04\"), \"04-01-2021\") == 0);\n\n assert(strcmp(func0(\"2030-06-06\"), \"06-06-2030\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x28,%rsp\nlea 0xd65(%rip),%rsi\nmov %fs:0x28,%rax\nmov %rax,0x18(%rsp)\nxor %eax,%eax\nlea 0x10(%rsp),%rcx\nlea 0xc(%rsp),%rdx\nlea 0x14(%rsp),%r8\ncallq 10a0 <__isoc99_sscanf@plt>\nsub $0x8,%rsp\nmov $0xb,%edx\nlea 0xd3a(%rip),%rcx\nmov 0x14(%rsp),%eax\nmov $0x1,%esi\nlea 0x2d35(%rip),%rdi\npush %rax\nmov 0x20(%rsp),%r9d\nxor %eax,%eax\nmov 0x24(%rsp),%r8d\ncallq 10b0 <__sprintf_chk@plt>\npop %rax\npop %rdx\nmov 0x18(%rsp),%rax\nxor %fs:0x28,%rax\njne 1313 \nlea 0x2d0a(%rip),%rax\nadd $0x28,%rsp\nretq\ncallq 1080 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nlea rsi, aDDD; \"%d-%d-%d\"\nlea rbx, new_format_1\nsub rsp, 20h\nmov rax, fs:28h\nmov [rsp+28h+var_10], rax\nxor eax, eax\nlea rcx, [rsp+28h+var_18]\nlea rdx, [rsp+28h+var_1C]\nlea r8, [rsp+28h+var_14]\ncall ___isoc99_sscanf\nsub rsp, 8\nmov edx, 0Bh\nmov rdi, rbx\nmov eax, [rsp+30h+var_1C]\nlea rcx, a02d02dD; \"%02d-%02d-%d\"\nmov esi, 2\npush rax\nmov r9d, [rsp+38h+var_18]\nxor eax, eax\nmov r8d, [rsp+38h+var_14]\ncall ___sprintf_chk\npop rax\npop rdx\nmov rax, [rsp+28h+var_10]\nsub rax, fs:28h\njnz short loc_1324\nadd rsp, 20h\nmov rax, rbx\npop rbx\nretn\nloc_1324:\ncall ___stack_chk_fail", + "ida_pseudo": "void *__fastcall func0(__int64 a1)\n{\n int v2; // [rsp+Ch] [rbp-1Ch] BYREF\n int v3; // [rsp+10h] [rbp-18h] BYREF\n int v4; // [rsp+14h] [rbp-14h] BYREF\n unsigned __int64 v5; // [rsp+18h] [rbp-10h]\n\n v5 = __readfsqword(0x28u);\n __isoc99_sscanf(a1, \"%d-%d-%d\", &v2, &v3, &v4);\n __sprintf_chk(&new_format_1, 2LL, 11LL, \"%02d-%02d-%d\", v4, v3, v2);\n return &new_format_1;\n}", + "ida_strip_asm": "sub_12A0:\nendbr64\npush rbx\nlea rsi, aDDD; \"%d-%d-%d\"\nlea rbx, unk_4018\nsub rsp, 20h\nmov rax, fs:28h\nmov [rsp+28h+var_10], rax\nxor eax, eax\nlea rcx, [rsp+28h+var_18]\nlea rdx, [rsp+28h+var_1C]\nlea r8, [rsp+28h+var_14]\ncall ___isoc99_sscanf\nsub rsp, 8\nmov edx, 0Bh\nmov rdi, rbx\nmov eax, [rsp+30h+var_1C]\nlea rcx, a02d02dD; \"%02d-%02d-%d\"\nmov esi, 2\npush rax\nmov r9d, [rsp+38h+var_18]\nxor eax, eax\nmov r8d, [rsp+38h+var_14]\ncall ___sprintf_chk\npop rax\npop rdx\nmov rax, [rsp+28h+var_10]\nsub rax, fs:28h\njnz short loc_1324\nadd rsp, 20h\nmov rax, rbx\npop rbx\nretn\nloc_1324:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "void *__fastcall sub_12A0(__int64 a1)\n{\n int v2; // [rsp+Ch] [rbp-1Ch] BYREF\n int v3; // [rsp+10h] [rbp-18h] BYREF\n int v4; // [rsp+14h] [rbp-14h] BYREF\n unsigned __int64 v5; // [rsp+18h] [rbp-10h]\n\n v5 = __readfsqword(0x28u);\n __isoc99_sscanf(a1, \"%d-%d-%d\", &v2, &v3, &v4);\n __sprintf_chk(&unk_4018, 2LL, 11LL, \"%02d-%02d-%d\", v4, v3, v2);\n return &unk_4018;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void* sub_12A0(long long a1) {\n int v2;\n int v3;\n int v4;\n unsigned long long v5;\n v5 = __readfsqword(40u);\n __isoc99_sscanf(a1, \"%d-%d-%d\", &v2, &v3, &v4);\n __sprintf_chk(&unk_4018, 2LL, 11LL, \"%02d-%02d-%d\", v4, v3, v2);\n return &unk_4018;\n}", + "ida_pseudo_norm": "void* func0(long long a1) {\n int v2;\n int v3;\n int v4;\n unsigned long long v5;\n v5 = __readfsqword(40u);\n __isoc99_sscanf(a1, \"%d-%d-%d\", &v2, &v3, &v4);\n __sprintf_chk(&new_format_1, 2LL, 11LL, \"%02d-%02d-%d\", v4, v3, v2);\n return &new_format_1;\n}" + }, + { + "index": 929, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int *tuplex, int size, int value) {\n int count = 0;\n for (int i = 0; i < size; i++) {\n if (tuplex[i] == value) {\n count++;\n }\n }\n return count;\n}", + "test": "int main() {\n\n int tuplex1[] = {2, 4, 5, 6, 2, 3, 4, 4, 7};\n\n int tuplex2[] = {2, 4, 7, 7, 7, 3, 4, 4, 7};\n\n\n\n assert(func0(tuplex1, 9, 4) == 3);\n\n assert(func0(tuplex1, 9, 2) == 2);\n\n assert(func0(tuplex2, 9, 7) == 4);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %edx,-0x20(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11ae \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x20(%rbp)\njne 11aa \naddl $0x1,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 118b \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11AE\nloc_118B:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njnz short loc_11AA\nadd [rbp+var_8], 1\nloc_11AA:\nadd [rbp+var_4], 1\nloc_11AE:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_118B\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n unsigned int v4; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( a3 == *(_DWORD *)(4LL * i + a1) )\n ++v4;\n }\n return v4;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_20], edx\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11AE\nloc_118B:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_20], eax\njnz short loc_11AA\nadd [rbp+var_8], 1\nloc_11AA:\nadd [rbp+var_4], 1\nloc_11AE:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_118B\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n unsigned int v4; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v4 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( a3 == *(_DWORD *)(4LL * i + a1) )\n ++v4;\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n unsigned int v4;\n int i;\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n if (a3 == *(uint32_t *)(4LL * i + a1)) ++v4;\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n unsigned int v4;\n int i;\n v4 = 0;\n for (i = 0; i < a2; ++i) {\n if (a3 == *(uint32_t *)(4LL * i + a1)) ++v4;\n }\n return v4;\n}" + }, + { + "index": 929, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int *tuplex, int size, int value) {\n int count = 0;\n for (int i = 0; i < size; i++) {\n if (tuplex[i] == value) {\n count++;\n }\n }\n return count;\n}", + "test": "int main() {\n\n int tuplex1[] = {2, 4, 5, 6, 2, 3, 4, 4, 7};\n\n int tuplex2[] = {2, 4, 7, 7, 7, 3, 4, 4, 7};\n\n\n\n assert(func0(tuplex1, 9, 4) == 3);\n\n assert(func0(tuplex1, 9, 2) == 2);\n\n assert(func0(tuplex2, 9, 7) == 4);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1199 \nmov %rdi,%rax\nlea -0x1(%rsi),%ecx\nlea 0x4(%rdi,%rcx,4),%rdi\nmov $0x0,%ecx\ncmp %edx,(%rax)\nsete %sil\nmovzbl %sil,%esi\nadd %esi,%ecx\nadd $0x4,%rax\ncmp %rdi,%rax\njne 1181 \nmov %ecx,%eax\nretq\nmov $0x0,%ecx\njmp 1196 \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1198\nmov rax, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*4]\nmov ecx, 0\nloc_1180:\ncmp [rax], edx\nsetz sil\nmovzx esi, sil\nadd ecx, esi\nadd rax, 4\ncmp rax, rdi\njnz short loc_1180\nloc_1195:\nmov eax, ecx\nretn\nloc_1198:\nmov ecx, 0\njmp short loc_1195", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2, int a3)\n{\n _DWORD *v3; // rax\n _DWORD *v4; // rdi\n unsigned int v5; // ecx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n do\n v5 += *v3++ == a3;\n while ( v3 != v4 );\n }\n return v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_1198\nmov rax, rdi\nmovsxd rsi, esi\nlea rdi, [rdi+rsi*4]\nmov ecx, 0\nloc_1180:\ncmp [rax], edx\nsetz sil\nmovzx esi, sil\nadd ecx, esi\nadd rax, 4\ncmp rax, rdi\njnz short loc_1180\nloc_1195:\nmov eax, ecx\nretn\nloc_1198:\nmov ecx, 0\njmp short loc_1195", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2, int a3)\n{\n _DWORD *v3; // rax\n _DWORD *v4; // rdi\n unsigned int v5; // ecx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n do\n v5 += *v3++ == a3;\n while ( v3 != v4 );\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2, int a3) {\n uint32_t *v3;\n uint32_t *v4;\n unsigned int v5;\n if (a2 <= 0) {\n return 0;\n } else {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n do\n v5 += *v3++ == a3;\n while (v3 != v4);\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2, int a3) {\n uint32_t *v3;\n uint32_t *v4;\n unsigned int v5;\n if (a2 <= 0) {\n return 0;\n } else {\n v3 = a1;\n v4 = &a1[a2];\n v5 = 0;\n do\n v5 += *v3++ == a3;\n while (v3 != v4);\n }\n return v5;\n}" + }, + { + "index": 930, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include\n\n", + "func": "char* func0(const char* text) {\n regex_t regex;\n int ret;\n char* patterns = \"ab*?\";\n ret = regcomp(®ex, patterns, REG_EXTENDED);\n if (ret) {\n return \"Error compiling regex\";\n }\n ret = regexec(®ex, text, 0, NULL, 0);\n regfree(®ex);\n if (!ret) {\n return \"Found a match!\";\n } else if (ret == REG_NOMATCH) {\n return \"Not matched!\";\n } else {\n return \"Regex match failed\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"msb\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"a0c\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\"abbc\"), \"Found a match!\") == 0);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x70,%rsp\nmov %rdi,-0x68(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea 0xdf9(%rip),%rax\nmov %rax,-0x58(%rbp)\nmov -0x58(%rbp),%rcx\nlea -0x50(%rbp),%rax\nmov $0x1,%edx\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 10d0 \nmov %eax,-0x5c(%rbp)\ncmpl $0x0,-0x5c(%rbp)\nje 123d \nlea 0xdd2(%rip),%rax\njmp 1291 \nmov -0x68(%rbp),%rsi\nlea -0x50(%rbp),%rax\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rax,%rdi\ncallq 10f0 \nmov %eax,-0x5c(%rbp)\nlea -0x50(%rbp),%rax\nmov %rax,%rdi\ncallq 10a0 \ncmpl $0x0,-0x5c(%rbp)\njne 127b \nlea 0xdaa(%rip),%rax\njmp 1291 \ncmpl $0x1,-0x5c(%rbp)\njne 128a \nlea 0xdaa(%rip),%rax\njmp 1291 \nlea 0xdae(%rip),%rax\nmov -0x8(%rbp),%rdx\nxor %fs:0x28,%rdx\nje 12a5 \ncallq 10b0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aAb; \"ab*?\"\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+var_5C], eax\ncmp [rbp+var_5C], 0\njz short loc_123D\nlea rax, aErrorCompiling; \"Error compiling regex\"\njmp short loc_1291\nloc_123D:\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_5C], eax\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\ncmp [rbp+var_5C], 0\njnz short loc_127B\nlea rax, aFoundAMatch; \"Found a match!\"\njmp short loc_1291\nloc_127B:\ncmp [rbp+var_5C], 1\njnz short loc_128A\nlea rax, s2; \"Not matched!\"\njmp short loc_1291\nloc_128A:\nlea rax, aRegexMatchFail; \"Regex match failed\"\nloc_1291:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12A5\ncall ___stack_chk_fail\nlocret_12A5:\nleave\nretn", + "ida_pseudo": "const char *__fastcall func0(const char *a1)\n{\n int v2; // [rsp+14h] [rbp-5Ch]\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n unsigned __int64 v4; // [rsp+68h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"ab*?\", 1) )\n return \"Error compiling regex\";\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if ( !v2 )\n return \"Found a match!\";\n if ( v2 == 1 )\n return \"Not matched!\";\n return \"Regex match failed\";\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 70h\nmov [rbp+string], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rax, aAb; \"ab*?\"\nmov [rbp+pattern], rax\nmov rcx, [rbp+pattern]\nlea rax, [rbp+preg]\nmov edx, 1; cflags\nmov rsi, rcx; pattern\nmov rdi, rax; preg\ncall _regcomp\nmov [rbp+var_5C], eax\ncmp [rbp+var_5C], 0\njz short loc_123D\nlea rax, aErrorCompiling; \"Error compiling regex\"\njmp short loc_1291\nloc_123D:\nmov rsi, [rbp+string]; string\nlea rax, [rbp+preg]\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rdi, rax; preg\ncall _regexec\nmov [rbp+var_5C], eax\nlea rax, [rbp+preg]\nmov rdi, rax; preg\ncall _regfree\ncmp [rbp+var_5C], 0\njnz short loc_127B\nlea rax, aFoundAMatch; \"Found a match!\"\njmp short loc_1291\nloc_127B:\ncmp [rbp+var_5C], 1\njnz short loc_128A\nlea rax, s2; \"Not matched!\"\njmp short loc_1291\nloc_128A:\nlea rax, aRegexMatchFail; \"Regex match failed\"\nloc_1291:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12A5\ncall ___stack_chk_fail\nlocret_12A5:\nleave\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_11E9(const char *a1)\n{\n int v2; // [rsp+14h] [rbp-5Ch]\n regex_t preg; // [rsp+20h] [rbp-50h] BYREF\n unsigned __int64 v4; // [rsp+68h] [rbp-8h]\n\n v4 = __readfsqword(0x28u);\n if ( regcomp(&preg, \"ab*?\", 1) )\n return \"Error compiling regex\";\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if ( !v2 )\n return \"Found a match!\";\n if ( v2 == 1 )\n return \"Not matched!\";\n return \"Regex match failed\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_11E9(const char *a1) {\n int v2;\n regex_t preg;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n if (regcomp(&preg, \"ab*?\", 1)) return \"Error compiling regex\";\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if (!v2) return \"Found a match!\";\n if (v2 == 1) return \"Not matched!\";\n return \"Regex match failed\";\n}", + "ida_pseudo_norm": "const char *func0(const char *a1) {\n int v2;\n regex_t preg;\n unsigned long long v4;\n v4 = __readfsqword(40u);\n if (regcomp(&preg, \"ab*?\", 1)) return \"Error compiling regex\";\n v2 = regexec(&preg, a1, 0LL, 0LL, 0);\n regfree(&preg);\n if (!v2) return \"Found a match!\";\n if (v2 == 1) return \"Not matched!\";\n return \"Regex match failed\";\n}" + }, + { + "index": 930, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include\n\n", + "func": "char* func0(const char* text) {\n regex_t regex;\n int ret;\n char* patterns = \"ab*?\";\n ret = regcomp(®ex, patterns, REG_EXTENDED);\n if (ret) {\n return \"Error compiling regex\";\n }\n ret = regexec(®ex, text, 0, NULL, 0);\n regfree(®ex);\n if (!ret) {\n return \"Found a match!\";\n } else if (ret == REG_NOMATCH) {\n return \"Not matched!\";\n } else {\n return \"Regex match failed\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"msb\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"a0c\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\"abbc\"), \"Found a match!\") == 0);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x58,%rsp\nmov %rdi,%rbx\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nmov $0x1,%edx\nlea 0xe54(%rip),%rsi\ncallq 10c0 \nmov %eax,%edx\nlea 0xe1d(%rip),%rax\ntest %edx,%edx\nje 121e \nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 1268 \nadd $0x58,%rsp\npop %rbx\npop %rbp\nretq\nmov %rsp,%rbp\nmov $0x0,%r8d\nmov $0x0,%ecx\nmov $0x0,%edx\nmov %rbx,%rsi\nmov %rbp,%rdi\ncallq 10d0 \nmov %eax,%ebx\nmov %rbp,%rdi\ncallq 1090 \nlea 0xdb7(%rip),%rax\ntest %ebx,%ebx\nje 1207 \ncmp $0x1,%ebx\nlea 0xdb8(%rip),%rax\nlea 0xdd4(%rip),%rdx\ncmovne %rdx,%rax\njmp 1207 \ncallq 10a0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+68h+var_20], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"ab*?\"\ncall _regcomp\nmov edx, eax\nlea rax, aErrorCompiling; \"Error compiling regex\"\ntest edx, edx\njz short loc_123E\nloc_1227:\nmov rdx, [rsp+68h+var_20]\nsub rdx, fs:28h\njnz short loc_1288\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_123E:\nmov rbp, rsp\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov ebx, eax\nmov rdi, rbp; preg\ncall _regfree\nlea rax, aFoundAMatch; \"Found a match!\"\ntest ebx, ebx\njz short loc_1227\ncmp ebx, 1\nlea rax, aRegexMatchFail; \"Regex match failed\"\nlea rdx, s2; \"Not matched!\"\ncmovz rax, rdx\njmp short loc_1227\nloc_1288:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // edx\n const char *result; // rax\n int v3; // ebx\n regex_t v4; // [rsp+0h] [rbp-68h] BYREF\n unsigned __int64 v5; // [rsp+48h] [rbp-20h]\n\n v5 = __readfsqword(0x28u);\n v1 = regcomp(&v4, \"ab*?\", 1);\n result = \"Error compiling regex\";\n if ( !v1 )\n {\n v3 = regexec(&v4, string, 0LL, 0LL, 0);\n regfree(&v4);\n result = \"Found a match!\";\n if ( v3 )\n {\n result = \"Regex match failed\";\n if ( v3 == 1 )\n return \"Not matched!\";\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_11E9:\nendbr64\npush rbp\npush rbx\nsub rsp, 58h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+68h+var_20], rax\nxor eax, eax\nmov rdi, rsp; preg\nmov edx, 1; cflags\nlea rsi, pattern; \"ab*?\"\ncall _regcomp\nmov edx, eax\nlea rax, aErrorCompiling; \"Error compiling regex\"\ntest edx, edx\njz short loc_123E\nloc_1227:\nmov rdx, [rsp+68h+var_20]\nsub rdx, fs:28h\njnz short loc_1288\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_123E:\nmov rbp, rsp\nmov r8d, 0; eflags\nmov ecx, 0; pmatch\nmov edx, 0; nmatch\nmov rsi, rbx; string\nmov rdi, rbp; preg\ncall _regexec\nmov ebx, eax\nmov rdi, rbp; preg\ncall _regfree\nlea rax, aFoundAMatch; \"Found a match!\"\ntest ebx, ebx\njz short loc_1227\ncmp ebx, 1\nlea rax, aRegexMatchFail; \"Regex match failed\"\nlea rdx, s2; \"Not matched!\"\ncmovz rax, rdx\njmp short loc_1227\nloc_1288:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_11E9(char *string)\n{\n int v1; // edx\n const char *result; // rax\n int v3; // ebx\n regex_t v4; // [rsp+0h] [rbp-68h] BYREF\n unsigned __int64 v5; // [rsp+48h] [rbp-20h]\n\n v5 = __readfsqword(0x28u);\n v1 = regcomp(&v4, \"ab*?\", 1);\n result = \"Error compiling regex\";\n if ( !v1 )\n {\n v3 = regexec(&v4, string, 0LL, 0LL, 0);\n regfree(&v4);\n result = \"Found a match!\";\n if ( v3 )\n {\n result = \"Regex match failed\";\n if ( v3 == 1 )\n return \"Not matched!\";\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_11E9(char *string) {\n int v1;\n const char *result;\n int v3;\n regex_t v4;\n unsigned long long v5;\n v5 = __readfsqword(40u);\n v1 = regcomp(&v4, \"ab*?\", 1);\n result = \"Error compiling regex\";\n if (!v1) {\n v3 = regexec(&v4, string, 0LL, 0LL, 0);\n regfree(&v4);\n result = \"Found a match!\";\n if (v3) {\n result = \"Regex match failed\";\n if (v3 == 1) return \"Not matched!\";\n }\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n const char *result;\n int v3;\n regex_t v4;\n unsigned long long v5;\n v5 = __readfsqword(40u);\n v1 = regcomp(&v4, \"ab*?\", 1);\n result = \"Error compiling regex\";\n if (!v1) {\n v3 = regexec(&v4, string, 0LL, 0LL, 0);\n regfree(&v4);\n result = \"Found a match!\";\n if (v3) {\n result = \"Regex match failed\";\n if (v3 == 1) return \"Not matched!\";\n }\n }\n return result;\n}" + }, + { + "index": 930, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include\n\n", + "func": "char* func0(const char* text) {\n regex_t regex;\n int ret;\n char* patterns = \"ab*?\";\n ret = regcomp(®ex, patterns, REG_EXTENDED);\n if (ret) {\n return \"Error compiling regex\";\n }\n ret = regexec(®ex, text, 0, NULL, 0);\n regfree(®ex);\n if (!ret) {\n return \"Found a match!\";\n } else if (ret == REG_NOMATCH) {\n return \"Not matched!\";\n } else {\n return \"Regex match failed\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"msb\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"a0c\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\"abbc\"), \"Found a match!\") == 0);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov $0x1,%edx\nlea 0xd87(%rip),%rsi\npush %rbp\nmov %rdi,%rbp\nsub $0x58,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%r12\nmov %r12,%rdi\ncallq 10c0 \nmov %eax,%r8d\nlea 0xd31(%rip),%rax\ntest %r8d,%r8d\nje 1310 \nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 134b \nadd $0x58,%rsp\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax)\nmov %rbp,%rsi\nxor %ecx,%ecx\nxor %edx,%edx\nmov %r12,%rdi\ncallq 10d0 \nmov %r12,%rdi\nmov %eax,%ebp\ncallq 1090 \nlea 0xcd4(%rip),%rax\ntest %ebp,%ebp\nje 12f4 \ncmp $0x1,%ebp\nlea 0xcd5(%rip),%rax\nlea 0xcf1(%rip),%rdx\ncmovne %rdx,%rax\njmp 12f4 \ncallq 10a0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"ab*?\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nmov edx, eax\nlea rax, aErrorCompiling; \"Error compiling regex\"\ntest edx, edx\njz short loc_1320\nloc_1301:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_135E\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1320:\nmov rsi, rbx; string\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\nlea rax, aFoundAMatch; \"Found a match!\"\ntest ebx, ebx\njz short loc_1301\ncmp ebx, 1\nlea rax, aRegexMatchFail; \"Regex match failed\"\nlea rdx, s2; \"Not matched!\"\ncmovz rax, rdx\njmp short loc_1301\nloc_135E:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // edx\n const char *result; // rax\n int v3; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n v1 = regcomp(&_0, \"ab*?\", 1);\n result = \"Error compiling regex\";\n if ( !v1 )\n {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Found a match!\";\n if ( v3 )\n {\n result = \"Regex match failed\";\n if ( v3 == 1 )\n return \"Not matched!\";\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"ab*?\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nmov edx, eax\nlea rax, aErrorCompiling; \"Error compiling regex\"\ntest edx, edx\njz short loc_1320\nloc_1301:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_135E\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1320:\nmov rsi, rbx; string\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\nlea rax, aFoundAMatch; \"Found a match!\"\ntest ebx, ebx\njz short loc_1301\ncmp ebx, 1\nlea rax, aRegexMatchFail; \"Regex match failed\"\nlea rdx, s2; \"Not matched!\"\ncmovz rax, rdx\njmp short loc_1301\nloc_135E:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_12C0(char *string)\n{\n int v1; // edx\n const char *result; // rax\n int v3; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n v1 = regcomp(&_0, \"ab*?\", 1);\n result = \"Error compiling regex\";\n if ( !v1 )\n {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Found a match!\";\n if ( v3 )\n {\n result = \"Regex match failed\";\n if ( v3 == 1 )\n return \"Not matched!\";\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_12C0(char *string) {\n int v1;\n const char *result;\n int v3;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n v1 = regcomp(&_0, \"ab*?\", 1);\n result = \"Error compiling regex\";\n if (!v1) {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Found a match!\";\n if (v3) {\n result = \"Regex match failed\";\n if (v3 == 1) return \"Not matched!\";\n }\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n const char *result;\n int v3;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n v1 = regcomp(&_0, \"ab*?\", 1);\n result = \"Error compiling regex\";\n if (!v1) {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Found a match!\";\n if (v3) {\n result = \"Regex match failed\";\n if (v3 == 1) return \"Not matched!\";\n }\n }\n return result;\n}" + }, + { + "index": 930, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include\n\n", + "func": "char* func0(const char* text) {\n regex_t regex;\n int ret;\n char* patterns = \"ab*?\";\n ret = regcomp(®ex, patterns, REG_EXTENDED);\n if (ret) {\n return \"Error compiling regex\";\n }\n ret = regexec(®ex, text, 0, NULL, 0);\n regfree(®ex);\n if (!ret) {\n return \"Found a match!\";\n } else if (ret == REG_NOMATCH) {\n return \"Not matched!\";\n } else {\n return \"Regex match failed\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"msb\"), \"Not matched!\") == 0);\n\n assert(strcmp(func0(\"a0c\"), \"Found a match!\") == 0);\n\n assert(strcmp(func0(\"abbc\"), \"Found a match!\") == 0);\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov $0x1,%edx\nlea 0xd87(%rip),%rsi\npush %rbp\nmov %rdi,%rbp\nsub $0x58,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x48(%rsp)\nxor %eax,%eax\nmov %rsp,%r12\nmov %r12,%rdi\ncallq 10c0 \nmov %eax,%r8d\nlea 0xd31(%rip),%rax\ntest %r8d,%r8d\nje 1310 \nmov 0x48(%rsp),%rcx\nxor %fs:0x28,%rcx\njne 134b \nadd $0x58,%rsp\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax)\nmov %rbp,%rsi\nxor %ecx,%ecx\nxor %edx,%edx\nmov %r12,%rdi\ncallq 10d0 \nmov %r12,%rdi\nmov %eax,%ebp\ncallq 1090 \nlea 0xcd4(%rip),%rax\ntest %ebp,%ebp\nje 12f4 \ncmp $0x1,%ebp\nlea 0xcd5(%rip),%rax\nlea 0xcf1(%rip),%rdx\ncmovne %rdx,%rax\njmp 12f4 \ncallq 10a0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"ab*?\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nmov edx, eax\nlea rax, aErrorCompiling; \"Error compiling regex\"\ntest edx, edx\njz short loc_1320\nloc_1301:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_135E\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1320:\nmov rsi, rbx; string\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\nlea rax, aFoundAMatch; \"Found a match!\"\ntest ebx, ebx\njz short loc_1301\ncmp ebx, 1\nlea rax, aRegexMatchFail; \"Regex match failed\"\nlea rdx, s2; \"Not matched!\"\ncmovz rax, rdx\njmp short loc_1301\nloc_135E:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *string)\n{\n int v1; // edx\n const char *result; // rax\n int v3; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n v1 = regcomp(&_0, \"ab*?\", 1);\n result = \"Error compiling regex\";\n if ( !v1 )\n {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Found a match!\";\n if ( v3 )\n {\n result = \"Regex match failed\";\n if ( v3 == 1 )\n return \"Not matched!\";\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\npush rbp\nmov edx, 1; cflags\nlea rsi, pattern; \"ab*?\"\npush rbx\nmov rbx, rdi\nsub rsp, 58h\nmov rax, fs:28h\nmov [rsp+var_s48], rax\nxor eax, eax\nmov rbp, rsp\nmov rdi, rbp; preg\ncall _regcomp\nmov edx, eax\nlea rax, aErrorCompiling; \"Error compiling regex\"\ntest edx, edx\njz short loc_1320\nloc_1301:\nmov rdx, [rsp+var_s48]\nsub rdx, fs:28h\njnz short loc_135E\nadd rsp, 58h\npop rbx\npop rbp\nretn\nloc_1320:\nmov rsi, rbx; string\nxor r8d, r8d; eflags\nxor ecx, ecx; pmatch\nxor edx, edx; nmatch\nmov rdi, rbp; preg\ncall _regexec\nmov rdi, rbp; preg\nmov ebx, eax\ncall _regfree\nlea rax, aFoundAMatch; \"Found a match!\"\ntest ebx, ebx\njz short loc_1301\ncmp ebx, 1\nlea rax, aRegexMatchFail; \"Regex match failed\"\nlea rdx, s2; \"Not matched!\"\ncmovz rax, rdx\njmp short loc_1301\nloc_135E:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_12C0(char *string)\n{\n int v1; // edx\n const char *result; // rax\n int v3; // ebx\n regex_t _0; // [rsp+0h] [rbp+0h] BYREF\n unsigned __int64 vars48; // [rsp+48h] [rbp+48h]\n\n vars48 = __readfsqword(0x28u);\n v1 = regcomp(&_0, \"ab*?\", 1);\n result = \"Error compiling regex\";\n if ( !v1 )\n {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Found a match!\";\n if ( v3 )\n {\n result = \"Regex match failed\";\n if ( v3 == 1 )\n return \"Not matched!\";\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_12C0(char *string) {\n int v1;\n const char *result;\n int v3;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n v1 = regcomp(&_0, \"ab*?\", 1);\n result = \"Error compiling regex\";\n if (!v1) {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Found a match!\";\n if (v3) {\n result = \"Regex match failed\";\n if (v3 == 1) return \"Not matched!\";\n }\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *string) {\n int v1;\n const char *result;\n int v3;\n regex_t _0;\n unsigned long long vars48;\n vars48 = __readfsqword(40u);\n v1 = regcomp(&_0, \"ab*?\", 1);\n result = \"Error compiling regex\";\n if (!v1) {\n v3 = regexec(&_0, string, 0LL, 0LL, 0);\n regfree(&_0);\n result = \"Found a match!\";\n if (v3) {\n result = \"Regex match failed\";\n if (v3 == 1) return \"Not matched!\";\n }\n }\n return result;\n}" + }, + { + "index": 931, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int number) {\n double total = 0;\n total = pow(((number * (number + 1)) / 2.0), 2);\n return total;\n}", + "test": "int main() {\n\n assert(func0(7) == 784);\n\n assert(func0(5) == 225);\n\n assert(func0(15) == 14400);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %edi,-0x14(%rbp)\npxor %xmm0,%xmm0\nmovsd %xmm0,-0x8(%rbp)\nmov -0x14(%rbp),%eax\nadd $0x1,%eax\nimul -0x14(%rbp),%eax\ncvtsi2sd %eax,%xmm0\nmovsd 0xee9(%rip),%xmm1\ndivsd %xmm1,%xmm0\nmovsd 0xedd(%rip),%xmm1\ncallq 1060 \nmovq %xmm0,%rax\nmov %rax,-0x8(%rbp)\nmovsd -0x8(%rbp),%xmm0\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\npxor xmm0, xmm0\nmovsd [rbp+var_8], xmm0\nmov eax, [rbp+var_14]\nadd eax, 1\nimul eax, [rbp+var_14]\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmovsd xmm1, cs:y\ndivsd xmm0, xmm1\nmovq rax, xmm0\nmovsd xmm0, cs:y\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\nmovq rax, xmm0\nmov [rbp+var_8], rax\nmovsd xmm0, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n return pow((double)(a1 * (a1 + 1)) / 2.0, 2.0);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_14], edi\npxor xmm0, xmm0\nmovsd [rbp+var_8], xmm0\nmov eax, [rbp+var_14]\nadd eax, 1\nimul eax, [rbp+var_14]\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax\nmovsd xmm1, cs:y\ndivsd xmm0, xmm1\nmovq rax, xmm0\nmovsd xmm0, cs:y\nmovapd xmm1, xmm0; y\nmovq xmm0, rax; x\ncall _pow\nmovq rax, xmm0\nmov [rbp+var_8], rax\nmovsd xmm0, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n return pow((double)(a1 * (a1 + 1)) / 2.0, 2.0);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) { return pow((double)(a1 * (a1 + 1)) / 2.0, 2.0); }", + "ida_pseudo_norm": "long long func0(int a1) { return pow((double)(a1 * (a1 + 1)) / 2.0, 2.0); }" + }, + { + "index": 932, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n#define MAX_ELEMENTS 100\n\n\n\n", + "func": "int func0(const char *input[], int input_size, const char *output[]) {\n int count = 0;\n for (int i = 0; i < input_size; i++) {\n int exists = 0;\n for (int j = 0; j < count; j++) {\n if (strcmp(input[i], output[j]) == 0) {\n exists = 1;\n break;\n }\n }\n if (!exists) {\n output[count++] = input[i];\n }\n }\n return count;\n}", + "test": "int main() {\n\n const char *input1[] = {\"Python\", \"Exercises\", \"Practice\", \"Solution\", \"Exercises\"};\n\n const char *expected1[] = {\"Python\", \"Exercises\", \"Practice\", \"Solution\"};\n\n const char *output1[MAX_ELEMENTS];\n\n int count1 = func0(input1, 5, output1);\n\n assert(count1 == 4);\n\n for(int i = 0; i < count1; i++) {\n\n assert(strcmp(output1[i], expected1[i]) == 0);\n\n }\n\n\n\n const char *input2[] = {\"Python\", \"Exercises\", \"Practice\", \"Solution\", \"Exercises\", \"Java\"};\n\n const char *expected2[] = {\"Python\", \"Exercises\", \"Practice\", \"Solution\", \"Java\"};\n\n const char *output2[MAX_ELEMENTS];\n\n int count2 = func0(input2, 6, output2);\n\n assert(count2 == 5);\n\n for(int i = 0; i < count2; i++) {\n\n assert(strcmp(output2[i], expected2[i]) == 0);\n\n }\n\n\n\n const char *input3[] = {\"Python\", \"Exercises\", \"Practice\", \"Solution\", \"Exercises\", \"C++\", \"C\", \"C++\"};\n\n const char *expected3[] = {\"Python\", \"Exercises\", \"Practice\", \"Solution\", \"C++\", \"C\"};\n\n const char *output3[MAX_ELEMENTS];\n\n int count3 = func0(input3, 8, output3);\n\n assert(count3 == 6);\n\n for(int i = 0; i < count3; i++) {\n\n assert(strcmp(output3[i], expected3[i]) == 0);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmovl $0x0,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\njmpq 1254 \nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 120d \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rdx\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%rax\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 1090 \ntest %eax,%eax\njne 1209 \nmovl $0x1,-0x8(%rbp)\njmp 1215 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x10(%rbp),%eax\njl 11c3 \ncmpl $0x0,-0x8(%rbp)\njne 1250 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x10(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x10(%rbp)\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x28(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%rax\nmov %rax,(%rdx)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11b3 \nmov -0x10(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp loc_1254\nloc_11B3:\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_120D\nloc_11C3:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1209\nmov [rbp+var_8], 1\njmp short loc_1215\nloc_1209:\nadd [rbp+var_4], 1\nloc_120D:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_10]\njl short loc_11C3\nloc_1215:\ncmp [rbp+var_8], 0\njnz short loc_1250\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov rax, [rcx]\nmov [rdx], rax\nloc_1250:\nadd [rbp+var_C], 1\nloc_1254:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl loc_11B3\nmov eax, [rbp+var_10]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3)\n{\n int v3; // eax\n unsigned int v6; // [rsp+20h] [rbp-10h]\n int i; // [rsp+24h] [rbp-Ch]\n int v8; // [rsp+28h] [rbp-8h]\n int j; // [rsp+2Ch] [rbp-4h]\n\n v6 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v8 = 0;\n for ( j = 0; j < (int)v6; ++j )\n {\n if ( !strcmp(*(const char **)(8LL * i + a1), *(const char **)(8LL * j + a3)) )\n {\n v8 = 1;\n break;\n }\n }\n if ( !v8 )\n {\n v3 = v6++;\n *(_QWORD *)(a3 + 8LL * v3) = *(_QWORD *)(8LL * i + a1);\n }\n }\n return v6;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp loc_1254\nloc_11B3:\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_120D\nloc_11C3:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov rax, [rax]\nmov rsi, rdx; s2\nmov rdi, rax; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1209\nmov [rbp+var_8], 1\njmp short loc_1215\nloc_1209:\nadd [rbp+var_4], 1\nloc_120D:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_10]\njl short loc_11C3\nloc_1215:\ncmp [rbp+var_8], 0\njnz short loc_1250\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov rax, [rcx]\nmov [rdx], rax\nloc_1250:\nadd [rbp+var_C], 1\nloc_1254:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl loc_11B3\nmov eax, [rbp+var_10]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2, __int64 a3)\n{\n int v3; // eax\n unsigned int v6; // [rsp+20h] [rbp-10h]\n int i; // [rsp+24h] [rbp-Ch]\n int v8; // [rsp+28h] [rbp-8h]\n int j; // [rsp+2Ch] [rbp-4h]\n\n v6 = 0;\n for ( i = 0; i < a2; ++i )\n {\n v8 = 0;\n for ( j = 0; j < (int)v6; ++j )\n {\n if ( !strcmp(*(const char **)(8LL * i + a1), *(const char **)(8LL * j + a3)) )\n {\n v8 = 1;\n break;\n }\n }\n if ( !v8 )\n {\n v3 = v6++;\n *(_QWORD *)(a3 + 8LL * v3) = *(_QWORD *)(8LL * i + a1);\n }\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2, long long a3) {\n int v3;\n unsigned int v6;\n int i;\n int v8;\n int j;\n v6 = 0;\n for (i = 0; i < a2; ++i) {\n v8 = 0;\n for (j = 0; j < (int)v6; ++j) {\n if (!strcmp(*(const char **)(8LL * i + a1),\n *(const char **)(8LL * j + a3))) {\n v8 = 1;\n break;\n }\n }\n if (!v8) {\n v3 = v6++;\n *(uint64_t *)(a3 + 8LL * v3) = *(uint64_t *)(8LL * i + a1);\n }\n }\n return v6;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3) {\n int v3;\n unsigned int v6;\n int i;\n int v8;\n int j;\n v6 = 0;\n for (i = 0; i < a2; ++i) {\n v8 = 0;\n for (j = 0; j < (int)v6; ++j) {\n if (!strcmp(*(const char **)(8LL * i + a1),\n *(const char **)(8LL * j + a3))) {\n v8 = 1;\n break;\n }\n }\n if (!v8) {\n v3 = v6++;\n *(uint64_t *)(a3 + 8LL * v3) = *(uint64_t *)(8LL * i + a1);\n }\n }\n return v6;\n}" + }, + { + "index": 932, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n#define MAX_ELEMENTS 100\n\n\n\n", + "func": "int func0(const char *input[], int input_size, const char *output[]) {\n int count = 0;\n for (int i = 0; i < input_size; i++) {\n int exists = 0;\n for (int j = 0; j < count; j++) {\n if (strcmp(input[i], output[j]) == 0) {\n exists = 1;\n break;\n }\n }\n if (!exists) {\n output[count++] = input[i];\n }\n }\n return count;\n}", + "test": "int main() {\n\n const char *input1[] = {\"Python\", \"Exercises\", \"Practice\", \"Solution\", \"Exercises\"};\n\n const char *expected1[] = {\"Python\", \"Exercises\", \"Practice\", \"Solution\"};\n\n const char *output1[MAX_ELEMENTS];\n\n int count1 = func0(input1, 5, output1);\n\n assert(count1 == 4);\n\n for(int i = 0; i < count1; i++) {\n\n assert(strcmp(output1[i], expected1[i]) == 0);\n\n }\n\n\n\n const char *input2[] = {\"Python\", \"Exercises\", \"Practice\", \"Solution\", \"Exercises\", \"Java\"};\n\n const char *expected2[] = {\"Python\", \"Exercises\", \"Practice\", \"Solution\", \"Java\"};\n\n const char *output2[MAX_ELEMENTS];\n\n int count2 = func0(input2, 6, output2);\n\n assert(count2 == 5);\n\n for(int i = 0; i < count2; i++) {\n\n assert(strcmp(output2[i], expected2[i]) == 0);\n\n }\n\n\n\n const char *input3[] = {\"Python\", \"Exercises\", \"Practice\", \"Solution\", \"Exercises\", \"C++\", \"C\", \"C++\"};\n\n const char *expected3[] = {\"Python\", \"Exercises\", \"Practice\", \"Solution\", \"C++\", \"C\"};\n\n const char *output3[MAX_ELEMENTS];\n\n int count3 = func0(input3, 8, output3);\n\n assert(count3 == 6);\n\n for(int i = 0; i < count3; i++) {\n\n assert(strcmp(output3[i], expected3[i]) == 0);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\ntest %esi,%esi\njle 11c2 \nmov %rdx,%r15\nmov %rdi,%r13\nlea -0x1(%rsi),%eax\nlea 0x8(%rdi,%rax,8),%rax\nmov %rax,(%rsp)\nmov $0x0,%r14d\nlea 0x8(%rdx),%rax\nmov %rax,0x8(%rsp)\njmp 11f3 \nmov $0x0,%r14d\nmov %r14d,%eax\nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmov 0x0(%r13),%rdx\nmovslq %r14d,%rax\nmov %rdx,(%r15,%rax,8)\nlea 0x1(%r14),%r14d\nadd $0x8,%r13\ncmp (%rsp),%r13\nje 11c8 \ntest %r14d,%r14d\njle 11da \nmov 0x0(%r13),%rbp\nmov %r15,%rbx\nlea -0x1(%r14),%eax\nmov 0x8(%rsp),%rcx\nlea (%rcx,%rax,8),%r12\nmov (%rbx),%rsi\nmov %rbp,%rdi\ncallq 1090 \ntest %eax,%eax\nje 11e9 \nadd $0x8,%rbx\ncmp %r12,%rbx\njne 120c \njmp 11da \n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\ntest esi, esi\njle short loc_1203\nmov r15, rdx\nmov r13, rdi\nmovsxd rsi, esi\nlea rax, [rdi+rsi*8]\nmov [rsp+48h+var_40], rax\nmov r14d, 0\njmp short loc_11D6\nloc_11B9:\nmov rdx, [r13+0]\nmovsxd rax, r14d\nmov [r15+rax*8], rdx\nlea r14d, [r14+1]\nloc_11C8:\nadd r13, 8\nmov rax, [rsp+48h+var_40]\ncmp r13, rax\njz short loc_1209\nloc_11D6:\ntest r14d, r14d\njle short loc_11B9\nmov rbp, [r13+0]\nmov rbx, r15\nmovsxd rax, r14d\nlea r12, [r15+rax*8]\nloc_11E9:\nmov rsi, [rbx]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njz short loc_11C8\nadd rbx, 8\ncmp rbx, r12\njnz short loc_11E9\njmp short loc_11B9\nloc_1203:\nmov r14d, 0\nloc_1209:\nmov eax, r14d\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char **a1, int a2, const char **a3)\n{\n const char **v4; // r13\n int v5; // r14d\n const char *v6; // rbp\n const char **v7; // rbx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v4 = a1;\n v5 = 0;\n do\n {\n if ( v5 <= 0 )\n {\nLABEL_3:\n a3[v5++] = *v4;\n }\n else\n {\n v6 = *v4;\n v7 = a3;\n while ( strcmp(v6, *v7) )\n {\n if ( ++v7 == &a3[v5] )\n goto LABEL_3;\n }\n }\n ++v4;\n }\n while ( v4 != &a1[a2] );\n }\n return (unsigned int)v5;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\ntest esi, esi\njle short loc_1203\nmov r15, rdx\nmov r13, rdi\nmovsxd rsi, esi\nlea rax, [rdi+rsi*8]\nmov [rsp+48h+var_40], rax\nmov r14d, 0\njmp short loc_11D6\nloc_11B9:\nmov rdx, [r13+0]\nmovsxd rax, r14d\nmov [r15+rax*8], rdx\nlea r14d, [r14+1]\nloc_11C8:\nadd r13, 8\nmov rax, [rsp+48h+var_40]\ncmp r13, rax\njz short loc_1209\nloc_11D6:\ntest r14d, r14d\njle short loc_11B9\nmov rbp, [r13+0]\nmov rbx, r15\nmovsxd rax, r14d\nlea r12, [r15+rax*8]\nloc_11E9:\nmov rsi, [rbx]; s2\nmov rdi, rbp; s1\ncall _strcmp\ntest eax, eax\njz short loc_11C8\nadd rbx, 8\ncmp rbx, r12\njnz short loc_11E9\njmp short loc_11B9\nloc_1203:\nmov r14d, 0\nloc_1209:\nmov eax, r14d\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(const char **a1, int a2, const char **a3)\n{\n const char **v4; // r13\n int v5; // r14d\n const char *v6; // rbp\n const char **v7; // rbx\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v4 = a1;\n v5 = 0;\n do\n {\n if ( v5 <= 0 )\n {\nLABEL_3:\n a3[v5++] = *v4;\n }\n else\n {\n v6 = *v4;\n v7 = a3;\n while ( strcmp(v6, *v7) )\n {\n if ( ++v7 == &a3[v5] )\n goto LABEL_3;\n }\n }\n ++v4;\n }\n while ( v4 != &a1[a2] );\n }\n return (unsigned int)v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(const char **a1, int a2, const char **a3) {\n const char **v4;\n int v5;\n const char *v6;\n const char **v7;\n if (a2 <= 0) {\n return 0;\n } else {\n v4 = a1;\n v5 = 0;\n do {\n if (v5 <= 0) {\n LABEL_3:\n a3[v5++] = *v4;\n } else {\n v6 = *v4;\n v7 = a3;\n while (strcmp(v6, *v7)) {\n if (++v7 == &a3[v5]) goto LABEL_3;\n }\n }\n ++v4;\n } while (v4 != &a1[a2]);\n }\n return (unsigned int)v5;\n}", + "ida_pseudo_norm": "long long func0(const char **a1, int a2, const char **a3) {\n const char **v4;\n int v5;\n const char *v6;\n const char **v7;\n if (a2 <= 0) {\n return 0;\n } else {\n v4 = a1;\n v5 = 0;\n do {\n if (v5 <= 0) {\n LABEL_3:\n a3[v5++] = *v4;\n } else {\n v6 = *v4;\n v7 = a3;\n while (strcmp(v6, *v7)) {\n if (++v7 == &a3[v5]) goto LABEL_3;\n }\n }\n ++v4;\n } while (v4 != &a1[a2]);\n }\n return (unsigned int)v5;\n}" + }, + { + "index": 932, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n#define MAX_ELEMENTS 100\n\n\n\n", + "func": "int func0(const char *input[], int input_size, const char *output[]) {\n int count = 0;\n for (int i = 0; i < input_size; i++) {\n int exists = 0;\n for (int j = 0; j < count; j++) {\n if (strcmp(input[i], output[j]) == 0) {\n exists = 1;\n break;\n }\n }\n if (!exists) {\n output[count++] = input[i];\n }\n }\n return count;\n}", + "test": "int main() {\n\n const char *input1[] = {\"Python\", \"Exercises\", \"Practice\", \"Solution\", \"Exercises\"};\n\n const char *expected1[] = {\"Python\", \"Exercises\", \"Practice\", \"Solution\"};\n\n const char *output1[MAX_ELEMENTS];\n\n int count1 = func0(input1, 5, output1);\n\n assert(count1 == 4);\n\n for(int i = 0; i < count1; i++) {\n\n assert(strcmp(output1[i], expected1[i]) == 0);\n\n }\n\n\n\n const char *input2[] = {\"Python\", \"Exercises\", \"Practice\", \"Solution\", \"Exercises\", \"Java\"};\n\n const char *expected2[] = {\"Python\", \"Exercises\", \"Practice\", \"Solution\", \"Java\"};\n\n const char *output2[MAX_ELEMENTS];\n\n int count2 = func0(input2, 6, output2);\n\n assert(count2 == 5);\n\n for(int i = 0; i < count2; i++) {\n\n assert(strcmp(output2[i], expected2[i]) == 0);\n\n }\n\n\n\n const char *input3[] = {\"Python\", \"Exercises\", \"Practice\", \"Solution\", \"Exercises\", \"C++\", \"C\", \"C++\"};\n\n const char *expected3[] = {\"Python\", \"Exercises\", \"Practice\", \"Solution\", \"C++\", \"C\"};\n\n const char *output3[MAX_ELEMENTS];\n\n int count3 = func0(input3, 8, output3);\n\n assert(count3 == 6);\n\n for(int i = 0; i < count3; i++) {\n\n assert(strcmp(output3[i], expected3[i]) == 0);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\ntest %esi,%esi\njle 155f \nlea -0x1(%rsi),%eax\nmov %rdx,%r14\nmov %rdi,%r12\nxor %r13d,%r13d\nlea 0x8(%rdi,%rax,8),%rax\nmov %rax,(%rsp)\nlea 0x8(%rdx),%rax\nmov %rax,0x8(%rsp)\nnopl 0x0(%rax,%rax,1)\nmov (%r12),%rbx\ntest %r13d,%r13d\nje 1548 \nmov 0x8(%rsp),%rcx\nlea -0x1(%r13),%eax\nmov %r14,%r15\nlea (%rcx,%rax,8),%rbp\njmp 1519 \nnopl 0x0(%rax,%rax,1)\nadd $0x8,%r15\ncmp %rbp,%r15\nje 1548 \nmov (%r15),%rsi\nmov %rbx,%rdi\ncallq 1090 \ntest %eax,%eax\njne 1510 \nadd $0x8,%r12\ncmp (%rsp),%r12\njne 14f0 \nadd $0x18,%rsp\nmov %r13d,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\nmovslq %r13d,%rax\nadd $0x8,%r12\nadd $0x1,%r13d\nmov %rbx,(%r14,%rax,8)\ncmp (%rsp),%r12\njne 14f0 \njmp 1532 \nxor %r13d,%r13d\njmp 1532 \nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\ntest esi, esi\njle loc_1589\nmovsxd rsi, esi\nmov r14, rdx\nmov r12, rdi\nxor r13d, r13d\nlea rax, [rdi+rsi*8]\nmov [rsp+48h+var_48], rax\nxchg ax, ax\nloc_1510:\nmovsxd rax, r13d\nmov rbx, [r12]\nmov [rsp+48h+var_40], rax\nlea rbp, [r14+rax*8]\ntest r13d, r13d\njle short loc_1560\nloc_1525:\nmov r15, r14\njmp short loc_1539\nloc_1530:\nadd r15, 8\ncmp r15, rbp\njz short loc_1560\nloc_1539:\nmov rsi, [r15]; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1530\nmov rax, [rsp+48h+var_48]\nadd r12, 8\ncmp r12, rax\njz short loc_1577\nmov rbx, [r12]\njmp short loc_1525\nloc_1560:\nmov rax, [rsp+48h+var_40]\nadd r13d, 1\nadd r12, 8\nmov [r14+rax*8], rbx\ncmp [rsp+48h+var_48], r12\njnz short loc_1510\nloc_1577:\nadd rsp, 18h\nmov eax, r13d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1589:\nxor r13d, r13d\njmp short loc_1577", + "ida_pseudo": "__int64 __fastcall func0(const char **a1, int a2, const char **a3)\n{\n const char **v4; // r12\n int v5; // r13d\n const char *v6; // rbx\n const char **v7; // r15\n const char **v9; // [rsp+0h] [rbp-48h]\n __int64 v10; // [rsp+8h] [rbp-40h]\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v4 = a1;\n v5 = 0;\n v9 = &a1[a2];\n while ( 1 )\n {\n v6 = *v4;\n v10 = v5;\n if ( v5 > 0 )\n break;\nLABEL_9:\n ++v5;\n ++v4;\n a3[v10] = v6;\n if ( v9 == v4 )\n return (unsigned int)v5;\n }\n while ( 1 )\n {\n v7 = a3;\n while ( strcmp(v6, *v7) )\n {\n if ( ++v7 == &a3[v5] )\n goto LABEL_9;\n }\n if ( ++v4 == v9 )\n break;\n v6 = *v4;\n }\n }\n return (unsigned int)v5;\n}", + "ida_strip_asm": "sub_14E0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\ntest esi, esi\njle loc_1589\nmovsxd rsi, esi\nmov r14, rdx\nmov r12, rdi\nxor r13d, r13d\nlea rax, [rdi+rsi*8]\nmov [rsp+48h+var_48], rax\nxchg ax, ax\nloc_1510:\nmovsxd rax, r13d\nmov rbx, [r12]\nmov [rsp+48h+var_40], rax\nlea rbp, [r14+rax*8]\ntest r13d, r13d\njle short loc_1560\nloc_1525:\nmov r15, r14\njmp short loc_1539\nloc_1530:\nadd r15, 8\ncmp r15, rbp\njz short loc_1560\nloc_1539:\nmov rsi, [r15]; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_1530\nmov rax, [rsp+48h+var_48]\nadd r12, 8\ncmp r12, rax\njz short loc_1577\nmov rbx, [r12]\njmp short loc_1525\nloc_1560:\nmov rax, [rsp+48h+var_40]\nadd r13d, 1\nadd r12, 8\nmov [r14+rax*8], rbx\ncmp [rsp+48h+var_48], r12\njnz short loc_1510\nloc_1577:\nadd rsp, 18h\nmov eax, r13d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1589:\nxor r13d, r13d\njmp short loc_1577", + "ida_strip_pseudo": "__int64 __fastcall sub_14E0(const char **a1, int a2, const char **a3)\n{\n const char **v4; // r12\n int v5; // r13d\n const char *v6; // rbx\n const char **v7; // r15\n const char **v9; // [rsp+0h] [rbp-48h]\n __int64 v10; // [rsp+8h] [rbp-40h]\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v4 = a1;\n v5 = 0;\n v9 = &a1[a2];\n while ( 1 )\n {\n v6 = *v4;\n v10 = v5;\n if ( v5 > 0 )\n break;\nLABEL_9:\n ++v5;\n ++v4;\n a3[v10] = v6;\n if ( v9 == v4 )\n return (unsigned int)v5;\n }\n while ( 1 )\n {\n v7 = a3;\n while ( strcmp(v6, *v7) )\n {\n if ( ++v7 == &a3[v5] )\n goto LABEL_9;\n }\n if ( ++v4 == v9 )\n break;\n v6 = *v4;\n }\n }\n return (unsigned int)v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_14E0(const char **a1, int a2, const char **a3) {\n const char **v4;\n int v5;\n const char *v6;\n const char **v7;\n const char **v9;\n long long v10;\n if (a2 <= 0) {\n return 0;\n } else {\n v4 = a1;\n v5 = 0;\n v9 = &a1[a2];\n while (1) {\n v6 = *v4;\n v10 = v5;\n if (v5 > 0) break;\n LABEL_9:\n ++v5;\n ++v4;\n a3[v10] = v6;\n if (v9 == v4) return (unsigned int)v5;\n }\n while (1) {\n v7 = a3;\n while (strcmp(v6, *v7)) {\n if (++v7 == &a3[v5]) goto LABEL_9;\n }\n if (++v4 == v9) break;\n v6 = *v4;\n }\n }\n return (unsigned int)v5;\n}", + "ida_pseudo_norm": "long long func0(const char **a1, int a2, const char **a3) {\n const char **v4;\n int v5;\n const char *v6;\n const char **v7;\n const char **v9;\n long long v10;\n if (a2 <= 0) {\n return 0;\n } else {\n v4 = a1;\n v5 = 0;\n v9 = &a1[a2];\n while (1) {\n v6 = *v4;\n v10 = v5;\n if (v5 > 0) break;\n LABEL_9:\n ++v5;\n ++v4;\n a3[v10] = v6;\n if (v9 == v4) return (unsigned int)v5;\n }\n while (1) {\n v7 = a3;\n while (strcmp(v6, *v7)) {\n if (++v7 == &a3[v5]) goto LABEL_9;\n }\n if (++v4 == v9) break;\n v6 = *v4;\n }\n }\n return (unsigned int)v5;\n}" + }, + { + "index": 932, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n#define MAX_ELEMENTS 100\n\n\n\n", + "func": "int func0(const char *input[], int input_size, const char *output[]) {\n int count = 0;\n for (int i = 0; i < input_size; i++) {\n int exists = 0;\n for (int j = 0; j < count; j++) {\n if (strcmp(input[i], output[j]) == 0) {\n exists = 1;\n break;\n }\n }\n if (!exists) {\n output[count++] = input[i];\n }\n }\n return count;\n}", + "test": "int main() {\n\n const char *input1[] = {\"Python\", \"Exercises\", \"Practice\", \"Solution\", \"Exercises\"};\n\n const char *expected1[] = {\"Python\", \"Exercises\", \"Practice\", \"Solution\"};\n\n const char *output1[MAX_ELEMENTS];\n\n int count1 = func0(input1, 5, output1);\n\n assert(count1 == 4);\n\n for(int i = 0; i < count1; i++) {\n\n assert(strcmp(output1[i], expected1[i]) == 0);\n\n }\n\n\n\n const char *input2[] = {\"Python\", \"Exercises\", \"Practice\", \"Solution\", \"Exercises\", \"Java\"};\n\n const char *expected2[] = {\"Python\", \"Exercises\", \"Practice\", \"Solution\", \"Java\"};\n\n const char *output2[MAX_ELEMENTS];\n\n int count2 = func0(input2, 6, output2);\n\n assert(count2 == 5);\n\n for(int i = 0; i < count2; i++) {\n\n assert(strcmp(output2[i], expected2[i]) == 0);\n\n }\n\n\n\n const char *input3[] = {\"Python\", \"Exercises\", \"Practice\", \"Solution\", \"Exercises\", \"C++\", \"C\", \"C++\"};\n\n const char *expected3[] = {\"Python\", \"Exercises\", \"Practice\", \"Solution\", \"C++\", \"C\"};\n\n const char *output3[MAX_ELEMENTS];\n\n int count3 = func0(input3, 8, output3);\n\n assert(count3 == 6);\n\n for(int i = 0; i < count3; i++) {\n\n assert(strcmp(output3[i], expected3[i]) == 0);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\ntest %esi,%esi\njle 165f \nlea -0x1(%rsi),%eax\nmov %rdx,%r14\nmov %rdi,%r12\nxor %r13d,%r13d\nlea 0x8(%rdi,%rax,8),%rax\nmov %rax,(%rsp)\nlea 0x8(%rdx),%rax\nmov %rax,0x8(%rsp)\nnopl 0x0(%rax,%rax,1)\nmov (%r12),%rbx\ntest %r13d,%r13d\nje 1648 \nmov 0x8(%rsp),%rcx\nlea -0x1(%r13),%eax\nmov %r14,%r15\nlea (%rcx,%rax,8),%rbp\njmp 1619 \nnopl 0x0(%rax,%rax,1)\nadd $0x8,%r15\ncmp %r15,%rbp\nje 1648 \nmov (%r15),%rsi\nmov %rbx,%rdi\ncallq 1090 \ntest %eax,%eax\njne 1610 \nadd $0x8,%r12\ncmp %r12,(%rsp)\njne 15f0 \nadd $0x18,%rsp\nmov %r13d,%eax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\nmovslq %r13d,%rax\nadd $0x8,%r12\nadd $0x1,%r13d\nmov %rbx,(%r14,%rax,8)\ncmp %r12,(%rsp)\njne 15f0 \njmp 1632 \nxor %r13d,%r13d\njmp 1632 \nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\ntest esi, esi\njle loc_15F9\nmovsxd rsi, esi\nmov r14, rdx\nmov r12, rdi\nxor r13d, r13d\nlea rax, [rdi+rsi*8]\nmov [rsp+48h+var_48], rax\nxchg ax, ax\nloc_1580:\nmovsxd rax, r13d\nmov rbx, [r12]\nmov [rsp+48h+var_40], rax\nlea rbp, [r14+rax*8]\ntest r13d, r13d\njle short loc_15D0\nloc_1595:\nmov r15, r14\njmp short loc_15A9\nloc_15A0:\nadd r15, 8\ncmp rbp, r15\njz short loc_15D0\nloc_15A9:\nmov rsi, [r15]; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_15A0\nadd r12, 8\ncmp [rsp+48h+var_48], r12\njz short loc_15E7\nmov rbx, [r12]\njmp short loc_1595\nloc_15D0:\nmov rax, [rsp+48h+var_40]\nadd r13d, 1\nadd r12, 8\nmov [r14+rax*8], rbx\ncmp [rsp+48h+var_48], r12\njnz short loc_1580\nloc_15E7:\nadd rsp, 18h\nmov eax, r13d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15F9:\nxor r13d, r13d\njmp short loc_15E7", + "ida_pseudo": "__int64 __fastcall func0(const char **a1, int a2, const char **a3)\n{\n const char **v4; // r12\n int v5; // r13d\n const char *v6; // rbx\n const char **v7; // r15\n const char **v9; // [rsp+0h] [rbp-48h]\n __int64 v10; // [rsp+8h] [rbp-40h]\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v4 = a1;\n v5 = 0;\n v9 = &a1[a2];\n while ( 1 )\n {\n v6 = *v4;\n v10 = v5;\n if ( v5 > 0 )\n break;\nLABEL_9:\n ++v5;\n ++v4;\n a3[v10] = v6;\n if ( v9 == v4 )\n return (unsigned int)v5;\n }\n while ( 1 )\n {\n v7 = a3;\n while ( strcmp(v6, *v7) )\n {\n if ( &a3[v5] == ++v7 )\n goto LABEL_9;\n }\n if ( v9 == ++v4 )\n break;\n v6 = *v4;\n }\n }\n return (unsigned int)v5;\n}", + "ida_strip_asm": "sub_1550:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\ntest esi, esi\njle loc_15F9\nmovsxd rsi, esi\nmov r14, rdx\nmov r12, rdi\nxor r13d, r13d\nlea rax, [rdi+rsi*8]\nmov [rsp+48h+var_48], rax\nxchg ax, ax\nloc_1580:\nmovsxd rax, r13d\nmov rbx, [r12]\nmov [rsp+48h+var_40], rax\nlea rbp, [r14+rax*8]\ntest r13d, r13d\njle short loc_15D0\nloc_1595:\nmov r15, r14\njmp short loc_15A9\nloc_15A0:\nadd r15, 8\ncmp rbp, r15\njz short loc_15D0\nloc_15A9:\nmov rsi, [r15]; s2\nmov rdi, rbx; s1\ncall _strcmp\ntest eax, eax\njnz short loc_15A0\nadd r12, 8\ncmp [rsp+48h+var_48], r12\njz short loc_15E7\nmov rbx, [r12]\njmp short loc_1595\nloc_15D0:\nmov rax, [rsp+48h+var_40]\nadd r13d, 1\nadd r12, 8\nmov [r14+rax*8], rbx\ncmp [rsp+48h+var_48], r12\njnz short loc_1580\nloc_15E7:\nadd rsp, 18h\nmov eax, r13d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_15F9:\nxor r13d, r13d\njmp short loc_15E7", + "ida_strip_pseudo": "__int64 __fastcall sub_1550(const char **a1, int a2, const char **a3)\n{\n const char **v4; // r12\n int v5; // r13d\n const char *v6; // rbx\n const char **v7; // r15\n const char **v9; // [rsp+0h] [rbp-48h]\n __int64 v10; // [rsp+8h] [rbp-40h]\n\n if ( a2 <= 0 )\n {\n return 0;\n }\n else\n {\n v4 = a1;\n v5 = 0;\n v9 = &a1[a2];\n while ( 1 )\n {\n v6 = *v4;\n v10 = v5;\n if ( v5 > 0 )\n break;\nLABEL_9:\n ++v5;\n ++v4;\n a3[v10] = v6;\n if ( v9 == v4 )\n return (unsigned int)v5;\n }\n while ( 1 )\n {\n v7 = a3;\n while ( strcmp(v6, *v7) )\n {\n if ( &a3[v5] == ++v7 )\n goto LABEL_9;\n }\n if ( v9 == ++v4 )\n break;\n v6 = *v4;\n }\n }\n return (unsigned int)v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1550(const char **a1, int a2, const char **a3) {\n const char **v4;\n int v5;\n const char *v6;\n const char **v7;\n const char **v9;\n long long v10;\n if (a2 <= 0) {\n return 0;\n } else {\n v4 = a1;\n v5 = 0;\n v9 = &a1[a2];\n while (1) {\n v6 = *v4;\n v10 = v5;\n if (v5 > 0) break;\n LABEL_9:\n ++v5;\n ++v4;\n a3[v10] = v6;\n if (v9 == v4) return (unsigned int)v5;\n }\n while (1) {\n v7 = a3;\n while (strcmp(v6, *v7)) {\n if (&a3[v5] == ++v7) goto LABEL_9;\n }\n if (v9 == ++v4) break;\n v6 = *v4;\n }\n }\n return (unsigned int)v5;\n}", + "ida_pseudo_norm": "long long func0(const char **a1, int a2, const char **a3) {\n const char **v4;\n int v5;\n const char *v6;\n const char **v7;\n const char **v9;\n long long v10;\n if (a2 <= 0) {\n return 0;\n } else {\n v4 = a1;\n v5 = 0;\n v9 = &a1[a2];\n while (1) {\n v6 = *v4;\n v10 = v5;\n if (v5 > 0) break;\n LABEL_9:\n ++v5;\n ++v4;\n a3[v10] = v6;\n if (v9 == v4) return (unsigned int)v5;\n }\n while (1) {\n v7 = a3;\n while (strcmp(v6, *v7)) {\n if (&a3[v5] == ++v7) goto LABEL_9;\n }\n if (v9 == ++v4) break;\n v6 = *v4;\n }\n }\n return (unsigned int)v5;\n}" + }, + { + "index": 933, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n size_t length = strlen(text);\n size_t new_length = 0;\n char* result = (char*)malloc(sizeof(char) * (length * 2));\n int i, j = 0;\n for (i = 0; i < length; i++) {\n if (i > 0 && isupper(text[i]) &&\n (islower(text[i - 1]) || isdigit(text[i - 1]))) {\n result[j++] = '_';\n result[j++] = tolower(text[i]);\n } else if (i > 0 && isupper(text[i]) && isupper(text[i - 1]) &&\n islower(text[i + 1])) {\n result[j++] = '_';\n result[j++] = tolower(text[i]);\n } else {\n result[j++] = tolower(text[i]);\n }\n }\n result[j] = '\\0';\n return result;\n}", + "test": "int main() {\n\n char* result;\n\n\n\n result = func0(\"GoogleAssistant\");\n\n assert(strcmp(result, \"google_assistant\") == 0);\n\n free(result);\n\n\n\n result = func0(\"ChromeCast\");\n\n assert(strcmp(result, \"chrome_cast\") == 0);\n\n free(result);\n\n\n\n result = func0(\"QuadCore\");\n\n assert(strcmp(result, \"quad_core\") == 0);\n\n free(result);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x28(%rbp)\nmov -0x28(%rbp),%rax\nmov %rax,%rdi\ncallq 10c0 \nmov %rax,-0x18(%rbp)\nmovq $0x0,-0x10(%rbp)\nmov -0x18(%rbp),%rax\nadd %rax,%rax\nmov %rax,%rdi\ncallq 1100 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0x1c(%rbp)\nmovl $0x0,-0x20(%rbp)\njmpq 147d \ncmpl $0x0,-0x20(%rbp)\njle 134e \ncallq 1110 <__ctype_b_loc@plt>\nmov (%rax),%rax\nmov -0x20(%rbp),%edx\nmovslq %edx,%rcx\nmov -0x28(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rdx),%edx\nmovsbq %dl,%rdx\nadd %rdx,%rdx\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x100,%eax\ntest %eax,%eax\nje 134e \ncallq 1110 <__ctype_b_loc@plt>\nmov (%rax),%rax\nmov -0x20(%rbp),%edx\nmovslq %edx,%rdx\nlea -0x1(%rdx),%rcx\nmov -0x28(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rdx),%edx\nmovsbq %dl,%rdx\nadd %rdx,%rdx\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x200,%eax\ntest %eax,%eax\njne 1300 \ncallq 1110 <__ctype_b_loc@plt>\nmov (%rax),%rax\nmov -0x20(%rbp),%edx\nmovslq %edx,%rdx\nlea -0x1(%rdx),%rcx\nmov -0x28(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rdx),%edx\nmovsbq %dl,%rdx\nadd %rdx,%rdx\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x800,%eax\ntest %eax,%eax\nje 134e \nmov -0x1c(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x1c(%rbp)\nmovslq %eax,%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmovb $0x5f,(%rax)\nmov -0x20(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmovsbl %al,%eax\nmov %eax,%edi\ncallq 10f0 \nmov %eax,%ecx\nmov -0x1c(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x1c(%rbp)\nmovslq %eax,%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov %ecx,%edx\nmov %dl,(%rax)\njmpq 1479 \ncmpl $0x0,-0x20(%rbp)\njle 1446 \ncallq 1110 <__ctype_b_loc@plt>\nmov (%rax),%rax\nmov -0x20(%rbp),%edx\nmovslq %edx,%rcx\nmov -0x28(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rdx),%edx\nmovsbq %dl,%rdx\nadd %rdx,%rdx\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x100,%eax\ntest %eax,%eax\nje 1446 \ncallq 1110 <__ctype_b_loc@plt>\nmov (%rax),%rax\nmov -0x20(%rbp),%edx\nmovslq %edx,%rdx\nlea -0x1(%rdx),%rcx\nmov -0x28(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rdx),%edx\nmovsbq %dl,%rdx\nadd %rdx,%rdx\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x100,%eax\ntest %eax,%eax\nje 1446 \ncallq 1110 <__ctype_b_loc@plt>\nmov (%rax),%rax\nmov -0x20(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x1(%rdx),%rcx\nmov -0x28(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rdx),%edx\nmovsbq %dl,%rdx\nadd %rdx,%rdx\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x200,%eax\ntest %eax,%eax\nje 1446 \nmov -0x1c(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x1c(%rbp)\nmovslq %eax,%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmovb $0x5f,(%rax)\nmov -0x20(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmovsbl %al,%eax\nmov %eax,%edi\ncallq 10f0 \nmov %eax,%ecx\nmov -0x1c(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x1c(%rbp)\nmovslq %eax,%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov %ecx,%edx\nmov %dl,(%rax)\njmp 1479 \nmov -0x20(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmovsbl %al,%eax\nmov %eax,%edi\ncallq 10f0 \nmov %eax,%ecx\nmov -0x1c(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x1c(%rbp)\nmovslq %eax,%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov %ecx,%edx\nmov %dl,(%rax)\naddl $0x1,-0x20(%rbp)\nmov -0x20(%rbp),%eax\ncltq\ncmp %rax,-0x18(%rbp)\nja 1257 \nmov -0x1c(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmovb $0x0,(%rax)\nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_18], rax\nmov [rbp+var_10], 0\nmov rax, [rbp+var_18]\nadd rax, rax\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_1C], 0\nmov [rbp+var_20], 0\njmp loc_147D\nloc_1257:\ncmp [rbp+var_20], 0\njle loc_134E\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_20]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 100h\ntest eax, eax\njz loc_134E\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nlea rcx, [rdx-1]\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 200h\ntest eax, eax\njnz short loc_1300\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nlea rcx, [rdx-1]\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 800h\ntest eax, eax\njz short loc_134E\nloc_1300:\nmov eax, [rbp+var_1C]\nlea edx, [rax+1]\nmov [rbp+var_1C], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov byte ptr [rax], 5Fh ; '_'\nmov eax, [rbp+var_20]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nmov edi, eax; c\ncall _tolower\nmov ecx, eax\nmov eax, [rbp+var_1C]\nlea edx, [rax+1]\nmov [rbp+var_1C], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, ecx\nmov [rax], dl\njmp loc_1479\nloc_134E:\ncmp [rbp+var_20], 0\njle loc_1446\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_20]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 100h\ntest eax, eax\njz loc_1446\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nlea rcx, [rdx-1]\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 100h\ntest eax, eax\njz loc_1446\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nlea rcx, [rdx+1]\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 200h\ntest eax, eax\njz short loc_1446\nmov eax, [rbp+var_1C]\nlea edx, [rax+1]\nmov [rbp+var_1C], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov byte ptr [rax], 5Fh ; '_'\nmov eax, [rbp+var_20]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nmov edi, eax; c\ncall _tolower\nmov ecx, eax\nmov eax, [rbp+var_1C]\nlea edx, [rax+1]\nmov [rbp+var_1C], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, ecx\nmov [rax], dl\njmp short loc_1479\nloc_1446:\nmov eax, [rbp+var_20]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nmov edi, eax; c\ncall _tolower\nmov ecx, eax\nmov eax, [rbp+var_1C]\nlea edx, [rax+1]\nmov [rbp+var_1C], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, ecx\nmov [rax], dl\nloc_1479:\nadd [rbp+var_20], 1\nloc_147D:\nmov eax, [rbp+var_20]\ncdqe\ncmp rax, [rbp+var_18]\njb loc_1257\nmov eax, [rbp+var_1C]\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1)\n{\n char v1; // cl\n int v2; // eax\n char v3; // cl\n int v4; // eax\n int i; // [rsp+10h] [rbp-20h]\n int v7; // [rsp+14h] [rbp-1Ch]\n size_t v8; // [rsp+18h] [rbp-18h]\n _BYTE *v9; // [rsp+28h] [rbp-8h]\n\n v8 = strlen(a1);\n v9 = malloc(2 * v8);\n v7 = 0;\n for ( i = 0; i < v8; ++i )\n {\n if ( i > 0\n && ((*__ctype_b_loc())[a1[i]] & 0x100) != 0\n && (((*__ctype_b_loc())[a1[i - 1]] & 0x200) != 0 || ((*__ctype_b_loc())[a1[i - 1]] & 0x800) != 0)\n || i > 0\n && ((*__ctype_b_loc())[a1[i]] & 0x100) != 0\n && ((*__ctype_b_loc())[a1[i - 1]] & 0x100) != 0\n && ((*__ctype_b_loc())[a1[i + 1]] & 0x200) != 0 )\n {\n v9[v7] = 95;\n v1 = tolower(a1[i]);\n v2 = v7 + 1;\n v7 += 2;\n v9[v2] = v1;\n }\n else\n {\n v3 = tolower(a1[i]);\n v4 = v7++;\n v9[v4] = v3;\n }\n }\n v9[v7] = 0;\n return v9;\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_18], rax\nmov [rbp+var_10], 0\nmov rax, [rbp+var_18]\nadd rax, rax\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_1C], 0\nmov [rbp+var_20], 0\njmp loc_147D\nloc_1257:\ncmp [rbp+var_20], 0\njle loc_134E\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_20]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 100h\ntest eax, eax\njz loc_134E\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nlea rcx, [rdx-1]\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 200h\ntest eax, eax\njnz short loc_1300\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nlea rcx, [rdx-1]\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 800h\ntest eax, eax\njz short loc_134E\nloc_1300:\nmov eax, [rbp+var_1C]\nlea edx, [rax+1]\nmov [rbp+var_1C], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov byte ptr [rax], 5Fh ; '_'\nmov eax, [rbp+var_20]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nmov edi, eax; c\ncall _tolower\nmov ecx, eax\nmov eax, [rbp+var_1C]\nlea edx, [rax+1]\nmov [rbp+var_1C], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, ecx\nmov [rax], dl\njmp loc_1479\nloc_134E:\ncmp [rbp+var_20], 0\njle loc_1446\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_20]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 100h\ntest eax, eax\njz loc_1446\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nlea rcx, [rdx-1]\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 100h\ntest eax, eax\njz loc_1446\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nlea rcx, [rdx+1]\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 200h\ntest eax, eax\njz short loc_1446\nmov eax, [rbp+var_1C]\nlea edx, [rax+1]\nmov [rbp+var_1C], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov byte ptr [rax], 5Fh ; '_'\nmov eax, [rbp+var_20]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nmov edi, eax; c\ncall _tolower\nmov ecx, eax\nmov eax, [rbp+var_1C]\nlea edx, [rax+1]\nmov [rbp+var_1C], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, ecx\nmov [rax], dl\njmp short loc_1479\nloc_1446:\nmov eax, [rbp+var_20]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nmov edi, eax; c\ncall _tolower\nmov ecx, eax\nmov eax, [rbp+var_1C]\nlea edx, [rax+1]\nmov [rbp+var_1C], edx\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov edx, ecx\nmov [rax], dl\nloc_1479:\nadd [rbp+var_20], 1\nloc_147D:\nmov eax, [rbp+var_20]\ncdqe\ncmp rax, [rbp+var_18]\njb loc_1257\nmov eax, [rbp+var_1C]\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1209(const char *a1)\n{\n char v1; // cl\n int v2; // eax\n char v3; // cl\n int v4; // eax\n int i; // [rsp+10h] [rbp-20h]\n int v7; // [rsp+14h] [rbp-1Ch]\n size_t v8; // [rsp+18h] [rbp-18h]\n _BYTE *v9; // [rsp+28h] [rbp-8h]\n\n v8 = strlen(a1);\n v9 = malloc(2 * v8);\n v7 = 0;\n for ( i = 0; i < v8; ++i )\n {\n if ( i > 0\n && ((*__ctype_b_loc())[a1[i]] & 0x100) != 0\n && (((*__ctype_b_loc())[a1[i - 1]] & 0x200) != 0 || ((*__ctype_b_loc())[a1[i - 1]] & 0x800) != 0)\n || i > 0\n && ((*__ctype_b_loc())[a1[i]] & 0x100) != 0\n && ((*__ctype_b_loc())[a1[i - 1]] & 0x100) != 0\n && ((*__ctype_b_loc())[a1[i + 1]] & 0x200) != 0 )\n {\n v9[v7] = 95;\n v1 = tolower(a1[i]);\n v2 = v7 + 1;\n v7 += 2;\n v9[v2] = v1;\n }\n else\n {\n v3 = tolower(a1[i]);\n v4 = v7++;\n v9[v4] = v3;\n }\n }\n v9[v7] = 0;\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1209(const char *a1) {\n char v1;\n int v2;\n char v3;\n int v4;\n int i;\n int v7;\n unsigned int v8;\n uint8_t *v9;\n v8 = strlen(a1);\n v9 = malloc(2 * v8);\n v7 = 0;\n for (i = 0; i < v8; ++i) {\n if (i > 0 && ((*__ctype_b_loc())[a1[i]] & 256) != 0 &&\n (((*__ctype_b_loc())[a1[i - 1]] & 512) != 0 ||\n ((*__ctype_b_loc())[a1[i - 1]] & 2048) != 0) ||\n i > 0 && ((*__ctype_b_loc())[a1[i]] & 256) != 0 &&\n ((*__ctype_b_loc())[a1[i - 1]] & 256) != 0 &&\n ((*__ctype_b_loc())[a1[i + 1]] & 512) != 0) {\n v9[v7] = 95;\n v1 = tolower(a1[i]);\n v2 = v7 + 1;\n v7 += 2;\n v9[v2] = v1;\n } else {\n v3 = tolower(a1[i]);\n v4 = v7++;\n v9[v4] = v3;\n }\n }\n v9[v7] = 0;\n return v9;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1) {\n char v1;\n int v2;\n char v3;\n int v4;\n int i;\n int v7;\n unsigned int v8;\n uint8_t *v9;\n v8 = strlen(a1);\n v9 = malloc(2 * v8);\n v7 = 0;\n for (i = 0; i < v8; ++i) {\n if (i > 0 && ((*__ctype_b_loc())[a1[i]] & 256) != 0 &&\n (((*__ctype_b_loc())[a1[i - 1]] & 512) != 0 ||\n ((*__ctype_b_loc())[a1[i - 1]] & 2048) != 0) ||\n i > 0 && ((*__ctype_b_loc())[a1[i]] & 256) != 0 &&\n ((*__ctype_b_loc())[a1[i - 1]] & 256) != 0 &&\n ((*__ctype_b_loc())[a1[i + 1]] & 512) != 0) {\n v9[v7] = 95;\n v1 = tolower(a1[i]);\n v2 = v7 + 1;\n v7 += 2;\n v9[v2] = v1;\n } else {\n v3 = tolower(a1[i]);\n v4 = v7++;\n v9[v4] = v3;\n }\n }\n v9[v7] = 0;\n return v9;\n}" + }, + { + "index": 933, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n size_t length = strlen(text);\n size_t new_length = 0;\n char* result = (char*)malloc(sizeof(char) * (length * 2));\n int i, j = 0;\n for (i = 0; i < length; i++) {\n if (i > 0 && isupper(text[i]) &&\n (islower(text[i - 1]) || isdigit(text[i - 1]))) {\n result[j++] = '_';\n result[j++] = tolower(text[i]);\n } else if (i > 0 && isupper(text[i]) && isupper(text[i - 1]) &&\n islower(text[i + 1])) {\n result[j++] = '_';\n result[j++] = tolower(text[i]);\n } else {\n result[j++] = tolower(text[i]);\n }\n }\n result[j] = '\\0';\n return result;\n}", + "test": "int main() {\n\n char* result;\n\n\n\n result = func0(\"GoogleAssistant\");\n\n assert(strcmp(result, \"google_assistant\") == 0);\n\n free(result);\n\n\n\n result = func0(\"ChromeCast\");\n\n assert(strcmp(result, \"chrome_cast\") == 0);\n\n free(result);\n\n\n\n result = func0(\"QuadCore\");\n\n assert(strcmp(result, \"quad_core\") == 0);\n\n free(result);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov %rdi,%r12\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nlea -0x1(%rcx),%r13\nlea 0x0(%r13,%r13,1),%rdi\ncallq 10b0 \nmov %rax,%r14\ntest %r13,%r13\nje 12e0 \nmov $0x0,%ebx\nmov $0x0,%ebp\njmp 1286 \ntest %ax,%ax\nje 1260 \nmovsbq -0x1(%r12,%rbx,1),%rax\ntestb $0x1,0x1(%rdx,%rax,2)\nje 1260 \nmovsbq 0x1(%r12,%rbx,1),%rax\ntestb $0x2,0x1(%rdx,%rax,2)\nje 1260 \nlea 0x1(%rbp),%eax\nmov %eax,0xc(%rsp)\nmovslq %ebp,%rax\nmovb $0x5f,(%r14,%rax,1)\ncallq 10c0 <__ctype_tolower_loc@plt>\nmov %rax,%rdx\nadd $0x2,%ebp\nmovslq 0xc(%rsp),%rax\nmov (%rdx),%rdx\nmov (%rdx,%r15,4),%edx\nmov %dl,(%r14,%rax,1)\njmp 127d \ncallq 10c0 <__ctype_tolower_loc@plt>\nmov %rax,%rdx\nmovslq %ebp,%rax\nmovsbq (%r12,%rbx,1),%rcx\nmov (%rdx),%rdx\nmov (%rdx,%rcx,4),%edx\nmov %dl,(%r14,%rax,1)\nlea 0x1(%rbp),%ebp\nadd $0x1,%rbx\ncmp %rbx,%r13\nje 12e5 \ntest %ebx,%ebx\njle 1260 \ncallq 10d0 <__ctype_b_loc@plt>\nmov (%rax),%rdx\nmovsbq (%r12,%rbx,1),%r15\nmovzwl (%rdx,%r15,2),%eax\nand $0x100,%ax\nje 1260 \nmovsbq -0x1(%r12,%rbx,1),%rcx\ntestw $0xa00,(%rdx,%rcx,2)\nje 1215 \nlea 0x1(%rbp),%eax\nmov %eax,0xc(%rsp)\nmovslq %ebp,%rax\nmovb $0x5f,(%r14,%rax,1)\ncallq 10c0 <__ctype_tolower_loc@plt>\nmov %rax,%rdx\nadd $0x2,%ebp\nmovslq 0xc(%rsp),%rax\nmov (%rdx),%rdx\nmov (%rdx,%r15,4),%edx\nmov %dl,(%r14,%rax,1)\njmp 127d \nmov $0x0,%ebp\nmovslq %ebp,%rbp\nmovb $0x0,(%r14,%rbp,1)\nmov %r14,%rax\nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov rbx, rdi\ncall _strlen\nmov r14, rax\nlea rdi, [rax+rax]; size\ncall _malloc\nmov r13, rax\ntest r14, r14\njz loc_1310\nmov r12d, 0\nmov ebp, 0\njmp short loc_12B5\nloc_1248:\ntest dh, 1\njz short loc_128A\nmovsx rdx, byte ptr [rbx+1]\ntest byte ptr [rax+rdx*2+1], 2\njz short loc_128A\nlea eax, [r12+1]\nmov [rsp+48h+var_3C], eax\nmovsxd rax, r12d\nmov byte ptr [r13+rax+0], 5Fh ; '_'\ncall ___ctype_tolower_loc\nmov rdx, rax\nadd r12d, 2\nmovsxd rax, [rsp+48h+var_3C]\nmov rdx, [rdx]\nmov edx, [rdx+r15*4]\nmov [r13+rax+0], dl\njmp short loc_12A9\nloc_128A:\ncall ___ctype_tolower_loc\nmov rdx, rax\nmovsxd rax, r12d\nmovsx rcx, byte ptr [rbx]\nmov rdx, [rdx]\nmov edx, [rdx+rcx*4]\nmov [r13+rax+0], dl\nlea r12d, [r12+1]\nloc_12A9:\nadd ebp, 1\nadd rbx, 1\ncmp ebp, r14d\njz short loc_1316\nloc_12B5:\ntest ebp, ebp\njle short loc_128A\ncall ___ctype_b_loc\nmov rax, [rax]\nmovsx r15, byte ptr [rbx]\ntest byte ptr [rax+r15*2+1], 1\njz short loc_128A\nmovsx rdx, byte ptr [rbx-1]\nmovzx edx, word ptr [rax+rdx*2]\ntest dh, 0Ah\njz loc_1248\nlea eax, [r12+1]\nmov [rsp+48h+var_3C], eax\nmovsxd rax, r12d\nmov byte ptr [r13+rax+0], 5Fh ; '_'\ncall ___ctype_tolower_loc\nmov rdx, rax\nadd r12d, 2\nmovsxd rax, [rsp+48h+var_3C]\nmov rdx, [rdx]\nmov edx, [rdx+r15*4]\nmov [r13+rax+0], dl\njmp short loc_12A9\nloc_1310:\nmov r12d, 0\nloc_1316:\nmovsxd r12, r12d\nmov byte ptr [r13+r12+0], 0\nmov rax, r13\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1)\n{\n const char *v1; // rbx\n size_t v2; // r14\n _BYTE *v3; // r13\n int v4; // r12d\n int v5; // ebp\n const unsigned __int16 *v6; // rax\n __int64 v7; // r15\n unsigned __int16 v8; // dx\n int v10; // [rsp+Ch] [rbp-3Ch]\n\n v1 = a1;\n v2 = strlen(a1);\n v3 = malloc(2 * v2);\n if ( v2 )\n {\n v4 = 0;\n v5 = 0;\n do\n {\n if ( v5 > 0\n && (v6 = *__ctype_b_loc(), v7 = *v1, (v6[v7] & 0x100) != 0)\n && ((v8 = v6[*(v1 - 1)], (v8 & 0xA00) != 0) || (v8 & 0x100) != 0 && (v6[v1[1]] & 0x200) != 0) )\n {\n v10 = v4 + 1;\n v3[v4] = 95;\n v4 += 2;\n v3[v10] = (*__ctype_tolower_loc())[v7];\n }\n else\n {\n v3[v4++] = (*__ctype_tolower_loc())[*v1];\n }\n ++v5;\n ++v1;\n }\n while ( v5 != (_DWORD)v2 );\n }\n else\n {\n v4 = 0;\n }\n v3[v4] = 0;\n return v3;\n}", + "ida_strip_asm": "sub_1209:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov rbx, rdi\ncall _strlen\nmov r14, rax\nlea rdi, [rax+rax]; size\ncall _malloc\nmov r13, rax\ntest r14, r14\njz loc_1310\nmov r12d, 0\nmov ebp, 0\njmp short loc_12B5\nloc_1248:\ntest dh, 1\njz short loc_128A\nmovsx rdx, byte ptr [rbx+1]\ntest byte ptr [rax+rdx*2+1], 2\njz short loc_128A\nlea eax, [r12+1]\nmov [rsp+48h+var_3C], eax\nmovsxd rax, r12d\nmov byte ptr [r13+rax+0], 5Fh ; '_'\ncall ___ctype_tolower_loc\nmov rdx, rax\nadd r12d, 2\nmovsxd rax, [rsp+48h+var_3C]\nmov rdx, [rdx]\nmov edx, [rdx+r15*4]\nmov [r13+rax+0], dl\njmp short loc_12A9\nloc_128A:\ncall ___ctype_tolower_loc\nmov rdx, rax\nmovsxd rax, r12d\nmovsx rcx, byte ptr [rbx]\nmov rdx, [rdx]\nmov edx, [rdx+rcx*4]\nmov [r13+rax+0], dl\nlea r12d, [r12+1]\nloc_12A9:\nadd ebp, 1\nadd rbx, 1\ncmp ebp, r14d\njz short loc_1316\nloc_12B5:\ntest ebp, ebp\njle short loc_128A\ncall ___ctype_b_loc\nmov rax, [rax]\nmovsx r15, byte ptr [rbx]\ntest byte ptr [rax+r15*2+1], 1\njz short loc_128A\nmovsx rdx, byte ptr [rbx-1]\nmovzx edx, word ptr [rax+rdx*2]\ntest dh, 0Ah\njz loc_1248\nlea eax, [r12+1]\nmov [rsp+48h+var_3C], eax\nmovsxd rax, r12d\nmov byte ptr [r13+rax+0], 5Fh ; '_'\ncall ___ctype_tolower_loc\nmov rdx, rax\nadd r12d, 2\nmovsxd rax, [rsp+48h+var_3C]\nmov rdx, [rdx]\nmov edx, [rdx+r15*4]\nmov [r13+rax+0], dl\njmp short loc_12A9\nloc_1310:\nmov r12d, 0\nloc_1316:\nmovsxd r12, r12d\nmov byte ptr [r13+r12+0], 0\nmov rax, r13\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1209(const char *a1)\n{\n const char *v1; // rbx\n size_t v2; // r14\n _BYTE *v3; // r13\n int v4; // r12d\n int v5; // ebp\n const unsigned __int16 *v6; // rax\n __int64 v7; // r15\n unsigned __int16 v8; // dx\n int v10; // [rsp+Ch] [rbp-3Ch]\n\n v1 = a1;\n v2 = strlen(a1);\n v3 = malloc(2 * v2);\n if ( v2 )\n {\n v4 = 0;\n v5 = 0;\n do\n {\n if ( v5 > 0\n && (v6 = *__ctype_b_loc(), v7 = *v1, (v6[v7] & 0x100) != 0)\n && ((v8 = v6[*(v1 - 1)], (v8 & 0xA00) != 0) || (v8 & 0x100) != 0 && (v6[v1[1]] & 0x200) != 0) )\n {\n v10 = v4 + 1;\n v3[v4] = 95;\n v4 += 2;\n v3[v10] = (*__ctype_tolower_loc())[v7];\n }\n else\n {\n v3[v4++] = (*__ctype_tolower_loc())[*v1];\n }\n ++v5;\n ++v1;\n }\n while ( v5 != (_DWORD)v2 );\n }\n else\n {\n v4 = 0;\n }\n v3[v4] = 0;\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1209(const char *a1) {\n const char *v1;\n unsigned int v2;\n uint8_t *v3;\n int v4;\n int v5;\n const unsigned short *v6;\n long long v7;\n unsigned short v8;\n int v10;\n v1 = a1;\n v2 = strlen(a1);\n v3 = malloc(2 * v2);\n if (v2) {\n v4 = 0;\n v5 = 0;\n do {\n if (v5 > 0 && (v6 = *__ctype_b_loc(), v7 = *v1, (v6[v7] & 256) != 0) &&\n ((v8 = v6[*(v1 - 1)], (v8 & 2560) != 0) ||\n (v8 & 256) != 0 && (v6[v1[1]] & 512) != 0)) {\n v10 = v4 + 1;\n v3[v4] = 95;\n v4 += 2;\n v3[v10] = (*__ctype_tolower_loc())[v7];\n } else {\n v3[v4++] = (*__ctype_tolower_loc())[*v1];\n }\n ++v5;\n ++v1;\n } while (v5 != (uint32_t)v2);\n } else {\n v4 = 0;\n }\n v3[v4] = 0;\n return v3;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1) {\n const char *v1;\n unsigned int v2;\n uint8_t *v3;\n int v4;\n int v5;\n const unsigned short *v6;\n long long v7;\n unsigned short v8;\n int v10;\n v1 = a1;\n v2 = strlen(a1);\n v3 = malloc(2 * v2);\n if (v2) {\n v4 = 0;\n v5 = 0;\n do {\n if (v5 > 0 && (v6 = *__ctype_b_loc(), v7 = *v1, (v6[v7] & 256) != 0) &&\n ((v8 = v6[*(v1 - 1)], (v8 & 2560) != 0) ||\n (v8 & 256) != 0 && (v6[v1[1]] & 512) != 0)) {\n v10 = v4 + 1;\n v3[v4] = 95;\n v4 += 2;\n v3[v10] = (*__ctype_tolower_loc())[v7];\n } else {\n v3[v4++] = (*__ctype_tolower_loc())[*v1];\n }\n ++v5;\n ++v1;\n } while (v5 != (uint32_t)v2);\n } else {\n v4 = 0;\n }\n v3[v4] = 0;\n return v3;\n}" + }, + { + "index": 933, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n size_t length = strlen(text);\n size_t new_length = 0;\n char* result = (char*)malloc(sizeof(char) * (length * 2));\n int i, j = 0;\n for (i = 0; i < length; i++) {\n if (i > 0 && isupper(text[i]) &&\n (islower(text[i - 1]) || isdigit(text[i - 1]))) {\n result[j++] = '_';\n result[j++] = tolower(text[i]);\n } else if (i > 0 && isupper(text[i]) && isupper(text[i - 1]) &&\n islower(text[i + 1])) {\n result[j++] = '_';\n result[j++] = tolower(text[i]);\n } else {\n result[j++] = tolower(text[i]);\n }\n }\n result[j] = '\\0';\n return result;\n}", + "test": "int main() {\n\n char* result;\n\n\n\n result = func0(\"GoogleAssistant\");\n\n assert(strcmp(result, \"google_assistant\") == 0);\n\n free(result);\n\n\n\n result = func0(\"ChromeCast\");\n\n assert(strcmp(result, \"chrome_cast\") == 0);\n\n free(result);\n\n\n\n result = func0(\"QuadCore\");\n\n assert(strcmp(result, \"quad_core\") == 0);\n\n free(result);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\nmov %rdi,%r12\npush %rbp\npush %rbx\nsub $0x28,%rsp\ncallq 10b0 \nlea (%rax,%rax,1),%rdi\nmov %rax,0x10(%rsp)\nmov %rax,%rbx\ncallq 10d0 \nmov %rax,%r13\ntest %rbx,%rbx\nje 1410 \ncallq 10e0 <__ctype_tolower_loc@plt>\nxor %ebx,%ebx\nxor %ebp,%ebp\nmov (%rax),%rax\nmov %rax,0x18(%rsp)\njmp 139e \nnopw 0x0(%rax,%rax,1)\nmovzbl (%r12,%rbx,1),%eax\nmov %ecx,0xc(%rsp)\nmov %al,0xb(%rsp)\ncallq 10f0 <__ctype_b_loc@plt>\nmov 0xc(%rsp),%ecx\nmov (%rax),%rdi\nmovsbq 0xb(%rsp),%rax\ntestb $0x1,0x1(%rdi,%rax,2)\nje 13b6 \nmovsbq -0x1(%r12,%rbx,1),%r9\nmovzwl (%rdi,%r9,2),%r9d\ntest $0xa00,%r9w\nje 13f0 \nmov 0x18(%rsp),%rsi\nmovb $0x5f,(%r14)\nadd $0x2,%ebp\nadd $0x1,%rbx\nmov (%rsi,%rax,4),%eax\nmov %al,(%r15)\nmovslq %ebp,%rax\nlea 0x0(%r13,%rax,1),%r15\ncmp %rbx,0x10(%rsp)\nje 13d3 \nlea 0x1(%rbp),%ecx\nmovslq %ecx,%rax\nlea 0x0(%r13,%rax,1),%r15\nmovslq %ebp,%rax\nlea 0x0(%r13,%rax,1),%r14\ntest %rbx,%rbx\njne 1340 \nmovsbq (%r12,%rbx,1),%rax\nmov 0x18(%rsp),%rdx\nmov %ecx,%ebp\nadd $0x1,%rbx\nmov (%rdx,%rax,4),%eax\nmov %al,(%r14)\ncmp %rbx,0x10(%rsp)\njne 139e \nmovb $0x0,(%r15)\nadd $0x28,%rsp\nmov %r13,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\ntest $0x100,%r9w\nje 13b6 \nmovsbq 0x1(%r12,%rbx,1),%r9\ntestb $0x2,0x1(%rdi,%r9,2)\nje 13b6 \njmpq 1379 \nnopl 0x0(%rax,%rax,1)\nmov %rax,%r15\njmp 13d3 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 28h\ncall _strlen\nlea rdi, [rax+rax]; size\nmov [rsp+58h+var_48], rax\nmov rbx, rax\ncall _malloc\nmov r14, rax\ntest rbx, rbx\njz loc_1418\ncall ___ctype_tolower_loc\nxor ebx, ebx\nxor r15d, r15d\nmov rax, [rax]\nmov [rsp+58h+var_40], rax\nnop dword ptr [rax+00000000h]\nloc_1350:\nmovzx ebp, byte ptr [r12+rbx]\nmovsxd rax, r15d\nlea r13d, [r15+1]\nlea rdx, [r14+rax]\nmovsx rax, bpl\ntest rbx, rbx\njz short loc_13C0\nmov [rsp+58h+var_50], rdx\ncall ___ctype_b_loc\nmov rdx, [rsp+58h+var_50]\nmov rdi, [rax]\nmovsx rax, bpl\ntest byte ptr [rdi+rax*2+1], 1\njz short loc_13C0\nmovsxd r8, r13d\nlea r9, [r14+r8]\nmovsx r8, byte ptr [r12+rbx-1]\nmovzx r8d, word ptr [rdi+r8*2]\ntest r8w, 0A00h\njnz short loc_1400\ntest r8w, 100h\njz short loc_13C0\nmovsx r8, byte ptr [r12+rbx+1]\ntest byte ptr [rdi+r8*2+1], 2\njnz short loc_1400\nnop word ptr [rax+rax+00000000h]\nloc_13C0:\nmov rcx, [rsp+58h+var_40]\nmov r15d, r13d\nmov eax, [rcx+rax*4]\nmov [rdx], al\nloc_13CD:\nadd rbx, 1\ncmp [rsp+58h+var_48], rbx\njnz loc_1350\nmovsxd r15, r15d\nadd r15, r14\nloc_13E2:\nmov byte ptr [r15], 0\nadd rsp, 28h\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1400:\nmov rsi, [rsp+58h+var_40]\nmov byte ptr [rdx], 5Fh ; '_'\nadd r15d, 2\nmov eax, [rsi+rax*4]\nmov [r9], al\njmp short loc_13CD\nloc_1418:\nmov r15, rax\njmp short loc_13E2", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1)\n{\n _BYTE *v2; // rax\n _BYTE *v3; // r14\n __int64 v4; // rbx\n int v5; // r15d\n char v6; // bp\n int v7; // r13d\n _BYTE *v8; // rdx\n __int64 v9; // rax\n const unsigned __int16 **v10; // rax\n const unsigned __int16 *v11; // rdi\n unsigned __int16 v12; // r8\n _BYTE *v13; // r15\n size_t v15; // [rsp+10h] [rbp-48h]\n const __int32_t *v16; // [rsp+18h] [rbp-40h]\n\n v15 = strlen(a1);\n v2 = malloc(2 * v15);\n v3 = v2;\n if ( v15 )\n {\n v4 = 0LL;\n v5 = 0;\n v16 = *__ctype_tolower_loc();\n do\n {\n v6 = a1[v4];\n v7 = v5 + 1;\n v8 = &v3[v5];\n v9 = v6;\n if ( v4\n && (v10 = __ctype_b_loc(), v8 = &v3[v5], v11 = *v10, v9 = v6, (v11[v6] & 0x100) != 0)\n && ((v12 = v11[a1[v4 - 1]], (v12 & 0xA00) != 0) || (v12 & 0x100) != 0 && (v11[a1[v4 + 1]] & 0x200) != 0) )\n {\n v3[v5] = 95;\n v5 += 2;\n v3[v7] = v16[v6];\n }\n else\n {\n ++v5;\n *v8 = v16[v9];\n }\n ++v4;\n }\n while ( v15 != v4 );\n v13 = &v3[v5];\n }\n else\n {\n v13 = v2;\n }\n *v13 = 0;\n return v3;\n}", + "ida_strip_asm": "sub_1300:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 28h\ncall _strlen\nlea rdi, [rax+rax]; size\nmov [rsp+58h+var_48], rax\nmov rbx, rax\ncall _malloc\nmov r14, rax\ntest rbx, rbx\njz loc_1418\ncall ___ctype_tolower_loc\nxor ebx, ebx\nxor r15d, r15d\nmov rax, [rax]\nmov [rsp+58h+var_40], rax\nnop dword ptr [rax+00000000h]\nloc_1350:\nmovzx ebp, byte ptr [r12+rbx]\nmovsxd rax, r15d\nlea r13d, [r15+1]\nlea rdx, [r14+rax]\nmovsx rax, bpl\ntest rbx, rbx\njz short loc_13C0\nmov [rsp+58h+var_50], rdx\ncall ___ctype_b_loc\nmov rdx, [rsp+58h+var_50]\nmov rdi, [rax]\nmovsx rax, bpl\ntest byte ptr [rdi+rax*2+1], 1\njz short loc_13C0\nmovsxd r8, r13d\nlea r9, [r14+r8]\nmovsx r8, byte ptr [r12+rbx-1]\nmovzx r8d, word ptr [rdi+r8*2]\ntest r8w, 0A00h\njnz short loc_1400\ntest r8w, 100h\njz short loc_13C0\nmovsx r8, byte ptr [r12+rbx+1]\ntest byte ptr [rdi+r8*2+1], 2\njnz short loc_1400\nnop word ptr [rax+rax+00000000h]\nloc_13C0:\nmov rcx, [rsp+58h+var_40]\nmov r15d, r13d\nmov eax, [rcx+rax*4]\nmov [rdx], al\nloc_13CD:\nadd rbx, 1\ncmp [rsp+58h+var_48], rbx\njnz loc_1350\nmovsxd r15, r15d\nadd r15, r14\nloc_13E2:\nmov byte ptr [r15], 0\nadd rsp, 28h\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1400:\nmov rsi, [rsp+58h+var_40]\nmov byte ptr [rdx], 5Fh ; '_'\nadd r15d, 2\nmov eax, [rsi+rax*4]\nmov [r9], al\njmp short loc_13CD\nloc_1418:\nmov r15, rax\njmp short loc_13E2", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1300(const char *a1)\n{\n _BYTE *v2; // rax\n _BYTE *v3; // r14\n __int64 v4; // rbx\n int v5; // r15d\n char v6; // bp\n int v7; // r13d\n _BYTE *v8; // rdx\n __int64 v9; // rax\n const unsigned __int16 **v10; // rax\n const unsigned __int16 *v11; // rdi\n unsigned __int16 v12; // r8\n _BYTE *v13; // r15\n size_t v15; // [rsp+10h] [rbp-48h]\n const __int32_t *v16; // [rsp+18h] [rbp-40h]\n\n v15 = strlen(a1);\n v2 = malloc(2 * v15);\n v3 = v2;\n if ( v15 )\n {\n v4 = 0LL;\n v5 = 0;\n v16 = *__ctype_tolower_loc();\n do\n {\n v6 = a1[v4];\n v7 = v5 + 1;\n v8 = &v3[v5];\n v9 = v6;\n if ( v4\n && (v10 = __ctype_b_loc(), v8 = &v3[v5], v11 = *v10, v9 = v6, (v11[v6] & 0x100) != 0)\n && ((v12 = v11[a1[v4 - 1]], (v12 & 0xA00) != 0) || (v12 & 0x100) != 0 && (v11[a1[v4 + 1]] & 0x200) != 0) )\n {\n v3[v5] = 95;\n v5 += 2;\n v3[v7] = v16[v6];\n }\n else\n {\n ++v5;\n *v8 = v16[v9];\n }\n ++v4;\n }\n while ( v15 != v4 );\n v13 = &v3[v5];\n }\n else\n {\n v13 = v2;\n }\n *v13 = 0;\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1300(const char *a1) {\n uint8_t *v2;\n uint8_t *v3;\n long long v4;\n int v5;\n char v6;\n int v7;\n uint8_t *v8;\n long long v9;\n const unsigned short **v10;\n const unsigned short *v11;\n unsigned short v12;\n uint8_t *v13;\n unsigned int v15;\n const __int32_t *v16;\n v15 = strlen(a1);\n v2 = malloc(2 * v15);\n v3 = v2;\n if (v15) {\n v4 = 0LL;\n v5 = 0;\n v16 = *__ctype_tolower_loc();\n do {\n v6 = a1[v4];\n v7 = v5 + 1;\n v8 = &v3[v5];\n v9 = v6;\n if (v4 &&\n (v10 = __ctype_b_loc(), v8 = &v3[v5], v11 = *v10, v9 = v6,\n (v11[v6] & 256) != 0) &&\n ((v12 = v11[a1[v4 - 1]], (v12 & 2560) != 0) ||\n (v12 & 256) != 0 && (v11[a1[v4 + 1]] & 512) != 0)) {\n v3[v5] = 95;\n v5 += 2;\n v3[v7] = v16[v6];\n } else {\n ++v5;\n *v8 = v16[v9];\n }\n ++v4;\n } while (v15 != v4);\n v13 = &v3[v5];\n } else {\n v13 = v2;\n }\n *v13 = 0;\n return v3;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1) {\n uint8_t *v2;\n uint8_t *v3;\n long long v4;\n int v5;\n char v6;\n int v7;\n uint8_t *v8;\n long long v9;\n const unsigned short **v10;\n const unsigned short *v11;\n unsigned short v12;\n uint8_t *v13;\n unsigned int v15;\n const __int32_t *v16;\n v15 = strlen(a1);\n v2 = malloc(2 * v15);\n v3 = v2;\n if (v15) {\n v4 = 0LL;\n v5 = 0;\n v16 = *__ctype_tolower_loc();\n do {\n v6 = a1[v4];\n v7 = v5 + 1;\n v8 = &v3[v5];\n v9 = v6;\n if (v4 &&\n (v10 = __ctype_b_loc(), v8 = &v3[v5], v11 = *v10, v9 = v6,\n (v11[v6] & 256) != 0) &&\n ((v12 = v11[a1[v4 - 1]], (v12 & 2560) != 0) ||\n (v12 & 256) != 0 && (v11[a1[v4 + 1]] & 512) != 0)) {\n v3[v5] = 95;\n v5 += 2;\n v3[v7] = v16[v6];\n } else {\n ++v5;\n *v8 = v16[v9];\n }\n ++v4;\n } while (v15 != v4);\n v13 = &v3[v5];\n } else {\n v13 = v2;\n }\n *v13 = 0;\n return v3;\n}" + }, + { + "index": 933, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n size_t length = strlen(text);\n size_t new_length = 0;\n char* result = (char*)malloc(sizeof(char) * (length * 2));\n int i, j = 0;\n for (i = 0; i < length; i++) {\n if (i > 0 && isupper(text[i]) &&\n (islower(text[i - 1]) || isdigit(text[i - 1]))) {\n result[j++] = '_';\n result[j++] = tolower(text[i]);\n } else if (i > 0 && isupper(text[i]) && isupper(text[i - 1]) &&\n islower(text[i + 1])) {\n result[j++] = '_';\n result[j++] = tolower(text[i]);\n } else {\n result[j++] = tolower(text[i]);\n }\n }\n result[j] = '\\0';\n return result;\n}", + "test": "int main() {\n\n char* result;\n\n\n\n result = func0(\"GoogleAssistant\");\n\n assert(strcmp(result, \"google_assistant\") == 0);\n\n free(result);\n\n\n\n result = func0(\"ChromeCast\");\n\n assert(strcmp(result, \"chrome_cast\") == 0);\n\n free(result);\n\n\n\n result = func0(\"QuadCore\");\n\n assert(strcmp(result, \"quad_core\") == 0);\n\n free(result);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\nmov %rdi,%r12\npush %rbp\npush %rbx\nsub $0x28,%rsp\ncallq 10b0 \nlea (%rax,%rax,1),%rdi\nmov %rax,0x10(%rsp)\nmov %rax,%rbx\ncallq 10d0 \nmov %rax,%r13\ntest %rbx,%rbx\nje 1410 \ncallq 10e0 <__ctype_tolower_loc@plt>\nxor %ebx,%ebx\nxor %ebp,%ebp\nmov (%rax),%rax\nmov %rax,0x18(%rsp)\njmp 139e \nnopw 0x0(%rax,%rax,1)\nmovzbl (%r12,%rbx,1),%eax\nmov %ecx,0xc(%rsp)\nmov %al,0xb(%rsp)\ncallq 10f0 <__ctype_b_loc@plt>\nmov 0xc(%rsp),%ecx\nmov (%rax),%rdi\nmovsbq 0xb(%rsp),%rax\ntestb $0x1,0x1(%rdi,%rax,2)\nje 13b6 \nmovsbq -0x1(%r12,%rbx,1),%r9\nmovzwl (%rdi,%r9,2),%r9d\ntest $0xa00,%r9w\nje 13f0 \nmov 0x18(%rsp),%rsi\nmovb $0x5f,(%r14)\nadd $0x2,%ebp\nadd $0x1,%rbx\nmov (%rsi,%rax,4),%eax\nmov %al,(%r15)\nmovslq %ebp,%rax\nlea 0x0(%r13,%rax,1),%r15\ncmp %rbx,0x10(%rsp)\nje 13d3 \nlea 0x1(%rbp),%ecx\nmovslq %ecx,%rax\nlea 0x0(%r13,%rax,1),%r15\nmovslq %ebp,%rax\nlea 0x0(%r13,%rax,1),%r14\ntest %rbx,%rbx\njne 1340 \nmovsbq (%r12,%rbx,1),%rax\nmov 0x18(%rsp),%rdx\nmov %ecx,%ebp\nadd $0x1,%rbx\nmov (%rdx,%rax,4),%eax\nmov %al,(%r14)\ncmp %rbx,0x10(%rsp)\njne 139e \nmovb $0x0,(%r15)\nadd $0x28,%rsp\nmov %r13,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\ntest $0x100,%r9w\nje 13b6 \nmovsbq 0x1(%r12,%rbx,1),%r9\ntestb $0x2,0x1(%rdi,%r9,2)\nje 13b6 \njmpq 1379 \nnopl 0x0(%rax,%rax,1)\nmov %rax,%r15\njmp 13d3 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 28h\ncall _strlen\nlea rdi, [rax+rax]; size\nmov [rsp+58h+var_48], rax\nmov rbx, rax\ncall _malloc\nmov r14, rax\ntest rbx, rbx\njz loc_1418\ncall ___ctype_tolower_loc\nxor ebx, ebx\nxor r15d, r15d\nmov rax, [rax]\nmov [rsp+58h+var_40], rax\nnop dword ptr [rax+00000000h]\nloc_1350:\nmovzx ebp, byte ptr [r12+rbx]\nmovsxd rax, r15d\nlea r13d, [r15+1]\nlea rdx, [r14+rax]\nmovsx rax, bpl\ntest rbx, rbx\njz short loc_13C0\nmov [rsp+58h+var_50], rdx\ncall ___ctype_b_loc\nmov rdx, [rsp+58h+var_50]\nmov rdi, [rax]\nmovsx rax, bpl\ntest byte ptr [rdi+rax*2+1], 1\njz short loc_13C0\nmovsxd r8, r13d\nlea r9, [r14+r8]\nmovsx r8, byte ptr [r12+rbx-1]\nmovzx r8d, word ptr [rdi+r8*2]\ntest r8w, 0A00h\njnz short loc_1400\ntest r8w, 100h\njz short loc_13C0\nmovsx r8, byte ptr [r12+rbx+1]\ntest byte ptr [rdi+r8*2+1], 2\njnz short loc_1400\nnop word ptr [rax+rax+00000000h]\nloc_13C0:\nmov rcx, [rsp+58h+var_40]\nmov r15d, r13d\nmov eax, [rcx+rax*4]\nmov [rdx], al\nloc_13CD:\nadd rbx, 1\ncmp [rsp+58h+var_48], rbx\njnz loc_1350\nmovsxd r15, r15d\nadd r15, r14\nloc_13E2:\nmov byte ptr [r15], 0\nadd rsp, 28h\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1400:\nmov rsi, [rsp+58h+var_40]\nmov byte ptr [rdx], 5Fh ; '_'\nadd r15d, 2\nmov eax, [rsi+rax*4]\nmov [r9], al\njmp short loc_13CD\nloc_1418:\nmov r15, rax\njmp short loc_13E2", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1)\n{\n _BYTE *v2; // rax\n _BYTE *v3; // r14\n __int64 v4; // rbx\n int v5; // r15d\n char v6; // bp\n int v7; // r13d\n _BYTE *v8; // rdx\n __int64 v9; // rax\n const unsigned __int16 **v10; // rax\n const unsigned __int16 *v11; // rdi\n unsigned __int16 v12; // r8\n _BYTE *v13; // r15\n size_t v15; // [rsp+10h] [rbp-48h]\n const __int32_t *v16; // [rsp+18h] [rbp-40h]\n\n v15 = strlen(a1);\n v2 = malloc(2 * v15);\n v3 = v2;\n if ( v15 )\n {\n v4 = 0LL;\n v5 = 0;\n v16 = *__ctype_tolower_loc();\n do\n {\n v6 = a1[v4];\n v7 = v5 + 1;\n v8 = &v3[v5];\n v9 = v6;\n if ( v4\n && (v10 = __ctype_b_loc(), v8 = &v3[v5], v11 = *v10, v9 = v6, (v11[v6] & 0x100) != 0)\n && ((v12 = v11[a1[v4 - 1]], (v12 & 0xA00) != 0) || (v12 & 0x100) != 0 && (v11[a1[v4 + 1]] & 0x200) != 0) )\n {\n v3[v5] = 95;\n v5 += 2;\n v3[v7] = v16[v6];\n }\n else\n {\n ++v5;\n *v8 = v16[v9];\n }\n ++v4;\n }\n while ( v15 != v4 );\n v13 = &v3[v5];\n }\n else\n {\n v13 = v2;\n }\n *v13 = 0;\n return v3;\n}", + "ida_strip_asm": "sub_1300:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12, rdi\npush rbp\npush rbx\nsub rsp, 28h\ncall _strlen\nlea rdi, [rax+rax]; size\nmov [rsp+58h+var_48], rax\nmov rbx, rax\ncall _malloc\nmov r14, rax\ntest rbx, rbx\njz loc_1418\ncall ___ctype_tolower_loc\nxor ebx, ebx\nxor r15d, r15d\nmov rax, [rax]\nmov [rsp+58h+var_40], rax\nnop dword ptr [rax+00000000h]\nloc_1350:\nmovzx ebp, byte ptr [r12+rbx]\nmovsxd rax, r15d\nlea r13d, [r15+1]\nlea rdx, [r14+rax]\nmovsx rax, bpl\ntest rbx, rbx\njz short loc_13C0\nmov [rsp+58h+var_50], rdx\ncall ___ctype_b_loc\nmov rdx, [rsp+58h+var_50]\nmov rdi, [rax]\nmovsx rax, bpl\ntest byte ptr [rdi+rax*2+1], 1\njz short loc_13C0\nmovsxd r8, r13d\nlea r9, [r14+r8]\nmovsx r8, byte ptr [r12+rbx-1]\nmovzx r8d, word ptr [rdi+r8*2]\ntest r8w, 0A00h\njnz short loc_1400\ntest r8w, 100h\njz short loc_13C0\nmovsx r8, byte ptr [r12+rbx+1]\ntest byte ptr [rdi+r8*2+1], 2\njnz short loc_1400\nnop word ptr [rax+rax+00000000h]\nloc_13C0:\nmov rcx, [rsp+58h+var_40]\nmov r15d, r13d\nmov eax, [rcx+rax*4]\nmov [rdx], al\nloc_13CD:\nadd rbx, 1\ncmp [rsp+58h+var_48], rbx\njnz loc_1350\nmovsxd r15, r15d\nadd r15, r14\nloc_13E2:\nmov byte ptr [r15], 0\nadd rsp, 28h\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1400:\nmov rsi, [rsp+58h+var_40]\nmov byte ptr [rdx], 5Fh ; '_'\nadd r15d, 2\nmov eax, [rsi+rax*4]\nmov [r9], al\njmp short loc_13CD\nloc_1418:\nmov r15, rax\njmp short loc_13E2", + "ida_strip_pseudo": "_BYTE *__fastcall sub_1300(const char *a1)\n{\n _BYTE *v2; // rax\n _BYTE *v3; // r14\n __int64 v4; // rbx\n int v5; // r15d\n char v6; // bp\n int v7; // r13d\n _BYTE *v8; // rdx\n __int64 v9; // rax\n const unsigned __int16 **v10; // rax\n const unsigned __int16 *v11; // rdi\n unsigned __int16 v12; // r8\n _BYTE *v13; // r15\n size_t v15; // [rsp+10h] [rbp-48h]\n const __int32_t *v16; // [rsp+18h] [rbp-40h]\n\n v15 = strlen(a1);\n v2 = malloc(2 * v15);\n v3 = v2;\n if ( v15 )\n {\n v4 = 0LL;\n v5 = 0;\n v16 = *__ctype_tolower_loc();\n do\n {\n v6 = a1[v4];\n v7 = v5 + 1;\n v8 = &v3[v5];\n v9 = v6;\n if ( v4\n && (v10 = __ctype_b_loc(), v8 = &v3[v5], v11 = *v10, v9 = v6, (v11[v6] & 0x100) != 0)\n && ((v12 = v11[a1[v4 - 1]], (v12 & 0xA00) != 0) || (v12 & 0x100) != 0 && (v11[a1[v4 + 1]] & 0x200) != 0) )\n {\n v3[v5] = 95;\n v5 += 2;\n v3[v7] = v16[v6];\n }\n else\n {\n ++v5;\n *v8 = v16[v9];\n }\n ++v4;\n }\n while ( v15 != v4 );\n v13 = &v3[v5];\n }\n else\n {\n v13 = v2;\n }\n *v13 = 0;\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_1300(const char *a1) {\n uint8_t *v2;\n uint8_t *v3;\n long long v4;\n int v5;\n char v6;\n int v7;\n uint8_t *v8;\n long long v9;\n const unsigned short **v10;\n const unsigned short *v11;\n unsigned short v12;\n uint8_t *v13;\n unsigned int v15;\n const __int32_t *v16;\n v15 = strlen(a1);\n v2 = malloc(2 * v15);\n v3 = v2;\n if (v15) {\n v4 = 0LL;\n v5 = 0;\n v16 = *__ctype_tolower_loc();\n do {\n v6 = a1[v4];\n v7 = v5 + 1;\n v8 = &v3[v5];\n v9 = v6;\n if (v4 &&\n (v10 = __ctype_b_loc(), v8 = &v3[v5], v11 = *v10, v9 = v6,\n (v11[v6] & 256) != 0) &&\n ((v12 = v11[a1[v4 - 1]], (v12 & 2560) != 0) ||\n (v12 & 256) != 0 && (v11[a1[v4 + 1]] & 512) != 0)) {\n v3[v5] = 95;\n v5 += 2;\n v3[v7] = v16[v6];\n } else {\n ++v5;\n *v8 = v16[v9];\n }\n ++v4;\n } while (v15 != v4);\n v13 = &v3[v5];\n } else {\n v13 = v2;\n }\n *v13 = 0;\n return v3;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1) {\n uint8_t *v2;\n uint8_t *v3;\n long long v4;\n int v5;\n char v6;\n int v7;\n uint8_t *v8;\n long long v9;\n const unsigned short **v10;\n const unsigned short *v11;\n unsigned short v12;\n uint8_t *v13;\n unsigned int v15;\n const __int32_t *v16;\n v15 = strlen(a1);\n v2 = malloc(2 * v15);\n v3 = v2;\n if (v15) {\n v4 = 0LL;\n v5 = 0;\n v16 = *__ctype_tolower_loc();\n do {\n v6 = a1[v4];\n v7 = v5 + 1;\n v8 = &v3[v5];\n v9 = v6;\n if (v4 &&\n (v10 = __ctype_b_loc(), v8 = &v3[v5], v11 = *v10, v9 = v6,\n (v11[v6] & 256) != 0) &&\n ((v12 = v11[a1[v4 - 1]], (v12 & 2560) != 0) ||\n (v12 & 256) != 0 && (v11[a1[v4 + 1]] & 512) != 0)) {\n v3[v5] = 95;\n v5 += 2;\n v3[v7] = v16[v6];\n } else {\n ++v5;\n *v8 = v16[v9];\n }\n ++v4;\n } while (v15 != v4);\n v13 = &v3[v5];\n } else {\n v13 = v2;\n }\n *v13 = 0;\n return v3;\n}" + }, + { + "index": 934, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n, int m) {\n if (m == 0 || n == 0) {\n return 1;\n }\n return func0(m - 1, n) + func0(m - 1, n - 1) + func0(m, n - 1);\n}", + "test": "int main() {\n\n assert(func0(3, 4) == 129);\n\n assert(func0(3, 3) == 63);\n\n assert(func0(4, 5) == 681);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x18,%rsp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\ncmpl $0x0,-0x18(%rbp)\nje 1168 \ncmpl $0x0,-0x14(%rbp)\njne 116f \nmov $0x1,%eax\njmp 11ae \nmov -0x18(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x14(%rbp),%eax\nmov %eax,%esi\nmov %edx,%edi\ncallq 1149 \nmov %eax,%ebx\nmov -0x14(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x18(%rbp),%eax\nsub $0x1,%eax\nmov %edx,%esi\nmov %eax,%edi\ncallq 1149 \nadd %eax,%ebx\nmov -0x14(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x18(%rbp),%eax\nmov %edx,%esi\nmov %eax,%edi\ncallq 1149 \nadd %ebx,%eax\nadd $0x18,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 18h\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\ncmp [rbp+var_18], 0\njz short loc_1168\ncmp [rbp+var_14], 0\njnz short loc_116F\nloc_1168:\nmov eax, 1\njmp short loc_11AE\nloc_116F:\nmov eax, [rbp+var_18]\nlea edx, [rax-1]\nmov eax, [rbp+var_14]\nmov esi, eax\nmov edi, edx\ncall func0\nmov ebx, eax\nmov eax, [rbp+var_14]\nlea edx, [rax-1]\nmov eax, [rbp+var_18]\nsub eax, 1\nmov esi, edx\nmov edi, eax\ncall func0\nadd ebx, eax\nmov eax, [rbp+var_14]\nlea edx, [rax-1]\nmov eax, [rbp+var_18]\nmov esi, edx\nmov edi, eax\ncall func0\nadd eax, ebx\nloc_11AE:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1, unsigned int a2)\n{\n int v3; // ebx\n int v4; // ebx\n\n if ( !a2 || !a1 )\n return 1LL;\n v3 = func0(a2 - 1, a1);\n v4 = func0(a2 - 1, a1 - 1) + v3;\n return v4 + (unsigned int)func0(a2, a1 - 1);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 18h\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\ncmp [rbp+var_18], 0\njz short loc_1168\ncmp [rbp+var_14], 0\njnz short loc_116F\nloc_1168:\nmov eax, 1\njmp short loc_11AE\nloc_116F:\nmov eax, [rbp+var_18]\nlea edx, [rax-1]\nmov eax, [rbp+var_14]\nmov esi, eax\nmov edi, edx\ncall sub_1149\nmov ebx, eax\nmov eax, [rbp+var_14]\nlea edx, [rax-1]\nmov eax, [rbp+var_18]\nsub eax, 1\nmov esi, edx\nmov edi, eax\ncall sub_1149\nadd ebx, eax\nmov eax, [rbp+var_14]\nlea edx, [rax-1]\nmov eax, [rbp+var_18]\nmov esi, edx\nmov edi, eax\ncall sub_1149\nadd eax, ebx\nloc_11AE:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(unsigned int a1, unsigned int a2)\n{\n int v3; // ebx\n int v4; // ebx\n\n if ( !a2 || !a1 )\n return 1LL;\n v3 = sub_1149(a2 - 1, a1);\n v4 = sub_1149(a2 - 1, a1 - 1) + v3;\n return v4 + (unsigned int)sub_1149(a2, a1 - 1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(unsigned int a1, unsigned int a2) {\n int v3;\n int v4;\n if (!a2 || !a1) return 1LL;\n v3 = sub_1149(a2 - 1, a1);\n v4 = sub_1149(a2 - 1, a1 - 1) + v3;\n return v4 + (unsigned int)sub_1149(a2, a1 - 1);\n}", + "ida_pseudo_norm": "long long func0(unsigned int a1, unsigned int a2) {\n int v3;\n int v4;\n if (!a2 || !a1) return 1LL;\n v3 = func0(a2 - 1, a1);\n v4 = func0(a2 - 1, a1 - 1) + v3;\n return v4 + (unsigned int)func0(a2, a1 - 1);\n}" + }, + { + "index": 934, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n, int m) {\n if (m == 0 || n == 0) {\n return 1;\n }\n return func0(m - 1, n) + func0(m - 1, n - 1) + func0(m, n - 1);\n}", + "test": "int main() {\n\n assert(func0(3, 4) == 129);\n\n assert(func0(3, 3) == 63);\n\n assert(func0(4, 5) == 681);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\nje 11a0 \npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %edi,%ebx\nmov %esi,%ebp\nmov $0x1,%eax\ntest %edi,%edi\nje 1195 \nlea -0x1(%rsi),%r13d\nmov %edi,%esi\nmov %r13d,%edi\ncallq 1149 \nmov %eax,%r12d\nsub $0x1,%ebx\nmov %ebx,%esi\nmov %r13d,%edi\ncallq 1149 \nadd %eax,%r12d\nmov %ebx,%esi\nmov %ebp,%edi\ncallq 1149 \nadd %r12d,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nmov $0x1,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njz short loc_11A0\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov ebx, edi\nmov ebp, esi\nmov eax, 1\ntest edi, edi\njz short loc_1195\nlea r13d, [rsi-1]\nmov esi, edi\nmov edi, r13d\ncall func0\nmov r12d, eax\nsub ebx, 1\nmov esi, ebx\nmov edi, r13d\ncall func0\nadd r12d, eax\nmov esi, ebx\nmov edi, ebp\ncall func0\nadd eax, r12d\nloc_1195:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_11A0:\nmov eax, 1\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1, unsigned int a2)\n{\n __int64 result; // rax\n int v3; // r12d\n int v4; // r12d\n\n if ( !a2 )\n return 1LL;\n result = 1LL;\n if ( a1 )\n {\n v3 = func0(a2 - 1, a1);\n v4 = func0(a2 - 1, a1 - 1) + v3;\n return v4 + (unsigned int)func0(a2, a1 - 1);\n }\n return result;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ntest esi, esi\njz short loc_11A0\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov ebx, edi\nmov ebp, esi\nmov eax, 1\ntest edi, edi\njz short loc_1195\nlea r13d, [rsi-1]\nmov esi, edi\nmov edi, r13d\ncall sub_1149\nmov r12d, eax\nsub ebx, 1\nmov esi, ebx\nmov edi, r13d\ncall sub_1149\nadd r12d, eax\nmov esi, ebx\nmov edi, ebp\ncall sub_1149\nadd eax, r12d\nloc_1195:\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_11A0:\nmov eax, 1\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(unsigned int a1, unsigned int a2)\n{\n __int64 result; // rax\n int v3; // r12d\n int v4; // r12d\n\n if ( !a2 )\n return 1LL;\n result = 1LL;\n if ( a1 )\n {\n v3 = sub_1149(a2 - 1, a1);\n v4 = sub_1149(a2 - 1, a1 - 1) + v3;\n return v4 + (unsigned int)sub_1149(a2, a1 - 1);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(unsigned int a1, unsigned int a2) {\n long long result;\n int v3;\n int v4;\n if (!a2) return 1LL;\n result = 1LL;\n if (a1) {\n v3 = sub_1149(a2 - 1, a1);\n v4 = sub_1149(a2 - 1, a1 - 1) + v3;\n return v4 + (unsigned int)sub_1149(a2, a1 - 1);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(unsigned int a1, unsigned int a2) {\n long long result;\n int v3;\n int v4;\n if (!a2) return 1LL;\n result = 1LL;\n if (a1) {\n v3 = func0(a2 - 1, a1);\n v4 = func0(a2 - 1, a1 - 1) + v3;\n return v4 + (unsigned int)func0(a2, a1 - 1);\n }\n return result;\n}" + }, + { + "index": 934, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n, int m) {\n if (m == 0 || n == 0) {\n return 1;\n }\n return func0(m - 1, n) + func0(m - 1, n - 1) + func0(m, n - 1);\n}", + "test": "int main() {\n\n assert(func0(3, 4) == 129);\n\n assert(func0(3, 3) == 63);\n\n assert(func0(4, 5) == 681);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\nje 1278 \npush %r15\nmov $0x1,%eax\npush %r14\nxor %r14d,%r14d\npush %r13\npush %r12\nmov %esi,%r12d\npush %rbp\nmov %edi,%ebp\npush %rbx\nsub $0x8,%rsp\ntest %edi,%edi\nje 1264 \nlea -0x1(%r12),%r15d\nmov %ebp,%esi\nlea -0x1(%rbp),%r13d\nmov %r12d,%ebp\nmov %r15d,%edi\ncallq 1200 \nmov %r13d,%esi\nmov %r15d,%edi\nmov %eax,%ebx\ncallq 1200 \nadd %eax,%ebx\nadd %ebx,%r14d\ntest %r13d,%r13d\nje 1260 \nmov %r13d,%r12d\njmp 1227 \nnopl 0x0(%rax)\nlea 0x1(%r14),%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax,%rax,1)\nmov $0x1,%eax\nretq\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njz loc_1D7B\npush r15\nmov ecx, edi\nmov eax, 1\npush r14\npush r13\npush r12\nxor r12d, r12d\npush rbp\npush rbx\nsub rsp, 48h\ntest edi, edi\njz loc_1D6C\nmov [rsp+78h+var_44], r12d\nmov [rsp+78h+var_48], esi\nloc_1235:\nmov r9d, [rsp+78h+var_48]\nlea eax, [rcx-1]\nmov r14d, eax\nsub r9d, 1\njz loc_1D59\nmov esi, r9d\nmov ebp, eax\nmov [rsp+78h+var_40], r9d\nxor r15d, r15d\nmov r9d, ebp\nlea r14d, [rsi-1]\nmov [rsp+78h+var_4C], r15d\nmov [rsp+78h+var_3C], eax\nmov ebp, r14d\nmov [rsp+78h+var_58], ecx\ntest r9d, r9d\njz loc_17AD\nloc_1277:\nmov r8d, r9d\nxor r13d, r13d\nmov edx, r14d\nmov [rsp+78h+var_68], esi\nlea eax, [r8-1]\nmov [rsp+78h+var_5C], r13d\nmov [rsp+78h+var_54], r9d\nmov r15d, eax\nmov [rsp+78h+var_50], r14d\ntest edx, edx\njz loc_14EA\nloc_12A2:\nxor edi, edi\nmov ebp, edx\nmov esi, eax\nmov [rsp+78h+var_60], eax\nmov [rsp+78h+var_6C], edi\nlea edi, [rbp-1]\nmov [rsp+78h+var_78], r8d\nmov eax, edi\nmov [rsp+78h+var_64], edx\ntest esi, esi\njz loc_138A\nloc_12C5:\nmov [rsp+78h+var_74], esi\nxor r12d, r12d\nmov r14d, ebp\nmov r13d, esi\nmov [rsp+78h+var_70], edi\nmov ebp, r12d\nmov r12d, edi\nloc_12DC:\nmov esi, r13d\nmov edi, r12d\nlea r15d, [r13-1]\nmov r13d, r14d\ncall func0\nmov esi, r15d\nmov edi, r12d\nmov ebx, eax\ncall func0\nadd ebx, eax\nadd ebp, ebx\ntest r15d, r15d\njz short loc_1310\nmov r14d, r15d\nlea r12d, [r15-1]\njmp short loc_12DC\nloc_1310:\nmov eax, [rsp+78h+var_70]\nmov r14d, [rsp+78h+var_74]\nlea ebx, [rbp+1]\ntest eax, eax\njz loc_1EBB\nmov [rsp+78h+var_74], ebx\nmov r13d, eax\nmov ebx, r15d\nloc_132E:\nlea r15d, [r13-1]\nmov esi, r14d\nlea r12d, [r14-1]\nmov r14d, r13d\nmov edi, r15d\ncall func0\nmov esi, r12d\nmov edi, r15d\nmov ebp, eax\ncall func0\nadd ebp, eax\nadd ebx, ebp\ntest r12d, r12d\njz short loc_1360\nmov r13d, r12d\njmp short loc_132E\nloc_1360:\nmov r15d, ebx\nmov ebx, [rsp+78h+var_74]\nmov eax, [rsp+78h+var_70]\nlea edx, [r15+rbx+1]\nadd [rsp+78h+var_6C], edx\nloc_1374:\nmov ebp, [rsp+78h+var_78]\nlea esi, [rax-1]\nmov [rsp+78h+var_78], eax\nlea edi, [rbp-1]\nmov eax, edi\ntest esi, esi\njnz loc_12C5\nloc_138A:\nadd [rsp+78h+var_6C], 2\ntest edi, edi\njnz short loc_1374\nmov edi, [rsp+78h+var_6C]\nmov r9d, [rsp+78h+var_64]\nmov r15d, [rsp+78h+var_60]\nloc_13A1:\nlea r14d, [rdi+1]\ntest r15d, r15d\njz loc_1EA3\nmov [rsp+78h+var_78], r15d\nmov ebp, r9d\nmov r13d, [rsp+78h+var_78]\nxor esi, esi\nlea edi, [rbp-1]\nmov [rsp+78h+var_64], r14d\nmov [rsp+78h+var_6C], esi\nmov eax, edi\nmov [rsp+78h+var_60], r15d\nsub r13d, 1\njz loc_14AD\nloc_13D8:\nmov [rsp+78h+var_70], edi\nxor r12d, r12d\nmov r14d, r13d\nmov [rsp+78h+var_74], r13d\nmov r13d, ebp\nmov ebp, r12d\nmov r12d, edi\nloc_13F0:\nmov esi, r14d\nmov edi, r12d\nlea r15d, [r14-1]\nmov r14d, r13d\ncall func0\nmov esi, r15d\nmov edi, r12d\nmov ebx, eax\ncall func0\nadd ebx, eax\nadd ebp, ebx\ntest r15d, r15d\njz short loc_1428\nmov r13d, r15d\nlea r12d, [r15-1]\njmp short loc_13F0\nloc_1428:\nmov eax, [rsp+78h+var_70]\nmov r13d, [rsp+78h+var_74]\nlea ebx, [rbp+1]\ntest eax, eax\njz loc_1E8C\nmov [rsp+78h+var_74], ebx\nmov r14d, eax\nmov ebx, r15d\nloc_1446:\nlea r15d, [r14-1]\nmov esi, r13d\nlea r12d, [r13-1]\nmov r13d, r14d\nmov edi, r15d\ncall func0\nmov esi, r12d\nmov edi, r15d\nmov ebp, eax\ncall func0\nadd ebp, eax\nadd ebx, ebp\ntest r12d, r12d\njz short loc_1480\nmov r14d, r12d\njmp short loc_1446\nloc_1480:\nmov r15d, ebx\nmov ebx, [rsp+78h+var_74]\nmov eax, [rsp+78h+var_70]\nlea edx, [r15+rbx+1]\nadd [rsp+78h+var_6C], edx\nloc_1494:\nmov ebp, [rsp+78h+var_78]\nmov [rsp+78h+var_78], eax\nmov r13d, [rsp+78h+var_78]\nlea edi, [rbp-1]\nmov eax, edi\nsub r13d, 1\njnz loc_13D8\nloc_14AD:\nadd [rsp+78h+var_6C], 2\ntest edi, edi\njnz short loc_1494\nmov r14d, [rsp+78h+var_64]\nmov esi, [rsp+78h+var_6C]\nmov r15d, [rsp+78h+var_60]\nloc_14C4:\nlea eax, [r14+rsi+1]\nadd [rsp+78h+var_5C], eax\nloc_14CD:\nmov r8d, [rsp+78h+var_68]\nlea edx, [r15-1]\nmov [rsp+78h+var_68], r15d\nlea eax, [r8-1]\nmov r15d, eax\ntest edx, edx\njnz loc_12A2\nloc_14EA:\nadd [rsp+78h+var_5C], 2\ntest eax, eax\njnz short loc_14CD\nmov r13d, [rsp+78h+var_5C]\nmov r9d, [rsp+78h+var_54]\nmov ebp, [rsp+78h+var_50]\nloc_1501:\nlea ebx, [r13+1]\ntest ebp, ebp\njz loc_1E73\nxor r13d, r13d\nmov [rsp+78h+var_54], ebx\nmov [rsp+78h+var_5C], r13d\nmov [rsp+78h+var_68], ebp\nmov [rsp+78h+var_50], ebp\nloc_1521:\nmov r10d, [rsp+78h+var_68]\nlea eax, [r9-1]\nmov ecx, eax\nsub r10d, 1\njz loc_1770\nmov ebp, r10d\nxor edx, edx\nmov [rsp+78h+var_60], eax\nlea edi, [rbp-1]\nmov [rsp+78h+var_6C], edx\nmov [rsp+78h+var_78], r9d\nmov eax, edi\nmov [rsp+78h+var_64], r10d\ntest ecx, ecx\njz loc_162A\nloc_1559:\nmov [rsp+78h+var_74], ecx\nxor r12d, r12d\nmov r15d, ebp\nmov r14d, ecx\nmov [rsp+78h+var_70], edi\nmov ebp, r12d\nmov r12d, edi\nloc_1570:\nmov esi, r14d\nmov edi, r12d\nlea r13d, [r14-1]\nmov r14d, r15d\ncall func0\nmov esi, r13d\nmov edi, r12d\nmov ebx, eax\ncall func0\nadd ebx, eax\nadd ebp, ebx\ntest r13d, r13d\njz short loc_15A8\nmov r15d, r13d\nlea r12d, [r13-1]\njmp short loc_1570\nloc_15A8:\nmov eax, [rsp+78h+var_70]\nmov r15d, [rsp+78h+var_74]\nlea ebx, [rbp+1]\ntest eax, eax\njz loc_1E5D\nmov [rsp+78h+var_74], ebx\nmov r14d, eax\nmov ebx, r13d\nloc_15C6:\nlea r13d, [r14-1]\nmov esi, r15d\nlea r12d, [r15-1]\nmov r15d, r14d\nmov edi, r13d\ncall func0\nmov esi, r12d\nmov edi, r13d\nmov ebp, eax\ncall func0\nadd ebp, eax\nadd ebx, ebp\ntest r12d, r12d\njz short loc_1600\nmov r14d, r12d\njmp short loc_15C6\nloc_1600:\nmov r13d, ebx\nmov ebx, [rsp+78h+var_74]\nmov eax, [rsp+78h+var_70]\nlea edx, [r13+rbx+1]\nadd [rsp+78h+var_6C], edx\nloc_1614:\nmov ebp, [rsp+78h+var_78]\nlea ecx, [rax-1]\nmov [rsp+78h+var_78], eax\nlea edi, [rbp-1]\nmov eax, edi\ntest ecx, ecx\njnz loc_1559\nloc_162A:\nadd [rsp+78h+var_6C], 2\ntest edi, edi\njnz short loc_1614\nmov edx, [rsp+78h+var_6C]\nmov r10d, [rsp+78h+var_64]\nmov ecx, [rsp+78h+var_60]\nloc_1640:\nlea r14d, [rdx+1]\ntest ecx, ecx\njz loc_1E46\nmov [rsp+78h+var_78], ecx\nmov ebp, r10d\nxor esi, esi\nmov [rsp+78h+var_64], r14d\nmov r14d, [rsp+78h+var_78]\nlea edi, [rbp-1]\nmov [rsp+78h+var_6C], esi\nmov eax, edi\nmov [rsp+78h+var_60], ecx\nsub r14d, 1\njz loc_173D\nloc_1674:\nmov [rsp+78h+var_70], edi\nxor r12d, r12d\nmov r15d, r14d\nmov [rsp+78h+var_74], r14d\nmov r14d, ebp\nmov ebp, r12d\nmov r12d, edi\nloc_168C:\nmov esi, r15d\nmov edi, r12d\nlea r13d, [r15-1]\nmov r15d, r14d\ncall func0\nmov esi, r13d\nmov edi, r12d\nmov ebx, eax\ncall func0\nadd ebx, eax\nadd ebp, ebx\ntest r13d, r13d\njz short loc_16C0\nmov r14d, r13d\nlea r12d, [r13-1]\njmp short loc_168C\nloc_16C0:\nmov eax, [rsp+78h+var_70]\nmov r14d, [rsp+78h+var_74]\nlea ebx, [rbp+1]\ntest eax, eax\njz loc_1E30\nmov [rsp+78h+var_74], ebx\nmov r15d, eax\nmov ebx, r13d\nloc_16DE:\nlea r13d, [r15-1]\nmov esi, r14d\nlea r12d, [r14-1]\nmov r14d, r15d\nmov edi, r13d\ncall func0\nmov esi, r12d\nmov edi, r13d\nmov ebp, eax\ncall func0\nadd ebp, eax\nadd ebx, ebp\ntest r12d, r12d\njz short loc_1710\nmov r15d, r12d\njmp short loc_16DE\nloc_1710:\nmov r13d, ebx\nmov ebx, [rsp+78h+var_74]\nmov eax, [rsp+78h+var_70]\nlea edx, [r13+rbx+1]\nadd [rsp+78h+var_6C], edx\nloc_1724:\nmov ebp, [rsp+78h+var_78]\nmov [rsp+78h+var_78], eax\nmov r14d, [rsp+78h+var_78]\nlea edi, [rbp-1]\nmov eax, edi\nsub r14d, 1\njnz loc_1674\nloc_173D:\nadd [rsp+78h+var_6C], 2\ntest edi, edi\njnz short loc_1724\nmov r14d, [rsp+78h+var_64]\nmov esi, [rsp+78h+var_6C]\nmov ecx, [rsp+78h+var_60]\nloc_1753:\nlea eax, [r14+rsi+1]\nadd [rsp+78h+var_5C], eax\nloc_175C:\nmov r9d, [rsp+78h+var_68]\nmov [rsp+78h+var_68], ecx\njmp loc_1521\nloc_1770:\nadd [rsp+78h+var_5C], 2\ntest eax, eax\njnz short loc_175C\nmov ebx, [rsp+78h+var_54]\nmov r13d, [rsp+78h+var_5C]\nmov ebp, [rsp+78h+var_50]\nloc_1786:\nlea eax, [rbx+r13+1]\nadd [rsp+78h+var_4C], eax\nloc_178F:\nmov esi, [rsp+78h+var_58]\nmov [rsp+78h+var_58], ebp\nlea ebp, [rbp-1]\nmov r9d, ebp\nlea r14d, [rsi-1]\nmov ebp, r14d\ntest r9d, r9d\njnz loc_1277\nloc_17AD:\nadd [rsp+78h+var_4C], 2\ntest r14d, r14d\njnz short loc_178F\nmov r15d, [rsp+78h+var_4C]\nmov r9d, [rsp+78h+var_40]\nmov r14d, [rsp+78h+var_3C]\nloc_17C6:\nlea ebx, [r15+1]\ntest r14d, r14d\njz loc_1E21\nxor ecx, ecx\nmov [rsp+78h+var_58], r14d\nmov esi, r9d\nmov [rsp+78h+var_40], ebx\nmov [rsp+78h+var_4C], ecx\nmov [rsp+78h+var_3C], r14d\nloc_17EA:\nmov r9d, [rsp+78h+var_58]\nlea r13d, [rsi-1]\nmov edx, r13d\nsub r9d, 1\njz loc_1D2C\nmov r8d, r9d\nxor r12d, r12d\nmov [rsp+78h+var_68], esi\nlea eax, [r8-1]\nmov [rsp+78h+var_5C], r12d\nmov [rsp+78h+var_54], r9d\nmov r15d, eax\nmov [rsp+78h+var_50], r13d\ntest edx, edx\njz loc_1A7A\nloc_1828:\nxor edi, edi\nmov ebp, edx\nmov esi, eax\nmov [rsp+78h+var_60], eax\nmov [rsp+78h+var_6C], edi\nlea edi, [rbp-1]\nmov [rsp+78h+var_78], r8d\nmov eax, edi\nmov [rsp+78h+var_64], edx\ntest esi, esi\njz loc_191A\nloc_184B:\nmov [rsp+78h+var_74], esi\nxor r14d, r14d\nmov r13d, ebp\nmov r12d, esi\nmov [rsp+78h+var_70], edi\nmov ebp, r14d\nmov r14d, edi\nloc_1862:\nmov esi, r12d\nmov edi, r14d\nlea r15d, [r12-1]\nmov r12d, r13d\ncall func0\nmov esi, r15d\nmov edi, r14d\nmov ebx, eax\ncall func0\nadd ebx, eax\nadd ebp, ebx\ntest r15d, r15d\njz short loc_1898\nmov r13d, r15d\nlea r14d, [r15-1]\njmp short loc_1862\nloc_1898:\nmov eax, [rsp+78h+var_70]\nmov r13d, [rsp+78h+var_74]\nlea ebx, [rbp+1]\ntest eax, eax\njz loc_1E0A\nmov [rsp+78h+var_74], ebx\nmov r14d, eax\nmov ebx, r15d\nloc_18B6:\nlea r15d, [r14-1]\nmov esi, r13d\nlea r12d, [r13-1]\nmov r13d, r14d\nmov edi, r15d\ncall func0\nmov esi, r12d\nmov edi, r15d\nmov ebp, eax\ncall func0\nadd ebp, eax\nadd ebx, ebp\ntest r12d, r12d\njz short loc_18F0\nmov r14d, r12d\njmp short loc_18B6\nloc_18F0:\nmov r15d, ebx\nmov ebx, [rsp+78h+var_74]\nmov eax, [rsp+78h+var_70]\nlea edx, [r15+rbx+1]\nadd [rsp+78h+var_6C], edx\nloc_1904:\nmov ebp, [rsp+78h+var_78]\nlea esi, [rax-1]\nmov [rsp+78h+var_78], eax\nlea edi, [rbp-1]\nmov eax, edi\ntest esi, esi\njnz loc_184B\nloc_191A:\nadd [rsp+78h+var_6C], 2\ntest edi, edi\njnz short loc_1904\nmov edi, [rsp+78h+var_6C]\nmov r9d, [rsp+78h+var_64]\nmov r15d, [rsp+78h+var_60]\nloc_1931:\nlea r13d, [rdi+1]\ntest r15d, r15d\njz loc_1DF2\nmov [rsp+78h+var_78], r15d\nmov ebp, r9d\nxor esi, esi\nmov [rsp+78h+var_64], r13d\nmov r13d, [rsp+78h+var_78]\nlea edi, [rbp-1]\nmov [rsp+78h+var_6C], esi\nmov eax, edi\nmov [rsp+78h+var_60], r15d\nsub r13d, 1\njz loc_1A3D\nloc_1968:\nmov [rsp+78h+var_70], edi\nxor r14d, r14d\nmov r12d, r13d\nmov [rsp+78h+var_74], r13d\nmov r13d, ebp\nmov ebp, r14d\nmov r14d, edi\nloc_1980:\nmov esi, r12d\nmov edi, r14d\nlea r15d, [r12-1]\nmov r12d, r13d\ncall func0\nmov esi, r15d\nmov edi, r14d\nmov ebx, eax\ncall func0\nadd ebx, eax\nadd ebp, ebx\ntest r15d, r15d\njz short loc_19B8\nmov r13d, r15d\nlea r14d, [r15-1]\njmp short loc_1980\nloc_19B8:\nmov eax, [rsp+78h+var_70]\nmov r13d, [rsp+78h+var_74]\nlea ebx, [rbp+1]\ntest eax, eax\njz loc_1DDB\nmov [rsp+78h+var_74], ebx\nmov r14d, eax\nmov ebx, r15d\nloc_19D6:\nlea r15d, [r14-1]\nmov esi, r13d\nlea r12d, [r13-1]\nmov r13d, r14d\nmov edi, r15d\ncall func0\nmov esi, r12d\nmov edi, r15d\nmov ebp, eax\ncall func0\nadd ebp, eax\nadd ebx, ebp\ntest r12d, r12d\njz short loc_1A10\nmov r14d, r12d\njmp short loc_19D6\nloc_1A10:\nmov r15d, ebx\nmov ebx, [rsp+78h+var_74]\nmov eax, [rsp+78h+var_70]\nlea edx, [r15+rbx+1]\nadd [rsp+78h+var_6C], edx\nloc_1A24:\nmov ebp, [rsp+78h+var_78]\nmov [rsp+78h+var_78], eax\nmov r13d, [rsp+78h+var_78]\nlea edi, [rbp-1]\nmov eax, edi\nsub r13d, 1\njnz loc_1968\nloc_1A3D:\nadd [rsp+78h+var_6C], 2\ntest edi, edi\njnz short loc_1A24\nmov r13d, [rsp+78h+var_64]\nmov esi, [rsp+78h+var_6C]\nmov r15d, [rsp+78h+var_60]\nloc_1A54:\nlea eax, [r13+rsi+1]\nadd [rsp+78h+var_5C], eax\nloc_1A5D:\nmov r8d, [rsp+78h+var_68]\nlea edx, [r15-1]\nmov [rsp+78h+var_68], r15d\nlea eax, [r8-1]\nmov r15d, eax\ntest edx, edx\njnz loc_1828\nloc_1A7A:\nadd [rsp+78h+var_5C], 2\ntest eax, eax\njnz short loc_1A5D\nmov r12d, [rsp+78h+var_5C]\nmov r9d, [rsp+78h+var_54]\nmov edx, [rsp+78h+var_50]\nloc_1A91:\nlea ebp, [r12+1]\ntest edx, edx\njz loc_1DC4\nxor r13d, r13d\nmov [rsp+78h+var_54], ebp\nmov [rsp+78h+var_5C], r13d\nmov [rsp+78h+var_68], edx\nmov [rsp+78h+var_50], edx\nloc_1AB2:\nmov r8d, [rsp+78h+var_68]\nlea eax, [r9-1]\nmov edx, eax\nsub r8d, 1\njz loc_1D00\nxor esi, esi\nmov ebp, r8d\nmov [rsp+78h+var_60], eax\nmov [rsp+78h+var_6C], esi\nlea edi, [rbp-1]\nmov esi, eax\nmov [rsp+78h+var_78], r9d\nmov eax, edi\nmov [rsp+78h+var_64], r8d\ntest esi, esi\njz loc_1BBA\nloc_1AEC:\nmov [rsp+78h+var_74], esi\nxor r12d, r12d\nmov r15d, ebp\nmov r14d, esi\nmov [rsp+78h+var_70], edi\nmov ebp, r12d\nmov r12d, edi\nloc_1B03:\nmov esi, r14d\nmov edi, r12d\nlea r13d, [r14-1]\nmov r14d, r15d\ncall func0\nmov esi, r13d\nmov edi, r12d\nmov ebx, eax\ncall func0\nadd ebx, eax\nadd ebp, ebx\ntest r13d, r13d\njz short loc_1B38\nmov r15d, r13d\nlea r12d, [r13-1]\njmp short loc_1B03\nloc_1B38:\nmov eax, [rsp+78h+var_70]\nmov r15d, [rsp+78h+var_74]\nlea ebx, [rbp+1]\ntest eax, eax\njz loc_1DAE\nmov [rsp+78h+var_74], ebx\nmov r14d, eax\nmov ebx, r13d\nloc_1B56:\nlea r13d, [r14-1]\nmov esi, r15d\nlea r12d, [r15-1]\nmov r15d, r14d\nmov edi, r13d\ncall func0\nmov esi, r12d\nmov edi, r13d\nmov ebp, eax\ncall func0\nadd ebp, eax\nadd ebx, ebp\ntest r12d, r12d\njz short loc_1B90\nmov r14d, r12d\njmp short loc_1B56\nloc_1B90:\nmov r13d, ebx\nmov ebx, [rsp+78h+var_74]\nmov eax, [rsp+78h+var_70]\nlea edx, [r13+rbx+1]\nadd [rsp+78h+var_6C], edx\nloc_1BA4:\nmov ebp, [rsp+78h+var_78]\nlea esi, [rax-1]\nmov [rsp+78h+var_78], eax\nlea edi, [rbp-1]\nmov eax, edi\ntest esi, esi\njnz loc_1AEC\nloc_1BBA:\nadd [rsp+78h+var_6C], 2\ntest edi, edi\njnz short loc_1BA4\nmov esi, [rsp+78h+var_6C]\nmov r8d, [rsp+78h+var_64]\nmov edx, [rsp+78h+var_60]\nloc_1BD0:\nlea r14d, [rsi+1]\ntest edx, edx\njz loc_1D97\nmov [rsp+78h+var_78], edx\nmov ebp, r8d\nxor esi, esi\nmov [rsp+78h+var_64], r14d\nmov r14d, [rsp+78h+var_78]\nlea edi, [rbp-1]\nmov [rsp+78h+var_6C], esi\nmov eax, edi\nmov [rsp+78h+var_60], edx\nsub r14d, 1\njz loc_1CCD\nloc_1C04:\nmov [rsp+78h+var_70], edi\nxor r12d, r12d\nmov r15d, r14d\nmov [rsp+78h+var_74], r14d\nmov r14d, ebp\nmov ebp, r12d\nmov r12d, edi\nloc_1C1C:\nmov esi, r15d\nmov edi, r12d\nlea r13d, [r15-1]\nmov r15d, r14d\ncall func0\nmov esi, r13d\nmov edi, r12d\nmov ebx, eax\ncall func0\nadd ebx, eax\nadd ebp, ebx\ntest r13d, r13d\njz short loc_1C50\nmov r14d, r13d\nlea r12d, [r13-1]\njmp short loc_1C1C\nloc_1C50:\nmov eax, [rsp+78h+var_70]\nmov r14d, [rsp+78h+var_74]\nlea ebx, [rbp+1]\ntest eax, eax\njz loc_1D81\nmov [rsp+78h+var_74], ebx\nmov r15d, eax\nmov ebx, r13d\nloc_1C6E:\nlea r13d, [r15-1]\nmov esi, r14d\nlea r12d, [r14-1]\nmov r14d, r15d\nmov edi, r13d\ncall func0\nmov esi, r12d\nmov edi, r13d\nmov ebp, eax\ncall func0\nadd ebp, eax\nadd ebx, ebp\ntest r12d, r12d\njz short loc_1CA0\nmov r15d, r12d\njmp short loc_1C6E\nloc_1CA0:\nmov r13d, ebx\nmov ebx, [rsp+78h+var_74]\nmov eax, [rsp+78h+var_70]\nlea edx, [r13+rbx+1]\nadd [rsp+78h+var_6C], edx\nloc_1CB4:\nmov ebp, [rsp+78h+var_78]\nmov [rsp+78h+var_78], eax\nmov r14d, [rsp+78h+var_78]\nlea edi, [rbp-1]\nmov eax, edi\nsub r14d, 1\njnz loc_1C04\nloc_1CCD:\nadd [rsp+78h+var_6C], 2\ntest edi, edi\njnz short loc_1CB4\nmov r14d, [rsp+78h+var_64]\nmov esi, [rsp+78h+var_6C]\nmov edx, [rsp+78h+var_60]\nloc_1CE3:\nlea eax, [r14+rsi+1]\nadd [rsp+78h+var_5C], eax\nloc_1CEC:\nmov r9d, [rsp+78h+var_68]\nmov [rsp+78h+var_68], edx\njmp loc_1AB2\nloc_1D00:\nadd [rsp+78h+var_5C], 2\ntest eax, eax\njnz short loc_1CEC\nmov ebp, [rsp+78h+var_54]\nmov r13d, [rsp+78h+var_5C]\nmov edx, [rsp+78h+var_50]\nloc_1D16:\nlea eax, [rbp+r13+1]\nadd [rsp+78h+var_4C], eax\nloc_1D1F:\nmov esi, [rsp+78h+var_58]\nmov [rsp+78h+var_58], edx\njmp loc_17EA\nloc_1D2C:\nadd [rsp+78h+var_4C], 2\ntest r13d, r13d\njnz short loc_1D1F\nmov ebx, [rsp+78h+var_40]\nmov ecx, [rsp+78h+var_4C]\nmov r14d, [rsp+78h+var_3C]\nloc_1D43:\nlea eax, [rbx+rcx+1]\nadd [rsp+78h+var_44], eax\nloc_1D4B:\nmov ecx, [rsp+78h+var_48]\nmov [rsp+78h+var_48], r14d\njmp loc_1235\nloc_1D59:\nadd [rsp+78h+var_44], 2\ntest eax, eax\njnz short loc_1D4B\nmov r12d, [rsp+78h+var_44]\nloc_1D67:\nlea eax, [r12+1]\nloc_1D6C:\nadd rsp, 48h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1D7B:\nmov eax, 1\nretn\nloc_1D81:\nmov esi, [rsp+78h+var_6C]\nmov r14d, [rsp+78h+var_64]\nmov edx, [rsp+78h+var_60]\nlea esi, [rbp+rsi+2]\njmp loc_1CE3\nloc_1D97:\nmov r13d, [rsp+78h+var_5C]\nmov ebp, [rsp+78h+var_54]\nmov edx, [rsp+78h+var_50]\nlea r13d, [rsi+r13+2]\njmp loc_1D16\nloc_1DAE:\nmov esi, [rsp+78h+var_6C]\nmov r8d, [rsp+78h+var_64]\nmov edx, [rsp+78h+var_60]\nlea esi, [rbp+rsi+2]\njmp loc_1BD0\nloc_1DC4:\nmov ecx, [rsp+78h+var_4C]\nmov ebx, [rsp+78h+var_40]\nmov r14d, [rsp+78h+var_3C]\nlea ecx, [r12+rcx+2]\njmp loc_1D43\nloc_1DDB:\nmov esi, [rsp+78h+var_6C]\nmov r13d, [rsp+78h+var_64]\nmov r15d, [rsp+78h+var_60]\nlea esi, [rbp+rsi+2]\njmp loc_1A54\nloc_1DF2:\nmov r12d, [rsp+78h+var_5C]\nmov r9d, [rsp+78h+var_54]\nmov edx, [rsp+78h+var_50]\nlea r12d, [rdi+r12+2]\njmp loc_1A91\nloc_1E0A:\nmov edi, [rsp+78h+var_6C]\nmov r9d, [rsp+78h+var_64]\nmov r15d, [rsp+78h+var_60]\nlea edi, [rbp+rdi+2]\njmp loc_1931\nloc_1E21:\nmov r12d, [rsp+78h+var_44]\nlea r12d, [r15+r12+2]\njmp loc_1D67\nloc_1E30:\nmov esi, [rsp+78h+var_6C]\nmov r14d, [rsp+78h+var_64]\nmov ecx, [rsp+78h+var_60]\nlea esi, [rbp+rsi+2]\njmp loc_1753\nloc_1E46:\nmov r13d, [rsp+78h+var_5C]\nmov ebx, [rsp+78h+var_54]\nmov ebp, [rsp+78h+var_50]\nlea r13d, [rdx+r13+2]\njmp loc_1786\nloc_1E5D:\nmov edx, [rsp+78h+var_6C]\nmov r10d, [rsp+78h+var_64]\nmov ecx, [rsp+78h+var_60]\nlea edx, [rbp+rdx+2]\njmp loc_1640\nloc_1E73:\nmov r15d, [rsp+78h+var_4C]\nmov r9d, [rsp+78h+var_40]\nmov r14d, [rsp+78h+var_3C]\nlea r15d, [r13+r15+2]\njmp loc_17C6\nloc_1E8C:\nmov esi, [rsp+78h+var_6C]\nmov r14d, [rsp+78h+var_64]\nmov r15d, [rsp+78h+var_60]\nlea esi, [rbp+rsi+2]\njmp loc_14C4\nloc_1EA3:\nmov r13d, [rsp+78h+var_5C]\nmov r9d, [rsp+78h+var_54]\nmov ebp, [rsp+78h+var_50]\nlea r13d, [rdi+r13+2]\njmp loc_1501\nloc_1EBB:\nmov edi, [rsp+78h+var_6C]\nmov r9d, [rsp+78h+var_64]\nmov r15d, [rsp+78h+var_60]\nlea edi, [rbp+rdi+2]\njmp loc_13A1", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1, unsigned int a2)\n{\n unsigned int v2; // ecx\n __int64 result; // rax\n unsigned int v4; // r14d\n unsigned int v5; // esi\n unsigned int v6; // r9d\n unsigned int v7; // r14d\n unsigned int v8; // ebp\n unsigned int v9; // r8d\n unsigned int v10; // edx\n unsigned int v11; // eax\n unsigned int v12; // r15d\n unsigned int v13; // ebp\n unsigned int v14; // esi\n unsigned int v15; // edi\n unsigned int v16; // eax\n unsigned int v17; // r14d\n unsigned int v18; // r13d\n int v19; // ebp\n unsigned int j; // r12d\n __int64 v21; // rsi\n unsigned int v22; // r15d\n int v23; // ebx\n unsigned int v24; // r14d\n unsigned int v25; // r13d\n int v26; // ebx\n __int64 v27; // rsi\n unsigned int v28; // r12d\n int v29; // ebp\n int v30; // edi\n unsigned int v31; // r9d\n unsigned int v32; // r15d\n int v33; // r14d\n unsigned int v34; // ebp\n unsigned int v35; // edi\n unsigned int v36; // eax\n unsigned int v37; // r13d\n unsigned int v38; // r14d\n unsigned int v39; // r13d\n int v40; // ebp\n unsigned int k; // r12d\n __int64 v42; // rsi\n unsigned int v43; // r15d\n int v44; // ebx\n unsigned int v45; // r13d\n unsigned int v46; // r14d\n int v47; // ebx\n __int64 v48; // rsi\n unsigned int v49; // r12d\n int v50; // ebp\n unsigned int v51; // r13d\n int v52; // r14d\n int v53; // esi\n int v54; // r13d\n unsigned int v55; // r9d\n unsigned int v56; // ebp\n unsigned int v57; // ecx\n unsigned int v58; // ebp\n unsigned int v59; // edi\n unsigned int v60; // eax\n unsigned int v61; // r15d\n unsigned int v62; // r14d\n int v63; // ebp\n unsigned int m; // r12d\n __int64 v65; // rsi\n unsigned int v66; // r13d\n int v67; // ebx\n unsigned int v68; // r15d\n unsigned int v69; // r14d\n int v70; // ebx\n __int64 v71; // rsi\n unsigned int v72; // r12d\n int v73; // ebp\n int v74; // edx\n unsigned int v75; // r10d\n unsigned int v76; // ecx\n unsigned int v77; // ebp\n unsigned int v78; // edi\n unsigned int v79; // eax\n unsigned int v80; // r14d\n unsigned int v81; // r15d\n unsigned int v82; // r14d\n int v83; // ebp\n unsigned int n; // r12d\n __int64 v85; // rsi\n unsigned int v86; // r13d\n int v87; // ebx\n unsigned int v88; // r14d\n unsigned int v89; // r15d\n int v90; // ebx\n __int64 v91; // rsi\n unsigned int v92; // r12d\n int v93; // ebp\n unsigned int v94; // r14d\n int v95; // r14d\n int v96; // esi\n int v97; // ebx\n int v98; // r13d\n int v99; // r15d\n unsigned int v100; // r9d\n unsigned int v101; // r14d\n unsigned int v102; // esi\n unsigned int v103; // edx\n unsigned int v104; // r8d\n unsigned int v105; // eax\n unsigned int v106; // r15d\n unsigned int v107; // ebp\n unsigned int v108; // esi\n unsigned int v109; // edi\n unsigned int v110; // eax\n unsigned int v111; // r13d\n unsigned int v112; // r12d\n int v113; // ebp\n unsigned int ii; // r14d\n __int64 v115; // rsi\n unsigned int v116; // r15d\n int v117; // ebx\n unsigned int v118; // r13d\n unsigned int v119; // r14d\n int v120; // ebx\n __int64 v121; // rsi\n unsigned int v122; // r12d\n int v123; // ebp\n int v124; // edi\n unsigned int v125; // r9d\n unsigned int v126; // r15d\n unsigned int v127; // ebp\n unsigned int v128; // edi\n unsigned int v129; // eax\n unsigned int v130; // r13d\n unsigned int v131; // r12d\n unsigned int v132; // r13d\n int v133; // ebp\n unsigned int jj; // r14d\n __int64 v135; // rsi\n unsigned int v136; // r15d\n int v137; // ebx\n unsigned int v138; // r13d\n unsigned int v139; // r14d\n int v140; // ebx\n __int64 v141; // rsi\n unsigned int v142; // r12d\n int v143; // ebp\n unsigned int v144; // r13d\n int v145; // r13d\n int v146; // esi\n int v147; // r12d\n unsigned int v148; // r9d\n unsigned int v149; // edx\n unsigned int v150; // edx\n unsigned int v151; // ebp\n unsigned int v152; // edi\n unsigned int v153; // esi\n unsigned int v154; // eax\n unsigned int v155; // r15d\n unsigned int v156; // r14d\n int v157; // ebp\n unsigned int kk; // r12d\n __int64 v159; // rsi\n unsigned int v160; // r13d\n int v161; // ebx\n unsigned int v162; // r15d\n unsigned int v163; // r14d\n int v164; // ebx\n __int64 v165; // rsi\n unsigned int v166; // r12d\n int v167; // ebp\n int v168; // esi\n unsigned int v169; // r8d\n unsigned int v170; // edx\n unsigned int v171; // ebp\n unsigned int v172; // edi\n unsigned int v173; // eax\n unsigned int v174; // r14d\n unsigned int v175; // r15d\n unsigned int v176; // r14d\n int v177; // ebp\n unsigned int mm; // r12d\n __int64 v179; // rsi\n unsigned int v180; // r13d\n int v181; // ebx\n unsigned int v182; // r14d\n unsigned int v183; // r15d\n int v184; // ebx\n __int64 v185; // rsi\n unsigned int v186; // r12d\n int v187; // ebp\n unsigned int v188; // r14d\n int v189; // r14d\n int v190; // esi\n int v191; // ebp\n int v192; // r13d\n int v193; // ebx\n int v194; // ecx\n int v195; // r12d\n unsigned int v196; // [rsp+0h] [rbp-78h]\n unsigned int v197; // [rsp+0h] [rbp-78h]\n unsigned int v198; // [rsp+0h] [rbp-78h]\n unsigned int v199; // [rsp+0h] [rbp-78h]\n unsigned int v200; // [rsp+0h] [rbp-78h]\n unsigned int v201; // [rsp+0h] [rbp-78h]\n unsigned int v202; // [rsp+0h] [rbp-78h]\n unsigned int v203; // [rsp+0h] [rbp-78h]\n unsigned int v204; // [rsp+4h] [rbp-74h]\n int v205; // [rsp+4h] [rbp-74h]\n unsigned int v206; // [rsp+4h] [rbp-74h]\n int v207; // [rsp+4h] [rbp-74h]\n unsigned int v208; // [rsp+4h] [rbp-74h]\n int v209; // [rsp+4h] [rbp-74h]\n unsigned int v210; // [rsp+4h] [rbp-74h]\n int v211; // [rsp+4h] [rbp-74h]\n unsigned int v212; // [rsp+4h] [rbp-74h]\n int v213; // [rsp+4h] [rbp-74h]\n unsigned int v214; // [rsp+4h] [rbp-74h]\n int v215; // [rsp+4h] [rbp-74h]\n unsigned int v216; // [rsp+4h] [rbp-74h]\n int v217; // [rsp+4h] [rbp-74h]\n unsigned int v218; // [rsp+4h] [rbp-74h]\n int v219; // [rsp+4h] [rbp-74h]\n int v220; // [rsp+Ch] [rbp-6Ch]\n int v221; // [rsp+Ch] [rbp-6Ch]\n int v222; // [rsp+Ch] [rbp-6Ch]\n int v223; // [rsp+Ch] [rbp-6Ch]\n int v224; // [rsp+Ch] [rbp-6Ch]\n int v225; // [rsp+Ch] [rbp-6Ch]\n int v226; // [rsp+Ch] [rbp-6Ch]\n int v227; // [rsp+Ch] [rbp-6Ch]\n unsigned int v228; // [rsp+10h] [rbp-68h]\n unsigned int v229; // [rsp+10h] [rbp-68h]\n unsigned int v230; // [rsp+10h] [rbp-68h]\n unsigned int v231; // [rsp+10h] [rbp-68h]\n unsigned int v232; // [rsp+14h] [rbp-64h]\n int v233; // [rsp+14h] [rbp-64h]\n int v234; // [rsp+14h] [rbp-64h]\n unsigned int v235; // [rsp+14h] [rbp-64h]\n int v236; // [rsp+14h] [rbp-64h]\n int v237; // [rsp+14h] [rbp-64h]\n unsigned int v238; // [rsp+18h] [rbp-60h]\n unsigned int v239; // [rsp+18h] [rbp-60h]\n unsigned int v240; // [rsp+18h] [rbp-60h]\n unsigned int v241; // [rsp+18h] [rbp-60h]\n unsigned int v242; // [rsp+18h] [rbp-60h]\n unsigned int v243; // [rsp+18h] [rbp-60h]\n unsigned int v244; // [rsp+18h] [rbp-60h]\n unsigned int v245; // [rsp+18h] [rbp-60h]\n int v246; // [rsp+1Ch] [rbp-5Ch]\n int v247; // [rsp+1Ch] [rbp-5Ch]\n int v248; // [rsp+1Ch] [rbp-5Ch]\n int v249; // [rsp+1Ch] [rbp-5Ch]\n unsigned int v250; // [rsp+20h] [rbp-58h]\n unsigned int v251; // [rsp+20h] [rbp-58h]\n unsigned int v252; // [rsp+24h] [rbp-54h]\n int v253; // [rsp+24h] [rbp-54h]\n int v254; // [rsp+24h] [rbp-54h]\n unsigned int v255; // [rsp+28h] [rbp-50h]\n unsigned int v256; // [rsp+28h] [rbp-50h]\n unsigned int v257; // [rsp+28h] [rbp-50h]\n unsigned int v258; // [rsp+28h] [rbp-50h]\n int v259; // [rsp+2Ch] [rbp-4Ch]\n int v260; // [rsp+2Ch] [rbp-4Ch]\n unsigned int i; // [rsp+30h] [rbp-48h]\n int v262; // [rsp+34h] [rbp-44h]\n int v263; // [rsp+38h] [rbp-40h]\n unsigned int v264; // [rsp+3Ch] [rbp-3Ch]\n unsigned int v265; // [rsp+3Ch] [rbp-3Ch]\n\n if ( !a2 )\n return 1LL;\n v2 = a1;\n result = 1LL;\n if ( a1 )\n {\n v262 = 0;\n for ( i = a2; ; i = v4 )\n {\n v4 = v2 - 1;\n if ( i == 1 )\n break;\n v5 = i - 1;\n v6 = v2 - 1;\n v7 = i - 2;\n v259 = 0;\n v264 = v2 - 1;\n v8 = i - 2;\n v250 = v2;\n if ( v2 == 1 )\n {\n while ( 1 )\n {\n v259 += 2;\n if ( !v7 )\n break;\nLABEL_69:\n v5 = v250;\n v250 = v8;\n v6 = v8 - 1;\n v7 = v5 - 1;\n v8 = v5 - 1;\n if ( v6 )\n goto LABEL_6;\n }\n v99 = v259;\n v100 = i - 1;\n v101 = v264;\n }\n else\n {\nLABEL_6:\n v9 = v6;\n v10 = v7;\n v228 = v5;\n v11 = v6 - 1;\n v246 = 0;\n v252 = v6;\n v12 = v6 - 1;\n v255 = v7;\n if ( v7 )\n {\nLABEL_7:\n v13 = v10;\n v14 = v11;\n v238 = v11;\n v220 = 0;\n v15 = v10 - 1;\n v196 = v9;\n v16 = v10 - 1;\n v232 = v10;\n if ( v14 )\n {\nLABEL_8:\n v204 = v14;\n v17 = v13;\n v18 = v14;\n v19 = 0;\n for ( j = v15; ; j = v22 - 1 )\n {\n v21 = v18;\n v22 = v18 - 1;\n v18 = v17;\n v23 = func0(j, v21);\n v19 += func0(j, v22) + v23;\n if ( !v22 )\n break;\n v17 = v22;\n }\n v24 = v204;\n if ( v15 )\n {\n v205 = v19 + 1;\n v25 = v15;\n v26 = 0;\n while ( 1 )\n {\n v27 = v24;\n v28 = v24 - 1;\n v24 = v25;\n v29 = func0(v25 - 1, v27);\n v26 += func0(v25 - 1, v28) + v29;\n if ( !v28 )\n break;\n v25 = v28;\n }\n v16 = v15;\n v220 += v26 + v205 + 1;\n goto LABEL_16;\n }\n v31 = v232;\n v32 = v238;\n v30 = v19 + v220 + 2;\n }\n else\n {\n while ( 1 )\n {\n v220 += 2;\n if ( !v15 )\n break;\nLABEL_16:\n v13 = v196;\n v14 = v16 - 1;\n v196 = v16;\n v15 = v13 - 1;\n v16 = v13 - 1;\n if ( v14 )\n goto LABEL_8;\n }\n v30 = v220;\n v31 = v232;\n v32 = v238;\n }\n v33 = v30 + 1;\n if ( v32 )\n {\n v197 = v32;\n v34 = v31;\n v35 = v31 - 1;\n v233 = v33;\n v221 = 0;\n v36 = v31 - 1;\n v239 = v32;\n v37 = v32 - 1;\n if ( v32 == 1 )\n goto LABEL_30;\nLABEL_21:\n v38 = v37;\n v206 = v37;\n v39 = v34;\n v40 = 0;\n for ( k = v35; ; k = v43 - 1 )\n {\n v42 = v38;\n v43 = v38 - 1;\n v38 = v39;\n v44 = func0(k, v42);\n v40 += func0(k, v43) + v44;\n if ( !v43 )\n break;\n v39 = v43;\n }\n v45 = v206;\n if ( v35 )\n {\n v207 = v40 + 1;\n v46 = v35;\n v47 = 0;\n while ( 1 )\n {\n v48 = v45;\n v49 = v45 - 1;\n v45 = v46;\n v50 = func0(v46 - 1, v48);\n v47 += func0(v46 - 1, v49) + v50;\n if ( !v49 )\n break;\n v46 = v49;\n }\n v36 = v35;\n v221 += v47 + v207 + 1;\n do\n {\n v34 = v197;\n v197 = v36;\n v51 = v36;\n v35 = v34 - 1;\n v36 = v34 - 1;\n v37 = v51 - 1;\n if ( v37 )\n goto LABEL_21;\nLABEL_30:\n v221 += 2;\n }\n while ( v35 );\n v52 = v233;\n v53 = v221;\n v12 = v239;\n }\n else\n {\n v52 = v233;\n v12 = v239;\n v53 = v40 + v221 + 2;\n }\n v246 += v52 + v53 + 1;\n goto LABEL_33;\n }\n v55 = v252;\n v56 = v255;\n v54 = v30 + v246 + 2;\n }\n else\n {\n while ( 1 )\n {\n v246 += 2;\n if ( !v11 )\n break;\nLABEL_33:\n v9 = v228;\n v10 = v12 - 1;\n v228 = v12;\n v11 = v9 - 1;\n v12 = v9 - 1;\n if ( v10 )\n goto LABEL_7;\n }\n v54 = v246;\n v55 = v252;\n v56 = v255;\n }\n if ( v56 )\n {\n v253 = v54 + 1;\n v247 = 0;\n v229 = v56;\n v256 = v56;\n while ( 1 )\n {\n v57 = v55 - 1;\n if ( v229 == 1 )\n {\n v247 += 2;\n if ( v55 == 1 )\n {\n v97 = v253;\n v98 = v247;\n v8 = v256;\nLABEL_68:\n v259 += v97 + v98 + 1;\n goto LABEL_69;\n }\n }\n else\n {\n v58 = v229 - 1;\n v240 = v55 - 1;\n v59 = v229 - 2;\n v222 = 0;\n v198 = v55;\n v60 = v229 - 2;\n if ( v55 == 1 )\n {\n while ( 1 )\n {\n v222 += 2;\n if ( !v59 )\n break;\nLABEL_48:\n v58 = v198;\n v57 = v60 - 1;\n v198 = v60;\n v59 = v58 - 1;\n v60 = v58 - 1;\n if ( v57 )\n goto LABEL_40;\n }\n v74 = v222;\n v75 = v229 - 1;\n v76 = v240;\n }\n else\n {\nLABEL_40:\n v208 = v57;\n v61 = v58;\n v62 = v57;\n v63 = 0;\n for ( m = v59; ; m = v66 - 1 )\n {\n v65 = v62;\n v66 = v62 - 1;\n v62 = v61;\n v67 = func0(m, v65);\n v63 += func0(m, v66) + v67;\n if ( !v66 )\n break;\n v61 = v66;\n }\n v68 = v208;\n if ( v59 )\n {\n v209 = v63 + 1;\n v69 = v59;\n v70 = 0;\n while ( 1 )\n {\n v71 = v68;\n v72 = v68 - 1;\n v68 = v69;\n v73 = func0(v69 - 1, v71);\n v70 += func0(v69 - 1, v72) + v73;\n if ( !v72 )\n break;\n v69 = v72;\n }\n v60 = v59;\n v222 += v70 + v209 + 1;\n goto LABEL_48;\n }\n v75 = v229 - 1;\n v76 = v240;\n v74 = v63 + v222 + 2;\n }\n if ( !v76 )\n {\n v97 = v253;\n v8 = v256;\n v98 = v74 + v247 + 2;\n goto LABEL_68;\n }\n v199 = v76;\n v77 = v75;\n v234 = v74 + 1;\n v78 = v75 - 1;\n v223 = 0;\n v79 = v75 - 1;\n v241 = v76;\n v80 = v76 - 1;\n if ( v76 == 1 )\n {\n while ( 1 )\n {\n v223 += 2;\n if ( !v78 )\n break;\nLABEL_61:\n v77 = v199;\n v199 = v79;\n v94 = v79;\n v78 = v77 - 1;\n v79 = v77 - 1;\n v80 = v94 - 1;\n if ( v80 )\n goto LABEL_53;\n }\n v95 = v234;\n v96 = v223;\n v57 = v241;\n }\n else\n {\nLABEL_53:\n v81 = v80;\n v210 = v80;\n v82 = v77;\n v83 = 0;\n for ( n = v78; ; n = v86 - 1 )\n {\n v85 = v81;\n v86 = v81 - 1;\n v81 = v82;\n v87 = func0(n, v85);\n v83 += func0(n, v86) + v87;\n if ( !v86 )\n break;\n v82 = v86;\n }\n v88 = v210;\n if ( v78 )\n {\n v211 = v83 + 1;\n v89 = v78;\n v90 = 0;\n while ( 1 )\n {\n v91 = v88;\n v92 = v88 - 1;\n v88 = v89;\n v93 = func0(v89 - 1, v91);\n v90 += func0(v89 - 1, v92) + v93;\n if ( !v92 )\n break;\n v89 = v92;\n }\n v79 = v78;\n v223 += v90 + v211 + 1;\n goto LABEL_61;\n }\n v95 = v234;\n v57 = v241;\n v96 = v83 + v223 + 2;\n }\n v247 += v95 + v96 + 1;\n }\n v55 = v229;\n v229 = v57;\n }\n }\n v100 = i - 1;\n v101 = v264;\n v99 = v54 + v259 + 2;\n }\n if ( !v101 )\n {\n v195 = v99 + v262 + 2;\n return (unsigned int)(v195 + 1);\n }\n v251 = v101;\n v102 = v100;\n v263 = v99 + 1;\n v260 = 0;\n v265 = v101;\nLABEL_74:\n v103 = v102 - 1;\n if ( v251 != 1 )\n {\n v104 = v251 - 1;\n v230 = v102;\n v105 = v251 - 2;\n v248 = 0;\n v106 = v251 - 2;\n v257 = v102 - 1;\n if ( v102 == 1 )\n {\n while ( 1 )\n {\n v248 += 2;\n if ( !v105 )\n break;\nLABEL_102:\n v104 = v230;\n v103 = v106 - 1;\n v230 = v106;\n v105 = v104 - 1;\n v106 = v104 - 1;\n if ( v103 )\n goto LABEL_76;\n }\n v147 = v248;\n v148 = v251 - 1;\n v149 = v257;\n }\n else\n {\nLABEL_76:\n v107 = v103;\n v108 = v105;\n v242 = v105;\n v224 = 0;\n v109 = v103 - 1;\n v200 = v104;\n v110 = v103 - 1;\n v235 = v103;\n if ( v108 )\n {\nLABEL_77:\n v212 = v108;\n v111 = v107;\n v112 = v108;\n v113 = 0;\n for ( ii = v109; ; ii = v116 - 1 )\n {\n v115 = v112;\n v116 = v112 - 1;\n v112 = v111;\n v117 = func0(ii, v115);\n v113 += func0(ii, v116) + v117;\n if ( !v116 )\n break;\n v111 = v116;\n }\n v118 = v212;\n if ( v109 )\n {\n v213 = v113 + 1;\n v119 = v109;\n v120 = 0;\n while ( 1 )\n {\n v121 = v118;\n v122 = v118 - 1;\n v118 = v119;\n v123 = func0(v119 - 1, v121);\n v120 += func0(v119 - 1, v122) + v123;\n if ( !v122 )\n break;\n v119 = v122;\n }\n v110 = v109;\n v224 += v120 + v213 + 1;\n goto LABEL_85;\n }\n v125 = v235;\n v126 = v242;\n v124 = v113 + v224 + 2;\n }\n else\n {\n while ( 1 )\n {\n v224 += 2;\n if ( !v109 )\n break;\nLABEL_85:\n v107 = v200;\n v108 = v110 - 1;\n v200 = v110;\n v109 = v107 - 1;\n v110 = v107 - 1;\n if ( v108 )\n goto LABEL_77;\n }\n v124 = v224;\n v125 = v235;\n v126 = v242;\n }\n if ( v126 )\n {\n v201 = v126;\n v127 = v125;\n v236 = v124 + 1;\n v128 = v125 - 1;\n v225 = 0;\n v129 = v125 - 1;\n v243 = v126;\n v130 = v126 - 1;\n if ( v126 == 1 )\n goto LABEL_99;\nLABEL_90:\n v131 = v130;\n v214 = v130;\n v132 = v127;\n v133 = 0;\n for ( jj = v128; ; jj = v136 - 1 )\n {\n v135 = v131;\n v136 = v131 - 1;\n v131 = v132;\n v137 = func0(jj, v135);\n v133 += func0(jj, v136) + v137;\n if ( !v136 )\n break;\n v132 = v136;\n }\n v138 = v214;\n if ( v128 )\n {\n v215 = v133 + 1;\n v139 = v128;\n v140 = 0;\n while ( 1 )\n {\n v141 = v138;\n v142 = v138 - 1;\n v138 = v139;\n v143 = func0(v139 - 1, v141);\n v140 += func0(v139 - 1, v142) + v143;\n if ( !v142 )\n break;\n v139 = v142;\n }\n v129 = v128;\n v225 += v140 + v215 + 1;\n do\n {\n v127 = v201;\n v201 = v129;\n v144 = v129;\n v128 = v127 - 1;\n v129 = v127 - 1;\n v130 = v144 - 1;\n if ( v130 )\n goto LABEL_90;\nLABEL_99:\n v225 += 2;\n }\n while ( v128 );\n v145 = v236;\n v146 = v225;\n v106 = v243;\n }\n else\n {\n v145 = v236;\n v106 = v243;\n v146 = v133 + v225 + 2;\n }\n v248 += v145 + v146 + 1;\n goto LABEL_102;\n }\n v148 = v251 - 1;\n v149 = v257;\n v147 = v124 + v248 + 2;\n }\n if ( !v149 )\n {\n v193 = v263;\n v4 = v265;\n v194 = v147 + v260 + 2;\n goto LABEL_141;\n }\n v254 = v147 + 1;\n v249 = 0;\n v231 = v149;\n v258 = v149;\n while ( 1 )\n {\n v150 = v148 - 1;\n if ( v231 == 1 )\n {\n v249 += 2;\n if ( v148 == 1 )\n {\n v191 = v254;\n v192 = v249;\n v103 = v258;\n goto LABEL_137;\n }\n }\n else\n {\n v151 = v231 - 1;\n v244 = v148 - 1;\n v226 = 0;\n v152 = v231 - 2;\n v153 = v148 - 1;\n v202 = v148;\n v154 = v231 - 2;\n if ( v148 == 1 )\n {\n while ( 1 )\n {\n v226 += 2;\n if ( !v152 )\n break;\nLABEL_117:\n v151 = v202;\n v153 = v154 - 1;\n v202 = v154;\n v152 = v151 - 1;\n v154 = v151 - 1;\n if ( v153 )\n goto LABEL_109;\n }\n v168 = v226;\n v169 = v231 - 1;\n v170 = v244;\n }\n else\n {\nLABEL_109:\n v216 = v153;\n v155 = v151;\n v156 = v153;\n v157 = 0;\n for ( kk = v152; ; kk = v160 - 1 )\n {\n v159 = v156;\n v160 = v156 - 1;\n v156 = v155;\n v161 = func0(kk, v159);\n v157 += func0(kk, v160) + v161;\n if ( !v160 )\n break;\n v155 = v160;\n }\n v162 = v216;\n if ( v152 )\n {\n v217 = v157 + 1;\n v163 = v152;\n v164 = 0;\n while ( 1 )\n {\n v165 = v162;\n v166 = v162 - 1;\n v162 = v163;\n v167 = func0(v163 - 1, v165);\n v164 += func0(v163 - 1, v166) + v167;\n if ( !v166 )\n break;\n v163 = v166;\n }\n v154 = v152;\n v226 += v164 + v217 + 1;\n goto LABEL_117;\n }\n v169 = v231 - 1;\n v170 = v244;\n v168 = v157 + v226 + 2;\n }\n if ( !v170 )\n {\n v191 = v254;\n v103 = v258;\n v192 = v168 + v249 + 2;\nLABEL_137:\n v260 += v191 + v192 + 1;\nLABEL_138:\n v102 = v251;\n v251 = v103;\n goto LABEL_74;\n }\n v203 = v170;\n v171 = v169;\n v237 = v168 + 1;\n v172 = v169 - 1;\n v227 = 0;\n v173 = v169 - 1;\n v245 = v170;\n v174 = v170 - 1;\n if ( v170 == 1 )\n {\n while ( 1 )\n {\n v227 += 2;\n if ( !v172 )\n break;\nLABEL_130:\n v171 = v203;\n v203 = v173;\n v188 = v173;\n v172 = v171 - 1;\n v173 = v171 - 1;\n v174 = v188 - 1;\n if ( v174 )\n goto LABEL_122;\n }\n v189 = v237;\n v190 = v227;\n v150 = v245;\n }\n else\n {\nLABEL_122:\n v175 = v174;\n v218 = v174;\n v176 = v171;\n v177 = 0;\n for ( mm = v172; ; mm = v180 - 1 )\n {\n v179 = v175;\n v180 = v175 - 1;\n v175 = v176;\n v181 = func0(mm, v179);\n v177 += func0(mm, v180) + v181;\n if ( !v180 )\n break;\n v176 = v180;\n }\n v182 = v218;\n if ( v172 )\n {\n v219 = v177 + 1;\n v183 = v172;\n v184 = 0;\n while ( 1 )\n {\n v185 = v182;\n v186 = v182 - 1;\n v182 = v183;\n v187 = func0(v183 - 1, v185);\n v184 += func0(v183 - 1, v186) + v187;\n if ( !v186 )\n break;\n v183 = v186;\n }\n v173 = v172;\n v227 += v184 + v219 + 1;\n goto LABEL_130;\n }\n v189 = v237;\n v150 = v245;\n v190 = v177 + v227 + 2;\n }\n v249 += v189 + v190 + 1;\n }\n v148 = v231;\n v231 = v150;\n }\n }\n v260 += 2;\n if ( v102 != 1 )\n goto LABEL_138;\n v193 = v263;\n v194 = v260;\n v4 = v265;\nLABEL_141:\n v262 += v193 + v194 + 1;\nLABEL_142:\n v2 = i;\n }\n v262 += 2;\n if ( v2 != 1 )\n goto LABEL_142;\n v195 = v262;\n return (unsigned int)(v195 + 1);\n }\n return result;\n}", + "ida_strip_asm": "sub_1200:\nendbr64\ntest esi, esi\njz loc_1D7B\npush r15\nmov ecx, edi\nmov eax, 1\npush r14\npush r13\npush r12\nxor r12d, r12d\npush rbp\npush rbx\nsub rsp, 48h\ntest edi, edi\njz loc_1D6C\nmov [rsp+78h+var_44], r12d\nmov [rsp+78h+var_48], esi\nloc_1235:\nmov r9d, [rsp+78h+var_48]\nlea eax, [rcx-1]\nmov r14d, eax\nsub r9d, 1\njz loc_1D59\nmov esi, r9d\nmov ebp, eax\nmov [rsp+78h+var_40], r9d\nxor r15d, r15d\nmov r9d, ebp\nlea r14d, [rsi-1]\nmov [rsp+78h+var_4C], r15d\nmov [rsp+78h+var_3C], eax\nmov ebp, r14d\nmov [rsp+78h+var_58], ecx\ntest r9d, r9d\njz loc_17AD\nloc_1277:\nmov r8d, r9d\nxor r13d, r13d\nmov edx, r14d\nmov [rsp+78h+var_68], esi\nlea eax, [r8-1]\nmov [rsp+78h+var_5C], r13d\nmov [rsp+78h+var_54], r9d\nmov r15d, eax\nmov [rsp+78h+var_50], r14d\ntest edx, edx\njz loc_14EA\nloc_12A2:\nxor edi, edi\nmov ebp, edx\nmov esi, eax\nmov [rsp+78h+var_60], eax\nmov [rsp+78h+var_6C], edi\nlea edi, [rbp-1]\nmov [rsp+78h+var_78], r8d\nmov eax, edi\nmov [rsp+78h+var_64], edx\ntest esi, esi\njz loc_138A\nloc_12C5:\nmov [rsp+78h+var_74], esi\nxor r12d, r12d\nmov r14d, ebp\nmov r13d, esi\nmov [rsp+78h+var_70], edi\nmov ebp, r12d\nmov r12d, edi\nloc_12DC:\nmov esi, r13d\nmov edi, r12d\nlea r15d, [r13-1]\nmov r13d, r14d\ncall sub_1200\nmov esi, r15d\nmov edi, r12d\nmov ebx, eax\ncall sub_1200\nadd ebx, eax\nadd ebp, ebx\ntest r15d, r15d\njz short loc_1310\nmov r14d, r15d\nlea r12d, [r15-1]\njmp short loc_12DC\nloc_1310:\nmov eax, [rsp+78h+var_70]\nmov r14d, [rsp+78h+var_74]\nlea ebx, [rbp+1]\ntest eax, eax\njz loc_1EBB\nmov [rsp+78h+var_74], ebx\nmov r13d, eax\nmov ebx, r15d\nloc_132E:\nlea r15d, [r13-1]\nmov esi, r14d\nlea r12d, [r14-1]\nmov r14d, r13d\nmov edi, r15d\ncall sub_1200\nmov esi, r12d\nmov edi, r15d\nmov ebp, eax\ncall sub_1200\nadd ebp, eax\nadd ebx, ebp\ntest r12d, r12d\njz short loc_1360\nmov r13d, r12d\njmp short loc_132E\nloc_1360:\nmov r15d, ebx\nmov ebx, [rsp+78h+var_74]\nmov eax, [rsp+78h+var_70]\nlea edx, [r15+rbx+1]\nadd [rsp+78h+var_6C], edx\nloc_1374:\nmov ebp, [rsp+78h+var_78]\nlea esi, [rax-1]\nmov [rsp+78h+var_78], eax\nlea edi, [rbp-1]\nmov eax, edi\ntest esi, esi\njnz loc_12C5\nloc_138A:\nadd [rsp+78h+var_6C], 2\ntest edi, edi\njnz short loc_1374\nmov edi, [rsp+78h+var_6C]\nmov r9d, [rsp+78h+var_64]\nmov r15d, [rsp+78h+var_60]\nloc_13A1:\nlea r14d, [rdi+1]\ntest r15d, r15d\njz loc_1EA3\nmov [rsp+78h+var_78], r15d\nmov ebp, r9d\nmov r13d, [rsp+78h+var_78]\nxor esi, esi\nlea edi, [rbp-1]\nmov [rsp+78h+var_64], r14d\nmov [rsp+78h+var_6C], esi\nmov eax, edi\nmov [rsp+78h+var_60], r15d\nsub r13d, 1\njz loc_14AD\nloc_13D8:\nmov [rsp+78h+var_70], edi\nxor r12d, r12d\nmov r14d, r13d\nmov [rsp+78h+var_74], r13d\nmov r13d, ebp\nmov ebp, r12d\nmov r12d, edi\nloc_13F0:\nmov esi, r14d\nmov edi, r12d\nlea r15d, [r14-1]\nmov r14d, r13d\ncall sub_1200\nmov esi, r15d\nmov edi, r12d\nmov ebx, eax\ncall sub_1200\nadd ebx, eax\nadd ebp, ebx\ntest r15d, r15d\njz short loc_1428\nmov r13d, r15d\nlea r12d, [r15-1]\njmp short loc_13F0\nloc_1428:\nmov eax, [rsp+78h+var_70]\nmov r13d, [rsp+78h+var_74]\nlea ebx, [rbp+1]\ntest eax, eax\njz loc_1E8C\nmov [rsp+78h+var_74], ebx\nmov r14d, eax\nmov ebx, r15d\nloc_1446:\nlea r15d, [r14-1]\nmov esi, r13d\nlea r12d, [r13-1]\nmov r13d, r14d\nmov edi, r15d\ncall sub_1200\nmov esi, r12d\nmov edi, r15d\nmov ebp, eax\ncall sub_1200\nadd ebp, eax\nadd ebx, ebp\ntest r12d, r12d\njz short loc_1480\nmov r14d, r12d\njmp short loc_1446\nloc_1480:\nmov r15d, ebx\nmov ebx, [rsp+78h+var_74]\nmov eax, [rsp+78h+var_70]\nlea edx, [r15+rbx+1]\nadd [rsp+78h+var_6C], edx\nloc_1494:\nmov ebp, [rsp+78h+var_78]\nmov [rsp+78h+var_78], eax\nmov r13d, [rsp+78h+var_78]\nlea edi, [rbp-1]\nmov eax, edi\nsub r13d, 1\njnz loc_13D8\nloc_14AD:\nadd [rsp+78h+var_6C], 2\ntest edi, edi\njnz short loc_1494\nmov r14d, [rsp+78h+var_64]\nmov esi, [rsp+78h+var_6C]\nmov r15d, [rsp+78h+var_60]\nloc_14C4:\nlea eax, [r14+rsi+1]\nadd [rsp+78h+var_5C], eax\nloc_14CD:\nmov r8d, [rsp+78h+var_68]\nlea edx, [r15-1]\nmov [rsp+78h+var_68], r15d\nlea eax, [r8-1]\nmov r15d, eax\ntest edx, edx\njnz loc_12A2\nloc_14EA:\nadd [rsp+78h+var_5C], 2\ntest eax, eax\njnz short loc_14CD\nmov r13d, [rsp+78h+var_5C]\nmov r9d, [rsp+78h+var_54]\nmov ebp, [rsp+78h+var_50]\nloc_1501:\nlea ebx, [r13+1]\ntest ebp, ebp\njz loc_1E73\nxor r13d, r13d\nmov [rsp+78h+var_54], ebx\nmov [rsp+78h+var_5C], r13d\nmov [rsp+78h+var_68], ebp\nmov [rsp+78h+var_50], ebp\nloc_1521:\nmov r10d, [rsp+78h+var_68]\nlea eax, [r9-1]\nmov ecx, eax\nsub r10d, 1\njz loc_1770\nmov ebp, r10d\nxor edx, edx\nmov [rsp+78h+var_60], eax\nlea edi, [rbp-1]\nmov [rsp+78h+var_6C], edx\nmov [rsp+78h+var_78], r9d\nmov eax, edi\nmov [rsp+78h+var_64], r10d\ntest ecx, ecx\njz loc_162A\nloc_1559:\nmov [rsp+78h+var_74], ecx\nxor r12d, r12d\nmov r15d, ebp\nmov r14d, ecx\nmov [rsp+78h+var_70], edi\nmov ebp, r12d\nmov r12d, edi\nloc_1570:\nmov esi, r14d\nmov edi, r12d\nlea r13d, [r14-1]\nmov r14d, r15d\ncall sub_1200\nmov esi, r13d\nmov edi, r12d\nmov ebx, eax\ncall sub_1200\nadd ebx, eax\nadd ebp, ebx\ntest r13d, r13d\njz short loc_15A8\nmov r15d, r13d\nlea r12d, [r13-1]\njmp short loc_1570\nloc_15A8:\nmov eax, [rsp+78h+var_70]\nmov r15d, [rsp+78h+var_74]\nlea ebx, [rbp+1]\ntest eax, eax\njz loc_1E5D\nmov [rsp+78h+var_74], ebx\nmov r14d, eax\nmov ebx, r13d\nloc_15C6:\nlea r13d, [r14-1]\nmov esi, r15d\nlea r12d, [r15-1]\nmov r15d, r14d\nmov edi, r13d\ncall sub_1200\nmov esi, r12d\nmov edi, r13d\nmov ebp, eax\ncall sub_1200\nadd ebp, eax\nadd ebx, ebp\ntest r12d, r12d\njz short loc_1600\nmov r14d, r12d\njmp short loc_15C6\nloc_1600:\nmov r13d, ebx\nmov ebx, [rsp+78h+var_74]\nmov eax, [rsp+78h+var_70]\nlea edx, [r13+rbx+1]\nadd [rsp+78h+var_6C], edx\nloc_1614:\nmov ebp, [rsp+78h+var_78]\nlea ecx, [rax-1]\nmov [rsp+78h+var_78], eax\nlea edi, [rbp-1]\nmov eax, edi\ntest ecx, ecx\njnz loc_1559\nloc_162A:\nadd [rsp+78h+var_6C], 2\ntest edi, edi\njnz short loc_1614\nmov edx, [rsp+78h+var_6C]\nmov r10d, [rsp+78h+var_64]\nmov ecx, [rsp+78h+var_60]\nloc_1640:\nlea r14d, [rdx+1]\ntest ecx, ecx\njz loc_1E46\nmov [rsp+78h+var_78], ecx\nmov ebp, r10d\nxor esi, esi\nmov [rsp+78h+var_64], r14d\nmov r14d, [rsp+78h+var_78]\nlea edi, [rbp-1]\nmov [rsp+78h+var_6C], esi\nmov eax, edi\nmov [rsp+78h+var_60], ecx\nsub r14d, 1\njz loc_173D\nloc_1674:\nmov [rsp+78h+var_70], edi\nxor r12d, r12d\nmov r15d, r14d\nmov [rsp+78h+var_74], r14d\nmov r14d, ebp\nmov ebp, r12d\nmov r12d, edi\nloc_168C:\nmov esi, r15d\nmov edi, r12d\nlea r13d, [r15-1]\nmov r15d, r14d\ncall sub_1200\nmov esi, r13d\nmov edi, r12d\nmov ebx, eax\ncall sub_1200\nadd ebx, eax\nadd ebp, ebx\ntest r13d, r13d\njz short loc_16C0\nmov r14d, r13d\nlea r12d, [r13-1]\njmp short loc_168C\nloc_16C0:\nmov eax, [rsp+78h+var_70]\nmov r14d, [rsp+78h+var_74]\nlea ebx, [rbp+1]\ntest eax, eax\njz loc_1E30\nmov [rsp+78h+var_74], ebx\nmov r15d, eax\nmov ebx, r13d\nloc_16DE:\nlea r13d, [r15-1]\nmov esi, r14d\nlea r12d, [r14-1]\nmov r14d, r15d\nmov edi, r13d\ncall sub_1200\nmov esi, r12d\nmov edi, r13d\nmov ebp, eax\ncall sub_1200\nadd ebp, eax\nadd ebx, ebp\ntest r12d, r12d\njz short loc_1710\nmov r15d, r12d\njmp short loc_16DE\nloc_1710:\nmov r13d, ebx\nmov ebx, [rsp+78h+var_74]\nmov eax, [rsp+78h+var_70]\nlea edx, [r13+rbx+1]\nadd [rsp+78h+var_6C], edx\nloc_1724:\nmov ebp, [rsp+78h+var_78]\nmov [rsp+78h+var_78], eax\nmov r14d, [rsp+78h+var_78]\nlea edi, [rbp-1]\nmov eax, edi\nsub r14d, 1\njnz loc_1674\nloc_173D:\nadd [rsp+78h+var_6C], 2\ntest edi, edi\njnz short loc_1724\nmov r14d, [rsp+78h+var_64]\nmov esi, [rsp+78h+var_6C]\nmov ecx, [rsp+78h+var_60]\nloc_1753:\nlea eax, [r14+rsi+1]\nadd [rsp+78h+var_5C], eax\nloc_175C:\nmov r9d, [rsp+78h+var_68]\nmov [rsp+78h+var_68], ecx\njmp loc_1521\nloc_1770:\nadd [rsp+78h+var_5C], 2\ntest eax, eax\njnz short loc_175C\nmov ebx, [rsp+78h+var_54]\nmov r13d, [rsp+78h+var_5C]\nmov ebp, [rsp+78h+var_50]\nloc_1786:\nlea eax, [rbx+r13+1]\nadd [rsp+78h+var_4C], eax\nloc_178F:\nmov esi, [rsp+78h+var_58]\nmov [rsp+78h+var_58], ebp\nlea ebp, [rbp-1]\nmov r9d, ebp\nlea r14d, [rsi-1]\nmov ebp, r14d\ntest r9d, r9d\njnz loc_1277\nloc_17AD:\nadd [rsp+78h+var_4C], 2\ntest r14d, r14d\njnz short loc_178F\nmov r15d, [rsp+78h+var_4C]\nmov r9d, [rsp+78h+var_40]\nmov r14d, [rsp+78h+var_3C]\nloc_17C6:\nlea ebx, [r15+1]\ntest r14d, r14d\njz loc_1E21\nxor ecx, ecx\nmov [rsp+78h+var_58], r14d\nmov esi, r9d\nmov [rsp+78h+var_40], ebx\nmov [rsp+78h+var_4C], ecx\nmov [rsp+78h+var_3C], r14d\nloc_17EA:\nmov r9d, [rsp+78h+var_58]\nlea r13d, [rsi-1]\nmov edx, r13d\nsub r9d, 1\njz loc_1D2C\nmov r8d, r9d\nxor r12d, r12d\nmov [rsp+78h+var_68], esi\nlea eax, [r8-1]\nmov [rsp+78h+var_5C], r12d\nmov [rsp+78h+var_54], r9d\nmov r15d, eax\nmov [rsp+78h+var_50], r13d\ntest edx, edx\njz loc_1A7A\nloc_1828:\nxor edi, edi\nmov ebp, edx\nmov esi, eax\nmov [rsp+78h+var_60], eax\nmov [rsp+78h+var_6C], edi\nlea edi, [rbp-1]\nmov [rsp+78h+var_78], r8d\nmov eax, edi\nmov [rsp+78h+var_64], edx\ntest esi, esi\njz loc_191A\nloc_184B:\nmov [rsp+78h+var_74], esi\nxor r14d, r14d\nmov r13d, ebp\nmov r12d, esi\nmov [rsp+78h+var_70], edi\nmov ebp, r14d\nmov r14d, edi\nloc_1862:\nmov esi, r12d\nmov edi, r14d\nlea r15d, [r12-1]\nmov r12d, r13d\ncall sub_1200\nmov esi, r15d\nmov edi, r14d\nmov ebx, eax\ncall sub_1200\nadd ebx, eax\nadd ebp, ebx\ntest r15d, r15d\njz short loc_1898\nmov r13d, r15d\nlea r14d, [r15-1]\njmp short loc_1862\nloc_1898:\nmov eax, [rsp+78h+var_70]\nmov r13d, [rsp+78h+var_74]\nlea ebx, [rbp+1]\ntest eax, eax\njz loc_1E0A\nmov [rsp+78h+var_74], ebx\nmov r14d, eax\nmov ebx, r15d\nloc_18B6:\nlea r15d, [r14-1]\nmov esi, r13d\nlea r12d, [r13-1]\nmov r13d, r14d\nmov edi, r15d\ncall sub_1200\nmov esi, r12d\nmov edi, r15d\nmov ebp, eax\ncall sub_1200\nadd ebp, eax\nadd ebx, ebp\ntest r12d, r12d\njz short loc_18F0\nmov r14d, r12d\njmp short loc_18B6\nloc_18F0:\nmov r15d, ebx\nmov ebx, [rsp+78h+var_74]\nmov eax, [rsp+78h+var_70]\nlea edx, [r15+rbx+1]\nadd [rsp+78h+var_6C], edx\nloc_1904:\nmov ebp, [rsp+78h+var_78]\nlea esi, [rax-1]\nmov [rsp+78h+var_78], eax\nlea edi, [rbp-1]\nmov eax, edi\ntest esi, esi\njnz loc_184B\nloc_191A:\nadd [rsp+78h+var_6C], 2\ntest edi, edi\njnz short loc_1904\nmov edi, [rsp+78h+var_6C]\nmov r9d, [rsp+78h+var_64]\nmov r15d, [rsp+78h+var_60]\nloc_1931:\nlea r13d, [rdi+1]\ntest r15d, r15d\njz loc_1DF2\nmov [rsp+78h+var_78], r15d\nmov ebp, r9d\nxor esi, esi\nmov [rsp+78h+var_64], r13d\nmov r13d, [rsp+78h+var_78]\nlea edi, [rbp-1]\nmov [rsp+78h+var_6C], esi\nmov eax, edi\nmov [rsp+78h+var_60], r15d\nsub r13d, 1\njz loc_1A3D\nloc_1968:\nmov [rsp+78h+var_70], edi\nxor r14d, r14d\nmov r12d, r13d\nmov [rsp+78h+var_74], r13d\nmov r13d, ebp\nmov ebp, r14d\nmov r14d, edi\nloc_1980:\nmov esi, r12d\nmov edi, r14d\nlea r15d, [r12-1]\nmov r12d, r13d\ncall sub_1200\nmov esi, r15d\nmov edi, r14d\nmov ebx, eax\ncall sub_1200\nadd ebx, eax\nadd ebp, ebx\ntest r15d, r15d\njz short loc_19B8\nmov r13d, r15d\nlea r14d, [r15-1]\njmp short loc_1980\nloc_19B8:\nmov eax, [rsp+78h+var_70]\nmov r13d, [rsp+78h+var_74]\nlea ebx, [rbp+1]\ntest eax, eax\njz loc_1DDB\nmov [rsp+78h+var_74], ebx\nmov r14d, eax\nmov ebx, r15d\nloc_19D6:\nlea r15d, [r14-1]\nmov esi, r13d\nlea r12d, [r13-1]\nmov r13d, r14d\nmov edi, r15d\ncall sub_1200\nmov esi, r12d\nmov edi, r15d\nmov ebp, eax\ncall sub_1200\nadd ebp, eax\nadd ebx, ebp\ntest r12d, r12d\njz short loc_1A10\nmov r14d, r12d\njmp short loc_19D6\nloc_1A10:\nmov r15d, ebx\nmov ebx, [rsp+78h+var_74]\nmov eax, [rsp+78h+var_70]\nlea edx, [r15+rbx+1]\nadd [rsp+78h+var_6C], edx\nloc_1A24:\nmov ebp, [rsp+78h+var_78]\nmov [rsp+78h+var_78], eax\nmov r13d, [rsp+78h+var_78]\nlea edi, [rbp-1]\nmov eax, edi\nsub r13d, 1\njnz loc_1968\nloc_1A3D:\nadd [rsp+78h+var_6C], 2\ntest edi, edi\njnz short loc_1A24\nmov r13d, [rsp+78h+var_64]\nmov esi, [rsp+78h+var_6C]\nmov r15d, [rsp+78h+var_60]\nloc_1A54:\nlea eax, [r13+rsi+1]\nadd [rsp+78h+var_5C], eax\nloc_1A5D:\nmov r8d, [rsp+78h+var_68]\nlea edx, [r15-1]\nmov [rsp+78h+var_68], r15d\nlea eax, [r8-1]\nmov r15d, eax\ntest edx, edx\njnz loc_1828\nloc_1A7A:\nadd [rsp+78h+var_5C], 2\ntest eax, eax\njnz short loc_1A5D\nmov r12d, [rsp+78h+var_5C]\nmov r9d, [rsp+78h+var_54]\nmov edx, [rsp+78h+var_50]\nloc_1A91:\nlea ebp, [r12+1]\ntest edx, edx\njz loc_1DC4\nxor r13d, r13d\nmov [rsp+78h+var_54], ebp\nmov [rsp+78h+var_5C], r13d\nmov [rsp+78h+var_68], edx\nmov [rsp+78h+var_50], edx\nloc_1AB2:\nmov r8d, [rsp+78h+var_68]\nlea eax, [r9-1]\nmov edx, eax\nsub r8d, 1\njz loc_1D00\nxor esi, esi\nmov ebp, r8d\nmov [rsp+78h+var_60], eax\nmov [rsp+78h+var_6C], esi\nlea edi, [rbp-1]\nmov esi, eax\nmov [rsp+78h+var_78], r9d\nmov eax, edi\nmov [rsp+78h+var_64], r8d\ntest esi, esi\njz loc_1BBA\nloc_1AEC:\nmov [rsp+78h+var_74], esi\nxor r12d, r12d\nmov r15d, ebp\nmov r14d, esi\nmov [rsp+78h+var_70], edi\nmov ebp, r12d\nmov r12d, edi\nloc_1B03:\nmov esi, r14d\nmov edi, r12d\nlea r13d, [r14-1]\nmov r14d, r15d\ncall sub_1200\nmov esi, r13d\nmov edi, r12d\nmov ebx, eax\ncall sub_1200\nadd ebx, eax\nadd ebp, ebx\ntest r13d, r13d\njz short loc_1B38\nmov r15d, r13d\nlea r12d, [r13-1]\njmp short loc_1B03\nloc_1B38:\nmov eax, [rsp+78h+var_70]\nmov r15d, [rsp+78h+var_74]\nlea ebx, [rbp+1]\ntest eax, eax\njz loc_1DAE\nmov [rsp+78h+var_74], ebx\nmov r14d, eax\nmov ebx, r13d\nloc_1B56:\nlea r13d, [r14-1]\nmov esi, r15d\nlea r12d, [r15-1]\nmov r15d, r14d\nmov edi, r13d\ncall sub_1200\nmov esi, r12d\nmov edi, r13d\nmov ebp, eax\ncall sub_1200\nadd ebp, eax\nadd ebx, ebp\ntest r12d, r12d\njz short loc_1B90\nmov r14d, r12d\njmp short loc_1B56\nloc_1B90:\nmov r13d, ebx\nmov ebx, [rsp+78h+var_74]\nmov eax, [rsp+78h+var_70]\nlea edx, [r13+rbx+1]\nadd [rsp+78h+var_6C], edx\nloc_1BA4:\nmov ebp, [rsp+78h+var_78]\nlea esi, [rax-1]\nmov [rsp+78h+var_78], eax\nlea edi, [rbp-1]\nmov eax, edi\ntest esi, esi\njnz loc_1AEC\nloc_1BBA:\nadd [rsp+78h+var_6C], 2\ntest edi, edi\njnz short loc_1BA4\nmov esi, [rsp+78h+var_6C]\nmov r8d, [rsp+78h+var_64]\nmov edx, [rsp+78h+var_60]\nloc_1BD0:\nlea r14d, [rsi+1]\ntest edx, edx\njz loc_1D97\nmov [rsp+78h+var_78], edx\nmov ebp, r8d\nxor esi, esi\nmov [rsp+78h+var_64], r14d\nmov r14d, [rsp+78h+var_78]\nlea edi, [rbp-1]\nmov [rsp+78h+var_6C], esi\nmov eax, edi\nmov [rsp+78h+var_60], edx\nsub r14d, 1\njz loc_1CCD\nloc_1C04:\nmov [rsp+78h+var_70], edi\nxor r12d, r12d\nmov r15d, r14d\nmov [rsp+78h+var_74], r14d\nmov r14d, ebp\nmov ebp, r12d\nmov r12d, edi\nloc_1C1C:\nmov esi, r15d\nmov edi, r12d\nlea r13d, [r15-1]\nmov r15d, r14d\ncall sub_1200\nmov esi, r13d\nmov edi, r12d\nmov ebx, eax\ncall sub_1200\nadd ebx, eax\nadd ebp, ebx\ntest r13d, r13d\njz short loc_1C50\nmov r14d, r13d\nlea r12d, [r13-1]\njmp short loc_1C1C\nloc_1C50:\nmov eax, [rsp+78h+var_70]\nmov r14d, [rsp+78h+var_74]\nlea ebx, [rbp+1]\ntest eax, eax\njz loc_1D81\nmov [rsp+78h+var_74], ebx\nmov r15d, eax\nmov ebx, r13d\nloc_1C6E:\nlea r13d, [r15-1]\nmov esi, r14d\nlea r12d, [r14-1]\nmov r14d, r15d\nmov edi, r13d\ncall sub_1200\nmov esi, r12d\nmov edi, r13d\nmov ebp, eax\ncall sub_1200\nadd ebp, eax\nadd ebx, ebp\ntest r12d, r12d\njz short loc_1CA0\nmov r15d, r12d\njmp short loc_1C6E\nloc_1CA0:\nmov r13d, ebx\nmov ebx, [rsp+78h+var_74]\nmov eax, [rsp+78h+var_70]\nlea edx, [r13+rbx+1]\nadd [rsp+78h+var_6C], edx\nloc_1CB4:\nmov ebp, [rsp+78h+var_78]\nmov [rsp+78h+var_78], eax\nmov r14d, [rsp+78h+var_78]\nlea edi, [rbp-1]\nmov eax, edi\nsub r14d, 1\njnz loc_1C04\nloc_1CCD:\nadd [rsp+78h+var_6C], 2\ntest edi, edi\njnz short loc_1CB4\nmov r14d, [rsp+78h+var_64]\nmov esi, [rsp+78h+var_6C]\nmov edx, [rsp+78h+var_60]\nloc_1CE3:\nlea eax, [r14+rsi+1]\nadd [rsp+78h+var_5C], eax\nloc_1CEC:\nmov r9d, [rsp+78h+var_68]\nmov [rsp+78h+var_68], edx\njmp loc_1AB2\nloc_1D00:\nadd [rsp+78h+var_5C], 2\ntest eax, eax\njnz short loc_1CEC\nmov ebp, [rsp+78h+var_54]\nmov r13d, [rsp+78h+var_5C]\nmov edx, [rsp+78h+var_50]\nloc_1D16:\nlea eax, [rbp+r13+1]\nadd [rsp+78h+var_4C], eax\nloc_1D1F:\nmov esi, [rsp+78h+var_58]\nmov [rsp+78h+var_58], edx\njmp loc_17EA\nloc_1D2C:\nadd [rsp+78h+var_4C], 2\ntest r13d, r13d\njnz short loc_1D1F\nmov ebx, [rsp+78h+var_40]\nmov ecx, [rsp+78h+var_4C]\nmov r14d, [rsp+78h+var_3C]\nloc_1D43:\nlea eax, [rbx+rcx+1]\nadd [rsp+78h+var_44], eax\nloc_1D4B:\nmov ecx, [rsp+78h+var_48]\nmov [rsp+78h+var_48], r14d\njmp loc_1235\nloc_1D59:\nadd [rsp+78h+var_44], 2\ntest eax, eax\njnz short loc_1D4B\nmov r12d, [rsp+78h+var_44]\nloc_1D67:\nlea eax, [r12+1]\nloc_1D6C:\nadd rsp, 48h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1D7B:\nmov eax, 1\nretn\nloc_1D81:\nmov esi, [rsp+78h+var_6C]\nmov r14d, [rsp+78h+var_64]\nmov edx, [rsp+78h+var_60]\nlea esi, [rbp+rsi+2]\njmp loc_1CE3\nloc_1D97:\nmov r13d, [rsp+78h+var_5C]\nmov ebp, [rsp+78h+var_54]\nmov edx, [rsp+78h+var_50]\nlea r13d, [rsi+r13+2]\njmp loc_1D16\nloc_1DAE:\nmov esi, [rsp+78h+var_6C]\nmov r8d, [rsp+78h+var_64]\nmov edx, [rsp+78h+var_60]\nlea esi, [rbp+rsi+2]\njmp loc_1BD0\nloc_1DC4:\nmov ecx, [rsp+78h+var_4C]\nmov ebx, [rsp+78h+var_40]\nmov r14d, [rsp+78h+var_3C]\nlea ecx, [r12+rcx+2]\njmp loc_1D43\nloc_1DDB:\nmov esi, [rsp+78h+var_6C]\nmov r13d, [rsp+78h+var_64]\nmov r15d, [rsp+78h+var_60]\nlea esi, [rbp+rsi+2]\njmp loc_1A54\nloc_1DF2:\nmov r12d, [rsp+78h+var_5C]\nmov r9d, [rsp+78h+var_54]\nmov edx, [rsp+78h+var_50]\nlea r12d, [rdi+r12+2]\njmp loc_1A91\nloc_1E0A:\nmov edi, [rsp+78h+var_6C]\nmov r9d, [rsp+78h+var_64]\nmov r15d, [rsp+78h+var_60]\nlea edi, [rbp+rdi+2]\njmp loc_1931\nloc_1E21:\nmov r12d, [rsp+78h+var_44]\nlea r12d, [r15+r12+2]\njmp loc_1D67\nloc_1E30:\nmov esi, [rsp+78h+var_6C]\nmov r14d, [rsp+78h+var_64]\nmov ecx, [rsp+78h+var_60]\nlea esi, [rbp+rsi+2]\njmp loc_1753\nloc_1E46:\nmov r13d, [rsp+78h+var_5C]\nmov ebx, [rsp+78h+var_54]\nmov ebp, [rsp+78h+var_50]\nlea r13d, [rdx+r13+2]\njmp loc_1786\nloc_1E5D:\nmov edx, [rsp+78h+var_6C]\nmov r10d, [rsp+78h+var_64]\nmov ecx, [rsp+78h+var_60]\nlea edx, [rbp+rdx+2]\njmp loc_1640\nloc_1E73:\nmov r15d, [rsp+78h+var_4C]\nmov r9d, [rsp+78h+var_40]\nmov r14d, [rsp+78h+var_3C]\nlea r15d, [r13+r15+2]\njmp loc_17C6\nloc_1E8C:\nmov esi, [rsp+78h+var_6C]\nmov r14d, [rsp+78h+var_64]\nmov r15d, [rsp+78h+var_60]\nlea esi, [rbp+rsi+2]\njmp loc_14C4\nloc_1EA3:\nmov r13d, [rsp+78h+var_5C]\nmov r9d, [rsp+78h+var_54]\nmov ebp, [rsp+78h+var_50]\nlea r13d, [rdi+r13+2]\njmp loc_1501\nloc_1EBB:\nmov edi, [rsp+78h+var_6C]\nmov r9d, [rsp+78h+var_64]\nmov r15d, [rsp+78h+var_60]\nlea edi, [rbp+rdi+2]\njmp loc_13A1", + "ida_strip_pseudo": "__int64 __fastcall sub_1200(unsigned int a1, unsigned int a2)\n{\n unsigned int v2; // ecx\n __int64 result; // rax\n unsigned int v4; // r14d\n unsigned int v5; // esi\n unsigned int v6; // r9d\n unsigned int v7; // r14d\n unsigned int v8; // ebp\n unsigned int v9; // r8d\n unsigned int v10; // edx\n unsigned int v11; // eax\n unsigned int v12; // r15d\n unsigned int v13; // ebp\n unsigned int v14; // esi\n unsigned int v15; // edi\n unsigned int v16; // eax\n unsigned int v17; // r14d\n unsigned int v18; // r13d\n int v19; // ebp\n unsigned int j; // r12d\n __int64 v21; // rsi\n unsigned int v22; // r15d\n int v23; // ebx\n unsigned int v24; // r14d\n unsigned int v25; // r13d\n int v26; // ebx\n __int64 v27; // rsi\n unsigned int v28; // r12d\n int v29; // ebp\n int v30; // edi\n unsigned int v31; // r9d\n unsigned int v32; // r15d\n int v33; // r14d\n unsigned int v34; // ebp\n unsigned int v35; // edi\n unsigned int v36; // eax\n unsigned int v37; // r13d\n unsigned int v38; // r14d\n unsigned int v39; // r13d\n int v40; // ebp\n unsigned int k; // r12d\n __int64 v42; // rsi\n unsigned int v43; // r15d\n int v44; // ebx\n unsigned int v45; // r13d\n unsigned int v46; // r14d\n int v47; // ebx\n __int64 v48; // rsi\n unsigned int v49; // r12d\n int v50; // ebp\n unsigned int v51; // r13d\n int v52; // r14d\n int v53; // esi\n int v54; // r13d\n unsigned int v55; // r9d\n unsigned int v56; // ebp\n unsigned int v57; // ecx\n unsigned int v58; // ebp\n unsigned int v59; // edi\n unsigned int v60; // eax\n unsigned int v61; // r15d\n unsigned int v62; // r14d\n int v63; // ebp\n unsigned int m; // r12d\n __int64 v65; // rsi\n unsigned int v66; // r13d\n int v67; // ebx\n unsigned int v68; // r15d\n unsigned int v69; // r14d\n int v70; // ebx\n __int64 v71; // rsi\n unsigned int v72; // r12d\n int v73; // ebp\n int v74; // edx\n unsigned int v75; // r10d\n unsigned int v76; // ecx\n unsigned int v77; // ebp\n unsigned int v78; // edi\n unsigned int v79; // eax\n unsigned int v80; // r14d\n unsigned int v81; // r15d\n unsigned int v82; // r14d\n int v83; // ebp\n unsigned int n; // r12d\n __int64 v85; // rsi\n unsigned int v86; // r13d\n int v87; // ebx\n unsigned int v88; // r14d\n unsigned int v89; // r15d\n int v90; // ebx\n __int64 v91; // rsi\n unsigned int v92; // r12d\n int v93; // ebp\n unsigned int v94; // r14d\n int v95; // r14d\n int v96; // esi\n int v97; // ebx\n int v98; // r13d\n int v99; // r15d\n unsigned int v100; // r9d\n unsigned int v101; // r14d\n unsigned int v102; // esi\n unsigned int v103; // edx\n unsigned int v104; // r8d\n unsigned int v105; // eax\n unsigned int v106; // r15d\n unsigned int v107; // ebp\n unsigned int v108; // esi\n unsigned int v109; // edi\n unsigned int v110; // eax\n unsigned int v111; // r13d\n unsigned int v112; // r12d\n int v113; // ebp\n unsigned int ii; // r14d\n __int64 v115; // rsi\n unsigned int v116; // r15d\n int v117; // ebx\n unsigned int v118; // r13d\n unsigned int v119; // r14d\n int v120; // ebx\n __int64 v121; // rsi\n unsigned int v122; // r12d\n int v123; // ebp\n int v124; // edi\n unsigned int v125; // r9d\n unsigned int v126; // r15d\n unsigned int v127; // ebp\n unsigned int v128; // edi\n unsigned int v129; // eax\n unsigned int v130; // r13d\n unsigned int v131; // r12d\n unsigned int v132; // r13d\n int v133; // ebp\n unsigned int jj; // r14d\n __int64 v135; // rsi\n unsigned int v136; // r15d\n int v137; // ebx\n unsigned int v138; // r13d\n unsigned int v139; // r14d\n int v140; // ebx\n __int64 v141; // rsi\n unsigned int v142; // r12d\n int v143; // ebp\n unsigned int v144; // r13d\n int v145; // r13d\n int v146; // esi\n int v147; // r12d\n unsigned int v148; // r9d\n unsigned int v149; // edx\n unsigned int v150; // edx\n unsigned int v151; // ebp\n unsigned int v152; // edi\n unsigned int v153; // esi\n unsigned int v154; // eax\n unsigned int v155; // r15d\n unsigned int v156; // r14d\n int v157; // ebp\n unsigned int kk; // r12d\n __int64 v159; // rsi\n unsigned int v160; // r13d\n int v161; // ebx\n unsigned int v162; // r15d\n unsigned int v163; // r14d\n int v164; // ebx\n __int64 v165; // rsi\n unsigned int v166; // r12d\n int v167; // ebp\n int v168; // esi\n unsigned int v169; // r8d\n unsigned int v170; // edx\n unsigned int v171; // ebp\n unsigned int v172; // edi\n unsigned int v173; // eax\n unsigned int v174; // r14d\n unsigned int v175; // r15d\n unsigned int v176; // r14d\n int v177; // ebp\n unsigned int mm; // r12d\n __int64 v179; // rsi\n unsigned int v180; // r13d\n int v181; // ebx\n unsigned int v182; // r14d\n unsigned int v183; // r15d\n int v184; // ebx\n __int64 v185; // rsi\n unsigned int v186; // r12d\n int v187; // ebp\n unsigned int v188; // r14d\n int v189; // r14d\n int v190; // esi\n int v191; // ebp\n int v192; // r13d\n int v193; // ebx\n int v194; // ecx\n int v195; // r12d\n unsigned int v196; // [rsp+0h] [rbp-78h]\n unsigned int v197; // [rsp+0h] [rbp-78h]\n unsigned int v198; // [rsp+0h] [rbp-78h]\n unsigned int v199; // [rsp+0h] [rbp-78h]\n unsigned int v200; // [rsp+0h] [rbp-78h]\n unsigned int v201; // [rsp+0h] [rbp-78h]\n unsigned int v202; // [rsp+0h] [rbp-78h]\n unsigned int v203; // [rsp+0h] [rbp-78h]\n unsigned int v204; // [rsp+4h] [rbp-74h]\n int v205; // [rsp+4h] [rbp-74h]\n unsigned int v206; // [rsp+4h] [rbp-74h]\n int v207; // [rsp+4h] [rbp-74h]\n unsigned int v208; // [rsp+4h] [rbp-74h]\n int v209; // [rsp+4h] [rbp-74h]\n unsigned int v210; // [rsp+4h] [rbp-74h]\n int v211; // [rsp+4h] [rbp-74h]\n unsigned int v212; // [rsp+4h] [rbp-74h]\n int v213; // [rsp+4h] [rbp-74h]\n unsigned int v214; // [rsp+4h] [rbp-74h]\n int v215; // [rsp+4h] [rbp-74h]\n unsigned int v216; // [rsp+4h] [rbp-74h]\n int v217; // [rsp+4h] [rbp-74h]\n unsigned int v218; // [rsp+4h] [rbp-74h]\n int v219; // [rsp+4h] [rbp-74h]\n int v220; // [rsp+Ch] [rbp-6Ch]\n int v221; // [rsp+Ch] [rbp-6Ch]\n int v222; // [rsp+Ch] [rbp-6Ch]\n int v223; // [rsp+Ch] [rbp-6Ch]\n int v224; // [rsp+Ch] [rbp-6Ch]\n int v225; // [rsp+Ch] [rbp-6Ch]\n int v226; // [rsp+Ch] [rbp-6Ch]\n int v227; // [rsp+Ch] [rbp-6Ch]\n unsigned int v228; // [rsp+10h] [rbp-68h]\n unsigned int v229; // [rsp+10h] [rbp-68h]\n unsigned int v230; // [rsp+10h] [rbp-68h]\n unsigned int v231; // [rsp+10h] [rbp-68h]\n unsigned int v232; // [rsp+14h] [rbp-64h]\n int v233; // [rsp+14h] [rbp-64h]\n int v234; // [rsp+14h] [rbp-64h]\n unsigned int v235; // [rsp+14h] [rbp-64h]\n int v236; // [rsp+14h] [rbp-64h]\n int v237; // [rsp+14h] [rbp-64h]\n unsigned int v238; // [rsp+18h] [rbp-60h]\n unsigned int v239; // [rsp+18h] [rbp-60h]\n unsigned int v240; // [rsp+18h] [rbp-60h]\n unsigned int v241; // [rsp+18h] [rbp-60h]\n unsigned int v242; // [rsp+18h] [rbp-60h]\n unsigned int v243; // [rsp+18h] [rbp-60h]\n unsigned int v244; // [rsp+18h] [rbp-60h]\n unsigned int v245; // [rsp+18h] [rbp-60h]\n int v246; // [rsp+1Ch] [rbp-5Ch]\n int v247; // [rsp+1Ch] [rbp-5Ch]\n int v248; // [rsp+1Ch] [rbp-5Ch]\n int v249; // [rsp+1Ch] [rbp-5Ch]\n unsigned int v250; // [rsp+20h] [rbp-58h]\n unsigned int v251; // [rsp+20h] [rbp-58h]\n unsigned int v252; // [rsp+24h] [rbp-54h]\n int v253; // [rsp+24h] [rbp-54h]\n int v254; // [rsp+24h] [rbp-54h]\n unsigned int v255; // [rsp+28h] [rbp-50h]\n unsigned int v256; // [rsp+28h] [rbp-50h]\n unsigned int v257; // [rsp+28h] [rbp-50h]\n unsigned int v258; // [rsp+28h] [rbp-50h]\n int v259; // [rsp+2Ch] [rbp-4Ch]\n int v260; // [rsp+2Ch] [rbp-4Ch]\n unsigned int i; // [rsp+30h] [rbp-48h]\n int v262; // [rsp+34h] [rbp-44h]\n int v263; // [rsp+38h] [rbp-40h]\n unsigned int v264; // [rsp+3Ch] [rbp-3Ch]\n unsigned int v265; // [rsp+3Ch] [rbp-3Ch]\n\n if ( !a2 )\n return 1LL;\n v2 = a1;\n result = 1LL;\n if ( a1 )\n {\n v262 = 0;\n for ( i = a2; ; i = v4 )\n {\n v4 = v2 - 1;\n if ( i == 1 )\n break;\n v5 = i - 1;\n v6 = v2 - 1;\n v7 = i - 2;\n v259 = 0;\n v264 = v2 - 1;\n v8 = i - 2;\n v250 = v2;\n if ( v2 == 1 )\n {\n while ( 1 )\n {\n v259 += 2;\n if ( !v7 )\n break;\nLABEL_69:\n v5 = v250;\n v250 = v8;\n v6 = v8 - 1;\n v7 = v5 - 1;\n v8 = v5 - 1;\n if ( v6 )\n goto LABEL_6;\n }\n v99 = v259;\n v100 = i - 1;\n v101 = v264;\n }\n else\n {\nLABEL_6:\n v9 = v6;\n v10 = v7;\n v228 = v5;\n v11 = v6 - 1;\n v246 = 0;\n v252 = v6;\n v12 = v6 - 1;\n v255 = v7;\n if ( v7 )\n {\nLABEL_7:\n v13 = v10;\n v14 = v11;\n v238 = v11;\n v220 = 0;\n v15 = v10 - 1;\n v196 = v9;\n v16 = v10 - 1;\n v232 = v10;\n if ( v14 )\n {\nLABEL_8:\n v204 = v14;\n v17 = v13;\n v18 = v14;\n v19 = 0;\n for ( j = v15; ; j = v22 - 1 )\n {\n v21 = v18;\n v22 = v18 - 1;\n v18 = v17;\n v23 = sub_1200(j, v21);\n v19 += sub_1200(j, v22) + v23;\n if ( !v22 )\n break;\n v17 = v22;\n }\n v24 = v204;\n if ( v15 )\n {\n v205 = v19 + 1;\n v25 = v15;\n v26 = 0;\n while ( 1 )\n {\n v27 = v24;\n v28 = v24 - 1;\n v24 = v25;\n v29 = sub_1200(v25 - 1, v27);\n v26 += sub_1200(v25 - 1, v28) + v29;\n if ( !v28 )\n break;\n v25 = v28;\n }\n v16 = v15;\n v220 += v26 + v205 + 1;\n goto LABEL_16;\n }\n v31 = v232;\n v32 = v238;\n v30 = v19 + v220 + 2;\n }\n else\n {\n while ( 1 )\n {\n v220 += 2;\n if ( !v15 )\n break;\nLABEL_16:\n v13 = v196;\n v14 = v16 - 1;\n v196 = v16;\n v15 = v13 - 1;\n v16 = v13 - 1;\n if ( v14 )\n goto LABEL_8;\n }\n v30 = v220;\n v31 = v232;\n v32 = v238;\n }\n v33 = v30 + 1;\n if ( v32 )\n {\n v197 = v32;\n v34 = v31;\n v35 = v31 - 1;\n v233 = v33;\n v221 = 0;\n v36 = v31 - 1;\n v239 = v32;\n v37 = v32 - 1;\n if ( v32 == 1 )\n goto LABEL_30;\nLABEL_21:\n v38 = v37;\n v206 = v37;\n v39 = v34;\n v40 = 0;\n for ( k = v35; ; k = v43 - 1 )\n {\n v42 = v38;\n v43 = v38 - 1;\n v38 = v39;\n v44 = sub_1200(k, v42);\n v40 += sub_1200(k, v43) + v44;\n if ( !v43 )\n break;\n v39 = v43;\n }\n v45 = v206;\n if ( v35 )\n {\n v207 = v40 + 1;\n v46 = v35;\n v47 = 0;\n while ( 1 )\n {\n v48 = v45;\n v49 = v45 - 1;\n v45 = v46;\n v50 = sub_1200(v46 - 1, v48);\n v47 += sub_1200(v46 - 1, v49) + v50;\n if ( !v49 )\n break;\n v46 = v49;\n }\n v36 = v35;\n v221 += v47 + v207 + 1;\n do\n {\n v34 = v197;\n v197 = v36;\n v51 = v36;\n v35 = v34 - 1;\n v36 = v34 - 1;\n v37 = v51 - 1;\n if ( v37 )\n goto LABEL_21;\nLABEL_30:\n v221 += 2;\n }\n while ( v35 );\n v52 = v233;\n v53 = v221;\n v12 = v239;\n }\n else\n {\n v52 = v233;\n v12 = v239;\n v53 = v40 + v221 + 2;\n }\n v246 += v52 + v53 + 1;\n goto LABEL_33;\n }\n v55 = v252;\n v56 = v255;\n v54 = v30 + v246 + 2;\n }\n else\n {\n while ( 1 )\n {\n v246 += 2;\n if ( !v11 )\n break;\nLABEL_33:\n v9 = v228;\n v10 = v12 - 1;\n v228 = v12;\n v11 = v9 - 1;\n v12 = v9 - 1;\n if ( v10 )\n goto LABEL_7;\n }\n v54 = v246;\n v55 = v252;\n v56 = v255;\n }\n if ( v56 )\n {\n v253 = v54 + 1;\n v247 = 0;\n v229 = v56;\n v256 = v56;\n while ( 1 )\n {\n v57 = v55 - 1;\n if ( v229 == 1 )\n {\n v247 += 2;\n if ( v55 == 1 )\n {\n v97 = v253;\n v98 = v247;\n v8 = v256;\nLABEL_68:\n v259 += v97 + v98 + 1;\n goto LABEL_69;\n }\n }\n else\n {\n v58 = v229 - 1;\n v240 = v55 - 1;\n v59 = v229 - 2;\n v222 = 0;\n v198 = v55;\n v60 = v229 - 2;\n if ( v55 == 1 )\n {\n while ( 1 )\n {\n v222 += 2;\n if ( !v59 )\n break;\nLABEL_48:\n v58 = v198;\n v57 = v60 - 1;\n v198 = v60;\n v59 = v58 - 1;\n v60 = v58 - 1;\n if ( v57 )\n goto LABEL_40;\n }\n v74 = v222;\n v75 = v229 - 1;\n v76 = v240;\n }\n else\n {\nLABEL_40:\n v208 = v57;\n v61 = v58;\n v62 = v57;\n v63 = 0;\n for ( m = v59; ; m = v66 - 1 )\n {\n v65 = v62;\n v66 = v62 - 1;\n v62 = v61;\n v67 = sub_1200(m, v65);\n v63 += sub_1200(m, v66) + v67;\n if ( !v66 )\n break;\n v61 = v66;\n }\n v68 = v208;\n if ( v59 )\n {\n v209 = v63 + 1;\n v69 = v59;\n v70 = 0;\n while ( 1 )\n {\n v71 = v68;\n v72 = v68 - 1;\n v68 = v69;\n v73 = sub_1200(v69 - 1, v71);\n v70 += sub_1200(v69 - 1, v72) + v73;\n if ( !v72 )\n break;\n v69 = v72;\n }\n v60 = v59;\n v222 += v70 + v209 + 1;\n goto LABEL_48;\n }\n v75 = v229 - 1;\n v76 = v240;\n v74 = v63 + v222 + 2;\n }\n if ( !v76 )\n {\n v97 = v253;\n v8 = v256;\n v98 = v74 + v247 + 2;\n goto LABEL_68;\n }\n v199 = v76;\n v77 = v75;\n v234 = v74 + 1;\n v78 = v75 - 1;\n v223 = 0;\n v79 = v75 - 1;\n v241 = v76;\n v80 = v76 - 1;\n if ( v76 == 1 )\n {\n while ( 1 )\n {\n v223 += 2;\n if ( !v78 )\n break;\nLABEL_61:\n v77 = v199;\n v199 = v79;\n v94 = v79;\n v78 = v77 - 1;\n v79 = v77 - 1;\n v80 = v94 - 1;\n if ( v80 )\n goto LABEL_53;\n }\n v95 = v234;\n v96 = v223;\n v57 = v241;\n }\n else\n {\nLABEL_53:\n v81 = v80;\n v210 = v80;\n v82 = v77;\n v83 = 0;\n for ( n = v78; ; n = v86 - 1 )\n {\n v85 = v81;\n v86 = v81 - 1;\n v81 = v82;\n v87 = sub_1200(n, v85);\n v83 += sub_1200(n, v86) + v87;\n if ( !v86 )\n break;\n v82 = v86;\n }\n v88 = v210;\n if ( v78 )\n {\n v211 = v83 + 1;\n v89 = v78;\n v90 = 0;\n while ( 1 )\n {\n v91 = v88;\n v92 = v88 - 1;\n v88 = v89;\n v93 = sub_1200(v89 - 1, v91);\n v90 += sub_1200(v89 - 1, v92) + v93;\n if ( !v92 )\n break;\n v89 = v92;\n }\n v79 = v78;\n v223 += v90 + v211 + 1;\n goto LABEL_61;\n }\n v95 = v234;\n v57 = v241;\n v96 = v83 + v223 + 2;\n }\n v247 += v95 + v96 + 1;\n }\n v55 = v229;\n v229 = v57;\n }\n }\n v100 = i - 1;\n v101 = v264;\n v99 = v54 + v259 + 2;\n }\n if ( !v101 )\n {\n v195 = v99 + v262 + 2;\n return (unsigned int)(v195 + 1);\n }\n v251 = v101;\n v102 = v100;\n v263 = v99 + 1;\n v260 = 0;\n v265 = v101;\nLABEL_74:\n v103 = v102 - 1;\n if ( v251 != 1 )\n {\n v104 = v251 - 1;\n v230 = v102;\n v105 = v251 - 2;\n v248 = 0;\n v106 = v251 - 2;\n v257 = v102 - 1;\n if ( v102 == 1 )\n {\n while ( 1 )\n {\n v248 += 2;\n if ( !v105 )\n break;\nLABEL_102:\n v104 = v230;\n v103 = v106 - 1;\n v230 = v106;\n v105 = v104 - 1;\n v106 = v104 - 1;\n if ( v103 )\n goto LABEL_76;\n }\n v147 = v248;\n v148 = v251 - 1;\n v149 = v257;\n }\n else\n {\nLABEL_76:\n v107 = v103;\n v108 = v105;\n v242 = v105;\n v224 = 0;\n v109 = v103 - 1;\n v200 = v104;\n v110 = v103 - 1;\n v235 = v103;\n if ( v108 )\n {\nLABEL_77:\n v212 = v108;\n v111 = v107;\n v112 = v108;\n v113 = 0;\n for ( ii = v109; ; ii = v116 - 1 )\n {\n v115 = v112;\n v116 = v112 - 1;\n v112 = v111;\n v117 = sub_1200(ii, v115);\n v113 += sub_1200(ii, v116) + v117;\n if ( !v116 )\n break;\n v111 = v116;\n }\n v118 = v212;\n if ( v109 )\n {\n v213 = v113 + 1;\n v119 = v109;\n v120 = 0;\n while ( 1 )\n {\n v121 = v118;\n v122 = v118 - 1;\n v118 = v119;\n v123 = sub_1200(v119 - 1, v121);\n v120 += sub_1200(v119 - 1, v122) + v123;\n if ( !v122 )\n break;\n v119 = v122;\n }\n v110 = v109;\n v224 += v120 + v213 + 1;\n goto LABEL_85;\n }\n v125 = v235;\n v126 = v242;\n v124 = v113 + v224 + 2;\n }\n else\n {\n while ( 1 )\n {\n v224 += 2;\n if ( !v109 )\n break;\nLABEL_85:\n v107 = v200;\n v108 = v110 - 1;\n v200 = v110;\n v109 = v107 - 1;\n v110 = v107 - 1;\n if ( v108 )\n goto LABEL_77;\n }\n v124 = v224;\n v125 = v235;\n v126 = v242;\n }\n if ( v126 )\n {\n v201 = v126;\n v127 = v125;\n v236 = v124 + 1;\n v128 = v125 - 1;\n v225 = 0;\n v129 = v125 - 1;\n v243 = v126;\n v130 = v126 - 1;\n if ( v126 == 1 )\n goto LABEL_99;\nLABEL_90:\n v131 = v130;\n v214 = v130;\n v132 = v127;\n v133 = 0;\n for ( jj = v128; ; jj = v136 - 1 )\n {\n v135 = v131;\n v136 = v131 - 1;\n v131 = v132;\n v137 = sub_1200(jj, v135);\n v133 += sub_1200(jj, v136) + v137;\n if ( !v136 )\n break;\n v132 = v136;\n }\n v138 = v214;\n if ( v128 )\n {\n v215 = v133 + 1;\n v139 = v128;\n v140 = 0;\n while ( 1 )\n {\n v141 = v138;\n v142 = v138 - 1;\n v138 = v139;\n v143 = sub_1200(v139 - 1, v141);\n v140 += sub_1200(v139 - 1, v142) + v143;\n if ( !v142 )\n break;\n v139 = v142;\n }\n v129 = v128;\n v225 += v140 + v215 + 1;\n do\n {\n v127 = v201;\n v201 = v129;\n v144 = v129;\n v128 = v127 - 1;\n v129 = v127 - 1;\n v130 = v144 - 1;\n if ( v130 )\n goto LABEL_90;\nLABEL_99:\n v225 += 2;\n }\n while ( v128 );\n v145 = v236;\n v146 = v225;\n v106 = v243;\n }\n else\n {\n v145 = v236;\n v106 = v243;\n v146 = v133 + v225 + 2;\n }\n v248 += v145 + v146 + 1;\n goto LABEL_102;\n }\n v148 = v251 - 1;\n v149 = v257;\n v147 = v124 + v248 + 2;\n }\n if ( !v149 )\n {\n v193 = v263;\n v4 = v265;\n v194 = v147 + v260 + 2;\n goto LABEL_141;\n }\n v254 = v147 + 1;\n v249 = 0;\n v231 = v149;\n v258 = v149;\n while ( 1 )\n {\n v150 = v148 - 1;\n if ( v231 == 1 )\n {\n v249 += 2;\n if ( v148 == 1 )\n {\n v191 = v254;\n v192 = v249;\n v103 = v258;\n goto LABEL_137;\n }\n }\n else\n {\n v151 = v231 - 1;\n v244 = v148 - 1;\n v226 = 0;\n v152 = v231 - 2;\n v153 = v148 - 1;\n v202 = v148;\n v154 = v231 - 2;\n if ( v148 == 1 )\n {\n while ( 1 )\n {\n v226 += 2;\n if ( !v152 )\n break;\nLABEL_117:\n v151 = v202;\n v153 = v154 - 1;\n v202 = v154;\n v152 = v151 - 1;\n v154 = v151 - 1;\n if ( v153 )\n goto LABEL_109;\n }\n v168 = v226;\n v169 = v231 - 1;\n v170 = v244;\n }\n else\n {\nLABEL_109:\n v216 = v153;\n v155 = v151;\n v156 = v153;\n v157 = 0;\n for ( kk = v152; ; kk = v160 - 1 )\n {\n v159 = v156;\n v160 = v156 - 1;\n v156 = v155;\n v161 = sub_1200(kk, v159);\n v157 += sub_1200(kk, v160) + v161;\n if ( !v160 )\n break;\n v155 = v160;\n }\n v162 = v216;\n if ( v152 )\n {\n v217 = v157 + 1;\n v163 = v152;\n v164 = 0;\n while ( 1 )\n {\n v165 = v162;\n v166 = v162 - 1;\n v162 = v163;\n v167 = sub_1200(v163 - 1, v165);\n v164 += sub_1200(v163 - 1, v166) + v167;\n if ( !v166 )\n break;\n v163 = v166;\n }\n v154 = v152;\n v226 += v164 + v217 + 1;\n goto LABEL_117;\n }\n v169 = v231 - 1;\n v170 = v244;\n v168 = v157 + v226 + 2;\n }\n if ( !v170 )\n {\n v191 = v254;\n v103 = v258;\n v192 = v168 + v249 + 2;\nLABEL_137:\n v260 += v191 + v192 + 1;\nLABEL_138:\n v102 = v251;\n v251 = v103;\n goto LABEL_74;\n }\n v203 = v170;\n v171 = v169;\n v237 = v168 + 1;\n v172 = v169 - 1;\n v227 = 0;\n v173 = v169 - 1;\n v245 = v170;\n v174 = v170 - 1;\n if ( v170 == 1 )\n {\n while ( 1 )\n {\n v227 += 2;\n if ( !v172 )\n break;\nLABEL_130:\n v171 = v203;\n v203 = v173;\n v188 = v173;\n v172 = v171 - 1;\n v173 = v171 - 1;\n v174 = v188 - 1;\n if ( v174 )\n goto LABEL_122;\n }\n v189 = v237;\n v190 = v227;\n v150 = v245;\n }\n else\n {\nLABEL_122:\n v175 = v174;\n v218 = v174;\n v176 = v171;\n v177 = 0;\n for ( mm = v172; ; mm = v180 - 1 )\n {\n v179 = v175;\n v180 = v175 - 1;\n v175 = v176;\n v181 = sub_1200(mm, v179);\n v177 += sub_1200(mm, v180) + v181;\n if ( !v180 )\n break;\n v176 = v180;\n }\n v182 = v218;\n if ( v172 )\n {\n v219 = v177 + 1;\n v183 = v172;\n v184 = 0;\n while ( 1 )\n {\n v185 = v182;\n v186 = v182 - 1;\n v182 = v183;\n v187 = sub_1200(v183 - 1, v185);\n v184 += sub_1200(v183 - 1, v186) + v187;\n if ( !v186 )\n break;\n v183 = v186;\n }\n v173 = v172;\n v227 += v184 + v219 + 1;\n goto LABEL_130;\n }\n v189 = v237;\n v150 = v245;\n v190 = v177 + v227 + 2;\n }\n v249 += v189 + v190 + 1;\n }\n v148 = v231;\n v231 = v150;\n }\n }\n v260 += 2;\n if ( v102 != 1 )\n goto LABEL_138;\n v193 = v263;\n v194 = v260;\n v4 = v265;\nLABEL_141:\n v262 += v193 + v194 + 1;\nLABEL_142:\n v2 = i;\n }\n v262 += 2;\n if ( v2 != 1 )\n goto LABEL_142;\n v195 = v262;\n return (unsigned int)(v195 + 1);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1200(unsigned int a1, unsigned int a2) {\n unsigned int v2;\n long long result;\n unsigned int v4;\n unsigned int v5;\n unsigned int v6;\n unsigned int v7;\n unsigned int v8;\n unsigned int v9;\n unsigned int v10;\n unsigned int v11;\n unsigned int v12;\n unsigned int v13;\n unsigned int v14;\n unsigned int v15;\n unsigned int v16;\n unsigned int v17;\n unsigned int v18;\n int v19;\n unsigned int j;\n long long v21;\n unsigned int v22;\n int v23;\n unsigned int v24;\n unsigned int v25;\n int v26;\n long long v27;\n unsigned int v28;\n int v29;\n int v30;\n unsigned int v31;\n unsigned int v32;\n int v33;\n unsigned int v34;\n unsigned int v35;\n unsigned int v36;\n unsigned int v37;\n unsigned int v38;\n unsigned int v39;\n int v40;\n unsigned int k;\n long long v42;\n unsigned int v43;\n int v44;\n unsigned int v45;\n unsigned int v46;\n int v47;\n long long v48;\n unsigned int v49;\n int v50;\n unsigned int v51;\n int v52;\n int v53;\n int v54;\n unsigned int v55;\n unsigned int v56;\n unsigned int v57;\n unsigned int v58;\n unsigned int v59;\n unsigned int v60;\n unsigned int v61;\n unsigned int v62;\n int v63;\n unsigned int m;\n long long v65;\n unsigned int v66;\n int v67;\n unsigned int v68;\n unsigned int v69;\n int v70;\n long long v71;\n unsigned int v72;\n int v73;\n int v74;\n unsigned int v75;\n unsigned int v76;\n unsigned int v77;\n unsigned int v78;\n unsigned int v79;\n unsigned int v80;\n unsigned int v81;\n unsigned int v82;\n int v83;\n unsigned int n;\n long long v85;\n unsigned int v86;\n int v87;\n unsigned int v88;\n unsigned int v89;\n int v90;\n long long v91;\n unsigned int v92;\n int v93;\n unsigned int v94;\n int v95;\n int v96;\n int v97;\n int v98;\n int v99;\n unsigned int v100;\n unsigned int v101;\n unsigned int v102;\n unsigned int v103;\n unsigned int v104;\n unsigned int v105;\n unsigned int v106;\n unsigned int v107;\n unsigned int v108;\n unsigned int v109;\n unsigned int v110;\n unsigned int v111;\n unsigned int v112;\n int v113;\n unsigned int ii;\n long long v115;\n unsigned int v116;\n int v117;\n unsigned int v118;\n unsigned int v119;\n int v120;\n long long v121;\n unsigned int v122;\n int v123;\n int v124;\n unsigned int v125;\n unsigned int v126;\n unsigned int v127;\n unsigned int v128;\n unsigned int v129;\n unsigned int v130;\n unsigned int v131;\n unsigned int v132;\n int v133;\n unsigned int jj;\n long long v135;\n unsigned int v136;\n int v137;\n unsigned int v138;\n unsigned int v139;\n int v140;\n long long v141;\n unsigned int v142;\n int v143;\n unsigned int v144;\n int v145;\n int v146;\n int v147;\n unsigned int v148;\n unsigned int v149;\n unsigned int v150;\n unsigned int v151;\n unsigned int v152;\n unsigned int v153;\n unsigned int v154;\n unsigned int v155;\n unsigned int v156;\n int v157;\n unsigned int kk;\n long long v159;\n unsigned int v160;\n int v161;\n unsigned int v162;\n unsigned int v163;\n int v164;\n long long v165;\n unsigned int v166;\n int v167;\n int v168;\n unsigned int v169;\n unsigned int v170;\n unsigned int v171;\n unsigned int v172;\n unsigned int v173;\n unsigned int v174;\n unsigned int v175;\n unsigned int v176;\n int v177;\n unsigned int mm;\n long long v179;\n unsigned int v180;\n int v181;\n unsigned int v182;\n unsigned int v183;\n int v184;\n long long v185;\n unsigned int v186;\n int v187;\n unsigned int v188;\n int v189;\n int v190;\n int v191;\n int v192;\n int v193;\n int v194;\n int v195;\n unsigned int v196;\n unsigned int v197;\n unsigned int v198;\n unsigned int v199;\n unsigned int v200;\n unsigned int v201;\n unsigned int v202;\n unsigned int v203;\n unsigned int v204;\n int v205;\n unsigned int v206;\n int v207;\n unsigned int v208;\n int v209;\n unsigned int v210;\n int v211;\n unsigned int v212;\n int v213;\n unsigned int v214;\n int v215;\n unsigned int v216;\n int v217;\n unsigned int v218;\n int v219;\n int v220;\n int v221;\n int v222;\n int v223;\n int v224;\n int v225;\n int v226;\n int v227;\n unsigned int v228;\n unsigned int v229;\n unsigned int v230;\n unsigned int v231;\n unsigned int v232;\n int v233;\n int v234;\n unsigned int v235;\n int v236;\n int v237;\n unsigned int v238;\n unsigned int v239;\n unsigned int v240;\n unsigned int v241;\n unsigned int v242;\n unsigned int v243;\n unsigned int v244;\n unsigned int v245;\n int v246;\n int v247;\n int v248;\n int v249;\n unsigned int v250;\n unsigned int v251;\n unsigned int v252;\n int v253;\n int v254;\n unsigned int v255;\n unsigned int v256;\n unsigned int v257;\n unsigned int v258;\n int v259;\n int v260;\n unsigned int i;\n int v262;\n int v263;\n unsigned int v264;\n unsigned int v265;\n if (!a2) return 1LL;\n v2 = a1;\n result = 1LL;\n if (a1) {\n v262 = 0;\n for (i = a2;; i = v4) {\n v4 = v2 - 1;\n if (i == 1) break;\n v5 = i - 1;\n v6 = v2 - 1;\n v7 = i - 2;\n v259 = 0;\n v264 = v2 - 1;\n v8 = i - 2;\n v250 = v2;\n if (v2 == 1) {\n while (1) {\n v259 += 2;\n if (!v7) break;\n LABEL_69:\n v5 = v250;\n v250 = v8;\n v6 = v8 - 1;\n v7 = v5 - 1;\n v8 = v5 - 1;\n if (v6) goto LABEL_6;\n }\n v99 = v259;\n v100 = i - 1;\n v101 = v264;\n } else {\n LABEL_6:\n v9 = v6;\n v10 = v7;\n v228 = v5;\n v11 = v6 - 1;\n v246 = 0;\n v252 = v6;\n v12 = v6 - 1;\n v255 = v7;\n if (v7) {\n LABEL_7:\n v13 = v10;\n v14 = v11;\n v238 = v11;\n v220 = 0;\n v15 = v10 - 1;\n v196 = v9;\n v16 = v10 - 1;\n v232 = v10;\n if (v14) {\n LABEL_8:\n v204 = v14;\n v17 = v13;\n v18 = v14;\n v19 = 0;\n for (j = v15;; j = v22 - 1) {\n v21 = v18;\n v22 = v18 - 1;\n v18 = v17;\n v23 = sub_1200(j, v21);\n v19 += sub_1200(j, v22) + v23;\n if (!v22) break;\n v17 = v22;\n }\n v24 = v204;\n if (v15) {\n v205 = v19 + 1;\n v25 = v15;\n v26 = 0;\n while (1) {\n v27 = v24;\n v28 = v24 - 1;\n v24 = v25;\n v29 = sub_1200(v25 - 1, v27);\n v26 += sub_1200(v25 - 1, v28) + v29;\n if (!v28) break;\n v25 = v28;\n }\n v16 = v15;\n v220 += v26 + v205 + 1;\n goto LABEL_16;\n }\n v31 = v232;\n v32 = v238;\n v30 = v19 + v220 + 2;\n } else {\n while (1) {\n v220 += 2;\n if (!v15) break;\n LABEL_16:\n v13 = v196;\n v14 = v16 - 1;\n v196 = v16;\n v15 = v13 - 1;\n v16 = v13 - 1;\n if (v14) goto LABEL_8;\n }\n v30 = v220;\n v31 = v232;\n v32 = v238;\n }\n v33 = v30 + 1;\n if (v32) {\n v197 = v32;\n v34 = v31;\n v35 = v31 - 1;\n v233 = v33;\n v221 = 0;\n v36 = v31 - 1;\n v239 = v32;\n v37 = v32 - 1;\n if (v32 == 1) goto LABEL_30;\n LABEL_21:\n v38 = v37;\n v206 = v37;\n v39 = v34;\n v40 = 0;\n for (k = v35;; k = v43 - 1) {\n v42 = v38;\n v43 = v38 - 1;\n v38 = v39;\n v44 = sub_1200(k, v42);\n v40 += sub_1200(k, v43) + v44;\n if (!v43) break;\n v39 = v43;\n }\n v45 = v206;\n if (v35) {\n v207 = v40 + 1;\n v46 = v35;\n v47 = 0;\n while (1) {\n v48 = v45;\n v49 = v45 - 1;\n v45 = v46;\n v50 = sub_1200(v46 - 1, v48);\n v47 += sub_1200(v46 - 1, v49) + v50;\n if (!v49) break;\n v46 = v49;\n }\n v36 = v35;\n v221 += v47 + v207 + 1;\n do {\n v34 = v197;\n v197 = v36;\n v51 = v36;\n v35 = v34 - 1;\n v36 = v34 - 1;\n v37 = v51 - 1;\n if (v37) goto LABEL_21;\n LABEL_30:\n v221 += 2;\n } while (v35);\n v52 = v233;\n v53 = v221;\n v12 = v239;\n } else {\n v52 = v233;\n v12 = v239;\n v53 = v40 + v221 + 2;\n }\n v246 += v52 + v53 + 1;\n goto LABEL_33;\n }\n v55 = v252;\n v56 = v255;\n v54 = v30 + v246 + 2;\n } else {\n while (1) {\n v246 += 2;\n if (!v11) break;\n LABEL_33:\n v9 = v228;\n v10 = v12 - 1;\n v228 = v12;\n v11 = v9 - 1;\n v12 = v9 - 1;\n if (v10) goto LABEL_7;\n }\n v54 = v246;\n v55 = v252;\n v56 = v255;\n }\n if (v56) {\n v253 = v54 + 1;\n v247 = 0;\n v229 = v56;\n v256 = v56;\n while (1) {\n v57 = v55 - 1;\n if (v229 == 1) {\n v247 += 2;\n if (v55 == 1) {\n v97 = v253;\n v98 = v247;\n v8 = v256;\n LABEL_68:\n v259 += v97 + v98 + 1;\n goto LABEL_69;\n }\n } else {\n v58 = v229 - 1;\n v240 = v55 - 1;\n v59 = v229 - 2;\n v222 = 0;\n v198 = v55;\n v60 = v229 - 2;\n if (v55 == 1) {\n while (1) {\n v222 += 2;\n if (!v59) break;\n LABEL_48:\n v58 = v198;\n v57 = v60 - 1;\n v198 = v60;\n v59 = v58 - 1;\n v60 = v58 - 1;\n if (v57) goto LABEL_40;\n }\n v74 = v222;\n v75 = v229 - 1;\n v76 = v240;\n } else {\n LABEL_40:\n v208 = v57;\n v61 = v58;\n v62 = v57;\n v63 = 0;\n for (m = v59;; m = v66 - 1) {\n v65 = v62;\n v66 = v62 - 1;\n v62 = v61;\n v67 = sub_1200(m, v65);\n v63 += sub_1200(m, v66) + v67;\n if (!v66) break;\n v61 = v66;\n }\n v68 = v208;\n if (v59) {\n v209 = v63 + 1;\n v69 = v59;\n v70 = 0;\n while (1) {\n v71 = v68;\n v72 = v68 - 1;\n v68 = v69;\n v73 = sub_1200(v69 - 1, v71);\n v70 += sub_1200(v69 - 1, v72) + v73;\n if (!v72) break;\n v69 = v72;\n }\n v60 = v59;\n v222 += v70 + v209 + 1;\n goto LABEL_48;\n }\n v75 = v229 - 1;\n v76 = v240;\n v74 = v63 + v222 + 2;\n }\n if (!v76) {\n v97 = v253;\n v8 = v256;\n v98 = v74 + v247 + 2;\n goto LABEL_68;\n }\n v199 = v76;\n v77 = v75;\n v234 = v74 + 1;\n v78 = v75 - 1;\n v223 = 0;\n v79 = v75 - 1;\n v241 = v76;\n v80 = v76 - 1;\n if (v76 == 1) {\n while (1) {\n v223 += 2;\n if (!v78) break;\n LABEL_61:\n v77 = v199;\n v199 = v79;\n v94 = v79;\n v78 = v77 - 1;\n v79 = v77 - 1;\n v80 = v94 - 1;\n if (v80) goto LABEL_53;\n }\n v95 = v234;\n v96 = v223;\n v57 = v241;\n } else {\n LABEL_53:\n v81 = v80;\n v210 = v80;\n v82 = v77;\n v83 = 0;\n for (n = v78;; n = v86 - 1) {\n v85 = v81;\n v86 = v81 - 1;\n v81 = v82;\n v87 = sub_1200(n, v85);\n v83 += sub_1200(n, v86) + v87;\n if (!v86) break;\n v82 = v86;\n }\n v88 = v210;\n if (v78) {\n v211 = v83 + 1;\n v89 = v78;\n v90 = 0;\n while (1) {\n v91 = v88;\n v92 = v88 - 1;\n v88 = v89;\n v93 = sub_1200(v89 - 1, v91);\n v90 += sub_1200(v89 - 1, v92) + v93;\n if (!v92) break;\n v89 = v92;\n }\n v79 = v78;\n v223 += v90 + v211 + 1;\n goto LABEL_61;\n }\n v95 = v234;\n v57 = v241;\n v96 = v83 + v223 + 2;\n }\n v247 += v95 + v96 + 1;\n }\n v55 = v229;\n v229 = v57;\n }\n }\n v100 = i - 1;\n v101 = v264;\n v99 = v54 + v259 + 2;\n }\n if (!v101) {\n v195 = v99 + v262 + 2;\n return (unsigned int)(v195 + 1);\n }\n v251 = v101;\n v102 = v100;\n v263 = v99 + 1;\n v260 = 0;\n v265 = v101;\n LABEL_74:\n v103 = v102 - 1;\n if (v251 != 1) {\n v104 = v251 - 1;\n v230 = v102;\n v105 = v251 - 2;\n v248 = 0;\n v106 = v251 - 2;\n v257 = v102 - 1;\n if (v102 == 1) {\n while (1) {\n v248 += 2;\n if (!v105) break;\n LABEL_102:\n v104 = v230;\n v103 = v106 - 1;\n v230 = v106;\n v105 = v104 - 1;\n v106 = v104 - 1;\n if (v103) goto LABEL_76;\n }\n v147 = v248;\n v148 = v251 - 1;\n v149 = v257;\n } else {\n LABEL_76:\n v107 = v103;\n v108 = v105;\n v242 = v105;\n v224 = 0;\n v109 = v103 - 1;\n v200 = v104;\n v110 = v103 - 1;\n v235 = v103;\n if (v108) {\n LABEL_77:\n v212 = v108;\n v111 = v107;\n v112 = v108;\n v113 = 0;\n for (ii = v109;; ii = v116 - 1) {\n v115 = v112;\n v116 = v112 - 1;\n v112 = v111;\n v117 = sub_1200(ii, v115);\n v113 += sub_1200(ii, v116) + v117;\n if (!v116) break;\n v111 = v116;\n }\n v118 = v212;\n if (v109) {\n v213 = v113 + 1;\n v119 = v109;\n v120 = 0;\n while (1) {\n v121 = v118;\n v122 = v118 - 1;\n v118 = v119;\n v123 = sub_1200(v119 - 1, v121);\n v120 += sub_1200(v119 - 1, v122) + v123;\n if (!v122) break;\n v119 = v122;\n }\n v110 = v109;\n v224 += v120 + v213 + 1;\n goto LABEL_85;\n }\n v125 = v235;\n v126 = v242;\n v124 = v113 + v224 + 2;\n } else {\n while (1) {\n v224 += 2;\n if (!v109) break;\n LABEL_85:\n v107 = v200;\n v108 = v110 - 1;\n v200 = v110;\n v109 = v107 - 1;\n v110 = v107 - 1;\n if (v108) goto LABEL_77;\n }\n v124 = v224;\n v125 = v235;\n v126 = v242;\n }\n if (v126) {\n v201 = v126;\n v127 = v125;\n v236 = v124 + 1;\n v128 = v125 - 1;\n v225 = 0;\n v129 = v125 - 1;\n v243 = v126;\n v130 = v126 - 1;\n if (v126 == 1) goto LABEL_99;\n LABEL_90:\n v131 = v130;\n v214 = v130;\n v132 = v127;\n v133 = 0;\n for (jj = v128;; jj = v136 - 1) {\n v135 = v131;\n v136 = v131 - 1;\n v131 = v132;\n v137 = sub_1200(jj, v135);\n v133 += sub_1200(jj, v136) + v137;\n if (!v136) break;\n v132 = v136;\n }\n v138 = v214;\n if (v128) {\n v215 = v133 + 1;\n v139 = v128;\n v140 = 0;\n while (1) {\n v141 = v138;\n v142 = v138 - 1;\n v138 = v139;\n v143 = sub_1200(v139 - 1, v141);\n v140 += sub_1200(v139 - 1, v142) + v143;\n if (!v142) break;\n v139 = v142;\n }\n v129 = v128;\n v225 += v140 + v215 + 1;\n do {\n v127 = v201;\n v201 = v129;\n v144 = v129;\n v128 = v127 - 1;\n v129 = v127 - 1;\n v130 = v144 - 1;\n if (v130) goto LABEL_90;\n LABEL_99:\n v225 += 2;\n } while (v128);\n v145 = v236;\n v146 = v225;\n v106 = v243;\n } else {\n v145 = v236;\n v106 = v243;\n v146 = v133 + v225 + 2;\n }\n v248 += v145 + v146 + 1;\n goto LABEL_102;\n }\n v148 = v251 - 1;\n v149 = v257;\n v147 = v124 + v248 + 2;\n }\n if (!v149) {\n v193 = v263;\n v4 = v265;\n v194 = v147 + v260 + 2;\n goto LABEL_141;\n }\n v254 = v147 + 1;\n v249 = 0;\n v231 = v149;\n v258 = v149;\n while (1) {\n v150 = v148 - 1;\n if (v231 == 1) {\n v249 += 2;\n if (v148 == 1) {\n v191 = v254;\n v192 = v249;\n v103 = v258;\n goto LABEL_137;\n }\n } else {\n v151 = v231 - 1;\n v244 = v148 - 1;\n v226 = 0;\n v152 = v231 - 2;\n v153 = v148 - 1;\n v202 = v148;\n v154 = v231 - 2;\n if (v148 == 1) {\n while (1) {\n v226 += 2;\n if (!v152) break;\n LABEL_117:\n v151 = v202;\n v153 = v154 - 1;\n v202 = v154;\n v152 = v151 - 1;\n v154 = v151 - 1;\n if (v153) goto LABEL_109;\n }\n v168 = v226;\n v169 = v231 - 1;\n v170 = v244;\n } else {\n LABEL_109:\n v216 = v153;\n v155 = v151;\n v156 = v153;\n v157 = 0;\n for (kk = v152;; kk = v160 - 1) {\n v159 = v156;\n v160 = v156 - 1;\n v156 = v155;\n v161 = sub_1200(kk, v159);\n v157 += sub_1200(kk, v160) + v161;\n if (!v160) break;\n v155 = v160;\n }\n v162 = v216;\n if (v152) {\n v217 = v157 + 1;\n v163 = v152;\n v164 = 0;\n while (1) {\n v165 = v162;\n v166 = v162 - 1;\n v162 = v163;\n v167 = sub_1200(v163 - 1, v165);\n v164 += sub_1200(v163 - 1, v166) + v167;\n if (!v166) break;\n v163 = v166;\n }\n v154 = v152;\n v226 += v164 + v217 + 1;\n goto LABEL_117;\n }\n v169 = v231 - 1;\n v170 = v244;\n v168 = v157 + v226 + 2;\n }\n if (!v170) {\n v191 = v254;\n v103 = v258;\n v192 = v168 + v249 + 2;\n LABEL_137:\n v260 += v191 + v192 + 1;\n LABEL_138:\n v102 = v251;\n v251 = v103;\n goto LABEL_74;\n }\n v203 = v170;\n v171 = v169;\n v237 = v168 + 1;\n v172 = v169 - 1;\n v227 = 0;\n v173 = v169 - 1;\n v245 = v170;\n v174 = v170 - 1;\n if (v170 == 1) {\n while (1) {\n v227 += 2;\n if (!v172) break;\n LABEL_130:\n v171 = v203;\n v203 = v173;\n v188 = v173;\n v172 = v171 - 1;\n v173 = v171 - 1;\n v174 = v188 - 1;\n if (v174) goto LABEL_122;\n }\n v189 = v237;\n v190 = v227;\n v150 = v245;\n } else {\n LABEL_122:\n v175 = v174;\n v218 = v174;\n v176 = v171;\n v177 = 0;\n for (mm = v172;; mm = v180 - 1) {\n v179 = v175;\n v180 = v175 - 1;\n v175 = v176;\n v181 = sub_1200(mm, v179);\n v177 += sub_1200(mm, v180) + v181;\n if (!v180) break;\n v176 = v180;\n }\n v182 = v218;\n if (v172) {\n v219 = v177 + 1;\n v183 = v172;\n v184 = 0;\n while (1) {\n v185 = v182;\n v186 = v182 - 1;\n v182 = v183;\n v187 = sub_1200(v183 - 1, v185);\n v184 += sub_1200(v183 - 1, v186) + v187;\n if (!v186) break;\n v183 = v186;\n }\n v173 = v172;\n v227 += v184 + v219 + 1;\n goto LABEL_130;\n }\n v189 = v237;\n v150 = v245;\n v190 = v177 + v227 + 2;\n }\n v249 += v189 + v190 + 1;\n }\n v148 = v231;\n v231 = v150;\n }\n }\n v260 += 2;\n if (v102 != 1) goto LABEL_138;\n v193 = v263;\n v194 = v260;\n v4 = v265;\n LABEL_141:\n v262 += v193 + v194 + 1;\n LABEL_142:\n v2 = i;\n }\n v262 += 2;\n if (v2 != 1) goto LABEL_142;\n v195 = v262;\n return (unsigned int)(v195 + 1);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(unsigned int a1, unsigned int a2) {\n unsigned int v2;\n long long result;\n unsigned int v4;\n unsigned int v5;\n unsigned int v6;\n unsigned int v7;\n unsigned int v8;\n unsigned int v9;\n unsigned int v10;\n unsigned int v11;\n unsigned int v12;\n unsigned int v13;\n unsigned int v14;\n unsigned int v15;\n unsigned int v16;\n unsigned int v17;\n unsigned int v18;\n int v19;\n unsigned int j;\n long long v21;\n unsigned int v22;\n int v23;\n unsigned int v24;\n unsigned int v25;\n int v26;\n long long v27;\n unsigned int v28;\n int v29;\n int v30;\n unsigned int v31;\n unsigned int v32;\n int v33;\n unsigned int v34;\n unsigned int v35;\n unsigned int v36;\n unsigned int v37;\n unsigned int v38;\n unsigned int v39;\n int v40;\n unsigned int k;\n long long v42;\n unsigned int v43;\n int v44;\n unsigned int v45;\n unsigned int v46;\n int v47;\n long long v48;\n unsigned int v49;\n int v50;\n unsigned int v51;\n int v52;\n int v53;\n int v54;\n unsigned int v55;\n unsigned int v56;\n unsigned int v57;\n unsigned int v58;\n unsigned int v59;\n unsigned int v60;\n unsigned int v61;\n unsigned int v62;\n int v63;\n unsigned int m;\n long long v65;\n unsigned int v66;\n int v67;\n unsigned int v68;\n unsigned int v69;\n int v70;\n long long v71;\n unsigned int v72;\n int v73;\n int v74;\n unsigned int v75;\n unsigned int v76;\n unsigned int v77;\n unsigned int v78;\n unsigned int v79;\n unsigned int v80;\n unsigned int v81;\n unsigned int v82;\n int v83;\n unsigned int n;\n long long v85;\n unsigned int v86;\n int v87;\n unsigned int v88;\n unsigned int v89;\n int v90;\n long long v91;\n unsigned int v92;\n int v93;\n unsigned int v94;\n int v95;\n int v96;\n int v97;\n int v98;\n int v99;\n unsigned int v100;\n unsigned int v101;\n unsigned int v102;\n unsigned int v103;\n unsigned int v104;\n unsigned int v105;\n unsigned int v106;\n unsigned int v107;\n unsigned int v108;\n unsigned int v109;\n unsigned int v110;\n unsigned int v111;\n unsigned int v112;\n int v113;\n unsigned int ii;\n long long v115;\n unsigned int v116;\n int v117;\n unsigned int v118;\n unsigned int v119;\n int v120;\n long long v121;\n unsigned int v122;\n int v123;\n int v124;\n unsigned int v125;\n unsigned int v126;\n unsigned int v127;\n unsigned int v128;\n unsigned int v129;\n unsigned int v130;\n unsigned int v131;\n unsigned int v132;\n int v133;\n unsigned int jj;\n long long v135;\n unsigned int v136;\n int v137;\n unsigned int v138;\n unsigned int v139;\n int v140;\n long long v141;\n unsigned int v142;\n int v143;\n unsigned int v144;\n int v145;\n int v146;\n int v147;\n unsigned int v148;\n unsigned int v149;\n unsigned int v150;\n unsigned int v151;\n unsigned int v152;\n unsigned int v153;\n unsigned int v154;\n unsigned int v155;\n unsigned int v156;\n int v157;\n unsigned int kk;\n long long v159;\n unsigned int v160;\n int v161;\n unsigned int v162;\n unsigned int v163;\n int v164;\n long long v165;\n unsigned int v166;\n int v167;\n int v168;\n unsigned int v169;\n unsigned int v170;\n unsigned int v171;\n unsigned int v172;\n unsigned int v173;\n unsigned int v174;\n unsigned int v175;\n unsigned int v176;\n int v177;\n unsigned int mm;\n long long v179;\n unsigned int v180;\n int v181;\n unsigned int v182;\n unsigned int v183;\n int v184;\n long long v185;\n unsigned int v186;\n int v187;\n unsigned int v188;\n int v189;\n int v190;\n int v191;\n int v192;\n int v193;\n int v194;\n int v195;\n unsigned int v196;\n unsigned int v197;\n unsigned int v198;\n unsigned int v199;\n unsigned int v200;\n unsigned int v201;\n unsigned int v202;\n unsigned int v203;\n unsigned int v204;\n int v205;\n unsigned int v206;\n int v207;\n unsigned int v208;\n int v209;\n unsigned int v210;\n int v211;\n unsigned int v212;\n int v213;\n unsigned int v214;\n int v215;\n unsigned int v216;\n int v217;\n unsigned int v218;\n int v219;\n int v220;\n int v221;\n int v222;\n int v223;\n int v224;\n int v225;\n int v226;\n int v227;\n unsigned int v228;\n unsigned int v229;\n unsigned int v230;\n unsigned int v231;\n unsigned int v232;\n int v233;\n int v234;\n unsigned int v235;\n int v236;\n int v237;\n unsigned int v238;\n unsigned int v239;\n unsigned int v240;\n unsigned int v241;\n unsigned int v242;\n unsigned int v243;\n unsigned int v244;\n unsigned int v245;\n int v246;\n int v247;\n int v248;\n int v249;\n unsigned int v250;\n unsigned int v251;\n unsigned int v252;\n int v253;\n int v254;\n unsigned int v255;\n unsigned int v256;\n unsigned int v257;\n unsigned int v258;\n int v259;\n int v260;\n unsigned int i;\n int v262;\n int v263;\n unsigned int v264;\n unsigned int v265;\n if (!a2) return 1LL;\n v2 = a1;\n result = 1LL;\n if (a1) {\n v262 = 0;\n for (i = a2;; i = v4) {\n v4 = v2 - 1;\n if (i == 1) break;\n v5 = i - 1;\n v6 = v2 - 1;\n v7 = i - 2;\n v259 = 0;\n v264 = v2 - 1;\n v8 = i - 2;\n v250 = v2;\n if (v2 == 1) {\n while (1) {\n v259 += 2;\n if (!v7) break;\n LABEL_69:\n v5 = v250;\n v250 = v8;\n v6 = v8 - 1;\n v7 = v5 - 1;\n v8 = v5 - 1;\n if (v6) goto LABEL_6;\n }\n v99 = v259;\n v100 = i - 1;\n v101 = v264;\n } else {\n LABEL_6:\n v9 = v6;\n v10 = v7;\n v228 = v5;\n v11 = v6 - 1;\n v246 = 0;\n v252 = v6;\n v12 = v6 - 1;\n v255 = v7;\n if (v7) {\n LABEL_7:\n v13 = v10;\n v14 = v11;\n v238 = v11;\n v220 = 0;\n v15 = v10 - 1;\n v196 = v9;\n v16 = v10 - 1;\n v232 = v10;\n if (v14) {\n LABEL_8:\n v204 = v14;\n v17 = v13;\n v18 = v14;\n v19 = 0;\n for (j = v15;; j = v22 - 1) {\n v21 = v18;\n v22 = v18 - 1;\n v18 = v17;\n v23 = func0(j, v21);\n v19 += func0(j, v22) + v23;\n if (!v22) break;\n v17 = v22;\n }\n v24 = v204;\n if (v15) {\n v205 = v19 + 1;\n v25 = v15;\n v26 = 0;\n while (1) {\n v27 = v24;\n v28 = v24 - 1;\n v24 = v25;\n v29 = func0(v25 - 1, v27);\n v26 += func0(v25 - 1, v28) + v29;\n if (!v28) break;\n v25 = v28;\n }\n v16 = v15;\n v220 += v26 + v205 + 1;\n goto LABEL_16;\n }\n v31 = v232;\n v32 = v238;\n v30 = v19 + v220 + 2;\n } else {\n while (1) {\n v220 += 2;\n if (!v15) break;\n LABEL_16:\n v13 = v196;\n v14 = v16 - 1;\n v196 = v16;\n v15 = v13 - 1;\n v16 = v13 - 1;\n if (v14) goto LABEL_8;\n }\n v30 = v220;\n v31 = v232;\n v32 = v238;\n }\n v33 = v30 + 1;\n if (v32) {\n v197 = v32;\n v34 = v31;\n v35 = v31 - 1;\n v233 = v33;\n v221 = 0;\n v36 = v31 - 1;\n v239 = v32;\n v37 = v32 - 1;\n if (v32 == 1) goto LABEL_30;\n LABEL_21:\n v38 = v37;\n v206 = v37;\n v39 = v34;\n v40 = 0;\n for (k = v35;; k = v43 - 1) {\n v42 = v38;\n v43 = v38 - 1;\n v38 = v39;\n v44 = func0(k, v42);\n v40 += func0(k, v43) + v44;\n if (!v43) break;\n v39 = v43;\n }\n v45 = v206;\n if (v35) {\n v207 = v40 + 1;\n v46 = v35;\n v47 = 0;\n while (1) {\n v48 = v45;\n v49 = v45 - 1;\n v45 = v46;\n v50 = func0(v46 - 1, v48);\n v47 += func0(v46 - 1, v49) + v50;\n if (!v49) break;\n v46 = v49;\n }\n v36 = v35;\n v221 += v47 + v207 + 1;\n do {\n v34 = v197;\n v197 = v36;\n v51 = v36;\n v35 = v34 - 1;\n v36 = v34 - 1;\n v37 = v51 - 1;\n if (v37) goto LABEL_21;\n LABEL_30:\n v221 += 2;\n } while (v35);\n v52 = v233;\n v53 = v221;\n v12 = v239;\n } else {\n v52 = v233;\n v12 = v239;\n v53 = v40 + v221 + 2;\n }\n v246 += v52 + v53 + 1;\n goto LABEL_33;\n }\n v55 = v252;\n v56 = v255;\n v54 = v30 + v246 + 2;\n } else {\n while (1) {\n v246 += 2;\n if (!v11) break;\n LABEL_33:\n v9 = v228;\n v10 = v12 - 1;\n v228 = v12;\n v11 = v9 - 1;\n v12 = v9 - 1;\n if (v10) goto LABEL_7;\n }\n v54 = v246;\n v55 = v252;\n v56 = v255;\n }\n if (v56) {\n v253 = v54 + 1;\n v247 = 0;\n v229 = v56;\n v256 = v56;\n while (1) {\n v57 = v55 - 1;\n if (v229 == 1) {\n v247 += 2;\n if (v55 == 1) {\n v97 = v253;\n v98 = v247;\n v8 = v256;\n LABEL_68:\n v259 += v97 + v98 + 1;\n goto LABEL_69;\n }\n } else {\n v58 = v229 - 1;\n v240 = v55 - 1;\n v59 = v229 - 2;\n v222 = 0;\n v198 = v55;\n v60 = v229 - 2;\n if (v55 == 1) {\n while (1) {\n v222 += 2;\n if (!v59) break;\n LABEL_48:\n v58 = v198;\n v57 = v60 - 1;\n v198 = v60;\n v59 = v58 - 1;\n v60 = v58 - 1;\n if (v57) goto LABEL_40;\n }\n v74 = v222;\n v75 = v229 - 1;\n v76 = v240;\n } else {\n LABEL_40:\n v208 = v57;\n v61 = v58;\n v62 = v57;\n v63 = 0;\n for (m = v59;; m = v66 - 1) {\n v65 = v62;\n v66 = v62 - 1;\n v62 = v61;\n v67 = func0(m, v65);\n v63 += func0(m, v66) + v67;\n if (!v66) break;\n v61 = v66;\n }\n v68 = v208;\n if (v59) {\n v209 = v63 + 1;\n v69 = v59;\n v70 = 0;\n while (1) {\n v71 = v68;\n v72 = v68 - 1;\n v68 = v69;\n v73 = func0(v69 - 1, v71);\n v70 += func0(v69 - 1, v72) + v73;\n if (!v72) break;\n v69 = v72;\n }\n v60 = v59;\n v222 += v70 + v209 + 1;\n goto LABEL_48;\n }\n v75 = v229 - 1;\n v76 = v240;\n v74 = v63 + v222 + 2;\n }\n if (!v76) {\n v97 = v253;\n v8 = v256;\n v98 = v74 + v247 + 2;\n goto LABEL_68;\n }\n v199 = v76;\n v77 = v75;\n v234 = v74 + 1;\n v78 = v75 - 1;\n v223 = 0;\n v79 = v75 - 1;\n v241 = v76;\n v80 = v76 - 1;\n if (v76 == 1) {\n while (1) {\n v223 += 2;\n if (!v78) break;\n LABEL_61:\n v77 = v199;\n v199 = v79;\n v94 = v79;\n v78 = v77 - 1;\n v79 = v77 - 1;\n v80 = v94 - 1;\n if (v80) goto LABEL_53;\n }\n v95 = v234;\n v96 = v223;\n v57 = v241;\n } else {\n LABEL_53:\n v81 = v80;\n v210 = v80;\n v82 = v77;\n v83 = 0;\n for (n = v78;; n = v86 - 1) {\n v85 = v81;\n v86 = v81 - 1;\n v81 = v82;\n v87 = func0(n, v85);\n v83 += func0(n, v86) + v87;\n if (!v86) break;\n v82 = v86;\n }\n v88 = v210;\n if (v78) {\n v211 = v83 + 1;\n v89 = v78;\n v90 = 0;\n while (1) {\n v91 = v88;\n v92 = v88 - 1;\n v88 = v89;\n v93 = func0(v89 - 1, v91);\n v90 += func0(v89 - 1, v92) + v93;\n if (!v92) break;\n v89 = v92;\n }\n v79 = v78;\n v223 += v90 + v211 + 1;\n goto LABEL_61;\n }\n v95 = v234;\n v57 = v241;\n v96 = v83 + v223 + 2;\n }\n v247 += v95 + v96 + 1;\n }\n v55 = v229;\n v229 = v57;\n }\n }\n v100 = i - 1;\n v101 = v264;\n v99 = v54 + v259 + 2;\n }\n if (!v101) {\n v195 = v99 + v262 + 2;\n return (unsigned int)(v195 + 1);\n }\n v251 = v101;\n v102 = v100;\n v263 = v99 + 1;\n v260 = 0;\n v265 = v101;\n LABEL_74:\n v103 = v102 - 1;\n if (v251 != 1) {\n v104 = v251 - 1;\n v230 = v102;\n v105 = v251 - 2;\n v248 = 0;\n v106 = v251 - 2;\n v257 = v102 - 1;\n if (v102 == 1) {\n while (1) {\n v248 += 2;\n if (!v105) break;\n LABEL_102:\n v104 = v230;\n v103 = v106 - 1;\n v230 = v106;\n v105 = v104 - 1;\n v106 = v104 - 1;\n if (v103) goto LABEL_76;\n }\n v147 = v248;\n v148 = v251 - 1;\n v149 = v257;\n } else {\n LABEL_76:\n v107 = v103;\n v108 = v105;\n v242 = v105;\n v224 = 0;\n v109 = v103 - 1;\n v200 = v104;\n v110 = v103 - 1;\n v235 = v103;\n if (v108) {\n LABEL_77:\n v212 = v108;\n v111 = v107;\n v112 = v108;\n v113 = 0;\n for (ii = v109;; ii = v116 - 1) {\n v115 = v112;\n v116 = v112 - 1;\n v112 = v111;\n v117 = func0(ii, v115);\n v113 += func0(ii, v116) + v117;\n if (!v116) break;\n v111 = v116;\n }\n v118 = v212;\n if (v109) {\n v213 = v113 + 1;\n v119 = v109;\n v120 = 0;\n while (1) {\n v121 = v118;\n v122 = v118 - 1;\n v118 = v119;\n v123 = func0(v119 - 1, v121);\n v120 += func0(v119 - 1, v122) + v123;\n if (!v122) break;\n v119 = v122;\n }\n v110 = v109;\n v224 += v120 + v213 + 1;\n goto LABEL_85;\n }\n v125 = v235;\n v126 = v242;\n v124 = v113 + v224 + 2;\n } else {\n while (1) {\n v224 += 2;\n if (!v109) break;\n LABEL_85:\n v107 = v200;\n v108 = v110 - 1;\n v200 = v110;\n v109 = v107 - 1;\n v110 = v107 - 1;\n if (v108) goto LABEL_77;\n }\n v124 = v224;\n v125 = v235;\n v126 = v242;\n }\n if (v126) {\n v201 = v126;\n v127 = v125;\n v236 = v124 + 1;\n v128 = v125 - 1;\n v225 = 0;\n v129 = v125 - 1;\n v243 = v126;\n v130 = v126 - 1;\n if (v126 == 1) goto LABEL_99;\n LABEL_90:\n v131 = v130;\n v214 = v130;\n v132 = v127;\n v133 = 0;\n for (jj = v128;; jj = v136 - 1) {\n v135 = v131;\n v136 = v131 - 1;\n v131 = v132;\n v137 = func0(jj, v135);\n v133 += func0(jj, v136) + v137;\n if (!v136) break;\n v132 = v136;\n }\n v138 = v214;\n if (v128) {\n v215 = v133 + 1;\n v139 = v128;\n v140 = 0;\n while (1) {\n v141 = v138;\n v142 = v138 - 1;\n v138 = v139;\n v143 = func0(v139 - 1, v141);\n v140 += func0(v139 - 1, v142) + v143;\n if (!v142) break;\n v139 = v142;\n }\n v129 = v128;\n v225 += v140 + v215 + 1;\n do {\n v127 = v201;\n v201 = v129;\n v144 = v129;\n v128 = v127 - 1;\n v129 = v127 - 1;\n v130 = v144 - 1;\n if (v130) goto LABEL_90;\n LABEL_99:\n v225 += 2;\n } while (v128);\n v145 = v236;\n v146 = v225;\n v106 = v243;\n } else {\n v145 = v236;\n v106 = v243;\n v146 = v133 + v225 + 2;\n }\n v248 += v145 + v146 + 1;\n goto LABEL_102;\n }\n v148 = v251 - 1;\n v149 = v257;\n v147 = v124 + v248 + 2;\n }\n if (!v149) {\n v193 = v263;\n v4 = v265;\n v194 = v147 + v260 + 2;\n goto LABEL_141;\n }\n v254 = v147 + 1;\n v249 = 0;\n v231 = v149;\n v258 = v149;\n while (1) {\n v150 = v148 - 1;\n if (v231 == 1) {\n v249 += 2;\n if (v148 == 1) {\n v191 = v254;\n v192 = v249;\n v103 = v258;\n goto LABEL_137;\n }\n } else {\n v151 = v231 - 1;\n v244 = v148 - 1;\n v226 = 0;\n v152 = v231 - 2;\n v153 = v148 - 1;\n v202 = v148;\n v154 = v231 - 2;\n if (v148 == 1) {\n while (1) {\n v226 += 2;\n if (!v152) break;\n LABEL_117:\n v151 = v202;\n v153 = v154 - 1;\n v202 = v154;\n v152 = v151 - 1;\n v154 = v151 - 1;\n if (v153) goto LABEL_109;\n }\n v168 = v226;\n v169 = v231 - 1;\n v170 = v244;\n } else {\n LABEL_109:\n v216 = v153;\n v155 = v151;\n v156 = v153;\n v157 = 0;\n for (kk = v152;; kk = v160 - 1) {\n v159 = v156;\n v160 = v156 - 1;\n v156 = v155;\n v161 = func0(kk, v159);\n v157 += func0(kk, v160) + v161;\n if (!v160) break;\n v155 = v160;\n }\n v162 = v216;\n if (v152) {\n v217 = v157 + 1;\n v163 = v152;\n v164 = 0;\n while (1) {\n v165 = v162;\n v166 = v162 - 1;\n v162 = v163;\n v167 = func0(v163 - 1, v165);\n v164 += func0(v163 - 1, v166) + v167;\n if (!v166) break;\n v163 = v166;\n }\n v154 = v152;\n v226 += v164 + v217 + 1;\n goto LABEL_117;\n }\n v169 = v231 - 1;\n v170 = v244;\n v168 = v157 + v226 + 2;\n }\n if (!v170) {\n v191 = v254;\n v103 = v258;\n v192 = v168 + v249 + 2;\n LABEL_137:\n v260 += v191 + v192 + 1;\n LABEL_138:\n v102 = v251;\n v251 = v103;\n goto LABEL_74;\n }\n v203 = v170;\n v171 = v169;\n v237 = v168 + 1;\n v172 = v169 - 1;\n v227 = 0;\n v173 = v169 - 1;\n v245 = v170;\n v174 = v170 - 1;\n if (v170 == 1) {\n while (1) {\n v227 += 2;\n if (!v172) break;\n LABEL_130:\n v171 = v203;\n v203 = v173;\n v188 = v173;\n v172 = v171 - 1;\n v173 = v171 - 1;\n v174 = v188 - 1;\n if (v174) goto LABEL_122;\n }\n v189 = v237;\n v190 = v227;\n v150 = v245;\n } else {\n LABEL_122:\n v175 = v174;\n v218 = v174;\n v176 = v171;\n v177 = 0;\n for (mm = v172;; mm = v180 - 1) {\n v179 = v175;\n v180 = v175 - 1;\n v175 = v176;\n v181 = func0(mm, v179);\n v177 += func0(mm, v180) + v181;\n if (!v180) break;\n v176 = v180;\n }\n v182 = v218;\n if (v172) {\n v219 = v177 + 1;\n v183 = v172;\n v184 = 0;\n while (1) {\n v185 = v182;\n v186 = v182 - 1;\n v182 = v183;\n v187 = func0(v183 - 1, v185);\n v184 += func0(v183 - 1, v186) + v187;\n if (!v186) break;\n v183 = v186;\n }\n v173 = v172;\n v227 += v184 + v219 + 1;\n goto LABEL_130;\n }\n v189 = v237;\n v150 = v245;\n v190 = v177 + v227 + 2;\n }\n v249 += v189 + v190 + 1;\n }\n v148 = v231;\n v231 = v150;\n }\n }\n v260 += 2;\n if (v102 != 1) goto LABEL_138;\n v193 = v263;\n v194 = v260;\n v4 = v265;\n LABEL_141:\n v262 += v193 + v194 + 1;\n LABEL_142:\n v2 = i;\n }\n v262 += 2;\n if (v2 != 1) goto LABEL_142;\n v195 = v262;\n return (unsigned int)(v195 + 1);\n }\n return result;\n}" + }, + { + "index": 934, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n, int m) {\n if (m == 0 || n == 0) {\n return 1;\n }\n return func0(m - 1, n) + func0(m - 1, n - 1) + func0(m, n - 1);\n}", + "test": "int main() {\n\n assert(func0(3, 4) == 129);\n\n assert(func0(3, 3) == 63);\n\n assert(func0(4, 5) == 681);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\nje 1278 \npush %r15\nmov $0x1,%eax\npush %r14\nxor %r14d,%r14d\npush %r13\npush %r12\nmov %esi,%r12d\npush %rbp\nmov %edi,%ebp\npush %rbx\nsub $0x8,%rsp\ntest %edi,%edi\nje 1264 \nlea -0x1(%r12),%r15d\nmov %ebp,%esi\nlea -0x1(%rbp),%r13d\nmov %r12d,%ebp\nmov %r15d,%edi\ncallq 1200 \nmov %r13d,%esi\nmov %r15d,%edi\nmov %eax,%ebx\ncallq 1200 \nadd %eax,%ebx\nadd %ebx,%r14d\ntest %r13d,%r13d\nje 1260 \nmov %r13d,%r12d\njmp 1227 \nnopl 0x0(%rax)\nlea 0x1(%r14),%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax,%rax,1)\nmov $0x1,%eax\nretq\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njz loc_1D9F\npush r15\nmov ecx, edi\nmov eax, 1\npush r14\npush r13\npush r12\nxor r12d, r12d\npush rbp\npush rbx\nsub rsp, 48h\ntest edi, edi\njz loc_1D90\nlea eax, [rcx-1]\nmov r9d, esi\nmov [rsp+78h+var_44], r12d\nmov [rsp+78h+var_48], esi\nmov r14d, eax\nsub r9d, 1\njz loc_1D7D\nloc_1248:\nmov esi, r9d\nmov ebp, eax\nmov [rsp+78h+var_40], r9d\nxor r15d, r15d\nmov r9d, ebp\nlea r14d, [rsi-1]\nmov [rsp+78h+var_4C], r15d\nmov [rsp+78h+var_3C], eax\nmov ebp, r14d\nmov [rsp+78h+var_58], ecx\ntest r9d, r9d\njz loc_17B4\nloc_1275:\nmov r8d, r9d\nxor r13d, r13d\nmov edx, r14d\nmov [rsp+78h+var_68], esi\nlea eax, [r8-1]\nmov [rsp+78h+var_54], r9d\nmov [rsp+78h+var_5C], r13d\nmov r15d, eax\nmov [rsp+78h+var_50], r14d\ntest edx, edx\njz loc_14F4\nloc_12A0:\nxor edi, edi\nmov r12d, edx\nmov esi, eax\nmov [rsp+78h+var_60], eax\nmov [rsp+78h+var_6C], edi\nlea edi, [r12-1]\nmov [rsp+78h+var_78], r8d\nmov eax, edi\nmov [rsp+78h+var_64], edx\ntest esi, esi\njz loc_1395\nloc_12C6:\nmov [rsp+78h+var_74], esi\nxor r13d, r13d\nmov r14d, r12d\nmov ebp, esi\nmov [rsp+78h+var_70], edi\nmov r12d, r13d\nmov r13d, edi\nloc_12DC:\nmov esi, ebp\nmov edi, r13d\nlea r15d, [rbp-1]\nmov ebp, r14d\ncall func0\nmov esi, r15d\nmov edi, r13d\nmov ebx, eax\ncall func0\nadd ebx, eax\nadd r12d, ebx\ntest r15d, r15d\njz short loc_1310\nmov r14d, r15d\nlea r13d, [r15-1]\njmp short loc_12DC\nloc_1310:\nmov eax, [rsp+78h+var_70]\nmov r14d, [rsp+78h+var_74]\nlea ebx, [r12+1]\ntest eax, eax\njz loc_1EE2\nmov [rsp+78h+var_74], ebx\nmov r13d, eax\nmov ebx, r15d\nloc_1330:\nlea r15d, [r13-1]\nmov esi, r14d\nlea r12d, [r14-1]\nmov r14d, r13d\nmov edi, r15d\ncall func0\nmov esi, r12d\nmov edi, r15d\nmov ebp, eax\ncall func0\nadd ebp, eax\nadd ebx, ebp\ntest r12d, r12d\njz short loc_1368\nmov r13d, r12d\njmp short loc_1330\nloc_1368:\nmov r15d, ebx\nmov ebx, [rsp+78h+var_74]\nmov eax, [rsp+78h+var_70]\nlea edx, [r15+rbx+1]\nadd [rsp+78h+var_6C], edx\nloc_137C:\nmov r12d, [rsp+78h+var_78]\nlea esi, [rax-1]\nmov [rsp+78h+var_78], eax\nlea edi, [r12-1]\nmov eax, edi\ntest esi, esi\njnz loc_12C6\nloc_1395:\nadd [rsp+78h+var_6C], 2\ntest edi, edi\njnz short loc_137C\nmov r9d, [rsp+78h+var_64]\nmov edi, [rsp+78h+var_6C]\nmov r15d, [rsp+78h+var_60]\nloc_13AC:\nlea r14d, [rdi+1]\ntest r15d, r15d\njz loc_1ECA\nmov r12d, r9d\nmov [rsp+78h+var_64], r14d\nxor esi, esi\nmov r14d, r15d\nlea edi, [r12-1]\nmov [rsp+78h+var_78], r15d\nmov [rsp+78h+var_6C], esi\nmov eax, edi\nmov [rsp+78h+var_60], r15d\nsub r14d, 1\njz loc_14B7\nloc_13E4:\nmov [rsp+78h+var_70], edi\nxor r13d, r13d\nmov ebp, r14d\nmov [rsp+78h+var_74], r14d\nmov r14d, r12d\nmov r12d, r13d\nmov r13d, edi\nloc_13FC:\nmov esi, ebp\nmov edi, r13d\nlea r15d, [rbp-1]\nmov ebp, r14d\ncall func0\nmov esi, r15d\nmov edi, r13d\nmov ebx, eax\ncall func0\nadd ebx, eax\nadd r12d, ebx\ntest r15d, r15d\njz short loc_1430\nmov r14d, r15d\nlea r13d, [r15-1]\njmp short loc_13FC\nloc_1430:\nmov eax, [rsp+78h+var_70]\nmov r14d, [rsp+78h+var_74]\nlea ebx, [r12+1]\ntest eax, eax\njz loc_1EB2\nmov [rsp+78h+var_74], ebx\nmov r13d, eax\nmov ebx, r15d\nloc_1450:\nlea r15d, [r13-1]\nmov esi, r14d\nlea r12d, [r14-1]\nmov r14d, r13d\nmov edi, r15d\ncall func0\nmov esi, r12d\nmov edi, r15d\nmov ebp, eax\ncall func0\nadd ebp, eax\nadd ebx, ebp\ntest r12d, r12d\njz short loc_1488\nmov r13d, r12d\njmp short loc_1450\nloc_1488:\nmov r15d, ebx\nmov ebx, [rsp+78h+var_74]\nmov eax, [rsp+78h+var_70]\nlea edx, [r15+rbx+1]\nadd [rsp+78h+var_6C], edx\nloc_149C:\nmov r12d, [rsp+78h+var_78]\nmov r14d, eax\nmov [rsp+78h+var_78], eax\nlea edi, [r12-1]\nmov eax, edi\nsub r14d, 1\njnz loc_13E4\nloc_14B7:\nadd [rsp+78h+var_6C], 2\ntest edi, edi\njnz short loc_149C\nmov r14d, [rsp+78h+var_64]\nmov esi, [rsp+78h+var_6C]\nmov r15d, [rsp+78h+var_60]\nloc_14CE:\nlea eax, [r14+rsi+1]\nadd [rsp+78h+var_5C], eax\nloc_14D7:\nmov r8d, [rsp+78h+var_68]\nlea edx, [r15-1]\nmov [rsp+78h+var_68], r15d\nlea eax, [r8-1]\nmov r15d, eax\ntest edx, edx\njnz loc_12A0\nloc_14F4:\nadd [rsp+78h+var_5C], 2\ntest eax, eax\njnz short loc_14D7\nmov r9d, [rsp+78h+var_54]\nmov r13d, [rsp+78h+var_5C]\nmov ebp, [rsp+78h+var_50]\nloc_150B:\nlea ebx, [r13+1]\ntest ebp, ebp\njz loc_1E99\nxor r13d, r13d\nlea eax, [r9-1]\nmov r10d, ebp\nmov [rsp+78h+var_54], ebx\nmov [rsp+78h+var_68], ebp\nmov ecx, eax\nmov [rsp+78h+var_5C], r13d\nmov [rsp+78h+var_50], ebp\nsub r10d, 1\njz loc_1777\nloc_153E:\nmov ebp, r10d\nxor edx, edx\nmov [rsp+78h+var_60], eax\nlea edi, [rbp-1]\nmov [rsp+78h+var_78], r9d\nmov [rsp+78h+var_64], r10d\nmov eax, edi\nmov [rsp+78h+var_6C], edx\ntest ecx, ecx\njz loc_162A\nloc_1561:\nmov [rsp+78h+var_74], ecx\nxor r12d, r12d\nmov r15d, ebp\nmov r14d, ecx\nmov [rsp+78h+var_70], edi\nmov ebp, r12d\nmov r12d, edi\nloc_1578:\nmov esi, r14d\nmov edi, r12d\nlea r13d, [r14-1]\nmov r14d, r15d\ncall func0\nmov esi, r13d\nmov edi, r12d\nmov ebx, eax\ncall func0\nadd ebx, eax\nadd ebp, ebx\ntest r13d, r13d\njz short loc_15B0\nmov r15d, r13d\nlea r12d, [r13-1]\njmp short loc_1578\nloc_15B0:\nmov eax, [rsp+78h+var_70]\nmov r15d, [rsp+78h+var_74]\nlea ebx, [rbp+1]\ntest eax, eax\njz loc_1E83\nmov [rsp+78h+var_74], ebx\nmov r14d, eax\nmov ebx, r13d\nloc_15CE:\nlea r13d, [r14-1]\nmov esi, r15d\nlea r12d, [r15-1]\nmov r15d, r14d\nmov edi, r13d\ncall func0\nmov esi, r12d\nmov edi, r13d\nmov ebp, eax\ncall func0\nadd ebp, eax\nadd ebx, ebp\ntest r12d, r12d\njz short loc_1600\nmov r14d, r12d\njmp short loc_15CE\nloc_1600:\nmov r13d, ebx\nmov ebx, [rsp+78h+var_74]\nmov eax, [rsp+78h+var_70]\nlea edx, [r13+rbx+1]\nadd [rsp+78h+var_6C], edx\nloc_1614:\nmov ebp, [rsp+78h+var_78]\nlea ecx, [rax-1]\nmov [rsp+78h+var_78], eax\nlea edi, [rbp-1]\nmov eax, edi\ntest ecx, ecx\njnz loc_1561\nloc_162A:\nadd [rsp+78h+var_6C], 2\ntest edi, edi\njnz short loc_1614\nmov r10d, [rsp+78h+var_64]\nmov edx, [rsp+78h+var_6C]\nmov ecx, [rsp+78h+var_60]\nloc_1640:\nlea r14d, [rdx+1]\ntest ecx, ecx\njz loc_1E6C\nmov ebp, r10d\nmov [rsp+78h+var_64], r14d\nxor esi, esi\nmov r14d, ecx\nlea edi, [rbp-1]\nmov [rsp+78h+var_78], ecx\nmov [rsp+78h+var_6C], esi\nmov eax, edi\nmov [rsp+78h+var_60], ecx\nsub r14d, 1\njz loc_173C\nloc_1673:\nmov [rsp+78h+var_70], edi\nxor r12d, r12d\nmov r15d, r14d\nmov [rsp+78h+var_74], r14d\nmov r14d, ebp\nmov ebp, r12d\nmov r12d, edi\nloc_168B:\nmov esi, r15d\nmov edi, r12d\nlea r13d, [r15-1]\nmov r15d, r14d\ncall func0\nmov esi, r13d\nmov edi, r12d\nmov ebx, eax\ncall func0\nadd ebx, eax\nadd ebp, ebx\ntest r13d, r13d\njz short loc_16C0\nmov r14d, r13d\nlea r12d, [r13-1]\njmp short loc_168B\nloc_16C0:\nmov eax, [rsp+78h+var_70]\nmov r14d, [rsp+78h+var_74]\nlea ebx, [rbp+1]\ntest eax, eax\njz loc_1E56\nmov [rsp+78h+var_74], ebx\nmov r15d, eax\nmov ebx, r13d\nloc_16DE:\nlea r13d, [r15-1]\nmov esi, r14d\nlea r12d, [r14-1]\nmov r14d, r15d\nmov edi, r13d\ncall func0\nmov esi, r12d\nmov edi, r13d\nmov ebp, eax\ncall func0\nadd ebp, eax\nadd ebx, ebp\ntest r12d, r12d\njz short loc_1710\nmov r15d, r12d\njmp short loc_16DE\nloc_1710:\nmov r13d, ebx\nmov ebx, [rsp+78h+var_74]\nmov eax, [rsp+78h+var_70]\nlea edx, [r13+rbx+1]\nadd [rsp+78h+var_6C], edx\nloc_1724:\nmov ebp, [rsp+78h+var_78]\nmov r14d, eax\nmov [rsp+78h+var_78], eax\nlea edi, [rbp-1]\nmov eax, edi\nsub r14d, 1\njnz loc_1673\nloc_173C:\nadd [rsp+78h+var_6C], 2\ntest edi, edi\njnz short loc_1724\nmov r14d, [rsp+78h+var_64]\nmov esi, [rsp+78h+var_6C]\nmov ecx, [rsp+78h+var_60]\nloc_1752:\nlea eax, [r14+rsi+1]\nadd [rsp+78h+var_5C], eax\nloc_175B:\nmov r9d, [rsp+78h+var_68]\nmov r10d, ecx\nmov [rsp+78h+var_68], ecx\nlea eax, [r9-1]\nmov ecx, eax\nsub r10d, 1\njnz loc_153E\nloc_1777:\nadd [rsp+78h+var_5C], 2\ntest eax, eax\njnz short loc_175B\nmov ebx, [rsp+78h+var_54]\nmov r13d, [rsp+78h+var_5C]\nmov ebp, [rsp+78h+var_50]\nloc_178D:\nlea eax, [rbx+r13+1]\nadd [rsp+78h+var_4C], eax\nloc_1796:\nmov esi, [rsp+78h+var_58]\nmov [rsp+78h+var_58], ebp\nlea ebp, [rbp-1]\nmov r9d, ebp\nlea r14d, [rsi-1]\nmov ebp, r14d\ntest r9d, r9d\njnz loc_1275\nloc_17B4:\nadd [rsp+78h+var_4C], 2\ntest r14d, r14d\njnz short loc_1796\nmov r9d, [rsp+78h+var_40]\nmov r15d, [rsp+78h+var_4C]\nmov r14d, [rsp+78h+var_3C]\nloc_17CD:\nlea ebx, [r15+1]\ntest r14d, r14d\njz loc_1E47\nmov esi, r9d\nxor ecx, ecx\nmov r9d, r14d\nmov [rsp+78h+var_58], r14d\nlea r13d, [rsi-1]\nmov [rsp+78h+var_40], ebx\nmov [rsp+78h+var_4C], ecx\nmov edx, r13d\nmov [rsp+78h+var_3C], r14d\nsub r9d, 1\njz loc_1D42\nloc_1805:\nmov r8d, r9d\nxor r12d, r12d\nmov [rsp+78h+var_68], esi\nlea eax, [r8-1]\nmov [rsp+78h+var_54], r9d\nmov [rsp+78h+var_5C], r12d\nmov r15d, eax\nmov [rsp+78h+var_50], r13d\ntest edx, edx\njz loc_1A84\nloc_182D:\nxor edi, edi\nmov r12d, edx\nmov esi, eax\nmov [rsp+78h+var_60], eax\nmov [rsp+78h+var_6C], edi\nlea edi, [r12-1]\nmov [rsp+78h+var_78], r8d\nmov eax, edi\nmov [rsp+78h+var_64], edx\ntest esi, esi\njz loc_1925\nloc_1853:\nmov [rsp+78h+var_74], esi\nxor r14d, r14d\nmov r13d, r12d\nmov ebp, esi\nmov [rsp+78h+var_70], edi\nmov r12d, r14d\nmov r14d, edi\nloc_1869:\nmov esi, ebp\nmov edi, r14d\nlea r15d, [rbp-1]\nmov ebp, r13d\ncall func0\nmov esi, r15d\nmov edi, r14d\nmov ebx, eax\ncall func0\nadd ebx, eax\nadd r12d, ebx\ntest r15d, r15d\njz short loc_18A0\nmov r13d, r15d\nlea r14d, [r15-1]\njmp short loc_1869\nloc_18A0:\nmov eax, [rsp+78h+var_70]\nmov r13d, [rsp+78h+var_74]\nlea ebx, [r12+1]\ntest eax, eax\njz loc_1E2F\nmov [rsp+78h+var_74], ebx\nmov r14d, eax\nmov ebx, r15d\nloc_18C0:\nlea r15d, [r14-1]\nmov esi, r13d\nlea r12d, [r13-1]\nmov r13d, r14d\nmov edi, r15d\ncall func0\nmov esi, r12d\nmov edi, r15d\nmov ebp, eax\ncall func0\nadd ebp, eax\nadd ebx, ebp\ntest r12d, r12d\njz short loc_18F8\nmov r14d, r12d\njmp short loc_18C0\nloc_18F8:\nmov r15d, ebx\nmov ebx, [rsp+78h+var_74]\nmov eax, [rsp+78h+var_70]\nlea edx, [r15+rbx+1]\nadd [rsp+78h+var_6C], edx\nloc_190C:\nmov r12d, [rsp+78h+var_78]\nlea esi, [rax-1]\nmov [rsp+78h+var_78], eax\nlea edi, [r12-1]\nmov eax, edi\ntest esi, esi\njnz loc_1853\nloc_1925:\nadd [rsp+78h+var_6C], 2\ntest edi, edi\njnz short loc_190C\nmov r9d, [rsp+78h+var_64]\nmov edi, [rsp+78h+var_6C]\nmov r15d, [rsp+78h+var_60]\nloc_193C:\nlea r13d, [rdi+1]\ntest r15d, r15d\njz loc_1E17\nmov r12d, r9d\nmov [rsp+78h+var_64], r13d\nxor esi, esi\nmov r13d, r15d\nlea edi, [r12-1]\nmov [rsp+78h+var_78], r15d\nmov [rsp+78h+var_6C], esi\nmov eax, edi\nmov [rsp+78h+var_60], r15d\nsub r13d, 1\njz loc_1A47\nloc_1974:\nmov [rsp+78h+var_70], edi\nxor r14d, r14d\nmov ebp, r13d\nmov [rsp+78h+var_74], r13d\nmov r13d, r12d\nmov r12d, r14d\nmov r14d, edi\nloc_198C:\nmov esi, ebp\nmov edi, r14d\nlea r15d, [rbp-1]\nmov ebp, r13d\ncall func0\nmov esi, r15d\nmov edi, r14d\nmov ebx, eax\ncall func0\nadd ebx, eax\nadd r12d, ebx\ntest r15d, r15d\njz short loc_19C0\nmov r13d, r15d\nlea r14d, [r15-1]\njmp short loc_198C\nloc_19C0:\nmov eax, [rsp+78h+var_70]\nmov r13d, [rsp+78h+var_74]\nlea ebx, [r12+1]\ntest eax, eax\njz loc_1DFF\nmov [rsp+78h+var_74], ebx\nmov r14d, eax\nmov ebx, r15d\nloc_19E0:\nlea r15d, [r14-1]\nmov esi, r13d\nlea r12d, [r13-1]\nmov r13d, r14d\nmov edi, r15d\ncall func0\nmov esi, r12d\nmov edi, r15d\nmov ebp, eax\ncall func0\nadd ebp, eax\nadd ebx, ebp\ntest r12d, r12d\njz short loc_1A18\nmov r14d, r12d\njmp short loc_19E0\nloc_1A18:\nmov r15d, ebx\nmov ebx, [rsp+78h+var_74]\nmov eax, [rsp+78h+var_70]\nlea edx, [r15+rbx+1]\nadd [rsp+78h+var_6C], edx\nloc_1A2C:\nmov r12d, [rsp+78h+var_78]\nmov r13d, eax\nmov [rsp+78h+var_78], eax\nlea edi, [r12-1]\nmov eax, edi\nsub r13d, 1\njnz loc_1974\nloc_1A47:\nadd [rsp+78h+var_6C], 2\ntest edi, edi\njnz short loc_1A2C\nmov r13d, [rsp+78h+var_64]\nmov esi, [rsp+78h+var_6C]\nmov r15d, [rsp+78h+var_60]\nloc_1A5E:\nlea eax, [r13+rsi+1]\nadd [rsp+78h+var_5C], eax\nloc_1A67:\nmov r8d, [rsp+78h+var_68]\nlea edx, [r15-1]\nmov [rsp+78h+var_68], r15d\nlea eax, [r8-1]\nmov r15d, eax\ntest edx, edx\njnz loc_182D\nloc_1A84:\nadd [rsp+78h+var_5C], 2\ntest eax, eax\njnz short loc_1A67\nmov r9d, [rsp+78h+var_54]\nmov r12d, [rsp+78h+var_5C]\nmov edx, [rsp+78h+var_50]\nloc_1A9B:\nlea ebp, [r12+1]\ntest edx, edx\njz loc_1DE8\nxor r13d, r13d\nmov r8d, edx\nlea eax, [r9-1]\nmov [rsp+78h+var_68], edx\nmov [rsp+78h+var_50], edx\nmov edx, eax\nmov [rsp+78h+var_54], ebp\nmov [rsp+78h+var_5C], r13d\nsub r8d, 1\njz loc_1D07\nloc_1ACF:\nxor esi, esi\nmov ebp, r8d\nmov [rsp+78h+var_60], eax\nmov [rsp+78h+var_6C], esi\nlea edi, [rbp-1]\nmov esi, eax\nmov [rsp+78h+var_78], r9d\nmov eax, edi\nmov [rsp+78h+var_64], r8d\ntest esi, esi\njz loc_1BBA\nloc_1AF4:\nmov [rsp+78h+var_74], esi\nxor r12d, r12d\nmov r15d, ebp\nmov r14d, esi\nmov [rsp+78h+var_70], edi\nmov ebp, r12d\nmov r12d, edi\nloc_1B0B:\nmov esi, r14d\nmov edi, r12d\nlea r13d, [r14-1]\nmov r14d, r15d\ncall func0\nmov esi, r13d\nmov edi, r12d\nmov ebx, eax\ncall func0\nadd ebx, eax\nadd ebp, ebx\ntest r13d, r13d\njz short loc_1B40\nmov r15d, r13d\nlea r12d, [r13-1]\njmp short loc_1B0B\nloc_1B40:\nmov eax, [rsp+78h+var_70]\nmov r15d, [rsp+78h+var_74]\nlea ebx, [rbp+1]\ntest eax, eax\njz loc_1DD2\nmov [rsp+78h+var_74], ebx\nmov r14d, eax\nmov ebx, r13d\nloc_1B5E:\nlea r13d, [r14-1]\nmov esi, r15d\nlea r12d, [r15-1]\nmov r15d, r14d\nmov edi, r13d\ncall func0\nmov esi, r12d\nmov edi, r13d\nmov ebp, eax\ncall func0\nadd ebp, eax\nadd ebx, ebp\ntest r12d, r12d\njz short loc_1B90\nmov r14d, r12d\njmp short loc_1B5E\nloc_1B90:\nmov r13d, ebx\nmov ebx, [rsp+78h+var_74]\nmov eax, [rsp+78h+var_70]\nlea edx, [r13+rbx+1]\nadd [rsp+78h+var_6C], edx\nloc_1BA4:\nmov ebp, [rsp+78h+var_78]\nlea esi, [rax-1]\nmov [rsp+78h+var_78], eax\nlea edi, [rbp-1]\nmov eax, edi\ntest esi, esi\njnz loc_1AF4\nloc_1BBA:\nadd [rsp+78h+var_6C], 2\ntest edi, edi\njnz short loc_1BA4\nmov r8d, [rsp+78h+var_64]\nmov esi, [rsp+78h+var_6C]\nmov edx, [rsp+78h+var_60]\nloc_1BD0:\nlea r14d, [rsi+1]\ntest edx, edx\njz loc_1DBB\nmov ebp, r8d\nmov [rsp+78h+var_64], r14d\nxor esi, esi\nmov r14d, edx\nlea edi, [rbp-1]\nmov [rsp+78h+var_78], edx\nmov [rsp+78h+var_6C], esi\nmov eax, edi\nmov [rsp+78h+var_60], edx\nsub r14d, 1\njz loc_1CCC\nloc_1C03:\nmov [rsp+78h+var_70], edi\nxor r12d, r12d\nmov r15d, r14d\nmov [rsp+78h+var_74], r14d\nmov r14d, ebp\nmov ebp, r12d\nmov r12d, edi\nloc_1C1B:\nmov esi, r15d\nmov edi, r12d\nlea r13d, [r15-1]\nmov r15d, r14d\ncall func0\nmov esi, r13d\nmov edi, r12d\nmov ebx, eax\ncall func0\nadd ebx, eax\nadd ebp, ebx\ntest r13d, r13d\njz short loc_1C50\nmov r14d, r13d\nlea r12d, [r13-1]\njmp short loc_1C1B\nloc_1C50:\nmov eax, [rsp+78h+var_70]\nmov r14d, [rsp+78h+var_74]\nlea ebx, [rbp+1]\ntest eax, eax\njz loc_1DA5\nmov [rsp+78h+var_74], ebx\nmov r15d, eax\nmov ebx, r13d\nloc_1C6E:\nlea r13d, [r15-1]\nmov esi, r14d\nlea r12d, [r14-1]\nmov r14d, r15d\nmov edi, r13d\ncall func0\nmov esi, r12d\nmov edi, r13d\nmov ebp, eax\ncall func0\nadd ebp, eax\nadd ebx, ebp\ntest r12d, r12d\njz short loc_1CA0\nmov r15d, r12d\njmp short loc_1C6E\nloc_1CA0:\nmov r13d, ebx\nmov ebx, [rsp+78h+var_74]\nmov eax, [rsp+78h+var_70]\nlea edx, [r13+rbx+1]\nadd [rsp+78h+var_6C], edx\nloc_1CB4:\nmov ebp, [rsp+78h+var_78]\nmov r14d, eax\nmov [rsp+78h+var_78], eax\nlea edi, [rbp-1]\nmov eax, edi\nsub r14d, 1\njnz loc_1C03\nloc_1CCC:\nadd [rsp+78h+var_6C], 2\ntest edi, edi\njnz short loc_1CB4\nmov r14d, [rsp+78h+var_64]\nmov esi, [rsp+78h+var_6C]\nmov edx, [rsp+78h+var_60]\nloc_1CE2:\nlea eax, [r14+rsi+1]\nadd [rsp+78h+var_5C], eax\nloc_1CEB:\nmov r9d, [rsp+78h+var_68]\nmov r8d, edx\nmov [rsp+78h+var_68], edx\nlea eax, [r9-1]\nmov edx, eax\nsub r8d, 1\njnz loc_1ACF\nloc_1D07:\nadd [rsp+78h+var_5C], 2\ntest eax, eax\njnz short loc_1CEB\nmov ebp, [rsp+78h+var_54]\nmov r13d, [rsp+78h+var_5C]\nmov edx, [rsp+78h+var_50]\nloc_1D1D:\nlea eax, [rbp+r13+1]\nadd [rsp+78h+var_4C], eax\nloc_1D26:\nmov esi, [rsp+78h+var_58]\nmov r9d, edx\nmov [rsp+78h+var_58], edx\nlea r13d, [rsi-1]\nmov edx, r13d\nsub r9d, 1\njnz loc_1805\nloc_1D42:\nadd [rsp+78h+var_4C], 2\ntest r13d, r13d\njnz short loc_1D26\nmov ebx, [rsp+78h+var_40]\nmov ecx, [rsp+78h+var_4C]\nmov r14d, [rsp+78h+var_3C]\nloc_1D59:\nlea eax, [rbx+rcx+1]\nadd [rsp+78h+var_44], eax\nloc_1D61:\nmov ecx, [rsp+78h+var_48]\nmov r9d, r14d\nmov [rsp+78h+var_48], r14d\nlea eax, [rcx-1]\nmov r14d, eax\nsub r9d, 1\njnz loc_1248\nloc_1D7D:\nadd [rsp+78h+var_44], 2\ntest eax, eax\njnz short loc_1D61\nmov r12d, [rsp+78h+var_44]\nloc_1D8B:\nlea eax, [r12+1]\nloc_1D90:\nadd rsp, 48h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1D9F:\nmov eax, 1\nretn\nloc_1DA5:\nmov esi, [rsp+78h+var_6C]\nmov r14d, [rsp+78h+var_64]\nmov edx, [rsp+78h+var_60]\nlea esi, [rbp+rsi+2]\njmp loc_1CE2\nloc_1DBB:\nmov r13d, [rsp+78h+var_5C]\nmov ebp, [rsp+78h+var_54]\nmov edx, [rsp+78h+var_50]\nlea r13d, [r13+rsi+2]\njmp loc_1D1D\nloc_1DD2:\nmov esi, [rsp+78h+var_6C]\nmov r8d, [rsp+78h+var_64]\nmov edx, [rsp+78h+var_60]\nlea esi, [rbp+rsi+2]\njmp loc_1BD0\nloc_1DE8:\nmov ecx, [rsp+78h+var_4C]\nmov ebx, [rsp+78h+var_40]\nmov r14d, [rsp+78h+var_3C]\nlea ecx, [rcx+r12+2]\njmp loc_1D59\nloc_1DFF:\nmov esi, [rsp+78h+var_6C]\nmov r13d, [rsp+78h+var_64]\nmov r15d, [rsp+78h+var_60]\nlea esi, [r12+rsi+2]\njmp loc_1A5E\nloc_1E17:\nmov r12d, [rsp+78h+var_5C]\nmov r9d, [rsp+78h+var_54]\nmov edx, [rsp+78h+var_50]\nlea r12d, [r12+rdi+2]\njmp loc_1A9B\nloc_1E2F:\nmov edi, [rsp+78h+var_6C]\nmov r9d, [rsp+78h+var_64]\nmov r15d, [rsp+78h+var_60]\nlea edi, [r12+rdi+2]\njmp loc_193C\nloc_1E47:\nmov r12d, [rsp+78h+var_44]\nlea r12d, [r12+r15+2]\njmp loc_1D8B\nloc_1E56:\nmov esi, [rsp+78h+var_6C]\nmov r14d, [rsp+78h+var_64]\nmov ecx, [rsp+78h+var_60]\nlea esi, [rbp+rsi+2]\njmp loc_1752\nloc_1E6C:\nmov r13d, [rsp+78h+var_5C]\nmov ebx, [rsp+78h+var_54]\nmov ebp, [rsp+78h+var_50]\nlea r13d, [r13+rdx+2]\njmp loc_178D\nloc_1E83:\nmov edx, [rsp+78h+var_6C]\nmov r10d, [rsp+78h+var_64]\nmov ecx, [rsp+78h+var_60]\nlea edx, [rbp+rdx+2]\njmp loc_1640\nloc_1E99:\nmov r15d, [rsp+78h+var_4C]\nmov r9d, [rsp+78h+var_40]\nmov r14d, [rsp+78h+var_3C]\nlea r15d, [r15+r13+2]\njmp loc_17CD\nloc_1EB2:\nmov esi, [rsp+78h+var_6C]\nmov r14d, [rsp+78h+var_64]\nmov r15d, [rsp+78h+var_60]\nlea esi, [r12+rsi+2]\njmp loc_14CE\nloc_1ECA:\nmov r13d, [rsp+78h+var_5C]\nmov r9d, [rsp+78h+var_54]\nmov ebp, [rsp+78h+var_50]\nlea r13d, [r13+rdi+2]\njmp loc_150B\nloc_1EE2:\nmov edi, [rsp+78h+var_6C]\nmov r9d, [rsp+78h+var_64]\nmov r15d, [rsp+78h+var_60]\nlea edi, [r12+rdi+2]\njmp loc_13AC", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1, unsigned int a2)\n{\n unsigned int v2; // ecx\n __int64 result; // rax\n unsigned int v4; // eax\n unsigned int v5; // r14d\n unsigned int v6; // r9d\n unsigned int v7; // esi\n unsigned int v8; // r9d\n unsigned int v9; // r14d\n unsigned int v10; // ebp\n unsigned int v11; // r8d\n unsigned int v12; // edx\n unsigned int v13; // eax\n unsigned int v14; // r15d\n unsigned int v15; // r12d\n unsigned int v16; // esi\n unsigned int v17; // edi\n unsigned int v18; // eax\n unsigned int v19; // r14d\n unsigned int v20; // ebp\n int v21; // r12d\n unsigned int i; // r13d\n __int64 v23; // rsi\n unsigned int v24; // r15d\n int v25; // ebx\n unsigned int v26; // r14d\n unsigned int v27; // r13d\n int v28; // ebx\n __int64 v29; // rsi\n unsigned int v30; // r12d\n int v31; // ebp\n unsigned int v32; // r9d\n int v33; // edi\n unsigned int v34; // r15d\n unsigned int v35; // r12d\n unsigned int v36; // edi\n unsigned int v37; // eax\n unsigned int v38; // r14d\n unsigned int v39; // ebp\n unsigned int v40; // r14d\n int v41; // r12d\n unsigned int j; // r13d\n __int64 v43; // rsi\n unsigned int v44; // r15d\n int v45; // ebx\n unsigned int v46; // r14d\n unsigned int v47; // r13d\n int v48; // ebx\n __int64 v49; // rsi\n unsigned int v50; // r12d\n int v51; // ebp\n unsigned int v52; // r14d\n int v53; // r14d\n int v54; // esi\n unsigned int v55; // r9d\n int v56; // r13d\n unsigned int v57; // ebp\n unsigned int v58; // eax\n unsigned int v59; // ecx\n unsigned int v60; // r10d\n unsigned int v61; // ebp\n unsigned int v62; // edi\n unsigned int v63; // eax\n unsigned int v64; // r15d\n unsigned int v65; // r14d\n int v66; // ebp\n unsigned int k; // r12d\n __int64 v68; // rsi\n unsigned int v69; // r13d\n int v70; // ebx\n unsigned int v71; // r15d\n unsigned int v72; // r14d\n int v73; // ebx\n __int64 v74; // rsi\n unsigned int v75; // r12d\n int v76; // ebp\n unsigned int v77; // r10d\n int v78; // edx\n unsigned int v79; // ecx\n unsigned int v80; // ebp\n unsigned int v81; // edi\n unsigned int v82; // eax\n unsigned int v83; // r14d\n unsigned int v84; // r15d\n unsigned int v85; // r14d\n int v86; // ebp\n unsigned int m; // r12d\n __int64 v88; // rsi\n unsigned int v89; // r13d\n int v90; // ebx\n unsigned int v91; // r14d\n unsigned int v92; // r15d\n int v93; // ebx\n __int64 v94; // rsi\n unsigned int v95; // r12d\n int v96; // ebp\n unsigned int v97; // r14d\n int v98; // r14d\n int v99; // esi\n unsigned int v100; // r10d\n int v101; // ebx\n int v102; // r13d\n unsigned int v103; // r9d\n int v104; // r15d\n unsigned int v105; // r14d\n unsigned int v106; // esi\n unsigned int v107; // r13d\n unsigned int v108; // edx\n unsigned int v109; // r9d\n unsigned int v110; // r8d\n unsigned int v111; // eax\n unsigned int v112; // r15d\n unsigned int v113; // r12d\n unsigned int v114; // esi\n unsigned int v115; // edi\n unsigned int v116; // eax\n unsigned int v117; // r13d\n unsigned int v118; // ebp\n int v119; // r12d\n unsigned int n; // r14d\n __int64 v121; // rsi\n unsigned int v122; // r15d\n int v123; // ebx\n unsigned int v124; // r13d\n unsigned int v125; // r14d\n int v126; // ebx\n __int64 v127; // rsi\n unsigned int v128; // r12d\n int v129; // ebp\n unsigned int v130; // r9d\n int v131; // edi\n unsigned int v132; // r15d\n unsigned int v133; // r12d\n unsigned int v134; // edi\n unsigned int v135; // eax\n unsigned int v136; // r13d\n unsigned int v137; // ebp\n unsigned int v138; // r13d\n int v139; // r12d\n unsigned int ii; // r14d\n __int64 v141; // rsi\n unsigned int v142; // r15d\n int v143; // ebx\n unsigned int v144; // r13d\n unsigned int v145; // r14d\n int v146; // ebx\n __int64 v147; // rsi\n unsigned int v148; // r12d\n int v149; // ebp\n unsigned int v150; // r13d\n int v151; // r13d\n int v152; // esi\n unsigned int v153; // r9d\n int v154; // r12d\n unsigned int v155; // edx\n unsigned int v156; // r8d\n unsigned int v157; // eax\n unsigned int v158; // edx\n unsigned int v159; // r8d\n unsigned int v160; // ebp\n unsigned int v161; // edi\n unsigned int v162; // esi\n unsigned int v163; // eax\n unsigned int v164; // r15d\n unsigned int v165; // r14d\n int v166; // ebp\n unsigned int jj; // r12d\n __int64 v168; // rsi\n unsigned int v169; // r13d\n int v170; // ebx\n unsigned int v171; // r15d\n unsigned int v172; // r14d\n int v173; // ebx\n __int64 v174; // rsi\n unsigned int v175; // r12d\n int v176; // ebp\n unsigned int v177; // r8d\n int v178; // esi\n unsigned int v179; // edx\n unsigned int v180; // ebp\n unsigned int v181; // edi\n unsigned int v182; // eax\n unsigned int v183; // r14d\n unsigned int v184; // r15d\n unsigned int v185; // r14d\n int v186; // ebp\n unsigned int kk; // r12d\n __int64 v188; // rsi\n unsigned int v189; // r13d\n int v190; // ebx\n unsigned int v191; // r14d\n unsigned int v192; // r15d\n int v193; // ebx\n __int64 v194; // rsi\n unsigned int v195; // r12d\n int v196; // ebp\n unsigned int v197; // r14d\n int v198; // r14d\n int v199; // esi\n unsigned int v200; // r8d\n int v201; // ebp\n int v202; // r13d\n unsigned int v203; // r9d\n int v204; // ebx\n int v205; // ecx\n unsigned int v206; // r9d\n int v207; // r12d\n unsigned int v208; // [rsp+0h] [rbp-78h]\n unsigned int v209; // [rsp+0h] [rbp-78h]\n unsigned int v210; // [rsp+0h] [rbp-78h]\n unsigned int v211; // [rsp+0h] [rbp-78h]\n unsigned int v212; // [rsp+0h] [rbp-78h]\n unsigned int v213; // [rsp+0h] [rbp-78h]\n unsigned int v214; // [rsp+0h] [rbp-78h]\n unsigned int v215; // [rsp+0h] [rbp-78h]\n unsigned int v216; // [rsp+4h] [rbp-74h]\n int v217; // [rsp+4h] [rbp-74h]\n unsigned int v218; // [rsp+4h] [rbp-74h]\n int v219; // [rsp+4h] [rbp-74h]\n unsigned int v220; // [rsp+4h] [rbp-74h]\n int v221; // [rsp+4h] [rbp-74h]\n unsigned int v222; // [rsp+4h] [rbp-74h]\n int v223; // [rsp+4h] [rbp-74h]\n unsigned int v224; // [rsp+4h] [rbp-74h]\n int v225; // [rsp+4h] [rbp-74h]\n unsigned int v226; // [rsp+4h] [rbp-74h]\n int v227; // [rsp+4h] [rbp-74h]\n unsigned int v228; // [rsp+4h] [rbp-74h]\n int v229; // [rsp+4h] [rbp-74h]\n unsigned int v230; // [rsp+4h] [rbp-74h]\n int v231; // [rsp+4h] [rbp-74h]\n int v232; // [rsp+Ch] [rbp-6Ch]\n int v233; // [rsp+Ch] [rbp-6Ch]\n int v234; // [rsp+Ch] [rbp-6Ch]\n int v235; // [rsp+Ch] [rbp-6Ch]\n int v236; // [rsp+Ch] [rbp-6Ch]\n int v237; // [rsp+Ch] [rbp-6Ch]\n int v238; // [rsp+Ch] [rbp-6Ch]\n int v239; // [rsp+Ch] [rbp-6Ch]\n unsigned int v240; // [rsp+10h] [rbp-68h]\n unsigned int v241; // [rsp+10h] [rbp-68h]\n unsigned int v242; // [rsp+10h] [rbp-68h]\n unsigned int v243; // [rsp+10h] [rbp-68h]\n unsigned int v244; // [rsp+14h] [rbp-64h]\n int v245; // [rsp+14h] [rbp-64h]\n unsigned int v246; // [rsp+14h] [rbp-64h]\n int v247; // [rsp+14h] [rbp-64h]\n unsigned int v248; // [rsp+14h] [rbp-64h]\n int v249; // [rsp+14h] [rbp-64h]\n unsigned int v250; // [rsp+14h] [rbp-64h]\n int v251; // [rsp+14h] [rbp-64h]\n unsigned int v252; // [rsp+18h] [rbp-60h]\n unsigned int v253; // [rsp+18h] [rbp-60h]\n unsigned int v254; // [rsp+18h] [rbp-60h]\n unsigned int v255; // [rsp+18h] [rbp-60h]\n unsigned int v256; // [rsp+18h] [rbp-60h]\n unsigned int v257; // [rsp+18h] [rbp-60h]\n unsigned int v258; // [rsp+18h] [rbp-60h]\n unsigned int v259; // [rsp+18h] [rbp-60h]\n int v260; // [rsp+1Ch] [rbp-5Ch]\n int v261; // [rsp+1Ch] [rbp-5Ch]\n int v262; // [rsp+1Ch] [rbp-5Ch]\n int v263; // [rsp+1Ch] [rbp-5Ch]\n unsigned int v264; // [rsp+20h] [rbp-58h]\n unsigned int v265; // [rsp+20h] [rbp-58h]\n unsigned int v266; // [rsp+24h] [rbp-54h]\n int v267; // [rsp+24h] [rbp-54h]\n unsigned int v268; // [rsp+24h] [rbp-54h]\n int v269; // [rsp+24h] [rbp-54h]\n unsigned int v270; // [rsp+28h] [rbp-50h]\n unsigned int v271; // [rsp+28h] [rbp-50h]\n unsigned int v272; // [rsp+28h] [rbp-50h]\n unsigned int v273; // [rsp+28h] [rbp-50h]\n int v274; // [rsp+2Ch] [rbp-4Ch]\n int v275; // [rsp+2Ch] [rbp-4Ch]\n unsigned int v276; // [rsp+30h] [rbp-48h]\n int v277; // [rsp+34h] [rbp-44h]\n unsigned int v278; // [rsp+38h] [rbp-40h]\n int v279; // [rsp+38h] [rbp-40h]\n unsigned int v280; // [rsp+3Ch] [rbp-3Ch]\n unsigned int v281; // [rsp+3Ch] [rbp-3Ch]\n\n if ( !a2 )\n return 1LL;\n v2 = a1;\n result = 1LL;\n if ( a1 )\n {\n v4 = a1 - 1;\n v277 = 0;\n v276 = a2;\n v5 = a1 - 1;\n v6 = a2 - 1;\n if ( a2 == 1 )\n goto LABEL_139;\n while ( 1 )\n {\n v7 = v6;\n v278 = v6;\n v8 = v4;\n v9 = v7 - 1;\n v274 = 0;\n v280 = v4;\n v10 = v7 - 1;\n v264 = v2;\n if ( v4 )\n {\nLABEL_5:\n v11 = v8;\n v12 = v9;\n v240 = v7;\n v13 = v8 - 1;\n v266 = v8;\n v260 = 0;\n v14 = v8 - 1;\n v270 = v9;\n if ( v9 )\n {\nLABEL_6:\n v15 = v12;\n v16 = v13;\n v252 = v13;\n v232 = 0;\n v17 = v12 - 1;\n v208 = v11;\n v18 = v12 - 1;\n v244 = v12;\n if ( v16 )\n {\nLABEL_7:\n v216 = v16;\n v19 = v15;\n v20 = v16;\n v21 = 0;\n for ( i = v17; ; i = v24 - 1 )\n {\n v23 = v20;\n v24 = v20 - 1;\n v20 = v19;\n v25 = func0(i, v23);\n v21 += func0(i, v24) + v25;\n if ( !v24 )\n break;\n v19 = v24;\n }\n v26 = v216;\n if ( v17 )\n {\n v217 = v21 + 1;\n v27 = v17;\n v28 = 0;\n while ( 1 )\n {\n v29 = v26;\n v30 = v26 - 1;\n v26 = v27;\n v31 = func0(v27 - 1, v29);\n v28 += func0(v27 - 1, v30) + v31;\n if ( !v30 )\n break;\n v27 = v30;\n }\n v18 = v17;\n v232 += v28 + v217 + 1;\n goto LABEL_15;\n }\n v32 = v244;\n v34 = v252;\n v33 = v21 + v232 + 2;\n }\n else\n {\n while ( 1 )\n {\n v232 += 2;\n if ( !v17 )\n break;\nLABEL_15:\n v15 = v208;\n v16 = v18 - 1;\n v208 = v18;\n v17 = v15 - 1;\n v18 = v15 - 1;\n if ( v16 )\n goto LABEL_7;\n }\n v32 = v244;\n v33 = v232;\n v34 = v252;\n }\n if ( v34 )\n {\n v35 = v32;\n v245 = v33 + 1;\n v36 = v32 - 1;\n v209 = v34;\n v233 = 0;\n v37 = v32 - 1;\n v253 = v34;\n v38 = v34 - 1;\n if ( v34 == 1 )\n goto LABEL_29;\nLABEL_20:\n v39 = v38;\n v218 = v38;\n v40 = v35;\n v41 = 0;\n for ( j = v36; ; j = v44 - 1 )\n {\n v43 = v39;\n v44 = v39 - 1;\n v39 = v40;\n v45 = func0(j, v43);\n v41 += func0(j, v44) + v45;\n if ( !v44 )\n break;\n v40 = v44;\n }\n v46 = v218;\n if ( v36 )\n {\n v219 = v41 + 1;\n v47 = v36;\n v48 = 0;\n while ( 1 )\n {\n v49 = v46;\n v50 = v46 - 1;\n v46 = v47;\n v51 = func0(v47 - 1, v49);\n v48 += func0(v47 - 1, v50) + v51;\n if ( !v50 )\n break;\n v47 = v50;\n }\n v37 = v36;\n v233 += v48 + v219 + 1;\n do\n {\n v35 = v209;\n v52 = v37;\n v209 = v37;\n v36 = v35 - 1;\n v37 = v35 - 1;\n v38 = v52 - 1;\n if ( v38 )\n goto LABEL_20;\nLABEL_29:\n v233 += 2;\n }\n while ( v36 );\n v53 = v245;\n v54 = v233;\n v14 = v253;\n }\n else\n {\n v53 = v245;\n v14 = v253;\n v54 = v41 + v233 + 2;\n }\n v260 += v53 + v54 + 1;\n goto LABEL_32;\n }\n v55 = v266;\n v57 = v270;\n v56 = v260 + v33 + 2;\n }\n else\n {\n while ( 1 )\n {\n v260 += 2;\n if ( !v13 )\n break;\nLABEL_32:\n v11 = v240;\n v12 = v14 - 1;\n v240 = v14;\n v13 = v11 - 1;\n v14 = v11 - 1;\n if ( v12 )\n goto LABEL_6;\n }\n v55 = v266;\n v56 = v260;\n v57 = v270;\n }\n if ( v57 )\n {\n v58 = v55 - 1;\n v267 = v56 + 1;\n v241 = v57;\n v59 = v55 - 1;\n v261 = 0;\n v271 = v57;\n v60 = v57 - 1;\n if ( v57 == 1 )\n goto LABEL_64;\nLABEL_37:\n v61 = v60;\n v254 = v58;\n v62 = v60 - 1;\n v210 = v55;\n v246 = v60;\n v63 = v60 - 1;\n v234 = 0;\n if ( !v59 )\n goto LABEL_47;\nLABEL_38:\n v220 = v59;\n v64 = v61;\n v65 = v59;\n v66 = 0;\n for ( k = v62; ; k = v69 - 1 )\n {\n v68 = v65;\n v69 = v65 - 1;\n v65 = v64;\n v70 = func0(k, v68);\n v66 += func0(k, v69) + v70;\n if ( !v69 )\n break;\n v64 = v69;\n }\n v71 = v220;\n if ( v62 )\n {\n v221 = v66 + 1;\n v72 = v62;\n v73 = 0;\n while ( 1 )\n {\n v74 = v71;\n v75 = v71 - 1;\n v71 = v72;\n v76 = func0(v72 - 1, v74);\n v73 += func0(v72 - 1, v75) + v76;\n if ( !v75 )\n break;\n v72 = v75;\n }\n v63 = v62;\n v234 += v73 + v221 + 1;\n do\n {\n v61 = v210;\n v59 = v63 - 1;\n v210 = v63;\n v62 = v61 - 1;\n v63 = v61 - 1;\n if ( v59 )\n goto LABEL_38;\nLABEL_47:\n v234 += 2;\n }\n while ( v62 );\n v77 = v246;\n v78 = v234;\n v79 = v254;\n }\n else\n {\n v77 = v246;\n v79 = v254;\n v78 = v66 + v234 + 2;\n }\n if ( v79 )\n {\n v80 = v77;\n v247 = v78 + 1;\n v81 = v77 - 1;\n v211 = v79;\n v235 = 0;\n v82 = v77 - 1;\n v255 = v79;\n v83 = v79 - 1;\n if ( v79 == 1 )\n goto LABEL_60;\nLABEL_51:\n v84 = v83;\n v222 = v83;\n v85 = v80;\n v86 = 0;\n for ( m = v81; ; m = v89 - 1 )\n {\n v88 = v84;\n v89 = v84 - 1;\n v84 = v85;\n v90 = func0(m, v88);\n v86 += func0(m, v89) + v90;\n if ( !v89 )\n break;\n v85 = v89;\n }\n v91 = v222;\n if ( v81 )\n {\n v223 = v86 + 1;\n v92 = v81;\n v93 = 0;\n while ( 1 )\n {\n v94 = v91;\n v95 = v91 - 1;\n v91 = v92;\n v96 = func0(v92 - 1, v94);\n v93 += func0(v92 - 1, v95) + v96;\n if ( !v95 )\n break;\n v92 = v95;\n }\n v82 = v81;\n v235 += v93 + v223 + 1;\n do\n {\n v80 = v211;\n v97 = v82;\n v211 = v82;\n v81 = v80 - 1;\n v82 = v80 - 1;\n v83 = v97 - 1;\n if ( v83 )\n goto LABEL_51;\nLABEL_60:\n v235 += 2;\n }\n while ( v81 );\n v98 = v247;\n v99 = v235;\n v59 = v255;\n }\n else\n {\n v98 = v247;\n v59 = v255;\n v99 = v86 + v235 + 2;\n }\n v261 += v98 + v99 + 1;\n do\n {\n v55 = v241;\n v100 = v59;\n v241 = v59;\n v58 = v55 - 1;\n v59 = v55 - 1;\n v60 = v100 - 1;\n if ( v60 )\n goto LABEL_37;\nLABEL_64:\n v261 += 2;\n }\n while ( v58 );\n v101 = v267;\n v102 = v261;\n v10 = v271;\n }\n else\n {\n v101 = v267;\n v10 = v271;\n v102 = v261 + v78 + 2;\n }\n v274 += v101 + v102 + 1;\n goto LABEL_67;\n }\n v103 = v278;\n v105 = v280;\n v104 = v274 + v56 + 2;\n }\n else\n {\n while ( 1 )\n {\n v274 += 2;\n if ( !v9 )\n break;\nLABEL_67:\n v7 = v264;\n v264 = v10;\n v8 = v10 - 1;\n v9 = v7 - 1;\n v10 = v7 - 1;\n if ( v8 )\n goto LABEL_5;\n }\n v103 = v278;\n v104 = v274;\n v105 = v280;\n }\n if ( !v105 )\n break;\n v106 = v103;\n v265 = v105;\n v107 = v103 - 1;\n v279 = v104 + 1;\n v275 = 0;\n v108 = v103 - 1;\n v281 = v105;\n v109 = v105 - 1;\n if ( v105 == 1 )\n {\n while ( 1 )\n {\n v275 += 2;\n if ( !v107 )\n break;\nLABEL_134:\n v106 = v265;\n v203 = v108;\n v265 = v108;\n v107 = v106 - 1;\n v108 = v106 - 1;\n v109 = v203 - 1;\n if ( v109 )\n goto LABEL_72;\n }\n v204 = v279;\n v205 = v275;\n v5 = v281;\n }\n else\n {\nLABEL_72:\n v110 = v109;\n v242 = v106;\n v111 = v109 - 1;\n v268 = v109;\n v262 = 0;\n v112 = v109 - 1;\n v272 = v107;\n if ( v108 )\n {\nLABEL_73:\n v113 = v108;\n v114 = v111;\n v256 = v111;\n v236 = 0;\n v115 = v108 - 1;\n v212 = v110;\n v116 = v108 - 1;\n v248 = v108;\n if ( v114 )\n {\nLABEL_74:\n v224 = v114;\n v117 = v113;\n v118 = v114;\n v119 = 0;\n for ( n = v115; ; n = v122 - 1 )\n {\n v121 = v118;\n v122 = v118 - 1;\n v118 = v117;\n v123 = func0(n, v121);\n v119 += func0(n, v122) + v123;\n if ( !v122 )\n break;\n v117 = v122;\n }\n v124 = v224;\n if ( v115 )\n {\n v225 = v119 + 1;\n v125 = v115;\n v126 = 0;\n while ( 1 )\n {\n v127 = v124;\n v128 = v124 - 1;\n v124 = v125;\n v129 = func0(v125 - 1, v127);\n v126 += func0(v125 - 1, v128) + v129;\n if ( !v128 )\n break;\n v125 = v128;\n }\n v116 = v115;\n v236 += v126 + v225 + 1;\n goto LABEL_82;\n }\n v130 = v248;\n v132 = v256;\n v131 = v119 + v236 + 2;\n }\n else\n {\n while ( 1 )\n {\n v236 += 2;\n if ( !v115 )\n break;\nLABEL_82:\n v113 = v212;\n v114 = v116 - 1;\n v212 = v116;\n v115 = v113 - 1;\n v116 = v113 - 1;\n if ( v114 )\n goto LABEL_74;\n }\n v130 = v248;\n v131 = v236;\n v132 = v256;\n }\n if ( v132 )\n {\n v133 = v130;\n v249 = v131 + 1;\n v134 = v130 - 1;\n v213 = v132;\n v237 = 0;\n v135 = v130 - 1;\n v257 = v132;\n v136 = v132 - 1;\n if ( v132 == 1 )\n goto LABEL_96;\nLABEL_87:\n v137 = v136;\n v226 = v136;\n v138 = v133;\n v139 = 0;\n for ( ii = v134; ; ii = v142 - 1 )\n {\n v141 = v137;\n v142 = v137 - 1;\n v137 = v138;\n v143 = func0(ii, v141);\n v139 += func0(ii, v142) + v143;\n if ( !v142 )\n break;\n v138 = v142;\n }\n v144 = v226;\n if ( v134 )\n {\n v227 = v139 + 1;\n v145 = v134;\n v146 = 0;\n while ( 1 )\n {\n v147 = v144;\n v148 = v144 - 1;\n v144 = v145;\n v149 = func0(v145 - 1, v147);\n v146 += func0(v145 - 1, v148) + v149;\n if ( !v148 )\n break;\n v145 = v148;\n }\n v135 = v134;\n v237 += v146 + v227 + 1;\n do\n {\n v133 = v213;\n v150 = v135;\n v213 = v135;\n v134 = v133 - 1;\n v135 = v133 - 1;\n v136 = v150 - 1;\n if ( v136 )\n goto LABEL_87;\nLABEL_96:\n v237 += 2;\n }\n while ( v134 );\n v151 = v249;\n v152 = v237;\n v112 = v257;\n }\n else\n {\n v151 = v249;\n v112 = v257;\n v152 = v139 + v237 + 2;\n }\n v262 += v151 + v152 + 1;\n goto LABEL_99;\n }\n v153 = v268;\n v155 = v272;\n v154 = v262 + v131 + 2;\n }\n else\n {\n while ( 1 )\n {\n v262 += 2;\n if ( !v111 )\n break;\nLABEL_99:\n v110 = v242;\n v108 = v112 - 1;\n v242 = v112;\n v111 = v110 - 1;\n v112 = v110 - 1;\n if ( v108 )\n goto LABEL_73;\n }\n v153 = v268;\n v154 = v262;\n v155 = v272;\n }\n if ( v155 )\n {\n v156 = v155;\n v157 = v153 - 1;\n v243 = v155;\n v273 = v155;\n v158 = v153 - 1;\n v269 = v154 + 1;\n v263 = 0;\n v159 = v156 - 1;\n if ( !v159 )\n goto LABEL_131;\nLABEL_104:\n v160 = v159;\n v258 = v157;\n v238 = 0;\n v161 = v159 - 1;\n v162 = v157;\n v214 = v153;\n v163 = v159 - 1;\n v250 = v159;\n if ( !v162 )\n goto LABEL_114;\nLABEL_105:\n v228 = v162;\n v164 = v160;\n v165 = v162;\n v166 = 0;\n for ( jj = v161; ; jj = v169 - 1 )\n {\n v168 = v165;\n v169 = v165 - 1;\n v165 = v164;\n v170 = func0(jj, v168);\n v166 += func0(jj, v169) + v170;\n if ( !v169 )\n break;\n v164 = v169;\n }\n v171 = v228;\n if ( v161 )\n {\n v229 = v166 + 1;\n v172 = v161;\n v173 = 0;\n while ( 1 )\n {\n v174 = v171;\n v175 = v171 - 1;\n v171 = v172;\n v176 = func0(v172 - 1, v174);\n v173 += func0(v172 - 1, v175) + v176;\n if ( !v175 )\n break;\n v172 = v175;\n }\n v163 = v161;\n v238 += v173 + v229 + 1;\n do\n {\n v160 = v214;\n v162 = v163 - 1;\n v214 = v163;\n v161 = v160 - 1;\n v163 = v160 - 1;\n if ( v162 )\n goto LABEL_105;\nLABEL_114:\n v238 += 2;\n }\n while ( v161 );\n v177 = v250;\n v178 = v238;\n v179 = v258;\n }\n else\n {\n v177 = v250;\n v179 = v258;\n v178 = v166 + v238 + 2;\n }\n if ( v179 )\n {\n v180 = v177;\n v251 = v178 + 1;\n v181 = v177 - 1;\n v215 = v179;\n v239 = 0;\n v182 = v177 - 1;\n v259 = v179;\n v183 = v179 - 1;\n if ( v179 == 1 )\n goto LABEL_127;\nLABEL_118:\n v184 = v183;\n v230 = v183;\n v185 = v180;\n v186 = 0;\n for ( kk = v181; ; kk = v189 - 1 )\n {\n v188 = v184;\n v189 = v184 - 1;\n v184 = v185;\n v190 = func0(kk, v188);\n v186 += func0(kk, v189) + v190;\n if ( !v189 )\n break;\n v185 = v189;\n }\n v191 = v230;\n if ( v181 )\n {\n v231 = v186 + 1;\n v192 = v181;\n v193 = 0;\n while ( 1 )\n {\n v194 = v191;\n v195 = v191 - 1;\n v191 = v192;\n v196 = func0(v192 - 1, v194);\n v193 += func0(v192 - 1, v195) + v196;\n if ( !v195 )\n break;\n v192 = v195;\n }\n v182 = v181;\n v239 += v193 + v231 + 1;\n do\n {\n v180 = v215;\n v197 = v182;\n v215 = v182;\n v181 = v180 - 1;\n v182 = v180 - 1;\n v183 = v197 - 1;\n if ( v183 )\n goto LABEL_118;\nLABEL_127:\n v239 += 2;\n }\n while ( v181 );\n v198 = v251;\n v199 = v239;\n v158 = v259;\n }\n else\n {\n v198 = v251;\n v158 = v259;\n v199 = v186 + v239 + 2;\n }\n v263 += v198 + v199 + 1;\n do\n {\n v153 = v243;\n v200 = v158;\n v243 = v158;\n v157 = v153 - 1;\n v158 = v153 - 1;\n v159 = v200 - 1;\n if ( v159 )\n goto LABEL_104;\nLABEL_131:\n v263 += 2;\n }\n while ( v157 );\n v201 = v269;\n v202 = v263;\n v108 = v273;\n }\n else\n {\n v201 = v269;\n v108 = v273;\n v202 = v263 + v178 + 2;\n }\n v275 += v201 + v202 + 1;\n goto LABEL_134;\n }\n v204 = v279;\n v5 = v281;\n v205 = v275 + v154 + 2;\n }\n v277 += v204 + v205 + 1;\n while ( 1 )\n {\n v2 = v276;\n v206 = v5;\n v276 = v5;\n v4 = v2 - 1;\n v5 = v2 - 1;\n v6 = v206 - 1;\n if ( v6 )\n break;\nLABEL_139:\n v277 += 2;\n if ( !v4 )\n {\n v207 = v277;\n return (unsigned int)(v207 + 1);\n }\n }\n }\n v207 = v277 + v104 + 2;\n return (unsigned int)(v207 + 1);\n }\n return result;\n}", + "ida_strip_asm": "sub_1200:\nendbr64\ntest esi, esi\njz loc_1D9F\npush r15\nmov ecx, edi\nmov eax, 1\npush r14\npush r13\npush r12\nxor r12d, r12d\npush rbp\npush rbx\nsub rsp, 48h\ntest edi, edi\njz loc_1D90\nlea eax, [rcx-1]\nmov r9d, esi\nmov [rsp+78h+var_44], r12d\nmov [rsp+78h+var_48], esi\nmov r14d, eax\nsub r9d, 1\njz loc_1D7D\nloc_1248:\nmov esi, r9d\nmov ebp, eax\nmov [rsp+78h+var_40], r9d\nxor r15d, r15d\nmov r9d, ebp\nlea r14d, [rsi-1]\nmov [rsp+78h+var_4C], r15d\nmov [rsp+78h+var_3C], eax\nmov ebp, r14d\nmov [rsp+78h+var_58], ecx\ntest r9d, r9d\njz loc_17B4\nloc_1275:\nmov r8d, r9d\nxor r13d, r13d\nmov edx, r14d\nmov [rsp+78h+var_68], esi\nlea eax, [r8-1]\nmov [rsp+78h+var_54], r9d\nmov [rsp+78h+var_5C], r13d\nmov r15d, eax\nmov [rsp+78h+var_50], r14d\ntest edx, edx\njz loc_14F4\nloc_12A0:\nxor edi, edi\nmov r12d, edx\nmov esi, eax\nmov [rsp+78h+var_60], eax\nmov [rsp+78h+var_6C], edi\nlea edi, [r12-1]\nmov [rsp+78h+var_78], r8d\nmov eax, edi\nmov [rsp+78h+var_64], edx\ntest esi, esi\njz loc_1395\nloc_12C6:\nmov [rsp+78h+var_74], esi\nxor r13d, r13d\nmov r14d, r12d\nmov ebp, esi\nmov [rsp+78h+var_70], edi\nmov r12d, r13d\nmov r13d, edi\nloc_12DC:\nmov esi, ebp\nmov edi, r13d\nlea r15d, [rbp-1]\nmov ebp, r14d\ncall sub_1200\nmov esi, r15d\nmov edi, r13d\nmov ebx, eax\ncall sub_1200\nadd ebx, eax\nadd r12d, ebx\ntest r15d, r15d\njz short loc_1310\nmov r14d, r15d\nlea r13d, [r15-1]\njmp short loc_12DC\nloc_1310:\nmov eax, [rsp+78h+var_70]\nmov r14d, [rsp+78h+var_74]\nlea ebx, [r12+1]\ntest eax, eax\njz loc_1EE2\nmov [rsp+78h+var_74], ebx\nmov r13d, eax\nmov ebx, r15d\nloc_1330:\nlea r15d, [r13-1]\nmov esi, r14d\nlea r12d, [r14-1]\nmov r14d, r13d\nmov edi, r15d\ncall sub_1200\nmov esi, r12d\nmov edi, r15d\nmov ebp, eax\ncall sub_1200\nadd ebp, eax\nadd ebx, ebp\ntest r12d, r12d\njz short loc_1368\nmov r13d, r12d\njmp short loc_1330\nloc_1368:\nmov r15d, ebx\nmov ebx, [rsp+78h+var_74]\nmov eax, [rsp+78h+var_70]\nlea edx, [r15+rbx+1]\nadd [rsp+78h+var_6C], edx\nloc_137C:\nmov r12d, [rsp+78h+var_78]\nlea esi, [rax-1]\nmov [rsp+78h+var_78], eax\nlea edi, [r12-1]\nmov eax, edi\ntest esi, esi\njnz loc_12C6\nloc_1395:\nadd [rsp+78h+var_6C], 2\ntest edi, edi\njnz short loc_137C\nmov r9d, [rsp+78h+var_64]\nmov edi, [rsp+78h+var_6C]\nmov r15d, [rsp+78h+var_60]\nloc_13AC:\nlea r14d, [rdi+1]\ntest r15d, r15d\njz loc_1ECA\nmov r12d, r9d\nmov [rsp+78h+var_64], r14d\nxor esi, esi\nmov r14d, r15d\nlea edi, [r12-1]\nmov [rsp+78h+var_78], r15d\nmov [rsp+78h+var_6C], esi\nmov eax, edi\nmov [rsp+78h+var_60], r15d\nsub r14d, 1\njz loc_14B7\nloc_13E4:\nmov [rsp+78h+var_70], edi\nxor r13d, r13d\nmov ebp, r14d\nmov [rsp+78h+var_74], r14d\nmov r14d, r12d\nmov r12d, r13d\nmov r13d, edi\nloc_13FC:\nmov esi, ebp\nmov edi, r13d\nlea r15d, [rbp-1]\nmov ebp, r14d\ncall sub_1200\nmov esi, r15d\nmov edi, r13d\nmov ebx, eax\ncall sub_1200\nadd ebx, eax\nadd r12d, ebx\ntest r15d, r15d\njz short loc_1430\nmov r14d, r15d\nlea r13d, [r15-1]\njmp short loc_13FC\nloc_1430:\nmov eax, [rsp+78h+var_70]\nmov r14d, [rsp+78h+var_74]\nlea ebx, [r12+1]\ntest eax, eax\njz loc_1EB2\nmov [rsp+78h+var_74], ebx\nmov r13d, eax\nmov ebx, r15d\nloc_1450:\nlea r15d, [r13-1]\nmov esi, r14d\nlea r12d, [r14-1]\nmov r14d, r13d\nmov edi, r15d\ncall sub_1200\nmov esi, r12d\nmov edi, r15d\nmov ebp, eax\ncall sub_1200\nadd ebp, eax\nadd ebx, ebp\ntest r12d, r12d\njz short loc_1488\nmov r13d, r12d\njmp short loc_1450\nloc_1488:\nmov r15d, ebx\nmov ebx, [rsp+78h+var_74]\nmov eax, [rsp+78h+var_70]\nlea edx, [r15+rbx+1]\nadd [rsp+78h+var_6C], edx\nloc_149C:\nmov r12d, [rsp+78h+var_78]\nmov r14d, eax\nmov [rsp+78h+var_78], eax\nlea edi, [r12-1]\nmov eax, edi\nsub r14d, 1\njnz loc_13E4\nloc_14B7:\nadd [rsp+78h+var_6C], 2\ntest edi, edi\njnz short loc_149C\nmov r14d, [rsp+78h+var_64]\nmov esi, [rsp+78h+var_6C]\nmov r15d, [rsp+78h+var_60]\nloc_14CE:\nlea eax, [r14+rsi+1]\nadd [rsp+78h+var_5C], eax\nloc_14D7:\nmov r8d, [rsp+78h+var_68]\nlea edx, [r15-1]\nmov [rsp+78h+var_68], r15d\nlea eax, [r8-1]\nmov r15d, eax\ntest edx, edx\njnz loc_12A0\nloc_14F4:\nadd [rsp+78h+var_5C], 2\ntest eax, eax\njnz short loc_14D7\nmov r9d, [rsp+78h+var_54]\nmov r13d, [rsp+78h+var_5C]\nmov ebp, [rsp+78h+var_50]\nloc_150B:\nlea ebx, [r13+1]\ntest ebp, ebp\njz loc_1E99\nxor r13d, r13d\nlea eax, [r9-1]\nmov r10d, ebp\nmov [rsp+78h+var_54], ebx\nmov [rsp+78h+var_68], ebp\nmov ecx, eax\nmov [rsp+78h+var_5C], r13d\nmov [rsp+78h+var_50], ebp\nsub r10d, 1\njz loc_1777\nloc_153E:\nmov ebp, r10d\nxor edx, edx\nmov [rsp+78h+var_60], eax\nlea edi, [rbp-1]\nmov [rsp+78h+var_78], r9d\nmov [rsp+78h+var_64], r10d\nmov eax, edi\nmov [rsp+78h+var_6C], edx\ntest ecx, ecx\njz loc_162A\nloc_1561:\nmov [rsp+78h+var_74], ecx\nxor r12d, r12d\nmov r15d, ebp\nmov r14d, ecx\nmov [rsp+78h+var_70], edi\nmov ebp, r12d\nmov r12d, edi\nloc_1578:\nmov esi, r14d\nmov edi, r12d\nlea r13d, [r14-1]\nmov r14d, r15d\ncall sub_1200\nmov esi, r13d\nmov edi, r12d\nmov ebx, eax\ncall sub_1200\nadd ebx, eax\nadd ebp, ebx\ntest r13d, r13d\njz short loc_15B0\nmov r15d, r13d\nlea r12d, [r13-1]\njmp short loc_1578\nloc_15B0:\nmov eax, [rsp+78h+var_70]\nmov r15d, [rsp+78h+var_74]\nlea ebx, [rbp+1]\ntest eax, eax\njz loc_1E83\nmov [rsp+78h+var_74], ebx\nmov r14d, eax\nmov ebx, r13d\nloc_15CE:\nlea r13d, [r14-1]\nmov esi, r15d\nlea r12d, [r15-1]\nmov r15d, r14d\nmov edi, r13d\ncall sub_1200\nmov esi, r12d\nmov edi, r13d\nmov ebp, eax\ncall sub_1200\nadd ebp, eax\nadd ebx, ebp\ntest r12d, r12d\njz short loc_1600\nmov r14d, r12d\njmp short loc_15CE\nloc_1600:\nmov r13d, ebx\nmov ebx, [rsp+78h+var_74]\nmov eax, [rsp+78h+var_70]\nlea edx, [r13+rbx+1]\nadd [rsp+78h+var_6C], edx\nloc_1614:\nmov ebp, [rsp+78h+var_78]\nlea ecx, [rax-1]\nmov [rsp+78h+var_78], eax\nlea edi, [rbp-1]\nmov eax, edi\ntest ecx, ecx\njnz loc_1561\nloc_162A:\nadd [rsp+78h+var_6C], 2\ntest edi, edi\njnz short loc_1614\nmov r10d, [rsp+78h+var_64]\nmov edx, [rsp+78h+var_6C]\nmov ecx, [rsp+78h+var_60]\nloc_1640:\nlea r14d, [rdx+1]\ntest ecx, ecx\njz loc_1E6C\nmov ebp, r10d\nmov [rsp+78h+var_64], r14d\nxor esi, esi\nmov r14d, ecx\nlea edi, [rbp-1]\nmov [rsp+78h+var_78], ecx\nmov [rsp+78h+var_6C], esi\nmov eax, edi\nmov [rsp+78h+var_60], ecx\nsub r14d, 1\njz loc_173C\nloc_1673:\nmov [rsp+78h+var_70], edi\nxor r12d, r12d\nmov r15d, r14d\nmov [rsp+78h+var_74], r14d\nmov r14d, ebp\nmov ebp, r12d\nmov r12d, edi\nloc_168B:\nmov esi, r15d\nmov edi, r12d\nlea r13d, [r15-1]\nmov r15d, r14d\ncall sub_1200\nmov esi, r13d\nmov edi, r12d\nmov ebx, eax\ncall sub_1200\nadd ebx, eax\nadd ebp, ebx\ntest r13d, r13d\njz short loc_16C0\nmov r14d, r13d\nlea r12d, [r13-1]\njmp short loc_168B\nloc_16C0:\nmov eax, [rsp+78h+var_70]\nmov r14d, [rsp+78h+var_74]\nlea ebx, [rbp+1]\ntest eax, eax\njz loc_1E56\nmov [rsp+78h+var_74], ebx\nmov r15d, eax\nmov ebx, r13d\nloc_16DE:\nlea r13d, [r15-1]\nmov esi, r14d\nlea r12d, [r14-1]\nmov r14d, r15d\nmov edi, r13d\ncall sub_1200\nmov esi, r12d\nmov edi, r13d\nmov ebp, eax\ncall sub_1200\nadd ebp, eax\nadd ebx, ebp\ntest r12d, r12d\njz short loc_1710\nmov r15d, r12d\njmp short loc_16DE\nloc_1710:\nmov r13d, ebx\nmov ebx, [rsp+78h+var_74]\nmov eax, [rsp+78h+var_70]\nlea edx, [r13+rbx+1]\nadd [rsp+78h+var_6C], edx\nloc_1724:\nmov ebp, [rsp+78h+var_78]\nmov r14d, eax\nmov [rsp+78h+var_78], eax\nlea edi, [rbp-1]\nmov eax, edi\nsub r14d, 1\njnz loc_1673\nloc_173C:\nadd [rsp+78h+var_6C], 2\ntest edi, edi\njnz short loc_1724\nmov r14d, [rsp+78h+var_64]\nmov esi, [rsp+78h+var_6C]\nmov ecx, [rsp+78h+var_60]\nloc_1752:\nlea eax, [r14+rsi+1]\nadd [rsp+78h+var_5C], eax\nloc_175B:\nmov r9d, [rsp+78h+var_68]\nmov r10d, ecx\nmov [rsp+78h+var_68], ecx\nlea eax, [r9-1]\nmov ecx, eax\nsub r10d, 1\njnz loc_153E\nloc_1777:\nadd [rsp+78h+var_5C], 2\ntest eax, eax\njnz short loc_175B\nmov ebx, [rsp+78h+var_54]\nmov r13d, [rsp+78h+var_5C]\nmov ebp, [rsp+78h+var_50]\nloc_178D:\nlea eax, [rbx+r13+1]\nadd [rsp+78h+var_4C], eax\nloc_1796:\nmov esi, [rsp+78h+var_58]\nmov [rsp+78h+var_58], ebp\nlea ebp, [rbp-1]\nmov r9d, ebp\nlea r14d, [rsi-1]\nmov ebp, r14d\ntest r9d, r9d\njnz loc_1275\nloc_17B4:\nadd [rsp+78h+var_4C], 2\ntest r14d, r14d\njnz short loc_1796\nmov r9d, [rsp+78h+var_40]\nmov r15d, [rsp+78h+var_4C]\nmov r14d, [rsp+78h+var_3C]\nloc_17CD:\nlea ebx, [r15+1]\ntest r14d, r14d\njz loc_1E47\nmov esi, r9d\nxor ecx, ecx\nmov r9d, r14d\nmov [rsp+78h+var_58], r14d\nlea r13d, [rsi-1]\nmov [rsp+78h+var_40], ebx\nmov [rsp+78h+var_4C], ecx\nmov edx, r13d\nmov [rsp+78h+var_3C], r14d\nsub r9d, 1\njz loc_1D42\nloc_1805:\nmov r8d, r9d\nxor r12d, r12d\nmov [rsp+78h+var_68], esi\nlea eax, [r8-1]\nmov [rsp+78h+var_54], r9d\nmov [rsp+78h+var_5C], r12d\nmov r15d, eax\nmov [rsp+78h+var_50], r13d\ntest edx, edx\njz loc_1A84\nloc_182D:\nxor edi, edi\nmov r12d, edx\nmov esi, eax\nmov [rsp+78h+var_60], eax\nmov [rsp+78h+var_6C], edi\nlea edi, [r12-1]\nmov [rsp+78h+var_78], r8d\nmov eax, edi\nmov [rsp+78h+var_64], edx\ntest esi, esi\njz loc_1925\nloc_1853:\nmov [rsp+78h+var_74], esi\nxor r14d, r14d\nmov r13d, r12d\nmov ebp, esi\nmov [rsp+78h+var_70], edi\nmov r12d, r14d\nmov r14d, edi\nloc_1869:\nmov esi, ebp\nmov edi, r14d\nlea r15d, [rbp-1]\nmov ebp, r13d\ncall sub_1200\nmov esi, r15d\nmov edi, r14d\nmov ebx, eax\ncall sub_1200\nadd ebx, eax\nadd r12d, ebx\ntest r15d, r15d\njz short loc_18A0\nmov r13d, r15d\nlea r14d, [r15-1]\njmp short loc_1869\nloc_18A0:\nmov eax, [rsp+78h+var_70]\nmov r13d, [rsp+78h+var_74]\nlea ebx, [r12+1]\ntest eax, eax\njz loc_1E2F\nmov [rsp+78h+var_74], ebx\nmov r14d, eax\nmov ebx, r15d\nloc_18C0:\nlea r15d, [r14-1]\nmov esi, r13d\nlea r12d, [r13-1]\nmov r13d, r14d\nmov edi, r15d\ncall sub_1200\nmov esi, r12d\nmov edi, r15d\nmov ebp, eax\ncall sub_1200\nadd ebp, eax\nadd ebx, ebp\ntest r12d, r12d\njz short loc_18F8\nmov r14d, r12d\njmp short loc_18C0\nloc_18F8:\nmov r15d, ebx\nmov ebx, [rsp+78h+var_74]\nmov eax, [rsp+78h+var_70]\nlea edx, [r15+rbx+1]\nadd [rsp+78h+var_6C], edx\nloc_190C:\nmov r12d, [rsp+78h+var_78]\nlea esi, [rax-1]\nmov [rsp+78h+var_78], eax\nlea edi, [r12-1]\nmov eax, edi\ntest esi, esi\njnz loc_1853\nloc_1925:\nadd [rsp+78h+var_6C], 2\ntest edi, edi\njnz short loc_190C\nmov r9d, [rsp+78h+var_64]\nmov edi, [rsp+78h+var_6C]\nmov r15d, [rsp+78h+var_60]\nloc_193C:\nlea r13d, [rdi+1]\ntest r15d, r15d\njz loc_1E17\nmov r12d, r9d\nmov [rsp+78h+var_64], r13d\nxor esi, esi\nmov r13d, r15d\nlea edi, [r12-1]\nmov [rsp+78h+var_78], r15d\nmov [rsp+78h+var_6C], esi\nmov eax, edi\nmov [rsp+78h+var_60], r15d\nsub r13d, 1\njz loc_1A47\nloc_1974:\nmov [rsp+78h+var_70], edi\nxor r14d, r14d\nmov ebp, r13d\nmov [rsp+78h+var_74], r13d\nmov r13d, r12d\nmov r12d, r14d\nmov r14d, edi\nloc_198C:\nmov esi, ebp\nmov edi, r14d\nlea r15d, [rbp-1]\nmov ebp, r13d\ncall sub_1200\nmov esi, r15d\nmov edi, r14d\nmov ebx, eax\ncall sub_1200\nadd ebx, eax\nadd r12d, ebx\ntest r15d, r15d\njz short loc_19C0\nmov r13d, r15d\nlea r14d, [r15-1]\njmp short loc_198C\nloc_19C0:\nmov eax, [rsp+78h+var_70]\nmov r13d, [rsp+78h+var_74]\nlea ebx, [r12+1]\ntest eax, eax\njz loc_1DFF\nmov [rsp+78h+var_74], ebx\nmov r14d, eax\nmov ebx, r15d\nloc_19E0:\nlea r15d, [r14-1]\nmov esi, r13d\nlea r12d, [r13-1]\nmov r13d, r14d\nmov edi, r15d\ncall sub_1200\nmov esi, r12d\nmov edi, r15d\nmov ebp, eax\ncall sub_1200\nadd ebp, eax\nadd ebx, ebp\ntest r12d, r12d\njz short loc_1A18\nmov r14d, r12d\njmp short loc_19E0\nloc_1A18:\nmov r15d, ebx\nmov ebx, [rsp+78h+var_74]\nmov eax, [rsp+78h+var_70]\nlea edx, [r15+rbx+1]\nadd [rsp+78h+var_6C], edx\nloc_1A2C:\nmov r12d, [rsp+78h+var_78]\nmov r13d, eax\nmov [rsp+78h+var_78], eax\nlea edi, [r12-1]\nmov eax, edi\nsub r13d, 1\njnz loc_1974\nloc_1A47:\nadd [rsp+78h+var_6C], 2\ntest edi, edi\njnz short loc_1A2C\nmov r13d, [rsp+78h+var_64]\nmov esi, [rsp+78h+var_6C]\nmov r15d, [rsp+78h+var_60]\nloc_1A5E:\nlea eax, [r13+rsi+1]\nadd [rsp+78h+var_5C], eax\nloc_1A67:\nmov r8d, [rsp+78h+var_68]\nlea edx, [r15-1]\nmov [rsp+78h+var_68], r15d\nlea eax, [r8-1]\nmov r15d, eax\ntest edx, edx\njnz loc_182D\nloc_1A84:\nadd [rsp+78h+var_5C], 2\ntest eax, eax\njnz short loc_1A67\nmov r9d, [rsp+78h+var_54]\nmov r12d, [rsp+78h+var_5C]\nmov edx, [rsp+78h+var_50]\nloc_1A9B:\nlea ebp, [r12+1]\ntest edx, edx\njz loc_1DE8\nxor r13d, r13d\nmov r8d, edx\nlea eax, [r9-1]\nmov [rsp+78h+var_68], edx\nmov [rsp+78h+var_50], edx\nmov edx, eax\nmov [rsp+78h+var_54], ebp\nmov [rsp+78h+var_5C], r13d\nsub r8d, 1\njz loc_1D07\nloc_1ACF:\nxor esi, esi\nmov ebp, r8d\nmov [rsp+78h+var_60], eax\nmov [rsp+78h+var_6C], esi\nlea edi, [rbp-1]\nmov esi, eax\nmov [rsp+78h+var_78], r9d\nmov eax, edi\nmov [rsp+78h+var_64], r8d\ntest esi, esi\njz loc_1BBA\nloc_1AF4:\nmov [rsp+78h+var_74], esi\nxor r12d, r12d\nmov r15d, ebp\nmov r14d, esi\nmov [rsp+78h+var_70], edi\nmov ebp, r12d\nmov r12d, edi\nloc_1B0B:\nmov esi, r14d\nmov edi, r12d\nlea r13d, [r14-1]\nmov r14d, r15d\ncall sub_1200\nmov esi, r13d\nmov edi, r12d\nmov ebx, eax\ncall sub_1200\nadd ebx, eax\nadd ebp, ebx\ntest r13d, r13d\njz short loc_1B40\nmov r15d, r13d\nlea r12d, [r13-1]\njmp short loc_1B0B\nloc_1B40:\nmov eax, [rsp+78h+var_70]\nmov r15d, [rsp+78h+var_74]\nlea ebx, [rbp+1]\ntest eax, eax\njz loc_1DD2\nmov [rsp+78h+var_74], ebx\nmov r14d, eax\nmov ebx, r13d\nloc_1B5E:\nlea r13d, [r14-1]\nmov esi, r15d\nlea r12d, [r15-1]\nmov r15d, r14d\nmov edi, r13d\ncall sub_1200\nmov esi, r12d\nmov edi, r13d\nmov ebp, eax\ncall sub_1200\nadd ebp, eax\nadd ebx, ebp\ntest r12d, r12d\njz short loc_1B90\nmov r14d, r12d\njmp short loc_1B5E\nloc_1B90:\nmov r13d, ebx\nmov ebx, [rsp+78h+var_74]\nmov eax, [rsp+78h+var_70]\nlea edx, [r13+rbx+1]\nadd [rsp+78h+var_6C], edx\nloc_1BA4:\nmov ebp, [rsp+78h+var_78]\nlea esi, [rax-1]\nmov [rsp+78h+var_78], eax\nlea edi, [rbp-1]\nmov eax, edi\ntest esi, esi\njnz loc_1AF4\nloc_1BBA:\nadd [rsp+78h+var_6C], 2\ntest edi, edi\njnz short loc_1BA4\nmov r8d, [rsp+78h+var_64]\nmov esi, [rsp+78h+var_6C]\nmov edx, [rsp+78h+var_60]\nloc_1BD0:\nlea r14d, [rsi+1]\ntest edx, edx\njz loc_1DBB\nmov ebp, r8d\nmov [rsp+78h+var_64], r14d\nxor esi, esi\nmov r14d, edx\nlea edi, [rbp-1]\nmov [rsp+78h+var_78], edx\nmov [rsp+78h+var_6C], esi\nmov eax, edi\nmov [rsp+78h+var_60], edx\nsub r14d, 1\njz loc_1CCC\nloc_1C03:\nmov [rsp+78h+var_70], edi\nxor r12d, r12d\nmov r15d, r14d\nmov [rsp+78h+var_74], r14d\nmov r14d, ebp\nmov ebp, r12d\nmov r12d, edi\nloc_1C1B:\nmov esi, r15d\nmov edi, r12d\nlea r13d, [r15-1]\nmov r15d, r14d\ncall sub_1200\nmov esi, r13d\nmov edi, r12d\nmov ebx, eax\ncall sub_1200\nadd ebx, eax\nadd ebp, ebx\ntest r13d, r13d\njz short loc_1C50\nmov r14d, r13d\nlea r12d, [r13-1]\njmp short loc_1C1B\nloc_1C50:\nmov eax, [rsp+78h+var_70]\nmov r14d, [rsp+78h+var_74]\nlea ebx, [rbp+1]\ntest eax, eax\njz loc_1DA5\nmov [rsp+78h+var_74], ebx\nmov r15d, eax\nmov ebx, r13d\nloc_1C6E:\nlea r13d, [r15-1]\nmov esi, r14d\nlea r12d, [r14-1]\nmov r14d, r15d\nmov edi, r13d\ncall sub_1200\nmov esi, r12d\nmov edi, r13d\nmov ebp, eax\ncall sub_1200\nadd ebp, eax\nadd ebx, ebp\ntest r12d, r12d\njz short loc_1CA0\nmov r15d, r12d\njmp short loc_1C6E\nloc_1CA0:\nmov r13d, ebx\nmov ebx, [rsp+78h+var_74]\nmov eax, [rsp+78h+var_70]\nlea edx, [r13+rbx+1]\nadd [rsp+78h+var_6C], edx\nloc_1CB4:\nmov ebp, [rsp+78h+var_78]\nmov r14d, eax\nmov [rsp+78h+var_78], eax\nlea edi, [rbp-1]\nmov eax, edi\nsub r14d, 1\njnz loc_1C03\nloc_1CCC:\nadd [rsp+78h+var_6C], 2\ntest edi, edi\njnz short loc_1CB4\nmov r14d, [rsp+78h+var_64]\nmov esi, [rsp+78h+var_6C]\nmov edx, [rsp+78h+var_60]\nloc_1CE2:\nlea eax, [r14+rsi+1]\nadd [rsp+78h+var_5C], eax\nloc_1CEB:\nmov r9d, [rsp+78h+var_68]\nmov r8d, edx\nmov [rsp+78h+var_68], edx\nlea eax, [r9-1]\nmov edx, eax\nsub r8d, 1\njnz loc_1ACF\nloc_1D07:\nadd [rsp+78h+var_5C], 2\ntest eax, eax\njnz short loc_1CEB\nmov ebp, [rsp+78h+var_54]\nmov r13d, [rsp+78h+var_5C]\nmov edx, [rsp+78h+var_50]\nloc_1D1D:\nlea eax, [rbp+r13+1]\nadd [rsp+78h+var_4C], eax\nloc_1D26:\nmov esi, [rsp+78h+var_58]\nmov r9d, edx\nmov [rsp+78h+var_58], edx\nlea r13d, [rsi-1]\nmov edx, r13d\nsub r9d, 1\njnz loc_1805\nloc_1D42:\nadd [rsp+78h+var_4C], 2\ntest r13d, r13d\njnz short loc_1D26\nmov ebx, [rsp+78h+var_40]\nmov ecx, [rsp+78h+var_4C]\nmov r14d, [rsp+78h+var_3C]\nloc_1D59:\nlea eax, [rbx+rcx+1]\nadd [rsp+78h+var_44], eax\nloc_1D61:\nmov ecx, [rsp+78h+var_48]\nmov r9d, r14d\nmov [rsp+78h+var_48], r14d\nlea eax, [rcx-1]\nmov r14d, eax\nsub r9d, 1\njnz loc_1248\nloc_1D7D:\nadd [rsp+78h+var_44], 2\ntest eax, eax\njnz short loc_1D61\nmov r12d, [rsp+78h+var_44]\nloc_1D8B:\nlea eax, [r12+1]\nloc_1D90:\nadd rsp, 48h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1D9F:\nmov eax, 1\nretn\nloc_1DA5:\nmov esi, [rsp+78h+var_6C]\nmov r14d, [rsp+78h+var_64]\nmov edx, [rsp+78h+var_60]\nlea esi, [rbp+rsi+2]\njmp loc_1CE2\nloc_1DBB:\nmov r13d, [rsp+78h+var_5C]\nmov ebp, [rsp+78h+var_54]\nmov edx, [rsp+78h+var_50]\nlea r13d, [r13+rsi+2]\njmp loc_1D1D\nloc_1DD2:\nmov esi, [rsp+78h+var_6C]\nmov r8d, [rsp+78h+var_64]\nmov edx, [rsp+78h+var_60]\nlea esi, [rbp+rsi+2]\njmp loc_1BD0\nloc_1DE8:\nmov ecx, [rsp+78h+var_4C]\nmov ebx, [rsp+78h+var_40]\nmov r14d, [rsp+78h+var_3C]\nlea ecx, [rcx+r12+2]\njmp loc_1D59\nloc_1DFF:\nmov esi, [rsp+78h+var_6C]\nmov r13d, [rsp+78h+var_64]\nmov r15d, [rsp+78h+var_60]\nlea esi, [r12+rsi+2]\njmp loc_1A5E\nloc_1E17:\nmov r12d, [rsp+78h+var_5C]\nmov r9d, [rsp+78h+var_54]\nmov edx, [rsp+78h+var_50]\nlea r12d, [r12+rdi+2]\njmp loc_1A9B\nloc_1E2F:\nmov edi, [rsp+78h+var_6C]\nmov r9d, [rsp+78h+var_64]\nmov r15d, [rsp+78h+var_60]\nlea edi, [r12+rdi+2]\njmp loc_193C\nloc_1E47:\nmov r12d, [rsp+78h+var_44]\nlea r12d, [r12+r15+2]\njmp loc_1D8B\nloc_1E56:\nmov esi, [rsp+78h+var_6C]\nmov r14d, [rsp+78h+var_64]\nmov ecx, [rsp+78h+var_60]\nlea esi, [rbp+rsi+2]\njmp loc_1752\nloc_1E6C:\nmov r13d, [rsp+78h+var_5C]\nmov ebx, [rsp+78h+var_54]\nmov ebp, [rsp+78h+var_50]\nlea r13d, [r13+rdx+2]\njmp loc_178D\nloc_1E83:\nmov edx, [rsp+78h+var_6C]\nmov r10d, [rsp+78h+var_64]\nmov ecx, [rsp+78h+var_60]\nlea edx, [rbp+rdx+2]\njmp loc_1640\nloc_1E99:\nmov r15d, [rsp+78h+var_4C]\nmov r9d, [rsp+78h+var_40]\nmov r14d, [rsp+78h+var_3C]\nlea r15d, [r15+r13+2]\njmp loc_17CD\nloc_1EB2:\nmov esi, [rsp+78h+var_6C]\nmov r14d, [rsp+78h+var_64]\nmov r15d, [rsp+78h+var_60]\nlea esi, [r12+rsi+2]\njmp loc_14CE\nloc_1ECA:\nmov r13d, [rsp+78h+var_5C]\nmov r9d, [rsp+78h+var_54]\nmov ebp, [rsp+78h+var_50]\nlea r13d, [r13+rdi+2]\njmp loc_150B\nloc_1EE2:\nmov edi, [rsp+78h+var_6C]\nmov r9d, [rsp+78h+var_64]\nmov r15d, [rsp+78h+var_60]\nlea edi, [r12+rdi+2]\njmp loc_13AC", + "ida_strip_pseudo": "__int64 __fastcall sub_1200(unsigned int a1, unsigned int a2)\n{\n unsigned int v2; // ecx\n __int64 result; // rax\n unsigned int v4; // eax\n unsigned int v5; // r14d\n unsigned int v6; // r9d\n unsigned int v7; // esi\n unsigned int v8; // r9d\n unsigned int v9; // r14d\n unsigned int v10; // ebp\n unsigned int v11; // r8d\n unsigned int v12; // edx\n unsigned int v13; // eax\n unsigned int v14; // r15d\n unsigned int v15; // r12d\n unsigned int v16; // esi\n unsigned int v17; // edi\n unsigned int v18; // eax\n unsigned int v19; // r14d\n unsigned int v20; // ebp\n int v21; // r12d\n unsigned int i; // r13d\n __int64 v23; // rsi\n unsigned int v24; // r15d\n int v25; // ebx\n unsigned int v26; // r14d\n unsigned int v27; // r13d\n int v28; // ebx\n __int64 v29; // rsi\n unsigned int v30; // r12d\n int v31; // ebp\n unsigned int v32; // r9d\n int v33; // edi\n unsigned int v34; // r15d\n unsigned int v35; // r12d\n unsigned int v36; // edi\n unsigned int v37; // eax\n unsigned int v38; // r14d\n unsigned int v39; // ebp\n unsigned int v40; // r14d\n int v41; // r12d\n unsigned int j; // r13d\n __int64 v43; // rsi\n unsigned int v44; // r15d\n int v45; // ebx\n unsigned int v46; // r14d\n unsigned int v47; // r13d\n int v48; // ebx\n __int64 v49; // rsi\n unsigned int v50; // r12d\n int v51; // ebp\n unsigned int v52; // r14d\n int v53; // r14d\n int v54; // esi\n unsigned int v55; // r9d\n int v56; // r13d\n unsigned int v57; // ebp\n unsigned int v58; // eax\n unsigned int v59; // ecx\n unsigned int v60; // r10d\n unsigned int v61; // ebp\n unsigned int v62; // edi\n unsigned int v63; // eax\n unsigned int v64; // r15d\n unsigned int v65; // r14d\n int v66; // ebp\n unsigned int k; // r12d\n __int64 v68; // rsi\n unsigned int v69; // r13d\n int v70; // ebx\n unsigned int v71; // r15d\n unsigned int v72; // r14d\n int v73; // ebx\n __int64 v74; // rsi\n unsigned int v75; // r12d\n int v76; // ebp\n unsigned int v77; // r10d\n int v78; // edx\n unsigned int v79; // ecx\n unsigned int v80; // ebp\n unsigned int v81; // edi\n unsigned int v82; // eax\n unsigned int v83; // r14d\n unsigned int v84; // r15d\n unsigned int v85; // r14d\n int v86; // ebp\n unsigned int m; // r12d\n __int64 v88; // rsi\n unsigned int v89; // r13d\n int v90; // ebx\n unsigned int v91; // r14d\n unsigned int v92; // r15d\n int v93; // ebx\n __int64 v94; // rsi\n unsigned int v95; // r12d\n int v96; // ebp\n unsigned int v97; // r14d\n int v98; // r14d\n int v99; // esi\n unsigned int v100; // r10d\n int v101; // ebx\n int v102; // r13d\n unsigned int v103; // r9d\n int v104; // r15d\n unsigned int v105; // r14d\n unsigned int v106; // esi\n unsigned int v107; // r13d\n unsigned int v108; // edx\n unsigned int v109; // r9d\n unsigned int v110; // r8d\n unsigned int v111; // eax\n unsigned int v112; // r15d\n unsigned int v113; // r12d\n unsigned int v114; // esi\n unsigned int v115; // edi\n unsigned int v116; // eax\n unsigned int v117; // r13d\n unsigned int v118; // ebp\n int v119; // r12d\n unsigned int n; // r14d\n __int64 v121; // rsi\n unsigned int v122; // r15d\n int v123; // ebx\n unsigned int v124; // r13d\n unsigned int v125; // r14d\n int v126; // ebx\n __int64 v127; // rsi\n unsigned int v128; // r12d\n int v129; // ebp\n unsigned int v130; // r9d\n int v131; // edi\n unsigned int v132; // r15d\n unsigned int v133; // r12d\n unsigned int v134; // edi\n unsigned int v135; // eax\n unsigned int v136; // r13d\n unsigned int v137; // ebp\n unsigned int v138; // r13d\n int v139; // r12d\n unsigned int ii; // r14d\n __int64 v141; // rsi\n unsigned int v142; // r15d\n int v143; // ebx\n unsigned int v144; // r13d\n unsigned int v145; // r14d\n int v146; // ebx\n __int64 v147; // rsi\n unsigned int v148; // r12d\n int v149; // ebp\n unsigned int v150; // r13d\n int v151; // r13d\n int v152; // esi\n unsigned int v153; // r9d\n int v154; // r12d\n unsigned int v155; // edx\n unsigned int v156; // r8d\n unsigned int v157; // eax\n unsigned int v158; // edx\n unsigned int v159; // r8d\n unsigned int v160; // ebp\n unsigned int v161; // edi\n unsigned int v162; // esi\n unsigned int v163; // eax\n unsigned int v164; // r15d\n unsigned int v165; // r14d\n int v166; // ebp\n unsigned int jj; // r12d\n __int64 v168; // rsi\n unsigned int v169; // r13d\n int v170; // ebx\n unsigned int v171; // r15d\n unsigned int v172; // r14d\n int v173; // ebx\n __int64 v174; // rsi\n unsigned int v175; // r12d\n int v176; // ebp\n unsigned int v177; // r8d\n int v178; // esi\n unsigned int v179; // edx\n unsigned int v180; // ebp\n unsigned int v181; // edi\n unsigned int v182; // eax\n unsigned int v183; // r14d\n unsigned int v184; // r15d\n unsigned int v185; // r14d\n int v186; // ebp\n unsigned int kk; // r12d\n __int64 v188; // rsi\n unsigned int v189; // r13d\n int v190; // ebx\n unsigned int v191; // r14d\n unsigned int v192; // r15d\n int v193; // ebx\n __int64 v194; // rsi\n unsigned int v195; // r12d\n int v196; // ebp\n unsigned int v197; // r14d\n int v198; // r14d\n int v199; // esi\n unsigned int v200; // r8d\n int v201; // ebp\n int v202; // r13d\n unsigned int v203; // r9d\n int v204; // ebx\n int v205; // ecx\n unsigned int v206; // r9d\n int v207; // r12d\n unsigned int v208; // [rsp+0h] [rbp-78h]\n unsigned int v209; // [rsp+0h] [rbp-78h]\n unsigned int v210; // [rsp+0h] [rbp-78h]\n unsigned int v211; // [rsp+0h] [rbp-78h]\n unsigned int v212; // [rsp+0h] [rbp-78h]\n unsigned int v213; // [rsp+0h] [rbp-78h]\n unsigned int v214; // [rsp+0h] [rbp-78h]\n unsigned int v215; // [rsp+0h] [rbp-78h]\n unsigned int v216; // [rsp+4h] [rbp-74h]\n int v217; // [rsp+4h] [rbp-74h]\n unsigned int v218; // [rsp+4h] [rbp-74h]\n int v219; // [rsp+4h] [rbp-74h]\n unsigned int v220; // [rsp+4h] [rbp-74h]\n int v221; // [rsp+4h] [rbp-74h]\n unsigned int v222; // [rsp+4h] [rbp-74h]\n int v223; // [rsp+4h] [rbp-74h]\n unsigned int v224; // [rsp+4h] [rbp-74h]\n int v225; // [rsp+4h] [rbp-74h]\n unsigned int v226; // [rsp+4h] [rbp-74h]\n int v227; // [rsp+4h] [rbp-74h]\n unsigned int v228; // [rsp+4h] [rbp-74h]\n int v229; // [rsp+4h] [rbp-74h]\n unsigned int v230; // [rsp+4h] [rbp-74h]\n int v231; // [rsp+4h] [rbp-74h]\n int v232; // [rsp+Ch] [rbp-6Ch]\n int v233; // [rsp+Ch] [rbp-6Ch]\n int v234; // [rsp+Ch] [rbp-6Ch]\n int v235; // [rsp+Ch] [rbp-6Ch]\n int v236; // [rsp+Ch] [rbp-6Ch]\n int v237; // [rsp+Ch] [rbp-6Ch]\n int v238; // [rsp+Ch] [rbp-6Ch]\n int v239; // [rsp+Ch] [rbp-6Ch]\n unsigned int v240; // [rsp+10h] [rbp-68h]\n unsigned int v241; // [rsp+10h] [rbp-68h]\n unsigned int v242; // [rsp+10h] [rbp-68h]\n unsigned int v243; // [rsp+10h] [rbp-68h]\n unsigned int v244; // [rsp+14h] [rbp-64h]\n int v245; // [rsp+14h] [rbp-64h]\n unsigned int v246; // [rsp+14h] [rbp-64h]\n int v247; // [rsp+14h] [rbp-64h]\n unsigned int v248; // [rsp+14h] [rbp-64h]\n int v249; // [rsp+14h] [rbp-64h]\n unsigned int v250; // [rsp+14h] [rbp-64h]\n int v251; // [rsp+14h] [rbp-64h]\n unsigned int v252; // [rsp+18h] [rbp-60h]\n unsigned int v253; // [rsp+18h] [rbp-60h]\n unsigned int v254; // [rsp+18h] [rbp-60h]\n unsigned int v255; // [rsp+18h] [rbp-60h]\n unsigned int v256; // [rsp+18h] [rbp-60h]\n unsigned int v257; // [rsp+18h] [rbp-60h]\n unsigned int v258; // [rsp+18h] [rbp-60h]\n unsigned int v259; // [rsp+18h] [rbp-60h]\n int v260; // [rsp+1Ch] [rbp-5Ch]\n int v261; // [rsp+1Ch] [rbp-5Ch]\n int v262; // [rsp+1Ch] [rbp-5Ch]\n int v263; // [rsp+1Ch] [rbp-5Ch]\n unsigned int v264; // [rsp+20h] [rbp-58h]\n unsigned int v265; // [rsp+20h] [rbp-58h]\n unsigned int v266; // [rsp+24h] [rbp-54h]\n int v267; // [rsp+24h] [rbp-54h]\n unsigned int v268; // [rsp+24h] [rbp-54h]\n int v269; // [rsp+24h] [rbp-54h]\n unsigned int v270; // [rsp+28h] [rbp-50h]\n unsigned int v271; // [rsp+28h] [rbp-50h]\n unsigned int v272; // [rsp+28h] [rbp-50h]\n unsigned int v273; // [rsp+28h] [rbp-50h]\n int v274; // [rsp+2Ch] [rbp-4Ch]\n int v275; // [rsp+2Ch] [rbp-4Ch]\n unsigned int v276; // [rsp+30h] [rbp-48h]\n int v277; // [rsp+34h] [rbp-44h]\n unsigned int v278; // [rsp+38h] [rbp-40h]\n int v279; // [rsp+38h] [rbp-40h]\n unsigned int v280; // [rsp+3Ch] [rbp-3Ch]\n unsigned int v281; // [rsp+3Ch] [rbp-3Ch]\n\n if ( !a2 )\n return 1LL;\n v2 = a1;\n result = 1LL;\n if ( a1 )\n {\n v4 = a1 - 1;\n v277 = 0;\n v276 = a2;\n v5 = a1 - 1;\n v6 = a2 - 1;\n if ( a2 == 1 )\n goto LABEL_139;\n while ( 1 )\n {\n v7 = v6;\n v278 = v6;\n v8 = v4;\n v9 = v7 - 1;\n v274 = 0;\n v280 = v4;\n v10 = v7 - 1;\n v264 = v2;\n if ( v4 )\n {\nLABEL_5:\n v11 = v8;\n v12 = v9;\n v240 = v7;\n v13 = v8 - 1;\n v266 = v8;\n v260 = 0;\n v14 = v8 - 1;\n v270 = v9;\n if ( v9 )\n {\nLABEL_6:\n v15 = v12;\n v16 = v13;\n v252 = v13;\n v232 = 0;\n v17 = v12 - 1;\n v208 = v11;\n v18 = v12 - 1;\n v244 = v12;\n if ( v16 )\n {\nLABEL_7:\n v216 = v16;\n v19 = v15;\n v20 = v16;\n v21 = 0;\n for ( i = v17; ; i = v24 - 1 )\n {\n v23 = v20;\n v24 = v20 - 1;\n v20 = v19;\n v25 = sub_1200(i, v23);\n v21 += sub_1200(i, v24) + v25;\n if ( !v24 )\n break;\n v19 = v24;\n }\n v26 = v216;\n if ( v17 )\n {\n v217 = v21 + 1;\n v27 = v17;\n v28 = 0;\n while ( 1 )\n {\n v29 = v26;\n v30 = v26 - 1;\n v26 = v27;\n v31 = sub_1200(v27 - 1, v29);\n v28 += sub_1200(v27 - 1, v30) + v31;\n if ( !v30 )\n break;\n v27 = v30;\n }\n v18 = v17;\n v232 += v28 + v217 + 1;\n goto LABEL_15;\n }\n v32 = v244;\n v34 = v252;\n v33 = v21 + v232 + 2;\n }\n else\n {\n while ( 1 )\n {\n v232 += 2;\n if ( !v17 )\n break;\nLABEL_15:\n v15 = v208;\n v16 = v18 - 1;\n v208 = v18;\n v17 = v15 - 1;\n v18 = v15 - 1;\n if ( v16 )\n goto LABEL_7;\n }\n v32 = v244;\n v33 = v232;\n v34 = v252;\n }\n if ( v34 )\n {\n v35 = v32;\n v245 = v33 + 1;\n v36 = v32 - 1;\n v209 = v34;\n v233 = 0;\n v37 = v32 - 1;\n v253 = v34;\n v38 = v34 - 1;\n if ( v34 == 1 )\n goto LABEL_29;\nLABEL_20:\n v39 = v38;\n v218 = v38;\n v40 = v35;\n v41 = 0;\n for ( j = v36; ; j = v44 - 1 )\n {\n v43 = v39;\n v44 = v39 - 1;\n v39 = v40;\n v45 = sub_1200(j, v43);\n v41 += sub_1200(j, v44) + v45;\n if ( !v44 )\n break;\n v40 = v44;\n }\n v46 = v218;\n if ( v36 )\n {\n v219 = v41 + 1;\n v47 = v36;\n v48 = 0;\n while ( 1 )\n {\n v49 = v46;\n v50 = v46 - 1;\n v46 = v47;\n v51 = sub_1200(v47 - 1, v49);\n v48 += sub_1200(v47 - 1, v50) + v51;\n if ( !v50 )\n break;\n v47 = v50;\n }\n v37 = v36;\n v233 += v48 + v219 + 1;\n do\n {\n v35 = v209;\n v52 = v37;\n v209 = v37;\n v36 = v35 - 1;\n v37 = v35 - 1;\n v38 = v52 - 1;\n if ( v38 )\n goto LABEL_20;\nLABEL_29:\n v233 += 2;\n }\n while ( v36 );\n v53 = v245;\n v54 = v233;\n v14 = v253;\n }\n else\n {\n v53 = v245;\n v14 = v253;\n v54 = v41 + v233 + 2;\n }\n v260 += v53 + v54 + 1;\n goto LABEL_32;\n }\n v55 = v266;\n v57 = v270;\n v56 = v260 + v33 + 2;\n }\n else\n {\n while ( 1 )\n {\n v260 += 2;\n if ( !v13 )\n break;\nLABEL_32:\n v11 = v240;\n v12 = v14 - 1;\n v240 = v14;\n v13 = v11 - 1;\n v14 = v11 - 1;\n if ( v12 )\n goto LABEL_6;\n }\n v55 = v266;\n v56 = v260;\n v57 = v270;\n }\n if ( v57 )\n {\n v58 = v55 - 1;\n v267 = v56 + 1;\n v241 = v57;\n v59 = v55 - 1;\n v261 = 0;\n v271 = v57;\n v60 = v57 - 1;\n if ( v57 == 1 )\n goto LABEL_64;\nLABEL_37:\n v61 = v60;\n v254 = v58;\n v62 = v60 - 1;\n v210 = v55;\n v246 = v60;\n v63 = v60 - 1;\n v234 = 0;\n if ( !v59 )\n goto LABEL_47;\nLABEL_38:\n v220 = v59;\n v64 = v61;\n v65 = v59;\n v66 = 0;\n for ( k = v62; ; k = v69 - 1 )\n {\n v68 = v65;\n v69 = v65 - 1;\n v65 = v64;\n v70 = sub_1200(k, v68);\n v66 += sub_1200(k, v69) + v70;\n if ( !v69 )\n break;\n v64 = v69;\n }\n v71 = v220;\n if ( v62 )\n {\n v221 = v66 + 1;\n v72 = v62;\n v73 = 0;\n while ( 1 )\n {\n v74 = v71;\n v75 = v71 - 1;\n v71 = v72;\n v76 = sub_1200(v72 - 1, v74);\n v73 += sub_1200(v72 - 1, v75) + v76;\n if ( !v75 )\n break;\n v72 = v75;\n }\n v63 = v62;\n v234 += v73 + v221 + 1;\n do\n {\n v61 = v210;\n v59 = v63 - 1;\n v210 = v63;\n v62 = v61 - 1;\n v63 = v61 - 1;\n if ( v59 )\n goto LABEL_38;\nLABEL_47:\n v234 += 2;\n }\n while ( v62 );\n v77 = v246;\n v78 = v234;\n v79 = v254;\n }\n else\n {\n v77 = v246;\n v79 = v254;\n v78 = v66 + v234 + 2;\n }\n if ( v79 )\n {\n v80 = v77;\n v247 = v78 + 1;\n v81 = v77 - 1;\n v211 = v79;\n v235 = 0;\n v82 = v77 - 1;\n v255 = v79;\n v83 = v79 - 1;\n if ( v79 == 1 )\n goto LABEL_60;\nLABEL_51:\n v84 = v83;\n v222 = v83;\n v85 = v80;\n v86 = 0;\n for ( m = v81; ; m = v89 - 1 )\n {\n v88 = v84;\n v89 = v84 - 1;\n v84 = v85;\n v90 = sub_1200(m, v88);\n v86 += sub_1200(m, v89) + v90;\n if ( !v89 )\n break;\n v85 = v89;\n }\n v91 = v222;\n if ( v81 )\n {\n v223 = v86 + 1;\n v92 = v81;\n v93 = 0;\n while ( 1 )\n {\n v94 = v91;\n v95 = v91 - 1;\n v91 = v92;\n v96 = sub_1200(v92 - 1, v94);\n v93 += sub_1200(v92 - 1, v95) + v96;\n if ( !v95 )\n break;\n v92 = v95;\n }\n v82 = v81;\n v235 += v93 + v223 + 1;\n do\n {\n v80 = v211;\n v97 = v82;\n v211 = v82;\n v81 = v80 - 1;\n v82 = v80 - 1;\n v83 = v97 - 1;\n if ( v83 )\n goto LABEL_51;\nLABEL_60:\n v235 += 2;\n }\n while ( v81 );\n v98 = v247;\n v99 = v235;\n v59 = v255;\n }\n else\n {\n v98 = v247;\n v59 = v255;\n v99 = v86 + v235 + 2;\n }\n v261 += v98 + v99 + 1;\n do\n {\n v55 = v241;\n v100 = v59;\n v241 = v59;\n v58 = v55 - 1;\n v59 = v55 - 1;\n v60 = v100 - 1;\n if ( v60 )\n goto LABEL_37;\nLABEL_64:\n v261 += 2;\n }\n while ( v58 );\n v101 = v267;\n v102 = v261;\n v10 = v271;\n }\n else\n {\n v101 = v267;\n v10 = v271;\n v102 = v261 + v78 + 2;\n }\n v274 += v101 + v102 + 1;\n goto LABEL_67;\n }\n v103 = v278;\n v105 = v280;\n v104 = v274 + v56 + 2;\n }\n else\n {\n while ( 1 )\n {\n v274 += 2;\n if ( !v9 )\n break;\nLABEL_67:\n v7 = v264;\n v264 = v10;\n v8 = v10 - 1;\n v9 = v7 - 1;\n v10 = v7 - 1;\n if ( v8 )\n goto LABEL_5;\n }\n v103 = v278;\n v104 = v274;\n v105 = v280;\n }\n if ( !v105 )\n break;\n v106 = v103;\n v265 = v105;\n v107 = v103 - 1;\n v279 = v104 + 1;\n v275 = 0;\n v108 = v103 - 1;\n v281 = v105;\n v109 = v105 - 1;\n if ( v105 == 1 )\n {\n while ( 1 )\n {\n v275 += 2;\n if ( !v107 )\n break;\nLABEL_134:\n v106 = v265;\n v203 = v108;\n v265 = v108;\n v107 = v106 - 1;\n v108 = v106 - 1;\n v109 = v203 - 1;\n if ( v109 )\n goto LABEL_72;\n }\n v204 = v279;\n v205 = v275;\n v5 = v281;\n }\n else\n {\nLABEL_72:\n v110 = v109;\n v242 = v106;\n v111 = v109 - 1;\n v268 = v109;\n v262 = 0;\n v112 = v109 - 1;\n v272 = v107;\n if ( v108 )\n {\nLABEL_73:\n v113 = v108;\n v114 = v111;\n v256 = v111;\n v236 = 0;\n v115 = v108 - 1;\n v212 = v110;\n v116 = v108 - 1;\n v248 = v108;\n if ( v114 )\n {\nLABEL_74:\n v224 = v114;\n v117 = v113;\n v118 = v114;\n v119 = 0;\n for ( n = v115; ; n = v122 - 1 )\n {\n v121 = v118;\n v122 = v118 - 1;\n v118 = v117;\n v123 = sub_1200(n, v121);\n v119 += sub_1200(n, v122) + v123;\n if ( !v122 )\n break;\n v117 = v122;\n }\n v124 = v224;\n if ( v115 )\n {\n v225 = v119 + 1;\n v125 = v115;\n v126 = 0;\n while ( 1 )\n {\n v127 = v124;\n v128 = v124 - 1;\n v124 = v125;\n v129 = sub_1200(v125 - 1, v127);\n v126 += sub_1200(v125 - 1, v128) + v129;\n if ( !v128 )\n break;\n v125 = v128;\n }\n v116 = v115;\n v236 += v126 + v225 + 1;\n goto LABEL_82;\n }\n v130 = v248;\n v132 = v256;\n v131 = v119 + v236 + 2;\n }\n else\n {\n while ( 1 )\n {\n v236 += 2;\n if ( !v115 )\n break;\nLABEL_82:\n v113 = v212;\n v114 = v116 - 1;\n v212 = v116;\n v115 = v113 - 1;\n v116 = v113 - 1;\n if ( v114 )\n goto LABEL_74;\n }\n v130 = v248;\n v131 = v236;\n v132 = v256;\n }\n if ( v132 )\n {\n v133 = v130;\n v249 = v131 + 1;\n v134 = v130 - 1;\n v213 = v132;\n v237 = 0;\n v135 = v130 - 1;\n v257 = v132;\n v136 = v132 - 1;\n if ( v132 == 1 )\n goto LABEL_96;\nLABEL_87:\n v137 = v136;\n v226 = v136;\n v138 = v133;\n v139 = 0;\n for ( ii = v134; ; ii = v142 - 1 )\n {\n v141 = v137;\n v142 = v137 - 1;\n v137 = v138;\n v143 = sub_1200(ii, v141);\n v139 += sub_1200(ii, v142) + v143;\n if ( !v142 )\n break;\n v138 = v142;\n }\n v144 = v226;\n if ( v134 )\n {\n v227 = v139 + 1;\n v145 = v134;\n v146 = 0;\n while ( 1 )\n {\n v147 = v144;\n v148 = v144 - 1;\n v144 = v145;\n v149 = sub_1200(v145 - 1, v147);\n v146 += sub_1200(v145 - 1, v148) + v149;\n if ( !v148 )\n break;\n v145 = v148;\n }\n v135 = v134;\n v237 += v146 + v227 + 1;\n do\n {\n v133 = v213;\n v150 = v135;\n v213 = v135;\n v134 = v133 - 1;\n v135 = v133 - 1;\n v136 = v150 - 1;\n if ( v136 )\n goto LABEL_87;\nLABEL_96:\n v237 += 2;\n }\n while ( v134 );\n v151 = v249;\n v152 = v237;\n v112 = v257;\n }\n else\n {\n v151 = v249;\n v112 = v257;\n v152 = v139 + v237 + 2;\n }\n v262 += v151 + v152 + 1;\n goto LABEL_99;\n }\n v153 = v268;\n v155 = v272;\n v154 = v262 + v131 + 2;\n }\n else\n {\n while ( 1 )\n {\n v262 += 2;\n if ( !v111 )\n break;\nLABEL_99:\n v110 = v242;\n v108 = v112 - 1;\n v242 = v112;\n v111 = v110 - 1;\n v112 = v110 - 1;\n if ( v108 )\n goto LABEL_73;\n }\n v153 = v268;\n v154 = v262;\n v155 = v272;\n }\n if ( v155 )\n {\n v156 = v155;\n v157 = v153 - 1;\n v243 = v155;\n v273 = v155;\n v158 = v153 - 1;\n v269 = v154 + 1;\n v263 = 0;\n v159 = v156 - 1;\n if ( !v159 )\n goto LABEL_131;\nLABEL_104:\n v160 = v159;\n v258 = v157;\n v238 = 0;\n v161 = v159 - 1;\n v162 = v157;\n v214 = v153;\n v163 = v159 - 1;\n v250 = v159;\n if ( !v162 )\n goto LABEL_114;\nLABEL_105:\n v228 = v162;\n v164 = v160;\n v165 = v162;\n v166 = 0;\n for ( jj = v161; ; jj = v169 - 1 )\n {\n v168 = v165;\n v169 = v165 - 1;\n v165 = v164;\n v170 = sub_1200(jj, v168);\n v166 += sub_1200(jj, v169) + v170;\n if ( !v169 )\n break;\n v164 = v169;\n }\n v171 = v228;\n if ( v161 )\n {\n v229 = v166 + 1;\n v172 = v161;\n v173 = 0;\n while ( 1 )\n {\n v174 = v171;\n v175 = v171 - 1;\n v171 = v172;\n v176 = sub_1200(v172 - 1, v174);\n v173 += sub_1200(v172 - 1, v175) + v176;\n if ( !v175 )\n break;\n v172 = v175;\n }\n v163 = v161;\n v238 += v173 + v229 + 1;\n do\n {\n v160 = v214;\n v162 = v163 - 1;\n v214 = v163;\n v161 = v160 - 1;\n v163 = v160 - 1;\n if ( v162 )\n goto LABEL_105;\nLABEL_114:\n v238 += 2;\n }\n while ( v161 );\n v177 = v250;\n v178 = v238;\n v179 = v258;\n }\n else\n {\n v177 = v250;\n v179 = v258;\n v178 = v166 + v238 + 2;\n }\n if ( v179 )\n {\n v180 = v177;\n v251 = v178 + 1;\n v181 = v177 - 1;\n v215 = v179;\n v239 = 0;\n v182 = v177 - 1;\n v259 = v179;\n v183 = v179 - 1;\n if ( v179 == 1 )\n goto LABEL_127;\nLABEL_118:\n v184 = v183;\n v230 = v183;\n v185 = v180;\n v186 = 0;\n for ( kk = v181; ; kk = v189 - 1 )\n {\n v188 = v184;\n v189 = v184 - 1;\n v184 = v185;\n v190 = sub_1200(kk, v188);\n v186 += sub_1200(kk, v189) + v190;\n if ( !v189 )\n break;\n v185 = v189;\n }\n v191 = v230;\n if ( v181 )\n {\n v231 = v186 + 1;\n v192 = v181;\n v193 = 0;\n while ( 1 )\n {\n v194 = v191;\n v195 = v191 - 1;\n v191 = v192;\n v196 = sub_1200(v192 - 1, v194);\n v193 += sub_1200(v192 - 1, v195) + v196;\n if ( !v195 )\n break;\n v192 = v195;\n }\n v182 = v181;\n v239 += v193 + v231 + 1;\n do\n {\n v180 = v215;\n v197 = v182;\n v215 = v182;\n v181 = v180 - 1;\n v182 = v180 - 1;\n v183 = v197 - 1;\n if ( v183 )\n goto LABEL_118;\nLABEL_127:\n v239 += 2;\n }\n while ( v181 );\n v198 = v251;\n v199 = v239;\n v158 = v259;\n }\n else\n {\n v198 = v251;\n v158 = v259;\n v199 = v186 + v239 + 2;\n }\n v263 += v198 + v199 + 1;\n do\n {\n v153 = v243;\n v200 = v158;\n v243 = v158;\n v157 = v153 - 1;\n v158 = v153 - 1;\n v159 = v200 - 1;\n if ( v159 )\n goto LABEL_104;\nLABEL_131:\n v263 += 2;\n }\n while ( v157 );\n v201 = v269;\n v202 = v263;\n v108 = v273;\n }\n else\n {\n v201 = v269;\n v108 = v273;\n v202 = v263 + v178 + 2;\n }\n v275 += v201 + v202 + 1;\n goto LABEL_134;\n }\n v204 = v279;\n v5 = v281;\n v205 = v275 + v154 + 2;\n }\n v277 += v204 + v205 + 1;\n while ( 1 )\n {\n v2 = v276;\n v206 = v5;\n v276 = v5;\n v4 = v2 - 1;\n v5 = v2 - 1;\n v6 = v206 - 1;\n if ( v6 )\n break;\nLABEL_139:\n v277 += 2;\n if ( !v4 )\n {\n v207 = v277;\n return (unsigned int)(v207 + 1);\n }\n }\n }\n v207 = v277 + v104 + 2;\n return (unsigned int)(v207 + 1);\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1200(unsigned int a1, unsigned int a2) {\n unsigned int v2;\n long long result;\n unsigned int v4;\n unsigned int v5;\n unsigned int v6;\n unsigned int v7;\n unsigned int v8;\n unsigned int v9;\n unsigned int v10;\n unsigned int v11;\n unsigned int v12;\n unsigned int v13;\n unsigned int v14;\n unsigned int v15;\n unsigned int v16;\n unsigned int v17;\n unsigned int v18;\n unsigned int v19;\n unsigned int v20;\n int v21;\n unsigned int i;\n long long v23;\n unsigned int v24;\n int v25;\n unsigned int v26;\n unsigned int v27;\n int v28;\n long long v29;\n unsigned int v30;\n int v31;\n unsigned int v32;\n int v33;\n unsigned int v34;\n unsigned int v35;\n unsigned int v36;\n unsigned int v37;\n unsigned int v38;\n unsigned int v39;\n unsigned int v40;\n int v41;\n unsigned int j;\n long long v43;\n unsigned int v44;\n int v45;\n unsigned int v46;\n unsigned int v47;\n int v48;\n long long v49;\n unsigned int v50;\n int v51;\n unsigned int v52;\n int v53;\n int v54;\n unsigned int v55;\n int v56;\n unsigned int v57;\n unsigned int v58;\n unsigned int v59;\n unsigned int v60;\n unsigned int v61;\n unsigned int v62;\n unsigned int v63;\n unsigned int v64;\n unsigned int v65;\n int v66;\n unsigned int k;\n long long v68;\n unsigned int v69;\n int v70;\n unsigned int v71;\n unsigned int v72;\n int v73;\n long long v74;\n unsigned int v75;\n int v76;\n unsigned int v77;\n int v78;\n unsigned int v79;\n unsigned int v80;\n unsigned int v81;\n unsigned int v82;\n unsigned int v83;\n unsigned int v84;\n unsigned int v85;\n int v86;\n unsigned int m;\n long long v88;\n unsigned int v89;\n int v90;\n unsigned int v91;\n unsigned int v92;\n int v93;\n long long v94;\n unsigned int v95;\n int v96;\n unsigned int v97;\n int v98;\n int v99;\n unsigned int v100;\n int v101;\n int v102;\n unsigned int v103;\n int v104;\n unsigned int v105;\n unsigned int v106;\n unsigned int v107;\n unsigned int v108;\n unsigned int v109;\n unsigned int v110;\n unsigned int v111;\n unsigned int v112;\n unsigned int v113;\n unsigned int v114;\n unsigned int v115;\n unsigned int v116;\n unsigned int v117;\n unsigned int v118;\n int v119;\n unsigned int n;\n long long v121;\n unsigned int v122;\n int v123;\n unsigned int v124;\n unsigned int v125;\n int v126;\n long long v127;\n unsigned int v128;\n int v129;\n unsigned int v130;\n int v131;\n unsigned int v132;\n unsigned int v133;\n unsigned int v134;\n unsigned int v135;\n unsigned int v136;\n unsigned int v137;\n unsigned int v138;\n int v139;\n unsigned int ii;\n long long v141;\n unsigned int v142;\n int v143;\n unsigned int v144;\n unsigned int v145;\n int v146;\n long long v147;\n unsigned int v148;\n int v149;\n unsigned int v150;\n int v151;\n int v152;\n unsigned int v153;\n int v154;\n unsigned int v155;\n unsigned int v156;\n unsigned int v157;\n unsigned int v158;\n unsigned int v159;\n unsigned int v160;\n unsigned int v161;\n unsigned int v162;\n unsigned int v163;\n unsigned int v164;\n unsigned int v165;\n int v166;\n unsigned int jj;\n long long v168;\n unsigned int v169;\n int v170;\n unsigned int v171;\n unsigned int v172;\n int v173;\n long long v174;\n unsigned int v175;\n int v176;\n unsigned int v177;\n int v178;\n unsigned int v179;\n unsigned int v180;\n unsigned int v181;\n unsigned int v182;\n unsigned int v183;\n unsigned int v184;\n unsigned int v185;\n int v186;\n unsigned int kk;\n long long v188;\n unsigned int v189;\n int v190;\n unsigned int v191;\n unsigned int v192;\n int v193;\n long long v194;\n unsigned int v195;\n int v196;\n unsigned int v197;\n int v198;\n int v199;\n unsigned int v200;\n int v201;\n int v202;\n unsigned int v203;\n int v204;\n int v205;\n unsigned int v206;\n int v207;\n unsigned int v208;\n unsigned int v209;\n unsigned int v210;\n unsigned int v211;\n unsigned int v212;\n unsigned int v213;\n unsigned int v214;\n unsigned int v215;\n unsigned int v216;\n int v217;\n unsigned int v218;\n int v219;\n unsigned int v220;\n int v221;\n unsigned int v222;\n int v223;\n unsigned int v224;\n int v225;\n unsigned int v226;\n int v227;\n unsigned int v228;\n int v229;\n unsigned int v230;\n int v231;\n int v232;\n int v233;\n int v234;\n int v235;\n int v236;\n int v237;\n int v238;\n int v239;\n unsigned int v240;\n unsigned int v241;\n unsigned int v242;\n unsigned int v243;\n unsigned int v244;\n int v245;\n unsigned int v246;\n int v247;\n unsigned int v248;\n int v249;\n unsigned int v250;\n int v251;\n unsigned int v252;\n unsigned int v253;\n unsigned int v254;\n unsigned int v255;\n unsigned int v256;\n unsigned int v257;\n unsigned int v258;\n unsigned int v259;\n int v260;\n int v261;\n int v262;\n int v263;\n unsigned int v264;\n unsigned int v265;\n unsigned int v266;\n int v267;\n unsigned int v268;\n int v269;\n unsigned int v270;\n unsigned int v271;\n unsigned int v272;\n unsigned int v273;\n int v274;\n int v275;\n unsigned int v276;\n int v277;\n unsigned int v278;\n int v279;\n unsigned int v280;\n unsigned int v281;\n if (!a2) return 1LL;\n v2 = a1;\n result = 1LL;\n if (a1) {\n v4 = a1 - 1;\n v277 = 0;\n v276 = a2;\n v5 = a1 - 1;\n v6 = a2 - 1;\n if (a2 == 1) goto LABEL_139;\n while (1) {\n v7 = v6;\n v278 = v6;\n v8 = v4;\n v9 = v7 - 1;\n v274 = 0;\n v280 = v4;\n v10 = v7 - 1;\n v264 = v2;\n if (v4) {\n LABEL_5:\n v11 = v8;\n v12 = v9;\n v240 = v7;\n v13 = v8 - 1;\n v266 = v8;\n v260 = 0;\n v14 = v8 - 1;\n v270 = v9;\n if (v9) {\n LABEL_6:\n v15 = v12;\n v16 = v13;\n v252 = v13;\n v232 = 0;\n v17 = v12 - 1;\n v208 = v11;\n v18 = v12 - 1;\n v244 = v12;\n if (v16) {\n LABEL_7:\n v216 = v16;\n v19 = v15;\n v20 = v16;\n v21 = 0;\n for (i = v17;; i = v24 - 1) {\n v23 = v20;\n v24 = v20 - 1;\n v20 = v19;\n v25 = sub_1200(i, v23);\n v21 += sub_1200(i, v24) + v25;\n if (!v24) break;\n v19 = v24;\n }\n v26 = v216;\n if (v17) {\n v217 = v21 + 1;\n v27 = v17;\n v28 = 0;\n while (1) {\n v29 = v26;\n v30 = v26 - 1;\n v26 = v27;\n v31 = sub_1200(v27 - 1, v29);\n v28 += sub_1200(v27 - 1, v30) + v31;\n if (!v30) break;\n v27 = v30;\n }\n v18 = v17;\n v232 += v28 + v217 + 1;\n goto LABEL_15;\n }\n v32 = v244;\n v34 = v252;\n v33 = v21 + v232 + 2;\n } else {\n while (1) {\n v232 += 2;\n if (!v17) break;\n LABEL_15:\n v15 = v208;\n v16 = v18 - 1;\n v208 = v18;\n v17 = v15 - 1;\n v18 = v15 - 1;\n if (v16) goto LABEL_7;\n }\n v32 = v244;\n v33 = v232;\n v34 = v252;\n }\n if (v34) {\n v35 = v32;\n v245 = v33 + 1;\n v36 = v32 - 1;\n v209 = v34;\n v233 = 0;\n v37 = v32 - 1;\n v253 = v34;\n v38 = v34 - 1;\n if (v34 == 1) goto LABEL_29;\n LABEL_20:\n v39 = v38;\n v218 = v38;\n v40 = v35;\n v41 = 0;\n for (j = v36;; j = v44 - 1) {\n v43 = v39;\n v44 = v39 - 1;\n v39 = v40;\n v45 = sub_1200(j, v43);\n v41 += sub_1200(j, v44) + v45;\n if (!v44) break;\n v40 = v44;\n }\n v46 = v218;\n if (v36) {\n v219 = v41 + 1;\n v47 = v36;\n v48 = 0;\n while (1) {\n v49 = v46;\n v50 = v46 - 1;\n v46 = v47;\n v51 = sub_1200(v47 - 1, v49);\n v48 += sub_1200(v47 - 1, v50) + v51;\n if (!v50) break;\n v47 = v50;\n }\n v37 = v36;\n v233 += v48 + v219 + 1;\n do {\n v35 = v209;\n v52 = v37;\n v209 = v37;\n v36 = v35 - 1;\n v37 = v35 - 1;\n v38 = v52 - 1;\n if (v38) goto LABEL_20;\n LABEL_29:\n v233 += 2;\n } while (v36);\n v53 = v245;\n v54 = v233;\n v14 = v253;\n } else {\n v53 = v245;\n v14 = v253;\n v54 = v41 + v233 + 2;\n }\n v260 += v53 + v54 + 1;\n goto LABEL_32;\n }\n v55 = v266;\n v57 = v270;\n v56 = v260 + v33 + 2;\n } else {\n while (1) {\n v260 += 2;\n if (!v13) break;\n LABEL_32:\n v11 = v240;\n v12 = v14 - 1;\n v240 = v14;\n v13 = v11 - 1;\n v14 = v11 - 1;\n if (v12) goto LABEL_6;\n }\n v55 = v266;\n v56 = v260;\n v57 = v270;\n }\n if (v57) {\n v58 = v55 - 1;\n v267 = v56 + 1;\n v241 = v57;\n v59 = v55 - 1;\n v261 = 0;\n v271 = v57;\n v60 = v57 - 1;\n if (v57 == 1) goto LABEL_64;\n LABEL_37:\n v61 = v60;\n v254 = v58;\n v62 = v60 - 1;\n v210 = v55;\n v246 = v60;\n v63 = v60 - 1;\n v234 = 0;\n if (!v59) goto LABEL_47;\n LABEL_38:\n v220 = v59;\n v64 = v61;\n v65 = v59;\n v66 = 0;\n for (k = v62;; k = v69 - 1) {\n v68 = v65;\n v69 = v65 - 1;\n v65 = v64;\n v70 = sub_1200(k, v68);\n v66 += sub_1200(k, v69) + v70;\n if (!v69) break;\n v64 = v69;\n }\n v71 = v220;\n if (v62) {\n v221 = v66 + 1;\n v72 = v62;\n v73 = 0;\n while (1) {\n v74 = v71;\n v75 = v71 - 1;\n v71 = v72;\n v76 = sub_1200(v72 - 1, v74);\n v73 += sub_1200(v72 - 1, v75) + v76;\n if (!v75) break;\n v72 = v75;\n }\n v63 = v62;\n v234 += v73 + v221 + 1;\n do {\n v61 = v210;\n v59 = v63 - 1;\n v210 = v63;\n v62 = v61 - 1;\n v63 = v61 - 1;\n if (v59) goto LABEL_38;\n LABEL_47:\n v234 += 2;\n } while (v62);\n v77 = v246;\n v78 = v234;\n v79 = v254;\n } else {\n v77 = v246;\n v79 = v254;\n v78 = v66 + v234 + 2;\n }\n if (v79) {\n v80 = v77;\n v247 = v78 + 1;\n v81 = v77 - 1;\n v211 = v79;\n v235 = 0;\n v82 = v77 - 1;\n v255 = v79;\n v83 = v79 - 1;\n if (v79 == 1) goto LABEL_60;\n LABEL_51:\n v84 = v83;\n v222 = v83;\n v85 = v80;\n v86 = 0;\n for (m = v81;; m = v89 - 1) {\n v88 = v84;\n v89 = v84 - 1;\n v84 = v85;\n v90 = sub_1200(m, v88);\n v86 += sub_1200(m, v89) + v90;\n if (!v89) break;\n v85 = v89;\n }\n v91 = v222;\n if (v81) {\n v223 = v86 + 1;\n v92 = v81;\n v93 = 0;\n while (1) {\n v94 = v91;\n v95 = v91 - 1;\n v91 = v92;\n v96 = sub_1200(v92 - 1, v94);\n v93 += sub_1200(v92 - 1, v95) + v96;\n if (!v95) break;\n v92 = v95;\n }\n v82 = v81;\n v235 += v93 + v223 + 1;\n do {\n v80 = v211;\n v97 = v82;\n v211 = v82;\n v81 = v80 - 1;\n v82 = v80 - 1;\n v83 = v97 - 1;\n if (v83) goto LABEL_51;\n LABEL_60:\n v235 += 2;\n } while (v81);\n v98 = v247;\n v99 = v235;\n v59 = v255;\n } else {\n v98 = v247;\n v59 = v255;\n v99 = v86 + v235 + 2;\n }\n v261 += v98 + v99 + 1;\n do {\n v55 = v241;\n v100 = v59;\n v241 = v59;\n v58 = v55 - 1;\n v59 = v55 - 1;\n v60 = v100 - 1;\n if (v60) goto LABEL_37;\n LABEL_64:\n v261 += 2;\n } while (v58);\n v101 = v267;\n v102 = v261;\n v10 = v271;\n } else {\n v101 = v267;\n v10 = v271;\n v102 = v261 + v78 + 2;\n }\n v274 += v101 + v102 + 1;\n goto LABEL_67;\n }\n v103 = v278;\n v105 = v280;\n v104 = v274 + v56 + 2;\n } else {\n while (1) {\n v274 += 2;\n if (!v9) break;\n LABEL_67:\n v7 = v264;\n v264 = v10;\n v8 = v10 - 1;\n v9 = v7 - 1;\n v10 = v7 - 1;\n if (v8) goto LABEL_5;\n }\n v103 = v278;\n v104 = v274;\n v105 = v280;\n }\n if (!v105) break;\n v106 = v103;\n v265 = v105;\n v107 = v103 - 1;\n v279 = v104 + 1;\n v275 = 0;\n v108 = v103 - 1;\n v281 = v105;\n v109 = v105 - 1;\n if (v105 == 1) {\n while (1) {\n v275 += 2;\n if (!v107) break;\n LABEL_134:\n v106 = v265;\n v203 = v108;\n v265 = v108;\n v107 = v106 - 1;\n v108 = v106 - 1;\n v109 = v203 - 1;\n if (v109) goto LABEL_72;\n }\n v204 = v279;\n v205 = v275;\n v5 = v281;\n } else {\n LABEL_72:\n v110 = v109;\n v242 = v106;\n v111 = v109 - 1;\n v268 = v109;\n v262 = 0;\n v112 = v109 - 1;\n v272 = v107;\n if (v108) {\n LABEL_73:\n v113 = v108;\n v114 = v111;\n v256 = v111;\n v236 = 0;\n v115 = v108 - 1;\n v212 = v110;\n v116 = v108 - 1;\n v248 = v108;\n if (v114) {\n LABEL_74:\n v224 = v114;\n v117 = v113;\n v118 = v114;\n v119 = 0;\n for (n = v115;; n = v122 - 1) {\n v121 = v118;\n v122 = v118 - 1;\n v118 = v117;\n v123 = sub_1200(n, v121);\n v119 += sub_1200(n, v122) + v123;\n if (!v122) break;\n v117 = v122;\n }\n v124 = v224;\n if (v115) {\n v225 = v119 + 1;\n v125 = v115;\n v126 = 0;\n while (1) {\n v127 = v124;\n v128 = v124 - 1;\n v124 = v125;\n v129 = sub_1200(v125 - 1, v127);\n v126 += sub_1200(v125 - 1, v128) + v129;\n if (!v128) break;\n v125 = v128;\n }\n v116 = v115;\n v236 += v126 + v225 + 1;\n goto LABEL_82;\n }\n v130 = v248;\n v132 = v256;\n v131 = v119 + v236 + 2;\n } else {\n while (1) {\n v236 += 2;\n if (!v115) break;\n LABEL_82:\n v113 = v212;\n v114 = v116 - 1;\n v212 = v116;\n v115 = v113 - 1;\n v116 = v113 - 1;\n if (v114) goto LABEL_74;\n }\n v130 = v248;\n v131 = v236;\n v132 = v256;\n }\n if (v132) {\n v133 = v130;\n v249 = v131 + 1;\n v134 = v130 - 1;\n v213 = v132;\n v237 = 0;\n v135 = v130 - 1;\n v257 = v132;\n v136 = v132 - 1;\n if (v132 == 1) goto LABEL_96;\n LABEL_87:\n v137 = v136;\n v226 = v136;\n v138 = v133;\n v139 = 0;\n for (ii = v134;; ii = v142 - 1) {\n v141 = v137;\n v142 = v137 - 1;\n v137 = v138;\n v143 = sub_1200(ii, v141);\n v139 += sub_1200(ii, v142) + v143;\n if (!v142) break;\n v138 = v142;\n }\n v144 = v226;\n if (v134) {\n v227 = v139 + 1;\n v145 = v134;\n v146 = 0;\n while (1) {\n v147 = v144;\n v148 = v144 - 1;\n v144 = v145;\n v149 = sub_1200(v145 - 1, v147);\n v146 += sub_1200(v145 - 1, v148) + v149;\n if (!v148) break;\n v145 = v148;\n }\n v135 = v134;\n v237 += v146 + v227 + 1;\n do {\n v133 = v213;\n v150 = v135;\n v213 = v135;\n v134 = v133 - 1;\n v135 = v133 - 1;\n v136 = v150 - 1;\n if (v136) goto LABEL_87;\n LABEL_96:\n v237 += 2;\n } while (v134);\n v151 = v249;\n v152 = v237;\n v112 = v257;\n } else {\n v151 = v249;\n v112 = v257;\n v152 = v139 + v237 + 2;\n }\n v262 += v151 + v152 + 1;\n goto LABEL_99;\n }\n v153 = v268;\n v155 = v272;\n v154 = v262 + v131 + 2;\n } else {\n while (1) {\n v262 += 2;\n if (!v111) break;\n LABEL_99:\n v110 = v242;\n v108 = v112 - 1;\n v242 = v112;\n v111 = v110 - 1;\n v112 = v110 - 1;\n if (v108) goto LABEL_73;\n }\n v153 = v268;\n v154 = v262;\n v155 = v272;\n }\n if (v155) {\n v156 = v155;\n v157 = v153 - 1;\n v243 = v155;\n v273 = v155;\n v158 = v153 - 1;\n v269 = v154 + 1;\n v263 = 0;\n v159 = v156 - 1;\n if (!v159) goto LABEL_131;\n LABEL_104:\n v160 = v159;\n v258 = v157;\n v238 = 0;\n v161 = v159 - 1;\n v162 = v157;\n v214 = v153;\n v163 = v159 - 1;\n v250 = v159;\n if (!v162) goto LABEL_114;\n LABEL_105:\n v228 = v162;\n v164 = v160;\n v165 = v162;\n v166 = 0;\n for (jj = v161;; jj = v169 - 1) {\n v168 = v165;\n v169 = v165 - 1;\n v165 = v164;\n v170 = sub_1200(jj, v168);\n v166 += sub_1200(jj, v169) + v170;\n if (!v169) break;\n v164 = v169;\n }\n v171 = v228;\n if (v161) {\n v229 = v166 + 1;\n v172 = v161;\n v173 = 0;\n while (1) {\n v174 = v171;\n v175 = v171 - 1;\n v171 = v172;\n v176 = sub_1200(v172 - 1, v174);\n v173 += sub_1200(v172 - 1, v175) + v176;\n if (!v175) break;\n v172 = v175;\n }\n v163 = v161;\n v238 += v173 + v229 + 1;\n do {\n v160 = v214;\n v162 = v163 - 1;\n v214 = v163;\n v161 = v160 - 1;\n v163 = v160 - 1;\n if (v162) goto LABEL_105;\n LABEL_114:\n v238 += 2;\n } while (v161);\n v177 = v250;\n v178 = v238;\n v179 = v258;\n } else {\n v177 = v250;\n v179 = v258;\n v178 = v166 + v238 + 2;\n }\n if (v179) {\n v180 = v177;\n v251 = v178 + 1;\n v181 = v177 - 1;\n v215 = v179;\n v239 = 0;\n v182 = v177 - 1;\n v259 = v179;\n v183 = v179 - 1;\n if (v179 == 1) goto LABEL_127;\n LABEL_118:\n v184 = v183;\n v230 = v183;\n v185 = v180;\n v186 = 0;\n for (kk = v181;; kk = v189 - 1) {\n v188 = v184;\n v189 = v184 - 1;\n v184 = v185;\n v190 = sub_1200(kk, v188);\n v186 += sub_1200(kk, v189) + v190;\n if (!v189) break;\n v185 = v189;\n }\n v191 = v230;\n if (v181) {\n v231 = v186 + 1;\n v192 = v181;\n v193 = 0;\n while (1) {\n v194 = v191;\n v195 = v191 - 1;\n v191 = v192;\n v196 = sub_1200(v192 - 1, v194);\n v193 += sub_1200(v192 - 1, v195) + v196;\n if (!v195) break;\n v192 = v195;\n }\n v182 = v181;\n v239 += v193 + v231 + 1;\n do {\n v180 = v215;\n v197 = v182;\n v215 = v182;\n v181 = v180 - 1;\n v182 = v180 - 1;\n v183 = v197 - 1;\n if (v183) goto LABEL_118;\n LABEL_127:\n v239 += 2;\n } while (v181);\n v198 = v251;\n v199 = v239;\n v158 = v259;\n } else {\n v198 = v251;\n v158 = v259;\n v199 = v186 + v239 + 2;\n }\n v263 += v198 + v199 + 1;\n do {\n v153 = v243;\n v200 = v158;\n v243 = v158;\n v157 = v153 - 1;\n v158 = v153 - 1;\n v159 = v200 - 1;\n if (v159) goto LABEL_104;\n LABEL_131:\n v263 += 2;\n } while (v157);\n v201 = v269;\n v202 = v263;\n v108 = v273;\n } else {\n v201 = v269;\n v108 = v273;\n v202 = v263 + v178 + 2;\n }\n v275 += v201 + v202 + 1;\n goto LABEL_134;\n }\n v204 = v279;\n v5 = v281;\n v205 = v275 + v154 + 2;\n }\n v277 += v204 + v205 + 1;\n while (1) {\n v2 = v276;\n v206 = v5;\n v276 = v5;\n v4 = v2 - 1;\n v5 = v2 - 1;\n v6 = v206 - 1;\n if (v6) break;\n LABEL_139:\n v277 += 2;\n if (!v4) {\n v207 = v277;\n return (unsigned int)(v207 + 1);\n }\n }\n }\n v207 = v277 + v104 + 2;\n return (unsigned int)(v207 + 1);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(unsigned int a1, unsigned int a2) {\n unsigned int v2;\n long long result;\n unsigned int v4;\n unsigned int v5;\n unsigned int v6;\n unsigned int v7;\n unsigned int v8;\n unsigned int v9;\n unsigned int v10;\n unsigned int v11;\n unsigned int v12;\n unsigned int v13;\n unsigned int v14;\n unsigned int v15;\n unsigned int v16;\n unsigned int v17;\n unsigned int v18;\n unsigned int v19;\n unsigned int v20;\n int v21;\n unsigned int i;\n long long v23;\n unsigned int v24;\n int v25;\n unsigned int v26;\n unsigned int v27;\n int v28;\n long long v29;\n unsigned int v30;\n int v31;\n unsigned int v32;\n int v33;\n unsigned int v34;\n unsigned int v35;\n unsigned int v36;\n unsigned int v37;\n unsigned int v38;\n unsigned int v39;\n unsigned int v40;\n int v41;\n unsigned int j;\n long long v43;\n unsigned int v44;\n int v45;\n unsigned int v46;\n unsigned int v47;\n int v48;\n long long v49;\n unsigned int v50;\n int v51;\n unsigned int v52;\n int v53;\n int v54;\n unsigned int v55;\n int v56;\n unsigned int v57;\n unsigned int v58;\n unsigned int v59;\n unsigned int v60;\n unsigned int v61;\n unsigned int v62;\n unsigned int v63;\n unsigned int v64;\n unsigned int v65;\n int v66;\n unsigned int k;\n long long v68;\n unsigned int v69;\n int v70;\n unsigned int v71;\n unsigned int v72;\n int v73;\n long long v74;\n unsigned int v75;\n int v76;\n unsigned int v77;\n int v78;\n unsigned int v79;\n unsigned int v80;\n unsigned int v81;\n unsigned int v82;\n unsigned int v83;\n unsigned int v84;\n unsigned int v85;\n int v86;\n unsigned int m;\n long long v88;\n unsigned int v89;\n int v90;\n unsigned int v91;\n unsigned int v92;\n int v93;\n long long v94;\n unsigned int v95;\n int v96;\n unsigned int v97;\n int v98;\n int v99;\n unsigned int v100;\n int v101;\n int v102;\n unsigned int v103;\n int v104;\n unsigned int v105;\n unsigned int v106;\n unsigned int v107;\n unsigned int v108;\n unsigned int v109;\n unsigned int v110;\n unsigned int v111;\n unsigned int v112;\n unsigned int v113;\n unsigned int v114;\n unsigned int v115;\n unsigned int v116;\n unsigned int v117;\n unsigned int v118;\n int v119;\n unsigned int n;\n long long v121;\n unsigned int v122;\n int v123;\n unsigned int v124;\n unsigned int v125;\n int v126;\n long long v127;\n unsigned int v128;\n int v129;\n unsigned int v130;\n int v131;\n unsigned int v132;\n unsigned int v133;\n unsigned int v134;\n unsigned int v135;\n unsigned int v136;\n unsigned int v137;\n unsigned int v138;\n int v139;\n unsigned int ii;\n long long v141;\n unsigned int v142;\n int v143;\n unsigned int v144;\n unsigned int v145;\n int v146;\n long long v147;\n unsigned int v148;\n int v149;\n unsigned int v150;\n int v151;\n int v152;\n unsigned int v153;\n int v154;\n unsigned int v155;\n unsigned int v156;\n unsigned int v157;\n unsigned int v158;\n unsigned int v159;\n unsigned int v160;\n unsigned int v161;\n unsigned int v162;\n unsigned int v163;\n unsigned int v164;\n unsigned int v165;\n int v166;\n unsigned int jj;\n long long v168;\n unsigned int v169;\n int v170;\n unsigned int v171;\n unsigned int v172;\n int v173;\n long long v174;\n unsigned int v175;\n int v176;\n unsigned int v177;\n int v178;\n unsigned int v179;\n unsigned int v180;\n unsigned int v181;\n unsigned int v182;\n unsigned int v183;\n unsigned int v184;\n unsigned int v185;\n int v186;\n unsigned int kk;\n long long v188;\n unsigned int v189;\n int v190;\n unsigned int v191;\n unsigned int v192;\n int v193;\n long long v194;\n unsigned int v195;\n int v196;\n unsigned int v197;\n int v198;\n int v199;\n unsigned int v200;\n int v201;\n int v202;\n unsigned int v203;\n int v204;\n int v205;\n unsigned int v206;\n int v207;\n unsigned int v208;\n unsigned int v209;\n unsigned int v210;\n unsigned int v211;\n unsigned int v212;\n unsigned int v213;\n unsigned int v214;\n unsigned int v215;\n unsigned int v216;\n int v217;\n unsigned int v218;\n int v219;\n unsigned int v220;\n int v221;\n unsigned int v222;\n int v223;\n unsigned int v224;\n int v225;\n unsigned int v226;\n int v227;\n unsigned int v228;\n int v229;\n unsigned int v230;\n int v231;\n int v232;\n int v233;\n int v234;\n int v235;\n int v236;\n int v237;\n int v238;\n int v239;\n unsigned int v240;\n unsigned int v241;\n unsigned int v242;\n unsigned int v243;\n unsigned int v244;\n int v245;\n unsigned int v246;\n int v247;\n unsigned int v248;\n int v249;\n unsigned int v250;\n int v251;\n unsigned int v252;\n unsigned int v253;\n unsigned int v254;\n unsigned int v255;\n unsigned int v256;\n unsigned int v257;\n unsigned int v258;\n unsigned int v259;\n int v260;\n int v261;\n int v262;\n int v263;\n unsigned int v264;\n unsigned int v265;\n unsigned int v266;\n int v267;\n unsigned int v268;\n int v269;\n unsigned int v270;\n unsigned int v271;\n unsigned int v272;\n unsigned int v273;\n int v274;\n int v275;\n unsigned int v276;\n int v277;\n unsigned int v278;\n int v279;\n unsigned int v280;\n unsigned int v281;\n if (!a2) return 1LL;\n v2 = a1;\n result = 1LL;\n if (a1) {\n v4 = a1 - 1;\n v277 = 0;\n v276 = a2;\n v5 = a1 - 1;\n v6 = a2 - 1;\n if (a2 == 1) goto LABEL_139;\n while (1) {\n v7 = v6;\n v278 = v6;\n v8 = v4;\n v9 = v7 - 1;\n v274 = 0;\n v280 = v4;\n v10 = v7 - 1;\n v264 = v2;\n if (v4) {\n LABEL_5:\n v11 = v8;\n v12 = v9;\n v240 = v7;\n v13 = v8 - 1;\n v266 = v8;\n v260 = 0;\n v14 = v8 - 1;\n v270 = v9;\n if (v9) {\n LABEL_6:\n v15 = v12;\n v16 = v13;\n v252 = v13;\n v232 = 0;\n v17 = v12 - 1;\n v208 = v11;\n v18 = v12 - 1;\n v244 = v12;\n if (v16) {\n LABEL_7:\n v216 = v16;\n v19 = v15;\n v20 = v16;\n v21 = 0;\n for (i = v17;; i = v24 - 1) {\n v23 = v20;\n v24 = v20 - 1;\n v20 = v19;\n v25 = func0(i, v23);\n v21 += func0(i, v24) + v25;\n if (!v24) break;\n v19 = v24;\n }\n v26 = v216;\n if (v17) {\n v217 = v21 + 1;\n v27 = v17;\n v28 = 0;\n while (1) {\n v29 = v26;\n v30 = v26 - 1;\n v26 = v27;\n v31 = func0(v27 - 1, v29);\n v28 += func0(v27 - 1, v30) + v31;\n if (!v30) break;\n v27 = v30;\n }\n v18 = v17;\n v232 += v28 + v217 + 1;\n goto LABEL_15;\n }\n v32 = v244;\n v34 = v252;\n v33 = v21 + v232 + 2;\n } else {\n while (1) {\n v232 += 2;\n if (!v17) break;\n LABEL_15:\n v15 = v208;\n v16 = v18 - 1;\n v208 = v18;\n v17 = v15 - 1;\n v18 = v15 - 1;\n if (v16) goto LABEL_7;\n }\n v32 = v244;\n v33 = v232;\n v34 = v252;\n }\n if (v34) {\n v35 = v32;\n v245 = v33 + 1;\n v36 = v32 - 1;\n v209 = v34;\n v233 = 0;\n v37 = v32 - 1;\n v253 = v34;\n v38 = v34 - 1;\n if (v34 == 1) goto LABEL_29;\n LABEL_20:\n v39 = v38;\n v218 = v38;\n v40 = v35;\n v41 = 0;\n for (j = v36;; j = v44 - 1) {\n v43 = v39;\n v44 = v39 - 1;\n v39 = v40;\n v45 = func0(j, v43);\n v41 += func0(j, v44) + v45;\n if (!v44) break;\n v40 = v44;\n }\n v46 = v218;\n if (v36) {\n v219 = v41 + 1;\n v47 = v36;\n v48 = 0;\n while (1) {\n v49 = v46;\n v50 = v46 - 1;\n v46 = v47;\n v51 = func0(v47 - 1, v49);\n v48 += func0(v47 - 1, v50) + v51;\n if (!v50) break;\n v47 = v50;\n }\n v37 = v36;\n v233 += v48 + v219 + 1;\n do {\n v35 = v209;\n v52 = v37;\n v209 = v37;\n v36 = v35 - 1;\n v37 = v35 - 1;\n v38 = v52 - 1;\n if (v38) goto LABEL_20;\n LABEL_29:\n v233 += 2;\n } while (v36);\n v53 = v245;\n v54 = v233;\n v14 = v253;\n } else {\n v53 = v245;\n v14 = v253;\n v54 = v41 + v233 + 2;\n }\n v260 += v53 + v54 + 1;\n goto LABEL_32;\n }\n v55 = v266;\n v57 = v270;\n v56 = v260 + v33 + 2;\n } else {\n while (1) {\n v260 += 2;\n if (!v13) break;\n LABEL_32:\n v11 = v240;\n v12 = v14 - 1;\n v240 = v14;\n v13 = v11 - 1;\n v14 = v11 - 1;\n if (v12) goto LABEL_6;\n }\n v55 = v266;\n v56 = v260;\n v57 = v270;\n }\n if (v57) {\n v58 = v55 - 1;\n v267 = v56 + 1;\n v241 = v57;\n v59 = v55 - 1;\n v261 = 0;\n v271 = v57;\n v60 = v57 - 1;\n if (v57 == 1) goto LABEL_64;\n LABEL_37:\n v61 = v60;\n v254 = v58;\n v62 = v60 - 1;\n v210 = v55;\n v246 = v60;\n v63 = v60 - 1;\n v234 = 0;\n if (!v59) goto LABEL_47;\n LABEL_38:\n v220 = v59;\n v64 = v61;\n v65 = v59;\n v66 = 0;\n for (k = v62;; k = v69 - 1) {\n v68 = v65;\n v69 = v65 - 1;\n v65 = v64;\n v70 = func0(k, v68);\n v66 += func0(k, v69) + v70;\n if (!v69) break;\n v64 = v69;\n }\n v71 = v220;\n if (v62) {\n v221 = v66 + 1;\n v72 = v62;\n v73 = 0;\n while (1) {\n v74 = v71;\n v75 = v71 - 1;\n v71 = v72;\n v76 = func0(v72 - 1, v74);\n v73 += func0(v72 - 1, v75) + v76;\n if (!v75) break;\n v72 = v75;\n }\n v63 = v62;\n v234 += v73 + v221 + 1;\n do {\n v61 = v210;\n v59 = v63 - 1;\n v210 = v63;\n v62 = v61 - 1;\n v63 = v61 - 1;\n if (v59) goto LABEL_38;\n LABEL_47:\n v234 += 2;\n } while (v62);\n v77 = v246;\n v78 = v234;\n v79 = v254;\n } else {\n v77 = v246;\n v79 = v254;\n v78 = v66 + v234 + 2;\n }\n if (v79) {\n v80 = v77;\n v247 = v78 + 1;\n v81 = v77 - 1;\n v211 = v79;\n v235 = 0;\n v82 = v77 - 1;\n v255 = v79;\n v83 = v79 - 1;\n if (v79 == 1) goto LABEL_60;\n LABEL_51:\n v84 = v83;\n v222 = v83;\n v85 = v80;\n v86 = 0;\n for (m = v81;; m = v89 - 1) {\n v88 = v84;\n v89 = v84 - 1;\n v84 = v85;\n v90 = func0(m, v88);\n v86 += func0(m, v89) + v90;\n if (!v89) break;\n v85 = v89;\n }\n v91 = v222;\n if (v81) {\n v223 = v86 + 1;\n v92 = v81;\n v93 = 0;\n while (1) {\n v94 = v91;\n v95 = v91 - 1;\n v91 = v92;\n v96 = func0(v92 - 1, v94);\n v93 += func0(v92 - 1, v95) + v96;\n if (!v95) break;\n v92 = v95;\n }\n v82 = v81;\n v235 += v93 + v223 + 1;\n do {\n v80 = v211;\n v97 = v82;\n v211 = v82;\n v81 = v80 - 1;\n v82 = v80 - 1;\n v83 = v97 - 1;\n if (v83) goto LABEL_51;\n LABEL_60:\n v235 += 2;\n } while (v81);\n v98 = v247;\n v99 = v235;\n v59 = v255;\n } else {\n v98 = v247;\n v59 = v255;\n v99 = v86 + v235 + 2;\n }\n v261 += v98 + v99 + 1;\n do {\n v55 = v241;\n v100 = v59;\n v241 = v59;\n v58 = v55 - 1;\n v59 = v55 - 1;\n v60 = v100 - 1;\n if (v60) goto LABEL_37;\n LABEL_64:\n v261 += 2;\n } while (v58);\n v101 = v267;\n v102 = v261;\n v10 = v271;\n } else {\n v101 = v267;\n v10 = v271;\n v102 = v261 + v78 + 2;\n }\n v274 += v101 + v102 + 1;\n goto LABEL_67;\n }\n v103 = v278;\n v105 = v280;\n v104 = v274 + v56 + 2;\n } else {\n while (1) {\n v274 += 2;\n if (!v9) break;\n LABEL_67:\n v7 = v264;\n v264 = v10;\n v8 = v10 - 1;\n v9 = v7 - 1;\n v10 = v7 - 1;\n if (v8) goto LABEL_5;\n }\n v103 = v278;\n v104 = v274;\n v105 = v280;\n }\n if (!v105) break;\n v106 = v103;\n v265 = v105;\n v107 = v103 - 1;\n v279 = v104 + 1;\n v275 = 0;\n v108 = v103 - 1;\n v281 = v105;\n v109 = v105 - 1;\n if (v105 == 1) {\n while (1) {\n v275 += 2;\n if (!v107) break;\n LABEL_134:\n v106 = v265;\n v203 = v108;\n v265 = v108;\n v107 = v106 - 1;\n v108 = v106 - 1;\n v109 = v203 - 1;\n if (v109) goto LABEL_72;\n }\n v204 = v279;\n v205 = v275;\n v5 = v281;\n } else {\n LABEL_72:\n v110 = v109;\n v242 = v106;\n v111 = v109 - 1;\n v268 = v109;\n v262 = 0;\n v112 = v109 - 1;\n v272 = v107;\n if (v108) {\n LABEL_73:\n v113 = v108;\n v114 = v111;\n v256 = v111;\n v236 = 0;\n v115 = v108 - 1;\n v212 = v110;\n v116 = v108 - 1;\n v248 = v108;\n if (v114) {\n LABEL_74:\n v224 = v114;\n v117 = v113;\n v118 = v114;\n v119 = 0;\n for (n = v115;; n = v122 - 1) {\n v121 = v118;\n v122 = v118 - 1;\n v118 = v117;\n v123 = func0(n, v121);\n v119 += func0(n, v122) + v123;\n if (!v122) break;\n v117 = v122;\n }\n v124 = v224;\n if (v115) {\n v225 = v119 + 1;\n v125 = v115;\n v126 = 0;\n while (1) {\n v127 = v124;\n v128 = v124 - 1;\n v124 = v125;\n v129 = func0(v125 - 1, v127);\n v126 += func0(v125 - 1, v128) + v129;\n if (!v128) break;\n v125 = v128;\n }\n v116 = v115;\n v236 += v126 + v225 + 1;\n goto LABEL_82;\n }\n v130 = v248;\n v132 = v256;\n v131 = v119 + v236 + 2;\n } else {\n while (1) {\n v236 += 2;\n if (!v115) break;\n LABEL_82:\n v113 = v212;\n v114 = v116 - 1;\n v212 = v116;\n v115 = v113 - 1;\n v116 = v113 - 1;\n if (v114) goto LABEL_74;\n }\n v130 = v248;\n v131 = v236;\n v132 = v256;\n }\n if (v132) {\n v133 = v130;\n v249 = v131 + 1;\n v134 = v130 - 1;\n v213 = v132;\n v237 = 0;\n v135 = v130 - 1;\n v257 = v132;\n v136 = v132 - 1;\n if (v132 == 1) goto LABEL_96;\n LABEL_87:\n v137 = v136;\n v226 = v136;\n v138 = v133;\n v139 = 0;\n for (ii = v134;; ii = v142 - 1) {\n v141 = v137;\n v142 = v137 - 1;\n v137 = v138;\n v143 = func0(ii, v141);\n v139 += func0(ii, v142) + v143;\n if (!v142) break;\n v138 = v142;\n }\n v144 = v226;\n if (v134) {\n v227 = v139 + 1;\n v145 = v134;\n v146 = 0;\n while (1) {\n v147 = v144;\n v148 = v144 - 1;\n v144 = v145;\n v149 = func0(v145 - 1, v147);\n v146 += func0(v145 - 1, v148) + v149;\n if (!v148) break;\n v145 = v148;\n }\n v135 = v134;\n v237 += v146 + v227 + 1;\n do {\n v133 = v213;\n v150 = v135;\n v213 = v135;\n v134 = v133 - 1;\n v135 = v133 - 1;\n v136 = v150 - 1;\n if (v136) goto LABEL_87;\n LABEL_96:\n v237 += 2;\n } while (v134);\n v151 = v249;\n v152 = v237;\n v112 = v257;\n } else {\n v151 = v249;\n v112 = v257;\n v152 = v139 + v237 + 2;\n }\n v262 += v151 + v152 + 1;\n goto LABEL_99;\n }\n v153 = v268;\n v155 = v272;\n v154 = v262 + v131 + 2;\n } else {\n while (1) {\n v262 += 2;\n if (!v111) break;\n LABEL_99:\n v110 = v242;\n v108 = v112 - 1;\n v242 = v112;\n v111 = v110 - 1;\n v112 = v110 - 1;\n if (v108) goto LABEL_73;\n }\n v153 = v268;\n v154 = v262;\n v155 = v272;\n }\n if (v155) {\n v156 = v155;\n v157 = v153 - 1;\n v243 = v155;\n v273 = v155;\n v158 = v153 - 1;\n v269 = v154 + 1;\n v263 = 0;\n v159 = v156 - 1;\n if (!v159) goto LABEL_131;\n LABEL_104:\n v160 = v159;\n v258 = v157;\n v238 = 0;\n v161 = v159 - 1;\n v162 = v157;\n v214 = v153;\n v163 = v159 - 1;\n v250 = v159;\n if (!v162) goto LABEL_114;\n LABEL_105:\n v228 = v162;\n v164 = v160;\n v165 = v162;\n v166 = 0;\n for (jj = v161;; jj = v169 - 1) {\n v168 = v165;\n v169 = v165 - 1;\n v165 = v164;\n v170 = func0(jj, v168);\n v166 += func0(jj, v169) + v170;\n if (!v169) break;\n v164 = v169;\n }\n v171 = v228;\n if (v161) {\n v229 = v166 + 1;\n v172 = v161;\n v173 = 0;\n while (1) {\n v174 = v171;\n v175 = v171 - 1;\n v171 = v172;\n v176 = func0(v172 - 1, v174);\n v173 += func0(v172 - 1, v175) + v176;\n if (!v175) break;\n v172 = v175;\n }\n v163 = v161;\n v238 += v173 + v229 + 1;\n do {\n v160 = v214;\n v162 = v163 - 1;\n v214 = v163;\n v161 = v160 - 1;\n v163 = v160 - 1;\n if (v162) goto LABEL_105;\n LABEL_114:\n v238 += 2;\n } while (v161);\n v177 = v250;\n v178 = v238;\n v179 = v258;\n } else {\n v177 = v250;\n v179 = v258;\n v178 = v166 + v238 + 2;\n }\n if (v179) {\n v180 = v177;\n v251 = v178 + 1;\n v181 = v177 - 1;\n v215 = v179;\n v239 = 0;\n v182 = v177 - 1;\n v259 = v179;\n v183 = v179 - 1;\n if (v179 == 1) goto LABEL_127;\n LABEL_118:\n v184 = v183;\n v230 = v183;\n v185 = v180;\n v186 = 0;\n for (kk = v181;; kk = v189 - 1) {\n v188 = v184;\n v189 = v184 - 1;\n v184 = v185;\n v190 = func0(kk, v188);\n v186 += func0(kk, v189) + v190;\n if (!v189) break;\n v185 = v189;\n }\n v191 = v230;\n if (v181) {\n v231 = v186 + 1;\n v192 = v181;\n v193 = 0;\n while (1) {\n v194 = v191;\n v195 = v191 - 1;\n v191 = v192;\n v196 = func0(v192 - 1, v194);\n v193 += func0(v192 - 1, v195) + v196;\n if (!v195) break;\n v192 = v195;\n }\n v182 = v181;\n v239 += v193 + v231 + 1;\n do {\n v180 = v215;\n v197 = v182;\n v215 = v182;\n v181 = v180 - 1;\n v182 = v180 - 1;\n v183 = v197 - 1;\n if (v183) goto LABEL_118;\n LABEL_127:\n v239 += 2;\n } while (v181);\n v198 = v251;\n v199 = v239;\n v158 = v259;\n } else {\n v198 = v251;\n v158 = v259;\n v199 = v186 + v239 + 2;\n }\n v263 += v198 + v199 + 1;\n do {\n v153 = v243;\n v200 = v158;\n v243 = v158;\n v157 = v153 - 1;\n v158 = v153 - 1;\n v159 = v200 - 1;\n if (v159) goto LABEL_104;\n LABEL_131:\n v263 += 2;\n } while (v157);\n v201 = v269;\n v202 = v263;\n v108 = v273;\n } else {\n v201 = v269;\n v108 = v273;\n v202 = v263 + v178 + 2;\n }\n v275 += v201 + v202 + 1;\n goto LABEL_134;\n }\n v204 = v279;\n v5 = v281;\n v205 = v275 + v154 + 2;\n }\n v277 += v204 + v205 + 1;\n while (1) {\n v2 = v276;\n v206 = v5;\n v276 = v5;\n v4 = v2 - 1;\n v5 = v2 - 1;\n v6 = v206 - 1;\n if (v6) break;\n LABEL_139:\n v277 += 2;\n if (!v4) {\n v207 = v277;\n return (unsigned int)(v207 + 1);\n }\n }\n }\n v207 = v277 + v104 + 2;\n return (unsigned int)(v207 + 1);\n }\n return result;\n}" + }, + { + "index": 935, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int number) {\n int total = 0;\n total = (number * (number + 1) * (2 * number + 1)) / 6;\n return total;\n}", + "test": "int main() {\n\n assert(func0(6) == 91);\n\n assert(func0(7) == 140);\n\n assert(func0(12) == 650);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmovl $0x0,-0x4(%rbp)\nmov -0x14(%rbp),%eax\nadd $0x1,%eax\nimul -0x14(%rbp),%eax\nmov -0x14(%rbp),%edx\nadd %edx,%edx\nadd $0x1,%edx\nimul %edx,%eax\nmovslq %eax,%rdx\nimul $0x2aaaaaab,%rdx,%rdx\nshr $0x20,%rdx\nsar $0x1f,%eax\nmov %edx,%ecx\nsub %eax,%ecx\nmov %ecx,%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_4], 0\nmov eax, [rbp+var_14]\nadd eax, 1\nimul eax, [rbp+var_14]\nmov edx, [rbp+var_14]\nadd edx, edx\nadd edx, 1\nimul eax, edx\nmovsxd rdx, eax\nimul rdx, 2AAAAAABh\nmov rcx, rdx\nshr rcx, 20h\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n return (unsigned int)((2 * a1 + 1) * a1 * (a1 + 1) / 6);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_4], 0\nmov eax, [rbp+var_14]\nadd eax, 1\nimul eax, [rbp+var_14]\nmov edx, [rbp+var_14]\nadd edx, edx\nadd edx, 1\nimul eax, edx\nmovsxd rdx, eax\nimul rdx, 2AAAAAABh\nmov rcx, rdx\nshr rcx, 20h\ncdq\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n return (unsigned int)((2 * a1 + 1) * a1 * (a1 + 1) / 6);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n return (unsigned int)((2 * a1 + 1) * a1 * (a1 + 1) / 6);\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n return (unsigned int)((2 * a1 + 1) * a1 * (a1 + 1) / 6);\n}" + }, + { + "index": 936, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int key;\n\n int value;\n\n} pair;\n\n\n\n", + "func": "pair* func0(pair test_list[], int test_list_size, int ord_list[],\n int ord_list_size) {\n pair* res = (pair*)malloc(ord_list_size * sizeof(pair));\n int i, j;\n for (i = 0; i < ord_list_size; i++) {\n for (j = 0; j < test_list_size; j++) {\n if (ord_list[i] == test_list[j].key) {\n res[i].key = test_list[j].key;\n res[i].value = test_list[j].value;\n break;\n }\n }\n }\n return res;\n}", + "test": "int main() {\n\n pair test_list1[] = {{4, 3}, {1, 9}, {2, 10}, {3, 2}};\n\n int ord_list1[] = {1, 4, 2, 3};\n\n pair *result1 = func0(test_list1, 4, ord_list1, 4);\n\n assert((result1[0].key == 1 && result1[0].value == 9) &&\n\n (result1[1].key == 4 && result1[1].value == 3) &&\n\n (result1[2].key == 2 && result1[2].value == 10) &&\n\n (result1[3].key == 3 && result1[3].value == 2));\n\n\n\n pair test_list2[] = {{5, 4}, {2, 10}, {3, 11}, {4, 3}};\n\n int ord_list2[] = {3, 4, 2, 3};\n\n pair *result2 = func0(test_list2, 4, ord_list2, 4);\n\n assert((result2[0].key == 3 && result2[0].value == 11) &&\n\n (result2[1].key == 4 && result2[1].value == 3) &&\n\n (result2[2].key == 2 && result2[2].value == 10) &&\n\n (result2[3].key == 3 && result2[3].value == 11));\n\n\n\n pair test_list3[] = {{6, 3}, {3, 8}, {5, 7}, {2, 4}};\n\n int ord_list3[] = {2, 5, 3, 6};\n\n pair *result3 = func0(test_list3, 4, ord_list3, 4);\n\n assert((result3[0].key == 2 && result3[0].value == 4) &&\n\n (result3[1].key == 5 && result3[1].value == 7) &&\n\n (result3[2].key == 3 && result3[2].value == 8) &&\n\n (result3[3].key == 6 && result3[3].value == 3));\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %ecx,-0x20(%rbp)\nmov -0x20(%rbp),%eax\ncltq\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 1090 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0x10(%rbp)\njmpq 1272 \nmovl $0x0,-0xc(%rbp)\njmpq 1262 \nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 125e \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0x10(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0x10(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nmov 0x4(%rax),%eax\nmov %eax,0x4(%rdx)\njmp 126e \naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11d0 \naddl $0x1,-0x10(%rbp)\nmov -0x10(%rbp),%eax\ncmp -0x20(%rbp),%eax\njl 11c4 \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov eax, [rbp+var_20]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_10], 0\njmp loc_1272\nloc_11C4:\nmov [rbp+var_C], 0\njmp loc_1262\nloc_11D0:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_125E\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax+4]\nmov [rdx+4], eax\njmp short loc_126E\nloc_125E:\nadd [rbp+var_C], 1\nloc_1262:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl loc_11D0\nloc_126E:\nadd [rbp+var_10], 1\nloc_1272:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_20]\njl loc_11C4\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, __int64 a3, int a4)\n{\n int i; // [rsp+20h] [rbp-10h]\n int j; // [rsp+24h] [rbp-Ch]\n _DWORD *v9; // [rsp+28h] [rbp-8h]\n\n v9 = malloc(8LL * a4);\n for ( i = 0; i < a4; ++i )\n {\n for ( j = 0; j < a2; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a3) == *(_DWORD *)(8LL * j + a1) )\n {\n v9[2 * i] = *(_DWORD *)(8LL * j + a1);\n v9[2 * i + 1] = *(_DWORD *)(8LL * j + a1 + 4);\n break;\n }\n }\n }\n return v9;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov eax, [rbp+var_20]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_10], 0\njmp loc_1272\nloc_11C4:\nmov [rbp+var_C], 0\njmp loc_1262\nloc_11D0:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_C]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_125E\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov edx, [rbp+var_10]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmov eax, [rax+4]\nmov [rdx+4], eax\njmp short loc_126E\nloc_125E:\nadd [rbp+var_C], 1\nloc_1262:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl loc_11D0\nloc_126E:\nadd [rbp+var_10], 1\nloc_1272:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_20]\njl loc_11C4\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1189(__int64 a1, int a2, __int64 a3, int a4)\n{\n int i; // [rsp+20h] [rbp-10h]\n int j; // [rsp+24h] [rbp-Ch]\n _DWORD *v9; // [rsp+28h] [rbp-8h]\n\n v9 = malloc(8LL * a4);\n for ( i = 0; i < a4; ++i )\n {\n for ( j = 0; j < a2; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a3) == *(_DWORD *)(8LL * j + a1) )\n {\n v9[2 * i] = *(_DWORD *)(8LL * j + a1);\n v9[2 * i + 1] = *(_DWORD *)(8LL * j + a1 + 4);\n break;\n }\n }\n }\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1189(long long a1, int a2, long long a3, int a4) {\n int i;\n int j;\n uint32_t *v9;\n v9 = malloc(8LL * a4);\n for (i = 0; i < a4; ++i) {\n for (j = 0; j < a2; ++j) {\n if (*(uint32_t *)(4LL * i + a3) == *(uint32_t *)(8LL * j + a1)) {\n v9[2 * i] = *(uint32_t *)(8LL * j + a1);\n v9[2 * i + 1] = *(uint32_t *)(8LL * j + a1 + 4);\n break;\n }\n }\n }\n return v9;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, long long a3, int a4) {\n int i;\n int j;\n uint32_t *v9;\n v9 = malloc(8LL * a4);\n for (i = 0; i < a4; ++i) {\n for (j = 0; j < a2; ++j) {\n if (*(uint32_t *)(4LL * i + a3) == *(uint32_t *)(8LL * j + a1)) {\n v9[2 * i] = *(uint32_t *)(8LL * j + a1);\n v9[2 * i + 1] = *(uint32_t *)(8LL * j + a1 + 4);\n break;\n }\n }\n }\n return v9;\n}" + }, + { + "index": 936, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int key;\n\n int value;\n\n} pair;\n\n\n\n", + "func": "pair* func0(pair test_list[], int test_list_size, int ord_list[],\n int ord_list_size) {\n pair* res = (pair*)malloc(ord_list_size * sizeof(pair));\n int i, j;\n for (i = 0; i < ord_list_size; i++) {\n for (j = 0; j < test_list_size; j++) {\n if (ord_list[i] == test_list[j].key) {\n res[i].key = test_list[j].key;\n res[i].value = test_list[j].value;\n break;\n }\n }\n }\n return res;\n}", + "test": "int main() {\n\n pair test_list1[] = {{4, 3}, {1, 9}, {2, 10}, {3, 2}};\n\n int ord_list1[] = {1, 4, 2, 3};\n\n pair *result1 = func0(test_list1, 4, ord_list1, 4);\n\n assert((result1[0].key == 1 && result1[0].value == 9) &&\n\n (result1[1].key == 4 && result1[1].value == 3) &&\n\n (result1[2].key == 2 && result1[2].value == 10) &&\n\n (result1[3].key == 3 && result1[3].value == 2));\n\n\n\n pair test_list2[] = {{5, 4}, {2, 10}, {3, 11}, {4, 3}};\n\n int ord_list2[] = {3, 4, 2, 3};\n\n pair *result2 = func0(test_list2, 4, ord_list2, 4);\n\n assert((result2[0].key == 3 && result2[0].value == 11) &&\n\n (result2[1].key == 4 && result2[1].value == 3) &&\n\n (result2[2].key == 2 && result2[2].value == 10) &&\n\n (result2[3].key == 3 && result2[3].value == 11));\n\n\n\n pair test_list3[] = {{6, 3}, {3, 8}, {5, 7}, {2, 4}};\n\n int ord_list3[] = {2, 5, 3, 6};\n\n pair *result3 = func0(test_list3, 4, ord_list3, 4);\n\n assert((result3[0].key == 2 && result3[0].value == 4) &&\n\n (result3[1].key == 5 && result3[1].value == 7) &&\n\n (result3[2].key == 3 && result3[2].value == 8) &&\n\n (result3[3].key == 6 && result3[3].value == 3));\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%r12\nmov %esi,%ebx\nmov %rdx,%rbp\nmov %ecx,%r13d\nmovslq %ecx,%rdi\nshl $0x3,%rdi\ncallq 1090 \ntest %r13d,%r13d\njle 11ff \nlea -0x1(%r13),%r10d\nmov %r12,%r11\nlea -0x1(%rbx),%edx\nlea 0x8(%r12,%rdx,8),%r8\nmov $0x0,%r9d\njmp 11e2 \nmov %ecx,(%rax,%r9,8)\nmov 0x4(%rdx),%edx\nmov %edx,0x4(%rax,%r9,8)\nlea 0x1(%r9),%rdx\ncmp %r10,%r9\nje 11ff \nmov %rdx,%r9\ntest %ebx,%ebx\njle 11d6 \nmov 0x0(%rbp,%r9,4),%esi\nmov %r11,%rdx\nmov (%rdx),%ecx\ncmp %ecx,%esi\nje 11ca \nadd $0x8,%rdx\ncmp %r8,%rdx\njne 11ee \njmp 11d6 \nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbp, rdi\nmov ebx, esi\nmov r12, rdx\nmov r14d, ecx\nmovsxd r13, ecx\nlea rdi, ds:0[r13*8]; size\ncall _malloc\ntest r14d, r14d\njle short loc_11F6\nmovsxd rdx, ebx\nlea rdi, [rbp+rdx*8+0]\nmov r8d, 0\njmp short loc_11DA\nloc_11C5:\nmov [rax+r8*8], ecx\nmov edx, [rdx+4]\nmov [rax+r8*8+4], edx\nloc_11D1:\nadd r8, 1\ncmp r13, r8\njz short loc_11F6\nloc_11DA:\ntest ebx, ebx\njle short loc_11D1\nmov esi, [r12+r8*4]\nmov rdx, rbp\nloc_11E5:\nmov ecx, [rdx]\ncmp esi, ecx\njz short loc_11C5\nadd rdx, 8\ncmp rdx, rdi\njnz short loc_11E5\njmp short loc_11D1\nloc_11F6:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(_DWORD *a1, int a2, __int64 a3, int a4)\n{\n __int64 v6; // r13\n _DWORD *result; // rax\n __int64 v8; // r8\n _DWORD *v9; // rdx\n\n v6 = a4;\n result = malloc(8LL * a4);\n if ( a4 > 0 )\n {\n v8 = 0LL;\n do\n {\n if ( a2 > 0 )\n {\n v9 = a1;\n while ( *(_DWORD *)(a3 + 4 * v8) != *v9 )\n {\n v9 += 2;\n if ( v9 == &a1[2 * a2] )\n goto LABEL_4;\n }\n result[2 * v8] = *v9;\n result[2 * v8 + 1] = v9[1];\n }\nLABEL_4:\n ++v8;\n }\n while ( v6 != v8 );\n }\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbp, rdi\nmov ebx, esi\nmov r12, rdx\nmov r14d, ecx\nmovsxd r13, ecx\nlea rdi, ds:0[r13*8]; size\ncall _malloc\ntest r14d, r14d\njle short loc_11F6\nmovsxd rdx, ebx\nlea rdi, [rbp+rdx*8+0]\nmov r8d, 0\njmp short loc_11DA\nloc_11C5:\nmov [rax+r8*8], ecx\nmov edx, [rdx+4]\nmov [rax+r8*8+4], edx\nloc_11D1:\nadd r8, 1\ncmp r13, r8\njz short loc_11F6\nloc_11DA:\ntest ebx, ebx\njle short loc_11D1\nmov esi, [r12+r8*4]\nmov rdx, rbp\nloc_11E5:\nmov ecx, [rdx]\ncmp esi, ecx\njz short loc_11C5\nadd rdx, 8\ncmp rdx, rdi\njnz short loc_11E5\njmp short loc_11D1\nloc_11F6:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1189(_DWORD *a1, int a2, __int64 a3, int a4)\n{\n __int64 v6; // r13\n _DWORD *result; // rax\n __int64 v8; // r8\n _DWORD *v9; // rdx\n\n v6 = a4;\n result = malloc(8LL * a4);\n if ( a4 > 0 )\n {\n v8 = 0LL;\n do\n {\n if ( a2 > 0 )\n {\n v9 = a1;\n while ( *(_DWORD *)(a3 + 4 * v8) != *v9 )\n {\n v9 += 2;\n if ( v9 == &a1[2 * a2] )\n goto LABEL_4;\n }\n result[2 * v8] = *v9;\n result[2 * v8 + 1] = v9[1];\n }\nLABEL_4:\n ++v8;\n }\n while ( v6 != v8 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1189(uint32_t *a1, int a2, long long a3, int a4) {\n long long v6;\n uint32_t *result;\n long long v8;\n uint32_t *v9;\n v6 = a4;\n result = malloc(8LL * a4);\n if (a4 > 0) {\n v8 = 0LL;\n do {\n if (a2 > 0) {\n v9 = a1;\n while (*(uint32_t *)(a3 + 4 * v8) != *v9) {\n v9 += 2;\n if (v9 == &a1[2 * a2]) goto LABEL_4;\n }\n result[2 * v8] = *v9;\n result[2 * v8 + 1] = v9[1];\n }\n LABEL_4:\n ++v8;\n } while (v6 != v8);\n }\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(uint32_t *a1, int a2, long long a3, int a4) {\n long long v6;\n uint32_t *result;\n long long v8;\n uint32_t *v9;\n v6 = a4;\n result = malloc(8LL * a4);\n if (a4 > 0) {\n v8 = 0LL;\n do {\n if (a2 > 0) {\n v9 = a1;\n while (*(uint32_t *)(a3 + 4 * v8) != *v9) {\n v9 += 2;\n if (v9 == &a1[2 * a2]) goto LABEL_4;\n }\n result[2 * v8] = *v9;\n result[2 * v8 + 1] = v9[1];\n }\n LABEL_4:\n ++v8;\n } while (v6 != v8);\n }\n return result;\n}" + }, + { + "index": 936, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int key;\n\n int value;\n\n} pair;\n\n\n\n", + "func": "pair* func0(pair test_list[], int test_list_size, int ord_list[],\n int ord_list_size) {\n pair* res = (pair*)malloc(ord_list_size * sizeof(pair));\n int i, j;\n for (i = 0; i < ord_list_size; i++) {\n for (j = 0; j < test_list_size; j++) {\n if (ord_list[i] == test_list[j].key) {\n res[i].key = test_list[j].key;\n res[i].value = test_list[j].value;\n break;\n }\n }\n }\n return res;\n}", + "test": "int main() {\n\n pair test_list1[] = {{4, 3}, {1, 9}, {2, 10}, {3, 2}};\n\n int ord_list1[] = {1, 4, 2, 3};\n\n pair *result1 = func0(test_list1, 4, ord_list1, 4);\n\n assert((result1[0].key == 1 && result1[0].value == 9) &&\n\n (result1[1].key == 4 && result1[1].value == 3) &&\n\n (result1[2].key == 2 && result1[2].value == 10) &&\n\n (result1[3].key == 3 && result1[3].value == 2));\n\n\n\n pair test_list2[] = {{5, 4}, {2, 10}, {3, 11}, {4, 3}};\n\n int ord_list2[] = {3, 4, 2, 3};\n\n pair *result2 = func0(test_list2, 4, ord_list2, 4);\n\n assert((result2[0].key == 3 && result2[0].value == 11) &&\n\n (result2[1].key == 4 && result2[1].value == 3) &&\n\n (result2[2].key == 2 && result2[2].value == 10) &&\n\n (result2[3].key == 3 && result2[3].value == 11));\n\n\n\n pair test_list3[] = {{6, 3}, {3, 8}, {5, 7}, {2, 4}};\n\n int ord_list3[] = {2, 5, 3, 6};\n\n pair *result3 = func0(test_list3, 4, ord_list3, 4);\n\n assert((result3[0].key == 2 && result3[0].value == 4) &&\n\n (result3[1].key == 5 && result3[1].value == 7) &&\n\n (result3[2].key == 3 && result3[2].value == 8) &&\n\n (result3[3].key == 6 && result3[3].value == 3));\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\nmov %rdx,%r12\npush %rbp\nmov %rdi,%rbp\nmovslq %ecx,%rdi\npush %rbx\nmov %rdi,%r13\nshl $0x3,%rdi\nmov %esi,%ebx\nsub $0x8,%rsp\ncallq 1090 \ntest %r13d,%r13d\njle 14c0 \nlea -0x1(%rbx),%ecx\nlea -0x1(%r13),%edx\nxor %r9d,%r9d\nlea 0x8(%rbp,%rcx,8),%r8\nnopl 0x0(%rax)\ntest %ebx,%ebx\njle 14a9 \nmov (%r12,%r9,4),%edi\nmov %rbp,%rcx\njmp 1499 \nnopl (%rax)\nadd $0x8,%rcx\ncmp %r8,%rcx\nje 14a9 \ncmp (%rcx),%edi\njne 1490 \nmov 0x4(%rcx),%ecx\nmov %edi,(%rax,%r9,8)\nmov %ecx,0x4(%rax,%r9,8)\nlea 0x1(%r9),%rcx\ncmp %rdx,%r9\nje 14c0 \nmov %rcx,%r9\njmp 1480 \nnopw 0x0(%rax,%rax,1)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\nmovsxd r13, esi\npush r12\nmovsxd r12, ecx\npush rbp\nmov rbp, rdx\npush rbx\nmov rbx, rdi\nlea rdi, ds:0[r12*8]; size\ncall _malloc\nxor edi, edi\ntest r12d, r12d\njle short loc_13FA\nloc_13EC:\ntest r13d, r13d\njg short loc_1403\nadd rdi, 1\ncmp r12, rdi\njnz short loc_13EC\nloc_13FA:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1403:\nlea rsi, [rbx+r13*8]\nnop word ptr [rax+rax+00000000h]\nloc_1410:\nmov ecx, [rbp+rdi*4+0]\nmov rdx, rbx\njmp short loc_1429\nloc_1420:\nadd rdx, 8\ncmp rsi, rdx\njz short loc_1458\nloc_1429:\ncmp ecx, [rdx]\njnz short loc_1420\nmovd xmm0, dword ptr [rdx+4]\nmovd xmm1, ecx\npunpckldq xmm1, xmm0\nmovq qword ptr [rax+rdi*8], xmm1\nadd rdi, 1\ncmp r12, rdi\njnz short loc_1410\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1458:\nadd rdi, 1\ncmp r12, rdi\njnz short loc_1410\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(_DWORD *a1, int a2, __int64 a3, int a4)\n{\n __int64 v4; // r12\n _QWORD *result; // rax\n __int64 v8; // rdi\n _DWORD *v9; // rsi\n unsigned int v10; // ecx\n _DWORD *v11; // rdx\n\n v4 = a4;\n result = malloc(8LL * a4);\n v8 = 0LL;\n if ( (int)v4 > 0 )\n {\n while ( a2 <= 0 )\n {\n if ( v4 == ++v8 )\n return result;\n }\n v9 = &a1[2 * a2];\nLABEL_6:\n while ( 2 )\n {\n v10 = *(_DWORD *)(a3 + 4 * v8);\n v11 = a1;\n do\n {\n if ( v10 == *v11 )\n {\n result[v8++] = _mm_unpacklo_epi32(_mm_cvtsi32_si128(v10), _mm_cvtsi32_si128(v11[1])).m128i_u64[0];\n if ( v4 != v8 )\n goto LABEL_6;\n return result;\n }\n v11 += 2;\n }\n while ( v9 != v11 );\n if ( v4 != ++v8 )\n continue;\n break;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_13C0:\nendbr64\npush r14\npush r13\nmovsxd r13, esi\npush r12\nmovsxd r12, ecx\npush rbp\nmov rbp, rdx\npush rbx\nmov rbx, rdi\nlea rdi, ds:0[r12*8]; size\ncall _malloc\nxor edi, edi\ntest r12d, r12d\njle short loc_13FA\nloc_13EC:\ntest r13d, r13d\njg short loc_1403\nadd rdi, 1\ncmp r12, rdi\njnz short loc_13EC\nloc_13FA:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1403:\nlea rsi, [rbx+r13*8]\nnop word ptr [rax+rax+00000000h]\nloc_1410:\nmov ecx, [rbp+rdi*4+0]\nmov rdx, rbx\njmp short loc_1429\nloc_1420:\nadd rdx, 8\ncmp rsi, rdx\njz short loc_1458\nloc_1429:\ncmp ecx, [rdx]\njnz short loc_1420\nmovd xmm0, dword ptr [rdx+4]\nmovd xmm1, ecx\npunpckldq xmm1, xmm0\nmovq qword ptr [rax+rdi*8], xmm1\nadd rdi, 1\ncmp r12, rdi\njnz short loc_1410\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1458:\nadd rdi, 1\ncmp r12, rdi\njnz short loc_1410\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_13C0(_DWORD *a1, int a2, __int64 a3, int a4)\n{\n __int64 v4; // r12\n _QWORD *result; // rax\n __int64 v8; // rdi\n _DWORD *v9; // rsi\n unsigned int v10; // ecx\n _DWORD *v11; // rdx\n\n v4 = a4;\n result = malloc(8LL * a4);\n v8 = 0LL;\n if ( (int)v4 > 0 )\n {\n while ( a2 <= 0 )\n {\n if ( v4 == ++v8 )\n return result;\n }\n v9 = &a1[2 * a2];\nLABEL_6:\n while ( 2 )\n {\n v10 = *(_DWORD *)(a3 + 4 * v8);\n v11 = a1;\n do\n {\n if ( v10 == *v11 )\n {\n result[v8++] = _mm_unpacklo_epi32(_mm_cvtsi32_si128(v10), _mm_cvtsi32_si128(v11[1])).m128i_u64[0];\n if ( v4 != v8 )\n goto LABEL_6;\n return result;\n }\n v11 += 2;\n }\n while ( v9 != v11 );\n if ( v4 != ++v8 )\n continue;\n break;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_13C0(uint32_t *a1, int a2, long long a3, int a4) {\n long long v4;\n uint64_t *result;\n long long v8;\n uint32_t *v9;\n unsigned int v10;\n uint32_t *v11;\n v4 = a4;\n result = malloc(8LL * a4);\n v8 = 0LL;\n if ((int)v4 > 0) {\n while (a2 <= 0) {\n if (v4 == ++v8) return result;\n }\n v9 = &a1[2 * a2];\n LABEL_6:\n while (2) {\n v10 = *(uint32_t *)(a3 + 4 * v8);\n v11 = a1;\n do {\n if (v10 == *v11) {\n result[v8++] = _mm_unpacklo_epi32(_mm_cvtsi32_si128(v10),\n _mm_cvtsi32_si128(v11[1]))\n .m128i_u64[0];\n if (v4 != v8) goto LABEL_6;\n return result;\n }\n v11 += 2;\n } while (v9 != v11);\n if (v4 != ++v8) continue;\n break;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "uint64_t *func0(uint32_t *a1, int a2, long long a3, int a4) {\n long long v4;\n uint64_t *result;\n long long v8;\n uint32_t *v9;\n unsigned int v10;\n uint32_t *v11;\n v4 = a4;\n result = malloc(8LL * a4);\n v8 = 0LL;\n if ((int)v4 > 0) {\n while (a2 <= 0) {\n if (v4 == ++v8) return result;\n }\n v9 = &a1[2 * a2];\n LABEL_6:\n while (2) {\n v10 = *(uint32_t *)(a3 + 4 * v8);\n v11 = a1;\n do {\n if (v10 == *v11) {\n result[v8++] = _mm_unpacklo_epi32(_mm_cvtsi32_si128(v10),\n _mm_cvtsi32_si128(v11[1]))\n .m128i_u64[0];\n if (v4 != v8) goto LABEL_6;\n return result;\n }\n v11 += 2;\n } while (v9 != v11);\n if (v4 != ++v8) continue;\n break;\n }\n }\n return result;\n}" + }, + { + "index": 936, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int key;\n\n int value;\n\n} pair;\n\n\n\n", + "func": "pair* func0(pair test_list[], int test_list_size, int ord_list[],\n int ord_list_size) {\n pair* res = (pair*)malloc(ord_list_size * sizeof(pair));\n int i, j;\n for (i = 0; i < ord_list_size; i++) {\n for (j = 0; j < test_list_size; j++) {\n if (ord_list[i] == test_list[j].key) {\n res[i].key = test_list[j].key;\n res[i].value = test_list[j].value;\n break;\n }\n }\n }\n return res;\n}", + "test": "int main() {\n\n pair test_list1[] = {{4, 3}, {1, 9}, {2, 10}, {3, 2}};\n\n int ord_list1[] = {1, 4, 2, 3};\n\n pair *result1 = func0(test_list1, 4, ord_list1, 4);\n\n assert((result1[0].key == 1 && result1[0].value == 9) &&\n\n (result1[1].key == 4 && result1[1].value == 3) &&\n\n (result1[2].key == 2 && result1[2].value == 10) &&\n\n (result1[3].key == 3 && result1[3].value == 2));\n\n\n\n pair test_list2[] = {{5, 4}, {2, 10}, {3, 11}, {4, 3}};\n\n int ord_list2[] = {3, 4, 2, 3};\n\n pair *result2 = func0(test_list2, 4, ord_list2, 4);\n\n assert((result2[0].key == 3 && result2[0].value == 11) &&\n\n (result2[1].key == 4 && result2[1].value == 3) &&\n\n (result2[2].key == 2 && result2[2].value == 10) &&\n\n (result2[3].key == 3 && result2[3].value == 11));\n\n\n\n pair test_list3[] = {{6, 3}, {3, 8}, {5, 7}, {2, 4}};\n\n int ord_list3[] = {2, 5, 3, 6};\n\n pair *result3 = func0(test_list3, 4, ord_list3, 4);\n\n assert((result3[0].key == 2 && result3[0].value == 4) &&\n\n (result3[1].key == 5 && result3[1].value == 7) &&\n\n (result3[2].key == 3 && result3[2].value == 8) &&\n\n (result3[3].key == 6 && result3[3].value == 3));\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\nmov %rdx,%r12\npush %rbp\nmov %rdi,%rbp\nmovslq %ecx,%rdi\npush %rbx\nmov %rdi,%r13\nshl $0x3,%rdi\nmov %esi,%ebx\nsub $0x8,%rsp\ncallq 1090 \ntest %r13d,%r13d\njle 1440 \nlea -0x1(%rbx),%ecx\nlea -0x1(%r13),%edx\nxor %r9d,%r9d\nlea 0x8(%rbp,%rcx,8),%r8\nnopl 0x0(%rax)\ntest %ebx,%ebx\njle 1429 \nmov (%r12,%r9,4),%edi\nmov %rbp,%rcx\njmp 1419 \nnopl (%rax)\nadd $0x8,%rcx\ncmp %r8,%rcx\nje 1429 \ncmp (%rcx),%edi\njne 1410 \nmov 0x4(%rcx),%ecx\nmov %edi,(%rax,%r9,8)\nmov %ecx,0x4(%rax,%r9,8)\nlea 0x1(%r9),%rcx\ncmp %rdx,%r9\nje 1440 \nmov %rcx,%r9\njmp 1400 \nnopw 0x0(%rax,%rax,1)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\nmovsxd r13, esi\npush r12\nmovsxd r12, ecx\npush rbp\nmov rbp, rdx\npush rbx\nmov rbx, rdi\nlea rdi, ds:0[r12*8]; size\ncall _malloc\nxor edi, edi\ntest r12d, r12d\njle short loc_13FA\nloc_13EC:\ntest r13d, r13d\njg short loc_1403\nadd rdi, 1\ncmp r12, rdi\njnz short loc_13EC\nloc_13FA:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1403:\nlea rsi, [rbx+r13*8]\nnop word ptr [rax+rax+00000000h]\nloc_1410:\nmov ecx, [rbp+rdi*4+0]\nmov rdx, rbx\njmp short loc_1429\nloc_1420:\nadd rdx, 8\ncmp rsi, rdx\njz short loc_1458\nloc_1429:\ncmp ecx, [rdx]\njnz short loc_1420\nmovd xmm0, dword ptr [rdx+4]\nmovd xmm1, ecx\npunpckldq xmm1, xmm0\nmovq qword ptr [rax+rdi*8], xmm1\nadd rdi, 1\ncmp r12, rdi\njnz short loc_1410\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1458:\nadd rdi, 1\ncmp r12, rdi\njnz short loc_1410\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(_DWORD *a1, int a2, __int64 a3, int a4)\n{\n __int64 v4; // r12\n _QWORD *result; // rax\n __int64 v8; // rdi\n _DWORD *v9; // rsi\n unsigned int v10; // ecx\n _DWORD *v11; // rdx\n\n v4 = a4;\n result = malloc(8LL * a4);\n v8 = 0LL;\n if ( (int)v4 > 0 )\n {\n while ( a2 <= 0 )\n {\n if ( v4 == ++v8 )\n return result;\n }\n v9 = &a1[2 * a2];\nLABEL_6:\n while ( 2 )\n {\n v10 = *(_DWORD *)(a3 + 4 * v8);\n v11 = a1;\n do\n {\n if ( v10 == *v11 )\n {\n result[v8++] = _mm_unpacklo_epi32(_mm_cvtsi32_si128(v10), _mm_cvtsi32_si128(v11[1])).m128i_u64[0];\n if ( v4 != v8 )\n goto LABEL_6;\n return result;\n }\n v11 += 2;\n }\n while ( v9 != v11 );\n if ( v4 != ++v8 )\n continue;\n break;\n }\n }\n return result;\n}", + "ida_strip_asm": "sub_13C0:\nendbr64\npush r14\npush r13\nmovsxd r13, esi\npush r12\nmovsxd r12, ecx\npush rbp\nmov rbp, rdx\npush rbx\nmov rbx, rdi\nlea rdi, ds:0[r12*8]; size\ncall _malloc\nxor edi, edi\ntest r12d, r12d\njle short loc_13FA\nloc_13EC:\ntest r13d, r13d\njg short loc_1403\nadd rdi, 1\ncmp r12, rdi\njnz short loc_13EC\nloc_13FA:\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1403:\nlea rsi, [rbx+r13*8]\nnop word ptr [rax+rax+00000000h]\nloc_1410:\nmov ecx, [rbp+rdi*4+0]\nmov rdx, rbx\njmp short loc_1429\nloc_1420:\nadd rdx, 8\ncmp rsi, rdx\njz short loc_1458\nloc_1429:\ncmp ecx, [rdx]\njnz short loc_1420\nmovd xmm0, dword ptr [rdx+4]\nmovd xmm1, ecx\npunpckldq xmm1, xmm0\nmovq qword ptr [rax+rdi*8], xmm1\nadd rdi, 1\ncmp r12, rdi\njnz short loc_1410\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1458:\nadd rdi, 1\ncmp r12, rdi\njnz short loc_1410\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_13C0(_DWORD *a1, int a2, __int64 a3, int a4)\n{\n __int64 v4; // r12\n _QWORD *result; // rax\n __int64 v8; // rdi\n _DWORD *v9; // rsi\n unsigned int v10; // ecx\n _DWORD *v11; // rdx\n\n v4 = a4;\n result = malloc(8LL * a4);\n v8 = 0LL;\n if ( (int)v4 > 0 )\n {\n while ( a2 <= 0 )\n {\n if ( v4 == ++v8 )\n return result;\n }\n v9 = &a1[2 * a2];\nLABEL_6:\n while ( 2 )\n {\n v10 = *(_DWORD *)(a3 + 4 * v8);\n v11 = a1;\n do\n {\n if ( v10 == *v11 )\n {\n result[v8++] = _mm_unpacklo_epi32(_mm_cvtsi32_si128(v10), _mm_cvtsi32_si128(v11[1])).m128i_u64[0];\n if ( v4 != v8 )\n goto LABEL_6;\n return result;\n }\n v11 += 2;\n }\n while ( v9 != v11 );\n if ( v4 != ++v8 )\n continue;\n break;\n }\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_13C0(uint32_t *a1, int a2, long long a3, int a4) {\n long long v4;\n uint64_t *result;\n long long v8;\n uint32_t *v9;\n unsigned int v10;\n uint32_t *v11;\n v4 = a4;\n result = malloc(8LL * a4);\n v8 = 0LL;\n if ((int)v4 > 0) {\n while (a2 <= 0) {\n if (v4 == ++v8) return result;\n }\n v9 = &a1[2 * a2];\n LABEL_6:\n while (2) {\n v10 = *(uint32_t *)(a3 + 4 * v8);\n v11 = a1;\n do {\n if (v10 == *v11) {\n result[v8++] = _mm_unpacklo_epi32(_mm_cvtsi32_si128(v10),\n _mm_cvtsi32_si128(v11[1]))\n .m128i_u64[0];\n if (v4 != v8) goto LABEL_6;\n return result;\n }\n v11 += 2;\n } while (v9 != v11);\n if (v4 != ++v8) continue;\n break;\n }\n }\n return result;\n}", + "ida_pseudo_norm": "uint64_t *func0(uint32_t *a1, int a2, long long a3, int a4) {\n long long v4;\n uint64_t *result;\n long long v8;\n uint32_t *v9;\n unsigned int v10;\n uint32_t *v11;\n v4 = a4;\n result = malloc(8LL * a4);\n v8 = 0LL;\n if ((int)v4 > 0) {\n while (a2 <= 0) {\n if (v4 == ++v8) return result;\n }\n v9 = &a1[2 * a2];\n LABEL_6:\n while (2) {\n v10 = *(uint32_t *)(a3 + 4 * v8);\n v11 = a1;\n do {\n if (v10 == *v11) {\n result[v8++] = _mm_unpacklo_epi32(_mm_cvtsi32_si128(v10),\n _mm_cvtsi32_si128(v11[1]))\n .m128i_u64[0];\n if (v4 != v8) goto LABEL_6;\n return result;\n }\n v11 += 2;\n } while (v9 != v11);\n if (v4 != ++v8) continue;\n break;\n }\n }\n return result;\n}" + }, + { + "index": 937, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char func0(const char *str1) {\n int frequency[256] = {0};\n int max_freq = 0;\n char max_char = '\\0';\n int len = strlen(str1);\n for (int i = 0; i < len; i++) {\n frequency[(unsigned char)str1[i]]++;\n if (frequency[(unsigned char)str1[i]] > max_freq) {\n max_freq = frequency[(unsigned char)str1[i]];\n max_char = str1[i];\n }\n }\n return max_char;\n}", + "test": "int main() {\n\n assert(func0(\"hello world\") == 'l');\n\n assert(func0(\"hello \") == 'l');\n\n assert(func0(\"python pr\") == 'p');\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x430,%rsp\nmov %rdi,-0x428(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea -0x410(%rbp),%rdx\nmov $0x0,%eax\nmov $0x80,%ecx\nmov %rdx,%rdi\nrep stos %rax,%es:(%rdi)\nmovl $0x0,-0x41c(%rbp)\nmovb $0x0,-0x41d(%rbp)\nmov -0x428(%rbp),%rax\nmov %rax,%rdi\ncallq 1070 \nmov %eax,-0x414(%rbp)\nmovl $0x0,-0x418(%rbp)\njmpq 129e \nmov -0x418(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x428(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmovzbl %al,%eax\nmovslq %eax,%rdx\nmov -0x410(%rbp,%rdx,4),%edx\nadd $0x1,%edx\ncltq\nmov %edx,-0x410(%rbp,%rax,4)\nmov -0x418(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x428(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmovzbl %al,%eax\ncltq\nmov -0x410(%rbp,%rax,4),%eax\ncmp %eax,-0x41c(%rbp)\njge 1297 \nmov -0x418(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x428(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmovzbl %al,%eax\ncltq\nmov -0x410(%rbp,%rax,4),%eax\nmov %eax,-0x41c(%rbp)\nmov -0x418(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x428(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmov %al,-0x41d(%rbp)\naddl $0x1,-0x418(%rbp)\nmov -0x418(%rbp),%eax\ncmp -0x414(%rbp),%eax\njl 11fa \nmovzbl -0x41d(%rbp),%eax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 12cb \ncallq 1080 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 430h\nmov [rbp+s], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rdx, [rbp+var_410]\nmov eax, 0\nmov ecx, 80h\nmov rdi, rdx\nrep stosq\nmov [rbp+var_41C], 0\nmov [rbp+var_41D], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_414], eax\nmov [rbp+var_418], 0\njmp loc_129E\nloc_11FA:\nmov eax, [rbp+var_418]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovzx eax, al\nmovsxd rdx, eax\nmov edx, [rbp+rdx*4+var_410]\nadd edx, 1\ncdqe\nmov [rbp+rax*4+var_410], edx\nmov eax, [rbp+var_418]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovzx eax, al\ncdqe\nmov eax, [rbp+rax*4+var_410]\ncmp [rbp+var_41C], eax\njge short loc_1297\nmov eax, [rbp+var_418]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovzx eax, al\ncdqe\nmov eax, [rbp+rax*4+var_410]\nmov [rbp+var_41C], eax\nmov eax, [rbp+var_418]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_41D], al\nloc_1297:\nadd [rbp+var_418], 1\nloc_129E:\nmov eax, [rbp+var_418]\ncmp eax, [rbp+var_414]\njl loc_11FA\nmovzx eax, [rbp+var_41D]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12CB\ncall ___stack_chk_fail\nlocret_12CB:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n unsigned __int8 v2; // [rsp+13h] [rbp-41Dh]\n int v3; // [rsp+14h] [rbp-41Ch]\n int i; // [rsp+18h] [rbp-418h]\n int v5; // [rsp+1Ch] [rbp-414h]\n _DWORD v6[258]; // [rsp+20h] [rbp-410h] BYREF\n unsigned __int64 v7; // [rsp+428h] [rbp-8h]\n\n v7 = __readfsqword(0x28u);\n memset(v6, 0, 0x400uLL);\n v3 = 0;\n v2 = 0;\n v5 = strlen(a1);\n for ( i = 0; i < v5; ++i )\n {\n if ( v3 < ++v6[(unsigned __int8)a1[i]] )\n {\n v3 = v6[(unsigned __int8)a1[i]];\n v2 = a1[i];\n }\n }\n return v2;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 430h\nmov [rbp+s], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rdx, [rbp+var_410]\nmov eax, 0\nmov ecx, 80h\nmov rdi, rdx\nrep stosq\nmov [rbp+var_41C], 0\nmov [rbp+var_41D], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_414], eax\nmov [rbp+var_418], 0\njmp loc_129E\nloc_11FA:\nmov eax, [rbp+var_418]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovzx eax, al\nmovsxd rdx, eax\nmov edx, [rbp+rdx*4+var_410]\nadd edx, 1\ncdqe\nmov [rbp+rax*4+var_410], edx\nmov eax, [rbp+var_418]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovzx eax, al\ncdqe\nmov eax, [rbp+rax*4+var_410]\ncmp [rbp+var_41C], eax\njge short loc_1297\nmov eax, [rbp+var_418]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovzx eax, al\ncdqe\nmov eax, [rbp+rax*4+var_410]\nmov [rbp+var_41C], eax\nmov eax, [rbp+var_418]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_41D], al\nloc_1297:\nadd [rbp+var_418], 1\nloc_129E:\nmov eax, [rbp+var_418]\ncmp eax, [rbp+var_414]\njl loc_11FA\nmovzx eax, [rbp+var_41D]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12CB\ncall ___stack_chk_fail\nlocret_12CB:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(const char *a1)\n{\n unsigned __int8 v2; // [rsp+13h] [rbp-41Dh]\n int v3; // [rsp+14h] [rbp-41Ch]\n int i; // [rsp+18h] [rbp-418h]\n int v5; // [rsp+1Ch] [rbp-414h]\n _DWORD v6[258]; // [rsp+20h] [rbp-410h] BYREF\n unsigned __int64 v7; // [rsp+428h] [rbp-8h]\n\n v7 = __readfsqword(0x28u);\n memset(v6, 0, 0x400uLL);\n v3 = 0;\n v2 = 0;\n v5 = strlen(a1);\n for ( i = 0; i < v5; ++i )\n {\n if ( v3 < ++v6[(unsigned __int8)a1[i]] )\n {\n v3 = v6[(unsigned __int8)a1[i]];\n v2 = a1[i];\n }\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(const char *a1) {\n unsigned char v2;\n int v3;\n int i;\n int v5;\n uint32_t v6[258];\n unsigned long long v7;\n v7 = __readfsqword(40u);\n memset(v6, 0, 1024uLL);\n v3 = 0;\n v2 = 0;\n v5 = strlen(a1);\n for (i = 0; i < v5; ++i) {\n if (v3 < ++v6[(unsigned char)a1[i]]) {\n v3 = v6[(unsigned char)a1[i]];\n v2 = a1[i];\n }\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n unsigned char v2;\n int v3;\n int i;\n int v5;\n uint32_t v6[258];\n unsigned long long v7;\n v7 = __readfsqword(40u);\n memset(v6, 0, 1024uLL);\n v3 = 0;\n v2 = 0;\n v5 = strlen(a1);\n for (i = 0; i < v5; ++i) {\n if (v3 < ++v6[(unsigned char)a1[i]]) {\n v3 = v6[(unsigned char)a1[i]];\n v2 = a1[i];\n }\n }\n return v2;\n}" + }, + { + "index": 937, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char func0(const char *str1) {\n int frequency[256] = {0};\n int max_freq = 0;\n char max_char = '\\0';\n int len = strlen(str1);\n for (int i = 0; i < len; i++) {\n frequency[(unsigned char)str1[i]]++;\n if (frequency[(unsigned char)str1[i]] > max_freq) {\n max_freq = frequency[(unsigned char)str1[i]];\n max_char = str1[i];\n }\n }\n return max_char;\n}", + "test": "int main() {\n\n assert(func0(\"hello world\") == 'l');\n\n assert(func0(\"hello \") == 'l');\n\n assert(func0(\"python pr\") == 'p');\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x418,%rsp\nmov %rdi,%rsi\nmov %fs:0x28,%rax\nmov %rax,0x408(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nmov $0x80,%ecx\nrep stos %rax,%es:(%rdi)\nmov $0xffffffffffffffff,%rcx\nmov %rsi,%rdi\nrepnz scas %es:(%rdi),%al\nnot %rcx\nsub $0x1,%rcx\ntest %ecx,%ecx\njle 11e8 \nmov %rsi,%rdx\nlea -0x1(%rcx),%eax\nlea 0x1(%rsi,%rax,1),%r8\nmov $0x0,%r9d\nmov $0x0,%edi\njmp 11cd \nadd $0x1,%rdx\ncmp %r8,%rdx\nje 11ee \nmovzbl (%rdx),%esi\nmovzbl %sil,%ecx\nmov (%rsp,%rcx,4),%eax\nadd $0x1,%eax\nmov %eax,(%rsp,%rcx,4)\ncmp %edi,%eax\njle 11c4 \nmov %esi,%r9d\nmov %eax,%edi\njmp 11c4 \nmov $0x0,%r9d\nmov 0x408(%rsp),%rax\nxor %fs:0x28,%rax\njne 120c \nmov %r9d,%eax\nadd $0x418,%rsp\nretq\ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbx\nsub rsp, 410h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+418h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nmov ecx, 80h\nrep stosq\nmov rdi, rbx; s\ncall _strlen\ntest eax, eax\njle short loc_11FE\nmov rdx, rbx\nlea eax, [rax-1]\nlea r8, [rbx+rax+1]\nmov r9d, 0\nmov edi, 0\njmp short loc_11E3\nloc_11DA:\nadd rdx, 1\ncmp rdx, r8\njz short loc_1204\nloc_11E3:\nmovzx esi, byte ptr [rdx]\nmovzx ecx, sil\nmov eax, [rsp+rcx*4+418h+var_418]\nadd eax, 1\nmov [rsp+rcx*4+418h+var_418], eax\ncmp eax, edi\njle short loc_11DA\nmov r9d, esi\nmov edi, eax\njmp short loc_11DA\nloc_11FE:\nmov r9d, 0\nloc_1204:\nmov rax, [rsp+418h+var_10]\nsub rax, fs:28h\njnz short loc_1223\nmov eax, r9d\nadd rsp, 410h\npop rbx\nretn\nloc_1223:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(char *s)\n{\n int v1; // eax\n char *v2; // rdx\n char *v3; // r8\n unsigned int v4; // r9d\n int v5; // edi\n unsigned int v6; // esi\n int v7; // eax\n _DWORD v9[258]; // [rsp+0h] [rbp-418h] BYREF\n unsigned __int64 v10; // [rsp+408h] [rbp-10h]\n\n v10 = __readfsqword(0x28u);\n memset(v9, 0, 0x400uLL);\n v1 = strlen(s);\n if ( v1 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = s;\n v3 = &s[v1 - 1 + 1];\n v4 = 0;\n v5 = 0;\n do\n {\n v6 = (unsigned __int8)*v2;\n v7 = v9[(unsigned __int8)v6] + 1;\n v9[(unsigned __int8)v6] = v7;\n if ( v7 > v5 )\n {\n v4 = v6;\n v5 = v7;\n }\n ++v2;\n }\n while ( v2 != v3 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbx\nsub rsp, 410h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+418h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nmov ecx, 80h\nrep stosq\nmov rdi, rbx; s\ncall _strlen\ntest eax, eax\njle short loc_11FE\nmov rdx, rbx\nlea eax, [rax-1]\nlea r8, [rbx+rax+1]\nmov r9d, 0\nmov edi, 0\njmp short loc_11E3\nloc_11DA:\nadd rdx, 1\ncmp rdx, r8\njz short loc_1204\nloc_11E3:\nmovzx esi, byte ptr [rdx]\nmovzx ecx, sil\nmov eax, [rsp+rcx*4+418h+var_418]\nadd eax, 1\nmov [rsp+rcx*4+418h+var_418], eax\ncmp eax, edi\njle short loc_11DA\nmov r9d, esi\nmov edi, eax\njmp short loc_11DA\nloc_11FE:\nmov r9d, 0\nloc_1204:\nmov rax, [rsp+418h+var_10]\nsub rax, fs:28h\njnz short loc_1223\nmov eax, r9d\nadd rsp, 410h\npop rbx\nretn\nloc_1223:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(char *s)\n{\n int v1; // eax\n char *v2; // rdx\n char *v3; // r8\n unsigned int v4; // r9d\n int v5; // edi\n unsigned int v6; // esi\n int v7; // eax\n _DWORD v9[258]; // [rsp+0h] [rbp-418h] BYREF\n unsigned __int64 v10; // [rsp+408h] [rbp-10h]\n\n v10 = __readfsqword(0x28u);\n memset(v9, 0, 0x400uLL);\n v1 = strlen(s);\n if ( v1 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = s;\n v3 = &s[v1 - 1 + 1];\n v4 = 0;\n v5 = 0;\n do\n {\n v6 = (unsigned __int8)*v2;\n v7 = v9[(unsigned __int8)v6] + 1;\n v9[(unsigned __int8)v6] = v7;\n if ( v7 > v5 )\n {\n v4 = v6;\n v5 = v7;\n }\n ++v2;\n }\n while ( v2 != v3 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(char *s) {\n int v1;\n char *v2;\n char *v3;\n unsigned int v4;\n int v5;\n unsigned int v6;\n int v7;\n uint32_t v9[258];\n unsigned long long v10;\n v10 = __readfsqword(40u);\n memset(v9, 0, 1024uLL);\n v1 = strlen(s);\n if (v1 <= 0) {\n return 0;\n } else {\n v2 = s;\n v3 = &s[v1 - 1 + 1];\n v4 = 0;\n v5 = 0;\n do {\n v6 = (unsigned char)*v2;\n v7 = v9[(unsigned char)v6] + 1;\n v9[(unsigned char)v6] = v7;\n if (v7 > v5) {\n v4 = v6;\n v5 = v7;\n }\n ++v2;\n } while (v2 != v3);\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(char *s) {\n int v1;\n char *v2;\n char *v3;\n unsigned int v4;\n int v5;\n unsigned int v6;\n int v7;\n uint32_t v9[258];\n unsigned long long v10;\n v10 = __readfsqword(40u);\n memset(v9, 0, 1024uLL);\n v1 = strlen(s);\n if (v1 <= 0) {\n return 0;\n } else {\n v2 = s;\n v3 = &s[v1 - 1 + 1];\n v4 = 0;\n v5 = 0;\n do {\n v6 = (unsigned char)*v2;\n v7 = v9[(unsigned char)v6] + 1;\n v9[(unsigned char)v6] = v7;\n if (v7 > v5) {\n v4 = v6;\n v5 = v7;\n }\n ++v2;\n } while (v2 != v3);\n }\n return v4;\n}" + }, + { + "index": 937, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char func0(const char *str1) {\n int frequency[256] = {0};\n int max_freq = 0;\n char max_char = '\\0';\n int len = strlen(str1);\n for (int i = 0; i < len; i++) {\n frequency[(unsigned char)str1[i]]++;\n if (frequency[(unsigned char)str1[i]] > max_freq) {\n max_freq = frequency[(unsigned char)str1[i]];\n max_char = str1[i];\n }\n }\n return max_char;\n}", + "test": "int main() {\n\n assert(func0(\"hello world\") == 'l');\n\n assert(func0(\"hello \") == 'l');\n\n assert(func0(\"python pr\") == 'p');\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov $0x80,%ecx\nmov %rdi,%rbx\nsub $0x410,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x408(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nrep stos %rax,%es:(%rdi)\nmov %rbx,%rdi\ncallq 1070 \ntest %eax,%eax\njle 12c0 \nsub $0x1,%eax\nmov %rbx,%rdi\nxor %r9d,%r9d\nxor %esi,%esi\nlea 0x1(%rbx,%rax,1),%r8\nnopl 0x0(%rax)\nmovzbl (%rdi),%edx\nmov (%rsp,%rdx,4),%eax\nadd $0x1,%eax\nmov %eax,(%rsp,%rdx,4)\ncmp %esi,%eax\njle 1295 \nmov %edx,%r9d\nmov %eax,%esi\nadd $0x1,%rdi\ncmp %r8,%rdi\njne 1280 \nmov 0x408(%rsp),%rax\nxor %fs:0x28,%rax\njne 12c5 \nadd $0x410,%rsp\nmov %r9d,%eax\npop %rbx\nretq\nnopl (%rax)\nxor %r9d,%r9d\njmp 129e \ncallq 1080 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov ecx, 80h\nmov rbx, rdi\nsub rsp, 410h\nmov rax, fs:28h\nmov [rsp+418h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\nmov rdi, rbx; s\ncall _strlen\ntest eax, eax\njle short loc_12C0\nsub eax, 1\nmov rdi, rbx\nxor r9d, r9d\nxor esi, esi\nlea r8, [rbx+rax+1]\nnop dword ptr [rax+00000000h]\nloc_1280:\nmovzx edx, byte ptr [rdi]\nmov eax, [rsp+rdx*4+418h+var_418]\nadd eax, 1\nmov [rsp+rdx*4+418h+var_418], eax\ncmp esi, eax\njge short loc_1295\nmov r9d, edx\nmov esi, eax\nloc_1295:\nadd rdi, 1\ncmp r8, rdi\njnz short loc_1280\nloc_129E:\nmov rax, [rsp+418h+var_10]\nsub rax, fs:28h\njnz short loc_12C5\nadd rsp, 410h\nmov eax, r9d\npop rbx\nretn\nloc_12C0:\nxor r9d, r9d\njmp short loc_129E\nloc_12C5:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(char *s)\n{\n int v1; // eax\n unsigned int v2; // r9d\n int v3; // esi\n char *v4; // r8\n __int64 v5; // rdx\n int v6; // eax\n _DWORD v8[258]; // [rsp+0h] [rbp-418h] BYREF\n unsigned __int64 v9; // [rsp+408h] [rbp-10h]\n\n v9 = __readfsqword(0x28u);\n memset(v8, 0, 0x400uLL);\n v1 = strlen(s);\n if ( v1 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = 0;\n v3 = 0;\n v4 = &s[v1 - 1 + 1];\n do\n {\n v5 = (unsigned __int8)*s;\n v6 = v8[v5] + 1;\n v8[v5] = v6;\n if ( v3 < v6 )\n {\n v2 = v5;\n v3 = v6;\n }\n ++s;\n }\n while ( v4 != s );\n }\n return v2;\n}", + "ida_strip_asm": "sub_1230:\nendbr64\npush rbx\nmov ecx, 80h\nmov rbx, rdi\nsub rsp, 410h\nmov rax, fs:28h\nmov [rsp+418h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\nmov rdi, rbx; s\ncall _strlen\ntest eax, eax\njle short loc_12C0\nsub eax, 1\nmov rdi, rbx\nxor r9d, r9d\nxor esi, esi\nlea r8, [rbx+rax+1]\nnop dword ptr [rax+00000000h]\nloc_1280:\nmovzx edx, byte ptr [rdi]\nmov eax, [rsp+rdx*4+418h+var_418]\nadd eax, 1\nmov [rsp+rdx*4+418h+var_418], eax\ncmp esi, eax\njge short loc_1295\nmov r9d, edx\nmov esi, eax\nloc_1295:\nadd rdi, 1\ncmp r8, rdi\njnz short loc_1280\nloc_129E:\nmov rax, [rsp+418h+var_10]\nsub rax, fs:28h\njnz short loc_12C5\nadd rsp, 410h\nmov eax, r9d\npop rbx\nretn\nloc_12C0:\nxor r9d, r9d\njmp short loc_129E\nloc_12C5:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1230(char *s)\n{\n int v1; // eax\n unsigned int v2; // r9d\n int v3; // esi\n char *v4; // r8\n __int64 v5; // rdx\n int v6; // eax\n _DWORD v8[258]; // [rsp+0h] [rbp-418h] BYREF\n unsigned __int64 v9; // [rsp+408h] [rbp-10h]\n\n v9 = __readfsqword(0x28u);\n memset(v8, 0, 0x400uLL);\n v1 = strlen(s);\n if ( v1 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = 0;\n v3 = 0;\n v4 = &s[v1 - 1 + 1];\n do\n {\n v5 = (unsigned __int8)*s;\n v6 = v8[v5] + 1;\n v8[v5] = v6;\n if ( v3 < v6 )\n {\n v2 = v5;\n v3 = v6;\n }\n ++s;\n }\n while ( v4 != s );\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1230(char *s) {\n int v1;\n unsigned int v2;\n int v3;\n char *v4;\n long long v5;\n int v6;\n uint32_t v8[258];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n memset(v8, 0, 1024uLL);\n v1 = strlen(s);\n if (v1 <= 0) {\n return 0;\n } else {\n v2 = 0;\n v3 = 0;\n v4 = &s[v1 - 1 + 1];\n do {\n v5 = (unsigned char)*s;\n v6 = v8[v5] + 1;\n v8[v5] = v6;\n if (v3 < v6) {\n v2 = v5;\n v3 = v6;\n }\n ++s;\n } while (v4 != s);\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(char *s) {\n int v1;\n unsigned int v2;\n int v3;\n char *v4;\n long long v5;\n int v6;\n uint32_t v8[258];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n memset(v8, 0, 1024uLL);\n v1 = strlen(s);\n if (v1 <= 0) {\n return 0;\n } else {\n v2 = 0;\n v3 = 0;\n v4 = &s[v1 - 1 + 1];\n do {\n v5 = (unsigned char)*s;\n v6 = v8[v5] + 1;\n v8[v5] = v6;\n if (v3 < v6) {\n v2 = v5;\n v3 = v6;\n }\n ++s;\n } while (v4 != s);\n }\n return v2;\n}" + }, + { + "index": 937, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char func0(const char *str1) {\n int frequency[256] = {0};\n int max_freq = 0;\n char max_char = '\\0';\n int len = strlen(str1);\n for (int i = 0; i < len; i++) {\n frequency[(unsigned char)str1[i]]++;\n if (frequency[(unsigned char)str1[i]] > max_freq) {\n max_freq = frequency[(unsigned char)str1[i]];\n max_char = str1[i];\n }\n }\n return max_char;\n}", + "test": "int main() {\n\n assert(func0(\"hello world\") == 'l');\n\n assert(func0(\"hello \") == 'l');\n\n assert(func0(\"python pr\") == 'p');\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov $0x80,%ecx\nmov %rdi,%rbx\nsub $0x410,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x408(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nrep stos %rax,%es:(%rdi)\nmov %rbx,%rdi\ncallq 1070 \ntest %eax,%eax\njle 12c0 \nsub $0x1,%eax\nmov %rbx,%rdi\nxor %r9d,%r9d\nxor %esi,%esi\nlea 0x1(%rbx,%rax,1),%r8\nnopl 0x0(%rax)\nmovzbl (%rdi),%edx\nmov (%rsp,%rdx,4),%eax\nadd $0x1,%eax\nmov %eax,(%rsp,%rdx,4)\ncmp %eax,%esi\njge 1295 \nmov %edx,%r9d\nmov %eax,%esi\nadd $0x1,%rdi\ncmp %rdi,%r8\njne 1280 \nmov 0x408(%rsp),%rax\nxor %fs:0x28,%rax\njne 12c5 \nadd $0x410,%rsp\nmov %r9d,%eax\npop %rbx\nretq\nnopl (%rax)\nxor %r9d,%r9d\njmp 129e \ncallq 1080 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov ecx, 80h\nmov rbx, rdi\nsub rsp, 410h\nmov rax, fs:28h\nmov [rsp+418h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\nmov rdi, rbx; s\ncall _strlen\ntest eax, eax\njle short loc_12C0\nsub eax, 1\nmov rdi, rbx\nxor r9d, r9d\nxor esi, esi\nlea r8, [rbx+rax+1]\nnop dword ptr [rax+00000000h]\nloc_1280:\nmovzx edx, byte ptr [rdi]\nmov eax, [rsp+rdx*4+418h+var_418]\nadd eax, 1\nmov [rsp+rdx*4+418h+var_418], eax\ncmp esi, eax\njge short loc_1295\nmov r9d, edx\nmov esi, eax\nloc_1295:\nadd rdi, 1\ncmp r8, rdi\njnz short loc_1280\nloc_129E:\nmov rax, [rsp+418h+var_10]\nsub rax, fs:28h\njnz short loc_12C5\nadd rsp, 410h\nmov eax, r9d\npop rbx\nretn\nloc_12C0:\nxor r9d, r9d\njmp short loc_129E\nloc_12C5:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(char *s)\n{\n int v1; // eax\n unsigned int v2; // r9d\n int v3; // esi\n char *v4; // r8\n __int64 v5; // rdx\n int v6; // eax\n _DWORD v8[258]; // [rsp+0h] [rbp-418h] BYREF\n unsigned __int64 v9; // [rsp+408h] [rbp-10h]\n\n v9 = __readfsqword(0x28u);\n memset(v8, 0, 0x400uLL);\n v1 = strlen(s);\n if ( v1 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = 0;\n v3 = 0;\n v4 = &s[v1 - 1 + 1];\n do\n {\n v5 = (unsigned __int8)*s;\n v6 = v8[v5] + 1;\n v8[v5] = v6;\n if ( v3 < v6 )\n {\n v2 = v5;\n v3 = v6;\n }\n ++s;\n }\n while ( v4 != s );\n }\n return v2;\n}", + "ida_strip_asm": "sub_1230:\nendbr64\npush rbx\nmov ecx, 80h\nmov rbx, rdi\nsub rsp, 410h\nmov rax, fs:28h\nmov [rsp+418h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\nmov rdi, rbx; s\ncall _strlen\ntest eax, eax\njle short loc_12C0\nsub eax, 1\nmov rdi, rbx\nxor r9d, r9d\nxor esi, esi\nlea r8, [rbx+rax+1]\nnop dword ptr [rax+00000000h]\nloc_1280:\nmovzx edx, byte ptr [rdi]\nmov eax, [rsp+rdx*4+418h+var_418]\nadd eax, 1\nmov [rsp+rdx*4+418h+var_418], eax\ncmp esi, eax\njge short loc_1295\nmov r9d, edx\nmov esi, eax\nloc_1295:\nadd rdi, 1\ncmp r8, rdi\njnz short loc_1280\nloc_129E:\nmov rax, [rsp+418h+var_10]\nsub rax, fs:28h\njnz short loc_12C5\nadd rsp, 410h\nmov eax, r9d\npop rbx\nretn\nloc_12C0:\nxor r9d, r9d\njmp short loc_129E\nloc_12C5:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1230(char *s)\n{\n int v1; // eax\n unsigned int v2; // r9d\n int v3; // esi\n char *v4; // r8\n __int64 v5; // rdx\n int v6; // eax\n _DWORD v8[258]; // [rsp+0h] [rbp-418h] BYREF\n unsigned __int64 v9; // [rsp+408h] [rbp-10h]\n\n v9 = __readfsqword(0x28u);\n memset(v8, 0, 0x400uLL);\n v1 = strlen(s);\n if ( v1 <= 0 )\n {\n return 0;\n }\n else\n {\n v2 = 0;\n v3 = 0;\n v4 = &s[v1 - 1 + 1];\n do\n {\n v5 = (unsigned __int8)*s;\n v6 = v8[v5] + 1;\n v8[v5] = v6;\n if ( v3 < v6 )\n {\n v2 = v5;\n v3 = v6;\n }\n ++s;\n }\n while ( v4 != s );\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1230(char *s) {\n int v1;\n unsigned int v2;\n int v3;\n char *v4;\n long long v5;\n int v6;\n uint32_t v8[258];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n memset(v8, 0, 1024uLL);\n v1 = strlen(s);\n if (v1 <= 0) {\n return 0;\n } else {\n v2 = 0;\n v3 = 0;\n v4 = &s[v1 - 1 + 1];\n do {\n v5 = (unsigned char)*s;\n v6 = v8[v5] + 1;\n v8[v5] = v6;\n if (v3 < v6) {\n v2 = v5;\n v3 = v6;\n }\n ++s;\n } while (v4 != s);\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(char *s) {\n int v1;\n unsigned int v2;\n int v3;\n char *v4;\n long long v5;\n int v6;\n uint32_t v8[258];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n memset(v8, 0, 1024uLL);\n v1 = strlen(s);\n if (v1 <= 0) {\n return 0;\n } else {\n v2 = 0;\n v3 = 0;\n v4 = &s[v1 - 1 + 1];\n do {\n v5 = (unsigned char)*s;\n v6 = v8[v5] + 1;\n v8[v5] = v6;\n if (v3 < v6) {\n v2 = v5;\n v3 = v6;\n }\n ++s;\n } while (v4 != s);\n }\n return v2;\n}" + }, + { + "index": 938, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int A[], int B[], int C[], int p, int q, int r, int res[3]) {\n int diff = INT_MAX;\n int res_i = 0;\n int res_j = 0;\n int res_k = 0;\n int i = 0;\n int j = 0;\n int k = 0;\n while (i < p && j < q && k < r) {\n int minimum =\n A[i] < B[j] ? (A[i] < C[k] ? A[i] : C[k]) : (B[j] < C[k] ? B[j] : C[k]);\n int maximum =\n A[i] > B[j] ? (A[i] > C[k] ? A[i] : C[k]) : (B[j] > C[k] ? B[j] : C[k]);\n if (maximum - minimum < diff) {\n res_i = i;\n res_j = j;\n res_k = k;\n diff = maximum - minimum;\n }\n if (diff == 0) {\n break;\n }\n if (A[i] == minimum) {\n i++;\n } else if (B[j] == minimum) {\n j++;\n } else {\n k++;\n }\n }\n res[0] = A[res_i];\n res[1] = B[res_j];\n res[2] = C[res_k];\n}", + "test": "int main() {\n\n int res[3];\n\n func0((int[]){1, 4, 10}, (int[]){2, 15, 20}, (int[]){10, 12}, 3, 3, 2, res);\n\n assert(res[0] == 10 && res[1] == 15 && res[2] == 10);\n\n\n\n func0((int[]){20, 24, 100}, (int[]){2, 19, 22, 79, 800}, (int[]){10, 12, 23, 24, 119}, 3, 5, 5, res);\n\n assert(res[0] == 24 && res[1] == 22 && res[2] == 23);\n\n\n\n func0((int[]){2, 5, 11}, (int[]){3, 16, 21}, (int[]){11, 13}, 3, 3, 2, res);\n\n assert(res[0] == 11 && res[1] == 16 && res[2] == 11);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x38(%rbp)\nmov %rsi,-0x40(%rbp)\nmov %rdx,-0x48(%rbp)\nmov %ecx,-0x4c(%rbp)\nmov %r8d,-0x50(%rbp)\nmov %r9d,-0x54(%rbp)\nmovl $0x7fffffff,-0x24(%rbp)\nmovl $0x0,-0x20(%rbp)\nmovl $0x0,-0x1c(%rbp)\nmovl $0x0,-0x18(%rbp)\nmovl $0x0,-0x14(%rbp)\nmovl $0x0,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\njmpq 135e \nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x40(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njge 1221 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x38(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\ncmovle %edx,%eax\njmp 1252 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x40(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\ncmovle %edx,%eax\nmov %eax,-0x8(%rbp)\nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x40(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njle 12b8 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x38(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\ncmovge %edx,%eax\njmp 12e9 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x40(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\ncmovge %edx,%eax\nmov %eax,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nsub -0x8(%rbp),%eax\ncmp %eax,-0x24(%rbp)\njle 1312 \nmov -0x14(%rbp),%eax\nmov %eax,-0x20(%rbp)\nmov -0x10(%rbp),%eax\nmov %eax,-0x1c(%rbp)\nmov -0xc(%rbp),%eax\nmov %eax,-0x18(%rbp)\nmov -0x4(%rbp),%eax\nsub -0x8(%rbp),%eax\nmov %eax,-0x24(%rbp)\ncmpl $0x0,-0x24(%rbp)\nje 137c \nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x8(%rbp)\njne 1339 \naddl $0x1,-0x14(%rbp)\njmp 135e \nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x40(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x8(%rbp)\njne 135a \naddl $0x1,-0x10(%rbp)\njmp 135e \naddl $0x1,-0xc(%rbp)\nmov -0x14(%rbp),%eax\ncmp -0x4c(%rbp),%eax\njge 137d \nmov -0x10(%rbp),%eax\ncmp -0x50(%rbp),%eax\njge 137d \nmov -0xc(%rbp),%eax\ncmp -0x54(%rbp),%eax\njl 11be \njmp 137d \nmov -0x20(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov 0x10(%rbp),%rax\nmov %edx,(%rax)\nmov -0x1c(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x40(%rbp),%rax\nadd %rdx,%rax\nmov 0x10(%rbp),%rdx\nadd $0x4,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x48(%rbp),%rax\nadd %rdx,%rax\nmov 0x10(%rbp),%rdx\nadd $0x8,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_38], rdi\nmov [rbp+var_40], rsi\nmov [rbp+var_48], rdx\nmov [rbp+var_4C], ecx\nmov [rbp+var_50], r8d\nmov [rbp+var_54], r9d\nmov [rbp+var_24], 7FFFFFFFh\nmov [rbp+var_20], 0\nmov [rbp+var_1C], 0\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp loc_135E\nloc_11BE:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njge short loc_1221\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_14]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\ncmovle eax, edx\njmp short loc_1252\nloc_1221:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\ncmovle eax, edx\nloc_1252:\nmov [rbp+var_8], eax\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_12B8\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_14]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\ncmovge eax, edx\njmp short loc_12E9\nloc_12B8:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\ncmovge eax, edx\nloc_12E9:\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\nsub eax, [rbp+var_8]\ncmp [rbp+var_24], eax\njle short loc_1312\nmov eax, [rbp+var_14]\nmov [rbp+var_20], eax\nmov eax, [rbp+var_10]\nmov [rbp+var_1C], eax\nmov eax, [rbp+var_C]\nmov [rbp+var_18], eax\nmov eax, [rbp+var_4]\nsub eax, [rbp+var_8]\nmov [rbp+var_24], eax\nloc_1312:\ncmp [rbp+var_24], 0\njz short loc_137C\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_8], eax\njnz short loc_1339\nadd [rbp+var_14], 1\njmp short loc_135E\nloc_1339:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_8], eax\njnz short loc_135A\nadd [rbp+var_10], 1\njmp short loc_135E\nloc_135A:\nadd [rbp+var_C], 1\nloc_135E:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_4C]\njge short loc_137D\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_50]\njge short loc_137D\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_54]\njl loc_11BE\njmp short loc_137D\nloc_137C:\nnop\nloc_137D:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+arg_0]\nmov [rax], edx\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nadd rax, rdx\nmov rdx, [rbp+arg_0]\nadd rdx, 4\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov rdx, [rbp+arg_0]\nadd rdx, 8\nmov eax, [rax]\nmov [rdx], eax\nnop\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, __int64 a3, int a4, int a5, int a6, _DWORD *a7)\n{\n int v7; // eax\n int v8; // eax\n __int64 result; // rax\n int v10; // [rsp+30h] [rbp-24h]\n int v11; // [rsp+34h] [rbp-20h]\n int v12; // [rsp+38h] [rbp-1Ch]\n int v13; // [rsp+3Ch] [rbp-18h]\n int v14; // [rsp+40h] [rbp-14h]\n int v15; // [rsp+44h] [rbp-10h]\n int v16; // [rsp+48h] [rbp-Ch]\n int v17; // [rsp+4Ch] [rbp-8h]\n\n v10 = 0x7FFFFFFF;\n v11 = 0;\n v12 = 0;\n v13 = 0;\n v14 = 0;\n v15 = 0;\n v16 = 0;\n while ( v14 < a4 && v15 < a5 && v16 < a6 )\n {\n if ( *(_DWORD *)(4LL * v14 + a1) >= *(_DWORD *)(4LL * v15 + a2) )\n {\n v7 = *(_DWORD *)(4LL * v15 + a2);\n if ( *(_DWORD *)(4LL * v16 + a3) <= v7 )\n v7 = *(_DWORD *)(4LL * v16 + a3);\n }\n else\n {\n v7 = *(_DWORD *)(4LL * v14 + a1);\n if ( *(_DWORD *)(4LL * v16 + a3) <= v7 )\n v7 = *(_DWORD *)(4LL * v16 + a3);\n }\n v17 = v7;\n if ( *(_DWORD *)(4LL * v14 + a1) <= *(_DWORD *)(4LL * v15 + a2) )\n {\n v8 = *(_DWORD *)(4LL * v15 + a2);\n if ( *(_DWORD *)(4LL * v16 + a3) >= v8 )\n v8 = *(_DWORD *)(4LL * v16 + a3);\n }\n else\n {\n v8 = *(_DWORD *)(4LL * v14 + a1);\n if ( *(_DWORD *)(4LL * v16 + a3) >= v8 )\n v8 = *(_DWORD *)(4LL * v16 + a3);\n }\n if ( v10 > v8 - v17 )\n {\n v11 = v14;\n v12 = v15;\n v13 = v16;\n v10 = v8 - v17;\n }\n if ( !v10 )\n break;\n if ( v17 == *(_DWORD *)(4LL * v14 + a1) )\n {\n ++v14;\n }\n else if ( v17 == *(_DWORD *)(4LL * v15 + a2) )\n {\n ++v15;\n }\n else\n {\n ++v16;\n }\n }\n *a7 = *(_DWORD *)(4LL * v11 + a1);\n a7[1] = *(_DWORD *)(4LL * v12 + a2);\n result = *(unsigned int *)(4LL * v13 + a3);\n a7[2] = result;\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_38], rdi\nmov [rbp+var_40], rsi\nmov [rbp+var_48], rdx\nmov [rbp+var_4C], ecx\nmov [rbp+var_50], r8d\nmov [rbp+var_54], r9d\nmov [rbp+var_24], 7FFFFFFFh\nmov [rbp+var_20], 0\nmov [rbp+var_1C], 0\nmov [rbp+var_18], 0\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp loc_135E\nloc_11BE:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njge short loc_1221\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_14]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\ncmovle eax, edx\njmp short loc_1252\nloc_1221:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\ncmovle eax, edx\nloc_1252:\nmov [rbp+var_8], eax\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_12B8\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_14]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\ncmovge eax, edx\njmp short loc_12E9\nloc_12B8:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\ncmovge eax, edx\nloc_12E9:\nmov [rbp+var_4], eax\nmov eax, [rbp+var_4]\nsub eax, [rbp+var_8]\ncmp [rbp+var_24], eax\njle short loc_1312\nmov eax, [rbp+var_14]\nmov [rbp+var_20], eax\nmov eax, [rbp+var_10]\nmov [rbp+var_1C], eax\nmov eax, [rbp+var_C]\nmov [rbp+var_18], eax\nmov eax, [rbp+var_4]\nsub eax, [rbp+var_8]\nmov [rbp+var_24], eax\nloc_1312:\ncmp [rbp+var_24], 0\njz short loc_137C\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_8], eax\njnz short loc_1339\nadd [rbp+var_14], 1\njmp short loc_135E\nloc_1339:\nmov eax, [rbp+var_10]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_8], eax\njnz short loc_135A\nadd [rbp+var_10], 1\njmp short loc_135E\nloc_135A:\nadd [rbp+var_C], 1\nloc_135E:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_4C]\njge short loc_137D\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_50]\njge short loc_137D\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_54]\njl loc_11BE\njmp short loc_137D\nloc_137C:\nnop\nloc_137D:\nmov eax, [rbp+var_20]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rax]\nmov rax, [rbp+arg_0]\nmov [rax], edx\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_40]\nadd rax, rdx\nmov rdx, [rbp+arg_0]\nadd rdx, 4\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_48]\nadd rax, rdx\nmov rdx, [rbp+arg_0]\nadd rdx, 8\nmov eax, [rax]\nmov [rdx], eax\nnop\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, __int64 a3, int a4, int a5, int a6, _DWORD *a7)\n{\n int v7; // eax\n int v8; // eax\n __int64 result; // rax\n int v10; // [rsp+30h] [rbp-24h]\n int v11; // [rsp+34h] [rbp-20h]\n int v12; // [rsp+38h] [rbp-1Ch]\n int v13; // [rsp+3Ch] [rbp-18h]\n int v14; // [rsp+40h] [rbp-14h]\n int v15; // [rsp+44h] [rbp-10h]\n int v16; // [rsp+48h] [rbp-Ch]\n int v17; // [rsp+4Ch] [rbp-8h]\n\n v10 = 0x7FFFFFFF;\n v11 = 0;\n v12 = 0;\n v13 = 0;\n v14 = 0;\n v15 = 0;\n v16 = 0;\n while ( v14 < a4 && v15 < a5 && v16 < a6 )\n {\n if ( *(_DWORD *)(4LL * v14 + a1) >= *(_DWORD *)(4LL * v15 + a2) )\n {\n v7 = *(_DWORD *)(4LL * v15 + a2);\n if ( *(_DWORD *)(4LL * v16 + a3) <= v7 )\n v7 = *(_DWORD *)(4LL * v16 + a3);\n }\n else\n {\n v7 = *(_DWORD *)(4LL * v14 + a1);\n if ( *(_DWORD *)(4LL * v16 + a3) <= v7 )\n v7 = *(_DWORD *)(4LL * v16 + a3);\n }\n v17 = v7;\n if ( *(_DWORD *)(4LL * v14 + a1) <= *(_DWORD *)(4LL * v15 + a2) )\n {\n v8 = *(_DWORD *)(4LL * v15 + a2);\n if ( *(_DWORD *)(4LL * v16 + a3) >= v8 )\n v8 = *(_DWORD *)(4LL * v16 + a3);\n }\n else\n {\n v8 = *(_DWORD *)(4LL * v14 + a1);\n if ( *(_DWORD *)(4LL * v16 + a3) >= v8 )\n v8 = *(_DWORD *)(4LL * v16 + a3);\n }\n if ( v10 > v8 - v17 )\n {\n v11 = v14;\n v12 = v15;\n v13 = v16;\n v10 = v8 - v17;\n }\n if ( !v10 )\n break;\n if ( v17 == *(_DWORD *)(4LL * v14 + a1) )\n {\n ++v14;\n }\n else if ( v17 == *(_DWORD *)(4LL * v15 + a2) )\n {\n ++v15;\n }\n else\n {\n ++v16;\n }\n }\n *a7 = *(_DWORD *)(4LL * v11 + a1);\n a7[1] = *(_DWORD *)(4LL * v12 + a2);\n result = *(unsigned int *)(4LL * v13 + a3);\n a7[2] = result;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, long long a3, int a4, int a5,\n int a6, uint32_t *a7) {\n int v7;\n int v8;\n long long result;\n int v10;\n int v11;\n int v12;\n int v13;\n int v14;\n int v15;\n int v16;\n int v17;\n v10 = 2147483647;\n v11 = 0;\n v12 = 0;\n v13 = 0;\n v14 = 0;\n v15 = 0;\n v16 = 0;\n while (v14 < a4 && v15 < a5 && v16 < a6) {\n if (*(uint32_t *)(4LL * v14 + a1) >= *(uint32_t *)(4LL * v15 + a2)) {\n v7 = *(uint32_t *)(4LL * v15 + a2);\n if (*(uint32_t *)(4LL * v16 + a3) <= v7)\n v7 = *(uint32_t *)(4LL * v16 + a3);\n } else {\n v7 = *(uint32_t *)(4LL * v14 + a1);\n if (*(uint32_t *)(4LL * v16 + a3) <= v7)\n v7 = *(uint32_t *)(4LL * v16 + a3);\n }\n v17 = v7;\n if (*(uint32_t *)(4LL * v14 + a1) <= *(uint32_t *)(4LL * v15 + a2)) {\n v8 = *(uint32_t *)(4LL * v15 + a2);\n if (*(uint32_t *)(4LL * v16 + a3) >= v8)\n v8 = *(uint32_t *)(4LL * v16 + a3);\n } else {\n v8 = *(uint32_t *)(4LL * v14 + a1);\n if (*(uint32_t *)(4LL * v16 + a3) >= v8)\n v8 = *(uint32_t *)(4LL * v16 + a3);\n }\n if (v10 > v8 - v17) {\n v11 = v14;\n v12 = v15;\n v13 = v16;\n v10 = v8 - v17;\n }\n if (!v10) break;\n if (v17 == *(uint32_t *)(4LL * v14 + a1)) {\n ++v14;\n } else if (v17 == *(uint32_t *)(4LL * v15 + a2)) {\n ++v15;\n } else {\n ++v16;\n }\n }\n *a7 = *(uint32_t *)(4LL * v11 + a1);\n a7[1] = *(uint32_t *)(4LL * v12 + a2);\n result = *(unsigned int *)(4LL * v13 + a3);\n a7[2] = result;\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, long long a3, int a4, int a5,\n int a6, uint32_t *a7) {\n int v7;\n int v8;\n long long result;\n int v10;\n int v11;\n int v12;\n int v13;\n int v14;\n int v15;\n int v16;\n int v17;\n v10 = 2147483647;\n v11 = 0;\n v12 = 0;\n v13 = 0;\n v14 = 0;\n v15 = 0;\n v16 = 0;\n while (v14 < a4 && v15 < a5 && v16 < a6) {\n if (*(uint32_t *)(4LL * v14 + a1) >= *(uint32_t *)(4LL * v15 + a2)) {\n v7 = *(uint32_t *)(4LL * v15 + a2);\n if (*(uint32_t *)(4LL * v16 + a3) <= v7)\n v7 = *(uint32_t *)(4LL * v16 + a3);\n } else {\n v7 = *(uint32_t *)(4LL * v14 + a1);\n if (*(uint32_t *)(4LL * v16 + a3) <= v7)\n v7 = *(uint32_t *)(4LL * v16 + a3);\n }\n v17 = v7;\n if (*(uint32_t *)(4LL * v14 + a1) <= *(uint32_t *)(4LL * v15 + a2)) {\n v8 = *(uint32_t *)(4LL * v15 + a2);\n if (*(uint32_t *)(4LL * v16 + a3) >= v8)\n v8 = *(uint32_t *)(4LL * v16 + a3);\n } else {\n v8 = *(uint32_t *)(4LL * v14 + a1);\n if (*(uint32_t *)(4LL * v16 + a3) >= v8)\n v8 = *(uint32_t *)(4LL * v16 + a3);\n }\n if (v10 > v8 - v17) {\n v11 = v14;\n v12 = v15;\n v13 = v16;\n v10 = v8 - v17;\n }\n if (!v10) break;\n if (v17 == *(uint32_t *)(4LL * v14 + a1)) {\n ++v14;\n } else if (v17 == *(uint32_t *)(4LL * v15 + a2)) {\n ++v15;\n } else {\n ++v16;\n }\n }\n *a7 = *(uint32_t *)(4LL * v11 + a1);\n a7[1] = *(uint32_t *)(4LL * v12 + a2);\n result = *(unsigned int *)(4LL * v13 + a3);\n a7[2] = result;\n return result;\n}" + }, + { + "index": 938, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int A[], int B[], int C[], int p, int q, int r, int res[3]) {\n int diff = INT_MAX;\n int res_i = 0;\n int res_j = 0;\n int res_k = 0;\n int i = 0;\n int j = 0;\n int k = 0;\n while (i < p && j < q && k < r) {\n int minimum =\n A[i] < B[j] ? (A[i] < C[k] ? A[i] : C[k]) : (B[j] < C[k] ? B[j] : C[k]);\n int maximum =\n A[i] > B[j] ? (A[i] > C[k] ? A[i] : C[k]) : (B[j] > C[k] ? B[j] : C[k]);\n if (maximum - minimum < diff) {\n res_i = i;\n res_j = j;\n res_k = k;\n diff = maximum - minimum;\n }\n if (diff == 0) {\n break;\n }\n if (A[i] == minimum) {\n i++;\n } else if (B[j] == minimum) {\n j++;\n } else {\n k++;\n }\n }\n res[0] = A[res_i];\n res[1] = B[res_j];\n res[2] = C[res_k];\n}", + "test": "int main() {\n\n int res[3];\n\n func0((int[]){1, 4, 10}, (int[]){2, 15, 20}, (int[]){10, 12}, 3, 3, 2, res);\n\n assert(res[0] == 10 && res[1] == 15 && res[2] == 10);\n\n\n\n func0((int[]){20, 24, 100}, (int[]){2, 19, 22, 79, 800}, (int[]){10, 12, 23, 24, 119}, 3, 5, 5, res);\n\n assert(res[0] == 24 && res[1] == 22 && res[2] == 23);\n\n\n\n func0((int[]){2, 5, 11}, (int[]){3, 16, 21}, (int[]){11, 13}, 3, 3, 2, res);\n\n assert(res[0] == 11 && res[1] == 16 && res[2] == 11);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov 0x38(%rsp),%r15\ntest %r8d,%r8d\nsetg %r10b\ntest %r9d,%r9d\nsetg %al\ntest %al,%r10b\nje 1277 \ntest %ecx,%ecx\njle 1277 \nmov $0x0,%ebx\nmov $0x0,%r13d\nmov $0x0,%r12d\nmovl $0x0,-0x4(%rsp)\nmovl $0x0,-0x8(%rsp)\nmovl $0x0,-0xc(%rsp)\nmov $0x7fffffff,%r14d\njmp 122f \nmovslq %ebx,%rax\nmov (%rdx,%rax,4),%eax\ncmp %eax,%r11d\nmov %eax,%ebp\ncmovle %r11d,%ebp\ncmp %r11d,%r10d\njle 1250 \ncmp %eax,%r10d\ncmovge %r10d,%eax\nsub %ebp,%eax\ncmp %r14d,%eax\njge 11fe \nmov %ebx,-0x4(%rsp)\nmov %r13d,-0x8(%rsp)\nmov %r12d,-0xc(%rsp)\nmov %eax,%r14d\ntest %r14d,%r14d\nje 1291 \ncmp %ebp,%r10d\nje 1264 \ncmp %ebp,%r11d\nje 126a \nadd $0x1,%ebx\ncmp %ecx,%r12d\nsetl %r10b\ncmp %r13d,%r8d\nsetg %al\ntest %al,%r10b\nje 12c4 \ncmp %ebx,%r9d\njle 1270 \nmovslq %r12d,%rax\nmov (%rdi,%rax,4),%r10d\nmovslq %r13d,%rax\nmov (%rsi,%rax,4),%r11d\ncmp %r11d,%r10d\njge 11cb \nmovslq %ebx,%rax\ncmp %r10d,(%rdx,%rax,4)\nmov %r10d,%ebp\ncmovle (%rdx,%rax,4),%ebp\nmovslq %ebx,%rax\ncmp %r11d,(%rdx,%rax,4)\nmov %r11d,%r15d\ncmovge (%rdx,%rax,4),%r15d\nmov %r15d,%eax\njmp 11e6 \nadd $0x1,%r12d\njmp 1214 \nadd $0x1,%r13d\njmp 1214 \nmov 0x38(%rsp),%r15\njmp 1296 \nmovl $0x0,-0x4(%rsp)\nmovl $0x0,-0x8(%rsp)\nmovl $0x0,-0xc(%rsp)\njmp 1296 \nmov 0x38(%rsp),%r15\nmovslq -0xc(%rsp),%rax\nmov (%rdi,%rax,4),%eax\nmov %eax,(%r15)\nmovslq -0x8(%rsp),%rax\nmov (%rsi,%rax,4),%eax\nmov %eax,0x4(%r15)\nmovslq -0x4(%rsp),%rax\nmov (%rdx,%rax,4),%eax\nmov %eax,0x8(%r15)\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmov 0x38(%rsp),%r15\njmp 1296 \n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r12, rdi\nmov r13, rsi\nmov rbx, rdx\nmov r14d, ecx\nmov rdx, [rsp+30h+arg_0]\ntest r8d, r8d\nsetnle cl\ntest r9d, r9d\nsetnle al\ntest cl, al\njz loc_1267\ntest r14d, r14d\njle loc_1267\nmov edi, 0\nmov r11d, 0\nmov r10d, 0\nmov [rsp+30h+var_34], 0\nmov [rsp+30h+var_38], 0\nmov r15d, 0\nmov ebp, 7FFFFFFFh\njmp short loc_1229\nloc_11D3:\nmovsxd rax, edi\nmov eax, [rbx+rax*4]\ncmp ecx, eax\nmov esi, eax\ncmovle esi, ecx\ncmp edx, ecx\njle short loc_1247\ncmp edx, eax\ncmovge eax, edx\nloc_11E9:\nsub eax, esi\ncmp eax, ebp\njge short loc_1205\ntest eax, eax\njz loc_127F\nmov [rsp+30h+var_34], edi\nmov [rsp+30h+var_38], r11d\nmov r15d, r10d\nmov ebp, eax\nloc_1205:\ncmp edx, esi\njz short loc_1254\ncmp ecx, esi\njz short loc_125A\nadd edi, 1\nloc_1210:\ncmp r10d, r14d\nsetl dl\ncmp r8d, r11d\nsetnle al\ntest dl, al\njz loc_12BC\ncmp r9d, edi\njle short loc_1260\nloc_1229:\nmovsxd rax, r10d\nmov edx, [r12+rax*4]\nmovsxd rax, r11d\nmov ecx, [r13+rax*4+0]\ncmp edx, ecx\njge short loc_11D3\nmovsxd rax, edi\nmov esi, [rbx+rax*4]\ncmp edx, esi\ncmovle esi, edx\nloc_1247:\nmovsxd rax, edi\nmov eax, [rbx+rax*4]\ncmp ecx, eax\ncmovge eax, ecx\njmp short loc_11E9\nloc_1254:\nadd r10d, 1\njmp short loc_1210\nloc_125A:\nadd r11d, 1\njmp short loc_1210\nloc_1260:\nmov rdx, [rsp+30h+arg_0]\njmp short loc_1290\nloc_1267:\nmov [rsp+30h+var_34], 0\nmov [rsp+30h+var_38], 0\nmov r15d, 0\njmp short loc_1290\nloc_127F:\nmov rdx, [rsp+30h+arg_0]\nmov [rsp+30h+var_34], edi\nmov [rsp+30h+var_38], r11d\nmov r15d, r10d\nloc_1290:\nmovsxd r15, r15d\nmov eax, [r12+r15*4]\nmov [rdx], eax\nmovsxd rax, [rsp+30h+var_38]\nmov eax, [r13+rax*4+0]\nmov [rdx+4], eax\nmovsxd rax, [rsp+30h+var_34]\nmov eax, [rbx+rax*4]\nmov [rdx+8], eax\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_12BC:\nmov rdx, [rsp+30h+arg_0]\njmp short loc_1290", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, __int64 a2, __int64 a3, int a4, int a5, int a6, _DWORD *a7)\n{\n _DWORD *v11; // rdx\n int v12; // edi\n int v13; // r11d\n int v14; // r10d\n int v15; // r15d\n int v16; // ebp\n int v17; // eax\n int v18; // esi\n int v19; // eax\n int v20; // edx\n int v21; // ecx\n __int64 result; // rax\n int v23; // [rsp+0h] [rbp-38h]\n int v24; // [rsp+4h] [rbp-34h]\n\n v11 = a7;\n if ( a6 > 0 && a5 > 0 && a4 > 0 )\n {\n v12 = 0;\n v13 = 0;\n v14 = 0;\n v24 = 0;\n v23 = 0;\n v15 = 0;\n v16 = 0x7FFFFFFF;\n while ( 1 )\n {\n v20 = *(_DWORD *)(a1 + 4LL * v14);\n v21 = *(_DWORD *)(a2 + 4LL * v13);\n if ( v20 < v21 )\n break;\n v17 = *(_DWORD *)(a3 + 4LL * v12);\n v18 = v17;\n if ( v21 <= v17 )\n v18 = *(_DWORD *)(a2 + 4LL * v13);\n if ( v20 <= v21 )\n goto LABEL_20;\n if ( v20 >= v17 )\n v17 = *(_DWORD *)(a1 + 4LL * v14);\nLABEL_9:\n v19 = v17 - v18;\n if ( v19 < v16 )\n {\n if ( !v19 )\n {\n v11 = a7;\n v24 = v12;\n v23 = v13;\n v15 = v14;\n goto LABEL_28;\n }\n v24 = v12;\n v23 = v13;\n v15 = v14;\n v16 = v19;\n }\n if ( v20 == v18 )\n {\n ++v14;\n }\n else if ( v21 == v18 )\n {\n ++v13;\n }\n else\n {\n ++v12;\n }\n if ( a5 <= v13 || v14 >= a4 )\n {\n v11 = a7;\n goto LABEL_28;\n }\n if ( a6 <= v12 )\n {\n v11 = a7;\n goto LABEL_28;\n }\n }\n v18 = *(_DWORD *)(a3 + 4LL * v12);\n if ( v20 <= v18 )\n v18 = *(_DWORD *)(a1 + 4LL * v14);\nLABEL_20:\n v17 = *(_DWORD *)(a3 + 4LL * v12);\n if ( v21 >= v17 )\n v17 = *(_DWORD *)(a2 + 4LL * v13);\n goto LABEL_9;\n }\n v24 = 0;\n v23 = 0;\n v15 = 0;\nLABEL_28:\n *v11 = *(_DWORD *)(a1 + 4LL * v15);\n v11[1] = *(_DWORD *)(a2 + 4LL * v23);\n result = *(unsigned int *)(a3 + 4LL * v24);\n v11[2] = result;\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov r12, rdi\nmov r13, rsi\nmov rbx, rdx\nmov r14d, ecx\nmov rdx, [rsp+30h+arg_0]\ntest r8d, r8d\nsetnle cl\ntest r9d, r9d\nsetnle al\ntest cl, al\njz loc_1267\ntest r14d, r14d\njle loc_1267\nmov edi, 0\nmov r11d, 0\nmov r10d, 0\nmov [rsp+30h+var_34], 0\nmov [rsp+30h+var_38], 0\nmov r15d, 0\nmov ebp, 7FFFFFFFh\njmp short loc_1229\nloc_11D3:\nmovsxd rax, edi\nmov eax, [rbx+rax*4]\ncmp ecx, eax\nmov esi, eax\ncmovle esi, ecx\ncmp edx, ecx\njle short loc_1247\ncmp edx, eax\ncmovge eax, edx\nloc_11E9:\nsub eax, esi\ncmp eax, ebp\njge short loc_1205\ntest eax, eax\njz loc_127F\nmov [rsp+30h+var_34], edi\nmov [rsp+30h+var_38], r11d\nmov r15d, r10d\nmov ebp, eax\nloc_1205:\ncmp edx, esi\njz short loc_1254\ncmp ecx, esi\njz short loc_125A\nadd edi, 1\nloc_1210:\ncmp r10d, r14d\nsetl dl\ncmp r8d, r11d\nsetnle al\ntest dl, al\njz loc_12BC\ncmp r9d, edi\njle short loc_1260\nloc_1229:\nmovsxd rax, r10d\nmov edx, [r12+rax*4]\nmovsxd rax, r11d\nmov ecx, [r13+rax*4+0]\ncmp edx, ecx\njge short loc_11D3\nmovsxd rax, edi\nmov esi, [rbx+rax*4]\ncmp edx, esi\ncmovle esi, edx\nloc_1247:\nmovsxd rax, edi\nmov eax, [rbx+rax*4]\ncmp ecx, eax\ncmovge eax, ecx\njmp short loc_11E9\nloc_1254:\nadd r10d, 1\njmp short loc_1210\nloc_125A:\nadd r11d, 1\njmp short loc_1210\nloc_1260:\nmov rdx, [rsp+30h+arg_0]\njmp short loc_1290\nloc_1267:\nmov [rsp+30h+var_34], 0\nmov [rsp+30h+var_38], 0\nmov r15d, 0\njmp short loc_1290\nloc_127F:\nmov rdx, [rsp+30h+arg_0]\nmov [rsp+30h+var_34], edi\nmov [rsp+30h+var_38], r11d\nmov r15d, r10d\nloc_1290:\nmovsxd r15, r15d\nmov eax, [r12+r15*4]\nmov [rdx], eax\nmovsxd rax, [rsp+30h+var_38]\nmov eax, [r13+rax*4+0]\nmov [rdx+4], eax\nmovsxd rax, [rsp+30h+var_34]\nmov eax, [rbx+rax*4]\nmov [rdx+8], eax\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_12BC:\nmov rdx, [rsp+30h+arg_0]\njmp short loc_1290", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, __int64 a2, __int64 a3, int a4, int a5, int a6, _DWORD *a7)\n{\n _DWORD *v11; // rdx\n int v12; // edi\n int v13; // r11d\n int v14; // r10d\n int v15; // r15d\n int v16; // ebp\n int v17; // eax\n int v18; // esi\n int v19; // eax\n int v20; // edx\n int v21; // ecx\n __int64 result; // rax\n int v23; // [rsp+0h] [rbp-38h]\n int v24; // [rsp+4h] [rbp-34h]\n\n v11 = a7;\n if ( a6 > 0 && a5 > 0 && a4 > 0 )\n {\n v12 = 0;\n v13 = 0;\n v14 = 0;\n v24 = 0;\n v23 = 0;\n v15 = 0;\n v16 = 0x7FFFFFFF;\n while ( 1 )\n {\n v20 = *(_DWORD *)(a1 + 4LL * v14);\n v21 = *(_DWORD *)(a2 + 4LL * v13);\n if ( v20 < v21 )\n break;\n v17 = *(_DWORD *)(a3 + 4LL * v12);\n v18 = v17;\n if ( v21 <= v17 )\n v18 = *(_DWORD *)(a2 + 4LL * v13);\n if ( v20 <= v21 )\n goto LABEL_20;\n if ( v20 >= v17 )\n v17 = *(_DWORD *)(a1 + 4LL * v14);\nLABEL_9:\n v19 = v17 - v18;\n if ( v19 < v16 )\n {\n if ( !v19 )\n {\n v11 = a7;\n v24 = v12;\n v23 = v13;\n v15 = v14;\n goto LABEL_28;\n }\n v24 = v12;\n v23 = v13;\n v15 = v14;\n v16 = v19;\n }\n if ( v20 == v18 )\n {\n ++v14;\n }\n else if ( v21 == v18 )\n {\n ++v13;\n }\n else\n {\n ++v12;\n }\n if ( a5 <= v13 || v14 >= a4 )\n {\n v11 = a7;\n goto LABEL_28;\n }\n if ( a6 <= v12 )\n {\n v11 = a7;\n goto LABEL_28;\n }\n }\n v18 = *(_DWORD *)(a3 + 4LL * v12);\n if ( v20 <= v18 )\n v18 = *(_DWORD *)(a1 + 4LL * v14);\nLABEL_20:\n v17 = *(_DWORD *)(a3 + 4LL * v12);\n if ( v21 >= v17 )\n v17 = *(_DWORD *)(a2 + 4LL * v13);\n goto LABEL_9;\n }\n v24 = 0;\n v23 = 0;\n v15 = 0;\nLABEL_28:\n *v11 = *(_DWORD *)(a1 + 4LL * v15);\n v11[1] = *(_DWORD *)(a2 + 4LL * v23);\n result = *(unsigned int *)(a3 + 4LL * v24);\n v11[2] = result;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, long long a2, long long a3, int a4, int a5,\n int a6, uint32_t *a7) {\n uint32_t *v11;\n int v12;\n int v13;\n int v14;\n int v15;\n int v16;\n int v17;\n int v18;\n int v19;\n int v20;\n int v21;\n long long result;\n int v23;\n int v24;\n v11 = a7;\n if (a6 > 0 && a5 > 0 && a4 > 0) {\n v12 = 0;\n v13 = 0;\n v14 = 0;\n v24 = 0;\n v23 = 0;\n v15 = 0;\n v16 = 2147483647;\n while (1) {\n v20 = *(uint32_t *)(a1 + 4LL * v14);\n v21 = *(uint32_t *)(a2 + 4LL * v13);\n if (v20 < v21) break;\n v17 = *(uint32_t *)(a3 + 4LL * v12);\n v18 = v17;\n if (v21 <= v17) v18 = *(uint32_t *)(a2 + 4LL * v13);\n if (v20 <= v21) goto LABEL_20;\n if (v20 >= v17) v17 = *(uint32_t *)(a1 + 4LL * v14);\n LABEL_9:\n v19 = v17 - v18;\n if (v19 < v16) {\n if (!v19) {\n v11 = a7;\n v24 = v12;\n v23 = v13;\n v15 = v14;\n goto LABEL_28;\n }\n v24 = v12;\n v23 = v13;\n v15 = v14;\n v16 = v19;\n }\n if (v20 == v18) {\n ++v14;\n } else if (v21 == v18) {\n ++v13;\n } else {\n ++v12;\n }\n if (a5 <= v13 || v14 >= a4) {\n v11 = a7;\n goto LABEL_28;\n }\n if (a6 <= v12) {\n v11 = a7;\n goto LABEL_28;\n }\n }\n v18 = *(uint32_t *)(a3 + 4LL * v12);\n if (v20 <= v18) v18 = *(uint32_t *)(a1 + 4LL * v14);\n LABEL_20:\n v17 = *(uint32_t *)(a3 + 4LL * v12);\n if (v21 >= v17) v17 = *(uint32_t *)(a2 + 4LL * v13);\n goto LABEL_9;\n }\n v24 = 0;\n v23 = 0;\n v15 = 0;\nLABEL_28:\n *v11 = *(uint32_t *)(a1 + 4LL * v15);\n v11[1] = *(uint32_t *)(a2 + 4LL * v23);\n result = *(unsigned int *)(a3 + 4LL * v24);\n v11[2] = result;\n return result;\n}", + "ida_pseudo_norm": "long long func0(long long a1, long long a2, long long a3, int a4, int a5,\n int a6, uint32_t *a7) {\n uint32_t *v11;\n int v12;\n int v13;\n int v14;\n int v15;\n int v16;\n int v17;\n int v18;\n int v19;\n int v20;\n int v21;\n long long result;\n int v23;\n int v24;\n v11 = a7;\n if (a6 > 0 && a5 > 0 && a4 > 0) {\n v12 = 0;\n v13 = 0;\n v14 = 0;\n v24 = 0;\n v23 = 0;\n v15 = 0;\n v16 = 2147483647;\n while (1) {\n v20 = *(uint32_t *)(a1 + 4LL * v14);\n v21 = *(uint32_t *)(a2 + 4LL * v13);\n if (v20 < v21) break;\n v17 = *(uint32_t *)(a3 + 4LL * v12);\n v18 = v17;\n if (v21 <= v17) v18 = *(uint32_t *)(a2 + 4LL * v13);\n if (v20 <= v21) goto LABEL_20;\n if (v20 >= v17) v17 = *(uint32_t *)(a1 + 4LL * v14);\n LABEL_9:\n v19 = v17 - v18;\n if (v19 < v16) {\n if (!v19) {\n v11 = a7;\n v24 = v12;\n v23 = v13;\n v15 = v14;\n goto LABEL_28;\n }\n v24 = v12;\n v23 = v13;\n v15 = v14;\n v16 = v19;\n }\n if (v20 == v18) {\n ++v14;\n } else if (v21 == v18) {\n ++v13;\n } else {\n ++v12;\n }\n if (a5 <= v13 || v14 >= a4) {\n v11 = a7;\n goto LABEL_28;\n }\n if (a6 <= v12) {\n v11 = a7;\n goto LABEL_28;\n }\n }\n v18 = *(uint32_t *)(a3 + 4LL * v12);\n if (v20 <= v18) v18 = *(uint32_t *)(a1 + 4LL * v14);\n LABEL_20:\n v17 = *(uint32_t *)(a3 + 4LL * v12);\n if (v21 >= v17) v17 = *(uint32_t *)(a2 + 4LL * v13);\n goto LABEL_9;\n }\n v24 = 0;\n v23 = 0;\n v15 = 0;\nLABEL_28:\n *v11 = *(uint32_t *)(a1 + 4LL * v15);\n v11[1] = *(uint32_t *)(a2 + 4LL * v23);\n result = *(unsigned int *)(a3 + 4LL * v24);\n v11[2] = result;\n return result;\n}" + }, + { + "index": 938, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int A[], int B[], int C[], int p, int q, int r, int res[3]) {\n int diff = INT_MAX;\n int res_i = 0;\n int res_j = 0;\n int res_k = 0;\n int i = 0;\n int j = 0;\n int k = 0;\n while (i < p && j < q && k < r) {\n int minimum =\n A[i] < B[j] ? (A[i] < C[k] ? A[i] : C[k]) : (B[j] < C[k] ? B[j] : C[k]);\n int maximum =\n A[i] > B[j] ? (A[i] > C[k] ? A[i] : C[k]) : (B[j] > C[k] ? B[j] : C[k]);\n if (maximum - minimum < diff) {\n res_i = i;\n res_j = j;\n res_k = k;\n diff = maximum - minimum;\n }\n if (diff == 0) {\n break;\n }\n if (A[i] == minimum) {\n i++;\n } else if (B[j] == minimum) {\n j++;\n } else {\n k++;\n }\n }\n res[0] = A[res_i];\n res[1] = B[res_j];\n res[2] = C[res_k];\n}", + "test": "int main() {\n\n int res[3];\n\n func0((int[]){1, 4, 10}, (int[]){2, 15, 20}, (int[]){10, 12}, 3, 3, 2, res);\n\n assert(res[0] == 10 && res[1] == 15 && res[2] == 10);\n\n\n\n func0((int[]){20, 24, 100}, (int[]){2, 19, 22, 79, 800}, (int[]){10, 12, 23, 24, 119}, 3, 5, 5, res);\n\n assert(res[0] == 24 && res[1] == 22 && res[2] == 23);\n\n\n\n func0((int[]){2, 5, 11}, (int[]){3, 16, 21}, (int[]){11, 13}, 3, 3, 2, res);\n\n assert(res[0] == 11 && res[1] == 16 && res[2] == 11);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov %r9d,%eax\npush %r15\ntest %eax,%eax\npush %r14\npush %r13\nsetg %r10b\ntest %r8d,%r8d\npush %r12\nsetg %al\npush %rbp\npush %rbx\nmov %r9d,-0x10(%rsp)\nmov (%rdi),%r9d\ntest %al,%r10b\nje 1510 \ntest %ecx,%ecx\njle 1510 \nmovl $0x0,-0x4(%rsp)\nxor %ebx,%ebx\nxor %r12d,%r12d\nxor %ebp,%ebp\nmovl $0x0,-0xc(%rsp)\nmov $0x7fffffff,%r15d\nmovl $0x0,-0x8(%rsp)\njmp 148c \nnopl (%rax)\ncmp %r9d,%eax\nmov %r9d,%r11d\ncmovle %eax,%r11d\ncmp %eax,%r10d\ncmovge %r10d,%eax\nsub %r11d,%eax\ncmp %r15d,%eax\njge 1461 \ntest %eax,%eax\nje 14eb \nmov %ebx,-0x4(%rsp)\nmov %eax,%r15d\nmov %r12d,-0xc(%rsp)\nmov %ebp,-0x8(%rsp)\ncmp %r9d,%r11d\nje 14c0 \ncmp %r11d,%r10d\nje 14c8 \nadd $0x1,%ebx\ncmp %ebp,%ecx\nsetg %r9b\ncmp %r8d,%r12d\nsetl %al\ntest %al,%r9b\nje 14d0 \ncmp -0x10(%rsp),%ebx\njge 14d0 \nmovslq %ebp,%rax\nmov (%rdi,%rax,4),%r9d\nmovslq %r12d,%rax\nlea (%rsi,%rax,4),%r14\nmovslq %ebx,%rax\nmov (%r14),%r10d\nlea (%rdx,%rax,4),%r13\nmov 0x0(%r13),%eax\ncmp %r9d,%r10d\njg 1430 \ncmp %eax,%r10d\nmov %eax,%r11d\ncmovle %r10d,%r11d\ncmp %r9d,%r10d\njge 143a \ncmp %r9d,%eax\ncmovl %r9d,%eax\njmp 1441 \nxchg %ax,%ax\nadd $0x1,%ebp\njmp 146e \nnopl (%rax)\nadd $0x1,%r12d\njmp 146e \nxchg %ax,%ax\nmovslq -0x8(%rsp),%rax\nmov (%rdi,%rax,4),%r9d\nmovslq -0xc(%rsp),%rax\nlea (%rsi,%rax,4),%r14\nmovslq -0x4(%rsp),%rax\nlea (%rdx,%rax,4),%r13\nmov 0x38(%rsp),%rax\nmov 0x38(%rsp),%rcx\nmov %r9d,(%rax)\nmov (%r14),%eax\nmov %eax,0x4(%rcx)\nmov 0x0(%r13),%eax\nmov %eax,0x8(%rcx)\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmov %rdx,%r13\nmov %rsi,%r14\njmp 14eb \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\ntest r9d, r9d\npush r14\nmov r14, rdx\npush r13\nmov r13, rsi\nsetnle sil\ntest r8d, r8d\npush r12\npush rbp\npush rbx\nmov ebx, ecx\nmov rax, [rsp+30h+arg_0]\nmov edx, [rdi]\nmov [rsp+30h+var_40], ecx\nsetnle cl\ntest sil, cl\njz loc_14F7\ntest ebx, ebx\njle loc_14F7\nmov r12, rdi\nmov [rsp+30h+var_34], 0\nxor edi, edi\nxor r11d, r11d\nmov [rsp+30h+var_38], 0\nxor r10d, r10d\nmov r15d, 7FFFFFFFh\nmov [rsp+30h+var_3C], 0\njmp short loc_145E\nloc_1410:\ncmp edx, eax\nmov esi, eax\ncmovle esi, edx\nloc_1417:\ncmp ecx, eax\ncmovge eax, ecx\nloc_141C:\nsub eax, esi\ncmp r15d, eax\njle short loc_143C\ntest eax, eax\njz loc_14F0\nmov [rsp+30h+var_34], edi\nmov r15d, eax\nmov [rsp+30h+var_38], r11d\nmov [rsp+30h+var_3C], r10d\nloc_143C:\ncmp edx, esi\njz short loc_1490\ncmp ecx, esi\njz short loc_14A0\nadd edi, 1\nloc_1447:\ncmp [rsp+30h+var_40], r10d\nsetnle dl\ncmp r11d, r8d\nsetl al\ntest dl, al\njz short loc_14B0\ncmp edi, r9d\njge short loc_14B0\nloc_145E:\nmovsxd rax, r10d\nmov edx, [r12+rax*4]\nmovsxd rax, r11d\nlea rbp, [r13+rax*4+0]\nmovsxd rax, edi\nmov ecx, [rbp+0]\nlea rbx, [r14+rax*4]\nmov eax, [rbx]\ncmp edx, ecx\njl short loc_1410\ncmp ecx, eax\nmov esi, eax\ncmovle esi, ecx\ncmp edx, ecx\njle short loc_1417\ncmp edx, eax\ncmovge eax, edx\njmp short loc_141C\nloc_1490:\nadd r10d, 1\njmp short loc_1447\nloc_14A0:\nadd r11d, 1\njmp short loc_1447\nloc_14B0:\nmovsxd rcx, [rsp+30h+var_38]\nmovsxd rdx, [rsp+30h+var_3C]\nmov rax, [rsp+30h+arg_0]\nlea rbp, [r13+rcx*4+0]\nmovsxd rcx, [rsp+30h+var_34]\nmov edx, [r12+rdx*4]\nlea rbx, [r14+rcx*4]\nloc_14D1:\nmov [rax], edx\nmov edx, [rbp+0]\nmov [rax+4], edx\nmov edx, [rbx]\nmov [rax+8], edx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14F0:\nmov rax, [rsp+30h+arg_0]\njmp short loc_14D1\nloc_14F7:\nmov rbx, r14\nmov rbp, r13\njmp short loc_14D1", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int *a2, int *a3, int a4, int a5, int a6, _DWORD *a7)\n{\n _DWORD *result; // rax\n int v10; // edx\n int v12; // edi\n int v13; // r11d\n int v14; // r10d\n int v15; // r15d\n int v16; // esi\n int v17; // eax\n int v18; // eax\n int *v19; // rbp\n int v20; // ecx\n int *v21; // rbx\n int v23; // [rsp+4h] [rbp-3Ch]\n int v24; // [rsp+8h] [rbp-38h]\n int v25; // [rsp+Ch] [rbp-34h]\n\n result = a7;\n v10 = *a1;\n if ( a5 <= 0 || a6 <= 0 || a4 <= 0 )\n {\n v21 = a3;\n v19 = a2;\n goto LABEL_26;\n }\n v25 = 0;\n v12 = 0;\n v13 = 0;\n v24 = 0;\n v14 = 0;\n v15 = 0x7FFFFFFF;\n v23 = 0;\n while ( 1 )\n {\n v10 = a1[v14];\n v19 = &a2[v13];\n v20 = *v19;\n v21 = &a3[v12];\n v17 = *v21;\n if ( v10 < *v19 )\n {\n v16 = *v21;\n if ( v10 <= v17 )\n v16 = a1[v14];\n }\n else\n {\n v16 = *v21;\n if ( v20 <= v17 )\n v16 = *v19;\n if ( v10 > v20 )\n {\n if ( v10 >= v17 )\n v17 = a1[v14];\n goto LABEL_8;\n }\n }\n if ( v20 >= v17 )\n v17 = *v19;\nLABEL_8:\n v18 = v17 - v16;\n if ( v15 > v18 )\n break;\nLABEL_11:\n if ( v10 == v16 )\n {\n ++v14;\n }\n else if ( v20 == v16 )\n {\n ++v13;\n }\n else\n {\n ++v12;\n }\n if ( v13 >= a5 || a4 <= v14 || v12 >= a6 )\n {\n result = a7;\n v19 = &a2[v24];\n v10 = a1[v23];\n v21 = &a3[v25];\n goto LABEL_26;\n }\n }\n if ( v18 )\n {\n v25 = v12;\n v15 = v18;\n v24 = v13;\n v23 = v14;\n goto LABEL_11;\n }\n result = a7;\nLABEL_26:\n *result = v10;\n result[1] = *v19;\n result[2] = *v21;\n return result;\n}", + "ida_strip_asm": "sub_13A0:\nendbr64\npush r15\ntest r9d, r9d\npush r14\nmov r14, rdx\npush r13\nmov r13, rsi\nsetnle sil\ntest r8d, r8d\npush r12\npush rbp\npush rbx\nmov ebx, ecx\nmov rax, [rsp+30h+arg_0]\nmov edx, [rdi]\nmov [rsp+30h+var_40], ecx\nsetnle cl\ntest sil, cl\njz loc_14F7\ntest ebx, ebx\njle loc_14F7\nmov r12, rdi\nmov [rsp+30h+var_34], 0\nxor edi, edi\nxor r11d, r11d\nmov [rsp+30h+var_38], 0\nxor r10d, r10d\nmov r15d, 7FFFFFFFh\nmov [rsp+30h+var_3C], 0\njmp short loc_145E\nloc_1410:\ncmp edx, eax\nmov esi, eax\ncmovle esi, edx\nloc_1417:\ncmp ecx, eax\ncmovge eax, ecx\nloc_141C:\nsub eax, esi\ncmp r15d, eax\njle short loc_143C\ntest eax, eax\njz loc_14F0\nmov [rsp+30h+var_34], edi\nmov r15d, eax\nmov [rsp+30h+var_38], r11d\nmov [rsp+30h+var_3C], r10d\nloc_143C:\ncmp edx, esi\njz short loc_1490\ncmp ecx, esi\njz short loc_14A0\nadd edi, 1\nloc_1447:\ncmp [rsp+30h+var_40], r10d\nsetnle dl\ncmp r11d, r8d\nsetl al\ntest dl, al\njz short loc_14B0\ncmp edi, r9d\njge short loc_14B0\nloc_145E:\nmovsxd rax, r10d\nmov edx, [r12+rax*4]\nmovsxd rax, r11d\nlea rbp, [r13+rax*4+0]\nmovsxd rax, edi\nmov ecx, [rbp+0]\nlea rbx, [r14+rax*4]\nmov eax, [rbx]\ncmp edx, ecx\njl short loc_1410\ncmp ecx, eax\nmov esi, eax\ncmovle esi, ecx\ncmp edx, ecx\njle short loc_1417\ncmp edx, eax\ncmovge eax, edx\njmp short loc_141C\nloc_1490:\nadd r10d, 1\njmp short loc_1447\nloc_14A0:\nadd r11d, 1\njmp short loc_1447\nloc_14B0:\nmovsxd rcx, [rsp+30h+var_38]\nmovsxd rdx, [rsp+30h+var_3C]\nmov rax, [rsp+30h+arg_0]\nlea rbp, [r13+rcx*4+0]\nmovsxd rcx, [rsp+30h+var_34]\nmov edx, [r12+rdx*4]\nlea rbx, [r14+rcx*4]\nloc_14D1:\nmov [rax], edx\nmov edx, [rbp+0]\nmov [rax+4], edx\nmov edx, [rbx]\nmov [rax+8], edx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14F0:\nmov rax, [rsp+30h+arg_0]\njmp short loc_14D1\nloc_14F7:\nmov rbx, r14\nmov rbp, r13\njmp short loc_14D1", + "ida_strip_pseudo": "_DWORD *__fastcall sub_13A0(int *a1, int *a2, int *a3, int a4, int a5, int a6, _DWORD *a7)\n{\n _DWORD *result; // rax\n int v10; // edx\n int v12; // edi\n int v13; // r11d\n int v14; // r10d\n int v15; // r15d\n int v16; // esi\n int v17; // eax\n int v18; // eax\n int *v19; // rbp\n int v20; // ecx\n int *v21; // rbx\n int v23; // [rsp+4h] [rbp-3Ch]\n int v24; // [rsp+8h] [rbp-38h]\n int v25; // [rsp+Ch] [rbp-34h]\n\n result = a7;\n v10 = *a1;\n if ( a5 <= 0 || a6 <= 0 || a4 <= 0 )\n {\n v21 = a3;\n v19 = a2;\n goto LABEL_26;\n }\n v25 = 0;\n v12 = 0;\n v13 = 0;\n v24 = 0;\n v14 = 0;\n v15 = 0x7FFFFFFF;\n v23 = 0;\n while ( 1 )\n {\n v10 = a1[v14];\n v19 = &a2[v13];\n v20 = *v19;\n v21 = &a3[v12];\n v17 = *v21;\n if ( v10 < *v19 )\n {\n v16 = *v21;\n if ( v10 <= v17 )\n v16 = a1[v14];\n }\n else\n {\n v16 = *v21;\n if ( v20 <= v17 )\n v16 = *v19;\n if ( v10 > v20 )\n {\n if ( v10 >= v17 )\n v17 = a1[v14];\n goto LABEL_8;\n }\n }\n if ( v20 >= v17 )\n v17 = *v19;\nLABEL_8:\n v18 = v17 - v16;\n if ( v15 > v18 )\n break;\nLABEL_11:\n if ( v10 == v16 )\n {\n ++v14;\n }\n else if ( v20 == v16 )\n {\n ++v13;\n }\n else\n {\n ++v12;\n }\n if ( v13 >= a5 || a4 <= v14 || v12 >= a6 )\n {\n result = a7;\n v19 = &a2[v24];\n v10 = a1[v23];\n v21 = &a3[v25];\n goto LABEL_26;\n }\n }\n if ( v18 )\n {\n v25 = v12;\n v15 = v18;\n v24 = v13;\n v23 = v14;\n goto LABEL_11;\n }\n result = a7;\nLABEL_26:\n *result = v10;\n result[1] = *v19;\n result[2] = *v21;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_13A0(int *a1, int *a2, int *a3, int a4, int a5, int a6,\n uint32_t *a7) {\n uint32_t *result;\n int v10;\n int v12;\n int v13;\n int v14;\n int v15;\n int v16;\n int v17;\n int v18;\n int *v19;\n int v20;\n int *v21;\n int v23;\n int v24;\n int v25;\n result = a7;\n v10 = *a1;\n if (a5 <= 0 || a6 <= 0 || a4 <= 0) {\n v21 = a3;\n v19 = a2;\n goto LABEL_26;\n }\n v25 = 0;\n v12 = 0;\n v13 = 0;\n v24 = 0;\n v14 = 0;\n v15 = 2147483647;\n v23 = 0;\n while (1) {\n v10 = a1[v14];\n v19 = &a2[v13];\n v20 = *v19;\n v21 = &a3[v12];\n v17 = *v21;\n if (v10 < *v19) {\n v16 = *v21;\n if (v10 <= v17) v16 = a1[v14];\n } else {\n v16 = *v21;\n if (v20 <= v17) v16 = *v19;\n if (v10 > v20) {\n if (v10 >= v17) v17 = a1[v14];\n goto LABEL_8;\n }\n }\n if (v20 >= v17) v17 = *v19;\n LABEL_8:\n v18 = v17 - v16;\n if (v15 > v18) break;\n LABEL_11:\n if (v10 == v16) {\n ++v14;\n } else if (v20 == v16) {\n ++v13;\n } else {\n ++v12;\n }\n if (v13 >= a5 || a4 <= v14 || v12 >= a6) {\n result = a7;\n v19 = &a2[v24];\n v10 = a1[v23];\n v21 = &a3[v25];\n goto LABEL_26;\n }\n }\n if (v18) {\n v25 = v12;\n v15 = v18;\n v24 = v13;\n v23 = v14;\n goto LABEL_11;\n }\n result = a7;\nLABEL_26:\n *result = v10;\n result[1] = *v19;\n result[2] = *v21;\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int *a2, int *a3, int a4, int a5, int a6,\n uint32_t *a7) {\n uint32_t *result;\n int v10;\n int v12;\n int v13;\n int v14;\n int v15;\n int v16;\n int v17;\n int v18;\n int *v19;\n int v20;\n int *v21;\n int v23;\n int v24;\n int v25;\n result = a7;\n v10 = *a1;\n if (a5 <= 0 || a6 <= 0 || a4 <= 0) {\n v21 = a3;\n v19 = a2;\n goto LABEL_26;\n }\n v25 = 0;\n v12 = 0;\n v13 = 0;\n v24 = 0;\n v14 = 0;\n v15 = 2147483647;\n v23 = 0;\n while (1) {\n v10 = a1[v14];\n v19 = &a2[v13];\n v20 = *v19;\n v21 = &a3[v12];\n v17 = *v21;\n if (v10 < *v19) {\n v16 = *v21;\n if (v10 <= v17) v16 = a1[v14];\n } else {\n v16 = *v21;\n if (v20 <= v17) v16 = *v19;\n if (v10 > v20) {\n if (v10 >= v17) v17 = a1[v14];\n goto LABEL_8;\n }\n }\n if (v20 >= v17) v17 = *v19;\n LABEL_8:\n v18 = v17 - v16;\n if (v15 > v18) break;\n LABEL_11:\n if (v10 == v16) {\n ++v14;\n } else if (v20 == v16) {\n ++v13;\n } else {\n ++v12;\n }\n if (v13 >= a5 || a4 <= v14 || v12 >= a6) {\n result = a7;\n v19 = &a2[v24];\n v10 = a1[v23];\n v21 = &a3[v25];\n goto LABEL_26;\n }\n }\n if (v18) {\n v25 = v12;\n v15 = v18;\n v24 = v13;\n v23 = v14;\n goto LABEL_11;\n }\n result = a7;\nLABEL_26:\n *result = v10;\n result[1] = *v19;\n result[2] = *v21;\n return result;\n}" + }, + { + "index": 938, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "void func0(int A[], int B[], int C[], int p, int q, int r, int res[3]) {\n int diff = INT_MAX;\n int res_i = 0;\n int res_j = 0;\n int res_k = 0;\n int i = 0;\n int j = 0;\n int k = 0;\n while (i < p && j < q && k < r) {\n int minimum =\n A[i] < B[j] ? (A[i] < C[k] ? A[i] : C[k]) : (B[j] < C[k] ? B[j] : C[k]);\n int maximum =\n A[i] > B[j] ? (A[i] > C[k] ? A[i] : C[k]) : (B[j] > C[k] ? B[j] : C[k]);\n if (maximum - minimum < diff) {\n res_i = i;\n res_j = j;\n res_k = k;\n diff = maximum - minimum;\n }\n if (diff == 0) {\n break;\n }\n if (A[i] == minimum) {\n i++;\n } else if (B[j] == minimum) {\n j++;\n } else {\n k++;\n }\n }\n res[0] = A[res_i];\n res[1] = B[res_j];\n res[2] = C[res_k];\n}", + "test": "int main() {\n\n int res[3];\n\n func0((int[]){1, 4, 10}, (int[]){2, 15, 20}, (int[]){10, 12}, 3, 3, 2, res);\n\n assert(res[0] == 10 && res[1] == 15 && res[2] == 10);\n\n\n\n func0((int[]){20, 24, 100}, (int[]){2, 19, 22, 79, 800}, (int[]){10, 12, 23, 24, 119}, 3, 5, 5, res);\n\n assert(res[0] == 24 && res[1] == 22 && res[2] == 23);\n\n\n\n func0((int[]){2, 5, 11}, (int[]){3, 16, 21}, (int[]){11, 13}, 3, 3, 2, res);\n\n assert(res[0] == 11 && res[1] == 16 && res[2] == 11);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nmov %r9d,%eax\npush %r15\ntest %eax,%eax\npush %r14\npush %r13\nsetg %r10b\ntest %r8d,%r8d\npush %r12\nsetg %al\npush %rbp\npush %rbx\nmov %r9d,-0x10(%rsp)\nmov (%rdi),%r9d\ntest %al,%r10b\nje 14f0 \ntest %ecx,%ecx\njle 14f0 \nmovl $0x0,-0x4(%rsp)\nxor %ebx,%ebx\nxor %r12d,%r12d\nxor %ebp,%ebp\nmovl $0x0,-0xc(%rsp)\nmov $0x7fffffff,%r15d\nmovl $0x0,-0x8(%rsp)\njmp 146c \nnopl (%rax)\ncmp %r9d,%eax\nmov %r9d,%r11d\ncmovle %eax,%r11d\ncmp %eax,%r10d\ncmovge %r10d,%eax\nsub %r11d,%eax\ncmp %r15d,%eax\njge 1441 \ntest %eax,%eax\nje 14cb \nmov %ebx,-0x4(%rsp)\nmov %eax,%r15d\nmov %r12d,-0xc(%rsp)\nmov %ebp,-0x8(%rsp)\ncmp %r9d,%r11d\nje 14a0 \ncmp %r11d,%r10d\nje 14a8 \nadd $0x1,%ebx\ncmp %ebp,%ecx\nsetg %r9b\ncmp %r8d,%r12d\nsetl %al\ntest %al,%r9b\nje 14b0 \ncmp -0x10(%rsp),%ebx\njge 14b0 \nmovslq %ebp,%rax\nmov (%rdi,%rax,4),%r9d\nmovslq %r12d,%rax\nlea (%rsi,%rax,4),%r14\nmovslq %ebx,%rax\nmov (%r14),%r10d\nlea (%rdx,%rax,4),%r13\nmov 0x0(%r13),%eax\ncmp %r9d,%r10d\njg 1410 \ncmp %eax,%r10d\nmov %eax,%r11d\ncmovle %r10d,%r11d\ncmp %r9d,%r10d\njge 141a \ncmp %r9d,%eax\ncmovl %r9d,%eax\njmp 1421 \nxchg %ax,%ax\nadd $0x1,%ebp\njmp 144e \nnopl (%rax)\nadd $0x1,%r12d\njmp 144e \nxchg %ax,%ax\nmovslq -0x8(%rsp),%rax\nmov (%rdi,%rax,4),%r9d\nmovslq -0xc(%rsp),%rax\nlea (%rsi,%rax,4),%r14\nmovslq -0x4(%rsp),%rax\nlea (%rdx,%rax,4),%r13\nmov 0x38(%rsp),%rax\nmov 0x38(%rsp),%rcx\nmov %r9d,(%rax)\nmov (%r14),%eax\nmov %eax,0x4(%rcx)\nmov 0x0(%r13),%eax\nmov %eax,0x8(%rcx)\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nmov %rdx,%r13\nmov %rsi,%r14\njmp 14cb \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\ntest r9d, r9d\npush r14\nmov r14, rdx\npush r13\nmov r13, rsi\nsetnle sil\ntest r8d, r8d\npush r12\npush rbp\npush rbx\nmov ebx, ecx\nmov rax, [rsp+30h+arg_0]\nmov edx, [rdi]\nmov [rsp+30h+var_40], ecx\nsetnle cl\ntest sil, cl\njz loc_14F7\ntest ebx, ebx\njle loc_14F7\nmov r12, rdi\nmov [rsp+30h+var_34], 0\nxor edi, edi\nxor r11d, r11d\nmov [rsp+30h+var_38], 0\nxor r10d, r10d\nmov r15d, 7FFFFFFFh\nmov [rsp+30h+var_3C], 0\njmp short loc_145E\nloc_1410:\ncmp edx, eax\nmov esi, eax\ncmovle esi, edx\nloc_1417:\ncmp ecx, eax\ncmovge eax, ecx\nloc_141C:\nsub eax, esi\ncmp r15d, eax\njle short loc_143C\ntest eax, eax\njz loc_14F0\nmov [rsp+30h+var_34], edi\nmov r15d, eax\nmov [rsp+30h+var_38], r11d\nmov [rsp+30h+var_3C], r10d\nloc_143C:\ncmp edx, esi\njz short loc_1490\ncmp ecx, esi\njz short loc_14A0\nadd edi, 1\nloc_1447:\ncmp [rsp+30h+var_40], r10d\nsetnle dl\ncmp r11d, r8d\nsetl al\ntest dl, al\njz short loc_14B0\ncmp edi, r9d\njge short loc_14B0\nloc_145E:\nmovsxd rax, r10d\nmov edx, [r12+rax*4]\nmovsxd rax, r11d\nlea rbp, [r13+rax*4+0]\nmovsxd rax, edi\nmov ecx, [rbp+0]\nlea rbx, [r14+rax*4]\nmov eax, [rbx]\ncmp edx, ecx\njl short loc_1410\ncmp ecx, eax\nmov esi, eax\ncmovle esi, ecx\ncmp edx, ecx\njle short loc_1417\ncmp edx, eax\ncmovge eax, edx\njmp short loc_141C\nloc_1490:\nadd r10d, 1\njmp short loc_1447\nloc_14A0:\nadd r11d, 1\njmp short loc_1447\nloc_14B0:\nmovsxd rcx, [rsp+30h+var_38]\nmovsxd rdx, [rsp+30h+var_3C]\nmov rax, [rsp+30h+arg_0]\nlea rbp, [r13+rcx*4+0]\nmovsxd rcx, [rsp+30h+var_34]\nmov edx, [r12+rdx*4]\nlea rbx, [r14+rcx*4]\nloc_14D1:\nmov [rax], edx\nmov edx, [rbp+0]\nmov [rax+4], edx\nmov edx, [rbx]\nmov [rax+8], edx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14F0:\nmov rax, [rsp+30h+arg_0]\njmp short loc_14D1\nloc_14F7:\nmov rbx, r14\nmov rbp, r13\njmp short loc_14D1", + "ida_pseudo": "_DWORD *__fastcall func0(int *a1, int *a2, int *a3, int a4, int a5, int a6, _DWORD *a7)\n{\n _DWORD *result; // rax\n int v10; // edx\n int v12; // edi\n int v13; // r11d\n int v14; // r10d\n int v15; // r15d\n int v16; // esi\n int v17; // eax\n int v18; // eax\n int *v19; // rbp\n int v20; // ecx\n int *v21; // rbx\n int v23; // [rsp+4h] [rbp-3Ch]\n int v24; // [rsp+8h] [rbp-38h]\n int v25; // [rsp+Ch] [rbp-34h]\n\n result = a7;\n v10 = *a1;\n if ( a5 <= 0 || a6 <= 0 || a4 <= 0 )\n {\n v21 = a3;\n v19 = a2;\n goto LABEL_26;\n }\n v25 = 0;\n v12 = 0;\n v13 = 0;\n v24 = 0;\n v14 = 0;\n v15 = 0x7FFFFFFF;\n v23 = 0;\n while ( 1 )\n {\n v10 = a1[v14];\n v19 = &a2[v13];\n v20 = *v19;\n v21 = &a3[v12];\n v17 = *v21;\n if ( v10 < *v19 )\n {\n v16 = *v21;\n if ( v10 <= v17 )\n v16 = a1[v14];\n }\n else\n {\n v16 = *v21;\n if ( v20 <= v17 )\n v16 = *v19;\n if ( v10 > v20 )\n {\n if ( v10 >= v17 )\n v17 = a1[v14];\n goto LABEL_8;\n }\n }\n if ( v20 >= v17 )\n v17 = *v19;\nLABEL_8:\n v18 = v17 - v16;\n if ( v15 > v18 )\n break;\nLABEL_11:\n if ( v10 == v16 )\n {\n ++v14;\n }\n else if ( v20 == v16 )\n {\n ++v13;\n }\n else\n {\n ++v12;\n }\n if ( v13 >= a5 || a4 <= v14 || v12 >= a6 )\n {\n result = a7;\n v19 = &a2[v24];\n v10 = a1[v23];\n v21 = &a3[v25];\n goto LABEL_26;\n }\n }\n if ( v18 )\n {\n v25 = v12;\n v15 = v18;\n v24 = v13;\n v23 = v14;\n goto LABEL_11;\n }\n result = a7;\nLABEL_26:\n *result = v10;\n result[1] = *v19;\n result[2] = *v21;\n return result;\n}", + "ida_strip_asm": "sub_13A0:\nendbr64\npush r15\ntest r9d, r9d\npush r14\nmov r14, rdx\npush r13\nmov r13, rsi\nsetnle sil\ntest r8d, r8d\npush r12\npush rbp\npush rbx\nmov ebx, ecx\nmov rax, [rsp+30h+arg_0]\nmov edx, [rdi]\nmov [rsp+30h+var_40], ecx\nsetnle cl\ntest sil, cl\njz loc_14F7\ntest ebx, ebx\njle loc_14F7\nmov r12, rdi\nmov [rsp+30h+var_34], 0\nxor edi, edi\nxor r11d, r11d\nmov [rsp+30h+var_38], 0\nxor r10d, r10d\nmov r15d, 7FFFFFFFh\nmov [rsp+30h+var_3C], 0\njmp short loc_145E\nloc_1410:\ncmp edx, eax\nmov esi, eax\ncmovle esi, edx\nloc_1417:\ncmp ecx, eax\ncmovge eax, ecx\nloc_141C:\nsub eax, esi\ncmp r15d, eax\njle short loc_143C\ntest eax, eax\njz loc_14F0\nmov [rsp+30h+var_34], edi\nmov r15d, eax\nmov [rsp+30h+var_38], r11d\nmov [rsp+30h+var_3C], r10d\nloc_143C:\ncmp edx, esi\njz short loc_1490\ncmp ecx, esi\njz short loc_14A0\nadd edi, 1\nloc_1447:\ncmp [rsp+30h+var_40], r10d\nsetnle dl\ncmp r11d, r8d\nsetl al\ntest dl, al\njz short loc_14B0\ncmp edi, r9d\njge short loc_14B0\nloc_145E:\nmovsxd rax, r10d\nmov edx, [r12+rax*4]\nmovsxd rax, r11d\nlea rbp, [r13+rax*4+0]\nmovsxd rax, edi\nmov ecx, [rbp+0]\nlea rbx, [r14+rax*4]\nmov eax, [rbx]\ncmp edx, ecx\njl short loc_1410\ncmp ecx, eax\nmov esi, eax\ncmovle esi, ecx\ncmp edx, ecx\njle short loc_1417\ncmp edx, eax\ncmovge eax, edx\njmp short loc_141C\nloc_1490:\nadd r10d, 1\njmp short loc_1447\nloc_14A0:\nadd r11d, 1\njmp short loc_1447\nloc_14B0:\nmovsxd rcx, [rsp+30h+var_38]\nmovsxd rdx, [rsp+30h+var_3C]\nmov rax, [rsp+30h+arg_0]\nlea rbp, [r13+rcx*4+0]\nmovsxd rcx, [rsp+30h+var_34]\nmov edx, [r12+rdx*4]\nlea rbx, [r14+rcx*4]\nloc_14D1:\nmov [rax], edx\nmov edx, [rbp+0]\nmov [rax+4], edx\nmov edx, [rbx]\nmov [rax+8], edx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_14F0:\nmov rax, [rsp+30h+arg_0]\njmp short loc_14D1\nloc_14F7:\nmov rbx, r14\nmov rbp, r13\njmp short loc_14D1", + "ida_strip_pseudo": "_DWORD *__fastcall sub_13A0(int *a1, int *a2, int *a3, int a4, int a5, int a6, _DWORD *a7)\n{\n _DWORD *result; // rax\n int v10; // edx\n int v12; // edi\n int v13; // r11d\n int v14; // r10d\n int v15; // r15d\n int v16; // esi\n int v17; // eax\n int v18; // eax\n int *v19; // rbp\n int v20; // ecx\n int *v21; // rbx\n int v23; // [rsp+4h] [rbp-3Ch]\n int v24; // [rsp+8h] [rbp-38h]\n int v25; // [rsp+Ch] [rbp-34h]\n\n result = a7;\n v10 = *a1;\n if ( a5 <= 0 || a6 <= 0 || a4 <= 0 )\n {\n v21 = a3;\n v19 = a2;\n goto LABEL_26;\n }\n v25 = 0;\n v12 = 0;\n v13 = 0;\n v24 = 0;\n v14 = 0;\n v15 = 0x7FFFFFFF;\n v23 = 0;\n while ( 1 )\n {\n v10 = a1[v14];\n v19 = &a2[v13];\n v20 = *v19;\n v21 = &a3[v12];\n v17 = *v21;\n if ( v10 < *v19 )\n {\n v16 = *v21;\n if ( v10 <= v17 )\n v16 = a1[v14];\n }\n else\n {\n v16 = *v21;\n if ( v20 <= v17 )\n v16 = *v19;\n if ( v10 > v20 )\n {\n if ( v10 >= v17 )\n v17 = a1[v14];\n goto LABEL_8;\n }\n }\n if ( v20 >= v17 )\n v17 = *v19;\nLABEL_8:\n v18 = v17 - v16;\n if ( v15 > v18 )\n break;\nLABEL_11:\n if ( v10 == v16 )\n {\n ++v14;\n }\n else if ( v20 == v16 )\n {\n ++v13;\n }\n else\n {\n ++v12;\n }\n if ( v13 >= a5 || a4 <= v14 || v12 >= a6 )\n {\n result = a7;\n v19 = &a2[v24];\n v10 = a1[v23];\n v21 = &a3[v25];\n goto LABEL_26;\n }\n }\n if ( v18 )\n {\n v25 = v12;\n v15 = v18;\n v24 = v13;\n v23 = v14;\n goto LABEL_11;\n }\n result = a7;\nLABEL_26:\n *result = v10;\n result[1] = *v19;\n result[2] = *v21;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_13A0(int *a1, int *a2, int *a3, int a4, int a5, int a6,\n uint32_t *a7) {\n uint32_t *result;\n int v10;\n int v12;\n int v13;\n int v14;\n int v15;\n int v16;\n int v17;\n int v18;\n int *v19;\n int v20;\n int *v21;\n int v23;\n int v24;\n int v25;\n result = a7;\n v10 = *a1;\n if (a5 <= 0 || a6 <= 0 || a4 <= 0) {\n v21 = a3;\n v19 = a2;\n goto LABEL_26;\n }\n v25 = 0;\n v12 = 0;\n v13 = 0;\n v24 = 0;\n v14 = 0;\n v15 = 2147483647;\n v23 = 0;\n while (1) {\n v10 = a1[v14];\n v19 = &a2[v13];\n v20 = *v19;\n v21 = &a3[v12];\n v17 = *v21;\n if (v10 < *v19) {\n v16 = *v21;\n if (v10 <= v17) v16 = a1[v14];\n } else {\n v16 = *v21;\n if (v20 <= v17) v16 = *v19;\n if (v10 > v20) {\n if (v10 >= v17) v17 = a1[v14];\n goto LABEL_8;\n }\n }\n if (v20 >= v17) v17 = *v19;\n LABEL_8:\n v18 = v17 - v16;\n if (v15 > v18) break;\n LABEL_11:\n if (v10 == v16) {\n ++v14;\n } else if (v20 == v16) {\n ++v13;\n } else {\n ++v12;\n }\n if (v13 >= a5 || a4 <= v14 || v12 >= a6) {\n result = a7;\n v19 = &a2[v24];\n v10 = a1[v23];\n v21 = &a3[v25];\n goto LABEL_26;\n }\n }\n if (v18) {\n v25 = v12;\n v15 = v18;\n v24 = v13;\n v23 = v14;\n goto LABEL_11;\n }\n result = a7;\nLABEL_26:\n *result = v10;\n result[1] = *v19;\n result[2] = *v21;\n return result;\n}", + "ida_pseudo_norm": "uint32_t *func0(int *a1, int *a2, int *a3, int a4, int a5, int a6,\n uint32_t *a7) {\n uint32_t *result;\n int v10;\n int v12;\n int v13;\n int v14;\n int v15;\n int v16;\n int v17;\n int v18;\n int *v19;\n int v20;\n int *v21;\n int v23;\n int v24;\n int v25;\n result = a7;\n v10 = *a1;\n if (a5 <= 0 || a6 <= 0 || a4 <= 0) {\n v21 = a3;\n v19 = a2;\n goto LABEL_26;\n }\n v25 = 0;\n v12 = 0;\n v13 = 0;\n v24 = 0;\n v14 = 0;\n v15 = 2147483647;\n v23 = 0;\n while (1) {\n v10 = a1[v14];\n v19 = &a2[v13];\n v20 = *v19;\n v21 = &a3[v12];\n v17 = *v21;\n if (v10 < *v19) {\n v16 = *v21;\n if (v10 <= v17) v16 = a1[v14];\n } else {\n v16 = *v21;\n if (v20 <= v17) v16 = *v19;\n if (v10 > v20) {\n if (v10 >= v17) v17 = a1[v14];\n goto LABEL_8;\n }\n }\n if (v20 >= v17) v17 = *v19;\n LABEL_8:\n v18 = v17 - v16;\n if (v15 > v18) break;\n LABEL_11:\n if (v10 == v16) {\n ++v14;\n } else if (v20 == v16) {\n ++v13;\n } else {\n ++v12;\n }\n if (v13 >= a5 || a4 <= v14 || v12 >= a6) {\n result = a7;\n v19 = &a2[v24];\n v10 = a1[v23];\n v21 = &a3[v25];\n goto LABEL_26;\n }\n }\n if (v18) {\n v25 = v12;\n v15 = v18;\n v24 = v13;\n v23 = v14;\n goto LABEL_11;\n }\n result = a7;\nLABEL_26:\n *result = v10;\n result[1] = *v19;\n result[2] = *v21;\n return result;\n}" + }, + { + "index": 939, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char *make;\n\n int model;\n\n char *color;\n\n} Phone;\n\n\n\nint comparator(const void *v1, const void *v2) {\n\n Phone *p1 = (Phone *)v1;\n\n Phone *p2 = (Phone *)v2;\n\n return strcmp(p1->color, p2->color);\n\n}\n\n\n\n", + "func": "void func0(Phone *models, int len) {\n qsort(models, len, sizeof(Phone), comparator);\n}", + "test": "int main() {\n\n Phone phones1[] = {{\"Nokia\", 216, \"Black\"}, {\"Mi Max\", 2, \"Gold\"}, {\"Samsung\", 7, \"Blue\"}};\n\n Phone sorted1[] = {{\"Nokia\", 216, \"Black\"}, {\"Samsung\", 7, \"Blue\"}, {\"Mi Max\", 2, \"Gold\"}};\n\n int len1 = sizeof(phones1) / sizeof(phones1[0]);\n\n\n\n func0(phones1, len1);\n\n for (int i = 0; i < len1; i++) {\n\n assert(strcmp(phones1[i].make, sorted1[i].make) == 0);\n\n assert(phones1[i].model == sorted1[i].model);\n\n assert(strcmp(phones1[i].color, sorted1[i].color) == 0);\n\n }\n\n\n\n Phone phones2[] = {{\"Vivo\", 20, \"Blue\"}, {\"oppo\", 17, \"Gold\"}, {\"Apple\", 11, \"red\"}};\n\n Phone sorted2[] = {{\"Vivo\", 20, \"Blue\"}, {\"oppo\", 17, \"Gold\"}, {\"Apple\", 11, \"red\"}};\n\n int len2 = sizeof(phones2) / sizeof(phones2[0]);\n\n\n\n func0(phones2, len2);\n\n for (int i = 0; i < len2; i++) {\n\n assert(strcmp(phones2[i].make, sorted2[i].make) == 0);\n\n assert(phones2[i].model == sorted2[i].model);\n\n assert(strcmp(phones2[i].color, sorted2[i].color) == 0);\n\n }\n\n\n\n Phone phones3[] = {{\"micromax\", 40, \"grey\"}, {\"poco\", 60, \"blue\"}};\n\n Phone sorted3[] = {{\"poco\", 60, \"blue\"}, {\"micromax\", 40, \"grey\"}};\n\n int len3 = sizeof(phones3) / sizeof(phones3[0]);\n\n\n\n func0(phones3, len3);\n\n for (int i = 0; i < len3; i++) {\n\n assert(strcmp(phones3[i].make, sorted3[i].make) == 0);\n\n assert(phones3[i].model == sorted3[i].model);\n\n assert(strcmp(phones3[i].color, sorted3[i].color) == 0);\n\n }\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %rdi,-0x8(%rbp)\nmov %esi,-0xc(%rbp)\nmov -0xc(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x8(%rbp),%rax\nlea -0x65(%rip),%rcx\nmov $0x18,%edx\nmov %rax,%rdi\ncallq 1080 \nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+base], rdi\nmov [rbp+var_C], esi\nmov eax, [rbp+var_C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, comparator\nmov rcx, rdx; compar\nmov edx, 18h; size\nmov rdi, rax; base\ncall _qsort\nnop\nleave\nretn", + "ida_pseudo": "void __fastcall func0(void *a1, int a2)\n{\n qsort(a1, a2, 0x18uLL, comparator);\n}", + "ida_strip_asm": "sub_11EA:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+base], rdi\nmov [rbp+var_C], esi\nmov eax, [rbp+var_C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 18h; size\nmov rdi, rax; base\ncall _qsort\nnop\nleave\nretn", + "ida_strip_pseudo": "void __fastcall sub_11EA(void *a1, int a2)\n{\n qsort(a1, a2, 0x18uLL, compar);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_11EA(void *a1, int a2) { qsort(a1, a2, 24uLL, compar); }", + "ida_pseudo_norm": "void func0(void *a1, int a2) { qsort(a1, a2, 24uLL, comparator); }" + }, + { + "index": 939, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char *make;\n\n int model;\n\n char *color;\n\n} Phone;\n\n\n\nint comparator(const void *v1, const void *v2) {\n\n Phone *p1 = (Phone *)v1;\n\n Phone *p2 = (Phone *)v2;\n\n return strcmp(p1->color, p2->color);\n\n}\n\n\n\n", + "func": "void func0(Phone *models, int len) {\n qsort(models, len, sizeof(Phone), comparator);\n}", + "test": "int main() {\n\n Phone phones1[] = {{\"Nokia\", 216, \"Black\"}, {\"Mi Max\", 2, \"Gold\"}, {\"Samsung\", 7, \"Blue\"}};\n\n Phone sorted1[] = {{\"Nokia\", 216, \"Black\"}, {\"Samsung\", 7, \"Blue\"}, {\"Mi Max\", 2, \"Gold\"}};\n\n int len1 = sizeof(phones1) / sizeof(phones1[0]);\n\n\n\n func0(phones1, len1);\n\n for (int i = 0; i < len1; i++) {\n\n assert(strcmp(phones1[i].make, sorted1[i].make) == 0);\n\n assert(phones1[i].model == sorted1[i].model);\n\n assert(strcmp(phones1[i].color, sorted1[i].color) == 0);\n\n }\n\n\n\n Phone phones2[] = {{\"Vivo\", 20, \"Blue\"}, {\"oppo\", 17, \"Gold\"}, {\"Apple\", 11, \"red\"}};\n\n Phone sorted2[] = {{\"Vivo\", 20, \"Blue\"}, {\"oppo\", 17, \"Gold\"}, {\"Apple\", 11, \"red\"}};\n\n int len2 = sizeof(phones2) / sizeof(phones2[0]);\n\n\n\n func0(phones2, len2);\n\n for (int i = 0; i < len2; i++) {\n\n assert(strcmp(phones2[i].make, sorted2[i].make) == 0);\n\n assert(phones2[i].model == sorted2[i].model);\n\n assert(strcmp(phones2[i].color, sorted2[i].color) == 0);\n\n }\n\n\n\n Phone phones3[] = {{\"micromax\", 40, \"grey\"}, {\"poco\", 60, \"blue\"}};\n\n Phone sorted3[] = {{\"poco\", 60, \"blue\"}, {\"micromax\", 40, \"grey\"}};\n\n int len3 = sizeof(phones3) / sizeof(phones3[0]);\n\n\n\n func0(phones3, len3);\n\n for (int i = 0; i < len3; i++) {\n\n assert(strcmp(phones3[i].make, sorted3[i].make) == 0);\n\n assert(phones3[i].model == sorted3[i].model);\n\n assert(strcmp(phones3[i].color, sorted3[i].color) == 0);\n\n }\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x8,%rsp\nmovslq %esi,%rsi\nlea -0x2c(%rip),%rcx\nmov $0x18,%edx\ncallq 1080 \nadd $0x8,%rsp\nretq\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\nmovsxd rsi, esi; nmemb\nlea rcx, comparator; compar\nmov edx, 18h; size\ncall _qsort\nadd rsp, 8\nretn", + "ida_pseudo": "void __fastcall func0(void *a1, int a2)\n{\n qsort(a1, a2, 0x18uLL, comparator);\n}", + "ida_strip_asm": "sub_11C3:\nendbr64\nsub rsp, 8\nmovsxd rsi, esi; nmemb\nlea rcx, compar; compar\nmov edx, 18h; size\ncall _qsort\nadd rsp, 8\nretn", + "ida_strip_pseudo": "void __fastcall sub_11C3(void *a1, int a2)\n{\n qsort(a1, a2, 0x18uLL, compar);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_11C3(void *a1, int a2) { qsort(a1, a2, 24uLL, compar); }", + "ida_pseudo_norm": "void func0(void *a1, int a2) { qsort(a1, a2, 24uLL, comparator); }" + }, + { + "index": 940, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nvoid shift_down(int arr[], int start, int end) {\n\n int root = start;\n\n while (root * 2 + 1 <= end) {\n\n int child = root * 2 + 1;\n\n if (child + 1 <= end && arr[child] < arr[child + 1]) {\n\n child += 1;\n\n }\n\n if (child <= end && arr[root] < arr[child]) {\n\n int temp = arr[root];\n\n arr[root] = arr[child];\n\n arr[child] = temp;\n\n root = child;\n\n } else {\n\n return;\n\n }\n\n }\n\n}\n\n\n\nvoid heapify(int arr[], int length) {\n\n int start = (length - 2) / 2;\n\n while (start >= 0) {\n\n shift_down(arr, start, length - 1);\n\n start -= 1;\n\n }\n\n}\n\n\n\n", + "func": "void func0(int arr[], int length) {\n heapify(arr, length);\n int end = length - 1;\n while (end > 0) {\n int temp = arr[end];\n arr[end] = arr[0];\n arr[0] = temp;\n end -= 1;\n shift_down(arr, 0, end);\n }\n}", + "test": "int main() {\n\n int arr1[] = {12, 2, 4, 5, 2, 3};\n\n func0(arr1, 6);\n\n int sorted1[] = {2, 2, 3, 4, 5, 12};\n\n for (int i = 0; i < 6; i++) {\n\n assert(arr1[i] == sorted1[i]);\n\n }\n\n\n\n int arr2[] = {32, 14, 5, 6, 7, 19};\n\n func0(arr2, 6);\n\n int sorted2[] = {5, 6, 7, 14, 19, 32};\n\n for (int i = 0; i < 6; i++) {\n\n assert(arr2[i] == sorted2[i]);\n\n }\n\n\n\n int arr3[] = {21, 15, 29, 78, 65};\n\n func0(arr3, 5);\n\n int sorted3[] = {15, 21, 29, 65, 78};\n\n for (int i = 0; i < 5; i++) {\n\n assert(arr3[i] == sorted3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov -0x1c(%rbp),%edx\nmov -0x18(%rbp),%rax\nmov %edx,%esi\nmov %rax,%rdi\ncallq 1286 \nmov -0x1c(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0x8(%rbp)\njmp 1357 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x4(%rbp)\nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rax,%rdx\nmov -0x18(%rbp),%rax\nmov (%rax),%eax\nmov %eax,(%rdx)\nmov -0x18(%rbp),%rax\nmov -0x4(%rbp),%edx\nmov %edx,(%rax)\nsubl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%edx\nmov -0x18(%rbp),%rax\nmov $0x0,%esi\nmov %rax,%rdi\ncallq 1169 \ncmpl $0x0,-0x8(%rbp)\njg 1301 \nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov edx, [rbp+var_1C]\nmov rax, [rbp+var_18]\nmov esi, edx\nmov rdi, rax\ncall heapify\nmov eax, [rbp+var_1C]\nsub eax, 1\nmov [rbp+var_8], eax\njmp short loc_1357\nloc_1301:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov rax, [rbp+var_18]\nmov eax, [rax]\nmov [rdx], eax\nmov rax, [rbp+var_18]\nmov edx, [rbp+var_4]\nmov [rax], edx\nsub [rbp+var_8], 1\nmov edx, [rbp+var_8]\nmov rax, [rbp+var_18]\nmov esi, 0\nmov rdi, rax\ncall shift_down\nloc_1357:\ncmp [rbp+var_8], 0\njg short loc_1301\nnop\nnop\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, unsigned int a2)\n{\n __int64 result; // rax\n int i; // [rsp+18h] [rbp-8h]\n int v4; // [rsp+1Ch] [rbp-4h]\n\n heapify(a1, a2);\n result = a2 - 1;\n for ( i = a2 - 1; i > 0; result = shift_down(a1, 0LL, (unsigned int)i) )\n {\n v4 = a1[i];\n a1[i] = *a1;\n *a1 = v4;\n --i;\n }\n return result;\n}", + "ida_strip_asm": "sub_12D2:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov edx, [rbp+var_1C]\nmov rax, [rbp+var_18]\nmov esi, edx\nmov rdi, rax\ncall sub_1286\nmov eax, [rbp+var_1C]\nsub eax, 1\nmov [rbp+var_8], eax\njmp short loc_1357\nloc_1301:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rdx, rax\nmov rax, [rbp+var_18]\nmov eax, [rax]\nmov [rdx], eax\nmov rax, [rbp+var_18]\nmov edx, [rbp+var_4]\nmov [rax], edx\nsub [rbp+var_8], 1\nmov edx, [rbp+var_8]\nmov rax, [rbp+var_18]\nmov esi, 0\nmov rdi, rax\ncall sub_1169\nloc_1357:\ncmp [rbp+var_8], 0\njg short loc_1301\nnop\nnop\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12D2(_DWORD *a1, unsigned int a2)\n{\n __int64 result; // rax\n int i; // [rsp+18h] [rbp-8h]\n int v4; // [rsp+1Ch] [rbp-4h]\n\n sub_1286(a1, a2);\n result = a2 - 1;\n for ( i = a2 - 1; i > 0; result = sub_1169(a1, 0LL, (unsigned int)i) )\n {\n v4 = a1[i];\n a1[i] = *a1;\n *a1 = v4;\n --i;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12D2(uint32_t *a1, unsigned int a2) {\n long long result;\n int i;\n int v4;\n sub_1286(a1, a2);\n result = a2 - 1;\n for (i = a2 - 1; i > 0; result = sub_1169(a1, 0LL, (unsigned int)i)) {\n v4 = a1[i];\n a1[i] = *a1;\n *a1 = v4;\n --i;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, unsigned int a2) {\n long long result;\n int i;\n int v4;\n heapify(a1, a2);\n result = a2 - 1;\n for (i = a2 - 1; i > 0; result = shift_down(a1, 0LL, (unsigned int)i)) {\n v4 = a1[i];\n a1[i] = *a1;\n *a1 = v4;\n --i;\n }\n return result;\n}" + }, + { + "index": 940, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nvoid shift_down(int arr[], int start, int end) {\n\n int root = start;\n\n while (root * 2 + 1 <= end) {\n\n int child = root * 2 + 1;\n\n if (child + 1 <= end && arr[child] < arr[child + 1]) {\n\n child += 1;\n\n }\n\n if (child <= end && arr[root] < arr[child]) {\n\n int temp = arr[root];\n\n arr[root] = arr[child];\n\n arr[child] = temp;\n\n root = child;\n\n } else {\n\n return;\n\n }\n\n }\n\n}\n\n\n\nvoid heapify(int arr[], int length) {\n\n int start = (length - 2) / 2;\n\n while (start >= 0) {\n\n shift_down(arr, start, length - 1);\n\n start -= 1;\n\n }\n\n}\n\n\n\n", + "func": "void func0(int arr[], int length) {\n heapify(arr, length);\n int end = length - 1;\n while (end > 0) {\n int temp = arr[end];\n arr[end] = arr[0];\n arr[0] = temp;\n end -= 1;\n shift_down(arr, 0, end);\n }\n}", + "test": "int main() {\n\n int arr1[] = {12, 2, 4, 5, 2, 3};\n\n func0(arr1, 6);\n\n int sorted1[] = {2, 2, 3, 4, 5, 12};\n\n for (int i = 0; i < 6; i++) {\n\n assert(arr1[i] == sorted1[i]);\n\n }\n\n\n\n int arr2[] = {32, 14, 5, 6, 7, 19};\n\n func0(arr2, 6);\n\n int sorted2[] = {5, 6, 7, 14, 19, 32};\n\n for (int i = 0; i < 6; i++) {\n\n assert(arr2[i] == sorted2[i]);\n\n }\n\n\n\n int arr3[] = {21, 15, 29, 78, 65};\n\n func0(arr3, 5);\n\n int sorted3[] = {15, 21, 29, 65, 78};\n\n for (int i = 0; i < 5; i++) {\n\n assert(arr3[i] == sorted3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nmov %rdi,%rbp\nmov %esi,%ebx\ncallq 11bc \nsub $0x1,%ebx\ntest %ebx,%ebx\njle 1230 \nmovslq %ebx,%rbx\nmov 0x0(%rbp,%rbx,4),%eax\nmov 0x0(%rbp),%edx\nmov %edx,0x0(%rbp,%rbx,4)\nmov %eax,0x0(%rbp)\nlea -0x1(%rbx),%edx\nmov $0x0,%esi\nmov %rbp,%rdi\ncallq 1169 \nsub $0x1,%rbx\ntest %ebx,%ebx\njg 120a \npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nmov rbp, rdi\nmov ebx, esi\ncall heapify\nsub ebx, 1\ntest ebx, ebx\njle short loc_1236\nmovsxd rbx, ebx\nloc_1210:\nmov eax, [rbp+rbx*4+0]\nmov edx, [rbp+0]\nmov [rbp+rbx*4+0], edx\nmov [rbp+0], eax\nlea edx, [rbx-1]\nmov esi, 0\nmov rdi, rbp\ncall shift_down\nsub rbx, 1\ntest ebx, ebx\njg short loc_1210\nloc_1236:\npop rbx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n __int64 result; // rax\n __int64 v3; // rbx\n int v4; // eax\n\n result = heapify();\n LODWORD(v3) = a2 - 1;\n if ( a2 - 1 > 0 )\n {\n v3 = (int)v3;\n do\n {\n v4 = a1[v3];\n a1[v3] = *a1;\n *a1 = v4;\n result = shift_down(a1, 0LL, (unsigned int)--v3);\n }\n while ( (int)v3 > 0 );\n }\n return result;\n}", + "ida_strip_asm": "sub_11F6:\nendbr64\npush rbp\npush rbx\nmov rbp, rdi\nmov ebx, esi\ncall sub_11BF\nsub ebx, 1\ntest ebx, ebx\njle short loc_1236\nmovsxd rbx, ebx\nloc_1210:\nmov eax, [rbp+rbx*4+0]\nmov edx, [rbp+0]\nmov [rbp+rbx*4+0], edx\nmov [rbp+0], eax\nlea edx, [rbx-1]\nmov esi, 0\nmov rdi, rbp\ncall sub_1169\nsub rbx, 1\ntest ebx, ebx\njg short loc_1210\nloc_1236:\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11F6(_DWORD *a1, int a2)\n{\n __int64 result; // rax\n __int64 v3; // rbx\n int v4; // eax\n\n result = sub_11BF();\n LODWORD(v3) = a2 - 1;\n if ( a2 - 1 > 0 )\n {\n v3 = (int)v3;\n do\n {\n v4 = a1[v3];\n a1[v3] = *a1;\n *a1 = v4;\n result = sub_1169(a1, 0LL, (unsigned int)--v3);\n }\n while ( (int)v3 > 0 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11F6(uint32_t *a1, int a2) {\n long long result;\n long long v3;\n int v4;\n result = sub_11BF();\n LODWORD(v3) = a2 - 1;\n if (a2 - 1 > 0) {\n v3 = (int)v3;\n do {\n v4 = a1[v3];\n a1[v3] = *a1;\n *a1 = v4;\n result = sub_1169(a1, 0LL, (unsigned int)--v3);\n } while ((int)v3 > 0);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n long long result;\n long long v3;\n int v4;\n result = heapify();\n LODWORD(v3) = a2 - 1;\n if (a2 - 1 > 0) {\n v3 = (int)v3;\n do {\n v4 = a1[v3];\n a1[v3] = *a1;\n *a1 = v4;\n result = shift_down(a1, 0LL, (unsigned int)--v3);\n } while ((int)v3 > 0);\n }\n return result;\n}" + }, + { + "index": 940, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nvoid shift_down(int arr[], int start, int end) {\n\n int root = start;\n\n while (root * 2 + 1 <= end) {\n\n int child = root * 2 + 1;\n\n if (child + 1 <= end && arr[child] < arr[child + 1]) {\n\n child += 1;\n\n }\n\n if (child <= end && arr[root] < arr[child]) {\n\n int temp = arr[root];\n\n arr[root] = arr[child];\n\n arr[child] = temp;\n\n root = child;\n\n } else {\n\n return;\n\n }\n\n }\n\n}\n\n\n\nvoid heapify(int arr[], int length) {\n\n int start = (length - 2) / 2;\n\n while (start >= 0) {\n\n shift_down(arr, start, length - 1);\n\n start -= 1;\n\n }\n\n}\n\n\n\n", + "func": "void func0(int arr[], int length) {\n heapify(arr, length);\n int end = length - 1;\n while (end > 0) {\n int temp = arr[end];\n arr[end] = arr[0];\n arr[0] = temp;\n end -= 1;\n shift_down(arr, 0, end);\n }\n}", + "test": "int main() {\n\n int arr1[] = {12, 2, 4, 5, 2, 3};\n\n func0(arr1, 6);\n\n int sorted1[] = {2, 2, 3, 4, 5, 12};\n\n for (int i = 0; i < 6; i++) {\n\n assert(arr1[i] == sorted1[i]);\n\n }\n\n\n\n int arr2[] = {32, 14, 5, 6, 7, 19};\n\n func0(arr2, 6);\n\n int sorted2[] = {5, 6, 7, 14, 19, 32};\n\n for (int i = 0; i < 6; i++) {\n\n assert(arr2[i] == sorted2[i]);\n\n }\n\n\n\n int arr3[] = {21, 15, 29, 78, 65};\n\n func0(arr3, 5);\n\n int sorted3[] = {15, 21, 29, 65, 78};\n\n for (int i = 0; i < 5; i++) {\n\n assert(arr3[i] == sorted3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nlea -0x2(%rsi),%eax\nlea -0x1(%rsi),%edx\nmov %eax,%r10d\nshr $0x1f,%r10d\nadd %eax,%r10d\nsar %r10d\ntest %esi,%esi\njle 1482 \nnopl 0x0(%rax,%rax,1)\nmov %r10d,%esi\ncallq 13b0 \nsub $0x1,%r10d\ncmp $0xffffffff,%r10d\njne 1470 \nmovslq %edx,%r10\ntest %edx,%edx\njle 14b8 \nnopl 0x0(%rax)\nmov (%rdi,%r10,4),%eax\nmov (%rdi),%edx\nxor %esi,%esi\nmov %edx,(%rdi,%r10,4)\nlea -0x1(%r10),%edx\nmov %eax,(%rdi)\ncallq 13b0 \nsub $0x1,%r10\ntest %r10d,%r10d\njg 1490 \nretq\nnopl 0x0(%rax)\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\nlea eax, [rsi-2]\nmov r10, rdi\nlea edx, [rsi-1]\nmov r11d, eax\nshr r11d, 1Fh\nadd r11d, eax\nsar r11d, 1\ntest esi, esi\njle short loc_1421\nxchg ax, ax\nloc_1410:\nmov esi, r11d\nmov rdi, r10\ncall shift_down\nsub r11d, 1\njnb short loc_1410\nloc_1421:\nmovsxd r11, edx\ntest edx, edx\njle short locret_1460\nnop dword ptr [rax+rax+00000000h]\nloc_1430:\nmov eax, [r10+r11*4]\nmov edx, [r10]\nxor esi, esi\nmov rdi, r10\nmov [r10+r11*4], edx\nlea edx, [r11-1]\nsub r11, 1\nmov [r10], eax\ncall shift_down\ntest r11d, r11d\njg short loc_1430\nretn\nlocret_1460:\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n __int64 result; // rax\n _DWORD *v3; // r10\n __int64 v4; // rdx\n unsigned int v5; // r11d\n int v6; // r11d\n bool v7; // cf\n __int64 v8; // r11\n int v9; // eax\n\n result = (unsigned int)(a2 - 2);\n v3 = a1;\n v4 = (unsigned int)(a2 - 1);\n v5 = (a2 - 2) / 2;\n if ( a2 > 0 )\n {\n do\n {\n result = shift_down(v3, v5, v4);\n v7 = v6 == 0;\n v5 = v6 - 1;\n }\n while ( !v7 );\n }\n v8 = (int)v4;\n if ( (int)v4 > 0 )\n {\n do\n {\n v9 = v3[v8];\n v3[v8] = *v3;\n *v3 = v9;\n result = shift_down(v3, 0LL, (unsigned int)(v8 - 1));\n }\n while ( (int)v8 > 0 );\n }\n return result;\n}", + "ida_strip_asm": "sub_13F0:\nendbr64\nlea eax, [rsi-2]\nmov r10, rdi\nlea edx, [rsi-1]\nmov r11d, eax\nshr r11d, 1Fh\nadd r11d, eax\nsar r11d, 1\ntest esi, esi\njle short loc_1421\nxchg ax, ax\nloc_1410:\nmov esi, r11d\nmov rdi, r10\ncall sub_1350\nsub r11d, 1\njnb short loc_1410\nloc_1421:\nmovsxd r11, edx\ntest edx, edx\njle short locret_1460\nnop dword ptr [rax+rax+00000000h]\nloc_1430:\nmov eax, [r10+r11*4]\nmov edx, [r10]\nxor esi, esi\nmov rdi, r10\nmov [r10+r11*4], edx\nlea edx, [r11-1]\nsub r11, 1\nmov [r10], eax\ncall sub_1350\ntest r11d, r11d\njg short loc_1430\nretn\nlocret_1460:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_13F0(_DWORD *a1, int a2)\n{\n __int64 result; // rax\n _DWORD *v3; // r10\n __int64 v4; // rdx\n unsigned int v5; // r11d\n int v6; // r11d\n bool v7; // cf\n __int64 v8; // r11\n int v9; // eax\n\n result = (unsigned int)(a2 - 2);\n v3 = a1;\n v4 = (unsigned int)(a2 - 1);\n v5 = (a2 - 2) / 2;\n if ( a2 > 0 )\n {\n do\n {\n result = sub_1350(v3, v5, v4);\n v7 = v6 == 0;\n v5 = v6 - 1;\n }\n while ( !v7 );\n }\n v8 = (int)v4;\n if ( (int)v4 > 0 )\n {\n do\n {\n v9 = v3[v8];\n v3[v8] = *v3;\n *v3 = v9;\n result = sub_1350(v3, 0LL, (unsigned int)(v8 - 1));\n }\n while ( (int)v8 > 0 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_13F0(uint32_t *a1, int a2) {\n long long result;\n uint32_t *v3;\n long long v4;\n unsigned int v5;\n int v6;\n bool v7;\n long long v8;\n int v9;\n result = (unsigned int)(a2 - 2);\n v3 = a1;\n v4 = (unsigned int)(a2 - 1);\n v5 = (a2 - 2) / 2;\n if (a2 > 0) {\n do {\n result = sub_1350(v3, v5, v4);\n v7 = v6 == 0;\n v5 = v6 - 1;\n } while (!v7);\n }\n v8 = (int)v4;\n if ((int)v4 > 0) {\n do {\n v9 = v3[v8];\n v3[v8] = *v3;\n *v3 = v9;\n result = sub_1350(v3, 0LL, (unsigned int)(v8 - 1));\n } while ((int)v8 > 0);\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n long long result;\n uint32_t *v3;\n long long v4;\n unsigned int v5;\n int v6;\n bool v7;\n long long v8;\n int v9;\n result = (unsigned int)(a2 - 2);\n v3 = a1;\n v4 = (unsigned int)(a2 - 1);\n v5 = (a2 - 2) / 2;\n if (a2 > 0) {\n do {\n result = shift_down(v3, v5, v4);\n v7 = v6 == 0;\n v5 = v6 - 1;\n } while (!v7);\n }\n v8 = (int)v4;\n if ((int)v4 > 0) {\n do {\n v9 = v3[v8];\n v3[v8] = *v3;\n *v3 = v9;\n result = shift_down(v3, 0LL, (unsigned int)(v8 - 1));\n } while ((int)v8 > 0);\n }\n return result;\n}" + }, + { + "index": 940, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\nvoid shift_down(int arr[], int start, int end) {\n\n int root = start;\n\n while (root * 2 + 1 <= end) {\n\n int child = root * 2 + 1;\n\n if (child + 1 <= end && arr[child] < arr[child + 1]) {\n\n child += 1;\n\n }\n\n if (child <= end && arr[root] < arr[child]) {\n\n int temp = arr[root];\n\n arr[root] = arr[child];\n\n arr[child] = temp;\n\n root = child;\n\n } else {\n\n return;\n\n }\n\n }\n\n}\n\n\n\nvoid heapify(int arr[], int length) {\n\n int start = (length - 2) / 2;\n\n while (start >= 0) {\n\n shift_down(arr, start, length - 1);\n\n start -= 1;\n\n }\n\n}\n\n\n\n", + "func": "void func0(int arr[], int length) {\n heapify(arr, length);\n int end = length - 1;\n while (end > 0) {\n int temp = arr[end];\n arr[end] = arr[0];\n arr[0] = temp;\n end -= 1;\n shift_down(arr, 0, end);\n }\n}", + "test": "int main() {\n\n int arr1[] = {12, 2, 4, 5, 2, 3};\n\n func0(arr1, 6);\n\n int sorted1[] = {2, 2, 3, 4, 5, 12};\n\n for (int i = 0; i < 6; i++) {\n\n assert(arr1[i] == sorted1[i]);\n\n }\n\n\n\n int arr2[] = {32, 14, 5, 6, 7, 19};\n\n func0(arr2, 6);\n\n int sorted2[] = {5, 6, 7, 14, 19, 32};\n\n for (int i = 0; i < 6; i++) {\n\n assert(arr2[i] == sorted2[i]);\n\n }\n\n\n\n int arr3[] = {21, 15, 29, 78, 65};\n\n func0(arr3, 5);\n\n int sorted3[] = {15, 21, 29, 65, 78};\n\n for (int i = 0; i < 5; i++) {\n\n assert(arr3[i] == sorted3[i]);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nlea -0x2(%rsi),%edx\npush %rbp\nlea -0x1(%rsi),%r11d\npush %rbx\nmov %edx,%ebx\nshr $0x1f,%ebx\nadd %edx,%ebx\nmov %ebx,%ebp\nand $0xfffffffe,%ebx\nsar %ebp\ntest %esi,%esi\njle 152a \nmov %ebx,%r8d\nmovslq %ebp,%rcx\ncmp %r11d,%ebx\njl 14f8 \njmp 151f \nnopl (%rax)\nmovslq %eax,%r8\nlea (%rdi,%r8,4),%r8\nmov (%r8),%r9d\nlea (%rdi,%rcx,4),%r10\nmov (%r10),%ecx\ncmp %r9d,%ecx\njge 151f \nmov %r9d,(%r10)\nmov %ecx,(%r8)\nlea (%rax,%rax,1),%r8d\ncmp %r11d,%r8d\njge 151f \nmovslq %eax,%rcx\nlea 0x1(%r8),%eax\ncmp %r11d,%eax\njge 151a \nmovslq %eax,%r10\nshl $0x2,%r10\nlea (%rdi,%r10,1),%r8\nmov (%r8),%r9d\ncmp 0x4(%rdi,%r10,1),%r9d\njge 14da \nlea 0x2(%rcx,%rcx,1),%eax\ncmp %r11d,%eax\njle 14d0 \nsub $0x1,%ebp\nsub $0x2,%ebx\ncmp $0xffffffff,%ebp\njne 14c0 \ntest %r11d,%r11d\njle 15bd \nmovslq %r11d,%r11\nmov (%rdi),%ecx\nlea (%rdi,%r11,4),%rax\nmov (%rax),%r10d\nmov %ecx,(%rax)\nmov %r10d,(%rdi)\ncmp $0x2,%esi\nje 15bd \nmovslq %edx,%rdx\nnopl 0x0(%rax)\nxor %ecx,%ecx\nxor %esi,%esi\nmov %edx,%r11d\njmp 1584 \nnopl 0x0(%rax)\nmovslq %eax,%rsi\nlea (%rdi,%rsi,4),%rsi\nmov (%rsi),%r8d\nlea (%rdi,%rcx,4),%rcx\ncmp %r8d,%r10d\njge 15a9 \nmov %r8d,(%rcx)\nmov %r10d,(%rsi)\nlea (%rax,%rax,1),%esi\ncmp %r11d,%esi\njge 15a9 \nmovslq %eax,%rcx\nlea 0x1(%rsi),%eax\ncmp %edx,%eax\njge 15a4 \nmovslq %eax,%r9\nshl $0x2,%r9\nlea (%rdi,%r9,1),%rsi\nmov (%rsi),%r8d\ncmp 0x4(%rdi,%r9,1),%r8d\njge 156a \nlea 0x2(%rcx,%rcx,1),%eax\ncmp %r11d,%eax\njle 1560 \nmov (%rdi),%eax\nmov (%rdi,%rdx,4),%r10d\nmov %eax,(%rdi,%rdx,4)\nsub $0x1,%rdx\nmov %r10d,(%rdi)\ntest %edx,%edx\njg 1550 \npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\nlea r11d, [rsi-2]\npush rbx\nmov rdx, rdi\nlea r9d, [rsi-1]\nmov r10d, r11d\nshr r10d, 1Fh\nadd r10d, r11d\nmov ebx, r10d\nand r10d, 0FFFFFFFEh\nsar ebx, 1\ntest esi, esi\njle short loc_14B5\nnop word ptr [rax+rax+00000000h]\nloc_1450:\nmov esi, r10d\nmovsxd rcx, ebx\ncmp r10d, r9d\njl short loc_1484\njmp short loc_14A9\nloc_1460:\nmovsxd rsi, eax\nlea rdi, [rdx+rsi*4]\nmov esi, [rdi]\nloc_1469:\nlea r8, [rdx+rcx*4]\nmov ecx, [r8]\ncmp ecx, esi\njge short loc_14A9\nmov [r8], esi\nlea esi, [rax+rax]\nmov [rdi], ecx\ncmp esi, r9d\njge short loc_14A9\nmovsxd rcx, eax\nloc_1484:\nlea eax, [rsi+1]\ncmp eax, r9d\njge short loc_14A4\nmovsxd r8, eax\nshl r8, 2\nlea rdi, [rdx+r8]\nmov esi, [rdi]\ncmp esi, [rdx+r8+4]\njge short loc_1469\nlea eax, [rcx+rcx+2]\nloc_14A4:\ncmp eax, r9d\njle short loc_1460\nloc_14A9:\nsub ebx, 1\nsub r10d, 2\ncmp ebx, 0FFFFFFFFh\njnz short loc_1450\nloc_14B5:\ntest r9d, r9d\njle loc_1546\nmovsxd r9, r9d\nmov esi, [rdx]\nmovsxd r10, r11d\nlea rax, [rdx+r9*4]\nmov ecx, [rax]\nmov [rax], esi\nmov [rdx], ecx\ntest r11d, r11d\njz short loc_1546\nnop dword ptr [rax]\nloc_14D8:\nxor ecx, ecx\nxor esi, esi\nmov r9d, r10d\njmp short loc_150C\nloc_14E8:\nmovsxd rsi, eax\nlea rdi, [rdx+rsi*4]\nmov esi, [rdi]\nloc_14F1:\nlea r8, [rdx+rcx*4]\nmov ecx, [r8]\ncmp ecx, esi\njge short loc_1531\nmov [r8], esi\nlea esi, [rax+rax]\nmov [rdi], ecx\ncmp esi, r9d\njge short loc_1531\nmovsxd rcx, eax\nloc_150C:\nlea eax, [rsi+1]\ncmp eax, r10d\njge short loc_152C\nmovsxd r8, eax\nshl r8, 2\nlea rdi, [rdx+r8]\nmov esi, [rdi]\ncmp esi, [rdx+r8+4]\njge short loc_14F1\nlea eax, [rcx+rcx+2]\nloc_152C:\ncmp eax, r9d\njle short loc_14E8\nloc_1531:\nmov ecx, [rdx]\nmov eax, [rdx+r10*4]\nmov [rdx+r10*4], ecx\nsub r10, 1\nmov [rdx], eax\ntest r10d, r10d\njg short loc_14D8\nloc_1546:\npop rbx\nretn", + "ida_pseudo": "void __fastcall func0(int *a1, int a2)\n{\n int v2; // r11d\n int v4; // r9d\n signed int v5; // r10d\n int v6; // ebx\n int v7; // esi\n __int64 v8; // rcx\n int *v9; // rdi\n int v10; // esi\n int *v11; // r8\n int v12; // ecx\n int v13; // eax\n __int64 v14; // r10\n int *v15; // rax\n int v16; // ecx\n __int64 v17; // rcx\n int v18; // esi\n int *v19; // rdi\n int v20; // esi\n int *v21; // r8\n int v22; // ecx\n int v23; // eax\n int v24; // eax\n\n v2 = a2 - 2;\n v4 = a2 - 1;\n v5 = (a2 - 2 + ((unsigned int)(a2 - 2) >> 31)) & 0xFFFFFFFE;\n v6 = (a2 - 2) / 2;\n if ( a2 > 0 )\n {\n while ( 1 )\n {\n v7 = v5;\n v8 = v6;\n if ( v5 < v4 )\n break;\nLABEL_12:\n --v6;\n v5 -= 2;\n if ( v6 == -1 )\n goto LABEL_13;\n }\n while ( 1 )\n {\n v13 = v7 + 1;\n if ( v7 + 1 < v4 )\n {\n v9 = &a1[v13];\n v10 = *v9;\n if ( *v9 >= v9[1] )\n goto LABEL_5;\n v13 = 2 * v8 + 2;\n }\n if ( v13 > v4 )\n goto LABEL_12;\n v9 = &a1[v13];\n v10 = *v9;\nLABEL_5:\n v11 = &a1[v8];\n v12 = *v11;\n if ( *v11 >= v10 )\n goto LABEL_12;\n *v11 = v10;\n v7 = 2 * v13;\n *v9 = v12;\n if ( 2 * v13 >= v4 )\n goto LABEL_12;\n v8 = v13;\n }\n }\nLABEL_13:\n if ( v4 > 0 )\n {\n v14 = v2;\n v15 = &a1[v4];\n v16 = *v15;\n *v15 = *a1;\n *a1 = v16;\n if ( v2 )\n {\nLABEL_15:\n v17 = 0LL;\n v18 = 0;\n while ( 1 )\n {\n v23 = v18 + 1;\n if ( v18 + 1 < (int)v14 )\n {\n v19 = &a1[v23];\n v20 = *v19;\n if ( *v19 >= v19[1] )\n goto LABEL_17;\n v23 = 2 * v17 + 2;\n }\n if ( v23 > (int)v14 )\n goto LABEL_24;\n v19 = &a1[v23];\n v20 = *v19;\nLABEL_17:\n v21 = &a1[v17];\n v22 = *v21;\n if ( *v21 >= v20 || (*v21 = v20, v18 = 2 * v23, *v19 = v22, 2 * v23 >= (int)v14) )\n {\nLABEL_24:\n v24 = a1[v14];\n a1[v14--] = *a1;\n *a1 = v24;\n if ( (int)v14 <= 0 )\n return;\n goto LABEL_15;\n }\n v17 = v23;\n }\n }\n }\n}", + "ida_strip_asm": "sub_1420:\nendbr64\nlea r11d, [rsi-2]\npush rbx\nmov rdx, rdi\nlea r9d, [rsi-1]\nmov r10d, r11d\nshr r10d, 1Fh\nadd r10d, r11d\nmov ebx, r10d\nand r10d, 0FFFFFFFEh\nsar ebx, 1\ntest esi, esi\njle short loc_14B5\nnop word ptr [rax+rax+00000000h]\nloc_1450:\nmov esi, r10d\nmovsxd rcx, ebx\ncmp r10d, r9d\njl short loc_1484\njmp short loc_14A9\nloc_1460:\nmovsxd rsi, eax\nlea rdi, [rdx+rsi*4]\nmov esi, [rdi]\nloc_1469:\nlea r8, [rdx+rcx*4]\nmov ecx, [r8]\ncmp ecx, esi\njge short loc_14A9\nmov [r8], esi\nlea esi, [rax+rax]\nmov [rdi], ecx\ncmp esi, r9d\njge short loc_14A9\nmovsxd rcx, eax\nloc_1484:\nlea eax, [rsi+1]\ncmp eax, r9d\njge short loc_14A4\nmovsxd r8, eax\nshl r8, 2\nlea rdi, [rdx+r8]\nmov esi, [rdi]\ncmp esi, [rdx+r8+4]\njge short loc_1469\nlea eax, [rcx+rcx+2]\nloc_14A4:\ncmp eax, r9d\njle short loc_1460\nloc_14A9:\nsub ebx, 1\nsub r10d, 2\ncmp ebx, 0FFFFFFFFh\njnz short loc_1450\nloc_14B5:\ntest r9d, r9d\njle loc_1546\nmovsxd r9, r9d\nmov esi, [rdx]\nmovsxd r10, r11d\nlea rax, [rdx+r9*4]\nmov ecx, [rax]\nmov [rax], esi\nmov [rdx], ecx\ntest r11d, r11d\njz short loc_1546\nnop dword ptr [rax]\nloc_14D8:\nxor ecx, ecx\nxor esi, esi\nmov r9d, r10d\njmp short loc_150C\nloc_14E8:\nmovsxd rsi, eax\nlea rdi, [rdx+rsi*4]\nmov esi, [rdi]\nloc_14F1:\nlea r8, [rdx+rcx*4]\nmov ecx, [r8]\ncmp ecx, esi\njge short loc_1531\nmov [r8], esi\nlea esi, [rax+rax]\nmov [rdi], ecx\ncmp esi, r9d\njge short loc_1531\nmovsxd rcx, eax\nloc_150C:\nlea eax, [rsi+1]\ncmp eax, r10d\njge short loc_152C\nmovsxd r8, eax\nshl r8, 2\nlea rdi, [rdx+r8]\nmov esi, [rdi]\ncmp esi, [rdx+r8+4]\njge short loc_14F1\nlea eax, [rcx+rcx+2]\nloc_152C:\ncmp eax, r9d\njle short loc_14E8\nloc_1531:\nmov ecx, [rdx]\nmov eax, [rdx+r10*4]\nmov [rdx+r10*4], ecx\nsub r10, 1\nmov [rdx], eax\ntest r10d, r10d\njg short loc_14D8\nloc_1546:\npop rbx\nretn", + "ida_strip_pseudo": "void __fastcall sub_1420(int *a1, int a2)\n{\n int v2; // r11d\n int v4; // r9d\n signed int v5; // r10d\n int v6; // ebx\n int v7; // esi\n __int64 v8; // rcx\n int *v9; // rdi\n int v10; // esi\n int *v11; // r8\n int v12; // ecx\n int v13; // eax\n __int64 v14; // r10\n int *v15; // rax\n int v16; // ecx\n __int64 v17; // rcx\n int v18; // esi\n int *v19; // rdi\n int v20; // esi\n int *v21; // r8\n int v22; // ecx\n int v23; // eax\n int v24; // eax\n\n v2 = a2 - 2;\n v4 = a2 - 1;\n v5 = (a2 - 2 + ((unsigned int)(a2 - 2) >> 31)) & 0xFFFFFFFE;\n v6 = (a2 - 2) / 2;\n if ( a2 > 0 )\n {\n while ( 1 )\n {\n v7 = v5;\n v8 = v6;\n if ( v5 < v4 )\n break;\nLABEL_12:\n --v6;\n v5 -= 2;\n if ( v6 == -1 )\n goto LABEL_13;\n }\n while ( 1 )\n {\n v13 = v7 + 1;\n if ( v7 + 1 < v4 )\n {\n v9 = &a1[v13];\n v10 = *v9;\n if ( *v9 >= v9[1] )\n goto LABEL_5;\n v13 = 2 * v8 + 2;\n }\n if ( v13 > v4 )\n goto LABEL_12;\n v9 = &a1[v13];\n v10 = *v9;\nLABEL_5:\n v11 = &a1[v8];\n v12 = *v11;\n if ( *v11 >= v10 )\n goto LABEL_12;\n *v11 = v10;\n v7 = 2 * v13;\n *v9 = v12;\n if ( 2 * v13 >= v4 )\n goto LABEL_12;\n v8 = v13;\n }\n }\nLABEL_13:\n if ( v4 > 0 )\n {\n v14 = v2;\n v15 = &a1[v4];\n v16 = *v15;\n *v15 = *a1;\n *a1 = v16;\n if ( v2 )\n {\nLABEL_15:\n v17 = 0LL;\n v18 = 0;\n while ( 1 )\n {\n v23 = v18 + 1;\n if ( v18 + 1 < (int)v14 )\n {\n v19 = &a1[v23];\n v20 = *v19;\n if ( *v19 >= v19[1] )\n goto LABEL_17;\n v23 = 2 * v17 + 2;\n }\n if ( v23 > (int)v14 )\n goto LABEL_24;\n v19 = &a1[v23];\n v20 = *v19;\nLABEL_17:\n v21 = &a1[v17];\n v22 = *v21;\n if ( *v21 >= v20 || (*v21 = v20, v18 = 2 * v23, *v19 = v22, 2 * v23 >= (int)v14) )\n {\nLABEL_24:\n v24 = a1[v14];\n a1[v14--] = *a1;\n *a1 = v24;\n if ( (int)v14 <= 0 )\n return;\n goto LABEL_15;\n }\n v17 = v23;\n }\n }\n }\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void sub_1420(int *a1, int a2) {\n int v2;\n int v4;\n signed int v5;\n int v6;\n int v7;\n long long v8;\n int *v9;\n int v10;\n int *v11;\n int v12;\n int v13;\n long long v14;\n int *v15;\n int v16;\n long long v17;\n int v18;\n int *v19;\n int v20;\n int *v21;\n int v22;\n int v23;\n int v24;\n v2 = a2 - 2;\n v4 = a2 - 1;\n v5 = (a2 - 2 + ((unsigned int)(a2 - 2) >> 31)) & 4294967294;\n v6 = (a2 - 2) / 2;\n if (a2 > 0) {\n while (1) {\n v7 = v5;\n v8 = v6;\n if (v5 < v4) break;\n LABEL_12:\n --v6;\n v5 -= 2;\n if (v6 == -1) goto LABEL_13;\n }\n while (1) {\n v13 = v7 + 1;\n if (v7 + 1 < v4) {\n v9 = &a1[v13];\n v10 = *v9;\n if (*v9 >= v9[1]) goto LABEL_5;\n v13 = 2 * v8 + 2;\n }\n if (v13 > v4) goto LABEL_12;\n v9 = &a1[v13];\n v10 = *v9;\n LABEL_5:\n v11 = &a1[v8];\n v12 = *v11;\n if (*v11 >= v10) goto LABEL_12;\n *v11 = v10;\n v7 = 2 * v13;\n *v9 = v12;\n if (2 * v13 >= v4) goto LABEL_12;\n v8 = v13;\n }\n }\nLABEL_13:\n if (v4 > 0) {\n v14 = v2;\n v15 = &a1[v4];\n v16 = *v15;\n *v15 = *a1;\n *a1 = v16;\n if (v2) {\n LABEL_15:\n v17 = 0LL;\n v18 = 0;\n while (1) {\n v23 = v18 + 1;\n if (v18 + 1 < (int)v14) {\n v19 = &a1[v23];\n v20 = *v19;\n if (*v19 >= v19[1]) goto LABEL_17;\n v23 = 2 * v17 + 2;\n }\n if (v23 > (int)v14) goto LABEL_24;\n v19 = &a1[v23];\n v20 = *v19;\n LABEL_17:\n v21 = &a1[v17];\n v22 = *v21;\n if (*v21 >= v20 ||\n (*v21 = v20, v18 = 2 * v23, *v19 = v22, 2 * v23 >= (int)v14)) {\n LABEL_24:\n v24 = a1[v14];\n a1[v14--] = *a1;\n *a1 = v24;\n if ((int)v14 <= 0) return;\n goto LABEL_15;\n }\n v17 = v23;\n }\n }\n }\n}", + "ida_pseudo_norm": "void func0(int *a1, int a2) {\n int v2;\n int v4;\n signed int v5;\n int v6;\n int v7;\n long long v8;\n int *v9;\n int v10;\n int *v11;\n int v12;\n int v13;\n long long v14;\n int *v15;\n int v16;\n long long v17;\n int v18;\n int *v19;\n int v20;\n int *v21;\n int v22;\n int v23;\n int v24;\n v2 = a2 - 2;\n v4 = a2 - 1;\n v5 = (a2 - 2 + ((unsigned int)(a2 - 2) >> 31)) & 4294967294;\n v6 = (a2 - 2) / 2;\n if (a2 > 0) {\n while (1) {\n v7 = v5;\n v8 = v6;\n if (v5 < v4) break;\n LABEL_12:\n --v6;\n v5 -= 2;\n if (v6 == -1) goto LABEL_13;\n }\n while (1) {\n v13 = v7 + 1;\n if (v7 + 1 < v4) {\n v9 = &a1[v13];\n v10 = *v9;\n if (*v9 >= v9[1]) goto LABEL_5;\n v13 = 2 * v8 + 2;\n }\n if (v13 > v4) goto LABEL_12;\n v9 = &a1[v13];\n v10 = *v9;\n LABEL_5:\n v11 = &a1[v8];\n v12 = *v11;\n if (*v11 >= v10) goto LABEL_12;\n *v11 = v10;\n v7 = 2 * v13;\n *v9 = v12;\n if (2 * v13 >= v4) goto LABEL_12;\n v8 = v13;\n }\n }\nLABEL_13:\n if (v4 > 0) {\n v14 = v2;\n v15 = &a1[v4];\n v16 = *v15;\n *v15 = *a1;\n *a1 = v16;\n if (v2) {\n LABEL_15:\n v17 = 0LL;\n v18 = 0;\n while (1) {\n v23 = v18 + 1;\n if (v18 + 1 < (int)v14) {\n v19 = &a1[v23];\n v20 = *v19;\n if (*v19 >= v19[1]) goto LABEL_17;\n v23 = 2 * v17 + 2;\n }\n if (v23 > (int)v14) goto LABEL_24;\n v19 = &a1[v23];\n v20 = *v19;\n LABEL_17:\n v21 = &a1[v17];\n v22 = *v21;\n if (*v21 >= v20 ||\n (*v21 = v20, v18 = 2 * v23, *v19 = v22, 2 * v23 >= (int)v14)) {\n LABEL_24:\n v24 = a1[v14];\n a1[v14--] = *a1;\n *a1 = v24;\n if ((int)v14 <= 0) return;\n goto LABEL_15;\n }\n v17 = v23;\n }\n }\n }\n}" + }, + { + "index": 941, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int num[], int size) {\n int count_elim = 0;\n for (int i = 0; i < size; i++) {\n if (num[i] == -1) {\n break;\n }\n count_elim++;\n }\n return count_elim;\n}", + "test": "int main() {\n\n int arr1[] = {10, 20, 30, -1, 40}; // -1 represents tuple (10,20)\n\n int arr2[] = {10, -1, -1, 40}; // -1 represents tuples (20,30) and (10,20)\n\n int arr3[] = {-1}; // -1 represents tuple (10,(20,30,(10,20),40))\n\n \n\n assert(func0(arr1, 5) == 3);\n\n assert(func0(arr2, 4) == 1);\n\n assert(func0(arr3, 1) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11ab \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp $0xffffffff,%eax\nje 11b5 \naddl $0x1,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1188 \njmp 11b6 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11AB\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp eax, 0FFFFFFFFh\njz short loc_11B5\nadd [rbp+var_8], 1\nadd [rbp+var_4], 1\nloc_11AB:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\njmp short loc_11B6\nloc_11B5:\nnop\nloc_11B6:\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2 && *(_DWORD *)(4LL * i + a1) != -1; ++i )\n ++v3;\n return v3;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11AB\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\ncmp eax, 0FFFFFFFFh\njz short loc_11B5\nadd [rbp+var_8], 1\nadd [rbp+var_4], 1\nloc_11AB:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\njmp short loc_11B6\nloc_11B5:\nnop\nloc_11B6:\nmov eax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2)\n{\n unsigned int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2 && *(_DWORD *)(4LL * i + a1) != -1; ++i )\n ++v3;\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2 && *(uint32_t *)(4LL * i + a1) != -1; ++i) ++v3;\n return v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2 && *(uint32_t *)(4LL * i + a1) != -1; ++i) ++v3;\n return v3;\n}" + }, + { + "index": 941, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int num[], int size) {\n int count_elim = 0;\n for (int i = 0; i < size; i++) {\n if (num[i] == -1) {\n break;\n }\n count_elim++;\n }\n return count_elim;\n}", + "test": "int main() {\n\n int arr1[] = {10, 20, 30, -1, 40}; // -1 represents tuple (10,20)\n\n int arr2[] = {10, -1, -1, 40}; // -1 represents tuples (20,30) and (10,20)\n\n int arr3[] = {-1}; // -1 represents tuple (10,(20,30,(10,20),40))\n\n \n\n assert(func0(arr1, 5) == 3);\n\n assert(func0(arr2, 4) == 1);\n\n assert(func0(arr3, 1) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 1195 \nlea -0x1(%rsi),%esi\nmov $0x0,%eax\njmp 117e \nmov %rcx,%rax\nmov %eax,%edx\ncmpl $0xffffffff,(%rdi,%rax,4)\nje 1192 \nlea 0x1(%rax),%edx\nlea 0x1(%rax),%rcx\ncmp %rsi,%rax\njne 117b \nmov %edx,%eax\nretq\nmov $0x0,%edx\njmp 1192 \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_1189\nmov eax, 0\nloc_1176:\ncmp dword ptr [rdi], 0FFFFFFFFh\njz short locret_118E\nadd eax, 1\nadd rdi, 4\ncmp esi, eax\njnz short loc_1176\nmov eax, esi\nretn\nloc_1189:\nmov eax, 0\nlocret_118E:\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2)\n{\n __int64 result; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n result = 0LL;\n while ( *a1 != -1 )\n {\n result = (unsigned int)(result + 1);\n ++a1;\n if ( a2 == (_DWORD)result )\n return (unsigned int)a2;\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_1189\nmov eax, 0\nloc_1176:\ncmp dword ptr [rdi], 0FFFFFFFFh\njz short locret_118E\nadd eax, 1\nadd rdi, 4\ncmp esi, eax\njnz short loc_1176\nmov eax, esi\nretn\nloc_1189:\nmov eax, 0\nlocret_118E:\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2)\n{\n __int64 result; // rax\n\n if ( a2 <= 0 )\n return 0LL;\n result = 0LL;\n while ( *a1 != -1 )\n {\n result = (unsigned int)(result + 1);\n ++a1;\n if ( a2 == (_DWORD)result )\n return (unsigned int)a2;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2) {\n long long result;\n if (a2 <= 0) return 0LL;\n result = 0LL;\n while (*a1 != -1) {\n result = (unsigned int)(result + 1);\n ++a1;\n if (a2 == (uint32_t)result) return (unsigned int)a2;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2) {\n long long result;\n if (a2 <= 0) return 0LL;\n result = 0LL;\n while (*a1 != -1) {\n result = (unsigned int)(result + 1);\n ++a1;\n if (a2 == (uint32_t)result) return (unsigned int)a2;\n }\n return result;\n}" + }, + { + "index": 942, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int test_tup[], int tup_size, int check_list[], int list_size) {\n bool res = false;\n for (int i = 0; i < list_size; i++) {\n for (int j = 0; j < tup_size; j++) {\n if (check_list[i] == test_tup[j]) {\n res = true;\n break;\n }\n }\n if (res) break;\n }\n return res;\n}", + "test": "int main() {\n\n int test_tup1[] = {4, 5, 7, 9, 3};\n\n int check_list1[] = {6, 7, 10, 11};\n\n int test_tup2[] = {1, 2, 3, 4};\n\n int check_list2[] = {4, 6, 7, 8, 9};\n\n int test_tup3[] = {3, 2, 1, 4, 5};\n\n int check_list3[] = {9, 8, 7, 6};\n\n \n\n assert(func0(test_tup1, 5, check_list1, 4) == true);\n\n assert(func0(test_tup2, 4, check_list2, 5) == true);\n\n assert(func0(test_tup3, 5, check_list3, 4) == false);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmov %ecx,-0x20(%rbp)\nmovb $0x0,-0x9(%rbp)\nmovl $0x0,-0x8(%rbp)\njmp 11e1 \nmovl $0x0,-0x4(%rbp)\njmp 11cf \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 11cb \nmovb $0x1,-0x9(%rbp)\njmp 11d7 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1195 \ncmpb $0x0,-0x9(%rbp)\njne 11eb \naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\ncmp -0x20(%rbp),%eax\njl 118c \njmp 11ec \nmovzbl -0x9(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov [rbp+var_9], 0\nmov [rbp+var_8], 0\njmp short loc_11E1\nloc_118C:\nmov [rbp+var_4], 0\njmp short loc_11CF\nloc_1195:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11CB\nmov [rbp+var_9], 1\njmp short loc_11D7\nloc_11CB:\nadd [rbp+var_4], 1\nloc_11CF:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1195\nloc_11D7:\ncmp [rbp+var_9], 0\njnz short loc_11EB\nadd [rbp+var_8], 1\nloc_11E1:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_20]\njl short loc_118C\njmp short loc_11EC\nloc_11EB:\nnop\nloc_11EC:\nmovzx eax, [rbp+var_9]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, __int64 a3, int a4)\n{\n unsigned __int8 v5; // [rsp+1Fh] [rbp-9h]\n int i; // [rsp+20h] [rbp-8h]\n int j; // [rsp+24h] [rbp-4h]\n\n v5 = 0;\n for ( i = 0; i < a4; ++i )\n {\n for ( j = 0; j < a2; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a3) == *(_DWORD *)(4LL * j + a1) )\n {\n v5 = 1;\n break;\n }\n }\n if ( v5 )\n break;\n }\n return v5;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov [rbp+var_20], ecx\nmov [rbp+var_9], 0\nmov [rbp+var_8], 0\njmp short loc_11E1\nloc_118C:\nmov [rbp+var_4], 0\njmp short loc_11CF\nloc_1195:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njnz short loc_11CB\nmov [rbp+var_9], 1\njmp short loc_11D7\nloc_11CB:\nadd [rbp+var_4], 1\nloc_11CF:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1195\nloc_11D7:\ncmp [rbp+var_9], 0\njnz short loc_11EB\nadd [rbp+var_8], 1\nloc_11E1:\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_20]\njl short loc_118C\njmp short loc_11EC\nloc_11EB:\nnop\nloc_11EC:\nmovzx eax, [rbp+var_9]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, __int64 a3, int a4)\n{\n unsigned __int8 v5; // [rsp+1Fh] [rbp-9h]\n int i; // [rsp+20h] [rbp-8h]\n int j; // [rsp+24h] [rbp-4h]\n\n v5 = 0;\n for ( i = 0; i < a4; ++i )\n {\n for ( j = 0; j < a2; ++j )\n {\n if ( *(_DWORD *)(4LL * i + a3) == *(_DWORD *)(4LL * j + a1) )\n {\n v5 = 1;\n break;\n }\n }\n if ( v5 )\n break;\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, long long a3, int a4) {\n unsigned char v5;\n int i;\n int j;\n v5 = 0;\n for (i = 0; i < a4; ++i) {\n for (j = 0; j < a2; ++j) {\n if (*(uint32_t *)(4LL * i + a3) == *(uint32_t *)(4LL * j + a1)) {\n v5 = 1;\n break;\n }\n }\n if (v5) break;\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, long long a3, int a4) {\n unsigned char v5;\n int i;\n int j;\n v5 = 0;\n for (i = 0; i < a4; ++i) {\n for (j = 0; j < a2; ++j) {\n if (*(uint32_t *)(4LL * i + a3) == *(uint32_t *)(4LL * j + a1)) {\n v5 = 1;\n break;\n }\n }\n if (v5) break;\n }\n return v5;\n}" + }, + { + "index": 942, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int test_tup[], int tup_size, int check_list[], int list_size) {\n bool res = false;\n for (int i = 0; i < list_size; i++) {\n for (int j = 0; j < tup_size; j++) {\n if (check_list[i] == test_tup[j]) {\n res = true;\n break;\n }\n }\n if (res) break;\n }\n return res;\n}", + "test": "int main() {\n\n int test_tup1[] = {4, 5, 7, 9, 3};\n\n int check_list1[] = {6, 7, 10, 11};\n\n int test_tup2[] = {1, 2, 3, 4};\n\n int check_list2[] = {4, 6, 7, 8, 9};\n\n int test_tup3[] = {3, 2, 1, 4, 5};\n\n int check_list3[] = {9, 8, 7, 6};\n\n \n\n assert(func0(test_tup1, 5, check_list1, 4) == true);\n\n assert(func0(test_tup2, 4, check_list2, 5) == true);\n\n assert(func0(test_tup3, 5, check_list3, 4) == false);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %ecx,%ecx\njle 11ab \nmov %rdx,%r8\nlea -0x1(%rcx),%eax\nlea 0x4(%rdx,%rax,4),%r10\nmov %rdi,%r9\nlea -0x1(%rsi),%eax\nlea 0x4(%rdi,%rax,4),%rcx\njmp 1192 \nadd $0x4,%r8\ncmp %r10,%r8\nje 11b7 \ntest %esi,%esi\njle 1189 \nmov (%r8),%edx\nmov %r9,%rax\ncmp (%rax),%edx\nje 11b1 \nadd $0x4,%rax\ncmp %rcx,%rax\njne 119c \njmp 1189 \nmov $0x0,%eax\nretq\nmov $0x1,%eax\nretq\nmov $0x0,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\nmov r8, rdi\ntest ecx, ecx\njle short loc_11A8\nmov rdi, rdx\nmovsxd rcx, ecx\nlea r9, [rdx+rcx*4]\nmovsxd rax, esi\nlea rcx, [r8+rax*4]\njmp short loc_1190\nloc_1187:\nadd rdi, 4\ncmp rdi, r9\njz short loc_11B4\nloc_1190:\ntest esi, esi\njle short loc_1187\nmov edx, [rdi]\nmov rax, r8\nloc_1199:\ncmp edx, [rax]\njz short loc_11AE\nadd rax, 4\ncmp rax, rcx\njnz short loc_1199\njmp short loc_1187\nloc_11A8:\nmov eax, 0\nretn\nloc_11AE:\nmov eax, 1\nretn\nloc_11B4:\nmov eax, 0\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2, _DWORD *a3, int a4)\n{\n _DWORD *v5; // rdi\n _DWORD *v6; // rax\n\n if ( a4 <= 0 )\n return 0LL;\n v5 = a3;\n while ( a2 <= 0 )\n {\nLABEL_3:\n if ( ++v5 == &a3[a4] )\n return 0LL;\n }\n v6 = a1;\n while ( *v5 != *v6 )\n {\n if ( ++v6 == &a1[a2] )\n goto LABEL_3;\n }\n return 1LL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nmov r8, rdi\ntest ecx, ecx\njle short loc_11A8\nmov rdi, rdx\nmovsxd rcx, ecx\nlea r9, [rdx+rcx*4]\nmovsxd rax, esi\nlea rcx, [r8+rax*4]\njmp short loc_1190\nloc_1187:\nadd rdi, 4\ncmp rdi, r9\njz short loc_11B4\nloc_1190:\ntest esi, esi\njle short loc_1187\nmov edx, [rdi]\nmov rax, r8\nloc_1199:\ncmp edx, [rax]\njz short loc_11AE\nadd rax, 4\ncmp rax, rcx\njnz short loc_1199\njmp short loc_1187\nloc_11A8:\nmov eax, 0\nretn\nloc_11AE:\nmov eax, 1\nretn\nloc_11B4:\nmov eax, 0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(_DWORD *a1, int a2, _DWORD *a3, int a4)\n{\n _DWORD *v5; // rdi\n _DWORD *v6; // rax\n\n if ( a4 <= 0 )\n return 0LL;\n v5 = a3;\n while ( a2 <= 0 )\n {\nLABEL_3:\n if ( ++v5 == &a3[a4] )\n return 0LL;\n }\n v6 = a1;\n while ( *v5 != *v6 )\n {\n if ( ++v6 == &a1[a2] )\n goto LABEL_3;\n }\n return 1LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(uint32_t *a1, int a2, uint32_t *a3, int a4) {\n uint32_t *v5;\n uint32_t *v6;\n if (a4 <= 0) return 0LL;\n v5 = a3;\n while (a2 <= 0) {\n LABEL_3:\n if (++v5 == &a3[a4]) return 0LL;\n }\n v6 = a1;\n while (*v5 != *v6) {\n if (++v6 == &a1[a2]) goto LABEL_3;\n }\n return 1LL;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2, uint32_t *a3, int a4) {\n uint32_t *v5;\n uint32_t *v6;\n if (a4 <= 0) return 0LL;\n v5 = a3;\n while (a2 <= 0) {\n LABEL_3:\n if (++v5 == &a3[a4]) return 0LL;\n }\n v6 = a1;\n while (*v5 != *v6) {\n if (++v6 == &a1[a2]) goto LABEL_3;\n }\n return 1LL;\n}" + }, + { + "index": 942, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "bool func0(int test_tup[], int tup_size, int check_list[], int list_size) {\n bool res = false;\n for (int i = 0; i < list_size; i++) {\n for (int j = 0; j < tup_size; j++) {\n if (check_list[i] == test_tup[j]) {\n res = true;\n break;\n }\n }\n if (res) break;\n }\n return res;\n}", + "test": "int main() {\n\n int test_tup1[] = {4, 5, 7, 9, 3};\n\n int check_list1[] = {6, 7, 10, 11};\n\n int test_tup2[] = {1, 2, 3, 4};\n\n int check_list2[] = {4, 6, 7, 8, 9};\n\n int test_tup3[] = {3, 2, 1, 4, 5};\n\n int check_list3[] = {9, 8, 7, 6};\n\n \n\n assert(func0(test_tup1, 5, check_list1, 4) == true);\n\n assert(func0(test_tup2, 4, check_list2, 5) == true);\n\n assert(func0(test_tup3, 5, check_list3, 4) == false);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %ecx,%ecx\njle 1371 \nlea -0x1(%rcx),%eax\nmov %rdx,%r8\nlea 0x4(%rdx,%rax,4),%r9\nlea -0x1(%rsi),%eax\nlea 0x4(%rdi,%rax,4),%rcx\nnopl 0x0(%rax,%rax,1)\ntest %esi,%esi\njle 1368 \nmov (%r8),%edx\nmov %rdi,%rax\njmp 1359 \nnopl 0x0(%rax)\nadd $0x4,%rax\ncmp %rcx,%rax\nje 1368 \ncmp (%rax),%edx\njne 1350 \nmov $0x1,%eax\nretq\nnopl 0x0(%rax,%rax,1)\nadd $0x4,%r8\ncmp %r9,%r8\njne 1340 \nxor %eax,%eax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\nmov r8, rdi\ntest ecx, ecx\njle short loc_1321\nmovsxd rcx, ecx\nmovsxd rax, esi\nlea r9, [rdx+rcx*4]\nlea rdi, [rdi+rax*4]\nnop dword ptr [rax+00000000h]\nloc_12F0:\ntest esi, esi\njle short loc_1318\nloc_12F4:\nmov ecx, [rdx]\nmov rax, r8\njmp short loc_1309\nloc_1300:\nadd rax, 4\ncmp rax, rdi\njz short loc_1328\nloc_1309:\ncmp ecx, [rax]\njnz short loc_1300\nmov eax, 1\nretn\nloc_1318:\nadd rdx, 4\ncmp rdx, r9\njnz short loc_12F0\nloc_1321:\nxor eax, eax\nretn\nloc_1328:\nadd rdx, 4\ncmp rdx, r9\njnz short loc_12F4\nxor eax, eax\nretn", + "ida_pseudo": "__int64 __fastcall func0(_DWORD *a1, int a2, _DWORD *a3, int a4)\n{\n _DWORD *v5; // r9\n _DWORD *v6; // rdi\n _DWORD *v7; // rax\n\n if ( a4 <= 0 )\n return 0LL;\n v5 = &a3[a4];\n v6 = &a1[a2];\n while ( a2 <= 0 )\n {\n if ( ++a3 == v5 )\n return 0LL;\n }\n do\n {\n v7 = a1;\n do\n {\n if ( *a3 == *v7 )\n return 1LL;\n ++v7;\n }\n while ( v7 != v6 );\n ++a3;\n }\n while ( a3 != v5 );\n return 0LL;\n}", + "ida_strip_asm": "sub_12D0:\nendbr64\nmov r8, rdi\ntest ecx, ecx\njle short loc_1321\nmovsxd rcx, ecx\nmovsxd rax, esi\nlea r9, [rdx+rcx*4]\nlea rdi, [rdi+rax*4]\nnop dword ptr [rax+00000000h]\nloc_12F0:\ntest esi, esi\njle short loc_1318\nloc_12F4:\nmov ecx, [rdx]\nmov rax, r8\njmp short loc_1309\nloc_1300:\nadd rax, 4\ncmp rax, rdi\njz short loc_1328\nloc_1309:\ncmp ecx, [rax]\njnz short loc_1300\nmov eax, 1\nretn\nloc_1318:\nadd rdx, 4\ncmp rdx, r9\njnz short loc_12F0\nloc_1321:\nxor eax, eax\nretn\nloc_1328:\nadd rdx, 4\ncmp rdx, r9\njnz short loc_12F4\nxor eax, eax\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12D0(_DWORD *a1, int a2, _DWORD *a3, int a4)\n{\n _DWORD *v5; // r9\n _DWORD *v6; // rdi\n _DWORD *v7; // rax\n\n if ( a4 <= 0 )\n return 0LL;\n v5 = &a3[a4];\n v6 = &a1[a2];\n while ( a2 <= 0 )\n {\n if ( ++a3 == v5 )\n return 0LL;\n }\n do\n {\n v7 = a1;\n do\n {\n if ( *a3 == *v7 )\n return 1LL;\n ++v7;\n }\n while ( v7 != v6 );\n ++a3;\n }\n while ( a3 != v5 );\n return 0LL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12D0(uint32_t *a1, int a2, uint32_t *a3, int a4) {\n uint32_t *v5;\n uint32_t *v6;\n uint32_t *v7;\n if (a4 <= 0) return 0LL;\n v5 = &a3[a4];\n v6 = &a1[a2];\n while (a2 <= 0) {\n if (++a3 == v5) return 0LL;\n }\n do {\n v7 = a1;\n do {\n if (*a3 == *v7) return 1LL;\n ++v7;\n } while (v7 != v6);\n ++a3;\n } while (a3 != v5);\n return 0LL;\n}", + "ida_pseudo_norm": "long long func0(uint32_t *a1, int a2, uint32_t *a3, int a4) {\n uint32_t *v5;\n uint32_t *v6;\n uint32_t *v7;\n if (a4 <= 0) return 0LL;\n v5 = &a3[a4];\n v6 = &a1[a2];\n while (a2 <= 0) {\n if (++a3 == v5) return 0LL;\n }\n do {\n v7 = a1;\n do {\n if (*a3 == *v7) return 1LL;\n ++v7;\n } while (v7 != v6);\n ++a3;\n } while (a3 != v5);\n return 0LL;\n}" + }, + { + "index": 943, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int *func0(int *num1, int size1, int *num2, int size2) {\n int *result = (int *)malloc((size1 + size2) * sizeof(int));\n int i = 0, j = 0, k = 0;\n while (i < size1 && j < size2) {\n if (num1[i] < num2[j]) {\n result[k++] = num1[i++];\n } else {\n result[k++] = num2[j++];\n }\n }\n while (i < size1) {\n result[k++] = num1[i++];\n }\n while (j < size2) {\n result[k++] = num2[j++];\n }\n return result;\n}", + "test": "int main() {\n\n int arr1[] = {1, 3, 5, 7, 9, 11};\n\n int arr2[] = {0, 2, 4, 6, 8, 10};\n\n int expected1[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11};\n\n int* result1 = func0(arr1, 6, arr2, 6);\n\n for (int i = 0; i < 12; i++) assert(result1[i] == expected1[i]);\n\n\n\n int arr3[] = {1, 3, 5, 6, 8, 9};\n\n int arr4[] = {2, 5, 7, 11};\n\n int expected2[] = {1, 2, 3, 5, 5, 6, 7, 8, 9, 11};\n\n int* result2 = func0(arr3, 6, arr4, 4);\n\n for (int i = 0; i < 10; i++) assert(result2[i] == expected2[i]);\n\n\n\n int arr5[] = {1, 3, 7};\n\n int arr6[] = {2, 4, 6};\n\n int expected3[] = {1, 2, 3, 4, 6, 7};\n\n int* result3 = func0(arr5, 3, arr6, 3);\n\n for (int i = 0; i < 6; i++) assert(result3[i] == expected3[i]);\n\n\n\n // Free allocated memory\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0; \n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x40,%rsp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmov %rdx,-0x38(%rbp)\nmov %ecx,-0x30(%rbp)\nmov -0x2c(%rbp),%edx\nmov -0x30(%rbp),%eax\nadd %edx,%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0x14(%rbp)\nmovl $0x0,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\njmpq 12bb \nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x10(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x38(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njge 1282 \nmov -0x14(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x14(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0xc(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0xc(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\njmp 12bb \nmov -0x10(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x10(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x38(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0xc(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0xc(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\nmov -0x14(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njge 130a \nmov -0x10(%rbp),%eax\ncmp -0x30(%rbp),%eax\njl 1217 \njmp 130a \nmov -0x14(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x14(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0xc(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0xc(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\nmov -0x14(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 12d1 \njmp 134d \nmov -0x10(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x10(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x38(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0xc(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0xc(%rbp)\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%eax\nmov %eax,(%rdx)\nmov -0x10(%rbp),%eax\ncmp -0x30(%rbp),%eax\njl 1314 \nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmov [rbp+var_30], ecx\nmov edx, [rbp+var_2C]\nmov eax, [rbp+var_30]\nadd eax, edx\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp loc_12BB\nloc_1217:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njge short loc_1282\nmov eax, [rbp+var_14]\nlea edx, [rax+1]\nmov [rbp+var_14], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\njmp short loc_12BB\nloc_1282:\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_12BB:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njge short loc_130A\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_30]\njl loc_1217\njmp short loc_130A\nloc_12D1:\nmov eax, [rbp+var_14]\nlea edx, [rax+1]\nmov [rbp+var_14], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_130A:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl short loc_12D1\njmp short loc_134D\nloc_1314:\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_134D:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_30]\njl short loc_1314\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, __int64 a3, int a4)\n{\n int v4; // eax\n _DWORD *v5; // rcx\n int v6; // eax\n int v7; // eax\n int v8; // eax\n _DWORD *v9; // rcx\n int v10; // eax\n int v11; // eax\n _DWORD *v12; // rcx\n int v13; // eax\n int v17; // [rsp+2Ch] [rbp-14h]\n int v18; // [rsp+30h] [rbp-10h]\n int v19; // [rsp+34h] [rbp-Ch]\n _DWORD *v20; // [rsp+38h] [rbp-8h]\n\n v20 = malloc(4LL * (a2 + a4));\n v17 = 0;\n v18 = 0;\n v19 = 0;\n while ( v17 < a2 && v18 < a4 )\n {\n if ( *(_DWORD *)(4LL * v17 + a1) >= *(_DWORD *)(4LL * v18 + a3) )\n {\n v7 = v18++;\n v5 = (_DWORD *)(4LL * v7 + a3);\n }\n else\n {\n v4 = v17++;\n v5 = (_DWORD *)(4LL * v4 + a1);\n }\n v6 = v19++;\n v20[v6] = *v5;\n }\n while ( v17 < a2 )\n {\n v8 = v17++;\n v9 = (_DWORD *)(4LL * v8 + a1);\n v10 = v19++;\n v20[v10] = *v9;\n }\n while ( v18 < a4 )\n {\n v11 = v18++;\n v12 = (_DWORD *)(4LL * v11 + a3);\n v13 = v19++;\n v20[v13] = *v12;\n }\n return v20;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_38], rdx\nmov [rbp+var_30], ecx\nmov edx, [rbp+var_2C]\nmov eax, [rbp+var_30]\nadd eax, edx\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_14], 0\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp loc_12BB\nloc_1217:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_10]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njge short loc_1282\nmov eax, [rbp+var_14]\nlea edx, [rax+1]\nmov [rbp+var_14], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\njmp short loc_12BB\nloc_1282:\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_12BB:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njge short loc_130A\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_30]\njl loc_1217\njmp short loc_130A\nloc_12D1:\nmov eax, [rbp+var_14]\nlea edx, [rax+1]\nmov [rbp+var_14], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_130A:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl short loc_12D1\njmp short loc_134D\nloc_1314:\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_38]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_C]\nlea edx, [rax+1]\nmov [rbp+var_C], edx\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov eax, [rcx]\nmov [rdx], eax\nloc_134D:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_30]\njl short loc_1314\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11C9(__int64 a1, int a2, __int64 a3, int a4)\n{\n int v4; // eax\n _DWORD *v5; // rcx\n int v6; // eax\n int v7; // eax\n int v8; // eax\n _DWORD *v9; // rcx\n int v10; // eax\n int v11; // eax\n _DWORD *v12; // rcx\n int v13; // eax\n int v17; // [rsp+2Ch] [rbp-14h]\n int v18; // [rsp+30h] [rbp-10h]\n int v19; // [rsp+34h] [rbp-Ch]\n _DWORD *v20; // [rsp+38h] [rbp-8h]\n\n v20 = malloc(4LL * (a2 + a4));\n v17 = 0;\n v18 = 0;\n v19 = 0;\n while ( v17 < a2 && v18 < a4 )\n {\n if ( *(_DWORD *)(4LL * v17 + a1) >= *(_DWORD *)(4LL * v18 + a3) )\n {\n v7 = v18++;\n v5 = (_DWORD *)(4LL * v7 + a3);\n }\n else\n {\n v4 = v17++;\n v5 = (_DWORD *)(4LL * v4 + a1);\n }\n v6 = v19++;\n v20[v6] = *v5;\n }\n while ( v17 < a2 )\n {\n v8 = v17++;\n v9 = (_DWORD *)(4LL * v8 + a1);\n v10 = v19++;\n v20[v10] = *v9;\n }\n while ( v18 < a4 )\n {\n v11 = v18++;\n v12 = (_DWORD *)(4LL * v11 + a3);\n v13 = v19++;\n v20[v13] = *v12;\n }\n return v20;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11C9(long long a1, int a2, long long a3, int a4) {\n int v4;\n uint32_t *v5;\n int v6;\n int v7;\n int v8;\n uint32_t *v9;\n int v10;\n int v11;\n uint32_t *v12;\n int v13;\n int v17;\n int v18;\n int v19;\n uint32_t *v20;\n v20 = malloc(4LL * (a2 + a4));\n v17 = 0;\n v18 = 0;\n v19 = 0;\n while (v17 < a2 && v18 < a4) {\n if (*(uint32_t *)(4LL * v17 + a1) >= *(uint32_t *)(4LL * v18 + a3)) {\n v7 = v18++;\n v5 = (uint32_t *)(4LL * v7 + a3);\n } else {\n v4 = v17++;\n v5 = (uint32_t *)(4LL * v4 + a1);\n }\n v6 = v19++;\n v20[v6] = *v5;\n }\n while (v17 < a2) {\n v8 = v17++;\n v9 = (uint32_t *)(4LL * v8 + a1);\n v10 = v19++;\n v20[v10] = *v9;\n }\n while (v18 < a4) {\n v11 = v18++;\n v12 = (uint32_t *)(4LL * v11 + a3);\n v13 = v19++;\n v20[v13] = *v12;\n }\n return v20;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, long long a3, int a4) {\n int v4;\n uint32_t *v5;\n int v6;\n int v7;\n int v8;\n uint32_t *v9;\n int v10;\n int v11;\n uint32_t *v12;\n int v13;\n int v17;\n int v18;\n int v19;\n uint32_t *v20;\n v20 = malloc(4LL * (a2 + a4));\n v17 = 0;\n v18 = 0;\n v19 = 0;\n while (v17 < a2 && v18 < a4) {\n if (*(uint32_t *)(4LL * v17 + a1) >= *(uint32_t *)(4LL * v18 + a3)) {\n v7 = v18++;\n v5 = (uint32_t *)(4LL * v7 + a3);\n } else {\n v4 = v17++;\n v5 = (uint32_t *)(4LL * v4 + a1);\n }\n v6 = v19++;\n v20[v6] = *v5;\n }\n while (v17 < a2) {\n v8 = v17++;\n v9 = (uint32_t *)(4LL * v8 + a1);\n v10 = v19++;\n v20[v10] = *v9;\n }\n while (v18 < a4) {\n v11 = v18++;\n v12 = (uint32_t *)(4LL * v11 + a3);\n v13 = v19++;\n v20[v13] = *v12;\n }\n return v20;\n}" + }, + { + "index": 943, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int *func0(int *num1, int size1, int *num2, int size2) {\n int *result = (int *)malloc((size1 + size2) * sizeof(int));\n int i = 0, j = 0, k = 0;\n while (i < size1 && j < size2) {\n if (num1[i] < num2[j]) {\n result[k++] = num1[i++];\n } else {\n result[k++] = num2[j++];\n }\n }\n while (i < size1) {\n result[k++] = num1[i++];\n }\n while (j < size2) {\n result[k++] = num2[j++];\n }\n return result;\n}", + "test": "int main() {\n\n int arr1[] = {1, 3, 5, 7, 9, 11};\n\n int arr2[] = {0, 2, 4, 6, 8, 10};\n\n int expected1[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11};\n\n int* result1 = func0(arr1, 6, arr2, 6);\n\n for (int i = 0; i < 12; i++) assert(result1[i] == expected1[i]);\n\n\n\n int arr3[] = {1, 3, 5, 6, 8, 9};\n\n int arr4[] = {2, 5, 7, 11};\n\n int expected2[] = {1, 2, 3, 5, 5, 6, 7, 8, 9, 11};\n\n int* result2 = func0(arr3, 6, arr4, 4);\n\n for (int i = 0; i < 10; i++) assert(result2[i] == expected2[i]);\n\n\n\n int arr5[] = {1, 3, 7};\n\n int arr6[] = {2, 4, 6};\n\n int expected3[] = {1, 2, 3, 4, 6, 7};\n\n int* result3 = func0(arr5, 3, arr6, 3);\n\n for (int i = 0; i < 6; i++) assert(result3[i] == expected3[i]);\n\n\n\n // Free allocated memory\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0; \n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%r13\nmov %esi,%ebx\nmov %rdx,%r12\nmov %ecx,%ebp\nlea (%rsi,%rcx,1),%edi\nmovslq %edi,%rdi\nshl $0x2,%rdi\ncallq 10d0 \ntest %ebx,%ebx\njle 123f \ntest %ebp,%ebp\njle 123f \nmov $0x0,%ecx\nmov $0x0,%edx\nmov $0x0,%edi\njmp 121f \nadd $0x1,%edx\nlea 0x1(%rcx),%esi\nmov %r8d,(%rax,%rcx,4)\nadd $0x1,%rcx\ncmp %ebx,%edi\njge 124e \ncmp %ebp,%edx\njge 124e \nmovslq %edi,%rsi\nmov 0x0(%r13,%rsi,4),%r9d\nmovslq %edx,%rsi\nmov (%r12,%rsi,4),%r8d\ncmp %r8d,%r9d\njge 1209 \nadd $0x1,%edi\nlea 0x1(%rcx),%esi\nmov %r9d,(%rax,%rcx,4)\njmp 1213 \nmov $0x0,%esi\nmov $0x0,%edx\nmov $0x0,%edi\ncmp %edi,%ebx\njle 1276 \nmovslq %edi,%rcx\nmovslq %esi,%r8\nsub %rcx,%r8\nlea (%rax,%r8,4),%r9\nmov 0x0(%r13,%rcx,4),%r8d\nmov %r8d,(%r9,%rcx,4)\nadd $0x1,%rcx\ncmp %ecx,%ebx\njg 125f \nadd %esi,%ebx\nsub %edi,%ebx\nmov %ebx,%esi\ncmp %edx,%ebp\njle 1296 \nmovslq %edx,%rdx\nmovslq %esi,%rbx\nsub %rdx,%rbx\nlea (%rax,%rbx,4),%rsi\nmov (%r12,%rdx,4),%ecx\nmov %ecx,(%rsi,%rdx,4)\nadd $0x1,%rdx\ncmp %edx,%ebp\njg 1287 \nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r13, rdi\nmov ebp, esi\nmov r12, rdx\nmov ebx, ecx\nlea edi, [rsi+rcx]\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov rdi, rax\ntest ebp, ebp\njle short loc_1246\ntest ebx, ebx\njle short loc_1246\nmov rsi, rax\nmov ecx, 1\nmov edx, 0\nmov eax, 0\njmp short loc_1227\nloc_120F:\nadd edx, 1\nmov r8d, ecx\nmov [rsi], r9d\nloc_1218:\nadd ecx, 1\nadd rsi, 4\ncmp eax, ebp\njge short loc_1256\ncmp edx, ebx\njge short loc_1256\nloc_1227:\nmovsxd r8, eax\nmov r10d, [r13+r8*4+0]\nmovsxd r8, edx\nmov r9d, [r12+r8*4]\ncmp r10d, r9d\njge short loc_120F\nadd eax, 1\nmov r8d, ecx\nmov [rsi], r10d\njmp short loc_1218\nloc_1246:\nmov r8d, 0\nmov edx, 0\nmov eax, 0\nloc_1256:\ncmp ebp, eax\njle short loc_1292\nmov r10d, eax\nmov esi, ebp\nsub esi, eax\nshl rsi, 2\ncdqe\nlea r11, [r13+rax*4+0]\nmovsxd rax, r8d\nlea r9, [rdi+rax*4]\nmov eax, 0\nloc_1278:\nmov ecx, [r11+rax]\nmov [r9+rax], ecx\nadd rax, 4\ncmp rax, rsi\njnz short loc_1278\nadd ebp, r8d\nmov r8d, ebp\nsub r8d, r10d\nloc_1292:\ncmp ebx, edx\njle short loc_12BE\nsub ebx, edx\nshl rbx, 2\nmovsxd rdx, edx\nlea rsi, [r12+rdx*4]\nmovsxd r8, r8d\nlea rcx, [rdi+r8*4]\nmov eax, 0\nloc_12AF:\nmov edx, [rsi+rax]\nmov [rcx+rax], edx\nadd rax, 4\ncmp rax, rbx\njnz short loc_12AF\nloc_12BE:\nmov rax, rdi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, __int64 a3, int a4)\n{\n _DWORD *v8; // rax\n _DWORD *v9; // rdi\n _DWORD *v10; // rsi\n int v11; // ecx\n int v12; // edx\n int v13; // eax\n int v14; // r8d\n int v15; // r10d\n int v16; // r9d\n int v17; // r10d\n __int64 v18; // rsi\n __int64 v19; // r11\n unsigned __int64 v20; // rax\n __int64 v21; // rbx\n unsigned __int64 v22; // rax\n\n v8 = malloc(4LL * (a2 + a4));\n v9 = v8;\n if ( a2 <= 0 || a4 <= 0 )\n {\n v14 = 0;\n v12 = 0;\n v13 = 0;\n }\n else\n {\n v10 = v8;\n v11 = 1;\n v12 = 0;\n v13 = 0;\n do\n {\n v15 = *(_DWORD *)(a1 + 4LL * v13);\n v16 = *(_DWORD *)(a3 + 4LL * v12);\n if ( v15 >= v16 )\n {\n ++v12;\n v14 = v11;\n *v10 = v16;\n }\n else\n {\n ++v13;\n v14 = v11;\n *v10 = v15;\n }\n ++v11;\n ++v10;\n }\n while ( v13 < a2 && v12 < a4 );\n }\n if ( a2 > v13 )\n {\n v17 = v13;\n v18 = 4LL * (unsigned int)(a2 - v13);\n v19 = a1 + 4LL * v13;\n v20 = 0LL;\n do\n {\n v9[v14 + v20 / 4] = *(_DWORD *)(v19 + v20);\n v20 += 4LL;\n }\n while ( v20 != v18 );\n v14 = v14 + a2 - v17;\n }\n if ( a4 > v12 )\n {\n v21 = 4LL * (unsigned int)(a4 - v12);\n v22 = 0LL;\n do\n {\n v9[v14 + v22 / 4] = *(_DWORD *)(a3 + 4LL * v12 + v22);\n v22 += 4LL;\n }\n while ( v22 != v21 );\n }\n return v9;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r13, rdi\nmov ebp, esi\nmov r12, rdx\nmov ebx, ecx\nlea edi, [rsi+rcx]\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\nmov rdi, rax\ntest ebp, ebp\njle short loc_1246\ntest ebx, ebx\njle short loc_1246\nmov rsi, rax\nmov ecx, 1\nmov edx, 0\nmov eax, 0\njmp short loc_1227\nloc_120F:\nadd edx, 1\nmov r8d, ecx\nmov [rsi], r9d\nloc_1218:\nadd ecx, 1\nadd rsi, 4\ncmp eax, ebp\njge short loc_1256\ncmp edx, ebx\njge short loc_1256\nloc_1227:\nmovsxd r8, eax\nmov r10d, [r13+r8*4+0]\nmovsxd r8, edx\nmov r9d, [r12+r8*4]\ncmp r10d, r9d\njge short loc_120F\nadd eax, 1\nmov r8d, ecx\nmov [rsi], r10d\njmp short loc_1218\nloc_1246:\nmov r8d, 0\nmov edx, 0\nmov eax, 0\nloc_1256:\ncmp ebp, eax\njle short loc_1292\nmov r10d, eax\nmov esi, ebp\nsub esi, eax\nshl rsi, 2\ncdqe\nlea r11, [r13+rax*4+0]\nmovsxd rax, r8d\nlea r9, [rdi+rax*4]\nmov eax, 0\nloc_1278:\nmov ecx, [r11+rax]\nmov [r9+rax], ecx\nadd rax, 4\ncmp rax, rsi\njnz short loc_1278\nadd ebp, r8d\nmov r8d, ebp\nsub r8d, r10d\nloc_1292:\ncmp ebx, edx\njle short loc_12BE\nsub ebx, edx\nshl rbx, 2\nmovsxd rdx, edx\nlea rsi, [r12+rdx*4]\nmovsxd r8, r8d\nlea rcx, [rdi+r8*4]\nmov eax, 0\nloc_12AF:\nmov edx, [rsi+rax]\nmov [rcx+rax], edx\nadd rax, 4\ncmp rax, rbx\njnz short loc_12AF\nloc_12BE:\nmov rax, rdi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11C9(__int64 a1, int a2, __int64 a3, int a4)\n{\n _DWORD *v8; // rax\n _DWORD *v9; // rdi\n _DWORD *v10; // rsi\n int v11; // ecx\n int v12; // edx\n int v13; // eax\n int v14; // r8d\n int v15; // r10d\n int v16; // r9d\n int v17; // r10d\n __int64 v18; // rsi\n __int64 v19; // r11\n unsigned __int64 v20; // rax\n __int64 v21; // rbx\n unsigned __int64 v22; // rax\n\n v8 = malloc(4LL * (a2 + a4));\n v9 = v8;\n if ( a2 <= 0 || a4 <= 0 )\n {\n v14 = 0;\n v12 = 0;\n v13 = 0;\n }\n else\n {\n v10 = v8;\n v11 = 1;\n v12 = 0;\n v13 = 0;\n do\n {\n v15 = *(_DWORD *)(a1 + 4LL * v13);\n v16 = *(_DWORD *)(a3 + 4LL * v12);\n if ( v15 >= v16 )\n {\n ++v12;\n v14 = v11;\n *v10 = v16;\n }\n else\n {\n ++v13;\n v14 = v11;\n *v10 = v15;\n }\n ++v11;\n ++v10;\n }\n while ( v13 < a2 && v12 < a4 );\n }\n if ( a2 > v13 )\n {\n v17 = v13;\n v18 = 4LL * (unsigned int)(a2 - v13);\n v19 = a1 + 4LL * v13;\n v20 = 0LL;\n do\n {\n v9[v14 + v20 / 4] = *(_DWORD *)(v19 + v20);\n v20 += 4LL;\n }\n while ( v20 != v18 );\n v14 = v14 + a2 - v17;\n }\n if ( a4 > v12 )\n {\n v21 = 4LL * (unsigned int)(a4 - v12);\n v22 = 0LL;\n do\n {\n v9[v14 + v22 / 4] = *(_DWORD *)(a3 + 4LL * v12 + v22);\n v22 += 4LL;\n }\n while ( v22 != v21 );\n }\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11C9(long long a1, int a2, long long a3, int a4) {\n uint32_t *v8;\n uint32_t *v9;\n uint32_t *v10;\n int v11;\n int v12;\n int v13;\n int v14;\n int v15;\n int v16;\n int v17;\n long long v18;\n long long v19;\n unsigned long long v20;\n long long v21;\n unsigned long long v22;\n v8 = malloc(4LL * (a2 + a4));\n v9 = v8;\n if (a2 <= 0 || a4 <= 0) {\n v14 = 0;\n v12 = 0;\n v13 = 0;\n } else {\n v10 = v8;\n v11 = 1;\n v12 = 0;\n v13 = 0;\n do {\n v15 = *(uint32_t *)(a1 + 4LL * v13);\n v16 = *(uint32_t *)(a3 + 4LL * v12);\n if (v15 >= v16) {\n ++v12;\n v14 = v11;\n *v10 = v16;\n } else {\n ++v13;\n v14 = v11;\n *v10 = v15;\n }\n ++v11;\n ++v10;\n } while (v13 < a2 && v12 < a4);\n }\n if (a2 > v13) {\n v17 = v13;\n v18 = 4LL * (unsigned int)(a2 - v13);\n v19 = a1 + 4LL * v13;\n v20 = 0LL;\n do {\n v9[v14 + v20 / 4] = *(uint32_t *)(v19 + v20);\n v20 += 4LL;\n } while (v20 != v18);\n v14 = v14 + a2 - v17;\n }\n if (a4 > v12) {\n v21 = 4LL * (unsigned int)(a4 - v12);\n v22 = 0LL;\n do {\n v9[v14 + v22 / 4] = *(uint32_t *)(a3 + 4LL * v12 + v22);\n v22 += 4LL;\n } while (v22 != v21);\n }\n return v9;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, long long a3, int a4) {\n uint32_t *v8;\n uint32_t *v9;\n uint32_t *v10;\n int v11;\n int v12;\n int v13;\n int v14;\n int v15;\n int v16;\n int v17;\n long long v18;\n long long v19;\n unsigned long long v20;\n long long v21;\n unsigned long long v22;\n v8 = malloc(4LL * (a2 + a4));\n v9 = v8;\n if (a2 <= 0 || a4 <= 0) {\n v14 = 0;\n v12 = 0;\n v13 = 0;\n } else {\n v10 = v8;\n v11 = 1;\n v12 = 0;\n v13 = 0;\n do {\n v15 = *(uint32_t *)(a1 + 4LL * v13);\n v16 = *(uint32_t *)(a3 + 4LL * v12);\n if (v15 >= v16) {\n ++v12;\n v14 = v11;\n *v10 = v16;\n } else {\n ++v13;\n v14 = v11;\n *v10 = v15;\n }\n ++v11;\n ++v10;\n } while (v13 < a2 && v12 < a4);\n }\n if (a2 > v13) {\n v17 = v13;\n v18 = 4LL * (unsigned int)(a2 - v13);\n v19 = a1 + 4LL * v13;\n v20 = 0LL;\n do {\n v9[v14 + v20 / 4] = *(uint32_t *)(v19 + v20);\n v20 += 4LL;\n } while (v20 != v18);\n v14 = v14 + a2 - v17;\n }\n if (a4 > v12) {\n v21 = 4LL * (unsigned int)(a4 - v12);\n v22 = 0LL;\n do {\n v9[v14 + v22 / 4] = *(uint32_t *)(a3 + 4LL * v12 + v22);\n v22 += 4LL;\n } while (v22 != v21);\n }\n return v9;\n}" + }, + { + "index": 943, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int *func0(int *num1, int size1, int *num2, int size2) {\n int *result = (int *)malloc((size1 + size2) * sizeof(int));\n int i = 0, j = 0, k = 0;\n while (i < size1 && j < size2) {\n if (num1[i] < num2[j]) {\n result[k++] = num1[i++];\n } else {\n result[k++] = num2[j++];\n }\n }\n while (i < size1) {\n result[k++] = num1[i++];\n }\n while (j < size2) {\n result[k++] = num2[j++];\n }\n return result;\n}", + "test": "int main() {\n\n int arr1[] = {1, 3, 5, 7, 9, 11};\n\n int arr2[] = {0, 2, 4, 6, 8, 10};\n\n int expected1[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11};\n\n int* result1 = func0(arr1, 6, arr2, 6);\n\n for (int i = 0; i < 12; i++) assert(result1[i] == expected1[i]);\n\n\n\n int arr3[] = {1, 3, 5, 6, 8, 9};\n\n int arr4[] = {2, 5, 7, 11};\n\n int expected2[] = {1, 2, 3, 5, 5, 6, 7, 8, 9, 11};\n\n int* result2 = func0(arr3, 6, arr4, 4);\n\n for (int i = 0; i < 10; i++) assert(result2[i] == expected2[i]);\n\n\n\n int arr5[] = {1, 3, 7};\n\n int arr6[] = {2, 4, 6};\n\n int expected3[] = {1, 2, 3, 4, 6, 7};\n\n int* result3 = func0(arr5, 3, arr6, 3);\n\n for (int i = 0; i < 6; i++) assert(result3[i] == expected3[i]);\n\n\n\n // Free allocated memory\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0; \n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\nmov %rdi,%r13\nlea (%rsi,%rcx,1),%edi\npush %r12\nmovslq %edi,%rdi\nmov %rdx,%r12\npush %rbp\nshl $0x2,%rdi\nmov %ecx,%ebp\npush %rbx\nmov %esi,%ebx\nsub $0x8,%rsp\ncallq 10d0 \ntest %ebx,%ebx\njle 1610 \ntest %ebp,%ebp\njle 1610 \nmov $0x1,%edi\nxor %esi,%esi\nxor %r8d,%r8d\njmp 157e \nnopl 0x0(%rax,%rax,1)\nadd $0x1,%r8d\nmov %r9d,-0x4(%rax,%rdi,4)\nadd $0x1,%rdi\ncmp %ebx,%r8d\njge 15a5 \ncmp %ebp,%esi\njge 15a5 \nmovslq %r8d,%rdx\nmov %edi,%r10d\nmov 0x0(%r13,%rdx,4),%r9d\nmovslq %esi,%rdx\nmov (%r12,%rdx,4),%ecx\ncmp %ecx,%r9d\njl 1568 \nmov %ecx,-0x4(%rax,%rdi,4)\nadd $0x1,%esi\nadd $0x1,%rdi\ncmp %ebx,%r8d\njl 157a \ncmp %r8d,%ebx\njle 15d9 \nmovslq %r8d,%rdi\nmovslq %r10d,%rdx\nsub %rdi,%rdx\nlea (%rax,%rdx,4),%rcx\nnopw 0x0(%rax,%rax,1)\nmov 0x0(%r13,%rdi,4),%edx\nmov %edx,(%rcx,%rdi,4)\nadd $0x1,%rdi\ncmp %edi,%ebx\njg 15c0 \nadd %r10d,%ebx\nsub %r8d,%ebx\nmov %ebx,%r10d\ncmp %esi,%ebp\njle 15ff \nmovslq %esi,%rsi\nmovslq %r10d,%rbx\nsub %rsi,%rbx\nlea (%rax,%rbx,4),%rcx\nnopw 0x0(%rax,%rax,1)\nmov (%r12,%rsi,4),%edx\nmov %edx,(%rcx,%rsi,4)\nadd $0x1,%rsi\ncmp %esi,%ebp\njg 15f0 \nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopw 0x0(%rax,%rax,1)\nxor %r10d,%r10d\nxor %esi,%esi\nxor %r8d,%r8d\njmp 15a5 \nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov r15, rdx\npush r14\npush r13\nmov r13d, esi\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rdi\nlea edi, [rsi+rcx]\nmovsxd rdi, edi\nmov [rsp+48h+var_44], ecx\nshl rdi, 2; size\ncall _malloc\ntest r13d, r13d\nmov r9d, [rsp+48h+var_44]\nmov r8, [rsp+48h+var_40]\nmov r14, rax\njle loc_1598\ntest r9d, r9d\njle loc_1598\nmov edx, 1\nxor ebp, ebp\nxor r12d, r12d\njmp short loc_14FC\nloc_14E0:\nmov eax, ecx\nadd r12d, 1\nmov [r14+rdx*4-4], eax\nlea rax, [rdx+1]\ncmp r12d, r13d\njge short loc_151F\nloc_14F4:\ncmp r9d, ebp\njle short loc_151F\nmov rdx, rax\nloc_14FC:\nmovsxd rax, r12d\nmov ecx, [r8+rax*4]\nmovsxd rax, ebp\nmov eax, [r15+rax*4]\ncmp ecx, eax\njl short loc_14E0\nmov [r14+rdx*4-4], eax\nadd ebp, 1\nlea rax, [rdx+1]\ncmp r12d, r13d\njl short loc_14F4\nloc_151F:\nmov ebx, edx\nloc_1521:\ncmp r13d, r12d\njle short loc_155B\nmovsxd rax, ebx\nmov [rsp+48h+var_44], r9d\nlea rdi, [r14+rax*4]; dest\nlea eax, [r13-1]\nadd r13d, ebx\nsub eax, r12d\nmov ebx, r13d\nlea rdx, ds:4[rax*4]; n\nmovsxd rax, r12d\nsub ebx, r12d\nlea rsi, [r8+rax*4]; src\ncall _memcpy\nmov r9d, [rsp+48h+var_44]\nloc_155B:\ncmp r9d, ebp\njle short loc_1582\nsub r9d, 1\nmovsxd rdx, ebx\nmovsxd rax, ebp\nsub r9d, ebp\nlea rdi, [r14+rdx*4]; dest\nlea rsi, [r15+rax*4]; src\nlea rdx, ds:4[r9*4]; n\ncall _memcpy\nloc_1582:\nadd rsp, 18h\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1598:\nxor ebx, ebx\nxor ebp, ebp\nxor r12d, r12d\njmp short loc_1521", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, __int64 a3, int a4)\n{\n _DWORD *v5; // rax\n int v6; // r9d\n _DWORD *v8; // r14\n __int64 v9; // rdx\n int v10; // ebp\n int v11; // r12d\n __int64 v12; // rax\n int v13; // ecx\n int v14; // eax\n int v15; // ebx\n char *v16; // rdi\n\n v5 = malloc(4LL * (a2 + a4));\n v6 = a4;\n v8 = v5;\n if ( a2 > 0 && a4 > 0 )\n {\n v9 = 1LL;\n v10 = 0;\n v11 = 0;\n while ( 1 )\n {\n v13 = *(_DWORD *)(a1 + 4LL * v11);\n v14 = *(_DWORD *)(a3 + 4LL * v10);\n if ( v13 < v14 )\n {\n ++v11;\n v8[v9 - 1] = v13;\n v12 = v9 + 1;\n if ( v11 >= a2 )\n goto LABEL_9;\n }\n else\n {\n v8[v9 - 1] = v14;\n ++v10;\n v12 = v9 + 1;\n if ( v11 >= a2 )\n {\nLABEL_9:\n v15 = v9;\n goto LABEL_10;\n }\n }\n if ( a4 <= v10 )\n goto LABEL_9;\n v9 = v12;\n }\n }\n v15 = 0;\n v10 = 0;\n v11 = 0;\nLABEL_10:\n if ( a2 > v11 )\n {\n v16 = (char *)&v8[v15];\n v15 = v15 + a2 - v11;\n memcpy(v16, (const void *)(a1 + 4LL * v11), 4LL * (unsigned int)(a2 - 1 - v11) + 4);\n v6 = a4;\n }\n if ( v6 > v10 )\n memcpy(&v8[v15], (const void *)(a3 + 4LL * v10), 4LL * (unsigned int)(v6 - 1 - v10) + 4);\n return v8;\n}", + "ida_strip_asm": "sub_1480:\nendbr64\npush r15\nmov r15, rdx\npush r14\npush r13\nmov r13d, esi\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rdi\nlea edi, [rsi+rcx]\nmovsxd rdi, edi\nmov [rsp+48h+var_44], ecx\nshl rdi, 2; size\ncall _malloc\ntest r13d, r13d\nmov r9d, [rsp+48h+var_44]\nmov r8, [rsp+48h+var_40]\nmov r14, rax\njle loc_1598\ntest r9d, r9d\njle loc_1598\nmov edx, 1\nxor ebp, ebp\nxor r12d, r12d\njmp short loc_14FC\nloc_14E0:\nmov eax, ecx\nadd r12d, 1\nmov [r14+rdx*4-4], eax\nlea rax, [rdx+1]\ncmp r12d, r13d\njge short loc_151F\nloc_14F4:\ncmp r9d, ebp\njle short loc_151F\nmov rdx, rax\nloc_14FC:\nmovsxd rax, r12d\nmov ecx, [r8+rax*4]\nmovsxd rax, ebp\nmov eax, [r15+rax*4]\ncmp ecx, eax\njl short loc_14E0\nmov [r14+rdx*4-4], eax\nadd ebp, 1\nlea rax, [rdx+1]\ncmp r12d, r13d\njl short loc_14F4\nloc_151F:\nmov ebx, edx\nloc_1521:\ncmp r13d, r12d\njle short loc_155B\nmovsxd rax, ebx\nmov [rsp+48h+var_44], r9d\nlea rdi, [r14+rax*4]; dest\nlea eax, [r13-1]\nadd r13d, ebx\nsub eax, r12d\nmov ebx, r13d\nlea rdx, ds:4[rax*4]; n\nmovsxd rax, r12d\nsub ebx, r12d\nlea rsi, [r8+rax*4]; src\ncall _memcpy\nmov r9d, [rsp+48h+var_44]\nloc_155B:\ncmp r9d, ebp\njle short loc_1582\nsub r9d, 1\nmovsxd rdx, ebx\nmovsxd rax, ebp\nsub r9d, ebp\nlea rdi, [r14+rdx*4]; dest\nlea rsi, [r15+rax*4]; src\nlea rdx, ds:4[r9*4]; n\ncall _memcpy\nloc_1582:\nadd rsp, 18h\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1598:\nxor ebx, ebx\nxor ebp, ebp\nxor r12d, r12d\njmp short loc_1521", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1480(__int64 a1, int a2, __int64 a3, int a4)\n{\n _DWORD *v5; // rax\n int v6; // r9d\n _DWORD *v8; // r14\n __int64 v9; // rdx\n int v10; // ebp\n int v11; // r12d\n __int64 v12; // rax\n int v13; // ecx\n int v14; // eax\n int v15; // ebx\n char *v16; // rdi\n\n v5 = malloc(4LL * (a2 + a4));\n v6 = a4;\n v8 = v5;\n if ( a2 > 0 && a4 > 0 )\n {\n v9 = 1LL;\n v10 = 0;\n v11 = 0;\n while ( 1 )\n {\n v13 = *(_DWORD *)(a1 + 4LL * v11);\n v14 = *(_DWORD *)(a3 + 4LL * v10);\n if ( v13 < v14 )\n {\n ++v11;\n v8[v9 - 1] = v13;\n v12 = v9 + 1;\n if ( v11 >= a2 )\n goto LABEL_9;\n }\n else\n {\n v8[v9 - 1] = v14;\n ++v10;\n v12 = v9 + 1;\n if ( v11 >= a2 )\n {\nLABEL_9:\n v15 = v9;\n goto LABEL_10;\n }\n }\n if ( a4 <= v10 )\n goto LABEL_9;\n v9 = v12;\n }\n }\n v15 = 0;\n v10 = 0;\n v11 = 0;\nLABEL_10:\n if ( a2 > v11 )\n {\n v16 = (char *)&v8[v15];\n v15 = v15 + a2 - v11;\n memcpy(v16, (const void *)(a1 + 4LL * v11), 4LL * (unsigned int)(a2 - 1 - v11) + 4);\n v6 = a4;\n }\n if ( v6 > v10 )\n memcpy(&v8[v15], (const void *)(a3 + 4LL * v10), 4LL * (unsigned int)(v6 - 1 - v10) + 4);\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1480(long long a1, int a2, long long a3, int a4) {\n uint32_t *v5;\n int v6;\n uint32_t *v8;\n long long v9;\n int v10;\n int v11;\n long long v12;\n int v13;\n int v14;\n int v15;\n char *v16;\n v5 = malloc(4LL * (a2 + a4));\n v6 = a4;\n v8 = v5;\n if (a2 > 0 && a4 > 0) {\n v9 = 1LL;\n v10 = 0;\n v11 = 0;\n while (1) {\n v13 = *(uint32_t *)(a1 + 4LL * v11);\n v14 = *(uint32_t *)(a3 + 4LL * v10);\n if (v13 < v14) {\n ++v11;\n v8[v9 - 1] = v13;\n v12 = v9 + 1;\n if (v11 >= a2) goto LABEL_9;\n } else {\n v8[v9 - 1] = v14;\n ++v10;\n v12 = v9 + 1;\n if (v11 >= a2) {\n LABEL_9:\n v15 = v9;\n goto LABEL_10;\n }\n }\n if (a4 <= v10) goto LABEL_9;\n v9 = v12;\n }\n }\n v15 = 0;\n v10 = 0;\n v11 = 0;\nLABEL_10:\n if (a2 > v11) {\n v16 = (char *)&v8[v15];\n v15 = v15 + a2 - v11;\n memcpy(v16, (const void *)(a1 + 4LL * v11),\n 4LL * (unsigned int)(a2 - 1 - v11) + 4);\n v6 = a4;\n }\n if (v6 > v10)\n memcpy(&v8[v15], (const void *)(a3 + 4LL * v10),\n 4LL * (unsigned int)(v6 - 1 - v10) + 4);\n return v8;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, long long a3, int a4) {\n uint32_t *v5;\n int v6;\n uint32_t *v8;\n long long v9;\n int v10;\n int v11;\n long long v12;\n int v13;\n int v14;\n int v15;\n char *v16;\n v5 = malloc(4LL * (a2 + a4));\n v6 = a4;\n v8 = v5;\n if (a2 > 0 && a4 > 0) {\n v9 = 1LL;\n v10 = 0;\n v11 = 0;\n while (1) {\n v13 = *(uint32_t *)(a1 + 4LL * v11);\n v14 = *(uint32_t *)(a3 + 4LL * v10);\n if (v13 < v14) {\n ++v11;\n v8[v9 - 1] = v13;\n v12 = v9 + 1;\n if (v11 >= a2) goto LABEL_9;\n } else {\n v8[v9 - 1] = v14;\n ++v10;\n v12 = v9 + 1;\n if (v11 >= a2) {\n LABEL_9:\n v15 = v9;\n goto LABEL_10;\n }\n }\n if (a4 <= v10) goto LABEL_9;\n v9 = v12;\n }\n }\n v15 = 0;\n v10 = 0;\n v11 = 0;\nLABEL_10:\n if (a2 > v11) {\n v16 = (char *)&v8[v15];\n v15 = v15 + a2 - v11;\n memcpy(v16, (const void *)(a1 + 4LL * v11),\n 4LL * (unsigned int)(a2 - 1 - v11) + 4);\n v6 = a4;\n }\n if (v6 > v10)\n memcpy(&v8[v15], (const void *)(a3 + 4LL * v10),\n 4LL * (unsigned int)(v6 - 1 - v10) + 4);\n return v8;\n}" + }, + { + "index": 943, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int *func0(int *num1, int size1, int *num2, int size2) {\n int *result = (int *)malloc((size1 + size2) * sizeof(int));\n int i = 0, j = 0, k = 0;\n while (i < size1 && j < size2) {\n if (num1[i] < num2[j]) {\n result[k++] = num1[i++];\n } else {\n result[k++] = num2[j++];\n }\n }\n while (i < size1) {\n result[k++] = num1[i++];\n }\n while (j < size2) {\n result[k++] = num2[j++];\n }\n return result;\n}", + "test": "int main() {\n\n int arr1[] = {1, 3, 5, 7, 9, 11};\n\n int arr2[] = {0, 2, 4, 6, 8, 10};\n\n int expected1[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11};\n\n int* result1 = func0(arr1, 6, arr2, 6);\n\n for (int i = 0; i < 12; i++) assert(result1[i] == expected1[i]);\n\n\n\n int arr3[] = {1, 3, 5, 6, 8, 9};\n\n int arr4[] = {2, 5, 7, 11};\n\n int expected2[] = {1, 2, 3, 5, 5, 6, 7, 8, 9, 11};\n\n int* result2 = func0(arr3, 6, arr4, 4);\n\n for (int i = 0; i < 10; i++) assert(result2[i] == expected2[i]);\n\n\n\n int arr5[] = {1, 3, 7};\n\n int arr6[] = {2, 4, 6};\n\n int expected3[] = {1, 2, 3, 4, 6, 7};\n\n int* result3 = func0(arr5, 3, arr6, 3);\n\n for (int i = 0; i < 6; i++) assert(result3[i] == expected3[i]);\n\n\n\n // Free allocated memory\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n printf(\"All tests passed!\\n\");\n\n return 0; \n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmov %esi,%r15d\npush %r14\npush %r13\nmov %rdx,%r13\npush %r12\nmov %ecx,%r12d\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov %rdi,0x8(%rsp)\nlea (%rsi,%rcx,1),%edi\nmovslq %edi,%rdi\nshl $0x2,%rdi\ncallq 10f0 \ntest %r15d,%r15d\nmov 0x8(%rsp),%r8\nmov %rax,%r14\njle 1688 \ntest %r12d,%r12d\njle 1688 \nmov $0x1,%eax\nxor %ebx,%ebx\nxor %ebp,%ebp\nxor %r9d,%r9d\nxor %edi,%edi\nmov (%r8,%r9,4),%esi\nmov 0x0(%r13,%rdi,4),%edx\nmov %eax,%ecx\ncmp %edx,%esi\njge 1667 \nadd $0x1,%ebp\nmov %esi,-0x4(%r14,%rax,4)\nadd $0x1,%rax\ncmp %r15d,%ebp\njge 1690 \ncmp %ebx,%r12d\njle 1690 \nmovslq %ebp,%r9\nmov 0x0(%r13,%rdi,4),%edx\nmov %eax,%ecx\nmov (%r8,%r9,4),%esi\ncmp %edx,%esi\njl 163f \nadd $0x1,%ebx\nmov %edx,-0x4(%r14,%rax,4)\nadd $0x1,%rax\ncmp %r12d,%ebx\njge 1690 \ncmp %ebp,%r15d\njle 16c6 \nmovslq %ebx,%rdi\njmp 1630 \nnopw 0x0(%rax,%rax,1)\nxor %ecx,%ecx\nxor %ebx,%ebx\nxor %ebp,%ebp\nxchg %ax,%ax\ncmp %ebp,%r15d\njle 16c6 \nmovslq %ecx,%rax\nmov %ecx,0x8(%rsp)\nlea (%r14,%rax,4),%rdi\nlea -0x1(%r15),%eax\nsub %ebp,%eax\nlea 0x4(,%rax,4),%rdx\nmovslq %ebp,%rax\nlea (%r8,%rax,4),%rsi\ncallq 10e0 \nmov 0x8(%rsp),%ecx\nadd %ecx,%r15d\nmov %r15d,%ecx\nsub %ebp,%ecx\ncmp %ebx,%r12d\njle 16ee \nsub $0x1,%r12d\nmovslq %ecx,%r15\nsub %ebx,%r12d\nmovslq %ebx,%rbx\nlea (%r14,%r15,4),%rdi\nlea 0x4(,%r12,4),%rdx\nlea 0x0(%r13,%rbx,4),%rsi\ncallq 10e0 \nadd $0x18,%rsp\nmov %r14,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\nmov r15d, esi\npush r14\npush r13\nmov r13, rdx\npush r12\nmov r12d, ecx\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rdi\nlea edi, [rsi+rcx]\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\ntest r15d, r15d\nmov r8, [rsp+48h+var_40]\nmov r14, rax\njle short loc_1558\ntest r12d, r12d\njle short loc_1558\nmov eax, 1\nxor ebx, ebx\nxor ebp, ebp\nxor edi, edi\nxor esi, esi\nxchg ax, ax\nloc_1500:\nmov ecx, [r8+rdi*4]\nmov edx, [r13+rsi*4+0]\nmovsxd r9, eax\ncmp ecx, edx\njge short loc_1539\nloc_1510:\nadd ebp, 1\nmov [r14+rax*4-4], ecx\nadd rax, 1\ncmp ebp, r15d\njge short loc_1560\ncmp r12d, ebx\njle short loc_1560\nmovsxd rdi, ebp\nmov edx, [r13+rsi*4+0]\nmovsxd r9, eax\nmov ecx, [r8+rdi*4]\ncmp ecx, edx\njl short loc_1510\nloc_1539:\nadd ebx, 1\nmov [r14+rax*4-4], edx\nadd rax, 1\ncmp ebx, r12d\njge short loc_1560\ncmp r15d, ebp\njle short loc_1599\nmovsxd rsi, ebx\njmp short loc_1500\nloc_1558:\nxor r9d, r9d\nxor ebx, ebx\nxor ebp, ebp\nnop\nloc_1560:\ncmp r15d, ebp\njle short loc_1599\nmovsxd rax, r9d\nmov dword ptr [rsp+48h+var_40], r9d\nlea rdi, [r14+rax*4]; dest\nlea eax, [r15-1]\nsub eax, ebp\nlea rdx, ds:4[rax*4]; n\nmovsxd rax, ebp\nlea rsi, [r8+rax*4]; src\ncall _memcpy\nmov r9d, dword ptr [rsp+48h+var_40]\nadd r15d, r9d\nsub r15d, ebp\nmovsxd r9, r15d\nloc_1599:\ncmp r12d, ebx\njle short loc_15BE\nsub r12d, 1\nlea rdi, [r14+r9*4]; dest\nsub r12d, ebx\nmovsxd rbx, ebx\nlea rdx, ds:4[r12*4]; n\nlea rsi, [r13+rbx*4+0]; src\ncall _memcpy\nloc_15BE:\nadd rsp, 18h\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2, __int64 a3, int a4)\n{\n _DWORD *v7; // rax\n _DWORD *v9; // r14\n __int64 v10; // rax\n int v11; // ebx\n int v12; // ebp\n __int64 v13; // rdi\n __int64 i; // rsi\n int v15; // ecx\n int v16; // edx\n __int64 v17; // r9\n int v19; // [rsp+8h] [rbp-40h]\n\n v7 = malloc(4LL * (a2 + a4));\n v9 = v7;\n if ( a2 <= 0 || a4 <= 0 )\n {\n v17 = 0LL;\n v11 = 0;\n v12 = 0;\n }\n else\n {\n v10 = 1LL;\n v11 = 0;\n v12 = 0;\n v13 = 0LL;\n for ( i = 0LL; ; i = v11 )\n {\n v15 = *(_DWORD *)(a1 + 4 * v13);\n v16 = *(_DWORD *)(a3 + 4 * i);\n v17 = (int)v10;\n if ( v15 < v16 )\n break;\nLABEL_8:\n ++v11;\n v9[v10++ - 1] = v16;\n if ( v11 >= a4 )\n goto LABEL_12;\n if ( a2 <= v12 )\n goto LABEL_14;\n }\n while ( 1 )\n {\n ++v12;\n v9[v10++ - 1] = v15;\n if ( v12 >= a2 || a4 <= v11 )\n break;\n v13 = v12;\n v16 = *(_DWORD *)(a3 + 4 * i);\n v17 = (int)v10;\n v15 = *(_DWORD *)(a1 + 4LL * v12);\n if ( v15 >= v16 )\n goto LABEL_8;\n }\n }\nLABEL_12:\n if ( a2 > v12 )\n {\n v19 = v17;\n memcpy(&v9[(int)v17], (const void *)(a1 + 4LL * v12), 4LL * (unsigned int)(a2 - 1 - v12) + 4);\n v17 = v19 + a2 - v12;\n }\nLABEL_14:\n if ( a4 > v11 )\n memcpy(&v9[v17], (const void *)(a3 + 4LL * v11), 4LL * (unsigned int)(a4 - 1 - v11) + 4);\n return v9;\n}", + "ida_strip_asm": "sub_14B0:\nendbr64\npush r15\nmov r15d, esi\npush r14\npush r13\nmov r13, rdx\npush r12\nmov r12d, ecx\npush rbp\npush rbx\nsub rsp, 18h\nmov [rsp+48h+var_40], rdi\nlea edi, [rsi+rcx]\nmovsxd rdi, edi\nshl rdi, 2; size\ncall _malloc\ntest r15d, r15d\nmov r8, [rsp+48h+var_40]\nmov r14, rax\njle short loc_1558\ntest r12d, r12d\njle short loc_1558\nmov eax, 1\nxor ebx, ebx\nxor ebp, ebp\nxor edi, edi\nxor esi, esi\nxchg ax, ax\nloc_1500:\nmov ecx, [r8+rdi*4]\nmov edx, [r13+rsi*4+0]\nmovsxd r9, eax\ncmp ecx, edx\njge short loc_1539\nloc_1510:\nadd ebp, 1\nmov [r14+rax*4-4], ecx\nadd rax, 1\ncmp ebp, r15d\njge short loc_1560\ncmp r12d, ebx\njle short loc_1560\nmovsxd rdi, ebp\nmov edx, [r13+rsi*4+0]\nmovsxd r9, eax\nmov ecx, [r8+rdi*4]\ncmp ecx, edx\njl short loc_1510\nloc_1539:\nadd ebx, 1\nmov [r14+rax*4-4], edx\nadd rax, 1\ncmp ebx, r12d\njge short loc_1560\ncmp r15d, ebp\njle short loc_1599\nmovsxd rsi, ebx\njmp short loc_1500\nloc_1558:\nxor r9d, r9d\nxor ebx, ebx\nxor ebp, ebp\nnop\nloc_1560:\ncmp r15d, ebp\njle short loc_1599\nmovsxd rax, r9d\nmov dword ptr [rsp+48h+var_40], r9d\nlea rdi, [r14+rax*4]; dest\nlea eax, [r15-1]\nsub eax, ebp\nlea rdx, ds:4[rax*4]; n\nmovsxd rax, ebp\nlea rsi, [r8+rax*4]; src\ncall _memcpy\nmov r9d, dword ptr [rsp+48h+var_40]\nadd r15d, r9d\nsub r15d, ebp\nmovsxd r9, r15d\nloc_1599:\ncmp r12d, ebx\njle short loc_15BE\nsub r12d, 1\nlea rdi, [r14+r9*4]; dest\nsub r12d, ebx\nmovsxd rbx, ebx\nlea rdx, ds:4[r12*4]; n\nlea rsi, [r13+rbx*4+0]; src\ncall _memcpy\nloc_15BE:\nadd rsp, 18h\nmov rax, r14\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_14B0(__int64 a1, int a2, __int64 a3, int a4)\n{\n _DWORD *v7; // rax\n _DWORD *v9; // r14\n __int64 v10; // rax\n int v11; // ebx\n int v12; // ebp\n __int64 v13; // rdi\n __int64 i; // rsi\n int v15; // ecx\n int v16; // edx\n __int64 v17; // r9\n int v19; // [rsp+8h] [rbp-40h]\n\n v7 = malloc(4LL * (a2 + a4));\n v9 = v7;\n if ( a2 <= 0 || a4 <= 0 )\n {\n v17 = 0LL;\n v11 = 0;\n v12 = 0;\n }\n else\n {\n v10 = 1LL;\n v11 = 0;\n v12 = 0;\n v13 = 0LL;\n for ( i = 0LL; ; i = v11 )\n {\n v15 = *(_DWORD *)(a1 + 4 * v13);\n v16 = *(_DWORD *)(a3 + 4 * i);\n v17 = (int)v10;\n if ( v15 < v16 )\n break;\nLABEL_8:\n ++v11;\n v9[v10++ - 1] = v16;\n if ( v11 >= a4 )\n goto LABEL_12;\n if ( a2 <= v12 )\n goto LABEL_14;\n }\n while ( 1 )\n {\n ++v12;\n v9[v10++ - 1] = v15;\n if ( v12 >= a2 || a4 <= v11 )\n break;\n v13 = v12;\n v16 = *(_DWORD *)(a3 + 4 * i);\n v17 = (int)v10;\n v15 = *(_DWORD *)(a1 + 4LL * v12);\n if ( v15 >= v16 )\n goto LABEL_8;\n }\n }\nLABEL_12:\n if ( a2 > v12 )\n {\n v19 = v17;\n memcpy(&v9[(int)v17], (const void *)(a1 + 4LL * v12), 4LL * (unsigned int)(a2 - 1 - v12) + 4);\n v17 = v19 + a2 - v12;\n }\nLABEL_14:\n if ( a4 > v11 )\n memcpy(&v9[v17], (const void *)(a3 + 4LL * v11), 4LL * (unsigned int)(a4 - 1 - v11) + 4);\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_14B0(long long a1, int a2, long long a3, int a4) {\n uint32_t *v7;\n uint32_t *v9;\n long long v10;\n int v11;\n int v12;\n long long v13;\n long long i;\n int v15;\n int v16;\n long long v17;\n int v19;\n v7 = malloc(4LL * (a2 + a4));\n v9 = v7;\n if (a2 <= 0 || a4 <= 0) {\n v17 = 0LL;\n v11 = 0;\n v12 = 0;\n } else {\n v10 = 1LL;\n v11 = 0;\n v12 = 0;\n v13 = 0LL;\n for (i = 0LL;; i = v11) {\n v15 = *(uint32_t *)(a1 + 4 * v13);\n v16 = *(uint32_t *)(a3 + 4 * i);\n v17 = (int)v10;\n if (v15 < v16) break;\n LABEL_8:\n ++v11;\n v9[v10++ - 1] = v16;\n if (v11 >= a4) goto LABEL_12;\n if (a2 <= v12) goto LABEL_14;\n }\n while (1) {\n ++v12;\n v9[v10++ - 1] = v15;\n if (v12 >= a2 || a4 <= v11) break;\n v13 = v12;\n v16 = *(uint32_t *)(a3 + 4 * i);\n v17 = (int)v10;\n v15 = *(uint32_t *)(a1 + 4LL * v12);\n if (v15 >= v16) goto LABEL_8;\n }\n }\nLABEL_12:\n if (a2 > v12) {\n v19 = v17;\n memcpy(&v9[(int)v17], (const void *)(a1 + 4LL * v12),\n 4LL * (unsigned int)(a2 - 1 - v12) + 4);\n v17 = v19 + a2 - v12;\n }\nLABEL_14:\n if (a4 > v11)\n memcpy(&v9[v17], (const void *)(a3 + 4LL * v11),\n 4LL * (unsigned int)(a4 - 1 - v11) + 4);\n return v9;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2, long long a3, int a4) {\n uint32_t *v7;\n uint32_t *v9;\n long long v10;\n int v11;\n int v12;\n long long v13;\n long long i;\n int v15;\n int v16;\n long long v17;\n int v19;\n v7 = malloc(4LL * (a2 + a4));\n v9 = v7;\n if (a2 <= 0 || a4 <= 0) {\n v17 = 0LL;\n v11 = 0;\n v12 = 0;\n } else {\n v10 = 1LL;\n v11 = 0;\n v12 = 0;\n v13 = 0LL;\n for (i = 0LL;; i = v11) {\n v15 = *(uint32_t *)(a1 + 4 * v13);\n v16 = *(uint32_t *)(a3 + 4 * i);\n v17 = (int)v10;\n if (v15 < v16) break;\n LABEL_8:\n ++v11;\n v9[v10++ - 1] = v16;\n if (v11 >= a4) goto LABEL_12;\n if (a2 <= v12) goto LABEL_14;\n }\n while (1) {\n ++v12;\n v9[v10++ - 1] = v15;\n if (v12 >= a2 || a4 <= v11) break;\n v13 = v12;\n v16 = *(uint32_t *)(a3 + 4 * i);\n v17 = (int)v10;\n v15 = *(uint32_t *)(a1 + 4LL * v12);\n if (v15 >= v16) goto LABEL_8;\n }\n }\nLABEL_12:\n if (a2 > v12) {\n v19 = v17;\n memcpy(&v9[(int)v17], (const void *)(a1 + 4LL * v12),\n 4LL * (unsigned int)(a2 - 1 - v12) + 4);\n v17 = v19 + a2 - v12;\n }\nLABEL_14:\n if (a4 > v11)\n memcpy(&v9[v17], (const void *)(a3 + 4LL * v11),\n 4LL * (unsigned int)(a4 - 1 - v11) + 4);\n return v9;\n}" + }, + { + "index": 944, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *text) {\n for (int i = 0; text[i] != '\\0'; i++) {\n if (isdigit(text[i])) {\n return i;\n }\n }\n return -1;\n}", + "test": "int main() {\n\n assert(func0(\"there are 70 flats in this apartment\") == 10);\n\n assert(func0(\"every adult have 32 teeth\") == 17);\n\n assert(func0(\"isha has 79 chocolates in her bag\") == 9);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11bc \ncallq 1070 <__ctype_b_loc@plt>\nmov (%rax),%rax\nmov -0x4(%rbp),%edx\nmovslq %edx,%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rdx),%edx\nmovsbq %dl,%rdx\nadd %rdx,%rdx\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x800,%eax\ntest %eax,%eax\nje 11b8 \nmov -0x4(%rbp),%eax\njmp 11d5 \naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 1182 \nmov $0xffffffff,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_4], 0\njmp short loc_11BC\nloc_1182:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_4]\nmovsxd rcx, edx\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 800h\ntest eax, eax\njz short loc_11B8\nmov eax, [rbp+var_4]\njmp short locret_11D5\nloc_11B8:\nadd [rbp+var_4], 1\nloc_11BC:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1182\nmov eax, 0FFFFFFFFh\nlocret_11D5:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1)\n{\n unsigned int i; // [rsp+1Ch] [rbp-4h]\n\n for ( i = 0; *(_BYTE *)((int)i + a1); ++i )\n {\n if ( ((*__ctype_b_loc())[*(char *)((int)i + a1)] & 0x800) != 0 )\n return i;\n }\n return 0xFFFFFFFFLL;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_4], 0\njmp short loc_11BC\nloc_1182:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_4]\nmovsxd rcx, edx\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 800h\ntest eax, eax\njz short loc_11B8\nmov eax, [rbp+var_4]\njmp short locret_11D5\nloc_11B8:\nadd [rbp+var_4], 1\nloc_11BC:\nmov eax, [rbp+var_4]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_1182\nmov eax, 0FFFFFFFFh\nlocret_11D5:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1)\n{\n unsigned int i; // [rsp+1Ch] [rbp-4h]\n\n for ( i = 0; *(_BYTE *)((int)i + a1); ++i )\n {\n if ( ((*__ctype_b_loc())[*(char *)((int)i + a1)] & 0x800) != 0 )\n return i;\n }\n return 0xFFFFFFFFLL;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1) {\n unsigned int i;\n for (i = 0; *(uint8_t *)((int)i + a1); ++i) {\n if (((*__ctype_b_loc())[*(char *)((int)i + a1)] & 2048) != 0) return i;\n }\n return 4294967295LL;\n}", + "ida_pseudo_norm": "long long func0(long long a1) {\n unsigned int i;\n for (i = 0; *(uint8_t *)((int)i + a1); ++i) {\n if (((*__ctype_b_loc())[*(char *)((int)i + a1)] & 2048) != 0) return i;\n }\n return 4294967295LL;\n}" + }, + { + "index": 944, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *text) {\n for (int i = 0; text[i] != '\\0'; i++) {\n if (isdigit(text[i])) {\n return i;\n }\n }\n return -1;\n}", + "test": "int main() {\n\n assert(func0(\"there are 70 flats in this apartment\") == 10);\n\n assert(func0(\"every adult have 32 teeth\") == 17);\n\n assert(func0(\"isha has 79 chocolates in her bag\") == 9);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmovzbl (%rdi),%ebx\ntest %bl,%bl\nje 11b2 \nmov %rdi,%rbp\ncallq 1070 <__ctype_b_loc@plt>\nmov (%rax),%rcx\nmov $0x0,%eax\nmov %eax,%edx\nmovsbq %bl,%rbx\ntestb $0x8,0x1(%rcx,%rbx,2)\njne 11a9 \nadd $0x1,%rax\nmovzbl 0x0(%rbp,%rax,1),%ebx\ntest %bl,%bl\njne 118a \nmov $0xffffffff,%edx\nmov %edx,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\nmov $0xffffffff,%edx\njmp 11a9 \n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_11AE\nmov rbp, rdi\ncall ___ctype_b_loc\nmov rdx, [rax]\nmov eax, 0\nloc_118A:\nmovsx rbx, bl\ntest byte ptr [rdx+rbx*2+1], 8\njnz short loc_11A7\nadd rax, 1\nmovzx ebx, byte ptr [rbp+rax+0]\ntest bl, bl\njnz short loc_118A\nmov eax, 0FFFFFFFFh\nloc_11A7:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_11AE:\nmov eax, 0FFFFFFFFh\njmp short loc_11A7", + "ida_pseudo": "__int64 __fastcall func0(char *a1)\n{\n char v1; // bl\n const unsigned __int16 *v2; // rdx\n __int64 result; // rax\n\n v1 = *a1;\n if ( !*a1 )\n return 0xFFFFFFFFLL;\n v2 = *__ctype_b_loc();\n result = 0LL;\n while ( (v2[v1] & 0x800) == 0 )\n {\n v1 = a1[++result];\n if ( !v1 )\n return 0xFFFFFFFFLL;\n }\n return result;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmovzx ebx, byte ptr [rdi]\ntest bl, bl\njz short loc_11AE\nmov rbp, rdi\ncall ___ctype_b_loc\nmov rdx, [rax]\nmov eax, 0\nloc_118A:\nmovsx rbx, bl\ntest byte ptr [rdx+rbx*2+1], 8\njnz short loc_11A7\nadd rax, 1\nmovzx ebx, byte ptr [rbp+rax+0]\ntest bl, bl\njnz short loc_118A\nmov eax, 0FFFFFFFFh\nloc_11A7:\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_11AE:\nmov eax, 0FFFFFFFFh\njmp short loc_11A7", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(char *a1)\n{\n char v1; // bl\n const unsigned __int16 *v2; // rdx\n __int64 result; // rax\n\n v1 = *a1;\n if ( !*a1 )\n return 0xFFFFFFFFLL;\n v2 = *__ctype_b_loc();\n result = 0LL;\n while ( (v2[v1] & 0x800) == 0 )\n {\n v1 = a1[++result];\n if ( !v1 )\n return 0xFFFFFFFFLL;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(char *a1) {\n char v1;\n const unsigned short *v2;\n long long result;\n v1 = *a1;\n if (!*a1) return 4294967295LL;\n v2 = *__ctype_b_loc();\n result = 0LL;\n while ((v2[v1] & 2048) == 0) {\n v1 = a1[++result];\n if (!v1) return 4294967295LL;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(char *a1) {\n char v1;\n const unsigned short *v2;\n long long result;\n v1 = *a1;\n if (!*a1) return 4294967295LL;\n v2 = *__ctype_b_loc();\n result = 0LL;\n while ((v2[v1] & 2048) == 0) {\n v1 = a1[++result];\n if (!v1) return 4294967295LL;\n }\n return result;\n}" + }, + { + "index": 944, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *text) {\n for (int i = 0; text[i] != '\\0'; i++) {\n if (isdigit(text[i])) {\n return i;\n }\n }\n return -1;\n}", + "test": "int main() {\n\n assert(func0(\"there are 70 flats in this apartment\") == 10);\n\n assert(func0(\"every adult have 32 teeth\") == 17);\n\n assert(func0(\"isha has 79 chocolates in her bag\") == 9);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmovsbq (%rdi),%rbx\ntest %bl,%bl\nje 1260 \nmov %rdi,%rbp\ncallq 1070 <__ctype_b_loc@plt>\nmov (%rax),%rdx\nxor %eax,%eax\njmp 1246 \nnopl 0x0(%rax)\nadd $0x1,%rax\nmovsbq 0x0(%rbp,%rax,1),%rbx\ntest %bl,%bl\nje 1260 \nmov %eax,%r8d\ntestb $0x8,0x1(%rdx,%rbx,2)\nje 1238 \nadd $0x8,%rsp\nmov %r8d,%eax\npop %rbx\npop %rbp\nretq\nnopw 0x0(%rax,%rax,1)\nadd $0x8,%rsp\nmov $0xffffffff,%r8d\nmov %r8d,%eax\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmovsx rbx, byte ptr [rdi]\ntest bl, bl\njz short loc_1258\nmov rbp, rdi\ncall ___ctype_b_loc\nmov rdx, [rax]\nxor eax, eax\njmp short loc_1246\nloc_1238:\nadd rax, 1\nmovsx rbx, byte ptr [rbp+rax+0]\ntest bl, bl\njz short loc_1258\nloc_1246:\ntest byte ptr [rdx+rbx*2+1], 8\njz short loc_1238\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1258:\nadd rsp, 8\nmov eax, 0FFFFFFFFh\npop rbx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(char *a1)\n{\n __int64 v1; // rbx\n const unsigned __int16 *v2; // rdx\n __int64 result; // rax\n\n v1 = *a1;\n if ( !(_BYTE)v1 )\n return 0xFFFFFFFFLL;\n v2 = *__ctype_b_loc();\n result = 0LL;\n while ( (v2[v1] & 0x800) == 0 )\n {\n v1 = a1[++result];\n if ( !(_BYTE)v1 )\n return 0xFFFFFFFFLL;\n }\n return result;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmovsx rbx, byte ptr [rdi]\ntest bl, bl\njz short loc_1258\nmov rbp, rdi\ncall ___ctype_b_loc\nmov rdx, [rax]\nxor eax, eax\njmp short loc_1246\nloc_1238:\nadd rax, 1\nmovsx rbx, byte ptr [rbp+rax+0]\ntest bl, bl\njz short loc_1258\nloc_1246:\ntest byte ptr [rdx+rbx*2+1], 8\njz short loc_1238\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1258:\nadd rsp, 8\nmov eax, 0FFFFFFFFh\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(char *a1)\n{\n __int64 v1; // rbx\n const unsigned __int16 *v2; // rdx\n __int64 result; // rax\n\n v1 = *a1;\n if ( !(_BYTE)v1 )\n return 0xFFFFFFFFLL;\n v2 = *__ctype_b_loc();\n result = 0LL;\n while ( (v2[v1] & 0x800) == 0 )\n {\n v1 = a1[++result];\n if ( !(_BYTE)v1 )\n return 0xFFFFFFFFLL;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(char *a1) {\n long long v1;\n const unsigned short *v2;\n long long result;\n v1 = *a1;\n if (!(uint8_t)v1) return 4294967295LL;\n v2 = *__ctype_b_loc();\n result = 0LL;\n while ((v2[v1] & 2048) == 0) {\n v1 = a1[++result];\n if (!(uint8_t)v1) return 4294967295LL;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(char *a1) {\n long long v1;\n const unsigned short *v2;\n long long result;\n v1 = *a1;\n if (!(uint8_t)v1) return 4294967295LL;\n v2 = *__ctype_b_loc();\n result = 0LL;\n while ((v2[v1] & 2048) == 0) {\n v1 = a1[++result];\n if (!(uint8_t)v1) return 4294967295LL;\n }\n return result;\n}" + }, + { + "index": 944, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(const char *text) {\n for (int i = 0; text[i] != '\\0'; i++) {\n if (isdigit(text[i])) {\n return i;\n }\n }\n return -1;\n}", + "test": "int main() {\n\n assert(func0(\"there are 70 flats in this apartment\") == 10);\n\n assert(func0(\"every adult have 32 teeth\") == 17);\n\n assert(func0(\"isha has 79 chocolates in her bag\") == 9);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmovsbq (%rdi),%rbx\ntest %bl,%bl\nje 1260 \nmov %rdi,%rbp\ncallq 1070 <__ctype_b_loc@plt>\nmov (%rax),%rdx\nxor %eax,%eax\njmp 1246 \nnopl 0x0(%rax)\nadd $0x1,%rax\nmovsbq 0x0(%rbp,%rax,1),%rbx\ntest %bl,%bl\nje 1260 \nmov %eax,%r8d\ntestb $0x8,0x1(%rdx,%rbx,2)\nje 1238 \nadd $0x8,%rsp\nmov %r8d,%eax\npop %rbx\npop %rbp\nretq\nnopw 0x0(%rax,%rax,1)\nadd $0x8,%rsp\nmov $0xffffffff,%r8d\nmov %r8d,%eax\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmovsx rbx, byte ptr [rdi]\ntest bl, bl\njz short loc_1258\nmov rbp, rdi\ncall ___ctype_b_loc\nmov rdx, [rax]\nxor eax, eax\njmp short loc_1246\nloc_1238:\nadd rax, 1\nmovsx rbx, byte ptr [rbp+rax+0]\ntest bl, bl\njz short loc_1258\nloc_1246:\ntest byte ptr [rdx+rbx*2+1], 8\njz short loc_1238\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1258:\nadd rsp, 8\nmov eax, 0FFFFFFFFh\npop rbx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(char *a1)\n{\n __int64 v1; // rbx\n const unsigned __int16 *v2; // rdx\n __int64 result; // rax\n\n v1 = *a1;\n if ( !(_BYTE)v1 )\n return 0xFFFFFFFFLL;\n v2 = *__ctype_b_loc();\n result = 0LL;\n while ( (v2[v1] & 0x800) == 0 )\n {\n v1 = a1[++result];\n if ( !(_BYTE)v1 )\n return 0xFFFFFFFFLL;\n }\n return result;\n}", + "ida_strip_asm": "sub_1210:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmovsx rbx, byte ptr [rdi]\ntest bl, bl\njz short loc_1258\nmov rbp, rdi\ncall ___ctype_b_loc\nmov rdx, [rax]\nxor eax, eax\njmp short loc_1246\nloc_1238:\nadd rax, 1\nmovsx rbx, byte ptr [rbp+rax+0]\ntest bl, bl\njz short loc_1258\nloc_1246:\ntest byte ptr [rdx+rbx*2+1], 8\njz short loc_1238\nadd rsp, 8\npop rbx\npop rbp\nretn\nloc_1258:\nadd rsp, 8\nmov eax, 0FFFFFFFFh\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1210(char *a1)\n{\n __int64 v1; // rbx\n const unsigned __int16 *v2; // rdx\n __int64 result; // rax\n\n v1 = *a1;\n if ( !(_BYTE)v1 )\n return 0xFFFFFFFFLL;\n v2 = *__ctype_b_loc();\n result = 0LL;\n while ( (v2[v1] & 0x800) == 0 )\n {\n v1 = a1[++result];\n if ( !(_BYTE)v1 )\n return 0xFFFFFFFFLL;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1210(char *a1) {\n long long v1;\n const unsigned short *v2;\n long long result;\n v1 = *a1;\n if (!(uint8_t)v1) return 4294967295LL;\n v2 = *__ctype_b_loc();\n result = 0LL;\n while ((v2[v1] & 2048) == 0) {\n v1 = a1[++result];\n if (!(uint8_t)v1) return 4294967295LL;\n }\n return result;\n}", + "ida_pseudo_norm": "long long func0(char *a1) {\n long long v1;\n const unsigned short *v2;\n long long result;\n v1 = *a1;\n if (!(uint8_t)v1) return 4294967295LL;\n v2 = *__ctype_b_loc();\n result = 0LL;\n while ((v2[v1] & 2048) == 0) {\n v1 = a1[++result];\n if (!(uint8_t)v1) return 4294967295LL;\n }\n return result;\n}" + }, + { + "index": 945, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char **elements;\n\n int size;\n\n} Set;\n\n\n\nint set_contains(Set *set, char *element) {\n\n for (int i = 0; i < set->size; i++) {\n\n if (strcmp(set->elements[i], element) == 0)\n\n return 1;\n\n }\n\n return 0;\n\n}\n\n\n\nint sets_are_equal(Set *set1, Set *set2) {\n\n if (set1->size != set2->size) return 0;\n\n for (int i = 0; i < set1->size; i++) {\n\n if (!set_contains(set2, set1->elements[i]))\n\n return 0;\n\n }\n\n return 1;\n\n}\n\n\n\nvoid free_set(Set *s) {\n\n for (int i = 0; i < s->size; i++) {\n\n free(s->elements[i]);\n\n }\n\n free(s->elements);\n\n}\n\n", + "func": "Set func0(char *t[], int size) {\n Set s;\n s.size = size;\n s.elements = malloc(size * sizeof(char *));\n for (int i = 0; i < size; i++) {\n s.elements[i] = strdup(t[i]);\n }\n return s;\n}", + "test": "int main() {\n\n char *test1[] = {\"x\", \"y\", \"z\"};\n\n char *test2[] = {\"a\", \"b\", \"c\"};\n\n char *test3[] = {\"z\", \"d\", \"e\"};\n\n\n\n Set result1 = func0(test1, 3);\n\n Set expected1 = func0((char *[]){\"y\", \"x\", \"z\"}, 3);\n\n \n\n Set result2 = func0(test2, 3);\n\n Set expected2 = func0((char *[]){\"c\", \"a\", \"b\"}, 3);\n\n \n\n Set result3 = func0(test3, 3);\n\n Set expected3 = func0((char *[]){\"d\", \"e\", \"z\"}, 3);\n\n\n\n assert(sets_are_equal(&result1, &expected1));\n\n assert(sets_are_equal(&result2, &expected2));\n\n assert(sets_are_equal(&result3, &expected3));\n\n\n\n free_set(&result1);\n\n free_set(&expected1);\n\n free_set(&result2);\n\n free_set(&expected2);\n\n free_set(&result3);\n\n free_set(&expected3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x38,%rsp\nmov %rdi,-0x38(%rbp)\nmov %esi,-0x3c(%rbp)\nmov -0x3c(%rbp),%eax\nmov %eax,-0x18(%rbp)\nmov -0x3c(%rbp),%eax\ncltq\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 10e0 \nmov %rax,-0x20(%rbp)\nmovl $0x0,-0x24(%rbp)\njmp 1396 \nmov -0x24(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0x20(%rbp),%rdx\nmov -0x24(%rbp),%ecx\nmovslq %ecx,%rcx\nshl $0x3,%rcx\nlea (%rdx,%rcx,1),%rbx\nmov %rax,%rdi\ncallq 10f0 \nmov %rax,(%rbx)\naddl $0x1,-0x24(%rbp)\nmov -0x24(%rbp),%eax\ncmp -0x3c(%rbp),%eax\njl 135e \nmov -0x20(%rbp),%rax\nmov -0x18(%rbp),%rdx\nadd $0x38,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov eax, [rbp+var_3C]\nmov dword ptr [rbp+var_18], eax\nmov eax, [rbp+var_3C]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_20], rax\nmov [rbp+var_24], 0\njmp short loc_1396\nloc_135E:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nmov rdx, [rbp+var_20]\nmov ecx, [rbp+var_24]\nmovsxd rcx, ecx\nshl rcx, 3\nlea rbx, [rdx+rcx]\nmov rdi, rax; s\ncall _strdup\nmov [rbx], rax\nadd [rbp+var_24], 1\nloc_1396:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_3C]\njl short loc_135E\nmov rax, [rbp+var_20]\nmov rdx, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, int a2)\n{\n int i; // [rsp+1Ch] [rbp-24h]\n _QWORD *v4; // [rsp+20h] [rbp-20h]\n\n v4 = malloc(8LL * a2);\n for ( i = 0; i < a2; ++i )\n v4[i] = strdup(*(const char **)(8LL * i + a1));\n return v4;\n}", + "ida_strip_asm": "sub_1326:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov eax, [rbp+var_3C]\nmov dword ptr [rbp+var_18], eax\nmov eax, [rbp+var_3C]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_20], rax\nmov [rbp+var_24], 0\njmp short loc_1396\nloc_135E:\nmov eax, [rbp+var_24]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax]\nmov rdx, [rbp+var_20]\nmov ecx, [rbp+var_24]\nmovsxd rcx, ecx\nshl rcx, 3\nlea rbx, [rdx+rcx]\nmov rdi, rax; s\ncall _strdup\nmov [rbx], rax\nadd [rbp+var_24], 1\nloc_1396:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_3C]\njl short loc_135E\nmov rax, [rbp+var_20]\nmov rdx, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1326(__int64 a1, int a2)\n{\n int i; // [rsp+1Ch] [rbp-24h]\n _QWORD *v4; // [rsp+20h] [rbp-20h]\n\n v4 = malloc(8LL * a2);\n for ( i = 0; i < a2; ++i )\n v4[i] = strdup(*(const char **)(8LL * i + a1));\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1326(long long a1, int a2) {\n int i;\n uint64_t *v4;\n v4 = malloc(8LL * a2);\n for (i = 0; i < a2; ++i) v4[i] = strdup(*(const char **)(8LL * i + a1));\n return v4;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, int a2) {\n int i;\n uint64_t *v4;\n v4 = malloc(8LL * a2);\n for (i = 0; i < a2; ++i) v4[i] = strdup(*(const char **)(8LL * i + a1));\n return v4;\n}" + }, + { + "index": 945, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char **elements;\n\n int size;\n\n} Set;\n\n\n\nint set_contains(Set *set, char *element) {\n\n for (int i = 0; i < set->size; i++) {\n\n if (strcmp(set->elements[i], element) == 0)\n\n return 1;\n\n }\n\n return 0;\n\n}\n\n\n\nint sets_are_equal(Set *set1, Set *set2) {\n\n if (set1->size != set2->size) return 0;\n\n for (int i = 0; i < set1->size; i++) {\n\n if (!set_contains(set2, set1->elements[i]))\n\n return 0;\n\n }\n\n return 1;\n\n}\n\n\n\nvoid free_set(Set *s) {\n\n for (int i = 0; i < s->size; i++) {\n\n free(s->elements[i]);\n\n }\n\n free(s->elements);\n\n}\n\n", + "func": "Set func0(char *t[], int size) {\n Set s;\n s.size = size;\n s.elements = malloc(size * sizeof(char *));\n for (int i = 0; i < size; i++) {\n s.elements[i] = strdup(t[i]);\n }\n return s;\n}", + "test": "int main() {\n\n char *test1[] = {\"x\", \"y\", \"z\"};\n\n char *test2[] = {\"a\", \"b\", \"c\"};\n\n char *test3[] = {\"z\", \"d\", \"e\"};\n\n\n\n Set result1 = func0(test1, 3);\n\n Set expected1 = func0((char *[]){\"y\", \"x\", \"z\"}, 3);\n\n \n\n Set result2 = func0(test2, 3);\n\n Set expected2 = func0((char *[]){\"c\", \"a\", \"b\"}, 3);\n\n \n\n Set result3 = func0(test3, 3);\n\n Set expected3 = func0((char *[]){\"d\", \"e\", \"z\"}, 3);\n\n\n\n assert(sets_are_equal(&result1, &expected1));\n\n assert(sets_are_equal(&result2, &expected2));\n\n assert(sets_are_equal(&result3, &expected3));\n\n\n\n free_set(&result1);\n\n free_set(&expected1);\n\n free_set(&result2);\n\n free_set(&expected2);\n\n free_set(&result3);\n\n free_set(&expected3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%r12\nmov %esi,%r14d\nmovslq %esi,%rdi\nshl $0x3,%rdi\ncallq 10e0 \nmov %rax,%rbp\ntest %r14d,%r14d\njle 130d \nlea -0x1(%r14),%r13d\nmov $0x0,%ebx\nmov (%r12,%rbx,8),%rdi\ncallq 10f0 \nmov %rax,0x0(%rbp,%rbx,8)\nmov %rbx,%rax\nadd $0x1,%rbx\ncmp %r13,%rax\njne 12f3 \nmov %r14d,%edx\nmov %rbp,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12, rdi\nmov r13d, esi\nmovsxd r15, esi\nshl r15, 3\nmov rdi, r15; size\ncall _malloc\nmov r14, rax\ntest r13d, r13d\njle short loc_1312\nmov rbx, r12\nmov rbp, rax\nadd r12, r15\nloc_12F9:\nmov rdi, [rbx]; s\ncall _strdup\nmov [rbp+0], rax\nadd rbx, 8\nadd rbp, 8\ncmp rbx, r12\njnz short loc_12F9\nloc_1312:\nmov edx, r13d\nmov rax, r14\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(const char **a1, int a2)\n{\n _QWORD *v2; // rax\n _QWORD *v3; // r14\n const char **v4; // rbx\n char **v5; // rbp\n\n v2 = malloc(8LL * a2);\n v3 = v2;\n if ( a2 > 0 )\n {\n v4 = a1;\n v5 = (char **)v2;\n do\n *v5++ = strdup(*v4++);\n while ( v4 != &a1[a2] );\n }\n return v3;\n}", + "ida_strip_asm": "sub_12C1:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r12, rdi\nmov r13d, esi\nmovsxd r15, esi\nshl r15, 3\nmov rdi, r15; size\ncall _malloc\nmov r14, rax\ntest r13d, r13d\njle short loc_1312\nmov rbx, r12\nmov rbp, rax\nadd r12, r15\nloc_12F9:\nmov rdi, [rbx]; s\ncall _strdup\nmov [rbp+0], rax\nadd rbx, 8\nadd rbp, 8\ncmp rbx, r12\njnz short loc_12F9\nloc_1312:\nmov edx, r13d\nmov rax, r14\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_12C1(const char **a1, int a2)\n{\n _QWORD *v2; // rax\n _QWORD *v3; // r14\n const char **v4; // rbx\n char **v5; // rbp\n\n v2 = malloc(8LL * a2);\n v3 = v2;\n if ( a2 > 0 )\n {\n v4 = a1;\n v5 = (char **)v2;\n do\n *v5++ = strdup(*v4++);\n while ( v4 != &a1[a2] );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_12C1(const char **a1, int a2) {\n uint64_t *v2;\n uint64_t *v3;\n const char **v4;\n char **v5;\n v2 = malloc(8LL * a2);\n v3 = v2;\n if (a2 > 0) {\n v4 = a1;\n v5 = (char **)v2;\n do\n *v5++ = strdup(*v4++);\n while (v4 != &a1[a2]);\n }\n return v3;\n}", + "ida_pseudo_norm": "uint64_t *func0(const char **a1, int a2) {\n uint64_t *v2;\n uint64_t *v3;\n const char **v4;\n char **v5;\n v2 = malloc(8LL * a2);\n v3 = v2;\n if (a2 > 0) {\n v4 = a1;\n v5 = (char **)v2;\n do\n *v5++ = strdup(*v4++);\n while (v4 != &a1[a2]);\n }\n return v3;\n}" + }, + { + "index": 945, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char **elements;\n\n int size;\n\n} Set;\n\n\n\nint set_contains(Set *set, char *element) {\n\n for (int i = 0; i < set->size; i++) {\n\n if (strcmp(set->elements[i], element) == 0)\n\n return 1;\n\n }\n\n return 0;\n\n}\n\n\n\nint sets_are_equal(Set *set1, Set *set2) {\n\n if (set1->size != set2->size) return 0;\n\n for (int i = 0; i < set1->size; i++) {\n\n if (!set_contains(set2, set1->elements[i]))\n\n return 0;\n\n }\n\n return 1;\n\n}\n\n\n\nvoid free_set(Set *s) {\n\n for (int i = 0; i < s->size; i++) {\n\n free(s->elements[i]);\n\n }\n\n free(s->elements);\n\n}\n\n", + "func": "Set func0(char *t[], int size) {\n Set s;\n s.size = size;\n s.elements = malloc(size * sizeof(char *));\n for (int i = 0; i < size; i++) {\n s.elements[i] = strdup(t[i]);\n }\n return s;\n}", + "test": "int main() {\n\n char *test1[] = {\"x\", \"y\", \"z\"};\n\n char *test2[] = {\"a\", \"b\", \"c\"};\n\n char *test3[] = {\"z\", \"d\", \"e\"};\n\n\n\n Set result1 = func0(test1, 3);\n\n Set expected1 = func0((char *[]){\"y\", \"x\", \"z\"}, 3);\n\n \n\n Set result2 = func0(test2, 3);\n\n Set expected2 = func0((char *[]){\"c\", \"a\", \"b\"}, 3);\n\n \n\n Set result3 = func0(test3, 3);\n\n Set expected3 = func0((char *[]){\"d\", \"e\", \"z\"}, 3);\n\n\n\n assert(sets_are_equal(&result1, &expected1));\n\n assert(sets_are_equal(&result2, &expected2));\n\n assert(sets_are_equal(&result3, &expected3));\n\n\n\n free_set(&result1);\n\n free_set(&expected1);\n\n free_set(&result2);\n\n free_set(&expected2);\n\n free_set(&result3);\n\n free_set(&expected3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\nmov %rdi,%rbp\nmovslq %esi,%rdi\npush %rbx\nmov %rdi,%r14\nshl $0x3,%rdi\ncallq 10e0 \nmov %rax,%r12\ntest %r14d,%r14d\njle 15fa \nlea -0x1(%r14),%r13d\nxor %ebx,%ebx\nnopl 0x0(%rax)\nmov 0x0(%rbp,%rbx,8),%rdi\ncallq 10f0 \nmov %rax,(%r12,%rbx,8)\nmov %rbx,%rax\nadd $0x1,%rbx\ncmp %r13,%rax\njne 15e0 \npop %rbx\nmov %r14d,%edx\npop %rbp\nmov %r12,%rax\npop %r12\npop %r13\npop %r14\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r14\nmovsxd r14, esi\npush r13\npush r12\nmov r12, r14\nshl r14, 3\npush rbp\npush rbx\nmov rbx, rdi\nmov rdi, r14; size\ncall _malloc\nmov r13, rax\ntest r12d, r12d\njle short loc_1679\nmov rbp, rax\nadd r14, rbx\nnop\nloc_1660:\nmov rdi, [rbx]; s\nadd rbx, 8\nadd rbp, 8\ncall _strdup\nmov [rbp-8], rax\ncmp rbx, r14\njnz short loc_1660\nloc_1679:\npop rbx\nmov edx, r12d\npop rbp\nmov rax, r13\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "void *__fastcall func0(const char **a1, int a2)\n{\n const char **v2; // rbx\n void *v3; // rax\n void *v4; // r13\n _QWORD *v5; // rbp\n const char **v6; // r14\n const char *v7; // rdi\n\n v2 = a1;\n v3 = malloc(8LL * a2);\n v4 = v3;\n if ( a2 > 0 )\n {\n v5 = v3;\n v6 = &a1[a2];\n do\n {\n v7 = *v2++;\n *v5++ = strdup(v7);\n }\n while ( v2 != v6 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_1630:\nendbr64\npush r14\nmovsxd r14, esi\npush r13\npush r12\nmov r12, r14\nshl r14, 3\npush rbp\npush rbx\nmov rbx, rdi\nmov rdi, r14; size\ncall _malloc\nmov r13, rax\ntest r12d, r12d\njle short loc_1679\nmov rbp, rax\nadd r14, rbx\nnop\nloc_1660:\nmov rdi, [rbx]; s\nadd rbx, 8\nadd rbp, 8\ncall _strdup\nmov [rbp-8], rax\ncmp rbx, r14\njnz short loc_1660\nloc_1679:\npop rbx\nmov edx, r12d\npop rbp\nmov rax, r13\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "void *__fastcall sub_1630(const char **a1, int a2)\n{\n const char **v2; // rbx\n void *v3; // rax\n void *v4; // r13\n _QWORD *v5; // rbp\n const char **v6; // r14\n const char *v7; // rdi\n\n v2 = a1;\n v3 = malloc(8LL * a2);\n v4 = v3;\n if ( a2 > 0 )\n {\n v5 = v3;\n v6 = &a1[a2];\n do\n {\n v7 = *v2++;\n *v5++ = strdup(v7);\n }\n while ( v2 != v6 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1630(const char **a1, int a2) {\n const char **v2;\n void *v3;\n void *v4;\n uint64_t *v5;\n const char **v6;\n const char *v7;\n v2 = a1;\n v3 = malloc(8LL * a2);\n v4 = v3;\n if (a2 > 0) {\n v5 = v3;\n v6 = &a1[a2];\n do {\n v7 = *v2++;\n *v5++ = strdup(v7);\n } while (v2 != v6);\n }\n return v4;\n}", + "ida_pseudo_norm": "void *func0(const char **a1, int a2) {\n const char **v2;\n void *v3;\n void *v4;\n uint64_t *v5;\n const char **v6;\n const char *v7;\n v2 = a1;\n v3 = malloc(8LL * a2);\n v4 = v3;\n if (a2 > 0) {\n v5 = v3;\n v6 = &a1[a2];\n do {\n v7 = *v2++;\n *v5++ = strdup(v7);\n } while (v2 != v6);\n }\n return v4;\n}" + }, + { + "index": 945, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char **elements;\n\n int size;\n\n} Set;\n\n\n\nint set_contains(Set *set, char *element) {\n\n for (int i = 0; i < set->size; i++) {\n\n if (strcmp(set->elements[i], element) == 0)\n\n return 1;\n\n }\n\n return 0;\n\n}\n\n\n\nint sets_are_equal(Set *set1, Set *set2) {\n\n if (set1->size != set2->size) return 0;\n\n for (int i = 0; i < set1->size; i++) {\n\n if (!set_contains(set2, set1->elements[i]))\n\n return 0;\n\n }\n\n return 1;\n\n}\n\n\n\nvoid free_set(Set *s) {\n\n for (int i = 0; i < s->size; i++) {\n\n free(s->elements[i]);\n\n }\n\n free(s->elements);\n\n}\n\n", + "func": "Set func0(char *t[], int size) {\n Set s;\n s.size = size;\n s.elements = malloc(size * sizeof(char *));\n for (int i = 0; i < size; i++) {\n s.elements[i] = strdup(t[i]);\n }\n return s;\n}", + "test": "int main() {\n\n char *test1[] = {\"x\", \"y\", \"z\"};\n\n char *test2[] = {\"a\", \"b\", \"c\"};\n\n char *test3[] = {\"z\", \"d\", \"e\"};\n\n\n\n Set result1 = func0(test1, 3);\n\n Set expected1 = func0((char *[]){\"y\", \"x\", \"z\"}, 3);\n\n \n\n Set result2 = func0(test2, 3);\n\n Set expected2 = func0((char *[]){\"c\", \"a\", \"b\"}, 3);\n\n \n\n Set result3 = func0(test3, 3);\n\n Set expected3 = func0((char *[]){\"d\", \"e\", \"z\"}, 3);\n\n\n\n assert(sets_are_equal(&result1, &expected1));\n\n assert(sets_are_equal(&result2, &expected2));\n\n assert(sets_are_equal(&result3, &expected3));\n\n\n\n free_set(&result1);\n\n free_set(&expected1);\n\n free_set(&result2);\n\n free_set(&expected2);\n\n free_set(&result3);\n\n free_set(&expected3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\nmov %rdi,%rbp\nmovslq %esi,%rdi\npush %rbx\nmov %rdi,%r14\nshl $0x3,%rdi\ncallq 10e0 \nmov %rax,%r12\ntest %r14d,%r14d\njle 169a \nlea -0x1(%r14),%r13d\nxor %ebx,%ebx\nnopl 0x0(%rax)\nmov 0x0(%rbp,%rbx,8),%rdi\ncallq 10f0 \nmov %rax,(%r12,%rbx,8)\nmov %rbx,%rax\nadd $0x1,%rbx\ncmp %rax,%r13\njne 1680 \npop %rbx\nmov %r14d,%edx\npop %rbp\nmov %r12,%rax\npop %r12\npop %r13\npop %r14\nretq\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r14\nmovsxd r14, esi\npush r13\npush r12\nmov r12, r14\nshl r14, 3\npush rbp\npush rbx\nmov rbx, rdi\nmov rdi, r14; size\ncall _malloc\nmov r13, rax\ntest r12d, r12d\njle short loc_1679\nmov rbp, rax\nadd r14, rbx\nnop\nloc_1660:\nmov rdi, [rbx]; s\nadd rbx, 8\nadd rbp, 8\ncall _strdup\nmov [rbp-8], rax\ncmp rbx, r14\njnz short loc_1660\nloc_1679:\npop rbx\nmov edx, r12d\npop rbp\nmov rax, r13\npop r12\npop r13\npop r14\nretn", + "ida_pseudo": "void *__fastcall func0(const char **a1, int a2)\n{\n const char **v2; // rbx\n void *v3; // rax\n void *v4; // r13\n _QWORD *v5; // rbp\n const char **v6; // r14\n const char *v7; // rdi\n\n v2 = a1;\n v3 = malloc(8LL * a2);\n v4 = v3;\n if ( a2 > 0 )\n {\n v5 = v3;\n v6 = &a1[a2];\n do\n {\n v7 = *v2++;\n *v5++ = strdup(v7);\n }\n while ( v2 != v6 );\n }\n return v4;\n}", + "ida_strip_asm": "sub_1630:\nendbr64\npush r14\nmovsxd r14, esi\npush r13\npush r12\nmov r12, r14\nshl r14, 3\npush rbp\npush rbx\nmov rbx, rdi\nmov rdi, r14; size\ncall _malloc\nmov r13, rax\ntest r12d, r12d\njle short loc_1679\nmov rbp, rax\nadd r14, rbx\nnop\nloc_1660:\nmov rdi, [rbx]; s\nadd rbx, 8\nadd rbp, 8\ncall _strdup\nmov [rbp-8], rax\ncmp rbx, r14\njnz short loc_1660\nloc_1679:\npop rbx\nmov edx, r12d\npop rbp\nmov rax, r13\npop r12\npop r13\npop r14\nretn", + "ida_strip_pseudo": "void *__fastcall sub_1630(const char **a1, int a2)\n{\n const char **v2; // rbx\n void *v3; // rax\n void *v4; // r13\n _QWORD *v5; // rbp\n const char **v6; // r14\n const char *v7; // rdi\n\n v2 = a1;\n v3 = malloc(8LL * a2);\n v4 = v3;\n if ( a2 > 0 )\n {\n v5 = v3;\n v6 = &a1[a2];\n do\n {\n v7 = *v2++;\n *v5++ = strdup(v7);\n }\n while ( v2 != v6 );\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1630(const char **a1, int a2) {\n const char **v2;\n void *v3;\n void *v4;\n uint64_t *v5;\n const char **v6;\n const char *v7;\n v2 = a1;\n v3 = malloc(8LL * a2);\n v4 = v3;\n if (a2 > 0) {\n v5 = v3;\n v6 = &a1[a2];\n do {\n v7 = *v2++;\n *v5++ = strdup(v7);\n } while (v2 != v6);\n }\n return v4;\n}", + "ida_pseudo_norm": "void *func0(const char **a1, int a2) {\n const char **v2;\n void *v3;\n void *v4;\n uint64_t *v5;\n const char **v6;\n const char *v7;\n v2 = a1;\n v3 = malloc(8LL * a2);\n v4 = v3;\n if (a2 > 0) {\n v5 = v3;\n v6 = &a1[a2];\n do {\n v7 = *v2++;\n *v5++ = strdup(v7);\n } while (v2 != v6);\n }\n return v4;\n}" + }, + { + "index": 946, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char character;\n\n int count;\n\n int first_index;\n\n} CharCount;\n\n\n\nint compare(const void* a, const void* b) {\n\n CharCount* cc1 = (CharCount*)a;\n\n CharCount* cc2 = (CharCount*)b;\n\n if (cc2->count != cc1->count)\n\n return cc2->count - cc1->count;\n\n return cc1->first_index - cc2->first_index;\n\n}\n\n\n\n", + "func": "CharCount* func0(const char* s, int a) {\n int counts[256] = {0};\n int first_occurrence[256];\n for (int i = 0; i < 256; i++) first_occurrence[i] = -1;\n for (int i = 0; s[i]; i++) {\n unsigned char c = s[i];\n counts[c]++;\n if (first_occurrence[c] == -1) first_occurrence[c] = i;\n }\n CharCount temp[256];\n int unique = 0;\n for (int i = 0; i < 256; i++) {\n if (counts[i] > 0) {\n temp[unique].character = (char)i;\n temp[unique].count = counts[i];\n temp[unique].first_index = first_occurrence[i];\n unique++;\n }\n }\n qsort(temp, unique, sizeof(CharCount), compare);\n CharCount* result = malloc(a * sizeof(CharCount));\n for (int i = 0; i < a && i < unique; i++) {\n result[i] = temp[i];\n }\n return result;\n}", + "test": "int main() {\n\n CharCount* res1 = func0(\"lkseropewdssafsdfafkpwe\", 3);\n\n assert(res1[0].character == 's' && res1[0].count == 4);\n\n assert(res1[1].character == 'e' && res1[1].count == 3);\n\n assert(res1[2].character == 'f' && res1[2].count == 3);\n\n free(res1);\n\n\n\n CharCount* res2 = func0(\"lkseropewdssafsdfafkpwe\", 2);\n\n assert(res2[0].character == 's' && res2[0].count == 4);\n\n assert(res2[1].character == 'e' && res2[1].count == 3);\n\n free(res2);\n\n\n\n CharCount* res3 = func0(\"lkseropewdssafsdfafkpwe\", 7);\n\n assert(res3[0].character == 's' && res3[0].count == 4);\n\n assert(res3[1].character == 'e' && res3[1].count == 3);\n\n assert(res3[2].character == 'f' && res3[2].count == 3);\n\n assert(res3[3].character == 'k' && res3[3].count == 2);\n\n assert(res3[4].character == 'p' && res3[4].count == 2);\n\n assert(res3[5].character == 'w' && res3[5].count == 2);\n\n assert(res3[6].character == 'd' && res3[6].count == 2);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x1000,%rsp\norq $0x0,(%rsp)\nsub $0x440,%rsp\nmov %rdi,-0x1438(%rbp)\nmov %esi,-0x143c(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea -0x1410(%rbp),%rdx\nmov $0x0,%eax\nmov $0x80,%ecx\nmov %rdx,%rdi\nrep stos %rax,%es:(%rdi)\nmovl $0x0,-0x142c(%rbp)\njmp 1297 \nmov -0x142c(%rbp),%eax\ncltq\nmovl $0xffffffff,-0x1010(%rbp,%rax,4)\naddl $0x1,-0x142c(%rbp)\ncmpl $0xff,-0x142c(%rbp)\njle 127d \nmovl $0x0,-0x1428(%rbp)\njmp 131a \nmov -0x1428(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x1438(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmov %al,-0x142d(%rbp)\nmovzbl -0x142d(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x1410(%rbp,%rdx,4),%edx\nadd $0x1,%edx\ncltq\nmov %edx,-0x1410(%rbp,%rax,4)\nmovzbl -0x142d(%rbp),%eax\ncltq\nmov -0x1010(%rbp,%rax,4),%eax\ncmp $0xffffffff,%eax\njne 1313 \nmovzbl -0x142d(%rbp),%eax\ncltq\nmov -0x1428(%rbp),%edx\nmov %edx,-0x1010(%rbp,%rax,4)\naddl $0x1,-0x1428(%rbp)\nmov -0x1428(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x1438(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 12af \nmovl $0x0,-0x1424(%rbp)\nmovl $0x0,-0x1420(%rbp)\njmpq 13ff \nmov -0x1420(%rbp),%eax\ncltq\nmov -0x1410(%rbp,%rax,4),%eax\ntest %eax,%eax\njle 13f8 \nmov -0x1420(%rbp),%eax\nmov %eax,%ecx\nmov -0x1424(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rbp,%rax\nsub $0xc10,%rax\nmov %cl,(%rax)\nmov -0x1420(%rbp),%eax\ncltq\nmov -0x1410(%rbp,%rax,4),%ecx\nmov -0x1424(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rbp,%rax\nsub $0xc0c,%rax\nmov %ecx,(%rax)\nmov -0x1420(%rbp),%eax\ncltq\nmov -0x1010(%rbp,%rax,4),%ecx\nmov -0x1424(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nadd %rbp,%rax\nsub $0xc08,%rax\nmov %ecx,(%rax)\naddl $0x1,-0x1424(%rbp)\naddl $0x1,-0x1420(%rbp)\ncmpl $0xff,-0x1420(%rbp)\njle 1351 \nmov -0x1424(%rbp),%eax\nmovslq %eax,%rsi\nlea -0xc10(%rbp),%rax\nlea -0x25d(%rip),%rcx\nmov $0xc,%edx\nmov %rax,%rdi\ncallq 10a0 \nmov -0x143c(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,-0x1418(%rbp)\nmovl $0x0,-0x141c(%rbp)\njmp 14b9 \nmov -0x141c(%rbp),%eax\nmovslq %eax,%rdx\nmov %rdx,%rax\nadd %rax,%rax\nadd %rdx,%rax\nshl $0x2,%rax\nmov %rax,%rdx\nmov -0x1418(%rbp),%rax\nadd %rax,%rdx\nmov -0x141c(%rbp),%eax\nmovslq %eax,%rcx\nmov %rcx,%rax\nadd %rax,%rax\nadd %rcx,%rax\nshl $0x2,%rax\nadd %rbp,%rax\nsub $0xc10,%rax\nmov (%rax),%rcx\nmov %rcx,(%rdx)\nmov 0x8(%rax),%eax\nmov %eax,0x8(%rdx)\naddl $0x1,-0x141c(%rbp)\nmov -0x141c(%rbp),%eax\ncmp -0x143c(%rbp),%eax\njge 14d5 \nmov -0x141c(%rbp),%eax\ncmp -0x1424(%rbp),%eax\njl 1464 \nmov -0x1418(%rbp),%rax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 14f0 \ncallq 10b0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 1000h\nor [rsp+1000h+var_1000], 0\nsub rsp, 440h\nmov [rbp+var_1438], rdi\nmov [rbp+var_143C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rdx, [rbp+var_1410]\nmov eax, 0\nmov ecx, 80h\nmov rdi, rdx\nrep stosq\nmov [rbp+var_142C], 0\njmp short loc_1297\nloc_127D:\nmov eax, [rbp+var_142C]\ncdqe\nmov [rbp+rax*4+var_1010], 0FFFFFFFFh\nadd [rbp+var_142C], 1\nloc_1297:\ncmp [rbp+var_142C], 0FFh\njle short loc_127D\nmov [rbp+var_1428], 0\njmp short loc_131A\nloc_12AF:\nmov eax, [rbp+var_1428]\nmovsxd rdx, eax\nmov rax, [rbp+var_1438]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_142D], al\nmovzx eax, [rbp+var_142D]\nmovsxd rdx, eax\nmov edx, [rbp+rdx*4+var_1410]\nadd edx, 1\ncdqe\nmov [rbp+rax*4+var_1410], edx\nmovzx eax, [rbp+var_142D]\ncdqe\nmov eax, [rbp+rax*4+var_1010]\ncmp eax, 0FFFFFFFFh\njnz short loc_1313\nmovzx eax, [rbp+var_142D]\ncdqe\nmov edx, [rbp+var_1428]\nmov [rbp+rax*4+var_1010], edx\nloc_1313:\nadd [rbp+var_1428], 1\nloc_131A:\nmov eax, [rbp+var_1428]\nmovsxd rdx, eax\nmov rax, [rbp+var_1438]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_12AF\nmov [rbp+var_1424], 0\nmov [rbp+var_1420], 0\njmp loc_13FF\nloc_1351:\nmov eax, [rbp+var_1420]\ncdqe\nmov eax, [rbp+rax*4+var_1410]\ntest eax, eax\njle loc_13F8\nmov eax, [rbp+var_1420]\nmov ecx, eax\nmov eax, [rbp+var_1424]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rbp\nsub rax, 0C10h\nmov [rax], cl\nmov eax, [rbp+var_1420]\ncdqe\nmov ecx, [rbp+rax*4+var_1410]\nmov eax, [rbp+var_1424]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rbp\nsub rax, 0C0Ch\nmov [rax], ecx\nmov eax, [rbp+var_1420]\ncdqe\nmov ecx, [rbp+rax*4+var_1010]\nmov eax, [rbp+var_1424]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rbp\nsub rax, 0C08h\nmov [rax], ecx\nadd [rbp+var_1424], 1\nloc_13F8:\nadd [rbp+var_1420], 1\nloc_13FF:\ncmp [rbp+var_1420], 0FFh\njle loc_1351\nmov eax, [rbp+var_1424]\nmovsxd rsi, eax; nmemb\nlea rax, [rbp+base]\nlea rdx, compare\nmov rcx, rdx; compar\nmov edx, 0Ch; size\nmov rdi, rax; base\ncall _qsort\nmov eax, [rbp+var_143C]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_1418], rax\nmov [rbp+var_141C], 0\njmp short loc_14BC\nloc_1467:\nmov eax, [rbp+var_141C]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_1418]\nadd rdx, rax\nmov eax, [rbp+var_141C]\nmovsxd rcx, eax\nmov rax, rcx\nadd rax, rax\nadd rax, rcx\nshl rax, 2\nadd rax, rbp\nsub rax, 0C10h\nmov rcx, [rax]\nmov [rdx], rcx\nmov eax, [rax+8]\nmov [rdx+8], eax\nadd [rbp+var_141C], 1\nloc_14BC:\nmov eax, [rbp+var_141C]\ncmp eax, [rbp+var_143C]\njge short loc_14D8\nmov eax, [rbp+var_141C]\ncmp eax, [rbp+var_1424]\njl short loc_1467\nloc_14D8:\nmov rax, [rbp+var_1418]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_14F3\ncall ___stack_chk_fail\nlocret_14F3:\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(__int64 a1, int a2)\n{\n char *v2; // rdx\n unsigned __int8 v4; // [rsp+13h] [rbp-142Dh]\n int i; // [rsp+14h] [rbp-142Ch]\n int j; // [rsp+18h] [rbp-1428h]\n int v7; // [rsp+1Ch] [rbp-1424h]\n int k; // [rsp+20h] [rbp-1420h]\n int m; // [rsp+24h] [rbp-141Ch]\n char *v10; // [rsp+28h] [rbp-1418h]\n _DWORD v11[260]; // [rsp+30h] [rbp-1410h] BYREF\n _BYTE base[3080]; // [rsp+830h] [rbp-C10h] BYREF\n unsigned __int64 v13; // [rsp+1438h] [rbp-8h]\n\n v13 = __readfsqword(0x28u);\n memset(v11, 0, 0x400uLL);\n for ( i = 0; i <= 255; ++i )\n v11[i + 256] = -1;\n for ( j = 0; *(_BYTE *)(j + a1); ++j )\n {\n v4 = *(_BYTE *)(j + a1);\n ++v11[v4];\n if ( v11[v4 + 256] == -1 )\n v11[v4 + 256] = j;\n }\n v7 = 0;\n for ( k = 0; k <= 255; ++k )\n {\n if ( (int)v11[k] > 0 )\n {\n base[12 * v7] = k;\n *(_DWORD *)&base[12 * v7 + 4] = v11[k];\n *(_DWORD *)&base[12 * v7++ + 8] = v11[k + 256];\n }\n }\n qsort(base, v7, 0xCuLL, compare);\n v10 = (char *)malloc(12LL * a2);\n for ( m = 0; m < a2 && m < v7; ++m )\n {\n v2 = &v10[12 * m];\n *(_QWORD *)v2 = *(_QWORD *)&base[12 * m];\n *((_DWORD *)v2 + 2) = *(_DWORD *)&base[12 * m + 8];\n }\n return v10;\n}", + "ida_strip_asm": "sub_1223:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 1000h\nor [rsp+1000h+var_1000], 0\nsub rsp, 440h\nmov [rbp+var_1438], rdi\nmov [rbp+var_143C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rdx, [rbp+var_1410]\nmov eax, 0\nmov ecx, 80h\nmov rdi, rdx\nrep stosq\nmov [rbp+var_142C], 0\njmp short loc_1297\nloc_127D:\nmov eax, [rbp+var_142C]\ncdqe\nmov [rbp+rax*4+var_1010], 0FFFFFFFFh\nadd [rbp+var_142C], 1\nloc_1297:\ncmp [rbp+var_142C], 0FFh\njle short loc_127D\nmov [rbp+var_1428], 0\njmp short loc_131A\nloc_12AF:\nmov eax, [rbp+var_1428]\nmovsxd rdx, eax\nmov rax, [rbp+var_1438]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmov [rbp+var_142D], al\nmovzx eax, [rbp+var_142D]\nmovsxd rdx, eax\nmov edx, [rbp+rdx*4+var_1410]\nadd edx, 1\ncdqe\nmov [rbp+rax*4+var_1410], edx\nmovzx eax, [rbp+var_142D]\ncdqe\nmov eax, [rbp+rax*4+var_1010]\ncmp eax, 0FFFFFFFFh\njnz short loc_1313\nmovzx eax, [rbp+var_142D]\ncdqe\nmov edx, [rbp+var_1428]\nmov [rbp+rax*4+var_1010], edx\nloc_1313:\nadd [rbp+var_1428], 1\nloc_131A:\nmov eax, [rbp+var_1428]\nmovsxd rdx, eax\nmov rax, [rbp+var_1438]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_12AF\nmov [rbp+var_1424], 0\nmov [rbp+var_1420], 0\njmp loc_13FF\nloc_1351:\nmov eax, [rbp+var_1420]\ncdqe\nmov eax, [rbp+rax*4+var_1410]\ntest eax, eax\njle loc_13F8\nmov eax, [rbp+var_1420]\nmov ecx, eax\nmov eax, [rbp+var_1424]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rbp\nsub rax, 0C10h\nmov [rax], cl\nmov eax, [rbp+var_1420]\ncdqe\nmov ecx, [rbp+rax*4+var_1410]\nmov eax, [rbp+var_1424]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rbp\nsub rax, 0C0Ch\nmov [rax], ecx\nmov eax, [rbp+var_1420]\ncdqe\nmov ecx, [rbp+rax*4+var_1010]\nmov eax, [rbp+var_1424]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nadd rax, rbp\nsub rax, 0C08h\nmov [rax], ecx\nadd [rbp+var_1424], 1\nloc_13F8:\nadd [rbp+var_1420], 1\nloc_13FF:\ncmp [rbp+var_1420], 0FFh\njle loc_1351\nmov eax, [rbp+var_1424]\nmovsxd rsi, eax; nmemb\nlea rax, [rbp+base]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 0Ch; size\nmov rdi, rax; base\ncall _qsort\nmov eax, [rbp+var_143C]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_1418], rax\nmov [rbp+var_141C], 0\njmp short loc_14BC\nloc_1467:\nmov eax, [rbp+var_141C]\nmovsxd rdx, eax\nmov rax, rdx\nadd rax, rax\nadd rax, rdx\nshl rax, 2\nmov rdx, rax\nmov rax, [rbp+var_1418]\nadd rdx, rax\nmov eax, [rbp+var_141C]\nmovsxd rcx, eax\nmov rax, rcx\nadd rax, rax\nadd rax, rcx\nshl rax, 2\nadd rax, rbp\nsub rax, 0C10h\nmov rcx, [rax]\nmov [rdx], rcx\nmov eax, [rax+8]\nmov [rdx+8], eax\nadd [rbp+var_141C], 1\nloc_14BC:\nmov eax, [rbp+var_141C]\ncmp eax, [rbp+var_143C]\njge short loc_14D8\nmov eax, [rbp+var_141C]\ncmp eax, [rbp+var_1424]\njl short loc_1467\nloc_14D8:\nmov rax, [rbp+var_1418]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_14F3\ncall ___stack_chk_fail\nlocret_14F3:\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_1223(__int64 a1, int a2)\n{\n char *v2; // rdx\n unsigned __int8 v4; // [rsp+13h] [rbp-142Dh]\n int i; // [rsp+14h] [rbp-142Ch]\n int j; // [rsp+18h] [rbp-1428h]\n int v7; // [rsp+1Ch] [rbp-1424h]\n int k; // [rsp+20h] [rbp-1420h]\n int m; // [rsp+24h] [rbp-141Ch]\n char *v10; // [rsp+28h] [rbp-1418h]\n _DWORD v11[260]; // [rsp+30h] [rbp-1410h] BYREF\n _BYTE base[3080]; // [rsp+830h] [rbp-C10h] BYREF\n unsigned __int64 v13; // [rsp+1438h] [rbp-8h]\n\n v13 = __readfsqword(0x28u);\n memset(v11, 0, 0x400uLL);\n for ( i = 0; i <= 255; ++i )\n v11[i + 256] = -1;\n for ( j = 0; *(_BYTE *)(j + a1); ++j )\n {\n v4 = *(_BYTE *)(j + a1);\n ++v11[v4];\n if ( v11[v4 + 256] == -1 )\n v11[v4 + 256] = j;\n }\n v7 = 0;\n for ( k = 0; k <= 255; ++k )\n {\n if ( (int)v11[k] > 0 )\n {\n base[12 * v7] = k;\n *(_DWORD *)&base[12 * v7 + 4] = v11[k];\n *(_DWORD *)&base[12 * v7++ + 8] = v11[k + 256];\n }\n }\n qsort(base, v7, 0xCuLL, compar);\n v10 = (char *)malloc(12LL * a2);\n for ( m = 0; m < a2 && m < v7; ++m )\n {\n v2 = &v10[12 * m];\n *(_QWORD *)v2 = *(_QWORD *)&base[12 * m];\n *((_DWORD *)v2 + 2) = *(_DWORD *)&base[12 * m + 8];\n }\n return v10;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1223(long long a1, int a2) {\n char *v2;\n unsigned char v4;\n int i;\n int j;\n int v7;\n int k;\n int m;\n char *v10;\n uint32_t v11[260];\n uint8_t base[3080];\n unsigned long long v13;\n v13 = __readfsqword(40u);\n memset(v11, 0, 1024uLL);\n for (i = 0; i <= 255; ++i) v11[i + 256] = -1;\n for (j = 0; *(uint8_t *)(j + a1); ++j) {\n v4 = *(uint8_t *)(j + a1);\n ++v11[v4];\n if (v11[v4 + 256] == -1) v11[v4 + 256] = j;\n }\n v7 = 0;\n for (k = 0; k <= 255; ++k) {\n if ((int)v11[k] > 0) {\n base[12 * v7] = k;\n *(uint32_t *)&base[12 * v7 + 4] = v11[k];\n *(uint32_t *)&base[12 * v7++ + 8] = v11[k + 256];\n }\n }\n qsort(base, v7, 12uLL, compar);\n v10 = (char *)malloc(12LL * a2);\n for (m = 0; m < a2 && m < v7; ++m) {\n v2 = &v10[12 * m];\n *(uint64_t *)v2 = *(uint64_t *)&base[12 * m];\n *((uint32_t *)v2 + 2) = *(uint32_t *)&base[12 * m + 8];\n }\n return v10;\n}", + "ida_pseudo_norm": "char *func0(long long a1, int a2) {\n char *v2;\n unsigned char v4;\n int i;\n int j;\n int v7;\n int k;\n int m;\n char *v10;\n uint32_t v11[260];\n uint8_t base[3080];\n unsigned long long v13;\n v13 = __readfsqword(40u);\n memset(v11, 0, 1024uLL);\n for (i = 0; i <= 255; ++i) v11[i + 256] = -1;\n for (j = 0; *(uint8_t *)(j + a1); ++j) {\n v4 = *(uint8_t *)(j + a1);\n ++v11[v4];\n if (v11[v4 + 256] == -1) v11[v4 + 256] = j;\n }\n v7 = 0;\n for (k = 0; k <= 255; ++k) {\n if ((int)v11[k] > 0) {\n base[12 * v7] = k;\n *(uint32_t *)&base[12 * v7 + 4] = v11[k];\n *(uint32_t *)&base[12 * v7++ + 8] = v11[k + 256];\n }\n }\n qsort(base, v7, 12uLL, compare);\n v10 = (char *)malloc(12LL * a2);\n for (m = 0; m < a2 && m < v7; ++m) {\n v2 = &v10[12 * m];\n *(uint64_t *)v2 = *(uint64_t *)&base[12 * m];\n *((uint32_t *)v2 + 2) = *(uint32_t *)&base[12 * m + 8];\n }\n return v10;\n}" + }, + { + "index": 946, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char character;\n\n int count;\n\n int first_index;\n\n} CharCount;\n\n\n\nint compare(const void* a, const void* b) {\n\n CharCount* cc1 = (CharCount*)a;\n\n CharCount* cc2 = (CharCount*)b;\n\n if (cc2->count != cc1->count)\n\n return cc2->count - cc1->count;\n\n return cc1->first_index - cc2->first_index;\n\n}\n\n\n\n", + "func": "CharCount* func0(const char* s, int a) {\n int counts[256] = {0};\n int first_occurrence[256];\n for (int i = 0; i < 256; i++) first_occurrence[i] = -1;\n for (int i = 0; s[i]; i++) {\n unsigned char c = s[i];\n counts[c]++;\n if (first_occurrence[c] == -1) first_occurrence[c] = i;\n }\n CharCount temp[256];\n int unique = 0;\n for (int i = 0; i < 256; i++) {\n if (counts[i] > 0) {\n temp[unique].character = (char)i;\n temp[unique].count = counts[i];\n temp[unique].first_index = first_occurrence[i];\n unique++;\n }\n }\n qsort(temp, unique, sizeof(CharCount), compare);\n CharCount* result = malloc(a * sizeof(CharCount));\n for (int i = 0; i < a && i < unique; i++) {\n result[i] = temp[i];\n }\n return result;\n}", + "test": "int main() {\n\n CharCount* res1 = func0(\"lkseropewdssafsdfafkpwe\", 3);\n\n assert(res1[0].character == 's' && res1[0].count == 4);\n\n assert(res1[1].character == 'e' && res1[1].count == 3);\n\n assert(res1[2].character == 'f' && res1[2].count == 3);\n\n free(res1);\n\n\n\n CharCount* res2 = func0(\"lkseropewdssafsdfafkpwe\", 2);\n\n assert(res2[0].character == 's' && res2[0].count == 4);\n\n assert(res2[1].character == 'e' && res2[1].count == 3);\n\n free(res2);\n\n\n\n CharCount* res3 = func0(\"lkseropewdssafsdfafkpwe\", 7);\n\n assert(res3[0].character == 's' && res3[0].count == 4);\n\n assert(res3[1].character == 'e' && res3[1].count == 3);\n\n assert(res3[2].character == 'f' && res3[2].count == 3);\n\n assert(res3[3].character == 'k' && res3[3].count == 2);\n\n assert(res3[4].character == 'p' && res3[4].count == 2);\n\n assert(res3[5].character == 'w' && res3[5].count == 2);\n\n assert(res3[6].character == 'd' && res3[6].count == 2);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x1000,%rsp\norq $0x0,(%rsp)\nsub $0x418,%rsp\nmov %rdi,%r8\nmov %esi,%ebx\nmov %fs:0x28,%rax\nmov %rax,0x1408(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nmov $0x80,%ecx\nrep stos %rax,%es:(%rdi)\nlea 0x400(%rsp),%rax\nlea 0x800(%rsp),%rdx\nmovl $0xffffffff,(%rax)\nadd $0x4,%rax\ncmp %rax,%rdx\njne 122d \nmovzbl (%r8),%eax\ntest %al,%al\nje 1278 \nmov $0x0,%edx\njmp 1258 \nadd $0x1,%rdx\nmovzbl (%r8,%rdx,1),%eax\ntest %al,%al\nje 1278 \nmovzbl %al,%ecx\nmovzbl %al,%eax\naddl $0x1,(%rsp,%rax,4)\ncmpl $0xffffffff,0x400(%rsp,%rax,4)\njne 124b \nmovslq %ecx,%rcx\nmov %edx,0x400(%rsp,%rcx,4)\njmp 124b \nmov $0x0,%eax\nmov $0x0,%ebp\njmp 1290 \nadd $0x1,%rax\ncmp $0x100,%rax\nje 12c3 \nmov (%rsp,%rax,4),%esi\ntest %esi,%esi\njle 1284 \nmovslq %ebp,%rcx\nlea (%rcx,%rcx,1),%rdx\nlea (%rdx,%rcx,1),%rdi\nmov %al,0x800(%rsp,%rdi,4)\nmov %esi,0x804(%rsp,%rdi,4)\nmov 0x400(%rsp,%rax,4),%ecx\nmov %ecx,0x808(%rsp,%rdi,4)\nadd $0x1,%ebp\njmp 1284 \nmovslq %ebp,%rsi\nlea 0x800(%rsp),%rdi\nlea -0x10c(%rip),%rcx\nmov $0xc,%edx\ncallq 10a0 \nmovslq %ebx,%rax\nlea (%rax,%rax,2),%rdi\nshl $0x2,%rdi\ncallq 10d0 \ncmp %ebx,%ebp\ncmovle %ebp,%ebx\ntest %ebx,%ebx\njle 1329 \nlea -0x1(%rbx),%edx\nlea 0x3(%rdx,%rdx,2),%rsi\nshl $0x2,%rsi\nmov $0x0,%edx\nmov 0x800(%rsp,%rdx,1),%rcx\nmov %rcx,(%rax,%rdx,1)\nmov 0x808(%rsp,%rdx,1),%ecx\nmov %ecx,0x8(%rax,%rdx,1)\nadd $0xc,%rdx\ncmp %rdx,%rsi\njne 1309 \nmov 0x1408(%rsp),%rbx\nxor %fs:0x28,%rbx\njne 1346 \nadd $0x1418,%rsp\npop %rbx\npop %rbp\nretq\ncallq 10b0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 1000h\nor [rsp+1010h+var_1010], 0\nsub rsp, 418h\nmov r8, rdi\nmov ebx, esi\nmov rax, fs:28h\nmov [rsp+1428h+var_20], rax\nxor eax, eax\nmov rdi, rsp\nmov ecx, 80h\nrep stosq\nlea rax, [rsp+1428h+var_1028]\nlea rdx, [rsp+1428h+base]\nloc_122D:\nmov dword ptr [rax], 0FFFFFFFFh\nadd rax, 4\ncmp rdx, rax\njnz short loc_122D\nmovzx eax, byte ptr [r8]\ntest al, al\njz short loc_1284\nmov ecx, 0\njmp short loc_1264\nloc_124B:\nmov eax, ecx\nloc_124D:\nmovsxd rdx, edx\nmov [rsp+rdx*4+1428h+var_1028], eax\nadd rcx, 1\nmovzx eax, byte ptr [r8+rcx]\ntest al, al\njz short loc_1284\nloc_1264:\nmovzx edx, al\nmovzx eax, al\nadd [rsp+rax*4+1428h+var_1428], 1\ncmp [rsp+rax*4+1428h+var_1028], 0FFFFFFFFh\njz short loc_124B\nmovsxd rax, edx\nmov eax, [rsp+rax*4+1428h+var_1028]\njmp short loc_124D\nloc_1284:\nmov eax, 0\nmov ebp, 0\njmp short loc_129C\nloc_1290:\nadd rax, 1\ncmp rax, 100h\njz short loc_12CF\nloc_129C:\nmov esi, [rsp+rax*4+1428h+var_1428]\ntest esi, esi\njle short loc_1290\nmovsxd rcx, ebp\nlea rdx, [rcx+rcx]\nlea rdi, [rdx+rcx]\nmov byte ptr [rsp+rdi*4+1428h+base], al\nmov dword ptr [rsp+rdi*4+1428h+base+4], esi\nmov ecx, [rsp+rax*4+1428h+var_1028]\nmov [rsp+rdi*4+1428h+var_C20], ecx\nadd ebp, 1\njmp short loc_1290\nloc_12CF:\nmovsxd rsi, ebp; nmemb\nlea rdi, [rsp+1428h+base]; base\nlea rcx, compare; compar\nmov edx, 0Ch; size\ncall _qsort\nmovsxd rax, ebx\nlea rdi, [rax+rax*2]\nshl rdi, 2; size\ncall _malloc\ncmp ebp, ebx\ncmovg ebp, ebx\ntest ebp, ebp\njle short loc_1335\nmovsxd rbp, ebp\nlea rsi, [rbp+rbp*2+0]\nshl rsi, 2\nmov edx, 0\nloc_1315:\nmov rcx, [rsp+rdx+1428h+base]\nmov [rax+rdx], rcx\nmov ecx, [rsp+rdx+1428h+var_C20]\nmov [rax+rdx+8], ecx\nadd rdx, 0Ch\ncmp rsi, rdx\njnz short loc_1315\nloc_1335:\nmov rdx, [rsp+1428h+var_20]\nsub rdx, fs:28h\njnz short loc_1352\nadd rsp, 1418h\npop rbx\npop rbp\nretn\nloc_1352:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(unsigned __int8 *a1, int a2)\n{\n _QWORD *v3; // rax\n unsigned __int8 v4; // al\n __int64 v5; // rcx\n int v6; // eax\n int v7; // edx\n __int64 v8; // rax\n int v9; // ebp\n int v10; // esi\n __int64 v11; // rdi\n char *result; // rax\n __int64 v13; // rdx\n _DWORD v14[256]; // [rsp+0h] [rbp-1428h] BYREF\n _DWORD v15[6]; // [rsp+400h] [rbp-1028h] BYREF\n _QWORD base[389]; // [rsp+800h] [rbp-C28h] BYREF\n\n base[385] = __readfsqword(0x28u);\n memset(v14, 0, sizeof(v14));\n v3 = v15;\n do\n {\n *(_DWORD *)v3 = -1;\n v3 = (_QWORD *)((char *)v3 + 4);\n }\n while ( base != v3 );\n v4 = *a1;\n if ( *a1 )\n {\n v5 = 0LL;\n do\n {\n v7 = v4;\n ++v14[v4];\n if ( v15[v4] == -1 )\n v6 = v5;\n else\n v6 = v15[v4];\n v15[v7] = v6;\n v4 = a1[++v5];\n }\n while ( v4 );\n }\n v8 = 0LL;\n v9 = 0;\n do\n {\n v10 = v14[v8];\n if ( v10 > 0 )\n {\n v11 = 3LL * v9;\n *((_BYTE *)base + 4 * v11) = v8;\n *((_DWORD *)base + v11 + 1) = v10;\n *((_DWORD *)&base[1] + v11) = v15[v8];\n ++v9;\n }\n ++v8;\n }\n while ( v8 != 256 );\n qsort(base, v9, 0xCuLL, compare);\n result = (char *)malloc(12LL * a2);\n if ( v9 > a2 )\n v9 = a2;\n if ( v9 > 0 )\n {\n v13 = 0LL;\n do\n {\n *(_QWORD *)&result[v13] = *(_QWORD *)((char *)base + v13);\n *(_DWORD *)&result[v13 + 8] = *(_DWORD *)((char *)&base[1] + v13);\n v13 += 12LL;\n }\n while ( 12LL * v9 != v13 );\n }\n return result;\n}", + "ida_strip_asm": "sub_11E1:\nendbr64\npush rbp\npush rbx\nsub rsp, 1000h\nor [rsp+1010h+var_1010], 0\nsub rsp, 418h\nmov r8, rdi\nmov ebx, esi\nmov rax, fs:28h\nmov [rsp+1428h+var_20], rax\nxor eax, eax\nmov rdi, rsp\nmov ecx, 80h\nrep stosq\nlea rax, [rsp+1428h+var_1028]\nlea rdx, [rsp+1428h+base]\nloc_122D:\nmov dword ptr [rax], 0FFFFFFFFh\nadd rax, 4\ncmp rdx, rax\njnz short loc_122D\nmovzx eax, byte ptr [r8]\ntest al, al\njz short loc_1284\nmov ecx, 0\njmp short loc_1264\nloc_124B:\nmov eax, ecx\nloc_124D:\nmovsxd rdx, edx\nmov [rsp+rdx*4+1428h+var_1028], eax\nadd rcx, 1\nmovzx eax, byte ptr [r8+rcx]\ntest al, al\njz short loc_1284\nloc_1264:\nmovzx edx, al\nmovzx eax, al\nadd [rsp+rax*4+1428h+var_1428], 1\ncmp [rsp+rax*4+1428h+var_1028], 0FFFFFFFFh\njz short loc_124B\nmovsxd rax, edx\nmov eax, [rsp+rax*4+1428h+var_1028]\njmp short loc_124D\nloc_1284:\nmov eax, 0\nmov ebp, 0\njmp short loc_129C\nloc_1290:\nadd rax, 1\ncmp rax, 100h\njz short loc_12CF\nloc_129C:\nmov esi, [rsp+rax*4+1428h+var_1428]\ntest esi, esi\njle short loc_1290\nmovsxd rcx, ebp\nlea rdx, [rcx+rcx]\nlea rdi, [rdx+rcx]\nmov byte ptr [rsp+rdi*4+1428h+base], al\nmov dword ptr [rsp+rdi*4+1428h+base+4], esi\nmov ecx, [rsp+rax*4+1428h+var_1028]\nmov [rsp+rdi*4+1428h+var_C20], ecx\nadd ebp, 1\njmp short loc_1290\nloc_12CF:\nmovsxd rsi, ebp; nmemb\nlea rdi, [rsp+1428h+base]; base\nlea rcx, compar; compar\nmov edx, 0Ch; size\ncall _qsort\nmovsxd rax, ebx\nlea rdi, [rax+rax*2]\nshl rdi, 2; size\ncall _malloc\ncmp ebp, ebx\ncmovg ebp, ebx\ntest ebp, ebp\njle short loc_1335\nmovsxd rbp, ebp\nlea rsi, [rbp+rbp*2+0]\nshl rsi, 2\nmov edx, 0\nloc_1315:\nmov rcx, [rsp+rdx+1428h+base]\nmov [rax+rdx], rcx\nmov ecx, [rsp+rdx+1428h+var_C20]\nmov [rax+rdx+8], ecx\nadd rdx, 0Ch\ncmp rsi, rdx\njnz short loc_1315\nloc_1335:\nmov rdx, [rsp+1428h+var_20]\nsub rdx, fs:28h\njnz short loc_1352\nadd rsp, 1418h\npop rbx\npop rbp\nretn\nloc_1352:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_11E1(unsigned __int8 *a1, int a2)\n{\n _QWORD *v3; // rax\n unsigned __int8 v4; // al\n __int64 v5; // rcx\n int v6; // eax\n int v7; // edx\n __int64 v8; // rax\n int v9; // ebp\n int v10; // esi\n __int64 v11; // rdi\n char *result; // rax\n __int64 v13; // rdx\n _DWORD v14[256]; // [rsp+0h] [rbp-1428h] BYREF\n _DWORD v15[6]; // [rsp+400h] [rbp-1028h] BYREF\n _QWORD base[389]; // [rsp+800h] [rbp-C28h] BYREF\n\n base[385] = __readfsqword(0x28u);\n memset(v14, 0, sizeof(v14));\n v3 = v15;\n do\n {\n *(_DWORD *)v3 = -1;\n v3 = (_QWORD *)((char *)v3 + 4);\n }\n while ( base != v3 );\n v4 = *a1;\n if ( *a1 )\n {\n v5 = 0LL;\n do\n {\n v7 = v4;\n ++v14[v4];\n if ( v15[v4] == -1 )\n v6 = v5;\n else\n v6 = v15[v4];\n v15[v7] = v6;\n v4 = a1[++v5];\n }\n while ( v4 );\n }\n v8 = 0LL;\n v9 = 0;\n do\n {\n v10 = v14[v8];\n if ( v10 > 0 )\n {\n v11 = 3LL * v9;\n *((_BYTE *)base + 4 * v11) = v8;\n *((_DWORD *)base + v11 + 1) = v10;\n *((_DWORD *)&base[1] + v11) = v15[v8];\n ++v9;\n }\n ++v8;\n }\n while ( v8 != 256 );\n qsort(base, v9, 0xCuLL, compar);\n result = (char *)malloc(12LL * a2);\n if ( v9 > a2 )\n v9 = a2;\n if ( v9 > 0 )\n {\n v13 = 0LL;\n do\n {\n *(_QWORD *)&result[v13] = *(_QWORD *)((char *)base + v13);\n *(_DWORD *)&result[v13 + 8] = *(_DWORD *)((char *)&base[1] + v13);\n v13 += 12LL;\n }\n while ( 12LL * v9 != v13 );\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11E1(unsigned char *a1, int a2) {\n uint64_t *v3;\n unsigned char v4;\n long long v5;\n int v6;\n int v7;\n long long v8;\n int v9;\n int v10;\n long long v11;\n char *result;\n long long v13;\n uint32_t v14[256];\n uint32_t v15[6];\n uint64_t base[389];\n base[385] = __readfsqword(40u);\n memset(v14, 0, sizeof(v14));\n v3 = v15;\n do {\n *(uint32_t *)v3 = -1;\n v3 = (uint64_t *)((char *)v3 + 4);\n } while (base != v3);\n v4 = *a1;\n if (*a1) {\n v5 = 0LL;\n do {\n v7 = v4;\n ++v14[v4];\n if (v15[v4] == -1)\n v6 = v5;\n else\n v6 = v15[v4];\n v15[v7] = v6;\n v4 = a1[++v5];\n } while (v4);\n }\n v8 = 0LL;\n v9 = 0;\n do {\n v10 = v14[v8];\n if (v10 > 0) {\n v11 = 3LL * v9;\n *((uint8_t *)base + 4 * v11) = v8;\n *((uint32_t *)base + v11 + 1) = v10;\n *((uint32_t *)&base[1] + v11) = v15[v8];\n ++v9;\n }\n ++v8;\n } while (v8 != 256);\n qsort(base, v9, 12uLL, compar);\n result = (char *)malloc(12LL * a2);\n if (v9 > a2) v9 = a2;\n if (v9 > 0) {\n v13 = 0LL;\n do {\n *(uint64_t *)&result[v13] = *(uint64_t *)((char *)base + v13);\n *(uint32_t *)&result[v13 + 8] = *(uint32_t *)((char *)&base[1] + v13);\n v13 += 12LL;\n } while (12LL * v9 != v13);\n }\n return result;\n}", + "ida_pseudo_norm": "char *func0(unsigned char *a1, int a2) {\n uint64_t *v3;\n unsigned char v4;\n long long v5;\n int v6;\n int v7;\n long long v8;\n int v9;\n int v10;\n long long v11;\n char *result;\n long long v13;\n uint32_t v14[256];\n uint32_t v15[6];\n uint64_t base[389];\n base[385] = __readfsqword(40u);\n memset(v14, 0, sizeof(v14));\n v3 = v15;\n do {\n *(uint32_t *)v3 = -1;\n v3 = (uint64_t *)((char *)v3 + 4);\n } while (base != v3);\n v4 = *a1;\n if (*a1) {\n v5 = 0LL;\n do {\n v7 = v4;\n ++v14[v4];\n if (v15[v4] == -1)\n v6 = v5;\n else\n v6 = v15[v4];\n v15[v7] = v6;\n v4 = a1[++v5];\n } while (v4);\n }\n v8 = 0LL;\n v9 = 0;\n do {\n v10 = v14[v8];\n if (v10 > 0) {\n v11 = 3LL * v9;\n *((uint8_t *)base + 4 * v11) = v8;\n *((uint32_t *)base + v11 + 1) = v10;\n *((uint32_t *)&base[1] + v11) = v15[v8];\n ++v9;\n }\n ++v8;\n } while (v8 != 256);\n qsort(base, v9, 12uLL, compare);\n result = (char *)malloc(12LL * a2);\n if (v9 > a2) v9 = a2;\n if (v9 > 0) {\n v13 = 0LL;\n do {\n *(uint64_t *)&result[v13] = *(uint64_t *)((char *)base + v13);\n *(uint32_t *)&result[v13 + 8] = *(uint32_t *)((char *)&base[1] + v13);\n v13 += 12LL;\n } while (12LL * v9 != v13);\n }\n return result;\n}" + }, + { + "index": 946, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char character;\n\n int count;\n\n int first_index;\n\n} CharCount;\n\n\n\nint compare(const void* a, const void* b) {\n\n CharCount* cc1 = (CharCount*)a;\n\n CharCount* cc2 = (CharCount*)b;\n\n if (cc2->count != cc1->count)\n\n return cc2->count - cc1->count;\n\n return cc1->first_index - cc2->first_index;\n\n}\n\n\n\n", + "func": "CharCount* func0(const char* s, int a) {\n int counts[256] = {0};\n int first_occurrence[256];\n for (int i = 0; i < 256; i++) first_occurrence[i] = -1;\n for (int i = 0; s[i]; i++) {\n unsigned char c = s[i];\n counts[c]++;\n if (first_occurrence[c] == -1) first_occurrence[c] = i;\n }\n CharCount temp[256];\n int unique = 0;\n for (int i = 0; i < 256; i++) {\n if (counts[i] > 0) {\n temp[unique].character = (char)i;\n temp[unique].count = counts[i];\n temp[unique].first_index = first_occurrence[i];\n unique++;\n }\n }\n qsort(temp, unique, sizeof(CharCount), compare);\n CharCount* result = malloc(a * sizeof(CharCount));\n for (int i = 0; i < a && i < unique; i++) {\n result[i] = temp[i];\n }\n return result;\n}", + "test": "int main() {\n\n CharCount* res1 = func0(\"lkseropewdssafsdfafkpwe\", 3);\n\n assert(res1[0].character == 's' && res1[0].count == 4);\n\n assert(res1[1].character == 'e' && res1[1].count == 3);\n\n assert(res1[2].character == 'f' && res1[2].count == 3);\n\n free(res1);\n\n\n\n CharCount* res2 = func0(\"lkseropewdssafsdfafkpwe\", 2);\n\n assert(res2[0].character == 's' && res2[0].count == 4);\n\n assert(res2[1].character == 'e' && res2[1].count == 3);\n\n free(res2);\n\n\n\n CharCount* res3 = func0(\"lkseropewdssafsdfafkpwe\", 7);\n\n assert(res3[0].character == 's' && res3[0].count == 4);\n\n assert(res3[1].character == 'e' && res3[1].count == 3);\n\n assert(res3[2].character == 'f' && res3[2].count == 3);\n\n assert(res3[3].character == 'k' && res3[3].count == 2);\n\n assert(res3[4].character == 'p' && res3[4].count == 2);\n\n assert(res3[5].character == 'w' && res3[5].count == 2);\n\n assert(res3[6].character == 'd' && res3[6].count == 2);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nsub $0x1000,%rsp\norq $0x0,(%rsp)\nsub $0x410,%rsp\nmov $0x80,%ecx\nmov %fs:0x28,%rax\nmov %rax,0x1408(%rsp)\nxor %eax,%eax\nmov %esi,%ebx\nmov %rsp,%rsi\nmov %rdi,%r8\nmov %rsi,%rdi\nlea 0x800(%rsp),%r12\nrep stos %rax,%es:(%rdi)\nlea 0x400(%rsp),%rdi\nmov %rdi,%rax\nnopl 0x0(%rax)\nmovl $0xffffffff,(%rax)\nadd $0x4,%rax\ncmp %r12,%rax\njne 14f8 \nmovzbl (%r8),%eax\nxor %edx,%edx\ntest %al,%al\nje 153a \nnopl 0x0(%rax)\naddl $0x1,(%rsp,%rax,4)\ncmpl $0xffffffff,0x400(%rsp,%rax,4)\njne 152d \nmov %edx,0x400(%rsp,%rax,4)\nadd $0x1,%rdx\nmovzbl (%r8,%rdx,1),%eax\ntest %al,%al\njne 1518 \nxor %eax,%eax\nxor %ebp,%ebp\nxchg %ax,%ax\nadd $0x1,%rax\ncmp $0x100,%rax\nje 1585 \nmov (%rsi,%rax,4),%ecx\ntest %ecx,%ecx\njle 1540 \nmovslq %ebp,%rdx\nadd $0x1,%ebp\nlea (%rdx,%rdx,2),%rdx\nshl $0x2,%rdx\nmov %ecx,0x804(%rsp,%rdx,1)\nmov (%rdi,%rax,4),%ecx\nmov %al,0x800(%rsp,%rdx,1)\nadd $0x1,%rax\nmov %ecx,0x808(%rsp,%rdx,1)\ncmp $0x100,%rax\njne 154c \nmovslq %ebp,%rsi\nlea -0x10f(%rip),%rcx\nmov $0xc,%edx\nmov %r12,%rdi\ncallq 10a0 \nmovslq %ebx,%rax\nlea (%rax,%rax,2),%rdi\nshl $0x2,%rdi\ncallq 10d0 \ncmp %ebx,%ebp\ncmovle %ebp,%ebx\ntest %ebx,%ebx\njle 15e2 \nlea -0x1(%rbx),%edx\nlea 0x3(%rdx,%rdx,2),%rsi\nxor %edx,%edx\nshl $0x2,%rsi\nnopl 0x0(%rax,%rax,1)\nmov (%r12,%rdx,1),%rcx\nmov %rcx,(%rax,%rdx,1)\nmov 0x8(%r12,%rdx,1),%ecx\nmov %ecx,0x8(%rax,%rdx,1)\nadd $0xc,%rdx\ncmp %rdx,%rsi\njne 15c8 \nmov 0x1408(%rsp),%rbx\nxor %fs:0x28,%rbx\njne 1601 \nadd $0x1410,%rsp\npop %rbx\npop %rbp\npop %r12\nretq\ncallq 10b0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 1000h\nor [rsp+1018h+var_1018], 0\nsub rsp, 410h\nmov ecx, 80h\nmov rax, fs:28h\nmov [rsp+1428h+var_20], rax\nxor eax, eax\nmov ebx, esi\nmov rsi, rsp\nmov r9, rdi\nlea r8, [rsp+1428h+var_1028]\nmov rdi, rsi\nrep stosq\nmov rax, 0FFFFFFFFFFFFFFFFh\nmov ecx, 80h\nmov rdi, r8\nrep stosq\nmovzx eax, byte ptr [r9]\ntest al, al\njz short loc_1540\nnop dword ptr [rax+rax+00h]\nloc_1518:\nmovzx eax, al\nmov edx, [rsp+rax*4+1428h+var_1028]\nadd [rsp+rax*4+1428h+var_1428], 1\ncmp edx, 0FFFFFFFFh\ncmovz edx, ecx\nadd rcx, 1\nmov [rsp+rax*4+1428h+var_1028], edx\nmovzx eax, byte ptr [r9+rcx]\ntest al, al\njnz short loc_1518\nloc_1540:\nxor eax, eax\nxor ebp, ebp\nlea r12, [rsp+1428h+base]\nnop dword ptr [rax+00h]\nloc_1550:\nmov edx, [rsi+rax*4]\ntest edx, edx\njle short loc_1581\nmovd xmm1, dword ptr [r8+rax*4]\nmovsxd rcx, ebp\nmovd xmm0, edx\nadd ebp, 1\nlea rcx, [rcx+rcx*2]\nshl rcx, 2\npunpckldq xmm0, xmm1\nmov [rsp+rcx+1428h+base], al\nmovq qword ptr [r12+rcx+4], xmm0\nloc_1581:\nadd rax, 1\ncmp rax, 100h\njnz short loc_1550\nmovsxd rsi, ebp; nmemb\nlea rcx, compare; compar\nmov edx, 0Ch; size\nmov rdi, r12; base\ncall _qsort\nmovsxd rax, ebx\nlea rdi, [rax+rax*2]\nshl rdi, 2; size\ncall _malloc\ncmp ebp, ebx\ncmovg rbp, rbx\nmov rcx, rax\ntest ebp, ebp\njle short loc_15D8\nlea rdx, [rbp+rbp*2+0]\nmov rsi, r12; src\nmov rdi, rax; dest\nshl rdx, 2; n\ncall _memcpy\nmov rcx, rax\nloc_15D8:\nmov rax, [rsp+1428h+var_20]\nsub rax, fs:28h\njnz short loc_15FA\nadd rsp, 1410h\nmov rax, rcx\npop rbx\npop rbp\npop r12\nretn\nloc_15FA:\ncall ___stack_chk_fail", + "ida_pseudo": "void *__fastcall func0(unsigned __int8 *a1, int a2)\n{\n __int64 v2; // rcx\n unsigned __int8 i; // al\n int v4; // edx\n __int64 v5; // rax\n __int64 v6; // rbp\n signed int v7; // edx\n __int64 v8; // rcx\n unsigned __int64 v9; // xmm0_8\n void *v10; // rax\n void *v11; // rcx\n _DWORD v13[256]; // [rsp+0h] [rbp-1428h] BYREF\n _QWORD v14[128]; // [rsp+400h] [rbp-1028h] BYREF\n _BYTE base[3080]; // [rsp+800h] [rbp-C28h] BYREF\n unsigned __int64 v16; // [rsp+1408h] [rbp-20h]\n\n v16 = __readfsqword(0x28u);\n memset(v13, 0, sizeof(v13));\n memset(v14, 0xFFu, sizeof(v14));\n v2 = 0LL;\n for ( i = *a1; i; i = a1[v2] )\n {\n v4 = *((_DWORD *)v14 + i);\n ++v13[i];\n if ( v4 == -1 )\n v4 = v2;\n ++v2;\n *((_DWORD *)v14 + i) = v4;\n }\n v5 = 0LL;\n v6 = 0LL;\n do\n {\n v7 = v13[v5];\n if ( v7 > 0 )\n {\n v8 = (int)v6;\n v6 = (unsigned int)(v6 + 1);\n v8 *= 12LL;\n v9 = _mm_unpacklo_epi32(_mm_cvtsi32_si128(v7), _mm_cvtsi32_si128(*((_DWORD *)v14 + v5))).m128i_u64[0];\n base[v8] = v5;\n *(_QWORD *)&base[v8 + 4] = v9;\n }\n ++v5;\n }\n while ( v5 != 256 );\n qsort(base, (int)v6, 0xCuLL, compare);\n v10 = malloc(12LL * a2);\n if ( (int)v6 > a2 )\n v6 = (unsigned int)a2;\n v11 = v10;\n if ( (int)v6 > 0 )\n return memcpy(v10, base, 12 * v6);\n return v11;\n}", + "ida_strip_asm": "sub_14B0:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 1000h\nor [rsp+1018h+var_1018], 0\nsub rsp, 410h\nmov ecx, 80h\nmov rax, fs:28h\nmov [rsp+1428h+var_20], rax\nxor eax, eax\nmov ebx, esi\nmov rsi, rsp\nmov r9, rdi\nlea r8, [rsp+1428h+var_1028]\nmov rdi, rsi\nrep stosq\nmov rax, 0FFFFFFFFFFFFFFFFh\nmov ecx, 80h\nmov rdi, r8\nrep stosq\nmovzx eax, byte ptr [r9]\ntest al, al\njz short loc_1540\nnop dword ptr [rax+rax+00h]\nloc_1518:\nmovzx eax, al\nmov edx, [rsp+rax*4+1428h+var_1028]\nadd [rsp+rax*4+1428h+var_1428], 1\ncmp edx, 0FFFFFFFFh\ncmovz edx, ecx\nadd rcx, 1\nmov [rsp+rax*4+1428h+var_1028], edx\nmovzx eax, byte ptr [r9+rcx]\ntest al, al\njnz short loc_1518\nloc_1540:\nxor eax, eax\nxor ebp, ebp\nlea r12, [rsp+1428h+base]\nnop dword ptr [rax+00h]\nloc_1550:\nmov edx, [rsi+rax*4]\ntest edx, edx\njle short loc_1581\nmovd xmm1, dword ptr [r8+rax*4]\nmovsxd rcx, ebp\nmovd xmm0, edx\nadd ebp, 1\nlea rcx, [rcx+rcx*2]\nshl rcx, 2\npunpckldq xmm0, xmm1\nmov [rsp+rcx+1428h+base], al\nmovq qword ptr [r12+rcx+4], xmm0\nloc_1581:\nadd rax, 1\ncmp rax, 100h\njnz short loc_1550\nmovsxd rsi, ebp; nmemb\nlea rcx, compar; compar\nmov edx, 0Ch; size\nmov rdi, r12; base\ncall _qsort\nmovsxd rax, ebx\nlea rdi, [rax+rax*2]\nshl rdi, 2; size\ncall _malloc\ncmp ebp, ebx\ncmovg rbp, rbx\nmov rcx, rax\ntest ebp, ebp\njle short loc_15D8\nlea rdx, [rbp+rbp*2+0]\nmov rsi, r12; src\nmov rdi, rax; dest\nshl rdx, 2; n\ncall _memcpy\nmov rcx, rax\nloc_15D8:\nmov rax, [rsp+1428h+var_20]\nsub rax, fs:28h\njnz short loc_15FA\nadd rsp, 1410h\nmov rax, rcx\npop rbx\npop rbp\npop r12\nretn\nloc_15FA:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "void *__fastcall sub_14B0(unsigned __int8 *a1, int a2)\n{\n __int64 v2; // rcx\n unsigned __int8 i; // al\n int v4; // edx\n __int64 v5; // rax\n __int64 v6; // rbp\n signed int v7; // edx\n __int64 v8; // rcx\n unsigned __int64 v9; // xmm0_8\n void *v10; // rax\n void *v11; // rcx\n _DWORD v13[256]; // [rsp+0h] [rbp-1428h] BYREF\n _QWORD v14[128]; // [rsp+400h] [rbp-1028h] BYREF\n _BYTE base[3080]; // [rsp+800h] [rbp-C28h] BYREF\n unsigned __int64 v16; // [rsp+1408h] [rbp-20h]\n\n v16 = __readfsqword(0x28u);\n memset(v13, 0, sizeof(v13));\n memset(v14, 0xFFu, sizeof(v14));\n v2 = 0LL;\n for ( i = *a1; i; i = a1[v2] )\n {\n v4 = *((_DWORD *)v14 + i);\n ++v13[i];\n if ( v4 == -1 )\n v4 = v2;\n ++v2;\n *((_DWORD *)v14 + i) = v4;\n }\n v5 = 0LL;\n v6 = 0LL;\n do\n {\n v7 = v13[v5];\n if ( v7 > 0 )\n {\n v8 = (int)v6;\n v6 = (unsigned int)(v6 + 1);\n v8 *= 12LL;\n v9 = _mm_unpacklo_epi32(_mm_cvtsi32_si128(v7), _mm_cvtsi32_si128(*((_DWORD *)v14 + v5))).m128i_u64[0];\n base[v8] = v5;\n *(_QWORD *)&base[v8 + 4] = v9;\n }\n ++v5;\n }\n while ( v5 != 256 );\n qsort(base, (int)v6, 0xCuLL, compar);\n v10 = malloc(12LL * a2);\n if ( (int)v6 > a2 )\n v6 = (unsigned int)a2;\n v11 = v10;\n if ( (int)v6 > 0 )\n return memcpy(v10, base, 12 * v6);\n return v11;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_14B0(unsigned char *a1, int a2) {\n long long v2;\n unsigned char i;\n int v4;\n long long v5;\n long long v6;\n signed int v7;\n long long v8;\n unsigned long long v9;\n void *v10;\n void *v11;\n uint32_t v13[256];\n uint64_t v14[128];\n uint8_t base[3080];\n unsigned long long v16;\n v16 = __readfsqword(40u);\n memset(v13, 0, sizeof(v13));\n memset(v14, 255u, sizeof(v14));\n v2 = 0LL;\n for (i = *a1; i; i = a1[v2]) {\n v4 = *((uint32_t *)v14 + i);\n ++v13[i];\n if (v4 == -1) v4 = v2;\n ++v2;\n *((uint32_t *)v14 + i) = v4;\n }\n v5 = 0LL;\n v6 = 0LL;\n do {\n v7 = v13[v5];\n if (v7 > 0) {\n v8 = (int)v6;\n v6 = (unsigned int)(v6 + 1);\n v8 *= 12LL;\n v9 = _mm_unpacklo_epi32(_mm_cvtsi32_si128(v7),\n _mm_cvtsi32_si128(*((uint32_t *)v14 + v5)))\n .m128i_u64[0];\n base[v8] = v5;\n *(uint64_t *)&base[v8 + 4] = v9;\n }\n ++v5;\n } while (v5 != 256);\n qsort(base, (int)v6, 12uLL, compar);\n v10 = malloc(12LL * a2);\n if ((int)v6 > a2) v6 = (unsigned int)a2;\n v11 = v10;\n if ((int)v6 > 0) return memcpy(v10, base, 12 * v6);\n return v11;\n}", + "ida_pseudo_norm": "void *func0(unsigned char *a1, int a2) {\n long long v2;\n unsigned char i;\n int v4;\n long long v5;\n long long v6;\n signed int v7;\n long long v8;\n unsigned long long v9;\n void *v10;\n void *v11;\n uint32_t v13[256];\n uint64_t v14[128];\n uint8_t base[3080];\n unsigned long long v16;\n v16 = __readfsqword(40u);\n memset(v13, 0, sizeof(v13));\n memset(v14, 255u, sizeof(v14));\n v2 = 0LL;\n for (i = *a1; i; i = a1[v2]) {\n v4 = *((uint32_t *)v14 + i);\n ++v13[i];\n if (v4 == -1) v4 = v2;\n ++v2;\n *((uint32_t *)v14 + i) = v4;\n }\n v5 = 0LL;\n v6 = 0LL;\n do {\n v7 = v13[v5];\n if (v7 > 0) {\n v8 = (int)v6;\n v6 = (unsigned int)(v6 + 1);\n v8 *= 12LL;\n v9 = _mm_unpacklo_epi32(_mm_cvtsi32_si128(v7),\n _mm_cvtsi32_si128(*((uint32_t *)v14 + v5)))\n .m128i_u64[0];\n base[v8] = v5;\n *(uint64_t *)&base[v8 + 4] = v9;\n }\n ++v5;\n } while (v5 != 256);\n qsort(base, (int)v6, 12uLL, compare);\n v10 = malloc(12LL * a2);\n if ((int)v6 > a2) v6 = (unsigned int)a2;\n v11 = v10;\n if ((int)v6 > 0) return memcpy(v10, base, 12 * v6);\n return v11;\n}" + }, + { + "index": 946, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n char character;\n\n int count;\n\n int first_index;\n\n} CharCount;\n\n\n\nint compare(const void* a, const void* b) {\n\n CharCount* cc1 = (CharCount*)a;\n\n CharCount* cc2 = (CharCount*)b;\n\n if (cc2->count != cc1->count)\n\n return cc2->count - cc1->count;\n\n return cc1->first_index - cc2->first_index;\n\n}\n\n\n\n", + "func": "CharCount* func0(const char* s, int a) {\n int counts[256] = {0};\n int first_occurrence[256];\n for (int i = 0; i < 256; i++) first_occurrence[i] = -1;\n for (int i = 0; s[i]; i++) {\n unsigned char c = s[i];\n counts[c]++;\n if (first_occurrence[c] == -1) first_occurrence[c] = i;\n }\n CharCount temp[256];\n int unique = 0;\n for (int i = 0; i < 256; i++) {\n if (counts[i] > 0) {\n temp[unique].character = (char)i;\n temp[unique].count = counts[i];\n temp[unique].first_index = first_occurrence[i];\n unique++;\n }\n }\n qsort(temp, unique, sizeof(CharCount), compare);\n CharCount* result = malloc(a * sizeof(CharCount));\n for (int i = 0; i < a && i < unique; i++) {\n result[i] = temp[i];\n }\n return result;\n}", + "test": "int main() {\n\n CharCount* res1 = func0(\"lkseropewdssafsdfafkpwe\", 3);\n\n assert(res1[0].character == 's' && res1[0].count == 4);\n\n assert(res1[1].character == 'e' && res1[1].count == 3);\n\n assert(res1[2].character == 'f' && res1[2].count == 3);\n\n free(res1);\n\n\n\n CharCount* res2 = func0(\"lkseropewdssafsdfafkpwe\", 2);\n\n assert(res2[0].character == 's' && res2[0].count == 4);\n\n assert(res2[1].character == 'e' && res2[1].count == 3);\n\n free(res2);\n\n\n\n CharCount* res3 = func0(\"lkseropewdssafsdfafkpwe\", 7);\n\n assert(res3[0].character == 's' && res3[0].count == 4);\n\n assert(res3[1].character == 'e' && res3[1].count == 3);\n\n assert(res3[2].character == 'f' && res3[2].count == 3);\n\n assert(res3[3].character == 'k' && res3[3].count == 2);\n\n assert(res3[4].character == 'p' && res3[4].count == 2);\n\n assert(res3[5].character == 'w' && res3[5].count == 2);\n\n assert(res3[6].character == 'd' && res3[6].count == 2);\n\n free(res3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nsub $0x1000,%rsp\norq $0x0,(%rsp)\nsub $0x410,%rsp\nmov $0x80,%ecx\nmov %fs:0x28,%rax\nmov %rax,0x1408(%rsp)\nxor %eax,%eax\nmov %esi,%ebp\nmov %rsp,%rsi\nmov %rdi,%r9\nlea 0x400(%rsp),%r8\nmov %rsi,%rdi\nrep stos %rax,%es:(%rdi)\nmov $0xffffffffffffffff,%rax\nmov $0x80,%ecx\nmov %r8,%rdi\nrep stos %rax,%es:(%rdi)\nmovzbl (%r9),%eax\ntest %al,%al\nje 1547 \nxor %edx,%edx\nnopl (%rax)\naddl $0x1,(%rsp,%rax,4)\ncmpl $0xffffffff,0x400(%rsp,%rax,4)\nje 1608 \nadd $0x1,%rdx\nmovzbl (%r9,%rdx,1),%eax\ntest %al,%al\njne 1528 \nxor %eax,%eax\nxor %ebx,%ebx\nnopl 0x0(%rax,%rax,1)\nmov (%rsi,%rax,4),%ecx\ntest %ecx,%ecx\njle 157e \nmovslq %ebx,%rdx\nadd $0x1,%ebx\nlea (%rdx,%rdx,2),%rdx\nshl $0x2,%rdx\nmov %ecx,0x804(%rsp,%rdx,1)\nmov (%r8,%rax,4),%ecx\nmov %al,0x800(%rsp,%rdx,1)\nmov %ecx,0x808(%rsp,%rdx,1)\nadd $0x1,%rax\ncmp $0x100,%rax\njne 1550 \nlea 0x800(%rsp),%r12\nmovslq %ebx,%rsi\nmov $0xc,%edx\nlea -0x101(%rip),%rcx\nmov %r12,%rdi\ncallq 10b0 \nmovslq %ebp,%rax\nlea (%rax,%rax,2),%rdi\nshl $0x2,%rdi\ncallq 10f0 \ncmp %ebp,%ebx\ncmovg %ebp,%ebx\nmov %rax,%r8\ntest %ebx,%ebx\njle 15df \nlea -0x1(%rbx),%eax\nmov %r8,%rdi\nmov %r12,%rsi\nlea 0x3(%rax,%rax,2),%rdx\nshl $0x2,%rdx\ncallq 10e0 \nmov %rax,%r8\nmov 0x1408(%rsp),%rax\nxor %fs:0x28,%rax\njne 1625 \nadd $0x1410,%rsp\nmov %r8,%rax\npop %rbx\npop %rbp\npop %r12\nretq\nnopl 0x0(%rax)\nmov %edx,0x400(%rsp,%rax,4)\nadd $0x1,%rdx\nmovzbl (%r9,%rdx,1),%eax\ntest %al,%al\njne 1528 \njmpq 1547 \ncallq 10c0 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 1000h\nor [rsp+1018h+var_1018], 0\nsub rsp, 410h\nmov ecx, 80h\nxor edx, edx\nmov rax, fs:28h\nmov [rsp+1428h+var_20], rax\nxor eax, eax\nmov ebx, esi\nmov rsi, rsp\nmov r9, rdi\nlea r8, [rsp+1428h+var_1028]\nmov rdi, rsi\nrep stosq\nmov rax, 0FFFFFFFFFFFFFFFFh\nmov ecx, 80h\nmov rdi, r8\nrep stosq\nmovzx eax, byte ptr [r9]\ntest al, al\njz short loc_1540\nnop dword ptr [rax]\nloc_1518:\nmov ecx, [rsp+rax*4+1428h+var_1028]\nadd [rsp+rax*4+1428h+var_1428], 1\ncmp ecx, 0FFFFFFFFh\njz loc_1600\nadd rdx, 1\nmov [rsp+rax*4+1428h+var_1028], ecx\nmovzx eax, byte ptr [r9+rdx]\ntest al, al\njnz short loc_1518\nloc_1540:\nxor eax, eax\nxor ebp, ebp\nlea r12, [rsp+1428h+base]\nnop dword ptr [rax+00h]\nloc_1550:\nmov edx, [rsi+rax*4]\ntest edx, edx\njle short loc_1581\nmovd xmm1, dword ptr [r8+rax*4]\nmovsxd rcx, ebp\nmovd xmm0, edx\nadd ebp, 1\nlea rcx, [rcx+rcx*2]\nshl rcx, 2\npunpckldq xmm0, xmm1\nmov [rsp+rcx+1428h+base], al\nmovq qword ptr [r12+rcx+4], xmm0\nloc_1581:\nadd rax, 1\ncmp rax, 100h\njnz short loc_1550\nmovsxd rsi, ebp; nmemb\nlea rcx, compare; compar\nmov edx, 0Ch; size\nmov rdi, r12; base\ncall _qsort\nmovsxd rax, ebx\nlea rdi, [rax+rax*2]\nshl rdi, 2; size\ncall _malloc\ncmp ebp, ebx\ncmovg rbp, rbx\nmov rcx, rax\ntest ebp, ebp\njle short loc_15D8\nlea rdx, [rbp+rbp*2+0]\nmov rsi, r12; src\nmov rdi, rax; dest\nshl rdx, 2; n\ncall _memcpy\nmov rcx, rax\nloc_15D8:\nmov rax, [rsp+1428h+var_20]\nsub rax, fs:28h\njnz short loc_161D\nadd rsp, 1410h\nmov rax, rcx\npop rbx\npop rbp\npop r12\nretn\nloc_1600:\nmov [rsp+rax*4+1428h+var_1028], edx\nadd rdx, 1\nmovzx eax, byte ptr [r9+rdx]\ntest al, al\njnz loc_1518\njmp loc_1540\nloc_161D:\ncall ___stack_chk_fail", + "ida_pseudo": "void *__fastcall func0(unsigned __int8 *a1, int a2)\n{\n __int64 v2; // rdx\n __int64 i; // rax\n int v4; // ecx\n __int64 v5; // rax\n __int64 v6; // rbp\n signed int v7; // edx\n __int64 v8; // rcx\n unsigned __int64 v9; // xmm0_8\n void *v10; // rax\n void *v11; // rcx\n _DWORD v13[256]; // [rsp+0h] [rbp-1428h] BYREF\n _QWORD v14[128]; // [rsp+400h] [rbp-1028h] BYREF\n _BYTE base[3080]; // [rsp+800h] [rbp-C28h] BYREF\n unsigned __int64 v16; // [rsp+1408h] [rbp-20h]\n\n v2 = 0LL;\n v16 = __readfsqword(0x28u);\n memset(v13, 0, sizeof(v13));\n memset(v14, 0xFFu, sizeof(v14));\n for ( i = *a1; (_BYTE)i; i = a1[v2] )\n {\n while ( 1 )\n {\n v4 = *((_DWORD *)v14 + i);\n ++v13[i];\n if ( v4 == -1 )\n break;\n ++v2;\n *((_DWORD *)v14 + i) = v4;\n i = a1[v2];\n if ( !(_BYTE)i )\n goto LABEL_4;\n }\n *((_DWORD *)v14 + i) = v2++;\n }\nLABEL_4:\n v5 = 0LL;\n v6 = 0LL;\n do\n {\n v7 = v13[v5];\n if ( v7 > 0 )\n {\n v8 = (int)v6;\n v6 = (unsigned int)(v6 + 1);\n v8 *= 12LL;\n v9 = _mm_unpacklo_epi32(_mm_cvtsi32_si128(v7), _mm_cvtsi32_si128(*((_DWORD *)v14 + v5))).m128i_u64[0];\n base[v8] = v5;\n *(_QWORD *)&base[v8 + 4] = v9;\n }\n ++v5;\n }\n while ( v5 != 256 );\n qsort(base, (int)v6, 0xCuLL, compare);\n v10 = malloc(12LL * a2);\n if ( (int)v6 > a2 )\n v6 = (unsigned int)a2;\n v11 = v10;\n if ( (int)v6 > 0 )\n return memcpy(v10, base, 12 * v6);\n return v11;\n}", + "ida_strip_asm": "sub_14B0:\nendbr64\npush r12\npush rbp\npush rbx\nsub rsp, 1000h\nor [rsp+1018h+var_1018], 0\nsub rsp, 410h\nmov ecx, 80h\nxor edx, edx\nmov rax, fs:28h\nmov [rsp+1428h+var_20], rax\nxor eax, eax\nmov ebx, esi\nmov rsi, rsp\nmov r9, rdi\nlea r8, [rsp+1428h+var_1028]\nmov rdi, rsi\nrep stosq\nmov rax, 0FFFFFFFFFFFFFFFFh\nmov ecx, 80h\nmov rdi, r8\nrep stosq\nmovzx eax, byte ptr [r9]\ntest al, al\njz short loc_1540\nnop dword ptr [rax]\nloc_1518:\nmov ecx, [rsp+rax*4+1428h+var_1028]\nadd [rsp+rax*4+1428h+var_1428], 1\ncmp ecx, 0FFFFFFFFh\njz loc_1600\nadd rdx, 1\nmov [rsp+rax*4+1428h+var_1028], ecx\nmovzx eax, byte ptr [r9+rdx]\ntest al, al\njnz short loc_1518\nloc_1540:\nxor eax, eax\nxor ebp, ebp\nlea r12, [rsp+1428h+base]\nnop dword ptr [rax+00h]\nloc_1550:\nmov edx, [rsi+rax*4]\ntest edx, edx\njle short loc_1581\nmovd xmm1, dword ptr [r8+rax*4]\nmovsxd rcx, ebp\nmovd xmm0, edx\nadd ebp, 1\nlea rcx, [rcx+rcx*2]\nshl rcx, 2\npunpckldq xmm0, xmm1\nmov [rsp+rcx+1428h+base], al\nmovq qword ptr [r12+rcx+4], xmm0\nloc_1581:\nadd rax, 1\ncmp rax, 100h\njnz short loc_1550\nmovsxd rsi, ebp; nmemb\nlea rcx, compar; compar\nmov edx, 0Ch; size\nmov rdi, r12; base\ncall _qsort\nmovsxd rax, ebx\nlea rdi, [rax+rax*2]\nshl rdi, 2; size\ncall _malloc\ncmp ebp, ebx\ncmovg rbp, rbx\nmov rcx, rax\ntest ebp, ebp\njle short loc_15D8\nlea rdx, [rbp+rbp*2+0]\nmov rsi, r12; src\nmov rdi, rax; dest\nshl rdx, 2; n\ncall _memcpy\nmov rcx, rax\nloc_15D8:\nmov rax, [rsp+1428h+var_20]\nsub rax, fs:28h\njnz short loc_161D\nadd rsp, 1410h\nmov rax, rcx\npop rbx\npop rbp\npop r12\nretn\nloc_1600:\nmov [rsp+rax*4+1428h+var_1028], edx\nadd rdx, 1\nmovzx eax, byte ptr [r9+rdx]\ntest al, al\njnz loc_1518\njmp loc_1540\nloc_161D:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "void *__fastcall sub_14B0(unsigned __int8 *a1, int a2)\n{\n __int64 v2; // rdx\n __int64 i; // rax\n int v4; // ecx\n __int64 v5; // rax\n __int64 v6; // rbp\n signed int v7; // edx\n __int64 v8; // rcx\n unsigned __int64 v9; // xmm0_8\n void *v10; // rax\n void *v11; // rcx\n _DWORD v13[256]; // [rsp+0h] [rbp-1428h] BYREF\n _QWORD v14[128]; // [rsp+400h] [rbp-1028h] BYREF\n _BYTE base[3080]; // [rsp+800h] [rbp-C28h] BYREF\n unsigned __int64 v16; // [rsp+1408h] [rbp-20h]\n\n v2 = 0LL;\n v16 = __readfsqword(0x28u);\n memset(v13, 0, sizeof(v13));\n memset(v14, 0xFFu, sizeof(v14));\n for ( i = *a1; (_BYTE)i; i = a1[v2] )\n {\n while ( 1 )\n {\n v4 = *((_DWORD *)v14 + i);\n ++v13[i];\n if ( v4 == -1 )\n break;\n ++v2;\n *((_DWORD *)v14 + i) = v4;\n i = a1[v2];\n if ( !(_BYTE)i )\n goto LABEL_4;\n }\n *((_DWORD *)v14 + i) = v2++;\n }\nLABEL_4:\n v5 = 0LL;\n v6 = 0LL;\n do\n {\n v7 = v13[v5];\n if ( v7 > 0 )\n {\n v8 = (int)v6;\n v6 = (unsigned int)(v6 + 1);\n v8 *= 12LL;\n v9 = _mm_unpacklo_epi32(_mm_cvtsi32_si128(v7), _mm_cvtsi32_si128(*((_DWORD *)v14 + v5))).m128i_u64[0];\n base[v8] = v5;\n *(_QWORD *)&base[v8 + 4] = v9;\n }\n ++v5;\n }\n while ( v5 != 256 );\n qsort(base, (int)v6, 0xCuLL, compar);\n v10 = malloc(12LL * a2);\n if ( (int)v6 > a2 )\n v6 = (unsigned int)a2;\n v11 = v10;\n if ( (int)v6 > 0 )\n return memcpy(v10, base, 12 * v6);\n return v11;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_14B0(unsigned char *a1, int a2) {\n long long v2;\n long long i;\n int v4;\n long long v5;\n long long v6;\n signed int v7;\n long long v8;\n unsigned long long v9;\n void *v10;\n void *v11;\n uint32_t v13[256];\n uint64_t v14[128];\n uint8_t base[3080];\n unsigned long long v16;\n v2 = 0LL;\n v16 = __readfsqword(40u);\n memset(v13, 0, sizeof(v13));\n memset(v14, 255u, sizeof(v14));\n for (i = *a1; (uint8_t)i; i = a1[v2]) {\n while (1) {\n v4 = *((uint32_t *)v14 + i);\n ++v13[i];\n if (v4 == -1) break;\n ++v2;\n *((uint32_t *)v14 + i) = v4;\n i = a1[v2];\n if (!(uint8_t)i) goto LABEL_4;\n }\n *((uint32_t *)v14 + i) = v2++;\n }\nLABEL_4:\n v5 = 0LL;\n v6 = 0LL;\n do {\n v7 = v13[v5];\n if (v7 > 0) {\n v8 = (int)v6;\n v6 = (unsigned int)(v6 + 1);\n v8 *= 12LL;\n v9 = _mm_unpacklo_epi32(_mm_cvtsi32_si128(v7),\n _mm_cvtsi32_si128(*((uint32_t *)v14 + v5)))\n .m128i_u64[0];\n base[v8] = v5;\n *(uint64_t *)&base[v8 + 4] = v9;\n }\n ++v5;\n } while (v5 != 256);\n qsort(base, (int)v6, 12uLL, compar);\n v10 = malloc(12LL * a2);\n if ((int)v6 > a2) v6 = (unsigned int)a2;\n v11 = v10;\n if ((int)v6 > 0) return memcpy(v10, base, 12 * v6);\n return v11;\n}", + "ida_pseudo_norm": "void *func0(unsigned char *a1, int a2) {\n long long v2;\n long long i;\n int v4;\n long long v5;\n long long v6;\n signed int v7;\n long long v8;\n unsigned long long v9;\n void *v10;\n void *v11;\n uint32_t v13[256];\n uint64_t v14[128];\n uint8_t base[3080];\n unsigned long long v16;\n v2 = 0LL;\n v16 = __readfsqword(40u);\n memset(v13, 0, sizeof(v13));\n memset(v14, 255u, sizeof(v14));\n for (i = *a1; (uint8_t)i; i = a1[v2]) {\n while (1) {\n v4 = *((uint32_t *)v14 + i);\n ++v13[i];\n if (v4 == -1) break;\n ++v2;\n *((uint32_t *)v14 + i) = v4;\n i = a1[v2];\n if (!(uint8_t)i) goto LABEL_4;\n }\n *((uint32_t *)v14 + i) = v2++;\n }\nLABEL_4:\n v5 = 0LL;\n v6 = 0LL;\n do {\n v7 = v13[v5];\n if (v7 > 0) {\n v8 = (int)v6;\n v6 = (unsigned int)(v6 + 1);\n v8 *= 12LL;\n v9 = _mm_unpacklo_epi32(_mm_cvtsi32_si128(v7),\n _mm_cvtsi32_si128(*((uint32_t *)v14 + v5)))\n .m128i_u64[0];\n base[v8] = v5;\n *(uint64_t *)&base[v8 + 4] = v9;\n }\n ++v5;\n } while (v5 != 256);\n qsort(base, (int)v6, 12uLL, compare);\n v10 = malloc(12LL * a2);\n if ((int)v6 > a2) v6 = (unsigned int)a2;\n v11 = v10;\n if ((int)v6 > 0) return memcpy(v10, base, 12 * v6);\n return v11;\n}" + }, + { + "index": 947, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char *list1[], int n) {\n int min = strlen(list1[0]);\n for (int i = 0; i < n; i++) {\n if (strlen(list1[i]) < min) {\n min = strlen(list1[i]);\n }\n }\n return min;\n}", + "test": "int main() {\n\n char *list1[] = {\"win\", \"lose\", \"great\"};\n\n char *list2[] = {\"a\", \"ab\", \"abc\"};\n\n char *list3[] = {\"12\", \"12\", \"1234\"};\n\n\n\n assert(func0(list1, 3) == 3);\n\n assert(func0(list2, 3) == 1);\n\n assert(func0(list3, 3) == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov -0x18(%rbp),%rax\nmov (%rax),%rax\nmov %rax,%rdi\ncallq 1070 \nmov %eax,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 1207 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov %rax,%rdi\ncallq 1070 \nmov -0x8(%rbp),%edx\nmovslq %edx,%rdx\ncmp %rdx,%rax\njae 1203 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov %rax,%rdi\ncallq 1070 \nmov %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11b7 \nmov -0x8(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov rax, [rbp+var_18]\nmov rax, [rax]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_8], eax\nmov [rbp+var_4], 0\njmp short loc_1209\nloc_11B7:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov eax, [rbp+var_8]\ncdqe\ncmp rdx, rax\njnb short loc_1205\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_8], eax\nloc_1205:\nadd [rbp+var_4], 1\nloc_1209:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11B7\nmov eax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char **a1, int a2)\n{\n unsigned int v3; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v3 = strlen(*a1);\n for ( i = 0; i < a2; ++i )\n {\n if ( strlen(a1[i]) < (int)v3 )\n v3 = strlen(a1[i]);\n }\n return v3;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov rax, [rbp+var_18]\nmov rax, [rax]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_8], eax\nmov [rbp+var_4], 0\njmp short loc_1209\nloc_11B7:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nmov eax, [rbp+var_8]\ncdqe\ncmp rdx, rax\njnb short loc_1205\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_8], eax\nloc_1205:\nadd [rbp+var_4], 1\nloc_1209:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_11B7\nmov eax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(const char **a1, int a2)\n{\n unsigned int v3; // [rsp+18h] [rbp-8h]\n int i; // [rsp+1Ch] [rbp-4h]\n\n v3 = strlen(*a1);\n for ( i = 0; i < a2; ++i )\n {\n if ( strlen(a1[i]) < (int)v3 )\n v3 = strlen(a1[i]);\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(const char **a1, int a2) {\n unsigned int v3;\n int i;\n v3 = strlen(*a1);\n for (i = 0; i < a2; ++i) {\n if (strlen(a1[i]) < (int)v3) v3 = strlen(a1[i]);\n }\n return v3;\n}", + "ida_pseudo_norm": "long long func0(const char **a1, int a2) {\n unsigned int v3;\n int i;\n v3 = strlen(*a1);\n for (i = 0; i < a2; ++i) {\n if (strlen(a1[i]) < (int)v3) v3 = strlen(a1[i]);\n }\n return v3;\n}" + }, + { + "index": 947, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char *list1[], int n) {\n int min = strlen(list1[0]);\n for (int i = 0; i < n; i++) {\n if (strlen(list1[i]) < min) {\n min = strlen(list1[i]);\n }\n }\n return min;\n}", + "test": "int main() {\n\n char *list1[] = {\"win\", \"lose\", \"great\"};\n\n char *list2[] = {\"a\", \"ab\", \"abc\"};\n\n char *list3[] = {\"12\", \"12\", \"1234\"};\n\n\n\n assert(func0(list1, 3) == 3);\n\n assert(func0(list2, 3) == 1);\n\n assert(func0(list3, 3) == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nmov %rdi,%r9\nmov (%rdi),%rdi\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nlea -0x1(%rcx),%r8d\ntest %esi,%esi\njle 11c5 \nmov %r9,%rdx\nlea -0x1(%rsi),%eax\nlea 0x8(%r9,%rax,8),%r10\nmov $0xffffffffffffffff,%r9\nmov $0x0,%eax\nmov (%rdx),%rdi\nmov %r9,%rcx\nrepnz scas %es:(%rdi),%al\nnot %rcx\nsub $0x1,%rcx\nmovslq %r8d,%rsi\ncmp %rsi,%rcx\ncmovb %ecx,%r8d\nadd $0x8,%rdx\ncmp %r10,%rdx\njne 11a3 \nmov %r8d,%eax\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r13, rdi\nmov r12d, esi\nmov rdi, [rdi]; s\ncall _strlen\nmov ebp, eax\ntest r12d, r12d\njle short loc_11D1\nmov rbx, r13\nmovsxd r12, r12d\nlea r12, [r13+r12*8+0]\nloc_11B7:\nmov rdi, [rbx]; s\ncall _strlen\nmovsxd rdx, ebp\ncmp rax, rdx\ncmovb ebp, eax\nadd rbx, 8\ncmp rbx, r12\njnz short loc_11B7\nloc_11D1:\nmov eax, ebp\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char **a1, int a2)\n{\n unsigned int v2; // ebp\n const char **v3; // rbx\n size_t v4; // rax\n\n v2 = strlen(*a1);\n if ( a2 > 0 )\n {\n v3 = a1;\n do\n {\n v4 = strlen(*v3);\n if ( v4 < (int)v2 )\n v2 = v4;\n ++v3;\n }\n while ( v3 != &a1[a2] );\n }\n return v2;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov r13, rdi\nmov r12d, esi\nmov rdi, [rdi]; s\ncall _strlen\nmov ebp, eax\ntest r12d, r12d\njle short loc_11D1\nmov rbx, r13\nmovsxd r12, r12d\nlea r12, [r13+r12*8+0]\nloc_11B7:\nmov rdi, [rbx]; s\ncall _strlen\nmovsxd rdx, ebp\ncmp rax, rdx\ncmovb ebp, eax\nadd rbx, 8\ncmp rbx, r12\njnz short loc_11B7\nloc_11D1:\nmov eax, ebp\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(const char **a1, int a2)\n{\n unsigned int v2; // ebp\n const char **v3; // rbx\n size_t v4; // rax\n\n v2 = strlen(*a1);\n if ( a2 > 0 )\n {\n v3 = a1;\n do\n {\n v4 = strlen(*v3);\n if ( v4 < (int)v2 )\n v2 = v4;\n ++v3;\n }\n while ( v3 != &a1[a2] );\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(const char **a1, int a2) {\n unsigned int v2;\n const char **v3;\n unsigned int v4;\n v2 = strlen(*a1);\n if (a2 > 0) {\n v3 = a1;\n do {\n v4 = strlen(*v3);\n if (v4 < (int)v2) v2 = v4;\n ++v3;\n } while (v3 != &a1[a2]);\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(const char **a1, int a2) {\n unsigned int v2;\n const char **v3;\n unsigned int v4;\n v2 = strlen(*a1);\n if (a2 > 0) {\n v3 = a1;\n do {\n v4 = strlen(*v3);\n if (v4 < (int)v2) v2 = v4;\n ++v3;\n } while (v3 != &a1[a2]);\n }\n return v2;\n}" + }, + { + "index": 947, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char *list1[], int n) {\n int min = strlen(list1[0]);\n for (int i = 0; i < n; i++) {\n if (strlen(list1[i]) < min) {\n min = strlen(list1[i]);\n }\n }\n return min;\n}", + "test": "int main() {\n\n char *list1[] = {\"win\", \"lose\", \"great\"};\n\n char *list2[] = {\"a\", \"ab\", \"abc\"};\n\n char *list3[] = {\"12\", \"12\", \"1234\"};\n\n\n\n assert(func0(list1, 3) == 3);\n\n assert(func0(list2, 3) == 1);\n\n assert(func0(list3, 3) == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\nmov %esi,%ebp\npush %rbx\nmov %rdi,%rbx\nmov (%rdi),%rdi\ncallq 1070 \nmov %eax,%r12d\ntest %ebp,%ebp\njle 130b \nadd $0x8,%rbx\nlea -0x1(%rbp),%edx\nlea (%rbx,%rdx,8),%rbp\njmp 12fc \nnopl 0x0(%rax)\nmov (%rbx),%rdi\nadd $0x8,%rbx\ncallq 1070 \nmovslq %r12d,%rdx\ncmp %rax,%rdx\ncmova %eax,%r12d\ncmp %rbp,%rbx\njne 12f0 \nmov %r12d,%eax\npop %rbx\npop %rbp\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r12\nmovsxd r12, esi\npush rbp\npush rbx\nmov rbx, rdi\nmov rdi, [rdi]; s\ncall _strlen\nmov ebp, eax\ntest r12d, r12d\njle short loc_1322\nlea r12, [rbx+r12*8]\njmp short loc_1310\nloc_1308:\nmov rdi, [rbx]; s\ncall _strlen\nloc_1310:\nmovsxd rdx, ebp\ncmp rax, rdx\ncmovb ebp, eax\nadd rbx, 8\ncmp rbx, r12\njnz short loc_1308\nloc_1322:\nmov eax, ebp\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char **a1, int a2)\n{\n const char **v2; // rbx\n size_t v3; // rax\n unsigned int v4; // ebp\n\n v2 = a1;\n v3 = strlen(*a1);\n v4 = v3;\n if ( a2 > 0 )\n {\n while ( 1 )\n {\n if ( v3 < (int)v4 )\n v4 = v3;\n if ( ++v2 == &a1[a2] )\n break;\n v3 = strlen(*v2);\n }\n }\n return v4;\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\npush r12\nmovsxd r12, esi\npush rbp\npush rbx\nmov rbx, rdi\nmov rdi, [rdi]; s\ncall _strlen\nmov ebp, eax\ntest r12d, r12d\njle short loc_1322\nlea r12, [rbx+r12*8]\njmp short loc_1310\nloc_1308:\nmov rdi, [rbx]; s\ncall _strlen\nloc_1310:\nmovsxd rdx, ebp\ncmp rax, rdx\ncmovb ebp, eax\nadd rbx, 8\ncmp rbx, r12\njnz short loc_1308\nloc_1322:\nmov eax, ebp\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12E0(const char **a1, int a2)\n{\n const char **v2; // rbx\n size_t v3; // rax\n unsigned int v4; // ebp\n\n v2 = a1;\n v3 = strlen(*a1);\n v4 = v3;\n if ( a2 > 0 )\n {\n while ( 1 )\n {\n if ( v3 < (int)v4 )\n v4 = v3;\n if ( ++v2 == &a1[a2] )\n break;\n v3 = strlen(*v2);\n }\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12E0(const char **a1, int a2) {\n const char **v2;\n unsigned int v3;\n unsigned int v4;\n v2 = a1;\n v3 = strlen(*a1);\n v4 = v3;\n if (a2 > 0) {\n while (1) {\n if (v3 < (int)v4) v4 = v3;\n if (++v2 == &a1[a2]) break;\n v3 = strlen(*v2);\n }\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(const char **a1, int a2) {\n const char **v2;\n unsigned int v3;\n unsigned int v4;\n v2 = a1;\n v3 = strlen(*a1);\n v4 = v3;\n if (a2 > 0) {\n while (1) {\n if (v3 < (int)v4) v4 = v3;\n if (++v2 == &a1[a2]) break;\n v3 = strlen(*v2);\n }\n }\n return v4;\n}" + }, + { + "index": 947, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char *list1[], int n) {\n int min = strlen(list1[0]);\n for (int i = 0; i < n; i++) {\n if (strlen(list1[i]) < min) {\n min = strlen(list1[i]);\n }\n }\n return min;\n}", + "test": "int main() {\n\n char *list1[] = {\"win\", \"lose\", \"great\"};\n\n char *list2[] = {\"a\", \"ab\", \"abc\"};\n\n char *list3[] = {\"12\", \"12\", \"1234\"};\n\n\n\n assert(func0(list1, 3) == 3);\n\n assert(func0(list2, 3) == 1);\n\n assert(func0(list3, 3) == 2);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\nmov %esi,%ebp\npush %rbx\nmov %rdi,%rbx\nmov (%rdi),%rdi\ncallq 1070 \nmov %eax,%r12d\ntest %ebp,%ebp\njle 132b \nadd $0x8,%rbx\nlea -0x1(%rbp),%edx\nlea (%rbx,%rdx,8),%rbp\njmp 131c \nnopl 0x0(%rax)\nmov (%rbx),%rdi\nadd $0x8,%rbx\ncallq 1070 \nmovslq %r12d,%rdx\ncmp %rax,%rdx\ncmova %eax,%r12d\ncmp %rbp,%rbx\njne 1310 \nmov %r12d,%eax\npop %rbx\npop %rbp\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r12\nmovsxd r12, esi\npush rbp\npush rbx\nmov rbx, rdi\nmov rdi, [rdi]; s\ncall _strlen\nmov ebp, eax\ntest r12d, r12d\njle short loc_1322\nlea r12, [rbx+r12*8]\njmp short loc_1310\nloc_1308:\nmov rdi, [rbx]; s\ncall _strlen\nloc_1310:\nmovsxd rdx, ebp\ncmp rax, rdx\ncmovb ebp, eax\nadd rbx, 8\ncmp rbx, r12\njnz short loc_1308\nloc_1322:\nmov eax, ebp\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char **a1, int a2)\n{\n const char **v2; // rbx\n size_t v3; // rax\n unsigned int v4; // ebp\n\n v2 = a1;\n v3 = strlen(*a1);\n v4 = v3;\n if ( a2 > 0 )\n {\n while ( 1 )\n {\n if ( v3 < (int)v4 )\n v4 = v3;\n if ( ++v2 == &a1[a2] )\n break;\n v3 = strlen(*v2);\n }\n }\n return v4;\n}", + "ida_strip_asm": "sub_12E0:\nendbr64\npush r12\nmovsxd r12, esi\npush rbp\npush rbx\nmov rbx, rdi\nmov rdi, [rdi]; s\ncall _strlen\nmov ebp, eax\ntest r12d, r12d\njle short loc_1322\nlea r12, [rbx+r12*8]\njmp short loc_1310\nloc_1308:\nmov rdi, [rbx]; s\ncall _strlen\nloc_1310:\nmovsxd rdx, ebp\ncmp rax, rdx\ncmovb ebp, eax\nadd rbx, 8\ncmp rbx, r12\njnz short loc_1308\nloc_1322:\nmov eax, ebp\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_12E0(const char **a1, int a2)\n{\n const char **v2; // rbx\n size_t v3; // rax\n unsigned int v4; // ebp\n\n v2 = a1;\n v3 = strlen(*a1);\n v4 = v3;\n if ( a2 > 0 )\n {\n while ( 1 )\n {\n if ( v3 < (int)v4 )\n v4 = v3;\n if ( ++v2 == &a1[a2] )\n break;\n v3 = strlen(*v2);\n }\n }\n return v4;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12E0(const char **a1, int a2) {\n const char **v2;\n unsigned int v3;\n unsigned int v4;\n v2 = a1;\n v3 = strlen(*a1);\n v4 = v3;\n if (a2 > 0) {\n while (1) {\n if (v3 < (int)v4) v4 = v3;\n if (++v2 == &a1[a2]) break;\n v3 = strlen(*v2);\n }\n }\n return v4;\n}", + "ida_pseudo_norm": "long long func0(const char **a1, int a2) {\n const char **v2;\n unsigned int v3;\n unsigned int v4;\n v2 = a1;\n v3 = strlen(*a1);\n v4 = v3;\n if (a2 > 0) {\n while (1) {\n if (v3 < (int)v4) v4 = v3;\n if (++v2 == &a1[a2]) break;\n v3 = strlen(*v2);\n }\n }\n return v4;\n}" + }, + { + "index": 948, + "func_name": "func0", + "func_dep": "#include \n\n\n\n", + "func": "char func0(char tup1[], int index, int size) {\n if (index < 0) {\n index = size + index;\n }\n return tup1[index];\n}", + "test": "int main() {\n\n char tuple1[] = {'w', 3, 'r', 'e', 's', 'o', 'u', 'r', 'c', 'e'};\n\n int size = sizeof(tuple1) / sizeof(tuple1[0]);\n\n\n\n assert(func0(tuple1, 3, size) == 'e');\n\n assert(func0(tuple1, -4, size) == 'u');\n\n assert(func0(tuple1, -3, size) == 'r');\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x8(%rbp)\nmov %esi,-0xc(%rbp)\nmov %edx,-0x10(%rbp)\ncmpl $0x0,-0xc(%rbp)\njns 1187 \nmov -0x10(%rbp),%eax\nadd %eax,-0xc(%rbp)\nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_8], rdi\nmov [rbp+var_C], esi\nmov [rbp+var_10], edx\ncmp [rbp+var_C], 0\njns short loc_1187\nmov eax, [rbp+var_10]\nadd [rbp+var_C], eax\nloc_1187:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2, int a3)\n{\n int v4; // [rsp+4h] [rbp-Ch]\n\n v4 = a2;\n if ( a2 < 0 )\n v4 = a3 + a2;\n return *(unsigned __int8 *)(v4 + a1);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_8], rdi\nmov [rbp+var_C], esi\nmov [rbp+var_10], edx\ncmp [rbp+var_C], 0\njns short loc_1187\nmov eax, [rbp+var_10]\nadd [rbp+var_C], eax\nloc_1187:\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1, int a2, int a3)\n{\n int v4; // [rsp+4h] [rbp-Ch]\n\n v4 = a2;\n if ( a2 < 0 )\n v4 = a3 + a2;\n return *(unsigned __int8 *)(v4 + a1);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1, int a2, int a3) {\n int v4;\n v4 = a2;\n if (a2 < 0) v4 = a3 + a2;\n return *(unsigned char *)(v4 + a1);\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2, int a3) {\n int v4;\n v4 = a2;\n if (a2 < 0) v4 = a3 + a2;\n return *(unsigned char *)(v4 + a1);\n}" + }, + { + "index": 949, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n// Define a tuple structure\n\ntypedef struct {\n\n int *elements;\n\n int size;\n\n} Tuple;\n\n\n\n// Function to count the total number of digits in a tuple\n\nint count_digs(Tuple tup) {\n\n int total = 0;\n\n for(int i = 0; i < tup.size; i++) {\n\n int num = tup.elements[i];\n\n if(num == 0) {\n\n total += 1;\n\n } else {\n\n while(num != 0) {\n\n total += 1;\n\n num /= 10;\n\n }\n\n }\n\n }\n\n return total;\n\n}\n\n\n\n// Comparison function for sorting tuples based on digit count\n\nint compare_tuples(const void *a, const void *b) {\n\n Tuple *tupA = (Tuple *)a;\n\n Tuple *tupB = (Tuple *)b;\n\n int countA = count_digs(*tupA);\n\n int countB = count_digs(*tupB);\n\n return countA - countB;\n\n}\n\n\n\n// Function to convert the sorted list of tuples to a string\n\n", + "func": "char* func0(Tuple* list, int list_size) {\n qsort(list, list_size, sizeof(Tuple), compare_tuples);\n static char result[1000];\n result[0] = '\\0';\n strcat(result, \"[\");\n for (int i = 0; i < list_size; i++) {\n strcat(result, \"(\");\n for (int j = 0; j < list[i].size; j++) {\n char num_str[20];\n sprintf(num_str, \"%d\", list[i].elements[j]);\n strcat(result, num_str);\n if (j < list[i].size - 1) {\n strcat(result, \", \");\n }\n }\n strcat(result, \")\");\n if (i < list_size - 1) {\n strcat(result, \", \");\n }\n }\n strcat(result, \"]\");\n return result;\n}", + "test": "int main() {\n\n // First test case\n\n Tuple list1[4];\n\n int elems1_0[] = {3, 4, 6, 723};\n\n list1[0].elements = elems1_0;\n\n list1[0].size = 4;\n\n int elems1_1[] = {1, 2};\n\n list1[1].elements = elems1_1;\n\n list1[1].size = 2;\n\n int elems1_2[] = {12345};\n\n list1[2].elements = elems1_2;\n\n list1[2].size = 1;\n\n int elems1_3[] = {134, 234, 34};\n\n list1[3].elements = elems1_3;\n\n list1[3].size = 3;\n\n assert(strcmp(func0(list1, 4), \"[(1, 2), (12345), (3, 4, 6, 723), (134, 234, 34)]\") == 0);\n\n\n\n // Second test case\n\n Tuple list2[4];\n\n int elems2_0[] = {3, 4, 8};\n\n list2[0].elements = elems2_0;\n\n list2[0].size = 3;\n\n int elems2_1[] = {1, 2};\n\n list2[1].elements = elems2_1;\n\n list2[1].size = 2;\n\n int elems2_2[] = {1234335};\n\n list2[2].elements = elems2_2;\n\n list2[2].size = 1;\n\n int elems2_3[] = {1345, 234, 334};\n\n list2[3].elements = elems2_3;\n\n list2[3].size = 3;\n\n assert(strcmp(func0(list2, 4), \"[(1, 2), (3, 4, 8), (1234335), (1345, 234, 334)]\") == 0);\n\n\n\n // Third test case\n\n Tuple list3[4];\n\n int elems3_0[] = {34, 4, 61, 723};\n\n list3[0].elements = elems3_0;\n\n list3[0].size = 4;\n\n int elems3_1[] = {1, 2};\n\n list3[1].elements = elems3_1;\n\n list3[1].size = 2;\n\n int elems3_2[] = {145};\n\n list3[2].elements = elems3_2;\n\n list3[2].size = 1;\n\n int elems3_3[] = {134, 23};\n\n list3[3].elements = elems3_3;\n\n list3[3].size = 2;\n\n assert(strcmp(func0(list3, 4), \"[(1, 2), (145), (134, 23), (34, 4, 61, 723)]\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x40,%rsp\nmov %rdi,-0x38(%rbp)\nmov %esi,-0x3c(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmov -0x3c(%rbp),%eax\nmovslq %eax,%rsi\nmov -0x38(%rbp),%rax\nlea -0x91(%rip),%rcx\nmov $0x10,%edx\nmov %rax,%rdi\ncallq 10a0 \nmovb $0x0,0x2d2e(%rip)\nlea 0x2d27(%rip),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nlea 0x2d02(%rip),%rax\nadd %rdx,%rax\nmovw $0x5b,(%rax)\nmovl $0x0,-0x28(%rbp)\njmpq 14d6 \nlea 0x2ce7(%rip),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nlea 0x2cc2(%rip),%rax\nadd %rdx,%rax\nmovw $0x28,(%rax)\nmovl $0x0,-0x24(%rbp)\njmpq 143c \nmov -0x28(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0x24(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x2,%rdx\nadd %rdx,%rax\nmov (%rax),%edx\nlea -0x20(%rbp),%rax\nlea 0xc46(%rip),%rsi\nmov %rax,%rdi\nmov $0x0,%eax\ncallq 10f0 \nlea -0x20(%rbp),%rax\nmov %rax,%rsi\nlea 0x2c63(%rip),%rdi\ncallq 10e0 \nmov -0x28(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov 0x8(%rax),%eax\nsub $0x1,%eax\ncmp %eax,-0x24(%rbp)\njge 1438 \nlea 0x2c39(%rip),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nlea 0x2c14(%rip),%rax\nadd %rdx,%rax\nmovw $0x202c,(%rax)\nmovb $0x0,0x2(%rax)\naddl $0x1,-0x24(%rbp)\nmov -0x28(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov 0x8(%rax),%eax\ncmp %eax,-0x24(%rbp)\njl 1392 \nlea 0x2bde(%rip),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nlea 0x2bb9(%rip),%rax\nadd %rdx,%rax\nmovw $0x29,(%rax)\nmov -0x3c(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x28(%rbp)\njge 14d2 \nlea 0x2b9f(%rip),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nlea 0x2b7a(%rip),%rax\nadd %rdx,%rax\nmovw $0x202c,(%rax)\nmovb $0x0,0x2(%rax)\naddl $0x1,-0x28(%rbp)\nmov -0x28(%rbp),%eax\ncmp -0x3c(%rbp),%eax\njl 1352 \nlea 0x2b57(%rip),%rax\nmov $0xffffffffffffffff,%rcx\nmov %rax,%rdx\nmov $0x0,%eax\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nlea -0x1(%rax),%rdx\nlea 0x2b32(%rip),%rax\nadd %rdx,%rax\nmovw $0x5d,(%rax)\nlea 0x2b23(%rip),%rax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 1531 \ncallq 10b0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+base], rdi\nmov [rbp+var_3C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov eax, [rbp+var_3C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compare_tuples\nmov rcx, rdx; compar\nmov edx, 10h; size\nmov rdi, rax; base\ncall _qsort\nmov cs:result_1, 0\nlea rax, result_1\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nlea rax, result_1\nadd rax, rdx\nmov word ptr [rax], 5Bh ; '['\nmov [rbp+var_28], 0\njmp loc_14A0\nloc_1362:\nlea rax, result_1\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nlea rax, result_1\nadd rax, rdx\nmov word ptr [rax], 28h ; '('\nmov [rbp+var_24], 0\njmp loc_142C\nloc_138F:\nmov eax, [rbp+var_28]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+base]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov edx, [rax]\nlea rax, [rbp+s]\nlea rcx, format; \"%d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rax, [rbp+s]\nmov rsi, rax; src\nlea rax, result_1\nmov rdi, rax; dest\ncall _strcat\nmov eax, [rbp+var_28]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+base]\nadd rax, rdx\nmov eax, [rax+8]\nsub eax, 1\ncmp [rbp+var_24], eax\njge short loc_1428\nlea rax, result_1\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nlea rax, result_1\nadd rax, rdx\nmov word ptr [rax], 202Ch\nmov byte ptr [rax+2], 0\nloc_1428:\nadd [rbp+var_24], 1\nloc_142C:\nmov eax, [rbp+var_28]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+base]\nadd rax, rdx\nmov eax, [rax+8]\ncmp [rbp+var_24], eax\njl loc_138F\nlea rax, result_1\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nlea rax, result_1\nadd rax, rdx\nmov word ptr [rax], 29h ; ')'\nmov eax, [rbp+var_3C]\nsub eax, 1\ncmp [rbp+var_28], eax\njge short loc_149C\nlea rax, result_1\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nlea rax, result_1\nadd rax, rdx\nmov word ptr [rax], 202Ch\nmov byte ptr [rax+2], 0\nloc_149C:\nadd [rbp+var_28], 1\nloc_14A0:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_3C]\njl loc_1362\nlea rax, result_1\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nlea rax, result_1\nadd rax, rdx\nmov word ptr [rax], 5Dh ; ']'\nlea rax, result_1\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_14E8\ncall ___stack_chk_fail\nlocret_14E8:\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(void *a1, int a2)\n{\n int i; // [rsp+18h] [rbp-28h]\n int j; // [rsp+1Ch] [rbp-24h]\n char s[24]; // [rsp+20h] [rbp-20h] BYREF\n unsigned __int64 v6; // [rsp+38h] [rbp-8h]\n\n v6 = __readfsqword(0x28u);\n qsort(a1, a2, 0x10uLL, compare_tuples);\n result_1[0] = 0;\n *(_WORD *)&result_1[strlen(result_1)] = 91;\n for ( i = 0; i < a2; ++i )\n {\n *(_WORD *)&result_1[strlen(result_1)] = 40;\n for ( j = 0; j < *((_DWORD *)a1 + 4 * i + 2); ++j )\n {\n sprintf(s, \"%d\", *(_DWORD *)(4LL * j + *((_QWORD *)a1 + 2 * i)));\n strcat(result_1, s);\n if ( j < *((_DWORD *)a1 + 4 * i + 2) - 1 )\n strcpy(&result_1[strlen(result_1)], \", \");\n }\n *(_WORD *)&result_1[strlen(result_1)] = 41;\n if ( i < a2 - 1 )\n strcpy(&result_1[strlen(result_1)], \", \");\n }\n *(_WORD *)&result_1[strlen(result_1)] = 93;\n return result_1;\n}", + "ida_strip_asm": "sub_12EB:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+base], rdi\nmov [rbp+var_3C], esi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov eax, [rbp+var_3C]\nmovsxd rsi, eax; nmemb\nmov rax, [rbp+base]\nlea rdx, compar\nmov rcx, rdx; compar\nmov edx, 10h; size\nmov rdi, rax; base\ncall _qsort\nmov cs:s, 0\nlea rax, s\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nlea rax, s\nadd rax, rdx\nmov word ptr [rax], 5Bh ; '['\nmov [rbp+var_28], 0\njmp loc_14A0\nloc_1362:\nlea rax, s\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nlea rax, s\nadd rax, rdx\nmov word ptr [rax], 28h ; '('\nmov [rbp+var_24], 0\njmp loc_142C\nloc_138F:\nmov eax, [rbp+var_28]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+base]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov edx, [rax]\nlea rax, [rbp+s]\nlea rcx, format; \"%d\"\nmov rsi, rcx; format\nmov rdi, rax; s\nmov eax, 0\ncall _sprintf\nlea rax, [rbp+s]\nmov rsi, rax; src\nlea rax, s\nmov rdi, rax; dest\ncall _strcat\nmov eax, [rbp+var_28]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+base]\nadd rax, rdx\nmov eax, [rax+8]\nsub eax, 1\ncmp [rbp+var_24], eax\njge short loc_1428\nlea rax, s\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nlea rax, s\nadd rax, rdx\nmov word ptr [rax], 202Ch\nmov byte ptr [rax+2], 0\nloc_1428:\nadd [rbp+var_24], 1\nloc_142C:\nmov eax, [rbp+var_28]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+base]\nadd rax, rdx\nmov eax, [rax+8]\ncmp [rbp+var_24], eax\njl loc_138F\nlea rax, s\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nlea rax, s\nadd rax, rdx\nmov word ptr [rax], 29h ; ')'\nmov eax, [rbp+var_3C]\nsub eax, 1\ncmp [rbp+var_28], eax\njge short loc_149C\nlea rax, s\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nlea rax, s\nadd rax, rdx\nmov word ptr [rax], 202Ch\nmov byte ptr [rax+2], 0\nloc_149C:\nadd [rbp+var_28], 1\nloc_14A0:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_3C]\njl loc_1362\nlea rax, s\nmov rdi, rax; s\ncall _strlen\nmov rdx, rax\nlea rax, s\nadd rax, rdx\nmov word ptr [rax], 5Dh ; ']'\nlea rax, s\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_14E8\ncall ___stack_chk_fail\nlocret_14E8:\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_12EB(void *a1, int a2)\n{\n int i; // [rsp+18h] [rbp-28h]\n int j; // [rsp+1Ch] [rbp-24h]\n char s[24]; // [rsp+20h] [rbp-20h] BYREF\n unsigned __int64 v6; // [rsp+38h] [rbp-8h]\n\n v6 = __readfsqword(0x28u);\n qsort(a1, a2, 0x10uLL, compar);\n ::s[0] = 0;\n *(_WORD *)&::s[strlen(::s)] = 91;\n for ( i = 0; i < a2; ++i )\n {\n *(_WORD *)&::s[strlen(::s)] = 40;\n for ( j = 0; j < *((_DWORD *)a1 + 4 * i + 2); ++j )\n {\n sprintf(s, \"%d\", *(_DWORD *)(4LL * j + *((_QWORD *)a1 + 2 * i)));\n strcat(::s, s);\n if ( j < *((_DWORD *)a1 + 4 * i + 2) - 1 )\n strcpy(&::s[strlen(::s)], \", \");\n }\n *(_WORD *)&::s[strlen(::s)] = 41;\n if ( i < a2 - 1 )\n strcpy(&::s[strlen(::s)], \", \");\n }\n *(_WORD *)&::s[strlen(::s)] = 93;\n return ::s;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_12EB(void *a1, int a2) {\n int i;\n int j;\n char s[24];\n unsigned long long v6;\n v6 = __readfsqword(40u);\n qsort(a1, a2, 16uLL, compar);\n ::s[0] = 0;\n *(unsigned short *)&::s[strlen(::s)] = 91;\n for (i = 0; i < a2; ++i) {\n *(unsigned short *)&::s[strlen(::s)] = 40;\n for (j = 0; j < *((uint32_t *)a1 + 4 * i + 2); ++j) {\n sprintf(s, \"%d\", *(uint32_t *)(4LL * j + *((uint64_t *)a1 + 2 * i)));\n strcat(::s, s);\n if (j < *((uint32_t *)a1 + 4 * i + 2) - 1)\n strcpy(&::s[strlen(::s)], \", \");\n }\n *(unsigned short *)&::s[strlen(::s)] = 41;\n if (i < a2 - 1) strcpy(&::s[strlen(::s)], \", \");\n }\n *(unsigned short *)&::s[strlen(::s)] = 93;\n return ::s;\n}", + "ida_pseudo_norm": "char *func0(void *a1, int a2) {\n int i;\n int j;\n char s[24];\n unsigned long long v6;\n v6 = __readfsqword(40u);\n qsort(a1, a2, 16uLL, compare_tuples);\n result_1[0] = 0;\n *(unsigned short *)&result_1[strlen(result_1)] = 91;\n for (i = 0; i < a2; ++i) {\n *(unsigned short *)&result_1[strlen(result_1)] = 40;\n for (j = 0; j < *((uint32_t *)a1 + 4 * i + 2); ++j) {\n sprintf(s, \"%d\", *(uint32_t *)(4LL * j + *((uint64_t *)a1 + 2 * i)));\n strcat(result_1, s);\n if (j < *((uint32_t *)a1 + 4 * i + 2) - 1)\n strcpy(&result_1[strlen(result_1)], \", \");\n }\n *(unsigned short *)&result_1[strlen(result_1)] = 41;\n if (i < a2 - 1) strcpy(&result_1[strlen(result_1)], \", \");\n }\n *(unsigned short *)&result_1[strlen(result_1)] = 93;\n return result_1;\n}" + }, + { + "index": 949, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n// Define a tuple structure\n\ntypedef struct {\n\n int *elements;\n\n int size;\n\n} Tuple;\n\n\n\n// Function to count the total number of digits in a tuple\n\nint count_digs(Tuple tup) {\n\n int total = 0;\n\n for(int i = 0; i < tup.size; i++) {\n\n int num = tup.elements[i];\n\n if(num == 0) {\n\n total += 1;\n\n } else {\n\n while(num != 0) {\n\n total += 1;\n\n num /= 10;\n\n }\n\n }\n\n }\n\n return total;\n\n}\n\n\n\n// Comparison function for sorting tuples based on digit count\n\nint compare_tuples(const void *a, const void *b) {\n\n Tuple *tupA = (Tuple *)a;\n\n Tuple *tupB = (Tuple *)b;\n\n int countA = count_digs(*tupA);\n\n int countB = count_digs(*tupB);\n\n return countA - countB;\n\n}\n\n\n\n// Function to convert the sorted list of tuples to a string\n\n", + "func": "char* func0(Tuple* list, int list_size) {\n qsort(list, list_size, sizeof(Tuple), compare_tuples);\n static char result[1000];\n result[0] = '\\0';\n strcat(result, \"[\");\n for (int i = 0; i < list_size; i++) {\n strcat(result, \"(\");\n for (int j = 0; j < list[i].size; j++) {\n char num_str[20];\n sprintf(num_str, \"%d\", list[i].elements[j]);\n strcat(result, num_str);\n if (j < list[i].size - 1) {\n strcat(result, \", \");\n }\n }\n strcat(result, \")\");\n if (i < list_size - 1) {\n strcat(result, \", \");\n }\n }\n strcat(result, \"]\");\n return result;\n}", + "test": "int main() {\n\n // First test case\n\n Tuple list1[4];\n\n int elems1_0[] = {3, 4, 6, 723};\n\n list1[0].elements = elems1_0;\n\n list1[0].size = 4;\n\n int elems1_1[] = {1, 2};\n\n list1[1].elements = elems1_1;\n\n list1[1].size = 2;\n\n int elems1_2[] = {12345};\n\n list1[2].elements = elems1_2;\n\n list1[2].size = 1;\n\n int elems1_3[] = {134, 234, 34};\n\n list1[3].elements = elems1_3;\n\n list1[3].size = 3;\n\n assert(strcmp(func0(list1, 4), \"[(1, 2), (12345), (3, 4, 6, 723), (134, 234, 34)]\") == 0);\n\n\n\n // Second test case\n\n Tuple list2[4];\n\n int elems2_0[] = {3, 4, 8};\n\n list2[0].elements = elems2_0;\n\n list2[0].size = 3;\n\n int elems2_1[] = {1, 2};\n\n list2[1].elements = elems2_1;\n\n list2[1].size = 2;\n\n int elems2_2[] = {1234335};\n\n list2[2].elements = elems2_2;\n\n list2[2].size = 1;\n\n int elems2_3[] = {1345, 234, 334};\n\n list2[3].elements = elems2_3;\n\n list2[3].size = 3;\n\n assert(strcmp(func0(list2, 4), \"[(1, 2), (3, 4, 8), (1234335), (1345, 234, 334)]\") == 0);\n\n\n\n // Third test case\n\n Tuple list3[4];\n\n int elems3_0[] = {34, 4, 61, 723};\n\n list3[0].elements = elems3_0;\n\n list3[0].size = 4;\n\n int elems3_1[] = {1, 2};\n\n list3[1].elements = elems3_1;\n\n list3[1].size = 2;\n\n int elems3_2[] = {145};\n\n list3[2].elements = elems3_2;\n\n list3[2].size = 1;\n\n int elems3_3[] = {134, 23};\n\n list3[3].elements = elems3_3;\n\n list3[3].size = 2;\n\n assert(strcmp(func0(list3, 4), \"[(1, 2), (145), (134, 23), (34, 4, 61, 723)]\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x28,%rsp\nmov %rdi,%r13\nmov %esi,%r15d\nmov %fs:0x28,%rax\nmov %rax,0x18(%rsp)\nxor %eax,%eax\nmovslq %esi,%rsi\nlea -0x60(%rip),%rcx\nmov $0x10,%edx\ncallq 10a0 \nmovb $0x0,0x2db5(%rip)\nmov $0x3e8,%edx\nlea 0xd6d(%rip),%rsi\nlea 0x2da2(%rip),%rdi\ncallq 1090 <__strcat_chk@plt>\ntest %r15d,%r15d\njle 1399 \nadd $0x8,%r13\nmov $0x0,%r14d\nmov %rsp,%r12\njmpq 1353 \nmov $0x3e8,%edx\nlea 0xd41(%rip),%rsi\nlea 0x2d6f(%rip),%rdi\ncallq 1090 <__strcat_chk@plt>\nadd $0x1,%rbx\ncmp %ebx,0x0(%rbp)\njle 1325 \nmov -0x8(%rbp),%rax\nmov (%rax,%rbx,4),%r8d\nlea 0xd1a(%rip),%rcx\nmov $0x14,%edx\nmov $0x1,%esi\nmov %r12,%rdi\nmov $0x0,%eax\ncallq 10d0 <__sprintf_chk@plt>\nmov $0x3e8,%edx\nmov %r12,%rsi\nlea 0x2d2c(%rip),%rdi\ncallq 1090 <__strcat_chk@plt>\nmov 0x0(%rbp),%eax\nsub $0x1,%eax\ncmp %ebx,%eax\njle 12d6 \njmp 12be \nmov $0x3e8,%edx\nlea 0xcdd(%rip),%rsi\nlea 0x2d08(%rip),%rdi\ncallq 1090 <__strcat_chk@plt>\nlea -0x1(%r15),%eax\ncmp %r14d,%eax\njg 137f \nadd $0x1,%r14d\nadd $0x10,%r13\ncmp %r14d,%r15d\nje 1399 \nmov $0x3e8,%edx\nlea 0xca7(%rip),%rsi\nlea 0x2cda(%rip),%rdi\ncallq 1090 <__strcat_chk@plt>\nmov %r13,%rbp\ncmpl $0x0,0x0(%r13)\njle 1325 \nmov $0x0,%ebx\njmpq 12df \nmov $0x3e8,%edx\nlea 0xc80(%rip),%rsi\nlea 0x2cae(%rip),%rdi\ncallq 1090 <__strcat_chk@plt>\njmp 1346 \nmov $0x3e8,%edx\nlea 0xc6b(%rip),%rsi\nlea 0x2c94(%rip),%rdi\ncallq 1090 <__strcat_chk@plt>\nmov 0x18(%rsp),%rax\nxor %fs:0x28,%rax\njne 13d7 \nlea 0x2c78(%rip),%rax\nadd $0x28,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\ncallq 10b0 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 38h\nmov rbx, rdi\nmov r15d, esi\nmov [rsp+68h+var_64], esi\nmov rax, fs:28h\nmov [rsp+68h+var_40], rax\nxor eax, eax\nmovsxd rsi, esi; nmemb\nlea rcx, compare_tuples; compar\nmov edx, 10h; size\ncall _qsort\nmov cs:result_1, 0\nmov edx, 3E8h\nlea rsi, unk_2004\nlea rdi, result_1\ncall ___strcat_chk\ntest r15d, r15d\njle loc_13C5\nlea rax, [rbx+8]\nmov [rsp+68h+var_60], rax\nmov r15d, 0\nlea r13, result_1\njmp loc_1378\nloc_12EC:\nadd rbx, 1\ncmp [rbp+0], ebx\njle short loc_1347\nloc_12F5:\nmov rax, [rbp-8]\nmov r8d, [rax+rbx*4]\nmov rcx, r14\nmov edx, 14h\nmov esi, 2\nmov rdi, r12\nmov eax, 0\ncall ___sprintf_chk\nmov edx, 3E8h\nmov rsi, r12\nmov rdi, r13\ncall ___strcat_chk\nmov eax, [rbp+0]\nsub eax, 1\ncmp eax, ebx\njle short loc_12EC\nmov edx, 3E8h\nlea rsi, unk_200B\nmov rdi, r13\ncall ___strcat_chk\njmp short loc_12EC\nloc_1347:\nmov edx, 3E8h\nlea rsi, unk_200E\nmov rdi, r13\ncall ___strcat_chk\nmov eax, [rsp+68h+var_64]\nsub eax, 1\ncmp eax, r15d\njg short loc_13AF\nloc_1367:\nadd r15d, 1\nadd [rsp+68h+var_60], 10h\ncmp [rsp+68h+var_64], r15d\njz short loc_13C5\nloc_1378:\nmov edx, 3E8h\nlea rsi, unk_2006\nmov rdi, r13\ncall ___strcat_chk\nmov rax, [rsp+68h+var_60]\nmov rbp, rax\ncmp dword ptr [rax], 0\njle short loc_1347\nmov ebx, 0\nlea r12, [rsp+68h+var_58]\nlea r14, unk_2008\njmp loc_12F5\nloc_13AF:\nmov edx, 3E8h\nlea rsi, unk_200B\nmov rdi, r13\ncall ___strcat_chk\njmp short loc_1367\nloc_13C5:\nmov edx, 3E8h\nlea rsi, unk_2010\nlea rbx, result_1\nmov rdi, rbx\ncall ___strcat_chk\nmov rax, [rsp+68h+var_40]\nsub rax, fs:28h\njnz short loc_1402\nmov rax, rbx\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1402:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(_DWORD *a1, int a2)\n{\n int i; // r15d\n __int64 v3; // rbx\n _DWORD *v5; // [rsp+8h] [rbp-60h]\n _BYTE v6[24]; // [rsp+10h] [rbp-58h] BYREF\n unsigned __int64 v7; // [rsp+28h] [rbp-40h]\n\n v7 = __readfsqword(0x28u);\n qsort(a1, a2, 0x10uLL, compare_tuples);\n result_1 = 0;\n __strcat_chk(&result_1, &unk_2004, 1000LL);\n if ( a2 > 0 )\n {\n v5 = a1 + 2;\n for ( i = 0; i != a2; ++i )\n {\n __strcat_chk(&result_1, &unk_2006, 1000LL);\n if ( (int)*v5 > 0 )\n {\n v3 = 0LL;\n do\n {\n __sprintf_chk(v6, 2LL, 20LL, &unk_2008, *(unsigned int *)(*((_QWORD *)v5 - 1) + 4 * v3));\n __strcat_chk(&result_1, v6, 1000LL);\n if ( *v5 - 1 > (int)v3 )\n __strcat_chk(&result_1, &unk_200B, 1000LL);\n ++v3;\n }\n while ( *v5 > (int)v3 );\n }\n __strcat_chk(&result_1, &unk_200E, 1000LL);\n if ( a2 - 1 > i )\n __strcat_chk(&result_1, &unk_200B, 1000LL);\n v5 += 4;\n }\n }\n __strcat_chk(&result_1, &unk_2010, 1000LL);\n return &result_1;\n}", + "ida_strip_asm": "sub_1269:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 38h\nmov rbx, rdi\nmov r15d, esi\nmov [rsp+68h+var_64], esi\nmov rax, fs:28h\nmov [rsp+68h+var_40], rax\nxor eax, eax\nmovsxd rsi, esi; nmemb\nlea rcx, compar; compar\nmov edx, 10h; size\ncall _qsort\nmov cs:byte_4040, 0\nmov edx, 3E8h\nlea rsi, unk_2004\nlea rdi, byte_4040\ncall ___strcat_chk\ntest r15d, r15d\njle loc_13C5\nlea rax, [rbx+8]\nmov [rsp+68h+var_60], rax\nmov r15d, 0\nlea r13, byte_4040\njmp loc_1378\nloc_12EC:\nadd rbx, 1\ncmp [rbp+0], ebx\njle short loc_1347\nloc_12F5:\nmov rax, [rbp-8]\nmov r8d, [rax+rbx*4]\nmov rcx, r14\nmov edx, 14h\nmov esi, 2\nmov rdi, r12\nmov eax, 0\ncall ___sprintf_chk\nmov edx, 3E8h\nmov rsi, r12\nmov rdi, r13\ncall ___strcat_chk\nmov eax, [rbp+0]\nsub eax, 1\ncmp eax, ebx\njle short loc_12EC\nmov edx, 3E8h\nlea rsi, unk_200B\nmov rdi, r13\ncall ___strcat_chk\njmp short loc_12EC\nloc_1347:\nmov edx, 3E8h\nlea rsi, unk_200E\nmov rdi, r13\ncall ___strcat_chk\nmov eax, [rsp+68h+var_64]\nsub eax, 1\ncmp eax, r15d\njg short loc_13AF\nloc_1367:\nadd r15d, 1\nadd [rsp+68h+var_60], 10h\ncmp [rsp+68h+var_64], r15d\njz short loc_13C5\nloc_1378:\nmov edx, 3E8h\nlea rsi, unk_2006\nmov rdi, r13\ncall ___strcat_chk\nmov rax, [rsp+68h+var_60]\nmov rbp, rax\ncmp dword ptr [rax], 0\njle short loc_1347\nmov ebx, 0\nlea r12, [rsp+68h+var_58]\nlea r14, unk_2008\njmp loc_12F5\nloc_13AF:\nmov edx, 3E8h\nlea rsi, unk_200B\nmov rdi, r13\ncall ___strcat_chk\njmp short loc_1367\nloc_13C5:\nmov edx, 3E8h\nlea rsi, unk_2010\nlea rbx, byte_4040\nmov rdi, rbx\ncall ___strcat_chk\nmov rax, [rsp+68h+var_40]\nsub rax, fs:28h\njnz short loc_1402\nmov rax, rbx\nadd rsp, 38h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1402:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_1269(_DWORD *a1, int a2)\n{\n int i; // r15d\n __int64 v3; // rbx\n _DWORD *v5; // [rsp+8h] [rbp-60h]\n _BYTE v6[24]; // [rsp+10h] [rbp-58h] BYREF\n unsigned __int64 v7; // [rsp+28h] [rbp-40h]\n\n v7 = __readfsqword(0x28u);\n qsort(a1, a2, 0x10uLL, compar);\n byte_4040 = 0;\n __strcat_chk(&byte_4040, &unk_2004, 1000LL);\n if ( a2 > 0 )\n {\n v5 = a1 + 2;\n for ( i = 0; i != a2; ++i )\n {\n __strcat_chk(&byte_4040, &unk_2006, 1000LL);\n if ( (int)*v5 > 0 )\n {\n v3 = 0LL;\n do\n {\n __sprintf_chk(v6, 2LL, 20LL, &unk_2008, *(unsigned int *)(*((_QWORD *)v5 - 1) + 4 * v3));\n __strcat_chk(&byte_4040, v6, 1000LL);\n if ( *v5 - 1 > (int)v3 )\n __strcat_chk(&byte_4040, &unk_200B, 1000LL);\n ++v3;\n }\n while ( *v5 > (int)v3 );\n }\n __strcat_chk(&byte_4040, &unk_200E, 1000LL);\n if ( a2 - 1 > i )\n __strcat_chk(&byte_4040, &unk_200B, 1000LL);\n v5 += 4;\n }\n }\n __strcat_chk(&byte_4040, &unk_2010, 1000LL);\n return &byte_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1269(uint32_t *a1, int a2) {\n int i;\n long long v3;\n uint32_t *v5;\n uint8_t v6[24];\n unsigned long long v7;\n v7 = __readfsqword(40u);\n qsort(a1, a2, 16uLL, compar);\n byte_4040 = 0;\n __strcat_chk(&byte_4040, &unk_2004, 1000LL);\n if (a2 > 0) {\n v5 = a1 + 2;\n for (i = 0; i != a2; ++i) {\n __strcat_chk(&byte_4040, &unk_2006, 1000LL);\n if ((int)*v5 > 0) {\n v3 = 0LL;\n do {\n __sprintf_chk(v6, 2LL, 20LL, &unk_2008,\n *(unsigned int *)(*((uint64_t *)v5 - 1) + 4 * v3));\n __strcat_chk(&byte_4040, v6, 1000LL);\n if (*v5 - 1 > (int)v3) __strcat_chk(&byte_4040, &unk_200B, 1000LL);\n ++v3;\n } while (*v5 > (int)v3);\n }\n __strcat_chk(&byte_4040, &unk_200E, 1000LL);\n if (a2 - 1 > i) __strcat_chk(&byte_4040, &unk_200B, 1000LL);\n v5 += 4;\n }\n }\n __strcat_chk(&byte_4040, &unk_2010, 1000LL);\n return &byte_4040;\n}", + "ida_pseudo_norm": "char *func0(uint32_t *a1, int a2) {\n int i;\n long long v3;\n uint32_t *v5;\n uint8_t v6[24];\n unsigned long long v7;\n v7 = __readfsqword(40u);\n qsort(a1, a2, 16uLL, compare_tuples);\n result_1 = 0;\n __strcat_chk(&result_1, &unk_2004, 1000LL);\n if (a2 > 0) {\n v5 = a1 + 2;\n for (i = 0; i != a2; ++i) {\n __strcat_chk(&result_1, &unk_2006, 1000LL);\n if ((int)*v5 > 0) {\n v3 = 0LL;\n do {\n __sprintf_chk(v6, 2LL, 20LL, &unk_2008,\n *(unsigned int *)(*((uint64_t *)v5 - 1) + 4 * v3));\n __strcat_chk(&result_1, v6, 1000LL);\n if (*v5 - 1 > (int)v3) __strcat_chk(&result_1, &unk_200B, 1000LL);\n ++v3;\n } while (*v5 > (int)v3);\n }\n __strcat_chk(&result_1, &unk_200E, 1000LL);\n if (a2 - 1 > i) __strcat_chk(&result_1, &unk_200B, 1000LL);\n v5 += 4;\n }\n }\n __strcat_chk(&result_1, &unk_2010, 1000LL);\n return &result_1;\n}" + }, + { + "index": 949, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n// Define a tuple structure\n\ntypedef struct {\n\n int *elements;\n\n int size;\n\n} Tuple;\n\n\n\n// Function to count the total number of digits in a tuple\n\nint count_digs(Tuple tup) {\n\n int total = 0;\n\n for(int i = 0; i < tup.size; i++) {\n\n int num = tup.elements[i];\n\n if(num == 0) {\n\n total += 1;\n\n } else {\n\n while(num != 0) {\n\n total += 1;\n\n num /= 10;\n\n }\n\n }\n\n }\n\n return total;\n\n}\n\n\n\n// Comparison function for sorting tuples based on digit count\n\nint compare_tuples(const void *a, const void *b) {\n\n Tuple *tupA = (Tuple *)a;\n\n Tuple *tupB = (Tuple *)b;\n\n int countA = count_digs(*tupA);\n\n int countB = count_digs(*tupB);\n\n return countA - countB;\n\n}\n\n\n\n// Function to convert the sorted list of tuples to a string\n\n", + "func": "char* func0(Tuple* list, int list_size) {\n qsort(list, list_size, sizeof(Tuple), compare_tuples);\n static char result[1000];\n result[0] = '\\0';\n strcat(result, \"[\");\n for (int i = 0; i < list_size; i++) {\n strcat(result, \"(\");\n for (int j = 0; j < list[i].size; j++) {\n char num_str[20];\n sprintf(num_str, \"%d\", list[i].elements[j]);\n strcat(result, num_str);\n if (j < list[i].size - 1) {\n strcat(result, \", \");\n }\n }\n strcat(result, \")\");\n if (i < list_size - 1) {\n strcat(result, \", \");\n }\n }\n strcat(result, \"]\");\n return result;\n}", + "test": "int main() {\n\n // First test case\n\n Tuple list1[4];\n\n int elems1_0[] = {3, 4, 6, 723};\n\n list1[0].elements = elems1_0;\n\n list1[0].size = 4;\n\n int elems1_1[] = {1, 2};\n\n list1[1].elements = elems1_1;\n\n list1[1].size = 2;\n\n int elems1_2[] = {12345};\n\n list1[2].elements = elems1_2;\n\n list1[2].size = 1;\n\n int elems1_3[] = {134, 234, 34};\n\n list1[3].elements = elems1_3;\n\n list1[3].size = 3;\n\n assert(strcmp(func0(list1, 4), \"[(1, 2), (12345), (3, 4, 6, 723), (134, 234, 34)]\") == 0);\n\n\n\n // Second test case\n\n Tuple list2[4];\n\n int elems2_0[] = {3, 4, 8};\n\n list2[0].elements = elems2_0;\n\n list2[0].size = 3;\n\n int elems2_1[] = {1, 2};\n\n list2[1].elements = elems2_1;\n\n list2[1].size = 2;\n\n int elems2_2[] = {1234335};\n\n list2[2].elements = elems2_2;\n\n list2[2].size = 1;\n\n int elems2_3[] = {1345, 234, 334};\n\n list2[3].elements = elems2_3;\n\n list2[3].size = 3;\n\n assert(strcmp(func0(list2, 4), \"[(1, 2), (3, 4, 8), (1234335), (1345, 234, 334)]\") == 0);\n\n\n\n // Third test case\n\n Tuple list3[4];\n\n int elems3_0[] = {34, 4, 61, 723};\n\n list3[0].elements = elems3_0;\n\n list3[0].size = 4;\n\n int elems3_1[] = {1, 2};\n\n list3[1].elements = elems3_1;\n\n list3[1].size = 2;\n\n int elems3_2[] = {145};\n\n list3[2].elements = elems3_2;\n\n list3[2].size = 1;\n\n int elems3_3[] = {134, 23};\n\n list3[3].elements = elems3_3;\n\n list3[3].size = 2;\n\n assert(strcmp(func0(list3, 4), \"[(1, 2), (145), (134, 23), (34, 4, 61, 723)]\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmovslq %esi,%rsi\nmov $0x10,%edx\nxor %r15d,%r15d\npush %r14\nlea -0x13a(%rip),%rcx\npush %r13\npush %r12\npush %rbp\nmov %rdi,%rbp\npush %rbx\nmov %rsi,%rbx\nadd $0x8,%rbp\nsub $0x38,%rsp\nmov %esi,0xc(%rsp)\nmov %fs:0x28,%rax\nmov %rax,0x28(%rsp)\nxor %eax,%eax\ncallq 10c0 \nmov $0x5b,%ecx\nmov %ebx,%eax\nsub $0x1,%ebx\nmov %cx,0x29b8(%rip)\nmov %ebx,0x8(%rsp)\ntest %eax,%eax\njle 1811 \nnopl 0x0(%rax)\nmov $0x3e8,%edx\nlea 0x962(%rip),%rsi\nlea 0x10(%rsp),%r13\nxor %ebx,%ebx\nlea 0x298e(%rip),%rdi\nlea 0x2987(%rip),%r14\ncallq 10b0 <__strcat_chk@plt>\nmov 0x0(%rbp),%edx\nmov %r14,%r12\ntest %edx,%edx\njg 16dc \njmpq 1789 \nnopl (%rax)\nadd $0x1,%rbx\ncmp %ebx,%edx\njle 1789 \nmov -0x8(%rbp),%rax\nmov %r13,%rdi\nmov $0x14,%edx\nlea 0x919(%rip),%rcx\nmov $0x1,%esi\nmov (%rax,%rbx,4),%r8d\nxor %eax,%eax\ncallq 1110 <__sprintf_chk@plt>\nlea 0x293a(%rip),%rdi\nmov (%rdi),%edx\nadd $0x4,%rdi\nlea -0x1010101(%rdx),%eax\nnot %edx\nand %edx,%eax\nand $0x80808080,%eax\nje 1706 \nmov %eax,%edx\nshr $0x10,%edx\ntest $0x8080,%eax\ncmove %edx,%eax\nlea 0x2(%rdi),%rdx\ncmove %rdx,%rdi\nmov $0x3e8,%edx\nmov %eax,%esi\nadd %al,%sil\nmov %r13,%rsi\nsbb $0x3,%rdi\nsub %r14,%rdi\nadd %r12,%rdi\ncallq 1100 <__stpcpy_chk@plt>\nmov 0x0(%rbp),%edx\nlea -0x1(%rdx),%ecx\ncmp %ebx,%ecx\njle 16d0 \nlea 0x2cc5(%rip),%rcx\nmov $0x3,%edx\nmov %rax,%rdi\nadd $0x1,%rbx\nsub %rax,%rcx\nlea 0x892(%rip),%rsi\ncallq 10f0 <__memcpy_chk@plt>\nmov 0x0(%rbp),%edx\ncmp %ebx,%edx\njg 16dc \nlea 0x28b0(%rip),%rcx\nmov %rcx,%r12\nmov %rcx,%rdi\nmov (%rdi),%edx\nadd $0x4,%rdi\nlea -0x1010101(%rdx),%eax\nnot %edx\nand %edx,%eax\nand $0x80808080,%eax\nje 1796 \nmov %eax,%edx\nshr $0x10,%edx\ntest $0x8080,%eax\ncmove %edx,%eax\nlea 0x2(%rdi),%rdx\ncmove %rdx,%rdi\nmov %eax,%ebx\nadd %al,%bl\nmov $0x29,%eax\nsbb $0x3,%rdi\nsub %rcx,%rdi\nadd %r12,%rdi\nmov %ax,(%rdi)\nadd $0x1,%rdi\ncmp %r15d,0x8(%rsp)\njle 17fe \nlea 0x2c3e(%rip),%rcx\nmov $0x3,%edx\nlea 0x815(%rip),%rsi\nsub %rdi,%rcx\ncallq 10f0 <__memcpy_chk@plt>\nadd $0x1,%r15d\nadd $0x10,%rbp\ncmp %r15d,0xc(%rsp)\njne 1698 \nmov $0x3e8,%edx\nlea 0x7e7(%rip),%rsi\nlea 0x281c(%rip),%rdi\ncallq 10b0 <__strcat_chk@plt>\nmov 0x28(%rsp),%rax\nxor %fs:0x28,%rax\njne 184f \nadd $0x38,%rsp\nlea 0x27fc(%rip),%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\ncallq 10d0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\npush r15\nmovsxd rsi, esi; nmemb\nlea rcx, compare_tuples; compar\nmov r15, rdi\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 38h\nmov rdx, fs:28h\nmov [rsp+68h+var_40], rdx\nxor edx, edx\nmov edx, 10h; size\nmov [rsp+68h+var_60], esi\ncall _qsort\nmov r8d, [rsp+68h+var_60]\nmov esi, 5Bh ; '['\nmov cs:result_1, si\ntest r8d, r8d\njle loc_17E0\nlea eax, [r8-1]\nmov [rsp+68h+var_5C], r8d\nadd r15, 8\nxor r12d, r12d\nmov [rsp+68h+var_60], eax\nlea rbx, result_1\nlea rbp, unk_2008\nmov r14, r15\nnop dword ptr [rax+00h]\nloc_16C0:\nmov edx, 3E8h\nmov rdi, rbx\nlea r15, [rsp+68h+var_58]\nxor r13d, r13d\nlea rsi, unk_2006\ncall ___strcat_chk\nmov ecx, [r14]\ntest ecx, ecx\njg short loc_16F1\njmp short loc_175E\nloc_16E8:\nadd r13, 1\ncmp edx, r13d\njle short loc_175E\nloc_16F1:\nmov rax, [r14-8]\nmov rcx, rbp\nmov edx, 14h\nmov rdi, r15\nmov esi, 2\nmov r8d, [rax+r13*4]\nxor eax, eax\ncall ___sprintf_chk\nmov rdi, rbx; s\ncall _strlen\nmov edx, 3E8h\nmov rsi, r15\nlea rdi, [rbx+rax]\ncall ___stpcpy_chk\nmov edx, [r14]\nlea ecx, [rdx-1]\ncmp ecx, r13d\njle short loc_16E8\nlea rcx, _end\nmov edx, 3\nmov rdi, rax\nadd r13, 1\nsub rcx, rax\nlea rsi, unk_200B\ncall ___memcpy_chk\nmov edx, [r14]\ncmp edx, r13d\njg short loc_16F1\nloc_175E:\nmov rdi, rbx; s\ncall _strlen\nmov edx, 29h ; ')'\nadd rax, rbx\nmov [rax], dx\ncmp [rsp+68h+var_60], r12d\njle short loc_1797\nlea rdi, [rax+1]\nlea rcx, _end\nmov edx, 3\nsub rcx, rdi\nlea rsi, unk_200B\ncall ___memcpy_chk\nloc_1797:\nadd r12d, 1\nadd r14, 10h\ncmp [rsp+68h+var_5C], r12d\njnz loc_16C0\nloc_17AA:\nmov edx, 3E8h\nlea rsi, unk_2004\nmov rdi, rbx\ncall ___strcat_chk\nmov rax, [rsp+68h+var_40]\nsub rax, fs:28h\njnz short loc_17E9\nadd rsp, 38h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_17E0:\nlea rbx, result_1\njmp short loc_17AA\nloc_17E9:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(_DWORD *a1, int a2)\n{\n int v2; // r12d\n _DWORD *v3; // r14\n __int64 v4; // r13\n size_t v5; // rax\n __int64 v6; // rax\n char *v7; // rax\n _BYTE v9[24]; // [rsp+10h] [rbp-58h] BYREF\n unsigned __int64 v10; // [rsp+28h] [rbp-40h]\n\n v10 = __readfsqword(0x28u);\n qsort(a1, a2, 0x10uLL, compare_tuples);\n strcpy(result_1, \"[\");\n if ( a2 > 0 )\n {\n v2 = 0;\n v3 = a1 + 2;\n do\n {\n v4 = 0LL;\n __strcat_chk(result_1, &unk_2006, 1000LL);\n if ( (int)*v3 > 0 )\n {\n do\n {\n while ( 1 )\n {\n __sprintf_chk(v9, 2LL, 20LL, &unk_2008, *(unsigned int *)(*((_QWORD *)v3 - 1) + 4 * v4));\n v5 = strlen(result_1);\n v6 = __stpcpy_chk(&result_1[v5], v9, 1000LL);\n if ( *v3 - 1 > (int)v4 )\n break;\n if ( *v3 <= (int)++v4 )\n goto LABEL_8;\n }\n ++v4;\n __memcpy_chk(v6, &unk_200B, 3LL, (char *)&end - v6);\n }\n while ( *v3 > (int)v4 );\n }\nLABEL_8:\n v7 = &result_1[strlen(result_1)];\n *(_WORD *)v7 = 41;\n if ( a2 - 1 > v2 )\n __memcpy_chk(v7 + 1, &unk_200B, 3LL, &end - (_UNKNOWN *)(v7 + 1));\n ++v2;\n v3 += 4;\n }\n while ( a2 != v2 );\n }\n __strcat_chk(result_1, &unk_2004, 1000LL);\n return result_1;\n}", + "ida_strip_asm": "sub_1640:\nendbr64\npush r15\nmovsxd rsi, esi; nmemb\nlea rcx, compar; compar\nmov r15, rdi\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 38h\nmov rdx, fs:28h\nmov [rsp+68h+var_40], rdx\nxor edx, edx\nmov edx, 10h; size\nmov [rsp+68h+var_60], esi\ncall _qsort\nmov r8d, [rsp+68h+var_60]\nmov esi, 5Bh ; '['\nmov cs:s, si\ntest r8d, r8d\njle loc_17E0\nlea eax, [r8-1]\nmov [rsp+68h+var_5C], r8d\nadd r15, 8\nxor r12d, r12d\nmov [rsp+68h+var_60], eax\nlea rbx, s\nlea rbp, unk_2008\nmov r14, r15\nnop dword ptr [rax+00h]\nloc_16C0:\nmov edx, 3E8h\nmov rdi, rbx\nlea r15, [rsp+68h+var_58]\nxor r13d, r13d\nlea rsi, unk_2006\ncall ___strcat_chk\nmov ecx, [r14]\ntest ecx, ecx\njg short loc_16F1\njmp short loc_175E\nloc_16E8:\nadd r13, 1\ncmp edx, r13d\njle short loc_175E\nloc_16F1:\nmov rax, [r14-8]\nmov rcx, rbp\nmov edx, 14h\nmov rdi, r15\nmov esi, 2\nmov r8d, [rax+r13*4]\nxor eax, eax\ncall ___sprintf_chk\nmov rdi, rbx; s\ncall _strlen\nmov edx, 3E8h\nmov rsi, r15\nlea rdi, [rbx+rax]\ncall ___stpcpy_chk\nmov edx, [r14]\nlea ecx, [rdx-1]\ncmp ecx, r13d\njle short loc_16E8\nlea rcx, __strcat_chk\nmov edx, 3\nmov rdi, rax\nadd r13, 1\nsub rcx, rax\nlea rsi, unk_200B\ncall ___memcpy_chk\nmov edx, [r14]\ncmp edx, r13d\njg short loc_16F1\nloc_175E:\nmov rdi, rbx; s\ncall _strlen\nmov edx, 29h ; ')'\nadd rax, rbx\nmov [rax], dx\ncmp [rsp+68h+var_60], r12d\njle short loc_1797\nlea rdi, [rax+1]\nlea rcx, __strcat_chk\nmov edx, 3\nsub rcx, rdi\nlea rsi, unk_200B\ncall ___memcpy_chk\nloc_1797:\nadd r12d, 1\nadd r14, 10h\ncmp [rsp+68h+var_5C], r12d\njnz loc_16C0\nloc_17AA:\nmov edx, 3E8h\nlea rsi, unk_2004\nmov rdi, rbx\ncall ___strcat_chk\nmov rax, [rsp+68h+var_40]\nsub rax, fs:28h\njnz short loc_17E9\nadd rsp, 38h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_17E0:\nlea rbx, s\njmp short loc_17AA\nloc_17E9:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_1640(_DWORD *a1, int a2)\n{\n int v2; // r12d\n _DWORD *v3; // r14\n __int64 v4; // r13\n size_t v5; // rax\n __int64 v6; // rax\n char *v7; // rax\n _BYTE v9[24]; // [rsp+10h] [rbp-58h] BYREF\n unsigned __int64 v10; // [rsp+28h] [rbp-40h]\n\n v10 = __readfsqword(0x28u);\n qsort(a1, a2, 0x10uLL, compar);\n strcpy(s, \"[\");\n if ( a2 > 0 )\n {\n v2 = 0;\n v3 = a1 + 2;\n do\n {\n v4 = 0LL;\n __strcat_chk(s, &unk_2006, 1000LL);\n if ( (int)*v3 > 0 )\n {\n do\n {\n while ( 1 )\n {\n __sprintf_chk(v9, 2LL, 20LL, &unk_2008, *(unsigned int *)(*((_QWORD *)v3 - 1) + 4 * v4));\n v5 = strlen(s);\n v6 = __stpcpy_chk(&s[v5], v9, 1000LL);\n if ( *v3 - 1 > (int)v4 )\n break;\n if ( *v3 <= (int)++v4 )\n goto LABEL_8;\n }\n ++v4;\n __memcpy_chk(v6, &unk_200B, 3LL, (char *)&_strcat_chk - v6);\n }\n while ( *v3 > (int)v4 );\n }\nLABEL_8:\n v7 = &s[strlen(s)];\n *(_WORD *)v7 = 41;\n if ( a2 - 1 > v2 )\n __memcpy_chk(v7 + 1, &unk_200B, 3LL, &_strcat_chk - (_UNKNOWN *)(v7 + 1));\n ++v2;\n v3 += 4;\n }\n while ( a2 != v2 );\n }\n __strcat_chk(s, &unk_2004, 1000LL);\n return s;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1640(uint32_t *a1, int a2) {\n int v2;\n uint32_t *v3;\n long long v4;\n unsigned int v5;\n long long v6;\n char *v7;\n uint8_t v9[24];\n unsigned long long v10;\n v10 = __readfsqword(40u);\n qsort(a1, a2, 16uLL, compar);\n strcpy(s, \"[\");\n if (a2 > 0) {\n v2 = 0;\n v3 = a1 + 2;\n do {\n v4 = 0LL;\n __strcat_chk(s, &unk_2006, 1000LL);\n if ((int)*v3 > 0) {\n do {\n while (1) {\n __sprintf_chk(v9, 2LL, 20LL, &unk_2008,\n *(unsigned int *)(*((uint64_t *)v3 - 1) + 4 * v4));\n v5 = strlen(s);\n v6 = __stpcpy_chk(&s[v5], v9, 1000LL);\n if (*v3 - 1 > (int)v4) break;\n if (*v3 <= (int)++v4) goto LABEL_8;\n }\n ++v4;\n __memcpy_chk(v6, &unk_200B, 3LL, (char *)&_strcat_chk - v6);\n } while (*v3 > (int)v4);\n }\n LABEL_8:\n v7 = &s[strlen(s)];\n *(unsigned short *)v7 = 41;\n if (a2 - 1 > v2)\n __memcpy_chk(v7 + 1, &unk_200B, 3LL, &_strcat_chk - (void *)(v7 + 1));\n ++v2;\n v3 += 4;\n } while (a2 != v2);\n }\n __strcat_chk(s, &unk_2004, 1000LL);\n return s;\n}", + "ida_pseudo_norm": "char *func0(uint32_t *a1, int a2) {\n int v2;\n uint32_t *v3;\n long long v4;\n unsigned int v5;\n long long v6;\n char *v7;\n uint8_t v9[24];\n unsigned long long v10;\n v10 = __readfsqword(40u);\n qsort(a1, a2, 16uLL, compare_tuples);\n strcpy(result_1, \"[\");\n if (a2 > 0) {\n v2 = 0;\n v3 = a1 + 2;\n do {\n v4 = 0LL;\n __strcat_chk(result_1, &unk_2006, 1000LL);\n if ((int)*v3 > 0) {\n do {\n while (1) {\n __sprintf_chk(v9, 2LL, 20LL, &unk_2008,\n *(unsigned int *)(*((uint64_t *)v3 - 1) + 4 * v4));\n v5 = strlen(result_1);\n v6 = __stpcpy_chk(&result_1[v5], v9, 1000LL);\n if (*v3 - 1 > (int)v4) break;\n if (*v3 <= (int)++v4) goto LABEL_8;\n }\n ++v4;\n __memcpy_chk(v6, &unk_200B, 3LL, (char *)&end - v6);\n } while (*v3 > (int)v4);\n }\n LABEL_8:\n v7 = &result_1[strlen(result_1)];\n *(unsigned short *)v7 = 41;\n if (a2 - 1 > v2)\n __memcpy_chk(v7 + 1, &unk_200B, 3LL, &end - (void *)(v7 + 1));\n ++v2;\n v3 += 4;\n } while (a2 != v2);\n }\n __strcat_chk(result_1, &unk_2004, 1000LL);\n return result_1;\n}" + }, + { + "index": 949, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n// Define a tuple structure\n\ntypedef struct {\n\n int *elements;\n\n int size;\n\n} Tuple;\n\n\n\n// Function to count the total number of digits in a tuple\n\nint count_digs(Tuple tup) {\n\n int total = 0;\n\n for(int i = 0; i < tup.size; i++) {\n\n int num = tup.elements[i];\n\n if(num == 0) {\n\n total += 1;\n\n } else {\n\n while(num != 0) {\n\n total += 1;\n\n num /= 10;\n\n }\n\n }\n\n }\n\n return total;\n\n}\n\n\n\n// Comparison function for sorting tuples based on digit count\n\nint compare_tuples(const void *a, const void *b) {\n\n Tuple *tupA = (Tuple *)a;\n\n Tuple *tupB = (Tuple *)b;\n\n int countA = count_digs(*tupA);\n\n int countB = count_digs(*tupB);\n\n return countA - countB;\n\n}\n\n\n\n// Function to convert the sorted list of tuples to a string\n\n", + "func": "char* func0(Tuple* list, int list_size) {\n qsort(list, list_size, sizeof(Tuple), compare_tuples);\n static char result[1000];\n result[0] = '\\0';\n strcat(result, \"[\");\n for (int i = 0; i < list_size; i++) {\n strcat(result, \"(\");\n for (int j = 0; j < list[i].size; j++) {\n char num_str[20];\n sprintf(num_str, \"%d\", list[i].elements[j]);\n strcat(result, num_str);\n if (j < list[i].size - 1) {\n strcat(result, \", \");\n }\n }\n strcat(result, \")\");\n if (i < list_size - 1) {\n strcat(result, \", \");\n }\n }\n strcat(result, \"]\");\n return result;\n}", + "test": "int main() {\n\n // First test case\n\n Tuple list1[4];\n\n int elems1_0[] = {3, 4, 6, 723};\n\n list1[0].elements = elems1_0;\n\n list1[0].size = 4;\n\n int elems1_1[] = {1, 2};\n\n list1[1].elements = elems1_1;\n\n list1[1].size = 2;\n\n int elems1_2[] = {12345};\n\n list1[2].elements = elems1_2;\n\n list1[2].size = 1;\n\n int elems1_3[] = {134, 234, 34};\n\n list1[3].elements = elems1_3;\n\n list1[3].size = 3;\n\n assert(strcmp(func0(list1, 4), \"[(1, 2), (12345), (3, 4, 6, 723), (134, 234, 34)]\") == 0);\n\n\n\n // Second test case\n\n Tuple list2[4];\n\n int elems2_0[] = {3, 4, 8};\n\n list2[0].elements = elems2_0;\n\n list2[0].size = 3;\n\n int elems2_1[] = {1, 2};\n\n list2[1].elements = elems2_1;\n\n list2[1].size = 2;\n\n int elems2_2[] = {1234335};\n\n list2[2].elements = elems2_2;\n\n list2[2].size = 1;\n\n int elems2_3[] = {1345, 234, 334};\n\n list2[3].elements = elems2_3;\n\n list2[3].size = 3;\n\n assert(strcmp(func0(list2, 4), \"[(1, 2), (3, 4, 8), (1234335), (1345, 234, 334)]\") == 0);\n\n\n\n // Third test case\n\n Tuple list3[4];\n\n int elems3_0[] = {34, 4, 61, 723};\n\n list3[0].elements = elems3_0;\n\n list3[0].size = 4;\n\n int elems3_1[] = {1, 2};\n\n list3[1].elements = elems3_1;\n\n list3[1].size = 2;\n\n int elems3_2[] = {145};\n\n list3[2].elements = elems3_2;\n\n list3[2].size = 1;\n\n int elems3_3[] = {134, 23};\n\n list3[3].elements = elems3_3;\n\n list3[3].size = 2;\n\n assert(strcmp(func0(list3, 4), \"[(1, 2), (145), (134, 23), (34, 4, 61, 723)]\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nmovslq %esi,%rsi\nmov $0x10,%edx\nlea -0x135(%rip),%rcx\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nmov %rsi,%rbx\nsub $0x38,%rsp\nmov %esi,0x4(%rsp)\nmov %rdi,0x8(%rsp)\nmov %fs:0x28,%rax\nmov %rax,0x28(%rsp)\nxor %eax,%eax\ncallq 10c0 \nmov $0x5b,%esi\nmov %si,0x29e2(%rip)\ntest %ebx,%ebx\njle 18c9 \nmov 0x4(%rsp),%eax\nlea -0x1(%rax),%r14d\ntest %r14d,%r14d\njle 1978 \nmov 0x8(%rsp),%rax\nxor %r15d,%r15d\nlea 0x10(%rsp),%rbp\nlea 0x2d9d(%rip),%r12\nlea 0x8(%rax),%rbx\nmov $0x3e8,%edx\nlea 0x96a(%rip),%rsi\nlea 0x299d(%rip),%rdi\nxor %r13d,%r13d\ncallq 10b0 <__strcat_chk@plt>\nmov (%rbx),%ecx\ntest %ecx,%ecx\njle 173f \nnopl (%rax)\nmov -0x8(%rbx),%rax\nmov %rbp,%rdi\nmov $0x14,%edx\nlea 0x940(%rip),%rcx\nmov $0x1,%esi\nmov (%rax,%r13,4),%r8d\nxor %eax,%eax\ncallq 1110 <__sprintf_chk@plt>\nlea 0x295e(%rip),%rdi\nmov (%rdi),%edx\nadd $0x4,%rdi\nlea -0x1010101(%rdx),%eax\nnot %edx\nand %edx,%eax\nand $0x80808080,%eax\nje 16e2 \nmov %eax,%edx\nshr $0x10,%edx\ntest $0x8080,%eax\ncmove %edx,%eax\nlea 0x2(%rdi),%rdx\ncmove %rdx,%rdi\nmov $0x3e8,%edx\nmov %eax,%esi\nadd %al,%sil\nmov %rbp,%rsi\nsbb $0x3,%rdi\ncallq 1100 <__stpcpy_chk@plt>\nmov (%rbx),%edx\nlea -0x1(%rdx),%ecx\ncmp %r13d,%ecx\njg 1910 \nadd $0x1,%r13\ncmp %r13d,%edx\njg 16b8 \nlea 0x28fa(%rip),%rcx\nmov %rcx,%r13\nmov %rcx,%rdi\nmov (%rdi),%edx\nadd $0x4,%rdi\nlea -0x1010101(%rdx),%eax\nnot %edx\nand %edx,%eax\nand $0x80808080,%eax\nje 174c \nmov %eax,%edx\nshr $0x10,%edx\ntest $0x8080,%eax\ncmove %edx,%eax\nlea 0x2(%rdi),%rdx\ncmove %rdx,%rdi\nmov $0x29,%edx\nmov %eax,%esi\nadd %al,%sil\nlea 0x87f(%rip),%rsi\nsbb $0x3,%rdi\nadd $0x1,%r15d\nadd $0x10,%rbx\nsub %rcx,%rdi\nmov %r12,%rcx\nadd %r13,%rdi\nmov %dx,(%rdi)\nadd $0x1,%rdi\nmov $0x3,%edx\nsub %rdi,%rcx\ncallq 10f0 <__memcpy_chk@plt>\ncmp %r15d,%r14d\njg 1690 \ncmp %r15d,0x4(%rsp)\njle 18c9 \nmovslq %r15d,%r12\nshl $0x4,%r12\nadd 0x8(%rsp),%r12\nnopw 0x0(%rax,%rax,1)\nmov $0x3e8,%edx\nlea 0x822(%rip),%rsi\nlea 0x2855(%rip),%rdi\ncallq 10b0 <__strcat_chk@plt>\nmov 0x8(%r12),%eax\ntest %eax,%eax\njle 189e \nlea 0x283c(%rip),%r14\nxor %ebx,%ebx\nlea 0x10(%rsp),%rbp\nmov %r14,%r13\nxchg %ax,%ax\nmov (%r12),%rax\nmov %rbp,%rdi\nmov $0x14,%edx\nlea 0x7e8(%rip),%rcx\nmov $0x1,%esi\nmov (%rax,%rbx,4),%r8d\nxor %eax,%eax\ncallq 1110 <__sprintf_chk@plt>\nlea 0x2806(%rip),%rdi\nmov (%rdi),%edx\nadd $0x4,%rdi\nlea -0x1010101(%rdx),%eax\nnot %edx\nand %edx,%eax\nand $0x80808080,%eax\nje 183a \nmov %eax,%edx\nshr $0x10,%edx\ntest $0x8080,%eax\ncmove %edx,%eax\nlea 0x2(%rdi),%rdx\ncmove %rdx,%rdi\nmov $0x3e8,%edx\nmov %eax,%esi\nadd %al,%sil\nmov %rbp,%rsi\nsbb $0x3,%rdi\nsub %r14,%rdi\nadd %r13,%rdi\ncallq 1100 <__stpcpy_chk@plt>\nmov 0x8(%r12),%edx\nlea -0x1(%rdx),%ecx\ncmp %ebx,%ecx\njg 1940 \nadd $0x1,%rbx\ncmp %ebx,%edx\njg 1810 \nmov $0x3e8,%edx\nlea 0x764(%rip),%rsi\nadd $0x1,%r15d\nadd $0x10,%r12\nlea 0x2787(%rip),%rdi\ncallq 10b0 <__strcat_chk@plt>\ncmp %r15d,0x4(%rsp)\njg 17d8 \nmov $0x3e8,%edx\nlea 0x72f(%rip),%rsi\nlea 0x2764(%rip),%rdi\ncallq 10b0 <__strcat_chk@plt>\nmov 0x28(%rsp),%rax\nxor %fs:0x28,%rax\njne 1980 \nadd $0x38,%rsp\nlea 0x2740(%rip),%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax,%rax,1)\nmov %r12,%rcx\nmov $0x3,%edx\nmov %rax,%rdi\nadd $0x1,%r13\nsub %rax,%rcx\nlea 0x6df(%rip),%rsi\ncallq 10f0 <__memcpy_chk@plt>\ncmp %r13d,(%rbx)\njg 16b8 \njmpq 173f \nnopl 0x0(%rax)\nlea 0x2ae1(%rip),%rcx\nmov $0x3,%edx\nmov %rax,%rdi\nadd $0x1,%rbx\nsub %rax,%rcx\nlea 0x6ab(%rip),%rsi\ncallq 10f0 <__memcpy_chk@plt>\ncmp %ebx,0x8(%r12)\njg 1810 \njmpq 189e \nnopw 0x0(%rax,%rax,1)\nxor %r15d,%r15d\njmpq 17c6 \ncallq 10d0 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\nmovsxd rsi, esi; nmemb\nmov edx, 10h; size\nlea rcx, compare_tuples; compar\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rsi\nsub rsp, 38h\nmov [rsp+68h+var_68], esi\nmov [rsp+68h+var_60], rdi\nmov rax, fs:28h\nmov [rsp+68h+var_40], rax\nxor eax, eax\ncall _qsort\nmov esi, 5Bh ; '['\nmov cs:result_1, si\ntest ebx, ebx\njle loc_18E8\nmov eax, [rsp+68h+var_68]\nxor r13d, r13d\nlea rbx, result_1\nlea esi, [rax-1]\ntest esi, esi\njg loc_179E\nloc_16AD:\nmov r14, [rsp+68h+var_60]\nmovsxd r10, r13d\nlea r12, unk_200B\nshl r10, 4\nadd r14, r10\nnop dword ptr [rax+rax+00h]\nloc_16C8:\nmov edx, 3E8h\nlea rsi, unk_2006\nmov rdi, rbx\ncall ___strcat_chk\nmov eax, [r14+8]\ntest eax, eax\njle short loc_173E\nxor ebp, ebp\nlea r15, [rsp+68h+var_58]\nnop dword ptr [rax+rax+00h]\nloc_16F0:\nmov rax, [r14]\nmov rcx, r12\nmov edx, 14h\nmov esi, 2\nmov rdi, r15\nmov r8d, [rax+rbp*4]\nxor eax, eax\ncall ___sprintf_chk\nmov rdi, rbx; s\ncall _strlen\nmov edx, 3E8h\nmov rsi, r15\nlea rdi, [rbx+rax]\ncall ___stpcpy_chk\nmov edx, [r14+8]\nlea ecx, [rdx-1]\ncmp ecx, ebp\njg loc_1880\nadd rbp, 1\ncmp edx, ebp\njg short loc_16F0\nloc_173E:\nmov edx, 3E8h\nmov rdi, rbx\nadd r13d, 1\nadd r14, 10h\nlea rsi, unk_200E\ncall ___strcat_chk\ncmp [rsp+68h+var_68], r13d\njg loc_16C8\nloc_1764:\nmov edx, 3E8h\nlea rsi, unk_2004\nmov rdi, rbx\ncall ___strcat_chk\nmov rax, [rsp+68h+var_40]\nsub rax, fs:28h\njnz loc_18F4\nadd rsp, 38h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_179E:\nmov rax, [rsp+68h+var_60]\nmov [rsp+68h+var_64], esi\nlea r12, unk_200B\nlea r14, [rax+8]\nloc_17B2:\nmov edx, 3E8h\nmov rdi, rbx\nlea r15, [rsp+68h+var_58]\nxor ebp, ebp\nlea rsi, unk_2006\ncall ___strcat_chk\nmov ecx, [r14]\ntest ecx, ecx\njle short loc_1826\nnop dword ptr [rax+00h]\nloc_17D8:\nmov rax, [r14-8]\nmov rcx, r12\nmov edx, 14h\nmov rdi, r15\nmov esi, 2\nmov r8d, [rax+rbp*4]\nxor eax, eax\ncall ___sprintf_chk\nmov rdi, rbx; s\ncall _strlen\nmov edx, 3E8h\nmov rsi, r15\nlea rdi, [rbx+rax]\ncall ___stpcpy_chk\nmov edx, [r14]\nlea ecx, [rdx-1]\ncmp ecx, ebp\njg loc_18B8\nadd rbp, 1\ncmp edx, ebp\njg short loc_17D8\nloc_1826:\nmov rdi, rbx; s\nadd r13d, 1\nadd r14, 10h\ncall _strlen\nmov edx, 29h ; ')'\nlea rcx, _end\nlea rsi, unk_2008\nlea rdi, [rbx+rax]\nmov [rdi], dx\nadd rdi, 1\nmov edx, 3\nsub rcx, rdi\ncall ___memcpy_chk\ncmp [rsp+68h+var_64], r13d\njg loc_17B2\ncmp [rsp+68h+var_68], r13d\njg loc_16AD\njmp loc_1764\nloc_1880:\nlea rcx, _end\nmov edx, 3\nmov rdi, rax\nadd rbp, 1\nsub rcx, rax\nlea rsi, unk_2008\ncall ___memcpy_chk\ncmp [r14+8], ebp\njg loc_16F0\njmp loc_173E\nloc_18B8:\nlea rcx, _end\nmov edx, 3\nmov rdi, rax\nadd rbp, 1\nsub rcx, rax\nlea rsi, unk_2008\ncall ___memcpy_chk\ncmp [r14], ebp\njg loc_17D8\njmp loc_1826\nloc_18E8:\nlea rbx, result_1\njmp loc_1764\nloc_18F4:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(_DWORD *a1, int a2)\n{\n int v2; // r13d\n int v3; // esi\n char *v4; // r14\n __int64 v5; // rbp\n size_t v6; // rax\n __int64 v7; // rax\n int v8; // edx\n _DWORD *v10; // r14\n __int64 v11; // rbp\n size_t v12; // rax\n __int64 v13; // rax\n size_t v14; // rax\n _BYTE v16[24]; // [rsp+10h] [rbp-58h] BYREF\n unsigned __int64 v17; // [rsp+28h] [rbp-40h]\n\n v17 = __readfsqword(0x28u);\n qsort(a1, a2, 0x10uLL, compare_tuples);\n strcpy(result_1, \"[\");\n if ( a2 > 0 )\n {\n v2 = 0;\n v3 = a2 - 1;\n if ( a2 - 1 <= 0 )\n goto LABEL_3;\n v10 = a1 + 2;\n do\n {\n v11 = 0LL;\n __strcat_chk(result_1, &unk_2006, 1000LL);\n if ( (int)*v10 > 0 )\n {\n do\n {\n while ( 1 )\n {\n __sprintf_chk(v16, 2LL, 20LL, &unk_200B, *(unsigned int *)(*((_QWORD *)v10 - 1) + 4 * v11));\n v12 = strlen(result_1);\n v13 = __stpcpy_chk(&result_1[v12], v16, 1000LL);\n if ( *v10 - 1 > (int)v11 )\n break;\n if ( *v10 <= (int)++v11 )\n goto LABEL_14;\n }\n ++v11;\n __memcpy_chk(v13, &unk_2008, 3LL, (char *)&end - v13);\n }\n while ( *v10 > (int)v11 );\n }\nLABEL_14:\n ++v2;\n v10 += 4;\n v14 = strlen(result_1);\n *(_WORD *)&result_1[v14] = 41;\n __memcpy_chk(&result_1[v14 + 1], &unk_2008, 3LL, &end - (_UNKNOWN *)&result_1[v14 + 1]);\n }\n while ( v3 > v2 );\n if ( a2 > v2 )\n {\nLABEL_3:\n v4 = (char *)&a1[4 * v2];\n do\n {\n __strcat_chk(result_1, &unk_2006, 1000LL);\n if ( *((int *)v4 + 2) > 0 )\n {\n v5 = 0LL;\n do\n {\n while ( 1 )\n {\n __sprintf_chk(v16, 2LL, 20LL, &unk_200B, *(unsigned int *)(*(_QWORD *)v4 + 4 * v5));\n v6 = strlen(result_1);\n v7 = __stpcpy_chk(&result_1[v6], v16, 1000LL);\n v8 = *((_DWORD *)v4 + 2);\n if ( v8 - 1 > (int)v5 )\n break;\n if ( v8 <= (int)++v5 )\n goto LABEL_8;\n }\n ++v5;\n __memcpy_chk(v7, &unk_2008, 3LL, (char *)&end - v7);\n }\n while ( *((_DWORD *)v4 + 2) > (int)v5 );\n }\nLABEL_8:\n ++v2;\n v4 += 16;\n __strcat_chk(result_1, &unk_200E, 1000LL);\n }\n while ( a2 > v2 );\n }\n }\n __strcat_chk(result_1, &unk_2004, 1000LL);\n return result_1;\n}", + "ida_strip_asm": "sub_1640:\nendbr64\npush r15\nmovsxd rsi, esi; nmemb\nmov edx, 10h; size\nlea rcx, compar; compar\npush r14\npush r13\npush r12\npush rbp\npush rbx\nmov rbx, rsi\nsub rsp, 38h\nmov [rsp+68h+var_68], esi\nmov [rsp+68h+var_60], rdi\nmov rax, fs:28h\nmov [rsp+68h+var_40], rax\nxor eax, eax\ncall _qsort\nmov esi, 5Bh ; '['\nmov cs:s, si\ntest ebx, ebx\njle loc_18E8\nmov eax, [rsp+68h+var_68]\nxor r13d, r13d\nlea rbx, s\nlea esi, [rax-1]\ntest esi, esi\njg loc_179E\nloc_16AD:\nmov r14, [rsp+68h+var_60]\nmovsxd r10, r13d\nlea r12, unk_200B\nshl r10, 4\nadd r14, r10\nnop dword ptr [rax+rax+00h]\nloc_16C8:\nmov edx, 3E8h\nlea rsi, unk_2006\nmov rdi, rbx\ncall ___strcat_chk\nmov eax, [r14+8]\ntest eax, eax\njle short loc_173E\nxor ebp, ebp\nlea r15, [rsp+68h+var_58]\nnop dword ptr [rax+rax+00h]\nloc_16F0:\nmov rax, [r14]\nmov rcx, r12\nmov edx, 14h\nmov esi, 2\nmov rdi, r15\nmov r8d, [rax+rbp*4]\nxor eax, eax\ncall ___sprintf_chk\nmov rdi, rbx; s\ncall _strlen\nmov edx, 3E8h\nmov rsi, r15\nlea rdi, [rbx+rax]\ncall ___stpcpy_chk\nmov edx, [r14+8]\nlea ecx, [rdx-1]\ncmp ecx, ebp\njg loc_1880\nadd rbp, 1\ncmp edx, ebp\njg short loc_16F0\nloc_173E:\nmov edx, 3E8h\nmov rdi, rbx\nadd r13d, 1\nadd r14, 10h\nlea rsi, unk_200E\ncall ___strcat_chk\ncmp [rsp+68h+var_68], r13d\njg loc_16C8\nloc_1764:\nmov edx, 3E8h\nlea rsi, unk_2004\nmov rdi, rbx\ncall ___strcat_chk\nmov rax, [rsp+68h+var_40]\nsub rax, fs:28h\njnz loc_18F4\nadd rsp, 38h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_179E:\nmov rax, [rsp+68h+var_60]\nmov [rsp+68h+var_64], esi\nlea r12, unk_200B\nlea r14, [rax+8]\nloc_17B2:\nmov edx, 3E8h\nmov rdi, rbx\nlea r15, [rsp+68h+var_58]\nxor ebp, ebp\nlea rsi, unk_2006\ncall ___strcat_chk\nmov ecx, [r14]\ntest ecx, ecx\njle short loc_1826\nnop dword ptr [rax+00h]\nloc_17D8:\nmov rax, [r14-8]\nmov rcx, r12\nmov edx, 14h\nmov rdi, r15\nmov esi, 2\nmov r8d, [rax+rbp*4]\nxor eax, eax\ncall ___sprintf_chk\nmov rdi, rbx; s\ncall _strlen\nmov edx, 3E8h\nmov rsi, r15\nlea rdi, [rbx+rax]\ncall ___stpcpy_chk\nmov edx, [r14]\nlea ecx, [rdx-1]\ncmp ecx, ebp\njg loc_18B8\nadd rbp, 1\ncmp edx, ebp\njg short loc_17D8\nloc_1826:\nmov rdi, rbx; s\nadd r13d, 1\nadd r14, 10h\ncall _strlen\nmov edx, 29h ; ')'\nlea rcx, __strcat_chk\nlea rsi, unk_2008\nlea rdi, [rbx+rax]\nmov [rdi], dx\nadd rdi, 1\nmov edx, 3\nsub rcx, rdi\ncall ___memcpy_chk\ncmp [rsp+68h+var_64], r13d\njg loc_17B2\ncmp [rsp+68h+var_68], r13d\njg loc_16AD\njmp loc_1764\nloc_1880:\nlea rcx, __strcat_chk\nmov edx, 3\nmov rdi, rax\nadd rbp, 1\nsub rcx, rax\nlea rsi, unk_2008\ncall ___memcpy_chk\ncmp [r14+8], ebp\njg loc_16F0\njmp loc_173E\nloc_18B8:\nlea rcx, __strcat_chk\nmov edx, 3\nmov rdi, rax\nadd rbp, 1\nsub rcx, rax\nlea rsi, unk_2008\ncall ___memcpy_chk\ncmp [r14], ebp\njg loc_17D8\njmp loc_1826\nloc_18E8:\nlea rbx, s\njmp loc_1764\nloc_18F4:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_1640(_DWORD *a1, int a2)\n{\n int v2; // r13d\n int v3; // esi\n char *v4; // r14\n __int64 v5; // rbp\n size_t v6; // rax\n __int64 v7; // rax\n int v8; // edx\n _DWORD *v10; // r14\n __int64 v11; // rbp\n size_t v12; // rax\n __int64 v13; // rax\n size_t v14; // rax\n _BYTE v16[24]; // [rsp+10h] [rbp-58h] BYREF\n unsigned __int64 v17; // [rsp+28h] [rbp-40h]\n\n v17 = __readfsqword(0x28u);\n qsort(a1, a2, 0x10uLL, compar);\n strcpy(s, \"[\");\n if ( a2 > 0 )\n {\n v2 = 0;\n v3 = a2 - 1;\n if ( a2 - 1 <= 0 )\n goto LABEL_3;\n v10 = a1 + 2;\n do\n {\n v11 = 0LL;\n __strcat_chk(s, &unk_2006, 1000LL);\n if ( (int)*v10 > 0 )\n {\n do\n {\n while ( 1 )\n {\n __sprintf_chk(v16, 2LL, 20LL, &unk_200B, *(unsigned int *)(*((_QWORD *)v10 - 1) + 4 * v11));\n v12 = strlen(s);\n v13 = __stpcpy_chk(&s[v12], v16, 1000LL);\n if ( *v10 - 1 > (int)v11 )\n break;\n if ( *v10 <= (int)++v11 )\n goto LABEL_14;\n }\n ++v11;\n __memcpy_chk(v13, &unk_2008, 3LL, (char *)&_strcat_chk - v13);\n }\n while ( *v10 > (int)v11 );\n }\nLABEL_14:\n ++v2;\n v10 += 4;\n v14 = strlen(s);\n *(_WORD *)&s[v14] = 41;\n __memcpy_chk(&s[v14 + 1], &unk_2008, 3LL, &_strcat_chk - (_UNKNOWN *)&s[v14 + 1]);\n }\n while ( v3 > v2 );\n if ( a2 > v2 )\n {\nLABEL_3:\n v4 = (char *)&a1[4 * v2];\n do\n {\n __strcat_chk(s, &unk_2006, 1000LL);\n if ( *((int *)v4 + 2) > 0 )\n {\n v5 = 0LL;\n do\n {\n while ( 1 )\n {\n __sprintf_chk(v16, 2LL, 20LL, &unk_200B, *(unsigned int *)(*(_QWORD *)v4 + 4 * v5));\n v6 = strlen(s);\n v7 = __stpcpy_chk(&s[v6], v16, 1000LL);\n v8 = *((_DWORD *)v4 + 2);\n if ( v8 - 1 > (int)v5 )\n break;\n if ( v8 <= (int)++v5 )\n goto LABEL_8;\n }\n ++v5;\n __memcpy_chk(v7, &unk_2008, 3LL, (char *)&_strcat_chk - v7);\n }\n while ( *((_DWORD *)v4 + 2) > (int)v5 );\n }\nLABEL_8:\n ++v2;\n v4 += 16;\n __strcat_chk(s, &unk_200E, 1000LL);\n }\n while ( a2 > v2 );\n }\n }\n __strcat_chk(s, &unk_2004, 1000LL);\n return s;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1640(uint32_t *a1, int a2) {\n int v2;\n int v3;\n char *v4;\n long long v5;\n unsigned int v6;\n long long v7;\n int v8;\n uint32_t *v10;\n long long v11;\n unsigned int v12;\n long long v13;\n unsigned int v14;\n uint8_t v16[24];\n unsigned long long v17;\n v17 = __readfsqword(40u);\n qsort(a1, a2, 16uLL, compar);\n strcpy(s, \"[\");\n if (a2 > 0) {\n v2 = 0;\n v3 = a2 - 1;\n if (a2 - 1 <= 0) goto LABEL_3;\n v10 = a1 + 2;\n do {\n v11 = 0LL;\n __strcat_chk(s, &unk_2006, 1000LL);\n if ((int)*v10 > 0) {\n do {\n while (1) {\n __sprintf_chk(v16, 2LL, 20LL, &unk_200B,\n *(unsigned int *)(*((uint64_t *)v10 - 1) + 4 * v11));\n v12 = strlen(s);\n v13 = __stpcpy_chk(&s[v12], v16, 1000LL);\n if (*v10 - 1 > (int)v11) break;\n if (*v10 <= (int)++v11) goto LABEL_14;\n }\n ++v11;\n __memcpy_chk(v13, &unk_2008, 3LL, (char *)&_strcat_chk - v13);\n } while (*v10 > (int)v11);\n }\n LABEL_14:\n ++v2;\n v10 += 4;\n v14 = strlen(s);\n *(unsigned short *)&s[v14] = 41;\n __memcpy_chk(&s[v14 + 1], &unk_2008, 3LL,\n &_strcat_chk - (void *)&s[v14 + 1]);\n } while (v3 > v2);\n if (a2 > v2) {\n LABEL_3:\n v4 = (char *)&a1[4 * v2];\n do {\n __strcat_chk(s, &unk_2006, 1000LL);\n if (*((int *)v4 + 2) > 0) {\n v5 = 0LL;\n do {\n while (1) {\n __sprintf_chk(v16, 2LL, 20LL, &unk_200B,\n *(unsigned int *)(*(uint64_t *)v4 + 4 * v5));\n v6 = strlen(s);\n v7 = __stpcpy_chk(&s[v6], v16, 1000LL);\n v8 = *((uint32_t *)v4 + 2);\n if (v8 - 1 > (int)v5) break;\n if (v8 <= (int)++v5) goto LABEL_8;\n }\n ++v5;\n __memcpy_chk(v7, &unk_2008, 3LL, (char *)&_strcat_chk - v7);\n } while (*((uint32_t *)v4 + 2) > (int)v5);\n }\n LABEL_8:\n ++v2;\n v4 += 16;\n __strcat_chk(s, &unk_200E, 1000LL);\n } while (a2 > v2);\n }\n }\n __strcat_chk(s, &unk_2004, 1000LL);\n return s;\n}", + "ida_pseudo_norm": "char *func0(uint32_t *a1, int a2) {\n int v2;\n int v3;\n char *v4;\n long long v5;\n unsigned int v6;\n long long v7;\n int v8;\n uint32_t *v10;\n long long v11;\n unsigned int v12;\n long long v13;\n unsigned int v14;\n uint8_t v16[24];\n unsigned long long v17;\n v17 = __readfsqword(40u);\n qsort(a1, a2, 16uLL, compare_tuples);\n strcpy(result_1, \"[\");\n if (a2 > 0) {\n v2 = 0;\n v3 = a2 - 1;\n if (a2 - 1 <= 0) goto LABEL_3;\n v10 = a1 + 2;\n do {\n v11 = 0LL;\n __strcat_chk(result_1, &unk_2006, 1000LL);\n if ((int)*v10 > 0) {\n do {\n while (1) {\n __sprintf_chk(v16, 2LL, 20LL, &unk_200B,\n *(unsigned int *)(*((uint64_t *)v10 - 1) + 4 * v11));\n v12 = strlen(result_1);\n v13 = __stpcpy_chk(&result_1[v12], v16, 1000LL);\n if (*v10 - 1 > (int)v11) break;\n if (*v10 <= (int)++v11) goto LABEL_14;\n }\n ++v11;\n __memcpy_chk(v13, &unk_2008, 3LL, (char *)&end - v13);\n } while (*v10 > (int)v11);\n }\n LABEL_14:\n ++v2;\n v10 += 4;\n v14 = strlen(result_1);\n *(unsigned short *)&result_1[v14] = 41;\n __memcpy_chk(&result_1[v14 + 1], &unk_2008, 3LL,\n &end - (void *)&result_1[v14 + 1]);\n } while (v3 > v2);\n if (a2 > v2) {\n LABEL_3:\n v4 = (char *)&a1[4 * v2];\n do {\n __strcat_chk(result_1, &unk_2006, 1000LL);\n if (*((int *)v4 + 2) > 0) {\n v5 = 0LL;\n do {\n while (1) {\n __sprintf_chk(v16, 2LL, 20LL, &unk_200B,\n *(unsigned int *)(*(uint64_t *)v4 + 4 * v5));\n v6 = strlen(result_1);\n v7 = __stpcpy_chk(&result_1[v6], v16, 1000LL);\n v8 = *((uint32_t *)v4 + 2);\n if (v8 - 1 > (int)v5) break;\n if (v8 <= (int)++v5) goto LABEL_8;\n }\n ++v5;\n __memcpy_chk(v7, &unk_2008, 3LL, (char *)&end - v7);\n } while (*((uint32_t *)v4 + 2) > (int)v5);\n }\n LABEL_8:\n ++v2;\n v4 += 16;\n __strcat_chk(result_1, &unk_200E, 1000LL);\n } while (a2 > v2);\n }\n }\n __strcat_chk(result_1, &unk_2004, 1000LL);\n return result_1;\n}" + }, + { + "index": 950, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "const char* func0(int year) {\n const char* sign;\n int remainder = (year - 2000) % 12;\n if (remainder < 0) {\n remainder += 12;\n }\n switch (remainder) {\n case 0:\n sign = \"Dragon\";\n break;\n case 1:\n sign = \"Snake\";\n break;\n case 2:\n sign = \"Horse\";\n break;\n case 3:\n sign = \"sheep\";\n break;\n case 4:\n sign = \"Monkey\";\n break;\n case 5:\n sign = \"Rooster\";\n break;\n case 6:\n sign = \"Dog\";\n break;\n case 7:\n sign = \"Pig\";\n break;\n case 8:\n sign = \"Rat\";\n break;\n case 9:\n sign = \"Ox\";\n break;\n case 10:\n sign = \"Tiger\";\n break;\n default:\n sign = \"Hare\";\n break;\n }\n return sign;\n}", + "test": "int main() {\n\n assert(strcmp(func0(1997), \"Ox\") == 0);\n\n assert(strcmp(func0(1998), \"Tiger\") == 0);\n\n assert(strcmp(func0(1994), \"Dog\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov -0x14(%rbp),%eax\nlea -0x7d0(%rax),%edx\nmovslq %edx,%rax\nimul $0x2aaaaaab,%rax,%rax\nshr $0x20,%rax\nmov %eax,%ecx\nsar %ecx\nmov %edx,%eax\nsar $0x1f,%eax\nsub %eax,%ecx\nmov %ecx,%eax\nmov %eax,-0xc(%rbp)\nmov -0xc(%rbp),%ecx\nmov %ecx,%eax\nadd %eax,%eax\nadd %ecx,%eax\nshl $0x2,%eax\nsub %eax,%edx\nmov %edx,%eax\nmov %eax,-0xc(%rbp)\ncmpl $0x0,-0xc(%rbp)\njns 11b8 \naddl $0xc,-0xc(%rbp)\ncmpl $0xa,-0xc(%rbp)\nja 127b \nmov -0xc(%rbp),%eax\nlea 0x0(,%rax,4),%rdx\nlea 0xe78(%rip),%rax\nmov (%rdx,%rax,1),%eax\ncltq\nlea 0xe6c(%rip),%rdx\nadd %rdx,%rax\nnotrack jmpq *%rax\nlea 0xe1b(%rip),%rax\nmov %rax,-0x8(%rbp)\njmpq 1287 \nlea 0xe12(%rip),%rax\nmov %rax,-0x8(%rbp)\njmpq 1287 \nlea 0xe08(%rip),%rax\nmov %rax,-0x8(%rbp)\njmp 1287 \nlea 0xe01(%rip),%rax\nmov %rax,-0x8(%rbp)\njmp 1287 \nlea 0xdfa(%rip),%rax\nmov %rax,-0x8(%rbp)\njmp 1287 \nlea 0xdf4(%rip),%rax\nmov %rax,-0x8(%rbp)\njmp 1287 \nlea 0xdef(%rip),%rax\nmov %rax,-0x8(%rbp)\njmp 1287 \nlea 0xde6(%rip),%rax\nmov %rax,-0x8(%rbp)\njmp 1287 \nlea 0xddd(%rip),%rax\nmov %rax,-0x8(%rbp)\njmp 1287 \nlea 0xdd4(%rip),%rax\nmov %rax,-0x8(%rbp)\njmp 1287 \nlea 0xdca(%rip),%rax\nmov %rax,-0x8(%rbp)\njmp 1287 \nlea 0xdc3(%rip),%rax\nmov %rax,-0x8(%rbp)\nmov -0x8(%rbp),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov eax, [rbp+var_14]\nlea edx, [rax-7D0h]\nmovsxd rax, edx\nimul rax, 2AAAAAABh\nshr rax, 20h\nsar eax, 1\nmov ecx, edx\nsar ecx, 1Fh\nsub eax, ecx\nmov [rbp+var_C], eax\nmov ecx, [rbp+var_C]\nmov eax, ecx\nadd eax, eax\nadd eax, ecx\nshl eax, 2\nsub edx, eax\nmov [rbp+var_C], edx\ncmp [rbp+var_C], 0\njns short loc_11B2\nadd [rbp+var_C], 0Ch\nloc_11B2:\ncmp [rbp+var_C], 0Ah; switch 11 cases\nja def_11DD; jumptable 00000000000011DD default case\nmov eax, [rbp+var_C]\nlea rdx, ds:0[rax*4]\nlea rax, jpt_11DD\nmov eax, ds:(jpt_11DD - 204Ch)[rdx+rax]\ncdqe\nlea rdx, jpt_11DD\nadd rax, rdx\njmp rax; switch jump\nloc_11E0:\nlea rax, aDragon; jumptable 00000000000011DD case 0\nmov [rbp+var_8], rax\njmp loc_1281\nloc_11F0:\nlea rax, aSnake; jumptable 00000000000011DD case 1\nmov [rbp+var_8], rax\njmp loc_1281\nloc_1200:\nlea rax, aHorse; jumptable 00000000000011DD case 2\nmov [rbp+var_8], rax\njmp short loc_1281\nloc_120D:\nlea rax, aSheep; jumptable 00000000000011DD case 3\nmov [rbp+var_8], rax\njmp short loc_1281\nloc_121A:\nlea rax, aMonkey; jumptable 00000000000011DD case 4\nmov [rbp+var_8], rax\njmp short loc_1281\nloc_1227:\nlea rax, aRooster; jumptable 00000000000011DD case 5\nmov [rbp+var_8], rax\njmp short loc_1281\nloc_1234:\nlea rax, aDog; jumptable 00000000000011DD case 6\nmov [rbp+var_8], rax\njmp short loc_1281\nloc_1241:\nlea rax, aPig; jumptable 00000000000011DD case 7\nmov [rbp+var_8], rax\njmp short loc_1281\nloc_124E:\nlea rax, aRat; jumptable 00000000000011DD case 8\nmov [rbp+var_8], rax\njmp short loc_1281\nloc_125B:\nlea rax, s2; jumptable 00000000000011DD case 9\nmov [rbp+var_8], rax\njmp short loc_1281\nloc_1268:\nlea rax, aTiger; jumptable 00000000000011DD case 10\nmov [rbp+var_8], rax\njmp short loc_1281\ndef_11DD:\nlea rax, aHare; jumptable 00000000000011DD default case\nmov [rbp+var_8], rax\nnop\nloc_1281:\nmov rax, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "const char *__fastcall func0(int a1)\n{\n const char *v2; // [rsp+Ch] [rbp-8h]\n\n switch ( (a1 - 2000) % 12 + ((a1 - 2000) % 12 < 0 ? 0xC : 0) )\n {\n case 0:\n v2 = \"Dragon\";\n break;\n case 1:\n v2 = \"Snake\";\n break;\n case 2:\n v2 = \"Horse\";\n break;\n case 3:\n v2 = \"sheep\";\n break;\n case 4:\n v2 = \"Monkey\";\n break;\n case 5:\n v2 = \"Rooster\";\n break;\n case 6:\n v2 = \"Dog\";\n break;\n case 7:\n v2 = \"Pig\";\n break;\n case 8:\n v2 = \"Rat\";\n break;\n case 9:\n v2 = \"Ox\";\n break;\n case 0xA:\n v2 = \"Tiger\";\n break;\n default:\n v2 = \"Hare\";\n break;\n }\n return v2;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov eax, [rbp+var_14]\nlea edx, [rax-7D0h]\nmovsxd rax, edx\nimul rax, 2AAAAAABh\nshr rax, 20h\nsar eax, 1\nmov ecx, edx\nsar ecx, 1Fh\nsub eax, ecx\nmov [rbp+var_C], eax\nmov ecx, [rbp+var_C]\nmov eax, ecx\nadd eax, eax\nadd eax, ecx\nshl eax, 2\nsub edx, eax\nmov [rbp+var_C], edx\ncmp [rbp+var_C], 0\njns short loc_11B2\nadd [rbp+var_C], 0Ch\nloc_11B2:\ncmp [rbp+var_C], 0Ah; switch 11 cases\nja def_11DD; jumptable 00000000000011DD default case\nmov eax, [rbp+var_C]\nlea rdx, ds:0[rax*4]\nlea rax, jpt_11DD\nmov eax, ds:(jpt_11DD - 204Ch)[rdx+rax]\ncdqe\nlea rdx, jpt_11DD\nadd rax, rdx\njmp rax; switch jump\nloc_11E0:\nlea rax, aDragon; jumptable 00000000000011DD case 0\nmov [rbp+var_8], rax\njmp loc_1281\nloc_11F0:\nlea rax, aSnake; jumptable 00000000000011DD case 1\nmov [rbp+var_8], rax\njmp loc_1281\nloc_1200:\nlea rax, aHorse; jumptable 00000000000011DD case 2\nmov [rbp+var_8], rax\njmp short loc_1281\nloc_120D:\nlea rax, aSheep; jumptable 00000000000011DD case 3\nmov [rbp+var_8], rax\njmp short loc_1281\nloc_121A:\nlea rax, aMonkey; jumptable 00000000000011DD case 4\nmov [rbp+var_8], rax\njmp short loc_1281\nloc_1227:\nlea rax, aRooster; jumptable 00000000000011DD case 5\nmov [rbp+var_8], rax\njmp short loc_1281\nloc_1234:\nlea rax, aDog; jumptable 00000000000011DD case 6\nmov [rbp+var_8], rax\njmp short loc_1281\nloc_1241:\nlea rax, aPig; jumptable 00000000000011DD case 7\nmov [rbp+var_8], rax\njmp short loc_1281\nloc_124E:\nlea rax, aRat; jumptable 00000000000011DD case 8\nmov [rbp+var_8], rax\njmp short loc_1281\nloc_125B:\nlea rax, s2; jumptable 00000000000011DD case 9\nmov [rbp+var_8], rax\njmp short loc_1281\nloc_1268:\nlea rax, aTiger; jumptable 00000000000011DD case 10\nmov [rbp+var_8], rax\njmp short loc_1281\ndef_11DD:\nlea rax, aHare; jumptable 00000000000011DD default case\nmov [rbp+var_8], rax\nnop\nloc_1281:\nmov rax, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1169(int a1)\n{\n const char *v2; // [rsp+Ch] [rbp-8h]\n\n switch ( (a1 - 2000) % 12 + ((a1 - 2000) % 12 < 0 ? 0xC : 0) )\n {\n case 0:\n v2 = \"Dragon\";\n break;\n case 1:\n v2 = \"Snake\";\n break;\n case 2:\n v2 = \"Horse\";\n break;\n case 3:\n v2 = \"sheep\";\n break;\n case 4:\n v2 = \"Monkey\";\n break;\n case 5:\n v2 = \"Rooster\";\n break;\n case 6:\n v2 = \"Dog\";\n break;\n case 7:\n v2 = \"Pig\";\n break;\n case 8:\n v2 = \"Rat\";\n break;\n case 9:\n v2 = \"Ox\";\n break;\n case 0xA:\n v2 = \"Tiger\";\n break;\n default:\n v2 = \"Hare\";\n break;\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1169(int a1) {\n const char *v2;\n switch ((a1 - 2000) % 12 + ((a1 - 2000) % 12 < 0 ? 12 : 0)) {\n case 0:\n v2 = \"Dragon\";\n break;\n case 1:\n v2 = \"Snake\";\n break;\n case 2:\n v2 = \"Horse\";\n break;\n case 3:\n v2 = \"sheep\";\n break;\n case 4:\n v2 = \"Monkey\";\n break;\n case 5:\n v2 = \"Rooster\";\n break;\n case 6:\n v2 = \"Dog\";\n break;\n case 7:\n v2 = \"Pig\";\n break;\n case 8:\n v2 = \"Rat\";\n break;\n case 9:\n v2 = \"Ox\";\n break;\n case 10:\n v2 = \"Tiger\";\n break;\n default:\n v2 = \"Hare\";\n break;\n }\n return v2;\n}", + "ida_pseudo_norm": "const char *func0(int a1) {\n const char *v2;\n switch ((a1 - 2000) % 12 + ((a1 - 2000) % 12 < 0 ? 12 : 0)) {\n case 0:\n v2 = \"Dragon\";\n break;\n case 1:\n v2 = \"Snake\";\n break;\n case 2:\n v2 = \"Horse\";\n break;\n case 3:\n v2 = \"sheep\";\n break;\n case 4:\n v2 = \"Monkey\";\n break;\n case 5:\n v2 = \"Rooster\";\n break;\n case 6:\n v2 = \"Dog\";\n break;\n case 7:\n v2 = \"Pig\";\n break;\n case 8:\n v2 = \"Rat\";\n break;\n case 9:\n v2 = \"Ox\";\n break;\n case 10:\n v2 = \"Tiger\";\n break;\n default:\n v2 = \"Hare\";\n break;\n }\n return v2;\n}" + }, + { + "index": 951, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n} Pair;\n\n\n\n", + "func": "Pair *func0(Pair *test_list1, Pair *test_list2, int size) {\n static Pair res[3];\n for (int i = 0; i < size; i++) {\n res[i].first = test_list1[i].first > test_list2[i].first\n ? test_list1[i].first\n : test_list2[i].first;\n res[i].second = test_list1[i].second > test_list2[i].second\n ? test_list1[i].second\n : test_list2[i].second;\n }\n return res;\n}", + "test": "int main() {\n\n Pair test_list1[3] = {{2, 4}, {6, 7}, {5, 1}};\n\n Pair test_list2[3] = {{5, 4}, {8, 10}, {8, 14}};\n\n Pair expected1[3] = {{5, 4}, {8, 10}, {8, 14}};\n\n Pair *result1 = func0(test_list1, test_list2, 3);\n\n for (int i = 0; i < 3; i++) {\n\n assert(result1[i].first == expected1[i].first && result1[i].second == expected1[i].second);\n\n }\n\n \n\n Pair test_list3[3] = {{3, 5}, {7, 8}, {6, 2}};\n\n Pair test_list4[3] = {{6, 5}, {9, 11}, {9, 15}};\n\n Pair expected2[3] = {{6, 5}, {9, 11}, {9, 15}};\n\n Pair *result2 = func0(test_list3, test_list4, 3);\n\n for (int i = 0; i < 3; i++) {\n\n assert(result2[i].first == expected2[i].first && result2[i].second == expected2[i].second);\n\n }\n\n \n\n Pair test_list5[3] = {{4, 6}, {8, 9}, {7, 3}};\n\n Pair test_list6[3] = {{7, 6}, {10, 12}, {10, 16}};\n\n Pair expected3[3] = {{7, 6}, {10, 12}, {10, 16}};\n\n Pair *result3 = func0(test_list5, test_list6, 3);\n\n for (int i = 0; i < 3; i++) {\n\n assert(result3[i].first == expected3[i].first && result3[i].second == expected3[i].second);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %rsi,-0x20(%rbp)\nmov %edx,-0x24(%rbp)\nmovl $0x0,-0x4(%rbp)\njmpq 1220 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\ncmovge %edx,%eax\nmov -0x4(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nlea 0x2e52(%rip),%rdx\nmov %eax,(%rcx,%rdx,1)\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x20(%rbp),%rax\nadd %rdx,%rax\nmov 0x4(%rax),%edx\nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov 0x4(%rax),%eax\ncmp %eax,%edx\ncmovge %edx,%eax\nmov -0x4(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nlea 0x2e0b(%rip),%rdx\nmov %eax,(%rcx,%rdx,1)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x24(%rbp),%eax\njl 1188 \nlea 0x2ded(%rip),%rax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_4], 0\njmp loc_1220\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\ncmovge eax, edx\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nlea rdx, res_1\nmov [rcx+rdx], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov edx, [rax+4]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax+4]\ncmp edx, eax\ncmovge eax, edx\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nlea rdx, unk_4024\nmov [rcx+rdx], eax\nadd [rbp+var_4], 1\nloc_1220:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_24]\njl loc_1188\nlea rax, res_1\npop rbp\nretn", + "ida_pseudo": "void *__fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n int v3; // eax\n int v4; // eax\n int i; // [rsp+20h] [rbp-4h]\n\n for ( i = 0; i < a3; ++i )\n {\n v3 = *(_DWORD *)(8LL * i + a1);\n if ( *(_DWORD *)(8LL * i + a2) >= v3 )\n v3 = *(_DWORD *)(8LL * i + a2);\n *((_DWORD *)&res_1 + 2 * i) = v3;\n v4 = *(_DWORD *)(8LL * i + a1 + 4);\n if ( *(_DWORD *)(8LL * i + a2 + 4) >= v4 )\n v4 = *(_DWORD *)(8LL * i + a2 + 4);\n dword_4024[2 * i] = v4;\n }\n return &res_1;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_20], rsi\nmov [rbp+var_24], edx\nmov [rbp+var_4], 0\njmp loc_1220\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\ncmovge eax, edx\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nlea rdx, unk_4020\nmov [rcx+rdx], eax\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_20]\nadd rax, rdx\nmov edx, [rax+4]\nmov eax, [rbp+var_4]\ncdqe\nlea rcx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov eax, [rax+4]\ncmp edx, eax\ncmovge eax, edx\nmov edx, [rbp+var_4]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nlea rdx, unk_4024\nmov [rcx+rdx], eax\nadd [rbp+var_4], 1\nloc_1220:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_24]\njl loc_1188\nlea rax, unk_4020\npop rbp\nretn", + "ida_strip_pseudo": "void *__fastcall sub_1169(__int64 a1, __int64 a2, int a3)\n{\n int v3; // eax\n int v4; // eax\n int i; // [rsp+20h] [rbp-4h]\n\n for ( i = 0; i < a3; ++i )\n {\n v3 = *(_DWORD *)(8LL * i + a1);\n if ( *(_DWORD *)(8LL * i + a2) >= v3 )\n v3 = *(_DWORD *)(8LL * i + a2);\n *((_DWORD *)&unk_4020 + 2 * i) = v3;\n v4 = *(_DWORD *)(8LL * i + a1 + 4);\n if ( *(_DWORD *)(8LL * i + a2 + 4) >= v4 )\n v4 = *(_DWORD *)(8LL * i + a2 + 4);\n dword_4024[2 * i] = v4;\n }\n return &unk_4020;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "void *sub_1169(long long a1, long long a2, int a3) {\n int v3;\n int v4;\n int i;\n for (i = 0; i < a3; ++i) {\n v3 = *(uint32_t *)(8LL * i + a1);\n if (*(uint32_t *)(8LL * i + a2) >= v3) v3 = *(uint32_t *)(8LL * i + a2);\n *((uint32_t *)&unk_4020 + 2 * i) = v3;\n v4 = *(uint32_t *)(8LL * i + a1 + 4);\n if (*(uint32_t *)(8LL * i + a2 + 4) >= v4)\n v4 = *(uint32_t *)(8LL * i + a2 + 4);\n dword_4024[2 * i] = v4;\n }\n return &unk_4020;\n}", + "ida_pseudo_norm": "void *func0(long long a1, long long a2, int a3) {\n int v3;\n int v4;\n int i;\n for (i = 0; i < a3; ++i) {\n v3 = *(uint32_t *)(8LL * i + a1);\n if (*(uint32_t *)(8LL * i + a2) >= v3) v3 = *(uint32_t *)(8LL * i + a2);\n *((uint32_t *)&res_1 + 2 * i) = v3;\n v4 = *(uint32_t *)(8LL * i + a1 + 4);\n if (*(uint32_t *)(8LL * i + a2 + 4) >= v4)\n v4 = *(uint32_t *)(8LL * i + a2 + 4);\n dword_4024[2 * i] = v4;\n }\n return &res_1;\n}" + }, + { + "index": 951, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n} Pair;\n\n\n\n", + "func": "Pair *func0(Pair *test_list1, Pair *test_list2, int size) {\n static Pair res[3];\n for (int i = 0; i < size; i++) {\n res[i].first = test_list1[i].first > test_list2[i].first\n ? test_list1[i].first\n : test_list2[i].first;\n res[i].second = test_list1[i].second > test_list2[i].second\n ? test_list1[i].second\n : test_list2[i].second;\n }\n return res;\n}", + "test": "int main() {\n\n Pair test_list1[3] = {{2, 4}, {6, 7}, {5, 1}};\n\n Pair test_list2[3] = {{5, 4}, {8, 10}, {8, 14}};\n\n Pair expected1[3] = {{5, 4}, {8, 10}, {8, 14}};\n\n Pair *result1 = func0(test_list1, test_list2, 3);\n\n for (int i = 0; i < 3; i++) {\n\n assert(result1[i].first == expected1[i].first && result1[i].second == expected1[i].second);\n\n }\n\n \n\n Pair test_list3[3] = {{3, 5}, {7, 8}, {6, 2}};\n\n Pair test_list4[3] = {{6, 5}, {9, 11}, {9, 15}};\n\n Pair expected2[3] = {{6, 5}, {9, 11}, {9, 15}};\n\n Pair *result2 = func0(test_list3, test_list4, 3);\n\n for (int i = 0; i < 3; i++) {\n\n assert(result2[i].first == expected2[i].first && result2[i].second == expected2[i].second);\n\n }\n\n \n\n Pair test_list5[3] = {{4, 6}, {8, 9}, {7, 3}};\n\n Pair test_list6[3] = {{7, 6}, {10, 12}, {10, 16}};\n\n Pair expected3[3] = {{7, 6}, {10, 12}, {10, 16}};\n\n Pair *result3 = func0(test_list5, test_list6, 3);\n\n for (int i = 0; i < 3; i++) {\n\n assert(result3[i].first == expected3[i].first && result3[i].second == expected3[i].second);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %edx,%edx\njle 11a8 \nmov $0x0,%eax\nlea 0x2ea3(%rip),%r9\nlea 0x4(%r9),%r8\nmov (%rdi,%rax,8),%ecx\ncmp %ecx,(%rsi,%rax,8)\ncmovge (%rsi,%rax,8),%ecx\nmov %ecx,(%r9,%rax,8)\nmov 0x4(%rdi,%rax,8),%ecx\ncmp %ecx,0x4(%rsi,%rax,8)\ncmovge 0x4(%rsi,%rax,8),%ecx\nmov %ecx,(%r8,%rax,8)\nadd $0x1,%rax\ncmp %eax,%edx\njg 1181 \nlea 0x2e71(%rip),%rax\nretq\n", + "ida_asm": "func0:\nendbr64\ntest edx, edx\njle short loc_11B3\nmovsxd rdx, edx\nmov eax, 0\nlea r10, res_1\nlea r9, [r10+4]\nloc_1184:\nmov ecx, [rsi+rax*8]\nmov r8d, [rdi+rax*8]\ncmp ecx, r8d\ncmovl ecx, r8d\nmov [r10+rax*8], ecx\nmov ecx, [rsi+rax*8+4]\nmov r8d, [rdi+rax*8+4]\ncmp ecx, r8d\ncmovl ecx, r8d\nmov [r9+rax*8], ecx\nadd rax, 1\ncmp rdx, rax\njnz short loc_1184\nloc_11B3:\nlea rax, res_1\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n __int64 i; // rax\n int v4; // ecx\n int v5; // ecx\n\n if ( a3 > 0 )\n {\n for ( i = 0LL; i != a3; res_1[2 * i++ + 1] = v5 )\n {\n v4 = *(_DWORD *)(a2 + 8 * i);\n if ( v4 < *(_DWORD *)(a1 + 8 * i) )\n v4 = *(_DWORD *)(a1 + 8 * i);\n res_1[2 * i] = v4;\n v5 = *(_DWORD *)(a2 + 8 * i + 4);\n if ( v5 < *(_DWORD *)(a1 + 8 * i + 4) )\n v5 = *(_DWORD *)(a1 + 8 * i + 4);\n }\n }\n return res_1;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest edx, edx\njle short loc_11B3\nmovsxd rdx, edx\nmov eax, 0\nlea r10, unk_4020\nlea r9, [r10+4]\nloc_1184:\nmov ecx, [rsi+rax*8]\nmov r8d, [rdi+rax*8]\ncmp ecx, r8d\ncmovl ecx, r8d\nmov [r10+rax*8], ecx\nmov ecx, [rsi+rax*8+4]\nmov r8d, [rdi+rax*8+4]\ncmp ecx, r8d\ncmovl ecx, r8d\nmov [r9+rax*8], ecx\nadd rax, 1\ncmp rdx, rax\njnz short loc_1184\nloc_11B3:\nlea rax, unk_4020\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_1169(__int64 a1, __int64 a2, int a3)\n{\n __int64 i; // rax\n int v4; // ecx\n int v5; // ecx\n\n if ( a3 > 0 )\n {\n for ( i = 0LL; i != a3; dword_4020[2 * i++ + 1] = v5 )\n {\n v4 = *(_DWORD *)(a2 + 8 * i);\n if ( v4 < *(_DWORD *)(a1 + 8 * i) )\n v4 = *(_DWORD *)(a1 + 8 * i);\n dword_4020[2 * i] = v4;\n v5 = *(_DWORD *)(a2 + 8 * i + 4);\n if ( v5 < *(_DWORD *)(a1 + 8 * i + 4) )\n v5 = *(_DWORD *)(a1 + 8 * i + 4);\n }\n }\n return dword_4020;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_1169(long long a1, long long a2, int a3) {\n long long i;\n int v4;\n int v5;\n if (a3 > 0) {\n for (i = 0LL; i != a3; dword_4020[2 * i++ + 1] = v5) {\n v4 = *(uint32_t *)(a2 + 8 * i);\n if (v4 < *(uint32_t *)(a1 + 8 * i)) v4 = *(uint32_t *)(a1 + 8 * i);\n dword_4020[2 * i] = v4;\n v5 = *(uint32_t *)(a2 + 8 * i + 4);\n if (v5 < *(uint32_t *)(a1 + 8 * i + 4))\n v5 = *(uint32_t *)(a1 + 8 * i + 4);\n }\n }\n return dword_4020;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, long long a2, int a3) {\n long long i;\n int v4;\n int v5;\n if (a3 > 0) {\n for (i = 0LL; i != a3; res_1[2 * i++ + 1] = v5) {\n v4 = *(uint32_t *)(a2 + 8 * i);\n if (v4 < *(uint32_t *)(a1 + 8 * i)) v4 = *(uint32_t *)(a1 + 8 * i);\n res_1[2 * i] = v4;\n v5 = *(uint32_t *)(a2 + 8 * i + 4);\n if (v5 < *(uint32_t *)(a1 + 8 * i + 4))\n v5 = *(uint32_t *)(a1 + 8 * i + 4);\n }\n }\n return res_1;\n}" + }, + { + "index": 951, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int first;\n\n int second;\n\n} Pair;\n\n\n\n", + "func": "Pair *func0(Pair *test_list1, Pair *test_list2, int size) {\n static Pair res[3];\n for (int i = 0; i < size; i++) {\n res[i].first = test_list1[i].first > test_list2[i].first\n ? test_list1[i].first\n : test_list2[i].first;\n res[i].second = test_list1[i].second > test_list2[i].second\n ? test_list1[i].second\n : test_list2[i].second;\n }\n return res;\n}", + "test": "int main() {\n\n Pair test_list1[3] = {{2, 4}, {6, 7}, {5, 1}};\n\n Pair test_list2[3] = {{5, 4}, {8, 10}, {8, 14}};\n\n Pair expected1[3] = {{5, 4}, {8, 10}, {8, 14}};\n\n Pair *result1 = func0(test_list1, test_list2, 3);\n\n for (int i = 0; i < 3; i++) {\n\n assert(result1[i].first == expected1[i].first && result1[i].second == expected1[i].second);\n\n }\n\n \n\n Pair test_list3[3] = {{3, 5}, {7, 8}, {6, 2}};\n\n Pair test_list4[3] = {{6, 5}, {9, 11}, {9, 15}};\n\n Pair expected2[3] = {{6, 5}, {9, 11}, {9, 15}};\n\n Pair *result2 = func0(test_list3, test_list4, 3);\n\n for (int i = 0; i < 3; i++) {\n\n assert(result2[i].first == expected2[i].first && result2[i].second == expected2[i].second);\n\n }\n\n \n\n Pair test_list5[3] = {{4, 6}, {8, 9}, {7, 3}};\n\n Pair test_list6[3] = {{7, 6}, {10, 12}, {10, 16}};\n\n Pair expected3[3] = {{7, 6}, {10, 12}, {10, 16}};\n\n Pair *result3 = func0(test_list5, test_list6, 3);\n\n for (int i = 0; i < 3; i++) {\n\n assert(result3[i].first == expected3[i].first && result3[i].second == expected3[i].second);\n\n }\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\ntest %edx,%edx\njle 147c \nlea 0x2bd1(%rip),%r9\nxor %eax,%eax\nlea 0x4(%r9),%r8\nmov (%rdi,%rax,8),%ecx\ncmp %ecx,(%rsi,%rax,8)\ncmovge (%rsi,%rax,8),%ecx\nmov %ecx,(%r9,%rax,8)\nmov 0x4(%rdi,%rax,8),%ecx\ncmp %ecx,0x4(%rsi,%rax,8)\ncmovge 0x4(%rsi,%rax,8),%ecx\nmov %ecx,(%r8,%rax,8)\nadd $0x1,%rax\ncmp %eax,%edx\njg 1455 \nlea 0x2b9d(%rip),%rax\nretq\nnopw %cs:0x0(%rax,%rax,1)\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\nlea r9, res_1\ntest edx, edx\njle short loc_1407\nmovsxd rdx, edx\nxor eax, eax\nlea r10, [r9+4]\nloc_13D8:\nmov r8d, [rdi+rax*8]\nmov ecx, [rsi+rax*8]\ncmp ecx, r8d\ncmovl ecx, r8d\nmov [r9+rax*8], ecx\nmov ecx, [rsi+rax*8+4]\nmov r8d, [rdi+rax*8+4]\ncmp ecx, r8d\ncmovl ecx, r8d\nmov [r10+rax*8], ecx\nadd rax, 1\ncmp rdx, rax\njnz short loc_13D8\nloc_1407:\nmov rax, r9\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, __int64 a2, int a3)\n{\n __int64 i; // rax\n int v4; // ecx\n int v5; // ecx\n\n if ( a3 > 0 )\n {\n for ( i = 0LL; i != a3; res_1[2 * i++ + 1] = v5 )\n {\n v4 = *(_DWORD *)(a2 + 8 * i);\n if ( v4 < *(_DWORD *)(a1 + 8 * i) )\n v4 = *(_DWORD *)(a1 + 8 * i);\n res_1[2 * i] = v4;\n v5 = *(_DWORD *)(a2 + 8 * i + 4);\n if ( v5 < *(_DWORD *)(a1 + 8 * i + 4) )\n v5 = *(_DWORD *)(a1 + 8 * i + 4);\n }\n }\n return res_1;\n}", + "ida_strip_asm": "sub_13C0:\nendbr64\nlea r9, unk_4020\ntest edx, edx\njle short loc_1407\nmovsxd rdx, edx\nxor eax, eax\nlea r10, [r9+4]\nloc_13D8:\nmov r8d, [rdi+rax*8]\nmov ecx, [rsi+rax*8]\ncmp ecx, r8d\ncmovl ecx, r8d\nmov [r9+rax*8], ecx\nmov ecx, [rsi+rax*8+4]\nmov r8d, [rdi+rax*8+4]\ncmp ecx, r8d\ncmovl ecx, r8d\nmov [r10+rax*8], ecx\nadd rax, 1\ncmp rdx, rax\njnz short loc_13D8\nloc_1407:\nmov rax, r9\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_13C0(__int64 a1, __int64 a2, int a3)\n{\n __int64 i; // rax\n int v4; // ecx\n int v5; // ecx\n\n if ( a3 > 0 )\n {\n for ( i = 0LL; i != a3; dword_4020[2 * i++ + 1] = v5 )\n {\n v4 = *(_DWORD *)(a2 + 8 * i);\n if ( v4 < *(_DWORD *)(a1 + 8 * i) )\n v4 = *(_DWORD *)(a1 + 8 * i);\n dword_4020[2 * i] = v4;\n v5 = *(_DWORD *)(a2 + 8 * i + 4);\n if ( v5 < *(_DWORD *)(a1 + 8 * i + 4) )\n v5 = *(_DWORD *)(a1 + 8 * i + 4);\n }\n }\n return dword_4020;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_13C0(long long a1, long long a2, int a3) {\n long long i;\n int v4;\n int v5;\n if (a3 > 0) {\n for (i = 0LL; i != a3; dword_4020[2 * i++ + 1] = v5) {\n v4 = *(uint32_t *)(a2 + 8 * i);\n if (v4 < *(uint32_t *)(a1 + 8 * i)) v4 = *(uint32_t *)(a1 + 8 * i);\n dword_4020[2 * i] = v4;\n v5 = *(uint32_t *)(a2 + 8 * i + 4);\n if (v5 < *(uint32_t *)(a1 + 8 * i + 4))\n v5 = *(uint32_t *)(a1 + 8 * i + 4);\n }\n }\n return dword_4020;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, long long a2, int a3) {\n long long i;\n int v4;\n int v5;\n if (a3 > 0) {\n for (i = 0LL; i != a3; res_1[2 * i++ + 1] = v5) {\n v4 = *(uint32_t *)(a2 + 8 * i);\n if (v4 < *(uint32_t *)(a1 + 8 * i)) v4 = *(uint32_t *)(a1 + 8 * i);\n res_1[2 * i] = v4;\n v5 = *(uint32_t *)(a2 + 8 * i + 4);\n if (v5 < *(uint32_t *)(a1 + 8 * i + 4))\n v5 = *(uint32_t *)(a1 + 8 * i + 4);\n }\n }\n return res_1;\n}" + }, + { + "index": 952, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n, int r, int p) {\n if (r > n - r) r = n - r;\n int C[r + 1];\n for (int i = 0; i <= r; i++) C[i] = 0;\n C[0] = 1;\n for (int i = 1; i <= n; i++) {\n for (int j = (i < r ? i : r); j > 0; j--) {\n C[j] = (C[j] + C[j - 1]) % p;\n }\n }\n return C[r];\n}", + "test": "int main() {\n\n assert(func0(10, 2, 13) == 6);\n\n assert(func0(11, 3, 14) == 11);\n\n assert(func0(18, 14, 19) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x48,%rsp\nmov %edi,-0x44(%rbp)\nmov %esi,-0x48(%rbp)\nmov %edx,-0x4c(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmov %rsp,%rax\nmov %rax,%rsi\nmov -0x44(%rbp),%eax\nsub -0x48(%rbp),%eax\ncmp %eax,-0x48(%rbp)\njle 11a8 \nmov -0x44(%rbp),%eax\nsub -0x48(%rbp),%eax\nmov %eax,-0x48(%rbp)\nmov -0x48(%rbp),%eax\nadd $0x1,%eax\nmovslq %eax,%rdx\nsub $0x1,%rdx\nmov %rdx,-0x28(%rbp)\nmovslq %eax,%rdx\nmov %rdx,%r8\nmov $0x0,%r9d\nmovslq %eax,%rdx\nmov %rdx,%rcx\nmov $0x0,%ebx\ncltq\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%edi\nmov $0x0,%edx\ndiv %rdi\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rbx\nsub %rdx,%rbx\nmov %rbx,%rdx\ncmp %rdx,%rsp\nje 1221 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 120a \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 124b \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x20(%rbp)\nmovl $0x0,-0x2c(%rbp)\njmp 127c \nmov -0x20(%rbp),%rax\nmov -0x2c(%rbp),%edx\nmovslq %edx,%rdx\nmovl $0x0,(%rax,%rdx,4)\naddl $0x1,-0x2c(%rbp)\nmov -0x2c(%rbp),%eax\ncmp -0x48(%rbp),%eax\njle 1267 \nmov -0x20(%rbp),%rax\nmovl $0x1,(%rax)\nmovl $0x1,-0x30(%rbp)\njmp 12e6 \nmov -0x30(%rbp),%eax\ncmp %eax,-0x48(%rbp)\ncmovle -0x48(%rbp),%eax\nmov %eax,-0x34(%rbp)\njmp 12dc \nmov -0x20(%rbp),%rax\nmov -0x34(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%ecx\nmov -0x34(%rbp),%eax\nlea -0x1(%rax),%edx\nmov -0x20(%rbp),%rax\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nadd %ecx,%eax\ncltd\nidivl -0x4c(%rbp)\nmov %edx,%ecx\nmov -0x20(%rbp),%rax\nmov -0x34(%rbp),%edx\nmovslq %edx,%rdx\nmov %ecx,(%rax,%rdx,4)\nsubl $0x1,-0x34(%rbp)\ncmpl $0x0,-0x34(%rbp)\njg 12a6 \naddl $0x1,-0x30(%rbp)\nmov -0x30(%rbp),%eax\ncmp -0x44(%rbp),%eax\njle 1297 \nmov -0x20(%rbp),%rax\nmov -0x48(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nmov %rsi,%rsp\nmov -0x18(%rbp),%rdi\nxor %fs:0x28,%rdi\nje 1312 \ncallq 1060 <__stack_chk_fail@plt>\nmov -0x8(%rbp),%rbx\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_34], edi\nmov [rbp+var_38], esi\nmov [rbp+var_3C], edx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov eax, [rbp+var_34]\nsub eax, [rbp+var_38]\ncmp [rbp+var_38], eax\njle short loc_11A7\nmov eax, [rbp+var_34]\nsub eax, [rbp+var_38]\nmov [rbp+var_38], eax\nloc_11A7:\nmov eax, [rbp+var_38]\nadd eax, 1\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11EF:\ncmp rsp, rdx\njz short loc_1206\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_11EF\nloc_1206:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1230\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1230:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov [rbp+var_24], 0\njmp short loc_1261\nloc_124C:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov dword ptr [rax+rdx*4], 0\nadd [rbp+var_24], 1\nloc_1261:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_38]\njle short loc_124C\nmov rax, [rbp+var_10]\nmov dword ptr [rax], 1\nmov [rbp+var_20], 1\njmp short loc_12CC\nloc_127C:\nmov edx, [rbp+var_38]\nmov eax, [rbp+var_20]\ncmp edx, eax\ncmovle eax, edx\nmov [rbp+var_1C], eax\njmp short loc_12C2\nloc_128C:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov eax, [rbp+var_1C]\nlea edx, [rax-1]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nadd eax, ecx\ncdq\nidiv [rbp+var_3C]\nmov ecx, edx\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nsub [rbp+var_1C], 1\nloc_12C2:\ncmp [rbp+var_1C], 0\njg short loc_128C\nadd [rbp+var_20], 1\nloc_12CC:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_34]\njle short loc_127C\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12F8\ncall ___stack_chk_fail\nlocret_12F8:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, int a3)\n{\n unsigned __int64 v3; // rax\n void *v4; // rsp\n int v5; // eax\n _BYTE v7[4]; // [rsp+8h] [rbp-40h] BYREF\n int v8; // [rsp+Ch] [rbp-3Ch]\n int v9; // [rsp+10h] [rbp-38h]\n int v10; // [rsp+14h] [rbp-34h]\n int i; // [rsp+24h] [rbp-24h]\n int j; // [rsp+28h] [rbp-20h]\n int k; // [rsp+2Ch] [rbp-1Ch]\n __int64 v14; // [rsp+30h] [rbp-18h]\n _DWORD *v15; // [rsp+38h] [rbp-10h]\n unsigned __int64 v16; // [rsp+40h] [rbp-8h]\n\n v10 = a1;\n v9 = a2;\n v8 = a3;\n v16 = __readfsqword(0x28u);\n if ( a2 > a1 - a2 )\n v9 = v10 - v9;\n v14 = v9 + 1 - 1LL;\n v3 = 16 * ((4LL * (v9 + 1) + 15) / 0x10uLL);\n while ( v7 != &v7[-(v3 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v4 = alloca(v3 & 0xFFF);\n if ( (v3 & 0xFFF) != 0 )\n *(_QWORD *)&v7[(v3 & 0xFFF) - 8] = *(_QWORD *)&v7[(v3 & 0xFFF) - 8];\n v15 = v7;\n for ( i = 0; i <= v9; ++i )\n v15[i] = 0;\n *v15 = 1;\n for ( j = 1; j <= v10; ++j )\n {\n v5 = j;\n if ( v9 <= j )\n v5 = v9;\n for ( k = v5; k > 0; --k )\n v15[k] = (v15[k] + v15[k - 1]) % v8;\n }\n return (unsigned int)v15[v9];\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 40h\nmov [rbp+var_34], edi\nmov [rbp+var_38], esi\nmov [rbp+var_3C], edx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov eax, [rbp+var_34]\nsub eax, [rbp+var_38]\ncmp [rbp+var_38], eax\njle short loc_11A7\nmov eax, [rbp+var_34]\nsub eax, [rbp+var_38]\nmov [rbp+var_38], eax\nloc_11A7:\nmov eax, [rbp+var_38]\nadd eax, 1\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11EF:\ncmp rsp, rdx\njz short loc_1206\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\njmp short loc_11EF\nloc_1206:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_1230\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_1230:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov [rbp+var_24], 0\njmp short loc_1261\nloc_124C:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov dword ptr [rax+rdx*4], 0\nadd [rbp+var_24], 1\nloc_1261:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_38]\njle short loc_124C\nmov rax, [rbp+var_10]\nmov dword ptr [rax], 1\nmov [rbp+var_20], 1\njmp short loc_12CC\nloc_127C:\nmov edx, [rbp+var_38]\nmov eax, [rbp+var_20]\ncmp edx, eax\ncmovle eax, edx\nmov [rbp+var_1C], eax\njmp short loc_12C2\nloc_128C:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov eax, [rbp+var_1C]\nlea edx, [rax-1]\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nadd eax, ecx\ncdq\nidiv [rbp+var_3C]\nmov ecx, edx\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov [rax+rdx*4], ecx\nsub [rbp+var_1C], 1\nloc_12C2:\ncmp [rbp+var_1C], 0\njg short loc_128C\nadd [rbp+var_20], 1\nloc_12CC:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_34]\njle short loc_127C\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_38]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_12F8\ncall ___stack_chk_fail\nlocret_12F8:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1, int a2, int a3)\n{\n unsigned __int64 v3; // rax\n void *v4; // rsp\n int v5; // eax\n _BYTE v7[4]; // [rsp+8h] [rbp-40h] BYREF\n int v8; // [rsp+Ch] [rbp-3Ch]\n int v9; // [rsp+10h] [rbp-38h]\n int v10; // [rsp+14h] [rbp-34h]\n int i; // [rsp+24h] [rbp-24h]\n int j; // [rsp+28h] [rbp-20h]\n int k; // [rsp+2Ch] [rbp-1Ch]\n __int64 v14; // [rsp+30h] [rbp-18h]\n _DWORD *v15; // [rsp+38h] [rbp-10h]\n unsigned __int64 v16; // [rsp+40h] [rbp-8h]\n\n v10 = a1;\n v9 = a2;\n v8 = a3;\n v16 = __readfsqword(0x28u);\n if ( a2 > a1 - a2 )\n v9 = v10 - v9;\n v14 = v9 + 1 - 1LL;\n v3 = 16 * ((4LL * (v9 + 1) + 15) / 0x10uLL);\n while ( v7 != &v7[-(v3 & 0xFFFFFFFFFFFFF000LL)] )\n ;\n v4 = alloca(v3 & 0xFFF);\n if ( (v3 & 0xFFF) != 0 )\n *(_QWORD *)&v7[(v3 & 0xFFF) - 8] = *(_QWORD *)&v7[(v3 & 0xFFF) - 8];\n v15 = v7;\n for ( i = 0; i <= v9; ++i )\n v15[i] = 0;\n *v15 = 1;\n for ( j = 1; j <= v10; ++j )\n {\n v5 = j;\n if ( v9 <= j )\n v5 = v9;\n for ( k = v5; k > 0; --k )\n v15[k] = (v15[k] + v15[k - 1]) % v8;\n }\n return (unsigned int)v15[v9];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1, int a2, int a3) {\n unsigned long long v3;\n void *v4;\n int v5;\n uint8_t v7[4];\n int v8;\n int v9;\n int v10;\n int i;\n int j;\n int k;\n long long v14;\n uint32_t *v15;\n unsigned long long v16;\n v10 = a1;\n v9 = a2;\n v8 = a3;\n v16 = __readfsqword(40u);\n if (a2 > a1 - a2) v9 = v10 - v9;\n v14 = v9 + 1 - 1LL;\n v3 = 16 * ((4LL * (v9 + 1) + 15) / 16uLL);\n while (v7 != &v7[-(v3 & 18446744073709547520LL)])\n ;\n v4 = alloca(v3 & 4095);\n if ((v3 & 4095) != 0)\n *(uint64_t *)&v7[(v3 & 4095) - 8] = *(uint64_t *)&v7[(v3 & 4095) - 8];\n v15 = v7;\n for (i = 0; i <= v9; ++i) v15[i] = 0;\n *v15 = 1;\n for (j = 1; j <= v10; ++j) {\n v5 = j;\n if (v9 <= j) v5 = v9;\n for (k = v5; k > 0; --k) v15[k] = (v15[k] + v15[k - 1]) % v8;\n }\n return (unsigned int)v15[v9];\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, int a3) {\n unsigned long long v3;\n void *v4;\n int v5;\n uint8_t v7[4];\n int v8;\n int v9;\n int v10;\n int i;\n int j;\n int k;\n long long v14;\n uint32_t *v15;\n unsigned long long v16;\n v10 = a1;\n v9 = a2;\n v8 = a3;\n v16 = __readfsqword(40u);\n if (a2 > a1 - a2) v9 = v10 - v9;\n v14 = v9 + 1 - 1LL;\n v3 = 16 * ((4LL * (v9 + 1) + 15) / 16uLL);\n while (v7 != &v7[-(v3 & 18446744073709547520LL)])\n ;\n v4 = alloca(v3 & 4095);\n if ((v3 & 4095) != 0)\n *(uint64_t *)&v7[(v3 & 4095) - 8] = *(uint64_t *)&v7[(v3 & 4095) - 8];\n v15 = v7;\n for (i = 0; i <= v9; ++i) v15[i] = 0;\n *v15 = 1;\n for (j = 1; j <= v10; ++j) {\n v5 = j;\n if (v9 <= j) v5 = v9;\n for (k = v5; k > 0; --k) v15[k] = (v15[k] + v15[k - 1]) % v8;\n }\n return (unsigned int)v15[v9];\n}" + }, + { + "index": 952, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n, int r, int p) {\n if (r > n - r) r = n - r;\n int C[r + 1];\n for (int i = 0; i <= r; i++) C[i] = 0;\n C[0] = 1;\n for (int i = 1; i <= n; i++) {\n for (int j = (i < r ? i : r); j > 0; j--) {\n C[j] = (C[j] + C[j - 1]) % p;\n }\n }\n return C[r];\n}", + "test": "int main() {\n\n assert(func0(10, 2, 13) == 6);\n\n assert(func0(11, 3, 14) == 11);\n\n assert(func0(18, 14, 19) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r12\npush %rbx\nsub $0x10,%rsp\nmov %edx,%r8d\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\nmov %edi,%r9d\nsub %esi,%r9d\ncmp %esi,%r9d\ncmovg %esi,%r9d\nlea 0x1(%r9),%eax\ncltq\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffffff0,%rdx\nand $0xfffffffffffff000,%rax\nmov %rsp,%rbx\nsub %rax,%rbx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 11d2 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11bb \nmov %rdx,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 11e8 \norq $0x0,-0x8(%rsp,%rax,1)\nlea 0x3(%rsp),%r12\nmov %r12,%rcx\nshr $0x2,%rcx\nand $0xfffffffffffffffc,%r12\nmov %r12,%r11\ntest %r9d,%r9d\njs 121a \nmov %r12,%rax\nmov %r9d,%edx\nlea 0x4(%r12,%rdx,4),%rdx\nmovl $0x0,(%rax)\nadd $0x4,%rax\ncmp %rdx,%rax\njne 120b \nmovl $0x1,0x0(,%rcx,4)\ntest %edi,%edi\njle 127b \nlea 0x1(%rdi),%r10d\nmov $0x1,%edi\nlea -0x4(%r11),%rbx\njmp 1240 \nadd $0x1,%edi\ncmp %r10d,%edi\nje 127b \ncmp %edi,%r9d\nmov %edi,%eax\ncmovle %r9d,%eax\ntest %eax,%eax\njle 1238 \nmovslq %eax,%rsi\nshl $0x2,%rsi\nlea (%r11,%rsi,1),%rcx\nadd %rbx,%rsi\nlea -0x1(%rax),%eax\nshl $0x2,%rax\nsub %rax,%rsi\nmov -0x4(%rcx),%eax\nadd (%rcx),%eax\ncltd\nidiv %r8d\nmov %edx,(%rcx)\nsub $0x4,%rcx\ncmp %rsi,%rcx\njne 1265 \njmp 1238 \nmovslq %r9d,%r9\nmov (%r12,%r9,4),%eax\nmov -0x18(%rbp),%rbx\nxor %fs:0x28,%rbx\njne 129a \nlea -0x10(%rbp),%rsp\npop %rbx\npop %r12\npop %rbp\nretq\ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 18h\nmov r10d, edi\nmov eax, esi\nmov esi, edx\nmov rdx, fs:28h\nmov [rbp+var_18], rdx\nxor edx, edx\nmov r9d, edi\nsub r9d, eax\ncmp r9d, eax\ncmovg r9d, eax\nlea eax, [r9+1]\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11BA:\ncmp rsp, rdx\njz short loc_11D1\nsub rsp, 1000h\nor [rsp+1020h+var_28], 0\njmp short loc_11BA\nloc_11D1:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11E7\nor [rsp+rax+20h+var_28], 0\nloc_11E7:\nlea r11, [rsp+20h+var_1D]\nmov rcx, r11\nshr rcx, 2\nand r11, 0FFFFFFFFFFFFFFFCh\ntest r9d, r9d\njs short loc_1216\nmov rax, r11\nlea edx, [r9+1]\nlea rdx, [r11+rdx*4]\nloc_1207:\nmov dword ptr [rax], 0\nadd rax, 4\ncmp rax, rdx\njnz short loc_1207\nloc_1216:\nmov ds:dword_0[rcx*4], 1\ntest r10d, r10d\njle short loc_1276\nadd r10d, 1\nmov r8d, 1\nlea rbx, [r11-4]\nloc_1234:\ncmp r9d, r8d\nmov eax, r8d\ncmovle eax, r9d\ntest eax, eax\njle short loc_126D\nmovsxd rdi, eax\nshl rdi, 2\nlea rcx, [r11+rdi]\nadd rdi, rbx\nlea eax, [rax-1]\nshl rax, 2\nsub rdi, rax\nloc_125A:\nmov eax, [rcx-4]\nadd eax, [rcx]\ncdq\nidiv esi\nmov [rcx], edx\nsub rcx, 4\ncmp rcx, rdi\njnz short loc_125A\nloc_126D:\nadd r8d, 1\ncmp r8d, r10d\njnz short loc_1234\nloc_1276:\nmovsxd r9, r9d\nmov eax, [r11+r9*4]\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njnz short loc_1292\nmov rbx, [rbp+var_8]\nleave\nretn\nloc_1292:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, int a3)\n{\n int v3; // r9d\n signed __int64 v4; // rax\n void *v5; // rsp\n _DWORD *v6; // rax\n int v7; // r10d\n int v8; // r8d\n int v9; // eax\n __int64 v10; // rdi\n int *v11; // rcx\n int *v12; // rdi\n _DWORD v15[2]; // [rsp+8h] [rbp-20h] BYREF\n unsigned __int64 v16; // [rsp+10h] [rbp-18h]\n\n v16 = __readfsqword(0x28u);\n v3 = a1 - a2;\n if ( a1 - a2 > a2 )\n v3 = a2;\n while ( v15 != (_DWORD *)((char *)v15 - ((4LL * (v3 + 1) + 15) & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v4 = (4 * ((_WORD)v3 + 1) + 15) & 0xFF0;\n v5 = alloca(v4);\n if ( ((4 * ((_WORD)v3 + 1) + 15) & 0xFF0) != 0 )\n *(_QWORD *)((char *)&v15[-2] + v4) = *(_QWORD *)((char *)&v15[-2] + v4);\n if ( v3 >= 0 )\n {\n v6 = v15;\n do\n *v6++ = 0;\n while ( v6 != &v15[v3 + 1] );\n }\n v15[0] = 1;\n if ( a1 > 0 )\n {\n v7 = a1 + 1;\n v8 = 1;\n do\n {\n v9 = v8;\n if ( v3 <= v8 )\n v9 = v3;\n if ( v9 > 0 )\n {\n v10 = v9;\n v11 = &v15[v10];\n v12 = &v15[v10 - 1 - (unsigned int)(v9 - 1)];\n do\n {\n *v11 = (*v11 + *(v11 - 1)) % a3;\n --v11;\n }\n while ( v11 != v12 );\n }\n ++v8;\n }\n while ( v8 != v7 );\n }\n return (unsigned int)v15[v3];\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 18h\nmov r10d, edi\nmov eax, esi\nmov esi, edx\nmov rdx, fs:28h\nmov [rbp+var_18], rdx\nxor edx, edx\nmov r9d, edi\nsub r9d, eax\ncmp r9d, eax\ncmovg r9d, eax\nlea eax, [r9+1]\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rax\nloc_11BA:\ncmp rsp, rdx\njz short loc_11D1\nsub rsp, 1000h\nor [rsp+1020h+var_28], 0\njmp short loc_11BA\nloc_11D1:\nmov rax, rcx\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11E7\nor [rsp+rax+20h+var_28], 0\nloc_11E7:\nlea r11, [rsp+20h+var_1D]\nmov rcx, r11\nshr rcx, 2\nand r11, 0FFFFFFFFFFFFFFFCh\ntest r9d, r9d\njs short loc_1216\nmov rax, r11\nlea edx, [r9+1]\nlea rdx, [r11+rdx*4]\nloc_1207:\nmov dword ptr [rax], 0\nadd rax, 4\ncmp rax, rdx\njnz short loc_1207\nloc_1216:\nmov ds:dword_0[rcx*4], 1\ntest r10d, r10d\njle short loc_1276\nadd r10d, 1\nmov r8d, 1\nlea rbx, [r11-4]\nloc_1234:\ncmp r9d, r8d\nmov eax, r8d\ncmovle eax, r9d\ntest eax, eax\njle short loc_126D\nmovsxd rdi, eax\nshl rdi, 2\nlea rcx, [r11+rdi]\nadd rdi, rbx\nlea eax, [rax-1]\nshl rax, 2\nsub rdi, rax\nloc_125A:\nmov eax, [rcx-4]\nadd eax, [rcx]\ncdq\nidiv esi\nmov [rcx], edx\nsub rcx, 4\ncmp rcx, rdi\njnz short loc_125A\nloc_126D:\nadd r8d, 1\ncmp r8d, r10d\njnz short loc_1234\nloc_1276:\nmovsxd r9, r9d\nmov eax, [r11+r9*4]\nmov rdx, [rbp+var_18]\nsub rdx, fs:28h\njnz short loc_1292\nmov rbx, [rbp+var_8]\nleave\nretn\nloc_1292:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1, int a2, int a3)\n{\n int v3; // r9d\n signed __int64 v4; // rax\n void *v5; // rsp\n _DWORD *v6; // rax\n int v7; // r10d\n int v8; // r8d\n int v9; // eax\n __int64 v10; // rdi\n int *v11; // rcx\n int *v12; // rdi\n _DWORD v15[2]; // [rsp+8h] [rbp-20h] BYREF\n unsigned __int64 v16; // [rsp+10h] [rbp-18h]\n\n v16 = __readfsqword(0x28u);\n v3 = a1 - a2;\n if ( a1 - a2 > a2 )\n v3 = a2;\n while ( v15 != (_DWORD *)((char *)v15 - ((4LL * (v3 + 1) + 15) & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v4 = (4 * ((_WORD)v3 + 1) + 15) & 0xFF0;\n v5 = alloca(v4);\n if ( ((4 * ((_WORD)v3 + 1) + 15) & 0xFF0) != 0 )\n *(_QWORD *)((char *)&v15[-2] + v4) = *(_QWORD *)((char *)&v15[-2] + v4);\n if ( v3 >= 0 )\n {\n v6 = v15;\n do\n *v6++ = 0;\n while ( v6 != &v15[v3 + 1] );\n }\n v15[0] = 1;\n if ( a1 > 0 )\n {\n v7 = a1 + 1;\n v8 = 1;\n do\n {\n v9 = v8;\n if ( v3 <= v8 )\n v9 = v3;\n if ( v9 > 0 )\n {\n v10 = v9;\n v11 = &v15[v10];\n v12 = &v15[v10 - 1 - (unsigned int)(v9 - 1)];\n do\n {\n *v11 = (*v11 + *(v11 - 1)) % a3;\n --v11;\n }\n while ( v11 != v12 );\n }\n ++v8;\n }\n while ( v8 != v7 );\n }\n return (unsigned int)v15[v3];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1, int a2, int a3) {\n int v3;\n signed long long v4;\n void *v5;\n uint32_t *v6;\n int v7;\n int v8;\n int v9;\n long long v10;\n int *v11;\n int *v12;\n uint32_t v15[2];\n unsigned long long v16;\n v16 = __readfsqword(40u);\n v3 = a1 - a2;\n if (a1 - a2 > a2) v3 = a2;\n while (v15 != (uint32_t *)((char *)v15 -\n ((4LL * (v3 + 1) + 15) & 18446744073709547520LL)))\n ;\n v4 = (4 * ((unsigned short)v3 + 1) + 15) & 4080;\n v5 = alloca(v4);\n if (((4 * ((unsigned short)v3 + 1) + 15) & 4080) != 0)\n *(uint64_t *)((char *)&v15[-2] + v4) = *(uint64_t *)((char *)&v15[-2] + v4);\n if (v3 >= 0) {\n v6 = v15;\n do\n *v6++ = 0;\n while (v6 != &v15[v3 + 1]);\n }\n v15[0] = 1;\n if (a1 > 0) {\n v7 = a1 + 1;\n v8 = 1;\n do {\n v9 = v8;\n if (v3 <= v8) v9 = v3;\n if (v9 > 0) {\n v10 = v9;\n v11 = &v15[v10];\n v12 = &v15[v10 - 1 - (unsigned int)(v9 - 1)];\n do {\n *v11 = (*v11 + *(v11 - 1)) % a3;\n --v11;\n } while (v11 != v12);\n }\n ++v8;\n } while (v8 != v7);\n }\n return (unsigned int)v15[v3];\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, int a3) {\n int v3;\n signed long long v4;\n void *v5;\n uint32_t *v6;\n int v7;\n int v8;\n int v9;\n long long v10;\n int *v11;\n int *v12;\n uint32_t v15[2];\n unsigned long long v16;\n v16 = __readfsqword(40u);\n v3 = a1 - a2;\n if (a1 - a2 > a2) v3 = a2;\n while (v15 != (uint32_t *)((char *)v15 -\n ((4LL * (v3 + 1) + 15) & 18446744073709547520LL)))\n ;\n v4 = (4 * ((unsigned short)v3 + 1) + 15) & 4080;\n v5 = alloca(v4);\n if (((4 * ((unsigned short)v3 + 1) + 15) & 4080) != 0)\n *(uint64_t *)((char *)&v15[-2] + v4) = *(uint64_t *)((char *)&v15[-2] + v4);\n if (v3 >= 0) {\n v6 = v15;\n do\n *v6++ = 0;\n while (v6 != &v15[v3 + 1]);\n }\n v15[0] = 1;\n if (a1 > 0) {\n v7 = a1 + 1;\n v8 = 1;\n do {\n v9 = v8;\n if (v3 <= v8) v9 = v3;\n if (v9 > 0) {\n v10 = v9;\n v11 = &v15[v10];\n v12 = &v15[v10 - 1 - (unsigned int)(v9 - 1)];\n do {\n *v11 = (*v11 + *(v11 - 1)) % a3;\n --v11;\n } while (v11 != v12);\n }\n ++v8;\n } while (v8 != v7);\n }\n return (unsigned int)v15[v3];\n}" + }, + { + "index": 952, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n, int r, int p) {\n if (r > n - r) r = n - r;\n int C[r + 1];\n for (int i = 0; i <= r; i++) C[i] = 0;\n C[0] = 1;\n for (int i = 1; i <= n; i++) {\n for (int j = (i < r ? i : r); j > 0; j--) {\n C[j] = (C[j] + C[j - 1]) % p;\n }\n }\n return C[r];\n}", + "test": "int main() {\n\n assert(func0(10, 2, 13) == 6);\n\n assert(func0(11, 3, 14) == 11);\n\n assert(func0(18, 14, 19) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %edi,%r9d\nmov %edx,%r8d\nsub %esi,%r9d\nmov %rsp,%rbp\npush %r12\npush %rbx\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x18(%rbp)\nxor %eax,%eax\ncmp %esi,%r9d\nmov %rsp,%rbx\ncmovg %esi,%r9d\nlea 0x1(%r9),%eax\ncltq\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rbx\nand $0xfffffffffffffff0,%rdx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 147c \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 1467 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 1549 \nlea 0x3(%rsp),%r11\nmovslq %r9d,%r12\nmov %r11,%rcx\nand $0xfffffffffffffffc,%r11\nshr $0x2,%rcx\ntest %r9d,%r9d\njs 14c7 \nmovslq %r9d,%r12\nmov %r11,%rax\nlea 0x4(%r11,%r12,4),%rdx\nnopl 0x0(%rax)\nmovl $0x0,(%rax)\nadd $0x4,%rax\ncmp %rdx,%rax\njne 14b8 \nmovl $0x1,0x0(,%rcx,4)\ntest %edi,%edi\njle 152d \nlea 0x1(%rdi),%r10d\nlea -0x4(%r11),%rbx\nmov $0x1,%edi\nnopl 0x0(%rax,%rax,1)\ncmp %edi,%r9d\nmov %edi,%eax\ncmovle %r9d,%eax\ntest %eax,%eax\njle 1525 \nmovslq %eax,%rsi\nsub $0x1,%eax\nshl $0x2,%rsi\nshl $0x2,%rax\nlea (%r11,%rsi,1),%rcx\nadd %rbx,%rsi\nsub %rax,%rsi\nnopl (%rax)\nmov -0x4(%rcx),%eax\nadd (%rcx),%eax\nsub $0x4,%rcx\ncltd\nidiv %r8d\nmov %edx,0x4(%rcx)\ncmp %rsi,%rcx\njne 1510 \nadd $0x1,%edi\ncmp %r10d,%edi\njne 14e8 \nmov -0x18(%rbp),%rbx\nxor %fs:0x28,%rbx\nmov (%r11,%r12,4),%eax\njne 1554 \nlea -0x10(%rbp),%rsp\npop %rbx\npop %r12\npop %rbp\nretq\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 148e \ncallq 1060 <__stack_chk_fail@plt>\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\nmov r15d, edi\npush r14\npush r13\npush r12\nmov r12d, edi\npush rbx\nsub r12d, esi\nmov ebx, edx\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\ncmp r12d, esi\nmov rcx, rsp\ncmovg r12d, esi\nlea eax, [r12+1]\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_12C2\nloc_12AD:\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\ncmp rsp, rcx\njnz short loc_12AD\nloc_12C2:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1391\nloc_12D4:\nlea r10, [rsp+1040h+var_103D]\nmovsxd r13, r12d\nmov r14, r10\nand r10, 0FFFFFFFFFFFFFFFCh\nshr r14, 2\ntest r12d, r12d\njs short loc_1301\nmov rdi, r10; s\nlea rdx, ds:4[r13*4]; n\nxor esi, esi; c\ncall _memset\nmov r10, rax\nloc_1301:\nmov ds:dword_0[r14*4], 1\ntest r15d, r15d\njle short loc_136F\nlea r9d, [r15+1]\nmov r8d, 1\nlea r11, [r10-4]\nloc_1320:\ncmp r12d, r8d\nmov eax, r8d\ncmovle eax, r12d\ntest eax, eax\njle short loc_1366\nmovsxd rdi, eax\nsub eax, 1\nshl rdi, 2\nshl rax, 2\nlea rcx, [r10+rdi]\nadd rdi, r11\nmov esi, [rcx]\nsub rdi, rax\nnop dword ptr [rax+rax+00000000h]\nloc_1350:\nmov eax, esi\nmov esi, [rcx-4]\nsub rcx, 4\nadd eax, esi\ncdq\nidiv ebx\nmov [rcx+4], edx\ncmp rcx, rdi\njnz short loc_1350\nloc_1366:\nadd r8d, 1\ncmp r8d, r9d\njnz short loc_1320\nloc_136F:\nmov eax, [r10+r13*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_139C\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1391:\nor [rsp+rdx+1040h+var_1048], 0\njmp loc_12D4\nloc_139C:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, int a3)\n{\n int v3; // r12d\n __int64 v5; // rdx\n _DWORD *v6; // rcx\n __int16 v7; // dx\n signed __int64 v8; // rdx\n void *v9; // rsp\n _DWORD *v10; // r10\n int v11; // r9d\n int v12; // r8d\n int v13; // eax\n __int64 v14; // rdi\n _DWORD *v15; // rcx\n int v16; // esi\n __int64 v17; // rdi\n int v18; // eax\n _DWORD v21[1022]; // [rsp+8h] [rbp-1040h] BYREF\n _QWORD v22[8]; // [rsp+1008h] [rbp-40h] BYREF\n\n v3 = a1 - a2;\n v22[1] = __readfsqword(0x28u);\n if ( a1 - a2 > a2 )\n v3 = a2;\n v5 = 4LL * (v3 + 1) + 15;\n v6 = (_DWORD *)((char *)v22 - (v5 & 0xFFFFFFFFFFFFF000LL));\n v7 = v5 & 0xFFF0;\n if ( v22 != (_QWORD *)v6 )\n {\n while ( v21 != v6 )\n ;\n }\n v8 = v7 & 0xFFF;\n v9 = alloca(v8);\n if ( v8 )\n *(_QWORD *)((char *)&v21[-2] + v8) = *(_QWORD *)((char *)&v21[-2] + v8);\n v10 = v21;\n if ( v3 >= 0 )\n v10 = memset(v21, 0, 4LL * v3 + 4);\n v21[0] = 1;\n if ( a1 > 0 )\n {\n v11 = a1 + 1;\n v12 = 1;\n do\n {\n v13 = v12;\n if ( v3 <= v12 )\n v13 = v3;\n if ( v13 > 0 )\n {\n v14 = v13;\n v15 = &v10[v14];\n v16 = v10[v14];\n v17 = (__int64)&v10[v14 - 1 - (unsigned int)(v13 - 1)];\n do\n {\n v18 = v16;\n v16 = *--v15;\n v15[1] = (v16 + v18) % a3;\n }\n while ( v15 != (_DWORD *)v17 );\n }\n ++v12;\n }\n while ( v12 != v11 );\n }\n return (unsigned int)v10[v3];\n}", + "ida_strip_asm": "sub_1250:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\nmov r15d, edi\npush r14\npush r13\npush r12\nmov r12d, edi\npush rbx\nsub r12d, esi\nmov ebx, edx\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\ncmp r12d, esi\nmov rcx, rsp\ncmovg r12d, esi\nlea eax, [r12+1]\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_12C2\nloc_12AD:\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\ncmp rsp, rcx\njnz short loc_12AD\nloc_12C2:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1391\nloc_12D4:\nlea r10, [rsp+1040h+var_103D]\nmovsxd r13, r12d\nmov r14, r10\nand r10, 0FFFFFFFFFFFFFFFCh\nshr r14, 2\ntest r12d, r12d\njs short loc_1301\nmov rdi, r10; s\nlea rdx, ds:4[r13*4]; n\nxor esi, esi; c\ncall _memset\nmov r10, rax\nloc_1301:\nmov ds:dword_0[r14*4], 1\ntest r15d, r15d\njle short loc_136F\nlea r9d, [r15+1]\nmov r8d, 1\nlea r11, [r10-4]\nloc_1320:\ncmp r12d, r8d\nmov eax, r8d\ncmovle eax, r12d\ntest eax, eax\njle short loc_1366\nmovsxd rdi, eax\nsub eax, 1\nshl rdi, 2\nshl rax, 2\nlea rcx, [r10+rdi]\nadd rdi, r11\nmov esi, [rcx]\nsub rdi, rax\nnop dword ptr [rax+rax+00000000h]\nloc_1350:\nmov eax, esi\nmov esi, [rcx-4]\nsub rcx, 4\nadd eax, esi\ncdq\nidiv ebx\nmov [rcx+4], edx\ncmp rcx, rdi\njnz short loc_1350\nloc_1366:\nadd r8d, 1\ncmp r8d, r9d\njnz short loc_1320\nloc_136F:\nmov eax, [r10+r13*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_139C\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1391:\nor [rsp+rdx+1040h+var_1048], 0\njmp loc_12D4\nloc_139C:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1250(int a1, int a2, int a3)\n{\n int v3; // r12d\n __int64 v5; // rdx\n _DWORD *v6; // rcx\n __int16 v7; // dx\n signed __int64 v8; // rdx\n void *v9; // rsp\n _DWORD *v10; // r10\n int v11; // r9d\n int v12; // r8d\n int v13; // eax\n __int64 v14; // rdi\n _DWORD *v15; // rcx\n int v16; // esi\n __int64 v17; // rdi\n int v18; // eax\n _DWORD v21[1022]; // [rsp+8h] [rbp-1040h] BYREF\n _QWORD v22[8]; // [rsp+1008h] [rbp-40h] BYREF\n\n v3 = a1 - a2;\n v22[1] = __readfsqword(0x28u);\n if ( a1 - a2 > a2 )\n v3 = a2;\n v5 = 4LL * (v3 + 1) + 15;\n v6 = (_DWORD *)((char *)v22 - (v5 & 0xFFFFFFFFFFFFF000LL));\n v7 = v5 & 0xFFF0;\n if ( v22 != (_QWORD *)v6 )\n {\n while ( v21 != v6 )\n ;\n }\n v8 = v7 & 0xFFF;\n v9 = alloca(v8);\n if ( v8 )\n *(_QWORD *)((char *)&v21[-2] + v8) = *(_QWORD *)((char *)&v21[-2] + v8);\n v10 = v21;\n if ( v3 >= 0 )\n v10 = memset(v21, 0, 4LL * v3 + 4);\n v21[0] = 1;\n if ( a1 > 0 )\n {\n v11 = a1 + 1;\n v12 = 1;\n do\n {\n v13 = v12;\n if ( v3 <= v12 )\n v13 = v3;\n if ( v13 > 0 )\n {\n v14 = v13;\n v15 = &v10[v14];\n v16 = v10[v14];\n v17 = (__int64)&v10[v14 - 1 - (unsigned int)(v13 - 1)];\n do\n {\n v18 = v16;\n v16 = *--v15;\n v15[1] = (v16 + v18) % a3;\n }\n while ( v15 != (_DWORD *)v17 );\n }\n ++v12;\n }\n while ( v12 != v11 );\n }\n return (unsigned int)v10[v3];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1250(int a1, int a2, int a3) {\n int v3;\n long long v5;\n uint32_t *v6;\n short v7;\n signed long long v8;\n void *v9;\n uint32_t *v10;\n int v11;\n int v12;\n int v13;\n long long v14;\n uint32_t *v15;\n int v16;\n long long v17;\n int v18;\n uint32_t v21[1022];\n uint64_t v22[8];\n v3 = a1 - a2;\n v22[1] = __readfsqword(40u);\n if (a1 - a2 > a2) v3 = a2;\n v5 = 4LL * (v3 + 1) + 15;\n v6 = (uint32_t *)((char *)v22 - (v5 & 18446744073709547520LL));\n v7 = v5 & 65520;\n if (v22 != (uint64_t *)v6) {\n while (v21 != v6)\n ;\n }\n v8 = v7 & 4095;\n v9 = alloca(v8);\n if (v8)\n *(uint64_t *)((char *)&v21[-2] + v8) = *(uint64_t *)((char *)&v21[-2] + v8);\n v10 = v21;\n if (v3 >= 0) v10 = memset(v21, 0, 4LL * v3 + 4);\n v21[0] = 1;\n if (a1 > 0) {\n v11 = a1 + 1;\n v12 = 1;\n do {\n v13 = v12;\n if (v3 <= v12) v13 = v3;\n if (v13 > 0) {\n v14 = v13;\n v15 = &v10[v14];\n v16 = v10[v14];\n v17 = (long long)&v10[v14 - 1 - (unsigned int)(v13 - 1)];\n do {\n v18 = v16;\n v16 = *--v15;\n v15[1] = (v16 + v18) % a3;\n } while (v15 != (uint32_t *)v17);\n }\n ++v12;\n } while (v12 != v11);\n }\n return (unsigned int)v10[v3];\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, int a3) {\n int v3;\n long long v5;\n uint32_t *v6;\n short v7;\n signed long long v8;\n void *v9;\n uint32_t *v10;\n int v11;\n int v12;\n int v13;\n long long v14;\n uint32_t *v15;\n int v16;\n long long v17;\n int v18;\n uint32_t v21[1022];\n uint64_t v22[8];\n v3 = a1 - a2;\n v22[1] = __readfsqword(40u);\n if (a1 - a2 > a2) v3 = a2;\n v5 = 4LL * (v3 + 1) + 15;\n v6 = (uint32_t *)((char *)v22 - (v5 & 18446744073709547520LL));\n v7 = v5 & 65520;\n if (v22 != (uint64_t *)v6) {\n while (v21 != v6)\n ;\n }\n v8 = v7 & 4095;\n v9 = alloca(v8);\n if (v8)\n *(uint64_t *)((char *)&v21[-2] + v8) = *(uint64_t *)((char *)&v21[-2] + v8);\n v10 = v21;\n if (v3 >= 0) v10 = memset(v21, 0, 4LL * v3 + 4);\n v21[0] = 1;\n if (a1 > 0) {\n v11 = a1 + 1;\n v12 = 1;\n do {\n v13 = v12;\n if (v3 <= v12) v13 = v3;\n if (v13 > 0) {\n v14 = v13;\n v15 = &v10[v14];\n v16 = v10[v14];\n v17 = (long long)&v10[v14 - 1 - (unsigned int)(v13 - 1)];\n do {\n v18 = v16;\n v16 = *--v15;\n v15[1] = (v16 + v18) % a3;\n } while (v15 != (uint32_t *)v17);\n }\n ++v12;\n } while (v12 != v11);\n }\n return (unsigned int)v10[v3];\n}" + }, + { + "index": 952, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n, int r, int p) {\n if (r > n - r) r = n - r;\n int C[r + 1];\n for (int i = 0; i <= r; i++) C[i] = 0;\n C[0] = 1;\n for (int i = 1; i <= n; i++) {\n for (int j = (i < r ? i : r); j > 0; j--) {\n C[j] = (C[j] + C[j - 1]) % p;\n }\n }\n return C[r];\n}", + "test": "int main() {\n\n assert(func0(10, 2, 13) == 6);\n\n assert(func0(11, 3, 14) == 11);\n\n assert(func0(18, 14, 19) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\nmov %edi,%r15d\npush %r14\npush %r13\npush %r12\nmov %edi,%r12d\npush %rbx\nsub %esi,%r12d\nmov %edx,%ebx\nsub $0x18,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\ncmp %esi,%r12d\nmov %rsp,%rdi\ncmovg %esi,%r12d\nlea 0x1(%r12),%eax\ncltq\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rdi\nand $0xfffffffffffffff0,%rdx\nmov %rdi,%rax\ncmp %rax,%rsp\nje 1895 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 1880 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 1961 \nlea 0x3(%rsp),%r10\nmovslq %r12d,%r13\nmov %r10,%r14\nand $0xfffffffffffffffc,%r10\nshr $0x2,%r14\ntest %r12d,%r12d\njs 18d4 \nmov %r10,%rdi\nlea 0x4(,%r13,4),%rdx\nxor %esi,%esi\ncallq 1090 \nmov %rax,%r10\nmovl $0x1,0x0(,%r14,4)\ntest %r15d,%r15d\njle 193f \nlea 0x1(%r15),%r9d\nmov $0x1,%r8d\nlea -0x4(%r10),%r11\nnopl 0x0(%rax,%rax,1)\ncmp %r8d,%r12d\nmov %r8d,%eax\ncmovle %r12d,%eax\ntest %eax,%eax\njle 1936 \nmovslq %eax,%rdi\nsub $0x1,%eax\nshl $0x2,%rdi\nshl $0x2,%rax\nlea (%r10,%rdi,1),%rcx\nadd %r11,%rdi\nmov (%rcx),%esi\nsub %rax,%rdi\nmov %esi,%eax\nmov -0x4(%rcx),%esi\nsub $0x4,%rcx\nadd %esi,%eax\ncltd\nidiv %ebx\nmov %edx,0x4(%rcx)\ncmp %rdi,%rcx\njne 1920 \nadd $0x1,%r8d\ncmp %r9d,%r8d\njne 18f8 \nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\nmov (%r10,%r13,4),%eax\njne 196c \nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 18a7 \ncallq 1070 <__stack_chk_fail@plt>\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\nmov r15d, edi\npush r14\npush r13\npush r12\nmov r12d, edi\npush rbx\nsub r12d, esi\nmov ebx, edx\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\ncmp r12d, esi\nmov rcx, rsp\ncmovg r12d, esi\nlea eax, [r12+1]\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_12C2\nloc_12AD:\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\ncmp rsp, rcx\njnz short loc_12AD\nloc_12C2:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1391\nloc_12D4:\nlea r10, [rsp+1040h+var_103D]\nmovsxd r13, r12d\nmov r14, r10\nand r10, 0FFFFFFFFFFFFFFFCh\nshr r14, 2\ntest r12d, r12d\njs short loc_1301\nmov rdi, r10; s\nlea rdx, ds:4[r13*4]; n\nxor esi, esi; c\ncall _memset\nmov r10, rax\nloc_1301:\nmov ds:dword_0[r14*4], 1\ntest r15d, r15d\njle short loc_136F\nlea r9d, [r15+1]\nmov r8d, 1\nlea r11, [r10-4]\nloc_1320:\ncmp r12d, r8d\nmov eax, r8d\ncmovle eax, r12d\ntest eax, eax\njle short loc_1366\nmovsxd rdi, eax\nsub eax, 1\nshl rdi, 2\nshl rax, 2\nlea rcx, [r10+rdi]\nadd rdi, r11\nmov esi, [rcx]\nsub rdi, rax\nnop dword ptr [rax+rax+00000000h]\nloc_1350:\nmov eax, esi\nmov esi, [rcx-4]\nsub rcx, 4\nadd eax, esi\ncdq\nidiv ebx\nmov [rcx+4], edx\ncmp rcx, rdi\njnz short loc_1350\nloc_1366:\nadd r8d, 1\ncmp r8d, r9d\njnz short loc_1320\nloc_136F:\nmov eax, [r10+r13*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_139C\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1391:\nor [rsp+rdx+1040h+var_1048], 0\njmp loc_12D4\nloc_139C:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, int a3)\n{\n int v3; // r12d\n __int64 v5; // rdx\n _DWORD *v6; // rcx\n __int16 v7; // dx\n signed __int64 v8; // rdx\n void *v9; // rsp\n _DWORD *v10; // r10\n int v11; // r9d\n int v12; // r8d\n int v13; // eax\n __int64 v14; // rdi\n _DWORD *v15; // rcx\n int v16; // esi\n __int64 v17; // rdi\n int v18; // eax\n _DWORD v21[1022]; // [rsp+8h] [rbp-1040h] BYREF\n _QWORD v22[8]; // [rsp+1008h] [rbp-40h] BYREF\n\n v3 = a1 - a2;\n v22[1] = __readfsqword(0x28u);\n if ( a1 - a2 > a2 )\n v3 = a2;\n v5 = 4LL * (v3 + 1) + 15;\n v6 = (_DWORD *)((char *)v22 - (v5 & 0xFFFFFFFFFFFFF000LL));\n v7 = v5 & 0xFFF0;\n if ( v22 != (_QWORD *)v6 )\n {\n while ( v21 != v6 )\n ;\n }\n v8 = v7 & 0xFFF;\n v9 = alloca(v8);\n if ( v8 )\n *(_QWORD *)((char *)&v21[-2] + v8) = *(_QWORD *)((char *)&v21[-2] + v8);\n v10 = v21;\n if ( v3 >= 0 )\n v10 = memset(v21, 0, 4LL * v3 + 4);\n v21[0] = 1;\n if ( a1 > 0 )\n {\n v11 = a1 + 1;\n v12 = 1;\n do\n {\n v13 = v12;\n if ( v3 <= v12 )\n v13 = v3;\n if ( v13 > 0 )\n {\n v14 = v13;\n v15 = &v10[v14];\n v16 = v10[v14];\n v17 = (__int64)&v10[v14 - 1 - (unsigned int)(v13 - 1)];\n do\n {\n v18 = v16;\n v16 = *--v15;\n v15[1] = (v16 + v18) % a3;\n }\n while ( v15 != (_DWORD *)v17 );\n }\n ++v12;\n }\n while ( v12 != v11 );\n }\n return (unsigned int)v10[v3];\n}", + "ida_strip_asm": "sub_1250:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\nmov r15d, edi\npush r14\npush r13\npush r12\nmov r12d, edi\npush rbx\nsub r12d, esi\nmov ebx, edx\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\ncmp r12d, esi\nmov rcx, rsp\ncmovg r12d, esi\nlea eax, [r12+1]\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rdx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rcx, rax\nand rdx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rcx\njz short loc_12C2\nloc_12AD:\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\ncmp rsp, rcx\njnz short loc_12AD\nloc_12C2:\nand edx, 0FFFh\nsub rsp, rdx\ntest rdx, rdx\njnz loc_1391\nloc_12D4:\nlea r10, [rsp+1040h+var_103D]\nmovsxd r13, r12d\nmov r14, r10\nand r10, 0FFFFFFFFFFFFFFFCh\nshr r14, 2\ntest r12d, r12d\njs short loc_1301\nmov rdi, r10; s\nlea rdx, ds:4[r13*4]; n\nxor esi, esi; c\ncall _memset\nmov r10, rax\nloc_1301:\nmov ds:dword_0[r14*4], 1\ntest r15d, r15d\njle short loc_136F\nlea r9d, [r15+1]\nmov r8d, 1\nlea r11, [r10-4]\nloc_1320:\ncmp r12d, r8d\nmov eax, r8d\ncmovle eax, r12d\ntest eax, eax\njle short loc_1366\nmovsxd rdi, eax\nsub eax, 1\nshl rdi, 2\nshl rax, 2\nlea rcx, [r10+rdi]\nadd rdi, r11\nmov esi, [rcx]\nsub rdi, rax\nnop dword ptr [rax+rax+00000000h]\nloc_1350:\nmov eax, esi\nmov esi, [rcx-4]\nsub rcx, 4\nadd eax, esi\ncdq\nidiv ebx\nmov [rcx+4], edx\ncmp rcx, rdi\njnz short loc_1350\nloc_1366:\nadd r8d, 1\ncmp r8d, r9d\njnz short loc_1320\nloc_136F:\nmov eax, [r10+r13*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_139C\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_1391:\nor [rsp+rdx+1040h+var_1048], 0\njmp loc_12D4\nloc_139C:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1250(int a1, int a2, int a3)\n{\n int v3; // r12d\n __int64 v5; // rdx\n _DWORD *v6; // rcx\n __int16 v7; // dx\n signed __int64 v8; // rdx\n void *v9; // rsp\n _DWORD *v10; // r10\n int v11; // r9d\n int v12; // r8d\n int v13; // eax\n __int64 v14; // rdi\n _DWORD *v15; // rcx\n int v16; // esi\n __int64 v17; // rdi\n int v18; // eax\n _DWORD v21[1022]; // [rsp+8h] [rbp-1040h] BYREF\n _QWORD v22[8]; // [rsp+1008h] [rbp-40h] BYREF\n\n v3 = a1 - a2;\n v22[1] = __readfsqword(0x28u);\n if ( a1 - a2 > a2 )\n v3 = a2;\n v5 = 4LL * (v3 + 1) + 15;\n v6 = (_DWORD *)((char *)v22 - (v5 & 0xFFFFFFFFFFFFF000LL));\n v7 = v5 & 0xFFF0;\n if ( v22 != (_QWORD *)v6 )\n {\n while ( v21 != v6 )\n ;\n }\n v8 = v7 & 0xFFF;\n v9 = alloca(v8);\n if ( v8 )\n *(_QWORD *)((char *)&v21[-2] + v8) = *(_QWORD *)((char *)&v21[-2] + v8);\n v10 = v21;\n if ( v3 >= 0 )\n v10 = memset(v21, 0, 4LL * v3 + 4);\n v21[0] = 1;\n if ( a1 > 0 )\n {\n v11 = a1 + 1;\n v12 = 1;\n do\n {\n v13 = v12;\n if ( v3 <= v12 )\n v13 = v3;\n if ( v13 > 0 )\n {\n v14 = v13;\n v15 = &v10[v14];\n v16 = v10[v14];\n v17 = (__int64)&v10[v14 - 1 - (unsigned int)(v13 - 1)];\n do\n {\n v18 = v16;\n v16 = *--v15;\n v15[1] = (v16 + v18) % a3;\n }\n while ( v15 != (_DWORD *)v17 );\n }\n ++v12;\n }\n while ( v12 != v11 );\n }\n return (unsigned int)v10[v3];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1250(int a1, int a2, int a3) {\n int v3;\n long long v5;\n uint32_t *v6;\n short v7;\n signed long long v8;\n void *v9;\n uint32_t *v10;\n int v11;\n int v12;\n int v13;\n long long v14;\n uint32_t *v15;\n int v16;\n long long v17;\n int v18;\n uint32_t v21[1022];\n uint64_t v22[8];\n v3 = a1 - a2;\n v22[1] = __readfsqword(40u);\n if (a1 - a2 > a2) v3 = a2;\n v5 = 4LL * (v3 + 1) + 15;\n v6 = (uint32_t *)((char *)v22 - (v5 & 18446744073709547520LL));\n v7 = v5 & 65520;\n if (v22 != (uint64_t *)v6) {\n while (v21 != v6)\n ;\n }\n v8 = v7 & 4095;\n v9 = alloca(v8);\n if (v8)\n *(uint64_t *)((char *)&v21[-2] + v8) = *(uint64_t *)((char *)&v21[-2] + v8);\n v10 = v21;\n if (v3 >= 0) v10 = memset(v21, 0, 4LL * v3 + 4);\n v21[0] = 1;\n if (a1 > 0) {\n v11 = a1 + 1;\n v12 = 1;\n do {\n v13 = v12;\n if (v3 <= v12) v13 = v3;\n if (v13 > 0) {\n v14 = v13;\n v15 = &v10[v14];\n v16 = v10[v14];\n v17 = (long long)&v10[v14 - 1 - (unsigned int)(v13 - 1)];\n do {\n v18 = v16;\n v16 = *--v15;\n v15[1] = (v16 + v18) % a3;\n } while (v15 != (uint32_t *)v17);\n }\n ++v12;\n } while (v12 != v11);\n }\n return (unsigned int)v10[v3];\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, int a3) {\n int v3;\n long long v5;\n uint32_t *v6;\n short v7;\n signed long long v8;\n void *v9;\n uint32_t *v10;\n int v11;\n int v12;\n int v13;\n long long v14;\n uint32_t *v15;\n int v16;\n long long v17;\n int v18;\n uint32_t v21[1022];\n uint64_t v22[8];\n v3 = a1 - a2;\n v22[1] = __readfsqword(40u);\n if (a1 - a2 > a2) v3 = a2;\n v5 = 4LL * (v3 + 1) + 15;\n v6 = (uint32_t *)((char *)v22 - (v5 & 18446744073709547520LL));\n v7 = v5 & 65520;\n if (v22 != (uint64_t *)v6) {\n while (v21 != v6)\n ;\n }\n v8 = v7 & 4095;\n v9 = alloca(v8);\n if (v8)\n *(uint64_t *)((char *)&v21[-2] + v8) = *(uint64_t *)((char *)&v21[-2] + v8);\n v10 = v21;\n if (v3 >= 0) v10 = memset(v21, 0, 4LL * v3 + 4);\n v21[0] = 1;\n if (a1 > 0) {\n v11 = a1 + 1;\n v12 = 1;\n do {\n v13 = v12;\n if (v3 <= v12) v13 = v3;\n if (v13 > 0) {\n v14 = v13;\n v15 = &v10[v14];\n v16 = v10[v14];\n v17 = (long long)&v10[v14 - 1 - (unsigned int)(v13 - 1)];\n do {\n v18 = v16;\n v16 = *--v15;\n v15[1] = (v16 + v18) % a3;\n } while (v15 != (uint32_t *)v17);\n }\n ++v12;\n } while (v12 != v11);\n }\n return (unsigned int)v10[v3];\n}" + }, + { + "index": 953, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int ar[], int n) {\n int res = 0;\n int i, count;\n for (int step = 0; step < n - 1; ++step) {\n for (int i = 0; i < n - step - 1; ++i) {\n if (ar[i] > ar[i + 1]) {\n int temp = ar[i];\n ar[i] = ar[i + 1];\n ar[i + 1] = temp;\n }\n }\n }\n i = 0;\n while (i < n) {\n count = 1;\n while (i + 1 < n && ar[i] == ar[i + 1]) {\n count++;\n i++;\n }\n if (res < count) {\n res = count;\n }\n i++;\n }\n return res;\n}", + "test": "int main() {\n\n int ar1[] = {1, 2, 3, 4};\n\n int ar2[] = {5, 6, 9, 3, 4, 3, 4};\n\n int ar3[] = {1, 2, 3};\n\n\n\n assert(func0(ar1, 4) == 1);\n\n assert(func0(ar2, 7) == 2);\n\n assert(func0(ar3, 3) == 1);\n\n\n\n printf(\"All test cases passed!\\n\");\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmovl $0x0,-0x18(%rbp)\nmovl $0x0,-0xc(%rbp)\njmpq 126c \nmovl $0x0,-0x8(%rbp)\njmpq 1256 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x8(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\njle 1252 \nmov -0x8(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x4(%rbp)\nmov -0x8(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov -0x8(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x28(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\nmov -0x8(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rax,%rdx\nmov -0x4(%rbp),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x8(%rbp)\nmov -0x2c(%rbp),%eax\nsub -0xc(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0x8(%rbp)\njl 11b7 \naddl $0x1,-0xc(%rbp)\nmov -0x2c(%rbp),%eax\nsub $0x1,%eax\ncmp %eax,-0xc(%rbp)\njl 11ab \nmovl $0x0,-0x14(%rbp)\njmp 12e6 \nmovl $0x1,-0x10(%rbp)\njmp 1295 \naddl $0x1,-0x10(%rbp)\naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\nadd $0x1,%eax\ncmp %eax,-0x2c(%rbp)\njle 12d4 \nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x14(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rcx\nmov -0x28(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\nje 128d \nmov -0x18(%rbp),%eax\ncmp -0x10(%rbp),%eax\njge 12e2 \nmov -0x10(%rbp),%eax\nmov %eax,-0x18(%rbp)\naddl $0x1,-0x14(%rbp)\nmov -0x14(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 1284 \nmov -0x18(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_18], 0\nmov [rbp+var_C], 0\njmp loc_126C\nloc_11AB:\nmov [rbp+var_8], 0\njmp loc_1256\nloc_11B7:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_1252\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_8]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_8]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nloc_1252:\nadd [rbp+var_8], 1\nloc_1256:\nmov eax, [rbp+var_2C]\nsub eax, [rbp+var_C]\nsub eax, 1\ncmp [rbp+var_8], eax\njl loc_11B7\nadd [rbp+var_C], 1\nloc_126C:\nmov eax, [rbp+var_2C]\nsub eax, 1\ncmp [rbp+var_C], eax\njl loc_11AB\nmov [rbp+var_14], 0\njmp short loc_12E6\nloc_1284:\nmov [rbp+var_10], 1\njmp short loc_1295\nloc_128D:\nadd [rbp+var_10], 1\nadd [rbp+var_14], 1\nloc_1295:\nmov eax, [rbp+var_14]\nadd eax, 1\ncmp [rbp+var_2C], eax\njle short loc_12D4\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_14]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_128D\nloc_12D4:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_10]\njge short loc_12E2\nmov eax, [rbp+var_10]\nmov [rbp+var_18], eax\nloc_12E2:\nadd [rbp+var_14], 1\nloc_12E6:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl short loc_1284\nmov eax, [rbp+var_18]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int v3; // [rsp+14h] [rbp-18h]\n int k; // [rsp+18h] [rbp-14h]\n int v5; // [rsp+1Ch] [rbp-10h]\n int i; // [rsp+20h] [rbp-Ch]\n int j; // [rsp+24h] [rbp-8h]\n int v8; // [rsp+28h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2 - 1; ++i )\n {\n for ( j = 0; j < a2 - i - 1; ++j )\n {\n if ( *(_DWORD *)(4LL * j + a1) > *(_DWORD *)(4 * (j + 1LL) + a1) )\n {\n v8 = *(_DWORD *)(4LL * j + a1);\n *(_DWORD *)(4LL * j + a1) = *(_DWORD *)(4 * (j + 1LL) + a1);\n *(_DWORD *)(a1 + 4 * (j + 1LL)) = v8;\n }\n }\n }\n for ( k = 0; k < a2; ++k )\n {\n v5 = 1;\n while ( a2 > k + 1 && *(_DWORD *)(4LL * k + a1) == *(_DWORD *)(4 * (k + 1LL) + a1) )\n {\n ++v5;\n ++k;\n }\n if ( v3 < v5 )\n v3 = v5;\n }\n return (unsigned int)v3;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov [rbp+var_18], 0\nmov [rbp+var_C], 0\njmp loc_126C\nloc_11AB:\nmov [rbp+var_8], 0\njmp loc_1256\nloc_11B7:\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_8]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njle short loc_1252\nmov eax, [rbp+var_8]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_4], eax\nmov eax, [rbp+var_8]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+var_28]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nmov eax, [rbp+var_8]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rdx, rax\nmov eax, [rbp+var_4]\nmov [rdx], eax\nloc_1252:\nadd [rbp+var_8], 1\nloc_1256:\nmov eax, [rbp+var_2C]\nsub eax, [rbp+var_C]\nsub eax, 1\ncmp [rbp+var_8], eax\njl loc_11B7\nadd [rbp+var_C], 1\nloc_126C:\nmov eax, [rbp+var_2C]\nsub eax, 1\ncmp [rbp+var_C], eax\njl loc_11AB\nmov [rbp+var_14], 0\njmp short loc_12E6\nloc_1284:\nmov [rbp+var_10], 1\njmp short loc_1295\nloc_128D:\nadd [rbp+var_10], 1\nadd [rbp+var_14], 1\nloc_1295:\nmov eax, [rbp+var_14]\nadd eax, 1\ncmp [rbp+var_2C], eax\njle short loc_12D4\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_14]\ncdqe\nadd rax, 1\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+var_28]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\njz short loc_128D\nloc_12D4:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_10]\njge short loc_12E2\nmov eax, [rbp+var_10]\nmov [rbp+var_18], eax\nloc_12E2:\nadd [rbp+var_14], 1\nloc_12E6:\nmov eax, [rbp+var_14]\ncmp eax, [rbp+var_2C]\njl short loc_1284\nmov eax, [rbp+var_18]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(__int64 a1, int a2)\n{\n int v3; // [rsp+14h] [rbp-18h]\n int k; // [rsp+18h] [rbp-14h]\n int v5; // [rsp+1Ch] [rbp-10h]\n int i; // [rsp+20h] [rbp-Ch]\n int j; // [rsp+24h] [rbp-8h]\n int v8; // [rsp+28h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2 - 1; ++i )\n {\n for ( j = 0; j < a2 - i - 1; ++j )\n {\n if ( *(_DWORD *)(4LL * j + a1) > *(_DWORD *)(4 * (j + 1LL) + a1) )\n {\n v8 = *(_DWORD *)(4LL * j + a1);\n *(_DWORD *)(4LL * j + a1) = *(_DWORD *)(4 * (j + 1LL) + a1);\n *(_DWORD *)(a1 + 4 * (j + 1LL)) = v8;\n }\n }\n }\n for ( k = 0; k < a2; ++k )\n {\n v5 = 1;\n while ( a2 > k + 1 && *(_DWORD *)(4LL * k + a1) == *(_DWORD *)(4 * (k + 1LL) + a1) )\n {\n ++v5;\n ++k;\n }\n if ( v3 < v5 )\n v3 = v5;\n }\n return (unsigned int)v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(long long a1, int a2) {\n int v3;\n int k;\n int v5;\n int i;\n int j;\n int v8;\n v3 = 0;\n for (i = 0; i < a2 - 1; ++i) {\n for (j = 0; j < a2 - i - 1; ++j) {\n if (*(uint32_t *)(4LL * j + a1) > *(uint32_t *)(4 * (j + 1LL) + a1)) {\n v8 = *(uint32_t *)(4LL * j + a1);\n *(uint32_t *)(4LL * j + a1) = *(uint32_t *)(4 * (j + 1LL) + a1);\n *(uint32_t *)(a1 + 4 * (j + 1LL)) = v8;\n }\n }\n }\n for (k = 0; k < a2; ++k) {\n v5 = 1;\n while (a2 > k + 1 &&\n *(uint32_t *)(4LL * k + a1) == *(uint32_t *)(4 * (k + 1LL) + a1)) {\n ++v5;\n ++k;\n }\n if (v3 < v5) v3 = v5;\n }\n return (unsigned int)v3;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int v3;\n int k;\n int v5;\n int i;\n int j;\n int v8;\n v3 = 0;\n for (i = 0; i < a2 - 1; ++i) {\n for (j = 0; j < a2 - i - 1; ++j) {\n if (*(uint32_t *)(4LL * j + a1) > *(uint32_t *)(4 * (j + 1LL) + a1)) {\n v8 = *(uint32_t *)(4LL * j + a1);\n *(uint32_t *)(4LL * j + a1) = *(uint32_t *)(4 * (j + 1LL) + a1);\n *(uint32_t *)(a1 + 4 * (j + 1LL)) = v8;\n }\n }\n }\n for (k = 0; k < a2; ++k) {\n v5 = 1;\n while (a2 > k + 1 &&\n *(uint32_t *)(4LL * k + a1) == *(uint32_t *)(4 * (k + 1LL) + a1)) {\n ++v5;\n ++k;\n }\n if (v3 < v5) v3 = v5;\n }\n return (unsigned int)v3;\n}" + }, + { + "index": 953, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int ar[], int n) {\n int res = 0;\n int i, count;\n for (int step = 0; step < n - 1; ++step) {\n for (int i = 0; i < n - step - 1; ++i) {\n if (ar[i] > ar[i + 1]) {\n int temp = ar[i];\n ar[i] = ar[i + 1];\n ar[i + 1] = temp;\n }\n }\n }\n i = 0;\n while (i < n) {\n count = 1;\n while (i + 1 < n && ar[i] == ar[i + 1]) {\n count++;\n i++;\n }\n if (res < count) {\n res = count;\n }\n i++;\n }\n return res;\n}", + "test": "int main() {\n\n int ar1[] = {1, 2, 3, 4};\n\n int ar2[] = {5, 6, 9, 3, 4, 3, 4};\n\n int ar3[] = {1, 2, 3};\n\n\n\n assert(func0(ar1, 4) == 1);\n\n assert(func0(ar2, 7) == 2);\n\n assert(func0(ar3, 3) == 1);\n\n\n\n printf(\"All test cases passed!\\n\");\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nlea -0x1(%rsi),%r9d\ntest %r9d,%r9d\njle 11cd \nlea 0x4(%rdi),%r10\njmp 11bb \nadd $0x4,%rax\ncmp %r8,%rax\nje 11b5 \nmov (%rax),%edx\nmov 0x4(%rax),%ecx\ncmp %ecx,%edx\njle 119c \nmov %ecx,(%rax)\nmov %edx,0x4(%rax)\njmp 119c \nsub $0x1,%r9d\nje 11cd \ntest %r9d,%r9d\njle 11b5 \nmov %rdi,%rax\nlea -0x1(%r9),%edx\nlea (%r10,%rdx,4),%r8\njmp 11a5 \nmov $0x0,%ecx\nmov $0x0,%r10d\ntest %esi,%esi\njg 11e9 \njmp 1225 \ncmp %eax,%r10d\ncmovl %eax,%r10d\ncmp %ecx,%esi\njle 1225 \nlea 0x1(%rcx),%eax\ncmp %eax,%esi\njle 1229 \nmovslq %ecx,%rax\nlea (%rdi,%rax,4),%rdx\nmov %ecx,%r8d\nmov %esi,%r9d\nsub %ecx,%r9d\nmov $0x1,%eax\nlea (%rax,%r8,1),%ecx\nmov 0x4(%rdx),%r11d\ncmp %r11d,(%rdx)\njne 11de \nadd $0x1,%eax\nadd $0x4,%rdx\ncmp %r9d,%eax\njne 1205 \ncmp %r9d,%r10d\ncmovl %r9d,%r10d\nmov %r10d,%eax\nretq\ntest %r10d,%r10d\nmov $0x1,%eax\ncmovle %eax,%r10d\njmp 1225 \n", + "ida_asm": "func0:\nendbr64\nmov r9, rdi\nmov r8d, esi\ncmp esi, 1\njle loc_1239\nmov edi, esi\nlea r10, [r9+4]\njmp short loc_11C5\nloc_11A4:\nadd rax, 4\ncmp rax, rsi\njz short loc_11BD\nloc_11AD:\nmov edx, [rax]\nmov ecx, [rax+4]\ncmp edx, ecx\njle short loc_11A4\nmov [rax], ecx\nmov [rax+4], edx\njmp short loc_11A4\nloc_11BD:\nsub edi, 1\ncmp edi, 1\njz short loc_121A\nloc_11C5:\ncmp edi, 1\njle short loc_1244\nmov rax, r9\nlea edx, [rdi-2]\nlea rsi, [r10+rdx*4]\njmp short loc_11AD\nloc_11D6:\nlea esi, [rdx+r10]\ncmp edi, edx\ncmovl edi, edx\ncmp r8d, esi\njle short loc_1217\nloc_11E4:\nlea eax, [rsi+1]\ncmp r8d, eax\njle short loc_1226\nmovsxd rax, esi\nlea rax, [r9+rax*4]\nmov r10d, esi\nmov ecx, r8d\nsub ecx, esi\nmov edx, 1\nloc_1200:\nmov esi, [rax+4]\ncmp [rax], esi\njnz short loc_11D6\nadd edx, 1\nadd rax, 4\ncmp edx, ecx\njnz short loc_1200\nloc_1212:\ncmp edi, ecx\ncmovl edi, ecx\nloc_1217:\nmov eax, edi\nretn\nloc_121A:\nmov esi, 0\nmov edi, 0\njmp short loc_11E4\nloc_1226:\nmov ecx, 1\njmp short loc_1212\nloc_122D:\nmov edi, 0\nmov ecx, 1\njmp short loc_1212\nloc_1239:\ntest esi, esi\njg short loc_122D\nmov edi, 0\njmp short loc_1217\nloc_1244:\nsub edi, 1\njmp loc_11C5", + "ida_pseudo": "__int64 __fastcall func0(int *a1, int a2)\n{\n int i; // edi\n int *v5; // rax\n int v6; // edx\n int v7; // ecx\n int v8; // esi\n int v9; // edi\n int *v10; // rax\n int v11; // ecx\n int v12; // edx\n\n if ( a2 <= 1 )\n {\n if ( a2 <= 0 )\n return 0;\n v9 = 0;\n v11 = 1;\n }\n else\n {\n for ( i = a2; i != 1; --i )\n {\n while ( i <= 1 )\n --i;\n v5 = a1;\n do\n {\n v6 = *v5;\n v7 = v5[1];\n if ( *v5 > v7 )\n {\n *v5 = v7;\n v5[1] = v6;\n }\n ++v5;\n }\n while ( v5 != &a1[i - 2 + 1] );\n }\n v8 = 0;\n v9 = 0;\n while ( a2 > v8 + 1 )\n {\n v10 = &a1[v8];\n v11 = a2 - v8;\n v12 = 1;\n while ( *v10 == v10[1] )\n {\n ++v12;\n ++v10;\n if ( v12 == v11 )\n goto LABEL_16;\n }\n v8 += v12;\n if ( v9 < v12 )\n v9 = v12;\n if ( a2 <= v8 )\n return (unsigned int)v9;\n }\n v11 = 1;\n }\nLABEL_16:\n if ( v9 < v11 )\n return (unsigned int)v11;\n return (unsigned int)v9;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\nmov r9, rdi\nmov r8d, esi\ncmp esi, 1\njle loc_1239\nmov edi, esi\nlea r10, [r9+4]\njmp short loc_11C5\nloc_11A4:\nadd rax, 4\ncmp rax, rsi\njz short loc_11BD\nloc_11AD:\nmov edx, [rax]\nmov ecx, [rax+4]\ncmp edx, ecx\njle short loc_11A4\nmov [rax], ecx\nmov [rax+4], edx\njmp short loc_11A4\nloc_11BD:\nsub edi, 1\ncmp edi, 1\njz short loc_121A\nloc_11C5:\ncmp edi, 1\njle short loc_1244\nmov rax, r9\nlea edx, [rdi-2]\nlea rsi, [r10+rdx*4]\njmp short loc_11AD\nloc_11D6:\nlea esi, [rdx+r10]\ncmp edi, edx\ncmovl edi, edx\ncmp r8d, esi\njle short loc_1217\nloc_11E4:\nlea eax, [rsi+1]\ncmp r8d, eax\njle short loc_1226\nmovsxd rax, esi\nlea rax, [r9+rax*4]\nmov r10d, esi\nmov ecx, r8d\nsub ecx, esi\nmov edx, 1\nloc_1200:\nmov esi, [rax+4]\ncmp [rax], esi\njnz short loc_11D6\nadd edx, 1\nadd rax, 4\ncmp edx, ecx\njnz short loc_1200\nloc_1212:\ncmp edi, ecx\ncmovl edi, ecx\nloc_1217:\nmov eax, edi\nretn\nloc_121A:\nmov esi, 0\nmov edi, 0\njmp short loc_11E4\nloc_1226:\nmov ecx, 1\njmp short loc_1212\nloc_122D:\nmov edi, 0\nmov ecx, 1\njmp short loc_1212\nloc_1239:\ntest esi, esi\njg short loc_122D\nmov edi, 0\njmp short loc_1217\nloc_1244:\nsub edi, 1\njmp loc_11C5", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(int *a1, int a2)\n{\n int i; // edi\n int *v5; // rax\n int v6; // edx\n int v7; // ecx\n int v8; // esi\n int v9; // edi\n int *v10; // rax\n int v11; // ecx\n int v12; // edx\n\n if ( a2 <= 1 )\n {\n if ( a2 <= 0 )\n return 0;\n v9 = 0;\n v11 = 1;\n }\n else\n {\n for ( i = a2; i != 1; --i )\n {\n while ( i <= 1 )\n --i;\n v5 = a1;\n do\n {\n v6 = *v5;\n v7 = v5[1];\n if ( *v5 > v7 )\n {\n *v5 = v7;\n v5[1] = v6;\n }\n ++v5;\n }\n while ( v5 != &a1[i - 2 + 1] );\n }\n v8 = 0;\n v9 = 0;\n while ( a2 > v8 + 1 )\n {\n v10 = &a1[v8];\n v11 = a2 - v8;\n v12 = 1;\n while ( *v10 == v10[1] )\n {\n ++v12;\n ++v10;\n if ( v12 == v11 )\n goto LABEL_16;\n }\n v8 += v12;\n if ( v9 < v12 )\n v9 = v12;\n if ( a2 <= v8 )\n return (unsigned int)v9;\n }\n v11 = 1;\n }\nLABEL_16:\n if ( v9 < v11 )\n return (unsigned int)v11;\n return (unsigned int)v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(int *a1, int a2) {\n int i;\n int *v5;\n int v6;\n int v7;\n int v8;\n int v9;\n int *v10;\n int v11;\n int v12;\n if (a2 <= 1) {\n if (a2 <= 0) return 0;\n v9 = 0;\n v11 = 1;\n } else {\n for (i = a2; i != 1; --i) {\n while (i <= 1) --i;\n v5 = a1;\n do {\n v6 = *v5;\n v7 = v5[1];\n if (*v5 > v7) {\n *v5 = v7;\n v5[1] = v6;\n }\n ++v5;\n } while (v5 != &a1[i - 2 + 1]);\n }\n v8 = 0;\n v9 = 0;\n while (a2 > v8 + 1) {\n v10 = &a1[v8];\n v11 = a2 - v8;\n v12 = 1;\n while (*v10 == v10[1]) {\n ++v12;\n ++v10;\n if (v12 == v11) goto LABEL_16;\n }\n v8 += v12;\n if (v9 < v12) v9 = v12;\n if (a2 <= v8) return (unsigned int)v9;\n }\n v11 = 1;\n }\nLABEL_16:\n if (v9 < v11) return (unsigned int)v11;\n return (unsigned int)v9;\n}", + "ida_pseudo_norm": "long long func0(int *a1, int a2) {\n int i;\n int *v5;\n int v6;\n int v7;\n int v8;\n int v9;\n int *v10;\n int v11;\n int v12;\n if (a2 <= 1) {\n if (a2 <= 0) return 0;\n v9 = 0;\n v11 = 1;\n } else {\n for (i = a2; i != 1; --i) {\n while (i <= 1) --i;\n v5 = a1;\n do {\n v6 = *v5;\n v7 = v5[1];\n if (*v5 > v7) {\n *v5 = v7;\n v5[1] = v6;\n }\n ++v5;\n } while (v5 != &a1[i - 2 + 1]);\n }\n v8 = 0;\n v9 = 0;\n while (a2 > v8 + 1) {\n v10 = &a1[v8];\n v11 = a2 - v8;\n v12 = 1;\n while (*v10 == v10[1]) {\n ++v12;\n ++v10;\n if (v12 == v11) goto LABEL_16;\n }\n v8 += v12;\n if (v9 < v12) v9 = v12;\n if (a2 <= v8) return (unsigned int)v9;\n }\n v11 = 1;\n }\nLABEL_16:\n if (v9 < v11) return (unsigned int)v11;\n return (unsigned int)v9;\n}" + }, + { + "index": 953, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int ar[], int n) {\n int res = 0;\n int i, count;\n for (int step = 0; step < n - 1; ++step) {\n for (int i = 0; i < n - step - 1; ++i) {\n if (ar[i] > ar[i + 1]) {\n int temp = ar[i];\n ar[i] = ar[i + 1];\n ar[i + 1] = temp;\n }\n }\n }\n i = 0;\n while (i < n) {\n count = 1;\n while (i + 1 < n && ar[i] == ar[i + 1]) {\n count++;\n i++;\n }\n if (res < count) {\n res = count;\n }\n i++;\n }\n return res;\n}", + "test": "int main() {\n\n int ar1[] = {1, 2, 3, 4};\n\n int ar2[] = {5, 6, 9, 3, 4, 3, 4};\n\n int ar3[] = {1, 2, 3};\n\n\n\n assert(func0(ar1, 4) == 1);\n\n assert(func0(ar2, 7) == 2);\n\n assert(func0(ar3, 3) == 1);\n\n\n\n printf(\"All test cases passed!\\n\");\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nlea -0x1(%rsi),%edx\ntest %edx,%edx\njle 130f \nlea 0x4(%rdi),%r10\nsub $0x1,%edx\nmov %rdi,%rax\nmov %rdx,%r9\nlea (%r10,%rdx,4),%r8\nnopl (%rax)\nmov (%rax),%edx\nmov 0x4(%rax),%ecx\ncmp %ecx,%edx\njle 12fe \nmov %ecx,(%rax)\nmov %edx,0x4(%rax)\nadd $0x4,%rax\ncmp %rax,%r8\njne 12f0 \nmov %r9d,%edx\ntest %r9d,%r9d\njne 12e0 \nxor %ecx,%ecx\nxor %r10d,%r10d\ntest %esi,%esi\njle 1364 \nnopl 0x0(%rax,%rax,1)\nlea 0x1(%rcx),%eax\ncmp %eax,%esi\njle 137b \nmovslq %ecx,%rax\nmov %esi,%r9d\nmov %ecx,%r8d\nlea (%rdi,%rax,4),%rdx\nsub %ecx,%r9d\nmov $0x1,%eax\njmp 134c \nxchg %ax,%ax\nadd $0x1,%eax\nadd $0x4,%rdx\ncmp %r9d,%eax\nje 1370 \nmov 0x4(%rdx),%r11d\nlea (%rax,%r8,1),%ecx\ncmp %r11d,(%rdx)\nje 1340 \ncmp %eax,%r10d\ncmovl %eax,%r10d\ncmp %ecx,%esi\njg 1320 \nmov %r10d,%eax\nretq\nnopl 0x0(%rax,%rax,1)\ncmp %eax,%r10d\ncmovl %eax,%r10d\nmov %r10d,%eax\nretq\ntest %r10d,%r10d\nmov $0x1,%eax\ncmovle %eax,%r10d\njmp 1364 \nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\nmov r9, rdi\nmov r10d, esi\ncmp esi, 1\njle loc_1388\nmov edi, esi\nlea r8, [r9+4]\nnop dword ptr [rax+00000000h]\nloc_12D0:\ncmp edi, 1\njle loc_1370\nlea edx, [rdi-2]\nmov rax, r9\nlea rsi, [r8+rdx*4]\nnop dword ptr [rax+rax+00h]\nloc_12E8:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd edx, xmm0\nmovd ecx, xmm1\ncmp ecx, edx\njge short loc_1306\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_1306:\nadd rax, 4\ncmp rax, rsi\njnz short loc_12E8\nsub edi, 1\ncmp edi, 1\njnz short loc_12D0\nxor r8d, r8d\nxor r11d, r11d\nnop dword ptr [rax]\nloc_1320:\nlea eax, [r8+1]\ncmp r10d, eax\njle short loc_1378\nmovsxd rax, r8d\nmov edi, r10d\nmov edx, 1\nlea rax, [r9+rax*4]\nsub edi, r8d\nmov ecx, [rax]\njmp short loc_134B\nloc_1340:\nadd edx, 1\nadd rax, 4\ncmp edx, edi\njz short loc_137D\nloc_134B:\nmov esi, ecx\nmov ecx, [rax+4]\ncmp ecx, esi\njz short loc_1340\nadd r8d, edx\ncmp r11d, edx\ncmovl r11d, edx\ncmp r10d, r8d\njg short loc_1320\nmov eax, r11d\nretn\nloc_1370:\nsub edi, 1\njmp loc_12D0\nloc_1378:\nmov edi, 1\nloc_137D:\ncmp r11d, edi\ncmovl r11d, edi\nmov eax, r11d\nretn\nloc_1388:\njz short loc_1391\nxor r11d, r11d\nmov eax, r11d\nretn\nloc_1391:\nmov edi, 1\nxor r11d, r11d\njmp short loc_137D", + "ida_pseudo": "__int64 __fastcall func0(__m128i *a1, int a2)\n{\n int i; // edi\n __m128i *v5; // rax\n __m128i v6; // xmm0\n int v7; // r8d\n int v8; // r11d\n int v9; // edx\n __int32 *v10; // rax\n int v11; // edi\n __int32 v12; // ecx\n int v13; // esi\n\n if ( a2 <= 1 )\n {\n if ( a2 != 1 )\n return 0LL;\n v11 = 1;\n v8 = 0;\n }\n else\n {\n for ( i = a2; i != 1; --i )\n {\n while ( i <= 1 )\n --i;\n v5 = a1;\n do\n {\n v6 = _mm_loadl_epi64(v5);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v6, 229)) < _mm_cvtsi128_si32(v6) )\n v5->m128i_i64[0] = _mm_shuffle_epi32(v6, 225).m128i_u64[0];\n v5 = (__m128i *)((char *)v5 + 4);\n }\n while ( v5 != (__m128i *)((char *)a1->m128i_i64 + 4 * (unsigned int)(i - 2) + 4) );\n }\n v7 = 0;\n v8 = 0;\n while ( a2 > v7 + 1 )\n {\n v9 = 1;\n v10 = &a1->m128i_i32[v7];\n v11 = a2 - v7;\n v12 = *v10;\n while ( 1 )\n {\n v13 = v12;\n v12 = v10[1];\n if ( v12 != v13 )\n break;\n ++v9;\n ++v10;\n if ( v9 == v11 )\n goto LABEL_20;\n }\n v7 += v9;\n if ( v8 < v9 )\n v8 = v9;\n if ( a2 <= v7 )\n return (unsigned int)v8;\n }\n v11 = 1;\n }\nLABEL_20:\n if ( v8 < v11 )\n return (unsigned int)v11;\n return (unsigned int)v8;\n}", + "ida_strip_asm": "sub_12B0:\nendbr64\nmov r9, rdi\nmov r10d, esi\ncmp esi, 1\njle loc_1388\nmov edi, esi\nlea r8, [r9+4]\nnop dword ptr [rax+00000000h]\nloc_12D0:\ncmp edi, 1\njle loc_1370\nlea edx, [rdi-2]\nmov rax, r9\nlea rsi, [r8+rdx*4]\nnop dword ptr [rax+rax+00h]\nloc_12E8:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd edx, xmm0\nmovd ecx, xmm1\ncmp ecx, edx\njge short loc_1306\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_1306:\nadd rax, 4\ncmp rax, rsi\njnz short loc_12E8\nsub edi, 1\ncmp edi, 1\njnz short loc_12D0\nxor r8d, r8d\nxor r11d, r11d\nnop dword ptr [rax]\nloc_1320:\nlea eax, [r8+1]\ncmp r10d, eax\njle short loc_1378\nmovsxd rax, r8d\nmov edi, r10d\nmov edx, 1\nlea rax, [r9+rax*4]\nsub edi, r8d\nmov ecx, [rax]\njmp short loc_134B\nloc_1340:\nadd edx, 1\nadd rax, 4\ncmp edx, edi\njz short loc_137D\nloc_134B:\nmov esi, ecx\nmov ecx, [rax+4]\ncmp ecx, esi\njz short loc_1340\nadd r8d, edx\ncmp r11d, edx\ncmovl r11d, edx\ncmp r10d, r8d\njg short loc_1320\nmov eax, r11d\nretn\nloc_1370:\nsub edi, 1\njmp loc_12D0\nloc_1378:\nmov edi, 1\nloc_137D:\ncmp r11d, edi\ncmovl r11d, edi\nmov eax, r11d\nretn\nloc_1388:\njz short loc_1391\nxor r11d, r11d\nmov eax, r11d\nretn\nloc_1391:\nmov edi, 1\nxor r11d, r11d\njmp short loc_137D", + "ida_strip_pseudo": "__int64 __fastcall sub_12B0(__m128i *a1, int a2)\n{\n int i; // edi\n __m128i *v5; // rax\n __m128i v6; // xmm0\n int v7; // r8d\n int v8; // r11d\n int v9; // edx\n __int32 *v10; // rax\n int v11; // edi\n __int32 v12; // ecx\n int v13; // esi\n\n if ( a2 <= 1 )\n {\n if ( a2 != 1 )\n return 0LL;\n v11 = 1;\n v8 = 0;\n }\n else\n {\n for ( i = a2; i != 1; --i )\n {\n while ( i <= 1 )\n --i;\n v5 = a1;\n do\n {\n v6 = _mm_loadl_epi64(v5);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v6, 229)) < _mm_cvtsi128_si32(v6) )\n v5->m128i_i64[0] = _mm_shuffle_epi32(v6, 225).m128i_u64[0];\n v5 = (__m128i *)((char *)v5 + 4);\n }\n while ( v5 != (__m128i *)((char *)a1->m128i_i64 + 4 * (unsigned int)(i - 2) + 4) );\n }\n v7 = 0;\n v8 = 0;\n while ( a2 > v7 + 1 )\n {\n v9 = 1;\n v10 = &a1->m128i_i32[v7];\n v11 = a2 - v7;\n v12 = *v10;\n while ( 1 )\n {\n v13 = v12;\n v12 = v10[1];\n if ( v12 != v13 )\n break;\n ++v9;\n ++v10;\n if ( v9 == v11 )\n goto LABEL_20;\n }\n v7 += v9;\n if ( v8 < v9 )\n v8 = v9;\n if ( a2 <= v7 )\n return (unsigned int)v8;\n }\n v11 = 1;\n }\nLABEL_20:\n if ( v8 < v11 )\n return (unsigned int)v11;\n return (unsigned int)v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12B0(__m128i *a1, int a2) {\n int i;\n __m128i *v5;\n __m128i v6;\n int v7;\n int v8;\n int v9;\n int *v10;\n int v11;\n int v12;\n int v13;\n if (a2 <= 1) {\n if (a2 != 1) return 0LL;\n v11 = 1;\n v8 = 0;\n } else {\n for (i = a2; i != 1; --i) {\n while (i <= 1) --i;\n v5 = a1;\n do {\n v6 = _mm_loadl_epi64(v5);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v6, 229)) <\n _mm_cvtsi128_si32(v6))\n v5->m128i_i64[0] = _mm_shuffle_epi32(v6, 225).m128i_u64[0];\n v5 = (__m128i *)((char *)v5 + 4);\n } while (v5 != (__m128i *)((char *)a1->m128i_i64 +\n 4 * (unsigned int)(i - 2) + 4));\n }\n v7 = 0;\n v8 = 0;\n while (a2 > v7 + 1) {\n v9 = 1;\n v10 = &a1->m128i_i32[v7];\n v11 = a2 - v7;\n v12 = *v10;\n while (1) {\n v13 = v12;\n v12 = v10[1];\n if (v12 != v13) break;\n ++v9;\n ++v10;\n if (v9 == v11) goto LABEL_20;\n }\n v7 += v9;\n if (v8 < v9) v8 = v9;\n if (a2 <= v7) return (unsigned int)v8;\n }\n v11 = 1;\n }\nLABEL_20:\n if (v8 < v11) return (unsigned int)v11;\n return (unsigned int)v8;\n}", + "ida_pseudo_norm": "long long func0(__m128i *a1, int a2) {\n int i;\n __m128i *v5;\n __m128i v6;\n int v7;\n int v8;\n int v9;\n int *v10;\n int v11;\n int v12;\n int v13;\n if (a2 <= 1) {\n if (a2 != 1) return 0LL;\n v11 = 1;\n v8 = 0;\n } else {\n for (i = a2; i != 1; --i) {\n while (i <= 1) --i;\n v5 = a1;\n do {\n v6 = _mm_loadl_epi64(v5);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v6, 229)) <\n _mm_cvtsi128_si32(v6))\n v5->m128i_i64[0] = _mm_shuffle_epi32(v6, 225).m128i_u64[0];\n v5 = (__m128i *)((char *)v5 + 4);\n } while (v5 != (__m128i *)((char *)a1->m128i_i64 +\n 4 * (unsigned int)(i - 2) + 4));\n }\n v7 = 0;\n v8 = 0;\n while (a2 > v7 + 1) {\n v9 = 1;\n v10 = &a1->m128i_i32[v7];\n v11 = a2 - v7;\n v12 = *v10;\n while (1) {\n v13 = v12;\n v12 = v10[1];\n if (v12 != v13) break;\n ++v9;\n ++v10;\n if (v9 == v11) goto LABEL_20;\n }\n v7 += v9;\n if (v8 < v9) v8 = v9;\n if (a2 <= v7) return (unsigned int)v8;\n }\n v11 = 1;\n }\nLABEL_20:\n if (v8 < v11) return (unsigned int)v11;\n return (unsigned int)v8;\n}" + }, + { + "index": 953, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int ar[], int n) {\n int res = 0;\n int i, count;\n for (int step = 0; step < n - 1; ++step) {\n for (int i = 0; i < n - step - 1; ++i) {\n if (ar[i] > ar[i + 1]) {\n int temp = ar[i];\n ar[i] = ar[i + 1];\n ar[i + 1] = temp;\n }\n }\n }\n i = 0;\n while (i < n) {\n count = 1;\n while (i + 1 < n && ar[i] == ar[i + 1]) {\n count++;\n i++;\n }\n if (res < count) {\n res = count;\n }\n i++;\n }\n return res;\n}", + "test": "int main() {\n\n int ar1[] = {1, 2, 3, 4};\n\n int ar2[] = {5, 6, 9, 3, 4, 3, 4};\n\n int ar3[] = {1, 2, 3};\n\n\n\n assert(func0(ar1, 4) == 1);\n\n assert(func0(ar2, 7) == 2);\n\n assert(func0(ar3, 3) == 1);\n\n\n\n printf(\"All test cases passed!\\n\");\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nlea -0x1(%rsi),%edx\ntest %edx,%edx\njle 12ff \nlea 0x4(%rdi),%r10\nsub $0x1,%edx\nmov %rdi,%rax\nmov %rdx,%r9\nlea (%r10,%rdx,4),%r8\nnopl (%rax)\nmov (%rax),%edx\nmov 0x4(%rax),%ecx\ncmp %ecx,%edx\njle 12ee \nmov %ecx,(%rax)\nmov %edx,0x4(%rax)\nadd $0x4,%rax\ncmp %rax,%r8\njne 12e0 \nmov %r9d,%edx\ntest %r9d,%r9d\njne 12d0 \nxor %ecx,%ecx\nxor %r11d,%r11d\ntest %esi,%esi\njle 1359 \nnopl 0x0(%rax,%rax,1)\nlea 0x1(%rcx),%eax\ncmp %eax,%esi\njle 136b \nmovslq %ecx,%rax\nmov %esi,%r10d\nmov %ecx,%r8d\nlea (%rdi,%rax,4),%rdx\nsub %ecx,%r10d\nmov $0x1,%eax\nmov (%rdx),%r9d\njmp 1344 \nnopl 0x0(%rax)\nadd $0x1,%eax\nadd $0x4,%rdx\ncmp %r10d,%eax\nje 1360 \nlea (%rax,%r8,1),%ecx\ncmp %r9d,0x4(%rdx)\nje 1338 \ncmp %eax,%r11d\ncmovl %eax,%r11d\ncmp %ecx,%esi\njg 1310 \nmov %r11d,%eax\nretq\nnopl (%rax)\ncmp %eax,%r11d\ncmovl %eax,%r11d\nmov %r11d,%eax\nretq\ntest %r11d,%r11d\nmov $0x1,%eax\ncmovle %eax,%r11d\njmp 1359 \nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\nmov r9, rdi\nmov r10d, esi\ncmp esi, 1\njle loc_1388\nmov edi, esi\nlea r8, [r9+4]\nnop dword ptr [rax+00000000h]\nloc_12D0:\ncmp edi, 1\njle loc_1370\nlea edx, [rdi-2]\nmov rax, r9\nlea rsi, [r8+rdx*4]\nnop dword ptr [rax+rax+00h]\nloc_12E8:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd edx, xmm0\nmovd ecx, xmm1\ncmp ecx, edx\njge short loc_1306\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_1306:\nadd rax, 4\ncmp rax, rsi\njnz short loc_12E8\nsub edi, 1\ncmp edi, 1\njnz short loc_12D0\nxor r8d, r8d\nxor r11d, r11d\nnop dword ptr [rax]\nloc_1320:\nlea eax, [r8+1]\ncmp r10d, eax\njle short loc_1378\nmovsxd rax, r8d\nmov edi, r10d\nmov edx, 1\nlea rax, [r9+rax*4]\nsub edi, r8d\nmov ecx, [rax]\njmp short loc_134B\nloc_1340:\nadd edx, 1\nadd rax, 4\ncmp edx, edi\njz short loc_137D\nloc_134B:\nmov esi, ecx\nmov ecx, [rax+4]\ncmp ecx, esi\njz short loc_1340\nadd r8d, edx\ncmp r11d, edx\ncmovl r11d, edx\ncmp r10d, r8d\njg short loc_1320\nmov eax, r11d\nretn\nloc_1370:\nsub edi, 1\njmp loc_12D0\nloc_1378:\nmov edi, 1\nloc_137D:\ncmp r11d, edi\ncmovl r11d, edi\nmov eax, r11d\nretn\nloc_1388:\njz short loc_1391\nxor r11d, r11d\nmov eax, r11d\nretn\nloc_1391:\nmov edi, 1\nxor r11d, r11d\njmp short loc_137D", + "ida_pseudo": "__int64 __fastcall func0(__m128i *a1, int a2)\n{\n int i; // edi\n __m128i *v5; // rax\n __m128i v6; // xmm0\n int v7; // r8d\n int v8; // r11d\n int v9; // edx\n __int32 *v10; // rax\n int v11; // edi\n __int32 v12; // ecx\n int v13; // esi\n\n if ( a2 <= 1 )\n {\n if ( a2 != 1 )\n return 0LL;\n v11 = 1;\n v8 = 0;\n }\n else\n {\n for ( i = a2; i != 1; --i )\n {\n while ( i <= 1 )\n --i;\n v5 = a1;\n do\n {\n v6 = _mm_loadl_epi64(v5);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v6, 229)) < _mm_cvtsi128_si32(v6) )\n v5->m128i_i64[0] = _mm_shuffle_epi32(v6, 225).m128i_u64[0];\n v5 = (__m128i *)((char *)v5 + 4);\n }\n while ( v5 != (__m128i *)((char *)a1->m128i_i64 + 4 * (unsigned int)(i - 2) + 4) );\n }\n v7 = 0;\n v8 = 0;\n while ( a2 > v7 + 1 )\n {\n v9 = 1;\n v10 = &a1->m128i_i32[v7];\n v11 = a2 - v7;\n v12 = *v10;\n while ( 1 )\n {\n v13 = v12;\n v12 = v10[1];\n if ( v12 != v13 )\n break;\n ++v9;\n ++v10;\n if ( v9 == v11 )\n goto LABEL_20;\n }\n v7 += v9;\n if ( v8 < v9 )\n v8 = v9;\n if ( a2 <= v7 )\n return (unsigned int)v8;\n }\n v11 = 1;\n }\nLABEL_20:\n if ( v8 < v11 )\n return (unsigned int)v11;\n return (unsigned int)v8;\n}", + "ida_strip_asm": "sub_12B0:\nendbr64\nmov r9, rdi\nmov r10d, esi\ncmp esi, 1\njle loc_1388\nmov edi, esi\nlea r8, [r9+4]\nnop dword ptr [rax+00000000h]\nloc_12D0:\ncmp edi, 1\njle loc_1370\nlea edx, [rdi-2]\nmov rax, r9\nlea rsi, [r8+rdx*4]\nnop dword ptr [rax+rax+00h]\nloc_12E8:\nmovq xmm0, qword ptr [rax]\npshufd xmm1, xmm0, 0E5h\nmovd edx, xmm0\nmovd ecx, xmm1\ncmp ecx, edx\njge short loc_1306\npshufd xmm0, xmm0, 0E1h\nmovq qword ptr [rax], xmm0\nloc_1306:\nadd rax, 4\ncmp rax, rsi\njnz short loc_12E8\nsub edi, 1\ncmp edi, 1\njnz short loc_12D0\nxor r8d, r8d\nxor r11d, r11d\nnop dword ptr [rax]\nloc_1320:\nlea eax, [r8+1]\ncmp r10d, eax\njle short loc_1378\nmovsxd rax, r8d\nmov edi, r10d\nmov edx, 1\nlea rax, [r9+rax*4]\nsub edi, r8d\nmov ecx, [rax]\njmp short loc_134B\nloc_1340:\nadd edx, 1\nadd rax, 4\ncmp edx, edi\njz short loc_137D\nloc_134B:\nmov esi, ecx\nmov ecx, [rax+4]\ncmp ecx, esi\njz short loc_1340\nadd r8d, edx\ncmp r11d, edx\ncmovl r11d, edx\ncmp r10d, r8d\njg short loc_1320\nmov eax, r11d\nretn\nloc_1370:\nsub edi, 1\njmp loc_12D0\nloc_1378:\nmov edi, 1\nloc_137D:\ncmp r11d, edi\ncmovl r11d, edi\nmov eax, r11d\nretn\nloc_1388:\njz short loc_1391\nxor r11d, r11d\nmov eax, r11d\nretn\nloc_1391:\nmov edi, 1\nxor r11d, r11d\njmp short loc_137D", + "ida_strip_pseudo": "__int64 __fastcall sub_12B0(__m128i *a1, int a2)\n{\n int i; // edi\n __m128i *v5; // rax\n __m128i v6; // xmm0\n int v7; // r8d\n int v8; // r11d\n int v9; // edx\n __int32 *v10; // rax\n int v11; // edi\n __int32 v12; // ecx\n int v13; // esi\n\n if ( a2 <= 1 )\n {\n if ( a2 != 1 )\n return 0LL;\n v11 = 1;\n v8 = 0;\n }\n else\n {\n for ( i = a2; i != 1; --i )\n {\n while ( i <= 1 )\n --i;\n v5 = a1;\n do\n {\n v6 = _mm_loadl_epi64(v5);\n if ( _mm_cvtsi128_si32(_mm_shuffle_epi32(v6, 229)) < _mm_cvtsi128_si32(v6) )\n v5->m128i_i64[0] = _mm_shuffle_epi32(v6, 225).m128i_u64[0];\n v5 = (__m128i *)((char *)v5 + 4);\n }\n while ( v5 != (__m128i *)((char *)a1->m128i_i64 + 4 * (unsigned int)(i - 2) + 4) );\n }\n v7 = 0;\n v8 = 0;\n while ( a2 > v7 + 1 )\n {\n v9 = 1;\n v10 = &a1->m128i_i32[v7];\n v11 = a2 - v7;\n v12 = *v10;\n while ( 1 )\n {\n v13 = v12;\n v12 = v10[1];\n if ( v12 != v13 )\n break;\n ++v9;\n ++v10;\n if ( v9 == v11 )\n goto LABEL_20;\n }\n v7 += v9;\n if ( v8 < v9 )\n v8 = v9;\n if ( a2 <= v7 )\n return (unsigned int)v8;\n }\n v11 = 1;\n }\nLABEL_20:\n if ( v8 < v11 )\n return (unsigned int)v11;\n return (unsigned int)v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_12B0(__m128i *a1, int a2) {\n int i;\n __m128i *v5;\n __m128i v6;\n int v7;\n int v8;\n int v9;\n int *v10;\n int v11;\n int v12;\n int v13;\n if (a2 <= 1) {\n if (a2 != 1) return 0LL;\n v11 = 1;\n v8 = 0;\n } else {\n for (i = a2; i != 1; --i) {\n while (i <= 1) --i;\n v5 = a1;\n do {\n v6 = _mm_loadl_epi64(v5);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v6, 229)) <\n _mm_cvtsi128_si32(v6))\n v5->m128i_i64[0] = _mm_shuffle_epi32(v6, 225).m128i_u64[0];\n v5 = (__m128i *)((char *)v5 + 4);\n } while (v5 != (__m128i *)((char *)a1->m128i_i64 +\n 4 * (unsigned int)(i - 2) + 4));\n }\n v7 = 0;\n v8 = 0;\n while (a2 > v7 + 1) {\n v9 = 1;\n v10 = &a1->m128i_i32[v7];\n v11 = a2 - v7;\n v12 = *v10;\n while (1) {\n v13 = v12;\n v12 = v10[1];\n if (v12 != v13) break;\n ++v9;\n ++v10;\n if (v9 == v11) goto LABEL_20;\n }\n v7 += v9;\n if (v8 < v9) v8 = v9;\n if (a2 <= v7) return (unsigned int)v8;\n }\n v11 = 1;\n }\nLABEL_20:\n if (v8 < v11) return (unsigned int)v11;\n return (unsigned int)v8;\n}", + "ida_pseudo_norm": "long long func0(__m128i *a1, int a2) {\n int i;\n __m128i *v5;\n __m128i v6;\n int v7;\n int v8;\n int v9;\n int *v10;\n int v11;\n int v12;\n int v13;\n if (a2 <= 1) {\n if (a2 != 1) return 0LL;\n v11 = 1;\n v8 = 0;\n } else {\n for (i = a2; i != 1; --i) {\n while (i <= 1) --i;\n v5 = a1;\n do {\n v6 = _mm_loadl_epi64(v5);\n if (_mm_cvtsi128_si32(_mm_shuffle_epi32(v6, 229)) <\n _mm_cvtsi128_si32(v6))\n v5->m128i_i64[0] = _mm_shuffle_epi32(v6, 225).m128i_u64[0];\n v5 = (__m128i *)((char *)v5 + 4);\n } while (v5 != (__m128i *)((char *)a1->m128i_i64 +\n 4 * (unsigned int)(i - 2) + 4));\n }\n v7 = 0;\n v8 = 0;\n while (a2 > v7 + 1) {\n v9 = 1;\n v10 = &a1->m128i_i32[v7];\n v11 = a2 - v7;\n v12 = *v10;\n while (1) {\n v13 = v12;\n v12 = v10[1];\n if (v12 != v13) break;\n ++v9;\n ++v10;\n if (v9 == v11) goto LABEL_20;\n }\n v7 += v9;\n if (v8 < v9) v8 = v9;\n if (a2 <= v7) return (unsigned int)v8;\n }\n v11 = 1;\n }\nLABEL_20:\n if (v8 < v11) return (unsigned int)v11;\n return (unsigned int)v8;\n}" + }, + { + "index": 954, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int actual_cost, int sale_amount) {\n if (actual_cost > sale_amount) {\n return actual_cost - sale_amount;\n } else {\n return -1;\n }\n}", + "test": "int main() {\n\n assert(func0(1500, 1200) == 300);\n\n assert(func0(100, 200) == -1);\n\n assert(func0(2000, 5000) == -1);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov %esi,-0x8(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x8(%rbp),%eax\njle 1167 \nmov -0x4(%rbp),%eax\nsub -0x8(%rbp),%eax\njmp 116c \nmov $0xffffffff,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_8]\njle short loc_1167\nmov eax, [rbp+var_4]\nsub eax, [rbp+var_8]\njmp short loc_116C\nloc_1167:\nmov eax, 0FFFFFFFFh\nloc_116C:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n if ( a1 <= a2 )\n return 0xFFFFFFFFLL;\n else\n return (unsigned int)(a1 - a2);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_8]\njle short loc_1167\nmov eax, [rbp+var_4]\nsub eax, [rbp+var_8]\njmp short loc_116C\nloc_1167:\nmov eax, 0FFFFFFFFh\nloc_116C:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2)\n{\n if ( a1 <= a2 )\n return 0xFFFFFFFFLL;\n else\n return (unsigned int)(a1 - a2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2) {\n if (a1 <= a2)\n return 4294967295LL;\n else\n return (unsigned int)(a1 - a2);\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n if (a1 <= a2)\n return 4294967295LL;\n else\n return (unsigned int)(a1 - a2);\n}" + }, + { + "index": 955, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int fctrsum = 0;\n for (int fctr = 1; fctr < n; fctr++) {\n if (n % fctr == 0) {\n fctrsum += fctr;\n }\n }\n return fctrsum > n;\n}", + "test": "int main() {\n\n assert(func0(12) == 1);\n\n assert(func0(13) == 0);\n\n assert(func0(9) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x1,-0x4(%rbp)\njmp 117b \nmov -0x14(%rbp),%eax\ncltd\nidivl -0x4(%rbp)\nmov %edx,%eax\ntest %eax,%eax\njne 1177 \nmov -0x4(%rbp),%eax\nadd %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x14(%rbp),%eax\njl 1164 \nmov -0x8(%rbp),%eax\ncmp -0x14(%rbp),%eax\nsetg %al\nmovzbl %al,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 1\njmp short loc_117B\nloc_1164:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njnz short loc_1177\nmov eax, [rbp+var_4]\nadd [rbp+var_8], eax\nloc_1177:\nadd [rbp+var_4], 1\nloc_117B:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_14]\njl short loc_1164\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_14]\nsetnle al\nmovzx eax, al\npop rbp\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(int a1)\n{\n int v2; // [rsp+Ch] [rbp-8h]\n int i; // [rsp+10h] [rbp-4h]\n\n v2 = 0;\n for ( i = 1; i < a1; ++i )\n {\n if ( !(a1 % i) )\n v2 += i;\n }\n return v2 > a1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 1\njmp short loc_117B\nloc_1164:\nmov eax, [rbp+var_14]\ncdq\nidiv [rbp+var_4]\nmov eax, edx\ntest eax, eax\njnz short loc_1177\nmov eax, [rbp+var_4]\nadd [rbp+var_8], eax\nloc_1177:\nadd [rbp+var_4], 1\nloc_117B:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_14]\njl short loc_1164\nmov eax, [rbp+var_8]\ncmp eax, [rbp+var_14]\nsetnle al\nmovzx eax, al\npop rbp\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1149(int a1)\n{\n int v2; // [rsp+Ch] [rbp-8h]\n int i; // [rsp+10h] [rbp-4h]\n\n v2 = 0;\n for ( i = 1; i < a1; ++i )\n {\n if ( !(a1 % i) )\n v2 += i;\n }\n return v2 > a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1149(int a1) {\n int v2;\n int i;\n v2 = 0;\n for (i = 1; i < a1; ++i) {\n if (!(a1 % i)) v2 += i;\n }\n return v2 > a1;\n}", + "ida_pseudo_norm": "uint8_t func0(int a1) {\n int v2;\n int i;\n v2 = 0;\n for (i = 1; i < a1; ++i) {\n if (!(a1 % i)) v2 += i;\n }\n return v2 > a1;\n}" + }, + { + "index": 955, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) {\n int fctrsum = 0;\n for (int fctr = 1; fctr < n; fctr++) {\n if (n % fctr == 0) {\n fctrsum += fctr;\n }\n }\n return fctrsum > n;\n}", + "test": "int main() {\n\n assert(func0(12) == 1);\n\n assert(func0(13) == 0);\n\n assert(func0(9) == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ncmp $0x1,%edi\njle 1179 \nmov $0x1,%ecx\nmov $0x0,%esi\nmov %edi,%eax\ncltd\nidiv %ecx\nlea (%rsi,%rcx,1),%eax\ntest %edx,%edx\ncmove %eax,%esi\nadd $0x1,%ecx\ncmp %ecx,%edi\njne 115c \ncmp %esi,%edi\nsetl %al\nmovzbl %al,%eax\nretq\nmov $0x0,%esi\njmp 1170 \n", + "ida_asm": "func0:\nendbr64\ncmp edi, 1\njle short loc_1179\nmov ecx, 1\nmov esi, 0\nloc_115C:\nmov eax, edi\ncdq\nidiv ecx\nlea eax, [rsi+rcx]\ntest edx, edx\ncmovz esi, eax\nadd ecx, 1\ncmp edi, ecx\njnz short loc_115C\nloc_1170:\ncmp edi, esi\nsetl al\nmovzx eax, al\nretn\nloc_1179:\nmov esi, 0\njmp short loc_1170", + "ida_pseudo": "_BOOL8 __fastcall func0(int a1)\n{\n int v1; // ecx\n int v2; // esi\n\n if ( a1 <= 1 )\n {\n v2 = 0;\n }\n else\n {\n v1 = 1;\n v2 = 0;\n do\n {\n if ( !(a1 % v1) )\n v2 += v1;\n ++v1;\n }\n while ( a1 != v1 );\n }\n return a1 < v2;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\ncmp edi, 1\njle short loc_1179\nmov ecx, 1\nmov esi, 0\nloc_115C:\nmov eax, edi\ncdq\nidiv ecx\nlea eax, [rsi+rcx]\ntest edx, edx\ncmovz esi, eax\nadd ecx, 1\ncmp edi, ecx\njnz short loc_115C\nloc_1170:\ncmp edi, esi\nsetl al\nmovzx eax, al\nretn\nloc_1179:\nmov esi, 0\njmp short loc_1170", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1149(int a1)\n{\n int v1; // ecx\n int v2; // esi\n\n if ( a1 <= 1 )\n {\n v2 = 0;\n }\n else\n {\n v1 = 1;\n v2 = 0;\n do\n {\n if ( !(a1 % v1) )\n v2 += v1;\n ++v1;\n }\n while ( a1 != v1 );\n }\n return a1 < v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1149(int a1) {\n int v1;\n int v2;\n if (a1 <= 1) {\n v2 = 0;\n } else {\n v1 = 1;\n v2 = 0;\n do {\n if (!(a1 % v1)) v2 += v1;\n ++v1;\n } while (a1 != v1);\n }\n return a1 < v2;\n}", + "ida_pseudo_norm": "uint8_t func0(int a1) {\n int v1;\n int v2;\n if (a1 <= 1) {\n v2 = 0;\n } else {\n v1 = 1;\n v2 = 0;\n do {\n if (!(a1 % v1)) v2 += v1;\n ++v1;\n } while (a1 != v1);\n }\n return a1 < v2;\n}" + }, + { + "index": 956, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(const char* text, int* count) {\n int n = strlen(text);\n char** result = malloc(n * sizeof(char*));\n *count = 0;\n int word_start = 0;\n for (int i = 1; i <= n; i++) {\n if (i == n || (isupper(text[i]) && !isupper(text[i - 1]))) {\n int word_length = i - word_start;\n result[*count] = malloc((word_length + 1) * sizeof(char));\n strncpy(result[*count], text + word_start, word_length);\n result[*count][word_length] = '\\0';\n (*count)++;\n word_start = i;\n }\n }\n return result;\n}", + "test": "int main() {\n\n int count1, count2, count3;\n\n char** result1 = func0(\"LearnToBuildAnythingWithGoogle\", &count1);\n\n char** result2 = func0(\"ApmlifyingTheBlack+DeveloperCommunity\", &count2);\n\n char** result3 = func0(\"UpdateInTheGoEcoSystem\", &count3);\n\n\n\n assert(count1 == 6);\n\n assert(strcmp(result1[0], \"Learn\") == 0);\n\n assert(strcmp(result1[1], \"To\") == 0);\n\n assert(strcmp(result1[2], \"Build\") == 0);\n\n assert(strcmp(result1[3], \"Anything\") == 0);\n\n assert(strcmp(result1[4], \"With\") == 0);\n\n assert(strcmp(result1[5], \"Google\") == 0);\n\n\n\n assert(count2 == 5);\n\n assert(strcmp(result2[0], \"Apmlifying\") == 0);\n\n assert(strcmp(result2[1], \"The\") == 0);\n\n assert(strcmp(result2[2], \"Black+\") == 0);\n\n assert(strcmp(result2[3], \"Developer\") == 0);\n\n assert(strcmp(result2[4], \"Community\") == 0);\n\n\n\n assert(count3 == 6);\n\n assert(strcmp(result3[0], \"Update\") == 0);\n\n assert(strcmp(result3[1], \"In\") == 0);\n\n assert(strcmp(result3[2], \"The\") == 0);\n\n assert(strcmp(result3[3], \"Go\") == 0);\n\n assert(strcmp(result3[4], \"Eco\") == 0);\n\n assert(strcmp(result3[5], \"System\") == 0);\n\n\n\n for (int i = 0; i < count1; i++) free(result1[i]);\n\n free(result1);\n\n for (int i = 0; i < count2; i++) free(result2[i]);\n\n free(result2);\n\n for (int i = 0; i < count3; i++) free(result3[i]);\n\n free(result3);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x38,%rsp\nmov %rdi,-0x38(%rbp)\nmov %rsi,-0x40(%rbp)\nmov -0x38(%rbp),%rax\nmov %rax,%rdi\ncallq 10e0 \nmov %eax,-0x20(%rbp)\nmov -0x20(%rbp),%eax\ncltq\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 1120 \nmov %rax,-0x18(%rbp)\nmov -0x40(%rbp),%rax\nmovl $0x0,(%rax)\nmovl $0x0,-0x28(%rbp)\nmovl $0x1,-0x24(%rbp)\njmpq 13a0 \nmov -0x24(%rbp),%eax\ncmp -0x20(%rbp),%eax\nje 12f5 \ncallq 1130 <__ctype_b_loc@plt>\nmov (%rax),%rax\nmov -0x24(%rbp),%edx\nmovslq %edx,%rcx\nmov -0x38(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rdx),%edx\nmovsbq %dl,%rdx\nadd %rdx,%rdx\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x100,%eax\ntest %eax,%eax\nje 139c \ncallq 1130 <__ctype_b_loc@plt>\nmov (%rax),%rax\nmov -0x24(%rbp),%edx\nmovslq %edx,%rdx\nlea -0x1(%rdx),%rcx\nmov -0x38(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rdx),%edx\nmovsbq %dl,%rdx\nadd %rdx,%rdx\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x100,%eax\ntest %eax,%eax\njne 139c \nmov -0x24(%rbp),%eax\nsub -0x28(%rbp),%eax\nmov %eax,-0x1c(%rbp)\nmov -0x1c(%rbp),%eax\nadd $0x1,%eax\ncltq\nmov -0x40(%rbp),%rdx\nmov (%rdx),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,8),%rcx\nmov -0x18(%rbp),%rdx\nlea (%rcx,%rdx,1),%rbx\nmov %rax,%rdi\ncallq 1120 \nmov %rax,(%rbx)\nmov -0x1c(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x28(%rbp),%eax\nmovslq %eax,%rcx\nmov -0x38(%rbp),%rax\nadd %rax,%rcx\nmov -0x40(%rbp),%rax\nmov (%rax),%eax\ncltq\nlea 0x0(,%rax,8),%rsi\nmov -0x18(%rbp),%rax\nadd %rsi,%rax\nmov (%rax),%rax\nmov %rcx,%rsi\nmov %rax,%rdi\ncallq 10d0 \nmov -0x40(%rbp),%rax\nmov (%rax),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rdx\nmov -0x1c(%rbp),%eax\ncltq\nadd %rdx,%rax\nmovb $0x0,(%rax)\nmov -0x40(%rbp),%rax\nmov (%rax),%eax\nlea 0x1(%rax),%edx\nmov -0x40(%rbp),%rax\nmov %edx,(%rax)\nmov -0x24(%rbp),%eax\nmov %eax,-0x28(%rbp)\naddl $0x1,-0x24(%rbp)\nmov -0x24(%rbp),%eax\ncmp -0x20(%rbp),%eax\njle 127f \nmov -0x18(%rbp),%rax\nadd $0x38,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+s], rdi\nmov [rbp+var_40], rsi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_20], eax\nmov eax, [rbp+var_20]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov rax, [rbp+var_40]\nmov dword ptr [rax], 0\nmov [rbp+var_28], 0\nmov [rbp+var_24], 1\njmp loc_13A0\nloc_127F:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_20]\njz short loc_12F5\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_24]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 100h\ntest eax, eax\njz loc_139C\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nlea rcx, [rdx-1]\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 100h\ntest eax, eax\njnz loc_139C\nloc_12F5:\nmov eax, [rbp+var_24]\nsub eax, [rbp+var_28]\nmov [rbp+var_1C], eax\nmov eax, [rbp+var_1C]\nadd eax, 1\ncdqe\nmov rdx, [rbp+var_40]\nmov edx, [rdx]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nlea rbx, [rcx+rdx]\nmov rdi, rax; size\ncall _malloc\nmov [rbx], rax\nmov eax, [rbp+var_1C]\nmovsxd rdx, eax; n\nmov eax, [rbp+var_28]\nmovsxd rcx, eax\nmov rax, [rbp+s]\nadd rcx, rax\nmov rax, [rbp+var_40]\nmov eax, [rax]\ncdqe\nlea rsi, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rsi\nmov rax, [rax]\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strncpy\nmov rax, [rbp+var_40]\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_1C]\ncdqe\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+var_40]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_40]\nmov [rax], edx\nmov eax, [rbp+var_24]\nmov [rbp+var_28], eax\nloc_139C:\nadd [rbp+var_24], 1\nloc_13A0:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_20]\njle loc_127F\nmov rax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "char **__fastcall func0(const char *a1, int *a2)\n{\n void **v2; // rbx\n int v4; // [rsp+18h] [rbp-28h]\n int i; // [rsp+1Ch] [rbp-24h]\n int v6; // [rsp+20h] [rbp-20h]\n char **v7; // [rsp+28h] [rbp-18h]\n\n v6 = strlen(a1);\n v7 = (char **)malloc(8LL * v6);\n *a2 = 0;\n v4 = 0;\n for ( i = 1; i <= v6; ++i )\n {\n if ( i == v6 || ((*__ctype_b_loc())[a1[i]] & 0x100) != 0 && ((*__ctype_b_loc())[a1[i - 1]] & 0x100) == 0 )\n {\n v2 = (void **)&v7[*a2];\n *v2 = malloc(i - v4 + 1);\n strncpy(v7[*a2], &a1[v4], i - v4);\n v7[(*a2)++][i - v4] = 0;\n v4 = i;\n }\n }\n return v7;\n}", + "ida_strip_asm": "sub_1229:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+s], rdi\nmov [rbp+var_40], rsi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_20], eax\nmov eax, [rbp+var_20]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov rax, [rbp+var_40]\nmov dword ptr [rax], 0\nmov [rbp+var_28], 0\nmov [rbp+var_24], 1\njmp loc_13A0\nloc_127F:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_20]\njz short loc_12F5\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_24]\nmovsxd rcx, edx\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 100h\ntest eax, eax\njz loc_139C\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nlea rcx, [rdx-1]\nmov rdx, [rbp+s]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 100h\ntest eax, eax\njnz loc_139C\nloc_12F5:\nmov eax, [rbp+var_24]\nsub eax, [rbp+var_28]\nmov [rbp+var_1C], eax\nmov eax, [rbp+var_1C]\nadd eax, 1\ncdqe\nmov rdx, [rbp+var_40]\nmov edx, [rdx]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*8]\nmov rdx, [rbp+var_18]\nlea rbx, [rcx+rdx]\nmov rdi, rax; size\ncall _malloc\nmov [rbx], rax\nmov eax, [rbp+var_1C]\nmovsxd rdx, eax; n\nmov eax, [rbp+var_28]\nmovsxd rcx, eax\nmov rax, [rbp+s]\nadd rcx, rax\nmov rax, [rbp+var_40]\nmov eax, [rax]\ncdqe\nlea rsi, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rsi\nmov rax, [rax]\nmov rsi, rcx; src\nmov rdi, rax; dest\ncall _strncpy\nmov rax, [rbp+var_40]\nmov eax, [rax]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rdx, [rax]\nmov eax, [rbp+var_1C]\ncdqe\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+var_40]\nmov eax, [rax]\nlea edx, [rax+1]\nmov rax, [rbp+var_40]\nmov [rax], edx\nmov eax, [rbp+var_24]\nmov [rbp+var_28], eax\nloc_139C:\nadd [rbp+var_24], 1\nloc_13A0:\nmov eax, [rbp+var_24]\ncmp eax, [rbp+var_20]\njle loc_127F\nmov rax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "char **__fastcall sub_1229(const char *a1, int *a2)\n{\n void **v2; // rbx\n int v4; // [rsp+18h] [rbp-28h]\n int i; // [rsp+1Ch] [rbp-24h]\n int v6; // [rsp+20h] [rbp-20h]\n char **v7; // [rsp+28h] [rbp-18h]\n\n v6 = strlen(a1);\n v7 = (char **)malloc(8LL * v6);\n *a2 = 0;\n v4 = 0;\n for ( i = 1; i <= v6; ++i )\n {\n if ( i == v6 || ((*__ctype_b_loc())[a1[i]] & 0x100) != 0 && ((*__ctype_b_loc())[a1[i - 1]] & 0x100) == 0 )\n {\n v2 = (void **)&v7[*a2];\n *v2 = malloc(i - v4 + 1);\n strncpy(v7[*a2], &a1[v4], i - v4);\n v7[(*a2)++][i - v4] = 0;\n v4 = i;\n }\n }\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char **sub_1229(const char *a1, int *a2) {\n void **v2;\n int v4;\n int i;\n int v6;\n char **v7;\n v6 = strlen(a1);\n v7 = (char **)malloc(8LL * v6);\n *a2 = 0;\n v4 = 0;\n for (i = 1; i <= v6; ++i) {\n if (i == v6 || ((*__ctype_b_loc())[a1[i]] & 256) != 0 &&\n ((*__ctype_b_loc())[a1[i - 1]] & 256) == 0) {\n v2 = (void **)&v7[*a2];\n *v2 = malloc(i - v4 + 1);\n strncpy(v7[*a2], &a1[v4], i - v4);\n v7[(*a2)++][i - v4] = 0;\n v4 = i;\n }\n }\n return v7;\n}", + "ida_pseudo_norm": "char **func0(const char *a1, int *a2) {\n void **v2;\n int v4;\n int i;\n int v6;\n char **v7;\n v6 = strlen(a1);\n v7 = (char **)malloc(8LL * v6);\n *a2 = 0;\n v4 = 0;\n for (i = 1; i <= v6; ++i) {\n if (i == v6 || ((*__ctype_b_loc())[a1[i]] & 256) != 0 &&\n ((*__ctype_b_loc())[a1[i - 1]] & 256) == 0) {\n v2 = (void **)&v7[*a2];\n *v2 = malloc(i - v4 + 1);\n strncpy(v7[*a2], &a1[v4], i - v4);\n v7[(*a2)++][i - v4] = 0;\n v4 = i;\n }\n }\n return v7;\n}" + }, + { + "index": 956, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(const char* text, int* count) {\n int n = strlen(text);\n char** result = malloc(n * sizeof(char*));\n *count = 0;\n int word_start = 0;\n for (int i = 1; i <= n; i++) {\n if (i == n || (isupper(text[i]) && !isupper(text[i - 1]))) {\n int word_length = i - word_start;\n result[*count] = malloc((word_length + 1) * sizeof(char));\n strncpy(result[*count], text + word_start, word_length);\n result[*count][word_length] = '\\0';\n (*count)++;\n word_start = i;\n }\n }\n return result;\n}", + "test": "int main() {\n\n int count1, count2, count3;\n\n char** result1 = func0(\"LearnToBuildAnythingWithGoogle\", &count1);\n\n char** result2 = func0(\"ApmlifyingTheBlack+DeveloperCommunity\", &count2);\n\n char** result3 = func0(\"UpdateInTheGoEcoSystem\", &count3);\n\n\n\n assert(count1 == 6);\n\n assert(strcmp(result1[0], \"Learn\") == 0);\n\n assert(strcmp(result1[1], \"To\") == 0);\n\n assert(strcmp(result1[2], \"Build\") == 0);\n\n assert(strcmp(result1[3], \"Anything\") == 0);\n\n assert(strcmp(result1[4], \"With\") == 0);\n\n assert(strcmp(result1[5], \"Google\") == 0);\n\n\n\n assert(count2 == 5);\n\n assert(strcmp(result2[0], \"Apmlifying\") == 0);\n\n assert(strcmp(result2[1], \"The\") == 0);\n\n assert(strcmp(result2[2], \"Black+\") == 0);\n\n assert(strcmp(result2[3], \"Developer\") == 0);\n\n assert(strcmp(result2[4], \"Community\") == 0);\n\n\n\n assert(count3 == 6);\n\n assert(strcmp(result3[0], \"Update\") == 0);\n\n assert(strcmp(result3[1], \"In\") == 0);\n\n assert(strcmp(result3[2], \"The\") == 0);\n\n assert(strcmp(result3[3], \"Go\") == 0);\n\n assert(strcmp(result3[4], \"Eco\") == 0);\n\n assert(strcmp(result3[5], \"System\") == 0);\n\n\n\n for (int i = 0; i < count1; i++) free(result1[i]);\n\n free(result1);\n\n for (int i = 0; i < count2; i++) free(result2[i]);\n\n free(result2);\n\n for (int i = 0; i < count3; i++) free(result3[i]);\n\n free(result3);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x28,%rsp\nmov %rdi,%r12\nmov %rsi,%rbp\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nlea -0x1(%rcx),%rbx\nmov %ebx,0x14(%rsp)\nmovslq %ebx,%rdi\nshl $0x3,%rdi\ncallq 10e0 \nmov %rax,%r14\nmovl $0x0,0x0(%rbp)\ntest %ebx,%ebx\njle 12e9 \nlea -0x1(%rbx),%r15d\nadd $0x2,%r15\nmov $0x1,%ebx\nmovl $0x0,0x10(%rsp)\njmp 12b9 \nmov 0xc(%rsp),%r13d\nsub 0x10(%rsp),%r13d\nmovslq 0x0(%rbp),%rax\nlea (%r14,%rax,8),%rcx\nmov %rcx,0x18(%rsp)\nlea 0x1(%r13),%edi\nmovslq %edi,%rdi\ncallq 10e0 \nmov 0x18(%rsp),%rcx\nmov %rax,(%rcx)\nmovslq %r13d,%r13\nmovslq 0x10(%rsp),%rsi\nadd %r12,%rsi\nmovslq 0x0(%rbp),%rax\nmov (%r14,%rax,8),%rdi\nmov %r13,%rdx\ncallq 10b0 \nmovslq 0x0(%rbp),%rax\nmov (%r14,%rax,8),%rax\nmovb $0x0,(%rax,%r13,1)\naddl $0x1,0x0(%rbp)\nmov 0xc(%rsp),%r13d\nmov %r13d,0x10(%rsp)\nadd $0x1,%rbx\ncmp %r15,%rbx\nje 12e9 \nmov %ebx,0xc(%rsp)\ncmp %ebx,0x14(%rsp)\nje 124f \ncallq 10f0 <__ctype_b_loc@plt>\nmov (%rax),%rax\nmovsbq (%r12,%rbx,1),%rdx\ntestb $0x1,0x1(%rax,%rdx,2)\nje 12b0 \nmovsbq -0x1(%r12,%rbx,1),%rdx\ntestb $0x1,0x1(%rax,%rdx,2)\njne 12b0 \njmpq 124f \nmov %r14,%rax\nadd $0x28,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov rbp, rdi\nmov r13, rsi\ncall _strlen\nmov rbx, rax\nmov [rsp+58h+var_40], eax\nmovsxd rdi, eax\nshl rdi, 3; size\ncall _malloc\nmov [rsp+58h+var_48], rax\nmov dword ptr [r13+0], 0\ntest ebx, ebx\njle loc_1320\nlea r14d, [rbx-1]\nadd r14, 2\nmov ebx, 1\nmov [rsp+58h+var_4C], 0\njmp short loc_12F3\nloc_1285:\nmov r12d, ebx\nmov eax, [rsp+58h+var_4C]\nsub r12d, eax\nmovsxd rax, dword ptr [r13+0]\nmov rcx, [rsp+58h+var_48]\nlea r15, [rcx+rax*8]\nlea edi, [r12+1]\nmovsxd rdi, edi; size\ncall _malloc\nmov [r15], rax\nmovsxd r12, r12d\nmov esi, [r13+0]\nmov [rsp+58h+var_3C], esi\nmovsxd rax, esi\nmov rcx, [rsp+58h+var_48]\nmov r15, [rcx+rax*8]\nmovsxd rsi, [rsp+58h+var_4C]\nadd rsi, rbp; src\nmov rdx, r12; n\nmov rdi, r15; dest\ncall _strncpy\nmov byte ptr [r15+r12], 0\nmov esi, [rsp+58h+var_3C]\nlea eax, [rsi+1]\nmov [r13+0], eax\nmov [rsp+58h+var_4C], ebx\nloc_12EA:\nadd rbx, 1\ncmp rbx, r14\njz short loc_1320\nloc_12F3:\ncmp [rsp+58h+var_40], ebx\njz short loc_1285\ncall ___ctype_b_loc\nmov rax, [rax]\nmovsx rdx, byte ptr [rbp+rbx+0]\ntest byte ptr [rax+rdx*2+1], 1\njz short loc_12EA\nmovsx rdx, byte ptr [rbp+rbx-1]\ntest byte ptr [rax+rdx*2+1], 1\njnz short loc_12EA\njmp loc_1285\nloc_1320:\nmov rax, [rsp+58h+var_48]\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(const char *a1, int *a2)\n{\n int v2; // ebx\n __int64 v3; // r14\n __int64 v4; // rbx\n void **v5; // r15\n char *v6; // r15\n const unsigned __int16 *v7; // rax\n int v9; // [rsp+Ch] [rbp-4Ch]\n _QWORD *v10; // [rsp+10h] [rbp-48h]\n int v11; // [rsp+18h] [rbp-40h]\n int v12; // [rsp+1Ch] [rbp-3Ch]\n\n v2 = strlen(a1);\n v11 = v2;\n v10 = malloc(8LL * v2);\n *a2 = 0;\n if ( v2 > 0 )\n {\n v3 = (unsigned int)(v2 - 1) + 2LL;\n v4 = 1LL;\n v9 = 0;\n do\n {\n if ( v11 == (_DWORD)v4 || (v7 = *__ctype_b_loc(), (v7[a1[v4]] & 0x100) != 0) && (v7[a1[v4 - 1]] & 0x100) == 0 )\n {\n v5 = (void **)&v10[*a2];\n *v5 = malloc((int)v4 - v9 + 1);\n v12 = *a2;\n v6 = (char *)v10[*a2];\n strncpy(v6, &a1[v9], (int)v4 - v9);\n v6[(int)v4 - v9] = 0;\n *a2 = v12 + 1;\n v9 = v4;\n }\n ++v4;\n }\n while ( v4 != v3 );\n }\n return v10;\n}", + "ida_strip_asm": "sub_1229:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 28h\nmov rbp, rdi\nmov r13, rsi\ncall _strlen\nmov rbx, rax\nmov [rsp+58h+var_40], eax\nmovsxd rdi, eax\nshl rdi, 3; size\ncall _malloc\nmov [rsp+58h+var_48], rax\nmov dword ptr [r13+0], 0\ntest ebx, ebx\njle loc_1320\nlea r14d, [rbx-1]\nadd r14, 2\nmov ebx, 1\nmov [rsp+58h+var_4C], 0\njmp short loc_12F3\nloc_1285:\nmov r12d, ebx\nmov eax, [rsp+58h+var_4C]\nsub r12d, eax\nmovsxd rax, dword ptr [r13+0]\nmov rcx, [rsp+58h+var_48]\nlea r15, [rcx+rax*8]\nlea edi, [r12+1]\nmovsxd rdi, edi; size\ncall _malloc\nmov [r15], rax\nmovsxd r12, r12d\nmov esi, [r13+0]\nmov [rsp+58h+var_3C], esi\nmovsxd rax, esi\nmov rcx, [rsp+58h+var_48]\nmov r15, [rcx+rax*8]\nmovsxd rsi, [rsp+58h+var_4C]\nadd rsi, rbp; src\nmov rdx, r12; n\nmov rdi, r15; dest\ncall _strncpy\nmov byte ptr [r15+r12], 0\nmov esi, [rsp+58h+var_3C]\nlea eax, [rsi+1]\nmov [r13+0], eax\nmov [rsp+58h+var_4C], ebx\nloc_12EA:\nadd rbx, 1\ncmp rbx, r14\njz short loc_1320\nloc_12F3:\ncmp [rsp+58h+var_40], ebx\njz short loc_1285\ncall ___ctype_b_loc\nmov rax, [rax]\nmovsx rdx, byte ptr [rbp+rbx+0]\ntest byte ptr [rax+rdx*2+1], 1\njz short loc_12EA\nmovsx rdx, byte ptr [rbp+rbx-1]\ntest byte ptr [rax+rdx*2+1], 1\njnz short loc_12EA\njmp loc_1285\nloc_1320:\nmov rax, [rsp+58h+var_48]\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1229(const char *a1, int *a2)\n{\n int v2; // ebx\n __int64 v3; // r14\n __int64 v4; // rbx\n void **v5; // r15\n char *v6; // r15\n const unsigned __int16 *v7; // rax\n int v9; // [rsp+Ch] [rbp-4Ch]\n _QWORD *v10; // [rsp+10h] [rbp-48h]\n int v11; // [rsp+18h] [rbp-40h]\n int v12; // [rsp+1Ch] [rbp-3Ch]\n\n v2 = strlen(a1);\n v11 = v2;\n v10 = malloc(8LL * v2);\n *a2 = 0;\n if ( v2 > 0 )\n {\n v3 = (unsigned int)(v2 - 1) + 2LL;\n v4 = 1LL;\n v9 = 0;\n do\n {\n if ( v11 == (_DWORD)v4 || (v7 = *__ctype_b_loc(), (v7[a1[v4]] & 0x100) != 0) && (v7[a1[v4 - 1]] & 0x100) == 0 )\n {\n v5 = (void **)&v10[*a2];\n *v5 = malloc((int)v4 - v9 + 1);\n v12 = *a2;\n v6 = (char *)v10[*a2];\n strncpy(v6, &a1[v9], (int)v4 - v9);\n v6[(int)v4 - v9] = 0;\n *a2 = v12 + 1;\n v9 = v4;\n }\n ++v4;\n }\n while ( v4 != v3 );\n }\n return v10;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1229(const char *a1, int *a2) {\n int v2;\n long long v3;\n long long v4;\n void **v5;\n char *v6;\n const unsigned short *v7;\n int v9;\n uint64_t *v10;\n int v11;\n int v12;\n v2 = strlen(a1);\n v11 = v2;\n v10 = malloc(8LL * v2);\n *a2 = 0;\n if (v2 > 0) {\n v3 = (unsigned int)(v2 - 1) + 2LL;\n v4 = 1LL;\n v9 = 0;\n do {\n if (v11 == (uint32_t)v4 ||\n (v7 = *__ctype_b_loc(), (v7[a1[v4]] & 256) != 0) &&\n (v7[a1[v4 - 1]] & 256) == 0) {\n v5 = (void **)&v10[*a2];\n *v5 = malloc((int)v4 - v9 + 1);\n v12 = *a2;\n v6 = (char *)v10[*a2];\n strncpy(v6, &a1[v9], (int)v4 - v9);\n v6[(int)v4 - v9] = 0;\n *a2 = v12 + 1;\n v9 = v4;\n }\n ++v4;\n } while (v4 != v3);\n }\n return v10;\n}", + "ida_pseudo_norm": "uint64_t *func0(const char *a1, int *a2) {\n int v2;\n long long v3;\n long long v4;\n void **v5;\n char *v6;\n const unsigned short *v7;\n int v9;\n uint64_t *v10;\n int v11;\n int v12;\n v2 = strlen(a1);\n v11 = v2;\n v10 = malloc(8LL * v2);\n *a2 = 0;\n if (v2 > 0) {\n v3 = (unsigned int)(v2 - 1) + 2LL;\n v4 = 1LL;\n v9 = 0;\n do {\n if (v11 == (uint32_t)v4 ||\n (v7 = *__ctype_b_loc(), (v7[a1[v4]] & 256) != 0) &&\n (v7[a1[v4 - 1]] & 256) == 0) {\n v5 = (void **)&v10[*a2];\n *v5 = malloc((int)v4 - v9 + 1);\n v12 = *a2;\n v6 = (char *)v10[*a2];\n strncpy(v6, &a1[v9], (int)v4 - v9);\n v6[(int)v4 - v9] = 0;\n *a2 = v12 + 1;\n v9 = v4;\n }\n ++v4;\n } while (v4 != v3);\n }\n return v10;\n}" + }, + { + "index": 956, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(const char* text, int* count) {\n int n = strlen(text);\n char** result = malloc(n * sizeof(char*));\n *count = 0;\n int word_start = 0;\n for (int i = 1; i <= n; i++) {\n if (i == n || (isupper(text[i]) && !isupper(text[i - 1]))) {\n int word_length = i - word_start;\n result[*count] = malloc((word_length + 1) * sizeof(char));\n strncpy(result[*count], text + word_start, word_length);\n result[*count][word_length] = '\\0';\n (*count)++;\n word_start = i;\n }\n }\n return result;\n}", + "test": "int main() {\n\n int count1, count2, count3;\n\n char** result1 = func0(\"LearnToBuildAnythingWithGoogle\", &count1);\n\n char** result2 = func0(\"ApmlifyingTheBlack+DeveloperCommunity\", &count2);\n\n char** result3 = func0(\"UpdateInTheGoEcoSystem\", &count3);\n\n\n\n assert(count1 == 6);\n\n assert(strcmp(result1[0], \"Learn\") == 0);\n\n assert(strcmp(result1[1], \"To\") == 0);\n\n assert(strcmp(result1[2], \"Build\") == 0);\n\n assert(strcmp(result1[3], \"Anything\") == 0);\n\n assert(strcmp(result1[4], \"With\") == 0);\n\n assert(strcmp(result1[5], \"Google\") == 0);\n\n\n\n assert(count2 == 5);\n\n assert(strcmp(result2[0], \"Apmlifying\") == 0);\n\n assert(strcmp(result2[1], \"The\") == 0);\n\n assert(strcmp(result2[2], \"Black+\") == 0);\n\n assert(strcmp(result2[3], \"Developer\") == 0);\n\n assert(strcmp(result2[4], \"Community\") == 0);\n\n\n\n assert(count3 == 6);\n\n assert(strcmp(result3[0], \"Update\") == 0);\n\n assert(strcmp(result3[1], \"In\") == 0);\n\n assert(strcmp(result3[2], \"The\") == 0);\n\n assert(strcmp(result3[3], \"Go\") == 0);\n\n assert(strcmp(result3[4], \"Eco\") == 0);\n\n assert(strcmp(result3[5], \"System\") == 0);\n\n\n\n for (int i = 0; i < count1; i++) free(result1[i]);\n\n free(result1);\n\n for (int i = 0; i < count2; i++) free(result2[i]);\n\n free(result2);\n\n for (int i = 0; i < count3; i++) free(result3[i]);\n\n free(result3);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\nmov %rdi,%r12\npush %rbp\nmov %rsi,%rbp\npush %rbx\nsub $0x28,%rsp\ncallq 10d0 \nmovslq %eax,%rdi\nmov %eax,0x4(%rsp)\nmov %rax,%rbx\nshl $0x3,%rdi\ncallq 1100 \nmovl $0x0,0x0(%rbp)\nmov %rax,%r14\ntest %ebx,%ebx\njle 18a8 \nlea -0x1(%rbx),%eax\nmov $0x1,%r15d\nxor %ebx,%ebx\nadd $0x2,%rax\nmov %rax,0x8(%rsp)\nnopw %cs:0x0(%rax,%rax,1)\nmov %r15d,%r13d\ncmp %r15d,0x4(%rsp)\nje 183b \ncallq 1110 <__ctype_b_loc@plt>\nmovsbq (%r12,%r15,1),%rdx\nmov (%rax),%rax\ntestb $0x1,0x1(%rax,%rdx,2)\nje 1899 \nmovsbq -0x1(%r12,%r15,1),%rdx\ntestb $0x1,0x1(%rax,%rdx,2)\njne 1899 \nmov %r13d,%edx\nmovslq 0x0(%rbp),%rax\nsub %ebx,%edx\nlea 0x1(%rdx),%edi\nlea (%r14,%rax,8),%rsi\nmov %edx,0x10(%rsp)\nmovslq %edi,%rdi\nmov %rsi,0x18(%rsp)\ncallq 1100 \nmov 0x18(%rsp),%rsi\nmovslq 0x10(%rsp),%rdx\nmov %rax,(%rsi)\nmovslq 0x0(%rbp),%rax\nmovslq %ebx,%rsi\nmov %r13d,%ebx\nadd %r12,%rsi\nmov %rdx,0x10(%rsp)\nmov (%r14,%rax,8),%rdi\ncallq 10c0 \nmovslq 0x0(%rbp),%rax\nmov 0x10(%rsp),%rdx\nmov (%r14,%rax,8),%rax\nmovb $0x0,(%rax,%rdx,1)\naddl $0x1,0x0(%rbp)\nadd $0x1,%r15\ncmp 0x8(%rsp),%r15\njne 1810 \nadd $0x28,%rsp\nmov %r14,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12, rsi\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 28h\ncall _strlen\nmovsxd rdi, eax\nmov rbx, rax\nmov r15d, eax\nshl rdi, 3; size\ncall _malloc\nmov dword ptr [r12], 0\nmov [rsp+58h+var_50], rax\ntest ebx, ebx\njle loc_1849\nlea r13d, [rbx-1]\nmov r14d, 1\nxor ebx, ebx\nadd r13, 2\nnop dword ptr [rax+00h]\nloc_17A8:\ncmp r15d, r14d\njz short loc_17CF\ncall ___ctype_b_loc\nmovsx rdx, byte ptr [rbp+r14+0]\nmov rax, [rax]\ntest byte ptr [rax+rdx*2+1], 1\njz short loc_183C\nmovsx rdx, byte ptr [rbp+r14-1]\ntest byte ptr [rax+rdx*2+1], 1\njnz short loc_183C\nloc_17CF:\nmov edx, r14d\nmov rcx, [rsp+58h+var_50]\nmovsxd rax, dword ptr [r12]\nsub edx, ebx\nlea edi, [rdx+1]\nlea rsi, [rcx+rax*8]\nmov dword ptr [rsp+58h+var_48], edx\nmovsxd rdi, edi; size\nmov [rsp+58h+var_40], rsi\ncall _malloc\nmov rsi, [rsp+58h+var_40]\nmov rcx, [rsp+58h+var_50]\nmovsxd rdx, dword ptr [rsp+58h+var_48]; n\nmov [rsi], rax\nmovsxd rax, dword ptr [r12]\nmovsxd rsi, ebx\nmov ebx, r14d\nadd rsi, rbp; src\nmov [rsp+58h+var_48], rdx\nmov rdi, [rcx+rax*8]; dest\nmov dword ptr [rsp+58h+var_40], eax\ncall _strncpy\nmov r8d, dword ptr [rsp+58h+var_40]\nmov rdx, [rsp+58h+var_48]\nadd r8d, 1\nmov byte ptr [rax+rdx], 0\nmov [r12], r8d\nloc_183C:\nadd r14, 1\ncmp r14, r13\njnz loc_17A8\nloc_1849:\nmov rax, [rsp+58h+var_50]\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "char **__fastcall func0(const char *a1, int *a2)\n{\n int v3; // ebx\n int v4; // r15d\n char **v5; // rax\n __int64 v6; // r13\n __int64 v7; // r14\n int v8; // ebx\n __int64 v9; // r13\n const unsigned __int16 *v10; // rax\n __int64 v11; // rsi\n char **v13; // [rsp+8h] [rbp-50h]\n int v14; // [rsp+10h] [rbp-48h]\n void **v15; // [rsp+18h] [rbp-40h]\n\n v3 = strlen(a1);\n v4 = v3;\n v5 = (char **)malloc(8LL * v3);\n *a2 = 0;\n v13 = v5;\n if ( v3 > 0 )\n {\n v6 = (unsigned int)(v3 - 1);\n v7 = 1LL;\n v8 = 0;\n v9 = v6 + 2;\n do\n {\n if ( v4 == (_DWORD)v7 || (v10 = *__ctype_b_loc(), (v10[a1[v7]] & 0x100) != 0) && (v10[a1[v7 - 1]] & 0x100) == 0 )\n {\n v14 = v7 - v8;\n v15 = (void **)&v13[*a2];\n *v15 = malloc((int)v7 - v8 + 1);\n v11 = v8;\n v8 = v7;\n LODWORD(v15) = *a2;\n strncpy(v13[*a2], &a1[v11], v14)[v14] = 0;\n *a2 = (_DWORD)v15 + 1;\n }\n ++v7;\n }\n while ( v7 != v9 );\n }\n return v13;\n}", + "ida_strip_asm": "sub_1750:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12, rsi\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 28h\ncall _strlen\nmovsxd rdi, eax\nmov rbx, rax\nmov r15d, eax\nshl rdi, 3; size\ncall _malloc\nmov dword ptr [r12], 0\nmov [rsp+58h+var_50], rax\ntest ebx, ebx\njle loc_1849\nlea r13d, [rbx-1]\nmov r14d, 1\nxor ebx, ebx\nadd r13, 2\nnop dword ptr [rax+00h]\nloc_17A8:\ncmp r15d, r14d\njz short loc_17CF\ncall ___ctype_b_loc\nmovsx rdx, byte ptr [rbp+r14+0]\nmov rax, [rax]\ntest byte ptr [rax+rdx*2+1], 1\njz short loc_183C\nmovsx rdx, byte ptr [rbp+r14-1]\ntest byte ptr [rax+rdx*2+1], 1\njnz short loc_183C\nloc_17CF:\nmov edx, r14d\nmov rcx, [rsp+58h+var_50]\nmovsxd rax, dword ptr [r12]\nsub edx, ebx\nlea edi, [rdx+1]\nlea rsi, [rcx+rax*8]\nmov dword ptr [rsp+58h+var_48], edx\nmovsxd rdi, edi; size\nmov [rsp+58h+var_40], rsi\ncall _malloc\nmov rsi, [rsp+58h+var_40]\nmov rcx, [rsp+58h+var_50]\nmovsxd rdx, dword ptr [rsp+58h+var_48]; n\nmov [rsi], rax\nmovsxd rax, dword ptr [r12]\nmovsxd rsi, ebx\nmov ebx, r14d\nadd rsi, rbp; src\nmov [rsp+58h+var_48], rdx\nmov rdi, [rcx+rax*8]; dest\nmov dword ptr [rsp+58h+var_40], eax\ncall _strncpy\nmov r8d, dword ptr [rsp+58h+var_40]\nmov rdx, [rsp+58h+var_48]\nadd r8d, 1\nmov byte ptr [rax+rdx], 0\nmov [r12], r8d\nloc_183C:\nadd r14, 1\ncmp r14, r13\njnz loc_17A8\nloc_1849:\nmov rax, [rsp+58h+var_50]\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "char **__fastcall sub_1750(const char *a1, int *a2)\n{\n int v3; // ebx\n int v4; // r15d\n char **v5; // rax\n __int64 v6; // r13\n __int64 v7; // r14\n int v8; // ebx\n __int64 v9; // r13\n const unsigned __int16 *v10; // rax\n __int64 v11; // rsi\n char **v13; // [rsp+8h] [rbp-50h]\n int v14; // [rsp+10h] [rbp-48h]\n void **v15; // [rsp+18h] [rbp-40h]\n\n v3 = strlen(a1);\n v4 = v3;\n v5 = (char **)malloc(8LL * v3);\n *a2 = 0;\n v13 = v5;\n if ( v3 > 0 )\n {\n v6 = (unsigned int)(v3 - 1);\n v7 = 1LL;\n v8 = 0;\n v9 = v6 + 2;\n do\n {\n if ( v4 == (_DWORD)v7 || (v10 = *__ctype_b_loc(), (v10[a1[v7]] & 0x100) != 0) && (v10[a1[v7 - 1]] & 0x100) == 0 )\n {\n v14 = v7 - v8;\n v15 = (void **)&v13[*a2];\n *v15 = malloc((int)v7 - v8 + 1);\n v11 = v8;\n v8 = v7;\n LODWORD(v15) = *a2;\n strncpy(v13[*a2], &a1[v11], v14)[v14] = 0;\n *a2 = (_DWORD)v15 + 1;\n }\n ++v7;\n }\n while ( v7 != v9 );\n }\n return v13;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char **sub_1750(const char *a1, int *a2) {\n int v3;\n int v4;\n char **v5;\n long long v6;\n long long v7;\n int v8;\n long long v9;\n const unsigned short *v10;\n long long v11;\n char **v13;\n int v14;\n void **v15;\n v3 = strlen(a1);\n v4 = v3;\n v5 = (char **)malloc(8LL * v3);\n *a2 = 0;\n v13 = v5;\n if (v3 > 0) {\n v6 = (unsigned int)(v3 - 1);\n v7 = 1LL;\n v8 = 0;\n v9 = v6 + 2;\n do {\n if (v4 == (uint32_t)v7 ||\n (v10 = *__ctype_b_loc(), (v10[a1[v7]] & 256) != 0) &&\n (v10[a1[v7 - 1]] & 256) == 0) {\n v14 = v7 - v8;\n v15 = (void **)&v13[*a2];\n *v15 = malloc((int)v7 - v8 + 1);\n v11 = v8;\n v8 = v7;\n LODWORD(v15) = *a2;\n strncpy(v13[*a2], &a1[v11], v14)[v14] = 0;\n *a2 = (uint32_t)v15 + 1;\n }\n ++v7;\n } while (v7 != v9);\n }\n return v13;\n}", + "ida_pseudo_norm": "char **func0(const char *a1, int *a2) {\n int v3;\n int v4;\n char **v5;\n long long v6;\n long long v7;\n int v8;\n long long v9;\n const unsigned short *v10;\n long long v11;\n char **v13;\n int v14;\n void **v15;\n v3 = strlen(a1);\n v4 = v3;\n v5 = (char **)malloc(8LL * v3);\n *a2 = 0;\n v13 = v5;\n if (v3 > 0) {\n v6 = (unsigned int)(v3 - 1);\n v7 = 1LL;\n v8 = 0;\n v9 = v6 + 2;\n do {\n if (v4 == (uint32_t)v7 ||\n (v10 = *__ctype_b_loc(), (v10[a1[v7]] & 256) != 0) &&\n (v10[a1[v7 - 1]] & 256) == 0) {\n v14 = v7 - v8;\n v15 = (void **)&v13[*a2];\n *v15 = malloc((int)v7 - v8 + 1);\n v11 = v8;\n v8 = v7;\n LODWORD(v15) = *a2;\n strncpy(v13[*a2], &a1[v11], v14)[v14] = 0;\n *a2 = (uint32_t)v15 + 1;\n }\n ++v7;\n } while (v7 != v9);\n }\n return v13;\n}" + }, + { + "index": 956, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char** func0(const char* text, int* count) {\n int n = strlen(text);\n char** result = malloc(n * sizeof(char*));\n *count = 0;\n int word_start = 0;\n for (int i = 1; i <= n; i++) {\n if (i == n || (isupper(text[i]) && !isupper(text[i - 1]))) {\n int word_length = i - word_start;\n result[*count] = malloc((word_length + 1) * sizeof(char));\n strncpy(result[*count], text + word_start, word_length);\n result[*count][word_length] = '\\0';\n (*count)++;\n word_start = i;\n }\n }\n return result;\n}", + "test": "int main() {\n\n int count1, count2, count3;\n\n char** result1 = func0(\"LearnToBuildAnythingWithGoogle\", &count1);\n\n char** result2 = func0(\"ApmlifyingTheBlack+DeveloperCommunity\", &count2);\n\n char** result3 = func0(\"UpdateInTheGoEcoSystem\", &count3);\n\n\n\n assert(count1 == 6);\n\n assert(strcmp(result1[0], \"Learn\") == 0);\n\n assert(strcmp(result1[1], \"To\") == 0);\n\n assert(strcmp(result1[2], \"Build\") == 0);\n\n assert(strcmp(result1[3], \"Anything\") == 0);\n\n assert(strcmp(result1[4], \"With\") == 0);\n\n assert(strcmp(result1[5], \"Google\") == 0);\n\n\n\n assert(count2 == 5);\n\n assert(strcmp(result2[0], \"Apmlifying\") == 0);\n\n assert(strcmp(result2[1], \"The\") == 0);\n\n assert(strcmp(result2[2], \"Black+\") == 0);\n\n assert(strcmp(result2[3], \"Developer\") == 0);\n\n assert(strcmp(result2[4], \"Community\") == 0);\n\n\n\n assert(count3 == 6);\n\n assert(strcmp(result3[0], \"Update\") == 0);\n\n assert(strcmp(result3[1], \"In\") == 0);\n\n assert(strcmp(result3[2], \"The\") == 0);\n\n assert(strcmp(result3[3], \"Go\") == 0);\n\n assert(strcmp(result3[4], \"Eco\") == 0);\n\n assert(strcmp(result3[5], \"System\") == 0);\n\n\n\n for (int i = 0; i < count1; i++) free(result1[i]);\n\n free(result1);\n\n for (int i = 0; i < count2; i++) free(result2[i]);\n\n free(result2);\n\n for (int i = 0; i < count3; i++) free(result3[i]);\n\n free(result3);\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\nmov %rdi,%r12\npush %rbp\nmov %rsi,%rbp\npush %rbx\nsub $0x28,%rsp\ncallq 10d0 \nmovslq %eax,%rdi\nmov %eax,0x4(%rsp)\nmov %rax,%rbx\nshl $0x3,%rdi\ncallq 1100 \nmovl $0x0,0x0(%rbp)\nmov %rax,%r14\ntest %ebx,%ebx\njle 1898 \nlea -0x1(%rbx),%eax\nmov $0x1,%r15d\nxor %ebx,%ebx\nadd $0x2,%rax\nmov %rax,0x8(%rsp)\nnopw %cs:0x0(%rax,%rax,1)\nmov %r15d,%r13d\ncmp %r15d,0x4(%rsp)\nje 182b \ncallq 1110 <__ctype_b_loc@plt>\nmovsbq (%r12,%r15,1),%rdx\nmov (%rax),%rax\ntestb $0x1,0x1(%rax,%rdx,2)\nje 1889 \nmovsbq -0x1(%r12,%r15,1),%rdx\ntestb $0x1,0x1(%rax,%rdx,2)\njne 1889 \nmov %r13d,%edx\nmovslq 0x0(%rbp),%rax\nsub %ebx,%edx\nlea 0x1(%rdx),%edi\nlea (%r14,%rax,8),%rsi\nmov %edx,0x10(%rsp)\nmovslq %edi,%rdi\nmov %rsi,0x18(%rsp)\ncallq 1100 \nmov 0x18(%rsp),%rsi\nmovslq 0x10(%rsp),%rdx\nmov %rax,(%rsi)\nmovslq 0x0(%rbp),%rax\nmovslq %ebx,%rsi\nmov %r13d,%ebx\nadd %r12,%rsi\nmov %rdx,0x10(%rsp)\nmov (%r14,%rax,8),%rdi\ncallq 10c0 \nmovslq 0x0(%rbp),%rax\nmov 0x10(%rsp),%rdx\nmov (%r14,%rax,8),%rax\nmovb $0x0,(%rax,%rdx,1)\naddl $0x1,0x0(%rbp)\nadd $0x1,%r15\ncmp %r15,0x8(%rsp)\njne 1800 \nadd $0x28,%rsp\nmov %r14,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12, rsi\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 28h\ncall _strlen\nmovsxd rdi, eax\nmov rbx, rax\nmov r15d, eax\nshl rdi, 3; size\ncall _malloc\nmov dword ptr [r12], 0\nmov [rsp+58h+var_50], rax\ntest ebx, ebx\njle loc_1849\nlea r13d, [rbx-1]\nmov r14d, 1\nxor ebx, ebx\nadd r13, 2\nnop dword ptr [rax+00h]\nloc_17A8:\ncmp r15d, r14d\njz short loc_17CF\ncall ___ctype_b_loc\nmovsx rdx, byte ptr [rbp+r14+0]\nmov rax, [rax]\ntest byte ptr [rax+rdx*2+1], 1\njz short loc_183C\nmovsx rdx, byte ptr [rbp+r14-1]\ntest byte ptr [rax+rdx*2+1], 1\njnz short loc_183C\nloc_17CF:\nmov edx, r14d\nmov rcx, [rsp+58h+var_50]\nmovsxd rax, dword ptr [r12]\nsub edx, ebx\nlea edi, [rdx+1]\nlea rsi, [rcx+rax*8]\nmov dword ptr [rsp+58h+var_48], edx\nmovsxd rdi, edi; size\nmov [rsp+58h+var_40], rsi\ncall _malloc\nmov rsi, [rsp+58h+var_40]\nmov rcx, [rsp+58h+var_50]\nmovsxd rdx, dword ptr [rsp+58h+var_48]; n\nmov [rsi], rax\nmovsxd rax, dword ptr [r12]\nmovsxd rsi, ebx\nmov ebx, r14d\nadd rsi, rbp; src\nmov [rsp+58h+var_48], rdx\nmov rdi, [rcx+rax*8]; dest\nmov dword ptr [rsp+58h+var_40], eax\ncall _strncpy\nmov r8d, dword ptr [rsp+58h+var_40]\nmov rdx, [rsp+58h+var_48]\nadd r8d, 1\nmov byte ptr [rax+rdx], 0\nmov [r12], r8d\nloc_183C:\nadd r14, 1\ncmp r13, r14\njnz loc_17A8\nloc_1849:\nmov rax, [rsp+58h+var_50]\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "char **__fastcall func0(const char *a1, int *a2)\n{\n int v3; // ebx\n int v4; // r15d\n char **v5; // rax\n __int64 v6; // r13\n __int64 v7; // r14\n int v8; // ebx\n __int64 v9; // r13\n const unsigned __int16 *v10; // rax\n __int64 v11; // rsi\n char **v13; // [rsp+8h] [rbp-50h]\n int v14; // [rsp+10h] [rbp-48h]\n void **v15; // [rsp+18h] [rbp-40h]\n\n v3 = strlen(a1);\n v4 = v3;\n v5 = (char **)malloc(8LL * v3);\n *a2 = 0;\n v13 = v5;\n if ( v3 > 0 )\n {\n v6 = (unsigned int)(v3 - 1);\n v7 = 1LL;\n v8 = 0;\n v9 = v6 + 2;\n do\n {\n if ( v4 == (_DWORD)v7 || (v10 = *__ctype_b_loc(), (v10[a1[v7]] & 0x100) != 0) && (v10[a1[v7 - 1]] & 0x100) == 0 )\n {\n v14 = v7 - v8;\n v15 = (void **)&v13[*a2];\n *v15 = malloc((int)v7 - v8 + 1);\n v11 = v8;\n v8 = v7;\n LODWORD(v15) = *a2;\n strncpy(v13[*a2], &a1[v11], v14)[v14] = 0;\n *a2 = (_DWORD)v15 + 1;\n }\n ++v7;\n }\n while ( v9 != v7 );\n }\n return v13;\n}", + "ida_strip_asm": "sub_1750:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12, rsi\npush rbp\nmov rbp, rdi\npush rbx\nsub rsp, 28h\ncall _strlen\nmovsxd rdi, eax\nmov rbx, rax\nmov r15d, eax\nshl rdi, 3; size\ncall _malloc\nmov dword ptr [r12], 0\nmov [rsp+58h+var_50], rax\ntest ebx, ebx\njle loc_1849\nlea r13d, [rbx-1]\nmov r14d, 1\nxor ebx, ebx\nadd r13, 2\nnop dword ptr [rax+00h]\nloc_17A8:\ncmp r15d, r14d\njz short loc_17CF\ncall ___ctype_b_loc\nmovsx rdx, byte ptr [rbp+r14+0]\nmov rax, [rax]\ntest byte ptr [rax+rdx*2+1], 1\njz short loc_183C\nmovsx rdx, byte ptr [rbp+r14-1]\ntest byte ptr [rax+rdx*2+1], 1\njnz short loc_183C\nloc_17CF:\nmov edx, r14d\nmov rcx, [rsp+58h+var_50]\nmovsxd rax, dword ptr [r12]\nsub edx, ebx\nlea edi, [rdx+1]\nlea rsi, [rcx+rax*8]\nmov dword ptr [rsp+58h+var_48], edx\nmovsxd rdi, edi; size\nmov [rsp+58h+var_40], rsi\ncall _malloc\nmov rsi, [rsp+58h+var_40]\nmov rcx, [rsp+58h+var_50]\nmovsxd rdx, dword ptr [rsp+58h+var_48]; n\nmov [rsi], rax\nmovsxd rax, dword ptr [r12]\nmovsxd rsi, ebx\nmov ebx, r14d\nadd rsi, rbp; src\nmov [rsp+58h+var_48], rdx\nmov rdi, [rcx+rax*8]; dest\nmov dword ptr [rsp+58h+var_40], eax\ncall _strncpy\nmov r8d, dword ptr [rsp+58h+var_40]\nmov rdx, [rsp+58h+var_48]\nadd r8d, 1\nmov byte ptr [rax+rdx], 0\nmov [r12], r8d\nloc_183C:\nadd r14, 1\ncmp r13, r14\njnz loc_17A8\nloc_1849:\nmov rax, [rsp+58h+var_50]\nadd rsp, 28h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "char **__fastcall sub_1750(const char *a1, int *a2)\n{\n int v3; // ebx\n int v4; // r15d\n char **v5; // rax\n __int64 v6; // r13\n __int64 v7; // r14\n int v8; // ebx\n __int64 v9; // r13\n const unsigned __int16 *v10; // rax\n __int64 v11; // rsi\n char **v13; // [rsp+8h] [rbp-50h]\n int v14; // [rsp+10h] [rbp-48h]\n void **v15; // [rsp+18h] [rbp-40h]\n\n v3 = strlen(a1);\n v4 = v3;\n v5 = (char **)malloc(8LL * v3);\n *a2 = 0;\n v13 = v5;\n if ( v3 > 0 )\n {\n v6 = (unsigned int)(v3 - 1);\n v7 = 1LL;\n v8 = 0;\n v9 = v6 + 2;\n do\n {\n if ( v4 == (_DWORD)v7 || (v10 = *__ctype_b_loc(), (v10[a1[v7]] & 0x100) != 0) && (v10[a1[v7 - 1]] & 0x100) == 0 )\n {\n v14 = v7 - v8;\n v15 = (void **)&v13[*a2];\n *v15 = malloc((int)v7 - v8 + 1);\n v11 = v8;\n v8 = v7;\n LODWORD(v15) = *a2;\n strncpy(v13[*a2], &a1[v11], v14)[v14] = 0;\n *a2 = (_DWORD)v15 + 1;\n }\n ++v7;\n }\n while ( v9 != v7 );\n }\n return v13;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char **sub_1750(const char *a1, int *a2) {\n int v3;\n int v4;\n char **v5;\n long long v6;\n long long v7;\n int v8;\n long long v9;\n const unsigned short *v10;\n long long v11;\n char **v13;\n int v14;\n void **v15;\n v3 = strlen(a1);\n v4 = v3;\n v5 = (char **)malloc(8LL * v3);\n *a2 = 0;\n v13 = v5;\n if (v3 > 0) {\n v6 = (unsigned int)(v3 - 1);\n v7 = 1LL;\n v8 = 0;\n v9 = v6 + 2;\n do {\n if (v4 == (uint32_t)v7 ||\n (v10 = *__ctype_b_loc(), (v10[a1[v7]] & 256) != 0) &&\n (v10[a1[v7 - 1]] & 256) == 0) {\n v14 = v7 - v8;\n v15 = (void **)&v13[*a2];\n *v15 = malloc((int)v7 - v8 + 1);\n v11 = v8;\n v8 = v7;\n LODWORD(v15) = *a2;\n strncpy(v13[*a2], &a1[v11], v14)[v14] = 0;\n *a2 = (uint32_t)v15 + 1;\n }\n ++v7;\n } while (v9 != v7);\n }\n return v13;\n}", + "ida_pseudo_norm": "char **func0(const char *a1, int *a2) {\n int v3;\n int v4;\n char **v5;\n long long v6;\n long long v7;\n int v8;\n long long v9;\n const unsigned short *v10;\n long long v11;\n char **v13;\n int v14;\n void **v15;\n v3 = strlen(a1);\n v4 = v3;\n v5 = (char **)malloc(8LL * v3);\n *a2 = 0;\n v13 = v5;\n if (v3 > 0) {\n v6 = (unsigned int)(v3 - 1);\n v7 = 1LL;\n v8 = 0;\n v9 = v6 + 2;\n do {\n if (v4 == (uint32_t)v7 ||\n (v10 = *__ctype_b_loc(), (v10[a1[v7]] & 256) != 0) &&\n (v10[a1[v7 - 1]] & 256) == 0) {\n v14 = v7 - v8;\n v15 = (void **)&v13[*a2];\n *v15 = malloc((int)v7 - v8 + 1);\n v11 = v8;\n v8 = v7;\n LODWORD(v15) = *a2;\n strncpy(v13[*a2], &a1[v11], v14)[v14] = 0;\n *a2 = (uint32_t)v15 + 1;\n }\n ++v7;\n } while (v9 != v7);\n }\n return v13;\n}" + }, + { + "index": 957, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) { return (int)(log2(n & -n) + 1); }", + "test": "int main() {\n\n assert(func0(12) == 3);\n\n assert(func0(18) == 2);\n\n assert(func0(16) == 5);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x10,%rsp\nmov %edi,-0x4(%rbp)\nmov -0x4(%rbp),%eax\nneg %eax\nand -0x4(%rbp),%eax\ncvtsi2sd %eax,%xmm0\ncallq 1060 \nmovsd 0xee7(%rip),%xmm1\naddsd %xmm1,%xmm0\ncvttsd2si %xmm0,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+var_4], edi\nmov eax, [rbp+var_4]\nneg eax\nand eax, [rbp+var_4]\npxor xmm2, xmm2\ncvtsi2sd xmm2, eax\nmovq rax, xmm2\nmovq xmm0, rax; x\ncall _log2\nmovsd xmm1, cs:qword_2060\naddsd xmm0, xmm1\ncvttsd2si eax, xmm0\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n return (unsigned int)(int)(log2((double)(a1 & -a1)) + 1.0);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 10h\nmov [rbp+var_4], edi\nmov eax, [rbp+var_4]\nneg eax\nand eax, [rbp+var_4]\npxor xmm2, xmm2\ncvtsi2sd xmm2, eax\nmovq rax, xmm2\nmovq xmm0, rax; x\ncall _log2\nmovsd xmm1, cs:qword_2060\naddsd xmm0, xmm1\ncvttsd2si eax, xmm0\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n return (unsigned int)(int)(log2((double)(a1 & -a1)) + 1.0);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n return (unsigned int)(int)(log2((double)(a1 & -a1)) + 1.0);\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n return (unsigned int)(int)(log2((double)(a1 & -a1)) + 1.0);\n}" + }, + { + "index": 957, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) { return (int)(log2(n & -n) + 1); }", + "test": "int main() {\n\n assert(func0(12) == 3);\n\n assert(func0(18) == 2);\n\n assert(func0(16) == 5);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x8,%rsp\nmov %edi,%eax\nneg %edi\nand %eax,%edi\npxor %xmm0,%xmm0\ncvtsi2sd %edi,%xmm0\ncallq 1060 \naddsd 0xeec(%rip),%xmm0\ncvttsd2si %xmm0,%eax\nadd $0x8,%rsp\nretq\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\nmov eax, edi\nneg eax\nand eax, edi\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax; x\ncall _log2\naddsd xmm0, cs:qword_2060\ncvttsd2si eax, xmm0\nadd rsp, 8\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n return (unsigned int)(int)(log2((double)(a1 & -a1)) + 1.0);\n}", + "ida_strip_asm": "sub_1169:\nendbr64\nsub rsp, 8\nmov eax, edi\nneg eax\nand eax, edi\npxor xmm0, xmm0\ncvtsi2sd xmm0, eax; x\ncall _log2\naddsd xmm0, cs:qword_2060\ncvttsd2si eax, xmm0\nadd rsp, 8\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(int a1)\n{\n return (unsigned int)(int)(log2((double)(a1 & -a1)) + 1.0);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(int a1) {\n return (unsigned int)(int)(log2((double)(a1 & -a1)) + 1.0);\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n return (unsigned int)(int)(log2((double)(a1 & -a1)) + 1.0);\n}" + }, + { + "index": 957, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) { return (int)(log2(n & -n) + 1); }", + "test": "int main() {\n\n assert(func0(12) == 3);\n\n assert(func0(18) == 2);\n\n assert(func0(16) == 5);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nmov %edi,%r8d\nneg %edi\npxor %xmm0,%xmm0\nsub $0x8,%rsp\nand %r8d,%edi\ncvtsi2sd %edi,%xmm0\ncallq 1050 \naddsd 0xe83(%rip),%xmm0\nadd $0x8,%rsp\ncvttsd2si %xmm0,%eax\nretq\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\nmov eax, edi\npxor xmm0, xmm0\nsub rsp, 8\nneg eax\nand eax, edi\ncvtsi2sd xmm0, eax; x\ncall _log2\naddsd xmm0, cs:qword_2008\nadd rsp, 8\ncvttsd2si eax, xmm0\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n return (unsigned int)(int)(log2((double)(a1 & -a1)) + 1.0);\n}", + "ida_strip_asm": "sub_1160:\nendbr64\nmov eax, edi\npxor xmm0, xmm0\nsub rsp, 8\nneg eax\nand eax, edi\ncvtsi2sd xmm0, eax; x\ncall _log2\naddsd xmm0, cs:qword_2008\nadd rsp, 8\ncvttsd2si eax, xmm0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1160(int a1)\n{\n return (unsigned int)(int)(log2((double)(a1 & -a1)) + 1.0);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1160(int a1) {\n return (unsigned int)(int)(log2((double)(a1 & -a1)) + 1.0);\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n return (unsigned int)(int)(log2((double)(a1 & -a1)) + 1.0);\n}" + }, + { + "index": 957, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int n) { return (int)(log2(n & -n) + 1); }", + "test": "int main() {\n\n assert(func0(12) == 3);\n\n assert(func0(18) == 2);\n\n assert(func0(16) == 5);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nmov %edi,%r8d\nneg %edi\npxor %xmm0,%xmm0\nsub $0x8,%rsp\nand %r8d,%edi\ncvtsi2sd %edi,%xmm0\ncallq 1050 \naddsd 0xe83(%rip),%xmm0\nadd $0x8,%rsp\ncvttsd2si %xmm0,%eax\nretq\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\nmov eax, edi\npxor xmm0, xmm0\nsub rsp, 8\nneg eax\nand eax, edi\ncvtsi2sd xmm0, eax; x\ncall _log2\naddsd xmm0, cs:qword_2008\nadd rsp, 8\ncvttsd2si eax, xmm0\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n return (unsigned int)(int)(log2((double)(a1 & -a1)) + 1.0);\n}", + "ida_strip_asm": "sub_1160:\nendbr64\nmov eax, edi\npxor xmm0, xmm0\nsub rsp, 8\nneg eax\nand eax, edi\ncvtsi2sd xmm0, eax; x\ncall _log2\naddsd xmm0, cs:qword_2008\nadd rsp, 8\ncvttsd2si eax, xmm0\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1160(int a1)\n{\n return (unsigned int)(int)(log2((double)(a1 & -a1)) + 1.0);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1160(int a1) {\n return (unsigned int)(int)(log2((double)(a1 & -a1)) + 1.0);\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n return (unsigned int)(int)(log2((double)(a1 & -a1)) + 1.0);\n}" + }, + { + "index": 958, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(int num) {\n static char roman_num[100];\n int val[] = {1000, 900, 500, 400, 100, 90, 50, 40, 10, 9, 5, 4, 1};\n char* syb[] = {\"M\", \"CM\", \"D\", \"CD\", \"C\", \"XC\", \"L\",\n \"XL\", \"X\", \"IX\", \"V\", \"IV\", \"I\"};\n roman_num[0] = '\\0';\n int i = 0;\n while (num > 0) {\n while (num >= val[i]) {\n strcat(roman_num, syb[i]);\n num -= val[i];\n }\n i++;\n }\n return roman_num;\n}", + "test": "int main() {\n\n assert(strcmp(func0(1), \"I\") == 0);\n\n assert(strcmp(func0(50), \"L\") == 0);\n\n assert(strcmp(func0(4), \"IV\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0xd0,%rsp\nmov %edi,-0xc4(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovl $0x3e8,-0xb0(%rbp)\nmovl $0x384,-0xac(%rbp)\nmovl $0x1f4,-0xa8(%rbp)\nmovl $0x190,-0xa4(%rbp)\nmovl $0x64,-0xa0(%rbp)\nmovl $0x5a,-0x9c(%rbp)\nmovl $0x32,-0x98(%rbp)\nmovl $0x28,-0x94(%rbp)\nmovl $0xa,-0x90(%rbp)\nmovl $0x9,-0x8c(%rbp)\nmovl $0x5,-0x88(%rbp)\nmovl $0x4,-0x84(%rbp)\nmovl $0x1,-0x80(%rbp)\nlea 0xdb5(%rip),%rax\nmov %rax,-0x70(%rbp)\nlea 0xdac(%rip),%rax\nmov %rax,-0x68(%rbp)\nlea 0xda4(%rip),%rax\nmov %rax,-0x60(%rbp)\nlea 0xd9b(%rip),%rax\nmov %rax,-0x58(%rbp)\nlea 0xd93(%rip),%rax\nmov %rax,-0x50(%rbp)\nlea 0xd8a(%rip),%rax\nmov %rax,-0x48(%rbp)\nlea 0xd82(%rip),%rax\nmov %rax,-0x40(%rbp)\nlea 0xd79(%rip),%rax\nmov %rax,-0x38(%rbp)\nlea 0xd71(%rip),%rax\nmov %rax,-0x30(%rbp)\nlea 0xd68(%rip),%rax\nmov %rax,-0x28(%rbp)\nlea 0xd60(%rip),%rax\nmov %rax,-0x20(%rbp)\nlea 0xd57(%rip),%rax\nmov %rax,-0x18(%rbp)\nlea 0xd4f(%rip),%rax\nmov %rax,-0x10(%rbp)\nmovb $0x0,0x2d5e(%rip)\nmovl $0x0,-0xb4(%rbp)\njmp 133d \nmov -0xb4(%rbp),%eax\ncltq\nmov -0x70(%rbp,%rax,8),%rax\nmov %rax,%rsi\nlea 0x2d3b(%rip),%rdi\ncallq 10b0 \nmov -0xb4(%rbp),%eax\ncltq\nmov -0xb0(%rbp,%rax,4),%eax\nsub %eax,-0xc4(%rbp)\nmov -0xb4(%rbp),%eax\ncltq\nmov -0xb0(%rbp,%rax,4),%eax\ncmp %eax,-0xc4(%rbp)\njge 12ee \naddl $0x1,-0xb4(%rbp)\ncmpl $0x0,-0xc4(%rbp)\njg 131f \nlea 0x2cf3(%rip),%rax\nmov -0x8(%rbp),%rdx\nxor %fs:0x28,%rdx\nje 1361 \ncallq 1080 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0D0h\nmov [rbp+var_C4], edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_B0], 3E8h\nmov [rbp+var_AC], 384h\nmov [rbp+var_A8], 1F4h\nmov [rbp+var_A4], 190h\nmov [rbp+var_A0], 64h ; 'd'\nmov [rbp+var_9C], 5Ah ; 'Z'\nmov [rbp+var_98], 32h ; '2'\nmov [rbp+var_94], 28h ; '('\nmov [rbp+var_90], 0Ah\nmov [rbp+var_8C], 9\nmov [rbp+var_88], 5\nmov [rbp+var_84], 4\nmov [rbp+var_80], 1\nlea rax, unk_2008\nmov [rbp+src], rax\nlea rax, unk_200A\nmov [rbp+var_68], rax\nlea rax, unk_200D\nmov [rbp+var_60], rax\nlea rax, unk_200F\nmov [rbp+var_58], rax\nlea rax, unk_2012\nmov [rbp+var_50], rax\nlea rax, unk_2014\nmov [rbp+var_48], rax\nlea rax, asc_2017; \"L\"\nmov [rbp+var_40], rax\nlea rax, aXl; \"XL\"\nmov [rbp+var_38], rax\nlea rax, asc_201C; \"X\"\nmov [rbp+var_30], rax\nlea rax, aIx; \"IX\"\nmov [rbp+var_28], rax\nlea rax, aV; \"V\"\nmov [rbp+var_20], rax\nlea rax, aIv; \"IV\"\nmov [rbp+var_18], rax\nlea rax, s2; \"I\"\nmov [rbp+var_10], rax\nmov cs:roman_num_1, 0\nmov [rbp+var_B4], 0\njmp short loc_1340\nloc_12EE:\nmov eax, [rbp+var_B4]\ncdqe\nmov rax, [rbp+rax*8+src]\nmov rsi, rax; src\nlea rax, roman_num_1\nmov rdi, rax; dest\ncall _strcat\nmov eax, [rbp+var_B4]\ncdqe\nmov eax, [rbp+rax*4+var_B0]\nsub [rbp+var_C4], eax\nloc_1322:\nmov eax, [rbp+var_B4]\ncdqe\nmov eax, [rbp+rax*4+var_B0]\ncmp [rbp+var_C4], eax\njge short loc_12EE\nadd [rbp+var_B4], 1\nloc_1340:\ncmp [rbp+var_C4], 0\njg short loc_1322\nlea rax, roman_num_1\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1364\ncall ___stack_chk_fail\nlocret_1364:\nleave\nretn", + "ida_pseudo": "char *__fastcall func0(int a1)\n{\n int v3; // [rsp+1Ch] [rbp-B4h]\n _DWORD v4[16]; // [rsp+20h] [rbp-B0h]\n char *src[14]; // [rsp+60h] [rbp-70h]\n\n src[13] = (char *)__readfsqword(0x28u);\n v4[0] = 1000;\n v4[1] = 900;\n v4[2] = 500;\n v4[3] = 400;\n v4[4] = 100;\n v4[5] = 90;\n v4[6] = 50;\n v4[7] = 40;\n v4[8] = 10;\n v4[9] = 9;\n v4[10] = 5;\n v4[11] = 4;\n v4[12] = 1;\n src[0] = (char *)&unk_2008;\n src[1] = (char *)&unk_200A;\n src[2] = (char *)&unk_200D;\n src[3] = (char *)&unk_200F;\n src[4] = (char *)&unk_2012;\n src[5] = (char *)&unk_2014;\n src[6] = \"L\";\n src[7] = \"XL\";\n src[8] = \"X\";\n src[9] = \"IX\";\n src[10] = \"V\";\n src[11] = \"IV\";\n src[12] = \"I\";\n roman_num_1 = 0;\n v3 = 0;\n while ( a1 > 0 )\n {\n while ( a1 >= v4[v3] )\n {\n strcat(&roman_num_1, src[v3]);\n a1 -= v4[v3];\n }\n ++v3;\n }\n return &roman_num_1;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 0D0h\nmov [rbp+var_C4], edi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov [rbp+var_B0], 3E8h\nmov [rbp+var_AC], 384h\nmov [rbp+var_A8], 1F4h\nmov [rbp+var_A4], 190h\nmov [rbp+var_A0], 64h ; 'd'\nmov [rbp+var_9C], 5Ah ; 'Z'\nmov [rbp+var_98], 32h ; '2'\nmov [rbp+var_94], 28h ; '('\nmov [rbp+var_90], 0Ah\nmov [rbp+var_8C], 9\nmov [rbp+var_88], 5\nmov [rbp+var_84], 4\nmov [rbp+var_80], 1\nlea rax, unk_2008\nmov [rbp+src], rax\nlea rax, unk_200A\nmov [rbp+var_68], rax\nlea rax, unk_200D\nmov [rbp+var_60], rax\nlea rax, unk_200F\nmov [rbp+var_58], rax\nlea rax, unk_2012\nmov [rbp+var_50], rax\nlea rax, unk_2014\nmov [rbp+var_48], rax\nlea rax, asc_2017; \"L\"\nmov [rbp+var_40], rax\nlea rax, aXl; \"XL\"\nmov [rbp+var_38], rax\nlea rax, asc_201C; \"X\"\nmov [rbp+var_30], rax\nlea rax, aIx; \"IX\"\nmov [rbp+var_28], rax\nlea rax, aV; \"V\"\nmov [rbp+var_20], rax\nlea rax, aIv; \"IV\"\nmov [rbp+var_18], rax\nlea rax, s2; \"I\"\nmov [rbp+var_10], rax\nmov cs:dest, 0\nmov [rbp+var_B4], 0\njmp short loc_1340\nloc_12EE:\nmov eax, [rbp+var_B4]\ncdqe\nmov rax, [rbp+rax*8+src]\nmov rsi, rax; src\nlea rax, dest\nmov rdi, rax; dest\ncall _strcat\nmov eax, [rbp+var_B4]\ncdqe\nmov eax, [rbp+rax*4+var_B0]\nsub [rbp+var_C4], eax\nloc_1322:\nmov eax, [rbp+var_B4]\ncdqe\nmov eax, [rbp+rax*4+var_B0]\ncmp [rbp+var_C4], eax\njge short loc_12EE\nadd [rbp+var_B4], 1\nloc_1340:\ncmp [rbp+var_C4], 0\njg short loc_1322\nlea rax, dest\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1364\ncall ___stack_chk_fail\nlocret_1364:\nleave\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11A9(int a1)\n{\n int v3; // [rsp+1Ch] [rbp-B4h]\n _DWORD v4[16]; // [rsp+20h] [rbp-B0h]\n char *src[14]; // [rsp+60h] [rbp-70h]\n\n src[13] = (char *)__readfsqword(0x28u);\n v4[0] = 1000;\n v4[1] = 900;\n v4[2] = 500;\n v4[3] = 400;\n v4[4] = 100;\n v4[5] = 90;\n v4[6] = 50;\n v4[7] = 40;\n v4[8] = 10;\n v4[9] = 9;\n v4[10] = 5;\n v4[11] = 4;\n v4[12] = 1;\n src[0] = (char *)&unk_2008;\n src[1] = (char *)&unk_200A;\n src[2] = (char *)&unk_200D;\n src[3] = (char *)&unk_200F;\n src[4] = (char *)&unk_2012;\n src[5] = (char *)&unk_2014;\n src[6] = \"L\";\n src[7] = \"XL\";\n src[8] = \"X\";\n src[9] = \"IX\";\n src[10] = \"V\";\n src[11] = \"IV\";\n src[12] = \"I\";\n dest = 0;\n v3 = 0;\n while ( a1 > 0 )\n {\n while ( a1 >= v4[v3] )\n {\n strcat(&dest, src[v3]);\n a1 -= v4[v3];\n }\n ++v3;\n }\n return &dest;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11A9(int a1) {\n int v3;\n uint32_t v4[16];\n char *src[14];\n src[13] = (char *)__readfsqword(40u);\n v4[0] = 1000;\n v4[1] = 900;\n v4[2] = 500;\n v4[3] = 400;\n v4[4] = 100;\n v4[5] = 90;\n v4[6] = 50;\n v4[7] = 40;\n v4[8] = 10;\n v4[9] = 9;\n v4[10] = 5;\n v4[11] = 4;\n v4[12] = 1;\n src[0] = (char *)&unk_2008;\n src[1] = (char *)&unk_200A;\n src[2] = (char *)&unk_200D;\n src[3] = (char *)&unk_200F;\n src[4] = (char *)&unk_2012;\n src[5] = (char *)&unk_2014;\n src[6] = \"L\";\n src[7] = \"XL\";\n src[8] = \"X\";\n src[9] = \"IX\";\n src[10] = \"V\";\n src[11] = \"IV\";\n src[12] = \"I\";\n dest = 0;\n v3 = 0;\n while (a1 > 0) {\n while (a1 >= v4[v3]) {\n strcat(&dest, src[v3]);\n a1 -= v4[v3];\n }\n ++v3;\n }\n return &dest;\n}", + "ida_pseudo_norm": "char *func0(int a1) {\n int v3;\n uint32_t v4[16];\n char *src[14];\n src[13] = (char *)__readfsqword(40u);\n v4[0] = 1000;\n v4[1] = 900;\n v4[2] = 500;\n v4[3] = 400;\n v4[4] = 100;\n v4[5] = 90;\n v4[6] = 50;\n v4[7] = 40;\n v4[8] = 10;\n v4[9] = 9;\n v4[10] = 5;\n v4[11] = 4;\n v4[12] = 1;\n src[0] = (char *)&unk_2008;\n src[1] = (char *)&unk_200A;\n src[2] = (char *)&unk_200D;\n src[3] = (char *)&unk_200F;\n src[4] = (char *)&unk_2012;\n src[5] = (char *)&unk_2014;\n src[6] = \"L\";\n src[7] = \"XL\";\n src[8] = \"X\";\n src[9] = \"IX\";\n src[10] = \"V\";\n src[11] = \"IV\";\n src[12] = \"I\";\n roman_num_1 = 0;\n v3 = 0;\n while (a1 > 0) {\n while (a1 >= v4[v3]) {\n strcat(&roman_num_1, src[v3]);\n a1 -= v4[v3];\n }\n ++v3;\n }\n return &roman_num_1;\n}" + }, + { + "index": 958, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(int num) {\n static char roman_num[100];\n int val[] = {1000, 900, 500, 400, 100, 90, 50, 40, 10, 9, 5, 4, 1};\n char* syb[] = {\"M\", \"CM\", \"D\", \"CD\", \"C\", \"XC\", \"L\",\n \"XL\", \"X\", \"IX\", \"V\", \"IV\", \"I\"};\n roman_num[0] = '\\0';\n int i = 0;\n while (num > 0) {\n while (num >= val[i]) {\n strcat(roman_num, syb[i]);\n num -= val[i];\n }\n i++;\n }\n return roman_num;\n}", + "test": "int main() {\n\n assert(strcmp(func0(1), \"I\") == 0);\n\n assert(strcmp(func0(50), \"L\") == 0);\n\n assert(strcmp(func0(4), \"IV\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0xb0,%rsp\nmov %fs:0x28,%rax\nmov %rax,0xa8(%rsp)\nxor %eax,%eax\nmovl $0x3e8,(%rsp)\nmovl $0x384,0x4(%rsp)\nmovl $0x1f4,0x8(%rsp)\nmovl $0x190,0xc(%rsp)\nmovl $0x64,0x10(%rsp)\nmovl $0x5a,0x14(%rsp)\nmovl $0x32,0x18(%rsp)\nmovl $0x28,0x1c(%rsp)\nmovl $0xa,0x20(%rsp)\nmovl $0x9,0x24(%rsp)\nmovl $0x5,0x28(%rsp)\nmovl $0x4,0x2c(%rsp)\nmovl $0x1,0x30(%rsp)\nlea 0xde8(%rip),%rax\nmov %rax,0x40(%rsp)\nlea 0xddb(%rip),%rax\nmov %rax,0x48(%rsp)\nlea 0xdd3(%rip),%rax\nmov %rax,0x50(%rsp)\nlea 0xdc6(%rip),%rax\nmov %rax,0x58(%rsp)\nlea 0xdbe(%rip),%rax\nmov %rax,0x60(%rsp)\nlea 0xdb1(%rip),%rax\nmov %rax,0x68(%rsp)\nlea 0xda9(%rip),%rax\nmov %rax,0x70(%rsp)\nlea 0xd9c(%rip),%rax\nmov %rax,0x78(%rsp)\nlea 0xd94(%rip),%rax\nmov %rax,0x80(%rsp)\nlea 0xd84(%rip),%rax\nmov %rax,0x88(%rsp)\nlea 0xd79(%rip),%rax\nmov %rax,0x90(%rsp)\nlea 0xd69(%rip),%rax\nmov %rax,0x98(%rsp)\nlea 0xd5d(%rip),%rax\nmov %rax,0xa0(%rsp)\nmovb $0x0,0x2d78(%rip)\ntest %edi,%edi\njle 130b \nmov %edi,%ebx\nmov %rsp,%r14\nlea 0x40(%rsp),%r12\nlea 0x2d63(%rip),%r13\njmp 1302 \nmov $0x64,%edx\nmov (%r12),%rsi\nmov %r13,%rdi\ncallq 1070 <__strcat_chk@plt>\nsub %ebp,%ebx\ncmp %ebp,%ebx\njge 12df \nadd $0x4,%r14\nadd $0x8,%r12\ntest %ebx,%ebx\njle 130b \nmov (%r14),%ebp\ncmp %ebx,%ebp\njle 12df \njmp 12f6 \nmov 0xa8(%rsp),%rax\nxor %fs:0x28,%rax\njne 1335 \nlea 0x2d1b(%rip),%rax\nadd $0xb0,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\ncallq 1080 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 0B0h\nmov rax, fs:28h\nmov [rsp+0D8h+var_30], rax\nxor eax, eax\nmov [rsp+0D8h+var_D8], 3E8h\nmov [rsp+0D8h+var_D4], 384h\nmov [rsp+0D8h+var_D0], 1F4h\nmov [rsp+0D8h+var_CC], 190h\nmov [rsp+0D8h+var_C8], 64h ; 'd'\nmov [rsp+0D8h+var_C4], 5Ah ; 'Z'\nmov [rsp+0D8h+var_C0], 32h ; '2'\nmov [rsp+0D8h+var_BC], 28h ; '('\nmov [rsp+0D8h+var_B8], 0Ah\nmov [rsp+0D8h+var_B4], 9\nmov [rsp+0D8h+var_B0], 5\nmov [rsp+0D8h+var_AC], 4\nmov [rsp+0D8h+var_A8], 1\nlea rax, unk_2005\nmov [rsp+0D8h+var_98], rax\nlea rax, unk_2004\nmov [rsp+0D8h+var_90], rax\nlea rax, unk_2008\nmov [rsp+0D8h+var_88], rax\nlea rax, unk_2007\nmov [rsp+0D8h+var_80], rax\nlea rax, unk_200B\nmov [rsp+0D8h+var_78], rax\nlea rax, unk_200A\nmov [rsp+0D8h+var_70], rax\nlea rax, asc_200E; \"L\"\nmov [rsp+0D8h+var_68], rax\nlea rax, unk_200D\nmov [rsp+0D8h+var_60], rax\nlea rax, aIx+1; \"X\"\nmov [rsp+0D8h+var_58], rax\nlea rax, aIx; \"IX\"\nmov [rsp+0D8h+var_50], rax\nlea rax, aIv+1; \"V\"\nmov [rsp+0D8h+var_48], rax\nlea rax, aIv; \"IV\"\nmov [rsp+0D8h+var_40], rax\nlea rax, s2; \"I\"\nmov [rsp+0D8h+var_38], rax\nmov cs:roman_num_1, 0\ntest edi, edi\njle short loc_1327\nmov ebx, edi\nmov r14, rsp\nlea r12, [rsp+0D8h+var_98]\nlea r13, roman_num_1\nloc_12FD:\nmov ebp, [r14]\ncmp ebp, ebx\njg short loc_1351\nloc_1304:\nmov rsi, [r12]\nmov edx, 64h ; 'd'\nmov rdi, r13\ncall ___strcat_chk\nsub ebx, ebp\ncmp ebx, ebp\njge short loc_1304\nadd r14, 4\nadd r12, 8\ntest ebx, ebx\njg short loc_12FD\nloc_1327:\nmov rax, [rsp+0D8h+var_30]\nsub rax, fs:28h\njnz short loc_135B\nlea rax, roman_num_1\nadd rsp, 0B0h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1351:\nadd r14, 4\nadd r12, 8\njmp short loc_12FD\nloc_135B:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(int a1, __int64 a2, __int64 a3, __int64 a4, __int64 a5, __int64 a6)\n{\n int v6; // ebx\n __int64 *v7; // r14\n _QWORD *v8; // r12\n int v9; // ebp\n __int64 v11; // [rsp+0h] [rbp-D8h] BYREF\n __int64 v12; // [rsp+8h] [rbp-D0h]\n __int64 v13; // [rsp+10h] [rbp-C8h]\n __int64 v14; // [rsp+18h] [rbp-C0h]\n __int64 v15; // [rsp+20h] [rbp-B8h]\n __int64 v16; // [rsp+28h] [rbp-B0h]\n int v17; // [rsp+30h] [rbp-A8h]\n _QWORD v18[19]; // [rsp+40h] [rbp-98h] BYREF\n\n v18[13] = __readfsqword(0x28u);\n v11 = 0x384000003E8LL;\n v12 = 0x190000001F4LL;\n v13 = 0x5A00000064LL;\n v14 = 0x2800000032LL;\n v15 = 0x90000000ALL;\n v16 = 0x400000005LL;\n v17 = 1;\n v18[0] = &unk_2005;\n v18[1] = &unk_2004;\n v18[2] = &unk_2008;\n v18[3] = &unk_2007;\n v18[4] = &unk_200B;\n v18[5] = &unk_200A;\n v18[6] = \"L\";\n v18[7] = &unk_200D;\n v18[8] = \"X\";\n v18[9] = \"IX\";\n v18[10] = \"V\";\n v18[11] = \"IV\";\n v18[12] = \"I\";\n roman_num_1 = 0;\n if ( a1 > 0 )\n {\n v6 = a1;\n v7 = &v11;\n v8 = v18;\n do\n {\n while ( 1 )\n {\n v9 = *(_DWORD *)v7;\n if ( *(_DWORD *)v7 <= v6 )\n break;\n v7 = (__int64 *)((char *)v7 + 4);\n ++v8;\n }\n do\n {\n __strcat_chk(&roman_num_1, *v8, 100LL, a4, a5, a6, v11, v12, v13, v14, v15, v16, v17);\n v6 -= v9;\n }\n while ( v6 >= v9 );\n v7 = (__int64 *)((char *)v7 + 4);\n ++v8;\n }\n while ( v6 > 0 );\n }\n return &roman_num_1;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 0B0h\nmov rax, fs:28h\nmov [rsp+0D8h+var_30], rax\nxor eax, eax\nmov [rsp+0D8h+var_D8], 3E8h\nmov [rsp+0D8h+var_D4], 384h\nmov [rsp+0D8h+var_D0], 1F4h\nmov [rsp+0D8h+var_CC], 190h\nmov [rsp+0D8h+var_C8], 64h ; 'd'\nmov [rsp+0D8h+var_C4], 5Ah ; 'Z'\nmov [rsp+0D8h+var_C0], 32h ; '2'\nmov [rsp+0D8h+var_BC], 28h ; '('\nmov [rsp+0D8h+var_B8], 0Ah\nmov [rsp+0D8h+var_B4], 9\nmov [rsp+0D8h+var_B0], 5\nmov [rsp+0D8h+var_AC], 4\nmov [rsp+0D8h+var_A8], 1\nlea rax, unk_2005\nmov [rsp+0D8h+var_98], rax\nlea rax, unk_2004\nmov [rsp+0D8h+var_90], rax\nlea rax, unk_2008\nmov [rsp+0D8h+var_88], rax\nlea rax, unk_2007\nmov [rsp+0D8h+var_80], rax\nlea rax, unk_200B\nmov [rsp+0D8h+var_78], rax\nlea rax, unk_200A\nmov [rsp+0D8h+var_70], rax\nlea rax, asc_200E; \"L\"\nmov [rsp+0D8h+var_68], rax\nlea rax, unk_200D\nmov [rsp+0D8h+var_60], rax\nlea rax, aIx+1; \"X\"\nmov [rsp+0D8h+var_58], rax\nlea rax, aIx; \"IX\"\nmov [rsp+0D8h+var_50], rax\nlea rax, aIv+1; \"V\"\nmov [rsp+0D8h+var_48], rax\nlea rax, aIv; \"IV\"\nmov [rsp+0D8h+var_40], rax\nlea rax, s2; \"I\"\nmov [rsp+0D8h+var_38], rax\nmov cs:byte_4040, 0\ntest edi, edi\njle short loc_1327\nmov ebx, edi\nmov r14, rsp\nlea r12, [rsp+0D8h+var_98]\nlea r13, byte_4040\nloc_12FD:\nmov ebp, [r14]\ncmp ebp, ebx\njg short loc_1351\nloc_1304:\nmov rsi, [r12]\nmov edx, 64h ; 'd'\nmov rdi, r13\ncall ___strcat_chk\nsub ebx, ebp\ncmp ebx, ebp\njge short loc_1304\nadd r14, 4\nadd r12, 8\ntest ebx, ebx\njg short loc_12FD\nloc_1327:\nmov rax, [rsp+0D8h+var_30]\nsub rax, fs:28h\njnz short loc_135B\nlea rax, byte_4040\nadd rsp, 0B0h\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_1351:\nadd r14, 4\nadd r12, 8\njmp short loc_12FD\nloc_135B:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_11A9(int a1, __int64 a2, __int64 a3, __int64 a4, __int64 a5, __int64 a6)\n{\n int v6; // ebx\n __int64 *v7; // r14\n _QWORD *v8; // r12\n int v9; // ebp\n __int64 v11; // [rsp+0h] [rbp-D8h] BYREF\n __int64 v12; // [rsp+8h] [rbp-D0h]\n __int64 v13; // [rsp+10h] [rbp-C8h]\n __int64 v14; // [rsp+18h] [rbp-C0h]\n __int64 v15; // [rsp+20h] [rbp-B8h]\n __int64 v16; // [rsp+28h] [rbp-B0h]\n int v17; // [rsp+30h] [rbp-A8h]\n _QWORD v18[19]; // [rsp+40h] [rbp-98h] BYREF\n\n v18[13] = __readfsqword(0x28u);\n v11 = 0x384000003E8LL;\n v12 = 0x190000001F4LL;\n v13 = 0x5A00000064LL;\n v14 = 0x2800000032LL;\n v15 = 0x90000000ALL;\n v16 = 0x400000005LL;\n v17 = 1;\n v18[0] = &unk_2005;\n v18[1] = &unk_2004;\n v18[2] = &unk_2008;\n v18[3] = &unk_2007;\n v18[4] = &unk_200B;\n v18[5] = &unk_200A;\n v18[6] = \"L\";\n v18[7] = &unk_200D;\n v18[8] = \"X\";\n v18[9] = \"IX\";\n v18[10] = \"V\";\n v18[11] = \"IV\";\n v18[12] = \"I\";\n byte_4040 = 0;\n if ( a1 > 0 )\n {\n v6 = a1;\n v7 = &v11;\n v8 = v18;\n do\n {\n while ( 1 )\n {\n v9 = *(_DWORD *)v7;\n if ( *(_DWORD *)v7 <= v6 )\n break;\n v7 = (__int64 *)((char *)v7 + 4);\n ++v8;\n }\n do\n {\n __strcat_chk(&byte_4040, *v8, 100LL, a4, a5, a6, v11, v12, v13, v14, v15, v16, v17);\n v6 -= v9;\n }\n while ( v6 >= v9 );\n v7 = (__int64 *)((char *)v7 + 4);\n ++v8;\n }\n while ( v6 > 0 );\n }\n return &byte_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11A9(int a1, long long a2, long long a3, long long a4, long long a5,\n long long a6) {\n int v6;\n long long *v7;\n uint64_t *v8;\n int v9;\n long long v11;\n long long v12;\n long long v13;\n long long v14;\n long long v15;\n long long v16;\n int v17;\n uint64_t v18[19];\n v18[13] = __readfsqword(40u);\n v11 = 3865470567400LL;\n v12 = 1717986918900LL;\n v13 = 386547056740LL;\n v14 = 171798691890LL;\n v15 = 38654705674LL;\n v16 = 17179869189LL;\n v17 = 1;\n v18[0] = &unk_2005;\n v18[1] = &unk_2004;\n v18[2] = &unk_2008;\n v18[3] = &unk_2007;\n v18[4] = &unk_200B;\n v18[5] = &unk_200A;\n v18[6] = \"L\";\n v18[7] = &unk_200D;\n v18[8] = \"X\";\n v18[9] = \"IX\";\n v18[10] = \"V\";\n v18[11] = \"IV\";\n v18[12] = \"I\";\n byte_4040 = 0;\n if (a1 > 0) {\n v6 = a1;\n v7 = &v11;\n v8 = v18;\n do {\n while (1) {\n v9 = *(uint32_t *)v7;\n if (*(uint32_t *)v7 <= v6) break;\n v7 = (long long *)((char *)v7 + 4);\n ++v8;\n }\n do {\n __strcat_chk(&byte_4040, *v8, 100LL, a4, a5, a6, v11, v12, v13, v14,\n v15, v16, v17);\n v6 -= v9;\n } while (v6 >= v9);\n v7 = (long long *)((char *)v7 + 4);\n ++v8;\n } while (v6 > 0);\n }\n return &byte_4040;\n}", + "ida_pseudo_norm": "char *func0(int a1, long long a2, long long a3, long long a4, long long a5,\n long long a6) {\n int v6;\n long long *v7;\n uint64_t *v8;\n int v9;\n long long v11;\n long long v12;\n long long v13;\n long long v14;\n long long v15;\n long long v16;\n int v17;\n uint64_t v18[19];\n v18[13] = __readfsqword(40u);\n v11 = 3865470567400LL;\n v12 = 1717986918900LL;\n v13 = 386547056740LL;\n v14 = 171798691890LL;\n v15 = 38654705674LL;\n v16 = 17179869189LL;\n v17 = 1;\n v18[0] = &unk_2005;\n v18[1] = &unk_2004;\n v18[2] = &unk_2008;\n v18[3] = &unk_2007;\n v18[4] = &unk_200B;\n v18[5] = &unk_200A;\n v18[6] = \"L\";\n v18[7] = &unk_200D;\n v18[8] = \"X\";\n v18[9] = \"IX\";\n v18[10] = \"V\";\n v18[11] = \"IV\";\n v18[12] = \"I\";\n roman_num_1 = 0;\n if (a1 > 0) {\n v6 = a1;\n v7 = &v11;\n v8 = v18;\n do {\n while (1) {\n v9 = *(uint32_t *)v7;\n if (*(uint32_t *)v7 <= v6) break;\n v7 = (long long *)((char *)v7 + 4);\n ++v8;\n }\n do {\n __strcat_chk(&roman_num_1, *v8, 100LL, a4, a5, a6, v11, v12, v13, v14,\n v15, v16, v17);\n v6 -= v9;\n } while (v6 >= v9);\n v7 = (long long *)((char *)v7 + 4);\n ++v8;\n } while (v6 > 0);\n }\n return &roman_num_1;\n}" + }, + { + "index": 958, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(int num) {\n static char roman_num[100];\n int val[] = {1000, 900, 500, 400, 100, 90, 50, 40, 10, 9, 5, 4, 1};\n char* syb[] = {\"M\", \"CM\", \"D\", \"CD\", \"C\", \"XC\", \"L\",\n \"XL\", \"X\", \"IX\", \"V\", \"IV\", \"I\"};\n roman_num[0] = '\\0';\n int i = 0;\n while (num > 0) {\n while (num >= val[i]) {\n strcat(roman_num, syb[i]);\n num -= val[i];\n }\n i++;\n }\n return roman_num;\n}", + "test": "int main() {\n\n assert(strcmp(func0(1), \"I\") == 0);\n\n assert(strcmp(func0(50), \"L\") == 0);\n\n assert(strcmp(func0(4), \"IV\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0xb0,%rsp\nmov %fs:0x28,%rax\nmov %rax,0xa8(%rsp)\nxor %eax,%eax\nmovb $0x0,0x2dc3(%rip)\nmovabs $0x1f400000384,%rax\nmov %rax,0x4(%rsp)\nmovabs $0x6400000190,%rax\nmov %rax,0xc(%rsp)\nmovabs $0x320000005a,%rax\nmov %rax,0x14(%rsp)\nmovabs $0xa00000028,%rax\nmov %rax,0x1c(%rsp)\nmovabs $0x500000009,%rax\nmov %rax,0x24(%rsp)\nmovabs $0x100000004,%rax\nmov %rax,0x2c(%rsp)\nlea 0xd27(%rip),%rax\nmov %rax,0x40(%rsp)\nlea 0xd1a(%rip),%rax\nmov %rax,0x48(%rsp)\nlea 0xd12(%rip),%rax\nmov %rax,0x50(%rsp)\nlea 0xd05(%rip),%rax\nmov %rax,0x58(%rsp)\nlea 0xcfd(%rip),%rax\nmov %rax,0x60(%rsp)\nlea 0xcf0(%rip),%rax\nmov %rax,0x68(%rsp)\nlea 0xce8(%rip),%rax\nmov %rax,0x70(%rsp)\nlea 0xcdb(%rip),%rax\nmov %rax,0x78(%rsp)\nlea 0xcd3(%rip),%rax\nmov %rax,0x80(%rsp)\nlea 0xcc3(%rip),%rax\nmov %rax,0x88(%rsp)\nlea 0xcb8(%rip),%rax\nmov %rax,0x90(%rsp)\nlea 0xca8(%rip),%rax\nmov %rax,0x98(%rsp)\nlea 0xc9c(%rip),%rax\nmov %rax,0xa0(%rsp)\ntest %edi,%edi\njle 13e0 \nmov %edi,%ebx\nmov $0x3e8,%ebp\nlea 0x40(%rsp),%r14\nxor %r13d,%r13d\nlea 0x2ca4(%rip),%rcx\ncmp %ebx,%ebp\njg 13d1 \nmov (%r14,%r13,2),%r12\nnopl 0x0(%rax)\nmov %rcx,%rdi\nmov $0x64,%edx\nmov %r12,%rsi\nsub %ebp,%ebx\ncallq 1070 <__strcat_chk@plt>\nmov %rax,%rcx\ncmp %ebp,%ebx\njge 13a8 \nadd $0x4,%r13\ntest %ebx,%ebx\nje 13e0 \nmov (%rsp,%r13,1),%ebp\ncmp %ebx,%ebp\njle 13a0 \nadd $0x4,%r13\njmp 13c9 \nnopw 0x0(%rax,%rax,1)\nmov 0xa8(%rsp),%rax\nxor %fs:0x28,%rax\njne 140a \nadd $0xb0,%rsp\nlea 0x2c3f(%rip),%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\nretq\ncallq 1080 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush r15\nlea rdx, unk_2005\nlea rsi, unk_2008\npush r14\nlea rcx, roman_num_1\npush r13\npush r12\npush rbp\npush rbx\nmov ebx, edi\nlea rdi, unk_2011\nsub rsp, 0B8h\nmovdqa xmm0, cs:xmmword_20A0\nmov rax, fs:28h\nmov [rsp+0E8h+var_40], rax\nxor eax, eax\nlea rax, unk_2004\nmov cs:roman_num_1, 0\nmovaps [rsp+0E8h+var_E8], xmm0\nmovdqa xmm0, cs:xmmword_20B0\nmovq xmm1, rax\nlea rax, unk_2007\nmovq xmm2, rax\nlea rax, unk_200A\nmov [rsp+0E8h+var_B8], 1\nmovaps [rsp+0E8h+var_D8], xmm0\nmovdqa xmm0, cs:xmmword_20C0\nmovq xmm3, rax\nlea rax, unk_200D\nmovq xmm4, rax\nlea rax, unk_2010\nmovaps [rsp+0E8h+var_C8], xmm0\nmovq xmm0, rdx\nmovq xmm5, rax\nlea rdx, unk_200B\npunpcklqdq xmm0, xmm1\nlea rax, unk_2013\nmovaps [rsp+0E8h+var_A8], xmm0\nmovq xmm0, rsi\nmovq xmm6, rax\nlea rsi, unk_200E\npunpcklqdq xmm0, xmm2\nlea rax, unk_2016\nmovaps [rsp+0E8h+var_98], xmm0\nmovq xmm0, rdx\nlea rdx, unk_2014\npunpcklqdq xmm0, xmm3\nmov [rsp+0E8h+var_48], rax\nmovaps [rsp+0E8h+var_88], xmm0\nmovq xmm0, rsi\npunpcklqdq xmm0, xmm4\nmovaps [rsp+0E8h+var_78], xmm0\nmovq xmm0, rdi\npunpcklqdq xmm0, xmm5\nmovaps [rsp+0E8h+var_68], xmm0\nmovq xmm0, rdx\npunpcklqdq xmm0, xmm6\nmovaps [rsp+0E8h+var_58], xmm0\ntest ebx, ebx\njle short loc_13E1\nxor r13d, r13d\nlea r15, [rsp+0E8h+var_A8]\nlea rcx, roman_num_1\nmov r14, rsp\nnop word ptr [rax+rax+00000000h]\nloc_13B0:\nmov ebp, [r14+r13*4]\ncmp ebp, ebx\njg short loc_1410\nmov r12, [r15+r13*8]\nnop dword ptr [rax+00h]\nloc_13C0:\nmov rdi, rcx\nmov edx, 64h ; 'd'\nmov rsi, r12\nsub ebx, ebp\ncall ___strcat_chk\nmov rcx, rax\ncmp ebx, ebp\njge short loc_13C0\nadd r13, 1\ntest ebx, ebx\njnz short loc_13B0\nloc_13E1:\nmov rax, [rsp+0E8h+var_40]\nsub rax, fs:28h\njnz short loc_1416\nadd rsp, 0B8h\nmov rax, rcx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1410:\nadd r13, 1\njmp short loc_13B0\nloc_1416:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(int a1, __int64 a2, __int64 a3, __int64 a4, __int64 a5, __int64 a6)\n{\n char *v6; // rcx\n int v7; // ebx\n __int64 v8; // r13\n __int32 v9; // ebp\n __int64 v10; // r12\n __m128i si128; // [rsp+0h] [rbp-E8h]\n __m128i v13; // [rsp+10h] [rbp-D8h]\n __m128i v14; // [rsp+20h] [rbp-C8h]\n int v15; // [rsp+30h] [rbp-B8h]\n _OWORD v16[6]; // [rsp+40h] [rbp-A8h]\n void *v17; // [rsp+A0h] [rbp-48h]\n unsigned __int64 v18; // [rsp+A8h] [rbp-40h]\n\n v6 = &roman_num_1;\n v7 = a1;\n v18 = __readfsqword(0x28u);\n roman_num_1 = 0;\n si128 = _mm_load_si128((const __m128i *)&xmmword_20A0);\n v15 = 1;\n v13 = _mm_load_si128((const __m128i *)&xmmword_20B0);\n v14 = _mm_load_si128((const __m128i *)&xmmword_20C0);\n v16[0] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_2005, (__m128i)(unsigned __int64)&unk_2004);\n v16[1] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_2008, (__m128i)(unsigned __int64)&unk_2007);\n v17 = &unk_2016;\n v16[2] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_200B, (__m128i)(unsigned __int64)&unk_200A);\n v16[3] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_200E, (__m128i)(unsigned __int64)&unk_200D);\n v16[4] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_2011, (__m128i)(unsigned __int64)&unk_2010);\n v16[5] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_2014, (__m128i)(unsigned __int64)&unk_2013);\n if ( a1 > 0 )\n {\n v8 = 0LL;\n v6 = &roman_num_1;\n do\n {\n while ( 1 )\n {\n v9 = si128.m128i_i32[v8];\n if ( v9 <= v7 )\n break;\n ++v8;\n }\n v10 = *((_QWORD *)v16 + v8);\n do\n {\n v7 -= v9;\n v6 = (char *)__strcat_chk(\n v6,\n v10,\n 100LL,\n v6,\n a5,\n a6,\n si128.m128i_i64[0],\n si128.m128i_i64[1],\n v13.m128i_i64[0],\n v13.m128i_i64[1],\n v14.m128i_i64[0],\n v14.m128i_i64[1],\n v15);\n }\n while ( v7 >= v9 );\n ++v8;\n }\n while ( v7 );\n }\n return v6;\n}", + "ida_strip_asm": "sub_1250:\nendbr64\npush r15\nlea rdx, unk_2005\nlea rsi, unk_2008\npush r14\nlea rcx, byte_4040\npush r13\npush r12\npush rbp\npush rbx\nmov ebx, edi\nlea rdi, unk_2011\nsub rsp, 0B8h\nmovdqa xmm0, cs:xmmword_20A0\nmov rax, fs:28h\nmov [rsp+0E8h+var_40], rax\nxor eax, eax\nlea rax, unk_2004\nmov cs:byte_4040, 0\nmovaps [rsp+0E8h+var_E8], xmm0\nmovdqa xmm0, cs:xmmword_20B0\nmovq xmm1, rax\nlea rax, unk_2007\nmovq xmm2, rax\nlea rax, unk_200A\nmov [rsp+0E8h+var_B8], 1\nmovaps [rsp+0E8h+var_D8], xmm0\nmovdqa xmm0, cs:xmmword_20C0\nmovq xmm3, rax\nlea rax, unk_200D\nmovq xmm4, rax\nlea rax, unk_2010\nmovaps [rsp+0E8h+var_C8], xmm0\nmovq xmm0, rdx\nmovq xmm5, rax\nlea rdx, unk_200B\npunpcklqdq xmm0, xmm1\nlea rax, unk_2013\nmovaps [rsp+0E8h+var_A8], xmm0\nmovq xmm0, rsi\nmovq xmm6, rax\nlea rsi, unk_200E\npunpcklqdq xmm0, xmm2\nlea rax, unk_2016\nmovaps [rsp+0E8h+var_98], xmm0\nmovq xmm0, rdx\nlea rdx, unk_2014\npunpcklqdq xmm0, xmm3\nmov [rsp+0E8h+var_48], rax\nmovaps [rsp+0E8h+var_88], xmm0\nmovq xmm0, rsi\npunpcklqdq xmm0, xmm4\nmovaps [rsp+0E8h+var_78], xmm0\nmovq xmm0, rdi\npunpcklqdq xmm0, xmm5\nmovaps [rsp+0E8h+var_68], xmm0\nmovq xmm0, rdx\npunpcklqdq xmm0, xmm6\nmovaps [rsp+0E8h+var_58], xmm0\ntest ebx, ebx\njle short loc_13E1\nxor r13d, r13d\nlea r15, [rsp+0E8h+var_A8]\nlea rcx, byte_4040\nmov r14, rsp\nnop word ptr [rax+rax+00000000h]\nloc_13B0:\nmov ebp, [r14+r13*4]\ncmp ebp, ebx\njg short loc_1410\nmov r12, [r15+r13*8]\nnop dword ptr [rax+00h]\nloc_13C0:\nmov rdi, rcx\nmov edx, 64h ; 'd'\nmov rsi, r12\nsub ebx, ebp\ncall ___strcat_chk\nmov rcx, rax\ncmp ebx, ebp\njge short loc_13C0\nadd r13, 1\ntest ebx, ebx\njnz short loc_13B0\nloc_13E1:\nmov rax, [rsp+0E8h+var_40]\nsub rax, fs:28h\njnz short loc_1416\nadd rsp, 0B8h\nmov rax, rcx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1410:\nadd r13, 1\njmp short loc_13B0\nloc_1416:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_1250(int a1, __int64 a2, __int64 a3, __int64 a4, __int64 a5, __int64 a6)\n{\n char *v6; // rcx\n int v7; // ebx\n __int64 v8; // r13\n __int32 v9; // ebp\n __int64 v10; // r12\n __m128i si128; // [rsp+0h] [rbp-E8h]\n __m128i v13; // [rsp+10h] [rbp-D8h]\n __m128i v14; // [rsp+20h] [rbp-C8h]\n int v15; // [rsp+30h] [rbp-B8h]\n _OWORD v16[6]; // [rsp+40h] [rbp-A8h]\n void *v17; // [rsp+A0h] [rbp-48h]\n unsigned __int64 v18; // [rsp+A8h] [rbp-40h]\n\n v6 = &byte_4040;\n v7 = a1;\n v18 = __readfsqword(0x28u);\n byte_4040 = 0;\n si128 = _mm_load_si128((const __m128i *)&xmmword_20A0);\n v15 = 1;\n v13 = _mm_load_si128((const __m128i *)&xmmword_20B0);\n v14 = _mm_load_si128((const __m128i *)&xmmword_20C0);\n v16[0] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_2005, (__m128i)(unsigned __int64)&unk_2004);\n v16[1] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_2008, (__m128i)(unsigned __int64)&unk_2007);\n v17 = &unk_2016;\n v16[2] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_200B, (__m128i)(unsigned __int64)&unk_200A);\n v16[3] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_200E, (__m128i)(unsigned __int64)&unk_200D);\n v16[4] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_2011, (__m128i)(unsigned __int64)&unk_2010);\n v16[5] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_2014, (__m128i)(unsigned __int64)&unk_2013);\n if ( a1 > 0 )\n {\n v8 = 0LL;\n v6 = &byte_4040;\n do\n {\n while ( 1 )\n {\n v9 = si128.m128i_i32[v8];\n if ( v9 <= v7 )\n break;\n ++v8;\n }\n v10 = *((_QWORD *)v16 + v8);\n do\n {\n v7 -= v9;\n v6 = (char *)__strcat_chk(\n v6,\n v10,\n 100LL,\n v6,\n a5,\n a6,\n si128.m128i_i64[0],\n si128.m128i_i64[1],\n v13.m128i_i64[0],\n v13.m128i_i64[1],\n v14.m128i_i64[0],\n v14.m128i_i64[1],\n v15);\n }\n while ( v7 >= v9 );\n ++v8;\n }\n while ( v7 );\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1250(int a1, long long a2, long long a3, long long a4, long long a5,\n long long a6) {\n char *v6;\n int v7;\n long long v8;\n int v9;\n long long v10;\n __m128i si128;\n __m128i v13;\n __m128i v14;\n int v15;\n long double v16[6];\n void *v17;\n unsigned long long v18;\n v6 = &byte_4040;\n v7 = a1;\n v18 = __readfsqword(40u);\n byte_4040 = 0;\n si128 = _mm_load_si128((const __m128i *)&xmmword_20A0);\n v15 = 1;\n v13 = _mm_load_si128((const __m128i *)&xmmword_20B0);\n v14 = _mm_load_si128((const __m128i *)&xmmword_20C0);\n v16[0] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_2005,\n (__m128i)(unsigned long long)&unk_2004);\n v16[1] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_2008,\n (__m128i)(unsigned long long)&unk_2007);\n v17 = &unk_2016;\n v16[2] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_200B,\n (__m128i)(unsigned long long)&unk_200A);\n v16[3] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_200E,\n (__m128i)(unsigned long long)&unk_200D);\n v16[4] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_2011,\n (__m128i)(unsigned long long)&unk_2010);\n v16[5] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_2014,\n (__m128i)(unsigned long long)&unk_2013);\n if (a1 > 0) {\n v8 = 0LL;\n v6 = &byte_4040;\n do {\n while (1) {\n v9 = si128.m128i_i32[v8];\n if (v9 <= v7) break;\n ++v8;\n }\n v10 = *((uint64_t *)v16 + v8);\n do {\n v7 -= v9;\n v6 = (char *)__strcat_chk(v6, v10, 100LL, v6, a5, a6,\n si128.m128i_i64[0], si128.m128i_i64[1],\n v13.m128i_i64[0], v13.m128i_i64[1],\n v14.m128i_i64[0], v14.m128i_i64[1], v15);\n } while (v7 >= v9);\n ++v8;\n } while (v7);\n }\n return v6;\n}", + "ida_pseudo_norm": "char *func0(int a1, long long a2, long long a3, long long a4, long long a5,\n long long a6) {\n char *v6;\n int v7;\n long long v8;\n int v9;\n long long v10;\n __m128i si128;\n __m128i v13;\n __m128i v14;\n int v15;\n long double v16[6];\n void *v17;\n unsigned long long v18;\n v6 = &roman_num_1;\n v7 = a1;\n v18 = __readfsqword(40u);\n roman_num_1 = 0;\n si128 = _mm_load_si128((const __m128i *)&xmmword_20A0);\n v15 = 1;\n v13 = _mm_load_si128((const __m128i *)&xmmword_20B0);\n v14 = _mm_load_si128((const __m128i *)&xmmword_20C0);\n v16[0] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_2005,\n (__m128i)(unsigned long long)&unk_2004);\n v16[1] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_2008,\n (__m128i)(unsigned long long)&unk_2007);\n v17 = &unk_2016;\n v16[2] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_200B,\n (__m128i)(unsigned long long)&unk_200A);\n v16[3] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_200E,\n (__m128i)(unsigned long long)&unk_200D);\n v16[4] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_2011,\n (__m128i)(unsigned long long)&unk_2010);\n v16[5] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_2014,\n (__m128i)(unsigned long long)&unk_2013);\n if (a1 > 0) {\n v8 = 0LL;\n v6 = &roman_num_1;\n do {\n while (1) {\n v9 = si128.m128i_i32[v8];\n if (v9 <= v7) break;\n ++v8;\n }\n v10 = *((uint64_t *)v16 + v8);\n do {\n v7 -= v9;\n v6 = (char *)__strcat_chk(v6, v10, 100LL, v6, a5, a6,\n si128.m128i_i64[0], si128.m128i_i64[1],\n v13.m128i_i64[0], v13.m128i_i64[1],\n v14.m128i_i64[0], v14.m128i_i64[1], v15);\n } while (v7 >= v9);\n ++v8;\n } while (v7);\n }\n return v6;\n}" + }, + { + "index": 958, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(int num) {\n static char roman_num[100];\n int val[] = {1000, 900, 500, 400, 100, 90, 50, 40, 10, 9, 5, 4, 1};\n char* syb[] = {\"M\", \"CM\", \"D\", \"CD\", \"C\", \"XC\", \"L\",\n \"XL\", \"X\", \"IX\", \"V\", \"IV\", \"I\"};\n roman_num[0] = '\\0';\n int i = 0;\n while (num > 0) {\n while (num >= val[i]) {\n strcat(roman_num, syb[i]);\n num -= val[i];\n }\n i++;\n }\n return roman_num;\n}", + "test": "int main() {\n\n assert(strcmp(func0(1), \"I\") == 0);\n\n assert(strcmp(func0(50), \"L\") == 0);\n\n assert(strcmp(func0(4), \"IV\") == 0);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\nlea 0xda8(%rip),%rdx\nlea 0xda4(%rip),%rsi\npush %r14\nlea 0x2dd3(%rip),%rcx\npush %r13\nxor %r13d,%r13d\npush %r12\npush %rbp\npush %rbx\nmov %edi,%ebx\nlea 0xd92(%rip),%rdi\nsub $0xb8,%rsp\nmovdqa 0xe32(%rip),%xmm0\nmov %fs:0x28,%rax\nmov %rax,0xa8(%rsp)\nxor %eax,%eax\nlea 0xd5c(%rip),%rax\nlea 0x40(%rsp),%r15\nmov %rsp,%r14\nmovaps %xmm0,(%rsp)\nmovdqa 0xe14(%rip),%xmm0\nmovq %rax,%xmm1\nlea 0xd3f(%rip),%rax\nmovq %rax,%xmm2\nlea 0xd36(%rip),%rax\nmovl $0x1,0x30(%rsp)\nmovaps %xmm0,0x10(%rsp)\nmovdqa 0xdf7(%rip),%xmm0\nmovq %rax,%xmm3\nlea 0xd18(%rip),%rax\nmovq %rax,%xmm4\nlea 0xd0f(%rip),%rax\nmovb $0x0,0x2d38(%rip)\nmovaps %xmm0,0x20(%rsp)\nmovq %rdx,%xmm0\nmovq %rax,%xmm5\nlea 0xced(%rip),%rdx\npunpcklqdq %xmm1,%xmm0\nlea 0xcea(%rip),%rax\nmovaps %xmm0,0x40(%rsp)\nmovq %rsi,%xmm0\nmovq %rax,%xmm6\nlea 0xccf(%rip),%rsi\npunpcklqdq %xmm2,%xmm0\nlea 0xccc(%rip),%rax\nmovaps %xmm0,0x50(%rsp)\nmovq %rdx,%xmm0\nlea 0xcb9(%rip),%rdx\npunpcklqdq %xmm3,%xmm0\nmov %rax,0xa0(%rsp)\nmovaps %xmm0,0x60(%rsp)\nmovq %rsi,%xmm0\npunpcklqdq %xmm4,%xmm0\nmovaps %xmm0,0x70(%rsp)\nmovq %rdi,%xmm0\npunpcklqdq %xmm5,%xmm0\nmovaps %xmm0,0x80(%rsp)\nmovq %rdx,%xmm0\npunpcklqdq %xmm6,%xmm0\nmovaps %xmm0,0x90(%rsp)\ntest %ebx,%ebx\njle 13d1 \nmov (%r14,%r13,4),%ebp\ncmp %ebx,%ebp\njg 1400 \nmov (%r15,%r13,8),%r12\nnopl 0x0(%rax)\nmov %rcx,%rdi\nmov $0x64,%edx\nmov %r12,%rsi\nsub %ebp,%ebx\ncallq 1070 <__strcat_chk@plt>\nmov %rax,%rcx\ncmp %ebp,%ebx\njge 13b0 \nadd $0x1,%r13\ntest %ebx,%ebx\njne 13a0 \nmov 0xa8(%rsp),%rax\nxor %fs:0x28,%rax\njne 1406 \nadd $0xb8,%rsp\nlea 0x2c4e(%rip),%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl (%rax)\nadd $0x1,%r13\njmp 13a0 \ncallq 1080 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\nlea rdx, unk_2005\nlea rsi, unk_2008\npush r14\nlea rcx, roman_num_1\npush r13\npush r12\npush rbp\npush rbx\nmov ebx, edi\nlea rdi, unk_2011\nsub rsp, 0B8h\nmovdqa xmm0, cs:xmmword_20A0\nmov rax, fs:28h\nmov [rsp+0E8h+var_40], rax\nxor eax, eax\nlea rax, unk_2004\nmov cs:roman_num_1, 0\nmovaps [rsp+0E8h+var_E8], xmm0\nmovdqa xmm0, cs:xmmword_20B0\nmovq xmm1, rax\nlea rax, unk_2007\nmovq xmm2, rax\nlea rax, unk_200A\nmov [rsp+0E8h+var_B8], 1\nmovaps [rsp+0E8h+var_D8], xmm0\nmovdqa xmm0, cs:xmmword_20C0\nmovq xmm3, rax\nlea rax, unk_200D\nmovq xmm4, rax\nlea rax, unk_2010\nmovaps [rsp+0E8h+var_C8], xmm0\nmovq xmm0, rdx\nmovq xmm5, rax\nlea rdx, unk_200B\npunpcklqdq xmm0, xmm1\nlea rax, unk_2013\nmovaps [rsp+0E8h+var_A8], xmm0\nmovq xmm0, rsi\nmovq xmm6, rax\nlea rsi, unk_200E\npunpcklqdq xmm0, xmm2\nlea rax, unk_2016\nmovaps [rsp+0E8h+var_98], xmm0\nmovq xmm0, rdx\nlea rdx, unk_2014\npunpcklqdq xmm0, xmm3\nmov [rsp+0E8h+var_48], rax\nmovaps [rsp+0E8h+var_88], xmm0\nmovq xmm0, rsi\npunpcklqdq xmm0, xmm4\nmovaps [rsp+0E8h+var_78], xmm0\nmovq xmm0, rdi\npunpcklqdq xmm0, xmm5\nmovaps [rsp+0E8h+var_68], xmm0\nmovq xmm0, rdx\npunpcklqdq xmm0, xmm6\nmovaps [rsp+0E8h+var_58], xmm0\ntest ebx, ebx\njle short loc_13E1\nxor r13d, r13d\nlea r15, [rsp+0E8h+var_A8]\nlea rcx, roman_num_1\nmov r14, rsp\nnop word ptr [rax+rax+00000000h]\nloc_13B0:\nmov ebp, [r14+r13*4]\ncmp ebp, ebx\njg short loc_1410\nmov r12, [r15+r13*8]\nnop dword ptr [rax+00h]\nloc_13C0:\nmov rdi, rcx\nmov edx, 64h ; 'd'\nmov rsi, r12\nsub ebx, ebp\ncall ___strcat_chk\nmov rcx, rax\ncmp ebx, ebp\njge short loc_13C0\nadd r13, 1\ntest ebx, ebx\njnz short loc_13B0\nloc_13E1:\nmov rax, [rsp+0E8h+var_40]\nsub rax, fs:28h\njnz short loc_1416\nadd rsp, 0B8h\nmov rax, rcx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1410:\nadd r13, 1\njmp short loc_13B0\nloc_1416:\ncall ___stack_chk_fail", + "ida_pseudo": "char *__fastcall func0(int a1, __int64 a2, __int64 a3, __int64 a4, __int64 a5, __int64 a6)\n{\n char *v6; // rcx\n int v7; // ebx\n __int64 v8; // r13\n __int32 v9; // ebp\n __int64 v10; // r12\n __m128i si128; // [rsp+0h] [rbp-E8h]\n __m128i v13; // [rsp+10h] [rbp-D8h]\n __m128i v14; // [rsp+20h] [rbp-C8h]\n int v15; // [rsp+30h] [rbp-B8h]\n _OWORD v16[6]; // [rsp+40h] [rbp-A8h]\n void *v17; // [rsp+A0h] [rbp-48h]\n unsigned __int64 v18; // [rsp+A8h] [rbp-40h]\n\n v6 = &roman_num_1;\n v7 = a1;\n v18 = __readfsqword(0x28u);\n roman_num_1 = 0;\n si128 = _mm_load_si128((const __m128i *)&xmmword_20A0);\n v15 = 1;\n v13 = _mm_load_si128((const __m128i *)&xmmword_20B0);\n v14 = _mm_load_si128((const __m128i *)&xmmword_20C0);\n v16[0] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_2005, (__m128i)(unsigned __int64)&unk_2004);\n v16[1] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_2008, (__m128i)(unsigned __int64)&unk_2007);\n v17 = &unk_2016;\n v16[2] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_200B, (__m128i)(unsigned __int64)&unk_200A);\n v16[3] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_200E, (__m128i)(unsigned __int64)&unk_200D);\n v16[4] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_2011, (__m128i)(unsigned __int64)&unk_2010);\n v16[5] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_2014, (__m128i)(unsigned __int64)&unk_2013);\n if ( a1 > 0 )\n {\n v8 = 0LL;\n v6 = &roman_num_1;\n do\n {\n while ( 1 )\n {\n v9 = si128.m128i_i32[v8];\n if ( v9 <= v7 )\n break;\n ++v8;\n }\n v10 = *((_QWORD *)v16 + v8);\n do\n {\n v7 -= v9;\n v6 = (char *)__strcat_chk(\n v6,\n v10,\n 100LL,\n v6,\n a5,\n a6,\n si128.m128i_i64[0],\n si128.m128i_i64[1],\n v13.m128i_i64[0],\n v13.m128i_i64[1],\n v14.m128i_i64[0],\n v14.m128i_i64[1],\n v15);\n }\n while ( v7 >= v9 );\n ++v8;\n }\n while ( v7 );\n }\n return v6;\n}", + "ida_strip_asm": "sub_1250:\nendbr64\npush r15\nlea rdx, unk_2005\nlea rsi, unk_2008\npush r14\nlea rcx, byte_4040\npush r13\npush r12\npush rbp\npush rbx\nmov ebx, edi\nlea rdi, unk_2011\nsub rsp, 0B8h\nmovdqa xmm0, cs:xmmword_20A0\nmov rax, fs:28h\nmov [rsp+0E8h+var_40], rax\nxor eax, eax\nlea rax, unk_2004\nmov cs:byte_4040, 0\nmovaps [rsp+0E8h+var_E8], xmm0\nmovdqa xmm0, cs:xmmword_20B0\nmovq xmm1, rax\nlea rax, unk_2007\nmovq xmm2, rax\nlea rax, unk_200A\nmov [rsp+0E8h+var_B8], 1\nmovaps [rsp+0E8h+var_D8], xmm0\nmovdqa xmm0, cs:xmmword_20C0\nmovq xmm3, rax\nlea rax, unk_200D\nmovq xmm4, rax\nlea rax, unk_2010\nmovaps [rsp+0E8h+var_C8], xmm0\nmovq xmm0, rdx\nmovq xmm5, rax\nlea rdx, unk_200B\npunpcklqdq xmm0, xmm1\nlea rax, unk_2013\nmovaps [rsp+0E8h+var_A8], xmm0\nmovq xmm0, rsi\nmovq xmm6, rax\nlea rsi, unk_200E\npunpcklqdq xmm0, xmm2\nlea rax, unk_2016\nmovaps [rsp+0E8h+var_98], xmm0\nmovq xmm0, rdx\nlea rdx, unk_2014\npunpcklqdq xmm0, xmm3\nmov [rsp+0E8h+var_48], rax\nmovaps [rsp+0E8h+var_88], xmm0\nmovq xmm0, rsi\npunpcklqdq xmm0, xmm4\nmovaps [rsp+0E8h+var_78], xmm0\nmovq xmm0, rdi\npunpcklqdq xmm0, xmm5\nmovaps [rsp+0E8h+var_68], xmm0\nmovq xmm0, rdx\npunpcklqdq xmm0, xmm6\nmovaps [rsp+0E8h+var_58], xmm0\ntest ebx, ebx\njle short loc_13E1\nxor r13d, r13d\nlea r15, [rsp+0E8h+var_A8]\nlea rcx, byte_4040\nmov r14, rsp\nnop word ptr [rax+rax+00000000h]\nloc_13B0:\nmov ebp, [r14+r13*4]\ncmp ebp, ebx\njg short loc_1410\nmov r12, [r15+r13*8]\nnop dword ptr [rax+00h]\nloc_13C0:\nmov rdi, rcx\nmov edx, 64h ; 'd'\nmov rsi, r12\nsub ebx, ebp\ncall ___strcat_chk\nmov rcx, rax\ncmp ebx, ebp\njge short loc_13C0\nadd r13, 1\ntest ebx, ebx\njnz short loc_13B0\nloc_13E1:\nmov rax, [rsp+0E8h+var_40]\nsub rax, fs:28h\njnz short loc_1416\nadd rsp, 0B8h\nmov rax, rcx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1410:\nadd r13, 1\njmp short loc_13B0\nloc_1416:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "char *__fastcall sub_1250(int a1, __int64 a2, __int64 a3, __int64 a4, __int64 a5, __int64 a6)\n{\n char *v6; // rcx\n int v7; // ebx\n __int64 v8; // r13\n __int32 v9; // ebp\n __int64 v10; // r12\n __m128i si128; // [rsp+0h] [rbp-E8h]\n __m128i v13; // [rsp+10h] [rbp-D8h]\n __m128i v14; // [rsp+20h] [rbp-C8h]\n int v15; // [rsp+30h] [rbp-B8h]\n _OWORD v16[6]; // [rsp+40h] [rbp-A8h]\n void *v17; // [rsp+A0h] [rbp-48h]\n unsigned __int64 v18; // [rsp+A8h] [rbp-40h]\n\n v6 = &byte_4040;\n v7 = a1;\n v18 = __readfsqword(0x28u);\n byte_4040 = 0;\n si128 = _mm_load_si128((const __m128i *)&xmmword_20A0);\n v15 = 1;\n v13 = _mm_load_si128((const __m128i *)&xmmword_20B0);\n v14 = _mm_load_si128((const __m128i *)&xmmword_20C0);\n v16[0] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_2005, (__m128i)(unsigned __int64)&unk_2004);\n v16[1] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_2008, (__m128i)(unsigned __int64)&unk_2007);\n v17 = &unk_2016;\n v16[2] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_200B, (__m128i)(unsigned __int64)&unk_200A);\n v16[3] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_200E, (__m128i)(unsigned __int64)&unk_200D);\n v16[4] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_2011, (__m128i)(unsigned __int64)&unk_2010);\n v16[5] = _mm_unpacklo_epi64((__m128i)(unsigned __int64)&unk_2014, (__m128i)(unsigned __int64)&unk_2013);\n if ( a1 > 0 )\n {\n v8 = 0LL;\n v6 = &byte_4040;\n do\n {\n while ( 1 )\n {\n v9 = si128.m128i_i32[v8];\n if ( v9 <= v7 )\n break;\n ++v8;\n }\n v10 = *((_QWORD *)v16 + v8);\n do\n {\n v7 -= v9;\n v6 = (char *)__strcat_chk(\n v6,\n v10,\n 100LL,\n v6,\n a5,\n a6,\n si128.m128i_i64[0],\n si128.m128i_i64[1],\n v13.m128i_i64[0],\n v13.m128i_i64[1],\n v14.m128i_i64[0],\n v14.m128i_i64[1],\n v15);\n }\n while ( v7 >= v9 );\n ++v8;\n }\n while ( v7 );\n }\n return v6;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1250(int a1, long long a2, long long a3, long long a4, long long a5,\n long long a6) {\n char *v6;\n int v7;\n long long v8;\n int v9;\n long long v10;\n __m128i si128;\n __m128i v13;\n __m128i v14;\n int v15;\n long double v16[6];\n void *v17;\n unsigned long long v18;\n v6 = &byte_4040;\n v7 = a1;\n v18 = __readfsqword(40u);\n byte_4040 = 0;\n si128 = _mm_load_si128((const __m128i *)&xmmword_20A0);\n v15 = 1;\n v13 = _mm_load_si128((const __m128i *)&xmmword_20B0);\n v14 = _mm_load_si128((const __m128i *)&xmmword_20C0);\n v16[0] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_2005,\n (__m128i)(unsigned long long)&unk_2004);\n v16[1] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_2008,\n (__m128i)(unsigned long long)&unk_2007);\n v17 = &unk_2016;\n v16[2] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_200B,\n (__m128i)(unsigned long long)&unk_200A);\n v16[3] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_200E,\n (__m128i)(unsigned long long)&unk_200D);\n v16[4] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_2011,\n (__m128i)(unsigned long long)&unk_2010);\n v16[5] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_2014,\n (__m128i)(unsigned long long)&unk_2013);\n if (a1 > 0) {\n v8 = 0LL;\n v6 = &byte_4040;\n do {\n while (1) {\n v9 = si128.m128i_i32[v8];\n if (v9 <= v7) break;\n ++v8;\n }\n v10 = *((uint64_t *)v16 + v8);\n do {\n v7 -= v9;\n v6 = (char *)__strcat_chk(v6, v10, 100LL, v6, a5, a6,\n si128.m128i_i64[0], si128.m128i_i64[1],\n v13.m128i_i64[0], v13.m128i_i64[1],\n v14.m128i_i64[0], v14.m128i_i64[1], v15);\n } while (v7 >= v9);\n ++v8;\n } while (v7);\n }\n return v6;\n}", + "ida_pseudo_norm": "char *func0(int a1, long long a2, long long a3, long long a4, long long a5,\n long long a6) {\n char *v6;\n int v7;\n long long v8;\n int v9;\n long long v10;\n __m128i si128;\n __m128i v13;\n __m128i v14;\n int v15;\n long double v16[6];\n void *v17;\n unsigned long long v18;\n v6 = &roman_num_1;\n v7 = a1;\n v18 = __readfsqword(40u);\n roman_num_1 = 0;\n si128 = _mm_load_si128((const __m128i *)&xmmword_20A0);\n v15 = 1;\n v13 = _mm_load_si128((const __m128i *)&xmmword_20B0);\n v14 = _mm_load_si128((const __m128i *)&xmmword_20C0);\n v16[0] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_2005,\n (__m128i)(unsigned long long)&unk_2004);\n v16[1] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_2008,\n (__m128i)(unsigned long long)&unk_2007);\n v17 = &unk_2016;\n v16[2] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_200B,\n (__m128i)(unsigned long long)&unk_200A);\n v16[3] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_200E,\n (__m128i)(unsigned long long)&unk_200D);\n v16[4] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_2011,\n (__m128i)(unsigned long long)&unk_2010);\n v16[5] = _mm_unpacklo_epi64((__m128i)(unsigned long long)&unk_2014,\n (__m128i)(unsigned long long)&unk_2013);\n if (a1 > 0) {\n v8 = 0LL;\n v6 = &roman_num_1;\n do {\n while (1) {\n v9 = si128.m128i_i32[v8];\n if (v9 <= v7) break;\n ++v8;\n }\n v10 = *((uint64_t *)v16 + v8);\n do {\n v7 -= v9;\n v6 = (char *)__strcat_chk(v6, v10, 100LL, v6, a5, a6,\n si128.m128i_i64[0], si128.m128i_i64[1],\n v13.m128i_i64[0], v13.m128i_i64[1],\n v14.m128i_i64[0], v14.m128i_i64[1], v15);\n } while (v7 >= v9);\n ++v8;\n } while (v7);\n }\n return v6;\n}" + }, + { + "index": 959, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int lst[], int len) {\n int sum = 0;\n for (int i = 0; i < len; i++) {\n sum += lst[i];\n }\n return (double)sum / len;\n}", + "test": "int main() {\n\n int a[] = {15, 9, 55, 41, 35, 20, 62, 49};\n\n int b[] = {4, 5, 1, 2, 9, 7, 10, 8};\n\n int c[] = {1, 2, 3};\n\n\n\n assert(func0(a, 8) == 35.75);\n\n assert(func0(b, 8) == 5.75);\n\n assert(func0(c, 3) == 2);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmp 11a5 \nmov -0x4(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nadd %eax,-0x8(%rbp)\naddl $0x1,-0x4(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 1188 \ncvtsi2sdl -0x8(%rbp),%xmm0\ncvtsi2sdl -0x1c(%rbp),%xmm1\ndivsd %xmm1,%xmm0\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11A5\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_11A5:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_8]\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_1C]\ndivsd xmm0, xmm1\npop rbp\nretn", + "ida_pseudo": "double __fastcall func0(__int64 a1, int a2)\n{\n int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n v3 += *(_DWORD *)(4LL * i + a1);\n return (double)v3 / (double)a2;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp short loc_11A5\nloc_1188:\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nadd [rbp+var_8], eax\nadd [rbp+var_4], 1\nloc_11A5:\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_1C]\njl short loc_1188\npxor xmm0, xmm0\ncvtsi2sd xmm0, [rbp+var_8]\npxor xmm1, xmm1\ncvtsi2sd xmm1, [rbp+var_1C]\ndivsd xmm0, xmm1\npop rbp\nretn", + "ida_strip_pseudo": "double __fastcall sub_1169(__int64 a1, int a2)\n{\n int v3; // [rsp+14h] [rbp-8h]\n int i; // [rsp+18h] [rbp-4h]\n\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n v3 += *(_DWORD *)(4LL * i + a1);\n return (double)v3 / (double)a2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1169(long long a1, int a2) {\n int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) v3 += *(uint32_t *)(4LL * i + a1);\n return (double)v3 / (double)a2;\n}", + "ida_pseudo_norm": "double func0(long long a1, int a2) {\n int v3;\n int i;\n v3 = 0;\n for (i = 0; i < a2; ++i) v3 += *(uint32_t *)(4LL * i + a1);\n return (double)v3 / (double)a2;\n}" + }, + { + "index": 959, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "double func0(int lst[], int len) {\n int sum = 0;\n for (int i = 0; i < len; i++) {\n sum += lst[i];\n }\n return (double)sum / len;\n}", + "test": "int main() {\n\n int a[] = {15, 9, 55, 41, 35, 20, 62, 49};\n\n int b[] = {4, 5, 1, 2, 9, 7, 10, 8};\n\n int c[] = {1, 2, 3};\n\n\n\n assert(func0(a, 8) == 35.75);\n\n assert(func0(b, 8) == 5.75);\n\n assert(func0(c, 3) == 2);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\ntest %esi,%esi\njle 11a1 \nmov %rdi,%rax\nlea -0x1(%rsi),%edx\nlea 0x4(%rdi,%rdx,4),%rcx\nmov $0x0,%edx\nadd (%rax),%edx\nadd $0x4,%rax\ncmp %rcx,%rax\njne 1181 \npxor %xmm0,%xmm0\ncvtsi2sd %edx,%xmm0\npxor %xmm1,%xmm1\ncvtsi2sd %esi,%xmm1\ndivsd %xmm1,%xmm0\nretq\nmov $0x0,%edx\njmp 118c \n", + "ida_asm": "func0:\nendbr64\ntest esi, esi\njle short loc_11A0\nmov rax, rdi\nmovsxd rdx, esi\nlea rcx, [rdi+rdx*4]\nmov edx, 0\nloc_1180:\nadd edx, [rax]\nadd rax, 4\ncmp rax, rcx\njnz short loc_1180\nloc_118B:\npxor xmm0, xmm0\ncvtsi2sd xmm0, edx\npxor xmm1, xmm1\ncvtsi2sd xmm1, esi\ndivsd xmm0, xmm1\nretn\nloc_11A0:\nmov edx, 0\njmp short loc_118B", + "ida_pseudo": "double __fastcall func0(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n int v3; // edx\n\n if ( a2 <= 0 )\n {\n v3 = 0;\n }\n else\n {\n v2 = a1;\n v3 = 0;\n do\n v3 += *v2++;\n while ( v2 != &a1[a2] );\n }\n return (double)v3 / (double)a2;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\ntest esi, esi\njle short loc_11A0\nmov rax, rdi\nmovsxd rdx, esi\nlea rcx, [rdi+rdx*4]\nmov edx, 0\nloc_1180:\nadd edx, [rax]\nadd rax, 4\ncmp rax, rcx\njnz short loc_1180\nloc_118B:\npxor xmm0, xmm0\ncvtsi2sd xmm0, edx\npxor xmm1, xmm1\ncvtsi2sd xmm1, esi\ndivsd xmm0, xmm1\nretn\nloc_11A0:\nmov edx, 0\njmp short loc_118B", + "ida_strip_pseudo": "double __fastcall sub_1169(_DWORD *a1, int a2)\n{\n _DWORD *v2; // rax\n int v3; // edx\n\n if ( a2 <= 0 )\n {\n v3 = 0;\n }\n else\n {\n v2 = a1;\n v3 = 0;\n do\n v3 += *v2++;\n while ( v2 != &a1[a2] );\n }\n return (double)v3 / (double)a2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "double sub_1169(uint32_t *a1, int a2) {\n uint32_t *v2;\n int v3;\n if (a2 <= 0) {\n v3 = 0;\n } else {\n v2 = a1;\n v3 = 0;\n do\n v3 += *v2++;\n while (v2 != &a1[a2]);\n }\n return (double)v3 / (double)a2;\n}", + "ida_pseudo_norm": "double func0(uint32_t *a1, int a2) {\n uint32_t *v2;\n int v3;\n if (a2 <= 0) {\n v3 = 0;\n } else {\n v2 = a1;\n v3 = 0;\n do\n v3 += *v2++;\n while (v2 != &a1[a2]);\n }\n return (double)v3 / (double)a2;\n}" + }, + { + "index": 960, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n == 0) return 0;\n if (n == 1) return 1;\n return func0(n - 1) + func0(n - 2);\n}", + "test": "int main() {\n\n assert(func0(4) == 3);\n\n assert(func0(3) == 2);\n\n assert(func0(5) == 5);\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x18,%rsp\nmov %edi,-0x14(%rbp)\ncmpl $0x0,-0x14(%rbp)\njne 1166 \nmov $0x0,%eax\njmp 1191 \ncmpl $0x1,-0x14(%rbp)\njne 1173 \nmov $0x1,%eax\njmp 1191 \nmov -0x14(%rbp),%eax\nsub $0x1,%eax\nmov %eax,%edi\ncallq 1149 \nmov %eax,%ebx\nmov -0x14(%rbp),%eax\nsub $0x2,%eax\nmov %eax,%edi\ncallq 1149 \nadd %ebx,%eax\nadd $0x18,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 18h\nmov [rbp+var_14], edi\ncmp [rbp+var_14], 0\njnz short loc_1166\nmov eax, 0\njmp short loc_1191\nloc_1166:\ncmp [rbp+var_14], 1\njnz short loc_1173\nmov eax, 1\njmp short loc_1191\nloc_1173:\nmov eax, [rbp+var_14]\nsub eax, 1\nmov edi, eax\ncall func0\nmov ebx, eax\nmov eax, [rbp+var_14]\nsub eax, 2\nmov edi, eax\ncall func0\nadd eax, ebx\nloc_1191:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1)\n{\n int v2; // ebx\n\n if ( !a1 )\n return 0LL;\n if ( a1 == 1 )\n return 1LL;\n v2 = func0((unsigned int)(a1 - 1));\n return v2 + (unsigned int)func0((unsigned int)(a1 - 2));\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 18h\nmov [rbp+var_14], edi\ncmp [rbp+var_14], 0\njnz short loc_1166\nmov eax, 0\njmp short loc_1191\nloc_1166:\ncmp [rbp+var_14], 1\njnz short loc_1173\nmov eax, 1\njmp short loc_1191\nloc_1173:\nmov eax, [rbp+var_14]\nsub eax, 1\nmov edi, eax\ncall sub_1149\nmov ebx, eax\nmov eax, [rbp+var_14]\nsub eax, 2\nmov edi, eax\ncall sub_1149\nadd eax, ebx\nloc_1191:\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1)\n{\n int v2; // ebx\n\n if ( !a1 )\n return 0LL;\n if ( a1 == 1 )\n return 1LL;\n v2 = sub_1149((unsigned int)(a1 - 1));\n return v2 + (unsigned int)sub_1149((unsigned int)(a1 - 2));\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1) {\n int v2;\n if (!a1) return 0LL;\n if (a1 == 1) return 1LL;\n v2 = sub_1149((unsigned int)(a1 - 1));\n return v2 + (unsigned int)sub_1149((unsigned int)(a1 - 2));\n}", + "ida_pseudo_norm": "long long func0(int a1) {\n int v2;\n if (!a1) return 0LL;\n if (a1 == 1) return 1LL;\n v2 = func0((unsigned int)(a1 - 1));\n return v2 + (unsigned int)func0((unsigned int)(a1 - 2));\n}" + }, + { + "index": 960, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n == 0) return 0;\n if (n == 1) return 1;\n return func0(n - 1) + func0(n - 2);\n}", + "test": "int main() {\n\n assert(func0(4) == 3);\n\n assert(func0(3) == 2);\n\n assert(func0(5) == 5);\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %edi,%ebx\ntest %edi,%edi\nje 1174 \ncmp $0x1,%edi\nje 1174 \nlea -0x1(%rdi),%edi\ncallq 1149 \nmov %eax,%ebp\nlea -0x2(%rbx),%edi\ncallq 1149 \nlea 0x0(%rbp,%rax,1),%ebx\nmov %ebx,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov ebx, edi\ntest edi, edi\njz short loc_1174\ncmp edi, 1\njz short loc_1174\nlea edi, [rdi-1]\ncall func0\nmov ebp, eax\nlea edi, [rbx-2]\ncall func0\nlea ebx, [rbp+rax+0]\nloc_1174:\nmov eax, ebx\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1)\n{\n unsigned int v1; // ebx\n int v2; // ebp\n\n v1 = a1;\n if ( a1 >= 2 )\n {\n v2 = func0(a1 - 1);\n return v2 + (unsigned int)func0(a1 - 2);\n }\n return v1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\npush rbx\nsub rsp, 8\nmov ebx, edi\ntest edi, edi\njz short loc_1174\ncmp edi, 1\njz short loc_1174\nlea edi, [rdi-1]\ncall sub_1149\nmov ebp, eax\nlea edi, [rbx-2]\ncall sub_1149\nlea ebx, [rbp+rax+0]\nloc_1174:\nmov eax, ebx\nadd rsp, 8\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(unsigned int a1)\n{\n unsigned int v1; // ebx\n int v2; // ebp\n\n v1 = a1;\n if ( a1 >= 2 )\n {\n v2 = sub_1149(a1 - 1);\n return v2 + (unsigned int)sub_1149(a1 - 2);\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(unsigned int a1) {\n unsigned int v1;\n int v2;\n v1 = a1;\n if (a1 >= 2) {\n v2 = sub_1149(a1 - 1);\n return v2 + (unsigned int)sub_1149(a1 - 2);\n }\n return v1;\n}", + "ida_pseudo_norm": "long long func0(unsigned int a1) {\n unsigned int v1;\n int v2;\n v1 = a1;\n if (a1 >= 2) {\n v2 = func0(a1 - 1);\n return v2 + (unsigned int)func0(a1 - 2);\n }\n return v1;\n}" + }, + { + "index": 960, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n == 0) return 0;\n if (n == 1) return 1;\n return func0(n - 1) + func0(n - 2);\n}", + "test": "int main() {\n\n assert(func0(4) == 3);\n\n assert(func0(3) == 2);\n\n assert(func0(5) == 5);\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbx\nsub $0x8,%rsp\ntest %edi,%edi\nje 1230 \nmov %edi,%ebx\ncmp $0x1,%edi\nje 1240 \nxor %r12d,%r12d\nlea -0x1(%rbx),%edi\ncallq 11f0 \nadd %eax,%r12d\nsub $0x2,%ebx\nje 1222 \ncmp $0x1,%ebx\njne 1209 \nadd $0x1,%r12d\nadd $0x8,%rsp\nmov %r12d,%eax\npop %rbx\npop %r12\nretq\nnopl (%rax)\nxor %r12d,%r12d\nadd $0x8,%rsp\nmov %r12d,%eax\npop %rbx\npop %r12\nretq\nxchg %ax,%ax\nmov $0x1,%r12d\njmp 1222 \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12d, edi\npush rbp\npush rbx\nsub rsp, 58h\ntest edi, edi\njz loc_1429\ncmp edi, 1\njz loc_1429\nlea r15d, [rdi-1]\nxor r12d, r12d\nloc_121D:\ncmp r15d, 1\njz loc_1425\nlea r13d, [r15-1]\nxor r14d, r14d\nmov [rsp+88h+var_6C], r12d\nmov [rsp+88h+var_68], r13d\nmov ebp, r13d\nmov r12d, r14d\nloc_123E:\ncmp ebp, 1\njz loc_1403\nmov [rsp+88h+var_64], r15d\nlea ecx, [rbp-1]\nxor r14d, r14d\nmov [rsp+88h+var_60], ebp\nmov ebp, ecx\nloc_1258:\ncmp ebp, 1\njz loc_13E7\nmov [rsp+88h+var_58], r14d\nlea edi, [rbp-1]\nxor r15d, r15d\nmov r13d, ebp\nmov [rsp+88h+var_54], ecx\nmov [rsp+88h+var_5C], r12d\nmov r12d, edi\nloc_127B:\ncmp r12d, 1\njz loc_13C3\nlea r11d, [r12-1]\nxor r14d, r14d\nmov [rsp+88h+var_50], r15d\nmov [rsp+88h+var_78], r14d\nmov ebp, r11d\nmov [rsp+88h+var_4C], edi\nmov [rsp+88h+var_48], r11d\nmov [rsp+88h+var_44], r12d\nloc_12A8:\ncmp ebp, 1\njz loc_1396\nlea r12d, [rbp-1]\nmov [rsp+88h+var_3C], ebp\nxor r15d, r15d\nmov [rsp+88h+var_40], r12d\nmov r14d, r12d\nloc_12C4:\ncmp r14d, 1\njz loc_1377\nlea ebp, [r14-1]\nmov [rsp+88h+var_84], r13d\nxor ecx, ecx\nmov [rsp+88h+var_80], ebp\nmov ebx, ebp\nmov [rsp+88h+var_7C], r14d\nloc_12E4:\ncmp ebx, 1\njz short loc_1354\nlea ebp, [rbx-1]\nxor r13d, r13d\nmov r14d, ebp\nmov edx, ebp\nmov ebp, ecx\nmov ecx, ebx\nmov ebx, r14d\nloc_12FB:\nmov r14d, ebx\ncmp ebx, 1\njz short loc_1342\nmov [rsp+88h+var_74], ebx\nxor r12d, r12d\nmov ebx, edx\nloc_130C:\nlea edi, [r14-1]\nmov [rsp+88h+var_70], ecx\ncall func0\nmov ecx, [rsp+88h+var_70]\nadd r12d, eax\nsub r14d, 2\njz loc_1440\ncmp r14d, 1\njnz short loc_130C\nmov edx, ebx\nmov ebx, [rsp+88h+var_74]\nadd r12d, 1\nloc_133A:\nadd r13d, r12d\nsub ebx, 2\njnz short loc_12FB\nloc_1342:\nmov ebx, ecx\nlea esi, [r13+1]\nmov ecx, ebp\nadd ecx, esi\nsub ebx, 2\ncmp edx, 1\njnz short loc_12E4\nloc_1354:\nmov r14d, [rsp+88h+var_7C]\nmov ebx, ecx\nmov ebp, [rsp+88h+var_80]\nadd ebx, 1\nmov r13d, [rsp+88h+var_84]\nadd r15d, ebx\nsub r14d, 2\ncmp ebp, 1\njnz loc_12C4\nloc_1377:\nmov ebp, [rsp+88h+var_3C]\nmov r12d, [rsp+88h+var_40]\nadd r15d, 1\nadd [rsp+88h+var_78], r15d\nsub ebp, 2\ncmp r12d, 1\njnz loc_12A8\nloc_1396:\nmov r14d, [rsp+88h+var_78]\nmov r15d, [rsp+88h+var_50]\nmov r12d, [rsp+88h+var_44]\nmov r11d, [rsp+88h+var_48]\nadd r14d, 1\nmov edi, [rsp+88h+var_4C]\nadd r15d, r14d\nsub r12d, 2\ncmp r11d, 1\njnz loc_127B\nloc_13C3:\nmov r14d, [rsp+88h+var_58]\nmov ebp, r13d\nadd r15d, 1\nmov ecx, [rsp+88h+var_54]\nmov r12d, [rsp+88h+var_5C]\nsub ebp, 2\nadd r14d, r15d\ncmp edi, 1\njnz loc_1258\nloc_13E7:\nmov ebp, [rsp+88h+var_60]\nadd r14d, 1\nmov r15d, [rsp+88h+var_64]\nadd r12d, r14d\nsub ebp, 2\ncmp ecx, 1\njnz loc_123E\nloc_1403:\nmov r14d, r12d\nmov r13d, [rsp+88h+var_68]\nmov r12d, [rsp+88h+var_6C]\nsub r15d, 2\nadd r14d, 1\nadd r12d, r14d\ncmp r13d, 1\njnz loc_121D\nloc_1425:\nadd r12d, 1\nloc_1429:\nadd rsp, 58h\nmov eax, r12d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1440:\nmov edx, ebx\nmov ebx, [rsp+88h+var_74]\njmp loc_133A", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1)\n{\n unsigned int v1; // r12d\n unsigned int v2; // r15d\n int v3; // r12d\n unsigned int v4; // ebp\n int v5; // r12d\n unsigned int v6; // ecx\n int v7; // r14d\n unsigned int v8; // ebp\n unsigned int v9; // edi\n int v10; // r15d\n unsigned int v11; // r13d\n unsigned int v12; // r12d\n unsigned int v13; // ebp\n int v14; // r15d\n unsigned int v15; // r14d\n int v16; // ecx\n unsigned int v17; // ebx\n int v18; // r13d\n unsigned int v19; // edx\n int v20; // ebp\n unsigned int v21; // ecx\n unsigned int v22; // ebx\n unsigned int v23; // r14d\n int v24; // r12d\n unsigned int v25; // ebx\n int v26; // eax\n unsigned int v27; // ebx\n unsigned int v28; // ebx\n unsigned int v30; // [rsp+4h] [rbp-84h]\n unsigned int v31; // [rsp+8h] [rbp-80h]\n unsigned int v32; // [rsp+Ch] [rbp-7Ch]\n int v33; // [rsp+10h] [rbp-78h]\n unsigned int v34; // [rsp+14h] [rbp-74h]\n unsigned int v35; // [rsp+18h] [rbp-70h]\n int v36; // [rsp+1Ch] [rbp-6Ch]\n unsigned int v37; // [rsp+20h] [rbp-68h]\n unsigned int v38; // [rsp+24h] [rbp-64h]\n unsigned int v39; // [rsp+28h] [rbp-60h]\n int v40; // [rsp+2Ch] [rbp-5Ch]\n int v41; // [rsp+30h] [rbp-58h]\n unsigned int v42; // [rsp+34h] [rbp-54h]\n int v43; // [rsp+38h] [rbp-50h]\n unsigned int v44; // [rsp+40h] [rbp-48h]\n unsigned int v45; // [rsp+44h] [rbp-44h]\n unsigned int v46; // [rsp+48h] [rbp-40h]\n unsigned int v47; // [rsp+4Ch] [rbp-3Ch]\n\n v1 = a1;\n if ( a1 >= 2 )\n {\n v2 = a1 - 1;\n v3 = 0;\n do\n {\n if ( v2 == 1 )\n break;\n v36 = v3;\n v37 = v2 - 1;\n v4 = v2 - 1;\n v5 = 0;\n do\n {\n if ( v4 == 1 )\n break;\n v38 = v2;\n v6 = v4 - 1;\n v7 = 0;\n v39 = v4;\n v8 = v4 - 1;\n do\n {\n if ( v8 == 1 )\n break;\n v41 = v7;\n v9 = v8 - 1;\n v10 = 0;\n v11 = v8;\n v42 = v6;\n v40 = v5;\n v12 = v8 - 1;\n do\n {\n if ( v12 == 1 )\n break;\n v43 = v10;\n v33 = 0;\n v13 = v12 - 1;\n v44 = v12 - 1;\n v45 = v12;\n do\n {\n if ( v13 == 1 )\n break;\n v47 = v13;\n v14 = 0;\n v46 = v13 - 1;\n v15 = v13 - 1;\n do\n {\n if ( v15 == 1 )\n break;\n v30 = v11;\n v16 = 0;\n v31 = v15 - 1;\n v17 = v15 - 1;\n v32 = v15;\n do\n {\n if ( v17 == 1 )\n break;\n v18 = 0;\n v19 = v17 - 1;\n v20 = v16;\n v21 = v17;\n v22 = v17 - 1;\n do\n {\n v23 = v22;\n if ( v22 == 1 )\n break;\n v34 = v22;\n v24 = 0;\n v25 = v19;\n while ( 1 )\n {\n v35 = v21;\n v26 = func0(v23 - 1);\n v21 = v35;\n v24 += v26;\n v23 -= 2;\n if ( !v23 )\n break;\n if ( v23 == 1 )\n {\n v19 = v25;\n v27 = v34;\n ++v24;\n goto LABEL_22;\n }\n }\n v19 = v25;\n v27 = v34;\nLABEL_22:\n v18 += v24;\n v22 = v27 - 2;\n }\n while ( v22 );\n v28 = v21;\n v16 = v18 + 1 + v20;\n v17 = v28 - 2;\n }\n while ( v19 != 1 );\n v11 = v30;\n v14 += v16 + 1;\n v15 = v32 - 2;\n }\n while ( v31 != 1 );\n v33 += v14 + 1;\n v13 = v47 - 2;\n }\n while ( v46 != 1 );\n v10 = v33 + 1 + v43;\n v12 = v45 - 2;\n }\n while ( v44 != 1 );\n v6 = v42;\n v5 = v40;\n v8 = v11 - 2;\n v7 = v10 + 1 + v41;\n }\n while ( v9 != 1 );\n v2 = v38;\n v5 += v7 + 1;\n v4 = v39 - 2;\n }\n while ( v6 != 1 );\n v2 -= 2;\n v3 = v5 + 1 + v36;\n }\n while ( v37 != 1 );\n return (unsigned int)(v3 + 1);\n }\n return v1;\n}", + "ida_strip_asm": "sub_11F0:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12d, edi\npush rbp\npush rbx\nsub rsp, 58h\ntest edi, edi\njz loc_1429\ncmp edi, 1\njz loc_1429\nlea r15d, [rdi-1]\nxor r12d, r12d\nloc_121D:\ncmp r15d, 1\njz loc_1425\nlea r13d, [r15-1]\nxor r14d, r14d\nmov [rsp+88h+var_6C], r12d\nmov [rsp+88h+var_68], r13d\nmov ebp, r13d\nmov r12d, r14d\nloc_123E:\ncmp ebp, 1\njz loc_1403\nmov [rsp+88h+var_64], r15d\nlea ecx, [rbp-1]\nxor r14d, r14d\nmov [rsp+88h+var_60], ebp\nmov ebp, ecx\nloc_1258:\ncmp ebp, 1\njz loc_13E7\nmov [rsp+88h+var_58], r14d\nlea edi, [rbp-1]\nxor r15d, r15d\nmov r13d, ebp\nmov [rsp+88h+var_54], ecx\nmov [rsp+88h+var_5C], r12d\nmov r12d, edi\nloc_127B:\ncmp r12d, 1\njz loc_13C3\nlea r11d, [r12-1]\nxor r14d, r14d\nmov [rsp+88h+var_50], r15d\nmov [rsp+88h+var_78], r14d\nmov ebp, r11d\nmov [rsp+88h+var_4C], edi\nmov [rsp+88h+var_48], r11d\nmov [rsp+88h+var_44], r12d\nloc_12A8:\ncmp ebp, 1\njz loc_1396\nlea r12d, [rbp-1]\nmov [rsp+88h+var_3C], ebp\nxor r15d, r15d\nmov [rsp+88h+var_40], r12d\nmov r14d, r12d\nloc_12C4:\ncmp r14d, 1\njz loc_1377\nlea ebp, [r14-1]\nmov [rsp+88h+var_84], r13d\nxor ecx, ecx\nmov [rsp+88h+var_80], ebp\nmov ebx, ebp\nmov [rsp+88h+var_7C], r14d\nloc_12E4:\ncmp ebx, 1\njz short loc_1354\nlea ebp, [rbx-1]\nxor r13d, r13d\nmov r14d, ebp\nmov edx, ebp\nmov ebp, ecx\nmov ecx, ebx\nmov ebx, r14d\nloc_12FB:\nmov r14d, ebx\ncmp ebx, 1\njz short loc_1342\nmov [rsp+88h+var_74], ebx\nxor r12d, r12d\nmov ebx, edx\nloc_130C:\nlea edi, [r14-1]\nmov [rsp+88h+var_70], ecx\ncall sub_11F0\nmov ecx, [rsp+88h+var_70]\nadd r12d, eax\nsub r14d, 2\njz loc_1440\ncmp r14d, 1\njnz short loc_130C\nmov edx, ebx\nmov ebx, [rsp+88h+var_74]\nadd r12d, 1\nloc_133A:\nadd r13d, r12d\nsub ebx, 2\njnz short loc_12FB\nloc_1342:\nmov ebx, ecx\nlea esi, [r13+1]\nmov ecx, ebp\nadd ecx, esi\nsub ebx, 2\ncmp edx, 1\njnz short loc_12E4\nloc_1354:\nmov r14d, [rsp+88h+var_7C]\nmov ebx, ecx\nmov ebp, [rsp+88h+var_80]\nadd ebx, 1\nmov r13d, [rsp+88h+var_84]\nadd r15d, ebx\nsub r14d, 2\ncmp ebp, 1\njnz loc_12C4\nloc_1377:\nmov ebp, [rsp+88h+var_3C]\nmov r12d, [rsp+88h+var_40]\nadd r15d, 1\nadd [rsp+88h+var_78], r15d\nsub ebp, 2\ncmp r12d, 1\njnz loc_12A8\nloc_1396:\nmov r14d, [rsp+88h+var_78]\nmov r15d, [rsp+88h+var_50]\nmov r12d, [rsp+88h+var_44]\nmov r11d, [rsp+88h+var_48]\nadd r14d, 1\nmov edi, [rsp+88h+var_4C]\nadd r15d, r14d\nsub r12d, 2\ncmp r11d, 1\njnz loc_127B\nloc_13C3:\nmov r14d, [rsp+88h+var_58]\nmov ebp, r13d\nadd r15d, 1\nmov ecx, [rsp+88h+var_54]\nmov r12d, [rsp+88h+var_5C]\nsub ebp, 2\nadd r14d, r15d\ncmp edi, 1\njnz loc_1258\nloc_13E7:\nmov ebp, [rsp+88h+var_60]\nadd r14d, 1\nmov r15d, [rsp+88h+var_64]\nadd r12d, r14d\nsub ebp, 2\ncmp ecx, 1\njnz loc_123E\nloc_1403:\nmov r14d, r12d\nmov r13d, [rsp+88h+var_68]\nmov r12d, [rsp+88h+var_6C]\nsub r15d, 2\nadd r14d, 1\nadd r12d, r14d\ncmp r13d, 1\njnz loc_121D\nloc_1425:\nadd r12d, 1\nloc_1429:\nadd rsp, 58h\nmov eax, r12d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1440:\nmov edx, ebx\nmov ebx, [rsp+88h+var_74]\njmp loc_133A", + "ida_strip_pseudo": "__int64 __fastcall sub_11F0(unsigned int a1)\n{\n unsigned int v1; // r12d\n unsigned int v2; // r15d\n int v3; // r12d\n unsigned int v4; // ebp\n int v5; // r12d\n unsigned int v6; // ecx\n int v7; // r14d\n unsigned int v8; // ebp\n unsigned int v9; // edi\n int v10; // r15d\n unsigned int v11; // r13d\n unsigned int v12; // r12d\n unsigned int v13; // ebp\n int v14; // r15d\n unsigned int v15; // r14d\n int v16; // ecx\n unsigned int v17; // ebx\n int v18; // r13d\n unsigned int v19; // edx\n int v20; // ebp\n unsigned int v21; // ecx\n unsigned int v22; // ebx\n unsigned int v23; // r14d\n int v24; // r12d\n unsigned int v25; // ebx\n int v26; // eax\n unsigned int v27; // ebx\n unsigned int v28; // ebx\n unsigned int v30; // [rsp+4h] [rbp-84h]\n unsigned int v31; // [rsp+8h] [rbp-80h]\n unsigned int v32; // [rsp+Ch] [rbp-7Ch]\n int v33; // [rsp+10h] [rbp-78h]\n unsigned int v34; // [rsp+14h] [rbp-74h]\n unsigned int v35; // [rsp+18h] [rbp-70h]\n int v36; // [rsp+1Ch] [rbp-6Ch]\n unsigned int v37; // [rsp+20h] [rbp-68h]\n unsigned int v38; // [rsp+24h] [rbp-64h]\n unsigned int v39; // [rsp+28h] [rbp-60h]\n int v40; // [rsp+2Ch] [rbp-5Ch]\n int v41; // [rsp+30h] [rbp-58h]\n unsigned int v42; // [rsp+34h] [rbp-54h]\n int v43; // [rsp+38h] [rbp-50h]\n unsigned int v44; // [rsp+40h] [rbp-48h]\n unsigned int v45; // [rsp+44h] [rbp-44h]\n unsigned int v46; // [rsp+48h] [rbp-40h]\n unsigned int v47; // [rsp+4Ch] [rbp-3Ch]\n\n v1 = a1;\n if ( a1 >= 2 )\n {\n v2 = a1 - 1;\n v3 = 0;\n do\n {\n if ( v2 == 1 )\n break;\n v36 = v3;\n v37 = v2 - 1;\n v4 = v2 - 1;\n v5 = 0;\n do\n {\n if ( v4 == 1 )\n break;\n v38 = v2;\n v6 = v4 - 1;\n v7 = 0;\n v39 = v4;\n v8 = v4 - 1;\n do\n {\n if ( v8 == 1 )\n break;\n v41 = v7;\n v9 = v8 - 1;\n v10 = 0;\n v11 = v8;\n v42 = v6;\n v40 = v5;\n v12 = v8 - 1;\n do\n {\n if ( v12 == 1 )\n break;\n v43 = v10;\n v33 = 0;\n v13 = v12 - 1;\n v44 = v12 - 1;\n v45 = v12;\n do\n {\n if ( v13 == 1 )\n break;\n v47 = v13;\n v14 = 0;\n v46 = v13 - 1;\n v15 = v13 - 1;\n do\n {\n if ( v15 == 1 )\n break;\n v30 = v11;\n v16 = 0;\n v31 = v15 - 1;\n v17 = v15 - 1;\n v32 = v15;\n do\n {\n if ( v17 == 1 )\n break;\n v18 = 0;\n v19 = v17 - 1;\n v20 = v16;\n v21 = v17;\n v22 = v17 - 1;\n do\n {\n v23 = v22;\n if ( v22 == 1 )\n break;\n v34 = v22;\n v24 = 0;\n v25 = v19;\n while ( 1 )\n {\n v35 = v21;\n v26 = sub_11F0(v23 - 1);\n v21 = v35;\n v24 += v26;\n v23 -= 2;\n if ( !v23 )\n break;\n if ( v23 == 1 )\n {\n v19 = v25;\n v27 = v34;\n ++v24;\n goto LABEL_22;\n }\n }\n v19 = v25;\n v27 = v34;\nLABEL_22:\n v18 += v24;\n v22 = v27 - 2;\n }\n while ( v22 );\n v28 = v21;\n v16 = v18 + 1 + v20;\n v17 = v28 - 2;\n }\n while ( v19 != 1 );\n v11 = v30;\n v14 += v16 + 1;\n v15 = v32 - 2;\n }\n while ( v31 != 1 );\n v33 += v14 + 1;\n v13 = v47 - 2;\n }\n while ( v46 != 1 );\n v10 = v33 + 1 + v43;\n v12 = v45 - 2;\n }\n while ( v44 != 1 );\n v6 = v42;\n v5 = v40;\n v8 = v11 - 2;\n v7 = v10 + 1 + v41;\n }\n while ( v9 != 1 );\n v2 = v38;\n v5 += v7 + 1;\n v4 = v39 - 2;\n }\n while ( v6 != 1 );\n v2 -= 2;\n v3 = v5 + 1 + v36;\n }\n while ( v37 != 1 );\n return (unsigned int)(v3 + 1);\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11F0(unsigned int a1) {\n unsigned int v1;\n unsigned int v2;\n int v3;\n unsigned int v4;\n int v5;\n unsigned int v6;\n int v7;\n unsigned int v8;\n unsigned int v9;\n int v10;\n unsigned int v11;\n unsigned int v12;\n unsigned int v13;\n int v14;\n unsigned int v15;\n int v16;\n unsigned int v17;\n int v18;\n unsigned int v19;\n int v20;\n unsigned int v21;\n unsigned int v22;\n unsigned int v23;\n int v24;\n unsigned int v25;\n int v26;\n unsigned int v27;\n unsigned int v28;\n unsigned int v30;\n unsigned int v31;\n unsigned int v32;\n int v33;\n unsigned int v34;\n unsigned int v35;\n int v36;\n unsigned int v37;\n unsigned int v38;\n unsigned int v39;\n int v40;\n int v41;\n unsigned int v42;\n int v43;\n unsigned int v44;\n unsigned int v45;\n unsigned int v46;\n unsigned int v47;\n v1 = a1;\n if (a1 >= 2) {\n v2 = a1 - 1;\n v3 = 0;\n do {\n if (v2 == 1) break;\n v36 = v3;\n v37 = v2 - 1;\n v4 = v2 - 1;\n v5 = 0;\n do {\n if (v4 == 1) break;\n v38 = v2;\n v6 = v4 - 1;\n v7 = 0;\n v39 = v4;\n v8 = v4 - 1;\n do {\n if (v8 == 1) break;\n v41 = v7;\n v9 = v8 - 1;\n v10 = 0;\n v11 = v8;\n v42 = v6;\n v40 = v5;\n v12 = v8 - 1;\n do {\n if (v12 == 1) break;\n v43 = v10;\n v33 = 0;\n v13 = v12 - 1;\n v44 = v12 - 1;\n v45 = v12;\n do {\n if (v13 == 1) break;\n v47 = v13;\n v14 = 0;\n v46 = v13 - 1;\n v15 = v13 - 1;\n do {\n if (v15 == 1) break;\n v30 = v11;\n v16 = 0;\n v31 = v15 - 1;\n v17 = v15 - 1;\n v32 = v15;\n do {\n if (v17 == 1) break;\n v18 = 0;\n v19 = v17 - 1;\n v20 = v16;\n v21 = v17;\n v22 = v17 - 1;\n do {\n v23 = v22;\n if (v22 == 1) break;\n v34 = v22;\n v24 = 0;\n v25 = v19;\n while (1) {\n v35 = v21;\n v26 = sub_11F0(v23 - 1);\n v21 = v35;\n v24 += v26;\n v23 -= 2;\n if (!v23) break;\n if (v23 == 1) {\n v19 = v25;\n v27 = v34;\n ++v24;\n goto LABEL_22;\n }\n }\n v19 = v25;\n v27 = v34;\n LABEL_22:\n v18 += v24;\n v22 = v27 - 2;\n } while (v22);\n v28 = v21;\n v16 = v18 + 1 + v20;\n v17 = v28 - 2;\n } while (v19 != 1);\n v11 = v30;\n v14 += v16 + 1;\n v15 = v32 - 2;\n } while (v31 != 1);\n v33 += v14 + 1;\n v13 = v47 - 2;\n } while (v46 != 1);\n v10 = v33 + 1 + v43;\n v12 = v45 - 2;\n } while (v44 != 1);\n v6 = v42;\n v5 = v40;\n v8 = v11 - 2;\n v7 = v10 + 1 + v41;\n } while (v9 != 1);\n v2 = v38;\n v5 += v7 + 1;\n v4 = v39 - 2;\n } while (v6 != 1);\n v2 -= 2;\n v3 = v5 + 1 + v36;\n } while (v37 != 1);\n return (unsigned int)(v3 + 1);\n }\n return v1;\n}", + "ida_pseudo_norm": "long long func0(unsigned int a1) {\n unsigned int v1;\n unsigned int v2;\n int v3;\n unsigned int v4;\n int v5;\n unsigned int v6;\n int v7;\n unsigned int v8;\n unsigned int v9;\n int v10;\n unsigned int v11;\n unsigned int v12;\n unsigned int v13;\n int v14;\n unsigned int v15;\n int v16;\n unsigned int v17;\n int v18;\n unsigned int v19;\n int v20;\n unsigned int v21;\n unsigned int v22;\n unsigned int v23;\n int v24;\n unsigned int v25;\n int v26;\n unsigned int v27;\n unsigned int v28;\n unsigned int v30;\n unsigned int v31;\n unsigned int v32;\n int v33;\n unsigned int v34;\n unsigned int v35;\n int v36;\n unsigned int v37;\n unsigned int v38;\n unsigned int v39;\n int v40;\n int v41;\n unsigned int v42;\n int v43;\n unsigned int v44;\n unsigned int v45;\n unsigned int v46;\n unsigned int v47;\n v1 = a1;\n if (a1 >= 2) {\n v2 = a1 - 1;\n v3 = 0;\n do {\n if (v2 == 1) break;\n v36 = v3;\n v37 = v2 - 1;\n v4 = v2 - 1;\n v5 = 0;\n do {\n if (v4 == 1) break;\n v38 = v2;\n v6 = v4 - 1;\n v7 = 0;\n v39 = v4;\n v8 = v4 - 1;\n do {\n if (v8 == 1) break;\n v41 = v7;\n v9 = v8 - 1;\n v10 = 0;\n v11 = v8;\n v42 = v6;\n v40 = v5;\n v12 = v8 - 1;\n do {\n if (v12 == 1) break;\n v43 = v10;\n v33 = 0;\n v13 = v12 - 1;\n v44 = v12 - 1;\n v45 = v12;\n do {\n if (v13 == 1) break;\n v47 = v13;\n v14 = 0;\n v46 = v13 - 1;\n v15 = v13 - 1;\n do {\n if (v15 == 1) break;\n v30 = v11;\n v16 = 0;\n v31 = v15 - 1;\n v17 = v15 - 1;\n v32 = v15;\n do {\n if (v17 == 1) break;\n v18 = 0;\n v19 = v17 - 1;\n v20 = v16;\n v21 = v17;\n v22 = v17 - 1;\n do {\n v23 = v22;\n if (v22 == 1) break;\n v34 = v22;\n v24 = 0;\n v25 = v19;\n while (1) {\n v35 = v21;\n v26 = func0(v23 - 1);\n v21 = v35;\n v24 += v26;\n v23 -= 2;\n if (!v23) break;\n if (v23 == 1) {\n v19 = v25;\n v27 = v34;\n ++v24;\n goto LABEL_22;\n }\n }\n v19 = v25;\n v27 = v34;\n LABEL_22:\n v18 += v24;\n v22 = v27 - 2;\n } while (v22);\n v28 = v21;\n v16 = v18 + 1 + v20;\n v17 = v28 - 2;\n } while (v19 != 1);\n v11 = v30;\n v14 += v16 + 1;\n v15 = v32 - 2;\n } while (v31 != 1);\n v33 += v14 + 1;\n v13 = v47 - 2;\n } while (v46 != 1);\n v10 = v33 + 1 + v43;\n v12 = v45 - 2;\n } while (v44 != 1);\n v6 = v42;\n v5 = v40;\n v8 = v11 - 2;\n v7 = v10 + 1 + v41;\n } while (v9 != 1);\n v2 = v38;\n v5 += v7 + 1;\n v4 = v39 - 2;\n } while (v6 != 1);\n v2 -= 2;\n v3 = v5 + 1 + v36;\n } while (v37 != 1);\n return (unsigned int)(v3 + 1);\n }\n return v1;\n}" + }, + { + "index": 960, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int n) {\n if (n == 0) return 0;\n if (n == 1) return 1;\n return func0(n - 1) + func0(n - 2);\n}", + "test": "int main() {\n\n assert(func0(4) == 3);\n\n assert(func0(3) == 2);\n\n assert(func0(5) == 5);\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbx\nsub $0x8,%rsp\ntest %edi,%edi\nje 1230 \nmov %edi,%ebx\ncmp $0x1,%edi\nje 1240 \nxor %r12d,%r12d\nlea -0x1(%rbx),%edi\ncallq 11f0 \nadd %eax,%r12d\nsub $0x2,%ebx\nje 1222 \ncmp $0x1,%ebx\njne 1209 \nadd $0x1,%r12d\nadd $0x8,%rsp\nmov %r12d,%eax\npop %rbx\npop %r12\nretq\nnopl (%rax)\nxor %r12d,%r12d\nadd $0x8,%rsp\nmov %r12d,%eax\npop %rbx\npop %r12\nretq\nxchg %ax,%ax\nmov $0x1,%r12d\njmp 1222 \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12d, edi\npush rbp\npush rbx\nsub rsp, 58h\ntest edi, edi\njz loc_1429\ncmp edi, 1\njz loc_1429\nlea r15d, [rdi-1]\nxor r12d, r12d\nloc_121D:\ncmp r15d, 1\njz loc_1425\nlea r13d, [r15-1]\nxor r14d, r14d\nmov [rsp+88h+var_6C], r12d\nmov [rsp+88h+var_68], r13d\nmov ebp, r13d\nmov r12d, r14d\nloc_123E:\ncmp ebp, 1\njz loc_1403\nmov [rsp+88h+var_64], r15d\nlea ecx, [rbp-1]\nxor r14d, r14d\nmov [rsp+88h+var_60], ebp\nmov ebp, ecx\nloc_1258:\ncmp ebp, 1\njz loc_13E7\nmov [rsp+88h+var_58], r14d\nlea edi, [rbp-1]\nxor r15d, r15d\nmov r13d, ebp\nmov [rsp+88h+var_54], ecx\nmov [rsp+88h+var_5C], r12d\nmov r12d, edi\nloc_127B:\ncmp r12d, 1\njz loc_13C3\nlea r11d, [r12-1]\nxor r14d, r14d\nmov [rsp+88h+var_50], r15d\nmov [rsp+88h+var_78], r14d\nmov ebp, r11d\nmov [rsp+88h+var_4C], edi\nmov [rsp+88h+var_48], r11d\nmov [rsp+88h+var_44], r12d\nloc_12A8:\ncmp ebp, 1\njz loc_1396\nlea r12d, [rbp-1]\nmov [rsp+88h+var_3C], ebp\nxor r15d, r15d\nmov [rsp+88h+var_40], r12d\nmov r14d, r12d\nloc_12C4:\ncmp r14d, 1\njz loc_1377\nlea ebp, [r14-1]\nmov [rsp+88h+var_84], r13d\nxor ecx, ecx\nmov [rsp+88h+var_80], ebp\nmov ebx, ebp\nmov [rsp+88h+var_7C], r14d\nloc_12E4:\ncmp ebx, 1\njz short loc_1354\nlea ebp, [rbx-1]\nxor r13d, r13d\nmov r14d, ebp\nmov edx, ebp\nmov ebp, ecx\nmov ecx, ebx\nmov ebx, r14d\nloc_12FB:\nmov r14d, ebx\ncmp ebx, 1\njz short loc_1342\nmov [rsp+88h+var_74], ebx\nxor r12d, r12d\nmov ebx, edx\nloc_130C:\nlea edi, [r14-1]\nmov [rsp+88h+var_70], ecx\ncall func0\nmov ecx, [rsp+88h+var_70]\nadd r12d, eax\nsub r14d, 2\njz loc_1440\ncmp r14d, 1\njnz short loc_130C\nmov edx, ebx\nmov ebx, [rsp+88h+var_74]\nadd r12d, 1\nloc_133A:\nadd r13d, r12d\nsub ebx, 2\njnz short loc_12FB\nloc_1342:\nmov ebx, ecx\nlea esi, [r13+1]\nmov ecx, ebp\nadd ecx, esi\nsub ebx, 2\ncmp edx, 1\njnz short loc_12E4\nloc_1354:\nmov r14d, [rsp+88h+var_7C]\nmov ebx, ecx\nmov ebp, [rsp+88h+var_80]\nadd ebx, 1\nmov r13d, [rsp+88h+var_84]\nadd r15d, ebx\nsub r14d, 2\ncmp ebp, 1\njnz loc_12C4\nloc_1377:\nmov ebp, [rsp+88h+var_3C]\nmov r12d, [rsp+88h+var_40]\nadd r15d, 1\nadd [rsp+88h+var_78], r15d\nsub ebp, 2\ncmp r12d, 1\njnz loc_12A8\nloc_1396:\nmov r14d, [rsp+88h+var_78]\nmov r15d, [rsp+88h+var_50]\nmov r12d, [rsp+88h+var_44]\nmov r11d, [rsp+88h+var_48]\nadd r14d, 1\nmov edi, [rsp+88h+var_4C]\nadd r15d, r14d\nsub r12d, 2\ncmp r11d, 1\njnz loc_127B\nloc_13C3:\nmov r14d, [rsp+88h+var_58]\nmov ebp, r13d\nadd r15d, 1\nmov ecx, [rsp+88h+var_54]\nmov r12d, [rsp+88h+var_5C]\nsub ebp, 2\nadd r14d, r15d\ncmp edi, 1\njnz loc_1258\nloc_13E7:\nmov ebp, [rsp+88h+var_60]\nadd r14d, 1\nmov r15d, [rsp+88h+var_64]\nadd r12d, r14d\nsub ebp, 2\ncmp ecx, 1\njnz loc_123E\nloc_1403:\nmov r14d, r12d\nmov r13d, [rsp+88h+var_68]\nmov r12d, [rsp+88h+var_6C]\nsub r15d, 2\nadd r14d, 1\nadd r12d, r14d\ncmp r13d, 1\njnz loc_121D\nloc_1425:\nadd r12d, 1\nloc_1429:\nadd rsp, 58h\nmov eax, r12d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1440:\nmov edx, ebx\nmov ebx, [rsp+88h+var_74]\njmp loc_133A", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1)\n{\n unsigned int v1; // r12d\n unsigned int v2; // r15d\n int v3; // r12d\n unsigned int v4; // ebp\n int v5; // r12d\n unsigned int v6; // ecx\n int v7; // r14d\n unsigned int v8; // ebp\n unsigned int v9; // edi\n int v10; // r15d\n unsigned int v11; // r13d\n unsigned int v12; // r12d\n unsigned int v13; // ebp\n int v14; // r15d\n unsigned int v15; // r14d\n int v16; // ecx\n unsigned int v17; // ebx\n int v18; // r13d\n unsigned int v19; // edx\n int v20; // ebp\n unsigned int v21; // ecx\n unsigned int v22; // ebx\n unsigned int v23; // r14d\n int v24; // r12d\n unsigned int v25; // ebx\n int v26; // eax\n unsigned int v27; // ebx\n unsigned int v28; // ebx\n unsigned int v30; // [rsp+4h] [rbp-84h]\n unsigned int v31; // [rsp+8h] [rbp-80h]\n unsigned int v32; // [rsp+Ch] [rbp-7Ch]\n int v33; // [rsp+10h] [rbp-78h]\n unsigned int v34; // [rsp+14h] [rbp-74h]\n unsigned int v35; // [rsp+18h] [rbp-70h]\n int v36; // [rsp+1Ch] [rbp-6Ch]\n unsigned int v37; // [rsp+20h] [rbp-68h]\n unsigned int v38; // [rsp+24h] [rbp-64h]\n unsigned int v39; // [rsp+28h] [rbp-60h]\n int v40; // [rsp+2Ch] [rbp-5Ch]\n int v41; // [rsp+30h] [rbp-58h]\n unsigned int v42; // [rsp+34h] [rbp-54h]\n int v43; // [rsp+38h] [rbp-50h]\n unsigned int v44; // [rsp+40h] [rbp-48h]\n unsigned int v45; // [rsp+44h] [rbp-44h]\n unsigned int v46; // [rsp+48h] [rbp-40h]\n unsigned int v47; // [rsp+4Ch] [rbp-3Ch]\n\n v1 = a1;\n if ( a1 >= 2 )\n {\n v2 = a1 - 1;\n v3 = 0;\n do\n {\n if ( v2 == 1 )\n break;\n v36 = v3;\n v37 = v2 - 1;\n v4 = v2 - 1;\n v5 = 0;\n do\n {\n if ( v4 == 1 )\n break;\n v38 = v2;\n v6 = v4 - 1;\n v7 = 0;\n v39 = v4;\n v8 = v4 - 1;\n do\n {\n if ( v8 == 1 )\n break;\n v41 = v7;\n v9 = v8 - 1;\n v10 = 0;\n v11 = v8;\n v42 = v6;\n v40 = v5;\n v12 = v8 - 1;\n do\n {\n if ( v12 == 1 )\n break;\n v43 = v10;\n v33 = 0;\n v13 = v12 - 1;\n v44 = v12 - 1;\n v45 = v12;\n do\n {\n if ( v13 == 1 )\n break;\n v47 = v13;\n v14 = 0;\n v46 = v13 - 1;\n v15 = v13 - 1;\n do\n {\n if ( v15 == 1 )\n break;\n v30 = v11;\n v16 = 0;\n v31 = v15 - 1;\n v17 = v15 - 1;\n v32 = v15;\n do\n {\n if ( v17 == 1 )\n break;\n v18 = 0;\n v19 = v17 - 1;\n v20 = v16;\n v21 = v17;\n v22 = v17 - 1;\n do\n {\n v23 = v22;\n if ( v22 == 1 )\n break;\n v34 = v22;\n v24 = 0;\n v25 = v19;\n while ( 1 )\n {\n v35 = v21;\n v26 = func0(v23 - 1);\n v21 = v35;\n v24 += v26;\n v23 -= 2;\n if ( !v23 )\n break;\n if ( v23 == 1 )\n {\n v19 = v25;\n v27 = v34;\n ++v24;\n goto LABEL_22;\n }\n }\n v19 = v25;\n v27 = v34;\nLABEL_22:\n v18 += v24;\n v22 = v27 - 2;\n }\n while ( v22 );\n v28 = v21;\n v16 = v18 + 1 + v20;\n v17 = v28 - 2;\n }\n while ( v19 != 1 );\n v11 = v30;\n v14 += v16 + 1;\n v15 = v32 - 2;\n }\n while ( v31 != 1 );\n v33 += v14 + 1;\n v13 = v47 - 2;\n }\n while ( v46 != 1 );\n v10 = v33 + 1 + v43;\n v12 = v45 - 2;\n }\n while ( v44 != 1 );\n v6 = v42;\n v5 = v40;\n v8 = v11 - 2;\n v7 = v10 + 1 + v41;\n }\n while ( v9 != 1 );\n v2 = v38;\n v5 += v7 + 1;\n v4 = v39 - 2;\n }\n while ( v6 != 1 );\n v2 -= 2;\n v3 = v5 + 1 + v36;\n }\n while ( v37 != 1 );\n return (unsigned int)(v3 + 1);\n }\n return v1;\n}", + "ida_strip_asm": "sub_11F0:\nendbr64\npush r15\npush r14\npush r13\npush r12\nmov r12d, edi\npush rbp\npush rbx\nsub rsp, 58h\ntest edi, edi\njz loc_1429\ncmp edi, 1\njz loc_1429\nlea r15d, [rdi-1]\nxor r12d, r12d\nloc_121D:\ncmp r15d, 1\njz loc_1425\nlea r13d, [r15-1]\nxor r14d, r14d\nmov [rsp+88h+var_6C], r12d\nmov [rsp+88h+var_68], r13d\nmov ebp, r13d\nmov r12d, r14d\nloc_123E:\ncmp ebp, 1\njz loc_1403\nmov [rsp+88h+var_64], r15d\nlea ecx, [rbp-1]\nxor r14d, r14d\nmov [rsp+88h+var_60], ebp\nmov ebp, ecx\nloc_1258:\ncmp ebp, 1\njz loc_13E7\nmov [rsp+88h+var_58], r14d\nlea edi, [rbp-1]\nxor r15d, r15d\nmov r13d, ebp\nmov [rsp+88h+var_54], ecx\nmov [rsp+88h+var_5C], r12d\nmov r12d, edi\nloc_127B:\ncmp r12d, 1\njz loc_13C3\nlea r11d, [r12-1]\nxor r14d, r14d\nmov [rsp+88h+var_50], r15d\nmov [rsp+88h+var_78], r14d\nmov ebp, r11d\nmov [rsp+88h+var_4C], edi\nmov [rsp+88h+var_48], r11d\nmov [rsp+88h+var_44], r12d\nloc_12A8:\ncmp ebp, 1\njz loc_1396\nlea r12d, [rbp-1]\nmov [rsp+88h+var_3C], ebp\nxor r15d, r15d\nmov [rsp+88h+var_40], r12d\nmov r14d, r12d\nloc_12C4:\ncmp r14d, 1\njz loc_1377\nlea ebp, [r14-1]\nmov [rsp+88h+var_84], r13d\nxor ecx, ecx\nmov [rsp+88h+var_80], ebp\nmov ebx, ebp\nmov [rsp+88h+var_7C], r14d\nloc_12E4:\ncmp ebx, 1\njz short loc_1354\nlea ebp, [rbx-1]\nxor r13d, r13d\nmov r14d, ebp\nmov edx, ebp\nmov ebp, ecx\nmov ecx, ebx\nmov ebx, r14d\nloc_12FB:\nmov r14d, ebx\ncmp ebx, 1\njz short loc_1342\nmov [rsp+88h+var_74], ebx\nxor r12d, r12d\nmov ebx, edx\nloc_130C:\nlea edi, [r14-1]\nmov [rsp+88h+var_70], ecx\ncall sub_11F0\nmov ecx, [rsp+88h+var_70]\nadd r12d, eax\nsub r14d, 2\njz loc_1440\ncmp r14d, 1\njnz short loc_130C\nmov edx, ebx\nmov ebx, [rsp+88h+var_74]\nadd r12d, 1\nloc_133A:\nadd r13d, r12d\nsub ebx, 2\njnz short loc_12FB\nloc_1342:\nmov ebx, ecx\nlea esi, [r13+1]\nmov ecx, ebp\nadd ecx, esi\nsub ebx, 2\ncmp edx, 1\njnz short loc_12E4\nloc_1354:\nmov r14d, [rsp+88h+var_7C]\nmov ebx, ecx\nmov ebp, [rsp+88h+var_80]\nadd ebx, 1\nmov r13d, [rsp+88h+var_84]\nadd r15d, ebx\nsub r14d, 2\ncmp ebp, 1\njnz loc_12C4\nloc_1377:\nmov ebp, [rsp+88h+var_3C]\nmov r12d, [rsp+88h+var_40]\nadd r15d, 1\nadd [rsp+88h+var_78], r15d\nsub ebp, 2\ncmp r12d, 1\njnz loc_12A8\nloc_1396:\nmov r14d, [rsp+88h+var_78]\nmov r15d, [rsp+88h+var_50]\nmov r12d, [rsp+88h+var_44]\nmov r11d, [rsp+88h+var_48]\nadd r14d, 1\nmov edi, [rsp+88h+var_4C]\nadd r15d, r14d\nsub r12d, 2\ncmp r11d, 1\njnz loc_127B\nloc_13C3:\nmov r14d, [rsp+88h+var_58]\nmov ebp, r13d\nadd r15d, 1\nmov ecx, [rsp+88h+var_54]\nmov r12d, [rsp+88h+var_5C]\nsub ebp, 2\nadd r14d, r15d\ncmp edi, 1\njnz loc_1258\nloc_13E7:\nmov ebp, [rsp+88h+var_60]\nadd r14d, 1\nmov r15d, [rsp+88h+var_64]\nadd r12d, r14d\nsub ebp, 2\ncmp ecx, 1\njnz loc_123E\nloc_1403:\nmov r14d, r12d\nmov r13d, [rsp+88h+var_68]\nmov r12d, [rsp+88h+var_6C]\nsub r15d, 2\nadd r14d, 1\nadd r12d, r14d\ncmp r13d, 1\njnz loc_121D\nloc_1425:\nadd r12d, 1\nloc_1429:\nadd rsp, 58h\nmov eax, r12d\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1440:\nmov edx, ebx\nmov ebx, [rsp+88h+var_74]\njmp loc_133A", + "ida_strip_pseudo": "__int64 __fastcall sub_11F0(unsigned int a1)\n{\n unsigned int v1; // r12d\n unsigned int v2; // r15d\n int v3; // r12d\n unsigned int v4; // ebp\n int v5; // r12d\n unsigned int v6; // ecx\n int v7; // r14d\n unsigned int v8; // ebp\n unsigned int v9; // edi\n int v10; // r15d\n unsigned int v11; // r13d\n unsigned int v12; // r12d\n unsigned int v13; // ebp\n int v14; // r15d\n unsigned int v15; // r14d\n int v16; // ecx\n unsigned int v17; // ebx\n int v18; // r13d\n unsigned int v19; // edx\n int v20; // ebp\n unsigned int v21; // ecx\n unsigned int v22; // ebx\n unsigned int v23; // r14d\n int v24; // r12d\n unsigned int v25; // ebx\n int v26; // eax\n unsigned int v27; // ebx\n unsigned int v28; // ebx\n unsigned int v30; // [rsp+4h] [rbp-84h]\n unsigned int v31; // [rsp+8h] [rbp-80h]\n unsigned int v32; // [rsp+Ch] [rbp-7Ch]\n int v33; // [rsp+10h] [rbp-78h]\n unsigned int v34; // [rsp+14h] [rbp-74h]\n unsigned int v35; // [rsp+18h] [rbp-70h]\n int v36; // [rsp+1Ch] [rbp-6Ch]\n unsigned int v37; // [rsp+20h] [rbp-68h]\n unsigned int v38; // [rsp+24h] [rbp-64h]\n unsigned int v39; // [rsp+28h] [rbp-60h]\n int v40; // [rsp+2Ch] [rbp-5Ch]\n int v41; // [rsp+30h] [rbp-58h]\n unsigned int v42; // [rsp+34h] [rbp-54h]\n int v43; // [rsp+38h] [rbp-50h]\n unsigned int v44; // [rsp+40h] [rbp-48h]\n unsigned int v45; // [rsp+44h] [rbp-44h]\n unsigned int v46; // [rsp+48h] [rbp-40h]\n unsigned int v47; // [rsp+4Ch] [rbp-3Ch]\n\n v1 = a1;\n if ( a1 >= 2 )\n {\n v2 = a1 - 1;\n v3 = 0;\n do\n {\n if ( v2 == 1 )\n break;\n v36 = v3;\n v37 = v2 - 1;\n v4 = v2 - 1;\n v5 = 0;\n do\n {\n if ( v4 == 1 )\n break;\n v38 = v2;\n v6 = v4 - 1;\n v7 = 0;\n v39 = v4;\n v8 = v4 - 1;\n do\n {\n if ( v8 == 1 )\n break;\n v41 = v7;\n v9 = v8 - 1;\n v10 = 0;\n v11 = v8;\n v42 = v6;\n v40 = v5;\n v12 = v8 - 1;\n do\n {\n if ( v12 == 1 )\n break;\n v43 = v10;\n v33 = 0;\n v13 = v12 - 1;\n v44 = v12 - 1;\n v45 = v12;\n do\n {\n if ( v13 == 1 )\n break;\n v47 = v13;\n v14 = 0;\n v46 = v13 - 1;\n v15 = v13 - 1;\n do\n {\n if ( v15 == 1 )\n break;\n v30 = v11;\n v16 = 0;\n v31 = v15 - 1;\n v17 = v15 - 1;\n v32 = v15;\n do\n {\n if ( v17 == 1 )\n break;\n v18 = 0;\n v19 = v17 - 1;\n v20 = v16;\n v21 = v17;\n v22 = v17 - 1;\n do\n {\n v23 = v22;\n if ( v22 == 1 )\n break;\n v34 = v22;\n v24 = 0;\n v25 = v19;\n while ( 1 )\n {\n v35 = v21;\n v26 = sub_11F0(v23 - 1);\n v21 = v35;\n v24 += v26;\n v23 -= 2;\n if ( !v23 )\n break;\n if ( v23 == 1 )\n {\n v19 = v25;\n v27 = v34;\n ++v24;\n goto LABEL_22;\n }\n }\n v19 = v25;\n v27 = v34;\nLABEL_22:\n v18 += v24;\n v22 = v27 - 2;\n }\n while ( v22 );\n v28 = v21;\n v16 = v18 + 1 + v20;\n v17 = v28 - 2;\n }\n while ( v19 != 1 );\n v11 = v30;\n v14 += v16 + 1;\n v15 = v32 - 2;\n }\n while ( v31 != 1 );\n v33 += v14 + 1;\n v13 = v47 - 2;\n }\n while ( v46 != 1 );\n v10 = v33 + 1 + v43;\n v12 = v45 - 2;\n }\n while ( v44 != 1 );\n v6 = v42;\n v5 = v40;\n v8 = v11 - 2;\n v7 = v10 + 1 + v41;\n }\n while ( v9 != 1 );\n v2 = v38;\n v5 += v7 + 1;\n v4 = v39 - 2;\n }\n while ( v6 != 1 );\n v2 -= 2;\n v3 = v5 + 1 + v36;\n }\n while ( v37 != 1 );\n return (unsigned int)(v3 + 1);\n }\n return v1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11F0(unsigned int a1) {\n unsigned int v1;\n unsigned int v2;\n int v3;\n unsigned int v4;\n int v5;\n unsigned int v6;\n int v7;\n unsigned int v8;\n unsigned int v9;\n int v10;\n unsigned int v11;\n unsigned int v12;\n unsigned int v13;\n int v14;\n unsigned int v15;\n int v16;\n unsigned int v17;\n int v18;\n unsigned int v19;\n int v20;\n unsigned int v21;\n unsigned int v22;\n unsigned int v23;\n int v24;\n unsigned int v25;\n int v26;\n unsigned int v27;\n unsigned int v28;\n unsigned int v30;\n unsigned int v31;\n unsigned int v32;\n int v33;\n unsigned int v34;\n unsigned int v35;\n int v36;\n unsigned int v37;\n unsigned int v38;\n unsigned int v39;\n int v40;\n int v41;\n unsigned int v42;\n int v43;\n unsigned int v44;\n unsigned int v45;\n unsigned int v46;\n unsigned int v47;\n v1 = a1;\n if (a1 >= 2) {\n v2 = a1 - 1;\n v3 = 0;\n do {\n if (v2 == 1) break;\n v36 = v3;\n v37 = v2 - 1;\n v4 = v2 - 1;\n v5 = 0;\n do {\n if (v4 == 1) break;\n v38 = v2;\n v6 = v4 - 1;\n v7 = 0;\n v39 = v4;\n v8 = v4 - 1;\n do {\n if (v8 == 1) break;\n v41 = v7;\n v9 = v8 - 1;\n v10 = 0;\n v11 = v8;\n v42 = v6;\n v40 = v5;\n v12 = v8 - 1;\n do {\n if (v12 == 1) break;\n v43 = v10;\n v33 = 0;\n v13 = v12 - 1;\n v44 = v12 - 1;\n v45 = v12;\n do {\n if (v13 == 1) break;\n v47 = v13;\n v14 = 0;\n v46 = v13 - 1;\n v15 = v13 - 1;\n do {\n if (v15 == 1) break;\n v30 = v11;\n v16 = 0;\n v31 = v15 - 1;\n v17 = v15 - 1;\n v32 = v15;\n do {\n if (v17 == 1) break;\n v18 = 0;\n v19 = v17 - 1;\n v20 = v16;\n v21 = v17;\n v22 = v17 - 1;\n do {\n v23 = v22;\n if (v22 == 1) break;\n v34 = v22;\n v24 = 0;\n v25 = v19;\n while (1) {\n v35 = v21;\n v26 = sub_11F0(v23 - 1);\n v21 = v35;\n v24 += v26;\n v23 -= 2;\n if (!v23) break;\n if (v23 == 1) {\n v19 = v25;\n v27 = v34;\n ++v24;\n goto LABEL_22;\n }\n }\n v19 = v25;\n v27 = v34;\n LABEL_22:\n v18 += v24;\n v22 = v27 - 2;\n } while (v22);\n v28 = v21;\n v16 = v18 + 1 + v20;\n v17 = v28 - 2;\n } while (v19 != 1);\n v11 = v30;\n v14 += v16 + 1;\n v15 = v32 - 2;\n } while (v31 != 1);\n v33 += v14 + 1;\n v13 = v47 - 2;\n } while (v46 != 1);\n v10 = v33 + 1 + v43;\n v12 = v45 - 2;\n } while (v44 != 1);\n v6 = v42;\n v5 = v40;\n v8 = v11 - 2;\n v7 = v10 + 1 + v41;\n } while (v9 != 1);\n v2 = v38;\n v5 += v7 + 1;\n v4 = v39 - 2;\n } while (v6 != 1);\n v2 -= 2;\n v3 = v5 + 1 + v36;\n } while (v37 != 1);\n return (unsigned int)(v3 + 1);\n }\n return v1;\n}", + "ida_pseudo_norm": "long long func0(unsigned int a1) {\n unsigned int v1;\n unsigned int v2;\n int v3;\n unsigned int v4;\n int v5;\n unsigned int v6;\n int v7;\n unsigned int v8;\n unsigned int v9;\n int v10;\n unsigned int v11;\n unsigned int v12;\n unsigned int v13;\n int v14;\n unsigned int v15;\n int v16;\n unsigned int v17;\n int v18;\n unsigned int v19;\n int v20;\n unsigned int v21;\n unsigned int v22;\n unsigned int v23;\n int v24;\n unsigned int v25;\n int v26;\n unsigned int v27;\n unsigned int v28;\n unsigned int v30;\n unsigned int v31;\n unsigned int v32;\n int v33;\n unsigned int v34;\n unsigned int v35;\n int v36;\n unsigned int v37;\n unsigned int v38;\n unsigned int v39;\n int v40;\n int v41;\n unsigned int v42;\n int v43;\n unsigned int v44;\n unsigned int v45;\n unsigned int v46;\n unsigned int v47;\n v1 = a1;\n if (a1 >= 2) {\n v2 = a1 - 1;\n v3 = 0;\n do {\n if (v2 == 1) break;\n v36 = v3;\n v37 = v2 - 1;\n v4 = v2 - 1;\n v5 = 0;\n do {\n if (v4 == 1) break;\n v38 = v2;\n v6 = v4 - 1;\n v7 = 0;\n v39 = v4;\n v8 = v4 - 1;\n do {\n if (v8 == 1) break;\n v41 = v7;\n v9 = v8 - 1;\n v10 = 0;\n v11 = v8;\n v42 = v6;\n v40 = v5;\n v12 = v8 - 1;\n do {\n if (v12 == 1) break;\n v43 = v10;\n v33 = 0;\n v13 = v12 - 1;\n v44 = v12 - 1;\n v45 = v12;\n do {\n if (v13 == 1) break;\n v47 = v13;\n v14 = 0;\n v46 = v13 - 1;\n v15 = v13 - 1;\n do {\n if (v15 == 1) break;\n v30 = v11;\n v16 = 0;\n v31 = v15 - 1;\n v17 = v15 - 1;\n v32 = v15;\n do {\n if (v17 == 1) break;\n v18 = 0;\n v19 = v17 - 1;\n v20 = v16;\n v21 = v17;\n v22 = v17 - 1;\n do {\n v23 = v22;\n if (v22 == 1) break;\n v34 = v22;\n v24 = 0;\n v25 = v19;\n while (1) {\n v35 = v21;\n v26 = func0(v23 - 1);\n v21 = v35;\n v24 += v26;\n v23 -= 2;\n if (!v23) break;\n if (v23 == 1) {\n v19 = v25;\n v27 = v34;\n ++v24;\n goto LABEL_22;\n }\n }\n v19 = v25;\n v27 = v34;\n LABEL_22:\n v18 += v24;\n v22 = v27 - 2;\n } while (v22);\n v28 = v21;\n v16 = v18 + 1 + v20;\n v17 = v28 - 2;\n } while (v19 != 1);\n v11 = v30;\n v14 += v16 + 1;\n v15 = v32 - 2;\n } while (v31 != 1);\n v33 += v14 + 1;\n v13 = v47 - 2;\n } while (v46 != 1);\n v10 = v33 + 1 + v43;\n v12 = v45 - 2;\n } while (v44 != 1);\n v6 = v42;\n v5 = v40;\n v8 = v11 - 2;\n v7 = v10 + 1 + v41;\n } while (v9 != 1);\n v2 = v38;\n v5 += v7 + 1;\n v4 = v39 - 2;\n } while (v6 != 1);\n v2 -= 2;\n v3 = v5 + 1 + v36;\n } while (v37 != 1);\n return (unsigned int)(v3 + 1);\n }\n return v1;\n}" + }, + { + "index": 961, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char *s) {\n int rom_val[256] = {0};\n rom_val['I'] = 1;\n rom_val['V'] = 5;\n rom_val['X'] = 10;\n rom_val['L'] = 50;\n rom_val['C'] = 100;\n rom_val['D'] = 500;\n rom_val['M'] = 1000;\n int int_val = 0;\n int len = strlen(s);\n for (int i = 0; i < len; i++) {\n if (i > 0 && rom_val[s[i]] > rom_val[s[i - 1]]) {\n int_val += rom_val[s[i]] - 2 * rom_val[s[i - 1]];\n } else {\n int_val += rom_val[s[i]];\n }\n }\n return int_val;\n}", + "test": "int main() {\n\n assert(func0(\"MMMCMLXXXVI\") == 3986);\n\n assert(func0(\"MMMM\") == 4000);\n\n assert(func0(\"C\") == 100);\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x430,%rsp\nmov %rdi,-0x428(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nlea -0x410(%rbp),%rdx\nmov $0x0,%eax\nmov $0x80,%ecx\nmov %rdx,%rdi\nrep stos %rax,%es:(%rdi)\nmovl $0x1,-0x2ec(%rbp)\nmovl $0x5,-0x2b8(%rbp)\nmovl $0xa,-0x2b0(%rbp)\nmovl $0x32,-0x2e0(%rbp)\nmovl $0x64,-0x304(%rbp)\nmovl $0x1f4,-0x300(%rbp)\nmovl $0x3e8,-0x2dc(%rbp)\nmovl $0x0,-0x41c(%rbp)\nmov -0x428(%rbp),%rax\nmov %rax,%rdi\ncallq 1090 \nmov %eax,-0x414(%rbp)\nmovl $0x0,-0x418(%rbp)\njmpq 1335 \ncmpl $0x0,-0x418(%rbp)\njle 1306 \nmov -0x418(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x428(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmovsbl %al,%eax\ncltq\nmov -0x410(%rbp,%rax,4),%edx\nmov -0x418(%rbp),%eax\ncltq\nlea -0x1(%rax),%rcx\nmov -0x428(%rbp),%rax\nadd %rcx,%rax\nmovzbl (%rax),%eax\nmovsbl %al,%eax\ncltq\nmov -0x410(%rbp,%rax,4),%eax\ncmp %eax,%edx\njle 1306 \nmov -0x418(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x428(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmovsbl %al,%eax\ncltq\nmov -0x410(%rbp,%rax,4),%edx\nmov -0x418(%rbp),%eax\ncltq\nlea -0x1(%rax),%rcx\nmov -0x428(%rbp),%rax\nadd %rcx,%rax\nmovzbl (%rax),%eax\nmovsbl %al,%eax\ncltq\nmov -0x410(%rbp,%rax,4),%eax\nadd %eax,%eax\nsub %eax,%edx\nmov %edx,%eax\nadd %eax,-0x41c(%rbp)\njmp 132e \nmov -0x418(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x428(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmovsbl %al,%eax\ncltq\nmov -0x410(%rbp,%rax,4),%eax\nadd %eax,-0x41c(%rbp)\naddl $0x1,-0x418(%rbp)\nmov -0x418(%rbp),%eax\ncmp -0x414(%rbp),%eax\njl 1259 \nmov -0x41c(%rbp),%eax\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 1361 \ncallq 10a0 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 430h\nmov [rbp+s], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rdx, [rbp+var_410]\nmov eax, 0\nmov ecx, 80h\nmov rdi, rdx\nrep stosq\nmov [rbp+var_2EC], 1\nmov [rbp+var_2B8], 5\nmov [rbp+var_2B0], 0Ah\nmov [rbp+var_2E0], 32h ; '2'\nmov [rbp+var_304], 64h ; 'd'\nmov [rbp+var_300], 1F4h\nmov [rbp+var_2DC], 3E8h\nmov [rbp+var_41C], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_414], eax\nmov [rbp+var_418], 0\njmp loc_1336\nloc_1259:\ncmp [rbp+var_418], 0\njle loc_1307\nmov eax, [rbp+var_418]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\ncdqe\nmov edx, [rbp+rax*4+var_410]\nmov eax, [rbp+var_418]\ncdqe\nlea rcx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\ncdqe\nmov eax, [rbp+rax*4+var_410]\ncmp edx, eax\njle short loc_1307\nmov eax, [rbp+var_418]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\ncdqe\nmov ecx, [rbp+rax*4+var_410]\nmov eax, [rbp+var_418]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\ncdqe\nmov eax, [rbp+rax*4+var_410]\nlea edx, [rax+rax]\nmov eax, ecx\nsub eax, edx\nadd [rbp+var_41C], eax\njmp short loc_132F\nloc_1307:\nmov eax, [rbp+var_418]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\ncdqe\nmov eax, [rbp+rax*4+var_410]\nadd [rbp+var_41C], eax\nloc_132F:\nadd [rbp+var_418], 1\nloc_1336:\nmov eax, [rbp+var_418]\ncmp eax, [rbp+var_414]\njl loc_1259\nmov eax, [rbp+var_41C]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1362\ncall ___stack_chk_fail\nlocret_1362:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(const char *a1)\n{\n unsigned int v2; // [rsp+14h] [rbp-41Ch]\n int i; // [rsp+18h] [rbp-418h]\n int v4; // [rsp+1Ch] [rbp-414h]\n _DWORD v5[258]; // [rsp+20h] [rbp-410h] BYREF\n unsigned __int64 v6; // [rsp+428h] [rbp-8h]\n\n v6 = __readfsqword(0x28u);\n memset(v5, 0, 0x400uLL);\n v5[73] = 1;\n v5[86] = 5;\n v5[88] = 10;\n v5[76] = 50;\n v5[67] = 100;\n v5[68] = 500;\n v5[77] = 1000;\n v2 = 0;\n v4 = strlen(a1);\n for ( i = 0; i < v4; ++i )\n {\n if ( i <= 0 || v5[a1[i]] <= v5[a1[i - 1]] )\n v2 += v5[a1[i]];\n else\n v2 += v5[a1[i]] - 2 * v5[a1[i - 1]];\n }\n return v2;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 430h\nmov [rbp+s], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nlea rdx, [rbp+var_410]\nmov eax, 0\nmov ecx, 80h\nmov rdi, rdx\nrep stosq\nmov [rbp+var_2EC], 1\nmov [rbp+var_2B8], 5\nmov [rbp+var_2B0], 0Ah\nmov [rbp+var_2E0], 32h ; '2'\nmov [rbp+var_304], 64h ; 'd'\nmov [rbp+var_300], 1F4h\nmov [rbp+var_2DC], 3E8h\nmov [rbp+var_41C], 0\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_414], eax\nmov [rbp+var_418], 0\njmp loc_1336\nloc_1259:\ncmp [rbp+var_418], 0\njle loc_1307\nmov eax, [rbp+var_418]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\ncdqe\nmov edx, [rbp+rax*4+var_410]\nmov eax, [rbp+var_418]\ncdqe\nlea rcx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rcx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\ncdqe\nmov eax, [rbp+rax*4+var_410]\ncmp edx, eax\njle short loc_1307\nmov eax, [rbp+var_418]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\ncdqe\nmov ecx, [rbp+rax*4+var_410]\nmov eax, [rbp+var_418]\ncdqe\nlea rdx, [rax-1]\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\ncdqe\nmov eax, [rbp+rax*4+var_410]\nlea edx, [rax+rax]\nmov eax, ecx\nsub eax, edx\nadd [rbp+var_41C], eax\njmp short loc_132F\nloc_1307:\nmov eax, [rbp+var_418]\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\ncdqe\nmov eax, [rbp+rax*4+var_410]\nadd [rbp+var_41C], eax\nloc_132F:\nadd [rbp+var_418], 1\nloc_1336:\nmov eax, [rbp+var_418]\ncmp eax, [rbp+var_414]\njl loc_1259\nmov eax, [rbp+var_41C]\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1362\ncall ___stack_chk_fail\nlocret_1362:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(const char *a1)\n{\n unsigned int v2; // [rsp+14h] [rbp-41Ch]\n int i; // [rsp+18h] [rbp-418h]\n int v4; // [rsp+1Ch] [rbp-414h]\n _DWORD v5[258]; // [rsp+20h] [rbp-410h] BYREF\n unsigned __int64 v6; // [rsp+428h] [rbp-8h]\n\n v6 = __readfsqword(0x28u);\n memset(v5, 0, 0x400uLL);\n v5[73] = 1;\n v5[86] = 5;\n v5[88] = 10;\n v5[76] = 50;\n v5[67] = 100;\n v5[68] = 500;\n v5[77] = 1000;\n v2 = 0;\n v4 = strlen(a1);\n for ( i = 0; i < v4; ++i )\n {\n if ( i <= 0 || v5[a1[i]] <= v5[a1[i - 1]] )\n v2 += v5[a1[i]];\n else\n v2 += v5[a1[i]] - 2 * v5[a1[i - 1]];\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(const char *a1) {\n unsigned int v2;\n int i;\n int v4;\n uint32_t v5[258];\n unsigned long long v6;\n v6 = __readfsqword(40u);\n memset(v5, 0, 1024uLL);\n v5[73] = 1;\n v5[86] = 5;\n v5[88] = 10;\n v5[76] = 50;\n v5[67] = 100;\n v5[68] = 500;\n v5[77] = 1000;\n v2 = 0;\n v4 = strlen(a1);\n for (i = 0; i < v4; ++i) {\n if (i <= 0 || v5[a1[i]] <= v5[a1[i - 1]])\n v2 += v5[a1[i]];\n else\n v2 += v5[a1[i]] - 2 * v5[a1[i - 1]];\n }\n return v2;\n}", + "ida_pseudo_norm": "long long func0(const char *a1) {\n unsigned int v2;\n int i;\n int v4;\n uint32_t v5[258];\n unsigned long long v6;\n v6 = __readfsqword(40u);\n memset(v5, 0, 1024uLL);\n v5[73] = 1;\n v5[86] = 5;\n v5[88] = 10;\n v5[76] = 50;\n v5[67] = 100;\n v5[68] = 500;\n v5[77] = 1000;\n v2 = 0;\n v4 = strlen(a1);\n for (i = 0; i < v4; ++i) {\n if (i <= 0 || v5[a1[i]] <= v5[a1[i - 1]])\n v2 += v5[a1[i]];\n else\n v2 += v5[a1[i]] - 2 * v5[a1[i - 1]];\n }\n return v2;\n}" + }, + { + "index": 961, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char *s) {\n int rom_val[256] = {0};\n rom_val['I'] = 1;\n rom_val['V'] = 5;\n rom_val['X'] = 10;\n rom_val['L'] = 50;\n rom_val['C'] = 100;\n rom_val['D'] = 500;\n rom_val['M'] = 1000;\n int int_val = 0;\n int len = strlen(s);\n for (int i = 0; i < len; i++) {\n if (i > 0 && rom_val[s[i]] > rom_val[s[i - 1]]) {\n int_val += rom_val[s[i]] - 2 * rom_val[s[i - 1]];\n } else {\n int_val += rom_val[s[i]];\n }\n }\n return int_val;\n}", + "test": "int main() {\n\n assert(func0(\"MMMCMLXXXVI\") == 3986);\n\n assert(func0(\"MMMM\") == 4000);\n\n assert(func0(\"C\") == 100);\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x418,%rsp\nmov %rdi,%rdx\nmov %fs:0x28,%rax\nmov %rax,0x408(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nmov $0x80,%ecx\nrep stos %rax,%es:(%rdi)\nmovl $0x1,0x124(%rsp)\nmovl $0x5,0x158(%rsp)\nmovl $0xa,0x160(%rsp)\nmovl $0x32,0x130(%rsp)\nmovl $0x64,0x10c(%rsp)\nmovl $0x1f4,0x110(%rsp)\nmovl $0x3e8,0x134(%rsp)\nmov $0xffffffffffffffff,%rcx\nmov %rdx,%rdi\nrepnz scas %es:(%rdi),%al\nnot %rcx\nsub $0x1,%rcx\ntest %ecx,%ecx\njle 125e \nlea -0x1(%rcx),%r8d\nmov $0x0,%eax\nmov $0x0,%edi\njmp 123d \nmovsbq (%rdx,%rax,1),%rcx\nadd (%rsp,%rcx,4),%edi\nlea 0x1(%rax),%rcx\ncmp %r8,%rax\nje 1263 \nmov %rcx,%rax\ntest %eax,%eax\njle 1229 \nmovsbq (%rdx,%rax,1),%rcx\nmov (%rsp,%rcx,4),%ecx\nmovsbq -0x1(%rdx,%rax,1),%rsi\nmov (%rsp,%rsi,4),%esi\ncmp %esi,%ecx\njle 1229 \nadd %esi,%esi\nsub %esi,%ecx\nadd %ecx,%edi\njmp 1231 \nmov $0x0,%edi\nmov 0x408(%rsp),%rax\nxor %fs:0x28,%rax\njne 1280 \nmov %edi,%eax\nadd $0x418,%rsp\nretq\ncallq 1080 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbx\nsub rsp, 410h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+418h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nmov ecx, 80h\nrep stosq\nmov [rsp+418h+var_2F4], 1\nmov [rsp+418h+var_2C0], 5\nmov [rsp+418h+var_2B8], 0Ah\nmov [rsp+418h+var_2E8], 32h ; '2'\nmov [rsp+418h+var_30C], 64h ; 'd'\nmov [rsp+418h+var_308], 1F4h\nmov [rsp+418h+var_2E4], 3E8h\nmov rdi, rbx; s\ncall _strlen\ntest eax, eax\njle short loc_1273\nlea edi, [rax-1]\nmov eax, 0\nmov esi, 0\njmp short loc_1252\nloc_123E:\nmovsx rdx, byte ptr [rbx+rax]\nadd esi, [rsp+rdx*4+418h+var_418]\nloc_1246:\nlea rdx, [rax+1]\ncmp rax, rdi\njz short loc_1278\nmov rax, rdx\nloc_1252:\ntest eax, eax\njle short loc_123E\nmovsx rdx, byte ptr [rbx+rax]\nmov edx, [rsp+rdx*4+418h+var_418]\nmovsx rcx, byte ptr [rbx+rax-1]\nmov ecx, [rsp+rcx*4+418h+var_418]\ncmp edx, ecx\njle short loc_123E\nadd ecx, ecx\nsub edx, ecx\nadd esi, edx\njmp short loc_1246\nloc_1273:\nmov esi, 0\nloc_1278:\nmov rax, [rsp+418h+var_10]\nsub rax, fs:28h\njnz short loc_1296\nmov eax, esi\nadd rsp, 410h\npop rbx\nretn\nloc_1296:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(char *s)\n{\n int v2; // eax\n __int64 v3; // rdi\n __int64 v4; // rax\n unsigned int v5; // esi\n int v6; // edx\n int v7; // ecx\n _DWORD v9[258]; // [rsp+0h] [rbp-418h] BYREF\n unsigned __int64 v10; // [rsp+408h] [rbp-10h]\n\n v10 = __readfsqword(0x28u);\n memset(v9, 0, 0x400uLL);\n v9[73] = 1;\n v9[86] = 5;\n v9[88] = 10;\n v9[76] = 50;\n v9[67] = 100;\n v9[68] = 500;\n v9[77] = 1000;\n v2 = strlen(s);\n if ( v2 <= 0 )\n {\n return 0;\n }\n else\n {\n v3 = (unsigned int)(v2 - 1);\n v4 = 0LL;\n v5 = 0;\n while ( 1 )\n {\n if ( (int)v4 <= 0 || (v6 = v9[s[v4]], v7 = v9[s[v4 - 1]], v6 <= v7) )\n v5 += v9[s[v4]];\n else\n v5 += v6 - 2 * v7;\n if ( v4 == v3 )\n break;\n ++v4;\n }\n }\n return v5;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbx\nsub rsp, 410h\nmov rbx, rdi\nmov rax, fs:28h\nmov [rsp+418h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nmov ecx, 80h\nrep stosq\nmov [rsp+418h+var_2F4], 1\nmov [rsp+418h+var_2C0], 5\nmov [rsp+418h+var_2B8], 0Ah\nmov [rsp+418h+var_2E8], 32h ; '2'\nmov [rsp+418h+var_30C], 64h ; 'd'\nmov [rsp+418h+var_308], 1F4h\nmov [rsp+418h+var_2E4], 3E8h\nmov rdi, rbx; s\ncall _strlen\ntest eax, eax\njle short loc_1273\nlea edi, [rax-1]\nmov eax, 0\nmov esi, 0\njmp short loc_1252\nloc_123E:\nmovsx rdx, byte ptr [rbx+rax]\nadd esi, [rsp+rdx*4+418h+var_418]\nloc_1246:\nlea rdx, [rax+1]\ncmp rax, rdi\njz short loc_1278\nmov rax, rdx\nloc_1252:\ntest eax, eax\njle short loc_123E\nmovsx rdx, byte ptr [rbx+rax]\nmov edx, [rsp+rdx*4+418h+var_418]\nmovsx rcx, byte ptr [rbx+rax-1]\nmov ecx, [rsp+rcx*4+418h+var_418]\ncmp edx, ecx\njle short loc_123E\nadd ecx, ecx\nsub edx, ecx\nadd esi, edx\njmp short loc_1246\nloc_1273:\nmov esi, 0\nloc_1278:\nmov rax, [rsp+418h+var_10]\nsub rax, fs:28h\njnz short loc_1296\nmov eax, esi\nadd rsp, 410h\npop rbx\nretn\nloc_1296:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_11A9(char *s)\n{\n int v2; // eax\n __int64 v3; // rdi\n __int64 v4; // rax\n unsigned int v5; // esi\n int v6; // edx\n int v7; // ecx\n _DWORD v9[258]; // [rsp+0h] [rbp-418h] BYREF\n unsigned __int64 v10; // [rsp+408h] [rbp-10h]\n\n v10 = __readfsqword(0x28u);\n memset(v9, 0, 0x400uLL);\n v9[73] = 1;\n v9[86] = 5;\n v9[88] = 10;\n v9[76] = 50;\n v9[67] = 100;\n v9[68] = 500;\n v9[77] = 1000;\n v2 = strlen(s);\n if ( v2 <= 0 )\n {\n return 0;\n }\n else\n {\n v3 = (unsigned int)(v2 - 1);\n v4 = 0LL;\n v5 = 0;\n while ( 1 )\n {\n if ( (int)v4 <= 0 || (v6 = v9[s[v4]], v7 = v9[s[v4 - 1]], v6 <= v7) )\n v5 += v9[s[v4]];\n else\n v5 += v6 - 2 * v7;\n if ( v4 == v3 )\n break;\n ++v4;\n }\n }\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11A9(char *s) {\n int v2;\n long long v3;\n long long v4;\n unsigned int v5;\n int v6;\n int v7;\n uint32_t v9[258];\n unsigned long long v10;\n v10 = __readfsqword(40u);\n memset(v9, 0, 1024uLL);\n v9[73] = 1;\n v9[86] = 5;\n v9[88] = 10;\n v9[76] = 50;\n v9[67] = 100;\n v9[68] = 500;\n v9[77] = 1000;\n v2 = strlen(s);\n if (v2 <= 0) {\n return 0;\n } else {\n v3 = (unsigned int)(v2 - 1);\n v4 = 0LL;\n v5 = 0;\n while (1) {\n if ((int)v4 <= 0 || (v6 = v9[s[v4]], v7 = v9[s[v4 - 1]], v6 <= v7))\n v5 += v9[s[v4]];\n else\n v5 += v6 - 2 * v7;\n if (v4 == v3) break;\n ++v4;\n }\n }\n return v5;\n}", + "ida_pseudo_norm": "long long func0(char *s) {\n int v2;\n long long v3;\n long long v4;\n unsigned int v5;\n int v6;\n int v7;\n uint32_t v9[258];\n unsigned long long v10;\n v10 = __readfsqword(40u);\n memset(v9, 0, 1024uLL);\n v9[73] = 1;\n v9[86] = 5;\n v9[88] = 10;\n v9[76] = 50;\n v9[67] = 100;\n v9[68] = 500;\n v9[77] = 1000;\n v2 = strlen(s);\n if (v2 <= 0) {\n return 0;\n } else {\n v3 = (unsigned int)(v2 - 1);\n v4 = 0LL;\n v5 = 0;\n while (1) {\n if ((int)v4 <= 0 || (v6 = v9[s[v4]], v7 = v9[s[v4 - 1]], v6 <= v7))\n v5 += v9[s[v4]];\n else\n v5 += v6 - 2 * v7;\n if (v4 == v3) break;\n ++v4;\n }\n }\n return v5;\n}" + }, + { + "index": 961, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char *s) {\n int rom_val[256] = {0};\n rom_val['I'] = 1;\n rom_val['V'] = 5;\n rom_val['X'] = 10;\n rom_val['L'] = 50;\n rom_val['C'] = 100;\n rom_val['D'] = 500;\n rom_val['M'] = 1000;\n int int_val = 0;\n int len = strlen(s);\n for (int i = 0; i < len; i++) {\n if (i > 0 && rom_val[s[i]] > rom_val[s[i - 1]]) {\n int_val += rom_val[s[i]] - 2 * rom_val[s[i - 1]];\n } else {\n int_val += rom_val[s[i]];\n }\n }\n return int_val;\n}", + "test": "int main() {\n\n assert(func0(\"MMMCMLXXXVI\") == 3986);\n\n assert(func0(\"MMMM\") == 4000);\n\n assert(func0(\"C\") == 100);\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov $0x80,%ecx\nmov %rdi,%rbx\nsub $0x410,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x408(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nrep stos %rax,%es:(%rdi)\nmov %rbx,%rdi\nmovabs $0x1f400000064,%rax\nmovl $0x1,0x124(%rsp)\nmov %rax,0x10c(%rsp)\nmovabs $0x3e800000032,%rax\nmovl $0x5,0x158(%rsp)\nmovl $0xa,0x160(%rsp)\nmov %rax,0x130(%rsp)\ncallq 1090 \ntest %eax,%eax\njle 1350 \nlea -0x1(%rax),%edi\nxor %r8d,%r8d\nxor %eax,%eax\njmp 131b \nnopl 0x0(%rax,%rax,1)\nmovsbq (%rbx,%rax,1),%rcx\nmovsbq -0x1(%rbx,%rax,1),%rsi\nmov %rcx,%rdx\nmov (%rsp,%rsi,4),%esi\nmov (%rsp,%rcx,4),%ecx\ncmp %esi,%ecx\njle 1324 \nadd %esi,%esi\nlea 0x1(%rax),%rdx\nsub %esi,%ecx\nadd %ecx,%r8d\ncmp %rax,%rdi\nje 1331 \nmov %rdx,%rax\ntest %rax,%rax\njne 12f0 \nmovsbq (%rbx),%rdx\nadd (%rsp,%rdx,4),%r8d\nlea 0x1(%rax),%rdx\ncmp %rax,%rdi\njne 1318 \nmov 0x408(%rsp),%rax\nxor %fs:0x28,%rax\njne 1355 \nadd $0x410,%rsp\nmov %r8d,%eax\npop %rbx\nretq\nxor %r8d,%r8d\njmp 1331 \ncallq 10a0 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov ecx, 80h\nmov rbx, rdi\nsub rsp, 410h\nmov rax, fs:28h\nmov [rsp+418h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\nmov rax, cs:qword_20A8\nmov rdi, rbx; s\nmov [rsp+418h+var_2F4], 1\nmov [rsp+418h+var_2C0], 5\nmov [rsp+418h+var_30C], rax\nmov rax, cs:qword_20B0\nmov [rsp+418h+var_2B8], 0Ah\nmov [rsp+418h+var_2E8], rax\ncall _strlen\ntest eax, eax\njle short loc_1348\nlea r8d, [rax-1]\nxor ecx, ecx\nxor eax, eax\njmp short loc_1312\nloc_12E8:\nmovsx rsi, byte ptr [rbx+rax]\nmovsx rdi, byte ptr [rbx+rax-1]\nmov rdx, rsi\nmov edi, [rsp+rdi*4+418h+var_418]\nmov esi, [rsp+rsi*4+418h+var_418]\ncmp esi, edi\njle short loc_131B\nadd edi, edi\nlea rdx, [rax+1]\nsub esi, edi\nadd ecx, esi\ncmp r8, rax\njz short loc_1327\nloc_130F:\nmov rax, rdx\nloc_1312:\ntest rax, rax\njnz short loc_12E8\nmovsx rdx, byte ptr [rbx]\nloc_131B:\nadd ecx, [rsp+rdx*4+418h+var_418]\nlea rdx, [rax+1]\ncmp r8, rax\njnz short loc_130F\nloc_1327:\nmov rax, [rsp+418h+var_10]\nsub rax, fs:28h\njnz short loc_134C\nadd rsp, 410h\nmov eax, ecx\npop rbx\nretn\nloc_1348:\nxor ecx, ecx\njmp short loc_1327\nloc_134C:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(char *s)\n{\n int v2; // eax\n __int64 v3; // r8\n unsigned int v4; // ecx\n __int64 i; // rax\n __int64 v6; // rdx\n int v7; // edi\n int v8; // esi\n __int64 v9; // rdx\n _QWORD v11[131]; // [rsp+0h] [rbp-418h] BYREF\n\n v11[129] = __readfsqword(0x28u);\n memset(v11, 0, 0x400uLL);\n HIDWORD(v11[36]) = 1;\n LODWORD(v11[43]) = 5;\n *(_QWORD *)((char *)&v11[33] + 4) = 0x1F400000064LL;\n LODWORD(v11[44]) = 10;\n v11[38] = 0x3E800000032LL;\n v2 = strlen(s);\n if ( v2 > 0 )\n {\n v3 = (unsigned int)(v2 - 1);\n v4 = 0;\n for ( i = 0LL; ; i = v9 )\n {\n if ( i )\n {\n v6 = s[i];\n v7 = *((_DWORD *)v11 + s[i - 1]);\n v8 = *((_DWORD *)v11 + v6);\n if ( v8 > v7 )\n {\n v9 = i + 1;\n v4 += v8 - 2 * v7;\n if ( v3 == i )\n return v4;\n continue;\n }\n }\n else\n {\n v6 = *s;\n }\n v4 += *((_DWORD *)v11 + v6);\n v9 = i + 1;\n if ( v3 == i )\n return v4;\n }\n }\n return 0;\n}", + "ida_strip_asm": "sub_1260:\nendbr64\npush rbx\nmov ecx, 80h\nmov rbx, rdi\nsub rsp, 410h\nmov rax, fs:28h\nmov [rsp+418h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\nmov rax, cs:qword_20A8\nmov rdi, rbx; s\nmov [rsp+418h+var_2F4], 1\nmov [rsp+418h+var_2C0], 5\nmov [rsp+418h+var_30C], rax\nmov rax, cs:qword_20B0\nmov [rsp+418h+var_2B8], 0Ah\nmov [rsp+418h+var_2E8], rax\ncall _strlen\ntest eax, eax\njle short loc_1348\nlea r8d, [rax-1]\nxor ecx, ecx\nxor eax, eax\njmp short loc_1312\nloc_12E8:\nmovsx rsi, byte ptr [rbx+rax]\nmovsx rdi, byte ptr [rbx+rax-1]\nmov rdx, rsi\nmov edi, [rsp+rdi*4+418h+var_418]\nmov esi, [rsp+rsi*4+418h+var_418]\ncmp esi, edi\njle short loc_131B\nadd edi, edi\nlea rdx, [rax+1]\nsub esi, edi\nadd ecx, esi\ncmp r8, rax\njz short loc_1327\nloc_130F:\nmov rax, rdx\nloc_1312:\ntest rax, rax\njnz short loc_12E8\nmovsx rdx, byte ptr [rbx]\nloc_131B:\nadd ecx, [rsp+rdx*4+418h+var_418]\nlea rdx, [rax+1]\ncmp r8, rax\njnz short loc_130F\nloc_1327:\nmov rax, [rsp+418h+var_10]\nsub rax, fs:28h\njnz short loc_134C\nadd rsp, 410h\nmov eax, ecx\npop rbx\nretn\nloc_1348:\nxor ecx, ecx\njmp short loc_1327\nloc_134C:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1260(char *s)\n{\n int v2; // eax\n __int64 v3; // r8\n unsigned int v4; // ecx\n __int64 i; // rax\n __int64 v6; // rdx\n int v7; // edi\n int v8; // esi\n __int64 v9; // rdx\n _QWORD v11[131]; // [rsp+0h] [rbp-418h] BYREF\n\n v11[129] = __readfsqword(0x28u);\n memset(v11, 0, 0x400uLL);\n HIDWORD(v11[36]) = 1;\n LODWORD(v11[43]) = 5;\n *(_QWORD *)((char *)&v11[33] + 4) = 0x1F400000064LL;\n LODWORD(v11[44]) = 10;\n v11[38] = 0x3E800000032LL;\n v2 = strlen(s);\n if ( v2 > 0 )\n {\n v3 = (unsigned int)(v2 - 1);\n v4 = 0;\n for ( i = 0LL; ; i = v9 )\n {\n if ( i )\n {\n v6 = s[i];\n v7 = *((_DWORD *)v11 + s[i - 1]);\n v8 = *((_DWORD *)v11 + v6);\n if ( v8 > v7 )\n {\n v9 = i + 1;\n v4 += v8 - 2 * v7;\n if ( v3 == i )\n return v4;\n continue;\n }\n }\n else\n {\n v6 = *s;\n }\n v4 += *((_DWORD *)v11 + v6);\n v9 = i + 1;\n if ( v3 == i )\n return v4;\n }\n }\n return 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1260(char *s) {\n int v2;\n long long v3;\n unsigned int v4;\n long long i;\n long long v6;\n int v7;\n int v8;\n long long v9;\n uint64_t v11[131];\n v11[129] = __readfsqword(40u);\n memset(v11, 0, 1024uLL);\n HIDWORD(v11[36]) = 1;\n LODWORD(v11[43]) = 5;\n *(uint64_t *)((char *)&v11[33] + 4) = 2147483648100LL;\n LODWORD(v11[44]) = 10;\n v11[38] = 4294967296050LL;\n v2 = strlen(s);\n if (v2 > 0) {\n v3 = (unsigned int)(v2 - 1);\n v4 = 0;\n for (i = 0LL;; i = v9) {\n if (i) {\n v6 = s[i];\n v7 = *((uint32_t *)v11 + s[i - 1]);\n v8 = *((uint32_t *)v11 + v6);\n if (v8 > v7) {\n v9 = i + 1;\n v4 += v8 - 2 * v7;\n if (v3 == i) return v4;\n continue;\n }\n } else {\n v6 = *s;\n }\n v4 += *((uint32_t *)v11 + v6);\n v9 = i + 1;\n if (v3 == i) return v4;\n }\n }\n return 0;\n}", + "ida_pseudo_norm": "long long func0(char *s) {\n int v2;\n long long v3;\n unsigned int v4;\n long long i;\n long long v6;\n int v7;\n int v8;\n long long v9;\n uint64_t v11[131];\n v11[129] = __readfsqword(40u);\n memset(v11, 0, 1024uLL);\n HIDWORD(v11[36]) = 1;\n LODWORD(v11[43]) = 5;\n *(uint64_t *)((char *)&v11[33] + 4) = 2147483648100LL;\n LODWORD(v11[44]) = 10;\n v11[38] = 4294967296050LL;\n v2 = strlen(s);\n if (v2 > 0) {\n v3 = (unsigned int)(v2 - 1);\n v4 = 0;\n for (i = 0LL;; i = v9) {\n if (i) {\n v6 = s[i];\n v7 = *((uint32_t *)v11 + s[i - 1]);\n v8 = *((uint32_t *)v11 + v6);\n if (v8 > v7) {\n v9 = i + 1;\n v4 += v8 - 2 * v7;\n if (v3 == i) return v4;\n continue;\n }\n } else {\n v6 = *s;\n }\n v4 += *((uint32_t *)v11 + v6);\n v9 = i + 1;\n if (v3 == i) return v4;\n }\n }\n return 0;\n}" + }, + { + "index": 961, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char *s) {\n int rom_val[256] = {0};\n rom_val['I'] = 1;\n rom_val['V'] = 5;\n rom_val['X'] = 10;\n rom_val['L'] = 50;\n rom_val['C'] = 100;\n rom_val['D'] = 500;\n rom_val['M'] = 1000;\n int int_val = 0;\n int len = strlen(s);\n for (int i = 0; i < len; i++) {\n if (i > 0 && rom_val[s[i]] > rom_val[s[i - 1]]) {\n int_val += rom_val[s[i]] - 2 * rom_val[s[i - 1]];\n } else {\n int_val += rom_val[s[i]];\n }\n }\n return int_val;\n}", + "test": "int main() {\n\n assert(func0(\"MMMCMLXXXVI\") == 3986);\n\n assert(func0(\"MMMM\") == 4000);\n\n assert(func0(\"C\") == 100);\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbx\nmov $0x80,%ecx\nmov %rdi,%rbx\nsub $0x410,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x408(%rsp)\nxor %eax,%eax\nmov %rsp,%rdi\nrep stos %rax,%es:(%rdi)\nmov %rbx,%rdi\nmovabs $0x1f400000064,%rax\nmovl $0x1,0x124(%rsp)\nmov %rax,0x10c(%rsp)\nmovabs $0x3e800000032,%rax\nmovl $0x5,0x158(%rsp)\nmovl $0xa,0x160(%rsp)\nmov %rax,0x130(%rsp)\ncallq 1090 \ntest %eax,%eax\njle 1350 \nlea -0x1(%rax),%edi\nxor %r8d,%r8d\nxor %eax,%eax\njmp 131b \nnopl 0x0(%rax,%rax,1)\nmovsbq (%rbx,%rax,1),%rcx\nmovsbq -0x1(%rbx,%rax,1),%rsi\nmov %rcx,%rdx\nmov (%rsp,%rsi,4),%esi\nmov (%rsp,%rcx,4),%ecx\ncmp %esi,%ecx\njle 1324 \nadd %esi,%esi\nlea 0x1(%rax),%rdx\nsub %esi,%ecx\nadd %ecx,%r8d\ncmp %rdi,%rax\nje 1331 \nmov %rdx,%rax\ntest %rax,%rax\njne 12f0 \nmovsbq (%rbx),%rdx\nadd (%rsp,%rdx,4),%r8d\nlea 0x1(%rax),%rdx\ncmp %rdi,%rax\njne 1318 \nmov 0x408(%rsp),%rax\nxor %fs:0x28,%rax\njne 1355 \nadd $0x410,%rsp\nmov %r8d,%eax\npop %rbx\nretq\nxor %r8d,%r8d\njmp 1331 \ncallq 10a0 <__stack_chk_fail@plt>\nnopw 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbx\nmov ecx, 80h\nmov rbx, rdi\nsub rsp, 410h\nmov rax, fs:28h\nmov [rsp+418h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\nmov rax, cs:qword_20A8\nmov rdi, rbx; s\nmov [rsp+418h+var_2F4], 1\nmov [rsp+418h+var_2C0], 5\nmov [rsp+418h+var_30C], rax\nmov rax, cs:qword_20B0\nmov [rsp+418h+var_2B8], 0Ah\nmov [rsp+418h+var_2E8], rax\ncall _strlen\ntest eax, eax\njle short loc_1348\nlea r8d, [rax-1]\nxor ecx, ecx\nxor eax, eax\njmp short loc_1312\nloc_12E8:\nmovsx rsi, byte ptr [rbx+rax]\nmovsx rdi, byte ptr [rbx+rax-1]\nmov rdx, rsi\nmov edi, [rsp+rdi*4+418h+var_418]\nmov esi, [rsp+rsi*4+418h+var_418]\ncmp esi, edi\njle short loc_131B\nadd edi, edi\nlea rdx, [rax+1]\nsub esi, edi\nadd ecx, esi\ncmp rax, r8\njz short loc_1327\nloc_130F:\nmov rax, rdx\nloc_1312:\ntest rax, rax\njnz short loc_12E8\nmovsx rdx, byte ptr [rbx]\nloc_131B:\nadd ecx, [rsp+rdx*4+418h+var_418]\nlea rdx, [rax+1]\ncmp rax, r8\njnz short loc_130F\nloc_1327:\nmov rax, [rsp+418h+var_10]\nsub rax, fs:28h\njnz short loc_134C\nadd rsp, 410h\nmov eax, ecx\npop rbx\nretn\nloc_1348:\nxor ecx, ecx\njmp short loc_1327\nloc_134C:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(char *s)\n{\n int v2; // eax\n __int64 v3; // r8\n unsigned int v4; // ecx\n __int64 i; // rax\n __int64 v6; // rdx\n int v7; // edi\n int v8; // esi\n __int64 v9; // rdx\n _QWORD v11[131]; // [rsp+0h] [rbp-418h] BYREF\n\n v11[129] = __readfsqword(0x28u);\n memset(v11, 0, 0x400uLL);\n HIDWORD(v11[36]) = 1;\n LODWORD(v11[43]) = 5;\n *(_QWORD *)((char *)&v11[33] + 4) = 0x1F400000064LL;\n LODWORD(v11[44]) = 10;\n v11[38] = 0x3E800000032LL;\n v2 = strlen(s);\n if ( v2 > 0 )\n {\n v3 = (unsigned int)(v2 - 1);\n v4 = 0;\n for ( i = 0LL; ; i = v9 )\n {\n if ( i )\n {\n v6 = s[i];\n v7 = *((_DWORD *)v11 + s[i - 1]);\n v8 = *((_DWORD *)v11 + v6);\n if ( v8 > v7 )\n {\n v9 = i + 1;\n v4 += v8 - 2 * v7;\n if ( i == v3 )\n return v4;\n continue;\n }\n }\n else\n {\n v6 = *s;\n }\n v4 += *((_DWORD *)v11 + v6);\n v9 = i + 1;\n if ( i == v3 )\n return v4;\n }\n }\n return 0;\n}", + "ida_strip_asm": "sub_1260:\nendbr64\npush rbx\nmov ecx, 80h\nmov rbx, rdi\nsub rsp, 410h\nmov rax, fs:28h\nmov [rsp+418h+var_10], rax\nxor eax, eax\nmov rdi, rsp\nrep stosq\nmov rax, cs:qword_20A8\nmov rdi, rbx; s\nmov [rsp+418h+var_2F4], 1\nmov [rsp+418h+var_2C0], 5\nmov [rsp+418h+var_30C], rax\nmov rax, cs:qword_20B0\nmov [rsp+418h+var_2B8], 0Ah\nmov [rsp+418h+var_2E8], rax\ncall _strlen\ntest eax, eax\njle short loc_1348\nlea r8d, [rax-1]\nxor ecx, ecx\nxor eax, eax\njmp short loc_1312\nloc_12E8:\nmovsx rsi, byte ptr [rbx+rax]\nmovsx rdi, byte ptr [rbx+rax-1]\nmov rdx, rsi\nmov edi, [rsp+rdi*4+418h+var_418]\nmov esi, [rsp+rsi*4+418h+var_418]\ncmp esi, edi\njle short loc_131B\nadd edi, edi\nlea rdx, [rax+1]\nsub esi, edi\nadd ecx, esi\ncmp rax, r8\njz short loc_1327\nloc_130F:\nmov rax, rdx\nloc_1312:\ntest rax, rax\njnz short loc_12E8\nmovsx rdx, byte ptr [rbx]\nloc_131B:\nadd ecx, [rsp+rdx*4+418h+var_418]\nlea rdx, [rax+1]\ncmp rax, r8\njnz short loc_130F\nloc_1327:\nmov rax, [rsp+418h+var_10]\nsub rax, fs:28h\njnz short loc_134C\nadd rsp, 410h\nmov eax, ecx\npop rbx\nretn\nloc_1348:\nxor ecx, ecx\njmp short loc_1327\nloc_134C:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1260(char *s)\n{\n int v2; // eax\n __int64 v3; // r8\n unsigned int v4; // ecx\n __int64 i; // rax\n __int64 v6; // rdx\n int v7; // edi\n int v8; // esi\n __int64 v9; // rdx\n _QWORD v11[131]; // [rsp+0h] [rbp-418h] BYREF\n\n v11[129] = __readfsqword(0x28u);\n memset(v11, 0, 0x400uLL);\n HIDWORD(v11[36]) = 1;\n LODWORD(v11[43]) = 5;\n *(_QWORD *)((char *)&v11[33] + 4) = 0x1F400000064LL;\n LODWORD(v11[44]) = 10;\n v11[38] = 0x3E800000032LL;\n v2 = strlen(s);\n if ( v2 > 0 )\n {\n v3 = (unsigned int)(v2 - 1);\n v4 = 0;\n for ( i = 0LL; ; i = v9 )\n {\n if ( i )\n {\n v6 = s[i];\n v7 = *((_DWORD *)v11 + s[i - 1]);\n v8 = *((_DWORD *)v11 + v6);\n if ( v8 > v7 )\n {\n v9 = i + 1;\n v4 += v8 - 2 * v7;\n if ( i == v3 )\n return v4;\n continue;\n }\n }\n else\n {\n v6 = *s;\n }\n v4 += *((_DWORD *)v11 + v6);\n v9 = i + 1;\n if ( i == v3 )\n return v4;\n }\n }\n return 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1260(char *s) {\n int v2;\n long long v3;\n unsigned int v4;\n long long i;\n long long v6;\n int v7;\n int v8;\n long long v9;\n uint64_t v11[131];\n v11[129] = __readfsqword(40u);\n memset(v11, 0, 1024uLL);\n HIDWORD(v11[36]) = 1;\n LODWORD(v11[43]) = 5;\n *(uint64_t *)((char *)&v11[33] + 4) = 2147483648100LL;\n LODWORD(v11[44]) = 10;\n v11[38] = 4294967296050LL;\n v2 = strlen(s);\n if (v2 > 0) {\n v3 = (unsigned int)(v2 - 1);\n v4 = 0;\n for (i = 0LL;; i = v9) {\n if (i) {\n v6 = s[i];\n v7 = *((uint32_t *)v11 + s[i - 1]);\n v8 = *((uint32_t *)v11 + v6);\n if (v8 > v7) {\n v9 = i + 1;\n v4 += v8 - 2 * v7;\n if (i == v3) return v4;\n continue;\n }\n } else {\n v6 = *s;\n }\n v4 += *((uint32_t *)v11 + v6);\n v9 = i + 1;\n if (i == v3) return v4;\n }\n }\n return 0;\n}", + "ida_pseudo_norm": "long long func0(char *s) {\n int v2;\n long long v3;\n unsigned int v4;\n long long i;\n long long v6;\n int v7;\n int v8;\n long long v9;\n uint64_t v11[131];\n v11[129] = __readfsqword(40u);\n memset(v11, 0, 1024uLL);\n HIDWORD(v11[36]) = 1;\n LODWORD(v11[43]) = 5;\n *(uint64_t *)((char *)&v11[33] + 4) = 2147483648100LL;\n LODWORD(v11[44]) = 10;\n v11[38] = 4294967296050LL;\n v2 = strlen(s);\n if (v2 > 0) {\n v3 = (unsigned int)(v2 - 1);\n v4 = 0;\n for (i = 0LL;; i = v9) {\n if (i) {\n v6 = s[i];\n v7 = *((uint32_t *)v11 + s[i - 1]);\n v8 = *((uint32_t *)v11 + v6);\n if (v8 > v7) {\n v9 = i + 1;\n v4 += v8 - 2 * v7;\n if (i == v3) return v4;\n continue;\n }\n } else {\n v6 = *s;\n }\n v4 += *((uint32_t *)v11 + v6);\n v9 = i + 1;\n if (i == v3) return v4;\n }\n }\n return 0;\n}" + }, + { + "index": 962, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n\n\n", + "func": "int func0(int l, int r) {\n return r / 2 * (r / 2 + 1) - (l - 1) / 2 * (l + 1) / 2;\n}", + "test": "int main() {\n\n assert(func0(2, 5) == 6);\n\n assert(func0(3, 8) == 18);\n\n assert(func0(4, 6) == 10);\n\n \n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov %esi,-0x8(%rbp)\nmov -0x8(%rbp),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nmov %eax,%ecx\nmov -0x8(%rbp),%eax\nmov %eax,%edx\nshr $0x1f,%edx\nadd %edx,%eax\nsar %eax\nadd $0x1,%eax\nimul %eax,%ecx\nmov %ecx,%edx\nmov -0x4(%rbp),%eax\nsub $0x1,%eax\nmov %eax,%ecx\nshr $0x1f,%ecx\nadd %ecx,%eax\nsar %eax\nmov %eax,%ecx\nmov -0x4(%rbp),%eax\nadd $0x1,%eax\nimul %ecx,%eax\nmov %eax,%ecx\nshr $0x1f,%ecx\nadd %ecx,%eax\nsar %eax\nneg %eax\nadd %edx,%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov eax, [rbp+var_8]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov ecx, eax\nmov eax, [rbp+var_8]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nadd eax, 1\nimul ecx, eax\nmov edx, ecx\nmov eax, [rbp+var_4]\nsub eax, 1\nmov ecx, eax\nshr ecx, 1Fh\nadd eax, ecx\nsar eax, 1\nmov ecx, eax\nmov eax, [rbp+var_4]\nadd eax, 1\nimul eax, ecx\nmov ecx, eax\nshr ecx, 1Fh\nadd eax, ecx\nsar eax, 1\nneg eax\nadd eax, edx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2)\n{\n return (unsigned int)((a2 / 2 + 1) * (a2 / 2) + (a1 - 1) / 2 * (a1 + 1) / -2);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov eax, [rbp+var_8]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nmov ecx, eax\nmov eax, [rbp+var_8]\nmov edx, eax\nshr edx, 1Fh\nadd eax, edx\nsar eax, 1\nadd eax, 1\nimul ecx, eax\nmov edx, ecx\nmov eax, [rbp+var_4]\nsub eax, 1\nmov ecx, eax\nshr ecx, 1Fh\nadd eax, ecx\nsar eax, 1\nmov ecx, eax\nmov eax, [rbp+var_4]\nadd eax, 1\nimul eax, ecx\nmov ecx, eax\nshr ecx, 1Fh\nadd eax, ecx\nsar eax, 1\nneg eax\nadd eax, edx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2)\n{\n return (unsigned int)((a2 / 2 + 1) * (a2 / 2) + (a1 - 1) / 2 * (a1 + 1) / -2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2) {\n return (unsigned int)((a2 / 2 + 1) * (a2 / 2) + (a1 - 1) / 2 * (a1 + 1) / -2);\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2) {\n return (unsigned int)((a2 / 2 + 1) * (a2 / 2) + (a1 - 1) / 2 * (a1 + 1) / -2);\n}" + }, + { + "index": 963, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\ntypedef struct {\n\n char *description;\n\n int value;\n\n} Result;\n\n\n\n", + "func": "Result func0(int x, int y, int z) {\n int discriminant = (y * y) - (4 * x * z);\n Result result;\n if (discriminant > 0) {\n result.description = \"Two solutions\";\n result.value = discriminant;\n } else if (discriminant == 0) {\n result.description = \"one solution\";\n result.value = discriminant;\n } else {\n result.description = \"no real solution\";\n result.value = discriminant;\n }\n return result;\n}", + "test": "int main() {\n\n Result res;\n\n res = func0(4, 8, 2);\n\n assert(res.value == 32 && strcmp(res.description, \"Two solutions\") == 0);\n\n\n\n res = func0(5, 7, 9);\n\n assert(res.value == -131 && strcmp(res.description, \"no real solution\") == 0);\n\n \n\n res = func0(0, 0, 9);\n\n assert(res.value == 0 && strcmp(res.description, \"one solution\") == 0);\n\n \n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x24(%rbp)\nmov %esi,-0x28(%rbp)\nmov %edx,-0x2c(%rbp)\nmov -0x28(%rbp),%eax\nimul %eax,%eax\nmov %eax,%edx\nmov -0x24(%rbp),%eax\nimul -0x2c(%rbp),%eax\nshl $0x2,%eax\nsub %eax,%edx\nmov %edx,%eax\nmov %eax,-0x14(%rbp)\ncmpl $0x0,-0x14(%rbp)\njle 11ac \nlea 0xe68(%rip),%rax\nmov %rax,-0x10(%rbp)\nmov -0x14(%rbp),%eax\nmov %eax,-0x8(%rbp)\njmp 11d6 \ncmpl $0x0,-0x14(%rbp)\njne 11c5 \nlea 0xe5d(%rip),%rax\nmov %rax,-0x10(%rbp)\nmov -0x14(%rbp),%eax\nmov %eax,-0x8(%rbp)\njmp 11d6 \nlea 0xe57(%rip),%rax\nmov %rax,-0x10(%rbp)\nmov -0x14(%rbp),%eax\nmov %eax,-0x8(%rbp)\nmov -0x10(%rbp),%rax\nmov -0x8(%rbp),%rdx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_24], edi\nmov [rbp+var_28], esi\nmov [rbp+var_2C], edx\nmov eax, [rbp+var_28]\nimul eax, eax\nmov ecx, eax\nmov eax, [rbp+var_24]\nimul eax, [rbp+var_2C]\nlea edx, ds:0[rax*4]\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_14], eax\ncmp [rbp+var_14], 0\njle short loc_11B0\nlea rax, s2; \"Two solutions\"\nmov [rbp+var_10], rax\nmov eax, [rbp+var_14]\nmov dword ptr [rbp+var_8], eax\njmp short loc_11DA\nloc_11B0:\ncmp [rbp+var_14], 0\njnz short loc_11C9\nlea rax, aOneSolution; \"one solution\"\nmov [rbp+var_10], rax\nmov eax, [rbp+var_14]\nmov dword ptr [rbp+var_8], eax\njmp short loc_11DA\nloc_11C9:\nlea rax, aNoRealSolution; \"no real solution\"\nmov [rbp+var_10], rax\nmov eax, [rbp+var_14]\nmov dword ptr [rbp+var_8], eax\nloc_11DA:\nmov rax, [rbp+var_10]\nmov rdx, [rbp+var_8]\npop rbp\nretn", + "ida_pseudo": "const char *__fastcall func0(int a1, int a2, int a3)\n{\n int v4; // [rsp+18h] [rbp-14h]\n\n v4 = a2 * a2 - 4 * a3 * a1;\n if ( v4 > 0 )\n return \"Two solutions\";\n if ( v4 )\n return \"no real solution\";\n return \"one solution\";\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_24], edi\nmov [rbp+var_28], esi\nmov [rbp+var_2C], edx\nmov eax, [rbp+var_28]\nimul eax, eax\nmov ecx, eax\nmov eax, [rbp+var_24]\nimul eax, [rbp+var_2C]\nlea edx, ds:0[rax*4]\nmov eax, ecx\nsub eax, edx\nmov [rbp+var_14], eax\ncmp [rbp+var_14], 0\njle short loc_11B0\nlea rax, s2; \"Two solutions\"\nmov [rbp+var_10], rax\nmov eax, [rbp+var_14]\nmov dword ptr [rbp+var_8], eax\njmp short loc_11DA\nloc_11B0:\ncmp [rbp+var_14], 0\njnz short loc_11C9\nlea rax, aOneSolution; \"one solution\"\nmov [rbp+var_10], rax\nmov eax, [rbp+var_14]\nmov dword ptr [rbp+var_8], eax\njmp short loc_11DA\nloc_11C9:\nlea rax, aNoRealSolution; \"no real solution\"\nmov [rbp+var_10], rax\nmov eax, [rbp+var_14]\nmov dword ptr [rbp+var_8], eax\nloc_11DA:\nmov rax, [rbp+var_10]\nmov rdx, [rbp+var_8]\npop rbp\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1169(int a1, int a2, int a3)\n{\n int v4; // [rsp+18h] [rbp-14h]\n\n v4 = a2 * a2 - 4 * a3 * a1;\n if ( v4 > 0 )\n return \"Two solutions\";\n if ( v4 )\n return \"no real solution\";\n return \"one solution\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char* sub_1169(int a1, int a2, int a3) {\n int v4;\n v4 = a2 * a2 - 4 * a3 * a1;\n if (v4 > 0) return \"Two solutions\";\n if (v4) return \"no real solution\";\n return \"one solution\";\n}", + "ida_pseudo_norm": "const char* func0(int a1, int a2, int a3) {\n int v4;\n v4 = a2 * a2 - 4 * a3 * a1;\n if (v4 > 0) return \"Two solutions\";\n if (v4) return \"no real solution\";\n return \"one solution\";\n}" + }, + { + "index": 964, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char* s) {\n char* word = strtok(s, \" \");\n while (word != NULL) {\n if (strlen(word) % 2 == 0) {\n return 1;\n } else {\n return 0;\n }\n word = strtok(NULL, \" \");\n }\n return 0;\n}", + "test": "int main() {\n\n assert(func0(\"program\") == 0);\n\n assert(func0(\"solution\") == 1);\n\n assert(func0(\"data\") == 1);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov -0x18(%rbp),%rax\nlea 0xe64(%rip),%rsi\nmov %rax,%rdi\ncallq 1090 \nmov %rax,-0x8(%rbp)\ncmpq $0x0,-0x8(%rbp)\nje 11d9 \nmov -0x8(%rbp),%rax\nmov %rax,%rdi\ncallq 1070 \nand $0x1,%eax\ntest %rax,%rax\njne 11d2 \nmov $0x1,%eax\njmp 11de \nmov $0x0,%eax\njmp 11de \nmov $0x0,%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nlea rdx, delim; \" \"\nmov rsi, rdx; delim\nmov rdi, rax; s\ncall _strtok\nmov [rbp+var_8], rax\nnop\ncmp [rbp+var_8], 0\njz short loc_11DD\nmov rax, [rbp+var_8]\nmov rdi, rax; s\ncall _strlen\nand eax, 1\ntest rax, rax\njnz short loc_11D6\nmov eax, 1\njmp short locret_11E2\nloc_11D6:\nmov eax, 0\njmp short locret_11E2\nloc_11DD:\nmov eax, 0\nlocret_11E2:\nleave\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(char *a1)\n{\n const char *v2; // [rsp+18h] [rbp-8h]\n\n v2 = strtok(a1, \" \");\n return v2 && (strlen(v2) & 1) == 0;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov rax, [rbp+s]\nlea rdx, delim; \" \"\nmov rsi, rdx; delim\nmov rdi, rax; s\ncall _strtok\nmov [rbp+var_8], rax\nnop\ncmp [rbp+var_8], 0\njz short loc_11DD\nmov rax, [rbp+var_8]\nmov rdi, rax; s\ncall _strlen\nand eax, 1\ntest rax, rax\njnz short loc_11D6\nmov eax, 1\njmp short locret_11E2\nloc_11D6:\nmov eax, 0\njmp short locret_11E2\nloc_11DD:\nmov eax, 0\nlocret_11E2:\nleave\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1189(char *a1)\n{\n const char *v2; // [rsp+18h] [rbp-8h]\n\n v2 = strtok(a1, \" \");\n return v2 && (strlen(v2) & 1) == 0;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1189(char *a1) {\n const char *v2;\n v2 = strtok(a1, \" \");\n return v2 && (strlen(v2) & 1) == 0;\n}", + "ida_pseudo_norm": "uint8_t func0(char *a1) {\n const char *v2;\n v2 = strtok(a1, \" \");\n return v2 && (strlen(v2) & 1) == 0;\n}" + }, + { + "index": 964, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char* s) {\n char* word = strtok(s, \" \");\n while (word != NULL) {\n if (strlen(word) % 2 == 0) {\n return 1;\n } else {\n return 0;\n }\n word = strtok(NULL, \" \");\n }\n return 0;\n}", + "test": "int main() {\n\n assert(func0(\"program\") == 0);\n\n assert(func0(\"solution\") == 1);\n\n assert(func0(\"data\") == 1);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x8,%rsp\nlea 0xe8c(%rip),%rsi\ncallq 1070 \nmov %rax,%rdi\nmov $0x0,%eax\ntest %rdi,%rdi\nje 119c \nmov $0xffffffffffffffff,%rcx\nrepnz scas %es:(%rdi),%al\nmov %rcx,%rax\nnot %rax\nand $0x1,%eax\nadd $0x8,%rsp\nretq\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\nlea rsi, delim; \" \"\ncall _strtok\nmov rdi, rax; s\nmov eax, 0\ntest rdi, rdi\njz short loc_11B5\ncall _strlen\nnot rax\nand eax, 1\nloc_11B5:\nadd rsp, 8\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(char *a1)\n{\n char *v1; // rdi\n _BOOL8 result; // rax\n\n v1 = strtok(a1, \" \");\n result = 0LL;\n if ( v1 )\n return (strlen(v1) & 1) == 0;\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\nsub rsp, 8\nlea rsi, delim; \" \"\ncall _strtok\nmov rdi, rax; s\nmov eax, 0\ntest rdi, rdi\njz short loc_11B5\ncall _strlen\nnot rax\nand eax, 1\nloc_11B5:\nadd rsp, 8\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1189(char *a1)\n{\n char *v1; // rdi\n _BOOL8 result; // rax\n\n v1 = strtok(a1, \" \");\n result = 0LL;\n if ( v1 )\n return (strlen(v1) & 1) == 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1189(char *a1) {\n char *v1;\n uint8_t result;\n v1 = strtok(a1, \" \");\n result = 0LL;\n if (v1) return (strlen(v1) & 1) == 0;\n return result;\n}", + "ida_pseudo_norm": "uint8_t func0(char *a1) {\n char *v1;\n uint8_t result;\n v1 = strtok(a1, \" \");\n result = 0LL;\n if (v1) return (strlen(v1) & 1) == 0;\n return result;\n}" + }, + { + "index": 964, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char* s) {\n char* word = strtok(s, \" \");\n while (word != NULL) {\n if (strlen(word) % 2 == 0) {\n return 1;\n } else {\n return 0;\n }\n word = strtok(NULL, \" \");\n }\n return 0;\n}", + "test": "int main() {\n\n assert(func0(\"program\") == 0);\n\n assert(func0(\"solution\") == 1);\n\n assert(func0(\"data\") == 1);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x8,%rsp\nlea 0xdc5(%rip),%rsi\ncallq 1090 \nmov %rax,%rdi\nxor %eax,%eax\ntest %rdi,%rdi\nje 1259 \ncallq 1070 \nnot %rax\nand $0x1,%eax\nadd $0x8,%rsp\nretq\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\nlea rsi, delim; \" \"\ncall _strtok\nmov rdi, rax; s\nxor eax, eax\ntest rdi, rdi\njz short loc_1259\ncall _strlen\nnot rax\nand eax, 1\nloc_1259:\nadd rsp, 8\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(char *a1)\n{\n char *v1; // rdi\n _BOOL8 result; // rax\n\n v1 = strtok(a1, \" \");\n result = 0LL;\n if ( v1 )\n return (strlen(v1) & 1) == 0;\n return result;\n}", + "ida_strip_asm": "sub_1230:\nendbr64\nsub rsp, 8\nlea rsi, delim; \" \"\ncall _strtok\nmov rdi, rax; s\nxor eax, eax\ntest rdi, rdi\njz short loc_1259\ncall _strlen\nnot rax\nand eax, 1\nloc_1259:\nadd rsp, 8\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1230(char *a1)\n{\n char *v1; // rdi\n _BOOL8 result; // rax\n\n v1 = strtok(a1, \" \");\n result = 0LL;\n if ( v1 )\n return (strlen(v1) & 1) == 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1230(char *a1) {\n char *v1;\n uint8_t result;\n v1 = strtok(a1, \" \");\n result = 0LL;\n if (v1) return (strlen(v1) & 1) == 0;\n return result;\n}", + "ida_pseudo_norm": "uint8_t func0(char *a1) {\n char *v1;\n uint8_t result;\n v1 = strtok(a1, \" \");\n result = 0LL;\n if (v1) return (strlen(v1) & 1) == 0;\n return result;\n}" + }, + { + "index": 964, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(char* s) {\n char* word = strtok(s, \" \");\n while (word != NULL) {\n if (strlen(word) % 2 == 0) {\n return 1;\n } else {\n return 0;\n }\n word = strtok(NULL, \" \");\n }\n return 0;\n}", + "test": "int main() {\n\n assert(func0(\"program\") == 0);\n\n assert(func0(\"solution\") == 1);\n\n assert(func0(\"data\") == 1);\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x8,%rsp\nlea 0xdc5(%rip),%rsi\ncallq 1090 \nmov %rax,%rdi\nxor %eax,%eax\ntest %rdi,%rdi\nje 1259 \ncallq 1070 \nnot %rax\nand $0x1,%eax\nadd $0x8,%rsp\nretq\nxchg %ax,%ax\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 8\nlea rsi, delim; \" \"\ncall _strtok\nmov rdi, rax; s\nxor eax, eax\ntest rdi, rdi\njz short loc_1259\ncall _strlen\nnot rax\nand eax, 1\nloc_1259:\nadd rsp, 8\nretn", + "ida_pseudo": "_BOOL8 __fastcall func0(char *a1)\n{\n char *v1; // rdi\n _BOOL8 result; // rax\n\n v1 = strtok(a1, \" \");\n result = 0LL;\n if ( v1 )\n return (strlen(v1) & 1) == 0;\n return result;\n}", + "ida_strip_asm": "sub_1230:\nendbr64\nsub rsp, 8\nlea rsi, delim; \" \"\ncall _strtok\nmov rdi, rax; s\nxor eax, eax\ntest rdi, rdi\njz short loc_1259\ncall _strlen\nnot rax\nand eax, 1\nloc_1259:\nadd rsp, 8\nretn", + "ida_strip_pseudo": "_BOOL8 __fastcall sub_1230(char *a1)\n{\n char *v1; // rdi\n _BOOL8 result; // rax\n\n v1 = strtok(a1, \" \");\n result = 0LL;\n if ( v1 )\n return (strlen(v1) & 1) == 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t sub_1230(char *a1) {\n char *v1;\n uint8_t result;\n v1 = strtok(a1, \" \");\n result = 0LL;\n if (v1) return (strlen(v1) & 1) == 0;\n return result;\n}", + "ida_pseudo_norm": "uint8_t func0(char *a1) {\n char *v1;\n uint8_t result;\n v1 = strtok(a1, \" \");\n result = 0LL;\n if (v1) return (strlen(v1) & 1) == 0;\n return result;\n}" + }, + { + "index": 965, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n static char buffer[100];\n int i = 0, j = 0;\n while (text[i] != '\\0') {\n if (isupper(text[i])) {\n if (i != 0 && (islower(text[i - 1]) || isdigit(text[i - 1]))) {\n buffer[j++] = '_';\n }\n buffer[j++] = tolower(text[i]);\n } else {\n buffer[j++] = text[i];\n }\n i++;\n }\n buffer[j] = '\\0';\n return buffer;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"PythonProgram\"), \"python_program\") == 0);\n\n assert(strcmp(func0(\"pythonLanguage\"), \"python_language\") == 0);\n\n assert(strcmp(func0(\"ProgrammingLanguage\"), \"programming_language\") == 0);\n\n\n\n printf(\"All assertions passed!\\n\");\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmovl $0x0,-0x8(%rbp)\nmovl $0x0,-0x4(%rbp)\njmpq 1308 \ncallq 10d0 <__ctype_b_loc@plt>\nmov (%rax),%rax\nmov -0x8(%rbp),%edx\nmovslq %edx,%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rdx),%edx\nmovsbq %dl,%rdx\nadd %rdx,%rdx\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x100,%eax\ntest %eax,%eax\nje 12de \ncmpl $0x0,-0x8(%rbp)\nje 12ab \ncallq 10d0 <__ctype_b_loc@plt>\nmov (%rax),%rax\nmov -0x8(%rbp),%edx\nmovslq %edx,%rdx\nlea -0x1(%rdx),%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rdx),%edx\nmovsbq %dl,%rdx\nadd %rdx,%rdx\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x200,%eax\ntest %eax,%eax\njne 1295 \ncallq 10d0 <__ctype_b_loc@plt>\nmov (%rax),%rax\nmov -0x8(%rbp),%edx\nmovslq %edx,%rdx\nlea -0x1(%rdx),%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rdx),%edx\nmovsbq %dl,%rdx\nadd %rdx,%rdx\nadd %rdx,%rax\nmovzwl (%rax),%eax\nmovzwl %ax,%eax\nand $0x800,%eax\ntest %eax,%eax\nje 12ab \nmov -0x4(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x4(%rbp)\ncltq\nlea 0x2d99(%rip),%rdx\nmovb $0x5f,(%rax,%rdx,1)\nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\nmovsbl %al,%eax\nmov %eax,%edi\ncallq 10c0 \nmov %eax,%ecx\nmov -0x4(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x4(%rbp)\ncltq\nlea 0x2d67(%rip),%rdx\nmov %cl,(%rax,%rdx,1)\njmp 1304 \nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x4(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x4(%rbp)\nmovzbl (%rcx),%edx\ncltq\nlea 0x2d3f(%rip),%rcx\nmov %dl,(%rax,%rcx,1)\naddl $0x1,-0x8(%rbp)\nmov -0x8(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 11ec \nmov -0x4(%rbp),%eax\ncltq\nlea 0x2d14(%rip),%rdx\nmovb $0x0,(%rax,%rdx,1)\nlea 0x2d09(%rip),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp loc_1308\nloc_11EC:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_8]\nmovsxd rcx, edx\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 100h\ntest eax, eax\njz loc_12DE\ncmp [rbp+var_8], 0\njz loc_12AB\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nlea rcx, [rdx-1]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 200h\ntest eax, eax\njnz short loc_1295\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nlea rcx, [rdx-1]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 800h\ntest eax, eax\njz short loc_12AB\nloc_1295:\nmov eax, [rbp+var_4]\nlea edx, [rax+1]\nmov [rbp+var_4], edx\ncdqe\nlea rdx, buffer_1\nmov byte ptr [rax+rdx], 5Fh ; '_'\nloc_12AB:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nmov edi, eax; c\ncall _tolower\nmov ecx, eax\nmov eax, [rbp+var_4]\nlea edx, [rax+1]\nmov [rbp+var_4], edx\ncdqe\nlea rdx, buffer_1\nmov [rax+rdx], cl\njmp short loc_1304\nloc_12DE:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_4]\nlea edx, [rax+1]\nmov [rbp+var_4], edx\nmovzx edx, byte ptr [rcx]\ncdqe\nlea rcx, buffer_1\nmov [rax+rcx], dl\nloc_1304:\nadd [rbp+var_8], 1\nloc_1308:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_11EC\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, buffer_1\nmov byte ptr [rax+rdx], 0\nlea rax, buffer_1\nleave\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(__int64 a1)\n{\n int v1; // eax\n char v2; // cl\n int v3; // eax\n int v4; // eax\n int v6; // [rsp+18h] [rbp-8h]\n int v7; // [rsp+1Ch] [rbp-4h]\n\n v6 = 0;\n v7 = 0;\n while ( *(_BYTE *)(v6 + a1) )\n {\n if ( ((*__ctype_b_loc())[*(char *)(v6 + a1)] & 0x100) != 0 )\n {\n if ( v6\n && (((*__ctype_b_loc())[*(char *)(v6 - 1LL + a1)] & 0x200) != 0\n || ((*__ctype_b_loc())[*(char *)(v6 - 1LL + a1)] & 0x800) != 0) )\n {\n v1 = v7++;\n buffer_1[v1] = 95;\n }\n v2 = tolower(*(char *)(v6 + a1));\n v3 = v7++;\n buffer_1[v3] = v2;\n }\n else\n {\n v4 = v7++;\n buffer_1[v4] = *(_BYTE *)(v6 + a1);\n }\n ++v6;\n }\n buffer_1[v7] = 0;\n return buffer_1;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+var_18], rdi\nmov [rbp+var_8], 0\nmov [rbp+var_4], 0\njmp loc_1308\nloc_11EC:\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_8]\nmovsxd rcx, edx\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 100h\ntest eax, eax\njz loc_12DE\ncmp [rbp+var_8], 0\njz loc_12AB\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nlea rcx, [rdx-1]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 200h\ntest eax, eax\njnz short loc_1295\ncall ___ctype_b_loc\nmov rax, [rax]\nmov edx, [rbp+var_8]\nmovsxd rdx, edx\nlea rcx, [rdx-1]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmovzx edx, byte ptr [rdx]\nmovsx rdx, dl\nadd rdx, rdx\nadd rax, rdx\nmovzx eax, word ptr [rax]\nmovzx eax, ax\nand eax, 800h\ntest eax, eax\njz short loc_12AB\nloc_1295:\nmov eax, [rbp+var_4]\nlea edx, [rax+1]\nmov [rbp+var_4], edx\ncdqe\nlea rdx, unk_4040\nmov byte ptr [rax+rdx], 5Fh ; '_'\nloc_12AB:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\nmovsx eax, al\nmov edi, eax; c\ncall _tolower\nmov ecx, eax\nmov eax, [rbp+var_4]\nlea edx, [rax+1]\nmov [rbp+var_4], edx\ncdqe\nlea rdx, unk_4040\nmov [rax+rdx], cl\njmp short loc_1304\nloc_12DE:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_4]\nlea edx, [rax+1]\nmov [rbp+var_4], edx\nmovzx edx, byte ptr [rcx]\ncdqe\nlea rcx, unk_4040\nmov [rax+rcx], dl\nloc_1304:\nadd [rbp+var_8], 1\nloc_1308:\nmov eax, [rbp+var_8]\nmovsxd rdx, eax\nmov rax, [rbp+var_18]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz loc_11EC\nmov eax, [rbp+var_4]\ncdqe\nlea rdx, unk_4040\nmov byte ptr [rax+rdx], 0\nlea rax, unk_4040\nleave\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_11C9(__int64 a1)\n{\n int v1; // eax\n char v2; // cl\n int v3; // eax\n int v4; // eax\n int v6; // [rsp+18h] [rbp-8h]\n int v7; // [rsp+1Ch] [rbp-4h]\n\n v6 = 0;\n v7 = 0;\n while ( *(_BYTE *)(v6 + a1) )\n {\n if ( ((*__ctype_b_loc())[*(char *)(v6 + a1)] & 0x100) != 0 )\n {\n if ( v6\n && (((*__ctype_b_loc())[*(char *)(v6 - 1LL + a1)] & 0x200) != 0\n || ((*__ctype_b_loc())[*(char *)(v6 - 1LL + a1)] & 0x800) != 0) )\n {\n v1 = v7++;\n byte_4040[v1] = 95;\n }\n v2 = tolower(*(char *)(v6 + a1));\n v3 = v7++;\n byte_4040[v3] = v2;\n }\n else\n {\n v4 = v7++;\n byte_4040[v4] = *(_BYTE *)(v6 + a1);\n }\n ++v6;\n }\n byte_4040[v7] = 0;\n return byte_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_11C9(long long a1) {\n int v1;\n char v2;\n int v3;\n int v4;\n int v6;\n int v7;\n v6 = 0;\n v7 = 0;\n while (*(uint8_t *)(v6 + a1)) {\n if (((*__ctype_b_loc())[*(char *)(v6 + a1)] & 256) != 0) {\n if (v6 && (((*__ctype_b_loc())[*(char *)(v6 - 1LL + a1)] & 512) != 0 ||\n ((*__ctype_b_loc())[*(char *)(v6 - 1LL + a1)] & 2048) != 0)) {\n v1 = v7++;\n byte_4040[v1] = 95;\n }\n v2 = tolower(*(char *)(v6 + a1));\n v3 = v7++;\n byte_4040[v3] = v2;\n } else {\n v4 = v7++;\n byte_4040[v4] = *(uint8_t *)(v6 + a1);\n }\n ++v6;\n }\n byte_4040[v7] = 0;\n return byte_4040;\n}", + "ida_pseudo_norm": "uint8_t *func0(long long a1) {\n int v1;\n char v2;\n int v3;\n int v4;\n int v6;\n int v7;\n v6 = 0;\n v7 = 0;\n while (*(uint8_t *)(v6 + a1)) {\n if (((*__ctype_b_loc())[*(char *)(v6 + a1)] & 256) != 0) {\n if (v6 && (((*__ctype_b_loc())[*(char *)(v6 - 1LL + a1)] & 512) != 0 ||\n ((*__ctype_b_loc())[*(char *)(v6 - 1LL + a1)] & 2048) != 0)) {\n v1 = v7++;\n buffer_1[v1] = 95;\n }\n v2 = tolower(*(char *)(v6 + a1));\n v3 = v7++;\n buffer_1[v3] = v2;\n } else {\n v4 = v7++;\n buffer_1[v4] = *(uint8_t *)(v6 + a1);\n }\n ++v6;\n }\n buffer_1[v7] = 0;\n return buffer_1;\n}" + }, + { + "index": 965, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n static char buffer[100];\n int i = 0, j = 0;\n while (text[i] != '\\0') {\n if (isupper(text[i])) {\n if (i != 0 && (islower(text[i - 1]) || isdigit(text[i - 1]))) {\n buffer[j++] = '_';\n }\n buffer[j++] = tolower(text[i]);\n } else {\n buffer[j++] = text[i];\n }\n i++;\n }\n buffer[j] = '\\0';\n return buffer;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"PythonProgram\"), \"python_program\") == 0);\n\n assert(strcmp(func0(\"pythonLanguage\"), \"python_language\") == 0);\n\n assert(strcmp(func0(\"ProgrammingLanguage\"), \"programming_language\") == 0);\n\n\n\n printf(\"All assertions passed!\\n\");\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmovzbl (%rdi),%r12d\ntest %r12b,%r12b\nje 124c \nmov %rdi,%r13\ncallq 10b0 <__ctype_b_loc@plt>\nmov %rax,%r14\nmov $0x0,%ebx\nmov $0x0,%ebp\nlea 0x2e5c(%rip),%r15\njmp 1213 \ncallq 10a0 <__ctype_tolower_loc@plt>\nmov %rax,%rdx\nmovslq %ebp,%rax\nmovsbq 0x0(%r13,%rbx,1),%rcx\nmov (%rdx),%rdx\nmov (%rdx,%rcx,4),%edx\nmov %dl,(%r15,%rax,1)\nlea 0x1(%rbp),%ebp\nadd $0x1,%rbx\nmovzbl 0x0(%r13,%rbx,1),%r12d\ntest %r12b,%r12b\nje 1251 \nmov (%r14),%rax\nmovsbq %r12b,%rdx\ntestb $0x1,0x1(%rax,%rdx,2)\nje 1240 \ntest %ebx,%ebx\nje 11e6 \nmovsbq -0x1(%r13,%rbx,1),%rdx\ntestw $0xa00,(%rax,%rdx,2)\nje 11e6 \nmovslq %ebp,%rax\nmovb $0x5f,(%r15,%rax,1)\nlea 0x1(%rbp),%ebp\njmp 11e6 \nmovslq %ebp,%rax\nmov %r12b,(%r15,%rax,1)\nlea 0x1(%rbp),%ebp\njmp 1204 \nmov $0x0,%ebp\nlea 0x2de8(%rip),%rax\nmovslq %ebp,%rbp\nmovb $0x0,(%rax,%rbp,1)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmovzx r12d, byte ptr [rdi]\ntest r12b, r12b\njz loc_126C\nmov r13, rdi\ncall ___ctype_b_loc\nmov r14, rax\nmov ebx, 0\nmov ebp, 0\nlea r15, buffer_1\njmp short loc_1233\nloc_1206:\ncall ___ctype_tolower_loc\nmov rdx, rax\nmovsxd rax, ebp\nmovsx rcx, byte ptr [r13+rbx+0]\nmov rdx, [rdx]\nmov edx, [rdx+rcx*4]\nmov [r15+rax], dl\nlea ebp, [rbp+1]\nloc_1224:\nadd rbx, 1\nmovzx r12d, byte ptr [r13+rbx+0]\ntest r12b, r12b\njz short loc_1271\nloc_1233:\nmov rax, [r14]\nmovsx rdx, r12b\ntest byte ptr [rax+rdx*2+1], 1\njz short loc_1260\ntest ebx, ebx\njz short loc_1206\nmovsx rdx, byte ptr [r13+rbx-1]\ntest word ptr [rax+rdx*2], 0A00h\njz short loc_1206\nmovsxd rax, ebp\nmov byte ptr [r15+rax], 5Fh ; '_'\nlea ebp, [rbp+1]\njmp short loc_1206\nloc_1260:\nmovsxd rax, ebp\nmov [r15+rax], r12b\nlea ebp, [rbp+1]\njmp short loc_1224\nloc_126C:\nmov ebp, 0\nloc_1271:\nlea rax, buffer_1\nmovsxd rbp, ebp\nmov byte ptr [rax+rbp], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(char *a1)\n{\n char v1; // r12\n const unsigned __int16 **v2; // r14\n __int64 v3; // rbx\n int v4; // ebp\n _BYTE *result; // rax\n\n v1 = *a1;\n if ( *a1 )\n {\n v2 = __ctype_b_loc();\n v3 = 0LL;\n v4 = 0;\n do\n {\n if ( ((*v2)[v1] & 0x100) != 0 )\n {\n if ( (_DWORD)v3 && ((*v2)[a1[v3 - 1]] & 0xA00) != 0 )\n buffer_1[v4++] = 95;\n buffer_1[v4++] = (*__ctype_tolower_loc())[a1[v3]];\n }\n else\n {\n buffer_1[v4++] = v1;\n }\n v1 = a1[++v3];\n }\n while ( v1 );\n }\n else\n {\n v4 = 0;\n }\n result = buffer_1;\n buffer_1[v4] = 0;\n return result;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmovzx r12d, byte ptr [rdi]\ntest r12b, r12b\njz loc_126C\nmov r13, rdi\ncall ___ctype_b_loc\nmov r14, rax\nmov ebx, 0\nmov ebp, 0\nlea r15, unk_4040\njmp short loc_1233\nloc_1206:\ncall ___ctype_tolower_loc\nmov rdx, rax\nmovsxd rax, ebp\nmovsx rcx, byte ptr [r13+rbx+0]\nmov rdx, [rdx]\nmov edx, [rdx+rcx*4]\nmov [r15+rax], dl\nlea ebp, [rbp+1]\nloc_1224:\nadd rbx, 1\nmovzx r12d, byte ptr [r13+rbx+0]\ntest r12b, r12b\njz short loc_1271\nloc_1233:\nmov rax, [r14]\nmovsx rdx, r12b\ntest byte ptr [rax+rdx*2+1], 1\njz short loc_1260\ntest ebx, ebx\njz short loc_1206\nmovsx rdx, byte ptr [r13+rbx-1]\ntest word ptr [rax+rdx*2], 0A00h\njz short loc_1206\nmovsxd rax, ebp\nmov byte ptr [r15+rax], 5Fh ; '_'\nlea ebp, [rbp+1]\njmp short loc_1206\nloc_1260:\nmovsxd rax, ebp\nmov [r15+rax], r12b\nlea ebp, [rbp+1]\njmp short loc_1224\nloc_126C:\nmov ebp, 0\nloc_1271:\nlea rax, unk_4040\nmovsxd rbp, ebp\nmov byte ptr [rax+rbp], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_11C9(char *a1)\n{\n char v1; // r12\n const unsigned __int16 **v2; // r14\n __int64 v3; // rbx\n int v4; // ebp\n _BYTE *result; // rax\n\n v1 = *a1;\n if ( *a1 )\n {\n v2 = __ctype_b_loc();\n v3 = 0LL;\n v4 = 0;\n do\n {\n if ( ((*v2)[v1] & 0x100) != 0 )\n {\n if ( (_DWORD)v3 && ((*v2)[a1[v3 - 1]] & 0xA00) != 0 )\n byte_4040[v4++] = 95;\n byte_4040[v4++] = (*__ctype_tolower_loc())[a1[v3]];\n }\n else\n {\n byte_4040[v4++] = v1;\n }\n v1 = a1[++v3];\n }\n while ( v1 );\n }\n else\n {\n v4 = 0;\n }\n result = byte_4040;\n byte_4040[v4] = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_11C9(char *a1) {\n char v1;\n const unsigned short **v2;\n long long v3;\n int v4;\n uint8_t *result;\n v1 = *a1;\n if (*a1) {\n v2 = __ctype_b_loc();\n v3 = 0LL;\n v4 = 0;\n do {\n if (((*v2)[v1] & 256) != 0) {\n if ((uint32_t)v3 && ((*v2)[a1[v3 - 1]] & 2560) != 0)\n byte_4040[v4++] = 95;\n byte_4040[v4++] = (*__ctype_tolower_loc())[a1[v3]];\n } else {\n byte_4040[v4++] = v1;\n }\n v1 = a1[++v3];\n } while (v1);\n } else {\n v4 = 0;\n }\n result = byte_4040;\n byte_4040[v4] = 0;\n return result;\n}", + "ida_pseudo_norm": "uint8_t *func0(char *a1) {\n char v1;\n const unsigned short **v2;\n long long v3;\n int v4;\n uint8_t *result;\n v1 = *a1;\n if (*a1) {\n v2 = __ctype_b_loc();\n v3 = 0LL;\n v4 = 0;\n do {\n if (((*v2)[v1] & 256) != 0) {\n if ((uint32_t)v3 && ((*v2)[a1[v3 - 1]] & 2560) != 0)\n buffer_1[v4++] = 95;\n buffer_1[v4++] = (*__ctype_tolower_loc())[a1[v3]];\n } else {\n buffer_1[v4++] = v1;\n }\n v1 = a1[++v3];\n } while (v1);\n } else {\n v4 = 0;\n }\n result = buffer_1;\n buffer_1[v4] = 0;\n return result;\n}" + }, + { + "index": 965, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n static char buffer[100];\n int i = 0, j = 0;\n while (text[i] != '\\0') {\n if (isupper(text[i])) {\n if (i != 0 && (islower(text[i - 1]) || isdigit(text[i - 1]))) {\n buffer[j++] = '_';\n }\n buffer[j++] = tolower(text[i]);\n } else {\n buffer[j++] = text[i];\n }\n i++;\n }\n buffer[j] = '\\0';\n return buffer;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"PythonProgram\"), \"python_program\") == 0);\n\n assert(strcmp(func0(\"pythonLanguage\"), \"python_language\") == 0);\n\n assert(strcmp(func0(\"ProgrammingLanguage\"), \"programming_language\") == 0);\n\n\n\n printf(\"All assertions passed!\\n\");\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmovzbl (%rdi),%r12d\ntest %r12b,%r12b\nje 1378 \nmov %rdi,%r14\nxor %ebp,%ebp\nlea 0x2d75(%rip),%r15\nxor %ebx,%ebx\ncallq 10b0 <__ctype_b_loc@plt>\nmov %rax,%rcx\njmp 1333 \nnopw 0x0(%rax,%rax,1)\ntest %rbp,%rbp\nje 1304 \nmovsbq -0x1(%r14,%rbp,1),%rdx\ntestw $0xa00,(%rax,%rdx,2)\nje 1304 \nmovslq %ebx,%rax\nmovb $0x5f,(%r15,%rax,1)\nlea 0x2(%rbx),%eax\nmovslq %r13d,%rbx\nmov %eax,%r13d\nmov %rcx,0x8(%rsp)\ncallq 10a0 <__ctype_tolower_loc@plt>\nmovsbq (%r14,%rbp,1),%rdx\nadd $0x1,%rbp\nmov 0x8(%rsp),%rcx\nmov (%rax),%rax\nmov (%rax,%rdx,4),%eax\nmov %al,(%r15,%rbx,1)\nmovzbl (%r14,%rbp,1),%r12d\nmovslq %r13d,%rbx\ntest %r12b,%r12b\nje 135a \nmov (%rcx),%rax\nmovsbq %r12b,%rdx\nlea 0x1(%rbx),%r13d\ntestb $0x1,0x1(%rax,%rdx,2)\njne 12e0 \nadd $0x1,%rbp\nmov %r12b,(%r15,%rbx,1)\nmovslq %r13d,%rbx\nmovzbl (%r14,%rbp,1),%r12d\ntest %r12b,%r12b\njne 1333 \nmovb $0x0,(%r15,%rbx,1)\nadd $0x18,%rsp\nlea 0x2cd6(%rip),%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl (%rax)\nxor %ebx,%ebx\nlea 0x2cbf(%rip),%r15\njmp 135a \nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmovzx r12d, byte ptr [rdi]\ntest r12b, r12b\njz loc_1380\nmov r14, rdi\nxor ebp, ebp\nlea r15, buffer_1\nxor ebx, ebx\ncall ___ctype_b_loc\nmov rcx, rax\njmp short loc_133E\nloc_12F0:\ntest rbp, rbp\njz short loc_130F\nmovsx rdx, byte ptr [r14+rbp-1]\ntest word ptr [rax+rdx*2], 0A00h\njz short loc_130F\nmov byte ptr [r15+rbx], 5Fh ; '_'\nmovsxd rbx, r13d\nlea r13d, [rbx+1]\nloc_130F:\nmov [rsp+48h+var_40], rcx\ncall ___ctype_tolower_loc\nmovsx rdx, byte ptr [r14+rbp]\nadd rbp, 1\nmov rcx, [rsp+48h+var_40]\nmov rax, [rax]\nmov eax, [rax+rdx*4]\nmov [r15+rbx], al\nmovzx r12d, byte ptr [r14+rbp]\nmovsxd rbx, r13d\ntest r12b, r12b\njz short loc_1365\nloc_133E:\nmov rax, [rcx]\nmovsx rdx, r12b\nlea r13d, [rbx+1]\ntest byte ptr [rax+rdx*2+1], 1\njnz short loc_12F0\nadd rbp, 1\nmov [r15+rbx], r12b\nmovsxd rbx, r13d\nmovzx r12d, byte ptr [r14+rbp]\ntest r12b, r12b\njnz short loc_133E\nloc_1365:\nmov byte ptr [r15+rbx], 0\nadd rsp, 18h\nmov rax, r15\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1380:\nxor ebx, ebx\nlea r15, buffer_1\njmp short loc_1365", + "ida_pseudo": "_BYTE *__fastcall func0(char *a1)\n{\n char v1; // r12\n __int64 v2; // rbp\n __int64 v3; // rbx\n const unsigned __int16 **v4; // rcx\n int v5; // r13d\n const __int32_t **v6; // rax\n __int64 v7; // rdx\n const unsigned __int16 **v9; // [rsp+8h] [rbp-40h]\n\n v1 = *a1;\n if ( *a1 )\n {\n v2 = 0LL;\n v3 = 0LL;\n v4 = __ctype_b_loc();\n do\n {\n while ( 1 )\n {\n v5 = v3 + 1;\n if ( ((*v4)[v1] & 0x100) != 0 )\n break;\n ++v2;\n buffer_1[v3] = v1;\n v3 = v5;\n v1 = a1[v2];\n if ( !v1 )\n goto LABEL_9;\n }\n if ( v2 && ((*v4)[a1[v2 - 1]] & 0xA00) != 0 )\n {\n buffer_1[v3] = 95;\n v3 = v5++;\n }\n v9 = v4;\n v6 = __ctype_tolower_loc();\n v7 = a1[v2++];\n v4 = v9;\n buffer_1[v3] = (*v6)[v7];\n v1 = a1[v2];\n v3 = v5;\n }\n while ( v1 );\n }\n else\n {\n v3 = 0LL;\n }\nLABEL_9:\n buffer_1[v3] = 0;\n return buffer_1;\n}", + "ida_strip_asm": "sub_12B0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmovzx r12d, byte ptr [rdi]\ntest r12b, r12b\njz loc_1380\nmov r14, rdi\nxor ebp, ebp\nlea r15, unk_4040\nxor ebx, ebx\ncall ___ctype_b_loc\nmov rcx, rax\njmp short loc_133E\nloc_12F0:\ntest rbp, rbp\njz short loc_130F\nmovsx rdx, byte ptr [r14+rbp-1]\ntest word ptr [rax+rdx*2], 0A00h\njz short loc_130F\nmov byte ptr [r15+rbx], 5Fh ; '_'\nmovsxd rbx, r13d\nlea r13d, [rbx+1]\nloc_130F:\nmov [rsp+48h+var_40], rcx\ncall ___ctype_tolower_loc\nmovsx rdx, byte ptr [r14+rbp]\nadd rbp, 1\nmov rcx, [rsp+48h+var_40]\nmov rax, [rax]\nmov eax, [rax+rdx*4]\nmov [r15+rbx], al\nmovzx r12d, byte ptr [r14+rbp]\nmovsxd rbx, r13d\ntest r12b, r12b\njz short loc_1365\nloc_133E:\nmov rax, [rcx]\nmovsx rdx, r12b\nlea r13d, [rbx+1]\ntest byte ptr [rax+rdx*2+1], 1\njnz short loc_12F0\nadd rbp, 1\nmov [r15+rbx], r12b\nmovsxd rbx, r13d\nmovzx r12d, byte ptr [r14+rbp]\ntest r12b, r12b\njnz short loc_133E\nloc_1365:\nmov byte ptr [r15+rbx], 0\nadd rsp, 18h\nmov rax, r15\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1380:\nxor ebx, ebx\nlea r15, unk_4040\njmp short loc_1365", + "ida_strip_pseudo": "_BYTE *__fastcall sub_12B0(char *a1)\n{\n char v1; // r12\n __int64 v2; // rbp\n __int64 v3; // rbx\n const unsigned __int16 **v4; // rcx\n int v5; // r13d\n const __int32_t **v6; // rax\n __int64 v7; // rdx\n const unsigned __int16 **v9; // [rsp+8h] [rbp-40h]\n\n v1 = *a1;\n if ( *a1 )\n {\n v2 = 0LL;\n v3 = 0LL;\n v4 = __ctype_b_loc();\n do\n {\n while ( 1 )\n {\n v5 = v3 + 1;\n if ( ((*v4)[v1] & 0x100) != 0 )\n break;\n ++v2;\n byte_4040[v3] = v1;\n v3 = v5;\n v1 = a1[v2];\n if ( !v1 )\n goto LABEL_9;\n }\n if ( v2 && ((*v4)[a1[v2 - 1]] & 0xA00) != 0 )\n {\n byte_4040[v3] = 95;\n v3 = v5++;\n }\n v9 = v4;\n v6 = __ctype_tolower_loc();\n v7 = a1[v2++];\n v4 = v9;\n byte_4040[v3] = (*v6)[v7];\n v1 = a1[v2];\n v3 = v5;\n }\n while ( v1 );\n }\n else\n {\n v3 = 0LL;\n }\nLABEL_9:\n byte_4040[v3] = 0;\n return byte_4040;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_12B0(char *a1) {\n char v1;\n long long v2;\n long long v3;\n const unsigned short **v4;\n int v5;\n const __int32_t **v6;\n long long v7;\n const unsigned short **v9;\n v1 = *a1;\n if (*a1) {\n v2 = 0LL;\n v3 = 0LL;\n v4 = __ctype_b_loc();\n do {\n while (1) {\n v5 = v3 + 1;\n if (((*v4)[v1] & 256) != 0) break;\n ++v2;\n byte_4040[v3] = v1;\n v3 = v5;\n v1 = a1[v2];\n if (!v1) goto LABEL_9;\n }\n if (v2 && ((*v4)[a1[v2 - 1]] & 2560) != 0) {\n byte_4040[v3] = 95;\n v3 = v5++;\n }\n v9 = v4;\n v6 = __ctype_tolower_loc();\n v7 = a1[v2++];\n v4 = v9;\n byte_4040[v3] = (*v6)[v7];\n v1 = a1[v2];\n v3 = v5;\n } while (v1);\n } else {\n v3 = 0LL;\n }\nLABEL_9:\n byte_4040[v3] = 0;\n return byte_4040;\n}", + "ida_pseudo_norm": "uint8_t *func0(char *a1) {\n char v1;\n long long v2;\n long long v3;\n const unsigned short **v4;\n int v5;\n const __int32_t **v6;\n long long v7;\n const unsigned short **v9;\n v1 = *a1;\n if (*a1) {\n v2 = 0LL;\n v3 = 0LL;\n v4 = __ctype_b_loc();\n do {\n while (1) {\n v5 = v3 + 1;\n if (((*v4)[v1] & 256) != 0) break;\n ++v2;\n buffer_1[v3] = v1;\n v3 = v5;\n v1 = a1[v2];\n if (!v1) goto LABEL_9;\n }\n if (v2 && ((*v4)[a1[v2 - 1]] & 2560) != 0) {\n buffer_1[v3] = 95;\n v3 = v5++;\n }\n v9 = v4;\n v6 = __ctype_tolower_loc();\n v7 = a1[v2++];\n v4 = v9;\n buffer_1[v3] = (*v6)[v7];\n v1 = a1[v2];\n v3 = v5;\n } while (v1);\n } else {\n v3 = 0LL;\n }\nLABEL_9:\n buffer_1[v3] = 0;\n return buffer_1;\n}" + }, + { + "index": 965, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(const char* text) {\n static char buffer[100];\n int i = 0, j = 0;\n while (text[i] != '\\0') {\n if (isupper(text[i])) {\n if (i != 0 && (islower(text[i - 1]) || isdigit(text[i - 1]))) {\n buffer[j++] = '_';\n }\n buffer[j++] = tolower(text[i]);\n } else {\n buffer[j++] = text[i];\n }\n i++;\n }\n buffer[j] = '\\0';\n return buffer;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"PythonProgram\"), \"python_program\") == 0);\n\n assert(strcmp(func0(\"pythonLanguage\"), \"python_language\") == 0);\n\n assert(strcmp(func0(\"ProgrammingLanguage\"), \"programming_language\") == 0);\n\n\n\n printf(\"All assertions passed!\\n\");\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmovzbl (%rdi),%r12d\ntest %r12b,%r12b\nje 1380 \nmov %rdi,%r15\nxor %ebp,%ebp\nxor %ebx,%ebx\ncallq 10b0 <__ctype_b_loc@plt>\nlea 0x2d6e(%rip),%rdx\nmov %rax,%rcx\njmp 133a \nnopw 0x0(%rax,%rax,1)\ntest %rbp,%rbp\nje 1308 \nmovsbq -0x1(%r15,%rbp,1),%rsi\ntestw $0xa00,(%rax,%rsi,2)\nje 1308 \nmovslq %ebx,%rax\nmovb $0x5f,(%rdx,%rax,1)\nlea 0x2(%rbx),%eax\nmovsbq (%r15,%rbp,1),%r13\nmovslq %r14d,%rbx\nmov %eax,%r14d\nmov %rdx,0x8(%rsp)\nadd $0x1,%rbp\nmov %rcx,(%rsp)\ncallq 10a0 <__ctype_tolower_loc@plt>\nmov 0x8(%rsp),%rdx\nmov (%rsp),%rcx\nmov (%rax),%rax\nmov (%rax,%r13,4),%eax\nmov %al,(%rdx,%rbx,1)\nmovzbl (%r15,%rbp,1),%r12d\nmovslq %r14d,%rbx\ntest %r12b,%r12b\nje 1362 \nmov (%rcx),%rax\nmovsbq %r12b,%r13\nlea 0x1(%rbx),%r14d\ntestb $0x1,0x1(%rax,%r13,2)\njne 12e0 \nadd $0x1,%rbp\nmov %r12b,(%rdx,%rbx,1)\nmovslq %r14d,%rbx\nmovzbl (%r15,%rbp,1),%r12d\ntest %r12b,%r12b\njne 133a \nmovb $0x0,(%rdx,%rbx,1)\nadd $0x18,%rsp\nlea 0x2ccf(%rip),%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\nxor %ebx,%ebx\nlea 0x2cb7(%rip),%rdx\njmp 1362 \nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmovzx r12d, byte ptr [rdi]\ntest r12b, r12b\njz loc_1388\nmov r15, rdi\nxor ebp, ebp\nxor ebx, ebx\ncall ___ctype_b_loc\nlea rdx, buffer_1\nmov rcx, rax\njmp short loc_1345\nloc_12F0:\ntest rbp, rbp\njz short loc_1313\nmovsx rsi, byte ptr [r15+rbp-1]\ntest word ptr [rax+rsi*2], 0A00h\njz short loc_1313\nmov byte ptr [rdx+rbx], 5Fh ; '_'\nmovsxd rbx, r14d\nmovsx r13, byte ptr [r15+rbp]\nlea r14d, [rbx+1]\nloc_1313:\nmov [rsp+48h+var_40], rdx\nadd rbp, 1\nmov [rsp+48h+var_48], rcx\ncall ___ctype_tolower_loc\nmov rdx, [rsp+48h+var_40]\nmov rcx, [rsp+48h+var_48]\nmov rax, [rax]\nmov eax, [rax+r13*4]\nmov [rdx+rbx], al\nmovzx r12d, byte ptr [r15+rbp]\nmovsxd rbx, r14d\ntest r12b, r12b\njz short loc_136D\nloc_1345:\nmov rax, [rcx]\nmovsx r13, r12b\nlea r14d, [rbx+1]\ntest byte ptr [rax+r13*2+1], 1\njnz short loc_12F0\nadd rbp, 1\nmov [rdx+rbx], r12b\nmovsxd rbx, r14d\nmovzx r12d, byte ptr [r15+rbp]\ntest r12b, r12b\njnz short loc_1345\nloc_136D:\nmov byte ptr [rdx+rbx], 0\nadd rsp, 18h\nmov rax, rdx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1388:\nxor ebx, ebx\nlea rdx, buffer_1\njmp short loc_136D", + "ida_pseudo": "_BYTE *__fastcall func0(char *a1)\n{\n char v1; // r12\n __int64 v2; // rbp\n __int64 v3; // rbx\n const unsigned __int16 **v4; // rax\n _BYTE *v5; // rdx\n const unsigned __int16 **v6; // rcx\n __int64 v7; // r13\n int v8; // r14d\n const __int32_t **v9; // rax\n const unsigned __int16 **v11; // [rsp+0h] [rbp-48h]\n _BYTE *v12; // [rsp+8h] [rbp-40h]\n\n v1 = *a1;\n if ( *a1 )\n {\n v2 = 0LL;\n v3 = 0LL;\n v4 = __ctype_b_loc();\n v5 = &buffer_1;\n v6 = v4;\n do\n {\n while ( 1 )\n {\n v7 = v1;\n v8 = v3 + 1;\n if ( ((*v6)[v1] & 0x100) != 0 )\n break;\n ++v2;\n v5[v3] = v1;\n v3 = v8;\n v1 = a1[v2];\n if ( !v1 )\n goto LABEL_9;\n }\n if ( v2 && ((*v6)[a1[v2 - 1]] & 0xA00) != 0 )\n {\n v5[v3] = 95;\n v3 = v8;\n v7 = a1[v2];\n ++v8;\n }\n v12 = v5;\n ++v2;\n v11 = v6;\n v9 = __ctype_tolower_loc();\n v5 = v12;\n v6 = v11;\n v12[v3] = (*v9)[v7];\n v1 = a1[v2];\n v3 = v8;\n }\n while ( v1 );\n }\n else\n {\n v3 = 0LL;\n v5 = &buffer_1;\n }\nLABEL_9:\n v5[v3] = 0;\n return v5;\n}", + "ida_strip_asm": "sub_12B0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmovzx r12d, byte ptr [rdi]\ntest r12b, r12b\njz loc_1388\nmov r15, rdi\nxor ebp, ebp\nxor ebx, ebx\ncall ___ctype_b_loc\nlea rdx, unk_4040\nmov rcx, rax\njmp short loc_1345\nloc_12F0:\ntest rbp, rbp\njz short loc_1313\nmovsx rsi, byte ptr [r15+rbp-1]\ntest word ptr [rax+rsi*2], 0A00h\njz short loc_1313\nmov byte ptr [rdx+rbx], 5Fh ; '_'\nmovsxd rbx, r14d\nmovsx r13, byte ptr [r15+rbp]\nlea r14d, [rbx+1]\nloc_1313:\nmov [rsp+48h+var_40], rdx\nadd rbp, 1\nmov [rsp+48h+var_48], rcx\ncall ___ctype_tolower_loc\nmov rdx, [rsp+48h+var_40]\nmov rcx, [rsp+48h+var_48]\nmov rax, [rax]\nmov eax, [rax+r13*4]\nmov [rdx+rbx], al\nmovzx r12d, byte ptr [r15+rbp]\nmovsxd rbx, r14d\ntest r12b, r12b\njz short loc_136D\nloc_1345:\nmov rax, [rcx]\nmovsx r13, r12b\nlea r14d, [rbx+1]\ntest byte ptr [rax+r13*2+1], 1\njnz short loc_12F0\nadd rbp, 1\nmov [rdx+rbx], r12b\nmovsxd rbx, r14d\nmovzx r12d, byte ptr [r15+rbp]\ntest r12b, r12b\njnz short loc_1345\nloc_136D:\nmov byte ptr [rdx+rbx], 0\nadd rsp, 18h\nmov rax, rdx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_1388:\nxor ebx, ebx\nlea rdx, unk_4040\njmp short loc_136D", + "ida_strip_pseudo": "_BYTE *__fastcall sub_12B0(char *a1)\n{\n char v1; // r12\n __int64 v2; // rbp\n __int64 v3; // rbx\n const unsigned __int16 **v4; // rax\n _BYTE *v5; // rdx\n const unsigned __int16 **v6; // rcx\n __int64 v7; // r13\n int v8; // r14d\n const __int32_t **v9; // rax\n const unsigned __int16 **v11; // [rsp+0h] [rbp-48h]\n _BYTE *v12; // [rsp+8h] [rbp-40h]\n\n v1 = *a1;\n if ( *a1 )\n {\n v2 = 0LL;\n v3 = 0LL;\n v4 = __ctype_b_loc();\n v5 = &unk_4040;\n v6 = v4;\n do\n {\n while ( 1 )\n {\n v7 = v1;\n v8 = v3 + 1;\n if ( ((*v6)[v1] & 0x100) != 0 )\n break;\n ++v2;\n v5[v3] = v1;\n v3 = v8;\n v1 = a1[v2];\n if ( !v1 )\n goto LABEL_9;\n }\n if ( v2 && ((*v6)[a1[v2 - 1]] & 0xA00) != 0 )\n {\n v5[v3] = 95;\n v3 = v8;\n v7 = a1[v2];\n ++v8;\n }\n v12 = v5;\n ++v2;\n v11 = v6;\n v9 = __ctype_tolower_loc();\n v5 = v12;\n v6 = v11;\n v12[v3] = (*v9)[v7];\n v1 = a1[v2];\n v3 = v8;\n }\n while ( v1 );\n }\n else\n {\n v3 = 0LL;\n v5 = &unk_4040;\n }\nLABEL_9:\n v5[v3] = 0;\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_12B0(char *a1) {\n char v1;\n long long v2;\n long long v3;\n const unsigned short **v4;\n uint8_t *v5;\n const unsigned short **v6;\n long long v7;\n int v8;\n const __int32_t **v9;\n const unsigned short **v11;\n uint8_t *v12;\n v1 = *a1;\n if (*a1) {\n v2 = 0LL;\n v3 = 0LL;\n v4 = __ctype_b_loc();\n v5 = &unk_4040;\n v6 = v4;\n do {\n while (1) {\n v7 = v1;\n v8 = v3 + 1;\n if (((*v6)[v1] & 256) != 0) break;\n ++v2;\n v5[v3] = v1;\n v3 = v8;\n v1 = a1[v2];\n if (!v1) goto LABEL_9;\n }\n if (v2 && ((*v6)[a1[v2 - 1]] & 2560) != 0) {\n v5[v3] = 95;\n v3 = v8;\n v7 = a1[v2];\n ++v8;\n }\n v12 = v5;\n ++v2;\n v11 = v6;\n v9 = __ctype_tolower_loc();\n v5 = v12;\n v6 = v11;\n v12[v3] = (*v9)[v7];\n v1 = a1[v2];\n v3 = v8;\n } while (v1);\n } else {\n v3 = 0LL;\n v5 = &unk_4040;\n }\nLABEL_9:\n v5[v3] = 0;\n return v5;\n}", + "ida_pseudo_norm": "uint8_t *func0(char *a1) {\n char v1;\n long long v2;\n long long v3;\n const unsigned short **v4;\n uint8_t *v5;\n const unsigned short **v6;\n long long v7;\n int v8;\n const __int32_t **v9;\n const unsigned short **v11;\n uint8_t *v12;\n v1 = *a1;\n if (*a1) {\n v2 = 0LL;\n v3 = 0LL;\n v4 = __ctype_b_loc();\n v5 = &buffer_1;\n v6 = v4;\n do {\n while (1) {\n v7 = v1;\n v8 = v3 + 1;\n if (((*v6)[v1] & 256) != 0) break;\n ++v2;\n v5[v3] = v1;\n v3 = v8;\n v1 = a1[v2];\n if (!v1) goto LABEL_9;\n }\n if (v2 && ((*v6)[a1[v2 - 1]] & 2560) != 0) {\n v5[v3] = 95;\n v3 = v8;\n v7 = a1[v2];\n ++v8;\n }\n v12 = v5;\n ++v2;\n v11 = v6;\n v9 = __ctype_tolower_loc();\n v5 = v12;\n v6 = v11;\n v12[v3] = (*v9)[v7];\n v1 = a1[v2];\n v3 = v8;\n } while (v1);\n } else {\n v3 = 0LL;\n v5 = &buffer_1;\n }\nLABEL_9:\n v5[v3] = 0;\n return v5;\n}" + }, + { + "index": 966, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n// Function to remove empty elements\n\n", + "func": "char** func0(char** tuple1, int size, int* new_size) {\n char** result = malloc(size * sizeof(char*));\n int j = 0;\n for (int i = 0; i < size; i++) {\n if (tuple1[i] != NULL) {\n result[j++] = tuple1[i];\n }\n }\n *new_size = j;\n return result;\n}", + "test": "int main() {\n\n // First test case\n\n char* input1[] = {NULL, NULL, \"\", \"a,b\", \"a,b,c\", \"d\"};\n\n char* expected1[] = {\"\", \"a,b\", \"a,b,c\", \"d\"};\n\n int new_size1;\n\n char** output1 = func0(input1, 6, &new_size1);\n\n assert(new_size1 == 4);\n\n for(int i = 0; i < new_size1; i++) {\n\n assert(output1[i] == expected1[i]);\n\n }\n\n\n\n // Second test case\n\n char* input2[] = {NULL, NULL, \"\", \"python\", \"program\"};\n\n char* expected2[] = {\"\", \"python\", \"program\"};\n\n int new_size2;\n\n char** output2 = func0(input2, 5, &new_size2);\n\n assert(new_size2 == 3);\n\n for(int i = 0; i < new_size2; i++) {\n\n assert(output2[i] == expected2[i]);\n\n }\n\n\n\n // Third test case\n\n char* input3[] = {NULL, NULL, \"\", \"java\"};\n\n char* expected3[] = {\"\", \"java\"};\n\n int new_size3;\n\n char** output3 = func0(input3, 4, &new_size3);\n\n assert(new_size3 == 2);\n\n for(int i = 0; i < new_size3; i++) {\n\n assert(output3[i] == expected3[i]);\n\n }\n\n\n\n // Free allocated memory\n\n free(output1);\n\n free(output2);\n\n free(output3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov %rdx,-0x28(%rbp)\nmov -0x1c(%rbp),%eax\ncltq\nshl $0x3,%rax\nmov %rax,%rdi\ncallq 10b0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0x10(%rbp)\nmovl $0x0,-0xc(%rbp)\njmp 123a \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\ntest %rax,%rax\nje 1236 \nmov -0xc(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x18(%rbp),%rax\nlea (%rdx,%rax,1),%rcx\nmov -0x10(%rbp),%eax\nlea 0x1(%rax),%edx\nmov %edx,-0x10(%rbp)\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x8(%rbp),%rax\nadd %rax,%rdx\nmov (%rcx),%rax\nmov %rax,(%rdx)\naddl $0x1,-0xc(%rbp)\nmov -0xc(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 11e5 \nmov -0x28(%rbp),%rax\nmov -0x10(%rbp),%edx\nmov %edx,(%rax)\nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp short loc_123A\nloc_11E5:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\ntest rax, rax\njz short loc_1236\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov rax, [rcx]\nmov [rdx], rax\nloc_1236:\nadd [rbp+var_C], 1\nloc_123A:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_11E5\nmov rax, [rbp+var_28]\nmov edx, [rbp+var_10]\nmov [rax], edx\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(__int64 a1, int a2, _DWORD *a3)\n{\n int v3; // eax\n int v6; // [rsp+20h] [rbp-10h]\n int i; // [rsp+24h] [rbp-Ch]\n _QWORD *v8; // [rsp+28h] [rbp-8h]\n\n v8 = malloc(8LL * a2);\n v6 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(_QWORD *)(8LL * i + a1) )\n {\n v3 = v6++;\n v8[v3] = *(_QWORD *)(8LL * i + a1);\n }\n }\n *a3 = v6;\n return v8;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_18], rdi\nmov [rbp+var_1C], esi\nmov [rbp+var_28], rdx\nmov eax, [rbp+var_1C]\ncdqe\nshl rax, 3\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_10], 0\nmov [rbp+var_C], 0\njmp short loc_123A\nloc_11E5:\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax]\ntest rax, rax\njz short loc_1236\nmov eax, [rbp+var_C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_18]\nlea rcx, [rdx+rax]\nmov eax, [rbp+var_10]\nlea edx, [rax+1]\nmov [rbp+var_10], edx\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_8]\nadd rdx, rax\nmov rax, [rcx]\nmov [rdx], rax\nloc_1236:\nadd [rbp+var_C], 1\nloc_123A:\nmov eax, [rbp+var_C]\ncmp eax, [rbp+var_1C]\njl short loc_11E5\nmov rax, [rbp+var_28]\nmov edx, [rbp+var_10]\nmov [rax], edx\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11A9(__int64 a1, int a2, _DWORD *a3)\n{\n int v3; // eax\n int v6; // [rsp+20h] [rbp-10h]\n int i; // [rsp+24h] [rbp-Ch]\n _QWORD *v8; // [rsp+28h] [rbp-8h]\n\n v8 = malloc(8LL * a2);\n v6 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( *(_QWORD *)(8LL * i + a1) )\n {\n v3 = v6++;\n v8[v3] = *(_QWORD *)(8LL * i + a1);\n }\n }\n *a3 = v6;\n return v8;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11A9(long long a1, int a2, uint32_t *a3) {\n int v3;\n int v6;\n int i;\n uint64_t *v8;\n v8 = malloc(8LL * a2);\n v6 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(uint64_t *)(8LL * i + a1)) {\n v3 = v6++;\n v8[v3] = *(uint64_t *)(8LL * i + a1);\n }\n }\n *a3 = v6;\n return v8;\n}", + "ida_pseudo_norm": "uint64_t *func0(long long a1, int a2, uint32_t *a3) {\n int v3;\n int v6;\n int i;\n uint64_t *v8;\n v8 = malloc(8LL * a2);\n v6 = 0;\n for (i = 0; i < a2; ++i) {\n if (*(uint64_t *)(8LL * i + a1)) {\n v3 = v6++;\n v8[v3] = *(uint64_t *)(8LL * i + a1);\n }\n }\n *a3 = v6;\n return v8;\n}" + }, + { + "index": 966, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n// Function to remove empty elements\n\n", + "func": "char** func0(char** tuple1, int size, int* new_size) {\n char** result = malloc(size * sizeof(char*));\n int j = 0;\n for (int i = 0; i < size; i++) {\n if (tuple1[i] != NULL) {\n result[j++] = tuple1[i];\n }\n }\n *new_size = j;\n return result;\n}", + "test": "int main() {\n\n // First test case\n\n char* input1[] = {NULL, NULL, \"\", \"a,b\", \"a,b,c\", \"d\"};\n\n char* expected1[] = {\"\", \"a,b\", \"a,b,c\", \"d\"};\n\n int new_size1;\n\n char** output1 = func0(input1, 6, &new_size1);\n\n assert(new_size1 == 4);\n\n for(int i = 0; i < new_size1; i++) {\n\n assert(output1[i] == expected1[i]);\n\n }\n\n\n\n // Second test case\n\n char* input2[] = {NULL, NULL, \"\", \"python\", \"program\"};\n\n char* expected2[] = {\"\", \"python\", \"program\"};\n\n int new_size2;\n\n char** output2 = func0(input2, 5, &new_size2);\n\n assert(new_size2 == 3);\n\n for(int i = 0; i < new_size2; i++) {\n\n assert(output2[i] == expected2[i]);\n\n }\n\n\n\n // Third test case\n\n char* input3[] = {NULL, NULL, \"\", \"java\"};\n\n char* expected3[] = {\"\", \"java\"};\n\n int new_size3;\n\n char** output3 = func0(input3, 4, &new_size3);\n\n assert(new_size3 == 2);\n\n for(int i = 0; i < new_size3; i++) {\n\n assert(output3[i] == expected3[i]);\n\n }\n\n\n\n // Free allocated memory\n\n free(output1);\n\n free(output2);\n\n free(output3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%r12\nmov %esi,%ebp\nmov %rdx,%rbx\nmovslq %esi,%rdi\nshl $0x3,%rdi\ncallq 10b0 \ntest %ebp,%ebp\njle 11f8 \nmov %r12,%rdx\nlea -0x1(%rbp),%ecx\nlea 0x8(%r12,%rcx,8),%r8\nmov $0x0,%esi\njmp 11e4 \nadd $0x8,%rdx\ncmp %r8,%rdx\nje 11fd \nmov (%rdx),%rcx\ntest %rcx,%rcx\nje 11db \nmovslq %esi,%rdi\nmov %rcx,(%rax,%rdi,8)\nlea 0x1(%rsi),%esi\njmp 11db \nmov $0x0,%esi\nmov %esi,(%rbx)\npop %rbx\npop %rbp\npop %r12\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov r13d, esi\nmov rbp, rdx\nmovsxd r12, esi\nshl r12, 3\nmov rdi, r12; size\ncall _malloc\ntest r13d, r13d\njle short loc_11FF\nmov rdx, rbx\nlea rdi, [rbx+r12]\nmov esi, 0\njmp short loc_11F5\nloc_11E2:\nmovsxd r8, esi\nmov [rax+r8*8], rcx\nlea esi, [rsi+1]\nloc_11EC:\nadd rdx, 8\ncmp rdx, rdi\njz short loc_1204\nloc_11F5:\nmov rcx, [rdx]\ntest rcx, rcx\njnz short loc_11E2\njmp short loc_11EC\nloc_11FF:\nmov esi, 0\nloc_1204:\nmov [rbp+0], esi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(_QWORD *a1, int a2, _DWORD *a3)\n{\n _QWORD *result; // rax\n _QWORD *v5; // rdx\n _QWORD *v6; // rdi\n int v7; // esi\n\n result = malloc(8LL * a2);\n if ( a2 <= 0 )\n {\n v7 = 0;\n }\n else\n {\n v5 = a1;\n v6 = &a1[a2];\n v7 = 0;\n do\n {\n if ( *v5 )\n result[v7++] = *v5;\n ++v5;\n }\n while ( v5 != v6 );\n }\n *a3 = v7;\n return result;\n}", + "ida_strip_asm": "sub_11A9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbx, rdi\nmov r13d, esi\nmov rbp, rdx\nmovsxd r12, esi\nshl r12, 3\nmov rdi, r12; size\ncall _malloc\ntest r13d, r13d\njle short loc_11FF\nmov rdx, rbx\nlea rdi, [rbx+r12]\nmov esi, 0\njmp short loc_11F5\nloc_11E2:\nmovsxd r8, esi\nmov [rax+r8*8], rcx\nlea esi, [rsi+1]\nloc_11EC:\nadd rdx, 8\ncmp rdx, rdi\njz short loc_1204\nloc_11F5:\nmov rcx, [rdx]\ntest rcx, rcx\njnz short loc_11E2\njmp short loc_11EC\nloc_11FF:\nmov esi, 0\nloc_1204:\nmov [rbp+0], esi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_11A9(_QWORD *a1, int a2, _DWORD *a3)\n{\n _QWORD *result; // rax\n _QWORD *v5; // rdx\n _QWORD *v6; // rdi\n int v7; // esi\n\n result = malloc(8LL * a2);\n if ( a2 <= 0 )\n {\n v7 = 0;\n }\n else\n {\n v5 = a1;\n v6 = &a1[a2];\n v7 = 0;\n do\n {\n if ( *v5 )\n result[v7++] = *v5;\n ++v5;\n }\n while ( v5 != v6 );\n }\n *a3 = v7;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_11A9(uint64_t *a1, int a2, uint32_t *a3) {\n uint64_t *result;\n uint64_t *v5;\n uint64_t *v6;\n int v7;\n result = malloc(8LL * a2);\n if (a2 <= 0) {\n v7 = 0;\n } else {\n v5 = a1;\n v6 = &a1[a2];\n v7 = 0;\n do {\n if (*v5) result[v7++] = *v5;\n ++v5;\n } while (v5 != v6);\n }\n *a3 = v7;\n return result;\n}", + "ida_pseudo_norm": "uint64_t *func0(uint64_t *a1, int a2, uint32_t *a3) {\n uint64_t *result;\n uint64_t *v5;\n uint64_t *v6;\n int v7;\n result = malloc(8LL * a2);\n if (a2 <= 0) {\n v7 = 0;\n } else {\n v5 = a1;\n v6 = &a1[a2];\n v7 = 0;\n do {\n if (*v5) result[v7++] = *v5;\n ++v5;\n } while (v5 != v6);\n }\n *a3 = v7;\n return result;\n}" + }, + { + "index": 966, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n// Function to remove empty elements\n\n", + "func": "char** func0(char** tuple1, int size, int* new_size) {\n char** result = malloc(size * sizeof(char*));\n int j = 0;\n for (int i = 0; i < size; i++) {\n if (tuple1[i] != NULL) {\n result[j++] = tuple1[i];\n }\n }\n *new_size = j;\n return result;\n}", + "test": "int main() {\n\n // First test case\n\n char* input1[] = {NULL, NULL, \"\", \"a,b\", \"a,b,c\", \"d\"};\n\n char* expected1[] = {\"\", \"a,b\", \"a,b,c\", \"d\"};\n\n int new_size1;\n\n char** output1 = func0(input1, 6, &new_size1);\n\n assert(new_size1 == 4);\n\n for(int i = 0; i < new_size1; i++) {\n\n assert(output1[i] == expected1[i]);\n\n }\n\n\n\n // Second test case\n\n char* input2[] = {NULL, NULL, \"\", \"python\", \"program\"};\n\n char* expected2[] = {\"\", \"python\", \"program\"};\n\n int new_size2;\n\n char** output2 = func0(input2, 5, &new_size2);\n\n assert(new_size2 == 3);\n\n for(int i = 0; i < new_size2; i++) {\n\n assert(output2[i] == expected2[i]);\n\n }\n\n\n\n // Third test case\n\n char* input3[] = {NULL, NULL, \"\", \"java\"};\n\n char* expected3[] = {\"\", \"java\"};\n\n int new_size3;\n\n char** output3 = func0(input3, 4, &new_size3);\n\n assert(new_size3 == 2);\n\n for(int i = 0; i < new_size3; i++) {\n\n assert(output3[i] == expected3[i]);\n\n }\n\n\n\n // Free allocated memory\n\n free(output1);\n\n free(output2);\n\n free(output3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %rdx,%r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nmovslq %esi,%rdi\nmov %rdi,%rbp\nshl $0x3,%rdi\ncallq 10b0 \ntest %ebp,%ebp\njle 1498 \nlea -0x1(%rbp),%edx\nmov %rbx,%rdi\nxor %esi,%esi\nlea 0x8(%rbx,%rdx,8),%r9\nxchg %ax,%ax\nmov (%rdi),%rcx\ntest %rcx,%rcx\nje 1482 \nmovslq %esi,%r8\nadd $0x1,%esi\nmov %rcx,(%rax,%r8,8)\nadd $0x8,%rdi\ncmp %r9,%rdi\njne 1470 \npop %rbx\npop %rbp\nmov %esi,(%r12)\npop %r12\nretq\nnopl 0x0(%rax)\nxor %esi,%esi\npop %rbx\npop %rbp\nmov %esi,(%r12)\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r13\nmovsxd r8, esi\nmov r13, rdx\npush r12\nmov r12, r8\npush rbp\nlea rbp, ds:0[r8*8]\npush rbx\nmov rbx, rdi\nmov rdi, rbp; size\nsub rsp, 8\ncall _malloc\ntest r12d, r12d\njle short loc_14D0\nmov rcx, rbx\nlea r8, [rbx+rbp]\nxor edi, edi\nnop dword ptr [rax+rax+00000000h]\nloc_14A0:\nmov rsi, [rcx]\ntest rsi, rsi\njz short loc_14B2\nmovsxd r9, edi\nadd edi, 1\nmov [rax+r9*8], rsi\nloc_14B2:\nadd rcx, 8\ncmp rcx, r8\njnz short loc_14A0\nmov [r13+0], edi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_14D0:\nxor edi, edi\nmov [r13+0], edi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(_QWORD *a1, int a2, _DWORD *a3)\n{\n _QWORD *result; // rax\n _QWORD *v6; // rcx\n int v7; // edi\n __int64 v8; // r9\n\n result = malloc(8LL * a2);\n if ( a2 <= 0 )\n {\n *a3 = 0;\n }\n else\n {\n v6 = a1;\n v7 = 0;\n do\n {\n if ( *v6 )\n {\n v8 = v7++;\n result[v8] = *v6;\n }\n ++v6;\n }\n while ( v6 != &a1[a2] );\n *a3 = v7;\n }\n return result;\n}", + "ida_strip_asm": "sub_1460:\nendbr64\npush r13\nmovsxd r8, esi\nmov r13, rdx\npush r12\nmov r12, r8\npush rbp\nlea rbp, ds:0[r8*8]\npush rbx\nmov rbx, rdi\nmov rdi, rbp; size\nsub rsp, 8\ncall _malloc\ntest r12d, r12d\njle short loc_14D0\nmov rcx, rbx\nlea r8, [rbx+rbp]\nxor edi, edi\nnop dword ptr [rax+rax+00000000h]\nloc_14A0:\nmov rsi, [rcx]\ntest rsi, rsi\njz short loc_14B2\nmovsxd r9, edi\nadd edi, 1\nmov [rax+r9*8], rsi\nloc_14B2:\nadd rcx, 8\ncmp rcx, r8\njnz short loc_14A0\nmov [r13+0], edi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_14D0:\nxor edi, edi\nmov [r13+0], edi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1460(_QWORD *a1, int a2, _DWORD *a3)\n{\n _QWORD *result; // rax\n _QWORD *v6; // rcx\n int v7; // edi\n __int64 v8; // r9\n\n result = malloc(8LL * a2);\n if ( a2 <= 0 )\n {\n *a3 = 0;\n }\n else\n {\n v6 = a1;\n v7 = 0;\n do\n {\n if ( *v6 )\n {\n v8 = v7++;\n result[v8] = *v6;\n }\n ++v6;\n }\n while ( v6 != &a1[a2] );\n *a3 = v7;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1460(uint64_t *a1, int a2, uint32_t *a3) {\n uint64_t *result;\n uint64_t *v6;\n int v7;\n long long v8;\n result = malloc(8LL * a2);\n if (a2 <= 0) {\n *a3 = 0;\n } else {\n v6 = a1;\n v7 = 0;\n do {\n if (*v6) {\n v8 = v7++;\n result[v8] = *v6;\n }\n ++v6;\n } while (v6 != &a1[a2]);\n *a3 = v7;\n }\n return result;\n}", + "ida_pseudo_norm": "uint64_t *func0(uint64_t *a1, int a2, uint32_t *a3) {\n uint64_t *result;\n uint64_t *v6;\n int v7;\n long long v8;\n result = malloc(8LL * a2);\n if (a2 <= 0) {\n *a3 = 0;\n } else {\n v6 = a1;\n v7 = 0;\n do {\n if (*v6) {\n v8 = v7++;\n result[v8] = *v6;\n }\n ++v6;\n } while (v6 != &a1[a2]);\n *a3 = v7;\n }\n return result;\n}" + }, + { + "index": 966, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n// Function to remove empty elements\n\n", + "func": "char** func0(char** tuple1, int size, int* new_size) {\n char** result = malloc(size * sizeof(char*));\n int j = 0;\n for (int i = 0; i < size; i++) {\n if (tuple1[i] != NULL) {\n result[j++] = tuple1[i];\n }\n }\n *new_size = j;\n return result;\n}", + "test": "int main() {\n\n // First test case\n\n char* input1[] = {NULL, NULL, \"\", \"a,b\", \"a,b,c\", \"d\"};\n\n char* expected1[] = {\"\", \"a,b\", \"a,b,c\", \"d\"};\n\n int new_size1;\n\n char** output1 = func0(input1, 6, &new_size1);\n\n assert(new_size1 == 4);\n\n for(int i = 0; i < new_size1; i++) {\n\n assert(output1[i] == expected1[i]);\n\n }\n\n\n\n // Second test case\n\n char* input2[] = {NULL, NULL, \"\", \"python\", \"program\"};\n\n char* expected2[] = {\"\", \"python\", \"program\"};\n\n int new_size2;\n\n char** output2 = func0(input2, 5, &new_size2);\n\n assert(new_size2 == 3);\n\n for(int i = 0; i < new_size2; i++) {\n\n assert(output2[i] == expected2[i]);\n\n }\n\n\n\n // Third test case\n\n char* input3[] = {NULL, NULL, \"\", \"java\"};\n\n char* expected3[] = {\"\", \"java\"};\n\n int new_size3;\n\n char** output3 = func0(input3, 4, &new_size3);\n\n assert(new_size3 == 2);\n\n for(int i = 0; i < new_size3; i++) {\n\n assert(output3[i] == expected3[i]);\n\n }\n\n\n\n // Free allocated memory\n\n free(output1);\n\n free(output2);\n\n free(output3);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\nmov %rdx,%r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nmovslq %esi,%rdi\nmov %rdi,%rbp\nshl $0x3,%rdi\ncallq 10b0 \ntest %ebp,%ebp\njle 14c8 \nlea -0x1(%rbp),%edx\nmov %rbx,%rdi\nxor %esi,%esi\nlea 0x8(%rbx,%rdx,8),%r9\nxchg %ax,%ax\nmov (%rdi),%rcx\ntest %rcx,%rcx\nje 14b2 \nmovslq %esi,%r8\nadd $0x1,%esi\nmov %rcx,(%rax,%r8,8)\nadd $0x8,%rdi\ncmp %r9,%rdi\njne 14a0 \npop %rbx\npop %rbp\nmov %esi,(%r12)\npop %r12\nretq\nnopl 0x0(%rax)\nxor %esi,%esi\npop %rbx\npop %rbp\nmov %esi,(%r12)\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\npush r13\nmovsxd r8, esi\nmov r13, rdx\npush r12\nmov r12, r8\npush rbp\nlea rbp, ds:0[r8*8]\npush rbx\nmov rbx, rdi\nmov rdi, rbp; size\nsub rsp, 8\ncall _malloc\ntest r12d, r12d\njle short loc_14C0\nmov rcx, rbx\nlea r8, [rbx+rbp]\nxor edi, edi\nnop dword ptr [rax+rax+00000000h]\nloc_1490:\nmov rsi, [rcx]\ntest rsi, rsi\njz short loc_14A2\nmovsxd r9, edi\nadd edi, 1\nmov [rax+r9*8], rsi\nloc_14A2:\nadd rcx, 8\ncmp rcx, r8\njnz short loc_1490\nmov [r13+0], edi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_14C0:\nxor edi, edi\nmov [r13+0], edi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_QWORD *__fastcall func0(_QWORD *a1, int a2, _DWORD *a3)\n{\n _QWORD *result; // rax\n _QWORD *v6; // rcx\n int v7; // edi\n __int64 v8; // r9\n\n result = malloc(8LL * a2);\n if ( a2 <= 0 )\n {\n *a3 = 0;\n }\n else\n {\n v6 = a1;\n v7 = 0;\n do\n {\n if ( *v6 )\n {\n v8 = v7++;\n result[v8] = *v6;\n }\n ++v6;\n }\n while ( v6 != &a1[a2] );\n *a3 = v7;\n }\n return result;\n}", + "ida_strip_asm": "sub_1450:\nendbr64\npush r13\nmovsxd r8, esi\nmov r13, rdx\npush r12\nmov r12, r8\npush rbp\nlea rbp, ds:0[r8*8]\npush rbx\nmov rbx, rdi\nmov rdi, rbp; size\nsub rsp, 8\ncall _malloc\ntest r12d, r12d\njle short loc_14C0\nmov rcx, rbx\nlea r8, [rbx+rbp]\nxor edi, edi\nnop dword ptr [rax+rax+00000000h]\nloc_1490:\nmov rsi, [rcx]\ntest rsi, rsi\njz short loc_14A2\nmovsxd r9, edi\nadd edi, 1\nmov [rax+r9*8], rsi\nloc_14A2:\nadd rcx, 8\ncmp rcx, r8\njnz short loc_1490\nmov [r13+0], edi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn\nloc_14C0:\nxor edi, edi\nmov [r13+0], edi\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_QWORD *__fastcall sub_1450(_QWORD *a1, int a2, _DWORD *a3)\n{\n _QWORD *result; // rax\n _QWORD *v6; // rcx\n int v7; // edi\n __int64 v8; // r9\n\n result = malloc(8LL * a2);\n if ( a2 <= 0 )\n {\n *a3 = 0;\n }\n else\n {\n v6 = a1;\n v7 = 0;\n do\n {\n if ( *v6 )\n {\n v8 = v7++;\n result[v8] = *v6;\n }\n ++v6;\n }\n while ( v6 != &a1[a2] );\n *a3 = v7;\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint64_t *sub_1450(uint64_t *a1, int a2, uint32_t *a3) {\n uint64_t *result;\n uint64_t *v6;\n int v7;\n long long v8;\n result = malloc(8LL * a2);\n if (a2 <= 0) {\n *a3 = 0;\n } else {\n v6 = a1;\n v7 = 0;\n do {\n if (*v6) {\n v8 = v7++;\n result[v8] = *v6;\n }\n ++v6;\n } while (v6 != &a1[a2]);\n *a3 = v7;\n }\n return result;\n}", + "ida_pseudo_norm": "uint64_t *func0(uint64_t *a1, int a2, uint32_t *a3) {\n uint64_t *result;\n uint64_t *v6;\n int v7;\n long long v8;\n result = malloc(8LL * a2);\n if (a2 <= 0) {\n *a3 = 0;\n } else {\n v6 = a1;\n v7 = 0;\n do {\n if (*v6) {\n v8 = v7++;\n result[v8] = *v6;\n }\n ++v6;\n } while (v6 != &a1[a2]);\n *a3 = v7;\n }\n return result;\n}" + }, + { + "index": 967, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "const char* func0(const char* string) {\n char vowels[] = \"AEIOUaeiou\";\n int count = 0;\n int found[10] = {0};\n for (int i = 0; string[i] != '\\0'; i++) {\n for (int j = 0; j < 10; j++) {\n if (string[i] == vowels[j] && found[j] == 0) {\n found[j] = 1;\n count++;\n break;\n }\n }\n }\n if (count >= 5) {\n return \"accepted\";\n } else {\n return \"not accepted\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"SEEquoiaL\"), \"accepted\") == 0);\n\n assert(strcmp(func0(\"program\"), \"not accepted\") == 0);\n\n assert(strcmp(func0(\"fine\"), \"not accepted\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x60,%rsp\nmov %rdi,-0x58(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmovabs $0x696561554f494541,%rax\nmov %rax,-0x13(%rbp)\nmovw $0x756f,-0xb(%rbp)\nmovb $0x0,-0x9(%rbp)\nmovl $0x0,-0x4c(%rbp)\nmovq $0x0,-0x40(%rbp)\nmovq $0x0,-0x38(%rbp)\nmovq $0x0,-0x30(%rbp)\nmovq $0x0,-0x28(%rbp)\nmovq $0x0,-0x20(%rbp)\nmovl $0x0,-0x48(%rbp)\njmp 124d \nmovl $0x0,-0x44(%rbp)\njmp 1243 \nmov -0x48(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x58(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%edx\nmov -0x44(%rbp),%eax\ncltq\nmovzbl -0x13(%rbp,%rax,1),%eax\ncmp %al,%dl\njne 123f \nmov -0x44(%rbp),%eax\ncltq\nmov -0x40(%rbp,%rax,4),%eax\ntest %eax,%eax\njne 123f \nmov -0x44(%rbp),%eax\ncltq\nmovl $0x1,-0x40(%rbp,%rax,4)\naddl $0x1,-0x4c(%rbp)\njmp 1249 \naddl $0x1,-0x44(%rbp)\ncmpl $0x9,-0x44(%rbp)\njle 1201 \naddl $0x1,-0x48(%rbp)\nmov -0x48(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x58(%rbp),%rax\nadd %rdx,%rax\nmovzbl (%rax),%eax\ntest %al,%al\njne 11f8 \ncmpl $0x4,-0x4c(%rbp)\njle 1270 \nlea 0xd9a(%rip),%rax\njmp 1277 \nlea 0xd9a(%rip),%rax\nmov -0x8(%rbp),%rcx\nxor %fs:0x28,%rcx\nje 128b \ncallq 1070 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 60h\nmov [rbp+var_58], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, 696561554F494541h\nmov [rbp+var_13], rax\nmov dword ptr [rbp+var_13+7], 756F69h\nmov [rbp+var_4C], 0\npxor xmm0, xmm0\nmovaps [rbp+var_40], xmm0\nmovaps [rbp+var_30], xmm0\nmovq [rbp+var_20], xmm0\nmov [rbp+var_48], 0\njmp short loc_1233\nloc_11DE:\nmov [rbp+var_44], 0\njmp short loc_1229\nloc_11E7:\nmov eax, [rbp+var_48]\nmovsxd rdx, eax\nmov rax, [rbp+var_58]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_44]\ncdqe\nmovzx eax, byte ptr [rbp+rax+var_13]\ncmp dl, al\njnz short loc_1225\nmov eax, [rbp+var_44]\ncdqe\nmov eax, dword ptr [rbp+rax*4+var_40]\ntest eax, eax\njnz short loc_1225\nmov eax, [rbp+var_44]\ncdqe\nmov dword ptr [rbp+rax*4+var_40], 1\nadd [rbp+var_4C], 1\njmp short loc_122F\nloc_1225:\nadd [rbp+var_44], 1\nloc_1229:\ncmp [rbp+var_44], 9\njle short loc_11E7\nloc_122F:\nadd [rbp+var_48], 1\nloc_1233:\nmov eax, [rbp+var_48]\nmovsxd rdx, eax\nmov rax, [rbp+var_58]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_11DE\ncmp [rbp+var_4C], 4\njle short loc_1256\nlea rax, s2; \"accepted\"\njmp short loc_125D\nloc_1256:\nlea rax, aNotAccepted; \"not accepted\"\nloc_125D:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1271\ncall ___stack_chk_fail\nlocret_1271:\nleave\nretn", + "ida_pseudo": "const char *__fastcall func0(__int64 a1)\n{\n int v2; // [rsp+14h] [rbp-4Ch]\n int i; // [rsp+18h] [rbp-48h]\n int j; // [rsp+1Ch] [rbp-44h]\n _OWORD v5[2]; // [rsp+20h] [rbp-40h] BYREF\n __int64 v6; // [rsp+40h] [rbp-20h]\n _BYTE v7[19]; // [rsp+4Dh] [rbp-13h] BYREF\n\n *(_QWORD *)&v7[11] = __readfsqword(0x28u);\n strcpy(v7, \"AEIOUaeiou\");\n v2 = 0;\n memset(v5, 0, sizeof(v5));\n v6 = 0LL;\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n {\n for ( j = 0; j <= 9; ++j )\n {\n if ( *(_BYTE *)(i + a1) == v7[j] && !*((_DWORD *)v5 + j) )\n {\n *((_DWORD *)v5 + j) = 1;\n ++v2;\n break;\n }\n }\n }\n if ( v2 <= 4 )\n return \"not accepted\";\n else\n return \"accepted\";\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 60h\nmov [rbp+var_58], rdi\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, 696561554F494541h\nmov [rbp+var_13], rax\nmov dword ptr [rbp+var_13+7], 756F69h\nmov [rbp+var_4C], 0\npxor xmm0, xmm0\nmovaps [rbp+var_40], xmm0\nmovaps [rbp+var_30], xmm0\nmovq [rbp+var_20], xmm0\nmov [rbp+var_48], 0\njmp short loc_1233\nloc_11DE:\nmov [rbp+var_44], 0\njmp short loc_1229\nloc_11E7:\nmov eax, [rbp+var_48]\nmovsxd rdx, eax\nmov rax, [rbp+var_58]\nadd rax, rdx\nmovzx edx, byte ptr [rax]\nmov eax, [rbp+var_44]\ncdqe\nmovzx eax, byte ptr [rbp+rax+var_13]\ncmp dl, al\njnz short loc_1225\nmov eax, [rbp+var_44]\ncdqe\nmov eax, dword ptr [rbp+rax*4+var_40]\ntest eax, eax\njnz short loc_1225\nmov eax, [rbp+var_44]\ncdqe\nmov dword ptr [rbp+rax*4+var_40], 1\nadd [rbp+var_4C], 1\njmp short loc_122F\nloc_1225:\nadd [rbp+var_44], 1\nloc_1229:\ncmp [rbp+var_44], 9\njle short loc_11E7\nloc_122F:\nadd [rbp+var_48], 1\nloc_1233:\nmov eax, [rbp+var_48]\nmovsxd rdx, eax\nmov rax, [rbp+var_58]\nadd rax, rdx\nmovzx eax, byte ptr [rax]\ntest al, al\njnz short loc_11DE\ncmp [rbp+var_4C], 4\njle short loc_1256\nlea rax, s2; \"accepted\"\njmp short loc_125D\nloc_1256:\nlea rax, aNotAccepted; \"not accepted\"\nloc_125D:\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_1271\ncall ___stack_chk_fail\nlocret_1271:\nleave\nretn", + "ida_strip_pseudo": "const char *__fastcall sub_1189(__int64 a1)\n{\n int v2; // [rsp+14h] [rbp-4Ch]\n int i; // [rsp+18h] [rbp-48h]\n int j; // [rsp+1Ch] [rbp-44h]\n _OWORD v5[2]; // [rsp+20h] [rbp-40h] BYREF\n __int64 v6; // [rsp+40h] [rbp-20h]\n _BYTE v7[19]; // [rsp+4Dh] [rbp-13h] BYREF\n\n *(_QWORD *)&v7[11] = __readfsqword(0x28u);\n strcpy(v7, \"AEIOUaeiou\");\n v2 = 0;\n memset(v5, 0, sizeof(v5));\n v6 = 0LL;\n for ( i = 0; *(_BYTE *)(i + a1); ++i )\n {\n for ( j = 0; j <= 9; ++j )\n {\n if ( *(_BYTE *)(i + a1) == v7[j] && !*((_DWORD *)v5 + j) )\n {\n *((_DWORD *)v5 + j) = 1;\n ++v2;\n break;\n }\n }\n }\n if ( v2 <= 4 )\n return \"not accepted\";\n else\n return \"accepted\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1189(long long a1) {\n int v2;\n int i;\n int j;\n long double v5[2];\n long long v6;\n uint8_t v7[19];\n *(uint64_t *)&v7[11] = __readfsqword(40u);\n strcpy(v7, \"AEIOUaeiou\");\n v2 = 0;\n memset(v5, 0, sizeof(v5));\n v6 = 0LL;\n for (i = 0; *(uint8_t *)(i + a1); ++i) {\n for (j = 0; j <= 9; ++j) {\n if (*(uint8_t *)(i + a1) == v7[j] && !*((uint32_t *)v5 + j)) {\n *((uint32_t *)v5 + j) = 1;\n ++v2;\n break;\n }\n }\n }\n if (v2 <= 4)\n return \"not accepted\";\n else\n return \"accepted\";\n}", + "ida_pseudo_norm": "const char *func0(long long a1) {\n int v2;\n int i;\n int j;\n long double v5[2];\n long long v6;\n uint8_t v7[19];\n *(uint64_t *)&v7[11] = __readfsqword(40u);\n strcpy(v7, \"AEIOUaeiou\");\n v2 = 0;\n memset(v5, 0, sizeof(v5));\n v6 = 0LL;\n for (i = 0; *(uint8_t *)(i + a1); ++i) {\n for (j = 0; j <= 9; ++j) {\n if (*(uint8_t *)(i + a1) == v7[j] && !*((uint32_t *)v5 + j)) {\n *((uint32_t *)v5 + j) = 1;\n ++v2;\n break;\n }\n }\n }\n if (v2 <= 4)\n return \"not accepted\";\n else\n return \"accepted\";\n}" + }, + { + "index": 967, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "const char* func0(const char* string) {\n char vowels[] = \"AEIOUaeiou\";\n int count = 0;\n int found[10] = {0};\n for (int i = 0; string[i] != '\\0'; i++) {\n for (int j = 0; j < 10; j++) {\n if (string[i] == vowels[j] && found[j] == 0) {\n found[j] = 1;\n count++;\n break;\n }\n }\n }\n if (count >= 5) {\n return \"accepted\";\n } else {\n return \"not accepted\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"SEEquoiaL\"), \"accepted\") == 0);\n\n assert(strcmp(func0(\"program\"), \"not accepted\") == 0);\n\n assert(strcmp(func0(\"fine\"), \"not accepted\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x48,%rsp\nmov %fs:0x28,%rax\nmov %rax,0x38(%rsp)\nxor %eax,%eax\nmovabs $0x696561554f494541,%rax\nmov %rax,0x2d(%rsp)\nmovw $0x756f,0x35(%rsp)\nmovb $0x0,0x37(%rsp)\nmovq $0x0,(%rsp)\nmovq $0x0,0x8(%rsp)\nmovq $0x0,0x10(%rsp)\nmovq $0x0,0x18(%rsp)\nmovq $0x0,0x20(%rsp)\nmovzbl (%rdi),%edx\nlea 0xe32(%rip),%rax\ntest %dl,%dl\nje 1237 \nadd $0x1,%rdi\nmov $0x0,%r9d\nlea 0x2d(%rsp),%rsi\nmov %rsp,%r8\njmp 121a \nadd $0x1,%rax\ncmp $0xa,%rax\nje 120e \ncmp %dl,(%rax,%rsi,1)\njne 11ea \ncmpl $0x0,(%r8,%rax,4)\njne 11ea \nmovslq %eax,%rcx\nmovl $0x1,(%rsp,%rcx,4)\nadd $0x1,%r9d\nadd $0x1,%rdi\nmovzbl -0x1(%rdi),%edx\ntest %dl,%dl\nje 1221 \nmov $0x0,%eax\njmp 11f4 \ncmp $0x4,%r9d\nlea 0xddc(%rip),%rax\nlea 0xdd1(%rip),%rdx\ncmovle %rdx,%rax\nmov 0x38(%rsp),%rdi\nxor %fs:0x28,%rdi\njne 124c \nadd $0x48,%rsp\nretq\ncallq 1060 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 48h\nmov rax, fs:28h\nmov [rsp+48h+var_10], rax\nxor eax, eax\nmov rax, 696561554F494541h\nmov [rsp+48h+var_1B], rax\nmov dword ptr [rsp+48h+var_1B+7], 756F69h\npxor xmm0, xmm0\nmovaps [rsp+48h+var_48], xmm0\nmovaps [rsp+48h+var_38], xmm0\nmov [rsp+48h+var_28], 0\nmovzx edx, byte ptr [rdi]\nlea rax, s2; \"not accepted\"\ntest dl, dl\njz short loc_123B\nlea rsi, [rdi+1]\nmov r8d, 0\nlea rcx, [rsp+48h+var_1B]\nmov rdi, rsp\njmp short loc_121E\nloc_11F0:\nadd rax, 1\ncmp rax, 0Ah\njz short loc_1212\nloc_11FA:\ncmp [rax+rcx], dl\njnz short loc_11F0\ncmp dword ptr [rdi+rax*4], 0\njnz short loc_11F0\ncdqe\nmov dword ptr [rsp+rax*4+48h+var_48], 1\nadd r8d, 1\nloc_1212:\nadd rsi, 1\nmovzx edx, byte ptr [rsi-1]\ntest dl, dl\njz short loc_1225\nloc_121E:\nmov eax, 0\njmp short loc_11FA\nloc_1225:\ncmp r8d, 5\nlea rax, s2; \"not accepted\"\nlea rdx, s2+4; \"accepted\"\ncmovge rax, rdx\nloc_123B:\nmov rdx, [rsp+48h+var_10]\nsub rdx, fs:28h\njnz short loc_1250\nadd rsp, 48h\nretn\nloc_1250:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *a1)\n{\n char v1; // dl\n const char *result; // rax\n char *v3; // rsi\n int v4; // r8d\n __int64 v5; // rax\n _OWORD v6[2]; // [rsp+0h] [rbp-48h] BYREF\n __int64 v7; // [rsp+20h] [rbp-28h]\n _QWORD v8[3]; // [rsp+2Dh] [rbp-1Bh] BYREF\n\n *(_QWORD *)((char *)&v8[1] + 3) = __readfsqword(0x28u);\n strcpy((char *)v8, \"AEIOUaeiou\");\n memset(v6, 0, sizeof(v6));\n v7 = 0LL;\n v1 = *a1;\n result = \"not accepted\";\n if ( *a1 )\n {\n v3 = a1 + 1;\n v4 = 0;\n do\n {\n v5 = 0LL;\n while ( *((_BYTE *)v8 + v5) != v1 || *((_DWORD *)v6 + v5) )\n {\n if ( ++v5 == 10 )\n goto LABEL_7;\n }\n *((_DWORD *)v6 + (int)v5) = 1;\n ++v4;\nLABEL_7:\n v1 = *v3++;\n }\n while ( v1 );\n result = \"not accepted\";\n if ( v4 >= 5 )\n return \"accepted\";\n }\n return result;\n}", + "ida_strip_asm": "sub_1189:\nendbr64\nsub rsp, 48h\nmov rax, fs:28h\nmov [rsp+48h+var_10], rax\nxor eax, eax\nmov rax, 696561554F494541h\nmov [rsp+48h+var_1B], rax\nmov dword ptr [rsp+48h+var_1B+7], 756F69h\npxor xmm0, xmm0\nmovaps [rsp+48h+var_48], xmm0\nmovaps [rsp+48h+var_38], xmm0\nmov [rsp+48h+var_28], 0\nmovzx edx, byte ptr [rdi]\nlea rax, s2; \"not accepted\"\ntest dl, dl\njz short loc_123B\nlea rsi, [rdi+1]\nmov r8d, 0\nlea rcx, [rsp+48h+var_1B]\nmov rdi, rsp\njmp short loc_121E\nloc_11F0:\nadd rax, 1\ncmp rax, 0Ah\njz short loc_1212\nloc_11FA:\ncmp [rax+rcx], dl\njnz short loc_11F0\ncmp dword ptr [rdi+rax*4], 0\njnz short loc_11F0\ncdqe\nmov dword ptr [rsp+rax*4+48h+var_48], 1\nadd r8d, 1\nloc_1212:\nadd rsi, 1\nmovzx edx, byte ptr [rsi-1]\ntest dl, dl\njz short loc_1225\nloc_121E:\nmov eax, 0\njmp short loc_11FA\nloc_1225:\ncmp r8d, 5\nlea rax, s2; \"not accepted\"\nlea rdx, s2+4; \"accepted\"\ncmovge rax, rdx\nloc_123B:\nmov rdx, [rsp+48h+var_10]\nsub rdx, fs:28h\njnz short loc_1250\nadd rsp, 48h\nretn\nloc_1250:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_1189(char *a1)\n{\n char v1; // dl\n const char *result; // rax\n char *v3; // rsi\n int v4; // r8d\n __int64 v5; // rax\n _OWORD v6[2]; // [rsp+0h] [rbp-48h] BYREF\n __int64 v7; // [rsp+20h] [rbp-28h]\n _QWORD v8[3]; // [rsp+2Dh] [rbp-1Bh] BYREF\n\n *(_QWORD *)((char *)&v8[1] + 3) = __readfsqword(0x28u);\n strcpy((char *)v8, \"AEIOUaeiou\");\n memset(v6, 0, sizeof(v6));\n v7 = 0LL;\n v1 = *a1;\n result = \"not accepted\";\n if ( *a1 )\n {\n v3 = a1 + 1;\n v4 = 0;\n do\n {\n v5 = 0LL;\n while ( *((_BYTE *)v8 + v5) != v1 || *((_DWORD *)v6 + v5) )\n {\n if ( ++v5 == 10 )\n goto LABEL_7;\n }\n *((_DWORD *)v6 + (int)v5) = 1;\n ++v4;\nLABEL_7:\n v1 = *v3++;\n }\n while ( v1 );\n result = \"not accepted\";\n if ( v4 >= 5 )\n return \"accepted\";\n }\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1189(char *a1) {\n char v1;\n const char *result;\n char *v3;\n int v4;\n long long v5;\n long double v6[2];\n long long v7;\n uint64_t v8[3];\n *(uint64_t *)((char *)&v8[1] + 3) = __readfsqword(40u);\n strcpy((char *)v8, \"AEIOUaeiou\");\n memset(v6, 0, sizeof(v6));\n v7 = 0LL;\n v1 = *a1;\n result = \"not accepted\";\n if (*a1) {\n v3 = a1 + 1;\n v4 = 0;\n do {\n v5 = 0LL;\n while (*((uint8_t *)v8 + v5) != v1 || *((uint32_t *)v6 + v5)) {\n if (++v5 == 10) goto LABEL_7;\n }\n *((uint32_t *)v6 + (int)v5) = 1;\n ++v4;\n LABEL_7:\n v1 = *v3++;\n } while (v1);\n result = \"not accepted\";\n if (v4 >= 5) return \"accepted\";\n }\n return result;\n}", + "ida_pseudo_norm": "const char *func0(char *a1) {\n char v1;\n const char *result;\n char *v3;\n int v4;\n long long v5;\n long double v6[2];\n long long v7;\n uint64_t v8[3];\n *(uint64_t *)((char *)&v8[1] + 3) = __readfsqword(40u);\n strcpy((char *)v8, \"AEIOUaeiou\");\n memset(v6, 0, sizeof(v6));\n v7 = 0LL;\n v1 = *a1;\n result = \"not accepted\";\n if (*a1) {\n v3 = a1 + 1;\n v4 = 0;\n do {\n v5 = 0LL;\n while (*((uint8_t *)v8 + v5) != v1 || *((uint32_t *)v6 + v5)) {\n if (++v5 == 10) goto LABEL_7;\n }\n *((uint32_t *)v6 + (int)v5) = 1;\n ++v4;\n LABEL_7:\n v1 = *v3++;\n } while (v1);\n result = \"not accepted\";\n if (v4 >= 5) return \"accepted\";\n }\n return result;\n}" + }, + { + "index": 967, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "const char* func0(const char* string) {\n char vowels[] = \"AEIOUaeiou\";\n int count = 0;\n int found[10] = {0};\n for (int i = 0; string[i] != '\\0'; i++) {\n for (int j = 0; j < 10; j++) {\n if (string[i] == vowels[j] && found[j] == 0) {\n found[j] = 1;\n count++;\n break;\n }\n }\n }\n if (count >= 5) {\n return \"accepted\";\n } else {\n return \"not accepted\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"SEEquoiaL\"), \"accepted\") == 0);\n\n assert(strcmp(func0(\"program\"), \"not accepted\") == 0);\n\n assert(strcmp(func0(\"fine\"), \"not accepted\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x48,%rsp\nmov $0x756f,%ecx\npxor %xmm0,%xmm0\nxor %r9d,%r9d\nmov %fs:0x28,%rax\nmov %rax,0x38(%rsp)\nxor %eax,%eax\nmov %cx,0x35(%rsp)\nmovzbl (%rdi),%ecx\nmov %rsp,%r8\nmovabs $0x696561554f494541,%rax\nmovb $0x0,0x37(%rsp)\nadd $0x1,%rdi\nmov %rax,0x2d(%rsp)\nmovq $0x0,0x20(%rsp)\nmovaps %xmm0,(%rsp)\nmovaps %xmm0,0x10(%rsp)\ntest %cl,%cl\nje 131d \nnopl (%rax)\nxor %eax,%eax\nmov $0x41,%edx\njmp 12cf \nnopl 0x0(%rax)\nadd $0x1,%rax\ncmp $0xa,%rax\nje 12f0 \nmovzbl 0x2d(%rsp,%rax,1),%edx\nmovslq %eax,%rsi\ncmp %cl,%dl\njne 12c0 \nmov (%r8,%rax,4),%edx\ntest %edx,%edx\njne 12c0 \nmovl $0x1,(%rsp,%rsi,4)\nadd $0x1,%r9d\nnopl 0x0(%rax)\nmovzbl (%rdi),%ecx\nadd $0x1,%rdi\ntest %cl,%cl\njne 12b0 \ncmp $0x4,%r9d\njle 131d \nlea 0xd00(%rip),%rax\nmov 0x38(%rsp),%rdi\nxor %fs:0x28,%rdi\njne 1326 \nadd $0x48,%rsp\nretq\nlea 0xce0(%rip),%rax\njmp 1308 \ncallq 1060 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 48h\nmovzx edx, byte ptr [rdi]\npxor xmm0, xmm0\nmov rax, fs:28h\nmov [rsp+48h+var_10], rax\nmov rax, 696561554F494541h\nmovaps [rsp+48h+var_48], xmm0\nmov [rsp+48h+var_28], 0\nmovaps [rsp+48h+var_38], xmm0\nmov [rsp+48h+var_1B], rax\nmov dword ptr [rsp+48h+var_1B+7], 756F69h\ntest dl, dl\njz short loc_131D\nlea rsi, [rdi+1]\nxor r8d, r8d\nlea rcx, [rsp+48h+var_1B]\nmov rdi, rsp\nnop dword ptr [rax+00000000h]\nloc_12C0:\nxor eax, eax\njmp short loc_12D2\nloc_12C8:\nadd rax, 1\ncmp rax, 0Ah\njz short loc_12F0\nloc_12D2:\ncmp [rcx+rax], dl\njnz short loc_12C8\nmov r9d, [rdi+rax*4]\ntest r9d, r9d\njnz short loc_12C8\ncdqe\nadd r8d, 1\nmov dword ptr [rsp+rax*4+48h+var_48], 1\nnop dword ptr [rax]\nloc_12F0:\nmovzx edx, byte ptr [rsi]\nadd rsi, 1\ntest dl, dl\njnz short loc_12C0\ncmp r8d, 4\njle short loc_131D\nlea rax, s2+4; \"accepted\"\nloc_1308:\nmov rdx, [rsp+48h+var_10]\nsub rdx, fs:28h\njnz short loc_1326\nadd rsp, 48h\nretn\nloc_131D:\nlea rax, s2; \"not accepted\"\njmp short loc_1308\nloc_1326:\ncall ___stack_chk_fail", + "ida_pseudo": "const char *__fastcall func0(char *a1)\n{\n char v1; // dl\n char *v2; // rsi\n int v3; // r8d\n __int64 v4; // rax\n _OWORD v6[2]; // [rsp+0h] [rbp-48h] BYREF\n __int64 v7; // [rsp+20h] [rbp-28h]\n _QWORD v8[3]; // [rsp+2Dh] [rbp-1Bh] BYREF\n\n v1 = *a1;\n *(_QWORD *)((char *)&v8[1] + 3) = __readfsqword(0x28u);\n memset(v6, 0, sizeof(v6));\n v7 = 0LL;\n strcpy((char *)v8, \"AEIOUaeiou\");\n if ( !v1 )\n return \"not accepted\";\n v2 = a1 + 1;\n v3 = 0;\n do\n {\n v4 = 0LL;\n while ( *((_BYTE *)v8 + v4) != v1 || *((_DWORD *)v6 + v4) )\n {\n if ( ++v4 == 10 )\n goto LABEL_8;\n }\n ++v3;\n *((_DWORD *)v6 + (int)v4) = 1;\nLABEL_8:\n v1 = *v2++;\n }\n while ( v1 );\n if ( v3 > 4 )\n return \"accepted\";\n else\n return \"not accepted\";\n}", + "ida_strip_asm": "sub_1260:\nendbr64\nsub rsp, 48h\nmovzx edx, byte ptr [rdi]\npxor xmm0, xmm0\nmov rax, fs:28h\nmov [rsp+48h+var_10], rax\nmov rax, 696561554F494541h\nmovaps [rsp+48h+var_48], xmm0\nmov [rsp+48h+var_28], 0\nmovaps [rsp+48h+var_38], xmm0\nmov [rsp+48h+var_1B], rax\nmov dword ptr [rsp+48h+var_1B+7], 756F69h\ntest dl, dl\njz short loc_131D\nlea rsi, [rdi+1]\nxor r8d, r8d\nlea rcx, [rsp+48h+var_1B]\nmov rdi, rsp\nnop dword ptr [rax+00000000h]\nloc_12C0:\nxor eax, eax\njmp short loc_12D2\nloc_12C8:\nadd rax, 1\ncmp rax, 0Ah\njz short loc_12F0\nloc_12D2:\ncmp [rcx+rax], dl\njnz short loc_12C8\nmov r9d, [rdi+rax*4]\ntest r9d, r9d\njnz short loc_12C8\ncdqe\nadd r8d, 1\nmov dword ptr [rsp+rax*4+48h+var_48], 1\nnop dword ptr [rax]\nloc_12F0:\nmovzx edx, byte ptr [rsi]\nadd rsi, 1\ntest dl, dl\njnz short loc_12C0\ncmp r8d, 4\njle short loc_131D\nlea rax, s2+4; \"accepted\"\nloc_1308:\nmov rdx, [rsp+48h+var_10]\nsub rdx, fs:28h\njnz short loc_1326\nadd rsp, 48h\nretn\nloc_131D:\nlea rax, s2; \"not accepted\"\njmp short loc_1308\nloc_1326:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "const char *__fastcall sub_1260(char *a1)\n{\n char v1; // dl\n char *v2; // rsi\n int v3; // r8d\n __int64 v4; // rax\n _OWORD v6[2]; // [rsp+0h] [rbp-48h] BYREF\n __int64 v7; // [rsp+20h] [rbp-28h]\n _QWORD v8[3]; // [rsp+2Dh] [rbp-1Bh] BYREF\n\n v1 = *a1;\n *(_QWORD *)((char *)&v8[1] + 3) = __readfsqword(0x28u);\n memset(v6, 0, sizeof(v6));\n v7 = 0LL;\n strcpy((char *)v8, \"AEIOUaeiou\");\n if ( !v1 )\n return \"not accepted\";\n v2 = a1 + 1;\n v3 = 0;\n do\n {\n v4 = 0LL;\n while ( *((_BYTE *)v8 + v4) != v1 || *((_DWORD *)v6 + v4) )\n {\n if ( ++v4 == 10 )\n goto LABEL_8;\n }\n ++v3;\n *((_DWORD *)v6 + (int)v4) = 1;\nLABEL_8:\n v1 = *v2++;\n }\n while ( v1 );\n if ( v3 > 4 )\n return \"accepted\";\n else\n return \"not accepted\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1260(char *a1) {\n char v1;\n char *v2;\n int v3;\n long long v4;\n long double v6[2];\n long long v7;\n uint64_t v8[3];\n v1 = *a1;\n *(uint64_t *)((char *)&v8[1] + 3) = __readfsqword(40u);\n memset(v6, 0, sizeof(v6));\n v7 = 0LL;\n strcpy((char *)v8, \"AEIOUaeiou\");\n if (!v1) return \"not accepted\";\n v2 = a1 + 1;\n v3 = 0;\n do {\n v4 = 0LL;\n while (*((uint8_t *)v8 + v4) != v1 || *((uint32_t *)v6 + v4)) {\n if (++v4 == 10) goto LABEL_8;\n }\n ++v3;\n *((uint32_t *)v6 + (int)v4) = 1;\n LABEL_8:\n v1 = *v2++;\n } while (v1);\n if (v3 > 4)\n return \"accepted\";\n else\n return \"not accepted\";\n}", + "ida_pseudo_norm": "const char *func0(char *a1) {\n char v1;\n char *v2;\n int v3;\n long long v4;\n long double v6[2];\n long long v7;\n uint64_t v8[3];\n v1 = *a1;\n *(uint64_t *)((char *)&v8[1] + 3) = __readfsqword(40u);\n memset(v6, 0, sizeof(v6));\n v7 = 0LL;\n strcpy((char *)v8, \"AEIOUaeiou\");\n if (!v1) return \"not accepted\";\n v2 = a1 + 1;\n v3 = 0;\n do {\n v4 = 0LL;\n while (*((uint8_t *)v8 + v4) != v1 || *((uint32_t *)v6 + v4)) {\n if (++v4 == 10) goto LABEL_8;\n }\n ++v3;\n *((uint32_t *)v6 + (int)v4) = 1;\n LABEL_8:\n v1 = *v2++;\n } while (v1);\n if (v3 > 4)\n return \"accepted\";\n else\n return \"not accepted\";\n}" + }, + { + "index": 967, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "const char* func0(const char* string) {\n char vowels[] = \"AEIOUaeiou\";\n int count = 0;\n int found[10] = {0};\n for (int i = 0; string[i] != '\\0'; i++) {\n for (int j = 0; j < 10; j++) {\n if (string[i] == vowels[j] && found[j] == 0) {\n found[j] = 1;\n count++;\n break;\n }\n }\n }\n if (count >= 5) {\n return \"accepted\";\n } else {\n return \"not accepted\";\n }\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"SEEquoiaL\"), \"accepted\") == 0);\n\n assert(strcmp(func0(\"program\"), \"not accepted\") == 0);\n\n assert(strcmp(func0(\"fine\"), \"not accepted\") == 0);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\nsub $0x38,%rsp\npxor %xmm0,%xmm0\nmov %fs:0x28,%rax\nmov %rax,0x28(%rsp)\nxor %eax,%eax\nmovzbl (%rdi),%eax\nmovaps %xmm0,(%rsp)\nmovq $0x0,0x20(%rsp)\nmovaps %xmm0,0x10(%rsp)\ntest %al,%al\nje 1478 \nlea 0x1(%rdi),%rdx\nxor %ecx,%ecx\njmp 12f3 \nnopl 0x0(%rax)\ncmp $0x45,%al\nje 1350 \ncmp $0x49,%al\nje 1370 \ncmp $0x4f,%al\nje 1390 \ncmp $0x55,%al\nje 13b8 \ncmp $0x61,%al\nje 13e0 \ncmp $0x65,%al\nje 1408 \ncmp $0x69,%al\nje 1430 \ncmp $0x6f,%al\njne 1450 \nmov 0x20(%rsp),%esi\ntest %esi,%esi\nje 1484 \nnopl 0x0(%rax)\nmovzbl (%rdx),%eax\nadd $0x1,%rdx\ntest %al,%al\nje 1320 \ncmp $0x41,%al\njne 1298 \nmovslq (%rsp),%rax\ntest %eax,%eax\njne 12e8 \nmovl $0x1,(%rsp,%rax,4)\nadd $0x1,%ecx\nnopl 0x0(%rax)\nmovzbl (%rdx),%eax\nadd $0x1,%rdx\ntest %al,%al\njne 12f3 \nnopl 0x0(%rax,%rax,1)\ncmp $0x4,%ecx\njle 1478 \nlea 0xcd8(%rip),%rax\nmov 0x28(%rsp),%rsi\nxor %fs:0x28,%rsi\njne 1498 \nadd $0x38,%rsp\nretq\nnopl 0x0(%rax)\nmov 0x4(%rsp),%eax\ntest %eax,%eax\njne 12e8 \nmov $0x1,%eax\nadd $0x1,%ecx\nmovl $0x1,(%rsp,%rax,4)\njmp 1310 \nnopl 0x0(%rax)\nmov 0x8(%rsp),%eax\ntest %eax,%eax\njne 12e8 \nmov $0x2,%eax\nadd $0x1,%ecx\nmovl $0x1,(%rsp,%rax,4)\njmp 1310 \nnopl (%rax)\nmov 0xc(%rsp),%r11d\ntest %r11d,%r11d\njne 12e8 \nmov $0x3,%eax\nadd $0x1,%ecx\nmovl $0x1,(%rsp,%rax,4)\njmpq 1310 \nnopw 0x0(%rax,%rax,1)\nmov 0x10(%rsp),%r10d\ntest %r10d,%r10d\njne 12e8 \nmov $0x4,%eax\nadd $0x1,%ecx\nmovl $0x1,(%rsp,%rax,4)\njmpq 1310 \nnopw 0x0(%rax,%rax,1)\nmov 0x14(%rsp),%r9d\ntest %r9d,%r9d\njne 12e8 \nmov $0x5,%eax\nadd $0x1,%ecx\nmovl $0x1,(%rsp,%rax,4)\njmpq 1310 \nnopw 0x0(%rax,%rax,1)\nmov 0x18(%rsp),%r8d\ntest %r8d,%r8d\njne 12e8 \nmov $0x6,%eax\nadd $0x1,%ecx\nmovl $0x1,(%rsp,%rax,4)\njmpq 1310 \nnopw 0x0(%rax,%rax,1)\nmov 0x1c(%rsp),%edi\ntest %edi,%edi\njne 12e8 \nmov $0x7,%eax\nadd $0x1,%ecx\nmovl $0x1,(%rsp,%rax,4)\njmpq 1310 \ncmp $0x75,%al\njne 12e8 \nmov 0x24(%rsp),%eax\ntest %eax,%eax\njne 12e8 \nmov $0x9,%eax\nadd $0x1,%ecx\nmovl $0x1,(%rsp,%rax,4)\njmpq 1310 \nlea 0xb85(%rip),%rax\njmpq 1330 \nmov $0x8,%eax\nadd $0x1,%ecx\nmovl $0x1,(%rsp,%rax,4)\njmpq 1310 \ncallq 1060 <__stack_chk_fail@plt>\nnopl (%rax)\n", + "ida_asm": "func0:\nendbr64\nsub rsp, 38h\npxor xmm0, xmm0\nmov rax, fs:28h\nmov [rsp+38h+var_10], rax\nxor eax, eax\nmovzx eax, byte ptr [rdi]\nmovaps [rsp+38h+var_38], xmm0\nmov [rsp+38h+var_18], 0\nmovaps [rsp+38h+var_28], xmm0\ntest al, al\njz loc_13B0\nlea rdx, [rdi+1]\nxor ecx, ecx\njmp short loc_12CB\nloc_12A8:\ncmp al, 45h ; 'E'\njnz short loc_1320\nmov eax, dword ptr [rsp+38h+var_38+4]\ntest eax, eax\njz loc_13BC\nnop dword ptr [rax+rax+00000000h]\nloc_12C0:\nmovzx eax, byte ptr [rdx]\nadd rdx, 1\ntest al, al\njz short loc_12F0\nloc_12CB:\ncmp al, 41h ; 'A'\njnz short loc_12A8\nmovsxd rax, dword ptr [rsp+38h+var_38]\ntest eax, eax\njnz short loc_12C0\nloc_12D7:\nmov dword ptr [rsp+rax*4+38h+var_38], 1\nadd ecx, 1\nloc_12E1:\nmovzx eax, byte ptr [rdx]\nadd rdx, 1\ntest al, al\njnz short loc_12CB\nnop dword ptr [rax+00h]\nloc_12F0:\ncmp ecx, 4\njle loc_13B0\nlea rax, s2+4; \"accepted\"\nloc_1300:\nmov rdx, [rsp+38h+var_10]\nsub rdx, fs:28h\njnz loc_13F6\nadd rsp, 38h\nretn\nloc_1320:\ncmp al, 49h ; 'I'\njnz short loc_1338\nmov eax, dword ptr [rsp+38h+var_38+8]\ntest eax, eax\njnz short loc_12C0\nmov eax, 2\njmp short loc_12D7\nloc_1338:\ncmp al, 4Fh ; 'O'\njz short loc_1370\ncmp al, 55h ; 'U'\njz short loc_1390\ncmp al, 61h ; 'a'\njnz loc_13D0\nmov r9d, dword ptr [rsp+38h+var_28+4]\ntest r9d, r9d\njnz loc_12C0\nmov eax, 5\nadd ecx, 1\nmov dword ptr [rsp+rax*4+38h+var_38], 1\njmp loc_12E1\nloc_1370:\nmov r11d, dword ptr [rsp+38h+var_38+0Ch]\ntest r11d, r11d\njnz loc_12C0\nmov eax, 3\njmp loc_12D7\nloc_1390:\nmov r10d, dword ptr [rsp+38h+var_28]\ntest r10d, r10d\njnz loc_12C0\nmov eax, 4\njmp loc_12D7\nloc_13B0:\nlea rax, s2; \"not accepted\"\njmp loc_1300\nloc_13BC:\nmov eax, 1\nadd ecx, 1\nmov dword ptr [rsp+rax*4+38h+var_38], 1\njmp loc_12E1\nloc_13D0:\ncmp al, 65h ; 'e'\njnz short loc_13FB\nmov r8d, dword ptr [rsp+38h+var_28+8]\ntest r8d, r8d\njnz loc_12C0\nmov eax, 6\nadd ecx, 1\nmov dword ptr [rsp+rax*4+38h+var_38], 1\njmp loc_12E1\nloc_13F6:\ncall ___stack_chk_fail\nloc_13FB:\ncmp al, 69h ; 'i'\njz short loc_1430\ncmp al, 6Fh ; 'o'\njz short loc_1450\ncmp al, 75h ; 'u'\njnz loc_12C0\nmov eax, dword ptr [rsp+38h+var_18+4]\ntest eax, eax\njnz loc_12C0\nmov eax, 9\nadd ecx, 1\nmov dword ptr [rsp+rax*4+38h+var_38], 1\njmp loc_12E1\nloc_1430:\nmov edi, dword ptr [rsp+38h+var_28+0Ch]\ntest edi, edi\njnz loc_12C0\nmov eax, 7\nadd ecx, 1\nmov dword ptr [rsp+rax*4+38h+var_38], 1\njmp loc_12E1\nloc_1450:\nmov esi, dword ptr [rsp+38h+var_18]\ntest esi, esi\njnz loc_12C0\nmov eax, 8\nadd ecx, 1\nmov dword ptr [rsp+rax*4+38h+var_38], 1\njmp loc_12E1", + "ida_pseudo": "const char *__fastcall func0(char *a1)\n{\n char v1; // al\n char *v2; // rdx\n int v3; // ecx\n __int64 v4; // rax\n __int128 v6; // [rsp+0h] [rbp-38h]\n __int128 v7; // [rsp+10h] [rbp-28h]\n __int64 v8; // [rsp+20h] [rbp-18h]\n unsigned __int64 v9; // [rsp+28h] [rbp-10h]\n\n v9 = __readfsqword(0x28u);\n v1 = *a1;\n v6 = 0LL;\n v8 = 0LL;\n v7 = 0LL;\n if ( !v1 )\n return \"not accepted\";\n v2 = a1 + 1;\n v3 = 0;\n do\n {\n while ( 1 )\n {\n if ( v1 == 65 )\n {\n v4 = (int)v6;\n if ( !(_DWORD)v6 )\n goto LABEL_8;\n goto LABEL_5;\n }\n if ( v1 == 69 )\n break;\n switch ( v1 )\n {\n case 'I':\n if ( !DWORD2(v6) )\n {\n v4 = 2LL;\nLABEL_8:\n *((_DWORD *)&v6 + v4) = 1;\n ++v3;\n goto LABEL_9;\n }\n break;\n case 'O':\n if ( !HIDWORD(v6) )\n {\n v4 = 3LL;\n goto LABEL_8;\n }\n break;\n case 'U':\n if ( !(_DWORD)v7 )\n {\n v4 = 4LL;\n goto LABEL_8;\n }\n break;\n default:\n switch ( v1 )\n {\n case 'a':\n if ( DWORD1(v7) )\n goto LABEL_5;\n ++v3;\n DWORD1(v7) = 1;\n break;\n case 'e':\n if ( DWORD2(v7) )\n goto LABEL_5;\n ++v3;\n DWORD2(v7) = 1;\n break;\n case 'i':\n if ( HIDWORD(v7) )\n goto LABEL_5;\n ++v3;\n HIDWORD(v7) = 1;\n break;\n case 'o':\n if ( (_DWORD)v8 )\n goto LABEL_5;\n ++v3;\n LODWORD(v8) = 1;\n break;\n default:\n if ( v1 != 117 || HIDWORD(v8) )\n goto LABEL_5;\n ++v3;\n HIDWORD(v8) = 1;\n break;\n }\n goto LABEL_9;\n }\nLABEL_5:\n v1 = *v2++;\n if ( !v1 )\n goto LABEL_10;\n }\n if ( DWORD1(v6) )\n goto LABEL_5;\n ++v3;\n DWORD1(v6) = 1;\nLABEL_9:\n v1 = *v2++;\n }\n while ( v1 );\nLABEL_10:\n if ( v3 > 4 )\n return \"accepted\";\n return \"not accepted\";\n}", + "ida_strip_asm": "sub_1260:\nendbr64\nsub rsp, 38h\npxor xmm0, xmm0\nmov rax, fs:28h\nmov [rsp+38h+var_10], rax\nxor eax, eax\nmovzx eax, byte ptr [rdi]\nmovaps [rsp+38h+var_38], xmm0\nmov [rsp+38h+var_18], 0\nmovaps [rsp+38h+var_28], xmm0\ntest al, al\njz loc_13B0\nlea rdx, [rdi+1]\nxor ecx, ecx\njmp short loc_12CB\nloc_12A8:\ncmp al, 45h ; 'E'\njnz short loc_1320\nmov eax, dword ptr [rsp+38h+var_38+4]\ntest eax, eax\njz loc_13BC\nnop dword ptr [rax+rax+00000000h]\nloc_12C0:\nmovzx eax, byte ptr [rdx]\nadd rdx, 1\ntest al, al\njz short loc_12F0\nloc_12CB:\ncmp al, 41h ; 'A'\njnz short loc_12A8\nmovsxd rax, dword ptr [rsp+38h+var_38]\ntest eax, eax\njnz short loc_12C0\nloc_12D7:\nmov dword ptr [rsp+rax*4+38h+var_38], 1\nadd ecx, 1\nloc_12E1:\nmovzx eax, byte ptr [rdx]\nadd rdx, 1\ntest al, al\njnz short loc_12CB\nnop dword ptr [rax+00h]\nloc_12F0:\ncmp ecx, 4\njle loc_13B0\nlea rax, s2+4; \"accepted\"\nloc_1300:\nmov rdx, [rsp+38h+var_10]\nsub rdx, fs:28h\njnz loc_13F6\nadd rsp, 38h\nretn\nloc_1320:\ncmp al, 49h ; 'I'\njnz short loc_1338\nmov eax, dword ptr [rsp+38h+var_38+8]\ntest eax, eax\njnz short loc_12C0\nmov eax, 2\njmp short loc_12D7\nloc_1338:\ncmp al, 4Fh ; 'O'\njz short loc_1370\ncmp al, 55h ; 'U'\njz short loc_1390\ncmp al, 61h ; 'a'\njnz loc_13D0\nmov r9d, dword ptr [rsp+38h+var_28+4]\ntest r9d, r9d\njnz loc_12C0\nmov eax, 5\nadd ecx, 1\nmov dword ptr [rsp+rax*4+38h+var_38], 1\njmp loc_12E1\nloc_1370:\nmov r11d, dword ptr [rsp+38h+var_38+0Ch]\ntest r11d, r11d\njnz loc_12C0\nmov eax, 3\njmp loc_12D7\nloc_1390:\nmov r10d, dword ptr [rsp+38h+var_28]\ntest r10d, r10d\njnz loc_12C0\nmov eax, 4\njmp loc_12D7\nloc_13B0:\nlea rax, s2; \"not accepted\"\njmp loc_1300\nloc_13BC:\nmov eax, 1\nadd ecx, 1\nmov dword ptr [rsp+rax*4+38h+var_38], 1\njmp loc_12E1\nloc_13D0:\ncmp al, 65h ; 'e'\njnz short loc_13FB\nmov r8d, dword ptr [rsp+38h+var_28+8]\ntest r8d, r8d\njnz loc_12C0\nmov eax, 6\nadd ecx, 1\nmov dword ptr [rsp+rax*4+38h+var_38], 1\njmp loc_12E1\nloc_13F6:\ncall ___stack_chk_fail\nloc_13FB:\ncmp al, 69h ; 'i'\njz short loc_1430\ncmp al, 6Fh ; 'o'\njz short loc_1450\ncmp al, 75h ; 'u'\njnz loc_12C0\nmov eax, dword ptr [rsp+38h+var_18+4]\ntest eax, eax\njnz loc_12C0\nmov eax, 9\nadd ecx, 1\nmov dword ptr [rsp+rax*4+38h+var_38], 1\njmp loc_12E1\nloc_1430:\nmov edi, dword ptr [rsp+38h+var_28+0Ch]\ntest edi, edi\njnz loc_12C0\nmov eax, 7\nadd ecx, 1\nmov dword ptr [rsp+rax*4+38h+var_38], 1\njmp loc_12E1\nloc_1450:\nmov esi, dword ptr [rsp+38h+var_18]\ntest esi, esi\njnz loc_12C0\nmov eax, 8\nadd ecx, 1\nmov dword ptr [rsp+rax*4+38h+var_38], 1\njmp loc_12E1", + "ida_strip_pseudo": "const char *__fastcall sub_1260(char *a1)\n{\n char v1; // al\n char *v2; // rdx\n int v3; // ecx\n __int64 v4; // rax\n __int128 v6; // [rsp+0h] [rbp-38h]\n __int128 v7; // [rsp+10h] [rbp-28h]\n __int64 v8; // [rsp+20h] [rbp-18h]\n unsigned __int64 v9; // [rsp+28h] [rbp-10h]\n\n v9 = __readfsqword(0x28u);\n v1 = *a1;\n v6 = 0LL;\n v8 = 0LL;\n v7 = 0LL;\n if ( !v1 )\n return \"not accepted\";\n v2 = a1 + 1;\n v3 = 0;\n do\n {\n while ( 1 )\n {\n if ( v1 == 65 )\n {\n v4 = (int)v6;\n if ( !(_DWORD)v6 )\n goto LABEL_8;\n goto LABEL_5;\n }\n if ( v1 == 69 )\n break;\n switch ( v1 )\n {\n case 'I':\n if ( !DWORD2(v6) )\n {\n v4 = 2LL;\nLABEL_8:\n *((_DWORD *)&v6 + v4) = 1;\n ++v3;\n goto LABEL_9;\n }\n break;\n case 'O':\n if ( !HIDWORD(v6) )\n {\n v4 = 3LL;\n goto LABEL_8;\n }\n break;\n case 'U':\n if ( !(_DWORD)v7 )\n {\n v4 = 4LL;\n goto LABEL_8;\n }\n break;\n default:\n switch ( v1 )\n {\n case 'a':\n if ( DWORD1(v7) )\n goto LABEL_5;\n ++v3;\n DWORD1(v7) = 1;\n break;\n case 'e':\n if ( DWORD2(v7) )\n goto LABEL_5;\n ++v3;\n DWORD2(v7) = 1;\n break;\n case 'i':\n if ( HIDWORD(v7) )\n goto LABEL_5;\n ++v3;\n HIDWORD(v7) = 1;\n break;\n case 'o':\n if ( (_DWORD)v8 )\n goto LABEL_5;\n ++v3;\n LODWORD(v8) = 1;\n break;\n default:\n if ( v1 != 117 || HIDWORD(v8) )\n goto LABEL_5;\n ++v3;\n HIDWORD(v8) = 1;\n break;\n }\n goto LABEL_9;\n }\nLABEL_5:\n v1 = *v2++;\n if ( !v1 )\n goto LABEL_10;\n }\n if ( DWORD1(v6) )\n goto LABEL_5;\n ++v3;\n DWORD1(v6) = 1;\nLABEL_9:\n v1 = *v2++;\n }\n while ( v1 );\nLABEL_10:\n if ( v3 > 4 )\n return \"accepted\";\n return \"not accepted\";\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "const char *sub_1260(char *a1) {\n char v1;\n char *v2;\n int v3;\n long long v4;\n __int128 v6;\n __int128 v7;\n long long v8;\n unsigned long long v9;\n v9 = __readfsqword(40u);\n v1 = *a1;\n v6 = 0LL;\n v8 = 0LL;\n v7 = 0LL;\n if (!v1) return \"not accepted\";\n v2 = a1 + 1;\n v3 = 0;\n do {\n while (1) {\n if (v1 == 65) {\n v4 = (int)v6;\n if (!(uint32_t)v6) goto LABEL_8;\n goto LABEL_5;\n }\n if (v1 == 69) break;\n switch (v1) {\n case 'I':\n if (!DWORD2(v6)) {\n v4 = 2LL;\n LABEL_8:\n *((uint32_t *)&v6 + v4) = 1;\n ++v3;\n goto LABEL_9;\n }\n break;\n case 'O':\n if (!HIDWORD(v6)) {\n v4 = 3LL;\n goto LABEL_8;\n }\n break;\n case 'U':\n if (!(uint32_t)v7) {\n v4 = 4LL;\n goto LABEL_8;\n }\n break;\n default:\n switch (v1) {\n case 'a':\n if (DWORD1(v7)) goto LABEL_5;\n ++v3;\n DWORD1(v7) = 1;\n break;\n case 'e':\n if (DWORD2(v7)) goto LABEL_5;\n ++v3;\n DWORD2(v7) = 1;\n break;\n case 'i':\n if (HIDWORD(v7)) goto LABEL_5;\n ++v3;\n HIDWORD(v7) = 1;\n break;\n case 'o':\n if ((uint32_t)v8) goto LABEL_5;\n ++v3;\n LODWORD(v8) = 1;\n break;\n default:\n if (v1 != 117 || HIDWORD(v8)) goto LABEL_5;\n ++v3;\n HIDWORD(v8) = 1;\n break;\n }\n goto LABEL_9;\n }\n LABEL_5:\n v1 = *v2++;\n if (!v1) goto LABEL_10;\n }\n if (DWORD1(v6)) goto LABEL_5;\n ++v3;\n DWORD1(v6) = 1;\n LABEL_9:\n v1 = *v2++;\n } while (v1);\nLABEL_10:\n if (v3 > 4) return \"accepted\";\n return \"not accepted\";\n}", + "ida_pseudo_norm": "const char *func0(char *a1) {\n char v1;\n char *v2;\n int v3;\n long long v4;\n __int128 v6;\n __int128 v7;\n long long v8;\n unsigned long long v9;\n v9 = __readfsqword(40u);\n v1 = *a1;\n v6 = 0LL;\n v8 = 0LL;\n v7 = 0LL;\n if (!v1) return \"not accepted\";\n v2 = a1 + 1;\n v3 = 0;\n do {\n while (1) {\n if (v1 == 65) {\n v4 = (int)v6;\n if (!(uint32_t)v6) goto LABEL_8;\n goto LABEL_5;\n }\n if (v1 == 69) break;\n switch (v1) {\n case 'I':\n if (!DWORD2(v6)) {\n v4 = 2LL;\n LABEL_8:\n *((uint32_t *)&v6 + v4) = 1;\n ++v3;\n goto LABEL_9;\n }\n break;\n case 'O':\n if (!HIDWORD(v6)) {\n v4 = 3LL;\n goto LABEL_8;\n }\n break;\n case 'U':\n if (!(uint32_t)v7) {\n v4 = 4LL;\n goto LABEL_8;\n }\n break;\n default:\n switch (v1) {\n case 'a':\n if (DWORD1(v7)) goto LABEL_5;\n ++v3;\n DWORD1(v7) = 1;\n break;\n case 'e':\n if (DWORD2(v7)) goto LABEL_5;\n ++v3;\n DWORD2(v7) = 1;\n break;\n case 'i':\n if (HIDWORD(v7)) goto LABEL_5;\n ++v3;\n HIDWORD(v7) = 1;\n break;\n case 'o':\n if ((uint32_t)v8) goto LABEL_5;\n ++v3;\n LODWORD(v8) = 1;\n break;\n default:\n if (v1 != 117 || HIDWORD(v8)) goto LABEL_5;\n ++v3;\n HIDWORD(v8) = 1;\n break;\n }\n goto LABEL_9;\n }\n LABEL_5:\n v1 = *v2++;\n if (!v1) goto LABEL_10;\n }\n if (DWORD1(v6)) goto LABEL_5;\n ++v3;\n DWORD1(v6) = 1;\n LABEL_9:\n v1 = *v2++;\n } while (v1);\nLABEL_10:\n if (v3 > 4) return \"accepted\";\n return \"not accepted\";\n}" + }, + { + "index": 968, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int A, int B, int N) {\n int x = (B - 1 < N) ? (B - 1) : N;\n return (A * x) / B;\n}", + "test": "int main() {\n\n assert(func0(11, 10, 9) == 9);\n\n assert(func0(5, 7, 4) == 2);\n\n assert(func0(2, 2, 1) == 1);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x14(%rbp)\nmov %esi,-0x18(%rbp)\nmov %edx,-0x1c(%rbp)\nmov -0x18(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njg 116a \nmov -0x18(%rbp),%eax\nsub $0x1,%eax\njmp 116d \nmov -0x1c(%rbp),%eax\nmov %eax,-0x4(%rbp)\nmov -0x14(%rbp),%eax\nimul -0x4(%rbp),%eax\ncltd\nidivl -0x18(%rbp)\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_1C]\njg short loc_116A\nmov eax, [rbp+var_18]\nsub eax, 1\njmp short loc_116D\nloc_116A:\nmov eax, [rbp+var_1C]\nloc_116D:\nmov [rbp+var_4], eax\nmov eax, [rbp+var_14]\nimul eax, [rbp+var_4]\ncdq\nidiv [rbp+var_18]\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, int a3)\n{\n int v3; // eax\n\n if ( a2 > a3 )\n v3 = a3;\n else\n v3 = a2 - 1;\n return (unsigned int)(v3 * a1 / a2);\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_14], edi\nmov [rbp+var_18], esi\nmov [rbp+var_1C], edx\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_1C]\njg short loc_116A\nmov eax, [rbp+var_18]\nsub eax, 1\njmp short loc_116D\nloc_116A:\nmov eax, [rbp+var_1C]\nloc_116D:\nmov [rbp+var_4], eax\nmov eax, [rbp+var_14]\nimul eax, [rbp+var_4]\ncdq\nidiv [rbp+var_18]\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(int a1, int a2, int a3)\n{\n int v3; // eax\n\n if ( a2 > a3 )\n v3 = a3;\n else\n v3 = a2 - 1;\n return (unsigned int)(v3 * a1 / a2);\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(int a1, int a2, int a3) {\n int v3;\n if (a2 > a3)\n v3 = a3;\n else\n v3 = a2 - 1;\n return (unsigned int)(v3 * a1 / a2);\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, int a3) {\n int v3;\n if (a2 > a3)\n v3 = a3;\n else\n v3 = a2 - 1;\n return (unsigned int)(v3 * a1 / a2);\n}" + }, + { + "index": 969, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int size;\n\n int *elements;\n\n} tuple;\n\n\n\n", + "func": "tuple* func0(tuple test_list[], int list_size) {\n tuple* res = malloc(sizeof(tuple) * list_size);\n int res_size = 0;\n for (int i = 0; i < list_size; i++) {\n if (res_size > 0 &&\n res[res_size - 1].elements[0] == test_list[i].elements[0]) {\n int last_size = res[res_size - 1].size;\n int this_size = test_list[i].size;\n res[res_size - 1].elements =\n realloc(res[res_size - 1].elements,\n sizeof(int) * (last_size + this_size - 1));\n for (int j = 1; j < this_size; j++) {\n res[res_size - 1].elements[last_size + j - 1] =\n test_list[i].elements[j];\n }\n res[res_size - 1].size = last_size + this_size - 1;\n } else {\n res[res_size].elements = malloc(sizeof(int) * test_list[i].size);\n for (int j = 0; j < test_list[i].size; j++) {\n res[res_size].elements[j] = test_list[i].elements[j];\n }\n res[res_size].size = test_list[i].size;\n res_size++;\n }\n }\n return res;\n}", + "test": "int main() {\n\n tuple list1[] = {{2, (int[]){5, 6}}, {2, (int[]){5, 7}}, {2, (int[]){6, 8}}, {2, (int[]){6, 10}}, {2, (int[]){7, 13}}};\n\n tuple *result1 = func0(list1, 5);\n\n assert(result1[0].size == 3 && (result1[0].elements[0] == 5 && result1[0].elements[1] == 6 && result1[0].elements[2] == 7));\n\n assert(result1[1].size == 3 && (result1[1].elements[0] == 6 && result1[1].elements[1] == 8 && result1[1].elements[2] == 10));\n\n assert(result1[2].size == 2 && (result1[2].elements[0] == 7 && result1[2].elements[1] == 13));\n\n\n\n tuple list2[] = {{2, (int[]){6, 7}}, {2, (int[]){6, 8}}, {2, (int[]){7, 9}}, {2, (int[]){7, 11}}, {2, (int[]){8, 14}}};\n\n tuple *result2 = func0(list2, 5);\n\n assert(result2[0].size == 3 && (result2[0].elements[0] == 6 && result2[0].elements[1] == 7 && result2[0].elements[2] == 8));\n\n assert(result2[1].size == 3 && (result2[1].elements[0] == 7 && result2[1].elements[1] == 9 && result2[1].elements[2] == 11));\n\n assert(result2[2].size == 2 && (result2[2].elements[0] == 8 && result2[2].elements[1] == 14));\n\n\n\n tuple list3[] = {{2, (int[]){7, 8}}, {2, (int[]){7, 9}}, {2, (int[]){8, 10}}, {2, (int[]){8, 12}}, {2, (int[]){9, 15}}};\n\n tuple *result3 = func0(list3, 5);\n\n assert(result3[0].size == 3 && (result3[0].elements[0] == 7 && result3[0].elements[1] == 8 && result3[0].elements[2] == 9));\n\n assert(result3[1].size == 3 && (result3[1].elements[0] == 8 && result3[1].elements[1] == 10 && result3[1].elements[2] == 12));\n\n assert(result3[2].size == 2 && (result3[2].elements[0] == 9 && result3[2].elements[1] == 15));\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nsub $0x38,%rsp\nmov %rdi,-0x38(%rbp)\nmov %esi,-0x3c(%rbp)\nmov -0x3c(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdi\ncallq 10c0 \nmov %rax,-0x18(%rbp)\nmovl $0x0,-0x30(%rbp)\nmovl $0x0,-0x2c(%rbp)\njmpq 1442 \ncmpl $0x0,-0x30(%rbp)\njle 135f \nmov -0x30(%rbp),%eax\ncltq\nshl $0x4,%rax\nlea -0x10(%rax),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov 0x8(%rax),%rax\nmov (%rax),%edx\nmov -0x2c(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rcx\nmov -0x38(%rbp),%rax\nadd %rcx,%rax\nmov 0x8(%rax),%rax\nmov (%rax),%eax\ncmp %eax,%edx\njne 135f \nmov -0x30(%rbp),%eax\ncltq\nshl $0x4,%rax\nlea -0x10(%rax),%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x20(%rbp)\nmov -0x2c(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\nmov %eax,-0x1c(%rbp)\nmov -0x20(%rbp),%edx\nmov -0x1c(%rbp),%eax\nadd %edx,%eax\nsub $0x1,%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x30(%rbp),%eax\ncltq\nshl $0x4,%rax\nlea -0x10(%rax),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nmov 0x8(%rax),%rax\nmov -0x30(%rbp),%ecx\nmovslq %ecx,%rcx\nshl $0x4,%rcx\nlea -0x10(%rcx),%rsi\nmov -0x18(%rbp),%rcx\nlea (%rsi,%rcx,1),%rbx\nmov %rdx,%rsi\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,0x8(%rbx)\nmovl $0x1,-0x28(%rbp)\njmp 1331 \nmov -0x2c(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov 0x8(%rax),%rax\nmov -0x28(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x2,%rdx\nadd %rdx,%rax\nmov -0x30(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x4,%rdx\nlea -0x10(%rdx),%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmov 0x8(%rdx),%rdx\nmov -0x20(%rbp),%esi\nmov -0x28(%rbp),%ecx\nadd %esi,%ecx\nmovslq %ecx,%rcx\nshl $0x2,%rcx\nsub $0x4,%rcx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x28(%rbp)\nmov -0x28(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njl 12d6 \nmov -0x20(%rbp),%edx\nmov -0x1c(%rbp),%eax\nadd %eax,%edx\nmov -0x30(%rbp),%eax\ncltq\nshl $0x4,%rax\nlea -0x10(%rax),%rcx\nmov -0x18(%rbp),%rax\nadd %rcx,%rax\nsub $0x1,%edx\nmov %edx,(%rax)\njmpq 143e \nmov -0x2c(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncltq\nshl $0x2,%rax\nmov -0x30(%rbp),%edx\nmovslq %edx,%rdx\nmov %rdx,%rcx\nshl $0x4,%rcx\nmov -0x18(%rbp),%rdx\nlea (%rcx,%rdx,1),%rbx\nmov %rax,%rdi\ncallq 10c0 \nmov %rax,0x8(%rbx)\nmovl $0x0,-0x24(%rbp)\njmp 13f5 \nmov -0x2c(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov 0x8(%rax),%rax\nmov -0x24(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x2,%rdx\nadd %rdx,%rax\nmov -0x30(%rbp),%edx\nmovslq %edx,%rdx\nmov %rdx,%rcx\nshl $0x4,%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmov 0x8(%rdx),%rdx\nmov -0x24(%rbp),%ecx\nmovslq %ecx,%rcx\nshl $0x2,%rcx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x24(%rbp)\nmov -0x2c(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%eax\ncmp %eax,-0x24(%rbp)\njl 13a4 \nmov -0x2c(%rbp),%eax\ncltq\nshl $0x4,%rax\nmov %rax,%rdx\nmov -0x38(%rbp),%rax\nadd %rdx,%rax\nmov -0x30(%rbp),%edx\nmovslq %edx,%rdx\nmov %rdx,%rcx\nshl $0x4,%rcx\nmov -0x18(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x30(%rbp)\naddl $0x1,-0x2c(%rbp)\nmov -0x2c(%rbp),%eax\ncmp -0x3c(%rbp),%eax\njl 1205 \nmov -0x18(%rbp),%rax\nadd $0x38,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov eax, [rbp+var_3C]\ncdqe\nshl rax, 4\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_30], 0\nmov [rbp+var_2C], 0\njmp loc_1442\nloc_1205:\ncmp [rbp+var_30], 0\njle loc_135F\nmov eax, [rbp+var_30]\ncdqe\nshl rax, 4\nlea rdx, [rax-10h]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax+8]\nmov edx, [rax]\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 4\nmov rcx, rax\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov rax, [rax+8]\nmov eax, [rax]\ncmp edx, eax\njnz loc_135F\nmov eax, [rbp+var_30]\ncdqe\nshl rax, 4\nlea rdx, [rax-10h]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_20], eax\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_1C], eax\nmov edx, [rbp+var_20]\nmov eax, [rbp+var_1C]\nadd eax, edx\nsub eax, 1\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, [rbp+var_30]\ncdqe\nshl rax, 4\nlea rcx, [rax-10h]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov rax, [rax+8]\nmov ecx, [rbp+var_30]\nmovsxd rcx, ecx\nshl rcx, 4\nlea rsi, [rcx-10h]\nmov rcx, [rbp+var_18]\nlea rbx, [rsi+rcx]\nmov rsi, rdx; size\nmov rdi, rax; ptr\ncall _realloc\nmov [rbx+8], rax\nmov [rbp+var_28], 1\njmp short loc_1331\nloc_12D6:\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax+8]\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov edx, [rbp+var_30]\nmovsxd rdx, edx\nshl rdx, 4\nlea rcx, [rdx-10h]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov rdx, [rdx+8]\nmov esi, [rbp+var_20]\nmov ecx, [rbp+var_28]\nadd ecx, esi\nmovsxd rcx, ecx\nshl rcx, 2\nsub rcx, 4\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_28], 1\nloc_1331:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_1C]\njl short loc_12D6\nmov edx, [rbp+var_20]\nmov eax, [rbp+var_1C]\nadd edx, eax\nmov eax, [rbp+var_30]\ncdqe\nshl rax, 4\nlea rcx, [rax-10h]\nmov rax, [rbp+var_18]\nadd rax, rcx\nsub edx, 1\nmov [rax], edx\njmp loc_143E\nloc_135F:\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nshl rax, 2\nmov edx, [rbp+var_30]\nmovsxd rdx, edx\nmov rcx, rdx\nshl rcx, 4\nmov rdx, [rbp+var_18]\nlea rbx, [rcx+rdx]\nmov rdi, rax; size\ncall _malloc\nmov [rbx+8], rax\nmov [rbp+var_24], 0\njmp short loc_13F5\nloc_13A4:\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax+8]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov edx, [rbp+var_30]\nmovsxd rdx, edx\nmov rcx, rdx\nshl rcx, 4\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov rdx, [rdx+8]\nmov ecx, [rbp+var_24]\nmovsxd rcx, ecx\nshl rcx, 2\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_24], 1\nloc_13F5:\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_24], eax\njl short loc_13A4\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rbp+var_30]\nmovsxd rdx, edx\nmov rcx, rdx\nshl rcx, 4\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_30], 1\nloc_143E:\nadd [rbp+var_2C], 1\nloc_1442:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_3C]\njl loc_1205\nmov rax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_DWORD *__fastcall func0(__int64 a1, int a2)\n{\n int v3; // [rsp+10h] [rbp-30h]\n int i; // [rsp+14h] [rbp-2Ch]\n int j; // [rsp+18h] [rbp-28h]\n int k; // [rsp+1Ch] [rbp-24h]\n int v7; // [rsp+20h] [rbp-20h]\n int v8; // [rsp+24h] [rbp-1Ch]\n _DWORD *v9; // [rsp+28h] [rbp-18h]\n\n v9 = malloc(16LL * a2);\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( v3 > 0 && **(_DWORD **)&v9[4 * v3 - 2] == **(_DWORD **)(16LL * i + a1 + 8) )\n {\n v7 = v9[4 * v3 - 4];\n v8 = *(_DWORD *)(16LL * i + a1);\n *(_QWORD *)&v9[4 * v3 - 2] = realloc(*(void **)&v9[4 * v3 - 2], 4LL * (v7 + v8 - 1));\n for ( j = 1; j < v8; ++j )\n *(_DWORD *)(4LL * (v7 + j) - 4 + *(_QWORD *)&v9[4 * v3 - 2]) = *(_DWORD *)(4LL * j\n + *(_QWORD *)(16LL * i + a1 + 8));\n v9[4 * v3 - 4] = v8 + v7 - 1;\n }\n else\n {\n *(_QWORD *)&v9[4 * v3 + 2] = malloc(4LL * *(int *)(16LL * i + a1));\n for ( k = 0; k < *(_DWORD *)(16LL * i + a1); ++k )\n *(_DWORD *)(4LL * k + *(_QWORD *)&v9[4 * v3 + 2]) = *(_DWORD *)(4LL * k + *(_QWORD *)(16LL * i + a1 + 8));\n v9[4 * v3++] = *(_DWORD *)(16LL * i + a1);\n }\n }\n return v9;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nsub rsp, 38h\nmov [rbp+var_38], rdi\nmov [rbp+var_3C], esi\nmov eax, [rbp+var_3C]\ncdqe\nshl rax, 4\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_18], rax\nmov [rbp+var_30], 0\nmov [rbp+var_2C], 0\njmp loc_1442\nloc_1205:\ncmp [rbp+var_30], 0\njle loc_135F\nmov eax, [rbp+var_30]\ncdqe\nshl rax, 4\nlea rdx, [rax-10h]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov rax, [rax+8]\nmov edx, [rax]\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 4\nmov rcx, rax\nmov rax, [rbp+var_38]\nadd rax, rcx\nmov rax, [rax+8]\nmov eax, [rax]\ncmp edx, eax\njnz loc_135F\nmov eax, [rbp+var_30]\ncdqe\nshl rax, 4\nlea rdx, [rax-10h]\nmov rax, [rbp+var_18]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_20], eax\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov eax, [rax]\nmov [rbp+var_1C], eax\nmov edx, [rbp+var_20]\nmov eax, [rbp+var_1C]\nadd eax, edx\nsub eax, 1\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, [rbp+var_30]\ncdqe\nshl rax, 4\nlea rcx, [rax-10h]\nmov rax, [rbp+var_18]\nadd rax, rcx\nmov rax, [rax+8]\nmov ecx, [rbp+var_30]\nmovsxd rcx, ecx\nshl rcx, 4\nlea rsi, [rcx-10h]\nmov rcx, [rbp+var_18]\nlea rbx, [rsi+rcx]\nmov rsi, rdx; size\nmov rdi, rax; ptr\ncall _realloc\nmov [rbx+8], rax\nmov [rbp+var_28], 1\njmp short loc_1331\nloc_12D6:\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax+8]\nmov edx, [rbp+var_28]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov edx, [rbp+var_30]\nmovsxd rdx, edx\nshl rdx, 4\nlea rcx, [rdx-10h]\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov rdx, [rdx+8]\nmov esi, [rbp+var_20]\nmov ecx, [rbp+var_28]\nadd ecx, esi\nmovsxd rcx, ecx\nshl rcx, 2\nsub rcx, 4\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_28], 1\nloc_1331:\nmov eax, [rbp+var_28]\ncmp eax, [rbp+var_1C]\njl short loc_12D6\nmov edx, [rbp+var_20]\nmov eax, [rbp+var_1C]\nadd edx, eax\nmov eax, [rbp+var_30]\ncdqe\nshl rax, 4\nlea rcx, [rax-10h]\nmov rax, [rbp+var_18]\nadd rax, rcx\nsub edx, 1\nmov [rax], edx\njmp loc_143E\nloc_135F:\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov eax, [rax]\ncdqe\nshl rax, 2\nmov edx, [rbp+var_30]\nmovsxd rdx, edx\nmov rcx, rdx\nshl rcx, 4\nmov rdx, [rbp+var_18]\nlea rbx, [rcx+rdx]\nmov rdi, rax; size\ncall _malloc\nmov [rbx+8], rax\nmov [rbp+var_24], 0\njmp short loc_13F5\nloc_13A4:\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov rax, [rax+8]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov edx, [rbp+var_30]\nmovsxd rdx, edx\nmov rcx, rdx\nshl rcx, 4\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov rdx, [rdx+8]\nmov ecx, [rbp+var_24]\nmovsxd rcx, ecx\nshl rcx, 2\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_24], 1\nloc_13F5:\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov eax, [rax]\ncmp [rbp+var_24], eax\njl short loc_13A4\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 4\nmov rdx, rax\nmov rax, [rbp+var_38]\nadd rax, rdx\nmov edx, [rbp+var_30]\nmovsxd rdx, edx\nmov rcx, rdx\nshl rcx, 4\nmov rdx, [rbp+var_18]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_30], 1\nloc_143E:\nadd [rbp+var_2C], 1\nloc_1442:\nmov eax, [rbp+var_2C]\ncmp eax, [rbp+var_3C]\njl loc_1205\nmov rax, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_DWORD *__fastcall sub_11C9(__int64 a1, int a2)\n{\n int v3; // [rsp+10h] [rbp-30h]\n int i; // [rsp+14h] [rbp-2Ch]\n int j; // [rsp+18h] [rbp-28h]\n int k; // [rsp+1Ch] [rbp-24h]\n int v7; // [rsp+20h] [rbp-20h]\n int v8; // [rsp+24h] [rbp-1Ch]\n _DWORD *v9; // [rsp+28h] [rbp-18h]\n\n v9 = malloc(16LL * a2);\n v3 = 0;\n for ( i = 0; i < a2; ++i )\n {\n if ( v3 > 0 && **(_DWORD **)&v9[4 * v3 - 2] == **(_DWORD **)(16LL * i + a1 + 8) )\n {\n v7 = v9[4 * v3 - 4];\n v8 = *(_DWORD *)(16LL * i + a1);\n *(_QWORD *)&v9[4 * v3 - 2] = realloc(*(void **)&v9[4 * v3 - 2], 4LL * (v7 + v8 - 1));\n for ( j = 1; j < v8; ++j )\n *(_DWORD *)(4LL * (v7 + j) - 4 + *(_QWORD *)&v9[4 * v3 - 2]) = *(_DWORD *)(4LL * j\n + *(_QWORD *)(16LL * i + a1 + 8));\n v9[4 * v3 - 4] = v8 + v7 - 1;\n }\n else\n {\n *(_QWORD *)&v9[4 * v3 + 2] = malloc(4LL * *(int *)(16LL * i + a1));\n for ( k = 0; k < *(_DWORD *)(16LL * i + a1); ++k )\n *(_DWORD *)(4LL * k + *(_QWORD *)&v9[4 * v3 + 2]) = *(_DWORD *)(4LL * k + *(_QWORD *)(16LL * i + a1 + 8));\n v9[4 * v3++] = *(_DWORD *)(16LL * i + a1);\n }\n }\n return v9;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint32_t *sub_11C9(long long a1, int a2) {\n int v3;\n int i;\n int j;\n int k;\n int v7;\n int v8;\n uint32_t *v9;\n v9 = malloc(16LL * a2);\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n if (v3 > 0 &&\n **(uint32_t **)&v9[4 * v3 - 2] == **(uint32_t **)(16LL * i + a1 + 8)) {\n v7 = v9[4 * v3 - 4];\n v8 = *(uint32_t *)(16LL * i + a1);\n *(uint64_t *)&v9[4 * v3 - 2] =\n realloc(*(void **)&v9[4 * v3 - 2], 4LL * (v7 + v8 - 1));\n for (j = 1; j < v8; ++j)\n *(uint32_t *)(4LL * (v7 + j) - 4 + *(uint64_t *)&v9[4 * v3 - 2]) =\n *(uint32_t *)(4LL * j + *(uint64_t *)(16LL * i + a1 + 8));\n v9[4 * v3 - 4] = v8 + v7 - 1;\n } else {\n *(uint64_t *)&v9[4 * v3 + 2] = malloc(4LL * *(int *)(16LL * i + a1));\n for (k = 0; k < *(uint32_t *)(16LL * i + a1); ++k)\n *(uint32_t *)(4LL * k + *(uint64_t *)&v9[4 * v3 + 2]) =\n *(uint32_t *)(4LL * k + *(uint64_t *)(16LL * i + a1 + 8));\n v9[4 * v3++] = *(uint32_t *)(16LL * i + a1);\n }\n }\n return v9;\n}", + "ida_pseudo_norm": "uint32_t *func0(long long a1, int a2) {\n int v3;\n int i;\n int j;\n int k;\n int v7;\n int v8;\n uint32_t *v9;\n v9 = malloc(16LL * a2);\n v3 = 0;\n for (i = 0; i < a2; ++i) {\n if (v3 > 0 &&\n **(uint32_t **)&v9[4 * v3 - 2] == **(uint32_t **)(16LL * i + a1 + 8)) {\n v7 = v9[4 * v3 - 4];\n v8 = *(uint32_t *)(16LL * i + a1);\n *(uint64_t *)&v9[4 * v3 - 2] =\n realloc(*(void **)&v9[4 * v3 - 2], 4LL * (v7 + v8 - 1));\n for (j = 1; j < v8; ++j)\n *(uint32_t *)(4LL * (v7 + j) - 4 + *(uint64_t *)&v9[4 * v3 - 2]) =\n *(uint32_t *)(4LL * j + *(uint64_t *)(16LL * i + a1 + 8));\n v9[4 * v3 - 4] = v8 + v7 - 1;\n } else {\n *(uint64_t *)&v9[4 * v3 + 2] = malloc(4LL * *(int *)(16LL * i + a1));\n for (k = 0; k < *(uint32_t *)(16LL * i + a1); ++k)\n *(uint32_t *)(4LL * k + *(uint64_t *)&v9[4 * v3 + 2]) =\n *(uint32_t *)(4LL * k + *(uint64_t *)(16LL * i + a1 + 8));\n v9[4 * v3++] = *(uint32_t *)(16LL * i + a1);\n }\n }\n return v9;\n}" + }, + { + "index": 969, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int size;\n\n int *elements;\n\n} tuple;\n\n\n\n", + "func": "tuple* func0(tuple test_list[], int list_size) {\n tuple* res = malloc(sizeof(tuple) * list_size);\n int res_size = 0;\n for (int i = 0; i < list_size; i++) {\n if (res_size > 0 &&\n res[res_size - 1].elements[0] == test_list[i].elements[0]) {\n int last_size = res[res_size - 1].size;\n int this_size = test_list[i].size;\n res[res_size - 1].elements =\n realloc(res[res_size - 1].elements,\n sizeof(int) * (last_size + this_size - 1));\n for (int j = 1; j < this_size; j++) {\n res[res_size - 1].elements[last_size + j - 1] =\n test_list[i].elements[j];\n }\n res[res_size - 1].size = last_size + this_size - 1;\n } else {\n res[res_size].elements = malloc(sizeof(int) * test_list[i].size);\n for (int j = 0; j < test_list[i].size; j++) {\n res[res_size].elements[j] = test_list[i].elements[j];\n }\n res[res_size].size = test_list[i].size;\n res_size++;\n }\n }\n return res;\n}", + "test": "int main() {\n\n tuple list1[] = {{2, (int[]){5, 6}}, {2, (int[]){5, 7}}, {2, (int[]){6, 8}}, {2, (int[]){6, 10}}, {2, (int[]){7, 13}}};\n\n tuple *result1 = func0(list1, 5);\n\n assert(result1[0].size == 3 && (result1[0].elements[0] == 5 && result1[0].elements[1] == 6 && result1[0].elements[2] == 7));\n\n assert(result1[1].size == 3 && (result1[1].elements[0] == 6 && result1[1].elements[1] == 8 && result1[1].elements[2] == 10));\n\n assert(result1[2].size == 2 && (result1[2].elements[0] == 7 && result1[2].elements[1] == 13));\n\n\n\n tuple list2[] = {{2, (int[]){6, 7}}, {2, (int[]){6, 8}}, {2, (int[]){7, 9}}, {2, (int[]){7, 11}}, {2, (int[]){8, 14}}};\n\n tuple *result2 = func0(list2, 5);\n\n assert(result2[0].size == 3 && (result2[0].elements[0] == 6 && result2[0].elements[1] == 7 && result2[0].elements[2] == 8));\n\n assert(result2[1].size == 3 && (result2[1].elements[0] == 7 && result2[1].elements[1] == 9 && result2[1].elements[2] == 11));\n\n assert(result2[2].size == 2 && (result2[2].elements[0] == 8 && result2[2].elements[1] == 14));\n\n\n\n tuple list3[] = {{2, (int[]){7, 8}}, {2, (int[]){7, 9}}, {2, (int[]){8, 10}}, {2, (int[]){8, 12}}, {2, (int[]){9, 15}}};\n\n tuple *result3 = func0(list3, 5);\n\n assert(result3[0].size == 3 && (result3[0].elements[0] == 7 && result3[0].elements[1] == 8 && result3[0].elements[2] == 9));\n\n assert(result3[1].size == 3 && (result3[1].elements[0] == 8 && result3[1].elements[1] == 10 && result3[1].elements[2] == 12));\n\n assert(result3[2].size == 2 && (result3[2].elements[0] == 9 && result3[2].elements[1] == 15));\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x18,%rsp\nmov %rdi,%rbp\nmov %esi,%ebx\nmovslq %esi,%rdi\nshl $0x4,%rdi\ncallq 10c0 \nmov %rax,%r15\ntest %ebx,%ebx\njle 12f9 \nmov %rbp,%r13\nlea -0x1(%rbx),%eax\nshl $0x4,%rax\nlea 0x10(%rbp,%rax,1),%rax\nmov %rax,(%rsp)\nmov $0x0,%r14d\njmp 126d \nmov %r13,%rbp\nmov 0x0(%r13),%ebx\nmovslq %r14d,%r12\nshl $0x4,%r12\nadd %r15,%r12\nmovslq %ebx,%rdi\nshl $0x2,%rdi\ncallq 10c0 \nmov %rax,0x8(%r12)\ntest %ebx,%ebx\njle 1257 \nmov $0x0,%eax\nmov 0x8(%rbp),%rdx\nmov (%rdx,%rax,4),%ecx\nmov 0x8(%r12),%rdx\nmov %ecx,(%rdx,%rax,4)\nmov 0x0(%rbp),%ebx\nadd $0x1,%rax\ncmp %eax,%ebx\njg 123d \nmov %ebx,(%r12)\nadd $0x1,%r14d\nadd $0x10,%r13\ncmp (%rsp),%r13\nje 12f9 \ntest %r14d,%r14d\njle 1212 \nmovslq %r14d,%rax\nshl $0x4,%rax\nlea -0x10(%r15,%rax,1),%rbx\nmov 0x8(%rbx),%rdi\nmov %r13,%rbp\nmov 0x8(%r13),%rax\nmov (%rax),%eax\ncmp %eax,(%rdi)\njne 1212 \nmov (%rbx),%eax\nmov 0x0(%r13),%r12d\nmov %eax,0xc(%rsp)\nlea -0x1(%rax,%r12,1),%eax\nmov %eax,0x8(%rsp)\nmovslq %eax,%rsi\nshl $0x2,%rsi\ncallq 10d0 \nmov %rax,0x8(%rbx)\ncmp $0x1,%r12d\njle 12ee \nlea -0x2(%r12),%eax\nlea 0x8(,%rax,4),%rdi\nmovslq 0xc(%rsp),%rsi\nshl $0x2,%rsi\nmov $0x4,%eax\nmov 0x8(%rbp),%rdx\nmov (%rdx,%rax,1),%ecx\nmov %rax,%rdx\nadd 0x8(%rbx),%rdx\nmov %ecx,-0x4(%rsi,%rdx,1)\nadd $0x4,%rax\ncmp %rdi,%rax\njne 12d3 \nmov 0x8(%rsp),%eax\nmov %eax,(%rbx)\njmpq 125f \nmov %r15,%rax\nadd $0x18,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov r12, rdi\nmov ebx, esi\nmovsxd rbp, esi\nshl rbp, 4\nmov rdi, rbp; size\ncall _malloc\nmov r15, rax\ntest ebx, ebx\njle loc_12F1\nmov r13, r12\nlea rax, [r12+rbp]\nmov [rsp+48h+var_48], rax\nmov r14d, 0\njmp short loc_126B\nloc_120D:\nmov rbp, r13\nmov ebx, [r13+0]\nmovsxd r12, r14d\nshl r12, 4\nadd r12, r15\nmovsxd rdi, ebx\nshl rdi, 2; size\ncall _malloc\nmov [r12+8], rax\ntest ebx, ebx\njle short loc_1252\nmov eax, 0\nloc_1238:\nmov rdx, [rbp+8]\nmov ecx, [rdx+rax*4]\nmov rdx, [r12+8]\nmov [rdx+rax*4], ecx\nmov ebx, [rbp+0]\nadd rax, 1\ncmp ebx, eax\njg short loc_1238\nloc_1252:\nmov [r12], ebx\nadd r14d, 1\nloc_125A:\nadd r13, 10h\nmov rax, [rsp+48h+var_48]\ncmp r13, rax\njz loc_12F1\nloc_126B:\ntest r14d, r14d\njle short loc_120D\nmovsxd rax, r14d\nshl rax, 4\nlea rbx, [r15+rax-10h]\nmov rdi, [rbx+8]; ptr\nmov rbp, r13\nmov rax, [r13+8]\nmov eax, [rax]\ncmp [rdi], eax\njnz short loc_120D\nmov eax, [rbx]\nmov r12d, [r13+0]\nmov [rsp+48h+var_3C], eax\nlea eax, [rax+r12-1]\nmov [rsp+48h+var_40], eax\nmovsxd rsi, eax\nshl rsi, 2; size\ncall _realloc\nmov [rbx+8], rax\ncmp r12d, 1\njle short loc_12E6\nmov r12d, r12d\nshl r12, 2\nmovsxd rsi, [rsp+48h+var_3C]\nshl rsi, 2\nmov eax, 4\nloc_12CB:\nmov rdx, [rbp+8]\nmov ecx, [rdx+rax]\nmov rdx, rax\nadd rdx, [rbx+8]\nmov [rsi+rdx-4], ecx\nadd rax, 4\ncmp rax, r12\njnz short loc_12CB\nloc_12E6:\nmov eax, [rsp+48h+var_40]\nmov [rbx], eax\njmp loc_125A\nloc_12F1:\nmov rax, r15\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_pseudo": "char *__fastcall func0(int *a1, int a2)\n{\n char *v2; // r15\n int *v3; // r13\n int v4; // r14d\n int v5; // ebx\n char *v6; // r12\n __int64 v7; // rax\n __int64 v8; // rbx\n _DWORD *v9; // rdi\n int v10; // r12d\n __int64 v11; // r12\n __int64 v12; // rax\n int *v14; // [rsp+0h] [rbp-48h]\n int v15; // [rsp+8h] [rbp-40h]\n int v16; // [rsp+Ch] [rbp-3Ch]\n\n v2 = (char *)malloc(16LL * a2);\n if ( a2 > 0 )\n {\n v3 = a1;\n v14 = &a1[4 * a2];\n v4 = 0;\n do\n {\n if ( v4 > 0 && (v8 = (__int64)&v2[16 * v4 - 16], v9 = *(_DWORD **)(v8 + 8), *v9 == **((_DWORD **)v3 + 1)) )\n {\n v10 = *v3;\n v16 = *(_DWORD *)v8;\n v15 = *(_DWORD *)v8 + *v3 - 1;\n *(_QWORD *)(v8 + 8) = realloc(v9, 4LL * v15);\n if ( v10 > 1 )\n {\n v11 = 4LL * (unsigned int)v10;\n v12 = 4LL;\n do\n {\n *(_DWORD *)(4LL * v16 + *(_QWORD *)(v8 + 8) + v12 - 4) = *(_DWORD *)(*((_QWORD *)v3 + 1) + v12);\n v12 += 4LL;\n }\n while ( v12 != v11 );\n }\n *(_DWORD *)v8 = v15;\n }\n else\n {\n v5 = *v3;\n v6 = &v2[16 * v4];\n *((_QWORD *)v6 + 1) = malloc(4LL * *v3);\n if ( v5 > 0 )\n {\n v7 = 0LL;\n do\n {\n *(_DWORD *)(*((_QWORD *)v6 + 1) + 4 * v7) = *(_DWORD *)(*((_QWORD *)v3 + 1) + 4 * v7);\n v5 = *v3;\n ++v7;\n }\n while ( *v3 > (int)v7 );\n }\n *(_DWORD *)v6 = v5;\n ++v4;\n }\n v3 += 4;\n }\n while ( v3 != v14 );\n }\n return v2;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r15\npush r14\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 18h\nmov r12, rdi\nmov ebx, esi\nmovsxd rbp, esi\nshl rbp, 4\nmov rdi, rbp; size\ncall _malloc\nmov r15, rax\ntest ebx, ebx\njle loc_12F1\nmov r13, r12\nlea rax, [r12+rbp]\nmov [rsp+48h+var_48], rax\nmov r14d, 0\njmp short loc_126B\nloc_120D:\nmov rbp, r13\nmov ebx, [r13+0]\nmovsxd r12, r14d\nshl r12, 4\nadd r12, r15\nmovsxd rdi, ebx\nshl rdi, 2; size\ncall _malloc\nmov [r12+8], rax\ntest ebx, ebx\njle short loc_1252\nmov eax, 0\nloc_1238:\nmov rdx, [rbp+8]\nmov ecx, [rdx+rax*4]\nmov rdx, [r12+8]\nmov [rdx+rax*4], ecx\nmov ebx, [rbp+0]\nadd rax, 1\ncmp ebx, eax\njg short loc_1238\nloc_1252:\nmov [r12], ebx\nadd r14d, 1\nloc_125A:\nadd r13, 10h\nmov rax, [rsp+48h+var_48]\ncmp r13, rax\njz loc_12F1\nloc_126B:\ntest r14d, r14d\njle short loc_120D\nmovsxd rax, r14d\nshl rax, 4\nlea rbx, [r15+rax-10h]\nmov rdi, [rbx+8]; ptr\nmov rbp, r13\nmov rax, [r13+8]\nmov eax, [rax]\ncmp [rdi], eax\njnz short loc_120D\nmov eax, [rbx]\nmov r12d, [r13+0]\nmov [rsp+48h+var_3C], eax\nlea eax, [rax+r12-1]\nmov [rsp+48h+var_40], eax\nmovsxd rsi, eax\nshl rsi, 2; size\ncall _realloc\nmov [rbx+8], rax\ncmp r12d, 1\njle short loc_12E6\nmov r12d, r12d\nshl r12, 2\nmovsxd rsi, [rsp+48h+var_3C]\nshl rsi, 2\nmov eax, 4\nloc_12CB:\nmov rdx, [rbp+8]\nmov ecx, [rdx+rax]\nmov rdx, rax\nadd rdx, [rbx+8]\nmov [rsi+rdx-4], ecx\nadd rax, 4\ncmp rax, r12\njnz short loc_12CB\nloc_12E6:\nmov eax, [rsp+48h+var_40]\nmov [rbx], eax\njmp loc_125A\nloc_12F1:\nmov rax, r15\nadd rsp, 18h\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn", + "ida_strip_pseudo": "char *__fastcall sub_11C9(int *a1, int a2)\n{\n char *v2; // r15\n int *v3; // r13\n int v4; // r14d\n int v5; // ebx\n char *v6; // r12\n __int64 v7; // rax\n __int64 v8; // rbx\n _DWORD *v9; // rdi\n int v10; // r12d\n __int64 v11; // r12\n __int64 v12; // rax\n int *v14; // [rsp+0h] [rbp-48h]\n int v15; // [rsp+8h] [rbp-40h]\n int v16; // [rsp+Ch] [rbp-3Ch]\n\n v2 = (char *)malloc(16LL * a2);\n if ( a2 > 0 )\n {\n v3 = a1;\n v14 = &a1[4 * a2];\n v4 = 0;\n do\n {\n if ( v4 > 0 && (v8 = (__int64)&v2[16 * v4 - 16], v9 = *(_DWORD **)(v8 + 8), *v9 == **((_DWORD **)v3 + 1)) )\n {\n v10 = *v3;\n v16 = *(_DWORD *)v8;\n v15 = *(_DWORD *)v8 + *v3 - 1;\n *(_QWORD *)(v8 + 8) = realloc(v9, 4LL * v15);\n if ( v10 > 1 )\n {\n v11 = 4LL * (unsigned int)v10;\n v12 = 4LL;\n do\n {\n *(_DWORD *)(4LL * v16 + *(_QWORD *)(v8 + 8) + v12 - 4) = *(_DWORD *)(*((_QWORD *)v3 + 1) + v12);\n v12 += 4LL;\n }\n while ( v12 != v11 );\n }\n *(_DWORD *)v8 = v15;\n }\n else\n {\n v5 = *v3;\n v6 = &v2[16 * v4];\n *((_QWORD *)v6 + 1) = malloc(4LL * *v3);\n if ( v5 > 0 )\n {\n v7 = 0LL;\n do\n {\n *(_DWORD *)(*((_QWORD *)v6 + 1) + 4 * v7) = *(_DWORD *)(*((_QWORD *)v3 + 1) + 4 * v7);\n v5 = *v3;\n ++v7;\n }\n while ( *v3 > (int)v7 );\n }\n *(_DWORD *)v6 = v5;\n ++v4;\n }\n v3 += 4;\n }\n while ( v3 != v14 );\n }\n return v2;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_11C9(int *a1, int a2) {\n char *v2;\n int *v3;\n int v4;\n int v5;\n char *v6;\n long long v7;\n long long v8;\n uint32_t *v9;\n int v10;\n long long v11;\n long long v12;\n int *v14;\n int v15;\n int v16;\n v2 = (char *)malloc(16LL * a2);\n if (a2 > 0) {\n v3 = a1;\n v14 = &a1[4 * a2];\n v4 = 0;\n do {\n if (v4 > 0 &&\n (v8 = (long long)&v2[16 * v4 - 16], v9 = *(uint32_t **)(v8 + 8),\n *v9 == **((uint32_t **)v3 + 1))) {\n v10 = *v3;\n v16 = *(uint32_t *)v8;\n v15 = *(uint32_t *)v8 + *v3 - 1;\n *(uint64_t *)(v8 + 8) = realloc(v9, 4LL * v15);\n if (v10 > 1) {\n v11 = 4LL * (unsigned int)v10;\n v12 = 4LL;\n do {\n *(uint32_t *)(4LL * v16 + *(uint64_t *)(v8 + 8) + v12 - 4) =\n *(uint32_t *)(*((uint64_t *)v3 + 1) + v12);\n v12 += 4LL;\n } while (v12 != v11);\n }\n *(uint32_t *)v8 = v15;\n } else {\n v5 = *v3;\n v6 = &v2[16 * v4];\n *((uint64_t *)v6 + 1) = malloc(4LL * *v3);\n if (v5 > 0) {\n v7 = 0LL;\n do {\n *(uint32_t *)(*((uint64_t *)v6 + 1) + 4 * v7) =\n *(uint32_t *)(*((uint64_t *)v3 + 1) + 4 * v7);\n v5 = *v3;\n ++v7;\n } while (*v3 > (int)v7);\n }\n *(uint32_t *)v6 = v5;\n ++v4;\n }\n v3 += 4;\n } while (v3 != v14);\n }\n return v2;\n}", + "ida_pseudo_norm": "char *func0(int *a1, int a2) {\n char *v2;\n int *v3;\n int v4;\n int v5;\n char *v6;\n long long v7;\n long long v8;\n uint32_t *v9;\n int v10;\n long long v11;\n long long v12;\n int *v14;\n int v15;\n int v16;\n v2 = (char *)malloc(16LL * a2);\n if (a2 > 0) {\n v3 = a1;\n v14 = &a1[4 * a2];\n v4 = 0;\n do {\n if (v4 > 0 &&\n (v8 = (long long)&v2[16 * v4 - 16], v9 = *(uint32_t **)(v8 + 8),\n *v9 == **((uint32_t **)v3 + 1))) {\n v10 = *v3;\n v16 = *(uint32_t *)v8;\n v15 = *(uint32_t *)v8 + *v3 - 1;\n *(uint64_t *)(v8 + 8) = realloc(v9, 4LL * v15);\n if (v10 > 1) {\n v11 = 4LL * (unsigned int)v10;\n v12 = 4LL;\n do {\n *(uint32_t *)(4LL * v16 + *(uint64_t *)(v8 + 8) + v12 - 4) =\n *(uint32_t *)(*((uint64_t *)v3 + 1) + v12);\n v12 += 4LL;\n } while (v12 != v11);\n }\n *(uint32_t *)v8 = v15;\n } else {\n v5 = *v3;\n v6 = &v2[16 * v4];\n *((uint64_t *)v6 + 1) = malloc(4LL * *v3);\n if (v5 > 0) {\n v7 = 0LL;\n do {\n *(uint32_t *)(*((uint64_t *)v6 + 1) + 4 * v7) =\n *(uint32_t *)(*((uint64_t *)v3 + 1) + 4 * v7);\n v5 = *v3;\n ++v7;\n } while (*v3 > (int)v7);\n }\n *(uint32_t *)v6 = v5;\n ++v4;\n }\n v3 += 4;\n } while (v3 != v14);\n }\n return v2;\n}" + }, + { + "index": 969, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int size;\n\n int *elements;\n\n} tuple;\n\n\n\n", + "func": "tuple* func0(tuple test_list[], int list_size) {\n tuple* res = malloc(sizeof(tuple) * list_size);\n int res_size = 0;\n for (int i = 0; i < list_size; i++) {\n if (res_size > 0 &&\n res[res_size - 1].elements[0] == test_list[i].elements[0]) {\n int last_size = res[res_size - 1].size;\n int this_size = test_list[i].size;\n res[res_size - 1].elements =\n realloc(res[res_size - 1].elements,\n sizeof(int) * (last_size + this_size - 1));\n for (int j = 1; j < this_size; j++) {\n res[res_size - 1].elements[last_size + j - 1] =\n test_list[i].elements[j];\n }\n res[res_size - 1].size = last_size + this_size - 1;\n } else {\n res[res_size].elements = malloc(sizeof(int) * test_list[i].size);\n for (int j = 0; j < test_list[i].size; j++) {\n res[res_size].elements[j] = test_list[i].elements[j];\n }\n res[res_size].size = test_list[i].size;\n res_size++;\n }\n }\n return res;\n}", + "test": "int main() {\n\n tuple list1[] = {{2, (int[]){5, 6}}, {2, (int[]){5, 7}}, {2, (int[]){6, 8}}, {2, (int[]){6, 10}}, {2, (int[]){7, 13}}};\n\n tuple *result1 = func0(list1, 5);\n\n assert(result1[0].size == 3 && (result1[0].elements[0] == 5 && result1[0].elements[1] == 6 && result1[0].elements[2] == 7));\n\n assert(result1[1].size == 3 && (result1[1].elements[0] == 6 && result1[1].elements[1] == 8 && result1[1].elements[2] == 10));\n\n assert(result1[2].size == 2 && (result1[2].elements[0] == 7 && result1[2].elements[1] == 13));\n\n\n\n tuple list2[] = {{2, (int[]){6, 7}}, {2, (int[]){6, 8}}, {2, (int[]){7, 9}}, {2, (int[]){7, 11}}, {2, (int[]){8, 14}}};\n\n tuple *result2 = func0(list2, 5);\n\n assert(result2[0].size == 3 && (result2[0].elements[0] == 6 && result2[0].elements[1] == 7 && result2[0].elements[2] == 8));\n\n assert(result2[1].size == 3 && (result2[1].elements[0] == 7 && result2[1].elements[1] == 9 && result2[1].elements[2] == 11));\n\n assert(result2[2].size == 2 && (result2[2].elements[0] == 8 && result2[2].elements[1] == 14));\n\n\n\n tuple list3[] = {{2, (int[]){7, 8}}, {2, (int[]){7, 9}}, {2, (int[]){8, 10}}, {2, (int[]){8, 12}}, {2, (int[]){9, 15}}};\n\n tuple *result3 = func0(list3, 5);\n\n assert(result3[0].size == 3 && (result3[0].elements[0] == 7 && result3[0].elements[1] == 8 && result3[0].elements[2] == 9));\n\n assert(result3[1].size == 3 && (result3[1].elements[0] == 8 && result3[1].elements[1] == 10 && result3[1].elements[2] == 12));\n\n assert(result3[2].size == 2 && (result3[2].elements[0] == 9 && result3[2].elements[1] == 15));\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\nmov %rdi,%r13\nmovslq %esi,%rdi\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nshl $0x4,%rdi\nsub $0x18,%rsp\ncallq 10c0 \nmov %rax,%r12\ntest %ebx,%ebx\njle 17f2 \nlea -0x1(%rbx),%eax\nlea 0x8(%r13),%rbp\nshl $0x4,%rax\nlea 0x18(%r13,%rax,1),%rbx\nxor %r13d,%r13d\nnopw 0x0(%rax,%rax,1)\nmovslq %r13d,%rax\nmov -0x8(%rbp),%r14d\nshl $0x4,%rax\ntest %r13d,%r13d\nje 17ab \nlea -0x10(%r12,%rax,1),%r15\nmov 0x0(%rbp),%rdx\nmov 0x8(%r15),%rdi\nmov (%rdx),%esi\ncmp %esi,(%rdi)\nje 1808 \nmovslq %r14d,%rdi\nlea (%r12,%rax,1),%r15\nshl $0x2,%rdi\ncallq 10c0 \nmov %rax,0x8(%r15)\ntest %r14d,%r14d\njle 17e2 \nmov 0x0(%rbp),%rdi\nlea -0x1(%r14),%esi\nxor %edx,%edx\nxchg %ax,%ax\nmov (%rdi,%rdx,4),%ecx\nmov %ecx,(%rax,%rdx,4)\nmov %rdx,%rcx\nadd $0x1,%rdx\ncmp %rcx,%rsi\njne 17d0 \nmov %r14d,(%r15)\nadd $0x1,%r13d\nadd $0x10,%rbp\ncmp %rbx,%rbp\njne 1788 \nadd $0x18,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopl 0x0(%rax)\nmov (%r15),%edx\nlea -0x1(%rdx,%r14,1),%r8d\nmov %edx,0xc(%rsp)\nmovslq %r8d,%rsi\nmov %r8d,0x8(%rsp)\nshl $0x2,%rsi\ncallq 10d0 \ncmp $0x1,%r14d\nmov 0x8(%rsp),%r8d\nmovslq 0xc(%rsp),%rdx\nmov %rax,0x8(%r15)\njle 1860 \nlea -0x2(%r14),%ecx\nmov 0x0(%rbp),%rdi\nlea (%rax,%rdx,4),%rsi\nmov $0x1,%eax\nadd $0x2,%rcx\nxchg %ax,%ax\nmov (%rdi,%rax,4),%edx\nmov %edx,-0x4(%rsi,%rax,4)\nadd $0x1,%rax\ncmp %rax,%rcx\njne 1850 \nmov %r8d,(%r15)\njmp 17e9 \nnopw %cs:0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\npush r13\nmov r13, rdi\npush r12\nmovsxd r12, esi\npush rbp\npush rbx\nmov rbx, r12\nshl r12, 4\nmov rdi, r12; size\nsub rsp, 18h\ncall _malloc\nmov rbp, rax\nlea rax, [r13+r12+0]\nmov [rsp+48h+var_48], rax\ntest ebx, ebx\njle short loc_17B4\nxor r14d, r14d\nnop word ptr [rax+rax+00h]\nloc_1740:\nmovsxd r12, r14d\nmov r15d, [r13+0]\nmov rax, r12\nshl rax, 4\ntest r14d, r14d\njle short loc_1766\nloc_1753:\nlea rbx, [rbp+rax-10h]\nmov rdx, [r13+8]\nmov rdi, [rbx+8]; ptr\nmov esi, [rdx]\ncmp [rdi], esi\njz short loc_17D0\nloc_1766:\nmovsxd rbx, r15d\nlea r12, [rbp+rax+0]\nshl rbx, 2\nmov rdi, rbx; size\ncall _malloc\nmov [r12+8], rax\ntest r15d, r15d\njle short loc_179F\nmov rsi, [r13+8]\nxor edx, edx\nnop word ptr [rax+rax+00h]\nloc_1790:\nmov ecx, [rsi+rdx]\nmov [rax+rdx], ecx\nadd rdx, 4\ncmp rbx, rdx\njnz short loc_1790\nloc_179F:\nmov rax, [rsp+48h+var_48]\nadd r13, 10h\nmov [r12], r15d\nadd r14d, 1\ncmp r13, rax\njnz short loc_1740\nloc_17B4:\nadd rsp, 18h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_17D0:\nmov edx, [rbx]\nlea r8d, [r15+rdx-1]\nmov [rsp+48h+var_3C], edx\nmovsxd rsi, r8d\nmov [rsp+48h+var_40], r8d\nshl rsi, 2; size\ncall _realloc\ncmp r15d, 1\nmov r8d, [rsp+48h+var_40]\nmovsxd rdx, [rsp+48h+var_3C]\nmov [rbx+8], rax\njle short loc_1820\nmov rdi, [r13+8]\nlea rsi, [rax+rdx*4]\nmov eax, 1\nnop dword ptr [rax]\nloc_1810:\nmov edx, [rdi+rax*4]\nmov [rsi+rax*4-4], edx\nadd rax, 1\ncmp r15, rax\njnz short loc_1810\nloc_1820:\nmov rax, [rsp+48h+var_48]\nadd r13, 10h\nmov [rbx], r8d\ncmp r13, rax\njz short loc_17B4\nmov rax, r12\nmov r15d, [r13+0]\nshl rax, 4\njmp loc_1753", + "ida_pseudo": "char *__fastcall func0(unsigned int *a1, int a2)\n{\n unsigned int *v2; // r13\n char *v3; // rbp\n int v4; // r14d\n __int64 v5; // r15\n __int64 v6; // rax\n __int64 v7; // rbx\n _DWORD *v8; // rdi\n char *v9; // r12\n char *v10; // rax\n __int64 v11; // rsi\n __int64 v12; // rdx\n char *v14; // rax\n __int64 v15; // rdi\n char *v16; // rsi\n __int64 i; // rax\n unsigned int *v18; // [rsp+0h] [rbp-48h]\n int v19; // [rsp+8h] [rbp-40h]\n int v20; // [rsp+Ch] [rbp-3Ch]\n\n v2 = a1;\n v3 = (char *)malloc(16LL * a2);\n v18 = &a1[4 * a2];\n if ( a2 > 0 )\n {\n v4 = 0;\n do\n {\n v5 = *v2;\n v6 = 16LL * v4;\n if ( v4 > 0 )\n {\n while ( 1 )\n {\n v7 = (__int64)&v3[v6 - 16];\n v8 = *(_DWORD **)(v7 + 8);\n if ( *v8 != **((_DWORD **)v2 + 1) )\n break;\n v20 = *(_DWORD *)v7;\n v19 = v5 + *(_DWORD *)v7 - 1;\n v14 = (char *)realloc(v8, 4LL * v19);\n *(_QWORD *)(v7 + 8) = v14;\n if ( (int)v5 > 1 )\n {\n v15 = *((_QWORD *)v2 + 1);\n v16 = &v14[4 * v20];\n for ( i = 1LL; i != v5; ++i )\n *(_DWORD *)&v16[4 * i - 4] = *(_DWORD *)(v15 + 4 * i);\n }\n v2 += 4;\n *(_DWORD *)v7 = v19;\n if ( v2 == v18 )\n return v3;\n v5 = *v2;\n v6 = 16LL * v4;\n }\n }\n v9 = &v3[v6];\n v10 = (char *)malloc(4LL * (int)v5);\n *((_QWORD *)v9 + 1) = v10;\n if ( (int)v5 > 0 )\n {\n v11 = *((_QWORD *)v2 + 1);\n v12 = 0LL;\n do\n {\n *(_DWORD *)&v10[v12] = *(_DWORD *)(v11 + v12);\n v12 += 4LL;\n }\n while ( 4LL * (int)v5 != v12 );\n }\n v2 += 4;\n *(_DWORD *)v9 = v5;\n ++v4;\n }\n while ( v2 != v18 );\n }\n return v3;\n}", + "ida_strip_asm": "sub_1700:\nendbr64\npush r15\npush r14\npush r13\nmov r13, rdi\npush r12\nmovsxd r12, esi\npush rbp\npush rbx\nmov rbx, r12\nshl r12, 4\nmov rdi, r12; size\nsub rsp, 18h\ncall _malloc\nmov rbp, rax\nlea rax, [r13+r12+0]\nmov [rsp+48h+var_48], rax\ntest ebx, ebx\njle short loc_17B4\nxor r14d, r14d\nnop word ptr [rax+rax+00h]\nloc_1740:\nmovsxd r12, r14d\nmov r15d, [r13+0]\nmov rax, r12\nshl rax, 4\ntest r14d, r14d\njle short loc_1766\nloc_1753:\nlea rbx, [rbp+rax-10h]\nmov rdx, [r13+8]\nmov rdi, [rbx+8]; ptr\nmov esi, [rdx]\ncmp [rdi], esi\njz short loc_17D0\nloc_1766:\nmovsxd rbx, r15d\nlea r12, [rbp+rax+0]\nshl rbx, 2\nmov rdi, rbx; size\ncall _malloc\nmov [r12+8], rax\ntest r15d, r15d\njle short loc_179F\nmov rsi, [r13+8]\nxor edx, edx\nnop word ptr [rax+rax+00h]\nloc_1790:\nmov ecx, [rsi+rdx]\nmov [rax+rdx], ecx\nadd rdx, 4\ncmp rbx, rdx\njnz short loc_1790\nloc_179F:\nmov rax, [rsp+48h+var_48]\nadd r13, 10h\nmov [r12], r15d\nadd r14d, 1\ncmp r13, rax\njnz short loc_1740\nloc_17B4:\nadd rsp, 18h\nmov rax, rbp\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_17D0:\nmov edx, [rbx]\nlea r8d, [r15+rdx-1]\nmov [rsp+48h+var_3C], edx\nmovsxd rsi, r8d\nmov [rsp+48h+var_40], r8d\nshl rsi, 2; size\ncall _realloc\ncmp r15d, 1\nmov r8d, [rsp+48h+var_40]\nmovsxd rdx, [rsp+48h+var_3C]\nmov [rbx+8], rax\njle short loc_1820\nmov rdi, [r13+8]\nlea rsi, [rax+rdx*4]\nmov eax, 1\nnop dword ptr [rax]\nloc_1810:\nmov edx, [rdi+rax*4]\nmov [rsi+rax*4-4], edx\nadd rax, 1\ncmp r15, rax\njnz short loc_1810\nloc_1820:\nmov rax, [rsp+48h+var_48]\nadd r13, 10h\nmov [rbx], r8d\ncmp r13, rax\njz short loc_17B4\nmov rax, r12\nmov r15d, [r13+0]\nshl rax, 4\njmp loc_1753", + "ida_strip_pseudo": "char *__fastcall sub_1700(unsigned int *a1, int a2)\n{\n unsigned int *v2; // r13\n char *v3; // rbp\n int v4; // r14d\n __int64 v5; // r15\n __int64 v6; // rax\n __int64 v7; // rbx\n _DWORD *v8; // rdi\n char *v9; // r12\n char *v10; // rax\n __int64 v11; // rsi\n __int64 v12; // rdx\n char *v14; // rax\n __int64 v15; // rdi\n char *v16; // rsi\n __int64 i; // rax\n unsigned int *v18; // [rsp+0h] [rbp-48h]\n int v19; // [rsp+8h] [rbp-40h]\n int v20; // [rsp+Ch] [rbp-3Ch]\n\n v2 = a1;\n v3 = (char *)malloc(16LL * a2);\n v18 = &a1[4 * a2];\n if ( a2 > 0 )\n {\n v4 = 0;\n do\n {\n v5 = *v2;\n v6 = 16LL * v4;\n if ( v4 > 0 )\n {\n while ( 1 )\n {\n v7 = (__int64)&v3[v6 - 16];\n v8 = *(_DWORD **)(v7 + 8);\n if ( *v8 != **((_DWORD **)v2 + 1) )\n break;\n v20 = *(_DWORD *)v7;\n v19 = v5 + *(_DWORD *)v7 - 1;\n v14 = (char *)realloc(v8, 4LL * v19);\n *(_QWORD *)(v7 + 8) = v14;\n if ( (int)v5 > 1 )\n {\n v15 = *((_QWORD *)v2 + 1);\n v16 = &v14[4 * v20];\n for ( i = 1LL; i != v5; ++i )\n *(_DWORD *)&v16[4 * i - 4] = *(_DWORD *)(v15 + 4 * i);\n }\n v2 += 4;\n *(_DWORD *)v7 = v19;\n if ( v2 == v18 )\n return v3;\n v5 = *v2;\n v6 = 16LL * v4;\n }\n }\n v9 = &v3[v6];\n v10 = (char *)malloc(4LL * (int)v5);\n *((_QWORD *)v9 + 1) = v10;\n if ( (int)v5 > 0 )\n {\n v11 = *((_QWORD *)v2 + 1);\n v12 = 0LL;\n do\n {\n *(_DWORD *)&v10[v12] = *(_DWORD *)(v11 + v12);\n v12 += 4LL;\n }\n while ( 4LL * (int)v5 != v12 );\n }\n v2 += 4;\n *(_DWORD *)v9 = v5;\n ++v4;\n }\n while ( v2 != v18 );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1700(unsigned int *a1, int a2) {\n unsigned int *v2;\n char *v3;\n int v4;\n long long v5;\n long long v6;\n long long v7;\n uint32_t *v8;\n char *v9;\n char *v10;\n long long v11;\n long long v12;\n char *v14;\n long long v15;\n char *v16;\n long long i;\n unsigned int *v18;\n int v19;\n int v20;\n v2 = a1;\n v3 = (char *)malloc(16LL * a2);\n v18 = &a1[4 * a2];\n if (a2 > 0) {\n v4 = 0;\n do {\n v5 = *v2;\n v6 = 16LL * v4;\n if (v4 > 0) {\n while (1) {\n v7 = (long long)&v3[v6 - 16];\n v8 = *(uint32_t **)(v7 + 8);\n if (*v8 != **((uint32_t **)v2 + 1)) break;\n v20 = *(uint32_t *)v7;\n v19 = v5 + *(uint32_t *)v7 - 1;\n v14 = (char *)realloc(v8, 4LL * v19);\n *(uint64_t *)(v7 + 8) = v14;\n if ((int)v5 > 1) {\n v15 = *((uint64_t *)v2 + 1);\n v16 = &v14[4 * v20];\n for (i = 1LL; i != v5; ++i)\n *(uint32_t *)&v16[4 * i - 4] = *(uint32_t *)(v15 + 4 * i);\n }\n v2 += 4;\n *(uint32_t *)v7 = v19;\n if (v2 == v18) return v3;\n v5 = *v2;\n v6 = 16LL * v4;\n }\n }\n v9 = &v3[v6];\n v10 = (char *)malloc(4LL * (int)v5);\n *((uint64_t *)v9 + 1) = v10;\n if ((int)v5 > 0) {\n v11 = *((uint64_t *)v2 + 1);\n v12 = 0LL;\n do {\n *(uint32_t *)&v10[v12] = *(uint32_t *)(v11 + v12);\n v12 += 4LL;\n } while (4LL * (int)v5 != v12);\n }\n v2 += 4;\n *(uint32_t *)v9 = v5;\n ++v4;\n } while (v2 != v18);\n }\n return v3;\n}", + "ida_pseudo_norm": "char *func0(unsigned int *a1, int a2) {\n unsigned int *v2;\n char *v3;\n int v4;\n long long v5;\n long long v6;\n long long v7;\n uint32_t *v8;\n char *v9;\n char *v10;\n long long v11;\n long long v12;\n char *v14;\n long long v15;\n char *v16;\n long long i;\n unsigned int *v18;\n int v19;\n int v20;\n v2 = a1;\n v3 = (char *)malloc(16LL * a2);\n v18 = &a1[4 * a2];\n if (a2 > 0) {\n v4 = 0;\n do {\n v5 = *v2;\n v6 = 16LL * v4;\n if (v4 > 0) {\n while (1) {\n v7 = (long long)&v3[v6 - 16];\n v8 = *(uint32_t **)(v7 + 8);\n if (*v8 != **((uint32_t **)v2 + 1)) break;\n v20 = *(uint32_t *)v7;\n v19 = v5 + *(uint32_t *)v7 - 1;\n v14 = (char *)realloc(v8, 4LL * v19);\n *(uint64_t *)(v7 + 8) = v14;\n if ((int)v5 > 1) {\n v15 = *((uint64_t *)v2 + 1);\n v16 = &v14[4 * v20];\n for (i = 1LL; i != v5; ++i)\n *(uint32_t *)&v16[4 * i - 4] = *(uint32_t *)(v15 + 4 * i);\n }\n v2 += 4;\n *(uint32_t *)v7 = v19;\n if (v2 == v18) return v3;\n v5 = *v2;\n v6 = 16LL * v4;\n }\n }\n v9 = &v3[v6];\n v10 = (char *)malloc(4LL * (int)v5);\n *((uint64_t *)v9 + 1) = v10;\n if ((int)v5 > 0) {\n v11 = *((uint64_t *)v2 + 1);\n v12 = 0LL;\n do {\n *(uint32_t *)&v10[v12] = *(uint32_t *)(v11 + v12);\n v12 += 4LL;\n } while (4LL * (int)v5 != v12);\n }\n v2 += 4;\n *(uint32_t *)v9 = v5;\n ++v4;\n } while (v2 != v18);\n }\n return v3;\n}" + }, + { + "index": 969, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n#include \n\n\n\ntypedef struct {\n\n int size;\n\n int *elements;\n\n} tuple;\n\n\n\n", + "func": "tuple* func0(tuple test_list[], int list_size) {\n tuple* res = malloc(sizeof(tuple) * list_size);\n int res_size = 0;\n for (int i = 0; i < list_size; i++) {\n if (res_size > 0 &&\n res[res_size - 1].elements[0] == test_list[i].elements[0]) {\n int last_size = res[res_size - 1].size;\n int this_size = test_list[i].size;\n res[res_size - 1].elements =\n realloc(res[res_size - 1].elements,\n sizeof(int) * (last_size + this_size - 1));\n for (int j = 1; j < this_size; j++) {\n res[res_size - 1].elements[last_size + j - 1] =\n test_list[i].elements[j];\n }\n res[res_size - 1].size = last_size + this_size - 1;\n } else {\n res[res_size].elements = malloc(sizeof(int) * test_list[i].size);\n for (int j = 0; j < test_list[i].size; j++) {\n res[res_size].elements[j] = test_list[i].elements[j];\n }\n res[res_size].size = test_list[i].size;\n res_size++;\n }\n }\n return res;\n}", + "test": "int main() {\n\n tuple list1[] = {{2, (int[]){5, 6}}, {2, (int[]){5, 7}}, {2, (int[]){6, 8}}, {2, (int[]){6, 10}}, {2, (int[]){7, 13}}};\n\n tuple *result1 = func0(list1, 5);\n\n assert(result1[0].size == 3 && (result1[0].elements[0] == 5 && result1[0].elements[1] == 6 && result1[0].elements[2] == 7));\n\n assert(result1[1].size == 3 && (result1[1].elements[0] == 6 && result1[1].elements[1] == 8 && result1[1].elements[2] == 10));\n\n assert(result1[2].size == 2 && (result1[2].elements[0] == 7 && result1[2].elements[1] == 13));\n\n\n\n tuple list2[] = {{2, (int[]){6, 7}}, {2, (int[]){6, 8}}, {2, (int[]){7, 9}}, {2, (int[]){7, 11}}, {2, (int[]){8, 14}}};\n\n tuple *result2 = func0(list2, 5);\n\n assert(result2[0].size == 3 && (result2[0].elements[0] == 6 && result2[0].elements[1] == 7 && result2[0].elements[2] == 8));\n\n assert(result2[1].size == 3 && (result2[1].elements[0] == 7 && result2[1].elements[1] == 9 && result2[1].elements[2] == 11));\n\n assert(result2[2].size == 2 && (result2[2].elements[0] == 8 && result2[2].elements[1] == 14));\n\n\n\n tuple list3[] = {{2, (int[]){7, 8}}, {2, (int[]){7, 9}}, {2, (int[]){8, 10}}, {2, (int[]){8, 12}}, {2, (int[]){9, 15}}};\n\n tuple *result3 = func0(list3, 5);\n\n assert(result3[0].size == 3 && (result3[0].elements[0] == 7 && result3[0].elements[1] == 8 && result3[0].elements[2] == 9));\n\n assert(result3[1].size == 3 && (result3[1].elements[0] == 8 && result3[1].elements[1] == 10 && result3[1].elements[2] == 12));\n\n assert(result3[2].size == 2 && (result3[2].elements[0] == 9 && result3[2].elements[1] == 15));\n\n\n\n free(result1);\n\n free(result2);\n\n free(result3);\n\n\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r15\npush %r14\npush %r13\npush %r12\npush %rbp\nmov %rdi,%rbp\nmovslq %esi,%rdi\npush %rbx\nmov %rdi,%rbx\nshl $0x4,%rdi\nsub $0x18,%rsp\ncallq 10c0 \nmov %rax,%r12\ntest %ebx,%ebx\njle 1858 \nlea -0x1(%rbx),%eax\nlea 0x8(%rbp),%r13\nxor %r14d,%r14d\nshl $0x4,%rax\nlea 0x18(%rbp,%rax,1),%rbp\nnopw 0x0(%rax,%rax,1)\nmovslq %r14d,%rax\nmov -0x8(%r13),%ebx\nshl $0x4,%rax\ntest %r14d,%r14d\nje 17af \nlea -0x10(%r12,%rax,1),%r15\nmov 0x0(%r13),%rdx\nmov 0x8(%r15),%rdi\nmov (%rdx),%ecx\ncmp %ecx,(%rdi)\nje 1870 \nmovslq %ebx,%rdi\nlea (%r12,%rax,1),%r15\nshl $0x2,%rdi\ncallq 10c0 \nmov %rax,0x8(%r15)\ntest %ebx,%ebx\njle 1844 \nmov 0x0(%r13),%rcx\nlea 0xf(%rax),%rsi\nlea -0x1(%rbx),%edx\nsub %rcx,%rsi\ncmp $0x1e,%rsi\njbe 1960 \ncmp $0x3,%edx\njbe 1960 \nmov %ebx,%esi\nxor %edx,%edx\nshr $0x2,%esi\nshl $0x4,%rsi\nnopl 0x0(%rax,%rax,1)\nmovdqu (%rcx,%rdx,1),%xmm0\nmovups %xmm0,(%rax,%rdx,1)\nadd $0x10,%rdx\ncmp %rsi,%rdx\njne 17f8 \nmov %ebx,%edx\nand $0xfffffffc,%edx\ntest $0x3,%bl\nje 1844 \nmov %edx,%edi\nmov (%rcx,%rdi,4),%r8d\nlea 0x0(,%rdi,4),%rsi\nmov %r8d,(%rax,%rdi,4)\nlea 0x1(%rdx),%edi\ncmp %edi,%ebx\njle 1844 \nmov 0x4(%rcx,%rsi,1),%edi\nadd $0x2,%edx\nmov %edi,0x4(%rax,%rsi,1)\ncmp %edx,%ebx\njle 1844 \nmov 0x8(%rcx,%rsi,1),%edx\nmov %edx,0x8(%rax,%rsi,1)\nmov %ebx,(%r15)\nadd $0x1,%r14d\nadd $0x10,%r13\ncmp %rbp,%r13\njne 1788 \nadd $0x18,%rsp\nmov %r12,%rax\npop %rbx\npop %rbp\npop %r12\npop %r13\npop %r14\npop %r15\nretq\nnopw 0x0(%rax,%rax,1)\nmov (%r15),%r9d\nlea -0x1(%r9,%rbx,1),%r8d\nmov %r9d,0xc(%rsp)\nmovslq %r8d,%rsi\nmov %r8d,0x8(%rsp)\nshl $0x2,%rsi\ncallq 10d0 \ncmp $0x1,%ebx\nmov 0x8(%rsp),%r8d\nmov 0xc(%rsp),%r9d\nmov %rax,0x8(%r15)\njle 1957 \nmov 0x0(%r13),%rcx\nmovslq %r9d,%rsi\nlea -0x2(%rbx),%edx\nlea 0x10(%rax,%rsi,4),%r10\nlea (%rax,%rsi,4),%rdi\nlea 0x4(%rcx),%r11\ncmp %r10,%r11\nlea 0x14(%rcx),%r10\nsetae %r11b\ncmp %r10,%rdi\nsetae %r10b\nor %r10b,%r11b\nje 197f \ncmp $0x3,%edx\njbe 197f \nlea -0x1(%rbx),%r10d\nxor %edx,%edx\nmov %r10d,%esi\nshr $0x2,%esi\nshl $0x4,%rsi\nmovdqu 0x4(%rcx,%rdx,1),%xmm1\nmovups %xmm1,(%rdi,%rdx,1)\nadd $0x10,%rdx\ncmp %rsi,%rdx\njne 18f0 \nmov %r10d,%edx\nand $0xfffffffc,%edx\nlea 0x1(%rdx),%esi\ncmp %edx,%r10d\nje 1957 \nmovslq %esi,%r10\nadd %r9d,%esi\nlea 0x0(,%r10,4),%rdi\nmov (%rcx,%r10,4),%r10d\nmovslq %esi,%rsi\nmov %r10d,-0x4(%rax,%rsi,4)\nlea 0x2(%rdx),%esi\ncmp %ebx,%esi\njge 1957 \nmov 0x4(%rcx,%rdi,1),%r10d\nadd %r9d,%esi\nadd $0x3,%edx\nmovslq %esi,%rsi\nmov %r10d,-0x4(%rax,%rsi,4)\ncmp %ebx,%edx\njge 1957 \nmov 0x8(%rcx,%rdi,1),%ecx\nadd %r9d,%edx\nmovslq %edx,%rdx\nmov %ecx,-0x4(%rax,%rdx,4)\nmov %r8d,(%r15)\njmpq 184b \nmov %edx,%esi\nxor %edx,%edx\nnopl 0x0(%rax)\nmov (%rcx,%rdx,4),%edi\nmov %edi,(%rax,%rdx,4)\nmov %rdx,%rdi\nadd $0x1,%rdx\ncmp %rsi,%rdi\njne 1968 \njmpq 1844 \nlea (%rax,%rsi,4),%rdi\nadd $0x2,%rdx\nmov $0x1,%eax\nnopl 0x0(%rax)\nmov (%rcx,%rax,4),%esi\nmov %esi,-0x4(%rdi,%rax,4)\nadd $0x1,%rax\ncmp %rax,%rdx\njne 1990 \njmp 1957 \nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush r15\npush r14\nmov r14, rdi\npush r13\npush r12\npush rbp\nmovsxd rbp, esi\npush rbx\nmov r12, rbp\nshl rbp, 4\nmov rdi, rbp; size\nsub rsp, 28h\ncall _malloc\nmov rbx, rax\nlea rax, [r14+rbp]\nmov [rsp+58h+var_50], rax\ntest r12d, r12d\njle loc_17D7\nxor ebp, ebp\nxchg ax, ax\nloc_1740:\nmovsxd rdx, ebp\nmov r12d, [r14]\nmov r15, rdx\nshl r15, 4\ntest ebp, ebp\njle short loc_1768\nloc_1751:\nlea r13, [rbx+r15-10h]\nmov rax, [r14+8]\nmov rdi, [r13+8]; ptr\nmov eax, [rax]\ncmp [rdi], eax\njz loc_1870\nloc_1768:\nmovsxd r13, r12d\nadd r15, rbx\nshl r13, 2\nmov rdi, r13; size\ncall _malloc\nmov [r15+8], rax\nmov rdx, rax\ntest r12d, r12d\njle short loc_17BF\nlea eax, [r12-1]\nmov rsi, [r14+8]\ncmp eax, 2\njbe loc_1860\nlea rax, [rsi+4]\nmov rcx, rdx\nsub rcx, rax\nxor eax, eax\ncmp rcx, 8\nja short loc_17F0\nnop word ptr [rax+rax+00h]\nloc_17B0:\nmov ecx, [rsi+rax]\nmov [rdx+rax], ecx\nadd rax, 4\ncmp r13, rax\njnz short loc_17B0\nloc_17BF:\nmov rax, [rsp+58h+var_50]\nadd r14, 10h\nmov [r15], r12d\nadd ebp, 1\ncmp r14, rax\njnz loc_1740\nloc_17D7:\nadd rsp, 28h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_17F0:\nmov ecx, r12d\nshr ecx, 2\nshl rcx, 4\nnop word ptr [rax+rax+00h]\nloc_1800:\nmovdqu xmm0, xmmword ptr [rsi+rax]\nmovups xmmword ptr [rdx+rax], xmm0\nadd rax, 10h\ncmp rax, rcx\njnz short loc_1800\nmov eax, r12d\nand eax, 0FFFFFFFCh\ntest r12b, 3\njz short loc_17BF\nmov edi, eax\nmov r9d, [rsi+rdi*4]\nlea rcx, ds:0[rdi*4]\nmov [rdx+rdi*4], r9d\nlea edi, [rax+1]\ncmp r12d, edi\njle short loc_17BF\nmov edi, [rsi+rcx+4]\nadd eax, 2\nmov [rdx+rcx+4], edi\ncmp r12d, eax\njle loc_17BF\nmov eax, [rsi+rcx+8]\nmov [rdx+rcx+8], eax\njmp loc_17BF\nloc_1860:\nxor eax, eax\njmp loc_17B0\nloc_1870:\nmov r9d, [r13+0]\nmov [rsp+58h+var_40], rdx\nlea r15d, [r9+r12-1]\nmov [rsp+58h+var_44], r9d\nmovsxd rsi, r15d\nshl rsi, 2; size\ncall _realloc\ncmp r12d, 1\nmov r9d, [rsp+58h+var_44]\nmov rdx, [rsp+58h+var_40]\nmov [r13+8], rax\nmov rsi, rax\njle short loc_18E8\nlea eax, [r12-2]\nmov rcx, [r14+8]\ncmp eax, 2\nmovsxd rax, r9d\njbe short loc_18CB\nlea r10, [rsi+rax*4]\nlea r11, [rcx+8]\nmov rdi, r10\nsub rdi, r11\ncmp rdi, 8\nja short loc_190D\nloc_18CB:\nlea rdi, [rsi+rax*4]\nmov eax, 1\nnop dword ptr [rax+00h]\nloc_18D8:\nmov esi, [rcx+rax*4]\nmov [rdi+rax*4-4], esi\nadd rax, 1\ncmp r12, rax\njnz short loc_18D8\nloc_18E8:\nmov rax, [rsp+58h+var_50]\nadd r14, 10h\nmov [r13+0], r15d\ncmp r14, rax\njz loc_17D7\nmov r15, rdx\nmov r12d, [r14]\nshl r15, 4\njmp loc_1751\nloc_190D:\nlea r11d, [r12-1]\nxor eax, eax\nmov edi, r11d\nshr edi, 2\nshl rdi, 4\nxchg ax, ax\nloc_1920:\nmovdqu xmm1, xmmword ptr [rcx+rax+4]\nmovups xmmword ptr [r10+rax], xmm1\nadd rax, 10h\ncmp rdi, rax\njnz short loc_1920\nmov eax, r11d\nand eax, 0FFFFFFFCh\nand r11d, 3\nlea edi, [rax+1]\njz short loc_18E8\nmovsxd r11, edi\nadd edi, r9d\nlea r10, ds:0[r11*4]\nmov r11d, [rcx+r11*4]\nmovsxd rdi, edi\nmov [rsi+rdi*4-4], r11d\nlea edi, [rax+2]\ncmp edi, r12d\njge short loc_18E8\nmov r11d, [rcx+r10+4]\nadd edi, r9d\nadd eax, 3\nmovsxd rdi, edi\nmov [rsi+rdi*4-4], r11d\ncmp eax, r12d\njge loc_18E8\nmov ecx, [rcx+r10+8]\nadd eax, r9d\ncdqe\nmov [rsi+rax*4-4], ecx\njmp loc_18E8", + "ida_pseudo": "char *__fastcall func0(unsigned int *a1, int a2)\n{\n unsigned int *v2; // r14\n char *v3; // rbx\n int v4; // ebp\n __int64 v5; // rdx\n __int64 v6; // r12\n __int64 v7; // r15\n __int64 v8; // r13\n _DWORD *v9; // rdi\n char *v10; // r15\n char *v11; // rax\n char *v12; // rdx\n __int64 v13; // rsi\n __int64 v14; // rax\n unsigned int v16; // eax\n __int64 v17; // rcx\n int v18; // r15d\n _DWORD *v19; // rax\n _DWORD *v20; // rsi\n __int64 v21; // rcx\n __int64 i; // rax\n int v23; // r11d\n __int64 v24; // rax\n unsigned int v25; // eax\n signed int v26; // edi\n __int64 v27; // r10\n unsigned int v28; // edi\n int v29; // eax\n unsigned int *v30; // [rsp+8h] [rbp-50h]\n int v31; // [rsp+14h] [rbp-44h]\n __int64 v32; // [rsp+18h] [rbp-40h]\n\n v2 = a1;\n v3 = (char *)malloc(16LL * a2);\n v30 = &a1[4 * a2];\n if ( a2 > 0 )\n {\n v4 = 0;\n do\n {\n v5 = v4;\n v6 = *v2;\n v7 = 16LL * v4;\n if ( v4 > 0 )\n {\n while ( 1 )\n {\n v8 = (__int64)&v3[v7 - 16];\n v9 = *(_DWORD **)(v8 + 8);\n if ( *v9 != **((_DWORD **)v2 + 1) )\n break;\n v32 = v5;\n v18 = *(_DWORD *)v8 + v6 - 1;\n v31 = *(_DWORD *)v8;\n v19 = realloc(v9, 4LL * v18);\n v5 = v32;\n *(_QWORD *)(v8 + 8) = v19;\n v20 = v19;\n if ( (int)v6 > 1 )\n {\n v21 = *((_QWORD *)v2 + 1);\n if ( (unsigned int)(v6 - 2) > 2 && (unsigned __int64)&v19[v31 - 2] - v21 > 8 )\n {\n v23 = v6 - 1;\n v24 = 0LL;\n do\n {\n *(__m128i *)&v20[v31 + v24] = _mm_loadu_si128((const __m128i *)(v21 + v24 * 4 + 4));\n v24 += 4LL;\n }\n while ( 4LL * ((unsigned int)(v6 - 1) >> 2) != v24 );\n v25 = v23 & 0xFFFFFFFC;\n v26 = (v23 & 0xFFFFFFFC) + 1;\n if ( (v23 & 3) != 0 )\n {\n v27 = 4LL * v26;\n v20[v31 - 1 + v26] = *(_DWORD *)(v21 + v27);\n v28 = v25 + 2;\n if ( (int)(v25 + 2) < (int)v6 )\n {\n v29 = v25 + 3;\n v20[v31 + v28 - 1] = *(_DWORD *)(v21 + v27 + 4);\n if ( v29 < (int)v6 )\n v20[v31 - 1 + v29] = *(_DWORD *)(v21 + v27 + 8);\n }\n }\n }\n else\n {\n for ( i = 1LL; i != v6; ++i )\n v20[v31 - 1 + i] = *(_DWORD *)(v21 + 4 * i);\n }\n }\n v2 += 4;\n *(_DWORD *)v8 = v18;\n if ( v2 == v30 )\n return v3;\n v6 = *v2;\n v7 = 16 * v32;\n }\n }\n v10 = &v3[v7];\n v11 = (char *)malloc(4LL * (int)v6);\n *((_QWORD *)v10 + 1) = v11;\n v12 = v11;\n if ( (int)v6 <= 0 )\n goto LABEL_9;\n v13 = *((_QWORD *)v2 + 1);\n if ( (unsigned int)(v6 - 1) <= 2 )\n {\n v14 = 0LL;\n }\n else\n {\n v14 = 0LL;\n if ( (unsigned __int64)&v12[-v13 - 4] > 8 )\n {\n do\n {\n *(__m128i *)&v12[v14] = _mm_loadu_si128((const __m128i *)(v13 + v14));\n v14 += 16LL;\n }\n while ( v14 != 16LL * ((unsigned int)v6 >> 2) );\n v16 = v6 & 0x7FFFFFFC;\n if ( (v6 & 3) != 0 )\n {\n v17 = 4LL * v16;\n *(_DWORD *)&v12[v17] = *(_DWORD *)(v13 + v17);\n if ( (int)v6 > (int)(v16 + 1) )\n {\n *(_DWORD *)&v12[v17 + 4] = *(_DWORD *)(v13 + v17 + 4);\n if ( (int)v6 > (int)(v16 + 2) )\n *(_DWORD *)&v12[v17 + 8] = *(_DWORD *)(v13 + v17 + 8);\n }\n }\n goto LABEL_9;\n }\n }\n do\n {\n *(_DWORD *)&v12[v14] = *(_DWORD *)(v13 + v14);\n v14 += 4LL;\n }\n while ( 4LL * (int)v6 != v14 );\nLABEL_9:\n v2 += 4;\n *(_DWORD *)v10 = v6;\n ++v4;\n }\n while ( v2 != v30 );\n }\n return v3;\n}", + "ida_strip_asm": "sub_1700:\nendbr64\npush r15\npush r14\nmov r14, rdi\npush r13\npush r12\npush rbp\nmovsxd rbp, esi\npush rbx\nmov r12, rbp\nshl rbp, 4\nmov rdi, rbp; size\nsub rsp, 28h\ncall _malloc\nmov rbx, rax\nlea rax, [r14+rbp]\nmov [rsp+58h+var_50], rax\ntest r12d, r12d\njle loc_17D7\nxor ebp, ebp\nxchg ax, ax\nloc_1740:\nmovsxd rdx, ebp\nmov r12d, [r14]\nmov r15, rdx\nshl r15, 4\ntest ebp, ebp\njle short loc_1768\nloc_1751:\nlea r13, [rbx+r15-10h]\nmov rax, [r14+8]\nmov rdi, [r13+8]; ptr\nmov eax, [rax]\ncmp [rdi], eax\njz loc_1870\nloc_1768:\nmovsxd r13, r12d\nadd r15, rbx\nshl r13, 2\nmov rdi, r13; size\ncall _malloc\nmov [r15+8], rax\nmov rdx, rax\ntest r12d, r12d\njle short loc_17BF\nlea eax, [r12-1]\nmov rsi, [r14+8]\ncmp eax, 2\njbe loc_1860\nlea rax, [rsi+4]\nmov rcx, rdx\nsub rcx, rax\nxor eax, eax\ncmp rcx, 8\nja short loc_17F0\nnop word ptr [rax+rax+00h]\nloc_17B0:\nmov ecx, [rsi+rax]\nmov [rdx+rax], ecx\nadd rax, 4\ncmp r13, rax\njnz short loc_17B0\nloc_17BF:\nmov rax, [rsp+58h+var_50]\nadd r14, 10h\nmov [r15], r12d\nadd ebp, 1\ncmp r14, rax\njnz loc_1740\nloc_17D7:\nadd rsp, 28h\nmov rax, rbx\npop rbx\npop rbp\npop r12\npop r13\npop r14\npop r15\nretn\nloc_17F0:\nmov ecx, r12d\nshr ecx, 2\nshl rcx, 4\nnop word ptr [rax+rax+00h]\nloc_1800:\nmovdqu xmm0, xmmword ptr [rsi+rax]\nmovups xmmword ptr [rdx+rax], xmm0\nadd rax, 10h\ncmp rax, rcx\njnz short loc_1800\nmov eax, r12d\nand eax, 0FFFFFFFCh\ntest r12b, 3\njz short loc_17BF\nmov edi, eax\nmov r9d, [rsi+rdi*4]\nlea rcx, ds:0[rdi*4]\nmov [rdx+rdi*4], r9d\nlea edi, [rax+1]\ncmp r12d, edi\njle short loc_17BF\nmov edi, [rsi+rcx+4]\nadd eax, 2\nmov [rdx+rcx+4], edi\ncmp r12d, eax\njle loc_17BF\nmov eax, [rsi+rcx+8]\nmov [rdx+rcx+8], eax\njmp loc_17BF\nloc_1860:\nxor eax, eax\njmp loc_17B0\nloc_1870:\nmov r9d, [r13+0]\nmov [rsp+58h+var_40], rdx\nlea r15d, [r9+r12-1]\nmov [rsp+58h+var_44], r9d\nmovsxd rsi, r15d\nshl rsi, 2; size\ncall _realloc\ncmp r12d, 1\nmov r9d, [rsp+58h+var_44]\nmov rdx, [rsp+58h+var_40]\nmov [r13+8], rax\nmov rsi, rax\njle short loc_18E8\nlea eax, [r12-2]\nmov rcx, [r14+8]\ncmp eax, 2\nmovsxd rax, r9d\njbe short loc_18CB\nlea r10, [rsi+rax*4]\nlea r11, [rcx+8]\nmov rdi, r10\nsub rdi, r11\ncmp rdi, 8\nja short loc_190D\nloc_18CB:\nlea rdi, [rsi+rax*4]\nmov eax, 1\nnop dword ptr [rax+00h]\nloc_18D8:\nmov esi, [rcx+rax*4]\nmov [rdi+rax*4-4], esi\nadd rax, 1\ncmp r12, rax\njnz short loc_18D8\nloc_18E8:\nmov rax, [rsp+58h+var_50]\nadd r14, 10h\nmov [r13+0], r15d\ncmp r14, rax\njz loc_17D7\nmov r15, rdx\nmov r12d, [r14]\nshl r15, 4\njmp loc_1751\nloc_190D:\nlea r11d, [r12-1]\nxor eax, eax\nmov edi, r11d\nshr edi, 2\nshl rdi, 4\nxchg ax, ax\nloc_1920:\nmovdqu xmm1, xmmword ptr [rcx+rax+4]\nmovups xmmword ptr [r10+rax], xmm1\nadd rax, 10h\ncmp rdi, rax\njnz short loc_1920\nmov eax, r11d\nand eax, 0FFFFFFFCh\nand r11d, 3\nlea edi, [rax+1]\njz short loc_18E8\nmovsxd r11, edi\nadd edi, r9d\nlea r10, ds:0[r11*4]\nmov r11d, [rcx+r11*4]\nmovsxd rdi, edi\nmov [rsi+rdi*4-4], r11d\nlea edi, [rax+2]\ncmp edi, r12d\njge short loc_18E8\nmov r11d, [rcx+r10+4]\nadd edi, r9d\nadd eax, 3\nmovsxd rdi, edi\nmov [rsi+rdi*4-4], r11d\ncmp eax, r12d\njge loc_18E8\nmov ecx, [rcx+r10+8]\nadd eax, r9d\ncdqe\nmov [rsi+rax*4-4], ecx\njmp loc_18E8", + "ida_strip_pseudo": "char *__fastcall sub_1700(unsigned int *a1, int a2)\n{\n unsigned int *v2; // r14\n char *v3; // rbx\n int v4; // ebp\n __int64 v5; // rdx\n __int64 v6; // r12\n __int64 v7; // r15\n __int64 v8; // r13\n _DWORD *v9; // rdi\n char *v10; // r15\n char *v11; // rax\n char *v12; // rdx\n __int64 v13; // rsi\n __int64 v14; // rax\n unsigned int v16; // eax\n __int64 v17; // rcx\n int v18; // r15d\n _DWORD *v19; // rax\n _DWORD *v20; // rsi\n __int64 v21; // rcx\n __int64 i; // rax\n int v23; // r11d\n __int64 v24; // rax\n unsigned int v25; // eax\n signed int v26; // edi\n __int64 v27; // r10\n unsigned int v28; // edi\n int v29; // eax\n unsigned int *v30; // [rsp+8h] [rbp-50h]\n int v31; // [rsp+14h] [rbp-44h]\n __int64 v32; // [rsp+18h] [rbp-40h]\n\n v2 = a1;\n v3 = (char *)malloc(16LL * a2);\n v30 = &a1[4 * a2];\n if ( a2 > 0 )\n {\n v4 = 0;\n do\n {\n v5 = v4;\n v6 = *v2;\n v7 = 16LL * v4;\n if ( v4 > 0 )\n {\n while ( 1 )\n {\n v8 = (__int64)&v3[v7 - 16];\n v9 = *(_DWORD **)(v8 + 8);\n if ( *v9 != **((_DWORD **)v2 + 1) )\n break;\n v32 = v5;\n v18 = *(_DWORD *)v8 + v6 - 1;\n v31 = *(_DWORD *)v8;\n v19 = realloc(v9, 4LL * v18);\n v5 = v32;\n *(_QWORD *)(v8 + 8) = v19;\n v20 = v19;\n if ( (int)v6 > 1 )\n {\n v21 = *((_QWORD *)v2 + 1);\n if ( (unsigned int)(v6 - 2) > 2 && (unsigned __int64)&v19[v31 - 2] - v21 > 8 )\n {\n v23 = v6 - 1;\n v24 = 0LL;\n do\n {\n *(__m128i *)&v20[v31 + v24] = _mm_loadu_si128((const __m128i *)(v21 + v24 * 4 + 4));\n v24 += 4LL;\n }\n while ( 4LL * ((unsigned int)(v6 - 1) >> 2) != v24 );\n v25 = v23 & 0xFFFFFFFC;\n v26 = (v23 & 0xFFFFFFFC) + 1;\n if ( (v23 & 3) != 0 )\n {\n v27 = 4LL * v26;\n v20[v31 - 1 + v26] = *(_DWORD *)(v21 + v27);\n v28 = v25 + 2;\n if ( (int)(v25 + 2) < (int)v6 )\n {\n v29 = v25 + 3;\n v20[v31 + v28 - 1] = *(_DWORD *)(v21 + v27 + 4);\n if ( v29 < (int)v6 )\n v20[v31 - 1 + v29] = *(_DWORD *)(v21 + v27 + 8);\n }\n }\n }\n else\n {\n for ( i = 1LL; i != v6; ++i )\n v20[v31 - 1 + i] = *(_DWORD *)(v21 + 4 * i);\n }\n }\n v2 += 4;\n *(_DWORD *)v8 = v18;\n if ( v2 == v30 )\n return v3;\n v6 = *v2;\n v7 = 16 * v32;\n }\n }\n v10 = &v3[v7];\n v11 = (char *)malloc(4LL * (int)v6);\n *((_QWORD *)v10 + 1) = v11;\n v12 = v11;\n if ( (int)v6 <= 0 )\n goto LABEL_9;\n v13 = *((_QWORD *)v2 + 1);\n if ( (unsigned int)(v6 - 1) <= 2 )\n {\n v14 = 0LL;\n }\n else\n {\n v14 = 0LL;\n if ( (unsigned __int64)&v12[-v13 - 4] > 8 )\n {\n do\n {\n *(__m128i *)&v12[v14] = _mm_loadu_si128((const __m128i *)(v13 + v14));\n v14 += 16LL;\n }\n while ( v14 != 16LL * ((unsigned int)v6 >> 2) );\n v16 = v6 & 0x7FFFFFFC;\n if ( (v6 & 3) != 0 )\n {\n v17 = 4LL * v16;\n *(_DWORD *)&v12[v17] = *(_DWORD *)(v13 + v17);\n if ( (int)v6 > (int)(v16 + 1) )\n {\n *(_DWORD *)&v12[v17 + 4] = *(_DWORD *)(v13 + v17 + 4);\n if ( (int)v6 > (int)(v16 + 2) )\n *(_DWORD *)&v12[v17 + 8] = *(_DWORD *)(v13 + v17 + 8);\n }\n }\n goto LABEL_9;\n }\n }\n do\n {\n *(_DWORD *)&v12[v14] = *(_DWORD *)(v13 + v14);\n v14 += 4LL;\n }\n while ( 4LL * (int)v6 != v14 );\nLABEL_9:\n v2 += 4;\n *(_DWORD *)v10 = v6;\n ++v4;\n }\n while ( v2 != v30 );\n }\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_1700(unsigned int *a1, int a2) {\n unsigned int *v2;\n char *v3;\n int v4;\n long long v5;\n long long v6;\n long long v7;\n long long v8;\n uint32_t *v9;\n char *v10;\n char *v11;\n char *v12;\n long long v13;\n long long v14;\n unsigned int v16;\n long long v17;\n int v18;\n uint32_t *v19;\n uint32_t *v20;\n long long v21;\n long long i;\n int v23;\n long long v24;\n unsigned int v25;\n signed int v26;\n long long v27;\n unsigned int v28;\n int v29;\n unsigned int *v30;\n int v31;\n long long v32;\n v2 = a1;\n v3 = (char *)malloc(16LL * a2);\n v30 = &a1[4 * a2];\n if (a2 > 0) {\n v4 = 0;\n do {\n v5 = v4;\n v6 = *v2;\n v7 = 16LL * v4;\n if (v4 > 0) {\n while (1) {\n v8 = (long long)&v3[v7 - 16];\n v9 = *(uint32_t **)(v8 + 8);\n if (*v9 != **((uint32_t **)v2 + 1)) break;\n v32 = v5;\n v18 = *(uint32_t *)v8 + v6 - 1;\n v31 = *(uint32_t *)v8;\n v19 = realloc(v9, 4LL * v18);\n v5 = v32;\n *(uint64_t *)(v8 + 8) = v19;\n v20 = v19;\n if ((int)v6 > 1) {\n v21 = *((uint64_t *)v2 + 1);\n if ((unsigned int)(v6 - 2) > 2 &&\n (unsigned long long)&v19[v31 - 2] - v21 > 8) {\n v23 = v6 - 1;\n v24 = 0LL;\n do {\n *(__m128i *)&v20[v31 + v24] =\n _mm_loadu_si128((const __m128i *)(v21 + v24 * 4 + 4));\n v24 += 4LL;\n } while (4LL * ((unsigned int)(v6 - 1) >> 2) != v24);\n v25 = v23 & 4294967292;\n v26 = (v23 & 4294967292) + 1;\n if ((v23 & 3) != 0) {\n v27 = 4LL * v26;\n v20[v31 - 1 + v26] = *(uint32_t *)(v21 + v27);\n v28 = v25 + 2;\n if ((int)(v25 + 2) < (int)v6) {\n v29 = v25 + 3;\n v20[v31 + v28 - 1] = *(uint32_t *)(v21 + v27 + 4);\n if (v29 < (int)v6)\n v20[v31 - 1 + v29] = *(uint32_t *)(v21 + v27 + 8);\n }\n }\n } else {\n for (i = 1LL; i != v6; ++i)\n v20[v31 - 1 + i] = *(uint32_t *)(v21 + 4 * i);\n }\n }\n v2 += 4;\n *(uint32_t *)v8 = v18;\n if (v2 == v30) return v3;\n v6 = *v2;\n v7 = 16 * v32;\n }\n }\n v10 = &v3[v7];\n v11 = (char *)malloc(4LL * (int)v6);\n *((uint64_t *)v10 + 1) = v11;\n v12 = v11;\n if ((int)v6 <= 0) goto LABEL_9;\n v13 = *((uint64_t *)v2 + 1);\n if ((unsigned int)(v6 - 1) <= 2) {\n v14 = 0LL;\n } else {\n v14 = 0LL;\n if ((unsigned long long)&v12[-v13 - 4] > 8) {\n do {\n *(__m128i *)&v12[v14] =\n _mm_loadu_si128((const __m128i *)(v13 + v14));\n v14 += 16LL;\n } while (v14 != 16LL * ((unsigned int)v6 >> 2));\n v16 = v6 & 2147483644;\n if ((v6 & 3) != 0) {\n v17 = 4LL * v16;\n *(uint32_t *)&v12[v17] = *(uint32_t *)(v13 + v17);\n if ((int)v6 > (int)(v16 + 1)) {\n *(uint32_t *)&v12[v17 + 4] = *(uint32_t *)(v13 + v17 + 4);\n if ((int)v6 > (int)(v16 + 2))\n *(uint32_t *)&v12[v17 + 8] = *(uint32_t *)(v13 + v17 + 8);\n }\n }\n goto LABEL_9;\n }\n }\n do {\n *(uint32_t *)&v12[v14] = *(uint32_t *)(v13 + v14);\n v14 += 4LL;\n } while (4LL * (int)v6 != v14);\n LABEL_9:\n v2 += 4;\n *(uint32_t *)v10 = v6;\n ++v4;\n } while (v2 != v30);\n }\n return v3;\n}", + "ida_pseudo_norm": "char *func0(unsigned int *a1, int a2) {\n unsigned int *v2;\n char *v3;\n int v4;\n long long v5;\n long long v6;\n long long v7;\n long long v8;\n uint32_t *v9;\n char *v10;\n char *v11;\n char *v12;\n long long v13;\n long long v14;\n unsigned int v16;\n long long v17;\n int v18;\n uint32_t *v19;\n uint32_t *v20;\n long long v21;\n long long i;\n int v23;\n long long v24;\n unsigned int v25;\n signed int v26;\n long long v27;\n unsigned int v28;\n int v29;\n unsigned int *v30;\n int v31;\n long long v32;\n v2 = a1;\n v3 = (char *)malloc(16LL * a2);\n v30 = &a1[4 * a2];\n if (a2 > 0) {\n v4 = 0;\n do {\n v5 = v4;\n v6 = *v2;\n v7 = 16LL * v4;\n if (v4 > 0) {\n while (1) {\n v8 = (long long)&v3[v7 - 16];\n v9 = *(uint32_t **)(v8 + 8);\n if (*v9 != **((uint32_t **)v2 + 1)) break;\n v32 = v5;\n v18 = *(uint32_t *)v8 + v6 - 1;\n v31 = *(uint32_t *)v8;\n v19 = realloc(v9, 4LL * v18);\n v5 = v32;\n *(uint64_t *)(v8 + 8) = v19;\n v20 = v19;\n if ((int)v6 > 1) {\n v21 = *((uint64_t *)v2 + 1);\n if ((unsigned int)(v6 - 2) > 2 &&\n (unsigned long long)&v19[v31 - 2] - v21 > 8) {\n v23 = v6 - 1;\n v24 = 0LL;\n do {\n *(__m128i *)&v20[v31 + v24] =\n _mm_loadu_si128((const __m128i *)(v21 + v24 * 4 + 4));\n v24 += 4LL;\n } while (4LL * ((unsigned int)(v6 - 1) >> 2) != v24);\n v25 = v23 & 4294967292;\n v26 = (v23 & 4294967292) + 1;\n if ((v23 & 3) != 0) {\n v27 = 4LL * v26;\n v20[v31 - 1 + v26] = *(uint32_t *)(v21 + v27);\n v28 = v25 + 2;\n if ((int)(v25 + 2) < (int)v6) {\n v29 = v25 + 3;\n v20[v31 + v28 - 1] = *(uint32_t *)(v21 + v27 + 4);\n if (v29 < (int)v6)\n v20[v31 - 1 + v29] = *(uint32_t *)(v21 + v27 + 8);\n }\n }\n } else {\n for (i = 1LL; i != v6; ++i)\n v20[v31 - 1 + i] = *(uint32_t *)(v21 + 4 * i);\n }\n }\n v2 += 4;\n *(uint32_t *)v8 = v18;\n if (v2 == v30) return v3;\n v6 = *v2;\n v7 = 16 * v32;\n }\n }\n v10 = &v3[v7];\n v11 = (char *)malloc(4LL * (int)v6);\n *((uint64_t *)v10 + 1) = v11;\n v12 = v11;\n if ((int)v6 <= 0) goto LABEL_9;\n v13 = *((uint64_t *)v2 + 1);\n if ((unsigned int)(v6 - 1) <= 2) {\n v14 = 0LL;\n } else {\n v14 = 0LL;\n if ((unsigned long long)&v12[-v13 - 4] > 8) {\n do {\n *(__m128i *)&v12[v14] =\n _mm_loadu_si128((const __m128i *)(v13 + v14));\n v14 += 16LL;\n } while (v14 != 16LL * ((unsigned int)v6 >> 2));\n v16 = v6 & 2147483644;\n if ((v6 & 3) != 0) {\n v17 = 4LL * v16;\n *(uint32_t *)&v12[v17] = *(uint32_t *)(v13 + v17);\n if ((int)v6 > (int)(v16 + 1)) {\n *(uint32_t *)&v12[v17 + 4] = *(uint32_t *)(v13 + v17 + 4);\n if ((int)v6 > (int)(v16 + 2))\n *(uint32_t *)&v12[v17 + 8] = *(uint32_t *)(v13 + v17 + 8);\n }\n }\n goto LABEL_9;\n }\n }\n do {\n *(uint32_t *)&v12[v14] = *(uint32_t *)(v13 + v14);\n v14 += 4LL;\n } while (4LL * (int)v6 != v14);\n LABEL_9:\n v2 += 4;\n *(uint32_t *)v10 = v6;\n ++v4;\n } while (v2 != v30);\n }\n return v3;\n}" + }, + { + "index": 970, + "func_name": "func0", + "func_dep": "\n\n#include \n\n\n\n", + "func": "int func0(int x, int y) {\n if (x < y) {\n return x;\n }\n return y;\n}", + "test": "int main() {\n\n assert(func0(10, 20) == 10);\n\n assert(func0(19, 15) == 15);\n\n assert(func0(-10, -20) == -20);\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nmov %edi,-0x4(%rbp)\nmov %esi,-0x8(%rbp)\nmov -0x4(%rbp),%eax\ncmp -0x8(%rbp),%eax\njge 1164 \nmov -0x4(%rbp),%eax\njmp 1167 \nmov -0x8(%rbp),%eax\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_8]\njge short loc_1164\nmov eax, [rbp+var_4]\njmp short loc_1167\nloc_1164:\nmov eax, [rbp+var_8]\nloc_1167:\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(unsigned int a1, unsigned int a2)\n{\n if ( (int)a1 >= (int)a2 )\n return a2;\n else\n return a1;\n}", + "ida_strip_asm": "sub_1149:\nendbr64\npush rbp\nmov rbp, rsp\nmov [rbp+var_4], edi\nmov [rbp+var_8], esi\nmov eax, [rbp+var_4]\ncmp eax, [rbp+var_8]\njge short loc_1164\nmov eax, [rbp+var_4]\njmp short loc_1167\nloc_1164:\nmov eax, [rbp+var_8]\nloc_1167:\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1149(unsigned int a1, unsigned int a2)\n{\n if ( (int)a1 >= (int)a2 )\n return a2;\n else\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1149(unsigned int a1, unsigned int a2) {\n if ((int)a1 >= (int)a2)\n return a2;\n else\n return a1;\n}", + "ida_pseudo_norm": "long long func0(unsigned int a1, unsigned int a2) {\n if ((int)a1 >= (int)a2)\n return a2;\n else\n return a1;\n}" + }, + { + "index": 971, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(int n, int a, int b, int c) {\n int dp[n + 10];\n for (int i = 0; i < n + 10; i++) {\n dp[i] = -1;\n }\n dp[0] = 0;\n for (int i = 0; i <= n; i++) {\n if (dp[i] != -1) {\n if (i + a <= n) {\n dp[i + a] = (dp[i] + 1 > dp[i + a]) ? dp[i] + 1 : dp[i + a];\n }\n if (i + b <= n) {\n dp[i + b] = (dp[i] + 1 > dp[i + b]) ? dp[i] + 1 : dp[i + b];\n }\n if (i + c <= n) {\n dp[i + c] = (dp[i] + 1 > dp[i + c]) ? dp[i] + 1 : dp[i + c];\n }\n }\n }\n return dp[n];\n}", + "test": "int main() {\n\n assert(func0(7, 5, 2, 5) == 2);\n\n assert(func0(17, 2, 1, 3) == 17);\n\n assert(func0(18, 16, 3, 6) == 6);\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %edi,-0x24(%rbp)\nmov %esi,-0x28(%rbp)\nmov %edx,-0x2c(%rbp)\nmov %ecx,-0x30(%rbp)\nmov %fs:0x28,%rax\nmov %rax,-0x8(%rbp)\nxor %eax,%eax\nmov %rsp,%rax\nmov %rax,%rsi\nmov -0x24(%rbp),%eax\nadd $0xa,%eax\nmovslq %eax,%rdx\nsub $0x1,%rdx\nmov %rdx,-0x18(%rbp)\nmovslq %eax,%rdx\nmov %rdx,%r10\nmov $0x0,%r11d\nmovslq %eax,%rdx\nmov %rdx,%r8\nmov $0x0,%r9d\ncltq\nlea 0x0(,%rax,4),%rdx\nmov $0x10,%eax\nsub $0x1,%rax\nadd %rdx,%rax\nmov $0x10,%edi\nmov $0x0,%edx\ndiv %rdi\nimul $0x10,%rax,%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rdx\nmov %rsp,%rdi\nsub %rdx,%rdi\nmov %rdi,%rdx\ncmp %rdx,%rsp\nje 1230 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 1219 \nmov %rax,%rdx\nand $0xfff,%edx\nsub %rdx,%rsp\nmov %rax,%rdx\nand $0xfff,%edx\ntest %rdx,%rdx\nje 125a \nand $0xfff,%eax\nsub $0x8,%rax\nadd %rsp,%rax\norq $0x0,(%rax)\nmov %rsp,%rax\nadd $0x3,%rax\nshr $0x2,%rax\nshl $0x2,%rax\nmov %rax,-0x10(%rbp)\nmovl $0x0,-0x1c(%rbp)\njmp 128b \nmov -0x10(%rbp),%rax\nmov -0x1c(%rbp),%edx\nmovslq %edx,%rdx\nmovl $0xffffffff,(%rax,%rdx,4)\naddl $0x1,-0x1c(%rbp)\nmov -0x24(%rbp),%eax\nadd $0x9,%eax\ncmp %eax,-0x1c(%rbp)\njle 1276 \nmov -0x10(%rbp),%rax\nmovl $0x0,(%rax)\nmovl $0x0,-0x20(%rbp)\njmpq 13f8 \nmov -0x10(%rbp),%rax\nmov -0x20(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\ncmp $0xffffffff,%eax\nje 13f4 \nmov -0x20(%rbp),%edx\nmov -0x28(%rbp),%eax\nadd %edx,%eax\ncmp %eax,-0x24(%rbp)\njl 1328 \nmov -0x10(%rbp),%rax\nmov -0x20(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%ecx\nmov -0x20(%rbp),%edx\nmov -0x28(%rbp),%eax\nadd %eax,%edx\nmov -0x10(%rbp),%rax\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\ncmp %eax,%ecx\njl 1304 \nmov -0x10(%rbp),%rax\nmov -0x20(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nadd $0x1,%eax\njmp 1316 \nmov -0x20(%rbp),%edx\nmov -0x28(%rbp),%eax\nadd %eax,%edx\nmov -0x10(%rbp),%rax\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nmov -0x20(%rbp),%ecx\nmov -0x28(%rbp),%edx\nadd %edx,%ecx\nmov -0x10(%rbp),%rdx\nmovslq %ecx,%rcx\nmov %eax,(%rdx,%rcx,4)\nmov -0x20(%rbp),%edx\nmov -0x2c(%rbp),%eax\nadd %edx,%eax\ncmp %eax,-0x24(%rbp)\njl 138e \nmov -0x10(%rbp),%rax\nmov -0x20(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%ecx\nmov -0x20(%rbp),%edx\nmov -0x2c(%rbp),%eax\nadd %eax,%edx\nmov -0x10(%rbp),%rax\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\ncmp %eax,%ecx\njl 136a \nmov -0x10(%rbp),%rax\nmov -0x20(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nadd $0x1,%eax\njmp 137c \nmov -0x20(%rbp),%edx\nmov -0x2c(%rbp),%eax\nadd %eax,%edx\nmov -0x10(%rbp),%rax\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nmov -0x20(%rbp),%ecx\nmov -0x2c(%rbp),%edx\nadd %edx,%ecx\nmov -0x10(%rbp),%rdx\nmovslq %ecx,%rcx\nmov %eax,(%rdx,%rcx,4)\nmov -0x20(%rbp),%edx\nmov -0x30(%rbp),%eax\nadd %edx,%eax\ncmp %eax,-0x24(%rbp)\njl 13f4 \nmov -0x10(%rbp),%rax\nmov -0x20(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%ecx\nmov -0x20(%rbp),%edx\nmov -0x30(%rbp),%eax\nadd %eax,%edx\nmov -0x10(%rbp),%rax\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\ncmp %eax,%ecx\njl 13d0 \nmov -0x10(%rbp),%rax\nmov -0x20(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nadd $0x1,%eax\njmp 13e2 \nmov -0x20(%rbp),%edx\nmov -0x30(%rbp),%eax\nadd %eax,%edx\nmov -0x10(%rbp),%rax\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nmov -0x20(%rbp),%ecx\nmov -0x30(%rbp),%edx\nadd %edx,%ecx\nmov -0x10(%rbp),%rdx\nmovslq %ecx,%rcx\nmov %eax,(%rdx,%rcx,4)\naddl $0x1,-0x20(%rbp)\nmov -0x20(%rbp),%eax\ncmp -0x24(%rbp),%eax\njle 12ac \nmov -0x10(%rbp),%rax\nmov -0x24(%rbp),%edx\nmovslq %edx,%rdx\nmov (%rax,%rdx,4),%eax\nmov %rsi,%rsp\nmov -0x8(%rbp),%rsi\nxor %fs:0x28,%rsi\nje 1428 \ncallq 1080 <__stack_chk_fail@plt>\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_24], edi\nmov [rbp+var_28], esi\nmov [rbp+var_2C], edx\nmov [rbp+var_30], ecx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov eax, [rbp+var_24]\nadd eax, 0Ah\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11FE:\ncmp rsp, rdx\njz short loc_1215\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\njmp short loc_11FE\nloc_1215:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_123F\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_123F:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov [rbp+var_20], 0\njmp short loc_1270\nloc_125B:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nmov dword ptr [rax+rdx*4], 0FFFFFFFFh\nadd [rbp+var_20], 1\nloc_1270:\nmov eax, [rbp+var_24]\nadd eax, 9\ncmp [rbp+var_20], eax\njle short loc_125B\nmov rax, [rbp+var_10]\nmov dword ptr [rax], 0\nmov [rbp+var_1C], 0\njmp loc_13DD\nloc_1291:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ncmp eax, 0FFFFFFFFh\njz loc_13D9\nmov edx, [rbp+var_1C]\nmov eax, [rbp+var_28]\nadd eax, edx\ncmp [rbp+var_24], eax\njl short loc_130D\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov edx, [rbp+var_1C]\nmov eax, [rbp+var_28]\nadd edx, eax\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ncmp ecx, eax\njl short loc_12E9\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nadd eax, 1\njmp short loc_12FB\nloc_12E9:\nmov edx, [rbp+var_1C]\nmov eax, [rbp+var_28]\nadd edx, eax\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nloc_12FB:\nmov ecx, [rbp+var_1C]\nmov edx, [rbp+var_28]\nadd ecx, edx\nmov rdx, [rbp+var_10]\nmovsxd rcx, ecx\nmov [rdx+rcx*4], eax\nloc_130D:\nmov edx, [rbp+var_1C]\nmov eax, [rbp+var_2C]\nadd eax, edx\ncmp [rbp+var_24], eax\njl short loc_1373\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov edx, [rbp+var_1C]\nmov eax, [rbp+var_2C]\nadd edx, eax\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ncmp ecx, eax\njl short loc_134F\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nadd eax, 1\njmp short loc_1361\nloc_134F:\nmov edx, [rbp+var_1C]\nmov eax, [rbp+var_2C]\nadd edx, eax\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nloc_1361:\nmov ecx, [rbp+var_1C]\nmov edx, [rbp+var_2C]\nadd ecx, edx\nmov rdx, [rbp+var_10]\nmovsxd rcx, ecx\nmov [rdx+rcx*4], eax\nloc_1373:\nmov edx, [rbp+var_1C]\nmov eax, [rbp+var_30]\nadd eax, edx\ncmp [rbp+var_24], eax\njl short loc_13D9\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov edx, [rbp+var_1C]\nmov eax, [rbp+var_30]\nadd edx, eax\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ncmp ecx, eax\njl short loc_13B5\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nadd eax, 1\njmp short loc_13C7\nloc_13B5:\nmov edx, [rbp+var_1C]\nmov eax, [rbp+var_30]\nadd edx, eax\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nloc_13C7:\nmov ecx, [rbp+var_1C]\nmov edx, [rbp+var_30]\nadd ecx, edx\nmov rdx, [rbp+var_10]\nmovsxd rcx, ecx\nmov [rdx+rcx*4], eax\nloc_13D9:\nadd [rbp+var_1C], 1\nloc_13DD:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_24]\njle loc_1291\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_140D\ncall ___stack_chk_fail\nlocret_140D:\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, int a3, int a4)\n{\n unsigned __int64 v4; // rax\n void *v5; // rsp\n int v6; // eax\n int v7; // eax\n int v8; // eax\n int v10; // [rsp+8h] [rbp-30h] BYREF\n int v11; // [rsp+Ch] [rbp-2Ch]\n int v12; // [rsp+10h] [rbp-28h]\n int v13; // [rsp+14h] [rbp-24h]\n int i; // [rsp+18h] [rbp-20h]\n int j; // [rsp+1Ch] [rbp-1Ch]\n __int64 v16; // [rsp+20h] [rbp-18h]\n int *v17; // [rsp+28h] [rbp-10h]\n unsigned __int64 v18; // [rsp+30h] [rbp-8h]\n\n v13 = a1;\n v12 = a2;\n v11 = a3;\n v10 = a4;\n v18 = __readfsqword(0x28u);\n v16 = a1 + 10 - 1LL;\n v4 = 16 * ((4LL * (a1 + 10) + 15) / 0x10uLL);\n while ( &v10 != (int *)((char *)&v10 - (v4 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v5 = alloca(v4 & 0xFFF);\n if ( (v4 & 0xFFF) != 0 )\n *(_QWORD *)((char *)&v10 + (v4 & 0xFFF) - 8) = *(_QWORD *)((char *)&v10 + (v4 & 0xFFF) - 8);\n v17 = &v10;\n for ( i = 0; i <= v13 + 9; ++i )\n v17[i] = -1;\n *v17 = 0;\n for ( j = 0; j <= v13; ++j )\n {\n if ( v17[j] != -1 )\n {\n if ( v13 >= j + v12 )\n {\n if ( v17[j] < v17[v12 + j] )\n v6 = v17[v12 + j];\n else\n v6 = v17[j] + 1;\n v17[v12 + j] = v6;\n }\n if ( v13 >= j + v11 )\n {\n if ( v17[j] < v17[v11 + j] )\n v7 = v17[v11 + j];\n else\n v7 = v17[j] + 1;\n v17[v11 + j] = v7;\n }\n if ( v13 >= j + v10 )\n {\n if ( v17[j] < v17[v10 + j] )\n v8 = v17[v10 + j];\n else\n v8 = v17[j] + 1;\n v17[v10 + j] = v8;\n }\n }\n }\n return (unsigned int)v17[v13];\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_24], edi\nmov [rbp+var_28], esi\nmov [rbp+var_2C], edx\nmov [rbp+var_30], ecx\nmov rax, fs:28h\nmov [rbp+var_8], rax\nxor eax, eax\nmov rax, rsp\nmov rsi, rax\nmov eax, [rbp+var_24]\nadd eax, 0Ah\nmovsxd rdx, eax\nsub rdx, 1\nmov [rbp+var_18], rdx\ncdqe\nlea rdx, ds:0[rax*4]\nmov eax, 10h\nsub rax, 1\nadd rax, rdx\nmov edi, 10h\nmov edx, 0\ndiv rdi\nimul rax, 10h\nmov rcx, rax\nand rcx, 0FFFFFFFFFFFFF000h\nmov rdx, rsp\nsub rdx, rcx\nloc_11FE:\ncmp rsp, rdx\njz short loc_1215\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\njmp short loc_11FE\nloc_1215:\nmov rdx, rax\nand edx, 0FFFh\nsub rsp, rdx\nmov rdx, rax\nand edx, 0FFFh\ntest rdx, rdx\njz short loc_123F\nand eax, 0FFFh\nsub rax, 8\nadd rax, rsp\nor qword ptr [rax], 0\nloc_123F:\nmov rax, rsp\nadd rax, 3\nshr rax, 2\nshl rax, 2\nmov [rbp+var_10], rax\nmov [rbp+var_20], 0\njmp short loc_1270\nloc_125B:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nmov dword ptr [rax+rdx*4], 0FFFFFFFFh\nadd [rbp+var_20], 1\nloc_1270:\nmov eax, [rbp+var_24]\nadd eax, 9\ncmp [rbp+var_20], eax\njle short loc_125B\nmov rax, [rbp+var_10]\nmov dword ptr [rax], 0\nmov [rbp+var_1C], 0\njmp loc_13DD\nloc_1291:\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ncmp eax, 0FFFFFFFFh\njz loc_13D9\nmov edx, [rbp+var_1C]\nmov eax, [rbp+var_28]\nadd eax, edx\ncmp [rbp+var_24], eax\njl short loc_130D\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov edx, [rbp+var_1C]\nmov eax, [rbp+var_28]\nadd edx, eax\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ncmp ecx, eax\njl short loc_12E9\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nadd eax, 1\njmp short loc_12FB\nloc_12E9:\nmov edx, [rbp+var_1C]\nmov eax, [rbp+var_28]\nadd edx, eax\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nloc_12FB:\nmov ecx, [rbp+var_1C]\nmov edx, [rbp+var_28]\nadd ecx, edx\nmov rdx, [rbp+var_10]\nmovsxd rcx, ecx\nmov [rdx+rcx*4], eax\nloc_130D:\nmov edx, [rbp+var_1C]\nmov eax, [rbp+var_2C]\nadd eax, edx\ncmp [rbp+var_24], eax\njl short loc_1373\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov edx, [rbp+var_1C]\nmov eax, [rbp+var_2C]\nadd edx, eax\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ncmp ecx, eax\njl short loc_134F\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nadd eax, 1\njmp short loc_1361\nloc_134F:\nmov edx, [rbp+var_1C]\nmov eax, [rbp+var_2C]\nadd edx, eax\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nloc_1361:\nmov ecx, [rbp+var_1C]\nmov edx, [rbp+var_2C]\nadd ecx, edx\nmov rdx, [rbp+var_10]\nmovsxd rcx, ecx\nmov [rdx+rcx*4], eax\nloc_1373:\nmov edx, [rbp+var_1C]\nmov eax, [rbp+var_30]\nadd eax, edx\ncmp [rbp+var_24], eax\njl short loc_13D9\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov ecx, [rax+rdx*4]\nmov edx, [rbp+var_1C]\nmov eax, [rbp+var_30]\nadd edx, eax\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\ncmp ecx, eax\njl short loc_13B5\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_1C]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nadd eax, 1\njmp short loc_13C7\nloc_13B5:\nmov edx, [rbp+var_1C]\nmov eax, [rbp+var_30]\nadd edx, eax\nmov rax, [rbp+var_10]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nloc_13C7:\nmov ecx, [rbp+var_1C]\nmov edx, [rbp+var_30]\nadd ecx, edx\nmov rdx, [rbp+var_10]\nmovsxd rcx, ecx\nmov [rdx+rcx*4], eax\nloc_13D9:\nadd [rbp+var_1C], 1\nloc_13DD:\nmov eax, [rbp+var_1C]\ncmp eax, [rbp+var_24]\njle loc_1291\nmov rax, [rbp+var_10]\nmov edx, [rbp+var_24]\nmovsxd rdx, edx\nmov eax, [rax+rdx*4]\nmov rsp, rsi\nmov rdx, [rbp+var_8]\nsub rdx, fs:28h\njz short locret_140D\ncall ___stack_chk_fail\nlocret_140D:\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(int a1, int a2, int a3, int a4)\n{\n unsigned __int64 v4; // rax\n void *v5; // rsp\n int v6; // eax\n int v7; // eax\n int v8; // eax\n int v10; // [rsp+8h] [rbp-30h] BYREF\n int v11; // [rsp+Ch] [rbp-2Ch]\n int v12; // [rsp+10h] [rbp-28h]\n int v13; // [rsp+14h] [rbp-24h]\n int i; // [rsp+18h] [rbp-20h]\n int j; // [rsp+1Ch] [rbp-1Ch]\n __int64 v16; // [rsp+20h] [rbp-18h]\n int *v17; // [rsp+28h] [rbp-10h]\n unsigned __int64 v18; // [rsp+30h] [rbp-8h]\n\n v13 = a1;\n v12 = a2;\n v11 = a3;\n v10 = a4;\n v18 = __readfsqword(0x28u);\n v16 = a1 + 10 - 1LL;\n v4 = 16 * ((4LL * (a1 + 10) + 15) / 0x10uLL);\n while ( &v10 != (int *)((char *)&v10 - (v4 & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v5 = alloca(v4 & 0xFFF);\n if ( (v4 & 0xFFF) != 0 )\n *(_QWORD *)((char *)&v10 + (v4 & 0xFFF) - 8) = *(_QWORD *)((char *)&v10 + (v4 & 0xFFF) - 8);\n v17 = &v10;\n for ( i = 0; i <= v13 + 9; ++i )\n v17[i] = -1;\n *v17 = 0;\n for ( j = 0; j <= v13; ++j )\n {\n if ( v17[j] != -1 )\n {\n if ( v13 >= j + v12 )\n {\n if ( v17[j] < v17[v12 + j] )\n v6 = v17[v12 + j];\n else\n v6 = v17[j] + 1;\n v17[v12 + j] = v6;\n }\n if ( v13 >= j + v11 )\n {\n if ( v17[j] < v17[v11 + j] )\n v7 = v17[v11 + j];\n else\n v7 = v17[j] + 1;\n v17[v11 + j] = v7;\n }\n if ( v13 >= j + v10 )\n {\n if ( v17[j] < v17[v10 + j] )\n v8 = v17[v10 + j];\n else\n v8 = v17[j] + 1;\n v17[v10 + j] = v8;\n }\n }\n }\n return (unsigned int)v17[v13];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(int a1, int a2, int a3, int a4) {\n unsigned long long v4;\n void *v5;\n int v6;\n int v7;\n int v8;\n int v10;\n int v11;\n int v12;\n int v13;\n int i;\n int j;\n long long v16;\n int *v17;\n unsigned long long v18;\n v13 = a1;\n v12 = a2;\n v11 = a3;\n v10 = a4;\n v18 = __readfsqword(40u);\n v16 = a1 + 10 - 1LL;\n v4 = 16 * ((4LL * (a1 + 10) + 15) / 16uLL);\n while (&v10 != (int *)((char *)&v10 - (v4 & 18446744073709547520LL)))\n ;\n v5 = alloca(v4 & 4095);\n if ((v4 & 4095) != 0)\n *(uint64_t *)((char *)&v10 + (v4 & 4095) - 8) =\n *(uint64_t *)((char *)&v10 + (v4 & 4095) - 8);\n v17 = &v10;\n for (i = 0; i <= v13 + 9; ++i) v17[i] = -1;\n *v17 = 0;\n for (j = 0; j <= v13; ++j) {\n if (v17[j] != -1) {\n if (v13 >= j + v12) {\n if (v17[j] < v17[v12 + j])\n v6 = v17[v12 + j];\n else\n v6 = v17[j] + 1;\n v17[v12 + j] = v6;\n }\n if (v13 >= j + v11) {\n if (v17[j] < v17[v11 + j])\n v7 = v17[v11 + j];\n else\n v7 = v17[j] + 1;\n v17[v11 + j] = v7;\n }\n if (v13 >= j + v10) {\n if (v17[j] < v17[v10 + j])\n v8 = v17[v10 + j];\n else\n v8 = v17[j] + 1;\n v17[v10 + j] = v8;\n }\n }\n }\n return (unsigned int)v17[v13];\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, int a3, int a4) {\n unsigned long long v4;\n void *v5;\n int v6;\n int v7;\n int v8;\n int v10;\n int v11;\n int v12;\n int v13;\n int i;\n int j;\n long long v16;\n int *v17;\n unsigned long long v18;\n v13 = a1;\n v12 = a2;\n v11 = a3;\n v10 = a4;\n v18 = __readfsqword(40u);\n v16 = a1 + 10 - 1LL;\n v4 = 16 * ((4LL * (a1 + 10) + 15) / 16uLL);\n while (&v10 != (int *)((char *)&v10 - (v4 & 18446744073709547520LL)))\n ;\n v5 = alloca(v4 & 4095);\n if ((v4 & 4095) != 0)\n *(uint64_t *)((char *)&v10 + (v4 & 4095) - 8) =\n *(uint64_t *)((char *)&v10 + (v4 & 4095) - 8);\n v17 = &v10;\n for (i = 0; i <= v13 + 9; ++i) v17[i] = -1;\n *v17 = 0;\n for (j = 0; j <= v13; ++j) {\n if (v17[j] != -1) {\n if (v13 >= j + v12) {\n if (v17[j] < v17[v12 + j])\n v6 = v17[v12 + j];\n else\n v6 = v17[j] + 1;\n v17[v12 + j] = v6;\n }\n if (v13 >= j + v11) {\n if (v17[j] < v17[v11 + j])\n v7 = v17[v11 + j];\n else\n v7 = v17[j] + 1;\n v17[v11 + j] = v7;\n }\n if (v13 >= j + v10) {\n if (v17[j] < v17[v10 + j])\n v8 = v17[v10 + j];\n else\n v8 = v17[j] + 1;\n v17[v10 + j] = v8;\n }\n }\n }\n return (unsigned int)v17[v13];\n}" + }, + { + "index": 971, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(int n, int a, int b, int c) {\n int dp[n + 10];\n for (int i = 0; i < n + 10; i++) {\n dp[i] = -1;\n }\n dp[0] = 0;\n for (int i = 0; i <= n; i++) {\n if (dp[i] != -1) {\n if (i + a <= n) {\n dp[i + a] = (dp[i] + 1 > dp[i + a]) ? dp[i] + 1 : dp[i + a];\n }\n if (i + b <= n) {\n dp[i + b] = (dp[i] + 1 > dp[i + b]) ? dp[i] + 1 : dp[i + b];\n }\n if (i + c <= n) {\n dp[i + c] = (dp[i] + 1 > dp[i + c]) ? dp[i] + 1 : dp[i + c];\n }\n }\n }\n return dp[n];\n}", + "test": "int main() {\n\n assert(func0(7, 5, 2, 5) == 2);\n\n assert(func0(17, 2, 1, 3) == 17);\n\n assert(func0(18, 16, 3, 6) == 6);\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r14\npush %r13\npush %r12\npush %rbx\nsub $0x10,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x28(%rbp)\nxor %eax,%eax\nlea 0xa(%rdi),%eax\ncltq\nlea 0xf(,%rax,4),%rax\nmov %rax,%r8\nand $0xfffffffffffffff0,%r8\nand $0xfffffffffffff000,%rax\nmov %rsp,%rbx\nsub %rax,%rbx\nmov %rbx,%rax\ncmp %rax,%rsp\nje 11e5 \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\njmp 11ce \nmov %r8,%rax\nand $0xfff,%eax\nsub %rax,%rsp\ntest %rax,%rax\nje 11fb \norq $0x0,-0x8(%rsp,%rax,1)\nlea 0x3(%rsp),%r11\nmov %r11,%r10\nshr $0x2,%r10\nand $0xfffffffffffffffc,%r11\nmov %r11,%r9\ncmp $0xfffffff7,%edi\njl 122e \nmov %r11,%rax\nlea 0x9(%rdi),%r8d\nlea 0x4(%r11,%r8,4),%r8\nmovl $0xffffffff,(%rax)\nadd $0x4,%rax\ncmp %r8,%rax\njne 121f \nmovl $0x0,0x0(,%r10,4)\ntest %edi,%edi\njs 12dc \nmov %edi,%ebx\nmov $0x0,%eax\njmp 125b \nlea 0x1(%rax),%r8\ncmp %rbx,%rax\nje 12dc \nmov %r8,%rax\nmov (%r9,%rax,4),%r10d\ncmp $0xffffffff,%r10d\nje 124b \nmov %eax,%r8d\nlea (%rsi,%rax,1),%r12d\ncmp %r12d,%edi\njl 128b \nmovslq %r12d,%r12\nlea (%r9,%r12,4),%r13\nmov 0x0(%r13),%r12d\nlea 0x1(%r10),%r14d\ncmp %r12d,%r10d\ncmovge %r14d,%r12d\nmov %r12d,0x0(%r13)\nlea (%rdx,%r8,1),%r10d\ncmp %r10d,%edi\njl 12b2 \nmov (%r9,%rax,4),%r13d\nmovslq %r10d,%r10\nlea (%r9,%r10,4),%r12\nmov (%r12),%r10d\nlea 0x1(%r13),%r14d\ncmp %r10d,%r13d\ncmovge %r14d,%r10d\nmov %r10d,(%r12)\nadd %ecx,%r8d\ncmp %r8d,%edi\njl 124b \nmov (%r9,%rax,4),%r12d\nmovslq %r8d,%r8\nlea (%r9,%r8,4),%r10\nmov (%r10),%r8d\nlea 0x1(%r12),%r13d\ncmp %r8d,%r12d\ncmovge %r13d,%r8d\nmov %r8d,(%r10)\njmpq 124b \nmovslq %edi,%rdi\nmov (%r11,%rdi,4),%eax\nmov -0x28(%rbp),%rdx\nxor %fs:0x28,%rdx\njne 12ff \nlea -0x20(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %rbp\nretq\ncallq 1080 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r13\npush r12\npush rbx\nsub rsp, 18h\nmov r11d, esi\nmov r10d, ecx\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nlea eax, [rdi+0Ah]\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rsi, rax\nand rsi, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rcx, rsp\nsub rcx, rax\nloc_11CF:\ncmp rsp, rcx\njz short loc_11E6\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\njmp short loc_11CF\nloc_11E6:\nmov rax, rsi\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11FC\nor [rsp+rax+30h+var_38], 0\nloc_11FC:\nlea r9, [rsp+30h+var_2D]\nmov rcx, r9\nshr rcx, 2\nand r9, 0FFFFFFFFFFFFFFFCh\ncmp edi, 0FFFFFFF7h\njl loc_12D0\nmov rsi, r9\nlea eax, [rdi+0Ah]\nlea r8, [r9+rax*4]\nmov rax, r9\nloc_1222:\nmov dword ptr [rax], 0FFFFFFFFh\nadd rax, 4\ncmp rax, r8\njnz short loc_1222\nmov ds:dword_0[rcx*4], 0\ntest edi, edi\njs loc_12DB\nmov eax, r10d\nmov ecx, edx\nmov edx, r11d\nlea ebx, [rdi+r10+1]\njmp short loc_1264\nloc_1253:\nadd rsi, 4\nadd eax, 1\nadd ecx, 1\nadd edx, 1\ncmp eax, ebx\njz short loc_12DB\nloc_1264:\nmov r10, rsi\nmov r8d, [rsi]\ncmp r8d, 0FFFFFFFFh\njz short loc_1253\ncmp edx, edi\njg short loc_128D\nmovsxd r12, edx\nmov r12d, [r9+r12*4]\nlea r13d, [r8+1]\ncmp r8d, r12d\ncmovge r12d, r13d\nmovsxd r11, edx\nmov [r9+r11*4], r12d\nloc_128D:\ncmp ecx, edi\njg short loc_12AE\nmov r12d, [r10]\nmovsxd r11, ecx\nmov r11d, [r9+r11*4]\nlea r13d, [r12+1]\ncmp r12d, r11d\ncmovge r11d, r13d\nmovsxd r8, ecx\nmov [r9+r8*4], r11d\nloc_12AE:\ncmp eax, edi\njg short loc_1253\nmov r11d, [r10]\nmovsxd r10, eax\nmov r10d, [r9+r10*4]\nlea r12d, [r11+1]\ncmp r11d, r10d\ncmovge r10d, r12d\nmovsxd r8, eax\nmov [r9+r8*4], r10d\njmp short loc_1253\nloc_12D0:\nmov ds:dword_0[rcx*4], 0\nloc_12DB:\nmovsxd rdi, edi\nmov eax, [r9+rdi*4]\nmov rdx, [rbp+var_28]\nsub rdx, fs:28h\njnz short loc_12FC\nlea rsp, [rbp-18h]\npop rbx\npop r12\npop r13\npop rbp\nretn\nloc_12FC:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, int a3, int a4)\n{\n signed __int64 v6; // rax\n void *v7; // rsp\n int *v8; // rsi\n _DWORD *v9; // rax\n int v10; // eax\n int v12; // edx\n int v13; // ebx\n int v14; // r8d\n int v15; // r12d\n int v16; // r11d\n int v17; // r10d\n _DWORD v20[2]; // [rsp+8h] [rbp-30h] BYREF\n unsigned __int64 v21; // [rsp+10h] [rbp-28h]\n\n v21 = __readfsqword(0x28u);\n while ( v20 != (_DWORD *)((char *)v20 - ((4LL * (a1 + 10) + 15) & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v6 = (4 * ((_WORD)a1 + 10) + 15) & 0xFF0;\n v7 = alloca(v6);\n if ( ((4 * ((_WORD)a1 + 10) + 15) & 0xFF0) != 0 )\n *(_QWORD *)((char *)&v20[-2] + v6) = *(_QWORD *)((char *)&v20[-2] + v6);\n if ( a1 < -9 )\n {\n v20[0] = 0;\n }\n else\n {\n v8 = v20;\n v9 = v20;\n do\n *v9++ = -1;\n while ( v9 != &v20[a1 + 10] );\n v20[0] = 0;\n if ( a1 >= 0 )\n {\n v10 = a4;\n v12 = a2;\n v13 = a1 + a4 + 1;\n do\n {\n v14 = *v8;\n if ( *v8 != -1 )\n {\n if ( v12 <= a1 )\n {\n v15 = v20[v12];\n if ( v14 >= v15 )\n v15 = v14 + 1;\n v20[v12] = v15;\n }\n if ( a3 <= a1 )\n {\n v16 = v20[a3];\n if ( *v8 >= v16 )\n v16 = *v8 + 1;\n v20[a3] = v16;\n }\n if ( v10 <= a1 )\n {\n v17 = v20[v10];\n if ( *v8 >= v17 )\n v17 = *v8 + 1;\n v20[v10] = v17;\n }\n }\n ++v8;\n ++v10;\n ++a3;\n ++v12;\n }\n while ( v10 != v13 );\n }\n }\n return (unsigned int)v20[a1];\n}", + "ida_strip_asm": "sub_1189:\nendbr64\npush rbp\nmov rbp, rsp\npush r13\npush r12\npush rbx\nsub rsp, 18h\nmov r11d, esi\nmov r10d, ecx\nmov rax, fs:28h\nmov [rbp+var_28], rax\nxor eax, eax\nlea eax, [rdi+0Ah]\ncdqe\nlea rax, ds:0Fh[rax*4]\nmov rsi, rax\nand rsi, 0FFFFFFFFFFFFFFF0h\nand rax, 0FFFFFFFFFFFFF000h\nmov rcx, rsp\nsub rcx, rax\nloc_11CF:\ncmp rsp, rcx\njz short loc_11E6\nsub rsp, 1000h\nor [rsp+1030h+var_38], 0\njmp short loc_11CF\nloc_11E6:\nmov rax, rsi\nand eax, 0FFFh\nsub rsp, rax\ntest rax, rax\njz short loc_11FC\nor [rsp+rax+30h+var_38], 0\nloc_11FC:\nlea r9, [rsp+30h+var_2D]\nmov rcx, r9\nshr rcx, 2\nand r9, 0FFFFFFFFFFFFFFFCh\ncmp edi, 0FFFFFFF7h\njl loc_12D0\nmov rsi, r9\nlea eax, [rdi+0Ah]\nlea r8, [r9+rax*4]\nmov rax, r9\nloc_1222:\nmov dword ptr [rax], 0FFFFFFFFh\nadd rax, 4\ncmp rax, r8\njnz short loc_1222\nmov ds:dword_0[rcx*4], 0\ntest edi, edi\njs loc_12DB\nmov eax, r10d\nmov ecx, edx\nmov edx, r11d\nlea ebx, [rdi+r10+1]\njmp short loc_1264\nloc_1253:\nadd rsi, 4\nadd eax, 1\nadd ecx, 1\nadd edx, 1\ncmp eax, ebx\njz short loc_12DB\nloc_1264:\nmov r10, rsi\nmov r8d, [rsi]\ncmp r8d, 0FFFFFFFFh\njz short loc_1253\ncmp edx, edi\njg short loc_128D\nmovsxd r12, edx\nmov r12d, [r9+r12*4]\nlea r13d, [r8+1]\ncmp r8d, r12d\ncmovge r12d, r13d\nmovsxd r11, edx\nmov [r9+r11*4], r12d\nloc_128D:\ncmp ecx, edi\njg short loc_12AE\nmov r12d, [r10]\nmovsxd r11, ecx\nmov r11d, [r9+r11*4]\nlea r13d, [r12+1]\ncmp r12d, r11d\ncmovge r11d, r13d\nmovsxd r8, ecx\nmov [r9+r8*4], r11d\nloc_12AE:\ncmp eax, edi\njg short loc_1253\nmov r11d, [r10]\nmovsxd r10, eax\nmov r10d, [r9+r10*4]\nlea r12d, [r11+1]\ncmp r11d, r10d\ncmovge r10d, r12d\nmovsxd r8, eax\nmov [r9+r8*4], r10d\njmp short loc_1253\nloc_12D0:\nmov ds:dword_0[rcx*4], 0\nloc_12DB:\nmovsxd rdi, edi\nmov eax, [r9+rdi*4]\nmov rdx, [rbp+var_28]\nsub rdx, fs:28h\njnz short loc_12FC\nlea rsp, [rbp-18h]\npop rbx\npop r12\npop r13\npop rbp\nretn\nloc_12FC:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1189(int a1, int a2, int a3, int a4)\n{\n signed __int64 v6; // rax\n void *v7; // rsp\n int *v8; // rsi\n _DWORD *v9; // rax\n int v10; // eax\n int v12; // edx\n int v13; // ebx\n int v14; // r8d\n int v15; // r12d\n int v16; // r11d\n int v17; // r10d\n _DWORD v20[2]; // [rsp+8h] [rbp-30h] BYREF\n unsigned __int64 v21; // [rsp+10h] [rbp-28h]\n\n v21 = __readfsqword(0x28u);\n while ( v20 != (_DWORD *)((char *)v20 - ((4LL * (a1 + 10) + 15) & 0xFFFFFFFFFFFFF000LL)) )\n ;\n v6 = (4 * ((_WORD)a1 + 10) + 15) & 0xFF0;\n v7 = alloca(v6);\n if ( ((4 * ((_WORD)a1 + 10) + 15) & 0xFF0) != 0 )\n *(_QWORD *)((char *)&v20[-2] + v6) = *(_QWORD *)((char *)&v20[-2] + v6);\n if ( a1 < -9 )\n {\n v20[0] = 0;\n }\n else\n {\n v8 = v20;\n v9 = v20;\n do\n *v9++ = -1;\n while ( v9 != &v20[a1 + 10] );\n v20[0] = 0;\n if ( a1 >= 0 )\n {\n v10 = a4;\n v12 = a2;\n v13 = a1 + a4 + 1;\n do\n {\n v14 = *v8;\n if ( *v8 != -1 )\n {\n if ( v12 <= a1 )\n {\n v15 = v20[v12];\n if ( v14 >= v15 )\n v15 = v14 + 1;\n v20[v12] = v15;\n }\n if ( a3 <= a1 )\n {\n v16 = v20[a3];\n if ( *v8 >= v16 )\n v16 = *v8 + 1;\n v20[a3] = v16;\n }\n if ( v10 <= a1 )\n {\n v17 = v20[v10];\n if ( *v8 >= v17 )\n v17 = *v8 + 1;\n v20[v10] = v17;\n }\n }\n ++v8;\n ++v10;\n ++a3;\n ++v12;\n }\n while ( v10 != v13 );\n }\n }\n return (unsigned int)v20[a1];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1189(int a1, int a2, int a3, int a4) {\n signed long long v6;\n void *v7;\n int *v8;\n uint32_t *v9;\n int v10;\n int v12;\n int v13;\n int v14;\n int v15;\n int v16;\n int v17;\n uint32_t v20[2];\n unsigned long long v21;\n v21 = __readfsqword(40u);\n while (v20 != (uint32_t *)((char *)v20 -\n ((4LL * (a1 + 10) + 15) & 18446744073709547520LL)))\n ;\n v6 = (4 * ((unsigned short)a1 + 10) + 15) & 4080;\n v7 = alloca(v6);\n if (((4 * ((unsigned short)a1 + 10) + 15) & 4080) != 0)\n *(uint64_t *)((char *)&v20[-2] + v6) = *(uint64_t *)((char *)&v20[-2] + v6);\n if (a1 < -9) {\n v20[0] = 0;\n } else {\n v8 = v20;\n v9 = v20;\n do\n *v9++ = -1;\n while (v9 != &v20[a1 + 10]);\n v20[0] = 0;\n if (a1 >= 0) {\n v10 = a4;\n v12 = a2;\n v13 = a1 + a4 + 1;\n do {\n v14 = *v8;\n if (*v8 != -1) {\n if (v12 <= a1) {\n v15 = v20[v12];\n if (v14 >= v15) v15 = v14 + 1;\n v20[v12] = v15;\n }\n if (a3 <= a1) {\n v16 = v20[a3];\n if (*v8 >= v16) v16 = *v8 + 1;\n v20[a3] = v16;\n }\n if (v10 <= a1) {\n v17 = v20[v10];\n if (*v8 >= v17) v17 = *v8 + 1;\n v20[v10] = v17;\n }\n }\n ++v8;\n ++v10;\n ++a3;\n ++v12;\n } while (v10 != v13);\n }\n }\n return (unsigned int)v20[a1];\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, int a3, int a4) {\n signed long long v6;\n void *v7;\n int *v8;\n uint32_t *v9;\n int v10;\n int v12;\n int v13;\n int v14;\n int v15;\n int v16;\n int v17;\n uint32_t v20[2];\n unsigned long long v21;\n v21 = __readfsqword(40u);\n while (v20 != (uint32_t *)((char *)v20 -\n ((4LL * (a1 + 10) + 15) & 18446744073709547520LL)))\n ;\n v6 = (4 * ((unsigned short)a1 + 10) + 15) & 4080;\n v7 = alloca(v6);\n if (((4 * ((unsigned short)a1 + 10) + 15) & 4080) != 0)\n *(uint64_t *)((char *)&v20[-2] + v6) = *(uint64_t *)((char *)&v20[-2] + v6);\n if (a1 < -9) {\n v20[0] = 0;\n } else {\n v8 = v20;\n v9 = v20;\n do\n *v9++ = -1;\n while (v9 != &v20[a1 + 10]);\n v20[0] = 0;\n if (a1 >= 0) {\n v10 = a4;\n v12 = a2;\n v13 = a1 + a4 + 1;\n do {\n v14 = *v8;\n if (*v8 != -1) {\n if (v12 <= a1) {\n v15 = v20[v12];\n if (v14 >= v15) v15 = v14 + 1;\n v20[v12] = v15;\n }\n if (a3 <= a1) {\n v16 = v20[a3];\n if (*v8 >= v16) v16 = *v8 + 1;\n v20[a3] = v16;\n }\n if (v10 <= a1) {\n v17 = v20[v10];\n if (*v8 >= v17) v17 = *v8 + 1;\n v20[v10] = v17;\n }\n }\n ++v8;\n ++v10;\n ++a3;\n ++v12;\n } while (v10 != v13);\n }\n }\n return (unsigned int)v20[a1];\n}" + }, + { + "index": 971, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(int n, int a, int b, int c) {\n int dp[n + 10];\n for (int i = 0; i < n + 10; i++) {\n dp[i] = -1;\n }\n dp[0] = 0;\n for (int i = 0; i <= n; i++) {\n if (dp[i] != -1) {\n if (i + a <= n) {\n dp[i + a] = (dp[i] + 1 > dp[i + a]) ? dp[i] + 1 : dp[i + a];\n }\n if (i + b <= n) {\n dp[i + b] = (dp[i] + 1 > dp[i + b]) ? dp[i] + 1 : dp[i + b];\n }\n if (i + c <= n) {\n dp[i + c] = (dp[i] + 1 > dp[i + c]) ? dp[i] + 1 : dp[i + c];\n }\n }\n }\n return dp[n];\n}", + "test": "int main() {\n\n assert(func0(7, 5, 2, 5) == 2);\n\n assert(func0(17, 2, 1, 3) == 17);\n\n assert(func0(18, 16, 3, 6) == 6);\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r13\npush %r12\npush %rbx\nsub $0x18,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x28(%rbp)\nxor %eax,%eax\nlea 0xa(%rdi),%eax\nmov %rsp,%rbx\ncltq\nlea 0xf(,%rax,4),%rax\nmov %rax,%r8\nand $0xfffffffffffff000,%rax\nsub %rax,%rbx\nand $0xfffffffffffffff0,%r8\nmov %rbx,%rax\ncmp %rax,%rsp\nje 12cd \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 12b8 \nand $0xfff,%r8d\nsub %r8,%rsp\ntest %r8,%r8\njne 13e0 \nlea 0x3(%rsp),%r9\nmov %r9,%r10\nand $0xfffffffffffffffc,%r9\nshr $0x2,%r10\ncmp $0xfffffff7,%edi\njl 1317 \nlea 0x9(%rdi),%r8d\nmov %r9,%rax\nlea 0x4(%r9,%r8,4),%r8\nnopl 0x0(%rax)\nmovl $0xffffffff,(%rax)\nadd $0x4,%rax\ncmp %r8,%rax\njne 1308 \nmovl $0x0,0x0(,%r10,4)\nmovslq %edi,%r11\nxor %eax,%eax\nxor %r10d,%r10d\ntest %edi,%edi\njns 133f \njmpq 13c0 \nnopl 0x0(%rax)\nmov (%r9,%r8,4),%r10d\nmov %r8,%rax\ncmp $0xffffffff,%r10d\nje 13b3 \nlea (%rsi,%rax,1),%ebx\nmov %eax,%r8d\ncmp %ebx,%edi\njl 1369 \nmovslq %ebx,%rbx\nlea 0x1(%r10),%r13d\nlea (%r9,%rbx,4),%r12\nmov (%r12),%ebx\ncmp %ebx,%r10d\ncmovge %r13d,%ebx\nmov %ebx,(%r12)\nlea (%rdx,%r8,1),%r10d\ncmp %r10d,%edi\njl 138f \nmovslq %r10d,%r10\nmov (%r9,%rax,4),%r12d\nlea (%r9,%r10,4),%rbx\nmov (%rbx),%r10d\nlea 0x1(%r12),%r13d\ncmp %r10d,%r12d\ncmovge %r13d,%r10d\nmov %r10d,(%rbx)\nadd %ecx,%r8d\ncmp %r8d,%edi\njl 13b3 \nmovslq %r8d,%r8\nmov (%r9,%rax,4),%ebx\nlea (%r9,%r8,4),%r10\nmov (%r10),%r8d\nlea 0x1(%rbx),%r12d\ncmp %r8d,%ebx\ncmovge %r12d,%r8d\nmov %r8d,(%r10)\nlea 0x1(%rax),%r8\ncmp %rax,%r11\njne 1338 \nmov -0x28(%rbp),%rdx\nxor %fs:0x28,%rdx\nmov (%r9,%r11,4),%eax\njne 13eb \nlea -0x18(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %rbp\nretq\nxchg %ax,%ax\norq $0x0,-0x8(%rsp,%r8,1)\njmpq 12e0 \ncallq 1080 <__stack_chk_fail@plt>\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\nmovsxd r14, edi\npush r13\nmov r13d, edx\nlea edx, [r14+0Ah]\npush r12\nmov r12d, esi\npush rbx\nmov ebx, ecx\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nmovsxd rax, edx\nmov rsi, rsp\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rsi, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rsi\njz short loc_12FB\nloc_12E6:\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\ncmp rsp, rsi\njnz short loc_12E6\nloc_12FB:\nand ecx, 0FFFh\nsub rsp, rcx\ntest rcx, rcx\njnz loc_13F0\nloc_130D:\nlea rcx, [rsp+1040h+var_103D]\nmov r15, rcx\nand rcx, 0FFFFFFFFFFFFFFFCh\nshr r15, 2\ncmp r14d, 0FFFFFFF7h\njl loc_13FB\nmov edx, edx\nmov rdi, rcx; s\nmov esi, 0FFh; c\nshl rdx, 2; n\ncall _memset\nlea r8d, [rbx+r14+1]\nmov ds:dword_0[r15*4], 0\nmov rcx, rax\nmov rdx, rax\nmov eax, ebx\ntest r14d, r14d\njs short loc_13CD\nnop dword ptr [rax+rax+00000000h]\nloc_1360:\nmov esi, [rdx]\ncmp esi, 0FFFFFFFFh\njz short loc_13B9\ncmp r12d, r14d\njg short loc_1381\nmovsxd r9, r12d\nlea r10d, [rsi+1]\nmov edi, [rcx+r9*4]\ncmp esi, edi\ncmovge edi, r10d\nmov [rcx+r9*4], edi\nloc_1381:\ncmp r13d, r14d\njg short loc_139D\nmovsxd rdi, r13d\nmov r9d, [rdx]\nmov esi, [rcx+rdi*4]\nlea r10d, [r9+1]\ncmp r9d, esi\ncmovge esi, r10d\nmov [rcx+rdi*4], esi\nloc_139D:\ncmp eax, r14d\njg short loc_13B9\nmovsxd rdi, eax\nmov r9d, [rdx]\nmov esi, [rcx+rdi*4]\nlea r10d, [r9+1]\ncmp r9d, esi\ncmovge esi, r10d\nmov [rcx+rdi*4], esi\nloc_13B9:\nadd eax, 1\nadd rdx, 4\nadd r13d, 1\nadd r12d, 1\ncmp r8d, eax\njnz short loc_1360\nloc_13CD:\nmov eax, [rcx+r14*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_1409\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_13F0:\nor [rsp+rcx+1040h+var_1048], 0\njmp loc_130D\nloc_13FB:\nmov ds:dword_0[r15*4], 0\njmp short loc_13CD\nloc_1409:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, int a3, int a4)\n{\n __int64 v4; // r14\n __int64 v8; // rcx\n _DWORD *v9; // rsi\n __int16 v10; // cx\n signed __int64 v11; // rcx\n void *v12; // rsp\n _DWORD *v13; // rcx\n _DWORD *v14; // rax\n int *v15; // rdx\n int v16; // eax\n int v17; // esi\n int v18; // edi\n int v19; // esi\n int v20; // esi\n _DWORD v23[1022]; // [rsp+8h] [rbp-1040h] BYREF\n _QWORD v24[8]; // [rsp+1008h] [rbp-40h] BYREF\n\n v4 = a1;\n v24[1] = __readfsqword(0x28u);\n v8 = 4LL * (a1 + 10) + 15;\n v9 = (_DWORD *)((char *)v24 - (v8 & 0xFFFFFFFFFFFFF000LL));\n v10 = v8 & 0xFFF0;\n if ( v24 != (_QWORD *)v9 )\n {\n while ( v23 != v9 )\n ;\n }\n v11 = v10 & 0xFFF;\n v12 = alloca(v11);\n if ( v11 )\n *(_QWORD *)((char *)&v23[-2] + v11) = *(_QWORD *)((char *)&v23[-2] + v11);\n v13 = v23;\n if ( a1 < -9 )\n {\n v23[0] = 0;\n }\n else\n {\n v14 = memset(v23, 255, 4LL * (unsigned int)(a1 + 10));\n v23[0] = 0;\n v13 = v14;\n v15 = v14;\n v16 = a4;\n if ( a1 >= 0 )\n {\n do\n {\n v17 = *v15;\n if ( *v15 != -1 )\n {\n if ( a2 <= (int)v4 )\n {\n v18 = v13[a2];\n if ( v17 >= v18 )\n v18 = v17 + 1;\n v13[a2] = v18;\n }\n if ( a3 <= (int)v4 )\n {\n v19 = v13[a3];\n if ( *v15 >= v19 )\n v19 = *v15 + 1;\n v13[a3] = v19;\n }\n if ( v16 <= (int)v4 )\n {\n v20 = v13[v16];\n if ( *v15 >= v20 )\n v20 = *v15 + 1;\n v13[v16] = v20;\n }\n }\n ++v16;\n ++v15;\n ++a3;\n ++a2;\n }\n while ( a4 + (_DWORD)v4 + 1 != v16 );\n }\n }\n return (unsigned int)v13[v4];\n}", + "ida_strip_asm": "sub_1290:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\nmovsxd r14, edi\npush r13\nmov r13d, edx\nlea edx, [r14+0Ah]\npush r12\nmov r12d, esi\npush rbx\nmov ebx, ecx\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nmovsxd rax, edx\nmov rsi, rsp\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rsi, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rsi\njz short loc_12FB\nloc_12E6:\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\ncmp rsp, rsi\njnz short loc_12E6\nloc_12FB:\nand ecx, 0FFFh\nsub rsp, rcx\ntest rcx, rcx\njnz loc_13F0\nloc_130D:\nlea rcx, [rsp+1040h+var_103D]\nmov r15, rcx\nand rcx, 0FFFFFFFFFFFFFFFCh\nshr r15, 2\ncmp r14d, 0FFFFFFF7h\njl loc_13FB\nmov edx, edx\nmov rdi, rcx; s\nmov esi, 0FFh; c\nshl rdx, 2; n\ncall _memset\nlea r8d, [rbx+r14+1]\nmov ds:dword_0[r15*4], 0\nmov rcx, rax\nmov rdx, rax\nmov eax, ebx\ntest r14d, r14d\njs short loc_13CD\nnop dword ptr [rax+rax+00000000h]\nloc_1360:\nmov esi, [rdx]\ncmp esi, 0FFFFFFFFh\njz short loc_13B9\ncmp r12d, r14d\njg short loc_1381\nmovsxd r9, r12d\nlea r10d, [rsi+1]\nmov edi, [rcx+r9*4]\ncmp esi, edi\ncmovge edi, r10d\nmov [rcx+r9*4], edi\nloc_1381:\ncmp r13d, r14d\njg short loc_139D\nmovsxd rdi, r13d\nmov r9d, [rdx]\nmov esi, [rcx+rdi*4]\nlea r10d, [r9+1]\ncmp r9d, esi\ncmovge esi, r10d\nmov [rcx+rdi*4], esi\nloc_139D:\ncmp eax, r14d\njg short loc_13B9\nmovsxd rdi, eax\nmov r9d, [rdx]\nmov esi, [rcx+rdi*4]\nlea r10d, [r9+1]\ncmp r9d, esi\ncmovge esi, r10d\nmov [rcx+rdi*4], esi\nloc_13B9:\nadd eax, 1\nadd rdx, 4\nadd r13d, 1\nadd r12d, 1\ncmp r8d, eax\njnz short loc_1360\nloc_13CD:\nmov eax, [rcx+r14*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_1409\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_13F0:\nor [rsp+rcx+1040h+var_1048], 0\njmp loc_130D\nloc_13FB:\nmov ds:dword_0[r15*4], 0\njmp short loc_13CD\nloc_1409:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1290(int a1, int a2, int a3, int a4)\n{\n __int64 v4; // r14\n __int64 v8; // rcx\n _DWORD *v9; // rsi\n __int16 v10; // cx\n signed __int64 v11; // rcx\n void *v12; // rsp\n _DWORD *v13; // rcx\n _DWORD *v14; // rax\n int *v15; // rdx\n int v16; // eax\n int v17; // esi\n int v18; // edi\n int v19; // esi\n int v20; // esi\n _DWORD v23[1022]; // [rsp+8h] [rbp-1040h] BYREF\n _QWORD v24[8]; // [rsp+1008h] [rbp-40h] BYREF\n\n v4 = a1;\n v24[1] = __readfsqword(0x28u);\n v8 = 4LL * (a1 + 10) + 15;\n v9 = (_DWORD *)((char *)v24 - (v8 & 0xFFFFFFFFFFFFF000LL));\n v10 = v8 & 0xFFF0;\n if ( v24 != (_QWORD *)v9 )\n {\n while ( v23 != v9 )\n ;\n }\n v11 = v10 & 0xFFF;\n v12 = alloca(v11);\n if ( v11 )\n *(_QWORD *)((char *)&v23[-2] + v11) = *(_QWORD *)((char *)&v23[-2] + v11);\n v13 = v23;\n if ( a1 < -9 )\n {\n v23[0] = 0;\n }\n else\n {\n v14 = memset(v23, 255, 4LL * (unsigned int)(a1 + 10));\n v23[0] = 0;\n v13 = v14;\n v15 = v14;\n v16 = a4;\n if ( a1 >= 0 )\n {\n do\n {\n v17 = *v15;\n if ( *v15 != -1 )\n {\n if ( a2 <= (int)v4 )\n {\n v18 = v13[a2];\n if ( v17 >= v18 )\n v18 = v17 + 1;\n v13[a2] = v18;\n }\n if ( a3 <= (int)v4 )\n {\n v19 = v13[a3];\n if ( *v15 >= v19 )\n v19 = *v15 + 1;\n v13[a3] = v19;\n }\n if ( v16 <= (int)v4 )\n {\n v20 = v13[v16];\n if ( *v15 >= v20 )\n v20 = *v15 + 1;\n v13[v16] = v20;\n }\n }\n ++v16;\n ++v15;\n ++a3;\n ++a2;\n }\n while ( a4 + (_DWORD)v4 + 1 != v16 );\n }\n }\n return (unsigned int)v13[v4];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1290(int a1, int a2, int a3, int a4) {\n long long v4;\n long long v8;\n uint32_t *v9;\n short v10;\n signed long long v11;\n void *v12;\n uint32_t *v13;\n uint32_t *v14;\n int *v15;\n int v16;\n int v17;\n int v18;\n int v19;\n int v20;\n uint32_t v23[1022];\n uint64_t v24[8];\n v4 = a1;\n v24[1] = __readfsqword(40u);\n v8 = 4LL * (a1 + 10) + 15;\n v9 = (uint32_t *)((char *)v24 - (v8 & 18446744073709547520LL));\n v10 = v8 & 65520;\n if (v24 != (uint64_t *)v9) {\n while (v23 != v9)\n ;\n }\n v11 = v10 & 4095;\n v12 = alloca(v11);\n if (v11)\n *(uint64_t *)((char *)&v23[-2] + v11) =\n *(uint64_t *)((char *)&v23[-2] + v11);\n v13 = v23;\n if (a1 < -9) {\n v23[0] = 0;\n } else {\n v14 = memset(v23, 255, 4LL * (unsigned int)(a1 + 10));\n v23[0] = 0;\n v13 = v14;\n v15 = v14;\n v16 = a4;\n if (a1 >= 0) {\n do {\n v17 = *v15;\n if (*v15 != -1) {\n if (a2 <= (int)v4) {\n v18 = v13[a2];\n if (v17 >= v18) v18 = v17 + 1;\n v13[a2] = v18;\n }\n if (a3 <= (int)v4) {\n v19 = v13[a3];\n if (*v15 >= v19) v19 = *v15 + 1;\n v13[a3] = v19;\n }\n if (v16 <= (int)v4) {\n v20 = v13[v16];\n if (*v15 >= v20) v20 = *v15 + 1;\n v13[v16] = v20;\n }\n }\n ++v16;\n ++v15;\n ++a3;\n ++a2;\n } while (a4 + (uint32_t)v4 + 1 != v16);\n }\n }\n return (unsigned int)v13[v4];\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, int a3, int a4) {\n long long v4;\n long long v8;\n uint32_t *v9;\n short v10;\n signed long long v11;\n void *v12;\n uint32_t *v13;\n uint32_t *v14;\n int *v15;\n int v16;\n int v17;\n int v18;\n int v19;\n int v20;\n uint32_t v23[1022];\n uint64_t v24[8];\n v4 = a1;\n v24[1] = __readfsqword(40u);\n v8 = 4LL * (a1 + 10) + 15;\n v9 = (uint32_t *)((char *)v24 - (v8 & 18446744073709547520LL));\n v10 = v8 & 65520;\n if (v24 != (uint64_t *)v9) {\n while (v23 != v9)\n ;\n }\n v11 = v10 & 4095;\n v12 = alloca(v11);\n if (v11)\n *(uint64_t *)((char *)&v23[-2] + v11) =\n *(uint64_t *)((char *)&v23[-2] + v11);\n v13 = v23;\n if (a1 < -9) {\n v23[0] = 0;\n } else {\n v14 = memset(v23, 255, 4LL * (unsigned int)(a1 + 10));\n v23[0] = 0;\n v13 = v14;\n v15 = v14;\n v16 = a4;\n if (a1 >= 0) {\n do {\n v17 = *v15;\n if (*v15 != -1) {\n if (a2 <= (int)v4) {\n v18 = v13[a2];\n if (v17 >= v18) v18 = v17 + 1;\n v13[a2] = v18;\n }\n if (a3 <= (int)v4) {\n v19 = v13[a3];\n if (*v15 >= v19) v19 = *v15 + 1;\n v13[a3] = v19;\n }\n if (v16 <= (int)v4) {\n v20 = v13[v16];\n if (*v15 >= v20) v20 = *v15 + 1;\n v13[v16] = v20;\n }\n }\n ++v16;\n ++v15;\n ++a3;\n ++a2;\n } while (a4 + (uint32_t)v4 + 1 != v16);\n }\n }\n return (unsigned int)v13[v4];\n}" + }, + { + "index": 971, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\n", + "func": "int func0(int n, int a, int b, int c) {\n int dp[n + 10];\n for (int i = 0; i < n + 10; i++) {\n dp[i] = -1;\n }\n dp[0] = 0;\n for (int i = 0; i <= n; i++) {\n if (dp[i] != -1) {\n if (i + a <= n) {\n dp[i + a] = (dp[i] + 1 > dp[i + a]) ? dp[i] + 1 : dp[i + a];\n }\n if (i + b <= n) {\n dp[i + b] = (dp[i] + 1 > dp[i + b]) ? dp[i] + 1 : dp[i + b];\n }\n if (i + c <= n) {\n dp[i + c] = (dp[i] + 1 > dp[i + c]) ? dp[i] + 1 : dp[i + c];\n }\n }\n }\n return dp[n];\n}", + "test": "int main() {\n\n assert(func0(7, 5, 2, 5) == 2);\n\n assert(func0(17, 2, 1, 3) == 17);\n\n assert(func0(18, 16, 3, 6) == 6);\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %r15\nmov %ecx,%r15d\npush %r14\npush %r13\nmov %edx,%r13d\npush %r12\nmov %esi,%r12d\npush %rbx\nmov %edi,%ebx\nsub $0x18,%rsp\nmov %fs:0x28,%rax\nmov %rax,-0x38(%rbp)\nxor %eax,%eax\nlea 0xa(%rdi),%eax\nmov %rsp,%rdi\ncltq\nlea 0xf(,%rax,4),%rax\nmov %rax,%rdx\nand $0xfffffffffffff000,%rax\nsub %rax,%rdi\nand $0xfffffffffffffff0,%rdx\nmov %rdi,%rax\ncmp %rax,%rsp\nje 12fc \nsub $0x1000,%rsp\norq $0x0,0xff8(%rsp)\ncmp %rax,%rsp\njne 12e7 \nand $0xfff,%edx\nsub %rdx,%rsp\ntest %rdx,%rdx\njne 13f8 \nlea 0x3(%rsp),%rdi\nmov %rdi,%r14\nand $0xfffffffffffffffc,%rdi\nshr $0x2,%r14\ncmp $0xfffffff7,%ebx\njl 133b \nlea 0x9(%rbx),%eax\nmov $0xff,%esi\nlea 0x4(,%rax,4),%rdx\ncallq 10b0 \nmov %rax,%rdi\nmovl $0x0,0x0(,%r14,4)\nmovslq %ebx,%r8\nxor %eax,%eax\ntest %ebx,%ebx\njns 135b \njmp 13cf \nnopw 0x0(%rax,%rax,1)\nmov %rdx,%rax\nmov (%rdi,%rax,4),%ecx\ncmp $0xffffffff,%ecx\nje 13c6 \nlea (%r12,%rax,1),%esi\nmov %eax,%edx\ncmp %esi,%ebx\njl 1384 \nmovslq %esi,%rsi\nlea 0x1(%rcx),%r10d\nlea (%rdi,%rsi,4),%r9\nmov (%r9),%esi\ncmp %esi,%ecx\ncmovge %r10d,%esi\nmov %esi,(%r9)\nlea 0x0(%r13,%rdx,1),%ecx\ncmp %ebx,%ecx\njg 13a7 \nmovslq %ecx,%rcx\nmov (%rdi,%rax,4),%r9d\nlea (%rdi,%rcx,4),%rsi\nmov (%rsi),%ecx\nlea 0x1(%r9),%r10d\ncmp %ecx,%r9d\ncmovge %r10d,%ecx\nmov %ecx,(%rsi)\nadd %r15d,%edx\ncmp %edx,%ebx\njl 13c6 \nmovslq %edx,%rdx\nmov (%rdi,%rax,4),%esi\nlea (%rdi,%rdx,4),%rcx\nmov (%rcx),%edx\nlea 0x1(%rsi),%r9d\ncmp %edx,%esi\ncmovge %r9d,%edx\nmov %edx,(%rcx)\nlea 0x1(%rax),%rdx\ncmp %rax,%r8\njne 1358 \nmov -0x38(%rbp),%rbx\nxor %fs:0x28,%rbx\nmov (%rdi,%r8,4),%eax\njne 1403 \nlea -0x28(%rbp),%rsp\npop %rbx\npop %r12\npop %r13\npop %r14\npop %r15\npop %rbp\nretq\nnopl 0x0(%rax)\norq $0x0,-0x8(%rsp,%rdx,1)\njmpq 130e \ncallq 1090 <__stack_chk_fail@plt>\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\nmovsxd r14, edi\npush r13\nmov r13d, edx\nlea edx, [r14+0Ah]\npush r12\nmov r12d, esi\npush rbx\nmov ebx, ecx\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nmovsxd rax, edx\nmov rsi, rsp\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rsi, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rsi\njz short loc_12FB\nloc_12E6:\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\ncmp rsp, rsi\njnz short loc_12E6\nloc_12FB:\nand ecx, 0FFFh\nsub rsp, rcx\ntest rcx, rcx\njnz loc_13F0\nloc_130D:\nlea rcx, [rsp+1040h+var_103D]\nmov r15, rcx\nand rcx, 0FFFFFFFFFFFFFFFCh\nshr r15, 2\ncmp r14d, 0FFFFFFF7h\njl loc_13FB\nmov edx, edx\nmov rdi, rcx; s\nmov esi, 0FFh; c\nshl rdx, 2; n\ncall _memset\nlea r8d, [rbx+r14+1]\nmov ds:dword_0[r15*4], 0\nmov rcx, rax\nmov rdx, rax\nmov eax, ebx\ntest r14d, r14d\njs short loc_13CD\nnop dword ptr [rax+rax+00000000h]\nloc_1360:\nmov esi, [rdx]\ncmp esi, 0FFFFFFFFh\njz short loc_13B9\ncmp r12d, r14d\njg short loc_1381\nmovsxd r9, r12d\nlea r10d, [rsi+1]\nmov edi, [rcx+r9*4]\ncmp esi, edi\ncmovge edi, r10d\nmov [rcx+r9*4], edi\nloc_1381:\ncmp r13d, r14d\njg short loc_139D\nmovsxd rdi, r13d\nmov r9d, [rdx]\nmov esi, [rcx+rdi*4]\nlea r10d, [r9+1]\ncmp r9d, esi\ncmovge esi, r10d\nmov [rcx+rdi*4], esi\nloc_139D:\ncmp eax, r14d\njg short loc_13B9\nmovsxd rdi, eax\nmov r9d, [rdx]\nmov esi, [rcx+rdi*4]\nlea r10d, [r9+1]\ncmp r9d, esi\ncmovge esi, r10d\nmov [rcx+rdi*4], esi\nloc_13B9:\nadd eax, 1\nadd rdx, 4\nadd r13d, 1\nadd r12d, 1\ncmp r8d, eax\njnz short loc_1360\nloc_13CD:\nmov eax, [rcx+r14*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_1409\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_13F0:\nor [rsp+rcx+1040h+var_1048], 0\njmp loc_130D\nloc_13FB:\nmov ds:dword_0[r15*4], 0\njmp short loc_13CD\nloc_1409:\ncall ___stack_chk_fail", + "ida_pseudo": "__int64 __fastcall func0(int a1, int a2, int a3, int a4)\n{\n __int64 v4; // r14\n __int64 v8; // rcx\n _DWORD *v9; // rsi\n __int16 v10; // cx\n signed __int64 v11; // rcx\n void *v12; // rsp\n _DWORD *v13; // rcx\n _DWORD *v14; // rax\n int *v15; // rdx\n int v16; // eax\n int v17; // esi\n int v18; // edi\n int v19; // esi\n int v20; // esi\n _DWORD v23[1022]; // [rsp+8h] [rbp-1040h] BYREF\n _QWORD v24[8]; // [rsp+1008h] [rbp-40h] BYREF\n\n v4 = a1;\n v24[1] = __readfsqword(0x28u);\n v8 = 4LL * (a1 + 10) + 15;\n v9 = (_DWORD *)((char *)v24 - (v8 & 0xFFFFFFFFFFFFF000LL));\n v10 = v8 & 0xFFF0;\n if ( v24 != (_QWORD *)v9 )\n {\n while ( v23 != v9 )\n ;\n }\n v11 = v10 & 0xFFF;\n v12 = alloca(v11);\n if ( v11 )\n *(_QWORD *)((char *)&v23[-2] + v11) = *(_QWORD *)((char *)&v23[-2] + v11);\n v13 = v23;\n if ( a1 < -9 )\n {\n v23[0] = 0;\n }\n else\n {\n v14 = memset(v23, 255, 4LL * (unsigned int)(a1 + 10));\n v23[0] = 0;\n v13 = v14;\n v15 = v14;\n v16 = a4;\n if ( a1 >= 0 )\n {\n do\n {\n v17 = *v15;\n if ( *v15 != -1 )\n {\n if ( a2 <= (int)v4 )\n {\n v18 = v13[a2];\n if ( v17 >= v18 )\n v18 = v17 + 1;\n v13[a2] = v18;\n }\n if ( a3 <= (int)v4 )\n {\n v19 = v13[a3];\n if ( *v15 >= v19 )\n v19 = *v15 + 1;\n v13[a3] = v19;\n }\n if ( v16 <= (int)v4 )\n {\n v20 = v13[v16];\n if ( *v15 >= v20 )\n v20 = *v15 + 1;\n v13[v16] = v20;\n }\n }\n ++v16;\n ++v15;\n ++a3;\n ++a2;\n }\n while ( a4 + (_DWORD)v4 + 1 != v16 );\n }\n }\n return (unsigned int)v13[v4];\n}", + "ida_strip_asm": "sub_1290:\nendbr64\npush rbp\nmov rbp, rsp\npush r15\npush r14\nmovsxd r14, edi\npush r13\nmov r13d, edx\nlea edx, [r14+0Ah]\npush r12\nmov r12d, esi\npush rbx\nmov ebx, ecx\nsub rsp, 18h\nmov rax, fs:28h\nmov [rbp+var_38], rax\nxor eax, eax\nmovsxd rax, edx\nmov rsi, rsp\nlea rax, ds:0Fh[rax*4]\nmov rcx, rax\nand rax, 0FFFFFFFFFFFFF000h\nsub rsi, rax\nand rcx, 0FFFFFFFFFFFFFFF0h\ncmp rsp, rsi\njz short loc_12FB\nloc_12E6:\nsub rsp, 1000h\nor [rsp+1040h+var_48], 0\ncmp rsp, rsi\njnz short loc_12E6\nloc_12FB:\nand ecx, 0FFFh\nsub rsp, rcx\ntest rcx, rcx\njnz loc_13F0\nloc_130D:\nlea rcx, [rsp+1040h+var_103D]\nmov r15, rcx\nand rcx, 0FFFFFFFFFFFFFFFCh\nshr r15, 2\ncmp r14d, 0FFFFFFF7h\njl loc_13FB\nmov edx, edx\nmov rdi, rcx; s\nmov esi, 0FFh; c\nshl rdx, 2; n\ncall _memset\nlea r8d, [rbx+r14+1]\nmov ds:dword_0[r15*4], 0\nmov rcx, rax\nmov rdx, rax\nmov eax, ebx\ntest r14d, r14d\njs short loc_13CD\nnop dword ptr [rax+rax+00000000h]\nloc_1360:\nmov esi, [rdx]\ncmp esi, 0FFFFFFFFh\njz short loc_13B9\ncmp r12d, r14d\njg short loc_1381\nmovsxd r9, r12d\nlea r10d, [rsi+1]\nmov edi, [rcx+r9*4]\ncmp esi, edi\ncmovge edi, r10d\nmov [rcx+r9*4], edi\nloc_1381:\ncmp r13d, r14d\njg short loc_139D\nmovsxd rdi, r13d\nmov r9d, [rdx]\nmov esi, [rcx+rdi*4]\nlea r10d, [r9+1]\ncmp r9d, esi\ncmovge esi, r10d\nmov [rcx+rdi*4], esi\nloc_139D:\ncmp eax, r14d\njg short loc_13B9\nmovsxd rdi, eax\nmov r9d, [rdx]\nmov esi, [rcx+rdi*4]\nlea r10d, [r9+1]\ncmp r9d, esi\ncmovge esi, r10d\nmov [rcx+rdi*4], esi\nloc_13B9:\nadd eax, 1\nadd rdx, 4\nadd r13d, 1\nadd r12d, 1\ncmp r8d, eax\njnz short loc_1360\nloc_13CD:\nmov eax, [rcx+r14*4]\nmov rdx, [rbp+var_38]\nsub rdx, fs:28h\njnz short loc_1409\nlea rsp, [rbp-28h]\npop rbx\npop r12\npop r13\npop r14\npop r15\npop rbp\nretn\nloc_13F0:\nor [rsp+rcx+1040h+var_1048], 0\njmp loc_130D\nloc_13FB:\nmov ds:dword_0[r15*4], 0\njmp short loc_13CD\nloc_1409:\ncall ___stack_chk_fail", + "ida_strip_pseudo": "__int64 __fastcall sub_1290(int a1, int a2, int a3, int a4)\n{\n __int64 v4; // r14\n __int64 v8; // rcx\n _DWORD *v9; // rsi\n __int16 v10; // cx\n signed __int64 v11; // rcx\n void *v12; // rsp\n _DWORD *v13; // rcx\n _DWORD *v14; // rax\n int *v15; // rdx\n int v16; // eax\n int v17; // esi\n int v18; // edi\n int v19; // esi\n int v20; // esi\n _DWORD v23[1022]; // [rsp+8h] [rbp-1040h] BYREF\n _QWORD v24[8]; // [rsp+1008h] [rbp-40h] BYREF\n\n v4 = a1;\n v24[1] = __readfsqword(0x28u);\n v8 = 4LL * (a1 + 10) + 15;\n v9 = (_DWORD *)((char *)v24 - (v8 & 0xFFFFFFFFFFFFF000LL));\n v10 = v8 & 0xFFF0;\n if ( v24 != (_QWORD *)v9 )\n {\n while ( v23 != v9 )\n ;\n }\n v11 = v10 & 0xFFF;\n v12 = alloca(v11);\n if ( v11 )\n *(_QWORD *)((char *)&v23[-2] + v11) = *(_QWORD *)((char *)&v23[-2] + v11);\n v13 = v23;\n if ( a1 < -9 )\n {\n v23[0] = 0;\n }\n else\n {\n v14 = memset(v23, 255, 4LL * (unsigned int)(a1 + 10));\n v23[0] = 0;\n v13 = v14;\n v15 = v14;\n v16 = a4;\n if ( a1 >= 0 )\n {\n do\n {\n v17 = *v15;\n if ( *v15 != -1 )\n {\n if ( a2 <= (int)v4 )\n {\n v18 = v13[a2];\n if ( v17 >= v18 )\n v18 = v17 + 1;\n v13[a2] = v18;\n }\n if ( a3 <= (int)v4 )\n {\n v19 = v13[a3];\n if ( *v15 >= v19 )\n v19 = *v15 + 1;\n v13[a3] = v19;\n }\n if ( v16 <= (int)v4 )\n {\n v20 = v13[v16];\n if ( *v15 >= v20 )\n v20 = *v15 + 1;\n v13[v16] = v20;\n }\n }\n ++v16;\n ++v15;\n ++a3;\n ++a2;\n }\n while ( a4 + (_DWORD)v4 + 1 != v16 );\n }\n }\n return (unsigned int)v13[v4];\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1290(int a1, int a2, int a3, int a4) {\n long long v4;\n long long v8;\n uint32_t *v9;\n short v10;\n signed long long v11;\n void *v12;\n uint32_t *v13;\n uint32_t *v14;\n int *v15;\n int v16;\n int v17;\n int v18;\n int v19;\n int v20;\n uint32_t v23[1022];\n uint64_t v24[8];\n v4 = a1;\n v24[1] = __readfsqword(40u);\n v8 = 4LL * (a1 + 10) + 15;\n v9 = (uint32_t *)((char *)v24 - (v8 & 18446744073709547520LL));\n v10 = v8 & 65520;\n if (v24 != (uint64_t *)v9) {\n while (v23 != v9)\n ;\n }\n v11 = v10 & 4095;\n v12 = alloca(v11);\n if (v11)\n *(uint64_t *)((char *)&v23[-2] + v11) =\n *(uint64_t *)((char *)&v23[-2] + v11);\n v13 = v23;\n if (a1 < -9) {\n v23[0] = 0;\n } else {\n v14 = memset(v23, 255, 4LL * (unsigned int)(a1 + 10));\n v23[0] = 0;\n v13 = v14;\n v15 = v14;\n v16 = a4;\n if (a1 >= 0) {\n do {\n v17 = *v15;\n if (*v15 != -1) {\n if (a2 <= (int)v4) {\n v18 = v13[a2];\n if (v17 >= v18) v18 = v17 + 1;\n v13[a2] = v18;\n }\n if (a3 <= (int)v4) {\n v19 = v13[a3];\n if (*v15 >= v19) v19 = *v15 + 1;\n v13[a3] = v19;\n }\n if (v16 <= (int)v4) {\n v20 = v13[v16];\n if (*v15 >= v20) v20 = *v15 + 1;\n v13[v16] = v20;\n }\n }\n ++v16;\n ++v15;\n ++a3;\n ++a2;\n } while (a4 + (uint32_t)v4 + 1 != v16);\n }\n }\n return (unsigned int)v13[v4];\n}", + "ida_pseudo_norm": "long long func0(int a1, int a2, int a3, int a4) {\n long long v4;\n long long v8;\n uint32_t *v9;\n short v10;\n signed long long v11;\n void *v12;\n uint32_t *v13;\n uint32_t *v14;\n int *v15;\n int v16;\n int v17;\n int v18;\n int v19;\n int v20;\n uint32_t v23[1022];\n uint64_t v24[8];\n v4 = a1;\n v24[1] = __readfsqword(40u);\n v8 = 4LL * (a1 + 10) + 15;\n v9 = (uint32_t *)((char *)v24 - (v8 & 18446744073709547520LL));\n v10 = v8 & 65520;\n if (v24 != (uint64_t *)v9) {\n while (v23 != v9)\n ;\n }\n v11 = v10 & 4095;\n v12 = alloca(v11);\n if (v11)\n *(uint64_t *)((char *)&v23[-2] + v11) =\n *(uint64_t *)((char *)&v23[-2] + v11);\n v13 = v23;\n if (a1 < -9) {\n v23[0] = 0;\n } else {\n v14 = memset(v23, 255, 4LL * (unsigned int)(a1 + 10));\n v23[0] = 0;\n v13 = v14;\n v15 = v14;\n v16 = a4;\n if (a1 >= 0) {\n do {\n v17 = *v15;\n if (*v15 != -1) {\n if (a2 <= (int)v4) {\n v18 = v13[a2];\n if (v17 >= v18) v18 = v17 + 1;\n v13[a2] = v18;\n }\n if (a3 <= (int)v4) {\n v19 = v13[a3];\n if (*v15 >= v19) v19 = *v15 + 1;\n v13[a3] = v19;\n }\n if (v16 <= (int)v4) {\n v20 = v13[v16];\n if (*v15 >= v20) v20 = *v15 + 1;\n v13[v16] = v20;\n }\n }\n ++v16;\n ++v15;\n ++a3;\n ++a2;\n } while (a4 + (uint32_t)v4 + 1 != v16);\n }\n }\n return (unsigned int)v13[v4];\n}" + }, + { + "index": 972, + "func_name": "func0", + "func_dep": "#include \n\n#include \n\n\n\ntypedef struct {\n\n int a;\n\n int b;\n\n int c;\n\n int d;\n\n} Tuple;\n\n\n\n", + "func": "Tuple func0(Tuple test_tup1, Tuple test_tup2) {\n Tuple res;\n res.a = test_tup1.a;\n res.b = test_tup1.b;\n res = (Tuple){res.a, res.b, test_tup2.a, test_tup2.b};\n return res;\n}", + "test": "int main() {\n\n Tuple t1 = {3, 4};\n\n Tuple t2 = {5, 6};\n\n Tuple result = func0(t1, t2);\n\n assert(result.a == 3 && result.b == 4 && result.c == 5 && result.d == 6);\n\n \n\n Tuple t3 = {1, 2};\n\n Tuple t4 = {3, 4};\n\n result = func0(t3, t4);\n\n assert(result.a == 1 && result.b == 2 && result.c == 3 && result.d == 4);\n\n \n\n Tuple t5 = {4, 5};\n\n Tuple t6 = {6, 8};\n\n result = func0(t5, t6);\n\n assert(result.a == 4 && result.b == 5 && result.c == 6 && result.d == 8);\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n return 0;\n\n}\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\npush %rbx\nmov %rsi,%rax\nmov %rdi,%r8\nmov %r8,%rsi\nmov %r9,%rdi\nmov %rax,%rdi\nmov %rsi,-0x30(%rbp)\nmov %rdi,-0x28(%rbp)\nmov %rdx,-0x40(%rbp)\nmov %rcx,-0x38(%rbp)\nmov -0x30(%rbp),%eax\nmov %eax,-0x20(%rbp)\nmov -0x2c(%rbp),%eax\nmov %eax,-0x1c(%rbp)\nmov -0x20(%rbp),%esi\nmov -0x1c(%rbp),%ecx\nmov -0x40(%rbp),%edx\nmov -0x3c(%rbp),%eax\nmov %esi,-0x20(%rbp)\nmov %ecx,-0x1c(%rbp)\nmov %edx,-0x18(%rbp)\nmov %eax,-0x14(%rbp)\nmov -0x20(%rbp),%rax\nmov -0x18(%rbp),%rdx\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nmov rax, rdi\nmov r8, rsi\nmov rsi, rax\nmov rdi, rdx\nmov rdi, r8\nmov [rbp+var_30], rsi\nmov [rbp+var_28], rdi\nmov [rbp+var_40], rdx\nmov [rbp+var_38], rcx\nmov eax, dword ptr [rbp+var_30]\nmov dword ptr [rbp+var_20], eax\nmov eax, dword ptr [rbp+var_30+4]\nmov dword ptr [rbp+var_20+4], eax\nmov esi, dword ptr [rbp+var_20]\nmov ecx, dword ptr [rbp+var_20+4]\nmov edx, dword ptr [rbp+var_40]\nmov eax, dword ptr [rbp+var_40+4]\nmov dword ptr [rbp+var_20], esi\nmov dword ptr [rbp+var_20+4], ecx\nmov dword ptr [rbp+var_18], edx\nmov dword ptr [rbp+var_18+4], eax\nmov rax, [rbp+var_20]\nmov rdx, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1)\n{\n return a1;\n}", + "ida_strip_asm": "sub_1169:\nendbr64\npush rbp\nmov rbp, rsp\npush rbx\nmov rax, rdi\nmov r8, rsi\nmov rsi, rax\nmov rdi, rdx\nmov rdi, r8\nmov [rbp+var_30], rsi\nmov [rbp+var_28], rdi\nmov [rbp+var_40], rdx\nmov [rbp+var_38], rcx\nmov eax, dword ptr [rbp+var_30]\nmov dword ptr [rbp+var_20], eax\nmov eax, dword ptr [rbp+var_30+4]\nmov dword ptr [rbp+var_20+4], eax\nmov esi, dword ptr [rbp+var_20]\nmov ecx, dword ptr [rbp+var_20+4]\nmov edx, dword ptr [rbp+var_40]\nmov eax, dword ptr [rbp+var_40+4]\nmov dword ptr [rbp+var_20], esi\nmov dword ptr [rbp+var_20+4], ecx\nmov dword ptr [rbp+var_18], edx\nmov dword ptr [rbp+var_18+4], eax\nmov rax, [rbp+var_20]\nmov rdx, [rbp+var_18]\nmov rbx, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1169(__int64 a1)\n{\n return a1;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1169(long long a1) { return a1; }", + "ida_pseudo_norm": "long long func0(long long a1) { return a1; }" + }, + { + "index": 973, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* s, int d) {\n int len = strlen(s);\n char* tmp = (char*)malloc(len + 1);\n for (int i = 0; i < len; i++) {\n tmp[i] = s[(i + d) % len];\n }\n tmp[len] = '\\0';\n return tmp;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"python\", 2), \"thonpy\") == 0);\n\n assert(strcmp(func0(\"bigdata\", 3), \"databig\") == 0);\n\n assert(strcmp(func0(\"hadoop\", 1), \"adooph\") == 0);\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x20,%rsp\nmov %rdi,-0x18(%rbp)\nmov %esi,-0x1c(%rbp)\nmov -0x18(%rbp),%rax\nmov %rax,%rdi\ncallq 10a0 \nmov %eax,-0xc(%rbp)\nmov -0xc(%rbp),%eax\nadd $0x1,%eax\ncltq\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,-0x8(%rbp)\nmovl $0x0,-0x10(%rbp)\njmp 1236 \nmov -0x10(%rbp),%edx\nmov -0x1c(%rbp),%eax\nadd %edx,%eax\ncltd\nidivl -0xc(%rbp)\nmov %edx,%eax\nmovslq %eax,%rdx\nmov -0x18(%rbp),%rax\nadd %rdx,%rax\nmov -0x10(%rbp),%edx\nmovslq %edx,%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nmovzbl (%rax),%eax\nmov %al,(%rdx)\naddl $0x1,-0x10(%rbp)\nmov -0x10(%rbp),%eax\ncmp -0xc(%rbp),%eax\njl 1208 \nmov -0xc(%rbp),%eax\nmovslq %eax,%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmovb $0x0,(%rax)\nmov -0x8(%rbp),%rax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov [rbp+var_1C], esi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_C], eax\nmov eax, [rbp+var_C]\nadd eax, 1\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_10], 0\njmp short loc_1236\nloc_1208:\nmov edx, [rbp+var_10]\nmov eax, [rbp+var_1C]\nadd eax, edx\ncdq\nidiv [rbp+var_C]\nmov eax, edx\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmov edx, [rbp+var_10]\nmovsxd rcx, edx\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmovzx eax, byte ptr [rax]\nmov [rdx], al\nadd [rbp+var_10], 1\nloc_1236:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_C]\njl short loc_1208\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1, int a2)\n{\n int i; // [rsp+10h] [rbp-10h]\n int v4; // [rsp+14h] [rbp-Ch]\n _BYTE *v5; // [rsp+18h] [rbp-8h]\n\n v4 = strlen(a1);\n v5 = malloc(v4 + 1);\n for ( i = 0; i < v4; ++i )\n v5[i] = a1[(i + a2) % v4];\n v5[v4] = 0;\n return v5;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 20h\nmov [rbp+s], rdi\nmov [rbp+var_1C], esi\nmov rax, [rbp+s]\nmov rdi, rax; s\ncall _strlen\nmov [rbp+var_C], eax\nmov eax, [rbp+var_C]\nadd eax, 1\ncdqe\nmov rdi, rax; size\ncall _malloc\nmov [rbp+var_8], rax\nmov [rbp+var_10], 0\njmp short loc_1236\nloc_1208:\nmov edx, [rbp+var_10]\nmov eax, [rbp+var_1C]\nadd eax, edx\ncdq\nidiv [rbp+var_C]\nmov eax, edx\nmovsxd rdx, eax\nmov rax, [rbp+s]\nadd rax, rdx\nmov edx, [rbp+var_10]\nmovsxd rcx, edx\nmov rdx, [rbp+var_8]\nadd rdx, rcx\nmovzx eax, byte ptr [rax]\nmov [rdx], al\nadd [rbp+var_10], 1\nloc_1236:\nmov eax, [rbp+var_10]\ncmp eax, [rbp+var_C]\njl short loc_1208\nmov eax, [rbp+var_C]\nmovsxd rdx, eax\nmov rax, [rbp+var_8]\nadd rax, rdx\nmov byte ptr [rax], 0\nmov rax, [rbp+var_8]\nleave\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_11C9(const char *a1, int a2)\n{\n int i; // [rsp+10h] [rbp-10h]\n int v4; // [rsp+14h] [rbp-Ch]\n _BYTE *v5; // [rsp+18h] [rbp-8h]\n\n v4 = strlen(a1);\n v5 = malloc(v4 + 1);\n for ( i = 0; i < v4; ++i )\n v5[i] = a1[(i + a2) % v4];\n v5[v4] = 0;\n return v5;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_11C9(const char *a1, int a2) {\n int i;\n int v4;\n uint8_t *v5;\n v4 = strlen(a1);\n v5 = malloc(v4 + 1);\n for (i = 0; i < v4; ++i) v5[i] = a1[(i + a2) % v4];\n v5[v4] = 0;\n return v5;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1, int a2) {\n int i;\n int v4;\n uint8_t *v5;\n v4 = strlen(a1);\n v5 = malloc(v4 + 1);\n for (i = 0; i < v4; ++i) v5[i] = a1[(i + a2) % v4];\n v5[v4] = 0;\n return v5;\n}" + }, + { + "index": 973, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* s, int d) {\n int len = strlen(s);\n char* tmp = (char*)malloc(len + 1);\n for (int i = 0; i < len; i++) {\n tmp[i] = s[(i + d) % len];\n }\n tmp[len] = '\\0';\n return tmp;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"python\", 2), \"thonpy\") == 0);\n\n assert(strcmp(func0(\"bigdata\", 3), \"databig\") == 0);\n\n assert(strcmp(func0(\"hadoop\", 1), \"adooph\") == 0);\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%r12\nmov %esi,%r13d\nmov $0xffffffffffffffff,%rcx\nmov $0x0,%eax\nrepnz scas %es:(%rdi),%al\nnot %rcx\nlea -0x1(%rcx),%rbp\nlea 0x1(%rbp),%edi\nmovslq %edi,%rdi\ncallq 1090 \nmov %rax,%r8\ntest %ebp,%ebp\njle 11f0 \nmov %ebp,%ebx\nlea -0x1(%rbp),%eax\nlea 0x1(%r8,%rax,1),%rdi\nmov %r8,%rcx\nmov %r13d,%esi\nsub %r8d,%esi\nlea (%rsi,%rcx,1),%eax\ncltd\nidiv %ebx\nmovslq %edx,%rdx\nmovzbl (%r12,%rdx,1),%eax\nmov %al,(%rcx)\nadd $0x1,%rcx\ncmp %rdi,%rcx\njne 11d7 \nmovslq %ebp,%rbp\nmovb $0x0,(%r8,%rbp,1)\nmov %r8,%rax\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov r13d, esi\ncall _strlen\nmov r12, rax\nmov ebx, eax\nlea edi, [rax+1]\nmovsxd rdi, edi; size\ncall _malloc\nmov r8, rax\ntest r12d, r12d\njle short loc_1226\nlea eax, [r12-1]\nlea rdi, [r8+rax+1]\nmov rcx, r8\nmov esi, r13d\nsub esi, r8d\nloc_120D:\nlea eax, [rsi+rcx]\ncdq\nidiv ebx\nmovsxd rdx, edx\nmovzx eax, byte ptr [rbp+rdx+0]\nmov [rcx], al\nadd rcx, 1\ncmp rcx, rdi\njnz short loc_120D\nloc_1226:\nmovsxd r12, r12d\nmov byte ptr [r8+r12], 0\nmov rax, r8\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "_BYTE *__fastcall func0(const char *a1, int a2)\n{\n int v2; // r12d\n _BYTE *v3; // r8\n _BYTE *v4; // rcx\n\n v2 = strlen(a1);\n v3 = malloc(v2 + 1);\n if ( v2 > 0 )\n {\n v4 = v3;\n do\n {\n *v4 = a1[(a2 - (int)v3 + (int)v4) % v2];\n ++v4;\n }\n while ( v4 != &v3[v2 - 1 + 1] );\n }\n v3[v2] = 0;\n return v3;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r13\npush r12\npush rbp\npush rbx\nsub rsp, 8\nmov rbp, rdi\nmov r13d, esi\ncall _strlen\nmov r12, rax\nmov ebx, eax\nlea edi, [rax+1]\nmovsxd rdi, edi; size\ncall _malloc\nmov r8, rax\ntest r12d, r12d\njle short loc_1226\nlea eax, [r12-1]\nlea rdi, [r8+rax+1]\nmov rcx, r8\nmov esi, r13d\nsub esi, r8d\nloc_120D:\nlea eax, [rsi+rcx]\ncdq\nidiv ebx\nmovsxd rdx, edx\nmovzx eax, byte ptr [rbp+rdx+0]\nmov [rcx], al\nadd rcx, 1\ncmp rcx, rdi\njnz short loc_120D\nloc_1226:\nmovsxd r12, r12d\nmov byte ptr [r8+r12], 0\nmov rax, r8\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "_BYTE *__fastcall sub_11C9(const char *a1, int a2)\n{\n int v2; // r12d\n _BYTE *v3; // r8\n _BYTE *v4; // rcx\n\n v2 = strlen(a1);\n v3 = malloc(v2 + 1);\n if ( v2 > 0 )\n {\n v4 = v3;\n do\n {\n *v4 = a1[(a2 - (int)v3 + (int)v4) % v2];\n ++v4;\n }\n while ( v4 != &v3[v2 - 1 + 1] );\n }\n v3[v2] = 0;\n return v3;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "uint8_t *sub_11C9(const char *a1, int a2) {\n int v2;\n uint8_t *v3;\n uint8_t *v4;\n v2 = strlen(a1);\n v3 = malloc(v2 + 1);\n if (v2 > 0) {\n v4 = v3;\n do {\n *v4 = a1[(a2 - (int)v3 + (int)v4) % v2];\n ++v4;\n } while (v4 != &v3[v2 - 1 + 1]);\n }\n v3[v2] = 0;\n return v3;\n}", + "ida_pseudo_norm": "uint8_t *func0(const char *a1, int a2) {\n int v2;\n uint8_t *v3;\n uint8_t *v4;\n v2 = strlen(a1);\n v3 = malloc(v2 + 1);\n if (v2 > 0) {\n v4 = v3;\n do {\n *v4 = a1[(a2 - (int)v3 + (int)v4) % v2];\n ++v4;\n } while (v4 != &v3[v2 - 1 + 1]);\n }\n v3[v2] = 0;\n return v3;\n}" + }, + { + "index": 973, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* s, int d) {\n int len = strlen(s);\n char* tmp = (char*)malloc(len + 1);\n for (int i = 0; i < len; i++) {\n tmp[i] = s[(i + d) % len];\n }\n tmp[len] = '\\0';\n return tmp;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"python\", 2), \"thonpy\") == 0);\n\n assert(strcmp(func0(\"bigdata\", 3), \"databig\") == 0);\n\n assert(strcmp(func0(\"hadoop\", 1), \"adooph\") == 0);\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\nmov %rdi,%r12\npush %rbp\nmov %esi,%ebp\npush %rbx\nsub $0x8,%rsp\ncallq 1090 \nlea 0x1(%rax),%edi\nmov %rax,%r13\nmov %eax,%ebx\nmovslq %edi,%rdi\ncallq 10b0 \nmov %rax,%r8\ntest %r13d,%r13d\njle 1312 \nlea -0x1(%r13),%eax\nmov %ebp,%esi\nmov %r8,%rcx\nlea 0x1(%r8,%rax,1),%rdi\nsub %r8d,%esi\nnopl 0x0(%rax)\nlea (%rsi,%rcx,1),%eax\nadd $0x1,%rcx\ncltd\nidiv %ebx\nmovslq %edx,%rdx\nmovzbl (%r12,%rdx,1),%eax\nmov %al,-0x1(%rcx)\ncmp %rdi,%rcx\njne 12f8 \nmovslq %r13d,%r13\nmov %r8,%rax\nmovb $0x0,(%r8,%r13,1)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\nmov r12, rdi\npush rbp\nmov ebp, esi\npush rbx\nsub rsp, 8\ncall _strlen\nlea edi, [rax+1]\nmov r13, rax\nmov ebx, eax\nmovsxd rdi, edi; size\ncall _malloc\nmov r8, rax\ntest r13d, r13d\njle short loc_1322\nlea eax, [r13-1]\nmov esi, ebp\nmov rcx, r8\nlea rdi, [r8+rax+1]\nsub esi, r8d\nnop dword ptr [rax+00000000h]\nloc_1308:\nlea eax, [rsi+rcx]\nadd rcx, 1\ncdq\nidiv ebx\nmovsxd rdx, edx\nmovzx eax, byte ptr [r12+rdx]\nmov [rcx-1], al\ncmp rcx, rdi\njnz short loc_1308\nloc_1322:\nmovsxd r13, r13d\nmov rax, r8\nmov byte ptr [r8+r13], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "char *__fastcall func0(const char *a1, int a2)\n{\n int v2; // r13d\n char *v3; // r8\n char *v4; // rcx\n int v5; // eax\n char *result; // rax\n\n v2 = strlen(a1);\n v3 = (char *)malloc(v2 + 1);\n if ( v2 > 0 )\n {\n v4 = v3;\n do\n {\n v5 = a2 - (_DWORD)v3 + (_DWORD)v4++;\n *(v4 - 1) = a1[v5 % v2];\n }\n while ( v4 != &v3[v2 - 1 + 1] );\n }\n result = v3;\n v3[v2] = 0;\n return result;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\npush r13\npush r12\nmov r12, rdi\npush rbp\nmov ebp, esi\npush rbx\nsub rsp, 8\ncall _strlen\nlea edi, [rax+1]\nmov r13, rax\nmov ebx, eax\nmovsxd rdi, edi; size\ncall _malloc\nmov r8, rax\ntest r13d, r13d\njle short loc_1322\nlea eax, [r13-1]\nmov esi, ebp\nmov rcx, r8\nlea rdi, [r8+rax+1]\nsub esi, r8d\nnop dword ptr [rax+00000000h]\nloc_1308:\nlea eax, [rsi+rcx]\nadd rcx, 1\ncdq\nidiv ebx\nmovsxd rdx, edx\nmovzx eax, byte ptr [r12+rdx]\nmov [rcx-1], al\ncmp rcx, rdi\njnz short loc_1308\nloc_1322:\nmovsxd r13, r13d\nmov rax, r8\nmov byte ptr [r8+r13], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "char *__fastcall sub_12C0(const char *a1, int a2)\n{\n int v2; // r13d\n char *v3; // r8\n char *v4; // rcx\n int v5; // eax\n char *result; // rax\n\n v2 = strlen(a1);\n v3 = (char *)malloc(v2 + 1);\n if ( v2 > 0 )\n {\n v4 = v3;\n do\n {\n v5 = a2 - (_DWORD)v3 + (_DWORD)v4++;\n *(v4 - 1) = a1[v5 % v2];\n }\n while ( v4 != &v3[v2 - 1 + 1] );\n }\n result = v3;\n v3[v2] = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_12C0(const char *a1, int a2) {\n int v2;\n char *v3;\n char *v4;\n int v5;\n char *result;\n v2 = strlen(a1);\n v3 = (char *)malloc(v2 + 1);\n if (v2 > 0) {\n v4 = v3;\n do {\n v5 = a2 - (uint32_t)v3 + (uint32_t)v4++;\n *(v4 - 1) = a1[v5 % v2];\n } while (v4 != &v3[v2 - 1 + 1]);\n }\n result = v3;\n v3[v2] = 0;\n return result;\n}", + "ida_pseudo_norm": "char *func0(const char *a1, int a2) {\n int v2;\n char *v3;\n char *v4;\n int v5;\n char *result;\n v2 = strlen(a1);\n v3 = (char *)malloc(v2 + 1);\n if (v2 > 0) {\n v4 = v3;\n do {\n v5 = a2 - (uint32_t)v3 + (uint32_t)v4++;\n *(v4 - 1) = a1[v5 % v2];\n } while (v4 != &v3[v2 - 1 + 1]);\n }\n result = v3;\n v3[v2] = 0;\n return result;\n}" + }, + { + "index": 973, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "char* func0(char* s, int d) {\n int len = strlen(s);\n char* tmp = (char*)malloc(len + 1);\n for (int i = 0; i < len; i++) {\n tmp[i] = s[(i + d) % len];\n }\n tmp[len] = '\\0';\n return tmp;\n}", + "test": "int main() {\n\n assert(strcmp(func0(\"python\", 2), \"thonpy\") == 0);\n\n assert(strcmp(func0(\"bigdata\", 3), \"databig\") == 0);\n\n assert(strcmp(func0(\"hadoop\", 1), \"adooph\") == 0);\n\n\n\n printf(\"All test cases passed.\\n\");\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r13\npush %r12\nmov %rdi,%r12\npush %rbp\nmov %esi,%ebp\npush %rbx\nsub $0x8,%rsp\ncallq 1090 \nlea 0x1(%rax),%edi\nmov %rax,%r13\nmov %eax,%ebx\nmovslq %edi,%rdi\ncallq 10b0 \nmov %rax,%r8\ntest %r13d,%r13d\njle 1312 \nlea -0x1(%r13),%eax\nmov %ebp,%esi\nmov %r8,%rcx\nlea 0x1(%r8,%rax,1),%rdi\nsub %r8d,%esi\nnopl 0x0(%rax)\nlea (%rsi,%rcx,1),%eax\nadd $0x1,%rcx\ncltd\nidiv %ebx\nmovslq %edx,%rdx\nmovzbl (%r12,%rdx,1),%eax\nmov %al,-0x1(%rcx)\ncmp %rcx,%rdi\njne 12f8 \nmovslq %r13d,%r13\nmov %r8,%rax\nmovb $0x0,(%r8,%r13,1)\nadd $0x8,%rsp\npop %rbx\npop %rbp\npop %r12\npop %r13\nretq\nnopl 0x0(%rax,%rax,1)\n", + "ida_asm": "func0:\nendbr64\npush r13\npush r12\nmov r12, rdi\npush rbp\nmov ebp, esi\npush rbx\nsub rsp, 8\ncall _strlen\nlea edi, [rax+1]\nmov r13, rax\nmov ebx, eax\nmovsxd rdi, edi; size\ncall _malloc\nmov r8, rax\ntest r13d, r13d\njle short loc_1322\nlea eax, [r13-1]\nmov esi, ebp\nmov rcx, r8\nlea rdi, [r8+rax+1]\nsub esi, r8d\nnop dword ptr [rax+00000000h]\nloc_1308:\nlea eax, [rsi+rcx]\nadd rcx, 1\ncdq\nidiv ebx\nmovsxd rdx, edx\nmovzx eax, byte ptr [r12+rdx]\nmov [rcx-1], al\ncmp rcx, rdi\njnz short loc_1308\nloc_1322:\nmovsxd r13, r13d\nmov rax, r8\nmov byte ptr [r8+r13], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_pseudo": "char *__fastcall func0(const char *a1, int a2)\n{\n int v2; // r13d\n char *v3; // r8\n char *v4; // rcx\n int v5; // eax\n char *result; // rax\n\n v2 = strlen(a1);\n v3 = (char *)malloc(v2 + 1);\n if ( v2 > 0 )\n {\n v4 = v3;\n do\n {\n v5 = a2 - (_DWORD)v3 + (_DWORD)v4++;\n *(v4 - 1) = a1[v5 % v2];\n }\n while ( v4 != &v3[v2 - 1 + 1] );\n }\n result = v3;\n v3[v2] = 0;\n return result;\n}", + "ida_strip_asm": "sub_12C0:\nendbr64\npush r13\npush r12\nmov r12, rdi\npush rbp\nmov ebp, esi\npush rbx\nsub rsp, 8\ncall _strlen\nlea edi, [rax+1]\nmov r13, rax\nmov ebx, eax\nmovsxd rdi, edi; size\ncall _malloc\nmov r8, rax\ntest r13d, r13d\njle short loc_1322\nlea eax, [r13-1]\nmov esi, ebp\nmov rcx, r8\nlea rdi, [r8+rax+1]\nsub esi, r8d\nnop dword ptr [rax+00000000h]\nloc_1308:\nlea eax, [rsi+rcx]\nadd rcx, 1\ncdq\nidiv ebx\nmovsxd rdx, edx\nmovzx eax, byte ptr [r12+rdx]\nmov [rcx-1], al\ncmp rcx, rdi\njnz short loc_1308\nloc_1322:\nmovsxd r13, r13d\nmov rax, r8\nmov byte ptr [r8+r13], 0\nadd rsp, 8\npop rbx\npop rbp\npop r12\npop r13\nretn", + "ida_strip_pseudo": "char *__fastcall sub_12C0(const char *a1, int a2)\n{\n int v2; // r13d\n char *v3; // r8\n char *v4; // rcx\n int v5; // eax\n char *result; // rax\n\n v2 = strlen(a1);\n v3 = (char *)malloc(v2 + 1);\n if ( v2 > 0 )\n {\n v4 = v3;\n do\n {\n v5 = a2 - (_DWORD)v3 + (_DWORD)v4++;\n *(v4 - 1) = a1[v5 % v2];\n }\n while ( v4 != &v3[v2 - 1 + 1] );\n }\n result = v3;\n v3[v2] = 0;\n return result;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "char *sub_12C0(const char *a1, int a2) {\n int v2;\n char *v3;\n char *v4;\n int v5;\n char *result;\n v2 = strlen(a1);\n v3 = (char *)malloc(v2 + 1);\n if (v2 > 0) {\n v4 = v3;\n do {\n v5 = a2 - (uint32_t)v3 + (uint32_t)v4++;\n *(v4 - 1) = a1[v5 % v2];\n } while (v4 != &v3[v2 - 1 + 1]);\n }\n result = v3;\n v3[v2] = 0;\n return result;\n}", + "ida_pseudo_norm": "char *func0(const char *a1, int a2) {\n int v2;\n char *v3;\n char *v4;\n int v5;\n char *result;\n v2 = strlen(a1);\n v3 = (char *)malloc(v2 + 1);\n if (v2 > 0) {\n v4 = v3;\n do {\n v5 = a2 - (uint32_t)v3 + (uint32_t)v4++;\n *(v4 - 1) = a1[v5 % v2];\n } while (v4 != &v3[v2 - 1 + 1]);\n }\n result = v3;\n v3[v2] = 0;\n return result;\n}" + }, + { + "index": 974, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int** A, int rows) {\n int* memo = (int*)malloc(rows * sizeof(int));\n int n = rows - 1;\n for (int i = 0; i < rows; i++) {\n memo[i] = A[n][i];\n }\n for (int i = rows - 2; i >= 0; i--) {\n for (int j = 0; j <= i; j++) {\n int minValue = memo[j] < memo[j + 1] ? memo[j] : memo[j + 1];\n memo[j] = A[i][j] + minValue;\n }\n }\n int result = memo[0];\n free(memo);\n return result;\n}", + "test": "int main() {\n\n int a1[3][3] = {{2}, {3, 9}, {1, 6, 7}};\n\n int a2[3][3] = {{2}, {3, 7}, {8, 5, 6}};\n\n int a3[3][3] = {{3}, {6, 4}, {5, 2, 7}};\n\n\n\n int* pa1[3] = {a1[0], a1[1], a1[2]};\n\n int* pa2[3] = {a2[0], a2[1], a2[2]};\n\n int* pa3[3] = {a3[0], a3[1], a3[2]};\n\n\n\n assert(func0(pa1, 3) == 6);\n\n assert(func0(pa2, 3) == 10);\n\n assert(func0(pa3, 3) == 9);\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O0", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\nmov %rsp,%rbp\nsub $0x30,%rsp\nmov %rdi,-0x28(%rbp)\nmov %esi,-0x2c(%rbp)\nmov -0x2c(%rbp),%eax\ncltq\nshl $0x2,%rax\nmov %rax,%rdi\ncallq 10d0 \nmov %rax,-0x8(%rbp)\nmov -0x2c(%rbp),%eax\nsub $0x1,%eax\nmov %eax,-0x14(%rbp)\nmovl $0x0,-0x20(%rbp)\njmp 1244 \nmov -0x14(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0x20(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x2,%rdx\nadd %rdx,%rax\nmov -0x20(%rbp),%edx\nmovslq %edx,%rdx\nlea 0x0(,%rdx,4),%rcx\nmov -0x8(%rbp),%rdx\nadd %rcx,%rdx\nmov (%rax),%eax\nmov %eax,(%rdx)\naddl $0x1,-0x20(%rbp)\nmov -0x20(%rbp),%eax\ncmp -0x2c(%rbp),%eax\njl 1203 \nmov -0x2c(%rbp),%eax\nsub $0x2,%eax\nmov %eax,-0x1c(%rbp)\njmpq 12f0 \nmovl $0x0,-0x18(%rbp)\njmp 12e0 \nmov -0x18(%rbp),%eax\ncltq\nadd $0x1,%rax\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%edx\nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rcx\nmov -0x8(%rbp),%rax\nadd %rcx,%rax\nmov (%rax),%eax\ncmp %eax,%edx\ncmovle %edx,%eax\nmov %eax,-0xc(%rbp)\nmov -0x1c(%rbp),%eax\ncltq\nlea 0x0(,%rax,8),%rdx\nmov -0x28(%rbp),%rax\nadd %rdx,%rax\nmov (%rax),%rax\nmov -0x18(%rbp),%edx\nmovslq %edx,%rdx\nshl $0x2,%rdx\nadd %rdx,%rax\nmov (%rax),%ecx\nmov -0x18(%rbp),%eax\ncltq\nlea 0x0(,%rax,4),%rdx\nmov -0x8(%rbp),%rax\nadd %rdx,%rax\nmov -0xc(%rbp),%edx\nadd %ecx,%edx\nmov %edx,(%rax)\naddl $0x1,-0x18(%rbp)\nmov -0x18(%rbp),%eax\ncmp -0x1c(%rbp),%eax\njle 1263 \nsubl $0x1,-0x1c(%rbp)\ncmpl $0x0,-0x1c(%rbp)\njns 125a \nmov -0x8(%rbp),%rax\nmov (%rax),%eax\nmov %eax,-0x10(%rbp)\nmov -0x8(%rbp),%rax\nmov %rax,%rdi\ncallq 1090 \nmov -0x10(%rbp),%eax\nleaveq\nretq\n", + "ida_asm": "func0:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov eax, [rbp+var_2C]\nsub eax, 1\nmov [rbp+var_14], eax\nmov [rbp+var_20], 0\njmp short loc_1244\nloc_1203:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+ptr]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_20], 1\nloc_1244:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_2C]\njl short loc_1203\nmov eax, [rbp+var_2C]\nsub eax, 2\nmov [rbp+var_1C], eax\njmp loc_12F0\nloc_125A:\nmov [rbp+var_18], 0\njmp short loc_12E0\nloc_1263:\nmov eax, [rbp+var_18]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_18]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\ncmovle eax, edx\nmov [rbp+var_C], eax\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_18]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov ecx, [rax]\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rbp+var_C]\nadd edx, ecx\nmov [rax], edx\nadd [rbp+var_18], 1\nloc_12E0:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_1C]\njle loc_1263\nsub [rbp+var_1C], 1\nloc_12F0:\ncmp [rbp+var_1C], 0\njns loc_125A\nmov rax, [rbp+ptr]\nmov eax, [rax]\nmov [rbp+var_10], eax\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov eax, [rbp+var_10]\nleave\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int v2; // eax\n int i; // [rsp+10h] [rbp-20h]\n int j; // [rsp+14h] [rbp-1Ch]\n int k; // [rsp+18h] [rbp-18h]\n unsigned int v7; // [rsp+20h] [rbp-10h]\n unsigned int *ptr; // [rsp+28h] [rbp-8h]\n\n ptr = (unsigned int *)malloc(4LL * a2);\n for ( i = 0; i < a2; ++i )\n ptr[i] = *(_DWORD *)(4LL * i + *(_QWORD *)(8LL * (a2 - 1) + a1));\n for ( j = a2 - 2; j >= 0; --j )\n {\n for ( k = 0; k <= j; ++k )\n {\n v2 = ptr[k];\n if ( (int)ptr[k + 1] <= v2 )\n v2 = ptr[k + 1];\n ptr[k] = *(_DWORD *)(4LL * k + *(_QWORD *)(8LL * j + a1)) + v2;\n }\n }\n v7 = *ptr;\n free(ptr);\n return v7;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush rbp\nmov rbp, rsp\nsub rsp, 30h\nmov [rbp+var_28], rdi\nmov [rbp+var_2C], esi\nmov eax, [rbp+var_2C]\ncdqe\nshl rax, 2\nmov rdi, rax; size\ncall _malloc\nmov [rbp+ptr], rax\nmov eax, [rbp+var_2C]\nsub eax, 1\nmov [rbp+var_14], eax\nmov [rbp+var_20], 0\njmp short loc_1244\nloc_1203:\nmov eax, [rbp+var_14]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov edx, [rbp+var_20]\nmovsxd rdx, edx\nlea rcx, ds:0[rdx*4]\nmov rdx, [rbp+ptr]\nadd rdx, rcx\nmov eax, [rax]\nmov [rdx], eax\nadd [rbp+var_20], 1\nloc_1244:\nmov eax, [rbp+var_20]\ncmp eax, [rbp+var_2C]\njl short loc_1203\nmov eax, [rbp+var_2C]\nsub eax, 2\nmov [rbp+var_1C], eax\njmp loc_12F0\nloc_125A:\nmov [rbp+var_18], 0\njmp short loc_12E0\nloc_1263:\nmov eax, [rbp+var_18]\ncdqe\nadd rax, 1\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rax]\nmov eax, [rbp+var_18]\ncdqe\nlea rcx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rcx\nmov eax, [rax]\ncmp edx, eax\ncmovle eax, edx\nmov [rbp+var_C], eax\nmov eax, [rbp+var_1C]\ncdqe\nlea rdx, ds:0[rax*8]\nmov rax, [rbp+var_28]\nadd rax, rdx\nmov rax, [rax]\nmov edx, [rbp+var_18]\nmovsxd rdx, edx\nshl rdx, 2\nadd rax, rdx\nmov ecx, [rax]\nmov eax, [rbp+var_18]\ncdqe\nlea rdx, ds:0[rax*4]\nmov rax, [rbp+ptr]\nadd rax, rdx\nmov edx, [rbp+var_C]\nadd edx, ecx\nmov [rax], edx\nadd [rbp+var_18], 1\nloc_12E0:\nmov eax, [rbp+var_18]\ncmp eax, [rbp+var_1C]\njle loc_1263\nsub [rbp+var_1C], 1\nloc_12F0:\ncmp [rbp+var_1C], 0\njns loc_125A\nmov rax, [rbp+ptr]\nmov eax, [rax]\nmov [rbp+var_10], eax\nmov rax, [rbp+ptr]\nmov rdi, rax; ptr\ncall _free\nmov eax, [rbp+var_10]\nleave\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11C9(__int64 a1, int a2)\n{\n int v2; // eax\n int i; // [rsp+10h] [rbp-20h]\n int j; // [rsp+14h] [rbp-1Ch]\n int k; // [rsp+18h] [rbp-18h]\n unsigned int v7; // [rsp+20h] [rbp-10h]\n unsigned int *ptr; // [rsp+28h] [rbp-8h]\n\n ptr = (unsigned int *)malloc(4LL * a2);\n for ( i = 0; i < a2; ++i )\n ptr[i] = *(_DWORD *)(4LL * i + *(_QWORD *)(8LL * (a2 - 1) + a1));\n for ( j = a2 - 2; j >= 0; --j )\n {\n for ( k = 0; k <= j; ++k )\n {\n v2 = ptr[k];\n if ( (int)ptr[k + 1] <= v2 )\n v2 = ptr[k + 1];\n ptr[k] = *(_DWORD *)(4LL * k + *(_QWORD *)(8LL * j + a1)) + v2;\n }\n }\n v7 = *ptr;\n free(ptr);\n return v7;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11C9(long long a1, int a2) {\n int v2;\n int i;\n int j;\n int k;\n unsigned int v7;\n unsigned int *ptr;\n ptr = (unsigned int *)malloc(4LL * a2);\n for (i = 0; i < a2; ++i)\n ptr[i] = *(uint32_t *)(4LL * i + *(uint64_t *)(8LL * (a2 - 1) + a1));\n for (j = a2 - 2; j >= 0; --j) {\n for (k = 0; k <= j; ++k) {\n v2 = ptr[k];\n if ((int)ptr[k + 1] <= v2) v2 = ptr[k + 1];\n ptr[k] = *(uint32_t *)(4LL * k + *(uint64_t *)(8LL * j + a1)) + v2;\n }\n }\n v7 = *ptr;\n free(ptr);\n return v7;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int v2;\n int i;\n int j;\n int k;\n unsigned int v7;\n unsigned int *ptr;\n ptr = (unsigned int *)malloc(4LL * a2);\n for (i = 0; i < a2; ++i)\n ptr[i] = *(uint32_t *)(4LL * i + *(uint64_t *)(8LL * (a2 - 1) + a1));\n for (j = a2 - 2; j >= 0; --j) {\n for (k = 0; k <= j; ++k) {\n v2 = ptr[k];\n if ((int)ptr[k + 1] <= v2) v2 = ptr[k + 1];\n ptr[k] = *(uint32_t *)(4LL * k + *(uint64_t *)(8LL * j + a1)) + v2;\n }\n }\n v7 = *ptr;\n free(ptr);\n return v7;\n}" + }, + { + "index": 974, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int** A, int rows) {\n int* memo = (int*)malloc(rows * sizeof(int));\n int n = rows - 1;\n for (int i = 0; i < rows; i++) {\n memo[i] = A[n][i];\n }\n for (int i = rows - 2; i >= 0; i--) {\n for (int j = 0; j <= i; j++) {\n int minValue = memo[j] < memo[j + 1] ? memo[j] : memo[j + 1];\n memo[j] = A[i][j] + minValue;\n }\n }\n int result = memo[0];\n free(memo);\n return result;\n}", + "test": "int main() {\n\n int a1[3][3] = {{2}, {3, 9}, {1, 6, 7}};\n\n int a2[3][3] = {{2}, {3, 7}, {8, 5, 6}};\n\n int a3[3][3] = {{3}, {6, 4}, {5, 2, 7}};\n\n\n\n int* pa1[3] = {a1[0], a1[1], a1[2]};\n\n int* pa2[3] = {a2[0], a2[1], a2[2]};\n\n int* pa3[3] = {a3[0], a3[1], a3[2]};\n\n\n\n assert(func0(pa1, 3) == 6);\n\n assert(func0(pa2, 3) == 10);\n\n assert(func0(pa3, 3) == 9);\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O1", + "language": "c", + "asm": "func0:\nendbr64\npush %rbp\npush %rbx\nsub $0x8,%rsp\nmov %rdi,%rbx\nmov %esi,%ebp\nmovslq %esi,%rdi\nshl $0x2,%rdi\ncallq 10d0 \nmov %rax,%rdi\ntest %ebp,%ebp\njle 120e \nlea -0x1(%rbp),%eax\ncltq\nmov (%rbx,%rax,8),%rsi\nlea -0x1(%rbp),%ecx\nmov $0x0,%eax\nmov (%rsi,%rax,4),%edx\nmov %edx,(%rdi,%rax,4)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rcx,%rdx\njne 11fc \nmov %ebp,%r8d\nsub $0x2,%r8d\njs 125b \nmovslq %r8d,%r8\njmp 1254 \nmov (%rbx,%r8,8),%rsi\nmov %r8d,%eax\nlea 0x4(,%rax,4),%rax\nmov $0x0,%edx\nmov (%rdi,%rdx,1),%ecx\ncmp %ecx,0x4(%rdi,%rdx,1)\ncmovle 0x4(%rdi,%rdx,1),%ecx\nadd (%rsi,%rdx,1),%ecx\nmov %ecx,(%rdi,%rdx,1)\nadd $0x4,%rdx\ncmp %rax,%rdx\njne 1230 \nsub $0x1,%r8\ntest %r8d,%r8d\njs 125b \ntest %r8d,%r8d\njns 121c \njmp 124b \nmov (%rdi),%ebx\ncallq 1090 \nmov %ebx,%eax\nadd $0x8,%rsp\npop %rbx\npop %rbp\nretq\n", + "ida_asm": "func0:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nmov ebp, esi\nmovsxd r12, esi\nshl r12, 2\nmov rdi, r12; size\ncall _malloc\nmov rdi, rax; ptr\ntest ebp, ebp\njle short loc_124A\nlea eax, [rbp-1]\ncdqe\nmov rcx, [rbx+rax*8]\nmov eax, 0\nloc_11FA:\nmov edx, [rcx+rax]\nmov [rdi+rax], edx\nadd rax, 4\ncmp r12, rax\njnz short loc_11FA\nsub ebp, 2\njs short loc_124A\nmovsxd r9, ebp\nloc_1211:\nmov r8, [rbx+r9*8]\nmov eax, r9d\nlea rsi, ds:4[rax*4]\nmov eax, 0\nloc_1225:\nmov edx, [rdi+rax+4]\nmov ecx, [rdi+rax]\ncmp edx, ecx\ncmovg edx, ecx\nadd edx, [r8+rax]\nmov [rdi+rax], edx\nadd rax, 4\ncmp rax, rsi\njnz short loc_1225\nsub r9, 1\ntest r9d, r9d\njns short loc_1211\nloc_124A:\nmov ebx, [rdi]\ncall _free\nmov eax, ebx\npop rbx\npop rbp\npop r12\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n unsigned int *v3; // rdi\n __int64 v4; // rcx\n __int64 i; // rax\n __int64 v6; // r9\n __int64 v7; // r8\n unsigned __int64 v8; // rax\n int v9; // edx\n unsigned int v10; // ebx\n\n v3 = (unsigned int *)malloc(4LL * a2);\n if ( a2 > 0 )\n {\n v4 = *(_QWORD *)(a1 + 8LL * (a2 - 1));\n for ( i = 0LL; i != a2; ++i )\n v3[i] = *(_DWORD *)(v4 + i * 4);\n if ( a2 - 2 >= 0 )\n {\n v6 = a2 - 2;\n do\n {\n v7 = *(_QWORD *)(a1 + 8 * v6);\n v8 = 0LL;\n do\n {\n v9 = v3[v8 / 4 + 1];\n if ( v9 > (int)v3[v8 / 4] )\n v9 = v3[v8 / 4];\n v3[v8 / 4] = *(_DWORD *)(v7 + v8) + v9;\n v8 += 4LL;\n }\n while ( v8 != 4LL * (unsigned int)v6 + 4 );\n --v6;\n }\n while ( (int)v6 >= 0 );\n }\n }\n v10 = *v3;\n free(v3);\n return v10;\n}", + "ida_strip_asm": "sub_11C9:\nendbr64\npush r12\npush rbp\npush rbx\nmov rbx, rdi\nmov ebp, esi\nmovsxd r12, esi\nshl r12, 2\nmov rdi, r12; size\ncall _malloc\nmov rdi, rax; ptr\ntest ebp, ebp\njle short loc_124A\nlea eax, [rbp-1]\ncdqe\nmov rcx, [rbx+rax*8]\nmov eax, 0\nloc_11FA:\nmov edx, [rcx+rax]\nmov [rdi+rax], edx\nadd rax, 4\ncmp r12, rax\njnz short loc_11FA\nsub ebp, 2\njs short loc_124A\nmovsxd r9, ebp\nloc_1211:\nmov r8, [rbx+r9*8]\nmov eax, r9d\nlea rsi, ds:4[rax*4]\nmov eax, 0\nloc_1225:\nmov edx, [rdi+rax+4]\nmov ecx, [rdi+rax]\ncmp edx, ecx\ncmovg edx, ecx\nadd edx, [r8+rax]\nmov [rdi+rax], edx\nadd rax, 4\ncmp rax, rsi\njnz short loc_1225\nsub r9, 1\ntest r9d, r9d\njns short loc_1211\nloc_124A:\nmov ebx, [rdi]\ncall _free\nmov eax, ebx\npop rbx\npop rbp\npop r12\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_11C9(__int64 a1, int a2)\n{\n unsigned int *v3; // rdi\n __int64 v4; // rcx\n __int64 i; // rax\n __int64 v6; // r9\n __int64 v7; // r8\n unsigned __int64 v8; // rax\n int v9; // edx\n unsigned int v10; // ebx\n\n v3 = (unsigned int *)malloc(4LL * a2);\n if ( a2 > 0 )\n {\n v4 = *(_QWORD *)(a1 + 8LL * (a2 - 1));\n for ( i = 0LL; i != a2; ++i )\n v3[i] = *(_DWORD *)(v4 + i * 4);\n if ( a2 - 2 >= 0 )\n {\n v6 = a2 - 2;\n do\n {\n v7 = *(_QWORD *)(a1 + 8 * v6);\n v8 = 0LL;\n do\n {\n v9 = v3[v8 / 4 + 1];\n if ( v9 > (int)v3[v8 / 4] )\n v9 = v3[v8 / 4];\n v3[v8 / 4] = *(_DWORD *)(v7 + v8) + v9;\n v8 += 4LL;\n }\n while ( v8 != 4LL * (unsigned int)v6 + 4 );\n --v6;\n }\n while ( (int)v6 >= 0 );\n }\n }\n v10 = *v3;\n free(v3);\n return v10;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_11C9(long long a1, int a2) {\n unsigned int *v3;\n long long v4;\n long long i;\n long long v6;\n long long v7;\n unsigned long long v8;\n int v9;\n unsigned int v10;\n v3 = (unsigned int *)malloc(4LL * a2);\n if (a2 > 0) {\n v4 = *(uint64_t *)(a1 + 8LL * (a2 - 1));\n for (i = 0LL; i != a2; ++i) v3[i] = *(uint32_t *)(v4 + i * 4);\n if (a2 - 2 >= 0) {\n v6 = a2 - 2;\n do {\n v7 = *(uint64_t *)(a1 + 8 * v6);\n v8 = 0LL;\n do {\n v9 = v3[v8 / 4 + 1];\n if (v9 > (int)v3[v8 / 4]) v9 = v3[v8 / 4];\n v3[v8 / 4] = *(uint32_t *)(v7 + v8) + v9;\n v8 += 4LL;\n } while (v8 != 4LL * (unsigned int)v6 + 4);\n --v6;\n } while ((int)v6 >= 0);\n }\n }\n v10 = *v3;\n free(v3);\n return v10;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n unsigned int *v3;\n long long v4;\n long long i;\n long long v6;\n long long v7;\n unsigned long long v8;\n int v9;\n unsigned int v10;\n v3 = (unsigned int *)malloc(4LL * a2);\n if (a2 > 0) {\n v4 = *(uint64_t *)(a1 + 8LL * (a2 - 1));\n for (i = 0LL; i != a2; ++i) v3[i] = *(uint32_t *)(v4 + i * 4);\n if (a2 - 2 >= 0) {\n v6 = a2 - 2;\n do {\n v7 = *(uint64_t *)(a1 + 8 * v6);\n v8 = 0LL;\n do {\n v9 = v3[v8 / 4 + 1];\n if (v9 > (int)v3[v8 / 4]) v9 = v3[v8 / 4];\n v3[v8 / 4] = *(uint32_t *)(v7 + v8) + v9;\n v8 += 4LL;\n } while (v8 != 4LL * (unsigned int)v6 + 4);\n --v6;\n } while ((int)v6 >= 0);\n }\n }\n v10 = *v3;\n free(v3);\n return v10;\n}" + }, + { + "index": 974, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int** A, int rows) {\n int* memo = (int*)malloc(rows * sizeof(int));\n int n = rows - 1;\n for (int i = 0; i < rows; i++) {\n memo[i] = A[n][i];\n }\n for (int i = rows - 2; i >= 0; i--) {\n for (int j = 0; j <= i; j++) {\n int minValue = memo[j] < memo[j + 1] ? memo[j] : memo[j + 1];\n memo[j] = A[i][j] + minValue;\n }\n }\n int result = memo[0];\n free(memo);\n return result;\n}", + "test": "int main() {\n\n int a1[3][3] = {{2}, {3, 9}, {1, 6, 7}};\n\n int a2[3][3] = {{2}, {3, 7}, {8, 5, 6}};\n\n int a3[3][3] = {{3}, {6, 4}, {5, 2, 7}};\n\n\n\n int* pa1[3] = {a1[0], a1[1], a1[2]};\n\n int* pa2[3] = {a2[0], a2[1], a2[2]};\n\n int* pa3[3] = {a3[0], a3[1], a3[2]};\n\n\n\n assert(func0(pa1, 3) == 6);\n\n assert(func0(pa2, 3) == 10);\n\n assert(func0(pa3, 3) == 9);\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O2", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\nmov %rdi,%rbp\nmovslq %esi,%rdi\npush %rbx\nmov %rdi,%rbx\nshl $0x2,%rdi\ncallq 10d0 \nmov %rax,%rdi\ntest %ebx,%ebx\njle 1452 \nlea -0x1(%rbx),%ecx\nmovslq %ecx,%rax\nmov %ecx,%ecx\nmov 0x0(%rbp,%rax,8),%rsi\nxor %eax,%eax\nmov (%rsi,%rax,4),%edx\nmov %edx,(%rdi,%rax,4)\nmov %rax,%rdx\nadd $0x1,%rax\ncmp %rdx,%rcx\njne 1440 \nmov %ebx,%eax\nsub $0x2,%eax\njs 1492 \ncltq\nnopl 0x0(%rax,%rax,1)\nmov 0x0(%rbp,%rax,8),%rsi\nxor %edx,%edx\nnopw 0x0(%rax,%rax,1)\nmov (%rdi,%rdx,4),%ecx\ncmp %ecx,0x4(%rdi,%rdx,4)\ncmovle 0x4(%rdi,%rdx,4),%ecx\nadd (%rsi,%rdx,4),%ecx\nmov %ecx,(%rdi,%rdx,4)\nadd $0x1,%rdx\ncmp %edx,%eax\njge 1470 \nsub $0x1,%rax\ntest %eax,%eax\njns 1460 \nmov (%rdi),%r12d\ncallq 1090 \npop %rbx\npop %rbp\nmov %r12d,%eax\npop %r12\nretq\nnopw %cs:0x0(%rax,%rax,1)\nnopl 0x0(%rax)\n", + "ida_asm": "func0:\nendbr64\npush rbp\npush rbx\nmov rbx, rdi\nmovsxd rdi, esi\nmov rbp, rdi\nshl rdi, 2; size\nsub rsp, 8\ncall _malloc\nmov rdi, rax; dest\ntest ebp, ebp\njle short loc_14BC\nlea eax, [rbp-1]\nmov edx, ebp\ncdqe\nshl rdx, 2; n\nmov rsi, [rbx+rax*8]; src\ncall _memcpy\nlea r9d, [rbp-2]\nmov rdi, rax; ptr\ncmp ebp, 1\njz short loc_14BC\nmovsxd r9, r9d\nnop word ptr [rax+rax+00000000h]\nloc_1480:\nmov eax, r9d\nmov r8, [rbx+r9*8]\nmov ecx, [rdi]\nxor edx, edx\nlea rsi, ds:4[rax*4]\nnop dword ptr [rax+rax+00h]\nloc_1498:\nmov eax, ecx\nmov ecx, [rdi+rdx+4]\ncmp ecx, eax\ncmovle eax, ecx\nadd eax, [r8+rdx]\nmov [rdi+rdx], eax\nadd rdx, 4\ncmp rdx, rsi\njnz short loc_1498\nsub r9, 1\ntest r9d, r9d\njns short loc_1480\nloc_14BC:\nmov ebx, [rdi]\ncall _free\nadd rsp, 8\nmov eax, ebx\npop rbx\npop rbp\nretn", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n int *v3; // rdi\n int *v4; // rax\n __int64 v5; // r9\n __int64 v6; // r8\n int v7; // ecx\n unsigned __int64 v8; // rdx\n int v9; // eax\n unsigned int v10; // ebx\n\n v3 = (int *)malloc(4LL * a2);\n if ( a2 > 0 )\n {\n v4 = (int *)memcpy(v3, *(const void **)(a1 + 8LL * (a2 - 1)), 4LL * (unsigned int)a2);\n LODWORD(v5) = a2 - 2;\n v3 = v4;\n if ( a2 != 1 )\n {\n v5 = (int)v5;\n do\n {\n v6 = *(_QWORD *)(a1 + 8 * v5);\n v7 = *v3;\n v8 = 0LL;\n do\n {\n v9 = v7;\n v7 = v3[v8 / 4 + 1];\n if ( v7 <= v9 )\n v9 = v3[v8 / 4 + 1];\n v3[v8 / 4] = *(_DWORD *)(v6 + v8) + v9;\n v8 += 4LL;\n }\n while ( v8 != 4LL * (unsigned int)v5 + 4 );\n --v5;\n }\n while ( (int)v5 >= 0 );\n }\n }\n v10 = *v3;\n free(v3);\n return v10;\n}", + "ida_strip_asm": "sub_1430:\nendbr64\npush rbp\npush rbx\nmov rbx, rdi\nmovsxd rdi, esi\nmov rbp, rdi\nshl rdi, 2; size\nsub rsp, 8\ncall _malloc\nmov rdi, rax; dest\ntest ebp, ebp\njle short loc_14BC\nlea eax, [rbp-1]\nmov edx, ebp\ncdqe\nshl rdx, 2; n\nmov rsi, [rbx+rax*8]; src\ncall _memcpy\nlea r9d, [rbp-2]\nmov rdi, rax; ptr\ncmp ebp, 1\njz short loc_14BC\nmovsxd r9, r9d\nnop word ptr [rax+rax+00000000h]\nloc_1480:\nmov eax, r9d\nmov r8, [rbx+r9*8]\nmov ecx, [rdi]\nxor edx, edx\nlea rsi, ds:4[rax*4]\nnop dword ptr [rax+rax+00h]\nloc_1498:\nmov eax, ecx\nmov ecx, [rdi+rdx+4]\ncmp ecx, eax\ncmovle eax, ecx\nadd eax, [r8+rdx]\nmov [rdi+rdx], eax\nadd rdx, 4\ncmp rdx, rsi\njnz short loc_1498\nsub r9, 1\ntest r9d, r9d\njns short loc_1480\nloc_14BC:\nmov ebx, [rdi]\ncall _free\nadd rsp, 8\nmov eax, ebx\npop rbx\npop rbp\nretn", + "ida_strip_pseudo": "__int64 __fastcall sub_1430(__int64 a1, int a2)\n{\n int *v3; // rdi\n int *v4; // rax\n __int64 v5; // r9\n __int64 v6; // r8\n int v7; // ecx\n unsigned __int64 v8; // rdx\n int v9; // eax\n unsigned int v10; // ebx\n\n v3 = (int *)malloc(4LL * a2);\n if ( a2 > 0 )\n {\n v4 = (int *)memcpy(v3, *(const void **)(a1 + 8LL * (a2 - 1)), 4LL * (unsigned int)a2);\n LODWORD(v5) = a2 - 2;\n v3 = v4;\n if ( a2 != 1 )\n {\n v5 = (int)v5;\n do\n {\n v6 = *(_QWORD *)(a1 + 8 * v5);\n v7 = *v3;\n v8 = 0LL;\n do\n {\n v9 = v7;\n v7 = v3[v8 / 4 + 1];\n if ( v7 <= v9 )\n v9 = v3[v8 / 4 + 1];\n v3[v8 / 4] = *(_DWORD *)(v6 + v8) + v9;\n v8 += 4LL;\n }\n while ( v8 != 4LL * (unsigned int)v5 + 4 );\n --v5;\n }\n while ( (int)v5 >= 0 );\n }\n }\n v10 = *v3;\n free(v3);\n return v10;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1430(long long a1, int a2) {\n int *v3;\n int *v4;\n long long v5;\n long long v6;\n int v7;\n unsigned long long v8;\n int v9;\n unsigned int v10;\n v3 = (int *)malloc(4LL * a2);\n if (a2 > 0) {\n v4 = (int *)memcpy(v3, *(const void **)(a1 + 8LL * (a2 - 1)),\n 4LL * (unsigned int)a2);\n LODWORD(v5) = a2 - 2;\n v3 = v4;\n if (a2 != 1) {\n v5 = (int)v5;\n do {\n v6 = *(uint64_t *)(a1 + 8 * v5);\n v7 = *v3;\n v8 = 0LL;\n do {\n v9 = v7;\n v7 = v3[v8 / 4 + 1];\n if (v7 <= v9) v9 = v3[v8 / 4 + 1];\n v3[v8 / 4] = *(uint32_t *)(v6 + v8) + v9;\n v8 += 4LL;\n } while (v8 != 4LL * (unsigned int)v5 + 4);\n --v5;\n } while ((int)v5 >= 0);\n }\n }\n v10 = *v3;\n free(v3);\n return v10;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n int *v3;\n int *v4;\n long long v5;\n long long v6;\n int v7;\n unsigned long long v8;\n int v9;\n unsigned int v10;\n v3 = (int *)malloc(4LL * a2);\n if (a2 > 0) {\n v4 = (int *)memcpy(v3, *(const void **)(a1 + 8LL * (a2 - 1)),\n 4LL * (unsigned int)a2);\n LODWORD(v5) = a2 - 2;\n v3 = v4;\n if (a2 != 1) {\n v5 = (int)v5;\n do {\n v6 = *(uint64_t *)(a1 + 8 * v5);\n v7 = *v3;\n v8 = 0LL;\n do {\n v9 = v7;\n v7 = v3[v8 / 4 + 1];\n if (v7 <= v9) v9 = v3[v8 / 4 + 1];\n v3[v8 / 4] = *(uint32_t *)(v6 + v8) + v9;\n v8 += 4LL;\n } while (v8 != 4LL * (unsigned int)v5 + 4);\n --v5;\n } while ((int)v5 >= 0);\n }\n }\n v10 = *v3;\n free(v3);\n return v10;\n}" + }, + { + "index": 974, + "func_name": "func0", + "func_dep": "\n\n#include \n\n#include \n\n#include \n\n\n\n", + "func": "int func0(int** A, int rows) {\n int* memo = (int*)malloc(rows * sizeof(int));\n int n = rows - 1;\n for (int i = 0; i < rows; i++) {\n memo[i] = A[n][i];\n }\n for (int i = rows - 2; i >= 0; i--) {\n for (int j = 0; j <= i; j++) {\n int minValue = memo[j] < memo[j + 1] ? memo[j] : memo[j + 1];\n memo[j] = A[i][j] + minValue;\n }\n }\n int result = memo[0];\n free(memo);\n return result;\n}", + "test": "int main() {\n\n int a1[3][3] = {{2}, {3, 9}, {1, 6, 7}};\n\n int a2[3][3] = {{2}, {3, 7}, {8, 5, 6}};\n\n int a3[3][3] = {{3}, {6, 4}, {5, 2, 7}};\n\n\n\n int* pa1[3] = {a1[0], a1[1], a1[2]};\n\n int* pa2[3] = {a2[0], a2[1], a2[2]};\n\n int* pa3[3] = {a3[0], a3[1], a3[2]};\n\n\n\n assert(func0(pa1, 3) == 6);\n\n assert(func0(pa2, 3) == 10);\n\n assert(func0(pa3, 3) == 9);\n\n\n\n printf(\"All tests passed successfully.\\n\");\n\n\n\n return 0;\n\n}\n\n", + "opt": "O3", + "language": "c", + "asm": "func0:\nendbr64\npush %r12\npush %rbp\npush %rbx\nmov %rdi,%rbx\nmovslq %esi,%rdi\nmov %rdi,%rbp\nshl $0x2,%rdi\ncallq 10f0 \nmov %rax,%rdi\ntest %ebp,%ebp\njle 147c \nlea -0x1(%rbp),%eax\nmov %eax,%edx\ncltq\nmov (%rbx,%rax,8),%rsi\nlea 0x4(,%rdx,4),%rdx\ncallq 10e0 \nmov %rax,%rdi\nmov %ebp,%edx\nsub $0x2,%edx\njs 163f \nmovslq %edx,%rdx\nxor %r9d,%r9d\nnopl (%rax)\ntest %edx,%edx\nmov %r9d,%r8d\nmov (%rbx,%rdx,8),%rcx\ncmovns %edx,%r8d\nadd $0x1,%r8d\ncmp $0x2,%edx\njle 1650 \nmov %r8d,%esi\nxor %eax,%eax\nshr $0x2,%esi\nshl $0x4,%rsi\nnopw %cs:0x0(%rax,%rax,1)\nmovdqu 0x4(%rdi,%rax,1),%xmm2\nmovdqu (%rdi,%rax,1),%xmm0\nmovdqu (%rdi,%rax,1),%xmm3\nmovdqu (%rcx,%rax,1),%xmm4\npcmpgtd %xmm2,%xmm0\nmovdqa %xmm2,%xmm1\npand %xmm0,%xmm1\npandn %xmm3,%xmm0\npor %xmm1,%xmm0\npaddd %xmm4,%xmm0\nmovups %xmm0,(%rdi,%rax,1)\nadd $0x10,%rax\ncmp %rax,%rsi\njne 14c0 \nmov %r8d,%r10d\nand $0xfffffffc,%r10d\nand $0x3,%r8d\nje 1633 \nmovslq %r10d,%r12\nlea 0x1(%r10),%esi\nmov %edx,%r11d\nlea 0x0(,%r12,4),%rax\nlea (%rdi,%rax,1),%r8\ncmp %edx,%esi\njge 1658 \ncmp %edx,%r10d\njg 1658 \nmov 0x4(%rdi,%rax,1),%esi\ncmp %esi,(%r8)\nmov %esi,%ebp\ncmovle (%r8),%ebp\nadd (%rcx,%r12,4),%ebp\nmov %ebp,(%r8)\nmov 0x8(%rdi,%rax,1),%r8d\nlea 0x3(%r10),%ebp\ncmp %r8d,%esi\ncmovg %r8d,%esi\nadd 0x4(%rcx,%rax,1),%esi\nmov %esi,0x4(%rdi,%rax,1)\nlea 0x2(%r10),%esi\ncmp %ebp,%edx\njle 15c5 \nmov 0xc(%rdi,%rax,1),%esi\nlea 0x5(%r10),%ebp\ncmp %esi,%r8d\ncmovg %esi,%r8d\nadd 0x8(%rcx,%rax,1),%r8d\nmov %r8d,0x8(%rdi,%rax,1)\nmov 0x10(%rdi,%rax,1),%r8d\ncmp %r8d,%esi\ncmovg %r8d,%esi\nadd 0xc(%rcx,%rax,1),%esi\nmov %esi,0xc(%rdi,%rax,1)\nlea 0x4(%r10),%esi\ncmp %ebp,%edx\njle 15c5 \nmov 0x14(%rdi,%rax,1),%esi\ncmp %r8d,%esi\ncmovle %esi,%r8d\nadd 0x10(%rcx,%rax,1),%r8d\ncmp %esi,0x18(%rdi,%rax,1)\nmov %r8d,0x10(%rdi,%rax,1)\ncmovle 0x18(%rdi,%rax,1),%esi\nadd 0x14(%rcx,%rax,1),%esi\nmov %esi,0x14(%rdi,%rax,1)\nlea 0x6(%r10),%esi\nmovslq %esi,%r10\nadd $0x1,%r10\nlea 0x0(,%r10,4),%rax\nlea -0x4(%rdi,%rax,1),%rbp\nmov 0x0(%rbp),%r8d\ncmp %r8d,(%rdi,%r10,4)\ncmovle (%rdi,%r10,4),%r8d\nadd -0x4(%rcx,%rax,1),%r8d\nmov %r8d,0x0(%rbp)\nlea 0x1(%rsi),%r8d\ncmp %r11d,%r8d\njg 1633 \nlea (%rdi,%rax,1),%rbp\nmov 0x0(%rbp),%r8d\ncmp %r8d,0x4(%rdi,%rax,1)\ncmovle 0x4(%rdi,%rax,1),%r8d\nadd $0x2,%esi\nadd (%rcx,%r10,4),%r8d\nmov %r8d,0x0(%rbp)\ncmp %r11d,%esi\njg 1633 \nlea 0x4(%rdi,%rax,1),%r8\nmov (%r8),%esi\ncmp %esi,0x8(%rdi,%rax,1)\ncmovle 0x8(%rdi,%rax,1),%esi\nadd 0x4(%rcx,%rax,1),%esi\nmov %esi,(%r8)\nsub $0x1,%rdx\ntest %edx,%edx\njns 1490 \nmov (%rdi),%r12d\ncallq 10a0 \npop %rbx\npop %rbp\nmov %r12d,%eax\npop %r12\nretq\nxor %r10d,%r10d\njmpq 150b \nmov %r10d,%esi\njmpq 15c5 \n", + "ida_asm": "func0:\nendbr64\npush r14\npush r13\npush r12\npush rbp\nmov rbp, rdi\nmovsxd rdi, esi\npush rbx\nmov r12, rdi\nshl rdi, 2; size\ncall _malloc\nmov rdi, rax; dest\ntest r12d, r12d\njle loc_15D9\nlea ebx, [r12-1]\nmov edx, r12d\nmovsxd rax, ebx\nshl rdx, 2; n\nmov rsi, [rbp+rax*8+0]; src\ncall _memcpy\nlea esi, [r12-2]\nmov rdi, rax; ptr\ncmp r12d, 1\njz loc_15D9\nmovsxd rsi, esi\nnop dword ptr [rax+rax+00000000h]\nloc_1490:\nmov rcx, [rbp+rsi*8+0]\ncmp esi, 2\njbe loc_1680\nmov edx, ebx\nxor eax, eax\nshr edx, 2\nshl rdx, 4\nnop dword ptr [rax+00000000h]\nloc_14B0:\nmovdqu xmm2, xmmword ptr [rdi+rax+4]\nmovdqu xmm0, xmmword ptr [rdi+rax]\nmovdqu xmm3, xmmword ptr [rdi+rax]\nmovdqu xmm4, xmmword ptr [rcx+rax]\npcmpgtd xmm0, xmm2\nmovdqa xmm1, xmm2\npand xmm1, xmm0\npandn xmm0, xmm3\npor xmm0, xmm1\npaddd xmm0, xmm4\nmovups xmmword ptr [rdi+rax], xmm0\nadd rax, 10h\ncmp rdx, rax\njnz short loc_14B0\nmov eax, ebx\nand eax, 0FFFFFFFCh\ntest bl, 3\njz loc_15CA\nloc_14F8:\nmovsxd r13, eax\nlea edx, [rax+1]\nmov r10d, esi\nlea r8, ds:0[r13*4]\nlea r11, [rdi+r8]\ncmp edx, esi\njge short loc_1561\ncmp eax, esi\njg short loc_1561\nmov r14d, [rdi+r8+4]\nmov edx, [r11]\nlea r12, [rdi+r8+8]\nmov r9d, [r12]\nmovq xmm1, qword ptr [rcx+r13*4]\ncmp r14d, edx\ncmovle edx, r14d\ncmp r14d, r9d\ncmovg r14d, r9d\nmovd xmm0, edx\nlea edx, [rax+3]\nmovd xmm5, r14d\npunpckldq xmm0, xmm5\npaddd xmm0, xmm1\nmovq qword ptr [r11], xmm0\ncmp esi, edx\njg loc_15F0\nadd eax, 2\nlea edx, [rax+1]\nloc_1561:\nmovsxd r8, edx\nlea r9, ds:0[r8*4]\nlea r12, [rdi+r9-4]\nlea r11, [rdi+r9]\nmov edx, [r11]\nmov r13d, [r12]\ncmp edx, r13d\ncmovg edx, r13d\nadd edx, [rcx+r9-4]\nmov [r12], edx\ncmp eax, r10d\njge short loc_15CA\nmov edx, [rdi+r9+4]\nmov r12d, [r11]\ncmp edx, r12d\ncmovg edx, r12d\nadd eax, 2\nadd edx, [rcx+r8*4]\nmov [r11], edx\ncmp eax, r10d\njg short loc_15CA\nlea rdx, [rdi+r9+4]\nmov eax, [rdi+r9+8]\nmov r8d, [rdx]\ncmp eax, r8d\ncmovg eax, r8d\nadd eax, [rcx+r9+4]\nmov [rdx], eax\nloc_15CA:\nsub rsi, 1\nsub ebx, 1\ntest esi, esi\njns loc_1490\nloc_15D9:\nmov ebx, [rdi]\ncall _free\nmov eax, ebx\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_15F0:\nmov r13d, [rdi+r8+0Ch]\nlea r11, [rdi+r8+10h]\nmovq xmm1, qword ptr [rcx+r8+8]\nmov edx, [r11]\ncmp r9d, r13d\ncmovg r9d, r13d\ncmp r13d, edx\ncmovg r13d, edx\nmovd xmm0, r9d\nlea r9d, [rax+5]\nmovd xmm6, r13d\npunpckldq xmm0, xmm6\npaddd xmm1, xmm0\nmovq qword ptr [r12], xmm1\ncmp esi, r9d\njg short loc_1640\nadd eax, 4\nlea edx, [rax+1]\njmp loc_1561\nloc_1640:\nmov r9d, [rdi+r8+14h]\nmovq xmm1, qword ptr [rcx+r8+10h]\ncmp r9d, edx\ncmovle edx, r9d\nmovd xmm0, edx\nmov edx, [rdi+r8+18h]\ncmp r9d, edx\ncmovg r9d, edx\nadd eax, 6\nlea edx, [rax+1]\nmovd xmm7, r9d\npunpckldq xmm0, xmm7\npaddd xmm0, xmm1\nmovq qword ptr [r11], xmm0\njmp loc_1561\nloc_1680:\nxor eax, eax\njmp loc_14F8", + "ida_pseudo": "__int64 __fastcall func0(__int64 a1, int a2)\n{\n _DWORD *v4; // rdi\n unsigned int v5; // ebx\n _DWORD *v6; // rax\n __int64 v7; // rsi\n __int64 v8; // rcx\n __int64 v9; // rax\n __m128i v10; // xmm2\n __m128i v11; // xmm0\n signed int v12; // eax\n int v13; // edx\n __int64 v14; // r8\n unsigned int *v15; // r11\n signed int v16; // r14d\n unsigned int v17; // edx\n signed int *v18; // r12\n signed int v19; // r9d\n __m128i v20; // xmm1\n __int64 v21; // r8\n __int64 v22; // r9\n int *v23; // r12\n int *v24; // r11\n int v25; // edx\n int v26; // edx\n int *v27; // rdx\n int v28; // eax\n unsigned int v29; // ebx\n signed int v31; // r13d\n signed int *v32; // r11\n __m128i v33; // xmm1\n signed int v34; // edx\n signed int v35; // r9d\n __m128i v36; // xmm1\n __m128i v37; // xmm0\n\n v4 = malloc(4LL * a2);\n if ( a2 > 0 )\n {\n v5 = a2 - 1;\n v6 = memcpy(v4, *(const void **)(a1 + 8LL * (a2 - 1)), 4LL * (unsigned int)a2);\n LODWORD(v7) = a2 - 2;\n v4 = v6;\n if ( a2 != 1 )\n {\n v7 = (int)v7;\n while ( 1 )\n {\n v8 = *(_QWORD *)(a1 + 8 * v7);\n if ( (unsigned int)v7 <= 2 )\n break;\n v9 = 0LL;\n do\n {\n v10 = _mm_loadu_si128((const __m128i *)&v4[v9 + 1]);\n v11 = _mm_cmpgt_epi32(_mm_loadu_si128((const __m128i *)&v4[v9]), v10);\n *(__m128i *)&v4[v9] = _mm_add_epi32(\n _mm_or_si128(\n _mm_andnot_si128(v11, _mm_loadu_si128((const __m128i *)&v4[v9])),\n _mm_and_si128(v10, v11)),\n _mm_loadu_si128((const __m128i *)(v8 + v9 * 4)));\n v9 += 4LL;\n }\n while ( 4LL * (v5 >> 2) != v9 );\n v12 = v5 & 0xFFFFFFFC;\n if ( (v5 & 3) != 0 )\n goto LABEL_8;\nLABEL_25:\n --v7;\n --v5;\n if ( (int)v7 < 0 )\n goto LABEL_26;\n }\n v12 = 0;\nLABEL_8:\n v13 = v12 + 1;\n v14 = v12;\n v15 = &v4[v14];\n if ( v12 + 1 < (int)v7 && v12 <= (int)v7 )\n {\n v16 = v4[v14 + 1];\n v17 = *v15;\n v18 = &v4[v14 + 2];\n v19 = *v18;\n v20 = _mm_loadl_epi64((const __m128i *)(v8 + 4LL * v12));\n if ( v16 <= (int)*v15 )\n v17 = v4[v14 + 1];\n if ( v16 > v19 )\n v16 = *v18;\n *(_QWORD *)v15 = _mm_add_epi32(_mm_unpacklo_epi32(_mm_cvtsi32_si128(v17), _mm_cvtsi32_si128(v16)), v20).m128i_u64[0];\n if ( (int)v7 > v12 + 3 )\n {\n v31 = v4[v14 + 3];\n v32 = &v4[v14 + 4];\n v33 = _mm_loadl_epi64((const __m128i *)(v8 + v14 * 4 + 8));\n v34 = *v32;\n if ( v19 > v31 )\n v19 = v4[v14 + 3];\n if ( v31 > v34 )\n v31 = *v32;\n *(_QWORD *)v18 = _mm_add_epi32(v33, _mm_unpacklo_epi32(_mm_cvtsi32_si128(v19), _mm_cvtsi32_si128(v31))).m128i_u64[0];\n if ( (int)v7 > v12 + 5 )\n {\n v35 = v4[v14 + 5];\n v36 = _mm_loadl_epi64((const __m128i *)(v8 + v14 * 4 + 16));\n if ( v35 <= v34 )\n v34 = v4[v14 + 5];\n v37 = _mm_cvtsi32_si128(v34);\n if ( v35 > v4[v14 + 6] )\n v35 = v4[v14 + 6];\n v12 += 6;\n v13 = v12 + 1;\n *(_QWORD *)v32 = _mm_add_epi32(_mm_unpacklo_epi32(v37, _mm_cvtsi32_si128(v35)), v36).m128i_u64[0];\n }\n else\n {\n v12 += 4;\n v13 = v12 + 1;\n }\n }\n else\n {\n v12 += 2;\n v13 = v12 + 1;\n }\n }\n v21 = v13;\n v22 = v13;\n v23 = &v4[v22 - 1];\n v24 = &v4[v22];\n v25 = v4[v22];\n if ( v25 > *v23 )\n v25 = *v23;\n *v23 = *(_DWORD *)(v8 + v22 * 4 - 4) + v25;\n if ( v12 < (int)v7 )\n {\n v26 = v4[v22 + 1];\n if ( v26 > *v24 )\n v26 = *v24;\n *v24 = *(_DWORD *)(v8 + 4 * v21) + v26;\n if ( v12 + 2 <= (int)v7 )\n {\n v27 = &v4[v22 + 1];\n v28 = v4[v22 + 2];\n if ( v28 > *v27 )\n v28 = *v27;\n *v27 = *(_DWORD *)(v8 + v22 * 4 + 4) + v28;\n }\n }\n goto LABEL_25;\n }\n }\nLABEL_26:\n v29 = *v4;\n free(v4);\n return v29;\n}", + "ida_strip_asm": "sub_1430:\nendbr64\npush r14\npush r13\npush r12\npush rbp\nmov rbp, rdi\nmovsxd rdi, esi\npush rbx\nmov r12, rdi\nshl rdi, 2; size\ncall _malloc\nmov rdi, rax; dest\ntest r12d, r12d\njle loc_15D9\nlea ebx, [r12-1]\nmov edx, r12d\nmovsxd rax, ebx\nshl rdx, 2; n\nmov rsi, [rbp+rax*8+0]; src\ncall _memcpy\nlea esi, [r12-2]\nmov rdi, rax; ptr\ncmp r12d, 1\njz loc_15D9\nmovsxd rsi, esi\nnop dword ptr [rax+rax+00000000h]\nloc_1490:\nmov rcx, [rbp+rsi*8+0]\ncmp esi, 2\njbe loc_1680\nmov edx, ebx\nxor eax, eax\nshr edx, 2\nshl rdx, 4\nnop dword ptr [rax+00000000h]\nloc_14B0:\nmovdqu xmm2, xmmword ptr [rdi+rax+4]\nmovdqu xmm0, xmmword ptr [rdi+rax]\nmovdqu xmm3, xmmword ptr [rdi+rax]\nmovdqu xmm4, xmmword ptr [rcx+rax]\npcmpgtd xmm0, xmm2\nmovdqa xmm1, xmm2\npand xmm1, xmm0\npandn xmm0, xmm3\npor xmm0, xmm1\npaddd xmm0, xmm4\nmovups xmmword ptr [rdi+rax], xmm0\nadd rax, 10h\ncmp rdx, rax\njnz short loc_14B0\nmov eax, ebx\nand eax, 0FFFFFFFCh\ntest bl, 3\njz loc_15CA\nloc_14F8:\nmovsxd r13, eax\nlea edx, [rax+1]\nmov r10d, esi\nlea r8, ds:0[r13*4]\nlea r11, [rdi+r8]\ncmp edx, esi\njge short loc_1561\ncmp eax, esi\njg short loc_1561\nmov r14d, [rdi+r8+4]\nmov edx, [r11]\nlea r12, [rdi+r8+8]\nmov r9d, [r12]\nmovq xmm1, qword ptr [rcx+r13*4]\ncmp r14d, edx\ncmovle edx, r14d\ncmp r14d, r9d\ncmovg r14d, r9d\nmovd xmm0, edx\nlea edx, [rax+3]\nmovd xmm5, r14d\npunpckldq xmm0, xmm5\npaddd xmm0, xmm1\nmovq qword ptr [r11], xmm0\ncmp esi, edx\njg loc_15F0\nadd eax, 2\nlea edx, [rax+1]\nloc_1561:\nmovsxd r8, edx\nlea r9, ds:0[r8*4]\nlea r12, [rdi+r9-4]\nlea r11, [rdi+r9]\nmov edx, [r11]\nmov r13d, [r12]\ncmp edx, r13d\ncmovg edx, r13d\nadd edx, [rcx+r9-4]\nmov [r12], edx\ncmp eax, r10d\njge short loc_15CA\nmov edx, [rdi+r9+4]\nmov r12d, [r11]\ncmp edx, r12d\ncmovg edx, r12d\nadd eax, 2\nadd edx, [rcx+r8*4]\nmov [r11], edx\ncmp eax, r10d\njg short loc_15CA\nlea rdx, [rdi+r9+4]\nmov eax, [rdi+r9+8]\nmov r8d, [rdx]\ncmp eax, r8d\ncmovg eax, r8d\nadd eax, [rcx+r9+4]\nmov [rdx], eax\nloc_15CA:\nsub rsi, 1\nsub ebx, 1\ntest esi, esi\njns loc_1490\nloc_15D9:\nmov ebx, [rdi]\ncall _free\nmov eax, ebx\npop rbx\npop rbp\npop r12\npop r13\npop r14\nretn\nloc_15F0:\nmov r13d, [rdi+r8+0Ch]\nlea r11, [rdi+r8+10h]\nmovq xmm1, qword ptr [rcx+r8+8]\nmov edx, [r11]\ncmp r9d, r13d\ncmovg r9d, r13d\ncmp r13d, edx\ncmovg r13d, edx\nmovd xmm0, r9d\nlea r9d, [rax+5]\nmovd xmm6, r13d\npunpckldq xmm0, xmm6\npaddd xmm1, xmm0\nmovq qword ptr [r12], xmm1\ncmp esi, r9d\njg short loc_1640\nadd eax, 4\nlea edx, [rax+1]\njmp loc_1561\nloc_1640:\nmov r9d, [rdi+r8+14h]\nmovq xmm1, qword ptr [rcx+r8+10h]\ncmp r9d, edx\ncmovle edx, r9d\nmovd xmm0, edx\nmov edx, [rdi+r8+18h]\ncmp r9d, edx\ncmovg r9d, edx\nadd eax, 6\nlea edx, [rax+1]\nmovd xmm7, r9d\npunpckldq xmm0, xmm7\npaddd xmm0, xmm1\nmovq qword ptr [r11], xmm0\njmp loc_1561\nloc_1680:\nxor eax, eax\njmp loc_14F8", + "ida_strip_pseudo": "__int64 __fastcall sub_1430(__int64 a1, int a2)\n{\n _DWORD *v4; // rdi\n unsigned int v5; // ebx\n _DWORD *v6; // rax\n __int64 v7; // rsi\n __int64 v8; // rcx\n __int64 v9; // rax\n __m128i v10; // xmm2\n __m128i v11; // xmm0\n signed int v12; // eax\n int v13; // edx\n __int64 v14; // r8\n unsigned int *v15; // r11\n signed int v16; // r14d\n unsigned int v17; // edx\n signed int *v18; // r12\n signed int v19; // r9d\n __m128i v20; // xmm1\n __int64 v21; // r8\n __int64 v22; // r9\n int *v23; // r12\n int *v24; // r11\n int v25; // edx\n int v26; // edx\n int *v27; // rdx\n int v28; // eax\n unsigned int v29; // ebx\n signed int v31; // r13d\n signed int *v32; // r11\n __m128i v33; // xmm1\n signed int v34; // edx\n signed int v35; // r9d\n __m128i v36; // xmm1\n __m128i v37; // xmm0\n\n v4 = malloc(4LL * a2);\n if ( a2 > 0 )\n {\n v5 = a2 - 1;\n v6 = memcpy(v4, *(const void **)(a1 + 8LL * (a2 - 1)), 4LL * (unsigned int)a2);\n LODWORD(v7) = a2 - 2;\n v4 = v6;\n if ( a2 != 1 )\n {\n v7 = (int)v7;\n while ( 1 )\n {\n v8 = *(_QWORD *)(a1 + 8 * v7);\n if ( (unsigned int)v7 <= 2 )\n break;\n v9 = 0LL;\n do\n {\n v10 = _mm_loadu_si128((const __m128i *)&v4[v9 + 1]);\n v11 = _mm_cmpgt_epi32(_mm_loadu_si128((const __m128i *)&v4[v9]), v10);\n *(__m128i *)&v4[v9] = _mm_add_epi32(\n _mm_or_si128(\n _mm_andnot_si128(v11, _mm_loadu_si128((const __m128i *)&v4[v9])),\n _mm_and_si128(v10, v11)),\n _mm_loadu_si128((const __m128i *)(v8 + v9 * 4)));\n v9 += 4LL;\n }\n while ( 4LL * (v5 >> 2) != v9 );\n v12 = v5 & 0xFFFFFFFC;\n if ( (v5 & 3) != 0 )\n goto LABEL_8;\nLABEL_25:\n --v7;\n --v5;\n if ( (int)v7 < 0 )\n goto LABEL_26;\n }\n v12 = 0;\nLABEL_8:\n v13 = v12 + 1;\n v14 = v12;\n v15 = &v4[v14];\n if ( v12 + 1 < (int)v7 && v12 <= (int)v7 )\n {\n v16 = v4[v14 + 1];\n v17 = *v15;\n v18 = &v4[v14 + 2];\n v19 = *v18;\n v20 = _mm_loadl_epi64((const __m128i *)(v8 + 4LL * v12));\n if ( v16 <= (int)*v15 )\n v17 = v4[v14 + 1];\n if ( v16 > v19 )\n v16 = *v18;\n *(_QWORD *)v15 = _mm_add_epi32(_mm_unpacklo_epi32(_mm_cvtsi32_si128(v17), _mm_cvtsi32_si128(v16)), v20).m128i_u64[0];\n if ( (int)v7 > v12 + 3 )\n {\n v31 = v4[v14 + 3];\n v32 = &v4[v14 + 4];\n v33 = _mm_loadl_epi64((const __m128i *)(v8 + v14 * 4 + 8));\n v34 = *v32;\n if ( v19 > v31 )\n v19 = v4[v14 + 3];\n if ( v31 > v34 )\n v31 = *v32;\n *(_QWORD *)v18 = _mm_add_epi32(v33, _mm_unpacklo_epi32(_mm_cvtsi32_si128(v19), _mm_cvtsi32_si128(v31))).m128i_u64[0];\n if ( (int)v7 > v12 + 5 )\n {\n v35 = v4[v14 + 5];\n v36 = _mm_loadl_epi64((const __m128i *)(v8 + v14 * 4 + 16));\n if ( v35 <= v34 )\n v34 = v4[v14 + 5];\n v37 = _mm_cvtsi32_si128(v34);\n if ( v35 > v4[v14 + 6] )\n v35 = v4[v14 + 6];\n v12 += 6;\n v13 = v12 + 1;\n *(_QWORD *)v32 = _mm_add_epi32(_mm_unpacklo_epi32(v37, _mm_cvtsi32_si128(v35)), v36).m128i_u64[0];\n }\n else\n {\n v12 += 4;\n v13 = v12 + 1;\n }\n }\n else\n {\n v12 += 2;\n v13 = v12 + 1;\n }\n }\n v21 = v13;\n v22 = v13;\n v23 = &v4[v22 - 1];\n v24 = &v4[v22];\n v25 = v4[v22];\n if ( v25 > *v23 )\n v25 = *v23;\n *v23 = *(_DWORD *)(v8 + v22 * 4 - 4) + v25;\n if ( v12 < (int)v7 )\n {\n v26 = v4[v22 + 1];\n if ( v26 > *v24 )\n v26 = *v24;\n *v24 = *(_DWORD *)(v8 + 4 * v21) + v26;\n if ( v12 + 2 <= (int)v7 )\n {\n v27 = &v4[v22 + 1];\n v28 = v4[v22 + 2];\n if ( v28 > *v27 )\n v28 = *v27;\n *v27 = *(_DWORD *)(v8 + v22 * 4 + 4) + v28;\n }\n }\n goto LABEL_25;\n }\n }\nLABEL_26:\n v29 = *v4;\n free(v4);\n return v29;\n}", + "func_name_ori": "func0", + "ida_strip_pseudo_norm": "long long sub_1430(long long a1, int a2) {\n uint32_t *v4;\n unsigned int v5;\n uint32_t *v6;\n long long v7;\n long long v8;\n long long v9;\n __m128i v10;\n __m128i v11;\n signed int v12;\n int v13;\n long long v14;\n unsigned int *v15;\n signed int v16;\n unsigned int v17;\n signed int *v18;\n signed int v19;\n __m128i v20;\n long long v21;\n long long v22;\n int *v23;\n int *v24;\n int v25;\n int v26;\n int *v27;\n int v28;\n unsigned int v29;\n signed int v31;\n signed int *v32;\n __m128i v33;\n signed int v34;\n signed int v35;\n __m128i v36;\n __m128i v37;\n v4 = malloc(4LL * a2);\n if (a2 > 0) {\n v5 = a2 - 1;\n v6 = memcpy(v4, *(const void **)(a1 + 8LL * (a2 - 1)),\n 4LL * (unsigned int)a2);\n LODWORD(v7) = a2 - 2;\n v4 = v6;\n if (a2 != 1) {\n v7 = (int)v7;\n while (1) {\n v8 = *(uint64_t *)(a1 + 8 * v7);\n if ((unsigned int)v7 <= 2) break;\n v9 = 0LL;\n do {\n v10 = _mm_loadu_si128((const __m128i *)&v4[v9 + 1]);\n v11 = _mm_cmpgt_epi32(_mm_loadu_si128((const __m128i *)&v4[v9]), v10);\n *(__m128i *)&v4[v9] = _mm_add_epi32(\n _mm_or_si128(_mm_andnot_si128(\n v11, _mm_loadu_si128((const __m128i *)&v4[v9])),\n _mm_and_si128(v10, v11)),\n _mm_loadu_si128((const __m128i *)(v8 + v9 * 4)));\n v9 += 4LL;\n } while (4LL * (v5 >> 2) != v9);\n v12 = v5 & 4294967292;\n if ((v5 & 3) != 0) goto LABEL_8;\n LABEL_25:\n --v7;\n --v5;\n if ((int)v7 < 0) goto LABEL_26;\n }\n v12 = 0;\n LABEL_8:\n v13 = v12 + 1;\n v14 = v12;\n v15 = &v4[v14];\n if (v12 + 1 < (int)v7 && v12 <= (int)v7) {\n v16 = v4[v14 + 1];\n v17 = *v15;\n v18 = &v4[v14 + 2];\n v19 = *v18;\n v20 = _mm_loadl_epi64((const __m128i *)(v8 + 4LL * v12));\n if (v16 <= (int)*v15) v17 = v4[v14 + 1];\n if (v16 > v19) v16 = *v18;\n *(uint64_t *)v15 =\n _mm_add_epi32(_mm_unpacklo_epi32(_mm_cvtsi32_si128(v17),\n _mm_cvtsi32_si128(v16)),\n v20)\n .m128i_u64[0];\n if ((int)v7 > v12 + 3) {\n v31 = v4[v14 + 3];\n v32 = &v4[v14 + 4];\n v33 = _mm_loadl_epi64((const __m128i *)(v8 + v14 * 4 + 8));\n v34 = *v32;\n if (v19 > v31) v19 = v4[v14 + 3];\n if (v31 > v34) v31 = *v32;\n *(uint64_t *)v18 =\n _mm_add_epi32(v33, _mm_unpacklo_epi32(_mm_cvtsi32_si128(v19),\n _mm_cvtsi32_si128(v31)))\n .m128i_u64[0];\n if ((int)v7 > v12 + 5) {\n v35 = v4[v14 + 5];\n v36 = _mm_loadl_epi64((const __m128i *)(v8 + v14 * 4 + 16));\n if (v35 <= v34) v34 = v4[v14 + 5];\n v37 = _mm_cvtsi32_si128(v34);\n if (v35 > v4[v14 + 6]) v35 = v4[v14 + 6];\n v12 += 6;\n v13 = v12 + 1;\n *(uint64_t *)v32 =\n _mm_add_epi32(_mm_unpacklo_epi32(v37, _mm_cvtsi32_si128(v35)),\n v36)\n .m128i_u64[0];\n } else {\n v12 += 4;\n v13 = v12 + 1;\n }\n } else {\n v12 += 2;\n v13 = v12 + 1;\n }\n }\n v21 = v13;\n v22 = v13;\n v23 = &v4[v22 - 1];\n v24 = &v4[v22];\n v25 = v4[v22];\n if (v25 > *v23) v25 = *v23;\n *v23 = *(uint32_t *)(v8 + v22 * 4 - 4) + v25;\n if (v12 < (int)v7) {\n v26 = v4[v22 + 1];\n if (v26 > *v24) v26 = *v24;\n *v24 = *(uint32_t *)(v8 + 4 * v21) + v26;\n if (v12 + 2 <= (int)v7) {\n v27 = &v4[v22 + 1];\n v28 = v4[v22 + 2];\n if (v28 > *v27) v28 = *v27;\n *v27 = *(uint32_t *)(v8 + v22 * 4 + 4) + v28;\n }\n }\n goto LABEL_25;\n }\n }\nLABEL_26:\n v29 = *v4;\n free(v4);\n return v29;\n}", + "ida_pseudo_norm": "long long func0(long long a1, int a2) {\n uint32_t *v4;\n unsigned int v5;\n uint32_t *v6;\n long long v7;\n long long v8;\n long long v9;\n __m128i v10;\n __m128i v11;\n signed int v12;\n int v13;\n long long v14;\n unsigned int *v15;\n signed int v16;\n unsigned int v17;\n signed int *v18;\n signed int v19;\n __m128i v20;\n long long v21;\n long long v22;\n int *v23;\n int *v24;\n int v25;\n int v26;\n int *v27;\n int v28;\n unsigned int v29;\n signed int v31;\n signed int *v32;\n __m128i v33;\n signed int v34;\n signed int v35;\n __m128i v36;\n __m128i v37;\n v4 = malloc(4LL * a2);\n if (a2 > 0) {\n v5 = a2 - 1;\n v6 = memcpy(v4, *(const void **)(a1 + 8LL * (a2 - 1)),\n 4LL * (unsigned int)a2);\n LODWORD(v7) = a2 - 2;\n v4 = v6;\n if (a2 != 1) {\n v7 = (int)v7;\n while (1) {\n v8 = *(uint64_t *)(a1 + 8 * v7);\n if ((unsigned int)v7 <= 2) break;\n v9 = 0LL;\n do {\n v10 = _mm_loadu_si128((const __m128i *)&v4[v9 + 1]);\n v11 = _mm_cmpgt_epi32(_mm_loadu_si128((const __m128i *)&v4[v9]), v10);\n *(__m128i *)&v4[v9] = _mm_add_epi32(\n _mm_or_si128(_mm_andnot_si128(\n v11, _mm_loadu_si128((const __m128i *)&v4[v9])),\n _mm_and_si128(v10, v11)),\n _mm_loadu_si128((const __m128i *)(v8 + v9 * 4)));\n v9 += 4LL;\n } while (4LL * (v5 >> 2) != v9);\n v12 = v5 & 4294967292;\n if ((v5 & 3) != 0) goto LABEL_8;\n LABEL_25:\n --v7;\n --v5;\n if ((int)v7 < 0) goto LABEL_26;\n }\n v12 = 0;\n LABEL_8:\n v13 = v12 + 1;\n v14 = v12;\n v15 = &v4[v14];\n if (v12 + 1 < (int)v7 && v12 <= (int)v7) {\n v16 = v4[v14 + 1];\n v17 = *v15;\n v18 = &v4[v14 + 2];\n v19 = *v18;\n v20 = _mm_loadl_epi64((const __m128i *)(v8 + 4LL * v12));\n if (v16 <= (int)*v15) v17 = v4[v14 + 1];\n if (v16 > v19) v16 = *v18;\n *(uint64_t *)v15 =\n _mm_add_epi32(_mm_unpacklo_epi32(_mm_cvtsi32_si128(v17),\n _mm_cvtsi32_si128(v16)),\n v20)\n .m128i_u64[0];\n if ((int)v7 > v12 + 3) {\n v31 = v4[v14 + 3];\n v32 = &v4[v14 + 4];\n v33 = _mm_loadl_epi64((const __m128i *)(v8 + v14 * 4 + 8));\n v34 = *v32;\n if (v19 > v31) v19 = v4[v14 + 3];\n if (v31 > v34) v31 = *v32;\n *(uint64_t *)v18 =\n _mm_add_epi32(v33, _mm_unpacklo_epi32(_mm_cvtsi32_si128(v19),\n _mm_cvtsi32_si128(v31)))\n .m128i_u64[0];\n if ((int)v7 > v12 + 5) {\n v35 = v4[v14 + 5];\n v36 = _mm_loadl_epi64((const __m128i *)(v8 + v14 * 4 + 16));\n if (v35 <= v34) v34 = v4[v14 + 5];\n v37 = _mm_cvtsi32_si128(v34);\n if (v35 > v4[v14 + 6]) v35 = v4[v14 + 6];\n v12 += 6;\n v13 = v12 + 1;\n *(uint64_t *)v32 =\n _mm_add_epi32(_mm_unpacklo_epi32(v37, _mm_cvtsi32_si128(v35)),\n v36)\n .m128i_u64[0];\n } else {\n v12 += 4;\n v13 = v12 + 1;\n }\n } else {\n v12 += 2;\n v13 = v12 + 1;\n }\n }\n v21 = v13;\n v22 = v13;\n v23 = &v4[v22 - 1];\n v24 = &v4[v22];\n v25 = v4[v22];\n if (v25 > *v23) v25 = *v23;\n *v23 = *(uint32_t *)(v8 + v22 * 4 - 4) + v25;\n if (v12 < (int)v7) {\n v26 = v4[v22 + 1];\n if (v26 > *v24) v26 = *v24;\n *v24 = *(uint32_t *)(v8 + 4 * v21) + v26;\n if (v12 + 2 <= (int)v7) {\n v27 = &v4[v22 + 1];\n v28 = v4[v22 + 2];\n if (v28 > *v27) v28 = *v27;\n *v27 = *(uint32_t *)(v8 + v22 * 4 + 4) + v28;\n }\n }\n goto LABEL_25;\n }\n }\nLABEL_26:\n v29 = *v4;\n free(v4);\n return v29;\n}" + } +] \ No newline at end of file diff --git a/sk2decompile/evaluation/evaluate_exe.py b/sk2decompile/evaluation/evaluate_exe.py new file mode 100644 index 0000000..cbe17b6 --- /dev/null +++ b/sk2decompile/evaluation/evaluate_exe.py @@ -0,0 +1,70 @@ +import os +import json +import subprocess +import pandas as pd +from metrics.cal_execute_rate import execute_rate_main +import sys +import argparse +current_dir = os.path.dirname(os.path.abspath(__file__)) +def get_score(metric, json_file, opt, decompiler, language): + gen_results = [] + source_codes = [] + with open(json_file) as f: + json_obj = json.load(f) + datas = [data for data in json_obj if data['opt'] == opt and data['language'] == language] + if decompiler in ['ida','ghidra']: + for data in datas: + source_codes.append(data['func']) + gen_result = data[f'{decompiler}_pseudo'] + old_name = gen_result.split('(')[0].split(' ')[-1] + gen_result = gen_result.replace(old_name, data['func_name']) + gen_results.append(gen_result) + else: + for data in datas: + fileName = str(data['index']) + '_' + opt + jsonName = json_file.split('/')[-1].replace('.json','') + filePath = f'./model_outputs/{jsonName}/{decompiler}/{opt}/{fileName}.{data["language"]}' + if not os.path.exists(filePath): + code = '' + else: + with open(filePath) as file: + code = file.read() + gen_results.append(code) + source_codes.append(data['func']) + + for idx in range(len(gen_results)): + one = gen_results[idx] + func_name = one.split('(')[0].split(' ')[-1].strip() + if func_name.strip() and func_name[0:2] == '**': + func_name = func_name[2:] + elif func_name.strip() and func_name[0] == '*': + func_name = func_name[1:] + + one = one.replace(func_name, datas[idx]["func_name"]) + gen_results[idx] = one + else: + return execute_rate_main(datas,gen_results,language=language) + + +def eval(json_file, lan, decompilers, metrics): + optimal_level = ['O0', 'O1', 'O2', 'O3'] + for opt in optimal_level: + result = {'decompiler': decompilers} + output_name = json_file.split('/')[-1].split('.')[0] + '_' + lan + '_' + opt + '.csv' + for metric in metrics: + scores = [get_score(metric, json_file, opt, decompiler, lan) for decompiler in decompilers] + result[metric] = scores + df = pd.DataFrame(result) + df.to_csv(f'{current_dir}/results/{output_name}', index = False) + + +if __name__ == '__main__': + arg_parser = argparse.ArgumentParser() + arg_parser.add_argument("--json_file", type=str, default='./data/mbpp_normsrcpseudo.json') + arg_parser.add_argument("--language", type=str, default='c') + arg_parser.add_argument("--decompilers", type=str, default='gpt-5-mini-name7,idioms,lmdc6.7,pseudo2normFinal-Debug,pseudo2normFinal_RL-Debug,pseudo2norm_Final+norm2codeFinal-Debug-11000,pseudo2norm_RLFinal+norm2codeFinal-Debug-11000,pseudo2code_Final-3200-Debug') + arg_parser.add_argument("--metrics", type=str, default='exe_rate') + args = arg_parser.parse_args() + decompilers = args.decompilers.split(",") + metrics = args.metrics.split(",") + eval(args.json_file, args.language, decompilers, metrics) \ No newline at end of file diff --git a/sk2decompile/evaluation/evaluate_r2i.py b/sk2decompile/evaluation/evaluate_r2i.py new file mode 100644 index 0000000..8555605 --- /dev/null +++ b/sk2decompile/evaluation/evaluate_r2i.py @@ -0,0 +1,83 @@ +import json +import argparse +import os +from metrics.R2I.run import run_r2i +from inf_type import process_one +import warnings +import sys +import shutil +current_dir = os.path.dirname(os.path.abspath(__file__)) + +if __name__ == "__main__": + arg_parser = argparse.ArgumentParser() + arg_parser.add_argument("--json_file",type=str,default='./data/humaneval_normsrcpseudo.json') + arg_parser.add_argument("--decompilers", type=str, default='gpt-5-mini-name7,idioms,lmdc6.7,pseudo2norm_RLFinal+norm2codeFinal-Debug-11000') + arg_parser.add_argument("--output_path", type=str, default='./result/humaneval_normsrcpseudo') + arg_parser.add_argument("--generator", default="./psychec/psychecgen", help="Path to your generator executable") + arg_parser.add_argument("--solver", default="./psychec/psychecsolver-exe", help="Name of your solver (for `stack exec …`)") + args = arg_parser.parse_args() + + decompilers = args.decompilers.split(",") + if len(decompilers) < 2: + warnings.warn("To calculate the R2I metric, at least two decompilers are needed") + sys.exit(1) + + dataset = args.json_file.split('/')[-1].replace('.json','') + with open(args.json_file) as f: + datas = json.load(f) + datas = [data for data in datas if data['language'] == 'c'] + + shutil.rmtree(f'metrics/R2I/dataset/test') + for decompiler in decompilers: + os.makedirs(f'metrics/R2I/dataset/test/{decompiler}/c', exist_ok=True) + os.makedirs(f'metrics/R2I/dataset/test/{decompiler}/json', exist_ok=True) + os.makedirs(f'metrics/R2I/dataset/test/{decompiler}/syntax_correction', exist_ok=True) + opts = ["O0", "O1", "O2", "O3"] + for opt in opts: + names = [] + i = 0 + for data in datas: + if data['opt'] == opt: + func_name = data['func_name'] + index = data['index'] + names.append(func_name) + for decompiler in decompilers: + if not os.path.exists(f'./model_outputs/{dataset}/{decompiler}/{opt}/{index}_{opt}.c'): + prediction = '' + else: + with open(f'./model_outputs/{dataset}/{decompiler}/{opt}/{index}_{opt}.c') as f: + prediction = f.read().replace('__fastcall', '') + old_name = prediction.split('(')[0].split(' ')[-1].strip() + if old_name.strip() and old_name[0:2] == '**': + old_name = old_name[2:] + elif old_name.strip() and old_name[0] == '*': + old_name = old_name[1:] + prediction = prediction.replace(old_name, func_name) + if os.path.exists(f'./headers/{dataset}/{decompiler}/{opt}/{index}_{opt}.h'): + with open(f'./headers/{dataset}/{decompiler}/{opt}/{index}_{opt}.h') as f: + header = f.read() + else: + header = process_one(prediction, args.generator, args.solver) + if header: + prediction = header + prediction + prediction_json = {} + prediction_json['isStripped'] = True + prediction_json['decompilerName'] = decompiler + prediction_json['compilerName'] = 'gcc' + prediction_json['optLevel'] = "-O" + prediction_json['funcInfo'] = [{"funcName":func_name,"decompiledFuncCode":prediction}] + with open(f'metrics/R2I/dataset/test/{decompiler}/c/file{i}.c','w') as f: + f.write(prediction) + with open(f'metrics/R2I/dataset/test/{decompiler}/json/file{i}.json','w') as f: + json.dump(prediction_json, f, indent=4, ensure_ascii=False) + with open(f'metrics/R2I/dataset/test/{decompiler}/syntax_correction/file{i}.c','w') as f: + f.write(prediction) + i += 1 + + scores = run_r2i(decompilers, names) + os.chdir(current_dir) + os.makedirs(args.output_path, exist_ok=True) + with open(os.path.join(args.output_path, args.output_path.split('/')[-1]+'_results.txt'), 'a') as f: + for key in scores: + f.write(f'r2i {opt} {key}: {scores[key]*100:.2f}, ') + f.write("\n") \ No newline at end of file diff --git a/sk2decompile/evaluation/gpt_judge.py b/sk2decompile/evaluation/gpt_judge.py new file mode 100644 index 0000000..f8b5cdd --- /dev/null +++ b/sk2decompile/evaluation/gpt_judge.py @@ -0,0 +1,209 @@ +import openai +import json +import os +from concurrent.futures import ThreadPoolExecutor, as_completed +import time +import argparse + +current_dir = os.path.dirname(os.path.abspath(__file__)) + +scores_tmp = { + "Code Readability Assessment": { + "score": 1, + "rationale": "" + } +} + +def eval_func(write_path, input_prompt, api_key, max_retries=5, initial_delay=1): + openai.base_url = "https://api5.xhub.chat/v1/" + openai.api_key = api_key + delay = initial_delay + for attempt in range(max_retries): + try: + response = openai.chat.completions.create( + model="gpt-5-mini",#"gpt-4o",##"gpt-4o-mini",#"gpt-5", + messages=[{"role": "user", "content": input_prompt}], + max_tokens=8192, + temperature=0, + ) + answer = response.choices[0].message.content + if not isinstance(answer, str): + answer = response.choices[0].message.content[1]['text'] + + try: + txt = answer.strip() + txt = txt.replace("```json","").replace("```", "").strip() + score = json.loads(txt) + for score_name in scores_tmp: + score_one = score[score_name] + except Exception as e: + if "Expecting ',' delimiter" in str(e): + try: + txt = answer.strip() + txt = txt.replace("```json","").replace("```", "").strip()+'}' + score = json.loads(txt) + for score_name in scores_tmp: + score_one = score[score_name] + except Exception as e2: + raise ValueError() + elif "Invalid \\escape:" in str(e): + try: + txt = answer.strip() + txt = txt.replace("```json","").replace("```", "").strip().replace('\\','') + score = json.loads(txt) + for score_name in scores_tmp: + score_one = score[score_name] + except Exception as e2: + raise ValueError() + else: + raise ValueError() + break + except Exception as e: + if attempt < max_retries - 1: + # delay *= 2 + # print(f"Retrying in {delay} seconds...") + time.sleep(delay) + else: + answer = f"# Error during judge: {str(e)}" + print(answer) + + os.makedirs(os.path.dirname(write_path), exist_ok=True) + with open(write_path, 'w') as f: + f.write(txt) + + +def eval_score(json_file, decompiler, opt): + with open(json_file) as f: + datas = json.load(f) + datas = [data for data in datas if data['opt'] == opt] + + scores = {score_name: [] for score_name in scores_tmp} + for data in datas: + opt = data['opt'] + language = data['language'] + file_name = os.path.basename(json_file).replace('.json', '') + output_name = str(data['index']) + '_' + opt + score_path = f'{current_dir}/judge_outputs/{file_name}/{decompiler}/{opt}/{output_name}.{language}' + try: + with open(score_path, 'r') as f: + txt = f.read().strip() + txt = txt.replace("```json","").replace("```", "").strip() + score = json.loads(txt) + for score_name in scores: + score_one = score.get(score_name, {"score":1}) + scores[score_name].append(int(score_one["score"])) + except Exception as e: + if "Expecting ',' delimiter" in str(e): + try: + with open(score_path, 'r') as f: + txt = f.read().strip() + txt = txt.replace("```json","").replace("```", "").strip()+'}' + score = json.loads(txt) + for score_name in scores: + score_one = score.get(score_name, {"score":1}) + scores[score_name].append(int(score_one["score"])) + except Exception as e2: + print(f"Error loading score for {score_path}: {str(e2)}") + for score_name in scores: + scores[score_name].append(1) + elif "Invalid \\escape:" in str(e): + try: + with open(score_path, 'r') as f: + txt = f.read().strip() + txt = txt.replace("```json","").replace("```", "").strip().replace('\\','') + score = json.loads(txt) + for score_name in scores: + score_one = score.get(score_name, {"score":1}) + scores[score_name].append(int(score_one["score"])) + except Exception as e2: + print(f"Error loading score for {score_path}: {str(e2)}") + for score_name in scores: + scores[score_name].append(1) + else: + print(f"Error loading score for {score_path}: {str(e)}") + for score_name in scores: + scores[score_name].append(1) + return scores + +def eval_funcs(json_file, decompiler, prompt, opt, api_key): + tasks = [] + with open(json_file) as f: + datas = json.load(f) + datas = [data for data in datas if data['opt'] == opt] + + with ThreadPoolExecutor(max_workers=64) as executor: # 可根据实际情况调整线程数 + for data in datas: + opt = data['opt'] + func = data['func'] + func_name = func.split('(')[0].split(' ')[-1].strip() + if func_name.strip() and func_name[0:2] == '**': + func_name = func_name[2:] + elif func_name.strip() and func_name[0] == '*': + func_name = func_name[1:] + + func = func.replace(func_name, 'func0') + language = data['language'] + file_name = os.path.basename(json_file).replace('.json', '') + output_name = str(data['index']) + '_' + opt + decompile_path = f'./model_outputs/{file_name}/{decompiler}/{opt}/{output_name}.{language}' + try: + with open(decompile_path, 'r') as f: + decompile_result = f.read().strip() + except: + decompile_result = 'decompile error' + print(decompile_result) + input_prompt = prompt.replace('[SRC]', func).replace('[DSRC]', decompile_result) + write_path = f'{current_dir}/judge_outputs/{file_name}/{decompiler}/{opt}/{output_name}.{language}' + tasks.append(executor.submit(eval_func, write_path, input_prompt, api_key)) + + # 可选：等所有任务完成后进行处理或打印进度 + for future in as_completed(tasks): + future.result() # 捕获异常，确保所有任务完成 + +def main(): + arg_parser = argparse.ArgumentParser() + arg_parser.add_argument("--json_file",type=str,default='./data/humaneval_normsrcpseudo.json') + arg_parser.add_argument("--prompt",type=str,default='template.txt') + arg_parser.add_argument("--decompilers",type=str,default='gpt-5-mini-name7,idioms,lmdc6.7,pseudo2normFinal-Debug,pseudo2normFinal_RL-Debug,pseudo2norm_Final+norm2codeFinal-Debug-11000,pseudo2norm_RLFinal+norm2codeFinal-Debug-11000,pseudo2code_Final-3200') + arg_parser.add_argument("--cal_score",type=int,default=1) + arg_parser.add_argument("--opt",type=str,default='O0') + arg_parser.add_argument("--api_key",type=str) + args = arg_parser.parse_args() + with open(args.prompt, 'r') as f: + prompt = f.read() + decompilers = args.decompilers.split(",") + opt = args.opt + if args.cal_score == 0: + for decompiler in decompilers: + eval_funcs(args.json_file, decompiler, prompt) + if args.cal_score == 1: + scores = {} + scores_str = f'{opt}:\n' + file_name = os.path.basename(args.json_file).replace('.json', '') + for decompiler in decompilers: + eval_funcs(args.json_file, decompiler, prompt, opt, args.api_key) + scores[decompiler] = eval_score(args.json_file, decompiler, opt) + score_string = f'{decompiler}:' + for socre_key in scores[decompiler]: + score_list = scores[decompiler][socre_key] + score_string += f'{socre_key}:{sum(score_list)/len(score_list):.2f};' + print(score_string) + scores_str += score_string+'\n' + with open(f'{current_dir}/{file_name}_gpt5minijudge_src.txt', 'w') as f: + f.write(scores_str) + if args.cal_score == 2: + scores = {} + scores_str = '' + file_name = os.path.basename(args.json_file).replace('.json', '') + for decompiler in decompilers: + scores[decompiler] = eval_score(args.json_file, decompiler, opt) + score_string = f'{decompiler}:' + for socre_key in scores[decompiler]: + score_list = scores[decompiler][socre_key] + score_string += f'{socre_key}:{sum(score_list)/len(score_list):.2f};' + print(score_string) + scores_str += score_string+'\n' + with open(f'{current_dir}/{file_name}_gpt5minijudge.txt', 'w') as f: + f.write(scores_str) +if __name__ == '__main__': + main() diff --git a/sk2decompile/evaluation/inf_type.py b/sk2decompile/evaluation/inf_type.py new file mode 100644 index 0000000..1ab21d1 --- /dev/null +++ b/sk2decompile/evaluation/inf_type.py @@ -0,0 +1,170 @@ +import os +import sys +import json +import tempfile +import subprocess +from functools import partial +from tqdm import tqdm +import argparse +def process_one(sample_src, generator, solver): + """ + Write sample_src to temp file (sample.c), + run generator -> sample.cstr, + run solver -> sample.h, + read header, return header text. + Any temp files are cleaned up automatically. + """ + with tempfile.TemporaryDirectory() as tmpdir: + sample_path = os.path.join(tmpdir, "sample.c") + output_path = os.path.join(tmpdir, "sample.cstr") + header_path = os.path.join(tmpdir, "sample.h") + + # 1) dump the C‐source + with open(sample_path, "w", encoding="utf-8") as f: + f.write(sample_src) + + try: + # 2) run the generator + subprocess.run( + [generator, sample_path, "-o", output_path], + check=True, + stdout=subprocess.PIPE, + stderr=subprocess.PIPE, + timeout=1, + ) + # 3) run the solver + subprocess.run( + ["stack", "exec", solver, "--", "-i", output_path, "-o", header_path], + check=True, + stdout=subprocess.PIPE, + stderr=subprocess.PIPE, + timeout=1, + ) + + # 4) read back the .h + with open(header_path, "r", encoding="utf-8") as f: + return f.read() + + # except subprocess.CalledProcessError as e: + # sys.stderr.write( + # f"[ERROR] sample failed:\n" + # f" cmd: {e.cmd!r}\n" + # f" returncode: {e.returncode}\n" + # f" stdout: {e.stdout.decode(errors='ignore')}\n" + # f" stderr: {e.stderr.decode(errors='ignore')}\n" + # ) + except Exception as e: + return None + + +def main(): + p = argparse.ArgumentParser(description="Batch‐process C samples into headers.") + p.add_argument("--input_json", default="train_norm.json", help="Path to JSON file with a list of {{'code': …}} entries") + p.add_argument("--output_name", default="train_type", help="Where to write the augmented JSON") + p.add_argument("--generator", default="/psychec/psychecgen", help="Path to your generator executable") + p.add_argument("--solver", default="/psychec/psychecsolver-exe", help="Name of your solver (for `stack exec …`)") + p.add_argument("--split", type=int, default=5, help="split the data to split parts") + p.add_argument("--idx", type=int, default=0, help="index of the split") + args = p.parse_args() + + # load + with open(args.input_json, "r", encoding="utf-8") as f: + samples = json.load(f) + + if args.split != 0: + SPLIT = int(len(samples) / args.split) + if args.idx == args.split - 1: + samples = samples[SPLIT * args.idx:] + else: + samples = samples[SPLIT * args.idx:SPLIT * (args.idx + 1)] + + # pull out all the code‐strings + codes = [s["code_format"] for s in samples]############# code norm is the final expectation + + # prepare a partial that only needs the code + worker = partial(process_one, generator=args.generator, solver=args.solver) + + memo = {} + results = [] + count_non = 0 + for code in tqdm(codes): + if code not in memo: + header = worker(code) + if header == None: + count_non += 1 + memo[code] = header + results.append(memo[code]) + if len(results) % 5000 == 0: + print(f"len code:{len(codes)}, fail:{count_non}") + + for sample, header in zip(samples, results): + sample["header"] = header + + # dump out + with open(args.output_name+'_'+str(args.idx)+'.json', "w", encoding="utf-8") as f: + json.dump(samples, f, indent=2) + print(f"len code:{len(codes)}, fail:{count_non}") + +def folder(): + p = argparse.ArgumentParser(description="Batch‐process C samples into headers.") + p.add_argument("--input_folder", default="/workspace/llm4binary/type/evaluation/result/exebench-8800_github1000") + # p.add_argument("--output_name", default="train_type", help="Where to write the augmented JSON") + p.add_argument("--generator", default="./psychec/psychecgen", help="Path to your generator executable") + p.add_argument("--solver", default="./psychec/psychecsolver-exe", help="Name of your solver (for `stack exec …`)") + # p.add_argument("--split", type=int, default=5, help="split the data to split parts") + # p.add_argument("--idx", type=int, default=0, help="index of the split") + args = p.parse_args() + worker = partial(process_one, generator=args.generator, solver=args.solver) + good = 0 + bad = 1 + for root, dirs, files in tqdm(os.walk(args.input_folder)): + for filename in files: + if filename.endswith(".c"): + file_path = os.path.join(root, filename) + with open(file_path, 'r') as f: + code = f.read() + header = worker(code) + with open(file_path.split('.c')[0] + ".h", 'w') as f: + if header: + good += 1 + f.write(header) + else: + bad += 1 + print(f'good:{good},bad:{bad}') + f.write("") + +def jsonfile(): + p = argparse.ArgumentParser(description="Batch‐process C samples into headers.") + p.add_argument("--input_json", default="/workspace/llm4binary/type/evaluation/data/github2025_normsrcpseudo.json") + p.add_argument("--output_json", default="/workspace/llm4binary/type/evaluation/data/github2025_normsrcpseudo_type.json") + # p.add_argument("--output_name", default="train_type", help="Where to write the augmented JSON") + p.add_argument("--generator", default="./psychec/psychecgen", help="Path to your generator executable") + p.add_argument("--solver", default="./psychec/psychecsolver-exe", help="Name of your solver (for `stack exec …`)") + # p.add_argument("--split", type=int, default=5, help="split the data to split parts") + # p.add_argument("--idx", type=int, default=0, help="index of the split") + args = p.parse_args() + worker = partial(process_one, generator=args.generator, solver=args.solver) + + with open(args.input_json, 'r') as f: + data = json.load(f) + data_good = [] + for one in tqdm(data): + code = one['func'] + header = worker(code) + if header: + one['func_dep'] = header + data_good.append(one) + # else: + # one['func_dep'] = '' + with open(args.output_json, 'w') as f: + json.dump(data_good, f, indent=4) + +if __name__ == "__main__": + jsonfile() + # folder() + # main() + + + +# ../psychec/psychecgen ./output/ori/3.c -o ./output/cstr/3.cstr +# stack exec ../psychec/psychecsolver-exe -- -i ./output/cstr/3.cstr -o ./output/header/3.h diff --git a/sk2decompile/evaluation/metrics/cal_execute_rate.py b/sk2decompile/evaluation/metrics/cal_execute_rate.py new file mode 100644 index 0000000..3bc62aa --- /dev/null +++ b/sk2decompile/evaluation/metrics/cal_execute_rate.py @@ -0,0 +1,102 @@ +#apt-get update +#apt-get install -y libboost-dev libssl-dev +import subprocess +import os +import json +# from loguru import logger +import traceback +from argparse import ArgumentParser +import sys +from tqdm import tqdm +import multiprocessing +import tempfile +import numpy as np + +# logger.add(sys.stdout, colorize=False, format="{time} {level} {message}") + +current_dir = os.path.dirname(os.path.abspath(__file__)) + +def execute_rate(func_dep, func, func_test=None, timeout=10, language='cpp', opt="-O0"): + flag_exe = 0 + flag_comp = 0 + + if func_test!=None: + func_exe = func_dep + "\n" + func + "\n" + func_test + else: + func_comp = func_dep + "\n" + func # no test, only compile + + with tempfile.TemporaryDirectory() as temp_dir: + pid = os.getpid() + file_exe = os.path.join(temp_dir, f"exe_{pid}.c") + binary_exe = os.path.join(temp_dir, f"exe_{pid}") + with open(file_exe, "w") as f: + f.write(func_exe) + # Compile the C program to an executable + if language == 'cpp': + + if func_test!=None: + compile_command = ["g++", opt, '-std=c++17', file_exe, "-o", binary_exe, "-lm", "-lcrypto"] + else: + compile_command = ["g++", opt, '-S', '-std=c++17', file_exe, "-o", binary_exe, "-lm", "-lcrypto"] # only compile + else: + if func_test!=None: + compile_command = ["gcc", opt, file_exe, "-o", binary_exe, "-lm"] + else: + compile_command = ["gcc", opt, '-S', file_exe, "-o", binary_exe, "-lm"] # only compile + + try: + subprocess.run(compile_command, check=True, timeout=timeout) + flag_comp = 1 + except: + return flag_comp, flag_exe + + if func_test==None: + return flag_comp, flag_exe + + # Run the compiled executable + run_command = [binary_exe] + try: + process = subprocess.run(run_command, timeout=timeout, check=True) + flag_exe = 1 + except: + # print(func) + if "process" in locals() and process: + process.kill() + process.wait() + return flag_comp, flag_exe + return flag_comp, flag_exe + +def wrapper_func(args): + # Unpack arguments and call the original function + return execute_rate(*args) +def execute_rate_main(testsets, gen_results, num_workers=20, timeout=10, language='cpp', opt="-O0"): + with multiprocessing.Pool(num_workers) as pool: + tasks = [[testset["func_dep"], gen_result, testset["test"],\ + timeout, language, opt] + for testset, gen_result in zip(testsets, gen_results) + ] + eval_results = list(tqdm(pool.imap(wrapper_func, tasks), total=len(tasks))) + + comp, exe = zip(*eval_results) + return sum(exe) / len(exe) + + +if __name__ == "__main__": + + with open('/workspace/llm4binary/benchmark/data/humaneval-c-processed_20250402_2014.json','r') as f: + json_new = json.load(f) + + test_dir = '/workspace/llm4binary/benchmark/text/llm4decompile-1.3b-v1.5-humaneval-c-vllm-ori' + exe_all = [] + for i in [0,1,2,3]: + gen_results = [] + for j in range(164): + with open(os.path.join(test_dir, str(j*4+i)+'.c'), 'r') as f: + gen_results.append(f.read().strip()) + eval_results, comp, exe = execute_rate_main(json_new, gen_results, num_workers=32, timeout=10, language='c', opt="-O0") + + exe_all.append(exe) + for i in [0,1,2,3]: + print(f'opt={i}, rate:{exe_all[i]/164.0}') + + diff --git a/sk2decompile/evaluation/stack.yaml b/sk2decompile/evaluation/stack.yaml new file mode 100644 index 0000000..28901bd --- /dev/null +++ b/sk2decompile/evaluation/stack.yaml @@ -0,0 +1,66 @@ +# This file was automatically generated by 'stack init' +# +# Some commonly used options have been documented as comments in this file. +# For advanced use and comprehensive documentation of the format, please see: +# https://docs.haskellstack.org/en/stable/yaml_configuration/ + +# Resolver to choose a 'specific' stackage snapshot or a compiler version. +# A snapshot resolver dictates the compiler version and the set of packages +# to be used for project dependencies. For example: +# +# resolver: lts-3.5 +# resolver: nightly-2015-09-21 +# resolver: ghc-7.10.2 +# +# The location of a snapshot can be provided as a file or url. Stack assumes +# a snapshot provided as a file might change, whereas a url resource does not. +# +# resolver: ./custom-snapshot.yaml +# resolver: https://example.com/snapshots/2018-01-01.yaml +resolver: lts-5.1 + +# User packages to be built. +# Various formats can be used as shown in the example below. +# +# packages: +# - some-directory +# - https://example.com/foo/bar/baz-0.0.2.tar.gz +# subdirs: +# - auto-update +# - wai +packages: +- '.' +# Dependency packages to be pulled from upstream that are not in the resolver. +# These entries can reference officially published versions as well as +# forks / in-progress versions pinned to a git hash. For example: +# +# extra-deps: +# - acme-missiles-0.3 +# - git: https://github.com/commercialhaskell/stack.git +# commit: e7b331f14bcffb8367cd58fbfc8b40ec7642100a +# +# extra-deps: [] + +# Override default flag values for local packages and extra-deps +# flags: {} + +# Extra package databases containing global packages +# extra-package-dbs: [] + +# Control whether we use the GHC we find on the path +# system-ghc: true +# +# Require a specific version of stack, using version ranges +# require-stack-version: -any # Default +# require-stack-version: ">=2.1" +# +# Override the architecture used by stack, especially useful on Windows +# arch: i386 +# arch: x86_64 +# +# Extra directories used by stack for building +# extra-include-dirs: [/path/to/dir] +# extra-lib-dirs: [/path/to/dir] +# +# Allow a newer minor version of GHC than the snapshot specifies +# compiler-check: newer-minor diff --git a/sk2decompile/evaluation/template.txt b/sk2decompile/evaluation/template.txt new file mode 100644 index 0000000..da93b3e --- /dev/null +++ b/sk2decompile/evaluation/template.txt @@ -0,0 +1,74 @@ +You are an expert reverse engineering analyst tasked with evaluating LLM decompiler performance. You will receive source code and its decompiled version, then assess the readability of the decompiler's output. + +For each criterion, provide: +1. An integer score from 1 (very poor) to 5 (excellent) +2. A concise 1-2 sentence rationale + +**Input Format:** +1. Original Function +[SRC] + +2. Decompiled Function +[DSRC] + +**Scoring guidance:** + +**1 — Very Poor** + +1.1 Function, variable, and field names are meaningless (e.g., `func1`, `var1`, `field_4`). + +1.2 Names do not reflect their semantic roles (e.g., a counter named `ptr2`). + +1.3 Types are missing or collapsed into raw pointers/integers, with no sign of higher-level structures. + +1.4 Access patterns are opaque (e.g., complex pointer arithmetic instead of `arr[i]` or `obj.field`). + +**2 — Poor** + +2.1 Some identifiers exist, but remain generic and uninformative. + +2.2 Type information is partially present, but arrays, structs, or objects are poorly reconstructed. + +2.3 Code is slightly more readable than raw disassembly, yet the correspondence to source-level abstractions is weak. + +**3 — Fair** + +3.1 Function and variable names are somewhat descriptive, though often inconsistent or too generic. + +3.2 Basic type recovery exists: arrays, pointers, and simple structs are recognizable. + +3.3 Field and array access are partly reconstructed, but may still fall back to pointer arithmetic in places. + +3.4 Readability is acceptable, but requires effort to interpret correctly. + +**4 — Good** + +4.1 Names are meaningful, semantically relevant, and generally consistent with their roles. + +4.2 Structs, arrays, and object types are restored in a way close to natural source code. + +4.3 Field and array access is mostly clean and human-readable (`obj.field`, `arr[i]`). + +4.4 Overall readability is high, though not fully equivalent to carefully written source code. + +**5 — Excellent** + +5.1 Function, variable, and type names are clear, natural, and semantically accurate. + +5.2 Type recovery is faithful, with well-structured classes, structs, and arrays that match typical source-level abstractions. + +5.3 Field access and indexing are intuitive and entirely free of unnecessary pointer arithmetic. + +5.4 The recovered code feels almost indistinguishable from human-written source, with excellent overall readability. + +**Output Format:** +Provide only a valid JSON object with exactly these two fields: + +```json +{ + "Code Readability Assessment": { + "score": , + "rationale": "" + } +} +Output only the JSON object without additional commentary. \ No newline at end of file diff --git a/sk2decompile/verl/.gemini/config.yaml b/sk2decompile/verl/.gemini/config.yaml new file mode 100644 index 0000000..66015ad --- /dev/null +++ b/sk2decompile/verl/.gemini/config.yaml @@ -0,0 +1,10 @@ +have_fun: false +code_review: + disable: false + comment_severity_threshold: HIGH + max_review_comments: -1 + pull_request_opened: + help: false + summary: false + code_review: true +ignore_patterns: [] diff --git a/sk2decompile/verl/.github/CODEOWNERS b/sk2decompile/verl/.github/CODEOWNERS new file mode 100644 index 0000000..ce4fff8 --- /dev/null +++ b/sk2decompile/verl/.github/CODEOWNERS @@ -0,0 +1,18 @@ +/docs @eric-haibin-lin @zhaochenyang20 @hongpeng-guo +/docs/amd_tutorial @yushengsu-thu +/docs/slang_multiturn @zhaochenyang20 @SwordFaith + +/recipe/dapo @tongyx361 @PeterSH6 +/recipe/spin @zhaochenyang20 +/recipe/sppo @zhaochenyang20 + +/third_party/sglang @zhaochenyang20 @SwordFaith +/third_party/vllm @PeterSH6 @wuxibin89 +/verl/single_controller @zw0610 @wuxibin89 +/verl/trainer @eric-haibin-lin @vermouth1992 @tongyx361 @PeterSH6 +/verl/workers/rollout/vllm_rollout @wuxibin89 @PeterSH6 @chenhaiq +/verl/workers/rollout/sglang_rollout @zhaochenyang20 @SwordFaith @chenhaiq + +/tests/single_controller @zw0610 @wuxibin89 +/tests/trainer @eric-haibin-lin @vermouth1992 @tongyx361 @PeterSH6 +/tests/workers/rollout/vllm_rollout @wuxibin89 @PeterSH6 @chenhaiq diff --git a/sk2decompile/verl/.github/PULL_REQUEST_TEMPLATE.md b/sk2decompile/verl/.github/PULL_REQUEST_TEMPLATE.md new file mode 100644 index 0000000..96f6641 --- /dev/null +++ b/sk2decompile/verl/.github/PULL_REQUEST_TEMPLATE.md @@ -0,0 +1,40 @@ +### What does this PR do? + +> Add **concise** overview of what this PR aims to achieve or accomplish. Reference related GitHub issues and PRs that help with the review. + +### Checklist Before Starting + +- [ ] Search for similar PRs. Paste at least one query link here: ... +- [ ] Format the PR title as `[{modules}] {type}: {description}` (This will be checked by the CI) + - `{modules}` include `fsdp`, `megatron`, `sglang`, `vllm`, `rollout`, `trainer`, `ci`, `training_utils`, `recipe`, `hardware`, `deployment`, `ray`, `worker`, `single_controller`, `misc`, `perf`, `model`, `algo`, `env`, `tool`, `ckpt`, `doc`, `data` + - If this PR involves multiple modules, separate them with `,` like `[megatron, fsdp, doc]` + - `{type}` is in `feat`, `fix`, `refactor`, `chore`, `test` + - If this PR breaks any API (CLI arguments, config, function signature, etc.), add `[BREAKING]` to the beginning of the title. + - Example: `[BREAKING][fsdp, megatron] feat: dynamic batching` + +### Test + +> For changes that can not be tested by CI (e.g., algorithm implementation, new model support), validate by experiment(s) and show results like training curve plots, evaluation results, etc. + +### API and Usage Example + +> Demonstrate how the API changes if any, and provide usage example(s) if possible. + +```python +# Add code snippet or script demonstrating how to use this +``` + +### Design & Code Changes + +> Demonstrate the high-level design if this PR is complex, and list the specific changes. + +### Checklist Before Submitting + +> [!IMPORTANT] +> Please check all the following items before requesting a review, otherwise the reviewer might deprioritize this PR for review. + +- [ ] Read the [Contribute Guide](https://github.com/volcengine/verl/blob/main/CONTRIBUTING.md). +- [ ] Apply [pre-commit checks](https://github.com/volcengine/verl/blob/main/CONTRIBUTING.md#code-linting-and-formatting): `pre-commit install && pre-commit run --all-files --show-diff-on-failure --color=always` +- [ ] Add / Update [the documentation](https://github.com/volcengine/verl/tree/main/docs). +- [ ] Add unit or end-to-end test(s) to [the CI workflow](https://github.com/volcengine/verl/tree/main/.github/workflows) to cover all the code. If not feasible, explain why: ... +- [ ] Once your PR is ready for CI, send a message in [the `ci-request` channel](https://verl-project.slack.com/archives/C091TCESWB1) in [the `verl` Slack workspace](https://join.slack.com/t/verl-project/shared_invite/zt-3855yhg8g-CTkqXu~hKojPCmo7k_yXTQ). diff --git a/sk2decompile/verl/.github/dependabot.yml b/sk2decompile/verl/.github/dependabot.yml new file mode 100644 index 0000000..24a3571 --- /dev/null +++ b/sk2decompile/verl/.github/dependabot.yml @@ -0,0 +1,9 @@ +## Enabled the dependabot to check the dependencies of the project +## Dependabot will open pull requests to update dependencies automatically + +version: 2 +updates: + - package-ecosystem: pip + directory: "/" + schedule: + interval: weekly \ No newline at end of file diff --git a/sk2decompile/verl/.github/workflows/README.md b/sk2decompile/verl/.github/workflows/README.md new file mode 100644 index 0000000..41aa570 --- /dev/null +++ b/sk2decompile/verl/.github/workflows/README.md @@ -0,0 +1,68 @@ +### Adding a New Workflow + +When adding a new workflow for continuous integration (CI), you have two runner options: a fixed runner or a machine from the vemlp. + +- **Fixed Runner**: To use a fixed runner, specify it in your workflow using the `runs-on` keyword, like `runs-on: [L20x8]`. +- **Vemlp Runner**: Opting for a Vemlp machine allows you to launch tasks elastically. + +Here is a template to assist you. This template is designed for using Vemlp machines. Currently, for each workflow, you need to create a `setup` and a `cleanup` job. When using this template, the main parts you need to modify are the `IMAGE` environment variable and the specific `job steps`. + +```yaml +name: Your Default Workflow + +on: + push: + branches: + - main + - v0.* + pull_request: + branches: + - main + - v0.* + paths: + - "**/*.py" + - ".github/workflows/template.yml" + +concurrency: + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: ${{ github.ref != 'refs/heads/main' }} + +permissions: + contents: read + +env: + IMAGE: "your vemlp image" # e.g. "verl-ci-cn-beijing.cr.volces.com/verlai/verl:app-verl0.4-vllm0.8.5-mcore0.12.1" + DYNAMIC_RUNNER_URL: "https://sd10g3clalm04ug7alq90.apigateway-cn-beijing.volceapi.com/runner" # public veFaas api + +jobs: + setup: + runs-on: ubuntu-latest + outputs: + runner-label: ${{ steps.create-runner.outputs.runner-label }} + task-id: ${{ steps.create-runner.outputs.task-id }} + steps: + - uses: actions/checkout@v4 + - id: create-runner + uses: volcengine/vemlp-github-runner@v1 + with: + mode: "create" + faas-url: "${{ env.DYNAMIC_RUNNER_URL }}" + image: "${{ env.DEFAULT_IMAGE }}" + + your_job: + needs: setup + runs-on: ["${{ needs.setup.outputs.runner-label || 'default-runner' }}"] + steps: + xxxx # your jobs + + cleanup: + runs-on: ubuntu-latest + needs: [setup, your_job] + if: always() + steps: + - id: destroy-runner + uses: volcengine/vemlp-github-runner@v1 + with: + mode: "destroy" + faas-url: "${{ env.DYNAMIC_RUNNER_URL }}" + task-id: "${{ needs.setup.outputs.task-id }}" \ No newline at end of file diff --git a/sk2decompile/verl/.github/workflows/check-pr-title.yml b/sk2decompile/verl/.github/workflows/check-pr-title.yml new file mode 100644 index 0000000..948ce5e --- /dev/null +++ b/sk2decompile/verl/.github/workflows/check-pr-title.yml @@ -0,0 +1,58 @@ +# # Tests layout + +# Each folder under tests/ corresponds to a test category for a sub-namespace in verl. For instance: +# - `tests/trainer` for testing functionality related to `verl/trainer` +# - `tests/models` for testing functionality related to `verl/models` +# - ... + +# There are a few folders with `special_` prefix, created for special purposes: +# - `special_distributed`: unit tests that must run with multiple GPUs +# - `special_e2e`: end-to-end tests with training/generation scripts +# - `special_npu`: tests for NPUs +# - `special_sanity`: a suite of quick sanity tests +# - `special_standalone`: a set of test that are designed to run in dedicated environments + +# Accelerators for tests +# - By default tests are run with GPU available, except for the ones under `special_npu`, and any test script whose name ends with `on_cpu.py`. +# - For test scripts with `on_cpu.py` name suffix would be tested on CPU resources in linux environment. + +# # Workflow layout + +# All CI tests are configured by yaml files in `.github/workflows/`. Here's an overview of all test configs: +# 1. A list of always triggered CPU sanity tests: `check-pr-title.yml`, `secrets_scan.yml`, `check-pr-title,yml`, `pre-commit.yml`, `doc.yml` +# 2. Some heavy multi-GPU unit tests, such as `model.yml`, `vllm.yml`, `sgl.yml` +# 3. End-to-end tests: `e2e_*.yml` +# 4. Unit tests +# - `cpu_unit_tests.yml`, run pytest on all scripts with file name pattern `tests/**/test_*_on_cpu.py` +# - `gpu_unit_tests.yml`, run pytest on all scripts with file without the `on_cpu.py` suffix. +# - Since cpu/gpu unit tests by default runs all tests under `tests`, please make sure tests are manually excluded in them when +# - new workflow yaml is added to `.github/workflows` +# - new tests are added to workflow mentioned in 2. + + +on: + pull_request: + types: [opened, edited, synchronize] + +jobs: + check-title: + runs-on: ubuntu-latest + steps: + - name: Checkout code + uses: actions/checkout@v4 + + - name: Set up Python + uses: actions/setup-python@v5 + with: + python-version: '3.11' + + - name: Run PR title checker + run: python3 tests/special_sanity/check_pr_title.py + env: + PR_TITLE: ${{ github.event.pull_request.title }} + + - name: Run PR description checker + run: python3 tests/special_sanity/check_pr_description.py + env: + PR_TITLE: ${{ github.event.pull_request.title }} + GITHUB_EVENT_PATH: ${{ github.event_path }} diff --git a/sk2decompile/verl/.github/workflows/checkpoint_converter.yml b/sk2decompile/verl/.github/workflows/checkpoint_converter.yml new file mode 100644 index 0000000..3dfe67e --- /dev/null +++ b/sk2decompile/verl/.github/workflows/checkpoint_converter.yml @@ -0,0 +1,136 @@ +# # Tests layout + +# Each folder under tests/ corresponds to a test category for a sub-namespace in verl. For instance: +# - `tests/trainer` for testing functionality related to `verl/trainer` +# - `tests/models` for testing functionality related to `verl/models` +# - ... + +# There are a few folders with `special_` prefix, created for special purposes: +# - `special_distributed`: unit tests that must run with multiple GPUs +# - `special_e2e`: end-to-end tests with training/generation scripts +# - `special_npu`: tests for NPUs +# - `special_sanity`: a suite of quick sanity tests +# - `special_standalone`: a set of test that are designed to run in dedicated environments + +# Accelerators for tests +# - By default tests are run with GPU available, except for the ones under `special_npu`, and any test script whose name ends with `on_cpu.py`. +# - For test scripts with `on_cpu.py` name suffix would be tested on CPU resources in linux environment. + +# # Workflow layout + +# All CI tests are configured by yaml files in `.github/workflows/`. Here's an overview of all test configs: +# 1. A list of always triggered CPU sanity tests: `check-pr-title.yml`, `secrets_scan.yml`, `check-pr-title,yml`, `pre-commit.yml`, `doc.yml` +# 2. Some heavy multi-GPU unit tests, such as `model.yml`, `vllm.yml`, `sgl.yml` +# 3. End-to-end tests: `e2e_*.yml` +# 4. Unit tests +# - `cpu_unit_tests.yml`, run pytest on all scripts with file name pattern `tests/**/test_*_on_cpu.py` +# - `gpu_unit_tests.yml`, run pytest on all scripts with file without the `on_cpu.py` suffix. +# - Since cpu/gpu unit tests by default runs all tests under `tests`, please make sure tests are manually excluded in them when +# - new workflow yaml is added to `.github/workflows` +# - new tests are added to workflow mentioned in 2. + + + +name: checkpoint_converter +# latest version: Megatron-LM core_r0.11.0 https://github.com/NVIDIA/Megatron-LM/tree/core_r0.11.0 + +on: + # Trigger the workflow on push or pull request, + # but only for the main branch + push: + branches: + - main + - v0.* + pull_request: + branches: + - main + - v0.* + paths: + - "**/*.py" + # Other entrypoints + - "!examples/**" + - "!tests/**" + - "!verl/trainer/main_*.py" + - "!verl/trainer/fsdp_sft_trainer.py" + # Recipes + - "!recipe/**" + # FSDP + - "!verl/workers/**/*dp_*.py" + # Entrypoints + - ".github/workflows/checkpoint_converter.yml" + - ".github/workflows/e2e_ppo_trainer_megatron.yml" + - "examples/data_preprocess/gsm8k.py" + - "tests/special_e2e/run_ppo_trainer_megatron.sh" + - "verl/trainer/main_ppo.py" + - "verl/trainer/config/ppo_megatron_trainer.yaml" + + +# Cancel jobs on the same ref if a new one is triggered +concurrency: + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: ${{ github.ref != 'refs/heads/main' }} + +# Declare permissions just read content. +permissions: + contents: read + +jobs: + checkpoint_converter: + runs-on: [L20x8] + timeout-minutes: 20 # Increase this timeout value as needed + env: + HTTP_PROXY: ${{ secrets.PROXY_HTTP }} + HTTPS_PROXY: ${{ secrets.PROXY_HTTPS }} + NO_PROXY: "localhost,127.0.0.1" + HF_HUB_ENABLE_HF_TRANSFER: "0" # This is more stable + container: + image: verlai/verl:app-verl0.4-sglang0.4.6.post5-vllm0.8.5-mcore0.12.1 + options: --gpus all --shm-size=10g + steps: + - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + with: + fetch-depth: 0 + - name: Install the current repository + run: | + pip3 install -e .[test] + - name: Running Huggingface to Megatron dist_ckpt converter (Qwen/Qwen2.5-0.5B) + run: | + ray stop --force + python scripts/converter_hf_to_mcore.py --hf_model_path=${HOME}/models/Qwen/Qwen2.5-0.5B --output_path checkpoints/Qwen/Qwen2.5-0.5B --test + - name: Running Huggingface to Megatron dist_ckpt converter (deepseek-ai/deepseek-coder-1.3b-instruct) + run: | + ray stop --force + python scripts/converter_hf_to_mcore.py --hf_model_path=${HOME}/models/deepseek-ai/deepseek-coder-1.3b-instruct --output_path checkpoints/deepseek-ai/deepseek-coder-1.3b-instruct --test + - name: Clean up + run: | + rm -rf checkpoints + checkpoint_converter_large_moe_models: + runs-on: [L20x8] + timeout-minutes: 30 # Increase this timeout value as needed + env: + HTTP_PROXY: ${{ secrets.PROXY_HTTP }} + HTTPS_PROXY: ${{ secrets.PROXY_HTTPS }} + NO_PROXY: "localhost,127.0.0.1" + HF_HUB_ENABLE_HF_TRANSFER: "0" # This is more stable + HF_ENDPOINT: "https://hf-mirror.com" + container: + image: verlai/verl:app-verl0.4-sglang0.4.6.post5-vllm0.8.5-mcore0.12.1 + options: --gpus all --shm-size=10g + steps: + - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + with: + fetch-depth: 0 + - name: Install the current repository + run: | + pip3 install -e .[test] + - name: Download Model to Use + run: | + huggingface-cli download Qwen/Qwen1.5-MoE-A2.7B-Chat --local-dir ${HOME}/models/Qwen/Qwen1.5-MoE-A2.7B-Chat + export HF_HUB_OFFLINE=1 + - name: Running Huggingface to Megatron dist_ckpt CPU converter (Qwen/Qwen1.5-MoE-A2.7B-Chat) + run: | + ray stop --force + python scripts/converter_hf_to_mcore.py --hf_model_path=${HOME}/models/Qwen/Qwen1.5-MoE-A2.7B-Chat --output_path checkpoints/Qwen/Qwen1.5-MoE-A2.7B-Chat --use_cpu_initialization + - name: clean up + run: | + rm -rf checkpoints diff --git a/sk2decompile/verl/.github/workflows/cpu_unit_tests.yml b/sk2decompile/verl/.github/workflows/cpu_unit_tests.yml new file mode 100644 index 0000000..c533240 --- /dev/null +++ b/sk2decompile/verl/.github/workflows/cpu_unit_tests.yml @@ -0,0 +1,83 @@ +# # Tests layout + +# Each folder under tests/ corresponds to a test category for a sub-namespace in verl. For instance: +# - `tests/trainer` for testing functionality related to `verl/trainer` +# - `tests/models` for testing functionality related to `verl/models` +# - ... + +# There are a few folders with `special_` prefix, created for special purposes: +# - `special_distributed`: unit tests that must run with multiple GPUs +# - `special_e2e`: end-to-end tests with training/generation scripts +# - `special_npu`: tests for NPUs +# - `special_sanity`: a suite of quick sanity tests +# - `special_standalone`: a set of test that are designed to run in dedicated environments + +# Accelerators for tests +# - By default tests are run with GPU available, except for the ones under `special_npu`, and any test script whose name ends with `on_cpu.py`. +# - For test scripts with `on_cpu.py` name suffix would be tested on CPU resources in linux environment. + +# # Workflow layout + +# All CI tests are configured by yaml files in `.github/workflows/`. Here's an overview of all test configs: +# 1. A list of always triggered CPU sanity tests: `check-pr-title.yml`, `secrets_scan.yml`, `check-pr-title,yml`, `pre-commit.yml`, `doc.yml` +# 2. Some heavy multi-GPU unit tests, such as `model.yml`, `vllm.yml`, `sgl.yml` +# 3. End-to-end tests: `e2e_*.yml` +# 4. Unit tests +# - `cpu_unit_tests.yml`, run pytest on all scripts with file name pattern `tests/**/test_*_on_cpu.py` +# - `gpu_unit_tests.yml`, run pytest on all scripts with file without the `on_cpu.py` suffix. +# - Since cpu/gpu unit tests by default runs all tests under `tests`, please make sure tests are manually excluded in them when +# - new workflow yaml is added to `.github/workflows` +# - new tests are added to workflow mentioned in 2. + + +name: cpu_unit_tests + +on: + # Trigger the workflow on push or pull request, + # but only for the main branch + push: + branches: + - main + - v0.* + pull_request: + branches: + - main + - v0.* + paths: + - "**/*.py" + - .github/workflows/cpu_unit_tests.yml + - "!recipe/**/*.py" + +# Cancel jobs on the same ref if a new one is triggered +concurrency: + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: ${{ github.ref != 'refs/heads/main' }} + +# Declare permissions just read content. +permissions: + contents: read + +jobs: + cpu_unit_tests: + runs-on: ubuntu-latest + timeout-minutes: 10 # Increase this timeout value as needed + strategy: + matrix: + python-version: ["3.10"] + steps: + - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + - name: Set up Python ${{ matrix.python-version }} + uses: actions/setup-python@0b93645e9fea7318ecaed2b359559ac225c90a2b # v5.3.0 + with: + python-version: ${{ matrix.python-version }} + - name: Install the current repository + run: | + pip install -e .[test,prime,geo] + pip install --upgrade "ray>=2.40.0" pillow + - name: Running CPU unit tests + run: | + [ ! -d "$HOME/verl-data" ] && huggingface-cli download verl-team/gsm8k-v0.4.1 --repo-type dataset --local-dir ~/verl-data/gsm8k + python3 examples/data_preprocess/geo3k.py + echo '[pytest]' > pytest.ini + echo 'python_files = *_on_cpu.py' >> pytest.ini + pytest -s -x tests/ diff --git a/sk2decompile/verl/.github/workflows/disabled/e2e_prime.yml b/sk2decompile/verl/.github/workflows/disabled/e2e_prime.yml new file mode 100644 index 0000000..b7d4f4e --- /dev/null +++ b/sk2decompile/verl/.github/workflows/disabled/e2e_prime.yml @@ -0,0 +1,66 @@ +name: e2e_prime + +on: + # Trigger the workflow on push or pull request, + # but only for the main branch + push: + branches: + - disabled_ci + pull_request: + branches: + - disabled_ci + paths: + - "**/*.py" + # Other entrypoints + - "!examples/**" + - "!tests/**" + - "!verl/trainer/main_*.py" + - "!verl/trainer/fsdp_sft_trainer.py" + # Other recipes + - "!recipe/**" + # Megatron + - "!verl/workers/**/megatron_*.py" + # Home + - "recipe/prime" + # Entrypoints + - ".github/workflows/e2e_prime.yml" + - "examples/data_preprocess/gsm8k.py" + - "tests/special_e2e/run_prime.sh" + +# Cancel jobs on the same ref if a new one is triggered +concurrency: + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: ${{ github.ref != 'refs/heads/main' }} + +# Declare permissions just read content. +permissions: + contents: read + +jobs: + e2e_prime: + runs-on: [L20x8] + timeout-minutes: 50 # Increase this timeout value as needed + env: + HTTP_PROXY: ${{ secrets.PROXY_HTTP }} + HTTPS_PROXY: ${{ secrets.PROXY_HTTPS }} + NO_PROXY: "localhost,127.0.0.1,hf-mirror.com" + HF_ENDPOINT: "https://hf-mirror.com" + HF_HUB_ENABLE_HF_TRANSFER: "0" # This is more stable + container: + image: whatcanyousee/verl:ngc-cu124-vllm0.8.5-sglang0.4.6.post5-mcore0.12.0-te2.3 + options: --gpus all --shm-size=10g + steps: + - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + with: + fetch-depth: 0 + - name: Install the current repository + run: | + pip3 install --no-deps -e .[test,gpu] + - name: Prepare gsm8k dataset + run: | + ray stop --force + python3 examples/data_preprocess/gsm8k.py + - name: Running GSM8K E2E with prime alg + run: | + ray stop --force + bash tests/special_e2e/run_prime.sh diff --git a/sk2decompile/verl/.github/workflows/doc.yml b/sk2decompile/verl/.github/workflows/doc.yml new file mode 100644 index 0000000..55eaa2e --- /dev/null +++ b/sk2decompile/verl/.github/workflows/doc.yml @@ -0,0 +1,100 @@ +# # Tests layout + +# Each folder under tests/ corresponds to a test category for a sub-namespace in verl. For instance: +# - `tests/trainer` for testing functionality related to `verl/trainer` +# - `tests/models` for testing functionality related to `verl/models` +# - ... + +# There are a few folders with `special_` prefix, created for special purposes: +# - `special_distributed`: unit tests that must run with multiple GPUs +# - `special_e2e`: end-to-end tests with training/generation scripts +# - `special_npu`: tests for NPUs +# - `special_sanity`: a suite of quick sanity tests +# - `special_standalone`: a set of test that are designed to run in dedicated environments + +# Accelerators for tests +# - By default tests are run with GPU available, except for the ones under `special_npu`, and any test script whose name ends with `on_cpu.py`. +# - For test scripts with `on_cpu.py` name suffix would be tested on CPU resources in linux environment. + +# # Workflow layout + +# All CI tests are configured by yaml files in `.github/workflows/`. Here's an overview of all test configs: +# 1. A list of always triggered CPU sanity tests: `check-pr-title.yml`, `secrets_scan.yml`, `check-pr-title,yml`, `pre-commit.yml`, `doc.yml` +# 2. Some heavy multi-GPU unit tests, such as `model.yml`, `vllm.yml`, `sgl.yml` +# 3. End-to-end tests: `e2e_*.yml` +# 4. Unit tests +# - `cpu_unit_tests.yml`, run pytest on all scripts with file name pattern `tests/**/test_*_on_cpu.py` +# - `gpu_unit_tests.yml`, run pytest on all scripts with file without the `on_cpu.py` suffix. +# - Since cpu/gpu unit tests by default runs all tests under `tests`, please make sure tests are manually excluded in them when +# - new workflow yaml is added to `.github/workflows` +# - new tests are added to workflow mentioned in 2. + + +name: doc_test + +on: + # Trigger the workflow on push or pull request, + # but only for the main branch + push: + branches: + - main + - v0.* + pull_request: + branches: + - main + - v0.* + paths: + - "**/*.py" + - "docs/**" + - .github/workflows/doc.yml + +# Cancel jobs on the same ref if a new one is triggered +concurrency: + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: ${{ github.ref != 'refs/heads/main' }} + +# Declare permissions just read content. +permissions: + contents: read # for checkout + pages: write # for deploy-pages + id-token: write # for deploy-pages + +jobs: + doc_test: + runs-on: ubuntu-latest + timeout-minutes: 5 # Increase this timeout value as needed + strategy: + matrix: + python-version: ["3.10"] + steps: + - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + - name: Set up Python ${{ matrix.python-version }} + uses: actions/setup-python@0b93645e9fea7318ecaed2b359559ac225c90a2b # v5.3.0 + with: + python-version: ${{ matrix.python-version }} + - name: Install the current repository + run: | + pip install -e .[test] + pip install -r docs/requirements-docs.txt + + - name: Run doc make html + run: | + cd docs + make clean + make html SPHINXOPTS="--keep-going -w _build/sphinx.log" + if grep -q ": ERROR:" _build/sphinx.log; then + echo "🚨 Sphinx doc build contained ERRORs - see _build/sphinx.log" + exit 1 + fi + if grep -q "WARNING: document isn't included in any toctree" _build/sphinx.log; then + echo "🚨 Sphinx doc build contained WARNING. Please include newly added docs in index.rst. See _build/sphinx.log for details" + exit 1 + fi + if grep -q "WARNING: Inline emphasis" _build/sphinx.log; then + echo "🚨 Sphinx doc build contained WARNING. Please check inline emphasis is correct. See _build/sphinx.log for details" + exit 1 + fi + if grep -q "WARNING: Definition list ends without a blank line" _build/sphinx.log; then + echo "🚨 Sphinx doc build contained WARNING. Please check if the indentation is correct. See _build/sphinx.log for details" + exit 1 + fi diff --git a/sk2decompile/verl/.github/workflows/e2e_ascend.yml b/sk2decompile/verl/.github/workflows/e2e_ascend.yml new file mode 100644 index 0000000..c66d772 --- /dev/null +++ b/sk2decompile/verl/.github/workflows/e2e_ascend.yml @@ -0,0 +1,142 @@ +# # Tests layout + +# Each folder under tests/ corresponds to a test category for a sub-namespace in verl. For instance: +# - `tests/trainer` for testing functionality related to `verl/trainer` +# - `tests/models` for testing functionality related to `verl/models` +# - ... + +# There are a few folders with `special_` prefix, created for special purposes: +# - `special_distributed`: unit tests that must run with multiple GPUs +# - `special_e2e`: end-to-end tests with training/generation scripts +# - `special_npu`: tests for NPUs +# - `special_sanity`: a suite of quick sanity tests +# - `special_standalone`: a set of test that are designed to run in dedicated environments + +# Accelerators for tests +# - By default tests are run with GPU available, except for the ones under `special_npu`, and any test script whose name ends with `on_cpu.py`. +# - For test scripts with `on_cpu.py` name suffix would be tested on CPU resources in linux environment. + +# # Workflow layout + +# All CI tests are configured by yaml files in `.github/workflows/`. Here's an overview of all test configs: +# 1. A list of always triggered CPU sanity tests: `check-pr-title.yml`, `secrets_scan.yml`, `check-pr-title,yml`, `pre-commit.yml`, `doc.yml` +# 2. Some heavy multi-GPU unit tests, such as `model.yml`, `vllm.yml`, `sgl.yml` +# 3. End-to-end tests: `e2e_*.yml` +# 4. Unit tests +# - `cpu_unit_tests.yml`, run pytest on all scripts with file name pattern `tests/**/test_*_on_cpu.py` +# - `gpu_unit_tests.yml`, run pytest on all scripts with file without the `on_cpu.py` suffix. +# - Since cpu/gpu unit tests by default runs all tests under `tests`, please make sure tests are manually excluded in them when +# - new workflow yaml is added to `.github/workflows` +# - new tests are added to workflow mentioned in 2. + + +name: e2e_ascend + +on: + # Trigger the workflow on push or pull request, + # but only for the main branch + push: + branches: + - main + - v0.* + pull_request: + branches: + - main + paths: + - "**/*.py" + - "requirements-npu.txt" + # Other entrypoints + - "!examples/**" + - "!tests/**" + - "!verl/trainer/main_*.py" + - "!verl/trainer/fsdp_sft_trainer.py" + # Recipes + - "!recipe/**" + # Entrypoints + - ".github/workflows/e2e_ascend.yml" + - "examples/data_preprocess/gsm8k.py" + - "examples/data_preprocess/geo3k.py" + - "tests/special_e2e/ppo_trainer" + - "verl/trainer/main_ppo.py" + - "verl/trainer/config/ppo_trainer.yaml" + +# Cancel jobs on the same ref if a new one is triggered +concurrency: + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: ${{ github.ref != 'refs/heads/main' }} + +permissions: + contents: read + +jobs: + test: + name: verl Ascend test (self-host) + runs-on: [self-hosted, npu-0] + timeout-minutes: 30 # Increase this timeout value as needed + container: + image: crispig/verl_npu:cann8.1rc1-py3.10-torch2.5.1-vllm-ascend0.7.3.post1-250616 + volumes: + - /usr/local/dcmi:/usr/local/dcmi + - /usr/local/bin/npu-smi:/usr/local/bin/npu-smi + - /usr/local/Ascend/driver/lib64/:/usr/local/Ascend/driver/lib64/ + - /usr/local/Ascend/driver/version.info:/usr/local/Ascend/driver/version.info + - /etc/ascend_install.info:/etc/ascend_install.info + # Use self-host cache speed up pip and model download + # - /home/action/actions-runner/_work/cache:/github/home/.cache/ + options: >- + --device /dev/davinci0 + --device /dev/davinci_manager + --device /dev/devmm_svm + --device /dev/hisi_hdc + --network host + --privileged + --shm-size 16g + env: + HTTP_PROXY: ${{ secrets.PROXY_HTTP }} + HTTPS_PROXY: ${{ secrets.PROXY_HTTPS }} + NO_PROXY: "localhost,127.0.0.1,hf-mirror.com" + HF_ENDPOINT: "https://hf-mirror.com" + HF_HUB_ENABLE_HF_TRANSFER: "0" # This is more stable + steps: + - name: Check npu and CANN info + run: | + cat /usr/local/Ascend/ascend-toolkit/latest/"$(uname -i)"-linux/ascend_toolkit_install.info + npu-smi info + - name: Checkout volcengine/verl repo + uses: actions/checkout@v4 + - name: Install the current repository + run: | + pip3 install hf_transfer peft + pip3 install -r requirements-npu.txt + pip install -e . + - name: Install torchviison + run: | + pip install torchvision==0.20.1+cpu --index-url https://download.pytorch.org/whl/cpu + - name: Prepare gsm8k dataset + run: | + ray stop --force + python3 examples/data_preprocess/gsm8k.py + - name: Prepare geo3k dataset + run: | + ray stop --force + python3 examples/data_preprocess/geo3k.py + - name: Running gsm8k e2e training tests with peft sft on ASCEND NPU + run: | + ray stop --force + bash tests/special_npu/run_qwen2_5_05b_sft_peft_sp2.sh + rm -rf $HOME/ckpts + - name: Running gsm8k e2e training tests with GRPO on ASCEND NPU + run: | + ray stop --force + bash tests/special_npu/run_qwen2_5_05b_grpo.sh + rm -rf $HOME/ckpts + - name: Running geo3k e2e training tests with GRPO on ASCEND NPU + run: | + ray stop --force + bash tests/special_npu/run_qwen2_5_vl_3b_npu.sh + rm -rf $HOME/ckpts + - name: Running gsm8k e2e training tests with DAPO on ASCEND NPU + run: | + ray stop --force + bash tests/special_npu/run_qwen2_5_05b_dapo.sh + rm -rf $HOME/ckpts diff --git a/sk2decompile/verl/.github/workflows/e2e_dapo.yml b/sk2decompile/verl/.github/workflows/e2e_dapo.yml new file mode 100644 index 0000000..446d2c1 --- /dev/null +++ b/sk2decompile/verl/.github/workflows/e2e_dapo.yml @@ -0,0 +1,112 @@ +# # Tests layout + +# Each folder under tests/ corresponds to a test category for a sub-namespace in verl. For instance: +# - `tests/trainer` for testing functionality related to `verl/trainer` +# - `tests/models` for testing functionality related to `verl/models` +# - ... + +# There are a few folders with `special_` prefix, created for special purposes: +# - `special_distributed`: unit tests that must run with multiple GPUs +# - `special_e2e`: end-to-end tests with training/generation scripts +# - `special_npu`: tests for NPUs +# - `special_sanity`: a suite of quick sanity tests +# - `special_standalone`: a set of test that are designed to run in dedicated environments + +# Accelerators for tests +# - By default tests are run with GPU available, except for the ones under `special_npu`, and any test script whose name ends with `on_cpu.py`. +# - For test scripts with `on_cpu.py` name suffix would be tested on CPU resources in linux environment. + +# # Workflow layout + +# All CI tests are configured by yaml files in `.github/workflows/`. Here's an overview of all test configs: +# 1. A list of always triggered CPU sanity tests: `check-pr-title.yml`, `secrets_scan.yml`, `check-pr-title,yml`, `pre-commit.yml`, `doc.yml` +# 2. Some heavy multi-GPU unit tests, such as `model.yml`, `vllm.yml`, `sgl.yml` +# 3. End-to-end tests: `e2e_*.yml` +# 4. Unit tests +# - `cpu_unit_tests.yml`, run pytest on all scripts with file name pattern `tests/**/test_*_on_cpu.py` +# - `gpu_unit_tests.yml`, run pytest on all scripts with file without the `on_cpu.py` suffix. +# - Since cpu/gpu unit tests by default runs all tests under `tests`, please make sure tests are manually excluded in them when +# - new workflow yaml is added to `.github/workflows` +# - new tests are added to workflow mentioned in 2. + + +name: e2e_dapo + +on: + # Trigger the workflow on push or pull request, + # but only for the main branch + # For push, for now only anti-patterns are specified so it is more conservative + # and achieves higher coverage. + push: + branches: + - main + - v0.* + paths: + - "verl/*.py" + # Other entrypoints + - "!examples/*trainer*" + - "!tests/**" + - "!verl/trainer/main_*.py" + - "!verl/trainer/fsdp_sft_trainer.py" + # Megatron + - "!verl/workers/**/megatron_*.py" + - "!recipe/**" + - "recipe/dapo" + pull_request: + branches: + - main + - v0.* + paths: + - "**/*.py" + # Other entrypoints + - "!examples/**" + - "!tests/**" + - "!verl/trainer/main_*.py" + - "!verl/trainer/fsdp_sft_trainer.py" + # Other recipes + - "!recipe/**" + # Megatron + - "!verl/workers/**/megatron_*.py" + # Home + - "recipe/dapo" + # Entrypoints + - ".github/workflows/e2e_dapo.yml" + - "examples/data_preprocess/gsm8k.py" + - "tests/special_e2e/run_dapo.sh" + +# Cancel jobs on the same ref if a new one is triggered +concurrency: + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: ${{ github.ref != 'refs/heads/main' }} + +# Declare permissions just read content. +permissions: + contents: read + +jobs: + e2e_dapo: + runs-on: [L20x8] + timeout-minutes: 40 # Increase this timeout value as needed + env: + HTTP_PROXY: ${{ secrets.PROXY_HTTP }} + HTTPS_PROXY: ${{ secrets.PROXY_HTTPS }} + NO_PROXY: "localhost,127.0.0.1,hf-mirror.com" + HF_ENDPOINT: "https://hf-mirror.com" + HF_HUB_ENABLE_HF_TRANSFER: "0" # This is more stable + container: + image: verlai/verl:app-verl0.4-vllm0.8.5-mcore0.12.1 + options: --gpus all --shm-size=10g + steps: + - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + with: + fetch-depth: 0 + - name: Install the current repository + run: | + pip3 install --no-deps -e .[test,gpu] + - name: Prepare GSM8K dataset + run: | + python3 examples/data_preprocess/gsm8k.py + - name: Running the E2E test with the DAPO algorithm + run: | + ray stop --force + bash tests/special_e2e/run_dapo.sh diff --git a/sk2decompile/verl/.github/workflows/e2e_eval_aime24.yml b/sk2decompile/verl/.github/workflows/e2e_eval_aime24.yml new file mode 100644 index 0000000..ab41431 --- /dev/null +++ b/sk2decompile/verl/.github/workflows/e2e_eval_aime24.yml @@ -0,0 +1,146 @@ +# # Tests layout + +# Each folder under tests/ corresponds to a test category for a sub-namespace in verl. For instance: +# - `tests/trainer` for testing functionality related to `verl/trainer` +# - `tests/models` for testing functionality related to `verl/models` +# - ... + +# There are a few folders with `special_` prefix, created for special purposes: +# - `special_distributed`: unit tests that must run with multiple GPUs +# - `special_e2e`: end-to-end tests with training/generation scripts +# - `special_npu`: tests for NPUs +# - `special_sanity`: a suite of quick sanity tests +# - `special_standalone`: a set of test that are designed to run in dedicated environments + +# Accelerators for tests +# - By default tests are run with GPU available, except for the ones under `special_npu`, and any test script whose name ends with `on_cpu.py`. +# - For test scripts with `on_cpu.py` name suffix would be tested on CPU resources in linux environment. + +# # Workflow layout + +# All CI tests are configured by yaml files in `.github/workflows/`. Here's an overview of all test configs: +# 1. A list of always triggered CPU sanity tests: `check-pr-title.yml`, `secrets_scan.yml`, `check-pr-title,yml`, `pre-commit.yml`, `doc.yml` +# 2. Some heavy multi-GPU unit tests, such as `model.yml`, `vllm.yml`, `sgl.yml` +# 3. End-to-end tests: `e2e_*.yml` +# 4. Unit tests +# - `cpu_unit_tests.yml`, run pytest on all scripts with file name pattern `tests/**/test_*_on_cpu.py` +# - `gpu_unit_tests.yml`, run pytest on all scripts with file without the `on_cpu.py` suffix. +# - Since cpu/gpu unit tests by default runs all tests under `tests`, please make sure tests are manually excluded in them when +# - new workflow yaml is added to `.github/workflows` +# - new tests are added to workflow mentioned in 2. + + +name: e2e_eval_aime24 + +on: + # Trigger the workflow on push or pull request, + # but only for the main branch + # For push, for now only anti-patterns are specified so it is more conservative + # and achieves higher coverage. + push: + branches: + - main + - v0.* + paths: + - "**/*.py" + # Other entrypoints + - "!*.md" + - "!docker/**" + - "!docs/**" + - "!examples/**" + - "!tests/**" + - "!verl/trainer/main_*.py" + - "!verl/trainer/fsdp_sft_trainer.py" + - "!recipe/**" + - "recipe/r1" + - "!recipe/r1/README.md" + pull_request: + branches: + - main + paths: + - "**/*.py" + # Other entrypoints + - "!*.md" + - "!docker/**" + - "!docs/**" + - "!examples/**" + - "!tests/**" + - "!verl/trainer/main_*.py" + - "!verl/trainer/fsdp_sft_trainer.py" + # Home + - "recipe/r1" + - "!recipe/r1/README.md" + # Other recipes + - "!recipe/**" + # Entrypoints + - ".github/workflows/e2e_eval_aime24.yml" + - "tests/special_e2e/run_r1_distill_qwen_aime24_eval.sh" + - "verl/trainer/main_generation.py" + - "verl/trainer/config/generation.yaml" + +# Cancel jobs on the same ref if a new one is triggered +concurrency: + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: ${{ github.ref != 'refs/heads/main' }} + +# Declare permissions just read content. +permissions: + contents: read + +env: + IMAGE: "verl-ci-cn-beijing.cr.volces.com/verlai/verl:app-verl0.4-vllm0.8.5-mcore0.12.1" + DYNAMIC_RUNNER_ENDPOINT: "https://sd10g3clalm04ug7alq90.apigateway-cn-beijing.volceapi.com/runner" + +jobs: + setup: + runs-on: ubuntu-latest + outputs: + runner-label: ${{ steps.create-runner.outputs.runner-label }} + mlp-task-id: ${{ steps.create-runner.outputs.mlp-task-id }} + steps: + - uses: actions/checkout@v4 + - id: create-runner + uses: volcengine/vemlp-github-runner@v1 + with: + mode: "create" + faas-url: "${{ env.DYNAMIC_RUNNER_ENDPOINT }}" + mlp-image: "${{ env.IMAGE }}" + + e2e_eval_aime24: + needs: setup + runs-on: ["${{ needs.setup.outputs.runner-label || 'L20x8' }}"] + timeout-minutes: 40 # Increase this timeout value as needed + env: + HTTP_PROXY: ${{ secrets.PROXY_HTTP }} + HTTPS_PROXY: ${{ secrets.PROXY_HTTPS }} + NO_PROXY: "localhost,127.0.0.1,hf-mirror.com" + HF_ENDPOINT: "https://hf-mirror.com" + HF_HUB_ENABLE_HF_TRANSFER: "0" # This is more stable + steps: + - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + with: + fetch-depth: 0 + - name: Install the current repository + run: | + pip3 install --no-deps -e .[test,gpu,math] + pip3 install math-verify + - name: Prepare aime24 dataset + run: | + ray stop --force + python3 recipe/r1/data_process.py --task aime2024 + - name: Running generation and evaluation in AIME 2024 + run: | + ray stop --force + bash tests/special_e2e/run_r1_distill_qwen_aime24_eval.sh + + cleanup: + runs-on: ubuntu-latest + needs: [setup, e2e_eval_aime24] + if: always() + steps: + - id: destroy-runner + uses: volcengine/vemlp-github-runner@v1 + with: + mode: "destroy" + faas-url: "${{ env.DYNAMIC_RUNNER_ENDPOINT }}" + mlp-task-id: "${{ needs.setup.outputs.mlp-task-id }}" \ No newline at end of file diff --git a/sk2decompile/verl/.github/workflows/e2e_genrm_remote.yml b/sk2decompile/verl/.github/workflows/e2e_genrm_remote.yml new file mode 100644 index 0000000..8f06a6c --- /dev/null +++ b/sk2decompile/verl/.github/workflows/e2e_genrm_remote.yml @@ -0,0 +1,105 @@ +# # Tests layout + +# Each folder under tests/ corresponds to a test category for a sub-namespace in verl. For instance: +# - `tests/trainer` for testing functionality related to `verl/trainer` +# - `tests/models` for testing functionality related to `verl/models` +# - ... + +# There are a few folders with `special_` prefix, created for special purposes: +# - `special_distributed`: unit tests that must run with multiple GPUs +# - `special_e2e`: end-to-end tests with training/generation scripts +# - `special_npu`: tests for NPUs +# - `special_sanity`: a suite of quick sanity tests +# - `special_standalone`: a set of test that are designed to run in dedicated environments + +# Accelerators for tests +# - By default tests are run with GPU available, except for the ones under `special_npu`, and any test script whose name ends with `on_cpu.py`. +# - For test scripts with `on_cpu.py` name suffix would be tested on CPU resources in linux environment. + +# # Workflow layout + +# All CI tests are configured by yaml files in `.github/workflows/`. Here's an overview of all test configs: +# 1. A list of always triggered CPU sanity tests: `check-pr-title.yml`, `secrets_scan.yml`, `check-pr-title,yml`, `pre-commit.yml`, `doc.yml` +# 2. Some heavy multi-GPU unit tests, such as `model.yml`, `vllm.yml`, `sgl.yml` +# 3. End-to-end tests: `e2e_*.yml` +# 4. Unit tests +# - `cpu_unit_tests.yml`, run pytest on all scripts with file name pattern `tests/**/test_*_on_cpu.py` +# - `gpu_unit_tests.yml`, run pytest on all scripts with file without the `on_cpu.py` suffix. +# - Since cpu/gpu unit tests by default runs all tests under `tests`, please make sure tests are manually excluded in them when +# - new workflow yaml is added to `.github/workflows` +# - new tests are added to workflow mentioned in 2. + + +name: e2e_genrm_remote + +on: + # Trigger the workflow on push or pull request, + # but only for the main branch + push: + branches: + - main + - v0.* + paths: + - "**/*.py" + - "tests/**" + - "!recipe/**" + - "recipe/genrm_remote" + pull_request: + branches: + - main + - v0.* + paths: + - "**/*.py" + # Other entrypoints + - "!examples/**" + - "!tests/**" + - "!verl/trainer/main_*.py" + - "!verl/trainer/fsdp_sft_trainer.py" + # Other recipes + - "!recipe/**" + # Megatron + - "!verl/workers/**/megatron_*.py" + # Home + - "recipe/genrm_remote" + - "!recipe/genrm_remote/README.md" + # Entrypoints + - ".github/workflows/e2e_genrm_remote.yml" + - "examples/data_preprocess/gsm8k.py" + - "tests/special_e2e/run_genrm_remote.sh" + +# Cancel jobs on the same ref if a new one is triggered +concurrency: + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: ${{ github.ref != 'refs/heads/main' }} + +# Declare permissions just read content. +permissions: + contents: read + +jobs: + e2e_genrm_remote: + runs-on: [L20x8] + timeout-minutes: 40 # Increase this timeout value as needed + env: + HTTP_PROXY: ${{ secrets.PROXY_HTTP }} + HTTPS_PROXY: ${{ secrets.PROXY_HTTPS }} + NO_PROXY: "localhost,127.0.0.1,hf-mirror.com" + HF_ENDPOINT: "https://hf-mirror.com" + HF_HUB_ENABLE_HF_TRANSFER: "0" # This is more stable + container: + image: whatcanyousee/verl:ngc-cu124-vllm0.8.5-sglang0.4.6.post5-mcore0.12.0-te2.3 + options: --gpus all --shm-size=10g + steps: + - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + with: + fetch-depth: 0 + - name: Install the current repository + run: | + pip3 install --no-deps -e .[test,gpu] + - name: Prepare GSM8K dataset + run: | + python3 examples/data_preprocess/gsm8k.py + - name: Running the E2E test with the Generative Reward Model + run: | + ray stop --force + bash tests/special_e2e/run_genrm_remote.sh diff --git a/sk2decompile/verl/.github/workflows/e2e_ppo_trainer.yml b/sk2decompile/verl/.github/workflows/e2e_ppo_trainer.yml new file mode 100644 index 0000000..1419a27 --- /dev/null +++ b/sk2decompile/verl/.github/workflows/e2e_ppo_trainer.yml @@ -0,0 +1,424 @@ +name: e2e_ppo_trainer + +on: + # Trigger the workflow on push or pull request, + # but only for the main branch + # For push, for now only anti-patterns are specified so it is more conservative + # and achieves higher coverage. + push: + branches: + - main + - v0.* + paths: + - "**/*.py" + # Other entrypoints + - "!verl/trainer/fsdp_sft_trainer.py" + # Recipes + - "!recipe/**" + # Megatron + - "!verl/workers/**/megatron_*.py" + + pull_request: + branches: + - main + - v0.* + paths: + - "**/*.py" + # Other entrypoints + - "!**/*.md" + - "!docker/**" + - "!examples/**" + - "!tests/**" + - "!verl/trainer/main_*.py" + - "!verl/trainer/fsdp_sft_trainer.py" + # Docs + - "!docs/**" + # Recipes + - "!recipe/**" + # Megatron + - "!verl/workers/**/megatron_*.py" + # Entrypoints + - ".github/workflows/e2e_ppo_trainer.yml" + - "examples/data_preprocess/gsm8k.py" + - "examples/data_preprocess/geo3k.py" + - "tests/special_e2e/ppo_trainer" + - "verl/trainer/main_ppo.py" + - "verl/trainer/config/ppo_trainer.yaml" + +# Cancel jobs on the same ref if a new one is triggered +concurrency: + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: ${{ github.ref != 'refs/heads/main' }} + +# Declare permissions just read content. +permissions: + contents: read + +jobs: + pre_commit_for_ppo: + runs-on: ubuntu-latest + strategy: + matrix: + python-version: ["3.12"] + steps: + - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + - name: Set up Python ${{ matrix.python-version }} + uses: actions/setup-python@0b93645e9fea7318ecaed2b359559ac225c90a2b # v5.3.0 + with: + python-version: ${{ matrix.python-version }} + - name: Set ruff --output-format=github + run: | + sed -i 's/--output-format=full/--output-format=github/' .pre-commit-config.yaml + git add .pre-commit-config.yaml + - uses: pre-commit/action@v3.0.1 + with: + extra_args: "" # Overriding default "--all-files" + + e2e_ppo_trainer_vllm: + runs-on: [L20x8] + timeout-minutes: 60 # Increase this timeout value as needed + env: + HTTP_PROXY: ${{ secrets.PROXY_HTTP }} + HTTPS_PROXY: ${{ secrets.PROXY_HTTPS }} + NO_PROXY: "localhost,127.0.0.1,hf-mirror.com" + HF_ENDPOINT: "https://hf-mirror.com" + HF_HUB_ENABLE_HF_TRANSFER: "0" # This is more stable + container: + image: verlai/verl:app-verl0.4-vllm0.8.5-mcore0.12.1 + options: --gpus all --shm-size=10g + steps: + - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + with: + fetch-depth: 0 + - name: Install the current repository + run: | + pip3 install --no-deps -e .[test,vllm] + - name: Prepare GSM8K dataset + run: | + ray stop --force + python3 examples/data_preprocess/gsm8k.py + # HF sanity + - name: Running GSM8K E2E training tests on 1 L20 GPU with hf for santiy + run: | + ray stop --force + bash tests/special_e2e/ppo_trainer/run_single_gpu.sh + # Function RM + - name: Running GSM8K E2E training tests on 8 L20 GPUs with rmpad using function rm with validation and saving (FSDP_SIZE=8) + run: | + ray stop --force + VAL_BEFORE_TRAIN=True TEST_FREQ=1 SAVE_FREQ=1 SAVE_HF_MODEL=True VERL_EXP_NAME="qwen2.5-0.5b-function-reward-minimal-fsdp-size8" bash tests/special_e2e/ppo_trainer/run_function_reward.sh + - name: Running GSM8K E2E training tests on 8 L20 GPUs with rmpad using function rm after resuming + run: | + ray stop --force + RESUME_MODE=auto VERL_EXP_NAME="qwen2.5-0.5b-function-reward-minimal-fsdp-size8" bash tests/special_e2e/ppo_trainer/run_function_reward.sh + - name: Test merging FSDP checkpoints (Qwen Actor) + run: | + exp_name="qwen2.5-0.5b-function-reward-minimal-fsdp-size8" + python -m verl.model_merger test --backend fsdp --local_dir checkpoints/verl-test/${exp_name}/global_step_1/actor --test_hf_dir checkpoints/verl-test/${exp_name}/global_step_1/actor/huggingface + - name: Running GSM8K E2E training tests on 8 L20 GPUs with rmpad using function rm with validation and saving (DDP_SIZE=2, FSDP_SIZE=4) + run: | + ray stop --force + VAL_BEFORE_TRAIN=True TEST_FREQ=1 SAVE_FREQ=1 SAVE_HF_MODEL=True FSDP_SIZE=4 VERL_EXP_NAME="qwen2.5-0.5b-function-reward-minimal-ddp-size2-fsdp-size4" bash tests/special_e2e/ppo_trainer/run_function_reward.sh + - name: Test merging DDP+FSDP checkpoints (Qwen Actor) + run: | + exp_name="qwen2.5-0.5b-function-reward-minimal-ddp-size2-fsdp-size4" + python -m verl.model_merger test --backend fsdp --local_dir checkpoints/verl-test/${exp_name}/global_step_1/actor --test_hf_dir checkpoints/verl-test/${exp_name}/global_step_1/actor/huggingface + - name: Running GSM8K E2E training tests on 8 L20 GPUs with rmpad using function rm with validation and saving (FSDP2) + run: | + ray stop --force + VAL_BEFORE_TRAIN=True TEST_FREQ=1 SAVE_FREQ=1 SAVE_HF_MODEL=True VERL_EXP_NAME="qwen2.5-0.5b-function-reward-minimal-fsdp2-size8" STRATEGY=fsdp2 bash tests/special_e2e/ppo_trainer/run_function_reward.sh + - name: Test merging FSDP2 checkpoints (Qwen Actor) + run: | + exp_name="qwen2.5-0.5b-function-reward-minimal-fsdp2-size8" + python -m verl.model_merger test --backend fsdp --local_dir checkpoints/verl-test/${exp_name}/global_step_1/actor --test_hf_dir checkpoints/verl-test/${exp_name}/global_step_1/actor/huggingface + - name: Running GSM8K E2E without rmpad using function rm + run: | + ray stop --force + RM_PAD=False bash tests/special_e2e/ppo_trainer/run_function_reward.sh + - name: Running GSM8K E2E training tests on 8 L20 GPUs with rmpad using function rm (GRPO) + run: | + ray stop --force + ADV_ESTIMATOR=grpo USE_KL=True bash tests/special_e2e/ppo_trainer/run_function_reward.sh + - name: Running GSM8K E2E training tests on 8 L20 GPUs with rmpad using function rm (ReMax) + run: | + ray stop --force + ADV_ESTIMATOR=remax USE_KL=True bash tests/special_e2e/ppo_trainer/run_function_reward.sh + - name: Running GSM8K E2E training tests on 8 L20 GPUs with rmpad using customized reward function + run: | + ray stop --force + CUSTOM_REWARD_FN=True bash tests/special_e2e/ppo_trainer/run_function_reward.sh + - name: Running GSM8K E2E training tests on 8 L20 GPUs with rmpad using function rm with in-reward kl and kl loss + run: | + ray stop --force + USE_KL=True bash tests/special_e2e/ppo_trainer/run_function_reward.sh + # LoRA tests + - name: Running GSM8K E2E training tests on 8 L20 GPUs with grpo lora using function rm with use_shm + run: | + ray stop --force + ADV_ESTIMATOR=grpo USE_SHM=True LORA_RANK=32 LOAD_FORMAT=safetensors bash tests/special_e2e/ppo_trainer/run_function_reward.sh + - name: Running GSM8K E2E training tests on 8 L20 GPUs with grpo lora using function rm with use_shm and layered_summon + run: | + ray stop --force + ADV_ESTIMATOR=grpo USE_SHM=True LORA_RANK=32 LOAD_FORMAT=safetensors LAYERED_SUMMON=True TOTAL_TRAIN_STEPS=1 SAVE_FREQ=1 FSDP_SIZE=4 VERL_EXP_NAME="qwen2.5-0.5b-function-reward-minimal" bash tests/special_e2e/ppo_trainer/run_function_reward.sh + - name: Test GRPO LoRA checkpoints merging function + run: | + export EXP_NAME="qwen2.5-0.5b-function-reward-minimal" + ls checkpoints/verl-test/${EXP_NAME}/global_step_1/actor + cat checkpoints/verl-test/${EXP_NAME}/global_step_1/actor/huggingface/config.json + python3 -m verl.model_merger merge --backend fsdp --local_dir checkpoints/verl-test/${EXP_NAME}/global_step_1/actor/ --target_dir checkpoints/verl-test/${EXP_NAME}/global_step_1/actor/huggingface + - name: Running GSM8K E2E training tests on 8 L20 GPUs with grpo lora using function rm with use_shm and layered_summon with fsdp2 + run: | + ray stop --force + ADV_ESTIMATOR=grpo USE_SHM=True LORA_RANK=32 LOAD_FORMAT=safetensors LAYERED_SUMMON=True STRATEGY=fsdp2 bash tests/special_e2e/ppo_trainer/run_function_reward.sh + # Model RM + - name: Running GRPO GSM8K E2E training tests with FSDP on 8 L20 GPUs (DeepSeek) + run: | + ray stop --force + MODEL_ID=deepseek-ai/deepseek-coder-1.3b-instruct bash tests/special_e2e/ppo_trainer/run_function_reward.sh + - name: Running GSM8K E2E with rmpad using model rm + run: | + ray stop --force + bash tests/special_e2e/ppo_trainer/run_model_reward.sh + - name: Running GSM8K E2E without rmpad using model rm + run: | + ray stop --force + RM_PAD=False bash tests/special_e2e/ppo_trainer/run_model_reward.sh + - name: Running GSM8K E2E with rmpad using model rm and ulysses sp=2 + run: | + ray stop --force + SP_SIZE=2 bash tests/special_e2e/ppo_trainer/run_model_reward.sh + - name: Running GSM8K E2E with rmpad using model rm and dynamic batch size + run: | + ray stop --force + SEQ_BALANCE=True bash tests/special_e2e/ppo_trainer/run_model_reward.sh + - name: Running GSM8K E2E with rmpad using model rm with Liger Kernel enabled + run: | + ray stop --force + LIGER=True bash tests/special_e2e/ppo_trainer/run_model_reward.sh + - name: Running GSM8K E2E with rmpad using model rm with Fused Kernel enabled + run: | + ray stop --force + FUSED_KERNELS=True bash tests/special_e2e/ppo_trainer/run_model_reward.sh + - name: Running GSM8K E2E with rmpad using model rm with Fused Kernel enabled + run: | + ray stop --force + FUSED_KERNEL=True FUSED_KERNEL_BACKEND=triton bash tests/special_e2e/ppo_trainer/run_model_reward.sh + + e2e_ppo_trainer_vllm_vlm: + runs-on: [L20x8] + needs: pre_commit_for_ppo + timeout-minutes: 40 # Increase this timeout value as needed + env: + HTTP_PROXY: ${{ secrets.PROXY_HTTP }} + HTTPS_PROXY: ${{ secrets.PROXY_HTTPS }} + NO_PROXY: "localhost,127.0.0.1,hf-mirror.com" + HF_ENDPOINT: "https://hf-mirror.com" + HF_HUB_ENABLE_HF_TRANSFER: "0" # This is more stable + container: + image: verlai/verl:app-verl0.4-vllm0.8.5-mcore0.12.1 + options: --gpus all --shm-size=50g # Visual dataloader requires large memory + steps: + - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + with: + fetch-depth: 0 + - name: Install the current repository + run: | + pip3 install -e .[test,gpu,vllm,geo,trl] + pip install "transformers[hf_xet]<4.53.0" # Fix for transformers 4.53.0 + # Geo3k + - name: Prepare GEO3K dataset + run: | + ray stop --force + python3 examples/data_preprocess/geo3k.py + - name: Running GEO3K VLM GRPO E2E training tests on 8 L20 GPUs with rmpad using function rm + run: | + ray stop --force + TRAIN_FILES=$HOME/data/geo3k/train.parquet VAL_FILES=$HOME/data/geo3k/test.parquet \ + MAX_PROMPT_LEN=1536 MAX_RESPONSE_LEN=1536 \ + MODEL_ID=Qwen/Qwen2-VL-2B-Instruct \ + ADV_ESTIMATOR=grpo RM_PAD=True USE_KL=True ENABLE_CHUNKED_PREFILL=False \ + SP_SIZE=2 \ + bash tests/special_e2e/ppo_trainer/run_function_reward.sh + + - name: Running GEO3K VLM PPO E2E training tests on 8 L20 GPUs with rmpad using function rm + run: | + ray stop --force + TRAIN_FILES=$HOME/data/geo3k/train.parquet VAL_FILES=$HOME/data/geo3k/test.parquet \ + MAX_PROMPT_LEN=1536 MAX_RESPONSE_LEN=1536 \ + MODEL_ID=Qwen/Qwen2-VL-2B-Instruct \ + ADV_ESTIMATOR=gae RM_PAD=True USE_KL=True ENABLE_CHUNKED_PREFILL=False \ + SP_SIZE=2 \ + bash tests/special_e2e/ppo_trainer/run_function_reward.sh + - name: Running GEO3K VLM GRPO E2E lora training tests on 8 L20 GPUs with rmpad using function rm + run: | + ray stop --force + TRAIN_FILES=$HOME/data/geo3k/train.parquet VAL_FILES=$HOME/data/geo3k/test.parquet \ + MAX_PROMPT_LEN=1536 MAX_RESPONSE_LEN=1536 \ + MODEL_ID=Qwen/Qwen2-VL-2B-Instruct \ + ADV_ESTIMATOR=grpo RM_PAD=True USE_KL=True ENABLE_CHUNKED_PREFILL=False \ + SP_SIZE=2 \ + LORA_RANK=32 LORA_EXCLUDE=".*visual.*" \ + bash tests/special_e2e/ppo_trainer/run_function_reward.sh + + + e2e_ppo_trainer_sglang: + runs-on: [L20x8] + needs: pre_commit_for_ppo + timeout-minutes: 40 # Increase this timeout value as needed + env: + HTTP_PROXY: ${{ secrets.PROXY_HTTP }} + HTTPS_PROXY: ${{ secrets.PROXY_HTTPS }} + NO_PROXY: "localhost,127.0.0.1,hf-mirror.com" + HF_ENDPOINT: "https://hf-mirror.com" + HF_HUB_ENABLE_HF_TRANSFER: "0" # This is more stable + container: + image: verlai/verl:app-verl0.4-sglang0.4.6.post5-vllm0.8.5-mcore0.12.1 + options: --gpus all --shm-size=10g + steps: + - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + with: + fetch-depth: 0 + - name: Install the current repository + run: | + pip3 install -e .[test,gpu,sglang] --no-deps + - name: Prepare gsm8k dataset + run: | + ray stop --force + python3 examples/data_preprocess/gsm8k.py + - name: Running GSM8K E2E training tests on 8 L20 GPUs with rmpad using function rm and save ckpt + run: | + ray stop --force + ENGINE=sglang bash tests/special_e2e/ppo_trainer/run_function_reward.sh + - name: Running GSM8K E2E training tests on sglang async + run: | + ray stop --force + TOTAL_TRAIN_STEPS=2 ENGINE=sglang ROLLOUT_MODE=async bash tests/special_e2e/ppo_trainer/run_function_reward.sh + - name: Running GSM8K E2E training tests on vllm async + run: | + ray stop --force + export VLLM_USE_V1=1 + ray start --head + TOTAL_TRAIN_STEPS=2 ENGINE=vllm ROLLOUT_MODE=async bash tests/special_e2e/ppo_trainer/run_function_reward.sh + + e2e_ppo_trainer_sglang_multiturn_with_tool: + runs-on: [L20x8] + needs: pre_commit_for_ppo + timeout-minutes: 40 # Increase this timeout value as needed + env: + HTTP_PROXY: ${{ secrets.PROXY_HTTP }} + HTTPS_PROXY: ${{ secrets.PROXY_HTTPS }} + NO_PROXY: "localhost,127.0.0.1,hf-mirror.com" + HF_ENDPOINT: "https://hf-mirror.com" + HF_HUB_ENABLE_HF_TRANSFER: "0" # This is more stable + container: + image: verlai/verl:app-verl0.4-sglang0.4.6.post5-vllm0.8.5-mcore0.12.1 + options: --gpus all --shm-size=10g + steps: + - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + with: + fetch-depth: 0 + - name: Install the current repository + run: | + pip3 install -e .[test,gpu,sglang] --no-deps + - name: Prepare gsm8k dataset with tool + run: | + ray stop --force + python3 examples/data_preprocess/gsm8k_multiturn_w_tool.py --local_dir $HOME/data/gsm8k_verl_sgl_multi_turn_preprocessed + - name: Running GSM8K with tool E2E training tests on 8 L20 GPUs with rmpad using function rm and save ckpt with sglang + run: | + ray stop --force + bash tests/special_e2e/run_gsm8k_fsdp_sgl_multiturn_w_tool.sh + - name: Running GSM8K with tool E2E training tests with FSDP2 + run: | + ray stop --force + FSDP_STRATEGY=fsdp2 bash tests/special_e2e/run_gsm8k_fsdp_sgl_multiturn_w_tool.sh + + e2e_ppo_trainer_sglang_vlm: + runs-on: [L20x8] + needs: pre_commit_for_ppo + timeout-minutes: 60 # Increase this timeout value as needed + env: + HTTP_PROXY: ${{ secrets.PROXY_HTTP }} + HTTPS_PROXY: ${{ secrets.PROXY_HTTPS }} + NO_PROXY: "localhost,127.0.0.1,hf-mirror.com" + HF_ENDPOINT: "https://hf-mirror.com" + HF_HUB_ENABLE_HF_TRANSFER: "0" # This is more stable + container: + image: verlai/verl:app-verl0.4-sglang0.4.6.post5-vllm0.8.5-mcore0.12.1 + options: --gpus all --shm-size=50g # Visual dataloader requires large memory + steps: + - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + with: + fetch-depth: 0 + - name: Install the current repository + run: | + pip3 install -e .[test,geo,gpu,sglang] + # Geo3k + - name: Prepare GEO3K dataset + run: | + ray stop --force + python3 examples/data_preprocess/geo3k.py + - name: Running GEO3K VLM E2E training tests on 8 L20 GPUs with rmpad using function rm + run: | + ray stop --force + TRAIN_FILES=$HOME/data/geo3k/train.parquet VAL_FILES=$HOME/data/geo3k/test.parquet \ + MAX_PROMPT_LEN=1536 MAX_RESPONSE_LEN=1536 \ + MODEL_ID=Qwen/Qwen2-VL-2B-Instruct \ + ADV_ESTIMATOR=grpo RM_PAD=True USE_KL=True ENABLE_CHUNKED_PREFILL=False \ + ENGINE=sglang GPU_MEMORY_UTILIZATION=0.6 ACTOR_FSDP_PARAM_OFFLOAD=True \ + ACTOR_FSDP_OPTIMIZER_OFFLOAD=True REF_FSDP_PARAM_OFFLOAD=True \ + bash tests/special_e2e/ppo_trainer/run_function_reward.sh + - name: Running GEO3K VLM E2E with rmpad using torch fused kernel (Qwen2.5-VL) + run: | + ray stop --force + FUSED_KERNELS=True TRAIN_FILES=$HOME/data/geo3k/train.parquet VAL_FILES=$HOME/data/geo3k/test.parquet \ + MAX_PROMPT_LEN=1536 MAX_RESPONSE_LEN=1536 \ + MODEL_ID=Qwen/Qwen2.5-VL-3B-Instruct \ + ADV_ESTIMATOR=grpo RM_PAD=True USE_KL=True ENABLE_CHUNKED_PREFILL=False \ + ENGINE=sglang GPU_MEMORY_UTILIZATION=0.6 ACTOR_FSDP_PARAM_OFFLOAD=True \ + ACTOR_FSDP_OPTIMIZER_OFFLOAD=True REF_FSDP_PARAM_OFFLOAD=True \ + bash tests/special_e2e/ppo_trainer/run_function_reward.sh + - name: Running GEO3K VLM E2E with rmpad using triton fused kernel (Qwen2.5-VL) + run: | + ray stop --force + FUSED_KERNELS=True FUSED_KERNEL_BACKEND=triton \ + TRAIN_FILES=$HOME/data/geo3k/train.parquet VAL_FILES=$HOME/data/geo3k/test.parquet \ + MAX_PROMPT_LEN=1536 MAX_RESPONSE_LEN=1536 \ + MODEL_ID=Qwen/Qwen2.5-VL-3B-Instruct \ + ADV_ESTIMATOR=grpo RM_PAD=True USE_KL=True ENABLE_CHUNKED_PREFILL=False \ + ENGINE=sglang GPU_MEMORY_UTILIZATION=0.6 ACTOR_FSDP_PARAM_OFFLOAD=True \ + ACTOR_FSDP_OPTIMIZER_OFFLOAD=True REF_FSDP_PARAM_OFFLOAD=True \ + bash tests/special_e2e/ppo_trainer/run_function_reward.sh + + e2e_ppo_trainer_sglang_vlm_multiturn_with_tool: + runs-on: [L20x8] + needs: pre_commit_for_ppo + timeout-minutes: 40 # Increase this timeout value as needed + env: + HTTP_PROXY: ${{ secrets.PROXY_HTTP }} + HTTPS_PROXY: ${{ secrets.PROXY_HTTPS }} + NO_PROXY: "localhost,127.0.0.1,hf-mirror.com" + HF_ENDPOINT: "https://hf-mirror.com" + HF_HUB_ENABLE_HF_TRANSFER: "0" # This is more stable + container: + image: verlai/verl:app-verl0.4-sglang0.4.6.post5-vllm0.8.5-mcore0.12.1 + options: --gpus all --shm-size=10g + steps: + - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + with: + fetch-depth: 0 + - name: Install the current repository + run: | + pip3 install -e .[test,geo,gpu,sglang] + - name: Prepare geo3k dataset with tool + run: | + ray stop --force + python3 examples/data_preprocess/geo3k_multiturn_w_tool.py --local_dir $HOME/data/geo3k_verl_sgl_multi_turn_preprocessed + - name: Running GEO3K with tool E2E training tests on 8 L20 GPUs with rmpad using function rm and save ckpt with sglang + run: | + ray stop --force + bash tests/special_e2e/run_geo3k_fsdp_sgl_multiturn_w_tool.sh + - name: Running GEO3K with tool E2E training tests with FSDP2 + run: | + ray stop --force + FSDP_STRATEGY=fsdp2 bash tests/special_e2e/run_geo3k_fsdp_sgl_multiturn_w_tool.sh diff --git a/sk2decompile/verl/.github/workflows/e2e_ppo_trainer_megatron_sglang.yml b/sk2decompile/verl/.github/workflows/e2e_ppo_trainer_megatron_sglang.yml new file mode 100644 index 0000000..2e807d8 --- /dev/null +++ b/sk2decompile/verl/.github/workflows/e2e_ppo_trainer_megatron_sglang.yml @@ -0,0 +1,365 @@ +# # Tests layout + +# Each folder under tests/ corresponds to a test category for a sub-namespace in verl. For instance: +# - `tests/trainer` for testing functionality related to `verl/trainer` +# - `tests/models` for testing functionality related to `verl/models` +# - ... + +# There are a few folders with `special_` prefix, created for special purposes: +# - `special_distributed`: unit tests that must run with multiple GPUs +# - `special_e2e`: end-to-end tests with training/generation scripts +# - `special_npu`: tests for NPUs +# - `special_sanity`: a suite of quick sanity tests +# - `special_standalone`: a set of test that are designed to run in dedicated environments + +# Accelerators for tests +# - By default tests are run with GPU available, except for the ones under `special_npu`, and any test script whose name ends with `on_cpu.py`. +# - For test scripts with `on_cpu.py` name suffix would be tested on CPU resources in linux environment. + +# # Workflow layout + +# All CI tests are configured by yaml files in `.github/workflows/`. Here's an overview of all test configs: +# 1. A list of always triggered CPU sanity tests: `check-pr-title.yml`, `secrets_scan.yml`, `check-pr-title,yml`, `pre-commit.yml`, `doc.yml` +# 2. Some heavy multi-GPU unit tests, such as `model.yml`, `vllm.yml`, `sgl.yml` +# 3. End-to-end tests: `e2e_*.yml` +# 4. Unit tests +# - `cpu_unit_tests.yml`, run pytest on all scripts with file name pattern `tests/**/test_*_on_cpu.py` +# - `gpu_unit_tests.yml`, run pytest on all scripts with file without the `on_cpu.py` suffix. +# - Since cpu/gpu unit tests by default runs all tests under `tests`, please make sure tests are manually excluded in them when +# - new workflow yaml is added to `.github/workflows` +# - new tests are added to workflow mentioned in 2. + +name: e2e_ppo_trainer_megatron_sglang + +on: + # Trigger the workflow on push or pull request, + # but only for the main branch. + # For push, for now only anti-patterns are specified so it is more conservative + # and achieves higher coverage. + push: + branches: + - main + - v0.* + paths: + - "**/*.py" + # Other entrypoints + - "!verl/trainer/fsdp_sft_trainer.py" + # Recipes + - "!recipe/**" + # FSDP + - "!verl/workers/**/*dp_*.py" + pull_request: + branches: + - main + - v0.* + paths: + - "**/*.py" + # Other entrypoints + - "!docker/**" + # Docs + - "!**/*.md" + - "!docs/**" + - "!examples/**" + - "!tests/**" + - "!verl/trainer/main_*.py" + - "!verl/trainer/fsdp_sft_trainer.py" + # Recipes + - "!recipe/**" + # FSDP + - "!verl/workers/**/*dp_*.py" + # Entrypoints + - ".github/workflows/e2e_ppo_trainer_megatron_sglang.yml" + - "examples/data_preprocess/gsm8k.py" + - "examples/data_preprocess/geo3k.py" + - "tests/special_e2e/run_ppo_trainer_megatron.sh" + - "verl/trainer/main_ppo.py" + - "verl/trainer/config/ppo_megatron_trainer.yaml" + +# Cancel jobs on the same ref if a new one is triggered +concurrency: + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: ${{ github.ref != 'refs/heads/main' }} + +# Declare permissions just read content. +permissions: + contents: read + +env: + IMAGE: "verl-ci-cn-beijing.cr.volces.com/verlai/verl:app-verl0.4-sglang0.4.6.post5-vllm0.8.5-mcore0.12.1" + DYNAMIC_RUNNER_ENDPOINT: "https://sd10g3clalm04ug7alq90.apigateway-cn-beijing.volceapi.com/runner" + +jobs: + setup: + runs-on: ubuntu-latest + outputs: + runner-label: ${{ steps.create-runner.outputs.runner-label }} + mlp-task-id: ${{ steps.create-runner.outputs.mlp-task-id }} + steps: + - uses: actions/checkout@v4 + - id: create-runner + uses: volcengine/vemlp-github-runner@v1 + with: + mode: "create" + faas-url: "${{ env.DYNAMIC_RUNNER_ENDPOINT }}" + mlp-image: "${{ env.IMAGE }}" + + e2e_ppo_trainer_megatron-deepseek: + needs: setup + runs-on: ["${{ needs.setup.outputs.runner-label || 'L20x8' }}"] + timeout-minutes: 60 # Increase this timeout value as needed + env: + HTTP_PROXY: ${{ secrets.PROXY_HTTP }} + HTTPS_PROXY: ${{ secrets.PROXY_HTTPS }} + NO_PROXY: "localhost,127.0.0.1,hf-mirror.com" + HF_ENDPOINT: "https://hf-mirror.com" + HF_HUB_ENABLE_HF_TRANSFER: "0" # This is more stable + steps: + - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + with: + fetch-depth: 0 + - name: Install the current repository + run: | + pip3 install --no-deps -e .[test] + - name: Prepare GSM8K dataset + run: | + python3 examples/data_preprocess/gsm8k.py + - name: Running GSM8K E2E training tests with 3D parallelism on 8 L20 GPUs with Megatron (DeepSeek) + run: | + ray stop --force + ENGINE=sglang ALL_OFFLOAD=True SAVE_FREQ=1 MODEL_ID=deepseek-ai/deepseek-coder-1.3b-instruct bash tests/special_e2e/run_ppo_trainer_megatron.sh + - name: Running GSM8K E2E training tests with 3D parallelism on 8 L20 GPUs with Megatron (DeepSeek) + run: | + ray stop --force + export VLLM_USE_V1=1 + ray start --head + ENGINE=sglang MODE=async RESUME_MODE=auto MODEL_ID=deepseek-ai/deepseek-coder-1.3b-instruct TOTAL_TRAIN_STEPS=2 bash tests/special_e2e/run_ppo_trainer_megatron.sh + - name: Test Megatron checkpoints merging function (DeepSeek Actor and Critic) + run: | + exp_name="deepseek-coder-1.3b-instruct-megatron-gsm8k-minimal" + python -m verl.model_merger test --backend megatron --local_dir checkpoints/verl-test/${exp_name}/global_step_1/actor --test_hf_dir checkpoints/verl-test/${exp_name}/global_step_1/actor/huggingface + python -m verl.model_merger test --backend megatron --is-value-model --local_dir checkpoints/verl-test/${exp_name}/global_step_1/critic --test_hf_dir checkpoints/verl-test/${exp_name}/global_step_1/critic/huggingface + - name: Running GRPO GSM8K E2E training tests with 3D parallelism on 8 L20 GPUs with Megatron (Deepseek) + run: | + ray stop --force + ENGINE=sglang ADV_ESTIMATOR=grpo USE_DYNAMIC_BSZ=False MODEL_ID=deepseek-ai/deepseek-coder-1.3b-instruct bash tests/special_e2e/run_ppo_trainer_megatron.sh + - name: clean up + run: | + rm -rf checkpoints + e2e_ppo_trainer_megatron-qwen3: + needs: setup + runs-on: ["${{ needs.setup.outputs.runner-label || 'L20x8' }}"] + timeout-minutes: 60 # Increase this timeout value as needed + env: + HTTP_PROXY: ${{ secrets.PROXY_HTTP }} + HTTPS_PROXY: ${{ secrets.PROXY_HTTPS }} + NO_PROXY: "localhost,127.0.0.1,hf-mirror.com" + HF_ENDPOINT: "https://hf-mirror.com" + HF_HUB_ENABLE_HF_TRANSFER: "0" # This is more stable + steps: + - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + with: + fetch-depth: 0 + - name: Install the current repository + run: | + pip3 install --no-deps -e .[test] + - name: Prepare GSM8K dataset + run: | + python3 examples/data_preprocess/gsm8k.py + - name: Running GSM8K E2E training tests with 3D parallelism on 8 L20 GPUs with Megatron (Qwen3) with validation and saving + run: | + ray stop --force + ENGINE=sglang ALL_OFFLOAD=True VAL_BEFORE_TRAIN=True TEST_FREQ=1 SAVE_FREQ=1 MODEL_ID=Qwen/Qwen3-0.6B bash tests/special_e2e/run_ppo_trainer_megatron.sh + - name: Running GSM8K E2E training tests with 3D parallelism on 8 L20 GPUs with Megatron (Qwen3) testing learning rate scheduler + run: | + ray stop --force + ENGINE=sglang LR_WARMUP_STEPS=1 TOTAL_TRAIN_STEPS=2 MODEL_ID=Qwen/Qwen3-0.6B bash tests/special_e2e/run_ppo_trainer_megatron.sh + + - name: Test Megatron checkpoints merging function (Qwen3 Actor and Critic) + run: | + exp_name="qwen3-0.6b-megatron-gsm8k-minimal" + python -m verl.model_merger test --backend megatron --tie-word-embedding --local_dir checkpoints/verl-test/${exp_name}/global_step_1/actor --test_hf_dir checkpoints/verl-test/${exp_name}/global_step_1/actor/huggingface + python -m verl.model_merger test --backend megatron --is-value-model --local_dir checkpoints/verl-test/${exp_name}/global_step_1/critic --test_hf_dir checkpoints/verl-test/${exp_name}/global_step_1/critic/huggingface + - name: clean up + run: | + rm -rf checkpoints + e2e_ppo_trainer_megatron-different-train-infer-tp-qwen-tie-embedding: + needs: setup + runs-on: ["${{ needs.setup.outputs.runner-label || 'L20x8' }}"] + timeout-minutes: 60 # Increase this timeout value as needed + env: + HTTP_PROXY: ${{ secrets.PROXY_HTTP }} + HTTPS_PROXY: ${{ secrets.PROXY_HTTPS }} + NO_PROXY: "localhost,127.0.0.1,hf-mirror.com" + HF_ENDPOINT: "https://hf-mirror.com" + HF_HUB_ENABLE_HF_TRANSFER: "0" # This is more stable + steps: + - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + with: + fetch-depth: 0 + - name: Install the current repository + run: | + pip3 install --no-deps -e .[test] + - name: Prepare GSM8K dataset + run: | + python3 examples/data_preprocess/gsm8k.py + - name: Running GSM8K E2E training tests with 3D parallelism on 8 L20 GPUs with tie-embedding Megatron (Qwen) with train tp > infer tp + run: | + ray stop --force + ENGINE=sglang VAL_BEFORE_TRAIN=True TEST_FREQ=1 SAVE_FREQ=1 TRAIN_TP=2 INFER_TP=1 MODEL_ID=Qwen/Qwen2.5-1.5B bash tests/special_e2e/run_ppo_trainer_megatron.sh + - name: Running GSM8K E2E training tests with 3D parallelism on 8 L20 GPUs with Megatron (Qwen) with train tp < infer tp + run: | + ray stop --force + ENGINE=sglang VAL_BEFORE_TRAIN=True TEST_FREQ=1 SAVE_FREQ=1 TRAIN_TP=1 INFER_TP=2 MODEL_ID=Qwen/Qwen2.5-1.5B bash tests/special_e2e/run_ppo_trainer_megatron.sh + - name: clean up + run: | + rm -rf checkpoints + e2e_ppo_trainer_megatron-qwen-override-transformer-config: + needs: setup + runs-on: ["${{ needs.setup.outputs.runner-label || 'L20x8' }}"] + timeout-minutes: 60 # Increase this timeout value as needed + env: + HTTP_PROXY: ${{ secrets.PROXY_HTTP }} + HTTPS_PROXY: ${{ secrets.PROXY_HTTPS }} + NO_PROXY: "localhost,127.0.0.1,hf-mirror.com" + HF_ENDPOINT: "https://hf-mirror.com" + HF_HUB_ENABLE_HF_TRANSFER: "0" # This is more stable + steps: + - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + with: + fetch-depth: 0 + - name: Install the current repository + run: | + pip3 install --no-deps -e .[test] + - name: Prepare GSM8K dataset + run: | + python3 examples/data_preprocess/gsm8k.py + - name: Prepare dist_ckpt of Qwen2.5-0.5B, uneven layer distribution only supports dist_ckpt + run: | + python3 scripts/converter_hf_to_mcore.py --hf_model_path ${HOME}/models/Qwen/Qwen2.5-0.5B --output_path checkpoints/verl-test/qwen2.5-0.5b-megatron + - name: Running GSM8K E2E training tests with 3D parallelism on 8 L20 GPUs with Megatron (Qwen) + run: | + ray stop --force + ENGINE=sglang SAVE_FREQ=1 COMMON_PP=4 COMMON_VPP=null COMMON_CP=1 SKIP_SAVE_HF_MODEL=1 bash tests/special_e2e/run_ppo_trainer_megatron.sh +actor_rollout_ref.actor.megatron.override_transformer_config.num_layers_in_first_pipeline_stage=8 +actor_rollout_ref.actor.megatron.override_transformer_config.num_layers_in_last_pipeline_stage=4 actor_rollout_ref.actor.megatron.use_dist_checkpointing=true actor_rollout_ref.actor.megatron.dist_checkpointing_path=checkpoints/verl-test/qwen2.5-0.5b-megatron actor_rollout_ref.ref.megatron.use_dist_checkpointing=true actor_rollout_ref.ref.megatron.dist_checkpointing_path=checkpoints/verl-test/qwen2.5-0.5b-megatron critic.megatron.use_dist_checkpointing=true critic.megatron.dist_checkpointing_path=checkpoints/verl-test/qwen2.5-0.5b-megatron reward_model.megatron.use_dist_checkpointing=true reward_model.megatron.dist_checkpointing_path=checkpoints/verl-test/qwen2.5-0.5b-megatron + cp -r checkpoints checkpoints-dut + ENGINE=sglang SAVE_FREQ=1 COMMON_PP=4 COMMON_VPP=null COMMON_CP=1 bash tests/special_e2e/run_ppo_trainer_megatron.sh + - name: Test Megatron checkpoints merging function (Qwen Actor and Critic) + run: | + exp_name="qwen2.5-0.5b-megatron-gsm8k-minimal" + python -m verl.model_merger test --backend megatron --tie-word-embedding --local_dir checkpoints-dut/verl-test/${exp_name}/global_step_1/actor --test_hf_dir checkpoints/verl-test/${exp_name}/global_step_1/actor/huggingface + python -m verl.model_merger test --backend megatron --is-value-model --local_dir checkpoints-dut/verl-test/${exp_name}/global_step_1/critic --test_hf_dir checkpoints/verl-test/${exp_name}/global_step_1/critic/huggingface + - name: clean up + run: | + rm -rf checkpoints + e2e_ppo_trainer_megatron-deepseek-override-transformer-config: + needs: setup + runs-on: ["${{ needs.setup.outputs.runner-label || 'L20x8' }}"] + timeout-minutes: 60 # Increase this timeout value as needed + env: + HTTP_PROXY: ${{ secrets.PROXY_HTTP }} + HTTPS_PROXY: ${{ secrets.PROXY_HTTPS }} + NO_PROXY: "localhost,127.0.0.1,hf-mirror.com" + HF_ENDPOINT: "https://hf-mirror.com" + HF_HUB_ENABLE_HF_TRANSFER: "0" # This is more stable + steps: + - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + with: + fetch-depth: 0 + - name: Install the current repository + run: | + pip3 install --no-deps -e .[test] + - name: Prepare GSM8K dataset + run: | + python3 examples/data_preprocess/gsm8k.py + - name: Running GSM8K E2E training tests with 3D parallelism on 8 L20 GPUs with Megatron (DeepSeek) + run: | + ray stop --force + ENGINE=sglang SAVE_FREQ=1 MODEL_ID=deepseek-ai/deepseek-coder-1.3b-instruct COMMON_PP=2 COMMON_VPP=null bash tests/special_e2e/run_ppo_trainer_megatron.sh +actor_rollout_ref.actor.megatron.override_transformer_config.account_for_embedding_in_pipeline_split=true +actor_rollout_ref.actor.megatron.override_transformer_config.account_for_loss_in_pipeline_split=true + - name: Test Megatron checkpoints merging function (DeepSeek Actor and Critic) + run: | + exp_name="deepseek-coder-1.3b-instruct-megatron-gsm8k-minimal" + python -m verl.model_merger test --backend megatron --local_dir checkpoints/verl-test/${exp_name}/global_step_1/actor --test_hf_dir checkpoints/verl-test/${exp_name}/global_step_1/actor/huggingface + python -m verl.model_merger test --backend megatron --is-value-model --local_dir checkpoints/verl-test/${exp_name}/global_step_1/critic --test_hf_dir checkpoints/verl-test/${exp_name}/global_step_1/critic/huggingface + - name: clean up + run: | + rm -rf checkpoints + e2e_ppo_trainer_megatron-moe-expert-parallel: + needs: setup + runs-on: ["${{ needs.setup.outputs.runner-label || 'L20x8' }}"] + timeout-minutes: 60 # Increase this timeout value as needed + env: + HTTP_PROXY: ${{ secrets.PROXY_HTTP }} + HTTPS_PROXY: ${{ secrets.PROXY_HTTPS }} + NO_PROXY: "localhost,127.0.0.1,hf-mirror.com" + HF_ENDPOINT: "https://hf-mirror.com" + HF_HUB_ENABLE_HF_TRANSFER: "0" # This is more stable + steps: + - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + with: + fetch-depth: 0 + - name: Install the current repository + run: | + pip3 install --no-deps -e .[test] + - name: Prepare GSM8K dataset + run: | + python3 examples/data_preprocess/gsm8k.py + - name: Running GSM8K E2E training tests with 3D parallelism on 8 L20 GPUs with Megatron (DeepSeek) + run: | + ray stop --force + ADV_ESTIMATOR=grpo USE_DUMMY_MODEL=True DUMMY_MODEL_CONFIG_PATH=tests/special_e2e/ppo_trainer/expert_parallel/qwen2moe_minimal.json \ + PPO_MAX_TOKEN_LEN=512 FWD_MAX_TOKEN_LEN=512 \ + MAX_PROMPT_LENGTH=256 MAX_RESPONSE_LENGTH=256 \ + MODEL_ID=Qwen/Qwen1.5-MoE-A2.7B-Chat \ + ENGINE=sglang COMMON_PP=2 COMMON_VPP=null COMMON_CP=1 COMMON_TP=4 COMMON_EP=4 COMMON_ETP=1 INFER_TP=8 \ + USE_DIST_CKPT=True ALL_OFFLOAD=True SKIP_SAVE_HF_MODEL=1 bash tests/special_e2e/run_ppo_trainer_megatron.sh + - name: clean up + run: | + rm -rf checkpoints + e2e_ppo_trainer_megatron-qwen2_5vl-3b: + needs: setup + runs-on: ["${{ needs.setup.outputs.runner-label || 'L20x8' }}"] + timeout-minutes: 60 # Increase this timeout value as needed + env: + HTTP_PROXY: ${{ secrets.PROXY_HTTP }} + HTTPS_PROXY: ${{ secrets.PROXY_HTTPS }} + NO_PROXY: "localhost,127.0.0.1,hf-mirror.com" + HF_ENDPOINT: "https://hf-mirror.com" + HF_HUB_ENABLE_HF_TRANSFER: "0" # This is more stable + steps: + - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + with: + fetch-depth: 0 + - name: Install the current repository + run: | + pip3 install --no-deps -e .[test] + - name: Prepare Geo3k dataset + run: | + python3 examples/data_preprocess/geo3k.py + - name: Prepare dist_ckpt of Qwen2.5-VL-3B, only supports dist_ckpt + run: | + python3 scripts/converter_hf_to_mcore.py --hf_model_path ${HOME}/models/Qwen/Qwen2.5-VL-3B-Instruct --output_path checkpoints/verl-test/qwen2.5-vl-3b-megatron + - name: Running Geo3k E2E training tests with 3D parallelism on 8 L20 GPUs with Megatron (Qwen) + run: | + ray stop --force + ENGINE=sglang TRAIN_FILES=${HOME}/data/geo3k/train.parquet VAL_FILES=${HOME}/data/geo3k/test.parquet MAX_PROMPT_LENGTH=1024 MAX_RESPONSE_LENGTH=2048 MODEL_ID=Qwen/Qwen2.5-VL-3B-Instruct ADV_ESTIMATOR=grpo USE_DYNAMIC_BSZ=False SKIP_SAVE_HF_MODEL=1 COMMON_PP=4 COMMON_VPP=null COMMON_CP=1 COMMON_TP=2 USE_DIST_CKPT=true DIST_CKPT_PATH=checkpoints/verl-test/qwen2.5-vl-3b-megatron bash tests/special_e2e/run_ppo_trainer_megatron.sh + - name: clean up + run: | + rm -rf checkpoints + + cleanup: + runs-on: ubuntu-latest + needs: [setup, + e2e_ppo_trainer_megatron-deepseek, + e2e_ppo_trainer_megatron-qwen3, + e2e_ppo_trainer_megatron-different-train-infer-tp-qwen-tie-embedding, + e2e_ppo_trainer_megatron-qwen-override-transformer-config, + e2e_ppo_trainer_megatron-deepseek-override-transformer-config, + e2e_ppo_trainer_megatron-moe-expert-parallel, + e2e_ppo_trainer_megatron-qwen2_5vl-3b] + if: always() + steps: + - id: destroy-runner + uses: volcengine/vemlp-github-runner@v1 + with: + mode: "destroy" + faas-url: "${{ env.DYNAMIC_RUNNER_ENDPOINT }}" + mlp-task-id: "${{ needs.setup.outputs.mlp-task-id }}" \ No newline at end of file diff --git a/sk2decompile/verl/.github/workflows/e2e_ppo_trainer_megatron_vllm.yml b/sk2decompile/verl/.github/workflows/e2e_ppo_trainer_megatron_vllm.yml new file mode 100644 index 0000000..96ec154 --- /dev/null +++ b/sk2decompile/verl/.github/workflows/e2e_ppo_trainer_megatron_vllm.yml @@ -0,0 +1,367 @@ +# # Tests layout + +# Each folder under tests/ corresponds to a test category for a sub-namespace in verl. For instance: +# - `tests/trainer` for testing functionality related to `verl/trainer` +# - `tests/models` for testing functionality related to `verl/models` +# - ... + +# There are a few folders with `special_` prefix, created for special purposes: +# - `special_distributed`: unit tests that must run with multiple GPUs +# - `special_e2e`: end-to-end tests with training/generation scripts +# - `special_npu`: tests for NPUs +# - `special_sanity`: a suite of quick sanity tests +# - `special_standalone`: a set of test that are designed to run in dedicated environments + +# Accelerators for tests +# - By default tests are run with GPU available, except for the ones under `special_npu`, and any test script whose name ends with `on_cpu.py`. +# - For test scripts with `on_cpu.py` name suffix would be tested on CPU resources in linux environment. + +# # Workflow layout + +# All CI tests are configured by yaml files in `.github/workflows/`. Here's an overview of all test configs: +# 1. A list of always triggered CPU sanity tests: `check-pr-title.yml`, `secrets_scan.yml`, `check-pr-title,yml`, `pre-commit.yml`, `doc.yml` +# 2. Some heavy multi-GPU unit tests, such as `model.yml`, `vllm.yml`, `sgl.yml` +# 3. End-to-end tests: `e2e_*.yml` +# 4. Unit tests +# - `cpu_unit_tests.yml`, run pytest on all scripts with file name pattern `tests/**/test_*_on_cpu.py` +# - `gpu_unit_tests.yml`, run pytest on all scripts with file without the `on_cpu.py` suffix. +# - Since cpu/gpu unit tests by default runs all tests under `tests`, please make sure tests are manually excluded in them when +# - new workflow yaml is added to `.github/workflows` +# - new tests are added to workflow mentioned in 2. + +name: e2e_ppo_trainer_megatron_vllm + +on: + # Trigger the workflow on push or pull request, + # but only for the main branch. + # For push, for now only anti-patterns are specified so it is more conservative + # and achieves higher coverage. + push: + branches: + - main + - v0.* + paths: + - "**/*.py" + # Other entrypoints + - "!verl/trainer/fsdp_sft_trainer.py" + # Recipes + - "!recipe/**" + # FSDP + - "!verl/workers/**/*dp_*.py" + pull_request: + branches: + - main + - v0.* + paths: + - "**/*.py" + # Other entrypoints + - "!docker/**" + # Docs + - "!**/*.md" + - "!docs/**" + - "!examples/**" + - "!tests/**" + - "!verl/trainer/main_*.py" + - "!verl/trainer/fsdp_sft_trainer.py" + # Recipes + - "!recipe/**" + # FSDP + - "!verl/workers/**/*dp_*.py" + # Entrypoints + - ".github/workflows/e2e_ppo_trainer_megatron_vllm.yml" + - "examples/data_preprocess/gsm8k.py" + - "examples/data_preprocess/geo3k.py" + - "tests/special_e2e/run_ppo_trainer_megatron.sh" + - "verl/trainer/main_ppo.py" + - "verl/trainer/config/ppo_megatron_trainer.yaml" + +# Cancel jobs on the same ref if a new one is triggered +concurrency: + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: ${{ github.ref != 'refs/heads/main' }} + +# Declare permissions just read content. +permissions: + contents: read + +env: + IMAGE: "verl-ci-cn-beijing.cr.volces.com/verlai/verl:app-verl0.4-vllm0.8.5-mcore0.12.1" + DYNAMIC_RUNNER_ENDPOINT: "https://sd10g3clalm04ug7alq90.apigateway-cn-beijing.volceapi.com/runner" + +jobs: + setup: + runs-on: ubuntu-latest + outputs: + runner-label: ${{ steps.create-runner.outputs.runner-label }} + mlp-task-id: ${{ steps.create-runner.outputs.mlp-task-id }} + steps: + - uses: actions/checkout@v4 + - id: create-runner + uses: volcengine/vemlp-github-runner@v1 + with: + mode: "create" + faas-url: "${{ env.DYNAMIC_RUNNER_ENDPOINT }}" + mlp-image: "${{ env.IMAGE }}" + + e2e_ppo_trainer_megatron-deepseek: + needs: setup + runs-on: ["${{ needs.setup.outputs.runner-label || 'L20x8' }}"] + timeout-minutes: 60 # Increase this timeout value as needed + env: + HTTP_PROXY: ${{ secrets.PROXY_HTTP }} + HTTPS_PROXY: ${{ secrets.PROXY_HTTPS }} + NO_PROXY: "localhost,127.0.0.1,hf-mirror.com" + HF_ENDPOINT: "https://hf-mirror.com" + HF_HUB_ENABLE_HF_TRANSFER: "0" # This is more stable + steps: + - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + with: + fetch-depth: 0 + - name: Install the current repository + run: | + pip3 install --no-deps -e .[test] + - name: Prepare GSM8K dataset + run: | + python3 examples/data_preprocess/gsm8k.py + - name: Running GSM8K E2E training tests with 3D parallelism on 8 L20 GPUs with Megatron (DeepSeek) + run: | + ray stop --force + ALL_OFFLOAD=True SAVE_FREQ=1 MODEL_ID=deepseek-ai/deepseek-coder-1.3b-instruct bash tests/special_e2e/run_ppo_trainer_megatron.sh + - name: Running GSM8K E2E training tests with 3D parallelism on 8 L20 GPUs with Megatron (DeepSeek) + run: | + ray stop --force + export VLLM_USE_V1=1 + ray start --head + MODE=async RESUME_MODE=auto MODEL_ID=deepseek-ai/deepseek-coder-1.3b-instruct TOTAL_TRAIN_STEPS=2 bash tests/special_e2e/run_ppo_trainer_megatron.sh + - name: Test Megatron checkpoints merging function (DeepSeek Actor and Critic) + run: | + exp_name="deepseek-coder-1.3b-instruct-megatron-gsm8k-minimal" + python -m verl.model_merger test --backend megatron --local_dir checkpoints/verl-test/${exp_name}/global_step_1/actor --test_hf_dir checkpoints/verl-test/${exp_name}/global_step_1/actor/huggingface + python -m verl.model_merger test --backend megatron --is-value-model --local_dir checkpoints/verl-test/${exp_name}/global_step_1/critic --test_hf_dir checkpoints/verl-test/${exp_name}/global_step_1/critic/huggingface + - name: Running GRPO GSM8K E2E training tests with 3D parallelism on 8 L20 GPUs with Megatron (Deepseek) + run: | + ray stop --force + ADV_ESTIMATOR=grpo USE_DYNAMIC_BSZ=False MODEL_ID=deepseek-ai/deepseek-coder-1.3b-instruct bash tests/special_e2e/run_ppo_trainer_megatron.sh + - name: clean up + run: | + rm -rf checkpoints + e2e_ppo_trainer_megatron-qwen3: + needs: setup + runs-on: ["${{ needs.setup.outputs.runner-label || 'L20x8' }}"] + timeout-minutes: 60 # Increase this timeout value as needed + env: + HTTP_PROXY: ${{ secrets.PROXY_HTTP }} + HTTPS_PROXY: ${{ secrets.PROXY_HTTPS }} + NO_PROXY: "localhost,127.0.0.1,hf-mirror.com" + HF_ENDPOINT: "https://hf-mirror.com" + HF_HUB_ENABLE_HF_TRANSFER: "0" # This is more stable + steps: + - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + with: + fetch-depth: 0 + - name: Install the current repository + run: | + pip3 install --no-deps -e .[test] + - name: Prepare GSM8K dataset + run: | + python3 examples/data_preprocess/gsm8k.py + - name: Running GSM8K E2E training tests with 3D parallelism on 8 L20 GPUs with Megatron (Qwen3) with validation and saving + run: | + ray stop --force + ALL_OFFLOAD=True VAL_BEFORE_TRAIN=True TEST_FREQ=1 SAVE_FREQ=1 MODEL_ID=Qwen/Qwen3-0.6B bash tests/special_e2e/run_ppo_trainer_megatron.sh + - name: Running GSM8K E2E training tests with 3D parallelism on 8 L20 GPUs with Megatron (Qwen3) testing learning rate scheduler + run: | + ray stop --force + LR_WARMUP_STEPS=1 TOTAL_TRAIN_STEPS=2 MODEL_ID=Qwen/Qwen3-0.6B bash tests/special_e2e/run_ppo_trainer_megatron.sh + + - name: Test Megatron checkpoints merging function (Qwen3 Actor and Critic) + run: | + exp_name="qwen3-0.6b-megatron-gsm8k-minimal" + python -m verl.model_merger test --backend megatron --tie-word-embedding --local_dir checkpoints/verl-test/${exp_name}/global_step_1/actor --test_hf_dir checkpoints/verl-test/${exp_name}/global_step_1/actor/huggingface + python -m verl.model_merger test --backend megatron --is-value-model --local_dir checkpoints/verl-test/${exp_name}/global_step_1/critic --test_hf_dir checkpoints/verl-test/${exp_name}/global_step_1/critic/huggingface + - name: clean up + run: | + rm -rf checkpoints + e2e_ppo_trainer_megatron-different-train-infer-tp-qwen-tie-embedding: + needs: setup + runs-on: ["${{ needs.setup.outputs.runner-label || 'L20x8' }}"] + timeout-minutes: 60 # Increase this timeout value as needed + env: + HTTP_PROXY: ${{ secrets.PROXY_HTTP }} + HTTPS_PROXY: ${{ secrets.PROXY_HTTPS }} + NO_PROXY: "localhost,127.0.0.1,hf-mirror.com" + HF_ENDPOINT: "https://hf-mirror.com" + HF_HUB_ENABLE_HF_TRANSFER: "0" # This is more stable + steps: + - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + with: + fetch-depth: 0 + - name: Install the current repository + run: | + pip3 install --no-deps -e .[test] + - name: Prepare GSM8K dataset + run: | + python3 examples/data_preprocess/gsm8k.py + - name: Running GSM8K E2E training tests with 3D parallelism on 8 L20 GPUs with tie-embedding Megatron (Qwen) with train tp > infer tp + run: | + ray stop --force + VAL_BEFORE_TRAIN=True TEST_FREQ=1 SAVE_FREQ=1 TRAIN_TP=2 INFER_TP=1 MODEL_ID=Qwen/Qwen2.5-1.5B bash tests/special_e2e/run_ppo_trainer_megatron.sh + - name: Running GSM8K E2E training tests with 3D parallelism on 8 L20 GPUs with Megatron (Qwen) with train tp < infer tp + run: | + ray stop --force + VAL_BEFORE_TRAIN=True TEST_FREQ=1 SAVE_FREQ=1 TRAIN_TP=1 INFER_TP=2 MODEL_ID=Qwen/Qwen2.5-1.5B bash tests/special_e2e/run_ppo_trainer_megatron.sh + - name: clean up + run: | + rm -rf checkpoints + e2e_ppo_trainer_megatron-qwen-override-transformer-config: + needs: setup + runs-on: ["${{ needs.setup.outputs.runner-label || 'L20x8' }}"] + timeout-minutes: 60 # Increase this timeout value as needed + env: + HTTP_PROXY: ${{ secrets.PROXY_HTTP }} + HTTPS_PROXY: ${{ secrets.PROXY_HTTPS }} + NO_PROXY: "localhost,127.0.0.1,hf-mirror.com" + HF_ENDPOINT: "https://hf-mirror.com" + HF_HUB_ENABLE_HF_TRANSFER: "0" # This is more stable + steps: + - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + with: + fetch-depth: 0 + - name: Install the current repository + run: | + pip3 install --no-deps -e .[test] + - name: Prepare GSM8K dataset + run: | + python3 examples/data_preprocess/gsm8k.py + - name: Prepare dist_ckpt of Qwen2.5-0.5B, uneven layer distribution only supports dist_ckpt + run: | + python3 scripts/converter_hf_to_mcore.py --hf_model_path ${HOME}/models/Qwen/Qwen2.5-0.5B --output_path checkpoints/verl-test/qwen2.5-0.5b-megatron + - name: Running GSM8K E2E training tests with 3D parallelism on 8 L20 GPUs with Megatron (Qwen) + run: | + ray stop --force + SAVE_FREQ=1 COMMON_PP=4 COMMON_VPP=null COMMON_CP=1 SKIP_SAVE_HF_MODEL=1 bash tests/special_e2e/run_ppo_trainer_megatron.sh +actor_rollout_ref.actor.megatron.override_transformer_config.num_layers_in_first_pipeline_stage=8 +actor_rollout_ref.actor.megatron.override_transformer_config.num_layers_in_last_pipeline_stage=4 actor_rollout_ref.actor.megatron.use_dist_checkpointing=true actor_rollout_ref.actor.megatron.dist_checkpointing_path=checkpoints/verl-test/qwen2.5-0.5b-megatron actor_rollout_ref.ref.megatron.use_dist_checkpointing=true actor_rollout_ref.ref.megatron.dist_checkpointing_path=checkpoints/verl-test/qwen2.5-0.5b-megatron critic.megatron.use_dist_checkpointing=true critic.megatron.dist_checkpointing_path=checkpoints/verl-test/qwen2.5-0.5b-megatron reward_model.megatron.use_dist_checkpointing=true reward_model.megatron.dist_checkpointing_path=checkpoints/verl-test/qwen2.5-0.5b-megatron + cp -r checkpoints checkpoints-dut + SAVE_FREQ=1 COMMON_PP=4 COMMON_VPP=null COMMON_CP=1 bash tests/special_e2e/run_ppo_trainer_megatron.sh + - name: Test Megatron checkpoints merging function (Qwen Actor and Critic) + run: | + exp_name="qwen2.5-0.5b-megatron-gsm8k-minimal" + python -m verl.model_merger test --backend megatron --tie-word-embedding --local_dir checkpoints-dut/verl-test/${exp_name}/global_step_1/actor --test_hf_dir checkpoints/verl-test/${exp_name}/global_step_1/actor/huggingface + python -m verl.model_merger test --backend megatron --is-value-model --local_dir checkpoints-dut/verl-test/${exp_name}/global_step_1/critic --test_hf_dir checkpoints/verl-test/${exp_name}/global_step_1/critic/huggingface + - name: clean up + run: | + rm -rf checkpoints + e2e_ppo_trainer_megatron-deepseek-override-transformer-config: + needs: setup + runs-on: ["${{ needs.setup.outputs.runner-label || 'L20x8' }}"] + timeout-minutes: 60 # Increase this timeout value as needed + env: + HTTP_PROXY: ${{ secrets.PROXY_HTTP }} + HTTPS_PROXY: ${{ secrets.PROXY_HTTPS }} + NO_PROXY: "localhost,127.0.0.1,hf-mirror.com" + HF_ENDPOINT: "https://hf-mirror.com" + HF_HUB_ENABLE_HF_TRANSFER: "0" # This is more stable + steps: + - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + with: + fetch-depth: 0 + - name: Install the current repository + run: | + pip3 install --no-deps -e .[test] + - name: Prepare GSM8K dataset + run: | + python3 examples/data_preprocess/gsm8k.py + - name: Running GSM8K E2E training tests with 3D parallelism on 8 L20 GPUs with Megatron (DeepSeek) + run: | + ray stop --force + SAVE_FREQ=1 MODEL_ID=deepseek-ai/deepseek-coder-1.3b-instruct COMMON_PP=2 COMMON_VPP=null bash tests/special_e2e/run_ppo_trainer_megatron.sh +actor_rollout_ref.actor.megatron.override_transformer_config.account_for_embedding_in_pipeline_split=true +actor_rollout_ref.actor.megatron.override_transformer_config.account_for_loss_in_pipeline_split=true + - name: Test Megatron checkpoints merging function (DeepSeek Actor and Critic) + run: | + exp_name="deepseek-coder-1.3b-instruct-megatron-gsm8k-minimal" + python -m verl.model_merger test --backend megatron --local_dir checkpoints/verl-test/${exp_name}/global_step_1/actor --test_hf_dir checkpoints/verl-test/${exp_name}/global_step_1/actor/huggingface + python -m verl.model_merger test --backend megatron --is-value-model --local_dir checkpoints/verl-test/${exp_name}/global_step_1/critic --test_hf_dir checkpoints/verl-test/${exp_name}/global_step_1/critic/huggingface + - name: clean up + run: | + rm -rf checkpoints + e2e_ppo_trainer_megatron-moe-expert-parallel: + needs: setup + runs-on: ["${{ needs.setup.outputs.runner-label || 'L20x8' }}"] + timeout-minutes: 60 # Increase this timeout value as needed + env: + HTTP_PROXY: ${{ secrets.PROXY_HTTP }} + HTTPS_PROXY: ${{ secrets.PROXY_HTTPS }} + NO_PROXY: "localhost,127.0.0.1,hf-mirror.com" + HF_ENDPOINT: "https://hf-mirror.com" + HF_HUB_ENABLE_HF_TRANSFER: "0" # This is more stable + steps: + - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + with: + fetch-depth: 0 + - name: Install the current repository + run: | + pip3 install --no-deps -e .[test] + pip3 install mbridge + - name: Prepare GSM8K dataset + run: | + python3 examples/data_preprocess/gsm8k.py + - name: Running GSM8K E2E training tests with 3D parallelism on 8 L20 GPUs with Megatron (DeepSeek) + run: | + ray stop --force + ADV_ESTIMATOR=grpo USE_DUMMY_MODEL=True DUMMY_MODEL_CONFIG_PATH=tests/special_e2e/ppo_trainer/expert_parallel/qwen2moe_minimal.json \ + PPO_MAX_TOKEN_LEN=512 FWD_MAX_TOKEN_LEN=512 \ + MAX_PROMPT_LENGTH=256 MAX_RESPONSE_LENGTH=256 \ + MODEL_ID=Qwen/Qwen1.5-MoE-A2.7B-Chat USE_MBRIDGE=True \ + COMMON_PP=2 COMMON_VPP=null COMMON_CP=1 COMMON_TP=4 COMMON_EP=4 COMMON_ETP=1 INFER_TP=8 \ + USE_DIST_CKPT=True ALL_OFFLOAD=True SKIP_SAVE_HF_MODEL=1 bash tests/special_e2e/run_ppo_trainer_megatron.sh + - name: clean up + run: | + rm -rf checkpoints + e2e_ppo_trainer_megatron-qwen2_5vl-3b: + needs: setup + runs-on: ["${{ needs.setup.outputs.runner-label || 'L20x8' }}"] + timeout-minutes: 60 # Increase this timeout value as needed + env: + HTTP_PROXY: ${{ secrets.PROXY_HTTP }} + HTTPS_PROXY: ${{ secrets.PROXY_HTTPS }} + NO_PROXY: "localhost,127.0.0.1,hf-mirror.com" + HF_ENDPOINT: "https://hf-mirror.com" + HF_HUB_ENABLE_HF_TRANSFER: "0" # This is more stable + steps: + - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + with: + fetch-depth: 0 + - name: Install the current repository + run: | + pip3 install --no-deps -e .[test] + pip3 install "transformers[hf_xet]<4.52.0" + - name: Prepare Geo3k dataset + run: | + python3 examples/data_preprocess/geo3k.py + - name: Prepare dist_ckpt of Qwen2.5-VL-3B, only supports dist_ckpt + run: | + python3 scripts/converter_hf_to_mcore.py --hf_model_path ${HOME}/models/Qwen/Qwen2.5-VL-3B-Instruct --output_path checkpoints/verl-test/qwen2.5-vl-3b-megatron + - name: Running Geo3k E2E training tests with 3D parallelism on 8 L20 GPUs with Megatron (Qwen) + run: | + ray stop --force + TRAIN_FILES=${HOME}/data/geo3k/train.parquet VAL_FILES=${HOME}/data/geo3k/test.parquet MAX_PROMPT_LENGTH=1024 MAX_RESPONSE_LENGTH=2048 MODEL_ID=Qwen/Qwen2.5-VL-3B-Instruct ADV_ESTIMATOR=grpo USE_DYNAMIC_BSZ=False SKIP_SAVE_HF_MODEL=1 COMMON_PP=4 COMMON_VPP=null COMMON_CP=1 COMMON_TP=2 USE_DIST_CKPT=true DIST_CKPT_PATH=checkpoints/verl-test/qwen2.5-vl-3b-megatron bash tests/special_e2e/run_ppo_trainer_megatron.sh + - name: clean up + run: | + rm -rf checkpoints + + cleanup: + runs-on: ubuntu-latest + needs: [setup, + e2e_ppo_trainer_megatron-deepseek, + e2e_ppo_trainer_megatron-qwen3, + e2e_ppo_trainer_megatron-different-train-infer-tp-qwen-tie-embedding, + e2e_ppo_trainer_megatron-qwen-override-transformer-config, + e2e_ppo_trainer_megatron-deepseek-override-transformer-config, + e2e_ppo_trainer_megatron-moe-expert-parallel, + e2e_ppo_trainer_megatron-qwen2_5vl-3b] + if: always() + steps: + - id: destroy-runner + uses: volcengine/vemlp-github-runner@v1 + with: + mode: "destroy" + faas-url: "${{ env.DYNAMIC_RUNNER_ENDPOINT }}" + mlp-task-id: "${{ needs.setup.outputs.mlp-task-id }}" \ No newline at end of file diff --git a/sk2decompile/verl/.github/workflows/e2e_sft.yml b/sk2decompile/verl/.github/workflows/e2e_sft.yml new file mode 100644 index 0000000..1e62d1f --- /dev/null +++ b/sk2decompile/verl/.github/workflows/e2e_sft.yml @@ -0,0 +1,148 @@ +# # Tests layout + +# Each folder under tests/ corresponds to a test category for a sub-namespace in verl. For instance: +# - `tests/trainer` for testing functionality related to `verl/trainer` +# - `tests/models` for testing functionality related to `verl/models` +# - ... + +# There are a few folders with `special_` prefix, created for special purposes: +# - `special_distributed`: unit tests that must run with multiple GPUs +# - `special_e2e`: end-to-end tests with training/generation scripts +# - `special_npu`: tests for NPUs +# - `special_sanity`: a suite of quick sanity tests +# - `special_standalone`: a set of test that are designed to run in dedicated environments + +# Accelerators for tests +# - By default tests are run with GPU available, except for the ones under `special_npu`, and any test script whose name ends with `on_cpu.py`. +# - For test scripts with `on_cpu.py` name suffix would be tested on CPU resources in linux environment. + +# # Workflow layout + +# All CI tests are configured by yaml files in `.github/workflows/`. Here's an overview of all test configs: +# 1. A list of always triggered CPU sanity tests: `check-pr-title.yml`, `secrets_scan.yml`, `check-pr-title,yml`, `pre-commit.yml`, `doc.yml` +# 2. Some heavy multi-GPU unit tests, such as `model.yml`, `vllm.yml`, `sgl.yml` +# 3. End-to-end tests: `e2e_*.yml` +# 4. Unit tests +# - `cpu_unit_tests.yml`, run pytest on all scripts with file name pattern `tests/**/test_*_on_cpu.py` +# - `gpu_unit_tests.yml`, run pytest on all scripts with file without the `on_cpu.py` suffix. +# - Since cpu/gpu unit tests by default runs all tests under `tests`, please make sure tests are manually excluded in them when +# - new workflow yaml is added to `.github/workflows` +# - new tests are added to workflow mentioned in 2. + +name: e2e_sft + +on: + # Trigger the workflow on push or pull request, + # but only for the main branch + push: + branches: + - main + - v0.* + pull_request: + branches: + - main + - v0.* + paths: + - "**/*.py" + # Other entrypoints + - "!examples/**" + - "!tests/**" + - "!verl/trainer/main_*.py" + - "!verl/trainer/fsdp_sft_trainer.py" + # Recipes + - "!recipe/**" + # Megatron + - "!verl/workers/**/megatron_*.py" + # Entrypoints + - ".github/workflows/e2e_sft.yml" + - "examples/data_preprocess/gsm8k.py" + - "tests/special_e2e/sft" + - "verl/trainer/fsdp_sft_trainer.py" + - "verl/trainer/config/sft_trainer.yaml" + +# Cancel jobs on the same ref if a new one is triggered +concurrency: + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: ${{ github.ref != 'refs/heads/main' }} + +# Declare permissions just read content. +permissions: + contents: read + +env: + IMAGE: "verl-ci-cn-beijing.cr.volces.com/verlai/verl:base-verl0.4-cu124-cudnn9.8-torch2.6-fa2.7.4" + DYNAMIC_RUNNER_ENDPOINT: "https://sd10g3clalm04ug7alq90.apigateway-cn-beijing.volceapi.com/runner" + +jobs: + setup: + runs-on: ubuntu-latest + outputs: + runner-label: ${{ steps.create-runner.outputs.runner-label }} + mlp-task-id: ${{ steps.create-runner.outputs.mlp-task-id }} + steps: + - uses: actions/checkout@v4 + - id: create-runner + uses: volcengine/vemlp-github-runner@v1 + with: + mode: "create" + faas-url: "${{ env.DYNAMIC_RUNNER_ENDPOINT }}" + mlp-image: "${{ env.IMAGE }}" + e2e_sft: + needs: setup + runs-on: ["${{ needs.setup.outputs.runner-label || 'L20x8' }}"] + timeout-minutes: 20 # Increase this timeout value as needed + env: + HTTP_PROXY: ${{ secrets.PROXY_HTTP }} + HTTPS_PROXY: ${{ secrets.PROXY_HTTPS }} + NO_PROXY: "localhost,127.0.0.1,hf-mirror.com" + HF_ENDPOINT: "https://hf-mirror.com" + HF_HUB_ENABLE_HF_TRANSFER: "0" # This is more stable + steps: + - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + with: + fetch-depth: 0 + - name: Install the current repository + run: | + pip3 install peft + pip3 install --no-deps -e .[test,gpu] + - name: Prepare gsm8k dataset + run: | + ray stop --force + python3 examples/data_preprocess/gsm8k.py + - name: Running GSM8K E2E training tests on 8 L20 GPUs with rmpad using function rm + run: | + ray stop --force + bash tests/special_e2e/sft/run_sft.sh + - name: Running GSM8K E2E training tests on 8 L20 GPUs w/o rmpad using function rm + run: | + ray stop --force + RM_PAD=False bash tests/special_e2e/sft/run_sft.sh + - name: Running GSM8K E2E training tests on 8 L20 GPUs with sequence parallism + run: | + ray stop --force + SP_SIZE=2 bash tests/special_e2e/sft/run_sft.sh + - name: Check loss difference between sequence parallel vs. default implementation + run: | + ray stop --force + ENTRYPOINT="tests/special_e2e/sft/test_sp_loss_match.py" SP_SIZE=2 bash tests/special_e2e/sft/run_sft.sh + - name: Running GSM8K E2E training tests on 8 L20 GPUs with sequence parallism and liger + run: | + ray stop --force + SP_SIZE=2 LIGER=True bash tests/special_e2e/sft/run_sft.sh + - name: Running GSM8K E2E training tests with LoRA + run: | + ray stop --force + LORA_RANK=32 bash tests/special_e2e/sft/run_sft.sh + # TODO: multiturn + + cleanup: + runs-on: ubuntu-latest + needs: [setup, e2e_sft] + if: always() + steps: + - id: destroy-runner + uses: volcengine/vemlp-github-runner@v1 + with: + mode: "destroy" + faas-url: "${{ env.DYNAMIC_RUNNER_ENDPOINT }}" + mlp-task-id: "${{ needs.setup.outputs.mlp-task-id }}" diff --git a/sk2decompile/verl/.github/workflows/e2e_spin.yml b/sk2decompile/verl/.github/workflows/e2e_spin.yml new file mode 100644 index 0000000..cff18df --- /dev/null +++ b/sk2decompile/verl/.github/workflows/e2e_spin.yml @@ -0,0 +1,89 @@ +name: e2e_spin + +on: + # Trigger the workflow on push or pull request, + # but only for the main branch + push: + branches: + - main + - v0.* + paths: + - "**/*.py" + # Other entrypoints + - "!examples/**" + - "!tests/**" + - "!verl/trainer/main_*.py" + - "!verl/trainer/fsdp_sft_trainer.py" + # Other recipes + - "!recipe/**" + # Megatron + - "!verl/workers/**/megatron_*.py" + # Home + - "recipe/spin" + # Entrypoints + - ".github/workflows/e2e_spin.yml" + - "examples/data_preprocess/gsm8k.py" + - "tests/special_e2e/run_spin.sh" + - "!examples" + pull_request: + branches: + - main + - v0.* + paths: + - "**/*.py" + # Other entrypoints + - "!examples/**" + - "!tests/**" + - "!verl/trainer/main_*.py" + - "!verl/trainer/fsdp_sft_trainer.py" + # Other recipes + - "!recipe/**" + # Megatron + - "!verl/workers/**/megatron_*.py" + # Home + - "recipe/spin" + # Entrypoints + - ".github/workflows/e2e_spin.yml" + - "examples/data_preprocess/gsm8k.py" + - "tests/special_e2e/run_spin.sh" + - "!examples" + +# Declare permissions just read content. +permissions: + contents: read + +# Cancel jobs on the same ref if a new one is triggered +concurrency: + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: ${{ github.ref != 'refs/heads/main' }} + +jobs: + e2e_spin: + runs-on: [L20x8] + timeout-minutes: 40 # Increase this timeout value as needed + env: + HTTP_PROXY: ${{ secrets.PROXY_HTTP }} + HTTPS_PROXY: ${{ secrets.PROXY_HTTPS }} + NO_PROXY: "localhost,127.0.0.1,hf-mirror.com" + HF_ENDPOINT: "https://hf-mirror.com" + HF_HUB_ENABLE_HF_TRANSFER: "0" # This is more stable + container: + image: verlai/verl:app-verl0.4-sglang0.4.6.post5-vllm0.8.5-mcore0.12.1 + options: --gpus all --shm-size=10g + steps: + - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + with: + fetch-depth: 0 + - name: Install the current repository + run: | + pip3 install -e .[test,gpu,sglang] --no-deps + - name: Prepare gsm8k dataset + run: | + python3 examples/data_preprocess/gsm8k.py --local_dir ./data/gsm8k + - name: Prepare Model checkpoint + run: | + huggingface-cli download Qwen/Qwen2.5-0.5B-Instruct --local-dir ./models/Qwen2.5-0.5B-Instruct + - name: Running the E2E test with the spin algorithm + run: | + ray stop --force + bash tests/special_e2e/run_spin.sh diff --git a/sk2decompile/verl/.github/workflows/e2e_sppo.yml b/sk2decompile/verl/.github/workflows/e2e_sppo.yml new file mode 100644 index 0000000..4f8cc1b --- /dev/null +++ b/sk2decompile/verl/.github/workflows/e2e_sppo.yml @@ -0,0 +1,87 @@ +name: e2e_sppo + +on: + # Trigger the workflow on push or pull request, + # but only for the main branch + push: + branches: + - main + - v0.* + paths: + - "**/*.py" + # Other entrypoints + - "!examples/**" + - "!tests/**" + - "!verl/trainer/main_*.py" + - "!verl/trainer/fsdp_sft_trainer.py" + # Other recipes + - "!recipe/**" + # Megatron + - "!verl/workers/**/megatron_*.py" + # Home + - "recipe/sppo" + # Entrypoints + - ".github/workflows/e2e_sppo.yml" + - "examples/data_preprocess/gsm8k.py" + - "tests/special_e2e/run_sppo.sh" + pull_request: + branches: + - main + - v0.* + paths: + - "**/*.py" + # Other entrypoints + - "!examples/**" + - "!tests/**" + - "!verl/trainer/main_*.py" + - "!verl/trainer/fsdp_sft_trainer.py" + # Other recipes + - "!recipe/**" + # Megatron + - "!verl/workers/**/megatron_*.py" + # Home + - "recipe/sppo" + # Entrypoints + - ".github/workflows/e2e_sppo.yml" + - "examples/data_preprocess/gsm8k.py" + - "tests/special_e2e/run_sppo.sh" + +# Declare permissions just read content. +permissions: + contents: read + +# Cancel jobs on the same ref if a new one is triggered +concurrency: + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: ${{ github.ref != 'refs/heads/main' }} + +jobs: + e2e_sppo: + runs-on: [L20x8] + timeout-minutes: 40 # Increase this timeout value as needed + env: + HTTP_PROXY: ${{ secrets.PROXY_HTTP }} + HTTPS_PROXY: ${{ secrets.PROXY_HTTPS }} + NO_PROXY: "localhost,127.0.0.1,hf-mirror.com" + HF_ENDPOINT: "https://hf-mirror.com" + HF_HUB_ENABLE_HF_TRANSFER: "0" # This is more stable + container: + image: verlai/verl:app-verl0.4-sglang0.4.6.post5-vllm0.8.5-mcore0.12.1 + options: --gpus all --shm-size=10g + steps: + - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + with: + fetch-depth: 0 + - name: Install the current repository + run: | + pip3 install -e .[test,gpu,sglang] --no-deps + - name: Prepare MATH dataset + run: | + python3 examples/data_preprocess/math_dataset.py --local_dir ./data/math + - name: Prepare Model checkpoint + run: | + huggingface-cli download Qwen/Qwen2.5-0.5B-Instruct --local-dir ./models/Qwen2.5-0.5B-Instruct + - name: Running the E2E test with the SPPO algorithm + run: | + ray stop --force + bash tests/special_e2e/run_sppo.sh diff --git a/sk2decompile/verl/.github/workflows/gpu_unit_tests.yml b/sk2decompile/verl/.github/workflows/gpu_unit_tests.yml new file mode 100644 index 0000000..24c0fe0 --- /dev/null +++ b/sk2decompile/verl/.github/workflows/gpu_unit_tests.yml @@ -0,0 +1,100 @@ +# # Tests layout + +# Each folder under tests/ corresponds to a test category for a sub-namespace in verl. For instance: +# - `tests/trainer` for testing functionality related to `verl/trainer` +# - `tests/models` for testing functionality related to `verl/models` +# - ... + +# There are a few folders with `special_` prefix, created for special purposes: +# - `special_distributed`: unit tests that must run with multiple GPUs +# - `special_e2e`: end-to-end tests with training/generation scripts +# - `special_npu`: tests for NPUs +# - `special_sanity`: a suite of quick sanity tests +# - `special_standalone`: a set of test that are designed to run in dedicated environments + +# Accelerators for tests +# - By default tests are run with GPU available, except for the ones under `special_npu`, and any test script whose name ends with `on_cpu.py`. +# - For test scripts with `on_cpu.py` name suffix would be tested on CPU resources in linux environment. + +# # Workflow layout + +# All CI tests are configured by yaml files in `.github/workflows/`. Here's an overview of all test configs: +# 1. A list of always triggered CPU sanity tests: `check-pr-title.yml`, `secrets_scan.yml`, `check-pr-title,yml`, `pre-commit.yml`, `doc.yml` +# 2. Some heavy multi-GPU unit tests, such as `model.yml`, `vllm.yml`, `sgl.yml` +# 3. End-to-end tests: `e2e_*.yml` +# 4. Unit tests +# - `cpu_unit_tests.yml`, run pytest on all scripts with file name pattern `tests/**/test_*_on_cpu.py` +# - `gpu_unit_tests.yml`, run pytest on all scripts with file without the `on_cpu.py` suffix. +# - Since cpu/gpu unit tests by default runs all tests under `tests`, please make sure tests are manually excluded in them when +# - new workflow yaml is added to `.github/workflows` +# - new tests are added to workflow mentioned in 2. + +name: GPU unit tests + +on: + # Trigger the workflow on push or pull request, + # but only for the main branch + push: + branches: + - main + - v0.4.x + paths: + - "**/*.py" + - .github/workflows/gpu_unit_tests.yml + pull_request: + branches: + - main + - v0.4.x + paths: + # The order that you define paths patterns matters: + # A matching negative pattern (prefixed with !) after a positive match will exclude the path. + # A matching positive pattern after a negative match will include the path again. + - "**/*.py" + # Other entrypoints + - "!examples/**" + - "!verl/trainer/main_*.py" + - "!verl/trainer/fsdp_sft_trainer.py" + - "!recipe/**" + # Entrypoints + - .github/workflows/gpu_unit_tests.yml + - "tests/**test_*.py" + # Ignore CPU tests + - "!tests/*_on_cpu.py" + +# Cancel jobs on the same ref if a new one is triggered +concurrency: + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: ${{ github.ref != 'refs/heads/main' }} + +# Declare permissions just read content. +permissions: + contents: read + +jobs: + gpu_unit_tests: + runs-on: [L20x8] + timeout-minutes: 40 # Increase this timeout value as needed + env: + HTTP_PROXY: ${{ secrets.PROXY_HTTP }} + HTTPS_PROXY: ${{ secrets.PROXY_HTTPS }} + NO_PROXY: "localhost,127.0.0.1" + HF_HUB_ENABLE_HF_TRANSFER: 1 + container: + image: verlai/verl:app-verl0.4-sglang0.4.6.post5-vllm0.8.5-mcore0.12.1 + options: --gpus all --shm-size=10g + steps: + - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + with: + fetch-depth: 0 + - name: Install the current repository + run: | + pip3 install hf_transfer + pip3 install --no-deps -e .[test] + pip3 install --upgrade "ray>=2.40.0" + pip3 install cupy-cuda12x + - name: Run all GPU unit tests + run: | + pytest -s -x --ignore-glob="*test_linear_cross_entropy_tp.py" --ignore-glob='*on_cpu.py' --ignore-glob="*test_vllm*" --ignore-glob="*_sglang*" --ignore-glob="*_hf_rollout*" --ignore-glob="tests/models/" --ignore-glob='tests/special*' --ignore-glob="tests/experimental" tests/ + - name: Testing LinearCrossEntropyTP Correctness, Computation Time and Memory Consumption + run: | + LOW_MEMORY=True torchrun --standalone --nnodes=1 --nproc-per-node=8 tests/utils/test_linear_cross_entropy_tp.py diff --git a/sk2decompile/verl/.github/workflows/model.yml b/sk2decompile/verl/.github/workflows/model.yml new file mode 100644 index 0000000..88563d8 --- /dev/null +++ b/sk2decompile/verl/.github/workflows/model.yml @@ -0,0 +1,144 @@ +# # Tests layout + +# Each folder under tests/ corresponds to a test category for a sub-namespace in verl. For instance: +# - `tests/trainer` for testing functionality related to `verl/trainer` +# - `tests/models` for testing functionality related to `verl/models` +# - ... + +# There are a few folders with `special_` prefix, created for special purposes: +# - `special_distributed`: unit tests that must run with multiple GPUs +# - `special_e2e`: end-to-end tests with training/generation scripts +# - `special_npu`: tests for NPUs +# - `special_sanity`: a suite of quick sanity tests +# - `special_standalone`: a set of test that are designed to run in dedicated environments + +# Accelerators for tests +# - By default tests are run with GPU available, except for the ones under `special_npu`, and any test script whose name ends with `on_cpu.py`. +# - For test scripts with `on_cpu.py` name suffix would be tested on CPU resources in linux environment. + +# # Workflow layout + +# All CI tests are configured by yaml files in `.github/workflows/`. Here's an overview of all test configs: +# 1. A list of always triggered CPU sanity tests: `check-pr-title.yml`, `secrets_scan.yml`, `check-pr-title,yml`, `pre-commit.yml`, `doc.yml` +# 2. Some heavy multi-GPU unit tests, such as `model.yml`, `vllm.yml`, `sgl.yml` +# 3. End-to-end tests: `e2e_*.yml` +# 4. Unit tests +# - `cpu_unit_tests.yml`, run pytest on all scripts with file name pattern `tests/**/test_*_on_cpu.py` +# - `gpu_unit_tests.yml`, run pytest on all scripts with file without the `on_cpu.py` suffix. +# - Since cpu/gpu unit tests by default runs all tests under `tests`, please make sure tests are manually excluded in them when +# - new workflow yaml is added to `.github/workflows` +# - new tests are added to workflow mentioned in 2. +# name: Check PR Title + +name: model_rmpad + +on: + # Trigger the workflow on push or pull request, + # but only for the main branch + push: + branches: + - main + - v0.* + pull_request: + branches: + - main + - v0.* + paths: + - "verl/**/*.py" + # Entrypoints + - ".github/workflows/model.yml" + - "tests/special_distributed/test_fsdp_ckpt.py" + - "tests/models/**" + - "tests/special_distributed/run_all.sh" + +# Declare permissions just read content. +permissions: + contents: read + +# Cancel jobs on the same ref if a new one is triggered +concurrency: + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: ${{ github.ref != 'refs/heads/main' }} + +jobs: + model_rmpad: + runs-on: [L20x8] + timeout-minutes: 20 # Increase this timeout value as needed + env: + HTTP_PROXY: ${{ secrets.PROXY_HTTP }} + HTTPS_PROXY: ${{ secrets.PROXY_HTTPS }} + NO_PROXY: "localhost,127.0.0.1,hf-mirror.com" + HF_ENDPOINT: "https://hf-mirror.com" + HF_HUB_ENABLE_HF_TRANSFER: "0" # This is more stable + container: + image: verlai/verl:app-verl0.4-sglang0.4.6.post5-vllm0.8.5-mcore0.12.1 + options: --gpus all --shm-size=10g + steps: + - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + with: + fetch-depth: 0 + - name: Install the current repository and upgrade to latest transformers/flash_attn + run: | + pip3 install --no-deps -e .[test] + pip3 install --upgrade transformers + - name: Running rmpad model tests on 8 L20 GPUs + flash_attn 2.5.8 + run: | + pytest -s tests/models/test_transformer.py + - name: Running rmpad model tests on 8 L20 GPUs + latest flash_attn + run: | + pytest -s tests/models/test_transformer.py + - name: Running FSDP rmpad model tests on 8 L20 GPUs + latest flash_attn + run: | + STRATEGY=fsdp torchrun --nproc_per_node=8 tests/special_distributed/test_fsdp_ckpt.py + - name: Running transformers ulysses tests on 8 L20 GPUs + latest transformers + run: | + torchrun --nproc_per_node=8 -m pytest tests/models/test_transformers_ulysses.py + - name: Running transformers ulysses tests on 8 L20 GPUs + transformers 4.49.0 + run: | + pip3 install transformers==4.49.0 + torchrun --nproc_per_node=8 -m pytest tests/models/test_transformers_ulysses.py + - name: Running transformers ulysses tests on 8 L20 GPUs + transformers 4.48.0 + run: | + pip3 install transformers==4.48.0 + torchrun --nproc_per_node=8 -m pytest tests/models/test_transformers_ulysses.py + - name: Running transformers ulysses tests on 8 L20 GPUs + transformers 4.47.0 + run: | + pip3 install transformers==4.47.0 + torchrun --nproc_per_node=8 -m pytest tests/models/test_transformers_ulysses.py + - name: Running transformers ulysses tests on 8 L20 GPUs + transformers 4.46.0 + run: | + pip3 install transformers==4.46.0 + torchrun --nproc_per_node=8 -m pytest tests/models/test_transformers_ulysses.py + - name: Running transformers ulysses tests on 8 L20 GPUs + transformers 4.45.0 + run: | + pip3 install transformers==4.45.0 + torchrun --nproc_per_node=8 -m pytest tests/models/test_transformers_ulysses.py + - name: Run distributed test + run: | + bash tests/special_distributed/run_all.sh + + # TODO: Move this back to model_rmpad once FSDP2 is stable. + # NOTE: List as an independent job to make rerun easier. + model_rmpad_fsdp2_unstable: + runs-on: [L20x8] + timeout-minutes: 20 # Increase this timeout value as needed + env: + HTTP_PROXY: ${{ secrets.PROXY_HTTP }} + HTTPS_PROXY: ${{ secrets.PROXY_HTTPS }} + NO_PROXY: "localhost,127.0.0.1,hf-mirror.com" + HF_ENDPOINT: "https://hf-mirror.com" + HF_HUB_ENABLE_HF_TRANSFER: "0" # This is more stable + container: + image: verlai/verl:base-verl0.4-cu124-cudnn9.8-torch2.6-fa2.7.4 + options: --gpus all --shm-size=10g + steps: + - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + with: + fetch-depth: 0 + - name: Install the current repository and upgrade to latest transformers/flash_attn + run: | + pip3 install --no-deps -e .[test] + pip3 install --upgrade transformers + - name: Running FSDP2 rmpad model tests on 8 L20 GPUs + latest flash_attn + run: | + STRATEGY=fsdp2 torchrun --nproc_per_node=8 tests/special_distributed/test_fsdp_ckpt.py diff --git a/sk2decompile/verl/.github/workflows/pre-commit-full.yml b/sk2decompile/verl/.github/workflows/pre-commit-full.yml new file mode 100644 index 0000000..be2dea6 --- /dev/null +++ b/sk2decompile/verl/.github/workflows/pre-commit-full.yml @@ -0,0 +1,30 @@ +name: pre-commit-full + +# Run weekly on Sunday at 00:00 UTC +on: + schedule: + - cron: "0 0 * * 0" + # Allow manual triggering + workflow_dispatch: + +# Declare permissions just read content. +permissions: + contents: read + +jobs: + pre-commit-full: + runs-on: ubuntu-latest + strategy: + matrix: + python-version: ["3.12"] + steps: + - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + - name: Set up Python ${{ matrix.python-version }} + uses: actions/setup-python@0b93645e9fea7318ecaed2b359559ac225c90a2b # v5.3.0 + with: + python-version: ${{ matrix.python-version }} + - name: Set ruff --output-format=github + run: | + sed -i 's/--output-format=full/--output-format=github/' .pre-commit-config.yaml + git add .pre-commit-config.yaml + - uses: pre-commit/action@v3.0.1 diff --git a/sk2decompile/verl/.github/workflows/pre-commit.yml b/sk2decompile/verl/.github/workflows/pre-commit.yml new file mode 100644 index 0000000..21dce5c --- /dev/null +++ b/sk2decompile/verl/.github/workflows/pre-commit.yml @@ -0,0 +1,33 @@ +# c.f. https://github.com/pre-commit/action?tab=readme-ov-file#using-this-action +name: pre-commit + +# No need to avoid / cancel lightweight pre-commit jobs +on: + pull_request: + push: + branches: + - main + - v0.* + +# Declare permissions just read content. +permissions: + contents: read + +jobs: + pre-commit: + runs-on: ubuntu-latest + strategy: + matrix: + python-version: ["3.12"] + steps: + - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + - name: Set up Python ${{ matrix.python-version }} + uses: actions/setup-python@0b93645e9fea7318ecaed2b359559ac225c90a2b # v5.3.0 + with: + python-version: ${{ matrix.python-version }} + - name: Set ruff --output-format=github + run: | + sed -i 's/--output-format=full/--output-format=github/' .pre-commit-config.yaml + git add .pre-commit-config.yaml + # Check "--all-files" by default + - uses: pre-commit/action@v3.0.1 diff --git a/sk2decompile/verl/.github/workflows/sanity.yml b/sk2decompile/verl/.github/workflows/sanity.yml new file mode 100644 index 0000000..a03baab --- /dev/null +++ b/sk2decompile/verl/.github/workflows/sanity.yml @@ -0,0 +1,97 @@ +# # Tests layout + +# Each folder under tests/ corresponds to a test category for a sub-namespace in verl. For instance: +# - `tests/trainer` for testing functionality related to `verl/trainer` +# - `tests/models` for testing functionality related to `verl/models` +# - ... + +# There are a few folders with `special_` prefix, created for special purposes: +# - `special_distributed`: unit tests that must run with multiple GPUs +# - `special_e2e`: end-to-end tests with training/generation scripts +# - `special_npu`: tests for NPUs +# - `special_sanity`: a suite of quick sanity tests +# - `special_standalone`: a set of test that are designed to run in dedicated environments + +# Accelerators for tests +# - By default tests are run with GPU available, except for the ones under `special_npu`, and any test script whose name ends with `on_cpu.py`. +# - For test scripts with `on_cpu.py` name suffix would be tested on CPU resources in linux environment. + +# # Workflow layout + +# All CI tests are configured by yaml files in `.github/workflows/`. Here's an overview of all test configs: +# 1. A list of always triggered CPU sanity tests: `check-pr-title.yml`, `secrets_scan.yml`, `check-pr-title,yml`, `pre-commit.yml`, `doc.yml` +# 2. Some heavy multi-GPU unit tests, such as `model.yml`, `vllm.yml`, `sgl.yml` +# 3. End-to-end tests: `e2e_*.yml` +# 4. Unit tests +# - `cpu_unit_tests.yml`, run pytest on all scripts with file name pattern `tests/**/test_*_on_cpu.py` +# - `gpu_unit_tests.yml`, run pytest on all scripts with file without the `on_cpu.py` suffix. +# - Since cpu/gpu unit tests by default runs all tests under `tests`, please make sure tests are manually excluded in them when +# - new workflow yaml is added to `.github/workflows` +# - new tests are added to workflow mentioned in 2. +# name: Check PR Title + +name: sanity + +on: + # Trigger the workflow on push or pull request, + # but only for the main branch + push: + branches: + - main + - v0.* + pull_request: + branches: + - main + - v0.* + paths: + - "**/*.py" + - .github/workflows/sanity.yml + - "tests/special_sanity/**" + +# Cancel jobs on the same ref if a new one is triggered +concurrency: + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: ${{ github.ref != 'refs/heads/main' }} + +# Declare permissions just read content. +permissions: + contents: read + +jobs: + sanity: + runs-on: ubuntu-latest + timeout-minutes: 5 # Increase this timeout value as needed + strategy: + matrix: + python-version: ["3.10"] + steps: + - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + - name: Set up Python ${{ matrix.python-version }} + uses: actions/setup-python@0b93645e9fea7318ecaed2b359559ac225c90a2b # v5.3.0 + with: + python-version: ${{ matrix.python-version }} + - name: Install the current repository + run: | + pip install -e .[test] + - name: Run sanity test + run: | + pytest -s -x tests/special_sanity + - name: Run license test + run: | + python3 tests/special_sanity/check_license.py --directory . + - name: Assert naming convention + run: | + if grep -rIn --exclude-dir=.git --exclude-dir=.github --exclude-dir=venv --exclude-dir=__pycache__ 'veRL' .; then + echo "Please use verl instead of veRL in the codebase" + exit 1 + fi + - name: Validate test folder structure + run: python3 tests/special_sanity/validate_structure.py + - name: Assert documentation requirement for functions + run: python3 tests/special_sanity/validate_imported_docs.py + - name: Assert device api usage in verl/recipe + run: python3 tests/special_sanity/check_device_api_usage.py --directory ./recipe + - name: Assert device api usage in verl/verl + run: python3 tests/special_sanity/check_device_api_usage.py --directory ./verl + - name: Assert documentation time info + run: python3 tests/special_sanity/check_docs_time_info.py diff --git a/sk2decompile/verl/.github/workflows/scorecard.yml b/sk2decompile/verl/.github/workflows/scorecard.yml new file mode 100644 index 0000000..176d15a --- /dev/null +++ b/sk2decompile/verl/.github/workflows/scorecard.yml @@ -0,0 +1,66 @@ +# This workflow uses actions that are not certified by GitHub. They are provided +# by a third-party and are governed by separate terms of service, privacy +# policy, and support documentation. + +name: Scorecard supply-chain security +on: + # For Branch-Protection check. Only the default branch is supported. See + # https://github.com/ossf/scorecard/blob/main/docs/checks.md#branch-protection + branch_protection_rule: + # To guarantee Maintained check is occasionally updated. See + # https://github.com/ossf/scorecard/blob/main/docs/checks.md#maintained + schedule: + - cron: "27 7 * * 1" + push: + branches: + - main + - v0.* + +# Declare default permissions as read only. +permissions: read-all + +jobs: + analysis: + name: Scorecard analysis + runs-on: ubuntu-latest + permissions: + # Needed to upload the results to code-scanning dashboard. + security-events: write + # Needed to publish results and get a badge (see publish_results below). + id-token: write + # Uncomment the permissions below if installing in a private repository. + # contents: read + # actions: read + + steps: + - name: "Checkout code" + uses: actions/checkout@b4ffde65f46336ab88eb53be808477a3936bae11 # v4.1.1 + with: + persist-credentials: false + + - name: "Run analysis" + uses: ossf/scorecard-action@0864cf19026789058feabb7e87baa5f140aac736 # v2.3.1 + with: + results_file: results.sarif + results_format: sarif + # (Optional) "write" PAT token. Uncomment the `repo_token` line below if: + # - you want to enable the Branch-Protection check on a *public* repository, or + # - you are installing Scorecard on a *private* repository + # To create the PAT, follow the steps in https://github.com/ossf/scorecard-action?tab=readme-ov-file#authentication-with-fine-grained-pat-optional. + # repo_token: ${{ secrets.SCORECARD_TOKEN }} + + # Public repositories: + # - Publish results to OpenSSF REST API for easy access by consumers + # - Allows the repository to include the Scorecard badge. + # - See https://github.com/ossf/scorecard-action#publishing-results. + # For private repositories: + # - `publish_results` will always be set to `false`, regardless + # of the value entered here. + publish_results: true + + # Upload the results to GitHub's code scanning dashboard (optional). + # Commenting out will disable upload of results to your repo's Code Scanning dashboard + - name: "Upload to code-scanning" + uses: github/codeql-action/upload-sarif@9e8d0789d4a0fa9ceb6b1738f7e269594bdd67f0 #v3.28.9 + with: + sarif_file: results.sarif diff --git a/sk2decompile/verl/.github/workflows/secrets_scan.yml b/sk2decompile/verl/.github/workflows/secrets_scan.yml new file mode 100644 index 0000000..298ed16 --- /dev/null +++ b/sk2decompile/verl/.github/workflows/secrets_scan.yml @@ -0,0 +1,22 @@ +on: + push: + branches: + - main + - v0.* + pull_request: + +permissions: + contents: read + +jobs: + test: + runs-on: ubuntu-latest + steps: + - name: Checkout code + uses: actions/checkout@b4ffde65f46336ab88eb53be808477a3936bae11 # v4.1.1 + with: + fetch-depth: 0 + - name: Secret Scanning + uses: trufflesecurity/trufflehog@7dc056a193116ba8d82154bf0549381c8fb8545c # v3.88.14 + with: + extra_args: --results=verified,unknown diff --git a/sk2decompile/verl/.github/workflows/sgl.yml b/sk2decompile/verl/.github/workflows/sgl.yml new file mode 100644 index 0000000..5999e7c --- /dev/null +++ b/sk2decompile/verl/.github/workflows/sgl.yml @@ -0,0 +1,142 @@ +# # Tests layout + +# Each folder under tests/ corresponds to a test category for a sub-namespace in verl. For instance: +# - `tests/trainer` for testing functionality related to `verl/trainer` +# - `tests/models` for testing functionality related to `verl/models` +# - ... + +# There are a few folders with `special_` prefix, created for special purposes: +# - `special_distributed`: unit tests that must run with multiple GPUs +# - `special_e2e`: end-to-end tests with training/generation scripts +# - `special_npu`: tests for NPUs +# - `special_sanity`: a suite of quick sanity tests +# - `special_standalone`: a set of test that are designed to run in dedicated environments + +# Accelerators for tests +# - By default tests are run with GPU available, except for the ones under `special_npu`, and any test script whose name ends with `on_cpu.py`. +# - For test scripts with `on_cpu.py` name suffix would be tested on CPU resources in linux environment. + +# # Workflow layout + +# All CI tests are configured by yaml files in `.github/workflows/`. Here's an overview of all test configs: +# 1. A list of always triggered CPU sanity tests: `check-pr-title.yml`, `secrets_scan.yml`, `check-pr-title,yml`, `pre-commit.yml`, `doc.yml` +# 2. Some heavy multi-GPU unit tests, such as `model.yml`, `vllm.yml`, `sgl.yml` +# 3. End-to-end tests: `e2e_*.yml` +# 4. Unit tests +# - `cpu_unit_tests.yml`, run pytest on all scripts with file name pattern `tests/**/test_*_on_cpu.py` +# - `gpu_unit_tests.yml`, run pytest on all scripts with file without the `on_cpu.py` suffix. +# - Since cpu/gpu unit tests by default runs all tests under `tests`, please make sure tests are manually excluded in them when +# - new workflow yaml is added to `.github/workflows` +# - new tests are added to workflow mentioned in 2. + +name: sgl + +on: + workflow_dispatch: # Manual + # Trigger the workflow on push or pull request, + # but only for the main branch + push: + branches: + - main + - v0.2.x + paths: + - "**/*.py" + - .github/workflows/vllm.yml + pull_request: + branches: + - main + - v0.2.x + paths: + - "**/*.py" + # Other entrypoints + - "!examples/**" + - "!tests/**" + - "!verl/trainer/main_*.py" + - "!verl/trainer/fsdp_sft_trainer.py" + # FSDP + - "!verl/workers/**/*dp_*.py" + # Megatron + - "!verl/workers/**/megatron_*.py" + # vLLM + - "!**/*vllm*" + # Recipes + - "!recipe/**" + # Entrypoints + - ".github/workflows/sgl.yml" + - "tests/rollout/*sglang*" + - "tests/rollout/async_rollout_utils.py" + - "tests/workers/rollout/*interaction*" + +# Cancel jobs on the same ref if a new one is triggered +concurrency: + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: ${{ github.ref != 'refs/heads/main' }} + +# Declare permissions just read content. +permissions: + contents: read + +jobs: + sgl: + runs-on: [L20x8] + timeout-minutes: 20 # Increase this timeout value as needed + env: + HTTP_PROXY: ${{ secrets.PROXY_HTTP }} + HTTPS_PROXY: ${{ secrets.PROXY_HTTPS }} + NO_PROXY: "localhost,127.0.0.1,hf-mirror.com" + HF_ENDPOINT: "https://hf-mirror.com" + HF_HUB_ENABLE_HF_TRANSFER: 1 + SGL_DISABLE_TP_MEMORY_INBALANCE_CHECK: "True" + container: + image: verlai/verl:app-verl0.4-sglang0.4.6.post5-vllm0.8.5-mcore0.12.1 + options: --gpus all --shm-size=10g + steps: + - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + with: + fetch-depth: 0 + - name: Install the current repository + run: | + pip3 install hf_transfer fastmcp + pip3 install -e .[test,gpu,sglang] --no-deps + - name: Download Model to Use + run: | + huggingface-cli download 'Qwen/Qwen2-7B-Instruct' + huggingface-cli download 'Qwen/Qwen2.5-0.5B' + huggingface-cli download Qwen/Qwen2.5-1.5B-Instruct + export HF_HUB_OFFLINE=1 + - name: Test the latest SGLang + run: | + cd tests/workers/rollout + torchrun --nnodes=1 --nproc_per_node=2 $(which pytest) -s test_sglang_spmd.py + - name: Test the latest SGLang Rollout async with interaction + run: | + cd tests/workers/rollout + torchrun --nnodes=1 --nproc_per_node=2 $(which pytest) -s test_sglang_async_rollout_w_interaction.py + - name: Test the latest SGLang Multi Interaction + run: | + cd tests/workers/rollout + torchrun --nnodes=1 --nproc_per_node=2 $(which pytest) -s test_sglang_multi_interaction.py + - name: Test the latest SGLang Rollout async with tool + run: | + cd tests/workers/rollout + torchrun --nnodes=1 --nproc_per_node=2 $(which pytest) -s test_sglang_async_rollout_w_tools.py + - name: Test the latest SGLang Rollout async with sandbox fusion tool + run: | + cd tests/workers/rollout + pytest -s test_sglang_async_rollout_sf_tools.py + - name: Test the latest SGLang Rollout async with search tool + run: | + cd tests/workers/rollout + pytest -s test_sglang_async_rollout_search_tools.py + - name: Test the latest SGLang Rollout async with mcp search tool + run: | + cd tests/workers/rollout + pytest -s test_sglang_async_rollout_mcp_tools.py + - name: Test the latest SGLang Rollout async with agent loop + run: | + ROLLOUT_NAME=sglang pytest -svvv tests/experimental/agent_loop/test_basic_agent_loop.py + # Note(haibin.lin): for any new test, please update gpu_unit_tests.yaml to avoid repeated tests + - name: Test the latest SGLang Rollout async with multimodal delta + run: | + cd tests/workers/rollout + pytest -s test_sglang_async_rollout_multimodal_delta.py \ No newline at end of file diff --git a/sk2decompile/verl/.github/workflows/type-coverage-check.yml b/sk2decompile/verl/.github/workflows/type-coverage-check.yml new file mode 100644 index 0000000..3010736 --- /dev/null +++ b/sk2decompile/verl/.github/workflows/type-coverage-check.yml @@ -0,0 +1,29 @@ +name: Type Annotation and Docstring Coverage + +on: + pull_request: + paths: + - '**/*.py' + +jobs: + type-coverage-check: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + with: + fetch-depth: 0 # 🚨 Important: fetch full history so `origin/main` is available + - name: Set up Python + uses: actions/setup-python@v5 + with: + python-version: '3.10' + + - name: Install dependencies + run: | + pip install gitpython + pip install -e .[sglang] + - name: Run type annotation coverage check + run: | + python3 tests/special_sanity/type_coverage_check.py + - name: Run docstring coverage check + run: | + python3 tests/special_sanity/check_api_docs.py verl diff --git a/sk2decompile/verl/.github/workflows/vllm.yml b/sk2decompile/verl/.github/workflows/vllm.yml new file mode 100644 index 0000000..d9bf9c7 --- /dev/null +++ b/sk2decompile/verl/.github/workflows/vllm.yml @@ -0,0 +1,124 @@ +# # Tests layout + +# Each folder under tests/ corresponds to a test category for a sub-namespace in verl. For instance: +# - `tests/trainer` for testing functionality related to `verl/trainer` +# - `tests/models` for testing functionality related to `verl/models` +# - ... + +# There are a few folders with `special_` prefix, created for special purposes: +# - `special_distributed`: unit tests that must run with multiple GPUs +# - `special_e2e`: end-to-end tests with training/generation scripts +# - `special_npu`: tests for NPUs +# - `special_sanity`: a suite of quick sanity tests +# - `special_standalone`: a set of test that are designed to run in dedicated environments + +# Accelerators for tests +# - By default tests are run with GPU available, except for the ones under `special_npu`, and any test script whose name ends with `on_cpu.py`. +# - For test scripts with `on_cpu.py` name suffix would be tested on CPU resources in linux environment. + +# # Workflow layout + +# All CI tests are configured by yaml files in `.github/workflows/`. Here's an overview of all test configs: +# 1. A list of always triggered CPU sanity tests: `check-pr-title.yml`, `secrets_scan.yml`, `check-pr-title,yml`, `pre-commit.yml`, `doc.yml` +# 2. Some heavy multi-GPU unit tests, such as `model.yml`, `vllm.yml`, `sgl.yml` +# 3. End-to-end tests: `e2e_*.yml` +# 4. Unit tests +# - `cpu_unit_tests.yml`, run pytest on all scripts with file name pattern `tests/**/test_*_on_cpu.py` +# - `gpu_unit_tests.yml`, run pytest on all scripts with file without the `on_cpu.py` suffix. +# - Since cpu/gpu unit tests by default runs all tests under `tests`, please make sure tests are manually excluded in them when +# - new workflow yaml is added to `.github/workflows` +# - new tests are added to workflow mentioned in 2. + +name: vllm + +on: + # Trigger the workflow on push or pull request, + # but only for the main branch + push: + branches: + - main + - v0.* + pull_request: + branches: + - main + - v0.* + paths: + - "**/*.py" + # Other entrypoints + - "!examples/**" + - "!tests/**" + - "!verl/trainer/main_*.py" + - "!verl/trainer/fsdp_sft_trainer.py" + # Recipes + - "!recipe/**" + # FSDP + - "!verl/workers/**/*dp_*.py" + # Megatron + - "!verl/workers/**/megatron_*.py" + # SGLang + - "!**/*sglang*" + # Entrypoints + - ".github/workflows/vllm.yml" + - "tests/special_e2e/generation" + - "tests/workers/rollout" + - "verl/trainer/main_generation.py" + - "verl/trainer/config/generation.yaml" + +# Cancel jobs on the same ref if a new one is triggered +concurrency: + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: ${{ github.ref != 'refs/heads/main' }} + +# Declare permissions just read content. +permissions: + contents: read + +jobs: + vllm: + runs-on: [L20x8] + timeout-minutes: 60 # Increase this timeout value as needed + env: + HTTP_PROXY: ${{ secrets.PROXY_HTTP }} + HTTPS_PROXY: ${{ secrets.PROXY_HTTPS }} + NO_PROXY: "localhost,127.0.0.1,hf-mirror.com" + HF_ENDPOINT: "https://hf-mirror.com" + HF_HUB_ENABLE_HF_TRANSFER: "0" # This is more stable + container: + image: whatcanyousee/verl:vemlp-th2.4.0-cu124-vllm0.6.3-ray2.10-te2.0-megatron0.11.0-v0.0.6 + options: --gpus all --shm-size=10g + steps: + - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + with: + fetch-depth: 0 + - name: Install the current repository + run: | + pip3 install -e .[test,vllm] + pip install tensordict==0.6.2 + - name: Download Model to Use + run: | + huggingface-cli download Qwen/Qwen2.5-0.5B-Instruct + huggingface-cli download Qwen/Qwen2.5-1.5B-Instruct + huggingface-cli download 'Qwen/Qwen2-7B-Instruct' + huggingface-cli download 'deepseek-ai/deepseek-llm-7b-chat' + export HF_HUB_OFFLINE=1 + # Disable requests to avoid network errors + - name: Test the latest vLLM + run: | + cd tests/workers/rollout/rollout_vllm + torchrun --standalone --nnodes=1 --nproc_per_node=4 $(which pytest) -s test_vllm_spmd.py + - name: Run Qwen 0.5B generation test + run: | + cd tests/special_e2e/generation + export OUTPUT_PATH="${HOME}/data/gen/qwen_05_gen_test.parquet" + MODEL_ID=Qwen/Qwen2.5-0.5B-Instruct NGPUS_PER_NODE=4 GEN_TP=2 bash ./run_gen_qwen05.sh + rm -rf "${OUTPUT_PATH}" + - name: Run Qwen 0.5B generation test when world_size == 1 + run: | + cd tests/special_e2e/generation + export OUTPUT_PATH="${HOME}/data/gen/qwen_05_gen_test.parquet" + MODEL_ID=Qwen/Qwen2.5-0.5B-Instruct NGPUS_PER_NODE=1 GEN_TP=1 bash ./run_gen_qwen05.sh + rm -rf "${OUTPUT_PATH}" + - name: Test the latest vLLM Rollout async with agent loop + run: | + ROLLOUT_NAME=vllm pytest -svvv tests/experimental/agent_loop/test_basic_agent_loop.py + # Note(haibin.lin): for any new test, please update gpu_unit_tests.yaml to avoid repeated tests diff --git a/sk2decompile/verl/.gitignore b/sk2decompile/verl/.gitignore new file mode 100644 index 0000000..8dc4dcb --- /dev/null +++ b/sk2decompile/verl/.gitignore @@ -0,0 +1,126 @@ + +**/*.pt +**/checkpoints +**/wget-log +**/_build/ +**/*.ckpt +**/outputs +**/*.tar.gz +**/playground +**/wandb + +# Byte-compiled / optimized / DLL files +__pycache__/ +*.py[cod] +*$py.class +dataset/* +tensorflow/my_graph/* +.idea/ +# C extensions +*.so + +# Distribution / packaging +.Python +env/ +build/ +develop-eggs/ +dist/ +downloads/ +eggs/ +.eggs/ +lib/ +lib64/ +parts/ +sdist/ +var/ +tmp/ +*.egg-info/ +.installed.cfg +*.egg + +# PyInstaller +# Usually these files are written by a python script from a template +# before PyInstaller builds the exe, so as to inject date/other infos into it. +*.manifest +*.spec + +# Installer logs +pip-log.txt +pip-delete-this-directory.txt + +# Unit test / coverage reports +htmlcov/ +.tox/ +.coverage +.coverage.* +.cache +nosetests.xml +coverage.xml +*,cover +.hypothesis/ + +# Translations +*.mo +*.pot + +# Django stuff: +*.log +local_settings.py + +# Flask stuff: +instance/ +.webassets-cache + +# Scrapy stuff: +.scrapy + +# Sphinx documentation +docs/_build/ + +# PyBuilder +target/ + +# IPython Notebook +.ipynb_checkpoints + +# pyenv +.python-version + +# celery beat schedule file +celerybeat-schedule + +# dotenv +.env + +# virtualenv +venv/ +.venv/ +ENV/ + +# Spyder project settings +.spyderproject + +# Rope project settings +.ropeproject + +# vscode +.vscode + +# Mac +.DS_Store + +# vim +*.swp + +# ckpt +*.lock + +# data +*.parquet + + +# local logs +logs +log +outputs +.history diff --git a/sk2decompile/verl/.pre-commit-config.yaml b/sk2decompile/verl/.pre-commit-config.yaml new file mode 100644 index 0000000..72e099f --- /dev/null +++ b/sk2decompile/verl/.pre-commit-config.yaml @@ -0,0 +1,8 @@ +repos: + - repo: https://github.com/astral-sh/ruff-pre-commit + rev: "v0.11.4" + hooks: + - id: ruff + args: ["--fix", "--show-fixes", "--output-format=full"] + exclude: ^.*\.(ipynb)$ + - id: ruff-format diff --git a/sk2decompile/verl/.readthedocs.yaml b/sk2decompile/verl/.readthedocs.yaml new file mode 100644 index 0000000..0016868 --- /dev/null +++ b/sk2decompile/verl/.readthedocs.yaml @@ -0,0 +1,19 @@ +# Read the Docs configuration file +# See https://docs.readthedocs.io/en/stable/config-file/v2.html for details + +version: 2 + +build: + os: ubuntu-22.04 + tools: + python: "3.11" + rust: "1.70" + +sphinx: + configuration: docs/conf.py + +python: + install: + - requirements: docs/requirements-docs.txt + - method: pip + path: . diff --git a/sk2decompile/verl/README.md b/sk2decompile/verl/README.md new file mode 100644 index 0000000..3775d44 --- /dev/null +++ b/sk2decompile/verl/README.md @@ -0,0 +1 @@ +Waitting to do \ No newline at end of file diff --git a/sk2decompile/verl/SK2DECOMPILE/data/sk2decompile-rl-examples.jsonl b/sk2decompile/verl/SK2DECOMPILE/data/sk2decompile-rl-examples.jsonl new file mode 100644 index 0000000..c2f7cfa --- /dev/null +++ b/sk2decompile/verl/SK2DECOMPILE/data/sk2decompile-rl-examples.jsonl @@ -0,0 +1,100 @@ +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long Verifie_Ligne_Produit(long long a1, const char *a2, int a3) {\n int v4;\n int v5;\n char *v6;\n int v7;\n int v8;\n __m128 v9;\n char *dest;\n int v12;\n int v13;\n int v14;\n char s[256];\n char src[264];\n unsigned long long v17;\n v17 = __readfsqword(40u);\n if (a2[(int)strlen(a2) - 1] == 10 || (int)strlen(a2) <= 254) {\n if (sscanf(a2, \"%d\\t%s\\t%s\\t%f\", &v13, s, src, &v14) == 4) {\n v4 = v13;\n if (v13 < 0) {\n v4 = -1;\n printf(\"La ligne %d est contient un no de produit invalide (< 0).\\n\",\n a3 + 1);\n } else {\n v12 = v14;\n v5 = strlen(s);\n v6 = (char *)malloc((unsigned int)(v5 + 1));\n v7 = strlen(src);\n dest = (char *)malloc((unsigned int)(v7 + 1));\n strcpy(v6, s);\n strcpy(dest, src);\n }\n } else {\n v4 = -1;\n printf(\"Le format de la ligne %d est incorrect.\\n\", a3 + 1);\n }\n } else {\n v4 = -1;\n printf(\"Nombre de caracteres trop grand sur la ligne %d.\\n\", a3 + 1);\n }\n v8 = v12;\n *(uint32_t *)a1 = v4;\n v9 = _mm_loadh_ps((const double *)&dest);\n *(uint32_t *)(a1 + 4) = v8;\n *(__m128 *)(a1 + 8) = v9;\n return a1;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "type1 Verifie_Ligne_Produit(char var1[], int var2) {\n int var3, var4, var5;\n float var6;\n char var7[255], var8[255];\n type1 var9;\n var4 = 0;\n if (var1[strlen(var1) - 1] != '\\n' && strlen(var1) >= 255) {\n printf(\"Nombre de caracteres trop grand sur la ligne %d.\\n\", var2 + 1);\n var4 = 1;\n } else {\n var3 = sscanf(var1, \"%d\\t%s\\t%s\\t%f\", &var5, var7, var8, &var6);\n if (var3 != 4) {\n printf(\"Le format de la ligne %d est incorrect.\\n\", var2 + 1);\n var4 = 1;\n } else {\n if (var5 < 0) {\n printf(\"La ligne %d est contient un no de produit invalide (< 0).\\n\",\n var2 + 1);\n var4 = 1;\n } else {\n var9.field1 = var5;\n var9.field2 = var6;\n var9.field3 = (char *)malloc(strlen(var7) * sizeof(char) + 1);\n var9.field4 = (char *)malloc(strlen(var8) * sizeof(char) + 1);\n strcpy(var9.field3, var7);\n strcpy(var9.field4, var8);\n }\n }\n }\n if (var4) {\n var9.field1 = -1;\n }\n return var9;\n}", "style": "rule"}, "extra_info": {"index": 7761, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_3__ TYPE_1__ ;\n\n/* Type definitions */\nstruct TYPE_3__ {int field1; float field2; char* field3; char* field4; } ;\ntypedef TYPE_1__ type1 ;\n\n/* Variables and functions */\n scalar_t__ malloc (int) ; \n int /*<<< orphan*/ printf (char*,int) ; \n int sscanf (char*,char*,int*,char*,char*,float*) ; \n int /*<<< orphan*/ strcpy (char*,char*) ; \n int strlen (char*) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long net_send(long long a1) {\n long long v1;\n long long v2;\n uint64_t *udata;\n uint64_t *v5;\n long long v6;\n unsigned int v7;\n long long v8;\n long long v9;\n long long v11;\n long long v12;\n long long v13;\n long long v14;\n long long v15;\n long long v16;\n uint8_t v17[4];\n long long v18;\n uint64_t v19[9];\n v19[1] = __readfsqword(40u);\n udata = (uint64_t *)net_get_udata();\n if (!udata) return luaL_error(a1, \"invalid user data\");\n v5 = udata;\n v6 = *udata;\n if (v6 == TYPE_TCP_SERVER) return luaL_error(a1, \"invalid user data\");\n v7 = 3;\n v8 = 2LL;\n v18 = 0LL;\n if (v6 == TYPE_UDP_SOCKET) {\n v19[0] = 0LL;\n v1 = luaL_checkinteger(a1, 2LL);\n if (!v1) return luaL_error(a1, \"need port\");\n v11 = luaL_checklstring(a1, 3LL, v19);\n if (!v11) return luaL_error(a1, \"need IP address\");\n v7 = 5;\n v8 = 4LL;\n if (!(unsigned int)ipaddr_aton(v11, v17))\n return luaL_error(a1, \"invalid IP address\");\n }\n v9 = luaL_checklstring(a1, v8, &v18);\n if (!v9 || !v18) return luaL_error(a1, \"no data to send\");\n if (lua_isfunction(a1, v7) || lua_islightfunction(a1, v7)) {\n lua_pushvalue(a1, v7);\n luaL_unref(a1, (unsigned int)LUA_REGISTRYINDEX, v5[3]);\n v5[3] = luaL_ref(a1, (unsigned int)LUA_REGISTRYINDEX);\n }\n if (*v5 != TYPE_UDP_SOCKET) goto LABEL_10;\n if (!*((uint32_t *)v5 + 10)) {\n v14 = udp_new();\n v5[4] = v14;\n if (!v14) return luaL_error(a1, \"cannot allocate PCB\");\n udp_recv(v14, (unsigned int)net_udp_recv_cb, v5);\n v15 = v5[4];\n LODWORD(v19[0]) = 0;\n v16 = udp_bind(v15, v19, 0LL);\n if (ERR_OK != v16) {\n udp_remove(v5[4]);\n v5[4] = 0LL;\n return lwip_lua_checkerr(a1, v16);\n }\n if (v5[1] == LUA_NOREF) {\n lua_pushvalue(a1, 1LL);\n v5[1] = luaL_ref(a1, (unsigned int)LUA_REGISTRYINDEX);\n }\n LABEL_10:\n if (*((uint32_t *)v5 + 10) && v5[1] != LUA_NOREF) {\n if (*v5 != TYPE_UDP_SOCKET) {\n if (*v5 == TYPE_TCP_CLIENT)\n v2 = tcp_write(*((unsigned int *)v5 + 4), v9, v18,\n (unsigned int)TCP_WRITE_FLAG_COPY);\n return lwip_lua_checkerr(a1, v2);\n }\n goto LABEL_27;\n }\n return luaL_error(a1, \"not connected\");\n }\n if (LUA_NOREF == v5[1]) return luaL_error(a1, \"not connected\");\nLABEL_27:\n v12 = pbuf_alloc((unsigned int)PBUF_TRANSPORT, v18, (unsigned int)PBUF_RAM);\n v13 = v12;\n if (v12) {\n pbuf_take(v12, v9, v18);\n v2 = udp_sendto(v5[4], v13, v17, v1);\n pbuf_free(v13);\n if (v5[3] != LUA_NOREF) {\n lua_rawgeti(a1, (unsigned int)LUA_REGISTRYINDEX);\n lua_rawgeti(a1, (unsigned int)LUA_REGISTRYINDEX);\n lua_call(a1, 1LL, 0LL);\n }\n return lwip_lua_checkerr(a1, v2);\n }\n return luaL_error(a1, \"cannot allocate message buffer\");\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "int net_send(type1 *var1) {\n type2 *var2 = net_get_udata(var1);\n if (!var2 || var2->field1 == var3)\n return luaL_error(var1, \"invalid user data\");\n type3 var4;\n uint16_t var5;\n const char *var6;\n size_t var7 = 0;\n int var8 = 2;\n if (var2->field1 == var9) {\n size_t var10 = 0;\n var5 = luaL_checkinteger(var1, var8++);\n if (var5 == 0) return luaL_error(var1, \"need port\");\n const char *var11 = luaL_checklstring(var1, var8++, &var10);\n if (!var11) return luaL_error(var1, \"need IP address\");\n if (!ipaddr_aton(var11, &var4))\n return luaL_error(var1, \"invalid IP address\");\n }\n var6 = luaL_checklstring(var1, var8++, &var7);\n if (!var6 || var7 == 0) return luaL_error(var1, \"no data to send\");\n if (lua_isfunction(var1, var8) || lua_islightfunction(var1, var8)) {\n lua_pushvalue(var1, var8++);\n luaL_unref(var1, var12, var2->field2.field3);\n var2->field2.field3 = luaL_ref(var1, var12);\n }\n if (var2->field1 == var9 && !var2->field4) {\n var2->field5 = udp_new();\n if (!var2->field5) return luaL_error(var1, \"cannot allocate PCB\");\n udp_recv(var2->field5, var13, var2);\n type3 var14 = {0};\n type4 var15 = udp_bind(var2->field5, &var14, 0);\n if (var15 != var16) {\n udp_remove(var2->field5);\n var2->field5 = NULL;\n return lwip_lua_checkerr(var1, var15);\n }\n if (var2->field6 == var17) {\n lua_pushvalue(var1, 1);\n var2->field6 = luaL_ref(var1, var12);\n }\n }\n if (!var2->field4 || var2->field6 == var17)\n return luaL_error(var1, \"not connected\");\n type4 var15;\n if (var2->field1 == var9) {\n struct type5 *var18 = pbuf_alloc(var19, var7, var20);\n if (!var18) return luaL_error(var1, \"cannot allocate message buffer\");\n pbuf_take(var18, var6, var7);\n var15 = udp_sendto(var2->field5, var18, &var4, var5);\n pbuf_free(var18);\n if (var2->field2.field3 != var17) {\n lua_rawgeti(var1, var12, var2->field2.field3);\n lua_rawgeti(var1, var12, var2->field6);\n lua_call(var1, 1, 0);\n }\n } else if (var2->field1 == var21) {\n var15 = tcp_write(var2->field7, var6, var7, var22);\n }\n return lwip_lua_checkerr(var1, var15);\n}", "style": "rule"}, "extra_info": {"index": 78379, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_11__ TYPE_3__ ;\ntypedef struct TYPE_10__ TYPE_2__ ;\ntypedef struct TYPE_9__ TYPE_1__ ;\n\n/* Type definitions */\ntypedef scalar_t__ uint16_t ;\ntypedef scalar_t__ type4 ;\nstruct TYPE_10__ {int /*<<< orphan*/ member_0; } ;\ntypedef TYPE_2__ type3 ;\nstruct TYPE_9__ {scalar_t__ field3; } ;\nstruct TYPE_11__ {scalar_t__ field1; scalar_t__ field6; int /*<<< orphan*/ field7; TYPE_1__ field2; int /*<<< orphan*/ * field5; int /*<<< orphan*/ field4; } ;\ntypedef TYPE_3__ type2 ;\ntypedef int /*<<< orphan*/ type1 ;\nstruct type5 {int dummy; } ;\n\n/* Variables and functions */\n int /*<<< orphan*/ ipaddr_aton (char const*,TYPE_2__*) ; \n scalar_t__ luaL_checkinteger (int /*<<< orphan*/ *,int /*<<< orphan*/ ) ; \n char* luaL_checklstring (int /*<<< orphan*/ *,int /*<<< orphan*/ ,size_t*) ; \n int luaL_error (int /*<<< orphan*/ *,char*) ; \n void* luaL_ref (int /*<<< orphan*/ *,int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ luaL_unref (int /*<<< orphan*/ *,int /*<<< orphan*/ ,scalar_t__) ; \n int /*<<< orphan*/ lua_call (int /*<<< orphan*/ *,int,int /*<<< orphan*/ ) ; \n scalar_t__ lua_isfunction (int /*<<< orphan*/ *,int) ; \n scalar_t__ lua_islightfunction (int /*<<< orphan*/ *,int) ; \n int /*<<< orphan*/ lua_pushvalue (int /*<<< orphan*/ *,int) ; \n int /*<<< orphan*/ lua_rawgeti (int /*<<< orphan*/ *,int /*<<< orphan*/ ,scalar_t__) ; \n int lwip_lua_checkerr (int /*<<< orphan*/ *,scalar_t__) ; \n TYPE_3__* net_get_udata (int /*<<< orphan*/ *) ; \n struct type5* pbuf_alloc (int /*<<< orphan*/ ,size_t,int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ pbuf_free (struct type5*) ; \n int /*<<< orphan*/ pbuf_take (struct type5*,char const*,size_t) ; \n scalar_t__ tcp_write (int /*<<< orphan*/ ,char const*,size_t,int /*<<< orphan*/ ) ; \n scalar_t__ udp_bind (int /*<<< orphan*/ *,TYPE_2__*,int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ * udp_new () ; \n int /*<<< orphan*/ udp_recv (int /*<<< orphan*/ *,int /*<<< orphan*/ ,TYPE_3__*) ; \n int /*<<< orphan*/ udp_remove (int /*<<< orphan*/ *) ; \n scalar_t__ udp_sendto (int /*<<< orphan*/ *,struct type5*,TYPE_2__*,scalar_t__) ; \n int /*<<< orphan*/ var12 ; \n int /*<<< orphan*/ var13 ; \n scalar_t__ var16 ; \n scalar_t__ var17 ; \n int /*<<< orphan*/ var19 ; \n int /*<<< orphan*/ var20 ; \n scalar_t__ var21 ; \n int /*<<< orphan*/ var22 ; \n scalar_t__ var3 ; \n scalar_t__ var9 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long GetTextLine(long long a1, uint8_t *a2, int a3, uint32_t *a4,\n uint32_t *a5) {\n int Character;\n int v7;\n int v8;\n char v9;\n int i;\n bool v11;\n long long v12;\n long long result;\n bool v14;\n bool v15;\n char v16;\n int v17;\n long long v18;\n char v19;\n uint8_t *v20;\n int v21;\n int v22;\n v20 = a2;\n do {\n do Character = ReadCharacter(a1);\n while ((unsigned int)(Character - 9) <= 1);\n } while (Character == 32);\n v7 = 0;\n v8 = 0;\n v9 = 0;\n v22 = a3 - 1;\n for (i = 0;; ++i) {\n if (Character != 34) {\n while (1) {\n if (v8) {\n v9 = 0;\n } else {\n v14 = v9;\n v15 = Character == 47;\n v16 = v9 & (Character == 47);\n if (v16) goto LABEL_30;\n if (Character == 59) {\n LABEL_29:\n v16 = v15;\n LABEL_30:\n if (i > 0 && v16)\n LODWORD(v12) = i - 1;\n else\n LODWORD(v12) = i;\n do Character = ReadCharacter(a1);\n while ((unsigned int)(Character + 1) > 1 && Character != 10);\n v8 = 0;\n if (!(uint32_t)v12) {\n *a2 = 0;\n goto LABEL_43;\n }\n goto LABEL_36;\n }\n LABEL_22:\n while (Character == 42 && v14) {\n v17 = 42;\n i = (i == 0) + i - 1;\n do {\n while (1) {\n v14 = v17 != 42 && v17 != -1;\n if (!v14) break;\n v17 = ReadCharacter(a1);\n }\n v17 = ReadCharacter(a1);\n } while (v17 != 47);\n v9 = 0;\n v8 = 0;\n Character = ReadCharacter(a1);\n v15 = Character == 47;\n if (Character == 34) goto LABEL_11;\n if (Character == 59) goto LABEL_29;\n }\n v8 = 0;\n }\n v11 = Character == 10;\n if (!v7 || Character != 10) break;\n i = (i == 0) + i - 1;\n v7 = 0;\n Character = ReadCharacter(a1);\n if (Character == 34) goto LABEL_11;\n }\n v12 = i;\n if (Character != 47) goto LABEL_13;\n v9 = 1;\n v7 = 0;\n if (v22 > i) goto LABEL_16;\n LABEL_19:\n Report(a1, 3LL, \"Line too long\");\n return 0LL;\n }\n LABEL_11:\n if (v8 == 1) {\n v14 = v9;\n goto LABEL_22;\n }\n v11 = 0;\n v12 = i;\n v8 ^= 1u;\n LABEL_13:\n v7 = Character == 92;\n if ((unsigned int)(Character + 1) <= 1) break;\n if (v11) {\n Character = 10;\n break;\n }\n v9 = 0;\n if (v22 <= i) goto LABEL_19;\n LABEL_16:\n a2[v12] = Character;\n Character = ReadCharacter(a1);\n }\n if (i) {\n LABEL_36:\n v18 = (int)v12;\n do {\n LODWORD(v12) = v18;\n v19 = v20[v18 - 1];\n if (v19 != 32 && v19 != 9) {\n v20 += v18;\n goto LABEL_41;\n }\n --v18;\n } while (v18);\n LODWORD(v12) = 0;\n }\nLABEL_41:\n *v20 = 0;\n if (v8) {\n v21 = Character;\n Report(a1, 3LL, \"Open Quotes\");\n Character = v21;\n }\nLABEL_43:\n if (a4) *a4 = v12;\n result = 1LL;\n if (a5) {\n if ((uint32_t)v12 || Character != -1) {\n *a5 = 0;\n return 1LL;\n } else {\n *a5 = 1;\n }\n }\n return result;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "static int GetTextLine(type1 *var1, char *var2, int var3, int *var4,\n int *var5) {\n int var6;\n int var7;\n int var8, var9, var10;\n do {\n var6 = ReadCharacter(var1);\n } while (var6 == ' ' || var6 == 0x9 || var6 == 0xa);\n var7 = 0;\n var8 = 0;\n var9 = 0;\n var10 = 0;\n for (;;) {\n if (var6 == '\"') var9 ^= 1;\n if (var9) var8 = 0;\n if ((var8 && var6 == '/') || (!var9 && var6 == ';')) {\n if (var6 == '/' && var7 > 0) var7--;\n while (var6 != 0 && var6 != -1 && var6 != 0xa) var6 = ReadCharacter(var1);\n break;\n } else if (var8 && var6 == '*') {\n if (var7 > 0) --var7;\n while (1) {\n while (var6 != -1 && var6 != '*') var6 = ReadCharacter(var1);\n var6 = ReadCharacter(var1);\n if (var6 == '/') break;\n }\n var6 = ReadCharacter(var1);\n var8 = 0;\n continue;\n } else if (var10 && var6 == '\\n') {\n if (var7 > 0) --var7;\n var6 = ReadCharacter(var1);\n var10 = 0;\n continue;\n }\n if (var6 == '/')\n var8 = 1;\n else\n var8 = 0;\n if (var6 == '\\\\')\n var10 = 1;\n else\n var10 = 0;\n if (var6 == 0 || var6 == -1 || var6 == 0xa) break;\n if (var7 < (var3 - 1)) {\n if (!(var10 && var6 == '\\n')) var2[var7++] = var6;\n } else {\n Report(var1, 3, \"Line too long\");\n return (0);\n }\n var6 = ReadCharacter(var1);\n }\n while (var7 > 0 && (var2[var7 - 1] == ' ' || var2[var7 - 1] == 0x9)) var7--;\n var2[var7] = 0;\n if (var9) Report(var1, 3, \"Open Quotes\");\n if (var4) *var4 = var7;\n if (var5) {\n if (var7 || var6 != -1)\n *var5 = 0;\n else\n *var5 = 1;\n }\n return (1);\n}", "style": "rule"}, "extra_info": {"index": 24378, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\ntypedef int /*<<< orphan*/ type1 ;\n\n/* Variables and functions */\n int ReadCharacter (int /*<<< orphan*/ *) ; \n int /*<<< orphan*/ Report (int /*<<< orphan*/ *,int,char*) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nuint64_t ***IoState_createOperatorTable(long long a1) {\n unsigned int v1;\n unsigned int v2;\n int *i;\n uint64_t ***v5;\n uint8_t v6[600];\n unsigned long long v7;\n v7 = __readfsqword(40u);\n qmemcpy(v6, &off_120, 592uLL);\n v5 = (uint64_t ***)IoMap_new(a1, &off_120 + 74, &off_120);\n for (i = (int *)v6; *(uint64_t *)i; i += 4) {\n v1 = IoState_numberWithDouble_(***v5, (double)i[2]);\n v2 = IoState_symbolWithCString_(***v5, *(uint64_t *)i);\n IoMap_rawAtPut(v5, v2, v1);\n }\n return v5;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "type1 *IoState_createOperatorTable(type2 *var1) {\n typedef struct type3 {\n char *field1;\n int field2;\n } type3;\n type3 var2[] = {\n {\"@\", 0}, {\"@@\", 0}, {\"?\", 0}, {\"**\", 1}, {\"*\", 2},\n {\"/\", 2}, {\"%\", 2}, {\"+\", 3}, {\"-\", 3}, {\"<<\", 4},\n {\">>\", 4}, {\">\", 5}, {\"<\", 5}, {\"<=\", 5}, {\">=\", 5},\n {\"==\", 6}, {\"!=\", 6}, {\"&\", 7}, {\"^\", 8}, {\"|\", 9},\n {\"and\", 10}, {\"&&\", 10}, {\"or\", 11}, {\"||\", 11}, {\"..\", 12},\n {\"+=\", 13}, {\"-=\", 13}, {\"*=\", 13}, {\"/=\", 13}, {\"%=\", 13},\n {\"&=\", 13}, {\"^=\", 13}, {\"|=\", 13}, {\"<<=\", 13}, {\">>=\", 13},\n {\"return\", 14}, {NULL, 0},\n };\n type1 *var3 = IoMap_new(var1);\n type3 *var4 = var2;\n while (var4->field1) {\n IoMap_rawAtPut(\n var3,\n IoState_symbolWithCString_(\n (type2 *)((type2 *)((((type4 *)(((type5 *)(var3))->field3))->field4)\n ->field5)),\n (char *)(var4->field1)),\n IoState_numberWithDouble_(\n (type2 *)((type2 *)((((type4 *)(((type5 *)(var3))->field3))->field4)\n ->field5)),\n (double)var4->field2));\n var4++;\n }\n return var3;\n}", "style": "rule"}, "extra_info": {"index": 43083, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_6__ TYPE_3__ ;\ntypedef struct TYPE_5__ TYPE_2__ ;\ntypedef struct TYPE_4__ TYPE_1__ ;\n\n/* Type definitions */\nstruct TYPE_5__ {scalar_t__ field3; } ;\ntypedef TYPE_2__ type5 ;\nstruct TYPE_6__ {TYPE_1__* field4; } ;\ntypedef TYPE_3__ type4 ;\ntypedef int /*<<< orphan*/ type2 ;\ntypedef int /*<<< orphan*/ type1 ;\nstruct TYPE_4__ {scalar_t__ field5; } ;\n\n/* Variables and functions */\n int /*<<< orphan*/ * IoMap_new (int /*<<< orphan*/ *) ; \n int /*<<< orphan*/ IoMap_rawAtPut (int /*<<< orphan*/ *,int /*<<< orphan*/ ,int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ IoState_numberWithDouble_ (int /*<<< orphan*/ *,double) ; \n int /*<<< orphan*/ IoState_symbolWithCString_ (int /*<<< orphan*/ *,char*) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nint pmat(int a1, int a2, long long a3) {\n int v3;\n int i;\n double *v5;\n double v6;\n int result;\n if (a1 > 0) {\n v3 = 0;\n for (i = 0; i != a1; ++i) {\n printf(\"row %d: \", i);\n if (a2 > 0) {\n v5 = (double *)(a3 + 8LL * v3);\n do {\n v6 = *v5++;\n printf(\"%.6f \", v6);\n } while (\n v5 !=\n (double *)(a3 +\n 8 * (v3 + (unsigned long long)(unsigned int)(a2 - 1)) +\n 8));\n v3 += a2;\n }\n result = putchar(10);\n }\n }\n return result;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "void pmat(int var1, int var2, double var3[]) {\n int var4;\n int var5;\n int var6;\n var6 = 0;\n for (var4 = 0; var4 < var1; var4++) {\n printf(\"row %d: \", var4);\n for (var5 = 0; var5 < var2; var5++) {\n printf(\"%.6f \", var3[var6]);\n var6 += 1;\n }\n printf(\"\\n\");\n }\n}", "style": "rule"}, "extra_info": {"index": 37724, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\n\n/* Variables and functions */\n int /*<<< orphan*/ printf (char*,...) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long update_anon_info(uint64_t *a1, const char *a2) {\n uint64_t *v2;\n int v3;\n unsigned int v4;\n long long **i;\n long long v6;\n long long v7;\n long long v8;\n long long v9;\n if (a2) {\n v2 = (uint64_t *)*a1;\n if (!*a1) goto LABEL_18;\n v3 = 0;\n v4 = 0;\n do {\n for (i = (long long **)v2[1]; i; i = (long long **)*i) {\n v6 = anonymize;\n if (!i[1]) {\n while (v6) {\n LODWORD(v7) = strcmp((const char *)*(unsigned int *)(v6 + 16), a2);\n if (!v7) {\n LODWORD(v8) = strcmp((const char *)*((unsigned int *)i + 4),\n *(const char **)v6);\n if (!v8) {\n LODWORD(v9) = strcmp((const char *)*((unsigned int *)i + 4),\n *(const char **)v6);\n if (!v9) {\n i[1] = (long long *)v6;\n ++v4;\n v3 = 1;\n break;\n }\n v3 = 1;\n }\n }\n v6 = *(uint64_t *)(v6 + 8);\n if (i[1]) break;\n }\n }\n }\n v2 = (uint64_t *)*v2;\n } while (v2);\n if (!v3)\n LABEL_18:\n panic(\"Unknown anonymization\", a2, 0LL);\n } else {\n return 0;\n }\n return v4;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "int update_anon_info(struct type1 *var1, char *var2) {\n struct type2 *var3 = var1->field1;\n struct type3 *var4;\n struct type4 *var5;\n int var6 = 0;\n int var7 = 0;\n if (var2 == NULL) return 0;\n while (var3 != NULL) {\n var4 = var3->field2;\n while (var4 != NULL) {\n var5 = var8;\n while (var4->field3 == NULL && var5 != NULL) {\n if (strcmp(var5->field4, var2) == 0 &&\n strcmp(var4->field5, var5->field6) == 0) {\n if (!var7) var7 = 1;\n if (strcmp(var4->field5, var5->field6) == 0) {\n var4->field3 = var5;\n var6++;\n }\n }\n var5 = var5->field7;\n }\n var4 = var4->field7;\n }\n var3 = var3->field7;\n }\n if (!var7) panic(\"Unknown anonymization\", var2, NULL);\n return var6;\n}", "style": "rule"}, "extra_info": {"index": 11236, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\nstruct type4 {char* field6; struct type4* field7; int /*<<< orphan*/ field4; } ;\nstruct type3 {struct type3* field7; struct type4* field3; int /*<<< orphan*/ field5; } ;\nstruct type2 {struct type2* field7; struct type3* field2; } ;\nstruct type1 {struct type2* field1; } ;\n\n/* Variables and functions */\n int /*<<< orphan*/ panic (char*,char*,int /*<<< orphan*/ *) ; \n scalar_t__ strcmp (int /*<<< orphan*/ ,char*) ; \n struct type4* var8 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long yadif_filter(int *a1, uint64_t *a2, unsigned int a3,\n unsigned int a4) {\n unsigned long long v5;\n int v6;\n int v7;\n int v8;\n int v9;\n int v10;\n long long v11;\n long long v12;\n long long v13;\n long long result;\n int *v15;\n char *v16;\n int *v17;\n char *v18;\n unsigned int v19;\n long long v20;\n int v21;\n void *v22;\n int v23;\n long long v24;\n long long v25;\n long long v26;\n v5 = _mm_unpacklo_epi32(_mm_cvtsi32_si128(a3), _mm_cvtsi32_si128(a4))\n .m128i_u64[0];\n v6 = *a1;\n v7 = HB_COMB_HEAVY;\n if ((MODE_DECOMB_SELECTIVE & *a1) != 0)\n v7 = **(uint32_t **)(*((uint64_t *)a1 + 1) + 8LL);\n v8 = MODE_DECOMB_BLEND;\n if ((MODE_DECOMB_BLEND & v6) == 0) {\n if (HB_COMB_NONE != v7) goto LABEL_6;\n if (!MODE_DECOMB_BLEND) {\n ++a1[13];\n ++a1[10];\n LABEL_28:\n *(uint32_t *)(*((uint64_t *)a1 + 2) + 8LL) = 0;\n return hb_buffer_copy(a2, *(uint64_t *)(*((uint64_t *)a1 + 1) + 8LL),\n *(double *)&v5);\n }\n LABEL_27:\n v5 = _mm_add_epi32(_mm_loadl_epi64((const __m128i *)(a1 + 10)),\n _mm_loadl_epi64((const __m128i *)&LC0))\n .m128i_u64[0];\n *((uint64_t *)a1 + 5) = v5;\n goto LABEL_28;\n }\n if (HB_COMB_LIGHT == v7) {\n ++a1[13];\n ++a1[10];\n if ((MODE_DECOMB_EEDI2 & v8) == 0) goto LABEL_31;\n goto LABEL_18;\n }\n if (v7 == HB_COMB_NONE) goto LABEL_27;\nLABEL_6:\n v9 = ~MODE_DECOMB_SELECTIVE & v6;\n if (MODE_DECOMB_BLEND == v9) {\n ++a1[13];\n ++a1[10];\n if ((MODE_DECOMB_EEDI2 & v8) == 0) {\n if (!v8) goto LABEL_28;\n LABEL_31:\n v9 = v8;\n goto LABEL_9;\n }\n LABEL_18:\n v9 = v8;\n goto LABEL_19;\n }\n if (!v9) goto LABEL_27;\n ++a1[12];\n ++a1[10];\n if ((MODE_DECOMB_EEDI2 & v9) == 0) {\n LABEL_9:\n v10 = a1[1];\n if (v10 > 0) {\n v11 = *((uint64_t *)a1 + 2);\n v12 = v11 + 24;\n v13 = v11 + 24 + 24LL * (unsigned int)(v10 - 1);\n while (1) {\n *(uint64_t *)(v11 + 16) = a2;\n *(uint32_t *)(v11 + 8) = v9;\n *(uint64_t *)v11 = v5;\n v11 = v12;\n if (v13 == v12) break;\n v12 += 24LL;\n }\n }\n return taskset_cycle(a1 + 6, *(double *)&v5);\n }\nLABEL_19:\n eedi2_planer(a1);\n if ((MODE_DECOMB_EEDI2 & v9) == 0 || (MODE_DECOMB_YADIF & v9) != 0)\n goto LABEL_9;\n v26 = 0LL;\n v25 = 0LL;\n do {\n v15 = (int *)(**(uint64_t **)(*((uint64_t *)a1 + 4) + 8 * DST2PF) + v25);\n v16 = (char *)*((uint64_t *)v15 + 1);\n v17 = (int *)(*a2 + v26);\n v18 = (char *)*((uint64_t *)v17 + 2);\n v19 = *v17;\n v23 = v17[1];\n if (v23 > 0) {\n v20 = 4LL * v17[2];\n v21 = 0;\n v24 = 4LL * *v15;\n do {\n v22 = v18;\n v18 += v20;\n memcpy(v22, v16, v19);\n ++v21;\n v16 += v24;\n } while (v23 != v21);\n }\n v25 += 16LL;\n result = v25;\n v26 += 24LL;\n } while (v25 != 48);\n return result;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "static void yadif_filter(type1* var1, type2* var2, int var3, int var4) {\n int var5 = var6;\n int var7 = 0;\n if (var1->field1 & var8) {\n var5 = var1->field2[1]->field3.field4;\n }\n if ((var1->field1 & var9) && var5 == var10) {\n var7 = var9;\n } else if (var5 != var11) {\n var7 = var1->field1 & ~var8;\n }\n if (var7 == var9) {\n var1->field5++;\n } else if (var7 != 0) {\n var1->field6++;\n } else {\n var1->field7++;\n }\n var1->field8++;\n if (var7 & var12) {\n eedi2_planer(var1);\n }\n if (var7 != 0) {\n if ((var7 & var12) && !(var7 & var13)) {\n int var14;\n for (var14 = 0; var14 < 3; var14++) {\n uint8_t* var15 = var1->field9[var16]->field10[var14].field11;\n int var17 = var1->field9[var16]->field10[var14].field12;\n uint8_t* var18 = var2->field10[var14].field11;\n int var19 = var2->field10[var14].field13;\n int var20 = var2->field10[var14].field14;\n int var21 = var2->field10[var14].field12;\n int var22;\n for (var22 = 0; var22 < var20; var22++) {\n memcpy(var18, var15, var19);\n var18 += var21;\n var15 += var17;\n }\n }\n } else {\n int var23;\n for (var23 = 0; var23 < var1->field15; var23++) {\n var1->field16[var23].field17 = var3;\n var1->field16[var23].field18 = var4;\n var1->field16[var23].field19 = var2;\n var1->field16[var23].field1 = var7;\n }\n taskset_cycle(&var1->field20);\n }\n } else {\n var1->field16[0].field1 = var7;\n hb_buffer_copy(var2, var1->field2[1]);\n }\n}", "style": "rule"}, "extra_info": {"index": 81957, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_20__ TYPE_7__ ;\ntypedef struct TYPE_19__ TYPE_6__ ;\ntypedef struct TYPE_18__ TYPE_5__ ;\ntypedef struct TYPE_17__ TYPE_4__ ;\ntypedef struct TYPE_16__ TYPE_3__ ;\ntypedef struct TYPE_15__ TYPE_2__ ;\ntypedef struct TYPE_14__ TYPE_1__ ;\ntypedef struct TYPE_13__ TYPE_11__ ;\n\n/* Type definitions */\ntypedef int /*<<< orphan*/ uint8_t ;\nstruct TYPE_19__ {TYPE_4__* field10; } ;\ntypedef TYPE_6__ type2 ;\nstruct TYPE_20__ {int field1; int field15; TYPE_11__** field2; TYPE_5__* field16; int /*<<< orphan*/ field20; TYPE_3__** field9; int /*<<< orphan*/ field8; int /*<<< orphan*/ field7; int /*<<< orphan*/ field6; int /*<<< orphan*/ field5; } ;\ntypedef TYPE_7__ type1 ;\nstruct TYPE_18__ {int field17; int field18; int field1; TYPE_6__* field19; } ;\nstruct TYPE_17__ {int field13; int field14; int field12; int /*<<< orphan*/ * field11; } ;\nstruct TYPE_16__ {TYPE_2__* field10; } ;\nstruct TYPE_15__ {int field12; int /*<<< orphan*/ * field11; } ;\nstruct TYPE_14__ {int field4; } ;\nstruct TYPE_13__ {TYPE_1__ field3; } ;\n\n/* Variables and functions */\n int /*<<< orphan*/ eedi2_planer (TYPE_7__*) ; \n int /*<<< orphan*/ hb_buffer_copy (TYPE_6__*,TYPE_11__*) ; \n int /*<<< orphan*/ memcpy (int /*<<< orphan*/ *,int /*<<< orphan*/ *,int) ; \n int /*<<< orphan*/ taskset_cycle (int /*<<< orphan*/ *) ; \n int var10 ; \n int var11 ; \n int var12 ; \n int var13 ; \n size_t var16 ; \n int var6 ; \n int var8 ; \n int var9 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nint printMap(int a1, long long a2) {\n long long v2;\n long long v3;\n int v4;\n const char *v5;\n if (a1 > 0) {\n v2 = a2 + 16LL * (unsigned int)(a1 - 1) + 16;\n v3 = a2;\n do {\n v4 = *(uint32_t *)(v3 + 8);\n v5 = *(const char **)v3;\n v3 += 16LL;\n printf(\"%s:%d\\n\", v5, v4);\n } while (v3 != v2);\n }\n return puts(\"\\n\");\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "void printMap(type1 var1) {\n int var2;\n for (var2 = 0; var2 < var1.field1; var2++)\n printf(\"%s:%d\\n\", var1.field2[var2].field3, var1.field2[var2].field4);\n printf(\"\\n\\n\");\n}", "style": "rule"}, "extra_info": {"index": 48996, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_5__ TYPE_2__ ;\ntypedef struct TYPE_4__ TYPE_1__ ;\n\n/* Type definitions */\nstruct TYPE_5__ {int field1; TYPE_1__* field2; } ;\ntypedef TYPE_2__ type1 ;\nstruct TYPE_4__ {char* field3; int field4; } ;\n\n/* Variables and functions */\n int /*<<< orphan*/ printf (char*,...) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nint main(int argc, const char **argv, const char **envp) {\n unsigned int v3;\n int i;\n int j;\n uint32_t v7[22];\n unsigned long long v8;\n v8 = __readfsqword(40u);\n v3 = time(0LL);\n srand(v3);\n for (i = 1; i <= 20; ++i) v7[i] = rand() % 20;\n heapsort(v7, 1LL, 20LL);\n for (j = 1; j <= 20; ++j) printf(\"%i \", v7[j]);\n putchar(10);\n return 0;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "int main(void) {\n int var1;\n type1 var2[20 + 1];\n srand(time(NULL));\n for (var1 = 1; var1 <= 20; ++var1) {\n var2[var1] = rand() % 20;\n }\n heapsort(var2, 1, 20);\n for (var1 = 1; var1 <= 20; ++var1) {\n printf(\"%i \", var2[var1]);\n }\n printf(\"\\n\");\n return 0;\n}", "style": "rule"}, "extra_info": {"index": 630, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\ntypedef int type1 ;\n\n/* Variables and functions */\n int /*<<< orphan*/ heapsort (int*,int,int) ; \n int /*<<< orphan*/ printf (char*,...) ; \n int rand () ; \n int /*<<< orphan*/ srand (int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ time (int /*<<< orphan*/ *) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long add_option(void **a1, const char *a2, int a3) {\n const char *v4;\n int v6;\n int v7;\n char *v8;\n char *v10;\n v4 = (const char *)*a1;\n if (v4) {\n v6 = strlen(v4);\n v7 = strlen(a2);\n v8 = (char *)realloc(*a1, (unsigned int)(v7 + v6 + a3 + 2));\n if (!v8) {\n LABEL_3:\n fprintf((FILE *)(unsigned int)stderr, \"%s: failed to allocate memory\\n\",\n (const char *)progname);\n return 4294967295LL;\n }\n v10 = v8;\n sprintf(&v8[v6], \",%s\", a2);\n } else {\n v10 = strdup(a2);\n if (!v10) goto LABEL_3;\n }\n *a1 = v10;\n return 0LL;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "static int add_option(char **var1, const char *var2, unsigned var3) {\n char *var4;\n if (*var1 == NULL)\n var4 = strdup(var2);\n else {\n unsigned var5 = strlen(*var1);\n unsigned var6 = var5 + 1 + strlen(var2) + var3 + 1;\n var4 = (char *)realloc(*var1, var6);\n if (var4) sprintf(var4 + var5, \",%s\", var2);\n }\n if (var4 == NULL) {\n fprintf(var7, \"%s: failed to allocate memory\\n\", var8);\n return -1;\n }\n *var1 = var4;\n return 0;\n}", "style": "rule"}, "extra_info": {"index": 60570, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\n\n/* Variables and functions */\n int /*<<< orphan*/ fprintf (int /*<<< orphan*/ ,char*,char*) ; \n scalar_t__ realloc (char*,unsigned int) ; \n int /*<<< orphan*/ sprintf (char*,char*,char const*) ; \n char* strdup (char const*) ; \n unsigned int strlen (char const*) ; \n int /*<<< orphan*/ var7 ; \n char* var8 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nuint64_t *on_request_path(uint64_t **a1, const void *a2, unsigned int a3) {\n uint64_t *result;\n uint64_t *v5;\n v5 = *a1;\n if (**a1 + a3 <= 255) memcpy((void *)(v5[1] + *v5), a2, a3);\n result = v5;\n *v5 += a3;\n return result;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "static void on_request_path(type1* var1, const char* var2, size_t var3) {\n type2* var4 = (type2*)var1->field1;\n if (var3 + var4->field2 < 256)\n memcpy(var4->field3 + var4->field2, var2, var3);\n var4->field2 += var3;\n}", "style": "rule"}, "extra_info": {"index": 32397, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_5__ TYPE_2__ ;\ntypedef struct TYPE_4__ TYPE_1__ ;\n\n/* Type definitions */\nstruct TYPE_4__ {size_t field2; scalar_t__ field3; } ;\ntypedef TYPE_1__ type2 ;\nstruct TYPE_5__ {scalar_t__ field1; } ;\ntypedef TYPE_2__ type1 ;\n\n/* Variables and functions */\n int /*<<< orphan*/ memcpy (scalar_t__,char const*,size_t) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long copy_data(int a1, int a2) {\n ssize_t i;\n unsigned int v4;\n long long n;\n uint8_t *buf;\n ssize_t j;\n uint8_t v8[16];\n unsigned long long v9;\n v9 = __readfsqword(40u);\n v4 = 0;\n for (i = read(a1, v8, 8192uLL);; i = read(a1, v8, 8192uLL)) {\n n = i;\n if (i <= 0) break;\n buf = v8;\n for (j = 0LL; n > 0; v4 += j) {\n j = write(a2, buf, n);\n if (j <= 0) break;\n buf += j;\n n -= j;\n }\n if (!j) {\n fprintf((FILE *)(unsigned int)stderr,\n \"Warning: EOF writing to output file.\\n\");\n return 4294967295LL;\n }\n }\n return v4;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "static int copy_data(int var1, int var2) {\n char var3[8192];\n ssize_t var4;\n int var5 = 0;\n while ((var4 = read(var1, var3, sizeof(var3))) > 0) {\n char *var6 = var3;\n ssize_t var7 = 0;\n while (var4 > 0 && (var7 = write(var2, var6, var4)) > 0) {\n var6 += var7;\n var4 -= var7;\n var5 += var7;\n }\n if (var7 == 0) {\n fprintf(var8, \"Warning: EOF writing to output file.\\n\");\n return (-1);\n }\n }\n return (var5);\n}", "style": "rule"}, "extra_info": {"index": 23049, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\ntypedef int /*<<< orphan*/ var3 ;\ntypedef scalar_t__ ssize_t ;\n\n/* Variables and functions */\n int /*<<< orphan*/ fprintf (int /*<<< orphan*/ ,char*) ; \n scalar_t__ read (int,char*,int) ; \n int /*<<< orphan*/ var8 ; \n scalar_t__ write (int,char*,scalar_t__) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long get_update_interval() {\n long long v0;\n long long v1;\n long long v2;\n long long v3;\n long long v5;\n long long v6;\n long long v7;\n long long v8;\n long long sensor_update_interval;\n long long v10;\n long long v11;\n long long v12;\n sensor_update_interval = get_sensor_update_interval(\"4-0040\");\n if (sensor_update_interval < 0)\n fprintf(\n (FILE *)(unsigned int)stderr,\n \"get_update_interval: Warning: could not read A15 update interval\\n\");\n v0 = sensor_update_interval;\n if (sensor_update_interval <= 0) v0 = 0LL;\n v5 = v0;\n v10 = get_sensor_update_interval(\"4-0045\");\n if (v10 < 0)\n fprintf(\n (FILE *)(unsigned int)stderr,\n \"get_update_interval: Warning: could not read A7 update interval\\n\");\n v1 = v10;\n if (v5 >= v10) v1 = v5;\n v6 = v1;\n v11 = get_sensor_update_interval(\"4-0041\");\n if (v11 < 0)\n fprintf(\n (FILE *)(unsigned int)stderr,\n \"get_update_interval: Warning: could not read MEM update interval\\n\");\n v2 = v11;\n if (v6 >= v11) v2 = v6;\n v7 = v2;\n v12 = get_sensor_update_interval(\"4-0044\");\n if (v12 < 0)\n fprintf(\n (FILE *)(unsigned int)stderr,\n \"get_update_interval: Warning: could not read GPU update interval\\n\");\n v3 = v12;\n if (v7 >= v12) v3 = v7;\n v8 = v3;\n if (!v3) {\n v8 = 263808LL;\n fprintf((FILE *)(unsigned int)stderr,\n \"get_update_interval: Using default value: %ld us\\n\", 263808LL);\n }\n return v8;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "static inline long get_update_interval() {\n long var1 = 0;\n long var2;\n var2 = get_sensor_update_interval(\"4-0040\");\n if (var2 < 0) {\n fprintf(var3,\n \"get_update_interval: Warning: could not read A15 update \"\n \"interval\\n\");\n }\n var1 = var2 > var1 ? var2 : var1;\n var2 = get_sensor_update_interval(\"4-0045\");\n if (var2 < 0) {\n fprintf(var3,\n \"get_update_interval: Warning: could not read A7 update \"\n \"interval\\n\");\n }\n var1 = var2 > var1 ? var2 : var1;\n var2 = get_sensor_update_interval(\"4-0041\");\n if (var2 < 0) {\n fprintf(var3,\n \"get_update_interval: Warning: could not read MEM update \"\n \"interval\\n\");\n }\n var1 = var2 > var1 ? var2 : var1;\n var2 = get_sensor_update_interval(\"4-0044\");\n if (var2 < 0) {\n fprintf(var3,\n \"get_update_interval: Warning: could not read GPU update \"\n \"interval\\n\");\n }\n var1 = var2 > var1 ? var2 : var1;\n if (var1 == 0) {\n var1 = 263808;\n fprintf(var3, \"get_update_interval: Using default value: %ld us\\n\", var1);\n }\n return var1;\n}", "style": "rule"}, "extra_info": {"index": 30190, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\n\n/* Variables and functions */\n int /*<<< orphan*/ fprintf (int /*<<< orphan*/ ,char*,...) ; \n long get_sensor_update_interval (char*) ; \n int /*<<< orphan*/ var3 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long eval_empty_actions(unsigned long long a1, unsigned long long a2) {\n unsigned int v2;\n uint64_t *v3;\n unsigned int v5;\n unsigned int v6;\n char *v7;\n long long v8;\n long long v9;\n __m128i v10;\n long long v11;\n int v12;\n unsigned int v13;\n int **i;\n int v15;\n __m128i v16;\n void *v17;\n void *ptr;\n __m128i v19;\n int v20;\n long long v21;\n int v22;\n unsigned long long v23;\n v2 = 0;\n v3 = *(uint64_t **)(a2 + 24);\n v23 = __readfsqword(40u);\n v16 = _mm_unpacklo_epi64((__m128i)a1, (__m128i)a2);\n if (*v3) return v2;\n v22 = *(uint32_t *)(a2 + 16);\n v5 = pathname(a2);\n ptr = strdup((const char *)v5);\n v6 = subpathname(a2);\n v7 = strdup((const char *)v6);\n v10 = _mm_load_si128(&v16);\n v11 = (unsigned int)empty_count;\n v17 = v7;\n v21 = *(uint64_t *)(a2 + 8);\n v12 = 0;\n LODWORD(v7) = **(uint32_t **)a2;\n v19 = v10;\n v20 = (int)v7;\n if (empty_count > 0) {\n LABEL_9:\n for (i = (int **)(empty_spec + 8LL * v12);; ++i) {\n ++v12;\n v15 = **i;\n if (v15 == 2) {\n if (v3[1]) goto LABEL_7;\n } else if (v15 != 1 || !v3[1]) {\n LABEL_7:\n v13 = ((long long (*)(int **, void **, long long, long long, long long,\n long long, long long, long long))eval_expr_top)(\n i, &v17, v11, empty_spec, v8, v9, v16.m128i_i64[0],\n v16.m128i_i64[1]);\n v11 = (unsigned int)empty_count;\n v2 = v13;\n if (empty_count <= v12 || v13) goto LABEL_15;\n goto LABEL_9;\n }\n if ((int)v11 <= v12) break;\n }\n }\n v2 = 0;\nLABEL_15:\n free(ptr);\n free(v17);\n return v2;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "int eval_empty_actions(struct type1 *var1, struct type2 *var2) {\n int var3, var4 = 0;\n struct type3 var5;\n struct type4 *var6;\n struct type1 *var7 = var2->field1;\n if (var7->field2 != 0) return 0;\n var5.field3 = var2->field3;\n var5.field4 = strdup(pathname(var2));\n var5.field5 = strdup(subpathname(var2));\n var5.field6 = &var2->field7->field6;\n var5.field8 = var2->field9->field8;\n var5.field10 = var2;\n var5.field11 = var1;\n for (var3 = 0; var3 < var8 && !var4; var3++) {\n var6 = var9[var3].field12;\n# 1674 \"/scratch/repos/new/home/jordi_armengol_estape/c-scraper/outputs/2022-01-22/02-19-57/repos/plougher/squashfs-tools/refs/heads/master/squashfs-tools/action.c\"\n if ((var6->field13 == 2 && !var7->field14) ||\n (var6->field13 == 1 && var7->field14))\n continue;\n var4 = func1(&var9[var3], &var5);\n }\n free(var5.field4);\n free(var5.field5);\n return var4;\n}", "style": "rule"}, "extra_info": {"index": 24170, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_7__ TYPE_3__ ;\ntypedef struct TYPE_6__ TYPE_2__ ;\ntypedef struct TYPE_5__ TYPE_1__ ;\n\n/* Type definitions */\nstruct type4 {int field13; } ;\nstruct type3 {void* field5; void* field4; struct type1* field11; struct type2* field10; int /*<<< orphan*/ field8; int /*<<< orphan*/ * field6; int /*<<< orphan*/ field3; } ;\nstruct type2 {TYPE_2__* field9; TYPE_1__* field7; int /*<<< orphan*/ field3; struct type1* field1; } ;\nstruct type1 {scalar_t__ field2; scalar_t__ field14; } ;\nstruct TYPE_7__ {struct type4* field12; } ;\nstruct TYPE_6__ {int /*<<< orphan*/ field8; } ;\nstruct TYPE_5__ {int /*<<< orphan*/ field6; } ;\n\n/* Variables and functions */\n int /*<<< orphan*/ free (void*) ; \n int func1 (TYPE_3__*,struct type3*) ; \n int /*<<< orphan*/ pathname (struct type2*) ; \n void* strdup (int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ subpathname (struct type2*) ; \n int var8 ; \n TYPE_3__* var9 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long fh_cli_cmd_process(uint8_t *a1) {\n uint8_t *i;\n long long v2;\n unsigned int v3;\n int v5;\n int v6;\n void **v7;\n uint8_t **v8;\n int v9;\n int v10;\n long long v11;\n void *v12;\n uint32_t v13[128];\n uint64_t v14[135];\n v14[129] = __readfsqword(40u);\n if (a1) {\n for (i = a1;; ++i) {\n LODWORD(v2) = isspace((char)*i);\n if (!v2) break;\n }\n if (*i && (v5 = fh_cli_cmd_parse(i, v14, 128LL), (v6 = v5) != 0)) {\n if (v5 <= 0) {\n v13[0] = 0;\n return (\n unsigned int)((long long (*)(void *, uint64_t, uint64_t *, uint64_t,\n uint32_t *, uint64_t))fh_cli_cmd_find)(\n &cmd_list, (unsigned int)v5, v14, 0LL, v13, 0LL);\n } else {\n v7 = (void **)v14;\n v8 = (uint8_t **)v14;\n v9 = 0;\n v10 = 0;\n do {\n if (**v8 == 124) {\n v11 = v9++;\n v13[v11] = v10;\n }\n ++v10;\n ++v8;\n } while (v6 > v10 && v9 <= 126);\n v13[v9] = 0;\n v3 = ((long long (*)(void *, uint64_t, uint64_t *, uint64_t, uint32_t *,\n uint64_t))fh_cli_cmd_find)(\n &cmd_list, (unsigned int)v6, v14, 0LL, v13, 0LL);\n do {\n v12 = *v7++;\n free(v12);\n } while (v7 != &v14[(unsigned int)(v6 - 1) + 1]);\n }\n } else {\n return 0;\n }\n } else {\n return (unsigned int)-1;\n }\n return v3;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "int fh_cli_cmd_process(char *var1) {\n char *var2[128];\n int var3[128];\n int var4;\n int var5 = 0;\n int var6, var7;\n if (!var1) return -1;\n while (isspace(*var1)) var1++;\n if (!*var1) {\n return 0;\n }\n var4 = fh_cli_cmd_parse(var1, var2, 128);\n if (var4 == 0) {\n return 0;\n }\n for (var6 = var7 = 0; var6 < var4 && var7 < 128 - 1; var6++) {\n if (var2[var6][0] == '|') {\n var3[var7++] = var6;\n }\n }\n var3[var7] = 0;\n if (var4) {\n var5 = func1(&var8, var4, var2, 0, var3, NULL);\n } else {\n var5 = -1;\n }\n for (var6 = 0; var6 < var4; var6++) {\n free(var2[var6]);\n }\n return var5;\n}", "style": "rule"}, "extra_info": {"index": 84318, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\n\n/* Variables and functions */\n int fh_cli_cmd_parse (char*,char**,int) ; \n int /*<<< orphan*/ free (char*) ; \n int func1 (int /*<<< orphan*/ *,int,char**,int /*<<< orphan*/ ,int*,int /*<<< orphan*/ *) ; \n scalar_t__ isspace (char) ; \n int /*<<< orphan*/ var8 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nint main(int argc, const char **argv, const char **envp) {\n __m128i si128;\n __m128i v4;\n long long *v5;\n __m128i v6;\n long long v7;\n int v8;\n long long v9;\n uint8_t *v10;\n pthread_t *v11;\n unsigned int *v12;\n unsigned int *v13;\n pthread_t v14;\n int v16;\n uint8_t v17[1024];\n uint8_t v18[1008];\n long long v19;\n int v20;\n unsigned long long v21;\n si128 = _mm_load_si128((const __m128i *)&LC0);\n v4 = _mm_load_si128((const __m128i *)&LC1);\n v21 = __readfsqword(40u);\n v5 = (long long *)v18;\n do {\n v6 = si128;\n v5 += 2;\n si128 = _mm_add_epi32(si128, v4);\n *((__m128i *)v5 - 1) = v6;\n } while (v5 != &v19);\n v20 = 254;\n v19 = LC2;\n while (1) {\n printf(\"Nombre de threads : \");\n LODWORD(v7) = fscanf((FILE *)(unsigned int)stdin, \"%d\", &v16);\n if (v7 == EOF) break;\n if (v16 > 255) {\n fprintf((FILE *)(unsigned int)stderr, \"La valeur max est 255\\n\");\n } else {\n RWLOCK_WRITE(*(double *)si128.m128i_i64);\n v8 = nb_thread;\n nb_thread = v16;\n RWUNLOCK();\n if (v16 < v8) {\n v12 = (unsigned int *)&v17[4 * v16];\n v13 = (unsigned int *)&v17[4 * (unsigned int)(v8 - 1 - v16) + 4 +\n 4 * (long long)v16];\n do {\n v14 = *v12++;\n pthread_join(v14, 0LL);\n } while (v12 != v13);\n } else if (v16 > v8) {\n v9 = 4LL * v8;\n do {\n ++v8;\n v10 = &v18[v9];\n v11 = (pthread_t *)&v17[v9];\n v9 += 4LL;\n pthread_create(v11, 0LL, (void *(*)(void *))(unsigned int)thd_main,\n v10);\n } while (v16 > v8);\n }\n }\n }\n return 0;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "int main(int var1, char *var2[]) {\n int var3;\n type1 var4[255];\n int var5[255];\n int var6;\n int var7;\n for (var6 = 0; var6 < 255; var6++) {\n var5[var6] = var6;\n }\n while (1) {\n printf(\"Nombre de threads : \");\n if (var8 == fscanf(var9, \"%d\", &var3)) {\n break;\n }\n if (var3 > 255) {\n fprintf(var10, \"La valeur max est 255\\n\");\n continue;\n }\n RWLOCK_WRITE();\n var7 = var11;\n var11 = var3;\n RWUNLOCK();\n if (var3 < var7) {\n for (var6 = var3; var6 < var7; var6++) {\n pthread_join(var4[var6], NULL);\n }\n } else if (var3 > var7) {\n for (var6 = var7; var6 < var3; var6++) {\n pthread_create(&(var4[var6]), NULL, var12, &(var5[var6]));\n }\n }\n }\n return 0;\n}", "style": "rule"}, "extra_info": {"index": 56913, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\ntypedef int /*<<< orphan*/ type1 ;\n\n/* Variables and functions */\n int /*<<< orphan*/ RWLOCK_WRITE () ; \n int /*<<< orphan*/ RWUNLOCK () ; \n int /*<<< orphan*/ fprintf (int /*<<< orphan*/ ,char*) ; \n scalar_t__ fscanf (int /*<<< orphan*/ ,char*,int*) ; \n int /*<<< orphan*/ printf (char*) ; \n int /*<<< orphan*/ pthread_create (int /*<<< orphan*/ *,int /*<<< orphan*/ *,int /*<<< orphan*/ ,int*) ; \n int /*<<< orphan*/ pthread_join (int /*<<< orphan*/ ,int /*<<< orphan*/ *) ; \n int /*<<< orphan*/ var10 ; \n int var11 ; \n int /*<<< orphan*/ var12 ; \n scalar_t__ var8 ; \n int /*<<< orphan*/ var9 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nint *collect_entries(const char *a1, unsigned int a2) {\n int *v2;\n int *v3;\n int *v4;\n struct dirent *v5;\n long long v6;\n long long v7;\n __m128 *v8;\n uint64_t *v9;\n int v10;\n __m128 *v13;\n char *v14;\n char *v15[9];\n v15[1] = (char *)__readfsqword(40u);\n v2 = opendir(a1);\n if (!v2) return 0LL;\n v3 = v2;\n v4 = (int *)directory_new();\n while (1) {\n v5 = readdir(v3);\n if (!v5) break;\n while (1) {\n LODWORD(v6) = strcmp((const char *)v5->d_ino, \".\");\n if (!v6) break;\n LODWORD(v7) = strcmp((const char *)v5->d_ino, \"..\");\n if (!v7) break;\n asprintf(&v14, \"%s\", (const char *)v5->d_ino);\n asprintf(v15, \"%s\", a1);\n v8 = (__m128 *)entry_new();\n *v8 = _mm_loadh_ps((const double *)v15);\n v8[1].m128_i32[0] = v5->d_off == DT_DIR;\n if (a2) {\n v13 = v8;\n populate_entry_details(v8, a2);\n v8 = v13;\n }\n v9 = (uint64_t *)*((uint64_t *)v4 + 1);\n v10 = *v4;\n v9[*v4 - 1] = v8;\n *v4 = ++v10;\n *((uint64_t *)v4 + 1) = realloc(v9, (unsigned int)(24 * v10));\n v5 = readdir(v3);\n if (!v5) goto LABEL_9;\n }\n }\nLABEL_9:\n closedir(v3);\n return v4;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "type1 *collect_entries(const char *var1, type2 var2) {\n struct type3 *var3;\n type4 *var4 = opendir(var1);\n if (var4 == NULL) {\n return NULL;\n }\n type1 *var5 = directory_new();\n while ((var3 = readdir(var4)) != NULL) {\n if (strcmp(var3->field1, \".\") == 0 || strcmp(var3->field1, \"..\") == 0) {\n continue;\n }\n char *var6, *var7;\n asprintf(&var6, \"%s\", var3->field1);\n asprintf(&var7, \"%s\", var1);\n type5 *var8 = entry_new();\n var8->field2 = var6;\n var8->field3 = var7;\n var8->field4 = (var3->field5 == var9 ? 1 : 0);\n if (var2) {\n populate_entry_details(var8, var2);\n }\n var5->field6[var5->field7 - 1] = var8;\n var5->field7++;\n var5->field6 = realloc(var5->field6, var5->field7 * sizeof(var10));\n }\n closedir(var4);\n return var5;\n}", "style": "rule"}, "extra_info": {"index": 77991, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_10__ TYPE_2__ ;\ntypedef struct TYPE_9__ TYPE_1__ ;\n\n/* Type definitions */\ntypedef int /*<<< orphan*/ var10 ;\nstruct TYPE_9__ {char* field2; char* field3; int field4; } ;\ntypedef TYPE_1__ type5 ;\ntypedef int /*<<< orphan*/ type4 ;\ntypedef int /*<<< orphan*/ type2 ;\nstruct TYPE_10__ {int field7; TYPE_1__** field6; } ;\ntypedef TYPE_2__ type1 ;\nstruct type3 {char const* field1; scalar_t__ field5; } ;\n\n/* Variables and functions */\n int /*<<< orphan*/ asprintf (char**,char*,char const*) ; \n int /*<<< orphan*/ closedir (int /*<<< orphan*/ *) ; \n TYPE_2__* directory_new () ; \n TYPE_1__* entry_new () ; \n int /*<<< orphan*/ * opendir (char const*) ; \n int /*<<< orphan*/ populate_entry_details (TYPE_1__*,int /*<<< orphan*/ ) ; \n struct type3* readdir (int /*<<< orphan*/ *) ; \n TYPE_1__** realloc (TYPE_1__**,int) ; \n scalar_t__ strcmp (char const*,char*) ; \n scalar_t__ var9 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nint main(int argc, const char **argv, const char **envp) {\n const char **v4;\n int v5;\n int i;\n int j;\n v5 = argc;\n v4 = argv;\n for (i = 0; i < argc; ++i) {\n printf(\"i = %d; \", i);\n printf(\"argv [ %d ] = %s;\\n\", i, argv[i]);\n }\n for (j = 0; j < argc; ++j) {\n printf(\"* ( argv + %d ) = %s;\\n\", j, argv[j]);\n printf(\"* ( ( argv + %d ) + %d ) = %c;\\n\", j, 2, argv[j + 2]);\n }\n while (v5 > 0) {\n printf(\"argc = %d;\", v5);\n printf(\" i = %d;\", j);\n printf(\" * argv = %s;\", *v4);\n printf(\" argv [ %d ] = %s;\", j, v4[j]);\n putchar(10);\n ++j;\n --v5;\n ++v4;\n }\n return 0;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "int main(int var1, char* var2[]) {\n int var3 = 0;\n int var4 = 2;\n while (var3 < var1) {\n printf(\"i = %d; \", var3);\n printf(\"argv [ %d ] = %s;\\n\", var3, var2[var3]);\n var3++;\n }\n var3 = 0;\n while (var3 < var1) {\n printf(\"* ( argv + %d ) = %s;\\n\", var3, *(var2 + var3));\n printf(\"* ( ( argv + %d ) + %d ) = %c;\\n\", var3, var4,\n *((var2 + var3) + var4));\n var3++;\n }\n while (var1 > 0) {\n printf(\"argc = %d;\", var1);\n printf(\" i = %d;\", var3);\n printf(\" * argv = %s;\", *var2);\n printf(\" argv [ %d ] = %s;\", var3, var2[var3]);\n printf(\"\\n\");\n var3++;\n var1--;\n *var2++;\n }\n return 0;\n}", "style": "rule"}, "extra_info": {"index": 87208, "split": "train", "header": null}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nunsigned long long init_recursive_mutex(pthread_mutex_t *mutex) {\n pthread_mutexattr_t attr;\n unsigned long long v3;\n v3 = __readfsqword(40u);\n pthread_mutexattr_init(&attr);\n pthread_mutexattr_settype(&attr, PTHREAD_MUTEX_RECURSIVE);\n pthread_mutex_init(mutex, &attr);\n pthread_mutexattr_destroy(&attr);\n return v3 - __readfsqword(40u);\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "static inline void init_recursive_mutex(type1 *var1) {\n type2 var2;\n pthread_mutexattr_init(&var2);\n pthread_mutexattr_settype(&var2, var3);\n pthread_mutex_init(var1, &var2);\n pthread_mutexattr_destroy(&var2);\n}", "style": "rule"}, "extra_info": {"index": 45874, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\ntypedef int /*<<< orphan*/ type2 ;\ntypedef int /*<<< orphan*/ type1 ;\n\n/* Variables and functions */\n int /*<<< orphan*/ pthread_mutex_init (int /*<<< orphan*/ *,int /*<<< orphan*/ *) ; \n int /*<<< orphan*/ pthread_mutexattr_destroy (int /*<<< orphan*/ *) ; \n int /*<<< orphan*/ pthread_mutexattr_init (int /*<<< orphan*/ *) ; \n int /*<<< orphan*/ pthread_mutexattr_settype (int /*<<< orphan*/ *,int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ var3 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nuint64_t *cl_pool_clear(long long a1) {\n uint64_t *result;\n uint64_t *v2;\n uint64_t *v3;\n result = *(uint64_t **)a1;\n if (*(uint64_t *)a1) {\n v2 = *(uint64_t **)(a1 + 8);\n while (1) {\n v3 = (uint64_t *)*result;\n *result = v2;\n v2 = result;\n *(uint64_t *)(a1 + 8) = result;\n if (!v3) break;\n result = v3;\n }\n }\n *(uint64_t *)a1 = 0LL;\n *(uint64_t *)(a1 + 16) = 0LL;\n return result;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "void cl_pool_clear(struct type1 *var1) {\n void **var2 = var1->field1;\n while (var2) {\n void **var3 = var2;\n var2 = *var2;\n *var3 = var1->field2;\n var1->field2 = var3;\n }\n var1->field1 = NULL;\n var1->field3 = NULL;\n}", "style": "rule"}, "extra_info": {"index": 34514, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\nstruct type1 {void** field1; void** field2; int /*<<< orphan*/ * field3; } ;\n\n/* Variables and functions */\n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long pci_xhci_cmd_address_device(long long a1, unsigned int a2,\n uint32_t *a3) {\n long long v4;\n int *dest;\n long long v6;\n v4 = XHCI_GADDR(a1, *a3 & 4294967280);\n DPRINTF(*(int *)(*(uint64_t *)(v4 + 16) + 40LL));\n if (!*(uint64_t *)v4 && (*(uint32_t *)(v4 + 8) & 3) == 3) {\n dest = (int *)pci_xhci_get_dev_ctx(a1, a2);\n DPRINTF(*dest);\n v6 = XHCI_SLOTDEV_PTR(a1, a2);\n assert(v6 != 0);\n }\n DPRINTF(\"pci_xhci: address device, input ctl invalid\\r\\n\");\n return (unsigned int)XHCI_TRB_ERROR_TRB;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "static uint32_t pci_xhci_cmd_address_device(struct type1 *var1, uint32_t var2,\n struct type2 *var3) {\n struct type3 *var4;\n struct type4 *var5;\n struct type5 *var6;\n struct type6 *var7;\n struct type7 *var8;\n uint32_t var9;\n var5 = XHCI_GADDR(var1, var3->field1 & ~0xFUL);\n var6 = &var5->field2;\n var8 = &var5->field3[1];\n var9 = var10;\n DPRINTF(\n (\"pci_xhci: address device, input ctl: D 0x%08x A 0x%08x,\\r\\n\"\n \" slot %08x %08x %08x %08x\\r\\n\"\n \" ep0 %08x %08x %016lx %08x\\r\\n\",\n var5->field4.field5, var5->field4.field6, var6->field7, var6->field8,\n var6->field9, var6->field10, var8->field11, var8->field12, var8->field13,\n var8->field14));\n if ((var5->field4.field5 != 0) || (var5->field4.field6 & 0x03) != 0x03) {\n DPRINTF((\"pci_xhci: address device, input ctl invalid\\r\\n\"));\n var9 = var11;\n goto done;\n }\n var7 = pci_xhci_get_dev_ctx(var1, var2);\n DPRINTF(\n (\"pci_xhci: address device, dev ctx\\r\\n\"\n \" slot %08x %08x %08x %08x\\r\\n\",\n var7->field2.field7, var7->field2.field8, var7->field2.field9,\n var7->field2.field10));\n var4 = XHCI_SLOTDEV_PTR(var1, var2);\n assert(var4 != NULL);\n var4->field15.field16 = var2;\n var4->field17 = var7;\n if (var4->field18->field19 == NULL ||\n var4->field18->field19(var4->field20) < 0) {\n var9 = var12;\n goto done;\n }\n memcpy(&var7->field2, var6, sizeof(struct type5));\n var7->field2.field10 = func1(var13) | func2(var2);\n memcpy(&var7->field3[1], var8, sizeof(struct type7));\n var8 = &var7->field3[1];\n var8->field11 = (var8->field11 & ~0x7) | func3(var14);\n func4(var4, 1);\n var4->field21 = var15;\n DPRINTF(\n (\"pci_xhci: address device, output ctx\\r\\n\"\n \" slot %08x %08x %08x %08x\\r\\n\"\n \" ep0 %08x %08x %016lx %08x\\r\\n\",\n var7->field2.field7, var7->field2.field8, var7->field2.field9,\n var7->field2.field10, var8->field11, var8->field12, var8->field13,\n var8->field14));\ndone:\n return (var9);\n}", "style": "rule"}, "extra_info": {"index": 38104, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_6__ TYPE_3__ ;\ntypedef struct TYPE_5__ TYPE_2__ ;\ntypedef struct TYPE_4__ TYPE_1__ ;\n\n/* Type definitions */\ntypedef int /*<<< orphan*/ uint32_t ;\nstruct type7 {int field10; int field11; int /*<<< orphan*/ field14; int /*<<< orphan*/ field13; int /*<<< orphan*/ field12; int /*<<< orphan*/ field9; int /*<<< orphan*/ field8; int /*<<< orphan*/ field7; } ;\nstruct type6 {struct type7 field2; struct type7* field3; } ;\nstruct type5 {int field10; int field11; int /*<<< orphan*/ field14; int /*<<< orphan*/ field13; int /*<<< orphan*/ field12; int /*<<< orphan*/ field9; int /*<<< orphan*/ field8; int /*<<< orphan*/ field7; } ;\nstruct TYPE_4__ {scalar_t__ field5; int field6; } ;\nstruct type4 {TYPE_1__ field4; struct type7* field3; struct type7 field2; } ;\nstruct TYPE_5__ {int /*<<< orphan*/ field16; } ;\nstruct type3 {int /*<<< orphan*/ field21; int /*<<< orphan*/ field20; TYPE_3__* field18; struct type6* field17; TYPE_2__ field15; } ;\nstruct type2 {int field1; } ;\nstruct type1 {int dummy; } ;\nstruct TYPE_6__ {scalar_t__ (* field19 ) (int /*<<< orphan*/ ) ;} ;\n\n/* Variables and functions */\n int /*<<< orphan*/ DPRINTF (char*) ; \n struct type4* XHCI_GADDR (struct type1*,int) ; \n struct type3* XHCI_SLOTDEV_PTR (struct type1*,int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ assert (int /*<<< orphan*/ ) ; \n int func1 (int /*<<< orphan*/ ) ; \n int func2 (int /*<<< orphan*/ ) ; \n int func3 (int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ func4 (struct type3*,int) ; \n int /*<<< orphan*/ memcpy (struct type7*,struct type7*,int) ; \n struct type6* pci_xhci_get_dev_ctx (struct type1*,int /*<<< orphan*/ ) ; \n scalar_t__ stub1 (int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ var10 ; \n int /*<<< orphan*/ var11 ; \n int /*<<< orphan*/ var12 ; \n int /*<<< orphan*/ var13 ; \n int /*<<< orphan*/ var14 ; \n int /*<<< orphan*/ var15 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long BIO_gets(long long a1, long long a2, int a3, long long a4,\n long long a5) {\n uint64_t *v5;\n unsigned long long v6;\n long long result;\n unsigned long long v8;\n bool v9;\n long long v10;\n uint64_t v11[5];\n v11[1] = __readfsqword(40u);\n v11[0] = 0LL;\n if (!a1 || (v5 = *(uint64_t **)(a1 + 16)) == 0LL || !*v5) {\n BIOerr((unsigned int)BIO_F_BIO_GETS,\n (unsigned int)BIO_R_UNSUPPORTED_METHOD);\n return 4294967294LL;\n }\n v6 = a3;\n if (a3 < 0) {\n BIOerr((unsigned int)BIO_F_BIO_GETS, (unsigned int)BIO_R_INVALID_ARGUMENT);\n return 0LL;\n }\n if (!*(uint64_t *)(a1 + 8) && !*(uint64_t *)a1 ||\n (result = bio_call_callback(a1, (unsigned int)BIO_CB_GETS, a2,\n (unsigned int)a3, 0LL, 0LL, 1LL, 0LL),\n a5 = v10, (int)result > 0)) {\n if (!*(uint32_t *)(a1 + 24)) {\n BIOerr((unsigned int)BIO_F_BIO_GETS, (unsigned int)BIO_R_UNINITIALIZED);\n return 4294967294LL;\n }\n result = (**(long long (***)(long long, long long, uint64_t, long long,\n long long))(a1 + 16))(a1, a2, (unsigned int)v6,\n a4, a5);\n if ((int)result > 0) {\n v8 = (int)result;\n v9 = *(uint64_t *)(a1 + 8) == 0LL;\n result = 1LL;\n v11[0] = v8;\n if (v9 && !*(uint64_t *)a1) {\n LABEL_12:\n result = 4294967295LL;\n if (v6 >= v8) return (unsigned int)v8;\n return result;\n }\n LABEL_10:\n result = bio_call_callback(a1, BIO_CB_RETURN | (unsigned int)BIO_CB_GETS,\n a2, (unsigned int)v6, 0LL, 0LL, result, v11);\n if ((int)result <= 0) return result;\n v8 = v11[0];\n goto LABEL_12;\n }\n if (*(uint64_t *)(a1 + 8) || *(uint64_t *)a1) goto LABEL_10;\n }\n return result;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "int BIO_gets(type1 *var1, char *var2, int var3) {\n int var4;\n size_t var5 = 0;\n if ((var1 == NULL) || (var1->field1 == NULL) ||\n (var1->field1->field2 == NULL)) {\n BIOerr(var6, var7);\n return -2;\n }\n if (var3 < 0) {\n BIOerr(var6, var8);\n return 0;\n }\n if (var1->field3 != NULL || var1->field4 != NULL) {\n var4 = (int)bio_call_callback(var1, var9, var2, var3, 0, 0L, 1, NULL);\n if (var4 <= 0) return var4;\n }\n if (!var1->field5) {\n BIOerr(var6, var10);\n return -2;\n }\n var4 = var1->field1->field2(var1, var2, var3);\n if (var4 > 0) {\n var5 = var4;\n var4 = 1;\n }\n if (var1->field3 != NULL || var1->field4 != NULL)\n var4 = (int)bio_call_callback(var1, var9 | var11, var2, var3, 0, 0L, var4,\n &var5);\n if (var4 > 0) {\n if (var5 > (size_t)var3)\n var4 = -1;\n else\n var4 = (int)var5;\n }\n return var4;\n}", "style": "rule"}, "extra_info": {"index": 9857, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_7__ TYPE_2__ ;\ntypedef struct TYPE_6__ TYPE_1__ ;\n\n/* Type definitions */\nstruct TYPE_7__ {int /*<<< orphan*/ * field4; int /*<<< orphan*/ * field3; TYPE_1__* field1; int /*<<< orphan*/ field5; } ;\ntypedef TYPE_2__ type1 ;\nstruct TYPE_6__ {int (* field2 ) (TYPE_2__*,char*,int) ;} ;\n\n/* Variables and functions */\n int /*<<< orphan*/ BIOerr (int /*<<< orphan*/ ,int /*<<< orphan*/ ) ; \n scalar_t__ bio_call_callback (TYPE_2__*,int,char*,int,int /*<<< orphan*/ ,long,int,size_t*) ; \n int stub1 (TYPE_2__*,char*,int) ; \n int /*<<< orphan*/ var10 ; \n int var11 ; \n int /*<<< orphan*/ var6 ; \n int /*<<< orphan*/ var7 ; \n int /*<<< orphan*/ var8 ; \n int var9 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long kvz_get_mvd_coding_cost_cabac(long long a1, uint64_t *a2,\n uint32_t *a3) {\n int v5;\n int v6;\n int v7;\n int x[2];\n int v9[2];\n uint64_t dest[6];\n dest[5] = __readfsqword(40u);\n *(uint64_t *)x = *a2;\n *(uint64_t *)v9 = a2[1];\n v5 = *a2 != 0LL;\n v6 = abs(*a2);\n v7 = abs(v9[0]);\n memcpy(dest, a3, 32uLL);\n LODWORD(dest[0]) = 1;\n dest[3] = dest[2];\n kvz_cabac_encode_bin(dest, *(uint64_t *)x != 0LL);\n kvz_cabac_encode_bin(dest, *(uint64_t *)v9 != 0LL);\n dest[3] = dest[2] + 4LL;\n if (v5) kvz_cabac_encode_bin(dest, v6 > 1);\n if (*(uint64_t *)v9) kvz_cabac_encode_bin(dest, v7 > 1);\n if (v5) {\n if (v6 > 1)\n kvz_cabac_write_ep_ex_golomb(a1, dest, (unsigned int)(v6 - 2), 1LL);\n kvz_cabac_encode_bin_ep(dest, *(uint64_t *)x <= 0LL);\n }\n if (*(uint64_t *)v9) {\n if (v7 > 1)\n kvz_cabac_write_ep_ex_golomb(a1, dest, (unsigned int)(v7 - 2), 1LL);\n kvz_cabac_encode_bin_ep(dest, *(uint64_t *)v9 <= 0LL);\n }\n return (unsigned int)(8 * LODWORD(dest[1]) - HIDWORD(dest[0]) -\n (8 * a3[2] - a3[1]));\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "uint32_t kvz_get_mvd_coding_cost_cabac(type1 *const var1, type2 *var2,\n const type3 *var3) {\n uint32_t var4 = 0;\n const int32_t var5 = var2->field1;\n const int32_t var6 = var2->field2;\n const int8_t var7 = var5 != 0;\n const int8_t var8 = var6 != 0;\n const uint32_t var9 = abs(var5);\n const uint32_t var10 = abs(var6);\n type3 var11;\n memcpy(&var11, var3, sizeof(var12));\n type3 *var13 = &var11;\n var13->field3 = 1;\n var13->field4 = &(var13->field5.field6[0]);\n kvz_cabac_encode_bin((var13), ((var5 != 0)));\n ;\n kvz_cabac_encode_bin((var13), ((var6 != 0)));\n ;\n var13->field4 = &(var13->field5.field6[1]);\n if (var7) {\n kvz_cabac_encode_bin((var13), ((var9 > 1)));\n ;\n }\n if (var8) {\n kvz_cabac_encode_bin((var13), ((var10 > 1)));\n ;\n }\n if (var7) {\n if (var9 > 1) {\n kvz_cabac_write_ep_ex_golomb(var1, var13, var9 - 2, 1);\n }\n kvz_cabac_encode_bin_ep((var13), ((var5 > 0) ? 0 : 1));\n ;\n }\n if (var8) {\n if (var10 > 1) {\n kvz_cabac_write_ep_ex_golomb(var1, var13, var10 - 2, 1);\n }\n kvz_cabac_encode_bin_ep((var13), ((var6 > 0) ? 0 : 1));\n ;\n }\n var4 = ((23 - var13->field7) + (var13->field8 << 3)) -\n ((23 - var3->field7) + (var3->field8 << 3));\n return var4;\n}", "style": "rule"}, "extra_info": {"index": 57170, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_13__ TYPE_3__ ;\ntypedef struct TYPE_12__ TYPE_2__ ;\ntypedef struct TYPE_11__ TYPE_1__ ;\n\n/* Type definitions */\ntypedef int /*<<< orphan*/ var12 ;\ntypedef int uint32_t ;\nstruct TYPE_11__ {int /*<<< orphan*/ * field6; } ;\nstruct TYPE_12__ {int field3; int field7; int field8; TYPE_1__ field5; int /*<<< orphan*/ * field4; } ;\ntypedef TYPE_2__ type3 ;\nstruct TYPE_13__ {scalar_t__ field1; scalar_t__ field2; } ;\ntypedef TYPE_3__ type2 ;\ntypedef int /*<<< orphan*/ type1 ;\ntypedef int int8_t ;\ntypedef scalar_t__ int32_t ;\n\n/* Variables and functions */\n int abs (scalar_t__ const) ; \n int /*<<< orphan*/ kvz_cabac_encode_bin (TYPE_2__*,int) ; \n int /*<<< orphan*/ kvz_cabac_encode_bin_ep (TYPE_2__*,int) ; \n int /*<<< orphan*/ kvz_cabac_write_ep_ex_golomb (int /*<<< orphan*/ * const,TYPE_2__*,int const,int) ; \n int /*<<< orphan*/ memcpy (TYPE_2__*,TYPE_2__ const*,int) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nuint64_t *doconst(uint64_t **a1, long long a2, long long a3, long long a4,\n long long a5, long long a6) {\n long long v6;\n long long v7;\n long long v8;\n uint64_t *result;\n result = *a1;\n if (*a1) assert(*result == 0LL, a2, a3, a4, a5, a6, v6, v7, v8);\n return result;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "void doconst(type1 var1, void *var2) {\n if (var1->field1.field2.field3) {\n assert(var1->field1.field2.field3->field1.field4 == 0);\n func1(var1->field1.field2.field3, var3);\n if (func2(var1->field5) && var1->field5->field5 == var4) {\n unsigned int *var5 = var1->field1.field2.field6.field7;\n int var6 = var1->field5->field8 / var4->field8;\n while (var6-- > 0) {\n type2 var7;\n var7.field1 = *var5++;\n (*var8->field9)(var4->field10, var4->field8, var7);\n }\n } else if (func2(var1->field5))\n (*var8->field11)(var1->field5->field8, var1->field1.field2.field6.field7);\n else\n (*var8->field9)(var1->field5->field10, var1->field5->field8,\n var1->field1.field2.field6);\n var1->field1.field2.field3 = NULL;\n }\n}", "style": "rule"}, "extra_info": {"index": 15452, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_21__ TYPE_7__ ;\ntypedef struct TYPE_20__ TYPE_6__ ;\ntypedef struct TYPE_19__ TYPE_5__ ;\ntypedef struct TYPE_18__ TYPE_4__ ;\ntypedef struct TYPE_17__ TYPE_3__ ;\ntypedef struct TYPE_16__ TYPE_2__ ;\ntypedef struct TYPE_15__ TYPE_1__ ;\ntypedef struct TYPE_14__ TYPE_11__ ;\ntypedef struct TYPE_13__ TYPE_10__ ;\n\n/* Type definitions */\nstruct TYPE_18__ {unsigned int* field7; int /*<<< orphan*/ field1; } ;\ntypedef TYPE_4__ type2 ;\ntypedef TYPE_5__* type1 ;\nstruct TYPE_21__ {int field8; int /*<<< orphan*/ field10; } ;\nstruct TYPE_20__ {int /*<<< orphan*/ (* field9 ) (int /*<<< orphan*/ ,int,TYPE_4__) ;int /*<<< orphan*/ (* field11 ) (int,unsigned int*) ;} ;\nstruct TYPE_16__ {TYPE_11__* field3; TYPE_4__ field6; } ;\nstruct TYPE_17__ {TYPE_2__ field2; } ;\nstruct TYPE_19__ {TYPE_3__ field1; TYPE_10__* field5; } ;\nstruct TYPE_15__ {scalar_t__ field4; } ;\nstruct TYPE_14__ {TYPE_1__ field1; } ;\nstruct TYPE_13__ {int field8; int /*<<< orphan*/ field10; TYPE_7__* field5; } ;\n\n/* Variables and functions */\n int /*<<< orphan*/ assert (int) ; \n int /*<<< orphan*/ func1 (TYPE_11__*,int /*<<< orphan*/ ) ; \n scalar_t__ func2 (TYPE_10__*) ; \n int /*<<< orphan*/ stub1 (int /*<<< orphan*/ ,int,TYPE_4__) ; \n int /*<<< orphan*/ stub2 (int,unsigned int*) ; \n int /*<<< orphan*/ stub3 (int /*<<< orphan*/ ,int,TYPE_4__) ; \n int /*<<< orphan*/ var3 ; \n TYPE_7__* var4 ; \n TYPE_6__* var8 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long nv94_aux(unsigned int *a1, int a2, unsigned int a3, void *a4,\n unsigned int a5) {\n unsigned int v10;\n int v11;\n int j;\n unsigned int v13;\n int i;\n int k;\n unsigned int v16;\n int v17;\n long long v18;\n uint64_t dest[5];\n dest[3] = __readfsqword(40u);\n v18 = nouveau_i2c(a1);\n dest[0] = 0LL;\n dest[1] = 0LL;\n v16 = *a1;\n AUX_DBG(\"%d: 0x%08x %d\\n\", a2, a3, a5);\n v13 = auxch_init(v18, v16);\n if (!v13) {\n if ((nv_rd32(v18, 80 * v16 + 58600) & 268435456) != 0) {\n if ((a2 & 1) == 0) {\n memcpy(dest, a4, a5);\n for (i = 0; i <= 15; i += 4) {\n AUX_DBG(\"wr 0x%08x\\n\", *((uint32_t *)dest + i / 4));\n nv_wr32(v18, i + 80 * v16 + 58560, *((unsigned int *)dest + i / 4));\n }\n }\n v10 = (a5 - 1) | (a2 << 12) | nv_rd32(v18, 80 * v16 + 58596) & 4294840064;\n nv_wr32(v18, 80 * v16 + 58592, a3);\n v13 = -EREMOTEIO;\n for (j = 0; j <= 31; ++j) {\n nv_wr32(v18, 80 * v16 + 58596, v10 | 2147483648);\n nv_wr32(v18, 80 * v16 + 58596, v10);\n if (j) udelay(400LL);\n nv_wr32(v18, 80 * v16 + 58596, v10 | 65536);\n v11 = 1000;\n do {\n v10 = nv_rd32(v18, 80 * v16 + 58596);\n udelay(1LL);\n if (!v11--) {\n AUX_ERR(\"tx req timeout 0x%08x\\n\", v10);\n goto LABEL_24;\n }\n } while ((v10 & 65536) != 0);\n v17 = nv_mask(v18, 80 * v16 + 58600, 0LL, 0LL);\n if ((v17 & 986880) == 0) {\n v13 = 0;\n break;\n }\n AUX_DBG(\"%02d 0x%08x 0x%08x\\n\", j, v10, v17);\n }\n if ((a2 & 1) != 0) {\n for (k = 0; k <= 15; k += 4) {\n *((uint32_t *)dest + k / 4) = nv_rd32(v18, k + 80 * v16 + 58576);\n AUX_DBG(\"rd 0x%08x\\n\", *((uint32_t *)dest + k / 4));\n }\n memcpy(a4, dest, a5);\n }\n } else {\n AUX_DBG(\"sink not detected\\n\");\n v13 = -ENXIO;\n }\n }\nLABEL_24:\n auxch_fini(v18, v16);\n return v13;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "int nv94_aux(struct type1 *var1, type2 var2, type3 var3, type2 *var4,\n type2 var5) {\n struct type4 *var6 = nouveau_i2c(var1);\n struct type5 *var7 = (void *)var1;\n type3 var8, var9, var10, var11;\n type3 var12[4] = {};\n int var13 = var7->field1;\n int var14, var15;\n AUX_DBG(\"%d: 0x%08x %d\\n\", var2, var3, var5);\n var14 = auxch_init(var6, var13);\n if (var14) goto out;\n var9 = nv_rd32(var6, 0x00e4e8 + (var13 * 0x50));\n if (!(var9 & 0x10000000)) {\n AUX_DBG(\"sink not detected\\n\");\n var14 = -var16;\n goto out;\n }\n if (!(var2 & 1)) {\n memcpy(var12, var4, var5);\n for (var15 = 0; var15 < 16; var15 += 4) {\n AUX_DBG(\"wr 0x%08x\\n\", var12[var15 / 4]);\n nv_wr32(var6, 0x00e4c0 + (var13 * 0x50) + var15, var12[var15 / 4]);\n }\n }\n var8 = nv_rd32(var6, 0x00e4e4 + (var13 * 0x50));\n var8 &= ~0x0001f0ff;\n var8 |= var2 << 12;\n var8 |= var5 - 1;\n nv_wr32(var6, 0x00e4e0 + (var13 * 0x50), var3);\n var14 = -var17;\n for (var11 = 0; var11 < 32; var11++) {\n nv_wr32(var6, 0x00e4e4 + (var13 * 0x50), 0x80000000 | var8);\n nv_wr32(var6, 0x00e4e4 + (var13 * 0x50), 0x00000000 | var8);\n if (var11) udelay(400);\n nv_wr32(var6, 0x00e4e4 + (var13 * 0x50), 0x00010000 | var8);\n var10 = 1000;\n do {\n var8 = nv_rd32(var6, 0x00e4e4 + (var13 * 0x50));\n udelay(1);\n if (!var10--) {\n AUX_ERR(\"tx req timeout 0x%08x\\n\", var8);\n goto out;\n }\n } while (var8 & 0x00010000);\n var9 = nv_mask(var6, 0x00e4e8 + (var13 * 0x50), 0, 0);\n if (!(var9 & 0x000f0f00)) {\n var14 = 0;\n break;\n }\n AUX_DBG(\"%02d 0x%08x 0x%08x\\n\", var11, var8, var9);\n }\n if (var2 & 1) {\n for (var15 = 0; var15 < 16; var15 += 4) {\n var12[var15 / 4] = nv_rd32(var6, 0x00e4d0 + (var13 * 0x50) + var15);\n AUX_DBG(\"rd 0x%08x\\n\", var12[var15 / 4]);\n }\n memcpy(var4, var12, var5);\n }\nout:\n auxch_fini(var6, var13);\n return var14;\n}", "style": "rule"}, "extra_info": {"index": 104428, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\ntypedef int type3 ;\ntypedef int type2 ;\nstruct type5 {int field1; } ;\nstruct type4 {int dummy; } ;\nstruct type1 {int dummy; } ;\n\n/* Variables and functions */\n int /*<<< orphan*/ AUX_DBG (char*,...) ; \n int /*<<< orphan*/ AUX_ERR (char*,int) ; \n int /*<<< orphan*/ auxch_fini (struct type4*,int) ; \n int auxch_init (struct type4*,int) ; \n int /*<<< orphan*/ memcpy (int*,int*,int) ; \n struct type4* nouveau_i2c (struct type1*) ; \n int nv_mask (struct type4*,int,int /*<<< orphan*/ ,int /*<<< orphan*/ ) ; \n int nv_rd32 (struct type4*,int) ; \n int /*<<< orphan*/ nv_wr32 (struct type4*,int,int) ; \n int /*<<< orphan*/ udelay (int) ; \n int var16 ; \n int var17 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long sig_handle(int a1, long long a2) {\n uint64_t v3[2];\n uint64_t v4[2];\n v4[1] = __readfsqword(40u);\n v3[0] = a2;\n sigemptyset((sigset_t *)v4);\n v3[1] = 0LL;\n if (sigaction(a1, (const struct sigaction *)v3, 0LL) == -1)\n return 4294967295LL;\n else\n return 0LL;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "static int sig_handle(int var1, void (*var2)(int)) {\n struct type1 var3;\n var3.field1 = var2;\n sigemptyset(&var3.field2);\n var3.field3 = 0;\n if (sigaction(var1, &var3, NULL) == -1) {\n return -1;\n }\n return 0;\n}", "style": "rule"}, "extra_info": {"index": 90536, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\nstruct type1 {void (* field1 ) (int) ;scalar_t__ field3; int /*<<< orphan*/ field2; } ;\n\n/* Variables and functions */\n int sigaction (int,struct type1*,int /*<<< orphan*/ *) ; \n int /*<<< orphan*/ sigemptyset (int /*<<< orphan*/ *) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nssize_t _stdio_read(long long a1, char *a2, ssize_t a3) {\n unsigned int v6;\n void *v7;\n int v8;\n ssize_t result;\n unsigned int iov_len;\n char *v11;\n bool v12;\n struct iovec v13;\n void *v14;\n unsigned int v15;\n unsigned long long v16;\n v6 = *(uint64_t *)a1;\n v16 = __readfsqword(40u);\n v13.iov_base = a2;\n v7 = *(void **)(a1 + 8);\n v15 = v6;\n v8 = *(uint32_t *)(a1 + 40);\n v14 = v7;\n v13.iov_len = (v6 == 0) + a3 - 1;\n if ((v6 == 0) + a3 != 1) {\n result = readv(v8, &v13, 2);\n if (result > 0) goto LABEL_3;\n LABEL_8:\n *(uint32_t *)(a1 + 16) |= result == 0 ? 16 : 32;\n return 0LL;\n }\n result = read(v8, v7, v6);\n if (result <= 0) goto LABEL_8;\nLABEL_3:\n iov_len = v13.iov_len;\n if ((long long)v13.iov_len < result) {\n v11 = *(char **)(a1 + 8);\n v12 = *(uint64_t *)a1 == 0LL;\n *(uint64_t *)(a1 + 24) = v11;\n *(uint64_t *)(a1 + 32) = &v11[result - iov_len];\n result = a3;\n if (!v12) {\n *(uint64_t *)(a1 + 24) = v11 + 1;\n a2[a3 - 1] = *v11;\n }\n }\n return result;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "size_t func1(type1 *var1, unsigned char *var2, size_t var3) {\n struct type2 var4[2] = {{.field1 = var2, .field2 = var3 - !!var1->field3},\n {.field1 = var1->field4, .field2 = var1->field3}};\n ssize_t var5;\n var5 = var4[0].field2 ? readv(var1->field5, var4, 2)\n : read(var1->field5, var4[1].field1, var4[1].field2);\n if (var5 <= 0) {\n var1->field6 |= var5 ? 32 : 16;\n return 0;\n }\n if (var5 <= var4[0].field2) return var5;\n var5 -= var4[0].field2;\n var1->field7 = var1->field4;\n var1->field8 = var1->field4 + var5;\n if (var1->field3) var2[var3 - 1] = *var1->field7++;\n return var3;\n}", "style": "rule"}, "extra_info": {"index": 74134, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_3__ TYPE_1__ ;\n\n/* Type definitions */\nstruct TYPE_3__ {scalar_t__ field3; unsigned char* field4; int field6; unsigned char* field7; scalar_t__ field8; int /*<<< orphan*/ field5; } ;\ntypedef TYPE_1__ type1 ;\nstruct type2 {unsigned char* field1; scalar_t__ field2; } ;\ntypedef scalar_t__ ssize_t ;\n\n/* Variables and functions */\n scalar_t__ read (int /*<<< orphan*/ ,unsigned char*,scalar_t__) ; \n scalar_t__ readv (int /*<<< orphan*/ ,struct type2*,int) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long instr_shlqby(uint64_t *a1, long long a2, long long a3, long long a4) {\n int v6;\n int v7;\n int v8;\n int v9;\n int v10;\n int v11;\n int v12;\n int v13;\n int v14;\n int v15;\n int v16;\n int v17;\n int v18;\n int v19;\n int v20;\n int v21;\n bool v22;\n int v23;\n uint32_t v25[16];\n uint32_t v26[16];\n uint8_t v27[72];\n unsigned long long v28;\n v28 = __readfsqword(40u);\n reg_to_byte(a1, v25, a2);\n reg_to_byte(a1, v26, a3);\n reg_to_byte(a1, v27, a4);\n v6 = **(uint32_t **)(*a1 + 8 * a4) & 31;\n if ((**(uint32_t **)(*a1 + 8 * a4) & 16) == 0) {\n v7 = v6 + 1;\n v25[0] = v26[v6];\n v8 = 0;\n if (v6 + 1 > 15) goto LABEL_4;\n goto LABEL_3;\n }\n v7 = v6 + 1;\n v25[0] = 0;\n v8 = 0;\n if (v6 + 1 <= 15)\n LABEL_3:\n v8 = v26[v7];\nLABEL_4:\n v25[1] = v8;\n v9 = 0;\n if (v6 + 2 <= 15) v9 = v26[v6 + 2];\n v25[2] = v9;\n v10 = 0;\n if (v6 + 3 <= 15) v10 = v26[v6 + 3];\n v25[3] = v10;\n v11 = 0;\n if (v6 + 4 <= 15) v11 = v26[v6 + 4];\n v25[4] = v11;\n v12 = 0;\n if (v6 + 5 <= 15) v12 = v26[v6 + 5];\n v25[5] = v12;\n v13 = 0;\n if (v6 + 6 <= 15) v13 = v26[v6 + 6];\n v25[6] = v13;\n v14 = 0;\n if (v6 + 7 <= 15) v14 = v26[v6 + 7];\n v25[7] = v14;\n v15 = 0;\n if (v6 + 8 <= 15) v15 = v26[v6 + 8];\n v25[8] = v15;\n v16 = 0;\n if (v6 + 9 <= 15) v16 = v26[v6 + 9];\n v25[9] = v16;\n v17 = 0;\n if (v6 + 10 <= 15) v17 = v26[v6 + 10];\n v25[10] = v17;\n v18 = 0;\n if (v6 + 11 <= 15) v18 = v26[v6 + 11];\n v25[11] = v18;\n v19 = 0;\n if (v6 + 12 <= 15) v19 = v26[v6 + 12];\n v25[12] = v19;\n v20 = 0;\n if (v6 + 13 <= 15) v20 = v26[v6 + 13];\n v25[13] = v20;\n v21 = 0;\n if (v6 + 14 <= 15) v21 = v26[v6 + 14];\n v22 = v6 == 0;\n v23 = 0;\n if (v22) v23 = v26[15];\n v25[14] = v21;\n v25[15] = v23;\n ((void (*)(uint64_t *, long long, uint32_t *))byte_to_reg)(a1, a2, v25);\n return 0LL;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "int instr_shlqby(type1 *var1, uint32_t var2, uint32_t var3, uint32_t var4) {\n uint8_t var5[16];\n uint8_t var6[16];\n uint8_t var7[16];\n int var8 = 0;\n reg_to_byte(var1, var5, var2);\n reg_to_byte(var1, var6, var3);\n reg_to_byte(var1, var7, var4);\n (void)*var1;\n (void)var2;\n (void)var3;\n (void)var4;\n ;\n {\n int var9;\n int var10 = var1->field1[var4][0] & 0x1f;\n for (var9 = 0; var9 < 16; ++var9)\n var5[var9] = (var9 + var10) < 16 ? var6[var9 + var10] : 0;\n func1(var1, var2, var5);\n }\n return var8;\n}", "style": "rule"}, "extra_info": {"index": 15507, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_5__ TYPE_1__ ;\n\n/* Type definitions */\ntypedef int /*<<< orphan*/ uint8_t ;\ntypedef size_t uint32_t ;\nstruct TYPE_5__ {int** field1; } ;\ntypedef TYPE_1__ type1 ;\n\n/* Variables and functions */\n int /*<<< orphan*/ func1 (TYPE_1__*,size_t,int /*<<< orphan*/ *) ; \n int /*<<< orphan*/ reg_to_byte (TYPE_1__*,int /*<<< orphan*/ *,size_t) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nunsigned long long test() {\n int v0;\n const char *v1;\n long long v2;\n int v3;\n int i;\n const char *v5;\n long long v6;\n int v8;\n int v9;\n const char *v10;\n unsigned int n;\n unsigned int v12;\n unsigned int v13;\n unsigned int v14;\n char s[32];\n char s2[24];\n unsigned long long v17;\n v0 = 0;\n v17 = __readfsqword(40u);\n init_db(&v12, \"localhost\", 8020LL, \"/l0/giga_ldb/l0/\");\n strcpy(s2, \"hello world\");\n v10 = 0LL;\n v8 = 0;\n do {\n sprintf(s, \"%010d\", v0);\n v1 = (const char *)leveldb_get(v13, v12, s, 20LL, &n, &v10);\n if (v10) goto LABEL_2;\n LODWORD(v2) = strncmp(v1, s2, n);\n if (v2 || !n) {\n printf(\"key=%s\\n\", s);\n LABEL_2:\n ++v8;\n }\n ++v0;\n } while (v0 != 1000);\n v3 = 0;\n printf(\"Error count = %d\\n\", v8);\n do {\n sprintf(s, \"%010d\", v3);\n leveldb_put(v13, v14, s, 20LL, s2, 20LL, &v10);\n if (v10) printf(\"Error: %s\\n\", v10);\n ++v3;\n } while (v3 != 1000);\n v9 = 0;\n for (i = 0; i != 1000; ++i) {\n while (1) {\n sprintf(s, \"%010d\", i);\n v5 = (const char *)leveldb_get(v13, v12, s, 20LL, &n, &v10);\n if (!v10) {\n LODWORD(v6) = strncmp(v5, s2, n);\n if (!v6) {\n if (n) break;\n }\n }\n ++i;\n ++v9;\n if (i == 1000) goto LABEL_18;\n }\n }\nLABEL_18:\n printf(\"Error count = %d\\n\", v9);\n close_db(&v12);\n return v17 - __readfsqword(40u);\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "void test() {\n struct type1 var1;\n init_db(&var1, \"localhost\", 8020, \"/l0/giga_ldb/l0/\");\n char var2[20];\n char var3[20];\n sprintf(var3, \"hello world\");\n char* var4 = NULL;\n int var5;\n int var6 = 1000;\n int var7 = 0;\n for (var5 = 0; var5 < var6; ++var5) {\n sprintf(var2, \"%010d\", var5);\n size_t var8;\n char* var9 = leveldb_get(var1.field1, var1.field2, var2, 20, &var8, &var4);\n if (var4 != NULL) {\n var7++;\n } else if (strncmp(var9, var3, var8) != 0 || var8 == 0) {\n printf(\"key=%s\\n\", var2);\n var7++;\n }\n }\n printf(\"Error count = %d\\n\", var7);\n for (var5 = 0; var5 < var6; ++var5) {\n sprintf(var2, \"%010d\", var5);\n leveldb_put(var1.field1, var1.field3, var2, 20, var3, 20, &var4);\n if (var4 != NULL) {\n printf(\"Error: %s\\n\", var4);\n }\n }\n var7 = 0;\n for (var5 = 0; var5 < var6; ++var5) {\n sprintf(var2, \"%010d\", var5);\n size_t var8;\n char* var9 = leveldb_get(var1.field1, var1.field2, var2, 20, &var8, &var4);\n if (var4 != NULL) {\n var7++;\n } else if (strncmp(var9, var3, var8) != 0 || var8 == 0) {\n var7++;\n }\n }\n printf(\"Error count = %d\\n\", var7);\n close_db(&var1);\n}", "style": "rule"}, "extra_info": {"index": 3180, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\nstruct type1 {int /*<<< orphan*/ field2; int /*<<< orphan*/ field1; int /*<<< orphan*/ field3; } ;\n\n/* Variables and functions */\n int /*<<< orphan*/ close_db (struct type1*) ; \n int /*<<< orphan*/ init_db (struct type1*,char*,int,char*) ; \n char* leveldb_get (int /*<<< orphan*/ ,int /*<<< orphan*/ ,char*,int,size_t*,char**) ; \n int /*<<< orphan*/ leveldb_put (int /*<<< orphan*/ ,int /*<<< orphan*/ ,char*,int,char*,int,char**) ; \n int /*<<< orphan*/ printf (char*,...) ; \n int /*<<< orphan*/ sprintf (char*,char*,...) ; \n scalar_t__ strncmp (char*,char*,size_t) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long lgdt3306a_power(long long a1, unsigned int a2) {\n unsigned int v3;\n dbg_info(\"(%d)\\n\", a2);\n if (a2) {\n v3 = lgdt3306a_set_reg_bit(a1, 0LL, 7LL, 1LL);\n if (!lg_chkerr(v3)) {\n v3 = lgdt3306a_set_reg_bit(a1, 0LL, 0LL, 1LL);\n lg_chkerr(v3);\n }\n } else {\n v3 = lgdt3306a_set_reg_bit(a1, 0LL, 7LL, 0LL);\n if (!lg_chkerr(v3)) {\n v3 = lgdt3306a_set_reg_bit(a1, 0LL, 0LL, 0LL);\n lg_chkerr(v3);\n }\n }\n return v3;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "static int lgdt3306a_power(struct type1 *var1, int var2) {\n int var3;\n dbg_info(\"(%d)\\n\", var2);\n if (var2 == 0) {\n var3 = lgdt3306a_set_reg_bit(var1, 0x0000, 7, 0);\n if (lg_chkerr(var3)) goto fail;\n var3 = lgdt3306a_set_reg_bit(var1, 0x0000, 0, 0);\n if (lg_chkerr(var3)) goto fail;\n } else {\n var3 = lgdt3306a_set_reg_bit(var1, 0x0000, 7, 1);\n if (lg_chkerr(var3)) goto fail;\n var3 = lgdt3306a_set_reg_bit(var1, 0x0000, 0, 1);\n if (lg_chkerr(var3)) goto fail;\n }\n#ifdef var4\n func1(var1);\n#endif\nfail:\n return var3;\n}", "style": "rule"}, "extra_info": {"index": 60809, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\nstruct type1 {int dummy; } ;\n\n/* Variables and functions */\n int /*<<< orphan*/ dbg_info (char*,int) ; \n int /*<<< orphan*/ func1 (struct type1*) ; \n scalar_t__ lg_chkerr (int) ; \n int lgdt3306a_set_reg_bit (struct type1*,int,int,int) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long StartTasks(uint64_t *a1, unsigned int *a2) {\n unsigned int v3;\n void *v4;\n unsigned int v5;\n void *v6;\n uint64_t *v7;\n long long v8;\n long long v9;\n unsigned int started;\n long long v11;\n unsigned int v12;\n uint64_t v14[7];\n v3 = *a2;\n v14[1] = __readfsqword(40u);\n v4 = calloc(v3, 8uLL);\n v5 = *a2;\n v14[0] = v4;\n v6 = v4;\n if (v5) {\n v7 = v4;\n v8 = 0LL;\n do {\n ++v7;\n v9 = v8 + *a1;\n v8 += 4LL;\n *(v7 - 1) = v9;\n } while (4 * v5 != v8);\n }\n started = StartTasksByPointers(v14, a2);\n v11 = v14[0];\n v12 = started;\n if (v14[0]) {\n if (v14[0] < (unsigned long long)v6 + 8 * v5)\n v11 = *(uint64_t *)v14[0];\n else\n v11 = 0LL;\n }\n *a1 = v11;\n free(v6);\n return v12;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "static int func1(type1** var1, size_t* var2) {\n type1** var3 = (type1**)calloc(*var2, sizeof(type1*));\n for (size_t var4 = 0; var4 < *var2; ++var4) {\n var3[var4] = *var1 + var4;\n }\n type1** var5 = var3;\n size_t var6 = *var2;\n int var7 = func2(&var3, var2);\n if (!var3 || var3 >= var5 + var6) {\n *var1 = NULL;\n } else {\n *var1 = *var3;\n }\n free(var5);\n return var7;\n}", "style": "rule"}, "extra_info": {"index": 44857, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\ntypedef int /*<<< orphan*/ type1 ;\n\n/* Variables and functions */\n scalar_t__ calloc (size_t,int) ; \n int /*<<< orphan*/ free (int /*<<< orphan*/ **) ; \n int func2 (int /*<<< orphan*/ ***,size_t*) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nint main(int argc, const char **argv, const char **envp) {\n void *v3;\n int v5;\n int v6;\n int i;\n int j;\n int fd;\n int v10;\n int v11;\n int v12;\n void *buf;\n void *v14;\n unsigned long long v15;\n v15 = __readfsqword(40u);\n fd = open(\"foo\", O_CREAT | O_TRUNC, 438LL);\n close(fd);\n v3 = malloc(16uLL);\n addStuff(v3);\n puts(\"Printing my schedule:\");\n v10 = open(\"foo\", O_RDONLY);\n buf = malloc(16uLL);\n for (i = 1; i <= 10; ++i) {\n read(v10, buf, 16uLL);\n printf(\"Period %d: %s\", i, *(const char **)buf);\n }\n close(v10);\n putchar(10);\n printf(\"Period to retrieve: \");\n scanf(\"%d\", &v5);\n v11 = open(\"foo\", O_RDONLY);\n if (v5 > 0 && v5 <= 10) {\n lseek(v11, (unsigned int)(16 * (v5 - 1)), SEEK_SET);\n read(v11, buf, 16uLL);\n printf(\"Period %d: %s\", *((uint32_t *)buf + 2), *(const char **)buf);\n }\n putchar(10);\n printf(\"Period to turn into a free: \");\n scanf(\"%d\", &v6);\n v12 = open(\"foo\", O_RDWR);\n if (v6 > 0 && v6 <= 10) {\n lseek(v12, (unsigned int)(16 * (v6 - 1)), SEEK_SET);\n v14 = malloc(16uLL);\n strcpy(*(char **)v14, \"Free\\n\");\n *((uint32_t *)v14 + 2) = v6;\n write(v12, v14, 16uLL);\n }\n lseek(v12, 0LL, SEEK_SET);\n for (j = 1; j <= 10; ++j) {\n read(v12, buf, 16uLL);\n printf(\"Period %d: %s\", j, *(const char **)buf);\n }\n putchar(10);\n close(v12);\n free(buf);\n return 0;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "int main() {\n int var1 = open(\"foo\", var2 | var3, 0666);\n close(var1);\n type1* var4 = malloc(sizeof(var5));\n addStuff(var4);\n printf(\"Printing my schedule:\\n\");\n int var6 = open(\"foo\", var7);\n var4 = malloc(sizeof(var5));\n int var8 = 1;\n while (var8 < 11) {\n read(var6, var4, sizeof(var5));\n printf(\"Period %d: %s\", var8, var4->field1);\n var8++;\n }\n close(var6);\n printf(\"\\n\");\n int var9;\n printf(\"Period to retrieve: \");\n scanf(\"%d\", &var9);\n int var10 = open(\"foo\", var7);\n if (var9 > 0 && var9 < 11) {\n lseek(var10, (var9 - 1) * sizeof(var5), var11);\n read(var10, var4, sizeof(var5));\n printf(\"Period %d: %s\", var4->field2, var4->field1);\n }\n printf(\"\\n\");\n int var12;\n printf(\"Period to turn into a free: \");\n scanf(\"%d\", &var12);\n int var13 = open(\"foo\", var14);\n if (var12 > 0 && var12 < 11) {\n lseek(var13, (var12 - 1) * sizeof(var5), var11);\n type1* var15 = malloc(sizeof(var5));\n strcpy(var15->field1, \"Free\\n\");\n var15->field2 = var12;\n write(var13, var15, sizeof(var5));\n }\n lseek(var13, 0, var11);\n int var16 = 1;\n while (var16 < 11) {\n read(var13, var4, sizeof(var5));\n printf(\"Period %d: %s\", var16, var4->field1);\n var16++;\n }\n printf(\"\\n\");\n close(var13);\n free(var4);\n}", "style": "rule"}, "extra_info": {"index": 40698, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_7__ TYPE_1__ ;\n\n/* Type definitions */\ntypedef int /*<<< orphan*/ var5 ;\nstruct TYPE_7__ {char* field1; int field2; } ;\ntypedef TYPE_1__ type1 ;\n\n/* Variables and functions */\n int /*<<< orphan*/ addStuff (TYPE_1__*) ; \n int /*<<< orphan*/ close (int) ; \n int /*<<< orphan*/ free (TYPE_1__*) ; \n int /*<<< orphan*/ lseek (int,int,int /*<<< orphan*/ ) ; \n TYPE_1__* malloc (int) ; \n int open (char*,int,...) ; \n int /*<<< orphan*/ printf (char*,...) ; \n int /*<<< orphan*/ read (int,TYPE_1__*,int) ; \n int /*<<< orphan*/ scanf (char*,int*) ; \n int /*<<< orphan*/ strcpy (char*,char*) ; \n int /*<<< orphan*/ var11 ; \n int /*<<< orphan*/ var14 ; \n int var2 ; \n int var3 ; \n int /*<<< orphan*/ var7 ; \n int /*<<< orphan*/ write (int,TYPE_1__*,int) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nvoid *ms_copy_int32(int a1, const void *a2) {\n void *dest;\n dest = malloc((unsigned int)(4 * a1));\n memcpy(dest, a2, 4LL * a1);\n return dest;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "int32_t* ms_copy_int32(uint32_t var1, const int32_t* var2) {\n size_t var3 = var1 * sizeof(int32_t);\n int32_t* var4 = (int32_t*)malloc(var1 * sizeof(int32_t));\n memcpy(var4, var2, var3);\n return var4;\n}", "style": "rule"}, "extra_info": {"index": 13865, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\ntypedef int uint32_t ;\ntypedef int /*<<< orphan*/ int32_t ;\n\n/* Variables and functions */\n scalar_t__ malloc (int) ; \n int /*<<< orphan*/ memcpy (int /*<<< orphan*/ *,int /*<<< orphan*/ const*,size_t) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nvoid maybe_change_configuration(long long a1) {\n int v2;\n long long v3;\n long long v4;\n long long v5;\n long long v6;\n long long v7;\n long long v8;\n long long v9;\n long long *v10;\n long long v11;\n if (*(uint64_t *)a1) {\n v2 = *(uint32_t *)(a1 + 8);\n v3 = *(uint64_t *)(a1 + 32);\n if (v2 <= 0) {\n *(uint32_t *)(a1 + 24) = 0;\n } else {\n v4 = *(uint64_t *)(a1 + 16);\n v5 = 0LL;\n do {\n v6 = *(uint64_t *)(v4 + 8 * v5);\n if (v6 != PMC_NO_INDEX && v6 != **(uint64_t **)(v3 + 8 * v5)) {\n alpha_perf_event_update(*(uint64_t *)(v3 + 8 * v5),\n *(uint64_t *)(v3 + 8 * v5), v6, 0LL);\n v4 = *(uint64_t *)(a1 + 16);\n v2 = *(uint32_t *)(a1 + 8);\n v3 = *(uint64_t *)(a1 + 32);\n *(uint64_t *)(v4 + 8 * v5) = PMC_NO_INDEX;\n }\n ++v5;\n } while (v2 > (int)v5);\n *(uint32_t *)(a1 + 24) = 0;\n if (v2 > 0) {\n v7 = v4;\n v8 = 0LL;\n do {\n v9 = *(uint64_t *)(v7 + 8 * v8);\n v10 = *(long long **)(v3 + 8 * v8);\n if (v9 == PMC_NO_INDEX) {\n v11 = *v10;\n alpha_perf_event_set_period(*(uint64_t *)(v3 + 8 * v8),\n *(uint64_t *)(v3 + 8 * v8),\n (unsigned int)*v10);\n v7 = *(uint64_t *)(a1 + 16);\n LOBYTE(v9) = v11;\n v2 = *(uint32_t *)(a1 + 8);\n v3 = *(uint64_t *)(a1 + 32);\n *(uint64_t *)(v7 + 8 * v8) = (int)v11;\n }\n if ((PERF_HES_STOPPED & (uint32_t)v10[1]) == 0)\n *(uint32_t *)(a1 + 24) |= 1 << v9;\n ++v8;\n } while (v2 > (int)v8);\n }\n }\n *(uint32_t *)(a1 + 40) = *(uint32_t *)(*(uint64_t *)v3 + 12LL);\n }\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "static void maybe_change_configuration(struct type1 *var1) {\n int var2;\n if (var1->field1 == 0) return;\n for (var2 = 0; var2 < var1->field2; var2++) {\n struct type2 *var3 = var1->field3[var2];\n if (var1->field4[var2] != var4 &&\n var1->field4[var2] != var3->field5.field6) {\n alpha_perf_event_update(var3, &var3->field5, var1->field4[var2], 0);\n var1->field4[var2] = var4;\n }\n }\n var1->field7 = 0;\n for (var2 = 0; var2 < var1->field2; var2++) {\n struct type2 *var3 = var1->field3[var2];\n struct type3 *var5 = &var3->field5;\n int var6 = var5->field6;\n if (var1->field4[var2] == var4) {\n alpha_perf_event_set_period(var3, var5, var6);\n var1->field4[var2] = var6;\n }\n if (!(var5->field8 & var7)) var1->field7 |= (1 << var1->field4[var2]);\n }\n var1->field9 = var1->field3[0]->field5.field10;\n}", "style": "rule"}, "extra_info": {"index": 8000, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\nstruct type3 {scalar_t__ field6; int field8; int /*<<< orphan*/ field10; } ;\nstruct type2 {struct type3 field5; } ;\nstruct type1 {scalar_t__ field1; int field2; scalar_t__* field4; int field7; struct type2** field3; int /*<<< orphan*/ field9; } ;\n\n/* Variables and functions */\n int /*<<< orphan*/ alpha_perf_event_set_period (struct type2*,struct type3*,int) ; \n int /*<<< orphan*/ alpha_perf_event_update (struct type2*,struct type3*,scalar_t__,int /*<<< orphan*/ ) ; \n scalar_t__ var4 ; \n int var7 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nuint64_t *split(char *a1, char *a2) {\n unsigned long long v2;\n void *v3;\n void **v4;\n uint64_t v6[2];\n char *delim;\n char *s;\n unsigned int n;\n unsigned int n_4;\n uint64_t *inited;\n char *i;\n long long v13;\n void *dest;\n unsigned long long v15;\n s = a1;\n delim = a2;\n v15 = __readfsqword(40u);\n n = strlen(a1) + 1;\n v13 = n - 1LL;\n v6[0] = n;\n v6[1] = 0LL;\n v2 = 16 * (((unsigned long long)n + 15) / 16);\n while (v6 != (uint64_t *)((char *)v6 - (v2 & 18446744073709547520LL)))\n ;\n v3 = alloca(v2 & 4095);\n if ((v2 & 4095) != 0)\n *(uint64_t *)((char *)&v6[-1] + (v2 & 4095)) =\n *(uint64_t *)((char *)&v6[-1] + (v2 & 4095));\n dest = v6;\n i = 0LL;\n inited = (uint64_t *)initSplitString(a1, a2);\n if (!inited) return 0LL;\n memcpy(dest, s, n);\n for (i = strtok((char *)dest, delim); i; i = strtok(0LL, delim)) {\n n_4 = strlen(i) + 1;\n v4 = (void **)(*inited + 8LL * inited[1]);\n *v4 = malloc(n_4);\n if (!*(uint64_t *)(*inited + 8LL * inited[1])) {\n splitFree(&inited);\n return 0LL;\n }\n memcpy(*(void **)(*inited + 8LL * inited[1]++), i, n_4);\n adjustSize(inited);\n }\n return inited;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "struct type1 *split(const char *var1, const char *var2) {\n unsigned var3 = strlen(var1) + 1;\n char var4[var3];\n char *var5 = NULL;\n struct type1 *var6 = initSplitString();\n if (var6 == NULL) {\n goto error;\n }\n memcpy(var4, var1, var3);\n var5 = strtok(var4, var2);\n while (var5 != NULL) {\n int var7 = strlen(var5) + 1;\n var6->field1[var6->field2] = malloc(var7);\n if (var6->field1[var6->field2]) {\n memcpy(var6->field1[var6->field2], var5, var7);\n } else {\n splitFree(&var6);\n goto error;\n }\n var6->field2++;\n adjustSize(var6);\n var5 = strtok(NULL, var2);\n }\n return var6;\nerror:\n return NULL;\n}", "style": "rule"}, "extra_info": {"index": 36112, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\nstruct type1 {char** field1; size_t field2; } ;\n\n/* Variables and functions */\n int /*<<< orphan*/ adjustSize (struct type1*) ; \n struct type1* initSplitString () ; \n char* malloc (int) ; \n int /*<<< orphan*/ memcpy (char*,char const*,int) ; \n int /*<<< orphan*/ splitFree (struct type1**) ; \n int strlen (char const*) ; \n char* strtok (char*,char const*) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nint main(int argc, const char **argv, const char **envp) {\n long long v3;\n __m128i *i;\n char *v5;\n char v6;\n signed int v7;\n long long v8;\n signed int v9;\n __m128i *v10;\n __m128i *v11;\n long long v12;\n __m128i si128;\n const __m128i *v14;\n __m128i v15;\n __m128i v16;\n unsigned int v17;\n long long v18;\n unsigned int v19;\n signed int v20;\n int v21;\n signed int v22;\n short *v23;\n int v24;\n long long v26;\n short v27;\n v3 = 0LL;\n for (i = (__m128i *)malloc(1uLL);;\n i = (__m128i *)realloc(i, (unsigned int)(v3 + 1))) {\n v5 = &i->m128i_i8[v3++];\n v6 = getchar();\n *v5 = v6;\n if (v6 == 10) break;\n }\n v7 = strlen(i->m128i_i8);\n v8 = v7;\n v9 = v7;\n v10 = (__m128i *)malloc((unsigned int)(2 * v7));\n v11 = v10;\n if ((int)v8 <= 0) {\n v21 = 0;\n } else {\n v12 = (unsigned int)(v8 - 1);\n if ((v10 >= (__m128i *)&i->m128i_i8[v8] ||\n i >= (__m128i *)((char *)v10 + 2 * v8)) &&\n (unsigned int)v12 > 14) {\n si128 = _mm_load_si128((const __m128i *)&LC0);\n v14 = i;\n do {\n v15 = _mm_loadu_si128(v14++);\n v10 += 2;\n v16 = _mm_cmpgt_epi8((__m128i)0LL, v15);\n v10[-2] = _mm_add_epi16(_mm_unpacklo_epi8(v15, v16), si128);\n v10[-1] = _mm_add_epi16(_mm_unpackhi_epi8(v15, v16), si128);\n } while (v14 != &i[(unsigned int)v9 >> 4]);\n v17 = v9 & 4294967280;\n if ((v9 & 15) != 0) {\n v18 = v17;\n v11->m128i_i16[v18] = i->m128i_i8[v17] - 48;\n if (v9 > (int)(v17 + 1)) {\n v11->m128i_i16[v18 + 1] = i->m128i_i8[v17 + 1] - 48;\n if (v9 > (int)(v17 + 2)) {\n v11->m128i_i16[v18 + 2] = i->m128i_i8[v17 + 2] - 48;\n if (v9 > (int)(v17 + 3)) {\n v11->m128i_i16[v18 + 3] = i->m128i_i8[v17 + 3] - 48;\n if (v9 > (int)(v17 + 4)) {\n v11->m128i_i16[v18 + 4] = i->m128i_i8[v17 + 4] - 48;\n if (v9 > (int)(v17 + 5)) {\n v11->m128i_i16[v18 + 5] = i->m128i_i8[v17 + 5] - 48;\n if (v9 > (int)(v17 + 6)) {\n v11->m128i_i16[v18 + 6] = i->m128i_i8[v17 + 6] - 48;\n if (v9 > (int)(v17 + 7)) {\n v11->m128i_i16[v18 + 7] = i->m128i_i8[v17 + 7] - 48;\n if (v9 > (int)(v17 + 8)) {\n v11[1].m128i_i16[v18] = i->m128i_i8[v17 + 8] - 48;\n if (v9 > (int)(v17 + 9)) {\n v11[1].m128i_i16[v18 + 1] = i->m128i_i8[v17 + 9] - 48;\n if (v9 > (int)(v17 + 10)) {\n v11[1].m128i_i16[v18 + 2] =\n i->m128i_i8[v17 + 10] - 48;\n if (v9 > (int)(v17 + 11)) {\n v11[1].m128i_i16[v18 + 3] =\n i->m128i_i8[v17 + 11] - 48;\n if (v9 > (int)(v17 + 12)) {\n v11[1].m128i_i16[v18 + 4] =\n i->m128i_i8[v17 + 12] - 48;\n v19 = v17 + 13;\n if (v9 > (int)(v17 + 13)) {\n v20 = v17 + 14;\n v11[1].m128i_i16[v18 + 5] =\n i->m128i_i8[v19] - 48;\n if (v9 > v20)\n v11[1].m128i_i16[v18 + 6] =\n i->m128i_i8[v20] - 48;\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n } else {\n v26 = (long long)v10->m128i_i64 + 2 * v12 + 2;\n do {\n v27 = i->m128i_i8[0];\n v10 = (__m128i *)((char *)v10 + 2);\n i = (__m128i *)((char *)i + 1);\n v10[-1].m128i_i16[7] = v27 - 48;\n } while (v10 != (__m128i *)v26);\n }\n v21 = 0;\n v22 = 0;\n do {\n v23 = &v11->m128i_i16[v22];\n do {\n v24 = *v23;\n ++v22;\n ++v23;\n v21 = v24 + 10 * v21;\n } while (v9 > v22 && v21 <= 299);\n v21 %= 300;\n } while (v9 > v22);\n }\n printf(\"remainder is = %d\\n\", v21);\n return 0;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "int main(void) {\n int var1 = 0;\n char *var2 = (char *)malloc(sizeof(char));\n while ((var2[var1] = getchar()) != '\\n') {\n var2 = (char *)realloc(var2, var1 + 2);\n var1++;\n }\n short int *var3;\n int var4;\n int var5 = 0;\n var4 = strlen(var2);\n var3 = (short int *)malloc(sizeof(short int) * var4);\n for (var1 = 0; var1 < var4; var1++) {\n var3[var1] = var2[var1] - '0';\n }\n var1 = 0;\n while (var1 < var4) {\n while (var1 < var4 && var5 < 300) {\n var5 = var5 * 10 + var3[var1];\n var1++;\n }\n var5 = var5 % 300;\n }\n printf(\"remainder is = %d\\n\", var5);\n}", "style": "rule"}, "extra_info": {"index": 91550, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\n\n/* Variables and functions */\n char getchar () ; \n scalar_t__ malloc (int) ; \n int /*<<< orphan*/ printf (char*,int) ; \n scalar_t__ realloc (char*,int) ; \n int strlen (char*) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long pcap_tstamp_type_name_to_val(long long a1) {\n long long v2;\n long long v3;\n v2 = *(uint64_t *)(tstamp_type_choices + 8);\n if (!v2) return 4294967295LL;\n v3 = 0LL;\n while (pcap_strcasecmp(v2, a1)) {\n v3 += 16LL;\n v2 = *(uint64_t *)(tstamp_type_choices + v3 + 8);\n if (!v2) return 4294967295LL;\n }\n return *(unsigned int *)(tstamp_type_choices + v3);\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "int pcap_tstamp_type_name_to_val(const char *var1) {\n int var2;\n for (var2 = 0; var3[var2].field1 != NULL; var2++) {\n if (pcap_strcasecmp(var3[var2].field1, var1) == 0)\n return (var3[var2].field2);\n }\n return (-1);\n}", "style": "rule"}, "extra_info": {"index": 60872, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_2__ TYPE_1__ ;\n\n/* Type definitions */\nstruct TYPE_2__ {int field2; int /*<<< orphan*/ * field1; } ;\n\n/* Variables and functions */\n scalar_t__ pcap_strcasecmp (int /*<<< orphan*/ *,char const*) ; \n TYPE_1__* var3 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nunsigned int *findrr(const char *a1) {\n unsigned int *i;\n for (i = (unsigned int *)rrhead; i; i = *(unsigned int **)i) {\n if (!strcmp(a1, (const char *)i[4])) return i;\n }\n i = (unsigned int *)malloc(24uLL);\n if (!i) puke(\"malloc failure\");\n i[4] = (unsigned int)strdup(a1);\n if (!i[4]) puke(\"malloc failure\");\n *((uint64_t *)i + 1) = 0LL;\n *(uint64_t *)i = rrhead;\n rrhead = (long long)i;\n return i;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "struct type1 *findrr(char *var1) {\n struct type1 *var2;\n var2 = var3;\n while (var2) {\n if (!strcmp(var1, var2->field1)) goto foundrr;\n var2 = var2->field2;\n }\n var2 = (struct type1 *)malloc(sizeof(struct type1));\n if (!var2) puke(\"malloc failure\");\n var2->field1 = strdup(var1);\n if (!var2->field1) puke(\"malloc failure\");\n var2->field3 = 0;\n var2->field2 = var3;\n var3 = var2;\nfoundrr:\n return var2;\n}", "style": "rule"}, "extra_info": {"index": 104430, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\nstruct type1 {struct type1* field2; scalar_t__ field3; int /*<<< orphan*/ field1; } ;\n\n/* Variables and functions */\n scalar_t__ malloc (int) ; \n int /*<<< orphan*/ puke (char*) ; \n int /*<<< orphan*/ strcmp (char*,int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ strdup (char*) ; \n struct type1* var3 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long multiplexFileControl(long long *a1, unsigned int a2, long long *a3) {\n long long v3;\n long long result;\n long long v6;\n uint8_t *v7;\n const char *v8;\n long long v9;\n int v10;\n long long (***v11)(uint64_t, uint64_t, long long *);\n unsigned int v12;\n unsigned long long v13;\n v3 = *a1;\n v13 = __readfsqword(40u);\n result = (unsigned int)SQLITE_ERROR;\n v12 = SQLITE_ERROR;\n if (!gMultiplex) return (unsigned int)SQLITE_MISUSE;\n switch (a2) {\n case 128u:\n case 130u:\n case 131u:\n goto LABEL_11;\n case 129u:\n v6 = a3[1];\n if (!v6 || (unsigned int)sqlite3_stricmp(v6, \"multiplex_truncate\"))\n goto LABEL_18;\n v7 = (uint8_t *)a3[2];\n if (!v7 || !*v7) goto LABEL_7;\n if ((unsigned int)sqlite3_stricmp(v7, \"on\") &&\n (unsigned int)sqlite3_stricmp(a3[2], \"1\")) {\n if ((unsigned int)sqlite3_stricmp(a3[2], \"off\") &&\n (unsigned int)sqlite3_stricmp(a3[2], \"0\")) {\n LABEL_7:\n v8 = \"on\";\n if (!*(uint32_t *)(v3 + 8)) v8 = \"off\";\n v9 = sqlite3_mprintf(v8);\n } else {\n *(uint32_t *)(v3 + 8) = 0;\n v9 = sqlite3_mprintf(\"off\");\n }\n } else {\n *(uint32_t *)(v3 + 8) = 1;\n v9 = sqlite3_mprintf(\"on\");\n }\n *a3 = v9;\n LABEL_11:\n result = (unsigned int)SQLITE_OK;\n break;\n case 132u:\n if (!a3) return result;\n v10 = *(uint32_t *)a3;\n if (!*(uint32_t *)a3) return (unsigned int)SQLITE_MISUSE;\n *(uint32_t *)(v3 + 4) = (MAX_PAGE_SIZE + v10 - 1) & -MAX_PAGE_SIZE;\n result = (unsigned int)SQLITE_OK;\n break;\n case 133u:\n if (a3) {\n *(uint8_t *)v3 = *(uint32_t *)a3;\n return (unsigned int)SQLITE_OK;\n }\n return result;\n default:\n LABEL_18:\n v11 = (long long (***)(uint64_t, uint64_t, long long *))multiplexSubOpen(\n v3, 0LL, &v12, 0LL, 0LL);\n if (!v11) goto LABEL_22;\n result = (**v11)(v11, a2, a3);\n v12 = result;\n if (SQLITE_FCNTL_VFSNAME == a2 && (uint32_t)result == SQLITE_OK) {\n *a3 = sqlite3_mprintf(\"multiplex/%z\", *a3);\n LABEL_22:\n result = v12;\n }\n break;\n }\n return result;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "static int multiplexFileControl(type1 *var1, int var2, void *var3) {\n type2 *var4 = (type2 *)var1;\n type3 *var5 = var4->field1;\n int var6 = var7;\n type1 *var8;\n if (!var9.field2) return var10;\n switch (var2) {\n case var11:\n if (var3) {\n int var12 = *(int *)var3;\n var5->field3 = (unsigned char)var12;\n var6 = var13;\n }\n break;\n case var14:\n if (var3) {\n unsigned int var15 = *(unsigned *)var3;\n if (var15 < 1) {\n var6 = var10;\n } else {\n var15 = (var15 + (var16 - 1));\n var15 &= ~(var16 - 1);\n var5->field4 = var15;\n var6 = var13;\n }\n }\n break;\n case var17:\n var6 = var13;\n break;\n case var18:\n case var19:\n var6 = var13;\n break;\n case var20: {\n char **var21 = (char **)var3;\n if (var21[1] && sqlite3_stricmp(var21[1], \"multiplex_truncate\") == 0) {\n if (var21[2] && var21[2][0]) {\n if (sqlite3_stricmp(var21[2], \"on\") == 0 ||\n sqlite3_stricmp(var21[2], \"1\") == 0) {\n var5->field5 = 1;\n } else if (sqlite3_stricmp(var21[2], \"off\") == 0 ||\n sqlite3_stricmp(var21[2], \"0\") == 0) {\n var5->field5 = 0;\n }\n }\n var21[0] = sqlite3_mprintf(var5->field5 ? \"on\" : \"off\");\n var6 = var13;\n break;\n }\n }\n default:\n var8 = multiplexSubOpen(var5, 0, &var6, NULL, 0);\n if (var8) {\n var6 = var8->field6->field7(var8, var2, var3);\n if (var2 == var22 && var6 == var13) {\n *(char **)var3 = sqlite3_mprintf(\"multiplex/%z\", *(char **)var3);\n }\n }\n break;\n }\n return var6;\n}", "style": "rule"}, "extra_info": {"index": 76754, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_14__ TYPE_5__ ;\ntypedef struct TYPE_13__ TYPE_4__ ;\ntypedef struct TYPE_12__ TYPE_3__ ;\ntypedef struct TYPE_11__ TYPE_2__ ;\ntypedef struct TYPE_10__ TYPE_1__ ;\n\n/* Type definitions */\nstruct TYPE_11__ {unsigned char field3; unsigned int field4; int field5; } ;\ntypedef TYPE_2__ type3 ;\nstruct TYPE_12__ {TYPE_2__* field1; } ;\ntypedef TYPE_3__ type2 ;\nstruct TYPE_13__ {TYPE_1__* field6; } ;\ntypedef TYPE_4__ type1 ;\nstruct TYPE_14__ {int /*<<< orphan*/ field2; } ;\nstruct TYPE_10__ {int (* field7 ) (TYPE_4__*,int,void*) ;} ;\n\n/* Variables and functions */\n TYPE_4__* multiplexSubOpen (TYPE_2__*,int /*<<< orphan*/ ,int*,int /*<<< orphan*/ *,int /*<<< orphan*/ ) ; \n char* sqlite3_mprintf (char*,...) ; \n int /*<<< orphan*/ sqlite3_stricmp (char*,char*) ; \n int stub1 (TYPE_4__*,int,void*) ; \n int var10 ; \n#define var11 133 \n int var13 ; \n#define var14 132 \n int /*<<< orphan*/ var16 ; \n#define var17 131 \n#define var18 130 \n#define var19 129 \n#define var20 128 \n int var22 ; \n int var7 ; \n TYPE_5__ var9 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long php_openssl_dh_pub_from_priv(long long a1, long long a2,\n long long a3) {\n long long v4;\n long long v5;\n long long v6;\n long long v8;\n long long v9;\n long long v10;\n v4 = BN_new();\n if (v4) {\n v5 = BN_new();\n if (v5) {\n v6 = BN_CTX_new();\n if (v6) {\n BN_with_flags(v5, a1, (unsigned int)BN_FLG_CONSTTIME);\n if (!(unsigned int)BN_mod_exp_mont(v4, a2, v5, a3, v6, 0LL)) {\n v8 = v4;\n v4 = 0LL;\n BN_free(v8);\n php_openssl_store_errors();\n }\n BN_free(v5);\n BN_CTX_free(v6);\n } else {\n v10 = v4;\n v4 = 0LL;\n BN_free(v10);\n BN_free(v5);\n php_openssl_store_errors();\n }\n } else {\n v9 = v4;\n v4 = 0LL;\n BN_free(v9);\n php_openssl_store_errors();\n }\n } else {\n php_openssl_store_errors();\n }\n return v4;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "static type1 *php_openssl_dh_pub_from_priv(type1 *var1, type1 *var2,\n type1 *var3) {\n type1 *var4, *var5;\n type2 *var6;\n var4 = BN_new();\n if (var4 == NULL) {\n php_openssl_store_errors();\n return NULL;\n }\n var5 = BN_new();\n if (var5 == NULL) {\n BN_free(var4);\n php_openssl_store_errors();\n return NULL;\n }\n var6 = BN_CTX_new();\n if (var6 == NULL) {\n BN_free(var4);\n BN_free(var5);\n php_openssl_store_errors();\n return NULL;\n }\n BN_with_flags(var5, var1, var7);\n if (!BN_mod_exp_mont(var4, var2, var5, var3, var6, NULL)) {\n BN_free(var4);\n php_openssl_store_errors();\n var4 = NULL;\n }\n BN_free(var5);\n BN_CTX_free(var6);\n return var4;\n}", "style": "rule"}, "extra_info": {"index": 18661, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\ntypedef int /*<<< orphan*/ type2 ;\ntypedef int /*<<< orphan*/ type1 ;\n\n/* Variables and functions */\n int /*<<< orphan*/ BN_CTX_free (int /*<<< orphan*/ *) ; \n int /*<<< orphan*/ * BN_CTX_new () ; \n int /*<<< orphan*/ BN_free (int /*<<< orphan*/ *) ; \n int /*<<< orphan*/ BN_mod_exp_mont (int /*<<< orphan*/ *,int /*<<< orphan*/ *,int /*<<< orphan*/ *,int /*<<< orphan*/ *,int /*<<< orphan*/ *,int /*<<< orphan*/ *) ; \n int /*<<< orphan*/ * BN_new () ; \n int /*<<< orphan*/ BN_with_flags (int /*<<< orphan*/ *,int /*<<< orphan*/ *,int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ php_openssl_store_errors () ; \n int /*<<< orphan*/ var7 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long grep_aliases(const char *a1, int a2, unsigned short a3,\n unsigned short a4) {\n long long v4;\n unsigned int n;\n const char *n_4;\n long long i;\n long long j;\n n_4 = a1;\n n = a2;\n if (a2 > 2 && *a1 == 91 && a1[a2 - 1] == 93) {\n n_4 = a1 + 1;\n n = a2 - 2;\n }\n for (i = aliases; i; i = *(uint64_t *)(i + 16)) {\n if (n == *(uint32_t *)(i + 4) &&\n (!*(unsigned short *)i || !a3 || a3 == *(unsigned short *)i) &&\n (!*(unsigned short *)(i + 2) || !a4 ||\n a4 == *(unsigned short *)(i + 2))) {\n LODWORD(v4) = strncasecmp((const char *)*(unsigned int *)(i + 8), n_4, n);\n if (!v4) return 1LL;\n }\n }\n for (j = alias_fcts; j; j = *(uint64_t *)(j + 8)) {\n if ((*(long long (**)(const char *, uint64_t, uint64_t, uint64_t))j)(\n n_4, n, a3, a4) > 0)\n return 1LL;\n }\n return 0LL;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "static inline int grep_aliases(char* var1, int var2, unsigned short var3,\n unsigned short var4) {\n struct type1* var5;\n struct type2* var6;\n if ((var2 > 2) && ((*var1) == '[') && (var1[var2 - 1] == ']')) {\n var1++;\n var2 -= 2;\n }\n for (var5 = var7; var5; var5 = var5->field1)\n if ((var5->field2.field3 == var2) &&\n ((var5->field4 == 0) || (var3 == 0) || (var5->field4 == var3)) &&\n ((var5->field5 == 0) || (var4 == 0) || (var5->field5 == var4)) &&\n (strncasecmp(var5->field2.field6, var1, var2) == 0))\n return 1;\n for (var6 = var8; var6; var6 = var6->field1) {\n if (var6->field7(var1, var2, var3, var4) > 0) return 1;\n }\n return 0;\n}", "style": "rule"}, "extra_info": {"index": 5364, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_2__ TYPE_1__ ;\n\n/* Type definitions */\nstruct type2 {scalar_t__ (* field7 ) (char*,int,unsigned short,unsigned short) ;struct type2* field1; } ;\nstruct TYPE_2__ {int field3; int /*<<< orphan*/ field6; } ;\nstruct type1 {unsigned short field4; unsigned short field5; TYPE_1__ field2; struct type1* field1; } ;\n\n/* Variables and functions */\n scalar_t__ strncasecmp (int /*<<< orphan*/ ,char*,int) ; \n scalar_t__ stub1 (char*,int,unsigned short,unsigned short) ; \n struct type1* var7 ; \n struct type2* var8 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long CreateTreeWindow(int a1, long long a2, long long a3, long long a4,\n long long a5, long long a6) {\n unsigned int v6;\n unsigned int v7;\n long long v9;\n long long v10;\n uint64_t v11[6];\n int v12;\n int v13;\n int v14;\n unsigned long long v15;\n v15 = __readfsqword(40u);\n if (iNumWindows <= 26) {\n v14 = szTreeClass;\n v13 = a1;\n v12 = hAppInstance;\n v11[0] = 0LL;\n v11[5] = a2;\n v11[4] = a3;\n v11[3] = a4;\n v11[2] = a5;\n v11[1] = a6;\n v9 = SendMessage((unsigned int)hwndMDIClient, (unsigned int)WM_MDIGETACTIVE,\n 0LL, 0LL);\n if (v9) {\n if ((WS_MAXIMIZE &\n (unsigned int)GetWindowLongPtr(v9, (unsigned int)GWL_STYLE)) != 0)\n v11[0] |= WS_MAXIMIZE;\n }\n v10 = SendMessage((unsigned int)hwndMDIClient, (unsigned int)WM_MDICREATE,\n 0LL, v11);\n SetWindowLongPtr(v10, (unsigned int)GWL_VIEW, (unsigned int)dwNewView);\n SetWindowLongPtr(v10, (unsigned int)GWL_SORT, (unsigned int)dwNewSort);\n SetWindowLongPtr(v10, (unsigned int)GWL_ATTRIBS,\n (unsigned int)dwNewAttribs);\n return v10;\n } else {\n v6 = COUNTOF((unsigned int)szTitle);\n LoadString((unsigned int)hAppInstance, (unsigned int)IDS_WINFILE,\n (unsigned int)szTitle, v6);\n v7 = COUNTOF((unsigned int)szMessage);\n LoadString((unsigned int)hAppInstance, (unsigned int)IDS_TOOMANYWINDOWS,\n (unsigned int)szMessage, v7);\n MessageBox((unsigned int)hwndFrame, (unsigned int)szMessage,\n (unsigned int)szTitle, MB_ICONEXCLAMATION | (unsigned int)MB_OK);\n return 0LL;\n }\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "type1 CreateTreeWindow(type2 var1, type3 var2, type3 var3, type3 var4,\n type3 var5, type3 var6) {\n type4 var7;\n type1 var8;\n if (var9 > 26) {\n LoadString(var10, var11, var12, COUNTOF(var12));\n LoadString(var10, var13, var14, COUNTOF(var14));\n MessageBox(var15, var14, var12, var16 | var17);\n return NULL;\n }\n var7.field1 = var18;\n var7.field2 = var1;\n var7.field3 = var10;\n var7.field4 = 0L;\n var7.field5 = var2;\n var7.field6 = var3;\n var7.field7 = var4;\n var7.field8 = var5;\n var7.field9 = var6;\n var8 = (type1)SendMessage(var19, var20, 0, 0L);\n if (var8 && GetWindowLongPtr(var8, var21) & var22) var7.field4 |= var22;\n var8 = (type1)SendMessage(var19, var23, 0L, (var24)&var7);\n SetWindowLongPtr(var8, var25, var26);\n SetWindowLongPtr(var8, var27, var28);\n SetWindowLongPtr(var8, var29, var30);\n return var8;\n}", "style": "rule"}, "extra_info": {"index": 5967, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_2__ TYPE_1__ ;\n\n/* Type definitions */\ntypedef long var24 ;\nstruct TYPE_2__ {long field4; void* field9; void* field8; void* field7; void* field6; void* field5; int /*<<< orphan*/ field3; int /*<<< orphan*/ field2; int /*<<< orphan*/ field1; } ;\ntypedef TYPE_1__ type4 ;\ntypedef void* type3 ;\ntypedef int /*<<< orphan*/ type2 ;\ntypedef int /*<<< orphan*/ * type1 ;\n\n/* Variables and functions */\n int /*<<< orphan*/ COUNTOF (int /*<<< orphan*/ ) ; \n int GetWindowLongPtr (int /*<<< orphan*/ *,int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ LoadString (int /*<<< orphan*/ ,int /*<<< orphan*/ ,int /*<<< orphan*/ ,int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ MessageBox (int /*<<< orphan*/ ,int /*<<< orphan*/ ,int /*<<< orphan*/ ,int) ; \n scalar_t__ SendMessage (int /*<<< orphan*/ ,int /*<<< orphan*/ ,long,long) ; \n int /*<<< orphan*/ SetWindowLongPtr (int /*<<< orphan*/ *,int /*<<< orphan*/ ,int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ var10 ; \n int /*<<< orphan*/ var11 ; \n int /*<<< orphan*/ var12 ; \n int /*<<< orphan*/ var13 ; \n int /*<<< orphan*/ var14 ; \n int /*<<< orphan*/ var15 ; \n int var16 ; \n int var17 ; \n int /*<<< orphan*/ var18 ; \n int /*<<< orphan*/ var19 ; \n int /*<<< orphan*/ var20 ; \n int /*<<< orphan*/ var21 ; \n int var22 ; \n int /*<<< orphan*/ var23 ; \n int /*<<< orphan*/ var25 ; \n int /*<<< orphan*/ var26 ; \n int /*<<< orphan*/ var27 ; \n int /*<<< orphan*/ var28 ; \n int /*<<< orphan*/ var29 ; \n int /*<<< orphan*/ var30 ; \n int var9 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long find_polltbl_idx(long long a1, long long a2) {\n unsigned int i;\n for (i = 0; (signed int)i < *(uint32_t *)a1; ++i) {\n if (a2 == *(uint64_t *)(*(uint64_t *)(a1 + 8) + 8LL * (int)i)) return i;\n }\n return 4294967295LL;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "static int find_polltbl_idx(struct type1 *var1, uint64_t var2) {\n int var3;\n for (var3 = 0; var3 < var1->field1; var3++) {\n if (var1->field2[var3].field3 != var2) continue;\n return (var3);\n }\n return (-1);\n}", "style": "rule"}, "extra_info": {"index": 60178, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_2__ TYPE_1__ ;\n\n/* Type definitions */\ntypedef scalar_t__ uint64_t ;\nstruct type1 {int field1; TYPE_1__* field2; } ;\nstruct TYPE_2__ {scalar_t__ field3; } ;\n\n/* Variables and functions */\n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nint main(int argc, const char **argv, const char **envp) {\n FILE *v3;\n unsigned int v4;\n int v5;\n unsigned int v6;\n int v7;\n uint64_t *v8;\n int v9;\n unsigned int v10;\n unsigned int v11;\n unsigned int v12;\n unsigned int v13;\n unsigned int v14;\n unsigned int v16;\n int v17;\n int fd;\n unsigned long long v19;\n v19 = __readfsqword(40u);\n v3 = tmpfile();\n BUG_ON(v3 == 0LL, \"tmpfile()\");\n v4 = MMAP_SZ;\n v5 = fileno(v3);\n v6 = ftruncate(v5, v4);\n BUG_ON(v6, \"ftruncate()\");\n v7 = fileno(v3);\n v8 = mmap(0LL, (unsigned int)MMAP_SZ, PROT_WRITE | (unsigned int)PROT_READ,\n MAP_SHARED, v7, 0LL);\n BUG_ON(MAP_FAILED == (uint64_t)v8, \"mmap()\");\n v9 = MS_SYNC;\n *v8 = 3735927486LL;\n v10 = msync(v8, (unsigned int)MMAP_SZ, v9);\n BUG_ON(v10, \"msync()\");\n v11 = socketpair(PF_LOCAL, SOCK_SEQPACKET, 0, &v17);\n BUG_ON(v11, \"socketpair()\");\n v12 = fork();\n BUG_ON(v12 == -1, \"fork()\");\n if (v12) {\n v16 = close(v17);\n BUG_ON(v16, \"close()\");\n return parent_f((unsigned int)fd, v8, v12);\n } else {\n v13 = close(fd);\n BUG_ON(v13, \"close()\");\n v14 = fileno(v3);\n return child_f((unsigned int)v17, v8, v14);\n }\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "int main(int var1, char **var2) {\n int var3[2], var4, var5;\n type1 *var6;\n unsigned long *var7;\n var6 = tmpfile();\n BUG_ON(var6 == 0, \"tmpfile()\");\n var5 = ftruncate(fileno(var6), var8);\n BUG_ON(var5, \"ftruncate()\");\n var7 = mmap(0, var8, var9 | var10, var11, fileno(var6), 0);\n BUG_ON(var7 == var12, \"mmap()\");\n *var7 = 0xdeadbabe;\n var5 = msync(var7, var8, var13);\n BUG_ON(var5, \"msync()\");\n var5 = socketpair(var14, var15, 0, var3);\n BUG_ON(var5, \"socketpair()\");\n var4 = fork();\n BUG_ON(var4 == -1, \"fork()\");\n if (var4) {\n var5 = close(var3[0]);\n BUG_ON(var5, \"close()\");\n return parent_f(var3[1], var7, var4);\n }\n var5 = close(var3[1]);\n BUG_ON(var5, \"close()\");\n return child_f(var3[0], var7, fileno(var6));\n}", "style": "rule"}, "extra_info": {"index": 3940, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\ntypedef int /*<<< orphan*/ type1 ;\n\n/* Variables and functions */\n int /*<<< orphan*/ BUG_ON (int,char*) ; \n int child_f (int,unsigned long*,int /*<<< orphan*/ ) ; \n int close (int) ; \n int /*<<< orphan*/ fileno (int /*<<< orphan*/ *) ; \n int fork () ; \n int ftruncate (int /*<<< orphan*/ ,int /*<<< orphan*/ ) ; \n unsigned long* mmap (int /*<<< orphan*/ ,int /*<<< orphan*/ ,int,int /*<<< orphan*/ ,int /*<<< orphan*/ ,int /*<<< orphan*/ ) ; \n int msync (unsigned long*,int /*<<< orphan*/ ,int /*<<< orphan*/ ) ; \n int parent_f (int,unsigned long*,int) ; \n int socketpair (int /*<<< orphan*/ ,int /*<<< orphan*/ ,int /*<<< orphan*/ ,int*) ; \n int /*<<< orphan*/ * tmpfile () ; \n int var10 ; \n int /*<<< orphan*/ var11 ; \n unsigned long* var12 ; \n int /*<<< orphan*/ var13 ; \n int /*<<< orphan*/ var14 ; \n int /*<<< orphan*/ var15 ; \n int /*<<< orphan*/ var8 ; \n int var9 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long dlr_are_libraries_compatible(long long a1, const char **a2,\n long long a3) {\n long long v6;\n long long v7;\n const char *v8;\n char *v9;\n const char *v10;\n const char *v11;\n long long v12;\n unsigned int v13;\n const char *v14;\n long long v15;\n long long v16;\n long long v18;\n long long symbol_name;\n long long v20;\n long long v21;\n const char *v22;\n const char *v23;\n const char *v24;\n long long v25;\n unsigned int v26;\n int v27;\n unsigned int v28;\n const char *v29;\n const char *v30;\n unsigned int v31;\n int v32;\n const char *v33;\n char *v34;\n long long v35;\n char *v36;\n char dest[24];\n unsigned long long v38;\n v38 = __readfsqword(40u);\n if (!a3) {\n symbol_name = dlr_get_symbol_name();\n v20 = *((unsigned int *)a2 + 6);\n v21 = *(unsigned int *)(a1 + 24);\n v34 = (char *)symbol_name;\n v22 = \"%s (%.*s vs. %.*s): no restrictions symbol (%s) present\";\n v33 = (const char *)*((unsigned int *)a2 + 4);\n v23 = (const char *)*(unsigned int *)(a1 + 16);\n LABEL_22:\n dlr_debug(1LL, v22, \"ACCEPT\", v21, v23, v20, v33, v34, v35, v36);\n HIDWORD(v35) = 1;\n return HIDWORD(v35);\n }\n LODWORD(v6) = strncmp(*(const char **)a3, \"DLR_SYMBOL_V1:\", 8uLL);\n if (v6) {\n v24 = *(const char **)a3;\n v25 = dlr_get_symbol_name();\n dlr_debug(1LL,\n \"%s (%.*s vs. %.*s): restrictions symbol (%s) magic (%.*s) \"\n \"unrecognized\",\n \"ACCEPT\", *(unsigned int *)(a1 + 24), *(unsigned int *)(a1 + 16),\n *((unsigned int *)a2 + 6), *((unsigned int *)a2 + 4), v25, 14LL,\n v24);\n goto LABEL_17;\n }\n v7 = *(unsigned int *)(a3 + 8);\n if ((unsigned int)v7 > 4096) {\n dlr_set_error(\n \"%.*s vs. %.*s: restrictions symbol expression is too long (%u). \"\n \"Maximum is %u\",\n *(uint32_t *)(a1 + 24), (const char *)*(unsigned int *)(a1 + 16),\n *((uint32_t *)a2 + 6), (const char *)*((unsigned int *)a2 + 4), v7,\n 4096);\n HIDWORD(v35) = -1;\n return HIDWORD(v35);\n }\n v8 = *(const char **)(a3 + 16);\n if (!(uint32_t)v7 || !v8) {\n dlr_debug(1LL,\n \"%s (%.*s vs. %.*s): restrictions symbol expression is empty \"\n \"(l=%d,exp=%lx)\",\n \"ACCEPT\", *(unsigned int *)(a1 + 24), *(unsigned int *)(a1 + 16),\n *((unsigned int *)a2 + 6), *((unsigned int *)a2 + 4), v7,\n *(uint64_t *)(a3 + 16));\n LABEL_17:\n HIDWORD(v35) = 1;\n return HIDWORD(v35);\n }\n v36 = dest;\n strncpy(dest, v8, (unsigned int)v7);\n dest[v7] = 0;\n v9 = strtok(dest, \",\");\n if (!v9) {\n v29 = (const char *)*((unsigned int *)a2 + 4);\n v20 = *((unsigned int *)a2 + 6);\n v23 = (const char *)*(unsigned int *)(a1 + 16);\n v21 = *(unsigned int *)(a1 + 24);\n LABEL_28:\n v34 = dest;\n v22 = \"%s (%.*s vs. %.*s): restriction expression (%s) processed\";\n v33 = v29;\n goto LABEL_22;\n }\n HIDWORD(v35) = 1;\n do {\n v14 = (const char *)skip_spaces(v9);\n LODWORD(v15) = strncmp(v14, \"ACCEPT:\", 7uLL);\n if (v15) {\n LODWORD(v16) = strncmp(v14, \"REJECT:\", 7uLL);\n if (v16) {\n v30 = (const char *)*(unsigned int *)(a1 + 16);\n v31 = *((uint32_t *)a2 + 6);\n v32 = *(uint32_t *)(a1 + 24);\n errno = EINVAL;\n dlr_set_error(\n \"%.*s vs. %.*s: syntax error in restriction expression (%s):%d: \"\n \"ACCEPT: or REJECT: expected\",\n v32, v30, v31, (const char *)*((unsigned int *)a2 + 4), dest,\n (uint32_t)v14 - (unsigned int)dest + 1);\n HIDWORD(v35) = -1;\n return HIDWORD(v35);\n }\n LODWORD(v35) = 0;\n v10 = v14 + 7;\n } else {\n LODWORD(v35) = 1;\n v10 = v14 + 7;\n }\n v11 = (const char *)skip_spaces(v10);\n LODWORD(v12) = strcmp(v11, \"OTHERSOVERSION\");\n if (v12) {\n v26 = *((uint32_t *)a2 + 6);\n v27 = *(uint32_t *)(a1 + 24);\n v28 = *(uint32_t *)(a1 + 16);\n errno = ENOTSUP;\n dlr_set_error(\n \"%.*s vs. %.*s: unsupported token in restriction expression (%s):%d: \"\n \"%s\",\n v27, (const char *)v28, v26, (const char *)*((unsigned int *)a2 + 4),\n dest, (uint32_t)v11 - (unsigned int)dest + 1, v11);\n HIDWORD(v35) = -1;\n return HIDWORD(v35);\n }\n v13 = *(unsigned int *)a2;\n if (*(uint32_t *)a1 != (uint32_t)v13 ||\n (LODWORD(v18) = strncmp(*(const char **)(a1 + 8), a2[1], v13), v18))\n HIDWORD(v35) = v35;\n v9 = strtok(0LL, \",\");\n } while (v9);\n v29 = (const char *)*((unsigned int *)a2 + 4);\n v23 = (const char *)*(unsigned int *)(a1 + 16);\n v21 = *(unsigned int *)(a1 + 24);\n v20 = (unsigned int)a2[3];\n if (HIDWORD(v35)) goto LABEL_28;\n dlr_debug(1LL, \"%s (%.*s vs. %.*s): restriction expression (%s) processed\",\n \"REJECT\", v21, v23, v20, v29, dest);\n dlr_set_error(\"%.*s vs. %.*s: libraries conflict%s\", *(uint32_t *)(a1 + 24),\n (const char *)*(unsigned int *)(a1 + 16), *((uint32_t *)a2 + 6),\n (const char *)*((unsigned int *)a2 + 4), (const char *)&LC14);\n return HIDWORD(v35);\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "static int dlr_are_libraries_compatible(type1 *var1, type1 *var2, type2 *var3) {\n unsigned int var4;\n char var5[4096 + 1];\n int var6;\n char *var7;\n unsigned char var8;\n if (var3 == NULL) {\n dlr_debug(1,\n \"%s (%.*s vs. %.*s): \"\n \"no restrictions symbol (%s) present\",\n \"ACCEPT\", (int)var1->field1, var1->field2, (int)var2->field1,\n var2->field2, dlr_get_symbol_name());\n return 1;\n }\n if (strncmp(var3->field3, \"DLR_SYMBOL_V1:\", sizeof(var3->field3))) {\n dlr_debug(1,\n \"%s (%.*s vs. %.*s): \"\n \"restrictions symbol (%s) magic (%.*s) unrecognized\",\n \"ACCEPT\", (int)var1->field1, var1->field2, (int)var2->field1,\n var2->field2, dlr_get_symbol_name(),\n (int)sizeof(\"DLR_SYMBOL_V1:\") - 1, var3->field3);\n return 1;\n }\n var4 = var3->field4;\n if (var4 > 4096) {\n dlr_set_error(\n \"%.*s vs. %.*s: \"\n \"restrictions symbol expression is too long (%u). Maximum is %u\",\n (int)var1->field1, var1->field2, (int)var2->field1, var2->field2, var4,\n 4096);\n ;\n return -1;\n }\n if (var4 == 0 || var3->field5 == NULL) {\n dlr_debug(1,\n \"%s (%.*s vs. %.*s): \"\n \"restrictions symbol expression is empty (l=%d,exp=%lx)\",\n \"ACCEPT\", (int)var1->field1, var1->field2, (int)var2->field1,\n var2->field2, var4, var3->field5);\n return 1;\n }\n strncpy(var5, var3->field5, var4);\n var5[var4] = '\\0';\n var6 = 1;\n var7 = strtok(var5, \",\");\n while (var7 != NULL) {\n var7 = skip_spaces(var7);\n if (strncmp(var7, \"ACCEPT:\", 7) == 0) {\n var8 = 1;\n var7 += 7;\n } else if (strncmp(var7, \"REJECT:\", 7) == 0) {\n var8 = 0;\n var7 += 7;\n } else {\n var9 = var10;\n dlr_set_error(\n \"%.*s vs. %.*s: syntax error in restriction expression (%s):%d: \"\n \"ACCEPT: or REJECT: expected\",\n (int)var1->field1, var1->field2, (int)var2->field1, var2->field2,\n var5, (int)(var7 - var5 + 1));\n return -1;\n }\n var7 = skip_spaces(var7);\n if (strcmp(var7, \"OTHERSOVERSION\") == 0) {\n if (!(var1->field6 == var2->field6 &&\n strncmp(var1->field7, var2->field7, var2->field6) == 0)) {\n var6 = var8;\n }\n } else {\n var9 = var11;\n dlr_set_error(\n \"%.*s vs. %.*s: unsupported token in restriction expression (%s):%d: \"\n \"%s\",\n (int)var1->field1, var1->field2, (int)var2->field1, var2->field2,\n var5, (int)(var7 - var5 + 1), var7);\n return -1;\n }\n var7 = strtok(NULL, \",\");\n }\n dlr_debug(1,\n \"%s (%.*s vs. %.*s): \"\n \"restriction expression (%s) processed\",\n ((var6) ? \"ACCEPT\" : \"REJECT\"), (int)var1->field1, var1->field2,\n (int)var2->field1, var2->field2, var5);\n if (var6 == 0) {\n dlr_set_error(\n \"%.*s vs. %.*s: \"\n \"libraries conflict%s\",\n (int)var1->field1, var1->field2, (int)var2->field1, var2->field2, \"\");\n ;\n }\n return var6;\n}", "style": "rule"}, "extra_info": {"index": 23378, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_7__ TYPE_2__ ;\ntypedef struct TYPE_6__ TYPE_1__ ;\n\n/* Type definitions */\nstruct TYPE_6__ {char* field3; unsigned int field4; int /*<<< orphan*/ * field5; } ;\ntypedef TYPE_1__ type2 ;\nstruct TYPE_7__ {int field6; char* field7; int /*<<< orphan*/ field2; scalar_t__ field1; } ;\ntypedef TYPE_2__ type1 ;\n\n/* Variables and functions */\n int /*<<< orphan*/ dlr_debug (int,char*,char*,int,int /*<<< orphan*/ ,int,int /*<<< orphan*/ ,...) ; \n char* dlr_get_symbol_name () ; \n int /*<<< orphan*/ dlr_set_error (char*,int,int /*<<< orphan*/ ,int,int /*<<< orphan*/ ,...) ; \n char* skip_spaces (char*) ; \n scalar_t__ strcmp (char*,char*) ; \n scalar_t__ strncmp (char*,char*,int) ; \n int /*<<< orphan*/ strncpy (char*,int /*<<< orphan*/ *,unsigned int) ; \n char* strtok (char*,char*) ; \n int /*<<< orphan*/ var10 ; \n int /*<<< orphan*/ var11 ; \n int /*<<< orphan*/ var9 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nint __noreturn main(int argc, const char **argv, const char **envp) {\n int v3;\n int v4;\n long long v5;\n long long v6;\n int v7;\n int v8;\n struct sockaddr s[65];\n unsigned long long v10;\n v10 = __readfsqword(40u);\n v3 = socket(AF_INET, SOCK_STREAM, 0);\n if (v3 >= 0) {\n memset(s, 0, 12uLL);\n *(uint32_t *)&s[0].sa_data[6] = AF_INET;\n *(uint32_t *)&s[0].sa_data[2] = htonl(INADDR_ANY);\n LOWORD(v4) = htons(50004u);\n *(uint32_t *)&s[0].sa_family = v4;\n LODWORD(v5) = bind(v3, s, 12u);\n if (v5 >= 0) {\n LODWORD(v6) = listen(v3, 5);\n if (v6 >= 0) {\n if (signal(SIGCHLD, (void (*)(int))(unsigned int)SIG_IGN) !=\n (void (*)(int))SIG_ERR) {\n while (1) {\n v7 = accept(v3, 0LL, 0LL);\n if (v7 < 0) break;\n if (fork() == -1) {\n perror(\"Errorea umea sortzean\");\n exit(1);\n }\n if (!fork()) {\n close(v3);\n while (1) {\n v8 = read(v7, &s[0].sa_data[10], 1024uLL);\n if (v8 <= 0) break;\n if ((int)write(v7, &s[0].sa_data[10], (unsigned int)v8) < v8) {\n perror(\"Errorea erantzuna bidaltzean\");\n close(v7);\n exit(1);\n }\n }\n if (v8) perror(\"Errorea mezua irakurtzean\");\n close(v7);\n exit(0);\n }\n close(v7);\n }\n perror(\"Errorea konexioa onartzean\");\n exit(1);\n }\n perror(\"Errorea signalen\");\n exit(1);\n }\n perror(\"Errorea socketa entzute socket bezala ezartzean\");\n exit(1);\n }\n perror(\"Errorea socketari helbidea esleitzean\");\n exit(1);\n }\n perror(\"Errorea socketa sortzean\");\n exit(1);\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "int main() {\n int var1, var2;\n int var3;\n struct type1 var4;\n char var5[1024];\n if ((var1 = socket(var6, var7, 0)) < 0) {\n perror(\"Errorea socketa sortzean\");\n exit(1);\n }\n memset(&var4, 0, sizeof(var4));\n var4.field1 = var6;\n var4.field2.field3 = htonl(var8);\n var4.field4 = htons(50004);\n if (bind(var1, (struct type2 *)&var4, sizeof(var4)) < 0) {\n perror(\"Errorea socketari helbidea esleitzean\");\n exit(1);\n }\n if (listen(var1, 5) < 0) {\n perror(\"Errorea socketa entzute socket bezala ezartzean\");\n exit(1);\n }\n if (signal(var9, var10) == var11) {\n perror(\"Errorea signalen\");\n exit(1);\n }\n while (1) {\n if ((var2 = accept(var1, NULL, NULL)) < 0) {\n perror(\"Errorea konexioa onartzean\");\n exit(1);\n }\n if (fork() == -1) {\n perror(\"Errorea umea sortzean\");\n exit(1);\n } else {\n if (fork() != 0) {\n close(var2);\n } else {\n close(var1);\n while ((var3 = read(var2, var5, 1024)) > 0) {\n if (write(var2, var5, var3) < var3) {\n perror(\"Errorea erantzuna bidaltzean\");\n close(var2);\n exit(1);\n }\n }\n if (var3 < 0) perror(\"Errorea mezua irakurtzean\");\n close(var2);\n exit(0);\n }\n }\n }\n}", "style": "rule"}, "extra_info": {"index": 109131, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_2__ TYPE_1__ ;\n\n/* Type definitions */\ntypedef int /*<<< orphan*/ var4 ;\nstruct type2 {int dummy; } ;\nstruct TYPE_2__ {int /*<<< orphan*/ field3; } ;\nstruct type1 {int /*<<< orphan*/ field4; TYPE_1__ field2; int /*<<< orphan*/ field1; } ;\n\n/* Variables and functions */\n int accept (int,int /*<<< orphan*/ *,int /*<<< orphan*/ *) ; \n scalar_t__ bind (int,struct type2*,int) ; \n int /*<<< orphan*/ close (int) ; \n int /*<<< orphan*/ exit (int) ; \n int fork () ; \n int /*<<< orphan*/ htonl (int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ htons (int) ; \n scalar_t__ listen (int,int) ; \n int /*<<< orphan*/ memset (struct type1*,int /*<<< orphan*/ ,int) ; \n int /*<<< orphan*/ perror (char*) ; \n int read (int,char*,int) ; \n scalar_t__ signal (int /*<<< orphan*/ ,int /*<<< orphan*/ ) ; \n int socket (int /*<<< orphan*/ ,int /*<<< orphan*/ ,int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ var10 ; \n scalar_t__ var11 ; \n int /*<<< orphan*/ var6 ; \n int /*<<< orphan*/ var7 ; \n int /*<<< orphan*/ var8 ; \n int /*<<< orphan*/ var9 ; \n int write (int,char*,int) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long ufs_mtk_phy_set_active(long long a1) {\n mphy_set_bit(a1, (unsigned int)MP_GLB_DIG_8C, (unsigned int)PLL_PWR_ON);\n mphy_clr_bit(a1, (unsigned int)MP_GLB_DIG_8C, (unsigned int)FRC_FRC_PWR_ON);\n mphy_clr_bit(a1, (unsigned int)MP_GLB_DIG_8C, (unsigned int)PLL_ISO_EN);\n mphy_clr_bit(a1, (unsigned int)MP_GLB_DIG_8C, (unsigned int)FRC_PLL_ISO_EN);\n mphy_set_bit(a1, (unsigned int)MP_LN_RX_44, (unsigned int)CDR_PWR_ON);\n mphy_clr_bit(a1, (unsigned int)MP_LN_RX_44, (unsigned int)FRC_CDR_PWR_ON);\n mphy_clr_bit(a1, (unsigned int)MP_LN_RX_44, (unsigned int)CDR_ISO_EN);\n mphy_clr_bit(a1, (unsigned int)MP_LN_RX_44, (unsigned int)FRC_CDR_ISO_EN);\n mphy_set_bit(a1, (unsigned int)MP_LN_DIG_RX_AC, (unsigned int)RX_SQ_EN);\n mphy_clr_bit(a1, (unsigned int)MP_LN_DIG_RX_AC, (unsigned int)FRC_RX_SQ_EN);\n udelay(1LL);\n return mphy_clr_bit(a1, (unsigned int)MP_LN_DIG_RX_9C,\n (unsigned int)FSM_DIFZ_FRC);\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "static void ufs_mtk_phy_set_active(struct type1 *var1) {\n mphy_set_bit(var1, var2, var3);\n mphy_clr_bit(var1, var2, var4);\n mphy_clr_bit(var1, var2, var5);\n mphy_clr_bit(var1, var2, var6);\n mphy_set_bit(var1, var7, var8);\n mphy_clr_bit(var1, var7, var9);\n mphy_clr_bit(var1, var7, var10);\n mphy_clr_bit(var1, var7, var11);\n mphy_set_bit(var1, var12, var13);\n mphy_clr_bit(var1, var12, var14);\n udelay(1);\n mphy_clr_bit(var1, var15, var16);\n}", "style": "rule"}, "extra_info": {"index": 33978, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\nstruct type1 {int dummy; } ;\n\n/* Variables and functions */\n int /*<<< orphan*/ mphy_clr_bit (struct type1*,int /*<<< orphan*/ ,int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ mphy_set_bit (struct type1*,int /*<<< orphan*/ ,int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ udelay (int) ; \n int /*<<< orphan*/ var10 ; \n int /*<<< orphan*/ var11 ; \n int /*<<< orphan*/ var12 ; \n int /*<<< orphan*/ var13 ; \n int /*<<< orphan*/ var14 ; \n int /*<<< orphan*/ var15 ; \n int /*<<< orphan*/ var16 ; \n int /*<<< orphan*/ var2 ; \n int /*<<< orphan*/ var3 ; \n int /*<<< orphan*/ var4 ; \n int /*<<< orphan*/ var5 ; \n int /*<<< orphan*/ var6 ; \n int /*<<< orphan*/ var7 ; \n int /*<<< orphan*/ var8 ; \n int /*<<< orphan*/ var9 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long GetKeyName(unsigned int a1) {\n long long LastError;\n unsigned int v2;\n long long v3;\n long long v4;\n unsigned int v5;\n unsigned int v6;\n unsigned int ProcessHeap;\n long long v8;\n unsigned int v9;\n unsigned int v10;\n unsigned int v11;\n int v13;\n long long v14;\n long long v15;\n long long v16;\n unsigned long long v17;\n v17 = __readfsqword(40u);\n v14 = TRUE;\n v13 = 0;\n v15 = 0LL;\n v16 = OpenSCManager(0LL, 0LL, (unsigned int)SC_MANAGER_CONNECT);\n if (!v16) {\n LastError = GetLastError();\n v2 = T(\"[SC] OpenSCManager FAILED %lu:\\n\\n\", 0LL);\n tprintf(v2, LastError);\n v14 = FALSE;\n goto LABEL_10;\n }\n v3 = a1;\n if (!(unsigned int)GetServiceKeyName(v16, a1, 0LL, &v13) && !v13)\n goto LABEL_5;\n v6 = 4 * (v13 + 1);\n ProcessHeap = GetProcessHeap();\n v15 = HeapAlloc(ProcessHeap, 0LL, v6);\n if (v15) {\n ++v13;\n v3 = a1;\n if (!(unsigned int)GetServiceKeyName(v16, a1, v15, &v13)) {\n LABEL_5:\n v4 = GetLastError();\n v5 = T(\"[SC] GetServiceKeyName FAILED %lu:\\n\\n\", v3);\n tprintf(v5, v4);\n v14 = FALSE;\n goto LABEL_10;\n }\n v10 = T(\"[SC] GetServiceKeyName SUCCESS Name = %s\\n\", (const char *)a1);\n tprintf(v10, v15);\n } else {\n SetLastError((unsigned int)ERROR_OUTOFMEMORY);\n v8 = GetLastError();\n v9 = T(\"[SC] HeapAlloc FAILED %lu:\\n\\n\", 0LL);\n tprintf(v9, v8);\n v14 = FALSE;\n }\nLABEL_10:\n if (v14 == FALSE) ReportLastError();\n if (v15) {\n v11 = GetProcessHeap();\n HeapFree(v11, 0LL, v15);\n }\n if (v16) CloseServiceHandle(v16);\n return v14;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "type1 GetKeyName(type2 var1) {\n type3 var2 = NULL;\n type1 var3 = TRUE;\n type4 var4 = 0;\n type5 var5 = NULL;\n var2 = OpenSCManager(NULL, NULL, var6);\n if (var2 == NULL) {\n func1(func2(\"[SC] OpenSCManager FAILED %lu:\\n\\n\"), GetLastError());\n var3 = FALSE;\n goto done;\n }\n if (!GetServiceKeyName(var2, var1, NULL, &var4)) {\n if (var4 == 0) {\n func1(func2(\"[SC] GetServiceKeyName FAILED %lu:\\n\\n\"), GetLastError());\n var3 = FALSE;\n goto done;\n }\n }\n var5 = HeapAlloc(GetProcessHeap(), 0, (var4 + 1) * sizeof(var7));\n if (var5 == NULL) {\n SetLastError(var8);\n func1(func2(\"[SC] HeapAlloc FAILED %lu:\\n\\n\"), GetLastError());\n var3 = FALSE;\n goto done;\n }\n var4++;\n if (!GetServiceKeyName(var2, var1, var5, &var4)) {\n func1(func2(\"[SC] GetServiceKeyName FAILED %lu:\\n\\n\"), GetLastError());\n var3 = FALSE;\n goto done;\n }\n func1(func2(\"[SC] GetServiceKeyName SUCCESS Name = %s\\n\"), var5);\ndone:\n if (var3 == FALSE) ReportLastError();\n if (var5 != NULL) HeapFree(GetProcessHeap(), 0, var5);\n if (var2) CloseServiceHandle(var2);\n return var3;\n}", "style": "rule"}, "extra_info": {"index": 73571, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\ntypedef int /*<<< orphan*/ var7 ;\ntypedef int /*<<< orphan*/ * type5 ;\ntypedef int type4 ;\ntypedef int /*<<< orphan*/ * type3 ;\ntypedef int /*<<< orphan*/ type2 ;\ntypedef scalar_t__ type1 ;\n\n/* Variables and functions */\n int /*<<< orphan*/ CloseServiceHandle (int /*<<< orphan*/ *) ; \n scalar_t__ FALSE ; \n int /*<<< orphan*/ * GetLastError () ; \n int /*<<< orphan*/ GetProcessHeap () ; \n int /*<<< orphan*/ GetServiceKeyName (int /*<<< orphan*/ *,int /*<<< orphan*/ ,int /*<<< orphan*/ *,int*) ; \n int /*<<< orphan*/ * HeapAlloc (int /*<<< orphan*/ ,int /*<<< orphan*/ ,int) ; \n int /*<<< orphan*/ HeapFree (int /*<<< orphan*/ ,int /*<<< orphan*/ ,int /*<<< orphan*/ *) ; \n int /*<<< orphan*/ * OpenSCManager (int /*<<< orphan*/ *,int /*<<< orphan*/ *,int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ ReportLastError () ; \n int /*<<< orphan*/ SetLastError (int /*<<< orphan*/ ) ; \n scalar_t__ TRUE ; \n int /*<<< orphan*/ func1 (int /*<<< orphan*/ ,int /*<<< orphan*/ *) ; \n int /*<<< orphan*/ func2 (char*) ; \n int /*<<< orphan*/ var6 ; \n int /*<<< orphan*/ var8 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nunsigned long long reduceset(unsigned int *a1) {\n int v1;\n int v2;\n uint64_t *v3;\n unsigned int v4;\n signed int v5;\n uint64_t *v6;\n uint64_t *v7;\n long long v8;\n unsigned int v9;\n signed int v10;\n uint64_t *v11;\n uint64_t *v12;\n long long v13;\n int v15;\n int v16;\n uint64_t *v17;\n long long v18;\n uint64_t *v19;\n unsigned long long v20;\n v20 = __readfsqword(40u);\n if (a1[8]) {\n v18 = *((uint64_t *)a1 + 5);\n v19 = (uint64_t *)*((uint64_t *)a1 + 6);\n v17 = (uint64_t *)findvect(*a1, v18, v19);\n if (v17) {\n if (*v17 > *((uint64_t *)a1 + 1)) improvesol(a1, v17);\n } else {\n v17 = (uint64_t *)(v18 - 16);\n }\n expandcore(a1, &v15, &v16);\n v1 = *a1;\n v2 = *((uint64_t *)a1 + 1) + 1;\n v3 = (uint64_t *)*((uint64_t *)a1 + 7);\n if (!v15) {\n v4 = a1[4];\n v5 = a1[5];\n v6 = v19;\n v7 = v17;\n while (v6 != v7) {\n if ((*v6 - v2) * v5 - (int)(v4 * (*((uint32_t *)v6 + 2) - v1)) >= 0LL) {\n v3 -= 2;\n v8 = v6[1];\n *v3 = *v6;\n v3[1] = v8;\n }\n v6 -= 2;\n }\n }\n if (!v16) {\n v9 = a1[6];\n v10 = a1[7];\n v11 = v17;\n v12 = (uint64_t *)(v18 - 16);\n while (v11 != v12) {\n if ((*v11 - v2) * v10 - (int)(v9 * (*((uint32_t *)v11 + 2) - v1)) >=\n 0LL) {\n v3 -= 2;\n v13 = v11[1];\n *v3 = *v11;\n v3[1] = v13;\n }\n v11 -= 2;\n }\n }\n *((uint64_t *)a1 + 5) = v3;\n *((uint64_t *)a1 + 6) = *((uint64_t *)a1 + 7) - 16LL;\n a1[8] = (*((uint64_t *)a1 + 6) + 16LL - *((uint64_t *)a1 + 5)) >> 4;\n }\n return v20 - __readfsqword(40u);\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "static void reduceset(type1 *var1) {\n register type2 *var2, *var3, *var4;\n register type3 var5, var6;\n register type4 var7, var8;\n type2 *var9, *var10, *var11;\n type5 var12, var13;\n if (var1->field1.field2 == 0) return;\n var10 = var1->field1.field3;\n var11 = var1->field1.field4;\n var9 = findvect(var1->field5, var10, var11);\n if (var9 == NULL)\n var9 = var10 - 1;\n else if (var9->field6 > var1->field7)\n improvesol(var1, var9);\n expandcore(var1, &var12, &var13);\n var5 = var1->field5;\n var6 = var1->field7 + 1;\n var4 = var1->field1.field8;\n if (!var12) {\n var7 = var1->field9;\n var8 = var1->field10;\n for (var2 = var11, var3 = var9; var2 != var3; var2--) {\n if (((var2->field6 - var6) * (type4)(type6) -\n (var2->field11 - var5) * (var14)(var7)) >= 0) {\n var4--;\n *var4 = *var2;\n }\n }\n }\n if (!var13) {\n var7 = var1->field12;\n var8 = var1->field13;\n for (var2 = var9, var3 = var10 - 1; var2 != var3; var2--) {\n if (((var2->field6 - var6) * (type4)(type6) -\n (var2->field11 - var5) * (var14)(var7)) >= 0) {\n var4--;\n *var4 = *var2;\n }\n }\n }\n var1->field1.field3 = var4;\n var1->field1.field4 = var1->field1.field8 - 1;\n var1->field1.field2 =\n ((int)(((var1->field1.field4) + 1) - (var1->field1.field3)));\n}", "style": "rule"}, "extra_info": {"index": 49853, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_13__ TYPE_3__ ;\ntypedef struct TYPE_12__ TYPE_2__ ;\ntypedef struct TYPE_11__ TYPE_1__ ;\n\n/* Type definitions */\ntypedef int var14 ;\ntypedef scalar_t__ type6 ;\ntypedef int /*<<< orphan*/ type5 ;\ntypedef int type4 ;\ntypedef int type3 ;\nstruct TYPE_12__ {scalar_t__ field6; int field11; } ;\ntypedef TYPE_2__ type2 ;\nstruct TYPE_11__ {int field2; TYPE_2__* field3; TYPE_2__* field4; TYPE_2__* field8; } ;\nstruct TYPE_13__ {int field5; scalar_t__ field7; int field9; int field10; int field12; int field13; TYPE_1__ field1; } ;\ntypedef TYPE_3__ type1 ;\n\n/* Variables and functions */\n int /*<<< orphan*/ expandcore (TYPE_3__*,int /*<<< orphan*/ *,int /*<<< orphan*/ *) ; \n TYPE_2__* findvect (int,TYPE_2__*,TYPE_2__*) ; \n int /*<<< orphan*/ improvesol (TYPE_3__*,TYPE_2__*) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nint __noreturn main(int argc, const char **argv, const char **envp) {\n int v3;\n int v4;\n int v5;\n struct sockaddr s[3];\n unsigned long long v7;\n v7 = __readfsqword(40u);\n memset(s, 0, 12uLL);\n *(uint32_t *)&s[0].sa_data[6] = AF_INET;\n *(uint32_t *)&s[0].sa_data[2] = htonl(INADDR_ANY);\n LOWORD(v3) = htons(6970u);\n *(uint32_t *)&s[0].sa_family = v3;\n v4 = socket(AF_INET, SOCK_STREAM, 0);\n bind(v4, s, 12u);\n listen(v4, 10);\n v5 = accept(v4, 0LL, 0LL);\n while (1) {\n recv(v5, &s[0].sa_data[10], 30uLL, 0);\n parse_gesture(&s[0].sa_data[10]);\n }\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "int main() {\n unsigned char var1[30];\n struct type1 var2;\n memset(&var2, 0, sizeof(struct type1));\n var2.field1 = var3;\n var2.field2.field3 = htonl(var4);\n var2.field4 = htons(6970);\n int var5 = socket(var3, var6, 0);\n bind(var5, (struct type2 *)&var2, sizeof(var2));\n listen(var5, 10);\n int var7 = accept(var5, (struct type2 *)NULL, NULL);\n while (1) {\n recv(var7, var1, 30, 0);\n parse_gesture(var1);\n }\n func1(var7);\n func1(var5);\n return 0;\n}", "style": "rule"}, "extra_info": {"index": 70608, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_2__ TYPE_1__ ;\n\n/* Type definitions */\ntypedef int /*<<< orphan*/ var2 ;\nstruct type2 {int dummy; } ;\nstruct TYPE_2__ {int /*<<< orphan*/ field3; } ;\nstruct type1 {int /*<<< orphan*/ field4; TYPE_1__ field2; int /*<<< orphan*/ field1; } ;\n\n/* Variables and functions */\n int accept (int,struct type2*,int /*<<< orphan*/ *) ; \n int /*<<< orphan*/ bind (int,struct type2*,int) ; \n int /*<<< orphan*/ func1 (int) ; \n int /*<<< orphan*/ htonl (int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ htons (int) ; \n int /*<<< orphan*/ listen (int,int) ; \n int /*<<< orphan*/ memset (struct type1*,int /*<<< orphan*/ ,int) ; \n int /*<<< orphan*/ parse_gesture (unsigned char*) ; \n int /*<<< orphan*/ recv (int,unsigned char*,int,int /*<<< orphan*/ ) ; \n int socket (int /*<<< orphan*/ ,int /*<<< orphan*/ ,int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ var3 ; \n int /*<<< orphan*/ var4 ; \n int /*<<< orphan*/ var6 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long buffer_path_simplify(char **a1, char **a2) {\n long long v3;\n char *v4;\n char *v5;\n char i;\n char *v7;\n char *v8;\n char v9;\n unsigned long long v10;\n char v11;\n long long v12;\n int v14;\n if (a1 && a2) {\n if (!buffer_string_is_empty(a2)) goto LABEL_4;\n return buffer_string_prepare_copy(a1, 0LL);\n }\n log_failed_assert(\n \"/scratch/repos/new/home/jordi_armengol_estape/c-scraper/outputs/\"\n \"2022-01-22/02-19-57/repos/PatchyFog/lighttpd1.4-mbed\"\n \"tls/refs/heads/master/src/buffer.c\",\n 889LL, \"assertion failed: NULL != dest && NULL != src\");\n if (buffer_string_is_empty(a2)) return buffer_string_prepare_copy(a1, 0LL);\nLABEL_4:\n if ((*a2)[*((int *)a2 + 2) - 1]) {\n log_failed_assert(\n \"/scratch/repos/new/home/jordi_armengol_estape/c-scraper/outputs/\"\n \"2022-01-22/02-19-57/repos/PatchyFog/lighttpd1.4-mb\"\n \"edtls/refs/heads/master/src/buffer.c\",\n 896LL, \"assertion failed: '\\\\0' == src->ptr[src->used-1]\");\n if (a1 != a2) goto LABEL_6;\n LABEL_36:\n buffer_string_prepare_append(a1, 1LL);\n goto LABEL_7;\n }\n if (a1 == a2) goto LABEL_36;\nLABEL_6:\n v3 = buffer_string_length(a2);\n buffer_string_prepare_copy(a1, v3 + 1);\nLABEL_7:\n v4 = *a2;\n v5 = *a1;\n for (i = **a2; i == 32; ++v4) i = v4[1];\n v7 = v4 + 1;\n if (i == 47) {\n v8 = *a1;\n v9 = 0;\n } else {\n *v5 = 47;\n v8 = v5 + 1;\n if (!i) {\n v12 = 1LL;\n return buffer_string_set_length(a1, v12);\n }\n v9 = 47;\n }\n v10 = (unsigned long long)v5;\n while (1) {\n v11 = *v7;\n *v8++ = i;\n ++v7;\n if (v11 != 47 && v11) goto LABEL_13;\n if (&v8[-v10] != (uint8_t *)buffer_path_simplify + 3 || v9 != 46) break;\n if (i == 46) {\n LODWORD(v8) = v10 + 1;\n if ((unsigned long long)v5 < v10) {\n v8 = (char *)(v10 - 1);\n if ((unsigned long long)v5 < v10 - 1) {\n while (1) {\n if (*v8 == 47) {\n v10 = (unsigned long long)v8;\n LODWORD(v8) = (uint32_t)v8 + 1;\n goto LABEL_27;\n }\n if (v5 == v8 - 1) break;\n --v8;\n }\n v10 = (unsigned long long)v5;\n } else {\n v14 = v10--;\n LODWORD(v8) = v14;\n }\n }\n LABEL_27:\n if (!v11) goto LABEL_24;\n goto LABEL_28;\n }\n LABEL_19:\n if (!v11) goto LABEL_24;\n v10 = (unsigned long long)v8;\n LABEL_13:\n v9 = i;\n i = v11;\n }\n if (&v8[-v10] != (uint8_t *)buffer_path_simplify + 1 && (v9 != 47 || i != 46))\n goto LABEL_19;\n if (v11) {\n LABEL_28:\n v8 = (char *)v10;\n goto LABEL_13;\n }\n LODWORD(v8) = v10 + 1;\nLABEL_24:\n v12 = (unsigned int)((uint32_t)v8 - (uint32_t)v5);\n return buffer_string_set_length(a1, v12);\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "void buffer_path_simplify(type1 *var1, type1 *var2) {\n char var3, var4, var5;\n char *var6, *var7, *var8, *var9;\n do {\n if (!(NULL != var1 && NULL != var2))\n log_failed_assert(\n \"/scratch/repos/new/home/jordi_armengol_estape/c-scraper/outputs/\"\n \"2022-01-22/02-19-57/repos/PatchyFog/lighttpd1.4-mbedtls/refs/heads/\"\n \"master/src/buffer.c\",\n 889,\n \"assertion failed: \"\n \"NULL != dest && NULL != src\");\n } while (0);\n if (buffer_string_is_empty(var2)) {\n buffer_string_prepare_copy(var1, 0);\n return;\n }\n do {\n if (!('\\0' == var2->field1[var2->field2 - 1]))\n log_failed_assert(\n \"/scratch/repos/new/home/jordi_armengol_estape/c-scraper/outputs/\"\n \"2022-01-22/02-19-57/repos/PatchyFog/lighttpd1.4-mbedtls/refs/heads/\"\n \"master/src/buffer.c\",\n 896,\n \"assertion failed: \"\n \"'\\\\0' == src->ptr[src->used-1]\");\n } while (0);\n if (var2 == var1) {\n buffer_string_prepare_append(var1, 1);\n } else {\n buffer_string_prepare_copy(var1, buffer_string_length(var2) + 1);\n }\n# 915 \"/scratch/repos/new/home/jordi_armengol_estape/c-scraper/outputs/2022-01-22/02-19-57/repos/PatchyFog/lighttpd1.4-mbedtls/refs/heads/master/src/buffer.c\"\n var8 = var2->field1;\n var6 = var1->field1;\n var9 = var1->field1;\n var7 = var1->field1;\n while (*var8 == ' ') {\n var8++;\n }\n var4 = 0;\n var3 = *(var8++);\n if (var3 != '/') {\n var4 = '/';\n *(var9++) = '/';\n }\n while (var3 != '\\0') {\n var5 = var4;\n var4 = var3;\n var3 = *var8;\n *var9 = var4;\n var9++;\n var8++;\n if (var3 == '/' || var3 == '\\0') {\n const size_t var10 = var9 - var7;\n if (var10 == 3 && var5 == '.' && var4 == '.') {\n var9 = var7;\n if (var9 > var6) {\n var9--;\n while (var9 > var6 && *var9 != '/') var9--;\n }\n if (var3 == '\\0') var9++;\n } else if (var10 == 1 || (var5 == '/' && var4 == '.')) {\n var9 = var7;\n if (var3 == '\\0') var9++;\n }\n var7 = var9;\n }\n }\n buffer_string_set_length(var1, var9 - var6);\n}", "style": "rule"}, "extra_info": {"index": 36943, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_9__ TYPE_1__ ;\n\n/* Type definitions */\nstruct TYPE_9__ {char* field1; int field2; } ;\ntypedef TYPE_1__ type1 ;\n\n/* Variables and functions */\n scalar_t__ buffer_string_is_empty (TYPE_1__*) ; \n scalar_t__ buffer_string_length (TYPE_1__*) ; \n int /*<<< orphan*/ buffer_string_prepare_append (TYPE_1__*,int) ; \n int /*<<< orphan*/ buffer_string_prepare_copy (TYPE_1__*,scalar_t__) ; \n int /*<<< orphan*/ buffer_string_set_length (TYPE_1__*,int) ; \n int /*<<< orphan*/ log_failed_assert (char*,int,char*) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long bta_ag_sdp_find_attr(long long a1, int a2) {\n int v3;\n uint64_t *v4;\n long long ServiceInDb;\n long long v6;\n long long v7;\n long long AttributeInRec;\n unsigned long long v9;\n v9 = __readfsqword(40u);\n ServiceInDb = 0LL;\n v7 = FALSE;\n if ((a2 & BTA_HFP_SERVICE_MASK) != 0) {\n v6 = UUID_SERVCLASS_HF_HANDSFREE;\n *(uint32_t *)a1 = HFP_VERSION_1_1;\n LABEL_23:\n while (TRUE) {\n ServiceInDb =\n SDP_FindServiceInDb(*(unsigned int *)(a1 + 32), v6, ServiceInDb);\n if (!ServiceInDb) {\n if (v6 != UUID_SERVCLASS_HEADSET_HS) break;\n v6 = UUID_SERVCLASS_HEADSET;\n ServiceInDb = SDP_FindServiceInDb(*(unsigned int *)(a1 + 32),\n UUID_SERVCLASS_HEADSET, ServiceInDb);\n if (!ServiceInDb) break;\n }\n if (*(uint64_t *)(a1 + 8) != BTA_AG_INT) goto LABEL_13;\n if (SDP_FindProtocolListElemInRec(\n ServiceInDb, (unsigned int)UUID_PROTOCOL_RFCOMM, &v4)) {\n *(uint64_t *)(a1 + 24) = *v4;\n LABEL_13:\n SDP_FindProfileVersionInRec(ServiceInDb, v6, a1);\n if ((a2 & BTA_HFP_SERVICE_MASK) != 0) {\n AttributeInRec = SDP_FindAttributeInRec(\n ServiceInDb, (unsigned int)ATTR_ID_SUPPORTED_FEATURES);\n if (AttributeInRec) {\n if (!*(uint32_t *)(a1 + 16))\n *(uint32_t *)(a1 + 16) = *(uint32_t *)(AttributeInRec + 8);\n }\n } else {\n AttributeInRec = SDP_FindAttributeInRec(\n ServiceInDb, (unsigned int)ATTR_ID_REMOTE_AUDIO_VOLUME_CONTROL);\n if (AttributeInRec) {\n if (*(uint64_t *)AttributeInRec)\n v3 = BTA_AG_PEER_FEAT_VOL | *(uint32_t *)(a1 + 16);\n else\n v3 = ~BTA_AG_PEER_FEAT_VOL & *(uint32_t *)(a1 + 16);\n *(uint32_t *)(a1 + 16) = v3;\n }\n }\n return TRUE;\n }\n }\n return v7;\n } else {\n if ((a2 & BTA_HSP_SERVICE_MASK) != 0 &&\n *(uint64_t *)(a1 + 8) == BTA_AG_INT) {\n v6 = UUID_SERVCLASS_HEADSET_HS;\n *(uint32_t *)a1 = 256;\n goto LABEL_23;\n }\n return v7;\n }\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "type1 bta_ag_sdp_find_attr(type2 *var1, type3 var2) {\n type4 *var3 = NULL;\n type5 *var4;\n type6 var5;\n type7 var6;\n type1 var7 = FALSE;\n if (var2 & var8) {\n var6 = var9;\n var1->field1 = var10;\n } else if (var2 & var11 && var1->field2 == var12) {\n var6 = var13;\n var1->field1 = 0x0100;\n } else {\n return var7;\n }\n while (TRUE) {\n if ((var3 = SDP_FindServiceInDb(var1->field3, var6, var3)) == NULL) {\n if (var6 == var13) {\n var6 = var14;\n if ((var3 = SDP_FindServiceInDb(var1->field3, var6, var3)) == NULL) {\n break;\n }\n } else {\n break;\n }\n }\n if (var1->field2 == var12) {\n if (SDP_FindProtocolListElemInRec(var3, var15, &var5)) {\n var1->field4 = (type8)var5.field5[0];\n } else {\n continue;\n }\n }\n SDP_FindProfileVersionInRec(var3, var6, &var1->field1);\n if (var2 & var8) {\n if ((var4 = SDP_FindAttributeInRec(var3, var16)) != NULL) {\n if (var1->field6 == 0) var1->field6 = var4->field7.field8.field9;\n }\n } else {\n if ((var4 = SDP_FindAttributeInRec(var3, var17)) != NULL) {\n if (var4->field7.field8.field10) {\n var1->field6 |= var18;\n } else {\n var1->field6 &= ~var18;\n }\n }\n }\n var7 = TRUE;\n break;\n }\n return var7;\n}", "style": "rule"}, "extra_info": {"index": 50289, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_13__ TYPE_5__ ;\ntypedef struct TYPE_12__ TYPE_4__ ;\ntypedef struct TYPE_11__ TYPE_3__ ;\ntypedef struct TYPE_10__ TYPE_2__ ;\ntypedef struct TYPE_9__ TYPE_1__ ;\n\n/* Type definitions */\ntypedef scalar_t__ type8 ;\ntypedef scalar_t__ type7 ;\nstruct TYPE_11__ {scalar_t__* field5; } ;\ntypedef TYPE_3__ type6 ;\nstruct TYPE_9__ {scalar_t__ field10; int /*<<< orphan*/ field9; } ;\nstruct TYPE_10__ {TYPE_1__ field8; } ;\nstruct TYPE_12__ {TYPE_2__ field7; } ;\ntypedef TYPE_4__ type5 ;\ntypedef int /*<<< orphan*/ type4 ;\ntypedef int type3 ;\nstruct TYPE_13__ {int field1; scalar_t__ field2; int /*<<< orphan*/ field6; scalar_t__ field4; int /*<<< orphan*/ field3; } ;\ntypedef TYPE_5__ type2 ;\ntypedef scalar_t__ type1 ;\n\n/* Variables and functions */\n scalar_t__ FALSE ; \n TYPE_4__* SDP_FindAttributeInRec (int /*<<< orphan*/ *,int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ SDP_FindProfileVersionInRec (int /*<<< orphan*/ *,scalar_t__,int*) ; \n scalar_t__ SDP_FindProtocolListElemInRec (int /*<<< orphan*/ *,int /*<<< orphan*/ ,TYPE_3__*) ; \n int /*<<< orphan*/ * SDP_FindServiceInDb (int /*<<< orphan*/ ,scalar_t__,int /*<<< orphan*/ *) ; \n scalar_t__ TRUE ; \n int var10 ; \n int var11 ; \n scalar_t__ var12 ; \n scalar_t__ var13 ; \n scalar_t__ var14 ; \n int /*<<< orphan*/ var15 ; \n int /*<<< orphan*/ var16 ; \n int /*<<< orphan*/ var17 ; \n int /*<<< orphan*/ var18 ; \n int var8 ; \n scalar_t__ var9 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nchar *cin_com_set_string(const char *a1, const char *a2) {\n unsigned int v2;\n const char *size_4;\n char *dest;\n if (a1) {\n size_4 = a1;\n v2 = strlen(a1);\n } else {\n size_4 = a2;\n v2 = strlen(a2);\n }\n dest = (char *)malloc(v2);\n if (!dest) return 0LL;\n strcpy(dest, size_4);\n return dest;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "char *cin_com_set_string(char *var1, char *var2) {\n char *var3, *var4;\n if (var1 != NULL) {\n var3 = var1;\n } else {\n var3 = var2;\n }\n int var5;\n var5 = strlen(var3);\n var4 = malloc(sizeof(char) * var5);\n if (var4 == NULL) {\n return NULL;\n }\n strcpy(var4, var3);\n return var4;\n}", "style": "rule"}, "extra_info": {"index": 30681, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\n\n/* Variables and functions */\n char* malloc (int) ; \n int /*<<< orphan*/ strcpy (char*,char*) ; \n int strlen (char*) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long b43legacy_pio_free(uint64_t *a1) {\n long long result;\n result = b43legacy_using_pio();\n if ((uint32_t)result) {\n b43legacy_destroy_pioqueue(a1[3]);\n a1[3] = 0LL;\n b43legacy_destroy_pioqueue(a1[2]);\n a1[2] = 0LL;\n b43legacy_destroy_pioqueue(a1[1]);\n a1[1] = 0LL;\n result = b43legacy_destroy_pioqueue(*a1);\n *a1 = 0LL;\n }\n return result;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "void b43legacy_pio_free(struct type1 *var1) {\n struct type2 *var2;\n if (!b43legacy_using_pio(var1)) return;\n var2 = &var1->field1;\n b43legacy_destroy_pioqueue(var2->field2);\n var2->field2 = NULL;\n b43legacy_destroy_pioqueue(var2->field3);\n var2->field3 = NULL;\n b43legacy_destroy_pioqueue(var2->field4);\n var2->field4 = NULL;\n b43legacy_destroy_pioqueue(var2->field5);\n var2->field5 = NULL;\n}", "style": "rule"}, "extra_info": {"index": 82390, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\nstruct type2 {int /*<<< orphan*/ * field5; int /*<<< orphan*/ * field4; int /*<<< orphan*/ * field3; int /*<<< orphan*/ * field2; } ;\nstruct type1 {struct type2 field1; } ;\n\n/* Variables and functions */\n int /*<<< orphan*/ b43legacy_destroy_pioqueue (int /*<<< orphan*/ *) ; \n int /*<<< orphan*/ b43legacy_using_pio (struct type1*) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long test_uncovered_buffer(long long a1) {\n long long top;\n uint64_t v3[5];\n v3[1] = __readfsqword(40u);\n duk_push_dynamic_buffer(a1, 64LL);\n duk_eval_string(\n a1,\n \"(function (plain_buffer) {\\n var b = plain_buffer.buffer;\\n \"\n \"return new Uint32Array(b).subarray(1,5);\\n})\");\n duk_dup(a1, 0LL);\n duk_call(a1, 1LL);\n v3[0] = 3735928559LL;\n if (duk_get_buffer_data_default(a1, 4294967295LL, v3, 305419896LL,\n 2271560481LL))\n printf(\"p is not NULL, sz=%lu\\n\", v3[0]);\n else\n puts(\"p is NULL\");\n duk_resize_buffer(a1, 0LL, 20LL);\n v3[0] = 3735928559LL;\n if (duk_get_buffer_data_default(a1, 4294967295LL, v3, 305419896LL,\n 2271560481LL))\n printf(\"p is not NULL, sz=%lu\\n\", v3[0]);\n else\n puts(\"p is NULL\");\n duk_resize_buffer(a1, 0LL, 19LL);\n v3[0] = 3735928559LL;\n if (duk_get_buffer_data_default(a1, 4294967295LL, v3, 305419896LL,\n 2271560481LL))\n printf(\"p is not NULL, sz=%lu\\n\", v3[0]);\n else\n puts(\"p is NULL\");\n top = duk_get_top(a1);\n printf(\"final top: %ld\\n\", top);\n return 0LL;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "static type1 test_uncovered_buffer(type2 *var1, void *var2) {\n unsigned char *var3;\n type3 var4;\n (void)var2;\n duk_push_dynamic_buffer(var1, 64);\n duk_eval_string(var1,\n \"(function (plain_buffer) {\\n\"\n \" var b = plain_buffer.buffer;\\n\"\n \" return new Uint32Array(b).subarray(1,5);\\n\"\n \"})\");\n duk_dup(var1, 0);\n duk_call(var1, 1);\n var4 = (type3)0xdeadbeefUL;\n var3 = duk_get_buffer_data_default(var1, -1, &var4, (void *)0x12345678UL,\n (type3)0x87654321UL);\n if (var3) {\n printf(\"p is not NULL, sz=%lu\\n\", (unsigned long)var4);\n } else {\n printf(\"p is NULL\\n\");\n }\n duk_resize_buffer(var1, 0, 20);\n var4 = (type3)0xdeadbeefUL;\n var3 = duk_get_buffer_data_default(var1, -1, &var4, (void *)0x12345678UL,\n (type3)0x87654321UL);\n if (var3) {\n printf(\"p is not NULL, sz=%lu\\n\", (unsigned long)var4);\n } else {\n printf(\"p is NULL\\n\");\n }\n duk_resize_buffer(var1, 0, 19);\n var4 = (type3)0xdeadbeefUL;\n var3 = duk_get_buffer_data_default(var1, -1, &var4, (void *)0x12345678UL,\n (type3)0x87654321UL);\n if (var3) {\n printf(\"p is not NULL, sz=%lu\\n\", (unsigned long)var4);\n } else {\n printf(\"p is NULL\\n\");\n }\n printf(\"final top: %ld\\n\", (long)duk_get_top(var1));\n return 0;\n}", "style": "rule"}, "extra_info": {"index": 18697, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\ntypedef scalar_t__ type3 ;\ntypedef int /*<<< orphan*/ type2 ;\ntypedef int /*<<< orphan*/ type1 ;\n\n/* Variables and functions */\n int /*<<< orphan*/ duk_call (int /*<<< orphan*/ *,int) ; \n int /*<<< orphan*/ duk_dup (int /*<<< orphan*/ *,int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ duk_eval_string (int /*<<< orphan*/ *,char*) ; \n unsigned char* duk_get_buffer_data_default (int /*<<< orphan*/ *,int,scalar_t__*,void*,scalar_t__) ; \n scalar_t__ duk_get_top (int /*<<< orphan*/ *) ; \n int /*<<< orphan*/ duk_push_dynamic_buffer (int /*<<< orphan*/ *,int) ; \n int /*<<< orphan*/ duk_resize_buffer (int /*<<< orphan*/ *,int /*<<< orphan*/ ,int) ; \n int /*<<< orphan*/ printf (char*,...) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long match_string(long long a1, unsigned long long a2, const char *a3) {\n unsigned int i;\n char *s1;\n for (i = 0; a2 > (int)i; ++i) {\n s1 = *(char **)(8LL * (int)i + a1);\n if (!s1) break;\n if (!strcmp(s1, a3)) return i;\n }\n return (unsigned int)-EINVAL;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "int match_string(const char *const *var1, size_t var2, const char *var3) {\n int var4;\n const char *var5;\n for (var4 = 0; var4 < var2; var4++) {\n var5 = var1[var4];\n if (!var5) break;\n if (!strcmp(var5, var3)) return var4;\n }\n return -var6;\n}", "style": "rule"}, "extra_info": {"index": 93423, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\n\n/* Variables and functions */\n int /*<<< orphan*/ strcmp (char const*,char const*) ; \n int var6 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nvoid __noreturn set_lookup_docids(uint64_t *a1, long long a2, long long a3,\n long long a4, double a5) {\n double v5;\n int v6;\n int v7;\n long long v8;\n double v9;\n long long v10;\n double v11;\n double v12;\n int v13;\n double v14;\n char v15;\n char v16;\n long long v17;\n double v18;\n long long v19;\n double v20;\n char v21;\n char v22;\n double v23;\n double v24;\n long long v25;\n long long v26;\n long long v27;\n char v30;\n *a1 = a3;\n a1[1] = a4;\n v5 = log2(a5);\n ceil(v5);\n v7 = v6;\n v8 = a1[1];\n if (v8 < 0) {\n v10 = a1[1] & 1LL | ((unsigned long long)v8 >> 1);\n v9 = (double)(int)v10 + (double)(int)v10;\n } else {\n v9 = (double)(int)v8;\n }\n v11 = log2(v9);\n v12 = ceil(v11);\n if (v7 - v13 <= 0) {\n v22 = 1;\n } else {\n v14 = log2(v12);\n ceil(v14);\n v16 = v15;\n v17 = a1[1];\n if (v17 < 0) {\n v19 = a1[1] & 1LL | ((unsigned long long)v17 >> 1);\n v18 = (double)(int)v19 + (double)(int)v19;\n } else {\n v18 = (double)(int)v17;\n }\n v20 = log2(v18);\n v12 = ceil(v20);\n v22 = v16 - v21;\n }\n v30 = v22;\n v23 = log2(v12);\n v24 = ceil(v23);\n a1[2] = malloc(4 * ((unsigned int)(1LL << v30) + 1));\n assert(a1[2], a2, a1, v25, v26, v27, v24, a4, a3, a2);\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "void set_lookup_docids(type1 *var1, type2 *var2, uint32_t *var3, size_t var4) {\n int var5;\n int var6;\n size_t var7;\n size_t var8;\n size_t var9;\n uint32_t var10 = var2->field1;\n var1->field2 = var3;\n var1->field3 = var4;\n unsigned int var11 =\n (((1 > ((int)ceil(log2(((1 > var10) ? 1 : var10)))) -\n (int)ceil(log2(var10 * (double)16 / var1->field3)))\n ? 1\n : ((int)ceil(log2(((1 > var10) ? 1 : var10)))) -\n (int)ceil(log2(var10 * (double)16 / var1->field3))));\n var6 = (((int)ceil(log2(((1 > var10) ? 1 : var10)))) - var11);\n var7 = (1L << var11);\n var1->field4 = malloc(sizeof(uint32_t) * (var7 + 1));\n assert(var1->field4);\n var8 = 0;\n var9 = 0;\n for (var5 = 0; var5 < var7; var5++) {\n while (var8 < var1->field3 && var1->field2[var8] >> var6 == var5) {\n var8++;\n }\n var1->field4[var5] = var9;\n var9 = var8;\n }\n var1->field4[var7] = var4;\n}", "style": "rule"}, "extra_info": {"index": 80846, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_6__ TYPE_2__ ;\ntypedef struct TYPE_5__ TYPE_1__ ;\n\n/* Type definitions */\ntypedef int uint32_t ;\nstruct TYPE_5__ {int field1; } ;\ntypedef TYPE_1__ type2 ;\nstruct TYPE_6__ {int* field2; size_t field3; size_t* field4; } ;\ntypedef TYPE_2__ type1 ;\n\n/* Variables and functions */\n int /*<<< orphan*/ assert (size_t*) ; \n scalar_t__ ceil (int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ log2 (int) ; \n size_t* malloc (int) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nint print_array(int *a1, int a2) {\n int *v3;\n int v4;\n v3 = a1;\n printf(\"Array : \");\n if (a2 > 0) {\n do {\n v4 = *v3++;\n printf(\"%d\\t\", v4);\n } while (v3 != &a1[a2 - 1 + 1]);\n }\n return putchar(10);\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "void print_array(int var1[], int var2) {\n int var3;\n printf(\"Array : \");\n for (var3 = 0; var3 < var2; var3++) printf(\"%d\\t\", var1[var3]);\n printf(\"\\n\");\n}", "style": "rule"}, "extra_info": {"index": 43596, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\n\n/* Variables and functions */\n int /*<<< orphan*/ printf (char*,...) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long TapeRewind() {\n *((uint64_t *)&tape + 13) = 0LL;\n *((uint64_t *)&tape + 12) = 0LL;\n *((uint64_t *)&tape + 11) = 0LL;\n *((uint64_t *)&tape + 10) = 0LL;\n *((uint64_t *)&tape + 9) = 0LL;\n *((uint64_t *)&tape + 8) = 0LL;\n *((uint64_t *)&tape + 7) = 0LL;\n *((uint64_t *)&tape + 6) = 0LL;\n *(&tape + 10) = global != 0;\n *((uint64_t *)&tape + 4) = 0LL;\n *((uint64_t *)&tape + 3) = 0LL;\n *((uint64_t *)&tape + 2) = 0LL;\n tape = -1;\n *((uint64_t *)&tape + 1) = 0LL;\n return InitRND((unsigned int)*(&tape + 1));\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "static void TapeRewind() {\n var1.field1 = 0;\n var1.field2 = 0;\n var1.field3 = 0;\n var1.field4 = 0;\n var1.field5 = 0;\n var1.field6 = 0;\n var1.field7 = 0;\n var1.field8 = 0;\n var1.field9 = (var2.field10 != NULL);\n var1.field11 = 0;\n var1.field12 = 0;\n var1.field13 = 0;\n var1.field14 = -1;\n var1.field15 = 0;\n InitRND(var1.field16);\n}", "style": "rule"}, "extra_info": {"index": 48597, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_4__ TYPE_2__ ;\ntypedef struct TYPE_3__ TYPE_1__ ;\n\n/* Type definitions */\nstruct TYPE_4__ {int field14; int /*<<< orphan*/ field16; scalar_t__ field15; scalar_t__ field13; scalar_t__ field12; scalar_t__ field11; int /*<<< orphan*/ field9; scalar_t__ field8; scalar_t__ field7; scalar_t__ field6; scalar_t__ field5; scalar_t__ field4; scalar_t__ field3; scalar_t__ field2; scalar_t__ field1; } ;\nstruct TYPE_3__ {int /*<<< orphan*/ * field10; } ;\n\n/* Variables and functions */\n int /*<<< orphan*/ InitRND (int /*<<< orphan*/ ) ; \n TYPE_2__ var1 ; \n TYPE_1__ var2 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long from_oct(int a1, unsigned char *a2) {\n long long v4;\n unsigned int v5;\n unsigned char *v6;\n unsigned char v7;\n unsigned char v8;\n long long v10;\n while (1) {\n LODWORD(v4) = isspace(*a2);\n if (!v4) break;\n --a1;\n ++a2;\n if (a1 <= 0) return 4294967295LL;\n }\n if (a1 <= 0) return 0;\n v5 = 0;\n v6 = &a2[a1];\n while (1) {\n v7 = *a2;\n v8 = *a2 - 48;\n if (v8 > 7u) break;\n ++a2;\n v5 = (char)v8 | (8 * v5);\n if (v6 == a2) return v5;\n }\n if (!v7) return v5;\n LODWORD(v10) = isspace(v7);\n if (v10) return v5;\n return 4294967295LL;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "static int from_oct(int var1, const char *var2) {\n int var3;\n while (isspace((unsigned char)*var2)) {\n var2++;\n if (--var1 <= 0) return -1;\n }\n var3 = 0;\n while (var1 > 0 && (((*var2) >= '0') && ((*var2) <= '7'))) {\n var3 = (var3 << 3) | (*var2++ - '0');\n --var1;\n }\n if (var1 > 0 && *var2 && !isspace((unsigned char)*var2)) return -1;\n return var3;\n}", "style": "rule"}, "extra_info": {"index": 104800, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\n\n/* Variables and functions */\n scalar_t__ isspace (unsigned char) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long read_data_ascii_mmap(char *a1, uint8_t *a2, unsigned long long a3,\n unsigned long long a4, uint64_t *a5) {\n int i;\n int v10;\n int v11;\n int v12;\n int v13;\n uint8_t *v14;\n int *v16;\n v11 = 0;\n v16 = (int *)pthread_getspecific(thread_key);\n v12 = *v16;\n v13 = v16[1];\n v14 = a2;\n memset(a2, 0, (unsigned int)a3);\n for (i = 0; a3 > i; ++i) {\n if (v12) {\n if (v13 == 10)\n LOBYTE(v10) = 10;\n else\n LOBYTE(v10) = 0;\n v12 = 0;\n } else {\n if (a4 <= v11) break;\n v10 = *a1++;\n if (v10 == 10 || v10 == 13) {\n v13 = v10;\n LOBYTE(v10) = 13;\n v12 = 1;\n }\n ++v11;\n }\n *v14++ = v10;\n }\n *v16 = v12;\n v16[1] = v13;\n *a5 = v11;\n return i;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "size_t read_data_ascii_mmap(char *var1, char *var2, size_t var3, size_t var4,\n size_t *var5) {\n char *var6;\n char *var7;\n int var8, var9, var10 = 0;\n type1 *var11;\n var11 = pthread_getspecific(var12);\n int var13 = var11->field1;\n int var14 = var11->field2;\n var6 = var2;\n var7 = var1;\n memset(var2, '\\0', sizeof(char) * var3);\n for (var8 = 0; var8 < var3; var8++) {\n if (var13) {\n if (var14 == '\\n')\n var9 = '\\n';\n else\n var9 = '\\0';\n var13 = 0;\n } else {\n if (var10 >= var4) {\n break;\n }\n var9 = *var7;\n var7++;\n if (var9 == '\\n' || var9 == '\\r') {\n var14 = var9;\n var9 = '\\r';\n var13 = 1;\n }\n var10++;\n }\n *var6 = var9;\n var6++;\n }\n var11->field1 = var13;\n var11->field2 = var14;\n *var5 = var10;\n return var8;\n}", "style": "rule"}, "extra_info": {"index": 46356, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_3__ TYPE_1__ ;\n\n/* Type definitions */\nstruct TYPE_3__ {int field1; int field2; } ;\ntypedef TYPE_1__ type1 ;\n\n/* Variables and functions */\n int /*<<< orphan*/ memset (char*,char,int) ; \n TYPE_1__* pthread_getspecific (int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ var12 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long flying_rc_track_flat_to_right_bank(long long a1, long long a2, int a3,\n long long a4, long long a5) {\n unsigned int v7;\n unsigned int v9;\n if (!(unsigned int)track_element_is_inverted(a5)) {\n if (a3 == 2) {\n sub_98197C_rotated(\n 2LL, *(uint32_t *)(gTrackColours + 4 * SCHEME_TRACK) | 17162u, 0LL,\n 0LL, 32LL, 20LL, 3LL, a4, 0LL, 6LL, a4);\n sub_98197C_rotated(\n 2LL, *(uint32_t *)(gTrackColours + 4 * SCHEME_TRACK) | 17166u, 0LL,\n 0LL, 32LL, 1LL, 26LL, a4, 0LL, 27LL, a4);\n } else if (a3 > 2) {\n if (a3 == 3) {\n sub_98197C_rotated(\n 3LL, *(uint32_t *)(gTrackColours + 4 * SCHEME_TRACK) | 17163u, 0LL,\n 0LL, 32LL, 20LL, 3LL, a4, 0LL, 6LL, a4);\n sub_98197C_rotated(\n 3LL, *(uint32_t *)(gTrackColours + 4 * SCHEME_TRACK) | 17167u, 0LL,\n 0LL, 32LL, 1LL, 26LL, a4, 0LL, 27LL, a4);\n if (!track_paint_util_should_paint_supports(\n (unsigned int)gPaintMapPosition))\n goto LABEL_8;\n goto LABEL_12;\n }\n } else if (a3) {\n if (a3 == 1)\n sub_98197C_rotated(\n 1LL, *(uint32_t *)(gTrackColours + 4 * SCHEME_TRACK) | 17161u, 0LL,\n 0LL, 32LL, 20LL, 3LL, a4, 0LL, 6LL, a4);\n } else {\n sub_98197C_rotated(\n 0LL, *(uint32_t *)(gTrackColours + 4 * SCHEME_TRACK) | 17160u, 0LL,\n 0LL, 32LL, 20LL, 3LL, a4, 0LL, 6LL, a4);\n }\n if (!track_paint_util_should_paint_supports(\n (unsigned int)gPaintMapPosition)) {\n LABEL_8:\n paint_util_push_tunnel_rotated((unsigned int)a3, a4,\n (unsigned int)TUNNEL_6);\n v7 = paint_util_rotate_segments(\n SEGMENT_D0 | SEGMENT_CC | (unsigned int)SEGMENT_C4, (unsigned int)a3);\n paint_util_set_segment_support_height(v7, 65535LL, 0LL);\n return paint_util_set_general_support_height(a4 + 32, 32LL);\n }\n LABEL_12:\n metal_a_supports_paint_setup(\n (unsigned int)METAL_SUPPORTS_TUBES_INVERTED, 4LL, 0LL, a4,\n *(unsigned int *)(gTrackColours + 4 * SCHEME_SUPPORTS));\n goto LABEL_8;\n }\n if (a3 == 2) {\n sub_98197C_rotated(2LL,\n *(uint32_t *)(gTrackColours + 4 * SCHEME_TRACK) | 27275u,\n 0LL, 0LL, 32LL, 20LL, 3LL, a4 + 24, 0LL, 6LL, a4 + 22);\n } else if (a3 > 2) {\n if (a3 == 3)\n sub_98197C_rotated(\n 3LL, *(uint32_t *)(gTrackColours + 4 * SCHEME_TRACK) | 27276u, 0LL,\n 0LL, 32LL, 20LL, 3LL, a4 + 24, 0LL, 6LL, a4 + 22);\n } else if (a3) {\n if (a3 == 1)\n sub_98197C_rotated(\n 1LL, *(uint32_t *)(gTrackColours + 4 * SCHEME_TRACK) | 27274u, 0LL,\n 0LL, 32LL, 20LL, 3LL, a4 + 24, 0LL, 6LL, a4 + 22);\n } else {\n sub_98197C_rotated(0LL,\n *(uint32_t *)(gTrackColours + 4 * SCHEME_TRACK) | 27273u,\n 0LL, 0LL, 32LL, 20LL, 3LL, a4 + 24, 0LL, 6LL, a4 + 22);\n }\n v9 = paint_util_rotate_segments(SEGMENT_D0 | SEGMENT_CC | SEGMENT_C8 |\n SEGMENT_C4 | SEGMENT_B8 |\n (unsigned int)SEGMENT_B4,\n (unsigned int)a3);\n paint_util_set_segment_support_height(v9, 65535LL, 0LL);\n if (track_paint_util_should_paint_supports((unsigned int)gPaintMapPosition))\n metal_a_supports_paint_setup(\n (unsigned int)METAL_SUPPORTS_TUBES_INVERTED, 4LL, 0LL, a4 + 39,\n *(unsigned int *)(gTrackColours + 4 * SCHEME_SUPPORTS));\n paint_util_push_tunnel_rotated((unsigned int)a3, a4, (unsigned int)TUNNEL_6);\n return paint_util_set_general_support_height(a4 + 32, 32LL);\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "static void flying_rc_track_flat_to_right_bank(type1 var1, type1 var2,\n type1 var3, type2 var4,\n type3* var5) {\n if (!track_element_is_inverted(var5)) {\n switch (var3) {\n case 0:\n sub_98197C_rotated(var3, var6[var7] | 17160, 0, 0, 32, 20, 3, var4, 0,\n 6, var4);\n break;\n case 1:\n sub_98197C_rotated(var3, var6[var7] | 17161, 0, 0, 32, 20, 3, var4, 0,\n 6, var4);\n break;\n case 2:\n sub_98197C_rotated(var3, var6[var7] | 17162, 0, 0, 32, 20, 3, var4, 0,\n 6, var4);\n sub_98197C_rotated(var3, var6[var7] | 17166, 0, 0, 32, 1, 26, var4, 0,\n 27, var4);\n break;\n case 3:\n sub_98197C_rotated(var3, var6[var7] | 17163, 0, 0, 32, 20, 3, var4, 0,\n 6, var4);\n sub_98197C_rotated(var3, var6[var7] | 17167, 0, 0, 32, 1, 26, var4, 0,\n 27, var4);\n break;\n }\n if (track_paint_util_should_paint_supports(var8)) {\n metal_a_supports_paint_setup(var9, 4, 0, var4, var6[var10]);\n }\n paint_util_push_tunnel_rotated(var3, var4, var11);\n paint_util_set_segment_support_height(\n paint_util_rotate_segments(var12 | var13 | var14, var3), 0xFFFF, 0);\n paint_util_set_general_support_height(var4 + 32, 0x20);\n } else {\n switch (var3) {\n case 0:\n sub_98197C_rotated(var3, var6[var7] | 27273, 0, 0, 32, 20, 3, var4 + 24,\n 0, 6, var4 + 22);\n break;\n case 1:\n sub_98197C_rotated(var3, var6[var7] | 27274, 0, 0, 32, 20, 3, var4 + 24,\n 0, 6, var4 + 22);\n break;\n case 2:\n sub_98197C_rotated(var3, var6[var7] | 27275, 0, 0, 32, 20, 3, var4 + 24,\n 0, 6, var4 + 22);\n break;\n case 3:\n sub_98197C_rotated(var3, var6[var7] | 27276, 0, 0, 32, 20, 3, var4 + 24,\n 0, 6, var4 + 22);\n break;\n }\n paint_util_set_segment_support_height(\n paint_util_rotate_segments(\n var15 | var16 | var12 | var17 | var13 | var14, var3),\n 0xFFFF, 0);\n if (track_paint_util_should_paint_supports(var8)) {\n metal_a_supports_paint_setup(var9, 4, 0, var4 + 39, var6[var10]);\n }\n paint_util_push_tunnel_rotated(var3, var4, var11);\n paint_util_set_general_support_height(var4 + 32, 0x20);\n }\n}", "style": "rule"}, "extra_info": {"index": 58067, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\ntypedef int /*<<< orphan*/ type3 ;\ntypedef scalar_t__ type2 ;\ntypedef int type1 ;\n\n/* Variables and functions */\n int /*<<< orphan*/ metal_a_supports_paint_setup (int /*<<< orphan*/ ,int,int /*<<< orphan*/ ,scalar_t__,int) ; \n int /*<<< orphan*/ paint_util_push_tunnel_rotated (int,scalar_t__,int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ paint_util_rotate_segments (int,int) ; \n int /*<<< orphan*/ paint_util_set_general_support_height (scalar_t__,int) ; \n int /*<<< orphan*/ paint_util_set_segment_support_height (int /*<<< orphan*/ ,int,int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ sub_98197C_rotated (int,int,int /*<<< orphan*/ ,int /*<<< orphan*/ ,int,int,int,scalar_t__,int /*<<< orphan*/ ,int,scalar_t__) ; \n int /*<<< orphan*/ track_element_is_inverted (int /*<<< orphan*/ *) ; \n scalar_t__ track_paint_util_should_paint_supports (int /*<<< orphan*/ ) ; \n size_t var10 ; \n int /*<<< orphan*/ var11 ; \n int var12 ; \n int var13 ; \n int var14 ; \n int var15 ; \n int var16 ; \n int var17 ; \n int* var6 ; \n size_t var7 ; \n int /*<<< orphan*/ var8 ; \n int /*<<< orphan*/ var9 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long call_funcdef(long long *a1, unsigned int *a2, unsigned int *a3,\n long long a4, uint32_t *a5) {\n int v7;\n long long scope;\n long long item;\n long long v11;\n long long v12;\n long long v13;\n int item_count;\n unsigned int v15;\n uint64_t *v16;\n long long variable;\n long long v18;\n long long v19;\n uint32_t *v20;\n long long v21;\n uint32_t *v22;\n long long v23;\n bool v24;\n long long v25;\n long long v27;\n v7 = 0;\n scope = create_scope();\n if (a4) {\n while ((int)list_get_item_count(*(unsigned int *)(a4 + 8)) > v7) {\n item = list_get_item(*(unsigned int *)(a4 + 8), (unsigned int)v7);\n LODWORD(v11) = strcmp((const char *)*(unsigned int *)(item + 4), \"this\");\n if (v11) list_insert(*(unsigned int *)(scope + 8), item);\n ++v7;\n }\n }\n stack_push(*((unsigned int *)a1 + 2), scope);\n v12 = *a1;\n v13 = a3[1];\n *a1 = scope;\n v27 = v12;\n item_count = list_get_item_count(v13);\n if (item_count != (unsigned int)list_get_item_count(*a2)) {\n fprintf((FILE *)(unsigned int)stderr, \"argument count mismatch\\n\");\n exit(EXIT_FAILURE);\n }\n v15 = 0;\n while ((int)list_get_item_count(a3[1]) > (int)v15) {\n v16 = (uint64_t *)list_get_item(a3[1], v15);\n variable = create_variable(a1, *v16);\n v18 = *a1;\n v19 = v15++;\n v20 = (uint32_t *)variable;\n *a1 = v27;\n v21 = list_get_item(*a2, v19);\n v22 = (uint32_t *)int_expression(a1, v21);\n *a1 = v18;\n *v20 = *v22;\n }\n if (a5) *(uint32_t *)create_variable(a1, \"this\") = *a5;\n v23 = int_block(a1, *a3);\n v24 = (*(uint64_t *)scope)-- == 1LL;\n v25 = v23;\n if (v24) destroy_scope(scope);\n stack_pop(*((unsigned int *)a1 + 2));\n *a1 = v27;\n return v25;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "static type1* call_funcdef(type2* var1, type3* var2, type4* var3, type5* var4,\n type1* var5) {\n type1* var6 = 0;\n type5* var7 = create_scope(var1);\n if (0 != var4) {\n for (int var8 = 0; var8 < list_get_item_count(var4->field1); var8++) {\n type1* var9 = list_get_item(var4->field1, var8);\n if (strcmp(var9->field2, \"this\") != 0) {\n list_insert(var7->field1, var9);\n }\n }\n }\n stack_push(var1->field3, var7);\n type5* var10 = var1->field4;\n var1->field4 = var7;\n if (list_get_item_count(var3->field5) != list_get_item_count(var2->field6)) {\n fprintf(var11, \"argument count mismatch\\n\");\n exit(var12);\n }\n for (int var13 = 0; var13 < list_get_item_count(var3->field5); var13++) {\n type6* var14 = list_get_item(var3->field5, var13);\n type1* var15 = create_variable(var1, var14->field2);\n type5* var16;\n var16 = var1->field4;\n var1->field4 = var10;\n type1* var17 = int_expression(var1, list_get_item(var2->field6, var13));\n var1->field4 = var16;\n var15->field7 = var17->field7;\n }\n if (var5 != 0) {\n type1* var18 = create_variable(var1, \"this\");\n var18->field7 = var5->field7;\n }\n var6 = int_block(var1, var3->field8);\n var7->field9 -= 1;\n if (var7->field9 == 0) {\n destroy_scope(var7);\n }\n stack_pop(var1->field3);\n var1->field4 = var10;\n return var6;\n}", "style": "rule"}, "extra_info": {"index": 29888, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_29__ TYPE_6__ ;\ntypedef struct TYPE_28__ TYPE_5__ ;\ntypedef struct TYPE_27__ TYPE_4__ ;\ntypedef struct TYPE_26__ TYPE_3__ ;\ntypedef struct TYPE_25__ TYPE_2__ ;\ntypedef struct TYPE_24__ TYPE_1__ ;\n\n/* Type definitions */\nstruct TYPE_24__ {char* field2; } ;\ntypedef TYPE_1__ type6 ;\nstruct TYPE_25__ {scalar_t__ field9; int /*<<< orphan*/ field1; } ;\ntypedef TYPE_2__ type5 ;\nstruct TYPE_26__ {int /*<<< orphan*/ field8; int /*<<< orphan*/ field5; } ;\ntypedef TYPE_3__ type4 ;\nstruct TYPE_27__ {int /*<<< orphan*/ field6; } ;\ntypedef TYPE_4__ type3 ;\nstruct TYPE_28__ {TYPE_2__* field4; int /*<<< orphan*/ field3; } ;\ntypedef TYPE_5__ type2 ;\nstruct TYPE_29__ {int /*<<< orphan*/ field7; int /*<<< orphan*/ field2; } ;\ntypedef TYPE_6__ type1 ;\n\n/* Variables and functions */\n TYPE_2__* create_scope (TYPE_5__*) ; \n TYPE_6__* create_variable (TYPE_5__*,char*) ; \n int /*<<< orphan*/ destroy_scope (TYPE_2__*) ; \n int /*<<< orphan*/ exit (int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ fprintf (int /*<<< orphan*/ ,char*) ; \n TYPE_6__* int_block (TYPE_5__*,int /*<<< orphan*/ ) ; \n TYPE_6__* int_expression (TYPE_5__*,void*) ; \n void* list_get_item (int /*<<< orphan*/ ,int) ; \n int list_get_item_count (int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ list_insert (int /*<<< orphan*/ ,TYPE_6__*) ; \n int /*<<< orphan*/ stack_pop (int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ stack_push (int /*<<< orphan*/ ,TYPE_2__*) ; \n scalar_t__ strcmp (int /*<<< orphan*/ ,char*) ; \n int /*<<< orphan*/ var11 ; \n int /*<<< orphan*/ var12 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nint __noreturn main(int argc, const char **argv, const char **envp) {\n int v3;\n FILE *v4;\n char v5;\n char *v6;\n char *v7;\n char *v8;\n char v9;\n uint8_t v10[1024];\n char v11[1024];\n char s[1032];\n unsigned long long v13;\n v13 = __readfsqword(40u);\n program_name = (long long)*argv;\n while (1) {\n v3 = getopt_long(argc, (char *const *)argv, \"gr:s:v\", &long_options_0, 0LL);\n if (EOF == v3) break;\n if (v3 == 115) {\n sscanf((const char *)(unsigned int)optarg, \"%u\", &point_size);\n } else if (v3 > 115) {\n if (v3 == 118) {\n printf(\"xtotroff (groff) version %s\\n\", (const char *)Version_string);\n exit(0);\n }\n if (v3 == 130) {\n usage((unsigned int)stdout);\n exit(0);\n }\n } else {\n if (v3 == 63) {\n usage((unsigned int)stderr);\n exit(1);\n }\n if (v3 == 114)\n sscanf((const char *)(unsigned int)optarg, \"%u\", &resolution);\n }\n }\n if (argc - optind != 1) {\n usage((unsigned int)stderr);\n exit(1);\n }\n dpy = (unsigned int)XOpenDisplay(0LL);\n if (!dpy) {\n fprintf((FILE *)(unsigned int)stderr, \"Can't connect to the X server.\\n\");\n fprintf((FILE *)(unsigned int)stderr,\n \"Make sure the DISPLAY environment variable is set correctly.\\n\");\n exit(1);\n }\n v4 = fopen(argv[optind], \"r\");\n if (!v4) {\n perror(argv[optind]);\n exit(1);\n }\n while (1) {\n if (!fgets(s, 1024, v4)) exit(0);\n v5 = s[0];\n v6 = v10;\n v7 = s;\n if (!s[0]) break;\n while (1) {\n *v6 = v5;\n if (v5 == 32 || v5 == 9) break;\n v5 = *++v7;\n ++v6;\n if (!v5) {\n *v6 = 0;\n goto LABEL_24;\n }\n }\n *v6 = 0;\n while (v5 == 32 || v5 == 9) {\n v5 = *++v7;\n if (!v5) goto LABEL_24;\n }\n v9 = *v7;\n if (*v7) {\n v8 = v11;\n while (1) {\n *v8 = v9;\n if (v9 == 10) break;\n v9 = *++v7;\n ++v8;\n if (!v9) goto LABEL_25;\n }\n *v8 = 0;\n if (!(unsigned int)MapFont(v11, v10))\n LABEL_26:\n exit(1);\n } else {\n LABEL_24:\n v8 = v11;\n LABEL_25:\n *v8 = 0;\n if (!(unsigned int)MapFont(v11, v10)) goto LABEL_26;\n }\n }\n v10[0] = 0;\n v8 = v11;\n goto LABEL_25;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "int main(int var1, char **var2) {\n char var3[1024];\n char var4[1024];\n char var5[1024];\n char *var6, *var7, var8;\n type1 *var9;\n int var10;\n static const struct type2 var11[] = {{\"help\", var12, 0, var13 + 1},\n {\"version\", var12, 0, 'v'},\n {NULL, 0, 0, 0}};\n var14 = var2[0];\n while ((var10 = getopt_long(var1, var2, \"gr:s:v\", var11, NULL)) != var15) {\n switch (var10) {\n case 'g':\n break;\n case 'r':\n sscanf(var16, \"%u\", &var17);\n break;\n case 's':\n sscanf(var16, \"%u\", &var18);\n break;\n case 'v':\n printf(\"xtotroff (groff) version %s\\n\", var19);\n exit(0);\n break;\n case var13 + 1:\n usage(var20);\n exit(0);\n break;\n case '?':\n usage(var21);\n exit(1);\n break;\n }\n }\n if (var1 - var22 != 1) {\n usage(var21);\n exit(1);\n }\n var23 = XOpenDisplay(0);\n if (!var23) {\n fprintf(var21, \"Can't connect to the X server.\\n\");\n fprintf(var21,\n \"Make sure the DISPLAY environment variable is set correctly.\\n\");\n exit(1);\n }\n var9 = fopen(var2[var22], \"r\");\n if (var9 == NULL) {\n perror(var2[var22]);\n exit(1);\n }\n while (fgets(var5, sizeof(var5), var9)) {\n for (var6 = var5, var7 = var3; *var6; var6++, var7++) {\n var8 = (*var7 = *var6);\n if (var8 == ' ' || var8 == '\\t') break;\n }\n *var7 = '\\0';\n while (*var6 && (*var6 == ' ' || *var6 == '\\t')) ++var6;\n for (var7 = var4; *var6; var6++, var7++)\n if ((*var7 = *var6) == '\\n') break;\n *var7 = '\\0';\n if (!MapFont(var4, var3)) exit(1);\n }\n exit(0);\n}", "style": "rule"}, "extra_info": {"index": 16085, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\ntypedef int /*<<< orphan*/ var5 ;\ntypedef int /*<<< orphan*/ type1 ;\nstruct type2 {char* member_0; char member_3; int /*<<< orphan*/ member_2; int /*<<< orphan*/ const member_1; } ;\n\n/* Variables and functions */\n int /*<<< orphan*/ MapFont (char*,char*) ; \n int /*<<< orphan*/ XOpenDisplay (int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ exit (int) ; \n scalar_t__ fgets (char*,int,int /*<<< orphan*/ *) ; \n int /*<<< orphan*/ * fopen (char*,char*) ; \n int /*<<< orphan*/ fprintf (int /*<<< orphan*/ ,char*) ; \n int getopt_long (int,char**,char*,struct type2 const*,int /*<<< orphan*/ *) ; \n int /*<<< orphan*/ perror (char*) ; \n int /*<<< orphan*/ printf (char*,char*) ; \n int /*<<< orphan*/ sscanf (int /*<<< orphan*/ ,char*,int /*<<< orphan*/ *) ; \n int /*<<< orphan*/ usage (int /*<<< orphan*/ ) ; \n#define var12 129 \n#define var13 128 \n char* var14 ; \n int var15 ; \n int /*<<< orphan*/ var16 ; \n int /*<<< orphan*/ var17 ; \n int /*<<< orphan*/ var18 ; \n char* var19 ; \n int /*<<< orphan*/ var20 ; \n int /*<<< orphan*/ var21 ; \n int var22 ; \n int /*<<< orphan*/ var23 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nint main(int argc, const char **argv, const char **envp) {\n const char *v3;\n const char *v4;\n const char *v5;\n const char *v6;\n const char *v7;\n const char *v8;\n unsigned int v10;\n uint8_t v11[4];\n unsigned int v12;\n unsigned int v13;\n unsigned int v14;\n int v15;\n int v16;\n unsigned int size;\n unsigned int size_4;\n void *s;\n void *ptr;\n long long info;\n char v22[16];\n char v23[88];\n unsigned long long v24;\n v24 = __readfsqword(40u);\n v13 = 0;\n v14 = -1;\n v15 = 0;\n v16 = 0;\n size = 0;\n s = 0LL;\n ptr = 0LL;\n while (2) {\n size_4 = getopt(argc, (char *const *)argv, \"e:b:l:sSh\");\n if (size_4 != -1) {\n switch (size_4) {\n case 'S':\n v15 = 1;\n continue;\n case 'b':\n v13 = atoi((const char *)(unsigned int)optarg);\n continue;\n case 'e':\n v14 = atoi((const char *)(unsigned int)optarg);\n continue;\n case 'h':\n goto LABEL_9;\n case 'l':\n size = atoi((const char *)(unsigned int)optarg);\n continue;\n case 's':\n v16 = 1;\n continue;\n default:\n fprintf((FILE *)(unsigned int)stderr, \"Unknown option -%c\\n\", size_4);\n LABEL_9:\n usage((unsigned int)argc, argv);\n exit(-1);\n }\n }\n break;\n }\n if (!v15 && !(unsigned int)getenv(\"OMX_DISABLE_SELF\"))\n putenv(\"OMX_DISABLE_SELF=1\");\n if (!v16 && !(unsigned int)getenv(\"OMX_DISABLE_SHARED\"))\n putenv(\"OMX_DISABLE_SHARED=1\");\n if (size) {\n s = malloc(size);\n ptr = malloc(size);\n if (!s || !ptr) return -1;\n memset(s, 97, size);\n memset(ptr, 98, size);\n }\n info = omx_init();\n if (info == OMX_SUCCESS) {\n info = omx_board_number_to_nic_id(v13, v11);\n if (info == OMX_SUCCESS) {\n info = omx_open_endpoint(v13, v14, 305419896LL, 0LL, 0LL, &v10);\n if (info == OMX_SUCCESS) {\n info = omx_get_info(v10, (unsigned int)OMX_INFO_BOARD_HOSTNAME, 0LL,\n 0LL, v23, 80LL);\n if (info == OMX_SUCCESS) {\n info = omx_get_info(v10, (unsigned int)OMX_INFO_BOARD_IFACENAME, 0LL,\n 0LL, v22, 16LL);\n if (info == OMX_SUCCESS) {\n printf(\"Using board #%d name '%s' hostname '%s'\\n\", v13, v22, v23);\n info = omx_get_endpoint_addr(v10, &v12);\n if (info == OMX_SUCCESS) {\n info = omx_isend(v10, s, size, v12, 1LL, 0LL, 0LL);\n assert(info == OMX_SUCCESS);\n }\n v8 = (const char *)omx_strerror(info);\n fprintf((FILE *)(unsigned int)stderr,\n \"Failed to get local endpoint address (%s)\\n\", v8);\n } else {\n v7 = (const char *)omx_strerror(info);\n fprintf((FILE *)(unsigned int)stderr,\n \"Failed to find board iface name (%s)\\n\", v7);\n }\n } else {\n v6 = (const char *)omx_strerror(info);\n fprintf((FILE *)(unsigned int)stderr,\n \"Failed to find board hostname (%s)\\n\", v6);\n }\n omx_close_endpoint(v10);\n } else {\n v5 = (const char *)omx_strerror(info);\n fprintf((FILE *)(unsigned int)stderr, \"Failed to open endpoint (%s)\\n\",\n v5);\n }\n } else {\n v4 = (const char *)omx_strerror(info);\n fprintf((FILE *)(unsigned int)stderr,\n \"Failed to find board %d nic id (%s)\\n\", v13, v4);\n }\n } else {\n v3 = (const char *)omx_strerror(info);\n fprintf((FILE *)(unsigned int)stderr, \"Failed to initialize (%s)\\n\", v3);\n }\n return -1;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "int main(int var1, char *var2[]) {\n type1 var3;\n uint64_t var4;\n int var5 = 0;\n int var6 = 0xffffffffU;\n char var7[80];\n char var8[16];\n type2 var9;\n int var10 = 0;\n int var11 = 0;\n int var12;\n type3 var13;\n type4 var14;\n uint32_t var15;\n int var16 = 0;\n char *var17 = NULL, *var18 = NULL;\n while ((var12 = getopt(var1, var2, \"e:b:l:sSh\")) != -1) switch (var12) {\n case 'b':\n var5 = atoi(var19);\n break;\n case 'e':\n var6 = atoi(var19);\n break;\n case 'l':\n var16 = atoi(var19);\n break;\n case 's':\n var11 = 1;\n break;\n case 'S':\n var10 = 1;\n break;\n default:\n fprintf(var20, \"Unknown option -%c\\n\", var12);\n case 'h':\n usage(var1, var2);\n exit(-1);\n break;\n }\n if (!var10 && !getenv(\"OMX_DISABLE_SELF\")) putenv(\"OMX_DISABLE_SELF=1\");\n if (!var11 && !getenv(\"OMX_DISABLE_SHARED\")) putenv(\"OMX_DISABLE_SHARED=1\");\n if (var16) {\n var17 = malloc(var16);\n var18 = malloc(var16);\n if (!var17 || !var18) goto out;\n memset(var17, 'a', var16);\n memset(var18, 'b', var16);\n }\n var13 = omx_init();\n if (var13 != var21) {\n fprintf(var20, \"Failed to initialize (%s)\\n\", omx_strerror(var13));\n goto out;\n }\n var13 = omx_board_number_to_nic_id(var5, &var4);\n if (var13 != var21) {\n fprintf(var20, \"Failed to find board %d nic id (%s)\\n\", var5,\n omx_strerror(var13));\n goto out;\n }\n var13 = omx_open_endpoint(var5, var6, 0x12345678, NULL, 0, &var3);\n if (var13 != var21) {\n fprintf(var20, \"Failed to open endpoint (%s)\\n\", omx_strerror(var13));\n goto out;\n }\n var13 = omx_get_info(var3, var22, NULL, 0, var7, sizeof(var7));\n if (var13 != var21) {\n fprintf(var20, \"Failed to find board hostname (%s)\\n\", omx_strerror(var13));\n goto out_with_ep;\n }\n var13 = omx_get_info(var3, var23, NULL, 0, var8, sizeof(var8));\n if (var13 != var21) {\n fprintf(var20, \"Failed to find board iface name (%s)\\n\",\n omx_strerror(var13));\n goto out_with_ep;\n }\n printf(\"Using board #%d name '%s' hostname '%s'\\n\", var5, var8, var7);\n var13 = omx_get_endpoint_addr(var3, &var9);\n if (var13 != var21) {\n fprintf(var20, \"Failed to get local endpoint address (%s)\\n\",\n omx_strerror(var13));\n goto out_with_ep;\n }\n var13 = omx_isend(var3, var17, var16, var9, 0x1, NULL, NULL);\n assert(var13 == var21);\n printf(\"posted send\\n\");\n var13 = func1(var3, 0x1, -1ULL, &var14, &var15, ((uint32_t)-1));\n assert(var13 == var21);\n assert(var15);\n assert(var14.field1 == 0x01);\n printf(\"probe found exact match\\n\");\n var13 = func2(var3, 0x2, -1ULL, &var14, &var15);\n assert(var13 == var21);\n assert(!var15);\n printf(\"iprobe did not found match with wrong bits\\n\");\n var13 = func2(var3, 0, -2ULL, &var14, &var15);\n assert(var13 == var21);\n assert(var15);\n assert(var14.field1 == 0x01);\n printf(\"iprobe found match with mask\\n\");\n var13 = func3(var3, var18, var16, 0, -2ULL, NULL, NULL);\n assert(var13 == var21);\n printf(\"posted recv with mask\\n\");\n var13 = func2(var3, 0, -2ULL, &var14, &var15);\n assert(var13 == var21);\n assert(!var15);\n printf(\"iprobe cannot found match with mask anymore\\n\");\n free(var17);\n free(var18);\n omx_close_endpoint(var3);\n return 0;\nout_with_ep:\n omx_close_endpoint(var3);\nout:\n return -1;\n}", "style": "rule"}, "extra_info": {"index": 4131, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_4__ TYPE_1__ ;\n\n/* Type definitions */\ntypedef int /*<<< orphan*/ var8 ;\ntypedef int /*<<< orphan*/ var7 ;\ntypedef int /*<<< orphan*/ uint64_t ;\ntypedef int uint32_t ;\nstruct TYPE_4__ {int field1; } ;\ntypedef TYPE_1__ type4 ;\ntypedef scalar_t__ type3 ;\ntypedef int /*<<< orphan*/ type2 ;\ntypedef int /*<<< orphan*/ type1 ;\n\n/* Variables and functions */\n int /*<<< orphan*/ assert (int) ; \n int atoi (int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ exit (int) ; \n int /*<<< orphan*/ fprintf (int /*<<< orphan*/ ,char*,...) ; \n int /*<<< orphan*/ free (char*) ; \n scalar_t__ func1 (int /*<<< orphan*/ ,int,unsigned long long,TYPE_1__*,int*,int) ; \n scalar_t__ func2 (int /*<<< orphan*/ ,int,unsigned long long,TYPE_1__*,int*) ; \n scalar_t__ func3 (int /*<<< orphan*/ ,char*,int,int /*<<< orphan*/ ,unsigned long long,int /*<<< orphan*/ *,int /*<<< orphan*/ *) ; \n int /*<<< orphan*/ getenv (char*) ; \n int getopt (int,char**,char*) ; \n char* malloc (int) ; \n int /*<<< orphan*/ memset (char*,char,int) ; \n scalar_t__ omx_board_number_to_nic_id (int,int /*<<< orphan*/ *) ; \n int /*<<< orphan*/ omx_close_endpoint (int /*<<< orphan*/ ) ; \n scalar_t__ omx_get_endpoint_addr (int /*<<< orphan*/ ,int /*<<< orphan*/ *) ; \n scalar_t__ omx_get_info (int /*<<< orphan*/ ,int /*<<< orphan*/ ,int /*<<< orphan*/ *,int /*<<< orphan*/ ,char*,int) ; \n scalar_t__ omx_init () ; \n scalar_t__ omx_isend (int /*<<< orphan*/ ,char*,int,int /*<<< orphan*/ ,int,int /*<<< orphan*/ *,int /*<<< orphan*/ *) ; \n scalar_t__ omx_open_endpoint (int,int,int,int /*<<< orphan*/ *,int /*<<< orphan*/ ,int /*<<< orphan*/ *) ; \n char* omx_strerror (scalar_t__) ; \n int /*<<< orphan*/ printf (char*,...) ; \n int /*<<< orphan*/ putenv (char*) ; \n int /*<<< orphan*/ usage (int,char**) ; \n int /*<<< orphan*/ var19 ; \n int /*<<< orphan*/ var20 ; \n scalar_t__ var21 ; \n int /*<<< orphan*/ var22 ; \n int /*<<< orphan*/ var23 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nint main(int argc, const char **argv, const char **envp) {\n int i;\n long long v5;\n long long v6;\n long long v7;\n long long v8;\n FILE *stream;\n char *s1;\n char *filename;\n long long v12;\n long long v13;\n long long v14;\n long long v15;\n uint8_t v16[520];\n unsigned long long v17;\n v17 = __readfsqword(40u);\n filename = 0LL;\n v12 = 0LL;\n v13 = 0LL;\n v14 = 0LL;\n v15 = 0LL;\n v5 = 0LL;\n v6 = 0LL;\n v7 = 0LL;\n v8 = 0LL;\n if (!(unsigned int)parse_args(&filename, (unsigned int)argc, argv))\n return EXIT_FAILURE;\n if (argc == optind) {\n usage();\n return EXIT_FAILURE;\n } else {\n if (!filename) {\n make_file_name(v16, 512LL, argv[optind], \".nes\");\n filename = v16;\n }\n for (i = optind; i < argc; ++i) {\n s1 = (char *)file_extension(argv[i]);\n if (s1 && !strcasecmp(s1, \".chr\")) {\n if (!(unsigned int)file_append(argv[i], &v8, &v6)) goto LABEL_11;\n } else {\n if (!s1 || strcasecmp(s1, \".prg\")) {\n fprintf((FILE *)(unsigned int)stderr, \"%s: unknown file extension.\\n\",\n argv[i]);\n usage();\n return EXIT_FAILURE;\n }\n if (!(unsigned int)file_append(argv[i], &v7, &v5)) {\n LABEL_11:\n usage();\n return EXIT_FAILURE;\n }\n }\n }\n stream = fopen(filename, \"wb\");\n if (stream) {\n if ((unsigned int)write_ines(stream, filename, v7, v5, v8, v6,\n (unsigned int)v13, HIDWORD(v12),\n (unsigned int)v12)) {\n fclose(stream);\n return 0;\n } else {\n return EXIT_FAILURE;\n }\n } else {\n perror(argv[i]);\n return EXIT_FAILURE;\n }\n }\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "int main(int var1, char **var2) {\n int var3;\n type1 *var4;\n char var5[512];\n struct type2 var6 = {0, NULL};\n unsigned char *var7 = NULL, *var8 = NULL;\n size_t var9 = 0, var10 = 0;\n if (!parse_args(&var6, var1, var2)) {\n return var11;\n }\n if (var1 == var12) {\n usage();\n return var11;\n }\n if (!var6.field1) {\n make_file_name(var5, sizeof var5, var2[var12], \".nes\");\n var6.field1 = var5;\n }\n for (var3 = var12; var3 < var1; var3++) {\n const char *var13;\n var13 = file_extension(var2[var3]);\n if (var13 && !strcasecmp(var13, \".chr\")) {\n if (!file_append(var2[var3], &var10, &var8)) {\n usage();\n return var11;\n }\n } else if (var13 && !strcasecmp(var13, \".prg\")) {\n if (!file_append(var2[var3], &var9, &var7)) {\n usage();\n return var11;\n }\n } else {\n fprintf(var14, \"%s: unknown file extension.\\n\", var2[var3]);\n usage();\n return var11;\n }\n }\n var4 = fopen(var6.field1, \"wb\");\n if (!var4) {\n perror(var2[var3]);\n return var11;\n }\n if (!write_ines(var4, var6.field1, var9, var7, var10, var8, var6.field2,\n var6.field3, var6.field4)) {\n return var11;\n }\n fclose(var4);\n return 0;\n}", "style": "rule"}, "extra_info": {"index": 14516, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\ntypedef int /*<<< orphan*/ type1 ;\nstruct type2 {char* field1; int /*<<< orphan*/ field4; int /*<<< orphan*/ field3; int /*<<< orphan*/ field2; int /*<<< orphan*/ * member_1; int /*<<< orphan*/ member_0; } ;\n\n/* Variables and functions */\n int /*<<< orphan*/ fclose (int /*<<< orphan*/ *) ; \n int /*<<< orphan*/ file_append (char*,size_t*,unsigned char**) ; \n char* file_extension (char*) ; \n int /*<<< orphan*/ * fopen (char*,char*) ; \n int /*<<< orphan*/ fprintf (int /*<<< orphan*/ ,char*,char*) ; \n int /*<<< orphan*/ make_file_name (char*,int,char*,char*) ; \n int /*<<< orphan*/ parse_args (struct type2*,int,char**) ; \n int /*<<< orphan*/ perror (char*) ; \n int /*<<< orphan*/ strcasecmp (char const*,char*) ; \n int /*<<< orphan*/ usage () ; \n int var11 ; \n int var12 ; \n int /*<<< orphan*/ var14 ; \n int /*<<< orphan*/ write_ines (int /*<<< orphan*/ *,char*,size_t,unsigned char*,size_t,unsigned char*,int /*<<< orphan*/ ,int /*<<< orphan*/ ,int /*<<< orphan*/ ) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long serial_out_sync(long long a1, unsigned int a2, unsigned int a3) {\n if ((unsigned int)(*(uint32_t *)a1 - 128) > 2)\n return (*(long long (**)(long long, uint64_t, uint64_t))(a1 + 8))(a1, a2,\n a3);\n (*(void (**)(long long, uint64_t, uint64_t))(a1 + 8))(a1, a2, a3);\n return (*(long long (**)(long long, uint64_t))(a1 + 16))(\n a1, (unsigned int)UART_LCR);\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "static void serial_out_sync(struct type1 *var1, int var2, int var3) {\n struct type2 *var4 = &var1->field1;\n switch (var4->field2) {\n case var5:\n case var6:\n#ifdef var7\n case var8:\n#endif\n case var9:\n var4->field3(var4, var2, var3);\n var4->field4(var4, var10);\n break;\n default:\n var4->field3(var4, var2, var3);\n }\n}", "style": "rule"}, "extra_info": {"index": 58003, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\nstruct type2 {int field2; int /*<<< orphan*/ (* field3 ) (struct type2*,int,int) ;int /*<<< orphan*/ (* field4 ) (struct type2*,int /*<<< orphan*/ ) ;} ;\nstruct type1 {struct type2 field1; } ;\n\n/* Variables and functions */\n int /*<<< orphan*/ stub1 (struct type2*,int,int) ; \n int /*<<< orphan*/ stub2 (struct type2*,int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ stub3 (struct type2*,int,int) ; \n int /*<<< orphan*/ var10 ; \n#define var5 131 \n#define var6 130 \n#define var8 129 \n#define var9 128 \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long extcss3_consume_bad_url_remnants(char **a1, long long a2) {\n char v2;\n while (1) {\n if ((unsigned int)extcss3_next_char(a1, a2) != 1) return 0LL;\n v2 = **a1;\n if (v2 == 41 || !v2) break;\n if ((unsigned int)extcss3_check_start_valid_escape() == 1 &&\n (unsigned int)extcss3_consume_escaped(a1, a2) != 1)\n return 0LL;\n }\n return extcss3_next_char(a1, a2);\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "static inline bool func1(type1 *var1, unsigned int *var2) {\n while (true) {\n do {\n bool var3 = func2(var1, var2);\n if ((true) != var3) {\n return (false);\n }\n } while (0);\n if ((*var1->field1.field2 == ')') || (*var1->field1.field2 == '\\0')) {\n return func2(var1, var2);\n } else if ((true) == func3(var1->field1.field2)) {\n if ((true) != func4(var1, var2)) {\n return (false);\n }\n }\n }\n return (true);\n}", "style": "rule"}, "extra_info": {"index": 28864, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_7__ TYPE_2__ ;\ntypedef struct TYPE_6__ TYPE_1__ ;\n\n/* Type definitions */\nstruct TYPE_6__ {char* field2; } ;\nstruct TYPE_7__ {TYPE_1__ field1; } ;\ntypedef TYPE_2__ type1 ;\n\n/* Variables and functions */\n int func2 (TYPE_2__*,unsigned int*) ; \n int func3 (char*) ; \n int func4 (TYPE_2__*,unsigned int*) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long halbtc8723b2ant_CoexTable(unsigned int a1, int a2, long long a3,\n long long a4, long long a5, long long a6) {\n long long result;\n BTC_PRINT((unsigned int)BTC_MSG_ALGORITHM, (unsigned int)ALGO_TRACE_SW, a6);\n *(uint64_t *)pCoexDm = a3;\n *(uint64_t *)(pCoexDm + 8) = a4;\n *(uint64_t *)(pCoexDm + 16) = a5;\n *(uint64_t *)(pCoexDm + 24) = a6;\n if (a2 ||\n (BTC_PRINT((unsigned int)BTC_MSG_ALGORITHM,\n (unsigned int)ALGO_TRACE_SW_DETAIL,\n *(uint64_t *)(pCoexDm + 56)),\n BTC_PRINT((unsigned int)BTC_MSG_ALGORITHM,\n (unsigned int)ALGO_TRACE_SW_DETAIL,\n *(uint64_t *)(pCoexDm + 24)),\n *(uint64_t *)(pCoexDm + 32) != *(uint64_t *)pCoexDm) ||\n *(uint64_t *)(pCoexDm + 40) != *(uint64_t *)(pCoexDm + 8) ||\n *(uint64_t *)(pCoexDm + 48) != *(uint64_t *)(pCoexDm + 16) ||\n (result = *(uint64_t *)(pCoexDm + 24),\n *(uint64_t *)(pCoexDm + 56) != result)) {\n halbtc8723b2ant_SetCoexTable(a1, a3, a4, a5, a6);\n *(uint64_t *)(pCoexDm + 32) = *(uint64_t *)pCoexDm;\n *(uint64_t *)(pCoexDm + 40) = *(uint64_t *)(pCoexDm + 8);\n *(uint64_t *)(pCoexDm + 48) = *(uint64_t *)(pCoexDm + 16);\n result = pCoexDm;\n *(uint64_t *)(pCoexDm + 56) = *(uint64_t *)(pCoexDm + 24);\n }\n return result;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "static void halbtc8723b2ant_CoexTable(type1 var1, bool var2, type2 var3,\n type2 var4, type2 var5, type3 var6) {\n BTC_PRINT(\n var7, var8,\n (\"[BTCoex], %s write Coex Table 0x6c0 = 0x%x, 0x6c4 = 0x%x, 0x6c8 = \"\n \"0x%x, 0x6cc = 0x%x\\n\",\n (var2 ? \"force to\" : \"\"), var3, var4, var5, var6));\n var9->field1 = var3;\n var9->field2 = var4;\n var9->field3 = var5;\n var9->field4 = var6;\n if (!var2) {\n BTC_PRINT(var7, var10,\n (\"[BTCoex], preVal0x6c0 = 0x%x, preVal0x6c4 = 0x%x, preVal0x6c8 \"\n \"= 0x%x, preVal0x6cc = 0x%x !!\\n\",\n var9->field5, var9->field6, var9->field7, var9->field8));\n BTC_PRINT(var7, var10,\n (\"[BTCoex], curVal0x6c0 = 0x%x, curVal0x6c4 = 0x%x, curVal0x6c8 \"\n \"= 0x%x, curVal0x6cc = 0x%x !!\\n\",\n var9->field1, var9->field2, var9->field3, var9->field4));\n if ((var9->field5 == var9->field1) && (var9->field6 == var9->field2) &&\n (var9->field7 == var9->field3) && (var9->field8 == var9->field4))\n return;\n }\n halbtc8723b2ant_SetCoexTable(var1, var3, var4, var5, var6);\n var9->field5 = var9->field1;\n var9->field6 = var9->field2;\n var9->field7 = var9->field3;\n var9->field8 = var9->field4;\n}", "style": "rule"}, "extra_info": {"index": 44199, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_2__ TYPE_1__ ;\n\n/* Type definitions */\ntypedef scalar_t__ type3 ;\ntypedef void* type2 ;\ntypedef int /*<<< orphan*/ type1 ;\nstruct TYPE_2__ {scalar_t__ field1; scalar_t__ field2; scalar_t__ field3; scalar_t__ field4; scalar_t__ field5; scalar_t__ field6; scalar_t__ field7; scalar_t__ field8; } ;\n\n/* Variables and functions */\n int /*<<< orphan*/ BTC_PRINT (int /*<<< orphan*/ ,int /*<<< orphan*/ ,char*) ; \n int /*<<< orphan*/ halbtc8723b2ant_SetCoexTable (int /*<<< orphan*/ ,void*,void*,void*,scalar_t__) ; \n int /*<<< orphan*/ var10 ; \n int /*<<< orphan*/ var7 ; \n int /*<<< orphan*/ var8 ; \n TYPE_1__* var9 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nvoid laguer(long long a1, int a2, long long *a3, int *a4) {\n long long v5;\n long long v6;\n long long v7;\n long long v8;\n long long v9;\n float v10;\n long long v11;\n long long v12;\n float v13;\n long long *v14;\n long long v15;\n long long v16;\n long long v17;\n long long v18;\n long long v19;\n long long v20;\n long long v21;\n long long v22;\n long long v23;\n long long v24;\n long long v25;\n float v26;\n float v27;\n long long v28;\n long long v29;\n long long v30;\n long long v31;\n long long v32;\n long long v33;\n long long v34;\n long long v35;\n long long v36;\n long long v37;\n long long v38;\n long long v39;\n long long v40;\n long long v41;\n long long v42;\n long long v43;\n long long v44;\n long long v45;\n long long v46;\n long long v47;\n long long v48;\n long long v49;\n long long v50;\n long long v51;\n long long v52;\n long long v53;\n long long v54;\n long long v55;\n float v56;\n double v57;\n double v58;\n double v59;\n long long v60;\n long long v61;\n long long v62;\n long long v63;\n long long v64;\n long long v65;\n long long v66;\n double v67;\n long long v68;\n long long v69;\n long long v70;\n long long v71;\n long long v72;\n long long v73;\n long long v74;\n long long v75;\n float v76;\n double v77;\n long long xa;\n long long x;\n float v80;\n long long v81;\n float v82;\n float v83;\n int v84;\n long long v85;\n long long *v86;\n int v88;\n v88 = a2 - 1;\n v86 = (long long *)(a1 + 16LL * a2);\n v84 = 1;\n while (1) {\n *a4 = v84;\n v5 = *v86;\n v6 = v86[1];\n v80 = Cabs(*v86, v6);\n v7 = Complex(0.0, 0.0);\n v9 = v8;\n v73 = v8;\n v10 = Cabs(*a3, a3[1]);\n v11 = v73;\n v12 = v7;\n v13 = v80;\n v83 = v10;\n if (v88 >= 0) {\n v14 = (long long *)(a1 + 16LL * (a2 - 1));\n do {\n v14 -= 2;\n v15 = Cmul(*a3, a3[1], v12, v11);\n v17 = Cadd(v15, v16, v7, v9);\n v74 = v18;\n xa = v17;\n v19 = Cmul(*a3, a3[1], v7, v9);\n v21 = Cadd(v19, v20, v5, v6);\n v9 = v22;\n v7 = v21;\n v23 = Cmul(*a3, a3[1], v5, v6);\n v5 = Cadd(v23, v24, v14[2], v14[3]);\n v6 = v25;\n v26 = Cabs(v5, v25);\n v11 = v74;\n v12 = xa;\n v13 = (float)(v13 * v83) + v26;\n } while (v14 != &v86[-2 * (unsigned int)(a2 - 1) - 4]);\n }\n v81 = v11;\n x = v12;\n v27 = v13 * 0.0000001;\n if (v27 >= Cabs(v5, v6)) break;\n v85 = Cdiv(v7, v9, v5, v6);\n v75 = v28;\n v29 = Cmul(v85, v75, v85, v75);\n v31 = v30;\n v32 = v29;\n v33 = Cdiv(x, v81, v5, v6);\n v35 = RCmul(v33, v34, 2.0);\n v37 = Csub(v32, v31, v35, v36);\n v82 = (float)a2;\n v39 = RCmul(v37, v38, (float)a2);\n v41 = Csub(v39, v40, v32, v31);\n v43 = RCmul(v41, v42, (float)v88);\n v45 = Csqrt(v43, v44);\n v47 = v46;\n v48 = v45;\n v49 = Cadd(v85, v75, v45, v46);\n v51 = v50;\n v52 = v49;\n v53 = Csub(v85, v75, v48, v47);\n v55 = v54;\n v76 = Cabs(v52, v51);\n v56 = Cabs(v53, v55);\n *(uint64_t *)&v57 = COERCE_UNSIGNED_INT((float)a2);\n if (v56 > v76) {\n v52 = v53;\n v51 = v55;\n }\n *(double *)&maxarg1 = v76;\n *(double *)&maxarg2 = v56;\n if (v76 <= v56) {\n if (v56 > 0.0) {\n LABEL_10:\n v58 = 0.0;\n *(uint64_t *)&v59 = LODWORD(v82);\n v60 = Complex(COERCE_DOUBLE((unsigned long long)LODWORD(v82)), 0.0);\n v62 = Cdiv(v60, v61, v52, v51);\n v64 = v63;\n goto LABEL_11;\n }\n } else if (v76 > 0.0) {\n goto LABEL_10;\n }\n *(uint64_t *)&v57 = COERCE_UNSIGNED_INT((float)v84);\n v77 = sin(v57);\n v67 = cos(v57);\n v58 = v77;\n v68 = Complex(v67, v77);\n *(uint64_t *)&v59 = (unsigned int)LC4;\n *(float *)&v59 = v83 + 1.0;\n v62 = RCmul(v68, v69, v83 + 1.0);\n v64 = v70;\n LABEL_11:\n v65 = Csub(*a3, a3[1], v62, v64);\n if (*a3 == v65 && a3[1] == v66) return;\n if (__ROR4__(-858993459 * v84, 1) <= 429496729u) {\n *(uint64_t *)&v59 = frac_0[(unsigned int)v84 / 10uLL];\n v71 = RCmul(v62, v64, *(float *)&v59);\n v65 = Csub(*a3, a3[1], v71, v72);\n }\n ++v84;\n *a3 = v65;\n a3[1] = v66;\n if (v84 == 81) {\n nrerror(\"too many iterations in laguer\", v59, v58, v57);\n return;\n }\n }\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "void laguer(type1 var1[], int var2, type1 *var3, int *var4) {\n int var5, var6;\n float var7, var8, var9, var10;\n type1 var11, var12, var13, var14, var15, var16, var17, var18, var19, var20,\n var21;\n static float var22[8 + 1] = {0.0, 0.5, 0.25, 0.75, 0.13,\n 0.38, 0.62, 0.88, 1.0};\n for (var5 = 1; var5 <= (10 * 8); var5++) {\n *var4 = var5;\n var13 = var1[var2];\n var10 = Cabs(var13);\n var14 = var15 = Complex(0.0, 0.0);\n var7 = Cabs(*var3);\n for (var6 = var2 - 1; var6 >= 0; var6--) {\n var15 = Cadd(Cmul(*var3, var15), var14);\n var14 = Cadd(Cmul(*var3, var14), var13);\n var13 = Cadd(Cmul(*var3, var13), var1[var6]);\n var10 = Cabs(var13) + var7 * var10;\n }\n var10 *= 1.0e-7;\n if (Cabs(var13) <= var10) return;\n var16 = Cdiv(var14, var13);\n var21 = Cmul(var16, var16);\n var17 = Csub(var21, RCmul(2.0, Cdiv(var15, var13)));\n var18 =\n Csqrt(RCmul((float)(var2 - 1), Csub(RCmul((float)var2, var17), var21)));\n var19 = Cadd(var16, var18);\n var20 = Csub(var16, var18);\n var8 = Cabs(var19);\n var9 = Cabs(var20);\n if (var8 < var9) var19 = var20;\n var11 =\n (((var23 = (var8), var24 = (var9),\n (var23) > (var24) ? (var23) : (var24)) > 0.0\n ? Cdiv(Complex((float)var2, 0.0), var19)\n : RCmul(1 + var7, Complex(cos((float)var5), sin((float)var5)))));\n var12 = Csub(*var3, var11);\n if (var3->field1 == var12.field1 && var3->field2 == var12.field2) return;\n if (var5 % 10)\n *var3 = var12;\n else\n *var3 = Csub(*var3, RCmul(var22[var5 / 10], var11));\n }\n nrerror(\"too many iterations in laguer\");\n return;\n}", "style": "rule"}, "extra_info": {"index": 27526, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_22__ TYPE_1__ ;\n\n/* Type definitions */\nstruct TYPE_22__ {scalar_t__ field1; scalar_t__ field2; } ;\ntypedef TYPE_1__ type1 ;\n\n/* Variables and functions */\n float Cabs (TYPE_1__) ; \n TYPE_1__ Cadd (TYPE_1__,TYPE_1__) ; \n TYPE_1__ Cdiv (TYPE_1__,TYPE_1__) ; \n TYPE_1__ Cmul (TYPE_1__,TYPE_1__) ; \n TYPE_1__ Complex (float,double) ; \n TYPE_1__ Csqrt (TYPE_1__) ; \n TYPE_1__ Csub (TYPE_1__,TYPE_1__) ; \n TYPE_1__ RCmul (float,TYPE_1__) ; \n float cos (float) ; \n int /*<<< orphan*/ nrerror (char*) ; \n double sin (float) ; \n double var23 ; \n double var24 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long *ev7_collect_logout_frame_subpackets(uint64_t *a1, long long *a2) {\n long long v3;\n long long v4;\n uint64_t *v5;\n int v6;\n uint64_t *v7;\n if (*a1 != EL_CLASS__HEADER || a1[1] != EL_TYPE__HEADER__LOGOUT_FRAME)\n return 0LL;\n v5 = (uint64_t *)((char *)a1 + a1[3]);\n if (*v5 != EL_CLASS__PAL || v5[1] != EL_TYPE__PAL__LOGOUT_FRAME) return 0LL;\n a2[5] = v5[2];\n v7 = (uint64_t *)((char *)v5 + v5[3]);\n v6 = 0;\n while (2) {\n if (!v7 || v6 >= *(uint32_t *)a2[5]) return a2;\n if (*v7 == EL_CLASS__PAL) {\n switch (v7[1]) {\n case 128LL:\n a2[2] = v7[2];\n goto LABEL_17;\n case 129LL:\n a2[3] = v7[2];\n goto LABEL_17;\n case 130LL:\n a2[4] = v7[2];\n goto LABEL_17;\n case 131LL:\n a2[1] = v7[2];\n goto LABEL_17;\n case 132LL:\n case 133LL:\n case 134LL:\n case 135LL:\n case 136LL:\n case 137LL:\n case 138LL:\n v3 = v7[2];\n v4 = *a2;\n *(uint64_t *)(v4 + 8 * ev7_lf_env_index((unsigned int)v7[1])) = v3;\n LABEL_17:\n v7 = (uint64_t *)((char *)v7 + v7[3]);\n ++v6;\n continue;\n default:\n return 0LL;\n }\n }\n break;\n }\n printk(\"%s**UNEXPECTED SUBPACKET CLASS %d IN LOGOUT FRAME (packet %d\\n\",\n (const char *)(unsigned int)err_print_prefix, *v7, v6);\n return 0LL;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "struct type1 *ev7_collect_logout_frame_subpackets(struct type2 *var1,\n struct type1 *var2) {\n struct type2 *var3;\n int var4;\n if (var1->field1 != var5 || var1->field2 != var6) return NULL;\n var1 = (struct type2 *)((unsigned long)var1 + var1->field3);\n if (var1->field1 != var7 || var1->field2 != var8) return NULL;\n var2->field4 = (struct type3 *)var1->field5.field6.field7;\n var3 = (struct type2 *)((unsigned long)var1 + var1->field3);\n for (var4 = 0; var3 && var4 < var2->field4->field8;\n var3 = (struct type2 *)((unsigned long)var3 + var3->field3), var4++) {\n if (var3->field1 != var7) {\n printk(\n \"%s**UNEXPECTED SUBPACKET CLASS %d \"\n \"IN LOGOUT FRAME (packet %d\\n\",\n var9, var3->field1, var4);\n return NULL;\n }\n switch (var3->field2) {\n case var10:\n var2->field9 = (struct type4 *)var3->field5.field6.field7;\n break;\n case var11:\n var2->field10 = (struct type5 *)var3->field5.field6.field7;\n break;\n case var12:\n var2->field11 = (struct type6 *)var3->field5.field6.field7;\n break;\n case var13:\n var2->field12 = (struct type7 *)var3->field5.field6.field7;\n break;\n case var14:\n case var15:\n case var16:\n case var17:\n case var18:\n case var19:\n case var20:\n var2->field13[ev7_lf_env_index(var3->field2)] =\n (struct type8 *)var3->field5.field6.field7;\n break;\n default:\n return NULL;\n }\n }\n return var2;\n}", "style": "rule"}, "extra_info": {"index": 38738, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_4__ TYPE_2__ ;\ntypedef struct TYPE_3__ TYPE_1__ ;\n\n/* Type definitions */\nstruct type8 {int dummy; } ;\nstruct type7 {int dummy; } ;\nstruct type6 {int dummy; } ;\nstruct type5 {int dummy; } ;\nstruct type4 {int dummy; } ;\nstruct type3 {int field8; } ;\nstruct TYPE_3__ {scalar_t__ field7; } ;\nstruct TYPE_4__ {TYPE_1__ field6; } ;\nstruct type2 {scalar_t__ field1; scalar_t__ field2; TYPE_2__ field5; scalar_t__ field3; } ;\nstruct type1 {struct type8** field13; struct type7* field12; struct type6* field11; struct type5* field10; struct type4* field9; struct type3* field4; } ;\n\n/* Variables and functions */\n size_t ev7_lf_env_index (int) ; \n int /*<<< orphan*/ printk (char*,int /*<<< orphan*/ ,scalar_t__,int) ; \n#define var10 138 \n#define var11 137 \n#define var12 136 \n#define var13 135 \n#define var14 134 \n#define var15 133 \n#define var16 132 \n#define var17 131 \n#define var18 130 \n#define var19 129 \n#define var20 128 \n scalar_t__ var5 ; \n scalar_t__ var6 ; \n scalar_t__ var7 ; \n scalar_t__ var8 ; \n int /*<<< orphan*/ var9 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long mptsas_sas_phy_pg0(unsigned int *a1, uint64_t *a2, long long a3,\n long long a4) {\n unsigned int v5;\n unsigned int *v7;\n long long v8;\n long long v9;\n unsigned int v10;\n uint64_t v11[2];\n int v12;\n long long v13;\n uint32_t *v14;\n uint32_t v15[4];\n __int128 v16;\n long long v17;\n int v18;\n unsigned long long v19;\n v19 = __readfsqword(40u);\n v11[1] = a4 + a3;\n v16 = 0LL;\n v15[0] = 0;\n v17 = 0LL;\n v13 = 0LL;\n LODWORD(v11[0]) = -1;\n v18 = MPI_SASPHY0_PAGEVERSION;\n v15[2] = MPI_CONFIG_PAGETYPE_EXTENDED;\n v15[1] = MPI_CONFIG_EXTPAGETYPE_SAS_PHY;\n v14 = v15;\n v12 = SAS_CONFIG_PAGE_TIMEOUT;\n HIDWORD(v11[0]) = MPI_CONFIG_ACTION_PAGE_HEADER;\n v5 = mpt_config(a1, v11);\n if (!v5) {\n if (v15[0]) {\n v7 = (unsigned int *)pci_alloc_consistent(*a1, (unsigned int)(4 * v15[0]),\n &v10);\n v5 = -ENOMEM;\n if (v7) {\n v11[0] = _mm_unpacklo_epi32(\n _mm_cvtsi32_si128(v10),\n _mm_cvtsi32_si128(MPI_CONFIG_ACTION_PAGE_READ_CURRENT))\n .m128i_u64[0];\n v5 = mpt_config(a1, v11);\n if (!v5) {\n mptsas_print_phy_pg0(a1, v7);\n a2[2] = *((uint64_t *)v7 + 1);\n v8 = le16_to_cpu(v7[1]);\n v9 = *v7;\n a2[1] = v8;\n *a2 = le16_to_cpu(v9);\n }\n pci_free_consistent(*a1, (unsigned int)(4 * v15[0]), v7, v10);\n }\n } else {\n return (unsigned int)-ENXIO;\n }\n }\n return v5;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "static int mptsas_sas_phy_pg0(type1 *var1, struct type2 *var2, type3 var3,\n type3 var4) {\n type4 var5;\n type5 var6;\n type6 *var7;\n type7 var8;\n int var9;\n var5.field1 = var10;\n var5.field2 = 0;\n var5.field3 = 0;\n var5.field4 = 0;\n var5.field5 = 0;\n var5.field6 = var11;\n var5.field7 = var12;\n var6.field8.field9 = &var5;\n var6.field10 = 0;\n var6.field11 = var13;\n var6.field12 = -1;\n var6.field13 = var3 + var4;\n var6.field14 = var14;\n var9 = mpt_config(var1, &var6);\n if (var9) goto out;\n if (!var5.field2) {\n var9 = -var15;\n goto out;\n }\n var7 = pci_alloc_consistent(var1->field15, var5.field2 * 4, &var8);\n if (!var7) {\n var9 = -var16;\n goto out;\n }\n var6.field12 = var8;\n var6.field14 = var17;\n var9 = mpt_config(var1, &var6);\n if (var9) goto out_free_consistent;\n mptsas_print_phy_pg0(var1, var7);\n var2->field16 = var7->field17;\n var2->field18 = var7->field19;\n var2->field20.field21 = le16_to_cpu(var7->field22);\n var2->field23.field21 = le16_to_cpu(var7->field24);\nout_free_consistent:\n pci_free_consistent(var1->field15, var5.field2 * 4, var7, var8);\nout:\n return var9;\n}", "style": "rule"}, "extra_info": {"index": 102516, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_21__ TYPE_7__ ;\ntypedef struct TYPE_20__ TYPE_6__ ;\ntypedef struct TYPE_19__ TYPE_5__ ;\ntypedef struct TYPE_18__ TYPE_4__ ;\ntypedef struct TYPE_17__ TYPE_3__ ;\ntypedef struct TYPE_16__ TYPE_2__ ;\ntypedef struct TYPE_15__ TYPE_1__ ;\n\n/* Type definitions */\ntypedef int type7 ;\nstruct TYPE_18__ {int /*<<< orphan*/ field24; int /*<<< orphan*/ field22; int /*<<< orphan*/ field19; int /*<<< orphan*/ field17; } ;\ntypedef TYPE_4__ type6 ;\nstruct TYPE_15__ {TYPE_6__* field9; } ;\nstruct TYPE_19__ {int field12; int /*<<< orphan*/ field14; scalar_t__ field13; int /*<<< orphan*/ field11; scalar_t__ field10; TYPE_1__ field8; } ;\ntypedef TYPE_5__ type5 ;\nstruct TYPE_20__ {int field2; int /*<<< orphan*/ field7; int /*<<< orphan*/ field6; scalar_t__ field5; scalar_t__ field4; scalar_t__ field3; int /*<<< orphan*/ field1; } ;\ntypedef TYPE_6__ type4 ;\ntypedef scalar_t__ type3 ;\nstruct TYPE_21__ {int /*<<< orphan*/ field15; } ;\ntypedef TYPE_7__ type1 ;\nstruct TYPE_17__ {void* field21; } ;\nstruct TYPE_16__ {void* field21; } ;\nstruct type2 {TYPE_3__ field23; TYPE_2__ field20; int /*<<< orphan*/ field18; int /*<<< orphan*/ field16; } ;\n\n/* Variables and functions */\n void* le16_to_cpu (int /*<<< orphan*/ ) ; \n int mpt_config (TYPE_7__*,TYPE_5__*) ; \n int /*<<< orphan*/ mptsas_print_phy_pg0 (TYPE_7__*,TYPE_4__*) ; \n TYPE_4__* pci_alloc_consistent (int /*<<< orphan*/ ,int,int*) ; \n int /*<<< orphan*/ pci_free_consistent (int /*<<< orphan*/ ,int,TYPE_4__*,int) ; \n int /*<<< orphan*/ var10 ; \n int /*<<< orphan*/ var11 ; \n int /*<<< orphan*/ var12 ; \n int /*<<< orphan*/ var13 ; \n int /*<<< orphan*/ var14 ; \n int var15 ; \n int var16 ; \n int /*<<< orphan*/ var17 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long rc_init(long long a1, long long a2) {\n long long result;\n *(uint64_t *)(a1 + 32) = a2;\n *(uint64_t *)(a1 + 24) = 0LL;\n *(uint32_t *)a1 = -1;\n *(uint64_t *)(a1 + 16) = 0LL;\n result = a1;\n *(uint64_t *)(a1 + 8) = 0LL;\n return result;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "void rc_init(struct type1 *var1, type2 *var2) {\n var1->field1 = var2;\n var1->field2 = 0;\n var1->field3 = 0xffffffff;\n var1->field4 = 0;\n var1->field5 = 0;\n}", "style": "rule"}, "extra_info": {"index": 91761, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\ntypedef int /*<<< orphan*/ type2 ;\nstruct type1 {int field3; scalar_t__ field5; scalar_t__ field4; scalar_t__ field2; int /*<<< orphan*/ * field1; } ;\n\n/* Variables and functions */\n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long readcharsetfile(char *filename, char *s1, long long a3) {\n FILE *v4;\n char *v5;\n long long v6;\n long long v7;\n long long v8;\n char *v10;\n const char *v11;\n unsigned int v12;\n void *v13;\n int v14;\n long long v15;\n int v16;\n long long v17;\n char *v18;\n int v19;\n char *v20;\n char v21[520];\n unsigned long long v22;\n v22 = __readfsqword(40u);\n errno = 0;\n memset(v21, 0, 512uLL);\n v4 = fopen(filename, \"r\");\n if (!v4) {\n fprintf((FILE *)(unsigned int)stderr,\n \"readcharset: File %s could not be opened\\n\", filename);\n v20 = strerror(errno);\n fprintf((FILE *)(unsigned int)stderr, \"The problem is = %s\\n\", v20);\n exit(EXIT_FAILURE);\n }\n do {\n if (!fgets(v21, 512, v4)) goto LABEL_5;\n v5 = strtok(v21, \" \");\n LODWORD(v6) = strcmp(s1, v5);\n } while (v6);\n strtok(0LL, \"[\");\n v10 = strtok(0LL, \"\\n\");\n v11 = v10;\n if (v10) {\n v12 = strlen(v10);\n v13 = calloc(v12, 1uLL);\n if (!v13) {\n fprintf((FILE *)(unsigned int)stderr,\n \"readcharset: can't allocate memory for charset\\n\");\n exit(EXIT_FAILURE);\n }\n v14 = strlen(v11);\n LODWORD(v15) = strncmp(&v11[v14 - 1], \"]\", 1uLL);\n if (v15) {\n v16 = strlen(v11);\n memcpy(v13, v11, (unsigned int)(v16 - 2));\n } else {\n v19 = strlen(v11);\n memcpy(v13, v11, (unsigned int)(v19 - 1));\n }\n v7 = alloc_wide_string(v13, a3);\n free(v13);\n LODWORD(v17) = fclose(v4);\n if (v17) {\n LABEL_12:\n fprintf((FILE *)(unsigned int)stderr,\n \"readcharset: fclose returned error number = %d\\n\", errno);\n v18 = strerror(errno);\n fprintf((FILE *)(unsigned int)stderr, \"The problem is = %s\\n\", v18);\n exit(EXIT_FAILURE);\n }\n } else {\n LABEL_5:\n v7 = 0LL;\n LODWORD(v8) = fclose(v4);\n if (v8) goto LABEL_12;\n }\n return v7;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "static type1 *readcharsetfile(const char *var1, const char *var2, int *var3) {\n type2 *var4;\n char *var5;\n char *var6;\n char *var7 = NULL;\n type1 *var8 = NULL;\n char var9[512];\n var10 = 0;\n memset(var9, 0, sizeof(var9));\n if ((var4 = fopen(var1, \"r\")) == NULL) {\n fprintf(var11, \"readcharset: File %s could not be opened\\n\", var1);\n fprintf(var11, \"The problem is = %s\\n\", strerror(var10));\n exit(var12);\n } else {\n while (fgets(var9, (int)sizeof(var9), var4) != NULL) {\n var5 = strtok(var9, \" \");\n if (strcmp(var2, var5) == 0) {\n var6 = strtok(NULL, \"[\");\n if ((var6 = strtok(NULL, \"\\n\")) != NULL) {\n var7 = calloc(strlen(var6), sizeof(char));\n if (var7 == NULL) {\n fprintf(var11, \"readcharset: can't allocate memory for charset\\n\");\n exit(var12);\n }\n if (strncmp(&var6[(strlen(var6) - 1)], \"]\", 1) == 0)\n memcpy(var7, var6, strlen(var6) - 1);\n else\n memcpy(var7, var6, strlen(var6) - 2);\n var8 = alloc_wide_string(var7, var3);\n free(var7);\n }\n break;\n }\n }\n if (fclose(var4) != 0) {\n fprintf(var11, \"readcharset: fclose returned error number = %d\\n\", var10);\n fprintf(var11, \"The problem is = %s\\n\", strerror(var10));\n exit(var12);\n }\n }\n return var8;\n}", "style": "rule"}, "extra_info": {"index": 36369, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\ntypedef int /*<<< orphan*/ var9 ;\ntypedef int /*<<< orphan*/ type2 ;\ntypedef int /*<<< orphan*/ type1 ;\n\n/* Variables and functions */\n int /*<<< orphan*/ * alloc_wide_string (char*,int*) ; \n char* calloc (int,int) ; \n int /*<<< orphan*/ exit (int /*<<< orphan*/ ) ; \n scalar_t__ fclose (int /*<<< orphan*/ *) ; \n int /*<<< orphan*/ * fgets (char*,int,int /*<<< orphan*/ *) ; \n int /*<<< orphan*/ * fopen (char const*,char*) ; \n int /*<<< orphan*/ fprintf (int /*<<< orphan*/ ,char*,...) ; \n int /*<<< orphan*/ free (char*) ; \n int /*<<< orphan*/ memcpy (char*,char*,int) ; \n int /*<<< orphan*/ memset (char*,int /*<<< orphan*/ ,int) ; \n scalar_t__ strcmp (char const*,char*) ; \n char* strerror (int) ; \n int strlen (char*) ; \n scalar_t__ strncmp (char*,char*,int) ; \n char* strtok (char*,char*) ; \n int var10 ; \n int /*<<< orphan*/ var11 ; \n int /*<<< orphan*/ var12 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nunsigned long long setup() {\n long long v0;\n long long v1;\n uint64_t *v2;\n uint64_t *v3;\n uint64_t *v4;\n uint64_t *v5;\n uint64_t *v6;\n uint64_t *v7;\n int v8;\n int v9;\n int v10;\n int v11;\n int v12;\n unsigned int v13;\n int v14;\n int v15;\n unsigned long long v16;\n Visual *v17;\n unsigned int v18;\n int v19;\n unsigned int v20;\n unsigned int v21;\n int i;\n int j;\n int v25;\n XModifierKeymap *v26;\n XClassHint *v27;\n uint32_t v28[3];\n unsigned long long v29;\n v29 = __readfsqword(40u);\n v26 = XGetModifierMapping((Display *)(unsigned int)dpy);\n for (i = 0; i <= 7; ++i) {\n for (j = 0; j < v26->max_keypermod; ++j) {\n v0 = *(uint64_t *)&v26->modifiermap[8 * i * v26->max_keypermod + 8 * j];\n LOBYTE(v1) = XKeysymToKeycode((Display *)(unsigned int)dpy,\n (unsigned int)XK_Num_Lock);\n if (v0 == v1) numlockmask = 1 << i;\n }\n }\n XFreeModifiermap(v26);\n initfont((unsigned int)font);\n v2 = (uint64_t *)(*((uint64_t *)&dc + 6) + 8 * ColBG);\n *v2 = getcolor((unsigned int)normbgcolor);\n v3 = (uint64_t *)(*((uint64_t *)&dc + 6) + 8 * ColFG);\n *v3 = getcolor((unsigned int)normfgcolor);\n v4 = (uint64_t *)(*((uint64_t *)&dc + 5) + 8 * ColBG);\n *v4 = getcolor((unsigned int)selbgcolor);\n v5 = (uint64_t *)(*((uint64_t *)&dc + 5) + 8 * ColFG);\n *v5 = getcolor((unsigned int)selfgcolor);\n v6 = (uint64_t *)(*((uint64_t *)&dc + 4) + 8 * ColBG);\n *v6 = getcolor((unsigned int)lastbgcolor);\n v7 = (uint64_t *)(*((uint64_t *)&dc + 4) + 8 * ColFG);\n *v7 = getcolor((unsigned int)lastfgcolor);\n v28[2] = True;\n v28[1] = ParentRelative;\n v28[0] = ButtonPressMask | ExposureMask | KeyPressMask;\n mh = dc + 2;\n if (dc + 2 < dword_6D0) mh = dword_6D0;\n x = 0;\n if (topbar)\n v8 = 0;\n else\n v8 = DisplayHeight((unsigned int)dpy, (unsigned int)screen) - mh;\n y = v8;\n mw = DisplayWidth((unsigned int)dpy, (unsigned int)screen);\n if (lines) {\n v9 = lines;\n } else {\n lines = height / (dc + 2);\n v9 = height / (dc + 2);\n }\n if (indicators)\n v10 = 3;\n else\n v10 = 1;\n if (vlist)\n v11 = (v10 + v9) * (dc + 2);\n else\n v11 = mh;\n mh = v11;\n if (topbar)\n v12 = y + yoffset;\n else\n v12 = y - mh + dc + 2 - yoffset;\n v25 = v12;\n if (alignright) {\n if (width)\n v13 = mw - width;\n else\n v13 = 0;\n v14 = v13 - xoffset;\n } else {\n v14 = xoffset;\n }\n x = v14;\n if (width)\n v15 = width;\n else\n v15 = mw;\n mw = v15;\n v16 = CWEventMask | CWBackPixmap | (unsigned int)CWOverrideRedirect;\n v17 = (Visual *)(unsigned int)DefaultVisual((unsigned int)dpy,\n (unsigned int)screen);\n v18 = CopyFromParent;\n v19 = DefaultDepth((unsigned int)dpy, (unsigned int)screen);\n LODWORD(win) =\n XCreateWindow((Display *)(unsigned int)dpy, (unsigned int)root, x, v25,\n mw, mh, 0, v19, v18, v17, v16, (XSetWindowAttributes *)v28);\n v20 = DefaultDepth((unsigned int)dpy, (unsigned int)screen);\n *(&dc + 7) = XCreatePixmap((Display *)(unsigned int)dpy, (unsigned int)root,\n mw, mh, v20);\n *(&dc + 6) = (unsigned int)XCreateGC((Display *)(unsigned int)dpy,\n (unsigned int)root, 0LL, 0LL);\n XSetLineAttributes((Display *)(unsigned int)dpy, (GC)(unsigned int)*(&dc + 6),\n 1u, LineSolid, CapButt, JoinMiter);\n if (!*(&dc + 4))\n XSetFont((Display *)(unsigned int)dpy, (GC)(unsigned int)*(&dc + 6),\n **((unsigned int **)&dc + 1));\n if (maxname) cmdw = textw(maxname);\n if ((int)mw / 3 < cmdw) cmdw = (int)mw / 3;\n if (prompt) promptw = textw(prompt);\n if ((int)mw / 5 < promptw) promptw = (int)mw / 5;\n *(uint64_t *)text = 0LL;\n if (xmms)\n v21 = 8 * maxtokens;\n else\n v21 = 8;\n tokens = (unsigned int)malloc(v21);\n match(text);\n XMapRaised((Display *)(unsigned int)dpy, (unsigned int)win);\n v27 = XAllocClassHint();\n v27->res_name = \"dmenu\";\n v27->res_class = \"DockApp\";\n XSetClassHint((Display *)(unsigned int)dpy, (unsigned int)win, v27);\n XFree(v27);\n return v29 - __readfsqword(40u);\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "void setup(void) {\n int var1, var2, var3, var4;\n type1 *var5;\n type2 var6;\n var5 = XGetModifierMapping(var7);\n for (var1 = 0; var1 < 8; var1++)\n for (var2 = 0; var2 < var5->field1; var2++) {\n if (var5->field2[var1 * var5->field1 + var2] ==\n XKeysymToKeycode(var7, var8))\n var9 = (1 << var1);\n }\n XFreeModifiermap(var5);\n initfont(var10);\n# 930 \"/scratch/repos/new/home/jordi_armengol_estape/c-scraper/outputs/2022-01-22/02-19-57/repos/hakt0r/dmenu-fly/refs/heads/master/dmenu.c\"\n var11.field3.field4[var12] = getcolor(var13);\n var11.field3.field4[var14] = getcolor(var15);\n var11.field5.field4[var12] = getcolor(var16);\n var11.field5.field4[var14] = getcolor(var17);\n var11.field6.field4[var12] = getcolor(var18);\n var11.field6.field4[var14] = getcolor(var19);\n var6.field7 = var20;\n var6.field8 = var21;\n var6.field9 = var22 | var23 | var24;\n var25 = var11.field10.field11 + 2;\n if (var25 < var26) var25 = var26;\n# 968 \"/scratch/repos/new/home/jordi_armengol_estape/c-scraper/outputs/2022-01-22/02-19-57/repos/hakt0r/dmenu-fly/refs/heads/master/dmenu.c\"\n {\n var27 = 0;\n var28 = var29 ? 0 : DisplayHeight(var7, var30) - var25;\n var31 = DisplayWidth(var7, var30);\n }\n var4 = (var32 ? var32 : (var32 = var33 / (var11.field10.field11 + 2))) +\n (var34 ? 3 : 1);\n var25 = var35 ? (var11.field10.field11 + 2) * var4 : var25;\n var3 = var29 ? var28 + var36\n : var28 - var25 + (var11.field10.field11 + 2) - var36;\n var27 = var37 ? var31 - (var38 ? var38 : var31) - var39 : var39;\n var31 = var38 ? var38 : var31;\n var40 = XCreateWindow(\n var7, var41, var27, var3, var31, var25, 0, DefaultDepth(var7, var30),\n var42, DefaultVisual(var7, var30), var43 | var44 | var45, &var6);\n var11.field12 =\n XCreatePixmap(var7, var41, var31, var25, DefaultDepth(var7, var30));\n var11.field13 = XCreateGC(var7, var41, 0, NULL);\n XSetLineAttributes(var7, var11.field13, 1, var46, var47, var48);\n# 999 \"/scratch/repos/new/home/jordi_armengol_estape/c-scraper/outputs/2022-01-22/02-19-57/repos/hakt0r/dmenu-fly/refs/heads/master/dmenu.c\"\n if (!var11.field10.field14)\n XSetFont(var7, var11.field13, var11.field10.field15->field16);\n if (var49) var50 = textw(var49);\n if (var50 > var31 / 3) var50 = var31 / 3;\n if (var51) var52 = textw(var51);\n if (var52 > var31 / 5) var52 = var31 / 5;\n var53[0] = 0;\n var54 = malloc((var55 ? var56 : 1) * sizeof(char *));\n match(var53);\n XMapRaised(var7, var40);\n type3 *var57 = XAllocClassHint();\n var57->field17 = \"dmenu\";\n var57->field18 = \"DockApp\";\n XSetClassHint(var7, var40, var57);\n XFree(var57);\n}", "style": "rule"}, "extra_info": {"index": 93828, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_24__ TYPE_9__ ;\ntypedef struct TYPE_23__ TYPE_8__ ;\ntypedef struct TYPE_22__ TYPE_7__ ;\ntypedef struct TYPE_21__ TYPE_6__ ;\ntypedef struct TYPE_20__ TYPE_5__ ;\ntypedef struct TYPE_19__ TYPE_4__ ;\ntypedef struct TYPE_18__ TYPE_3__ ;\ntypedef struct TYPE_17__ TYPE_2__ ;\ntypedef struct TYPE_16__ TYPE_1__ ;\n\n/* Type definitions */\nstruct TYPE_21__ {char* field17; char* field18; } ;\ntypedef TYPE_6__ type3 ;\nstruct TYPE_22__ {int field9; int /*<<< orphan*/ field8; int /*<<< orphan*/ field7; } ;\ntypedef TYPE_7__ type2 ;\nstruct TYPE_23__ {int field1; scalar_t__* field2; } ;\ntypedef TYPE_8__ type1 ;\nstruct TYPE_20__ {int field11; TYPE_4__* field15; int /*<<< orphan*/ field14; } ;\nstruct TYPE_18__ {void** field4; } ;\nstruct TYPE_17__ {void** field4; } ;\nstruct TYPE_16__ {void** field4; } ;\nstruct TYPE_24__ {TYPE_5__ field10; int /*<<< orphan*/ field13; int /*<<< orphan*/ field12; TYPE_3__ field6; TYPE_2__ field5; TYPE_1__ field3; } ;\nstruct TYPE_19__ {int /*<<< orphan*/ field16; } ;\n\n/* Variables and functions */\n int /*<<< orphan*/ DefaultDepth (int /*<<< orphan*/ ,int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ DefaultVisual (int /*<<< orphan*/ ,int /*<<< orphan*/ ) ; \n int DisplayHeight (int /*<<< orphan*/ ,int /*<<< orphan*/ ) ; \n int DisplayWidth (int /*<<< orphan*/ ,int /*<<< orphan*/ ) ; \n TYPE_6__* XAllocClassHint () ; \n int /*<<< orphan*/ XCreateGC (int /*<<< orphan*/ ,int /*<<< orphan*/ ,int /*<<< orphan*/ ,int /*<<< orphan*/ *) ; \n int /*<<< orphan*/ XCreatePixmap (int /*<<< orphan*/ ,int /*<<< orphan*/ ,int,int,int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ XCreateWindow (int /*<<< orphan*/ ,int /*<<< orphan*/ ,int,int,int,int,int /*<<< orphan*/ ,int /*<<< orphan*/ ,int /*<<< orphan*/ ,int /*<<< orphan*/ ,int,TYPE_7__*) ; \n int /*<<< orphan*/ XFree (TYPE_6__*) ; \n int /*<<< orphan*/ XFreeModifiermap (TYPE_8__*) ; \n TYPE_8__* XGetModifierMapping (int /*<<< orphan*/ ) ; \n scalar_t__ XKeysymToKeycode (int /*<<< orphan*/ ,int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ XMapRaised (int /*<<< orphan*/ ,int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ XSetClassHint (int /*<<< orphan*/ ,int /*<<< orphan*/ ,TYPE_6__*) ; \n int /*<<< orphan*/ XSetFont (int /*<<< orphan*/ ,int /*<<< orphan*/ ,int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ XSetLineAttributes (int /*<<< orphan*/ ,int /*<<< orphan*/ ,int,int /*<<< orphan*/ ,int /*<<< orphan*/ ,int /*<<< orphan*/ ) ; \n void* getcolor (int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ initfont (int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ malloc (int) ; \n int /*<<< orphan*/ match (scalar_t__*) ; \n int textw (scalar_t__) ; \n int /*<<< orphan*/ var10 ; \n TYPE_9__ var11 ; \n size_t var12 ; \n int /*<<< orphan*/ var13 ; \n size_t var14 ; \n int /*<<< orphan*/ var15 ; \n int /*<<< orphan*/ var16 ; \n int /*<<< orphan*/ var17 ; \n int /*<<< orphan*/ var18 ; \n int /*<<< orphan*/ var19 ; \n int /*<<< orphan*/ var20 ; \n int /*<<< orphan*/ var21 ; \n int var22 ; \n int var23 ; \n int var24 ; \n int var25 ; \n int var26 ; \n int var27 ; \n int var28 ; \n scalar_t__ var29 ; \n int /*<<< orphan*/ var30 ; \n int var31 ; \n int var32 ; \n int var33 ; \n scalar_t__ var34 ; \n scalar_t__ var35 ; \n int var36 ; \n scalar_t__ var37 ; \n int var38 ; \n int var39 ; \n int /*<<< orphan*/ var40 ; \n int /*<<< orphan*/ var41 ; \n int /*<<< orphan*/ var42 ; \n int var43 ; \n int var44 ; \n int var45 ; \n int /*<<< orphan*/ var46 ; \n int /*<<< orphan*/ var47 ; \n int /*<<< orphan*/ var48 ; \n scalar_t__ var49 ; \n int var50 ; \n scalar_t__ var51 ; \n int var52 ; \n scalar_t__* var53 ; \n int /*<<< orphan*/ var54 ; \n scalar_t__ var55 ; \n int var56 ; \n int /*<<< orphan*/ var7 ; \n int /*<<< orphan*/ var8 ; \n int var9 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nint main(int argc, const char **argv, const char **envp) {\n uint64_t *v3;\n int result;\n int v5;\n int v6;\n uint64_t v7[5];\n v7[1] = __readfsqword(40u);\n v3 = malloc(16uLL);\n v7[0] = v3;\n result = 1;\n if (v3) {\n v3[1] = 0LL;\n *v3 = 0LL;\n insert_tail(v3, 10LL);\n insert_tail(v7[0], 20LL);\n insert_tail(v7[0], 30LL);\n insert_head(v7, 10LL);\n insert_head(v7, 20LL);\n insert_head(v7, 30LL);\n print_list(v7[0]);\n v5 = remove_head(v7);\n printf(\"%d\\n\", v5);\n v6 = remove_tail(v7[0]);\n printf(\"%d\\n\", v6);\n remove_value(v7, 0LL);\n print_list(v7[0]);\n delete_list(v7[0]);\n return 0;\n }\n return result;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "int main(void) {\n type1 *var1 = NULL;\n var1 = malloc(sizeof(var2));\n if (var1 == NULL) return 1;\n var1->field1 = 0;\n var1->field2 = NULL;\n insert_tail(var1, 10);\n insert_tail(var1, 20);\n insert_tail(var1, 30);\n insert_head(&var1, 10);\n insert_head(&var1, 20);\n insert_head(&var1, 30);\n print_list(var1);\n printf(\"%d\\n\", remove_head(&var1));\n printf(\"%d\\n\", remove_tail(var1));\n remove_value(&var1, 0);\n print_list(var1);\n delete_list(var1);\n return 0;\n}", "style": "rule"}, "extra_info": {"index": 94349, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_10__ TYPE_1__ ;\n\n/* Type definitions */\ntypedef int /*<<< orphan*/ var2 ;\nstruct TYPE_10__ {int /*<<< orphan*/ * field2; scalar_t__ field1; } ;\ntypedef TYPE_1__ type1 ;\n\n/* Variables and functions */\n int /*<<< orphan*/ delete_list (TYPE_1__*) ; \n int /*<<< orphan*/ insert_head (TYPE_1__**,int) ; \n int /*<<< orphan*/ insert_tail (TYPE_1__*,int) ; \n TYPE_1__* malloc (int) ; \n int /*<<< orphan*/ print_list (TYPE_1__*) ; \n int /*<<< orphan*/ printf (char*,int) ; \n int remove_head (TYPE_1__**) ; \n int remove_tail (TYPE_1__*) ; \n int /*<<< orphan*/ remove_value (TYPE_1__**,int /*<<< orphan*/ ) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long message_decode(uint8_t *a1, unsigned int *a2) {\n long long v2;\n uint8_t *v3;\n unsigned int v4;\n char v5;\n long long v6;\n char v7;\n unsigned int v8;\n int v9;\n __m128i *v10;\n char *v11;\n char *v12;\n __m128i *v13;\n uint8_t *v14;\n long long v15;\n __m128i *v16;\n __m128i v17;\n int v18;\n long long v19;\n char *v20;\n unsigned int v21;\n unsigned int v22;\n int v23;\n int v24;\n long long v25;\n char *v27;\n long long v28;\n char v29;\n __m128i *v30;\n v2 = 0LL;\n v3 = a1;\n v4 = 0;\n if (*a1 != 255) {\n *a2 = -1;\n return v2;\n }\n do {\n v5 = v3[1];\n if (v5 != -86 && v5 != -2) {\n v6 = 0LL;\n do {\n v7 = v3[v6 + 2];\n v8 = v6;\n v9 = v6++;\n } while (v7 != -86 && v7 != -2);\n v10 = (__m128i *)malloc(v8 + 2);\n bzero(v10, (unsigned int)(v9 + 2));\n v13 = v10;\n v14 = v3 + 1;\n if ((unsigned long long)((char *)v10 - (v3 + 2)) <= 14 || v8 <= 6) {\n v27 = (char *)v10;\n v28 = v3 - (uint8_t *)v10;\n v15 = v8 + 1;\n v11 = &v10->m128i_i8[v15];\n do {\n v29 = v27[v28 + 1];\n *v27++ = v29;\n } while (v27 != v11);\n goto LABEL_22;\n }\n LODWORD(v15) = v8 + 1;\n if (v8 <= 14) {\n v22 = v8 + 1;\n v12 = (char *)v10;\n v20 = v3 + 1;\n v18 = 0;\n v19 = 0LL;\n } else {\n v16 = v10;\n do {\n v17 = _mm_loadu_si128(\n (const __m128i *)&v16->m128i_i8[v3 - (uint8_t *)v10 + 1]);\n ++v16;\n v16[-1] = v17;\n } while (&v10[(unsigned int)v15 >> 4] != v16);\n v18 = v15 & 4294967280;\n v19 = (unsigned int)v15 & 4294967280;\n v20 = &v14[v19];\n v12 = &v10->m128i_i8[v19];\n if ((uint32_t)v15 == (v15 & 4294967280)) goto LABEL_22;\n v21 = v8 - v18;\n v22 = v21 + 1;\n if (v21 <= 6) {\n LABEL_15:\n *v12 = *v20;\n if (v9 > v18) {\n v12[1] = v20[1];\n if (v9 > v18 + 1) {\n v12[2] = v20[2];\n if (v9 > v18 + 2) {\n v12[3] = v20[3];\n v23 = v18 + 4;\n if (v9 > v18 + 3) {\n v24 = v18 + 5;\n v12[4] = v20[4];\n if (v9 > v23) {\n v12[5] = v20[5];\n if (v9 > v24) v12[6] = v20[6];\n }\n }\n }\n }\n }\n goto LABEL_22;\n }\n }\n *(long long *)((char *)v10->m128i_i64 + v19) = *(uint64_t *)&v3[v19 + 1];\n v18 += v22 & 4294967288;\n v20 += v22 & 4294967288;\n v12 += v22 & 4294967288;\n if (v22 != (v22 & 4294967288)) goto LABEL_15;\n LABEL_22:\n v3 = &v14[(unsigned int)v15];\n goto LABEL_23;\n }\n v30 = (__m128i *)malloc(1uLL);\n bzero(v30, 1uLL);\n ++v3;\n v13 = v30;\n LABEL_23:\n v25 = v4++;\n v2 = matrix_append(v2, v25, v13, v14, v11, v12);\n } while (*v3 != 254);\n if (a2) *a2 = v4;\n return v2;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "char **message_decode(char *var1, int *var2) {\n char **var3 = NULL;\n int var4 = 0;\n unsigned char *var5 = var1;\n if (*var5 != 0xFF) {\n *var2 = -1;\n return NULL;\n } else {\n do {\n var5++;\n int var6 = 0;\n unsigned char *var7 = var5;\n while (*var7 != 0xAA && *var7 != 0xFE) {\n var6++;\n var7++;\n }\n int var8;\n char *var9 = (char *)malloc(sizeof(char) * var6 + 1);\n bzero(var9, var6 + 1);\n char *var10 = var9;\n for (var8 = 0; var8 < var6; var8++) {\n *var10 = *var5;\n var10++;\n var5++;\n }\n var10 = '\\0';\n var3 = matrix_append(var3, var4, var9);\n var4++;\n } while (*var5 != 0xFE);\n }\n if (var2 != NULL) {\n *var2 = var4;\n }\n return var3;\n}", "style": "rule"}, "extra_info": {"index": 36084, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\n\n/* Variables and functions */\n int /*<<< orphan*/ bzero (char*,int) ; \n scalar_t__ malloc (int) ; \n char** matrix_append (char**,int,char*) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nint sb_dump(uint32_t *a1) {\n puts(\"Superblock informaton:\");\n printf(\"EXT2 Magic\\t%x\\n\", *a1);\n printf(\"Inodes Count\\t%d\\t\", a1[1]);\n printf(\"Blocks Count\\t%d\\t\", a1[2]);\n printf(\"RBlock Count\\t%d\\n\", a1[3]);\n printf(\"FBlock Count\\t%d\\t\", a1[4]);\n printf(\"FInode Count\\t%d\\t\", a1[5]);\n printf(\"First Data Block\\t%d\\n\", a1[6]);\n printf(\"Block Size\\t%d\\t\", 1024 << a1[7]);\n printf(\"Fragment Sz \\t%d\\t\", 1024 << a1[8]);\n printf(\"Block/Group\\t%d\\n\", a1[9]);\n printf(\"Frag/Group \\t%d\\t\", a1[10]);\n printf(\"Inode/Group\\t%d\\t\", a1[11]);\n printf(\"mtime\\t%x\\n\", a1[12]);\n printf(\"wtime\\t%x\\t\", a1[13]);\n printf(\"Mount #\\t%x\\t\", a1[14]);\n printf(\"Max mounts\\t%x\\n\", a1[15]);\n printf(\"State\\t%x\\t\", a1[16]);\n printf(\"Errors\\t%x\\t\", a1[17]);\n printf(\"Minor\\t%x\\n\", a1[18]);\n printf(\"Last Chk\\t%x\\t\", a1[19]);\n printf(\"Chk int\\t%x\\t\", a1[20]);\n printf(\"OS\\t%x\\n\", a1[21]);\n printf(\"Rev #\\t%x\\t\", a1[22]);\n printf(\"ResUID\\t%x\\t\", a1[23]);\n return printf(\"ResGID\\t%x\\n\", a1[24]);\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "void sb_dump(struct type1* var1) {\n printf(\"Superblock informaton:\\n\");\n printf(\"EXT2 Magic\\t%x\\n\", var1->field1);\n printf(\"Inodes Count\\t%d\\t\", var1->field2);\n printf(\"Blocks Count\\t%d\\t\", var1->field3);\n printf(\"RBlock Count\\t%d\\n\", var1->field4);\n printf(\"FBlock Count\\t%d\\t\", var1->field5);\n ;\n printf(\"FInode Count\\t%d\\t\", var1->field6);\n printf(\"First Data Block\\t%d\\n\", var1->field7);\n printf(\"Block Size\\t%d\\t\", 1024 << var1->field8);\n printf(\"Fragment Sz \\t%d\\t\", 1024 << var1->field9);\n printf(\"Block/Group\\t%d\\n\", var1->field10);\n printf(\"Frag/Group \\t%d\\t\", var1->field11);\n printf(\"Inode/Group\\t%d\\t\", var1->field12);\n printf(\"mtime\\t%x\\n\", var1->field13);\n printf(\"wtime\\t%x\\t\", var1->field14);\n printf(\"Mount #\\t%x\\t\", var1->field15);\n printf(\"Max mounts\\t%x\\n\", var1->field16);\n printf(\"State\\t%x\\t\", var1->field17);\n printf(\"Errors\\t%x\\t\", var1->field18);\n printf(\"Minor\\t%x\\n\", var1->field19);\n printf(\"Last Chk\\t%x\\t\", var1->field20);\n printf(\"Chk int\\t%x\\t\", var1->field21);\n printf(\"OS\\t%x\\n\", var1->field22);\n printf(\"Rev #\\t%x\\t\", var1->field23);\n printf(\"ResUID\\t%x\\t\", var1->field24);\n printf(\"ResGID\\t%x\\n\", var1->field25);\n}", "style": "rule"}, "extra_info": {"index": 6767, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\nstruct type1 {int field1; int field2; int field3; int field4; int field5; int field6; int field7; int field8; int field9; int field10; int field11; int field12; int field13; int field14; int field15; int field16; int field17; int field18; int field19; int field20; int field21; int field22; int field23; int field24; int field25; } ;\n\n/* Variables and functions */\n int /*<<< orphan*/ printf (char*,...) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long mc_rand_prime(int a1, int a2) {\n int v2;\n int v3;\n unsigned int v4;\n unsigned int v5;\n v2 = 0;\n if (a1 >= 0) v2 = a1;\n v3 = 2147483647;\n v4 = v2;\n if (a2 > 0) {\n v3 = a2;\n if (v2 > a2) {\n v4 = a2;\n v3 = v2;\n }\n }\n if ((int)(v3 - v4) <= 3) {\n return (unsigned int)-1;\n } else {\n LABEL_7:\n v5 = mc_rand_odd(v4, (unsigned int)v3);\n while (!(unsigned int)mc_isprime(v5)) {\n v5 += 2;\n if (v3 <= (int)v5) goto LABEL_7;\n }\n }\n return v5;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "int mc_rand_prime(int var1, int var2) {\n int var3;\n var1 = (var1 > 0) ? var1 : 0;\n var2 = (var2 > 0) ? var2 : 0x7FFFFFFF;\n if (var1 > var2) {\n var3 = var2;\n var2 = var1;\n var1 = var3;\n }\n if ((var2 - var1) <= 3) {\n return -1;\n }\n var3 = mc_rand_odd(var1, var2);\n while (!mc_isprime(var3)) {\n var3 += 2;\n if (var3 >= var2) {\n var3 = mc_rand_odd(var1, var2);\n }\n }\n return var3;\n}", "style": "rule"}, "extra_info": {"index": 43116, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\n\n/* Variables and functions */\n int /*<<< orphan*/ mc_isprime (int) ; \n int mc_rand_odd (int,int) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nint printLine(char a1, int a2) {\n int i;\n if (a2 > 0) {\n for (i = 0; i != a2; ++i) putchar(a1);\n }\n return putchar(10);\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "static void printLine(char var1, int var2) {\n int var3;\n for (var3 = 0; var3 < var2; var3++) {\n putchar(var1);\n }\n putchar('\\n');\n}", "style": "rule"}, "extra_info": {"index": 5723, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\n\n/* Variables and functions */\n int /*<<< orphan*/ putchar (char) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nuint8_t test_char() {\n unsigned int v0;\n bool v1;\n unsigned int v2;\n int v3;\n unsigned int v4;\n int v5;\n unsigned int v6;\n int v7;\n unsigned int v8;\n int v9;\n unsigned int v10;\n int v11;\n unsigned int v12;\n int v13;\n unsigned int v14;\n int v15;\n unsigned int v16;\n int v17;\n unsigned int v18;\n int v19;\n unsigned int v20;\n int v21;\n unsigned int v22;\n int v23;\n unsigned int v24;\n int v25;\n unsigned int v26;\n v0 = TEST_char_eq(97LL, 97LL);\n v1 = (unsigned int)TEST(1LL, v0) == 0;\n v2 = TEST_char_eq(97LL, 65LL);\n v3 = v1 | ((unsigned int)TEST(0LL, v2) == 0);\n v4 = TEST_char_ne(97LL, 99LL);\n v5 = ((unsigned int)TEST(1LL, v4) == 0) | v3;\n v6 = TEST_char_ne(101LL, 101LL);\n v7 = ((unsigned int)TEST(0LL, v6) == 0) | v5;\n v8 = TEST_char_lt(105LL, 120LL);\n v9 = ((unsigned int)TEST(1LL, v8) == 0) | v7;\n v10 = TEST_char_lt(120LL, 105LL);\n v11 = ((unsigned int)TEST(0LL, v10) == 0) | v9;\n v12 = TEST_char_le(105LL, 120LL);\n v13 = ((unsigned int)TEST(1LL, v12) == 0) | v11;\n v14 = TEST_char_le(110LL, 110LL);\n v15 = ((unsigned int)TEST(1LL, v14) == 0) | v13;\n v16 = TEST_char_le(120LL, 105LL);\n v17 = ((unsigned int)TEST(0LL, v16) == 0) | v15;\n v18 = TEST_char_gt(119LL, 110LL);\n v19 = ((unsigned int)TEST(1LL, v18) == 0) | v17;\n v20 = TEST_char_gt(110LL, 119LL);\n v21 = ((unsigned int)TEST(0LL, v20) == 0) | v19;\n v22 = TEST_char_ge(119LL, 110LL);\n v23 = ((unsigned int)TEST(1LL, v22) == 0) | v21;\n v24 = TEST_char_ge(112LL, 112LL);\n v25 = ((unsigned int)TEST(1LL, v24) == 0) | v23;\n v26 = TEST_char_ge(110LL, 119LL);\n return (v25 | ((unsigned int)TEST(0LL, v26) == 0)) == 0;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "static int test_char(void) {\n if (!TEST(1, TEST_char_eq('a', 'a')) | !TEST(0, TEST_char_eq('a', 'A')) |\n !TEST(1, TEST_char_ne('a', 'c')) | !TEST(0, TEST_char_ne('e', 'e')) |\n !TEST(1, TEST_char_lt('i', 'x')) | !TEST(0, TEST_char_lt('x', 'i')) |\n !TEST(1, TEST_char_le('i', 'x')) | !TEST(1, TEST_char_le('n', 'n')) |\n !TEST(0, TEST_char_le('x', 'i')) | !TEST(1, TEST_char_gt('w', 'n')) |\n !TEST(0, TEST_char_gt('n', 'w')) | !TEST(1, TEST_char_ge('w', 'n')) |\n !TEST(1, TEST_char_ge('p', 'p')) | !TEST(0, TEST_char_ge('n', 'w')))\n goto err;\n return 1;\nerr:\n return 0;\n}", "style": "rule"}, "extra_info": {"index": 99401, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\n\n/* Variables and functions */\n int /*<<< orphan*/ TEST (int,int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ TEST_char_eq (char,char) ; \n int /*<<< orphan*/ TEST_char_ge (char,char) ; \n int /*<<< orphan*/ TEST_char_gt (char,char) ; \n int /*<<< orphan*/ TEST_char_le (char,char) ; \n int /*<<< orphan*/ TEST_char_lt (char,char) ; \n int /*<<< orphan*/ TEST_char_ne (char,char) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nvoid resize_mask(int a1, double a2) {\n long long v2;\n long long v3;\n long long v4;\n uint32_t *v5;\n int v6;\n long long i;\n long long v8;\n long long v9;\n int v10;\n long long v11;\n int v12;\n uint32_t *v13;\n long long v14;\n if (EXPLORE == 1 && numf == a1) {\n if (D2BINS <= 0) {\n EXPLORE = 0;\n } else {\n v2 = mask;\n v3 = HIGHESTESTATE;\n v4 = 0LL;\n v5 = (uint32_t *)LOWESTESTATE;\n do {\n v6 = D1BINS;\n for (i = 0LL; v6 > (int)i; ++i) {\n if (!*(uint32_t *)(*(uint64_t *)(v2 + 8 * i) + 4 * v4) &&\n *(uint32_t *)(v3 + 4 * v4) > (int)i) {\n v5[v4] = i;\n v6 = D1BINS;\n }\n }\n v5[v4] = v6 - (int)((double)(v6 - v5[v4]) * a2);\n ++v4;\n } while (D2BINS > (int)v4);\n EXPLORE = 0;\n if (D2BINS > 0) {\n v8 = wllng;\n v9 = 0LL;\n v10 = 0;\n if (D1BINS > 0) {\n do {\n v11 = 0LL;\n do {\n while (1) {\n v13 = (uint32_t *)(v9 + *(uint64_t *)(v2 + 8 * v11));\n if (*v5 > (int)v11 || *(uint32_t *)(v3 + v9) <= (int)v11) break;\n *v13 = 1;\n v12 = D1BINS;\n if (D1BINS <= (int)++v11) goto LABEL_19;\n }\n *v13 = 0;\n v14 = *(uint64_t *)(v8 + 8 * v11++);\n *(uint64_t *)(v14 + 2 * v9) = 0LL;\n v12 = D1BINS;\n } while (D1BINS > (int)v11);\n LABEL_19:\n if (++v10 >= D2BINS) break;\n ++v5;\n v9 += 4LL;\n } while (v12 > 0);\n }\n }\n }\n }\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "void resize_mask(double var1, int var2) {\n int var3, var4;\n if (var5 == 1 && var6 == var2) {\n for (var4 = 0; var4 < var7; var4++) {\n for (var3 = 0; var3 < var8; var3++) {\n if (var9[var3][var4] == 0 && var3 < var10[var4]) {\n var11[var4] = var3;\n }\n }\n var11[var4] = var11[var4] + (var8 - var11[var4]) -\n (int)(var1 * (var8 - var11[var4]));\n }\n var5 = 0;\n for (var4 = 0; var4 < var7; var4++)\n for (var3 = 0; var3 < var8; var3++) {\n if (var3 >= var11[var4] && var3 < var10[var4]) {\n var9[var3][var4] = 1;\n } else {\n var9[var3][var4] = 0;\n var12[var3][var4] = 0.0;\n }\n }\n };\n}", "style": "rule"}, "extra_info": {"index": 21083, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\n\n/* Variables and functions */\n int* var10 ; \n int* var11 ; \n double** var12 ; \n int var5 ; \n int var6 ; \n int var7 ; \n int var8 ; \n int** var9 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long DMD_setClippingArea(long long a1, long long a2, long long a3,\n long long a4) {\n if (!initialized) return 1LL;\n if (a3 + a1 > dimensions[0] || a4 + a2 > dimensions[1]) return 4LL;\n if (!a3 || !a4) return 5LL;\n DMDIF_writeReg(69LL, a1);\n DMDIF_writeReg(70LL, a1 + a3 - 1);\n DMDIF_writeReg(68LL, a2 | ((a2 + a4 - 1) << 8));\n dimensions[5] = a1;\n dimensions[4] = a2;\n dimensions[3] = a3;\n dimensions[2] = a4;\n return 0LL;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "type1 DMD_setClippingArea(uint16_t var1, uint16_t var2, uint16_t var3,\n uint16_t var4) {\n uint16_t var5;\n uint16_t var6;\n uint16_t var7;\n if (!var8) {\n return (0x00000000 | 0x0001);\n }\n if (var1 + var3 > var9.field1 || var2 + var4 > var9.field2) {\n return (0x00000000 | 0x0004);\n }\n if (var3 == 0 || var4 == 0) {\n return (0x00000000 | 0x0005);\n }\n var6 = var1 + var3 - 1;\n var7 = var2 + var4 - 1;\n DMDIF_writeReg(0x45, var1);\n DMDIF_writeReg(0x46, var6);\n var5 = var7 << 8;\n var5 |= var2 << 0;\n DMDIF_writeReg(0x44, var5);\n var9.field3 = var1;\n var9.field4 = var2;\n var9.field5 = var3;\n var9.field6 = var4;\n return 0x00000000;\n}", "style": "rule"}, "extra_info": {"index": 108597, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_2__ TYPE_1__ ;\n\n/* Type definitions */\ntypedef scalar_t__ uint16_t ;\ntypedef int type1 ;\nstruct TYPE_2__ {scalar_t__ field1; scalar_t__ field2; scalar_t__ field6; scalar_t__ field5; scalar_t__ field4; scalar_t__ field3; } ;\n\n/* Variables and functions */\n int /*<<< orphan*/ DMDIF_writeReg (int,scalar_t__) ; \n int /*<<< orphan*/ var8 ; \n TYPE_1__ var9 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long MP4AddTrackReference(long long a1, long long a2, long long a3,\n long long a4) {\n long long v7;\n long long TrackID;\n unsigned long long v9;\n v9 = __readfsqword(40u);\n TrackID = MP4NoErr;\n if (!a1 || !a2) return MP4BadParamErr;\n TrackID = MP4GetTrackID(a2, &v7);\n if (!TrackID) {\n if (v7)\n return MP4AddTrackReferenceWithID(a1, v7, a3, a4);\n else\n return MP4InvalidMediaErr;\n }\n return TrackID;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "extern type1 MP4AddTrackReference(type2 var1, type2 var2, type3 var3,\n type3 *var4) {\n type1 var5;\n type3 var6;\n var5 = var7;\n if ((var1 == 0) || (var2 == 0)) {\n var5 = (var8);\n goto bail;\n };\n var5 = MP4GetTrackID(var2, &var6);\n if (var5) goto bail;\n if (var6 == 0) {\n var5 = (var9);\n goto bail;\n };\n var5 = MP4AddTrackReferenceWithID(var1, var6, var3, var4);\n if (var5) goto bail;\nbail:;\n return var5;\n}", "style": "rule"}, "extra_info": {"index": 64313, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\ntypedef scalar_t__ type3 ;\ntypedef scalar_t__ type2 ;\ntypedef scalar_t__ type1 ;\n\n/* Variables and functions */\n scalar_t__ MP4AddTrackReferenceWithID (scalar_t__,scalar_t__,scalar_t__,scalar_t__*) ; \n scalar_t__ MP4GetTrackID (scalar_t__,scalar_t__*) ; \n scalar_t__ var7 ; \n scalar_t__ var8 ; \n scalar_t__ var9 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nint main(int argc, const char **argv, const char **envp) {\n int v3;\n int v4;\n int v5;\n int v7;\n unsigned long long v8;\n v8 = __readfsqword(40u);\n do {\n printf(\"Inserisci numero della tabellina tra 2 e 10: \");\n scanf(\"%d\", &v7);\n v3 = v7;\n } while ((unsigned int)(v7 - 2) > 8);\n v4 = 1;\n while (1) {\n v5 = v4 * v3;\n ++v4;\n printf(\" %d\", v5);\n if (v4 == 11) break;\n v3 = v7;\n }\n return 0;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "main() {\n int var1;\n int var2;\n int var3;\n do {\n printf(\"Inserisci numero della tabellina tra 2 e 10: \");\n scanf(\"%d\", &var1);\n } while ((var1 > 10) || (var1 < 2));\n var2 = 1;\n while (var2 <= 10) {\n var3 = var1 * var2;\n printf(\" %d\", var3);\n var2++;\n }\n}", "style": "rule"}, "extra_info": {"index": 84592, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\n\n/* Variables and functions */\n int /*<<< orphan*/ printf (char*,...) ; \n int /*<<< orphan*/ scanf (char*,int*) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nuint64_t *stack_i_init(int a1) {\n uint64_t *v1;\n void *v2;\n void *v4;\n if (a1 < 0) {\n print_error_msg(\"Error: stack_init: negative size!\");\n return 0LL;\n } else {\n v1 = malloc(16uLL);\n if (v1) {\n v2 = calloc((unsigned int)(a1 + 1), 4uLL);\n v1[1] = v2;\n if (v2) {\n *(uint32_t *)v1 = a1;\n *((uint32_t *)v1 + 1) = -1;\n } else {\n print_error_msg(\"Error: stack_i_init: calloc() failed!\");\n v4 = v1;\n v1 = 0LL;\n free(v4);\n }\n } else {\n print_error_msg(\"Error: stack_i_init: malloc() failed!\");\n }\n return v1;\n }\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "type1 *stack_i_init(int var1) {\n if (var1 < 0) {\n print_error_msg(\"Error: stack_init: negative size!\");\n return NULL;\n }\n type1 *var2 = malloc(sizeof(var3));\n if (var2 == NULL) {\n print_error_msg(\"Error: stack_i_init: malloc() failed!\");\n return NULL;\n }\n var2->field1 = calloc(var1 + 1, sizeof(int));\n if (var2->field1 == NULL) {\n print_error_msg(\"Error: stack_i_init: calloc() failed!\");\n free(var2);\n return NULL;\n }\n var2->field2 = var1;\n var2->field3 = -1;\n return var2;\n}", "style": "rule"}, "extra_info": {"index": 85893, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_5__ TYPE_1__ ;\n\n/* Type definitions */\ntypedef int /*<<< orphan*/ var3 ;\nstruct TYPE_5__ {int field2; int field3; int /*<<< orphan*/ * field1; } ;\ntypedef TYPE_1__ type1 ;\n\n/* Variables and functions */\n int /*<<< orphan*/ * calloc (int,int) ; \n int /*<<< orphan*/ free (TYPE_1__*) ; \n TYPE_1__* malloc (int) ; \n int /*<<< orphan*/ print_error_msg (char*) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long dbg_print_addr(int *a1) {\n int v1;\n int v2;\n int v3;\n long long v4;\n int v5;\n if (a1) {\n v1 = *a1;\n v2 = *a1 + 65535;\n v3 = *a1 + 16777215;\n if (*a1 >= 0) {\n v2 = *a1;\n v3 = *a1;\n }\n v4 = (unsigned char)(((unsigned int)(v2 >> 31) >> 24) + BYTE2(v2)) -\n ((unsigned int)(v2 >> 31) >> 24);\n v5 = v1 + 255;\n if (v1 >= 0) v5 = *a1;\n printf(\"%u.%u.%u.%u\\n\", (unsigned int)(v1 % 256),\n (unsigned char)(((unsigned int)(v5 >> 31) >> 24) + BYTE1(v5)) -\n ((unsigned int)(v5 >> 31) >> 24),\n v4, (unsigned int)(v3 >> 24));\n return 0LL;\n } else {\n puts(\"null addr\");\n return 0LL;\n }\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "int dbg_print_addr(struct type1 *var1) {\n type2 var2;\n if (var1 == NULL) {\n printf(\"null addr\\n\");\n return 0;\n }\n var2 = var1->field1.field2;\n printf(\"%u.%u.%u.%u\\n\", var2 % (256), var2 / 256 % 256,\n var2 / 256 / 256 % 256, var2 / 256 / 256 / 256);\n return 0;\n}", "style": "rule"}, "extra_info": {"index": 22258, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_2__ TYPE_1__ ;\n\n/* Type definitions */\ntypedef int type2 ;\nstruct TYPE_2__ {int field2; } ;\nstruct type1 {TYPE_1__ field1; } ;\n\n/* Variables and functions */\n int /*<<< orphan*/ printf (char*,...) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nunsigned long long search_symbol() {\n int *v0;\n long long v1;\n uint64_t *v2;\n int *v3;\n long long v4;\n unsigned int v5;\n unsigned int v6;\n long long v7;\n unsigned int v8;\n unsigned long long v10;\n unsigned long long v11;\n unsigned long long v12;\n unsigned long long v13;\n unsigned int v14;\n unsigned int v15;\n long long v16;\n unsigned int v17;\n unsigned int v18;\n unsigned int v19;\n char s[64];\n char dest[72];\n unsigned long long v22;\n v22 = __readfsqword(40u);\n printf(\"\\t[ss] Symbol Name: \");\n fgets(s, 64, (FILE *)(unsigned int)stdin);\n putchar(10);\n v0 = *(int **)(dsyms + 24);\n if (v0) {\n v10 = *(uint64_t *)(dsyms + 32);\n v11 = *(uint64_t *)(dsyms + 40);\n v12 = v10 / v11;\n printf(\"\\t[ss] ==== %lu Dynamic Linked Symbols ====\\n\", v10 / v11);\n if (v10 >= v11) {\n v13 = 0LL;\n do {\n while (1) {\n strncpy(dest, (const char *)(*(uint64_t *)dsyms + *v0), 64uLL);\n v14 = strlen(s);\n v15 = strlen(dest);\n if ((int)Levenshtein(dest, v15, s, v14) <= 3) break;\n ++v13;\n v0 += 6;\n if (v12 <= v13) goto LABEL_2;\n }\n v16 = (unsigned int)v0[4];\n ++v13;\n v0 += 6;\n v19 = st_bind_lookup(v16);\n v17 = st_type_lookup((unsigned int)*(v0 - 2));\n printf(\"\\tName: %s Addr: 0x%016lx Section: %s Type: %s Bind: %s\\n\",\n dest, (unsigned int)*(v0 - 1),\n (const char *)*(unsigned int *)(SECTIONS +\n 4LL * *((uint64_t *)v0 - 2)),\n (const char *)v17, (const char *)v19);\n } while (v12 > v13);\n }\n }\nLABEL_2:\n if (*(uint64_t *)(ssyms + 16)) {\n v1 = *(uint32_t *)(ssyms + 24) / *(uint32_t *)(ssyms + 28);\n printf(\"\\t[ss] ==== %lu Static Linked Symbols ====\\n\", v1);\n v2 = (uint64_t *)ssyms;\n v3 = *(int **)(ssyms + 16);\n if (v1) {\n v4 = 0LL;\n while (1) {\n strncpy(dest, (const char *)(*v2 + *v3), 64uLL);\n v5 = strlen(s);\n v6 = strlen(dest);\n if ((int)Levenshtein(dest, v6, s, v5) > 2) {\n ++v4;\n v3 += 6;\n if (v1 == v4) return v22 - __readfsqword(40u);\n } else {\n v7 = (unsigned int)v3[4];\n ++v4;\n v3 += 6;\n v18 = st_bind_lookup(v7);\n v8 = st_type_lookup((unsigned int)*(v3 - 2));\n printf(\"\\tName: %s Addr: 0x%016lx Section: %s Type: %s Bind: %s\\n\",\n dest, (unsigned int)*(v3 - 1),\n (const char *)*(unsigned int *)(SECTIONS +\n 4LL * *((uint64_t *)v3 - 2)),\n (const char *)v8, (const char *)v18);\n if (v1 == v4) return v22 - __readfsqword(40u);\n }\n v2 = (uint64_t *)ssyms;\n }\n }\n } else {\n puts(\"\\t[ss] No static symbols found, was the binary stripped?\");\n }\n return v22 - __readfsqword(40u);\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "void search_symbol(void) {\n char var1[64];\n printf(\"\\t[ss] Symbol Name: \");\n fgets(var1, 64, var2);\n printf(\"\\n\");\n if (var3[1].field1 != 0) {\n uint64_t var4 = (var3[1].field2 / var3[1].field3);\n type1* var5 = (type1*)var3[1].field1;\n printf(\"\\t[ss] ==== %lu Dynamic Linked Symbols ====\\n\", var4);\n int var6 = 0;\n for (uint64_t var7 = 0; var7 < var4; var7++) {\n char var8[64];\n strncpy(var8, (((char*)var3[0].field1) + var5[var7].field4), 64);\n if ((var6 = Levenshtein(var8, strlen(var8), var1, strlen(var1))) <= 3) {\n printf(\"\\tName: %s Addr: 0x%016lx Section: %s Type: %s Bind: %s\\n\",\n var8, var5[var7].field5, var9[var5[var7].field6].field7,\n st_type_lookup(var5[var7].field8),\n st_bind_lookup(var5[var7].field8));\n }\n }\n }\n if (var10[1].field1 != 0) {\n uint64_t var4 = (var10[1].field2 / var10[1].field3);\n printf(\"\\t[ss] ==== %lu Static Linked Symbols ====\\n\", var4);\n type1* var5 = (type1*)var10[1].field1;\n int var6 = 0;\n for (uint64_t var7 = 0; var7 < var4; var7++) {\n char var8[64];\n strncpy(var8, (((char*)var10[0].field1) + var5[var7].field4), 64);\n if ((var6 = Levenshtein(var8, strlen(var8), var1, strlen(var1))) <= 2) {\n printf(\"\\tName: %s Addr: 0x%016lx Section: %s Type: %s Bind: %s\\n\",\n var8, var5[var7].field5, var9[var5[var7].field6].field7,\n st_type_lookup(var5[var7].field8),\n st_bind_lookup(var5[var7].field8));\n }\n }\n } else {\n printf(\"\\t[ss] No static symbols found, was the binary stripped?\\n\");\n }\n}", "style": "rule"}, "extra_info": {"index": 33338, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_8__ TYPE_4__ ;\ntypedef struct TYPE_7__ TYPE_3__ ;\ntypedef struct TYPE_6__ TYPE_2__ ;\ntypedef struct TYPE_5__ TYPE_1__ ;\n\n/* Type definitions */\ntypedef size_t uint64_t ;\nstruct TYPE_5__ {int field4; size_t field6; int /*<<< orphan*/ field8; int /*<<< orphan*/ field5; } ;\ntypedef TYPE_1__ type1 ;\nstruct TYPE_8__ {scalar_t__ field1; int field2; int field3; } ;\nstruct TYPE_7__ {scalar_t__ field1; size_t field2; size_t field3; } ;\nstruct TYPE_6__ {int /*<<< orphan*/ field7; } ;\n\n/* Variables and functions */\n int Levenshtein (char*,int /*<<< orphan*/ ,char*,int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ fgets (char*,int,int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ printf (char*,...) ; \n int /*<<< orphan*/ st_bind_lookup (int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ st_type_lookup (int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ strlen (char*) ; \n int /*<<< orphan*/ strncpy (char*,char*,int) ; \n TYPE_4__* var10 ; \n int /*<<< orphan*/ var2 ; \n TYPE_3__* var3 ; \n TYPE_2__* var9 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long Item_TextScroll_Paint(unsigned int *a1) {\n unsigned int *v1;\n double v2;\n float v3;\n double v4;\n double v5;\n double v6;\n double v7;\n long long result;\n long long v9;\n float v10;\n float v11;\n long long v12;\n float v13;\n long long v14;\n float v15;\n long long v16;\n float v17;\n float v18;\n float v19;\n float v20;\n float v21;\n float v22;\n v1 = (unsigned int *)*((uint64_t *)a1 + 7);\n v2 = *((double *)a1 + 2) + *((double *)a1 + 3) - 16.0 - 1.0;\n v3 = COERCE_FLOAT(_mm_cvtsi128_si32((__m128i)*v1));\n *(float *)&v2 = v2;\n v18 = (float)(int)(a1[8] + 1);\n v17 = *(float *)&v2;\n (*(void (**)(uint64_t, double, float, double, double))(DC + 24))(\n *(unsigned int *)(DC + 20), v2, v18, 16.0, 16.0);\n v4 = *((double *)a1 + 5) - 32.0;\n v1[1] = v1[2];\n *(float *)&v4 = v4;\n v22 = *(float *)&v4;\n v19 = v18 + 15.0;\n (*(void (**)(uint64_t, float, float, double, double))(DC + 24))(\n *(unsigned int *)(DC + 16), v17, v19, 16.0, (float)(*(float *)&v4 + 1.0));\n *(uint64_t *)&v5 = LODWORD(v22);\n v20 = (float)(v22 - 1.0) + v19;\n *(float *)&v5 = v20;\n (*(void (**)(uint64_t, float, double, double, double))(DC + 24))(\n *(unsigned int *)(DC + 12), v17, v5, 16.0, 16.0);\n v6 = Item_TextScroll_ThumbDrawPosition(a1);\n v7 = v20 - 16.0 - 1.0;\n if (*(float *)&v6 > v7) {\n HIDWORD(v6) = 0;\n *(float *)&v6 = v7;\n }\n (*(void (**)(uint64_t, float, double, double, double))(DC + 24))(\n *(unsigned int *)(DC + 8), v17, v6, 16.0, 16.0);\n result = a1[8] + 1;\n v9 = (int)v1[2];\n v10 = (float)(int)result;\n v11 = *((double *)a1 + 2) + 1.0;\n v12 = 8 * v9;\n v13 = *((double *)a1 + 5) - 2.0;\n if (v3 > (float)(int)v1[2]) {\n do {\n result = *((uint64_t *)v1 + 2);\n v14 = *(uint64_t *)(result + v12);\n if (v14) {\n v21 = v13;\n (*(void (**)(uint64_t, uint64_t, long long, uint64_t, uint64_t,\n uint64_t, float, uint64_t))DC)(a1[12], a1[2], v14, 0LL,\n 0LL, a1[1], v11 + 4.0, *a1);\n v15 = *((float *)v1 + 6);\n result = v16;\n v13 = v13 - v15;\n if (v15 > (float)(v21 - v15)) {\n *((float *)v1 + 7) = v15 - v13;\n return result;\n }\n ++v1[1];\n v10 = v10 + v15;\n }\n LODWORD(v9) = v9 + 1;\n v12 += 8LL;\n } while (v3 > (float)(int)v9);\n }\n return result;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "void Item_TextScroll_Paint(type1 *var1) {\n float var2, var3, var4, var5, var6;\n int var7;\n type2 *var8 = (type2 *)var1->field1;\n var5 = var8->field2;\n var2 = var1->field3.field4.field5 + var1->field3.field4.field6 - 16.0 - 1;\n var3 = var1->field3.field4.field7 + 1;\n var9->field8(var2, var3, 16.0, 16.0, var9->field9.field10);\n var3 += 16.0 - 1;\n var8->field11 = var8->field12;\n var4 = var1->field3.field4.field13 - (16.0 * 2);\n var9->field8(var2, var3, 16.0, var4 + 1, var9->field9.field14);\n var3 += var4 - 1;\n var9->field8(var2, var3, 16.0, 16.0, var9->field9.field15);\n var6 = Item_TextScroll_ThumbDrawPosition(var1);\n if (var6 > var3 - 16.0 - 1) {\n var6 = var3 - 16.0 - 1;\n }\n var9->field8(var2, var6, 16.0, 16.0, var9->field9.field16);\n var4 = var1->field3.field4.field13 - 2;\n var2 = var1->field3.field4.field5 + 1;\n var3 = var1->field3.field4.field7 + 1;\n for (var7 = var8->field12; var7 < var5; var7++) {\n const char *var10;\n var10 = var8->field17[var7];\n if (!var10) {\n continue;\n }\n var9->field18(var2 + 4, var3, var1->field19, var1->field3.field20, var10, 0,\n 0, var1->field21, var1->field22);\n var4 -= var8->field23;\n if (var4 < var8->field23) {\n var8->field24 = var8->field23 - var4;\n break;\n }\n var8->field11++;\n var3 += var8->field23;\n }\n}", "style": "rule"}, "extra_info": {"index": 86915, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_14__ TYPE_6__ ;\ntypedef struct TYPE_13__ TYPE_5__ ;\ntypedef struct TYPE_12__ TYPE_4__ ;\ntypedef struct TYPE_11__ TYPE_3__ ;\ntypedef struct TYPE_10__ TYPE_2__ ;\ntypedef struct TYPE_9__ TYPE_1__ ;\n\n/* Type definitions */\nstruct TYPE_12__ {float field2; int field11; int field12; char** field17; float field23; float field24; } ;\ntypedef TYPE_4__ type2 ;\nstruct TYPE_10__ {double field5; double field6; int field7; double field13; } ;\nstruct TYPE_11__ {int /*<<< orphan*/ field20; TYPE_2__ field4; } ;\nstruct TYPE_13__ {int /*<<< orphan*/ field22; int /*<<< orphan*/ field21; TYPE_3__ field3; int /*<<< orphan*/ field19; scalar_t__ field1; } ;\ntypedef TYPE_5__ type1 ;\nstruct TYPE_9__ {int /*<<< orphan*/ field16; int /*<<< orphan*/ field15; int /*<<< orphan*/ field14; int /*<<< orphan*/ field10; } ;\nstruct TYPE_14__ {int /*<<< orphan*/ (* field18 ) (float,float,int /*<<< orphan*/ ,int /*<<< orphan*/ ,char const*,int /*<<< orphan*/ ,int /*<<< orphan*/ ,int /*<<< orphan*/ ,int /*<<< orphan*/ ) ;TYPE_1__ field9; int /*<<< orphan*/ (* field8 ) (float,float,double,double,int /*<<< orphan*/ ) ;} ;\n\n/* Variables and functions */\n float Item_TextScroll_ThumbDrawPosition (TYPE_5__*) ; \n int /*<<< orphan*/ stub1 (float,float,double,double,int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ stub2 (float,float,double,float,int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ stub3 (float,float,double,double,int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ stub4 (float,float,double,double,int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ stub5 (float,float,int /*<<< orphan*/ ,int /*<<< orphan*/ ,char const*,int /*<<< orphan*/ ,int /*<<< orphan*/ ,int /*<<< orphan*/ ,int /*<<< orphan*/ ) ; \n TYPE_6__* var9 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long buttons_pressed() {\n int i;\n int j;\n int k;\n int v4;\n v4 = 0;\n for (i = 0; i <= 3; ++i)\n buttonrow_input(*(uint64_t *)(button_matrix + 16LL * i + 8),\n *(unsigned int *)(button_matrix + 16LL * i));\n for (j = 0; j <= 3; ++j) {\n buttonrow_active(*(uint64_t *)(button_matrix + 16LL * j + 8),\n *(unsigned int *)(button_matrix + 16LL * j));\n **(uint32_t **)(button_matrix + 16LL * j + 8) =\n 1 << *(uint32_t *)(button_matrix + 16LL * j);\n for (k = 0; k <= 3; ++k) {\n if (j != k) {\n if (line_active(*(uint64_t *)(button_matrix + 16LL * k + 8),\n *(unsigned int *)(button_matrix + 16LL * k)))\n v4 |= 1 << k << (4 * j);\n }\n }\n buttonrow_input(*(uint64_t *)(button_matrix + 16LL * j + 8),\n *(unsigned int *)(button_matrix + 16LL * j));\n }\n if (v4 == 16388) return 55LL;\n if (v4 <= 16388) {\n if (v4 == 16384) return 56LL;\n if (v4 <= 16384) {\n if (v4 == 8704) return 53LL;\n if (v4 <= 8704) {\n if (v4 == 8194) return 52LL;\n if (v4 <= 8194) {\n if (v4 == 4352) return 50LL;\n if (v4 <= 4352) {\n if (v4 == 4096) return 49LL;\n if (v4 <= 4096) {\n if (v4 == 2176) return 35LL;\n if (v4 <= 2176) {\n if (v4 == 2048) return 48LL;\n if (v4 <= 2048) {\n if (v4 == 512) return 54LL;\n if (v4 <= 512) {\n if (v4 == 272) return 51LL;\n if (v4 <= 272) {\n if (v4 == 136) return 99LL;\n if (v4 <= 136) {\n if (v4 == 68) return 109LL;\n if (v4 <= 68) {\n if (v4 == 64) return 57LL;\n if (v4 <= 64) {\n if (v4 == 16) return 117LL;\n if (v4 <= 16) {\n if (v4 == 2) return 100LL;\n if (v4 == 8) return 42LL;\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n return 0LL;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "static unsigned char func1(void) {\n int var1, var2;\n uint32_t var3 = 0;\n for (var1 = 0; var1 < 4; var1++) {\n buttonrow_input(var4[var1].field1, var4[var1].field2);\n }\n for (var1 = 0; var1 < 4; var1++) {\n buttonrow_active(var4[var1].field1, var4[var1].field2);\n ((type1*)var4[var1].field1)->field3 = 1 << var4[var1].field2;\n for (var2 = 0; var2 < 4; var2++) {\n if (var1 == var2) continue;\n if (line_active(var4[var2].field1, var4[var2].field2)) {\n var3 |= ((1 << var2) << (var1 * 4));\n }\n }\n buttonrow_input(var4[var1].field1, var4[var1].field2);\n }\n switch (var3) {\n case 0x0088:\n return 'c';\n case 0x0044:\n return 'm';\n case 0x0002:\n return 'd';\n case 0x0010:\n return 'u';\n case 0x1000:\n return '1';\n case 0x1100:\n return '2';\n case 0x0110:\n return '3';\n case 0x2002:\n return '4';\n case 0x2200:\n return '5';\n case 0x0200:\n return '6';\n case 0x4004:\n return '7';\n case 0x4000:\n return '8';\n case 0x0040:\n return '9';\n case 0x0008:\n return '*';\n case 0x0800:\n return '0';\n case 0x0880:\n return '#';\n default:\n return 0;\n }\n}", "style": "rule"}, "extra_info": {"index": 78231, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_4__ TYPE_2__ ;\ntypedef struct TYPE_3__ TYPE_1__ ;\n\n/* Type definitions */\ntypedef int uint32_t ;\nstruct TYPE_3__ {int field3; } ;\ntypedef TYPE_1__ type1 ;\nstruct TYPE_4__ {int field2; scalar_t__ field1; } ;\n\n/* Variables and functions */\n int /*<<< orphan*/ buttonrow_active (scalar_t__,int) ; \n int /*<<< orphan*/ buttonrow_input (scalar_t__,int) ; \n scalar_t__ line_active (scalar_t__,int) ; \n TYPE_2__* var4 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nunsigned long long libevent_accept(int a1, short a2, long long a3) {\n long long v3;\n socklen_t addr_len;\n struct sockaddr s;\n unsigned long long v8;\n v8 = __readfsqword(40u);\n memset(&s, 0, 4uLL);\n addr_len = 4;\n *(uint32_t *)&s.sa_data[2] = accept(a1, &s, &addr_len);\n if (*(int *)&s.sa_data[2] < 0) goto LABEL_5;\n *(uint64_t *)&s.sa_data[6] = calloc(1uLL, 4uLL);\n if (!*(uint64_t *)&s.sa_data[6]) {\n close(*(int *)&s.sa_data[2]);\n LABEL_5:\n warn(\"accept() failed\");\n return v8 - __readfsqword(40u);\n }\n event_set(*(uint64_t *)&s.sa_data[6], *(unsigned int *)&s.sa_data[2],\n EV_PERSIST | (unsigned int)EV_READ,\n (unsigned int)libevent_readwrite, *(uint64_t *)&s.sa_data[6], v3,\n a3, a2);\n event_add(*(uint64_t *)&s.sa_data[6], 0LL);\n return v8 - __readfsqword(40u);\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "static void func1(int var1, short var2, void *var3) {\n struct type1 *var4;\n type2 var5;\n struct type3 var6;\n int var7;\n memset(&var6, 0, sizeof(var6));\n var5 = sizeof(var6);\n var7 = accept(var1, (struct type4 *)&var6, &var5);\n if (var7 < 0) goto err;\n var4 = calloc(1, sizeof(*var4));\n if (var4 == NULL) goto err1;\n event_set(&var4->field1, var7, var8 | var9, var10, var4);\n event_add(&var4->field1, NULL);\n return;\nerr1:\n close(var7);\nerr:\n warn(\"accept() failed\");\n}", "style": "rule"}, "extra_info": {"index": 24447, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\ntypedef int /*<<< orphan*/ var6 ;\ntypedef int type2 ;\nstruct type4 {int dummy; } ;\nstruct type3 {int dummy; } ;\nstruct type1 {int /*<<< orphan*/ field1; } ;\n\n/* Variables and functions */\n int accept (int,struct type4*,int*) ; \n struct type1* calloc (int,int) ; \n int /*<<< orphan*/ close (int) ; \n int /*<<< orphan*/ event_add (int /*<<< orphan*/ *,int /*<<< orphan*/ *) ; \n int /*<<< orphan*/ event_set (int /*<<< orphan*/ *,int,int,int /*<<< orphan*/ ,struct type1*) ; \n int /*<<< orphan*/ memset (struct type3*,int /*<<< orphan*/ ,int) ; \n int /*<<< orphan*/ var10 ; \n int var8 ; \n int var9 ; \n int /*<<< orphan*/ warn (char*) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nunsigned long long daemonize(const char **argv) {\n int v2;\n int v3;\n long long v4;\n __pid_t v5;\n unsigned int v6;\n const char *v7;\n int v8;\n __pid_t v9;\n bool v10;\n const char *v11;\n __pid_t v12;\n __pid_t v14;\n __pid_t v15;\n int v16;\n int v18;\n int v19;\n time_t timer;\n uint8_t v21[4];\n long long v22;\n long long v23;\n char s[24];\n unsigned long long v25;\n v25 = __readfsqword(40u);\n if (!*(&args + 3)) {\n if (!*(&args + 2)) goto LABEL_3;\n goto LABEL_34;\n }\n if (getppid() == 1) return v25 - __readfsqword(40u);\n v14 = fork();\n if (v14 < 0) exit(1);\n if (v14) exit(0);\n setsid();\n v15 = fork();\n if (v15 < 0) exit(1);\n if (v15) exit(0);\n v16 = getdtablesize();\n if (v16 >= 0) {\n do close(v16);\n while (v16-- != 0);\n }\n v18 = open(\"/dev/null\", O_RDWR);\n v19 = v18;\n if (v18 < 0) exit(1);\n dup(v18);\n dup(v19);\n if (*(&args + 2))\n LABEL_34:\n chdir((const char *)*((unsigned int *)&args + 3));\nLABEL_3:\n v2 = open((const char *)*((int *)&args + 2), O_CREAT | O_RDWR, 416LL);\n v3 = v2;\n if (v2 < 0) {\n perror(\"lock: open\");\n exit(1);\n }\n LODWORD(v4) = lockf(v2, F_TLOCK, 0LL);\n if (v4 < 0) {\n perror(\"lock: lockf\");\n printf(\"Aquila is already running.\\n\");\n exit(0);\n }\n v5 = getpid();\n snprintf(s, 16uLL, \"%d\\n\", v5);\n v6 = strlen(s);\n write(v3, s, v6);\n umask(23u);\n if (args) {\n v7 = *argv;\n if (!**argv) v7 = \"/proc/self/exe\";\n stat(v7, (struct stat *)&v22);\n sigemptyset((sigset_t *)((char *)&timer + 4));\n sigaddset((sigset_t *)((char *)&timer + 4), SIGCHLD);\n sigprocmask(SIG_SETMASK, (const sigset_t *)((char *)&timer + 4),\n (sigset_t *)v21);\n time(&timer);\n LABEL_9:\n v8 = timer;\n v9 = fork();\n v10 = v9 == 0;\n if (v9 < 0)\n LABEL_18:\n exit(1);\n while (!v10) {\n wait(0LL);\n time(&timer);\n if ((int)timer - v8 <= 2) sleep(3 - (timer - v8));\n if (**argv) {\n stat(*argv, (struct stat *)&v23);\n if (v23 == v22) goto LABEL_9;\n } else {\n stat(\"/proc/self/exe\", (struct stat *)&v23);\n if (v22 == v23) goto LABEL_9;\n }\n v11 = *argv;\n if (!**argv) v11 = \"/proc/self/exe\";\n execvp(v11, (char *const *)argv);\n v8 = timer;\n v12 = fork();\n v10 = v12 == 0;\n if (v12 < 0) goto LABEL_18;\n }\n sigprocmask(SIG_SETMASK, (const sigset_t *)v21, 0LL);\n }\n return v25 - __readfsqword(40u);\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "void daemonize(char **var1) {\n int var2, var3;\n unsigned char var4[16];\n if (var5.field1) {\n if (getppid() == 1) return;\n var2 = fork();\n if (var2 < 0) exit(1);\n if (var2 > 0) exit(0);\n setsid();\n var2 = fork();\n if (var2 < 0) exit(1);\n if (var2 > 0) exit(0);\n for (var2 = getdtablesize(); var2 >= 0; --var2) close(var2);\n var2 = open(\"/dev/null\", var6);\n if (var2 < 0) exit(1);\n dup(var2);\n dup(var2);\n }\n if (var5.field2) chdir(var5.field3);\n var3 = open(var5.field4, var6 | var7, 0640);\n if (var3 < 0) {\n perror(\"lock: open\");\n exit(1);\n }\n if (lockf(var3, var8, 0) < 0) {\n perror(\"lock: lockf\");\n printf(\n \"Aquila\"\n \" is already running.\\n\");\n exit(0);\n }\n# 221 \"/scratch/repos/new/home/jordi_armengol_estape/c-scraper/outputs/2022-01-22/02-19-57/repos/fleetcommand/aquila/refs/heads/master/src/main.c\"\n snprintf(var4, 16, \"%d\\n\", getpid());\n write(var3, var4, strlen(var4));\n umask(027);\n if (var5.field5) {\n type1 var9, var10;\n type2 var11, var12;\n struct type3 var13, var14;\n stat(*var1[0] ? var1[0] : \"/proc/self/exe\", &var13);\n sigemptyset(&var11);\n sigaddset(&var11, var15);\n sigprocmask(var16, &var11, &var12);\n time(&var10);\n do {\n var9 = var10;\n var2 = fork();\n if (var2 < 0) exit(1);\n if (var2 == 0) break;\n wait(NULL);\n time(&var10);\n if ((var10 - var9) < 3) sleep(3 - (var10 - var9));\n stat(*var1[0] ? var1[0] : \"/proc/self/exe\", &var14);\n if (var14.field6 != var13.field6)\n execvp(*var1[0] ? var1[0] : \"/proc/self/exe\", var1);\n } while (1);\n sigprocmask(var16, &var12, NULL);\n }\n}", "style": "rule"}, "extra_info": {"index": 85030, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_2__ TYPE_1__ ;\n\n/* Type definitions */\ntypedef int /*<<< orphan*/ type2 ;\ntypedef int type1 ;\nstruct type3 {scalar_t__ field6; } ;\nstruct TYPE_2__ {scalar_t__ field5; int /*<<< orphan*/ field4; int /*<<< orphan*/ field3; scalar_t__ field2; scalar_t__ field1; } ;\n\n/* Variables and functions */\n int /*<<< orphan*/ chdir (int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ close (int) ; \n int /*<<< orphan*/ dup (int) ; \n int /*<<< orphan*/ execvp (char*,char**) ; \n int /*<<< orphan*/ exit (int) ; \n int fork () ; \n int getdtablesize () ; \n int getpid () ; \n int getppid () ; \n scalar_t__ lockf (int,int /*<<< orphan*/ ,int /*<<< orphan*/ ) ; \n int open (char*,int,...) ; \n int /*<<< orphan*/ perror (char*) ; \n int /*<<< orphan*/ printf (char*) ; \n int /*<<< orphan*/ setsid () ; \n int /*<<< orphan*/ sigaddset (int /*<<< orphan*/ *,int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ sigemptyset (int /*<<< orphan*/ *) ; \n int /*<<< orphan*/ sigprocmask (int /*<<< orphan*/ ,int /*<<< orphan*/ *,int /*<<< orphan*/ *) ; \n int /*<<< orphan*/ sleep (int) ; \n int /*<<< orphan*/ snprintf (unsigned char*,int,char*,int) ; \n int /*<<< orphan*/ stat (char*,struct type3*) ; \n int /*<<< orphan*/ strlen (unsigned char*) ; \n int /*<<< orphan*/ time (int*) ; \n int /*<<< orphan*/ umask (int) ; \n int /*<<< orphan*/ var15 ; \n int /*<<< orphan*/ var16 ; \n TYPE_1__ var5 ; \n int var6 ; \n int var7 ; \n int /*<<< orphan*/ var8 ; \n int /*<<< orphan*/ wait (int /*<<< orphan*/ *) ; \n int /*<<< orphan*/ write (int,unsigned char*,int /*<<< orphan*/ ) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nunsigned long long retrieve_status(long long a1, long long a2, long long a3) {\n long long result_buffer;\n int v4;\n long long v5;\n unsigned int v6;\n long long v7;\n long long v8;\n uint64_t *target;\n long long v10;\n char *v11;\n long long v12;\n void (*v13)(uint64_t, uint64_t, uint64_t, long long, long long);\n void (***v15)(uint64_t, uint64_t, uint64_t, long long, long long);\n int num_targets;\n long long v17;\n unsigned int v19;\n unsigned int v20;\n long long v21;\n unsigned long long v22;\n v22 = __readfsqword(40u);\n result_buffer = get_result_buffer(a2, a3, &v21);\n v4 = STATUSTYPE_TABLE;\n if ((DM_STATUS_TABLE_FLAG & *(uint32_t *)a2) == 0) v4 = STATUSTYPE_INFO;\n v20 = v4;\n num_targets = dm_table_get_num_targets(a1);\n if (num_targets) {\n v19 = 0;\n v5 = result_buffer;\n v6 = 0;\n v17 = 0LL;\n while (1) {\n target = (uint64_t *)dm_table_get_target(a1, v6);\n if ((unsigned long long)(v21 + result_buffer - v5) <= 24) break;\n v10 = target[1];\n v11 = (char *)*(unsigned int *)(v5 + 4);\n *(uint64_t *)(v5 + 16) = 0LL;\n *(uint64_t *)(v5 + 8) = v10;\n v15 = (void (***)(uint64_t, uint64_t, uint64_t, long long,\n long long))target;\n strncpy(v11, (const char *)*(unsigned int *)(*target + 8LL), 4uLL);\n v12 = v21 + result_buffer - (v5 + 24);\n if (!v12) break;\n v13 = **v15;\n if (v13) {\n if ((DM_NOFLUSH_FLAG & *(uint32_t *)a2) != 0)\n v19 |= DM_STATUS_NOFLUSH_FLAG;\n v13(v15, v20, v19, v5 + 24, v12);\n } else {\n *(uint8_t *)(v5 + 24) = 0;\n }\n v7 = (int)(strlen((const char *)(v5 + 24)) + 1);\n if (v12 == v7) break;\n ++v6;\n v17 = *(int *)(a2 + 4) + v5 + 24 + v7 - result_buffer;\n v8 = align_ptr();\n *(uint32_t *)v5 = v8 - result_buffer;\n if (num_targets == v6) goto LABEL_16;\n v5 = v8;\n }\n *(uint32_t *)a2 |= DM_BUFFER_FULL_FLAG;\n LABEL_16:\n if (v17) *(uint64_t *)(a2 + 8) = v17;\n }\n *(uint32_t *)(a2 + 16) = num_targets;\n return v22 - __readfsqword(40u);\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "static void retrieve_status(struct type1 *var1, struct type2 *var2,\n size_t var3) {\n unsigned int var4, var5;\n struct type3 *var6;\n char *var7, *var8;\n type4 var9;\n size_t var10, var11, var12 = 0;\n unsigned var13 = 0;\n var8 = var7 = get_result_buffer(var2, var3, &var11);\n if (var2->field1 & var14)\n var9 = var15;\n else\n var9 = var16;\n var5 = dm_table_get_num_targets(var1);\n for (var4 = 0; var4 < var5; var4++) {\n struct type5 *var17 = dm_table_get_target(var1, var4);\n size_t var18;\n var10 = var11 - (var8 - var7);\n if (var10 <= sizeof(struct type3)) {\n var2->field1 |= var19;\n break;\n }\n var6 = (struct type3 *)var8;\n var6->field2 = 0;\n var6->field3 = var17->field4;\n var6->field5 = var17->field6;\n strncpy(var6->field7, var17->field8->field9, sizeof(var6->field7));\n var8 += sizeof(struct type3);\n var10 = var11 - (var8 - var7);\n if (var10 <= 0) {\n var2->field1 |= var19;\n break;\n }\n if (var17->field8->field2) {\n if (var2->field1 & var20) var13 |= var21;\n var17->field8->field2(var17, var9, var13, var8, var10);\n } else\n var8[0] = '\\0';\n var18 = strlen(var8) + 1;\n if (var18 == var10) {\n var2->field1 |= var19;\n break;\n }\n var8 += var18;\n var12 = var2->field10 + (var8 - var7);\n var8 = align_ptr(var8);\n var6->field11 = var8 - var7;\n }\n if (var12) var2->field12 = var12;\n var2->field13 = var5;\n}", "style": "rule"}, "extra_info": {"index": 88336, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_2__ TYPE_1__ ;\n\n/* Type definitions */\ntypedef int /*<<< orphan*/ type4 ;\nstruct type5 {TYPE_1__* field8; int /*<<< orphan*/ field6; int /*<<< orphan*/ field4; } ;\nstruct type3 {int field11; int /*<<< orphan*/ field7; int /*<<< orphan*/ field5; int /*<<< orphan*/ field3; scalar_t__ field2; } ;\nstruct type2 {int field1; int field10; size_t field12; unsigned int field13; } ;\nstruct type1 {int dummy; } ;\nstruct TYPE_2__ {int /*<<< orphan*/ (* field2 ) (struct type5*,int /*<<< orphan*/ ,unsigned int,char*,size_t) ;int /*<<< orphan*/ field9; } ;\n\n/* Variables and functions */\n char* align_ptr (char*) ; \n unsigned int dm_table_get_num_targets (struct type1*) ; \n struct type5* dm_table_get_target (struct type1*,unsigned int) ; \n char* get_result_buffer (struct type2*,size_t,size_t*) ; \n int strlen (char*) ; \n int /*<<< orphan*/ strncpy (int /*<<< orphan*/ ,int /*<<< orphan*/ ,int) ; \n int /*<<< orphan*/ stub1 (struct type5*,int /*<<< orphan*/ ,unsigned int,char*,size_t) ; \n int var14 ; \n int /*<<< orphan*/ var15 ; \n int /*<<< orphan*/ var16 ; \n int var19 ; \n int var20 ; \n unsigned int var21 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long calc_log_lookup() {\n long long result;\n __m128i v1;\n float v2;\n int i;\n unsigned int v4;\n result = log_table_lookup;\n *(uint32_t *)log_table_lookup = 63;\n for (i = 1; i <= 255; ++i) {\n v1 = 0LL;\n *(float *)v1.m128i_i32 = (float)i / 255.0;\n v2 = log10(*(double *)_mm_cvtsi32_si128(_mm_cvtsi128_si32(v1)).m128i_i64) *\n -40.0;\n if (v2 <= 63.0)\n v4 = (int)v2;\n else\n v4 = 63;\n result = v4;\n *(uint32_t *)(4LL * i + log_table_lookup) = v4;\n }\n return result;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "void calc_log_lookup() {\n int var1;\n float var2;\n uint8_t var3;\n var4[0] = 63;\n for (var1 = 1; var1 < 256; ++var1) {\n var2 = -40.0 * log10((float)var1 / 255.0);\n if (var2 > 63.0) {\n var3 = 63;\n } else {\n var3 = (uint8_t)var2;\n }\n var4[var1] = var3;\n }\n}", "style": "rule"}, "extra_info": {"index": 44407, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\ntypedef int uint8_t ;\n\n/* Variables and functions */\n double log10 (float) ; \n int* var4 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long goldbach_number(int a1) {\n int i;\n for (i = 1; i < a1; ++i) {\n if (is_prime((unsigned int)i) && is_prime((unsigned int)(a1 - i)))\n return 1LL;\n }\n return 0LL;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "int goldbach_number(int var1) {\n int var2;\n for (var2 = 1; var2 < var1; ++var2) {\n if (is_prime(var2) && is_prime(var1 - var2)) {\n return 1;\n }\n }\n return 0;\n}", "style": "rule"}, "extra_info": {"index": 89865, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\n\n/* Variables and functions */\n scalar_t__ is_prime (int) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nvoid chunk_free(uint64_t *a1) {\n void *ptr;\n while (a1) {\n ptr = a1;\n a1 = (uint64_t *)*a1;\n free(ptr);\n }\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "void chunk_free(type1* var1) {\n while (var1 != NULL) {\n type1* var2 = var1;\n var1 = var1->field1;\n free(var2);\n }\n}", "style": "rule"}, "extra_info": {"index": 31390, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_4__ TYPE_1__ ;\n\n/* Type definitions */\nstruct TYPE_4__ {struct TYPE_4__* field1; } ;\ntypedef TYPE_1__ type1 ;\n\n/* Variables and functions */\n int /*<<< orphan*/ free (TYPE_1__*) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long draw_box_caption(uint32_t *a1, int a2, uint64_t *a3) {\n unsigned int v3;\n uint8_t *v4;\n uint64_t *v5;\n long long result;\n signed int v8;\n unsigned int v9;\n int v10;\n int v11;\n int v12;\n int v13;\n uint8_t *v14;\n v10 = *a1 + a2;\n v11 = a1[2] - a2;\n v12 = a1[3] - a2;\n v8 = v10;\n v9 = a1[1] + a2;\nLABEL_13:\n v5 = a3++;\n v14 = (uint8_t *)*v5;\n if (*v5) {\n while (1) {\n while (1) {\n v4 = v14++;\n v13 = (char)*v4;\n if (!*v4) goto LABEL_13;\n if (v8 == v10) break;\n LABEL_5:\n putchar((char)v13);\n ++v8;\n if (v13 == 32 && v11 - v8 - 1 <= (int)next_word(v14)) {\n while (v8 < v11) {\n putchar(32);\n ++v8;\n }\n }\n if (v8 >= v11) {\n putchar(32);\n v8 = v10;\n ++v9;\n }\n }\n if (v13 != 32) {\n v3 = v8++;\n cup(v9, v3);\n putchar(32);\n goto LABEL_5;\n }\n }\n }\n while (1) {\n result = v9;\n if ((int)v9 > v12) break;\n if (v8 == v10) cup(v9, (unsigned int)v8);\n putchar(32);\n if (++v8 >= v11) {\n putchar(32);\n v8 = v10;\n ++v9;\n }\n }\n return result;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "void draw_box_caption(type1 *var1, int var2, const char **var3) {\n int var4 = (var1->field1 + var2);\n int var5 = (var1->field2 + var2);\n int var6 = (var1->field3 - var2);\n int var7 = (var1->field4 - var2);\n int var8 = var4;\n int var9 = var5;\n int var10;\n const char *var11;\n while ((var11 = *var3++) != 0) {\n while ((var10 = *var11++) != 0) {\n if (var8 == var4) {\n if (var10 == ' ') continue;\n cup(var9, var8++);\n putchar(' ');\n }\n putchar(var10);\n var8++;\n if ((var10 == ' ') && (next_word(var11) > (var6 - var8 - 2))) {\n while (var8 < var6) {\n putchar(' ');\n var8++;\n }\n }\n if (var8 >= var6) {\n putchar(' ');\n var8 = var4;\n var9++;\n }\n }\n }\n while (var9 <= var7) {\n if (var8 == var4) {\n cup(var9, var8);\n }\n putchar(' ');\n if (++var8 >= var6) {\n putchar(' ');\n var8 = var4;\n var9++;\n }\n }\n}", "style": "rule"}, "extra_info": {"index": 10617, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\ntypedef struct TYPE_3__ TYPE_1__ ;\n\n/* Type definitions */\nstruct TYPE_3__ {int field1; int field2; int field3; int field4; } ;\ntypedef TYPE_1__ type1 ;\n\n/* Variables and functions */\n int /*<<< orphan*/ cup (int,int) ; \n int next_word (char const*) ; \n int /*<<< orphan*/ putchar (char) ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long kmod_elf_strip_vermagic(long long a1) {\n long long v2;\n int v3;\n int i;\n int section;\n uint8_t *v6;\n uint8_t *v7;\n char *s1;\n unsigned int n;\n long long v10;\n unsigned long long v11;\n v11 = __readfsqword(40u);\n section = kmod_elf_get_section(a1, \".modinfo\", &v6, &v3);\n if (section < 0) return (unsigned int)section;\n v7 = v6;\n if (!v6 || !v3) return 0LL;\n while (!*v7 && v3 > 1) {\n ++v7;\n --v3;\n }\n if (v3 <= 1) return 0LL;\n for (i = 0;; ++i) {\n if (i >= v3) return (unsigned int)-ENOENT;\n if (v7[i]) {\n if (i + 1 < v3) {\n s1 = &v7[i];\n n = 9LL;\n if (i + 9LL < (unsigned long long)v3) break;\n }\n }\n LABEL_22:;\n }\n LODWORD(v2) = strncmp(s1, \"vermagic=\", n);\n if (v2) {\n i += strlen(s1);\n goto LABEL_22;\n }\n s1 += n;\n v10 = (long long)&s1[-*(uint64_t *)(a1 + 8)] >> 2;\n if (!*(uint64_t *)a1) {\n *(uint64_t *)a1 = malloc(*(unsigned int *)(a1 + 16));\n if (!*(uint64_t *)a1) return (unsigned int)-errno;\n memcpy(*(void **)a1, *(const void **)(a1 + 8), *(unsigned int *)(a1 + 16));\n *(uint64_t *)(a1 + 8) = *(uint64_t *)a1;\n }\n n = (int)strlen(s1);\n memset((void *)(*(uint64_t *)a1 + 4 * v10), 0, n);\n return 0LL;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "int kmod_elf_strip_vermagic(struct type1 *var1) {\n uint64_t var2, var3;\n const void *var4;\n const char *var5;\n int var6;\n var6 = kmod_elf_get_section(var1, \".modinfo\", &var4, &var3);\n if (var6 < 0) return var6;\n var5 = var4;\n if (var5 == NULL || var3 == 0) return 0;\n while (var5[0] == '\\0' && var3 > 1) {\n var5++;\n var3--;\n }\n if (var3 <= 1) return 0;\n for (var2 = 0; var2 < var3; var2++) {\n const char *var7;\n size_t var8, var9;\n if (var5[var2] == '\\0') continue;\n if (var2 + 1 >= var3) continue;\n var7 = var5 + var2;\n var9 = sizeof(\"vermagic=\") - 1;\n if (var2 + var9 >= var3) continue;\n if (strncmp(var7, \"vermagic=\", var9) != 0) {\n var2 += strlen(var7);\n continue;\n }\n var7 += var9;\n var8 = (const uint8_t *)var7 - var1->field1;\n if (var1->field2 == NULL) {\n var1->field2 = malloc(var1->field3);\n if (var1->field2 == NULL) return -var10;\n memcpy(var1->field2, var1->field1, var1->field3);\n var1->field1 = var1->field2;\n ;\n }\n var9 = strlen(var7);\n ;\n memset(var1->field2 + var8, '\\0', var9);\n return 0;\n };\n return -var11;\n}", "style": "rule"}, "extra_info": {"index": 74285, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\ntypedef int /*<<< orphan*/ uint8_t ;\ntypedef int uint64_t ;\nstruct type1 {int /*<<< orphan*/ const* field2; int /*<<< orphan*/ const* field1; int /*<<< orphan*/ field3; } ;\n\n/* Variables and functions */\n int kmod_elf_get_section (struct type1*,char*,void const**,int*) ; \n int /*<<< orphan*/ const* malloc (int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ memcpy (int /*<<< orphan*/ const*,int /*<<< orphan*/ const*,int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ memset (int /*<<< orphan*/ const*,char,size_t) ; \n int strlen (char const*) ; \n scalar_t__ strncmp (char const*,char*,size_t) ; \n int var10 ; \n int var11 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nvoid *xrealloc(void *a1, unsigned int a2) {\n void *result;\n result = realloc(a1, a2);\n if (!result) {\n fprintf((FILE *)(unsigned int)stderr, \"Error: could not allocate memory\");\n printf(\"Error: could not allocate memory\");\n exit(-1);\n }\n return result;\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "void *xrealloc(void *var1, size_t var2) {\n void *var3 = realloc(var1, var2);\n if (var3 != NULL) {\n return var3;\n } else {\n fprintf(var4, \"Error: could not allocate memory\");\n printf(\"Error: could not allocate memory\");\n exit(-1);\n }\n}", "style": "rule"}, "extra_info": {"index": 91491, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\n\n/* Variables and functions */\n int /*<<< orphan*/ exit (int) ; \n int /*<<< orphan*/ fprintf (int /*<<< orphan*/ ,char*) ; \n int /*<<< orphan*/ printf (char*) ; \n void* realloc (void*,size_t) ; \n int /*<<< orphan*/ var4 ; \n\n"}} +{"data_source": "llm4decompile_exe", "prompt": [{"content": "# This is the assembly code:\nlong long GPIOWrite(int a1, int a2) {\n int fd;\n char s[40];\n unsigned long long v5;\n v5 = __readfsqword(40u);\n snprintf(s, 30uLL, \"/sys/class/gpio/gpio%d/value\", a1);\n fd = open(s, O_WRONLY);\n if (fd == -1) {\n fprintf((FILE *)(unsigned int)stderr,\n \"Failed to open gpio value %s for writing!\\n\", s);\n perror(\"open\");\n return 4294967295LL;\n } else if ((unsigned int)write(fd, &s_values_str_0[a2 != 0], 1uLL) == 1) {\n close(fd);\n return 0LL;\n } else {\n fprintf((FILE *)(unsigned int)stderr, \"Failed to write value on %s!\\n\", s);\n perror(\"write\");\n return 4294967295LL;\n }\n}\n# What is the source code?\n", "role": "user"}], "ability": "decompile", "reward_model": {"ground_truth": "int GPIOWrite(int var1, int var2) {\n static const char var3[] = \"01\";\n char var4[30];\n int var5;\n snprintf(var4, 30, \"/sys/class/gpio/gpio%d/value\", var1);\n var5 = open(var4, var6);\n if (-1 == var5) {\n fprintf(var7, \"Failed to open gpio value %s for writing!\\n\", var4);\n perror(\"open\");\n return (-1);\n }\n if (1 != write(var5, &var3[0 == var2 ? 0 : 1], 1)) {\n fprintf(var7, \"Failed to write value on %s!\\n\", var4);\n perror(\"write\");\n return (-1);\n }\n close(var5);\n return (0);\n}", "style": "rule"}, "extra_info": {"index": 1641, "split": "train", "header": "#define NULL ((void*)0)\ntypedef unsigned long size_t; // Customize by platform.\ntypedef long intptr_t; typedef unsigned long uintptr_t;\ntypedef long scalar_t__; // Either arithmetic or pointer type.\n/* By default, we understand bool (as a convenience). */\ntypedef int bool;\n#define false 0\n#define true 1\n\n/* Forward declarations */\n\n/* Type definitions */\n\n/* Variables and functions */\n int /*<<< orphan*/ close (int) ; \n int /*<<< orphan*/ fprintf (int /*<<< orphan*/ ,char*,char*) ; \n int open (char*,int /*<<< orphan*/ ) ; \n int /*<<< orphan*/ perror (char*) ; \n int /*<<< orphan*/ snprintf (char*,int,char*,int) ; \n int /*<<< orphan*/ var6 ; \n int /*<<< orphan*/ var7 ; \n int write (int,char const*,int) ; \n\n"}}